diff --git a/dts/st/n6/stm32n645a0hxq-pinctrl.dtsi b/dts/st/n6/stm32n645a0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..8417596e6
--- /dev/null
+++ b/dts/st/n6/stm32n645a0hxq-pinctrl.dtsi
@@ -0,0 +1,2659 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n645b0hxq-pinctrl.dtsi b/dts/st/n6/stm32n645b0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..9ed74ae7a
--- /dev/null
+++ b/dts/st/n6/stm32n645b0hxq-pinctrl.dtsi
@@ -0,0 +1,3654 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n645i0hxq-pinctrl.dtsi b/dts/st/n6/stm32n645i0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..d622c1c0d
--- /dev/null
+++ b/dts/st/n6/stm32n645i0hxq-pinctrl.dtsi
@@ -0,0 +1,3304 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n645l0hxq-pinctrl.dtsi b/dts/st/n6/stm32n645l0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..f0005c1fe
--- /dev/null
+++ b/dts/st/n6/stm32n645l0hxq-pinctrl.dtsi
@@ -0,0 +1,4080 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n645x0hxq-pinctrl.dtsi b/dts/st/n6/stm32n645x0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..59d63374e
--- /dev/null
+++ b/dts/st/n6/stm32n645x0hxq-pinctrl.dtsi
@@ -0,0 +1,4461 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc0: analog_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc2: analog_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc3: analog_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc4: analog_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc5: analog_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe4: analog_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg7: analog_pg7 {
+				pinmux = <STM32_PINMUX('G', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph3: analog_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph4: analog_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph5: analog_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph6: analog_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph7: analog_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph8: analog_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq0: analog_pq0 {
+				pinmux = <STM32_PINMUX('Q', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq1: analog_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq2: analog_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq3: analog_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq4: analog_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq5: analog_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq6: analog_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq7: analog_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pc0: dcmi_hsync_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc3: dcmi_d2_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc5: dcmi_d2_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe4: dcmi_d5_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pc0: fmc_d14_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pc2: fmc_ne3_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pc3: fmc_d8_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pc4: fmc_ne1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pc5: fmc_nwe_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pc0: i2s1_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc0: i2s3_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc0: i2s6_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pc5: i2s1_ws_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_ph7: i3c2_scl_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_ph8: i3c2_sda_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pc0: ltdc_r4_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pc4: ltdc_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pc4: ltdc_vsync_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pe4: ltdc_g1_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_ph3: ltdc_b4_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_ph4: ltdc_r4_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_ph6: ltdc_b5_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pc0: sdmmc2_d2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pc2: sdmmc2_ck_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pc3: sdmmc2_cmd_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pc4: sdmmc2_d0_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pc5: sdmmc2_d1_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pe4: sdmmc2_d3_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pc4: spi2_miso_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_ph8: spi5_miso_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pe4: spi6_miso_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pc3: spi1_mosi_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc2: spi3_mosi_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_ph7: spi5_mosi_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pc5: spi1_nss_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_ph6: spi5_nss_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pc0: spi1_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc0: spi3_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_ph5: spi5_sck_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc0: spi6_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin_pq1: tim8_bkin_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin2_pq2: tim8_bkin2_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, AF2)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pc4: tim1_ch2n_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pc0: tim2_ch2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pc4: tim12_ch1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1_pq3: tim8_ch1_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1n_pq4: tim8_ch1n_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2_pq5: tim8_ch2_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2n_pq6: tim8_ch2n_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3_pq7: tim8_ch3_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart4_de_pc4: uart4_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pc4: usart3_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pc4: uart4_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pe4: usart6_rts_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pe4: usart10_rx_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pc2: usart2_rx_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pc0: uart7_rx_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pc4: usart1_tx_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph3: uart7_tx_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph4: uart7_tx_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n645z0hxq-pinctrl.dtsi b/dts/st/n6/stm32n645z0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..af554aca6
--- /dev/null
+++ b/dts/st/n6/stm32n645z0hxq-pinctrl.dtsi
@@ -0,0 +1,2241 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n647a0hxq-pinctrl.dtsi b/dts/st/n6/stm32n647a0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..8417596e6
--- /dev/null
+++ b/dts/st/n6/stm32n647a0hxq-pinctrl.dtsi
@@ -0,0 +1,2659 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n647b0hxq-pinctrl.dtsi b/dts/st/n6/stm32n647b0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..9ed74ae7a
--- /dev/null
+++ b/dts/st/n6/stm32n647b0hxq-pinctrl.dtsi
@@ -0,0 +1,3654 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n647i0hxq-pinctrl.dtsi b/dts/st/n6/stm32n647i0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..d622c1c0d
--- /dev/null
+++ b/dts/st/n6/stm32n647i0hxq-pinctrl.dtsi
@@ -0,0 +1,3304 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n647l0hxq-pinctrl.dtsi b/dts/st/n6/stm32n647l0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..f0005c1fe
--- /dev/null
+++ b/dts/st/n6/stm32n647l0hxq-pinctrl.dtsi
@@ -0,0 +1,4080 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n647x0hxq-pinctrl.dtsi b/dts/st/n6/stm32n647x0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..59d63374e
--- /dev/null
+++ b/dts/st/n6/stm32n647x0hxq-pinctrl.dtsi
@@ -0,0 +1,4461 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc0: analog_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc2: analog_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc3: analog_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc4: analog_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc5: analog_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe4: analog_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg7: analog_pg7 {
+				pinmux = <STM32_PINMUX('G', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph3: analog_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph4: analog_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph5: analog_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph6: analog_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph7: analog_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph8: analog_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq0: analog_pq0 {
+				pinmux = <STM32_PINMUX('Q', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq1: analog_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq2: analog_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq3: analog_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq4: analog_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq5: analog_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq6: analog_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq7: analog_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pc0: dcmi_hsync_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc3: dcmi_d2_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc5: dcmi_d2_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe4: dcmi_d5_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pc0: fmc_d14_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pc2: fmc_ne3_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pc3: fmc_d8_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pc4: fmc_ne1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pc5: fmc_nwe_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pc0: i2s1_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc0: i2s3_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc0: i2s6_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pc5: i2s1_ws_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_ph7: i3c2_scl_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_ph8: i3c2_sda_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pc0: ltdc_r4_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pc4: ltdc_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pc4: ltdc_vsync_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pe4: ltdc_g1_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_ph3: ltdc_b4_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_ph4: ltdc_r4_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_ph6: ltdc_b5_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pc0: sdmmc2_d2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pc2: sdmmc2_ck_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pc3: sdmmc2_cmd_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pc4: sdmmc2_d0_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pc5: sdmmc2_d1_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pe4: sdmmc2_d3_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pc4: spi2_miso_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_ph8: spi5_miso_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pe4: spi6_miso_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pc3: spi1_mosi_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc2: spi3_mosi_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_ph7: spi5_mosi_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pc5: spi1_nss_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_ph6: spi5_nss_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pc0: spi1_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc0: spi3_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_ph5: spi5_sck_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc0: spi6_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin_pq1: tim8_bkin_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin2_pq2: tim8_bkin2_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, AF2)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pc4: tim1_ch2n_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pc0: tim2_ch2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pc4: tim12_ch1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1_pq3: tim8_ch1_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1n_pq4: tim8_ch1n_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2_pq5: tim8_ch2_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2n_pq6: tim8_ch2n_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3_pq7: tim8_ch3_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart4_de_pc4: uart4_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pc4: usart3_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pc4: uart4_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pe4: usart6_rts_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pe4: usart10_rx_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pc2: usart2_rx_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pc0: uart7_rx_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pc4: usart1_tx_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph3: uart7_tx_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph4: uart7_tx_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n647z0hxq-pinctrl.dtsi b/dts/st/n6/stm32n647z0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..af554aca6
--- /dev/null
+++ b/dts/st/n6/stm32n647z0hxq-pinctrl.dtsi
@@ -0,0 +1,2241 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n655a0hxq-pinctrl.dtsi b/dts/st/n6/stm32n655a0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..8417596e6
--- /dev/null
+++ b/dts/st/n6/stm32n655a0hxq-pinctrl.dtsi
@@ -0,0 +1,2659 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n655b0hxq-pinctrl.dtsi b/dts/st/n6/stm32n655b0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..9ed74ae7a
--- /dev/null
+++ b/dts/st/n6/stm32n655b0hxq-pinctrl.dtsi
@@ -0,0 +1,3654 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n655i0hxq-pinctrl.dtsi b/dts/st/n6/stm32n655i0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..d622c1c0d
--- /dev/null
+++ b/dts/st/n6/stm32n655i0hxq-pinctrl.dtsi
@@ -0,0 +1,3304 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n655l0hxq-pinctrl.dtsi b/dts/st/n6/stm32n655l0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..f0005c1fe
--- /dev/null
+++ b/dts/st/n6/stm32n655l0hxq-pinctrl.dtsi
@@ -0,0 +1,4080 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n655x0hxq-pinctrl.dtsi b/dts/st/n6/stm32n655x0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..59d63374e
--- /dev/null
+++ b/dts/st/n6/stm32n655x0hxq-pinctrl.dtsi
@@ -0,0 +1,4461 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc0: analog_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc2: analog_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc3: analog_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc4: analog_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc5: analog_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe4: analog_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg7: analog_pg7 {
+				pinmux = <STM32_PINMUX('G', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph3: analog_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph4: analog_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph5: analog_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph6: analog_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph7: analog_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph8: analog_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq0: analog_pq0 {
+				pinmux = <STM32_PINMUX('Q', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq1: analog_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq2: analog_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq3: analog_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq4: analog_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq5: analog_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq6: analog_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq7: analog_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pc0: dcmi_hsync_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc3: dcmi_d2_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc5: dcmi_d2_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe4: dcmi_d5_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pc0: fmc_d14_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pc2: fmc_ne3_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pc3: fmc_d8_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pc4: fmc_ne1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pc5: fmc_nwe_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pc0: i2s1_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc0: i2s3_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc0: i2s6_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pc5: i2s1_ws_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_ph7: i3c2_scl_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_ph8: i3c2_sda_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pc0: ltdc_r4_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pc4: ltdc_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pc4: ltdc_vsync_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pe4: ltdc_g1_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_ph3: ltdc_b4_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_ph4: ltdc_r4_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_ph6: ltdc_b5_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pc0: sdmmc2_d2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pc2: sdmmc2_ck_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pc3: sdmmc2_cmd_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pc4: sdmmc2_d0_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pc5: sdmmc2_d1_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pe4: sdmmc2_d3_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pc4: spi2_miso_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_ph8: spi5_miso_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pe4: spi6_miso_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pc3: spi1_mosi_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc2: spi3_mosi_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_ph7: spi5_mosi_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pc5: spi1_nss_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_ph6: spi5_nss_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pc0: spi1_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc0: spi3_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_ph5: spi5_sck_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc0: spi6_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin_pq1: tim8_bkin_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin2_pq2: tim8_bkin2_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, AF2)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pc4: tim1_ch2n_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pc0: tim2_ch2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pc4: tim12_ch1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1_pq3: tim8_ch1_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1n_pq4: tim8_ch1n_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2_pq5: tim8_ch2_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2n_pq6: tim8_ch2n_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3_pq7: tim8_ch3_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart4_de_pc4: uart4_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pc4: usart3_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pc4: uart4_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pe4: usart6_rts_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pe4: usart10_rx_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pc2: usart2_rx_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pc0: uart7_rx_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pc4: usart1_tx_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph3: uart7_tx_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph4: uart7_tx_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n655z0hxq-pinctrl.dtsi b/dts/st/n6/stm32n655z0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..af554aca6
--- /dev/null
+++ b/dts/st/n6/stm32n655z0hxq-pinctrl.dtsi
@@ -0,0 +1,2241 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n657a0hxq-pinctrl.dtsi b/dts/st/n6/stm32n657a0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..8417596e6
--- /dev/null
+++ b/dts/st/n6/stm32n657a0hxq-pinctrl.dtsi
@@ -0,0 +1,2659 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n657b0hxq-pinctrl.dtsi b/dts/st/n6/stm32n657b0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..9ed74ae7a
--- /dev/null
+++ b/dts/st/n6/stm32n657b0hxq-pinctrl.dtsi
@@ -0,0 +1,3654 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n657i0hxq-pinctrl.dtsi b/dts/st/n6/stm32n657i0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..d622c1c0d
--- /dev/null
+++ b/dts/st/n6/stm32n657i0hxq-pinctrl.dtsi
@@ -0,0 +1,3304 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n657l0hxq-pinctrl.dtsi b/dts/st/n6/stm32n657l0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..f0005c1fe
--- /dev/null
+++ b/dts/st/n6/stm32n657l0hxq-pinctrl.dtsi
@@ -0,0 +1,4080 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n657x0hxq-pinctrl.dtsi b/dts/st/n6/stm32n657x0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..59d63374e
--- /dev/null
+++ b/dts/st/n6/stm32n657x0hxq-pinctrl.dtsi
@@ -0,0 +1,4461 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp15_pf6: adc1_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn3_pg15: adc1_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp7_pg15: adc1_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp15_pf6: adc2_inp15_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn3_pg15: adc2_inn3_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp7_pg15: adc2_inp7_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa3: analog_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa4: analog_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa7: analog_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb1: analog_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb2: analog_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb3: analog_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb8: analog_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb9: analog_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb13: analog_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb14: analog_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb15: analog_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc0: analog_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc1: analog_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc2: analog_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc3: analog_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc4: analog_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc5: analog_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc6: analog_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc7: analog_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd0: analog_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd2: analog_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd3: analog_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd4: analog_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd5: analog_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd6: analog_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd7: analog_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd9: analog_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd10: analog_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd11: analog_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd12: analog_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd13: analog_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd14: analog_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd15: analog_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe4: analog_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe5: analog_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe6: analog_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe11: analog_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf0: analog_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf1: analog_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf6: analog_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf9: analog_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg0: analog_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg1: analog_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg3: analog_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg4: analog_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg5: analog_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg6: analog_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg7: analog_pg7 {
+				pinmux = <STM32_PINMUX('G', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg8: analog_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg9: analog_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg11: analog_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg12: analog_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg15: analog_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph3: analog_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph4: analog_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph5: analog_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph6: analog_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph7: analog_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph8: analog_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph9: analog_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po0: analog_po0 {
+				pinmux = <STM32_PINMUX('O', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po1: analog_po1 {
+				pinmux = <STM32_PINMUX('O', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po2: analog_po2 {
+				pinmux = <STM32_PINMUX('O', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po3: analog_po3 {
+				pinmux = <STM32_PINMUX('O', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po4: analog_po4 {
+				pinmux = <STM32_PINMUX('O', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_po5: analog_po5 {
+				pinmux = <STM32_PINMUX('O', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp0: analog_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp1: analog_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp2: analog_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp3: analog_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp4: analog_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp5: analog_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp6: analog_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp7: analog_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp8: analog_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp9: analog_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp10: analog_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp11: analog_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp12: analog_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp13: analog_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp14: analog_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pp15: analog_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq0: analog_pq0 {
+				pinmux = <STM32_PINMUX('Q', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq1: analog_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq2: analog_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq3: analog_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq4: analog_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq5: analog_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq6: analog_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pq7: analog_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pa4: dcmi_d3_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb8: dcmi_vsync_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pb9: dcmi_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pc0: dcmi_hsync_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pc1: dcmi_d7_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc3: dcmi_d2_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc5: dcmi_d2_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc6: dcmi_d1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pc7: dcmi_d1_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pd0: dcmi_hsync_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pd5: dcmi_pixclk_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pd7: dcmi_d0_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe4: dcmi_d5_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pe5: dcmi_d5_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pe6: dcmi_d1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pe6: dcmi_vsync_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pf1: dcmi_d7_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pg1: dcmi_pixclk_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pg3: dcmi_hsync_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pg15: dcmi_d4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_ph9: dcmi_d6_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_pd0: fdcan1_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_rx_ph9: fdcan1_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pc1: fdcan1_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pb1: fdcan2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pe5: fdcan2_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pe11: fdcan3_tx_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pa3: fmc_a17_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a13_pa4: fmc_a13_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pb1: fmc_noe_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pb2: fmc_d2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pb3: fmc_a23_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl1_pb3: fmc_nbl1_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pb8: fmc_d1_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pb9: fmc_d3_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pb13: fmc_d5_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d7_pb14: fmc_d7_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pb15: fmc_d0_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pc0: fmc_d14_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pc2: fmc_ne3_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pc3: fmc_d8_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pc4: fmc_ne1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pc5: fmc_nwe_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a6_pd0: fmc_a6_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pd0: fmc_a22_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a0_pd2: fmc_a0_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pd2: fmc_a16_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a10_pd3: fmc_a10_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a11_pd4: fmc_a11_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pd5: fmc_d6_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a1_pd6: fmc_a1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a17_pd6: fmc_a17_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a2_pd7: fmc_a2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pd7: fmc_a18_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdclk_pd9: fmc_sdclk_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a3_pd10: fmc_a3_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pd10: fmc_a19_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pd11: fmc_d8_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a5_pd12: fmc_a5_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pd12: fmc_a21_pd12 {
+				pinmux = <STM32_PINMUX('D', 12, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pd13: fmc_d4_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a9_pd14: fmc_a9_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a8_pd15: fmc_a8_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne1_pe5: fmc_sdne1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke1_pe6: fmc_sdcke1_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnwe_pe11: fmc_sdnwe_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a19_pg1: fmc_a19_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pg8: fmc_a20_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d8_pg9: fmc_d8_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a18_pg12: fmc_a18_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pg15: fmc_clk_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_ph9: fmc_d9_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_po0: fmc_a22_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_po1: fmc_a23_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po2: fmc_a24_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po3: fmc_a25_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_po4: fmc_a24_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl2_po4: fmc_nbl2_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_po5: fmc_a25_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl3_po5: fmc_nbl3_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d16_pp0: fmc_d16_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d17_pp1: fmc_d17_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d18_pp2: fmc_d18_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d19_pp3: fmc_d19_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d20_pp4: fmc_d20_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d21_pp5: fmc_d21_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d22_pp6: fmc_d22_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d23_pp7: fmc_d23_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d24_pp8: fmc_d24_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d25_pp9: fmc_d25_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d26_pp10: fmc_d26_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d27_pp11: fmc_d27_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d28_pp12: fmc_d28_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d29_pp13: fmc_d29_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d30_pp14: fmc_d30_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d31_pp15: fmc_d31_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c1_scl_pe5: i2c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_ph9: i2c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_pd14: i2c2_scl_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c1_sda_pc1: i2c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_pe6: i2c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd4: i2c2_sda_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_pd15: i2c2_sda_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pd11: i2c4_sda_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c1_smba_pb5: i2c1_smba_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c2_smba_pd3: i2c2_smba_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pb9: i2s1_ck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pc0: i2s1_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc0: i2s3_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pb13: i2s6_ck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc0: i2s6_ck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_MCK */
+
+			/omit-if-no-ref/ i2s1_mck_pd10: i2s1_mck_pd10 {
+				pinmux = <STM32_PINMUX('D', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_mck_pc6: i2s2_mck_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_mck_pc7: i2s3_mck_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_mck_pf6: i2s6_mck_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pc5: i2s1_ws_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pc1: i2s2_ws_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pd7: i2s3_ws_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pb15: i2s6_ws_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_pe5: i3c1_scl_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_scl_ph9: i3c1_scl_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_ph7: i3c2_scl_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pc1: i3c1_sda_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF7)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c1_sda_pe6: i3c1_sda_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_ph8: i3c2_sda_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb3: debug_jtdo_swo_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pa7: ltdc_b1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pa7: ltdc_r4_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pb1: ltdc_r1_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pb2: ltdc_b2_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pb13: ltdc_clk_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pb14: ltdc_hsync_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pb15: ltdc_g4_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pc0: ltdc_r4_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pc4: ltdc_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pc4: ltdc_vsync_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pd9: ltdc_r1_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pd13: ltdc_r6_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pd15: ltdc_r2_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pe4: ltdc_g1_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pe11: ltdc_vsync_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pf6: ltdc_de_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pf9: ltdc_hsync_pf9 {
+				pinmux = <STM32_PINMUX('F', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg0: ltdc_r0_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pg0: ltdc_vsync_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pg1: ltdc_g1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg4: ltdc_b0_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg5: ltdc_b1_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pg6: ltdc_b3_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pg8: ltdc_g7_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pg9: ltdc_r7_pg9 {
+				pinmux = <STM32_PINMUX('G', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pg11: ltdc_r6_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pg12: ltdc_g0_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pg15: ltdc_b0_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_ph3: ltdc_b4_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_ph4: ltdc_r4_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_ph6: ltdc_b5_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_po2: ltdc_b7_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g3_po3: ltdc_g3_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_po4: ltdc_b4_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF10)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pp15: ltdc_b5_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SDMMC */
+
+			/omit-if-no-ref/ sdmmc1_cdir_pc1: sdmmc1_cdir_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d5_pc1: sdmmc1_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0dir_pc6: sdmmc1_d0dir_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d6_pc6: sdmmc1_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d123dir_pc7: sdmmc1_d123dir_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d7_pc7: sdmmc1_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pc8: sdmmc1_d0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d1_pc9: sdmmc1_d1_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d2_pc10: sdmmc1_d2_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d3_pc11: sdmmc1_d3_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ck_pc12: sdmmc1_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pd11: sdmmc1_d0_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d0_pe15: sdmmc1_d0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_cmd_ph2: sdmmc1_cmd_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_ckin_ph9: sdmmc1_ckin_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc1_d4_ph9: sdmmc1_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pa0: sdmmc2_cmd_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pb4: sdmmc2_d3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pb8: sdmmc2_d0_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pb9: sdmmc2_d2_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pb13: sdmmc2_d6_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d2_pc0: sdmmc2_d2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d5_pc1: sdmmc2_d5_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pc2: sdmmc2_ck_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_cmd_pc3: sdmmc2_cmd_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d0_pc4: sdmmc2_d0_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pc5: sdmmc2_d1_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d6_pc6: sdmmc2_d6_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pc7: sdmmc2_d7_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_ck_pd2: sdmmc2_ck_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d7_pd5: sdmmc2_d7_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d3_pe4: sdmmc2_d3_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d1_pg8: sdmmc2_d1_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ sdmmc2_d4_ph9: sdmmc2_d4_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF11)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb8: spi1_miso_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pc4: spi2_miso_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd6: spi2_miso_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pd11: spi2_miso_pd11 {
+				pinmux = <STM32_PINMUX('D', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_miso_pp8: spi2_miso_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pd4: spi5_miso_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pg1: spi5_miso_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_ph8: spi5_miso_ph8 {
+				pinmux = <STM32_PINMUX('H', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pe4: spi6_miso_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pa7: spi1_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_pc3: spi1_mosi_pc3 {
+				pinmux = <STM32_PINMUX('C', 3, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd2: spi2_mosi_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pd7: spi2_mosi_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pg8: spi2_mosi_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_pp9: spi2_mosi_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb2: spi3_mosi_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc2: spi3_mosi_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pa4: spi5_mosi_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_ph7: spi5_mosi_ph7 {
+				pinmux = <STM32_PINMUX('H', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pa7: spi6_mosi_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pc5: spi1_nss_pc5 {
+				pinmux = <STM32_PINMUX('C', 5, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pc1: spi2_nss_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pd7: spi3_nss_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pe11: spi4_nss_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pa3: spi5_nss_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_ph6: spi5_nss_ph6 {
+				pinmux = <STM32_PINMUX('H', 6, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pb15: spi6_nss_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pb9: spi1_sck_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pc0: spi1_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc0: spi3_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pg12: spi5_sck_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_ph5: spi5_sck_ph5 {
+				pinmux = <STM32_PINMUX('H', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pb13: spi6_sck_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc0: spi6_sck_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pd4: tim1_bkin2_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pg4: tim1_bkin2_pg4 {
+				pinmux = <STM32_PINMUX('G', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pg6: tim17_bkin_pg6 {
+				pinmux = <STM32_PINMUX('G', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin_pq1: tim8_bkin_pq1 {
+				pinmux = <STM32_PINMUX('Q', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_bkin2_pq2: tim8_bkin2_pq2 {
+				pinmux = <STM32_PINMUX('Q', 2, AF2)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pa7: tim1_ch1n_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pb1: tim1_ch3n_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pb2: tim1_ch1_pb2 {
+				pinmux = <STM32_PINMUX('B', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pb3: tim1_ch4n_pb3 {
+				pinmux = <STM32_PINMUX('B', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pc4: tim1_ch2n_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pc6: tim1_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pd2: tim1_ch3_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pd5: tim1_ch4n_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pd6: tim1_ch1_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pd7: tim1_ch2_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pe11: tim1_ch2_pe11 {
+				pinmux = <STM32_PINMUX('E', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pf6: tim1_ch3_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4n_pg0: tim1_ch4n_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pg8: tim1_ch3n_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pg15: tim1_ch4_pg15 {
+				pinmux = <STM32_PINMUX('G', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pc0: tim2_ch2_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pc4: tim12_ch1_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pf6: tim2_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch1_pg0: tim12_ch1_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim12_ch2_pg8: tim12_ch2_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pa7: tim3_ch2_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pb1: tim3_ch4_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pc6: tim3_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pc7: tim3_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pg1: tim13_ch1_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pa7: tim14_ch1_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pc1: tim4_ch4_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pd13: tim4_ch2_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pe5: tim4_ch1_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch2_pe6: tim4_ch2_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch4_pf0: tim4_ch4_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_pf1: tim4_ch3_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch3_ph9: tim4_ch3_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd2: tim15_ch1n_pd2 {
+				pinmux = <STM32_PINMUX('D', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pd6: tim15_ch2_pd6 {
+				pinmux = <STM32_PINMUX('D', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pd7: tim15_ch1n_pd7 {
+				pinmux = <STM32_PINMUX('D', 7, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pf6: tim15_ch2_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch4_pf6: tim5_ch4_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_pa3: tim16_ch1_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pc7: tim16_ch1n_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pe5: tim16_ch1n_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1n_pg1: tim16_ch1n_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_ch1_ph9: tim16_ch1_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pc1: tim17_ch1_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pe6: tim17_ch1n_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1_pg12: tim17_ch1_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3n_pb13: tim8_ch3n_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4n_pb14: tim8_ch4n_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1_pq3: tim8_ch1_pq3 {
+				pinmux = <STM32_PINMUX('Q', 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch1n_pq4: tim8_ch1n_pq4 {
+				pinmux = <STM32_PINMUX('Q', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2_pq5: tim8_ch2_pq5 {
+				pinmux = <STM32_PINMUX('Q', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch2n_pq6: tim8_ch2n_pq6 {
+				pinmux = <STM32_PINMUX('Q', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch3_pq7: tim8_ch3_pq7 {
+				pinmux = <STM32_PINMUX('Q', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pb1: tim9_ch2_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pc6: tim9_ch1_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pc7: tim9_ch2_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ usart10_cts_pb13: usart10_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pg5: usart2_cts_pg5 {
+				pinmux = <STM32_PINMUX('G', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pg8: uart4_cts_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb13: usart6_cts_pb13 {
+				pinmux = <STM32_PINMUX('B', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pb14: usart6_cts_pb14 {
+				pinmux = <STM32_PINMUX('B', 14, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_cts_pd3: usart6_cts_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_cts_pf1: uart8_cts_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_cts_pd0: uart9_cts_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart4_de_pc4: uart4_de_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pc4: usart3_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pc4: uart4_rts_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pb15: usart6_rts_pb15 {
+				pinmux = <STM32_PINMUX('B', 15, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pd4: usart6_rts_pd4 {
+				pinmux = <STM32_PINMUX('D', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart6_rts_pe4: usart6_rts_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pg1: uart7_rts_pg1 {
+				pinmux = <STM32_PINMUX('G', 1, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart8_rts_pf0: uart8_rts_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart9_rts_pd13: uart9_rts_pd13 {
+				pinmux = <STM32_PINMUX('D', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ usart10_rx_pd3: usart10_rx_pd3 {
+				pinmux = <STM32_PINMUX('D', 3, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pd14: usart10_rx_pd14 {
+				pinmux = <STM32_PINMUX('D', 14, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart10_rx_pe4: usart10_rx_pe4 {
+				pinmux = <STM32_PINMUX('E', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa7: usart1_rx_pa7 {
+				pinmux = <STM32_PINMUX('A', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ lpuart1_rx_pe6: lpuart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pe6: usart1_rx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pg8: usart1_rx_pg8 {
+				pinmux = <STM32_PINMUX('G', 8, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pc2: usart2_rx_pc2 {
+				pinmux = <STM32_PINMUX('C', 2, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart2_rx_pf6: usart2_rx_pf6 {
+				pinmux = <STM32_PINMUX('F', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pd9: usart3_rx_pd9 {
+				pinmux = <STM32_PINMUX('D', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pd0: uart4_rx_pd0 {
+				pinmux = <STM32_PINMUX('D', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_ph9: uart4_rx_ph9 {
+				pinmux = <STM32_PINMUX('H', 9, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pa4: usart6_rx_pa4 {
+				pinmux = <STM32_PINMUX('A', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pb8: usart6_rx_pb8 {
+				pinmux = <STM32_PINMUX('B', 8, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc7: usart6_rx_pc7 {
+				pinmux = <STM32_PINMUX('C', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa3: uart7_rx_pa3 {
+				pinmux = <STM32_PINMUX('A', 3, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pc0: uart7_rx_pc0 {
+				pinmux = <STM32_PINMUX('C', 0, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pg11: uart7_rx_pg11 {
+				pinmux = <STM32_PINMUX('G', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pf1: uart9_rx_pf1 {
+				pinmux = <STM32_PINMUX('F', 1, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart9_rx_pg0: uart9_rx_pg0 {
+				pinmux = <STM32_PINMUX('G', 0, AF7)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ usart10_tx_pb9: usart10_tx_pb9 {
+				pinmux = <STM32_PINMUX('B', 9, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart10_tx_pd15: usart10_tx_pd15 {
+				pinmux = <STM32_PINMUX('D', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pc4: usart1_tx_pc4 {
+				pinmux = <STM32_PINMUX('C', 4, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ lpuart1_tx_pe5: lpuart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pe5: usart1_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pb1: usart2_tx_pb1 {
+				pinmux = <STM32_PINMUX('B', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pd5: usart2_tx_pd5 {
+				pinmux = <STM32_PINMUX('D', 5, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pg3: usart2_tx_pg3 {
+				pinmux = <STM32_PINMUX('G', 3, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc1: uart4_tx_pc1 {
+				pinmux = <STM32_PINMUX('C', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe5: uart5_tx_pe5 {
+				pinmux = <STM32_PINMUX('E', 5, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pe6: uart5_tx_pe6 {
+				pinmux = <STM32_PINMUX('E', 6, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pc6: usart6_tx_pc6 {
+				pinmux = <STM32_PINMUX('C', 6, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pg12: uart7_tx_pg12 {
+				pinmux = <STM32_PINMUX('G', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph3: uart7_tx_ph3 {
+				pinmux = <STM32_PINMUX('H', 3, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_ph4: uart7_tx_ph4 {
+				pinmux = <STM32_PINMUX('H', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf0: uart9_tx_pf0 {
+				pinmux = <STM32_PINMUX('F', 0, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs1_po0: xspim_p1_ncs1_po0 {
+				pinmux = <STM32_PINMUX('O', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_ncs2_po1: xspim_p1_ncs2_po1 {
+				pinmux = <STM32_PINMUX('O', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs0_po2: xspim_p1_dqs0_po2 {
+				pinmux = <STM32_PINMUX('O', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_dqs1_po3: xspim_p1_dqs1_po3 {
+				pinmux = <STM32_PINMUX('O', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_clk_po4: xspim_p1_clk_po4 {
+				pinmux = <STM32_PINMUX('O', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_nclk_po5: xspim_p1_nclk_po5 {
+				pinmux = <STM32_PINMUX('O', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io0_pp0: xspim_p1_io0_pp0 {
+				pinmux = <STM32_PINMUX('P', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io1_pp1: xspim_p1_io1_pp1 {
+				pinmux = <STM32_PINMUX('P', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io2_pp2: xspim_p1_io2_pp2 {
+				pinmux = <STM32_PINMUX('P', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io3_pp3: xspim_p1_io3_pp3 {
+				pinmux = <STM32_PINMUX('P', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io4_pp4: xspim_p1_io4_pp4 {
+				pinmux = <STM32_PINMUX('P', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io5_pp5: xspim_p1_io5_pp5 {
+				pinmux = <STM32_PINMUX('P', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io6_pp6: xspim_p1_io6_pp6 {
+				pinmux = <STM32_PINMUX('P', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io7_pp7: xspim_p1_io7_pp7 {
+				pinmux = <STM32_PINMUX('P', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io8_pp8: xspim_p1_io8_pp8 {
+				pinmux = <STM32_PINMUX('P', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io9_pp9: xspim_p1_io9_pp9 {
+				pinmux = <STM32_PINMUX('P', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io10_pp10: xspim_p1_io10_pp10 {
+				pinmux = <STM32_PINMUX('P', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io11_pp11: xspim_p1_io11_pp11 {
+				pinmux = <STM32_PINMUX('P', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io12_pp12: xspim_p1_io12_pp12 {
+				pinmux = <STM32_PINMUX('P', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io13_pp13: xspim_p1_io13_pp13 {
+				pinmux = <STM32_PINMUX('P', 13, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io14_pp14: xspim_p1_io14_pp14 {
+				pinmux = <STM32_PINMUX('P', 14, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p1_io15_pp15: xspim_p1_io15_pp15 {
+				pinmux = <STM32_PINMUX('P', 15, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/dts/st/n6/stm32n657z0hxq-pinctrl.dtsi b/dts/st/n6/stm32n657z0hxq-pinctrl.dtsi
new file mode 100644
index 000000000..af554aca6
--- /dev/null
+++ b/dts/st/n6/stm32n657z0hxq-pinctrl.dtsi
@@ -0,0 +1,2241 @@
+/*
+ * NOTE: Autogenerated file using genpinctrl.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@56020000 {
+
+			/* ADC_IN / ADC_INN / ADC_INP */
+
+			/omit-if-no-ref/ adc1_inn1_pa0: adc1_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp0_pa0: adc1_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp1_pa1: adc1_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp14_pa2: adc1_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp3_pa6: adc1_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp5_pa8: adc1_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp10_pa9: adc1_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn10_pa10: adc1_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp11_pa10: adc1_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn11_pa11: adc1_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp12_pa11: adc1_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn12_pa12: adc1_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp13_pa12: adc1_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn4_pb10: adc1_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp8_pb10: adc1_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp4_pb11: adc1_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp16_pf3: adc1_inp16_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp18_pf4: adc1_inp18_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn5_pf7: adc1_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp9_pf7: adc1_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp2_pf11: adc1_inp2_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inn2_pf12: adc1_inn2_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc1_inp6_pf12: adc1_inp6_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn1_pa0: adc2_inn1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp0_pa0: adc2_inp0_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp1_pa1: adc2_inp1_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp14_pa2: adc2_inp14_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp18_pa5: adc2_inp18_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp3_pa6: adc2_inp3_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp5_pa8: adc2_inp5_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp10_pa9: adc2_inp10_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn10_pa10: adc2_inn10_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp11_pa10: adc2_inp11_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn11_pa11: adc2_inn11_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp12_pa11: adc2_inp12_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn12_pa12: adc2_inn12_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp13_pa12: adc2_inp13_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn4_pb10: adc2_inn4_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp8_pb10: adc2_inp8_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp4_pb11: adc2_inp4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn5_pf7: adc2_inn5_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp9_pf7: adc2_inp9_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp2_pf13: adc2_inp2_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inn2_pf14: adc2_inn2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ adc2_inp6_pf14: adc2_inp6_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/* Analog */
+
+			/omit-if-no-ref/ analog_pa0: analog_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa1: analog_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa2: analog_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa5: analog_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa6: analog_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa8: analog_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa9: analog_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa10: analog_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa11: analog_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa12: analog_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa13: analog_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa14: analog_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pa15: analog_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb0: analog_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb4: analog_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb5: analog_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb6: analog_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb7: analog_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb10: analog_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb11: analog_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pb12: analog_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc8: analog_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc9: analog_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc10: analog_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc11: analog_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc12: analog_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc13: analog_pc13 {
+				pinmux = <STM32_PINMUX('C', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc14: analog_pc14 {
+				pinmux = <STM32_PINMUX('C', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pc15: analog_pc15 {
+				pinmux = <STM32_PINMUX('C', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd1: analog_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pd8: analog_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe0: analog_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe1: analog_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe2: analog_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe3: analog_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe7: analog_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe8: analog_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe9: analog_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe10: analog_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe12: analog_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe13: analog_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe14: analog_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pe15: analog_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf2: analog_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf3: analog_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf4: analog_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf5: analog_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf7: analog_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf8: analog_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf10: analog_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf11: analog_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf12: analog_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf13: analog_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf14: analog_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pf15: analog_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg2: analog_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg10: analog_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg13: analog_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pg14: analog_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph0: analog_ph0 {
+				pinmux = <STM32_PINMUX('H', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph1: analog_ph1 {
+				pinmux = <STM32_PINMUX('H', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_ph2: analog_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn0: analog_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn1: analog_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn2: analog_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn3: analog_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn4: analog_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn5: analog_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn6: analog_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn7: analog_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn8: analog_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn9: analog_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn10: analog_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn11: analog_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, ANALOG)>;
+			};
+
+			/omit-if-no-ref/ analog_pn12: analog_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, ANALOG)>;
+			};
+
+			/* DCMI */
+
+			/omit-if-no-ref/ dcmi_d0_pa1: dcmi_d0_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_pixclk_pa6: dcmi_pixclk_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d0_pa9: dcmi_d0_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d1_pa10: dcmi_d1_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pb0: dcmi_d4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_vsync_pb4: dcmi_vsync_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pb6: dcmi_d6_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d7_pb7: dcmi_d7_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pc8: dcmi_d2_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pc9: dcmi_d3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pc11: dcmi_d4_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pe0: dcmi_d2_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d4_pe8: dcmi_d4_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d3_pe10: dcmi_d3_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf3: dcmi_hsync_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_hsync_pf4: dcmi_hsync_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pf5: dcmi_d6_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d6_pg2: dcmi_d6_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d2_pg10: dcmi_d2_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ dcmi_d5_pn9: dcmi_d5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF10)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* FDCAN_RX */
+
+			/omit-if-no-ref/ fdcan1_rx_pa11: fdcan1_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb5: fdcan2_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_rx_pb12: fdcan2_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pe12: fdcan3_rx_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_rx_pf3: fdcan3_rx_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF6)>;
+			};
+
+			/* FDCAN_TX */
+
+			/omit-if-no-ref/ fdcan1_tx_pa12: fdcan1_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_pd1: fdcan1_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan1_tx_ph2: fdcan1_tx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan2_tx_pg10: fdcan2_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF6)>;
+			};
+
+			/omit-if-no-ref/ fdcan3_tx_pf2: fdcan3_tx_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF6)>;
+			};
+
+			/* FMC */
+
+			/omit-if-no-ref/ fmc_d7_pa0: fmc_d7_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d6_pa1: fmc_d6_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d5_pa2: fmc_d5_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_noe_pa5: fmc_noe_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d4_pa8: fmc_d4_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d3_pa9: fmc_d3_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d2_pa10: fmc_d2_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d1_pa11: fmc_d1_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d0_pa12: fmc_d0_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pa15: fmc_d15_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb0: fmc_d13_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d13_pb4: fmc_d13_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pb5: fmc_d12_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d14_pb6: fmc_d14_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d15_pb7: fmc_d15_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pb10: fmc_d11_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pb11: fmc_d10_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pb12: fmc_d9_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne4_pc8: fmc_ne4_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_clk_pc10: fmc_clk_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pc12: fmc_nl_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a7_pd1: fmc_a7_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pd1: fmc_a23_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nbl0_pd8: fmc_nbl0_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d9_pe0: fmc_d9_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d10_pe1: fmc_d10_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d11_pe2: fmc_d11_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_d12_pe3: fmc_d12_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a4_pe7: fmc_a4_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a20_pe7: fmc_a20_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a12_pe8: fmc_a12_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a14_pe9: fmc_a14_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a15_pe10: fmc_a15_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdnras_pe12: fmc_sdnras_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdncas_pe13: fmc_sdncas_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pe14: fmc_nwe_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF14)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdne0_pe14: fmc_sdne0_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_sdcke0_pe15: fmc_sdcke0_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwait_pf2: fmc_nwait_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nl_pf3: fmc_nl_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_pf5: fmc_ne3_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nwe_pf8: fmc_nwe_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a21_pg2: fmc_a21_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a16_pg10: fmc_a16_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne1_pg13: fmc_ne1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_nce_pg14: fmc_nce_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF10)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne2_pg14: fmc_ne2_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_ne3_ph2: fmc_ne3_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a25_pn0: fmc_a25_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a24_pn1: fmc_a24_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a23_pn2: fmc_a23_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ fmc_a22_pn3: fmc_a22_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF12)>;
+				bias-pull-up;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2C_SCL */
+
+			/omit-if-no-ref/ i2c2_scl_pb10: i2c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_scl_pa8: i2c3_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pc10: i2c4_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_scl_pe13: i2c4_scl_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SDA */
+
+			/omit-if-no-ref/ i2c2_sda_pb11: i2c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pa9: i2c3_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c3_sda_pc9: i2c3_sda_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pc11: i2c4_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ i2c4_sda_pe14: i2c4_sda_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C_SMBA */
+
+			/omit-if-no-ref/ i2c2_smba_pb12: i2c2_smba_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c3_smba_pc8: i2c3_smba_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ i2c4_smba_pe15: i2c4_smba_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF4)>;
+				bias-pull-up;
+			};
+
+			/* I2S_CK */
+
+			/omit-if-no-ref/ i2s1_ck_pa5: i2s1_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s1_ck_pf7: i2s1_ck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa9: i2s2_ck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pa12: i2s2_ck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pb10: i2s2_ck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pf2: i2s2_ck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s2_ck_pg10: i2s2_ck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s3_ck_pc10: i2s3_ck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pa5: i2s6_ck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i2s6_ck_pc12: i2s6_ck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I2S_WS */
+
+			/omit-if-no-ref/ i2s1_ws_pa15: i2s1_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s1_ws_pf4: i2s1_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pa11: i2s2_ws_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb4: i2s2_ws_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s2_ws_pb12: i2s2_ws_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pa15: i2s3_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s3_ws_pf4: i2s3_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa0: i2s6_ws_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pa15: i2s6_ws_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+			};
+
+			/omit-if-no-ref/ i2s6_ws_pf4: i2s6_ws_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+			};
+
+			/* I3C_SCL */
+
+			/omit-if-no-ref/ i3c1_scl_pa5: i3c1_scl_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pa8: i3c2_scl_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pb10: i3c2_scl_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_scl_pc10: i3c2_scl_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* I3C_SDA */
+
+			/omit-if-no-ref/ i3c1_sda_pa6: i3c1_sda_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF4)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pa9: i3c2_sda_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pb11: i3c2_sda_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ i3c2_sda_pc11: i3c2_sda_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF2)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* JTAG PORT */
+
+			/omit-if-no-ref/ debug_jtms_swdio_pa13: debug_jtms_swdio_pa13 {
+				pinmux = <STM32_PINMUX('A', 13, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtck_swclk_pa14: debug_jtck_swclk_pa14 {
+				pinmux = <STM32_PINMUX('A', 14, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdi_pa15: debug_jtdi_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF0)>;
+			};
+
+			/omit-if-no-ref/ debug_jtdo_swo_pb5: debug_jtdo_swo_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF0)>;
+			};
+
+			/* LTDC */
+
+			/omit-if-no-ref/ ltdc_g3_pa0: ltdc_g3_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g2_pa1: ltdc_g2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa2: ltdc_b7_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_clk_pa5: ltdc_clk_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b7_pa6: ltdc_b7_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF12)>;
+			};
+
+			/omit-if-no-ref/ ltdc_hsync_pa6: ltdc_hsync_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pa8: ltdc_b6_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b5_pa9: ltdc_b5_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pa10: ltdc_b4_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pa11: ltdc_b3_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b2_pa12: ltdc_b2_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r5_pa15: ltdc_r5_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pb4: ltdc_r3_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r2_pb5: ltdc_r2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g7_pb10: ltdc_g7_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g6_pb11: ltdc_g6_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g5_pb12: ltdc_g5_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pc8: ltdc_b0_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b3_pc9: ltdc_b3_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r7_pd8: ltdc_r7_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pf2: ltdc_b1_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r4_pf3: ltdc_r4_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r3_pf4: ltdc_r3_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf5: ltdc_g0_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_vsync_pf7: ltdc_vsync_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r6_pf8: ltdc_r6_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r1_pf10: ltdc_r1_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b0_pf11: ltdc_b0_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g0_pf14: ltdc_g0_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g1_pf15: ltdc_g1_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_r0_pg2: ltdc_r0_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_g4_pg10: ltdc_g4_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_de_pg13: ltdc_de_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b1_pg14: ltdc_b1_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b4_pn10: ltdc_b4_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF14)>;
+			};
+
+			/omit-if-no-ref/ ltdc_b6_pn11: ltdc_b6_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF14)>;
+			};
+
+			/* RCC_MCO */
+
+			/omit-if-no-ref/ rcc_mco_1_pa8: rcc_mco_1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ rcc_mco_2_pc9: rcc_mco_2_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF0)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/* SPI_MISO */
+
+			/omit-if-no-ref/ spi1_miso_pa6: spi1_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi1_miso_pb4: spi1_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pb4: spi3_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_miso_pc11: spi3_miso_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pb6: spi4_miso_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_miso_pe13: spi4_miso_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_miso_pf12: spi5_miso_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pa6: spi6_miso_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_miso_pb4: spi6_miso_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF8)>;
+				bias-pull-down;
+			};
+
+			/* SPI_MOSI */
+
+			/omit-if-no-ref/ spi1_mosi_pb5: spi1_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pb5: spi3_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF7)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi3_mosi_pc12: spi3_mosi_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF6)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pb7: spi4_mosi_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi4_mosi_pe14: spi4_mosi_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf11: spi5_mosi_pf11 {
+				pinmux = <STM32_PINMUX('F', 11, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pf14: spi5_mosi_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi5_mosi_pg2: spi5_mosi_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF5)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pb5: spi6_mosi_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF8)>;
+				bias-pull-down;
+			};
+
+			/omit-if-no-ref/ spi6_mosi_pg14: spi6_mosi_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF5)>;
+				bias-pull-down;
+			};
+
+			/* SPI_NSS */
+
+			/omit-if-no-ref/ spi1_nss_pa15: spi1_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi1_nss_pf4: spi1_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pa11: spi2_nss_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb4: spi2_nss_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi2_nss_pb12: spi2_nss_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pa15: spi3_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi3_nss_pf4: spi3_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF6)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi4_nss_pb0: spi4_nss_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi5_nss_pf13: spi5_nss_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa0: spi6_nss_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF5)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pa15: spi6_nss_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ spi6_nss_pf4: spi6_nss_pf4 {
+				pinmux = <STM32_PINMUX('F', 4, AF8)>;
+				bias-pull-up;
+			};
+
+			/* SPI_SCK */
+
+			/omit-if-no-ref/ spi1_sck_pa5: spi1_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi1_sck_pf7: spi1_sck_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa9: spi2_sck_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pa12: spi2_sck_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pb10: spi2_sck_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pf2: spi2_sck_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi2_sck_pg10: spi2_sck_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi3_sck_pc10: spi3_sck_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF6)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe2: spi4_sck_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi4_sck_pe12: spi4_sck_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pe15: spi5_sck_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi5_sck_pf15: spi5_sck_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pa5: spi6_sck_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF8)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ spi6_sck_pc12: spi6_sck_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF5)>;
+				bias-pull-down;
+				slew-rate = "very-high-speed";
+			};
+
+			/* TIM_BKIN */
+
+			/omit-if-no-ref/ tim1_bkin_pa6: tim1_bkin_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin2_pb7: tim1_bkin2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pb12: tim1_bkin_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pc10: tim1_bkin_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_bkin_pe15: tim1_bkin_pe15 {
+				pinmux = <STM32_PINMUX('E', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pa0: tim15_bkin_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_pe3: tim15_bkin_pe3 {
+				pinmux = <STM32_PINMUX('E', 3, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_bkin_ph2: tim15_bkin_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pb4: tim16_bkin_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim16_bkin_pf10: tim16_bkin_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim17_bkin_pb5: tim17_bkin_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF1)>;
+			};
+
+			/* TIM_CH / TIM_CHN */
+
+			/omit-if-no-ref/ tim10_ch1_pa5: tim10_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim11_ch1_pa8: tim11_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF9)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pa8: tim1_ch1_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2_pa9: tim1_ch2_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pa10: tim1_ch3_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pa11: tim1_ch4_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pb0: tim1_ch4_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pc12: tim1_ch4_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe2: tim1_ch2n_pe2 {
+				pinmux = <STM32_PINMUX('E', 2, AF13)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pe8: tim1_ch1n_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1_pe9: tim1_ch1_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pe10: tim1_ch2n_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pe12: tim1_ch3n_pe12 {
+				pinmux = <STM32_PINMUX('E', 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3_pe13: tim1_ch3_pe13 {
+				pinmux = <STM32_PINMUX('E', 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch4_pe14: tim1_ch4_pe14 {
+				pinmux = <STM32_PINMUX('E', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch3n_pf2: tim1_ch3n_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch2n_pf7: tim1_ch2n_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim1_ch1n_pg10: tim1_ch1n_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa0: tim2_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pa1: tim2_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pa2: tim2_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa5: tim2_ch1_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch1_pa15: tim2_ch1_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch3_pb10: tim2_ch3_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch4_pb11: tim2_ch4_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim2_ch2_pf14: tim2_ch2_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim13_ch1_pa6: tim13_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF10)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pa6: tim3_ch1_pa6 {
+				pinmux = <STM32_PINMUX('A', 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch1_pb4: tim3_ch1_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch2_pb5: tim3_ch2_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pc8: tim3_ch3_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch4_pc9: tim3_ch4_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim3_ch3_pf7: tim3_ch3_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim14_ch1_pg2: tim14_ch1_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ tim4_ch1_pg13: tim4_ch1_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch1_pa0: tim5_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pa1: tim15_ch1n_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch2_pa1: tim5_ch2_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pa2: tim15_ch1_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim5_ch3_pa2: tim5_ch3_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1n_pb0: tim15_ch1n_pb0 {
+				pinmux = <STM32_PINMUX('B', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pb6: tim15_ch1_pb6 {
+				pinmux = <STM32_PINMUX('B', 6, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch2_pb7: tim15_ch2_pb7 {
+				pinmux = <STM32_PINMUX('B', 7, AF7)>;
+			};
+
+			/omit-if-no-ref/ tim15_ch1_pc12: tim15_ch1_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ tim17_ch1n_pg2: tim17_ch1n_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ tim8_ch4_pg14: tim8_ch4_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pa0: tim9_ch1_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch2_pa5: tim9_ch2_pa5 {
+				pinmux = <STM32_PINMUX('A', 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ tim9_ch1_pf7: tim9_ch1_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF3)>;
+			};
+
+			/* UART_CTS / USART_CTS / LPUART_CTS */
+
+			/omit-if-no-ref/ lpuart1_cts_pa11: lpuart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pa11: usart1_cts_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_cts_pf14: usart1_cts_pf14 {
+				pinmux = <STM32_PINMUX('F', 14, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pa0: usart2_cts_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_cts_pf2: usart2_cts_pf2 {
+				pinmux = <STM32_PINMUX('F', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pf5: usart3_cts_pf5 {
+				pinmux = <STM32_PINMUX('F', 5, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_cts_pg10: usart3_cts_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_cts_pf7: uart4_cts_pf7 {
+				pinmux = <STM32_PINMUX('F', 7, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_cts_pc9: uart5_cts_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pe10: uart7_cts_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_cts_pg2: uart7_cts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_DE / USART_DE / LPUART_DE */
+
+			/omit-if-no-ref/ uart4_de_pa15: uart4_de_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				drive-push-pull;
+			};
+
+			/omit-if-no-ref/ uart5_de_pc8: uart5_de_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				drive-push-pull;
+			};
+
+			/* UART_RTS / USART_RTS / LPUART_RTS */
+
+			/omit-if-no-ref/ usart10_rts_pg14: usart10_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF6)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ lpuart1_rts_pa12: lpuart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF3)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pa12: usart1_rts_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart1_rts_pf15: usart1_rts_pf15 {
+				pinmux = <STM32_PINMUX('F', 15, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pa1: usart2_rts_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pf3: usart2_rts_pf3 {
+				pinmux = <STM32_PINMUX('F', 3, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart2_rts_pg14: usart2_rts_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg2: usart3_rts_pg2 {
+				pinmux = <STM32_PINMUX('G', 2, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ usart3_rts_pg13: usart3_rts_pg13 {
+				pinmux = <STM32_PINMUX('G', 13, AF7)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart4_rts_pa15: uart4_rts_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart5_rts_pc8: uart5_rts_pc8 {
+				pinmux = <STM32_PINMUX('C', 8, AF11)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/omit-if-no-ref/ uart7_rts_pe9: uart7_rts_pe9 {
+				pinmux = <STM32_PINMUX('E', 9, AF8)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* UART_RX / USART_RX / LPUART_RX */
+
+			/omit-if-no-ref/ lpuart1_rx_pa10: lpuart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pa10: usart1_rx_pa10 {
+				pinmux = <STM32_PINMUX('A', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart1_rx_pf12: usart1_rx_pf12 {
+				pinmux = <STM32_PINMUX('F', 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pb11: usart3_rx_pb11 {
+				pinmux = <STM32_PINMUX('B', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pc11: usart3_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe0: usart3_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF7)>;
+			};
+
+			/omit-if-no-ref/ usart3_rx_pe10: usart3_rx_pe10 {
+				pinmux = <STM32_PINMUX('E', 10, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa1: uart4_rx_pa1 {
+				pinmux = <STM32_PINMUX('A', 1, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pa11: uart4_rx_pa11 {
+				pinmux = <STM32_PINMUX('A', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart4_rx_pc11: uart4_rx_pc11 {
+				pinmux = <STM32_PINMUX('C', 11, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb5: uart5_rx_pb5 {
+				pinmux = <STM32_PINMUX('B', 5, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_pb12: uart5_rx_pb12 {
+				pinmux = <STM32_PINMUX('B', 12, AF11)>;
+			};
+
+			/omit-if-no-ref/ uart5_rx_ph2: uart5_rx_ph2 {
+				pinmux = <STM32_PINMUX('H', 2, AF11)>;
+			};
+
+			/omit-if-no-ref/ usart6_rx_pc9: usart6_rx_pc9 {
+				pinmux = <STM32_PINMUX('C', 9, AF7)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pa8: uart7_rx_pa8 {
+				pinmux = <STM32_PINMUX('A', 8, AF10)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pe7: uart7_rx_pe7 {
+				pinmux = <STM32_PINMUX('E', 7, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart7_rx_pf10: uart7_rx_pf10 {
+				pinmux = <STM32_PINMUX('F', 10, AF8)>;
+			};
+
+			/omit-if-no-ref/ uart8_rx_pe0: uart8_rx_pe0 {
+				pinmux = <STM32_PINMUX('E', 0, AF8)>;
+			};
+
+			/* UART_TX / USART_TX / LPUART_TX */
+
+			/omit-if-no-ref/ lpuart1_tx_pa9: lpuart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF3)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pa9: usart1_tx_pa9 {
+				pinmux = <STM32_PINMUX('A', 9, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart1_tx_pf13: usart1_tx_pf13 {
+				pinmux = <STM32_PINMUX('F', 13, AF4)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart2_tx_pa2: usart2_tx_pa2 {
+				pinmux = <STM32_PINMUX('A', 2, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pb10: usart3_tx_pb10 {
+				pinmux = <STM32_PINMUX('B', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pc10: usart3_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pd8: usart3_tx_pd8 {
+				pinmux = <STM32_PINMUX('D', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe1: usart3_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart3_tx_pe8: usart3_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa0: uart4_tx_pa0 {
+				pinmux = <STM32_PINMUX('A', 0, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pa12: uart4_tx_pa12 {
+				pinmux = <STM32_PINMUX('A', 12, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pc10: uart4_tx_pc10 {
+				pinmux = <STM32_PINMUX('C', 10, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart4_tx_pd1: uart4_tx_pd1 {
+				pinmux = <STM32_PINMUX('D', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pc12: uart5_tx_pc12 {
+				pinmux = <STM32_PINMUX('C', 12, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart5_tx_pg10: uart5_tx_pg10 {
+				pinmux = <STM32_PINMUX('G', 10, AF11)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ usart6_tx_pg14: usart6_tx_pg14 {
+				pinmux = <STM32_PINMUX('G', 14, AF7)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pa15: uart7_tx_pa15 {
+				pinmux = <STM32_PINMUX('A', 15, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pb4: uart7_tx_pb4 {
+				pinmux = <STM32_PINMUX('B', 4, AF10)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart7_tx_pe8: uart7_tx_pe8 {
+				pinmux = <STM32_PINMUX('E', 8, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart8_tx_pe1: uart8_tx_pe1 {
+				pinmux = <STM32_PINMUX('E', 1, AF8)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart9_tx_pf8: uart9_tx_pf8 {
+				pinmux = <STM32_PINMUX('F', 8, AF7)>;
+				bias-pull-up;
+			};
+
+			/* XSPIM */
+
+			/omit-if-no-ref/ xspim_p2_dqs0_pn0: xspim_p2_dqs0_pn0 {
+				pinmux = <STM32_PINMUX('N', 0, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs1_pn1: xspim_p2_ncs1_pn1 {
+				pinmux = <STM32_PINMUX('N', 1, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io0_pn2: xspim_p2_io0_pn2 {
+				pinmux = <STM32_PINMUX('N', 2, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io1_pn3: xspim_p2_io1_pn3 {
+				pinmux = <STM32_PINMUX('N', 3, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io2_pn4: xspim_p2_io2_pn4 {
+				pinmux = <STM32_PINMUX('N', 4, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io3_pn5: xspim_p2_io3_pn5 {
+				pinmux = <STM32_PINMUX('N', 5, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_clk_pn6: xspim_p2_clk_pn6 {
+				pinmux = <STM32_PINMUX('N', 6, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_nclk_pn7: xspim_p2_nclk_pn7 {
+				pinmux = <STM32_PINMUX('N', 7, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io4_pn8: xspim_p2_io4_pn8 {
+				pinmux = <STM32_PINMUX('N', 8, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io5_pn9: xspim_p2_io5_pn9 {
+				pinmux = <STM32_PINMUX('N', 9, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io6_pn10: xspim_p2_io6_pn10 {
+				pinmux = <STM32_PINMUX('N', 10, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_io7_pn11: xspim_p2_io7_pn11 {
+				pinmux = <STM32_PINMUX('N', 11, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+			/omit-if-no-ref/ xspim_p2_ncs2_pn12: xspim_p2_ncs2_pn12 {
+				pinmux = <STM32_PINMUX('N', 12, AF9)>;
+				slew-rate = "very-high-speed";
+			};
+
+		};
+	};
+};
\ No newline at end of file
diff --git a/scripts/genpinctrl/genpinctrl.py b/scripts/genpinctrl/genpinctrl.py
index 31ff21821..ade7c9d2e 100644
--- a/scripts/genpinctrl/genpinctrl.py
+++ b/scripts/genpinctrl/genpinctrl.py
@@ -66,6 +66,7 @@
     "stm32l4": 0x48000000,
     "stm32l5": 0x42020000,
     "stm32mp1": 0x50002000,
+    "stm32n6": 0x56020000,
     "stm32u0": 0x50000000,
     "stm32u5": 0x42020000,
     "stm32wba": 0x42020000,
diff --git a/scripts/genpinctrl/stm32-pinctrl-config.yaml b/scripts/genpinctrl/stm32-pinctrl-config.yaml
index fe2637dbf..78a411e87 100644
--- a/scripts/genpinctrl/stm32-pinctrl-config.yaml
+++ b/scripts/genpinctrl/stm32-pinctrl-config.yaml
@@ -223,7 +223,7 @@
   slew-rate: very-high-speed
 
 - name: XSPIM
-  match: "^XSPIM(.*)(?:CLK|NCS[0-1]|DQS[0-1]|IO[0-7])$"
+  match: "^XSPIM(.*)(?:CLK|NCS[1-2]|DQS[0-1]|IO\\d+)$"
   slew-rate: very-high-speed
 
 - name: SDMMC
diff --git a/stm32cube/CMakeLists.txt b/stm32cube/CMakeLists.txt
index 432f58eb6..cbfb628da 100644
--- a/stm32cube/CMakeLists.txt
+++ b/stm32cube/CMakeLists.txt
@@ -64,6 +64,7 @@ set(supported_series
   stm32l4x
   stm32l5x
   stm32mp1x
+  stm32n6x
   stm32u0x
   stm32u5x
   stm32wb0x
@@ -78,6 +79,8 @@ if(CONFIG_CPU_CORTEX_M4)
   zephyr_compile_definitions( -DCORE_CM4 )
 elseif(CONFIG_CPU_CORTEX_M7)
   zephyr_compile_definitions( -DCORE_CM7 )
+elseif(CONFIG_CPU_CORTEX_M55)
+  zephyr_compile_definitions( -DCORE_CM55 )
 endif()
 
 # Define the HSE frequency visible to Cube if a value is specified in Zephyr.
diff --git a/stm32cube/common_ll/README.rst b/stm32cube/common_ll/README.rst
index 598bbc252..43b4c0114 100644
--- a/stm32cube/common_ll/README.rst
+++ b/stm32cube/common_ll/README.rst
@@ -27,6 +27,7 @@ stm32l1xx       1.10.4
 stm32l4xx       1.18.1
 stm32l5xx       1.5.1
 stm32mp1xx      1.6.0
+stm32n6xx       1.0.0
 stm32u0xx       1.2.0
 stm32u5xx       1.7.0
 stm32wb0x       1.0.0
diff --git a/stm32cube/common_ll/include/stm32_ll_adc.h b/stm32cube/common_ll/include/stm32_ll_adc.h
index 0a7bf0d36..3a7b0b409 100644
--- a/stm32cube/common_ll/include/stm32_ll_adc.h
+++ b/stm32cube/common_ll/include/stm32_ll_adc.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_adc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_adc.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_adc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_adc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_bus.h b/stm32cube/common_ll/include/stm32_ll_bus.h
index ab48223ee..1fe1cf554 100644
--- a/stm32cube/common_ll/include/stm32_ll_bus.h
+++ b/stm32cube/common_ll/include/stm32_ll_bus.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_bus.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_bus.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_bus.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_bus.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_cacheaxi.h b/stm32cube/common_ll/include/stm32_ll_cacheaxi.h
new file mode 100644
index 000000000..bd4877951
--- /dev/null
+++ b/stm32cube/common_ll/include/stm32_ll_cacheaxi.h
@@ -0,0 +1,9 @@
+/*
+ * NOTE: Autogenerated file using genllheaders.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_cacheaxi.h>
+#endif
diff --git a/stm32cube/common_ll/include/stm32_ll_cortex.h b/stm32cube/common_ll/include/stm32_ll_cortex.h
index e0db93006..68131ec97 100644
--- a/stm32cube/common_ll/include/stm32_ll_cortex.h
+++ b/stm32cube/common_ll/include/stm32_ll_cortex.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_cortex.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_cortex.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_cortex.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_cortex.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_crc.h b/stm32cube/common_ll/include/stm32_ll_crc.h
index c97bf9847..2e759a0ad 100644
--- a/stm32cube/common_ll/include/stm32_ll_crc.h
+++ b/stm32cube/common_ll/include/stm32_ll_crc.h
@@ -36,6 +36,8 @@
 #include <stm32l4xx_ll_crc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
 #include <stm32l5xx_ll_crc.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_crc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_crc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_dlyb.h b/stm32cube/common_ll/include/stm32_ll_dlyb.h
index df66c6793..5269503e1 100644
--- a/stm32cube/common_ll/include/stm32_ll_dlyb.h
+++ b/stm32cube/common_ll/include/stm32_ll_dlyb.h
@@ -8,6 +8,8 @@
 #include <stm32h5xx_ll_dlyb.h>
 #elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
 #include <stm32h7rsxx_ll_dlyb.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_dlyb.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32u5xx_ll_dlyb.h>
 #endif
diff --git a/stm32cube/common_ll/include/stm32_ll_dma.h b/stm32cube/common_ll/include/stm32_ll_dma.h
index 0611d7589..ecfec35c8 100644
--- a/stm32cube/common_ll/include/stm32_ll_dma.h
+++ b/stm32cube/common_ll/include/stm32_ll_dma.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_dma.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_dma.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_dma.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_dma.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_dma2d.h b/stm32cube/common_ll/include/stm32_ll_dma2d.h
index 06caeae2c..277b403e0 100644
--- a/stm32cube/common_ll/include/stm32_ll_dma2d.h
+++ b/stm32cube/common_ll/include/stm32_ll_dma2d.h
@@ -14,6 +14,8 @@
 #include <stm32h7xx_ll_dma2d.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L4X)
 #include <stm32l4xx_ll_dma2d.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_dma2d.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32u5xx_ll_dma2d.h>
 #endif
diff --git a/stm32cube/common_ll/include/stm32_ll_exti.h b/stm32cube/common_ll/include/stm32_ll_exti.h
index 8efcd25ca..fbf0fd416 100644
--- a/stm32cube/common_ll/include/stm32_ll_exti.h
+++ b/stm32cube/common_ll/include/stm32_ll_exti.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_exti.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_exti.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_exti.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_exti.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_fmc.h b/stm32cube/common_ll/include/stm32_ll_fmc.h
index f8ea5dae5..7f4ecb2af 100644
--- a/stm32cube/common_ll/include/stm32_ll_fmc.h
+++ b/stm32cube/common_ll/include/stm32_ll_fmc.h
@@ -24,6 +24,8 @@
 #include <stm32l5xx_ll_fmc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_fmc.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_fmc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32u5xx_ll_fmc.h>
 #endif
diff --git a/stm32cube/common_ll/include/stm32_ll_gpio.h b/stm32cube/common_ll/include/stm32_ll_gpio.h
index d1ad5e4ba..d9cc3da66 100644
--- a/stm32cube/common_ll/include/stm32_ll_gpio.h
+++ b/stm32cube/common_ll/include/stm32_ll_gpio.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_gpio.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_gpio.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_gpio.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_gpio.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_i2c.h b/stm32cube/common_ll/include/stm32_ll_i2c.h
index 3c12db068..74b567a60 100644
--- a/stm32cube/common_ll/include/stm32_ll_i2c.h
+++ b/stm32cube/common_ll/include/stm32_ll_i2c.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_i2c.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_i2c.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_i2c.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_i2c.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_i3c.h b/stm32cube/common_ll/include/stm32_ll_i3c.h
index 04d88fbcd..2c59417bb 100644
--- a/stm32cube/common_ll/include/stm32_ll_i3c.h
+++ b/stm32cube/common_ll/include/stm32_ll_i3c.h
@@ -8,4 +8,6 @@
 #include <stm32h5xx_ll_i3c.h>
 #elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
 #include <stm32h7rsxx_ll_i3c.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_i3c.h>
 #endif
diff --git a/stm32cube/common_ll/include/stm32_ll_icache.h b/stm32cube/common_ll/include/stm32_ll_icache.h
index a86b3505e..b5ad57b56 100644
--- a/stm32cube/common_ll/include/stm32_ll_icache.h
+++ b/stm32cube/common_ll/include/stm32_ll_icache.h
@@ -10,6 +10,8 @@
 #include <stm32h7rsxx_ll_icache.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
 #include <stm32l5xx_ll_icache.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_icache.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32u5xx_ll_icache.h>
 #elif defined(CONFIG_SOC_SERIES_STM32WBAX)
diff --git a/stm32cube/common_ll/include/stm32_ll_iwdg.h b/stm32cube/common_ll/include/stm32_ll_iwdg.h
index 4ab93b5b7..dea2c402e 100644
--- a/stm32cube/common_ll/include/stm32_ll_iwdg.h
+++ b/stm32cube/common_ll/include/stm32_ll_iwdg.h
@@ -36,6 +36,8 @@
 #include <stm32l4xx_ll_iwdg.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
 #include <stm32l5xx_ll_iwdg.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_iwdg.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_iwdg.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_lptim.h b/stm32cube/common_ll/include/stm32_ll_lptim.h
index b5e2e3d49..340c6e435 100644
--- a/stm32cube/common_ll/include/stm32_ll_lptim.h
+++ b/stm32cube/common_ll/include/stm32_ll_lptim.h
@@ -26,6 +26,8 @@
 #include <stm32l5xx_ll_lptim.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_lptim.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_lptim.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_lptim.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_lpuart.h b/stm32cube/common_ll/include/stm32_ll_lpuart.h
index 96f997607..d55efd2c2 100644
--- a/stm32cube/common_ll/include/stm32_ll_lpuart.h
+++ b/stm32cube/common_ll/include/stm32_ll_lpuart.h
@@ -20,6 +20,8 @@
 #include <stm32l4xx_ll_lpuart.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
 #include <stm32l5xx_ll_lpuart.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_lpuart.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_lpuart.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_pka.h b/stm32cube/common_ll/include/stm32_ll_pka.h
index 90740fc01..4688f68cf 100644
--- a/stm32cube/common_ll/include/stm32_ll_pka.h
+++ b/stm32cube/common_ll/include/stm32_ll_pka.h
@@ -12,6 +12,8 @@
 #include <stm32l4xx_ll_pka.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
 #include <stm32l5xx_ll_pka.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_pka.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32u5xx_ll_pka.h>
 #elif defined(CONFIG_SOC_SERIES_STM32WB0X)
diff --git a/stm32cube/common_ll/include/stm32_ll_pwr.h b/stm32cube/common_ll/include/stm32_ll_pwr.h
index fa8f77933..9b8bdfcc9 100644
--- a/stm32cube/common_ll/include/stm32_ll_pwr.h
+++ b/stm32cube/common_ll/include/stm32_ll_pwr.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_pwr.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_pwr.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_pwr.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_pwr.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_rcc.h b/stm32cube/common_ll/include/stm32_ll_rcc.h
index 27e6308e4..2ea2da6df 100644
--- a/stm32cube/common_ll/include/stm32_ll_rcc.h
+++ b/stm32cube/common_ll/include/stm32_ll_rcc.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_rcc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_rcc.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_rcc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_rcc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_rng.h b/stm32cube/common_ll/include/stm32_ll_rng.h
index d1787ab04..e7874f4d5 100644
--- a/stm32cube/common_ll/include/stm32_ll_rng.h
+++ b/stm32cube/common_ll/include/stm32_ll_rng.h
@@ -26,6 +26,8 @@
 #include <stm32l4xx_ll_rng.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
 #include <stm32l5xx_ll_rng.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_rng.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_rng.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_rtc.h b/stm32cube/common_ll/include/stm32_ll_rtc.h
index c633c129d..d0886b6f1 100644
--- a/stm32cube/common_ll/include/stm32_ll_rtc.h
+++ b/stm32cube/common_ll/include/stm32_ll_rtc.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_rtc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_rtc.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_rtc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_rtc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_sdmmc.h b/stm32cube/common_ll/include/stm32_ll_sdmmc.h
index 10247480b..73aea6505 100644
--- a/stm32cube/common_ll/include/stm32_ll_sdmmc.h
+++ b/stm32cube/common_ll/include/stm32_ll_sdmmc.h
@@ -26,6 +26,8 @@
 #include <stm32l5xx_ll_sdmmc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_sdmmc.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_sdmmc.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32u5xx_ll_sdmmc.h>
 #endif
diff --git a/stm32cube/common_ll/include/stm32_ll_spi.h b/stm32cube/common_ll/include/stm32_ll_spi.h
index f678d7ecd..1747d8f2c 100644
--- a/stm32cube/common_ll/include/stm32_ll_spi.h
+++ b/stm32cube/common_ll/include/stm32_ll_spi.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_spi.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_spi.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_spi.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_spi.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_system.h b/stm32cube/common_ll/include/stm32_ll_system.h
index 122ccd876..331a1f7da 100644
--- a/stm32cube/common_ll/include/stm32_ll_system.h
+++ b/stm32cube/common_ll/include/stm32_ll_system.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_system.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_system.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_system.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_system.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_tim.h b/stm32cube/common_ll/include/stm32_ll_tim.h
index a26988192..ac7d1fb57 100644
--- a/stm32cube/common_ll/include/stm32_ll_tim.h
+++ b/stm32cube/common_ll/include/stm32_ll_tim.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_tim.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_tim.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_tim.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_tim.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_ucpd.h b/stm32cube/common_ll/include/stm32_ll_ucpd.h
index c0aeb3d98..36fcdbc93 100644
--- a/stm32cube/common_ll/include/stm32_ll_ucpd.h
+++ b/stm32cube/common_ll/include/stm32_ll_ucpd.h
@@ -14,6 +14,8 @@
 #include <stm32h7rsxx_ll_ucpd.h>
 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
 #include <stm32l5xx_ll_ucpd.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_ucpd.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32u5xx_ll_ucpd.h>
 #endif
diff --git a/stm32cube/common_ll/include/stm32_ll_usart.h b/stm32cube/common_ll/include/stm32_ll_usart.h
index 40f419010..e9a608c54 100644
--- a/stm32cube/common_ll/include/stm32_ll_usart.h
+++ b/stm32cube/common_ll/include/stm32_ll_usart.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_usart.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_usart.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_usart.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_usart.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_utils.h b/stm32cube/common_ll/include/stm32_ll_utils.h
index 699d79798..84530d4b5 100644
--- a/stm32cube/common_ll/include/stm32_ll_utils.h
+++ b/stm32cube/common_ll/include/stm32_ll_utils.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_utils.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_utils.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_utils.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_utils.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/common_ll/include/stm32_ll_venc.h b/stm32cube/common_ll/include/stm32_ll_venc.h
new file mode 100644
index 000000000..80b718472
--- /dev/null
+++ b/stm32cube/common_ll/include/stm32_ll_venc.h
@@ -0,0 +1,9 @@
+/*
+ * NOTE: Autogenerated file using genllheaders.py
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_venc.h>
+#endif
diff --git a/stm32cube/common_ll/include/stm32_ll_wwdg.h b/stm32cube/common_ll/include/stm32_ll_wwdg.h
index 091793da8..bf22db6b8 100644
--- a/stm32cube/common_ll/include/stm32_ll_wwdg.h
+++ b/stm32cube/common_ll/include/stm32_ll_wwdg.h
@@ -38,6 +38,8 @@
 #include <stm32l5xx_ll_wwdg.h>
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 #include <stm32mp1xx_ll_wwdg.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <stm32n6xx_ll_wwdg.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <stm32u0xx_ll_wwdg.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
diff --git a/stm32cube/stm32n6xx/CMakeLists.txt b/stm32cube/stm32n6xx/CMakeLists.txt
new file mode 100644
index 000000000..f1b9dd1d6
--- /dev/null
+++ b/stm32cube/stm32n6xx/CMakeLists.txt
@@ -0,0 +1,112 @@
+# Copyright (c) 2025 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources(soc/system_stm32n6xx_fsbl.c)
+zephyr_library_sources(drivers/src/stm32n6xx_hal.c)
+zephyr_library_sources(drivers/src/stm32n6xx_hal_rcc.c)
+zephyr_library_sources(drivers/src/stm32n6xx_hal_rcc_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ADC drivers/src/stm32n6xx_hal_adc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ADC_EX drivers/src/stm32n6xx_hal_adc_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_BSEC drivers/src/stm32n6xx_hal_bsec.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CACHEAXI drivers/src/stm32n6xx_hal_cacheaxi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CORTEX drivers/src/stm32n6xx_hal_cortex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRC drivers/src/stm32n6xx_hal_crc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRC_EX drivers/src/stm32n6xx_hal_crc_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRYP drivers/src/stm32n6xx_hal_cryp.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_CRYP_EX drivers/src/stm32n6xx_hal_cryp_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DCMI drivers/src/stm32n6xx_hal_dcmi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DCMIPP drivers/src/stm32n6xx_hal_dcmipp.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA drivers/src/stm32n6xx_hal_dma.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA_EX drivers/src/stm32n6xx_hal_dma_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DMA2D drivers/src/stm32n6xx_hal_dma2d.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_DTS drivers/src/stm32n6xx_hal_dts.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ETH drivers/src/stm32n6xx_hal_eth.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ETH_EX drivers/src/stm32n6xx_hal_eth_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_EXTI drivers/src/stm32n6xx_hal_exti.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_FDCAN drivers/src/stm32n6xx_hal_fdcan.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GFXMMU drivers/src/stm32n6xx_hal_gfxmmu.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GFXTIM drivers/src/stm32n6xx_hal_gfxtim.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GPIO drivers/src/stm32n6xx_hal_gpio.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_GPU2D drivers/src/stm32n6xx_hal_gpu2d.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HASH drivers/src/stm32n6xx_hal_hash.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_HCD drivers/src/stm32n6xx_hal_hcd.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C drivers/src/stm32n6xx_hal_i2c.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2C_EX drivers/src/stm32n6xx_hal_i2c_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2S drivers/src/stm32n6xx_hal_i2s.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I2S_EX drivers/src/stm32n6xx_hal_i2s_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_I3C drivers/src/stm32n6xx_hal_i3c.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_ICACHE drivers/src/stm32n6xx_hal_icache.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IRDA drivers/src/stm32n6xx_hal_irda.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_IWDG drivers/src/stm32n6xx_hal_iwdg.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_JPEG drivers/src/stm32n6xx_hal_jpeg.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LPTIM drivers/src/stm32n6xx_hal_lptim.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LTDC drivers/src/stm32n6xx_hal_ltdc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_LTDC_EX drivers/src/stm32n6xx_hal_ltdc_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MCE drivers/src/stm32n6xx_hal_mce.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MDF drivers/src/stm32n6xx_hal_mdf.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MDIOS drivers/src/stm32n6xx_hal_mdios.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MMC drivers/src/stm32n6xx_hal_mmc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_MMC_EX drivers/src/stm32n6xx_hal_mmc_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_NAND drivers/src/stm32n6xx_hal_nand.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_NOR drivers/src/stm32n6xx_hal_nor.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD drivers/src/stm32n6xx_hal_pcd.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PCD_EX drivers/src/stm32n6xx_hal_pcd_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PKA drivers/src/stm32n6xx_hal_pka.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PSSI drivers/src/stm32n6xx_hal_pssi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR drivers/src/stm32n6xx_hal_pwr.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_PWR_EX drivers/src/stm32n6xx_hal_pwr_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RAMCFG drivers/src/stm32n6xx_hal_ramcfg.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RIF drivers/src/stm32n6xx_hal_rif.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RNG drivers/src/stm32n6xx_hal_rng.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RNG_EX drivers/src/stm32n6xx_hal_rng_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC drivers/src/stm32n6xx_hal_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_RTC_EX drivers/src/stm32n6xx_hal_rtc_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI drivers/src/stm32n6xx_hal_sai.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SAI_EX drivers/src/stm32n6xx_hal_sai_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD drivers/src/stm32n6xx_hal_sd.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SD_EX drivers/src/stm32n6xx_hal_sd_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SDIO drivers/src/stm32n6xx_hal_sdio.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SDRAM drivers/src/stm32n6xx_hal_sdram.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD drivers/src/stm32n6xx_hal_smartcard.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMARTCARD_EX drivers/src/stm32n6xx_hal_smartcard_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS drivers/src/stm32n6xx_hal_smbus.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SMBUS_EX drivers/src/stm32n6xx_hal_smbus_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPDIFRX drivers/src/stm32n6xx_hal_spdifrx.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI drivers/src/stm32n6xx_hal_spi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SPI_EX drivers/src/stm32n6xx_hal_spi_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_SRAM drivers/src/stm32n6xx_hal_sram.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM drivers/src/stm32n6xx_hal_tim.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_TIM_EX drivers/src/stm32n6xx_hal_tim_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART drivers/src/stm32n6xx_hal_uart.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_UART_EX drivers/src/stm32n6xx_hal_uart_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_USART drivers/src/stm32n6xx_hal_usart.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_USART_EX drivers/src/stm32n6xx_hal_usart_ex.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_WWDG drivers/src/stm32n6xx_hal_wwdg.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_HAL_XSPI drivers/src/stm32n6xx_hal_xspi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_ADC drivers/src/stm32n6xx_ll_adc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_CRC drivers/src/stm32n6xx_ll_crc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_DLYB drivers/src/stm32n6xx_ll_dlyb.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_DMA drivers/src/stm32n6xx_ll_dma.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_DMA2D drivers/src/stm32n6xx_ll_dma2d.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_EXTI drivers/src/stm32n6xx_ll_exti.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_FMC drivers/src/stm32n6xx_ll_fmc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_GPIO drivers/src/stm32n6xx_ll_gpio.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_I2C drivers/src/stm32n6xx_ll_i2c.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_I3C drivers/src/stm32n6xx_ll_i3c.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_LPTIM drivers/src/stm32n6xx_ll_lptim.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_LPUART drivers/src/stm32n6xx_ll_lpuart.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_PKA drivers/src/stm32n6xx_ll_pka.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_PWR drivers/src/stm32n6xx_ll_pwr.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RCC drivers/src/stm32n6xx_ll_rcc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RNG drivers/src/stm32n6xx_ll_rng.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_RTC drivers/src/stm32n6xx_ll_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_SDMMC drivers/src/stm32n6xx_ll_sdmmc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_SPI drivers/src/stm32n6xx_ll_spi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_TIM drivers/src/stm32n6xx_ll_tim.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_UCPD drivers/src/stm32n6xx_ll_ucpd.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USART drivers/src/stm32n6xx_ll_usart.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_USB drivers/src/stm32n6xx_ll_usb.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_UTILS drivers/src/stm32n6xx_ll_utils.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_LL_VENC drivers/src/stm32n6xx_ll_venc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_STM32_UTIL_I3C drivers/src/stm32n6xx_util_i3c.c)
diff --git a/stm32cube/stm32n6xx/LICENSE.md b/stm32cube/stm32n6xx/LICENSE.md
new file mode 100644
index 000000000..b95507de9
--- /dev/null
+++ b/stm32cube/stm32n6xx/LICENSE.md
@@ -0,0 +1,27 @@
+Copyright 2025 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/stm32cube/stm32n6xx/README b/stm32cube/stm32n6xx/README
new file mode 100644
index 000000000..aed085b0e
--- /dev/null
+++ b/stm32cube/stm32n6xx/README
@@ -0,0 +1,56 @@
+STM32CubeN6
+###########
+
+Origin:
+   ST Microelectronics
+   http://www.st.com/en/embedded-software/stm32cuben6.html
+
+Status:
+   version v1.0.0
+
+Purpose:
+   ST Microelectronics official MCU package for STM32N6 series.
+
+Description:
+   This package is an extract of official STM32CubeN6 package written by ST Microelectronics.
+   It is composed of STM32Cube hardware abstraction layer (HAL) and low layer (LL) plus a set
+   of CMSIS headers files, one for each SoC in STM32N6 series.
+
+Dependencies:
+    None.
+
+URL:
+   https://github.com/STMicroelectronics/STM32CubeN6
+
+Commit:
+   7cc0f778f9ed60d2a00ad9ba7794a3e7feaa3596
+
+Maintained-by:
+   External
+
+License:
+   BSD-3-Clause
+
+License Link:
+   https://opensource.org/licenses/BSD-3-Clause
+
+Patch List:
+   *Changes from official delivery:
+    -dos2unix applied
+    -trailing white spaces removed
+
+   *Provision to enable hal & ll asserts added
+    -Added stm32cube/stm32n6xx/drivers/include/stm32_assert.h
+    -Removed unused stm32cube/stm32n6xx/drivers/include/stm32_assert_template.h
+
+   *Fix to remove PAGESIZE definition which conflicts with POSIX
+    Impacted files:
+     drivers/include/Legacy/stm32_hal_legacy.h
+
+   *Fix FSBL configuration
+    -Remove CMSE_NS_ENTRY modifier, which requires enabling CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS
+     which we don't need right now.
+    Impacted files:
+    -soc/system_stm32n6xx_fsbl.c
+
+   See release_note.html from STM32Cube
diff --git a/stm32cube/stm32n6xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32n6xx/drivers/include/Legacy/stm32_hal_legacy.h
new file mode 100644
index 000000000..16e61cf6f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,4418 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+#if defined(STM32H7) || defined(STM32MP1)
+#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
+#endif /* STM32H7 || STM32MP1 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE               ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM 
+                                                                       input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
+#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
+#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#if defined(STM32H5) || defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 
+                                                                          inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 
+                                                                          inter STM32 series compatibility */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT       DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+    defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+    defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7)
+/* #define PAGESIZE                      FLASH_PAGE_SIZE */
+#endif /* STM32F2 && STM32F4 && STM32F7 &&  STM32H7 */
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0) || defined(STM32C0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST           OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE          OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE      OB_SRAM_RST_NOT_ERASE
+#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL             OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_USER_nBOOT1                OB_USER_NBOOT1
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#endif /* STM32U0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+#if defined(STM32U5)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster                 HAL_SYSCFG_EnableIOAnalogBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster                HAL_SYSCFG_DisableIOAnalogBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection        HAL_SYSCFG_EnableIOAnalogVoltageSelection
+#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection       HAL_SYSCFG_DisableIOAnalogVoltageSelection
+
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC         SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC         SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC         SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC         SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC         SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC         SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC    SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD          SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC     SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP       SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6   SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7   SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8   SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9   SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII   SBS_ETH_MII
+#define SYSCFG_ETH_RMII  SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG  IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE   SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR    SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG      IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC   SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC  SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU              SBS_SAU
+#define SYSCFG_MPU_SEC          SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC   SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK      SBS_CLK
+#define SYSCFG_CLASSB   SBS_CLASSB
+#define SYSCFG_FPU      SBS_FPU
+#define SYSCFG_ALL      SBS_ALL
+
+#define SYSCFG_SEC      SBS_SEC
+#define SYSCFG_NSEC     SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE   __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE  __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK        __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK     __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK        __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK   __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE   __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE  __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS    __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS  __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT    IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG     IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE     IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE    IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING  IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS      IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES  IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES        IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS        IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig   HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig    HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig         HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF                  HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF                 HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect             HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock     HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock  HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes     HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes  HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+         STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+    defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP                          GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO                          GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+
+#if defined(STM32WBA)
+#define GPIO_AF11_RF_ANTSW0    GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW1    GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW2    GPIO_AF11_RF
+#define GPIO_AF11_RF_IO1       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO2       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO3       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO4       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO5       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO6       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO7       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO8       GPIO_AF11_RF
+#define GPIO_AF11_RF_IO9       GPIO_AF11_RF
+#endif /* STM32WBA */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC                      GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12                     GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12                     GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS                     GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX            GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX        GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED        GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED          GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC                 GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC                  GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV                GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV                 GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF                   GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON                    GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
+#define HRTIMInterruptResquests  HRTIMInterruptRequests
+#endif /* STM32F3 || STM32G4 || STM32H7 */
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+#endif /* STM32F3 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+    defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
+/**
+  * @}
+  */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL    0x00000000U
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE               I2S_IT_TXP
+#define I2S_IT_RXNE              I2S_IT_RXP
+
+#define I2S_FLAG_TXE             I2S_FLAG_TXP
+#define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0   RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8   RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
+#define TAMP_SECRETDEVICE_ERASE_NONE        TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM    TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 || STM32H7RS || STM32N6 */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE            TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2           TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK            TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE          TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH   TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM        TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL             TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE     TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA || STM32H7RS ||  STM32N6 */
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE                    SPI_FLAG_TXP
+#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+#define SPI_IT_TXE                      SPI_IT_TXP
+#define SPI_IT_RXNE                     SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                           0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                       0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                   0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                           0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                           0x00100000U  /* Tx FIFO read status: Read (transferring data to 
+                                                                      the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                        0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from 
+                                                                      MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                        0x00300000U  /* Tx FIFO read status: Writing the received TxStatus
+                                                                      or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                    0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE          0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U  /* MAC transmit frame controller: Waiting for Status 
+                                                                   of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U  /* MAC transmit frame controller: Generating and 
+                                                             transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U  /* MAC transmit frame controller: Transferring input 
+                                                                      frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control 
+                                                              de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control 
+                                                              activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status 
+                                                             (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and 
+                                                              status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+#define ETH_TxPacketConfig        ETH_TxPacketConfigTypeDef   /* Transmit Packet Configuration structure definition */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+                                                                        for compatibility with legacy code */
+/**
+  * @}
+  */
+
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
+/**
+  *
+  * @}
+  */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+                                             HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : \
+                                             HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+    defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
+                                                                HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+                                                                HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+    defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+    defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+          STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+    defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+  * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION                PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION                PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION                PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION                PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION                PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION                PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION                PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION                PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION                PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION               PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION               PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION               PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION                 PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION                PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION                PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION                 PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION                PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION                PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION                PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION                PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION                PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION                PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION                PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION                PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION                PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION               PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION               PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION               PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION               PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION                 PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION                 PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION                PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION                PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION                PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION                PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION                PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION                PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION                PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION                PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION                PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION               PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION               PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION               PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION               PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION                 PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION                PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION                PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION                PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION                PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION                PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION                PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION                PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION                PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION                 PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION                PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION               PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION               PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION              PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION             PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION              PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION           PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION                PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION               PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION             PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION             PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION              PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION                  PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION                  PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION                  PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION                  PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION                  PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION                  PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK                PWR_ALL_RAM_RUN_MASK
+#endif
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
+#define HAL_RTCEx_SetBoothardwareKey            HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable              HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable             HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf          HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+    defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+    defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 
+                                                  done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is 
+                                                  done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                           ((WAVE) == DAC_WAVE_NOISE)|| \
+                           ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+                                                                      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+                                                                    } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+                                                                      HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+                                                                    } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+                                                                      HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+                                                                    } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+                                        HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#if defined(STM32C0)
+#define __HAL_RCC_APB1_FORCE_RESET    __HAL_RCC_APB1_GRP1_FORCE_RESET
+#define __HAL_RCC_APB1_RELEASE_RESET  __HAL_RCC_APB1_GRP1_RELEASE_RESET
+#define __HAL_RCC_APB2_FORCE_RESET    __HAL_RCC_APB1_GRP2_FORCE_RESET
+#define __HAL_RCC_APB2_RELEASE_RESET  __HAL_RCC_APB1_GRP2_RELEASE_RESET
+#endif /* STM32C0 */
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define  RCC_SPI4CLKSOURCE_D2PCLK1       RCC_SPI4CLKSOURCE_D2PCLK2
+#define  RCC_SPI5CLKSOURCE_D2PCLK1       RCC_SPI5CLKSOURCE_D2PCLK2
+#define  RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_D2PCLK2
+#define  RCC_SPI45CLKSOURCE_CDPCLK1      RCC_SPI45CLKSOURCE_CDPCLK2
+#define  RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_PCLK2
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR   RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+      defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
+      defined(STM32U0)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL                        RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL                        RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE             __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE            __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED         __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED        __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET            __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET          __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE       __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE      __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE            __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE             __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE            __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG             __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE                 IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE       __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE      __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG       __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE           IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE              RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI               RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI               RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE               RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0               RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1               RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2               RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3               RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE                 RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM               RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE                IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE             IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE          IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE        IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE          IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE               IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE               IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE               IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE               IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE               IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE            __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE           __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE      __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE     __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG            __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG  __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG       __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG      __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE          __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE          __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE     __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE      __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE     __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG  __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE      __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE     __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE     __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE    __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG      __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE      __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE     __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE     __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE    __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG      __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0              RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1              RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2              RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3              RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE                 RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM               RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE             RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI              RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI              RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE              RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0              RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1              RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2              RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3              RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE                 RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM               RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE             RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI              RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI              RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE              RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+    defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+    defined (STM32WBA) || defined (STM32H5) || \
+    defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) ||  defined (STM32U0)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+    defined (STM32H7) || \
+    defined (STM32L0) || defined (STM32L1) || \
+    defined (STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT                   __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE   __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE  __HAL_RCC_RTC_CLK_DISABLE
+#endif   /* STM32H5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16               0x00000000U
+#define USART_OVERSAMPLING_8                USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+#if defined(STM32U5)
+#define USB_OTG_GOTGCTL_BSESVLD                            USB_OTG_GOTGCTL_BSVLD
+#define USB_OTG_GAHBCFG_GINT                               USB_OTG_GAHBCFG_GINTMSK
+#define USB_OTG_GUSBCFG_PHYLPCS                            USB_OTG_GUSBCFG_PHYLPC
+#define USB_OTG_GRSTCTL_HSRST                              USB_OTG_GRSTCTL_PSRST
+#define USB_OTG_GINTSTS_BOUTNAKEFF                         USB_OTG_GINTSTS_GONAKEFF
+#define USB_OTG_GINTSTS_WKUINT                             USB_OTG_GINTSTS_WKUPINT
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM                    USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
+#define USB_OTG_GRXSTSP_EPNUM                              USB_OTG_GRXSTSP_EPNUM_CHNUM
+#define USB_OTG_GLPMCFG_L1ResumeOK                         USB_OTG_GLPMCFG_L1RSMOK
+#define USB_OTG_HPTXFSIZ_PTXFD                             USB_OTG_HPTXFSIZ_PTXFSIZ
+#define USB_OTG_HCCHAR_MC                                  USB_OTG_HCCHAR_MCNT
+#define USB_OTG_HCCHAR_MC_0                                USB_OTG_HCCHAR_MCNT_0
+#define USB_OTG_HCCHAR_MC_1                                USB_OTG_HCCHAR_MCNT_1
+#define USB_OTG_HCINTMSK_AHBERR                            USB_OTG_HCINTMSK_AHBERRM
+#define USB_OTG_HCTSIZ_DOPING                              USB_OTG_HCTSIZ_DOPNG
+#define USB_OTG_DOEPMSK_OPEM                               USB_OTG_DOEPMSK_OUTPKTERRM
+#define USB_OTG_DIEPCTL_SODDFRM                            USB_OTG_DIEPCTL_SD1PID_SODDFRM
+#define USB_OTG_DIEPTSIZ_MULCNT                            USB_OTG_DIEPTSIZ_MCNT
+#define USB_OTG_DOEPCTL_SODDFRM                            USB_OTG_DOEPCTL_SD1PID_SODDFRM
+#define USB_OTG_DOEPCTL_DPID                               USB_OTG_DOEPCTL_DPID_EONUM
+#define USB_OTG_DOEPTSIZ_STUPCNT                           USB_OTG_DOEPTSIZ_RXDPID
+#define USB_OTG_DOEPTSIZ_STUPCNT_0                         USB_OTG_DOEPTSIZ_RXDPID_0
+#define USB_OTG_DOEPTSIZ_STUPCNT_1                         USB_OTG_DOEPTSIZ_RXDPID_1
+#define USB_OTG_PCGCCTL_STOPCLK                            USB_OTG_PCGCCTL_STPPCLK
+#define USB_OTG_PCGCCTL_GATECLK                            USB_OTG_PCGCCTL_GATEHCLK
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1      TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2      TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32_assert.h b/stm32cube/stm32n6xx/drivers/include/stm32_assert.h
new file mode 100644
index 000000000..eca449266
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32_assert.h
@@ -0,0 +1,6 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+#include <stm32n6xx_hal_conf.h>
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal.h
new file mode 100644
index 000000000..2d45c165e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal.h
@@ -0,0 +1,1007 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32N6xx_HAL_H
+#define __STM32N6xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_conf.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Types HAL Exported Types
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+extern __IO uint32_t            uwTick;
+extern uint32_t                 uwTickPrio;
+extern HAL_TickFreqTypeDef      uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/**
+  * @brief STM32N6xx HAL Driver version number
+  */
+#define __STM32N6xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32N6xx_HAL_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
+#define __STM32N6xx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32N6xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32N6xx_HAL_VERSION         ((__STM32N6xx_HAL_VERSION_MAIN << 24U)  \
+                                         |(__STM32N6xx_HAL_VERSION_SUB1 << 16U) \
+                                         |(__STM32N6xx_HAL_VERSION_SUB2 << 8U ) \
+                                         |(__STM32N6xx_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_BootId Boot Id
+  * @{
+  */
+#define SYSCFG_BOOT_0              SYSCFG_BOOTCR_BOOT0_PD  /*!< Boot 0 selection */
+#define SYSCFG_BOOT_1              SYSCFG_BOOTCR_BOOT1_PD  /*!< Boot 1 selection */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_SDMMCId SDMMC Id
+  * @{
+  */
+#define SYSCFG_SDMMC1              SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE  /*!< SDMMC 1 selection */
+#define SYSCFG_SDMMC2              SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE  /*!< SDMMC 2 selection */
+#define SYSCFG_SDMMC_ALL           (SYSCFG_SDMMC1 | SYSCFG_SDMMC2)             /*!< SDMMC 1 & 2 selection */
+/**
+  * @}
+  */
+
+/** @defgroup  SYSCFG_USBId USB Id
+  * @{
+  */
+#define SYSCFG_USB1                SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE    /*!< USB 1 selection */
+#define SYSCFG_USB2                SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE    /*!< USB 2 selection */
+#define SYSCFG_USB_ALL             (SYSCFG_USB1 | SYSCFG_USB2)                 /*!< USB 1 & 2 selection */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_XPUId XPU Id
+  * @{
+  */
+#if defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE)
+#define SYSCFG_NPU_NIC             SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE           /*!< NPU_NIC clock gating disable selection */
+#endif /* defined(SYSCFG_ICNCGCR_NPU_NOCSYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_CG_DISABLE) */
+#define SYSCFG_CPU_NIC             SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE           /*!< CPU_NIC clock gating disable selection */
+#define SYSCFG_CPU_NOC             SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE           /*!< CPU_NOC clock gating disable selection */
+#if defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE)
+#define SYSCFG_CPU_ALL             (SYSCFG_NPU_NIC | SYSCFG_CPU_NIC | SYSCFG_CPU_NOC)
+#else
+#define SYSCFG_CPU_ALL             (SYSCFG_CPU_NIC | SYSCFG_CPU_NOC)
+#endif /* defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE) */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection
+  * @{
+  */
+#define SYSCFG_IO_VDDIO2_CELL       0U         /*!< I/O Compensation cell for VDDIO2 */
+#define SYSCFG_IO_VDDIO3_CELL       1U         /*!< I/O Compensation cell for VDDIO3 */
+#define SYSCFG_IO_VDDIO4_CELL       2U         /*!< I/O Compensation cell for VDDIO4 */
+#define SYSCFG_IO_VDDIO5_CELL       3U         /*!< I/O Compensation cell for VDDIO5 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config
+  * @{
+  */
+#define SYSCFG_IO_CELL_CODE               0UL                       /*!< Code from the cell */
+#define SYSCFG_IO_REGISTER_CODE           1UL                       /*!< Code from the values in the cell code register */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_DELAY_Feedback_Clock       Delay on feedback clock
+  * @{
+  */
+#define SYSCFG_DELAY_FEEDBACK_NONE              0U                                /*!< No delay on the feedback clock */
+#define SYSCFG_DELAY_FEEDBACK_HALF_CYCLE        SYSCFG_FMC_RETIMECR_SDFBCLK_180   /*!< Half a cycle delay on the feedback clock */
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+  * @{
+  */
+#define SYSCFG_IT_FPU_IOC              SYSCFG_CM55CR_FPU_IT_EN_0  /*!< Floating Point Unit Invalid operation Interrupt */
+#define SYSCFG_IT_FPU_DZC              SYSCFG_CM55CR_FPU_IT_EN_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC              SYSCFG_CM55CR_FPU_IT_EN_2  /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC              SYSCFG_CM55CR_FPU_IT_EN_3  /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC              SYSCFG_CM55CR_FPU_IT_EN_4  /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC              SYSCFG_CM55CR_FPU_IT_EN_5  /*!< Floating Point Unit Inexact Interrupt */
+#define SYSCFG_IT_FPU_ALL              (SYSCFG_CM55CR_FPU_IT_EN_0 |\
+                                        SYSCFG_CM55CR_FPU_IT_EN_1 |\
+                                        SYSCFG_CM55CR_FPU_IT_EN_2 |\
+                                        SYSCFG_CM55CR_FPU_IT_EN_3 |\
+                                        SYSCFG_CM55CR_FPU_IT_EN_4 |\
+                                        SYSCFG_CM55CR_FPU_IT_EN_5)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_Lock_items SYSCFG Lock items
+  * @brief SYSCFG items to set lock on
+  * @{
+  */
+#define SYSCFG_MPU_NSEC                SYSCFG_CM55CR_LOCKNSMPU            /*!< Non-secure MPU lock (privileged secure or non-secure only) */
+#define SYSCFG_VTOR_NSEC               SYSCFG_CM55CR_LOCKNSVTOR           /*!< Non-secure VTOR lock (privileged secure or non-secure only) */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_DCAIC                   (SYSCFG_CM55CR_LOCKDCAIC)          /*!< Disable access to the instruction cache direct cache access registers DCAICLR
+and DCAICRR */
+#define SYSCFG_SAU                     (SYSCFG_CM55CR_LOCKSAU)            /*!< SAU lock (privileged secure code only) */
+#define SYSCFG_MPU_SEC                 (SYSCFG_CM55CR_LOCKSMPU)           /*!< Secure MPU lock (privileged secure code only) */
+#define SYSCFG_VTOR_AIRCR_SEC          (SYSCFG_CM55CR_LOCKSVTAIRCR)       /*!< VTOR_S and AIRCR lock (privileged secure code only) */
+#define SYSCFG_LOCK_ALL                (SYSCFG_MPU_NSEC | SYSCFG_VTOR_NSEC | SYSCFG_DCAIC | SYSCFG_SAU | SYSCFG_MPU_SEC | SYSCFG_VTOR_AIRCR_SEC)  /*!< All */
+#else
+#define SYSCFG_LOCK_ALL                (SYSCFG_MPU_NSEC | SYSCFG_VTOR_NSEC)  /*!< All (privileged secure or non-secure only) */
+#endif /* __ARM_FEATURE_CMSE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_DTCM_size SYSCFG DTCM size
+  * @brief DTCM size to be configured
+  * @{
+  */
+#define SYSCFG_DTCM_128K (SYSCFG_CM55TCMCR_CFGDTCMSZ_3)                                /*!< DTCM memory size is 128K */
+#define SYSCFG_DTCM_256K (SYSCFG_CM55TCMCR_CFGDTCMSZ_0 | SYSCFG_CM55TCMCR_CFGDTCMSZ_3) /*!< DTCM memory size is 256K */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_ITCM_size SYSCFG ITCM size
+  * @brief ITCM size to be configured
+  * @{
+  */
+#define SYSCFG_ITCM_64K  (SYSCFG_CM55TCMCR_CFGITCMSZ_0 | SYSCFG_CM55TCMCR_CFGITCMSZ_1 | SYSCFG_CM55TCMCR_CFGITCMSZ_2) /*!< ITCM memory size is 64K  */
+#define SYSCFG_ITCM_128K (SYSCFG_CM55TCMCR_CFGITCMSZ_3)                                /*!< ITCM memory size is 128K */
+#define SYSCFG_ITCM_256K (SYSCFG_CM55TCMCR_CFGITCMSZ_0 | SYSCFG_CM55TCMCR_CFGITCMSZ_3) /*!< ITCM memory size is 256K */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_WRITE_access  WRITE access selection
+  * @brief WRITE assess to be configured
+  * @{
+  */
+#define SYSCFG_LOCK_WR_TCM  (SYSCFG_CM55TCMCR_LOCKTCM)  /*!< ITCM memory size is 64K  */
+#define SYSCFG_LOCK_WR_ITGU (SYSCFG_CM55TCMCR_LOCKITGU) /*!< Disable writes to registers associated with the ITCM interface security/gating. */
+#define SYSCFG_LOCK_WR_DTGU (SYSCFG_CM55TCMCR_LOCKDTGU) /*!< Disable writes to registers associated with the DTCM interface security/gating */
+#define SYSCFG_LOCK_WR_ALL  (SYSCFG_CM55TCMCR_LOCKTCM | SYSCFG_CM55TCMCR_LOCKITGU | SYSCFG_CM55TCMCR_LOCKDTGU)  /*!< All writes accesses */
+/**
+  * @}
+  */
+/** @defgroup SYSCFG_CACHE_biasing Cache biasing level adjust input selection
+  * @brief CACHE biasing level adjust input selection
+  * @{
+  */
+#define SYSCFG_CACHE_BIAS_VNOM            SYSCFG_CM55RWMCR_BC1_CACHE
+#define SYSCFG_CACHE_BIAS_VNOM_10_PERCENT SYSCFG_CM55RWMCR_BC2_CACHE
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_TCM_biasing biasing level selection
+  * @brief TCM biasing level adjust input selection
+  * @{
+  */
+#define SYSCFG_TCM_BIAS_VNOM            SYSCFG_CM55RWMCR_BC1_TCM
+#define SYSCFG_TCM_BIAS_VNOM_10_PERCENT SYSCFG_CM55RWMCR_BC2_TCM
+/**
+  * @}
+  */
+
+/** @defgroup SBS_Timer_Break_Inputs Timer Break Inputs
+  * @{
+  */
+#define SYSCFG_CBR_BREAK_LOCK_CORE        SYSCFG_CBR_CM55L         /*!< Cortex-CM55 lockup break lock */
+#define SYSCFG_CBR_BREAK_LOCK_PVD         SYSCFG_CBR_PVDL_LOCK     /*!< PVD lock */
+#define SYSCFG_CBR_BREAK_LOCK_BKPRAM      SYSCFG_CBR_BKPRAML       /*!< Backup SRAM ECC error break lock */
+#define SYSCFG_CBR_BREAK_LOCK_CM55_CACHE  SYSCFG_CBR_CM55CACHEL    /*!< CM55 cache double ECC error lock */
+#define SYSCFG_CBR_BREAK_LOCK_CM55_TCM    SYSCFG_CBR_CM55TCML      /*!< CM55 TCM double ECC error lock */
+#define SYSCFG_CBR_BREAK_LOCK_ALL         (SYSCFG_CBR_CM55L      |\
+                                           SYSCFG_CBR_PVDL_LOCK  |\
+                                           SYSCFG_CBR_BKPRAML    |\
+                                           SYSCFG_CBR_CM55CACHEL |\
+                                           SYSCFG_CBR_CM55TCML)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM2_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM2_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM3_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM3_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM4_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM4_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM5_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM5_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM6_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM6_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM7_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM7_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM10_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM10()             SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM10()           CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM10_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM10_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM11_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM11()             SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM11()           CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM11_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM11_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM12()             SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12()           CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM12_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM12_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM13()             SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13()           CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM13_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM13_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM14()             SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14()           CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM14_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM14_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1()            SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()          CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_WWDG1_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG()             SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_WWDG1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()           CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_WWDG1_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C1_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C1_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C2_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C2_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C3_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C3_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_I3C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I3C1()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I3C1()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C1_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_I3C1_STOP) */
+
+#if defined(DBGMCU_APB1LFZ1_DBG_I3C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I3C2()              SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I3C2()            CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C2_STOP)
+#endif /* defined(DBGMCU_APB1LFZ1_DBG_I3C2_STOP) */
+
+#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_FREEZE_FDCAN()             SET_BIT(DBGMCU->APB1HFZ1, DBGMCU_APB1HFZ1_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_UNFREEZE_FDCAN()           CLEAR_BIT(DBGMCU->APB1HFZ1, DBGMCU_APB1HFZ1_DBG_FDCAN_STOP)
+#endif /* defined(DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) */
+
+#if defined(DBGMCU_APB2FZ1_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1()              SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1()            CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM1_STOP)
+#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM1_STOP) */
+
+#if defined(DBGMCU_APB2FZ1_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8()              SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8()            CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM8_STOP)
+#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM8_STOP) */
+
+#if defined(DBGMCU_APB2FZ1_DBG_TIM18_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM18()             SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM18_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM18()           CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM18_STOP)
+#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM18_STOP) */
+
+#if defined(DBGMCU_APB2FZ1_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15()             SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15()           CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM15_STOP)
+#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM15_STOP) */
+
+#if defined(DBGMCU_APB2FZ1_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16()             SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16()           CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM16_STOP)
+#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM16_STOP) */
+
+#if defined(DBGMCU_APB2FZ1_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17()             SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17()           CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM17_STOP)
+#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM17_STOP) */
+
+#if defined(DBGMCU_APB2FZ1_DBG_TIM9_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM9()              SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM9()            CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM9_STOP)
+#endif /* defined(DBGMCU_APB2FZ1_DBG_TIM9_STOP) */
+
+#if defined(DBGMCU_APB4FZ1_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4()              SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4()            CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_I2C4_STOP)
+#endif /* defined(DBGMCU_APB4FZ1_DBG_I2C4_STOP) */
+
+#if defined(DBGMCU_APB4FZ1_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2()            SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2()          CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM2_STOP)
+#endif /* defined(DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) */
+
+#if defined(DBGMCU_APB4FZ1_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM3()            SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM3()          CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM3_STOP)
+#endif /* DBGMCU_APB4FZ1_DBG_LPTIM3_STOP */
+
+#if defined(DBGMCU_APB4FZ1_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM4()            SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM4()          CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM4_STOP)
+#endif /* DBGMCU_APB4FZ1_DBG_LPTIM4_STOP */
+
+#if defined(DBGMCU_APB4FZ1_DBG_LPTIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM5()            SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM5()          CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM5_STOP)
+#endif /* DBGMCU_APB4FZ1_DBG_LPTIM5_STOP */
+
+#if defined(DBGMCU_APB4FZ1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC()               SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC()             CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_RTC_STOP)
+#endif /* DBGMCU_APB4FZ1_DBG_RTC_STOP */
+
+#if defined(DBGMCU_APB4FZ1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG()              SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()            CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_IWDG_STOP)
+#endif /* DBGMCU_APB4FZ1_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB5FZ1_DBG_GFXTIM_STOP)
+#define __HAL_DBGMCU_FREEZE_GFXTIM()            SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5FZ1_DBG_GFXTIM_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GFXTIM()          CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5FZ1_DBG_GFXTIM_STOP)
+#endif /* DBGMCU_APB5FZ1_DBG_GFXTIM_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH0()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH0()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH1()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH1()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH2()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH2()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH3()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH3()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH4()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH4()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH5()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH5()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH6()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH6()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH7()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH7()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH8()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH8()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH9()        SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH9()      CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH10()       SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH10()     CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH11()       SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH11()     CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH12()       SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH12()     CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH13()       SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH13()     CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH14()       SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH14()     CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP */
+
+#if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP)
+#define __HAL_DBGMCU_FREEZE_GPDMA1_CH15()       SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH15()     CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP)
+#endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH0()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH0()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH1()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH1()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH2()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH2()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH3()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH3()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH4()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH4()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH5()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH5()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH6()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH6()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH7()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH7()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH8()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH8()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH9()        SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH9()      CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH10()       SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH10()     CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH11()       SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH11()     CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH12()       SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH12()     CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH13()       SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH13()     CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH14()       SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH14()     CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP)
+#define __HAL_DBGMCU_FREEZE_HPDMA1_CH15()       SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH15()     CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP)
+#endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP */
+
+#if defined(DBGMCU_AHB5FZ1_NPU_DBG_FREEZE)
+#define __HAL_DBGMCU_FREEZE_NPU()               SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_NPU_DBG_FREEZE)
+#define __HAL_DBGMCU_UNFREEZE_NPU()             CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_NPU_DBG_FREEZE)
+#endif /* DBGMCU_AHB5FZ1_NPU_DBG_FREEZE */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  Floating Point Unit interrupt enable/disable macros
+  * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
+  */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                 SET_BIT(SYSCFG->CM55CR, (__INTERRUPT__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                 CLEAR_BIT(SYSCFG->CM55CR, (__INTERRUPT__));\
+                                                               }while(0)
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+  * @{
+  */
+#define IS_SYSCFG_BOOT_ID(__BOOTID__)  ((((__BOOTID__) & SYSCFG_BOOT_0) == SYSCFG_BOOT_0) || \
+                                        (((__BOOTID__) & SYSCFG_BOOT_1) == SYSCFG_BOOT_1))
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) (((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC)  || \
+                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC)  || \
+                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC)  || \
+                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC)  || \
+                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC)  || \
+                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) && \
+                                                (((__INTERRUPT__) & ~(SYSCFG_IT_FPU_ALL)) == 0U))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) (((((__ITEM__) & SYSCFG_MPU_NSEC)       == SYSCFG_MPU_NSEC)  || \
+                                         (((__ITEM__) & SYSCFG_VTOR_NSEC)      == SYSCFG_VTOR_NSEC) || \
+                                         (((__ITEM__) & SYSCFG_DCAIC)          == SYSCFG_DCAIC)     || \
+                                         (((__ITEM__) & SYSCFG_SAU)            == SYSCFG_SAU)       || \
+                                         (((__ITEM__) & SYSCFG_MPU_SEC)        == SYSCFG_MPU_SEC)   || \
+                                         (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC)) && \
+                                        (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U))
+#else
+#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) (((((__ITEM__) & SYSCFG_MPU_NSEC)  == SYSCFG_MPU_NSEC)  || \
+                                         (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC)) && \
+                                        (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U))
+#endif /* __ARM_FEATURE_CMSE */
+
+#define IS_SYSCFG_DTCM_SIZE(__SIZE__) ((((__SIZE__) & SYSCFG_CM55TCMCR_CFGDTCMSZ) == SYSCFG_DTCM_128K)  || \
+                                       (((__SIZE__) & SYSCFG_CM55TCMCR_CFGDTCMSZ) == SYSCFG_DTCM_256K))
+
+#define IS_SYSCFG_ITCM_SIZE(__SIZE__) ((((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_64K)   || \
+                                       (((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_128K)  || \
+                                       (((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_256K))
+
+#define IS_SYSCFG_LOCK_WRACCESS(__WRACCESS__) (((((__WRACCESS__) & SYSCFG_LOCK_WR_TCM)   == SYSCFG_LOCK_WR_TCM)  || \
+                                                (((__WRACCESS__) & SYSCFG_LOCK_WR_ITGU)  == SYSCFG_LOCK_WR_ITGU) || \
+                                                (((__WRACCESS__) & SYSCFG_LOCK_WR_DTGU)  == SYSCFG_LOCK_WR_DTGU)) && \
+                                               (((__WRACCESS__) & ~(SYSCFG_LOCK_WR_ALL)) == 0U))
+
+#define IS_TCM_MARGIN_INPUT(__MARGIN__)  ((__MARGIN__) < 16U)
+
+#define IS_SYSCFG_CACHE_BIASING_LEVEL(__LEVEL__) ((((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_CACHE | SYSCFG_CM55RWMCR_BC2_CACHE)) == SYSCFG_CACHE_BIAS_VNOM)             || \
+                                                  (((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_CACHE | SYSCFG_CM55RWMCR_BC2_CACHE)) == SYSCFG_CACHE_BIAS_VNOM_10_PERCENT))
+
+#define IS_SYSCFG_TCM_BIASING_LEVEL(__LEVEL__) ((((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_TCM | SYSCFG_CM55RWMCR_BC2_TCM)) == SYSCFG_TCM_BIAS_VNOM)  || \
+                                                (((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_TCM | SYSCFG_CM55RWMCR_BC2_TCM)) == SYSCFG_TCM_BIAS_VNOM_10_PERCENT))
+
+#define IS_VTOR_ADDRESS(__ADDRESS__) (((__ADDRESS__) & 0x7FU) == 0U)
+
+#define IS_SYSCFG_QOS_CPU(__QOS__) ((__QOS__) < 16U)
+
+#define IS_SYSCFG_SDMMC(__SDMMC__) (((((__SDMMC__) & SYSCFG_SDMMC1) == SYSCFG_SDMMC1) || \
+                                     (((__SDMMC__) & SYSCFG_SDMMC2) == SYSCFG_SDMMC2)) && \
+                                    (((__SDMMC__) & ~(SYSCFG_SDMMC_ALL)) == 0U))
+
+#define IS_SYSCFG_USB(__USB__) (((((__USB__) & SYSCFG_USB1) == SYSCFG_USB1) || \
+                                 (((__USB__) & SYSCFG_USB2) == SYSCFG_USB2)) && \
+                                (((__USB__) & ~(SYSCFG_USB_ALL)) == 0U))
+
+#if defined(SYSCFG_ICNCGCR_NPU_NOC_CG_DISABLE)
+#define IS_SYSCFG_CPU_CLK_GATING(__CPU__) (((((__CPU__) & SYSCFG_NPU_NOC) == SYSCFG_NPU_NOC) || \
+                                            (((__CPU__) & SYSCFG_CPU_NIC) == SYSCFG_CPU_NIC) || \
+                                            (((__CPU__) & SYSCFG_CPU_NOC) == SYSCFG_CPU_NOC)) && \
+                                           (((__CPU__) & ~(SYSCFG_CPU_ALL)) == 0U))
+#else
+#define IS_SYSCFG_CPU_CLK_GATING(__CPU__) (((((__CPU__) & SYSCFG_CPU_NIC) == SYSCFG_CPU_NIC) ||  \
+                                            (((__CPU__) & SYSCFG_CPU_NOC) == SYSCFG_CPU_NOC)) && \
+                                           (((__CPU__) & ~(SYSCFG_CPU_ALL)) == 0U))
+#endif /* defined(SYSCFG_ICNCGCR_NPU_NOC_CG_DISABLE) */
+
+#define IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
+#define IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
+
+#define IS_SYSCFG_COMPENSATION_CELL(__VALUE__) (((__VALUE__) == SYSCFG_IO_VDDIO2_CELL) || \
+                                                ((__VALUE__) == SYSCFG_IO_VDDIO3_CELL) || \
+                                                ((__VALUE__) == SYSCFG_IO_VDDIO4_CELL) || \
+                                                ((__VALUE__) == SYSCFG_IO_VDDIO5_CELL))
+
+#define IS_SYSCFG_IO_COMPENSATION_CODE(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_CODE)      || \
+                                                  ((__CELL__) == SYSCFG_IO_REGISTER_CODE))
+
+#define IS_SYSCFG_CBR_BREAK_INPUT(__VALUE__) \
+  ((((__VALUE__) & SYSCFG_CBR_BREAK_LOCK_ALL) != 0U) && \
+   (((__VALUE__) & ~SYSCFG_CBR_BREAK_LOCK_ALL) == 0U))
+
+#define IS_SYSCFG_DMA_CID_SEC(__CID__) (((__CID__) < 8U))
+
+#define IS_SYSCFG_DMA_CID_NON_SEC(__CID__) (((__CID__) < 8U))
+
+#define IS_SYSCFG_DMA_DELAY_FEEDBACK_CLOCK(__DELAY__) (((__DELAY__) == SYSCFG_DELAY_FEEDBACK_NONE)  || \
+                                                       ((__DELAY__) == SYSCFG_DELAY_FEEDBACK_HALF_CYCLE))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+  * @{
+  */
+
+/* DBGMCU Peripheral Control functions  *****************************************/
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/** @addtogroup HAL_Exported_Functions_Group4
+  * @{
+  */
+
+/* SYSCFG Peripheral Control functions  *****************************************/
+void HAL_SYSCFG_EnablePullDown(uint32_t BootId);
+void HAL_SYSCFG_DisablePullDown(uint32_t BootId);
+
+
+void HAL_SYSCFG_Lock(uint32_t Item);
+HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem);
+
+void HAL_SYSCFG_SetTCMSize(uint32_t DtcmSize, uint32_t ItcmSize);
+HAL_StatusTypeDef HAL_SYSCFG_GetTCMSize(uint32_t *pDtcmSize, uint32_t *pItcmSize);
+
+void HAL_SYSCFG_LockWriteAccess(uint32_t Item);
+HAL_StatusTypeDef HAL_SYSCFG_GetLockWriteAccess(uint32_t *pItem);
+
+void HAL_SYSCFG_EnableITCMWaiteState(void);
+void HAL_SYSCFG_DisableITCMWaiteState(void);
+void HAL_SYSCFG_EnableDTCMWaiteState(void);
+void HAL_SYSCFG_DisableDTCMWaiteState(void);
+
+void HAL_SYSCFG_EnableTCMExternalMargin(void);
+void HAL_SYSCFG_DisableTCMExternalMargin(void);
+
+void HAL_SYSCFG_SetTCMRWMarginInput(uint32_t TcmRwMarginInput);
+HAL_StatusTypeDef HAL_SYSCFG_GetTCMRWMarginInput(uint32_t *pTcmRwMarginInput);
+
+void HAL_SYSCFG_SetTCMBiasingLevel(uint32_t Level);
+HAL_StatusTypeDef HAL_SYSCFG_GetTCMBiasingLevel(uint32_t *pLevel);
+
+void HAL_SYSCFG_EnableCacheExternalMargin(void);
+void HAL_SYSCFG_DisableCacheExternalMargin(void);
+
+void HAL_SYSCFG_SetCacheRWMarginInput(uint32_t CacheRWMarginInput);
+HAL_StatusTypeDef HAL_SYSCFG_GetCacheRWMarginInput(uint32_t *pCacheRWMarginInput);
+
+void HAL_SYSCFG_SetCacheBiasingLevel(uint32_t Level);
+HAL_StatusTypeDef HAL_SYSCFG_GetCacheBiasingLevel(uint32_t *pLevel);
+
+
+void HAL_SYSCFG_SetSVTORAddress(uint32_t Address);
+HAL_StatusTypeDef HAL_SYSCFG_GetSVTORAddress(uint32_t *pAddress);
+
+void HAL_SYSCFG_SetNSVTORAddress(uint32_t Address);
+HAL_StatusTypeDef HAL_SYSCFG_GetNSVTORAddress(uint32_t *pAddress);
+
+
+void HAL_SYSCFG_EnablePowerOnReset(void);
+void HAL_SYSCFG_DisablePowerOnReset(void);
+
+void HAL_SYSCFG_EnableLockupWarmResetonRCC(void);
+void HAL_SYSCFG_DisableLockupWarmResetonRCC(void);
+
+void HAL_SYSCFG_EnableLockupGenerateNMI(void);
+void HAL_SYSCFG_DisableLockupGenerateNMI(void);
+
+HAL_StatusTypeDef HAL_SYSCFG_ReEnableWritePostingErrorCapture(void);
+
+#if defined(VENC)
+void HAL_SYSCFG_EnableVENCRAMReserved(void);
+void HAL_SYSCFG_DisableVENCRAMReserved(void);
+#endif /* VENC */
+
+void HAL_SYSCFG_EnableCRYPPotentialTamper(void);
+void HAL_SYSCFG_DisableCRYPPotentialTamper(void);
+
+
+void HAL_SYSCFG_SetWriteQosNP1(uint32_t QosValue);
+HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP1(uint32_t *pQosValue);
+void HAL_SYSCFG_SetReadQosNP1(uint32_t QosValue);
+HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP1(uint32_t *pQosValue);
+
+void HAL_SYSCFG_SetWriteQosNP2(uint32_t QosValue);
+HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP2(uint32_t *pQosValue);
+void HAL_SYSCFG_SetReadQosNP2(uint32_t QosValue);
+HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP2(uint32_t *pQosValue);
+
+void HAL_SYSCFG_SetWriteQosCPUSS(uint32_t QosValue);
+HAL_StatusTypeDef HAL_SYSCFG_GetwriteQosCPUSS(uint32_t *pQosValue);
+void HAL_SYSCFG_SetReadQosCPUSS(uint32_t QosValue);
+HAL_StatusTypeDef HAL_SYSCFG_GetReadQosCPUSS(uint32_t *pQosValue);
+
+
+void HAL_SYSCFG_EnableSDMMCEarlyWRRESP(uint32_t Sdmmc);
+void HAL_SYSCFG_DisableSDMMCEarlyWRRSP(uint32_t Sdmmc);
+
+void HAL_SYSCFG_EnableUSBEarlyEarlyWRRESP(uint32_t Usb);
+void HAL_SYSCFG_DisableUSBEarlyEarlyWRRESP(uint32_t Usb);
+
+
+void HAL_SYSCFG_EnablexPUClockGating(uint32_t Xpu);
+void HAL_SYSCFG_DisablexPUClockGating(uint32_t Xpu);
+
+
+
+
+void HAL_SYSCFG_EnableVDDIO2CompensationCell(void);
+void HAL_SYSCFG_DisableVDDIO2CompensationCell(void);
+
+void HAL_SYSCFG_EnableVDDIO3CompensationCell(void);
+void HAL_SYSCFG_DisableVDDIO3CompensationCell(void);
+
+void HAL_SYSCFG_EnableVDDIO4CompensationCell(void);
+void HAL_SYSCFG_DisableVDDIO4CompensationCell(void);
+
+void HAL_SYSCFG_EnableVDDIO5CompensationCell(void);
+void HAL_SYSCFG_DisableVDDIO5CompensationCell(void);
+
+
+HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDIOCompensationCell(uint32_t Selection, uint32_t Code,
+                                                         uint32_t NmosValue, uint32_t PmosValue);
+
+HAL_StatusTypeDef HAL_SYSCFG_GetVDDIOCompensationCell(uint32_t Selection, const uint32_t *pCode, uint32_t *pNmosValue,
+                                                      uint32_t *pPmosValue);
+
+
+uint32_t HAL_SYSCFG_GetCompVDDIO2CellReadyStatus(void);
+uint32_t HAL_SYSCFG_GetCompVDDIO3CellReadyStatus(void);
+uint32_t HAL_SYSCFG_GetCompVDDIO4CellReadyStatus(void);
+uint32_t HAL_SYSCFG_GetCompVDDIO5CellReadyStatus(void);
+
+HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDCompensationCell(uint32_t Code, uint32_t NmosValue, uint32_t PmosValue);
+
+void HAL_SYSCFG_EnableVDDCompensationCell(void);
+void HAL_SYSCFG_DisableVDDCompensationCell(void);
+
+HAL_StatusTypeDef HAL_SYSCFG_GetVDDCompensationCell(uint32_t Code, uint32_t *pNmosValue,
+                                                 uint32_t *pPmosValue);
+uint32_t HAL_SYSCFG_GetCompensationVDDCellReadyStatus(void);
+
+void HAL_SYSCFG_ConfigTimerBreakInput(uint32_t Input);
+uint32_t HAL_SYSCFG_GetTimerBreakInputConfig(void);
+
+void HAL_SYSCFG_SetPerceivedCID(uint32_t Cid);
+uint32_t HAL_SYSCFG_GetPerceivedCID(void);
+
+void HAL_SYSCFG_SetPerceivedPrivCID(uint32_t Cid);
+uint32_t HAL_SYSCFG_GetPerceivedPrivCID(void);
+
+void HAL_SYSCFG_EnableReTimingRXpath(void);
+void HAL_SYSCFG_DisableReTimingRXpath(void);
+
+void HAL_SYSCFG_EnableReTimingTXpath(void);
+void HAL_SYSCFG_DisableReTimingTXpath(void);
+
+void HAL_SYSCFG_SetDelayOnFeedbackClock(uint32_t Delay);
+uint32_t HAL_SYSCFG_GetDelayOnFeedbackClock(void);
+
+void HAL_SYSCFG_EnableInterleavingCpuRam(void);
+void HAL_SYSCFG_DisableInterleavingCpuRam(void);
+
+uint32_t HAL_SYSCFG_GetBootPinConnection(uint32_t BootId);
+
+uint32_t HAL_SYSCFG_GetAddressWritePostingBuffer(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32N6xx_HAL_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_adc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_adc.h
new file mode 100644
index 000000000..f88fafeb0
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_adc.h
@@ -0,0 +1,1896 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_ADC_H
+#define STM32N6xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32n6xx_ll_adc.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC group regular oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value from 1 to 1024 */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+  uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
+                                               The oversampling is either temporary stopped or reset upon an injected
+                                               sequence interruption.
+                                               If oversampling is enabled on both regular and injected groups,
+                                               this parameter is discarded and forced to setting
+                                               "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed
+                                               during injection sequence).
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
+
+} ADC_OversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC instance and ADC group regular.
+  * @note   ADC clock prescaler (init structure "ClockPrescaler" in other ADC IP versions FW drivers)
+  *         is moved on RCC side on this STM32 series (rational: for feature "fixed trigger latency").
+  *         Refer to RCC FW drivers to configure ADC clock prescaler.
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (affects ADC groups regular and injected): Resolution,
+  *            GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
+  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
+  *            NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun,
+   *           OversamplingMode, Oversampling, SamplingMode.
+  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling':
+  *            ADC enabled without conversion on going on group regular.
+  *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
+  *            on groups regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t Resolution;            /*!< Configure the ADC resolution.
+                                       This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+  uint32_t GainCompensation;      /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw
+                                       conversion data, based on following formula:
+                                           DATA = DATA(raw) * (gain compensation coef) / 4096
+                                        12 bit format, unsigned: 2 bits exponents / 12 bits mantissa
+                                        Gain step is 1/4096 = 0.000244
+                                        Gain range is 0.0000 to 3.999756
+                                       This parameter value can be:
+                                        - value "0": Gain compensation will be disabled and coefficient set to 0
+                                        - value in range [0x0001; 0x3FFF]: Gain compensation will enabled
+                                          and coefficient set to specified value */
+
+  uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode'
+                                       to have main sequence subdivided in successive parts.
+                                       If disabled: Conversion is performed in single mode (one channel converted,
+                                                    the one defined in rank 1).
+                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion'
+                                                    are discarded (equivalent to set to 1).
+                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined
+                                                    by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of
+                                                    each channel in sequencer).
+                                                    Scan direction is upward: from rank 1 to rank 'n'.
+                                       This parameter can be a value of @ref ADC_Scan_mode */
+
+  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
+                                       interruption: end of unitary conversion or end of sequence conversions.
+                                       This parameter can be a value of @ref ADC_EOCSelection. */
+
+  FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
+                                       previous conversion (for ADC group regular) or previous sequence (for ADC group
+                                       injected) has been retrieved by user software, using function HAL_ADC_GetValue()
+                                       or HAL_ADCEx_InjectedGetValue().
+                                       This feature automatically adapts the frequency of ADC conversions triggers to
+                                       the speed of the system that reads the data. Moreover, this avoids risk of
+                                       overrun for low frequency applications.
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
+                                             HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
+                                             flag (by CPU to free the IRQ pending event or by DMA).
+                                             Auto wait will work but fort a very short time, discarding its intended
+                                             benefit (except specific case of high load of CPU or DMA transfers which
+                                             can justify usage of auto wait).
+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
+                                             when ADC conversion data is needed:
+                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and
+                                             HAL_ADC_GetValue() to retrieve conversion result and trig another
+                                             conversion start. (in case of usage of ADC group injected, use the
+                                             equivalent functions HAL_ADCExInjected_Start(),
+                                             HAL_ADCEx_InjectedGetValue(), ...). */
+
+  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
+                                           or continuous mode for ADC group regular, after the first ADC conversion
+                                           start trigger occurred (software start or external trigger). This parameter
+                                           can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group
+                                       sequencer.
+                                       To use the regular group sequencer and convert several ranks,
+                                       parameter 'ScanConvMode' must be enabled.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+                                       Note: This parameter must be modified when no conversion is on going on
+                                             regular group (ADC disabled, or ADC enabled without continuous mode
+                                             or external trigger that could launch a conversion). */
+
+  FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
+                                              in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
+                                              successive parts).
+                                              Discontinuous mode is used only if sequencer is enabled (parameter
+                                              'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                              Discontinuous mode can be enabled only if continuous mode is disabled.
+                                              If continuous mode is enabled, this parameter setting is discarded.
+                                              This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence
+                                       of ADC group regular (parameter NbrOfConversion) will be subdivided.
+                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+
+  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion
+                                       start.
+                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
+                                       is used instead.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
+                                       Caution: external trigger source is common to all ADC instances. */
+
+  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular
+                                       conversion start.
+                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+  uint32_t SamplingMode;          /*!< Select the sampling mode to be used for ADC group regular conversion.
+                                       This parameter can be a value of @ref ADC_regular_sampling_mode */
+
+  uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA
+                                       (oneshot or circular), or stored in the DR register or
+                                       transferred to MDF register.
+                                       Note: In continuous mode, DMA must be configured in circular mode.
+                                             Otherwise an overrun will be triggered when DMA buffer maximum pointer
+                                             is reached.
+                                       This parameter can be a value of @ref ADC_ConversionDataManagement.
+                                       Note: This parameter must be modified when no conversion is on going on both
+                                             regular and injected groups (ADC disabled, or ADC enabled without
+                                             continuous mode or external trigger that could launch a conversion). */
+
+  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+                                       This parameter applies to ADC group regular only.
+                                       This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+                                       Note: In case of overrun set to data preserved and usage with programming model
+                                             with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
+                                             conversion flags, this induces the release of the preserved data.
+                                             If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
+                                             placed in user program code (called before end of conversion flags clear).
+                                       Note: Error reporting with respect to the conversion mode:
+                                             - Usage with ADC conversion by polling for event or interruption:
+                                                  Error is reported only if overrun is set to data preserved.
+                                                  If overrun is set to data overwritten, user can willingly not read
+                                                  all the converted data, this is not considered as an erroneous case.
+                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun
+                                               setting (DMA is expected to process all data from data register). */
+
+  uint32_t LeftBitShift;             /*!< Configures the left shifting applied to the final result with or without
+                                          oversampling.
+                                          This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
+
+  FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter can be modified only if there is no conversion
+                                                     is ongoing on ADC groups regular and injected */
+
+  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
+                                               Caution: this setting overwrites the previous oversampling configuration
+                                                        if oversampling is already enabled. */
+
+} ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of ADC channel for regular group
+  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+  *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion
+  *            on going on regular group.
+  *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on
+  *            regular and injected groups.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly.
+  */
+typedef struct
+{
+  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+                                        Note: Depending on devices and ADC instances, some channels may not be available
+                                              on device package pins. Refer to device datasheet for channels
+                                              availability. */
+
+  uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
+                                        This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
+                                        Note: to disable a channel or change order of conversion sequencer, rank
+                                              containing a previous channel setting can be overwritten by
+                                              the new channel setting (or parameter number of conversions adjusted) */
+
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time
+                                        (13.5 ADC clock cycles at ADC resolution 12 bits, 11.5 cycles at 10 bits,
+                                        8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+                                        Caution: This parameter applies to a channel that can be used into regular
+                                                 and/or injected group. It overwrites the last setting.
+                                        Note: In case of usage of internal measurement channels
+                                              (VrefInt/Vbat/TempSensor), sampling time constraints must be respected
+                                              (sampling time can be adjusted in function of ADC clock frequency
+                                              and sampling time setting).
+                                              Refer to device datasheet for timings values. */
+
+  uint32_t SingleDiff;             /*!< Select single-ended or differential input.
+                                        In differential mode: Differential measurement is carried out between
+                                                              the selected channel (positive input) and
+                                                              another channel (negative input). Refer to
+                                                              reference manual for corresponding channel.
+                                                              Only channel of positive input has to be
+                                                              configured, the other channel is configured
+                                                              automatically.
+                                        This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
+                                        Caution: This parameter applies to a channel that can be used in a regular
+                                                 and/or injected group. It overwrites the last setting.
+                                        Note: Refer to Reference Manual to ensure the selected channel is available
+                                              in differential mode.
+                                        Note: When configuring a channel 'i' in differential mode, the channel 'i+1'
+                                              is not usable separately.
+                                        Note: This parameter must be modified when ADC is disabled (before ADC start
+                                              conversion or after ADC stop conversion).
+                                              If ADC is enabled, this parameter setting is bypassed without error
+                                              reporting (as it can be the expected behavior in case of another parameter
+                                              update on the fly) */
+
+  uint32_t OffsetNumber;           /*!< Select the offset number
+                                        This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
+                                        Caution: Only one offset is allowed per channel. This parameter overwrites the
+                                                 last setting. */
+
+  uint32_t Offset;                 /*!< Define the offset to be subtracted from the raw converted data.
+                                        Offset value must be a positive number.
+                                        Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+                                        must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
+                                        0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+                                        Note: This parameter must be modified when no conversion is on going on both
+                                              regular and injected groups (ADC disabled, or ADC enabled without
+                                              continuous mode or external trigger that could launch a conversion). */
+
+  FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
+                                             This parameter is applied only for 16-bit or 8-bit resolution.
+                                             This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState OffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
+                                        This parameter value can be ENABLE or DISABLE.
+                                        Note:
+                                              - This parameter must be modified when no conversion is on going on
+                                                both regular and injected groups (ADC disabled, or ADC enabled without
+                                                continuous mode or external trigger that could launch a conversion).*/
+
+  uint32_t OffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added
+                                           (positive sign) from or to the raw converted data.
+                                           This parameter can be a value of @ref ADCEx_OffsetSign.
+                                           Note:
+                                              - This parameter must be modified when no conversion is on going on
+                                                both regular and injected groups (ADC disabled, or ADC enabled without
+                                                continuous mode or external trigger that could launch a conversion).*/
+
+
+} ADC_ChannelConfTypeDef;
+
+/**
+  * @brief  Structure definition of ADC analog watchdog
+  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular
+  *            and injected.
+  */
+typedef struct
+{
+  uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
+                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
+                                                          by setting parameter 'WatchdogMode')
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
+                                                                of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+                                   This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
+                                                          channels, ADC groups regular and-or injected.
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored by applying
+                                                                successively the AWD init structure.
+                                   Channels on ADC group regular and injected are not differentiated:
+                                            Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel,
+                                            value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels,
+                                            'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
+                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
+                                                          is configured on single channel (only 1 channel can be
+                                                          monitored).
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
+                                                                call successively the function HAL_ADC_AnalogWDGConfig()
+                                                                for each channel to be added (or removed with value
+                                                                'ADC_ANALOGWATCHDOG_NONE').
+                                   This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+  FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+                                   must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF
+                                   or 0x3F respectively. */
+
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+                                   must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF
+                                   or 0x3F respectively. */
+
+  uint32_t FilteringConfig;   /*!< Specify whether filtering should be use and the number of samples to consider.
+                                   Before setting flag or raising interrupt, analog watchdog can wait to have several
+                                   consecutive out-of-window samples. This parameter allows to configure this number.
+                                   This parameter only applies to Analog watchdog 1. For others, use value
+                                   ADC_AWD_FILTERING_NONE.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
+
+} ADC_AnalogWDGConfTypeDef;
+
+/** @defgroup ADC_States ADC States
+  * @{
+  */
+
+/**
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  * @note   ADC state machine is managed by bitfields, state must be compared
+  *         with bit by bit.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization,
+                                                              calibration, ...) */
+#define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur
+                                                              (either by continuous mode, external trigger, low power
+                                                              auto power-on (if feature available), multimode ADC master
+                                                              control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag
+                                                              raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur
+                                                              (either by auto-injection mode, external trigger, low
+                                                              power auto power-on (if feature available), multimode
+                                                              ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)   /*!< Conversion data available on group injected */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< ADC in multimode slave state, controlled by another
+                                                              ADC master (when feature available) */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  ADC handle Structure definition
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+  ADC_TypeDef                   *Instance;                     /*!< Register base address */
+  ADC_InitTypeDef               Init;                          /*!< ADC initialization parameters and regular
+                                                                    conversions setting */
+  DMA_HandleTypeDef             *DMA_Handle;                   /*!< Pointer DMA Handler */
+  HAL_LockTypeDef               Lock;                          /*!< ADC locking object */
+  __IO uint32_t                 State;                         /*!< ADC communication state (bitmap of ADC states) */
+  __IO uint32_t                 ErrorCode;                     /*!< ADC Error code */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer
+                                                                                 callback */
+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
+  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete
+                                                                                 callback */
+  void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
+  void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
+  void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ADC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
+  HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ADC Callback pointer definition
+  */
+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */
+#define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
+#define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
+                                                       enable/disable, erroneous state, ...)       */
+#define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
+#define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
+#define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+  * @{
+  */
+#define ADC_SCAN_DISABLE         (0x00000000UL)       /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE          (0x00000001UL)       /*!< Scan mode enabled  */
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL    (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
+/**
+  * @}
+  */
+
+/* Combination of all CHSELR bits: SQ2...SQ8 */
+#define ADC_CHSELR_SQ2_TO_SQ8           (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5\
+                                         | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+  * @{
+  */
+#define ADC_SOFTWARE_START                 (LL_ADC_REG_TRIG_SOFTWARE)                /*!< ADC group regular conversion
+                                            trigger internal: SW start. */
+#define ADC_EXTERNALTRIG_EXT_IT11          (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         /*!< ADC group regular conversion
+                                           trigger from external peripheral: external interrupt line 11. */
+#define ADC_EXTERNALTRIG_T1_CC1            (LL_ADC_REG_TRIG_EXT_TIM1_CH1)            /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM1 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC2            (LL_ADC_REG_TRIG_EXT_TIM1_CH2)            /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM1 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC3            (LL_ADC_REG_TRIG_EXT_TIM1_CH3)            /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM1 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_TRGO           (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM1 TRGO event. */
+#define ADC_EXTERNALTRIG_T1_TRGO2          (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM1 TRGO2 event. */
+#define ADC_EXTERNALTRIG_T2_CC2            (LL_ADC_REG_TRIG_EXT_TIM2_CH2)            /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM2 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_TRGO           (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM2 TRGO event. */
+#define ADC_EXTERNALTRIG_T3_CC4            (LL_ADC_REG_TRIG_EXT_TIM3_CH4)            /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_T3_TRGO           (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM3 TRGO event. */
+#define ADC_EXTERNALTRIG_T4_CC4            (LL_ADC_REG_TRIG_EXT_TIM4_CH4)            /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM4 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_T4_TRGO           (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM4 TRGO event. */
+#define ADC_EXTERNALTRIG_T5_TRGO           (LL_ADC_REG_TRIG_EXT_TIM5_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM5 TRGO event. */
+#define ADC_EXTERNALTRIG_T6_TRGO           (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM6 TRGO event. */
+#define ADC_EXTERNALTRIG_T7_TRGO           (LL_ADC_REG_TRIG_EXT_TIM7_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM7 TRGO event. */
+#define ADC_EXTERNALTRIG_T8_TRGO           (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM8 TRGO event. */
+#define ADC_EXTERNALTRIG_T8_TRGO2          (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM8 TRGO2 event. */
+#define ADC_EXTERNALTRIG_T9_CC1            (LL_ADC_REG_TRIG_EXT_TIM9_CH1)            /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM9 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T9_TRGO           (LL_ADC_REG_TRIG_EXT_TIM9_TRGO)           /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM9 TRGO event. */
+#define ADC_EXTERNALTRIG_T12_TRGO          (LL_ADC_REG_TRIG_EXT_TIM12_TRGO)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM12 TRGO event. */
+#define ADC_EXTERNALTRIG_T15_TRGO          (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM15 TRGO event. */
+#define ADC_EXTERNALTRIG_T18_TRGO          (LL_ADC_REG_TRIG_EXT_TIM18_TRGO)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: TIM18 TRGO event. */
+#define ADC_EXTERNALTRIG_LPTIM1_CH1        (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: LPTIM1 channel 1 event. */
+#define ADC_EXTERNALTRIG_LPTIM2_CH1        (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: LPTIM2 channel 2 event. */
+#define ADC_EXTERNALTRIG_LPTIM3_CH1        (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1)          /*!< ADC group regular conversion
+                                           trigger from external peripheral: LPTIM3 channel 3 event. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< ADC group regular trigger
+                                                disabled (SW start)*/
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion
+                                                trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion
+                                                trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
+                                                trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
+  * @{
+  */
+#define ADC_SAMPLING_MODE_NORMAL                (0x00000000UL)      /*!< ADC conversions sampling phase duration is
+                                                defined using  @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
+#define ADC_SAMPLING_MODE_BULB                  (ADC_CFGR2_BULB)    /*!< ADC conversions sampling phase starts
+                                                immediately after end of conversion, and stops upon trigger event.
+                                                Note: First conversion is using minimal sampling time
+                                                      (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
+#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED     (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled
+                                                by trigger events:
+                                                Trigger rising edge  = start sampling
+                                                Trigger falling edge = stop sampling and start conversion */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+  * @{
+  */
+#define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
+#define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case
+                                           of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case
+                                           of overrun: data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_9                 (LL_ADC_REG_RANK_9)  /*!< ADC group regular sequencer rank 9 */
+#define ADC_REGULAR_RANK_10                (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
+#define ADC_REGULAR_RANK_11                (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
+#define ADC_REGULAR_RANK_12                (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
+#define ADC_REGULAR_RANK_13                (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
+#define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
+#define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
+#define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define ADC_SAMPLETIME_1CYCLE_5          (LL_ADC_SAMPLINGTIME_1CYCLE_5)     /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_2CYCLES_5         (LL_ADC_SAMPLINGTIME_2CYCLES_5)    /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_6CYCLES_5         (LL_ADC_SAMPLINGTIME_6CYCLES_5)    /*!< Sampling time 6.5 ADC clock cycles */
+#define ADC_SAMPLETIME_11CYCLES_5        (LL_ADC_SAMPLINGTIME_11CYCLES_5)   /*!< Sampling time 11.5 ADC clock cycles */
+#define ADC_SAMPLETIME_23CYCLES_5        (LL_ADC_SAMPLINGTIME_23CYCLES_5)   /*!< Sampling time 23.5 ADC clock cycles */
+#define ADC_SAMPLETIME_46CYCLES_5        (LL_ADC_SAMPLINGTIME_46CYCLES_5)   /*!< Sampling time 46.5 ADC clock cycles */
+#define ADC_SAMPLETIME_246CYCLES_5       (LL_ADC_SAMPLINGTIME_246CYCLES_5)  /*!< Sampling time 246.5 ADC clock cycles */
+#define ADC_SAMPLETIME_1499CYCLES_5      (LL_ADC_SAMPLINGTIME_1499CYCLES_5) /*!< Sampling time 1499.5 ADC clock cycles*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on  */
+/*        all ADC instances (refer to Reference Manual).                      */
+#define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN0  */
+#define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN1  */
+#define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN2  */
+#define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN3  */
+#define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN4  */
+#define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN5  */
+#define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN6  */
+#define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN7  */
+#define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN8  */
+#define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)               /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN9  */
+#define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN10 */
+#define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN11 */
+#define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN12 */
+#define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN13 */
+#define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN14 */
+#define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN15 */
+#define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN16 */
+#define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN17 */
+#define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN18 */
+#define ADC_CHANNEL_19                     (LL_ADC_CHANNEL_19)              /*!< ADC external channel (connected to GPIO
+                                           pin) ADCx_IN19 */
+#define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)         /*!< ADC internal channel connected to
+                                           VrefInt: Internal voltage reference.
+                                           On this STM32 series, ADC channel available only on ADC instance: ADC1. */
+#define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to
+                                           Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat
+                                           always below Vdda.
+                                           On this STM32 series, ADC channel available only on ADC instance: ADC2. */
+#define ADC_CHANNEL_VDDCORE                (LL_ADC_CHANNEL_VDDCORE)         /*!< ADC internal channel connected to
+                                           VddCore.
+                                           On this STM32 series, ADC channel available only on ADC instance: ADC2. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
+  * @{
+  */
+#define ADC_CONVERSIONDATA_DR              (LL_ADC_REG_DR_TRANSFER)            /*!< ADC conversions data are available
+                                           in ADC data register only */
+#define ADC_CONVERSIONDATA_DMA_ONESHOT     (LL_ADC_REG_DMA_TRANSFER_LIMITED)   /*!< ADC conversion data are transferred
+                                           by DMA, in limited mode (one shot mode): DMA transfer requests are stopped
+                                           when number of DMA data transfers (number of ADC conversions) is reached.
+                                           This ADC mode is intended to be used with DMA mode non-circular. */
+#define ADC_CONVERSIONDATA_DMA_CIRCULAR    (LL_ADC_REG_DMA_TRANSFER_UNLIMITED) /*!< ADC conversion data are transferred
+                                           by DMA, in unlimited mode: DMA transfer requests are unlimited,
+                                           whatever number of DMA data transferred (number of ADC conversions).
+                                           This ADC mode is intended to be used with DMA mode circular. */
+#define ADC_CONVERSIONDATA_MDF             (LL_ADC_REG_MDF_TRANSFER)           /*!< ADC conversion data are transferred
+                                           to MDF */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
+  * @{
+  */
+#define ADC_AWD_FILTERING_NONE          LL_ADC_AWD_FILTERING_NONE      /*!< ADC analog watchdog no filtering,
+                                        one out-of-window sample is needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_2SAMPLES      LL_ADC_AWD_FILTERING_2SAMPLES  /*!< ADC analog watchdog 2 consecutives
+                                        out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_3SAMPLES      LL_ADC_AWD_FILTERING_3SAMPLES  /*!< ADC analog watchdog 3 consecutives
+                                        out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_4SAMPLES      LL_ADC_AWD_FILTERING_4SAMPLES  /*!< ADC analog watchdog 4 consecutives
+                                        out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_5SAMPLES      LL_ADC_AWD_FILTERING_5SAMPLES  /*!< ADC analog watchdog 5 consecutives
+                                        out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_6SAMPLES      LL_ADC_AWD_FILTERING_6SAMPLES  /*!< ADC analog watchdog 6 consecutives
+                                        out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_7SAMPLES      LL_ADC_AWD_FILTERING_7SAMPLES  /*!< ADC analog watchdog 7 consecutives
+                                        out-of-window samples are needed to raise flag or interrupt */
+#define ADC_AWD_FILTERING_8SAMPLES      LL_ADC_AWD_FILTERING_8SAMPLES  /*!< ADC analog watchdog 8 consecutives
+                                        out-of-window samples are needed to raise flag or interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                          /*!< ADC AWD not selected */
+
+#define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN)  /*!< ADC AWD applied to a
+                                                regular group single channel */
+
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         (ADC_CFGR1_AWD1SGL | ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to an
+                                                injected group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN \
+                                                 | ADC_CFGR1_JAWD1EN)                   /*!< ADC AWD applied to a
+                                                regular and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR1_AWD1EN)                      /*!< ADC AWD applied to regular
+                                                group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC            (ADC_CFGR1_JAWD1EN)                     /*!< ADC AWD applied to injected
+                                                group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         (ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN)  /*!< ADC AWD applied to regular
+                                                and injected groups all channels */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
+  * @{
+  */
+#define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift   */
+#define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
+#define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
+#define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
+#define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
+#define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
+#define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
+#define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
+#define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
+#define ADC_RIGHTBITSHIFT_9                (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling right shift of 9 ranks */
+#define ADC_RIGHTBITSHIFT_10               (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling right shift of 10 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Left_Bit_Shift   ADC Extended Oversampling left Shift
+  * @{
+  */
+#define ADC_LEFTBITSHIFT_NONE  (LL_ADC_LEFT_BIT_SHIFT_NONE)   /*!<  ADC No bit shift */
+#define ADC_LEFTBITSHIFT_1     (LL_ADC_LEFT_BIT_SHIFT_1)      /*!<  ADC 1 bit shift  */
+#define ADC_LEFTBITSHIFT_2     (LL_ADC_LEFT_BIT_SHIFT_2)      /*!<  ADC 2 bits shift */
+#define ADC_LEFTBITSHIFT_3     (LL_ADC_LEFT_BIT_SHIFT_3)      /*!<  ADC 3 bits shift */
+#define ADC_LEFTBITSHIFT_4     (LL_ADC_LEFT_BIT_SHIFT_4)      /*!<  ADC 4 bits shift */
+#define ADC_LEFTBITSHIFT_5     (LL_ADC_LEFT_BIT_SHIFT_5)      /*!<  ADC 5 bits shift */
+#define ADC_LEFTBITSHIFT_6     (LL_ADC_LEFT_BIT_SHIFT_6)      /*!<  ADC 6 bits shift */
+#define ADC_LEFTBITSHIFT_7     (LL_ADC_LEFT_BIT_SHIFT_7)      /*!<  ADC 7 bits shift */
+#define ADC_LEFTBITSHIFT_8     (LL_ADC_LEFT_BIT_SHIFT_8)      /*!<  ADC 8 bits shift */
+#define ADC_LEFTBITSHIFT_9     (LL_ADC_LEFT_BIT_SHIFT_9)      /*!<  ADC 9 bits shift */
+#define ADC_LEFTBITSHIFT_10    (LL_ADC_LEFT_BIT_SHIFT_10)     /*!<  ADC 10 bits shift */
+#define ADC_LEFTBITSHIFT_11    (LL_ADC_LEFT_BIT_SHIFT_11)     /*!<  ADC 11 bits shift */
+#define ADC_LEFTBITSHIFT_12    (LL_ADC_LEFT_BIT_SHIFT_12)     /*!<  ADC 12 bits shift */
+#define ADC_LEFTBITSHIFT_13    (LL_ADC_LEFT_BIT_SHIFT_13)     /*!<  ADC 13 bits shift */
+#define ADC_LEFTBITSHIFT_14    (LL_ADC_LEFT_BIT_SHIFT_14)     /*!<  ADC 14 bits shift */
+#define ADC_LEFTBITSHIFT_15    (LL_ADC_LEFT_BIT_SHIFT_15)     /*!<  ADC 15 bits shift */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode:
+                                           continuous mode (all conversions of OVS ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode:
+                                           discontinuous mode (each conversion of OVS ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG  Oversampling - Oversampling scope for ADC group regular
+  * @{
+  */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained
+                                           during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE   (LL_ADC_OVS_GRP_REGULAR_RESUMED)   /*!< Oversampling buffer zeroed during
+                                           injection sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Event_type ADC Event type
+  * @{
+  */
+/**
+  * @note Analog watchdog 1 is available on all stm32 series
+  *       Analog watchdog 2 and 3 are not available on all series
+  */
+#define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog)       */
+#define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
+#define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
+#define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
+/**
+  * @}
+  */
+#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility
+                                                          with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+  * @{
+  */
+#define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
+#define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog
+                             watchdog) */
+#define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog
+                             watchdog) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+  * @{
+  */
+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Verify the ADC data conversion setting.
+  * @param DATA : programmed DATA conversion mode.
+  * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
+  */
+#define IS_ADC_CONVERSIONDATAMGT(DATA)                                         \
+  ((((DATA) == ADC_CONVERSIONDATA_DR))          || \
+   (((DATA) == ADC_CONVERSIONDATA_MDF))         || \
+   (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
+   (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
+
+/**
+  * @brief Return resolution bits in CFGR register RES[1:0] field.
+  * @param __HANDLE__ ADC handle
+  * @retval Value of bitfield RES in CFGR register.
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__)                                         \
+  (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+  * @brief Verification of ADC state: enabled or disabled.
+  * @param __HANDLE__ ADC handle
+  * @retval SET (ADC enabled) or RESET (ADC disabled)
+  */
+#define ADC_IS_ENABLE(__HANDLE__)                                                     \
+  ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+    ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
+   ) ? SET : RESET)
+
+/**
+  * @brief Check if conversion is on going on regular group.
+  * @param __HANDLE__ ADC handle
+  * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
+  */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
+  (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
+
+
+/**
+  * @brief Simultaneously clear and set specific bits of the handle State.
+  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Verify that a given value is aligned with the ADC resolution range.
+  * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+  * @param __ADC_VALUE__ value checked against the resolution.
+  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+  */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+  ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/**
+  * @brief Verify the length of the scheduled regular conversions group.
+  * @param __LENGTH__ number of programmed conversions.
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
+  *         or RESET (__LENGTH__ is null or too large)
+  */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+
+
+/**
+  * @brief Verify the number of scheduled regular conversions in discontinuous mode.
+  * @param NUMBER number of scheduled regular conversions in discontinuous mode.
+  * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
+  *         or RESET (NUMBER is null or too large)
+  */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
+
+/**
+  * @brief Verify the ADC resolution setting.
+  * @param __RESOLUTION__ programmed ADC resolution.
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
+
+/**
+  * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
+  * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */
+#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
+
+/**
+  * @brief Verify the ADC gain compensation.
+  * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
+  * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
+  */
+#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 0x3FFFUL)
+
+/**
+  * @brief Verify the ADC offset.
+  * @param __OFFSET__ programmed ADC offset.
+  * @retval SET (__OFFSET__ is a valid value) or RESET (__OFFSET__ is invalid)
+  */
+#define IS_ADC_OFFSET(__OFFSET__) ((__OFFSET__) <= 0x3FFFFFUL)
+
+/**
+  * @brief Verify the ADC scan mode.
+  * @param __SCAN_MODE__ programmed ADC scan mode.
+  * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+  */
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )
+
+/**
+  * @brief Verify the ADC edge trigger setting for regular group.
+  * @param __EDGE__ programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
+
+/**
+  * @brief Verify the ADC regular conversions external trigger.
+  * @param __ADC_INSTANCE__ ADC instance
+  * @param __REG_TRIG_SOURCE__ programmed ADC regular conversions external trigger.
+  * @retval SET (__REG_TRIG_SOURCE__ is a valid value) or RESET (__REG_TRIG_SOURCE__ is invalid)
+  */
+#define IS_ADC_EXTTRIG(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)            \
+  (((__REG_TRIG_SOURCE__) == ADC_SOFTWARE_START)                         \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_EXT_IT11)               \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC1)                 \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC2)                 \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC3)                 \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T2_CC2)                 \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T2_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T3_CC4)                 \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T3_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T4_CC4)                 \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T4_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T5_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T6_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T7_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T8_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T8_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T9_CC1)                 \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T9_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T12_TRGO)               \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T15_TRGO)               \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T18_TRGO)               \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM1_CH1)             \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM2_CH1)             \
+   || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM3_CH1)             \
+  )
+
+
+/**
+  * @brief Verify the ADC regular conversions external trigger.
+  * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
+  * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
+  */
+#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL)          || \
+                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB)            || \
+                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED)  )
+
+/**
+  * @brief Verify the ADC regular conversions check for converted data availability.
+  * @param __EOC_SELECTION__ converted data availability check.
+  * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
+  */
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
+                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )
+
+/**
+  * @brief Verify the ADC regular conversions overrun handling.
+  * @param __OVR__ ADC regular conversions overrun handling.
+  * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+  */
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
+                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )
+
+/**
+  * @brief Verify the ADC conversions sampling time.
+  * @param __SAMPLING_TIME__ ADC conversions sampling time.
+  * @retval SET (__SAMPLING_TIME__ is a valid value) or RESET (__SAMPLING_TIME__ is invalid)
+  */
+#define IS_ADC_SAMPLING_TIME(__SAMPLING_TIME__) (((__SAMPLING_TIME__) == ADC_SAMPLETIME_1CYCLE_5)    || \
+                                                 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
+                                                 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
+                                                 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_11CYCLES_5)  || \
+                                                 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_23CYCLES_5)  || \
+                                                 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_46CYCLES_5)  || \
+                                                 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_246CYCLES_5) || \
+                                                 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_1499CYCLES_5)   )
+
+/**
+  * @brief Verify the ADC regular channel setting.
+  * @param  __CHANNEL__ programmed ADC regular channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Fixed timeout values for ADC conversion (including sampling time)          */
+/* Maximum sampling time is 1499.5 ADC clock cycle (SMPx[2:0] = 0b111)        */
+/* Maximum conversion time is 12.5 + Maximum samling time                     */
+/*                       or 12.5  + 1499.5 = 1512 ADC clock cycles            */
+/* Minimum ADC Clock frequency is 0.7 MHz                                     */
+/* (refer to device datasheet, parameter "fADC")                              */
+/* Maximum conversion time is                                                 */
+/*                      = 1512 / 0.7MHz = 2.16 ms                             */
+/* Used timeout value includes a margin versus theoretical max value          */
+#define ADC_STOP_CONVERSION_TIMEOUT     (5UL)    /*!< ADC stop time-out value */
+
+/* Delay for temperature sensor stabilization time.                         */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
+/* Unit: us                                                                 */
+#define ADC_TEMPSENSOR_DELAY_US         (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+
+/* Delay for ADC voltage regulator startup time                               */
+/* Maximum delay is 10 microseconds                                           */
+/* (refer device RM, parameter Tadcvreg_stup).                                */
+#define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user.                                                                */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+  * @{
+  */
+
+/** @brief  Reset ADC handle state.
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  do{                                                                          \
+    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
+    (__HANDLE__)->MspInitCallback = NULL;                                      \
+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
+  } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @brief Enable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
+  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief Disable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
+  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC interrupt source to check
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief Check whether the specified ADC flag is set or not.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  * @retval State of flag (TRUE or FALSE).
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Clear the specified ADC flag.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  * @retval None
+  */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
+  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals ADC_CHANNEL_x.
+  * @note   Example:
+  *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  *         @arg @ref ADC_CHANNEL_VREFINT     (1)(4)
+  *         @arg @ref ADC_CHANNEL_VBAT        (2)(4)
+  *         @arg @ref ADC_CHANNEL_VDDCORE     (2)(4)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
+  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  *         @arg @ref ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
+  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           ADC_CHANNEL_VREFINT, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...),
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  *         @arg @ref ADC_CHANNEL_VREFINT     (1)(4)
+  *         @arg @ref ADC_CHANNEL_VBAT        (2)(4)
+  *         @arg @ref ADC_CHANNEL_VDDCORE     (2)(4)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+  *         (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
+  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (ADC_CHANNEL_VREFINT, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  *         @arg @ref ADC_CHANNEL_VREFINT     (1)(4)
+  *         @arg @ref ADC_CHANNEL_VBAT        (2)(4)
+  *         @arg @ref ADC_CHANNEL_VDDCORE     (2)(4)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
+  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
+  __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
+  __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value
+  */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                          __ADC_RESOLUTION_CURRENT__,\
+                                          __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+                                 (__ADC_RESOLUTION_CURRENT__),\
+                                 (__ADC_RESOLUTION_TARGET__))
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                       __ADC_DATA__,\
+                                       __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+                              (__ADC_DATA__),\
+                              (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value)
+  *         in differential ended mode.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                            __ADC_DATA__,\
+                                            __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+                                   (__ADC_DATA__),\
+                                   (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                          __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+                                 (__ADC_RESOLUTION__))
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include ADC HAL Extended module */
+#include "stm32n6xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions  *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
+int32_t                 HAL_ADC_GetSignedValue(const ADC_HandleTypeDef *hadc);
+
+/* ADC sampling control */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig);
+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
+                                                const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
+
+/**
+  * @}
+  */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+uint32_t                HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_ADC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_adc_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_adc_ex.h
new file mode 100644
index 000000000..e6faf79a6
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_adc_ex.h
@@ -0,0 +1,1324 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_adc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_ADC_EX_H
+#define STM32N6xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC Injected Conversion Oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value from 1 to 1024 */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+} ADC_InjOversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
+  *                           InjectedOffsetNumber, InjectedOffset
+  *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
+  *            InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConv,
+  *            ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
+  * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
+  *                               'InjectedSingleDiff')
+  *          - For parameters 'InjectedDiscontinuousConvMode', 'InjecOversampling':
+  *                           ADC enabled without conversion on going on injected group.
+  *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv':
+  *                           ADC enabled without conversion on going on regular and injected groups.
+  *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
+  *                           'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on ADC groups
+  *                            regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+                                               Note: Depending on devices and ADC instances, some channels may not be
+                                                     available on device package pins. Refer to device datasheet for
+                                                     channels availability. */
+
+  uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
+                                               This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
+                                               Note: to disable a channel or change order of conversion sequencer,
+                                                     rank containing a previous channel setting can be overwritten by
+                                                     the new channel setting (or parameter number of conversions
+                                                     adjusted) */
+
+  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
+                                               Unit: ADC clock cycles.
+                                               Conversion time is the addition of sampling time and processing time
+                                               (13.5 ADC clock cycles at ADC resolution 12 bits, 11.5 cycles at 10 bits,
+                                               8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
+                                               Caution: This parameter applies to a channel that can be used in a
+                                                        regular and/or injected group.
+                                                        It overwrites the last setting.
+                                               Note: In case of usage of internal measurement channels
+                                                    (VrefInt/Vbat/TempSensor), sampling time constraints must be
+                                                    respected (sampling time can be adjusted in function of ADC clock
+                                                    frequency and sampling time setting);
+                                                    Refer to device datasheet for timings values. */
+  uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
+                                               In differential mode: Differential measurement is carried out between
+                                                                     the selected channel (positive input) and
+                                                                     another channel (negative input). Refer to
+                                                                     reference manual for corresponding channel.
+                                                                     Only channel of positive input has to be
+                                                                     configured, the other channel is configured
+                                                                     automatically.
+                                               This parameter must be a value of:
+                                                    @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
+                                               Caution: This parameter applies to a channel that can be used in a
+                                                        regular and/or injected group. It overwrites the last setting.
+                                               Note: Refer to Reference Manual to ensure the selected channel is
+                                                     available in differential mode.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC
+                                                     start conversion or after ADC stop conversion).
+                                               If ADC is enabled, this parameter setting is bypassed without error
+                                               reporting (as it can be the expected behavior in case of another
+                                               parameter update on the fly) */
+
+  uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
+                                               Caution: Only one offset is allowed per channel. This parameter
+                                               overwrites the last setting. */
+
+  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
+                                               Offset value must be a positive number.
+                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
+                                               parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
+                                               0x3FF, 0xFF or 0x3F respectively.
+                                               Note: This parameter must be modified when no conversion is on going on
+                                                     both regular and injected groups (ADC disabled, or ADC enabled
+                                                     without continuous mode or external trigger that could launch a
+                                                     conversion). */
+
+  FunctionalState InjectedOffsetSignedSaturation;  /*!< Specifies whether the Signed saturation feature is used or not.
+                                                        This parameter is applied only for 14-bit or 8-bit resolution.
+                                                        This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t InjectedOffsetSign;            /*!< Define if the offset should be subtracted (negative sign) or added
+                                               (positive sign) from or to the raw converted data.
+                                               This parameter can be a value of @ref ADCEx_OffsetSign.
+                                               Note:
+                                                 - This parameter must be modified when no conversion is on going on
+                                                   both regular and injected groups (ADC disabled or ADC enabled without
+                                                   continuous mode or external trigger that could launch a conversion).
+                                                 - This parameter is specific to ADC1 only. */
+
+  FunctionalState InjectedOffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
+                                               This parameter value can be ENABLE or DISABLE.
+                                               Note: This parameter must be modified when no conversion is on going
+                                                     on both regular and injected groups (ADC disabled, or ADC enabled
+                                                     without continuous mode or external trigger that could launch
+                                                     a conversion). */
+
+  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within
+                                               the ADC group injected sequencer.
+                                               To use the injected group sequencer and convert several ranks,
+                                               parameter 'ScanConvMode' must be enabled.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                               Caution: this setting impacts the entire injected group.
+                                                        Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the
+                                                        configuration of other channels previously set. */
+
+  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
+                                                      is performed in Complete-sequence/Discontinuous-sequence
+                                                      (main sequence subdivided in successive parts).
+                                                      Discontinuous mode is used only if sequencer is enabled
+                                                      (parameter 'ScanConvMode').
+                                                      If sequencer is disabled, this parameter is discarded.
+                                                      Discontinuous mode can be enabled only if continuous
+                                                      mode is disabled.
+                                                      This parameter can be set to ENABLE or DISABLE.
+                                                      Note: This parameter must be modified when ADC is disabled
+                                                           (before ADC start conversion or after ADC stop conversion).
+                                                      Note: For injected group, discontinuous mode converts the
+                                                            sequence channel by channel (discontinuous length
+                                                            fixed to 1 rank).
+                                                      Caution: this setting impacts the entire injected group.
+                                                               Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                               configure a channel on injected group can impact the
+                                                               configuration of other channels previously set. */
+
+  FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion
+                                               after regular one
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: To use Automatic injected conversion, discontinuous mode must be
+                                                     disabled ('DiscontinuousConvMode' and
+                                                     'InjectedDiscontinuousConvMode' set to DISABLE)
+                                               Note: To use Automatic injected conversion, injected group external
+                                                     triggers must be disabled ('ExternalTrigInjecConv' set to
+                                                     ADC_INJECTED_SOFTWARE_START)
+                                               Note: In case of DMA used with regular group: if DMA configured in normal
+                                                     mode (single shot) JAUTO will be stopped upon DMA transfer
+                                                     complete. To maintain JAUTO always enabled,
+                                                     DMA must be configured in circular mode.
+                                               Caution: this setting impacts the entire injected group.
+                                                        Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the
+                                                        configuration of other channels previously set. */
+
+  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of
+                                               injected group.
+                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
+                                               and software trigger is used instead.
+                                               This parameter can be a value of
+                                               @ref ADC_injected_external_trigger_source.
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                                        call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
+                                                        on injected group can impact the configuration of other channels
+                                                        previously set. */
+
+  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
+                                               This parameter can be a value of @ref ADC_injected_external_trigger_edge.
+                                               If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
+                                               is discarded.
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                                        call of  HAL_ADCEx_InjectedConfigChannel() to configure a
+                                                        channel on injected group can impact the configuration of other
+                                                        channels previously set. */
+
+  FunctionalState InjecOversamplingMode;        /*!< Specifies whether the oversampling feature is enabled or disabled.
+                                                     This parameter can be set to ENABLE or DISABLE.
+                                                     Note: This parameter can be modified only if there is no conversion
+                                                           is ongoing (both ADSTART and JADSTART cleared). */
+
+  ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
+                                                      Caution: this setting overwrites the previous oversampling
+                                                               configuration if oversampling already enabled.
+                                                      Note: This parameter can be modified only if there is no
+                                                            conversion is ongoing (both ADSTART and
+                                                            JADSTART cleared).*/
+} ADC_InjectionConfTypeDef;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Structure definition of ADC multimode
+  * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs
+  *         state (both Master and Slave ADCs).
+  *         Both Master and Slave ADCs must be disabled.
+  */
+typedef struct
+{
+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
+
+  uint32_t DualModeData;      /*!< Configures the Dual ADC Mode Data Format:
+                                   This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
+
+  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY */
+} ADC_MultiModeTypeDef;
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)           /*!< ADC group injected conversion
+                                           trigger internal: SW start. */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)    /*!< ADC group injected conversion
+                                           trigger from external peripheral: external interrupt line 15. */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM1 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM1 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM1 TRGO2 event. */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM2 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM2 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM4 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T5_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM5_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM5 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM6 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T7_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM7 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM8 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM8 TRGO2 event. */
+#define ADC_EXTERNALTRIGINJEC_T9_CC2       (LL_ADC_INJ_TRIG_EXT_TIM9_CH2)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM9 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T9_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM9_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM9 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T12_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM12_TRGO)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM12 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T12_CC4      (LL_ADC_INJ_TRIG_EXT_TIM12_CH4)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM12 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM12 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_T18_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM18_TRGO)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM12 TRGO event. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM1_CH2   (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: LPTIM1 channel 2 event. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM2_CH2   (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: LPTIM2 channel 2 event. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM3_CH2   (LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: LPTIM3 channel 2 event. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions trigger
+                                                      disabled (SW start)*/
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions trigger
+                                                      polarity set to rising edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions trigger
+                                                      polarity set to falling edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions trigger
+                                                      polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+  * @{
+  */
+#define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)           /*!< ADC channel ending set to single ended */
+#define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)     /*!< ADC channel ending set to differential */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number
+  * @{
+  */
+#define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
+                                     ADC channel */
+#define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+#define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+#define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+#define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
+  * @{
+  */
+#define ADC_OFFSET_SIGN_NEGATIVE      LL_ADC_OFFSET_SIGN_NEGATIVE   /*!< Offset sign negative, offset is subtracted */
+#define ADC_OFFSET_SIGN_POSITIVE      LL_ADC_OFFSET_SIGN_POSITIVE   /*!< Offset sign positive, offset is added  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
+#define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
+#define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
+#define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
+/**
+  * @}
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_HAL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define ADC_MODE_INDEPENDENT               (LL_ADC_MULTI_INDEPENDENT)          /*!< ADC dual mode disabled
+                                           (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT             (LL_ADC_MULTI_DUAL_REG_SIMULT)      /*!< ADC dual mode enabled: group regular
+                                           simultaneous */
+#define ADC_DUALMODE_INTERL                (LL_ADC_MULTI_DUAL_REG_INTERL)      /*!< ADC dual mode enabled: Combined
+                                           group regular interleaved */
+#define ADC_DUALMODE_INJECSIMULT           (LL_ADC_MULTI_DUAL_INJ_SIMULT)      /*!< ADC dual mode enabled: group
+                                           injected simultaneous */
+#define ADC_DUALMODE_ALTERTRIG             (LL_ADC_MULTI_DUAL_INJ_ALTERN)      /*!< ADC dual mode enabled: group
+                                           injected alternate trigger. Works only with external triggers (not internal
+                                           SW start) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
+                                           group regular simultaneous + group injected simultaneous */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG   (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
+                                           group regular simultaneous + group injected alternate trigger */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
+                                           group regular interleaved + group injected simultaneous */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
+  * @{
+  */
+
+#define ADC_DUALMODEDATAFORMAT_DISABLED    (LL_ADC_MULTI_REG_DATA_EACH_ADC)    /*!< ADC multimode group regular data
+                                           format: conversion data in data register of each ADC instance.
+                                           If ADC data transfer by DMA is used: each ADC uses its own DMA channel,
+                                           with its individual DMA transfer settings. */
+#define ADC_DUALMODEDATAFORMAT_32_BIT      (LL_ADC_MULTI_REG_DATA_COMMON_32B)  /*!< ADC multimode group regular data
+                                           format: conversion data in two ADC common instance data registers (CDR, CDR2)
+                                           with packing option on 32 bit. In register CDR, data packing on 32 bit:
+                                           ADC master and slave data are concatenated (data master in [15; 0],
+                                           data slave in [31; 16]), therefore data width must be lower than 16 bit
+                                           (even with ADC resolution 12 bit, higher width reachable by post processing:
+                                           oversampling, offset, ...). In register CDR2, data of master and slave are
+                                           alternatively set in full register width 32 bit, therefore no constraint on
+                                           data width. In case of usage with DMA, CDR generate ones transfer request
+                                           and CDR2 two transfer requests per conversion. */
+#define ADC_DUALMODEDATAFORMAT_8_BIT       (LL_ADC_MULTI_REG_DATA_COMMON_16B)  /*!< ADC multimode group regular data
+                                           format: conversion data in two ADC common instance data registers (CDR, CDR2)
+                                           with packing option on 16 bit. In register CDR, data packing on 16 bit:
+                                           ADC master and slave data are concatenated (data master in [7; 0],
+                                           data slave in [15; 8]), therefore data width must be lower than 8 bit
+                                           (even with ADC resolution 8 bit, higher width reachable by post processing:
+                                           oversampling, offset, ...). In register CDR2, data of master and slave are
+                                           alternatively set in full register width 32 bit, therefore no constraint on
+                                           data width. In case of usage with DMA, CDR generate ones transfer request
+                                           and CDR2 two transfer requests per conversion. */
+
+/* Legacy literals */
+#define ADC_DUALMODEDATAFORMAT_32_10_BITS ADC_DUALMODEDATAFORMAT_32_BIT
+#define ADC_DUALMODEDATAFORMAT_8_BITS     ADC_DUALMODEDATAFORMAT_8_BIT
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE        (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)    /*!< ADC multimode delay between two
+                                           sampling phases: 1 ADC clock cycle */
+#define ADC_TWOSAMPLINGDELAY_2CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 2 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_3CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 3 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_4CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 4 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 5 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_6CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 6 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_7CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 7 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_8CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 8 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_9CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 9 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_10CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)  /*!< ADC multimode delay between two
+                                           sampling phases: 10 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_11CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)  /*!< ADC multimode delay between two
+                                           sampling phases: 11 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_12CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)  /*!< ADC multimode delay between two
+                                           sampling phases: 12 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_13CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES)  /*!< ADC multimode delay between two
+                                           sampling phases: 13 ADC clock cycles */
+/**
+  * @}
+  */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)          /*!< ADC group regular (available on
+                                                                                all STM32 devices) */
+#define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)         /*!< ADC group injected (not available on
+                                                                                all STM32 devices) */
+#define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CFGR1_fields ADCx CFGR fields
+  * @{
+  */
+#define ADC_CFGR1_FIELDS    (ADC_CFGR1_AWD1CH  | ADC_CFGR1_JAUTO   | ADC_CFGR1_JAWD1EN |\
+                             ADC_CFGR1_AWD1EN  | ADC_CFGR1_AWD1SGL | \
+                             ADC_CFGR1_JDISCEN | ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN  |\
+                             ADC_CFGR1_AUTDLY  | ADC_CFGR1_CONT    | ADC_CFGR1_OVRMOD  |\
+                             ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL  | ADC_CFGR1_ALIGN   |\
+                             ADC_CFGR1_RES     | ADC_CFGR1_DMACFG  | ADC_CFGR1_DMAEN   )
+/**
+  * @}
+  */
+
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+  * @{
+  */
+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+                             ADC_SMPR1_SMP0)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CFGR1_fields_2 ADCx CFGR sub fields
+  * @{
+  */
+/* ADC_CFGR1 fields of parameters that can be updated when no conversion
+   (neither regular nor injected) is on-going  */
+#define ADC_CFGR1_FIELDS_2  ((uint32_t)(ADC_CFGR1_DMNGT | ADC_CFGR1_AUTDLY))
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+  * @{
+  */
+#if defined(ADC_MULTIMODE_SUPPORT)
+
+/** @brief  Force ADC instance in multimode mode independent (multimode disable).
+  * @note   This macro must be used only in case of transition from multimode
+  *         to mode independent and in case of unknown previous state,
+  *         to ensure ADC configuration is in mode independent.
+  * @note   Standard way of multimode configuration change is done from
+  *         HAL ADC handle of ADC master using function
+  *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+  *         Usage of this macro is not the Standard way of multimode
+  *         configuration and can lead to have HAL ADC handles status
+  *         misaligned. Usage of this macro must be limited to cases
+  *         mentioned above.
+  * @param __HANDLE__ ADC handle.
+  * @retval None
+  */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \
+  LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Helper macro to determine the selected channel corresponding
+  *         negative input on the ADC instance selected.
+  * @param __HANDLE__ ADC handle.
+  * @param __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  *         @arg @ref ADC_CHANNEL_VREFINT     (1)(4)
+  *         @arg @ref ADC_CHANNEL_VBAT        (2)(4)
+  *         @arg @ref ADC_CHANNEL_VDDCORE     (2)(4)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  *         @arg @ref ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __HAL_ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__)              \
+  ((IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) != 0UL)                            \
+   ? __LL_ADC_CHANNEL_DIFF_NEG_INPUT((__HANDLE__)->Instance, __CHANNEL__)      \
+   : (ADC_CHANNEL_NONE)                                                        \
+  )
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Test if conversion trigger of injected group is software start
+  *        or external trigger.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (software start) or RESET (external trigger).
+  */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
+  (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
+
+/**
+  * @brief Check if conversion is on going on regular or injected groups.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (conversion is on going) or RESET (no conversion is on going).
+  */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                  \
+  (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \
+   ) ? RESET : SET)
+
+/**
+  * @brief Check if conversion is on going on injected group.
+  * @param __HANDLE__ ADC handle.
+  * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
+  */
+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                         \
+  (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
+
+/**
+  * @brief Check whether or not ADC is independent.
+  * @param __HANDLE__ ADC handle.
+  * @note  When multimode feature is not available, the macro always returns SET.
+  * @retval SET (ADC is independent) or RESET (ADC is not).
+  */
+#define ADC_IS_INDEPENDENT(__HANDLE__)    \
+  ( ( ( ((__HANDLE__)->Instance) == ADC3) \
+    )?                                    \
+    SET                                   \
+    :                                     \
+    RESET                                 \
+  )
+
+/**
+  * @brief Set the selected injected Channel rank.
+  * @param __CHANNELNB__ Channel number.
+  * @param __RANKNB__ Rank number.
+  * @retval None
+  */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) (((__CHANNELNB__)& ADC_CHANNEL_NUMBER_MASK)  \
+                                                << ((__RANKNB__)  & ADC_INJ_RANK_ID_JSQR_MASK))
+
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for injected group
+  * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR1_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__)\
+  ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR1_JDISCEN_Pos)
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for regular group
+  * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR1_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR1_DISCEN_Pos)
+
+/**
+  * @brief Configure the number of discontinuous conversions for regular group.
+  * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
+  * @retval None
+  */
+#define ADC_CFGR1_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__)\
+  (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR1_DISCNUM_Pos)
+
+/**
+  * @brief Configure the ADC auto delay mode.
+  * @param __AUTDLY__ Auto delay bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR1_AUTODELAY(__AUTDLY__) ((__AUTDLY__) << ADC_CFGR1_AUTDLY_Pos)
+
+/**
+  * @brief Configure ADC continuous conversion mode.
+  * @param __CONTINUOUS_MODE__ Continuous mode.
+  * @retval None
+  */
+#define ADC_CFGR1_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR1_CONT_Pos)
+
+/**
+  * @brief Enable the ADC DMA continuous request.
+  * @param __DMACONTREQ_MODE__: DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CFGR1_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
+
+/**
+  * @brief Configure the channel number into offset OFRx register.
+  * @param __CHANNEL__ ADC Channel.
+  * @retval None
+  */
+#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFCFGR1_OFFSET1_CH_Pos)
+
+/**
+  * @brief Configure the channel number into differential mode selection register.
+  * @param __CHANNEL__ ADC Channel.
+  * @retval None
+  */
+#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
+
+/**
+  * @brief Configure calibration factor in differential mode to be set into calibration register.
+  * @param __CALIBRATION_FACTOR__ Calibration factor value.
+  * @retval None
+  */
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__)\
+  (((__CALIBRATION_FACTOR__)& (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) )\
+   << ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+  * @brief Calibration factor in differential mode to be retrieved from calibration register.
+  * @param __CALIBRATION_FACTOR__ Calibration factor value.
+  * @retval None
+  */
+#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+  * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+  * @param __THRESHOLD__ Threshold value.
+  * @retval None
+  */
+#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief Configure the ADC DMA continuous request for ADC multimode.
+  * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief Shift the offset with respect to the selected ADC resolution.
+  * @note  Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the left.
+  *        If resolution 8 bits, shift of 4 ranks on the left.
+  *        If resolution 6 bits, shift of 6 ranks on the left.
+  *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 2)*2)).
+  * @param __HANDLE__ ADC handle
+  * @param __OFFSET__ Value to be shifted
+  * @retval None
+  */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)                                                     \
+  (((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)>> 2UL)*2UL)))
+
+/**
+  * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
+  * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the left.
+  *        If resolution 8 bits, shift of 4 ranks on the left.
+  *        If resolution 6 bits, shift of 6 ranks on the left.
+  *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 2)*2)).
+  * @param __HANDLE__ ADC handle
+  * @param __THRESHOLD__ Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+  ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 2UL) * 2UL))
+
+/**
+  * @brief Clear Common Control Register.
+  * @param __HANDLE__ ADC handle.
+  * @retval None
+  */
+/**
+  * @brief Report common register to ADC1 and ADC2
+  * @param __HANDLE__: ADC handle
+  * @retval Common control register
+  */
+#define ADC12_COMMON_REGISTER(__HANDLE__)   (ADC12_COMMON)
+/**
+  * @brief Report common register to ADC3
+  * @param __HANDLE__: ADC handle
+  * @retval Common control register
+  */
+#define ADC3_COMMON_REGISTER(__HANDLE__)   (ADC3_COMMON)
+
+/**
+  * @brief Report Master Instance
+  * @param __HANDLE__: ADC handle
+  * @note return same instance if ADC of input handle is independent ADC
+  * @retval Master Instance
+  */
+#define ADC_MASTER_REGISTER(__HANDLE__)                                          \
+  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
+    )?                                                                           \
+    ((__HANDLE__)->Instance)                                                    \
+    :                                                                           \
+    (ADC1)                                                                      \
+  )
+
+/**
+  * @brief Check whether or not dual regular conversions are enabled
+  * @param __HANDLE__: ADC handle
+  * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions
+  * are enabled)
+  */
+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)                        \
+  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+    )?                                                                           \
+    ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&        \
+      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&        \
+      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )           \
+    :                                                                            \
+    RESET                                                                        \
+  )
+
+/**
+  * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle
+  *        of ADC master
+  * @param __HANDLE__: ADC handle
+  * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
+  */
+#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                      \
+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)     \
+    )?                                                                         \
+    SET                                                                        \
+    :                                                                          \
+    ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET)                              \
+  )
+
+/**
+  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
+  * @param __HANDLE__: ADC handle
+  * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with
+  *         dual regular conversions enabled)
+  */
+
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
+    )?                                                                      \
+    SET                                                                     \
+    :                                                                       \
+    ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     ||   \
+      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) ||   \
+      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
+
+/**
+  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
+  * @param __HANDLE__: ADC handle
+  * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with
+  *         dual injected conversions enabled)
+  */
+
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)          \
+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
+    )?                                                                     \
+    SET                                                                    \
+    :                                                                      \
+    ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    ||   \
+      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  ||   \
+      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
+
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__)                      \
+  CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR,         \
+            ADC_CCR_VBATEN                                               | \
+            ADC_CCR_VREFEN )
+
+/**
+  * @brief Set handle instance of the ADC slave associated to the ADC master.
+  * @param __HANDLE_MASTER__ ADC master handle.
+  * @param __HANDLE_SLAVE__ ADC slave handle.
+  * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC,
+  *          __HANDLE_SLAVE__ instance is set to NULL.
+  * @retval None
+  */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
+  ((((__HANDLE_MASTER__)->Instance == ADC1))                             \
+   ? ((__HANDLE_SLAVE__)->Instance = ADC2)                               \
+   : ((__HANDLE_SLAVE__)->Instance = NULL))
+
+
+/**
+  * @brief Verify the ADC instance connected to the battery voltage VBAT.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC2))
+
+/**
+  * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+
+/**
+  * @brief Verify the ADC instance connected to the internal VDDCore.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#define ADC_VDDCORE_INSTANCE(__HANDLE__)  ((((__HANDLE__)->Instance) == ADC2) )
+
+/**
+  * @brief Verify the length of scheduled injected conversions group.
+  * @param __LENGTH__ number of programmed conversions.
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or
+  *         RESET (__LENGTH__ is null or too large)
+  */
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+
+/**
+  * @brief Calibration factor value range verification.
+  * @param __CALIBRATION_FACTOR__ Calibration factor value.
+  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+  */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x1FFU))
+
+
+/**
+  * @brief Verify the ADC channel setting.
+  * @param __HANDLE__ ADC handle.
+  * @param __CHANNEL__ programmed ADC channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_1)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_2)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_3)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_4)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_5)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_6)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_7)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_8)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_9)          || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_10)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_11)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_12)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_13)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_14)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_15)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_16)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_17)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_18)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_19)         || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_VBAT)       || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_VDDCORE)    || \
+                                                 ((__CHANNEL__) == ADC_CHANNEL_VREFINT)      )
+
+/**
+  * @brief Verify the ADC channel differential mode availability.
+  * @param __HANDLE__ ADC handle.
+  * @param __CHANNEL__ ADC channel
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \
+  (__HAL_ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) != ADC_CHANNEL_NONE)
+
+/**
+  * @brief Verify the ADC single-ended input or differential mode setting.
+  * @param __SING_DIFF__ programmed channel setting.
+  * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+  */
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
+                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
+
+/**
+  * @brief Verify the ADC offset sign setting.
+  * @param __OFFSET_SIGN__ ADC offset sign.
+  * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
+  */
+#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
+                                             ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE)    )
+/**
+  * @brief Verify the ADC offset management setting.
+  * @param __OFFSET_NUMBER__ ADC offset management.
+  * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
+  */
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
+
+/**
+  * @brief Verify the ADC injected channel setting.
+  * @param __CHANNEL__ programmed ADC injected channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
+
+/**
+  * @brief Verify the ADC injected conversions external trigger.
+  * @param __ADC_INSTANCE__ ADC instance
+  * @param __INJ_TRIG_SOURCE__ programmed ADC injected conversions external trigger.
+  * @retval SET (__INJ_TRIG_SOURCE__ is a valid value) or RESET (__INJ_TRIG_SOURCE__ is invalid)
+  */
+#define IS_ADC_EXTTRIGINJEC(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == ADC_INJECTED_SOFTWARE_START)                \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)          \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_CC4)            \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)          \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T2_CC1)            \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC1)            \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC3)            \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_CC4)            \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T5_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)          \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T9_CC2)            \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T9_TRGO)           \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T12_TRGO)          \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)          \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_T18_TRGO)          \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH2)        \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH2)        \
+   || ((__INJ_TRIG_SOURCE__) == ADC_EXTERNALTRIGINJEC_LPTIM3_CH2)        \
+  )
+
+/**
+  * @brief Verify the ADC edge trigger setting for injected group.
+  * @param __EDGE__ programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief Verify the ADC multimode setting.
+  * @param __MODE__ programmed ADC multimode setting.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
+                                    ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
+                                    ((__MODE__) == ADC_DUALMODE_INTERL)                || \
+                                    ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
+
+/**
+  * @brief Verify the ADC dual data mode setting.
+  * @param MODE: programmed ADC dual mode setting.
+  * @retval SET (MODE is valid) or RESET (MODE is invalid)
+  */
+#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \
+                                     ((MODE) == ADC_DUALMODEDATAFORMAT_32_BIT)   || \
+                                     ((MODE) == ADC_DUALMODEDATAFORMAT_8_BIT)      )
+
+/**
+  * @brief Verify the ADC multimode delay setting.
+  * @param __DELAY__ programmed ADC multimode delay setting.
+  * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+  */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES)   )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief Verify the ADC analog watchdog setting.
+  * @param __WATCHDOG__ programmed ADC analog watchdog setting.
+  * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
+
+/**
+  * @brief Verify the ADC analog watchdog mode setting.
+  * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
+  * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)           || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)     || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)|| \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)        || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)      || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)     )
+
+/**
+  * @brief Verify the ADC analog watchdog filtering setting.
+  * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
+  * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__)  \
+  (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE)     ||   \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES)  ||   \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES)  ||   \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES)  ||   \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES)  ||   \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES)  ||   \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES)  ||   \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES)    )
+
+
+/**
+  * @brief Verify the ADC conversion (regular or injected or both).
+  * @param __CONVERSION__ ADC conversion group.
+  * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+  */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
+                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
+                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
+
+/**
+  * @brief Verify the ADC event type.
+  * @param __EVENT__ ADC event.
+  * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+  */
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
+                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
+                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
+                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
+                                      ((__EVENT__) == ADC_OVR_EVENT)  )
+
+/**
+  * @brief Verify the ADC oversampling ratio.
+  * @param __RATIO__: programmed ADC oversampling ratio.
+  * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+  */
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)  (((__RATIO__) >= 1UL) && ((__RATIO__) <= 1024UL))
+
+/**
+  * @brief Verify the ADC oversampling shift.
+  * @param __SHIFT__ programmed ADC oversampling shift.
+  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+  */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_9   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_10  ))
+
+/**
+  * @brief Verify the ADC oversampling triggered mode.
+  * @param __MODE__ programmed ADC oversampling triggered mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+/**
+  * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
+  * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+uint32_t                HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+                                                       uint32_t CalibrationFactor);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* ADC multimode */
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+int32_t                 HAL_ADCEx_InjectedGetSignedValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+
+/* ADC group regular conversions stop */
+HAL_StatusTypeDef       HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef       HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+                                                        const ADC_InjectionConfTypeDef *pConfigInjected);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
+                                                         const ADC_MultiModeTypeDef *pMultimode);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_ADC_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_bsec.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_bsec.h
new file mode 100644
index 000000000..f9a0897e6
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_bsec.h
@@ -0,0 +1,452 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_bsec.h
+  * @author  MCD Application Team
+  * @brief   Header file of BSEC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_BSEC_H
+#define STM32N6xx_HAL_BSEC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup BSEC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup BSEC_Exported_Types BSEC Exported Types
+ * @{
+ */
+
+/**
+  * @brief  HAL BSEC Handle Structure definition
+  */
+typedef struct
+{
+  BSEC_TypeDef *Instance; /*!< BSEC registers base address                     */
+  uint32_t     ErrorCode; /*!< Error code in case of HAL driver internal error */
+} BSEC_HandleTypeDef;
+
+/**
+  * @brief  HAL BSEC Scratch and Write Once Scratch Register Structure definition
+  */
+typedef struct
+{
+  uint32_t RegType;    /*!< Type of the register
+                            This parameter can be a value of @ref BSEC_Register_Type                         */
+  uint32_t RegNumber;  /*!< Number of the register
+                            This parameter can be a value between 0 and 3 if RegType is HAL_BSEC_SCRATCH_REG
+                            and between 0 and 7 if RegType is HAL_BSEC_WRITE_ONCE_SCRATCH_REG                */
+} BSEC_ScratchRegTypeDef;
+
+/**
+  * @brief  HAL BSEC Debug configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t HDPL_Open_Dbg;    /*!< Level at which debug may be opened
+                                  This parameter can be a value of @ref BSEC_Open_Dbg        */
+  uint32_t Sec_Dbg_Auth;     /*!< Secure debug authorization
+                                  This parameter can be a value of @ref BSEC_Sec_Dbg_Auth    */
+  uint32_t NonSec_Dbg_Auth;  /*!< Non-secure debug authorization
+                                  This parameter can be a value of @ref BSEC_NonSec_Dbg_Auth */
+} BSEC_DebugCfgTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BSEC_Exported_Constants BSEC Exported Constants
+  * @{
+  */
+
+/** @defgroup BSEC_Error_Code BSEC Error code
+  * @{
+  */
+#define HAL_BSEC_ERROR_NONE             (0U)         /*!< No error                                 */
+#define HAL_BSEC_ERROR_INVALID_PARAM    (1U)         /*!< Parameter error                          */
+#define HAL_BSEC_ERROR_UNDEFINED_VALUE  (2U)         /*!< Undefined value error                    */
+#define HAL_BSEC_ERROR_LOCK             (4U)         /*!< Locked operation error                   */
+#define HAL_BSEC_ERROR_UNALLOWED        (8U)         /*!< Not possible operation error             */
+#define HAL_BSEC_ERROR_TIMEOUT          (10U)        /*!< Timeout error                            */
+
+#define HAL_BSEC_ERROR_PROGFAIL         BSEC_OTPSR_PROGFAIL  /*!< Programming failed                       */
+#define HAL_BSEC_ERROR_DISTURB          BSEC_OTPSR_DISTURBF  /*!< Disturb flag (unexpected error)          */
+#define HAL_BSEC_ERROR_DED              BSEC_OTPSR_DEDF      /*!< Double error detection flag              */
+#define HAL_BSEC_ERROR_SEC              BSEC_OTPSR_SECF      /*!< Single error detection flag              */
+#define HAL_BSEC_ERROR_PPL              BSEC_OTPSR_PPLF      /*!< Permanent programming lock flag          */
+#define HAL_BSEC_ERROR_PPLM             BSEC_OTPSR_PPLMF     /*!< Permanent programming lock mismatch flag */
+#define HAL_BSEC_ERROR_AME              BSEC_OTPSR_AMEF      /*!< Addresses mismatch error flag            */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Global_Lock BSEC Global write lock
+  * @{
+  */
+#define HAL_BSEC_WRITE_REG_ALLOWED  (0U)      /*!< Write to BSEC registers are allowed */
+#define HAL_BSEC_WRITE_REG_IGNORED  BSEC_LOCKR_GWLOCK  /*!< Write to BSEC registers are ignored */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Status BSEC Peripheral status
+  * @{
+  */
+#define HAL_BSEC_INIT_DONE           BSEC_OTPSR_INIT_DONE  /*!< BSEC initialized following a cold or warm reset   */
+#define HAL_BSEC_UPPER_FUSES_HIDDEN  BSEC_OTPSR_HIDEUP     /*!< Upper fuses are not accessible to the application */
+#define HAL_BSEC_OTP_NOT_VIRGIN      BSEC_OTPSR_OTPNVIR    /*!< BSEC is not virgin                                */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Permanent_Lock BSEC Permanent lock
+  * @{
+  */
+#define HAL_BSEC_NORMAL_PROG  (0U)      /*!< Fuse word is programmed normally                      */
+#define HAL_BSEC_LOCK_PROG    BSEC_OTPCR_PPLOCK  /*!< Fuse word is locked, preventing further modifications */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Reload_Validity BSEC Validity of shadow register reload
+  * @{
+  */
+#define HAL_BSEC_RELOAD_ERROR          (0U)  /*!< An error occurred while fuse word was last reloaded */
+#define HAL_BSEC_RELOAD_DONE           (1U)  /*!< Last reload of fuse word was done without error     */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_State BSEC State
+  * @{
+  */
+#define HAL_BSEC_FUSE_PROG_LOCKED      (0x00000001U)        /*!< Fuse word programming is silently ignored until next reset               */
+#define HAL_BSEC_FUSE_WRITE_LOCKED     (0x00000002U)        /*!< Shadow register writing is silently ignored until next reset             */
+#define HAL_BSEC_FUSE_RELOAD_LOCKED    (0x00000004U)        /*!< Fuse word loading is denied until next reset                             */
+#define HAL_BSEC_FUSE_LOCKED           (0x00000008U)        /*!< Fuse word is locked, preventing further modifications                    */
+#define HAL_BSEC_FUSE_SHADOWED         (0x00000100U)        /*!< Fuse word is shadowed                                                    */
+#define HAL_BSEC_FUSE_HIDDEN           (0x00000200U)        /*!< Fuse word is hidden                                                      */
+#define HAL_BSEC_FUSE_ERROR_DETECTED   BSEC_OTPSR_OTPERR  /*!< At least one error is detected during reset operations                   */
+#define HAL_BSEC_FUSE_ERROR_CORRECTED  BSEC_OTPSR_OTPSEC  /*!< At least one single-error correction is detected during reset operations */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Lifecycle_State BSEC Device lifecycle state
+  * @{
+  */
+#define HAL_BSEC_OPEN_STATE                 (0x16U << BSEC_SR_NVSTATE_Pos)  /*!< BSEC is in open state                                              */
+#define HAL_BSEC_CLOSED_STATE               (0x0DU << BSEC_SR_NVSTATE_Pos)  /*!< BSEC is in closed state                                            */
+#define HAL_BSEC_INVALID_STATE              (0x07U << BSEC_SR_NVSTATE_Pos)  /*!< BSEC is in invalid state                                           */
+#define HAL_BSEC_INVALID_STATE_WITH_TAMPER  (0x23U << BSEC_SR_NVSTATE_Pos)  /*!< BSEC is in invalid state with an active confirmed tamper triggered */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Epoch_Select BSEC Epoch selected register
+  * @{
+  */
+#define HAL_BSEC_EPOCH_COUNTER_0  (0U)  /*!< Epoch counter 0 */
+#define HAL_BSEC_EPOCH_COUNTER_1  (1U)  /*!< Epoch counter 1 */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_HDPL BSEC Hide protection level
+  * @{
+  */
+#define HAL_BSEC_HDPL_VALUE_0  (0xB4U)  /*!< Level 0 */
+#define HAL_BSEC_HDPL_VALUE_1  (0x51U)  /*!< Level 1 */
+#define HAL_BSEC_HDPL_VALUE_2  (0x8AU)  /*!< Level 2 */
+#define HAL_BSEC_HDPL_VALUE_3  (0x6FU)  /*!< Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_INCR_HDPL BSEC Increment of Hide protection level sent to SAES
+  * @{
+  */
+#define HAL_BSEC_HDPL_INCR_VALUE_0  (0U)  /*!< HDPL sent to SAES incremented by 0 */
+#define HAL_BSEC_HDPL_INCR_VALUE_1  (1U)  /*!< HDPL sent to SAES incremented by 1 */
+#define HAL_BSEC_HDPL_INCR_VALUE_2  (2U)  /*!< HDPL sent to SAES incremented by 2 */
+#define HAL_BSEC_HDPL_INCR_VALUE_3  (3U)  /*!< HDPL sent to SAES incremented by 3 */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Register_Type BSEC Type of scratch register
+  * @{
+  */
+#define HAL_BSEC_SCRATCH_REG             (0U)  /*!< Type of register is scratch register            */
+#define HAL_BSEC_WRITE_ONCE_SCRATCH_REG  (1U)  /*!< Type of register is write once scratch register */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Debug_Req BSEC Debug request
+  * @{
+  */
+#define HAL_BSEC_DBG_NOT_REQUESTED  (0U)            /*!< Host debugger is not requesting debug */
+#define HAL_BSEC_DBG_REQUESTED      BSEC_SR_DBGREQ  /*!< Host debugger is requesting debug     */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Open_Dbg BSEC Open debug level
+  * @{
+  */
+#define HAL_BSEC_OPEN_DBG_LEVEL_0  (0x00B40000U)  /*!< Debug opened for HDPL0 */
+#define HAL_BSEC_OPEN_DBG_LEVEL_1  (0x00510000U)  /*!< Debug opened for HDPL1 */
+#define HAL_BSEC_OPEN_DBG_LEVEL_2  (0x008A0000U)  /*!< Debug opened for HDPL2 */
+#define HAL_BSEC_OPEN_DBG_LEVEL_3  (0x006F0000U)  /*!< Debug opened for HDPL3 */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Sec_Dbg_Auth BSEC Secure debug authorization
+  * @{
+  */
+#define HAL_BSEC_SEC_DBG_UNAUTH  (0x00000000U)  /*!< Secure debug not authorized */
+#define HAL_BSEC_SEC_DBG_AUTH    (0xB4000000U)  /*!< Secure debug authorized     */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_NonSec_Dbg_Auth BSEC Non-secure debug authorization
+  * @{
+  */
+#define HAL_BSEC_NONSEC_DBG_UNAUTH  (0x00000000U)  /*!< Non-secure debug not authorized */
+#define HAL_BSEC_NONSEC_DBG_AUTH    (0x0000B400U)  /*!< Non-secure debug authorized     */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Debug_Lock BSEC Debug lock
+  * @{
+  */
+#define HAL_BSEC_DEBUG_LOCKED    (0x00000000U)  /*!< DBG_MCU AP interface locked   */
+#define HAL_BSEC_DEBUG_UNLOCKED  (0x000000B4U)  /*!< DBG_MCU AP interface unlocked */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_DHUK_Validity BSEC Derived hardware unique key validity
+  * @{
+  */
+#define HAL_BSEC_DHUK_INVALID    (0U)            /*!< DHUK can't be used in SAES */
+#define HAL_BSEC_DHUK_VALID      BSEC_SR_HVALID  /*!< DHUK can be used in SAES   */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_DHUK_Lock BSEC Derived hardware unique key lock
+  * @{
+  */
+#define HAL_BSEC_DHUK_USABLE      (0U)               /*!< DHUK in SAES is usable */
+#define HAL_BSEC_DHUK_NOT_USABLE  BSEC_LOCKR_HKLOCK  /*!< DHUK in SAES is not usable */
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Reset_Type BSEC Type of reset
+  * @{
+  */
+#define HAL_BSEC_HOT_RESET   (0U)  /*!< Type of reset is hot reset */
+#define HAL_BSEC_WARM_RESET  (1U)  /*!< Type of reset is warm reset */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup BSEC_Exported_Macros BSEC Exported Macros
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup BSEC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_GetStatus(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus);
+HAL_StatusTypeDef HAL_BSEC_GlobalLock(BSEC_HandleTypeDef *hbsec);
+HAL_StatusTypeDef HAL_BSEC_GetGlobalLockStatus(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus);
+HAL_StatusTypeDef HAL_BSEC_GetErrorCode(BSEC_HandleTypeDef * hbsec, uint32_t *pError);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_Read(BSEC_HandleTypeDef * hbsec, uint32_t FuseId, uint32_t *pFuseData);
+HAL_StatusTypeDef HAL_BSEC_OTP_Program(BSEC_HandleTypeDef *hbsec, uint32_t FuseId, uint32_t FuseData, uint32_t Lock);
+HAL_StatusTypeDef HAL_BSEC_OTP_Reload(BSEC_HandleTypeDef *hbsec, uint32_t FuseId);
+HAL_StatusTypeDef HAL_BSEC_OTP_Lock(BSEC_HandleTypeDef *hbsec, uint32_t FuseId, uint32_t Lock);
+HAL_StatusTypeDef HAL_BSEC_OTP_GetState(BSEC_HandleTypeDef * hbsec, uint32_t FuseId, uint32_t *pState);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_ReadShadow(BSEC_HandleTypeDef * hbsec, uint32_t RegId, uint32_t *pRegData);
+HAL_StatusTypeDef HAL_BSEC_OTP_WriteShadow(BSEC_HandleTypeDef *hbsec, uint32_t RegId, uint32_t RegData);
+HAL_StatusTypeDef HAL_BSEC_OTP_GetShadowState(BSEC_HandleTypeDef * hbsec, uint32_t RegId, uint32_t *pValidity);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group4
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDeviceLifeCycleState(BSEC_HandleTypeDef * hbsec, uint32_t *pState);
+HAL_StatusTypeDef HAL_BSEC_ReadEpochCounter(BSEC_HandleTypeDef * hbsec, uint32_t CounterId, uint32_t *pCounterData);
+HAL_StatusTypeDef HAL_BSEC_SelectEpochCounter(BSEC_HandleTypeDef *hbsec, uint32_t SelectedCounter);
+HAL_StatusTypeDef HAL_BSEC_GetEpochCounterSelection(BSEC_HandleTypeDef * hbsec, uint32_t *pSelectedCounter);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group5
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_GetHDPLValue(BSEC_HandleTypeDef * hbsec, uint32_t *pHDPL);
+HAL_StatusTypeDef HAL_BSEC_IncrementHDPLValue(BSEC_HandleTypeDef *hbsec);
+HAL_StatusTypeDef HAL_BSEC_ConfigSAESHDPLIncrementValue(BSEC_HandleTypeDef *hbsec, uint32_t Increment);
+HAL_StatusTypeDef HAL_BSEC_GetSAESHDPLIncrementValue(BSEC_HandleTypeDef * hbsec, uint32_t *pIncrement);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group6
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_WriteScratchValue(BSEC_HandleTypeDef *hbsec, const BSEC_ScratchRegTypeDef *pRegAddr, uint32_t Value);
+HAL_StatusTypeDef HAL_BSEC_ReadScratchValue(BSEC_HandleTypeDef * hbsec, const BSEC_ScratchRegTypeDef *pRegAddr, uint32_t *pValue);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group7
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDebugRequest(BSEC_HandleTypeDef * hbsec, uint32_t *pDbgReq);
+HAL_StatusTypeDef HAL_BSEC_SendJTAGData(BSEC_HandleTypeDef *hbsec, uint32_t Data);
+HAL_StatusTypeDef HAL_BSEC_ReceiveJTAGData(BSEC_HandleTypeDef * hbsec, uint32_t *pData);
+HAL_StatusTypeDef HAL_BSEC_ConfigDebug(BSEC_HandleTypeDef *hbsec,const BSEC_DebugCfgTypeDef *pCfg);
+HAL_StatusTypeDef HAL_BSEC_GetDebugConfig(BSEC_HandleTypeDef * hbsec, BSEC_DebugCfgTypeDef *pDbgCfg);
+HAL_StatusTypeDef HAL_BSEC_LockDebug(BSEC_HandleTypeDef *hbsec);
+HAL_StatusTypeDef HAL_BSEC_UnlockDebug(BSEC_HandleTypeDef *hbsec);
+HAL_StatusTypeDef HAL_BSEC_GetDebugLockState(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group8
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDHUKValidity(BSEC_HandleTypeDef * hbsec, uint32_t *pValidity);
+HAL_StatusTypeDef HAL_BSEC_LockDHUKUse(BSEC_HandleTypeDef *hbsec);
+HAL_StatusTypeDef HAL_BSEC_GetDHUKLockStatus(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup BSEC_Exported_Functions_Group9
+  * @{
+  */
+HAL_StatusTypeDef HAL_BSEC_GetNumberOfResets(BSEC_HandleTypeDef * hbsec, uint32_t ResetType, uint32_t *pResetNumber);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/**
+  @cond 0
+  */
+#define IS_BSEC_PERMANENT_LOCK(VALUE)  (((VALUE) == HAL_BSEC_NORMAL_PROG) || ((VALUE) == HAL_BSEC_LOCK_PROG))
+
+#define IS_BSEC_LOCK_CFG(CFG)          ((CFG) <= (HAL_BSEC_FUSE_PROG_LOCKED | HAL_BSEC_FUSE_WRITE_LOCKED | HAL_BSEC_FUSE_RELOAD_LOCKED))
+
+#define IS_BSEC_STATE(STATE)           (((STATE) == HAL_BSEC_OPEN_STATE)    || ((STATE) == HAL_BSEC_CLOSED_STATE) \
+                                     || ((STATE) == HAL_BSEC_INVALID_STATE) || ((STATE) == HAL_BSEC_INVALID_STATE_WITH_TAMPER))
+
+#define IS_BSEC_EPOCHSEL(VALUE)        (((VALUE) == HAL_BSEC_EPOCH_COUNTER_0) || ((VALUE) == HAL_BSEC_EPOCH_COUNTER_1))
+
+#define IS_BSEC_HDPL(LEVEL)            (((LEVEL) == HAL_BSEC_HDPL_VALUE_0) || ((LEVEL) == HAL_BSEC_HDPL_VALUE_1) \
+                                     || ((LEVEL) == HAL_BSEC_HDPL_VALUE_2) || ((LEVEL) == HAL_BSEC_HDPL_VALUE_3))
+
+#define IS_BSEC_NEXTHDPL(VALUE)        (((VALUE) == HAL_BSEC_HDPL_INCR_VALUE_0) || ((VALUE) == HAL_BSEC_HDPL_INCR_VALUE_1) \
+                                     || ((VALUE) == HAL_BSEC_HDPL_INCR_VALUE_2) || ((VALUE) == HAL_BSEC_HDPL_INCR_VALUE_3))
+
+#define IS_BSEC_REGTYPE(TYPE)          (((TYPE) == HAL_BSEC_SCRATCH_REG) || ((TYPE) == HAL_BSEC_WRITE_ONCE_SCRATCH_REG))
+
+#define IS_BSEC_OPENDBG(LEVEL)        (((LEVEL) == HAL_BSEC_OPEN_DBG_LEVEL_0) || ((LEVEL) == HAL_BSEC_OPEN_DBG_LEVEL_1) \
+                                    || ((LEVEL) == HAL_BSEC_OPEN_DBG_LEVEL_2) || ((LEVEL) == HAL_BSEC_OPEN_DBG_LEVEL_3))
+
+#define IS_BSEC_SECDBGAUTH(AUTH)      (((AUTH) == HAL_BSEC_SEC_DBG_UNAUTH) || ((AUTH) == HAL_BSEC_SEC_DBG_AUTH))
+
+#define IS_BSEC_NSDBGAUTH(AUTH)       (((AUTH) == HAL_BSEC_NONSEC_DBG_UNAUTH) || ((AUTH) == HAL_BSEC_NONSEC_DBG_AUTH))
+
+#define IS_BSEC_DEBUGLOCK(VALUE)      (((VALUE) == HAL_BSEC_DEBUG_LOCKED) || ((VALUE) == HAL_BSEC_DEBUG_UNLOCKED))
+
+#define IS_BSEC_RESETTYPE(TYPE)       (((TYPE) == HAL_BSEC_HOT_RESET) || ((TYPE) == HAL_BSEC_WARM_RESET))
+/**
+  @endcond
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_BSEC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cacheaxi.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cacheaxi.h
new file mode 100644
index 000000000..aaec95468
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cacheaxi.h
@@ -0,0 +1,352 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cacheaxi.h
+  * @author  MCD Application Team
+  * @brief   Header file of CACHEAXI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32N6xx_HAL_CACHEAXI_H
+#define STM32N6xx_HAL_CACHEAXI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (CACHEAXI)
+/** @addtogroup CACHEAXI
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CACHEAXI_Exported_Types CACHEAXI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_CACHEAXI_STATE_RESET   = 0x00U, /*!< CACHEAXI not yet initialized or disabled   */
+  HAL_CACHEAXI_STATE_READY   = 0x01U, /*!< Peripheral initialized and ready for use   */
+  HAL_CACHEAXI_STATE_BUSY    = 0x02U, /*!< An internal process is ongoing             */
+  HAL_CACHEAXI_STATE_TIMEOUT = 0x05U, /*!< Timeout state                              */
+  HAL_CACHEAXI_STATE_ERROR   = 0x06U, /*!< CACHEAXI state error                       */
+} HAL_CACHEAXI_StateTypeDef;
+
+/** @defgroup CACHEAXI_Configuration_Structure_definition CACHEAXI Configuration Structure definition
+  * @brief  CACHEAXI Configuration Structure definition
+  * @{
+  */
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+typedef struct __CACHEAXI_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+{
+  CACHEAXI_TypeDef               *Instance;    /*!< CACHEAXI register base address.    */
+  __IO HAL_CACHEAXI_StateTypeDef State;
+  __IO uint32_t                  ErrorCode;
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+  void (* ErrorCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
+  void (* CleanByAddrCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
+  void (* InvalidateCompleteCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
+  void (* CleanAndInvalidateByAddrCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
+
+  void (* MspInitCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
+  void (* MspDeInitCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+} CACHEAXI_HandleTypeDef;
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL CACHEAXI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_CACHEAXI_CLEAN_BY_ADDRESS_CB_ID                 = 0x00U, /*!< CACHEAXI Clean By Address callback ID                */
+  HAL_CACHEAXI_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID  = 0x01U, /*!< CACHEAXI Clean And Invalidate By Address callback ID */
+  HAL_CACHEAXI_INVALIDATE_COMPLETE_CB_ID              = 0x02U, /*!< CACHEAXI Invalidate Complete ID                      */
+  HAL_CACHEAXI_ERROR_CB_ID                            = 0x03U, /*!< CACHEAXI Error callback ID                           */
+
+  HAL_CACHEAXI_MSPINIT_CB_ID                          = 0x04U, /*!< CACHEAXI Msp Init callback ID                        */
+  HAL_CACHEAXI_MSPDEINIT_CB_ID                        = 0x05U  /*!< CACHEAXI Msp DeInit callback ID                      */
+} HAL_CACHEAXI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL CACHEAXI Callback pointer definition
+  */
+/*!< Pointer to a CACHEAXI common callback function */
+typedef  void (*pCACHEAXI_CallbackTypeDef)(CACHEAXI_HandleTypeDef *hcacheaxi);
+
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants -------------------------------------------------------*/
+/** @defgroup CACHEAXI_Exported_Constants CACHEAXI Exported Constants
+  * @{
+  */
+
+/** @defgroup CACHEAXI_Error_Code CACHEAXI Error Code
+  * @{
+  */
+#define HAL_CACHEAXI_ERROR_NONE              0x00000000U /*!< No error                */
+#define HAL_CACHEAXI_ERROR_TIMEOUT           0x00000010U /*!< Timeout error           */
+#define HAL_CACHEAXI_ERROR_EVICTION_CLEAN    0x00000020U /*!< Eviction or clean operation write-back error */
+#define HAL_CACHEAXI_ERROR_INVALID_OPERATION 0x00000040U /*!< Invalid operation       */
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+#define HAL_CACHEAXI_ERROR_INVALID_CALLBACK  0x00000080U /*!< Invalid callback error  */
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_Monitor_Type Monitor type
+  * @{
+  */
+#define CACHEAXI_MONITOR_READ_HIT         CACHEAXI_CR1_RHITMEN   /*!< Read Hit monitoring */
+#define CACHEAXI_MONITOR_READ_MISS        CACHEAXI_CR1_RMISSMEN  /*!< Read Miss monitoring */
+#define CACHEAXI_MONITOR_WRITE_HIT        CACHEAXI_CR1_WHITMEN   /*!< Write Hit monitoring */
+#define CACHEAXI_MONITOR_WRITE_MISS       CACHEAXI_CR1_WMISSMEN  /*!< Write Miss monitoring */
+#define CACHEAXI_MONITOR_READALLOC_MISS   CACHEAXI_CR1_RAMMEN    /*!< Read-allocate Miss monitoring */
+#define CACHEAXI_MONITOR_WRITEALLOC_MISS  CACHEAXI_CR1_WAMMEN    /*!< Write-allocate Miss monitoring */
+#define CACHEAXI_MONITOR_WRITETHROUGH     CACHEAXI_CR1_WTMEN     /*!< Write-through monitoring */
+#define CACHEAXI_MONITOR_EVICTION         CACHEAXI_CR1_EVIMEN    /*!< Eviction monitoring */
+#define CACHEAXI_MONITOR_ALL              (CACHEAXI_CR1_RHITMEN | CACHEAXI_CR1_RMISSMEN | \
+                                           CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_WMISSMEN | \
+                                           CACHEAXI_CR1_RAMMEN  | CACHEAXI_CR1_WAMMEN   | \
+                                           CACHEAXI_CR1_WTMEN   | CACHEAXI_CR1_EVIMEN   )
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_Interrupts Interrupts
+  * @{
+  */
+#define CACHEAXI_IT_BUSYEND              CACHEAXI_IER_BSYENDIE /*!< Busy end interrupt */
+#define CACHEAXI_IT_ERROR                CACHEAXI_IER_ERRIE    /*!< Cache error interrupt */
+#define CACHEAXI_IT_CMDEND               CACHEAXI_IER_CMDENDIE /*!< Command end interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_Flags Flags
+  * @{
+  */
+#define CACHEAXI_FLAG_BUSY               CACHEAXI_SR_BUSYF     /*!< Busy flag */
+#define CACHEAXI_FLAG_BUSYEND            CACHEAXI_SR_BSYENDF   /*!< Busy end flag */
+#define CACHEAXI_FLAG_ERROR              CACHEAXI_SR_ERRF      /*!< Cache error flag */
+#define CACHEAXI_FLAG_BUSYCMD            CACHEAXI_SR_BUSYCMDF  /*!< Busy command flag */
+#define CACHEAXI_FLAG_CMDEND             CACHEAXI_SR_CMDENDF   /*!< Command end flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ----------------------------------------------------------*/
+/** @defgroup CACHEAXI_Exported_Macros CACHEAXI Exported Macros
+  * @{
+  */
+
+/** @brief  Enable CACHEAXI interrupts.
+  * @param  __HANDLE__ specifies the CACHEAXI handle.
+  * @param  __INTERRUPT__ specifies the CACHEAXI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref CACHEAXI_IT_BUSYEND  Busy end interrupt
+  *            @arg @ref CACHEAXI_IT_ERROR    Cache error interrupt
+  *            @arg @ref CACHEAXI_IT_CMDEND   Cache Command end interrupt
+  * @retval None
+  */
+#define __HAL_CACHEAXI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief  Disable CACHEAXI interrupts.
+  * @param  __HANDLE__ specifies the CACHEAXI handle.
+  * @param  __INTERRUPT__ specifies the CACHEAXI interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref CACHEAXI_IT_BUSYEND  Busy end interrupt
+  *            @arg @ref CACHEAXI_IT_ERROR    Cache error interrupt
+  *            @arg @ref CACHEAXI_IT_CMDEND   Cache Command end interrupt
+  * @retval None
+  */
+#define __HAL_CACHEAXI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
+
+/** @brief  Check whether the specified CACHEAXI interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the CACHEAXI handle.
+  * @param  __INTERRUPT__ specifies the CACHEAXI interrupt source to check.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref CACHEAXI_IT_BUSYEND  Busy end interrupt
+  *            @arg @ref CACHEAXI_IT_ERROR    Cache error interrupt
+  *            @arg @ref CACHEAXI_IT_CMDEND   Cache Command end interrupt
+  *
+  * @retval The state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_CACHEAXI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+  ((READ_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the selected CACHEAXI flag is set or not.
+  * @param  __HANDLE__ specifies the CACHEAXI handle.
+  * @param  __FLAG__   specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CACHEAXI_FLAG_BUSY     Busy flag
+  *            @arg @ref CACHEAXI_FLAG_BUSYEND  Busy end flag
+  *            @arg @ref CACHEAXI_FLAG_ERROR    Cache error flag
+  *            @arg @ref CACHEAXI_FLAG_BUSYCMD  Cache Busy command flag
+  *            @arg @ref CACHEAXI_FLAG_CMDEND   Cache command end flag
+  * @retval The state of __FLAG__ (0 or 1).
+  */
+#define __HAL_CACHEAXI_GET_FLAG(__HANDLE__, __FLAG__) \
+  ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? 1U : 0U)
+
+/** @brief  Clear the selected CACHEAXI flags.
+  * @param  __HANDLE__ specifies the CACHEAXI handle.
+  * @param  __FLAG__   specifies the CACHEAXI flags to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref CACHEAXI_FLAG_BUSYEND  Busy end flag
+  *            @arg @ref CACHEAXI_FLAG_ERROR    Cache error flag
+  *            @arg @ref CACHEAXI_FLAG_CMDEND   Cache command end flag
+  */
+#define __HAL_CACHEAXI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup CACHEAXI_Exported_Functions CACHEAXI Exported Functions
+  *  @brief    CACHEAXI Exported functions
+  * @{
+  */
+
+/** @defgroup CACHEAXI_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @brief    Initialization and De-Initialization Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Init(CACHEAXI_HandleTypeDef *hcacheaxi);
+HAL_StatusTypeDef HAL_CACHEAXI_DeInit(CACHEAXI_HandleTypeDef *hcacheaxi);
+void              HAL_CACHEAXI_MspInit(CACHEAXI_HandleTypeDef *hcacheaxi);
+void              HAL_CACHEAXI_MspDeInit(CACHEAXI_HandleTypeDef *hcacheaxi);
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_Exported_Functions_Group2 I/O Operation Functions
+  * @brief    I/O Operation Functions
+  * @{
+  */
+/* Peripheral Control functions ***/
+HAL_StatusTypeDef HAL_CACHEAXI_Enable(CACHEAXI_HandleTypeDef *hcacheaxi);
+HAL_StatusTypeDef HAL_CACHEAXI_Disable(CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t          HAL_CACHEAXI_IsEnabled(const CACHEAXI_HandleTypeDef *hcacheaxi);
+
+/*** Cache maintenance in blocking mode (Polling) ***/
+HAL_StatusTypeDef HAL_CACHEAXI_Invalidate(CACHEAXI_HandleTypeDef *hcacheaxi);
+HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                           uint32_t dSize);
+HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                                  uint32_t dSize);
+
+/*** Cache maintenance in non-blocking mode (Interrupt) ***/
+HAL_StatusTypeDef HAL_CACHEAXI_Invalidate_IT(CACHEAXI_HandleTypeDef *hcacheaxi);
+HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                              uint32_t dSize);
+HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                                     uint32_t dSize);
+
+/*** IRQHandler and Callbacks ***/
+void HAL_CACHEAXI_IRQHandler(CACHEAXI_HandleTypeDef *hcacheaxi);
+void HAL_CACHEAXI_ErrorCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
+void HAL_CACHEAXI_CleanByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
+void HAL_CACHEAXI_InvalidateCompleteCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
+void HAL_CACHEAXI_CleanAndInvalidateByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***/
+HAL_StatusTypeDef HAL_CACHEAXI_RegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi,
+                                                HAL_CACHEAXI_CallbackIDTypeDef CallbackID,
+                                                pCACHEAXI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CACHEAXI_UnRegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi,
+                                                  HAL_CACHEAXI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+
+/*** Performance instruction cache monitoring functions ***/
+uint32_t HAL_CACHEAXI_Monitor_GetReadHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_Monitor_GetReadMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_Monitor_GetWriteHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_Monitor_GetWriteMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_Monitor_GetReadAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_Monitor_GetWriteAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_Monitor_GetWriteThroughValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_Monitor_GetEvictionValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
+HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Reset(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType);
+HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Start(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType);
+HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Stop(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType);
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_Exported_Functions_Group3 State and Error Functions
+  * @brief    State and Error Functions
+  * @{
+  */
+HAL_CACHEAXI_StateTypeDef HAL_CACHEAXI_GetState(const CACHEAXI_HandleTypeDef *hcacheaxi);
+uint32_t HAL_CACHEAXI_GetError(const CACHEAXI_HandleTypeDef *hcacheaxi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+#endif /* CACHEAXI */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_CACHEAXI_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_conf.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_conf.h
new file mode 100644
index 000000000..1a5559f40
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_conf.h
@@ -0,0 +1,494 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32n6xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_CONF_H
+#define STM32N6xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_BSEC_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_DCMI_MODULE_ENABLED   */
+/*#define HAL_DCMIPP_MODULE_ENABLED   */
+/*#define HAL_DMA2D_MODULE_ENABLED   */
+/*#define HAL_DTS_MODULE_ENABLED   */
+/*#define HAL_ETH_MODULE_ENABLED   */
+/*#define HAL_EXTI_MODULE_ENABLED   */
+/*#define HAL_FDCAN_MODULE_ENABLED   */
+/*#define HAL_GFXMMU_MODULE_ENABLED   */
+/*#define HAL_GFXTIM_MODULE_ENABLED   */
+/*#define HAL_HASH_MODULE_ENABLED   */
+/*#define HAL_HCD_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_I3C_MODULE_ENABLED   */
+/*#define HAL_ICACHE_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_JPEG_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_LTDC_MODULE_ENABLED   */
+/*#define HAL_MCE_MODULE_ENABLED   */
+/*#define HAL_MDF_MODULE_ENABLED   */
+/*#define HAL_MMC_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_PSSI_MODULE_ENABLED   */
+/*#define HAL_RAMCFG_MODULE_ENABLED   */
+/*#define HAL_RIF_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SD_MODULE_ENABLED   */
+/*#define HAL_SDRAM_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SPDIFRX_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_SRAM_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+/*#define HAL_XSPI_MODULE_ENABLED   */
+/*#define HAL_CACHEAXI_MODULE_ENABLED   */
+/*#define HAL_MDIOS_MODULE_ENABLED   */
+/*#define HAL_GPU2D_MODULE_ENABLED   */
+/*#define HAL_CACHEAXI_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE              48000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100UL   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE              32768UL   /*!< Value of the External oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000UL     /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+#define MSI_VALUE              4000000UL /*!< Value of the Internal oscillator in Hz */
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE              64000000UL /*!< Value of the Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE               32000UL    /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz */
+/* The real value may vary depending on the variations in voltage and temperature.*/
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                  3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY          15U  /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                   0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32n6xx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define  USE_HAL_ADC_REGISTER_CALLBACKS       0U /* ADC register callback disabled       */
+#define  USE_HAL_CACHEAXI_REGISTER_CALLBACKS  0U /* CACHEAXI register callback disabled  */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS      0U /* CRYP register callback disabled      */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS      0U /* DCMI register callback disabled      */
+#define  USE_HAL_DCMIPP_REGISTER_CALLBACKS    0U /* DCMIPP register callback disabled    */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS     0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS       0U /* DTS register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS       0U /* ETH register callback disabled       */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS     0U /* FDCAN register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS    0U /* GFXMMU register callback disabled    */
+#define  USE_HAL_GFXTIM_REGISTER_CALLBACKS    0U /* GFXTIM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS      0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS       0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS       0U /* I2C register callback disabled       */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS       0U /* I2S register callback disabled       */
+#define  USE_HAL_I3C_REGISTER_CALLBACKS       0U /* I3C register callback disabled       */
+#define  USE_HAL_IWDG_REGISTER_CALLBACKS      0U /* IWDG register callback disabled      */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS      0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS     0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS      0U /* LTDC register callback disabled      */
+#define  USE_HAL_MCE_REGISTER_CALLBACKS       0U /* MCE register callback disabled       */
+#define  USE_HAL_MDF_REGISTER_CALLBACKS       0U /* MDF register callback disabled       */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS       0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS      0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS       0U /* NOR register callback disabled       */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS       0U /* PCD register callback disabled       */
+#define  USE_HAL_PKA_REGISTER_CALLBACKS       0U /* PKA register callback disabled       */
+#define  USE_HAL_PSSI_REGISTER_CALLBACKS      0U /* PSSI register callback disabled      */
+#define  USE_HAL_RAMCFG_REGISTER_CALLBACKS    0U /* RAMCFG register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS       0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS       0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS       0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS        0U /* SD register callback disabled        */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS     0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS     0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS   0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS       0U /* SPI register callback disabled       */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS      0U /* SRAM register callback disabled      */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS       0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS      0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS     0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS      0U /* WWDG register callback disabled      */
+#define  USE_HAL_XSPI_REGISTER_CALLBACKS      0U /* XSPI register callback disabled      */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC                   0U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER            0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32n6xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32n6xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_RIF_MODULE_ENABLED
+#include "stm32n6xx_hal_rif.h"
+#endif /* HAL_RIF_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32n6xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CACHEAXI_MODULE_ENABLED
+#include "stm32n6xx_hal_cacheaxi.h"
+#endif /* HAL_CACHEAXI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32n6xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32n6xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_BSEC_MODULE_ENABLED
+#include "stm32n6xx_hal_bsec.h"
+#endif /* HAL_BSEC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32n6xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32n6xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+#include "stm32n6xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DCMIPP_MODULE_ENABLED
+#include "stm32n6xx_hal_dcmipp.h"
+#endif /* HAL_DCMIPP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#include "stm32n6xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+#include "stm32n6xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+#include "stm32n6xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32n6xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32n6xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+#include "stm32n6xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_GFXTIM_MODULE_ENABLED
+#include "stm32n6xx_hal_gfxtim.h"
+#endif /* HAL_GFXTIM_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32n6xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_GPU2D_MODULE_ENABLED
+#include "stm32n6xx_hal_gpu2d.h"
+#endif /* HAL_GPU2D_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32n6xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32n6xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32n6xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32n6xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_I3C_MODULE_ENABLED
+#include "stm32n6xx_hal_i3c.h"
+#endif /* HAL_I3C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+#include "stm32n6xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32n6xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32n6xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+#include "stm32n6xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32n6xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32n6xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_MCE_MODULE_ENABLED
+#include "stm32n6xx_hal_mce.h"
+#endif /* HAL_MCE_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+#include "stm32n6xx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+#include "stm32n6xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+#include "stm32n6xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32n6xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32n6xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32n6xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32n6xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+#include "stm32n6xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+#include "stm32n6xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32n6xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+#include "stm32n6xx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32n6xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32n6xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32n6xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+#include "stm32n6xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+#include "stm32n6xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32n6xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32n6xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+#include "stm32n6xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32n6xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32n6xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32n6xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32n6xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32n6xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32n6xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+#include "stm32n6xx_hal_xspi.h"
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macros -----------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_CONF_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cortex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cortex.h
new file mode 100644
index 000000000..b4fb881c8
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cortex.h
@@ -0,0 +1,407 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_CORTEX_H
+#define STM32N6xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+  * @{
+  */
+
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t  Enable;                /*!< Specifies the status of the region.
+                                       This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t  Number;                /*!< Specifies the number of the region to protect.
+                                       This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint32_t LimitAddress;          /*!< Specifies the limit address of the region to protect.                          */
+  uint8_t  AttributesIndex;       /*!< Specifies the memory attributes index.
+                                       This parameter can be a value of @ref CORTEX_MPU_Attributes_Number             */
+  uint8_t  AccessPermission;      /*!< Specifies the region access permission type.
+                                       This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t  DisableExec;           /*!< Specifies the instruction access status.
+                                       This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t  IsShareable;           /*!< Specifies the shareability status of the protected region.
+                                       This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+} MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t  Number;                /*!< Specifies the number of the memory attributes to configure.
+                                       This parameter can be a value of @ref CORTEX_MPU_Attributes_Number             */
+
+  uint8_t  Attributes;            /*!< Specifies the memory attributes vue.
+                                       This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF   */
+
+} MPU_Attributes_InitTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0            7U  /*!< 0 bit  for pre-emption priority,
+                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1            6U  /*!< 1 bit  for pre-emption priority,
+                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2            5U  /*!< 2 bits for pre-emption priority,
+                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3            4U  /*!< 3 bits for pre-emption priority,
+                                                 1 bit for subpriority  */
+#define NVIC_PRIORITYGROUP_4            3U  /*!< 4 bits for pre-emption priority,
+                                                 0 bit for subpriority  */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8     0U
+#define SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE          0U
+#define  MPU_HARDFAULT_NMI               MPU_CTRL_HFNMIENA_Msk
+#define  MPU_PRIVILEGED_DEFAULT          MPU_CTRL_PRIVDEFENA_Msk
+#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE               1U
+#define  MPU_REGION_DISABLE              0U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE   0U
+#define  MPU_INSTRUCTION_ACCESS_DISABLE  1U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_NOT_SHAREABLE        0U
+#define  MPU_ACCESS_OUTER_SHAREABLE      2U
+#define  MPU_ACCESS_INNER_SHAREABLE      3U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+  * @{
+  */
+#define  MPU_REGION_PRIV_RW              0U
+#define  MPU_REGION_ALL_RW               1U
+#define  MPU_REGION_PRIV_RO              2U
+#define  MPU_REGION_ALL_RO               3U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0              0U
+#define  MPU_REGION_NUMBER1              1U
+#define  MPU_REGION_NUMBER2              2U
+#define  MPU_REGION_NUMBER3              3U
+#define  MPU_REGION_NUMBER4              4U
+#define  MPU_REGION_NUMBER5              5U
+#define  MPU_REGION_NUMBER6              6U
+#define  MPU_REGION_NUMBER7              7U
+#define  MPU_REGION_NUMBER8              8U
+#define  MPU_REGION_NUMBER9              9U
+#define  MPU_REGION_NUMBER10             10U
+#define  MPU_REGION_NUMBER11             11U
+#define  MPU_REGION_NUMBER12             12U
+#define  MPU_REGION_NUMBER13             13U
+#define  MPU_REGION_NUMBER14             14U
+#define  MPU_REGION_NUMBER15             15U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number
+  * @{
+  */
+#define  MPU_ATTRIBUTES_NUMBER0          0U
+#define  MPU_ATTRIBUTES_NUMBER1          1U
+#define  MPU_ATTRIBUTES_NUMBER2          2U
+#define  MPU_ATTRIBUTES_NUMBER3          3U
+#define  MPU_ATTRIBUTES_NUMBER4          4U
+#define  MPU_ATTRIBUTES_NUMBER5          5U
+#define  MPU_ATTRIBUTES_NUMBER6          6U
+#define  MPU_ATTRIBUTES_NUMBER7          7U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
+  * @{
+  */
+
+/* Device memory attributes */
+#define  MPU_DEVICE_NGNRNE          0x0U  /* Device, noGather, noReorder, noEarly acknowledge. */
+#define  MPU_DEVICE_NGNRE           0x4U  /* Device, noGather, noReorder, Early acknowledge.   */
+#define  MPU_DEVICE_NGRE            0x8U  /* Device, noGather, Reorder, Early acknowledge.     */
+#define  MPU_DEVICE_GRE             0xCU  /* Device, Gather, Reorder, Early acknowledge.       */
+
+/* Normal Memory attributes */
+/* Note that these attributes need to be set for both inner AND outer attributes.
+   These defines should be used with the INNER_OUTER macro if they are the same for inner and outer. */
+/* - Non-cacheable memory attribute*/
+#define  MPU_NOT_CACHEABLE          0x4U  /* Normal memory, non-cacheable. */
+
+/* - Cacheable memory attributes*/
+#define  MPU_WRITE_THROUGH          0x0U  /* Normal memory, write-through. */
+#define  MPU_WRITE_BACK             0x4U  /* Normal memory, write-back.    */
+
+#define  MPU_TRANSIENT              0x0U  /* Normal memory, transient.     */
+#define  MPU_NON_TRANSIENT          0x8U  /* Normal memory, non-transient. */
+
+#define  MPU_NO_ALLOCATE            0x0U  /* Normal memory, no allocate.         */
+#define  MPU_W_ALLOCATE             0x1U  /* Normal memory, write allocate.      */
+#define  MPU_R_ALLOCATE             0x2U  /* Normal memory, read allocate.       */
+#define  MPU_RW_ALLOCATE            0x3U  /* Normal memory, read/write allocate. */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/** @defgroup CORTEX_MPU_Normal_Memory_Attributes CORTEX MPU Normal Memory Attributes
+  * @{
+  */
+/* __ATTR__ being a combination of MPU Normal memory attributes */
+#define OUTER(__ATTR__)        ((__ATTR__) << 4U)
+#define INNER_OUTER(__ATTR__)  ((__ATTR__) | ((__ATTR__) << 4U))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+  * @brief   Cortex control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup,
+                          uint32_t *pPreemptPriority, uint32_t *pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+void HAL_CORTEX_ClearEvent(void);
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
+void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit);
+void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit);
+#ifdef MPU_NS
+void HAL_MPU_Enable_NS(uint32_t MPU_Control);
+void HAL_MPU_Disable_NS(void);
+void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber);
+void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *pMPU_RegionInit);
+void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit);
+#endif /* MPU_NS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_INTERRUPT(__IT__)        (((__IT__) > HardFault_IRQn) && ((__IT__) != DebugMonitor_IRQn))
+
+#define IS_NVIC_PRIORITY_GROUP(__GROUP__)         (((__GROUP__) == NVIC_PRIORITYGROUP_0) || \
+                                                   ((__GROUP__) == NVIC_PRIORITYGROUP_1) || \
+                                                   ((__GROUP__) == NVIC_PRIORITYGROUP_2) || \
+                                                   ((__GROUP__) == NVIC_PRIORITYGROUP_3) || \
+                                                   ((__GROUP__) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(__PRIO__, __PRIOGRP__)   (((__PRIO__) < (1UL << __NVIC_PRIO_BITS)) && \
+                                                              ((__PRIO__) < (1UL << (7U - (__PRIOGRP__)))))
+
+#define IS_NVIC_SUB_PRIORITY(__PRIO__, __PRIOGRP__)   (((__PRIOGRP__) < (7U - __NVIC_PRIO_BITS)) ? \
+                                                       ((__PRIO__) < 1U): \
+                                                       ((__PRIO__) < (1UL << ((__PRIOGRP__) - (7U - __NVIC_PRIO_BITS)))))
+
+#define IS_NVIC_DEVICE_IRQ(__IRQ__)               ((__IRQ__) > SysTick_IRQn)
+
+#define IS_SYSTICK_CLK_SOURCE(__SOURCE__)         (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
+                                                   ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#define IS_MPU_REGION_ENABLE(__STATE__)           (((__STATE__) == MPU_REGION_ENABLE) || \
+                                                   ((__STATE__) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(__STATE__)      (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                                   ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(__STATE__)        (((__STATE__) == MPU_ACCESS_OUTER_SHAREABLE) || \
+                                                   ((__STATE__) == MPU_ACCESS_INNER_SHAREABLE) || \
+                                                   ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(__TYPE__) (((__TYPE__) == MPU_REGION_PRIV_RW) || \
+                                                      ((__TYPE__) == MPU_REGION_ALL_RW)  || \
+                                                      ((__TYPE__) == MPU_REGION_PRIV_RO) || \
+                                                      ((__TYPE__) == MPU_REGION_ALL_RO))
+
+#define IS_MPU_REGION_NUMBER(__NUMBER__)          (((__NUMBER__) == MPU_REGION_NUMBER0) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER1) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER2) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER3) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER4) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER5) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER6) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER7) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER8) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER9) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER10) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER11) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER12) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER13) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER14) || \
+                                                   ((__NUMBER__) == MPU_REGION_NUMBER15))
+
+#define IS_MPU_ATTRIBUTES_NUMBER(__NUMBER__)      (((__NUMBER__) == MPU_ATTRIBUTES_NUMBER0) || \
+                                                   ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER1) || \
+                                                   ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER2) || \
+                                                   ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER3) || \
+                                                   ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER4) || \
+                                                   ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER5) || \
+                                                   ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER6) || \
+                                                   ((__NUMBER__) == MPU_ATTRIBUTES_NUMBER7))
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_CORTEX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_crc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_crc.h
new file mode 100644
index 000000000..4258125f2
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_crc.h
@@ -0,0 +1,342 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_CRC_H
+#define STM32N6xx_HAL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  CRC HAL State Structure definition
+  */
+typedef enum
+{
+  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
+} HAL_CRC_StateTypeDef;
+
+/**
+  * @brief CRC Init Structure definition
+  */
+typedef struct
+{
+  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
+                                            X^4 + X^2+ X +1.
+                                            In that case, there is no need to set GeneratingPolynomial field.
+                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
+                                            CRCLength fields must be set. */
+
+  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
+                                           otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
+
+  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+                                           respectively equal to 7, 8, 16 or 32. This field is written in normal,
+                                           representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
+                                           is written 0x65. No need to specify it if DefaultPolynomialUse is set to
+                                            DEFAULT_POLYNOMIAL_ENABLE.   */
+
+  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+                                           Value can be either one of
+                                           @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
+
+  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+                                           is set to DEFAULT_INIT_VALUE_ENABLE.   */
+
+  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+                                           Can be either one of the following values
+                                           @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
+                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D
+                                           becomes 0x58D43CB2
+                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion,
+                                           0x1A2B3C4D becomes 0xD458B23C
+                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D
+                                           becomes 0xB23CD458 */
+
+  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+                                            Can be either
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted
+                                             into 0x22CC4488 */
+} CRC_InitTypeDef;
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
+typedef struct
+{
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */
+
+  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
+
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+
+  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+                                            Can be either
+                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes
+                                            (8-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of
+                                            half-words (16-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words
+                                            (32-bit data)
+
+                                          Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
+                                          error must occur if InputBufferFormat is not one of the three values listed
+                                          above  */
+} CRC_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
+  * @{
+  */
+#define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
+  * @{
+  */
+#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
+#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
+  * @{
+  */
+#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
+#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
+  * @{
+  */
+#define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
+#define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+  * @{
+  */
+#define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
+#define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+  * @{
+  */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
+#define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRC handle state.
+  * @param  __HANDLE__ CRC handle.
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+  * @brief  Set CRC INIT non-default value
+  * @param  __HANDLE__ CRC handle
+  * @param  __INIT__ 32-bit initial value
+  * @retval None
+  */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+  * @brief Store data in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @param __VALUE__  Value to be stored in the ID register
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval None
+  */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+  * @brief Return the data stored in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval Value of the ID register
+  */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup  CRC_Private_Macros CRC Private Macros
+  * @{
+  */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+#define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
+                                       ((LENGTH) == CRC_POLYLENGTH_7B))
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+  * @}
+  */
+
+/* Include CRC HAL Extended module */
+#include "stm32n6xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_CRC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_crc_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_crc_ex.h
new file mode 100644
index 000000000..35f6cf535
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_crc_ex.h
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_crc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_CRC_EX_H
+#define STM32N6xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+  * @{
+  */
+#define CRC_INPUTDATA_INVERSION_NONE               0x00000000U                         /*!< No input data inversion                    */
+#define CRC_INPUTDATA_INVERSION_HALFWORD_BYWORD    (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_0) /*!< Input data half-word-reversal done by word */
+#define CRC_INPUTDATA_INVERSION_BYTE_BYWORD        (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_1) /*!< Input data byte-reversal done by word      */
+#define CRC_INPUTDATA_INVERSION_BIT_BYBYTE         CRC_CR_REV_IN_0                     /*!< Input data bit-reversal done by byte       */
+#define CRC_INPUTDATA_INVERSION_BIT_BYHALFWORD     CRC_CR_REV_IN_1                     /*!< Input data bit-reversal done by half-word  */
+#define CRC_INPUTDATA_INVERSION_BIT_BYWORD         CRC_CR_REV_IN                       /*!< Input data bit-reversal done by word       */
+
+#define CRC_INPUTDATA_INVERSION_BYTE               CRC_INPUTDATA_INVERSION_BIT_BYBYTE     /*!< Definition for compatibility with legacy code */
+#define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_INPUTDATA_INVERSION_BIT_BYHALFWORD /*!< Definition for compatibility with legacy code */
+#define CRC_INPUTDATA_INVERSION_WORD               CRC_INPUTDATA_INVERSION_BIT_BYWORD     /*!< Definition for compatibility with legacy code */
+/**
+  * @}
+  */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+  * @{
+  */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U                            /*!< No output data inversion                       */
+#define CRC_OUTPUTDATA_INVERSION_BIT             CRC_CR_REV_OUT_0                       /*!< Output data bit-reversal                       */
+#define CRC_OUTPUTDATA_INVERSION_HALFWORD        (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_0)  /*!< Output data half-word-reversal done by word    */
+#define CRC_OUTPUTDATA_INVERSION_BYTE            (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_1)  /*!< Output data byte-reversal done by word         */
+
+#define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_OUTPUTDATA_INVERSION_BIT           /*!<  Definition for compatibility with legacy code */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Set CRC output bit-reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_BIT_ENABLE(__HANDLE__) MODIFY_REG(((__HANDLE__)->Instance->CR),\
+                                                                    (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT),\
+                                                                    CRC_CR_REV_OUT_0);
+
+/**
+  * @brief  Set CRC output halfword-reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_HALFWORD_ENABLE(__HANDLE__) MODIFY_REG(((__HANDLE__)->Instance->CR),\
+                                                                         (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT),\
+                                                                         (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_0));
+
+/**
+  * @brief  Set CRC output byte-reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_BYTE_ENABLE(__HANDLE__) MODIFY_REG(((__HANDLE__)->Instance->CR), \
+                                                                     (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT), \
+                                                                     (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_1));
+
+/* Definition for compatibility with legacy code */
+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__)    __HAL_CRC_OUTPUTREVERSAL_BIT_ENABLE(__HANDLE__)
+
+/**
+  * @brief  Unset CRC output reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_RTYPE_OUT |\
+                                                      CRC_CR_REV_OUT))
+
+/**
+  * @brief  Set CRC non-default polynomial
+  * @param  __HANDLE__ CRC handle
+  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+  * @retval None
+  */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+  * @{
+  */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)            || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD_BYWORD) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE_BYWORD)     || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BIT_BYBYTE)      || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BIT_BYHALFWORD)  || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BIT_BYWORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE)  || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_BIT)      || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_HALFWORD) || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_BYTE))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_CRC_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cryp.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cryp.h
new file mode 100644
index 000000000..fb771aa3c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cryp.h
@@ -0,0 +1,954 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cryp.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_CRYP_H
+#define STM32N6xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(USE_HAL_SAES_ONLY) && (USE_HAL_SAES_ONLY == 1U)
+#if !defined(USE_HAL_CRYP_ONLY)
+#define USE_HAL_CRYP_ONLY       0U
+#elif (USE_HAL_CRYP_ONLY == 1U)
+#error ' USE_HAL_CRYP_ONLY and USE_HAL_SAES_ONLY cannot be set both to 1U '
+#endif /* defined (USE_HAL_CRYP_ONLY) */
+#endif /* defined (USE_HAL_SAES_ONLY) */
+
+#if defined(USE_HAL_CRYP_ONLY) && (USE_HAL_CRYP_ONLY == 1U)
+#if !defined(USE_HAL_SAES_ONLY)
+#define USE_HAL_SAES_ONLY       0U
+#elif (USE_HAL_SAES_ONLY == 1U)
+#error ' USE_HAL_CRYP_ONLY and USE_HAL_SAES_ONLY cannot be set both to 1U '
+#endif /* defined (USE_HAL_SAES_ONLY) */
+#endif /* defined (USE_HAL_CRYP_ONLY) */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (CRYP)
+/** @addtogroup CRYP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+  * @{
+  */
+
+/**
+  * @brief CRYP Init Structure definition
+  */
+
+typedef struct
+{
+  uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                                        This parameter can be a value of @ref CRYP_Data_Type */
+  uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+                                        This parameter can be a value of @ref CRYP_Key_Size */
+  uint32_t *pKey;                      /*!< The key used for encryption/decryption */
+  uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization
+                                         counter in CTR mode */
+  uint32_t Algorithm;                  /*!< AES Algorithm ECB/CBC/CTR/GCM or CCM
+                                        This parameter can be a value of @ref CRYP_CR_ALGOMODE */
+  uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
+                                        GCM : also known as Additional Authentication Data
+                                        CCM : named B1 composed of the associated data length and Associated Data. */
+  uint32_t HeaderSize;                 /*!< The size of header buffer in word  */
+  uint32_t *B0;                        /*!< B0 is first authentication block used only in AES CCM mode */
+  uint32_t DataWidthUnit;              /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+  uint32_t HeaderWidthUnit;            /*!< Header Width Unit, this parameter can be value
+                                            of @ref CRYP_Header_Width_Unit */
+  uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip,
+                                            to configure Key and Initialization
+                                            Vector only once and to skip configuration for consecutive processing.
+                                        This parameter can be a value of @ref CRYP_Configuration_Skip */
+  uint32_t KeyMode;                    /*!< Key mode selection, this parameter can be a value of @ref CRYP_Key_Mode */
+  uint32_t KeySelect;                  /*!< Only for SAES : Key selection, this parameter can be a value
+                                            of @ref CRYP_Key_Select */
+  uint32_t KeyProtection;              /*!< Only for SAES : Key protection, this parameter can be a value of @ref CRYP_Key_Protection */
+
+} CRYP_ConfigTypeDef;
+
+
+/**
+  * @brief  CRYP State Structure definition
+  */
+
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled       */
+  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use         */
+  HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP BUSY, internal processing is ongoing  */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+  HAL_CRYP_STATE_SUSPENDED         = 0x03U,  /*!< CRYP suspended                             */
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+} HAL_CRYP_STATETypeDef;
+
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+/**
+  * @brief HAL CRYP mode suspend definitions
+  */
+
+typedef enum
+{
+  HAL_CRYP_SUSPEND_NONE            = 0x00U,    /*!< CRYP processing suspension not requested */
+  HAL_CRYP_SUSPEND                 = 0x01U     /*!< CRYP processing suspension requested     */
+} HAL_SuspendTypeDef;
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+/**
+  * @brief  CRYP handle Structure definition
+  */
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+typedef struct __CRYP_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+{
+  void                              *Instance;        /*!< CRYP or SAES registers base address */
+
+  CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
+
+  uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...)
+                                                           buffer */
+
+  uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...)
+                                                           buffer */
+
+  __IO uint16_t                     CrypHeaderCount;  /*!< Counter of header data */
+
+  __IO uint16_t                     CrypInCount;      /*!< Counter of input data */
+
+  __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */
+
+  uint16_t                          Size;             /*!< length of input data in word or in byte,
+                                                           according to DataWidthUnit */
+
+  uint32_t                          Phase;            /*!< CRYP peripheral phase */
+
+  DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
+
+  DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
+
+  HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
+
+  __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
+
+  __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
+
+  uint32_t                          Version;          /*!< CRYP1 IP version*/
+
+  uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
+                                                           configuration can be skipped */
+
+  uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
+                                                           for a single signature computation after several
+                                                           messages processing */
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+  void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
+  void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
+  void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */
+
+  void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */
+  void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+
+  __IO HAL_SuspendTypeDef     SuspendRequest;          /*!< CRYP peripheral suspension request flag */
+
+  CRYP_ConfigTypeDef          Init_saved;              /*!< copy of CRYP required parameters when processing
+                                                            is suspended */
+
+  uint32_t                    *pCrypInBuffPtr_saved;   /*!< copy of CRYP input pointer when processing
+                                                            is suspended */
+
+  uint32_t                    *pCrypOutBuffPtr_saved;  /*!< copy of CRYP output pointer when processing
+                                                            is suspended */
+
+  uint32_t                    CrypInCount_saved;       /*!< copy of CRYP input data counter when processing
+                                                            is suspended */
+
+  uint32_t                    CrypOutCount_saved;      /*!< copy of CRYP output data counter when processing
+                                                            is suspended */
+
+  uint32_t                    Phase_saved;             /*!< copy of CRYP authentication phase when processing
+                                                            is suspended */
+
+  __IO HAL_CRYP_STATETypeDef  State_saved;             /*!< copy of CRYP peripheral state when processing
+                                                            is suspended */
+
+  uint32_t                    IV_saved[4];             /*!< copy of Initialisation Vector registers */
+
+  uint32_t                    SUSPxR_saved[16];        /*!< copy of suspension registers */
+
+  uint32_t                    CR_saved;                /*!< copy of CRYP control register  when processing
+                                                            is suspended*/
+
+  uint32_t                    Key_saved[8];            /*!< copy of key registers */
+
+  uint16_t                    Size_saved;              /*!< copy of input buffer size */
+
+  uint16_t                    CrypHeaderCount_saved;   /*!< copy of CRYP header data counter when processing
+                                                            is suspended */
+
+  uint32_t                    SizesSum_saved;          /*!< copy of SizesSum when processing is suspended */
+
+  uint32_t                    ResumingFlag;            /*!< resumption flag to bypass steps already carried out */
+
+  uint32_t                    SuspendedProcessing;     /*< Report whether interruption or DMA-mode processing
+                                                           was suspended */
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+} CRYP_HandleTypeDef;
+
+
+/**
+  * @}
+  */
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
+  * @brief  HAL CRYP Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x01U,    /*!< CRYP Input FIFO transfer completed callback ID  */
+  HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x02U,    /*!< CRYP Output FIFO transfer completed callback ID */
+  HAL_CRYP_ERROR_CB_ID             = 0x03U,    /*!< CRYP Error callback ID                          */
+  HAL_CRYP_MSPINIT_CB_ID           = 0x04U,    /*!< CRYP MspInit callback ID                        */
+  HAL_CRYP_MSPDEINIT_CB_ID         = 0x05U     /*!< CRYP MspDeInit callback ID                      */
+
+} HAL_CRYP_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
+  * @brief  HAL CRYP Callback pointer definition
+  * @{
+  */
+
+typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */
+
+/**
+  * @}
+  */
+
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Error_Definition   CRYP Error Definition
+  * @{
+  */
+#define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
+#define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
+#define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
+#define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error      */
+#define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
+#define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error   */
+#define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
+#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#define HAL_CRYP_ERROR_KEY               0x00000100U  /*!< Key error */
+#define HAL_CRYP_ERROR_RNG               0x00000200U  /*!< RNG error */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+  * @{
+  */
+
+#define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is byte */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+  * @{
+  */
+
+#define CRYP_HEADERWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is byte */
+
+/**
+  * @}
+  */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+/** @defgroup SAES_CR_CHMOD SAES CHMOD Selection
+  * @{
+  */
+
+#define SAES_CR_CHMOD_AES_ECB     ((uint32_t)0x00000000)
+#define SAES_CR_CHMOD_AES_CBC     (SAES_CR_CHMOD_0)
+#define SAES_CR_CHMOD_AES_CTR     (SAES_CR_CHMOD_1)
+#define SAES_CR_CHMOD_AES_GCM     (SAES_CR_CHMOD_0 | SAES_CR_CHMOD_1)
+#define SAES_CR_CHMOD_AES_CCM     (SAES_CR_CHMOD_2)
+
+/**
+  * @}
+  */
+#endif /* USE_HAL_SAES_ONLY */
+
+/** @defgroup CRYP_CR_ALGOMODE CRYP Algorithm Mode
+  * @{
+  */
+
+#define CRYP_AES_ECB              (CRYP_CR_ALGOMODE_2)
+#define CRYP_AES_CBC              (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_2)
+#define CRYP_AES_CTR              (CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_2)
+#define CRYP_AES_KEY              (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_2)
+#define CRYP_AES_GCM              (CRYP_CR_ALGOMODE_3)
+#define CRYP_AES_CCM              (CRYP_CR_ALGOMODE_0 | CRYP_CR_ALGOMODE_3)
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Key_Size CRYP Key Size
+  * @{
+  */
+
+#define CRYP_KEYSIZE_128B         0x00000000U
+#define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
+#define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Data_Type CRYP Data Type
+  * @{
+  */
+
+#define CRYP_DATATYPE_32B         0x00000000U
+#define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
+
+#define CRYP_NO_SWAP              CRYP_DATATYPE_32B      /*!< 32-bit data type (no swapping)        */
+#define CRYP_HALFWORD_SWAP        CRYP_DATATYPE_16B      /*!< 16-bit data type (half-word swapping) */
+#define CRYP_BYTE_SWAP            CRYP_DATATYPE_8B       /*!< 8-bit data type (byte swapping)       */
+#define CRYP_BIT_SWAP             CRYP_DATATYPE_1B       /*!< 1-bit data type (bit swapping)        */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Interrupt  CRYP and SAES peripherals interrupts
+  * @{
+  */
+
+#define CRYP_IT_INI       CRYP_IMSCR_INIM   /*!< CRYP peripheral input FIFO Interrupt */
+#define CRYP_IT_OUTI      CRYP_IMSCR_OUTIM  /*!< CRYP peripheral output FIFO Interrupt */
+
+#define CRYP_IT_CCFIE     SAES_IER_CCFIE    /*!< SAES peripheral computation Complete interrupt enable */
+#define CRYP_IT_RWEIE     SAES_IER_RWEIE    /*!< SAES peripheral read or write Error interrupt enable  */
+#define CRYP_IT_KEIE      SAES_IER_KEIE     /*!< SAES peripheral key error interrupt enable  */
+#define CRYP_IT_RNGEIE    SAES_IER_RNGEIE   /*!< SAES peripheral RNG error interrupt enable  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Flags CRYP & SAES Flags
+  * @{
+  */
+
+/* Flags in the SR register */
+#define CRYP_FLAG_IFEM     CRYP_SR_IFEM      /*!< CRYP peripheral Input FIFO is empty */
+#define CRYP_FLAG_IFNF     CRYP_SR_IFNF      /*!< CRYP peripheral Input FIFO is not Full */
+#define CRYP_FLAG_OFNE     CRYP_SR_OFNE      /*!< CRYP peripheral Output FIFO is not empty */
+#define CRYP_FLAG_OFFU     CRYP_SR_OFFU      /*!< CRYP peripheral Output FIFO is Full */
+#define CRYP_FLAG_KERF     CRYP_SR_KERF      /*!< CRYP peripheral Key error flag */
+/* Flags in the RISR register */
+#define CRYP_FLAG_OUTRIS   0x01000002U  /*!< Output FIFO service raw interrupt status */
+#define CRYP_FLAG_INRIS    0x01000001U  /*!< Input FIFO service raw interrupt status*/
+
+#define CRYP_FLAG_BUSY     CRYP_SR_BUSY      /*!< The CRYP peripheral is currently processing a block of data
+                                                 or a key preparation (for AES decryption). */
+
+
+#define CRYP_FLAG_KEYVALID CRYP_SR_KEYVALID  /*!< CRYP or SAES peripheral Key valid flag */
+
+#define SAES_FLAG_BUSY     SAES_SR_BUSY      /*!< The SAES peripheral is currently processing a block of data
+                                                  or a key preparation (for AES decryption). */
+
+#define CRYP_FLAG_WRERR    (SAES_SR_WRERR | 0x80000000U) /*!< SAES peripheral Write Error flag */
+#define CRYP_FLAG_RDERR    (SAES_SR_RDERR | 0x80000000U) /*!< SAES peripheral Read error flag */
+#define CRYP_FLAG_CCF      SAES_SR_CCF                   /*!< SAES peripheral Computation completed flag 
+                                                              as AES_ISR_CCF */
+#define CRYP_FLAG_KEIF     SAES_ISR_KEIF                 /*!< SAES peripheral Key error interrupt flag */
+#define CRYP_FLAG_RWEIF    SAES_ISR_RWEIF                /*!< SAES peripheral Read or Write error Interrupt flag */
+#define CRYP_FLAG_RNGEIF   SAES_ISR_RNGEIF               /*!< SAES peripheral RNG error Interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_CLEAR_Flags SAES peripheral Clear Flags
+  * @{
+  */
+#define CRYP_CLEAR_CCF      SAES_ICR_CCF    /*!< SAES peripheral clear Computation Complete Flag */
+#define CRYP_CLEAR_RWEIF    SAES_ICR_RWEIF  /*!< SAES peripheral clear Error Flag : RWEIF in SAES_ISR and
+                                              both RDERR and WRERR flags in SAES_SR */
+#define CRYP_CLEAR_KEIF     SAES_ICR_KEIF   /*!< SAES peripheral clear Key Error Flag: KEIF in SAES_ISR */
+#define CRYP_CLEAR_RNGEIF   SAES_ICR_RNGEIF /*!< SAES peripheral clear RNG error Flag  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+  * @{
+  */
+
+#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration 
+                                                                   to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration
+                                                                   to do only once */
+#define CRYP_KEYNOCONFIG               0x00000002U            /*!< Peripheral Key configuration to not do */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Key_Mode CRYP or SAES Key Mode
+  * @{
+  */
+
+#define CRYP_KEYMODE_NORMAL         0x00000000U         /*!< Normal key usage, Key registers are freely usable */
+#define CRYP_KEYMODE_WRAPPED        SAES_CR_KMOD_0      /*!< Only for SAES, Wrapped key: to encrypt 
+                                                             or decrypt AES keys */
+#define CRYP_KEYMODE_SHARED         SAES_CR_KMOD_1      /*!< Key shared by SAES peripheral */
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Key_Select SAES Key Select
+  * @{
+  */
+
+#define CRYP_KEYSEL_NORMAL       0x00000000U            /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */
+#define CRYP_KEYSEL_HW           SAES_CR_KEYSEL_0       /*!< Only for SAES, Hardware key : derived hardware 
+                                                             unique key (DHUK 256-bit) */
+#define CRYP_KEYSEL_SW           SAES_CR_KEYSEL_1       /*!< Only for SAES, Software key : boot hardware 
+                                                             key BHK (256-bit) */
+#define CRYP_KEYSEL_HSW          SAES_CR_KEYSEL_2       /*!< Only for SAES, DHUK XOR BHK Hardware unique 
+                                                             key XOR software key */
+#define CRYP_KEYSEL_AHK          (SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0)  /*!< Only for SAES, Software key : 
+                                                                      application hardware key AHK (128- or 256-bit) */
+#define CRYP_KEYSEL_DUK_AHK      (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_0)   /*!< Only for SAES, DHUK XOR AHK */
+#define CRYP_KEYSEL_TEST_KEY     (SAES_CR_KEYSEL_2|SAES_CR_KEYSEL_1|SAES_CR_KEYSEL_0) /*!< Test mode key (256-bit 
+                                                                               hardware constant key 0xA5A5...A5A5) */
+/**
+  * @}
+  */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+/** @defgroup CRYP_Key_Protection SAES Key Protection
+  * @{
+  */
+
+#define CRYP_KEYPROT_ENABLE         SAES_CR_KEYPROT     /*!< Only for SAES, Key can't be shared between 
+                                                             two applications with different security contexts */
+#define CRYP_KEYPROT_DISABLE        0x00000000U         /*!< Only for SAES, Key can be shared between 
+                                                             two applications with different security contexts */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Key_Shared SAES Key Shared with Peripheral
+  * @{
+  */
+
+#define CRYP_KEYSHARED_CRYP         0x00000000U     /*!< Only for SAES, key is shared with CRYP peripheral */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Mode SAES processing mode
+  * @{
+  */
+
+#define CRYP_MODE_ENCRYPT                0x00000000U             /*!< SAES peripheral encryption mode   */
+#define CRYP_MODE_KEY_DERIVATION         SAES_CR_MODE_0          /*!< SAES peripheral key derivation    */
+#define CRYP_MODE_DECRYPT                SAES_CR_MODE_1          /*!< SAES peripheral decryption mode   */
+
+/**
+  * @}
+  */
+#endif /* USE_HAL_SAES_ONLY */
+
+/** @defgroup CRYP_Mode SAES processing mode
+  * @{
+  */
+
+#define CRYP_OPERATINGMODE_ENCRYPT       0x00000000U             /*!< CRYP peripheral encryption mode   */
+#define CRYP_OPERATINGMODE_DECRYPT       CRYP_CR_ALGODIR         /*!< CRYP peripheral decryption mode   */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Inform about which IP is the current INSTANCE: CRYP or SAES.
+  * @param  INSTANCE: specifies the HW instance.
+  * @retval None
+  */
+#define IS_CRYP_INSTANCE(INSTANCE) ((INSTANCE) == CRYP)
+#define IS_SAES_INSTANCE(INSTANCE) ((INSTANCE) == SAES)
+
+/** @brief Reset CRYP handle state
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @retval None
+  */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;\
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                     }while(0)
+#else
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable/Disable the CRYP or SAES peripheral.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @retval None
+  */
+
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ? \
+                                       (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |=  CRYP_CR_CRYPEN) :\
+                                       (((SAES_TypeDef *)((__HANDLE__)->Instance))->CR |=  SAES_CR_EN))
+
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ? \
+                                        (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR &=  ~CRYP_CR_CRYPEN) :\
+                                        (((SAES_TypeDef *)((__HANDLE__)->Instance))->CR &=  ~SAES_CR_EN))
+
+/** @brief  Check whether the specified CRYP or SAES peripheral status flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+  *                                 or a key preparation (for AES decryption)
+  *            @arg @ref CRYP_FLAG_KEYVALID Key valid flag
+  *            @arg @ref CRYP_FLAG_KEIF Key error flag
+  *            @arg CRYP_FLAG_IFEM: Input FIFO is empty                           (CRYP peripheral only)
+  *            @arg CRYP_FLAG_IFNF: Input FIFO is not full                        (CRYP peripheral only)
+  *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending  (CRYP peripheral only)
+  *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty                      (CRYP peripheral only)
+  *            @arg CRYP_FLAG_OFFU: Output FIFO is full                           (CRYP peripheral only)
+  *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending (CRYP peripheral only)
+  *            @arg @ref CRYP_FLAG_WRERR Write Error flag                         (SAES peripheral only)
+  *            @arg @ref CRYP_FLAG_RDERR Read Error flag                          (SAES peripheral only)
+  *            @arg @ref CRYP_FLAG_CCF Computation Complete flag                  (SAES peripheral only)
+  *            @arg @ref CRYP_FLAG_RWEIF Read/write Error flag                    (SAES peripheral only)
+  *            @arg @ref CRYP_FLAG_RNGEIF RNG Error flag                          (SAES peripheral only)
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define CRYP_FLAG_MASK  0x0000001FU
+
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\
+                                                   ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((((CRYP_TypeDef *) \
+                                                       ((__HANDLE__)->Instance))))->SR \
+                                                       & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \
+                                                   ((__FLAG__) == CRYP_FLAG_BUSY )?((((((CRYP_TypeDef *) \
+                                                       ((__HANDLE__)->Instance))))->SR \
+                                                       & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \
+                                                   ((__FLAG__) == CRYP_FLAG_KEIF )?((((((CRYP_TypeDef *) \
+                                                       ((__HANDLE__)->Instance))))->SR \
+                                                       & (CRYP_FLAG_KERF)) == (CRYP_FLAG_KERF)) : \
+                                                   ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?(((((CRYP_TypeDef *) \
+                                                       ((__HANDLE__)->Instance))->RISR) & ((__FLAG__) & \
+                                                           CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+                                                    (((((CRYP_TypeDef *)((__HANDLE__)->Instance))->RISR) & ((__FLAG__)\
+                                                        & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) :\
+                                                   (\
+                                                    ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((SAES_TypeDef *)\
+                                                        (((SAES_TypeDef *)((__HANDLE__)->Instance))))->SR \
+                                                        & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \
+                                                    ((__FLAG__) == CRYP_FLAG_BUSY )?((((SAES_TypeDef *) \
+                                                        ((__HANDLE__)->Instance))->SR \
+                                                        & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \
+                                                    ((__FLAG__) == CRYP_FLAG_WRERR )?((((SAES_TypeDef *) \
+                                                        ((__HANDLE__)->Instance))->SR \
+                                                        & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \
+                                                        (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \
+                                                    ((__FLAG__) == CRYP_FLAG_RDERR )?((((SAES_TypeDef *) \
+                                                        ((__HANDLE__)->Instance))->SR \
+                                                        & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \
+                                                        (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \
+                                                    ((__FLAG__) == CRYP_FLAG_RNGEIF )?((((SAES_TypeDef *) \
+                                                        ((__HANDLE__)->Instance))->ISR \
+                                                        & (CRYP_FLAG_RNGEIF)) == (CRYP_FLAG_RNGEIF)) : \
+                                                    ((__FLAG__) == CRYP_FLAG_KEIF )?((((SAES_TypeDef *) \
+                                                        ((__HANDLE__)->Instance))->ISR \
+                                                        & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \
+                                                    ((__FLAG__) == CRYP_FLAG_RWEIF )?((((SAES_TypeDef *) \
+                                                        ((__HANDLE__)->Instance))->ISR \
+                                                        & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \
+                                                    ((((SAES_TypeDef *)((__HANDLE__)->Instance))->ISR & \
+                                                      (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))))
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+/** @brief  Clear the SAES peripheral pending status flag.
+  * @param  __HANDLE__ specifies the SAES handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_CLEAR_RWEIF Read (RDERR), Write (WRERR) or Read/write (RWEIF) Error  Flag Clear
+  *            @arg @ref CRYP_CLEAR_CCF Computation Complete Flag (CCF) Clear
+  *            @arg @ref CRYP_CLEAR_KEIF Key error interrupt flag clear
+  *            @arg @ref CRYP_CLEAR_RNGEIF RNG error interrupt flag clear
+  * @retval None
+  */
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->ICR,\
+                                                              (__FLAG__))
+#endif /* USE_HAL_SAES_ONLY */
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+/** @brief  Check whether the specified CRYP peripheral interrupt is set or not.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__: specifies the interrupt to check.
+  *         This parameter can be one of the following values:
+  *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
+  *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) ((((CRYP_TypeDef *)((__HANDLE__)->Instance))->MISR\
+                                                       & (__INTERRUPT__)) == (__INTERRUPT__))
+#endif /* USE_HAL_CRYP_ONLY */
+
+/**
+  * @brief  Enable the CRYP or SAES peripheral interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__:  Interrupt.
+  *         This parameter can be one of the following values:
+  *            @arg @ref  CRYP_IT_INI    Input FIFO service interrupt mask          (CRYP peripheral only)
+  *            @arg @ref  CRYP_IT_OUTI   Output FIFO service interrupt mask         (CRYP peripheral only)
+  *            @arg @ref  CRYP_IT_RWEIE  Error interrupt (used for RDERR and WRERR) (SAES peripheral only)
+  *            @arg @ref  CRYP_IT_CCFIE  Computation Complete interrupt             (SAES peripheral only)
+  *            @arg @ref  CRYP_IT_KEIE   Key error interrupt                        (SAES peripheral only)
+  *            @arg @ref  CRYP_IT_RNGEIE RNG interrupt                              (SAES peripheral only)
+  * @retval None
+  */
+
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\
+                                                          ((((CRYP_TypeDef *)((__HANDLE__)->Instance))->IMSCR) |= \
+                                                              (__INTERRUPT__)) : ((((SAES_TypeDef *) \
+                                                                  ((__HANDLE__)->Instance))->IER) |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the CRYP or SAES peripheral interrupt.
+  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __INTERRUPT__:  Interrupt.
+  *         This parameter can be one of the following values:
+  *            @arg @ref  CRYP_IT_INI    Input FIFO service interrupt mask          (CRYP peripheral only)
+  *            @arg @ref  CRYP_IT_OUTI   Output FIFO service interrupt mask         (CRYP peripheral only)
+  *            @arg @ref  CRYP_IT_RWEIE  Error interrupt (used for RDERR and WRERR) (SAES peripheral only)
+  *            @arg @ref  CRYP_IT_CCFIE  Computation Complete interrupt             (SAES peripheral only)
+  *            @arg @ref  CRYP_IT_KEIE   Key error interrupt                        (SAES peripheral only)
+  *            @arg @ref  CRYP_IT_RNGEIE RNG interrupt                              (SAES peripheral only)
+  * @retval None
+  */
+
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_CRYP_INSTANCE((__HANDLE__)->Instance)) ?\
+                                                          ((((CRYP_TypeDef *)((__HANDLE__)->Instance))->IMSCR) &= \
+                                                              ~(__INTERRUPT__)) : ((((SAES_TypeDef *) \
+                                                                  ((__HANDLE__)->Instance))->IER) &= ~(__INTERRUPT__)))
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+/** @brief  Check whether the specified SAES peripheral interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param __INTERRUPT__  interrupt source to check
+  *         This parameter can be one of the following values for TinyAES:
+  *            @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+  *            @arg @ref CRYP_IT_KEIE Key error interrupt
+  *            @arg @ref CRYP_IT_RNGEIE RNG error interrupt
+  * @retval State of interruption (TRUE or FALSE).
+  */
+
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((SAES_TypeDef *)((__HANDLE__)->Instance))->IER\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
+#endif /* USE_HAL_SAES_ONLY */
+/**
+  * @}
+  */
+
+/* Include CRYP HAL Extended module */
+#include "stm32n6xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+                                            pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
+#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group2
+  * @{
+  */
+
+/* encryption/decryption ***********************************/
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+                                   uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+                                   uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup CRYP_Exported_Functions_Group3
+  * @{
+  */
+/* Interrupt Handler functions  **********************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros   CRYP Private Macros
+  * @{
+  */
+
+/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
+  * @{
+  */
+
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM)  == CRYP_AES_ECB)   || \
+                                      ((ALGORITHM)  == CRYP_AES_CBC)   || \
+                                      ((ALGORITHM)  == CRYP_AES_CTR)   || \
+                                      ((ALGORITHM)  == CRYP_AES_GCM)   || \
+                                      ((ALGORITHM)  == CRYP_AES_CCM))
+
+#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
+                                  ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
+                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
+
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
+                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
+                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
+                                    ((DATATYPE) == CRYP_DATATYPE_1B))
+
+#define IS_CRYP_INIT(CONFIG) (((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+                              ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)   || \
+                              ((CONFIG) == CRYP_KEYNOCONFIG))
+
+#define IS_CRYP_KEYIVCONFIG(CONFIG) (((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+                                     ((KEYSIZE) == CRYP_KEYSIZE_192B)  || \
+                                     ((KEYSIZE) == CRYP_KEYSIZE_256B))
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+#define IS_CRYP_KEYMODE(MODE) (((MODE) == CRYP_KEYMODE_NORMAL) || \
+                               ((MODE) == CRYP_KEYMODE_SHARED))
+
+#define IS_SAES_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB)   || \
+                                      ((ALGORITHM) == CRYP_AES_CBC)   || \
+                                      ((ALGORITHM) == CRYP_AES_CTR)   || \
+                                      ((ALGORITHM) == CRYP_AES_GCM)   || \
+                                      ((ALGORITHM) == CRYP_AES_CCM))
+
+#define IS_SAES_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KEYSIZE_128B)  || \
+                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
+
+#define IS_SAES_DATATYPE(DATATYPE) (((DATATYPE) == SAES_DATATYPE_32B) || \
+                                    ((DATATYPE) == SAES_DATATYPE_16B) || \
+                                    ((DATATYPE) == SAES_DATATYPE_8B)  || \
+                                    ((DATATYPE) == SAES_DATATYPE_1B))
+
+#define IS_SAES_KEYMODE(MODE) (((MODE) == CRYP_KEYMODE_NORMAL)  || \
+                               ((MODE) == CRYP_KEYMODE_WRAPPED) || \
+                               ((MODE) == CRYP_KEYMODE_SHARED))
+
+#define IS_SAES_KEYPROT(PROTECTION) (((PROTECTION) == CRYP_KEYPROT_ENABLE)  || \
+                                     ((PROTECTION) == CRYP_KEYPROT_DISABLE))
+
+#define IS_SAES_KEYSEL(SELECTION) (((SELECTION) == CRYP_KEYSEL_NORMAL)   || \
+                                   ((SELECTION) == CRYP_KEYSEL_HW)       || \
+                                   ((SELECTION) == CRYP_KEYSEL_SW)       || \
+                                   ((SELECTION) == CRYP_KEYSEL_HSW)      || \
+                                   ((SELECTION) == CRYP_KEYSEL_AHK)      || \
+                                   ((SELECTION) == CRYP_KEYSEL_DUK_AHK)  || \
+                                   ((SELECTION) == CRYP_KEYSEL_TEST_KEY))
+
+#define IS_SAES_KEYSHARED(PERIPHERAL) ((PERIPHERAL) == CRYP_KEYSHARED_CRYP)
+/**
+  * @}
+  */
+#endif /* USE_HAL_SAES_ONLY */
+
+/** @defgroup SAES_CONV_Definitions SAES Private macros to convert input parameters from CRYP peripheral to
+     SAES peripheral format
+  * @{
+  */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+#define SAES_CONV_DATATYPE(__DATATYPE__) ((__DATATYPE__) >> (CRYP_CR_DATATYPE_Pos - SAES_CR_DATATYPE_Pos))
+
+#define SAES_CONV_KEYSIZE(__KEY__) (((__KEY__)\
+                                     & CRYP_CR_KEYSIZE_1) << (SAES_CR_KEYSIZE_Pos - (CRYP_CR_KEYSIZE_Pos + 1U)))
+
+#define SAES_CONV_ALGO(__ALGO__) (((__ALGO__)\
+                                   & (CRYP_CR_ALGOMODE_1 | CRYP_CR_ALGOMODE_0)) << (SAES_CR_CHMOD_Pos - \
+                                       CRYP_CR_ALGOMODE_Pos))
+#endif /* USE_HAL_SAES_ONLY */
+#define CRYP_CONV_ALGODIR(__ALGODIR__) (((__ALGODIR__)\
+                                         & SAES_CR_MODE_1) >> ((SAES_CR_MODE_Pos + 1U) - CRYP_CR_ALGODIR_Pos))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRYP_Private_Defines CRYP Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+#endif /* CRYP */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+#endif /* STM32N6xx_HAL_CRYP_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cryp_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cryp_ex.h
new file mode 100644
index 000000000..803538744
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_cryp_ex.h
@@ -0,0 +1,129 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYP HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_CRYP_EX_H
+#define STM32N6xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (CRYP)
+/** @addtogroup CRYPEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
+  * @{
+  */
+
+/**
+  * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+                                                    uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+                                                    uint32_t Timeout);
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t *Output,
+                                              uint32_t ID, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t ID,
+                                              uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t *Output, uint32_t Timeout);
+#endif /* USE_HAL_SAES_ONLY */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* CRYP */
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_CRYP_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dcmi.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dcmi.h
new file mode 100644
index 000000000..be4f33498
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dcmi.h
@@ -0,0 +1,698 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_dcmi.h
+  * @author  MCD Application Team
+  * @brief   Header file of DCMI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_DCMI_H
+#define STM32N6xx_HAL_DCMI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (DCMI)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DCMI DCMI
+  * @brief DCMI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Types DCMI Exported Types
+  * @{
+  */
+/**
+  * @brief  HAL DCMI State structures definition
+  */
+typedef enum
+{
+  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
+  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
+  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
+  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
+  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
+  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
+} HAL_DCMI_StateTypeDef;
+
+/**
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */
+typedef struct
+{
+  uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+  uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
+  uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
+  uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
+} DCMI_CodesInitTypeDef;
+
+/**
+  * @brief   DCMI Embedded Synchronisation UNMASK Init structure definition
+  */
+typedef struct
+{
+  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */
+  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */
+  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */
+} DCMI_SyncUnmaskTypeDef;
+/**
+  * @brief   DCMI Init structure definition
+  */
+typedef struct
+{
+  uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+                                             This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+  uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.
+                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity       */
+
+  uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity       */
+
+  uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.
+                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity       */
+
+  uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+                                             This parameter can be a value of @ref DCMI_Capture_Rate         */
+
+  uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
+
+  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the
+                                             line/frame end delimiter */
+
+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
+                                             This parameter can be a value of @ref DCMI_MODE_JPEG            */
+
+  uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface
+                                            This parameter can be a value of @ref DCMI_Byte_Select_Mode      */
+
+  uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd
+                                            This parameter can be a value of @ref DCMI_Byte_Select_Start     */
+
+  uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface
+                                            This parameter can be a value of @ref DCMI_Line_Select_Mode      */
+
+  uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd
+                                            This parameter can be a value of @ref DCMI_Line_Select_Start     */
+} DCMI_InitTypeDef;
+
+/**
+  * @brief  DCMI handle Structure definition
+  */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+typedef struct  __DCMI_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+{
+  DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
+
+  DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */
+
+  HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */
+
+  __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */
+
+  __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */
+
+  __IO uint32_t                 XferSize;            /*!< DMA transfer size            */
+
+  uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */
+
+  uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */
+
+  DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
+
+  __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+  void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Frame Event Callback */
+  void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Vsync Event Callback */
+  void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Line Event Callback  */
+  void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi);            /*!< DCMI Error Callback       */
+  void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);          /*!< DCMI Msp Init callback    */
+  void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Msp DeInit callback  */
+#endif  /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+} DCMI_HandleTypeDef;
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DCMI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DCMI_FRAME_EVENT_CB_ID    = 0x00U,    /*!< DCMI Frame Event Callback ID */
+  HAL_DCMI_VSYNC_EVENT_CB_ID    = 0x01U,    /*!< DCMI Vsync Event Callback ID */
+  HAL_DCMI_LINE_EVENT_CB_ID     = 0x02U,    /*!< DCMI Line Event Callback ID  */
+  HAL_DCMI_ERROR_CB_ID          = 0x03U,    /*!< DCMI Error Callback ID       */
+  HAL_DCMI_MSPINIT_CB_ID        = 0x04U,    /*!< DCMI MspInit callback ID     */
+  HAL_DCMI_MSPDEINIT_CB_ID      = 0x05U     /*!< DCMI MspDeInit callback ID   */
+
+} HAL_DCMI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL DCMI Callback pointer definition
+  */
+typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); /*!< pointer to a DCMI callback function */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Error_Code DCMI Error Code
+  * @{
+  */
+#define HAL_DCMI_ERROR_NONE             (0x00000000U)  /*!< No error              */
+#define HAL_DCMI_ERROR_OVR              (0x00000001U)  /*!< Overrun error         */
+#define HAL_DCMI_ERROR_SYNC             (0x00000002U)  /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT          (0x00000020U)  /*!< Timeout error         */
+#define HAL_DCMI_ERROR_DMA              (0x00000040U)  /*!< DMA error             */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#define HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U)  /*!< Invalid callback error */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
+  * @{
+  */
+#define DCMI_MODE_CONTINUOUS           (0x00000000U)          /*!< The received data are transferred continuously
+                                                                   into the destination memory through the DMA    */
+#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of 
+                                                                   frame and then transfers a single frame 
+                                                                   through the DMA */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
+  * @{
+  */
+#define DCMI_SYNCHRO_HARDWARE        (0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)
+                                                          is synchronized with the HSYNC/VSYNC signals               */
+#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized 
+                                                                 with synchronization codes embedded in the data flow */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
+  * @{
+  */
+#define DCMI_PCKPOLARITY_FALLING    (0x00000000U)      /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
+  * @{
+  */
+#define DCMI_VSPOLARITY_LOW     (0x00000000U)     /*!< Vertical synchronization active Low  */
+#define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
+  * @{
+  */
+#define DCMI_HSPOLARITY_LOW     (0x00000000U)     /*!< Horizontal synchronization active Low  */
+#define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
+  * @{
+  */
+#define DCMI_JPEG_DISABLE   (0x00000000U)    /*!< Mode JPEG Disabled  */
+#define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
+  * @{
+  */
+#define DCMI_CR_ALL_FRAME            (0x00000000U)      /*!< All frames are captured        */
+#define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
+#define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
+  * @{
+  */
+#define DCMI_EXTEND_DATA_8B     (0x00000000U)              /*!< Interface captures 8-bit data on every pixel clock  */
+#define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)  /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)  /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 |\
+                                            DCMI_CR_EDM_1))          /*!< Interface captures 14-bit data on every pixel clock */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
+  * @{
+  */
+#define DCMI_WINDOW_COORDINATE    (0x3FFFU)  /*!< Window coordinate */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Window_Height DCMI Window Height
+  * @{
+  */
+#define DCMI_WINDOW_HEIGHT    (0x1FFFU)  /*!< Window Height */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
+  * @{
+  */
+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
+#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Flags DCMI Flags
+  * @{
+  */
+
+/**
+  * @brief   DCMI SR register
+  */
+#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization 
+                                                                         between lines)   */
+#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization 
+                                                                         between frames) */
+#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                          */
+/**
+  * @brief   DCMI RIS register
+  */
+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */
+#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */
+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */
+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */
+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */
+/**
+  * @brief   DCMI MIS register
+  */
+#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked 
+                                   interrupt status */
+#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */
+#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */
+#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */
+#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
+  * @{
+  */
+#define DCMI_BSM_ALL                 (0x00000000U)             /*!< Interface captures all received data */
+#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte 
+                                                                    from the received data */
+#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
+#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 |\
+                                                 DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
+  * @{
+  */
+#define DCMI_OEBS_ODD               (0x00000000U) /*!< Interface captures first data from the frame/line start, 
+                                                       second one being dropped */
+#define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from 
+                                                                  the frame/line start, first one being dropped */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
+  * @{
+  */
+#define DCMI_LSM_ALL                 (0x00000000U) /*!< Interface captures all received lines */
+#define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
+  * @{
+  */
+#define DCMI_OELS_ODD               (0x00000000U) /*!< Interface captures first line from the frame start,
+                                                       second one being dropped */
+#define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start,
+                                                                  first one being dropped */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
+  * @{
+  */
+
+/** @brief Reset DCMI handle state
+  * @param  __HANDLE__ specifies the DCMI handle.
+  * @retval None
+  */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__)  do{                                             \
+                                                       (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
+                                                       (__HANDLE__)->MspInitCallback = NULL;       \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                     } while(0)
+#else
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the DCMI.
+  * @param  __HANDLE__ DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
+
+/**
+  * @brief  Disable the DCMI.
+  * @param  __HANDLE__ DCMI handle
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DCMI pending flag.
+  * @param  __HANDLE__ DCMI handle
+  * @param  __FLAG__ Get the specified flag.
+  *         This parameter can be one of the following values (no combination allowed)
+  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
+  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
+  *            @arg DCMI_FLAG_FNE: FIFO empty flag
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+  *            @arg DCMI_FLAG_LINERI: Line flag mask
+  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
+  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
+  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
+  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
+  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
+  * @retval The state of FLAG.
+  */
+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
+  ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
+   (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) :\
+   ((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DCMI pending flags.
+  * @param  __HANDLE__ DCMI handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
+  *            @arg DCMI_FLAG_LINERI: Line flag mask
+  * @retval None
+  */
+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DCMI interrupts.
+  * @param  __HANDLE__    DCMI handle
+  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval None
+  */
+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DCMI interrupts.
+  * @param  __HANDLE__ DCMI handle
+  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval None
+  */
+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DCMI interrupt has occurred or not.
+  * @param  __HANDLE__ DCMI handle
+  * @param  __INTERRUPT__ specifies the DCMI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval The state of INTERRUPT.
+  */
+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
+  * @{
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
+                                            pDCMI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
+/**
+  * @}
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
+                                          uint32_t YSize);
+HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi);
+uint32_t              HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+  * @{
+  */
+/** @defgroup DCMI_MIS_INDEX DCMI Mis Index
+  * @{
+  */
+#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_SR_INDEX  DCMI SR Index
+  * @{
+  */
+#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Macros DCMI Private Macros
+  * @{
+  */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
+                                   ((MODE) == DCMI_MODE_SNAPSHOT))
+
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
+                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))
+
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
+                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))
+
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))
+
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
+                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))
+
+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
+                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))
+
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
+                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
+
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
+                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \
+                                    ((DATA) == DCMI_EXTEND_DATA_14B))
+
+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
+
+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
+
+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
+                                       ((MODE) == DCMI_BSM_OTHER) || \
+                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \
+                                       ((MODE) == DCMI_BSM_ALTERNATE_2))
+
+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
+                                            ((POLARITY) == DCMI_OEBS_EVEN))
+
+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
+                                       ((MODE) == DCMI_LSM_ALTERNATE_2))
+
+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
+                                            ((POLARITY) == DCMI_OELS_EVEN))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* DCMI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_DCMI_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dcmipp.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dcmipp.h
new file mode 100644
index 000000000..7083d8702
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dcmipp.h
@@ -0,0 +1,2488 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_dcmipp.h
+  * @author  MCD Application Team
+  * @brief   Header file of DCMIPP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32N6xx_HAL_DCMIPP_H
+#define __STM32N6xx_HAL_DCMIPP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (DCMIPP)
+
+/** @addtogroup DCMIPP DCMIPP
+  * @brief DCMIPP HAL module driver
+  * @{
+  */
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DCMIPP_Exported_Types DCMIPP Exported Types
+  * @brief    DCMIPP Exported Types
+  * @{
+  */
+#define MAX_DATATYPE_NB  7U  /*!< DCMIPP CSI maximum number of data types  */
+/**
+  * @brief   DCMIPP Embedded Synchronisation Unmask codes structure definition
+  */
+typedef struct
+{
+  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */
+  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */
+  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */
+} DCMIPP_EmbeddedSyncUnmaskTypeDef;
+
+/**
+  * @brief   DCMIPP Embedded Synchronisation codes structure definition (CCIR656)
+  */
+typedef struct
+{
+  uint8_t FrameStartCode;  /*!< Specifies the code of the frame start delimiter. */
+  uint8_t LineStartCode;   /*!< Specifies the code of the line start delimiter.  */
+  uint8_t LineEndCode;     /*!< Specifies the code of the line end delimiter.    */
+  uint8_t FrameEndCode;    /*!< Specifies the code of the frame end delimiter.   */
+} DCMIPP_EmbeddedSyncCodesTypeDef;
+
+/**
+  * @brief  HAL DCMIPP CSI PIPE configuration structure definition
+  */
+typedef struct
+{
+  uint32_t DataTypeMode ; /*!< Configures the Data Type Mode
+                               This parameter can be a value from @ref DCMIPP_DataTypeMode    */
+  uint32_t DataTypeIDA ;  /*!< Configures the Data type selection ID-A
+                               This parameter can be a value from @ref DCMIPP_DataType        */
+  uint32_t DataTypeIDB ;  /*!< Configures the Data type selection ID-B
+                               This parameter can be a value from @ref DCMIPP_DataType        */
+} DCMIPP_CSI_PIPE_ConfTypeDef;
+/**
+  * @brief  HAL DCMIPP CSI configuration structure definition
+  */
+typedef struct
+{
+  uint32_t NumberOfLanes;     /*!< Configures the Number of Lanes
+                                   This parameter can be a value from @ref DCMIPP_CSI_Number_Of_Lanes */
+  uint32_t DataLaneMapping;   /*!< Configures the Data Lane Mapping
+                                   This parameter can be a value from @ref DCMIPP_CSI_DataLaneMapping */
+  uint32_t PHYBitrate;        /*!< Configures the Phy Bitrate
+                                   This parameter can be a value from @ref DCMIPP_CSI_PHYBitRate      */
+} DCMIPP_CSI_ConfTypeDef;
+/**
+  * @brief  HAL DCMIPP CSI Virtual Channel Filtering configuration structure definition
+  */
+typedef struct
+{
+  uint32_t DataTypeNB;                        /*!< Configures the Data Type number
+                                                   This parameter can be a value from @ref DCMIPP_CSI_DataTypeID     */
+  uint32_t DataTypeClass[MAX_DATATYPE_NB];    /*!< Configures the Data Type Class
+                                                   This parameter can be a value between 0 and 63                    */
+  uint32_t DataTypeFormat[MAX_DATATYPE_NB];   /*!< Configures the Data Type Class
+                                                   This parameter can be a value from @ref DCMIPP_CSI_DataTypeFormat */
+} DCMIPP_CSI_VCFilteringConfTypeDef;
+
+/**
+  * @brief  HAL DCMIPP CSI Timer configuration structure definition
+  */
+typedef struct
+{
+  uint32_t VirtualChannel;       /*!< The Virtual Channel ID
+                                      This parameter can be a value from @ref DCMIPP_Virtual_Channel      */
+  uint32_t StartPoint;           /*!< The Start Point of the counter
+                                      This parameter can be a value from @ref DCMIPP_CSI_Timer_StartPoint */
+  uint32_t Count;                /*!< Number of clock cycle to count from the start point
+                                      This parameter can be a value between 0 and 0x1FFFFFF               */
+} DCMIPP_CSI_TimerConfTypeDef;
+/**
+  * @brief  HAL DCMIPP CSI LineByte Counter configuration structure definition
+  */
+typedef struct
+{
+  uint32_t VirtualChannel;   /*!< Configures the Virtual Channel ID
+                                  This parameter can be a value from @ref DCMIPP_Virtual_Channel */
+  uint32_t LineCounter;      /*!< Configures the Line Number
+                                  This parameter can be a value between 0 and 65535              */
+  uint32_t ByteCounter;      /*!< Configures the Byte Number
+                                  This parameter can be a value between 0 and 65535              */
+} DCMIPP_CSI_LineByteCounterConfTypeDef;
+
+/**
+  * @brief  HAL DCMIPP Parallel configuration structure definition
+  */
+typedef struct
+{
+  uint32_t  Format;                             /*!< Configures the DCMIPP Format
+                                                  This parameter can be one value of @ref DCMIPP_Format              */
+  uint32_t  VSPolarity;                         /*!< Specifies the Vertical synchronization polarity: High or Low.
+                                                  This parameter can be a value of @ref DCMIPP_VSYNC_Polarity        */
+  uint32_t  HSPolarity;                         /*!< Specifies the Horizontal synchronization polarity: High or Low.
+                                                  This parameter can be a value of @ref DCMIPP_HSYNC_Polarity        */
+  uint32_t  PCKPolarity;                        /*!< Specifies the Pixel clock polarity: Falling or Rising.
+                                                  This parameter can be a value of @ref DCMIPP_PIXCK_Polarity        */
+  uint32_t  ExtendedDataMode ;                  /*!< Specifies the data width: 8-bit, 10-bit, 12-bit 14-bit or 16-bits.
+                                                  This parameter can be a value of @ref DCMIPP_Extended_Data_Mode    */
+  uint32_t  SynchroMode;                        /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+                                                  This parameter can be a value of @ref DCMIPP_Synchronization_Mode  */
+  DCMIPP_EmbeddedSyncCodesTypeDef SynchroCodes; /*!< Specifies the code of the line/frame start delimiter and the
+                                                  line/frame end delimiter                                           */
+  uint32_t  SwapBits;                           /*!< Enable or Disable the Swap Bits.
+                                                  This parameter can be a value of @ref DCMIPP_SWAP_BITS             */
+  uint32_t  SwapCycles;                         /*!<  Enable or Disable the Swap Cycles.
+                                                  This parameter can be a value of @ref DCMIPP_SWAP_CYCLES           */
+} DCMIPP_ParallelConfTypeDef;
+
+/**
+  * @brief  HAL DCMIPP Pipe configuration structure definition
+  */
+typedef struct
+{
+  uint32_t FrameRate;         /*!< Configures the DCMIPP Pipe Frame Rate
+                                   This parameter can be one value of @ref DCMIPP_Frame_Rates           */
+  uint32_t PixelPipePitch;    /*!< Configures the DCMIPP Pixel Pipe Pitch
+                                   This parameter can be one value from                                 */
+  uint32_t PixelPackerFormat; /*!< Configures the DCMIPP Pixel Pipe Format
+                                   This parameter can be one value from @ref DCMIPP_Pixel_Packer_Format */
+} DCMIPP_PipeConfTypeDef;
+
+/**
+  * @brief  HAL DCMIPP IPPLUG configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Client;                      /*!< Configures the DCMIPP IPPLUG Client
+                                             This parameter can be a value from @ref DCMIPP_IPPLUG_Client      */
+  uint32_t MemoryPageSize;              /*!< Configures the DCMIPP IPPLUG Memory page size
+                                             This parameter can be a value from @ref DCMIPP_Memory_Page_Size   */
+  uint32_t Traffic;                     /*!< Configures the DCMIPP IPPLUG Traffic
+                                             This parameter can be a value from @ref DCMIPP_Traffic_Burst_Size */
+  uint32_t MaxOutstandingTransactions ; /*!< Configures the DCMIPP IPPLUG Maximum outstanding transactions
+                                             This parameter can be a value from
+                                             DCMIPP_Maximum_Outstanding_Transactions                           */
+  uint32_t DPREGStart;                  /*!< Configures the End word of the FIFO of Clientx
+                                             This parameter can be a value between 0 and  0x3FF                */
+  uint32_t DPREGEnd;                    /*!< Configures the Start word of the FIFO of Clientx
+                                             This parameter can be a value between 0 and  0x3FF                */
+  uint32_t WLRURatio;                   /*!< Configures the DCMIPP Ratio for WLRU arbitration
+                                             This parameter can be a value between 0 and 15                    */
+} DCMIPP_IPPlugConfTypeDef;
+
+/**
+  * @brief  HAL DCMIPP Crop configuration structure definition
+  */
+typedef struct
+{
+  uint32_t VStart;   /*!< Configures the DCMIPP Crop Vertical Start
+                          This parameter can be one value between 0 and 4095          */
+  uint32_t HStart;   /*!< Configures the DCMIPP Crop Horizontal Start
+                          This parameter can be one value between 0 and 4095          */
+  uint32_t VSize;    /*!< Configures the DCMIPP Crop Vertical Size
+                          This parameter can be one value between 0 and 4095          */
+  uint32_t HSize;    /*!< Configures the DCMIPP Crop Horizontal Size
+                          This parameter can be one value between 1 and 4095          */
+  uint32_t PipeArea; /*!< Configures the DCMIPP Crop Area for the pipe0
+                          This parameter can be one value of @ref DCMIPP_Crop_Area    */
+} DCMIPP_CropConfTypeDef;
+
+typedef struct
+{
+  uint32_t VStart;    /*!< Configures the DCMIPP Statistic Extraction Vertical Start
+                           This parameter can be one value between 0 and 4095                     */
+  uint32_t HStart;    /*!< Configures the DCMIPP Statistic Extraction Horizontal Start
+                           This parameter can be one value between 0 and 4095                     */
+  uint32_t VSize;     /*!< Configures the DCMIPP Statistic Extraction Vertical Size
+                           This parameter can be one value between 0 and 4095                     */
+  uint32_t HSize;     /*!< Configures the DCMIPP Statistic Extraction Horizontal Size
+                           This parameter can be one value between 0 and 4095                     */
+} DCMIPP_StatisticExtractionAreaConfTypeDef;
+
+typedef struct
+{
+  uint32_t Mode;      /*!< Configures the DCMIPP Statistic Extraction Mode
+                           This parameter can be a value from @ref DCMIPP_Statistics_Extraction_Mode   */
+  uint32_t Source;    /*!< Configures the DCMIPP Statistic Extraction Source
+                           This parameter can be a value from @ref DCMIPP_Statistics_Extraction_Source */
+  uint32_t Bins;      /*!< Configures the DCMIPP Statistic Extraction Bins
+                           This parameter can be a value from @ref DCMIPP_Statistics_Extraction_Bins   */
+} DCMIPP_StatisticExtractionConfTypeDef;
+
+
+typedef struct
+{
+  uint8_t ShiftRed;        /*!< Configures the DCMIPP Exposure Shift Red
+                                This parameter can be one value between 0 and 7    */
+  uint8_t MultiplierRed;   /*!< Configures the DCMIPP Exposure Multiplier Red
+                                This parameter can be one value between 0 and 127 */
+  uint8_t ShiftGreen;      /*!< Configures the DCMIPP Exposure Shift Green
+                                This parameter can be one value between 0 and 7    */
+  uint8_t MultiplierGreen; /*!< Configures the DCMIPP Exposure Multiplier Green
+                                This parameter can be one value between 0 and 127 */
+  uint8_t ShiftBlue;       /*!< Configures the DCMIPP Exposure Shift Blue
+                                This parameter can be one value between 0 and 7    */
+  uint8_t MultiplierBlue;  /*!< Configures the DCMIPP Exposure Multiplier Blue
+                                This parameter can be one value between 0 and 127 */
+} DCMIPP_ExposureConfTypeDef;
+
+typedef struct
+{
+  uint8_t LUM_0;    /*!< Luminance increase for input luminance of 0
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_32;   /*!< Luminance increase for input luminance of 32
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_64;   /*!< Luminance increase for input luminance of 64
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_96;   /*!< Luminance increase for input luminance of 96
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_128;  /*!< Luminance increase for input luminance of 128
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_160;  /*!< Luminance increase for input luminance of 160
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_192;  /*!< Luminance increase for input luminance of 192
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_224;  /*!< Luminance increase for input luminance of 224
+                         This parameter can be one value between 0 and 31 */
+  uint8_t LUM_256;  /*!< Luminance increase for input luminance of 256
+                         This parameter can be one value between 0 and 31 */
+} DCMIPP_ContrastConfTypeDef;
+
+typedef struct
+{
+  uint32_t VLineStrength;  /*!< Strength of the vertical line detection
+                                This parameter can be a value from @ref DCMIPP_RAWBayer2RGB_Strength */
+  uint32_t HLineStrength;  /*!< Strength of the horizontal line detection
+                                This parameter can be a value from @ref DCMIPP_RAWBayer2RGB_Strength */
+  uint32_t RawBayerType;   /*!< Raw Bayer type
+                                This parameter can be a value from @ref DCMIPP_RAWBayer2RGB_Type     */
+  uint32_t PeakStrength;   /*!< Strength of the peak detection
+                                This parameter can be a value from @ref DCMIPP_RAWBayer2RGB_Strength */
+  uint32_t EdgeStrength;   /*!< Strength of the edge detection
+                                This parameter can be a value from @ref DCMIPP_RAWBayer2RGB_Strength */
+} DCMIPP_RawBayer2RGBConfTypeDef;
+
+/**
+   * @brief  Color Conversion parameters
+   */
+typedef struct
+{
+  FunctionalState ClampOutputSamples;  /*!< Clamp the output samples depending on type
+                                            This parameter can be ENABLE or DISABLE */
+  uint8_t         OutputSamplesType;   /*!< Output samples type used while clamp is activated
+                                            This parameter can be a value from @ref DCMIPP_OutputSamplesType */
+  int16_t RR;                          /*!< Coefficient Row 1 Column 1 of the matrix
+                                            This parameter can be a value from -1023 to 1023 */
+  int16_t RG;                          /*!< Coefficient Row 1 Column 2 of the matrix
+                                            This parameter can be a value from -1023 to 1023 */
+  int16_t RB;                          /*!< Coefficient Row 1 Column 3 of the matrix
+                                            This parameter can be a value from -511 to 511   */
+  int16_t RA;                          /*!< Coefficient Row 1 of the added Column
+                                            This parameter can be a value from -511 to 511   */
+  int16_t GR;                          /*!< Coefficient Row 2 Column 1 of the matrix
+                                            This parameter can be a value from -1023 to 1023 */
+  int16_t GG;                          /*!< Coefficient Row 2 Column 2 of the matrix
+                                            This parameter can be a value from -1023 to 1023 */
+  int16_t GB;                          /*!< Coefficient Row 2 Column 3 of the matrix
+                                            This parameter can be a value from -511 to 511   */
+  int16_t GA;                          /*!< Coefficient Row 2 of the added Column
+                                            This parameter can be a value from -511 to 511   */
+  int16_t BR;                          /*!< Coefficient Row 3 Column 1 of the matrix
+                                            This parameter can be a value from -1023 to 1023 */
+  int16_t BG;                          /*!< Coefficient Row 3 Column 2 of the matrix
+                                             This parameter can be a value -1023 to 1023     */
+  int16_t BB;                          /*!< Coefficient Row 3 Column 3 of the matrix
+                                            This parameter can be a value from -511 to 511   */
+  int16_t BA;                          /*!< Coefficient Row 3 of the added Column
+                                            This parameter can be a value from -511 to 511   */
+} DCMIPP_ColorConversionConfTypeDef;
+
+/**
+   * @brief  Region Of Interest Structure
+   */
+typedef struct
+{
+  uint32_t VStart;           /*!< Configures the DCMIPP Region Of Interest Vertical Start
+                                  This parameter can be one value between 0 and 4095                      */
+  uint32_t HStart;           /*!< Configures the DCMIPP Region Of Interest Horizontal Start
+                                  This parameter can be one value between 0 and 4095                      */
+  uint32_t VSize;            /*!< Configures the DCMIPP Region Of Interest Vertical Size
+                                  This parameter can be one value between 0 and 4095                      */
+  uint32_t HSize;            /*!< Configures the DCMIPP Region Of Interest Horizontal Size
+                                  This parameter can be one value between 0 and 4095                      */
+  uint32_t LineSizeWidth;    /*!< Configures the DCMIPP Region Of Interest Line Size Width
+                                  This parameter can be a value from @ref DCMIPP_Region_Of_Interest_Line_Width */
+  uint32_t RegionOfInterest; /*!< Configures the DCMIPP Region Of Interest
+                                  This parameter can be a value from @ref DCMIPP_Region_Of_Interest       */
+  uint8_t  ColorLineRed;     /*!< Configures the DCMIPP Region Of Interest Line Color : Red Component
+                                  This parameter can be one value between 0 and 4095                      */
+  uint8_t  ColorLineGreen;   /*!< Configures the DCMIPP Region Of Interest Line Color : Green Component
+                                  This parameter can be one value between 0 and 4095                      */
+  uint8_t  ColorLineBlue;    /*!< Configures the DCMIPP Region Of Interest Line Color : Blue Component
+                                  This parameter can be one value between 0 and 4095                      */
+} DCMIPP_RegionOfInterestConfTypeDef;
+
+/**
+   * @brief  Black Level parameters
+   */
+typedef struct
+{
+  uint8_t RedCompBlackLevel;    /*!< Black value register to red component
+                                  This parameter can be one value between 0 and 255 */
+  uint8_t GreenCompBlackLevel;  /*!< Black value register to green component
+                                  This parameter can be one value between 0 and 255 */
+  uint8_t BlueCompBlackLevel;   /*!< Black value register to blue component
+                                  This parameter can be one value between 0 and 255 */
+} DCMIPP_BlackLevelConfTypeDef;
+
+/**
+  * @brief  HAL DCMIPP
+  */
+typedef struct
+{
+  uint32_t VSize;       /*!< Configures the DCMIPP Downsize Vertical Size
+                             This parameter can be one value between 0 and 4095     */
+  uint32_t HSize;       /*!< Configures the DCMIPP Downsize Horizontal Size
+                             This parameter can be one value between 0 and 4095     */
+  uint32_t VRatio;      /*!< Configures the DCMIPP Downsize Vertical Ratio
+                             This parameter can be one value between 0 and 4095     */
+  uint32_t HRatio;      /*!< Configures the DCMIPP Downsize Horizontal Ratio
+                             This parameter can be one value between 0 and 4095     */
+  uint32_t VDivFactor;  /*!< Configures the DCMIPP Downsize Vertical Division Factor
+                             This parameter can be one value between 0 and 4095     */
+  uint32_t HDivFactor;  /*!< Configures the DCMIPP Downsize Horizontal Division Factor
+                             This parameter can be one value between 0 and 4095     */
+} DCMIPP_DownsizeTypeDef;
+
+typedef struct
+{
+  uint32_t VRatio;  /*!< Configures the DCMIPP Downsize Vertical Size
+                         This parameter can be  a value from @ref DCMIPP_PIPE_Vertical_Decimation_Ratio   */
+  uint32_t HRatio;  /*!< Configures the DCMIPP Downsize Vertical Size
+                         This parameter can be  a value from @ref DCMIPP_PIPE_Horizontal_Decimation_Ratio */
+} DCMIPP_DecimationConfTypeDef;
+
+typedef struct
+{
+  uint32_t YAddress;     /*!< Y Frame Buffer address  */
+  uint32_t UVAddress;    /*!< UV Frame Buffer address */
+} DCMIPP_SemiPlanarDstAddressTypeDef;
+
+typedef struct
+{
+  uint32_t YAddress;    /*!< Y Frame Buffer address */
+  uint32_t UAddress;    /*!< U Frame Buffer address */
+  uint32_t VAddress;    /*!< V Frame Buffer address */
+} DCMIPP_FullPlanarDstAddressTypeDef;
+
+/**
+  * @brief  HAL DCMIPP State enumeration definition
+  */
+typedef enum
+{
+  HAL_DCMIPP_STATE_RESET = 0x00U,  /*!< DCMIPP not yet initialized or disabled  */
+  HAL_DCMIPP_STATE_INIT  = 0x01U,  /*!< DCMIPP initialized                      */
+  HAL_DCMIPP_STATE_READY = 0x02U,  /*!< DCMIPP configured and ready for use     */
+  HAL_DCMIPP_STATE_BUSY  = 0x03U,  /*!< DCMIPP internal processing is ongoing   */
+  HAL_DCMIPP_STATE_ERROR = 0x04U,  /*!< DCMIPP state error                      */
+} HAL_DCMIPP_StateTypeDef;
+
+/**
+  * @brief  HAL DCMIPP Pipe State enumeration definition
+  */
+
+typedef enum
+{
+  HAL_DCMIPP_PIPE_STATE_RESET             = 0x00U,  /*!< DCMIPP Pipe not yet initialized or disabled */
+  HAL_DCMIPP_PIPE_STATE_READY             = 0x01U,  /*!< DCMIPP Pipe initialized and ready for use   */
+  HAL_DCMIPP_PIPE_STATE_BUSY              = 0x02U,  /*!< DCMIPP internal processing is ongoing       */
+  HAL_DCMIPP_PIPE_STATE_SUSPEND           = 0x03U,  /*!< DCMIPP pipe process is suspended            */
+  HAL_DCMIPP_PIPE_STATE_ERROR             = 0x04U,  /*!< DCMIPP pipe error state                     */
+} HAL_DCMIPP_PipeStateTypeDef;
+
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DCMIPP common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DCMIPP_MSPINIT_CB_ID                = 0x00U,    /*!< DCMIPP MspInit callback ID                 */
+  HAL_DCMIPP_MSPDEINIT_CB_ID              = 0x01U,    /*!< DCMIPP MspDeInit callback ID               */
+  HAL_DCMIPP_ERROR_CB_ID                  = 0x02U,    /*!< DCMIPP Error callback ID                   */
+} HAL_DCMIPP_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL DCMIPP pipe Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID       = 0x01U,    /*!< DCMIPP Pipe Limit event callback ID        */
+  HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID        = 0x02U,    /*!< DCMIPP Pipe Line event callback ID         */
+  HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID       = 0x03U,    /*!< DCMIPP Pipe Frame event callback ID        */
+  HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID       = 0x04U,    /*!< DCMIPP Pipe Vsync event callback ID        */
+  HAL_DCMIPP_PIPE_ERROR_CB_ID             = 0x05U,    /*!< DCMIPP Pipe Error callback ID              */
+} HAL_DCMIPP_PIPE_CallbackIDTypeDef;
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+
+/**
+  * @brief  HAL DCMIPP handle structures definition
+  */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+typedef struct __DCMIPP_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+{
+  DCMIPP_TypeDef                    *Instance;                                             /*!< Register the DCMIPP base
+                                                                                                address               */
+  __IO HAL_DCMIPP_StateTypeDef      State;                                                 /*!< DCMIPP state          */
+  __IO HAL_DCMIPP_PipeStateTypeDef  PipeState[DCMIPP_NUM_OF_PIPES];                        /*!< DCMIPP Pipes state    */
+  __IO uint32_t                     ErrorCode;                                             /*!< DCMIPP Error code     */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+  void (* PIPE_FrameEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Frame Event
+                                                                                                Callback              */
+  void (* PIPE_VsyncEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Vsync Event
+                                                                                                Callback              */
+  void (* PIPE_LineEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);  /*!< DCMIPP Pipe Line Event
+                                                                                                Callback              */
+  void (* PIPE_LimitEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< DCMIPP Pipe Limit Event
+                                                                                                Callback              */
+  void (* PIPE_ErrorCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);      /*!< DCMIPP Pipe Error
+                                                                                                Callback              */
+  void (* ErrorCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp);                         /*!< DCMIPP Error Callback  */
+  void (* MspInitCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp);                       /*!< DCMIPP Msp Init
+                                                                                                Callback              */
+  void (* MspDeInitCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp);                     /*!< DCMIPP Msp DeInit
+                                                                                                Callback              */
+  void (* StartOfFrameEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel); /*!< DCMIPP CSI
+                                                                                        Start Of Frame Event Callback */
+  void (* EndOfFrameEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel); /*!< DCMIPP CSI
+                                                                                          End Of Frame Event Callback */
+  void (* TimerCounterEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer); /*!< DCMIPP CSI
+                                                                                         Timer Counter Event Callback */
+  void (* LineByteEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter); /*!< DCMIPP CSI Line/Byte
+                                                                                                 Event Callback       */
+  void (* LineErrorCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp, uint32_t DataLane); /*!< DCMIPP CSI Line Error
+                                                                                              Event Callback          */
+  void (* ClockChangerFifoFullEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP CSI Clock changer
+                                                                                           Fifo Event Callback        */
+  void (* ShortPacketDetectionEventCallback)(struct __DCMIPP_HandleTypeDef *hdcmipp); /*!< DCMIPP CSI Short Packet
+                                                                                           detection Event Callback   */
+#endif  /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+} DCMIPP_HandleTypeDef;
+
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DCMIPP Callback pointer definition
+  */
+typedef void (*pDCMIPP_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp); /*!< Pointer to a DCMIPP common callback
+                                                                              function */
+typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe); /*!< Pointer to a DCMIPP
+                                                                                               Pipe callback function */
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMIPP_Exported_Constants DCMIPP Exported Constants
+  * @brief    DCMIPP Exported constants
+  * @{
+  */
+
+/** @defgroup DCMIPP_Pipes DCMIPP Pipes
+  * @{
+  */
+#define  DCMIPP_PIPE0      0U     /*!< DCMIPP Pipe0 (Dump pipe)       */
+#define  DCMIPP_PIPE1      1U     /*!< DCMIPP Pipe1 (Main Pipe)       */
+#define  DCMIPP_PIPE2      2U     /*!< DCMIPP Pipe2 (Ancillary pipe)  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Error_Codes DCMIPP Error Codes
+  * @{
+  */
+#define HAL_DCMIPP_ERROR_NONE            (0x00000000U)             /*!< No error                  */
+#define HAL_DCMIPP_ERROR_AXI_TRANSFER    (0x00000001U)             /*!< IPPLUG AXI Transfer error */
+#define HAL_DCMIPP_ERROR_PARALLEL_SYNC   (0x00000002U)             /*!< Synchronization error     */
+#define HAL_DCMIPP_ERROR_PIPE0_LIMIT     (0x00000004U)             /*!< Limit error on pipe0      */
+#define HAL_DCMIPP_ERROR_PIPE0_OVR       (0x00000008U)             /*!< Overrun error on pipe0    */
+#define HAL_DCMIPP_ERROR_PIPE1_OVR       (0x00000010U)             /*!< Overrun error on pipe1    */
+#define HAL_DCMIPP_ERROR_PIPE2_OVR       (0x00000020U)             /*!< Overrun error on pipe2    */
+
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+#define  HAL_DCMIPP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error  */
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+
+#define HAL_DCMIPP_CSI_ERROR_NONE            (0x00000080U)       /*!< No error                               */
+#define HAL_DCMIPP_CSI_ERROR_SYNC            (0x00000100U)       /*!< Synchronization error                  */
+#define HAL_DCMIPP_CSI_ERROR_WDG             (0x00000200U)       /*!< Watchdog Error                         */
+#define HAL_DCMIPP_CSI_ERROR_SPKT            (0x00000400U)       /*!< Shorter Packet than expected Error     */
+#define HAL_DCMIPP_CSI_ERROR_DATA_ID         (0x00000800U)       /*!< Data ID Information Error              */
+#define HAL_DCMIPP_CSI_ERROR_CECC            (0x00001000U)       /*!< Corrected ECC Error                    */
+#define HAL_DCMIPP_CSI_ERROR_ECC             (0x00002000U)       /*!< ECC Error                              */
+#define HAL_DCMIPP_CSI_ERROR_CRC             (0x00004000U)       /*!< CRC Error                              */
+#define HAL_DCMIPP_CSI_ERROR_DPHY_CTRL       (0x00008000U)       /*!< Error Control on data line (0 OR 1)    */
+#define HAL_DCMIPP_CSI_ERROR_DPHY_LP_SYNC    (0x00010000U)       /*!< Low-Power data transmssion Synchronisation
+                                                                      Error on data line (0 OR 1)   */
+#define HAL_DCMIPP_CSI_ERROR_DPHY_ESCAPE     (0x00020000U)       /*!< Escape Entry Error on data line (0 OR 1) */
+#define HAL_DCMIPP_CSI_ERROR_SOT_SYNC        (0x00040000U)       /*!< SOT Synchronisation Error on data line(0 OR 1) */
+#define HAL_DCMIPP_CSI_ERROR_SOT             (0x00080000U)       /*!< SOT Error on data line (0 OR 1)        */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Capture_Mode DCMIPP Capture Mode
+  * @{
+  */
+#define  DCMIPP_MODE_CONTINUOUS   0U                      /*!< DCMIPP continuous mode (preview) */
+#define  DCMIPP_MODE_SNAPSHOT     DCMIPP_P0FCTCR_CPTMODE  /*!< DCMIPP snapshot mode             */
+/**
+  * @}
+  */
+
+/**
+  * @defgroup  DCMIPP_modes (DCMI or CSI): modes are exclusive
+  * @{
+  */
+#define  DCMIPP_PARALLEL_MODE   (0x00U << DCMIPP_CMCR_INSEL_Pos)  /*!< DCMIPP Parallel (DCMI) mode */
+#define  DCMIPP_SERIAL_MODE     (0x01U << DCMIPP_CMCR_INSEL_Pos)  /*!< DCMIPP CSI mode             */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_IPPLUG_Client DCMIPP IPPLUG Client
+  * @{
+  */
+#define DCMIPP_CLIENT1  1U /*!< Client 1 identifier */
+#define DCMIPP_CLIENT2  2U /*!< Client 2 identifier */
+#define DCMIPP_CLIENT3  3U /*!< Client 3 identifier */
+#define DCMIPP_CLIENT4  4U /*!< Client 4 identifier */
+#define DCMIPP_CLIENT5  5U /*!< Client 5 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Traffic_Burst_Size DCMIPP Traffic Burst Size
+  * @{
+  */
+#define DCMIPP_TRAFFIC_BURST_SIZE_8BYTES   0U                                   /*!< Traffic Burst size 8 Bytes   */
+#define DCMIPP_TRAFFIC_BURST_SIZE_16BYTES  (0x01U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 16 Bytes  */
+#define DCMIPP_TRAFFIC_BURST_SIZE_32BYTES  (0x02U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 32 Bytes  */
+#define DCMIPP_TRAFFIC_BURST_SIZE_64BYTES  (0x03U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 64 Bytes  */
+#define DCMIPP_TRAFFIC_BURST_SIZE_128BYTES (0x04U << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< Traffic Burst size 128 Bytes */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Memory_Page_Size DCMIPP Memory Page Size
+  * @{
+  */
+#define DCMIPP_MEMORY_PAGE_SIZE_64BYTES  0U                                     /*!< Memory Page size 64 Bytes  */
+#define DCMIPP_MEMORY_PAGE_SIZE_128BYTES (0x01U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 128 Bytes */
+#define DCMIPP_MEMORY_PAGE_SIZE_256BYTES (0x02U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 256 Bytes */
+#define DCMIPP_MEMORY_PAGE_SIZE_512BYTES (0x03U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 512 Bytes */
+#define DCMIPP_MEMORY_PAGE_SIZE_1KBYTES  (0x04U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 1 Bytes   */
+#define DCMIPP_MEMORY_PAGE_SIZE_2KBYTES  (0x05U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 2 Bytes   */
+#define DCMIPP_MEMORY_PAGE_SIZE_4KBYTES  (0x06U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 4 Bytes   */
+#define DCMIPP_MEMORY_PAGE_SIZE_8KBYTES  (0x07U << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< Memory Page size 8 Bytes   */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Maximum_Outstanding_Transactions DCMIPP Maximum Outstanding Transactions
+  * @{
+  */
+#define DCMIPP_OUTSTANDING_TRANSACTION_NONE 0U    /*!< Nooutstanding transaction limitation*/
+#define DCMIPP_OUTSTANDING_TRANSACTION_2    0x01U /*!< Two outstanding transactions        */
+#define DCMIPP_OUTSTANDING_TRANSACTION_3    0x02U /*!< Three outstanding transactions      */
+#define DCMIPP_OUTSTANDING_TRANSACTION_4    0x03U /*!< Four outstanding transactions       */
+#define DCMIPP_OUTSTANDING_TRANSACTION_5    0x04U /*!< 5 outstanding transactions          */
+#define DCMIPP_OUTSTANDING_TRANSACTION_6    0x05U /*!< 6 outstanding transactions          */
+#define DCMIPP_OUTSTANDING_TRANSACTION_7    0x06U /*!< 7 outstanding transactions          */
+#define DCMIPP_OUTSTANDING_TRANSACTION_8    0x07U /*!< 8 outstanding transactions          */
+#define DCMIPP_OUTSTANDING_TRANSACTION_9    0x08U /*!< 9 outstanding transactions          */
+#define DCMIPP_OUTSTANDING_TRANSACTION_10   0x09U /*!< 10 outstanding transactions         */
+#define DCMIPP_OUTSTANDING_TRANSACTION_11   0x0AU /*!< 11 outstanding transactions         */
+#define DCMIPP_OUTSTANDING_TRANSACTION_12   0x0BU /*!< 12 outstanding transactions         */
+#define DCMIPP_OUTSTANDING_TRANSACTION_13   0x0CU /*!< 13 outstanding transactions         */
+#define DCMIPP_OUTSTANDING_TRANSACTION_14   0x0DU /*!< 14 outstanding transactions         */
+#define DCMIPP_OUTSTANDING_TRANSACTION_15   0x0EU /*!< 15 outstanding transactions         */
+#define DCMIPP_OUTSTANDING_TRANSACTION_16   0x0FU /*!< 16 outstanding transactions         */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Frame_Rates  DCMIPP Frame Rates
+  * @{
+  */
+#define DCMIPP_FRAME_RATE_ALL       0U                               /*!< All frames captured     */
+#define DCMIPP_FRAME_RATE_1_OVER_2  (1U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 2 captured */
+#define DCMIPP_FRAME_RATE_1_OVER_4  (2U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 4 captured */
+#define DCMIPP_FRAME_RATE_1_OVER_8  (3U << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 1 frame over 8 captured */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Crop_Area  DCMIPP Crop Area
+  * @{
+  */
+#define DCMIPP_POSITIVE_AREA  0U                    /*!< Positive Area chosen for crop */
+#define DCMIPP_NEGATIVE_AREA  DCMIPP_P0SCSZR_POSNEG /*!< Negative Area chosen for crop */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Virtual_Channel DCMIPP Virtual Channel
+  * @{
+  */
+#define DCMIPP_VIRTUAL_CHANNEL0   0U /*!< DCMIPP Virtual Channel 0 */
+#define DCMIPP_VIRTUAL_CHANNEL1   1U /*!< DCMIPP Virtual Channel 1 */
+#define DCMIPP_VIRTUAL_CHANNEL2   2U /*!< DCMIPP Virtual Channel 2 */
+#define DCMIPP_VIRTUAL_CHANNEL3   3U /*!< DCMIPP Virtual Channel 3 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_DataTypeMode DCMIPP DCMIPP Data Type Mode
+  * @{
+  */
+#define DCMIPP_DTMODE_DTIDA                (0U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< Only flow DTIDA from the selected VC
+                                                                                 is forwarded in the pipe */
+#define DCMIPP_DTMODE_DTIDA_OR_DTIDB       (1U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< Flows DTIDA and/or DTIDB from the
+                                                                                selected VC are forwarded in the pipe */
+#define DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB (2U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< All data types from the selected VC
+                                                                                (except the DTIDA or DTIDB) are
+                                                                                 forwarded in the pipe,
+                                                                                 only for Pipe0 */
+#define DCMIPP_DTMODE_ALL                  (3U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< All data types of the selected virtual
+                                                                                 channel VC are forwarded in the pipe,
+                                                                                 only for Pipe0 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_DataTypeSelection DCMIPP Data Type Selection
+  * @{
+  */
+#define DCMIPP_DTSELECT_IDA  DCMIPP_P0FSCR_DTIDA_Pos  /*!< Data type selection ID A */
+#define DCMIPP_DTSELECT_IDB  DCMIPP_P0FSCR_DTIDB_Pos  /*!< Data type selection ID B */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_DataType DCMIPP  Data Type
+  * @{
+  */
+#define DCMIPP_DT_YUV420_8   0x18U   /*!< DCMIPP Data Type YUV420 8bit  */
+#define DCMIPP_DT_YUV420_10  0x19U   /*!< DCMIPP Data Type YUV420 8bit  */
+#define DCMIPP_DT_YUV422_8   0x1EU   /*!< DCMIPP Data Type YUV422 8bit  */
+#define DCMIPP_DT_YUV422_10  0x1FU   /*!< DCMIPP Data Type YUV422 10bit */
+#define DCMIPP_DT_RGB444     0x20U   /*!< DCMIPP Data Type RGB444       */
+#define DCMIPP_DT_RGB555     0x21U   /*!< DCMIPP Data Type RGB555       */
+#define DCMIPP_DT_RGB565     0x22U   /*!< DCMIPP Data Type RGB565       */
+#define DCMIPP_DT_RGB666     0x23U   /*!< DCMIPP Data Type RGB666       */
+#define DCMIPP_DT_RGB888     0x24U   /*!< DCMIPP Data Type RGB888       */
+#define DCMIPP_DT_RAW8       0x2AU   /*!< DCMIPP Data Type RawBayer8    */
+#define DCMIPP_DT_RAW10      0x2BU   /*!< DCMIPP Data Type RawBayer10   */
+#define DCMIPP_DT_RAW12      0x2CU   /*!< DCMIPP Data Type RawBayer12   */
+#define DCMIPP_DT_RAW14      0x2DU   /*!< DCMIPP Data Type RawBayer14   */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_DataTypeID DCMIPP CSI Data Type ID
+  * @{
+  */
+#define DCMIPP_CSI_DT1 1U  /*!< DCMIPP Data Type ID 1 */
+#define DCMIPP_CSI_DT2 2U  /*!< DCMIPP Data Type ID 2 */
+#define DCMIPP_CSI_DT3 3U  /*!< DCMIPP Data Type ID 3 */
+#define DCMIPP_CSI_DT4 4U  /*!< DCMIPP Data Type ID 4 */
+#define DCMIPP_CSI_DT5 5U  /*!< DCMIPP Data Type ID 5 */
+#define DCMIPP_CSI_DT6 6U  /*!< DCMIPP Data Type ID 6 */
+#define DCMIPP_CSI_DT7 7U  /*!< DCMIPP Data Type ID 7 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_CSI_Number_Of_Lanes DCMIPP CSI Number Of Lanes
+  * @{
+  */
+#define DCMIPP_CSI_ONE_DATA_LANE  (1U << CSI_LMCFGR_LANENB_Pos) /*!< DCMIPP CSI One Data Lane */
+#define DCMIPP_CSI_TWO_DATA_LANES (2U << CSI_LMCFGR_LANENB_Pos) /*!< DCMIPP CSI 2 Data Lanes  */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_DataLaneMapping DCMIPP CSI Data Lane Mapping
+  * @{
+  */
+#define DCMIPP_CSI_PHYSICAL_DATA_LANES   1U  /*!< Physical data lane 0 connected to logical data lane 0 and
+                                                  Physical data lane 1 connected to logical data lane 1  */
+#define DCMIPP_CSI_INVERTED_DATA_LANES   2U  /*!< Physical data lane 1 connected to logical data lane 0 and
+                                                  Physical data lane 0 connected to logical data lane 1 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_CSI_DataLane DCMIPP CSI Data Lane
+  * @{
+  */
+#define DCMIPP_CSI_DATA_LANE0   1U /*!< DCMIPP CSI Data Lane 0 */
+#define DCMIPP_CSI_DATA_LANE1   2U /*!< DCMIPP CSI Data Lane 1 */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_Timer_StartPoint DCMIPP CSI Timer StartPoint
+  * @{
+  */
+#define DCMIPP_CSI_TIMER_START_SOF  0U /*!< DCMIPP CSI Start timer counter at Start Of Frame */
+#define DCMIPP_CSI_TIMER_START_EOF  1U /*!< DCMIPP CSI Start timer counter at End Of Frame   */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_DataTypeFormat DCMIPP CSI Data Type Format
+  * @{
+  */
+#define DCMIPP_CSI_DT_BPP6  0U  /*!< DCMIPP CSI Data Type Format 6 bit words */
+#define DCMIPP_CSI_DT_BPP7  1U  /*!< DCMIPP CSI Data Type Format 7 bit words */
+#define DCMIPP_CSI_DT_BPP8  2U  /*!< DCMIPP CSI Data Type Format 8 bit words */
+#define DCMIPP_CSI_DT_BPP10 3U  /*!< DCMIPP CSI Data Type Format 10 bit words */
+#define DCMIPP_CSI_DT_BPP12 4U  /*!< DCMIPP CSI Data Type Format 12 bit words */
+#define DCMIPP_CSI_DT_BPP14 5U  /*!< DCMIPP CSI Data Type Format 14 bit words */
+#define DCMIPP_CSI_DT_BPP16 6U  /*!< DCMIPP CSI Data Type Format 16 bit words */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_Timer DCMIPP CSI Timer
+  * @{
+  */
+#define DCMIPP_CSI_TIMER0 0U     /*!< DCMIPP CSI Timer0 */
+#define DCMIPP_CSI_TIMER1 1U  /*!< DCMIPP CSI Timer1 */
+#define DCMIPP_CSI_TIMER2 2U  /*!< DCMIPP CSI Timer2 */
+#define DCMIPP_CSI_TIMER3 3U  /*!< DCMIPP CSI Timer3 */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_Counter DCMIPP CSI Counter
+  * @{
+  */
+#define DCMIPP_CSI_COUNTER0 0U /*!< DCMIPP CSI Counter 0 */
+#define DCMIPP_CSI_COUNTER1 1U /*!< DCMIPP CSI Counter 1 */
+#define DCMIPP_CSI_COUNTER2 2U /*!< DCMIPP CSI Counter 2 */
+#define DCMIPP_CSI_COUNTER3 3U /*!< DCMIPP CSI Counter 3 */
+/**
+  * @}
+  */
+/**
+  * @defgroup DCMIPP_CSI_PHYBitRate DCMIPP CSI PHY BitRate
+  * @{
+  */
+#define DCMIPP_CSI_PHY_BT_80      0U     /*!< PHY BitRate 80      */
+#define DCMIPP_CSI_PHY_BT_90      1U     /*!< PHY BitRate 90      */
+#define DCMIPP_CSI_PHY_BT_100     2U     /*!< PHY BitRate 100     */
+#define DCMIPP_CSI_PHY_BT_110     3U     /*!< PHY BitRate 110     */
+#define DCMIPP_CSI_PHY_BT_120     4U     /*!< PHY BitRate 120     */
+#define DCMIPP_CSI_PHY_BT_130     5U     /*!< PHY BitRate 130     */
+#define DCMIPP_CSI_PHY_BT_140     6U     /*!< PHY BitRate 140     */
+#define DCMIPP_CSI_PHY_BT_150     7U     /*!< PHY BitRate 150     */
+#define DCMIPP_CSI_PHY_BT_160     8U     /*!< PHY BitRate 160     */
+#define DCMIPP_CSI_PHY_BT_170     9U     /*!< PHY BitRate 170     */
+#define DCMIPP_CSI_PHY_BT_180     10U    /*!< PHY BitRate 180     */
+#define DCMIPP_CSI_PHY_BT_190     11U    /*!< PHY BitRate 190     */
+#define DCMIPP_CSI_PHY_BT_205     12U    /*!< PHY BitRate 205     */
+#define DCMIPP_CSI_PHY_BT_220     13U    /*!< PHY BitRate 220     */
+#define DCMIPP_CSI_PHY_BT_235     14U    /*!< PHY BitRate 235     */
+#define DCMIPP_CSI_PHY_BT_250     15U    /*!< PHY BitRate 250     */
+#define DCMIPP_CSI_PHY_BT_275     16U    /*!< PHY BitRate 275     */
+#define DCMIPP_CSI_PHY_BT_300     17U    /*!< PHY BitRate 300     */
+#define DCMIPP_CSI_PHY_BT_325     18U    /*!< PHY BitRate 325     */
+#define DCMIPP_CSI_PHY_BT_350     19U    /*!< PHY BitRate 350     */
+#define DCMIPP_CSI_PHY_BT_400     20U    /*!< PHY BitRate 400     */
+#define DCMIPP_CSI_PHY_BT_450     21U    /*!< PHY BitRate 450     */
+#define DCMIPP_CSI_PHY_BT_500     22U    /*!< PHY BitRate 500     */
+#define DCMIPP_CSI_PHY_BT_550     23U    /*!< PHY BitRate 550     */
+#define DCMIPP_CSI_PHY_BT_600     24U    /*!< PHY BitRate 600     */
+#define DCMIPP_CSI_PHY_BT_650     25U    /*!< PHY BitRate 650     */
+#define DCMIPP_CSI_PHY_BT_700     26U    /*!< PHY BitRate 700     */
+#define DCMIPP_CSI_PHY_BT_750     27U    /*!< PHY BitRate 750     */
+#define DCMIPP_CSI_PHY_BT_800     28U    /*!< PHY BitRate 800     */
+#define DCMIPP_CSI_PHY_BT_850     29U    /*!< PHY BitRate 850     */
+#define DCMIPP_CSI_PHY_BT_900     30U    /*!< PHY BitRate 900     */
+#define DCMIPP_CSI_PHY_BT_950     31U    /*!< PHY BitRate 950     */
+#define DCMIPP_CSI_PHY_BT_1000    32U    /*!< PHY BitRate 1000    */
+#define DCMIPP_CSI_PHY_BT_1050    33U    /*!< PHY BitRate 1050    */
+#define DCMIPP_CSI_PHY_BT_1100    34U    /*!< PHY BitRate 1100    */
+#define DCMIPP_CSI_PHY_BT_1150    35U    /*!< PHY BitRate 1150    */
+#define DCMIPP_CSI_PHY_BT_1200    36U    /*!< PHY BitRate 1200    */
+#define DCMIPP_CSI_PHY_BT_1250    37U    /*!< PHY BitRate 1250    */
+#define DCMIPP_CSI_PHY_BT_1300    38U    /*!< PHY BitRate 1300    */
+#define DCMIPP_CSI_PHY_BT_1350    39U    /*!< PHY BitRate 1350    */
+#define DCMIPP_CSI_PHY_BT_1400    40U    /*!< PHY BitRate 1400    */
+#define DCMIPP_CSI_PHY_BT_1450    41U    /*!< PHY BitRate 1450    */
+#define DCMIPP_CSI_PHY_BT_1500    42U    /*!< PHY BitRate 1500    */
+#define DCMIPP_CSI_PHY_BT_1550    43U    /*!< PHY BitRate 1550    */
+#define DCMIPP_CSI_PHY_BT_1600    44U    /*!< PHY BitRate 1600    */
+#define DCMIPP_CSI_PHY_BT_1650    45U    /*!< PHY BitRate 1650    */
+#define DCMIPP_CSI_PHY_BT_1700    46U    /*!< PHY BitRate 1700    */
+#define DCMIPP_CSI_PHY_BT_1750    47U    /*!< PHY BitRate 1750    */
+#define DCMIPP_CSI_PHY_BT_1800    48U    /*!< PHY BitRate 1800    */
+#define DCMIPP_CSI_PHY_BT_1850    49U    /*!< PHY BitRate 1850    */
+#define DCMIPP_CSI_PHY_BT_1900    50U    /*!< PHY BitRate 1900    */
+#define DCMIPP_CSI_PHY_BT_1950    51U    /*!< PHY BitRate 1950    */
+#define DCMIPP_CSI_PHY_BT_2000    52U    /*!< PHY BitRate 2000    */
+#define DCMIPP_CSI_PHY_BT_2050    53U    /*!< PHY BitRate 2050    */
+#define DCMIPP_CSI_PHY_BT_2100    54U    /*!< PHY BitRate 2100    */
+#define DCMIPP_CSI_PHY_BT_2150    55U    /*!< PHY BitRate 2150    */
+#define DCMIPP_CSI_PHY_BT_2200    56U    /*!< PHY BitRate 2200    */
+#define DCMIPP_CSI_PHY_BT_2250    57U    /*!< PHY BitRate 2250    */
+#define DCMIPP_CSI_PHY_BT_2300    58U    /*!< PHY BitRate 2300    */
+#define DCMIPP_CSI_PHY_BT_2350    59U    /*!< PHY BitRate 2350    */
+#define DCMIPP_CSI_PHY_BT_2400    60U    /*!< PHY BitRate 2400    */
+#define DCMIPP_CSI_PHY_BT_2450    61U    /*!< PHY BitRate 2450    */
+#define DCMIPP_CSI_PHY_BT_2500    62U    /*!< PHY BitRate 2500    */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_OutputSamplesType  DCMIPP OutputSamplesType
+  * @{
+  */
+#define DCMIPP_CLAMP_YUV (0x0U << DCMIPP_P1CCCR_TYPE_Pos) /*!< Output samples type : Clamped to [16;235] for Y and
+                                                               to [16;240] for U and V  */
+#define DCMIPP_CLAMP_RGB (0x1U << DCMIPP_P1CCCR_TYPE_Pos) /*!< Output samples type:Clamped to [16;235] for R, G and B */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Format  DCMIPP Format
+  * @{
+  */
+#define  DCMIPP_FORMAT_BYTE             0U                               /*!< DCMIPP Format BYTE    */
+#define  DCMIPP_FORMAT_YUV422          (0x1EU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format YUV422  */
+#define  DCMIPP_FORMAT_RGB565          (0x22U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB565  */
+#define  DCMIPP_FORMAT_RGB666          (0x23U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB666  */
+#define  DCMIPP_FORMAT_RGB888          (0x24U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB888  */
+#define  DCMIPP_FORMAT_RAW8            (0x2AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW8    */
+#define  DCMIPP_FORMAT_RAW10           (0x2BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW10   */
+#define  DCMIPP_FORMAT_RAW12           (0x2CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW12   */
+#define  DCMIPP_FORMAT_RAW14           (0x2DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW14   */
+#define  DCMIPP_FORMAT_MONOCHROME_8B   (0x4AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 8-bits  */
+#define  DCMIPP_FORMAT_MONOCHROME_10B  (0x4BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 10-bits */
+#define  DCMIPP_FORMAT_MONOCHROME_12B  (0x4CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 12-bits */
+#define  DCMIPP_FORMAT_MONOCHROME_14B  (0x4DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 14-bits */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Extended_Data_Mode  DCMIPP Extended Data Mode
+  * @{
+  */
+#define  DCMIPP_INTERFACE_8BITS   0U                         /*!< Interface captures 8bits on every pixel clock  */
+#define  DCMIPP_INTERFACE_10BITS (1U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 10bits on every pixel clock */
+#define  DCMIPP_INTERFACE_12BITS (2U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 12bits on every pixel clock */
+#define  DCMIPP_INTERFACE_14BITS (3U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 14bits on every pixel clock */
+#define  DCMIPP_INTERFACE_16BITS (4U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 16bits on every pixel clock */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_HSYNC_Polarity DCMIPP HSYNC Polarity
+  * @{
+  */
+#define DCMIPP_HSPOLARITY_LOW       0U                 /*!< Horizontal synchronization active Low  */
+#define DCMIPP_HSPOLARITY_HIGH      DCMIPP_PRCR_HSPOL  /*!< Horizontal synchronization active High */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_VSYNC_Polarity DCMIPP VSYNC Polarity
+  * @{
+  */
+#define DCMIPP_VSPOLARITY_LOW       0U                 /*!< Vertical synchronization active Low  */
+#define DCMIPP_VSPOLARITY_HIGH      DCMIPP_PRCR_VSPOL  /*!< Vertical synchronization active High */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_PIXCK_Polarity DCMIPP PIXCK Polarity
+  * @{
+  */
+#define DCMIPP_PCKPOLARITY_FALLING  0U                  /*!< Pixel clock active on Falling edge */
+#define DCMIPP_PCKPOLARITY_RISING   DCMIPP_PRCR_PCKPOL  /*!< Pixel clock active on Rising edge  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Synchronization_Mode DCMIPP Synchronization Mode
+  * @{
+  */
+#define DCMIPP_SYNCHRO_HARDWARE     0U                          /*!< Hardware Synchronization */
+#define DCMIPP_SYNCHRO_EMBEDDED    DCMIPP_PRCR_ESS              /*!< Embedded Synchronization */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_SWAP_COMPONENT  DCMIPP Swap Component
+  * @{
+  */
+#define DCMIPP_SWAP_COMPONENT_DISABLE  0U                   /*!< Disable Swap R/U and B/V */
+#define DCMIPP_SWAP_COMPONENT_ENABLE   (DCMIPP_CMCR_SWAPRB) /*!< Enable Swap R/U and B/V  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_SWAP_CYCLES  DCMIPP Swap Cycles
+  * @{
+  */
+#define DCMIPP_SWAPCYCLES_DISABLE  0U                       /*!< swap data from cycle 0 vs cycle 1 */
+#define DCMIPP_SWAPCYCLES_ENABLE   (DCMIPP_PRCR_SWAPCYCLES) /*!< swap data from cycle 0 vs cycle 1 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_SWAP_BITS  DCMIPP Swap Bits
+  * @{
+  */
+#define DCMIPP_SWAPBITS_DISABLE  0U                     /*!< swap lsb vs msb within each received component */
+#define DCMIPP_SWAPBITS_ENABLE   (DCMIPP_PRCR_SWAPBITS) /*!< swap lsb vs msb within each received component */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Pipe_Line_Decimation DCMIPP Pipe Line Decimation
+  * @{
+  */
+/** @defgroup DCMIPP_Line_Select_Mode DCMIPP Line Select Mode
+  * @{
+  */
+#define DCMIPP_LSM_ALL          0U                              /*!< Interface captures all received lines */
+#define DCMIPP_LSM_ALTERNATE_2 (1U << DCMIPP_P0PPCR_LSM_Pos )   /*!< Interface captures one line out of two */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Line_Start_Mode DCMIPP Line Start Mode
+  * @{
+  */
+#define DCMIPP_OELS_ODD         0U                              /*!< Interface captures first line from the frame start,
+                                                                     second one is dropped */
+#define DCMIPP_OELS_EVEN       (1U << DCMIPP_P0PPCR_OELS_Pos)   /*!< Interface captures second line from the frame
+                                                                     start, first one is dropped */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Pipe_Byte_Decimation DCMIPP Pipe Byte Decimation
+  * @{
+  */
+/** @defgroup DCMIPP_Byte_Select_Mode DCMIPP Byte Select Mode
+  * @{
+  */
+#define DCMIPP_BSM_ALL          0U                              /*!< Interface captures all received data */
+#define DCMIPP_BSM_DATA_OUT_2  (1U << DCMIPP_P0PPCR_BSM_Pos)    /*!< Interface captures 1 data out of 2   */
+#define DCMIPP_BSM_BYTE_OUT_4  (2U << DCMIPP_P0PPCR_BSM_Pos)    /*!< Interface captures 1 byte out of 4   */
+#define DCMIPP_BSM_2BYTE_OUT_4 (3U << DCMIPP_P0PPCR_BSM_Pos)    /*!< Interface captures 2 byte out of 4   */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Byte_Start_Mode DCMIPP Byte Start Mode
+  * @{
+  */
+#define DCMIPP_OEBS_ODD        0U                              /*!< Interface captures first data (byte or double byte)
+                                                                   from the frame/line start,second one being dropped */
+#define DCMIPP_OEBS_EVEN      (1U << DCMIPP_P0PPCR_OEBS_Pos)   /*!< Interface captures second data (byte or double byte)
+                                                                    from the frame/line start, first one is dropped   */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Memory DCMIPP Memory
+  * @{
+  */
+#define DCMIPP_MEMORY_ADDRESS_0 0U   /*!< Base destination address   */
+#define DCMIPP_MEMORY_ADDRESS_1 1U   /*!< Second destination address */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_LineMult DCMIPP Line Mult
+  * @{
+  */
+#define  DCMIPP_MULTILINE_1_LINE      0U                                  /*!< Event after every 1   line   */
+#define  DCMIPP_MULTILINE_2_LINES    (1U << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< Event after every 2   lines  */
+#define  DCMIPP_MULTILINE_4_LINES    (2U << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< Event after every 4   lines  */
+#define  DCMIPP_MULTILINE_8_LINES    (3U << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< Event after every 8   lines  */
+#define  DCMIPP_MULTILINE_16_LINES   (4U << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< Event after every 16  lines  */
+#define  DCMIPP_MULTILINE_32_LINES   (5U << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< Event after every 32  lines  */
+#define  DCMIPP_MULTILINE_64_LINES   (6U << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< Event after every 64  lines  */
+#define  DCMIPP_MULTILINE_128_LINES  (7U << DCMIPP_P0PPCR_LINEMULT_Pos)   /*!< Event after every 128 lines  */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_LineWrapAddress DCMIPP line Wrap Address
+  * @{
+  */
+#define  DCMIPP_WRAP_ADDRESS_1_LINE     (0U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 1   line   */
+#define  DCMIPP_WRAP_ADDRESS_2_LINES    (1U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 2   lines  */
+#define  DCMIPP_WRAP_ADDRESS_4_LINES    (2U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 4   lines  */
+#define  DCMIPP_WRAP_ADDRESS_8_LINES    (3U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 8   lines  */
+#define  DCMIPP_WRAP_ADDRESS_16_LINES   (4U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 16  lines  */
+#define  DCMIPP_WRAP_ADDRESS_32_LINES   (5U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 32  lines  */
+#define  DCMIPP_WRAP_ADDRESS_64_LINES   (6U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 64  lines  */
+#define  DCMIPP_WRAP_ADDRESS_128_LINES  (7U << DCMIPP_P1PPCR_LMAWM_Pos)  /*!< Wraps address after 128 lines  */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_PIPE_Vertical_Decimation_Ratio DCMIPP Pipe Vertical Decimation Ratio
+  * @{
+  */
+
+#define  DCMIPP_VDEC_ALL       0U                              /*!< All lines captured , no vertical decimation */
+#define  DCMIPP_VDEC_1_OUT_2  (1U << DCMIPP_P1DECR_VDEC_Pos)   /*!< One line out of two transmitted             */
+#define  DCMIPP_VDEC_1_OUT_4  (2U << DCMIPP_P1DECR_VDEC_Pos)   /*!< One line out of four transmitted            */
+#define  DCMIPP_VDEC_1_OUT_8  (3U << DCMIPP_P1DECR_VDEC_Pos)   /*!< One line out of eight transmitted           */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_PIPE_Horizontal_Decimation_Ratio DCMIPP Pipe Horizontal Decimation Ratio
+  * @{
+  */
+#define  DCMIPP_HDEC_ALL       0U                              /*!< All pixels captured , no horizontal decimation */
+#define  DCMIPP_HDEC_1_OUT_2  (1U << DCMIPP_P1DECR_HDEC_Pos)   /*!< One line out of two transmitted                */
+#define  DCMIPP_HDEC_1_OUT_4  (2U << DCMIPP_P1DECR_HDEC_Pos)   /*!< One line out of four transmitted               */
+#define  DCMIPP_HDEC_1_OUT_8  (3U << DCMIPP_P1DECR_HDEC_Pos)   /*!< One line out of eight transmitted              */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Pixel_Packer_Format  DCMIPP Pixel Packer Format
+  * @{
+  */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_RGB888_YUV444_1  0U                                /*!< RGB888 or YUV422 1-buffer*/
+#define  DCMIPP_PIXEL_PACKER_FORMAT_RGB565_1        (1U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< RGB565 1-buffer          */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_ARGB8888        (2U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< ARGB888  A=0xff          */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_RGBA888         (3U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< RGBA888  A=0xff)         */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_MONO_Y8_G8_1    (4U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< Monochrome Y8 or G8      */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_YUV444_1        (5U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< YUV444 1-buffer 32bpp
+                                                                                            A=0xff)                  */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1        (6U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< YUV422 1-buffer 16bpp    */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_YUV422_2        (7U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< YUV422 2-buffer 16bpp    */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_YUV420_2        (8U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< YUV420 2-buffer 12bpp    */
+#define  DCMIPP_PIXEL_PACKER_FORMAT_YUV420_3        (9U << DCMIPP_P1PPCR_FORMAT_Pos)   /*!< YUV420 3-buffer 12bpp    */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Statistics_Extraction_Mode  DCMIPP Statistics extraction Mode
+  * @{
+  */
+#define  DCMIPP_STAT_EXT_MODE_AVERAGE   0U                               /*!< Values of pixels are accumulated as-is */
+#define  DCMIPP_STAT_EXT_MODE_BINS     (1U << DCMIPP_P1ST1CR_MODE_Pos)   /*!< Values of pixels are used to see
+                                                                              if the pixel fits one of the 12 bins.*/
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Statistics_Extraction_Module_ID  DCMIPP Statistics Extraction Module ID
+  * @{
+  */
+#define DCMIPP_STATEXT_MODULE1  1U /*!< Statistic Extraction Module 1 */
+#define DCMIPP_STATEXT_MODULE2  2U /*!< Statistic Extraction Module 2 */
+#define DCMIPP_STATEXT_MODULE3  3U /*!< Statistic Extraction Module 3 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Statistics_Extraction_Source  DCMIPP Statistics extraction Source
+  * @{
+  */
+#define  DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_R   0U                              /*!< Statistics Extraction Source : Red
+                                                           is sampled before the black level calibration and exposure */
+#define  DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_G  (1U << DCMIPP_P1ST1CR_SRC_Pos) /*!< Statistics Extraction Source : Green
+                                                           is sampled before the black level calibration and exposure */
+#define  DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_B  (2U << DCMIPP_P1ST1CR_SRC_Pos) /*!< Statistics Extraction Source : Blue
+                                                           is sampled before the black level calibration and exposure */
+#define  DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_L  (3U << DCMIPP_P1ST1CR_SRC_Pos) /*!< Statistics Extraction Source :
+                                                 Luminance is sampled before the black level calibration and exposure */
+#define  DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_R  (4U << DCMIPP_P1ST1CR_SRC_Pos) /*!< Statistics Extraction Source : Red
+                                                            is sampled after the black level calibration and exposure */
+#define  DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_G  (5U << DCMIPP_P1ST1CR_SRC_Pos) /*!< Statistics Extraction Source : Green
+                                                            is sampled after the black level calibration and exposure */
+#define  DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_B  (6U << DCMIPP_P1ST1CR_SRC_Pos) /*!< Statistics Extraction Source : Blue
+                                                            is sampled after the black level calibration and exposure */
+#define  DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_L  (7U << DCMIPP_P1ST1CR_SRC_Pos) /*!< Statistics Extraction Source :
+                                                  Luminance is sampled after the black level calibration and exposure */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Statistics_Extraction_Bins  DCMIPP Statistics extraction Bins
+  * @{
+  */
+#define  DCMIPP_STAT_EXT_BINS_MODE_LOWER_BINS   0U                               /*!< LowerBins: Accu0 (1, 2)
+                                                                                      is incremented of 256 if
+                                                                                      Component <4 (<8, <16) */
+#define  DCMIPP_STAT_EXT_BINS_MODE_LOWMID_BINS (1U << DCMIPP_P1ST1CR_BINS_Pos) /*!< LowMid Bins: Accu0 (1, 2)
+                                                                                      is incremented of 256 if
+                                                                                      Component <32 (<64, <128) */
+#define  DCMIPP_STAT_EXT_BINS_MODE_UPMID_BINS  (2U << DCMIPP_P1ST1CR_BINS_Pos) /*!< UpMid Bins: Accu0 (1, 2) is
+                                                                                      incremented of 256 if
+                                                                                      Component >127 (>191, >224) */
+#define  DCMIPP_STAT_EXT_BINS_MODE_UP_BINS     (3U << DCMIPP_P1ST1CR_BINS_Pos) /*!< UpBins: Accu0 (1, 2) is
+                                                                                      incremented of 256 if
+                                                                                      Component >239 (>247, >251)
+                                                                                      Condition: MODE = Average */
+#define  DCMIPP_STAT_EXT_AVER_MODE_ALL_PIXELS  (0U << DCMIPP_P1ST1CR_BINS_Pos) /*!< All Pixels: Accu is incremented of
+                                                                                   Component, if 0 <= Component < 256 */
+#define  DCMIPP_STAT_EXT_AVER_MODE_NOEXT16     (1U << DCMIPP_P1ST1CR_BINS_Pos) /*!< NoExt16: Accu is incremented of
+                                                                                  Component, if 16 <= Component < 240 */
+#define  DCMIPP_STAT_EXT_AVER_MODE_NOEXT32     (2U << DCMIPP_P1ST1CR_BINS_Pos) /*!< NoExt32: Accu is incremented of
+                                                                                  Component, if 32 <= Component < 224 */
+#define  DCMIPP_STAT_EXT_AVER_MODE_NOEXT64     (3U << DCMIPP_P1ST1CR_BINS_Pos) /*!< NoExt64: Accu is incremented of
+                                                                                  Component, if 64 <= Component < 192 */
+/**
+  * @}
+  */
+
+/**
+  * @defgroup  DCMIPP_RAWBayer2RGB_Strength DCMIPP RAWBayer2RGB Strength
+  * @{
+  */
+#define  DCMIPP_RAWBAYER_ALGO_NONE        0U   /*!< No edge detection, pure linear interpolation */
+#define  DCMIPP_RAWBAYER_ALGO_STRENGTH_3  1U   /*!< RawBayer relative algorithm strength 3       */
+#define  DCMIPP_RAWBAYER_ALGO_STRENGTH_4  2U   /*!< RawBayer relative algorithm strength 4       */
+#define  DCMIPP_RAWBAYER_ALGO_STRENGTH_6  3U   /*!< RawBayer relative algorithm strength 6       */
+#define  DCMIPP_RAWBAYER_ALGO_STRENGTH_8  4U   /*!< RawBayer relative algorithm strength 8       */
+#define  DCMIPP_RAWBAYER_ALGO_STRENGTH_12 5U   /*!< RawBayer relative algorithm strength 12      */
+#define  DCMIPP_RAWBAYER_ALGO_STRENGTH_16 6U   /*!< RawBayer relative algorithm strength 16      */
+#define  DCMIPP_RAWBAYER_ALGO_STRENGTH_24 7U   /*!< RawBayer relative algorithm strength 24      */
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup  DCMIPP_RAWBayer2RGB_Type DCMIPP RAWBayer2RGB Type
+  * @{
+  */
+#define  DCMIPP_RAWBAYER_RGGB   0U                               /*!<Raw Bayer Type RGGB */
+#define  DCMIPP_RAWBAYER_GRBG  (1U << DCMIPP_P1DMCR_TYPE_Pos)    /*!<Raw Bayer Type GRBG */
+#define  DCMIPP_RAWBAYER_GBRG  (2U << DCMIPP_P1DMCR_TYPE_Pos)    /*!<Raw Bayer Type GBRG */
+#define  DCMIPP_RAWBAYER_BGGR  (3U << DCMIPP_P1DMCR_TYPE_Pos)    /*!<Raw Bayer Type BGGR */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Bad_Pixel_Removal_Strength  DCMIPP Bad Pixel Removal Strength
+  * @{
+  */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_0  0U   /*!< The filter is fairly tolerant: only a
+                                                  few pixels are declared bad, due to
+                                                  their high noise */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_1  1U   /*!< Bad Pixel detection strength 1 */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_2  2U   /*!< Bad Pixel detection strength 2 */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_3  3U   /*!< Bad Pixel detection strength 3 */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_4  4U   /*!< Bad Pixel detection strength 4 */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_5  5U   /*!< Bad Pixel detection strength 5 */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_6  6U   /*!< Bad Pixel detection strength 6 */
+#define  DCMIPP_BAD_PXL_REM_SRENGTH_7  7U   /*!< Bad Pixel detection strength 7 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Region_Of_Interest  DCMIPP Region Of Interest
+  * @{
+  */
+#define DCMIPP_REGION_OF_INTEREST1  1U  /*!< Region Of Interest 1 */
+#define DCMIPP_REGION_OF_INTEREST2  2U  /*!< Region Of Interest 2 */
+#define DCMIPP_REGION_OF_INTEREST3  3U  /*!< Region Of Interest 3 */
+#define DCMIPP_REGION_OF_INTEREST4  4U  /*!< Region Of Interest 4 */
+#define DCMIPP_REGION_OF_INTEREST5  5U  /*!< Region Of Interest 5 */
+#define DCMIPP_REGION_OF_INTEREST6  6U  /*!< Region Of Interest 6 */
+#define DCMIPP_REGION_OF_INTEREST7  7U  /*!< Region Of Interest 7 */
+#define DCMIPP_REGION_OF_INTEREST8  8U  /*!< Region Of Interest 8 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Region_Of_Interest_Line_Width  DCMIPP Region Of Interest Line Width
+  * @{
+  */
+#define DCMIPP_LINE_WIDTH_1PXL 0U    /*!< Line width 1 pixel  */
+#define DCMIPP_LINE_WIDTH_2PXL 1U    /*!< Line width 2 pixels */
+#define DCMIPP_LINE_WIDTH_4PXL 2U    /*!< Line width 4 pixels */
+#define DCMIPP_LINE_WIDTH_8PXL 3U    /*!< Line width 8 pixels */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Multiply  DCMIPP Multiply
+  * @{
+  */
+#define DCMIPP_MULTIPY_BY_1 0U   /*!< DCMIPP multiply R/G/B by 1 */
+#define DCMIPP_MULTIPY_BY_2 1U   /*!< DCMIPP multiply R/G/B by 2 */
+#define DCMIPP_MULTIPY_BY_4 2U   /*!< DCMIPP multiply R/G/B by 4 */
+#define DCMIPP_MULTIPY_BY_8 3U   /*!< DCMIPP multiply R/G/B by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Interrupt_Sources  DCMIPP Interrupt sources
+  * @{
+  */
+#define DCMIPP_IT_AXI_TRANSFER_ERROR  DCMIPP_CMIER_ATXERRIE  /*!< IPPLUG AXI Transfer error interrupt        */
+#define DCMIPP_IT_PARALLEL_SYNC_ERROR DCMIPP_CMIER_PRERRIE   /*!< Sync error interrupt on parallel interface */
+#define DCMIPP_IT_PIPE0_FRAME         DCMIPP_CMIER_P0FRAMEIE /*!< Frame capture interrupt complete for pipe0 */
+#define DCMIPP_IT_PIPE0_VSYNC         DCMIPP_CMIER_P0VSYNCIE /*!< Vertical sync interrupt for pipe0          */
+#define DCMIPP_IT_PIPE0_LINE          DCMIPP_CMIER_P0LINEIE  /*!< Multiline interrupt for pipe0              */
+#define DCMIPP_IT_PIPE0_LIMIT         DCMIPP_CMIER_P0LIMITIE /*!< Limit interrupt for pipe0                  */
+#define DCMIPP_IT_PIPE0_OVR           DCMIPP_CMIER_P0OVRIE   /*!< Overrun interrupt for pipe0                */
+#define DCMIPP_IT_PIPE1_LINE          DCMIPP_CMIER_P1LINEIE  /*!< Multiline capture interrupt for pipe1      */
+#define DCMIPP_IT_PIPE1_FRAME         DCMIPP_CMIER_P1FRAMEIE /*!< Frame capture interrupt complete for pipe1 */
+#define DCMIPP_IT_PIPE1_VSYNC         DCMIPP_CMIER_P1VSYNCIE /*!< Vertical sync interrupt for pipe1          */
+#define DCMIPP_IT_PIPE1_OVR           DCMIPP_CMIER_P1OVRIE   /*!< Overrun interrupt for pipe1                */
+#define DCMIPP_IT_PIPE2_LINE          DCMIPP_CMIER_P2LINEIE  /*!< Multiline capture interrupt for pipe2      */
+#define DCMIPP_IT_PIPE2_FRAME         DCMIPP_CMIER_P2FRAMEIE /*!< Frame capture interrupt complete for pipe2 */
+#define DCMIPP_IT_PIPE2_VSYNC         DCMIPP_CMIER_P2VSYNCIE /*!< Vertical synch interrupt for pipe2         */
+#define DCMIPP_IT_PIPE2_OVR           DCMIPP_CMIER_P2OVRIE   /*!< Overrun interrupt for pipe2                */
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Interrupt_Flags  DCMIPP Interrupt Flags
+  * @{
+  */
+#define DCMIPP_FLAG_AXI_TRANSFER_ERROR  DCMIPP_CMSR2_ATXERRF /*!< IPPLUG AXI Transfer error interrupt flag            */
+#define DCMIPP_FLAG_PARALLEL_SYNC_ERROR DCMIPP_CMSR2_PRERRF  /*!< Synchronization error interrupt on parallel interface
+                                                                  flag */
+#define DCMIPP_FLAG_PIPE0_FRAME       DCMIPP_CMSR2_P0FRAMEF  /*!< Frame capture interrupt complete for pipe0 flag     */
+#define DCMIPP_FLAG_PIPE0_VSYNC       DCMIPP_CMSR2_P0VSYNCF  /*!< Vertical synch interrupt for pipe0 flag             */
+#define DCMIPP_FLAG_PIPE0_LINE        DCMIPP_CMSR2_P0LINEF   /*!< Multiline interrupt for pipe0 flag                  */
+#define DCMIPP_FLAG_PIPE0_LIMIT       DCMIPP_CMSR2_P0LIMITF  /*!< Limit interrupt for pipe0 flag                      */
+#define DCMIPP_FLAG_PIPE0_OVR         DCMIPP_CMSR2_P0OVRF    /*!< Overrun interrupt for pipe0 flag                    */
+#define DCMIPP_FLAG_PIPE1_LINE        DCMIPP_CMSR2_P1LINEF   /*!< Multiline capture interrupt for pipe1 flag          */
+#define DCMIPP_FLAG_PIPE1_FRAME       DCMIPP_CMSR2_P1FRAMEF  /*!< Frame capture interrupt complete for pipe1 flag     */
+#define DCMIPP_FLAG_PIPE1_VSYNC       DCMIPP_CMSR2_P1VSYNCF  /*!< Vertical synch interrupt for pipe1 flag             */
+#define DCMIPP_FLAG_PIPE1_OVR         DCMIPP_CMSR2_P1OVRF    /*!< Overrun interrupt for pipe1 flag                    */
+#define DCMIPP_FLAG_PIPE2_LINE        DCMIPP_CMSR2_P2LINEF   /*!< Multiline capture interrupt for pipe2 flag          */
+#define DCMIPP_FLAG_PIPE2_FRAME       DCMIPP_CMSR2_P2FRAMEF  /*!< Frame capture interrupt complete for pipe2 flag     */
+#define DCMIPP_FLAG_PIPE2_VSYNC       DCMIPP_CMSR2_P2VSYNCF  /*!< Vertical synch interrupt for pipe2 flag             */
+#define DCMIPP_FLAG_PIPE2_OVR         DCMIPP_CMSR2_P2OVRF    /*!< Overrun interrupt for pipe2 flag                    */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_Interrupt_Sources  DCMIPP CSI Interrupt sources
+  * @{
+  */
+#define DCMIPP_CSI_IT_SYNCERR      CSI_IER0_SYNCERRIE     /*!< Synchronization error interrupt                    */
+#define DCMIPP_CSI_IT_WDERR        CSI_IER0_WDERRIE       /*!< Watchdog error interrupt                           */
+#define DCMIPP_CSI_IT_SPKTERR      CSI_IER0_SPKTERRIE     /*!< Shorter packet than expected error interrupt       */
+#define DCMIPP_CSI_IT_IDERR        CSI_IER0_IDERRIE       /*!< Data ID information error interrupt                */
+#define DCMIPP_CSI_IT_CECCERR      CSI_IER0_CECCERRIE     /*!< Corrected ECC error interrupt                      */
+#define DCMIPP_CSI_IT_ECCERR       CSI_IER0_ECCERRIE      /*!< ECC Error interrupt                                */
+#define DCMIPP_CSI_IT_CRCERR       CSI_IER0_CRCERRIE      /*!< CRC Error interrupt                                */
+#define DCMIPP_CSI_IT_CCFIFO       CSI_IER0_CCFIFOFIE     /*!< Clock changer FIFO full event interrupt            */
+#define DCMIPP_CSI_IT_SPKT         CSI_IER0_SPKTIE        /*!< Short packet detection interrupt                   */
+#define DCMIPP_CSI_IT_EOF3         CSI_IER0_EOF3IE        /*!< EOF on virtual channel 3 interrupt                 */
+#define DCMIPP_CSI_IT_EOF2         CSI_IER0_EOF2IE        /*!< EOF on virtual channel 2 interrupt                 */
+#define DCMIPP_CSI_IT_EOF1         CSI_IER0_EOF1IE        /*!< EOF on virtual channel 1 interrupt                 */
+#define DCMIPP_CSI_IT_EOF0         CSI_IER0_EOF0IE        /*!< EOF on virtual channel 0 interrupt                 */
+#define DCMIPP_CSI_IT_SOF3         CSI_IER0_SOF3IE        /*!< SOF on virtual channel 3 interrupt                 */
+#define DCMIPP_CSI_IT_SOF2         CSI_IER0_SOF2IE        /*!< SOF on virtual channel 2 interrupt                 */
+#define DCMIPP_CSI_IT_SOF1         CSI_IER0_SOF1IE        /*!< SOF on virtual channel 1 interrupt                 */
+#define DCMIPP_CSI_IT_SOF0         CSI_IER0_SOF0IE        /*!< SOF on virtual channel 0 interrupt                 */
+#define DCMIPP_CSI_IT_TIM3         CSI_IER0_TIM3IE        /*!< Timer 3 counter value reached interrupt            */
+#define DCMIPP_CSI_IT_TIM2         CSI_IER0_TIM2IE        /*!< Timer 2 counter value reached interrupt            */
+#define DCMIPP_CSI_IT_TIM1         CSI_IER0_TIM1IE        /*!< Timer 1 counter value reached interrupt            */
+#define DCMIPP_CSI_IT_TIM0         CSI_IER0_TIM0IE        /*!< Timer 0 counter value reached interrupt            */
+#define DCMIPP_CSI_IT_LB3          CSI_IER0_LB3IE         /*!< Line/byte event 3 reached interrupt                */
+#define DCMIPP_CSI_IT_LB2          CSI_IER0_LB2IE         /*!< Line/byte event 2 reached interrupt                */
+#define DCMIPP_CSI_IT_LB1          CSI_IER0_LB1IE         /*!< Line/byte event 1 reached interrupt                */
+#define DCMIPP_CSI_IT_LB0          CSI_IER0_LB0IE         /*!< Line/byte event 0 reached interrupt                */
+#define DCMIPP_CSI_IT_ECTRLDL1     CSI_IER1_ECTRLDL1IE    /*!< Error control on data line 1 interrupt             */
+#define DCMIPP_CSI_IT_ESYNCESCDL1  CSI_IER1_ESYNCESCDL1IE /*!< Low-power data transmission synchronization error on
+                                                               data line 1 interrupt                              */
+#define DCMIPP_CSI_IT_EESCDL1      CSI_IER1_EESCDL1IE     /*!< Escape entry error on data line 1 interrupt        */
+#define DCMIPP_CSI_IT_ESOTSYNCDL1  CSI_IER1_ESOTSYNCDL1IE /*!< SOT synchronization error on data line 1 interrupt */
+#define DCMIPP_CSI_IT_ESOTDL1      CSI_IER1_ESOTDL1IE     /*!< SOT error on data line 1 interrupt                 */
+#define DCMIPP_CSI_IT_ECTRLDL0     CSI_IER1_ECTRLDL0IE    /*!< Error control on data line 0 interrupt             */
+#define DCMIPP_CSI_IT_ESYNCESCDL0  CSI_IER1_ESYNCESCDL0IE /*!< Low-power data transmission synchronization error on
+                                                               data line 0 interrupt                               */
+#define DCMIPP_CSI_IT_EESCDL0      CSI_IER1_EESCDL0IE     /*!< Escape entry error on data line 0 interrupt        */
+#define DCMIPP_CSI_IT_ESOTSYNCDL0  CSI_IER1_ESOTSYNCDL0IE /*!< SOT synchronization error on data line 0 interrupt */
+#define DCMIPP_CSI_IT_ESOTDL0      CSI_IER1_ESOTDL0IE     /*!< SOT error on data line 0 interrupt                 */
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_Interrupt_Flags  DCMIPP CSI Interrupt Flags
+  * @{
+  */
+#define DCMIPP_CSI_FLAG_SYNCERR      CSI_SR0_SYNCERRF      /*!< Synchronization error flag                        */
+#define DCMIPP_CSI_FLAG_WDERR        CSI_SR0_WDERRF        /*!< Watchdog error flag                               */
+#define DCMIPP_CSI_FLAG_SPKTERR      CSI_SR0_SPKTERRF      /*!< Shorter packet than expected error flag           */
+#define DCMIPP_CSI_FLAG_IDERR        CSI_SR0_IDERRF        /*!< Data ID information error flag                    */
+#define DCMIPP_CSI_FLAG_CECCERR      CSI_SR0_CECCERRF      /*!< Corrected ECC error flag                          */
+#define DCMIPP_CSI_FLAG_ECCERR       CSI_SR0_ECCERRF       /*!< ECC Error flag                                    */
+#define DCMIPP_CSI_FLAG_CRCERR       CSI_SR0_CRCERRF       /*!< CRC Error flag                                    */
+#define DCMIPP_CSI_FLAG_CCFIFO       CSI_SR0_CCFIFOFF      /*!< Clock changer FIFO full event flag                */
+#define DCMIPP_CSI_FLAG_SPKT         CSI_SR0_SPKTF         /*!< Short packet detection flag                       */
+#define DCMIPP_CSI_FLAG_EOF3         CSI_SR0_EOF3F         /*!< EOF on virtual channel 3 flag                     */
+#define DCMIPP_CSI_FLAG_EOF2         CSI_SR0_EOF2F         /*!< EOF on virtual channel 2 flag                     */
+#define DCMIPP_CSI_FLAG_EOF1         CSI_SR0_EOF1F         /*!< EOF on virtual channel 1 flag                     */
+#define DCMIPP_CSI_FLAG_EOF0         CSI_SR0_EOF0F         /*!< EOF on virtual channel 0 flag                     */
+#define DCMIPP_CSI_FLAG_SOF3         CSI_SR0_SOF3F         /*!< SOF on virtual channel 3 flag                     */
+#define DCMIPP_CSI_FLAG_SOF2         CSI_SR0_SOF2F         /*!< SOF on virtual channel 2 flag                     */
+#define DCMIPP_CSI_FLAG_SOF1         CSI_SR0_SOF1F         /*!< SOF on virtual channel 1 flag                     */
+#define DCMIPP_CSI_FLAG_SOF0         CSI_SR0_SOF0F         /*!< SOF on virtual channel 0 flag                     */
+#define DCMIPP_CSI_FLAG_TIM3         CSI_SR0_TIM3F         /*!< Timer 3 counter value reached flag                */
+#define DCMIPP_CSI_FLAG_TIM2         CSI_SR0_TIM2F         /*!< Timer 2 counter value reached flag                */
+#define DCMIPP_CSI_FLAG_TIM1         CSI_SR0_TIM1F         /*!< Timer 1 counter value reached flag                */
+#define DCMIPP_CSI_FLAG_TIM0         CSI_SR0_TIM0F         /*!< Timer 0 counter value reached flag                */
+#define DCMIPP_CSI_FLAG_LB3          CSI_SR0_LB3F          /*!< Line/byte event 3 reached  flag                   */
+#define DCMIPP_CSI_FLAG_LB2          CSI_SR0_LB2F          /*!< Line/byte event 2 reached  flag                   */
+#define DCMIPP_CSI_FLAG_LB1          CSI_SR0_LB1F          /*!< Line/byte event 1 reached  flag                   */
+#define DCMIPP_CSI_FLAG_LB0          CSI_SR0_LB0F          /*!< Line/byte event 0 reached  flag                   */
+#define DCMIPP_CSI_FLAG_ECTRLDL1     CSI_SR1_ECTRLDL1F     /*!< Error control on data line 1 flag             */
+#define DCMIPP_CSI_FLAG_ESYNCESCDL1  CSI_SR1_ESYNCESCDL1F  /*!< Low-power data transmission synchronization
+                                                                error on data line 1 flag                     */
+#define DCMIPP_CSI_FLAG_EESCDL1      CSI_SR1_EESCDL1F      /*!< Escape entry error on data line 1 flag        */
+#define DCMIPP_CSI_FLAG_ESOTSYNCDL1  CSI_SR1_ESOTSYNCDL1F  /*!< SOT synchronization error on data line 1 flag */
+#define DCMIPP_CSI_FLAG_ESOTDL1      CSI_SR1_ESOTDL1F      /*!< SOT error on data line 1 flag                 */
+#define DCMIPP_CSI_FLAG_ECTRLDL0     CSI_SR1_ECTRLDL0F     /*!< Error control on data line 0 flag             */
+#define DCMIPP_CSI_FLAG_ESYNCESCDL0  CSI_SR1_ESYNCESCDL0F  /*!< Low-power data transmission synchronization
+                                                                error on data line 0 flag                     */
+#define DCMIPP_CSI_FLAG_EESCDL0      CSI_SR1_EESCDL0F      /*!< Escape entry error on data line 0 flag        */
+#define DCMIPP_CSI_FLAG_ESOTSYNCDL0  CSI_SR1_ESOTSYNCDL0F  /*!< SOT synchronization error on data line 0 flag */
+#define DCMIPP_CSI_FLAG_ESOTDL0      CSI_SR1_ESOTDL0F      /*!< SOT error on data line 0 flag                 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DCMIPP_Exported_Macros DCMIPP Exported Macros
+  * @brief    DCMIPP Exported Macros
+  * @{
+  */
+/**
+  * @brief  Enable the specified DCMIPP interrupts.
+  * @param  __HANDLE__    DCMIPP handle
+  * @param  __INTERRUPT__ specifies the DCMIPP interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
+  *            @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
+  *            @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE1_LINE Multi-line capture complete interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_FRAME Frame capture complete interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_VSYNC Vertical sync interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_OVR Overrun interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE2_LINE Multi-line capture complete interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_FRAME Frame capture complete interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_VSYNC Vertical sync interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_OVR Overrun interrupt for the pipe2
+  * @retval None
+  */
+#define __HAL_DCMIPP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CMIER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DCMIPP interrupts.
+  * @param  __HANDLE__    DCMIPP handle
+  * @param  __INTERRUPT__ specifies the DCMIPP interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
+  *            @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
+  *            @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE1_LINE Multi-line capture complete interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_FRAME Frame capture complete interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_VSYNC Vertical sync interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_OVR Overrun interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE2_LINE Multi-line capture complete interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_FRAME Frame capture complete interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_VSYNC Vertical sync interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_OVR Overrun interrupt for the pipe2
+  * @retval None
+  */
+#define __HAL_DCMIPP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CMIER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get the DCMIPP pending interrupt flags.
+  * @param  __HANDLE__ DCMIPP handle
+  * @param  __FLAG__   Get the specified flag.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_FLAG_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt flag
+  *            @arg DCMIPP_FLAG_PARALLEL_SYNC_ERR Synchronization error interrupt flag on parallel interface
+  *            @arg DCMIPP_FLAG_PIPE0_FRAME Frame capture complete interrupt flag for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_VSYNC Vertical sync interrupt flag for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_LINE Multi-line capture complete interrupt flag for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_LIMIT Limit interrupt flag for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_OVR Overrun interrupt flag for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE1_LINE Multi-line capture complete interrupt flag for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE1_FRAME Frame capture complete interrupt flag for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE1_VSYNC Vertical sync interrupt flag for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE1_OVR Overrun interrupt flag for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE2_LINE Multi-line capture complete interrupt flag for the pipe2
+  *            @arg DCMIPP_FLAG_PIPE2_FRAME Frame capture complete interrupt flag for the pipe2
+  *            @arg DCMIPP_FLAG_PIPE2_VSYNC Vertical sync interrupt flag for the pipe2
+  *            @arg DCMIPP_FLAG_PIPE2_OVR Overrun interrupt flag for the pipe2
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DCMIPP_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CMSR2 & (__FLAG__))
+
+/**
+  * @brief  Clear the DCMIPP pending interrupt flags.
+  * @param  __HANDLE__ DCMIPP handle
+  * @param  __FLAG__   specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_FLAG_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
+  *            @arg DCMIPP_FLAG_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
+  *            @arg DCMIPP_FLAG_PIPE0_FRAME Frame capture complete interrupt for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_VSYNC Vertical sync interrupt for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_LIMIT Limit interrupt for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE0_OVR Overrun interrupt for the pipe0
+  *            @arg DCMIPP_FLAG_PIPE1_LINE Multi-line capture complete interrupt for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE1_FRAME Frame capture complete interrupt for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE1_VSYNC Vertical sync interrupt for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE1_OVR Overrun interrupt for the pipe1
+  *            @arg DCMIPP_FLAG_PIPE2_LINE Multi-line capture complete interrupt for the pipe2
+  *            @arg DCMIPP_FLAG_PIPE2_FRAME Frame capture complete interrupt for the pipe2
+  *            @arg DCMIPP_FLAG_PIPE2_VSYNC Vertical sync interrupt for the pipe2
+  *            @arg DCMIPP_FLAG_PIPE2_OVR Overrun interrupt for the pipe2
+  * @retval None
+  */
+#define __HAL_DCMIPP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CMFCR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified DCMIPP interrupt is enabled or not.
+  * @param  __HANDLE__    DCMIPP handle
+  * @param  __INTERRUPT__ specifies the DCMIPP interrupt sources to be checked.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_IT_AXI_TRANSFER_ERR IPPLUG AXI Transfer error interrupt
+  *            @arg DCMIPP_IT_PARALLEL_SYNC_ERR Synchronization error interrupt on parallel interface
+  *            @arg DCMIPP_IT_PIPE0_FRAME Frame capture complete interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_VSYNC Vertical sync interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_LINE Multi-line capture complete interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_LIMIT Limit interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE0_OVR Overrun interrupt for the pipe0
+  *            @arg DCMIPP_IT_PIPE1_LINE Multi-line capture complete interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_FRAME Frame capture complete interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_VSYNC Vertical sync interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE1_OVR Overrun interrupt for the pipe1
+  *            @arg DCMIPP_IT_PIPE2_LINE Multi-line capture complete interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_FRAME Frame capture complete interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_VSYNC Vertical sync interrupt for the pipe2
+  *            @arg DCMIPP_IT_PIPE2_OVR Overrun interrupt for the pipe2
+  * @retval The state of DCMIPP interrupt (SET or RESET).
+  */
+#define __HAL_DCMIPP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CMIER & \
+                                                                 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Enable the specified DCMIPP CSI interrupts.
+  * @param  __HANDLE__    CSI handle
+  * @param  __INTERRUPT__ specifies the DCMIPP CSI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_IT_SYNCERR Synchronization error interrupt
+  *            @arg DCMIPP_CSI_IT_WDERR   Watchdog error interrupt
+  *            @arg DCMIPP_CSI_IT_SPKTERR Shorter packet than expected error interrupt
+  *            @arg DCMIPP_CSI_IT_IDERR   Data ID information error interrupt
+  *            @arg DCMIPP_CSI_IT_CECCERR Corrected ECC error interrupt
+  *            @arg DCMIPP_CSI_IT_ECCERR  ECC Error interrupt
+  *            @arg DCMIPP_CSI_IT_CRCERR  CRC Error interrupt
+  *            @arg DCMIPP_CSI_IT_CCFIFO  Clock changer FIFO full event interrupt
+  *            @arg DCMIPP_CSI_IT_SPKT    Short packet detection interrupt
+  *            @arg DCMIPP_CSI_IT_EOF3    EOF on virtual channel 3 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF2    EOF on virtual channel 2 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF1    EOF on virtual channel 1 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF0    EOF on virtual channel 0 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF3    SOF on virtual channel 3 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF2    SOF on virtual channel 2 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF1    SOF on virtual channel 1 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF0    SOF on virtual channel 0 interrupt
+  *            @arg DCMIPP_CSI_IT_TIM3    Timer 3 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM2    Timer 2 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM1    Timer 1 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM0    Timer 0 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB3     Line/byte event 3 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB2     Line/byte event 2 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB1     Line/byte event 1 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB0     Line/byte event 0 reached interrupt
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->IER0 |= (__INTERRUPT__))
+/**
+  * @brief  Disable the specified DCMIPP CSI interrupts.
+  * @param  __HANDLE__    CSI handle
+  * @param  __INTERRUPT__ specifies the DCMIPP CSI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_IT_SYNCERR Synchronization error interrupt
+  *            @arg DCMIPP_CSI_IT_WDERR   Watchdog error interrupt
+  *            @arg DCMIPP_CSI_IT_SPKTERR Shorter packet than expected error interrupt
+  *            @arg DCMIPP_CSI_IT_IDERR   Data ID information error interrupt
+  *            @arg DCMIPP_CSI_IT_CECCERR Corrected ECC error interrupt
+  *            @arg DCMIPP_CSI_IT_ECCERR  ECC Error interrupt
+  *            @arg DCMIPP_CSI_IT_CRCERR  CRC Error interrupt
+  *            @arg DCMIPP_CSI_IT_CCFIFO  Clock changer FIFO full event interrupt
+  *            @arg DCMIPP_CSI_IT_SPKT    Short packet detection interrupt
+  *            @arg DCMIPP_CSI_IT_EOF3    EOF on virtual channel 3 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF2    EOF on virtual channel 2 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF1    EOF on virtual channel 1 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF0    EOF on virtual channel 0 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF3    SOF on virtual channel 3 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF2    SOF on virtual channel 2 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF1    SOF on virtual channel 1 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF0    SOF on virtual channel 0 interrupt
+  *            @arg DCMIPP_CSI_IT_TIM3    Timer 3 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM2    Timer 2 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM1    Timer 1 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM0    Timer 0 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB3     Line/byte event 3 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB2     Line/byte event 2 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB1     Line/byte event 1 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB0     Line/byte event 0 reached interrupt
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->IER0 &= ~(__INTERRUPT__))
+/**
+  * @brief  Get the DCMIPP CSI pending interrupt flags.
+  * @param  __HANDLE__    CSI handle
+  * @param  __FLAG__   Get the specified flag.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_FLAG_SYNCERR Synchronization error flag
+  *            @arg DCMIPP_CSI_FLAG_WDERR   Watchdog error flag
+  *            @arg DCMIPP_CSI_FLAG_SPKTERR Shorter packet than expected error flag
+  *            @arg DCMIPP_CSI_FLAG_IDERR   Data ID information error flag
+  *            @arg DCMIPP_CSI_FLAG_CECCERR Corrected ECC error flag
+  *            @arg DCMIPP_CSI_FLAG_ECCERR  ECC Error flag
+  *            @arg DCMIPP_CSI_FLAG_CRCERR  CRC Error flag
+  *            @arg DCMIPP_CSI_FLAG_CCFIFO  Clock changer FIFO full event flag
+  *            @arg DCMIPP_CSI_FLAG_SPKT    Short packet detection flag
+  *            @arg DCMIPP_CSI_FLAG_EOF3    EOF on virtual channel 3 flag
+  *            @arg DCMIPP_CSI_FLAG_EOF2    EOF on virtual channel 2 flag
+  *            @arg DCMIPP_CSI_FLAG_EOF1    EOF on virtual channel 1 flag
+  *            @arg DCMIPP_CSI_FLAG_EOF0    EOF on virtual channel 0 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF3    SOF on virtual channel 3 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF2    SOF on virtual channel 2 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF1    SOF on virtual channel 1 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF0    SOF on virtual channel 0 flag
+  *            @arg DCMIPP_CSI_FLAG_TIM3    Timer 3 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_TIM2    Timer 2 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_TIM1    Timer 1 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_TIM0    Timer 0 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB3     Line/byte event 3 reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB2     Line/byte event 2 reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB1     Line/byte event 1 reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB0     Line/byte event 0 reached flag
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_GET_FLAG(__HANDLE__, __FLAG__)((__HANDLE__)->IER0 & (__FLAG__))
+/**
+  * @brief  Clear the DCMIPP CSI pending interrupt flags.
+  * @param  __HANDLE__    CSI handle
+  * @param  __FLAG__   specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_FLAG_SYNCERR Synchronization error flag
+  *            @arg DCMIPP_CSI_FLAG_WDERR   Watchdog error flag
+  *            @arg DCMIPP_CSI_FLAG_SPKTERR Shorter packet than expected error flag
+  *            @arg DCMIPP_CSI_FLAG_IDERR   Data ID information error flag
+  *            @arg DCMIPP_CSI_FLAG_CECCERR Corrected ECC error flag
+  *            @arg DCMIPP_CSI_FLAG_ECCERR  ECC Error flag
+  *            @arg DCMIPP_CSI_FLAG_CRCERR  CRC Error flag
+  *            @arg DCMIPP_CSI_FLAG_CCFIFO  Clock changer FIFO full event flag
+  *            @arg DCMIPP_CSI_FLAG_SPKT    Short packet detection flag
+  *            @arg DCMIPP_CSI_FLAG_EOF3    EOF on virtual channel 3 flag
+  *            @arg DCMIPP_CSI_FLAG_EOF2    EOF on virtual channel 2 flag
+  *            @arg DCMIPP_CSI_FLAG_EOF1    EOF on virtual channel 1 flag
+  *            @arg DCMIPP_CSI_FLAG_EOF0    EOF on virtual channel 0 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF3    SOF on virtual channel 3 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF2    SOF on virtual channel 2 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF1    SOF on virtual channel 1 flag
+  *            @arg DCMIPP_CSI_FLAG_SOF0    SOF on virtual channel 0 flag
+  *            @arg DCMIPP_CSI_FLAG_TIM3    Timer 3 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_TIM2    Timer 2 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_TIM1    Timer 1 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_TIM0    Timer 0 counter value reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB3     Line/byte event 3 reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB2     Line/byte event 2 reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB1     Line/byte event 1 reached flag
+  *            @arg DCMIPP_CSI_FLAG_LB0     Line/byte event 0 reached flag
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_CLEAR_FLAG(__HANDLE__, __FLAG__)((__HANDLE__)->FCR0 = (__FLAG__))
+/**
+  * @brief  Checks whether the specified DCMIPP interrupt is enabled or not.
+  * @param  __HANDLE__    DCMIPP handle
+  * @param  __INTERRUPT__ specifies the DCMIPP interrupt sources to be checked.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_IT_SYNCERR Synchronization error interrupt
+  *            @arg DCMIPP_CSI_IT_WDERR   Watchdog error interrupt
+  *            @arg DCMIPP_CSI_IT_SPKTERR Shorter packet than expected error interrupt
+  *            @arg DCMIPP_CSI_IT_IDERR   Data ID information error interrupt
+  *            @arg DCMIPP_CSI_IT_CECCERR Corrected ECC error interrupt
+  *            @arg DCMIPP_CSI_IT_ECCERR  ECC Error interrupt
+  *            @arg DCMIPP_CSI_IT_CRCERR  CRC Error interrupt
+  *            @arg DCMIPP_CSI_IT_CCFIFO  Clock changer FIFO full event interrupt
+  *            @arg DCMIPP_CSI_IT_SPKT    Short packet detection interrupt
+  *            @arg DCMIPP_CSI_IT_EOF3    EOF on virtual channel 3 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF2    EOF on virtual channel 2 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF1    EOF on virtual channel 1 interrupt
+  *            @arg DCMIPP_CSI_IT_EOF0    EOF on virtual channel 0 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF3    SOF on virtual channel 3 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF2    SOF on virtual channel 2 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF1    SOF on virtual channel 1 interrupt
+  *            @arg DCMIPP_CSI_IT_SOF0    SOF on virtual channel 0 interrupt
+  *            @arg DCMIPP_CSI_IT_TIM3    Timer 3 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM2    Timer 2 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM1    Timer 1 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_TIM0    Timer 0 counter value reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB3     Line/byte event 3 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB2     Line/byte event 2 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB1     Line/byte event 1 reached interrupt
+  *            @arg DCMIPP_CSI_IT_LB0     Line/byte event 0 reached interrupt
+  * @retval The state of DCMIPP interrupt (SET or RESET).
+  */
+#define __HAL_DCMIPP_CSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->IER0 & (__INTERRUPT__)) == \
+                                                                    (__INTERRUPT__)) ? SET : RESET)
+/**
+  * @brief  Enable the specified DCMIPP CSI DPHY interrupts.
+  * @param  __HANDLE__    CSI handle
+  * @param  __INTERRUPT__ specifies the DCMIPP CSI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_IT_ECTRLDL1    Error control on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESYNCESCDL1 Low-power data transmission synchronization error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_EESCDL1     Escape entry error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTSYNCDL1 SOT synchronization error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTDL1     SOT error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ECTRLDL0    Error control on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESYNCESCDL0 Low-power data transmission synchronization error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_EESCDL0     Escape entry error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTSYNCDL0 SOT synchronization error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTDL0     SOT error on data line 0 interrupt
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->IER1 |= (__INTERRUPT__))
+/**
+  * @brief  Disable the specified DCMIPP CSI DPHY interrupts.
+  * @param  __HANDLE__    CSI handle
+  * @param  __INTERRUPT__ specifies the DCMIPP CSI interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_IT_ECTRLDL1    Error control on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESYNCESCDL1 Low-power data transmission synchronization error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_EESCDL1     Escape entry error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTSYNCDL1 SOT synchronization error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTDL1     SOT error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ECTRLDL0    Error control on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESYNCESCDL0 Low-power data transmission synchronization error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_EESCDL0     Escape entry error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTSYNCDL0 SOT synchronization error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTDL0     SOT error on data line 0 interrupt
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_DPHY_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->IER1 &= ~(__INTERRUPT__))
+/**
+  * @brief  Get the DCMIPP CSI DPHY pending interrupt flags.
+  * @param  __HANDLE__    CSI handle
+  * @param  __FLAG__   Get the specified flag.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_FLAG_ECTRLDL1    Error control on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ESYNCESCDL1 Low-power data transmission synchronization error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_EESCDL1     Escape entry error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTSYNCDL1 SOT synchronization error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTDL1     SOT error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ECTRLDL0    Error control on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_ESYNCESCDL0 Low-power data transmission synchronization error on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_EESCDL0     Escape entry error on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTSYNCDL0 SOT synchronization error on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTDL0     SOT error on data line 0 flag
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_GET_DPHY_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->IER1 & (__FLAG__))
+/**
+  * @brief  Clear the DCMIPP CSI DPHY pending interrupt flags.
+  * @param  __HANDLE__    CSI handle
+  * @param  __FLAG__   specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_FLAG_ECTRLDL1    Error control on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ESYNCESCDL1 Low-power data transmission synchronization error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_EESCDL1     Escape entry error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTSYNCDL1 SOT synchronization error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTDL1     SOT error on data line 1 flag
+  *            @arg DCMIPP_CSI_FLAG_ECTRLDL0    Error control on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_ESYNCESCDL0 Low-power data transmission synchronization error on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_EESCDL0     Escape entry error on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTSYNCDL0 SOT synchronization error on data line 0 flag
+  *            @arg DCMIPP_CSI_FLAG_ESOTDL0     SOT error on data line 0 flag
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(__HANDLE__, __FLAG__)((__HANDLE__)->FCR1 = (__FLAG__))
+/**
+  * @brief  Checks whether the specified DCMIPP CSI DPHY interrupt is enabled or not.
+  * @param  __HANDLE__    CSI handle
+  * @param  __INTERRUPT__ specifies the DCMIPP CSI D-PHY interrupt sources to be checked.
+  *         This parameter can be any combination of the following values:
+  *            @arg DCMIPP_CSI_IT_ECTRLDL1    Error control on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESYNCESCDL1 Low-power data transmission synchronization error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_EESCDL1     Escape entry error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTSYNCDL1 SOT synchronization error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTDL1     SOT error on data line 1 interrupt
+  *            @arg DCMIPP_CSI_IT_ECTRLDL0    Error control on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESYNCESCDL0 Low-power data transmission synchronization error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_EESCDL0     Escape entry error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTSYNCDL0 SOT synchronization error on data line 0 interrupt
+  *            @arg DCMIPP_CSI_IT_ESOTDL0     SOT error on data line 0 interrupt
+  * @retval None
+  */
+#define __HAL_DCMIPP_CSI_GET_DPHY_IT_SOURCE(__HANDLE__,  __INTERRUPT__)((((__HANDLE__)->IER1 & (__INTERRUPT__)) == \
+                                                                         (__INTERRUPT__)) ? SET : RESET)
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DCMIPP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DCMIPP_Initialization_De-Initialization_Functions DCMIPP Initialization De-Initialization Functions
+  * @brief      Initialization and De-Initialization Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_Init(DCMIPP_HandleTypeDef *hdcmipp);
+HAL_StatusTypeDef HAL_DCMIPP_DeInit(DCMIPP_HandleTypeDef *hdcmipp);
+void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef *hdcmipp);
+void HAL_DCMIPP_MspDeInit(DCMIPP_HandleTypeDef *hdcmipp);
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Configuration_Functions DCMIPP Configuration Functions
+  * @brief    Configuration Functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetConfig(DCMIPP_HandleTypeDef *hdcmipp,
+                                                const DCMIPP_ParallelConfTypeDef *pParallelConfig);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp,
+                                                uint32_t Pipe, const DCMIPP_CSI_PIPE_ConfTypeDef *pCSI_PipeConfig);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetConfig(const DCMIPP_HandleTypeDef *hdcmipp,
+                                           const DCMIPP_CSI_ConfTypeDef *pCSI_Config);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetVCFilteringConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel,
+                                                      const DCMIPP_CSI_VCFilteringConfTypeDef *pVCFilteringConfig);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetVCConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel,
+                                             uint32_t DataTypeFormat);
+
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                            const DCMIPP_PipeConfTypeDef *pPipeConfig);
+HAL_StatusTypeDef HAL_DCMIPP_SetIPPlugConfig(DCMIPP_HandleTypeDef *hdcmipp,
+                                             const DCMIPP_IPPlugConfTypeDef *pIPPlugConfig);
+/**
+  * @}
+  */
+
+/** @addtogroup DCMIPP_IO_operation_Functions DCMIPP IO operation Functions
+  * @brief      IO Operation Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress,
+                                        uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
+                                                    uint32_t DstAddress1, uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel,
+                                            uint32_t DstAddress, uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                        uint32_t VirtualChannel, uint32_t DstAddress0,
+                                                        uint32_t DstAddress1, uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                  DCMIPP_SemiPlanarDstAddressTypeDef *pSemiPlanarDstAddress,
+                                                  uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              DCMIPP_SemiPlanarDstAddressTypeDef
+                                                              *pSemiPlanarDstAddress0,
+                                                              DCMIPP_SemiPlanarDstAddressTypeDef
+                                                              *pSemiPlanarDstAddress1, uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                  DCMIPP_FullPlanarDstAddressTypeDef *pFullPlanarDstAddress,
+                                                  uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              DCMIPP_FullPlanarDstAddressTypeDef
+                                                              *pFullPlanarDstAddress0,
+                                                              DCMIPP_FullPlanarDstAddressTypeDef
+                                                              *pFullPlanarDstAddress1, uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                      uint32_t VirtualChannel,
+                                                      DCMIPP_SemiPlanarDstAddressTypeDef *pSemiPlanarDstAddress,
+                                                      uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                  uint32_t VirtualChannel,
+                                                                  DCMIPP_SemiPlanarDstAddressTypeDef
+                                                                  *pSemiPlanarDstAddress0,
+                                                                  DCMIPP_SemiPlanarDstAddressTypeDef
+                                                                  *pSemiPlanarDstAddress1, uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                      uint32_t VirtualChannel,
+                                                      DCMIPP_FullPlanarDstAddressTypeDef *pFullPlanarDstAddress,
+                                                      uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                  uint32_t VirtualChannel,
+                                                                  DCMIPP_FullPlanarDstAddressTypeDef
+                                                                  *pFullPlanarDstAddress0,
+                                                                  DCMIPP_FullPlanarDstAddressTypeDef
+                                                                  *pFullPlanarDstAddress1,
+                                                                  uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Suspend(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Resume(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DCMIPP_IRQ_and_Callbacks_Functions DCMIPP IRQ and Callbacks Functions
+  * @brief      IRQ and Callbacks functions
+  * @{
+  */
+/** @addtogroup DCMIPP_IRQHandler_Function IRQHandler Function
+  * @{
+  */
+void HAL_DCMIPP_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp);
+void HAL_DCMIPP_CSI_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp);
+/**
+  * @}
+  */
+/** @addtogroup DCMIPP_Callback_Functions Callback Functions
+  * @{
+  */
+void HAL_DCMIPP_PIPE_FrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+void HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+void HAL_DCMIPP_PIPE_LineEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+void HAL_DCMIPP_PIPE_LimitEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+void HAL_DCMIPP_PIPE_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+void HAL_DCMIPP_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp);
+/**
+  * @}
+  */
+
+/** @addtogroup DCMIPP_CSI_Callback_Functions CSI Callback Functions
+  * @{
+  */
+void HAL_DCMIPP_CSI_StartOfFrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel);
+void HAL_DCMIPP_CSI_EndOfFrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel);
+void HAL_DCMIPP_CSI_TimerCounterEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer);
+void HAL_DCMIPP_CSI_LineByteEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter);
+void HAL_DCMIPP_CSI_LineErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t DataLane);
+void HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback(DCMIPP_HandleTypeDef *hdcmipp);
+void HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback(DCMIPP_HandleTypeDef *hdcmipp);
+/**
+  * @}
+  */
+/** @addtogroup DCMIPP_RegisterCallback_Functions Register Callback Functions
+  * @{
+  */
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DCMIPP_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID,
+                                              pDCMIPP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCMIPP_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
+                                                HAL_DCMIPP_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
+                                                   HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID,
+                                                   pDCMIPP_PIPE_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
+                                                     HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Decimation_Functions DCMIPP Decimation Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetBytesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           uint32_t SelectStart, uint32_t SelectMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLinesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           uint32_t SelectStart, uint32_t SelectMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         const DCMIPP_DecimationConfTypeDef *pDecConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                      const DCMIPP_DecimationConfTypeDef *pDecConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Crop_Functions DCMIPP Crop Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCropConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                const DCMIPP_CropConfTypeDef *pCropConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Line_Event_Functions DCMIPP Line Event Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Line);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_LimitEvent_Functions DCMIPP Limit Event Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Limit);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+/**
+  * @}
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPStatisticExtractionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                  uint8_t ModuleID, const
+                                                                  DCMIPP_StatisticExtractionConfTypeDef
+                                                                  *pStatisticExtractionConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPAreaStatisticExtractionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                      const DCMIPP_StatisticExtractionAreaConfTypeDef
+                                                                      *pStatisticExtractionAreaConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint8_t ModuleID);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                uint8_t ModuleID);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetDownsizeConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                    const DCMIPP_DownsizeTypeDef *pDownsizeConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableDownsize(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableDownsize(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPBlackLevelCalibrationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                    const DCMIPP_BlackLevelConfTypeDef
+                                                                    *pBlackLevelConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPBlackLevelCalibration(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPBlackLevelCalibration(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableGammaConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableGammaConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledGammaConversion(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPBadPixelRemovalConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              uint32_t Strength);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPBadPixelRemoval(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPBadPixelRemoval(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPCtrlContrastConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           const DCMIPP_ContrastConfTypeDef *pContrastConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPCtrlContrast(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPCtrlContrast(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetRegionOfInterestConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                            const DCMIPP_RegionOfInterestConfTypeDef *pROIConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableRegionOfInterest(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         uint32_t Region);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableRegionOfInterest(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                          uint32_t Region);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLineWrappingConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                        uint32_t AddressWrap);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineWrapping(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineWrapping(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPExposureConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                       const DCMIPP_ExposureConfTypeDef *pExposureConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPExposure(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPExposure(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPRemovalStatisticConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint32_t NbFirstLines, uint32_t NbLastLines);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPRemovalStatistic(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPRemovalStatistic(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPRawBayer2RGBConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           const DCMIPP_RawBayer2RGBConfTypeDef *pRawBayer2RGBConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPRawBayer2RGB(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPRawBayer2RGB(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetYUVConversionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         const DCMIPP_ColorConversionConfTypeDef
+                                                         *pColorConversionConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableYUVConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableYUVConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPColorConversionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              const DCMIPP_ColorConversionConfTypeDef
+                                                              *pColorConversionConfig);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPColorConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPColorConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+void HAL_DCMIPP_PIPE_GetISPDecimationConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                            DCMIPP_DecimationConfTypeDef *pDecConfig);
+void HAL_DCMIPP_PIPE_GetISPBlackLevelCalibrationConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                       DCMIPP_BlackLevelConfTypeDef *pBlackLevelConfig);
+uint32_t HAL_DCMIPP_PIPE_GetISPBadPixelRemovalConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+void HAL_DCMIPP_PIPE_GetISPStatisticExtractionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                     uint8_t ModuleID,
+                                                     DCMIPP_StatisticExtractionConfTypeDef
+                                                     *pStatisticExtractionConfig);
+void HAL_DCMIPP_PIPE_GetISPAreaStatisticExtractionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         DCMIPP_StatisticExtractionAreaConfTypeDef
+                                                         *pStatisticExtractionAreaConfig);
+void HAL_DCMIPP_PIPE_GetISPCtrlContrastConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                              DCMIPP_ContrastConfTypeDef *pContrastConfig);
+void HAL_DCMIPP_PIPE_GetISPExposureConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                          DCMIPP_ExposureConfTypeDef *pExposureConfig);
+void HAL_DCMIPP_PIPE_GetISPRawBayer2RGBConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                              DCMIPP_RawBayer2RGBConfTypeDef *pRawBayer2RGBConfig);
+void HAL_DCMIPP_PIPE_GetISPColorConversionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                 DCMIPP_ColorConversionConfTypeDef *pColorConversionConfig);
+void HAL_DCMIPP_PIPE_GetISPRemovalStatisticConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                  uint32_t *NbFirstLines, uint32_t *NbLastLines);
+
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPRemovalStatistic(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPBadPixelRemoval(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPDecimation(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPBlackLevelCalibration(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPExposure(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPRawBayer2RGB(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPColorConversion(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPCtrlContrast(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPStatisticExtraction(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         uint8_t ModuleID);
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPAreaStatisticExtraction(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+
+
+/** @defgroup DCMIPP_PeripheralControl_Functions DCMIPP Peripheral Control Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameRate(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t FrameRate);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCaptureMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t CaptureMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetMemoryAddress(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Memory,
+                                                   uint32_t DstAddress);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_PARALLEL_SetInputPixelFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint32_t InputPixelFormat);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetPitch(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t LinePitch);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetPixelPackerFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                       uint32_t PixelPackerFormat);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_EnableShare(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_DisableShare(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_ForceDataTypeFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                          uint32_t DataTypeFormat);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_SetDTMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                uint32_t DataTypeMode);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_SetDTSelection(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DataTypeID,
+                                                     uint32_t DataType);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_EnableHeader(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_DisableHeader(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef *hdcmipp,
+                                                    const DCMIPP_EmbeddedSyncUnmaskTypeDef *SyncUnmask);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetLineByteCounterConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter,
+                                                          const DCMIPP_CSI_LineByteCounterConfTypeDef *pLineByteConfig);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_EnableLineByteCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_DisableLineByteCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetTimerConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer,
+                                                const DCMIPP_CSI_TimerConfTypeDef *TimerConfig);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_EnableTimer(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_DisableTimer(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer);
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetWatchdogCounterConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter);
+
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableComponentsSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableComponentsSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableRedBlueSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableRedBlueSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableYUVSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableYUVSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Frame_Counter_Functions DCMIPP Frame Counter Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameCounterConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_ResetFrameCounter(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_ReadFrameCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                   uint32_t *pCounter);
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Data_Counter_Functions DCMIPP Data Counter Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetDataCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                 uint32_t *pCounter);
+/**
+  * @}
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetISPRemovedBadPixelCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint32_t *pCounter);
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetISPAccumulatedStatisticsCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                     uint8_t ModuleID, uint32_t *pCounter);
+uint32_t HAL_DCMIPP_GetMode(const DCMIPP_HandleTypeDef *hdcmipp);
+uint32_t HAL_DCMIPP_PIPE_GetMemoryAddress(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t MemoryAddress);
+
+/** @addtogroup DCMIPP_State_and_Error_Functions DCMIPP State and Error Functions
+  * @{
+  */
+HAL_DCMIPP_StateTypeDef HAL_DCMIPP_GetState(const DCMIPP_HandleTypeDef *hdcmipp);
+HAL_DCMIPP_PipeStateTypeDef HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp);
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DCMIPP_Private_Macros DCMIPP Private Macros
+  * @{
+  */
+#define IS_DCMIPP_PIPE(PIPE) (((PIPE) == DCMIPP_PIPE0) || \
+                              ((PIPE) == DCMIPP_PIPE1) || \
+                              ((PIPE) == DCMIPP_PIPE2))
+#define IS_DCMIPP_FORMAT(FORMAT) (((FORMAT) == DCMIPP_FORMAT_BYTE)   ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_YUV422) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_RGB565) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_RGB666) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_RGB888) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_RAW8  ) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_RAW10 ) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_RAW12 ) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_RAW14 ) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_8B)  ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_10B) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_12B) ||\
+                                  ((FORMAT) == DCMIPP_FORMAT_MONOCHROME_14B))
+
+#define IS_DCMIPP_PIXEL_PACKER_FORMAT(FORMAT) (((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_RGB888_YUV444_1) ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_RGB565_1)        ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_ARGB8888)        ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_RGBA888)         ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_MONO_Y8_G8_1)    ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV444_1)        ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1)        ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV422_2)        ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_2)        ||\
+                                               ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_3))
+
+#define IS_DCMIPP_PIXEL_PIPE_PITCH(PITCH) ((((PITCH) & 0xFU) == 0U) && ((PITCH) <= 0x7FFFU))
+
+#define IS_DCMIPP_PCKPOLARITY(POLARITY)(((POLARITY) == DCMIPP_PCKPOLARITY_FALLING) || \
+                                        ((POLARITY) == DCMIPP_PCKPOLARITY_RISING))
+
+#define IS_DCMIPP_VSPOLARITY(POLARITY)(((POLARITY) == DCMIPP_VSPOLARITY_LOW) || \
+                                       ((POLARITY) == DCMIPP_VSPOLARITY_HIGH))
+
+#define IS_DCMIPP_HSPOLARITY(POLARITY)(((POLARITY) == DCMIPP_HSPOLARITY_LOW) || \
+                                       ((POLARITY) == DCMIPP_HSPOLARITY_HIGH))
+
+
+#define IS_DCMIPP_EXTENDED_DATA_MODE(INTERFACE)(((INTERFACE) == DCMIPP_INTERFACE_8BITS ) ||\
+                                                ((INTERFACE) == DCMIPP_INTERFACE_10BITS) ||\
+                                                ((INTERFACE) == DCMIPP_INTERFACE_12BITS) ||\
+                                                ((INTERFACE) == DCMIPP_INTERFACE_14BITS) ||\
+                                                ((INTERFACE) == DCMIPP_INTERFACE_16BITS))
+
+#define IS_DCMIPP_SYNC_MODE(SYNC_MODE) (((SYNC_MODE) == DCMIPP_SYNCHRO_HARDWARE) ||\
+                                        ((SYNC_MODE) == DCMIPP_SYNCHRO_EMBEDDED))
+
+#define IS_DCMIPP_SWAP_BITS(SWAP_BITS)  (((SWAP_BITS) == DCMIPP_SWAPBITS_ENABLE) ||\
+                                         ((SWAP_BITS) == DCMIPP_SWAPBITS_DISABLE))
+
+#define IS_DCMIPP_SWAP_CYCLES(SWAP_CYCLES) (((SWAP_CYCLES) == DCMIPP_SWAPCYCLES_ENABLE) ||\
+                                            ((SWAP_CYCLES) == DCMIPP_SWAPCYCLES_DISABLE))
+
+#define IS_DCMIPP_VCID(VCID) (((VCID) == DCMIPP_VIRTUAL_CHANNEL0) ||\
+                              ((VCID) == DCMIPP_VIRTUAL_CHANNEL1) ||\
+                              ((VCID) == DCMIPP_VIRTUAL_CHANNEL2) ||\
+                              ((VCID) == DCMIPP_VIRTUAL_CHANNEL3))
+
+#define IS_DCMIPP_DATA_TYPE_MODE(DATA_TYPE_MODE) (((DATA_TYPE_MODE) == DCMIPP_DTMODE_DTIDA) ||\
+                                                  ((DATA_TYPE_MODE) == DCMIPP_DTMODE_DTIDA_OR_DTIDB) ||\
+                                                  ((DATA_TYPE_MODE) == DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB) ||\
+                                                  ((DATA_TYPE_MODE) == DCMIPP_DTMODE_ALL))
+
+#define IS_DCMIPP_DATA_TYPE(DATA_TYPE) (((DATA_TYPE) == DCMIPP_DT_RGB565) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RGB444) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RGB555) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RGB666) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RGB888) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_YUV420_8) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_YUV420_10) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_YUV422_8) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_YUV422_10) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RAW8) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RAW10) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RAW12) ||\
+                                        ((DATA_TYPE) == DCMIPP_DT_RAW14))
+
+#define IS_DCMIPP_NUMBER_OF_LANES(DATA_LANE_NB) (((DATA_LANE_NB) == DCMIPP_CSI_ONE_DATA_LANE) ||\
+                                                 ((DATA_LANE_NB) == DCMIPP_CSI_TWO_DATA_LANES))
+
+#define IS_DCMIPP_CSI_DATA_LANE_MAPPING(DATA_LANE_MAP) (((DATA_LANE_MAP) == DCMIPP_CSI_PHYSICAL_DATA_LANES) ||\
+                                                        ((DATA_LANE_MAP) == DCMIPP_CSI_INVERTED_DATA_LANES))
+#define IS_DCMIPP_CSI_DATA_PHY_BITRATE(PHY_BITRATE) ((PHY_BITRATE) <= DCMIPP_CSI_PHY_BT_2500)
+#define IS_DCMIPP_CSI_DATA_TYPE_NB(DATA_TYPE_NB) ((DATA_TYPE_NB) <= MAX_DATATYPE_NB)
+
+#define IS_DCMIPP_CSI_DATA_TYPE_FORMAT(DATA_TYPE_FORMAT) (((DATA_TYPE_FORMAT) == DCMIPP_CSI_DT_BPP6)  ||\
+                                                          ((DATA_TYPE_FORMAT) == DCMIPP_CSI_DT_BPP7)  ||\
+                                                          ((DATA_TYPE_FORMAT) == DCMIPP_CSI_DT_BPP8)  ||\
+                                                          ((DATA_TYPE_FORMAT) == DCMIPP_CSI_DT_BPP10) ||\
+                                                          ((DATA_TYPE_FORMAT) == DCMIPP_CSI_DT_BPP12) ||\
+                                                          ((DATA_TYPE_FORMAT) == DCMIPP_CSI_DT_BPP14) ||\
+                                                          ((DATA_TYPE_FORMAT) == DCMIPP_CSI_DT_BPP16))
+#define IS_DCMIPP_CSI_DATA_CLASS(DATA_TYPE_CLASS)((DATA_TYPE_CLASS) <= 0x3FU)
+#define IS_DCMIPP_CSI_COUNTER(COUNTER) (((COUNTER) == DCMIPP_CSI_COUNTER0) ||\
+                                        ((COUNTER) == DCMIPP_CSI_COUNTER1) ||\
+                                        ((COUNTER) == DCMIPP_CSI_COUNTER2) ||\
+                                        ((COUNTER) == DCMIPP_CSI_COUNTER3))
+#define IS_DCMIPP_CSI_LINE_COUNTER(LINE_COUNTER)((LINE_COUNTER) <= 0xFFFFU)
+#define IS_DCMIPP_CSI_BYTE_COUNTER(BYTE_COUNTER)((BYTE_COUNTER) <= 0xFFFFU)
+
+#define IS_DCMIPP_CSI_TIMER(TIMER) (((TIMER) == DCMIPP_CSI_TIMER0) ||\
+                                    ((TIMER) == DCMIPP_CSI_TIMER1) ||\
+                                    ((TIMER) == DCMIPP_CSI_TIMER2) ||\
+                                    ((TIMER) == DCMIPP_CSI_TIMER3))
+#define IS_DCMIPP_CSI_TIMER_START(TIMER_START) (((TIMER_START) == DCMIPP_CSI_TIMER_START_SOF)||\
+                                                ((TIMER_START) == DCMIPP_CSI_TIMER_START_EOF))
+
+
+#define IS_DCMIPP_FRAME_RATE(FRAME_RATE) (((FRAME_RATE) == DCMIPP_FRAME_RATE_ALL)      ||\
+                                          ((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_2) ||\
+                                          ((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_4) ||\
+                                          ((FRAME_RATE) == DCMIPP_FRAME_RATE_1_OVER_8))
+#define IS_DCMIPP_CLIENT(CLIENT) (((CLIENT) == DCMIPP_CLIENT1) ||\
+                                  ((CLIENT) == DCMIPP_CLIENT2) ||\
+                                  ((CLIENT) == DCMIPP_CLIENT3) ||\
+                                  ((CLIENT) == DCMIPP_CLIENT4) ||\
+                                  ((CLIENT) == DCMIPP_CLIENT5))
+
+#define IS_DCMIPP_DPREG_END(DPREG_END) ((DPREG_END) <= 0x3FFU)
+#define IS_DCMIPP_DPREG_START(DPREG_START) ((DPREG_START) <= 0x3FFU)
+
+#define IS_DCMIPP_MAX_OUTSTANDING_TRANSACTIONS(OUTS_TRANS) (((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_NONE )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_2    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_3    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_4    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_5    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_6    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_7    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_8    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_9    )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_10   )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_11   )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_12   )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_13   )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_14   )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_15   )||\
+                                                            ((OUTS_TRANS) == DCMIPP_OUTSTANDING_TRANSACTION_16   ))
+
+#define IS_DCMIPP_MEMORY_PAGE_SIZE(MEMORY_PAGE_SIZE) (((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_64BYTES)  ||\
+                                                      ((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_128BYTES) ||\
+                                                      ((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_256BYTES) ||\
+                                                      ((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_512BYTES) ||\
+                                                      ((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_1KBYTES)  ||\
+                                                      ((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_2KBYTES)  ||\
+                                                      ((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_4KBYTES)  ||\
+                                                      ((MEMORY_PAGE_SIZE) ==  DCMIPP_MEMORY_PAGE_SIZE_8KBYTES))
+#define IS_DCMIPP_TRAFFIC(TRAFFIC) (((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_8BYTES ) ||\
+                                    ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_16BYTES) ||\
+                                    ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_32BYTES) ||\
+                                    ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_64BYTES) ||\
+                                    ((TRAFFIC) == DCMIPP_TRAFFIC_BURST_SIZE_128BYTES))
+#define IS_DCMIPP_WLRU_RATIO(WLRU_RATIO) ((WLRU_RATIO)<= 0xFU)
+
+#define IS_DCMIPP_CAPTURE_MODE(CAPTURE_MODE) (((CAPTURE_MODE) == DCMIPP_MODE_CONTINUOUS)||\
+                                              ((CAPTURE_MODE) == DCMIPP_MODE_SNAPSHOT))
+
+#define IS_DCMIPP_PIPE_CROP_AREA(CROP_AREA)(((CROP_AREA) == DCMIPP_POSITIVE_AREA) ||\
+                                            ((CROP_AREA) == DCMIPP_NEGATIVE_AREA))
+
+#define IS_DCMIPP_PIPE_CROP_HSIZE(CROP_HSIZE) (((CROP_HSIZE) >= 0x1U) && ((CROP_HSIZE) <= 0xFFFU))
+#define IS_DCMIPP_PIPE_CROP_VSIZE(CROP_VSIZE) (((CROP_VSIZE) >= 0x1U) && ((CROP_VSIZE) <= 0xFFFU))
+#define IS_DCMIPP_PIPE_CROP_VSTART(CROP_VSTART) ((CROP_VSTART) <= 0xFFFU)
+#define IS_DCMIPP_PIPE_CROP_HSTART(CROP_HSTART) ((CROP_HSTART) <= 0xFFFU)
+
+#define IS_DCMIPP_BYTE_SELECT_MODE(BYTE_SELECT) (((BYTE_SELECT) == DCMIPP_BSM_ALL)        ||\
+                                                 ((BYTE_SELECT) == DCMIPP_BSM_DATA_OUT_2) ||\
+                                                 ((BYTE_SELECT) == DCMIPP_BSM_BYTE_OUT_4) ||\
+                                                 ((BYTE_SELECT) == DCMIPP_BSM_2BYTE_OUT_4))
+
+#define IS_DCMIPP_BYTE_SELECT_START(BYTE_START)(((BYTE_START) == DCMIPP_OEBS_ODD) ||\
+                                                ((BYTE_START) == DCMIPP_OEBS_EVEN))
+
+#define IS_DCMIPP_LINE_SELECT_MODE(LINE_SELECT) (((LINE_SELECT) == DCMIPP_LSM_ALL) ||\
+                                                 ((LINE_SELECT) == DCMIPP_LSM_ALTERNATE_2))
+
+#define IS_DCMIPP_LINE_SELECT_START(LINE__START)(((LINE__START) == DCMIPP_OELS_ODD) ||\
+                                                 ((LINE__START) == DCMIPP_OELS_EVEN))
+
+#define IS_DCMIPP_MEMORY_ADDRESS(MEMORY_ADDRESS) (((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_0) ||\
+                                                  ((MEMORY_ADDRESS) == DCMIPP_MEMORY_ADDRESS_1))
+
+#define IS_DCMIPP_DATA_LIMIT(DATA_LIMIT) (((DATA_LIMIT) >=1U ) && ((DATA_LIMIT) <= 0xFFFFFFU))
+
+#define IS_DCMIPP_PIPE_MULTILINE(MULTILINE) (((MULTILINE) == DCMIPP_MULTILINE_1_LINE )   ||\
+                                             ((MULTILINE) == DCMIPP_MULTILINE_2_LINES)  ||\
+                                             ((MULTILINE) == DCMIPP_MULTILINE_4_LINES)  ||\
+                                             ((MULTILINE) == DCMIPP_MULTILINE_8_LINES)  ||\
+                                             ((MULTILINE) == DCMIPP_MULTILINE_16_LINES) ||\
+                                             ((MULTILINE) == DCMIPP_MULTILINE_32_LINES) ||\
+                                             ((MULTILINE) == DCMIPP_MULTILINE_64_LINES) ||\
+                                             ((MULTILINE) == DCMIPP_MULTILINE_128_LINES))
+#define IS_DCMIPP_VRATIO(VRATIO) (((VRATIO) == DCMIPP_VDEC_ALL)     ||\
+                                  ((VRATIO) == DCMIPP_VDEC_1_OUT_2) ||\
+                                  ((VRATIO) == DCMIPP_VDEC_1_OUT_4) ||\
+                                  ((VRATIO) == DCMIPP_VDEC_1_OUT_8))
+
+#define IS_DCMIPP_HRATIO(HRATIO) (((HRATIO) == DCMIPP_HDEC_ALL)     ||\
+                                  ((HRATIO) == DCMIPP_HDEC_1_OUT_2) ||\
+                                  ((HRATIO) == DCMIPP_HDEC_1_OUT_4) ||\
+                                  ((HRATIO) == DCMIPP_HDEC_1_OUT_8))
+
+#define IS_DCMIPP_DOWSIZE_DIV_FACTOR(DIV_FACTOR) (((DIV_FACTOR)>=0x80U) && ((DIV_FACTOR)<= 0x3FFU))
+#define IS_DCMIPP_DOWSIZE_RATIO(RATIO) ((RATIO)<= 0xFFFFU)
+#define IS_DCMIPP_DOWSIZE_SIZE(SIZE) ((SIZE) <= 0xFFFU)
+
+#define IS_DCMIPP_RAWBAYER2RGB_RAW_TYPE(RAW_TYPE) (((RAW_TYPE) == DCMIPP_RAWBAYER_RGGB) ||\
+                                                   ((RAW_TYPE) == DCMIPP_RAWBAYER_GRBG) ||\
+                                                   ((RAW_TYPE) == DCMIPP_RAWBAYER_GBRG) ||\
+                                                   ((RAW_TYPE) == DCMIPP_RAWBAYER_BGGR))
+
+#define IS_DCMIPP_RAWBAYER2RGB_STRENGTH(STRENGTH) (((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_NONE)       ||\
+                                                   ((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_STRENGTH_3) ||\
+                                                   ((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_STRENGTH_4) ||\
+                                                   ((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_STRENGTH_6) ||\
+                                                   ((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_STRENGTH_8) ||\
+                                                   ((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_STRENGTH_12)||\
+                                                   ((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_STRENGTH_16)||\
+                                                   ((STRENGTH) ==  DCMIPP_RAWBAYER_ALGO_STRENGTH_24))
+
+#define IS_DCMIPP_NB_FIRST_LINES(NB_FIRST_LINES) ((NB_FIRST_LINES) <= 7U)
+
+#define IS_DCMIPP_NB_LAST_LINES(NB_LAST_LINES) ((NB_LAST_LINES) <= 0xFFFU)
+
+#define IS_DCMIPP_BAD_PXL_REMOVAL_STRENGTH(STRENGTH) (((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_0) ||\
+                                                      ((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_1) ||\
+                                                      ((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_2) ||\
+                                                      ((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_3) ||\
+                                                      ((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_4) ||\
+                                                      ((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_5) ||\
+                                                      ((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_6) ||\
+                                                      ((STRENGTH) ==  DCMIPP_BAD_PXL_REM_SRENGTH_7))
+
+#define IS_DCMIPP_ROI_COLOR(COLOR) ((COLOR) <= 3U)
+#define IS_DCMIPP_ROI_SIZE(SIZE) ((SIZE) <= 3U)
+#define IS_DCMIPP_ROI_START(START) ((START) <= 3U)
+#define IS_DCMIPP_ROI_LINE_WIDTH(LINE_WIDTH) ((LINE_WIDTH) <= DCMIPP_LINE_WIDTH_8PXL)
+#define IS_DCMIPP_ROI(REGION_OF_INTEREST) ((REGION_OF_INTEREST) <= DCMIPP_REGION_OF_INTEREST8)
+
+#define IS_DCMIPP_ADDRESS_WRAP(ADDRESS_WRAP) (((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_1_LINE)   ||\
+                                              ((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_2_LINES)  ||\
+                                              ((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_4_LINES)  ||\
+                                              ((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_8_LINES)  ||\
+                                              ((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_16_LINES) ||\
+                                              ((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_32_LINES) ||\
+                                              ((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_64_LINES) ||\
+                                              ((ADDRESS_WRAP) == DCMIPP_WRAP_ADDRESS_128_LINES))
+
+#define IS_DCMIPP_OUTPUT_SAMPLES_TYPES(OUTPUT_SAMPLES_TYPES) (((OUTPUT_SAMPLES_TYPES) == DCMIPP_CLAMP_YUV) ||\
+                                                              ((OUTPUT_SAMPLES_TYPES) == DCMIPP_CLAMP_RGB))
+#define IS_DCMIPP_COLOR_CONVERSION_COEF(COLOR_CONV_CONF) ((COLOR_CONV_CONF) <= 0x7FF)
+
+#define IS_DCMIPP_STAT_EXTRACTION_MODULE(MODULE) (((MODULE) == DCMIPP_STATEXT_MODULE1)||\
+                                                  ((MODULE) == DCMIPP_STATEXT_MODULE2)||\
+                                                  ((MODULE) == DCMIPP_STATEXT_MODULE3))
+
+#define IS_DCMIPP_LUMINANCE(LUMINANCE) ((LUMINANCE) <= 0x3FU)
+
+#define IS_DCMIPP_EXPOSURE_SHF(CHIFT) ((CHIFT) <= 0x7U)
+
+#define IS_DCMIPP_STAT_EXTRACTION_BINS(BINS) (((BINS) ==  DCMIPP_STAT_EXT_BINS_MODE_LOWER_BINS)  ||\
+                                              ((BINS) == DCMIPP_STAT_EXT_BINS_MODE_LOWMID_BINS) ||\
+                                              ((BINS) == DCMIPP_STAT_EXT_BINS_MODE_UPMID_BINS ) ||\
+                                              ((BINS) == DCMIPP_STAT_EXT_BINS_MODE_UP_BINS    ) ||\
+                                              ((BINS) == DCMIPP_STAT_EXT_AVER_MODE_ALL_PIXELS ) ||\
+                                              ((BINS) == DCMIPP_STAT_EXT_AVER_MODE_NOEXT16    ) ||\
+                                              ((BINS) == DCMIPP_STAT_EXT_AVER_MODE_NOEXT32    ) ||\
+                                              ((BINS) == DCMIPP_STAT_EXT_AVER_MODE_NOEXT64    ))
+
+#define IS_DCMIPP_STAT_EXTRACTION_SOURCE(SOURCE) (((SOURCE) == DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_R) ||\
+                                                  ((SOURCE) == DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_G) ||\
+                                                  ((SOURCE) == DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_B) ||\
+                                                  ((SOURCE) == DCMIPP_STAT_EXT_SOURCE_PRE_BLKLVL_L) ||\
+                                                  ((SOURCE) == DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_R) ||\
+                                                  ((SOURCE) == DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_G) ||\
+                                                  ((SOURCE) == DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_B) ||\
+                                                  ((SOURCE) == DCMIPP_STAT_EXT_SOURCE_POST_DEMOS_L))
+
+#define IS_DCMIPP_STAT_EXTRACTION_MODE(MODE) (((MODE) == DCMIPP_STAT_EXT_MODE_AVERAGE) ||\
+                                              ((MODE) == DCMIPP_STAT_EXT_MODE_BINS))
+
+#define IS_DCMIPP_PIPE_STAT_EXTRACTION_START(START) ((START) <= 0xFFFU)
+#define IS_DCMIPP_PIPE_STAT_EXTRACTION_SIZE(SIZE) ((SIZE) <= 0xFFFU)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DCMIPP */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32N6xx_HAL_DCMIPP_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_def.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_def.h
new file mode 100644
index 000000000..95a53177d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_def.h
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32N6xx_HAL_DEF
+#define __STM32N6xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+#include <arm_cmse.h>
+#endif /* defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U) */
+
+#include "stm32n6xx.h"
+#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */
+#include <stddef.h>
+#include <math.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if !defined(UNUSED)
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)       \
+  do{                                                                      \
+    (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__);                   \
+    (__DMA_HANDLE__).Parent = (__HANDLE__);                                \
+  } while(0)
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
+#else
+#define __HAL_LOCK(__HANDLE__)               \
+  do{                                        \
+    if((__HANDLE__)->Lock == HAL_LOCKED)     \
+    {                                        \
+      return HAL_BUSY;                       \
+    }                                        \
+    else                                     \
+    {                                        \
+      (__HANDLE__)->Lock = HAL_LOCKED;       \
+    }                                        \
+  }while (0)
+
+#define __HAL_UNLOCK(__HANDLE__)             \
+  do{                                        \
+    (__HANDLE__)->Lock = HAL_UNLOCKED;       \
+  }while (0)
+#endif /* USE_RTOS */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif /* __packed */
+#elif defined (__GNUC__) /* GNU Compiler */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __ARMCC_VERSION */
+
+/* Macro to get buffer 32-bytes aligned (aligned to cache line width) */
+#define ALIGN_32BYTES(buf)  buf __attribute__((aligned(32)))
+
+/* Legacy macros to get variable 4-bytes aligned */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#ifndef __ALIGN_END
+#define __ALIGN_END  __attribute__((aligned(4)))
+#endif /* __ALIGN_END */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+/* ARM Compiler V6
+   ---------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined (__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC  __ramfunc
+
+#elif defined (__GNUC__)
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC  __attribute__((section(".RamFunc")))
+
+#endif /* __ARMCC_VERSION */
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__)
+/* ARM Compiler V6 & GNU Compiler */
+#define __NOINLINE __attribute__((noinline))
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler */
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif /* __ARMCC_VERSION || __GNUC__ */
+
+/* Non cacheable section and attribute
+  ------------------------------------
+  Create a non-cacheable section for DMA buffers and other hardware shared data.
+  The user can then use the __NON_CACHEABLE_SECTION_BEGIN and NON_CACHEABLE_SECTION_END to configure a non cacheable region
+  containing the data that was defined using the __NON_CACHEABLE attribute. */
+#if defined(__ICCARM__)
+#pragma section=".noncacheable"
+#define __NON_CACHEABLE_SECTION_BEGIN ((uint32_t) __sfb(".noncacheable"))
+#define __NON_CACHEABLE_SECTION_END   ((uint32_t) __sfe(".noncacheable"))
+#elif defined(__ARMCC_VERSION)
+extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Base;
+extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Length;
+#define __NON_CACHEABLE_SECTION_BEGIN Image$$RW_NONCACHEABLEBUFFER$$Base
+#define __NON_CACHEABLE_SECTION_END   (__NON_CACHEABLE_SECTION_BEGIN + Image$$RW_NONCACHEABLEBUFFER$$Length)
+#elif defined(__GNUC__)
+extern uint32_t __snoncacheable;
+extern uint32_t __enoncacheable;
+#define __NON_CACHEABLE_SECTION_BEGIN ((uint32_t) &__snoncacheable)
+#define __NON_CACHEABLE_SECTION_END   ((uint32_t) &__enoncacheable)
+#endif /* defined(__ICCARM__) */
+#define __NON_CACHEABLE __attribute__((section(".noncacheable")))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32N6xx_HAL_DEF */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma.h
new file mode 100644
index 000000000..5d56157c7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma.h
@@ -0,0 +1,1173 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32N6xx_HAL_DMA_H
+#define STM32N6xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief DMA Transfer Configuration Structure definition.
+  */
+typedef struct
+{
+  uint32_t Request;               /*!< Specifies the DMA channel request.
+                                       This parameter can be a value of @ref DMA_Request_Selection                    */
+
+  uint32_t BlkHWRequest;          /*!< Specifies the Block hardware request mode for DMA channel.
+                                       Block Hardware request feature can be used only with dedicated peripherals.
+                                       This parameter can be a value of @ref DMA_Block_Request                        */
+
+  uint32_t Direction;             /*!< Specifies the transfer direction for DMA channel.
+                                       This parameter can be a value of @ref DMA_Transfer_Direction                   */
+
+  uint32_t SrcInc;                /*!< Specifies the source increment mode for the DMA channel.
+                                       This parameter can be a value of @ref DMA_Source_Increment_Mode                */
+
+  uint32_t DestInc;               /*!< Specifies the destination increment mode for the DMA channel.
+                                       This parameter can be a value of @ref DMA_Destination_Increment_Mode           */
+
+  uint32_t SrcDataWidth;          /*!< Specifies the source data width for the DMA channel.
+                                       This parameter can be a value of @ref DMA_Source_Data_Width                    */
+
+  uint32_t DestDataWidth;         /*!< Specifies the destination data width for the DMA channel.
+                                       This parameter can be a value of @ref DMA_Destination_Data_Width               */
+
+  uint32_t Priority;              /*!< Specifies the priority level for the DMA channel.
+                                       This parameter can be a value of @ref DMA_Priority_Level                       */
+
+  uint32_t SrcBurstLength;        /*!< Specifies the source burst length (number of beats within a burst) for the DMA
+                                       channel.
+                                       This parameter can be a value between 1 and 64                                 */
+
+  uint32_t DestBurstLength;       /*!< Specifies the destination burst length (number of beats within a burst) for the
+                                       DMA channel.
+                                       This parameter can be a value between 1 and 64                                 */
+
+  uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports.
+                                       This parameter can be a combination of @ref DMA_Transfer_Allocated_Port        */
+
+  uint32_t TransferEventMode;     /*!< Specifies the transfer event mode for the DMA channel.
+                                       This parameter can be a value of @ref DMA_Transfer_Event_Mode                  */
+
+  uint32_t Mode;                  /*!< Specifies the transfer mode for the DMA channel.
+                                       This parameter can be a value of @ref DMA_Transfer_Mode                        */
+
+} DMA_InitTypeDef;
+
+/**
+  * @brief DMA Linked-List Configuration Structure Definition.
+  */
+typedef struct
+{
+  uint32_t Priority;          /*!< Specifies the priority level for the DMA channel.
+                                   This parameter can be a value of @ref DMA_Priority_Level        */
+
+  uint32_t LinkStepMode;      /*!< Specifies the link step mode for the DMA channel.
+                                   This parameter can be a value of @ref DMAEx_Link_Step_Mode      */
+
+  uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel.
+                                   This parameter can be a value of @ref DMAEx_Link_Allocated_Port */
+
+  uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel.
+                                   This parameter can be a value of @ref DMA_Transfer_Event_Mode   */
+
+  uint32_t LinkedListMode;    /*!< Specifies linked-list transfer mode for the DMA channel.
+                                   This parameter can be a value of @ref DMAEx_LinkedList_Mode     */
+
+} DMA_InitLinkedListTypeDef;
+
+/**
+  * @brief DMA CID filtering (isolation) configuration structure.
+  */
+typedef struct
+{
+  uint32_t CidFiltering;      /*!< Specified the CID filtering mode.
+                                   This parameter can be a value of @ref DMA_ISOLATION_MODE               */
+  uint32_t StaticCid;         /*!< Specified the static CID.
+                                   This parameter can be a value of @ref DMA_Channel_CID_Filtering_Static */
+} DMA_IsolationConfigTypeDef;
+
+/**
+  * @brief  HAL DMA State Enumeration Definition.
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET   = 0x00U, /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY   = 0x01U, /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY    = 0x02U, /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_ERROR   = 0x03U, /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT   = 0x04U, /*!< DMA Abort state                     */
+  HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state                   */
+
+} HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Level Complete Enumeration Definition.
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */
+  HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */
+
+} HAL_DMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL DMA Callbacks IDs Enumeration Definition.
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID     = 0x00U, /*!< Complete transfer callback ID      */
+  HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */
+  HAL_DMA_XFER_ERROR_CB_ID    = 0x02U, /*!< Error transfer callback ID         */
+  HAL_DMA_XFER_ABORT_CB_ID    = 0x03U, /*!< Abort transfer callback ID         */
+  HAL_DMA_XFER_SUSPEND_CB_ID  = 0x04U, /*!< Suspend transfer callback ID       */
+  HAL_DMA_XFER_ALL_CB_ID      = 0x05U  /*!< All callback ID                    */
+
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef       *Instance;                             /*!< Register the DMA channel base address   */
+
+  DMA_InitTypeDef           Init;                                  /*!< DMA channel init parameters             */
+
+  DMA_InitLinkedListTypeDef InitLinkedList;                        /*!< DMA channel linked-list init parameters */
+
+  HAL_LockTypeDef           Lock;                                  /*!< DMA locking object                      */
+
+  uint32_t                  Mode;                                  /*!< DMA transfer mode                       */
+
+  __IO HAL_DMA_StateTypeDef State;                                 /*!< DMA transfer state                      */
+
+  __IO uint32_t             ErrorCode;                             /*!< DMA error code                          */
+
+  void                      *Parent;                               /*!< Parent object state                     */
+
+  void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);     /*!< DMA transfer complete callback          */
+
+  void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback     */
+
+  void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);    /*!< DMA transfer error callback             */
+
+  void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);    /*!< DMA transfer Abort callback             */
+
+  void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma);  /*!< DMA transfer Suspend callback           */
+
+  struct __DMA_QListTypeDef  *LinkedListQueue;                     /*!< DMA linked-list queue                   */
+
+} DMA_HandleTypeDef;
+/**
+  * @}
+  */
+
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Codes DMA Error Codes
+  * @brief    DMA Error Codes
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE             (0x0000U) /*!< No error                      */
+#define HAL_DMA_ERROR_DTE              (0x0001U) /*!< Data transfer error           */
+#define HAL_DMA_ERROR_ULE              (0x0002U) /*!< Update linked-list item error */
+#define HAL_DMA_ERROR_USE              (0x0004U) /*!< User setting error            */
+#define HAL_DMA_ERROR_TO               (0x0008U) /*!< Trigger overrun error         */
+#define HAL_DMA_ERROR_TIMEOUT          (0x0010U) /*!< Timeout error                 */
+#define HAL_DMA_ERROR_NO_XFER          (0x0020U) /*!< No transfer ongoing error     */
+#define HAL_DMA_ERROR_BUSY             (0x0040U) /*!< Busy error                    */
+#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error        */
+#define HAL_DMA_ERROR_NOT_SUPPORTED    (0x0100U) /*!< Not supported mode            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition
+  * @brief    DMA Interrupt Enable Definition
+  * @{
+  */
+#define DMA_IT_TC   DMA_CCR_TCIE   /*!< Transfer complete interrupt             */
+#define DMA_IT_HT   DMA_CCR_HTIE   /*!< Half transfer complete interrupt        */
+#define DMA_IT_DTE  DMA_CCR_DTEIE  /*!< Data transfer error interrupt           */
+#define DMA_IT_ULE  DMA_CCR_ULEIE  /*!< Update linked-list item error interrupt */
+#define DMA_IT_USE  DMA_CCR_USEIE  /*!< User eetting error interrupt            */
+#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt          */
+#define DMA_IT_TO   DMA_CCR_TOIE   /*!< Trigger overrun interrupt               */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Flag_Definition DMA Flag Definition
+  * @brief    DMA Flag Definition
+  * @{
+  */
+#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag                          */
+#define DMA_FLAG_TC   DMA_CSR_TCF   /*!< Transfer complete flag             */
+#define DMA_FLAG_HT   DMA_CSR_HTF   /*!< Half transfer complete flag        */
+#define DMA_FLAG_DTE  DMA_CSR_DTEF  /*!< Data transfer error flag           */
+#define DMA_FLAG_ULE  DMA_CSR_ULEF  /*!< Update linked-list item error flag */
+#define DMA_FLAG_USE  DMA_CSR_USEF  /*!< User setting error flag            */
+#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag          */
+#define DMA_FLAG_TO   DMA_CSR_TOF   /*!< Trigger overrun flag               */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Request_Selection DMA Request Selection
+  * @brief    DMA Request Selection
+  * @{
+  */
+/* HPDMA1 requests */
+#define HPDMA1_REQUEST_JPEG_RX        0U       /*!< HPDMA1 HW request is JPEG_RX        */
+#define HPDMA1_REQUEST_JPEG_TX        1U       /*!< HPDMA1 HW request is JPEG_TX        */
+#define HPDMA1_REQUEST_XSPI1          2U       /*!< HPDMA1 HW request is XSPI1          */
+#define HPDMA1_REQUEST_XSPI2          3U       /*!< HPDMA1 HW request is XSPI2          */
+#define HPDMA1_REQUEST_XSPI3          4U       /*!< HPDMA1 HW request is XSPI3          */
+#define HPDMA1_REQUEST_FMC2_TXRX      5U       /*!< HPDMA1 HW request is FMC2_TXRX      */
+#define HPDMA1_REQUEST_FMC2_BCH       6U       /*!< HPDMA1 HW request is FMC2_BCH       */
+#define HPDMA1_REQUEST_ADC1           7U       /*!< HPDMA1 HW request is ADC1           */
+#define HPDMA1_REQUEST_ADC2           8U       /*!< HPDMA1 HW request is ADC2           */
+#define HPDMA1_REQUEST_CRYP_IN        9U       /*!< HPDMA1 HW request is CRYP_IN        */
+#define HPDMA1_REQUEST_CRYP_OUT       10U      /*!< HPDMA1 HW request is CRYP_OUT       */
+#define HPDMA1_REQUEST_SAES_OUT       11U      /*!< HPDMA1 HW request is SAES_OUT       */
+#define HPDMA1_REQUEST_SAES_IN        12U      /*!< HPDMA1 HW request is SAES_IN        */
+#define HPDMA1_REQUEST_HASH_IN        13U      /*!< HPDMA1 HW request is HASH_IN        */
+
+#define HPDMA1_REQUEST_TIM1_CH1       14U      /*!< HPDMA1 HW request is TIM1_CH1       */
+#define HPDMA1_REQUEST_TIM1_CH2       15U      /*!< HPDMA1 HW request is TIM1_CH2       */
+#define HPDMA1_REQUEST_TIM1_CH3       16U      /*!< HPDMA1 HW request is TIM1_CH3       */
+#define HPDMA1_REQUEST_TIM1_CH4       17U      /*!< HPDMA1 HW request is TIM1_CH4       */
+#define HPDMA1_REQUEST_TIM1_UP        18U      /*!< HPDMA1 HW request is TIM1_UP        */
+#define HPDMA1_REQUEST_TIM1_TRIG      19U      /*!< HPDMA1 HW request is TIM1_TRIG      */
+#define HPDMA1_REQUEST_TIM1_COM       20U      /*!< HPDMA1 HW request is TIM1_COM       */
+
+#define HPDMA1_REQUEST_TIM2_CH1       21U      /*!< HPDMA1 HW request is TIM2_CH1       */
+#define HPDMA1_REQUEST_TIM2_CH2       22U      /*!< HPDMA1 HW request is TIM2_CH2       */
+#define HPDMA1_REQUEST_TIM2_CH3       23U      /*!< HPDMA1 HW request is TIM2_CH3       */
+#define HPDMA1_REQUEST_TIM2_CH4       24U      /*!< HPDMA1 HW request is TIM2_CH4       */
+#define HPDMA1_REQUEST_TIM2_UP        25U      /*!< HPDMA1 HW request is TIM2_UP        */
+#define HPDMA1_REQUEST_TIM2_TRIG      26U      /*!< HPDMA1 HW request is TIM2_TRIG      */
+
+#define HPDMA1_REQUEST_TIM3_CH1       27U      /*!< HPDMA1 HW request is TIM3_CH1       */
+#define HPDMA1_REQUEST_TIM3_CH2       28U      /*!< HPDMA1 HW request is TIM3_CH2       */
+#define HPDMA1_REQUEST_TIM3_CH3       29U      /*!< HPDMA1 HW request is TIM3_CH3       */
+#define HPDMA1_REQUEST_TIM3_CH4       30U      /*!< HPDMA1 HW request is TIM3_CH4       */
+#define HPDMA1_REQUEST_TIM3_UP        31U      /*!< HPDMA1 HW request is TIM3_UP        */
+#define HPDMA1_REQUEST_TIM3_TRIG      32U      /*!< HPDMA1 HW request is TIM3_TRIG      */
+
+#define HPDMA1_REQUEST_TIM4_CH1       33U      /*!< HPDMA1 HW request is TIM4_CH1       */
+#define HPDMA1_REQUEST_TIM4_CH2       34U      /*!< HPDMA1 HW request is TIM4_CH2       */
+#define HPDMA1_REQUEST_TIM4_CH3       35U      /*!< HPDMA1 HW request is TIM4_CH3       */
+#define HPDMA1_REQUEST_TIM4_CH4       36U      /*!< HPDMA1 HW request is TIM4_CH4       */
+#define HPDMA1_REQUEST_TIM4_UP        37U      /*!< HPDMA1 HW request is TIM4_UP        */
+#define HPDMA1_REQUEST_TIM4_TRIG      38U      /*!< HPDMA1 HW request is TIM4_TRIG      */
+
+#define HPDMA1_REQUEST_TIM5_CH1       39U      /*!< HPDMA1 HW request is TIM5_CH1       */
+#define HPDMA1_REQUEST_TIM5_CH2       40U      /*!< HPDMA1 HW request is TIM5_CH2       */
+#define HPDMA1_REQUEST_TIM5_CH3       41U      /*!< HPDMA1 HW request is TIM5_CH3       */
+#define HPDMA1_REQUEST_TIM5_CH4       42U      /*!< HPDMA1 HW request is TIM5_CH4       */
+#define HPDMA1_REQUEST_TIM5_UP        43U      /*!< HPDMA1 HW request is TIM5_UP        */
+#define HPDMA1_REQUEST_TIM5_TRIG      44U      /*!< HPDMA1 HW request is TIM5_TRIG      */
+
+#define HPDMA1_REQUEST_TIM6_UP        45U      /*!< HPDMA1 HW request is TIM6_UP        */
+#define HPDMA1_REQUEST_TIM7_UP        46U      /*!< HPDMA1 HW request is TIM7_UP        */
+
+#define HPDMA1_REQUEST_TIM8_CH1       47U      /*!< HPDMA1 HW request is TIM8_CH1       */
+#define HPDMA1_REQUEST_TIM8_CH2       48U      /*!< HPDMA1 HW request is TIM8_CH2       */
+#define HPDMA1_REQUEST_TIM8_CH3       49U      /*!< HPDMA1 HW request is TIM8_CH3       */
+#define HPDMA1_REQUEST_TIM8_CH4       50U      /*!< HPDMA1 HW request is TIM8_CH4       */
+#define HPDMA1_REQUEST_TIM8_UP        51U      /*!< HPDMA1 HW request is TIM8_UP        */
+#define HPDMA1_REQUEST_TIM8_TRIG      52U      /*!< HPDMA1 HW request is TIM8_TRIG      */
+#define HPDMA1_REQUEST_TIM8_COM       53U      /*!< HPDMA1 HW request is TIM8_COM       */
+
+/* reserved                           54U                                               */
+/* reserved                           55U                                               */
+
+#define HPDMA1_REQUEST_TIM15_CH1      56U      /*!< HPDMA1 HW request is TIM15_CH1      */
+#define HPDMA1_REQUEST_TIM15_CH2      57U      /*!< HPDMA1 HW request is TIM15_CH2      */
+#define HPDMA1_REQUEST_TIM15_UP       58U      /*!< HPDMA1 HW request is TIM15_UP       */
+#define HPDMA1_REQUEST_TIM15_TRIG     59U      /*!< HPDMA1 HW request is TIM15_TRIG     */
+#define HPDMA1_REQUEST_TIM15_COM      60U      /*!< HPDMA1 HW request is TIM15_COM      */
+
+#define HPDMA1_REQUEST_TIM16_CH1      61U      /*!< HPDMA1 HW request is TIM16_CH1      */
+#define HPDMA1_REQUEST_TIM16_UP       62U      /*!< HPDMA1 HW request is TIM16_UP       */
+#define HPDMA1_REQUEST_TIM16_COM      63U      /*!< HPDMA1 HW request is TIM16_COM      */
+
+#define HPDMA1_REQUEST_TIM17_CH1      64U      /*!< HPDMA1 HW request is TIM17_CH1      */
+#define HPDMA1_REQUEST_TIM17_UP       65U      /*!< HPDMA1 HW request is TIM17_UP       */
+#define HPDMA1_REQUEST_TIM17_COM      66U      /*!< HPDMA1 HW request is TIM17_COM      */
+
+#define HPDMA1_REQUEST_TIM18_CH1      67U      /*!< HPDMA1 HW request is TIM18_CH1      */
+#define HPDMA1_REQUEST_TIM18_UP       68U      /*!< HPDMA1 HW request is TIM18_UP       */
+#define HPDMA1_REQUEST_TIM18_COM      69U      /*!< HPDMA1 HW request is TIM18_COM      */
+
+#define HPDMA1_REQUEST_LPTIM1_IC1     70U      /*!< HPDMA1 HW request is LPTIM1_IC1     */
+#define HPDMA1_REQUEST_LPTIM1_IC2     71U      /*!< HPDMA1 HW request is LPTIM1_IC2     */
+#define HPDMA1_REQUEST_LPTIM1_UE      72U      /*!< HPDMA1 HW request is LPTIM1_UE      */
+#define HPDMA1_REQUEST_LPTIM2_IC1     73U      /*!< HPDMA1 HW request is LPTIM2_IC1     */
+#define HPDMA1_REQUEST_LPTIM2_IC2     74U      /*!< HPDMA1 HW request is LPTIM2_IC2     */
+#define HPDMA1_REQUEST_LPTIM2_UE      75U      /*!< HPDMA1 HW request is LPTIM2_UE      */
+#define HPDMA1_REQUEST_LPTIM3_IC1     76U      /*!< HPDMA1 HW request is LPTIM3_IC1     */
+#define HPDMA1_REQUEST_LPTIM3_IC2     77U      /*!< HPDMA1 HW request is LPTIM3_IC2     */
+#define HPDMA1_REQUEST_LPTIM3_UE      78U      /*!< HPDMA1 HW request is LPTIM3_UE      */
+
+#define HPDMA1_REQUEST_SPI1_RX        79U      /*!< HPDMA1 HW request is SPI1_RX        */
+#define HPDMA1_REQUEST_SPI1_TX        80U      /*!< HPDMA1 HW request is SPI1_TX        */
+#define HPDMA1_REQUEST_SPI2_RX        81U      /*!< HPDMA1 HW request is SPI2_RX        */
+#define HPDMA1_REQUEST_SPI2_TX        82U      /*!< HPDMA1 HW request is SPI2_TX        */
+#define HPDMA1_REQUEST_SPI3_RX        83U      /*!< HPDMA1 HW request is SPI3_RX        */
+#define HPDMA1_REQUEST_SPI3_TX        84U      /*!< HPDMA1 HW request is SPI3_TX        */
+#define HPDMA1_REQUEST_SPI4_RX        85U      /*!< HPDMA1 HW request is SPI4_RX        */
+#define HPDMA1_REQUEST_SPI4_TX        86U      /*!< HPDMA1 HW request is SPI4_TX        */
+#define HPDMA1_REQUEST_SPI5_RX        87U      /*!< HPDMA1 HW request is SPI5_RX        */
+#define HPDMA1_REQUEST_SPI5_TX        88U      /*!< HPDMA1 HW request is SPI5_TX        */
+#define HPDMA1_REQUEST_SPI6_RX        89U      /*!< HPDMA1 HW request is SPI6_RX        */
+#define HPDMA1_REQUEST_SPI6_TX        90U      /*!< HPDMA1 HW request is SPI6_TX        */
+
+#define HPDMA1_REQUEST_SAI1_A         91U      /*!< HPDMA1 HW request is SAI1_A         */
+#define HPDMA1_REQUEST_SAI1_B         92U      /*!< HPDMA1 HW request is SAI1_B         */
+#define HPDMA1_REQUEST_SAI2_A         93U      /*!< HPDMA1 HW request is SAI2_A         */
+#define HPDMA1_REQUEST_SAI2_B         94U      /*!< HPDMA1 HW request is SAI2_B         */
+
+#define HPDMA1_REQUEST_I2C1_RX        95U      /*!< HPDMA1 HW request is I2C1_RX        */
+#define HPDMA1_REQUEST_I2C1_TX        96U      /*!< HPDMA1 HW request is I2C1_TX        */
+#define HPDMA1_REQUEST_I2C2_RX        97U      /*!< HPDMA1 HW request is I2C2_RX        */
+#define HPDMA1_REQUEST_I2C2_TX        98U      /*!< HPDMA1 HW request is I2C2_TX        */
+#define HPDMA1_REQUEST_I2C3_RX        99U      /*!< HPDMA1 HW request is I2C3_RX        */
+#define HPDMA1_REQUEST_I2C3_TX        100U     /*!< HPDMA1 HW request is I2C3_TX        */
+
+#define HPDMA1_REQUEST_I2C4_RX        101U     /*!< HPDMA1 HW request is I2C4_RX        */
+#define HPDMA1_REQUEST_I2C4_TX        102U     /*!< HPDMA1 HW request is I2C4_TX        */
+
+#define HPDMA1_REQUEST_I3C1_RX        103U     /*!< HPDMA1 HW request is I3C1_RX        */
+#define HPDMA1_REQUEST_I3C1_TX        104U     /*!< HPDMA1 HW request is I3C1_TX        */
+#define HPDMA1_REQUEST_I3C2_RX        105U     /*!< HPDMA1 HW request is I3C2_RX        */
+#define HPDMA1_REQUEST_I3C2_TX        106U     /*!< HPDMA1 HW request is I3C2_TX        */
+
+#define HPDMA1_REQUEST_USART1_RX      107U     /*!< HPDMA1 HW request is USART1_RX      */
+#define HPDMA1_REQUEST_USART1_TX      108U     /*!< HPDMA1 HW request is USART1_TX      */
+#define HPDMA1_REQUEST_USART2_RX      109U     /*!< HPDMA1 HW request is USART2_RX      */
+#define HPDMA1_REQUEST_USART2_TX      110U     /*!< HPDMA1 HW request is USART2_TX      */
+#define HPDMA1_REQUEST_USART3_RX      111U     /*!< HPDMA1 HW request is USART3_RX      */
+#define HPDMA1_REQUEST_USART3_TX      112U     /*!< HPDMA1 HW request is USART3_TX      */
+#define HPDMA1_REQUEST_UART4_RX       113U     /*!< HPDMA1 HW request is UART4_RX       */
+#define HPDMA1_REQUEST_UART4_TX       114U     /*!< HPDMA1 HW request is UART4_TX       */
+#define HPDMA1_REQUEST_UART5_RX       115U     /*!< HPDMA1 HW request is UART5_RX       */
+#define HPDMA1_REQUEST_UART5_TX       116U     /*!< HPDMA1 HW request is UART5_TX       */
+#define HPDMA1_REQUEST_USART6_RX      117U     /*!< HPDMA1 HW request is USART6_RX      */
+#define HPDMA1_REQUEST_USART6_TX      118U     /*!< HPDMA1 HW request is USART6_TX      */
+#define HPDMA1_REQUEST_UART7_RX       119U     /*!< HPDMA1 HW request is UART7_RX       */
+#define HPDMA1_REQUEST_UART7_TX       120U     /*!< HPDMA1 HW request is UART7_TX       */
+#define HPDMA1_REQUEST_UART8_RX       121U     /*!< HPDMA1 HW request is UART8_RX       */
+#define HPDMA1_REQUEST_UART8_TX       122U     /*!< HPDMA1 HW request is UART8_TX       */
+#define HPDMA1_REQUEST_UART9_RX       123U     /*!< HPDMA1 HW request is UART9_RX       */
+#define HPDMA1_REQUEST_UART9_TX       124U     /*!< HPDMA1 HW request is UART9_TX       */
+#define HPDMA1_REQUEST_USART10_RX     125U     /*!< HPDMA1 HW request is USART10_RX     */
+#define HPDMA1_REQUEST_USART10_TX     126U     /*!< HPDMA1 HW request is USART10_TX     */
+
+#define HPDMA1_REQUEST_LPUART1_RX     127U     /*!< HPDMA1 HW request is LPUART1_RX     */
+#define HPDMA1_REQUEST_LPUART1_TX     128U     /*!< HPDMA1 HW request is LPUART1_TX     */
+
+#define HPDMA1_REQUEST_SPDIFRX_CS     129U     /*!< HPDMA1 HW request is SPDIFRX_CS     */
+#define HPDMA1_REQUEST_SPDIFRX_DT     130U     /*!< HPDMA1 HW request is SPDIFRX_DT     */
+
+#define HPDMA1_REQUEST_ADF1_FLT0      131U     /*!< HPDMA1 HW request is ADF1_FLT0      */
+
+#define HPDMA1_REQUEST_MDF1_FLT0      132U     /*!< HPDMA1 HW request is MDF1_FLT0      */
+#define HPDMA1_REQUEST_MDF1_FLT1      133U     /*!< HPDMA1 HW request is MDF1_FLT1      */
+#define HPDMA1_REQUEST_MDF1_FLT2      134U     /*!< HPDMA1 HW request is MDF1_FLT2      */
+#define HPDMA1_REQUEST_MDF1_FLT3      135U     /*!< HPDMA1 HW request is MDF1_FLT3      */
+#define HPDMA1_REQUEST_MDF1_FLT4      136U     /*!< HPDMA1 HW request is MDF1_FLT4      */
+#define HPDMA1_REQUEST_MDF1_FLT5      137U     /*!< HPDMA1 HW request is MDF1_FLT5      */
+
+#define HPDMA1_REQUEST_UCPD1_TX       138U     /*!< HPDMA1 HW request is UCPD1_TX       */
+#define HPDMA1_REQUEST_UCPD1_RX       139U     /*!< HPDMA1 HW request is UCPD1_RX       */
+
+#define HPDMA1_REQUEST_DCMI_PSSI      140U     /*!< HPDMA1 HW request is DCMI_PSSI      */
+
+#define HPDMA1_REQUEST_I3C1_TC        141U     /*!< HPDMA1 HW request is I3C1_TC        */
+#define HPDMA1_REQUEST_I3C1_RS        142U     /*!< HPDMA1 HW request is I3C1_RS        */
+
+#define HPDMA1_REQUEST_I3C2_TC        143U     /*!< HPDMA1 HW request is I3C2_TC        */
+#define HPDMA1_REQUEST_I3C2_RS        144U     /*!< HPDMA1 HW request is I3C2_RS        */
+
+/* GPDMA1 requests */
+#define GPDMA1_REQUEST_JPEG_RX        0U       /*!< GPDMA1 HW request is JPEG_DMA_RX    */
+#define GPDMA1_REQUEST_JPEG_TX        1U       /*!< GPDMA1 HW request is JPEG_DMA_TX    */
+#define GPDMA1_REQUEST_XSPI1          2U       /*!< GPDMA1 HW request is XSPI1          */
+#define GPDMA1_REQUEST_XSPI2          3U       /*!< GPDMA1 HW request is XSPI2          */
+#define GPDMA1_REQUEST_XSPI3          4U       /*!< GPDMA1 HW request is XSPI3          */
+#define GPDMA1_REQUEST_FMC2_TXRX      5U       /*!< GPDMA1 HW request is FMC2_TXRX      */
+#define GPDMA1_REQUEST_FMC2_BCH       6U       /*!< GPDMA1 HW request is FMC2_BCH       */
+#define GPDMA1_REQUEST_ADC1           7U       /*!< GPDMA1 HW request is ADC1           */
+#define GPDMA1_REQUEST_ADC2           8U       /*!< GPDMA1 HW request is ADC2           */
+#define GPDMA1_REQUEST_CRYP_IN        9U       /*!< GPDMA1 HW request is CRYP_IN        */
+#define GPDMA1_REQUEST_CRYP_OUT       10U      /*!< GPDMA1 HW request is CRYP_OUT       */
+#define GPDMA1_REQUEST_SAES_OUT       11U      /*!< GPDMA1 HW request is SAES_OUT       */
+#define GPDMA1_REQUEST_SAES_IN        12U      /*!< GPDMA1 HW request is SAES_IN        */
+#define GPDMA1_REQUEST_HASH_IN        13U      /*!< GPDMA1 HW request is HASH_IN        */
+
+#define GPDMA1_REQUEST_TIM1_CH1       14U      /*!< GPDMA1 HW request is TIM1_CH1       */
+#define GPDMA1_REQUEST_TIM1_CH2       15U      /*!< GPDMA1 HW request is TIM1_CH2       */
+#define GPDMA1_REQUEST_TIM1_CH3       16U      /*!< GPDMA1 HW request is TIM1_CH3       */
+#define GPDMA1_REQUEST_TIM1_CH4       17U      /*!< GPDMA1 HW request is TIM1_CH4       */
+#define GPDMA1_REQUEST_TIM1_UP        18U      /*!< GPDMA1 HW request is TIM1_UP        */
+#define GPDMA1_REQUEST_TIM1_TRIG      19U      /*!< GPDMA1 HW request is TIM1_TRIG      */
+#define GPDMA1_REQUEST_TIM1_COM       20U      /*!< GPDMA1 HW request is TIM1_COM       */
+
+#define GPDMA1_REQUEST_TIM2_CH1       21U      /*!< GPDMA1 HW request is TIM2_CH1       */
+#define GPDMA1_REQUEST_TIM2_CH2       22U      /*!< GPDMA1 HW request is TIM2_CH2       */
+#define GPDMA1_REQUEST_TIM2_CH3       23U      /*!< GPDMA1 HW request is TIM2_CH3       */
+#define GPDMA1_REQUEST_TIM2_CH4       24U      /*!< GPDMA1 HW request is TIM2_CH4       */
+#define GPDMA1_REQUEST_TIM2_UP        25U      /*!< GPDMA1 HW request is TIM2_UP        */
+#define GPDMA1_REQUEST_TIM2_TRIG      26U      /*!< GPDMA1 HW request is TIM2_TRIG      */
+
+#define GPDMA1_REQUEST_TIM3_CH1       27U      /*!< GPDMA1 HW request is TIM3_CH1       */
+#define GPDMA1_REQUEST_TIM3_CH2       28U      /*!< GPDMA1 HW request is TIM3_CH2       */
+#define GPDMA1_REQUEST_TIM3_CH3       29U      /*!< GPDMA1 HW request is TIM3_CH3       */
+#define GPDMA1_REQUEST_TIM3_CH4       30U      /*!< GPDMA1 HW request is TIM3_CH4       */
+#define GPDMA1_REQUEST_TIM3_UP        31U      /*!< GPDMA1 HW request is TIM3_UP        */
+#define GPDMA1_REQUEST_TIM3_TRIG      32U      /*!< GPDMA1 HW request is TIM3_TRIG      */
+
+#define GPDMA1_REQUEST_TIM4_CH1       33U      /*!< GPDMA1 HW request is TIM4_CH1       */
+#define GPDMA1_REQUEST_TIM4_CH2       34U      /*!< GPDMA1 HW request is TIM4_CH2       */
+#define GPDMA1_REQUEST_TIM4_CH3       35U      /*!< GPDMA1 HW request is TIM4_CH3       */
+#define GPDMA1_REQUEST_TIM4_CH4       36U      /*!< GPDMA1 HW request is TIM4_CH4       */
+#define GPDMA1_REQUEST_TIM4_UP        37U      /*!< GPDMA1 HW request is TIM4_UP        */
+#define GPDMA1_REQUEST_TIM4_TRIG      38U      /*!< GPDMA1 HW request is TIM4_TRIG      */
+
+#define GPDMA1_REQUEST_TIM5_CH1       39U      /*!< GPDMA1 HW request is TIM5_CH1       */
+#define GPDMA1_REQUEST_TIM5_CH2       40U      /*!< GPDMA1 HW request is TIM5_CH2       */
+#define GPDMA1_REQUEST_TIM5_CH3       41U      /*!< GPDMA1 HW request is TIM5_CH3       */
+#define GPDMA1_REQUEST_TIM5_CH4       42U      /*!< GPDMA1 HW request is TIM5_CH4       */
+#define GPDMA1_REQUEST_TIM5_UP        43U      /*!< GPDMA1 HW request is TIM5_UP        */
+#define GPDMA1_REQUEST_TIM5_TRIG      44U      /*!< GPDMA1 HW request is TIM5_TRIG      */
+
+#define GPDMA1_REQUEST_TIM6_UP        45U      /*!< GPDMA1 HW request is TIM6_UP        */
+#define GPDMA1_REQUEST_TIM7_UP        46U      /*!< GPDMA1 HW request is TIM6_UP        */
+
+#define GPDMA1_REQUEST_TIM8_CH1       47U      /*!< GPDMA1 HW request is TIM8_CH1       */
+#define GPDMA1_REQUEST_TIM8_CH2       48U      /*!< GPDMA1 HW request is TIM8_CH2       */
+#define GPDMA1_REQUEST_TIM8_CH3       49U      /*!< GPDMA1 HW request is TIM8_CH3       */
+#define GPDMA1_REQUEST_TIM8_CH4       50U      /*!< GPDMA1 HW request is TIM8_CH4       */
+#define GPDMA1_REQUEST_TIM8_UP        51U      /*!< GPDMA1 HW request is TIM8_UP        */
+#define GPDMA1_REQUEST_TIM8_TRIG      52U      /*!< GPDMA1 HW request is TIM8_TRIG      */
+#define GPDMA1_REQUEST_TIM8_COM       53U      /*!< GPDMA1 HW request is TIM8_COM       */
+
+/* reserved                           54U                                               */
+/* reserved                           55U                                               */
+
+#define GPDMA1_REQUEST_TIM15_CH1      56U      /*!< GPDMA1 HW request is TIM15_CH1      */
+#define GPDMA1_REQUEST_TIM15_CH2      57U      /*!< GPDMA1 HW request is TIM15_CH2      */
+#define GPDMA1_REQUEST_TIM15_UP       58U      /*!< GPDMA1 HW request is TIM15_UP       */
+#define GPDMA1_REQUEST_TIM15_TRIG     59U      /*!< GPDMA1 HW request is TIM15_TRIG     */
+#define GPDMA1_REQUEST_TIM15_COM      60U      /*!< GPDMA1 HW request is TIM15_COM      */
+
+#define GPDMA1_REQUEST_TIM16_CH1      61U      /*!< GPDMA1 HW request is TIM16_CH1      */
+#define GPDMA1_REQUEST_TIM16_UP       62U      /*!< GPDMA1 HW request is TIM16_UP       */
+#define GPDMA1_REQUEST_TIM16_COM      63U      /*!< GPDMA1 HW request is TIM16_COM      */
+
+#define GPDMA1_REQUEST_TIM17_CH1      64U      /*!< GPDMA1 HW request is TIM17_CH1      */
+#define GPDMA1_REQUEST_TIM17_UP       65U      /*!< GPDMA1 HW request is TIM17_UP       */
+#define GPDMA1_REQUEST_TIM17_COM      66U      /*!< GPDMA1 HW request is TIM17_COM      */
+
+#define GPDMA1_REQUEST_TIM18_CH1      67U      /*!< GPDMA1 HW request is TIM18_CH1      */
+#define GPDMA1_REQUEST_TIM18_UP       68U      /*!< GPDMA1 HW request is TIM18_UP       */
+#define GPDMA1_REQUEST_TIM18_COM      69U      /*!< GPDMA1 HW request is TIM18_COM      */
+
+#define GPDMA1_REQUEST_LPTIM1_IC1     70U      /*!< GPDMA1 HW request is LPTIM1_IC1     */
+#define GPDMA1_REQUEST_LPTIM1_IC2     71U      /*!< GPDMA1 HW request is LPTIM1_IC2     */
+#define GPDMA1_REQUEST_LPTIM1_UE      72U      /*!< GPDMA1 HW request is LPTIM1_UE      */
+#define GPDMA1_REQUEST_LPTIM2_IC1     73U      /*!< GPDMA1 HW request is LPTIM2_IC1     */
+#define GPDMA1_REQUEST_LPTIM2_IC2     74U      /*!< GPDMA1 HW request is LPTIM2_IC2     */
+#define GPDMA1_REQUEST_LPTIM2_UE      75U      /*!< GPDMA1 HW request is LPTIM2_UE      */
+#define GPDMA1_REQUEST_LPTIM3_IC1     76U      /*!< GPDMA1 HW request is LPTIM3_IC1     */
+#define GPDMA1_REQUEST_LPTIM3_IC2     77U      /*!< GPDMA1 HW request is LPTIM3_IC2     */
+#define GPDMA1_REQUEST_LPTIM3_UE      78U      /*!< GPDMA1 HW request is LPTIM3_UE      */
+
+#define GPDMA1_REQUEST_SPI1_RX        79U      /*!< GPDMA1 HW request is SPI1_RX        */
+#define GPDMA1_REQUEST_SPI1_TX        80U      /*!< GPDMA1 HW request is SPI1_TX        */
+#define GPDMA1_REQUEST_SPI2_RX        81U      /*!< GPDMA1 HW request is SPI2_RX        */
+#define GPDMA1_REQUEST_SPI2_TX        82U      /*!< GPDMA1 HW request is SPI2_TX        */
+#define GPDMA1_REQUEST_SPI3_RX        83U      /*!< GPDMA1 HW request is SPI3_RX        */
+#define GPDMA1_REQUEST_SPI3_TX        84U      /*!< GPDMA1 HW request is SPI3_TX        */
+#define GPDMA1_REQUEST_SPI4_RX        85U      /*!< GPDMA1 HW request is SPI4_RX        */
+#define GPDMA1_REQUEST_SPI4_TX        86U      /*!< GPDMA1 HW request is SPI4_TX        */
+#define GPDMA1_REQUEST_SPI5_RX        87U      /*!< GPDMA1 HW request is SPI5_RX        */
+#define GPDMA1_REQUEST_SPI5_TX        88U      /*!< GPDMA1 HW request is SPI5_TX        */
+#define GPDMA1_REQUEST_SPI6_RX        89U      /*!< GPDMA1 HW request is SPI6_RX        */
+#define GPDMA1_REQUEST_SPI6_TX        90U      /*!< GPDMA1 HW request is SPI6_TX        */
+
+#define GPDMA1_REQUEST_SAI1_A         91U      /*!< GPDMA1 HW request is SAI1_A         */
+#define GPDMA1_REQUEST_SAI1_B         92U      /*!< GPDMA1 HW request is SAI1_B         */
+#define GPDMA1_REQUEST_SAI2_A         93U      /*!< GPDMA1 HW request is SAI2_A         */
+#define GPDMA1_REQUEST_SAI2_B         94U      /*!< GPDMA1 HW request is SAI2_B         */
+
+#define GPDMA1_REQUEST_I2C1_RX        95U      /*!< GPDMA1 HW request is I2C1_RX        */
+#define GPDMA1_REQUEST_I2C1_TX        96U      /*!< GPDMA1 HW request is I2C1_TX        */
+#define GPDMA1_REQUEST_I2C2_RX        97U      /*!< GPDMA1 HW request is I2C2_RX        */
+#define GPDMA1_REQUEST_I2C2_TX        98U      /*!< GPDMA1 HW request is I2C2_TX        */
+#define GPDMA1_REQUEST_I2C3_RX        99U      /*!< GPDMA1 HW request is I2C3_RX        */
+#define GPDMA1_REQUEST_I2C3_TX        100U     /*!< GPDMA1 HW request is I2C3_TX        */
+
+#define GPDMA1_REQUEST_I2C4_RX        101U     /*!< GPDMA1 HW request is I2C4_RX        */
+#define GPDMA1_REQUEST_I2C4_TX        102U     /*!< GPDMA1 HW request is I2C4_TX        */
+
+#define GPDMA1_REQUEST_I3C1_RX        103U     /*!< GPDMA1 HW request is I3C1_RX        */
+#define GPDMA1_REQUEST_I3C1_TX        104U     /*!< GPDMA1 HW request is I3C1_TX        */
+#define GPDMA1_REQUEST_I3C2_RX        105U     /*!< GPDMA1 HW request is I3C2_RX        */
+#define GPDMA1_REQUEST_I3C2_TX        106U     /*!< GPDMA1 HW request is I3C2_TX        */
+
+#define GPDMA1_REQUEST_USART1_RX      107U     /*!< GPDMA1 HW request is USART1_RX      */
+#define GPDMA1_REQUEST_USART1_TX      108U     /*!< GPDMA1 HW request is USART1_TX      */
+#define GPDMA1_REQUEST_USART2_RX      109U     /*!< GPDMA1 HW request is USART2_RX      */
+#define GPDMA1_REQUEST_USART2_TX      110U     /*!< GPDMA1 HW request is USART2_TX      */
+#define GPDMA1_REQUEST_USART3_RX      111U     /*!< GPDMA1 HW request is USART3_RX      */
+#define GPDMA1_REQUEST_USART3_TX      112U     /*!< GPDMA1 HW request is USART3_TX      */
+#define GPDMA1_REQUEST_UART4_RX       113U     /*!< GPDMA1 HW request is UART4_RX       */
+#define GPDMA1_REQUEST_UART4_TX       114U     /*!< GPDMA1 HW request is UART4_TX       */
+#define GPDMA1_REQUEST_UART5_RX       115U     /*!< GPDMA1 HW request is UART5_RX       */
+#define GPDMA1_REQUEST_UART5_TX       116U     /*!< GPDMA1 HW request is UART5_TX       */
+#define GPDMA1_REQUEST_USART6_RX      117U     /*!< GPDMA1 HW request is USART6_RX      */
+#define GPDMA1_REQUEST_USART6_TX      118U     /*!< GPDMA1 HW request is USART6_TX      */
+#define GPDMA1_REQUEST_UART7_RX       119U     /*!< GPDMA1 HW request is UART7_RX       */
+#define GPDMA1_REQUEST_UART7_TX       120U     /*!< GPDMA1 HW request is UART7_TX       */
+#define GPDMA1_REQUEST_UART8_RX       121U     /*!< GPDMA1 HW request is UART8_RX       */
+#define GPDMA1_REQUEST_UART8_TX       122U     /*!< GPDMA1 HW request is UART8_TX       */
+#define GPDMA1_REQUEST_UART9_RX       123U     /*!< GPDMA1 HW request is UART9_RX       */
+#define GPDMA1_REQUEST_UART9_TX       124U     /*!< GPDMA1 HW request is UART9_TX       */
+#define GPDMA1_REQUEST_USART10_RX     125U     /*!< GPDMA1 HW request is USART10_RX     */
+#define GPDMA1_REQUEST_USART10_TX     126U     /*!< GPDMA1 HW request is USART10_TX     */
+
+#define GPDMA1_REQUEST_LPUART1_RX     127U     /*!< GPDMA1 HW request is LPUART1_RX     */
+#define GPDMA1_REQUEST_LPUART1_TX     128U     /*!< GPDMA1 HW request is LPUART1_TX     */
+
+#define GPDMA1_REQUEST_SPDIFRX_CS     129U     /*!< GPDMA1 HW request is SPDIFRX_CS     */
+#define GPDMA1_REQUEST_SPDIFRX_DT     130U     /*!< GPDMA1 HW request is SPDIFRX_DT     */
+
+#define GPDMA1_REQUEST_ADF1_FLT0      131U     /*!< GPDMA1 HW request is ADF1_FLT0      */
+
+#define GPDMA1_REQUEST_MDF1_FLT0      132U     /*!< GPDMA1 HW request is MDF1_FLT0      */
+#define GPDMA1_REQUEST_MDF1_FLT1      133U     /*!< GPDMA1 HW request is MDF1_FLT1      */
+#define GPDMA1_REQUEST_MDF1_FLT2      134U     /*!< GPDMA1 HW request is MDF1_FLT2      */
+#define GPDMA1_REQUEST_MDF1_FLT3      135U     /*!< GPDMA1 HW request is MDF1_FLT3      */
+#define GPDMA1_REQUEST_MDF1_FLT4      136U     /*!< GPDMA1 HW request is MDF1_FLT4      */
+#define GPDMA1_REQUEST_MDF1_FLT5      137U     /*!< GPDMA1 HW request is MDF1_FLT5      */
+
+#define GPDMA1_REQUEST_UCPD1_TX       138U     /*!< GPDMA1 HW request is UCPD1_TX       */
+#define GPDMA1_REQUEST_UCPD1_RX       139U     /*!< GPDMA1 HW request is UCPD1_RX       */
+
+#define GPDMA1_REQUEST_DCMI_PSSI      140U     /*!< GPDMA1 HW request is DCMI_PSSI      */
+
+#define GPDMA1_REQUEST_I3C1_TC        141U     /*!< GPDMA1 HW request is I3C1_TC        */
+#define GPDMA1_REQUEST_I3C1_RS        142U     /*!< GPDMA1 HW request is I3C1_RS        */
+
+#define GPDMA1_REQUEST_I3C2_TC        143U     /*!< GPDMA1 HW request is I3C2_TC        */
+#define GPDMA1_REQUEST_I3C2_RS        144U     /*!< GPDMA1 HW request is I3C2_RS        */
+
+/* Software request */
+#define DMA_REQUEST_SW                DMA_CTR2_SWREQ  /*!< DMA SW request               */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Block_Request DMA Block Request
+  * @brief    DMA Block Request
+  * @{
+  */
+#define DMA_BREQ_SINGLE_BURST          0x00000000U     /*!< Hardware request protocol at a single / burst level */
+#define DMA_BREQ_BLOCK                 DMA_CTR2_BREQ   /*!< Hardware request protocol at a block level          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Transfer_Direction DMA Transfer Direction
+  * @brief    DMA transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ           /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ          /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode
+  * @brief    DMA Source Increment Mode
+  * @{
+  */
+#define DMA_SINC_FIXED       0x00000000U   /*!< Source fixed       single / burst */
+#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode
+  * @brief    DMA Destination Increment Mode
+  * @{
+  */
+#define DMA_DINC_FIXED       0x00000000U   /*!< Destination fixed       single / burst */
+#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Source_Data_Width DMA Source Data Width
+  * @brief    DMA Source Data Width
+  * @{
+  */
+#define DMA_SRC_DATAWIDTH_BYTE       0x00000000U           /*!< Source data width : Byte       */
+#define DMA_SRC_DATAWIDTH_HALFWORD   DMA_CTR1_SDW_LOG2_0   /*!< Source data width : HalfWord   */
+#define DMA_SRC_DATAWIDTH_WORD       DMA_CTR1_SDW_LOG2_1   /*!< Source data width : Word       */
+#define DMA_SRC_DATAWIDTH_DOUBLEWORD DMA_CTR1_SDW_LOG2     /*!< Source data width : DoubleWord */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Destination_Data_Width DMA destination Data Width
+  * @brief    DMA destination Data Width
+  * @{
+  */
+#define DMA_DEST_DATAWIDTH_BYTE       0x00000000U          /*!< Destination data width : Byte       */
+#define DMA_DEST_DATAWIDTH_HALFWORD   DMA_CTR1_DDW_LOG2_0  /*!< Destination data width : HalfWord   */
+#define DMA_DEST_DATAWIDTH_WORD       DMA_CTR1_DDW_LOG2_1  /*!< Destination data width : Word       */
+#define DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2    /*!< Destination data width : DoubleWord */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_Level DMA Priority Level
+  * @brief    DMA Priority Level
+  * @{
+  */
+#define DMA_LOW_PRIORITY_LOW_WEIGHT  0x00000000U    /*!< Priority level : Low Priority, Low weight  */
+#define DMA_LOW_PRIORITY_MID_WEIGHT  DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight  */
+#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */
+#define DMA_HIGH_PRIORITY            DMA_CCR_PRIO   /*!< Priority level : HIGH Priority             */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port
+  * @brief    DMA Transfer Allocated Port
+  * @{
+  */
+#define DMA_SRC_ALLOCATED_PORT0  0x00000000U  /*!< Source allocated Port 0      */
+#define DMA_SRC_ALLOCATED_PORT1  DMA_CTR1_SAP /*!< Source allocated Port 1      */
+#define DMA_DEST_ALLOCATED_PORT0 0x00000000U  /*!< Destination allocated Port 0 */
+#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode
+  * @brief    DMA Transfer Event Mode
+  * @{
+  */
+#define DMA_TCEM_BLOCK_TRANSFER          0x00000000U     /*!< The TC event is generated at the end of each block and the
+                                                              HT event is generated at the half of each block         */
+#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block
+                                                              and the HT event is generated at the half of the repeated
+                                                              block                                                   */
+#define DMA_TCEM_EACH_LL_ITEM_TRANSFER   DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list
+                                                              item and the HT event is generated at the half of each
+                                                              linked-list item                                        */
+#define DMA_TCEM_LAST_LL_ITEM_TRANSFER   DMA_CTR2_TCEM   /*!< The TC event is generated at the end of the last
+                                                              linked-list item and the HT event is generated at the half
+                                                              of the last linked-list item                            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Transfer_Mode DMA Transfer Mode
+  * @brief    DMA Transfer Mode
+  * @{
+  */
+#define DMA_NORMAL                           (0x00U)     /*!< Normal DMA transfer                    */
+#define DMA_PFCTRL                    DMA_CTR2_PFREQ     /*!< HW request peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_ISOLATION_MODE DMA Channel isolation mode (CID filtering)
+  * @brief    DMA Channel isolation enabling (CID filtering)
+  * @{
+  */
+#define DMA_ISOLATION_OFF                      0U                /*!< DMA Channel isolation (CID filtering) is disabled */
+#define DMA_ISOLATION_ON                       1U                /*!< DMA Channel isolation (CID filtering) is enabled  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Channel_CID_Filtering_Static Static DMA Channel Filtering CID (isolation)
+  * @brief    DMA Channel Filtering Static CID (isolation)
+  * @{
+  */
+#define DMA_CHANNEL_STATIC_CID_0             (0U<<DMA_CCIDCFGR_SCID_Pos)         /*!<  Channel control to CID0 in static mode */
+#define DMA_CHANNEL_STATIC_CID_1             (1U<<DMA_CCIDCFGR_SCID_Pos)         /*!<  Channel control to CID1 in static mode */
+#define DMA_CHANNEL_STATIC_CID_2             (2U<<DMA_CCIDCFGR_SCID_Pos)         /*!<  Channel control to CID2 in static mode */
+#define DMA_CHANNEL_STATIC_CID_3             (3U<<DMA_CCIDCFGR_SCID_Pos)         /*!<  Channel control to CID3 in static mode */
+#define DMA_CHANNEL_STATIC_CID_4             (4U<<DMA_CCIDCFGR_SCID_Pos)         /*!<  Channel control to CID4 in static mode */
+#define DMA_CHANNEL_STATIC_CID_5             (5U<<DMA_CCIDCFGR_SCID_Pos)         /*!<  Channel control to CID5 in static mode */
+#define DMA_CHANNEL_STATIC_CID_6             (6U<<DMA_CCIDCFGR_SCID_Pos)         /*!<  Channel control to CID6 in static mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
+  * @brief    DMA Channel Security and Privilege Attributes
+  * @note     Secure and non-secure attributes are only available from the secure world when TZEN = 1
+  * @{
+  */
+#define DMA_CHANNEL_PRIV      (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U)     /*!< Channel is privileged             */
+#define DMA_CHANNEL_NPRIV     (DMA_CHANNEL_ATTR_PRIV_MASK)             /*!< Channel is unprivileged           */
+
+#define DMA_CHANNEL_SEC       (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U)      /*!< Channel is secure                 */
+#define DMA_CHANNEL_NSEC      (DMA_CHANNEL_ATTR_SEC_MASK)              /*!< Channel is non-secure             */
+#define DMA_CHANNEL_SRC_SEC   (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U)  /*!< Channel source is secure          */
+#define DMA_CHANNEL_SRC_NSEC  (DMA_CHANNEL_ATTR_SEC_SRC_MASK)          /*!< Channel source is non-secure      */
+#define DMA_CHANNEL_DEST_SEC  (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure     */
+#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK)         /*!< Channel destination is non-secure */
+
+#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U)                         /*!< Channel attribute is unlocked     */
+#define DMA_CHANNEL_ATTRIBUTE_LOCKED   (0x01U)                         /*!< Channel attribute is locked       */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @brief    DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state.
+  * @param  __HANDLE__ : DMA handle.
+  * @retval None.
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \
+  ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param  __HANDLE__ : DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__) \
+  ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param  __HANDLE__ : DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__) \
+  ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET))
+
+/**
+  * @brief  Get the DMA channel pending flags.
+  * @param  __HANDLE__ : DMA handle.
+  * @param  __FLAG__   : Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TC    : Transfer Complete flag.
+  *            @arg DMA_FLAG_HT    : Half Transfer Complete flag.
+  *            @arg DMA_FLAG_DTE   : Data Transfer Error flag.
+  *            @arg DMA_FLAG_ULE   : Update linked-list Error flag.
+  *            @arg DMA_FLAG_USE   : User Setting Error flag.
+  *            @arg DMA_FLAG_TO    : Trigger Overrun flag.
+  *            @arg DMA_FLAG_SUSP  : Completed Suspension flag.
+  *            @arg DMA_FLAG_IDLEF : Idle flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \
+  ((__HANDLE__)->Instance->CSR & (__FLAG__))
+
+/**
+  * @brief  Clear the DMA Channel pending flags.
+  * @param  __HANDLE__ : DMA handle.
+  * @param  __FLAG__   : Specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TC   : Transfer Complete flag.
+  *            @arg DMA_FLAG_HT   : Half Transfer Complete flag.
+  *            @arg DMA_FLAG_DTE  : Data Transfer Error flag.
+  *            @arg DMA_FLAG_ULE  : Update Linked-List Error flag.
+  *            @arg DMA_FLAG_USE  : User Setting Error flag.
+  *            @arg DMA_FLAG_TO   : Trigger Overrun flag.
+  *            @arg DMA_FLAG_SUSP : Completed Suspension flag.
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+  ((__HANDLE__)->Instance->CFCR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DMA Channel interrupts.
+  * @param  __HANDLE__    : DMA handle.
+  * @param  __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC   : Transfer Complete interrupt.
+  *            @arg DMA_IT_HT   : Half Transfer Complete interrupt.
+  *            @arg DMA_IT_DTE  : Data Transfer Error interrupt.
+  *            @arg DMA_IT_ULE  : Update Linked-List Error interrupt.
+  *            @arg DMA_IT_USE  : User Setting Error interrupt.
+  *            @arg DMA_IT_TO   : Trigger Overrun interrupt.
+  *            @arg DMA_IT_SUSP : Completed Suspension interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+  ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__   : DMA handle.
+  * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC   : Transfer Complete interrupt.
+  *            @arg DMA_IT_HT   : Half Transfer Complete interrupt.
+  *            @arg DMA_IT_DTE  : Data Transfer Error interrupt.
+  *            @arg DMA_IT_ULE  : Update Linked-List Error interrupt.
+  *            @arg DMA_IT_USE  : User Setting Error interrupt.
+  *            @arg DMA_IT_TO   : Trigger Overrun interrupt.
+  *            @arg DMA_IT_SUSP : Completed Suspension interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified DMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__    : DMA handle.
+  * @param  __INTERRUPT__ : specifies the DMA interrupt source to check.
+  *            @arg DMA_IT_TC   : Transfer Complete interrupt.
+  *            @arg DMA_IT_HT   : Half Transfer Complete interrupt.
+  *            @arg DMA_IT_DTE  : Data Transfer Error interrupt.
+  *            @arg DMA_IT_ULE  : Update Linked-List Error interrupt.
+  *            @arg DMA_IT_USE  : User Setting Error interrupt.
+  *            @arg DMA_IT_TO   : Trigger Overrun interrupt.
+  *            @arg DMA_IT_SUSP : Completed Suspension interrupt.
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Writes the block number of bytes to be transferred from the source on the DMA Channel.
+  * @param  __HANDLE__  : DMA handle.
+  * @param  __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535).
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \
+  MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__))
+
+/**
+  * @brief  Returns the number of remaining data bytes in the current DMA Channel transfer.
+  * @param  __HANDLE__ : DMA handle.
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) \
+  (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT)
+/**
+  * @}
+  */
+
+
+/* Include DMA HAL Extension module */
+#include "stm32n6xx_hal_dma_ex.h"
+
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @brief    Initialization and De-Initialization Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions
+  * @brief    I/O Operation Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
+                                uint32_t SrcAddress,
+                                uint32_t DstAddress,
+                                uint32_t SrcDataSize);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
+                                   uint32_t SrcAddress,
+                                   uint32_t DstAddress,
+                                   uint32_t SrcDataSize);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
+                                          HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+                                          uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
+                                           HAL_DMA_CallbackIDTypeDef CallbackID,
+                                           void (*const  pCallback)(DMA_HandleTypeDef *const _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
+                                             HAL_DMA_CallbackIDTypeDef CallbackID);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions
+  * @brief    State and Error Functions
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions
+  * @brief    DMA Attributes Functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
+                                                  uint32_t ChannelAttributes);
+HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
+                                                     uint32_t *const pChannelAttributes);
+
+#if defined (CPU_IN_SECURE_STATE)
+HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma);
+#endif /* CPU_IN_SECURE_STATE */
+HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma,
+                                                   uint32_t *const pLockState);
+
+
+#if defined (CPU_IN_SECURE_STATE)
+HAL_StatusTypeDef HAL_DMA_SetIsolationAttributes(DMA_HandleTypeDef *const hdma,
+                                                 DMA_IsolationConfigTypeDef const *const pConfig);
+#endif /* CPU_IN_SECURE_STATE */
+HAL_StatusTypeDef HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const *const hdma,
+                                                 DMA_IsolationConfigTypeDef *const pConfig);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA Private Constants
+  * @{
+  */
+#define HAL_TIMEOUT_DMA_ABORT          (0x00000005U) /* DMA channel abort timeout 5 milli-second */
+#define HAL_DMA_CHANNEL_START          (0x00000050U) /* DMA channel offset                       */
+#define HAL_DMA_CHANNEL_SIZE           (0x00000080U) /* DMA channel size                         */
+#define HAL_DMA_OFFSET_MASK            (0x00000FFFU) /* DMA channel offset mask                  */
+#define DMA_CHANNEL_ATTR_PRIV_MASK     (0x00000010U) /* DMA channel privilege mask               */
+#define DMA_CHANNEL_ATTR_SEC_MASK      (0x00000020U) /* DMA channel secure mask                  */
+#define DMA_CHANNEL_ATTR_SEC_SRC_MASK  (0x00000040U) /* DMA channel source secure mask           */
+#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask      */
+#define DMA_CHANNEL_ATTR_VALUE_MASK    (0x0000000FU) /* DMA channel attributes value mask        */
+#define DMA_CHANNEL_ATTR_ITEM_MASK     (0x000000F0U) /* DMA channel attributes item mask         */
+#define DMA_CHANNEL_BURST_MIN          (0x00000001U) /* DMA channel minimum burst size           */
+#define DMA_CHANNEL_BURST_MAX          (0x00000040U) /* DMA channel maximum burst size           */
+/**
+  * @}
+  */
+
+
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA Private Macros
+  * @{
+  */
+#define GET_DMA_INSTANCE(__HANDLE__) \
+  ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK)))
+
+#define GET_DMA_CHANNEL(__HANDLE__) \
+  ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE)
+
+#define IS_DMA_MODE(MODE) \
+  (((MODE) == DMA_NORMAL) || \
+   ((MODE) == DMA_PFCTRL))
+
+#define IS_DMA_DIRECTION(DIRECTION)         \
+  (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
+   ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+   ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_LEVEL_COMPLETE(LEVEL)     \
+  (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \
+   ((LEVEL) == HAL_DMA_HALF_TRANSFER))
+
+#define IS_DMA_SOURCE_INC(INC)  \
+  (((INC) == DMA_SINC_FIXED) || \
+   ((INC) == DMA_SINC_INCREMENTED))
+
+#define IS_DMA_DESTINATION_INC(INC) \
+  (((INC) == DMA_DINC_FIXED)     || \
+   ((INC) == DMA_DINC_INCREMENTED))
+
+#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH)       \
+  (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE)     || \
+   ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \
+   ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)     || \
+   ((WIDTH) == DMA_SRC_DATAWIDTH_DOUBLEWORD))
+
+#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH)   \
+  (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE)     || \
+   ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \
+   ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)     || \
+   ((WIDTH) == DMA_DEST_DATAWIDTH_DOUBLEWORD))
+
+#define IS_DMA_BURST_LENGTH(LENGTH)       \
+  (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \
+   ((LENGTH) <= DMA_CHANNEL_BURST_MAX))
+
+#define IS_DMA_PRIORITY(PRIORITY)                  \
+  (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT)  || \
+   ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT)  || \
+   ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
+   ((PRIORITY) == DMA_HIGH_PRIORITY))
+
+#define  IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \
+  (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U)
+
+#define IS_DMA_REQUEST(REQUEST)     \
+  (((REQUEST) == DMA_REQUEST_SW) || \
+   ((REQUEST) <= HPDMA1_REQUEST_I3C2_RS))
+
+#define IS_DMA_BLOCK_HW_REQUEST(MODE)   \
+  (((MODE) == DMA_BREQ_SINGLE_BURST) || \
+   ((MODE) == DMA_BREQ_BLOCK))
+
+#define IS_DMA_TCEM_EVENT_MODE(MODE)               \
+  (((MODE) == DMA_TCEM_BLOCK_TRANSFER)          || \
+   ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
+   ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER)   || \
+   ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
+
+#define IS_DMA_BLOCK_SIZE(SIZE) \
+  (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT))
+
+#if defined (CPU_IN_SECURE_STATE)
+#define IS_DMA_ATTRIBUTES(ATTRIBUTE)                                                                               \
+  (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \
+   (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) ==          \
+    (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U)))
+#else
+#define IS_DMA_ATTRIBUTES(ATTRIBUTE)    \
+  (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
+   ((ATTRIBUTE) == DMA_CHANNEL_NPRIV))
+#endif /* CPU_IN_SECURE_STATE */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \
+  (((INSTANCE)->SMISR & (GLOBAL_FLAG)))
+#endif /* CPU_IN_SECURE_STATE */
+#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \
+  (((INSTANCE)->MISR & (GLOBAL_FLAG)))
+
+#define IS_DMA_ISOLATION_MODE(MODE) \
+  (((MODE) == DMA_ISOLATION_OFF)  || \
+   ((MODE) == DMA_ISOLATION_ON))
+
+#define IS_DMA_ISOLATION_STATIC_CID(ID)          \
+  (((ID) == DMA_CHANNEL_STATIC_CID_0)  || \
+   ((ID) == DMA_CHANNEL_STATIC_CID_1)  || \
+   ((ID) == DMA_CHANNEL_STATIC_CID_2)  || \
+   ((ID) == DMA_CHANNEL_STATIC_CID_3)  || \
+   ((ID) == DMA_CHANNEL_STATIC_CID_4)  || \
+   ((ID) == DMA_CHANNEL_STATIC_CID_5)  || \
+   ((ID) == DMA_CHANNEL_STATIC_CID_6))
+
+/**
+  * @}
+  */
+
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_DMA_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma2d.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma2d.h
new file mode 100644
index 000000000..18c530d1e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma2d.h
@@ -0,0 +1,715 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_dma2d.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA2D HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_DMA2D_H
+#define STM32N6xx_HAL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (DMA2D)
+
+/** @addtogroup DMA2D DMA2D
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
+  * @{
+  */
+#define MAX_DMA2D_LAYER  2U  /*!< DMA2D maximum number of layers */
+
+/**
+  * @brief DMA2D CLUT Structure definition
+  */
+typedef struct
+{
+  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
+
+  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
+                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */
+
+  uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+} DMA2D_CLUTCfgTypeDef;
+
+/**
+  * @brief DMA2D Init structure definition
+  */
+typedef struct
+{
+  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
+                                                This parameter can be one value of @ref DMA2D_Mode. */
+
+  uint32_t             ColorMode;          /*!< Configures the color format of the output image.
+                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
+
+  uint32_t             OutputOffset;       /*!< Specifies the Offset value.
+                                                This parameter must be a number between
+                                                Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+
+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
+                                               for the output pixel format converter.
+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */
+
+
+  uint32_t             BytesSwap;         /*!< Select byte regular mode or bytes swap mode (two by two).
+                                               This parameter can be one value of @ref DMA2D_Bytes_Swap. */
+
+  uint32_t             LineOffsetMode;    /*!< Configures how is expressed the line offset for the foreground, background and output.
+                                               This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
+
+} DMA2D_InitTypeDef;
+
+
+/**
+  * @brief DMA2D Layer structure definition
+  */
+typedef struct
+{
+  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
+                                               This parameter must be a number between
+                                               Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
+                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
+
+  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+
+  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value
+                                               in case of A8 or A4 color mode.
+                                               This parameter must be a number between Min_Data = 0x00
+                                               and Max_Data = 0xFF except for the color modes detailed below.
+                                               @note In case of A8 or A4 color mode (ARGB),
+                                               this parameter must be a number between
+                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
+                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+                                               - InputAlpha[16:23] is the red value RED[0:7]
+                                               - InputAlpha[8:15] is the green value GREEN[0:7]
+                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */
+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
+
+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */
+
+  uint32_t             ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
+                                               This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
+
+} DMA2D_LayerCfgTypeDef;
+
+/**
+  * @brief  HAL DMA2D State structures definition
+  */
+typedef enum
+{
+  HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
+  HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
+  HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
+} HAL_DMA2D_StateTypeDef;
+
+/**
+  * @brief  DMA2D handle Structure definition
+  */
+typedef struct __DMA2D_HandleTypeDef
+{
+  DMA2D_TypeDef               *Instance;                                  /*!< DMA2D register base address.           */
+
+  DMA2D_InitTypeDef           Init;                                       /*!< DMA2D communication parameters.        */
+
+  void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);        /*!< DMA2D transfer complete callback.      */
+
+  void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D transfer error callback.         */
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+  void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D line event callback.             */
+
+  void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
+
+  void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);         /*!< DMA2D Msp Init callback.               */
+
+  void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D Msp DeInit callback.             */
+
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                  /*!< DMA2D Layers parameters                */
+
+  HAL_LockTypeDef             Lock;                                       /*!< DMA2D lock.                            */
+
+  __IO HAL_DMA2D_StateTypeDef State;                                      /*!< DMA2D transfer state.                  */
+
+  __IO uint32_t               ErrorCode;                                  /*!< DMA2D error code.                      */
+} DMA2D_HandleTypeDef;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DMA2D Callback pointer definition
+  */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Error_Code DMA2D Error Code
+  * @{
+  */
+#define HAL_DMA2D_ERROR_NONE        0x00000000U  /*!< No error             */
+#define HAL_DMA2D_ERROR_TE          0x00000001U  /*!< Transfer error       */
+#define HAL_DMA2D_ERROR_CE          0x00000002U  /*!< Configuration error  */
+#define HAL_DMA2D_ERROR_CAE         0x00000004U  /*!< CLUT access error    */
+#define HAL_DMA2D_ERROR_TIMEOUT     0x00000020U  /*!< Timeout error        */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U  /*!< Invalid callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Mode DMA2D Mode
+  * @{
+  */
+#define DMA2D_M2M                   0x00000000U                         /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0                     /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1                     /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M                   (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
+#define DMA2D_M2M_BLEND_FG          DMA2D_CR_MODE_2                     /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
+#define DMA2D_M2M_BLEND_BG          (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
+  * @{
+  */
+#define DMA2D_OUTPUT_ARGB8888       0x00000000U                           /*!< ARGB8888 DMA2D color mode */
+#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
+#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
+#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
+#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
+  * @{
+  */
+#define DMA2D_INPUT_ARGB8888        0x00000000U  /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888          0x00000001U  /*!< RGB888 color mode   */
+#define DMA2D_INPUT_RGB565          0x00000002U  /*!< RGB565 color mode   */
+#define DMA2D_INPUT_ARGB1555        0x00000003U  /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444        0x00000004U  /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8              0x00000005U  /*!< L8 color mode       */
+#define DMA2D_INPUT_AL44            0x00000006U  /*!< AL44 color mode     */
+#define DMA2D_INPUT_AL88            0x00000007U  /*!< AL88 color mode     */
+#define DMA2D_INPUT_L4              0x00000008U  /*!< L4 color mode       */
+#define DMA2D_INPUT_A8              0x00000009U  /*!< A8 color mode       */
+#define DMA2D_INPUT_A4              0x0000000AU  /*!< A4 color mode       */
+#define DMA2D_INPUT_YCBCR           0x0000000BU  /*!< YCbCr color mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
+  * @{
+  */
+#define DMA2D_NO_MODIF_ALPHA        0x00000000U  /*!< No modification of the alpha channel value                     */
+#define DMA2D_REPLACE_ALPHA         0x00000001U  /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA         0x00000002U  /*!< Replace original alpha channel value by programmed alpha value
+                                                      with original alpha channel value                              */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
+  * @{
+  */
+#define DMA2D_REGULAR_ALPHA         0x00000000U  /*!< No modification of the alpha channel value */
+#define DMA2D_INVERTED_ALPHA        0x00000001U  /*!< Invert the alpha channel value */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
+  * @{
+  */
+#define DMA2D_RB_REGULAR            0x00000000U  /*!< Select regular mode (RGB or ARGB) */
+#define DMA2D_RB_SWAP               0x00000001U  /*!< Select swap mode (BGR or ABGR) */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
+  * @{
+  */
+#define DMA2D_LOM_PIXELS            0x00000000U   /*!< Line offsets expressed in pixels */
+#define DMA2D_LOM_BYTES             DMA2D_CR_LOM  /*!< Line offsets expressed in bytes */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
+  * @{
+  */
+#define DMA2D_BYTES_REGULAR         0x00000000U      /*!< Bytes in regular order in output FIFO */
+#define DMA2D_BYTES_SWAP            DMA2D_OPFCCR_SB  /*!< Bytes are swapped two by two in output FIFO */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
+  * @{
+  */
+#define DMA2D_NO_CSS               0x00000000U  /*!< No chroma sub-sampling 4:4:4 */
+#define DMA2D_CSS_422              0x00000001U  /*!< chroma sub-sampling 4:2:2 */
+#define DMA2D_CSS_420              0x00000002U  /*!< chroma sub-sampling 4:2:0 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
+  * @{
+  */
+#define DMA2D_CCM_ARGB8888          0x00000000U  /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888            0x00000001U  /*!< RGB888 DMA2D CLUT color mode   */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Interrupts DMA2D Interrupts
+  * @{
+  */
+#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
+#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
+#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Flags DMA2D Flags
+  * @{
+  */
+#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
+/**
+  * @}
+  */
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DMA2D common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DMA2D_MSPINIT_CB_ID           = 0x00U,    /*!< DMA2D MspInit callback ID                 */
+  HAL_DMA2D_MSPDEINIT_CB_ID         = 0x01U,    /*!< DMA2D MspDeInit callback ID               */
+  HAL_DMA2D_TRANSFERCOMPLETE_CB_ID  = 0x02U,    /*!< DMA2D transfer complete callback ID       */
+  HAL_DMA2D_TRANSFERERROR_CB_ID     = 0x03U,    /*!< DMA2D transfer error callback ID          */
+  HAL_DMA2D_LINEEVENT_CB_ID         = 0x04U,    /*!< DMA2D line event callback ID              */
+  HAL_DMA2D_CLUTLOADINGCPLT_CB_ID   = 0x05U,    /*!< DMA2D CLUT loading completion callback ID */
+} HAL_DMA2D_CallbackIDTypeDef;
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA2D handle state
+  * @param  __HANDLE__ specifies the DMA2D handle.
+  * @retval None
+  */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{                                             \
+                                                       (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+                                                       (__HANDLE__)->MspInitCallback = NULL;       \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                     }while(0)
+#else
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+
+/**
+  * @brief  Enable the DMA2D.
+  * @param  __HANDLE__ DMA2D handle
+  * @retval None.
+  */
+#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the DMA2D pending flags.
+  * @param  __HANDLE__ DMA2D handle
+  * @param  __FLAG__ flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag
+  * @retval The state of FLAG.
+  */
+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/**
+  * @brief  Clear the DMA2D pending flags.
+  * @param  __HANDLE__ DMA2D handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_FLAG_CE:  Configuration error flag
+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag
+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag
+  *            @arg DMA2D_FLAG_TE:  Transfer error flag
+  * @retval None
+  */
+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DMA2D interrupts.
+  * @param  __HANDLE__ DMA2D handle
+  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA2D interrupts.
+  * @param  __HANDLE__ DMA2D handle
+  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
+  * @param  __HANDLE__ DMA2D handle
+  * @param  __INTERRUPT__ specifies the DMA2D interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
+  * @retval The state of INTERRUPT source.
+  */
+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+                                             pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                  uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+                                          uint32_t DstAddress, uint32_t Width,  uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                     uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+                                             uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
+                                          uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
+                                             uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
+void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
+void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions *************************************************/
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State functions ***************************************************/
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
+uint32_t               HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
+  * @{
+  */
+#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Color_Value DMA2D Color Value
+  * @{
+  */
+#define DMA2D_COLOR_VALUE                 0x000000FFU  /*!< Color value mask */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
+  * @{
+  */
+#define DMA2D_MAX_LAYER         2U         /*!< DMA2D maximum number of layers */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Layers DMA2D Layers
+  * @{
+  */
+#define DMA2D_BACKGROUND_LAYER             0x00000000U   /*!< DMA2D Background Layer (layer 0) */
+#define DMA2D_FOREGROUND_LAYER             0x00000001U   /*!< DMA2D Foreground Layer (layer 1) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Offset DMA2D Offset
+  * @{
+  */
+#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< maximum Line Offset */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Size DMA2D Size
+  * @{
+  */
+#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D maximum number of pixels per line */
+#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D maximum number of lines           */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
+  * @{
+  */
+#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D maximum CLUT size */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
+  * @{
+  */
+#define IS_DMA2D_LAYER(LAYER)                 (((LAYER) == DMA2D_BACKGROUND_LAYER)\
+                                               || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+
+#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)          || ((MODE) == DMA2D_M2M_PFC) || \
+                                               ((MODE) == DMA2D_M2M_BLEND)    || ((MODE) == DMA2D_R2M)     || \
+                                               ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
+
+#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+
+#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
+#define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
+#define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
+#define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
+
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
+                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || \
+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
+                                               ((INPUT_CM) == DMA2D_INPUT_L8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || \
+                                               ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
+                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_A8)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_A4)       || \
+                                               ((INPUT_CM) == DMA2D_INPUT_YCBCR))
+
+#define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
+                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
+                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
+#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
+                                                 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
+
+#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
+                                   ((RB_Swap) == DMA2D_RB_SWAP))
+
+#define IS_DMA2D_LOM_MODE(LOM)          (((LOM) == DMA2D_LOM_PIXELS) || \
+                                         ((LOM) == DMA2D_LOM_BYTES))
+
+#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
+                                         ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
+
+#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS)  || \
+                                           ((CSS) == DMA2D_CSS_422) || \
+                                           ((CSS) == DMA2D_CSS_420))
+
+#define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
+#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+                                               ((IT) == DMA2D_IT_TW)  || ((IT) == DMA2D_IT_TC)  || \
+                                               ((IT) == DMA2D_IT_TE)  || ((IT) == DMA2D_IT_CE))
+#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+                                               ((FLAG) == DMA2D_FLAG_TW)  || ((FLAG) == DMA2D_FLAG_TC)  || \
+                                               ((FLAG) == DMA2D_FLAG_TE)  || ((FLAG) == DMA2D_FLAG_CE))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (DMA2D) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_DMA2D_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma_ex.h
new file mode 100644
index 000000000..2067c9f48
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dma_ex.h
@@ -0,0 +1,876 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32N6xx_HAL_DMA_EX_H
+#define STM32N6xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+
+/**
+  * @brief DMAEx Data Handling Configuration Structure Definition.
+  */
+typedef struct
+{
+  uint32_t DataExchange;  /*!< Specifies the DMA channel data exchange mode.
+                               This parameter can be a value of @ref DMAEx_Data_Exchange  */
+
+  uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode
+                               This parameter can be a value of @ref DMAEx_Data_Alignment */
+
+} DMA_DataHandlingConfTypeDef;
+
+/**
+  * @brief DMAEx Trigger Configuration Structure Definition.
+  */
+typedef struct
+{
+  uint32_t TriggerMode;      /*!< Specifies the DMA channel trigger mode.
+                                  This parameter can be a value of @ref DMAEx_Trigger_Mode      */
+
+  uint32_t TriggerPolarity;  /*!< Specifies the DMA channel trigger event polarity.
+                                  This parameter can be a value of @ref DMAEx_Trigger_Polarity  */
+
+  uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection.
+                                  This parameter can be a value of @ref DMAEx_Trigger_Selection */
+
+} DMA_TriggerConfTypeDef;
+
+/**
+  * @brief DMAEx Repeated Block Configuration Structure Definition.
+  */
+typedef struct
+{
+  uint32_t RepeatCount;      /*!< Specifies the DMA channel repeat count (the number of repetitions of block).
+                                  This parameter can be a value between 1 and 2048                                    */
+
+  int32_t SrcAddrOffset;     /*!< Specifies the DMA channel single/burst source address offset :
+                                  This parameter can be a value between -8191 and 8191.
+                                  * If source address offset > 0 => Increment the source address by offset from where
+                                    the last single/burst transfer ends.
+                                  * If source address offset < 0 => Decrement the source address by offset from where
+                                    the last single/burst transfer ends.
+                                  * If source address offset == 0 => The next single/burst source address starts from
+                                    where the last transfer ends                                                      */
+
+  int32_t DestAddrOffset;    /*!< Specifies the DMA channel single/burst destination address offset signed value :
+                                  This parameter can be a value between -8191 and 8191.
+                                  * If destination address offset > 0 => Increment the destination address by offset
+                                    from where the last single/burst transfer ends.
+                                  * If destination address offset < 0 => Decrement the destination address by offset
+                                    from where the last single/burst transfer ends.
+                                  * If destination address offset == 0 => The next single/burst destination address
+                                    starts from where the last transfer ends.                                         */
+
+  int32_t BlkSrcAddrOffset;  /*!< Specifies the DMA channel block source address offset signed value :
+                                  This parameter can be a value between -65535 and 65535.
+                                  * If block source address offset > 0 => Increment the block source address by offset
+                                    from where the last block ends.
+                                  * If block source address offset < 0 => Decrement the next block source address by
+                                    offset from where the last block ends.
+                                  * If block source address offset == 0 =>  the next block source address starts from
+                                    where the last block ends                                                         */
+
+  int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value :
+                                  This parameter can be a value between -65535 and 65535.
+                                  * If block destination address offset > 0 => Increment the block destination address
+                                    by offset from where the last block ends.
+                                  * If block destination address offset < 0 => Decrement the next block destination
+                                    address by offset from where the last block ends.
+                                  * If block destination address offset == 0 =>  the next block destination address
+                                    starts from where the last block ends                                             */
+
+} DMA_RepeatBlockConfTypeDef;
+
+/**
+  * @brief DMAEx Queue State Enumeration Definition.
+  */
+typedef enum
+{
+  HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty              */
+  HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use      */
+  HAL_DMA_QUEUE_STATE_BUSY  = 0x02U  /*!< DMA queue execution on going */
+
+} HAL_DMA_QStateTypeDef;
+
+/**
+  * @brief  DMAEx Linked-List Node Configuration Structure Definition.
+  */
+typedef struct
+{
+  uint32_t                    NodeType;           /*!< Specifies the DMA channel node type.
+                                                       This parameter can be a value of @ref DMAEx_Node_Type          */
+
+  DMA_InitTypeDef             Init;               /*!< Specifies the DMA channel basic configuration                  */
+
+  DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration  */
+
+  DMA_TriggerConfTypeDef      TriggerConfig;      /*!< Specifies the DMA channel trigger configuration                */
+
+  DMA_RepeatBlockConfTypeDef  RepeatBlockConfig;  /*!< Specifies the DMA channel repeated block configuration         */
+
+  uint32_t                    SrcAddress;         /*!< Specifies the source memory address                            */
+  uint32_t                    DstAddress;         /*!< Specifies the destination memory address                       */
+  uint32_t                    DataSize;           /*!< Specifies the source data size in bytes                        */
+
+#if defined (CPU_IN_SECURE_STATE)
+  uint32_t                    SrcSecure;          /*!< Specifies the source security attribute                        */
+  uint32_t                    DestSecure;         /*!< Specifies the destination security attribute                   */
+#endif /* CPU_IN_SECURE_STATE */
+
+} DMA_NodeConfTypeDef;
+
+/**
+  * @brief  DMAEx Linked-List Node Structure Definition.
+  */
+typedef struct
+{
+  uint32_t LinkRegisters[8U]; /*!< Physical Node register description */
+  uint32_t NodeInfo;          /*!< Node information                   */
+
+} DMA_NodeTypeDef;
+
+/**
+  * @brief DMAEx Linked-List Queue Structure Definition.
+  */
+typedef struct __DMA_QListTypeDef
+{
+  DMA_NodeTypeDef                *Head;              /*!< Specifies the queue head node                    */
+
+  DMA_NodeTypeDef                *FirstCircularNode; /*!< Specifies the queue first circular node          */
+
+  uint32_t                       NodeNumber;         /*!< Specifies the queue node number                  */
+
+  __IO HAL_DMA_QStateTypeDef     State;              /*!< Specifies the queue state                        */
+
+  __IO uint32_t                  ErrorCode;          /*!< Specifies the queue error code                   */
+
+  __IO uint32_t                  Type;               /*!< Specifies whether the queue is static or dynamic */
+
+} DMA_QListTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
+  * @brief    DMAEx Exported Constants
+  * @{
+  */
+
+/** @defgroup Queue_Error_Codes Queue Error Codes
+  * @brief    Queue Error Codes
+  * @{
+  */
+#define HAL_DMA_QUEUE_ERROR_NONE        (0x00U) /*!< No error                                                */
+#define HAL_DMA_QUEUE_ERROR_BUSY        (0x01U) /*!< Error busy                                              */
+#define HAL_DMA_QUEUE_ERROR_EMPTY       (0x02U) /*!< Error unallowed operation for empty queue               */
+#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature                               */
+#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization
+                                                     and queue circular types are incompatible               */
+#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE  (0x05U) /*!< Error out of range node memory                          */
+#define HAL_DMA_QUEUE_ERROR_NOTFOUND    (0x06U) /*!< Error node not found in queue                           */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode
+  * @brief    DMAEx LinkedList Mode
+  * @{
+  */
+#define DMA_LINKEDLIST_NORMAL   DMA_LINKEDLIST             /*!< Linear linked-list DMA channel transfer   */
+#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment
+  * @brief    DMAEx Data Alignment
+  * @{
+  */
+#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U    /*!< If source data width < destination data width
+                                                           => Right aligned padded with 0 up to destination data
+                                                              width                                              */
+#define DMA_DATA_RIGHTALIGN_LEFTTRUNC  0x00000000U    /*!< If source data width > destination data width
+                                                           => Right aligned left Truncated down to destination
+                                                              data width                                         */
+#define DMA_DATA_RIGHTALIGN_SIGNEXT    DMA_CTR1_PAM_0 /*!< If source data width < destination data width
+                                                           => Right Aligned padded with sign extended up to
+                                                              destination data width                             */
+#define DMA_DATA_LEFTALIGN_RIGHTTRUNC  DMA_CTR1_PAM_0 /*!< If source data width > destination data width
+                                                           => Left Aligned Right Truncated down to the
+                                                              destination data width                             */
+#define DMA_DATA_PACK                  DMA_CTR1_PAM_1 /*!< If source data width < destination data width
+                                                           => Packed at the destination data width               */
+#define DMA_DATA_UNPACK                DMA_CTR1_PAM_1 /*!< If source data width > destination data width
+                                                           => Unpacked at the destination data width             */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange
+  * @brief    DMAEx Data Exchange
+  * @{
+  */
+#define DMA_EXCHANGE_NONE          0x00000000U  /*!< No data exchange                                                          */
+#define DMA_EXCHANGE_DEST_BYTE     DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte           */
+#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */
+#define DMA_EXCHANGE_SRC_BYTE      DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word            */
+#define DMA_EXCHANGE_DEST_WORD     DMA_CTR1_DWX /*!< Destination Word exchange when destination data width is > Word */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity
+  * @brief    DMAEx Trigger Polarity
+  * @{
+  */
+#define DMA_TRIG_POLARITY_MASKED  0x00000000U        /*!< No trigger of the selected DMA request. Masked trigger event                                */
+#define DMA_TRIG_POLARITY_RISING  DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input  */
+#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode
+  * @brief    DMAEx Trigger Mode
+  * @{
+  */
+#define DMA_TRIGM_BLOCK_TRANSFER          0x00000000U      /*!< A block transfer is conditioned by (at least) one hit trigger          */
+#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */
+#define DMA_TRIGM_LLI_LINK_TRANSFER       DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger       */
+#define DMA_TRIGM_SINGLE_BURST_TRANSFER   DMA_CTR2_TRIGM   /*!< A single/burst transfer is conditioned by (at least) one hit trigger   */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection
+  * @brief    DMAEx Trigger Selection
+  * @{
+  */
+/* HPDMA1 triggers */
+#define HPDMA1_TRIGGER_DCMIPP_P0_FEND             0U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_FEND            */
+#define HPDMA1_TRIGGER_DCMIPP_P0_LEND             1U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_LEND            */
+#define HPDMA1_TRIGGER_DCMIPP_P0_HSYNC            2U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC           */
+#define HPDMA1_TRIGGER_DCMIPP_P0_VSYNC            3U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC           */
+
+#define HPDMA1_TRIGGER_DCMIPP_P1_FEND             4U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_FEND            */
+#define HPDMA1_TRIGGER_DCMIPP_P1_LEND             5U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_LEND            */
+#define HPDMA1_TRIGGER_DCMIPP_P1_HSYNC            6U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC           */
+#define HPDMA1_TRIGGER_DCMIPP_P1_VSYNC            7U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC           */
+
+#define HPDMA1_TRIGGER_DCMIPP_P2_FEND             8U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_FEND            */
+#define HPDMA1_TRIGGER_DCMIPP_P2_LEND             9U    /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_LEND            */
+#define HPDMA1_TRIGGER_DCMIPP_P2_HSYNC            10U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC           */
+#define HPDMA1_TRIGGER_DCMIPP_P2_VSYNC            11U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC           */
+
+#define HPDMA1_TRIGGER_DMA2D_CTC                  12U   /*!< HPDMA1 HW Trigger signal is DMA2D_CTC                 */
+#define HPDMA1_TRIGGER_DMA2D_TC                   13U   /*!< HPDMA1 HW Trigger signal is DMA2D_TC                  */
+#define HPDMA1_TRIGGER_DMA2D_TW                   14U   /*!< HPDMA1 HW Trigger signal is DMA2D_TW                  */
+
+#define HPDMA1_TRIGGER_JPEG_EOC                   15U   /*!< HPDMA1 HW Trigger signal is JPEG_EOC                  */
+#define HPDMA1_TRIGGER_JPEG_IFNF                  16U   /*!< HPDMA1 HW Trigger signal is JPEG_IFNF                 */
+#define HPDMA1_TRIGGER_JPEG_IFT                   17U   /*!< HPDMA1 HW Trigger signal is JPEG_IFT                  */
+#define HPDMA1_TRIGGER_JPEG_OFNE                  18U   /*!< HPDMA1 HW Trigger signal is JPEG_OFNE                 */
+#define HPDMA1_TRIGGER_JPEG_OFT                   19U   /*!< HPDMA1 HW Trigger signal is JPEG_OFT                  */
+
+#define HPDMA1_LCD_LI                             20U   /*!< HPDMA1 HW Trigger signal is LCD_LI                    */
+
+#define HPDMA1_TRIGGER_GPU2D1_GP_0                21U   /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_0               */
+#define HPDMA1_TRIGGER_GPU2D1_GP_1                22U   /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_1               */
+#define HPDMA1_TRIGGER_GPU2D1_GP_2                23U   /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_2               */
+#define HPDMA1_TRIGGER_GPU2D1_GP_3                24U   /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_3               */
+
+#define HPDMA1_TRIGGER_GFXTIM_3                   25U   /*!< HPDMA1 HW Trigger signal is GFXTIM_3                  */
+#define HPDMA1_TRIGGER_GFXTIM_2                   26U   /*!< HPDMA1 HW Trigger signal is GFXTIM_2                  */
+#define HPDMA1_TRIGGER_GFXTIM_1                   27U   /*!< HPDMA1 HW Trigger signal is GFXTIM_1                  */
+#define HPDMA1_TRIGGER_GFXTIM_0                   28U   /*!< HPDMA1 HW Trigger signal is GFXTIM_0                  */
+
+/* reserved                                       29U                                                              */
+
+#define HPDMA1_TRIGGER_LPTIM1_CH1                 30U   /*!< HPDMA1 HW Trigger signal is LPTIM1_CH1                */
+#define HPDMA1_TRIGGER_LPTIM1_CH2                 31U   /*!< HPDMA1 HW Trigger signal is LPTIM1_CH2                */
+#define HPDMA1_TRIGGER_LPTIM2_CH1                 32U   /*!< HPDMA1 HW Trigger signal is LPTIM2_CH1                */
+#define HPDMA1_TRIGGER_LPTIM2_CH2                 33U   /*!< HPDMA1 HW Trigger signal is LPTIM2_CH2                */
+#define HPDMA1_TRIGGER_LPTIM3_CH1                 34U   /*!< HPDMA1 HW Trigger signal is LPTIM3_CH1                */
+#define HPDMA1_TRIGGER_LPTIM3_CH2                 35U   /*!< HPDMA1 HW Trigger signal is LPTIM3_CH2                */
+#define HPDMA1_TRIGGER_LPTIM4_OUT                 36U   /*!< HPDMA1 HW Trigger signal is LPTIM4_OUT                */
+#define HPDMA1_TRIGGER_LPTIM5_OUT                 37U   /*!< HPDMA1 HW Trigger signal is LPTIM5_OUT                */
+
+/* reserved                                       38U                                                              */
+
+#define HPDMA1_TRIGGER_RTC_WKUP                   39U    /*!< HPDMA1 HW Trigger signal is RTC_WKUP                 */
+
+#define HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC     40U    /*!< HPDMA1 HW Trigger signal is IT_R_WUP_ASYNC           */
+#define HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC     41U    /*!< HPDMA1 HW Trigger signal is IT_T_WUP_ASYNC           */
+
+#define HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC   42U    /*!< HPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */
+
+/* reserved                                       43U                                                              */
+
+#define HPDMA1_TRIGGER_TIM1_TRGO                  44U   /*!< HPDMA1 HW Trigger signal is TIM1_TRGO                 */
+#define HPDMA1_TRIGGER_TIM1_TRGO2                 45U   /*!< HPDMA1 HW Trigger signal is TIM1_TRGO2                */
+#define HPDMA1_TRIGGER_TIM2_TRGO                  46U   /*!< HPDMA1 HW Trigger signal is TIM2_TRGO                 */
+#define HPDMA1_TRIGGER_TIM3_TRGO                  47U   /*!< HPDMA1 HW Trigger signal is TIM3_TRGO                 */
+#define HPDMA1_TRIGGER_TIM4_TRGO                  48U   /*!< HPDMA1 HW Trigger signal is TIM4_TRGO                 */
+#define HPDMA1_TRIGGER_TIM5_TRGO                  49U   /*!< HPDMA1 HW Trigger signal is TIM5_TRGO                 */
+#define HPDMA1_TRIGGER_TIM6_TRGO                  50U   /*!< HPDMA1 HW Trigger signal is TIM6_TRGO                 */
+#define HPDMA1_TRIGGER_TIM7_TRGO                  51U   /*!< HPDMA1 HW Trigger signal is TIM7_TRGO                 */
+#define HPDMA1_TRIGGER_TIM8_TRGO                  52U   /*!< HPDMA1 HW Trigger signal is TIM8_TRGO                 */
+#define HPDMA1_TRIGGER_TIM8_TRGO2                 53U   /*!< HPDMA1 HW Trigger signal is TIM8_TRGO2                */
+
+/* reserved                                       54U                                                              */
+/* reserved                                       55U                                                              */
+/* reserved                                       56U                                                              */
+
+#define HPDMA1_TRIGGER_TIM12_TRGO                 57U   /*!< HPDMA1 HW Trigger signal is TIM12_TRGO                */
+#define HPDMA1_TRIGGER_TIM15_TRGO                 58U   /*!< HPDMA1 HW Trigger signal is TIM15_TRGO                */
+
+/* reserved                                       59U                                                              */
+
+#define HPDMA1_TRIGGER_HPDMA1_CH0_TCF             60U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH1_TCF             61U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH2_TCF             62U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH3_TCF             63U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH4_TCF             64U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH5_TCF             65U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH6_TCF             66U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH7_TCF             67U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH8_TCF             68U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH9_TCF             69U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF            */
+#define HPDMA1_TRIGGER_HPDMA1_CH10_TCF            70U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF           */
+#define HPDMA1_TRIGGER_HPDMA1_CH11_TCF            71U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF           */
+#define HPDMA1_TRIGGER_HPDMA1_CH12_TCF            72U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF           */
+#define HPDMA1_TRIGGER_HPDMA1_CH13_TCF            73U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF           */
+#define HPDMA1_TRIGGER_HPDMA1_CH14_TCF            74U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF           */
+#define HPDMA1_TRIGGER_HPDMA1_CH15_TCF            75U   /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF           */
+
+#define HPDMA1_TRIGGER_GPDMA1_CH0_TCF             76U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH1_TCF             77U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH2_TCF             78U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH3_TCF             79U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH4_TCF             80U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH5_TCF             81U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH6_TCF             82U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH7_TCF             83U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH8_TCF             84U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH9_TCF             85U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF            */
+#define HPDMA1_TRIGGER_GPDMA1_CH10_TCF            86U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF           */
+#define HPDMA1_TRIGGER_GPDMA1_CH11_TCF            87U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF           */
+#define HPDMA1_TRIGGER_GPDMA1_CH12_TCF            88U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF           */
+#define HPDMA1_TRIGGER_GPDMA1_CH13_TCF            89U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF           */
+#define HPDMA1_TRIGGER_GPDMA1_CH14_TCF            90U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF           */
+#define HPDMA1_TRIGGER_GPDMA1_CH15_TCF            91U   /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF           */
+
+/* reserved                                       92U                                                              */
+
+#define HPDMA1_TRIGGER_EXTIT0_SYNC                93U   /*!< HPDMA1 HW Trigger signal is EXTIT0_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT1_SYNC                94U   /*!< HPDMA1 HW Trigger signal is EXTIT1_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT2_SYNC                95U   /*!< HPDMA1 HW Trigger signal is EXTIT2_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT3_SYNC                96U   /*!< HPDMA1 HW Trigger signal is EXTIT3_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT4_SYNC                97U   /*!< HPDMA1 HW Trigger signal is EXTIT4_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT5_SYNC                98U   /*!< HPDMA1 HW Trigger signal is EXTIT5_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT6_SYNC                99U   /*!< HPDMA1 HW Trigger signal is EXTIT6_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT7_SYNC                100U  /*!< HPDMA1 HW Trigger signal is EXTIT7_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT8_SYNC                101U  /*!< HPDMA1 HW Trigger signal is EXTIT8_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT9_SYNC                102U  /*!< HPDMA1 HW Trigger signal is EXTIT9_SYNC               */
+#define HPDMA1_TRIGGER_EXTIT10_SYNC               103U  /*!< HPDMA1 HW Trigger signal is EXTIT10_SYNC              */
+#define HPDMA1_TRIGGER_EXTIT11_SYNC               104U  /*!< HPDMA1 HW Trigger signal is EXTIT11_SYNC              */
+#define HPDMA1_TRIGGER_EXTIT12_SYNC               105U  /*!< HPDMA1 HW Trigger signal is EXTIT12_SYNC              */
+#define HPDMA1_TRIGGER_EXTIT13_SYNC               106U  /*!< HPDMA1 HW Trigger signal is EXTIT13_SYNC              */
+#define HPDMA1_TRIGGER_EXTIT14_SYNC               107U  /*!< HPDMA1 HW Trigger signal is EXTIT14_SYNC              */
+#define HPDMA1_TRIGGER_EXTIT15_SYNC               108U  /*!< HPDMA1 HW Trigger signal is EXTIT15_SYNC              */
+
+
+/* GPDMA1 triggers */
+#define GPDMA1_TRIGGER_DCMIPP_P0_FEND             0U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_FEND            */
+#define GPDMA1_TRIGGER_DCMIPP_P0_LEND             1U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_LEND            */
+#define GPDMA1_TRIGGER_DCMIPP_P0_HSYNC            2U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC           */
+#define GPDMA1_TRIGGER_DCMIPP_P0_VSYNC            3U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC           */
+
+#define GPDMA1_TRIGGER_DCMIPP_P1_FEND             4U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_FEND            */
+#define GPDMA1_TRIGGER_DCMIPP_P1_LEND             5U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_LEND            */
+#define GPDMA1_TRIGGER_DCMIPP_P1_HSYNC            6U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC           */
+#define GPDMA1_TRIGGER_DCMIPP_P1_VSYNC            7U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC           */
+
+#define GPDMA1_TRIGGER_DCMIPP_P2_FEND             8U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_FEND            */
+#define GPDMA1_TRIGGER_DCMIPP_P2_LEND             9U     /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_LEND            */
+#define GPDMA1_TRIGGER_DCMIPP_P2_HSYNC            10U    /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC           */
+#define GPDMA1_TRIGGER_DCMIPP_P2_VSYNC            11U    /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC           */
+
+#define GPDMA1_TRIGGER_DMA2D_CTC                  12U    /*!< GPDMA1 HW Trigger signal is DMA2D_CTC                 */
+#define GPDMA1_TRIGGER_DMA2D_TC                   13U    /*!< GPDMA1 HW Trigger signal is DMA2D_TC                  */
+#define GPDMA1_TRIGGER_DMA2D_TW                   14U    /*!< GPDMA1 HW Trigger signal is DMA2D_TW                  */
+
+#define GPDMA1_TRIGGER_JPEG_EOC                   15U    /*!< GPDMA1 HW Trigger signal is JPEG_EOC                  */
+#define GPDMA1_TRIGGER_JPEG_IFNF                  16U    /*!< GPDMA1 HW Trigger signal is JPEG_IFNF                 */
+#define GPDMA1_TRIGGER_JPEG_IFT                   17U    /*!< GPDMA1 HW Trigger signal is JPEG_IFT                  */
+#define GPDMA1_TRIGGER_JPEG_OFNE                  18U    /*!< GPDMA1 HW Trigger signal is JPEG_OFNE                 */
+#define GPDMA1_TRIGGER_JPEG_OFT                   19U    /*!< GPDMA1 HW Trigger signal is JPEG_OFT                  */
+
+#define GPDMA1_LCD_LI                             20U    /*!< GPDMA1 HW Trigger signal is LCD_LI                    */
+
+#define GPDMA1_TRIGGER_GPU2D1_GP_0                21U    /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_0               */
+#define GPDMA1_TRIGGER_GPU2D1_GP_1                22U    /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_1               */
+#define GPDMA1_TRIGGER_GPU2D1_GP_2                23U    /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_2               */
+#define GPDMA1_TRIGGER_GPU2D1_GP_3                24U    /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_3               */
+
+#define GPDMA1_TRIGGER_GFXTIM_3                   25U    /*!< GPDMA1 HW Trigger signal is GFXTIM_3                  */
+#define GPDMA1_TRIGGER_GFXTIM_2                   26U    /*!< GPDMA1 HW Trigger signal is GFXTIM_2                  */
+#define GPDMA1_TRIGGER_GFXTIM_1                   27U    /*!< GPDMA1 HW Trigger signal is GFXTIM_1                  */
+#define GPDMA1_TRIGGER_GFXTIM_0                   28U    /*!< GPDMA1 HW Trigger signal is GFXTIM_0                  */
+
+/* reserved                                       29U                                                               */
+
+#define GPDMA1_TRIGGER_LPTIM1_CH1                 30U    /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1                */
+#define GPDMA1_TRIGGER_LPTIM1_CH2                 31U    /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2                */
+#define GPDMA1_TRIGGER_LPTIM2_CH1                 32U    /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1                */
+#define GPDMA1_TRIGGER_LPTIM2_CH2                 33U    /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2                */
+#define GPDMA1_TRIGGER_LPTIM3_CH1                 34U    /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1                */
+#define GPDMA1_TRIGGER_LPTIM3_CH2                 35U    /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2                */
+#define GPDMA1_TRIGGER_LPTIM4_OUT                 36U    /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT                */
+#define GPDMA1_TRIGGER_LPTIM5_OUT                 37U    /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT                */
+
+/* reserved                                       38U                                                               */
+
+#define GPDMA1_TRIGGER_RTC_WKUP                   39U    /*!< GPDMA1 HW Trigger signal is RTC_WKUP                  */
+
+#define GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC     40U    /*!< GPDMA1 HW Trigger signal is IT_R_WUP_ASYNC            */
+#define GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC     41U    /*!< GPDMA1 HW Trigger signal is IT_T_WUP_ASYNC            */
+
+#define GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC   42U    /*!< GPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC  */
+
+/* reserved                                       43U                                                               */
+
+#define GPDMA1_TRIGGER_TIM1_TRGO                  44U    /*!< GPDMA1 HW Trigger signal is TIM1_TRGO                 */
+#define GPDMA1_TRIGGER_TIM1_TRGO2                 45U    /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2                */
+#define GPDMA1_TRIGGER_TIM2_TRGO                  46U    /*!< GPDMA1 HW Trigger signal is TIM2_TRGO                 */
+#define GPDMA1_TRIGGER_TIM3_TRGO                  47U    /*!< GPDMA1 HW Trigger signal is TIM3_TRGO                 */
+#define GPDMA1_TRIGGER_TIM4_TRGO                  48U    /*!< GPDMA1 HW Trigger signal is TIM4_TRGO                 */
+#define GPDMA1_TRIGGER_TIM5_TRGO                  49U    /*!< GPDMA1 HW Trigger signal is TIM5_TRGO                 */
+#define GPDMA1_TRIGGER_TIM6_TRGO                  50U    /*!< GPDMA1 HW Trigger signal is TIM6_TRGO                 */
+#define GPDMA1_TRIGGER_TIM7_TRGO                  51U    /*!< GPDMA1 HW Trigger signal is TIM7_TRGO                 */
+#define GPDMA1_TRIGGER_TIM8_TRGO                  52U    /*!< GPDMA1 HW Trigger signal is TIM8_TRGO                 */
+#define GPDMA1_TRIGGER_TIM8_TRGO2                 53U    /*!< GPDMA1 HW Trigger signal is TIM8_TRGO2                */
+
+/* reserved                                       54U                                                               */
+/* reserved                                       55U                                                               */
+/* reserved                                       56U                                                               */
+
+#define GPDMA1_TRIGGER_TIM12_TRGO                 57U    /*!< GPDMA1 HW Trigger signal is TIM12_TRGO                */
+#define GPDMA1_TRIGGER_TIM15_TRGO                 58U    /*!< GPDMA1 HW Trigger signal is TIM15_TRGO                */
+
+/* reserved                                       59U                                                               */
+
+#define GPDMA1_TRIGGER_HPDMA1_CH0_TCF             60U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH1_TCF             61U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH2_TCF             62U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH3_TCF             63U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH4_TCF             64U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH5_TCF             65U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH6_TCF             66U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH7_TCF             67U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH8_TCF             68U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH9_TCF             69U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF            */
+#define GPDMA1_TRIGGER_HPDMA1_CH10_TCF            70U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF           */
+#define GPDMA1_TRIGGER_HPDMA1_CH11_TCF            71U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF           */
+#define GPDMA1_TRIGGER_HPDMA1_CH12_TCF            72U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF           */
+#define GPDMA1_TRIGGER_HPDMA1_CH13_TCF            73U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF           */
+#define GPDMA1_TRIGGER_HPDMA1_CH14_TCF            74U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF           */
+#define GPDMA1_TRIGGER_HPDMA1_CH15_TCF            75U    /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF           */
+
+#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF             76U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF             77U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF             78U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF             79U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF             80U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF             81U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF             82U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF             83U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF             84U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF             85U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF            */
+#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF            86U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF           */
+#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF            87U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF           */
+#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF            88U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF           */
+#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF            89U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF           */
+#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF            90U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF           */
+#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF            91U    /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF           */
+
+/* reserved                                       92U                                                               */
+
+#define GPDMA1_TRIGGER_EXTIT0_SYNC                93U    /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT1_SYNC                94U    /*!< GPDMA1 HW Trigger signal is EXTIT1_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT2_SYNC                95U    /*!< GPDMA1 HW Trigger signal is EXTIT2_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT3_SYNC                96U    /*!< GPDMA1 HW Trigger signal is EXTIT3_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT4_SYNC                97U    /*!< GPDMA1 HW Trigger signal is EXTIT4_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT5_SYNC                98U    /*!< GPDMA1 HW Trigger signal is EXTIT5_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT6_SYNC                99U    /*!< GPDMA1 HW Trigger signal is EXTIT6_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT7_SYNC                100U   /*!< GPDMA1 HW Trigger signal is EXTIT7_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT8_SYNC                101U   /*!< GPDMA1 HW Trigger signal is EXTIT8_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT9_SYNC                102U   /*!< GPDMA1 HW Trigger signal is EXTIT9_SYNC               */
+#define GPDMA1_TRIGGER_EXTIT10_SYNC               103U   /*!< GPDMA1 HW Trigger signal is EXTIT10_SYNC              */
+#define GPDMA1_TRIGGER_EXTIT11_SYNC               104U   /*!< GPDMA1 HW Trigger signal is EXTIT11_SYNC              */
+#define GPDMA1_TRIGGER_EXTIT12_SYNC               105U   /*!< GPDMA1 HW Trigger signal is EXTIT12_SYNC              */
+#define GPDMA1_TRIGGER_EXTIT13_SYNC               106U   /*!< GPDMA1 HW Trigger signal is EXTIT13_SYNC              */
+#define GPDMA1_TRIGGER_EXTIT14_SYNC               107U   /*!< GPDMA1 HW Trigger signal is EXTIT14_SYNC              */
+#define GPDMA1_TRIGGER_EXTIT15_SYNC               108U   /*!< GPDMA1 HW Trigger signal is EXTIT15_SYNC              */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Node_Type DMAEx Node Type
+  * @brief    DMAEx Node Type
+  * @{
+  */
+#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type      */
+#define DMA_GPDMA_2D_NODE     (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR)     /*!< Defines the GPDMA 2 dimension addressing node type */
+#define DMA_HPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the HPDMA linear addressing node type      */
+#define DMA_HPDMA_2D_NODE     (DMA_CHANNEL_TYPE_HPDMA | DMA_CHANNEL_TYPE_2D_ADDR)     /*!< Defines the HPDMA 2 dimension addressing node type */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port
+  * @brief    DMAEx Linked-List Allocated Port
+  * @{
+  */
+#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */
+#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode
+  * @brief    DMAEx Link Step Mode
+  * @{
+  */
+#define DMA_LSM_FULL_EXECUTION  0x00000000U /*!< Channel is executed for the full linked-list */
+#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief    DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions
+  * @brief    Linked-List Initialization and De-Initialization Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
+  * @brief    Linked-List IO Operation Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions
+  * @brief    Linked-List Management Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+                                           DMA_NodeTypeDef *const pNode);
+HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+                                               DMA_NodeTypeDef const *const pNode);
+
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
+                                            DMA_NodeTypeDef *const pPrevNode,
+                                            DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
+                                                 DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
+                                                 DMA_NodeTypeDef *const pNewNode);
+
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
+                                            DMA_NodeTypeDef *const pNode);
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
+                                             DMA_NodeTypeDef *const pOldNode,
+                                             DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
+                                                  DMA_NodeTypeDef *const pNewNode);
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
+                                                  DMA_NodeTypeDef *const pNewNode);
+
+HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
+                                         DMA_NodeTypeDef const *const pPrevNode,
+                                         DMA_QListTypeDef *const pDestQList);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
+                                              DMA_QListTypeDef *const pDestQList);
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
+                                              DMA_QListTypeDef *const pDestQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
+                                                       DMA_NodeTypeDef *const pFirstCircularNode);
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList);
+
+HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
+                                       DMA_QListTypeDef *const pQList);
+HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions
+  * @brief    Data Handling, Repeated Block and Trigger Configuration Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
+                                               DMA_DataHandlingConfTypeDef const *const pConfigDataHandling);
+HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
+                                          DMA_TriggerConfTypeDef const *const pConfigTrigger);
+HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
+                                              DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock);
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions
+  * @brief    Suspend and Resume Operation Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma);
+HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function
+  * @brief    FIFO Status Function
+  * @{
+  */
+uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Types DMAEx Private Types
+  * @brief    DMAEx Private Types
+  * @{
+  */
+
+/**
+  * @brief DMA Node in Queue Information Structure Definition.
+  */
+typedef struct
+{
+  uint32_t cllr_offset;       /* CLLR register offset  */
+
+  uint32_t previousnode_addr; /* Previous node address */
+
+  uint32_t currentnode_pos;   /* Current node position */
+
+  uint32_t currentnode_addr;  /* Current node address  */
+
+  uint32_t nextnode_addr;     /* Next node address     */
+
+} DMA_NodeInQInfoTypeDef;
+/**
+  * @}
+  */
+
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Constants DMAEx Private Constants
+  * @brief    DMAEx Private Constants
+  * @{
+  */
+#define DMA_LINKEDLIST                  (0x0080U) /* DMA channel linked-list mode          */
+
+#define DMA_CHANNEL_TYPE_LINEAR_ADDR    (0x0001U) /* DMA channel linear addressing mode    */
+#define DMA_CHANNEL_TYPE_2D_ADDR        (0x0002U) /* DMA channel 2D addressing mode        */
+#define DMA_CHANNEL_TYPE_GPDMA          (0x0020U) /* GPDMA channel node                    */
+#define DMA_CHANNEL_TYPE_HPDMA          (0x0040U) /* HPDMA channel node                    */
+
+#define NODE_TYPE_MASK                  (0x00FFU) /* DMA channel node type                 */
+#define NODE_CLLR_IDX                   (0x0700U) /* DMA channel node CLLR index mask      */
+#define NODE_CLLR_IDX_POS               (0x0008U) /* DMA channel node CLLR index position  */
+
+#define NODE_MAXIMUM_SIZE               (0x0008U) /* Amount of registers of the node       */
+
+#define NODE_STATIC_FORMAT              (0x0000U) /* DMA channel node static format        */
+#define NODE_DYNAMIC_FORMAT             (0x0001U) /* DMA channel node dynamic format       */
+
+#define UPDATE_CLLR_POSITION            (0x0000U) /* DMA channel update CLLR position      */
+#define UPDATE_CLLR_VALUE               (0x0001U) /* DMA channel update CLLR value         */
+
+#define LASTNODE_ISNOT_CIRCULAR         (0x0000U) /* Last node is not first circular node  */
+#define LASTNODE_IS_CIRCULAR            (0x0001U) /* Last node is first circular node      */
+
+#define QUEUE_TYPE_STATIC               (0x0000U) /* DMA channel static queue              */
+#define QUEUE_TYPE_DYNAMIC              (0x0001U) /* DMA channel dynamic queue             */
+
+#define NODE_CTR1_DEFAULT_OFFSET        (0x0000U) /* CTR1 default offset                   */
+#define NODE_CTR2_DEFAULT_OFFSET        (0x0001U) /* CTR2 default offset                   */
+#define NODE_CBR1_DEFAULT_OFFSET        (0x0002U) /* CBR1 default offset                   */
+#define NODE_CSAR_DEFAULT_OFFSET        (0x0003U) /* CSAR default offset                   */
+#define NODE_CDAR_DEFAULT_OFFSET        (0x0004U) /* CDAR default offset                   */
+#define NODE_CTR3_DEFAULT_OFFSET        (0x0005U) /* CTR3 2D addressing default offset     */
+#define NODE_CBR2_DEFAULT_OFFSET        (0x0006U) /* CBR2 2D addressing default offset     */
+#define NODE_CLLR_2D_DEFAULT_OFFSET     (0x0007U) /* CLLR 2D addressing default offset     */
+#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
+
+#define DMA_BURST_ADDR_OFFSET_MIN       (-8192L)  /* DMA burst minimum address offset      */
+#define DMA_BURST_ADDR_OFFSET_MAX       (8192L)   /* DMA burst maximum address offset      */
+#define DMA_BLOCK_ADDR_OFFSET_MIN       (-65536L) /* DMA block minimum address offset      */
+#define DMA_BLOCK_ADDR_OFFSET_MAX       (65536L)  /* DMA block maximum address offset      */
+/**
+  * @}
+  */
+
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
+  * @brief    DMAEx Private Macros
+  * @{
+  */
+#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT)              \
+  (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \
+   ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT)    || \
+   ((ALIGNMENT) == DMA_DATA_PACK))
+
+#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \
+  (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD | \
+                    DMA_EXCHANGE_DEST_WORD))) == 0U)
+
+#define IS_DMA_REPEAT_COUNT(COUNT) \
+  (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos)))
+
+#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET)     \
+  (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \
+   ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX))
+
+#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET)     \
+  (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \
+   ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX))
+
+#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \
+  (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U)
+
+#define IS_DMA_LINK_STEP_MODE(MODE)      \
+  (((MODE) == DMA_LSM_FULL_EXECUTION) || \
+   ((MODE) == DMA_LSM_1LINK_EXECUTION))
+
+#define IS_DMA_TRIGGER_MODE(MODE)                   \
+  (((MODE) == DMA_TRIGM_BLOCK_TRANSFER)          || \
+   ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \
+   ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER)       || \
+   ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER))
+
+#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE)    \
+  (((MODE) == DMA_TCEM_BLOCK_TRANSFER)          || \
+   ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
+   ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER)   || \
+   ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
+
+#define IS_DMA_LINKEDLIST_MODE(MODE)    \
+  (((MODE) == DMA_LINKEDLIST_NORMAL) || \
+   ((MODE) == DMA_LINKEDLIST_CIRCULAR))
+
+#define IS_DMA_TRIGGER_POLARITY(POLARITY)      \
+  (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \
+   ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
+   ((POLARITY) == DMA_TRIG_POLARITY_FALLING))
+
+#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \
+  ((TRIGGER) <= HPDMA1_TRIGGER_EXTIT15_SYNC)
+
+#define IS_DMA_NODE_TYPE(TYPE)          \
+  (((TYPE) == DMA_GPDMA_LINEAR_NODE) || \
+   ((TYPE) == DMA_GPDMA_2D_NODE) || \
+   ((TYPE) == DMA_HPDMA_LINEAR_NODE) || \
+   ((TYPE) == DMA_HPDMA_2D_NODE))
+/**
+  * @}
+  */
+
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief    DMAEx Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32N6xx_HAL_DMA_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dts.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dts.h
new file mode 100644
index 000000000..3f2cd81f3
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_dts.h
@@ -0,0 +1,356 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_dts.h
+  * @author  MCD Application Team
+  * @brief   Header file of DTS HAL module.
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32N6xx_HAL_DTS_H
+#define STM32N6xx_HAL_DTS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DTS
+  * @{
+  */
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DTS_Exported_Types  DTS Exported Types
+  * @{
+  */
+/**
+  * @brief  HAL DTS states definition
+  */
+typedef enum
+{
+  HAL_DTS_STATE_RESET        = 0x00U, /*!< DTS not initialized */
+  HAL_DTS_STATE_READY        = 0x01U, /*!< DTS initialized and ready for use */
+  HAL_DTS_STATE_RUNNING_0    = 0x02U, /*!< DTS temperature measure in progress on sensor 0 */
+  HAL_DTS_STATE_RUNNING_1    = 0x03U, /*!< DTS temperature measure in progress on sensor 1 */
+  HAL_DTS_STATE_RUNNING_BOTH = 0x04U  /*!< DTS temperature measure in progress on both sensors */
+} HAL_DTS_StateTypeDef;
+
+/**
+  * @brief  DTS sensors definition
+  */
+typedef enum
+{
+  DTS_SENSOR_0 = 0x00U, /*!< DTS sensor 0 */
+  DTS_SENSOR_1 = 0x01U, /*!< DTS sensor 1 */
+} HAL_DTS_Sensor;
+
+/**
+  * @brief  DTS handle structure definition
+  */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+typedef struct __DTS_HandleTypeDef
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+typedef struct
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+{
+  DTS_TypeDef               *Instance;        /*!< DTS instance */
+  __IO HAL_DTS_StateTypeDef  State;           /*!< DTS state */
+  __IO uint32_t              ErrorCode;       /*!< DTS error code */
+  uint32_t                   SensorMode[2U];  /*!< DTS sensor modes */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+  void (*MspInitCallback)(struct __DTS_HandleTypeDef *hdts);     /*!< DTS MSP init callback */
+  void (*MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts);   /*!< DTS MSP de-init callback */
+  void (*TemperatureCallback)(struct __DTS_HandleTypeDef *hdts,
+                              HAL_DTS_Sensor Sensor);            /*!< DTS temperature callback */
+  void (*AlarmACallback)(struct __DTS_HandleTypeDef *hdts,
+                         HAL_DTS_Sensor Sensor);                 /*!< DTS alarm A callback */
+  void (*AlarmBCallback)(struct __DTS_HandleTypeDef *hdts,
+                         HAL_DTS_Sensor Sensor);                 /*!< DTS alarm B callback */
+  void (*ErrorCallback)(struct __DTS_HandleTypeDef *hdts,
+                        HAL_DTS_Sensor Sensor);                  /*!< DTS error callback */
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+} DTS_HandleTypeDef;
+
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  DTS callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DTS_MSPINIT_CB_ID   = 0x00U, /*!< DTS MSP init callback ID */
+  HAL_DTS_MSPDEINIT_CB_ID = 0x01U  /*!< DTS MSP de-init callback ID */
+} HAL_DTS_CallbackIDTypeDef;
+
+/**
+  * @brief  DTS sensor callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DTS_SENSOR_TEMPERATURE_CB_ID = 0x00U, /*!< DTS sensor temperature callback ID */
+  HAL_DTS_SENSOR_ALARMA_CB_ID      = 0x01U, /*!< DTS sensor alarm A callback ID */
+  HAL_DTS_SENSOR_ALARMB_CB_ID      = 0x02U, /*!< DTS sensor alarm B callback ID */
+  HAL_DTS_SENSOR_ERROR_CB_ID       = 0x03U, /*!< DTS sensor error callback ID */
+} HAL_DTS_SensorCallbackIDTypeDef;
+
+/**
+  * @brief  DTS callback pointers definition
+  */
+typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts);
+typedef void (*pDTS_SensorCallbackTypeDef)(DTS_HandleTypeDef *hdts, HAL_DTS_Sensor Sensor);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
+/**
+  * @brief  DTS sensor configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Mode;       /*!< Sensor mode.
+                            This parameter can be a value of @ref DTS_SensorMode */
+  uint32_t Resolution; /*!< Sensor resolution.
+                            This parameter can be a value of @ref DTS_SensorResolution */
+  uint32_t Trigger;    /*!< Sensor trigger.
+                            This parameter can be a value of @ref DTS_SensorTrigger.
+                            @note This parameter is used only if Mode is set to DTS_SENSOR_MODE_TRIGGER */
+} DTS_SensorConfigTypeDef;
+
+/**
+  * @brief  DTS alarm configuration structure definition
+  */
+typedef struct
+{
+  FunctionalState Enable;     /*!< Alarm enable/disable */
+  float_t         Threshold;  /*!< Alarm threshold in celsius degree.
+                                   This parameter must be a number between Min_Data = -40 and Max_Data = 125 */
+  float_t         Hysteresis; /*!< Alarm hysteresis in celsius degree.
+                                   This parameter must be a number between Min_Data = -40 and Max_Data = 125 */
+} DTS_AlarmConfigTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DTS_Exported_Constants  DTS Exported Constants
+  * @{
+  */
+
+/** @defgroup DTS_ErrorCode DTS error code
+  * @{
+  */
+#define HAL_DTS_ERROR_NONE                 0x00000000U  /*!< No error */
+#define HAL_DTS_ERROR_INVALID_PARAM        0x00000001U  /*!< Invalid parameter */
+#define HAL_DTS_ERROR_INVALID_STATE        0x00000002U  /*!< Invalid state */
+#define HAL_DTS_ERROR_INVALID_SENSOR_MODE  0x00000004U  /*!< Invalid sensor mode */
+#define HAL_DTS_ERROR_INVALID_SAMPLE       0x00000008U  /*!< Invalid sample */
+#define HAL_DTS_ERROR_FAULT                0x00000010U  /*!< Fault */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+#define HAL_DTS_ERROR_INVALID_CALLBACK     0x00000020U  /*!< Invalid callback error */
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup DTS_SensorMode DTS sensor mode
+  * @{
+  */
+#define DTS_SENSOR_MODE_DISABLE     0x00000000U /*!< No acquisition */
+#define DTS_SENSOR_MODE_SINGLE      0x00000106U /*!< Single acquisition */
+#define DTS_SENSOR_MODE_CONTINUOUS  0x0000010AU /*!< Continuous acquisitions */
+#define DTS_SENSOR_MODE_TRIGGER     0x00000102U /*!< Acquisition with trigger */
+/**
+  * @}
+  */
+
+/** @defgroup DTS_SensorResolution DTS sensor resolution
+  * @{
+  */
+#define DTS_SENSOR_RESOLUTION_12BITS  0x00000001U /*!< Sensor resolution of 12 bits */
+#define DTS_SENSOR_RESOLUTION_10BITS  0x00000021U /*!< Sensor resolution of 10 bits */
+#define DTS_SENSOR_RESOLUTION_8BITS   0x00000041U /*!< Sensor resolution of 8 bits */
+/**
+  * @}
+  */
+
+/** @defgroup DTS_SensorTrigger DTS sensor trigger
+  * @{
+  */
+#define DTS_SENSOR_TRIGGER_LPTIM4_OUT  0x00010000U /*!< LPTIM4 output signal */
+#define DTS_SENSOR_TRIGGER_LPTIM2_CH1  0x00020000U /*!< LPTIM2 channel 1 signal */
+#define DTS_SENSOR_TRIGGER_LPTIM3_CH1  0x00030000U /*!< LPTIM3 channel 1 signal */
+#define DTS_SENSOR_TRIGGER_EXTI13      0x00040000U /*!< EXTI13 signal */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ---------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DTS_Exported_Macros  DTS Exported Macros
+  * @{
+  */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{                                             \
+                                                      (__HANDLE__)->State = HAL_DTS_STATE_RESET; \
+                                                      (__HANDLE__)->MspInitCallback = NULL;      \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                    } while(0)
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
+#define IS_DTS_SENSOR_MODE(PARAM) (((PARAM) == DTS_SENSOR_MODE_DISABLE)    || \
+                                   ((PARAM) == DTS_SENSOR_MODE_SINGLE)     || \
+                                   ((PARAM) == DTS_SENSOR_MODE_CONTINUOUS) || \
+                                   ((PARAM) == DTS_SENSOR_MODE_TRIGGER))
+
+#define IS_DTS_SENSOR_RESOLUTION(PARAM) (((PARAM) == DTS_SENSOR_RESOLUTION_12BITS) || \
+                                         ((PARAM) == DTS_SENSOR_RESOLUTION_10BITS) || \
+                                         ((PARAM) == DTS_SENSOR_RESOLUTION_8BITS))
+
+#define IS_DTS_SENSOR_TRIGGER(PARAM) (((PARAM) == DTS_SENSOR_TRIGGER_LPTIM4_OUT) || \
+                                      ((PARAM) == DTS_SENSOR_TRIGGER_LPTIM2_CH1) || \
+                                      ((PARAM) == DTS_SENSOR_TRIGGER_LPTIM3_CH1) || \
+                                      ((PARAM) == DTS_SENSOR_TRIGGER_EXTI13))
+
+#define IS_DTS_ALARM_PARAM(PARAM) ((-40.0f <= (PARAM)) && ((PARAM) <= 125.0f))
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+
+/** @addtogroup DTS_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions */
+/** @addtogroup DTS_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
+HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef        *hdts,
+                                           HAL_DTS_CallbackIDTypeDef CallbackID,
+                                           pDTS_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef        *hdts,
+                                             HAL_DTS_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_DTS_RegisterSensorCallback(DTS_HandleTypeDef              *hdts,
+                                                 HAL_DTS_SensorCallbackIDTypeDef CallbackID,
+                                                 pDTS_SensorCallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_DTS_UnRegisterSensorCallback(DTS_HandleTypeDef              *hdts,
+                                                   HAL_DTS_SensorCallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Temperature measurement functions */
+/** @addtogroup DTS_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_DTS_ConfigSensor(DTS_HandleTypeDef       *hdts,
+                                       HAL_DTS_Sensor           Sensor,
+                                       DTS_SensorConfigTypeDef *pSensorParams);
+HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts,
+                                HAL_DTS_Sensor     Sensor);
+HAL_StatusTypeDef HAL_DTS_PollForTemperature(DTS_HandleTypeDef *hdts,
+                                             HAL_DTS_Sensor     Sensor,
+                                             uint32_t              Timeout);
+HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts,
+                                         HAL_DTS_Sensor     Sensor,
+                                         float_t           *pTemperature);
+HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts,
+                               HAL_DTS_Sensor     Sensor);
+HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts,
+                                   HAL_DTS_Sensor     Sensor);
+HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts,
+                                  HAL_DTS_Sensor     Sensor);
+void              HAL_DTS_TemperatureCallback(DTS_HandleTypeDef *hdts,
+                                              HAL_DTS_Sensor     Sensor);
+HAL_StatusTypeDef HAL_DTS_GetExtremeTemperatures(DTS_HandleTypeDef *hdts,
+                                                 HAL_DTS_Sensor     Sensor,
+                                                 float_t           *pMin,
+                                                 float_t           *pMax);
+HAL_StatusTypeDef HAL_DTS_ConfigSampleCounter(DTS_HandleTypeDef *hdts,
+                                              FunctionalState    Enable,
+                                              FunctionalState    Clear,
+                                              FunctionalState    Hold);
+HAL_StatusTypeDef HAL_DTS_GetSampleCounterValue(DTS_HandleTypeDef *hdts,
+                                                uint32_t          *pNumber);
+HAL_StatusTypeDef HAL_DTS_ConfigSampleDiscard(DTS_HandleTypeDef *hdts,
+                                              FunctionalState    Status);
+/**
+  * @}
+  */
+
+/* Alarms functions */
+/** @addtogroup DTS_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_DTS_ConfigAlarmA(DTS_HandleTypeDef            *hdts,
+                                       HAL_DTS_Sensor                Sensor,
+                                       const DTS_AlarmConfigTypeDef *pAlarmParams);
+HAL_StatusTypeDef HAL_DTS_ConfigAlarmB(DTS_HandleTypeDef            *hdts,
+                                       HAL_DTS_Sensor                Sensor,
+                                       const DTS_AlarmConfigTypeDef *pAlarmParams);
+void              HAL_DTS_AlarmACallback(DTS_HandleTypeDef *hdts,
+                                         HAL_DTS_Sensor     Sensor);
+void              HAL_DTS_AlarmBCallback(DTS_HandleTypeDef *hdts,
+                                         HAL_DTS_Sensor     Sensor);
+/**
+  * @}
+  */
+
+/* Generic functions */
+/** @addtogroup DTS_Exported_Functions_Group4
+  * @{
+  */
+void                 HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);
+void                 HAL_DTS_ErrorCallback(DTS_HandleTypeDef *hdts,
+                                           HAL_DTS_Sensor     Sensor);
+HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts);
+uint32_t             HAL_DTS_GetError(const DTS_HandleTypeDef *hdts);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_DTS_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_eth.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_eth.h
new file mode 100644
index 000000000..d81e87aa4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_eth.h
@@ -0,0 +1,2103 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_eth.h
+  * @author  MCD Application Team
+  * @brief   Header file of ETH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_ETH_H
+#define STM32N6xx_HAL_ETH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined(ETH1)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ETH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* ETH Multi-Queue feature is supported by HW */
+#define ETH_MULTIQUEUE_SUPPORTED
+
+#ifndef ETH_MTL_TX_Q_CNT
+#define ETH_MTL_TX_Q_CNT         2U
+#endif /* ETH_MTL_TX_Q_CNT */
+
+#ifndef ETH_MTL_RX_Q_CNT
+#define ETH_MTL_RX_Q_CNT         2U
+#endif /* ETH_MTL_RX_Q_CNT */
+
+#ifndef ETH_DMA_CH_CNT
+#define ETH_DMA_CH_CNT         ETH_MTL_TX_Q_CNT
+#endif /* ETH_DMA_CH_CNT */
+
+#ifndef ETH_DMA_TX_CH_CNT
+#define ETH_DMA_TX_CH_CNT         2U
+#endif /* ETH_DMA_TX_CH_CNT */
+
+#ifndef ETH_DMA_RX_CH_CNT
+#define ETH_DMA_RX_CH_CNT         2U
+#endif /* ETH_DMA_RX_CH_CNT */
+
+#ifndef ETH_TX_DESC_CNT
+#define ETH_TX_DESC_CNT         4U
+#endif /* ETH_TX_DESC_CNT */
+
+#ifndef ETH_RX_DESC_CNT
+#define ETH_RX_DESC_CNT         4U
+#endif /* ETH_RX_DESC_CNT */
+
+#ifndef ETH_SWRESET_TIMEOUT
+#define ETH_SWRESET_TIMEOUT     500U
+#endif /* ETH_SWRESET_TIMEOUT */
+
+#ifndef ETH_MDIO_BUS_TIMEOUT
+#define ETH_MDIO_BUS_TIMEOUT    1000U
+#endif /* ETH_MDIO_BUS_TIMEOUT */
+
+#ifndef ETH_MAC_US_TICK
+#define ETH_MAC_US_TICK         1000000U
+#endif /* ETH_MAC_US_TICK */
+
+/*********************** Descriptors struct def section ************************/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ETH DMA Descriptor structure definition
+  */
+typedef struct
+{
+  __IO uint32_t DESC0;
+  __IO uint32_t DESC1;
+  __IO uint32_t DESC2;
+  __IO uint32_t DESC3;
+  uint32_t BackupAddr0; /* used to store rx buffer 1 address */
+  uint32_t BackupAddr1; /* used to store rx buffer 2 address */
+} ETH_DMADescTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Buffers List structure definition
+  */
+typedef struct __ETH_BufferTypeDef
+{
+  uint8_t *buffer;                /*<! buffer address */
+
+  uint32_t len;                   /*<! buffer length */
+
+  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
+} ETH_BufferTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  DMA Transmit Descriptors Wrapper structure definition
+  */
+typedef struct
+{
+  uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
+
+  uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
+
+  uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
+
+  uint32_t *CurrentPacketAddress;           /*<! Current transmit packet addresses */
+
+  uint32_t BuffersInUse;                   /*<! Buffers in Use */
+
+  uint32_t releaseIndex;                  /*<! Release index */
+} ETH_TxDescListTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  Transmit Packet Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t TxDMACh;                 /*!< Sets the Tx Queue/Channel which will transmit the packet */
+
+  uint32_t Attributes;              /*!< Tx packet HW features capabilities.
+                                         This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
+
+  uint32_t Length;                  /*!< Total packet length   */
+
+  ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
+
+  uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
+                                         This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
+
+  uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
+
+  uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
+
+  uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
+                                        This parameter can be a value from 0x0 to 0x3FFF */
+
+  uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
+                                        This parameter can be a value from 0x0 to 0x3FFFF */
+
+  uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
+                                        This parameter can be a value from 0x5 to 0xF */
+
+  uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
+                                        This parameter can be a value from 0x0 to 0xFFFF*/
+
+  uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
+
+  uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
+                                        This parameter can be a value from 0x0 to 0x3FFFF */
+
+  uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
+
+  void *pData;                     /*!< Specifies Application packet pointer to save   */
+
+} ETH_TxPacketConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Timestamp structure definition
+  */
+typedef struct
+{
+  uint32_t TimeStampLow;
+  uint32_t TimeStampHigh;
+
+} ETH_TimeStampTypeDef;
+/**
+  *
+  */
+
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  ETH Timeupdate structure definition
+  */
+typedef struct
+{
+  uint32_t Seconds;
+  uint32_t NanoSeconds;
+} ETH_TimeTypeDef;
+/**
+  *
+  */
+#endif  /* HAL_ETH_USE_PTP */
+
+/**
+  * @brief  DMA Receive Descriptors Wrapper structure definition
+  */
+typedef struct
+{
+  uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
+
+  uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
+                                             If 0, DMA will not generate the Rx complete interrupt. */
+
+  uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */
+
+  uint32_t RxDescCnt;                 /*<! Number of descriptors . */
+
+  uint32_t RxDataLength;              /*<! Received Data Length. */
+
+  uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */
+
+  uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */
+
+  uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */
+
+  ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */
+
+  void *pRxStart;                     /*<! Pointer to the first buff. */
+
+  void *pRxEnd;                       /*<! Pointer to the last buff. */
+
+} ETH_RxDescListTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH MAC Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t
+  SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
+                                                     This parameter can be a value of @ref ETH_Source_Addr_Control */
+
+  FunctionalState
+  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
+
+  uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
+                                                     This parameter can be a value of @ref ETH_Inter_Packet_Gap */
+
+  FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
+
+  FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
+
+  FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
+
+  FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
+
+  FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path.*/
+
+  FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path.*/
+
+  FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
+                                                           When enabled, the MAC allows jumbo packets of 9,018 bytes
+                                                           without reporting a giant packet error */
+
+  FunctionalState  PortSelect;                  /*!< Sets the Port Select
+                                                            When disabled, the line speed is for 1000Mbps operations
+                                                            When enabled, it is for 10 or 100Mbps operations*/
+
+  uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
+                                                           This parameter can be a value of @ref ETH_Speed */
+
+  uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */
+
+  FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
+
+  FunctionalState
+  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
+
+  FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
+
+  FunctionalState
+  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
+
+  FunctionalState
+  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
+
+  uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
+                                                        This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+  FunctionalState
+  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
+
+  uint32_t
+  PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
+                                                           This parameter can be a value of @ref ETH_Preamble_Length */
+
+  FunctionalState
+  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
+
+  FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
+
+  FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
+
+  uint32_t
+  GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
+                                                    greater than the value programmed in this field in units of bytes
+                                                    This parameter must be a number between
+                                                    Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
+
+  FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
+
+  uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
+                                                           This parameter can be a value from 0x0 to 0xFF */
+
+  FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
+
+  uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
+                                                        This parameter can be a value of @ref ETH_Watchdog_Timeout */
+
+  uint32_t
+  PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
+                                                   This parameter must be a number between
+                                                   Min_Data = 0x0 and Max_Data = 0xFFFF.*/
+
+  FunctionalState
+  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
+
+  uint32_t
+  PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
+                                                   This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+  FunctionalState
+  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
+                                                   or the MAC back pressure operation in Half Duplex mode */
+
+  FunctionalState
+  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
+
+  FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
+                                                  and disables its transmitter for a specified (Pause) time */
+
+  FunctionalState  PacketBurst;                 /*!< Enables or disables the MAC to allow packet bursting during transmission
+                                                      in the GMII Halfduplex mode */
+
+} ETH_MACConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH DMA Configuration Structure definition
+  */
+typedef struct
+{
+  FunctionalState         PBLx8Mode;                    /*!< Enables or disables the PBL multiplication by eight. */
+
+  uint32_t
+  TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+                                                     This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+  FunctionalState
+  SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
+                                 Packet of Transmit data even before obtaining the status for the first one. */
+  FunctionalState         TCPSegmentation;              /*!< Enables or disables the TCP Segmentation */
+
+  uint32_t                DescriptorSkipLength;         /*!< Sets the Descriptor Skip Length */
+
+  FunctionalState         FlushRxPacket;                /*!< Enables or disables the Rx Packet Flush */
+
+  uint32_t
+  RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+                                                    This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+  uint32_t                MaximumSegmentSize;           /*!< Sets the maximum segment size that should be used while segmenting the packet
+                                                             This parameter can be a value from 0x40 to 0x3FFF */
+} DMAChannelInstanceTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH DMA Configuration Structure definition
+  */
+typedef struct
+{
+  DMAChannelInstanceTypeDef DMACh[ETH_DMA_CH_CNT];          /*!< DMA Channel x Configuration */
+
+  uint32_t                  TransmitArbitrationAlgorithm;  /*!< Speicifies the arbitration algorithm for the Transmit side */
+
+  FunctionalState           AddressAlignedBeats;           /*!< Enables or disables the AHB Master interface address aligned
+                                                              burst transfers on Read and Write channels  */
+  uint32_t                  BurstMode;                     /*!< Sets the AHB Master interface burst transfers.
+                                                               This parameter can be a value of @ref ETH_Burst_Mode */
+  uint32_t                  RxOSRLimit;                    /*!< Sets the maximum outstanding request on the AXI read interface. */
+
+  uint32_t                  TxOSRLimit;                    /*!< Sets the maximum outstanding request on the AXI write interface. */
+
+  uint32_t                  AXIBLENMaxSize;                 /*!< Sets the maximum BLEN max size that should be used on th AXI interface to initiate burst transfers of specified lengths */
+
+  FunctionalState           TransmitPriority;               /*!< Sets Transmit priority over Receive */
+
+} ETH_DMAConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Media Interfaces enum definition
+  */
+typedef enum
+{
+  HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
+  HAL_ETH_RMII_MODE            = 0x01U,   /*!<   Reduced Media Independent Interface       */
+  HAL_ETH_GMII_MODE            = 0x02U,   /*!<  Giga Media Independent Interface       */
+  HAL_ETH_RGMII_MODE           = 0x03U    /*!<  Reduced Giga Media Independent Interface       */
+} ETH_MediaInterfaceTypeDef;
+/**
+  *
+  */
+
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  HAL ETH PTP Update type enum definition
+  */
+typedef enum
+{
+  HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,   /*!<  PTP positive time update       */
+  HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U   /*!<  PTP negative time update       */
+} ETH_PtpUpdateTypeDef;
+/**
+  *
+  */
+#endif  /* HAL_ETH_USE_PTP */
+
+/**
+  * @brief  ETH Init Structure definition
+  */
+typedef struct
+{
+  uint8_t
+  *MACAddr;                                     /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+  ETH_MediaInterfaceTypeDef   MediaInterface;   /*!< Selects the MII/RMII/RGMII interface. */
+
+  ETH_DMADescTypeDef
+  *TxDesc[ETH_DMA_TX_CH_CNT];                   /*!< Provides the address of the first DMA CH Tx descriptor in the list */
+
+  ETH_DMADescTypeDef
+  *RxDesc[ETH_DMA_RX_CH_CNT];                   /*!< Provides the address of the first DMA Rx CH descriptor in the list */
+
+  uint32_t                    RxBuffLen;        /*!< Provides the length of Rx buffers size */
+
+} ETH_InitTypeDef;
+/**
+  *
+  */
+
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  ETH PTP Init Structure definition
+  */
+typedef struct
+{
+  uint32_t                    AV8021ASMEN;                  /*!< Enable AV 802.1AS Mode */
+  uint32_t                    Timestamp;                    /*!< Enable Timestamp */
+  uint32_t                    TimestampUpdateMode;          /*!< Fine or Coarse Timestamp Update */
+  uint32_t                    TimestampInitialize;          /*!< Initialize Timestamp */
+  uint32_t                    TimestampUpdate;              /*!< Timestamp Update */
+  uint32_t                    TimestampAddendUpdate;        /*!< Timestamp Addend Update */
+  uint32_t                    TimestampAll;                 /*!< Enable Timestamp for All Packets */
+  uint32_t                    TimestampRolloverMode;        /*!< Timestamp Digital or Binary Rollover Control */
+  uint32_t                    TimestampV2;                  /*!< Enable PTP Packet Processing for Version 2 Format */
+  uint32_t                    TimestampEthernet;            /*!< Enable Processing of PTP over Ethernet Packets */
+  uint32_t                    TimestampIPv6;                /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
+  uint32_t                    TimestampIPv4;                /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
+  uint32_t                    TimestampEvent;               /*!< Enable Timestamp Snapshot for Event Messages */
+  uint32_t                    TimestampMaster;              /*!< Enable Timestamp Snapshot for Event Messages */
+  uint32_t                    TimestampSnapshots;           /*!< Select PTP packets for Taking Snapshots */
+  uint32_t                    TimestampFilter;              /*!< Enable MAC Address for PTP Packet Filtering */
+  uint32_t
+  TimestampChecksumCorrection;  /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+  uint32_t                    TimestampExternalSystemTime;  /*!< External System Time Input */
+  uint32_t                    TimestampStatusMode;          /*!< Transmit Timestamp Status Mode */
+  uint32_t                    TimestampAddend;              /*!< Timestamp addend value */
+  uint32_t                    TimestampSubsecondInc;        /*!< Subsecond Increment */
+
+} ETH_PTP_ConfigTypeDef;
+/**
+  *
+  */
+#endif  /* HAL_ETH_USE_PTP */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef uint32_t HAL_ETH_StateTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Rx Get Buffer Function definition
+  */
+typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);  /*!< pointer to an ETH Rx Get Buffer Function */
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Rx Set App Data Function definition
+  */
+typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
+                                            uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Tx Free Function definition
+  */
+typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);  /*!< pointer to an ETH Tx Free function */
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Tx Free Function definition
+  */
+typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
+                                           ETH_TimeStampTypeDef *timestamp);  /*!< pointer to an ETH Tx Free function */
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Handle Structure definition
+  */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+typedef struct __ETH_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+{
+  ETH_TypeDef                *Instance;                           /*!< Register base address       */
+
+  ETH_InitTypeDef            Init;                                /*!< Ethernet Init Configuration */
+
+  ETH_TxDescListTypeDef      TxDescList[ETH_DMA_TX_CH_CNT];       /*!< DMA Channel Tx descriptor wrapper: holds all Tx descriptors
+                                                                       list addresses and current descriptor index  */
+
+  ETH_RxDescListTypeDef      RxDescList[ETH_DMA_RX_CH_CNT];       /*!< DMA Channel Rx descriptor wrapper: holds all Rx descriptors
+                                                                       list addresses and current descriptor index  */
+#ifdef HAL_ETH_USE_PTP
+  ETH_TimeStampTypeDef       TxTimestamp;               /*!< Tx Timestamp */
+#endif /* HAL_ETH_USE_PTP */
+
+  __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
+                                                              and also related to Tx operations. This parameter can
+                                                              be a value of @ref ETH_State_Codes */
+
+  __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
+                                                             This parameter can be a value of @ref ETH_Error_Code.*/
+
+  __IO uint32_t
+  DMAErrorCode;              /*!< Holds the DMA CH0/CH1 Rx Tx Error code when a DMA AIS interrupt occurs
+                                                             This parameter can be a combination of
+                                                             @ref ETH_DMA_Status_Flags */
+
+  __IO uint32_t
+  MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
+                                                             This parameter can be a combination of
+                                                             @ref ETH_MAC_Rx_Tx_Status */
+
+  __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
+                                                             This parameter can be a value of
+                                                             @ref ETH_MAC_Wake_Up_Event */
+
+  __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
+                                                             This parameter can be a value of @ref ETHEx_LPI_Event */
+
+  __IO uint32_t              IsPtpConfigured;           /*!< Holds the PTP configuration status.
+                                                             This parameter can be a value of
+                                                             @ref ETH_PTP_Config_Status */
+
+  __IO uint32_t              TxCH;                      /*!< Holds the Tx DMA Channels Number events.
+                                                             This parameter can be a value of
+                                                             @ref ETH_DMA_Channel_Number_Tx_Rx_Selection */
+
+  __IO uint32_t              RxCH;                      /*!< Holds the Rx DMA Channels Number events.
+                                                             This parameter can be a value of
+                                                             @ref ETH_DMA_Channel_Number_Tx_Rx_Selection */
+  __IO uint32_t              TxOpCH;                    /*!< Holds the Tx DMA Channel Index which transfer data.
+                                                             This parameter can be a value of
+                                                             @ref ETH_DMA_Channel_Number_TxOp_RxOp_Selection */
+  __IO uint32_t              RxOpCH;                    /*!< Holds the Rx DMA Channel Index which receive data.
+                                                             This parameter can be a value of
+                                                             @ref ETH_DMA_Channel_Number_TxOp_RxOp_Selection */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+  void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Tx Complete Callback */
+  void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Rx  Complete Callback     */
+  void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Error Callback   */
+  void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH Power Management Callback            */
+  void (* EEECallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH EEE Callback   */
+  void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Wake UP Callback   */
+
+  void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Msp Init callback              */
+  void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);           /*!< ETH Msp DeInit callback            */
+
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+  pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;  /*!< ETH Rx Get Buffer Function   */
+  pETH_rxLinkCallbackTypeDef      rxLinkCallback; /*!< ETH Rx Set App Data Function */
+  pETH_txFreeCallbackTypeDef      txFreeCallback;       /*!< ETH Tx Free Function         */
+  pETH_txPtpCallbackTypeDef       txPtpCallback;  /*!< ETH Tx Handle Ptp Function */
+
+}
+ETH_HandleTypeDef;
+/**
+  *
+  */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ETH Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
+  HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
+  HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
+  HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
+  HAL_ETH_ERROR_CB_ID              = 0x04U,    /*!< ETH Error Callback ID             */
+  HAL_ETH_PMT_CB_ID                = 0x06U,    /*!< ETH Power Management Callback ID  */
+  HAL_ETH_EEE_CB_ID                = 0x07U,    /*!< ETH EEE Callback ID               */
+  HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
+
+} HAL_ETH_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ETH Callback pointer definition
+  */
+typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);  /*!< pointer to an ETH callback function */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @brief  ETH MAC filter structure definition
+  */
+typedef struct
+{
+  FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
+
+  FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
+
+  FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
+
+  FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
+
+  FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
+
+  FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
+
+  FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
+
+  FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
+
+  FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
+
+  FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
+
+  uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
+                                                 This parameter can be a value of @ref ETH_Control_Packets_Filter */
+} ETH_MACFilterConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Power Down structure definition
+  */
+typedef struct
+{
+  FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
+
+  FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
+
+  FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
+
+  FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
+
+} ETH_PowerDownConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+  * @{
+  */
+
+/** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
+  * @{
+  */
+
+/*
+   DMA Tx Normal Descriptor Read Format
+  -----------------------------------------------------------------------------------------------------------
+  TDES0 |                           Buffer1 or Header Address  [31:0]                                        |
+  -----------------------------------------------------------------------------------------------------------
+  TDES1 |                           Buffer2 Address [31:0] / Next Descriptor Address [31:0]                  |
+  -----------------------------------------------------------------------------------------------------------
+  TDES2 | IOC(31) |   TTSE(30) |    Buff2 Length[29:16] |    VTIR[15:14]  |    Header or Buff1 Length[13:0]  |
+  -----------------------------------------------------------------------------------------------------------
+  TDES3 | OWN(31)|CTXT(28)|FD(29)|LD(28)|CPC[27:26]|SAIC[25:23]|SLOTNUM[22:19]|TTSE(18)|TPL[17:16]|FT/L[15:0]|
+  -----------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of TDES0 RF register
+  */
+#define ETH_DMATXNDESCRF_B1AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
+
+/**
+  * @brief  Bit definition of TDES1 RF register
+  */
+#define ETH_DMATXNDESCRF_B2AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
+
+/**
+  * @brief  Bit definition of TDES2 RF register
+  */
+#define ETH_DMATXNDESCRF_IOC          0x80000000U  /*!< Interrupt on Completion */
+#define ETH_DMATXNDESCRF_TTSE         0x40000000U  /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCRF_B2L          0x3FFF0000U  /*!< Buffer 2 Length */
+#define ETH_DMATXNDESCRF_VTIR         0x0000C000U  /*!< VLAN Tag Insertion or Replacement mask */
+#define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U  /*!< Do not add a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REMOVE  0x00004000U  /*!< Remove the VLAN tag from the packets before transmission. */
+#define ETH_DMATXNDESCRF_VTIR_INSERT  0x00008000U  /*!< Insert a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U  /*!< Replace the VLAN tag. */
+#define ETH_DMATXNDESCRF_B1L          0x00003FFFU  /*!< Buffer 1 Length */
+#define ETH_DMATXNDESCRF_HL           0x000003FFU  /*!< Header Length */
+
+/**
+  * @brief  Bit definition of TDES3 RF register
+  */
+#define ETH_DMATXNDESCRF_OWN                                 0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCRF_CTXT                                0x40000000U  /*!< Context Type */
+#define ETH_DMATXNDESCRF_FD                                  0x20000000U  /*!< First Descriptor */
+#define ETH_DMATXNDESCRF_LD                                  0x10000000U  /*!< Last Descriptor */
+#define ETH_DMATXNDESCRF_CPC                                 0x0C000000U  /*!< CRC Pad Control mask */
+#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   0x00000000U  /*!< CRC Pad Control: CRC and Pad Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      0x04000000U  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
+#define ETH_DMATXNDESCRF_CPC_DISABLE                         0x08000000U  /*!< CRC Pad Control: Disable CRC Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     0x0C000000U  /*!< CRC Pad Control: CRC Replacement */
+#define ETH_DMATXNDESCRF_SAIC                                0x03800000U  /*!< SA Insertion Control mask*/
+#define ETH_DMATXNDESCRF_SAIC_DISABLE                        0x00000000U  /*!< SA Insertion Control: Do not include the source address */
+#define ETH_DMATXNDESCRF_SAIC_INSERT                         0x00800000U  /*!< SA Insertion Control: Include or insert the source address */
+#define ETH_DMATXNDESCRF_SAIC_REPLACE                        0x01000000U  /*!< SA Insertion Control: Replace the source address */
+#define ETH_DMATXNDESCRF_THL                                 0x00780000U  /*!< TCP Header Length */
+#define ETH_DMATXNDESCRF_SLOTNUM                             0x00780000U  /*!< Slot Number Control */
+#define ETH_DMATXNDESCRF_TSE                                 0x00040000U  /*!< TCP segmentation enable */
+#define ETH_DMATXNDESCRF_CIC                                 0x00030000U  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXNDESCRF_CIC_DISABLE                         0x00000000U  /*!< Do Nothing: Checksum Engine is disabled */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    0x00010000U  /*!< Only IP header checksum calculation and insertion are enabled. */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            0x00020000U  /*!< IP header checksum and payload checksum calculation and insertion are
+                                                                                        enabled, but pseudo header
+                                                                                        checksum is not
+                                                                                        calculated in hardware */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  0x00030000U  /*!< IP Header checksum and payload checksum calculation and insertion are
+                                                                                        enabled, and pseudo header
+                                                                                        checksum is
+                                                                                        calculated in hardware. */
+#define ETH_DMATXNDESCRF_TPL                                 0x0003FFFFU  /*!< TCP Payload Length */
+#define ETH_DMATXNDESCRF_FL                                  0x00007FFFU  /*!< Transmit End of Ring */
+
+/*
+   DMA Tx Normal Descriptor Write Back Format
+  -----------------------------------------------------------------------------------------------
+  TDES0 |                         Timestamp Low                                                  |
+  -----------------------------------------------------------------------------------------------
+  TDES1 |                         Timestamp High                                                 |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                         Reserved[31:0]                                                 |
+  -----------------------------------------------------------------------------------------------
+  TDES3 | OWN(31) |    Status[30:28]  |       Reserved[27:18] |         Status[17:0]             |
+  -----------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of TDES0 WBF register
+  */
+#define ETH_DMATXNDESCWBF_TTSL                    0xFFFFFFFFU  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
+
+/**
+  * @brief  Bit definition of TDES1 WBF register
+  */
+#define ETH_DMATXNDESCWBF_TTSH                    0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
+
+/**
+  * @brief  Bit definition of TDES3 WBF register
+  */
+#define ETH_DMATXNDESCWBF_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCWBF_CTXT                    0x40000000U  /*!< Context Type */
+#define ETH_DMATXNDESCWBF_FD                      0x20000000U  /*!< First Descriptor */
+#define ETH_DMATXNDESCWBF_LD                      0x10000000U  /*!< Last Descriptor */
+#define ETH_DMATXNDESCWBF_TTSS                    0x00020000U  /*!< Tx Timestamp Status */
+#define ETH_DMATXNDESCWBF_DP                      0x04000000U  /*!< Disable Padding */
+#define ETH_DMATXNDESCWBF_TTSE                    0x02000000U  /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCWBF_ES                      0x00008000U  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
+#define ETH_DMATXNDESCWBF_JT                      0x00004000U  /*!< Jabber Timeout */
+#define ETH_DMATXNDESCWBF_FF                      0x00002000U  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
+#define ETH_DMATXNDESCWBF_PCE                     0x00001000U  /*!< Payload Checksum Error */
+#define ETH_DMATXNDESCWBF_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXNDESCWBF_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXNDESCWBF_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXNDESCWBF_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXNDESCWBF_CC                      0x000000F0U  /*!< Collision Count */
+#define ETH_DMATXNDESCWBF_ED                      0x00000008U  /*!< Excessive Deferral */
+#define ETH_DMATXNDESCWBF_UF                      0x00000004U  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXNDESCWBF_DB                      0x00000002U  /*!< Deferred Bit */
+#define ETH_DMATXNDESCWBF_IHE                     0x00000004U  /*!< IP Header Error */
+
+/*
+   DMA Tx Context Descriptor
+  -----------------------------------------------------------------------------------------------
+  TDES0 |                               Timestamp Low                                            |
+  -----------------------------------------------------------------------------------------------
+  TDES1 |                               Timestamp High                                           |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 | OWN(31) |                          Status[30:0]                                        |
+  -----------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 0
+  */
+#define ETH_DMATXCDESC_TTSL                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 1
+  */
+#define ETH_DMATXCDESC_TTSH                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 2
+  */
+#define ETH_DMATXCDESC_IVT                     0xFFFF0000U  /*!< Inner VLAN Tag */
+#define ETH_DMATXCDESC_MSS                     0x00003FFFU  /*!< Maximum Segment Size */
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 3
+  */
+#define ETH_DMATXCDESC_OWN                     0x80000000U     /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXCDESC_CTXT                    0x40000000U     /*!< Context Type */
+#define ETH_DMATXCDESC_OSTC                    0x08000000U     /*!< One-Step Timestamp Correction Enable */
+#define ETH_DMATXCDESC_TCMSSV                  0x04000000U     /*!< One-Step Timestamp Correction Input or MSS Valid */
+#define ETH_DMATXCDESC_CDE                     0x00800000U     /*!< Context Descriptor Error */
+#define ETH_DMATXCDESC_IVTIR                   0x000C0000U     /*!< Inner VLAN Tag Insert or Replace Mask */
+#define ETH_DMATXCDESC_IVTIR_DISABLE           0x00000000U     /*!< Do not add the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REMOVE            0x00040000U     /*!< Remove the inner VLAN tag from the packets before transmission. */
+#define ETH_DMATXCDESC_IVTIR_INSERT            0x00080000U     /*!< Insert the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REPLACE           0x000C0000U     /*!< Replace the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVLTV                   0x00020000U     /*!< Inner VLAN Tag Valid */
+#define ETH_DMATXCDESC_VLTV                    0x00010000U     /*!< VLAN Tag Valid */
+#define ETH_DMATXCDESC_VT                      0x0000FFFFU     /*!< VLAN Tag */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
+  * @{
+  */
+
+/*
+  DMA Rx Normal Descriptor read format
+  -----------------------------------------------------------------------------------------------------------
+  RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
+  -----------------------------------------------------------------------------------------------------------
+  RDES1 |                                            Reserved                                               |
+  -----------------------------------------------------------------------------------------------------------
+  RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
+  -----------------------------------------------------------------------------------------------------------
+  RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
+  -----------------------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 0 read format
+  */
+#define ETH_DMARXNDESCRF_BUF1AP           0xFFFFFFFFU  /*!< Header or Buffer 1 Address Pointer  */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 2 read format
+  */
+#define ETH_DMARXNDESCRF_BUF2AP           0xFFFFFFFFU  /*!< Buffer 2 Address Pointer  */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 3 read format
+  */
+#define ETH_DMARXNDESCRF_OWN              0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARXNDESCRF_IOC              0x40000000U  /*!< Interrupt Enabled on Completion  */
+#define ETH_DMARXNDESCRF_BUF2V            0x02000000U  /*!< Buffer 2 Address Valid */
+#define ETH_DMARXNDESCRF_BUF1V            0x01000000U  /*!< Buffer 1 Address Valid */
+
+/*
+  DMA Rx Normal Descriptor write back format
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
+  ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 0 write back format
+  */
+#define ETH_DMARXNDESCWBF_IVT             0xFFFF0000U  /*!< Inner VLAN Tag  */
+#define ETH_DMARXNDESCWBF_OVT             0x0000FFFFU  /*!< Outer VLAN Tag  */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 1 write back format
+  */
+#define ETH_DMARXNDESCWBF_OPC             0xFFFF0000U  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
+#define ETH_DMARXNDESCWBF_TD              0x00008000U  /*!< Timestamp Dropped  */
+#define ETH_DMARXNDESCWBF_TSA             0x00004000U  /*!< Timestamp Available  */
+#define ETH_DMARXNDESCWBF_PV              0x00002000U  /*!< PTP Version  */
+#define ETH_DMARXNDESCWBF_PFT             0x00001000U  /*!< PTP Packet Type  */
+#define ETH_DMARXNDESCWBF_PMT_NO          0x00000000U  /*!< PTP Message Type: No PTP message received  */
+#define ETH_DMARXNDESCWBF_PMT_SYNC        0x00000100U  /*!< PTP Message Type: SYNC (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_FUP         0x00000200U  /*!< PTP Message Type: Follow_Up (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_DREQ        0x00000300U  /*!< PTP Message Type: Delay_Req (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_DRESP       0x00000400U  /*!< PTP Message Type: Delay_Resp (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_PDREQ       0x00000500U  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_PDRESP      0x00000600U  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   0x00000700U  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    0x00000800U  /*!< PTP Message Type: Announce  */
+#define ETH_DMARXNDESCWBF_PMT_MANAG       0x00000900U  /*!< PTP Message Type: Management  */
+#define ETH_DMARXNDESCWBF_PMT_SIGN        0x00000A00U  /*!< PTP Message Type: Signaling  */
+#define ETH_DMARXNDESCWBF_PMT_RESERVED    0x00000F00U  /*!< PTP Message Type: PTP packet with Reserved message type  */
+#define ETH_DMARXNDESCWBF_IPCE            0x00000080U  /*!< IP Payload Error */
+#define ETH_DMARXNDESCWBF_IPCB            0x00000040U  /*!< IP Checksum Bypassed */
+#define ETH_DMARXNDESCWBF_IPV6            0x00000020U  /*!< IPv6 header Present */
+#define ETH_DMARXNDESCWBF_IPV4            0x00000010U  /*!< IPv4 header Present */
+#define ETH_DMARXNDESCWBF_IPHE            0x00000008U  /*!< IP Header Error */
+#define ETH_DMARXNDESCWBF_PT              0x00000003U  /*!< Payload Type mask */
+#define ETH_DMARXNDESCWBF_PT_UNKNOWN      0x00000000U  /*!< Payload Type: Unknown type or IP/AV payload not processed */
+#define ETH_DMARXNDESCWBF_PT_UDP          0x00000001U  /*!< Payload Type: UDP */
+#define ETH_DMARXNDESCWBF_PT_TCP          0x00000002U  /*!< Payload Type: TCP  */
+#define ETH_DMARXNDESCWBF_PT_ICMP         0x00000003U  /*!< Payload Type: ICMP */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 2 write back format
+  */
+#define ETH_DMARXNDESCWBF_L3L4FM          0x20000000U  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
+#define ETH_DMARXNDESCWBF_L4FM            0x10000000U  /*!< Layer 4 Filter Match                  */
+#define ETH_DMARXNDESCWBF_L3FM            0x08000000U  /*!< Layer 3 Filter Match                  */
+#define ETH_DMARXNDESCWBF_MADRM           0x07F80000U  /*!< MAC Address Match or Hash Value       */
+#define ETH_DMARXNDESCWBF_HF              0x00040000U  /*!< Hash Filter Status                    */
+#define ETH_DMARXNDESCWBF_DAF             0x00020000U  /*!< Destination Address Filter Fail       */
+#define ETH_DMARXNDESCWBF_SAF             0x00010000U  /*!< SA Address Filter Fail                */
+#define ETH_DMARXNDESCWBF_VF              0x00008000U  /*!< VLAN Filter Status                    */
+#define ETH_DMARXNDESCWBF_ARPNR           0x00000400U  /*!< ARP Reply Not Generated               */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 3 write back format
+  */
+#define ETH_DMARXNDESCWBF_OWN             0x80000000U  /*!< Own Bit */
+#define ETH_DMARXNDESCWBF_CTXT            0x40000000U  /*!< Receive Context Descriptor */
+#define ETH_DMARXNDESCWBF_FD              0x20000000U  /*!< First Descriptor */
+#define ETH_DMARXNDESCWBF_LD              0x10000000U  /*!< Last Descriptor */
+#define ETH_DMARXNDESCWBF_RS2V            0x08000000U  /*!< Receive Status RDES2 Valid */
+#define ETH_DMARXNDESCWBF_RS1V            0x04000000U  /*!< Receive Status RDES1 Valid */
+#define ETH_DMARXNDESCWBF_RS0V            0x02000000U  /*!< Receive Status RDES0 Valid */
+#define ETH_DMARXNDESCWBF_CE              0x01000000U  /*!< CRC Error */
+#define ETH_DMARXNDESCWBF_GP              0x00800000U  /*!< Giant Packet */
+#define ETH_DMARXNDESCWBF_RWT             0x00400000U  /*!< Receive Watchdog Timeout */
+#define ETH_DMARXNDESCWBF_OE              0x00200000U  /*!< Overflow Error */
+#define ETH_DMARXNDESCWBF_RE              0x00100000U  /*!< Receive Error */
+#define ETH_DMARXNDESCWBF_DE              0x00080000U  /*!< Dribble Bit Error */
+#define ETH_DMARXNDESCWBF_LT              0x00070000U  /*!< Length/Type Field */
+#define ETH_DMARXNDESCWBF_LT_LP           0x00000000U  /*!< The packet is a length packet */
+#define ETH_DMARXNDESCWBF_LT_TP           0x00010000U  /*!< The packet is a type packet */
+#define ETH_DMARXNDESCWBF_LT_ARP          0x00030000U  /*!< The packet is a ARP Request packet type */
+#define ETH_DMARXNDESCWBF_LT_VLAN         0x00040000U  /*!< The packet is a type packet with VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_DVLAN        0x00050000U  /*!< The packet is a type packet with Double VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_MAC          0x00060000U  /*!< The packet is a MAC Control packet type */
+#define ETH_DMARXNDESCWBF_LT_OAM          0x00070000U  /*!< The packet is a OAM packet type */
+#define ETH_DMARXNDESCWBF_ES              0x00008000U  /*!< Error Summary */
+#define ETH_DMARXNDESCWBF_PL              0x00007FFFU  /*!< Packet Length */
+
+/*
+  DMA Rx context Descriptor
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES0 |                                     Timestamp Low[31:0]                                                     |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 |                                     Timestamp High[31:0]                                                    |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                          Reserved                                                           |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Rx context descriptor register 0
+  */
+#define ETH_DMARXCDESC_RTSL                   0xFFFFFFFFU  /*!< Receive Packet Timestamp Low  */
+
+/**
+  * @brief  Bit definition of Rx context descriptor register 1
+  */
+#define ETH_DMARXCDESC_RTSH                   0xFFFFFFFFU  /*!< Receive Packet Timestamp High  */
+
+/**
+  * @brief  Bit definition of Rx context descriptor register 3
+  */
+#define ETH_DMARXCDESC_OWN                    0x80000000U  /*!< Own Bit  */
+#define ETH_DMARXCDESC_CTXT                   0x40000000U  /*!< Receive Context Descriptor  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Frame_settings ETH frame settings
+  * @{
+  */
+#define ETH_MAX_PACKET_SIZE                   1528U    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER                            14U    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                               4U    /*!< Ethernet CRC */
+#define ETH_VLAN_TAG                          4U    /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_PAYLOAD                       46U    /*!< Minimum Ethernet payload size */
+#define ETH_MAX_PAYLOAD                       1500U    /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD               9000U    /*!< Jumbo frame payload size */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Error_Code ETH Error Code
+  * @{
+  */
+#define HAL_ETH_ERROR_NONE                    0x00000000U   /*!< No error            */
+#define HAL_ETH_ERROR_PARAM                   0x00000001U   /*!< Busy error          */
+#define HAL_ETH_ERROR_BUSY                    0x00000002U   /*!< Parameter error     */
+#define HAL_ETH_ERROR_TIMEOUT                 0x00000004U   /*!< Timeout error       */
+#define HAL_ETH_ERROR_MTL_Q0                  0x00000020U   /*!< MTL Q0 error  */
+#define HAL_ETH_ERROR_MTL_Q1                  0x00000040U   /*!< MTL Q1 error  */
+#define HAL_ETH_ERROR_MAC                     0x00000080U   /*!< MAC transfer error  */
+
+typedef enum
+{
+  HAL_ETH_ERROR_DMA = 0x00000008U,
+  HAL_ETH_ERROR_DMA_CH0 = 0x00000010U,
+  HAL_ETH_ERROR_DMA_CH1 = 0x00000020U
+} ETH_DMAChannelErrorTypeDef;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define HAL_ETH_ERROR_INVALID_CALLBACK        0x00000020U    /*!< Invalid Callback error  */
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
+  * @{
+  */
+#define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U
+#define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U
+#define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U
+#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U
+#define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U
+#define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
+  * @{
+  */
+#define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
+#define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
+#define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
+  * @{
+  */
+#define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
+#define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
+#define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
+#define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
+  * @{
+  */
+#define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
+#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
+  * @{
+  */
+#define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
+#define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
+#define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
+#define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
+  * @{
+  */
+#define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
+#define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
+#define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
+#define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
+  * @{
+  */
+#define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
+#define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
+#define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
+  * @{
+  */
+#define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
+#define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
+  * @{
+  */
+#define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
+#define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
+#define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
+#define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
+  * @{
+  */
+#define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
+#define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
+#define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
+#define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
+/**
+  * @}
+  */
+/** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
+  * @{
+  */
+#define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
+#define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
+  * @{
+  */
+#define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
+#define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
+  * @{
+  */
+#define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
+#define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
+#define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
+#define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
+#define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
+#define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
+  * @{
+  */
+#define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Transmit_Arbitration_Algorithm ETH DMA Transmit Arbitration Algorithm
+  * @{
+  */
+#define ETH_DMATXARBITRATION_FIXED_PRIO      (ETH_DMAMR_TAA_FP)
+#define ETH_DMATXARBITRATION_WEIGHTED_SP     (ETH_DMAMR_TAA_WSP)
+#define ETH_DMATXARBITRATION_WEIGHTED_RR     (ETH_DMAMR_TAA_WRR)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Burst_Mode ETH Burst Mode
+  * @{
+  */
+#define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
+#define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETH_BLEN_Size ETH Blen size
+  * @{
+  */
+#define ETH_BLEN_MAX_SIZE_256             (ETH_DMASBMR_BLEN256 | ETH_BLEN_MAX_SIZE_128)
+#define ETH_BLEN_MAX_SIZE_128             (ETH_DMASBMR_BLEN128 | ETH_BLEN_MAX_SIZE_64)
+#define ETH_BLEN_MAX_SIZE_64              (ETH_DMASBMR_BLEN64 | ETH_BLEN_MAX_SIZE_32)
+#define ETH_BLEN_MAX_SIZE_32              (ETH_DMASBMR_BLEN32 | ETH_BLEN_MAX_SIZE_16)
+#define ETH_BLEN_MAX_SIZE_16              (ETH_DMASBMR_BLEN16 | ETH_BLEN_MAX_SIZE_8)
+#define ETH_BLEN_MAX_SIZE_8               (ETH_DMASBMR_BLEN8 | ETH_BLEN_MAX_SIZE_4)
+#define ETH_BLEN_MAX_SIZE_4               ETH_DMASBMR_BLEN4
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_RX_OSR_LIMIT ETH Rx maximum read outstanding request limit
+  * @{
+  */
+#define ETH_RX_OSR_LIMIT_1 ETH_DMASBMR_RD_OSR_LMT_0
+#define ETH_RX_OSR_LIMIT_2 ETH_DMASBMR_RD_OSR_LMT_1
+#define ETH_RX_OSR_LIMIT_3 (ETH_DMASBMR_RD_OSR_LMT_1 | ETH_DMASBMR_RD_OSR_LMT_0)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_TX_OSR_LIMIT ETH Tx maximum write outstanding request limit
+  * @{
+  */
+#define ETH_TX_OSR_LIMIT_1 ETH_DMASBMR_WR_OSR_LMT_0
+#define ETH_TX_OSR_LIMIT_2 ETH_DMASBMR_WR_OSR_LMT_1
+#define ETH_TX_OSR_LIMIT_3 (ETH_DMASBMR_WR_OSR_LMT_1 | ETH_DMASBMR_WR_OSR_LMT_0)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
+  * @{
+  */
+#define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACxTXCR_TXPBL_1PBL
+#define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACxTXCR_TXPBL_2PBL
+#define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACxTXCR_TXPBL_4PBL
+#define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACxTXCR_TXPBL_8PBL
+#define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACxTXCR_TXPBL_16PBL
+#define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACxTXCR_TXPBL_32PBL
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_DMA_Channel_Weight ETH Tx DMA Channel Weight
+  * @{
+  */
+#define ETH_TXCHANNELWEIGHT_1               ETH_DMACxTXCR_TCW_1
+#define ETH_TXCHANNELWEIGHT_2               ETH_DMACxTXCR_TCW_2
+#define ETH_TXCHANNELWEIGHT_3               ETH_DMACxTXCR_TCW_3
+#define ETH_TXCHANNELWEIGHT_4               ETH_DMACxTXCR_TCW_4
+#define ETH_TXCHANNELWEIGHT_5               ETH_DMACxTXCR_TCW_5
+#define ETH_TXCHANNELWEIGHT_6               ETH_DMACxTXCR_TCW_6
+#define ETH_TXCHANNELWEIGHT_7               ETH_DMACxTXCR_TCW_7
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
+  * @{
+  */
+#define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACxRXCR_RXPBL_1PBL
+#define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACxRXCR_RXPBL_2PBL
+#define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACxRXCR_RXPBL_4PBL
+#define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACxRXCR_RXPBL_8PBL
+#define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACxRXCR_RXPBL_16PBL
+#define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACxRXCR_RXPBL_32PBL
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Descriptor_Skip_Length ETH DMA Descriptor Skip Length
+  * @{
+  */
+#define ETH_DMA_DESC_SKIP_LENGTH_0       ETH_DMACxCR_DSL_0BIT
+#define ETH_DMA_DESC_SKIP_LENGTH_32      ETH_DMACxCR_DSL_32BIT
+#define ETH_DMA_DESC_SKIP_LENGTH_64      ETH_DMACxCR_DSL_64BIT
+#define ETH_DMA_DESC_SKIP_LENGTH_128     ETH_DMACxCR_DSL_128BIT
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Queue_Operation_Mode ETH Queue Operation Mode
+  * @{
+  */
+#define ETH_TX_QUEUE_ENABLED     ETH_MTLTXQxOMR_TXQEN_EN
+#define ETH_TX_QUEUE_DISABLED    ETH_MTLTXQxOMR_TXQEN_NOT
+#define ETH_TX_QUEUE_AV_ENABLED  ETH_MTLTXQxOMR_TXQEN_AVMODE
+
+#define ETH_RX_QUEUE0_ENABLED     ETH_MACRXQC0R_RXQ0EN_GT
+#define ETH_RX_QUEUE0_DISABLED    ETH_MACRXQC0R_RXQ0EN_NOT
+#define ETH_RX_QUEUE0_AV_ENABLED  ETH_MACRXQC0R_RXQ0EN_AV
+
+#define ETH_RX_QUEUE1_ENABLED     ETH_MACRXQC0R_RXQ1EN_GT
+#define ETH_RX_QUEUE1_DISABLED    ETH_MACRXQC0R_RXQ1EN_NOT
+#define ETH_RX_QUEUE1_AV_ENABLED  ETH_MACRXQC0R_RXQ1EN_AV
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Queue_Size ETH Transmit Queue Size
+  * @{
+  */
+#define ETH_TRANSMIT_QUEUE_SIZE_256      0x00000000U
+#define ETH_TRANSMIT_QUEUE_SIZE_2048     (ETH_MTLTXQxOMR_TQS_0 | ETH_MTLTXQxOMR_TQS_1 | ETH_MTLTXQxOMR_TQS_2)
+#define ETH_TRANSMIT_QUEUE_SIZE_4096     (ETH_TRANSMIT_QUEUE_SIZE_2048 | ETH_MTLTXQxOMR_TQS_3)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Queue_Size ETH Receive Queue Size
+  * @{
+  */
+#define ETH_RECEIVE_QUEUE_SIZE_256      0x00000000U
+#define ETH_RECEIVE_QUEUE_SIZE_2048     (ETH_MTLRXQxOMR_RQS_0 | ETH_MTLRXQxOMR_RQS_1 | ETH_MTLRXQxOMR_RQS_2)
+#define ETH_RECEIVE_QUEUE_SIZE_4096     (ETH_RECEIVE_QUEUE_SIZE_2048 | ETH_MTLRXQxOMR_RQS_3)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+  * @{
+  */
+#define ETH_DMA_NORMAL_IT                 ETH_DMACxIER_NIE
+#define ETH_DMA_ABNORMAL_IT               ETH_DMACxIER_AIE
+#define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACxIER_CDEE
+#define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACxIER_FBEE
+#define ETH_DMA_EARLY_RX_IT               ETH_DMACxIER_ERIE
+#define ETH_DMA_EARLY_TX_IT               ETH_DMACxIER_ETIE
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACxIER_RWTE
+#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACxIER_RSE
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACxIER_RBUE
+#define ETH_DMA_RX_IT                     ETH_DMACxIER_RIE
+#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACxIER_TBUE
+#define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACxIER_TXSE
+#define ETH_DMA_TX_IT                     ETH_DMACxIER_TIE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
+  * @{
+  */
+#define ETH_DMA_RX_NO_ERROR_FLAG                 0x00000000U
+#define ETH_DMA_TX_NO_ERROR_FLAG                 0x00000000U
+#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG          ETH_DMACxSR_CDE
+#define ETH_DMA_FATAL_BUS_ERROR_FLAG             ETH_DMACxSR_FBE
+#define ETH_DMA_EARLY_TX_IT_FLAG                 ETH_DMACxSR_ERI
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG         ETH_DMACxSR_RWT
+#define ETH_DMA_RX_PROCESS_STOPPED_FLAG          ETH_DMACxSR_RPS
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG       ETH_DMACxSR_RBU
+#define ETH_DMA_TX_PROCESS_STOPPED_FLAG          ETH_DMACxSR_TPS
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
+  * @{
+  */
+#define ETH_TRANSMITSTOREFORWARD       ETH_MTLTXQxOMR_TSF
+#define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTXQxOMR_TTC_32BITS
+#define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTXQxOMR_TTC_64BITS
+#define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTXQxOMR_TTC_96BITS
+#define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTXQxOMR_TTC_128BITS
+#define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTXQxOMR_TTC_192BITS
+#define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTXQxOMR_TTC_256BITS
+#define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTXQxOMR_TTC_384BITS
+#define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTXQxOMR_TTC_512BITS
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Mode ETH Receive Mode
+  * @{
+  */
+#define ETH_RECEIVESTOREFORWARD        ETH_MTLRXQxOMR_RSF
+#define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRXQxOMR_RTC_64BITS
+#define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRXQxOMR_RTC_32BITS
+#define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRXQxOMR_RTC_96BITS
+#define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRXQxOMR_RTC_128BITS
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Queue_Mapped_DMA_Channel ETH Queue Mapped DMA Channel
+  * @{
+  */
+#define ETH_MTL_Q0_MAPPED_TO_DMA_CH0   ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0
+#define ETH_MTL_Q0_MAPPED_TO_DMA_CH1   ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1
+#define ETH_MTL_Q1_MAPPED_TO_DMA_CH0   ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0
+#define ETH_MTL_Q1_MAPPED_TO_DMA_CH1   ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Queue1_AV_Algo ETH Queue1 AV Algo
+  * @{
+  */
+#define ETH_TX_QUEUE_AV_ALGO_CBS    ETH_MTLTXQ1ECR_AVALG
+#define ETH_TX_QUEUE_AV_ALGO_SP     0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETH_RX_Queue ETH RX Queue
+  * @{
+  */
+#define ETH_RX_QUEUE0              0x00000000U
+#define ETH_RX_QUEUE1              0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MTL_Interrupts ETH MTL Interrupts
+  * @{
+  */
+#define ETH_RX_QUEUE_OVERFLOW_IT       ETH_MTLQxICSR_RXOIE
+#define ETH_AVERAGE_BITS_PER_SLOT_IT   ETH_MTLQxICSR_ABPSIE
+#define ETH_TX_QUEUE_UNDERFLOW_IT      ETH_MTLQxICSR_TXUIE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
+  * @{
+  */
+#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACQ0TXFCR_PLT_MINUS4
+#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACQ0TXFCR_PLT_MINUS28
+#define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACQ0TXFCR_PLT_MINUS36
+#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACQ0TXFCR_PLT_MINUS144
+#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACQ0TXFCR_PLT_MINUS256
+#define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACQ0TXFCR_PLT_MINUS512
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
+  * @{
+  */
+#define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
+#define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
+#define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
+#define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
+#define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
+#define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
+#define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
+#define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
+#define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
+#define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
+#define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
+#define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
+#define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
+  * @{
+  */
+#define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
+#define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
+#define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
+#define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
+#define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
+#define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
+#define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
+#define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Speed  ETH Speed
+  * @{
+  */
+#define ETH_SPEED_10M        0x00000000U
+#define ETH_SPEED_100M       ETH_MACCR_FES
+#define ETH_SPEED_1000M      0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+  * @{
+  */
+#define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
+#define ETH_HALFDUPLEX_MODE       0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
+  * @{
+  */
+#define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
+#define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
+#define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
+#define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Preamble_Length ETH Preamble Length
+  * @{
+  */
+#define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
+#define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
+#define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
+  * @{
+  */
+#define ETH_SOURCEADDRESS_DISABLE           0x00000000U
+#define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_1
+#define ETH_SOURCEADDRESS_INSERT_ADDR1      (ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1)
+#define ETH_SOURCEADDRESS_REPLACE_ADDR0     (ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0)
+#define ETH_SOURCEADDRESS_REPLACE_ADDR1     (ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
+  * @{
+  */
+#define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
+#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
+#define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
+#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
+/**
+  * @}
+  */
+
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
+  * @{
+  */
+#define ETH_VLANTAGCOMPARISON_16BIT          0x00000000U
+#define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTCR_ETV
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
+  * @{
+  */
+#define ETH_MAC_ADDRESS0     0x00000000U
+#define ETH_MAC_ADDRESS1     0x00000008U
+#define ETH_MAC_ADDRESS2     0x00000010U
+#define ETH_MAC_ADDRESS3     0x00000018U
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+  * @{
+  */
+#define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
+#define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
+#define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
+#define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
+#define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
+#define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
+  * @{
+  */
+#define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
+#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
+  * @{
+  */
+#define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
+#define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
+#define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
+#define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
+#define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
+#define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
+#define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
+/**
+  * @}
+  */
+
+/** @defgroup ETH_State_Codes ETH States
+  * @{
+  */
+#define HAL_ETH_STATE_RESET                0x00000000U    /*!< Peripheral not yet Initialized or disabled */
+#define HAL_ETH_STATE_READY                0x00000010U    /*!< Peripheral Communication started           */
+#define HAL_ETH_STATE_BUSY                 0x00000020U    /*!< an internal process is ongoing             */
+#define HAL_ETH_STATE_STARTED              0x00000040U    /*!< an internal process is started             */
+#define HAL_ETH_STATE_ERROR                0x000000E0U    /*!< Error State                                */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
+  * @{
+  */
+#define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U    /*!< ETH PTP Configuration not done */
+#define HAL_ETH_PTP_CONFIGURED            0x00000001U    /*!< ETH PTP Configuration done     */
+/**
+  * @}
+  */
+#ifdef HAL_ETH_USE_PTP
+/** @defgroup ETH_PTP_Update_Method ETH PTP Update Method
+  * @{
+  */
+#define HAL_ETH_PTP_COARSE_TS_UPDATE  0x00000000U    /*!< Coarse method is used to update the system timestamp */
+#define HAL_ETH_PTP_FINE_TS_UPDATE    0x00000002U    /*!< Fine method is used to update system timestamp     */
+/**
+  * @}
+  */
+/** @defgroup ETH_PTP_Snap_Type_Selection ETH PTP Snap Type Selection
+  * @{
+  */
+#define HAL_ETH_PTP_SNAPTYPSEL_0      0x00000000U    /*!< SNAPTYPSEL 00 */
+#define HAL_ETH_PTP_SNAPTYPSEL_1      0x00010000U    /*!< SNAPTYPSEL 01 */
+#define HAL_ETH_PTP_SNAPTYPSEL_2      0x00020000U    /*!< SNAPTYPSEL 10 */
+#define HAL_ETH_PTP_SNAPTYPSEL_3      0x00030000U    /*!< SNAPTYPSEL 11 */
+/**
+  * @}
+  */
+#endif /* HAL_ETH_USE_PTP */
+
+/** @defgroup ETH_DMA_Channel_Number_Tx_Rx_Selection ETH DMA Channel Number Tx Rx Selection
+  * @{
+  */
+#define ETH_DMA_CH0                 0x00000001U
+#define ETH_DMA_CH1                 0x00000002U
+/**
+  * @}
+  */
+/** @defgroup ETH_DMA_Channel_Number_TxOp_RxOp_Selection ETH DMA Channel Number Tx Rx Selection Index
+  * @{
+  */
+#define ETH_DMA_CH0_IDX             (0U)
+#define ETH_DMA_CH1_IDX             (1U)
+/**
+  * @}
+  */
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+  * @{
+  */
+
+/** @brief Reset ETH handle state
+  * @param  __HANDLE__: specifies the ETH handle.
+  * @retval None
+  */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
+                                                      (__HANDLE__)->MspInitCallback = NULL;             \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                    } while(0)
+#else
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
+                                                    } while(0)
+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enables the specified ETHERNET DMA interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __CH__   : DMA Channel
+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  *   enabled @ref ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_CH_ENABLE_IT(__HANDLE__, __INTERRUPT__,__CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACIER \
+                                                                      |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified ETHERNET DMA interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __CH__   : DMA Channel
+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  *   disabled. @ref ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_CH_DISABLE_IT(__HANDLE__, __INTERRUPT__, __CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACIER \
+                                                                        &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __CH__   : DMA Channel
+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+  * @retval The ETH DMA IT Source enabled or disabled
+  */
+#define __HAL_ETH_DMA_CH_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__, __CH__) \
+  (((__HANDLE__)->Instance->DMA_CH[__CH__].DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Gets the ETHERNET DMA IT pending bit.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __CH__   : DMA Channel
+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+  * @retval The state of ETH DMA IT (SET or RESET)
+  */
+#define __HAL_ETH_DMA_CH_GET_IT(__HANDLE__, __INTERRUPT__, __CH__) \
+  (((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the ETHERNET DMA IT pending bit.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __CH__   : DMA Channel
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_CH_CLEAR_IT(__HANDLE__, __INTERRUPT__, __CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR \
+                                                                      = (__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __CH__   : DMA Channel
+  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+  * @retval The state of ETH DMA FLAG (SET or RESET).
+  */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__, __CH__) (((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR &\
+                                                               ( __FLAG__)) == ( __FLAG__))
+
+/**
+  * @brief  Clears the specified ETHERNET DMA flag.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __CH__   : DMA Channel
+  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+  * @retval The state of ETH DMA FLAG (SET or RESET).
+  */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__, __CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR\
+                                                                = ( __FLAG__))
+
+/**
+  * @brief  Enables the specified ETHERNET MTL interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __Q__   : MTL Queue
+  * @param  __INTERRUPT__: specifies the ETHERNET MTL interrupt sources to be
+  *   enabled @ref ETH_MTL_Interrupts
+  * @retval None
+  */
+
+#define __HAL_ETH_MTL_Q_ENABLE_IT(__HANDLE__, __INTERRUPT__, __Q__) ((__HANDLE__)->Instance->MTL_QUEUE[__Q__].MTLQICSR \
+                                                                     |= (__INTERRUPT__))
+
+/**
+  * @brief  Gets the ETHERNET MTL IT source enabled or disabled.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_MTL_Interrupts
+  * @retval The ETH MTL IT Source enabled or disabled
+  */
+#define __HAL_ETH_MTL_GET_IT(__HANDLE__, __INTERRUPT__) \
+  (((__HANDLE__)->Instance->MTLISR &  (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Gets the ETHERNET MTL IT pending bit.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __Q__   : MTL Queue
+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_MTL_Interrupts
+  * @retval The state of ETH MTL IT (SET or RESET)
+  */
+#define __HAL_ETH_MTL_Q_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__, __Q__) \
+  (((__HANDLE__)->Instance->MTL_QUEUE[__Q__].MTLQICSR &  (__INTERRUPT__)) == (__INTERRUPT__))
+/**
+  * @brief  Disables the specified ETHERNET MTL interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __Q__   : MTL Queue
+  * @param  __INTERRUPT__: specifies the ETHERNET MTL interrupt sources to be
+  *   disabled @ref ETH_MTL_Interrupts
+  * @retval None
+  */
+
+#define __HAL_ETH_MTL_Q_DISABLE_IT(__HANDLE__, __INTERRUPT__, __Q__) \
+  ((__HANDLE__)->Instance->MTL_QUEUE[__Q__].MTLQICSR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Enables the specified ETHERNET MAC interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled @ref ETH_MAC_Interrupts
+  * @retval None
+  */
+
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified ETHERNET MAC interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled @ref ETH_MAC_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
+  * @retval The state of ETH MAC IT (SET or RESET).
+  */
+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACISR &\
+                                                                              ( __INTERRUPT__)) == ( __INTERRUPT__))
+
+/*!< External interrupt line 51 Connected to the ETH wakeup EXTI Line */
+#define ETH_WAKEUP_EXTI_LINE  0x00080000U  /* !<  IM51 in EXTI IMR2 register is bit 19 */
+
+/**
+  * @brief Enable the ETH WAKEUP Exti Line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval EXTI ETH WAKEUP Line Status.
+  */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->IMR2 & (__EXTI_LINE__))
+
+/**
+  * @brief Clear the ETH WAKEUP Exti flag.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->IMR2 = (__EXTI_LINE__))
+
+/**
+  * @brief  enable rising edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
+  (EXTI->RTSR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief  enable falling edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
+  (EXTI->FTSR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief  enable falling edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
+  (EXTI->FTSR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
+#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
+                                                           (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Include ETH HAL Extension module */
+#include "stm32n6xx_hal_eth_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup ETH_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de initialization functions  **********************************/
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
+                                           pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
+
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
+HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
+                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
+HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
+
+#ifdef HAL_ETH_USE_PTP
+HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
+                                            ETH_TimeTypeDef *timeoffset);
+HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
+#endif /* HAL_ETH_USE_PTP */
+
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
+
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                           uint32_t RegValue);
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                          uint32_t *pRegValue);
+
+void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_RxAllocateCallback(uint8_t **buff);
+void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
+void              HAL_ETH_TxFreeCallback(uint32_t *buff);
+void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* MAC & DMA Configuration APIs  **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
+
+/* MAC VLAN Processing APIs    ************************************************/
+void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
+                                              uint32_t VLANIdentifier);
+
+/* MAC L2 Packet Filtering APIs  **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
+                                                const uint8_t *pMACAddr);
+
+/* MAC Power Down APIs    *****************************************************/
+void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
+                                             const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
+void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
+
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions  **************************************************/
+HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_ETH_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_eth_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_eth_ex.h
new file mode 100644
index 000000000..cf3e52108
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_eth_ex.h
@@ -0,0 +1,738 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_eth_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of ETH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_ETH_EX_H
+#define STM32N6xx_HAL_ETH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(ETH1)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ETHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ETH RX VLAN structure definition
+  */
+typedef struct
+{
+  FunctionalState InnerVLANTagInStatus;      /*!< Enables or disables Inner VLAN Tag in Rx Status  */
+
+  uint32_t StripInnerVLANTag;                /*!< Sets the Inner VLAN Tag Stripping on Receive
+                                                  This parameter can be a value of
+                                                  @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
+
+  FunctionalState InnerVLANTag;              /*!< Enables or disables Inner VLAN Tag */
+
+  FunctionalState DoubleVLANProcessing;      /*!< Enable or Disable double VLAN processing */
+
+  FunctionalState VLANTagHashTableMatch;     /*!< Enable or Disable VLAN Tag Hash Table Match */
+
+  FunctionalState VLANTagInStatus;           /*!< Enable or Disable VLAN Tag in Rx status */
+
+  uint32_t StripVLANTag;                     /*!< Set the VLAN Tag Stripping on Receive
+                                                  This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
+
+  uint32_t VLANTypeCheck;                    /*!< Enable or Disable VLAN Type Check
+                                                  This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
+
+  FunctionalState VLANTagInverseMatch;       /*!< Enable or disable VLAN Tag Inverse Match */
+
+  FunctionalState BitVLANcomparison;         /*!< Enable 12-Bit VLAN Tag Comparison */
+
+  uint32_t        VLANcomparison;            /*!< 12-bit or 16-bit VLAN comparison */
+
+  FunctionalState VLANTagEnable;             /*!< VLAN Tag Enable */
+
+  uint32_t        VLANTagID;                 /*!< VLAN Tag ID */
+
+  uint32_t        RxDMAChannelNumber;          /*!< Rx DMA Channel Number  */
+
+  FunctionalState DMAChannelNumberEnable;    /*!< Enable Rx DMA Channel Number */
+} ETH_RxVLANConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH MAC TMRQR INDIRECT REG enum definition
+  */
+typedef enum
+{
+  ETH_IND_REG_0    = 0x00000000U,   /*!<  Indirect register 0 */
+  ETH_IND_REG_1    = 0x00000001U,   /*!<  Indirect register 1 */
+  ETH_IND_REG_2    = 0x00000002U,   /*!<  Indirect register 2 */
+  ETH_IND_REG_3    = 0x00000003U,   /*!<  Indirect register 3 */
+  ETH_IND_REG_4    = 0x00000004U,   /*!<  Indirect register 4 */
+  ETH_IND_REG_5    = 0x00000005U,   /*!<  Indirect register 5 */
+  ETH_IND_REG_6    = 0x00000006U,   /*!<  Indirect register 6 */
+  ETH_IND_REG_7    = 0x00000007U    /*!<  Indirect register 7 */
+} ETH_IDRegTypeDef;
+/**
+  *
+  */
+/**
+  * @brief  ETH MAC_MTL Mapping Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t                VLANTagFilterFailPacketsQueue;                  /*!< Specifies the Rx queue to which the tagged packets fail DA/SA/VLANtag filter must be routed to */
+
+  FunctionalState         VLANTagFilterFailPacketsQueuingEnable;          /*!< Enables routing the tagged packets fail DA/SA/VLANtag filter to Rx queue */
+
+  uint32_t                MulticastAddFilterFailPacketsQueue;             /*!< Specifies the Rx queue to which the Multicast packets fail the DA/SA filter are routed to */
+
+  FunctionalState         MulticastAddrFilterFailPacketsQueuingEnable;    /*!< Enables routing Multicast Packets fail DA/SA filter to Rx Queue programmed in MFFQ */
+
+  uint32_t                UnicastAddrFilterFailPacketsQueue;              /*!< Specifies the Rx queue to which the Unicast packets fail the DA/SA filter are routed to */
+
+  FunctionalState         UnicastAddrFilterFailPacketsQueuingEnable;      /*!< Enables routing Unicast Packets fail DA/SA filter to Rx Queue programmed in UFFQ */
+
+  FunctionalState         TypeFieldBasedRxQueuingEnable;                  /*!< Enables Type field based Rx queuing */
+
+  uint32_t                OverridingMCBCQueuePrioritySelect;              /*!< Select the Overriding MC-BC queue priority  */
+
+  uint32_t                FramePreemptionResidueQueue;                    /*!< Specifies the Rx queue to which the residual preemption frames must be forwarded */
+
+  uint32_t                TaggedPTPoEPacketsQueuingControl;               /*!< Specifies the routing of the VLAN tagged PTPoE packets */
+
+  FunctionalState         TaggedAVControlPacketsQueuingEnable;            /*!< Enable MAC routes the received Tagged AV control packets to Rx queue specified by AVCPQ field */
+
+  FunctionalState         MulticastBroadcastQueueEnable;                  /*!< Specifies that Multicast or Broadcast packets routing to the Rx queue is enabled */
+
+  uint32_t                MulticastBroadcastQueue;                        /*!< Specifies the Rx queue onto which Multicast or Broadcast packets are routed */
+
+  uint32_t                UntaggedPacketQueue;                            /*!< Specifies the Rx queue to which Untagged Packets are to be routed */
+
+  uint32_t                PTPPacketsQueue;                                /*!< Specifies the Rx queue on which the PTP packets sent over the Ethernet payload */
+
+  uint32_t                AVUntaggedControlPacketsQueue;                  /*!< Specifies the Receive queue to receive AV untagged control packets */
+
+  uint32_t                PrioritiesSelectedRxQ0;                         /*!< Specifies the Priorities Selected in the Receive Queue 0 @ref ETHEx_Rx_VLAN_PRIO */
+
+  uint32_t                PrioritiesSelectedRxQ1;                         /*!< Specifies the Priorities Selected in the Receive Queue 1 @ref ETHEx_Rx_VLAN_PRIO */
+
+
+} ETH_MACMTLMappingTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH MTL Queue Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t               QueueOpMode;                     /*!< Queue Disabled, Enabled or AV Mode. */
+
+  uint32_t               AVAlgorithm;                     /*!< Queue Disabled, Enabled or AV Mode. */
+
+  uint32_t               TxQueueSize;                     /*!< Specifies the Tx Queue Size */
+
+  uint32_t               TransmitQueueMode;               /*!< Specifies the Transmit Queue operating mode.*/
+} MTL_TxQueueInstance_t;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH MTL Queue Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t               QueueOpMode;                     /*!< Queue Disabled, Enabled or AV Mode. */
+
+  uint32_t               RxQueueSize;                     /*!< Specifies the Rx Queue Size */
+
+  FunctionalState        DropTCPIPChecksumErrorPacket;    /*!< Enables or disables Dropping of TCPIP Checksum Error Packets.*/
+
+  FunctionalState        ForwardRxErrorPacket;            /*!< Enables or disables  forwarding Error Packets. */
+
+  FunctionalState        ForwardRxUndersizedGoodPacket;   /*!< Enables or disables  forwarding Undersized Good Packets.*/
+
+  uint32_t               ReceiveQueueMode;                /*!< Specifies the Receive Queue operating mode */
+
+  uint32_t               MappedToDMACh;                   /*!< Specifies the DMA Channel to which MTL Q is mapped */
+
+} MTL_RxQueueInstance_t;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH MTL Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t                TxSchedulingAlgorithm;        /*!< Specifies the algorithm for Tx scheduling */
+
+  uint32_t                ReceiveArbitrationAlgorithm;  /*!< Specifies the arbitration algorithm for the Rx side */
+
+  MTL_TxQueueInstance_t   TxQ[ETH_MTL_TX_Q_CNT];        /*!< MTL Tx Queue Configuration */
+
+  MTL_RxQueueInstance_t   RxQ[ETH_MTL_RX_Q_CNT];        /*!< MTL Rx Queue Configuration */
+
+  FunctionalState         TransmitStatus;               /*!< Enables or disables forwarding Tx Packet Status to the application. */
+
+} ETH_MTLConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Packet TYPE Queue Configuration structure definition
+  */
+typedef struct
+{
+  ETH_IDRegTypeDef Address; /*!< Sets Address Offset for indirect accesses to ETH_MAC_TMRQR */
+
+  uint32_t Type;          /*!< Indicates the type value of packet that needs to be compared with the received packet. */
+
+  uint32_t Queue;         /*!< Indicates the receive queue number to which the packet needs to be forwarded */
+
+  uint32_t Preemption;    /*!< Preemption or Express Packet
+                                This parameter can be a value of @ref ETHEx_Preemption_Packet */
+} ETH_PacketTypeQueueConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH TX VLAN structure definition
+  */
+typedef struct
+{
+  FunctionalState SourceTxDesc;   /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
+
+  FunctionalState SVLANType;      /*!< Enable or Disable insertion of SVLAN type */
+
+  uint32_t VLANTagControl;        /*!< Sets the VLAN tag control in tx packets
+                                      This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
+} ETH_TxVLANConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH L3 filter structure definition
+  */
+typedef struct
+{
+  uint32_t Protocol;                /*!< Sets the L3 filter protocol to IPv4 or IPv6
+                                         This parameter can be a value of @ref ETHEx_L3_Protocol */
+
+  uint32_t SrcAddrFilterMatch;      /*!< Sets the L3 filter source address match
+                                         This parameter can be a value of @ref ETHEx_L3_Source_Match */
+
+  uint32_t DestAddrFilterMatch;     /*!< Sets the L3 filter destination address match
+                                         This parameter can be a value of @ref ETHEx_L3_Destination_Match */
+
+  uint32_t SrcAddrHigherBitsMatch;  /*!< Sets the L3 filter source address higher bits match
+                                         This parameter can be a value from 0 to 31 */
+
+  uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
+                                         This parameter can be a value from 0 to 31 */
+
+  uint32_t Ip4SrcAddr;              /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
+                                         This parameter can be a value from 0x0 to 0xFFFFFFFF */
+
+  uint32_t Ip4DestAddr;             /*!< Sets the L3 filter IPv4 destination  address if IPv4 protocol is used
+                                         This parameter can be a value from 0 to 0xFFFFFFFF  */
+
+  uint32_t Ip6Addr[4];                 /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
+                                          This parameter must be a table of 4 words (4* 32 bits) */
+} ETH_L3FilterConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH L4 filter structure definition
+  */
+typedef struct
+{
+  uint32_t Protocol;               /*!< Sets the L4 filter protocol to TCP or UDP
+                                        This parameter can be a value of @ref ETHEx_L4_Protocol */
+
+  uint32_t SrcPortFilterMatch;     /*!< Sets the L4 filter source port match
+                                        This parameter can be a value of @ref ETHEx_L4_Source_Match */
+
+  uint32_t DestPortFilterMatch;    /*!< Sets the L4 filter destination port match
+                                        This parameter can be a value of @ref ETHEx_L4_Destination_Match */
+
+  uint32_t SourcePort;             /*!< Sets the L4 filter source port
+                                        This parameter must be a value from 0x0 to 0xFFFF */
+
+  uint32_t DestinationPort;        /*!< Sets the L4 filter destination port
+                                        This parameter must be a value from 0x0 to 0xFFFF */
+} ETH_L4FilterConfigTypeDef;
+/**
+  *
+  */
+
+#ifdef HAL_ETH_USE_CBS
+/**
+  * @brief  ETH CBS Algorithm components
+  */
+typedef struct
+{
+  uint32_t               QueueIdx;            /*!< Specifies the queue Index to be configured  */
+
+  uint32_t               SlotCount;           /*!< Specifies number of slots  */
+
+  uint32_t               CreditControl;       /*!< Specifies Credit Control mode  */
+
+  uint32_t               IdleSlope;           /*!< idleSlopeCredit value required for the CBS algorithm */
+
+  uint32_t               SendSlope;           /*!< sendSlope value required for the CBS algorithm */
+
+  uint32_t               HiCredit;            /*!< hiCredit value required for the CBS algorithm */
+
+  uint32_t               LoCredit;            /*!< loCredit value required for the CBS algorithm */
+
+} ETH_CBSConfigTypeDef;
+/**
+  *
+  */
+
+#endif /* HAL_ETH_USE_CBS */
+
+#ifdef HAL_ETH_USE_TAS
+/**
+  * @brief  ETH TAS Operation components
+  */
+typedef struct
+{
+  uint32_t Gate;                         /*! Gate status Open or Closed */
+
+  uint32_t Interval;                     /*! Time interval valid gate control */
+
+} ETH_TASOperationConfigTypeDef;
+
+/**
+  * @brief  ETH TAS Operation components
+  */
+typedef struct
+{
+  uint64_t         BaseTimeRegister;                         /*! Base Time 32 bits seconds 32 bits nanoseconds */
+
+  uint64_t         CycleTimeRegister;                        /*! Cycle Time 32 bits seconds 32 bits nanoseconds */
+
+  uint32_t         TimeExtensionRegister;                    /*! Time Extension 32 bits seconds 32 bits nanoseconds */
+
+  uint32_t         ListLengthRegister;                       /*! GCL list Length */
+
+  ETH_TASOperationConfigTypeDef *opList;                     /*! Pointer to GCL list size */
+
+} ETH_GCLConfigTypeDef;
+
+/**
+  * @brief  ETH Enhancements to Scheduled Traffic components
+  */
+typedef struct
+{
+  uint32_t                  SwitchToSWOL;                      /*! Switch to S/W owned list */
+
+  uint32_t                  PTPTimeOffset;                     /*! PTP Time Offset Value */
+
+  uint32_t                  CurrentTimeOffset;                 /*! Current Time Offset Value */
+
+  uint32_t                  TimeIntervalLeftShift;             /*! Time Interval Left Shift Amount */
+
+  uint32_t                  LoopCountSchedulingError;          /*! Loop Count to report Scheduling Error */
+
+  FunctionalState           DropFramesCausingError;            /*! Drop Frames causing Scheduling Error */
+
+  FunctionalState           NotDropFramesDuringFrameSizeError; /*! Drop Frames causing Scheduling Error */
+
+  uint32_t                  OverheadBytesValue;                /*! Overhead Bytes Value */
+
+  ETH_GCLConfigTypeDef      GCLRegisters;                     /*! Pointer to GCL Registers */
+
+} ETH_ESTConfigTypeDef;
+/**
+  *
+  */
+#endif /* HAL_ETH_USE_TAS */
+
+#ifdef HAL_ETH_USE_FPE
+/**
+  * @brief  ETH Frame Preemption components
+  */
+typedef struct
+{
+  uint32_t            AdditionalFragmentSize;   /*! Additional Fragment Size */
+
+  uint32_t            PreemptionClassification; /*! Preemption Classification
+                                      This parameter can be a combination of @ref ETHEx_FPE_Preemption_Classification*/
+
+  uint32_t            HoldReleaseStatus;        /*! Hold/Release Status */
+
+  FunctionalState     SendVerifymPacket;        /*! Send Verify mPacket */
+
+  FunctionalState     SendRespondmPacket;       /*! Send Respond mPacket */
+
+  uint32_t            HoldAdvance;              /*! The maximum time in nanoseconds that can elapse between issuing a
+                                               HOLD to the MAC and the MAC ceasing to transmit any preemptible frame */
+  uint32_t            ReleaseAdvance;           /*! The maximum time in nanoseconds that can elapse between issuing a
+                             RELEASE to the MAC and the MAC being ready to resume transmission of preemptible frames */
+} ETH_FPEConfigTypeDef;
+/**
+  *
+  */
+#endif /* HAL_ETH_USE_FPE */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
+  * @{
+  */
+
+/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
+  * @{
+  */
+#define ETH_TX_LPI_ENTRY    ETH_MACLCSR_TLPIEN
+#define ETH_TX_LPI_EXIT     ETH_MACLCSR_TLPIEX
+#define ETH_RX_LPI_ENTRY    ETH_MACLCSR_RLPIEN
+#define ETH_RX_LPI_EXIT     ETH_MACLCSR_RLPIEX
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
+  * @{
+  */
+#define ETH_L3_FILTER_0                 0x00000000U
+#define ETH_L3_FILTER_1                 0x0000000CU
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
+  * @{
+  */
+#define ETH_L4_FILTER_0                 0x00000000U
+#define ETH_L4_FILTER_1                 0x0000000CU
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
+  * @{
+  */
+#define ETH_L3_IPV6_MATCH                       ETH_MACL3L4C0R_L3PEN0
+#define ETH_L3_IPV4_MATCH                       0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
+  * @{
+  */
+#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE    ETH_MACL3L4C0R_L3SAM0
+#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE    (ETH_MACL3L4C0R_L3SAM0 | ETH_MACL3L4C0R_L3SAIM0)
+#define ETH_L3_SRC_ADDR_MATCH_DISABLE           0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
+  * @{
+  */
+#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE   ETH_MACL3L4C0R_L3DAM0
+#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE   (ETH_MACL3L4C0R_L3DAM0 | ETH_MACL3L4C0R_L3DAIM0)
+#define ETH_L3_DEST_ADDR_MATCH_DISABLE          0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
+  * @{
+  */
+#define ETH_L4_UDP_MATCH                        ETH_MACL3L4C0R_L4PEN0
+#define ETH_L4_TCP_MATCH                        0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
+  * @{
+  */
+#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE    ETH_MACL3L4C0R_L4SPM0
+#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE    (ETH_MACL3L4C0R_L4SPM0 |ETH_MACL3L4C0R_L4SPIM0)
+#define ETH_L4_SRC_PORT_MATCH_DISABLE           0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
+  * @{
+  */
+#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE   ETH_MACL3L4C0R_L4DPM0
+#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE   (ETH_MACL3L4C0R_L4DPM0 | ETH_MACL3L4C0R_L4DPIM0)
+#define ETH_L4_DEST_PORT_MATCH_DISABLE          0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
+  * @{
+  */
+#define ETH_INNERVLANTAGRXSTRIPPING_NONE      ETH_MACVTCR_EIVLS_DONOTSTRIP
+#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS    ETH_MACVTCR_EIVLS_STRIPIFPASS
+#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTCR_EIVLS_STRIPIFFAILS
+#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTCR_EIVLS_ALWAYSSTRIP
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
+  * @{
+  */
+#define ETH_VLANTAGRXSTRIPPING_NONE      ETH_MACVTCR_EVLS_DONOTSTRIP
+#define ETH_VLANTAGRXSTRIPPING_IFPASS    ETH_MACVTCR_EVLS_STRIPIFPASS
+#define ETH_VLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTCR_EVLS_STRIPIFFAILS
+#define ETH_VLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTCR_EVLS_ALWAYSSTRIP
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
+  * @{
+  */
+#define ETH_VLANTYPECHECK_DISABLE    ETH_MACVTCR_DOVLTC
+#define ETH_VLANTYPECHECK_SVLAN      (ETH_MACVTCR_ERSVLM | ETH_MACVTCR_ESVL)
+#define ETH_VLANTYPECHECK_CVLAN      0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
+  * @{
+  */
+#define ETH_VLANTAGCONTROL_NONE       (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
+#define ETH_VLANTAGCONTROL_DELETE     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
+#define ETH_VLANTAGCONTROL_INSERT     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
+#define ETH_VLANTAGCONTROL_REPLACE    (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
+  * @{
+  */
+#define ETH_INNER_TX_VLANTAG    0x00000001U
+#define ETH_OUTER_TX_VLANTAG    0x00000000U
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Rx_VLAN_PRIO ETHEx Rx VLAN PRIO
+  * @{
+  */
+#define  ETH_RX_QUEUE_PRIO_0   0x00000001U    /*!<  Rx VLAN User Tag Priority 0 */
+#define  ETH_RX_QUEUE_PRIO_1   0x00000002U    /*!<  Rx VLAN User Tag Priority 1 */
+#define  ETH_RX_QUEUE_PRIO_2   0x00000004U    /*!<  Rx VLAN User Tag Priority 2 */
+#define  ETH_RX_QUEUE_PRIO_3   0x00000008U    /*!<  Rx VLAN User Tag Priority 3 */
+#define  ETH_RX_QUEUE_PRIO_4   0x00000010U    /*!<  Rx VLAN User Tag Priority 4 */
+#define  ETH_RX_QUEUE_PRIO_5   0x00000020U    /*!<  Rx VLAN User Tag Priority 5 */
+#define  ETH_RX_QUEUE_PRIO_6   0x00000040U    /*!<  Rx VLAN User Tag Priority 6 */
+#define  ETH_RX_QUEUE_PRIO_7   0x00000080U    /*!<  Rx VLAN User Tag Priority 7 */
+/**
+  *
+  */
+
+/** @defgroup ETHEx_Preemption_Packet ETHEx Preemption Packet
+  * @{
+  */
+#define ETH_EXPRESS_PACKET           0x00000000U
+#define ETH_PREEMPTION_PACKET        ETH_MACTMRQR_PFEX
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Command_Type ETHEx Command Type
+  * @{
+  */
+#define ETH_WRITE_OPERATION          0x00000000U
+#define ETH_READ_OPERATION           ETH_MACIACR_COM
+/**
+  * @}
+  */
+
+#ifdef HAL_ETH_USE_CBS
+/** @defgroup ETHEx_CBS_Credit_Control ETHEx CBS Credit Control
+  * @{
+  */
+#define ETH_ENABLE_CBS_CREDIT_CONTROL    ETH_MTLTXQ1ECR_CC
+#define ETH_DISABLE_CBS_CREDIT_CONTROL   0x00000000U
+/**
+  * @}
+  */
+#endif /* HAL_ETH_USE_CBS */
+
+#ifdef HAL_ETH_USE_TAS
+#ifndef ETH_HWRESET_TIMEOUT
+#define ETH_HWRESET_TIMEOUT     1000U
+#endif /* ETH_SWRESET_TIMEOUT */
+#endif /* HAL_ETH_USE_TAS */
+
+#ifdef HAL_ETH_USE_FPE
+/** @defgroup ETHEx_FPE_Preemption_Classification ETHEx FPE Preemption Classification
+  * @{
+  */
+#define ETH_QUEUE0_EXPRESS         0x00000000U
+#define ETH_QUEUE0_PREEMPTABLE     0x00000100U
+#define ETH_QUEUE1_EXPRESS         0x00000000U
+#define ETH_QUEUE1_PREEMPTABLE     0x00000200U
+/**
+  * @}
+  */
+#endif /* HAL_ETH_USE_FPE */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ETHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ETHEx_Exported_Functions_Group1
+  * @{
+  */
+/* MAC ARP Offloading APIs  ***************************************************/
+void              HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
+
+/* MAC L3 L4 Filtering APIs ***************************************************/
+void              HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+
+/* MAC VLAN Processing APIs    ************************************************/
+void              HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+void              HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            ETH_TxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            const ETH_TxVLANConfigTypeDef *pVlanConfig);
+void              HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
+
+/* Energy Efficient Ethernet APIs *********************************************/
+void              HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
+                                         FunctionalState TxClockStop);
+void              HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
+uint32_t          HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
+/* Multi-Queue Ethernet APIs *********************************************/
+uint32_t          HAL_ETHEx_GetRxDMAChNumber(const ETH_HandleTypeDef *heth);
+uint32_t          HAL_ETHEx_GetTxDMAChNumber(const ETH_HandleTypeDef *heth);
+uint32_t          HAL_ETHEx_GetRxMTLQNumber(const ETH_HandleTypeDef *heth);
+uint32_t          HAL_ETHEx_GetTxMTLQNumber(const ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetMTLConfig(const ETH_HandleTypeDef *heth, ETH_MTLConfigTypeDef *mtlconf);
+HAL_StatusTypeDef HAL_ETHEx_SetMTLConfig(ETH_HandleTypeDef *heth, ETH_MTLConfigTypeDef *mtlconf);
+HAL_StatusTypeDef HAL_ETHEx_SetMACMTLMappingConfig(ETH_HandleTypeDef *heth, const ETH_MACMTLMappingTypeDef *macmtlconf);
+HAL_StatusTypeDef HAL_ETHEx_GetMACMTLMappingConfig(const ETH_HandleTypeDef *heth, ETH_MACMTLMappingTypeDef *macmtlconf);
+void              ETHEx_SetMTLConfig(ETH_HandleTypeDef *heth, const ETH_MTLConfigTypeDef *mtlconf);
+HAL_StatusTypeDef ETHEx_SetMACMTLMappingConfig(ETH_HandleTypeDef *heth, const ETH_MACMTLMappingTypeDef *macmtlconf);
+HAL_StatusTypeDef HAL_ETHEx_SetUserTagPriorityQueue(ETH_HandleTypeDef *heth, uint32_t psrq, uint32_t queue);
+HAL_StatusTypeDef HAL_ETHEx_GetUserTagPriorityQueue(const ETH_HandleTypeDef *heth, uint32_t *psrq,
+                                                    uint32_t queue);
+HAL_StatusTypeDef HAL_ETHEx_SetPacketTypeQueue(ETH_HandleTypeDef *heth,
+                                               const ETH_PacketTypeQueueConfigTypeDef *typequeueconf);
+HAL_StatusTypeDef HAL_ETHEx_GetPacketTypeQueue(ETH_HandleTypeDef *heth,
+                                               ETH_PacketTypeQueueConfigTypeDef *typequeueconf);
+#ifdef HAL_ETH_USE_CBS
+HAL_StatusTypeDef HAL_ETHEx_SetCBSConfig(ETH_HandleTypeDef *heth, ETH_CBSConfigTypeDef *cbsconf);
+HAL_StatusTypeDef HAL_ETHEx_GetCBSConfig(const ETH_HandleTypeDef *heth,
+                                         ETH_CBSConfigTypeDef *pCBSConfig, uint8_t queueIndex);
+HAL_StatusTypeDef HAL_ETHEx_EnableCBS(ETH_HandleTypeDef *heth, uint8_t queueIndex);
+#endif /* HAL_ETH_USE_CBS */
+#ifdef HAL_ETH_USE_TAS
+uint32_t          HAL_ETHEx_GetGCLDepth(const ETH_HandleTypeDef *heth);
+uint32_t          HAL_ETHEx_GetGCLWidthTimeInterval(const ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_EnableEST(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_DisableEST(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_SetESTConfig(ETH_HandleTypeDef *heth,  ETH_ESTConfigTypeDef *estconf);
+HAL_StatusTypeDef HAL_ETHEx_SetGCLRegisters(ETH_HandleTypeDef *heth, const ETH_GCLConfigTypeDef *gclconf);
+HAL_StatusTypeDef HAL_ETHEx_SetGCLConfig(ETH_HandleTypeDef *heth, ETH_GCLConfigTypeDef *gclconf);
+HAL_StatusTypeDef HAL_ETHEx_GetGCLRegisters(ETH_HandleTypeDef *heth, ETH_GCLConfigTypeDef *gclconf);
+#endif /* HAL_ETH_USE_TAS */
+#ifdef HAL_ETH_USE_FPE
+HAL_StatusTypeDef HAL_ETHEx_EnableFPE(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_DisableFPE(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetFPEConfig(ETH_HandleTypeDef *heth,  ETH_FPEConfigTypeDef *fpeconf);
+HAL_StatusTypeDef HAL_ETHEx_SetFPEConfig(ETH_HandleTypeDef *heth,  ETH_FPEConfigTypeDef *fpeconf);
+#endif /* HAL_ETH_USE_FPE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_ETH_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_exti.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_exti.h
new file mode 100644
index 000000000..7fb168f21
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_exti.h
@@ -0,0 +1,413 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_exti.h
+  * @author  GPM Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_EXTI_H
+#define STM32N6xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,
+  HAL_EXTI_RISING_CB_ID          = 0x01U,
+  HAL_EXTI_FALLING_CB_ID         = 0x02U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* RisingCallback)(void);    /*!<  Exti rising callback */
+  void (* FallingCallback)(void);   /*!<  Exti falling callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter
+                           can be a value of @ref EXTI_Line */
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
+                           This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
+                           can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
+                           This parameter is only possible for line 0 to 15. It
+                           can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x00U)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x01U)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x02U)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x03U)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x04U)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x05U)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x06U)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x07U)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x08U)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x09U)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0AU)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0BU)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0CU)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0DU)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0EU)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | EXTI_EVENT | 0x0FU)
+#define EXTI_LINE_16                        (EXTI_RESERVED | EXTI_REG1              | 0x10U)
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x11U)
+#define EXTI_LINE_18                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x12U)
+#define EXTI_LINE_19                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x13U)
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x14U)
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | EXTI_EVENT | 0x15U)
+#define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x16U)
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x17U)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x18U)
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x19U)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1AU)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1BU)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1CU)
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1DU)
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1EU)
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | EXTI_EVENT | 0x1FU)
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x00U)
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x01U)
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x02U)
+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x03U)
+#define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x04U)
+#define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x05U)
+#define EXTI_LINE_38                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x06U)
+#define EXTI_LINE_39                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x07U)
+#define EXTI_LINE_40                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x08U)
+#define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x09U)
+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x0AU)
+#define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x0BU)
+#define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x0CU)
+#define EXTI_LINE_45                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x0DU)
+#define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x0EU)
+#define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x0FU)
+#define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x10U)
+#define EXTI_LINE_49                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x11U)
+#define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x12U)
+#define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x13U)
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x14U)
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x15U)
+#define EXTI_LINE_54                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x16U)
+#define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x17U)
+#define EXTI_LINE_56                        (EXTI_CONFIG   | EXTI_REG2 | EXTI_EVENT | 0x18U)
+#define EXTI_LINE_57                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x19U)
+#define EXTI_LINE_58                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x1AU)
+#define EXTI_LINE_59                        (EXTI_RESERVED | EXTI_REG2              | 0x1BU)
+#define EXTI_LINE_60                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x1CU)
+#define EXTI_LINE_61                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x1DU)
+#define EXTI_LINE_62                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x1EU)
+#define EXTI_LINE_63                        (EXTI_DIRECT   | EXTI_REG2 | EXTI_EVENT | 0x1FU)
+#define EXTI_LINE_64                        (EXTI_DIRECT   | EXTI_REG3 | EXTI_EVENT | 0x00U)
+#define EXTI_LINE_65                        (EXTI_DIRECT   | EXTI_REG3 | EXTI_EVENT | 0x01U)
+#define EXTI_LINE_66                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x02U)
+#define EXTI_LINE_67                        (EXTI_RESERVED | EXTI_REG3              | 0x03U)
+#define EXTI_LINE_68                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x04U)
+#define EXTI_LINE_69                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x05U)
+#define EXTI_LINE_70                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x06U)
+#define EXTI_LINE_71                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x07U)
+#define EXTI_LINE_72                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x08U)
+#define EXTI_LINE_73                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x09U)
+#define EXTI_LINE_74                        (EXTI_CONFIG   | EXTI_REG3 | EXTI_EVENT | 0x0AU)
+#define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_REG3              | 0x0BU)
+#define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_REG3              | 0x0CU)
+#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_REG3 | EXTI_EVENT | 0x0DU)
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000U
+#define EXTI_MODE_INTERRUPT                 0x00000001U
+#define EXTI_MODE_EVENT                     0x00000002U
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000U
+#define EXTI_TRIGGER_RISING                 0x00000001U
+#define EXTI_TRIGGER_FALLING                0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000U
+#define EXTI_GPIOB                          0x00000001U
+#define EXTI_GPIOC                          0x00000002U
+#define EXTI_GPIOD                          0x00000003U
+#define EXTI_GPIOE                          0x00000004U
+#define EXTI_GPIOF                          0x00000005U
+#define EXTI_GPIOG                          0x00000006U
+#define EXTI_GPIOH                          0x00000007U
+#define EXTI_GPION                          0x00000008U
+#define EXTI_GPIOO                          0x00000009U
+#define EXTI_GPIOP                          0x0000000AU
+#define EXTI_GPIOQ                          0x0000000BU
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Line_attributes EXTI line attributes
+  * @brief EXTI line secure or non-secure and privileged or non-privileged attributes
+  * @note secure and non-secure attributes are only available from secure state
+  * @{
+  */
+#define  EXTI_LINE_SEC                  (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U)   /*!< Secure line attribute          */
+#define  EXTI_LINE_NSEC                 (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U)   /*!< Non-secure line attribute      */
+#define  EXTI_LINE_PRIV                 (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U)   /*!< Privileged line attribute     */
+#define  EXTI_LINE_NPRIV                (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U)   /*!< Non-privileged line attribute */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+
+/**
+  * @brief  EXTI Event presence definition
+ */
+#define EXTI_EVENT_PRESENCE_SHIFT           28U
+#define EXTI_EVENT                          (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
+#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)
+
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                 24U
+#define EXTI_DIRECT                         (0x01U << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02U << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08U << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16U
+#define EXTI_REG1                           (0x00U << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01U << EXTI_REG_SHIFT)
+#define EXTI_REG3                           (0x02U << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
+#define EXTI_PIN_MASK                       0x0000001FU
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#define EXTI_LINE_NB                        78U
+
+
+/**
+  * @brief  EXTI Mask for secure & privilege attributes
+  */
+#define EXTI_LINE_ATTR_SEC_MASK             0x100U
+#define EXTI_LINE_ATTR_PRIV_MASK            0x200U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
+                                         ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
+                                          (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
+                                          (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
+                                         ((((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                           (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))) || \
+                                          (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x0002000DUL)))
+
+#define IS_EXTI_MODE(__LINE__)          ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \
+                                         (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+
+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \
+                                         ((__LINE__) == EXTI_TRIGGER_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00U)
+
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPION) || \
+                                         ((__PORT__) == EXTI_GPIOO) || \
+                                         ((__PORT__) == EXTI_GPIOP) || \
+                                         ((__PORT__) == EXTI_GPIOQ))
+
+#define IS_EXTI_GPIO_PIN(__PIN__)        ((__PIN__) < 16U)
+
+#if defined CPU_IN_SECURE_STATE
+#define IS_EXTI_LINE_ATTRIBUTES(__ATTR__) (((((__ATTR__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \
+                                            (((__ATTR__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \
+                                            (((__ATTR__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
+                                            (((__ATTR__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
+                                           (((__ATTR__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
+#else
+#define IS_EXTI_LINE_ATTRIBUTES(__ATTR__) (((((__ATTR__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
+                                            (((__ATTR__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
+                                           (((__ATTR__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
+                                            void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti);
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
+  * @{
+  */
+
+
+/* EXTI line attributes management functions **********************************/
+void              HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes);
+#if defined CPU_IN_SECURE_STATE
+void              HAL_EXTI_LockAttributes(void);
+uint32_t          HAL_EXTI_GetLockAttributes(void);
+#endif /* CPU_IN_SECURE_STATE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_EXTI_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_fdcan.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_fdcan.h
new file mode 100644
index 000000000..1dcfa0b1b
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_fdcan.h
@@ -0,0 +1,2464 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_fdcan.h
+  * @author  MCD Application Team
+  * @brief   Header file of FDCAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_FDCAN_H
+#define STM32N6xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FDCAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
+  HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
+  HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
+  HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+  * @brief FDCAN Init structure definition
+  */
+typedef struct
+{
+  uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
+                                              This parameter can be a value of @ref FDCAN_frame_format     */
+
+  uint32_t Mode;                         /*!< Specifies the FDCAN mode.
+                                              This parameter can be a value of @ref FDCAN_operating_mode   */
+
+  FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the nominal bit time quanta.
+                                              This parameter must be a number between 1 and 512            */
+
+  uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a bit to perform
+                                              resynchronization.
+                                              This parameter must be a number between 1 and 128            */
+
+  uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
+                                              This parameter must be a number between 2 and 256            */
+
+  uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
+                                              This parameter must be a number between 2 and 128            */
+
+  uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the data bit time quanta.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a data bit to
+                                              perform resynchronization.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
+                                              This parameter must be a number between 0 and 2560           */
+
+  uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
+                                              This parameter must be a number between 0 and 128            */
+
+  uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
+                                              This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+  uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+} FDCAN_InitTypeDef;
+
+/**
+  * @brief  FDCAN clock calibration unit structure definition
+  */
+typedef struct
+{
+  uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
+                                      This parameter can be a value of @ref FDCAN_clock_calibration.       */
+
+  uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
+                                      is bypassed.
+                                      This parameter can be a value of @ref FDCAN_clock_divider            */
+
+  uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
+                                      actual configured number of periods is MinOscClkPeriods x 32.
+                                      This parameter must be a number between 0x00 and 0xFF                */
+
+  uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
+                                      This parameter can be a value of @ref FDCAN_calibration_field_length */
+
+  uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
+                                      This parameter must be a number between 4 and 25                     */
+
+  uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
+                                      If set to zero the counter is disabled.
+                                      This parameter must be a number between 0x0000 and 0xFFFF            */
+
+} FDCAN_ClkCalUnitTypeDef;
+
+/**
+  * @brief  FDCAN filter structure definition
+  */
+typedef struct
+{
+  uint32_t IdType;           /*!< Specifies the identifier type.
+                                  This parameter can be a value of @ref FDCAN_id_type       */
+
+  uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
+                                  This parameter must be a number between:
+                                   - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t FilterType;       /*!< Specifies the filter type.
+                                  This parameter can be a value of @ref FDCAN_filter_type.
+                                  The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
+                                  only when IdType is FDCAN_EXTENDED_ID.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER                                  */
+
+  uint32_t FilterConfig;     /*!< Specifies the filter configuration.
+                                  This parameter can be a value of @ref FDCAN_filter_config */
+
+  uint32_t FilterID1;        /*!< Specifies the filter identification 1.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t FilterID2;        /*!< Specifies the filter identification 2.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
+                                  matching message will be stored.
+                                  This parameter must be a number between 0 and 63.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER                             */
+
+  uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
+                                  calibration messages.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter can be:
+                                   - 0 : ordinary message
+                                   - 1 : calibration message                                */
+
+} FDCAN_FilterTypeDef;
+
+/**
+  * @brief  FDCAN Tx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
+                                     transmitted.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
+                                      This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
+                                     bit rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
+                                     FD format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
+                                     This parameter can be a value of @ref FDCAN_EFC                   */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
+                                     element for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Rx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;            /*!< Specifies the identifier.
+                                       This parameter must be a number between:
+                                        - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;                /*!< Specifies the identifier type of the received message.
+                                       This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
+                                       This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;            /*!< Specifies the received frame length.
+                                        This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
+                                       This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
+                                       rate switching.
+                                       This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
+                                       format.
+                                       This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
+                                       reception.
+                                       This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
+                                       This parameter must be a number between:
+                                        - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID
+                                       When the frame is a Non-Filter matching frame, this parameter
+                                       is unused.                                                        */
+
+  uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+                                       Acceptance of non-matching frames may be enabled via
+                                       HAL_FDCAN_ConfigGlobalFilter().
+                                       This parameter takes 0 if the frame matched an Rx filter or
+                                       1 if it did not match any Rx filter                               */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Tx event FIFO structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
+                                     This parameter can be a value of @ref FDCAN_data_length_code      */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
+                                     rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
+                                     format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
+                                     transmission.
+                                     This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
+                                     for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+  uint32_t EventType;           /*!< Specifies the event type.
+                                     This parameter can be a value of @ref FDCAN_event_type            */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+  * @brief  FDCAN High Priority Message Status structure definition
+  */
+typedef struct
+{
+  uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
+                                This parameter can be:
+                                 - 0 : Standard Filter List
+                                 - 1 : Extended Filter List                                */
+
+  uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
+                                This parameter can be a number between:
+                                - 0 and 127, if FilterList is 0 (Standard)
+                                - 0 and 63, if FilterList is 1 (Extended)                  */
+
+  uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+                                This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+  uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
+                                message was stored.
+                                This parameter is valid only when MessageStorage is:
+                                  FDCAN_HP_STORAGE_RXFIFO0
+                                 or
+                                  FDCAN_HP_STORAGE_RXFIFO1                                 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+  * @brief FDCAN Protocol Status structure definition
+  */
+typedef struct
+{
+  uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code             */
+
+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
+                                   of a CAN FD format frame with its BRS flag set.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code             */
+
+  uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
+                                   This parameter can be a value of @ref FDCAN_communication_state             */
+
+  uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is in Error_Active state
+                                    - 1 : The FDCAN is in Error_Passive state                                  */
+
+  uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
+                                   This parameter can be:
+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
+                                          Error_Warning limit of 96
+                                    - 1 : at least one of error counters has reached the Error_Warning
+                                          limit of 96                                                          */
+
+  uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is not in Bus_Off state
+                                    - 1 : The FDCAN is in Bus_Off state                                        */
+
+  uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its ESI flag set
+                                    - 1 : Last received CAN FD message had its ESI flag set                    */
+
+  uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its BRS flag set
+                                    - 1 : Last received CAN FD message had its BRS flag set                    */
+
+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received
+                                   since last protocol status.
+                                   This parameter can be:
+                                    - 0 : No CAN FD message received
+                                    - 1 : CAN FD message received                                              */
+
+  uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+                                   This parameter can be:
+                                    - 0 : No protocol exception event occurred since last read access
+                                    - 1 : Protocol exception event occurred                                    */
+
+  uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
+                                   This parameter can be a number between 0 and 127                            */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+  * @brief FDCAN Error Counters structure definition
+  */
+typedef struct
+{
+  uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
+                                This parameter can be a number between 0 and 255                               */
+
+  uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
+                                This parameter can be a number between 0 and 127                               */
+
+  uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+                                This parameter can be:
+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error
+                                       passive level of 128
+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error
+                                       passive level of 128                                                    */
+
+  uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
+                                This parameter can be a number between 0 and 255.
+                                This counter is incremented each time when a FDCAN protocol error causes
+                                the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
+                                the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
+                                FDCAN_FLAG_ERROR_LOGGING_OVERFLOW                                              */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+  * @brief FDCAN TT Init structure definition
+  */
+typedef struct
+{
+  uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
+                                   This parameter can be a value of @ref FDCAN_operation_mode               */
+
+  uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
+                                   This parameter can be a value of @ref FDCAN_TT_operation.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
+                                   This parameter can be a value of @ref FDCAN_TT_time_master               */
+
+  uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
+                                   numerator : TUR = (Numerator +/- SDL) / Denominator.
+                                   With : SDL = 2^(SyncDevLimit+5).
+                                   This parameter must be a number between 0 and 7                          */
+
+  uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
+                                   This parameter must be a number between 0 and 127                        */
+
+  uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
+                                   This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
+                                   which the application has to serve the application watchdog.
+                                   The application watchdog is incremented once each 256 NTUs.
+                                   The application watchdog can be disabled by setting AppWdgLimit to 0.
+                                   This parameter must be a number between 0 and 255.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
+                                   This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
+                                   This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t BasicCyclesNbr;    /*!< Specifies the number of basic cycles in the system matrix.
+                                   This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
+
+  uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
+                                   This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
+
+  uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
+                                   This parameter must be a number between 1 and 16                         */
+
+  uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
+                                   This is the sum of Tx_Triggers for exclusive, single arbitrating and
+                                   merged arbitrating windows.
+                                   This parameter must be a number between 0 and 4095                       */
+
+  uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
+                                   It is advised to set this parameter to the largest applicable value.
+                                   This parameter must be a number between 0x10000 and 0x1FFFF              */
+
+  uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
+                                   This parameter must be a number between 0x0001 and 0x3FFF                */
+
+  uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
+                                   This parameter must be a number between 0 and 64                         */
+
+  uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
+
+  uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
+
+} FDCAN_TT_ConfigTypeDef;
+
+/**
+  * @brief  FDCAN Trigger structure definition
+  */
+typedef struct
+{
+  uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
+                               This parameter must be a number between 0 and 63                                 */
+
+  uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
+                               This parameter must be a number between 0 and 0xFFFF                             */
+
+  uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
+                               This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
+
+  uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
+                               This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+                               This parameter must be a number between 0 and RepeatFactor                       */
+
+  uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
+                               If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
+                               becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
+
+  uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
+                               If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
+                               trigger memory element becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
+
+  uint32_t TriggerType;   /*!< Specifies the trigger type.
+                               This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
+
+  uint32_t FilterType;    /*!< Specifies the filter identifier type.
+                               This parameter can be a value of @ref FDCAN_id_type                              */
+
+  uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
+                               This parameter can be a value of @ref FDCAN_Tx_location.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               transmission.                                                                    */
+
+  uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               reception.
+                               This parameter must be a number between:
+                                - 0 and 127, if FilterType is FDCAN_STANDARD_ID
+                                - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
+
+} FDCAN_TriggerTypeDef;
+
+/**
+  * @brief  FDCAN TT Operation Status structure definition
+  */
+typedef struct
+{
+  uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
+                                  This parameter can be a value of @ref FDCAN_TT_error_level                    */
+
+  uint32_t MasterState;      /*!< Specifies the type of the TT master state.
+                                  This parameter can be a value of @ref FDCAN_TT_master_state                   */
+
+  uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
+                                  This parameter can be a value of @ref FDCAN_TT_sync_state                     */
+
+  uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
+                                  This parameter can be:
+                                   - 0 : Global time not valid
+                                   - 1 : Global time in phase with Time Master                                  */
+
+  uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
+                                  This parameter can be:
+                                   - 0 : Local clock speed not synchronized to Time Master clock speed
+                                   - 1 : Synchronization Deviation = SDL                                        */
+
+  uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
+                                  This parameter can be a number between 0 and 0xFF                             */
+
+  uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
+                                  This parameter can be:
+                                   - 0 : No global time preset pending
+                                   - 1 : Node waits for the global time preset to take effect                   */
+
+  uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
+                                  This parameter can be:
+                                   - 0 : Reset at the end of each reference message
+                                   - 1 : Gap finished                                                           */
+
+  uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
+                                  This parameter can be a number between 0 and 0x7                              */
+
+  uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
+                                  This parameter can be:
+                                   - 0 : No Gap in schedule
+                                   - 1 : Gap time after Basic Cycle has started                                 */
+
+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is announced.
+                                  This parameter can be:
+                                   - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
+                                   - 1 : Reference message with Next_is_Gap = 1 received                        */
+
+  uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
+                                  This parameter can be:
+                                   - 0 : Application Watchdog served in time
+                                   - 1 : Failed to serve Application Watchdog in time                           */
+
+  uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
+                                  This parameter can be:
+                                   - 0 : No external clock synchronization pending
+                                   - 1 : Node waits for external clock synchronization to take effect           */
+
+  uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
+                                  This parameter can be:
+                                   - 0 : Phase outside range
+                                   - 1 : Phase inside range                                                     */
+
+} FDCAN_TTOperationStatusTypeDef;
+
+/**
+  * @brief  FDCAN Message RAM blocks
+  */
+typedef struct
+{
+  uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
+                                  This parameter must be a 32-bit word address      */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+  * @brief  FDCAN handle structure definition
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+  FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
+
+  TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
+
+  FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
+
+  FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
+
+  uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+                                               of latest Tx FIFO/Queue request */
+
+  __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
+
+  HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
+
+  __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
+  void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
+  void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
+  void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
+  void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
+  void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
+  void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
+  void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
+  void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
+  void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
+  void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
+  void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
+  void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
+  void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
+  void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
+  void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
+  void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
+
+  void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
+  void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL FDCAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U,    /*!< FDCAN Tx Fifo Empty callback ID         */
+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U,    /*!< FDCAN Rx buffer new message callback ID */
+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U,    /*!< FDCAN High priority message callback ID */
+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U,    /*!< FDCAN Timestamp wraparound callback ID  */
+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U,    /*!< FDCAN Timeout occurred callback ID      */
+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U,    /*!< FDCAN Error callback ID                 */
+
+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U,    /*!< FDCAN MspInit callback ID               */
+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U,    /*!< FDCAN MspDeInit callback ID             */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL FDCAN Callback pointer definition
+  */
+typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
+typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
+typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
+typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
+typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
+typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
+typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
+typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
+typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
+typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
+typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
+typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+  * @{
+  */
+#define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
+#define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
+#define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
+#define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
+#define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
+#define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
+#define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
+#define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
+#define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
+#define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
+#define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
+#define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+  * @{
+  */
+#define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+  * @{
+  */
+#define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
+#define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
+  * @{
+  */
+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
+#define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+  * @{
+  */
+#define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2  */
+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4  */
+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6  */
+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8  */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
+  * @{
+  */
+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_state FDCAN Calibration State
+  * @{
+  */
+#define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
+#define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
+  * @{
+  */
+#define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
+#define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
+  * @{
+  */
+#define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+  * @{
+  */
+#define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+  * @{
+  */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+  * @{
+  */
+#define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+  * @{
+  */
+#define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00000001U) /*!< 1 bytes data field  */
+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00000002U) /*!< 2 bytes data field  */
+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00000003U) /*!< 3 bytes data field  */
+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00000004U) /*!< 4 bytes data field  */
+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00000005U) /*!< 5 bytes data field  */
+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00000006U) /*!< 6 bytes data field  */
+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00000007U) /*!< 7 bytes data field  */
+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00000008U) /*!< 8 bytes data field  */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+  * @{
+  */
+#define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+  * @{
+  */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_format FDCAN format
+  * @{
+  */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+  * @{
+  */
+#define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+  * @{
+  */
+#define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
+#define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
+#define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+  * @{
+  */
+#define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
+#define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
+#define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
+#define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
+#define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
+#define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+  * @{
+  */
+#define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
+#define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
+#define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
+#define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
+#define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
+#define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
+#define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
+#define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
+#define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
+#define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+  * @{
+  */
+#define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
+#define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
+#define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
+#define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
+#define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
+#define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
+#define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
+#define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
+#define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
+#define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
+#define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
+#define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+  * @{
+  */
+#define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+  * @{
+  */
+#define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
+#define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+  * @{
+  */
+#define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
+#define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
+#define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
+#define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
+#define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
+#define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
+#define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+  * @{
+  */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
+#define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
+#define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
+  * @{
+  */
+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
+#define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
+#define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+  * @{
+  */
+#define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+  * @{
+  */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+  * @{
+  */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+  * @{
+  */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+  * @{
+  */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+  * @{
+  */
+#define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2  */
+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3  */
+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4  */
+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5  */
+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6  */
+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7  */
+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8  */
+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9  */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+  * @{
+  */
+#define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
+#define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
+  * @{
+  */
+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
+  * @{
+  */
+#define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
+  * @{
+  */
+#define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
+#define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
+#define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
+#define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
+#define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
+#define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
+#define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
+#define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
+#define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
+  * @{
+  */
+#define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
+  * @{
+  */
+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
+  * @{
+  */
+#define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
+#define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
+#define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_operation FDCAN TT Operation
+  * @{
+  */
+#define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
+  * @{
+  */
+#define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
+  * @{
+  */
+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
+  * @{
+  */
+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
+  * @{
+  */
+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
+  * @{
+  */
+#define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
+  * @{
+  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
+#define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
+  * @{
+  */
+#define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
+#define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
+  * @{
+  */
+#define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
+  * @{
+  */
+#define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
+#define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
+#define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
+  * @{
+  */
+#define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
+#define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
+#define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
+  * @{
+  */
+#define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
+#define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
+#define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
+/**
+  * @}
+  */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+  * @{
+  */
+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
+#define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+  * @{
+  */
+#define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
+#define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
+#define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
+#define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
+#define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
+#define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
+#define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
+#define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
+#define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
+#define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
+#define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
+#define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
+#define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+  * @{
+  */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
+#define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
+  * @{
+  */
+#define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
+#define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
+#define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
+#define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
+#define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
+#define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+  * @{
+  */
+#define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+  * @{
+  */
+#define FDCAN_IT_ERROR_PASSIVE           FDCAN_IE_EPE   /*!< Error_Passive status changed      */
+#define FDCAN_IT_ERROR_WARNING           FDCAN_IE_EWE   /*!< Error_Warning status changed      */
+#define FDCAN_IT_BUS_OFF                 FDCAN_IE_BOE   /*!< Bus_Off status changed            */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTflags FDCAN TT Flags
+  * @{
+  */
+#define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
+#define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
+#define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
+#define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
+#define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
+#define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
+#define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
+#define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
+  * @{
+  */
+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
+#define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
+#define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset FDCAN handle state.
+  * @param  __HANDLE__ FDCAN handle.
+  * @retval None
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
+                                                       (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
+                                                       (__HANDLE__)->MspInitCallback = NULL;           \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                     } while(0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
+  do{                                                                \
+    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
+  }while(0)
+
+
+/**
+  * @brief  Disable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
+  do{                                                                   \
+    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be one of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
+                                                       ((__HANDLE__)->Instance->IR &\
+                                                        (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Clear the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)                  \
+  do {                                                                   \
+    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  } while(0);
+
+/**
+  * @brief  Check whether the specified FDCAN flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN flag.
+  *         This parameter can be one of @arg FDCAN_flags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? \
+                                                    ((__HANDLE__)->Instance->IR &\
+                                                     (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FDCAN flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_flags
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)                \
+  do {                                                              \
+    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
+  } while(0);
+
+/** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
+                                                              ((__HANDLE__)->Instance->IE &\
+                                                               (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & \
+                                                                   (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be one of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
+
+/**
+  * @brief  Clear the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the TT interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN TT flag.
+  *         This parameter can be one of @arg FDCAN_TTflags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
+
+/**
+  * @brief  Clear the specified FDCAN TT flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the TT flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTflags
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
+
+/** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+                                             pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                          pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                           pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                       pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                         pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
+                                                   const FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t          HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+                                                 uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+                                                      uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+  * @{
+  */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                const uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                 const uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+                                         FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                         FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                              FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
+                                             FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+  * @{
+  */
+/* TT Configuration and control functions**************************************/
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier,
+                                                      uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource,
+                                                      uint32_t TimeMarkValue, uint32_t RepeatFactor,
+                                                      uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                  FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+  * @{
+  */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList,
+                                                    uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+                                                 uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
+void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+  * @{
+  */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group7
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Types FDCAN Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+  * @{
+  */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
+                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
+                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
+                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
+
+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
+                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
+
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
+#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_64))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
+                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+                                ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
+                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
+                                   ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_12) || \
+                           ((DLC) == FDCAN_DLC_BYTES_16) || \
+                           ((DLC) == FDCAN_DLC_BYTES_20) || \
+                           ((DLC) == FDCAN_DLC_BYTES_24) || \
+                           ((DLC) == FDCAN_DLC_BYTES_32) || \
+                           ((DLC) == FDCAN_DLC_BYTES_48) || \
+                           ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+                           ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+                           ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+                           ((FDF) == FDCAN_FD_CAN     ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
+                           ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+                                            ((DESTINATION) == FDCAN_REJECT            ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
+                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
+                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
+                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
+                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
+                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
+                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
+                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
+                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))
+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
+                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
+                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
+                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
+                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
+                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
+                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
+                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+
+#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__)  ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FDCAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_FDCAN_H */
+
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gfxmmu.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gfxmmu.h
new file mode 100644
index 000000000..bebacda63
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gfxmmu.h
@@ -0,0 +1,370 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gfxmmu.h
+  * @author  MCD Application Team
+  * @brief   Header file of GFXMMU HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_GFXMMU_H
+#define STM32N6xx_HAL_GFXMMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined(GFXMMU)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GFXMMU
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL GFXMMU states definition
+  */
+typedef enum
+{
+  HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized. */
+  HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use. */
+} HAL_GFXMMU_StateTypeDef;
+
+/**
+  * @brief  GFXMMU buffers structure definition
+  */
+typedef struct
+{
+  uint32_t Buf0Address; /*!< Physical address of buffer 0. */
+  uint32_t Buf1Address; /*!< Physical address of buffer 1. */
+  uint32_t Buf2Address; /*!< Physical address of buffer 2. */
+  uint32_t Buf3Address; /*!< Physical address of buffer 3. */
+} GFXMMU_BuffersTypeDef;
+
+/**
+  * @brief  GFXMMU interrupts structure definition
+  */
+typedef struct
+{
+  FunctionalState Activation;     /*!< Interrupts enable/disable. */
+  uint32_t        UsedInterrupts; /*!< Interrupts used.
+                                       This parameter can be a values combination of @ref GFXMMU_Interrupts.
+                                       @note: Useful only when interrupts are enabled. */
+} GFXMMU_InterruptsTypeDef;
+
+/**
+  * @brief  GFXMMU init structure definition
+  */
+typedef struct
+{
+  uint32_t                    BlockSize;          /*!< Size of virtual memory block.
+                                                       This parameter can be a value of @ref GFXMMU_BlockSize. */
+  uint32_t                    DefaultValue;       /*!< Value returned when virtual memory location not physically mapped. */
+                                                  /*   @note: Useful only when address translation is enabled. */
+  FunctionalState             AddressTranslation; /*!< Address translation enable/disable. */
+  GFXMMU_BuffersTypeDef       Buffers;            /*!< Physical buffers addresses. */
+  GFXMMU_InterruptsTypeDef    Interrupts;         /*!< Interrupts parameters. */
+} GFXMMU_InitTypeDef;
+
+/**
+  * @brief  GFXMMU handle structure definition
+  */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+typedef struct __GFXMMU_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
+{
+  GFXMMU_TypeDef          *Instance; /*!< GFXMMU instance. */
+  GFXMMU_InitTypeDef      Init;      /*!< GFXMMU init parameters. */
+  HAL_GFXMMU_StateTypeDef State;     /*!< GFXMMU state. */
+  __IO uint32_t           ErrorCode; /*!< GFXMMU error code. */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+  void (*ErrorCallback)     (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback. */
+  void (*MspInitCallback)   (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback. */
+  void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback. */
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
+} GFXMMU_HandleTypeDef;
+
+/**
+  * @brief  GFXMMU LUT line structure definition
+  */
+typedef struct
+{
+  uint32_t LineNumber;        /*!< LUT line number.
+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */
+  uint32_t LineStatus;        /*!< LUT line enable/disable.
+                                   This parameter can be a value of @ref GFXMMU_LutLineStatus. */
+  uint32_t FirstVisibleBlock; /*!< First visible block on this line.
+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
+  uint32_t LastVisibleBlock;  /*!< Last visible block on this line.
+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
+  int32_t  LineOffset;        /*!< Offset of block 0 of the current line in physical buffer.
+                                   This parameter must be a number between Min_Data = -255 and Max_Data = 261888.
+                                   @note: Line offset has to be computed with the following formula:
+                                          LineOffset = [(Blocks already used) - (1st visible block)]. */
+} GFXMMU_LutLineTypeDef;
+
+/**
+  * @brief  GFXMMU packing structure definition
+  */
+typedef struct
+{
+  FunctionalState Buffer0Activation; /*!< Packing on buffer 0 enable/disable. */
+  uint32_t        Buffer0Mode;       /*!< Buffer 0 packing mode.
+                                          This parameter can be a value of @ref GFXMMU_PackingModes. */
+  FunctionalState Buffer1Activation; /*!< Packing on buffer 1 enable/disable. */
+  uint32_t        Buffer1Mode;       /*!< Buffer 1 packing mode.
+                                          This parameter can be a value of @ref GFXMMU_PackingModes. */
+  FunctionalState Buffer2Activation; /*!< Packing on buffer 2 enable/disable. */
+  uint32_t        Buffer2Mode;       /*!< Buffer 2 packing mode.
+                                          This parameter can be a value of @ref GFXMMU_PackingModes. */
+  FunctionalState Buffer3Activation; /*!< Packing on buffer 3 enable/disable. */
+  uint32_t        Buffer3Mode;       /*!< Buffer 3 packing mode.
+                                          This parameter can be a value of @ref GFXMMU_PackingModes. */
+  uint32_t        DefaultAlpha;      /*!< Default alpha value.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
+} GFXMMU_PackingTypeDef;
+
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  GFXMMU callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_GFXMMU_ERROR_CB_ID     = 0x00U, /*!< GFXMMU error callback ID. */
+  HAL_GFXMMU_MSPINIT_CB_ID   = 0x01U, /*!< GFXMMU MSP init callback ID. */
+  HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U  /*!< GFXMMU MSP de-init callback ID. */
+} HAL_GFXMMU_CallbackIDTypeDef;
+
+/**
+  * @brief  GFXMMU callback pointer definition
+  */
+typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants
+  * @{
+  */
+
+/** @defgroup GFXMMU_BlockSize GFXMMU block size
+  * @{
+  */
+#define GFXMMU_12BYTE_BLOCKS GFXMMU_CR_BS  /*!< Blocks of 12-byte. */
+#define GFXMMU_16BYTE_BLOCKS 0x00000000U   /*!< Blocks of 16-byte. */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Interrupts GFXMMU interrupts
+  * @{
+  */
+#define GFXMMU_BUS_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< Bus master error interrupt. */
+#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt. */
+#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt. */
+#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt. */
+#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt. */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Error_Code GFXMMU Error Code
+  * @{
+  */
+#define GFXMMU_ERROR_NONE             0x00000000U    /*!< No error. */
+#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow. */
+#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow. */
+#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow. */
+#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow. */
+#define GFXMMU_ERROR_BUS_MASTER       GFXMMU_SR_AMEF /*!< Bus master error. */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U    /*!< Invalid callback error. */
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status
+  * @{
+  */
+#define GFXMMU_LUT_LINE_DISABLE 0x00000000U     /*!< LUT line disabled. */
+#define GFXMMU_LUT_LINE_ENABLE  GFXMMU_LUTxL_EN /*!< LUT line enabled. */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_PackingModes GFXMMU packing modes
+  * @{
+  */
+#define GFXMMU_PACKING_MSB_REMOVE 0x00000000U /*!< Remove MSB during packing operation. */
+#define GFXMMU_PACKING_LSB_REMOVE 0x00000001U /*!< Remove LSB during packing operation. */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros
+  * @{
+  */
+
+/** @brief  Reset GFXMMU handle state.
+  * @param  __HANDLE__ GFXMMU handle.
+  * @retval None
+  */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{                                               \
+                                                        (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
+                                                        (__HANDLE__)->MspInitCallback = NULL;         \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;       \
+                                                      } while(0)
+#else
+#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions
+  * @{
+  */
+
+/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
+HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
+void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
+void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+/* GFXMMU callbacks register/unregister functions *****************************/
+HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
+                                              HAL_GFXMMU_CallbackIDTypeDef CallbackID,
+                                              pGFXMMU_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
+                                                HAL_GFXMMU_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions
+  * @{
+  */
+/* Operation functions ********************************************************/
+HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu,
+                                       uint32_t FirstLine,
+                                       uint32_t LinesNumber,
+                                       uint32_t Address);
+
+HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu,
+                                             uint32_t FirstLine,
+                                             uint32_t LinesNumber);
+
+HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine);
+
+HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers);
+
+HAL_StatusTypeDef HAL_GFXMMU_ConfigPacking(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_PackingTypeDef *pPacking);
+
+void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);
+
+void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
+  * @{
+  */
+/* State function *************************************************************/
+HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu);
+
+uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros
+  * @{
+  */
+#define IS_GFXMMU_BLOCK_SIZE(VALUE) (((VALUE) == GFXMMU_12BYTE_BLOCKS) || \
+                                     ((VALUE) == GFXMMU_16BYTE_BLOCKS))
+#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -255) && ((VALUE) <= 261888))
+
+#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
+
+#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
+
+#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
+
+#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
+
+#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
+                                          ((VALUE) == GFXMMU_LUT_LINE_ENABLE))
+
+#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
+
+#define IS_GFXMMU_PACKING_MODE(VALUE) (((VALUE) == GFXMMU_PACKING_MSB_REMOVE) || \
+                                       ((VALUE) == GFXMMU_PACKING_LSB_REMOVE))
+
+#define IS_GFXMMU_DEFAULT_ALPHA_VALUE(VALUE) ((VALUE) < 256U)
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* GFXMMU */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_GFXMMU_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gfxtim.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gfxtim.h
new file mode 100644
index 000000000..f5a39fad1
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gfxtim.h
@@ -0,0 +1,929 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gfxtim.h
+  * @author  MCD Application Team
+  * @brief   Header file of GFXTIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_GFXTIM_H
+#define STM32N6xx_HAL_GFXTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (GFXTIM)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GFXTIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GFXTIM_Exported_Types  GFXTIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL GFXTIM states definition
+  */
+typedef enum
+{
+  HAL_GFXTIM_STATE_RESET       = 0x00U,      /*!< GFXTIM not initialized */
+  HAL_GFXTIM_STATE_READY       = 0x01U,      /*!< GFXTIM initialized and ready for use */
+  HAL_GFXTIM_STATE_ERROR       = 0xFFU       /*!< GFXTIM state error */
+} HAL_GFXTIM_StateTypeDef;
+
+/**
+  * @brief  GFXTIM initialization structure definition
+  */
+typedef struct
+{
+  uint32_t SynchroSrc;               /*!< Synchronization signals (HSYNC and VSYNC) sources.
+                                     This parameter can be a value of @ref GFXTIM_SynchroSrc */
+  uint32_t TearingEffectSrc;         /*!< Tearing effect source
+                                     This parameter can be a value of @ref GFXTIM_TearingEffectSrc */
+  uint32_t TearingEffectPolarity;    /*!< Tearing effect source
+                                     This parameter can be a value of @ref GFXTIM_TearingEffectPolarity */
+  uint32_t TearingEffectInterrupt;   /*!< Tearing effect interrupt Enable or Disable
+                                     This parameter can be a value of @ref GFXTIM_Interrupt */
+} GFXTIM_InitTypeDef;
+
+/**
+  * @brief  GFXTIM handle structure definition
+  */
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+typedef struct __GFXTIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+{
+  GFXTIM_TypeDef                    *Instance;             /*!< GFXTIM instance */
+  __IO HAL_GFXTIM_StateTypeDef      State;                 /*!< GFXTIM state */
+  __IO uint32_t                     ErrorCode;             /*!< GFXTIM error code */
+  GFXTIM_InitTypeDef                Init;                  /*!< GFXTIM initialization */
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+  void (*HAL_GFXTIM_AbsoluteTimer_AFCC1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Absolute frame counter compare 1 callback */
+  void (*HAL_GFXTIM_AbsoluteTimer_AFCOFCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Absolute frame counter overflow callback */
+  void (*HAL_GFXTIM_AbsoluteTimer_ALCC1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Absolute line counter compare 1 callback */
+  void (*HAL_GFXTIM_AbsoluteTimer_ALCC2Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Absolute line counter compare 2 callback */
+  void (*HAL_GFXTIM_AbsoluteTimer_ALCOFCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Absolute line counter overflow callback */
+  void (*HAL_GFXTIM_RelativeTimer_RFC1RCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Relative frame counter 1 reload callback */
+  void (*HAL_GFXTIM_RelativeTimer_RFC2RCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Relative frame counter 2 reload callback */
+  void (*HAL_GFXTIM_TECallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);                     /*!< GFXTIM Tearing effect callback */
+  void (*HAL_GFXTIM_EventGenerator_EV1Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim);     /*!< GFXTIM Event events 1 callback */
+  void (*HAL_GFXTIM_EventGenerator_EV2Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim);     /*!< GFXTIM Event events 2 callback */
+  void (*HAL_GFXTIM_EventGenerator_EV3Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim);     /*!< GFXTIM Event events 3 callback */
+  void (*HAL_GFXTIM_EventGenerator_EV4Callback)(struct __GFXTIM_HandleTypeDef *hgfxtim);     /*!< GFXTIM Event events 4 callback */
+  void (*HAL_GFXTIM_WatchdogTimer_AlarmCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);    /*!< GFXTIM Watchdog alarm callback */
+  void (*HAL_GFXTIM_WatchdogTimer_PreAlarmCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim); /*!< GFXTIM Watchdog pre alarm callback */
+  void (*ErrorCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);                             /*!< GFXTIM error callback */
+  void (*MspInitCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);                           /*!< GFXTIM MSP initialization user callback */
+  void (*MspDeInitCallback)(struct __GFXTIM_HandleTypeDef *hgfxtim);                         /*!< GFXTIM MSP de-initialization user callback */
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+} GFXTIM_HandleTypeDef;
+
+
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  GFXTIM callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_GFXTIM_AFC_COMPARE1_CB_ID   =  1U,    /*!< GFXTIM Absolute frame counter compare 1 callback ID */
+  HAL_GFXTIM_AFC_OVERFLOW_CB_ID   =  2U,    /*!< GFXTIM Absolute frame counter overflow callback ID */
+  HAL_GFXTIM_ALC_COMPARE1_CB_ID   =  3U,    /*!< GFXTIM Absolute line counter compare 1 callback ID */
+  HAL_GFXTIM_ALC_COMPARE2_CB_ID   =  4U,    /*!< GFXTIM Absolute line counter compare 2 callback ID */
+  HAL_GFXTIM_ALC_OVERFLOW_CB_ID   =  5U,    /*!< GFXTIM Absolute line counter overflow callback ID */
+  HAL_GFXTIM_RFC1_RELOAD_CB_ID    =  6U,    /*!< GFXTIM Relative frame counter 1 reload callback ID */
+  HAL_GFXTIM_RFC2_RELOAD_CB_ID    =  7U,    /*!< GFXTIM Relative frame counter 2 reload callback ID */
+  HAL_GFXTIM_TE_CB_ID             =  8U,    /*!< GFXTIM External tearing effect callback ID */
+  HAL_GFXTIM_EVENT1_CB_ID         =  9U,    /*!< GFXTIM Event events 1 callback ID */
+  HAL_GFXTIM_EVENT2_CB_ID         = 10U,    /*!< GFXTIM Event events 2 callback ID */
+  HAL_GFXTIM_EVENT3_CB_ID         = 11U,    /*!< GFXTIM Event events 3 callback ID */
+  HAL_GFXTIM_EVENT4_CB_ID         = 12U,    /*!< GFXTIM Event events 4 callback ID */
+  HAL_GFXTIM_WDG_ALARM_CB_ID      = 13U,    /*!< GFXTIM Watchdog alarm callback ID */
+  HAL_GFXTIM_WDG_PREALARM_CB_ID   = 14U,    /*!< GFXTIM Watchdog pre alarm callback ID */
+  HAL_GFXTIM_ERROR_CB_ID          = 15U,    /*!< GFXTIM error callback ID */
+  HAL_GFXTIM_MSP_INIT_CB_ID       = 16U,    /*!< GFXTIM MSP initialization user callback ID */
+  HAL_GFXTIM_MSP_DEINIT_CB_ID     = 17U,    /*!< GFXTIM MSP de-initialization user callback ID */
+} HAL_GFXTIM_CallbackIDTypeDef;
+
+/**
+  * @brief  GFXTIM callback pointers definition
+  */
+typedef void (*pGFXTIM_CallbackTypeDef)(GFXTIM_HandleTypeDef *hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+
+
+
+
+/**
+  * @brief  GFXTIM clock generator structure definition
+  */
+typedef struct
+{
+  uint32_t LCCHwReloadSrc;      /*!< Line Clock Counter hardware reload source
+                                This parameter can be a value of @ref GFXTIM_LCCHwReloadSrc */
+
+  uint32_t LCCReloadValue;      /*!< Line Clock Counter reload value (22 bits)
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 4194303 */
+
+  uint32_t LCCClockSrc;         /*!< Line Clock Counter Clock Source
+                                This parameter can be a value of @ref GFXTIM_LCCClockSrc */
+
+  uint32_t LineClockSrc;        /*!< Line Clock Source
+                                This parameter can be a value of @ref GFXTIM_LineClockSrc */
+
+  uint32_t FCCHwReloadSrc;      /*!< Frame Clock Counter hardware reload source
+                                This parameter can be a value of @ref GFXTIM_FCCHwReloadSrc */
+
+  uint32_t FCCReloadValue;      /*!< Frame Clock Counter reload value (12 bits)
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 4095 */
+
+  uint32_t FCCClockSrc;         /*!< Frame Clock Counter Clock Source
+                                This parameter can be a value of @ref GFXTIM_FCCClockSrc */
+
+  uint32_t FrameClockSrc;       /*!< Frame Clock Source
+                                This parameter can be a value of @ref GFXTIM_FrameClockSrc */
+
+  uint32_t LineClockCalib;      /*!< Debug purpose
+                                This parameter can be a value of @ref GFXTIM_LineClockCalib */
+
+  uint32_t FrameClockCalib;     /*!< Debug purpose
+                                This parameter can be a value of @ref GFXTIM_FrameClockCalib */
+} GFXTIM_ClockGeneratorConfigTypeDef;
+
+/**
+  * @brief  GFXTIM absolute timer configuration structure
+  */
+typedef struct
+{
+  uint32_t FrameCompare1Value;      /*!< Absolute Frame Compare 1 value (20 bits)
+                                    This parameter must be a number between 1 and 1048575 */
+
+  uint32_t FrameCounterValue;       /*!< Absolute Frame Counter initial value (20 bits)
+                                    This parameter must be a number between 1 and 1048575 */
+
+  uint32_t FrameOverflowInterrupt;  /*!< Absolute Frame Counter Overflow Interrupt Enable or Disable
+                                    This parameter can be a value of @ref GFXTIM_Interrupt */
+
+  uint32_t FrameCompare1Interrupt;  /*!< Absolute Frame Compare 1 Interrupt Enable or Disable
+                                    This parameter can be a value of @ref GFXTIM_Interrupt */
+
+  uint32_t LineCompare1Value;       /*!< Absolute Line Compare 1 value (12 bits)
+                                    This parameter must be a number between 1 and 4095 */
+
+  uint32_t LineCompare2Value;       /*!< Absolute Line Compare 2 value (12 bits)
+                                    This parameter must be a number between 1 and 4095 */
+
+  uint32_t LineCounterValue;        /*!< Absolute Line Counter value (12 bits)
+                                    This parameter must be a number between 1 and 4095 */
+
+  uint32_t LineOverflowInterrupt;   /*!< Absolute Line Counter Overflow Interrupt Enable or Disable
+                                    This parameter can be a value of @ref GFXTIM_Interrupt */
+
+  uint32_t LineCompare1Interrupt;   /*!< Absolute Line Compare 1 Interrupt Enable or Disable
+                                    This parameter can be a value of @ref GFXTIM_Interrupt */
+
+  uint32_t LineCompare2Interrupt;   /*!< Absolute Line Compare 2 Interrupt Enable or Disable
+                                    This parameter can be a value of @ref GFXTIM_Interrupt */
+} GFXTIM_AbsoluteTimerConfigTypeDef;
+
+
+/**
+  * @brief  GFXTIM relative timer configuration structure
+  */
+typedef struct
+{
+  uint32_t AutoReloadValue;      /*!< Auto reload value (12 bits)
+                                 This parameter must be a number between 1 and 4095 */
+
+  uint32_t CounterMode;          /*!< Counter Mode
+                                 This parameter can be a value of GFXTIM_RelativeCounterMode */
+  uint32_t ReloadInterrupt;      /*!< Relative Frame Counter Reload Interrupt Enable or Disable
+                                 This parameter can be a value of @ref GFXTIM_Interrupt */
+} GFXTIM_RelativeTimerConfigTypeDef;
+
+
+/**
+  * @brief  GFXTIM event generator configuration structure
+  */
+typedef struct
+{
+  uint32_t LineEvent;          /*!< Line event selection
+                               This parameter can be a value of GFXTIM_EventLine */
+
+  uint32_t FrameEvent;         /*!< Frmae event selection
+                               This parameter can be a value of GFXTIM_EventFrame */
+
+  uint32_t EventInterrupt;     /*!< Event interrupt Enable or Disable
+                               This parameter can be a value of @ref GFXTIM_Interrupt */
+} GFXTIM_EventGeneratorConfigTypeDef;
+
+/**
+  * @brief  GFXTIM watchdog configuration structure
+  */
+typedef struct
+{
+  uint32_t ClockSrc;          /*!< Clock source
+                              This parameter can be a value of GFXTIM_WatchdogClockSrc */
+
+  uint32_t AutoReloadValue;   /*!< Reload value (16 bits)
+                              This parameter must be a number between 1 and 65535 */
+
+  uint32_t HwReloadConfig;    /*!< Hardware reload configuration
+                              This parameter can be a value of GFXTIM_WatchdogHwReloadConfig */
+
+  uint32_t PreAlarmValue;     /*!< Pre-alarm value (16 bits)
+                              This parameter must be a number between 1 and 65535 */
+
+  uint32_t AlarmInterrupt;    /*!< Interrupt Enable or Disable when watchdog counter reaches 0
+                              This parameter can be a value of @ref GFXTIM_Interrupt */
+
+  uint32_t PreAlarmInterrupt; /*!< Interrupt Enable or Disable when watchdog counter reaches pre-alarm value
+                               This parameter can be a value of @ref GFXTIM_Interrupt */
+} GFXTIM_WatchdogConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GFXTIM_Exported_Constants GFXTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup GFXTIM_ErrorCode GFXTIM Error Code
+  * @{
+  */
+#define GFXTIM_ERROR_NONE                      0U /*!< No error */
+#define GFXTIM_ERROR_STATE                     1U /*!< State error */
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+#define GFXTIM_ERROR_INVALID_CALLBACK          2U /*!< Invalid callback error occurs */
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Interrupt GFXTIM Interrupt
+  * @{
+  */
+#define GFXTIM_IT_DISABLE                   0U    /*!< gfxtim_interrupt disable */
+#define GFXTIM_IT_ENABLE                    1U    /*!< gfxtim_interrupt enable */
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_SynchroSrc GFXTIM Synchronization Source
+  * @{
+  */
+#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_0    0U                                       /*!< gfxtim_hsync[0] and gfxtim_vsync[0] are used as synchronization source */
+#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_1    GFXTIM_CR_SYNCS_0                        /*!< gfxtim_hsync[1] and gfxtim_vsync[1] are used as synchronization source */
+#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_2    GFXTIM_CR_SYNCS_1                        /*!< gfxtim_hsync[2] and gfxtim_vsync[2] are used as synchronization source */
+#define GFXTIM_SYNC_SRC_HSYNC_VSYNC_3    (GFXTIM_CR_SYNCS_0 | GFXTIM_CR_SYNCS_1)  /*!< gfxtim_hsync[3] and gfxtim_vsync[3] are used as synchronization source */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_TearingEffectSrc GFXTIM Tearing Effect Source
+  * @{
+  */
+#define GFXTIM_TE_SRC_GPIO         0U                                                    /*!< Input pad rising */
+#define GFXTIM_TE_SRC_ITE          GFXTIM_CR_TES_0                                       /*!< gfxtim_ite rising */
+#define GFXTIM_TE_SRC_HSYNC        GFXTIM_CR_TES_1                                       /*!< HSYNC (see SynchroSrc) rising */
+#define GFXTIM_TE_SRC_VSYNC        (GFXTIM_CR_TES_0 | GFXTIM_CR_TES_1)                   /*!< VSYNC (see SynchroSrc) rising  */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_TearingEffectPolarity GFXTIM Tearing Effect Polarity
+  * @{
+  */
+#define GFXTIM_TE_RISING_EDGE           0U                  /*!< Tearing Effect active on rizing edge */
+#define GFXTIM_TE_FALLING_EDGE          GFXTIM_CR_TEPOL     /*!< Tearing Effect active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_LCCHwReloadSrc GFXTIM Line Clock Counter Hardware Reload Source
+  * @{
+  */
+#define GFXTIM_LCC_HW_RELOAD_SRC_NONE           0U                                                                    /*!< No hardware reload */
+#define GFXTIM_LCC_HW_RELOAD_SRC_FCC_UNDERFLOW  GFXTIM_CGCR_LCCHRS_0                                                  /*!< FCC underflow */
+#define GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_RISING   GFXTIM_CGCR_LCCHRS_1                                                  /*!< HSYNC rising */
+#define GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_FALLING  (GFXTIM_CGCR_LCCHRS_0 | GFXTIM_CGCR_LCCHRS_1)                         /*!< HSYNC falling */
+#define GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_RISING   GFXTIM_CGCR_LCCHRS_2                                                  /*!< VSYNC rising */
+#define GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_FALLING  (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_0)                         /*!< VSYNC falling */
+#define GFXTIM_LCC_HW_RELOAD_SRC_TE_RISING      (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_1)                         /*!< TE rising */
+#define GFXTIM_LCC_HW_RELOAD_SRC_TE_FALLING     (GFXTIM_CGCR_LCCHRS_2 | GFXTIM_CGCR_LCCHRS_1 | GFXTIM_CGCR_LCCHRS_0)  /*!< TE falling */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_LCCClockSrc GFXTIM Line Clock Counter Clock Source
+  * @{
+  */
+#define GFXTIM_LCC_CLK_SRC_DISABLE    0U                 /*!< Disable line clock counter */
+#define GFXTIM_LCC_CLK_SRC_SYSCLOCK   GFXTIM_CGCR_LCCCS  /*!< System clock as line clock counter source*/
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_LineClockSrc GFXTIM Line Clock Source
+  * @{
+  */
+#define GFXTIM_LINE_CLK_SRC_LCC_UNDERFLOW   0U                                                          /*!< Line Clock Counter underflow */
+#define GFXTIM_LINE_CLK_SRC_FCC_UNDERFLOW   GFXTIM_CGCR_LCS_0                                           /*!< Frame Clock Counter underflow */
+#define GFXTIM_LINE_CLK_SRC_HSYNC_RISING    GFXTIM_CGCR_LCS_1                                           /*!< HSYNC rising edge */
+#define GFXTIM_LINE_CLK_SRC_HSYNC_FALLING   (GFXTIM_CGCR_LCS_0 | GFXTIM_CGCR_LCS_1)                     /*!< HSYNC falling edge*/
+#define GFXTIM_LINE_CLK_SRC_VSYNC_RISING    GFXTIM_CGCR_LCS_2                                           /*!< VSYNC rising edge*/
+#define GFXTIM_LINE_CLK_SRC_VSYNC_FALLING   (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_0)                     /*!< VSYNC falling edge*/
+#define GFXTIM_LINE_CLK_SRC_TE_RISING       (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_1)                     /*!< TE rising edge*/
+#define GFXTIM_LINE_CLK_SRC_TE_FALLING      (GFXTIM_CGCR_LCS_2 | GFXTIM_CGCR_LCS_1 | GFXTIM_CGCR_LCS_0) /*!< TE falling edge*/
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_FCCHwReloadSrc GFXTIM Frame Clock Counter Hardware Reload source
+  * @{
+  */
+#define GFXTIM_FCC_HW_RELOAD_SRC_NONE           0U                                                                   /*!< No hardware reload */
+#define GFXTIM_FCC_HW_RELOAD_SRC_LCC_UNDERFLOW  GFXTIM_CGCR_FCCHRS_0                                                 /*!< Line Clock Counter underflow */
+#define GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_RISING   GFXTIM_CGCR_FCCHRS_1                                                 /*!< HSYNC rising edge */
+#define GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_FALLING  (GFXTIM_CGCR_FCCHRS_0 | GFXTIM_CGCR_FCCHRS_1)                        /*!< HSYNC falling edge */
+#define GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_RISING   GFXTIM_CGCR_FCCHRS_2                                                 /*!< VSYNC rising edge */
+#define GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_FALLING  (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_0)                        /*!< VSYNC falling edge */
+#define GFXTIM_FCC_HW_RELOAD_SRC_TE_RISING      (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_1)                        /*!< TE rising edge */
+#define GFXTIM_FCC_HW_RELOAD_SRC_TE_FALLING     (GFXTIM_CGCR_FCCHRS_2 | GFXTIM_CGCR_FCCHRS_1 | GFXTIM_CGCR_FCCHRS_0) /*!< TE falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_FCCClockSrc GFXTIM Frame CLock Counter Clock Source
+  * @{
+  */
+#define GFXTIM_FCC_CLK_SRC_DISABLE         0U                                                                /*!< Disable */
+#define GFXTIM_FCC_CLK_SRC_LCC_UNDERFLOW   GFXTIM_CGCR_FCCCS_0                                               /*!< Line Clock Counter underflow */
+#define GFXTIM_FCC_CLK_SRC_HSYNC_RISING    GFXTIM_CGCR_FCCCS_1                                               /*!< HSYNC rising edge */
+#define GFXTIM_FCC_CLK_SRC_HSYNC_FALLING   (GFXTIM_CGCR_FCCCS_0 | GFXTIM_CGCR_FCCCS_1)                       /*!< HSYNC falling edge */
+#define GFXTIM_FCC_CLK_SRC_VSYNC_RISING    GFXTIM_CGCR_FCCCS_2                                               /*!< VSYNC rising edge */
+#define GFXTIM_FCC_CLK_SRC_VSYNC_FALLING   (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_0)                       /*!< VSYNC falling edge */
+#define GFXTIM_FCC_CLK_SRC_TE_RISING       (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_1)                       /*!< TE rising edge */
+#define GFXTIM_FCC_CLK_SRC_TE_FALLING      (GFXTIM_CGCR_FCCCS_2 | GFXTIM_CGCR_FCCCS_1 | GFXTIM_CGCR_FCCCS_0) /*!< TE falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_FrameClockSrc GFXTIM GFXTIM  Frame Clock Source
+  * @{
+  */
+#define GFXTIM_FRAME_CLK_SRC_LCC_UNDERFLOW   0U                                                          /*!< Line Clock Counter underflow */
+#define GFXTIM_FRAME_CLK_SRC_FCC_UNDERFLOW   GFXTIM_CGCR_FCS_0                                           /*!< Frame Clock Counter underflow */
+#define GFXTIM_FRAME_CLK_SRC_HSYNC_RISING    GFXTIM_CGCR_FCS_1                                           /*!< HSYNC rising edge */
+#define GFXTIM_FRAME_CLK_SRC_HSYNC_FALLING   (GFXTIM_CGCR_FCS_0 | GFXTIM_CGCR_FCS_1)                     /*!< HSYNC falling edge */
+#define GFXTIM_FRAME_CLK_SRC_VSYNC_RISING    GFXTIM_CGCR_FCS_2                                           /*!< VSYNC rising edge */
+#define GFXTIM_FRAME_CLK_SRC_VSYNC_FALLING   (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_0)                     /*!< VSYNC falling edge */
+#define GFXTIM_FRAME_CLK_SRC_TE_RISING       (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_1)                     /*!< TE rising edge */
+#define GFXTIM_FRAME_CLK_SRC_TE_FALLING      (GFXTIM_CGCR_FCS_2 | GFXTIM_CGCR_FCS_1 | GFXTIM_CGCR_FCS_0) /*!< TE falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_LineClockCalib GFXTIM Line Clock Calibration Output
+  * @{
+  */
+#define GFXTIM_LINE_CLK_CALIB_DISABLE   0U               /*!< Disable Line clock calibration */
+#define GFXTIM_LINE_CLK_CALIB_ENABLE    GFXTIM_CR_LCCOE  /*!< Enable Line clock calibration */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_FrameClockCalib GFXTIM Frame Clock Calibration Output (for debug purpose)
+  * @{
+  */
+#define GFXTIM_FRAME_CLK_CALIB_DISABLE   0U               /*!< Frame clock output calibration Disable */
+#define GFXTIM_FRAME_CLK_CALIB_ENABLE    GFXTIM_CR_FCCOE  /*!< Frame clock output calibration Enable */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_ClockGeneratorCounter GFXTIM  Clock Generator Counter
+  * @{
+  */
+#define GFXTIM_LINE_CLK_COUNTER     GFXTIM_CGCR_LCCFR      /*!< Line clock counter */
+#define GFXTIM_FRAME_CLK_COUNTER    GFXTIM_CGCR_FCCFR      /*!< Frame clock counter */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_AbsoluteTime GFXTIM Absolute Time
+  * @{
+  */
+#define GFXTIM_ABSOLUTE_GLOBAL_TIME   0x00000014U  /*!< Absolute global time (frame and line) counters ATR*/
+#define GFXTIM_ABSOLUTE_FRAME_TIME    0x00000015U  /*!< Absolute frame counter AFCR */
+#define GFXTIM_ABSOLUTE_LINE_TIME     0x00000016U  /*!< Absolute line counter ALCR */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_AbsoluteLineComparator GFXTIM Absolute Line Comparator
+  * @{
+  */
+#define GFXTIM_ABSOLUTE_LINE_COMPARE1   0x1CU  /*!< Absolute line compare 1 */
+#define GFXTIM_ABSOLUTE_LINE_COMPARE2   0x1DU  /*!< Absolute line compare 2 */
+/**
+  * @}
+  */
+
+
+/** @defgroup GFXTIM_RelativeCounterMode GFXTIM Relative Frame Counter Mode
+  * @{
+  */
+#define GFXTIM_MODE_ONE_SHOT          0U  /*!< Relative Frame Counter One Shot Mode*/
+#define GFXTIM_MODE_CONTINUOUS        1U  /*!< Relative Frame Counter Continuous Mode */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_RelativeTimer GFXTIM Relative Timer
+  * @{
+  */
+#define GFXTIM_RELATIVE_TIMER1          0U  /*!< Relative Timer 1*/
+#define GFXTIM_RELATIVE_TIMER2          1U  /*!< Relative Timer 2 */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_EventLineSrc GFXTIM Event generator Line source selection
+  * @{
+  */
+#define GFXTIM_LINE_EVENT_NONE            (0U << GFXTIM_EVSR_LES1_Pos)  /*!< None */
+#define GFXTIM_LINE_EVENT_ALC_OVERFLOW    (1U << GFXTIM_EVSR_LES1_Pos)  /*!< Absolute line counter overflow */
+#define GFXTIM_LINE_EVENT_TE              (2U << GFXTIM_EVSR_LES1_Pos)  /*!< Tearing effect */
+#define GFXTIM_LINE_EVENT_ALC1_COMPARE    (4U << GFXTIM_EVSR_LES1_Pos)  /*!< Absolute line counter 1 compare */
+#define GFXTIM_LINE_EVENT_ALC2_COMPARE    (5U << GFXTIM_EVSR_LES1_Pos)  /*!< Absolute line counter 2 compare */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_EventFrameSrc GFXTIM Event generator Frame Source selection
+  * @{
+  */
+#define GFXTIM_FRAME_EVENT_NONE            (0U << GFXTIM_EVSR_FES1_Pos ) /*!< None */
+#define GFXTIM_FRAME_EVENT_AFC_OVERFLOW    (1U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counter overflow */
+#define GFXTIM_FRAME_EVENT_AFC_COMPARE     (2U << GFXTIM_EVSR_FES1_Pos ) /*!< Absolute frame counter compare */
+#define GFXTIM_FRAME_EVENT_RFC1_RELOAD     (4U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counter 1 reload */
+#define GFXTIM_FRAME_EVENT_RFC2_RELOAD     (5U << GFXTIM_EVSR_FES1_Pos ) /*!< Relative frame counter 1 reload */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_EventGenerator GFXTIM Event Generator ID
+  * @{
+  */
+#define GFXTIM_EVENT_GENERATOR_1      0U  /*!< Event Generator 1 */
+#define GFXTIM_EVENT_GENERATOR_2      1U  /*!< Event Generator 2 */
+#define GFXTIM_EVENT_GENERATOR_3      2U  /*!< Event Generator 3 */
+#define GFXTIM_EVENT_GENERATOR_4      3U  /*!< Event Generator 4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup GFXTIM_WatchdogHwReloadConfig GFXTIM Watchdog hardware reload configuration
+  * @{
+  */
+#define GFXTIM_WATCHDOG_HW_RELOAD_DISABLE           (0U  <<  GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog hardware reload is disable */
+#define GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE       (1U  <<  GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog is reload on rising edge of gfxtim_wrld */
+#define GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE      (2U  <<  GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdog is reload on falling edge of gfxtim_wrld */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_WatchdogClockSrc GFXTIM Watchdog clock source
+  * @{
+  */
+#define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK       (0U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */
+#define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK      (1U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */
+#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING   (2U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising edge */
+#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING  (3U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling edge */
+#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING   (4U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising edge */
+#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING  (5U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling edge */
+#define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING      (6U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect rising edge */
+#define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING     (7U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect falling edge */
+#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1        (8U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 1 output */
+#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2        (9U  <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 2 output */
+#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_3        (10U <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 3 output */
+#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_4        (11U <<  GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 4 output */
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Flag GFXTIM flags
+  * @{
+  */
+#define GFXTIM_FLAG_AFCO  GFXTIM_ISR_AFCOF     /* Absolute Frame Counter Overflow Flag */
+#define GFXTIM_FLAG_ALCO  GFXTIM_ISR_ALCOF     /* Absolute Line Counter Overflow Flag */
+#define GFXTIM_FLAG_TE    GFXTIM_ISR_TEF       /* Tearing Effect Flag */
+#define GFXTIM_FLAG_AFCC1 GFXTIM_ISR_AFCC1F    /* Absolute Frame Counter Compare 1 Flag */
+#define GFXTIM_FLAG_ALCC1 GFXTIM_ISR_ALCC1F    /* Absolute Line Counter Compare 1 Flag */
+#define GFXTIM_FLAG_ALCC2 GFXTIM_ISR_ALCC2F    /* Absolute Line Counter Compare 2 Flag */
+#define GFXTIM_FLAG_RFC1R GFXTIM_ISR_RFC1RF    /* Relative Frame Counter 1 Reload Flag */
+#define GFXTIM_FLAG_RFC2R GFXTIM_ISR_RFC2RF    /* Relative Frame Counter 2 Reload Flag */
+#define GFXTIM_FLAG_EV1   GFXTIM_ISR_EV1F      /* Event 1 Flag */
+#define GFXTIM_FLAG_EV2   GFXTIM_ISR_EV2F      /* Event 2 Flag */
+#define GFXTIM_FLAG_EV3   GFXTIM_ISR_EV3F      /* Event 3 Flag */
+#define GFXTIM_FLAG_EV4   GFXTIM_ISR_EV4F      /* Event 4 Flag */
+#define GFXTIM_FLAG_WDGA  GFXTIM_ISR_WDGAF     /* Watchdog Alarm Flag */
+#define GFXTIM_FLAG_WDGP  GFXTIM_ISR_WDGPF     /* Watchdog Pre-alarm Flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GFXTIM_Private_Macros  GFXTIM Private Macros
+  * @{
+  */
+#define IS_GFXTIM_INTERRUPT(PARAM) (((PARAM) == GFXTIM_IT_ENABLE  ) || \
+                                    ((PARAM) == GFXTIM_IT_DISABLE ))
+
+#define IS_GFXTIM_SYNC_SRC(PARAM) (((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_0) || \
+                                   ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_1) || \
+                                   ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_2) || \
+                                   ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_3))
+
+#define IS_GFXTIM_TE_SRC(PARAM) (((PARAM) == GFXTIM_TE_SRC_GPIO ) || \
+                                 ((PARAM) == GFXTIM_TE_SRC_ITE       ) || \
+                                 ((PARAM) == GFXTIM_TE_SRC_HSYNC     ) || \
+                                 ((PARAM) == GFXTIM_TE_SRC_VSYNC     ))
+
+#define IS_GFXTIM_TE_POLARITY(PARAM) (((PARAM) == GFXTIM_TE_RISING_EDGE  ) || \
+                                      ((PARAM) == GFXTIM_TE_FALLING_EDGE ))
+
+#define IS_GFXTIM_LCC_HW_RELOAD_SRC(PARAM) (((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_NONE         ) || \
+                                            ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_FCC_UNDERFLOW) || \
+                                            ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_RISING ) || \
+                                            ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_HSYNC_FALLING) || \
+                                            ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_RISING ) || \
+                                            ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_VSYNC_FALLING) || \
+                                            ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_TE_RISING    ) || \
+                                            ((PARAM) == GFXTIM_LCC_HW_RELOAD_SRC_TE_FALLING    ))
+
+#define IS_GFXTIM_LCC_CLK_SRC(PARAM) (((PARAM) == GFXTIM_LCC_CLK_SRC_DISABLE) || \
+                                      ((PARAM) == GFXTIM_LCC_CLK_SRC_SYSCLOCK))
+
+#define IS_GFXTIM_LINE_CLK_SRC(PARAM)      (((PARAM) == GFXTIM_LINE_CLK_SRC_LCC_UNDERFLOW) || \
+                                            ((PARAM) == GFXTIM_LINE_CLK_SRC_FCC_UNDERFLOW) || \
+                                            ((PARAM) == GFXTIM_LINE_CLK_SRC_HSYNC_RISING ) || \
+                                            ((PARAM) == GFXTIM_LINE_CLK_SRC_HSYNC_FALLING) || \
+                                            ((PARAM) == GFXTIM_LINE_CLK_SRC_VSYNC_RISING ) || \
+                                            ((PARAM) == GFXTIM_LINE_CLK_SRC_VSYNC_FALLING) || \
+                                            ((PARAM) == GFXTIM_LINE_CLK_SRC_TE_RISING) || \
+                                            ((PARAM) == GFXTIM_LINE_CLK_SRC_TE_FALLING))
+
+#define IS_GFXTIM_FCC_HW_RELOAD_SRC(PARAM) (((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_NONE) || \
+                                            ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_LCC_UNDERFLOW) || \
+                                            ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_RISING ) || \
+                                            ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_HSYNC_FALLING) || \
+                                            ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_RISING ) || \
+                                            ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_VSYNC_FALLING) || \
+                                            ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_TE_RISING) || \
+                                            ((PARAM) == GFXTIM_FCC_HW_RELOAD_SRC_TE_FALLING))
+
+#define IS_GFXTIM_FCC_CLK_SRC(PARAM) (((PARAM) == GFXTIM_FCC_CLK_SRC_DISABLE) || \
+                                      ((PARAM) == GFXTIM_FCC_CLK_SRC_LCC_UNDERFLOW) || \
+                                      ((PARAM) == GFXTIM_FCC_CLK_SRC_HSYNC_RISING ) || \
+                                      ((PARAM) == GFXTIM_FCC_CLK_SRC_HSYNC_FALLING) || \
+                                      ((PARAM) == GFXTIM_FCC_CLK_SRC_VSYNC_RISING ) || \
+                                      ((PARAM) == GFXTIM_FCC_CLK_SRC_VSYNC_FALLING) || \
+                                      ((PARAM) == GFXTIM_FCC_CLK_SRC_TE_RISING) || \
+                                      ((PARAM) == GFXTIM_FCC_CLK_SRC_TE_FALLING))
+
+#define IS_GFXTIM_FRAME_CLK_SRC(PARAM) (((PARAM) == GFXTIM_FRAME_CLK_SRC_LCC_UNDERFLOW) || \
+                                        ((PARAM) == GFXTIM_FRAME_CLK_SRC_FCC_UNDERFLOW) || \
+                                        ((PARAM) == GFXTIM_FRAME_CLK_SRC_HSYNC_RISING ) || \
+                                        ((PARAM) == GFXTIM_FRAME_CLK_SRC_HSYNC_FALLING) || \
+                                        ((PARAM) == GFXTIM_FRAME_CLK_SRC_VSYNC_RISING ) || \
+                                        ((PARAM) == GFXTIM_FRAME_CLK_SRC_VSYNC_FALLING) || \
+                                        ((PARAM) == GFXTIM_FRAME_CLK_SRC_TE_RISING) || \
+                                        ((PARAM) == GFXTIM_FRAME_CLK_SRC_TE_FALLING))
+
+#define IS_GFXTIM_LINE_CLK_CALIB(PARAM) (((PARAM) == GFXTIM_LINE_CLK_CALIB_DISABLE) || \
+                                         ((PARAM) == GFXTIM_LINE_CLK_CALIB_ENABLE))
+
+#define IS_GFXTIM_FRAME_CLK_CALIB(PARAM) (((PARAM) == GFXTIM_FRAME_CLK_CALIB_DISABLE) || \
+                                          ((PARAM) == GFXTIM_FRAME_CLK_CALIB_ENABLE))
+
+#define IS_GFXTIM_CLOCK_GENERATOR_COUNTER(PARAM) (((PARAM) == GFXTIM_LINE_CLK_COUNTER) || \
+                                                  ((PARAM) == GFXTIM_FRAME_CLK_COUNTER) || \
+                                                  ((PARAM) == (GFXTIM_LINE_CLK_COUNTER | \
+                                                               GFXTIM_FRAME_CLK_COUNTER)))
+
+#define IS_GFXTIM_ABSOLUTE_TIME(PARAM) (((PARAM) == GFXTIM_ABSOLUTE_GLOBAL_TIME) || \
+                                        ((PARAM) == GFXTIM_ABSOLUTE_FRAME_TIME) || \
+                                        ((PARAM) == GFXTIM_ABSOLUTE_LINE_TIME))
+
+#define IS_GFXTIM_ABSOLUTE_LINE_COMPARATOR(PARAM) (((PARAM) == GFXTIM_ABSOLUTE_LINE_COMPARE1) || \
+                                                   ((PARAM) == GFXTIM_ABSOLUTE_LINE_COMPARE2))
+
+#define IS_GFXTIM_RELATIVE_TIMER(PARAM) (((PARAM) == GFXTIM_RELATIVE_TIMER1) || \
+                                         ((PARAM) == GFXTIM_RELATIVE_TIMER2))
+
+#define IS_GFXTIM_RELATIVE_COUNTER_MODE(PARAM) (((PARAM) == GFXTIM_MODE_ONE_SHOT) || \
+                                                ((PARAM) == GFXTIM_MODE_CONTINUOUS))
+
+#define IS_GFXTIM_EVENT_LINE(PARAM) (((PARAM) == GFXTIM_LINE_EVENT_NONE) || \
+                                     ((PARAM) == GFXTIM_LINE_EVENT_ALC_OVERFLOW) || \
+                                     ((PARAM) == GFXTIM_LINE_EVENT_TE) || \
+                                     ((PARAM) == GFXTIM_LINE_EVENT_ALC1_COMPARE) || \
+                                     ((PARAM) == GFXTIM_LINE_EVENT_ALC2_COMPARE))
+
+#define IS_GFXTIM_EVENT_FRAME(PARAM) (((PARAM) == GFXTIM_FRAME_EVENT_NONE) || \
+                                      ((PARAM) == GFXTIM_FRAME_EVENT_AFC_OVERFLOW) || \
+                                      ((PARAM) == GFXTIM_FRAME_EVENT_AFC_COMPARE) || \
+                                      ((PARAM) == GFXTIM_FRAME_EVENT_RFC1_RELOAD) || \
+                                      ((PARAM) == GFXTIM_FRAME_EVENT_RFC2_RELOAD))
+
+#define IS_GFXTIM_EVENT_GENERATOR(PARAM) (((PARAM) == GFXTIM_EVENT_GENERATOR_1) || \
+                                          ((PARAM) == GFXTIM_EVENT_GENERATOR_2) || \
+                                          ((PARAM) == GFXTIM_EVENT_GENERATOR_3) || \
+                                          ((PARAM) == GFXTIM_EVENT_GENERATOR_4))
+
+
+#define IS_GFXTIM_CLOCK_GENERATOR_COUNTER_FORCE_RELOAD(PARAM) (((PARAM) == GFXTIM_LINE_CLK_COUNTER) || \
+                                                               ((PARAM) == GFXTIM_FRAME_CLK_COUNTER) || \
+                                                               ((PARAM) == (GFXTIM_LINE_CLK_COUNTER | \
+                                                                            GFXTIM_FRAME_CLK_COUNTER)))
+
+
+#define IS_GFXTIM_WATCHDOG_HW_RELOAD_CONFIG(PARAM) (((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_DISABLE) || \
+                                                    ((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE) || \
+                                                    ((PARAM) == GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE))
+
+#define IS_GFXTIM_WATCHDOG_CLOCK_SRC(PARAM) (((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_TE_RISING) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_1) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_2) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_3) || \
+                                             ((PARAM) == GFXTIM_WATCHDOG_CLK_SRC_EVENT_4))
+#define IS_GFXTIM_WATCHDOG_VALUE(PARAM) ((PARAM) <= 65535U)
+#define IS_GFXTIM_RELATIVE_FRAME_VALUE(PARAM) ((PARAM) <= 4095U)
+#define IS_GFXTIM_ABSOLUTE_FRAME_VALUE(PARAM) ((PARAM) <= 1048575U)
+#define IS_GFXTIM_ABSOLUTE_LINE_VALUE(PARAM) ((PARAM) <= 4095U)
+#define IS_GFXTIM_LCC_RELOAD_VALUE(PARAM) ((PARAM) <= 4194303U)
+#define IS_GFXTIM_FCC_RELOAD_VALUE(PARAM) ((PARAM) <= 4095U)
+
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GFXTIM_Exported_Macros  GFXTIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset GFXTIM handle state.
+  * @param  __HANDLE__ GFXTIM handle.
+  * @retval None
+  */
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+#define __HAL_GFXTIM_RESET_HANDLE_STATE(__HANDLE__) do{                                             \
+                                                        (__HANDLE__)->State = HAL_GFXTIM_STATE_RESET; \
+                                                        (__HANDLE__)->MspInitCallback = NULL;      \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                      } while(0)
+#else /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+#define __HAL_GFXTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXTIM_STATE_RESET)
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+
+
+
+/**
+  * @brief Check whether the specified GFXTIM flag is set or not.
+  * @param __HANDLE__ GFXTIM handle
+  * @param __FLAG__ GFXTIM flag
+  *        This parameter can be one or a combination of the following values:
+  *            @arg @ref GFXTIM_FLAG_AFCO   Absolute Frame Counter Overflow Flag
+  *            @arg @ref GFXTIM_FLAG_ALCO   Absolute Line Counter Overflow Flag
+  *            @arg @ref GFXTIM_FLAG_TE     Tearing Effect Flag
+  *            @arg @ref GFXTIM_FLAG_AFCC1  Absolute Frame Counter Compare 1 Flag
+  *            @arg @ref GFXTIM_FLAG_ALCC1  Absolute Line Counter Compare 1 Flag
+  *            @arg @ref GFXTIM_FLAG_ALCC2  Absolute Line Counter Compare 2 Flag
+  *            @arg @ref GFXTIM_FLAG_RFC1R  Relative Frame Counter 1 Reload Flag
+  *            @arg @ref GFXTIM_FLAG_RFC2R  Relative Frame Counter 2 Reload Flag
+  *            @arg @ref GFXTIM_FLAG_EV1    Event 1 Flag
+  *            @arg @ref GFXTIM_FLAG_EV2    Event 2 Flag
+  *            @arg @ref GFXTIM_FLAG_EV3    Event 3 Flag
+  *            @arg @ref GFXTIM_FLAG_EV4    Event 4 Flag
+  *            @arg @ref GFXTIM_FLAG_WDGA   Watchdog Alarm Flag
+  *            @arg @ref GFXTIM_FLAG_WDGP   Watchdog Pre-alarm Flag
+  * @retval State of flag (TRUE or FALSE).
+  */
+#define __HAL_GFXTIM_GET_FLAG(__HANDLE__, __FLAG__)\
+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Clear the specified GFXTIM flag.
+  * @param __HANDLE__ GFXTIM handle
+  * @param __FLAG__ GFXTIM flag
+  *        This parameter can be one or a combination of the following values:
+  *            @arg @ref GFXTIM_FLAG_AFCO   Absolute Frame Counter Overflow Flag
+  *            @arg @ref GFXTIM_FLAG_ALCO   Absolute Line Counter Overflow Flag
+  *            @arg @ref GFXTIM_FLAG_TE     Tearing Effect Flag
+  *            @arg @ref GFXTIM_FLAG_AFCC1  Absolute Frame Counter Compare 1 Flag
+  *            @arg @ref GFXTIM_FLAG_ALCC1  Absolute Line Counter Compare 1 Flag
+  *            @arg @ref GFXTIM_FLAG_ALCC2  Absolute Line Counter Compare 2 Flag
+  *            @arg @ref GFXTIM_FLAG_RFC1R  Relative Frame Counter 1 Reload Flag
+  *            @arg @ref GFXTIM_FLAG_RFC2R  Relative Frame Counter 2 Reload Flag
+  *            @arg @ref GFXTIM_FLAG_EV1    Event 1 Flag
+  *            @arg @ref GFXTIM_FLAG_EV2    Event 2 Flag
+  *            @arg @ref GFXTIM_FLAG_EV3    Event 3 Flag
+  *            @arg @ref GFXTIM_FLAG_EV4    Event 4 Flag
+  *            @arg @ref GFXTIM_FLAG_WDGA   Watchdog Alarm Flag
+  *            @arg @ref GFXTIM_FLAG_WDGP   Watchdog Pre-alarm Flag
+  * @retval None
+  */
+#define __HAL_GFXTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)\
+  (((__HANDLE__)->Instance->ICR) = (__FLAG__))
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GFXTIM_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup GFXTIM_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_GFXTIM_Init(GFXTIM_HandleTypeDef *hgfxtim);
+HAL_StatusTypeDef HAL_GFXTIM_DeInit(GFXTIM_HandleTypeDef *hgfxtim);
+void              HAL_GFXTIM_MspInit(GFXTIM_HandleTypeDef *hgfxtim);
+void              HAL_GFXTIM_MspDeInit(GFXTIM_HandleTypeDef *hgfxtim);
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_GFXTIM_RegisterCallback(GFXTIM_HandleTypeDef *hgfxtim,
+                                              HAL_GFXTIM_CallbackIDTypeDef CallbackID,
+                                              pGFXTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_GFXTIM_UnRegisterCallback(GFXTIM_HandleTypeDef *hgfxtim,
+                                                HAL_GFXTIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+void HAL_GFXTIM_TECallback(GFXTIM_HandleTypeDef *hgfxtim);
+/**
+  * @}
+  */
+
+/* Clock Generator functions  *****************************************************/
+/** @addtogroup GFXTIM_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                   const GFXTIM_ClockGeneratorConfigTypeDef *pClockGeneratorConfig);
+HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Reload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t ClockGeneratorCounter);
+/**
+  * @}
+  */
+
+/* Absolute Timer functions  *****************************************/
+/** @addtogroup GFXTIM_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                  const GFXTIM_AbsoluteTimerConfigTypeDef *pAbsoluteTimerConfig);
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Start(GFXTIM_HandleTypeDef *hgfxtim);
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim);
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Reset(GFXTIM_HandleTypeDef *hgfxtim);
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime,
+                                                      uint32_t *pValue);
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetFrameCompare(GFXTIM_HandleTypeDef *hgfxtim, uint32_t Value);
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetLineCompare(GFXTIM_HandleTypeDef *hgfxtim,
+                                                          uint32_t AbsoluteLineComparator,
+                                                          uint32_t Value);
+void HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(GFXTIM_HandleTypeDef *hgfxtim);
+/**
+  * @}
+  */
+
+/* Relative Timer functions  *****************************************/
+/** @addtogroup GFXTIM_Exported_Functions_Group4
+  * @{
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                  const GFXTIM_RelativeTimerConfigTypeDef *pRelativeTimerConfig,
+                                                  uint32_t RelativeTimer);
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Start(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer);
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer);
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_ForceReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer);
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_SetReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer,
+                                                     uint32_t Value);
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer,
+                                                      uint32_t *pValue);
+void HAL_GFXTIM_RelativeTimer_RFC1RCallback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_RelativeTimer_RFC2RCallback(GFXTIM_HandleTypeDef *hgfxtim);
+/**
+  * @}
+  */
+
+/* Event Generator functions  *****************************************/
+/** @addtogroup GFXTIM_Exported_Functions_Group5
+  * @{
+  */
+HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator,
+                                                   const GFXTIM_EventGeneratorConfigTypeDef *pEventGeneratorConfig);
+HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Enable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator);
+HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Disable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator);
+void HAL_GFXTIM_EventGenerator_EV1Callback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_EventGenerator_EV2Callback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_EventGenerator_EV3Callback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_EventGenerator_EV4Callback(GFXTIM_HandleTypeDef *hgfxtim);
+/**
+  * @}
+  */
+
+/* Watchdog functions  *****************************************/
+/** @addtogroup GFXTIM_Exported_Functions_Group6
+  * @{
+  */
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                  const GFXTIM_WatchdogConfigTypeDef *pWatchdogConfig);
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Enable(GFXTIM_HandleTypeDef *hgfxtim);
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Disable(GFXTIM_HandleTypeDef *hgfxtim);
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Refresh(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_WatchdogTimer_AlarmCallback(GFXTIM_HandleTypeDef *hgfxtim);
+void HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(GFXTIM_HandleTypeDef *hgfxtim);
+/**
+  * @}
+  */
+
+/* Generic functions  *********************************************************/
+/** @addtogroup GFXTIM_Exported_Functions_Group7
+  * @{
+  */
+void                    HAL_GFXTIM_IRQHandler(GFXTIM_HandleTypeDef *hgfxtim);
+void                    HAL_GFXTIM_ErrorCallback(GFXTIM_HandleTypeDef *hgfxtim);
+uint32_t                HAL_GFXTIM_GetError(const GFXTIM_HandleTypeDef *hgfxtim);
+HAL_GFXTIM_StateTypeDef HAL_GFXTIM_GetState(const GFXTIM_HandleTypeDef *hgfxtim);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* GFXTIM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_GFXTIM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpio.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpio.h
new file mode 100644
index 000000000..d2594c669
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpio.h
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gpio.h
+  * @author  GPM Application Team
+  * @brief   Header for gpio.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_GPIO_H
+#define STM32N6xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins */
+
+  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode */
+
+  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull */
+
+  uint32_t Speed;      /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
+                           This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief   GPIO delay parameters structure definition
+  */
+typedef struct
+{
+  uint32_t Delay;      /*!< Specifies the delay to apply on signal of a pin.
+                           This parameter can be a value of @ref GPIO_delay */
+
+  uint32_t Path;       /*!< Specifies the path of the delay.
+                           This parameter can be a value of @ref GPIO_path */
+} GPIO_DelayTypeDef;
+
+/**
+  * @brief   GPIO retime parameters structure definition
+  */
+typedef struct
+{
+  uint32_t Retime;     /*!< Enable or disable the retime functionality on a pin
+                           This parameter can be any value of @ref GPIO_retime */
+
+  uint32_t Edge;       /*!< Specifies the clock edge for retime functionality.
+                           This parameter can be a value of @ref GPIO_clock */
+} GPIO_RetimeTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_ALL               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode GPIO mode
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0x00WX00YZ
+  *           - W  : EXTI trigger detection on 3 bits
+  *           - X  : EXTI mode (IT or Event) on 2 bits
+  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
+  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
+  * @{
+  */
+#define GPIO_MODE_INPUT                 MODE_INPUT                                                  /*!< Input Floating Mode                                                */
+#define GPIO_MODE_OUTPUT_PP             (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                                              */
+#define GPIO_MODE_OUTPUT_OD             (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                                             */
+#define GPIO_MODE_AF_PP                 (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode                                  */
+#define GPIO_MODE_AF_OD                 (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode                                 */
+#define GPIO_MODE_ANALOG                MODE_ANALOG                                                 /*!< Analog Mode                                                        */
+#define GPIO_MODE_IT_RISING             (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define GPIO_MODE_IT_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define GPIO_MODE_IT_RISING_FALLING     (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING            (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                    /*!< External Event Mode with Rising edge trigger detection             */
+#define GPIO_MODE_EVT_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                   /*!< External Event Mode with Falling edge trigger detection            */
+#define GPIO_MODE_EVT_RISING_FALLING    (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)  /*!< External Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed GPIO speed
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define GPIO_SPEED_FREQ_LOW             0x00000000u  /*!< Low speed       */
+#define GPIO_SPEED_FREQ_MEDIUM          0x00000001u  /*!< Medium speed    */
+#define GPIO_SPEED_FREQ_HIGH            0x00000002u  /*!< High speed      */
+#define GPIO_SPEED_FREQ_VERY_HIGH       0x00000003u  /*!< Very high speed */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull GPIO pull
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define GPIO_NOPULL                     0x00000000u   /*!< No Pull-up or Pull-down activation  */
+#define GPIO_PULLUP                     0x00000001u   /*!< Pull-up activation                  */
+#define GPIO_PULLDOWN                   0x00000002u   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_retime GPIO retime control
+  * @brief GPIO data retime enable/disable
+  * @{
+  */
+#define GPIO_RETIME_OFF                 0x00000000u                /*!< Retime disable at pad level  */
+#define GPIO_RETIME_ON                  GPIO_ADVCFGRL_RET0         /*!< Retime enable at pad level   */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_clock GPIO clock control
+  * @brief GPIO clock edge configuration for retime functionality
+  * @{
+  */
+#define GPIO_CLOCK_RISING               0x00000000u               /*!< Retime on rising edge  */
+#define GPIO_CLOCK_FALLING              GPIO_ADVCFGRL_INVCLK0     /*!< Retime on falling edge  */
+#define GPIO_CLOCK_RISING_FALLING       GPIO_ADVCFGRL_DE0         /*!< Retime on both edge  */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_path GPIO path control
+  * @brief GPIO path configuration for delay functionality
+  * @{
+  */
+#define GPIO_PATH_OUT                   0x00000000u               /*!< Delay applied to output signal */
+#define GPIO_PATH_IN                    GPIO_ADVCFGRL_DLYPATH0    /*!< Delay applied to input signal */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_delay GPIO delay
+  * @brief GPIO delay in picosecond to apply on the input/output path depending the value of control GPIO_path
+  * @{
+  */
+#define GPIO_DELAY_PS_0               (GPIO_DELAYRL_DLY0_Pos)
+#define GPIO_DELAY_PS_300             (GPIO_DELAYRL_DLY0_0)
+#define GPIO_DELAY_PS_500             (GPIO_DELAYRL_DLY0_1)
+#define GPIO_DELAY_PS_750             (GPIO_DELAYRL_DLY0_1 | GPIO_DELAYRL_DLY0_0)
+#define GPIO_DELAY_PS_1000            (GPIO_DELAYRL_DLY0_2)
+#define GPIO_DELAY_PS_1250            (GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_0)
+#define GPIO_DELAY_PS_1500            (GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_1)
+#define GPIO_DELAY_PS_1750            (GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_1 | GPIO_DELAYRL_DLY0_0)
+#define GPIO_DELAY_PS_2000            (GPIO_DELAYRL_DLY0_3)
+#define GPIO_DELAY_PS_2250            (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_0)
+#define GPIO_DELAY_PS_2500            (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_1)
+#define GPIO_DELAY_PS_2750            (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_1 | GPIO_DELAYRL_DLY0_0)
+#define GPIO_DELAY_PS_3000            (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_2)
+#define GPIO_DELAY_PS_3250            (GPIO_DELAYRL_DLY0_3 | GPIO_DELAYRL_DLY0_2 | GPIO_DELAYRL_DLY0_0)
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_attributes GPIO attributes
+  * @brief GPIO pin secure/non-secure or/and privileged/non-privileged
+  * @{
+  */
+#define  GPIO_PIN_SEC                  (GPIO_PIN_ATTR_SEC_MASK | 0x00000001U)    /*!< Secure pin attribute         */
+#define  GPIO_PIN_NSEC                 (GPIO_PIN_ATTR_SEC_MASK | 0x00000000U)    /*!< Non-secure pin attribute     */
+#define  GPIO_PIN_PRIV                 (GPIO_PIN_ATTR_PRIV_MASK | 0x00000002U)   /*!< Privileged pin attribute     */
+#define  GPIO_PIN_NPRIV                (GPIO_PIN_ATTR_PRIV_MASK | 0x00000000U)   /*!< Non-privileged pin attribute */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Check whether the specified EXTI line is rising edge asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__)         (EXTI->RPR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI line rising pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__)       (EXTI->RPR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line is falling edge asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)        (EXTI->FPR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI line falling pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__)      (EXTI->FPR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line is asserted or not.
+  * @param __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
+                                                       __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)         \
+  do {                                                  \
+    __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__);     \
+    __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__);    \
+  } while(0)
+
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @param __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
+
+/**
+  * @brief  Clear the EXTI line pending flags.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE_Pos                           0u
+#define GPIO_MODE                               (0x3uL << GPIO_MODE_Pos)
+#define MODE_INPUT                              (0x0uL << GPIO_MODE_Pos)
+#define MODE_OUTPUT                             (0x1uL << GPIO_MODE_Pos)
+#define MODE_AF                                 (0x2uL << GPIO_MODE_Pos)
+#define MODE_ANALOG                             (0x3uL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos                         4u
+#define OUTPUT_TYPE                             (0x1uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP                               (0x0uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD                               (0x1uL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos                           16u
+#define EXTI_MODE                               (0x3uL << EXTI_MODE_Pos)
+#define EXTI_IT                                 (0x1uL << EXTI_MODE_Pos)
+#define EXTI_EVT                                (0x2uL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos                        20u
+#define TRIGGER_MODE                            (0x7uL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING                          (0x1uL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING                         (0x2uL << TRIGGER_MODE_Pos)
+#define GPIO_PIN_ATTR_SEC_MASK                  0x100U
+#define GPIO_PIN_ATTR_PRIV_MASK                 0x200U
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
+
+#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0)   ||\
+                                     ((__PIN__) == GPIO_PIN_1)   ||\
+                                     ((__PIN__) == GPIO_PIN_2)   ||\
+                                     ((__PIN__) == GPIO_PIN_3)   ||\
+                                     ((__PIN__) == GPIO_PIN_4)   ||\
+                                     ((__PIN__) == GPIO_PIN_5)   ||\
+                                     ((__PIN__) == GPIO_PIN_6)   ||\
+                                     ((__PIN__) == GPIO_PIN_7)   ||\
+                                     ((__PIN__) == GPIO_PIN_8)   ||\
+                                     ((__PIN__) == GPIO_PIN_9)   ||\
+                                     ((__PIN__) == GPIO_PIN_10)  ||\
+                                     ((__PIN__) == GPIO_PIN_11)  ||\
+                                     ((__PIN__) == GPIO_PIN_12)  ||\
+                                     ((__PIN__) == GPIO_PIN_13)  ||\
+                                     ((__PIN__) == GPIO_PIN_14)  ||\
+                                     ((__PIN__) == GPIO_PIN_15))
+
+#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
+
+#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                                     ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
+                                     ((__PULL__) == GPIO_PULLUP)   || \
+                                     ((__PULL__) == GPIO_PULLDOWN))
+
+#define IS_GPIO_DELAY(__DELAY__)    (((__DELAY__) == GPIO_DELAY_PS_0)      ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_300)    ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_500)    ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_750)    ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_1000)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_1250)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_1500)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_1750)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_2000)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_2250)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_2500)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_2750)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_3000)   ||\
+                                     ((__DELAY__) == GPIO_DELAY_PS_3250))
+
+#define IS_GPIO_RETIME(__RETIME__)  (((__RETIME__) == GPIO_RETIME_ON)   ||\
+                                     ((__RETIME__) == GPIO_RETIME_OFF))
+
+#define IS_GPIO_CLOCK(__CLOCK__)    (((__CLOCK__) == GPIO_CLOCK_RISING)    ||\
+                                     ((__CLOCK__) == GPIO_CLOCK_FALLING)   || \
+                                     ((__CLOCK__) == GPIO_CLOCK_RISING_FALLING))
+
+#define IS_GPIO_PATH(__PATH__)      (((__PATH__) == GPIO_PATH_OUT)   ||\
+                                     ((__PATH__) == GPIO_PATH_IN))
+
+#if defined CPU_IN_SECURE_STATE
+#define IS_GPIO_PIN_ATTRIBUTES(__ATTR__) (((((__ATTR__) & GPIO_PIN_SEC) == GPIO_PIN_SEC) || \
+                                           (((__ATTR__) & GPIO_PIN_NSEC) == GPIO_PIN_NSEC) || \
+                                           (((__ATTR__) & GPIO_PIN_PRIV) == GPIO_PIN_PRIV) || \
+                                           (((__ATTR__) & GPIO_PIN_NPRIV) == GPIO_PIN_NPRIV)) && \
+                                          (((__ATTR__) & ~(GPIO_PIN_SEC|GPIO_PIN_NSEC|GPIO_PIN_PRIV|GPIO_PIN_NPRIV)) == 0U))
+#else
+#define IS_GPIO_PIN_ATTRIBUTES(__ATTR__) (((((__ATTR__) & GPIO_PIN_PRIV) == GPIO_PIN_PRIV) || \
+                                           (((__ATTR__) & GPIO_PIN_NPRIV) == GPIO_PIN_NPRIV)) && \
+                                          (((__ATTR__) & ~(GPIO_PIN_PRIV | GPIO_PIN_NPRIV)) == 0U))
+#endif /* CPU_IN_SECURE_STATE */
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extended module */
+#include "stm32n6xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  *  @brief    GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *****************************/
+void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, const GPIO_InitTypeDef *GPIO_Init);
+void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+  *  @brief    IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState     HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_SetRetime(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_RetimeTypeDef *pRet_Init);
+HAL_StatusTypeDef HAL_GPIO_GetRetime(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_RetimeTypeDef *pRet_Init);
+void              HAL_GPIO_SetDelay(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_DelayTypeDef *pDly_Init);
+HAL_StatusTypeDef HAL_GPIO_GetDelay(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_DelayTypeDef *pDly_Init);
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+#if defined CPU_IN_SECURE_STATE
+
+/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions
+  * @{
+  */
+
+/* IO attributes management functions *****************************************/
+void              HAL_GPIO_LockPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+uint32_t          HAL_GPIO_GetLockPinAttributes(const GPIO_TypeDef *GPIOx);
+#endif /* CPU_IN_SECURE_STATE */
+void              HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes);
+HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
+                                                  uint32_t *pPinAttributes);
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_GPIO_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpio_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpio_ex.h
new file mode 100644
index 000000000..03f97dcbf
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpio_ex.h
@@ -0,0 +1,274 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gpio_ex.h
+  * @author  GPM Application Team
+  * @brief   Header file of GPIO HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_GPIO_EX_H
+#define STM32N6xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @brief GPIO Extended HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+  * @{
+  */
+
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_PWR           ((uint8_t)0x00)  /*!< PWR Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO Alternate Function mapping */
+#define GPIO_AF0_RTC           ((uint8_t)0x00)  /*!< RTC Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /*!< TRACE Alternate Function mapping */
+#define GPIO_AF0_SYS           ((uint8_t)0x00)  /*!< BOOT1 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_LPTIM5        ((uint8_t)0x01)  /*!< LPTIM5 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_GFXTIM        ((uint8_t)0x02)  /*!< GFXTIM Alternate Function mapping */
+#define GPIO_AF2_I3C2          ((uint8_t)0x02)  /*!< I3C2 Alternate Function mapping */
+#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /*!< SAI1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /*!< TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM8          ((uint8_t)0x02)  /*!< TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /*!< TIM12 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_ADF1          ((uint8_t)0x03)  /*!< ADF1 Alternate Function mapping */
+#define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /*!< LPTIM3 Alternate Function mapping */
+#define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /*!< LPTIM4 Alternate Function mapping */
+#define GPIO_AF3_LPUART1       ((uint8_t)0x03)  /*!< LPUART1 Alternate Function mapping */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /*!< TIM9 Alternate Function mapping */
+#define GPIO_AF3_USART3        ((uint8_t)0x03)  /*!< USART3 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /*!< I2C3 Alternate Function mapping */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /*!< I2C4 Alternate Function mapping */
+#define GPIO_AF4_I3C1          ((uint8_t)0x04)  /*!< I3C1 Alternate Function mapping */
+#define GPIO_AF4_MDF1          ((uint8_t)0x04)  /*!< MDF1 Alternate Function mapping */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< UASRT1 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_I3C1          ((uint8_t)0x05)  /*!< I3C1 Alternate Function mapping */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /*!< SPI3 Alternate Function mapping */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /*!< SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /*!< SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /*!< SPI6 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_FDCAN1        ((uint8_t)0x06)  /*!< FDCAN1 Alternate Function mapping */
+#define GPIO_AF6_FDCAN2        ((uint8_t)0x06)  /*!< FDCAN2 Alternate Function mapping */
+#define GPIO_AF6_FDCAN3        ((uint8_t)0x06)  /*!< FDCAN3 Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /*!< SAI1 Alternate Function mapping */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /*!< SPI3 Alternate Function mapping */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /*!< SPI4 Alternate Function mapping */
+#define GPIO_AF6_UCPD1         ((uint8_t)0x06)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF6_USART10       ((uint8_t)0x06)  /*!< USART10 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_I3C1          ((uint8_t)0x07)  /*!< I3C1 Alternate Function mapping */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /*!< SPI3 Alternate Function mapping */
+#define GPIO_AF7_SPI6          ((uint8_t)0x07)  /*!< SPI6 Alternate Function mapping */
+#define GPIO_AF7_TIM15         ((uint8_t)0x07)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF7_UART9         ((uint8_t)0x07)  /*!< UART9 Alternate Function mapping */
+#define GPIO_AF7_UCPD1         ((uint8_t)0x07)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF7_USART6        ((uint8_t)0x07)  /*!< USART6 Alternate Function mapping */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_GFXTIM        ((uint8_t)0x08)  /*!< GFXTIM Alternate Function mapping */
+#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08)  /*!< SPDIFRX Alternate Function mapping */
+#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /*!< SPI6 Alternate Function mapping */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /*!< UART4 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /*!< UART7 Alternate Function mapping */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /*!< UART8 Alternate Function mapping */
+#define GPIO_AF8_USART2        ((uint8_t)0x08)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_XSPIM_P1      ((uint8_t)0x09)  /*!< XSPIM Manager Port 1 Alternate Function mapping  */
+#define GPIO_AF9_XSPIM_P2      ((uint8_t)0x09)  /*!< XSPIM Manager Port 2 Alternate Function mapping  */
+#define GPIO_AF9_PSSI          ((uint8_t)0x09)  /*!< PSSI Alternate Function mapping */
+#define GPIO_AF9_SPI5          ((uint8_t)0x09)  /*!< SPI5 Alternate Function mapping */
+#define GPIO_AF9_TIM11         ((uint8_t)0x09)  /*!< TIM11 Alternate Function mapping */
+#define GPIO_AF9_DCMIPP        ((uint8_t)0x09)  /*!< DCMIPP Alternate Function mapping */
+#define GPIO_AF9_DCMI          ((uint8_t)0x09)  /*!< DCMI Alternate Function mapping */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_LCD          ((uint8_t)0x0A)  /*!< LCD Alternate Function mapping */
+#define GPIO_AF10_MDIOS        ((uint8_t)0x0A)  /*!< MDIOS Alternate Function mapping */
+#define GPIO_AF10_PSSI         ((uint8_t)0x0A)  /*!< PSSI Alternate Function mapping */
+#define GPIO_AF10_SAI2         ((uint8_t)0x0A)  /*!< SAI2 Alternate Function mapping */
+#define GPIO_AF10_SDMMC1       ((uint8_t)0x0A)  /*!< SDMMC1 Alternate Function mapping */
+#define GPIO_AF10_SPI1         ((uint8_t)0x0A)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF10_TIM10        ((uint8_t)0x0A)  /*!< TIM10 Alternate Function mapping */
+#define GPIO_AF10_TIM13        ((uint8_t)0x0A)  /*!< TIM13 Alternate Function mapping */
+#define GPIO_AF10_UART7        ((uint8_t)0x0A)  /*!< UART7 Alternate Function mapping */
+#define GPIO_AF10_FMC          ((uint8_t)0x0A)  /*!< FMC Alternate Function mapping */
+#define GPIO_AF10_DCMIPP       ((uint8_t)0x0A)  /*!< DCMIPP Alternate Function mapping */
+#define GPIO_AF10_DCMI         ((uint8_t)0x0A)  /*!< DCMI Alternate Function mapping */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_ETH1         ((uint8_t)0x0B)  /*!< ETH1 Alternate Function mapping */
+#define GPIO_AF11_MDIOS        ((uint8_t)0x0B)  /*!< MDIOS Alternate Function mapping */
+#define GPIO_AF11_SDMMC2       ((uint8_t)0x0B)  /*!< SDMMC2 Alternate Function mapping */
+#define GPIO_AF11_UART5        ((uint8_t)0x0B)  /*!< UART5 Alternate Function mapping */
+#define GPIO_AF11_TIM14        ((uint8_t)0x0B)  /*!< TIM14 Alternate Function mapping */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_ETH1         ((uint8_t)0x0C)  /*!< ETH1 Alternate Function mapping */
+#define GPIO_AF12_FMC          ((uint8_t)0x0C)  /*!< FMC Alternate Function mapping */
+#define GPIO_AF12_GFXTIM       ((uint8_t)0x0C)  /*!< GFXTIM Alternate Function mapping */
+#define GPIO_AF12_LCD          ((uint8_t)0x0C)  /*!< LCD Alternate Function mapping */
+#define GPIO_AF12_SDMMC1       ((uint8_t)0x0C)  /*!< SDMMC1 Alternate Function mapping */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_GFXTIM       ((uint8_t)0x0D)  /*!< GFXTIM Alternate Function mapping */
+#define GPIO_AF13_TIM1         ((uint8_t)0x0D)  /*!< TIM1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_FMC          ((uint8_t)0x0E)   /*!< FMC Alternate Function mapping */
+#define GPIO_AF14_LCD          ((uint8_t)0x0E)   /*!< LCD Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT     ((uint8_t)0x0F)    /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_HDP          ((uint8_t)0x0F)    /*!< HDP Alternate Function mapping */
+
+/**
+  * @brief   check if AF is valid
+  */
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
+  * @{
+  */
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\
+                                      ((__GPIOx__) == (GPIOD))? 3uL :\
+                                      ((__GPIOx__) == (GPIOE))? 4uL :\
+                                      ((__GPIOx__) == (GPIOF))? 5uL :\
+                                      ((__GPIOx__) == (GPIOG))? 6uL :\
+                                      ((__GPIOx__) == (GPIOH))? 7uL :\
+                                      ((__GPIOx__) == (GPION))? 8uL :\
+                                      ((__GPIOx__) == (GPIOO))? 9uL :\
+                                      ((__GPIOx__) == (GPIOP))? 10uL :\
+                                      ((__GPIOx__) == (GPIOQ))? 11uL : 16uL)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_GPIO_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpu2d.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpu2d.h
new file mode 100644
index 000000000..ab023732d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_gpu2d.h
@@ -0,0 +1,321 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gpu2d.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPU2D HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_GPU2D_H
+#define STM32N6xx_HAL_GPU2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (GPU2D)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPU2D GPU2D
+  * @brief GPU2D HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPU2D_Exported_Types GPU2D Exported Types
+  * @{
+  */
+/**
+  * @brief  HAL GPU2D State enumeration definition
+  */
+typedef enum
+{
+  HAL_GPU2D_STATE_RESET             = 0x00U,    /*!< GPU2D not yet initialized or disabled      */
+  HAL_GPU2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use   */
+  HAL_GPU2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing             */
+  HAL_GPU2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                              */
+  HAL_GPU2D_STATE_ERROR             = 0x04U
+} HAL_GPU2D_StateTypeDef;
+
+/**
+  * @brief  GPU2D_TypeDef definition
+  */
+typedef uint32_t GPU2D_TypeDef;
+
+/**
+  * @brief  GPU2D handle Structure definition
+  */
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+typedef struct __GPU2D_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+{
+  GPU2D_TypeDef                Instance;                                                      /*!< GPU2D register base address.               */
+
+  HAL_LockTypeDef              Lock;                                                          /*!< GPU2D lock.                                */
+
+  __IO HAL_GPU2D_StateTypeDef  State;                                                         /*!< GPU2D transfer state.                      */
+
+  __IO uint32_t                ErrorCode;                                                     /*!< GPU2D error code.                          */
+
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+  void (* CommandListCpltCallback)(struct __GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID); /*!< GPU2D Command Complete Callback            */
+
+  void (* MspInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d);                             /*!< GPU2D Msp Init callback                    */
+
+  void (* MspDeInitCallback)(struct __GPU2D_HandleTypeDef *hgpu2d);                           /*!< GPU2D Msp DeInit callback                  */
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+} GPU2D_HandleTypeDef;
+
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL GPU2D Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_GPU2D_MSPINIT_CB_ID             = 0x00U,    /*!< GPU2D MspInit callback ID                 */
+  HAL_GPU2D_MSPDEINIT_CB_ID           = 0x01U,    /*!< GPU2D MspDeInit callback ID               */
+} HAL_GPU2D_CallbackIDTypeDef;
+
+/** @defgroup HAL_GPU2D_Callback_pointer_definition HAL GPU2D Callback pointer definition
+  * @brief  HAL GPU2D Callback pointer definition
+  * @{
+  */
+typedef  void (*pGPU2D_CallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d);                                /*!< pointer to an GPU2D Callback function                       */
+typedef  void (*pGPU2D_CommandListCpltCallbackTypeDef)(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdID); /*!< pointer to an GPU2D Command List Complete Callback function */
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPU2D_Exported_Constants GPU2D Exported Constants
+  * @{
+  */
+
+/** @defgroup GPU2D_Error_Code_definition GPU2D Error Code definition
+  * @brief  GPU2D Error Code definition
+  * @{
+  */
+#define HAL_GPU2D_ERROR_NONE             (0x00000000U)  /*!< No error                */
+#define HAL_GPU2D_ERROR_TIMEOUT          (0x00000001U)  /*!< Timeout error           */
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+#define HAL_GPU2D_ERROR_INVALID_CALLBACK (0x00000002U)  /*!< Invalid callback error  */
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+/**
+  * @}
+  */
+
+/** @defgroup GPU2D_Interrupt_configuration_definition GPU2D Interrupt configuration definition
+  * @brief GPU2D Interrupt definition
+  * @{
+  */
+#define GPU2D_IT_CLC                     0x00000001U              /*!< Command List Complete Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup GPU2D_Flag_definition GPU2D Flag definition
+  * @brief GPU2D Flags definition
+  * @{
+  */
+#define GPU2D_FLAG_CLC                   0x00000001U              /*!< Command List Complete Interrupt Flag  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup GPU2D_Exported_Macros GPU2D Exported Macros
+  * @{
+  */
+
+/** @brief Reset GPU2D handle state
+  * @param  __HANDLE__: specifies the GPU2D handle.
+  * @retval None
+  */
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) do {                                               \
+                                                        (__HANDLE__)->State = HAL_GPU2D_STATE_RESET;  \
+                                                        (__HANDLE__)->MspInitCallback = NULL;         \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;       \
+                                                        (__HANDLE__)->CommandListCpltCallback = NULL; \
+                                                      } while(0)
+#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
+#define __HAL_GPU2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GPU2D_STATE_RESET)
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the GPU2D pending flags.
+  * @param  __HANDLE__: GPU2D handle
+  * @param  __FLAG__: flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg GPU2D_FLAG_CLC:   Command List Complete interrupt mask
+  * @retval The state of FLAG.
+  */
+#define __HAL_GPU2D_GET_FLAG(__HANDLE__, __FLAG__) (READ_REG(*(__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
+                                                                                + GPU2D_ITCTRL)) & (__FLAG__))
+
+/**
+  * @brief  Clear the GPU2D pending flags.
+  * @param  __HANDLE__: GPU2D handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg GPU2D_FLAG_CLC:   Command List Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_GPU2D_CLEAR_FLAG(__HANDLE__, __FLAG__) do { \
+                                                          __IO uint32_t *tmpreg = \
+                                                            (__IO uint32_t *)((uint32_t)(__HANDLE__)->Instance\
+                                                                              + GPU2D_ITCTRL); \
+                                                          CLEAR_BIT(*tmpreg, __FLAG__); \
+                                                        } while(0U)
+
+/**
+  * @brief  Check whether the specified GPU2D interrupt source is enabled or not.
+  * @param  __HANDLE__: GPU2D handle
+  * @param  __INTERRUPT__: specifies the GPU2D interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg GPU2D_IT_CLC:   Command List Complete interrupt mask
+  * @retval The state of INTERRUPT source.
+  */
+#define __HAL_GPU2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_REG(*(__IO uint32_t *)\
+                                                                       ((uint32_t)(__HANDLE__)->Instance\
+                                                                        + GPU2D_ITCTRL)) & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPU2D_Exported_Functions GPU2D Exported Functions
+  * @{
+  */
+
+/** @addtogroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d);
+HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d);
+void              HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d);
+void              HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
+                                             pGPU2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
+                                                            pGPU2D_CommandListCpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d);
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup GPU2D_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+uint32_t          HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset);
+HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value);
+void              HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
+void              HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d);
+void              HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID);
+void              HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d);
+
+/**
+  * @}
+  */
+
+/** @addtogroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State functions ***************************************************/
+HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d);
+uint32_t               HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d);
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup GPU2D_Private_Constants GPU2D Private Constants
+  * @{
+  */
+
+#define GPU2D_ITCTRL                    (0x0F8U)   /*!< GPU2D Interrupt Control Register Offset            */
+#define GPU2D_CLID                      (0x148U)   /*!< GPU2D Last Command List Identifier Register Offset */
+#define GPU2D_BREAKPOINT                (0x080U)   /*!< GPU2D Breakpoint Register Offset                   */
+#define GPU2D_SYS_INTERRUPT             (0xff8U)   /*!< GPU2D System Interrupt Register Offset             */
+
+/** @defgroup GPU2D_Offset GPU2D Last Register Offset
+  * @{
+  */
+#define GPU2D_OFFSET                     0x1000U                  /*!< Last GPU2D Register Offset */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
+  * @{
+  */
+#define IS_GPU2D_OFFSET(OFFSET)          ((OFFSET) < GPU2D_OFFSET)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPU2D) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_GPU2D_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_hash.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_hash.h
new file mode 100644
index 000000000..217338b12
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_hash.h
@@ -0,0 +1,581 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_hash.h
+  * @author  MCD Application Team
+  * @brief   Header file of HASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_HASH_H
+#define STM32N6xx_HAL_HASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (HASH)
+/** @defgroup HASH HASH
+  * @brief HASH HAL module driver.
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HASH_Exported_Types HASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HASH Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t DataType;    /*!< no swap (32-bit data), half word swap (16-bit data), byte swap (8-bit data) or bit swap
+                             (1-bit data). This parameter can be a value of @ref HASH_Data_Type.       */
+
+  uint32_t KeySize;     /*!< The key size is used only in HMAC operation.                 */
+
+  uint8_t *pKey;        /*!< The key is used only in HMAC operation.                      */
+
+  uint32_t Algorithm;   /*!<  HASH algorithm MD5, SHA1 or SHA2.
+                            This parameter can be a value of @ref HASH_Algorithm_Selection */
+
+
+} HASH_ConfigTypeDef;
+
+/**
+  * @brief HAL State structure definition
+  */
+typedef enum
+{
+  HAL_HASH_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized            */
+  HAL_HASH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
+  HAL_HASH_STATE_BUSY              = 0x02U,    /*!< Processing (hashing) is ongoing          */
+  HAL_HASH_STATE_SUSPENDED         = 0x03U     /*!< Suspended state                          */
+} HAL_HASH_StateTypeDef;
+
+/**
+  * @brief HAL phase structure definition
+  */
+typedef enum
+{
+  HAL_HASH_PHASE_READY             = 0x01U,    /*!< HASH peripheral is ready to start                  */
+  HAL_HASH_PHASE_PROCESS           = 0x02U,    /*!< HASH peripheral is in HASH processing phase        */
+  HAL_HASH_PHASE_HMAC_STEP_1       = 0x03U,    /*!< HASH peripheral is in HMAC step 1 processing phase
+                                              (step 1 consists in entering the inner hash function key)*/
+  HAL_HASH_PHASE_HMAC_STEP_2       = 0x04U,    /*!< HASH peripheral is in HMAC step 2 processing phase
+                                              (step 2 consists in entering the message text)           */
+  HAL_HASH_PHASE_HMAC_STEP_3       = 0x05U     /*!< HASH peripheral is in HMAC step 3 processing phase
+                                              (step 3 consists in entering the outer hash function key)*/
+
+} HAL_HASH_PhaseTypeDef;
+
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+/**
+  * @brief HAL HASH mode suspend definitions
+  */
+typedef enum
+{
+  HAL_HASH_SUSPEND_NONE            = 0x00U,    /*!< HASH peripheral suspension not requested */
+  HAL_HASH_SUSPEND                 = 0x01U     /*!< HASH peripheral suspension is requested  */
+} HAL_HASH_SuspendTypeDef;
+#endif /* USE_HAL_HASH_SUSPEND_RESUME */
+
+
+/**
+  * @brief  HASH Handle Structure definition
+  */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+typedef struct __HASH_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+{
+  HASH_TypeDef               *Instance;        /*!< HASH Register base address              */
+
+  HASH_ConfigTypeDef           Init;           /*!< HASH required parameters                */
+
+  uint8_t const              *pHashInBuffPtr;  /*!< Pointer to input buffer                 */
+
+  uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest)       */
+
+  __IO uint32_t              HashInCount;      /*!< Counter of inputted data                */
+
+  uint32_t                   Size;             /*!< Size of buffer to be processed in bytes */
+
+  uint8_t                   *pHashKeyBuffPtr;  /*!< Pointer to key buffer (HMAC only)       */
+
+  HAL_HASH_PhaseTypeDef      Phase;            /*!< HASH peripheral phase                   */
+
+  DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters           */
+
+  HAL_LockTypeDef            Lock;             /*!< Locking object                          */
+
+  __IO  uint32_t             ErrorCode;        /*!< HASH Error code                         */
+
+  __IO HAL_HASH_StateTypeDef State;            /*!< HASH peripheral state                   */
+
+  __IO  uint32_t             Accumulation;     /*!< HASH multi buffers accumulation flag    */
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+  void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash);         /*!< HASH input completion callback            */
+
+  void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash);       /*!< HASH digest computation complete callback */
+
+  void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash);          /*!< HASH error callback                       */
+
+  void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash);        /*!< HASH Msp Init callback                    */
+
+  void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash);      /*!< HASH Msp DeInit callback                  */
+
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+  __IO HAL_HASH_SuspendTypeDef    SuspendRequest;    /*!< HASH peripheral suspension request flag */
+
+  HASH_ConfigTypeDef         Init_saved;             /*!< Saved HASH required parameters          */
+
+  uint8_t const              *pHashInBuffPtr_saved;  /*!< Saved pointer to input buffer           */
+
+  uint8_t                    *pHashOutBuffPtr_saved; /*!< Saved pointer to output buffer (digest) */
+
+  __IO uint32_t              HashInCount_saved;      /*!< Saved counter of inputted data          */
+
+  uint32_t                   Size_saved;             /*!< Saved size of buffer to be processed    */
+
+  uint8_t                    *pHashKeyBuffPtr_saved; /*!< Saved pointer to key buffer (HMAC only) */
+
+  HAL_HASH_PhaseTypeDef      Phase_saved;            /*!< Saved HASH peripheral phase             */
+#endif /* USE_HAL_HASH_SUSPEND_RESUME */
+
+} HASH_HandleTypeDef;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  HAL HASH common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_HASH_MSPINIT_CB_ID           = 0x00U,    /*!< HASH MspInit callback ID                       */
+  HAL_HASH_MSPDEINIT_CB_ID         = 0x01U,    /*!< HASH MspDeInit callback ID                     */
+  HAL_HASH_INPUTCPLT_CB_ID         = 0x02U,    /*!< HASH input completion callback ID              */
+  HAL_HASH_DGSTCPLT_CB_ID          = 0x03U,    /*!< HASH digest computation completion callback ID */
+  HAL_HASH_ERROR_CB_ID             = 0x04U,    /*!< HASH error callback ID                         */
+} HAL_HASH_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL HASH Callback pointer definition
+  */
+typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash);  /*!< pointer to a HASH common callback functions */
+
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants  HASH Exported Constants
+  * @{
+  */
+
+/** @defgroup HASH_Error_Definition   HASH Error Definition
+  * @{
+  */
+#define  HAL_HASH_ERROR_NONE             0x00000000U   /*!< No error                */
+#define  HAL_HASH_ERROR_BUSY             0x00000001U   /*!< Busy flag error  */
+#define  HAL_HASH_ERROR_DMA              0x00000002U   /*!< DMA-based process error */
+#define  HAL_HASH_ERROR_TIMEOUT          0x00000004U   /*!< Timeout error */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+#define  HAL_HASH_ERROR_INVALID_CALLBACK 0x00000010U   /*!< Invalid Callback error  */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Algorithm_Selection   HASH algorithm selection
+  * @{
+  */
+#define HASH_ALGOSELECTION_SHA1         0x00000000U                         /*!< HASH function is SHA1   */
+#define HASH_ALGOSELECTION_SHA224       HASH_CR_ALGO_1                      /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256       (HASH_CR_ALGO_0 | HASH_CR_ALGO_1)   /*!< HASH function is SHA256 */
+#define HASH_ALGOSELECTION_SHA384       (HASH_CR_ALGO_2 |  HASH_CR_ALGO_3)  /*!< HASH function is SHA384 */
+#define HASH_ALGOSELECTION_SHA512_224   (HASH_CR_ALGO_0 | HASH_CR_ALGO_2 |  HASH_CR_ALGO_3)
+/*!< HASH function is SHA512_224 */
+#define HASH_ALGOSELECTION_SHA512_256   (HASH_CR_ALGO_1 | HASH_CR_ALGO_2 |  HASH_CR_ALGO_3)
+/*!< HASH function is SHA512_256 */
+#define HASH_ALGOSELECTION_SHA512        HASH_CR_ALGO                       /*!< HASH function is SHA512 */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Mode   HASH Mode
+  * @{
+  */
+#define HASH_ALGOMODE_HASH         0x00000000U     /*!< HASH mode */
+#define HASH_ALGOMODE_HMAC         HASH_CR_MODE    /*!< HMAC mode */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Data_Type      HASH Data Type
+  * @{
+  */
+#define HASH_NO_SWAP          0x00000000U        /*!< 32-bit data. No swapping                     */
+#define HASH_HALFWORD_SWAP    HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
+#define HASH_BYTE_SWAP        HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
+#define HASH_BIT_SWAP         HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_HMAC_KEY   key length only for HMAC mode
+  * @{
+  */
+#define HASH_SHORTKEY      0x00000000U   /*!< HMAC Key size is <= block size (64 or 128 bytes) */
+#define HASH_LONGKEY       HASH_CR_LKEY  /*!< HMAC Key size is > block size (64 or 128 bytes) */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_flags_definition  HASH flags definitions
+  * @{
+  */
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : new block can be entered 
+                                                       in the Peripheral */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                    */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing     */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data              */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : input buffer contains at least one word of data*/
+/**
+  * @}
+  */
+
+/** @defgroup HASH_interrupts_definition   HASH interrupts definitions
+  * @{
+  */
+#define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HASH_Exported_Macros HASH Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether or not the specified HASH flag is set.
+  * @param  __HANDLE__ specifies the HASH handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
+  *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
+  *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
+  *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) > 8U)  ?                           \
+                                                    ((((__HANDLE__)->Instance->CR & (__FLAG__)) == \
+                                                      (__FLAG__)) ? SET : RESET) :                     \
+                                                    ((((__HANDLE__)->Instance->SR & (__FLAG__)) == \
+                                                      (__FLAG__)) ? SET : RESET) )
+
+/** @brief  Clear the specified HASH flag.
+  * @param  __HANDLE__ specifies the HASH handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_CLEAR_FLAG(__HANDLE__, __FLAG__) CLEAR_BIT((__HANDLE__)->Instance->SR, (__FLAG__))
+
+/** @brief  Check whether the specified HASH interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the HASH handle.
+  * @param __INTERRUPT__ HASH interrupt source to check
+  *         This parameter can be one of the following values :
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval State of interruption (TRUE or FALSE).
+  */
+#define __HAL_HASH_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMR\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief  Enable the specified HASH interrupt.
+  * @param  __HANDLE__ specifies the HASH handle.
+  * @param  __INTERRUPT__ specifies the HASH interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__))
+
+/** @brief  Disable the specified HASH interrupt.
+  * @param  __HANDLE__ specifies the HASH handle.
+  * @param  __INTERRUPT__ specifies the HASH interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_DISABLE_IT(__HANDLE__, __INTERRUPT__)   CLEAR_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__))
+
+/** @brief Reset HASH handle state.
+  * @param  __HANDLE__ HASH handle.
+  * @retval None
+  */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;      \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                     }while(0)
+#else
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the multi-buffer DMA transfer mode.
+  * @note   This bit is set when hashing large files when multiple DMA transfers are needed.
+  * @retval None
+  */
+#define __HAL_HASH_SET_MDMAT()          SET_BIT(HASH->CR, HASH_CR_MDMAT)
+
+/**
+  * @brief  Disable the multi-buffer DMA transfer mode.
+  * @retval None
+  */
+#define __HAL_HASH_RESET_MDMAT()        CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
+
+/**
+  * @brief  HAL HASH driver version.
+  * @retval None
+  */
+#define HAL_HASH_VERSION       200  /*!< HAL HASH driver version 2.0.0*/
+
+/**
+  * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions
+  * @{
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+                                            pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash);
+void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                 uint8_t *const pOutBuffer,
+                                 uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const  uint8_t *const pInBuffer, uint32_t Size,
+                                    uint8_t  *const pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint8_t  *const pOutBuffer);
+
+HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *const pOutBuffer,
+                                          uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *const pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group3 HMAC processing functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint8_t  *const pOutBuffer,
+                                      uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *const pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                         uint8_t *const pOutBuffer);
+
+HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                               uint8_t *const pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                  uint32_t Size, uint8_t *const pOutBuffer);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HASH_Exported_Functions_Group4 HASH IRQ handler management
+  * @{
+  */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
+uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros   HASH Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Return digest length in bytes.
+  * @retval Digest length
+  */
+#define HASH_DIGEST_LENGTH(__HANDLE__) (((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
+                                          == HASH_ALGOSELECTION_SHA1) ?  20U : \
+                                         ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
+                                           == HASH_ALGOSELECTION_SHA224) ?  28U : \
+                                          ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
+                                            == HASH_ALGOSELECTION_SHA256) ?  32U : \
+                                           ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
+                                             == HASH_ALGOSELECTION_SHA384) ?  48U : \
+                                            ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
+                                              == HASH_ALGOSELECTION_SHA512_224) ?  28U : \
+                                             ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
+                                               == HASH_ALGOSELECTION_SHA512_256) ?  32U : \
+                                              ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \
+                                                == HASH_ALGOSELECTION_SHA512) ?  64U : 20U ) ) ))))))
+
+/**
+  * @brief Ensure that HASH input data type is valid.
+  * @param __DATATYPE__ HASH input data type.
+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+  */
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_NO_SWAP)|| \
+                                        ((__DATATYPE__) == HASH_HALFWORD_SWAP)|| \
+                                        ((__DATATYPE__) == HASH_BYTE_SWAP) || \
+                                        ((__DATATYPE__) == HASH_BIT_SWAP))
+
+/**
+  * @brief Ensure that HASH input algorithm is valid.
+  * @param __ALGORITHM__ HASH algorithm.
+  * @retval SET (__ALGORITHM__ is valid) or RESET (__ALGORITHM__ is invalid)
+  */
+#define IS_HASH_ALGORITHM(__ALGORITHM__) (((__ALGORITHM__) == HASH_ALGOSELECTION_SHA1)|| \
+                                          ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA224)|| \
+                                          ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA256)|| \
+                                          ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA384)|| \
+                                          ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_224)|| \
+                                          ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512_256)|| \
+                                          ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA512))
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Constants HASH Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup HASH_Private_Defines HASH Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HASH_Private_Variables HASH Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private functions -----------------------------------------------------------*/
+
+/** @addtogroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /*  HASH*/
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_HASH_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_hcd.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_hcd.h
new file mode 100644
index 000000000..681107083
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_hcd.h
@@ -0,0 +1,327 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_hcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of HCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_HCD_H
+#define STM32N6xx_HAL_HCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_usb.h"
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HCD HCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Types HCD Exported Types
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_HCD_STATE_RESET    = 0x00,
+  HAL_HCD_STATE_READY    = 0x01,
+  HAL_HCD_STATE_ERROR    = 0x02,
+  HAL_HCD_STATE_BUSY     = 0x03,
+  HAL_HCD_STATE_TIMEOUT  = 0x04
+} HCD_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
+typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+  * @{
+  */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+typedef struct __HCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+{
+  HCD_TypeDef               *Instance;  /*!< Register base address    */
+  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
+  HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */
+  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
+  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
+  __IO  uint32_t            ErrorCode;  /*!< HCD Error code           */
+  void                      *pData;     /*!< Pointer Stack Handler    */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd);                               /*!< USB OTG HCD SOF callback                */
+  void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Connect callback            */
+  void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd);                        /*!< USB OTG HCD Disconnect callback         */
+  void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd);                       /*!< USB OTG HCD Port Enable callback        */
+  void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd);                      /*!< USB OTG HCD Port Disable callback       */
+  void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
+                                      HCD_URBStateTypeDef urb_state);                   /*!< USB OTG HCD Host Channel Notify URB Change callback  */
+
+  void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd);                         /*!< USB OTG HCD Msp DeInit callback         */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+} HCD_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Constants HCD Exported Constants
+  * @{
+  */
+
+/** @defgroup HCD_Speed HCD Speed
+  * @{
+  */
+#define HCD_SPEED_HIGH               USBH_HS_SPEED
+#define HCD_SPEED_FULL               USBH_FSLS_SPEED
+#define HCD_SPEED_LOW                USBH_FSLS_SPEED
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Device_Speed HCD Device Speed
+  * @{
+  */
+#define HCD_DEVICE_SPEED_HIGH               0U
+#define HCD_DEVICE_SPEED_FULL               1U
+#define HCD_DEVICE_SPEED_LOW                2U
+/**
+  * @}
+  */
+
+/** @defgroup HCD_PHY_Module HCD PHY Module
+  * @{
+  */
+#define HCD_PHY_ULPI                 1U
+#define HCD_PHY_EMBEDDED             2U
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Error_Code_definition HCD Error Code definition
+  * @brief  HCD Error Code definition
+  * @{
+  */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_HCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HCD_Exported_Macros HCD Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+#define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+                                                             & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
+  ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_SET_HC_CSPLT(chnum)                 (USBx_HC(chnum)->HCSPLT   |= USB_OTG_HCSPLT_COMPLSPLT)
+#define __HAL_HCD_CLEAR_HC_CSPLT(chnum)               (USBx_HC(chnum)->HCSPLT   &= ~USB_OTG_HCSPLT_COMPLSPLT)
+#define __HAL_HCD_CLEAR_HC_SSPLT(chnum)               (USBx_HC(chnum)->HCSPLT   &= ~USB_OTG_HCSPLT_SPLITEN)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HCD_Exported_Functions HCD Exported Functions
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                  uint8_t epnum, uint8_t dev_address,
+                                  uint8_t speed, uint8_t ep_type, uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void              HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void              HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
+  * @brief  HAL USB OTG HCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_HCD_SOF_CB_ID            = 0x01,       /*!< USB HCD SOF callback ID           */
+  HAL_HCD_CONNECT_CB_ID        = 0x02,       /*!< USB HCD Connect callback ID       */
+  HAL_HCD_DISCONNECT_CB_ID     = 0x03,       /*!< USB HCD Disconnect callback ID    */
+  HAL_HCD_PORT_ENABLED_CB_ID   = 0x04,       /*!< USB HCD Port Enable callback ID   */
+  HAL_HCD_PORT_DISABLED_CB_ID  = 0x05,       /*!< USB HCD Port Disable callback ID  */
+
+  HAL_HCD_MSPINIT_CB_ID        = 0x06,       /*!< USB HCD MspInit callback ID       */
+  HAL_HCD_MSPDEINIT_CB_ID      = 0x07        /*!< USB HCD MspDeInit callback ID     */
+
+} HAL_HCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
+  * @brief  HAL USB OTG HCD Callback pointer definition
+  * @{
+  */
+
+typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd);                   /*!< pointer to a common USB OTG HCD callback function  */
+typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
+                                                       uint8_t epnum,
+                                                       HCD_URBStateTypeDef urb_state);   /*!< pointer to USB OTG HCD host channel  callback */
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+                                           HAL_HCD_CallbackIDTypeDef CallbackID,
+                                           pHCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
+                                             HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+                                                             pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                           uint8_t direction, uint8_t ep_type,
+                                           uint8_t token, uint8_t *pbuff,
+                                           uint16_t length, uint8_t do_ping);
+
+HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                        uint8_t addr, uint8_t PortNbr);
+
+HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
+                                         HCD_URBStateTypeDef urb_state);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HCD_Private_Macros HCD Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private functions prototypes ----------------------------------------------*/
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_HCD_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2c.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2c.h
new file mode 100644
index 000000000..cc3883b74
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2c.h
@@ -0,0 +1,842 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_I2C_H
+#define STM32N6xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                     This parameter calculated by referring to I2C initialization section
+                                     in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                     This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                     This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                     This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                     This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
+                                     mode is selected.
+                                     This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                     This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                     This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+  /*!< I2C transfer IRQ handler function pointer */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+  __IO uint32_t              Devaddress;     /*!< I2C Target device address                 */
+
+  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
+/*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
+                                          uint16_t AddrMatchCode);
+/*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & \
+                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
+                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32n6xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+                                           pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+                                        uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                            uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                               uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                              uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                  uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                 uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions);
+#endif /*HAL_DMA_MODULE_ENABLED*/
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
+                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
+                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
+                                                                          I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
+                                                              >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
+                                                             >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+                                                                         (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+                                                                (~I2C_CR2_RD_WRN)) : \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+                                                                 (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+                                                    ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32n6xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_I2C_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2c_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2c_ex.h
new file mode 100644
index 000000000..3522fa415
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2c_ex.h
@@ -0,0 +1,156 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_I2C_EX_H
+#define STM32N6xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FASTMODEPLUS_ENABLE         0x00000000U           /*!< Enable Fast Mode Plus                        */
+#define I2C_FASTMODEPLUS_DISABLE        0x00000001U           /*!< Disable Fast Mode Plus                       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+  * @}
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                         ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE))   || \
+                                         ((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE)))
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32n6xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_I2C_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2s.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2s.h
new file mode 100644
index 000000000..bf4306232
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2s.h
@@ -0,0 +1,663 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2s.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2S HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_I2S_H
+#define STM32N6xx_HAL_I2S_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2S
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+  * @{
+  */
+
+/**
+  * @brief I2S Init structure definition
+  */
+typedef struct
+{
+  uint32_t Mode;                /*!< Specifies the I2S operating mode.
+                                     This parameter can be a value of @ref I2S_Mode */
+
+  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
+                                     This parameter can be a value of @ref I2S_Standard */
+
+  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
+                                     This parameter can be a value of @ref I2S_Data_Format */
+
+  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                     This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
+                                     This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
+                                     This parameter can be a value of @ref I2S_Clock_Polarity */
+
+  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                     This parameter can be a value of @ref I2S_MSB_LSB_Transmission       */
+
+  uint32_t WSInversion;         /*!< Control the Word Select Inversion.
+                                     This parameter can be a value of @ref I2S_WSInversion                */
+
+  uint32_t Data24BitAlignment;  /*!< Specifies the Data Padding for 24 bits data length
+                                      This parameter can be a value of @ref I2S_Data_24Bit_Alignment       */
+
+  uint32_t MasterKeepIOState;   /*!< Control of Alternate function GPIOs state
+                                     This parameter can be a value of @ref I2S_Master_Keep_IO_State */
+
+} I2S_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_I2S_STATE_RESET      = 0x00UL,  /*!< I2S not yet initialized or disabled                */
+  HAL_I2S_STATE_READY      = 0x01UL,  /*!< I2S initialized and ready for use                  */
+  HAL_I2S_STATE_BUSY       = 0x02UL,  /*!< I2S internal process is ongoing                    */
+  HAL_I2S_STATE_BUSY_TX    = 0x03UL,  /*!< Data Transmission process is ongoing               */
+  HAL_I2S_STATE_BUSY_RX    = 0x04UL,  /*!< Data Reception process is ongoing                  */
+  HAL_I2S_STATE_BUSY_TX_RX = 0x05UL,  /*!< Data Transmission and Reception process is ongoing */
+  HAL_I2S_STATE_TIMEOUT    = 0x06UL,  /*!< I2S timeout state                                  */
+  HAL_I2S_STATE_ERROR      = 0x07UL   /*!< I2S error state                                    */
+} HAL_I2S_StateTypeDef;
+
+/**
+  * @brief I2S handle Structure definition
+  */
+typedef struct __I2S_HandleTypeDef
+{
+  SPI_TypeDef                *Instance;            /*!< I2S registers base address */
+
+  I2S_InitTypeDef            Init;                 /*!< I2S communication parameters */
+
+  const uint16_t             *pTxBuffPtr;          /*!< Pointer to I2S Tx transfer buffer */
+
+  __IO uint16_t              TxXferSize;           /*!< I2S Tx transfer size */
+
+  __IO uint16_t              TxXferCount;          /*!< I2S Tx transfer Counter */
+
+  uint16_t                   *pRxBuffPtr;          /*!< Pointer to I2S Rx transfer buffer */
+
+  __IO uint16_t              RxXferSize;           /*!< I2S Rx transfer size */
+
+  __IO uint16_t              RxXferCount;          /*!< I2S Rx transfer counter
+                                                      (This field is initialized at the
+                                                       same value as transfer size at the
+                                                       beginning of the transfer and
+                                                       decremented when a sample is received
+                                                       NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+  void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
+
+  void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
+
+  DMA_HandleTypeDef          *hdmatx;              /*!< I2S Tx DMA handle parameters */
+
+  DMA_HandleTypeDef          *hdmarx;              /*!< I2S Rx DMA handle parameters */
+
+  __IO HAL_LockTypeDef       Lock;                 /*!< I2S locking object */
+
+  __IO HAL_I2S_StateTypeDef  State;                /*!< I2S communication state */
+
+  __IO uint32_t              ErrorCode;            /*!< I2S Error code
+                                                        This parameter can be a value of @ref I2S_Error */
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
+  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
+  void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);           /*!< I2S TxRx Completed callback        */
+  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
+  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
+  void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);       /*!< I2S TxRx Half Completed callback   */
+  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
+  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
+  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
+
+#endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
+} I2S_HandleTypeDef;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+/**
+
+  * @brief  HAL I2S Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2S_TX_COMPLETE_CB_ID             = 0x00UL,    /*!< I2S Tx Completed callback ID         */
+  HAL_I2S_RX_COMPLETE_CB_ID             = 0x01UL,    /*!< I2S Rx Completed callback ID         */
+  HAL_I2S_TX_RX_COMPLETE_CB_ID          = 0x02UL,    /*!< I2S TxRx Completed callback ID       */
+  HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03UL,    /*!< I2S Tx Half Completed callback ID    */
+  HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04UL,    /*!< I2S Rx Half Completed callback ID    */
+  HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID     = 0x05UL,    /*!< I2S TxRx Half Completed callback ID  */
+  HAL_I2S_ERROR_CB_ID                   = 0x06UL,    /*!< I2S Error callback ID                */
+  HAL_I2S_MSPINIT_CB_ID                 = 0x07UL,    /*!< I2S Msp Init callback ID             */
+  HAL_I2S_MSPDEINIT_CB_ID               = 0x08UL     /*!< I2S Msp DeInit callback ID           */
+
+} HAL_I2S_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2S Callback pointer definition
+  */
+typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
+
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+  * @{
+  */
+/** @defgroup I2S_Error I2S Error
+  * @{
+  */
+#define HAL_I2S_ERROR_NONE               (0x00000000UL)  /*!< No error                          */
+#define HAL_I2S_ERROR_TIMEOUT            (0x00000001UL)  /*!< Timeout error                     */
+#define HAL_I2S_ERROR_OVR                (0x00000002UL)  /*!< OVR error                         */
+#define HAL_I2S_ERROR_UDR                (0x00000004UL)  /*!< UDR error                         */
+#define HAL_I2S_ERROR_DMA                (0x00000008UL)  /*!< DMA transfer error                */
+#define HAL_I2S_ERROR_PRESCALER          (0x00000010UL)  /*!< Prescaler Calculation error       */
+#define HAL_I2S_ERROR_FRE                (0x00000020UL)  /*!< FRE error                         */
+#define HAL_I2S_ERROR_NO_OGT             (0x00000040UL)  /*!< No On Going Transfer error        */
+#define HAL_I2S_ERROR_NOT_SUPPORTED      (0x00000080UL)  /*!< Requested operation not supported */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000100UL)  /*!< Invalid Callback error      */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Mode I2S Mode
+  * @{
+  */
+#define I2S_MODE_SLAVE_TX                (0x00000000UL)
+#define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX               (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_SLAVE_FULLDUPLEX        (SPI_I2SCFGR_I2SCFG_2)
+#define I2S_MODE_MASTER_FULLDUPLEX       (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Standard I2S Standard
+  * @{
+  */
+#define I2S_STANDARD_PHILIPS             (0x00000000UL)
+#define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_LONG            (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_Format I2S Data Format
+  * @{
+  */
+#define I2S_DATAFORMAT_16B               (0x00000000UL)
+#define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B               (SPI_I2SCFGR_DATLEN_0)
+#define I2S_DATAFORMAT_32B               (SPI_I2SCFGR_DATLEN_1)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+  * @{
+  */
+#define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SCFGR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE           (0x00000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+  * @{
+  */
+#define I2S_AUDIOFREQ_192K               (192000UL)
+#define I2S_AUDIOFREQ_96K                (96000UL)
+#define I2S_AUDIOFREQ_48K                (48000UL)
+#define I2S_AUDIOFREQ_44K                (44100UL)
+#define I2S_AUDIOFREQ_32K                (32000UL)
+#define I2S_AUDIOFREQ_22K                (22050UL)
+#define I2S_AUDIOFREQ_16K                (16000UL)
+#define I2S_AUDIOFREQ_11K                (11025UL)
+#define I2S_AUDIOFREQ_8K                 (8000UL)
+#define I2S_AUDIOFREQ_DEFAULT            (2UL)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Clock_Polarity I2S FullDuplex Mode
+  * @{
+  */
+#define I2S_CPOL_LOW                     (0x00000000UL)
+#define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission
+  * @{
+  */
+#define I2S_FIRSTBIT_MSB                 (0x00000000UL)
+#define I2S_FIRSTBIT_LSB                 SPI_CFG2_LSBFRST
+/**
+  * @}
+  */
+
+/** @defgroup I2S_WSInversion I2S Word Select Inversion
+  * @{
+  */
+#define I2S_WS_INVERSION_DISABLE         (0x00000000UL)
+#define I2S_WS_INVERSION_ENABLE          SPI_I2SCFGR_WSINV
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
+  * @{
+  */
+#define I2S_DATA_24BIT_ALIGNMENT_RIGHT   (0x00000000UL)
+#define I2S_DATA_24BIT_ALIGNMENT_LEFT    SPI_I2SCFGR_DATFMT
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Master_Keep_IO_State Keep IO State
+  * @{
+  */
+#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
+#define I2S_MASTER_KEEP_IO_STATE_ENABLE  SPI_CFG2_AFCNTR
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
+  * @{
+  */
+#define I2S_IT_RXP                       SPI_IER_RXPIE
+#define I2S_IT_TXP                       SPI_IER_TXPIE
+#define I2S_IT_DXP                       SPI_IER_DXPIE
+#define I2S_IT_UDR                       SPI_IER_UDRIE
+#define I2S_IT_OVR                       SPI_IER_OVRIE
+#define I2S_IT_FRE                       SPI_IER_TIFREIE
+#define I2S_IT_ERR                       (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Flags_Definition I2S Flags Definition
+  * @{
+  */
+#define I2S_FLAG_RXP                     SPI_SR_RXP       /* I2S status flag : Rx-Packet available flag              */
+#define I2S_FLAG_TXP                     SPI_SR_TXP       /* I2S status flag : Tx-Packet space available flag        */
+#define I2S_FLAG_DXP                     SPI_SR_DXP       /* I2S status flag : Dx-Packet space available flag        */
+#define I2S_FLAG_UDR                     SPI_SR_UDR       /* I2S Error flag  : Underrun flag                         */
+#define I2S_FLAG_OVR                     SPI_SR_OVR       /* I2S Error flag  : Overrun flag                          */
+#define I2S_FLAG_FRE                     SPI_SR_TIFRE     /* I2S Error flag  : TI mode frame format error flag       */
+
+#define I2S_FLAG_MASK                    (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2S_Exported_macros I2S Exported Macros
+  * @{
+  */
+
+/** @brief  Reset I2S handle state
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
+                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
+
+/** @brief  Disable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
+
+/** @brief  Enable the specified I2S interrupts.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  *        This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt
+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
+  *            @arg I2S_IT_UDR : Underrun interrupt
+  *            @arg I2S_IT_OVR : Overrun interrupt
+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt
+  *            @arg I2S_IT_ERR : Error interrupt enable
+  * @retval None
+  */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2S interrupts.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt
+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
+  *            @arg I2S_IT_UDR : Underrun interrupt
+  *            @arg I2S_IT_OVR : Overrun interrupt
+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt
+  *            @arg I2S_IT_ERR : Error interrupt enable
+  * @retval None
+  */
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief  Check if the specified I2S interrupt source is enabled or disabled.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
+  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt
+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
+  *            @arg I2S_IT_DXP : Tx-Packet space available interrupt
+  *            @arg I2S_IT_UDR : Underrun interrupt
+  *            @arg I2S_IT_OVR : Overrun interrupt
+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt
+  *            @arg I2S_IT_ERR : Error interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2S flag is set or not.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_FLAG_RXP : Rx-Packet available flag
+  *            @arg I2S_FLAG_TXP : Tx-Packet space available flag
+  *            @arg I2S_FLAG_UDR : Underrun flag
+  *            @arg I2S_FLAG_OVR : Overrun flag
+  *            @arg I2S_FLAG_FRE : TI mode frame format error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the I2S OVR pending flag.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
+
+/** @brief Clear the I2S UDR pending flag.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
+
+/** @brief  Clear the I2S FRE pending flag.
+  * @param  __HANDLE__: specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2S_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+                                           pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions  ***************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
+                                            uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
+                                               uint16_t Size);
+
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
+                                                uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+  * @}
+  */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control and State functions  ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Constants I2S Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2S.c file */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+  * @{
+  */
+
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __SR__  copy of I2S SR register.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_FLAG_RXP : Rx-Packet available flag
+  *            @arg I2S_FLAG_TXP : Tx-Packet space available flag
+  *            @arg I2S_FLAG_UDR : Underrun flag
+  *            @arg I2S_FLAG_OVR : Overrun flag
+  *            @arg I2S_FLAG_FRE : TI mode frame format error flag
+  * @retval SET or RESET.
+  */
+#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
+                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\
+                                                  ? SET : RESET)
+
+/** @brief  Check whether the specified SPI Interrupt is set or not.
+  * @param  __IER__  copy of I2S IER register.
+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt
+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt
+  *            @arg I2S_IT_UDR : Underrun interrupt
+  *            @arg I2S_IT_OVR : Overrun interrupt
+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt
+  *            @arg I2S_IT_ERR : Error interrupt enable
+  * @retval SET or RESET.
+  */
+#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__)      ((((__IER__)\
+                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks if I2S Mode parameter is in allowed range.
+  * @param  __MODE__ specifies the I2S Mode.
+  *         This parameter can be a value of @ref I2S_Mode
+  * @retval None
+  */
+#define IS_I2S_MODE(__MODE__)                       (((__MODE__) == I2S_MODE_SLAVE_TX)                   || \
+                                                     ((__MODE__) == I2S_MODE_SLAVE_RX)                   || \
+                                                     ((__MODE__) == I2S_MODE_MASTER_TX)                  || \
+                                                     ((__MODE__) == I2S_MODE_MASTER_RX)                  || \
+                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)           || \
+                                                     ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
+
+#define IS_I2S_MASTER(__MODE__)                     (((__MODE__) == I2S_MODE_MASTER_TX)                  || \
+                                                     ((__MODE__) == I2S_MODE_MASTER_RX)                  || \
+                                                     ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
+
+#define IS_I2S_SLAVE(__MODE__)                      (((__MODE__) == I2S_MODE_SLAVE_TX)                  || \
+                                                     ((__MODE__) == I2S_MODE_SLAVE_RX)                  || \
+                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
+
+#define IS_I2S_FULLDUPLEX(__MODE__)                 (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX)         || \
+                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
+
+#define IS_I2S_STANDARD(__STANDARD__)               (((__STANDARD__) == I2S_STANDARD_PHILIPS)            || \
+                                                     ((__STANDARD__) == I2S_STANDARD_MSB)                || \
+                                                     ((__STANDARD__) == I2S_STANDARD_LSB)                || \
+                                                     ((__STANDARD__) == I2S_STANDARD_PCM_SHORT)          || \
+                                                     ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(__FORMAT__)              (((__FORMAT__) == I2S_DATAFORMAT_16B)                || \
+                                                     ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED)       || \
+                                                     ((__FORMAT__) == I2S_DATAFORMAT_24B)                || \
+                                                     ((__FORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__OUTPUT__)              (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE)             || \
+                                                     ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(__FREQ__)                ((((__FREQ__) >= I2S_AUDIOFREQ_8K)                    && \
+                                                     ((__FREQ__) <= I2S_AUDIOFREQ_192K))                 || \
+                                                    ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_I2S_CPOL(__CPOL__)                       (((__CPOL__) == I2S_CPOL_LOW)                        || \
+                                                     ((__CPOL__) == I2S_CPOL_HIGH))
+
+#define IS_I2S_FIRST_BIT(__BIT__)                   (((__BIT__) == I2S_FIRSTBIT_MSB)                     || \
+                                                     ((__BIT__) == I2S_FIRSTBIT_LSB))
+
+#define IS_I2S_WS_INVERSION(__WSINV__)              (((__WSINV__) == I2S_WS_INVERSION_DISABLE)           || \
+                                                     ((__WSINV__) == I2S_WS_INVERSION_ENABLE))
+
+#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__)  (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
+                                                     ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
+
+#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__)     (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE)  || \
+                                                     ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_I2S_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2s_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2s_ex.h
new file mode 100644
index 000000000..40970e4dc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i2s_ex.h
@@ -0,0 +1,26 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2s_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2S HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/**
+  ******************************************************************************
+                      ===== I2S FULL DUPLEX FEATURE =====
+       I2S Full Duplex APIs are available in stm32n6xx_hal_i2s.c/.h
+  ******************************************************************************
+  */
+
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i3c.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i3c.h
new file mode 100644
index 000000000..54f7b0f6a
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_i3c.h
@@ -0,0 +1,1397 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_i3c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I3C HAL module.
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32N6xx_HAL_I3C_H
+#define STM32N6xx_HAL_I3C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+#include "stm32n6xx_ll_i3c.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I3C
+  * @{
+  */
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Exported_Types I3C Exported Types
+  * @{
+  */
+/** @defgroup I3C_Init_Structure_definition I3C Init Structure definition
+  * @brief    I3C Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration
+                                                        when Controller mode                                          */
+
+  LL_I3C_TgtBusConfTypeDef  TgtBusCharacteristic;  /*!< Specifies the I3C target bus characteristic configuration
+                                                        when Target mode                                              */
+
+} I3C_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_FIFO_Config_Structure_definition I3C FIFO Configuration Structure definition
+  * @brief    I3C FIFO configuration structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t RxFifoThreshold; /*!< Specifies the I3C Rx FIFO threshold level.
+                                 This parameter must be a value of @ref I3C_RX_FIFO_THRESHOLD                         */
+
+  uint32_t TxFifoThreshold; /*!< Specifies the I3C Tx FIFO threshold level.
+                                 This parameter must be a value of @ref I3C_TX_FIFO_THRESHOLD                         */
+
+  uint32_t ControlFifo;     /*!< Specifies the I3C control FIFO enable/disable state.
+                                 This parameter is configured only with controller mode and it
+                                 must be a value of @ref I3C_CONTROL_FIFO_STATE                                       */
+
+  uint32_t StatusFifo;      /*!< Specifies the I3C status FIFO enable/disable state.
+                                 This parameter is configured only with controller mode and it
+                                 must be a value of @ref I3C_STATUS_FIFO_STATE                                        */
+} I3C_FifoConfTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Controller_Config_Structure_definition I3C Controller Configuration Structure definition
+  * @brief    I3C controller configuration structure definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t DynamicAddr;            /*!< Specifies the dynamic address of the controller when goes in target mode.
+                                       This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F        */
+
+  uint8_t StallTime;              /*!< Specifies the controller clock stall time in number of kernel clock cycles.
+                                       This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF        */
+
+  FunctionalState HotJoinAllowed; /*!< Specifies the Enable/Disable state of the controller Hot Join acknowledgement
+                                       when receiving a hot join request from target.
+                                       This parameter can be set to ENABLE or DISABLE                                 */
+
+  FunctionalState ACKStallState;  /*!< Specifies the Enable/Disable state of the controller clock stall
+                                       on the ACK phase.
+                                       This parameter can be set to ENABLE or DISABLE                                 */
+
+  FunctionalState CCCStallState;  /*!< Specifies the Enable/Disable state of the controller clock stall on the
+                                       T bit phase of a CCC communication to allow the target to decode command.
+                                       This parameter can be set to ENABLE or DISABLE                                 */
+
+  FunctionalState TxStallState;   /*!< Specifies the Enable/Disable state of the controller clock stall on
+                                       parity phase of data to allow the target to read received data.
+                                       This parameter can be set to ENABLE or DISABLE                                 */
+
+  FunctionalState RxStallState;   /*!< Specifies the Enable/Disable state of the controller clock stall on the T bit
+                                       phase of data enable to allow the target to prepare data to be sent.
+                                       This parameter can be set to ENABLE or DISABLE                                 */
+
+  FunctionalState HighKeeperSDA;  /*!< Specifies the Enable/Disable state of the controller SDA high keeper.
+                                       This parameter can be set to ENABLE or DISABLE                                 */
+} I3C_CtrlConfTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Target_Config_Structure_definition I3C Target Configuration Structure definition
+  * @brief    I3C target configuration structure definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t Identifier;                  /*!< Specifies the target characteristic ID (MIPI named reference DCR).
+                                            This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF   */
+
+  uint8_t MIPIIdentifier;              /*!< Specifies the bits [12-15] of the 48-provisioned ID
+                                            (MIPI named reference PID), other 48-provisioned ID are hardcoded.
+                                            This parameter must be a number between Min_Data=0x00 and Max_Data=0x0F   */
+
+  FunctionalState CtrlRoleRequest;     /*!< Specifies the Enable/Disable state of the target authorization request
+                                            for a second master Chip.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  FunctionalState HotJoinRequest;      /*!< Specifies the Enable/Disable state of the target hot join
+                                            authorization request.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  FunctionalState IBIRequest;          /*!< Specifies the Enable/Disable state of the target in Band Interrupt
+                                            authorization request.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  FunctionalState IBIPayload;          /*!< Specifies the Enable/Disable state of sending data payload after
+                                            an accepted IBI.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  uint32_t IBIPayloadSize;             /*!< Specifies the I3C target payload data size.
+                                            This parameter must be a value of @ref I3C_PAYLOAD_SIZE                   */
+
+  uint16_t MaxReadDataSize;            /*!< Specifies the numbers of data bytes that the target can read at maximum.
+                                            This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */
+
+  uint16_t MaxWriteDataSize;           /*!< Specifies the numbers of data bytes that the target can write at maximum.
+                                            This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */
+
+  FunctionalState CtrlCapability;      /*!< Specifies the Enable/Disable state of the target controller capability.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  FunctionalState GroupAddrCapability; /*!< Specifies the Enable/Disable state of the target support of group address
+                                            after a controller role hand-off.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  uint32_t DataTurnAroundDuration;     /*!< Specifies the I3C target clock-to-data turnaround time.
+                                            This parameter must be a value of @ref I3C_TURNAROUND_TIME_TSCO           */
+
+  uint8_t MaxReadTurnAround;           /*!< Specifies the target maximum read turnaround byte.
+                                            This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF   */
+
+  uint32_t MaxDataSpeed;               /*!< Specifies the I3C target returned GETMXDS CCC format.
+                                            This parameter must be a value of @ref I3C_GETMXDS_FORMAT                 */
+
+  FunctionalState MaxSpeedLimitation;  /*!< Specifies the Enable/Disable state of the target max data speed limitation.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  uint32_t HandOffActivityState;       /*!< Specifies the I3C target activity state when becoming controller.
+                                            This parameter must be a value of @ref I3C_HANDOFF_ACTIVITY_STATE         */
+
+  FunctionalState HandOffDelay;        /*!< Specifies the Enable/Disable state of the target need of delay to process
+                                            the controller role hand-off.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+
+  FunctionalState PendingReadMDB;      /*!< Specifies the Enable/Disable state of the transmission of a mandatory
+                                            data bytes indicating a pending read notification for GETCAPR CCC command.
+                                            This parameter can be set to ENABLE or DISABLE                            */
+} I3C_TgtConfTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Device_Config_Structure_definition I3C Device Configuration Structure definition
+  * @brief    I3C device configuration structure definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t         DeviceIndex;       /*!< Specifies the index value of the device in the DEVRx register.
+                                          This parameter must be a number between Min_Data=1 and Max_Data=4           */
+
+  uint8_t         TargetDynamicAddr; /*!< Specifies the dynamic address of the target x (1 to 4) connected on the bus.
+                                          This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F     */
+
+  FunctionalState IBIAck;            /*!< Specifies the Enable/Disable state of the controller's ACK when receiving
+                                          an IBI from a target x (1 to 4) connected on the bus.
+                                          This parameter can be set to ENABLE or DISABLE                              */
+
+  FunctionalState IBIPayload;        /*!< Specifies the Enable/Disable state of the controller's receiving IBI payload
+                                          after acknowledging an IBI requested from a target x (1 to 4) connected
+                                          on the bus.
+                                          This parameter can be set to ENABLE or DISABLE                              */
+
+  FunctionalState CtrlRoleReqAck;    /*!< Specifies the Enable/Disable state of the controller's ACK when receiving
+                                          a control request from a target x (1 to 4) connected on the bus.
+                                          This parameter can be set to ENABLE or DISABLE                              */
+
+  FunctionalState CtrlStopTransfer;  /*!< Specifies the Enable/Disable state of the controller's stop transfer after
+                                          receiving an IBI request from a target x (1 to 4) connected on the bus.
+                                          This parameter can be set to ENABLE or DISABLE                              */
+
+} I3C_DeviceConfTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_mode_structure_definition I3C mode structure definition
+  * @brief    I3C Mode structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_I3C_MODE_NONE       = 0x00U,  /*!< No I3C communication on going             */
+  HAL_I3C_MODE_CONTROLLER = 0x01U,  /*!< I3C communication is in controller Mode   */
+  HAL_I3C_MODE_TARGET     = 0x02U,  /*!< I3C communication is in target Mode       */
+
+} HAL_I3C_ModeTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief    HAL State structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_I3C_STATE_RESET       = 0x00U,   /*!< Peripheral is not yet Initialized                   */
+  HAL_I3C_STATE_READY       = 0x10U,   /*!< Peripheral Initialized and ready for use            */
+  HAL_I3C_STATE_BUSY        = 0x20U,   /*!< An internal process is ongoing                      */
+  HAL_I3C_STATE_BUSY_TX     = 0x21U,   /*!< Data Transmission process is ongoing                */
+  HAL_I3C_STATE_BUSY_RX     = 0x22U,   /*!< Data Reception process is ongoing                   */
+  HAL_I3C_STATE_BUSY_TX_RX  = 0x23U,   /*!< Data Multiple Transfer process is ongoing           */
+  HAL_I3C_STATE_BUSY_DAA    = 0x24U,   /*!< Dynamic address assignment process is ongoing       */
+  HAL_I3C_STATE_LISTEN      = 0x30U,   /*!< Listen process is ongoing                           */
+  HAL_I3C_STATE_ABORT       = 0x60U,   /*!< Abort user request ongoing                          */
+  HAL_I3C_STATE_ERROR       = 0xE0U,   /*!< Error                                               */
+
+} HAL_I3C_StateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_CCCInfoTypeDef_Structure_definition I3C CCCInfoTypeDef Structure definition
+  * @brief    I3C CCCInfoTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t DynamicAddrValid;    /*!< I3C target Dynamic Address Valid (updated during ENTDAA/RSTDAA/SETNEWDA CCC)
+                                     This parameter can be Valid=1U or Not Valid=0U                                   */
+  uint32_t DynamicAddr;         /*!< I3C target Dynamic Address (updated during ENTDAA/RSTDAA/SETNEWDA CCC)           */
+  uint32_t MaxWriteLength;      /*!< I3C target Maximum Write Length (updated during SETMWL CCC)                      */
+  uint32_t MaxReadLength;       /*!< I3C target Maximum Read Length (updated during SETMRL CCC)                       */
+  uint32_t ResetAction;         /*!< I3C target Reset Action level (updated during RSTACT CCC)                        */
+  uint32_t ActivityState;       /*!< I3C target Activity State (updated during ENTASx CCC)                            */
+  uint32_t HotJoinAllowed;      /*!< I3C target Hot Join (updated during ENEC/DISEC CCC)
+                                     This parameter can be Allowed=1U or Not Allowed=0U                               */
+  uint32_t InBandAllowed;       /*!< I3C target In Band Interrupt (updated during ENEC/DISEC CCC)
+                                     This parameter can be Allowed=1U or Not Allowed=0U                               */
+  uint32_t CtrlRoleAllowed;     /*!< I3C target Controller Role Request (updated during ENEC/DISEC CCC)
+                                     This parameter can be Allowed=1U or Not Allowed=0U                               */
+  uint32_t IBICRTgtAddr;        /*!< I3C controller receive Target Address during IBI or Controller Role Request event*/
+  uint32_t IBITgtNbPayload;     /*!< I3C controller get Number of Data Payload after an IBI event                     */
+  uint32_t IBITgtPayload;       /*!< I3C controller receive IBI Payload after an IBI event                            */
+
+} I3C_CCCInfoTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_ControlTypeDef_Structure_definition I3C ControlTypeDef Structure definition
+  * @brief    I3C ControlTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t *pBuffer;  /*!< Pointer to the buffer containing the control or status register values */
+  uint32_t  Size;     /*!< The size of pBuffer in words                                           */
+
+} I3C_ControlTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_DataTypeDef_Structure_definition I3C DataTypeDef Structure definition
+  * @brief    I3C DataTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t   *pBuffer;  /*!< Pointer to the buffer containing all data values to transfer */
+  uint32_t  Size;      /*!< The size of pBuffer in bytes                                 */
+
+} I3C_DataTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I3C_CCCTypeDef_Structure_definition I3C CCCTypeDef Structure definition
+  * @brief    I3C CCCTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t            TargetAddr; /*!< Dynamic or Static target Address                                      */
+  uint8_t            CCC;        /*!< CCC value code                                                        */
+  I3C_DataTypeDef    CCCBuf;     /*!< Contain size of associated data and size of defining byte if any.
+                                      Contain pointer to CCC associated data                                */
+  uint32_t           Direction;  /*!< CCC read and/or write direction message                               */
+
+} I3C_CCCTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_BCRTypeDef_Structure_definition I3C BCRTypeDef Structure definition
+  * @brief    I3C BCRTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  FunctionalState         MaxDataSpeedLimitation;  /*!< Max data speed limitation */
+  FunctionalState         IBIRequestCapable;       /*!< IBI request capable */
+  FunctionalState         IBIPayload;              /*!< IBI payload data */
+  FunctionalState         OfflineCapable;          /*!< Offline capable */
+  FunctionalState         VirtualTargetSupport;    /*!< Virtual target support */
+  FunctionalState         AdvancedCapabilities;    /*!< Advanced capabilities */
+  FunctionalState         DeviceRole;              /*!< Device role */
+
+} I3C_BCRTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_PIDTypeDef_Structure_definition I3C PIDTypeDef Structure definition
+  * @brief    I3C_PIDTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint16_t  MIPIMID;         /*!< MIPI Manufacturer ID */
+  uint8_t   IDTSEL;          /*!< Provisioned ID Type Selector */
+  uint16_t  PartID;          /*!< Part ID device vendor to define */
+  uint8_t   MIPIID;          /*!< Instance ID */
+
+} I3C_PIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_ENTDAAPayloadTypeDef_Structure_definition I3C ENTDAAPayloadTypeDef Structure definition
+  * @brief    I3C ENTDAAPayloadTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  I3C_BCRTypeDef   BCR;             /*!< Bus Characteristics Register */
+  uint32_t         DCR;             /*!< Device Characteristics Register */
+  I3C_PIDTypeDef   PID;             /*!< Provisioned ID */
+
+} I3C_ENTDAAPayloadTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_PrivateTypeDef_Structure_definition I3C PrivateTypeDef Structure definition
+  * @brief    I3C PrivateTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t            TargetAddr;  /*!< Dynamic or Static target Address                                 */
+  I3C_DataTypeDef    TxBuf;       /*!< Buffer structure containing the data to transmit (little endian) */
+  I3C_DataTypeDef    RxBuf;       /*!< Buffer structure containing the data to receive (little endian)  */
+  uint32_t           Direction;   /*!< Read and/or write message                                        */
+
+} I3C_PrivateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_XferTypeDef_Structure_definition I3C XferTypeDef Structure definition
+  * @brief    I3C XferTypeDef Structure definition
+  * @{
+  */
+typedef struct
+{
+  I3C_ControlTypeDef CtrlBuf;      /*!< Buffer structure containing the control register values  */
+  I3C_ControlTypeDef StatusBuf;    /*!< Buffer structure containing the status register values   */
+  I3C_DataTypeDef    TxBuf;        /*!< Buffer structure containing the data to transmit         */
+  I3C_DataTypeDef    RxBuf;        /*!< Buffer structure containing the data to receive          */
+
+} I3C_XferTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_handle_Structure_definition I3C handle Structure definition
+  * @brief    I3C handle Structure definition
+  * @{
+  */
+typedef struct __I3C_HandleTypeDef
+{
+  I3C_TypeDef                *Instance;                           /*!< I3C registers base address                */
+
+  I3C_InitTypeDef            Init;                                /*!< I3C communication parameters              */
+
+  HAL_I3C_ModeTypeDef        Mode;                                /*!< I3C communication mode.
+                                                                       This parameter must be a value of
+                                                                       @ref I3C_mode_structure_definition        */
+
+  I3C_XferTypeDef            *pXferData;                          /*!< I3C transfer buffers pointer              */
+
+  const I3C_CCCTypeDef       *pCCCDesc;                           /*!< I3C CCC descriptor pointer                */
+
+  const I3C_PrivateTypeDef   *pPrivateDesc;                       /*!< I3C private transfer descriptor pointer   */
+
+  uint32_t                   ControlXferCount;                    /*!< I3C counter indicating the remaining
+                                                                       control data bytes to write in
+                                                                       the control register                      */
+
+  uint32_t                   RxXferCount;                         /*!< I3C counter indicating the remaining
+                                                                       data bytes to receive                     */
+
+  uint32_t                   TxXferCount;                         /*!< I3C counter indicating the remaining
+                                                                       data bytes to transmit                    */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  DMA_HandleTypeDef          *hdmacr;                             /*!< I3C control DMA handle parameters         */
+
+  DMA_HandleTypeDef          *hdmatx;                             /*!< I3C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;                             /*!< I3C Rx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmasr;                             /*!< I3C status DMA handle parameters          */
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  HAL_LockTypeDef            Lock;                                /*!< I3C locking object                        */
+
+  __IO HAL_I3C_StateTypeDef  State;                               /*!< I3C communication state                   */
+
+  __IO HAL_I3C_StateTypeDef  PreviousState;                       /*!< I3C communication previous state          */
+
+  __IO uint32_t              ErrorCode;                           /*!< I3C Error code                            */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I3C_HandleTypeDef *hi3c,
+                              uint32_t itMasks);                  /*!< I3C transfer IRQ handler function pointer */
+
+  void(*ptrTxFunc)(struct __I3C_HandleTypeDef *hi3c);             /*!< I3C transmit function pointer             */
+
+  void(*ptrRxFunc)(struct __I3C_HandleTypeDef *hi3c);             /*!< I3C receive function pointer              */
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+
+  void (* CtrlTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Controller private data and CCC Tx Transfer complete callback                           */
+
+  void (* CtrlRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Controller private data and CCC Rx Transfer completed callback                          */
+
+  void (* CtrlMultipleXferCpltCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Controller multiple Direct CCC, I3C private or I2C Transfer completed callback          */
+
+  void (* CtrlDAACpltCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Controller Dynamic Address Assignment completed callback                                */
+
+  void (* TgtReqDynamicAddrCallback)(struct __I3C_HandleTypeDef *hi3c, uint64_t targetPayload);
+  /*!< I3C Controller request dynamic address callback during Dynamic Address Assignment processus */
+
+  void (* TgtTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Target private data Tx Transfer completed callback                                      */
+
+  void (* TgtRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Target private data Rx Transfer completed callback                                      */
+
+  void (* TgtHotJoinCallback)(struct __I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress);
+  /*!< I3C Target Hot-Join callback                                                                */
+
+  void (* NotifyCallback)(struct __I3C_HandleTypeDef *hi3c, uint32_t eventId);
+  /*!< I3C Target or Controller asynchronous events callback                                       */
+
+  void (* ErrorCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Error callback                                                                          */
+
+  void (* AbortCpltCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Abort complete callback                                                                 */
+
+  void (* MspInitCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Msp Init callback                                                                       */
+
+  void (* MspDeInitCallback)(struct __I3C_HandleTypeDef *hi3c);
+  /*!< I3C Msp DeInit callback                                                                     */
+
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+} I3C_HandleTypeDef;
+/**
+  * @}
+  */
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_I3C_Callback_ID_definition I3C callback ID definition
+  * @brief    HAL I3C callback ID definition
+  * @{
+  */
+typedef enum
+{
+  /*!< I3C Controller Tx Transfer completed callback ID                  */
+  HAL_I3C_CTRL_TX_COMPLETE_CB_ID               = 0x00U,
+  /*!< I3C Controller Rx Transfer completed callback ID                  */
+  HAL_I3C_CTRL_RX_COMPLETE_CB_ID               = 0x01U,
+  /*!< I3C Controller Multiple Transfer completed callback ID            */
+  HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID    = 0x02U,
+  /*!< I3C Controller Dynamic Address Assignment completed callback ID   */
+  HAL_I3C_CTRL_DAA_COMPLETE_CB_ID              = 0x03U,
+  /*!< I3C Controller request dynamic address completed callback ID      */
+  HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID           = 0x04U,
+  /*!< I3C Target Tx Transfer completed callback ID                      */
+  HAL_I3C_TGT_TX_COMPLETE_CB_ID                = 0x05U,
+  /*!< I3C Target Rx Transfer completed callback ID                      */
+  HAL_I3C_TGT_RX_COMPLETE_CB_ID                = 0x06U,
+  /*!< I3C Target Hot-join notification callback ID                      */
+  HAL_I3C_TGT_HOTJOIN_CB_ID                    = 0x07U,
+  /*!< I3C Target or Controller receive notification callback ID         */
+  HAL_I3C_NOTIFY_CB_ID                         = 0x08U,
+  /*!< I3C Error callback ID                                             */
+  HAL_I3C_ERROR_CB_ID                          = 0x09U,
+  /*!< I3C Abort callback ID                                             */
+  HAL_I3C_ABORT_CB_ID                          = 0x0AU,
+  /*!< I3C Msp Init callback ID                                          */
+  HAL_I3C_MSPINIT_CB_ID                        = 0x0BU,
+  /*!< I3C Msp DeInit callback ID                                        */
+  HAL_I3C_MSPDEINIT_CB_ID                      = 0x0CU
+
+} HAL_I3C_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I3C_Callback_Pointer_definition I3C callback Pointer definition
+  * @brief    HAL I3C callback pointer definition
+  * @{
+  */
+typedef  void (*pI3C_CallbackTypeDef)(I3C_HandleTypeDef *hi3c);
+typedef  void (*pI3C_NotifyCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint32_t notifyId);
+typedef  void (*pI3C_TgtHotJoinCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress);
+typedef  void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint64_t targetPayload);
+/**
+  * @}
+  */
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+/**
+  * @}
+  */
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Exported_Constants I3C Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_I3C_Notification_ID_definition I3C Notification ID definition
+  * @brief    HAL I3C Notification ID definition
+  * @{
+  */
+
+#define EVENT_ID_GETACCCR   (0x00000001U)
+/*!< I3C target complete controller-role hand-off (direct GETACCR CCC) event         */
+#define EVENT_ID_IBIEND     (0x00000002U)
+/*!< I3C target IBI end process event                                                */
+#define EVENT_ID_DAU        (0x00000004U)
+/*!< I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event  */
+#define EVENT_ID_GETx       (0x00000008U)
+/*!< I3C target receive any direct GETxxx CCC event                                  */
+#define EVENT_ID_GETSTATUS  (0x00000010U)
+/*!< I3C target receive get status command (direct GETSTATUS CCC) event              */
+#define EVENT_ID_SETMWL     (0x00000020U)
+/*!< I3C target receive maximum write length update (direct SETMWL CCC) event        */
+#define EVENT_ID_SETMRL     (0x00000040U)
+/*!< I3C target receive maximum read length update(direct SETMRL CCC) event          */
+#define EVENT_ID_RSTACT     (0x00000080U)
+/*!< I3C target detect reset pattern (broadcast or direct RSTACT CCC) event          */
+#define EVENT_ID_ENTASx     (0x00000100U)
+/*!< I3C target receive activity state update (direct or broadcast ENTASx) event     */
+#define EVENT_ID_ENEC_DISEC (0x00000200U)
+/*!< I3C target receive a direct or broadcast ENEC/DISEC CCC event                   */
+#define EVENT_ID_DEFTGTS    (0x00000400U)
+/*!< I3C target receive a broadcast DEFTGTS CCC event                                */
+#define EVENT_ID_DEFGRPA    (0x00000800U)
+/*!< I3C target receive a group addressing (broadcast DEFGRPA CCC) event             */
+#define EVENT_ID_WKP        (0x00001000U)
+/*!< I3C target wakeup event                                                         */
+#define EVENT_ID_IBI        (0x00002000U)
+/*!< I3C controller receive IBI event                                                */
+#define EVENT_ID_CR         (0x00004000U)
+/*!< I3C controller controller-role request event                                    */
+#define EVENT_ID_HJ         (0x00008000U)
+/*!< I3C controller hot-join event                                                   */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_OPTION_DEFINITION OPTION DEFINITION
+  * @note     HAL I3C option value coding follow below described bitmap:
+  *           b31
+  *                0  : message end type restart
+  *                1  : message end type stop
+  *           b30-b29-b28-b27
+  *                0010  : I3C private message
+  *                0011  : direct CCC message
+  *                0110  : broadcast CCC message
+  *                0100  : I2C private message
+  *           b4
+  *                0  : message without arbitration header
+  *                1  : message with arbitration header
+  *           b0
+  *                0  : message without defining byte
+  *                1  : message with defining byte
+  *
+  *           other bits (not used)
+  * @{
+  */
+#define I3C_DIRECT_WITH_DEFBYTE_RESTART       (0x18000001U) /*!< Restart between each Direct Command then Stop
+                                                                 request for last command.
+                                                                 Each Command have an associated defining byte        */
+#define I3C_DIRECT_WITH_DEFBYTE_STOP          (0x98000001U) /*!< Stop between each Direct Command.
+                                                                 Each Command have an associated defining byte        */
+#define I3C_DIRECT_WITHOUT_DEFBYTE_RESTART    (0x18000000U) /*!< Restart between each Direct Command then Stop
+                                                                 request for last command.
+                                                                 Each Command have not an associated defining byte    */
+#define I3C_DIRECT_WITHOUT_DEFBYTE_STOP       (0x98000000U) /*!< Stop between each Direct Command.
+                                                                 Each Command have not an associated defining byte    */
+#define I3C_BROADCAST_WITH_DEFBYTE_RESTART    (0x30000001U) /*!< Restart between each Broadcast Command then Stop
+                                                                 request for last command.
+                                                                 Each Command have an associated defining byte        */
+#define I3C_BROADCAST_WITH_DEFBYTE_STOP       (0xB0000001U) /*!< Stop between each Broadcast Command.
+                                                                 Each Command have an associated defining byte        */
+#define I3C_BROADCAST_WITHOUT_DEFBYTE_RESTART (0x30000000U) /*!< Restart between each Broadcast Command then Stop
+                                                                 request for last command.
+                                                                 Each Command have not an associated defining byte    */
+#define I3C_BROADCAST_WITHOUT_DEFBYTE_STOP    (0xB0000000U) /*!< Stop between each Broadcast Command.
+                                                                 Each Command have not an associated defining byte    */
+#define I3C_PRIVATE_WITH_ARB_RESTART          (0x10000000U) /*!< Restart between each I3C Private message then Stop
+                                                                 request for last message.
+                                                                 Each Message start with an arbitration header after
+                                                                 start bit condition                                  */
+#define I3C_PRIVATE_WITH_ARB_STOP             (0x90000000U) /*!< Stop between each I3C Private message.
+                                                                 Each Message start with an arbitration header after
+                                                                 start bit condition                                  */
+#define I3C_PRIVATE_WITHOUT_ARB_RESTART       (0x10000004U) /*!< Restart between each I3C message then Stop request
+                                                                 for last message.
+                                                                 Each Message start with Target address after start
+                                                                 bit condition                                        */
+#define I3C_PRIVATE_WITHOUT_ARB_STOP          (0x90000004U) /*!< Stop between each I3C Private message.
+                                                                 Each Message start with Target address after
+                                                                 start bit condition                                  */
+#define I2C_PRIVATE_WITH_ARB_RESTART          (0x20000000U) /*!< Restart between each I2C Private message then Stop
+                                                                 request for last message.
+                                                                 Each Message start with an arbitration header after
+                                                                 start bit condition                                  */
+#define I2C_PRIVATE_WITH_ARB_STOP             (0xA0000000U) /*!< Stop between each I2C Private message.
+                                                                 Each Message start with an arbitration header after
+                                                                 start bit condition                                  */
+#define I2C_PRIVATE_WITHOUT_ARB_RESTART       (0x20000004U) /*!< Restart between each I2C message then Stop request
+                                                                 for last message.
+                                                                 Each Message start with Target address after start
+                                                                 bit condition                                        */
+#define I2C_PRIVATE_WITHOUT_ARB_STOP          (0xA0000004U) /*!< Stop between each I2C Private message.
+                                                                 Each Message start with Target address after start
+                                                                 bit condition                                        */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION I3C DYNAMIC ADDRESS OPTION DEFINITION
+  * @{
+  */
+#define I3C_RSTDAA_THEN_ENTDAA  (0x00000001U) /*!< Initiate a RSTDAA before a ENTDAA procedure */
+#define I3C_ONLY_ENTDAA         (0x00000002U) /*!< Initiate a ENTDAA without RSTDAA            */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_ERROR_CODE_DEFINITION ERROR CODE DEFINITION
+  * @{
+  */
+#define HAL_I3C_ERROR_NONE (0x00000000U)                                /*!< No error                                 */
+
+#define HAL_I3C_ERROR_CE0  (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE0) /*!< Controller detected an illegally
+                                                                             formatted CCC                            */
+#define HAL_I3C_ERROR_CE1  (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE1) /*!< Controller detected that transmitted data
+                                                                             on the bus is different than expected    */
+#define HAL_I3C_ERROR_CE2  (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE2) /*!< Controller detected that broadcast address
+                                                                             7'h7E has been nacked                    */
+#define HAL_I3C_ERROR_CE3  (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE3) /*!< Controller detected that new Controller
+                                                                             did not drive the bus after
+                                                                             Controller-role handoff                  */
+#define HAL_I3C_ERROR_TE0  (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE0)     /*!< Target detected an invalid broadcast
+                                                                             address                                  */
+#define HAL_I3C_ERROR_TE1  (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE1)     /*!< Target detected an invalid CCC Code      */
+#define HAL_I3C_ERROR_TE2  (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE2)     /*!< Target detected a parity error during
+                                                                             a write data                             */
+#define HAL_I3C_ERROR_TE3  (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE3)     /*!< Target detected a parity error on assigned
+                                                                             address during dynamic address
+                                                                             arbitration                              */
+#define HAL_I3C_ERROR_TE4  (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE4)     /*!< Target detected 7'h7E missing after Restart
+                                                                             during Dynamic Address Assignment
+                                                                             procedure                                */
+#define HAL_I3C_ERROR_TE5  (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE5)     /*!< Target detected an illegally
+                                                                             formatted CCC                            */
+#define HAL_I3C_ERROR_TE6  (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE6)     /*!< Target detected that transmitted data on
+                                                                             the bus is different than expected       */
+#define HAL_I3C_ERROR_DATA_HAND_OFF (I3C_SER_DERR)  /*!< I3C data error during controller-role hand-off process       */
+#define HAL_I3C_ERROR_DATA_NACK     (I3C_SER_DNACK) /*!< I3C data not acknowledged error                              */
+#define HAL_I3C_ERROR_ADDRESS_NACK  (I3C_SER_ANACK) /*!< I3C address not acknowledged error                           */
+#define HAL_I3C_ERROR_COVR          (I3C_SER_COVR)  /*!< I3C S FIFO Over-Run or C FIFO Under-Run error                */
+#define HAL_I3C_ERROR_DOVR          (I3C_SER_DOVR)  /*!< I3C Rx FIFO Over-Run or Tx FIFO Under-Run error              */
+#define HAL_I3C_ERROR_STALL         (I3C_SER_STALL) /*!< I3C SCL stall error                                          */
+#define HAL_I3C_ERROR_DMA           (0x00010000U)   /*!< DMA transfer error                                           */
+#define HAL_I3C_ERROR_TIMEOUT       (0x00020000U)   /*!< Timeout error                                                */
+#define HAL_I3C_ERROR_DMA_PARAM     (0x00040000U)   /*!< DMA Parameter Error                                          */
+#define HAL_I3C_ERROR_INVALID_PARAM (0x00080000U)   /*!< Invalid Parameters error                                     */
+#define HAL_I3C_ERROR_SIZE          (0x00100000U)   /*!< I3C size management error                                    */
+#define HAL_I3C_ERROR_NOT_ALLOWED   (0x00200000U)   /*!< I3C operation is not allowed                                 */
+#define HAL_I3C_ERROR_DYNAMIC_ADDR  (0x00400000U)   /*!< I3C dynamic address error                                    */
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+#define HAL_I3C_ERROR_INVALID_CALLBACK (0x00800000U) /*!< Invalid Callback error                                      */
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_SDA_HOLD_TIME SDA HOLD TIME
+  * @{
+  */
+#define HAL_I3C_SDA_HOLD_TIME_0_5  LL_I3C_SDA_HOLD_TIME_0_5 /*!< SDA hold time equal to 0.5 x ti3cclk */
+#define HAL_I3C_SDA_HOLD_TIME_1_5  LL_I3C_SDA_HOLD_TIME_1_5 /*!< SDA hold time equal to 1.5 x ti3cclk */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_OWN_ACTIVITY_STATE OWN ACTIVITY STATE
+  * @{
+  */
+#define HAL_I3C_OWN_ACTIVITY_STATE_0  LL_I3C_OWN_ACTIVITY_STATE_0 /*!< Own Controller Activity state 0 */
+#define HAL_I3C_OWN_ACTIVITY_STATE_1  LL_I3C_OWN_ACTIVITY_STATE_1 /*!< Own Controller Activity state 1 */
+#define HAL_I3C_OWN_ACTIVITY_STATE_2  LL_I3C_OWN_ACTIVITY_STATE_2 /*!< Own Controller Activity state 2 */
+#define HAL_I3C_OWN_ACTIVITY_STATE_3  LL_I3C_OWN_ACTIVITY_STATE_3 /*!< Own Controller Activity state 3 */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_RX_FIFO_THRESHOLD RX FIFO THRESHOLD
+  * @{
+  */
+#define HAL_I3C_RXFIFO_THRESHOLD_1_4  LL_I3C_RXFIFO_THRESHOLD_1_4  /*!< Rx Fifo Threshold is 1 byte  */
+#define HAL_I3C_RXFIFO_THRESHOLD_4_4  LL_I3C_RXFIFO_THRESHOLD_4_4  /*!< Rx Fifo Threshold is 4 bytes */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_TX_FIFO_THRESHOLD TX FIFO THRESHOLD
+  * @{
+  */
+#define HAL_I3C_TXFIFO_THRESHOLD_1_4  LL_I3C_TXFIFO_THRESHOLD_1_4  /*!< Tx Fifo Threshold is 1 byte  */
+#define HAL_I3C_TXFIFO_THRESHOLD_4_4  LL_I3C_TXFIFO_THRESHOLD_4_4  /*!< Tx Fifo Threshold is 4 bytes */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_CONTROL_FIFO_STATE CONTROL FIFO STATE
+  * @{
+  */
+#define HAL_I3C_CONTROLFIFO_DISABLE  0x00000000U      /*!< Control FIFO mode disable */
+#define HAL_I3C_CONTROLFIFO_ENABLE   I3C_CFGR_TMODE   /*!< Control FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_STATUS_FIFO_STATE STATUS FIFO STATE
+  * @{
+  */
+#define HAL_I3C_STATUSFIFO_DISABLE  0x00000000U      /*!< Status FIFO mode disable */
+#define HAL_I3C_STATUSFIFO_ENABLE   I3C_CFGR_SMODE   /*!< Status FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_DIRECTION DIRECTION
+  * @{
+  */
+#define HAL_I3C_DIRECTION_WRITE     LL_I3C_DIRECTION_WRITE       /*!< Write transfer          */
+#define HAL_I3C_DIRECTION_READ      LL_I3C_DIRECTION_READ        /*!< Read transfer           */
+#define HAL_I3C_DIRECTION_BOTH      (LL_I3C_DIRECTION_READ | 1U) /*!< Read and Write transfer */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_PAYLOAD_SIZE PAYLOAD SIZE
+  * @{
+  */
+#define HAL_I3C_PAYLOAD_EMPTY    LL_I3C_PAYLOAD_EMPTY   /*!< Empty payload, no additional data after IBI acknowledge */
+#define HAL_I3C_PAYLOAD_1_BYTE   LL_I3C_PAYLOAD_1_BYTE  /*!< One additional data byte after IBI acknowledge          */
+#define HAL_I3C_PAYLOAD_2_BYTES  LL_I3C_PAYLOAD_2_BYTES /*!< Two additional data bytes after IBI acknowledge         */
+#define HAL_I3C_PAYLOAD_3_BYTES  LL_I3C_PAYLOAD_3_BYTES /*!< Three additional data bytes after IBI acknowledge       */
+#define HAL_I3C_PAYLOAD_4_BYTES  LL_I3C_PAYLOAD_4_BYTES /*!< Four additional data bytes after IBI acknowledge        */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE
+  * @{
+  */
+#define HAL_I3C_HANDOFF_ACTIVITY_STATE_0  LL_I3C_HANDOFF_ACTIVITY_STATE_0  /*!< Activity state 0 after handoff */
+#define HAL_I3C_HANDOFF_ACTIVITY_STATE_1  LL_I3C_HANDOFF_ACTIVITY_STATE_1  /*!< Activity state 1 after handoff */
+#define HAL_I3C_HANDOFF_ACTIVITY_STATE_2  LL_I3C_HANDOFF_ACTIVITY_STATE_2  /*!< Activity state 2 after handoff */
+#define HAL_I3C_HANDOFF_ACTIVITY_STATE_3  LL_I3C_HANDOFF_ACTIVITY_STATE_3  /*!< Activity state 3 after handoff */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_GETMXDS_FORMAT GETMXDS FORMAT
+  * @{
+  */
+#define HAL_I3C_GETMXDS_FORMAT_1     LL_I3C_GETMXDS_FORMAT_1      /*!< GETMXDS CCC Format 1 is used, no MaxRdTurn
+                                                                       field in response                              */
+#define HAL_I3C_GETMXDS_FORMAT_2_LSB LL_I3C_GETMXDS_FORMAT_2_LSB  /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field
+                                                                       in response, LSB = RDTURN[7:0]                 */
+#define HAL_I3C_GETMXDS_FORMAT_2_MID LL_I3C_GETMXDS_FORMAT_2_MID  /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field
+                                                                       in response, Middle byte = RDTURN[7:0]         */
+#define HAL_I3C_GETMXDS_FORMAT_2_MSB LL_I3C_GETMXDS_FORMAT_2_MSB  /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field
+                                                                       in response, MSB = RDTURN[7:0]                 */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_TURNAROUND_TIME_TSCO TURNAROUND TIME TSCO
+  * @{
+  */
+#define HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS    LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS
+/*!< clock-to-data turnaround time tSCO <= 12ns */
+#define HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS  LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS
+/*!< clock-to-data turnaround time tSCO > 12ns  */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_COMMON_INTERRUPT I3C COMMON INTERRUPT
+  * @{
+  */
+#define HAL_I3C_IT_TXFNFIE      LL_I3C_IER_TXFNFIE /*!< Tx FIFO not full interrupt enable      */
+#define HAL_I3C_IT_RXFNEIE      LL_I3C_IER_RXFNEIE /*!< Rx FIFO not empty interrupt enable     */
+#define HAL_I3C_IT_FCIE         LL_I3C_IER_FCIE    /*!< Frame complete interrupt enable        */
+#define HAL_I3C_IT_ERRIE        LL_I3C_IER_ERRIE   /*!< Error interrupt enable                 */
+#define HAL_I3C_ALL_COMMON_ITS  (uint32_t)(LL_I3C_IER_TXFNFIE | LL_I3C_IER_RXFNEIE | \
+                                           LL_I3C_IER_FCIE    | LL_I3C_IER_ERRIE)
+/**
+  * @}
+  */
+
+/** @defgroup I3C_TARGET_INTERRUPT I3C TARGET INTERRUPT
+  * @{
+  */
+#define HAL_I3C_IT_IBIENDIE     LL_I3C_IER_IBIENDIE /*!< IBI end interrupt enable                    */
+#define HAL_I3C_IT_CRUPDIE      LL_I3C_IER_CRUPDIE  /*!< controller-role update interrupt enable     */
+#define HAL_I3C_IT_WKPIE        LL_I3C_IER_WKPIE    /*!< wakeup interrupt enable                     */
+#define HAL_I3C_IT_GETIE        LL_I3C_IER_GETIE    /*!< GETxxx CCC interrupt enable                 */
+#define HAL_I3C_IT_STAIE        LL_I3C_IER_STAIE    /*!< GETSTATUS CCC interrupt enable              */
+#define HAL_I3C_IT_DAUPDIE      LL_I3C_IER_DAUPDIE  /*!< ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable */
+#define HAL_I3C_IT_MWLUPDIE     LL_I3C_IER_MWLUPDIE /*!< SETMWL CCC interrupt enable                 */
+#define HAL_I3C_IT_MRLUPDIE     LL_I3C_IER_MRLUPDIE /*!< SETMRL CCC interrupt enable                 */
+#define HAL_I3C_IT_RSTIE        LL_I3C_IER_RSTIE    /*!< reset pattern interrupt enable              */
+#define HAL_I3C_IT_ASUPDIE      LL_I3C_IER_ASUPDIE  /*!< ENTASx CCC interrupt enable                 */
+#define HAL_I3C_IT_INTUPDIE     LL_I3C_IER_INTUPDIE /*!< ENEC/DISEC CCC interrupt enable             */
+#define HAL_I3C_IT_DEFIE        (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE)
+/*!< DEFTGTS CCC interrupt enable                */
+#define HAL_I3C_IT_GRPIE        (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE)
+/*!< DEFGRPA CCC interrupt enable                */
+#define HAL_I3C_ALL_TGT_ITS     (uint32_t)(LL_I3C_IER_IBIENDIE | LL_I3C_IER_CRUPDIE  | LL_I3C_IER_WKPIE   | \
+                                           LL_I3C_IER_GETIE    | LL_I3C_IER_STAIE    | LL_I3C_IER_DAUPDIE | \
+                                           LL_I3C_IER_MWLUPDIE | LL_I3C_IER_MRLUPDIE | LL_I3C_IER_RSTIE   | \
+                                           LL_I3C_IER_ASUPDIE  | LL_I3C_IER_INTUPDIE | LL_I3C_IER_DEFIE   | \
+                                           LL_I3C_IER_GRPIE)
+/**
+  * @}
+  */
+
+/** @defgroup I3C_CONTROLLER_INTERRUPT I3C CONTROLLER INTERRUPT
+  * @{
+  */
+#define HAL_I3C_IT_CFNFIE      LL_I3C_IER_CFNFIE     /*!< Control FIFO not full interrupt enable     */
+#define HAL_I3C_IT_SFNEIE      LL_I3C_IER_SFNEIE     /*!< Status FIFO not empty interrupt enable     */
+#define HAL_I3C_IT_HJIE        LL_I3C_IER_HJIE       /*!< Hot-join interrupt enable                  */
+#define HAL_I3C_IT_CRIE        LL_I3C_IER_CRIE       /*!< Controller-role request interrupt enable   */
+#define HAL_I3C_IT_IBIIE       LL_I3C_IER_IBIIE      /*!< IBI request interrupt enable               */
+#define HAL_I3C_IT_RXTGTENDIE  LL_I3C_IER_RXTGTENDIE /*!< Target-initiated read end interrupt enable */
+#define HAL_I3C_ALL_CTRL_ITS   (uint32_t)(LL_I3C_IER_CFNFIE | LL_I3C_IER_SFNEIE | LL_I3C_IER_HJIE | \
+                                          LL_I3C_IER_CRIE  | LL_I3C_IER_IBIIE  | LL_I3C_IER_RXTGTENDIE)
+/**
+  * @}
+  */
+
+/** @defgroup I3C_FLAGS I3C FLAGS
+  * @{
+  */
+#define HAL_I3C_FLAG_CFEF       LL_I3C_EVR_CFEF      /*!< Control FIFO not empty flag      */
+#define HAL_I3C_FLAG_TXFEF      LL_I3C_EVR_TXFEF     /*!< Tx FIFO empty flag               */
+#define HAL_I3C_FLAG_CFNFF      LL_I3C_EVR_CFNFF     /*!< Control FIFO not full flag       */
+#define HAL_I3C_FLAG_SFNEF      LL_I3C_EVR_SFNEF     /*!< Status FIFO not empty flag       */
+#define HAL_I3C_FLAG_TXFNFF     LL_I3C_EVR_TXFNFF    /*!< Tx FIFO not full flag            */
+#define HAL_I3C_FLAG_RXFNEF     LL_I3C_EVR_RXFNEF    /*!< Rx FIFO not empty flag           */
+#define HAL_I3C_FLAG_RXLASTF    LL_I3C_EVR_RXLASTF   /*!< Last read data byte/word flag    */
+#define HAL_I3C_FLAG_TXLASTF    LL_I3C_EVR_TXLASTF   /*!< Last written data byte/word flag */
+#define HAL_I3C_FLAG_FCF        LL_I3C_EVR_FCF       /*!< Frame complete flag              */
+#define HAL_I3C_FLAG_RXTGTENDF  LL_I3C_EVR_RXTGTENDF /*!< Target-initiated read end flag   */
+#define HAL_I3C_FLAG_ERRF       LL_I3C_EVR_ERRF      /*!< Error flag                       */
+#define HAL_I3C_FLAG_IBIF       LL_I3C_EVR_IBIF      /*!< IBI request flag                 */
+#define HAL_I3C_FLAG_IBIENDF    LL_I3C_EVR_IBIENDF   /*!< IBI end flag                     */
+#define HAL_I3C_FLAG_CRF        LL_I3C_EVR_CRF       /*!< Controller-role request flag     */
+#define HAL_I3C_FLAG_CRUPDF     LL_I3C_EVR_CRUPDF    /*!< Controller-role update flag      */
+#define HAL_I3C_FLAG_HJF        LL_I3C_EVR_HJF       /*!< Hot-join flag                    */
+#define HAL_I3C_FLAG_WKPF       LL_I3C_EVR_WKPF      /*!< Wakeup flag                      */
+#define HAL_I3C_FLAG_GETF       LL_I3C_EVR_GETF      /*!< GETxxx CCC flag                  */
+#define HAL_I3C_FLAG_STAF       LL_I3C_EVR_STAF      /*!< Format 1 GETSTATUS CCC flag      */
+#define HAL_I3C_FLAG_DAUPDF     LL_I3C_EVR_DAUPDF    /*!< ENTDAA/RSTDAA/SETNEWDA CCC flag  */
+#define HAL_I3C_FLAG_MWLUPDF    LL_I3C_EVR_MWLUPDF   /*!< SETMWL CCC flag                  */
+#define HAL_I3C_FLAG_MRLUPDF    LL_I3C_EVR_MRLUPDF   /*!< SETMRL CCC flag                  */
+#define HAL_I3C_FLAG_RSTF       LL_I3C_EVR_RSTF      /*!< Reset pattern flag               */
+#define HAL_I3C_FLAG_ASUPDF     LL_I3C_EVR_ASUPDF    /*!< ENTASx CCC flag                  */
+#define HAL_I3C_FLAG_INTUPDF    LL_I3C_EVR_INTUPDF   /*!< ENEC/DISEC CCC flag              */
+#define HAL_I3C_FLAG_DEFF       LL_I3C_EVR_DEFF      /*!< DEFTGTS CCC flag                 */
+#define HAL_I3C_FLAG_GRPF       LL_I3C_EVR_GRPF      /*!< DEFGRPA CCC flag                 */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD
+  * @{
+  */
+#define HAL_I3C_BCR_IN_PAYLOAD_SHIFT             48                  /*!< BCR field in target payload */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_PATTERN_CONFIGURATION I3C PATTERN CONFIGURATION
+  * @{
+  */
+#define HAL_I3C_TARGET_RESET_PATTERN             0x00000001U        /*!< Target reset pattern */
+#define HAL_I3C_HDR_EXIT_PATTERN                 0x00000002U        /*!< HDR exit pattern */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_RESET_PATTERN RESET PATTERN
+  * @{
+  */
+#define HAL_I3C_RESET_PATTERN_DISABLE            0x00000000U
+/*!< Standard STOP condition emitted at the end of a frame */
+#define HAL_I3C_RESET_PATTERN_ENABLE             I3C_CFGR_RSTPTRN
+/*!< Reset pattern is inserted before the STOP condition of any emitted frame */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ---------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Exported_Macros I3C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I3C handle state.
+  * @param  __HANDLE__ specifies the I3C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1)
+#define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
+                                                                    (__HANDLE__)->State = HAL_I3C_STATE_RESET;  \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                                  } while(0)
+#else
+#define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I3C_STATE_RESET)
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified I3C interrupt.
+  * @param  __HANDLE__ specifies the I3C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *         This parameter can be one value or a combination of the following group's values:
+  *            @arg @ref I3C_CONTROLLER_INTERRUPT
+  *            @arg @ref I3C_TARGET_INTERRUPT
+  *            @arg @ref I3C_COMMON_INTERRUPT
+  * @retval None
+  */
+#define __HAL_I3C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I3C interrupt.
+  * @param  __HANDLE__ specifies the I3C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *         This parameter can be one value or a combination of the following group's values:
+  *            @arg @ref I3C_CONTROLLER_INTERRUPT
+  *            @arg @ref I3C_TARGET_INTERRUPT
+  *            @arg @ref I3C_COMMON_INTERRUPT
+  * @retval None
+  */
+#define __HAL_I3C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I3C flag is set or not.
+  * @param  __HANDLE__ specifies the I3C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one value of the group @arg @ref I3C_FLAGS values.
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_I3C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->EVR) &\
+                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Get Bus Characterics in payload (64bits) receive during ENTDAA procedure.
+  * @param  __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF.
+  * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF.
+  */
+#define __HAL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> HAL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \
+                                        I3C_BCR_BCR)
+
+/** @brief  Check IBI request capabilities.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval The state of IBI request capabilities (ENABLE or DISABLE).
+  */
+#define __HAL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \
+                                            ? ENABLE : DISABLE)
+
+/** @brief  Check IBI additional data byte capabilities.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval The state of IBI additional data byte capabilities (ENABLE or DISABLE).
+  */
+#define __HAL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \
+                                            ? ENABLE : DISABLE)
+
+/** @brief  Check Controller role request capabilities.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval The state of Controller role request capabilities (ENABLE or DISABLE).
+  */
+#define __HAL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \
+                                           ? ENABLE : DISABLE)
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @addtogroup I3C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions.
+  * @{
+  */
+HAL_StatusTypeDef HAL_I3C_Init(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_DeInit(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_MspInit(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c);
+/**
+  * @}
+  */
+
+/** @addtogroup I3C_Exported_Functions_Group2 Interrupt and callback functions.
+  * @{
+  */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_I3C_RegisterCallback(I3C_HandleTypeDef *hi3c,
+                                           HAL_I3C_CallbackIDTypeDef callbackID,
+                                           pI3C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I3C_RegisterNotifyCallback(I3C_HandleTypeDef *hi3c,
+                                                 pI3C_NotifyCallbackTypeDef pNotifyCallback);
+HAL_StatusTypeDef HAL_I3C_RegisterTgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c,
+                                                            pI3C_TgtReqDynamicAddrCallbackTypeDef pTgtReqAddrCallback);
+HAL_StatusTypeDef HAL_I3C_RegisterTgtHotJoinCallback(I3C_HandleTypeDef *hi3c,
+                                                     pI3C_TgtHotJoinCallbackTypeDef pTgtHotJoinCallback);
+HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_CallbackIDTypeDef callbackID);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData,
+                                               uint32_t interruptMask);
+HAL_StatusTypeDef HAL_I3C_DeactivateNotification(I3C_HandleTypeDef *hi3c, uint32_t interruptMask);
+void HAL_I3C_CtrlTxCpltCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_CtrlDAACpltCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_TgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, uint64_t targetPayload);
+void HAL_I3C_TgtTxCpltCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_TgtRxCpltCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_TgtHotJoinCallback(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress);
+void HAL_I3C_NotifyCallback(I3C_HandleTypeDef *hi3c, uint32_t eventId);
+void HAL_I3C_AbortCpltCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_ErrorCallback(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_ER_IRQHandler(I3C_HandleTypeDef *hi3c);
+void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c);
+/**
+  * @}
+  */
+
+/** @addtogroup I3C_Exported_Functions_Group3 Configuration functions.
+  * @{
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c,
+                                                       const LL_I3C_CtrlBusConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_I3C_Tgt_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c,
+                                                      const LL_I3C_TgtBusConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_I3C_SetConfigFifo(I3C_HandleTypeDef *hi3c, const I3C_FifoConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_I3C_Tgt_Config(I3C_HandleTypeDef *hi3c, const I3C_TgtConfTypeDef *pConfig);
+HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef           *hi3c,
+                                                const I3C_DeviceConfTypeDef *pDesc,
+                                                uint8_t                      nbDevice);
+HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef         *hi3c,
+                                         const I3C_CCCTypeDef      *pCCCDesc,
+                                         const I3C_PrivateTypeDef  *pPrivateDesc,
+                                         I3C_XferTypeDef           *pXferData,
+                                         uint8_t                   nbFrame,
+                                         uint32_t                  option);
+HAL_StatusTypeDef HAL_I3C_Ctrl_SetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t resetPattern);
+HAL_StatusTypeDef HAL_I3C_Ctrl_GetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t *pResetPattern);
+/**
+  * @}
+  */
+
+/** @addtogroup I3C_Exported_Functions_Group4 FIFO Management functions.
+  * @{
+  */
+HAL_StatusTypeDef HAL_I3C_FlushAllFifo(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_FlushTxFifo(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_FlushRxFifo(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_FlushControlFifo(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_FlushStatusFifo(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_ClearConfigFifo(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTypeDef *pConfig);
+/**
+  * @}
+  */
+
+/** @addtogroup I3C_Exported_Functions_Group5 Controller operational functions.
+  * @{
+  */
+/* Controller transmit direct write or a broadcast CCC command APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c,
+                                           I3C_XferTypeDef   *pXferData,
+                                           uint32_t           timeout);
+HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c,
+                                              I3C_XferTypeDef   *pXferData);
+HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c,
+                                               I3C_XferTypeDef   *pXferData);
+
+/* Controller transmit direct read CCC command APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c,
+                                          I3C_XferTypeDef   *pXferData,
+                                          uint32_t           timeout);
+HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c,
+                                             I3C_XferTypeDef   *pXferData);
+HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c,
+                                              I3C_XferTypeDef   *pXferData);
+
+/* Controller private write APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef   *hi3c,
+                                        I3C_XferTypeDef     *pXferData,
+                                        uint32_t             timeout);
+HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef   *hi3c,
+                                           I3C_XferTypeDef     *pXferData);
+HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef   *hi3c,
+                                            I3C_XferTypeDef     *pXferData);
+
+/* Controller private read APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Receive(I3C_HandleTypeDef   *hi3c,
+                                       I3C_XferTypeDef     *pXferData,
+                                       uint32_t             timeout);
+HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef   *hi3c,
+                                          I3C_XferTypeDef     *pXferData);
+HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef   *hi3c,
+                                           I3C_XferTypeDef     *pXferData);
+
+/* Controller multiple Direct CCC Command, I3C private or I2C transfer APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef   *hi3c,
+                                                   I3C_XferTypeDef     *pXferData);
+HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef   *hi3c,
+                                                    I3C_XferTypeDef     *pXferData);
+
+/* Controller assign dynamic address APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAddress);
+HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption);
+HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c,
+                                             uint64_t          *target_payload,
+                                             uint32_t           dynOption,
+                                             uint32_t           timeout);
+/* Controller check device ready APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c,
+                                                 uint8_t            devAddress,
+                                                 uint32_t           trials,
+                                                 uint32_t           timeout);
+HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c,
+                                                 uint8_t            devAddress,
+                                                 uint32_t           trials,
+                                                 uint32_t           timeout);
+/* Controller arbitration APIs */
+HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint32_t timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup I3C_Exported_Functions_Group6 Target operational functions.
+  * @{
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout);
+HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData);
+HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData);
+HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout);
+HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData);
+HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData);
+HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq(I3C_HandleTypeDef *hi3c, uint32_t timeout);
+HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq_IT(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq(I3C_HandleTypeDef *hi3c, uint8_t *pAddress, uint32_t timeout);
+HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq_IT(I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload,
+                                     uint8_t payloadSize, uint32_t timeout);
+HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq_IT(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, uint8_t payloadSize);
+/**
+  * @}
+  */
+
+/** @addtogroup I3C_Exported_Functions_Group7 Generic and Common functions.
+  * @{
+  */
+HAL_StatusTypeDef HAL_I3C_Abort_IT(I3C_HandleTypeDef *hi3c);
+HAL_I3C_StateTypeDef HAL_I3C_GetState(const I3C_HandleTypeDef *hi3c);
+HAL_I3C_ModeTypeDef HAL_I3C_GetMode(const I3C_HandleTypeDef *hi3c);
+uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c);
+HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c,
+                                     uint32_t notifyId,
+                                     I3C_CCCInfoTypeDef *pCCCInfo);
+HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c,
+                                                  uint64_t ENTDAA_payload,
+                                                  I3C_ENTDAAPayloadTypeDef *pENTDAA_payload);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Private_Constants I3C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Private_Macro I3C Private Macros
+  * @{
+  */
+#define IS_I3C_MODE(__MODE__) (((__MODE__) == HAL_I3C_MODE_NONE)       || \
+                               ((__MODE__) == HAL_I3C_MODE_CONTROLLER) || \
+                               ((__MODE__) == HAL_I3C_MODE_TARGET))
+
+#define IS_I3C_INTERRUPTMASK(__MODE__, __ITMASK__) (((__MODE__) == HAL_I3C_MODE_CONTROLLER)             ? \
+                                                    ((((__ITMASK__) & HAL_I3C_ALL_CTRL_ITS) != 0x0U)   || \
+                                                     (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U)) : \
+                                                    ((((__ITMASK__) & HAL_I3C_ALL_TGT_ITS) != 0x0U)    || \
+                                                     (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U)))
+
+#define IS_I3C_ENTDAA_OPTION(__OPTION__) (((__OPTION__) == I3C_RSTDAA_THEN_ENTDAA) || \
+                                          ((__OPTION__) == I3C_ONLY_ENTDAA))
+
+#define IS_I3C_SDAHOLDTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_0_5) || \
+                                             ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_1_5))
+
+#define IS_I3C_WAITTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_0) || \
+                                          ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_1) || \
+                                          ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_2) || \
+                                          ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_3))
+
+#define IS_I3C_TXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_4_4))
+
+#define IS_I3C_RXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_4_4))
+
+#define IS_I3C_CONTROLFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_CONTROLFIFO_DISABLE) || \
+                                                  ((__VALUE__) == HAL_I3C_CONTROLFIFO_ENABLE))
+
+#define IS_I3C_STATUSFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_STATUSFIFO_DISABLE) || \
+                                                 ((__VALUE__) == HAL_I3C_STATUSFIFO_ENABLE))
+
+#define IS_I3C_DEVICE_VALUE(__VALUE__) (((__VALUE__) >= 1U) && ((__VALUE__) <= 4U))
+
+#define IS_I3C_DYNAMICADDRESS_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU)
+
+#define IS_I3C_FUNCTIONALSTATE_VALUE(__VALUE__) (((__VALUE__) == DISABLE) || \
+                                                 ((__VALUE__) == ENABLE))
+
+#define IS_I3C_HANDOFFACTIVITYSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_0) || \
+                                                      ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_1) || \
+                                                      ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_2) || \
+                                                      ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_3))
+
+#define IS_I3C_TSCOTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS) || \
+                                          ((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS))
+
+#define IS_I3C_MAXSPEEDDATA_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_1    ) || \
+                                              ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_LSB) || \
+                                              ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MID) || \
+                                              ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MSB))
+
+#define IS_I3C_IBIPAYLOADSIZE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_PAYLOAD_EMPTY  ) || \
+                                                ((__VALUE__) == HAL_I3C_PAYLOAD_1_BYTE ) || \
+                                                ((__VALUE__) == HAL_I3C_PAYLOAD_2_BYTES) || \
+                                                ((__VALUE__) == HAL_I3C_PAYLOAD_3_BYTES) || \
+                                                ((__VALUE__) == HAL_I3C_PAYLOAD_4_BYTES))
+
+#define IS_I3C_MIPIIDENTIFIER_VALUE(__VALUE__) ((__VALUE__) <= 0x0FU)
+
+#define IS_I3C_MAXREADTURNARROUND_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
+
+#define I3C_CHECK_IT_SOURCE(__IER__, __IT__)  ((((__IER__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define I3C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+#define IS_I3C_DMASOURCEBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_BYTE)
+
+#define IS_I3C_DMASOURCEWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_WORD)
+
+#define IS_I3C_DMADESTINATIONBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_BYTE)
+
+#define IS_I3C_DMADESTINATIONWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_WORD)
+
+#define I3C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
+#define IS_I3C_RESET_PATTERN(__RSTPTRN__) (((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_ENABLE)   || \
+                                           ((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_DISABLE))
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Private_Functions I3C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32n6xx_hal_i3c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_I3C_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_icache.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_icache.h
new file mode 100644
index 000000000..4630212c4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_icache.h
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_icache.h
+  * @author  MCD Application Team
+  * @brief   Header file of ICACHE HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32N6xx_HAL_ICACHE_H
+#define STM32N6xx_HAL_ICACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined(ICACHE)
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ICACHE
+  * @{
+  */
+
+/* Exported types -----------------------------------------------------------*/
+
+/* Exported constants -------------------------------------------------------*/
+/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants
+  * @{
+  */
+
+/** @defgroup ICACHE_WaysSelection Ways selection
+  * @{
+  */
+#define ICACHE_1WAY                    0U                /*!< 1-way cache (direct mapped cache) */
+#define ICACHE_4WAYS                   ICACHE_CR_WAYSEL  /*!< 4-ways set associative cache (default) */
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_Monitor_Type Monitor type
+  * @{
+  */
+#define ICACHE_MONITOR_HIT_MISS        (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */
+#define ICACHE_MONITOR_HIT             ICACHE_CR_HITMEN                       /*!< Hit monitoring */
+#define ICACHE_MONITOR_MISS            ICACHE_CR_MISSMEN                      /*!< Miss monitoring */
+/**
+  * @}
+  */
+
+
+/** @defgroup ICACHE_Interrupts Interrupts
+  * @{
+  */
+#define ICACHE_IT_BUSYEND              ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
+#define ICACHE_IT_ERROR                ICACHE_IER_ERRIE    /*!< Cache error interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_Flags Flags
+  * @{
+  */
+#define ICACHE_FLAG_BUSY               ICACHE_SR_BUSYF     /*!< Busy flag */
+#define ICACHE_FLAG_BUSYEND            ICACHE_SR_BSYENDF   /*!< Busy end flag */
+#define ICACHE_FLAG_ERROR              ICACHE_SR_ERRF      /*!< Cache error flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ----------------------------------------------------------*/
+/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros
+  * @{
+  */
+
+/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management
+  * @brief macros to manage the specified ICACHE flags and interrupts.
+  * @{
+  */
+
+/** @brief  Enable ICACHE interrupts.
+  * @param  __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref ICACHE_IT_BUSYEND  Busy end interrupt
+  *            @arg @ref ICACHE_IT_ERROR  Cache error interrupt
+  */
+#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__))
+
+/** @brief  Disable ICACHE interrupts.
+  * @param  __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref ICACHE_IT_BUSYEND  Busy end interrupt
+  *            @arg @ref ICACHE_IT_ERROR  Cache error interrupt
+  */
+#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__))
+
+/** @brief  Check whether the specified ICACHE interrupt source is enabled or not.
+  * @param  __INTERRUPT__ specifies the ICACHE interrupt source to check.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref ICACHE_IT_BUSYEND  Busy end interrupt
+  *            @arg @ref ICACHE_IT_ERROR  Cache error interrupt
+  * @retval The state of __INTERRUPT__ (0 or 1).
+  */
+#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__)  \
+  ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
+
+/** @brief  Check whether the selected ICACHE flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref ICACHE_FLAG_BUSY  Busy flag
+  *            @arg @ref ICACHE_FLAG_BUSYEND  Busy end flag
+  *            @arg @ref ICACHE_FLAG_ERROR  Cache error flag
+  * @retval The state of __FLAG__ (0 or 1).
+  */
+#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U)
+
+/** @brief  Clear the selected ICACHE flags.
+  * @param  __FLAG__ specifies the ICACHE flags to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref ICACHE_FLAG_BUSYEND  Busy end flag
+  *            @arg @ref ICACHE_FLAG_ERROR  Cache error flag
+  */
+#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions -------------------------------------------------------*/
+/** @addtogroup ICACHE_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ICACHE_Exported_Functions_Group1
+  * @brief    Initialization and control functions
+  * @{
+  */
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_ICACHE_Enable(void);
+HAL_StatusTypeDef HAL_ICACHE_Disable(void);
+uint32_t HAL_ICACHE_IsEnabled(void);
+HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
+HAL_StatusTypeDef HAL_ICACHE_DeInit(void);
+
+/******* Invalidate in blocking mode (Polling) */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
+/******* Invalidate in non-blocking mode (Interrupt) */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
+/******* Wait for Invalidate complete in blocking mode (Polling) */
+HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
+
+/******* Performance instruction cache monitoring functions */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType);
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType);
+uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
+uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup ICACHE_Exported_Functions_Group2
+  * @brief    IRQ and callback functions
+  * @{
+  */
+/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
+void HAL_ICACHE_IRQHandler(void);
+void HAL_ICACHE_InvalidateCompleteCallback(void);
+void HAL_ICACHE_ErrorCallback(void);
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* ICACHE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_ICACHE_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_irda.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_irda.h
new file mode 100644
index 000000000..143bdd737
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_irda.h
@@ -0,0 +1,885 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_irda.h
+  * @author  MCD Application Team
+  * @brief   Header file of IRDA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_IRDA_H
+#define STM32N6xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup IRDA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+  * @{
+  */
+
+/**
+  * @brief IRDA Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
+                                           where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref IRDAEx_Word_Length */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref IRDA_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+                                           to achieve low-power frequency.
+                                           @note Prescaler value 0 is forbidden */
+
+  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
+                                           This parameter can be a value of @ref IRDA_Low_Power */
+
+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the IRDA clock source.
+                                           This parameter can be a value of @ref IRDA_ClockPrescaler. */
+
+} IRDA_InitTypeDef;
+
+/**
+  * @brief HAL IRDA State definition
+  * @note  HAL IRDA State value is a combination of 2 different substates:
+  *        gState and RxState (see @ref IRDA_State_Definition).
+  *        - gState contains IRDA state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL IRDA Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_IRDA_StateTypeDef;
+
+/**
+  * @brief  IRDA handle Structure definition
+  */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+typedef struct __IRDA_HandleTypeDef
+#else
+typedef struct
+#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+{
+  USART_TypeDef            *Instance;        /*!< USART registers base address       */
+
+  IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
+
+  const uint8_t            *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
+
+  uint16_t                 Mask;             /*!< USART RX RDR register mask         */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+  HAL_LockTypeDef          Lock;             /*!< Locking object                     */
+
+  __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
+                                                  and also related to Tx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO uint32_t            ErrorCode;        /*!< IRDA Error code                    */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
+
+  void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
+
+  void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
+
+  void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
+
+  void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
+
+  void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
+
+  void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
+
+  void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
+
+
+  void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
+
+  void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
+#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+} IRDA_HandleTypeDef;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL IRDA Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
+  HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
+  HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
+  HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
+  HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
+  HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
+  HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
+  HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
+
+  HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
+  HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
+
+} HAL_IRDA_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL IRDA Callback pointer definition
+  */
+typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
+
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
+  * @{
+  */
+
+/** @defgroup IRDA_State_Definition IRDA State Code Definition
+  * @{
+  */
+#define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized
+                                                               Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use
+                                                               Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing
+                                                               Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing
+                                                               Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing
+                                                               Value is allowed for RxState only */
+#define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing
+                                                               Not to be used for neither gState nor RxState.
+                                                               Value is result of combination (Or) between
+                                                               gState and RxState values */
+#define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state
+                                                               Value is allowed for gState only */
+#define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error
+                                                               Value is allowed for gState only */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
+  * @{
+  */
+#define HAL_IRDA_ERROR_NONE                 (0x00000000U)          /*!< No error                */
+#define HAL_IRDA_ERROR_PE                   (0x00000001U)          /*!< Parity error            */
+#define HAL_IRDA_ERROR_NE                   (0x00000002U)          /*!< Noise error             */
+#define HAL_IRDA_ERROR_FE                   (0x00000004U)          /*!< frame error             */
+#define HAL_IRDA_ERROR_ORE                  (0x00000008U)          /*!< Overrun error           */
+#if defined(HAL_DMA_MODULE_ENABLED)
+#define HAL_IRDA_ERROR_DMA                  (0x00000010U)          /*!< DMA transfer error      */
+#endif /* HAL_DMA_MODULE_ENABLED */
+#define HAL_IRDA_ERROR_BUSY                 (0x00000020U)          /*!< Busy Error              */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+#define HAL_IRDA_ERROR_INVALID_CALLBACK     (0x00000040U)          /*!< Invalid Callback error  */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Parity IRDA Parity
+  * @{
+  */
+#define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */
+#define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */
+#define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+  * @{
+  */
+#define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */
+#define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */
+#define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+  * @{
+  */
+#define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
+  * @{
+  */
+#define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define IRDA_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define IRDA_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define IRDA_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define IRDA_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define IRDA_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define IRDA_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define IRDA_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define IRDA_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define IRDA_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define IRDA_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define IRDA_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_State IRDA State
+  * @{
+  */
+#define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */
+#define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Mode IRDA Mode
+  * @{
+  */
+#define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+  * @{
+  */
+#define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
+  * @{
+  */
+#define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+  * @{
+  */
+#define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
+#define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Flags IRDA Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */
+#define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */
+#define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */
+#define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */
+#define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */
+#define IRDA_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< IRDA transmit data register empty         */
+#define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */
+#define IRDA_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< IRDA read data register not empty         */
+#define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */
+#define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */
+#define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */
+#define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */
+#define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */
+#define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */
+
+/*       Elements values convention: 000000000XXYYYYYb
+             - YYYYY  : Interrupt source position in the XX register (5bits)
+             - XX  : Interrupt source register (2bits)
+                   - 01: CR1 register
+                   - 10: CR2 register
+                   - 11: CR3 register */
+#define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */
+
+/*       Elements values convention: 0000ZZZZ00000000b
+             - ZZZZ  : Flag position in the ISR register(4bits) */
+#define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */
+#define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
+  * @{
+  */
+#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
+#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
+#define IRDA_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag  */
+#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
+#define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
+#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
+  * @{
+  */
+#define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */
+#define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */
+#define IRDA_CR_POS   5U       /*!< IRDA control register position */
+#define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */
+#define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset IRDA handle state.
+  * @param  __HANDLE__ IRDA handle.
+  * @retval None
+  */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
+
+/** @brief  Flush the IRDA DR register.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
+  do{                                                                    \
+    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+  } while(0U)
+
+/** @brief  Clear the specified IRDA pending flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF
+  *            @arg @ref IRDA_CLEAR_FEF
+  *            @arg @ref IRDA_CLEAR_NEF
+  *            @arg @ref IRDA_CLEAR_OREF
+  *            @arg @ref IRDA_CLEAR_TCF
+  *            @arg @ref IRDA_CLEAR_IDLEF
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the IRDA PE pending flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief  Clear the IRDA FE pending flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief  Clear the IRDA NE pending flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief  Clear the IRDA ORE pending flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief  Clear the IRDA IDLE pending flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified IRDA flag is set or not.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref IRDA_FLAG_BUSY  Busy flag
+  *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
+  *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
+  *            @arg @ref IRDA_FLAG_NE    Noise Error flag
+  *            @arg @ref IRDA_FLAG_FE    Framing Error flag
+  *            @arg @ref IRDA_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Enable the specified IRDA interrupt.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+                                                           ((__HANDLE__)->Instance->CR1 |= (1U << \
+                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
+                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+                                                           ((__HANDLE__)->Instance->CR2 |= (1U << \
+                                                               ((__INTERRUPT__) & IRDA_IT_MASK))):\
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << \
+                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief  Disable the specified IRDA interrupt.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
+                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
+                                                               ((__INTERRUPT__) & IRDA_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
+                                                               ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief  Check whether the specified IRDA interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
+  *            @arg @ref IRDA_IT_NE Noise Error interrupt
+  *            @arg @ref IRDA_IT_FE Framing Error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (SET or RESET).
+  */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
+  ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
+
+/** @brief  Check whether the specified IRDA interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+  *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+  *            @arg @ref IRDA_IT_PE Parity Error interrupt
+  * @retval The new state of __IT__ (SET or RESET).
+  */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                                                          \
+  ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__)  \
+      & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3))           \
+     & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+
+/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+  *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+  *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
+  * @retval None
+  */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief  Set a specific IRDA request flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the IRDA one bit sample method.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the IRDA one bit sample method.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable UART/USART associated to IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup IRDA_Private_Macros
+  * @{
+  */
+
+/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
+  * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
+
+/** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
+  * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
+  * @retval True or False
+  */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
+
+/** @brief Ensure that IRDA frame parity is valid.
+  * @param __PARITY__ IRDA frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
+                                    ((__PARITY__) == IRDA_PARITY_ODD))
+
+/** @brief Ensure that IRDA communication mode is valid.
+  * @param __MODE__ IRDA communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
+                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/** @brief Ensure that IRDA power mode is valid.
+  * @param __MODE__ IRDA power mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/** @brief Ensure that IRDA clock Prescaler is valid.
+  * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
+
+/** @brief Ensure that IRDA state is valid.
+  * @param __STATE__ IRDA state mode.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+                                  ((__STATE__) == IRDA_STATE_ENABLE))
+
+/** @brief Ensure that IRDA associated UART/USART mode is valid.
+  * @param __MODE__ IRDA associated UART/USART mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
+                                 ((__MODE__) == IRDA_MODE_ENABLE))
+
+/** @brief Ensure that IRDA sampling rate is valid.
+  * @param __ONEBIT__ IRDA sampling rate.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/** @brief Ensure that IRDA DMA TX mode is valid.
+  * @param __DMATX__ IRDA DMA TX mode.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/** @brief Ensure that IRDA DMA RX mode is valid.
+  * @param __DMARX__ IRDA DMA RX mode.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/** @brief Ensure that IRDA request is valid.
+  * @param __PARAM__ IRDA request.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+  * @}
+  */
+
+/* Include IRDA HAL Extended module */
+#include "stm32n6xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+  * @{
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+                                            pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+#endif /* HAL_DMA_MODULE_ENABLED */
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
+uint32_t              HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_IRDA_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_irda_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_irda_ex.h
new file mode 100644
index 000000000..ec91daaa7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_irda_ex.h
@@ -0,0 +1,198 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_irda_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of IRDA HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_IRDA_EX_H
+#define STM32N6xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IRDAEx IRDAEx
+  * @brief IRDA Extended HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
+  * @{
+  */
+#define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the IRDA clock source.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+  */
+/** @brief  Return clock source used for USART instance used for IRDA.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval USART clocking source, written in __CLOCKSOURCE__.
+  */
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)           \
+  do {                                                            \
+    if((__HANDLE__)->Instance == USART1)                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART1;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART2)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART2;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART3)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART3;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART4)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART4;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART5)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART5;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART6)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART6;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART7)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART7;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART8)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART8;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART9)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART9;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART10)                    \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART10;        \
+    }                                                             \
+    else                                                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = 0U;                                     \
+    }                                                             \
+  } while(0U)
+
+
+/** @brief  Compute the mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/** @brief Ensure that IRDA frame length is valid.
+  * @param __LENGTH__ IRDA frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_IRDA_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_iwdg.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_iwdg.h
new file mode 100644
index 000000000..5d5598a0c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_iwdg.h
@@ -0,0 +1,302 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_iwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of IWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_IWDG_H
+#define STM32N6xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IWDG IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+  * @{
+  */
+
+/**
+  * @brief  IWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
+                            This parameter can be a value of @ref IWDG_Prescaler */
+
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+  uint32_t EWI;        /*!< Specifies if IWDG Early Wakeup Interrupt is enable or not and the comparator value.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF
+                            value 0 means that EWI is disabled */
+} IWDG_InitTypeDef;
+
+/**
+  * @brief  IWDG Handle Structure definition
+  */
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+typedef struct __IWDG_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+{
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+  void (* EwiCallback)(struct __IWDG_HandleTypeDef *hiwdg);                  /*!< IWDG Early WakeUp Interrupt callback */
+  void (* MspInitCallback)(struct __IWDG_HandleTypeDef *hiwdg);              /*!< IWDG Msp Init callback */
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+} IWDG_HandleTypeDef;
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL IWDG common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_IWDG_EWI_CB_ID          = 0x00U,    /*!< IWDG EWI callback ID */
+  HAL_IWDG_MSPINIT_CB_ID      = 0x01U,    /*!< IWDG MspInit callback ID */
+} HAL_IWDG_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL IWDG Callback pointer definition
+  */
+typedef void (*pIWDG_CallbackTypeDef)(IWDG_HandleTypeDef *hppp);  /*!< pointer to a IWDG common callback functions */
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+  * @{
+  */
+#define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
+#define IWDG_PRESCALER_512              (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0)    /*!< IWDG prescaler set to 512 */
+#define IWDG_PRESCALER_1024             IWDG_PR_PR_3                                    /*!< IWDG prescaler set to 1024 */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+  * @{
+  */
+#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_EWI_Mode IWDG Early Wakeup Interrupt Mode
+  * @{
+  */
+#define IWDG_EWI_DISABLE                0x00000000u       /*!< EWI Disable */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Active_Status IWDG Active Status
+  * @{
+  */
+#define IWDG_STATUS_DISABLE             0x00000000u
+#define IWDG_STATUS_ENABLE              IWDG_SR_ONF
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the IWDG peripheral.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+  * @brief  Reload IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers disabled).
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+  * @{
+  */
+/* Initialization/Start functions  ********************************************/
+HAL_StatusTypeDef     HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void                  HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef     HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID,
+                                                pIWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+uint32_t              HAL_IWDG_GetActiveStatus(const IWDG_HandleTypeDef *hiwdg);
+void                  HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg);
+void                  HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+/**
+  * @brief  IWDG Key Register BitMask
+  */
+#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+  * @brief  Check IWDG prescaler value.
+  * @param  __PRESCALER__  IWDG prescaler value
+  * @retval None
+  */
+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_256)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_512)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_1024))
+
+/**
+  * @brief  Check IWDG reload value.
+  * @param  __RELOAD__  IWDG reload value
+  * @retval None
+  */
+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+  * @brief  Check IWDG window value.
+  * @param  __WINDOW__  IWDG window value
+  * @retval None
+  */
+#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
+
+/**
+  * @brief  Check IWDG ewi value.
+  * @param  __EWI__  IWDG ewi value
+  * @retval None
+  */
+#define IS_IWDG_EWI(__EWI__)            ((__EWI__) <= IWDG_EWCR_EWIT)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_IWDG_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_jpeg.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_jpeg.h
new file mode 100644
index 000000000..55ac35b45
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_jpeg.h
@@ -0,0 +1,654 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_jpeg.h
+  * @author  MCD Application Team
+  * @brief   Header file of JPEG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_JPEG_H
+#define STM32N6xx_HAL_JPEG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (JPEG)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup JPEG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup JPEG_Exported_Types JPEG Exported Types
+  * @{
+  */
+
+/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
+  * @brief  JPEG encoding configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t ColorSpace;               /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
+                                           This parameter can be a value of @ref JPEG_ColorSpace */
+
+  uint32_t ChromaSubsampling;        /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
+                                           This parameter can be a value of @ref JPEG_ChromaSubsampling */
+
+  uint32_t ImageHeight;              /*!< Image height : number of lines */
+
+  uint32_t ImageWidth;               /*!< Image width : number of pixels per line */
+
+  uint32_t ImageQuality;             /*!< Quality of the JPEG encoding : from 1 to 100 */
+
+} JPEG_ConfTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
+  * @brief  HAL JPEG State structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_JPEG_STATE_RESET              = 0x00U,  /*!< JPEG not yet initialized or disabled  */
+  HAL_JPEG_STATE_READY              = 0x01U,  /*!< JPEG initialized and ready for use    */
+  HAL_JPEG_STATE_BUSY               = 0x02U,  /*!< JPEG internal processing is ongoing   */
+  HAL_JPEG_STATE_BUSY_ENCODING      = 0x03U,  /*!< JPEG encoding processing is ongoing   */
+  HAL_JPEG_STATE_BUSY_DECODING      = 0x04U,  /*!< JPEG decoding processing is ongoing   */
+  HAL_JPEG_STATE_TIMEOUT            = 0x05U,  /*!< JPEG timeout state                    */
+  HAL_JPEG_STATE_ERROR              = 0x06U   /*!< JPEG error state                      */
+} HAL_JPEG_STATETypeDef;
+
+/**
+  * @}
+  */
+
+
+/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
+  * @brief  JPEG handle Structure definition
+  * @{
+  */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+typedef struct __JPEG_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
+{
+  JPEG_TypeDef             *Instance;        /*!< JPEG peripheral register base address */
+
+  JPEG_ConfTypeDef         Conf;             /*!< Current JPEG encoding/decoding parameters */
+
+  uint8_t                  *pJpegInBuffPtr;  /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
+
+  uint8_t                  *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
+
+  __IO uint32_t            JpegInCount;      /*!< Internal Counter of input data */
+
+  __IO uint32_t            JpegOutCount;     /*!< Internal Counter of output data */
+
+  uint32_t                 InDataLength;     /*!< Input Buffer Length in Bytes */
+
+  uint32_t                 OutDataLength;    /*!< Output Buffer Length in Bytes */
+
+  DMA_HandleTypeDef        *hdmain;          /*!< JPEG In DMA handle parameters */
+
+  DMA_HandleTypeDef        *hdmaout;         /*!< JPEG Out DMA handle parameters */
+
+  uint8_t                  CustomQuanTable;  /*!< If set to 1 specify that user customized quantization tables are used */
+
+  uint8_t                  *QuantTable0;     /*!< Basic Quantization Table for component 0 */
+
+  uint8_t                  *QuantTable1;     /*!< Basic Quantization Table for component 1 */
+
+  uint8_t                  *QuantTable2;     /*!< Basic Quantization Table for component 2 */
+
+  uint8_t                  *QuantTable3;     /*!< Basic Quantization Table for component 3 */
+
+  HAL_LockTypeDef          Lock;             /*!< JPEG locking object */
+
+  __IO  HAL_JPEG_STATETypeDef State;         /*!< JPEG peripheral state */
+
+  __IO  uint32_t           ErrorCode;        /*!< JPEG Error code */
+
+  __IO uint32_t Context;                     /*!< JPEG Internal context */
+
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+  void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg,
+                            JPEG_ConfTypeDef *pInfo);  /*!< JPEG Info ready callback      */
+  void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef
+                             *hjpeg);                          /*!< JPEG Encode complete callback */
+  void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef
+                             *hjpeg);                          /*!< JPEG Decode complete callback */
+  void (*ErrorCallback)(struct __JPEG_HandleTypeDef
+                        *hjpeg);                               /*!< JPEG Error callback           */
+  void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg,
+                          uint32_t NbDecodedData);     /*!< JPEG Get Data callback        */
+  void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
+                            uint32_t OutDataLength);   /*!< JPEG Data ready callback */
+
+  void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg);                            /*!< JPEG Msp Init callback  */
+  void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef
+                             *hjpeg);                          /*!< JPEG Msp DeInit callback  */
+
+
+#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */
+
+
+} JPEG_HandleTypeDef;
+/**
+  * @}
+  */
+
+
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+/** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition
+  * @brief  HAL JPEG Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_JPEG_ENCODE_CPLT_CB_ID    = 0x01U,    /*!< JPEG Encode Complete callback ID */
+  HAL_JPEG_DECODE_CPLT_CB_ID    = 0x02U,    /*!< JPEG Decode Complete callback ID */
+  HAL_JPEG_ERROR_CB_ID          = 0x03U,    /*!< JPEG Error callback ID           */
+
+  HAL_JPEG_MSPINIT_CB_ID        = 0x04U,    /*!< JPEG MspInit callback ID         */
+  HAL_JPEG_MSPDEINIT_CB_ID      = 0x05U     /*!< JPEG MspDeInit callback ID       */
+
+} HAL_JPEG_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition
+  * @brief  HAL JPEG Callback pointer definition
+  * @{
+  */
+typedef  void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg);    /*!< pointer to a common JPEG callback function */
+typedef  void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
+                                                JPEG_ConfTypeDef *pInfo);  /*!< pointer to an Info ready JPEG callback function */
+typedef  void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,
+                                              uint32_t NbDecodedData);     /*!< pointer to a Get data JPEG callback function */
+typedef  void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,
+                                                uint32_t OutDataLength);  /*!< pointer to a Data ready JPEG callback function */
+/**
+  * @}
+  */
+
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup JPEG_Exported_Constants JPEG Exported Constants
+  * @{
+  */
+
+/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
+  * @brief  JPEG Error Code definition
+  * @{
+  */
+
+#define  HAL_JPEG_ERROR_NONE        ((uint32_t)0x00000000U)    /*!< No error             */
+#define  HAL_JPEG_ERROR_HUFF_TABLE  ((uint32_t)0x00000001U)    /*!< HUffman Table programming error */
+#define  HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)    /*!< Quantization Table programming error */
+#define  HAL_JPEG_ERROR_DMA         ((uint32_t)0x00000004U)    /*!< DMA transfer error   */
+#define  HAL_JPEG_ERROR_TIMEOUT     ((uint32_t)0x00000008U)    /*!< Timeout error        */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+#define  HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
+  * @brief  JPEG Quantization Table Size
+  * @{
+  */
+#define JPEG_QUANT_TABLE_SIZE  ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes  */
+/**
+  * @}
+  */
+
+
+/** @defgroup JPEG_ColorSpace JPEG ColorSpace
+  * @brief  JPEG Color Space
+  * @{
+  */
+#define JPEG_GRAYSCALE_COLORSPACE     ((uint32_t)0x00000000U)
+#define JPEG_YCBCR_COLORSPACE         JPEG_CONFR1_COLORSPACE_0
+#define JPEG_CMYK_COLORSPACE          JPEG_CONFR1_COLORSPACE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling
+  * @brief  JPEG Chrominance Sampling
+  * @{
+  */
+#define JPEG_444_SUBSAMPLING     ((uint32_t)0x00000000U)   /*!< Chroma Subsampling 4:4:4 */
+#define JPEG_420_SUBSAMPLING     ((uint32_t)0x00000001U)   /*!< Chroma Subsampling 4:2:0 */
+#define JPEG_422_SUBSAMPLING     ((uint32_t)0x00000002U)   /*!< Chroma Subsampling 4:2:2 */
+
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_ImageQuality JPEG Image Quality
+  * @brief  JPEG Min and Max Image Quality
+  * @{
+  */
+#define JPEG_IMAGE_QUALITY_MIN     ((uint32_t)1U)     /*!< Minimum JPEG quality */
+#define JPEG_IMAGE_QUALITY_MAX     ((uint32_t)100U)   /*!< Maximum JPEG quality */
+
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
+  * @brief JPEG Interrupt definition
+  * @{
+  */
+#define JPEG_IT_IFT     ((uint32_t)JPEG_CR_IFTIE)   /*!< Input FIFO Threshold Interrupt */
+#define JPEG_IT_IFNF    ((uint32_t)JPEG_CR_IFNFIE)  /*!< Input FIFO Not Full Interrupt */
+#define JPEG_IT_OFT     ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Threshold Interrupt */
+#define JPEG_IT_OFNE    ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Not Empty Interrupt */
+#define JPEG_IT_EOC     ((uint32_t)JPEG_CR_EOCIE)   /*!< End of Conversion Interrupt */
+#define JPEG_IT_HPD     ((uint32_t)JPEG_CR_HPDIE)   /*!< Header Parsing Done Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Flag_definition JPEG Flag definition
+  * @brief JPEG Flags definition
+  * @{
+  */
+#define JPEG_FLAG_IFTF     ((uint32_t)JPEG_SR_IFTF)   /*!< Input FIFO is not full and is below its threshold flag */
+#define JPEG_FLAG_IFNFF    ((uint32_t)JPEG_SR_IFNFF)  /*!< Input FIFO Not Full Flag, a data can be written */
+#define JPEG_FLAG_OFTF     ((uint32_t)JPEG_SR_OFTF)   /*!< Output FIFO is not empty and has reach its threshold */
+#define JPEG_FLAG_OFNEF    ((uint32_t)JPEG_SR_OFNEF)  /*!< Output FIFO is not empty, a data is available  */
+#define JPEG_FLAG_EOCF     ((uint32_t)JPEG_SR_EOCF)   /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO  */
+#define JPEG_FLAG_HPDF     ((uint32_t)JPEG_SR_HPDF)   /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated  */
+#define JPEG_FLAG_COF      ((uint32_t)JPEG_SR_COF)    /*!< JPEG Codec operation on going  flag*/
+
+#define JPEG_FLAG_ALL      ((uint32_t)0x000000FEU)     /*!< JPEG Codec All previous flag*/
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
+  * @brief JPEG process pause, resume definition
+  * @{
+  */
+#define JPEG_PAUSE_RESUME_INPUT          ((uint32_t)0x00000001U)     /*!< Pause/Resume Input FIFO Xfer*/
+#define JPEG_PAUSE_RESUME_OUTPUT         ((uint32_t)0x00000002U)     /*!< Pause/Resume Output FIFO Xfer*/
+#define JPEG_PAUSE_RESUME_INPUT_OUTPUT   ((uint32_t)0x00000003U)     /*!< Pause/Resume Input and Output FIFO Xfer*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup JPEG_Exported_Macros JPEG Exported Macros
+  * @{
+  */
+
+/** @brief Reset JPEG handle state
+  * @param  __HANDLE__ specifies the JPEG handle.
+  * @retval None
+  */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;\
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                      }while(0)
+#else
+#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+
+/**
+  * @brief  Enable the JPEG peripheral.
+  * @param  __HANDLE__ specifies the JPEG handle.
+  * @retval None
+  */
+#define __HAL_JPEG_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  JPEG_CR_JCEN)
+
+/**
+  * @brief Disable the JPEG peripheral.
+  * @param  __HANDLE__ specifies the JPEG handle.
+  * @retval None
+  */
+#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~JPEG_CR_JCEN)
+
+
+/**
+  * @brief  Check the specified JPEG status flag.
+  * @param  __HANDLE__ specifies the JPEG handle.
+  * @param  __FLAG__  specifies the flag to check
+  *         This parameter can be one of the following values:
+  *         @arg JPEG_FLAG_IFTF  : The input FIFO is not full and is below its threshold flag
+  *         @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
+  *         @arg JPEG_FLAG_OFTF  : The output FIFO is not empty and has reach its threshold
+  *         @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
+  *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process
+  *                                and than last data has been sent to the output FIFO
+  *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers
+  *                                and the internal registers have been updated
+  *         @arg JPEG_FLAG_COF   : JPEG Codec operation on going  flag
+  *
+  * @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
+  */
+
+#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified JPEG status flag.
+  * @param  __HANDLE__ specifies the JPEG handle.
+  * @param  __FLAG__  specifies the flag to clear
+  *         This parameter can be one of the following values:
+  *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process
+  *                                and than last data has been sent to the output FIFO
+  *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers
+  * @retval None
+  */
+
+#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->CFR |= ((__FLAG__) &\
+                                                      (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
+
+
+/**
+  * @brief  Enable Interrupt.
+  * @param   __HANDLE__ specifies the JPEG handle.
+  * @param  __INTERRUPT__  specifies the interrupt to enable
+  *         This parameter can be one of the following values:
+  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
+  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
+  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
+  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
+  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
+  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
+  *
+  * @retval No return
+  */
+#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
+
+/**
+  * @brief  Disable Interrupt.
+  * @param   __HANDLE__ specifies the JPEG handle.
+  * @param  __INTERRUPT__ specifies the interrupt to disable
+  *         This parameter can be one of the following values:
+  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
+  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
+  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
+  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
+  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
+  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
+  *
+  * @note    To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
+  *          located in the same IT enable register (CR register).
+  * @retval  No return
+  */
+#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
+
+
+/**
+  * @brief  Get Interrupt state.
+  * @param   __HANDLE__ specifies the JPEG handle.
+  * @param  __INTERRUPT__  specifies the interrupt to check
+  *         This parameter can be one of the following values:
+  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt
+  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt
+  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt
+  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt
+  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt
+  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt
+  *
+  * @retval returns The new state of __INTERRUPT__ (Enabled or disabled)
+  */
+#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__)     ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup JPEG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup JPEG_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
+HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
+void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
+void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
+
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,
+                                            pJPEG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,
+                                                     pJPEG_InfoReadyCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg);
+
+HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg);
+
+HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,
+                                                     pJPEG_DataReadyCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg);
+
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup JPEG_Exported_Functions_Group2
+  * @{
+  */
+/* Encoding/Decoding Configuration functions  ********************************/
+HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, const JPEG_ConfTypeDef *pConf);
+HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
+HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
+HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
+HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,
+                                              uint8_t *QTable2, uint8_t *QTable3);
+
+/**
+  * @}
+  */
+
+/** @addtogroup JPEG_Exported_Functions_Group3
+  * @{
+  */
+/* JPEG processing functions  **************************************/
+HAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+                                   uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
+HAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+                                   uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout);
+HAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+                                      uint8_t *pDataOut, uint32_t OutDataLength);
+HAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+                                      uint8_t *pDataOutMCU, uint32_t OutDataLength);
+HAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+                                       uint8_t *pDataOut, uint32_t OutDataLength);
+HAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+                                       uint8_t *pDataOutMCU, uint32_t OutDataLength);
+HAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
+HAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
+void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
+void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
+HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
+
+/**
+  * @}
+  */
+
+/** @addtogroup JPEG_Exported_Functions_Group4
+  * @{
+  */
+/* JPEG Decode/Encode callback functions  ********************************************************/
+void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
+void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
+void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
+void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
+void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
+void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
+
+/**
+  * @}
+  */
+
+/** @addtogroup JPEG_Exported_Functions_Group5
+  * @{
+  */
+/* JPEG IRQ handler management  ******************************************************/
+void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
+
+/**
+  * @}
+  */
+
+/** @addtogroup JPEG_Exported_Functions_Group6
+  * @{
+  */
+/* Peripheral State and Error functions  ************************************************/
+HAL_JPEG_STATETypeDef  HAL_JPEG_GetState(const JPEG_HandleTypeDef *hjpeg);
+uint32_t               HAL_JPEG_GetError(const JPEG_HandleTypeDef *hjpeg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup JPEG_Private_Types JPEG Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup JPEG_Private_Defines JPEG Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup JPEG_Private_Variables JPEG Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup JPEG_Private_Constants JPEG Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup JPEG_Private_Macros JPEG Private Macros
+  * @{
+  */
+
+#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
+                                                ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
+                                                ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
+
+#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
+
+#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
+                                        ((COLORSPACE) == JPEG_YCBCR_COLORSPACE)     || \
+                                        ((COLORSPACE) == JPEG_CMYK_COLORSPACE))
+
+#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
+                                           ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
+                                           ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup JPEG_Private_Functions JPEG Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* JPEG */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_JPEG_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_lptim.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_lptim.h
new file mode 100644
index 000000000..963faa87d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_lptim.h
@@ -0,0 +1,1274 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_lptim.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPTIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_LPTIM_H
+#define STM32N6xx_HAL_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32n6xx_ll_lptim.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
+
+/** @addtogroup LPTIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
+  * @{
+  */
+#define LPTIM_EXTI_LINE_LPTIM1  EXTI_IMR2_IM52  /*!< External interrupt line 52 Connected to the LPTIM1 EXTI Line */
+#define LPTIM_EXTI_LINE_LPTIM2  EXTI_IMR2_IM53  /*!< External interrupt line 53 Connected to the LPTIM2 EXTI Line */
+#define LPTIM_EXTI_LINE_LPTIM3  EXTI_IMR2_IM55  /*!< External interrupt line 55 Connected to the LPTIM3 EXTI Line */
+#define LPTIM_EXTI_LINE_LPTIM4  EXTI_IMR2_IM57  /*!< External interrupt line 57 Connected to the LPTIM4 EXTI Line */
+#define LPTIM_EXTI_LINE_LPTIM5  EXTI_IMR2_IM58  /*!< External interrupt line 58 Connected to the LPTIM5 EXTI Line */
+
+/**
+  * @brief  LPTIM Clock configuration definition
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Selects the clock source.
+                           This parameter can be a value of @ref LPTIM_Clock_Source   */
+
+  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
+                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */
+
+} LPTIM_ClockConfigTypeDef;
+
+/**
+  * @brief  LPTIM Clock configuration definition
+  */
+typedef struct
+{
+  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
+                           if the ULPTIM input is selected.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           Note: If the polarity is configured on 'both edges', an auxiliary clock
+                           (one of the Low power oscillator) must be active.
+                           This parameter can be a value of @ref LPTIM_Clock_Polarity */
+
+  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
+                           Note: This parameter is used only when Ultra low power clock source is used.
+                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
+
+} LPTIM_ULPClockConfigTypeDef;
+
+/**
+  * @brief  LPTIM Trigger configuration definition
+  */
+typedef struct
+{
+  uint32_t Source;        /*!< Selects the Trigger source.
+                          This parameter can be a value of @ref LPTIM_Trigger_Source */
+
+  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
+
+  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
+                          Note: This parameter is used only when an external trigger is used.
+                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
+} LPTIM_TriggerConfigTypeDef;
+
+/**
+  * @brief  LPTIM Initialization Structure definition
+  */
+typedef struct
+{
+  LPTIM_ClockConfigTypeDef     Clock;             /*!< Specifies the clock parameters */
+
+  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
+
+  LPTIM_TriggerConfigTypeDef   Trigger;           /*!< Specifies the Trigger parameters */
+
+  uint32_t                     Period;            /*!< Specifies the period value to be loaded into the active
+                                                  Auto-Reload Register at the next update event.
+                                                  This parameter can be a number between
+                                                  Min_Data = 0x0001 and Max_Data = 0xFFFF.  */
+
+  uint32_t                     UpdateMode;        /*!< Specifies whether the update of the autoreload and the compare
+                                                  values is done immediately or after the end of current period.
+                                                  This parameter can be a value of @ref LPTIM_Updating_Mode */
+
+  uint32_t                     CounterSource;     /*!< Specifies whether the counter is incremented each internal event
+                                                  or each external event.
+                                                  This parameter can be a value of @ref LPTIM_Counter_Source */
+
+  uint32_t                     Input1Source;      /*!< Specifies source selected for input1 (GPIO or comparator output).
+                                                  This parameter can be a value of @ref LPTIM_Input1_Source */
+
+  uint32_t                     Input2Source;      /*!< Specifies source selected for input2 (GPIO or comparator output).
+                                                  Note: This parameter is used only for encoder feature so is used only
+                                                  for LPTIM1 instance.
+                                                  This parameter can be a value of @ref LPTIM_Input2_Source */
+
+  uint32_t                     RepetitionCounter;/*!< Specifies the repetition counter value.
+                                                  Each time the RCR downcounter reaches zero, an update event is
+                                                  generated and counting restarts from the RCR value (N).
+                                                  Note: When using repetition counter the UpdateMode field must be
+                                                        set to LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable
+                                                        behavior may occur.
+                                                  This parameter must be a number between Min_Data = 0x00 and
+                                                  Max_Data = 0xFF. */
+} LPTIM_InitTypeDef;
+
+/**
+  * @brief  LPTIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Pulse;                 /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                       This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+  uint32_t OCPolarity;            /*!< Specifies the output polarity.
+                                       This parameter can be a value of @ref LPTIM_Output_Compare_Polarity */
+} LPTIM_OC_ConfigTypeDef;
+
+/**
+  * @brief  LPTIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t ICInputSource; /*!< Specifies source selected for IC channel.
+                               This parameter can be a value of @ref LPTIM_Input_Capture_Source */
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref LPTIM_Input_Capture_Prescaler */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref LPTIM_Input_Capture_Polarity */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref LPTIM_Input_Capture_Filter */
+} LPTIM_IC_ConfigTypeDef;
+
+/**
+  * @brief  HAL LPTIM State structure definition
+  */
+typedef enum
+{
+  HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
+  HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
+} HAL_LPTIM_StateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_LPTIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_LPTIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_LPTIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_LPTIM_ActiveChannel;
+
+/**
+  * @brief  LPTIM Channel States definition
+  */
+typedef enum
+{
+  HAL_LPTIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< LPTIM Channel initial state                         */
+  HAL_LPTIM_CHANNEL_STATE_READY             = 0x01U,    /*!< LPTIM Channel ready for use                         */
+  HAL_LPTIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the LPTIM channel */
+} HAL_LPTIM_ChannelStateTypeDef;
+
+/**
+  * @brief  LPTIM handle Structure definition
+  */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+typedef struct __LPTIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+{
+  LPTIM_TypeDef                 *Instance;         /*!< Register base address     */
+
+  LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */
+
+  HAL_LPTIM_ActiveChannel        Channel;          /*!< Active channel            */
+
+  DMA_HandleTypeDef             *hdma[3];          /*!< DMA Handlers array, This array is accessed by a @ref LPTIM_DMA_Handle_index */
+
+  HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */
+
+  HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */
+
+  __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
+
+  __IO  HAL_LPTIM_ChannelStateTypeDef   ChannelState[2];  /*!< LPTIM channel operation state                       */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */
+  void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */
+  void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */
+  void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */
+  void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */
+  void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */
+  void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */
+  void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */
+  void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */
+  void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Update event detection Callback              */
+  void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Repetition counter register write complete Callback */
+  void (* UpdateEventHalfCpltCallback)(struct __LPTIM_HandleTypeDef *hlptim);/*!< Update event half complete detection Callback */
+  void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim);              /*!< LPTIM Error Callback                         */
+  void (* IC_CaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim);         /*!< Input capture Callback                       */
+  void (* IC_CaptureHalfCpltCallback)(struct __LPTIM_HandleTypeDef *htim);   /*!< Input Capture half complete Callback         */
+  void (* IC_OverCaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim);     /*!< Over capture Callback                        */
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+} LPTIM_HandleTypeDef;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL LPTIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */
+  HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */
+  HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */
+  HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */
+  HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */
+  HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */
+  HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */
+  HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */
+  HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */
+  HAL_LPTIM_UPDATE_EVENT_CB_ID      = 0x09U,   /*!< Update event detection Callback ID               */
+  HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU,   /*!< Repetition counter register write complete Callback ID */
+  HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID = 0x0BU,   /*!< Update event half complete detection Callback ID */
+  HAL_LPTIM_ERROR_CB_ID             = 0x0CU,   /*!< LPTIM Error Callback ID                          */
+  HAL_LPTIM_IC_CAPTURE_CB_ID        = 0x0DU,   /*!< Input capture Callback ID                        */
+  HAL_LPTIM_IC_CAPTURE_HALF_CB_ID   = 0x0EU,   /*!< Input capture half complete Callback ID          */
+  HAL_LPTIM_OVER_CAPTURE_CB_ID      = 0x0FU,   /*!< Over capture Callback ID                         */
+} HAL_LPTIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */
+
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
+  * @{
+  */
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U
+#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
+  * @{
+  */
+#define LPTIM_PRESCALER_DIV1                    0x00000000U
+#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
+#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
+#define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
+#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
+#define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
+  * @{
+  */
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
+  * @{
+  */
+#define LPTIM_CLOCKPOLARITY_RISING              0x00000000U
+#define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
+  * @{
+  */
+#define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU
+#define LPTIM_TRIGSOURCE_0                      0x00000000U
+#define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0
+#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
+#define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
+#define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
+  * @{
+  */
+#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
+#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
+#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
+  * @{
+  */
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U
+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
+  * @{
+  */
+
+#define LPTIM_UPDATE_IMMEDIATE                  0x00000000U
+#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
+  * @{
+  */
+
+#define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U
+#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
+  * @{
+  */
+
+#define LPTIM_INPUT1SOURCE_GPIO         0x00000000UL          /*!< For LPTIM1 and LPTIM2 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
+  * @{
+  */
+
+#define LPTIM_INPUT2SOURCE_GPIO         0x00000000UL          /*!< For LPTIM1 and LPTIM2 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
+  * @{
+  */
+
+#define LPTIM_FLAG_CC1O                          LPTIM_ISR_CC1OF
+#define LPTIM_FLAG_CC2O                          LPTIM_ISR_CC2OF
+#define LPTIM_FLAG_CC1                           LPTIM_ISR_CC1IF
+#define LPTIM_FLAG_CC2                           LPTIM_ISR_CC2IF
+#define LPTIM_FLAG_CMP1OK                        LPTIM_ISR_CMP1OK
+#define LPTIM_FLAG_CMP2OK                        LPTIM_ISR_CMP2OK
+#define LPTIM_FLAG_DIEROK                        LPTIM_ISR_DIEROK
+#define LPTIM_FLAG_REPOK                         LPTIM_ISR_REPOK
+#define LPTIM_FLAG_UPDATE                        LPTIM_ISR_UE
+#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
+#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
+#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
+#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
+#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_DMA_sources LPTIM DMA Sources
+  * @{
+  */
+#define LPTIM_DMA_UPDATE                     LPTIM_DIER_UEDE         /*!< DMA request is triggered by the update event */
+#define LPTIM_DMA_CC1                        LPTIM_DIER_CC1DE        /*!< DMA request is triggered by the capture 1 event */
+#define LPTIM_DMA_CC2                        LPTIM_DIER_CC2DE        /*!< DMA request is triggered by the capture 2 event */
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_DMA_Handle_index LPTIM DMA Handle Index
+  * @{
+  */
+#define LPTIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define LPTIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Update event 1 DMA request */
+#define LPTIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Update event 2 DMA request */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
+  * @{
+  */
+#define LPTIM_IT_CC1O                            LPTIM_DIER_CC1OIE
+#define LPTIM_IT_CC2O                            LPTIM_DIER_CC2OIE
+#define LPTIM_IT_CC1                             LPTIM_DIER_CC1IE
+#define LPTIM_IT_CC2                             LPTIM_DIER_CC2IE
+#define LPTIM_IT_CMP1OK                          LPTIM_DIER_CMP1OKIE
+#define LPTIM_IT_CMP2OK                          LPTIM_DIER_CMP2OKIE
+#define LPTIM_IT_REPOK                           LPTIM_DIER_REPOKIE
+#define LPTIM_IT_UPDATE                          LPTIM_DIER_UEIE
+#define LPTIM_IT_DOWN                            LPTIM_DIER_DOWNIE
+#define LPTIM_IT_UP                              LPTIM_DIER_UPIE
+#define LPTIM_IT_ARROK                           LPTIM_DIER_ARROKIE
+#define LPTIM_IT_EXTTRIG                         LPTIM_DIER_EXTTRIGIE
+#define LPTIM_IT_ARRM                            LPTIM_DIER_ARRMIE
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Channel LPTIM Channel
+  * @{
+  */
+#define LPTIM_CHANNEL_1                      LL_LPTIM_CHANNEL_CH1                          /*!< Capture/compare channel 1 identifier      */
+#define LPTIM_CHANNEL_2                      LL_LPTIM_CHANNEL_CH2                          /*!< Capture/compare channel 2 identifier      */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Output_Compare_Polarity LPTIM Output Compare Polarity
+  * @{
+  */
+#define LPTIM_OCPOLARITY_HIGH                    0x00000000U                    /*!< Capture/Compare output polarity */
+#define LPTIM_OCPOLARITY_LOW                     0x00000001U                    /*!< Capture/Compare output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input_Capture_Prescaler LPTIM Input Capture Prescaler
+  * @{
+  */
+#define LPTIM_ICPSC_DIV1                          0x00000000UL                                  /*!< Capture performed each time an edge is detected on the capture input */
+#define LPTIM_ICPSC_DIV2                          LPTIM_CCMR1_IC1PSC_0                          /*!< Capture performed once every 2 events                                */
+#define LPTIM_ICPSC_DIV4                          LPTIM_CCMR1_IC1PSC_1                          /*!< Capture performed once every 4 events                                */
+#define LPTIM_ICPSC_DIV8                         (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1)    /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input_Capture_Polarity LPTIM Input Capture Polarity
+  * @{
+  */
+#define LPTIM_ICPOLARITY_RISING                    0x00000000UL                              /*!< Capture/Compare input rising polarity */
+#define LPTIM_ICPOLARITY_FALLING                   LPTIM_CCMR1_CC1P_0                        /*!< Capture/Compare input falling polarity */
+#define LPTIM_ICPOLARITY_RISING_FALLING           (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1)    /*!< Capture/Compare input rising and falling polarities */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input_Capture_Filter LPTIM Input Capture Filter
+  * @{
+  */
+#define LPTIM_ICFLT_CLOCK_DIV1                     0x00000000UL                            /*!< any external input capture signal level change is considered as a valid transition */
+#define LPTIM_ICFLT_CLOCK_DIV2                     LPTIM_CCMR1_IC1F_0                      /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
+#define LPTIM_ICFLT_CLOCK_DIV4                     LPTIM_CCMR1_IC1F_1                      /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
+#define LPTIM_ICFLT_CLOCK_DIV8                    (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1)  /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Input_Capture_Source LPTIM Input Capture Source
+  * @{
+  */
+#define LPTIM_IC1SOURCE_GPIO                       0x00000000UL                                  /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+#define LPTIM_IC1SOURCE_I3C1_IBIACK                LPTIM_CFGR2_IC1SEL_0                          /*!< For LPTIM2 and LPTIM3 */
+#define LPTIM_IC2SOURCE_GPIO                       0x00000000UL                                  /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+#define LPTIM_IC2SOURCE_LSI                        LPTIM_CFGR2_IC2SEL_0                          /*!< For LPTIM1 */
+#define LPTIM_IC2SOURCE_LSE                        LPTIM_CFGR2_IC2SEL_1                          /*!< For LPTIM1 */
+#define LPTIM_IC2SOURCE_HSI_1024                   LPTIM_CFGR2_IC2SEL_0                          /*!< For LPTIM2 */
+#define LPTIM_IC2SOURCE_MSI_128                    LPTIM_CFGR2_IC2SEL_1                          /*!< For LPTIM2 */
+#define LPTIM_IC2SOURCE_I3C2_IBIACK                (LPTIM_CFGR2_IC2SEL_1 | LPTIM_CFGR2_IC2SEL_0) /*!< For LPTIM2 and LPTIM3 */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @brief Reset LPTIM handle state.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval None
+  */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                        (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
+                                                        (__HANDLE__)->ChannelState[0]  = HAL_LPTIM_CHANNEL_STATE_RESET;\
+                                                        (__HANDLE__)->ChannelState[1]  = HAL_LPTIM_CHANNEL_STATE_RESET;\
+                                                        (__HANDLE__)->MspInitCallback   = NULL;                  \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;                  \
+                                                      } while(0)
+#else
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                              \
+                                                        (__HANDLE__)->State            = HAL_LPTIM_STATE_RESET;        \
+                                                        (__HANDLE__)->ChannelState[0]  = HAL_LPTIM_CHANNEL_STATE_RESET;\
+                                                        (__HANDLE__)->ChannelState[1]  = HAL_LPTIM_CHANNEL_STATE_RESET;\
+                                                      } while(0)
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the LPTIM peripheral.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
+
+/**
+  * @brief  Disable the LPTIM peripheral.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC1E) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC2E) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Start the LPTIM peripheral in Continuous mode.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
+/**
+  * @brief  Start the LPTIM peripheral in single mode.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
+
+/**
+  * @brief  Reset the LPTIM Counter register in synchronous mode.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)
+
+/**
+  * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval None
+  */
+#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)
+
+/**
+  * @brief  Write the passed parameter in the Autoreload register.
+  * @param  __HANDLE__ LPTIM handle
+  * @param  __VALUE__ Autoreload value
+  * @retval None
+  * @note   The ARR register can only be modified when the LPTIM instance is enabled.
+  */
+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
+
+/**
+  * @brief  Write the passed parameter in the Compare register.
+  * @param  __HANDLE__ LPTIM handle
+  * @param  __VALUE__ Compare value
+  * @param  __CHANNEL__ TIM Channel to be configured
+  * @retval None
+  * @note   The CCRx registers can only be modified when the LPTIM instance is enabled.
+  */
+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __CHANNEL__, __VALUE__) \
+  (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__VALUE__)) :\
+   ((__CHANNEL__) == LPTIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__VALUE__)) : 0U)
+
+/**
+  * @brief  Write the passed parameter in the Repetition register.
+  * @param  __HANDLE__ LPTIM handle
+  * @param  __VALUE__ Repetition value
+  * @retval None
+  */
+#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->RCR =  (__VALUE__))
+
+/**
+  * @brief  Return the current Repetition value.
+  * @param  __HANDLE__ LPTIM handle
+  * @retval Repetition register value
+  * @note   The RCR register can only be modified when the LPTIM instance is enabled.
+  */
+#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__)  ((__HANDLE__)->Instance->RCR)
+
+/**
+  * @brief  Enable the LPTIM signal input/output on the corresponding pin.
+  * @param  __HANDLE__  LPTIM handle
+  * @param  __CHANNEL__ LPTIM Channels to be enabled.
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval None
+  */
+#define __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(__HANDLE__, __CHANNEL__)                                            \
+  do {                                                        \
+    switch (__CHANNEL__)                                   \
+    {                                                      \
+      case LPTIM_CHANNEL_1:                                \
+        ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC1E); \
+        break;                                             \
+      case LPTIM_CHANNEL_2:                                \
+        ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC2E); \
+        break;                                             \
+      default:                                             \
+        break;                                             \
+    }                                                      \
+  }                                                          \
+  while(0)
+
+/**
+  * @brief  Disable the LPTIM signal input/output on the corresponding pin.
+  * @param  __HANDLE__  LPTIM handle
+  * @param  __CHANNEL__ LPTIM Channels to be disabled.
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval None
+  */
+#define __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(__HANDLE__, __CHANNEL__)                                            \
+  do {                                                         \
+    switch (__CHANNEL__)                                    \
+    {                                                       \
+      case LPTIM_CHANNEL_1:                                 \
+        ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC1E); \
+        break;                                              \
+      case LPTIM_CHANNEL_2:                                 \
+        ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC2E); \
+        break;                                              \
+      default:                                              \
+        break;                                              \
+    }                                                       \
+  }                                                           \
+  while(0)
+
+/**
+  * @brief  Check whether the specified LPTIM flag is set or not.
+  * @param  __HANDLE__ LPTIM handle
+  * @param  __FLAG__ LPTIM flag to check
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_REPOK   : Repetition register update OK Flag.
+  *            @arg LPTIM_FLAG_UPDATE  : Update event Flag.
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMP1OK  : Compare register 1 update OK Flag.
+  *            @arg LPTIM_FLAG_CMP2OK  : Compare register 2 update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CC1     : Capture/Compare 1 interrupt flag.
+  *            @arg LPTIM_FLAG_CC2     : Capture/Compare 2 interrupt flag.
+  *            @arg LPTIM_FLAG_CC1O    : Capture/Compare 1 over-capture flag.
+  *            @arg LPTIM_FLAG_CC2O    : Capture/Compare 2 over-capture flag.
+  *            @arg LPTIM_FLAG_DIEROK  : DMA & interrupt enable update OK flag.
+  * @retval The state of the specified flag (SET or RESET).
+  */
+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the specified LPTIM flag.
+  * @param  __HANDLE__ LPTIM handle.
+  * @param  __FLAG__ LPTIM flag to clear.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_FLAG_REPOK   : Repetition register update OK Flag.
+  *            @arg LPTIM_FLAG_UPDATE  : Update event Flag.
+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
+  *            @arg LPTIM_FLAG_CMP1OK  : Compare register 1 update OK Flag.
+  *            @arg LPTIM_FLAG_CMP2OK  : Compare register 2 update OK Flag.
+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
+  *            @arg LPTIM_FLAG_CC1     : Capture/Compare 1 interrupt flag.
+  *            @arg LPTIM_FLAG_CC2     : Capture/Compare 2 interrupt flag.
+  *            @arg LPTIM_FLAG_CC1O    : Capture/Compare 1 over-capture flag.
+  *            @arg LPTIM_FLAG_CC2O    : Capture/Compare 2 over-capture flag.
+  *            @arg LPTIM_FLAG_DIEROK  : DMA & interrupt enable update OK flag.
+  * @retval None.
+  */
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
+
+/**
+  * @brief  Enable the specified LPTIM interrupt.
+  * @param  __HANDLE__ LPTIM handle.
+  * @param  __INTERRUPT__ LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_REPOK   : Repetition register update OK Interrupt.
+  *            @arg LPTIM_IT_UPDATE  : Update event register Interrupt.
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMP1OK  : Compare register 1 update OK Interrupt.
+  *            @arg LPTIM_IT_CMP2OK  : Compare register 2 update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CC1     : Capture/Compare 1 interrupt Interrupt.
+  *            @arg LPTIM_IT_CC2     : Capture/Compare 2 interrupt Interrupt.
+  *            @arg LPTIM_IT_CC1O    : Capture/Compare 1 over-capture Interrupt.
+  *            @arg LPTIM_IT_CC2O    : Capture/Compare 2 over-capture Interrupt.
+  * @retval None.
+  * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is enabled.
+  */
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER  |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified LPTIM interrupt.
+  * @param  __HANDLE__ LPTIM handle.
+  * @param  __INTERRUPT__ LPTIM interrupt to set.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_REPOK   : Repetition register update OK Interrupt.
+  *            @arg LPTIM_IT_UPDATE  : Update event register Interrupt.
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMP1OK  : Compare register 1 update OK Interrupt.
+  *            @arg LPTIM_IT_CMP2OK  : Compare register 2 update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CC1     : Capture/Compare 1 interrupt Interrupt.
+  *            @arg LPTIM_IT_CC2     : Capture/Compare 2 interrupt Interrupt.
+  *            @arg LPTIM_IT_CC1O    : Capture/Compare 1 over-capture Interrupt.
+  *            @arg LPTIM_IT_CC2O    : Capture/Compare 2 over-capture Interrupt.
+  * @retval None.
+  * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is enabled.
+  */
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER  &= (~(__INTERRUPT__)))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the LPTIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_DMA_UPDATE: Update DMA request
+  *            @arg LPTIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg LPTIM_DMA_CC2:  Capture/Compare 2 DMA request
+  * @retval None
+  */
+#define __HAL_LPTIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the LPTIM Handle.
+  * @param  __DMA__ specifies the LPTIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_DMA_UPDATE: Update DMA request
+  *            @arg LPTIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg LPTIM_DMA_CC2:   Capture/Compare 2 DMA request
+  * @retval None
+  */
+#define __HAL_LPTIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/**
+  * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
+  * @param  __HANDLE__ LPTIM handle.
+  * @param  __INTERRUPT__ LPTIM interrupt to check.
+  *            This parameter can be a value of:
+  *            @arg LPTIM_IT_REPOK   : Repetition register update OK Interrupt.
+  *            @arg LPTIM_IT_UPDATE  : Update event register Interrupt.
+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
+  *            @arg LPTIM_IT_CMP1OK  : Compare register 1 update OK Interrupt.
+  *            @arg LPTIM_IT_CMP2OK  : Compare register 2 update OK Interrupt.
+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
+  *            @arg LPTIM_IT_CC1     : Capture/Compare 1 interrupt Interrupt.
+  *            @arg LPTIM_IT_CC2     : Capture/Compare 2 interrupt Interrupt.
+  *            @arg LPTIM_IT_CC1O    : Capture/Compare 1 over-capture Interrupt.
+  *            @arg LPTIM_IT_CC2O    : Capture/Compare 2 over-capture Interrupt.
+  * @retval Interrupt status.
+  */
+
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER\
+                                                                & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Enable the LPTIM1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()            (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM1)
+
+/**
+  * @brief  Disable the LPTIM1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()           (EXTI->IMR2\
+                                                        &= ~(LPTIM_EXTI_LINE_LPTIM1))
+
+/**
+  * @brief  Enable the LPTIM2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()            (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM2)
+
+/**
+  * @brief  Disable the LPTIM2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()           (EXTI->IMR2\
+                                                        &= ~(LPTIM_EXTI_LINE_LPTIM2))
+
+/**
+  * @brief  Enable the LPTIM3 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT()            (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM3)
+
+/**
+  * @brief  Disable the LPTIM3 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT()           (EXTI->IMR2\
+                                                        &= ~(LPTIM_EXTI_LINE_LPTIM3))
+
+/**
+  * @brief  Enable the LPTIM4 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM4_EXTI_ENABLE_IT()            (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM4)
+
+/**
+  * @brief  Disable the LPTIM4 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM4_EXTI_DISABLE_IT()           (EXTI->IMR2\
+                                                        &= ~(LPTIM_EXTI_LINE_LPTIM4))
+
+/**
+  * @brief  Enable the LPTIM5 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM5_EXTI_ENABLE_IT()            (EXTI->IMR2 |= LPTIM_EXTI_LINE_LPTIM5)
+
+/**
+  * @brief  Disable the LPTIM5 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_LPTIM_LPTIM5_EXTI_DISABLE_IT()           (EXTI->IMR2\
+                                                        &= ~(LPTIM_EXTI_LINE_LPTIM5))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group1
+  *  @brief    Initialization and Configuration functions.
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
+
+/* MSP functions  *************************************************************/
+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group2
+  *  @brief   Start-Stop operation functions.
+  * @{
+  */
+/* Config functions  **********************************************************/
+HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
+                                             uint32_t Channel);
+
+/* Start/Stop operation functions  *********************************************/
+/* ################################# PWM Mode ################################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
+                                          uint32_t Length);
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+
+/* ############################# One Pulse Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+
+/* ############################## Set once Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+
+/* ############################### Encoder Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################# Time out  Mode ##############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout);
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Counter Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim);
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+
+/* ############################## Input Capture Mode ###############################*/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
+                                             uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
+                                         uint32_t Length);
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group3
+  *  @brief  Read operation functions.
+  * @{
+  */
+/* Reading operation functions ************************************************/
+uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Exported_Functions_Group4
+  *  @brief  LPTIM IRQ handler and callback functions.
+  * @{
+  */
+/* LPTIM IRQ functions  *******************************************************/
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
+
+/* CallBack functions  ********************************************************/
+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim);
+void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+                                             pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Group5
+  *  @brief   Peripheral State functions.
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Types LPTIM Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
+  * @{
+  */
+
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
+
+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))
+
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
+
+#define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+
+#define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_PERIOD(__PERIOD__)             ((0x00000001UL <= (__PERIOD__)) &&\
+                                                 ((__PERIOD__) <= 0x0000FFFFUL))
+
+#define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
+
+#define IS_LPTIM_OC_POLARITY(__OCPOLARITY__)    (((__OCPOLARITY__) == LPTIM_OCPOLARITY_LOW) || \
+                                                 ((__OCPOLARITY__) == LPTIM_OCPOLARITY_HIGH))
+#define IS_LPTIM_IC_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == LPTIM_ICPSC_DIV1) ||\
+                                                 ((__PRESCALER__) == LPTIM_ICPSC_DIV2) ||\
+                                                 ((__PRESCALER__) == LPTIM_ICPSC_DIV4) ||\
+                                                 ((__PRESCALER__) == LPTIM_ICPSC_DIV8))
+
+#define IS_LPTIM_IC_POLARITY(__POLARITY__)      (((__POLARITY__) == LPTIM_ICPOLARITY_RISING) || \
+                                                 ((__POLARITY__) == LPTIM_ICPOLARITY_FALLING) ||\
+                                                 ((__POLARITY__) == LPTIM_ICPOLARITY_RISING_FALLING))
+
+#define IS_LPTIM_IC_FILTER(__FILTER__)          (((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV1) ||\
+                                                 ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV2) ||\
+                                                 ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV4) ||\
+                                                 ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV8))
+
+#define IS_LPTIM_REPETITION(__REPETITION__)     ((__REPETITION__) <= 0x000000FFUL)
+
+#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
+  ((((__INSTANCE__) == LPTIM1) &&                        \
+    ((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) )          \
+   ||                                                    \
+   (((__INSTANCE__) == LPTIM2) &&                        \
+    ((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO))           \
+   ||                                                    \
+   (((__INSTANCE__) == LPTIM3) &&                        \
+    ((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)))
+
+#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
+  ((((__INSTANCE__) == LPTIM1) &&                        \
+    ((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) )          \
+   ||                                                    \
+   (((__INSTANCE__) == LPTIM2) &&                        \
+    ((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))           \
+   ||                                                    \
+   (((__INSTANCE__) == LPTIM3) &&                        \
+    ((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)))
+
+#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \
+  ((((__INSTANCE__) == LPTIM1) &&                     \
+    (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO)))         \
+   ||                                                 \
+   (((__INSTANCE__) == LPTIM2) &&                     \
+    (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO)     ||    \
+     ((__SOURCE__) == LPTIM_IC1SOURCE_I3C1_IBIACK)))  \
+   ||                                                 \
+   (((__INSTANCE__) == LPTIM3) &&                     \
+    (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO)  ||       \
+     ((__SOURCE__) == LPTIM_IC1SOURCE_I3C1_IBIACK))))
+
+#define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \
+  ((((__INSTANCE__) == LPTIM1) &&                     \
+    (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) ||        \
+     ((__SOURCE__) == LPTIM_IC2SOURCE_LSI)  ||        \
+     ((__SOURCE__) == LPTIM_IC2SOURCE_LSE)))          \
+   ||                                                 \
+   (((__INSTANCE__) == LPTIM2) &&                     \
+    (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO)     ||    \
+     ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_1024) ||    \
+     ((__SOURCE__) == LPTIM_IC2SOURCE_MSI_128)  ||    \
+     ((__SOURCE__) == LPTIM_IC2SOURCE_I3C2_IBIACK)))  \
+   ||                                                 \
+   (((__INSTANCE__) == LPTIM3) &&                     \
+    (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO)  ||       \
+     ((__SOURCE__) == LPTIM_IC2SOURCE_I3C2_IBIACK))))
+
+#define LPTIM_CHANNEL_STATE_GET(__INSTANCE__, __CHANNEL__)\
+  (((__CHANNEL__) == LPTIM_CHANNEL_1) ? (__INSTANCE__)->ChannelState[0] :\
+   (__INSTANCE__)->ChannelState[1])
+
+#define LPTIM_CHANNEL_STATE_SET(__INSTANCE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__INSTANCE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+   ((__INSTANCE__)->ChannelState[1] = (__CHANNEL_STATE__)))
+
+#define LPTIM_CHANNEL_STATE_SET_ALL(__INSTANCE__,  __CHANNEL_STATE__) do { \
+                                                                           (__INSTANCE__)->ChannelState[0]  =\
+                                                                                                (__CHANNEL_STATE__);  \
+                                                                           (__INSTANCE__)->ChannelState[1]  =\
+                                                                                                (__CHANNEL_STATE__);  \
+                                                                         } while(0)
+
+#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
+  ((((__INSTANCE__) == LPTIM1)  && \
+    (((__CHANNEL__)  == LPTIM_CHANNEL_1) ||  \
+     ((__CHANNEL__)  == LPTIM_CHANNEL_2)))   \
+   ||                                        \
+   (((__INSTANCE__) == LPTIM2)  && \
+    (((__CHANNEL__)  == LPTIM_CHANNEL_1) ||  \
+     ((__CHANNEL__)  == LPTIM_CHANNEL_2)))   \
+   ||                                        \
+   (((__INSTANCE__) == LPTIM3)  && \
+    (((__CHANNEL__)  == LPTIM_CHANNEL_1) ||  \
+     ((__CHANNEL__)  == LPTIM_CHANNEL_2)))   \
+   ||                                        \
+   (((__INSTANCE__) == LPTIM4)  && \
+    (((__CHANNEL__)  == LPTIM_CHANNEL_1))) \
+   ||                                        \
+   (((__INSTANCE__) == LPTIM5)  && \
+    ((__CHANNEL__)  == LPTIM_CHANNEL_1)))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_LPTIM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ltdc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ltdc.h
new file mode 100644
index 000000000..67245ffd7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ltdc.h
@@ -0,0 +1,1134 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_ltdc.h
+  * @author  MCD Application Team
+  * @brief   Header file of LTDC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_LTDC_H
+#define STM32N6xx_HAL_LTDC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (LTDC)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup LTDC LTDC
+  * @brief LTDC HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Types LTDC Exported Types
+  * @{
+  */
+#define MAX_LAYER  2U
+
+/**
+  * @brief  LTDC color structure definition
+  */
+typedef struct
+{
+  uint8_t Blue;                    /*!< Configures the blue value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Green;                   /*!< Configures the green value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Red;                     /*!< Configures the red value.
+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint8_t Reserved;                /*!< Reserved 0xFF */
+} LTDC_ColorTypeDef;
+
+/**
+  * @brief  LTDC Init structure definition
+  */
+typedef struct
+{
+  uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.
+                                                      This parameter can be one value of @ref LTDC_HS_POLARITY */
+
+  uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.
+                                                      This parameter can be one value of @ref LTDC_VS_POLARITY */
+
+  uint32_t            DEPolarity;                /*!< configures the data enable polarity.
+                                                      This parameter can be one of value of @ref LTDC_DE_POLARITY */
+
+  uint32_t            PCPolarity;                /*!< configures the pixel clock polarity.
+                                                      This parameter can be one of value of @ref LTDC_PC_POLARITY */
+
+  uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
+                                                      This parameter must be a number between
+                                                      Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.
+                                                      This parameter must be a number between
+                                                      Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+
+  uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+
+  uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+
+  uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+
+  uint32_t            TotalWidth;                /*!< configures the total width.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+
+  uint32_t            TotalHeigh;                /*!< configures the total height.
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+
+  LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
+} LTDC_InitTypeDef;
+
+/**
+  * @brief  LTDC Layer structure definition
+  */
+typedef struct
+{
+  uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x7FF. */
+
+  uint32_t PixelFormat;                /*!< Specifies the pixel format.
+                                            This parameter can be one of value of @ref LTDC_Pixelformat */
+
+  uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Alpha0;                     /*!< Configures the default alpha value.
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor1 */
+
+  uint32_t BlendingFactor2;            /*!< Select the blending factor 2.
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor2 */
+
+  uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
+
+  uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+
+  uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
+} LTDC_LayerCfgTypeDef;
+
+/**
+  * @brief  LTDC Flexible Layer structure definition
+  */
+typedef struct
+{
+  uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
+
+  uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x7FF. */
+
+  uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t Alpha0;                     /*!< Configures the default alpha value.
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
+
+  uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor1 */
+
+  uint32_t BlendingFactor2;            /*!< Select the blending factor 2.
+                                            This parameter can be one of value of @ref LTDC_BlendingFactor2 */
+
+  uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+
+  uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
+
+  LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
+} LTDC_LayerTypeDef;
+
+/**
+  * @brief  LTDC Flexible ARGB format structure definition
+  */
+typedef struct
+{
+  uint32_t PixelSize;          /*!< Value of ARGB Pixel size. Could be a value of LTDC_ARGB_SIZE
+                                  This parameter can be one of value of @ref LTDC_ARGB_SIZE                     */
+
+  uint32_t AlphaPos;           /*!< Position of the Alpha component inside the pixel memory word (in bits)
+                                  This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x1F. */
+
+  uint32_t RedPos;             /*!< Position of the Red component inside the pixel memory word (in bits)
+                                  This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x1F. */
+
+  uint32_t GreenPos;           /*!< Position of the Green component inside the pixel memory word (in bits)
+                                  This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x1F. */
+
+  uint32_t BluePos;            /*!< Position of the Blue component inside the pixel memory word (in bits)
+                                  This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF.   */
+
+  uint32_t AlphaWidth;         /*!< Width of the Alpha component in bits
+                                  This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF.   */
+
+  uint32_t RedWidth;           /*!< Width of the Red component in bits
+                                  This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF.   */
+
+  uint32_t GreenWidth;         /*!< Width of the Green component in bits
+                                  This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF.   */
+
+  uint32_t BlueWidth;          /*!< Width of the Blue component in bits
+                                  This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF.   */
+} LTDC_FlexARGBTypeDef;
+
+/**
+  * @brief  LTDC Layer Flexible ARGB format structure definition
+  */
+typedef struct
+{
+  LTDC_LayerTypeDef Layer;          /*!< Pointer to LTDC_LayerTypeDef structure     */
+  LTDC_FlexARGBTypeDef FlexARGB;    /*!< Pointer to LTDC_FlexARGBTypeDef structure  */
+  uint32_t ARGBAddress;              /*!< Configures the color frame buffer address  */
+} LTDC_LayerFlexARGBTypeDef;
+
+/**
+  * @brief  LTDC Flexible YUV format structure definition
+  */
+typedef struct
+{
+  uint32_t YUVOrder;             /*!< Y/UV order.
+                                      This parameter can be one of value of @ref LTDC_YUV_ORDER        */
+
+  uint32_t LuminanceOrder;       /*!< Y1/Y2 order.
+                                      This parameter can be one of value of @ref LTDC_LUMINANCE_ORDER  */
+
+  uint32_t ChrominanceOrder;     /*!< U/V order.
+                                      This parameter can be one of value of @ref LTDC_CHROMINANCE_ORDER */
+
+  uint32_t LuminanceRescale;     /*!< Enable or disable luminance rescale.
+                                      This parameter can be one of value of @ref LTDC_LUMINANCE_RANGE   */
+} LTDC_FlexYUVTypeDef;
+
+/**
+  * @brief  LTDC Flexible YUV coplanar structure definition
+  */
+typedef struct
+{
+  LTDC_LayerTypeDef Layer;             /*!< Pointer to LTDC_LayerTypeDef structure                           */
+
+  LTDC_FlexYUVTypeDef FlexYUV;         /*!< Pointer to LTDC_FlexYUVTypeDef structure                         */
+
+  uint32_t YUVAddress;                        /*!< YUV Frame Buffer address                                         */
+
+  uint32_t ColorConverter;                    /*!< Configure the YUV to RGB conversion.
+                                                   This parameter can be one of value of @ref LTDC_YUV2RGBCONVERTOR */
+} LTDC_LayerFlexYUVCoPlanarTypeDef;
+
+/**
+  * @brief  LTDC YUV Semiplanar addresses structure definition
+  */
+typedef struct
+{
+  uint32_t YAddress;     /*!< Y Frame Buffer address  */
+  uint32_t UVAddress;    /*!< UV Frame Buffer address */
+} LTDC_YUVSemiPlanarAddressTypeDef;
+
+/**
+  * @brief  LTDC YUV Fullplanar addresses structure definition
+  */
+typedef struct
+{
+  uint32_t YAddress;    /*!< Y Frame Buffer address */
+  uint32_t UAddress;    /*!< U Frame Buffer address */
+  uint32_t VAddress;    /*!< V Frame Buffer address */
+} LTDC_YUVFullPlanarAddressTypeDef;
+
+/**
+  * @brief  LTDC Layer Flexible YUV semi Planar structure definition
+  */
+typedef struct
+{
+  LTDC_LayerTypeDef Layer;                                  /*!< Pointer to LTDC_LayerTypeDef              */
+  LTDC_FlexYUVTypeDef FlexYUV;                              /*!< Pointer LTDC_FlexYUVTypeDef               */
+  LTDC_YUVSemiPlanarAddressTypeDef YUVSemiPlanarAddress;    /*!< Pointer LTDC_YUVSemiPlanarAddressTypeDef  */
+  uint32_t ColorConverter;                                    /*!< Configure the YUV to RGB conversion.
+                                                                  This parameter can be one of value
+                                                                  of @ref LTDC_YUV2RGBCONVERTOR              */
+} LTDC_LayerFlexYUVSemiPlanarTypeDef;
+
+/**
+  * @brief  LTDC Layer Flexible YUV full Planar structure definition
+  */
+typedef struct
+{
+  LTDC_LayerTypeDef Layer;                                  /*!< Pointer to LTDC_LayerTypeDef              */
+  LTDC_FlexYUVTypeDef FlexYUV;                              /*!< Pointer LTDC_FlexYUVTypeDef               */
+  LTDC_YUVFullPlanarAddressTypeDef YUVFullPlanarAddress;    /*!< Pointer LTDC_YUVFullPlanarAddressTypeDef  */
+  uint32_t ColorConverter;                                    /*!< Configure the YUV to RGB conversion.
+                                                                   This parameter can be one of value
+                                                                   of @ref LTDC_YUV2RGBCONVERTOR              */
+} LTDC_LayerFlexYUVFullPlanarTypeDef;
+
+/**
+  * @brief  HAL LTDC State structures definition
+  */
+typedef enum
+{
+  HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */
+  HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */
+  HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */
+  HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */
+  HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */
+} HAL_LTDC_StateTypeDef;
+
+/**
+  * @brief  LTDC handle Structure definition
+  */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+typedef struct __LTDC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+{
+  LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
+
+  LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
+
+  LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
+
+  HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
+
+  __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
+
+  __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+  void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Line Event Callback    */
+  void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc);   /*!< LTDC Reload Event Callback  */
+  void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc);         /*!< LTDC Error Callback         */
+  void (* WarningEventCallback)(struct __LTDC_HandleTypeDef *hltdc);  /*!< LTDC Warning Event          */
+
+  void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc);       /*!< LTDC Msp Init callback      */
+  void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Msp DeInit callback    */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+
+} LTDC_HandleTypeDef;
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL LTDC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_LTDC_MSPINIT_CB_ID            = 0x00U,    /*!< LTDC MspInit callback ID       */
+  HAL_LTDC_MSPDEINIT_CB_ID          = 0x01U,    /*!< LTDC MspDeInit callback ID     */
+
+  HAL_LTDC_LINE_EVENT_CB_ID         = 0x02U,    /*!< LTDC Line Event Callback ID    */
+  HAL_LTDC_RELOAD_EVENT_CB_ID       = 0x03U,    /*!< LTDC Reload Callback ID        */
+  HAL_LTDC_WARNING_EVENT_CB_ID      = 0x08U,    /*!< LTDC Warning Event Callback ID */
+  HAL_LTDC_ERROR_CB_ID              = 0x04U     /*!< LTDC Error Callback ID         */
+
+} HAL_LTDC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL LTDC Callback pointer definition
+  */
+typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer to an LTDC callback function */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
+  * @{
+  */
+
+/** @defgroup LTDC_Error_Code LTDC Error Code
+  * @{
+  */
+#define HAL_LTDC_ERROR_NONE               0x00000000U   /*!< LTDC No error             */
+#define HAL_LTDC_ERROR_TE                 0x00000001U   /*!< LTDC Transfer error       */
+#define HAL_LTDC_ERROR_FU                 0x00000002U   /*!< LTDC FIFO Underrun        */
+#define HAL_LTDC_ERROR_CRC                0x00000004U   /*!< LTDC CRC error            */
+#define HAL_LTDC_ERROR_TIMEOUT            0x00000020U   /*!< LTDC Timeout error        */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define  HAL_LTDC_ERROR_INVALID_CALLBACK  0x00000040U   /*!< LTDC Invalid Callback error  */
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Layer LTDC Layer
+  * @{
+  */
+#define LTDC_LAYER_1                      0U       /*!< LTDC Layer 1 */
+#define LTDC_LAYER_2                      1U       /*!< LTDC Layer 2 */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
+  * @{
+  */
+#define LTDC_HSPOLARITY_AL                0U                    /*!< Horizontal Synchronization is active low. */
+#define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL        /*!< Horizontal Synchronization is active high. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
+  * @{
+  */
+#define LTDC_VSPOLARITY_AL                0U                    /*!< Vertical Synchronization is active low. */
+#define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL        /*!< Vertical Synchronization is active high. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
+  * @{
+  */
+#define LTDC_DEPOLARITY_AL                0U                    /*!< Data Enable, is active low. */
+#define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL        /*!< Data Enable, is active high. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
+  * @{
+  */
+#define LTDC_PCPOLARITY_IPC               0U                    /*!< input pixel clock. */
+#define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL        /*!< inverted input pixel clock. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_SYNC LTDC SYNC
+  * @{
+  */
+#define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16U)    /*!< Horizontal synchronization width. */
+#define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH             /*!< Vertical synchronization height. */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
+  * @{
+  */
+#define LTDC_COLOR                        0x000000FFU   /*!< Color mask */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
+  * @{
+  */
+#define LTDC_BLENDING_FACTOR1_CA          0x00000400U   /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR1_PAxCA       0x00000600U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
+  * @{
+  */
+#define LTDC_BLENDING_FACTOR2_CA          0x00000005U   /*!< Blending factor : Cte Alpha */
+#define LTDC_BLENDING_FACTOR2_PAxCA       0x00000007U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Pixelformat LTDC Pixel format
+  * @{
+  */
+#define LTDC_PIXEL_FORMAT_ARGB8888     0x0U             /*!< ARGB8888 LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_ABGR8888     0x1U             /*!< ABGR888  LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_RGBA8888     0x2U             /*!< RGBA888  LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_BGRA8888     0x3U             /*!< BGRA8888 LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_RGB565       0x4U             /*!< RGB565   LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_BGR565       0x5U             /*!< BGR565   LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_RGB888       0x6U             /*!< RGB888   LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_ARGB1555     0x7U             /*!< ARGB1555 LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_ARGB4444     0x8U             /*!< ARGB4444 LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_L8           0x9U             /*!< L8 LTDC pixel format      */
+#define LTDC_PIXEL_FORMAT_AL44         0xAU             /*!< AL44 LTDC pixel format    */
+#define LTDC_PIXEL_FORMAT_AL88         0xBU             /*!< AL88 LTDC pixel format    */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Mirror LTDC Mirror Configuration
+  * @{
+  */
+#define LTDC_MIRROR_HORIZONTAL                       0U       /*!< Enable Horizontal Mirroring                  */
+#define LTDC_MIRROR_VERTICAL                         1U       /*!< Enable Vertical Mirroring                    */
+#define LTDC_MIRROR_HORIZONTAL_VERTICAL              2U       /*!< Enable Horizontal and vertical Mirroring     */
+#define LTDC_MIRROR_NONE                             3U       /*!< Disable Horizontal and vertical Mirroring    */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_ARGB_SIZE LTDC ARGB pixel size in bytes
+  * @{
+  */
+#define LTDC_ARGB_PIXEL_SIZE_1_BYTE      0U       /*!<Custom ARGB with 1 byte per pixel          */
+#define LTDC_ARGB_PIXEL_SIZE_2_BYTES     1U       /*!<Custom ARGB with 2 bytes per pixel         */
+#define LTDC_ARGB_PIXEL_SIZE_3_BYTES     2U       /*!<Custom ARGB with 3 bytes per pixel         */
+#define LTDC_ARGB_PIXEL_SIZE_4_BYTES     3U       /*!<Custom ARGB with 4 bytes per pixel         */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_YUV_ORDER LTDC YUV order from LSB
+  * @{
+  */
+#define LTDC_YUV_ORDER_LUMINANCE_FIRST   LTDC_LxPCR_YF     /*!<Luminance component first            */
+#define LTDC_YUV_ORDER_CHROMINANCE_FIRST 0U                /*!<Chrominance component (U or V) first */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_CHROMINANCE_ORDER LTDC chrominance order from LSB
+  * @{
+  */
+#define LTDC_YUV_CHROMIANCE_ORDER_U_FIRST   LTDC_LxPCR_CBF    /*!<Chrominance order U first  */
+#define LTDC_YUV_CHROMIANCE_ORDER_V_FIRST   0U                /*!<Chrominance order V first  */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LUMINANCE_ORDER LTDC luminance order from LSB
+  * @{
+  */
+#define LTDC_YUV_LUMINANCE_ORDER_ODD_FIRST   LTDC_LxPCR_OF     /*!<Lumiance order Y1 then Y2    */
+#define LTDC_YUV_LUMINANCE_ORDER_EVEN_FIRST  0U                /*!<Luminance order Y2 then Y1   */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LUMINANCE_RANGE LTDC luminance range
+  * @{
+  */
+#define LTDC_YUV_LUMINANCE_RESCALE_ENABLE    LTDC_LxPCR_YREN   /*!< Rescale Luminance from [16-235] to [0-255] */
+#define LTDC_YUV_LUMINANCE_RESCALE_DISABLE   0U                /*!< Luminance provided in range [0-255]        */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_BLENDING_ORDER LTDC layers blending order
+  * @{
+  */
+#define LTDC_BLENDING_ORDER_FOREGROUND    LTDC_LxBFCR_BOR   /*!<Layer set to Foreground during blending */
+#define LTDC_BLENDING_ORDER_BACKGROUND    0U                /*!<Layer set to Background during blending  */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_RGB_COMPONENT LTDC RGB component
+  * @{
+  */
+#define LTDC_RGB_COMPONENT_RED   LTDC_GCCR_REN                                   /*!<Red component                   */
+#define LTDC_RGB_COMPONENT_GREEN LTDC_GCCR_GEN                                   /*!<Green component                 */
+#define LTDC_RGB_COMPONENT_BLUE  LTDC_GCCR_BEN                                   /*!<Blue component                  */
+#define LTDC_RGB_COMPONENT_ALL   (LTDC_GCCR_REN | LTDC_GCCR_GEN | LTDC_GCCR_BEN) /*!<Red, Blue and Green components  */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_DISPLAY LTDC Display
+  * @{
+  */
+#define LTDC_OUT_RGB       0U                                                       /*!< Select RGB as output format (default)    */
+#define LTDC_OUT_YUV_HDTV  (LTDC_EDCR_OCYEN  | LTDC_EDCR_OCYSEL)                    /*!< RGB converted to YUV using ITU-R BT.709  */
+#define LTDC_OUT_YUV_SDTV  LTDC_EDCR_OCYEN                                          /*!< RGB converted to YUV using ITU-R BT.601  */
+#define LTDC_OUT_YVU_HDTV  (LTDC_EDCR_OCYEN | LTDC_EDCR_OCYSEL | LTDC_EDCR_OCYCO)   /*!< RGB converted to YVU using ITU-R BT.709  */
+#define LTDC_OUT_YVU_SDTV  (LTDC_EDCR_OCYEN | LTDC_EDCR_OCYCO)                      /*!< RGB converted to YVU using ITU-R BT.601  */
+
+
+/**
+  * @}
+  */
+/** @defgroup LTDC_YUV2RGBCONVERTOR LTDC YUV to RGB color convertor
+  * @{
+ */
+#define LTDC_YUV2RGBCONVERTOR_BT601_REDUCED_RANGE  0U                /*!< Select ITU-R BT.601 as output format      */
+#define LTDC_YUV2RGBCONVERTOR_BT709_REDUCED_RANGE  1U                /*!< Select ITU-R BT.709 as output format      */
+#define LTDC_YUV2RGBCONVERTOR_BT601_FULL_RANGE     2U                /*!< Select RGB as output format               */
+#define LTDC_YUV2RGBCONVERTOR_BT709_FULL_RANGE     3U                /*!< Select RGB as output format               */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Alpha LTDC Alpha
+  * @{
+  */
+#define LTDC_ALPHA                        LTDC_LxCACR_CONSTA        /*!< LTDC Constant Alpha mask */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
+  * @{
+  */
+#define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position  */
+#define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS          /*!< LTDC Layer start position */
+
+#define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL            /*!< LTDC Layer Line length    */
+#define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR         /*!< LTDC Layer Line number    */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Interrupts LTDC Interrupts
+  * @{
+  */
+#define LTDC_IT_LI                        LTDC_IER_LIE              /*!< LTDC Line Interrupt                  */
+#define LTDC_IT_FU                        LTDC_IER_FUIE             /*!< LTDC FIFO Underrun Interrupt         */
+#define LTDC_IT_TE                        LTDC_IER_TERRIE           /*!< LTDC Transfer Error Interrupt        */
+#define LTDC_IT_RR                        LTDC_IER_RRIE             /*!< LTDC Register Reload Interrupt       */
+#define LTDC_IT_CRC                       LTDC_IER_CRCIE            /*!< LTDC CRC error Interrupt             */
+#define LTDC_IT_FUW                       LTDC_IER_FUWIE            /*!< LTDC FIFO Warning Underrun Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Flags LTDC Flags
+  * @{
+  */
+#define LTDC_FLAG_LI                      LTDC_ISR_LIF              /*!< LTDC Line Interrupt Flag             */
+#define LTDC_FLAG_FU                      LTDC_ISR_FUIF             /*!< LTDC FIFO Underrun interrupt Flag    */
+#define LTDC_FLAG_TE                      LTDC_ISR_TERRIF           /*!< LTDC Transfer Error interrupt Flag   */
+#define LTDC_FLAG_RR                      LTDC_ISR_RRIF             /*!< LTDC Register Reload interrupt Flag  */
+#define LTDC_FLAG_CRC                     LTDC_ISR_CRCIF            /*!< LTDC CRC error Interrupt             */
+#define LTDC_FLAG_FUW                     LTDC_ISR_FUWIF            /*!< LTDC FIFO Warning Underrun Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Reload_Type LTDC Reload Type
+  * @{
+  */
+#define LTDC_RELOAD_IMMEDIATE             LTDC_SRCR_IMR             /*!< Immediate Reload */
+#define LTDC_RELOAD_VERTICAL_BLANKING     LTDC_SRCR_VBR             /*!< Vertical Blanking Reload */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
+  * @{
+  */
+
+/** @brief Reset LTDC handle state.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None
+  */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
+                                                      (__HANDLE__)->State = HAL_LTDC_STATE_RESET;     \
+                                                      (__HANDLE__)->MspInitCallback = NULL;           \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                    } while(0)
+#else
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the LTDC.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
+
+/**
+  * @brief  Disable the LTDC.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
+
+/**
+  * @brief  Enable the LTDC Layer.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __LAYER__   Specify the layer to be enabled.
+  *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval None.
+  */
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+                                                         |= (uint32_t)LTDC_LxCR_LEN)
+
+/**
+  * @brief  Disable the LTDC Layer.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __LAYER__   Specify the layer to be disabled.
+  *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval None.
+  */
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+                                                         &= ~(uint32_t)LTDC_LxCR_LEN)
+
+/**
+  * @brief  Reload immediately all LTDC Layers.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
+
+/**
+  * @brief  Reload during vertical blanking period all LTDC Layers.
+  * @param  __HANDLE__  LTDC handle
+  * @retval None.
+  */
+#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the LTDC pending flags.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __FLAG__    Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_FLAG_LI: Line Interrupt flag
+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+  *            @arg LTDC_FLAG_CRC: LTDC CRC error interrupt flag
+  *            @arg LTDC_FLAG_FUW: FIFO Warning Underrun interrupt flag
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR2 & (__FLAG__))
+#else
+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+#endif /* __ARM_FEATURE_CMSE & __ARM_FEATURE_CMSE == 3U */
+
+/**
+  * @brief  Clears the LTDC pending flags.
+  * @param  __HANDLE__  LTDC handle
+  * @param  __FLAG__    Specify the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_FLAG_LI: Line Interrupt flag
+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag
+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
+  *            @arg LTDC_FLAG_CRC: LTDC CRC error Interrupt flag
+  *            @arg LTDC_FLAG_FUW: FIFO Warning Underrun Interrupt flag
+  * @retval None
+  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR2 = (__FLAG__))
+#else
+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#endif /* __ARM_FEATURE_CMSE & __ARM_FEATURE_CMSE == 3U */
+
+/**
+  * @brief  Enables the specified LTDC interrupts.
+  * @param  __HANDLE__  LTDC handle
+  * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  *            @arg LTDC_IT_CRC: LTDC CRC error Interrupt
+  *            @arg LTDC_IT_FUW: FIFO Warning Underrun Interrupt
+  * @retval None
+  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER2 |= (__INTERRUPT__))
+#else
+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+#endif /* __ARM_FEATURE_CMSE & __ARM_FEATURE_CMSE == 3U */
+
+/**
+  * @brief  Disables the specified LTDC interrupts.
+  * @param  __HANDLE__  LTDC handle
+  * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  *            @arg LTDC_IT_CRC: LTDC CRC error Interrupt
+  *            @arg LTDC_IT_FUW: FIFO Underrun Warning Interrupt
+  * @retval None
+  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER2 &= ~(__INTERRUPT__))
+#else
+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+#endif /* __ARM_FEATURE_CMSE & __ARM_FEATURE_CMSE == 3U */
+
+/**
+  * @brief  Check whether the specified LTDC interrupt has occurred or not.
+  * @param  __HANDLE__  LTDC handle
+  * @param __INTERRUPT__ Specify the LTDC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg LTDC_IT_LI: Line Interrupt flag
+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag
+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag
+  *            @arg LTDC_IT_CRC: LTDC CRC error Interrupt
+  *            @arg LTDC_IT_FUW: FIFO Underrun Warning Interrupt
+  * @retval The state of INTERRUPT (SET or RESET).
+  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER2 & (__INTERRUPT__))
+#else
+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+#endif /* __ARM_FEATURE_CMSE & __ARM_FEATURE_CMSE == 3U */
+/**
+  * @}
+  */
+
+/* Include LTDC HAL Extension module */
+#include "stm32n6xx_hal_ltdc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LTDC_Exported_Functions
+  * @{
+  */
+/** @addtogroup LTDC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_WarningEventCallback(LTDC_HandleTypeDef *hltdc);
+
+/* Burst length function *****************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigBurstLength(LTDC_HandleTypeDef *hltdc, uint32_t BurstLength, uint32_t LayerIdx);
+
+/* Underrun threshold function *****************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigUnderrunThreshold(LTDC_HandleTypeDef *hltdc, uint16_t Threshold);
+
+/* Mirroring functions *****************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigMirror(LTDC_HandleTypeDef *hltdc, uint32_t Mirror, uint32_t LayerIdx);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+                                            pLTDC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup LTDC_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
+/**
+  * @}
+  */
+
+/** @addtogroup LTDC_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexARGB(LTDC_HandleTypeDef *hltdc,
+                                               const LTDC_LayerFlexARGBTypeDef *pLayerFlexARGB,
+                                               uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexYUVSemiPlanar(LTDC_HandleTypeDef *hltdc,
+                                                        LTDC_LayerFlexYUVSemiPlanarTypeDef *pLayerFlexYUVSemiPlanar,
+                                                        uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexYUVFullPlanar(LTDC_HandleTypeDef *hltdc,
+                                                        LTDC_LayerFlexYUVFullPlanarTypeDef *pLayerFlexYUVFullPlanar,
+                                                        uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexYUVCoPlanar(LTDC_HandleTypeDef *hltdc,
+                                                      const LTDC_LayerFlexYUVCoPlanarTypeDef *pLayerFlexYUVCoPlanar,
+                                                      uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetSemiPlanarAddress(LTDC_HandleTypeDef *hltdc,
+                                                LTDC_LayerFlexYUVSemiPlanarTypeDef *pYUVSemiPlanarAddress,
+                                                uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetFullPlanarAddress(LTDC_HandleTypeDef *hltdc,
+                                                LTDC_LayerFlexYUVFullPlanarTypeDef *pYUVFullPlanarAddress,
+                                                uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetSemiPlanarAddress_NoReload(LTDC_HandleTypeDef *hltdc,
+                                                         LTDC_LayerFlexYUVSemiPlanarTypeDef *pYUVSemiPlanarAddress,
+                                                         uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetFullPlanarAddress_NoReload(LTDC_HandleTypeDef *hltdc,
+                                                         LTDC_LayerFlexYUVFullPlanarTypeDef *pYUVFullPlanarAddress,
+                                                         uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize,
+                                      uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigBlendingOrder(LTDC_HandleTypeDef *hltdc, uint32_t Order, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableDefaultColor(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableDefaultColor(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableGammaCorrection(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableGammaCorrection(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_ConfigGammaCorrection(LTDC_HandleTypeDef *hltdc, uint32_t GammaOnes,
+                                                 uint32_t GammaTenths, uint32_t RGBComponent);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
+HAL_StatusTypeDef HAL_LTDC_ReloadLayer(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetOutputDisplay(LTDC_HandleTypeDef *hltdc, uint32_t Display);
+HAL_StatusTypeDef HAL_LTDC_SetExpectedCRC(LTDC_HandleTypeDef *hltdc, uint16_t ExpectedCRC);
+HAL_StatusTypeDef HAL_LTDC_EnableCRC(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_DisableCRC(LTDC_HandleTypeDef *hltdc);
+HAL_StatusTypeDef HAL_LTDC_GetComputedCRC(LTDC_HandleTypeDef *hltdc, uint16_t *pComputedCRC);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+                                                uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+                                                  uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+                                                      uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
+
+/**
+  * @}
+  */
+
+/** @addtogroup LTDC_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc);
+uint32_t              HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup LTDC_Private_Macros LTDC Private Macros
+  * @{
+  */
+#define LTDC_LAYER(__HANDLE__, __LAYER__)              ((LTDC_Layer_TypeDef *)((uint32_t)(\
+                                                                               ((uint32_t)((__HANDLE__)->Instance))\
+                                                                               + 0x100U + (0x100U*(__LAYER__)))))
+
+#define IS_LTDC_LAYER(__LAYER__)                       ((__LAYER__) < MAX_LAYER)
+#define IS_LTDC_PLANAR_LAYER(__LAYER__)                ((__LAYER__) == LTDC_LAYER_1)
+#define IS_LTDC_HSPOL(__HSPOL__)                       (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
+                                                        || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(__VSPOL__)                       (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
+                                                        || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(__DEPOL__)                       (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
+                                                        || ((__DEPOL__) ==  LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(__PCPOL__)                       (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
+                                                        || ((__PCPOL__) ==  LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSYNC(__HSYNC__)                       ((__HSYNC__)  <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_VSYNC(__VSYNC__)                       ((__VSYNC__)  <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AHBP(__AHBP__)                         ((__AHBP__)   <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AVBP(__AVBP__)                         ((__AVBP__)   <= LTDC_VERTICALSYNC)
+#define IS_LTDC_AAW(__AAW__)                           ((__AAW__)    <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_AAH(__AAH__)                           ((__AAH__)    <= LTDC_VERTICALSYNC)
+#define IS_LTDC_TOTALW(__TOTALW__)                     ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
+#define IS_LTDC_TOTALH(__TOTALH__)                     ((__TOTALH__) <= LTDC_VERTICALSYNC)
+#define IS_LTDC_BLUEVALUE(__BBLUE__)                   ((__BBLUE__)  <= LTDC_COLOR)
+#define IS_LTDC_GREENVALUE(__BGREEN__)                 ((__BGREEN__) <= LTDC_COLOR)
+#define IS_LTDC_REDVALUE(__BRED__)                     ((__BRED__)   <= LTDC_COLOR)
+#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
+                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
+#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
+                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) \
+  (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888)  || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ABGR8888)  || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGBA8888)  || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_BGRA8888)  || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)    || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_BGR565)    || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)    || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555)  || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444)  || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)        || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)      || \
+   ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
+
+#define IS_LTDC_ALPHA(__ALPHA__)                       ((__ALPHA__) <= LTDC_ALPHA)
+#define IS_LTDC_HCONFIGST(__HCONFIGST__)               ((__HCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_HCONFIGSP(__HCONFIGSP__)               ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_VCONFIGST(__VCONFIGST__)               ((__VCONFIGST__) <= LTDC_STARTPOSITION)
+#define IS_LTDC_VCONFIGSP(__VCONFIGSP__)               ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
+#define IS_LTDC_CFBP(__CFBP__)                         ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLL(__CFBLL__)                       ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
+#define IS_LTDC_CFBLNBR(__CFBLNBR__)                   ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
+#define IS_LTDC_LIPOS(__LIPOS__)                       ((__LIPOS__) <= 0x7FFU)
+#define IS_LTDC_RELOAD(__RELOADTYPE__)                 (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
+                                                        ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
+
+#define IS_LTDC_MIRROR(__MIRROR__)         (((__MIRROR__) == LTDC_MIRROR_HORIZONTAL)           ||\
+                                            ((__MIRROR__) == LTDC_MIRROR_VERTICAL)             ||\
+                                            ((__MIRROR__) == LTDC_MIRROR_HORIZONTAL_VERTICAL) ||\
+                                            ((__MIRROR__) == LTDC_MIRROR_NONE))
+
+#define IS_LTDC_ARGB_SIZE(__ARGB_SIZE__)               (((__ARGB_SIZE__) == LTDC_ARGB_PIXEL_SIZE_1_BYTE)         ||\
+                                                        ((__ARGB_SIZE__) == LTDC_ARGB_PIXEL_SIZE_2_BYTES)        ||\
+                                                        ((__ARGB_SIZE__) == LTDC_ARGB_PIXEL_SIZE_3_BYTES)        ||\
+                                                        ((__ARGB_SIZE__) == LTDC_ARGB_PIXEL_SIZE_4_BYTES))
+
+#define IS_LTDC_ARGB_COMPONENT_POSITION(__ARGB_POS__)         ((__ARGB_POS__) <= 0x1FU)
+#define IS_LTDC_ARGB_COMPONENT_WIDTH(__ARGB_WIDTH__)         ((__ARGB_WIDTH__) <= 0xFU)
+#define IS_LTDC_YUV_ORDER(__YUV_ORDER__)               (((__YUV_ORDER__) == LTDC_YUV_ORDER_LUMINANCE_FIRST)      ||\
+                                                        ((__YUV_ORDER__) == LTDC_YUV_ORDER_CHROMINANCE_FIRST))
+
+#define IS_LTDC_Y_ORDER(__Y_ORDER__)                 (((__Y_ORDER__) == LTDC_YUV_LUMINANCE_ORDER_ODD_FIRST)         ||\
+                                                      ((__Y_ORDER__) == LTDC_YUV_LUMINANCE_ORDER_EVEN_FIRST))
+
+#define IS_LTDC_UV_ORDER(__UV_ORDER__)                 (((__UV_ORDER__) == LTDC_YUV_CHROMIANCE_ORDER_U_FIRST)   ||\
+                                                        ((__UV_ORDER__) == LTDC_YUV_CHROMIANCE_ORDER_V_FIRST))
+
+#define IS_LTDC_Y_RANHGE(__Y_RANGE__)                 (((__Y_RANGE__) == LTDC_YUV_LUMINANCE_RESCALE_ENABLE)   ||\
+                                                       ((__Y_RANGE__) == LTDC_YUV_LUMINANCE_RESCALE_DISABLE))
+
+#define IS_LTDC_BLEND_ORDER(__BLEND_ORDER__)          (((__BLEND_ORDER__) == LTDC_BLENDING_ORDER_FOREGROUND)   ||\
+                                                       ((__BLEND_ORDER__) == LTDC_BLENDING_ORDER_BACKGROUND))
+
+#define IS_LTDC_RGB_COMPONENT(__RGB_COMPONENT__)      (((__RGB_COMPONENT__) == LTDC_RGB_COMPONENT_RED)          ||\
+                                                       ((__RGB_COMPONENT__) == LTDC_RGB_COMPONENT_GREEN)        ||\
+                                                       ((__RGB_COMPONENT__) == LTDC_RGB_COMPONENT_BLUE )        ||\
+                                                       ((__RGB_COMPONENT__) == LTDC_RGB_COMPONENT_ALL))
+
+#define IS_LTDC_DISPLAY(__LTDC_DISPLAY__)             (((__LTDC_DISPLAY__) == LTDC_OUT_RGB)        ||\
+                                                       ((__LTDC_DISPLAY__) == LTDC_OUT_YUV_HDTV)   ||\
+                                                       ((__LTDC_DISPLAY__) == LTDC_OUT_YUV_SDTV)   ||\
+                                                       ((__LTDC_DISPLAY__) == LTDC_OUT_YVU_HDTV)   ||\
+                                                       ((__LTDC_DISPLAY__) == LTDC_OUT_YVU_SDTV))
+
+#define IS_LTDC_BURST_LENGTH(__BURST_LENGTH__)                       (((__BURST_LENGTH__) <= 0x10U) &&\
+                                                                      ((__BURST_LENGTH__) >= 0x1U))
+
+#define IS_LTDC_GAMMA_VALUE(__ONES__, __TENTHS__)      ((((__TENTHS__) + ((__ONES__) * 10U)) >= 4U)   &&\
+                                                        (((__TENTHS__) + ((__ONES__) * 10U)) <= 29U))
+
+#define IS_LTDC_YUV2RGBCONVERTOR(__CONVERTOR__)  (((__CONVERTOR__) == LTDC_YUV2RGBCONVERTOR_BT709_FULL_RANGE)      ||\
+                                                  ((__CONVERTOR__) == LTDC_YUV2RGBCONVERTOR_BT709_REDUCED_RANGE)   ||\
+                                                  ((__CONVERTOR__) == LTDC_YUV2RGBCONVERTOR_BT601_FULL_RANGE)      ||\
+                                                  ((__CONVERTOR__) == LTDC_YUV2RGBCONVERTOR_BT601_REDUCED_RANGE))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LTDC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_LTDC_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ltdc_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ltdc_ex.h
new file mode 100644
index 000000000..285845849
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ltdc_ex.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_ltdc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of LTDC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_LTDC_EX_H
+#define STM32N6xx_HAL_LTDC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (LTDC) && defined (DSI)
+
+#include "stm32n6xx_hal_dsi.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup LTDCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LTDCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LTDCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LTDC && DSI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_LTDC_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mce.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mce.h
new file mode 100644
index 000000000..1b10002a0
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mce.h
@@ -0,0 +1,467 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mce.h
+  * @author  MCD Application Team
+  * @brief   Header file of MCE HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2024 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_MCE_H
+#define STM32N6xx_HAL_MCE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined(MCE1)
+/** @addtogroup MCE
+  * @{
+  */
+typedef struct
+{
+  uint32_t         ContextID;              /*!< MCE region context ID (can be null) */
+  /*!< This parameter is a value of @ref MCE_Context_Index. */
+
+  uint32_t         StartAddress;           /*!< MCE region start address */
+
+  uint32_t         EndAddress;             /*!< MCE region end address */
+
+  uint32_t         Mode;                   /*!< Indicates the chaining mode used for encryption. */
+  /*!< This parameter is a value of @defgroup MCE_Ciphering_Algorithm */
+  uint32_t         AccessMode;             /*!< MCE region writes enabled or not */
+  /*!< This parameter is a value of @ref MCE_Region_Privilege. */
+
+  uint32_t         PrivilegedAccess;       /*!< MCE region privileged access or not */
+  /*!< This parameter is a value of @ref MCE_Region_Privilege. */
+
+} MCE_RegionConfigTypeDef;
+
+typedef struct
+{
+  uint32_t         Nonce[2];              /*!< MCE context nonce */
+
+  uint32_t         Version;               /*!< 16-bit long MCE context version */
+
+  uint32_t         *pKey;                  /*!< Pointer at the key used for encryption/decryption */
+
+  uint32_t         KeySize;               /*!< This parameter can be MCE_AES_128 or MCE_AES_256 */
+
+  uint32_t         Cipher_Mode;           /*!< Authorized cipher mode  */
+
+} MCE_AESConfigTypeDef;
+
+typedef struct
+{
+  uint32_t          KeyType;             /*!< This parameter is a value of @ref MCE_KeyType. */
+
+  uint32_t          *pKey;                   /*!< Pointer at the key used for encryption/decryption .*/
+
+} MCE_NoekeonConfigTypeDef;
+
+
+/**
+  * @brief MCE states structure definition
+  */
+typedef enum
+{
+  HAL_MCE_STATE_RESET             = 0x00U,  /*!< MCE not yet initialized or disabled */
+  HAL_MCE_STATE_READY             = 0x01U,  /*!< MCE initialized and ready for use   */
+  HAL_MCE_STATE_BUSY              = 0x02U,  /*!< MCE internal processing is ongoing  */
+} HAL_MCE_StateTypeDef;
+
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+typedef struct __MCE_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+{
+  MCE_TypeDef             *Instance;        /*!< MCE registers base address */
+
+  HAL_MCE_StateTypeDef    State;            /*!< MCE state */
+
+  HAL_LockTypeDef         Lock;             /*!< MCE Locking object */
+
+  __IO uint32_t           ErrorCode;        /*!< MCE error code */
+
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+  void (* ErrorCallback)(struct __MCE_HandleTypeDef *hmce);     /*!< MCE error callback */
+
+  void (* MspInitCallback)(struct __MCE_HandleTypeDef *hmce);   /*!< MCE Msp Init callback */
+
+  void (* MspDeInitCallback)(struct __MCE_HandleTypeDef *hmce); /*!< MCE Msp DeInit callback */
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+
+} MCE_HandleTypeDef;
+
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL MCE Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_MCE_ERROR_CB_ID       = 0x00U,  /*!< MCE error callback ID      */
+  HAL_MCE_MSPINIT_CB_ID     = 0x01U,  /*!< MCE Msp DeInit callback ID */
+  HAL_MCE_MSPDEINIT_CB_ID   = 0x02U   /*!< MCE Msp DeInit callback ID */
+} HAL_MCE_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL MCE Callback pointer definition
+  */
+typedef  void (*pMCE_CallbackTypeDef)(MCE_HandleTypeDef *hmce); /*!< pointer to a MCE callback function */
+
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MCE_Exported_Constants MCE Exported Constants
+  * @{
+  */
+
+/** @defgroup MCE_Error_Definition   MCE Error Definition
+  * @{
+  */
+#define  HAL_MCE_ERROR_NONE                       ((uint32_t)0x00000000U)    /*!< No error                                                         */
+#define  HAL_MCE_CONFIGURATION_ACCESS_ERROR       ((uint32_t)0x00000001U)    /*!< Configuration access error                                       */
+#define  HAL_MCE_ILLEGAL_ACCESS_READ_PRIV_ERROR   ((uint32_t)0x00000002U)    /*!< Illegal privileged data read or instruction fetch access error   */
+#define  HAL_MCE_ILLEGAL_ACCESS_READ_NPRIV_ERROR  ((uint32_t)0x00000004U)    /*!< Illegal unprivileged data read or instruction fetch access error */
+#define  HAL_MCE_ILLEGAL_ACCESS_WRITE_PRIV_ERROR  ((uint32_t)0x00000008U)    /*!< Illegal privileged data write access error                       */
+#define  HAL_MCE_ILLEGAL_ACCESS_WRITE_NPRIV_ERROR ((uint32_t)0x00000010U)    /*!< Illegal un privileged data write access error                    */
+#define  HAL_MCE_MASTER_KEY_ERROR                 ((uint32_t)0x00000020U)    /*!< Master key error                                                 */
+#define  HAL_MCE_FASTMASTER_KEY_ERROR             ((uint32_t)0x00000040U)    /*!< Fast master key error                                            */
+#define  HAL_MCE_CONTEXT_KEY_ERROR                ((uint32_t)0x00000080U)    /*!< Context key error                                                */
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+#define HAL_MCE_ERROR_INVALID_CALLBACK            ((uint32_t)0x00000100U)    /*!< Invalid Callback error                                           */
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_Interrupts    MCE Interrupts
+  * @{
+  */
+#define MCE_IT_ILLEGAL_ACCESS_ERROR        MCE_IAIER_IAEIE                   /*!< Illegal access error interrupt       */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_Illegal_Access_Flags    MCE Illegal Access Flags
+  * @{
+  */
+#define MCE_ILLEGAL_ACCESS_READ_NPRIV      MCE_IASR_IAEF                      /*!< Illegal unprivileged data read/instruction fetch access flag   */
+/**
+  * @}
+  */
+
+
+/** @defgroup MCE_Regions_Index   MCE Regions Index
+  * @{
+  */
+#define MCE_REGION1                       0U    /*!< MCE region 1 */
+#define MCE_REGION2                       1U    /*!< MCE region 2 */
+#define MCE_REGION3                       2U    /*!< MCE region 3 */
+#define MCE_REGION4                       3U    /*!< MCE region 4 */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_Context_Index   MCE Context Index
+  * @{
+  */
+#define MCE_NO_CONTEXT                    0U                /*!< MCE no context */
+#define MCE_CONTEXT1                      MCE_REGCR_CTXID_0 /*!< MCE context 1  */
+#define MCE_CONTEXT2                      MCE_REGCR_CTXID_1 /*!< MCE context 2  */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_Ciphering_Algorithm   MCE Ciphering Algorithm
+  * @{
+  */
+#define MCE_NO_CIPHER                     0U               /*!< MCE no cipher         */
+#define MCE_STREAM_CIPHER                 MCE_REGCR_ENC_0  /*!< MCE stream cipher     */
+#define MCE_BLOCK_CIPHER                  MCE_REGCR_ENC_1  /*!< MCE block cipher      */
+#define MCE_FASTBLOCK_CIPHER              MCE_REGCR_ENC    /*!< MCE fast block cipher */
+/**
+  * @}
+  */
+
+
+/** @defgroup MCE_Region_Privilege   MCE Region Privilege
+  * @{
+  */
+#define MCE_REGION_READONLY               0U               /*!< Writes to region are ignored, reads are allowed */
+#define MCE_REGION_READWRITE              MCE_ATTR_WREN    /*!< Region can be read and written                  */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_Configuration_Attributes   MCE Configuration Attributes
+  * @{
+  */
+#define MCE_ATTRIBUTE_NPRIV               0U                /*!< Non-privileged access protection */
+#define MCE_ATTRIBUTE_PRIV                MCE_PRIVCFGR_PRIV /*!< Privileged access protection     */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_Lock MCE Lock values
+  * @{
+  */
+#define MCE_LOCK_OFF                      0U            /*!< No global lock set */
+#define MCE_LOCK_ON                       MCE_CR_GLOCK  /*!< Global lock set    */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_Lock MCE Lock values
+  * @{
+  */
+#define MCE_MASTERKEYS_LOCK_OFF           0U             /*!< No master keys lock set */
+#define MCE_MASTERKEYS_LOCK_ON            MCE_CR_MKLOCK  /*!< Master keys lock set    */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_KeyType key type used for encryption, Master key or Fast Master key
+  * @{
+  */
+#define MCE_USE_MASTERKEYS              0U             /*!< Master keys used for encryption         */
+#define MCE_USE_FASTMASTERKEYS          1U             /*!< Fast Master keys used for encryption    */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup MCE_CipherSelection MCE Cipher Selection
+  * @{
+  */
+#define MCE_AES_128                       MCE_CR_CIPHERSEL_0  /*!< AES-128 cipher selected for all encrypted regions */
+#define MCE_AES_256                       MCE_CR_CIPHERSEL    /*!< AES-256 cipher selected for all encrypted regions */
+#define MCE_NOEKEON                       MCE_CR_CIPHERSEL_1  /*!< Noekeon cipher selected for all encrypted regions */
+/**
+  * @}
+  */
+
+/** @defgroup MCE_ContextMode MCE Context Mode
+  * @{
+  */
+#define MCE_CONTEXT_STREAM_CIPHER      MCE_CCCFGR_MODE_0  /*!< Stream cipher is allowed with this cipher context     */
+#define MCE_CONTEXT_BLOCK_CIPHER       MCE_CCCFGR_MODE_1  /*!< Block cipher is allowed with this cipher context      */
+#define MCE_CONTEXT_FASTBLOCK_CIPHER   MCE_CCCFGR_MODE    /*!< Fast block cipher is allowed with this cipher context */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MCE_Exported_Macros MCE Exported Macros
+  * @{
+  */
+
+/** @brief  Reset MCE handle state.
+  * @param  __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval None
+  */
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+#define __HAL_MCE_RESET_HANDLE_STATE(__HANDLE__)                            \
+  do{                                                                       \
+    (__HANDLE__)->State = HAL_MCE_STATE_RESET;                              \
+    (__HANDLE__)->MspInitCallback = NULL;                                   \
+    (__HANDLE__)->MspDeInitCallback = NULL;                                 \
+  } while(0)
+#else
+#define __HAL_MCE_RESET_HANDLE_STATE(__HANDLE__)                            \
+  ((__HANDLE__)->State = HAL_MCE_STATE_RESET)
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable MCE peripheral interrupts combination
+  * @param  __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  __INTERRUPT__ mask on enabled interrupts
+  *          This parameter can be one of the following values:
+  *            @arg @ref MCE_IT_ILLEGAL_ACCESS_ERROR        MCE illegal access error interrupt
+  * @retval None
+  */
+#define __HAL_MCE_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT(((__HANDLE__)->Instance->IAIER), (__INTERRUPT__))
+
+/**
+  * @brief  Disable MCE peripheral interrupts combination
+  * @param  __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  __INTERRUPT__ mask on disabled interrupts
+  *          This parameter can be one of the following values:
+  *            @arg @ref MCE_IT_ILLEGAL_ACCESS_ERROR        MCE illegal access error interrupt
+  * @retval None
+  */
+#define __HAL_MCE_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT(((__HANDLE__)->Instance->IAIER), (__INTERRUPT__))
+
+
+/**
+  * @brief  Get MCE peripheral access error flag
+  * @param  __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  __FLAG__ access error flag to check
+  *          This parameter can be one of the following values:
+  *            @arg @ref MCE_ILLEGAL_ACCESS_READ_NPRIV                 MCE illegal access error flag
+  * @retval 0 (not set) or 1 (set)
+  */
+#define __HAL_MCE_GET_FLAG(__HANDLE__, __FLAG__)  READ_BIT((__HANDLE__)->Instance->IASR, MCE_IASR_IAEF)
+
+
+
+/**
+  * @brief  Clear MCE peripheral illegal/configuration access flag
+  * @param  __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  __FLAG__ illegal access flag to check
+  *          This parameter can be one of the following values:
+  *            @arg @ref MCE_ILLEGAL_ACCESS_READ_NPRIV                 MCE illegal access error flag
+  * @retval 0 (not set) or 1 (set)
+  */
+#define __HAL_MCE_CLEAR_FLAG(__HANDLE__, __FLAG__)  WRITE_REG(((__HANDLE__)->Instance->IACR), MCE_IACR_IAEF)
+
+
+/**
+  * @}
+  */
+
+
+/* Exported functions ---------------------------------------------------------*/
+
+
+HAL_StatusTypeDef HAL_MCE_Init(MCE_HandleTypeDef *hmce);
+HAL_StatusTypeDef HAL_MCE_DeInit(MCE_HandleTypeDef *hmce);
+void HAL_MCE_MspInit(MCE_HandleTypeDef *hmce);
+void HAL_MCE_MspDeInit(MCE_HandleTypeDef *hmce);
+
+
+HAL_StatusTypeDef HAL_MCE_ConfigNoekeon(MCE_HandleTypeDef *hmce, const MCE_NoekeonConfigTypeDef *pConfig);
+HAL_StatusTypeDef HAL_MCE_ConfigAESContext(MCE_HandleTypeDef *hmce, const MCE_AESConfigTypeDef  *AESConfig,
+                                           uint32_t ContextIndex);
+HAL_StatusTypeDef HAL_MCE_ConfigRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex,
+                                       const MCE_RegionConfigTypeDef *pConfig);
+HAL_StatusTypeDef HAL_MCE_SetRegionAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_MCE_EnableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex);
+HAL_StatusTypeDef HAL_MCE_DisableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex);
+HAL_StatusTypeDef HAL_MCE_EnableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_MCE_DisableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_MCE_LockGlobalConfig(MCE_HandleTypeDef *hmce);
+HAL_StatusTypeDef HAL_MCE_LockAESContextConfig(MCE_HandleTypeDef *hmce, uint32_t ContextIndex);
+HAL_StatusTypeDef HAL_MCE_LockAESContextKey(MCE_HandleTypeDef *hmce, uint32_t ContextIndex);
+HAL_StatusTypeDef HAL_MCE_LockNoekeonMasterKeys(MCE_HandleTypeDef *hmce);
+HAL_StatusTypeDef HAL_MCE_LockNoekeonFastKeys(MCE_HandleTypeDef *hmce);
+HAL_StatusTypeDef HAL_MCE_GetAESContextCRCKey(const MCE_HandleTypeDef *hmce, uint32_t *pCRCKey, uint32_t ContextIndex);
+
+
+void HAL_MCE_IRQHandler(MCE_HandleTypeDef *hmce);
+void HAL_MCE_ErrorCallback(MCE_HandleTypeDef *hmce);
+
+HAL_MCE_StateTypeDef HAL_MCE_GetState(MCE_HandleTypeDef const *hmce);
+uint32_t HAL_MCE_GetError(MCE_HandleTypeDef const *hmce);
+uint32_t HAL_MCE_KeyCRCComputation(const uint32_t *pKey);
+
+#define IS_MCE_INTERRUPT(__INTERRUPT__) ((__INTERRUPT__) == MCE_IT_ILLEGAL_ACCESS_ERROR)
+
+/**
+  * @brief Verify the MCE region index.
+  * @param __INDEX__ MCE region index
+  * @retval SET (__INDEX__ is valid) or RESET (__INDEX__ is invalid)
+  */
+#define IS_MCE_REGIONINDEX(__INDEX__) (((__INDEX__) == MCE_REGION1)     || \
+                                       ((__INDEX__) == MCE_REGION2)     || \
+                                       ((__INDEX__) == MCE_REGION3)     || \
+                                       ((__INDEX__) == MCE_REGION4))
+
+/**
+  * @brief Verify the MCE configuration attributes.
+  * @param __ATTRIBUTE__ MCE region index
+  * @retval SET (__ATTRIBUTE__ is valid) or RESET (__ATTRIBUTE__ is invalid)
+  */
+#define IS_MCE_ATTRIBUTE(__ATTRIBUTE__) (((__ATTRIBUTE__) == MCE_ATTRIBUTE_PRIV)   || \
+                                         ((__ATTRIBUTE__) == MCE_ATTRIBUTE_NPRIV))
+
+/**
+  * @brief Verify the MCE region privilege attribute.
+  * @param __PRIVILEGED__ MCE region privilege attribute
+  * @retval SET (__PRIVILEGED__ is valid) or RESET (__PRIVILEGED__ is invalid)
+  */
+#define IS_MCE_REGIONPRIVILEGED(__PRIVILEGED__) (((__PRIVILEGED__) == MCE_REGION_NPRIV)   || \
+                                                 ((__PRIVILEGED__) == MCE_REGION_PRIV))
+
+/**
+  * @brief Verify the MCE region write enable attribute.
+  * @param __WRITE__ MCE region write enable attribute
+  * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
+  */
+#define IS_MCE_WRITE(__WRITE__) (((__WRITE__) == MCE_REGION_READONLY)   || \
+                                 ((__WRITE__) == MCE_REGION_READWRITE))
+
+/**
+  * @brief Verify the MCE region context.
+  * @param __INSTANCE__ MCE instance
+  * @param __CONTEXT__ MCE region context
+  * @retval SET (__CONTEXT__ is valid) or RESET (__CONTEXT__ is invalid)
+  */
+
+#define IS_MCE_CONTEXT(__INSTANCE__, __CONTEXT__) (((__INSTANCE__) == (MCE1)) ?           \
+                                                   (((__CONTEXT__) == MCE_NO_CONTEXT)   || \
+                                                    ((__CONTEXT__) == MCE_CONTEXT1)     || \
+                                                    ((__CONTEXT__) == MCE_CONTEXT2))     : \
+                                                   (((__CONTEXT__) == MCE_CONTEXT1)     || \
+                                                    ((__CONTEXT__) == MCE_CONTEXT2)     || \
+                                                    ((__CONTEXT__) == MCE_NO_CONTEXT)))
+/**
+  * @brief Verify the MCE region algorithm.
+  * @param __INSTANCE__ MCE instance
+  * @param __ALGO__ MCE region context
+  * @retval SET (__ALGO__ is valid) or RESET (__ALGO__ is invalid)
+  */
+#define IS_MCE_ALGORITHM(__INSTANCE__, __ALGO__) (((__INSTANCE__) == (MCE1)) ?             \
+                                                  (((__ALGO__) == MCE_NO_CIPHER)         || \
+                                                   ((__ALGO__) == MCE_STREAM_CIPHER)     || \
+                                                   ((__ALGO__) == MCE_BLOCK_CIPHER)      || \
+                                                   ((__ALGO__) == MCE_FASTBLOCK_CIPHER))  : \
+                                                  (((__ALGO__) == MCE_NO_CIPHER)         || \
+                                                   ((__ALGO__) == MCE_BLOCK_CIPHER)      || \
+                                                   ((__ALGO__) == MCE_STREAM_CIPHER)     || \
+                                                   ((__ALGO__) == MCE_FASTBLOCK_CIPHER)))
+
+#endif /* MCE1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_MCE_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mdf.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mdf.h
new file mode 100644
index 000000000..7a613704c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mdf.h
@@ -0,0 +1,1155 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mdf.h
+  * @author  MCD Application Team
+  * @brief   Header file of MDF HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_MDF_H
+#define STM32N6xx_HAL_MDF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup MDF
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MDF_Exported_Types  MDF Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL MDF states definition
+  */
+typedef enum
+{
+  HAL_MDF_STATE_RESET       = 0x00U, /*!< MDF not initialized */
+  HAL_MDF_STATE_READY       = 0x01U, /*!< MDF initialized and ready for use */
+  HAL_MDF_STATE_ACQUISITION = 0x02U, /*!< MDF acquisition in progress */
+  HAL_MDF_STATE_ERROR       = 0xFFU  /*!< MDF state error */
+} HAL_MDF_StateTypeDef;
+
+/**
+  * @brief  MDF clock trigger structure definition
+  */
+typedef struct
+{
+  FunctionalState Activation;  /*!< Output clock trigger enable/disable */
+  uint32_t        Source;      /*!< Output clock trigger source.
+                                    This parameter can be a value of @ref MDF_ClockTriggerSource */
+  uint32_t        Edge;        /*!< Output clock trigger edge.
+                                    This parameter can be a value of @ref MDF_ClockTriggerEdge */
+} MDF_ClockTriggerTypeDef;
+
+/**
+  * @brief  MDF output clock structure definition
+  */
+typedef struct
+{
+  FunctionalState         Activation; /*!< Output clock enable/disable */
+  uint32_t                Pins;       /*!< Output clock pins.
+                                           This parameter can be a value of @ref MDF_OuputClockPins */
+  uint32_t                Divider;    /*!< Output clock divider.
+                                           This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+  MDF_ClockTriggerTypeDef Trigger;    /*!< Output clock trigger parameters */
+} MDF_OutputClockTypeDef;
+
+/**
+  * @brief  MDF common parameters structure definition
+  */
+typedef struct
+{
+  uint32_t               InterleavedFilters; /*!< Number of filters in interleaved mode with filter 0.
+                                                  This parameter must be a number between Min_Data = 0
+                                                  and Max_Data = 5.
+                                                  @note This parameter is not used for ADF instance */
+  uint32_t               ProcClockDivider;   /*!< Processing clock divider.
+                                                  This parameter must be a number between Min_Data = 1
+                                                  and Max_Data = 128 */
+  MDF_OutputClockTypeDef OutputClock;        /*!< Output clock parameters */
+} MDF_CommonParamTypeDef;
+
+/**
+  * @brief  MDF serial interface structure definition
+  */
+typedef struct
+{
+  FunctionalState  Activation;  /*!< Serial interface enable/disable */
+  uint32_t         Mode;        /*!< Serial interface mode.
+                                     This parameter can be a value of @ref MDF_SitfMode */
+  uint32_t         ClockSource; /*!< Serial interface clock source.
+                                     This parameter can be a value of @ref MDF_SitfClockSource */
+  uint32_t         Threshold;   /*!< SPI threshold for clock absence detection or Manchester symbol threshold.
+                                     This parameter must be a number between Min_Data = 4 and Max_Data = 31 */
+} MDF_SerialInterfaceTypeDef;
+
+/**
+  * @brief  MDF init structure definition
+  */
+typedef struct
+{
+  MDF_CommonParamTypeDef      CommonParam;      /*!< MDF common parameters */
+  MDF_SerialInterfaceTypeDef  SerialInterface;  /*!< MDF serial interface parameters */
+  uint32_t                    FilterBistream;   /*!< MDF filter bitstream selection.
+                                                     This parameter can be a value of @ref MDF_FilterBitstream */
+} MDF_InitTypeDef;
+
+/**
+  * @brief  MDF handle structure definition
+  */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+typedef struct __MDF_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+{
+  MDF_Filter_TypeDef        *Instance;  /*!< MDF instance */
+  MDF_InitTypeDef            Init;      /*!< MDF init parameters */
+  DMA_HandleTypeDef         *hdma;      /*!< Pointer on DMA handler for acquisitions */
+  __IO HAL_MDF_StateTypeDef  State;     /*!< MDF state */
+  __IO uint32_t              ErrorCode; /*!< MDF error code */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+  void (*OldCallback)(struct __MDF_HandleTypeDef *hmdf,
+                      uint32_t Threshold);                        /*!< MDF out-off limit detector callback.
+                                                                       @note Not used for ADF instance */
+  void (*AcqCpltCallback)(struct __MDF_HandleTypeDef *hmdf);      /*!< MDF acquisition complete callback */
+  void (*AcqHalfCpltCallback)(struct __MDF_HandleTypeDef *hmdf);  /*!< MDF acquisition half complete callback */
+  void (*SndLvCallback)(struct __MDF_HandleTypeDef *hmdf,
+                        uint32_t SoundLevel,
+                        uint32_t AmbientNoise);                   /*!< MDF sound level callback.
+                                                                       @note Not used for MDF instance */
+  void (*SadCallback)(struct __MDF_HandleTypeDef *hmdf);          /*!< MDF sound activity detector callback.
+                                                                       @note Not used for MDF instance */
+  void (*ErrorCallback)(struct __MDF_HandleTypeDef *hmdf);        /*!< MDF error callback */
+  void (*MspInitCallback)(struct __MDF_HandleTypeDef *hmdf);      /*!< MDF MSP init callback */
+  void (*MspDeInitCallback)(struct __MDF_HandleTypeDef *hmdf);    /*!< MDF MSP de-init callback */
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+} MDF_HandleTypeDef;
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  MDF callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_MDF_OLD_CB_ID              = 0x00U, /*!< MDF out-off limit detector callback ID.
+                                               @note Not used for ADF instance */
+  HAL_MDF_ACQ_COMPLETE_CB_ID     = 0x01U, /*!< MDF acquisition complete callback ID */
+  HAL_MDF_ACQ_HALFCOMPLETE_CB_ID = 0x02U, /*!< MDF acquisition half complete callback ID */
+  HAL_MDF_SNDLVL_CB_ID           = 0x03U, /*!< MDF sound level callback ID.
+                                               @note Not used for MDF instance */
+  HAL_MDF_SAD_CB_ID              = 0x04U, /*!< MDF sound activity detector callback ID.
+                                               @note Not used for MDF instance */
+  HAL_MDF_ERROR_CB_ID            = 0x05U, /*!< MDF error callback ID */
+  HAL_MDF_MSPINIT_CB_ID          = 0x06U, /*!< MDF MSP init callback ID */
+  HAL_MDF_MSPDEINIT_CB_ID        = 0x07U  /*!< MDF MSP de-init callback ID */
+} HAL_MDF_CallbackIDTypeDef;
+
+/**
+  * @brief  MDF callback pointers definition
+  */
+typedef void (*pMDF_CallbackTypeDef)(MDF_HandleTypeDef *hmdf);
+typedef void (*pMDF_OldCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t Threshold);
+typedef void (*pMDF_SndLvlCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+/**
+  * @brief  MDF reshape filter structure definition
+  */
+typedef struct
+{
+  FunctionalState  Activation;       /*!< Reshape filter enable/disable */
+  uint32_t         DecimationRatio;  /*!< Reshape filter decimation ratio.
+                                          This parameter can be a value of @ref MDF_ReshapeDecimationRatio */
+} MDF_ReshapeFilterTypeDef;
+
+/**
+  * @brief  MDF high pass filter structure definition
+  */
+typedef struct
+{
+  FunctionalState  Activation;       /*!< High pass filter enable/disable */
+  uint32_t         CutOffFrequency;  /*!< High pass filter cut-off frequency.
+                                          This parameter can be a value of @ref MDF_HighPassCutOffFreq */
+} MDF_HighPassFilterTypeDef;
+
+/**
+  * @brief  MDF integrator structure definition
+  */
+typedef struct
+{
+  FunctionalState  Activation;      /*!< Integrator enable/disable */
+  uint32_t         Value;           /*!< Integrator value.
+                                         This parameter must be a number between Min_Data = 2 and Max_Data = 128 */
+  uint32_t         OutputDivision;  /*!< Integrator output division.
+                                         This parameter can be a value of @ref MDF_IntegratorOutputDiv */
+} MDF_IntegratorTypeDef;
+
+/**
+  * @brief  MDF sound activity structure definition
+  */
+typedef struct
+{
+  FunctionalState  Activation;            /*!< Sound activity detector enable/disable */
+  uint32_t         Mode;                  /*!< Sound activity detector mode.
+                                               This parameter can be a value of @ref MDF_SadMode */
+  uint32_t         FrameSize;             /*!< Size of one frame to compute short-term signal level.
+                                               This parameter can be a value of @ref MDF_SadFrameSize */
+  FunctionalState  Hysteresis;            /*!< Hysteresis enable/disable.
+                                               @note This parameter is not used if Mode is set
+                                                     to MDF_SAD_AMBIENT_NOISE_ESTIMATOR */
+  uint32_t         SoundTriggerEvent;     /*!< Sound trigger event configuration.
+                                               This parameter can be a value of @ref MDF_SadSoundTriggerEvent */
+  uint32_t         DataMemoryTransfer;    /*!< Data memory transfer mode.
+                                               This parameter can be a value of @ref MDF_SadDataMemoryTransfer */
+  uint32_t         MinNoiseLevel;         /*!< Minimum noise level.
+                                               This parameter must be a number between Min_Data = 0
+                                               and Max_Data = 8191 */
+  uint32_t         HangoverWindow;        /*!< Hangover time window in frames.
+                                               This parameter can be a value of @ref MDF_SadHangoverWindow */
+  uint32_t         LearningFrames;        /*!< Number of learning frames for the first estimation of noise level.
+                                               This parameter can be a value of @ref MDF_SadLearningFrames */
+  uint32_t         AmbientNoiseSlope;     /*!< Ambient noise slope control.
+                                               This parameter must be a number between Min_Data = 0 and Max_Data = 7.
+                                               @note This parameter is not used if Mode is set
+                                                     to MDF_SAD_SOUND_DETECTOR */
+  uint32_t         SignalNoiseThreshold;  /*!< Signal to noise threshold.
+                                               This parameter can be a value of @ref MDF_SadSignalNoiseThreshold */
+  FunctionalState  SoundLevelInterrupt;    /*!< Sound level interrupt enable/disable.
+                                               @note This interrupt is mainly used for debug purpose*/
+
+} MDF_SoundActivityTypeDef;
+
+/**
+  * @brief  MDF filter trigger structure definition
+  */
+typedef struct
+{
+  uint32_t  Source;  /*!< Filter trigger source.
+                          This parameter can be a value of @ref MDF_FilterTriggerSource */
+  uint32_t  Edge;    /*!< Filter trigger edge.
+                          This parameter can be a value of @ref MDF_FilterTriggerEdge */
+} MDF_FilterTriggerTypeDef;
+
+/**
+  * @brief  MDF filter configuration structure definition
+  */
+typedef struct
+{
+  uint32_t                  DataSource;      /*!< Filter data source.
+                                                  This parameter can be a value of @ref MDF_DataSource */
+  uint32_t                  Delay;           /*!< Delay to apply on data source in number of samples.
+                                                  This parameter must be a number between Min_Data = 0
+                                                  and Max_Data = 127 */
+  uint32_t                  CicMode;         /*!< CIC filter mode.
+                                                  This parameter can be a value of @ref MDF_CicMode */
+  uint32_t                  DecimationRatio; /*!< Filter decimation ratio.
+                                                  This parameter must be a number between Min_Data = 2
+                                                  and Max_Data = 512 */
+  int32_t                   Offset;          /*!< Filter offset error compensation.
+                                                  This parameter must be a number between Min_Data = -33554432
+                                                  and Max_Data = 33554431.
+                                                  @note This parameter is not used for ADF instance */
+  int32_t                   Gain;            /*!< Filter gain in step of around 3db (from -48db to 72dB).
+                                                  This parameter must be a number between Min_Data = -16
+                                                  and Max_Data = 24 */
+  MDF_ReshapeFilterTypeDef  ReshapeFilter;   /*!< Reshape filter configuration */
+  MDF_HighPassFilterTypeDef HighPassFilter;  /*!< High pass filter configuration */
+  MDF_IntegratorTypeDef     Integrator;      /*!< Integrator configuration.
+                                                  @note This parameter is not used for ADF instance */
+  MDF_SoundActivityTypeDef  SoundActivity;   /*!< Sound activity detector configuration.
+                                                  @note This parameter is not used for MDF instance */
+  uint32_t                  AcquisitionMode; /*!< Filter acquisition mode.
+                                                  This parameter can be a value of @ref MDF_AcquisitionMode */
+  uint32_t                  FifoThreshold;   /*!< Filter RXFIFO threshold.
+                                                  This parameter can be a value of @ref MDF_FifoThreshold */
+  uint32_t                  DiscardSamples;  /*!< Number of samples to discard after filter enable.
+                                                  This parameter must be a number between Min_Data = 0
+                                                  and Max_Data = 255 */
+  MDF_FilterTriggerTypeDef  Trigger;         /*!< Filter trigger configuration.
+                                                  @note This parameter is not used if AcquisitionMode is set
+                                                        to MDF_MODE_ASYNC_CONT or MDF_MODE_ASYNC_SINGLE */
+  uint32_t                  SnapshotFormat;  /*!< Snapshot format.
+                                                  This parameter can be a value of @ref MDF_SnapshotFormat.
+                                                  @note This parameter is used only if AcquisitionMode is set
+                                                        to MDF_MODE_SYNC_SNAPSHOT and for MDF instance */
+} MDF_FilterConfigTypeDef;
+
+/**
+  * @brief  MDF snapshot parameters structure definition
+  */
+typedef struct
+{
+  int32_t   Value;              /*!< Snapshot acquisition value on 16 or 23 MSB depending on snapshot format */
+  uint32_t  DecimationCounter;  /*!< Decimation counter value when snapshot trigger occurs */
+  uint32_t  IntegratorCounter;  /*!< Integrator counter value when snapshot trigger occurs.
+                                     This value is available only if snapshot format is 16 bits resolution */
+} MDF_SnapshotParamTypeDef;
+
+/**
+  * @brief  MDF DMA configuration structure definition
+  */
+typedef struct
+{
+  uint32_t         Address;     /*!< DMA destination address */
+  uint32_t         DataLength;  /*!< Length of data to transfer in bytes */
+  FunctionalState  MsbOnly;     /*!< Transfer only the 16MSB of the acquistion data */
+} MDF_DmaConfigTypeDef;
+
+/**
+  * @brief  MDF short-circuit detector configuration structure definition
+  */
+typedef struct
+{
+  uint32_t  Threshold;    /*!< Short-circuit detector threshold.
+                               This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
+  uint32_t  BreakSignal;  /*!< Break signal assignment for short-circuit detector.
+                               This parameter can be a values combination of @ref MDF_BreakSignals */
+} MDF_ScdConfigTypeDef;
+
+/**
+  * @brief  MDF out-off limit detector configuration structure definition
+  */
+typedef struct
+{
+  uint32_t  OldCicMode;          /*!< Out-off limit detector CIC filter mode.
+                                      This parameter can be a value of @ref MDF_OldCicMode */
+  uint32_t  OldDecimationRatio;  /*!< Out-off limit detector decimation ratio.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+  int32_t   HighThreshold;       /*!< Out-off limit detector high threshold.
+                                      This parameter must be a number between Min_Data = -33554432
+                                      and Max_Data = 33554431 */
+  int32_t   LowThreshold;        /*!< Out-off limit detector low threshold.
+                                      This parameter must be a number between Min_Data = -33554432
+                                      and Max_Data = 33554431 */
+  uint32_t  OldEventConfig;      /*!< Out-off limit event configuration.
+                                      This parameter can be a value of @ref MDF_OldEventConfig */
+  uint32_t  BreakSignal;         /*!< Break signal assignment for out-off limit detector.
+                                      This parameter can be a values combination of @ref MDF_BreakSignals */
+} MDF_OldConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MDF_Exported_Constants  MDF Exported Constants
+  * @{
+  */
+
+/** @defgroup MDF_ErrorCode MDF error code
+  * @{
+  */
+#define MDF_ERROR_NONE                  0x00000000U /*!< No error */
+#define MDF_ERROR_ACQUISITION_OVERFLOW  0x00000001U /*!< Overflow occurs during acquisition */
+#define MDF_ERROR_RSF_OVERRUN           0x00000002U /*!< Overrun occurs on reshape filter */
+#define MDF_ERROR_CLOCK_ABSENCE         0x00000004U /*!< Clock absence detection occurs */
+#define MDF_ERROR_SHORT_CIRCUIT         0x00000008U /*!< Short circuit detection occurs.
+                                                         @note Not used for ADF instance */
+#define MDF_ERROR_SATURATION            0x00000010U /*!< Saturation detection occurs */
+#define MDF_ERROR_OUT_OFF_LIMIT         0x00000020U /*!< Out-off limit detection occurs.
+                                                         @note Not used for ADF instance */
+#define MDF_ERROR_DMA                   0x00000040U /*!< DMA error occurs */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+#define MDF_ERROR_INVALID_CALLBACK      0x00000080U /*!< Invalid callback error occurs */
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_ClockTriggerSource MDF output clock trigger source
+  * @{
+  */
+#define MDF_CLOCK_TRIG_TRGO        0x00000000U
+#define MDF_CLOCK_TRIG_EXTI15      MDF_CKGCR_TRGSRC_1
+#define MDF_CLOCK_TRIG_EXTI11     (MDF_CKGCR_TRGSRC_0 | \
+                                   MDF_CKGCR_TRGSRC_1)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM1_TRGO   MDF_CKGCR_TRGSRC_2      /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM1_TRGO2 (MDF_CKGCR_TRGSRC_0 | \
+                                   MDF_CKGCR_TRGSRC_2)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM3_TRGO  (MDF_CKGCR_TRGSRC_1 | \
+                                   MDF_CKGCR_TRGSRC_2)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM4_TRGO  (MDF_CKGCR_TRGSRC_0 | \
+                                   MDF_CKGCR_TRGSRC_1 | \
+                                   MDF_CKGCR_TRGSRC_2)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM6_TRGO   MDF_CKGCR_TRGSRC_3      /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM7_TRGO  (MDF_CKGCR_TRGSRC_0 | \
+                                   MDF_CKGCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM8_TRGO  (MDF_CKGCR_TRGSRC_1 | \
+                                   MDF_CKGCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM8_TRGO2 (MDF_CKGCR_TRGSRC_0 | \
+                                   MDF_CKGCR_TRGSRC_1 | \
+                                   MDF_CKGCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_TIM15_TRGO (MDF_CKGCR_TRGSRC_2 | \
+                                   MDF_CKGCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_LPTIM1_OUT (MDF_CKGCR_TRGSRC_0 | \
+                                   MDF_CKGCR_TRGSRC_2 | \
+                                   MDF_CKGCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_SAD_DET    (MDF_CKGCR_TRGSRC_1 | \
+                                   MDF_CKGCR_TRGSRC_2 | \
+                                   MDF_CKGCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_CLOCK_TRIG_SAD_TRGO    MDF_CKGCR_TRGSRC        /*!< @note Not available for ADF instance */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_ClockTriggerEdge MDF output clock trigger edge
+  * @{
+  */
+#define MDF_CLOCK_TRIG_RISING_EDGE   0x00000000U        /*!< Rising edge */
+#define MDF_CLOCK_TRIG_FALLING_EDGE  MDF_CKGCR_TRGSENS  /*!< Falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_OuputClockPins MDF output clock pins
+  * @{
+  */
+#define MDF_OUTPUT_CLOCK_0    MDF_CKGCR_CCK0DIR      /*!< MDF_CCK0 is used as output clock */
+#define MDF_OUTPUT_CLOCK_1    MDF_CKGCR_CCK1DIR      /*!< MDF_CCK1 is used as output clock */
+#define MDF_OUTPUT_CLOCK_ALL (MDF_CKGCR_CCK0DIR | \
+                              MDF_CKGCR_CCK1DIR)     /*!< MDF_CCK0 and MDF_CCK1 are used as output clock */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SitfMode MDF serial interface mode
+  * @{
+  */
+#define MDF_SITF_LF_MASTER_SPI_MODE       0x00000000U           /*!< Low frequency master SPI mode */
+#define MDF_SITF_NORMAL_SPI_MODE          MDF_SITFCR_SITFMOD_0  /*!< Normal SPI mode */
+#define MDF_SITF_MANCHESTER_FALLING_MODE  MDF_SITFCR_SITFMOD_1  /*!< Manchester mode rising edge logic 0
+                                                                     and falling edge logic 1 */
+#define MDF_SITF_MANCHESTER_RISING_MODE   MDF_SITFCR_SITFMOD    /*!< Manchester mode rising edge logic 1
+                                                                     and falling edge logic 0 */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SitfClockSource MDF serial interface clock source
+  * @{
+  */
+#define MDF_SITF_CCK0_SOURCE  0x00000000U          /*!< Common clock 0 source */
+#define MDF_SITF_CCK1_SOURCE  MDF_SITFCR_SCKSRC_0  /*!< Common clock 1 source */
+#define MDF_SITF_CKI_SOURCE   MDF_SITFCR_SCKSRC_1  /*!< Dedicated input clock source.
+                                                        @note Not available for ADF instance */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_FilterBitstream MDF filter bitstream
+  * @{
+  */
+#define MDF_BITSTREAM0_RISING   0x00000000U
+#define MDF_BITSTREAM0_FALLING  MDF_BSMXCR_BSSEL_0
+#define MDF_BITSTREAM1_RISING   MDF_BSMXCR_BSSEL_1      /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM1_FALLING (MDF_BSMXCR_BSSEL_0 | \
+                                MDF_BSMXCR_BSSEL_1)     /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM2_RISING   MDF_BSMXCR_BSSEL_2      /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM2_FALLING (MDF_BSMXCR_BSSEL_0 | \
+                                MDF_BSMXCR_BSSEL_2)     /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM3_RISING  (MDF_BSMXCR_BSSEL_1 | \
+                                MDF_BSMXCR_BSSEL_2)     /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM3_FALLING (MDF_BSMXCR_BSSEL_0 | \
+                                MDF_BSMXCR_BSSEL_1 | \
+                                MDF_BSMXCR_BSSEL_2)     /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM4_RISING   MDF_BSMXCR_BSSEL_3      /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM4_FALLING (MDF_BSMXCR_BSSEL_0 | \
+                                MDF_BSMXCR_BSSEL_3)     /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM5_RISING  (MDF_BSMXCR_BSSEL_1 | \
+                                MDF_BSMXCR_BSSEL_3)     /*!< @note Not available for ADF instance */
+#define MDF_BITSTREAM5_FALLING (MDF_BSMXCR_BSSEL_0 | \
+                                MDF_BSMXCR_BSSEL_1 | \
+                                MDF_BSMXCR_BSSEL_3)     /*!< @note Not available for ADF instance */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_ReshapeDecimationRatio MDF reshape filter decimation ratio
+  * @{
+  */
+#define MDF_RSF_DECIMATION_RATIO_4  0x00000000U          /*!< Reshape filter decimation ratio is 4 */
+#define MDF_RSF_DECIMATION_RATIO_1  MDF_DFLTRSFR_RSFLTD  /*!< Reshape filter decimation ratio is 1 */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_HighPassCutOffFreq MDF high pass filter cut-off frequency
+  * @{
+  */
+#define MDF_HPF_CUTOFF_0_000625FPCM  0x00000000U          /*!< Cut-off frequency of 0.000625xFpcm */
+#define MDF_HPF_CUTOFF_0_00125FPCM   MDF_DFLTRSFR_HPFC_0  /*!< Cut-off frequency of 0.00125xFpcm */
+#define MDF_HPF_CUTOFF_0_0025FPCM    MDF_DFLTRSFR_HPFC_1  /*!< Cut-off frequency of 0.0025xFpcm */
+#define MDF_HPF_CUTOFF_0_0095FPCM    MDF_DFLTRSFR_HPFC    /*!< Cut-off frequency of 0.0095xFpcm */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_IntegratorOutputDiv MDF integrator output division
+  * @{
+  */
+#define MDF_INTEGRATOR_OUTPUT_DIV_128  0x00000000U            /*!< Integrator data outputs divided by 128 */
+#define MDF_INTEGRATOR_OUTPUT_DIV_32   MDF_DFLTINTR_INTDIV_0  /*!< Integrator data outputs divided by 32 */
+#define MDF_INTEGRATOR_OUTPUT_DIV_4    MDF_DFLTINTR_INTDIV_1  /*!< Integrator data outputs divided by 4 */
+#define MDF_INTEGRATOR_OUTPUT_NO_DIV   MDF_DFLTINTR_INTDIV    /*!< Integrator data outputs not divided */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SadMode MDF sound activity detector mode
+  * @{
+  */
+#define MDF_SAD_VOICE_ACTIVITY_DETECTOR  0x00000000U         /*!< Voice activity detector */
+#define MDF_SAD_SOUND_DETECTOR           MDF_SADCR_SADMOD_0  /*!< Sound detector */
+#define MDF_SAD_AMBIENT_NOISE_DETECTOR   MDF_SADCR_SADMOD    /*!< Ambient noise detector */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SadFrameSize MDF sound activity detector frame size
+  * @{
+  */
+#define MDF_SAD_8_PCM_SAMPLES    0x00000000U                               /*!< Frame size of 8 PCM samples */
+#define MDF_SAD_16_PCM_SAMPLES   MDF_SADCR_FRSIZE_0                        /*!< Frame size of 16 PCM samples */
+#define MDF_SAD_32_PCM_SAMPLES   MDF_SADCR_FRSIZE_1                        /*!< Frame size of 32 PCM samples */
+#define MDF_SAD_64_PCM_SAMPLES  (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_1)  /*!< Frame size of 64 PCM samples */
+#define MDF_SAD_128_PCM_SAMPLES  MDF_SADCR_FRSIZE_2                        /*!< Frame size of 128 PCM samples */
+#define MDF_SAD_256_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_2)  /*!< Frame size of 256 PCM samples */
+#define MDF_SAD_512_PCM_SAMPLES  MDF_SADCR_FRSIZE                          /*!< Frame size of 512 PCM samples */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SadSoundTriggerEvent MDF sound activity detector trigger event
+  * @{
+  */
+#define MDF_SAD_ENTER_DETECT       0x00000000U       /*!< Event when SAD enters in detect state */
+#define MDF_SAD_ENTER_EXIT_DETECT  MDF_SADCR_DETCFG  /*!< Event when SAD enters or exits from detect state */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SadDataMemoryTransfer MDF sound activity detector data memory transfer mode
+  * @{
+  */
+#define MDF_SAD_NO_MEMORY_TRANSFER         0x00000000U         /*!< No memory transfer */
+#define MDF_SAD_MEMORY_TRANSFER_IN_DETECT  MDF_SADCR_DATCAP_0  /*!< Memory transfer only in detect state */
+#define MDF_SAD_MEMORY_TRANSFER_ALWAYS     MDF_SADCR_DATCAP    /*!< Memory transfer always */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SadHangoverWindow MDF sound activity detector data hangover time window
+  * @{
+  */
+#define MDF_SAD_HANGOVER_4_FRAMES    0x00000000U              /*!< Hangover window of 4 frames */
+#define MDF_SAD_HANGOVER_8_FRAMES    MDF_SADCFGR_HGOVR_0      /*!< Hangover window of 8 frames */
+#define MDF_SAD_HANGOVER_16_FRAMES   MDF_SADCFGR_HGOVR_1      /*!< Hangover window of 16 frames */
+#define MDF_SAD_HANGOVER_32_FRAMES  (MDF_SADCFGR_HGOVR_0 | \
+                                     MDF_SADCFGR_HGOVR_1)     /*!< Hangover window of 32 frames */
+#define MDF_SAD_HANGOVER_64_FRAMES   MDF_SADCFGR_HGOVR_2      /*!< Hangover window of 64 frames */
+#define MDF_SAD_HANGOVER_128_FRAMES (MDF_SADCFGR_HGOVR_0 | \
+                                     MDF_SADCFGR_HGOVR_2)     /*!< Hangover window of 128 frames */
+#define MDF_SAD_HANGOVER_256_FRAMES (MDF_SADCFGR_HGOVR_1 | \
+                                     MDF_SADCFGR_HGOVR_2)     /*!< Hangover window of 256 frames */
+#define MDF_SAD_HANGOVER_512_FRAMES (MDF_SADCFGR_HGOVR_0 | \
+                                     MDF_SADCFGR_HGOVR_1 | \
+                                     MDF_SADCFGR_HGOVR_2)     /*!< Hangover window of 512 frames */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SadLearningFrames MDF sound activity detector data learning frames
+  * @{
+  */
+#define MDF_SAD_LEARNING_2_FRAMES   0x00000000U                                 /*!< 2 learning frames */
+#define MDF_SAD_LEARNING_4_FRAMES   MDF_SADCFGR_LFRNB_0                         /*!< 4 learning frames */
+#define MDF_SAD_LEARNING_8_FRAMES   MDF_SADCFGR_LFRNB_1                         /*!< 8 learning frames */
+#define MDF_SAD_LEARNING_16_FRAMES (MDF_SADCFGR_LFRNB_0 | MDF_SADCFGR_LFRNB_1)  /*!< 16 learning frames */
+#define MDF_SAD_LEARNING_32_FRAMES  MDF_SADCFGR_LFRNB                           /*!< 32 learning frames */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SadSignalNoiseThreshold MDF sound activity detector data signal to noise threshold
+  * @{
+  */
+#define MDF_SAD_SIGNAL_NOISE_3_5DB   0x00000000U              /*!< Signal to noise threshold is 3.5dB */
+#define MDF_SAD_SIGNAL_NOISE_6DB     MDF_SADCFGR_SNTHR_0      /*!< Signal to noise threshold is 6dB */
+#define MDF_SAD_SIGNAL_NOISE_9_5DB   MDF_SADCFGR_SNTHR_1      /*!< Signal to noise threshold is 9.5dB */
+#define MDF_SAD_SIGNAL_NOISE_12DB   (MDF_SADCFGR_SNTHR_0 | \
+                                     MDF_SADCFGR_SNTHR_1)     /*!< Signal to noise threshold is 12dB */
+#define MDF_SAD_SIGNAL_NOISE_15_6DB  MDF_SADCFGR_SNTHR_2      /*!< Signal to noise threshold is 15.6dB */
+#define MDF_SAD_SIGNAL_NOISE_18DB   (MDF_SADCFGR_SNTHR_0 | \
+                                     MDF_SADCFGR_SNTHR_2)     /*!< Signal to noise threshold is 18dB */
+#define MDF_SAD_SIGNAL_NOISE_21_6DB (MDF_SADCFGR_SNTHR_1 | \
+                                     MDF_SADCFGR_SNTHR_2)     /*!< Signal to noise threshold is 21.6dB */
+#define MDF_SAD_SIGNAL_NOISE_24_1DB (MDF_SADCFGR_SNTHR_0 | \
+                                     MDF_SADCFGR_SNTHR_1 | \
+                                     MDF_SADCFGR_SNTHR_2)     /*!< Signal to noise threshold is 24.1dB */
+#define MDF_SAD_SIGNAL_NOISE_27_6DB  MDF_SADCFGR_SNTHR_3      /*!< Signal to noise threshold is 27.6dB */
+#define MDF_SAD_SIGNAL_NOISE_30_1DB (MDF_SADCFGR_SNTHR_0 | \
+                                     MDF_SADCFGR_SNTHR_3)     /*!< Signal to noise threshold is 30.1dB */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_FilterTriggerSource MDF filter trigger source
+  * @{
+  */
+#define MDF_FILTER_TRIG_TRGO         0x00000000U
+#define MDF_FILTER_TRIG_OLD_EVENT    MDF_DFLTCR_TRGSRC_0      /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_EXTI15       MDF_DFLTCR_TRGSRC_1
+#define MDF_FILTER_TRIG_EXTI11      (MDF_DFLTCR_TRGSRC_0 | \
+                                     MDF_DFLTCR_TRGSRC_1)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM1_TRGO    MDF_DFLTCR_TRGSRC_2      /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM1_TRGO2  (MDF_DFLTCR_TRGSRC_0 | \
+                                     MDF_DFLTCR_TRGSRC_2)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM3_TRGO   (MDF_DFLTCR_TRGSRC_1 | \
+                                     MDF_DFLTCR_TRGSRC_2)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM4_TRGO   (MDF_DFLTCR_TRGSRC_0 | \
+                                     MDF_DFLTCR_TRGSRC_1 | \
+                                     MDF_DFLTCR_TRGSRC_2)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM6_TRGO    MDF_DFLTCR_TRGSRC_3      /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM7_TRGO   (MDF_DFLTCR_TRGSRC_0 | \
+                                     MDF_DFLTCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM8_TRGO   (MDF_DFLTCR_TRGSRC_1 | \
+                                     MDF_DFLTCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM8_TRGO2  (MDF_DFLTCR_TRGSRC_0 | \
+                                     MDF_DFLTCR_TRGSRC_1 | \
+                                     MDF_DFLTCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_TIM15_TRGO  (MDF_DFLTCR_TRGSRC_2 | \
+                                     MDF_DFLTCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_LPTIM1_OUT  (MDF_DFLTCR_TRGSRC_0 | \
+                                     MDF_DFLTCR_TRGSRC_2 | \
+                                     MDF_DFLTCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_ADF_SAD_DET (MDF_DFLTCR_TRGSRC_1 | \
+                                     MDF_DFLTCR_TRGSRC_2 | \
+                                     MDF_DFLTCR_TRGSRC_3)     /*!< @note Not available for ADF instance */
+#define MDF_FILTER_TRIG_ADF_TRGO     MDF_DFLTCR_TRGSRC        /*!< @note Not available for ADF instance */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_FilterTriggerEdge MDF filter trigger edge
+  * @{
+  */
+#define MDF_FILTER_TRIG_RISING_EDGE   0x00000000U         /*!< Rising edge */
+#define MDF_FILTER_TRIG_FALLING_EDGE  MDF_DFLTCR_TRGSENS  /*!< Falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_DataSource MDF data source
+  * @{
+  */
+#define MDF_DATA_SOURCE_BSMX     0x00000000U            /*!< Data from bitstream matrix */
+#define MDF_DATA_SOURCE_ADCITF1  MDF_DFLTCICR_DATSRC_1  /*!< Data from ADC interface 1.
+                                                             @note Not available for ADF instance */
+#define MDF_DATA_SOURCE_ADCITF2  MDF_DFLTCICR_DATSRC    /*!< Data from ADC interface 2.
+                                                             @note Not available for ADF instance */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_CicMode MDF CIC mode
+  * @{
+  */
+#define MDF_TWO_FILTERS_MCIC_FASTSINC  0x00000000U                /*!< Two filters, main filter in FastSinc order.
+                                                                       @note Not available for ADF instance */
+#define MDF_TWO_FILTERS_MCIC_SINC1     MDF_DFLTCICR_CICMOD_0      /*!< Two filters, main filter in Sinc1 order.
+                                                                       @note Not available for ADF instance */
+#define MDF_TWO_FILTERS_MCIC_SINC2     MDF_DFLTCICR_CICMOD_1      /*!< Two filters, main filter in Sinc2 order.
+                                                                       @note Not available for ADF instance */
+#define MDF_TWO_FILTERS_MCIC_SINC3    (MDF_DFLTCICR_CICMOD_0 | \
+                                       MDF_DFLTCICR_CICMOD_1)     /*!< Two filters, main filter in Sinc3 order.
+                                                                       @note Not available for ADF instance */
+#define MDF_ONE_FILTER_SINC4           MDF_DFLTCICR_CICMOD_2      /*!< One filter in Sinc4 order */
+#define MDF_ONE_FILTER_SINC5          (MDF_DFLTCICR_CICMOD_0 | \
+                                       MDF_DFLTCICR_CICMOD_2)     /*!< One filter in Sinc5 order */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_AcquisitionMode MDF acquisition mode
+  * @{
+  */
+#define MDF_MODE_ASYNC_CONT     0x00000000U              /*!< Asynchronous, continuous acquisition mode */
+#define MDF_MODE_ASYNC_SINGLE   MDF_DFLTCR_ACQMOD_0      /*!< Asynchronous, single-shot acquisition mode.
+                                                              @note Not available for ADF instance with SAD usage */
+#define MDF_MODE_SYNC_CONT      MDF_DFLTCR_ACQMOD_1      /*!< Synchronous, continuous acquisition mode */
+#define MDF_MODE_SYNC_SINGLE   (MDF_DFLTCR_ACQMOD_0 | \
+                                MDF_DFLTCR_ACQMOD_1)     /*!< Synchronous, single-shot acquisition mode.
+                                                              @note Not available for ADF instance with SAD usage*/
+#define MDF_MODE_WINDOW_CONT    MDF_DFLTCR_ACQMOD_2      /*!< Window, continuous acquisition mode.
+                                                              @note Not available for ADF instance with SAD usage*/
+#define MDF_MODE_SYNC_SNAPSHOT (MDF_DFLTCR_ACQMOD_0 | \
+                                MDF_DFLTCR_ACQMOD_2)     /*!< Synchronous, snapshot acquisition mode.
+                                                              @note Not available for ADF instance */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_FifoThreshold MDF RXFIFO threshold
+  * @{
+  */
+#define MDF_FIFO_THRESHOLD_NOT_EMPTY  0x00000000U     /*!< Event generated when RXFIFO is not empty */
+#define MDF_FIFO_THRESHOLD_HALF_FULL  MDF_DFLTCR_FTH  /*!< Event generated when RXFIFO is half_full */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_SnapshotFormat MDF snapshot format
+  * @{
+  */
+#define MDF_SNAPSHOT_23BITS  0x00000000U         /*!< Snapshot data resolution of 23 bits */
+#define MDF_SNAPSHOT_16BITS  MDF_DFLTCR_SNPSFMT  /*!< Snapshot data resolution of 16 bits */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_BreakSignals MDF break signals
+  * @{
+  */
+#define MDF_NO_BREAK_SIGNAL     0x00000000U /*!< No break signal */
+#define MDF_TIM1_BREAK_SIGNAL   0x00000001U /*!< TIM1_BREAK signal */
+#define MDF_TIM1_BREAK2_SIGNAL  0x00000002U /*!< TIM1_BREAK2 signal */
+#define MDF_TIM8_BREAK_SIGNAL   0x00000004U /*!< TIM8_BREAK signal */
+#define MDF_TIM8_BREAK2_SIGNAL  0x00000008U /*!< TIM8_BREAK2 signal */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_OldCicMode MDF out-off limit detector CIC mode
+  * @{
+  */
+#define MDF_OLD_FILTER_FASTSINC  0x00000000U        /*!< Out-off limit detector filter in FastSinc order */
+#define MDF_OLD_FILTER_SINC1     MDF_OLDCR_ACICN_0  /*!< Out-off limit detector filter in Sinc1 order */
+#define MDF_OLD_FILTER_SINC2     MDF_OLDCR_ACICN_1  /*!< Out-off limit detector filter in Sinc2 order */
+#define MDF_OLD_FILTER_SINC3     MDF_OLDCR_ACICN    /*!< Out-off limit detector filter in Sinc3 order */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_OldEventConfig MDF out-off limit detector event configuration
+  * @{
+  */
+#define MDF_OLD_SIGNAL_OUTSIDE_THRESHOLDS  0x00000000U      /*!< Out-off limit detector event is generated
+                                                                 if signal is outside thresholds */
+#define MDF_OLD_SIGNAL_IN_THRESHOLDS       MDF_OLDCR_THINB  /*!< Out-off limit detector event is generated
+                                                                 if signal is in thresholds */
+/**
+  * @}
+  */
+
+/** @defgroup MDF_OldThresholdInfo MDF out-off limit detector threshold information
+  * @{
+  */
+#define MDF_OLD_IN_THRESHOLDS   0x00000000U  /*!< The signal was in thresholds when out-off limit detection occurs */
+#define MDF_OLD_HIGH_THRESHOLD  0x00000001U  /*!< The signal was higher than high threshold
+                                                  when out-off limit detection occurs */
+#define MDF_OLD_LOW_THRESHOLD   0x00000002U  /*!< The signal was lower than low threshold
+                                                  when out-off limit detection occurs */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MDF_Exported_Macros  MDF Exported Macros
+  * @{
+  */
+
+/** @brief  Reset MDF handle state.
+  * @param  __HANDLE__ MDF handle.
+  * @retval None
+  */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) do{                                             \
+                                                      (__HANDLE__)->State = HAL_MDF_STATE_RESET; \
+                                                      (__HANDLE__)->MspInitCallback = NULL;      \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                    } while(0)
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDF_STATE_RESET)
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MDF_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup MDF_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf);
+void              HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf);
+void              HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf);
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef        *hmdf,
+                                           HAL_MDF_CallbackIDTypeDef CallbackID,
+                                           pMDF_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef        *hmdf,
+                                             HAL_MDF_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_MDF_RegisterOldCallback(MDF_HandleTypeDef      *hmdf,
+                                              pMDF_OldCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MDF_UnRegisterOldCallback(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef         *hmdf,
+                                                 pMDF_SndLvlCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Acquisition functions  *****************************************************/
+/** @addtogroup MDF_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue);
+HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam);
+HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig,
+                                       const MDF_DmaConfigTypeDef *pDmaConfig);
+HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay);
+HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay);
+HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain);
+HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain);
+HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset);
+HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset);
+HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel,
+                                        uint32_t *pAmbientNoise);
+HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+void              HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf);
+void              HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf);
+void              HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise);
+void              HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf);
+/**
+  * @}
+  */
+
+/* Clock absence detection functions  *****************************************/
+/** @addtogroup MDF_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf);
+/**
+  * @}
+  */
+
+/* Short circuit detection functions  *****************************************/
+/** @addtogroup MDF_Exported_Functions_Group4
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig);
+HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig);
+HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf);
+/**
+  * @}
+  */
+
+/* Out-off limit detection functions  *****************************************/
+/** @addtogroup MDF_Exported_Functions_Group5
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig);
+HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo);
+HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf);
+HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig);
+HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf);
+void              HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo);
+/**
+  * @}
+  */
+
+/* Generic functions  *********************************************************/
+/** @addtogroup MDF_Exported_Functions_Group6
+  * @{
+  */
+void                 HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf);
+void                 HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf);
+HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf);
+uint32_t             HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDF_Private_Macros  MDF Private Macros
+  * @{
+  */
+#define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \
+                                ((PARAM) == MDF1_Filter1) || \
+                                ((PARAM) == MDF1_Filter2) || \
+                                ((PARAM) == MDF1_Filter3) || \
+                                ((PARAM) == MDF1_Filter4) || \
+                                ((PARAM) == MDF1_Filter5))
+
+#define IS_ADF_INSTANCE(PARAM) ((PARAM) == ADF1_Filter0)
+
+#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING)  || \
+                                        ((PARAM) == MDF_BITSTREAM0_FALLING) || \
+                                        ((PARAM) == MDF_BITSTREAM1_RISING)  || \
+                                        ((PARAM) == MDF_BITSTREAM1_FALLING) || \
+                                        ((PARAM) == MDF_BITSTREAM2_RISING)  || \
+                                        ((PARAM) == MDF_BITSTREAM2_FALLING) || \
+                                        ((PARAM) == MDF_BITSTREAM3_RISING)  || \
+                                        ((PARAM) == MDF_BITSTREAM3_FALLING) || \
+                                        ((PARAM) == MDF_BITSTREAM4_RISING)  || \
+                                        ((PARAM) == MDF_BITSTREAM4_FALLING) || \
+                                        ((PARAM) == MDF_BITSTREAM5_RISING)  || \
+                                        ((PARAM) == MDF_BITSTREAM5_FALLING))
+
+#define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 5U)
+
+#define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U))
+
+#define IS_MDF_OUTPUT_CLOCK_PINS(PARAM) (((PARAM) == MDF_OUTPUT_CLOCK_0) || \
+                                         ((PARAM) == MDF_OUTPUT_CLOCK_1) || \
+                                         ((PARAM) == MDF_OUTPUT_CLOCK_ALL))
+
+#define IS_MDF_OUTPUT_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 16U))
+
+#define IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO)       || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM1_TRGO)  || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM1_TRGO2) || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM8_TRGO)  || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM8_TRGO2) || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM3_TRGO)  || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM4_TRGO)  || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM6_TRGO)  || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM7_TRGO)  || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_TIM15_TRGO) || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_SAD_DET)    || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_EXTI11)     || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_EXTI15)     || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_LPTIM1_OUT) || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_SAD_TRGO))
+
+#define IS_ADF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO)       || \
+                                                   ((PARAM) == MDF_CLOCK_TRIG_EXTI15))
+
+#define IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_RISING_EDGE) || \
+                                                 ((PARAM) == MDF_CLOCK_TRIG_FALLING_EDGE))
+
+#define IS_MDF_SITF_MODE(PARAM) (((PARAM) == MDF_SITF_LF_MASTER_SPI_MODE)      || \
+                                 ((PARAM) == MDF_SITF_NORMAL_SPI_MODE)         || \
+                                 ((PARAM) == MDF_SITF_MANCHESTER_FALLING_MODE) || \
+                                 ((PARAM) == MDF_SITF_MANCHESTER_RISING_MODE))
+
+#define IS_MDF_SITF_CLOCK_SOURCE(PARAM) (((PARAM) == MDF_SITF_CCK0_SOURCE) || \
+                                         ((PARAM) == MDF_SITF_CCK1_SOURCE) || \
+                                         ((PARAM) == MDF_SITF_CKI_SOURCE))
+
+#define IS_MDF_SITF_THRESHOLD(PARAM) ((4U <= (PARAM)) && ((PARAM) <= 31U))
+
+#define IS_MDF_CIC_MODE(PARAM) (((PARAM) == MDF_TWO_FILTERS_MCIC_FASTSINC) || \
+                                ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC1)    || \
+                                ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC2)    || \
+                                ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC3)    || \
+                                ((PARAM) == MDF_ONE_FILTER_SINC4)          || \
+                                ((PARAM) == MDF_ONE_FILTER_SINC5))
+
+#define IS_ADF_CIC_MODE(PARAM) (((PARAM) == MDF_ONE_FILTER_SINC4) || \
+                                ((PARAM) == MDF_ONE_FILTER_SINC5))
+
+#define IS_MDF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT)   || \
+                                        ((PARAM) == MDF_MODE_ASYNC_SINGLE) || \
+                                        ((PARAM) == MDF_MODE_SYNC_CONT)    || \
+                                        ((PARAM) == MDF_MODE_SYNC_SINGLE)  || \
+                                        ((PARAM) == MDF_MODE_WINDOW_CONT)  || \
+                                        ((PARAM) == MDF_MODE_SYNC_SNAPSHOT))
+
+#define IS_ADF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT)   || \
+                                        ((PARAM) == MDF_MODE_ASYNC_SINGLE) || \
+                                        ((PARAM) == MDF_MODE_SYNC_CONT)    || \
+                                        ((PARAM) == MDF_MODE_SYNC_SINGLE)  || \
+                                        ((PARAM) == MDF_MODE_WINDOW_CONT))
+
+#define IS_MDF_DISCARD_SAMPLES(PARAM) ((PARAM) <= 255U)
+
+#define IS_MDF_FIFO_THRESHOLD(PARAM) (((PARAM) == MDF_FIFO_THRESHOLD_NOT_EMPTY) || \
+                                      ((PARAM) == MDF_FIFO_THRESHOLD_HALF_FULL))
+
+#define IS_MDF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO)        || \
+                                      ((PARAM) == MDF_FILTER_TRIG_OLD_EVENT)   || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM1_TRGO)   || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM1_TRGO2)  || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM8_TRGO)   || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM8_TRGO2)  || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM3_TRGO)   || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM4_TRGO)   || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM6_TRGO)   || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM7_TRGO)   || \
+                                      ((PARAM) == MDF_FILTER_TRIG_TIM15_TRGO)  || \
+                                      ((PARAM) == MDF_FILTER_TRIG_ADF_SAD_DET) || \
+                                      ((PARAM) == MDF_FILTER_TRIG_EXTI11)      || \
+                                      ((PARAM) == MDF_FILTER_TRIG_EXTI15)      || \
+                                      ((PARAM) == MDF_FILTER_TRIG_LPTIM1_OUT)  || \
+                                      ((PARAM) == MDF_FILTER_TRIG_ADF_TRGO))
+
+#define IS_ADF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO) || \
+                                      ((PARAM) == MDF_FILTER_TRIG_EXTI15))
+
+#define IS_MDF_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_FILTER_TRIG_RISING_EDGE) || \
+                                    ((PARAM) == MDF_FILTER_TRIG_FALLING_EDGE))
+
+#define IS_MDF_SNAPSHOT_FORMAT(PARAM) (((PARAM) == MDF_SNAPSHOT_23BITS) || \
+                                       ((PARAM) == MDF_SNAPSHOT_16BITS))
+
+#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX)    || \
+                                   ((PARAM) == MDF_DATA_SOURCE_ADCITF1) || \
+                                   ((PARAM) == MDF_DATA_SOURCE_ADCITF2))
+
+#define IS_ADF_DATA_SOURCE(PARAM) ((PARAM) == MDF_DATA_SOURCE_BSMX)
+
+#define IS_MDF_DECIMATION_RATIO(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 512U))
+
+#define IS_MDF_GAIN(PARAM) ((-16 <= (PARAM)) && ((PARAM) <= 24))
+
+#define IS_MDF_DELAY(PARAM) ((PARAM) <= 127U)
+
+#define IS_MDF_OFFSET(PARAM) ((-33554432 <= (PARAM)) && ((PARAM) <= 33554431))
+
+#define IS_MDF_RSF_DECIMATION_RATIO(PARAM) (((PARAM) == MDF_RSF_DECIMATION_RATIO_4) || \
+                                            ((PARAM) == MDF_RSF_DECIMATION_RATIO_1))
+
+#define IS_MDF_HPF_CUTOFF_FREQ(PARAM) (((PARAM) == MDF_HPF_CUTOFF_0_000625FPCM) || \
+                                       ((PARAM) == MDF_HPF_CUTOFF_0_00125FPCM)  || \
+                                       ((PARAM) == MDF_HPF_CUTOFF_0_0025FPCM)   || \
+                                       ((PARAM) == MDF_HPF_CUTOFF_0_0095FPCM))
+
+#define IS_MDF_INTEGRATOR_VALUE(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 128U))
+
+#define IS_MDF_INTEGRATOR_OUTPUT_DIV(PARAM) (((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_128) || \
+                                             ((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_32)  || \
+                                             ((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_4)   || \
+                                             ((PARAM) == MDF_INTEGRATOR_OUTPUT_NO_DIV))
+
+#define IS_MDF_SAD_MODE(PARAM) (((PARAM) == MDF_SAD_VOICE_ACTIVITY_DETECTOR) || \
+                                ((PARAM) == MDF_SAD_SOUND_DETECTOR)          || \
+                                ((PARAM) == MDF_SAD_AMBIENT_NOISE_DETECTOR))
+
+#define IS_MDF_SAD_FRAME_SIZE(PARAM) (((PARAM) == MDF_SAD_8_PCM_SAMPLES)   || \
+                                      ((PARAM) == MDF_SAD_16_PCM_SAMPLES)  || \
+                                      ((PARAM) == MDF_SAD_32_PCM_SAMPLES)  || \
+                                      ((PARAM) == MDF_SAD_64_PCM_SAMPLES)  || \
+                                      ((PARAM) == MDF_SAD_128_PCM_SAMPLES) || \
+                                      ((PARAM) == MDF_SAD_256_PCM_SAMPLES) || \
+                                      ((PARAM) == MDF_SAD_512_PCM_SAMPLES))
+
+#define IS_MDF_SAD_SOUND_TRIGGER(PARAM) (((PARAM) == MDF_SAD_ENTER_DETECT) || \
+                                         ((PARAM) == MDF_SAD_ENTER_EXIT_DETECT))
+
+#define IS_MDF_SAD_DATA_MEMORY_TRANSFER(PARAM) (((PARAM) == MDF_SAD_NO_MEMORY_TRANSFER)        || \
+                                                ((PARAM) == MDF_SAD_MEMORY_TRANSFER_IN_DETECT) || \
+                                                ((PARAM) == MDF_SAD_MEMORY_TRANSFER_ALWAYS))
+
+#define IS_MDF_SAD_MIN_NOISE_LEVEL(PARAM) ((PARAM) <= 8191U)
+
+#define IS_MDF_SAD_HANGOVER_WINDOW(PARAM) (((PARAM) == MDF_SAD_HANGOVER_4_FRAMES)   || \
+                                           ((PARAM) == MDF_SAD_HANGOVER_8_FRAMES)   || \
+                                           ((PARAM) == MDF_SAD_HANGOVER_16_FRAMES)  || \
+                                           ((PARAM) == MDF_SAD_HANGOVER_32_FRAMES)  || \
+                                           ((PARAM) == MDF_SAD_HANGOVER_64_FRAMES)  || \
+                                           ((PARAM) == MDF_SAD_HANGOVER_128_FRAMES) || \
+                                           ((PARAM) == MDF_SAD_HANGOVER_256_FRAMES) || \
+                                           ((PARAM) == MDF_SAD_HANGOVER_512_FRAMES))
+
+#define IS_MDF_SAD_LEARNING_FRAMES(PARAM) (((PARAM) == MDF_SAD_LEARNING_2_FRAMES)  || \
+                                           ((PARAM) == MDF_SAD_LEARNING_4_FRAMES)  || \
+                                           ((PARAM) == MDF_SAD_LEARNING_8_FRAMES)  || \
+                                           ((PARAM) == MDF_SAD_LEARNING_16_FRAMES) || \
+                                           ((PARAM) == MDF_SAD_LEARNING_32_FRAMES))
+
+#define IS_MDF_SAD_AMBIENT_NOISE_SLOPE(PARAM) ((PARAM) <= 7U)
+
+#define IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(PARAM) (((PARAM) == MDF_SAD_SIGNAL_NOISE_3_5DB)  || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_6DB)    || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_9_5DB)  || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_12DB)   || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_15_6DB) || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_18DB)   || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_21_6DB) || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_24_1DB) || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_27_6DB) || \
+                                                  ((PARAM) == MDF_SAD_SIGNAL_NOISE_30_1DB))
+
+#define IS_MDF_SCD_THRESHOLD(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 256U))
+
+#define IS_MDF_BREAK_SIGNAL(PARAM) ((PARAM) <= 15U)
+
+#define IS_MDF_OLD_CIC_MODE(PARAM) (((PARAM) == MDF_OLD_FILTER_FASTSINC) || \
+                                    ((PARAM) == MDF_OLD_FILTER_SINC1)    || \
+                                    ((PARAM) == MDF_OLD_FILTER_SINC2)    || \
+                                    ((PARAM) == MDF_OLD_FILTER_SINC3))
+
+#define IS_MDF_OLD_DECIMATION_RATIO(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 32U))
+
+#define IS_MDF_OLD_THRESHOLD(PARAM) ((-33554432 <= (PARAM)) && ((PARAM) <= 33554431))
+
+#define IS_MDF_OLD_EVENT_CONFIG(PARAM) (((PARAM) == MDF_OLD_SIGNAL_OUTSIDE_THRESHOLDS) || \
+                                        ((PARAM) == MDF_OLD_SIGNAL_IN_THRESHOLDS))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_MDF_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mdios.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mdios.h
new file mode 100644
index 000000000..eb62ca6cf
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mdios.h
@@ -0,0 +1,576 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mdios.h
+  * @author  MCD Application Team
+  * @brief   Header file of MDIOS HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_MDIOS_H
+#define STM32N6xx_HAL_MDIOS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (MDIOS)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup MDIOS
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Types MDIOS Exported Types
+  * @{
+  */
+
+/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
+  * @{
+  */
+
+typedef enum
+{
+  HAL_MDIOS_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */
+  HAL_MDIOS_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */
+  HAL_MDIOS_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */
+  HAL_MDIOS_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */
+} HAL_MDIOS_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
+  * @{
+  */
+
+typedef struct
+{
+  uint32_t PortAddress;           /*!< Specifies the MDIOS port address.
+                                       This parameter can be a value from 0 to 31 */
+  uint32_t PreambleCheck;         /*!< Specifies whether the preamble check is enabled or disabled.
+                                       This parameter can be a value of @ref MDIOS_Preamble_Check */
+} MDIOS_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
+  * @{
+  */
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+typedef struct __MDIOS_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  MDIOS_TypeDef                *Instance;     /*!< Register base address       */
+
+  MDIOS_InitTypeDef            Init;          /*!< MDIOS Init Structure        */
+
+  __IO HAL_MDIOS_StateTypeDef  State;         /*!< MDIOS communication state
+                                                   This parameter can be a value of of @ref HAL_MDIOS_StateTypeDef */
+
+  __IO uint32_t                ErrorCode;     /*!< Holds the global Error code of the MDIOS HAL status machine
+                                                   This parameter can be a value of of @ref MDIOS_Error_Code */
+
+  HAL_LockTypeDef              Lock;          /*!< MDIOS Lock                  */
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+
+  void (* WriteCpltCallback)(struct __MDIOS_HandleTypeDef *hmdios);   /*!< MDIOS Write Complete Callback */
+  void (* ReadCpltCallback)(struct __MDIOS_HandleTypeDef *hmdios);    /*!< MDIOS Read  Complete Callback */
+  void (* ErrorCallback)(struct __MDIOS_HandleTypeDef *hmdios);       /*!< MDIOS Error Callback          */
+  void (* WakeUpCallback)(struct __MDIOS_HandleTypeDef *hmdios);      /*!< MDIOS Wake UP Callback        */
+
+  void (* MspInitCallback)(struct __MDIOS_HandleTypeDef *hmdios);     /*!< MDIOS Msp Init callback       */
+  void (* MspDeInitCallback)(struct __MDIOS_HandleTypeDef *hmdios);   /*!< MDIOS Msp DeInit callback     */
+
+#endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+} MDIOS_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL MDIOS Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_MDIOS_MSPINIT_CB_ID            = 0x00U,    /*!< MDIOS MspInit callback ID           */
+  HAL_MDIOS_MSPDEINIT_CB_ID          = 0x01U,    /*!< MDIOS MspDeInit callback ID         */
+
+  HAL_MDIOS_WRITE_COMPLETE_CB_ID     = 0x02U,    /*!< MDIOS Write Complete Callback ID    */
+  HAL_MDIOS_READ_COMPLETE_CB_ID      = 0x03U,    /*!< MDIOS Read Complete Callback ID     */
+  HAL_MDIOS_ERROR_CB_ID              = 0x04U,    /*!< MDIOS Error Callback ID             */
+  HAL_MDIOS_WAKEUP_CB_ID             = 0x05U     /*!< MDIOS Wake UP Callback ID           */
+} HAL_MDIOS_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL MDIOS Callback pointer definition
+  */
+typedef  void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef *hmdios); /*!< pointer to an MDIOS callback function */
+
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
+  * @{
+  */
+
+/** @defgroup MDIOS_Preamble_Check  MDIOS Preamble Check
+  * @{
+  */
+#define MDIOS_PREAMBLE_CHECK_ENABLE      ((uint32_t)0x00000000U)
+#define MDIOS_PREAMBLE_CHECK_DISABLE     MDIOS_CR_DPC
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
+  * @{
+  */
+#define MDIOS_REG0                      ((uint32_t)0x00000000U)
+#define MDIOS_REG1                      ((uint32_t)0x00000001U)
+#define MDIOS_REG2                      ((uint32_t)0x00000002U)
+#define MDIOS_REG3                      ((uint32_t)0x00000003U)
+#define MDIOS_REG4                      ((uint32_t)0x00000004U)
+#define MDIOS_REG5                      ((uint32_t)0x00000005U)
+#define MDIOS_REG6                      ((uint32_t)0x00000006U)
+#define MDIOS_REG7                      ((uint32_t)0x00000007U)
+#define MDIOS_REG8                      ((uint32_t)0x00000008U)
+#define MDIOS_REG9                      ((uint32_t)0x00000009U)
+#define MDIOS_REG10                     ((uint32_t)0x0000000AU)
+#define MDIOS_REG11                     ((uint32_t)0x0000000BU)
+#define MDIOS_REG12                     ((uint32_t)0x0000000CU)
+#define MDIOS_REG13                     ((uint32_t)0x0000000DU)
+#define MDIOS_REG14                     ((uint32_t)0x0000000EU)
+#define MDIOS_REG15                     ((uint32_t)0x0000000FU)
+#define MDIOS_REG16                     ((uint32_t)0x00000010U)
+#define MDIOS_REG17                     ((uint32_t)0x00000011U)
+#define MDIOS_REG18                     ((uint32_t)0x00000012U)
+#define MDIOS_REG19                     ((uint32_t)0x00000013U)
+#define MDIOS_REG20                     ((uint32_t)0x00000014U)
+#define MDIOS_REG21                     ((uint32_t)0x00000015U)
+#define MDIOS_REG22                     ((uint32_t)0x00000016U)
+#define MDIOS_REG23                     ((uint32_t)0x00000017U)
+#define MDIOS_REG24                     ((uint32_t)0x00000018U)
+#define MDIOS_REG25                     ((uint32_t)0x00000019U)
+#define MDIOS_REG26                     ((uint32_t)0x0000001AU)
+#define MDIOS_REG27                     ((uint32_t)0x0000001BU)
+#define MDIOS_REG28                     ((uint32_t)0x0000001CU)
+#define MDIOS_REG29                     ((uint32_t)0x0000001DU)
+#define MDIOS_REG30                     ((uint32_t)0x0000001EU)
+#define MDIOS_REG31                     ((uint32_t)0x0000001FU)
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Registers_Flags  MDIOS Registers Flags
+  * @{
+  */
+#define MDIOS_REG0_FLAG    ((uint32_t)0x00000001U)
+#define MDIOS_REG1_FLAG    ((uint32_t)0x00000002U)
+#define MDIOS_REG2_FLAG    ((uint32_t)0x00000004U)
+#define MDIOS_REG3_FLAG    ((uint32_t)0x00000008U)
+#define MDIOS_REG4_FLAG    ((uint32_t)0x00000010U)
+#define MDIOS_REG5_FLAG    ((uint32_t)0x00000020U)
+#define MDIOS_REG6_FLAG    ((uint32_t)0x00000040U)
+#define MDIOS_REG7_FLAG    ((uint32_t)0x00000080U)
+#define MDIOS_REG8_FLAG    ((uint32_t)0x00000100U)
+#define MDIOS_REG9_FLAG    ((uint32_t)0x00000200U)
+#define MDIOS_REG10_FLAG   ((uint32_t)0x00000400U)
+#define MDIOS_REG11_FLAG   ((uint32_t)0x00000800U)
+#define MDIOS_REG12_FLAG   ((uint32_t)0x00001000U)
+#define MDIOS_REG13_FLAG   ((uint32_t)0x00002000U)
+#define MDIOS_REG14_FLAG   ((uint32_t)0x00004000U)
+#define MDIOS_REG15_FLAG   ((uint32_t)0x00008000U)
+#define MDIOS_REG16_FLAG   ((uint32_t)0x00010000U)
+#define MDIOS_REG17_FLAG   ((uint32_t)0x00020000U)
+#define MDIOS_REG18_FLAG   ((uint32_t)0x00040000U)
+#define MDIOS_REG19_FLAG   ((uint32_t)0x00080000U)
+#define MDIOS_REG20_FLAG   ((uint32_t)0x00100000U)
+#define MDIOS_REG21_FLAG   ((uint32_t)0x00200000U)
+#define MDIOS_REG22_FLAG   ((uint32_t)0x00400000U)
+#define MDIOS_REG23_FLAG   ((uint32_t)0x00800000U)
+#define MDIOS_REG24_FLAG   ((uint32_t)0x01000000U)
+#define MDIOS_REG25_FLAG   ((uint32_t)0x02000000U)
+#define MDIOS_REG26_FLAG   ((uint32_t)0x04000000U)
+#define MDIOS_REG27_FLAG   ((uint32_t)0x08000000U)
+#define MDIOS_REG28_FLAG   ((uint32_t)0x10000000U)
+#define MDIOS_REG29_FLAG   ((uint32_t)0x20000000U)
+#define MDIOS_REG30_FLAG   ((uint32_t)0x40000000U)
+#define MDIOS_REG31_FLAG   ((uint32_t)0x80000000U)
+#define MDIOS_ALLREG_FLAG  ((uint32_t)0xFFFFFFFFU)
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Interrupt_sources Interrupt Sources
+  * @{
+  */
+#define MDIOS_IT_WRITE                   MDIOS_CR_WRIE
+#define MDIOS_IT_READ                    MDIOS_CR_RDIE
+#define MDIOS_IT_ERROR                   MDIOS_CR_EIE
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Interrupt_Flags  MDIOS Interrupt Flags
+  * @{
+  */
+#define MDIOS_TURNAROUND_ERROR_FLAG       MDIOS_SR_TERF
+#define MDIOS_START_ERROR_FLAG            MDIOS_SR_SERF
+#define MDIOS_PREAMBLE_ERROR_FLAG         MDIOS_SR_PERF
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Error_Code MDIOS Error Code
+  * @{
+  */
+#define HAL_MDIOS_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
+#define HAL_MDIOS_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */
+#define HAL_MDIOS_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */
+#define HAL_MDIOS_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */
+#define HAL_MDIOS_ERROR_DATA         ((uint32_t)0x00000010U)   /*!< Data transfer error       */
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+#define HAL_MDIOS_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Wakeup_Line  MDIOS Wakeup Line
+  * @{
+  */
+#define MDIOS_WAKEUP_EXTI_LINE  ((uint32_t)0x00008000)  /* !<  47 - 32 = 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
+  * @{
+  */
+
+/** @brief Reset MDIOS handle state
+  * @param  __HANDLE__: MDIOS handle.
+  * @retval None
+  */
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                        (__HANDLE__)->State = HAL_MDIOS_STATE_RESET;      \
+                                                        (__HANDLE__)->MspInitCallback = NULL;             \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                      } while(0)
+#else
+#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
+#endif /*USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable/Disable the MDIOS peripheral.
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @retval None
+  */
+#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
+#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
+
+
+/**
+  * @brief  Enable the MDIOS device interrupt.
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg MDIOS_IT_WRITE: Register write interrupt
+  *            @arg MDIOS_IT_READ: Register read interrupt
+  *            @arg MDIOS_IT_ERROR: Error interrupt
+  * @retval None
+  */
+#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the MDIOS device interrupt.
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg MDIOS_IT_WRITE: Register write interrupt
+  *            @arg MDIOS_IT_READ: Register read interrupt
+  *            @arg MDIOS_IT_ERROR: Error interrupt
+  * @retval None
+  */
+#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/** @brief Set MDIOS slave get write register flag
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @param  __FLAG__: specifies the write register flag
+  * @retval The state of write flag
+  */
+#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->WRFR &  (__FLAG__))
+
+/** @brief MDIOS slave get read register flag
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @param  __FLAG__: specifies the read register flag
+  * @retval The state of read flag
+  */
+#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->RDFR &  (__FLAG__))
+
+/** @brief MDIOS slave get interrupt
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @param  __FLAG__ : specifies the Error flag.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
+  *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt
+  *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
+  * @retval The state of the error flag
+  */
+#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->SR &  (__FLAG__))
+
+/** @brief  MDIOS slave clear interrupt
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @param  __FLAG__ : specifies the Error flag.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
+  *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt
+  *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
+  * @retval none
+  */
+#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
+
+/**
+  * @brief  Checks whether the specified MDIOS interrupt is set or not.
+  * @param  __HANDLE__: specifies the MDIOS handle.
+  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources
+  *            This parameter can be one or a combination of the following values:
+  *            @arg MDIOS_IT_WRITE: Register write interrupt
+  *            @arg MDIOS_IT_READ: Register read interrupt
+  *            @arg MDIOS_IT_ERROR: Error interrupt
+  * @retval The state of the interrupt source
+  */
+#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+  * @brief Enable the MDIOS WAKEUP Exti Line.
+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
+  * This parameter can be:
+  *   @arg MDIOS_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI->IMR2 |= (__EXTI_LINE__))
+
+/**
+  * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
+  * This parameter can be:
+  *   @arg MDIOS_WAKEUP_EXTI_LINE
+  * @retval EXTI MDIOS WAKEUP Line Status.
+  */
+#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->IMR2 & (__EXTI_LINE__))
+
+/**
+  * @brief Clear the MDIOS WAKEUP Exti flag.
+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
+  * This parameter can be:
+  *   @arg MDIOS_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->IMR2 &= ~ (__EXTI_LINE__))
+
+/**
+  * @brief  enable rising edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
+  * This parameter can be:
+  *  @arg MDIOS_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
+  (EXTI->RTSR2 |= (__EXTI_LINE__))
+
+/**
+  * @brief  enable falling edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
+  * This parameter can be:
+  *  @arg MDIOS_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\
+  (EXTI->FTSR2 |= (__EXTI_LINE__))
+
+/**
+  * @brief  enable falling edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
+  * This parameter can be:
+  *  @arg MDIOS_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\
+  (EXTI->FTSR2 |= (__EXTI_LINE__))
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
+  * This parameter can be:
+  *  @arg MDIOS_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
+  * @{
+  */
+
+/** @addtogroup MDIOS_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
+HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
+void  HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID,
+                                             pMDIOS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup MDIOS_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t Data);
+HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t *pData);
+
+uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios);
+uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios);
+HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
+HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
+
+HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
+/**
+  * @}
+  */
+
+/** @addtogroup MDIOS_Exported_Functions_Group3
+  * @{
+  */
+uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios);
+HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Types MDIOS Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Variables MDIOS Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Constants MDIOS Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Macros MDIOS Private Macros
+  * @{
+  */
+
+#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32U)
+
+#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32U)
+
+#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
+                                                   ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* MDIOS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_MDIOS_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mmc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mmc.h
new file mode 100644
index 000000000..1275ab081
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mmc.h
@@ -0,0 +1,873 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of MMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_MMC_H
+#define STM32N6xx_HAL_MMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_sdmmc.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+
+/** @addtogroup MMC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_Types MMC Exported Types
+  * @{
+  */
+
+/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
+  * @{
+  */
+typedef enum
+{
+  HAL_MMC_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< MMC not yet initialized or disabled  */
+  HAL_MMC_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< MMC initialized and ready for use    */
+  HAL_MMC_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< MMC Timeout state                    */
+  HAL_MMC_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< MMC process ongoing                  */
+  HAL_MMC_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< MMC Programming State                */
+  HAL_MMC_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< MMC Receinving State                 */
+  HAL_MMC_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< MMC Transfer State                   */
+  HAL_MMC_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< MMC is in error state                */
+} HAL_MMC_StateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
+  * @{
+  */
+typedef uint32_t HAL_MMC_CardStateTypeDef;
+
+#define HAL_MMC_CARD_IDLE           0x00000000U  /*!< Card is in idle state (can't be checked by CMD13)           */
+#define HAL_MMC_CARD_READY          0x00000001U  /*!< Card state is ready (can't be checked by CMD13)             */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                                    */
+#define HAL_MMC_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state                                   */
+#define HAL_MMC_CARD_SENDING        0x00000005U  /*!< Card is sending an operation                                */
+#define HAL_MMC_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information                     */
+#define HAL_MMC_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state                                */
+#define HAL_MMC_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                                        */
+#define HAL_MMC_CARD_BUSTEST        0x00000009U  /*!< Card is in bus test state                                   */
+#define HAL_MMC_CARD_SLEEP          0x0000000AU  /*!< Card is in sleep state (can't be checked by CMD13)          */
+#define HAL_MMC_CARD_ERROR          0x000000FFU  /*!< Card response Error (can't be checked by CMD13)             */
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
+  * @{
+  */
+#define MMC_InitTypeDef      SDMMC_InitTypeDef
+#define MMC_TypeDef          SDMMC_TypeDef
+
+/**
+  * @brief  MMC Card Information Structure definition
+  */
+typedef struct
+{
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+} HAL_MMC_CardInfoTypeDef;
+
+/**
+  * @brief  MMC handle Structure definition
+  */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+typedef struct __MMC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+{
+  MMC_TypeDef                  *Instance;        /*!< MMC registers base address           */
+
+  MMC_InitTypeDef              Init;             /*!< MMC required parameters              */
+
+  HAL_LockTypeDef              Lock;             /*!< MMC locking object                   */
+
+  const uint8_t                *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer    */
+
+  uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                 */
+
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to MMC Rx transfer Buffer    */
+
+  uint32_t                     RxXferSize;       /*!< MMC Rx Transfer size                 */
+
+  __IO uint32_t                Context;          /*!< MMC transfer context                 */
+
+  __IO HAL_MMC_StateTypeDef    State;            /*!< MMC card State                       */
+
+  __IO uint32_t                ErrorCode;        /*!< MMC Card Error codes                 */
+
+  __IO uint16_t                RPMBErrorCode;    /*!< MMC RPMB Area Error codes            */
+
+  HAL_MMC_CardInfoTypeDef      MmcCard;          /*!< MMC Card information                 */
+
+  uint32_t                     CSD[4U];          /*!< MMC card specific data table         */
+
+  uint32_t                     CID[4U];          /*!< MMC card identification number table */
+
+  uint32_t                     Ext_CSD[128];
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+  void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+  void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc);
+  void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+  void (* Read_DMALnkLstBufCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+  void (* Write_DMALnkLstBufCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+
+  void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+  void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+} MMC_HandleTypeDef;
+
+
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+
+} HAL_MMC_CardCSDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+} HAL_MMC_CardCIDTypeDef;
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_MMC_TX_CPLT_CB_ID                 = 0x00U,  /*!< MMC Tx Complete Callback ID                     */
+  HAL_MMC_RX_CPLT_CB_ID                 = 0x01U,  /*!< MMC Rx Complete Callback ID                     */
+  HAL_MMC_ERROR_CB_ID                   = 0x02U,  /*!< MMC Error Callback ID                           */
+  HAL_MMC_ABORT_CB_ID                   = 0x03U,  /*!< MMC Abort Callback ID                           */
+  HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID  = 0x04U,  /*!< MMC DMA Rx Linked List Node buffer Callback ID */
+  HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID = 0x05U,  /*!< MMC DMA Tx Linked List Node buffer Callback ID */
+
+  HAL_MMC_MSP_INIT_CB_ID                = 0x10U,  /*!< MMC MspInit Callback ID                         */
+  HAL_MMC_MSP_DEINIT_CB_ID              = 0x11U   /*!< MMC MspDeInit Callback ID                       */
+} HAL_MMC_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+  * @{
+  */
+typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Constants Exported Constants
+  * @{
+  */
+
+#define MMC_BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
+
+/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
+  * @{
+  */
+#define HAL_MMC_ERROR_NONE                           SDMMC_ERROR_NONE                    /*!< No error                                                      */
+#define HAL_MMC_ERROR_CMD_CRC_FAIL                   SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
+#define HAL_MMC_ERROR_DATA_CRC_FAIL                  SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT                SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
+#define HAL_MMC_ERROR_DATA_TIMEOUT                   SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
+#define HAL_MMC_ERROR_TX_UNDERRUN                    SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
+#define HAL_MMC_ERROR_RX_OVERRUN                     SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
+#define HAL_MMC_ERROR_ADDR_MISALIGNED                SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR                  SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the   */
+/*!< number of transferred bytes does not match the block length   */
+#define HAL_MMC_ERROR_ERASE_SEQ_ERR                  SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
+#define HAL_MMC_ERROR_BAD_ERASE_PARAM                SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION           SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED             SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock        */
+/*!< command or if there was an attempt to access a locked card    */
+#define HAL_MMC_ERROR_COM_CRC_FAILED                 SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
+#define HAL_MMC_ERROR_ILLEGAL_CMD                    SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
+#define HAL_MMC_ERROR_CARD_ECC_FAILED                SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
+#define HAL_MMC_ERROR_CC_ERR                         SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR            SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN           SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN           SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE              SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
+#define HAL_MMC_ERROR_WP_ERASE_SKIP                  SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
+#define HAL_MMC_ERROR_CARD_ECC_DISABLED              SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
+#define HAL_MMC_ERROR_ERASE_RESET                    SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out    */
+/*!< of erase sequence command was received                        */
+#define HAL_MMC_ERROR_AKE_SEQ_ERR                    SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
+#define HAL_MMC_ERROR_INVALID_VOLTRANGE              SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */
+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE              SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */
+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE         SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */
+#define HAL_MMC_ERROR_PARAM                          SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */
+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE            SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
+#define HAL_MMC_ERROR_BUSY                           SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */
+#define HAL_MMC_ERROR_DMA                            SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
+#define HAL_MMC_ERROR_TIMEOUT                        SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
+/*!< response results after operating with RPMB partition          */
+#define HAL_MMC_ERROR_RPMB_OPERATION_OK              0x0000U                             /*!< Operation OK                                                  */
+#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE           0x0001U                             /*!< General failure                                               */
+#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE    0x0002U                             /*!< Authentication failure                                        */
+#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE           0x0003U                             /*!< Counter failure                                               */
+#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE           0x0004U                             /*!< Address failure                                               */
+#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE             0x0005U                             /*!< Write failure                                                 */
+#define HAL_MMC_ERROR_RPMB_READ_FAILURE              0x0006U                             /*!< Read failure                                                  */
+#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG          0x0007U                             /*!< Authentication Key not yet programmed                         */
+#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED           0x0080U                             /*!< Write Counter has expired i.e. reached its max value          */
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define HAL_MMC_ERROR_INVALID_CALLBACK              SDMMC_ERROR_INVALID_PARAMETER        /*!< Invalid callback error                                        */
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
+  * @{
+  */
+#define   MMC_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
+#define   MMC_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
+#define   MMC_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
+#define   MMC_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
+#define   MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
+#define   MMC_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
+#define   MMC_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
+
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
+  * @{
+  */
+/**
+  * @brief
+  */
+#define MMC_HIGH_VOLTAGE_RANGE         0x80FF8000U  /*!< High voltage in byte mode    */
+#define MMC_DUAL_VOLTAGE_RANGE         0x80FF8080U  /*!< Dual voltage in byte mode    */
+#define MMC_LOW_VOLTAGE_RANGE          0x80000080U  /*!< Low voltage in byte mode     */
+#define EMMC_HIGH_VOLTAGE_RANGE        0xC0FF8000U  /*!< High voltage in sector mode  */
+#define EMMC_DUAL_VOLTAGE_RANGE        0xC0FF8080U  /*!< Dual voltage in sector mode  */
+#define EMMC_LOW_VOLTAGE_RANGE         0xC0000080U  /*!< Low voltage in sector mode   */
+#define MMC_INVALID_VOLTAGE_RANGE      0x0001FF01U
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
+  * @{
+  */
+#define  MMC_LOW_CAPACITY_CARD     ((uint32_t)0x00000000U)   /*!< MMC Card Capacity <=2Gbytes   */
+#define  MMC_HIGH_CAPACITY_CARD    ((uint32_t)0x00000001U)   /*!< MMC Card Capacity >2Gbytes and <2Tbytes   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group5 MMC Erase Type
+  * @{
+  */
+#define HAL_MMC_ERASE             0x00000000U  /*!< Erase the erase groups identified by CMD35 & 36                                   */
+#define HAL_MMC_TRIM              0x00000001U  /*!< Erase the write blocks identified by CMD35 & 36                                   */
+#define HAL_MMC_DISCARD           0x00000003U  /*!< Discard the write blocks identified by CMD35 & 36                                 */
+#define HAL_MMC_SECURE_ERASE      0x80000000U  /*!< Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 */
+#define HAL_MMC_SECURE_TRIM_STEP1 0x80000001U  /*!< Mark the write blocks identified by CMD35 & 36 for secure erase                   */
+#define HAL_MMC_SECURE_TRIM_STEP2 0x80008000U  /*!< Perform a secure purge according SRT on the write blocks previously identified    */
+
+#define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE)             || \
+                                 ((TYPE) == HAL_MMC_TRIM)              || \
+                                 ((TYPE) == HAL_MMC_DISCARD)           || \
+                                 ((TYPE) == HAL_MMC_SECURE_ERASE)      || \
+                                 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \
+                                 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP2))
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group6 MMC Secure Removal Type
+  * @{
+  */
+#define HAL_MMC_SRT_ERASE                   0x00000001U  /*!< Information removed by an erase                                                                */
+#define HAL_MMC_SRT_WRITE_CHAR_ERASE        0x00000002U  /*!< Information removed by an overwriting with a character followed by an erase                    */
+#define HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM 0x00000004U  /*!< Information removed by an overwriting with a character, its complement then a random character */
+#define HAL_MMC_SRT_VENDOR_DEFINED          0x00000008U  /*!< Information removed using a vendor defined                                                     */
+
+
+#define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE)                   || \
+                               ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE)        || \
+                               ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \
+                               ((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED))
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types
+  * @{
+  */
+typedef uint32_t HAL_MMC_PartitionTypeDef;
+
+#define HAL_MMC_USER_AREA_PARTITION              0x00000000U   /*!< User area partition */
+#define HAL_MMC_BOOT_PARTITION1                  0x00000100U   /*!< Boot partition 1    */
+#define HAL_MMC_BOOT_PARTITION2                  0x00000200U   /*!< Boot partition 2    */
+#define HAL_MMC_RPMB_PARTITION                   0x00000300U   /*!< RPMB partition      */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_macros MMC Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+/** @brief Reset MMC handle state.
+  * @param  __HANDLE__ MMC Handle.
+  * @retval None
+  */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                                (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
+                                                                (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                              } while(0)
+#else
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the MMC device interrupt.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the MMC device interrupt.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified MMC flag is set or not.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval The new state of MMC FLAG (SET or RESET).
+  */
+#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the MMC's pending flags.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval None
+  */
+#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified MMC interrupt has occurred or not.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval The new state of MMC IT (SET or RESET).
+  */
+#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the MMC's interrupt pending bits.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Include MMC HAL Extension module */
+#include "stm32n6xx_hal_mmc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Functions MMC Exported Functions
+  * @{
+  */
+
+/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks,
+                                     uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
+                                      uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
+                                          uint32_t NumberOfBlocks);
+
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/* MMC callback registering/unregistering */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+                                           pMMC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
+HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);
+HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
+  * @{
+  */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd,
+                                        uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode);
+HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
+
+/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey,
+                                                           uint32_t Timeout);
+uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout);
+uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce);
+HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd,
+                                           uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd,
+                                              uint16_t NumberOfBlocks, const uint8_t *pMAC);
+HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd,
+                                          uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC,
+                                          uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd,
+                                             uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC);
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MMC_Private_Types MMC Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MMC_Private_Defines MMC Private Defines
+  * @{
+  */
+#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61
+#define MMC_EXT_CSD_DATA_SEC_SIZE_POS   8
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Variables MMC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Constants MMC Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MMC_Private_Macros MMC Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_MMC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mmc_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mmc_ex.h
new file mode 100644
index 000000000..3d694f2e6
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_mmc_ex.h
@@ -0,0 +1,124 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mmc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SD HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_MMC_EX_H
+#define STM32N6xx_HAL_MMC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+/** @addtogroup MMCEx
+  * @brief SD HAL extended module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MMCEx_Exported_Types MMCEx Exported Types
+  * @{
+  */
+
+/** @defgroup MMCEx_Exported_Types_Group1 Linked List Wrapper
+  * @{
+  */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* -----------------Linked List Wrapper --------------------------------------*/
+
+#define MMC_DMALinkNodeTypeDef        SDMMC_DMALinkNodeTypeDef
+#define MMC_DMALinkNodeConfTypeDef    SDMMC_DMALinkNodeConfTypeDef
+#define MMC_DMALinkedListTypeDef      SDMMC_DMALinkedListTypeDef
+/* ----------------- Linked Aliases ------------------------------------------*/
+#define HAL_MMCx_DMALinkedList_WriteCpltCallback HAL_MMC_TxCpltCallback
+#define HAL_MMCx_DMALinkedList_ReadCpltCallback  HAL_MMC_RxCpltCallback
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
+  * @{
+  */
+
+/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc,
+                                                     const MMC_DMALinkedListTypeDef *pLinkedList,
+                                                     uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc,
+                                                      const MMC_DMALinkedListTypeDef *pLinkedList,
+                                                      uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode,
+                                                    MMC_DMALinkNodeConfTypeDef *pNodeConf);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_InsertNode(MMC_DMALinkedListTypeDef *pLinkedList,
+                                                     MMC_DMALinkNodeTypeDef *pPrevNode,
+                                                     MMC_DMALinkNodeTypeDef *pNewNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_RemoveNode(MMC_DMALinkedListTypeDef *pLinkedList,
+                                                     MMC_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_LockNode(MMC_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_UnlockNode(MMC_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+
+void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_MMCEx_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_nand.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_nand.h
new file mode 100644
index 000000000..05e6f6a02
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_nand.h
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_nand.h
+  * @author  MCD Application Team
+  * @brief   Header file of NAND HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_NAND_H
+#define STM32N6xx_HAL_NAND_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_fmc.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NAND
+  * @{
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL NAND State structures definition
+  */
+typedef enum
+{
+  HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
+  HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
+  HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
+  HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
+} HAL_NAND_StateTypeDef;
+
+/**
+  * @brief  NAND Memory electronic signature Structure definition
+  */
+typedef struct
+{
+  /*<! NAND memory electronic signature maker and device IDs */
+
+  uint8_t Maker_Id;
+
+  uint8_t Device_Id;
+
+  uint8_t Third_Id;
+
+  uint8_t Fourth_Id;
+} NAND_IDTypeDef;
+
+/**
+  * @brief  NAND Memory address Structure definition
+  */
+typedef struct
+{
+  uint16_t Page;   /*!< NAND memory Page address  */
+
+  uint16_t Plane;   /*!< NAND memory Zone address  */
+
+  uint16_t Block;  /*!< NAND memory Block address */
+
+} NAND_AddressTypeDef;
+
+/**
+  * @brief  NAND Memory info Structure definition
+  */
+typedef struct
+{
+  uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
+                                              for 8 bits addressing or words for 16 bits addressing             */
+
+  uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
+                                              for 8 bits addressing or words for 16 bits addressing             */
+
+  uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
+
+  uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
+
+  uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
+
+  uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
+
+  FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
+                                              parameter is mandatory for some NAND parts after the read
+                                              command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
+                                              This parameter could be ENABLE or DISABLE
+                                              Please check the Read Mode sequence in the NAND device datasheet */
+} NAND_DeviceConfigTypeDef;
+
+/**
+  * @brief  NAND handle Structure definition
+  */
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+typedef struct __NAND_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
+{
+  FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
+
+  FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
+
+  HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
+
+  __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
+
+  NAND_DeviceConfigTypeDef       Config;     /*!< NAND physical characteristic information structure    */
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand);               /*!< NAND Msp Init callback              */
+  void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand);             /*!< NAND Msp DeInit callback            */
+  void (* ItCallback)(struct __NAND_HandleTypeDef *hnand);                    /*!< NAND IT callback                    */
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+} NAND_HandleTypeDef;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL NAND Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
+  HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
+  HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
+} HAL_NAND_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL NAND Callback pointer definition
+  */
+typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
+  * @{
+  */
+
+/** @brief Reset NAND handle state
+  * @param  __HANDLE__ specifies the NAND handle.
+  * @retval None
+  */
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
+                                                               (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+  * @{
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+                                 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
+void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+  * @{
+  */
+
+/* IO operation functions  ****************************************************/
+HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                         uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                          const uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                              uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                               const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                          uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                           const uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                               uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                                const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
+
+uint32_t           HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/* NAND callback registering/unregistering */
+HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+                                             pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* NAND Control functions  ****************************************************/
+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
+uint32_t              HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+  * @{
+  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define NAND_DEVICE                0x37EFF000UL
+#else
+#define NAND_DEVICE                0x27EFF000UL
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#define NAND_WRITE_TIMEOUT         0x01000000UL
+
+#define CMD_AREA                   (1UL<<4U)  /* A16 = CLE high */
+#define ADDR_AREA                  (1UL<<5U)  /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)
+#define NAND_CMD_READID            ((uint8_t)0x90)
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS         0x00000100UL
+#define NAND_INVALID_ADDRESS       0x00000200UL
+#define NAND_TIMEOUT_ERROR         0x00000400UL
+#define NAND_BUSY                  0x00000000UL
+#define NAND_ERROR                 0x00000001UL
+#define NAND_READY                 0x00000040UL
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+  * @{
+  */
+
+/**
+  * @brief  NAND memory address computation.
+  * @param  __ADDRESS__ NAND memory address.
+  * @param  __HANDLE__  NAND handle.
+  * @retval NAND Raw address value
+  */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+                                                 (((__ADDRESS__)->Block + \
+                                                   (((__ADDRESS__)->Plane) * \
+                                                    ((__HANDLE__)->Config.PlaneSize))) * \
+                                                  ((__HANDLE__)->Config.BlockSize)))
+
+/**
+  * @brief  NAND memory Column address computation.
+  * @param  __HANDLE__ NAND handle.
+  * @retval NAND Raw address value
+  */
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+
+/**
+  * @brief  NAND memory address cycling.
+  * @param  __ADDRESS__ NAND memory address.
+  * @retval NAND address cycling value.
+  */
+#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
+
+/**
+  * @brief  NAND memory Columns cycling.
+  * @param  __ADDRESS__ NAND memory address.
+  * @retval NAND Column address cycling value.
+  */
+#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_NAND_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_nor.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_nor.h
new file mode 100644
index 000000000..dc5adfc51
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_nor.h
@@ -0,0 +1,324 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_nor.h
+  * @author  MCD Application Team
+  * @brief   Header file of NOR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_NOR_H
+#define STM32N6xx_HAL_NOR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_fmc.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup NOR
+  * @{
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL SRAM State structures definition
+  */
+typedef enum
+{
+  HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
+  HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
+  HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
+  HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
+  HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
+} HAL_NOR_StateTypeDef;
+
+/**
+  * @brief  FMC NOR Status typedef
+  */
+typedef enum
+{
+  HAL_NOR_STATUS_SUCCESS  = 0U,
+  HAL_NOR_STATUS_ONGOING,
+  HAL_NOR_STATUS_ERROR,
+  HAL_NOR_STATUS_TIMEOUT
+} HAL_NOR_StatusTypeDef;
+
+/**
+  * @brief  FMC NOR ID typedef
+  */
+typedef struct
+{
+  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
+
+  uint16_t Device_Code1;
+
+  uint16_t Device_Code2;
+
+  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
+                                    These codes can be accessed by performing read operations with specific
+                                    control signals and addresses set.They can also be accessed by issuing
+                                    an Auto Select command                                                   */
+} NOR_IDTypeDef;
+
+/**
+  * @brief  FMC NOR CFI typedef
+  */
+typedef struct
+{
+  /*!< Defines the information stored in the memory's Common flash interface
+       which contains a description of various electrical and timing parameters,
+       density information and functions supported by the memory                   */
+
+  uint16_t CFI_1;
+
+  uint16_t CFI_2;
+
+  uint16_t CFI_3;
+
+  uint16_t CFI_4;
+} NOR_CFITypeDef;
+
+/**
+  * @brief  NOR handle Structure definition
+  */
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+typedef struct __NOR_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
+
+{
+  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
+
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
+
+  FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
+
+  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
+
+  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
+
+  uint32_t                      CommandSet;   /*!< NOR algorithm command set and control        */
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor);               /*!< NOR Msp Init callback              */
+  void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor);             /*!< NOR Msp DeInit callback            */
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+} NOR_HandleTypeDef;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL NOR Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
+  HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
+} HAL_NOR_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL NOR Callback pointer definition
+  */
+typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+  * @{
+  */
+/** @brief Reset NOR handle state
+  * @param  __HANDLE__ specifies the NOR handle.
+  * @retval None
+  */
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
+                                                               (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+  * @{
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+                               FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+  * @{
+  */
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+                                     uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+                                        uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/* NOR callback registering/unregistering */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+                                           pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
+  * @{
+  */
+
+/* NOR Control functions  *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+/**
+  * @}
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
+  * @{
+  */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef  HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+  * @{
+  */
+/* NOR device IDs addresses */
+#define MC_ADDRESS               ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS             ((uint16_t)0x0061)
+#define CFI2_ADDRESS             ((uint16_t)0x0062)
+#define CFI3_ADDRESS             ((uint16_t)0x0063)
+#define CFI4_ADDRESS             ((uint16_t)0x0064)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT               ((uint16_t)0xFFFF)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B            ((uint8_t)0x00)
+#define NOR_MEMORY_16B           ((uint8_t)0x01)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1       (0x60000000U)
+#define NOR_MEMORY_ADRESS2       (0x64000000U)
+#define NOR_MEMORY_ADRESS3       (0x68000000U)
+#define NOR_MEMORY_ADRESS4       (0x6C000000U)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+  * @{
+  */
+/**
+  * @brief  NOR memory address shifting.
+  * @param  __NOR_ADDRESS NOR base address
+  * @param  __NOR_MEMORY_WIDTH_ NOR memory width
+  * @param  __ADDRESS__ NOR memory address
+  * @retval NOR shifted address value
+  */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
+  ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
+              ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
+              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+  * @brief  NOR memory write data to specified address.
+  * @param  __ADDRESS__ NOR memory address
+  * @param  __DATA__ Data to write
+  * @retval None
+  */
+#define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
+                                               (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
+                                               __DSB();                                                    \
+                                             } while(0)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_NOR_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pcd.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pcd.h
new file mode 100644
index 000000000..9f2f2299b
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pcd.h
@@ -0,0 +1,427 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_PCD_H
+#define STM32N6xx_HAL_PCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_usb.h"
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PCD State structure definition
+  */
+typedef enum
+{
+  HAL_PCD_STATE_RESET   = 0x00,
+  HAL_PCD_STATE_READY   = 0x01,
+  HAL_PCD_STATE_ERROR   = 0x02,
+  HAL_PCD_STATE_BUSY    = 0x03,
+  HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+  PCD_BCD_ERROR                     = 0xFF,
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+/**
+  * @brief  PCD Handle Structure definition
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address             */
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters           */
+  __IO uint8_t            USB_Address; /*!< USB Address                       */
+  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters            */
+  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters           */
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status             */
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state           */
+  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                    */
+  uint32_t                Setup[12];   /*!< Setup packet buffer               */
+  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */
+  uint32_t                BESL;
+  uint32_t                FrameNumber; /*!< Store Current Frame number        */
+
+
+  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
+                                       This parameter can be set to ENABLE or DISABLE        */
+
+  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
+                                       This parameter can be set to ENABLE or DISABLE        */
+  void                    *pData;      /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
+  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
+  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
+  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
+  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
+  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
+  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
+
+  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
+  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
+  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
+  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
+  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
+  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
+
+  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+} PCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Include PCD HAL Extended module */
+#include "stm32n6xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup PCD_Speed PCD Speed
+  * @{
+  */
+#define PCD_SPEED_HIGH               USBD_HS_SPEED
+#define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED
+#define PCD_SPEED_FULL               USBD_FS_SPEED
+/**
+  * @}
+  */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+  * @{
+  */
+#define PCD_PHY_ULPI                 1U
+#define PCD_PHY_EMBEDDED             2U
+#define PCD_PHY_UTMI                 3U
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+  * @brief  PCD Error Code definition
+  * @{
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+  ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
+  *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+  *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
+  ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+  * @brief  HAL USB OTG PCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
+  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
+  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
+  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
+  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
+  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
+  HAL_PCD_DISCONNECT_CB_ID   = 0x07,      /*!< USB PCD Disconnect callback ID   */
+
+  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
+  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+  * @brief  HAL USB OTG PCD Callback pointer definition
+  * @{
+  */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
+
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
+                                           pPCD_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_DataOutStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_DataInStageCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode);
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+#ifndef USB_OTG_DOEPINT_OTEPSPR
+#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */
+#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
+
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM
+#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */
+#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
+
+#ifndef USB_OTG_DOEPINT_NAK
+#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */
+#endif /* defined USB_OTG_DOEPINT_NAK */
+
+#ifndef USB_OTG_DOEPMSK_NAKM
+#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */
+#endif /* defined USB_OTG_DOEPMSK_NAKM */
+
+#ifndef USB_OTG_DOEPINT_STPKTRX
+#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */
+#endif /* defined USB_OTG_DOEPINT_STPKTRX */
+
+#ifndef USB_OTG_DOEPMSK_NYETM
+#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */
+#endif /* defined USB_OTG_DOEPMSK_NYETM */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_PCD_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pcd_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pcd_ex.h
new file mode 100644
index 000000000..64038c06e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pcd_ex.h
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pcd_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_PCD_EX_H
+#define STM32N6xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCDEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @{
+  */
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32N6xx_HAL_PCD_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pka.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pka.h
new file mode 100644
index 000000000..fde5d5916
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pka.h
@@ -0,0 +1,670 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pka.h
+  * @author  MCD Application Team
+  * @brief   Header file of PKA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_PKA_H
+#define STM32N6xx_HAL_PKA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
+
+/** @addtogroup PKA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PKA_Exported_Types PKA Exported Types
+  * @{
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structures definition
+  * @{
+  */
+typedef enum
+{
+  HAL_PKA_STATE_RESET   = 0x00U,  /*!< PKA not yet initialized or disabled  */
+  HAL_PKA_STATE_READY   = 0x01U,  /*!< PKA initialized and ready for use    */
+  HAL_PKA_STATE_BUSY    = 0x02U,  /*!< PKA internal processing is ongoing   */
+  HAL_PKA_STATE_ERROR   = 0x03U,  /*!< PKA error state                      */
+}
+HAL_PKA_StateTypeDef;
+
+/**
+  * @}
+  */
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/** @defgroup HAL_callback_id HAL callback ID enumeration
+  * @{
+  */
+typedef enum
+{
+  HAL_PKA_OPERATION_COMPLETE_CB_ID      = 0x00U,    /*!< PKA End of operation callback ID  */
+  HAL_PKA_ERROR_CB_ID                   = 0x01U,    /*!< PKA Error callback ID             */
+  HAL_PKA_MSPINIT_CB_ID                 = 0x02U,    /*!< PKA Msp Init callback ID          */
+  HAL_PKA_MSPDEINIT_CB_ID               = 0x03U     /*!< PKA Msp DeInit callback ID        */
+} HAL_PKA_CallbackIDTypeDef;
+
+/**
+  * @}
+  */
+
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/** @defgroup PKA_Error_Code_definition PKA Error Code definition
+  * @brief  PKA Error Code definition
+  * @{
+  */
+#define HAL_PKA_ERROR_NONE      (0x00000000U)
+#define HAL_PKA_ERROR_ADDRERR   (0x00000001U)
+#define HAL_PKA_ERROR_RAMERR    (0x00000002U)
+#define HAL_PKA_ERROR_TIMEOUT   (0x00000004U)
+#define HAL_PKA_ERROR_OPERATION (0x00000008U)
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+#define HAL_PKA_ERROR_INVALID_CALLBACK  (0x00000010U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition
+  * @brief  PKA handle Structure definition
+  * @{
+  */
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+typedef struct __PKA_HandleTypeDef
+#else
+typedef struct
+#endif  /* USE_HAL_PKA_REGISTER_CALLBACKS */
+{
+  PKA_TypeDef                   *Instance;              /*!< Register base address */
+  __IO HAL_PKA_StateTypeDef     State;                  /*!< PKA state */
+  __IO uint32_t                 ErrorCode;              /*!< PKA Error code */
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+  void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
+  void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka);         /*!< PKA Error callback            */
+  void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka);       /*!< PKA Msp Init callback         */
+  void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka);     /*!< PKA Msp DeInit callback       */
+#endif  /* USE_HAL_PKA_REGISTER_CALLBACKS */
+} PKA_HandleTypeDef;
+/**
+  * @}
+  */
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/** @defgroup PKA_Callback_definition PKA Callback pointer definition
+  * @brief  PKA Callback pointer definition
+  * @{
+  */
+typedef  void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */
+/**
+  * @}
+  */
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+/** @defgroup PKA_Operation PKA operation structure definition
+  * @brief  Input and output data definition
+  * @{
+  */
+
+typedef struct
+{
+  uint32_t scalarMulSize;              /*!< Number of element in scalarMul array */
+  uint32_t modulusSize;                /*!< Number of element in modulus, coefA, pointX and pointY arrays */
+  uint32_t coefSign;                   /*!< Curve coefficient a sign */
+  const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+  const uint8_t *coefB;                /*!< pointer to curve coefficient b */
+  const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+  const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
+  const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
+  const uint8_t *scalarMul;            /*!< Pointer to scalar multiplier k   (Array of scalarMulSize elements) */
+  const uint8_t *primeOrder;           /*!< pointer to order of the curve */
+} PKA_ECCMulInTypeDef;
+
+typedef struct
+{
+  uint32_t primeOrderSize;             /*!< Number of element in primeOrder array */
+  uint32_t scalarMulSize;              /*!< Number of element in scalarMul array */
+  uint32_t modulusSize;                /*!< Number of element in modulus, coefA, pointX and pointY arrays */
+  uint32_t coefSign;                   /*!< Curve coefficient a sign */
+  const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+  const uint8_t *coefB;                /*!< pointer to curve coefficient b */
+  const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+  const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
+  const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
+  const uint8_t *scalarMul;            /*!< Pointer to scalar multiplier k   (Array of scalarMulSize elements) */
+  const uint8_t *primeOrder;           /*!< pointer to order of the curve */
+} PKA_ECCMulExInTypeDef;
+
+typedef struct
+{
+  uint32_t modulusSize;                /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
+  uint32_t coefSign;                   /*!< Curve coefficient a sign */
+  const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
+  const uint8_t *coefB;                /*!< Pointer to curve coefficient b   (Array of modulusSize elements) */
+  const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
+  const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
+  const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
+  const uint32_t *pMontgomeryParam;    /*!< pointer to montgomery param R2 (modulus N) */
+} PKA_PointCheckInTypeDef;
+
+typedef struct
+{
+  uint32_t size;                       /*!< Number of element in popA array */
+  const uint8_t *pOpDp;                /*!< Pointer to operand dP   (Array of size/2 elements) */
+  const uint8_t *pOpDq;                /*!< Pointer to operand dQ   (Array of size/2 elements) */
+  const uint8_t *pOpQinv;              /*!< Pointer to operand qinv (Array of size/2 elements) */
+  const uint8_t *pPrimeP;              /*!< Pointer to prime p      (Array of size/2 elements) */
+  const uint8_t *pPrimeQ;              /*!< Pointer to prime Q      (Array of size/2 elements) */
+  const uint8_t *popA;                 /*!< Pointer to operand A    (Array of size elements) */
+} PKA_RSACRTExpInTypeDef;
+
+typedef struct
+{
+  uint32_t primeOrderSize;             /*!< Number of element in primeOrder array */
+  uint32_t modulusSize;                /*!< Number of element in modulus array */
+  uint32_t coefSign;                   /*!< Curve coefficient a sign */
+  const uint8_t *coef;                 /*!< Pointer to curve coefficient |a|     (Array of modulusSize elements) */
+  const uint8_t *modulus;              /*!< Pointer to curve modulus value p     (Array of modulusSize elements) */
+  const uint8_t *basePointX;           /*!< Pointer to curve base point xG       (Array of modulusSize elements) */
+  const uint8_t *basePointY;           /*!< Pointer to curve base point yG       (Array of modulusSize elements) */
+  const uint8_t *pPubKeyCurvePtX;      /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */
+  const uint8_t *pPubKeyCurvePtY;      /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */
+  const uint8_t *RSign;                /*!< Pointer to signature part r          (Array of primeOrderSize elements) */
+  const uint8_t *SSign;                /*!< Pointer to signature part s          (Array of primeOrderSize elements) */
+  const uint8_t *hash;                 /*!< Pointer to hash of the message e     (Array of primeOrderSize elements) */
+  const uint8_t *primeOrder;           /*!< Pointer to order of the curve n      (Array of primeOrderSize elements) */
+} PKA_ECDSAVerifInTypeDef;
+
+typedef struct
+{
+  uint32_t primeOrderSize;             /*!< Number of element in primeOrder array */
+  uint32_t modulusSize;                /*!< Number of element in modulus array */
+  uint32_t coefSign;                   /*!< Curve coefficient a sign */
+  const uint8_t *coef;                 /*!< Pointer to curve coefficient |a|     (Array of modulusSize elements) */
+  const uint8_t *coefB;                /*!< Pointer to B coefficient             (Array of modulusSize elements) */
+  const uint8_t *modulus;              /*!< Pointer to curve modulus value p     (Array of modulusSize elements) */
+  const uint8_t *integer;              /*!< Pointer to random integer k          (Array of primeOrderSize elements) */
+  const uint8_t *basePointX;           /*!< Pointer to curve base point xG       (Array of modulusSize elements) */
+  const uint8_t *basePointY;           /*!< Pointer to curve base point yG       (Array of modulusSize elements) */
+  const uint8_t *hash;                 /*!< Pointer to hash of the message       (Array of primeOrderSize elements) */
+  const uint8_t *privateKey;           /*!< Pointer to private key d             (Array of primeOrderSize elements) */
+  const uint8_t *primeOrder;           /*!< Pointer to order of the curve n      (Array of primeOrderSize elements) */
+} PKA_ECDSASignInTypeDef;
+
+typedef struct
+{
+  uint8_t *RSign;                      /*!< Pointer to signature part r          (Array of modulusSize elements) */
+  uint8_t *SSign;                      /*!< Pointer to signature part s          (Array of modulusSize elements) */
+} PKA_ECDSASignOutTypeDef;
+
+typedef struct
+{
+  uint8_t *ptX;                        /*!< Pointer to point P coordinate xP     (Array of modulusSize elements) */
+  uint8_t *ptY;                        /*!< Pointer to point P coordinate yP     (Array of modulusSize elements) */
+} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef, PKA_ECCProjective2AffineOutTypeDef,
+PKA_ECCDoubleBaseLadderOutTypeDef;
+
+typedef struct
+{
+  uint8_t *ptX;                        /*!< pointer to point P coordinate xP */
+  uint8_t *ptY;                        /*!< pointer to point P coordinate yP */
+  uint8_t *ptZ;                        /*!< pointer to point P coordinate zP */
+} PKA_ECCCompleteAdditionOutTypeDef;
+
+typedef struct
+{
+  uint32_t expSize;                    /*!< Number of element in pExp array */
+  uint32_t OpSize;                     /*!< Number of element in pOp1 and pMod arrays */
+  const uint8_t *pExp;                 /*!< Pointer to Exponent             (Array of expSize elements) */
+  const uint8_t *pOp1;                 /*!< Pointer to Operand              (Array of OpSize elements) */
+  const uint8_t *pMod;                 /*!< Pointer to modulus              (Array of OpSize elements) */
+} PKA_ModExpInTypeDef;
+
+typedef struct
+{
+  uint32_t expSize;                    /*!< Size of the operand in bytes */
+  uint32_t OpSize;                     /*!< Size of the operand in bytes */
+  const uint8_t *pOp1;                 /*!< Pointer to Operand 1 */
+  const uint8_t *pExp;                 /*!< Pointer to Exponent */
+  const uint8_t *pMod;                 /*!< Pointer to Operand 1 */
+  const uint8_t *pPhi;                 /*!< Pointer to Phi value */
+} PKA_ModExpProtectModeInTypeDef;
+
+typedef struct
+{
+  uint32_t expSize;                    /*!< Number of element in pExp and pMontgomeryParam arrays */
+  uint32_t OpSize;                     /*!< Number of element in pOp1 and pMod arrays */
+  const uint8_t *pExp;                 /*!< Pointer to Exponent             (Array of expSize elements) */
+  const uint8_t *pOp1;                 /*!< Pointer to Operand              (Array of OpSize elements) */
+  const uint8_t *pMod;                 /*!< Pointer to modulus              (Array of OpSize elements) */
+  const uint32_t *pMontgomeryParam;    /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */
+} PKA_ModExpFastModeInTypeDef;
+
+typedef struct
+{
+  uint32_t size;                       /*!< Number of element in pOp1 array */
+  const uint8_t *pOp1;                 /*!< Pointer to Operand (Array of size elements) */
+} PKA_MontgomeryParamInTypeDef;
+
+typedef struct
+{
+  uint32_t size;                       /*!< Number of element in pOp1 and pOp2 arrays */
+  const uint32_t *pOp1;                /*!< Pointer to Operand 1 (Array of size elements) */
+  const uint32_t *pOp2;                /*!< Pointer to Operand 2 (Array of size elements) */
+} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef;
+
+typedef struct
+{
+  uint32_t size;                       /*!< Number of element in pOp1 array */
+  const uint32_t *pOp1;                /*!< Pointer to Operand 1       (Array of size elements) */
+  const uint8_t *pMod;                 /*!< Pointer to modulus value n (Array of size*4 elements) */
+} PKA_ModInvInTypeDef;
+
+typedef struct
+{
+  uint32_t OpSize;                     /*!< Number of element in pOp1 array */
+  uint32_t modSize;                    /*!< Number of element in pMod array */
+  const uint32_t *pOp1;                /*!< Pointer to Operand 1       (Array of OpSize elements) */
+  const uint8_t *pMod;                 /*!< Pointer to modulus value n (Array of modSize elements) */
+} PKA_ModRedInTypeDef;
+
+typedef struct
+{
+  uint32_t size;                       /*!< Number of element in pOp1 and pOp2 arrays */
+  const uint32_t *pOp1;                /*!< Pointer to Operand 1 (Array of size elements) */
+  const uint32_t *pOp2;                /*!< Pointer to Operand 2 (Array of size elements) */
+  const uint8_t  *pOp3;                /*!< Pointer to Operand 3 (Array of size*4 elements) */
+} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef;
+
+typedef struct
+{
+  uint32_t primeOrderSize;             /*!< curve prime order n length */
+  uint32_t modulusSize;                /*!< curve modulus p length */
+  uint32_t coefSign;                   /*!< curve coefficient a sign */
+  const uint8_t *coefA;                /*!< pointer to curve coefficient |a| */
+  const uint8_t *modulus;              /*!< pointer to curve modulus value p */
+  const uint8_t *integerK;             /*!< pointer to cryptographically secure random integer k */
+  const uint8_t *integerM;             /*!< pointer to cryptographically secure random integer m */
+  const uint8_t *basePointX1;          /*!< pointer to curve base first point coordinate x */
+  const uint8_t *basePointY1;          /*!< pointer to curve base first point coordinate y */
+  const uint8_t *basePointZ1;          /*!< pointer to curve base first point coordinate z */
+  const uint8_t *basePointX2;          /*!< pointer to curve base second point coordinate x */
+  const uint8_t *basePointY2;          /*!< pointer to curve base second point coordinate y */
+  const uint8_t *basePointZ2;          /*!< pointer to curve base second point coordinate z */
+} PKA_ECCDoubleBaseLadderInTypeDef;
+
+typedef struct
+{
+  uint32_t modulusSize;                /*!< curve modulus p length */
+  const uint8_t *modulus;              /*!< pointer to curve modulus value p */
+  const uint8_t *basePointX;           /*!< pointer to curve base point coordinate x */
+  const uint8_t *basePointY;           /*!< pointer to curve base point coordinate y */
+  const uint8_t *basePointZ;           /*!< pointer to curve base point coordinate z */
+  const uint32_t *pMontgomeryParam;    /*!< pointer to montgomery parameter R2 modulus n*/
+} PKA_ECCProjective2AffineInTypeDef;
+
+typedef struct
+{
+  uint32_t modulusSize;                /*!< curve modulus p length */
+  uint32_t coefSign;                   /*!< curve coefficient a sign */
+  const uint8_t *modulus;              /*!< pointer to curve modulus value p */
+  const uint8_t *coefA;                /*!< pointer to curve coefficient |a| */
+  const uint8_t *basePointX1;          /*!< pointer to curve base first point coordinate x */
+  const uint8_t *basePointY1;          /*!< pointer to curve base first point coordinate y */
+  const uint8_t *basePointZ1;          /*!< pointer to curve base first point coordinate z */
+  const uint8_t *basePointX2;          /*!< pointer to curve base second point coordinate x */
+  const uint8_t *basePointY2;          /*!< pointer to curve base second point coordinate y */
+  const uint8_t *basePointZ2;          /*!< pointer to curve base second point coordinate z */
+} PKA_ECCCompleteAdditionInTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PKA_Exported_Constants PKA Exported Constants
+  * @{
+  */
+
+/** @defgroup PKA_Mode PKA mode
+  * @{
+  */
+#define PKA_MODE_MONTGOMERY_PARAM                 (0x00000001U)
+#define PKA_MODE_MODULAR_EXP                      (0x00000000U)
+#define PKA_MODE_MODULAR_EXP_FAST_MODE            (0x00000002U)
+#define PKA_MODE_ECC_MUL                          (0x00000020U)
+#define PKA_MODE_ECDSA_SIGNATURE                  (0x00000024U)
+#define PKA_MODE_ECDSA_VERIFICATION               (0x00000026U)
+#define PKA_MODE_POINT_CHECK                      (0x00000028U)
+#define PKA_MODE_RSA_CRT_EXP                      (0x00000007U)
+#define PKA_MODE_MODULAR_INV                      (0x00000008U)
+#define PKA_MODE_ARITHMETIC_ADD                   (0x00000009U)
+#define PKA_MODE_ARITHMETIC_SUB                   (0x0000000AU)
+#define PKA_MODE_ARITHMETIC_MUL                   (0x0000000BU)
+#define PKA_MODE_COMPARISON                       (0x0000000CU)
+#define PKA_MODE_MODULAR_RED                      (0x0000000DU)
+#define PKA_MODE_MODULAR_ADD                      (0x0000000EU)
+#define PKA_MODE_MODULAR_SUB                      (0x0000000FU)
+#define PKA_MODE_MONTGOMERY_MUL                   (0x00000010U)
+#define PKA_MODE_ECC_PROJECTIVE_AFF               (0x0000002FU)
+#define PKA_MODE_DOUBLE_BASE_LADDER               (0x00000027U)
+#define PKA_MODE_ECC_COMPLETE_ADD                 (0x00000023U)
+#define PKA_MODE_MODULAR_EXP_PROTECT              (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition
+  * @brief PKA Interrupt definition
+  * @{
+  */
+#define PKA_IT_PROCEND                            PKA_CR_PROCENDIE
+#define PKA_IT_ADDRERR                            PKA_CR_ADDRERRIE
+#define PKA_IT_RAMERR                             PKA_CR_RAMERRIE
+#define PKA_IT_OPERR                              PKA_CR_OPERRIE
+
+/**
+  * @}
+  */
+
+/** @defgroup PKA_Flag_definition PKA Flag definition
+  * @{
+  */
+#define PKA_FLAG_PROCEND                          PKA_SR_PROCENDF
+#define PKA_FLAG_ADDRERR                          PKA_SR_ADDRERRF
+#define PKA_FLAG_RAMERR                           PKA_SR_RAMERRF
+#define PKA_FLAG_OPERR                            PKA_SR_OPERRF
+
+/**
+  * @}
+  */
+
+/** @defgroup PKA_Operation_Status PKA Operation Status
+  * @{
+  */
+#define PKA_NO_ERROR                           0xD60DUL
+#define PKA_FAILED_COMPUTATION                 0xCBC9UL
+#define PKA_RPART_SIGNATURE_NULL               0xA3B7UL
+#define PKA_SPART_SIGNATURE_NULL               0xF946UL
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup PKA_Exported_Macros PKA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset PKA handle state.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @retval None
+  */
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_PKA_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified PKA interrupt.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
+  *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
+  *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
+  *            @arg @ref PKA_IT_OPERR Operation error interrupt enable
+  * @retval None
+  */
+#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/** @brief  Disable the specified PKA interrupt.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
+  *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
+  *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
+  *            @arg @ref PKA_IT_OPERR Operation error interrupt enable
+  * @retval None
+  */
+#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified PKA interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @param  __INTERRUPT__ specifies the PKA interrupt source to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
+  *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
+  *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
+  *            @arg @ref PKA_IT_OPERR Operation error interrupt enable
+  * @retval The new state of __INTERRUPT__ (SET or RESET)
+  */
+#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR\
+                                                                   & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified PKA flag is set or not.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref PKA_FLAG_PROCEND End Of Operation
+  *            @arg @ref PKA_FLAG_ADDRERR Address error
+  *            @arg @ref PKA_FLAG_RAMERR RAM error
+  *            @arg @ref PKA_FLAG_OPERR Operation error
+  * @retval The new state of __FLAG__ (SET or RESET)
+  */
+#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->SR)\
+                                                                   & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref PKA_FLAG_PROCEND End Of Operation
+  *            @arg @ref PKA_FLAG_ADDRERR Address error
+  *            @arg @ref PKA_FLAG_RAMERR RAM error
+  *            @arg @ref PKA_FLAG_OPERR Operation error
+  * @retval None
+  */
+#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__)              ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+/** @brief  Enable the specified PKA peripheral.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @retval None
+  */
+#define __HAL_PKA_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR,  PKA_CR_EN))
+
+/** @brief  Disable the specified PKA peripheral.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @retval None
+  */
+#define __HAL_PKA_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
+
+/** @brief  Start a PKA operation.
+  * @param  __HANDLE__ specifies the PKA Handle
+  * @retval None
+  */
+#define __HAL_PKA_START(__HANDLE__)                             (SET_BIT((__HANDLE__)->Instance->CR,  PKA_CR_START))
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PKA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PKA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka);
+HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka);
+void              HAL_PKA_MspInit(PKA_HandleTypeDef *hpka);
+void              HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka);
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID,
+                                           pPKA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup PKA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+/* High Level Functions *******************************************************/
+HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in,
+                                            uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in);
+void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
+void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out,
+                                 PKA_ECDSASignOutExtParamTypeDef *outExt);
+
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
+uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka);
+
+HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
+void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
+uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
+
+HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in);
+void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in);
+void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
+void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
+
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in,
+                                              uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in);
+void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in,
+                                               uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in);
+void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in,
+                                              uint32_t Timeout);
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in);
+void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out);
+
+HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
+void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
+void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);
+void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka);
+void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
+/**
+  * @}
+  */
+
+/** @addtogroup PKA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka);
+uint32_t             HAL_PKA_GetError(const PKA_HandleTypeDef *hpka);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_PKA_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pssi.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pssi.h
new file mode 100644
index 000000000..e69066748
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pssi.h
@@ -0,0 +1,563 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pssi.h
+  * @author  MCD Application Team
+  * @brief   Header file of PSSI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_PSSI_H
+#define STM32N6xx_HAL_PSSI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined(PSSI)
+
+#ifndef USE_HAL_PSSI_REGISTER_CALLBACKS
+/* For backward compatibility, if USE_HAL_PSSI_REGISTER_CALLBACKS not defined, define it to 1*/
+#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
+/** @addtogroup PSSI PSSI
+  * @brief PSSI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Types PSSI Exported Types
+  * @{
+  */
+
+
+/**
+  * @brief PSSI Init structure definition
+  */
+typedef struct
+{
+  uint32_t  DataWidth;          /* !< Configures the data width.
+                                      This parameter can be a value of @ref PSSI_DATA_WIDTH. */
+  uint32_t  BusWidth;           /* !< Configures the parallel bus width.
+                                      This parameter can be a value of @ref PSSI_BUS_WIDTH. */
+  uint32_t  ControlSignal;      /* !< Configures Data enable and Data ready.
+                                      This parameter can be a value of @ref ControlSignal_Configuration. */
+  uint32_t  ClockPolarity;      /* !< Configures the PSSI Input Clock polarity.
+                                      This parameter can be a value of @ref Clock_Polarity. */
+  uint32_t  DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity.
+                                      This parameter can be a value of @ref Data_Enable_Polarity. */
+  uint32_t  ReadyPolarity;      /* !< Configures the PSSI Ready polarity.
+                                      This parameter can be a value of @ref Ready_Polarity. */
+
+} PSSI_InitTypeDef;
+
+
+/**
+  * @brief  HAL PSSI State structures definition
+  */
+typedef enum
+{
+  HAL_PSSI_STATE_RESET   = 0x00U, /* !< PSSI not yet initialized or disabled     */
+  HAL_PSSI_STATE_READY   = 0x01U, /* !< Peripheral initialized and ready for use */
+  HAL_PSSI_STATE_BUSY    = 0x02U, /* !< An internal process is ongoing           */
+  HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing              */
+  HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing               */
+  HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state                            */
+  HAL_PSSI_STATE_ERROR   = 0x06U, /* !< PSSI state error                         */
+  HAL_PSSI_STATE_ABORT   = 0x07U, /* !< PSSI process is aborted                  */
+
+} HAL_PSSI_StateTypeDef;
+
+/**
+  * @brief  PSSI handle Structure definition
+  */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+typedef struct __PSSI_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+{
+  PSSI_TypeDef         *Instance;    /*!< PSSI register base address.    */
+  PSSI_InitTypeDef      Init;        /*!< PSSI Initialization Structure. */
+  uint32_t             *pBuffPtr;    /*!< PSSI Data buffer.              */
+  uint32_t              XferCount;   /*!< PSSI transfer count            */
+  uint32_t              XferSize;    /*!< PSSI  transfer size            */
+#if defined(HAL_DMA_MODULE_ENABLED)
+  DMA_HandleTypeDef    *hdmatx;      /*!< PSSI Tx DMA Handle parameters  */
+  DMA_HandleTypeDef    *hdmarx;      /*!< PSSI Rx DMA Handle parameters  */
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+  void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
+  void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
+  void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi);     /*!< PSSI transfer complete callback. */
+  void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback.    */
+
+  void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi);   /*!< PSSI Msp Init callback.          */
+  void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback.        */
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
+  HAL_LockTypeDef             Lock;                               /*!< PSSI lock.                       */
+  __IO HAL_PSSI_StateTypeDef State;                               /*!< PSSI transfer state.             */
+  __IO uint32_t               ErrorCode;                          /*!< PSSI error code.                 */
+
+} PSSI_HandleTypeDef;
+
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL PSSI Callback pointer definition
+  */
+typedef  void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi);  /*!< Pointer to a PSSI common callback function */
+
+/**
+  * @brief  HAL PSSI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID  */
+  HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID  */
+  HAL_PSSI_ERROR_CB_ID       = 0x03U, /*!< PSSI Error callback ID                  */
+  HAL_PSSI_ABORT_CB_ID       = 0x04U, /*!< PSSI Abort callback ID                  */
+
+  HAL_PSSI_MSPINIT_CB_ID     = 0x05U, /*!< PSSI Msp Init callback ID               */
+  HAL_PSSI_MSPDEINIT_CB_ID   = 0x06U  /*!< PSSI Msp DeInit callback ID             */
+
+} HAL_PSSI_CallbackIDTypeDef;
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Constants PSSI Exported Constants
+  * @{
+  */
+
+/** @defgroup PSSI_Error_Code PSSI Error Code
+  * @{
+  */
+#define HAL_PSSI_ERROR_NONE             0x00000000U /*!< No error                */
+#define HAL_PSSI_ERROR_NOT_SUPPORTED    0x00000001U /*!< Not supported operation */
+#define HAL_PSSI_ERROR_UNDER_RUN        0x00000002U /*!< FIFO Under-run error    */
+#define HAL_PSSI_ERROR_OVER_RUN         0x00000004U /*!< FIFO Over-run  error    */
+#define HAL_PSSI_ERROR_DMA              0x00000008U /*!< Dma     error           */
+#define HAL_PSSI_ERROR_TIMEOUT          0x00000010U /*!< Timeout error           */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error  */
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_DATA_WIDTH PSSI Data Width
+  * @{
+  */
+
+#define HAL_PSSI_8BITS                  0x00000000U   /*!<  8 Bits  */
+#define HAL_PSSI_16BITS                 0x00000001U   /*!< 16 Bits  */
+#define HAL_PSSI_32BITS                 0x00000002U   /*!< 32 Bits  */
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_BUS_WIDTH PSSI Bus Width
+  * @{
+  */
+
+#define HAL_PSSI_8LINES                 0x00000000U   /*!< 8 data lines  */
+#define HAL_PSSI_16LINES                PSSI_CR_EDM   /*!< 16 data lines */
+/**
+  * @}
+  */
+/** @defgroup PSSI_MODE PSSI mode
+  * @{
+  */
+#define HAL_PSSI_UNIDIRECTIONAL         0x00000000U /*!< Uni-directional mode */
+#define HAL_PSSI_BIDIRECTIONAL          0x00000001U /*!< Bi-directional mode  */
+/**
+  * @}
+  */
+
+/** @defgroup ControlSignal_Configuration ControlSignal Configuration
+  * @{
+  */
+#define HAL_PSSI_DE_RDY_DISABLE           (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */
+#define HAL_PSSI_RDY_ENABLE               (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */
+#define HAL_PSSI_DE_ENABLE                (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */
+#define HAL_PSSI_DE_RDY_ALT_ENABLE        (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */
+#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE     (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */
+#define HAL_PSSI_RDY_MAP_ENABLE           (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */
+#define HAL_PSSI_DE_MAP_ENABLE            (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */
+#define HAL_PSSI_MAP_DE_BIDIR_ENABLE      (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup Data_Enable_Polarity Data Enable Polarity
+  * @{
+  */
+#define HAL_PSSI_DEPOL_ACTIVE_LOW         0x0U            /*!< Active Low */
+#define HAL_PSSI_DEPOL_ACTIVE_HIGH        PSSI_CR_DEPOL   /*!< Active High */
+/**
+  * @}
+  */
+/** @defgroup Ready_Polarity Ready Polarity
+  * @{
+  */
+#define HAL_PSSI_RDYPOL_ACTIVE_LOW        0x0U            /*!< Active Low */
+#define HAL_PSSI_RDYPOL_ACTIVE_HIGH       PSSI_CR_RDYPOL  /*!< Active High */
+/**
+  * @}
+  */
+
+/** @defgroup Clock_Polarity Clock Polarity
+  * @{
+  */
+#define HAL_PSSI_FALLING_EDGE             0x0U            /*!< Fallling Edge */
+#define HAL_PSSI_RISING_EDGE              0x1U            /*!< Rising Edge */
+/**
+  * @}
+  */
+
+/** @defgroup Clock_Source Clock Source
+  * @{
+  */
+#define HAL_PSSI_CLOCK_EXT                0x0U                     /*!< External Clock */
+#define HAL_PSSI_CLOCK_INT                PSSI_CR_CKSRC            /*!< Internal Clock */
+/**
+  * @}
+  */
+
+
+/** @defgroup PSSI_DEFINITION PSSI definitions
+  * @{
+  */
+
+#define PSSI_MAX_NBYTE_SIZE         0x10000U         /* 64 KB */
+#define PSSI_TIMEOUT_TRANSMIT       0x0000FFFFU      /*!< Timeout Value   */
+
+#define PSSI_CR_OUTEN_INPUT         0x00000000U      /*!< Input Mode      */
+#define PSSI_CR_OUTEN_OUTPUT        PSSI_CR_OUTEN    /*!< Output Mode     */
+
+#define PSSI_CR_DMA_ENABLE          PSSI_CR_DMAEN    /*!< DMA Mode Enable */
+#define PSSI_CR_DMA_DISABLE         (~PSSI_CR_DMAEN) /*!< DMA Mode Disable*/
+
+#define PSSI_CR_16BITS              PSSI_CR_EDM      /*!< 16 Lines Mode   */
+#define PSSI_CR_8BITS               (~PSSI_CR_EDM)   /*!< 8 Lines Mode    */
+
+#define PSSI_FLAG_RTT1B             PSSI_SR_RTT1B    /*!< 1 Byte Fifo Flag */
+#define PSSI_FLAG_RTT4B             PSSI_SR_RTT4B    /*!< 4 Bytes Fifo Flag*/
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_Interrupts PSSI Interrupts
+  * @{
+  */
+
+#define PSSI_FLAG_OVR_RIS            PSSI_RIS_OVR_RIS     /*!< Overrun, Underrun errors flag */
+#define PSSI_FLAG_MASK               PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */
+#define PSSI_FLAG_OVR_MIS            PSSI_MIS_OVR_MIS     /*!< Overrun, Underrun masked errors flag */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Macros PSSI Exported Macros
+  * @{
+  */
+
+/** @brief Reset PSSI handle state
+  * @param  __HANDLE__ specifies the PSSI handle.
+  * @retval None
+  */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
+                                                      (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;       \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                     }while(0)
+#else
+#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PSSI_STATE_RESET)
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
+
+/**
+  * @brief  Enable the PSSI.
+  * @param  __HANDLE__ PSSI handle
+  * @retval None.
+  */
+#define HAL_PSSI_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)
+/**
+  * @brief  Disable the PSSI.
+  * @param  __HANDLE__ PSSI handle
+  * @retval None.
+  */
+#define HAL_PSSI_DISABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))
+
+/* PSSI pripheral STATUS */
+/**
+  * @brief  Get the PSSI pending flags.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __FLAG__ flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_RTT1B:  FIFO is ready to transfer one byte
+  *            @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes
+  * @retval The state of FLAG.
+  */
+
+#define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
+
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the PSSI pending flags.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __FLAG__ flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
+  * @retval The state of FLAG.
+  */
+#define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__))
+
+/**
+  * @brief  Clear the PSSI pending flags.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
+  * @retval None
+  */
+#define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified PSSI interrupts.
+  * @param  __HANDLE__ PSSI handle
+  * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_OVR_RIS: Configuration error mask
+  * @retval None
+  */
+#define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified PSSI interrupts.
+  * @param  __HANDLE__ PSSI handle
+  * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_IT_OVR_IE: Configuration error mask
+  * @retval None
+  */
+#define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified PSSI interrupt source is enabled or not.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __INTERRUPT__ specifies the PSSI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask
+  * @retval The state of INTERRUPT source.
+  */
+#define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+
+/**
+  * @brief  Check whether the PSSI Control signal is valid.
+  * @param  __CONTROL__ Control signals configuration
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE        ) || \
+                                             ((__CONTROL__) == HAL_PSSI_RDY_ENABLE            ) || \
+                                             ((__CONTROL__) == HAL_PSSI_DE_ENABLE             ) || \
+                                             ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE     ) || \
+                                             ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE  ) || \
+                                             ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE        ) || \
+                                             ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE         ) || \
+                                             ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE   ))
+
+
+/**
+  * @brief  Check whether the PSSI Bus Width is valid.
+  * @param  __BUSWIDTH__ PSSI Bush width
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES    ) || \
+                                        ((__BUSWIDTH__) == HAL_PSSI_16LINES   ))
+
+/**
+
+  * @brief  Check whether the PSSI Clock Polarity is valid.
+  * @param  __CLOCKPOL__ PSSI Clock Polarity
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE   ) || \
+                                              ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE    ))
+
+
+/**
+  * @brief  Check whether the PSSI Data Enable Polarity is valid.
+  * @param  __DEPOL__ PSSI DE Polarity
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW    ) || \
+                                        ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH   ))
+
+/**
+  * @brief  Check whether the PSSI Ready Polarity is valid.
+  * @param  __RDYPOL__ PSSI RDY Polarity
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW   ) || \
+                                          ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH   ))
+
+/**
+  * @brief  Check whether the PSSI Clock source is valid.
+  * @param  __CLOCKSRC__ PSSI Clock Source
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_CLOCK_SOURCE(__CLOCKSRC__) (((__CLOCKSRC__) == HAL_PSSI_CLOCK_EXT   ) || \
+                                            ((__CLOCKSRC__) == HAL_PSSI_CLOCK_INT   ))
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PSSI_Exported_Functions PSSI Exported Functions
+  * @{
+  */
+
+/** @addtogroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi);
+HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
+void              HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);
+void              HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
+                                            pPSSI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup PSSI_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State functions ***************************************************/
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi);
+uint32_t              HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi);
+
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_Exported_Functions_Group4 Clock Source Selection function
+  * @{
+  */
+/* Clock source selection function  *******************************************/
+HAL_StatusTypeDef HAL_PSSI_ClockConfig(PSSI_HandleTypeDef *hpssi, uint32_t ClockSource);
+
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+
+void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+
+
+/* Private macros ------------------------------------------------------------*/
+
+
+/**
+  * @}
+  */
+#endif /* PSSI */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_PSSI_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pwr.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pwr.h
new file mode 100644
index 000000000..8148b02e4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pwr.h
@@ -0,0 +1,683 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_PWR_H
+#define STM32N6xx_HAL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Mode;     /*!< Specifies the operating mode for the selected pins.
+                          This parameter can be a value of @ref PWR_PVD_Mode. */
+} PWR_PVDTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                (0x00000000U)                       /*!< Basic mode is used                                        */
+#define PWR_PVD_MODE_IT_RISING             (0x00010001U)                       /*!< Interrupt Mode with Rising edge trigger detection         */
+#define PWR_PVD_MODE_IT_FALLING            (0x00010002U)                       /*!< Interrupt Mode with Falling edge trigger detection        */
+#define PWR_PVD_MODE_IT_RISING_FALLING     (0x00010003U)                       /*!< Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING          (0x00020001U)                       /*!< Event Mode with Rising edge trigger detection             */
+#define PWR_PVD_MODE_EVENT_FALLING         (0x00020002U)                       /*!< Event Mode with Falling edge trigger detection            */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING  (0x00020003U)                       /*!< Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_LP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+/* define for interface compatibility purpose */
+#define PWR_MAINREGULATOR_ON           (0U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              (1U)                                   /*!< Wait For Interruption instruction to enter Sleep mode */
+#define PWR_SLEEPENTRY_WFE              (2U)                                   /*!< Wait For Event instruction to enter Sleep mode        */
+#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (3U)                                   /*!< Wait For Event instruction to enter Sleep mode with no event clear */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI              (1U)                                    /*!< Wait For Interruption instruction to enter Stop mode */
+#define PWR_STOPENTRY_WFE              (2U)                                    /*!< Wait For Event instruction to enter Stop mode        */
+#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (3U)                                    /*!< Wait For Event instruction to enter Stop mode with no event clear */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
+  * @{
+  */
+#define  PWR_EWUP_MASK                 (0x00FF0F0FU)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_WakeUp_Pins PWR Wake-Up Pins
+  * @{
+  */
+/* High level and No pull (default configuration) */
+#define PWR_WAKEUP_PIN4                PWR_WKUPEPR_WKUPEN4                     /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN3                PWR_WKUPEPR_WKUPEN3                     /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN2                PWR_WKUPEPR_WKUPEN2                     /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN1                PWR_WKUPEPR_WKUPEN1                     /*!< Wakeup pin 4 (with high level polarity) */
+
+/* High level and No pull */
+#define PWR_WAKEUP_PIN4_HIGH           PWR_WKUPEPR_WKUPEN4                     /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN3_HIGH           PWR_WKUPEPR_WKUPEN3                     /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN2_HIGH           PWR_WKUPEPR_WKUPEN2                     /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_HIGH           PWR_WKUPEPR_WKUPEN1                     /*!< Wakeup pin 4 (with high level polarity) */
+
+/* Low level and No pull */
+#define PWR_WAKEUP_PIN4_LOW            (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)  /*!< Wakeup pin 1 (with low level polarity) */
+#define PWR_WAKEUP_PIN3_LOW            (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)  /*!< Wakeup pin 2 (with low level polarity) */
+#define PWR_WAKEUP_PIN2_LOW            (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)  /*!< Wakeup pin 3 (with low level polarity) */
+#define PWR_WAKEUP_PIN1_LOW            (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)  /*!< Wakeup pin 4 (with low level polarity) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag_WUP PWR Flag WakeUp
+  * @{
+  */
+#define PWR_FLAG_WKUP1                 PWR_WKUPCR_WKUPC1
+#define PWR_FLAG_WKUP2                 PWR_WKUPCR_WKUPC2
+#define PWR_FLAG_WKUP3                 PWR_WKUPCR_WKUPC3
+#define PWR_FLAG_WKUP4                 PWR_WKUPCR_WKUPC4
+#define PWR_FLAG_WKUP                  (PWR_FLAG_WKUP1 | PWR_WKUPCR_WKUPC2 | \
+                                        PWR_FLAG_WKUP3 | PWR_WKUPCR_WKUPC4)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PIN_Polarity PWR Pin Polarity configuration
+  * @{
+  */
+#define PWR_PIN_POLARITY_HIGH          (0x0U)
+#define PWR_PIN_POLARITY_LOW           (0x1U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PIN_Pull PWR Pin Pull configuration
+  * @{
+  */
+#define PWR_PIN_NO_PULL                (0x0U)
+#define PWR_PIN_PULL_UP                (0x1U)
+#define PWR_PIN_PULL_DOWN              (0x2U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Wakeup_Pins_Flags PWR Wakeup Pins Flags.
+  * @{
+  */
+#define PWR_WAKEUP_FLAG1               PWR_WKUPSR_WKUPF1                       /*!< Wakeup flag on PA0  */
+#define PWR_WAKEUP_FLAG2               PWR_WKUPSR_WKUPF2                       /*!< Wakeup flag on PA2  */
+#define PWR_WAKEUP_FLAG3               PWR_WKUPSR_WKUPF3                       /*!< Wakeup flag on PC13 */
+#define PWR_WAKEUP_FLAG4               PWR_WKUPSR_WKUPF4                       /*!< Wakeup flag on PD2  */
+
+#define PWR_WAKEUP_FLAG_ALL           (PWR_WKUPSR_WKUPF1 | PWR_WKUPSR_WKUPF2 |\
+                                       PWR_WKUPSR_WKUPF3 | PWR_WKUPSR_WKUPF4)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Items PWR Items
+  * @{
+  */
+
+/* Use the PWR_SECCFGR bits definition offset for both Secure and Privilege because
+   it is the same offset value for the same item */
+#define PWR_ITEM_0                     PWR_SECCFGR_SEC0                        /*!< System supply configuration secure/privilege protection       */
+#define PWR_ITEM_1                     PWR_SECCFGR_SEC1                        /*!< Programmable voltage detector secure/privilege protection     */
+#define PWR_ITEM_2                     PWR_SECCFGR_SEC2                        /*!< VDDCORE monitor secure/privilege protection                   */
+#define PWR_ITEM_3                     PWR_SECCFGR_SEC3                        /*!< TCM and FLEXMEM low power control secure/privilege protection */
+#define PWR_ITEM_4                     PWR_SECCFGR_SEC4                        /*!< Voltage scaling selection secure/privilege protection         */
+#define PWR_ITEM_5                     PWR_SECCFGR_SEC5                        /*!< Backup domain secure/privilege protection                     */
+#define PWR_ITEM_6                     PWR_SECCFGR_SEC6                        /*!< CPU power control secure/privilege protection                 */
+#define PWR_ITEM_7                     PWR_SECCFGR_SEC7                        /*!< Peripheral voltage monitor secure/privilege protection        */
+#define PWR_ITEM_WKUP1                 PWR_SECCFGR_WKUPSEC1                    /*!< WKUP1 pin secure/privilege protection                         */
+#define PWR_ITEM_WKUP2                 PWR_SECCFGR_WKUPSEC2                    /*!< WKUP2 pin secure/privilege protection                         */
+#define PWR_ITEM_WKUP3                 PWR_SECCFGR_WKUPSEC3                    /*!< WKUP3 pin secure/privilege protection                         */
+#define PWR_ITEM_WKUP4                 PWR_SECCFGR_WKUPSEC4                    /*!< WKUP4 pin secure/privilege protection                         */
+
+#define PWR_ITEM_ALL                   (PWR_ITEM_0 | PWR_ITEM_1 | PWR_ITEM_2 | PWR_ITEM_3 | PWR_ITEM_4 | PWR_ITEM_5 | \
+                                        PWR_ITEM_6 | PWR_ITEM_7 | PWR_ITEM_WKUP1 | PWR_ITEM_WKUP2 | PWR_ITEM_WKUP3 | \
+                                        PWR_ITEM_WKUP4)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Attributes PWR Attributes
+  * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes
+  * @{
+  */
+/* Defines attribute */
+#define PWR_ITEM_ATTR_NSEC_PRIV_MASK   (0x10U)                                 /*!< NSecure Privilege / NPrivilege attribute item mask */
+#define PWR_ITEM_ATTR_SEC_PRIV_MASK    (0x20U)                                 /*!< Secure Privilege / NPrivilege attribute item mask  */
+
+#define PWR_NSEC_PRIV                  (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U)  /*!< NSecure and Privileged attribute  */
+#define PWR_NSEC_NPRIV                 PWR_ITEM_ATTR_NSEC_PRIV_MASK            /*!< NSecure and NPrivileged attribute */
+#define PWR_SEC_PRIV                   (PWR_ITEM_ATTR_SEC_PRIV_MASK  | 0x02U)  /*!< Secure and Privileged attribute   */
+#define PWR_SEC_NPRIV                  PWR_ITEM_ATTR_SEC_PRIV_MASK             /*!< Secure and NPrivileged attribute  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Status Flags
+  *        Elements values convention: 0000 00XX XXXX XXXY YYYYb
+  *           -      Y YYYY : Flag position in the XXX register (5 bits)
+  *           - XX XXXX XXX : Status register (9 bits)
+  *             - 000000001: CR2    register
+  *             - 000000010: VOSCR  register
+  *             - 000000100: CR3    register
+  *             - 000001000: BDCR1  register
+  *             - 000010000: CPUCR  register
+  *             - 000100000: SVMCR1 register
+  *             - 001000000: SVMCR2 register
+  *             - 010000000: SVMCR3 register
+  *             - 100000000: WKUPSR register
+  * @{
+  */
+/* CR2 */
+#define PWR_FLAG_PVDO                  (0x0028U)                               /*!< Programmable voltage detect output */
+
+/* VOSCR */
+#define PWR_FLAG_ACTVOSRDY             (0x0051U)                               /*!< Voltage levels ready bit                                 */
+#define PWR_FLAG_ACTVOS                (0x0050U)                               /*!< Programmable voltage detect output                       */
+#define PWR_FLAG_VOSRDY                (0x0041U)                               /*!< VOS Ready bit for VCORE voltage scaling output selection */
+
+/* CR3 */
+#define PWR_FLAG_VCOREH                (0x0089U)                               /*!< VDDCORE level monitoring versus high threshold */
+#define PWR_FLAG_VCOREL                (0x0088U)                               /*!< VDDCORE level monitoring versus low threshold  */
+
+/* BDCR1 */
+#define PWR_FLAG_TEMPH                 (0x0113U)                               /*!< Temperature level monitoring versus high threshold */
+#define PWR_FLAG_TEMPL                 (0x0112U)                               /*!< Temperature level monitoring versus low threshold  */
+#define PWR_FLAG_VBATH                 (0x0111U)                               /*!< VBAT level monitoring versus high threshold        */
+#define PWR_FLAG_VBATL                 (0x0110U)                               /*!< VBAT level monitoring versus low threshold         */
+
+/* CPUCR */
+#define PWR_FLAG_SBF                   (0x0209U)                               /*!< System Standby flag */
+#define PWR_FLAG_STOPF                 (0x0208U)                               /*!< System Stop flag    */
+
+/* SVMCR1 */
+#define PWR_FLAG_VDDIO4RDY             (0x0410U)                               /*!< VDDIO4 ready  */
+
+
+/* SVMCR2 */
+#define PWR_FLAG_VDDIO5RDY             (0x0810U)                               /*!< VDDIO5 ready  */
+
+/* SVMCR3 */
+#define PWR_FLAG_ARDY                  (0x1014U)                               /*!< VDDA18ADC ready */
+#define PWR_FLAG_USB33RDY              (0x1012U)                               /*!< VDD33USB ready  */
+#define PWR_FLAG_VDDIO3RDY             (0x1011U)                               /*!< VDDIO3 ready    */
+#define PWR_FLAG_VDDIO2RDY             (0x1010U)                               /*!< VDDIO2 ready    */
+
+/* WKUPSR */
+#define PWR_FLAG_WKUPF4                (0x2004U)                               /*!< Wakeup event on wakeup pin 4 */
+#define PWR_FLAG_WKUPF3                (0x2003U)                               /*!< Wakeup event on wakeup pin 3 */
+#define PWR_FLAG_WKUPF2                (0x2002U)                               /*!< Wakeup event on wakeup pin 2 */
+#define PWR_FLAG_WKUPF1                (0x2001U)                               /*!< Wakeup event on wakeup pin 1 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  Check whether or not a specific PWR flag is set.
+  * @param  __FLAG__ specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *          @arg PWR_FLAG_PVDO:      This flag is valid only if PVD
+  *                                   is enabled by the HAL_PWR_EnablePVD()function.
+  *                                   The PVD is stopped by STANDBY mode.
+  *          @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the regulator voltage
+  *                                   scaling output selection is ready.
+  *          @arg PWR_FLAG_ACTVOS:    This flag indicates that the regulator voltage
+  *                                   scaling output selection is ready.
+  *          @arg PWR_FLAG_VOSRDY     When an internal regulator is used, this bit indicates
+  *                                   that all the features allowed by the selected VOS can be used.
+  *          @arg PWR_FLAG_VCOREH:    This flag indicates if the VDDCORE level is above
+  *                                   the high monitoring threshold.
+  *          @arg PWR_FLAG_VCOREL     This flag indicates if the VDDCORE level is above
+  *                                   the low monitoring threshold.
+  *          @arg PWR_FLAG_TEMPH:     This flag indicates if the temperature level is above
+  *                                   the high monitoring threshold.
+  *          @arg PWR_FLAG_TEMPL      This flag indicates if the temperature level is above
+  *                                   the low monitoring threshold.
+  *          @arg PWR_FLAG_VBATH:     This flag indicates if the VBAT level is above
+  *                                   the high monitoring threshold.
+  *          @arg PWR_FLAG_VBATL:     This flag indicates if the VBAT level is above
+  *                                   the low monitoring threshold.
+  *          @arg PWR_FLAG_SBF:       Standby mode flag.
+  *          @arg PWR_FLAG_STOPF:     STOP mode flag.
+  *          @arg PWR_FLAG_VDDIO5RDY: This flag indicates if the VDDIO5 is ready.
+  *          @arg PWR_FLAG_VDDIO4RDY: This flag indicates if the VDDIO4 is ready.
+  *          @arg PWR_FLAG_VDDIO3RDY: This flag indicates if the VDDIO3 is ready.
+  *          @arg PWR_FLAG_VDDIO2RDY: This flag indicates if the VDDIO2 is ready.
+  *          @arg PWR_FLAG_ARDY:      This flag indicates if the VDDA18ADC is ready.
+  *          @arg PWR_FLAG_USB33RDY:  This flag indicates if the VDD33USB is ready.
+  *          @arg PWR_FLAG_WUF1:      This flag indicates a wakeup event was
+  *                                   received from WKUP1 pin.
+  *          @arg PWR_FLAG_WUF2:      This flag indicates a wakeup event was
+  *                                   received from WKUP2 pin.
+  *          @arg PWR_FLAG_WUF3:      This flag indicates a wakeup event was
+  *                                   received from WKUP3 pin.
+  *          @arg PWR_FLAG_WUF4:      This flag indicates a wakeup event was
+  *                                   received from WKUP4 pin.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
+                ((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CR2 & PWR_CR2_PVDO)            == PWR_CR2_PVDO)         : \
+                ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->VOSCR & PWR_VOSCR_ACTVOSRDY)   == PWR_VOSCR_ACTVOSRDY)  : \
+                ((__FLAG__) == PWR_FLAG_ACTVOS)    ? ((PWR->VOSCR & PWR_VOSCR_ACTVOS)      == PWR_VOSCR_ACTVOS)     : \
+                ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->VOSCR & PWR_VOSCR_VOSRDY)      == PWR_VOSCR_VOSRDY)     : \
+                ((__FLAG__) == PWR_FLAG_VCOREH)    ? ((PWR->CR3 & PWR_CR3_VCOREH)          == PWR_CR3_VCOREH)       : \
+                ((__FLAG__) == PWR_FLAG_VCOREL)    ? ((PWR->CR3 & PWR_CR3_VCOREL)          == PWR_CR3_VCOREL)       : \
+                ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->BDCR1 & PWR_BDCR1_TEMPH)       == PWR_BDCR1_TEMPH)      : \
+                ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->BDCR1 & PWR_BDCR1_TEMPL)       == PWR_BDCR1_TEMPL)      : \
+                ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->BDCR1 & PWR_BDCR1_VBATH)       == PWR_BDCR1_VBATH)      : \
+                ((__FLAG__) == PWR_FLAG_VBATL)     ? ((PWR->BDCR1 & PWR_BDCR1_VBATL)       == PWR_BDCR1_VBATL)      : \
+                ((__FLAG__) == PWR_FLAG_SBF)       ? ((PWR->CPUCR & PWR_CPUCR_SBF)         == PWR_CPUCR_SBF)        : \
+                ((__FLAG__) == PWR_FLAG_STOPF)     ? ((PWR->CPUCR & PWR_CPUCR_STOPF)       == PWR_CPUCR_STOPF)      : \
+                ((__FLAG__) == PWR_FLAG_VDDIO4RDY) ? ((PWR->SVMCR1 & PWR_SVMCR1_VDDIO4RDY) == PWR_SVMCR1_VDDIO4RDY) : \
+                ((__FLAG__) == PWR_FLAG_VDDIO5RDY) ? ((PWR->SVMCR2 & PWR_SVMCR2_VDDIO5RDY) == PWR_SVMCR2_VDDIO5RDY) : \
+                ((__FLAG__) == PWR_FLAG_ARDY)      ? ((PWR->SVMCR3 & PWR_SVMCR3_ARDY)      == PWR_SVMCR3_ARDY)      : \
+                ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->SVMCR3 & PWR_SVMCR3_USB33RDY)  == PWR_SVMCR3_USB33RDY)  : \
+                ((__FLAG__) == PWR_FLAG_VDDIO3RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_VDDIO3RDY) == PWR_SVMCR3_VDDIO3RDY) : \
+                ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_VDDIO2RDY) == PWR_SVMCR3_VDDIO2RDY) : \
+                ((__FLAG__) == PWR_FLAG_WKUPF4)    ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF4)    == PWR_WKUPSR_WKUPF4)    : \
+                ((__FLAG__) == PWR_FLAG_WKUPF3)    ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF3)    == PWR_WKUPSR_WKUPF3)    : \
+                ((__FLAG__) == PWR_FLAG_WKUPF2)    ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF2)    == PWR_WKUPSR_WKUPF2)    : \
+                ((__FLAG__) == PWR_FLAG_WKUPF1)    ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF1)    == PWR_WKUPSR_WKUPF1)    : \
+                ((PWR->WKUPSR & PWR_WKUPSR_WKUPF4) == PWR_WKUPSR_WKUPF4))
+
+/** @brief  Clear PWR flags.
+  * @param  __FLAG__: specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_FLAG_STOPF  : Stop flag.
+  *                                  Indicates that the device was resumed from Stop mode.
+  *           @arg PWR_FLAG_SBF    : Standby flag.
+  *                                  Indicates that the device was resumed from Standby mode.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \
+                                        ((__FLAG__) == PWR_FLAG_STOPF)  ? (SET_BIT(PWR->CPUCR,   PWR_CPUCR_CSSF))   : \
+                                        ((__FLAG__) == PWR_FLAG_SBF)    ? (SET_BIT(PWR->CPUCR,   PWR_CPUCR_CSSF))   : \
+                                        (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)))
+
+/** @brief  Check PWR wake up flags are set or not.
+  * @param  __FLAG__: specifies the wake up flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WKUP1 : This parameter gets Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter gets Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter gets Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter gets Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP  : This parameter gets Wake up lines 1 to 4 flags.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0U : 1U)
+
+/** @brief  Clear CPU PWR wake up flags.
+  * @param  __FLAG__ : Specifies the wake up flag to be cleared.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_FLAG_WKUP1 : This parameter clears Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clears Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clears Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clears Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP  : This parameter clears Wake up lines 1 to 4 flags.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Disable the PVD Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Enable the PVD Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Disable the PVD Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                    \
+  {                                                     \
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0);
+
+/**
+  * @brief  Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                     \
+  {                                                      \
+    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0);
+
+/**
+  * @brief  Check whether or not the PVD EXTI interrupt Rising flag is set.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR3 & PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Check whether or not the PVD EXTI interrupt Falling flag is set.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR3 & PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Clear the PVD EXTI interrupt Rising flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Clear the PVD EXTI interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVD)
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD              EXTI_IMR3_IM66                          /*!< External interrupt line 66 connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+
+/* Check PVD mode parameter */
+#define IS_PWR_PVD_MODE(__MODE__) (((__MODE__) == PWR_PVD_MODE_IT_RISING)            ||\
+                                   ((__MODE__) == PWR_PVD_MODE_IT_FALLING)           ||\
+                                   ((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
+                                   ((__MODE__) == PWR_PVD_MODE_EVENT_RISING)         ||\
+                                   ((__MODE__) == PWR_PVD_MODE_EVENT_FALLING)        ||\
+                                   ((__MODE__) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
+                                   ((__MODE__) == PWR_PVD_MODE_NORMAL))
+
+/* Check Sleep mode entry parameter */
+#define IS_PWR_SLEEP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_SLEEPENTRY_WFI) ||\
+                                       ((__ENTRY__) == PWR_SLEEPENTRY_WFE) ||\
+                                       ((__ENTRY__) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR))
+
+/* Check Stop mode mode entry parameter */
+#define IS_PWR_STOP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_STOPENTRY_WFI) ||\
+                                      ((__ENTRY__) == PWR_STOPENTRY_WFE) ||\
+                                      ((__ENTRY__) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR))
+
+/* Check wake up pin parameter */
+#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1)      ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN2)      ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN3)      ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN4)      ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN1_LOW)  ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN2_LOW)  ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN3_LOW)  ||\
+                                    ((__PIN__) == PWR_WAKEUP_PIN4_LOW))
+
+/* Check wake up pin polarity parameter */
+#define IS_PWR_WAKEUP_PIN_POLARITY(__POLARITY__) (((__POLARITY__) == PWR_PIN_POLARITY_HIGH) ||\
+                                                  ((__POLARITY__) == PWR_PIN_POLARITY_LOW))
+
+/* Check wake up pin pull configuration parameter */
+#define IS_PWR_WAKEUP_PIN_PULL(__PULL__) (((__PULL__) == PWR_PIN_NO_PULL) ||\
+                                          ((__PULL__) == PWR_PIN_PULL_UP) ||\
+                                          ((__PULL__) == PWR_PIN_PULL_DOWN))
+
+/* Check wake up flag parameter */
+#define IS_PWR_WAKEUP_FLAG(__FLAG__) (((__FLAG__) == PWR_WAKEUP_FLAG1) ||\
+                                      ((__FLAG__) == PWR_WAKEUP_FLAG2) ||\
+                                      ((__FLAG__) == PWR_WAKEUP_FLAG3) ||\
+                                      ((__FLAG__) == PWR_WAKEUP_FLAG4) ||\
+                                      ((__FLAG__) == PWR_WAKEUP_FLAG_ALL))
+
+
+/* PWR Secure/Privilege items check macro */
+#define IS_PWR_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & (~PWR_ITEM_ALL)) == 0U) && ((__ITEM__) != 0U))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* PWR attribute check macro (Secure) */
+#define IS_PWR_ATTRIBUTES(ATTRIBUTES) ((((~(((ATTRIBUTES)& \
+                                             0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && \
+                                       (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U))
+#else
+/* PWR attribute check macro (NSecure) */
+#define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV))
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extended module */
+#include "stm32n6xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions
+  * @{
+  */
+/* Peripheral Control Functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *pConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void              HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void              HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+uint32_t          HAL_PWR_GetWakeupFlag(uint32_t WakeUpFlag);
+HAL_StatusTypeDef HAL_PWR_ClearWakeupFlag(uint32_t WakeUpFlag);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+/* Interrupt handler functions ************************************************/
+void HAL_PWR_PVD_Rising_Callback(void);
+void HAL_PWR_PVD_Falling_Callback(void);
+void HAL_PWR_WAKEUP_PIN_IRQHandler(void);
+void HAL_PWR_WKUP1_Callback(void);
+void HAL_PWR_WKUP2_Callback(void);
+void HAL_PWR_WKUP3_Callback(void);
+void HAL_PWR_WKUP4_Callback(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group3
+  * @{
+  */
+/* Privileges and security configuration functions ****************************/
+void              HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes);
+HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32N6xx_HAL_PWR_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pwr_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pwr_ex.h
new file mode 100644
index 000000000..30767d3c2
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_pwr_ex.h
@@ -0,0 +1,1141 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_PWR_EX_H
+#define STM32N6xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+  * @{
+  */
+/**
+  * @brief  PWREx Wakeup pin configuration structure definition
+  */
+typedef struct
+{
+  uint32_t WakeUpPin;   /*!< Specifies the Wake-Up pin to be enabled.
+                             This parameter can be a value of @ref PWR_WakeUp_Pins  */
+
+  uint32_t PinPolarity; /*!< Specifies the Wake-Up pin polarity.
+                             This parameter can be a value of @ref PWR_PIN_Polarity */
+
+  uint32_t PinPull;     /*!< Specifies the Wake-Up pin pull.
+                             This parameter can be a value of @ref PWR_PIN_Pull     */
+} PWREx_WakeupPinTypeDef;
+
+/**
+  * @brief  PWR PVM configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVMType;   /*!< Specifies which voltage is monitored.
+                           This parameter can be a value of
+                           @ref PWREx_PVM_Type.                               */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of
+                           @ref PWREx_PVM_Mode.                               */
+} PWR_PVMTypeDef;
+
+
+/**
+  * @brief  PWR VddCORE monitoring configuration structure definition
+  */
+typedef struct
+{
+  uint32_t LowVoltageThreshold;   /*!< Specifies the VDDCORE voltage detector low-level.
+                                       This parameter can be a value of
+                                       @ref PWREx_VDDCORE_Levels.                          */
+
+  uint32_t Mode;                  /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of
+                                       @ref PWREx_VddCOREVM_Mode.                          */
+} PWR_VddCOREVMTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
+  * @{
+  */
+#define PWR_SMPS_SUPPLY                PWR_CR1_SDEN                            /*!< VCORE power domains are supplied from SMPS step-down converter according to VOS */
+#define PWR_EXTERNAL_SOURCE_SUPPLY     (0U)                                    /*!< SMPS step-down converter disabled. VCORE supplied from external source          */
+
+#define PWR_SUPPLY_CONFIG_MASK         PWR_CR1_SDEN
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
+  * @{
+  */
+#define PWR_REGULATOR_VOLTAGE_SCALE0   PWR_VOSCR_VOS                           /*!< Voltage scaling range 0 (highest frequency) */
+#define PWR_REGULATOR_VOLTAGE_SCALE1   (0U)                                    /*!< Voltage scaling range 1 (lowest power)      */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+  * @{
+  */
+#define PWR_REGULATOR_STOP_VOLTAGE_SCALE3    PWR_CPUCR_SVOS                    /*!< System Stop mode voltage scaling range 3 (highest frequency) */
+#define PWR_REGULATOR_STOP_VOLTAGE_SCALE5    (0U)                              /*!< System Stop mode voltage scaling range 5 (lowest power)      */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
+  * @{
+  */
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD    (0U)
+#define PWR_VBAT_BELOW_LOW_THRESHOLD           PWR_BDCR1_VBATL
+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD          PWR_BDCR1_VBATH
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
+  * @{
+  */
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0U)
+#define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_BDCR1_TEMPL
+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_BDCR1_TEMPH
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VDDCORE_Levels PWREx VDDCORE voltage detector low-level
+  * @{
+  */
+#define PWR_VDDCORE_THRESHOLD_VOS0     PWR_CR3_VCORELLS
+#define PWR_VDDCORE_THRESHOLD_VOS1     (0U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VDDCORE_Thresholds PWREx VDDCORE voltage detector low-level Thresholds
+  * @{
+  */
+#define PWR_VDDCORE_BETWEEN_HIGH_LOW_THRESHOLD  (0U)
+#define PWR_VDDCORE_BELOW_LOW_THRESHOLD         PWR_CR3_VCOREL
+#define PWR_VDDCORE_ABOVE_HIGH_THRESHOLD        PWR_CR3_VCOREH
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VddCOREVM_Mode PWR Extended VddCORE Monitoring Interrupt and Event Mode
+  * @{
+  */
+#define PWR_VDDCOREVM_MODE_NORMAL               (0x00U)                        /*!< Basic Mode is used                                                 */
+#define PWR_VDDCOREVM_MODE_IT_RISING            (0x05U)                        /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define PWR_VDDCOREVM_MODE_IT_FALLING           (0x06U)                        /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define PWR_VDDCOREVM_MODE_IT_RISING_FALLING    (0x07U)                        /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_VDDCOREVM_MODE_EVENT_RISING         (0x09U)                        /*!< Event Mode with Rising edge trigger detection                      */
+#define PWR_VDDCOREVM_MODE_EVENT_FALLING        (0x0AU)                        /*!< Event Mode with Falling edge trigger detection                     */
+#define PWR_VDDCOREVM_MODE_EVENT_RISING_FALLING (0x0BU)                        /*!< Event Mode with Rising/Falling edge trigger detection              */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VDDIO PWREx Vdd IO selection
+  * @{
+  */
+#define PWR_VDDIO                      (0U)
+#define PWR_VDDIO2                     (1U)
+#define PWR_VDDIO3                     (2U)
+#define PWR_VDDIO4                     (3U)
+#define PWR_VDDIO5                     (4U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VDDIO_Range PWREx Vdd IO Range
+  * @{
+  */
+#define PWR_VDDIO_RANGE_3V3            (0U)
+#define PWR_VDDIO_RANGE_1V8            (1U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_Mode PWR Extended PVM Interrupt and Event Mode
+  * @{
+  */
+#define PWR_PVM_MODE_NORMAL               (0x00U)                              /*!< Basic Mode is used                                                 */
+#define PWR_PVM_MODE_IT_RISING            (0x05U)                              /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define PWR_PVM_MODE_IT_FALLING           (0x06U)                              /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define PWR_PVM_MODE_IT_RISING_FALLING    (0x07U)                              /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING         (0x09U)                              /*!< Event Mode with Rising edge trigger detection                      */
+#define PWR_PVM_MODE_EVENT_FALLING        (0x0AU)                              /*!< Event Mode with Falling edge trigger detection                     */
+#define PWR_PVM_MODE_EVENT_RISING_FALLING (0x0BU)                              /*!< Event Mode with Rising/Falling edge trigger detection              */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the USBVM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Disable the USBVM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Enable the USBVM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Disable the USBVM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Enable the USBVM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Disable the USBVM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Enable the USBVM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Disable the USBVM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Enable the USBVM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                    \
+  {                                                     \
+    __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Disable the USBVM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                     \
+  {                                                      \
+    __HAL_PWR_USBVM_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_USBVM_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Generate a Software Interrupt on USBVM EXTI Line.
+  * @retval None
+  */
+#define __HAL_PWR_USBVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Check whether the specified USBVM EXTI flag is set or not.
+  * @retval EXTI USBVM Line Status.
+  */
+#define __HAL_PWR_USBVM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Clear the USBVM interrupt Rising flag.
+  * @retval None.
+  */
+#define __HAL_PWR_USBVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Clear the USBVM interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_USBVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDUSB)
+
+/**
+  * @brief  Enable the IO2VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Disable the IO2VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Enable the IO2VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Disable the IO2VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Enable the IO2VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Disable the IO2VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Enable the IO2VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Disable the IO2VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Enable the IO2VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                      \
+  {                                                       \
+    __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Disable the IO2VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                       \
+  {                                                        \
+    __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Generate a Software Interrupt on IO2VM EXTI Line.
+  * @retval None
+  */
+#define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Check whether the specified IO2VM EXTI flag is set or not.
+  * @retval EXTI IO2VM Line Status.
+  */
+#define __HAL_PWR_IO2VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Clear the IO2VM interrupt Rising flag.
+  * @retval None.
+  */
+#define __HAL_PWR_IO2VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Clear the IO2VM interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_IO2VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO2)
+
+/**
+  * @brief  Enable the IO3VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Disable the IO3VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Enable the IO3VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Disable the IO3VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Enable the IO3VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Disable the IO3VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Enable the IO3VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Disable the IO3VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Enable the IO3VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                      \
+  {                                                       \
+    __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_IO3VM_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Disable the IO3VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                       \
+  {                                                        \
+    __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_IO3VM_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Generate a Software Interrupt on IO3VM EXTI Line.
+  * @retval None
+  */
+#define __HAL_PWR_IO3VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Check whether the specified IO3VM EXTI flag is set or not.
+  * @retval EXTI IO3VM Line Status.
+  */
+#define __HAL_PWR_IO3VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Clear the IO3VM interrupt Rising flag.
+  * @retval None.
+  */
+#define __HAL_PWR_IO3VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Clear the IO3VM interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_IO3VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO3)
+
+/**
+  * @brief  Enable the IO4VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Disable the IO4VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Enable the IO4VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Disable the IO4VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Enable the IO4VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Disable the IO4VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Enable the IO4VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Disable the IO4VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Enable the IO4VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                      \
+  {                                                       \
+    __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_IO4VM_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Disable the IO4VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                       \
+  {                                                        \
+    __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_IO4VM_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Generate a Software Interrupt on IO4VM EXTI Line.
+  * @retval None
+  */
+#define __HAL_PWR_IO4VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Check whether the specified IO4VM EXTI flag is set or not.
+  * @retval EXTI IO4VM Line Status.
+  */
+#define __HAL_PWR_IO4VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Clear the IO4VM interrupt Rising flag.
+  * @retval None.
+  */
+#define __HAL_PWR_IO4VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Clear the IO4VM interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_IO4VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO4)
+
+/**
+  * @brief  Enable the IO5VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Disable the IO5VM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Enable the IO5VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Disable the IO5VM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Enable the IO5VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Disable the IO5VM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Enable the IO5VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Disable the IO5VM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Enable the IO5VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                      \
+  {                                                       \
+    __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_IO5VM_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Disable the IO5VM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                       \
+  {                                                        \
+    __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_IO5VM_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Generate a Software Interrupt on IO5VM EXTI Line.
+  * @retval None
+  */
+#define __HAL_PWR_IO5VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Check whether the specified IO5VM EXTI flag is set or not.
+  * @retval EXTI IO5VM Line Status.
+  */
+#define __HAL_PWR_IO5VM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Clear the IO5VM interrupt Rising flag.
+  * @retval None.
+  */
+#define __HAL_PWR_IO5VM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Clear the IO5VM interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_IO5VM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDIO5)
+
+/**
+  * @brief  Enable the ADCVM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Disable the ADCVM Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Enable the ADCVM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Disable the ADCVM Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Enable the ADCVM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Disable the ADCVM Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Enable the ADCVM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Disable the ADCVM Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Enable the ADCVM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                    \
+  {                                                     \
+    __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_ADCVM_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Disable the ADCVM Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                     \
+  {                                                      \
+    __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_ADCVM_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Generate a Software Interrupt on ADCVM EXTI Line.
+  * @retval None
+  */
+#define __HAL_PWR_ADCVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Check whether the specified ADCVM EXTI flag is set or not.
+  * @retval EXTI ADCVM Line Status.
+  */
+#define __HAL_PWR_ADCVM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Clear the ADCVM interrupt Rising flag.
+  * @retval None.
+  */
+#define __HAL_PWR_ADCVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Clear the ADCVM interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_ADCVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVM_VDDA)
+
+/**
+  * @brief  Enable the VddCORE monitoring Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Disable the VddCORE monitoring Extended Interrupt Line.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Enable the VddCORE monitoring Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Disable the VddCORE monitoring Event Line.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Enable the VddCORE monitoring Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Disable the VddCORE monitoring Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Enable the VddCORE monitoring Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Disable the VddCORE monitoring Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Enable the VddCORE monitoring Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+  do                                                    \
+  {                                                     \
+    __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_EDGE();            \
+    __HAL_PWR_VCOREVM_EXTI_ENABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Disable the VddCORE monitoring Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+  do                                                     \
+  {                                                      \
+    __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_EDGE();            \
+    __HAL_PWR_VCOREVM_EXTI_DISABLE_FALLING_EDGE();           \
+  } while(0)
+
+/**
+  * @brief  Generate a Software Interrupt on VddCORE monitoring EXTI Line.
+  * @retval None
+  */
+#define __HAL_PWR_VCOREVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Check whether the specified VddCORE monitoring EXTI flag is set or not.
+  * @retval EXTI VddCORE monitoring Line Status.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_GET_FLAG() ((EXTI->RPR3 | EXTI->FPR3) & PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Clear the VddCORE monitoring interrupt Rising flag.
+  * @retval None.
+  */
+#define __HAL_PWR_VCOREVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_VCOREVM)
+
+/**
+  * @brief  Clear the VddCORE monitoring interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_VCOREVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_VCOREVM)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @{
+  */
+/* Power supply control functions */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
+uint32_t          HAL_PWREx_GetSupplyConfig(void);
+
+/* Power voltage scaling functions */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+uint32_t          HAL_PWREx_GetVoltageRange(void);
+void              HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
+uint32_t          HAL_PWREx_GetStopModeVoltageRange(void);
+
+
+/** @addtogroup PWREx_Exported_Functions_Group2 Wakeup Pins configuration functions
+  * @{
+  */
+/* Wakeup Pins control functions */
+void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams);
+/**
+  * @}
+  */
+
+
+/** @addtogroup PWREx_Exported_Functions_Group3 Memories Retention Functions
+  * @{
+  */
+void HAL_PWREx_EnableBkupRAMRetention(void);
+void HAL_PWREx_DisableBkupRAMRetention(void);
+void HAL_PWREx_EnableTCMRetention(void);
+void HAL_PWREx_DisableTCMRetention(void);
+void HAL_PWREx_EnableTCMFLXRetention(void);
+void HAL_PWREx_DisableTCMFLXRetention(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group4 Low Power Control Functions
+  * @{
+  */
+void     HAL_PWREx_SetPulseLow(uint32_t Pulselowtime);
+uint32_t HAL_PWREx_GetPulseLow(void);
+void     HAL_PWREx_EnableSMPSPWM(void);
+void     HAL_PWREx_DisableSMPSPWM(void);
+void     HAL_PWREx_EnablePullDownOutput(void);
+void     HAL_PWREx_DisablePullDownOutput(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group5 Power Monitoring functions
+  * @{
+  */
+/* Power VBAT/Temperature monitoring functions */
+void              HAL_PWREx_EnableMonitoring(void);
+void              HAL_PWREx_DisableMonitoring(void);
+uint32_t          HAL_PWREx_GetTemperatureLevel(void);
+uint32_t          HAL_PWREx_GetVBATLevel(void);
+void              HAL_PWREx_EnableVDDCOREMonitoring(void);
+void              HAL_PWREx_DisableVDDCOREMonitoring(void);
+void              HAL_PWREx_ConfigVDDCOREVM(const PWR_VddCOREVMTypeDef *pConfigVddCOREVM);
+uint32_t          HAL_PWREx_GetVDDCORELevel(void);
+void              HAL_PWREx_ConfigVddIORange(uint32_t VddIOPort, uint32_t VoltageRange);
+uint32_t          HAL_PWREx_GetVddIORange(uint32_t VddIOPort);
+void              HAL_PWREx_EnableVddIO4RangeSTBY(void);
+void              HAL_PWREx_DisableVddIO4RangeSTBY(void);
+void              HAL_PWREx_EnableVddIO5RangeSTBY(void);
+void              HAL_PWREx_DisableVddIO5RangeSTBY(void);
+void              HAL_PWREx_EnableVddUSB(void);
+void              HAL_PWREx_DisableVddUSB(void);
+void              HAL_PWREx_EnableVddIO2(void);
+void              HAL_PWREx_DisableVddIO2(void);
+void              HAL_PWREx_EnableVddIO3(void);
+void              HAL_PWREx_DisableVddIO3(void);
+void              HAL_PWREx_EnableVddIO4(void);
+void              HAL_PWREx_DisableVddIO4(void);
+void              HAL_PWREx_EnableVddIO5(void);
+void              HAL_PWREx_DisableVddIO5(void);
+void              HAL_PWREx_EnableVddA(void);
+void              HAL_PWREx_DisableVddA(void);
+void              HAL_PWREx_EnableVddUSBVMEN(void);
+void              HAL_PWREx_DisableVddUSBVMEN(void);
+void              HAL_PWREx_EnableVddIO2VMEN(void);
+void              HAL_PWREx_DisableVddIO2VMEN(void);
+void              HAL_PWREx_EnableVddIO3VMEN(void);
+void              HAL_PWREx_DisableVddIO3VMEN(void);
+void              HAL_PWREx_EnableVddIO4VMEN(void);
+void              HAL_PWREx_DisableVddIO4VMEN(void);
+void              HAL_PWREx_EnableVddIO5VMEN(void);
+void              HAL_PWREx_DisableVddIO5VMEN(void);
+void              HAL_PWREx_EnableVddAVMEN(void);
+void              HAL_PWREx_DisableVddAVMEN(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *pConfigPVM);
+void              HAL_PWREx_PVD_PVM_IRQHandler(void);
+void              HAL_PWREx_VDDCORE_Rising_Callback(void);
+void              HAL_PWREx_VDDCORE_Falling_Callback(void);
+void              HAL_PWREx_USBVM_Rising_Callback(void);
+void              HAL_PWREx_USBVM_Falling_Callback(void);
+void              HAL_PWREx_IO2VM_Rising_Callback(void);
+void              HAL_PWREx_IO2VM_Falling_Callback(void);
+void              HAL_PWREx_IO3VM_Rising_Callback(void);
+void              HAL_PWREx_IO3VM_Falling_Callback(void);
+void              HAL_PWREx_IO4VM_Rising_Callback(void);
+void              HAL_PWREx_IO4VM_Falling_Callback(void);
+void              HAL_PWREx_IO5VM_Rising_Callback(void);
+void              HAL_PWREx_IO5VM_Falling_Callback(void);
+void              HAL_PWREx_ADCVM_Rising_Callback(void);
+void              HAL_PWREx_ADCVM_Falling_Callback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+
+/** @defgroup PWREx_VDDCOREVM_EXTI PWR VddCORE monitoring  extended interrupts and event lines defines
+  * @{
+  */
+#define PWR_EXTI_LINE_VCOREVM          EXTI_IMR3_IM68                          /*!< VddCORE monitoring EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_EXTI PWR PVM extended interrupts and event lines defines
+  * @{
+  */
+#define PWR_EXTI_LINE_PVM_VDDIO2       EXTI_IMR3_IM69                          /*!< PVM VDDIO2 EXTI Line  */
+#define PWR_EXTI_LINE_PVM_VDDIO3       EXTI_IMR3_IM70                          /*!< PVM VDDIO3 EXTI Line  */
+#define PWR_EXTI_LINE_PVM_VDDIO4       EXTI_IMR3_IM71                          /*!< PVM VDDIO4 EXTI Line  */
+#define PWR_EXTI_LINE_PVM_VDDIO5       EXTI_IMR3_IM72                          /*!< PVM VDDIO5 EXTI Line  */
+#define PWR_EXTI_LINE_PVM_VDDUSB       EXTI_IMR3_IM73                          /*!< PVM VDD USB EXTI Line */
+#define PWR_EXTI_LINE_PVM_VDDA         EXTI_IMR3_IM74                          /*!< PVM VDD ADC EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_Type PWR Extended Voltage Monitoring Type
+  * @{
+  */
+#define PWR_VDDUSB_VM                  (0U)                                    /*!< Independent USB voltage monitor    */
+#define PWR_VDDIO2_VM                  (1U)                                    /*!< Independent VDDIO2 voltage monitor */
+#define PWR_VDDIO3_VM                  (2U)                                    /*!< Independent VDDIO3 voltage monitor */
+#define PWR_VDDIO4_VM                  (3U)                                    /*!< Independent VDDIO4 voltage monitor */
+#define PWR_VDDIO5_VM                  (4U)                                    /*!< Independent VDDIO5 voltage monitor */
+#define PWR_VDDA_VM                    (5U)                                    /*!< Independent VDDA voltage monitor   */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+/* Check PWR regulator configuration parameter */
+#define IS_PWR_SUPPLY(__SOURCE__) (((__SOURCE__) == PWR_SMPS_SUPPLY)             ||\
+                                   ((__SOURCE__) == PWR_EXTERNAL_SOURCE_SUPPLY))
+
+/* Check low power regulator parameter */
+#define IS_PWR_REGULATOR(__REGULATOR__) ((__REGULATOR__) == PWR_MAINREGULATOR_ON)
+
+/* Check voltage scale level parameter */
+#define IS_PWR_REGULATOR_VOLTAGE(__VOLTAGE__) (((__VOLTAGE__) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
+                                               ((__VOLTAGE__) == PWR_REGULATOR_VOLTAGE_SCALE1))
+
+/* Check PWR regulator configuration in STOP mode parameter */
+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(__VOLTAGE__) (((__VOLTAGE__) == PWR_REGULATOR_STOP_VOLTAGE_SCALE3)  ||\
+                                                         ((__VOLTAGE__) == PWR_REGULATOR_STOP_VOLTAGE_SCALE5))
+
+/* Check PWR pulse low time configuration parameter */
+#define IS_PWR_PULSE_LOW_TIME(__LOWTIME__) ((__LOWTIME__) <= 31U)
+
+/* Check VDDCORE voltage detector low-level parameter */
+#define IS_PWR_VDDCOREVM_LEVEL(__LEVEL__) (((__LEVEL__) == PWR_VDDCORE_THRESHOLD_VOS0) || \
+                                           ((__LEVEL__) == PWR_VDDCORE_THRESHOLD_VOS1))
+
+/* Check VddCORE VM mode check parameter */
+#define IS_PWR_VDDCOREVM_MODE(__MODE__)                     \
+  (((__MODE__) == PWR_VDDCOREVM_MODE_NORMAL)              ||\
+   ((__MODE__) == PWR_VDDCOREVM_MODE_IT_RISING)           ||\
+   ((__MODE__) == PWR_VDDCOREVM_MODE_IT_FALLING)          ||\
+   ((__MODE__) == PWR_VDDCOREVM_MODE_IT_RISING_FALLING)   ||\
+   ((__MODE__) == PWR_VDDCOREVM_MODE_EVENT_RISING)        ||\
+   ((__MODE__) == PWR_VDDCOREVM_MODE_EVENT_FALLING)       ||\
+   ((__MODE__) == PWR_VDDCOREVM_MODE_EVENT_RISING_FALLING))
+
+/* Check PVM type parameter */
+#define IS_PWR_PVM_TYPE(__TYPE__)  \
+  (((__TYPE__) == PWR_VDDUSB_VM) ||\
+   ((__TYPE__) == PWR_VDDIO2_VM) ||\
+   ((__TYPE__) == PWR_VDDIO3_VM) ||\
+   ((__TYPE__) == PWR_VDDIO4_VM) ||\
+   ((__TYPE__) == PWR_VDDIO5_VM) ||\
+   ((__TYPE__) == PWR_VDDA_VM))
+
+/* Check PVM mode check parameter */
+#define IS_PWR_PVM_MODE(__MODE__)                   \
+  (((__MODE__) == PWR_PVM_MODE_NORMAL)            ||\
+   ((__MODE__) == PWR_PVM_MODE_IT_RISING)         ||\
+   ((__MODE__) == PWR_PVM_MODE_IT_FALLING)        ||\
+   ((__MODE__) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
+   ((__MODE__) == PWR_PVM_MODE_EVENT_RISING)      ||\
+   ((__MODE__) == PWR_PVM_MODE_EVENT_FALLING)     ||\
+   ((__MODE__) == PWR_PVM_MODE_EVENT_RISING_FALLING))
+
+/* Check the VddIO parameter */
+#define IS_PWR_VDDIO(__VDDIO__)  (((__VDDIO__) == PWR_VDDIO)  || \
+                                  ((__VDDIO__) == PWR_VDDIO2) || \
+                                  ((__VDDIO__) == PWR_VDDIO3) || \
+                                  ((__VDDIO__) == PWR_VDDIO4) || \
+                                  ((__VDDIO__) == PWR_VDDIO5))
+
+/* Check the VddIO Range parameter */
+#define IS_PWR_VDDIO_RANGE(__RANGE__)  (((__RANGE__) == PWR_VDDIO_RANGE_3V3) || \
+                                        ((__RANGE__) == PWR_VDDIO_RANGE_1V8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32N6xx_HAL_PWR_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ramcfg.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ramcfg.h
new file mode 100644
index 000000000..9c5e5212c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_ramcfg.h
@@ -0,0 +1,396 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_ramcfg.h
+  * @author  MCD Application Team
+  * @brief   Header file of RAMCFG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RAMCFG_H
+#define STM32N6xx_HAL_RAMCFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RAMCFG
+  * @{
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Types RAMCFG Exported Types
+  * @brief    RAMCFG Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL RAMCFG State Enumeration Definition
+  */
+typedef enum
+{
+  HAL_RAMCFG_STATE_RESET             = 0x00U,  /*!< RAMCFG not yet initialized or disabled */
+  HAL_RAMCFG_STATE_READY             = 0x01U,  /*!< RAMCFG initialized and ready for use   */
+  HAL_RAMCFG_STATE_BUSY              = 0x02U,  /*!< RAMCFG process is ongoing              */
+  HAL_RAMCFG_STATE_ERROR             = 0x03U,  /*!< RAMCFG error state                     */
+} HAL_RAMCFG_StateTypeDef;
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL RAMCFG Callbacks IDs Enumeration Definition
+  */
+typedef enum
+{
+  HAL_RAMCFG_MSPINIT_CB_ID           = 0x00U,  /*!< RAMCFG MSP Init Callback ID            */
+  HAL_RAMCFG_MSPDEINIT_CB_ID         = 0x01U,  /*!< RAMCFG MSP DeInit Callback ID          */
+  HAL_RAMCFG_SE_DETECT_CB_ID         = 0x02U,  /*!< RAMCFG Single Error Detect Callback ID */
+  HAL_RAMCFG_DE_DETECT_CB_ID         = 0x03U,  /*!< RAMCFG Double Error Detect Callback ID */
+  HAL_RAMCFG_ALL_CB_ID               = 0x04U,  /*!< RAMCFG All callback ID                 */
+} HAL_RAMCFG_CallbackIDTypeDef;
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+/**
+  * @brief  RAMCFG Handle Structure Definition
+  */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+typedef struct __RAMCFG_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_RAMCFG_REGISTER_CALLBACKS) */
+{
+  RAMCFG_TypeDef                  *Instance;                                 /*!< RAMCFG Register Base Address        */
+  __IO HAL_RAMCFG_StateTypeDef    State;                                     /*!< RAMCFG State                        */
+  __IO uint32_t                   ErrorCode;                                 /*!< RAMCFG Error Code                   */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);          /*!< RAMCFG MSP Init Callback            */
+  void (* MspDeInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);        /*!< RAMCFG MSP DeInit Callback          */
+  void (* DetectSingleErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);/*!< RAMCFG Single Error Detect Callback */
+  void (* DetectDoubleErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg);/*!< RAMCFG Double Error Detect Callback */
+#endif  /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+} RAMCFG_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Constants RAMCFG Exported Constants
+  * @brief    RAMCFG Exported Constants
+  * @{
+  */
+
+/** @defgroup RAMCFG_Error_Codes RAMCFG Error Codes
+  * @brief    RAMCFG Error Codes
+  * @{
+  */
+#define HAL_RAMCFG_ERROR_NONE             0x00000000U  /*!< RAMCFG No Error         */
+#define HAL_RAMCFG_ERROR_TIMEOUT          0x00000001U  /*!< RAMCFG Timeout Error    */
+#define HAL_RAMCFG_ERROR_BUSY             0x00000002U  /*!< RAMCFG Busy Error       */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+#define HAL_RAMCFG_ERROR_INVALID_CALLBACK 0x00000003U  /*!< Invalid Callback error  */
+#endif  /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup RAMCFG_Interrupt RAMCFG Interrupts
+  * @brief    RAMCFG Interrupts
+  * @{
+  */
+#define RAMCFG_IT_SINGLEERR   RAMCFG_IER_SEIE           /*!< RAMCFG Single Error Interrupt                   */
+#define RAMCFG_IT_DOUBLEERR   RAMCFG_IER_DEIE           /*!< RAMCFG Double Error Interrupt                   */
+#define RAMCFG_IT_ALL \
+  (RAMCFG_IER_SEIE | RAMCFG_IER_DEIE)                     /*!<RAMCFG All RAMCFG interrupt                      */
+/**
+  * @}
+  */
+
+/** @defgroup RAMCFG_FLAG RAMCFG Monitor Flags
+  * @brief    RAMCFG Monitor Flags
+  * @{
+  */
+#define RAMCFG_FLAG_SINGLEERR   RAMCFG_ISR_SEDC            /*!< RAMCFG Single Error Detected and Corrected Flag */
+#define RAMCFG_FLAG_DOUBLEERR   RAMCFG_ISR_DED             /*!< RAMCFG Double Error Detected Flag               */
+#define RAMCFG_FLAG_SRAMBUSY    RAMCFG_ISR_SRAMBUSY        /*!< RAMCFG SRAM busy Flag                           */
+#define RAMCFG_FLAGS_ALL \
+  (RAMCFG_ISR_SEDC | RAMCFG_ISR_DED  | RAMCFG_ISR_SRAMBUSY)  /*!< RAMCFG All Flags                                */
+/**
+  * @}
+  */
+
+/** @defgroup RAMCFG_Keys RAMCFG Keys
+  * @brief    RAMCFG Keys
+  * @{
+  */
+#define RAMCFG_ERASE_KEY1  (0xCAU) /*!< RAMCFG launch Erase Key 1 */
+#define RAMCFG_ERASE_KEY2  (0x53U) /*!< RAMCFG launch Erase Key 2 */
+
+#define RAMCFG_ECC_KEY1    (0xAEU) /*!< RAMCFG launch ECC Key 1 */
+#define RAMCFG_ECC_KEY2    (0x75U) /*!< RAMCFG launch ECC Key 2 */
+/**
+  * @}
+  */
+/** @defgroup RAMCFG_AXISRAM_PowerDown RAMCFG SRAM Power Down
+  * @{
+  */
+#define RAMCFG_AXISRAM_POWERDOWN       RAMCFG_CR_SRAMSD                         /*!< AXISRAM power down */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Macros RAMCFG Exported Macros
+  * @brief    RAMCFG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified RAMCFG interrupts.
+  * @param  __HANDLE__   : Specifies RAMCFG handle.
+  * @param  __INTERRUPT__: Specifies the RAMCFG interrupt sources to be enabled.
+  *         This parameter can be one of the following values:
+  *           @arg RAMCFG_IT_SINGLEERR    : Single Error Interrupt Mask.
+  *           @arg RAMCFG_IT_DOUBLEERR    : Double Error Interrupt Mask.
+  *           @arg RAMCFG_IT_NMIERR       : Double Error Interrupt redirection to NMI Mask.
+  *           @arg RAMCFG_IT_ALL          : All Interrupt Mask.
+  * @retval None
+  */
+#define __HAL_RAMCFG_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+  ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified RAMCFG interrupts.
+  * @note   This macros is used only to disable RAMCFG_IT_SINGLEERR and RAMCFG_IT_DOUBLEERR
+  *         interrupts. RAMCFG_IT_NMIERR interrupt can only be disabled by global  peripheral reset or system reset.
+  * @param  __HANDLE__   : Specifies RAMCFG handle.
+  * @param  __INTERRUPT__: Specifies the RAMCFG interrupt sources to be disabled.
+  *         This parameter can be one of the following values:
+  *           @arg RAMCFG_IT_SINGLEERR    : Single Error Interrupt Mask.
+  *           @arg RAMCFG_IT_DOUBLEERR    : Double Error Interrupt Mask.
+  * @retval None
+  */
+#define __HAL_RAMCFG_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+  ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RAMCFG interrupt source is enabled or not.
+  * @param  __HANDLE__    : Specifies the RAMCFG Handle.
+  * @param  __INTERRUPT__ : Specifies the RAMCFG interrupt source to check.
+  *          This parameter can be one of the following values:
+  *           @arg RAMCFG_IT_SINGLEERR    : Single Error Interrupt Mask.
+  *           @arg RAMCFG_IT_DOUBLEERR    : Double Error Interrupt Mask.
+  *           @arg RAMCFG_IT_NMIERR       : Double Error Interrupt Redirection to NMI Mask.
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RAMCFG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+  ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
+
+/**
+  * @brief  Get the RAMCFG pending flags.
+  * @param  __HANDLE__   : Specifies RAMCFG handle.
+  * @param  __FLAG__     : Specifies the flag to be checked.
+  *         This parameter can be one of the following values:
+  *            @arg RAMCFG_FLAG_SINGLEERR  : Single Error Detected and Corrected Flag.
+  *            @arg RAMCFG_FLAG_DOUBLEERR  : Double Error Detected Flag.
+  *            @arg RAMCFG_FLAG_SRAMBUSY   : SRAM Busy Flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_RAMCFG_GET_FLAG(__HANDLE__, __FLAG__) \
+  (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the RAMCFG pending flags.
+  * @param  __HANDLE__   : Specifies RAMCFG handle.
+  * @param  __FLAG__     : Specifies the flag to be cleared.
+  *          This parameter can be any combination of the following values:
+  *            @arg RAMCFG_FLAG_SINGLEERR  : Single Error Detected and Corrected Flag.
+  *            @arg RAMCFG_FLAG_DOUBLEERR  : Double Error Detected Flag.
+  * @retval None.
+  */
+#define __HAL_RAMCFG_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+  ((__HANDLE__)->Instance->ICR |= (__FLAG__))
+
+/** @brief  Reset the RAMCFG handle state.
+  * @param  __HANDLE__    : Specifies the RAMCFG Handle.
+  * @retval None.
+  */
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+#define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) \
+  do{\
+    (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \
+    (__HANDLE__)->MspInitCallback   = NULL;       \
+    (__HANDLE__)->MspDeInitCallback = NULL;       \
+  }while(0)
+#else
+#define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) \
+  do{\
+    (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \
+  }while(0)
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Exported_Functions RAMCFG Exported Functions
+  * @brief    RAMCFG Exported Functions
+  * @{
+  */
+
+/** @defgroup RAMCFG_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @brief    Initialization and De-Initialization Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg);
+HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg);
+void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg);
+void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg);
+/**
+  * @}
+  */
+
+/** @defgroup RAMCFG_Exported_Functions_Group2 ECC Operation Functions
+  * @brief    ECC Operation Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg);
+HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg);
+HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications);
+HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications);
+uint32_t HAL_RAMCFG_IsECCSingleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg);
+uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg);
+uint32_t HAL_RAMCFG_GetSingleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg);
+uint32_t HAL_RAMCFG_GetDoubleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg);
+/**
+  * @}
+  */
+
+/** @defgroup RAMCFG_Exported_Functions_Group5 Erase Operation Functions
+  * @brief    Erase Operation Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg);
+/**
+  * @}
+  */
+
+/** @defgroup RAMCFG_Exported_Functions_Group6 Handle Interrupt and Callbacks Functions
+  * @brief    Handle Interrupt and Callbacks Functions
+  * @{
+  */
+void              HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg);
+void              HAL_RAMCFG_DetectSingleErrorCallback(RAMCFG_HandleTypeDef *hramcfg);
+void              HAL_RAMCFG_DetectDoubleErrorCallback(RAMCFG_HandleTypeDef *hramcfg);
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg,
+                                              HAL_RAMCFG_CallbackIDTypeDef CallbackID,
+                                              void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg));
+HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup RAMCFG_Exported_Functions_Group7 State and Error Functions
+  * @brief    State and Error Functions
+  * @{
+  */
+uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg);
+HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg);
+/**
+  * @}
+  */
+
+
+/** @defgroup RAMCFG_Exported_Functions_Group9 AXISRAM Powerdown Functions
+  * @brief    AXISRAM Powerdown Functions
+  * @{
+  */
+void HAL_RAMCFG_EnableAXISRAM(const RAMCFG_HandleTypeDef *hramcfg);
+void HAL_RAMCFG_DisableAXISRAM(const RAMCFG_HandleTypeDef *hramcfg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private Constants ---------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Private_Constants RAMCFG Private Defines and Constants
+  * @brief    RAMCFG Private Defines and Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Private_Macros RAMCFG Private Macros
+  * @brief    RAMCFG Private Macros
+  * @{
+  */
+#define IS_RAMCFG_INTERRUPT(INTERRUPT) \
+  (((INTERRUPT) != 0U) && (((INTERRUPT) & ~(RAMCFG_IT_SINGLEERR | RAMCFG_IT_DOUBLEERR)) == 0U))
+
+
+/**
+  * @}
+  */
+
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RAMCFG_Private_Functions RAMCFG Private Functions
+  * @brief    RAMCFG Private Functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_RAMCFG_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rcc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rcc.h
new file mode 100644
index 000000000..fa2a51a9c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rcc.h
@@ -0,0 +1,4662 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RCC_H
+#define STM32N6xx_HAL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+#include "stm32n6xx_ll_bus.h"
+#include "stm32n6xx_ll_rcc.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  *         (allow to configure the PLL in integer and fractional modes)
+  *         Only PLLState field is applicable when its value is different from RCC_PLL_ON
+  */
+typedef struct
+{
+  uint32_t PLLState;            /*!< The new state of the PLL.
+                                     This parameter can be a value of @ref RCC_PLL_Config            */
+
+  uint32_t PLLSource;           /*!< PLL entry clock source.
+                                     This parameter must be a value of @ref RCC_PLL_Clock_Source     */
+
+  uint32_t PLLM;                /*!< Division factor M for PLL VCO input clock.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLLFractional;       /*!< Fractional part of he VCO mulliplication factor.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFFFF */
+
+  uint32_t PLLN;                /*!< Multiplication factor N for PLL VCO output clock.
+                                     In integer mode, this parameter must be a number between Min_Data = 10 and Max_Data = 2500.
+                                     In fractional mode, this parameter must be a number between Min_Data = 20 and Max_Data = 500.*/
+
+  uint32_t PLLP1;               /*!< Division factor P1 for system clock.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 7     */
+
+  uint32_t PLLP2;               /*!< Division factor P2 for system clock.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 7     */
+
+} RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) and PLLs configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSIDiv;               /*!< The division factor of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Div                           */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0 and Max_Data = 127     */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+  uint32_t MSIState;             /*!< The new state of the MSI.
+                                      This parameter can be a value of @ref RCC_MSI_Config */
+
+  uint32_t MSIFrequency;         /*!< The MSI frequency selection.
+                                      This parameter can be a value of @ref RCC_MSI_Frequency */
+
+  uint32_t MSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0 and Max_Data = 31      */
+
+  RCC_PLLInitTypeDef PLL1;       /*!< PLL1 structure parameters                                                   */
+
+  RCC_PLLInitTypeDef PLL2;       /*!< PLL2 structure parameters                                                   */
+
+  RCC_PLLInitTypeDef PLL3;       /*!< PLL3 structure parameters                                                   */
+
+  RCC_PLLInitTypeDef PLL4;       /*!< PLL4 structure parameters                                                   */
+
+} RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC extended interconnection structure definition
+  */
+typedef struct
+{
+  uint32_t  ClockSelection;        /*!< Specifies ICx clock source.
+                                        This parameter can be a value of @ref RCC_IC_Clock_Source */
+
+  uint32_t  ClockDivider;          /*!< Specifies ICx clock divider.
+                                        This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
+} RCC_ICInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_Clock_Type                           */
+
+  uint32_t CPUCLKSource;          /*!< The clock source used as CPU clock (CPUCLK).
+                                       This parameter can be a value of @ref RCC_CPU_Clock_Source                     */
+
+  uint32_t SYSCLKSource;          /*!< The clock source used as system bus clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_System_Bus_Clock_Source              */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock divider for HCLK.
+                                       This clock is derived from the system clock divided by the system clock divider.
+                                       This parameter can be a value of @ref RCC_HCLK_Clock_Source                    */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock divider for PCLK1.
+                                       This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_Clock_Source                    */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock divider for PCLK2.
+                                       This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB2_Clock_Source                    */
+
+  uint32_t APB4CLKDivider;        /*!< The APB4 clock divider for PCLK4.
+                                       This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB4_Clock_Source                    */
+
+  uint32_t APB5CLKDivider;        /*!< The APB5 clock divider for PCLK5.
+                                       This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB5_Clock_Source                    */
+
+  RCC_ICInitTypeDef IC1Selection; /*!< IC1 parameters.
+                                       This parameter shall be used when IC1 is selected as CPU clock source (sysa_ck)         */
+
+  RCC_ICInitTypeDef IC2Selection; /*!< IC2 parameters.
+                                       This parameter shall be used when IC2 is selected as system bus clock source (sysb_ck)  */
+
+  RCC_ICInitTypeDef IC6Selection; /*!< IC6 parameters.
+                                       This parameter shall be used when IC6 is selected as system bus clock source (sysc_ck)  */
+
+  RCC_ICInitTypeDef IC11Selection; /*!< IC11 parameters.
+                                       This parameter shall be used when IC11 is selected as system bus clock source (sysd_ck) */
+} RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type  Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE        0x00U  /*!< Oscillator configuration unchanged */
+#define RCC_OSCILLATORTYPE_HSE         0x01U  /*!< HSE selected */
+#define RCC_OSCILLATORTYPE_HSI         0x02U  /*!< HSI selected */
+#define RCC_OSCILLATORTYPE_LSE         0x04U  /*!< LSE selected */
+#define RCC_OSCILLATORTYPE_LSI         0x08U  /*!< LSI selected */
+#define RCC_OSCILLATORTYPE_MSI         0x10U  /*!< MSI selected */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config  HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                    0U                                                       /*!< HSE clock deactivation */
+#define RCC_HSE_ON                     RCC_CR_HSEON                                             /*!< HSE clock activation */
+#define RCC_HSE_BYPASS                 (RCC_HSECFGR_HSEBYP | RCC_CR_HSEON)                      /*!< HSE bypass analog clock activation */
+#define RCC_HSE_BYPASS_DIGITAL         (RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass digital clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config  LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    0U                                                       /*!< LSE clock deactivation */
+#define RCC_LSE_ON                     RCC_CR_LSEON                                             /*!< LSE clock activation */
+#define RCC_LSE_BYPASS                 (RCC_LSECFGR_LSEBYP | RCC_CR_LSEON)                      /*!< LSE bypass analog clock activation */
+#define RCC_LSE_BYPASS_DIGITAL         (RCC_LSECFGR_LSEEXT | RCC_LSECFGR_LSEBYP | RCC_CR_LSEON) /*!< LSE bypass digital clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config  HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                    0U                   /*!< HSI clock deactivation */
+#define RCC_HSI_ON                     RCC_CR_HSION         /*!< HSI clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Div HSI Clock Divider
+  * @{
+  */
+#define RCC_HSI_DIV1                   LL_RCC_HSI_DIV_1  /*!< HSI clock is not divided */
+#define RCC_HSI_DIV2                   LL_RCC_HSI_DIV_2  /*!< HSI clock is divided by 2 */
+#define RCC_HSI_DIV4                   LL_RCC_HSI_DIV_4  /*!< HSI clock is divided by 4 */
+#define RCC_HSI_DIV8                   LL_RCC_HSI_DIV_8  /*!< HSI clock is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Calibration_Default  HSI Calibration default
+  * @{
+  */
+#define RCC_HSICALIBRATION_DEFAULT     0U                  /*!< Default HSI calibration trimming value */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config  LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    0U                  /*!< LSI clock deactivation */
+#define RCC_LSI_ON                     RCC_CR_LSION        /*!< LSI clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MSI_Config  MSI Config
+  * @{
+  */
+#define RCC_MSI_OFF                    0U                  /*!< MSI clock deactivation */
+#define RCC_MSI_ON                     RCC_CR_MSION        /*!< MSI clock activation */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MSI_Frequency  MSI Frequency
+  * @{
+  */
+#define RCC_MSI_FREQ_4MHZ              LL_RCC_MSI_FREQ_4MHZ  /*!< MSI 4MHz selection */
+#define RCC_MSI_FREQ_16MHZ             LL_RCC_MSI_FREQ_16MHZ /*!< MSI 16MHz selection */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MSI_Calibration_Default  MSI Calibration default
+  * @{
+  */
+#define RCC_MSICALIBRATION_DEFAULT     0U                  /*!< Default MSI calibration trimming value */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config  PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   0U                  /*!< PLL configuration unchanged */
+#define RCC_PLL_OFF                    1U                  /*!< PLL deactivation */
+#define RCC_PLL_ON                     2U                  /*!< PLL activation */
+#define RCC_PLL_BYPASS                 3U                  /*!< PLL activation in bypass mode with FREF set as source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source  PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI              LL_RCC_PLLSOURCE_HSI      /*!< HSI clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_MSI              LL_RCC_PLLSOURCE_MSI      /*!< MSI clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSE              LL_RCC_PLLSOURCE_HSE      /*!< HSE clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_PIN              LL_RCC_PLLSOURCE_I2S_CKIN /*!< External clock I2S_CKIN selected as PLL entry clock source  */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Clock_Type  Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_CPUCLK           0x01U         /*!< CPU clock to configure */
+#define RCC_CLOCKTYPE_SYSCLK           0x02U         /*!< System bus clock to configure for AXI */
+#define RCC_CLOCKTYPE_HCLK             0x04U         /*!< HCLK to configure for AHB */
+#define RCC_CLOCKTYPE_PCLK1            0x08U         /*!< PCLK1 to configure for APB1 */
+#define RCC_CLOCKTYPE_PCLK2            0x10U         /*!< PCLK2 to configure for APB2 */
+#define RCC_CLOCKTYPE_PCLK4            0x20U         /*!< PCLK4 to configure for APB4 */
+#define RCC_CLOCKTYPE_PCLK5            0x40U         /*!< PCLK5 to configure for APB5 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CPU_Clock_Source  CPU Clock Source
+  * @{
+  */
+#define RCC_CPUCLKSOURCE_HSI           LL_RCC_CPU_CLKSOURCE_HSI  /*!< HSI selection as CPU clock */
+#define RCC_CPUCLKSOURCE_MSI           LL_RCC_CPU_CLKSOURCE_MSI  /*!< MSI selection as CPU clock */
+#define RCC_CPUCLKSOURCE_HSE           LL_RCC_CPU_CLKSOURCE_HSE  /*!< HSE selection as CPU clock */
+#define RCC_CPUCLKSOURCE_IC1           LL_RCC_CPU_CLKSOURCE_IC1  /*!< IC1 selection as CPU clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CPU_Clock_Source_Status CPU Clock Source Status
+  * @{
+  */
+#define RCC_CPUCLKSOURCE_STATUS_HSI    LL_RCC_CPU_CLKSOURCE_STATUS_HSI  /*!< HSI used as CPU clock */
+#define RCC_CPUCLKSOURCE_STATUS_MSI    LL_RCC_CPU_CLKSOURCE_STATUS_MSI  /*!< MSI used as CPU clock */
+#define RCC_CPUCLKSOURCE_STATUS_HSE    LL_RCC_CPU_CLKSOURCE_STATUS_HSE  /*!< HSE used as CPU clock */
+#define RCC_CPUCLKSOURCE_STATUS_IC1    LL_RCC_CPU_CLKSOURCE_STATUS_IC1  /*!< IC1 used as CPU clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Bus_Clock_Source  System Bus Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_HSI           LL_RCC_SYS_CLKSOURCE_HSI  /*!< HSI selection as system bus clocks */
+#define RCC_SYSCLKSOURCE_MSI           LL_RCC_SYS_CLKSOURCE_MSI  /*!< MSI selection as system bus clocks */
+#define RCC_SYSCLKSOURCE_HSE           LL_RCC_SYS_CLKSOURCE_HSE  /*!< HSE selection as system bus clocks */
+#define RCC_SYSCLKSOURCE_IC2_IC6_IC11  LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11 /*!< IC2/IC6/IC11 selection as system bus clocks */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Bus_Clock_Source_Status System Bus Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_HSI          LL_RCC_SYS_CLKSOURCE_STATUS_HSI  /*!< HSI used as system bus clocks */
+#define RCC_SYSCLKSOURCE_STATUS_MSI          LL_RCC_SYS_CLKSOURCE_STATUS_MSI  /*!< MSI used as system bus clocks */
+#define RCC_SYSCLKSOURCE_STATUS_HSE          LL_RCC_SYS_CLKSOURCE_STATUS_HSE  /*!< HSE used as system bus clocks */
+#define RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11 LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11  /*!< IC2/IC6/IC11 used as system bus clocks */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HCLK_Clock_Source  HCLK Clock Source
+  * @{
+  */
+#define RCC_HCLK_DIV1        LL_RCC_AHB_DIV_1    /*!< HCLK not divided */
+#define RCC_HCLK_DIV2        LL_RCC_AHB_DIV_2    /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4        LL_RCC_AHB_DIV_4    /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8        LL_RCC_AHB_DIV_8    /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16       LL_RCC_AHB_DIV_16   /*!< HCLK divided by 16 */
+#define RCC_HCLK_DIV32       LL_RCC_AHB_DIV_32   /*!< HCLK divided by 32 */
+#define RCC_HCLK_DIV64       LL_RCC_AHB_DIV_64   /*!< HCLK divided by 64 */
+#define RCC_HCLK_DIV128      LL_RCC_AHB_DIV_128  /*!< HCLK divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Source  APB1 Clock Source
+  * @{
+  */
+#define RCC_APB1_DIV1        LL_RCC_APB1_DIV_1    /*!< APB1 not divided */
+#define RCC_APB1_DIV2        LL_RCC_APB1_DIV_2    /*!< APB1 divided by 2 */
+#define RCC_APB1_DIV4        LL_RCC_APB1_DIV_4    /*!< APB1 divided by 4 */
+#define RCC_APB1_DIV8        LL_RCC_APB1_DIV_8    /*!< APB1 divided by 8 */
+#define RCC_APB1_DIV16       LL_RCC_APB1_DIV_16   /*!< APB1 divided by 16 */
+#define RCC_APB1_DIV32       LL_RCC_APB1_DIV_32   /*!< APB1 divided by 32 */
+#define RCC_APB1_DIV64       LL_RCC_APB1_DIV_64   /*!< APB1 divided by 64 */
+#define RCC_APB1_DIV128      LL_RCC_APB1_DIV_128  /*!< APB1 divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Source  APB2 Clock Source
+  * @{
+  */
+#define RCC_APB2_DIV1        LL_RCC_APB2_DIV_1    /*!< APB2 not divided */
+#define RCC_APB2_DIV2        LL_RCC_APB2_DIV_2    /*!< APB2 divided by 2 */
+#define RCC_APB2_DIV4        LL_RCC_APB2_DIV_4    /*!< APB2 divided by 4 */
+#define RCC_APB2_DIV8        LL_RCC_APB2_DIV_8    /*!< APB2 divided by 8 */
+#define RCC_APB2_DIV16       LL_RCC_APB2_DIV_16   /*!< APB2 divided by 16 */
+#define RCC_APB2_DIV32       LL_RCC_APB2_DIV_32   /*!< APB2 divided by 32 */
+#define RCC_APB2_DIV64       LL_RCC_APB2_DIV_64   /*!< APB2 divided by 64 */
+#define RCC_APB2_DIV128      LL_RCC_APB2_DIV_128  /*!< APB2 divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Source  APB4 Clock Source
+  * @{
+  */
+#define RCC_APB4_DIV1        LL_RCC_APB4_DIV_1    /*!< APB4 not divided */
+#define RCC_APB4_DIV2        LL_RCC_APB4_DIV_2    /*!< APB4 divided by 2 */
+#define RCC_APB4_DIV4        LL_RCC_APB4_DIV_4    /*!< APB4 divided by 4 */
+#define RCC_APB4_DIV8        LL_RCC_APB4_DIV_8    /*!< APB4 divided by 8 */
+#define RCC_APB4_DIV16       LL_RCC_APB4_DIV_16   /*!< APB4 divided by 16 */
+#define RCC_APB4_DIV32       LL_RCC_APB4_DIV_32   /*!< APB4 divided by 32 */
+#define RCC_APB4_DIV64       LL_RCC_APB4_DIV_64   /*!< APB4 divided by 64 */
+#define RCC_APB4_DIV128      LL_RCC_APB4_DIV_128  /*!< APB4 divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB5_Clock_Source  APB5 Clock Source
+  * @{
+  */
+#define RCC_APB5_DIV1        LL_RCC_APB5_DIV_1    /*!< APB5 not divided */
+#define RCC_APB5_DIV2        LL_RCC_APB5_DIV_2    /*!< APB5 divided by 2 */
+#define RCC_APB5_DIV4        LL_RCC_APB5_DIV_4    /*!< APB5 divided by 4 */
+#define RCC_APB5_DIV8        LL_RCC_APB5_DIV_8    /*!< APB5 divided by 8 */
+#define RCC_APB5_DIV16       LL_RCC_APB5_DIV_16   /*!< APB5 divided by 16 */
+#define RCC_APB5_DIV32       LL_RCC_APB5_DIV_32   /*!< APB5 divided by 32 */
+#define RCC_APB5_DIV64       LL_RCC_APB5_DIV_64   /*!< APB5 divided by 64 */
+#define RCC_APB5_DIV128      LL_RCC_APB5_DIV_128  /*!< APB5 divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_IC_Clock_Source  IC Clock Source
+  * @{
+  */
+#define RCC_ICCLKSOURCE_PLL1           LL_RCC_ICCLKSOURCE_PLL1 /*!< ICx clock source selection is PLL1 output */
+#define RCC_ICCLKSOURCE_PLL2           LL_RCC_ICCLKSOURCE_PLL2 /*!< ICx clock source selection is PLL2 output */
+#define RCC_ICCLKSOURCE_PLL3           LL_RCC_ICCLKSOURCE_PLL3 /*!< ICx clock source selection is PLL3 output */
+#define RCC_ICCLKSOURCE_PLL4           LL_RCC_ICCLKSOURCE_PLL4 /*!< ICx clock source selection is PLL4 output */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source  RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_DISABLE       0U                                                      /*!< No clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSE           RCC_CCIPR7_RTCSEL_0                                     /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI           RCC_CCIPR7_RTCSEL_1                                     /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV1      ((0x00U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 1 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV2      ((0x01U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 2 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV3      ((0x02U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 3 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV4      ((0x03U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 4 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV5      ((0x04U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 5 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV6      ((0x05U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 6 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV7      ((0x06U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 7 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV8      ((0x07U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 8 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV9      ((0x08U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 9 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV10     ((0x09U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 10 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV11     ((0x0AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 11 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV12     ((0x0BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 12 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV13     ((0x0CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 13 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV14     ((0x0DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 14 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV15     ((0x0EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 15 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV16     ((0x0FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 16 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV17     ((0x10U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 17 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV18     ((0x11U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 18 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV19     ((0x12U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 19 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV20     ((0x13U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 20 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV21     ((0x14U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 21 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV22     ((0x15U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 22 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV23     ((0x16U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 23 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV24     ((0x17U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 24 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV25     ((0x18U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 25 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV26     ((0x19U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 26 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV27     ((0x1AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 27 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV28     ((0x1BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 28 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV29     ((0x1CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 29 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV30     ((0x1DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 30 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV31     ((0x1EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 31 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32     ((0x1FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 32 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV33     ((0x20U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 33 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV34     ((0x21U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 34 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV35     ((0x22U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 35 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV36     ((0x23U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 36 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV37     ((0x24U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 37 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV38     ((0x25U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 38 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV39     ((0x26U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 39 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV40     ((0x27U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 40 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV41     ((0x28U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 41 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV42     ((0x29U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 42 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV43     ((0x2AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 43 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV44     ((0x2BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 44 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV45     ((0x2CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 45 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV46     ((0x2DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 46 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV47     ((0x2EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 47 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV48     ((0x2FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 48 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV49     ((0x30U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 49 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV50     ((0x31U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 50 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV51     ((0x32U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 51 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV52     ((0x33U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 52 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV53     ((0x34U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 53 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV54     ((0x35U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 54 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV55     ((0x36U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 55 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV56     ((0x37U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 56 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV57     ((0x38U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 57 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV58     ((0x39U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 58 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV59     ((0x3AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 59 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV60     ((0x3BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 60 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV61     ((0x3CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 61 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV62     ((0x3DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 62 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV63     ((0x3EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 63 used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV64     ((0x3FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL)  /*!< HSE oscillator clock divided by 64 used as RTC clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Index  MCOx Index
+  * @{
+  */
+#define RCC_MCO1                       0U    /*!< Microcontroller Clock Output 1 */
+#define RCC_MCO2                       1U    /*!< Microcontroller Clock Output 2 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source  MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI             LL_RCC_MCO1SOURCE_HSI     /*!< HSI clock selected as MCO1 source (reset) */
+#define RCC_MCO1SOURCE_LSE             LL_RCC_MCO1SOURCE_LSE     /*!< LSE clock selected as MCO1 source */
+#define RCC_MCO1SOURCE_MSI             LL_RCC_MCO1SOURCE_MSI     /*!< MSI clock selected as MCO1 source */
+#define RCC_MCO1SOURCE_LSI             LL_RCC_MCO1SOURCE_LSI     /*!< HSI clock selected as MCO1 source */
+#define RCC_MCO1SOURCE_HSE             LL_RCC_MCO1SOURCE_HSE     /*!< HSE clock selected as MCO1 source */
+#define RCC_MCO1SOURCE_IC5             LL_RCC_MCO1SOURCE_IC5     /*!< IC5 clock selected as MCO1 source */
+#define RCC_MCO1SOURCE_IC10            LL_RCC_MCO1SOURCE_IC10    /*!< IC10 clock selected as MCO1 source */
+#define RCC_MCO1SOURCE_SYSA            LL_RCC_MCO1SOURCE_SYSA    /*!< SYSA CPU clock selected as MCO1 source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO2_Clock_Source  MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_HSI             LL_RCC_MCO2SOURCE_HSI     /*!< HSI clock selected as MCO2 source (reset) */
+#define RCC_MCO2SOURCE_LSE             LL_RCC_MCO2SOURCE_LSE     /*!< LSE clock selected as MCO2 source */
+#define RCC_MCO2SOURCE_MSI             LL_RCC_MCO2SOURCE_MSI     /*!< MSI clock selected as MCO2 source */
+#define RCC_MCO2SOURCE_LSI             LL_RCC_MCO2SOURCE_LSI     /*!< LSI clock selected as MCO2 source */
+#define RCC_MCO2SOURCE_HSE             LL_RCC_MCO2SOURCE_HSE     /*!< HSE clock selected as MCO2 source */
+#define RCC_MCO2SOURCE_IC15            LL_RCC_MCO2SOURCE_IC15    /*!< IC15 clock selected as MCO2 source */
+#define RCC_MCO2SOURCE_IC20            LL_RCC_MCO2SOURCE_IC20    /*!< IC20 clock selected as MCO2 source */
+#define RCC_MCO2SOURCE_SYSB            LL_RCC_MCO2SOURCE_SYSB    /*!< SYSB bus clock selected as MCO2 source */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler  MCOx Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                   LL_RCC_MCO1_DIV_1   /*!< MCO divided by 1 */
+#define RCC_MCODIV_2                   LL_RCC_MCO1_DIV_2   /*!< MCO divided by 2 */
+#define RCC_MCODIV_3                   LL_RCC_MCO1_DIV_3   /*!< MCO divided by 3 */
+#define RCC_MCODIV_4                   LL_RCC_MCO1_DIV_4   /*!< MCO divided by 4 */
+#define RCC_MCODIV_5                   LL_RCC_MCO1_DIV_5   /*!< MCO divided by 5 */
+#define RCC_MCODIV_6                   LL_RCC_MCO1_DIV_6   /*!< MCO divided by 6 */
+#define RCC_MCODIV_7                   LL_RCC_MCO1_DIV_7   /*!< MCO divided by 7 */
+#define RCC_MCODIV_8                   LL_RCC_MCO1_DIV_8   /*!< MCO divided by 8 */
+#define RCC_MCODIV_9                   LL_RCC_MCO1_DIV_9   /*!< MCO divided by 9 */
+#define RCC_MCODIV_10                  LL_RCC_MCO1_DIV_10  /*!< MCO divided by 10 */
+#define RCC_MCODIV_11                  LL_RCC_MCO1_DIV_11  /*!< MCO divided by 11 */
+#define RCC_MCODIV_12                  LL_RCC_MCO1_DIV_12  /*!< MCO divided by 12 */
+#define RCC_MCODIV_13                  LL_RCC_MCO1_DIV_13  /*!< MCO divided by 13 */
+#define RCC_MCODIV_14                  LL_RCC_MCO1_DIV_14  /*!< MCO divided by 14 */
+#define RCC_MCODIV_15                  LL_RCC_MCO1_DIV_15  /*!< MCO divided by 15 */
+#define RCC_MCODIV_16                  LL_RCC_MCO1_DIV_16  /*!< MCO divided by 16 (reset) */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt  Interrupt
+  * @{
+  */
+#define RCC_IT_LSIRDY                  RCC_CIER_LSIRDYIE   /*!< LSI Ready Interrupt */
+#define RCC_IT_LSERDY                  RCC_CIER_LSERDYIE   /*!< LSE Ready Interrupt */
+#define RCC_IT_MSIRDY                  RCC_CIER_MSIRDYIE   /*!< MSI Ready Interrupt */
+#define RCC_IT_HSIRDY                  RCC_CIER_HSIRDYIE   /*!< HSI Ready Interrupt */
+#define RCC_IT_HSERDY                  RCC_CIER_HSERDYIE   /*!< HSE Ready Interrupt */
+#define RCC_IT_PLL1RDY                 RCC_CIER_PLL1RDYIE  /*!< PLL1 Ready Interrupt */
+#define RCC_IT_PLL2RDY                 RCC_CIER_PLL2RDYIE  /*!< PLL2 Ready Interrupt */
+#define RCC_IT_PLL3RDY                 RCC_CIER_PLL3RDYIE  /*!< PLL3 Ready Interrupt */
+#define RCC_IT_PLL4RDY                 RCC_CIER_PLL4RDYIE  /*!< PLL4 Ready Interrupt */
+#define RCC_IT_LSECSS                  RCC_CIER_LSECSSIE   /*!< LSE Clock Security System Interrupt */
+#define RCC_IT_HSECSS                  RCC_CIER_HSECSSIE   /*!< HSE Clock Security System Interrupt */
+#define RCC_IT_WKUP                    RCC_CIER_WKUPIE     /*!< CPU Wakeup Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag  Flag
+  *        Elements values convention: XXXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - XXX  : Register index
+  *                 - 001: SR register
+  *                 - 010: LSECFGR register
+  *                 - 011: HSECFGR register
+  *                 - 100: RSR register
+  * @{
+  */
+/* Flags in the SR register */
+#define RCC_FLAG_LSIRDY                ((RCC_SR_REG_INDEX << 5U) | RCC_SR_LSIRDY_Pos)   /*!< LSI ready flag */
+#define RCC_FLAG_LSERDY                ((RCC_SR_REG_INDEX << 5U) | RCC_SR_LSERDY_Pos)   /*!< LSE ready flag */
+#define RCC_FLAG_HSIRDY                ((RCC_SR_REG_INDEX << 5U) | RCC_SR_HSIRDY_Pos)   /*!< HSI ready flag */
+#define RCC_FLAG_MSIRDY                ((RCC_SR_REG_INDEX << 5U) | RCC_SR_MSIRDY_Pos)   /*!< MSI ready flag */
+#define RCC_FLAG_HSERDY                ((RCC_SR_REG_INDEX << 5U) | RCC_SR_HSERDY_Pos)   /*!< HSE ready flag */
+#define RCC_FLAG_PLL1RDY               ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL1RDY_Pos)  /*!< PLL1 ready flag */
+#define RCC_FLAG_PLL2RDY               ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL2RDY_Pos)  /*!< PLL2 ready flag */
+#define RCC_FLAG_PLL3RDY               ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL3RDY_Pos)  /*!< PLL3 ready flag */
+#define RCC_FLAG_PLL4RDY               ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL4RDY_Pos)  /*!< PLL4 ready flag */
+
+/* Flags in the LSECFGR register */
+#define RCC_FLAG_LSECSSD               ((RCC_LSECFGR_REG_INDEX << 5U) | RCC_LSECFGR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */
+
+/* Flags in the HSECFGR register */
+#define RCC_FLAG_HSECSSD               ((RCC_HSECFGR_REG_INDEX << 5U) | RCC_HSECFGR_HSECSSD_Pos) /*!< HSE Clock Security System failure detection flag */
+
+/* Flags in the RSR register */
+#define RCC_FLAG_LCKRST                ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LCKRSTF_Pos)  /*!< CPU Lockup reset flag */
+#define RCC_FLAG_BORRST                ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos)  /*!< BOR reset flag */
+#define RCC_FLAG_PINRST                ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos)  /*!< PIN reset flag */
+#define RCC_FLAG_PORRST                ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PORRSTF_Pos)  /*!< Power-on reset flag */
+#define RCC_FLAG_SFTRST                ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos)  /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST               ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST               ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST               ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW               LL_RCC_LSEDRIVE_LOW         /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW         LL_RCC_LSEDRIVE_MEDIUMLOW   /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH        LL_RCC_LSEDRIVE_MEDIUMHIGH  /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH              LL_RCC_LSEDRIVE_HIGH        /*!< LSE high drive capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_WakeUpClock  Stop WakeUp Clock
+  * @{
+  */
+#define RCC_STOP_WAKEUPCLOCK_HSI       LL_RCC_SYSWAKEUP_CLKSOURCE_HSI  /*!< HSI selected as wake up system clock from system Stop (default after reset) */
+#define RCC_STOP_WAKEUPCLOCK_MSI       LL_RCC_SYSWAKEUP_CLKSOURCE_MSI  /*!< MSI selected as wake up system clock from system Stop */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_items RCC items
+  * @brief RCC items to configure attributes on
+  * @{
+  */
+#define RCC_ITEM_LSI           (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_LSISEC)
+#define RCC_ITEM_LSE           (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_LSESEC)
+#define RCC_ITEM_MSI           (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_MSISEC)
+#define RCC_ITEM_HSI           (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_HSISEC)
+#define RCC_ITEM_HSE           (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_HSESEC)
+#define RCC_ITEM_PLL1          (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL1SEC)
+#define RCC_ITEM_PLL2          (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL2SEC)
+#define RCC_ITEM_PLL3          (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL3SEC)
+#define RCC_ITEM_PLL4          (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL4SEC)
+#define RCC_ITEM_IC1           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC1SEC)
+#define RCC_ITEM_IC2           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC2SEC)
+#define RCC_ITEM_IC3           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC3SEC)
+#define RCC_ITEM_IC4           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC4SEC)
+#define RCC_ITEM_IC5           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC5SEC)
+#define RCC_ITEM_IC6           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC6SEC)
+#define RCC_ITEM_IC7           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC7SEC)
+#define RCC_ITEM_IC8           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC8SEC)
+#define RCC_ITEM_IC9           (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC9SEC)
+#define RCC_ITEM_IC10          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC10SEC)
+#define RCC_ITEM_IC11          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC11SEC)
+#define RCC_ITEM_IC12          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC12SEC)
+#define RCC_ITEM_IC13          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC13SEC)
+#define RCC_ITEM_IC14          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC14SEC)
+#define RCC_ITEM_IC15          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC15SEC)
+#define RCC_ITEM_IC16          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC16SEC)
+#define RCC_ITEM_IC17          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC17SEC)
+#define RCC_ITEM_IC18          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC18SEC)
+#define RCC_ITEM_IC19          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC19SEC)
+#define RCC_ITEM_IC20          (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC20SEC)
+#define RCC_ITEM_MOD           (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_MODSEC)
+#define RCC_ITEM_SYS           (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_SYSSEC)
+#define RCC_ITEM_BUS           (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_BUSSEC)
+#define RCC_ITEM_PER           (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_PERSEC)
+#define RCC_ITEM_INT           (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_INTSEC)
+#define RCC_ITEM_RST           (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_RSTSEC)
+#define RCC_ITEM_ACLKN         (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_ACLKNSEC)
+#define RCC_ITEM_ACLKNC        (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_ACLKNCSEC)
+#define RCC_ITEM_AHBM          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHBMSEC)
+#define RCC_ITEM_AHB1          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB1SEC)
+#define RCC_ITEM_AHB2          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB2SEC)
+#define RCC_ITEM_AHB3          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB3SEC)
+#define RCC_ITEM_AHB4          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB4SEC)
+#define RCC_ITEM_AHB5          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB5SEC)
+#define RCC_ITEM_APB1          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB1SEC)
+#define RCC_ITEM_APB2          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB2SEC)
+#define RCC_ITEM_APB3          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB3SEC)
+#define RCC_ITEM_APB4          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB4SEC)
+#define RCC_ITEM_APB5          (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB5SEC)
+#define RCC_ITEM_NOC           (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_NOCSEC)
+#define RCC_ITEM_AXISRAM3      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM3PUB)
+#define RCC_ITEM_AXISRAM4      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM4PUB)
+#define RCC_ITEM_AXISRAM5      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM5PUB)
+#define RCC_ITEM_AXISRAM6      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM6PUB)
+#define RCC_ITEM_AHBSRAM1      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AHBSRAM1PUB)
+#define RCC_ITEM_AHBSRAM2      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AHBSRAM2PUB)
+#define RCC_ITEM_BKPSRAM       (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_BKPSRAMPUB)
+#define RCC_ITEM_AXISRAM1      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM1PUB)
+#define RCC_ITEM_AXISRAM2      (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM2PUB)
+#define RCC_ITEM_FLEXRAM       (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_FLEXRAMPUB)
+#if defined(CACHEAXI)
+#define RCC_ITEM_CACHEAXIRAM   (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_CACHEAXIRAMPUB)
+#else
+#define RCC_ITEM_CACHEAXIRAM   (RCC_ITEM_GROUP_MEM)
+#endif /* defined(CACHEAXI) */
+#define RCC_ITEM_VENCRAM       (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_VENCRAMPUB)
+
+#define RCC_ITEM_ALL           (RCC_ITEM_LSI | RCC_ITEM_LSE | RCC_ITEM_MSI | RCC_ITEM_HSI | RCC_ITEM_HSE | \
+                                RCC_ITEM_PLL1 | RCC_ITEM_PLL2 | RCC_ITEM_PLL3 | RCC_ITEM_PLL4 | RCC_ITEM_IC1 | \
+                                RCC_ITEM_IC2 | RCC_ITEM_IC3 | RCC_ITEM_IC4 | RCC_ITEM_IC5 | RCC_ITEM_IC6 | \
+                                RCC_ITEM_IC7 | RCC_ITEM_IC8 | RCC_ITEM_IC9 | RCC_ITEM_IC10 | RCC_ITEM_IC11 | \
+                                RCC_ITEM_IC12 | RCC_ITEM_IC13 | RCC_ITEM_IC14 | RCC_ITEM_IC15 | RCC_ITEM_IC16 | \
+                                RCC_ITEM_IC17 | RCC_ITEM_IC18 | RCC_ITEM_IC19 | RCC_ITEM_IC20 | RCC_ITEM_MOD | \
+                                RCC_ITEM_SYS | RCC_ITEM_BUS | RCC_ITEM_PER | RCC_ITEM_INT | RCC_ITEM_RST | \
+                                RCC_ITEM_ACLKN | RCC_ITEM_ACLKNC | RCC_ITEM_AHBM | RCC_ITEM_AHB1 | RCC_ITEM_AHB2 | \
+                                RCC_ITEM_AHB3 | RCC_ITEM_AHB4 | RCC_ITEM_AHB5 | RCC_ITEM_APB1 | RCC_ITEM_APB2 | \
+                                RCC_ITEM_APB3 | RCC_ITEM_APB4 | RCC_ITEM_APB5 | RCC_ITEM_NOC | RCC_ITEM_AXISRAM3 | \
+                                RCC_ITEM_AXISRAM4 | RCC_ITEM_AXISRAM5 | RCC_ITEM_AXISRAM6 | RCC_ITEM_AHBSRAM1 | \
+                                RCC_ITEM_AHBSRAM2 | RCC_ITEM_BKPSRAM | RCC_ITEM_AXISRAM1 | RCC_ITEM_AXISRAM2 | \
+                                RCC_ITEM_FLEXRAM | RCC_ITEM_CACHEAXIRAM | RCC_ITEM_VENCRAM)
+
+#define RCC_ITEM_ALL_CLK       (RCC_ITEM_LSI | RCC_ITEM_LSE | RCC_ITEM_MSI | RCC_ITEM_HSI | RCC_ITEM_HSE)
+#define RCC_ITEM_ALL_PLL       (RCC_ITEM_PLL1 | RCC_ITEM_PLL2 | RCC_ITEM_PLL3 | RCC_ITEM_PLL4)
+#define RCC_ITEM_ALL_ICx       (RCC_ITEM_IC1 | RCC_ITEM_IC2 | RCC_ITEM_IC3 | RCC_ITEM_IC4 | RCC_ITEM_IC5 | \
+                                RCC_ITEM_IC6 | RCC_ITEM_IC7 | RCC_ITEM_IC8 | RCC_ITEM_IC9 | RCC_ITEM_IC10 | \
+                                RCC_ITEM_IC11 | RCC_ITEM_IC12 | RCC_ITEM_IC13 | RCC_ITEM_IC14 | RCC_ITEM_IC15 | \
+                                RCC_ITEM_IC16 | RCC_ITEM_IC17 | RCC_ITEM_IC18 | RCC_ITEM_IC19 | RCC_ITEM_IC20)
+#define RCC_ITEM_ALL_SYSCFG    (RCC_ITEM_MOD | RCC_ITEM_SYS | RCC_ITEM_BUS | RCC_ITEM_PER | RCC_ITEM_INT | \
+                                RCC_ITEM_RST)
+#define RCC_ITEM_ALL_BUS       (RCC_ITEM_ACLKN | RCC_ITEM_ACLKNC | RCC_ITEM_AHBM | RCC_ITEM_AHB1 | RCC_ITEM_AHB2 | \
+                                RCC_ITEM_AHB3 | RCC_ITEM_AHB4 | RCC_ITEM_AHB5 | RCC_ITEM_APB1 | RCC_ITEM_APB2 | \
+                                RCC_ITEM_APB3 | RCC_ITEM_APB4 | RCC_ITEM_APB5 | RCC_ITEM_NOC)
+#define RCC_ITEM_ALL_MEM       (RCC_ITEM_AXISRAM3 | RCC_ITEM_AXISRAM4 | RCC_ITEM_AXISRAM5 | RCC_ITEM_AXISRAM6 | \
+                                RCC_ITEM_AHBSRAM1 | RCC_ITEM_AHBSRAM2 | RCC_ITEM_BKPSRAM | RCC_ITEM_AXISRAM1 | \
+                                RCC_ITEM_AXISRAM2 | RCC_ITEM_FLEXRAM | RCC_ITEM_CACHEAXIRAM | RCC_ITEM_VENCRAM)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_attributes RCC attributes
+  * @brief RCC privilege/non-privilege, secure/non-secure, public/non-public and lock attributes
+  * @note Configuration registers of a SECURED item are only accessible from secure state.
+  * @note Configuration registers of a PRIVILEGED item are only writable from privileged state.
+  * @note Configuration registers of a PUBLIC and SECURED item are visible from NS (and S) software.
+  * @note Setting an item to LOCKED, definitively locks the SEC and PRIV attribute setting for this item.
+  * @{
+  */
+#define RCC_ATTR_PRIV          (RCC_ATTR_PRIV_MASK | 0x01U)    /*!< attribute is privileged    */
+#define RCC_ATTR_NPRIV         RCC_ATTR_PRIV_MASK              /*!< attribute is unprivileged  */
+
+#define RCC_ATTR_SEC           (RCC_ATTR_SEC_MASK | 0x04U)     /*!< attribute is secure        */
+#define RCC_ATTR_NSEC          RCC_ATTR_SEC_MASK               /*!< attribute is non-secure    */
+
+#define RCC_ATTR_PUB           (RCC_ATTR_PUB_MASK | 0x10U)     /*!< attribute is public        */
+#define RCC_ATTR_NPUB          RCC_ATTR_PUB_MASK               /*!< attribute is not public    */
+
+#define RCC_ATTR_LOCK          (RCC_ATTR_LOCK_MASK | 0x40U)    /*!< attribute is locked        */
+#define RCC_ATTR_NLOCK         RCC_ATTR_LOCK_MASK              /*!< attribute is not locked    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_Embedded_Mem_Clock_Enable_Disable Embedded Memory Clock Enable Disable
+  * @brief  Enable or disable the Embedded Memory clock.
+  * @note   After reset, some embedded memory clocks are disabled
+  *         and the application software has to enable these memory clocks before using them.
+  * @{
+  */
+
+#define __HAL_RCC_AXISRAM1_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AXISRAM1)
+#define __HAL_RCC_AXISRAM1_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AXISRAM1)
+
+#define __HAL_RCC_AXISRAM2_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AXISRAM2)
+#define __HAL_RCC_AXISRAM2_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AXISRAM2)
+
+#define __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AXISRAM3)
+#define __HAL_RCC_AXISRAM3_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AXISRAM3)
+
+#define __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AXISRAM4)
+#define __HAL_RCC_AXISRAM4_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AXISRAM4)
+
+#define __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AXISRAM5)
+#define __HAL_RCC_AXISRAM5_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AXISRAM5)
+
+#define __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AXISRAM6)
+#define __HAL_RCC_AXISRAM6_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AXISRAM6)
+
+#define __HAL_RCC_AHBSRAM1_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AHBSRAM1)
+#define __HAL_RCC_AHBSRAM1_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AHBSRAM1)
+
+#define __HAL_RCC_AHBSRAM2_MEM_CLK_ENABLE()     LL_MEM_EnableClock(LL_MEM_AHBSRAM2)
+#define __HAL_RCC_AHBSRAM2_MEM_CLK_DISABLE()    LL_MEM_DisableClock(LL_MEM_AHBSRAM2)
+
+#define __HAL_RCC_BKPSRAM_MEM_CLK_ENABLE()      LL_MEM_EnableClock(LL_MEM_BKPSRAM)
+#define __HAL_RCC_BKPSRAM_MEM_CLK_DISABLE()     LL_MEM_DisableClock(LL_MEM_BKPSRAM)
+
+#define __HAL_RCC_FLEXRAM_MEM_CLK_ENABLE()      LL_MEM_EnableClock(LL_MEM_FLEXRAM)
+#define __HAL_RCC_FLEXRAM_MEM_CLK_DISABLE()     LL_MEM_DisableClock(LL_MEM_FLEXRAM)
+
+#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_ENABLE()  LL_MEM_EnableClock(LL_MEM_CACHEAXIRAM)
+#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_CACHEAXIRAM)
+
+#define __HAL_RCC_VENCRAM_MEM_CLK_ENABLE()      LL_MEM_EnableClock(LL_MEM_VENCRAM)
+#define __HAL_RCC_VENCRAM_MEM_CLK_DISABLE()     LL_MEM_DisableClock(LL_MEM_VENCRAM)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_ADC12_CLK_ENABLE()   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ADC12)
+#define __HAL_RCC_ADC12_CLK_DISABLE()  LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ADC12)
+
+#define __HAL_RCC_GPDMA1_CLK_ENABLE()  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPDMA1)
+#define __HAL_RCC_GPDMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_GPDMA1)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_ADF1_CLK_ENABLE()    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADF1)
+#define __HAL_RCC_ADF1_CLK_DISABLE()   LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADF1)
+
+#define __HAL_RCC_MDF1_CLK_ENABLE()    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_MDF1)
+#define __HAL_RCC_MDF1_CLK_DISABLE()   LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_MDF1)
+
+#define __HAL_RCC_RAMCFG_CLK_ENABLE()  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_RAMCFG)
+#define __HAL_RCC_RAMCFG_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_RAMCFG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @note   IAC, RIFSC and RISAF peripheral clocks are always security-protected and thus hidden
+  *         to the non-secure application.
+  * @{
+  */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_ENABLE()    LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_CRYP)
+#define __HAL_RCC_CRYP_CLK_DISABLE()   LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_CRYP)
+#endif /* CRYP */
+
+#define __HAL_RCC_HASH_CLK_ENABLE()    LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HASH)
+#define __HAL_RCC_HASH_CLK_DISABLE()   LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HASH)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_IAC_CLK_ENABLE()     LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IAC)
+#define __HAL_RCC_IAC_CLK_DISABLE()    LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IAC)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_PKA_CLK_ENABLE()     LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA)
+#define __HAL_RCC_PKA_CLK_DISABLE()    LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_RIFSC_CLK_ENABLE()   LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RIFSC)
+#define __HAL_RCC_RIFSC_CLK_DISABLE()  LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RIFSC)
+#endif /* CPU_IN_SECURE_STATE */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_RISAF_CLK_ENABLE()   LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RISAF)
+#define __HAL_RCC_RISAF_CLK_DISABLE()  LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RISAF)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()     LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG)
+#define __HAL_RCC_RNG_CLK_DISABLE()    LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG)
+
+#if defined(SAES)
+#define __HAL_RCC_SAES_CLK_ENABLE()    LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_SAES)
+#define __HAL_RCC_SAES_CLK_DISABLE()   LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_SAES)
+#endif /* SAES */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @note   PWR peripheral clock is always security-protected and thus hidden to the non-secure
+  *         application.
+  * @{
+  */
+
+#define __HAL_RCC_CRC_CLK_ENABLE()     LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_CRC)
+#define __HAL_RCC_CRC_CLK_DISABLE()    LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_CRC)
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA)
+#define __HAL_RCC_GPIOA_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOA)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB)
+#define __HAL_RCC_GPIOB_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOB)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC)
+#define __HAL_RCC_GPIOC_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOC)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOD)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOE)
+#define __HAL_RCC_GPIOE_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOE)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOF)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOF)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG)
+#define __HAL_RCC_GPIOG_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOG)
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH)
+#define __HAL_RCC_GPIOH_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOH)
+
+#define __HAL_RCC_GPION_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPION)
+#define __HAL_RCC_GPION_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPION)
+
+#define __HAL_RCC_GPIOO_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOO)
+#define __HAL_RCC_GPIOO_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOO)
+
+#define __HAL_RCC_GPIOP_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOP)
+#define __HAL_RCC_GPIOP_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOP)
+
+#define __HAL_RCC_GPIOQ_CLK_ENABLE()   LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOQ)
+#define __HAL_RCC_GPIOQ_CLK_DISABLE()  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOQ)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_PWR_CLK_ENABLE()     LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR)
+#define __HAL_RCC_PWR_CLK_DISABLE()    LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_PWR)
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB5_Peripheral_Clock_Enable_Disable AHB5 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB5 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DMA2D_CLK_ENABLE()   LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_DMA2D)
+#define __HAL_RCC_DMA2D_CLK_DISABLE()  LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_DMA2D)
+
+#if defined(ETH1)
+#define __HAL_RCC_ETH1_CLK_ENABLE()    LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1)
+#define __HAL_RCC_ETH1_CLK_DISABLE()   LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1)
+
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1MAC)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1MAC)
+
+#define __HAL_RCC_ETH1TX_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1TX)
+#define __HAL_RCC_ETH1TX_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1TX)
+
+#define __HAL_RCC_ETH1RX_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1RX)
+#define __HAL_RCC_ETH1RX_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1RX)
+#endif /* ETH1 */
+
+#define __HAL_RCC_FMC_CLK_ENABLE()     LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_FMC)
+#define __HAL_RCC_FMC_CLK_DISABLE()    LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_FMC)
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_CLK_ENABLE()   LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_GPU2D)
+#define __HAL_RCC_GPU2D_CLK_DISABLE()  LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_GPU2D)
+#endif /* GPU2D */
+
+#define __HAL_RCC_HPDMA1_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_HPDMA1)
+#define __HAL_RCC_HPDMA1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_HPDMA1)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_CLK_ENABLE()    LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_JPEG)
+#define __HAL_RCC_JPEG_CLK_DISABLE()   LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_JPEG)
+#endif /* JPEG */
+
+#define __HAL_RCC_XSPI1_CLK_ENABLE()   LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI1)
+#define __HAL_RCC_XSPI1_CLK_DISABLE()  LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI1)
+
+#define __HAL_RCC_XSPI2_CLK_ENABLE()   LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI2)
+#define __HAL_RCC_XSPI2_CLK_DISABLE()  LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI2)
+
+#define __HAL_RCC_XSPI3_CLK_ENABLE()   LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI3)
+#define __HAL_RCC_XSPI3_CLK_DISABLE()  LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI3)
+
+#define __HAL_RCC_XSPIM_CLK_ENABLE()   LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPIM)
+#define __HAL_RCC_XSPIM_CLK_DISABLE()  LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPIM)
+
+#define __HAL_RCC_MCE1_CLK_ENABLE()    LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE1)
+#define __HAL_RCC_MCE1_CLK_DISABLE()   LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE1)
+
+#define __HAL_RCC_MCE2_CLK_ENABLE()    LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE2)
+#define __HAL_RCC_MCE2_CLK_DISABLE()   LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE2)
+
+#define __HAL_RCC_MCE3_CLK_ENABLE()    LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE3)
+#define __HAL_RCC_MCE3_CLK_DISABLE()   LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE3)
+
+#define __HAL_RCC_MCE4_CLK_ENABLE()    LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE4)
+#define __HAL_RCC_MCE4_CLK_DISABLE()   LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE4)
+
+#define __HAL_RCC_CACHEAXI_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_CACHEAXI)
+#define __HAL_RCC_CACHEAXI_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_CACHEAXI)
+
+#define __HAL_RCC_NPU_CLK_ENABLE()     LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_NPU)
+#define __HAL_RCC_NPU_CLK_DISABLE()    LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_NPU)
+
+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()    LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()   LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_PSSI)
+
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_SDMMC1)
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_SDMMC1)
+
+#define __HAL_RCC_SDMMC2_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_SDMMC2)
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_SDMMC2)
+
+#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG1)
+#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTG1)
+
+#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1)
+#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1)
+
+#define __HAL_RCC_USB2_OTG_HS_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG2)
+#define __HAL_RCC_USB2_OTG_HS_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTG2)
+
+#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_ENABLE()  LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY2)
+#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTGPHY2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_FDCAN_CLK_ENABLE()  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_FDCAN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_FDCAN)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1)
+#define __HAL_RCC_I2C1_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2)
+#define __HAL_RCC_I2C2_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3)
+#define __HAL_RCC_I2C3_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3)
+
+#define __HAL_RCC_I3C1_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I3C1)
+#define __HAL_RCC_I3C1_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I3C1)
+
+#define __HAL_RCC_I3C2_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I3C2)
+#define __HAL_RCC_I3C2_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I3C2)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
+
+#define __HAL_RCC_MDIOS_CLK_ENABLE()  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_MDIOS)
+#define __HAL_RCC_MDIOS_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_MDIOS)
+
+#define __HAL_RCC_SPDIFRX1_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+#define __HAL_RCC_SPDIFRX1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)
+#define __HAL_RCC_SPI2_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI3)
+#define __HAL_RCC_SPI3_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI3)
+
+#define __HAL_RCC_TIM2_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2)
+#define __HAL_RCC_TIM2_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3)
+#define __HAL_RCC_TIM3_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM3)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM4)
+#define __HAL_RCC_TIM4_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM4)
+
+#define __HAL_RCC_TIM5_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5)
+#define __HAL_RCC_TIM5_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM5)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6)
+#define __HAL_RCC_TIM6_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM6)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7)
+#define __HAL_RCC_TIM7_CLK_DISABLE()  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM7)
+
+#define __HAL_RCC_TIM10_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM10)
+#define __HAL_RCC_TIM10_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM10)
+
+#define __HAL_RCC_TIM11_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM11)
+#define __HAL_RCC_TIM11_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM11)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM12)
+#define __HAL_RCC_TIM12_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM12)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM13)
+#define __HAL_RCC_TIM13_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM13)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM14)
+#define __HAL_RCC_TIM14_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM14)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2)
+#define __HAL_RCC_USART2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2)
+
+#define __HAL_RCC_USART3_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3)
+#define __HAL_RCC_USART3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART3)
+
+#define __HAL_RCC_UART4_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART4)
+#define __HAL_RCC_UART4_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART4)
+
+#define __HAL_RCC_UART5_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART5)
+#define __HAL_RCC_UART5_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART5)
+
+#define __HAL_RCC_UART7_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART7)
+#define __HAL_RCC_UART7_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART7)
+
+#define __HAL_RCC_UART8_CLK_ENABLE()  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART8)
+#define __HAL_RCC_UART8_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART8)
+
+#define __HAL_RCC_UCPD1_CLK_ENABLE()  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1)
+#define __HAL_RCC_UCPD1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1)
+
+#define __HAL_RCC_WWDG_CLK_ENABLE()   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1)
+#define __HAL_RCC_SAI1_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1)
+
+#define __HAL_RCC_SAI2_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI2)
+#define __HAL_RCC_SAI2_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI2)
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)
+#define __HAL_RCC_SPI1_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)
+
+#define __HAL_RCC_SPI4_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4)
+#define __HAL_RCC_SPI4_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI4)
+
+#define __HAL_RCC_SPI5_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5)
+#define __HAL_RCC_SPI5_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI5)
+
+#define __HAL_RCC_TIM1_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)
+#define __HAL_RCC_TIM1_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM8)
+#define __HAL_RCC_TIM8_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM8)
+
+#define __HAL_RCC_TIM9_CLK_ENABLE()    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM9)
+#define __HAL_RCC_TIM9_CLK_DISABLE()   LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM9)
+
+#define __HAL_RCC_TIM15_CLK_ENABLE()   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM15)
+#define __HAL_RCC_TIM15_CLK_DISABLE()  LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM15)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE()   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16)
+#define __HAL_RCC_TIM16_CLK_DISABLE()  LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE()   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17)
+#define __HAL_RCC_TIM17_CLK_DISABLE()  LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17)
+
+#define __HAL_RCC_TIM18_CLK_ENABLE()   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM18)
+#define __HAL_RCC_TIM18_CLK_DISABLE()  LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM18)
+
+#define __HAL_RCC_USART1_CLK_ENABLE()  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)
+#define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)
+
+#define __HAL_RCC_USART6_CLK_ENABLE()  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART6)
+#define __HAL_RCC_USART6_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART6)
+
+#define __HAL_RCC_UART9_CLK_ENABLE()   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_UART9)
+#define __HAL_RCC_UART9_CLK_DISABLE()  LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_UART9)
+
+#define __HAL_RCC_USART10_CLK_ENABLE()  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART10)
+#define __HAL_RCC_USART10_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART10)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DBGMCU_CLK_ENABLE()  LL_BUS_EnableClock(LL_APB3);
+#define __HAL_RCC_DBGMCU_CLK_DISABLE() LL_BUS_DisableClock(LL_APB3);
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Peripheral_Clock_Enable_Disable APB4 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @note   BSEC peripheral clock is always security-protected and thus hidden to the non-secure
+  *         application.
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_BSEC_CLK_ENABLE()     LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC)
+#define __HAL_RCC_BSEC_CLK_DISABLE()    LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_BSEC)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_DTS_CLK_ENABLE()      LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_DTS)
+#define __HAL_RCC_DTS_CLK_DISABLE()     LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_DTS)
+
+#define __HAL_RCC_HDP_CLK_ENABLE()      LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_HDP)
+#define __HAL_RCC_HDP_CLK_DISABLE()     LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_HDP)
+
+#define __HAL_RCC_I2C4_CLK_ENABLE()     LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_I2C4)
+#define __HAL_RCC_I2C4_CLK_DISABLE()    LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_I2C4)
+
+#define __HAL_RCC_LPTIM2_CLK_ENABLE()   LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM2)
+#define __HAL_RCC_LPTIM2_CLK_DISABLE()  LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM2)
+
+#define __HAL_RCC_LPTIM3_CLK_ENABLE()   LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM3)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE()  LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM3)
+
+#define __HAL_RCC_LPTIM4_CLK_ENABLE()   LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE()  LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM4)
+
+#define __HAL_RCC_LPTIM5_CLK_ENABLE()   LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE()  LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM5)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE()  LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPUART1)
+#define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPUART1)
+
+#define __HAL_RCC_RTC_CLK_ENABLE()      LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_RTC)
+#define __HAL_RCC_RTC_CLK_DISABLE()     LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_RTC)
+
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()   LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_RTCAPB)
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()  LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_RTCAPB)
+
+#define __HAL_RCC_SPI6_CLK_ENABLE()     LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SPI6)
+#define __HAL_RCC_SPI6_CLK_DISABLE()    LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_SPI6)
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG)
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()  LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_SYSCFG)
+
+#define __HAL_RCC_VREFBUF_CLK_ENABLE()  LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_VREFBUF)
+#define __HAL_RCC_VREFBUF_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_VREFBUF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB5_Peripheral_Clock_Enable_Disable APB5 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the APB5 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_CSI_CLK_ENABLE()     LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_CSI)
+#define __HAL_RCC_CSI_CLK_DISABLE()    LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_CSI)
+
+#define __HAL_RCC_DCMIPP_CLK_ENABLE()  LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_DCMIPP)
+#define __HAL_RCC_DCMIPP_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_DCMIPP)
+
+#define __HAL_RCC_GFXTIM_CLK_ENABLE()  LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_GFXTIM)
+#define __HAL_RCC_GFXTIM_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_GFXTIM)
+
+#define __HAL_RCC_LTDC_CLK_ENABLE()    LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_LTDC)
+#define __HAL_RCC_LTDC_CLK_DISABLE()   LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_LTDC)
+
+#define __HAL_RCC_VENC_CLK_ENABLE()    do { \
+                                            LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_VENC); \
+                                            LL_BUS_EnableClock(LL_APB5); \
+                                          } while(0)
+#define __HAL_RCC_VENC_CLK_DISABLE()   do { \
+                                            LL_BUS_DisableClock(LL_APB5); \
+                                            LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_VENC); \
+                                          } while(0)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MISC_Configuration_Clock_Enable_Disable Misc Configuration Clock Enable Disable
+  * @brief  Enable or disable the misc configuration clock.
+  * @note   After reset, the misc configuration clock is disabled and
+  *         the application software has to enable this clock before using it.
+  * @note   DBG clock is always security-protected and thus hidden to the non-secure application.
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_DBG_CLK_ENABLE()     LL_MISC_EnableClock(LL_DBG)
+#define __HAL_RCC_DBG_CLK_DISABLE()    LL_MISC_DisableClock(LL_DBG)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_XSPIPHYCOMP_CLK_ENABLE()  LL_MISC_EnableClock(LL_XSPIPHYCOMP)
+#define __HAL_RCC_XSPIPHYCOMP_CLK_DISABLE() LL_MISC_DisableClock(LL_XSPIPHYCOMP)
+
+#define __HAL_RCC_PER_CLK_ENABLE()  LL_MISC_EnableClock(LL_PER)
+#define __HAL_RCC_PER_CLK_DISABLE() LL_MISC_DisableClock(LL_PER)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Embedded_Mem_Clock_Status Embedded Memory Clock Enabled Status
+  * @brief  Check whether the embedded memory clock is enabled or not.
+  * @note   After reset, some embedded memory clocks are disabled
+  *         and the application software has to enable these memory clocks before using them.
+  * @{
+  */
+
+#define __HAL_RCC_AXISRAM1_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AXISRAM1)
+#define __HAL_RCC_AXISRAM2_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AXISRAM2)
+#define __HAL_RCC_AXISRAM3_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AXISRAM3)
+#define __HAL_RCC_AXISRAM4_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AXISRAM4)
+#define __HAL_RCC_AXISRAM5_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AXISRAM5)
+#define __HAL_RCC_AXISRAM6_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AXISRAM6)
+#define __HAL_RCC_AHBSRAM1_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AHBSRAM1)
+#define __HAL_RCC_AHBSRAM2_MEM_IS_CLK_ENABLED()     LL_MEM_IsEnabledClock(LL_MEM_AHBSRAM2)
+#define __HAL_RCC_BKPSRAM_MEM_IS_CLK_ENABLED()      LL_MEM_IsEnabledClock(LL_MEM_BKPSRAM)
+#define __HAL_RCC_FLEXRAM_MEM_IS_CLK_ENABLED()      LL_MEM_IsEnabledClock(LL_MEM_FLEXRAM)
+#define __HAL_RCC_CACHEAXIRAM_MEM_IS_CLK_ENABLED()  LL_MEM_IsEnabledClock(LL_MEM_CACHEAXIRAM)
+#define __HAL_RCC_VENCRAM_MEM_IS_CLK_ENABLED()      LL_MEM_IsEnabledClock(LL_MEM_VENCRAM)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Clock_Enable_Status AHB1 Peripheral Clock Enabled Status
+  * @brief  Check whether the AHB1 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED()   LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ADC12)
+
+#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED()  LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_GPDMA1)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Enable_Status AHB2 Peripheral Clock Enabled Status
+  * @brief  Check whether the AHB2 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_ADF1_IS_CLK_ENABLED()    LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADF1)
+
+#define __HAL_RCC_MDF1_IS_CLK_ENABLED()    LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_MDF1)
+
+#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED()  LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_RAMCFG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Enable_Status AHB3 Peripheral Clock Enabled Status
+  * @brief  Check whether the AHB3 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()    LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_CRYP)
+#endif /* CRYP */
+
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()    LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HASH)
+
+#define __HAL_RCC_IAC_IS_CLK_ENABLED()     LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IAC)
+
+#define __HAL_RCC_PKA_IS_CLK_ENABLED()     LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)
+
+#define __HAL_RCC_RIFSC_IS_CLK_ENABLED()   LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RIFSC)
+
+#define __HAL_RCC_RISAF_IS_CLK_ENABLED()   LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RISAF)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()     LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)
+
+#if defined(SAES)
+#define __HAL_RCC_SAES_IS_CLK_ENABLED()    LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_SAES)
+#endif /* SAES */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB4_Clock_Enable_Status AHB4 Peripheral Clock Enabled Status
+  * @brief  Check whether the AHB4 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()     LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_CRC)
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOA)
+
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOB)
+
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOC)
+
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOD)
+
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOE)
+
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOF)
+
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOG)
+
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOH)
+
+#define __HAL_RCC_GPION_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPION)
+
+#define __HAL_RCC_GPIOO_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOO)
+
+#define __HAL_RCC_GPIOP_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOP)
+
+#define __HAL_RCC_GPIOQ_IS_CLK_ENABLED()   LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOQ)
+
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()     LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_PWR)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB5_Clock_Enable_Status AHB5 Peripheral Clock Enabled Status
+  * @brief  Check whether the AHB5 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()   LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_DMA2D)
+
+#if defined(ETH1)
+#define __HAL_RCC_ETH1_IS_CLK_ENABLED()    LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1)
+
+#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1MAC)
+
+#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1TX)
+
+#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1RX)
+#endif /* ETH1 */
+
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()     LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_FMC)
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_IS_CLK_ENABLED()   LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_GPU2D)
+#endif /* GPU2D */
+
+#define __HAL_RCC_HPDMA1_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_HPDMA1)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_IS_CLK_ENABLED()    LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_JPEG)
+#endif /* JPEG */
+
+#define __HAL_RCC_XSPI1_IS_CLK_ENABLED()   LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI1)
+
+#define __HAL_RCC_XSPI2_IS_CLK_ENABLED()   LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI2)
+
+#define __HAL_RCC_XSPI3_IS_CLK_ENABLED()   LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI3)
+
+#define __HAL_RCC_XSPIM_IS_CLK_ENABLED()   LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPIM)
+
+#define __HAL_RCC_MCE1_IS_CLK_ENABLED()    LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE1)
+
+#define __HAL_RCC_MCE2_IS_CLK_ENABLED()    LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE2)
+
+#define __HAL_RCC_MCE3_IS_CLK_ENABLED()    LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE3)
+
+#define __HAL_RCC_MCE4_IS_CLK_ENABLED()    LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE4)
+
+#define __HAL_RCC_CACHEAXI_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_CACHEAXI)
+
+#define __HAL_RCC_NPU_IS_CLK_ENABLED()     LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_NPU)
+
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()    LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_PSSI)
+
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_SDMMC1)
+
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_SDMMC2)
+
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTG1)
+
+#define __HAL_RCC_USB1_OTG_HS_PHY_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTGPHY1)
+
+#define __HAL_RCC_USB2_OTG_HS_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTG2)
+
+#define __HAL_RCC_USB2_OTG_HS_PHY_IS_CLK_ENABLED()  LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTGPHY2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Status APB1 Peripheral Clock Enabled Status
+  * @brief  Check whether the APB1 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()  LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_FDCAN)
+
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)
+
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2)
+
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)
+
+#define __HAL_RCC_I3C1_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I3C1)
+
+#define __HAL_RCC_I3C2_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I3C2)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)
+
+#define __HAL_RCC_MDIOS_IS_CLK_ENABLED()  LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_MDIOS)
+
+#define __HAL_RCC_SPDIFRX1_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)
+
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI3)
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)
+
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM3)
+
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM4)
+
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM5)
+
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM6)
+
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM7)
+
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM10)
+
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM11)
+
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM12)
+
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM13)
+
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM14)
+
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART2)
+
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART3)
+
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART4)
+
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART5)
+
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART7)
+
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()  LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART8)
+
+#define __HAL_RCC_UCPD1_IS_CLK_ENABLED()  LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_UCPD1)
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Status APB2 Peripheral Clock Enabled Status
+  * @brief  Check whether the APB2 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)
+
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI2)
+
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)
+
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI4)
+
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI5)
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)
+
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM8)
+
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED()    LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM9)
+
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()   LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM15)
+
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()   LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)
+
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()   LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)
+
+#define __HAL_RCC_TIM18_IS_CLK_ENABLED()   LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM18)
+
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()  LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)
+
+#define __HAL_RCC_USART6_IS_CLK_ENABLED()  LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART6)
+
+#define __HAL_RCC_UART9_IS_CLK_ENABLED()   LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_UART9)
+
+#define __HAL_RCC_USART10_IS_CLK_ENABLED()  LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART10)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_APB3_Clock_Enable_Status APB3 Peripheral Clock Enabled Status
+  * @brief  Check whether the APB3 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED()   LL_BUS_IsEnabledClock(LL_APB3);
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Enable_Status APB4 Peripheral Clock Enabled Status
+  * @brief  Check whether the APB4 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_BSEC_IS_CLK_ENABLED()     LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_BSEC)
+
+#define __HAL_RCC_DTS_IS_CLK_ENABLED()      LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_DTS)
+
+#define __HAL_RCC_HDP_IS_CLK_ENABLED()      LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_HDP)
+
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()     LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_I2C4)
+
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()   LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM2)
+
+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()   LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM3)
+
+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()   LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM4)
+
+#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()   LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM5)
+
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()  LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPUART1)
+
+#define __HAL_RCC_RTC_IS_CLK_ENABLED()      LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_RTC)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()   LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_RTCAPB)
+
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()     LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_SPI6)
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()   LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_SYSCFG)
+
+#define __HAL_RCC_VREFBUF_IS_CLK_ENABLED()  LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_VREFBUF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB5_Clock_Enable_Status APB5 Peripheral Clock Enabled Status
+  * @brief  Check whether the APB5 peripheral clock is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_CSI_IS_CLK_ENABLED()     LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_CSI)
+
+#define __HAL_RCC_DCMIPP_IS_CLK_ENABLED()  LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_DCMIPP)
+
+#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED()  LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_GFXTIM)
+
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_LTDC)
+
+#define __HAL_RCC_VENC_IS_CLK_ENABLED()    LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_VENC)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MISC_Configuration_Clock_Enable_Status Misc Configuration Clock Enabled Status
+  * @brief  Check whether the misc configuration clock is enabled or not.
+  * @note   After reset, the misc configuration clock is disabled and
+  *         the application software has to enable this clock before using it.
+  * @{
+  */
+
+#define __HAL_RCC_DBG_IS_CLK_ENABLED()          LL_MISC_IsEnabledClock(LL_DBG)
+
+#define __HAL_RCC_MCO1_IS_CLK_ENABLED()         LL_MISC_IsEnabledClock(LL_MCO1)
+
+#define __HAL_RCC_MCO2_IS_CLK_ENABLED()         LL_MISC_IsEnabledClock(LL_MCO2)
+
+#define __HAL_RCC_XSPIPHYCOMP_IS_CLK_ENABLED()  LL_MISC_IsEnabledClock(LL_XSPIPHYCOMP)
+
+#define __HAL_RCC_PER_IS_CLK_ENABLED()          LL_MISC_IsEnabledClock(LL_PER)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+
+#define __HAL_RCC_AHB1_FORCE_RESET()       WRITE_REG(RCC->AHB1RSTSR, 0x00000030UL);
+#define __HAL_RCC_AHB1_RELEASE_RESET()     WRITE_REG(RCC->AHB1RSTSR, 0UL)
+
+#define __HAL_RCC_GPDMA1_FORCE_RESET()     LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1)
+#define __HAL_RCC_GPDMA1_RELEASE_RESET()   LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1)
+
+#define __HAL_RCC_ADC12_FORCE_RESET()      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12)
+#define __HAL_RCC_ADC12_RELEASE_RESET()    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+
+#define __HAL_RCC_AHB2_FORCE_RESET()       WRITE_REG(RCC->AHB2RSTSR, 0x00031000UL);
+#define __HAL_RCC_AHB2_RELEASE_RESET()     WRITE_REG(RCC->AHB2RSTSR, 0UL)
+
+#define __HAL_RCC_ADF1_FORCE_RESET()       LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADF1)
+#define __HAL_RCC_ADF1_RELEASE_RESET()     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADF1)
+
+#define __HAL_RCC_MDF1_FORCE_RESET()       LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_MDF1)
+#define __HAL_RCC_MDF1_RELEASE_RESET()     LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_MDF1)
+
+#define __HAL_RCC_RAMCFG_FORCE_RESET()     LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RAMCFG)
+#define __HAL_RCC_RAMCFG_RELEASE_RESET()   LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RAMCFG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
+  * @brief  Force or release AHB3 peripheral reset.
+  * @note   IAC peripheral reset is always security-protected and thus hidden to the non-secure
+  *         application.
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_AHB3_FORCE_RESET()       WRITE_REG(RCC->AHB3RSTSR, 0x00000517UL);
+#else
+#define __HAL_RCC_AHB3_FORCE_RESET()       WRITE_REG(RCC->AHB3RSTSR, 0x00000117UL);
+#endif /* CPU_IN_SECURE_STATE */
+#define __HAL_RCC_AHB3_RELEASE_RESET()     WRITE_REG(RCC->AHB3RSTSR, 0UL)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_IAC_FORCE_RESET()        LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IAC)
+#define __HAL_RCC_IAC_RELEASE_RESET()      LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IAC)
+#endif /* CPU_IN_SECURE_STATE */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_FORCE_RESET()       LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_CRYP)
+#define __HAL_RCC_CRYP_RELEASE_RESET()     LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_CRYP)
+#endif /* CRYP */
+
+#define __HAL_RCC_HASH_FORCE_RESET()       LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HASH)
+#define __HAL_RCC_HASH_RELEASE_RESET()     LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HASH)
+
+#define __HAL_RCC_PKA_FORCE_RESET()        LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA)
+#define __HAL_RCC_PKA_RELEASE_RESET()      LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA)
+
+#define __HAL_RCC_RNG_FORCE_RESET()        LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG)
+#define __HAL_RCC_RNG_RELEASE_RESET()      LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG)
+
+#if defined(SAES)
+#define __HAL_RCC_SAES_FORCE_RESET()       LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_SAES)
+#define __HAL_RCC_SAES_RELEASE_RESET()     LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_SAES)
+#endif /* SAES */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset
+  * @brief  Force or release AHB4 peripheral reset.
+  * @note   PWR peripheral reset is always security-protected and thus hidden to the non-secure
+  *         application.
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_AHB4_FORCE_RESET()       WRITE_REG(RCC->AHB4RSTSR, 0x000DE0FFUL);
+#else
+#define __HAL_RCC_AHB4_FORCE_RESET()       WRITE_REG(RCC->AHB4RSTSR, 0x0005E0FFUL);
+#endif /* CPU_IN_SECURE_STATE */
+#define __HAL_RCC_AHB4_RELEASE_RESET()     WRITE_REG(RCC->AHB4RSTSR, 0UL)
+
+#define __HAL_RCC_CRC_FORCE_RESET()        LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_CRC)
+#define __HAL_RCC_CRC_RELEASE_RESET()      LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_CRC)
+
+#define __HAL_RCC_GPIOA_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA)
+#define __HAL_RCC_GPIOA_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA)
+
+#define __HAL_RCC_GPIOB_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB)
+#define __HAL_RCC_GPIOB_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB)
+
+#define __HAL_RCC_GPIOC_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC)
+#define __HAL_RCC_GPIOC_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC)
+
+#define __HAL_RCC_GPIOD_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD)
+
+#define __HAL_RCC_GPIOE_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE)
+
+#define __HAL_RCC_GPIOF_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF)
+
+#define __HAL_RCC_GPIOG_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG)
+#define __HAL_RCC_GPIOG_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG)
+
+#define __HAL_RCC_GPIOH_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH)
+#define __HAL_RCC_GPIOH_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH)
+
+#define __HAL_RCC_GPION_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPION)
+#define __HAL_RCC_GPION_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPION)
+
+#define __HAL_RCC_GPIOO_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOO)
+#define __HAL_RCC_GPIOO_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOO)
+
+#define __HAL_RCC_GPIOP_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOP)
+#define __HAL_RCC_GPIOP_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOP)
+
+#define __HAL_RCC_GPIOQ_FORCE_RESET()      LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOQ)
+#define __HAL_RCC_GPIOQ_RELEASE_RESET()    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOQ)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_PWR_FORCE_RESET()        LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_PWR)
+#define __HAL_RCC_PWR_RELEASE_RESET()      LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_PWR)
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB5_Force_Release_Reset AHB5 Peripheral Force Release Reset
+  * @brief  Force or release AHB5 peripheral reset.
+  * @{
+  */
+
+/* Caution: The two following macros should only be called from code running in internal RAM
+ *          since it resets the external peripheral memory interfaces.
+ */
+#define __HAL_RCC_AHB5_FORCE_RESET()       WRITE_REG(RCC->AHB5RSTSR, 0xFF9A31FBUL)
+#define __HAL_RCC_AHB5_RELEASE_RESET()     WRITE_REG(RCC->AHB5RSTSR, 0UL)
+
+#define __HAL_RCC_DMA2D_FORCE_RESET()      LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_DMA2D)
+#define __HAL_RCC_DMA2D_RELEASE_RESET()    LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_DMA2D)
+
+#if defined(ETH1)
+#define __HAL_RCC_ETH1_FORCE_RESET()       LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_ETH1);
+#define __HAL_RCC_ETH1_RELEASE_RESET()     LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_ETH1);
+#endif /* ETH1 */
+
+#define __HAL_RCC_FMC_FORCE_RESET()        LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_FMC)
+#define __HAL_RCC_FMC_RELEASE_RESET()      LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_FMC)
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_FORCE_RESET()     LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#define __HAL_RCC_GFXMMU_RELEASE_RESET()   LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_FORCE_RESET()      LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_GPU2D)
+#define __HAL_RCC_GPU2D_RELEASE_RESET()    LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_GPU2D)
+#endif /* GPU2D */
+
+#define __HAL_RCC_HPDMA1_FORCE_RESET()     LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_HPDMA1)
+#define __HAL_RCC_HPDMA1_RELEASE_RESET()   LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_HPDMA1)
+
+#define __HAL_RCC_XSPI1_FORCE_RESET()      LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI1)
+#define __HAL_RCC_XSPI1_RELEASE_RESET()    LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI1)
+
+#define __HAL_RCC_XSPI2_FORCE_RESET()      LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI2)
+#define __HAL_RCC_XSPI2_RELEASE_RESET()    LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI2)
+
+#define __HAL_RCC_XSPI3_FORCE_RESET()      LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI3);
+#define __HAL_RCC_XSPI3_RELEASE_RESET()    LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI3);
+
+#define __HAL_RCC_XSPIM_FORCE_RESET()      LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPIM)
+#define __HAL_RCC_XSPIM_RELEASE_RESET()   LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPIM)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_FORCE_RESET()       LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_JPEG)
+#define __HAL_RCC_JPEG_RELEASE_RESET()     LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_JPEG)
+#endif /* JPEG */
+
+#define __HAL_RCC_CACHEAXI_FORCE_RESET()   LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_CACHEAXI);
+#define __HAL_RCC_CACHEAXI_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_CACHEAXI);
+
+#define __HAL_RCC_NPU_FORCE_RESET()        LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_NPU);
+#define __HAL_RCC_NPU_RELEASE_RESET()      LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_NPU);
+
+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET()       LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_PSSI)
+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()     LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_PSSI)
+
+#define __HAL_RCC_SDMMC1_FORCE_RESET()     LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_SDMMC1)
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()   LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_SDMMC1)
+
+#define __HAL_RCC_SDMMC2_FORCE_RESET()     LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_SDMMC2)
+#define __HAL_RCC_SDMMC2_RELEASE_RESET()   LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_SDMMC2)
+
+#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()   LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG1)
+#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG1)
+
+#define __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET()   LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTGPHY1);
+#define __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTGPHY1);
+
+#define __HAL_RCC_USB1_OTG_HS_CTL_FORCE_RESET()   LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG1PHYCTL);
+#define __HAL_RCC_USB1_OTG_HS_CTL_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG1PHYCTL);
+
+#define __HAL_RCC_USB2_OTG_HS_FORCE_RESET()   LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG2)
+#define __HAL_RCC_USB2_OTG_HS_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG2)
+
+#define __HAL_RCC_USB2_OTG_HS_PHY_FORCE_RESET()   LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTGPHY2);
+#define __HAL_RCC_USB2_OTG_HS_PHY_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTGPHY2);
+
+#define __HAL_RCC_USB2_OTG_HS_CTL_FORCE_RESET()   LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG2PHYCTL);
+#define __HAL_RCC_USB2_OTG_HS_CTL_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG2PHYCTL);
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+
+#define __HAL_RCC_APB1_FORCE_RESET()     do { \
+                                              WRITE_REG(RCC->APB1RSTSR1, 0xC3FFF3FFUL); \
+                                              WRITE_REG(RCC->APB1RSTSR2, 0x00040120UL); \
+                                            } while(0)
+#define __HAL_RCC_APB1_RELEASE_RESET()   do { \
+                                              WRITE_REG(RCC->APB1RSTSR1, 0UL); \
+                                              WRITE_REG(RCC->APB1RSTSR2, 0UL); \
+                                            } while(0)
+
+#define __HAL_RCC_FDCAN_FORCE_RESET()    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_FDCAN)
+#define __HAL_RCC_FDCAN_RELEASE_RESET()  LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_FDCAN)
+
+#define __HAL_RCC_I2C1_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1)
+#define __HAL_RCC_I2C1_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1)
+
+#define __HAL_RCC_I2C2_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2)
+#define __HAL_RCC_I2C2_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2)
+
+#define __HAL_RCC_I2C3_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3)
+#define __HAL_RCC_I2C3_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3)
+
+#define __HAL_RCC_I3C1_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C1)
+#define __HAL_RCC_I3C1_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C1)
+
+#define __HAL_RCC_I3C2_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C2)
+#define __HAL_RCC_I3C2_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C2)
+
+#define __HAL_RCC_LPTIM1_FORCE_RESET()   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1)
+
+#define __HAL_RCC_MDIOS_FORCE_RESET()    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_MDIOS)
+#define __HAL_RCC_MDIOS_RELEASE_RESET()  LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_MDIOS)
+
+#define __HAL_RCC_SPDIFRX1_FORCE_RESET()   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+#define __HAL_RCC_SPDIFRX1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+
+#define __HAL_RCC_SPI2_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2)
+#define __HAL_RCC_SPI2_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2)
+
+#define __HAL_RCC_SPI3_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3)
+#define __HAL_RCC_SPI3_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3)
+
+#define __HAL_RCC_TIM2_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2)
+#define __HAL_RCC_TIM2_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2)
+
+#define __HAL_RCC_TIM3_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3)
+#define __HAL_RCC_TIM3_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3)
+
+#define __HAL_RCC_TIM4_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4)
+#define __HAL_RCC_TIM4_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4)
+
+#define __HAL_RCC_TIM5_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5)
+#define __HAL_RCC_TIM5_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5)
+
+#define __HAL_RCC_TIM6_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6)
+#define __HAL_RCC_TIM6_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6)
+
+#define __HAL_RCC_TIM7_FORCE_RESET()     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7)
+#define __HAL_RCC_TIM7_RELEASE_RESET()   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7)
+
+#define __HAL_RCC_TIM10_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM10)
+#define __HAL_RCC_TIM10_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM10)
+
+#define __HAL_RCC_TIM11_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM11)
+#define __HAL_RCC_TIM11_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM11)
+
+#define __HAL_RCC_TIM12_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12)
+#define __HAL_RCC_TIM12_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12)
+
+#define __HAL_RCC_TIM13_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13)
+#define __HAL_RCC_TIM13_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13)
+
+#define __HAL_RCC_TIM14_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14)
+#define __HAL_RCC_TIM14_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14)
+
+#define __HAL_RCC_UCPD1_FORCE_RESET()    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1)
+#define __HAL_RCC_UCPD1_RELEASE_RESET()  LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1)
+
+#define __HAL_RCC_USART2_FORCE_RESET()   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2)
+#define __HAL_RCC_USART2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2)
+
+#define __HAL_RCC_USART3_FORCE_RESET()   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3)
+#define __HAL_RCC_USART3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3)
+
+#define __HAL_RCC_UART4_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4)
+#define __HAL_RCC_UART4_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4)
+
+#define __HAL_RCC_UART5_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5)
+#define __HAL_RCC_UART5_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5)
+
+#define __HAL_RCC_UART7_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7)
+#define __HAL_RCC_UART7_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7)
+
+#define __HAL_RCC_UART8_FORCE_RESET()    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8)
+#define __HAL_RCC_UART8_RELEASE_RESET()  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+
+#define __HAL_RCC_APB2_FORCE_RESET()      WRITE_REG(RCC->APB2RSTSR, 0x007FB0F3UL)
+#define __HAL_RCC_APB2_RELEASE_RESET()    WRITE_REG(RCC->APB2RSTSR, 0UL)
+
+#define __HAL_RCC_SAI1_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1)
+#define __HAL_RCC_SAI1_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1)
+
+#define __HAL_RCC_SAI2_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI2)
+#define __HAL_RCC_SAI2_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI2)
+
+#define __HAL_RCC_SPI1_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)
+#define __HAL_RCC_SPI1_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)
+
+#define __HAL_RCC_SPI4_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4)
+#define __HAL_RCC_SPI4_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4)
+
+#define __HAL_RCC_SPI5_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5)
+#define __HAL_RCC_SPI5_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5)
+
+#define __HAL_RCC_TIM1_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)
+#define __HAL_RCC_TIM1_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)
+
+#define __HAL_RCC_TIM8_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8)
+#define __HAL_RCC_TIM8_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8)
+
+#define __HAL_RCC_TIM9_FORCE_RESET()      LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9)
+#define __HAL_RCC_TIM9_RELEASE_RESET()    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9)
+
+#define __HAL_RCC_TIM15_FORCE_RESET()     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15)
+#define __HAL_RCC_TIM15_RELEASE_RESET()   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15)
+
+#define __HAL_RCC_TIM16_FORCE_RESET()     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16)
+#define __HAL_RCC_TIM16_RELEASE_RESET()   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16)
+
+#define __HAL_RCC_TIM17_FORCE_RESET()     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17)
+#define __HAL_RCC_TIM17_RELEASE_RESET()   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17)
+
+#define __HAL_RCC_TIM18_FORCE_RESET()     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM18)
+#define __HAL_RCC_TIM18_RELEASE_RESET()   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM18)
+
+#define __HAL_RCC_USART1_FORCE_RESET()    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)
+#define __HAL_RCC_USART1_RELEASE_RESET()  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)
+
+#define __HAL_RCC_USART6_FORCE_RESET()    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6)
+#define __HAL_RCC_USART6_RELEASE_RESET()  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6)
+
+#define __HAL_RCC_UART9_FORCE_RESET()     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9)
+#define __HAL_RCC_UART9_RELEASE_RESET()   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9)
+
+#define __HAL_RCC_USART10_FORCE_RESET()   LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10)
+#define __HAL_RCC_USART10_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Force_Release_Reset APB4 Peripheral Force Release Reset
+  * @brief  Force or release APB4 peripheral reset.
+  * @{
+  */
+
+#define __HAL_RCC_APB4_FORCE_RESET()      do { \
+                                               WRITE_REG(RCC->APB4RSTSR1, 0x00019EACUL); \
+                                               WRITE_REG(RCC->APB4RSTSR2, 0x00000005UL); \
+                                             } while(0)
+#define __HAL_RCC_APB4_RELEASE_RESET()    do { \
+                                               WRITE_REG(RCC->APB4RSTSR1, 0UL); \
+                                               WRITE_REG(RCC->APB4RSTSR2, 0UL); \
+                                             } while(0)
+
+#define __HAL_RCC_DTS_FORCE_RESET()       LL_APB4_GRP2_ForceReset(LL_APB4_GRP2_PERIPH_DTS)
+#define __HAL_RCC_DTS_RELEASE_RESET()     LL_APB4_GRP2_ReleaseReset(LL_APB4_GRP2_PERIPH_DTS)
+
+#define __HAL_RCC_HDP_FORCE_RESET()       LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_HDP)
+#define __HAL_RCC_HDP_RELEASE_RESET()     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_HDP)
+
+#define __HAL_RCC_I2C4_FORCE_RESET()      LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_I2C4)
+#define __HAL_RCC_I2C4_RELEASE_RESET()    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_I2C4)
+
+#define __HAL_RCC_LPTIM2_FORCE_RESET()    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2)
+#define __HAL_RCC_LPTIM2_RELEASE_RESET()  LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2)
+
+#define __HAL_RCC_LPTIM3_FORCE_RESET()    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3)
+#define __HAL_RCC_LPTIM3_RELEASE_RESET()  LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3)
+
+#define __HAL_RCC_LPTIM4_FORCE_RESET()    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4)
+#define __HAL_RCC_LPTIM4_RELEASE_RESET()  LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4)
+
+#define __HAL_RCC_LPTIM5_FORCE_RESET()    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5)
+#define __HAL_RCC_LPTIM5_RELEASE_RESET()  LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5)
+
+#define __HAL_RCC_LPUART1_FORCE_RESET()   LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPUART1)
+#define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPUART1)
+
+#define __HAL_RCC_RTC_FORCE_RESET()       LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_RTC)
+#define __HAL_RCC_RTC_RELEASE_RESET()     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_RTC)
+
+#define __HAL_RCC_SPI6_FORCE_RESET()      LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6)
+#define __HAL_RCC_SPI6_RELEASE_RESET()    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6)
+
+#define __HAL_RCC_SYSCFG_FORCE_RESET()    LL_APB4_GRP2_ForceReset(LL_APB4_GRP2_PERIPH_SYSCFG)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()  LL_APB4_GRP2_ReleaseReset(LL_APB4_GRP2_PERIPH_SYSCFG)
+
+#define __HAL_RCC_VREFBUF_FORCE_RESET()   LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_VREFBUF)
+#define __HAL_RCC_VREFBUF_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_VREFBUF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB5_Force_Release_Reset APB5 Peripheral Force Release Reset
+  * @brief  Force or release APB5 peripheral reset.
+  * @{
+  */
+
+#define __HAL_RCC_APB5_FORCE_RESET()      WRITE_REG(RCC->APB5RSTSR, 0x00000076UL)
+#define __HAL_RCC_APB5_RELEASE_RESET()    WRITE_REG(RCC->APB5RSTSR, 0UL)
+
+#define __HAL_RCC_CSI_FORCE_RESET()       LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_CSI)
+#define __HAL_RCC_CSI_RELEASE_RESET()     LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_CSI)
+
+#define __HAL_RCC_DCMIPP_FORCE_RESET()    LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_DCMIPP)
+#define __HAL_RCC_DCMIPP_RELEASE_RESET()  LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_DCMIPP)
+
+#define __HAL_RCC_GFXTIM_FORCE_RESET()    LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_GFXTIM)
+#define __HAL_RCC_GFXTIM_RELEASE_RESET()  LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_GFXTIM)
+
+#define __HAL_RCC_LTDC_FORCE_RESET()      LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_LTDC)
+#define __HAL_RCC_LTDC_RELEASE_RESET()    LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_LTDC)
+
+#define __HAL_RCC_VENC_FORCE_RESET()     LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_VENC)
+#define __HAL_RCC_VENC_RELEASE_RESET()   LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_VENC)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MISC_Configuration_Force_Release_Reset Misc Configuration Force Release Reset
+  * @brief  Force or release misc configuration reset.
+  * @note   DBG reset is always security-protected and thus hidden to the non-secure application.
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_DBG_FORCE_RESET()         LL_MISC_ForceReset(LL_DBG)
+#define __HAL_RCC_DBG_RELEASE_RESET()       LL_MISC_ReleaseReset(LL_DBG)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_XSPIPHY1_FORCE_RESET()    LL_MISC_ForceReset(LL_XSPIPHY1)
+#define __HAL_RCC_XSPIPHY1_RELEASE_RESET()  LL_MISC_ReleaseReset(LL_XSPIPHY1)
+
+#define __HAL_RCC_XSPIPHY2_FORCE_RESET()    LL_MISC_ForceReset(LL_XSPIPHY2)
+#define __HAL_RCC_XSPIPHY2_RELEASE_RESET()  LL_MISC_ReleaseReset(LL_XSPIPHY2)
+
+#define __HAL_RCC_SDMMC1DLL_FORCE_RESET()   LL_MISC_ForceReset(LL_SDMMC1DLL)
+#define __HAL_RCC_SDMMC1DLL_RELEASE_RESET() LL_MISC_ReleaseReset(LL_SDMMC1DLL)
+
+#define __HAL_RCC_SDMMC2DLL_FORCE_RESET()   LL_MISC_ForceReset(LL_SDMMC2DLL)
+#define __HAL_RCC_SDMMC2DLL_RELEASE_RESET() LL_MISC_ReleaseReset(LL_SDMMC2DLL)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_Embedded_Mem_Clock_Sleep_Enable_Disable Embedded memory Clock Sleep Enable Disable
+  * @brief  Enable or disable the embedded memory clock during Low Power (Sleep) mode.
+  * @note   Embedded memory clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all embedded memory clocks are disabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM1)
+#define __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM1)
+
+#define __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM2)
+#define __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM2)
+
+#define __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM3)
+#define __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM3)
+
+#define __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM4)
+#define __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM4)
+
+#define __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM5)
+#define __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM5)
+
+#define __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM6)
+#define __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM6)
+
+#define __HAL_RCC_AHBSRAM1_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AHBSRAM1)
+#define __HAL_RCC_AHBSRAM1_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AHBSRAM1)
+
+#define __HAL_RCC_AHBSRAM2_MEM_CLK_SLEEP_ENABLE()     LL_MEM_EnableClockLowPower(LL_MEM_AHBSRAM2)
+#define __HAL_RCC_AHBSRAM2_MEM_CLK_SLEEP_DISABLE()    LL_MEM_DisableClockLowPower(LL_MEM_AHBSRAM2)
+
+#define __HAL_RCC_BKPSRAM_MEM_CLK_SLEEP_ENABLE()      LL_MEM_EnableClockLowPower(LL_MEM_BKPSRAM)
+#define __HAL_RCC_BKPSRAM_MEM_CLK_SLEEP_DISABLE()     LL_MEM_DisableClockLowPower(LL_MEM_BKPSRAM)
+
+#define __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_ENABLE()      LL_MEM_EnableClockLowPower(LL_MEM_FLEXRAM)
+#define __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_DISABLE()     LL_MEM_DisableClockLowPower(LL_MEM_FLEXRAM)
+
+#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_SLEEP_ENABLE()  LL_MEM_EnableClockLowPower(LL_MEM_CACHEAXIRAM)
+#define __HAL_RCC_CACHEAXIRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_CACHEAXIRAM)
+
+#define __HAL_RCC_VENCRAM_MEM_CLK_SLEEP_ENABLE()      LL_MEM_EnableClockLowPower(LL_MEM_VENCRAM)
+#define __HAL_RCC_VENCRAM_MEM_CLK_SLEEP_DISABLE()     LL_MEM_DisableClockLowPower(LL_MEM_VENCRAM)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks are disabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()   LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12)
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()  LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12)
+
+#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE()  LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1)
+#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks are disabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE()    LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1)
+#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE()   LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1)
+
+#define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE()    LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1)
+#define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE()   LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1)
+
+#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE()  LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG)
+#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks except IAC are disabled during SLEEP mode.
+  * @note   IAC, RIFSC and RIFAF peripheral clocks are always security-protected and thus hidden
+  *         to the non-secure application.
+  * @{
+  */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()    LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()   LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP)
+#endif /* CRYP */
+
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()    LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()   LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_HASH)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_IAC_CLK_SLEEP_ENABLE()     LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_IAC)
+#define __HAL_RCC_IAC_CLK_SLEEP_DISABLE()    LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_IAC)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE()     LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_PKA)
+#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE()    LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_PKA)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_RIFSC_CLK_SLEEP_ENABLE()   LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC)
+#define __HAL_RCC_RIFSC_CLK_SLEEP_DISABLE()  LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC)
+#endif /* CPU_IN_SECURE_STATE */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_RISAF_CLK_SLEEP_ENABLE()   LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF)
+#define __HAL_RCC_RISAF_CLK_SLEEP_DISABLE()  LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()     LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RNG)
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()    LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RNG)
+
+#if defined(SAES)
+#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE()    LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_SAES)
+#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE()   LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_SAES)
+#endif /* SAES */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks except PWR are disabled during SLEEP mode.
+  * @note   PWR is always security-protected and thus hidden for non-secure application
+  * @{
+  */
+
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()     LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_CRC)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()    LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_CRC)
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA)
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA)
+
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB)
+
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC)
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD)
+
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE)
+
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF)
+
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG)
+
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH)
+
+#define __HAL_RCC_GPION_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPION)
+#define __HAL_RCC_GPION_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPION)
+
+#define __HAL_RCC_GPIOO_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO)
+#define __HAL_RCC_GPIOO_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO)
+
+#define __HAL_RCC_GPIOP_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP)
+#define __HAL_RCC_GPIOP_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP)
+
+#define __HAL_RCC_GPIOQ_CLK_SLEEP_ENABLE()   LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ)
+#define __HAL_RCC_GPIOQ_CLK_SLEEP_DISABLE()  LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_PWR)
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_PWR)
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable AHB5 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks are disabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()   LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D)
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()  LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D)
+
+#if defined(ETH1)
+#define __HAL_RCC_ETH1_CLK_SLEEP_ENABLE()    LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1)
+#define __HAL_RCC_ETH1_CLK_SLEEP_DISABLE()   LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1)
+
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC)
+
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX)
+
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX)
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX)
+#endif /* ETH1 */
+
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()     LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_FMC)
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()    LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_FMC)
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE()   LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D)
+#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE()  LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D)
+#endif /* GPU2D */
+
+#define __HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1)
+#define __HAL_RCC_HPDMA1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()    LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG)
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()   LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG)
+#endif /* JPEG */
+
+#define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE()   LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1)
+#define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE()  LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1)
+
+#define __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE()   LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2)
+#define __HAL_RCC_XSPI2_CLK_SLEEP_DISABLE()  LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2)
+
+#define __HAL_RCC_XSPI3_CLK_SLEEP_ENABLE()   LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3)
+#define __HAL_RCC_XSPI3_CLK_SLEEP_DISABLE()  LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3)
+
+#define __HAL_RCC_XSPIM_CLK_SLEEP_ENABLE()   LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM)
+#define __HAL_RCC_XSPIM_CLK_SLEEP_DISABLE()  LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM)
+
+#define __HAL_RCC_MCE1_CLK_SLEEP_ENABLE()    LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1)
+#define __HAL_RCC_MCE1_CLK_SLEEP_DISABLE()   LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1)
+
+#define __HAL_RCC_MCE2_CLK_SLEEP_ENABLE()    LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2)
+#define __HAL_RCC_MCE2_CLK_SLEEP_DISABLE()   LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2)
+
+#define __HAL_RCC_MCE3_CLK_SLEEP_ENABLE()    LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3)
+#define __HAL_RCC_MCE3_CLK_SLEEP_DISABLE()   LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3)
+
+#define __HAL_RCC_MCE4_CLK_SLEEP_ENABLE()    LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4)
+#define __HAL_RCC_MCE4_CLK_SLEEP_DISABLE()   LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4)
+
+#define __HAL_RCC_CACHEAXI_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI)
+#define __HAL_RCC_CACHEAXI_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI)
+
+#define __HAL_RCC_NPU_CLK_SLEEP_ENABLE()     LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_NPU)
+#define __HAL_RCC_NPU_CLK_SLEEP_DISABLE()    LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_NPU)
+
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()    LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()   LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI)
+
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1)
+
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2)
+
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1)
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1)
+
+#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1)
+#define __HAL_RCC_USB1_OTG_HS_PHY_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1)
+
+#define __HAL_RCC_USB2_OTG_HS_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2)
+#define __HAL_RCC_USB2_OTG_HS_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2)
+
+#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_SLEEP_ENABLE()  LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2)
+#define __HAL_RCC_USB2_OTG_HS_PHY_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks are disabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()  LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN)
+
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1)
+
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2)
+
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C3)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C3)
+
+#define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1)
+#define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1)
+
+#define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C2)
+#define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C2)
+
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1)
+
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()  LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS)
+
+#define __HAL_RCC_SPDIFRX1_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+#define __HAL_RCC_SPDIFRX1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2)
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2)
+
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3)
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2)
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2)
+
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3)
+
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4)
+
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5)
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6)
+
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7)
+
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM10)
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM10)
+
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM11)
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM11)
+
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12)
+
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM13)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM13)
+
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM14)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM14)
+
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART2)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART2)
+
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART3)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART3)
+
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART4)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART4)
+
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART5)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART5)
+
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART7)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART7)
+
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()  LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART8)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART8)
+
+#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE()  LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1)
+#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1)
+
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()   LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG)
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()  LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks are disabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SAI1)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SAI1)
+
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SAI2)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SAI2)
+
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1)
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1)
+
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI4)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI4)
+
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI5)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI5)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1)
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1)
+
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8)
+
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM9)
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM9)
+
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()   LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()  LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15)
+
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()   LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()  LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16)
+
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()   LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()  LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17)
+
+#define __HAL_RCC_TIM18_CLK_SLEEP_ENABLE()   LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM18)
+#define __HAL_RCC_TIM18_CLK_SLEEP_DISABLE()  LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM18)
+
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART1)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART1)
+
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART6)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART6)
+
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()   LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()  LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_UART9)
+
+#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()  LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART10)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Sleep_Enable_Disable APB4 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks except BSEC are disabled during SLEEP mode.
+  * @note   BSEC peripheral clock is always security-protected and thus hidden to the non-secure
+  *         application.
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE()     LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_BSEC)
+#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE()    LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_BSEC)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()      LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()     LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_DTS)
+
+#define __HAL_RCC_HDP_CLK_SLEEP_ENABLE()      LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_HDP)
+#define __HAL_RCC_HDP_CLK_SLEEP_DISABLE()     LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_HDP)
+
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()     LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_I2C4)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()    LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_I2C4)
+
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()   LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()  LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2)
+
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()   LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()  LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3)
+
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()   LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()  LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4)
+
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()   LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()  LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5)
+
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()  LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1)
+
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()      LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_RTC)
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()     LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_RTC)
+
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()   LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()  LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB)
+
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()     LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_SPI6)
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()    LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_SPI6)
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()   LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG)
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()  LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG)
+
+#define __HAL_RCC_VREFBUF_CLK_SLEEP_ENABLE()  LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF)
+#define __HAL_RCC_VREFBUF_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB5_Clock_Sleep_Enable_Disable APB5 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB5 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   By default, all peripheral clocks are disabled during SLEEP mode.
+  * @{
+  */
+
+#define __HAL_RCC_CSI_CLK_SLEEP_ENABLE()     LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_CSI)
+#define __HAL_RCC_CSI_CLK_SLEEP_DISABLE()    LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_CSI)
+
+#define __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE()  LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP)
+#define __HAL_RCC_DCMIPP_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP)
+
+#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE()  LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM)
+#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM)
+
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_LTDC)
+
+#define __HAL_RCC_VENC_CLK_SLEEP_ENABLE()    LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_VENC)
+#define __HAL_RCC_VENC_CLK_SLEEP_DISABLE()   LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_VENC)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MISC_Configuration_Clock_Sleep_Enable_Disable Misc Configuration Clock Sleep Enable Disable
+  * @brief  Enable or disable the misc configuration clock during Low Power (Sleep) mode.
+  * @note   After reset, the misc configuration clock is disabled and
+  *         the application software has to enable this clock before using it.
+  * @note   After wakeup from SLEEP mode, the misc configuration clock is enabled again.
+  * @note   DBG clock is always security-protected and thus hidden the non-secure application.
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+#define __HAL_RCC_DBG_CLK_SLEEP_ENABLE()     LL_MISC_EnableClockLowPower(LL_DBG)
+#define __HAL_RCC_DBG_CLK_SLEEP_DISABLE()    LL_MISC_DisableClockLowPower(LL_DBG)
+#endif /* CPU_IN_SECURE_STATE */
+
+#define __HAL_RCC_XSPIPHYCOMP_CLK_SLEEP_ENABLE()  LL_MISC_EnableClockLowPower(LL_XSPIPHYCOMP)
+#define __HAL_RCC_XSPIPHYCOMP_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_XSPIPHYCOMP)
+
+#define __HAL_RCC_PER_CLK_SLEEP_ENABLE()  LL_MISC_EnableClockLowPower(LL_PER)
+#define __HAL_RCC_PER_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_PER)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Embedded_Mem_Clock_Sleep_Enable_Status Embedded Memory Clock Sleep Enabled Status
+  * @brief  Check whether the embedded memory clock sleep is enabled or not.
+  * @note   After reset, some embedded memory clocks are disabled
+  *         and the application software has to enable these memory clocks before using them.
+  * @{
+  */
+
+#define __HAL_RCC_AXISRAM1_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM1)
+#define __HAL_RCC_AXISRAM2_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM2)
+#define __HAL_RCC_AXISRAM3_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM3)
+#define __HAL_RCC_AXISRAM4_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM4)
+#define __HAL_RCC_AXISRAM5_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM5)
+#define __HAL_RCC_AXISRAM6_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM6)
+#define __HAL_RCC_AHBSRAM1_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AHBSRAM1)
+#define __HAL_RCC_AHBSRAM2_MEM_IS_CLK_SLEEP_ENABLED()     LL_MEM_IsEnabledClockLowPower(LL_MEM_AHBSRAM2)
+#define __HAL_RCC_BKPSRAM_MEM_IS_CLK_SLEEP_ENABLED()      LL_MEM_IsEnabledClockLowPower(LL_MEM_BKPSRAM)
+#define __HAL_RCC_FLEXRAM_MEM_IS_CLK_SLEEP_ENABLED()      LL_MEM_IsEnabledClockLowPower(LL_MEM_FLEXRAM)
+#define __HAL_RCC_CACHEAXIRAM_MEM_IS_CLK_SLEEP_ENABLED()  LL_MEM_IsEnabledClockLowPower(LL_MEM_CACHEAXIRAM)
+#define __HAL_RCC_VENCRAM_MEM_IS_CLK_SLEEP_ENABLED()      LL_MEM_IsEnabledClockLowPower(LL_MEM_VENCRAM)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Status AHB1 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the AHB1 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()   LL_AHB1_GRP1_IsEnabledClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12)
+
+#define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED()  LL_AHB1_GRP1_IsEnabledClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Status AHB2 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the AHB2 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_ADF1_IS_CLK_SLEEP_ENABLED()    LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1)
+
+#define __HAL_RCC_MDF1_IS_CLK_SLEEP_ENABLED()    LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1)
+
+#define __HAL_RCC_RAMCFG_IS_CLK_SLEEP_ENABLED()  LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Status AHB3 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the AHB3 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()    LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP)
+#endif /* CRYP */
+
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()    LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_HASH)
+
+#define __HAL_RCC_IAC_IS_CLK_SLEEP_ENABLED()     LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_IAC)
+
+#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED()     LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_PKA)
+
+#define __HAL_RCC_RIFSC_IS_CLK_SLEEP_ENABLED()   LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC)
+
+#define __HAL_RCC_RISAF_IS_CLK_SLEEP_ENABLED()   LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF)
+
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RNG)
+
+#if defined(SAES)
+#define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED()    LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_SAES)
+#endif /* SAES */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Status AHB4 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the AHB4 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_CRC)
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA)
+
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB)
+
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC)
+
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD)
+
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE)
+
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF)
+
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG)
+
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH)
+
+#define __HAL_RCC_GPION_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPION)
+
+#define __HAL_RCC_GPIOO_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO)
+
+#define __HAL_RCC_GPIOP_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP)
+
+#define __HAL_RCC_GPIOQ_IS_CLK_SLEEP_ENABLED()   LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ)
+
+#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()     LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_PWR)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB5_Clock_Sleep_Enable_Status AHB5 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the AHB5 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()   LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D)
+
+#if defined(ETH1)
+#define __HAL_RCC_ETH1_IS_CLK_SLEEP_ENABLED()    LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1)
+
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC)
+
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX)
+
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX)
+#endif /* ETH1 */
+
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_FMC)
+
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU)
+#endif /* GFXMMU */
+
+#if defined(GPU2D)
+#define __HAL_RCC_GPU2D_IS_CLK_SLEEP_ENABLED()   LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D)
+#endif /* GPU2D */
+
+#define __HAL_RCC_HPDMA1_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED()    LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG)
+#endif /* JPEG */
+
+#define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED()   LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1)
+
+#define __HAL_RCC_XSPI2_IS_CLK_SLEEP_ENABLED()   LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2)
+
+#define __HAL_RCC_XSPI3_IS_CLK_SLEEP_ENABLED()   LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3)
+
+#define __HAL_RCC_XSPIM_IS_CLK_SLEEP_ENABLED()   LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM)
+
+#define __HAL_RCC_MCE1_IS_CLK_SLEEP_ENABLED()    LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1)
+
+#define __HAL_RCC_MCE2_IS_CLK_SLEEP_ENABLED()    LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2)
+
+#define __HAL_RCC_MCE3_IS_CLK_SLEEP_ENABLED()    LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3)
+
+#define __HAL_RCC_MCE4_IS_CLK_SLEEP_ENABLED()    LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4)
+
+#define __HAL_RCC_CACHEAXI_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI)
+
+#define __HAL_RCC_NPU_IS_CLK_SLEEP_ENABLED()     LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_NPU)
+
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()    LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI)
+
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1)
+
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2)
+
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1)
+
+#define __HAL_RCC_USB1_OTG_HS_PHY_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1)
+
+#define __HAL_RCC_USB2_OTG_HS_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2)
+
+#define __HAL_RCC_USB2_OTG_HS_PHY_IS_CLK_SLEEP_ENABLED()  LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Sleep_Enable_Status APB1 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the APB1 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN)
+
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C1)
+
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C2)
+
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C3)
+
+#define __HAL_RCC_I3C1_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I3C1)
+
+#define __HAL_RCC_I3C2_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I3C2)
+
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1)
+
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS)
+
+#define __HAL_RCC_SPDIFRX1_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1)
+
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPI2)
+
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPI3)
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM2)
+
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM3)
+
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM4)
+
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM5)
+
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM6)
+
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM7)
+
+#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM10)
+
+#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM11)
+
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM12)
+
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM13)
+
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM14)
+
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_USART2)
+
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_USART3)
+
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART4)
+
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART5)
+
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART7)
+
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART8)
+
+#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED()  LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1)
+
+#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()   LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_WWDG)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Sleep_Enable_Status APB2 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the APB2 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SAI1)
+
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SAI2)
+
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI1)
+
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI4)
+
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI5)
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM1)
+
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM8)
+
+#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM9)
+
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()   LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM15)
+
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()   LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM16)
+
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()   LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM17)
+
+#define __HAL_RCC_TIM18_IS_CLK_SLEEP_ENABLED()   LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM18)
+
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()  LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART1)
+
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()  LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART6)
+
+#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()   LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_UART9)
+
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()  LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART10)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Sleep_Enable_Status APB4 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the APB4 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_BSEC_IS_CLK_SLEEP_ENABLED()     LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_BSEC)
+
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()      LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_DTS)
+
+#define __HAL_RCC_HDP_IS_CLK_SLEEP_ENABLED()      LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_HDP)
+
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()     LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_I2C4)
+
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()   LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2)
+
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()   LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3)
+
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()   LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4)
+
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()   LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5)
+
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()  LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1)
+
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()      LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_RTC)
+
+#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()   LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB)
+
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()     LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_SPI6)
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()   LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG)
+
+#define __HAL_RCC_VREFBUF_IS_CLK_SLEEP_ENABLED()  LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB5_Clock_Sleep_Enable_Status APB5 Peripheral Clock Sleep Enabled Status
+  * @brief  Check whether the APB5 peripheral clock sleep is enabled or not.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+
+#define __HAL_RCC_CSI_IS_CLK_SLEEP_ENABLED()     LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_CSI)
+
+#define __HAL_RCC_DCMIPP_IS_CLK_SLEEP_ENABLED()  LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP)
+
+#define __HAL_RCC_GFXTIM_IS_CLK_SLEEP_ENABLED()  LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM)
+
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_LTDC)
+
+#define __HAL_RCC_VENC_IS_CLK_SLEEP_ENABLED()    LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_VENC)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MISC_Configuration_Clock_Sleep_Enable_Status Misc Configuration Clock Sleep Enabled Status
+  * @brief  Check whether the misc configuration clock sleep is enabled or not.
+  * @note   After reset, the misc configuration clock is disabled and
+  *         the application software has to enable this clock before using it.
+  * @{
+  */
+
+#define __HAL_RCC_DBG_IS_CLK_SLEEP_ENABLED()          LL_MISC_IsEnabledClockLowPower(LL_DBG)
+
+#define __HAL_RCC_XSPIPHYCOMP_IS_CLK_SLEEP_ENABLED()  LL_MISC_IsEnabledClockLowPower(LL_XSPIPHYCOMP)
+
+#define __HAL_RCC_PER_IS_CLK_SLEEP_ENABLED()          LL_MISC_IsEnabledClockLowPower(LL_PER)
+
+/**
+  * @}
+  */
+
+/** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   After enabling the HSI, the application software should wait on
+  *         HSIRDY flag to be set indicating that the HSI clock is stable
+  *         and that HSI clock can be used to clock the PLL and/or system clock.
+  * @note   HSI can not be stopped if it is used directly or through the PLL
+  *         as system clock. In this case, you have to select another source
+  *         of the system clock then stop the HSI.
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  __STATE__ specifies the new state of the HSI.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator
+  *            @arg @ref RCC_HSI_ON turn ON the HSI oscillator
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION, (uint32_t)(__STATE__))
+
+/** @brief  Macro to configure the Internal High Speed oscillator (HSI) clock divider.
+  * @param  __HSIDIV__ specifies the HSI division factor.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset)
+  *            @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2
+  *            @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4
+  *            @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8
+  */
+#define __HAL_RCC_HSI_DIVIDER_CONFIG(__HSIDIV__) LL_RCC_HSI_SetDivider((uint32_t)(__HSIDIV__))
+
+/** @brief  Macro to get the HSI divider.
+  * @retval The HSI divider. The returned value can be one of the following values:
+  *         of the following:
+  *            @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset)
+  *            @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2
+  *            @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4
+  *            @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8
+  */
+#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)LL_RCC_HSI_GetDivider())
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after start-up
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_ENABLE()  LL_RCC_HSI_Enable()
+
+#define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable()
+
+/** @brief  Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
+  *         (default is RCC_HSICALIBRATION_DEFAULT).
+  *         This parameter must be a number between 0 and 127.
+  * @retval None
+  */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
+  LL_RCC_HSI_SetCalibTrimming((uint32_t)(__HSICALIBRATIONVALUE__));
+
+/**
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+  *           in STOP mode to be quickly available as kernel clock for some peripherals.
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the HSI start-up time.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSISTOP_ENABLE()     LL_RCC_HSI_EnableInStopMode()
+
+#define __HAL_RCC_HSISTOP_DISABLE()    LL_RCC_HSI_DisableInStopMode()
+
+/**
+  * @brief  Macros to enable or disable the Internal oscillator (MSI).
+  * @note     The MSI is stopped by hardware when entering STOP and STANDBY modes.
+  *           It is used (enabled by hardware) as system clock source after
+  *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case
+  *           of failure of the HSE used directly or indirectly as system clock
+  *           (if the Clock Security System CSS is enabled).
+  * @note     MSI can not be stopped if it is used as system clock source.
+  *           In this case, you have to select another source of the system
+  *           clock then stop the MSI.
+  * @note     After enabling the MSI, the application software should wait on
+  *           MSIRDY flag to be set indicating that MSI clock is stable and can
+  *           be used as system clock source.
+  * @note     When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
+  *           clock cycles.
+  */
+#define __HAL_RCC_MSI_ENABLE()  LL_RCC_MSI_Enable()
+
+#define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable()
+
+/** @brief  Macro to configure the Internal oscillator (MSI) frequency.
+  * @param  __FREQ__ specifies the MSI frequency.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_MSI_FREQ_4MHZ  4MHz selection (default after reset)
+  *            @arg RCC_MSI_FREQ_16MHZ 16MHz selection
+  */
+#define __HAL_RCC_MSI_FREQUENCY_CONFIG(__FREQ__) LL_RCC_MSI_SetFrequency((uint32_t)(__FREQ__))
+
+/** @brief  Macro to adjust the Internal oscillator (MSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal MSI RC.
+  * @param  __MSICALIBRATIONVALUE__ specifies the calibration trimming value
+  *         (default is RCC_MSICALIBRATION_DEFAULT).
+  *         This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
+  LL_RCC_MSI_SetCalibTrimming((uint32_t)(__MSICALIBRATIONVALUE__))
+
+/**
+  * @brief  Macros to enable or disable the force of the Low-power Internal oscillator (MSI)
+  *         in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
+  * @note   Keeping the MSI ON in STOP mode allows to avoid slowing down the communication
+  *         speed because of the MSI start-up time.
+  * @note   The enable of this function has not effect on the MSION bit.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_MSISTOP_ENABLE()     LL_RCC_MSI_EnableInStopMode()
+
+#define __HAL_RCC_MSISTOP_DISABLE()    LL_RCC_MSI_DisableInStopMode()
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_LSI_ENABLE()         LL_RCC_LSI_Enable()
+
+#define __HAL_RCC_LSI_DISABLE()        LL_RCC_LSI_Disable()
+
+/**
+  * @brief  Macros to configure the External High Speed oscillator (HSE).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL),
+  *         the application software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock and peripheral kernel
+  *         clock source.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  __STATE__ specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HSE_OFF            turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                                             6 HSE oscillator clock cycles.
+  *            @arg @ref RCC_HSE_ON             turn ON the HSE oscillator.
+  *            @arg @ref RCC_HSE_BYPASS         HSE oscillator bypassed with external clock (analog).
+  *            @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed with external digital clock.
+  */
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                                                 \
+  do {                                                                  \
+    if ((__STATE__) == RCC_HSE_ON)                                      \
+    {                                                                   \
+      WRITE_REG(RCC->CSR, RCC_CSR_HSEONS);                              \
+    }                                                                   \
+    else if ((__STATE__) == RCC_HSE_OFF)                                \
+    {                                                                   \
+      WRITE_REG(RCC->CCR, RCC_CCR_HSEONC);                              \
+      CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \
+    }                                                                   \
+    else if ((__STATE__) == RCC_HSE_BYPASS)                             \
+    {                                                                   \
+      SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP);                        \
+      CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT);                      \
+      WRITE_REG(RCC->CSR, RCC_CSR_HSEONS);                              \
+    }                                                                   \
+    else if ((__STATE__) == RCC_HSE_BYPASS_DIGITAL)                     \
+    {                                                                   \
+      SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP);   \
+      WRITE_REG(RCC->CSR, RCC_CSR_HSEONS);                              \
+    }                                                                   \
+    else                                                                \
+    {                                                                   \
+      WRITE_REG(RCC->CCR, RCC_CCR_HSEONC);                              \
+      CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \
+    }                                                                   \
+  } while(0)
+
+/**
+  * @brief  Macros to configure the External Low Speed oscillator (LSE).
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+  * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).
+            A duty cycle close to 50% is recommended.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
+  * @param  __STATE__ specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_LSE_OFF            turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                                        6 LSE oscillator clock cycles.
+  *            @arg @ref RCC_LSE_ON             turn ON the LSE oscillator.
+  *            @arg @ref RCC_LSE_BYPASS         LSE oscillator bypassed with external clock (analog).
+  *            @arg @ref RCC_LSE_BYPASS_DIGITAL LSE oscillator bypassed with external digital clock.
+  */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+  do {                                               \
+    if((__STATE__) == RCC_LSE_ON)                    \
+    {                                                \
+      WRITE_REG(RCC->CSR, RCC_CSR_LSEONS);           \
+    }                                                \
+    else if((__STATE__) == RCC_LSE_OFF)              \
+    {                                                \
+      WRITE_REG(RCC->CCR, RCC_CCR_LSEONC);           \
+      CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);   \
+      CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);   \
+    }                                                \
+    else if((__STATE__) == RCC_LSE_BYPASS)           \
+    {                                                \
+      SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);     \
+      CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);   \
+      WRITE_REG(RCC->CSR, RCC_CSR_LSEONS);           \
+    }                                                \
+    else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \
+    {                                                \
+      SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);     \
+      SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);     \
+      WRITE_REG(RCC->CSR, RCC_CSR_LSEONS);           \
+    }                                                \
+    else                                             \
+    {                                                \
+      WRITE_REG(RCC->CCR, RCC_CCR_LSEONC);           \
+      CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);   \
+      CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);   \
+    }                                                \
+  } while(0)
+
+/** @brief  Macros to enable or disable the the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE()         LL_RCC_EnableRTC()
+
+#define __HAL_RCC_RTC_DISABLE()        LL_RCC_DisableRTC()
+
+/** @brief  Macro to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it cannot be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() and
+  *         __HAL_RCC_BACKUPRESET_RELEASE() macros, or by a Power On Reset (POR).
+  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            RCC_RTCCLKSOURCE_LSE      LSE selected as RTC clock.
+  *            RCC_RTCCLKSOURCE_LSI      LSI selected as RTC clock.
+  *            RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected
+  *                                      as RTC clock, where x:[1,64]
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
+  do { \
+    if (((__RTC_CLKSOURCE__) & (RCC_CCIPR7_RTCSEL)) == RCC_CCIPR7_RTCSEL) { \
+      __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
+    } \
+    LL_RCC_SetRTCClockSource((__RTC_CLKSOURCE__) & RCC_CCIPR7_RTCSEL); \
+  } while(0)
+
+/** @brief  Macro to configure the RTC clock prescaler for HSE for RTCCLK.
+  * @param  __RTC_CLKSOURCE__ specifies the RTC clock prescaler for HSE.
+  *         This parameter can be one of the following values:
+  *            RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected
+  *                                      as RTC clock, where x:[1,64]
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) \
+  LL_RCC_SetRTC_HSEPrescaler(((__RTC_CLKSOURCE__) & (~RCC_CCIPR7_RTCSEL)))
+
+/** @brief  Macros to get the RTC clock (RTCCLK).
+  * @retval The returned value can be one of the following values:
+  *            RCC_RTCCLKSOURCE_DISABLE  No clock selected as RTC clock.
+  *            RCC_RTCCLKSOURCE_LSE      LSE selected as RTC clock.
+  *            RCC_RTCCLKSOURCE_LSI      LSI selected as RTC clock.
+  *            RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected
+  *                                      as RTC clock, where x:[1,64]
+  */
+#define __HAL_RCC_GET_RTC_SOURCE() \
+  ((READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL) == RCC_CCIPR7_RTCSEL) ? \
+   (READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE) | RCC_CCIPR7_RTCSEL) : READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL))
+
+/** @brief  Macros to force or release the Vswitch backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   LL_RCC_ForceBackupDomainReset()
+
+#define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset()
+
+/** @brief  Macros to enable or disable the PLL1.
+  * @note   After enabling the PLL1, the application software should wait on
+  *         PLL1RDY flag to be set indicating that PLL1 clock is stable and can
+  *         be used as CPU and/or system bus and/or kernel clock source thru ICx.
+  * @note   The PLL1 can not be disabled if it is used as system clock source
+  * @note   The PLL1 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL1_ENABLE()        LL_RCC_PLL1_Enable()
+
+#define __HAL_RCC_PLL1_DISABLE()       LL_RCC_PLL1_Disable()
+
+/**
+  * @brief  Macros to enable or disable the PLL1 post divider 1, post divider 2
+  *         and PLL1 clock output when not in bypass mode.
+  */
+#define __HAL_RCC_PLL1CLKOUT_ENABLE()       LL_RCC_PLL1P_Enable()
+#define __HAL_RCC_PLL1CLKOUT_DISABLE()      LL_RCC_PLL1P_Disable()
+
+/**
+  * @brief  Macro to configure the PLL1 in integer mode with clock source, multiplication
+  *         and division factors.
+  * @note   This macro must be used only when the PLL1 is disabled or the PLL1 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *           This parameter can be one of the following values:
+  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry
+  * @note   This clock source cannot be changed on any PLL if another PLL is already enabled.
+  *
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock.
+  *           This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 50 MHz.
+  *
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock.
+  *           This parameter must be a number between 16 and 2500.
+  *
+  * @param  __PLLP1__ specifies the post division factor 1 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  *
+  * @param  __PLLP2__ specifies the post division factor 2 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  *
+  * @retval None
+  */
+
+#define __HAL_RCC_PLL1_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \
+  do { \
+    MODIFY_REG(RCC->PLL1CFGR1, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1BYP | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \
+               ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL1CFGR1_PLL1DIVM_Pos) | (((__PLLN__) << RCC_PLL1CFGR1_PLL1DIVN_Pos))));  \
+    MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC, 0U); \
+    MODIFY_REG(RCC->PLL1CFGR3, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \
+               ((((__PLLP1__) << RCC_PLL1CFGR3_PLL1PDIV1_Pos) & RCC_PLL1CFGR3_PLL1PDIV1) | \
+                ((((__PLLP2__) << RCC_PLL1CFGR3_PLL1PDIV2_Pos) & RCC_PLL1CFGR3_PLL1PDIV2)))); \
+  } while(0)
+
+/** @brief  Macro to configure the PLL1 clock source.
+  * @note   This macro must be used only when the PLL1 is disabled or the PLL1 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN clock selected as PLL clock entry
+  */
+#define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLLSOURCE__)  LL_RCC_PLL1_SetSource((uin32_t)__PLLSOURCE__)
+
+/** @brief  Macro to get the clock source used as PLL1 clock source.
+  * @retval The oscillator used as PLL clock source.
+  *         The returned value can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL1_OSCSOURCE()  LL_RCC_PLL1_GetSource()
+
+/**
+  * @brief  Macro to configure the PLL1 clock Fractional Part Of The Multiplication Factor
+  * @note   This configuration cannot be requested when the PLL1 has been enabled.
+  *
+  * @param  __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL1 VCO.
+  *                         It should be a value between 0 and 2^24.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL1_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL1_SetFRACN((uint32_t)(__PLLDIVNFRAC__))
+
+/**
+  * @brief  Macro to enable the PLL1 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL1 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL1_FRACN_ENABLE() LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum()
+
+/**
+  * @brief  Macro to disable the PLL1 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL1 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL1_FRACN_DISABLE() LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum()
+
+/** @brief  Macros to enable or disable PLL2.
+  * @note   After enabling PLL2, the application software should wait on
+  *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+  *         be used as CPU and/or system bus and/or kernel clock source thru ICx.
+  * @note   PLL2 is disabled by hardware when entering Stop and Standby modes.
+  */
+#define __HAL_RCC_PLL2_ENABLE()         LL_RCC_PLL2_Enable()
+#define __HAL_RCC_PLL2_DISABLE()        LL_RCC_PLL2_Disable()
+
+/**
+  * @brief  Macros to enable or disable the PLL2 post divider 1, post divider 2
+  *         and PLL2 clock output when not in bypass mode.
+  */
+#define __HAL_RCC_PLL2CLKOUT_ENABLE()       LL_RCC_PLL2P_Enable()
+#define __HAL_RCC_PLL2CLKOUT_DISABLE()      LL_RCC_PLL2P_Disable()
+
+/**
+  * @brief  Macro to configure the PLL2 in integer mode with clock source, multiplication
+  *         and division factors.
+  * @note   This macro must be used only when the PLL2 is disabled or the PLL2 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *           This parameter can be one of the following values:
+  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry
+  * @note   This clock source cannot be changed on any PLL if another PLL is already enabled.
+  *
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *           This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 50 MHz.
+  *
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *           This parameter must be a number between 16 and 2500.
+  * @param  __PLLP1__ specifies the post division factor 1 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  * @param  __PLLP2__ specifies the post division factor 2 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  *
+  * @retval None
+  */
+
+#define __HAL_RCC_PLL2_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \
+  do { \
+    MODIFY_REG(RCC->PLL2CFGR1, (RCC_PLL2CFGR1_PLL2SEL | RCC_PLL2CFGR1_PLL2BYP | RCC_PLL2CFGR1_PLL2DIVM | RCC_PLL2CFGR1_PLL2DIVN), \
+               ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL2CFGR1_PLL2DIVM_Pos) | (((__PLLN__) << RCC_PLL2CFGR1_PLL2DIVN_Pos))));  \
+    MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC, 0U); \
+    MODIFY_REG(RCC->PLL2CFGR3, (RCC_PLL2CFGR3_PLL2PDIV1 | RCC_PLL2CFGR3_PLL2PDIV2), \
+               ((((__PLLP1__) << RCC_PLL2CFGR3_PLL2PDIV1_Pos) & RCC_PLL2CFGR3_PLL2PDIV1) | \
+                ((((__PLLP2__) << RCC_PLL2CFGR3_PLL2PDIV2_Pos) & RCC_PLL2CFGR3_PLL2PDIV2)))); \
+  } while(0)
+
+
+/** @brief  Macro to configure the PLL2 clock source.
+  * @note   This macro must be used only when the PLL2 is disabled or the PLL2 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *           This parameter can be one of the following values:
+  *              @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *              @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
+  *              @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  *              @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN clock selected as PLL clock entry
+  */
+#define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL2_SetSource((uin32_t)__PLLSOURCE__)
+
+/** @brief  Macro to get the clock source used as PLL2 clock source.
+  * @retval The oscillator used as PLL clock source.
+  *         The returned value can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL2_OSCSOURCE() LL_RCC_PLL2_GetSource()
+
+/**
+  * @brief  Macro to configure the PLL2 clock Fractional Part Of The Multiplication Factor
+  * @note   This configuration cannot be requested when the PLL2 has been enabled.
+  *
+  * @param  __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL2 VCO.
+  *                         It should be a value between 0 and 2^24.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL2_SetFRACN((uint32_t)(__PLLDIVNFRAC__))
+
+/**
+  * @brief  Macro to enable the PLL2 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL2 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2_FRACN_ENABLE() LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum()
+
+/**
+  * @brief  Macro to disable the PLL2 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL2 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2_FRACN_DISABLE() LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum()
+
+/** @brief  Macros to enable or disable PLL3.
+  * @note   After enabling PLL3, the application software should wait on
+  *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can
+  *         be used as CPU and/or system bus and/or kernel clock source thru ICx.
+  * @note   PLL3 is disabled by hardware when entering Stop and Standby modes.
+  */
+#define __HAL_RCC_PLL3_ENABLE()         LL_RCC_PLL3_Enable()
+#define __HAL_RCC_PLL3_DISABLE()        LL_RCC_PLL3_Disable()
+
+/**
+  * @brief  Macros to enable or disable the PLL3 post divider 1, post divider 2
+  *         and PLL3 clock output when not in bypass mode.
+  */
+#define __HAL_RCC_PLL3CLKOUT_ENABLE()       LL_RCC_PLL3P_Enable()
+#define __HAL_RCC_PLL3CLKOUT_DISABLE()      LL_RCC_PLL3P_Disable()
+
+/**
+  * @brief  Macro to configure the PLL3 in integer mode with clock source, multiplication
+  *         and division factors.
+  * @note   This macro must be used only when the PLL3 is disabled or the PLL3 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *           This parameter can be one of the following values:
+  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry
+  * @note   This clock source cannot be changed on any PLL if another PLL is already enabled.
+  *
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *           This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 50 MHz.
+  *
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *           This parameter must be a number between 16 and 2500.
+  * @param  __PLLP1__ specifies the post division factor 1 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  * @param  __PLLP2__ specifies the post division factor 2 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  *
+  * @retval None
+  */
+
+#define __HAL_RCC_PLL3_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \
+  do { \
+    MODIFY_REG(RCC->PLL3CFGR1, (RCC_PLL3CFGR1_PLL3SEL | RCC_PLL3CFGR1_PLL3BYP | RCC_PLL3CFGR1_PLL3DIVM | RCC_PLL3CFGR1_PLL3DIVN), \
+               ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL3CFGR1_PLL3DIVM_Pos) | (((__PLLN__) << RCC_PLL3CFGR1_PLL3DIVN_Pos))));  \
+    MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC, 0U); \
+    MODIFY_REG(RCC->PLL3CFGR3, (RCC_PLL3CFGR3_PLL3PDIV1 | RCC_PLL3CFGR3_PLL3PDIV2), \
+               ((((__PLLP1__) << RCC_PLL3CFGR3_PLL3PDIV1_Pos) & RCC_PLL3CFGR3_PLL3PDIV1) | \
+                ((((__PLLP2__) << RCC_PLL3CFGR3_PLL3PDIV2_Pos) & RCC_PLL3CFGR3_PLL3PDIV2)))); \
+  } while(0)
+
+
+/** @brief  Macro to configure the PLL3 clock source.
+  * @note   This macro must be used only when the PLL3 is disabled or the PLL3 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *           This parameter can be one of the following values:
+  *              @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *              @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
+  *              @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  *              @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN clock selected as PLL clock entry
+  */
+#define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL3_SetSource((uin32_t)__PLLSOURCE__)
+
+/** @brief  Macro to get the clock source used as PLL3 clock source.
+  * @retval The oscillator used as PLL clock source.
+  *         The returned value can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL3_OSCSOURCE() LL_RCC_PLL3_GetSource()
+
+/**
+  * @brief  Macro to configure the PLL3 clock Fractional Part Of The Multiplication Factor
+  * @note   This configuration cannot be requested when the PLL3 has been enabled.
+  *
+  * @param  __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO.
+  *                         It should be a value between 0 and 2^24.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL3_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL3_SetFRACN((uint32_t)(__PLLDIVNFRAC__))
+
+/**
+  * @brief  Macro to enable the PLL3 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL3 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL3_FRACN_ENABLE() LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum()
+
+/**
+  * @brief  Macro to disable the PLL3 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL3 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL3_FRACN_DISABLE() LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum()
+
+/** @brief  Macros to enable or disable PLL4.
+  * @note   After enabling PLL4, the application software should wait on
+  *         PLL4RDY flag to be set indicating that PLL4 clock is stable and can
+  *         be used as CPU and/or system bus and/or kernel clock source thru ICx.
+  * @note   PLL4 is disabled by hardware when entering Stop and Standby modes.
+  */
+#define __HAL_RCC_PLL4_ENABLE()         LL_RCC_PLL4_Enable()
+#define __HAL_RCC_PLL4_DISABLE()        LL_RCC_PLL4_Disable()
+
+/**
+  * @brief  Macros to enable or disable the PLL4 post divider 1, post divider 2
+  *         and PLL4 clock output when not in bypass mode.
+  */
+#define __HAL_RCC_PLL4CLKOUT_ENABLE()       LL_RCC_PLL4P_Enable()
+#define __HAL_RCC_PLL4CLKOUT_DISABLE()      LL_RCC_PLL4P_Disable()
+
+/**
+  * @brief  Macro to configure the PLL4 in integer mode with clock source, multiplication
+  *         and division factors.
+  * @note   This macro must be used only when the PLL4 is disabled or the PLL4 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  *
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *           This parameter can be one of the following values:
+  *             @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+  *             @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry
+  * @note   This clock source cannot be changed on any PLL if another PLL is already enabled.
+  *
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *           This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 50 MHz.
+  *
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *           This parameter must be a number between 16 and 2500.
+  * @param  __PLLP1__ specifies the post division factor 1 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  * @param  __PLLP2__ specifies the post division factor 2 for system  clock.
+  *           This parameter must be a number between 1 and 7.
+  *
+  * @retval None
+  */
+
+#define __HAL_RCC_PLL4_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \
+  do { \
+    MODIFY_REG(RCC->PLL4CFGR1, (RCC_PLL4CFGR1_PLL4SEL | RCC_PLL4CFGR1_PLL4BYP | RCC_PLL4CFGR1_PLL4DIVM | RCC_PLL4CFGR1_PLL4DIVN), \
+               ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL4CFGR1_PLL4DIVM_Pos) | (((__PLLN__) << RCC_PLL4CFGR1_PLL4DIVN_Pos))));  \
+    MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC, 0U); \
+    MODIFY_REG(RCC->PLL4CFGR3, (RCC_PLL4CFGR3_PLL4PDIV1 | RCC_PLL4CFGR3_PLL4PDIV2), \
+               ((((__PLLP1__) << RCC_PLL4CFGR3_PLL4PDIV1_Pos) & RCC_PLL4CFGR3_PLL4PDIV1) | \
+                ((((__PLLP2__) << RCC_PLL4CFGR3_PLL4PDIV2_Pos) & RCC_PLL4CFGR3_PLL4PDIV2)))); \
+  } while(0)
+
+
+/** @brief  Macro to configure the PLL4 clock source.
+  * @note   This macro must be used only when the PLL4 is disabled or the PLL4 output is bypassed
+  *         and driven by the PLL reference clock. This macro switches off the bypass mode.
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN clock selected as PLL clock entry
+  */
+#define __HAL_RCC_PLL4_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL4_SetSource((uin32_t)__PLLSOURCE__)
+
+/** @brief  Macro to get the clock source used as PLL4 clock source.
+  * @retval The oscillator used as PLL clock source.
+  *         The returned value can be one of the following values:
+  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator is used as PLL clock source.
+  *            @arg @ref RCC_PLLSOURCE_PIN  External I2S_CKIN is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL4_OSCSOURCE() LL_RCC_PLL4_GetSource()
+
+/**
+  * @brief  Macro to configure the PLL4 clock Fractional Part Of The Multiplication Factor
+  * @note   This configuration cannot be requested when the PLL4 has been enabled.
+  *
+  * @param  __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL4 VCO.
+  *                         It should be a value between 0 and 2^24.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL4_DIVNFRAC_CONFIG(__PLLDIVNFRAC__)  LL_RCC_PLL4_SetFRACN((uint32_t)(__PLLDIVNFRAC__))
+
+/**
+  * @brief  Macro to enable the PLL4 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL4 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL4_FRACN_ENABLE() LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum()
+
+
+/**
+  * @brief  Macro to disable the PLL4 clock Fractional mode
+  * @note   This configuration cannot be requested when the PLL4 has been enabled.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL4_FRACN_DISABLE()  LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum()
+
+/**
+  * @brief Macro to configure the CPU clock source.
+  * @param  __CPUCLKSOURCE__ specifies the CPU clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_CPUCLKSOURCE_HSI    HSI oscillator is used as CPU clock source.
+  *            @arg @ref RCC_CPUCLKSOURCE_MSI    MSI oscillator is used as CPU clock source.
+  *            @arg @ref RCC_CPUCLKSOURCE_HSE    HSE oscillator is used as CPU clock source.
+  *            @arg @ref RCC_CPUCLKSOURCE_IC1    IC1 output is used as CPU clock source.
+  * @retval None
+  */
+#define __HAL_RCC_CPUCLK_CONFIG(__CPUCLKSOURCE__) LL_RCC_SetCpuClkSource((uint32_t)(__CPUCLKSOURCE__))
+
+/** @brief  Macro to get the clock source used as CPU clock.
+  * @retval The clock source used as CPU clock.
+  *         The returned value can be one of the following values:
+  *            @arg @ref RCC_CPUCLKSOURCE_STATUS_HSI    HSI used as CPU clock.
+  *            @arg @ref RCC_CPUCLKSOURCE_STATUS_MSI    MSI used as CPU clock.
+  *            @arg @ref RCC_CPUCLKSOURCE_STATUS_HSE    HSE used as CPU clock.
+  *            @arg @ref RCC_CPUCLKSOURCE_STATUS_IC1    IC1 used as CPU clock.
+  */
+#define __HAL_RCC_GET_CPUCLK_SOURCE() LL_RCC_GetCpuClkSource()
+
+
+/**
+  * @brief Macro to configure the system bus clock source.
+  * @param  __SYSCLKSOURCE__ specifies the system clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_SYSCLKSOURCE_HSI           HSI oscillator is used as system bus clock source.
+  *            @arg @ref RCC_SYSCLKSOURCE_MSI           MSI oscillator is used as system bus clock source.
+  *            @arg @ref RCC_SYSCLKSOURCE_HSE           HSE oscillator is used as system bus clock source.
+  *            @arg @ref RCC_SYSCLKSOURCE_IC2_IC6_IC11  IC2, IC6 and IC11 outputs are used as system bus clock source.
+  * @retval None
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource((uint32_t)(__SYSCLKSOURCE__))
+
+/** @brief  Macro to get the clock source used as system bus clock.
+  * @retval The clock source used as system clock.
+  *         The returned value can be one of the following values:
+  *            @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI           HSI used as system bus clock.
+  *            @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI           MSI used as system bus clock.
+  *            @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE           HSE used as system bus clock.
+  *            @arg @ref RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11  IC2, IC6 and IC11 outputs used as system bus clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource()
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   This parameter cannot be updated while LSE is ON.
+  * @param  __LSEDRIVE__ specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_LSEDRIVE_LOW        LSE oscillator low drive capability.
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
+  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
+  *            @arg @ref RCC_LSEDRIVE_HIGH       LSE oscillator high drive capability.
+  * @retval None
+  */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability((uint32_t)(__LSEDRIVE__))
+
+/**
+  * @brief  Macro to configure the wake up from stop clock.
+  * @param  __STOPWUCLK__ specifies the clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
+  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
+  * @retval None
+  */
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetSysWakeUpClkSource((uint32_t)(__STOPWUCLK__))
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{
+  */
+
+/**
+  * @brief  Macros to enable or disable the MCO1 clock output
+  * @retval None
+  */
+#define __HAL_RCC_MCO1_ENABLE()     LL_RCC_EnableMCO(LL_RCC_MCO1)
+
+#define __HAL_RCC_MCO1_DISABLE()    LL_RCC_DisableMCO(LL_RCC_MCO1)
+
+/**
+  * @brief  Macros to enable or disable the MCO2 clock output
+  * @retval None
+  */
+#define __HAL_RCC_MCO2_ENABLE()     LL_RCC_EnableMCO(LL_RCC_MCO2)
+
+#define __HAL_RCC_MCO2_DISABLE()    LL_RCC_DisableMCO(LL_RCC_MCO2)
+
+
+/** @brief  Macro to configure the MCO1 clock.
+  * @note   MCO1 clock output shall be enabled with __HAL_RCC_MCO1_ENABLE()
+  * @note   The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch).
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCO1SOURCE_HSI       HSI clock selected as MCO1 source
+  *            @arg @ref RCC_MCO1SOURCE_LSE       LSE clock selected as MCO1 source
+  *            @arg @ref RCC_MCO1SOURCE_MSI       MSI clock selected as MCO1 source
+  *            @arg @ref RCC_MCO1SOURCE_LSI       LSI clock selected as MCO1 source
+  *            @arg @ref RCC_MCO1SOURCE_HSE       HSE clock selected as MCO1 source
+  *            @arg @ref RCC_MCO1SOURCE_IC5       IC5 clock selected as MCO1 source
+  *            @arg @ref RCC_MCO1SOURCE_IC10      IC10 clock selected as MCO1 source
+  *            @arg @ref RCC_MCO1SOURCE_SYSA      SYSA CPU clock selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_16  : divider applied to MCO1 clock
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO(__MCOCLKSOURCE__, __MCODIV__)
+
+/** @brief  Macro to configure the MCO2 clock.
+  * @note   MCO2 clock output shall be enabled with __HAL_RCC_MCO2_ENABLE()
+  * @note   The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch).
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCO2SOURCE_HSI       HSI clock selected as MCO2 source
+  *            @arg @ref RCC_MCO2SOURCE_LSE       LSE clock selected as MCO2 source
+  *            @arg @ref RCC_MCO2SOURCE_MSI       MSI clock selected as MCO2 source
+  *            @arg @ref RCC_MCO2SOURCE_LSI       LSI clock selected as MCO2 source
+  *            @arg @ref RCC_MCO2SOURCE_HSE       HSE clock selected as MCO2 source
+  *            @arg @ref RCC_MCO2SOURCE_IC15      IC15 clock selected as MCO2 source
+  *            @arg @ref RCC_MCO2SOURCE_IC20      IC20 clock selected as MCO2 source
+  *            @arg @ref RCC_MCO2SOURCE_SYSB      SYSB bus clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_16  : divider applied to MCO2 clock
+  */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO(__MCOCLKSOURCE__, __MCODIV__)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+/** @brief  Enable RCC interrupt.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY   LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY   MSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt
+  *            @arg @ref RCC_IT_PLL1RDY  PLL1 ready interrupt
+  *            @arg @ref RCC_IT_PLL2RDY  PLL2 ready interrupt
+  *            @arg @ref RCC_IT_PLL3RDY  PLL3 ready interrupt
+  *            @arg @ref RCC_IT_PLL4RDY  PLL4 ready interrupt
+  *            @arg @ref RCC_IT_LSECSS   LSE clock security system interrupt
+  *            @arg @ref RCC_IT_HSECSS   HSE clock security system interrupt
+  *            @arg @ref RCC_IT_WKUP     CPU wakeup interrupt
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Disable RCC interrupt.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY   LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY   MSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt
+  *            @arg @ref RCC_IT_PLL1RDY  PLL1 ready interrupt
+  *            @arg @ref RCC_IT_PLL2RDY  PLL2 ready interrupt
+  *            @arg @ref RCC_IT_PLL3RDY  PLL3 ready interrupt
+  *            @arg @ref RCC_IT_PLL4RDY  PLL4 ready interrupt
+  *            @arg @ref RCC_IT_LSECSS   LSE clock security system interrupt
+  *            @arg @ref RCC_IT_HSECSS   HSE clock security system interrupt
+  *            @arg @ref RCC_IT_WKUP     CPU wakeup interrupt
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RCC_IT_LSIRDY   LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY   MSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt
+  *            @arg @ref RCC_IT_PLL1RDY  PLL1 ready interrupt
+  *            @arg @ref RCC_IT_PLL2RDY  PLL2 ready interrupt
+  *            @arg @ref RCC_IT_PLL3RDY  PLL3 ready interrupt
+  *            @arg @ref RCC_IT_PLL4RDY  PLL4 ready interrupt
+  *            @arg @ref RCC_IT_LSECSS   LSE clock security system interrupt
+  *            @arg @ref RCC_IT_HSECSS   HSE clock security interrupt
+  *            @arg @ref RCC_IT_WKUP     CPU wakeup interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
+
+/** @brief  Check whether the RCC interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_IT_LSIRDY   LSI ready interrupt
+  *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt
+  *            @arg @ref RCC_IT_MSIRDY   MSI ready interrupt
+  *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt
+  *            @arg @ref RCC_IT_PLL1RDY  PLL1 ready interrupt
+  *            @arg @ref RCC_IT_PLL2RDY  PLL2 ready interrupt
+  *            @arg @ref RCC_IT_PLL3RDY  PLL3 ready interrupt
+  *            @arg @ref RCC_IT_PLL4RDY  PLL4 ready interrupt
+  *            @arg @ref RCC_IT_LSECSS   LSE clock security system interrupt
+  *            @arg @ref RCC_IT_HSECSS   HSE clock security interrupt
+  *            @arg @ref RCC_IT_WKUP     CPU wakeup interrupt
+  * @retval The pending state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+  *        The reset flags are: RCC_FLAG_LCKRST, RCC_FLAG_BORRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags()
+
+/** @brief  Check whether the selected RCC flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_FLAG_LCKRST   CPU lockup reset flag
+  *            @arg @ref RCC_FLAG_BORRST   BOR reset flag
+  *            @arg @ref RCC_FLAG_PINRST   Pin reset flag
+  *            @arg @ref RCC_FLAG_PORRST   Power-on reset flag
+  *            @arg @ref RCC_FLAG_SFTRST   Software reset flag
+  *            @arg @ref RCC_FLAG_IWDGRST  Independent Watchdog reset flag
+  *            @arg @ref RCC_FLAG_WWDGRST  Window Watchdog reset flag
+  *            @arg @ref RCC_FLAG_LPWRRST  Low Power reset flag
+  *            @arg @ref RCC_FLAG_LSECSSD  Clock security system failure on LSE oscillator detection flag
+  *            @arg @ref RCC_FLAG_HSECSSD  Clock security system failure on HSE oscillator detection flag
+  *            @arg @ref RCC_FLAG_LSIRDY   LSI oscillator clock ready flag
+  *            @arg @ref RCC_FLAG_LSERDY   LSE oscillator clock ready flag
+  *            @arg @ref RCC_FLAG_HSIRDY   HSI oscillator clock ready flag
+  *            @arg @ref RCC_FLAG_MSIRDY   MSI oscillator clock ready flag
+  *            @arg @ref RCC_FLAG_HSERDY   HSE oscillator clock ready flag
+  *            @arg @ref RCC_FLAG_PLL1RDY  PLL1 ready flag
+  *            @arg @ref RCC_FLAG_PLL2RDY  PLL2 ready flag
+  *            @arg @ref RCC_FLAG_PLL3RDY  PLL3 ready flag
+  *            @arg @ref RCC_FLAG_PLL4RDY  PLL4 ready flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == RCC_RSR_REG_INDEX)     ? RCC->RSR :                   \
+                                          ((((__FLAG__) >> 5U) == RCC_LSECFGR_REG_INDEX) ? RCC->LSECFGR :              \
+                                           ((((__FLAG__) >> 5U) == RCC_HSECFGR_REG_INDEX) ? RCC->HSECFGR : RCC->SR)))) \
+                                        & (1UL << ((__FLAG__) & RCC_FLAG_POS_MASK))) != 0U) ? 1U : 0U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Attributes_Management Attribute Management
+  * @brief macros to manage the RCC Attributes.
+  * @{
+  */
+
+/** @brief  Check whether an item attribute is secured
+  * @param  __ATTRIBUTES__ specifies the item attributes
+  *         This parameter is a combination of @ref RCC_attributes
+  * @retval 1 if the item attribute is secured, 0 otherwise.
+  */
+#define HAL_RCC_ATTRIBUTES_IS_SEC(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_SEC) == RCC_ATTR_SEC) ? 1U : 0U)
+
+/** @brief  Check whether an item attribute is privileged
+  * @param  __ATTRIBUTES__ specifies the item attributes
+  *         This parameter is a combination of @ref RCC_attributes
+  * @retval 1 if the item attribute is privileged, 0 otherwise.
+  */
+#define HAL_RCC_ATTRIBUTES_IS_PRIV(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) ? 1U : 0U)
+
+/** @brief  Check whether an item attribute is public
+  * @param  __ATTRIBUTES__ specifies the item attributes
+  *         This parameter is a combination of @ref RCC_attributes
+  * @retval 1 if the item attribute is public, 0 otherwise.
+  */
+#define HAL_RCC_ATTRIBUTES_IS_PUB(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_PUB) == RCC_ATTR_PUB) ? 1U : 0U)
+
+/** @brief  Check whether an item attribute is locked
+  * @param  __ATTRIBUTES__ specifies the item attributes
+  *         This parameter is a combination of @ref RCC_attributes
+  * @retval 1 if the item attribute is locked, 0 otherwise.
+  */
+#define HAL_RCC_ATTRIBUTES_IS_LOCK(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_LOCK) == RCC_ATTR_LOCK) ? 1U : 0U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extension module */
+#include "stm32n6xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *pRCC_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+uint32_t HAL_RCC_GetCpuClockFreq(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+uint32_t HAL_RCC_GetPCLK4Freq(void);
+uint32_t HAL_RCC_GetPCLK5Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct);
+/* CSS NMI IRQ handler */
+void     HAL_RCC_NMI_IRQHandler(void);
+/* User callback in non blocking mode (IT mode) */
+void     HAL_RCC_CSSCallback(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group3
+  * @{
+  */
+/* Attributes management functions ********************************************/
+void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes);
+HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+#define RCC_LSE_TIMEOUT_VALUE     LSE_STARTUP_TIMEOUT
+#define RCC_PLL_TIMEOUT_VALUE     1U    /* 1 ms */
+
+/* Defines used for Flags */
+#define RCC_SR_REG_INDEX          1U
+#define RCC_LSECFGR_REG_INDEX     2U
+#define RCC_HSECFGR_REG_INDEX     3U
+#define RCC_RSR_REG_INDEX         4U
+#define RCC_FLAG_POS_MASK         0x0000001FU
+
+/* Defines RCC privilege/secure/public/lock attribute masks */
+#define RCC_ATTR_PRIV_MASK     (0x00000002U)    /* RCC privilege mask               */
+#define RCC_ATTR_SEC_MASK      (0x00000008U)    /* RCC secure mask                  */
+#define RCC_ATTR_PUB_MASK      (0x00000020U)    /* RCC public mask                  */
+#define RCC_ATTR_LOCK_MASK     (0x00000080U)    /* RCC lock mask                    */
+
+/* Defines RCC item groups masks */
+/* Item ID are masked with item group to get an unique ID
+   31           24            16           8             0
+   --------------------------------------------------------
+   | Item Group |               Item                       |
+   --------------------------------------------------------*/
+#define RCC_ITEM_GROUP_POS          24UL
+#define RCC_ITEM_GROUP_MASK         0xFF000000UL
+#define RCC_ITEM_MASK               0x00FFFFFFUL
+#define RCC_ITEM_GROUP_OSC          0x01000000UL
+#define RCC_ITEM_GROUP_PLL          0x02000000UL
+#define RCC_ITEM_GROUP_IC           0x04000000UL
+#define RCC_ITEM_GROUP_SYSCFG       0x08000000UL
+#define RCC_ITEM_GROUP_BUS          0x10000000UL
+#define RCC_ITEM_GROUP_MEM          0x20000000UL
+
+#define RCC_ITEM_GROUP_OSC_MASK     0x0000001FUL
+#define RCC_ITEM_GROUP_PLL_MASK     0x0000000FUL
+#define RCC_ITEM_GROUP_IC_MASK      0x000FFFFFUL
+#define RCC_ITEM_GROUP_SYSCFG_MASK  0x0000003FUL
+#define RCC_ITEM_GROUP_BUS_MASK     0x00003FFFUL
+#define RCC_ITEM_GROUP_MEM_MASK     0x00000FFFUL
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros
+  * @{
+  */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF)    || ((__HSE__) == RCC_HSE_ON) || \
+                             ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL))
+
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF)    || ((__LSE__) == RCC_LSE_ON) || \
+                             ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL))
+
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF)     || ((__HSI__) == RCC_HSI_ON))
+
+#define IS_RCC_HSI_DIV(__HSI__) (((__HSI__) == RCC_HSI_DIV1) || ((__HSI__) == RCC_HSI_DIV2) || \
+                                 ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_DIV8))
+
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+
+#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
+
+#define IS_RCC_MSI_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == RCC_MSI_FREQ_4MHZ) ||\
+                                             ((__FREQUENCY__) == RCC_MSI_FREQ_16MHZ))
+
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || \
+                             ((__PLL__) == RCC_PLL_OFF)  || \
+                             ((__PLL__) == RCC_PLL_ON)   || \
+                             ((__PLL__) == RCC_PLL_BYPASS))
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE) || \
+                                      ((__SOURCE__) == RCC_PLLSOURCE_PIN))
+
+#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
+
+#define IS_RCC_PLLN_VALUE(__VALUE__) ((10U <= (__VALUE__)) && ((__VALUE__) <= 2500U))
+
+#define IS_RCC_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 7U))
+
+#define IS_RCC_PLLFRACN_VALUE(__VALUE__) ((__VALUE__) <= (RCC_PLL1CFGR2_PLL1DIVNFRAC >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos))
+
+#define IS_RCC_CLOCKTYPE(__CLK__) ((__CLK__) <= 0x7FU)
+
+#define IS_RCC_CPUCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_CPUCLKSOURCE_HSI) || \
+                                         ((__SOURCE__) == RCC_CPUCLKSOURCE_MSI) || \
+                                         ((__SOURCE__) == RCC_CPUCLKSOURCE_HSE) || \
+                                         ((__SOURCE__) == RCC_CPUCLKSOURCE_IC1))
+
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_IC2_IC6_IC11))
+
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_HCLK_DIV1)   || ((__HCLK__) == RCC_HCLK_DIV2)  || \
+                               ((__HCLK__) == RCC_HCLK_DIV4)   || ((__HCLK__) == RCC_HCLK_DIV8)  || \
+                               ((__HCLK__) == RCC_HCLK_DIV16)  || ((__HCLK__) == RCC_HCLK_DIV32) || \
+                               ((__HCLK__) == RCC_HCLK_DIV64)  || ((__HCLK__) == RCC_HCLK_DIV128))
+
+#define IS_RCC_PCLK1(__PCLK1__) (((__PCLK1__) == RCC_APB1_DIV1)  || ((__PCLK1__) == RCC_APB1_DIV2)  || \
+                                 ((__PCLK1__) == RCC_APB1_DIV4)  || ((__PCLK1__) == RCC_APB1_DIV8)  || \
+                                 ((__PCLK1__) == RCC_APB1_DIV16) || ((__PCLK1__) == RCC_APB1_DIV32) || \
+                                 ((__PCLK1__) == RCC_APB1_DIV64) || ((__PCLK1__) == RCC_APB1_DIV128))
+
+#define IS_RCC_PCLK2(__PCLK2__) (((__PCLK2__) == RCC_APB2_DIV1)  || ((__PCLK2__) == RCC_APB2_DIV2) || \
+                                 ((__PCLK2__) == RCC_APB2_DIV4)  || ((__PCLK2__) == RCC_APB2_DIV8) || \
+                                 ((__PCLK2__) == RCC_APB2_DIV16) || ((__PCLK2__) == RCC_APB2_DIV32) || \
+                                 ((__PCLK2__) == RCC_APB2_DIV64) || ((__PCLK2__) == RCC_APB2_DIV128))
+
+#define IS_RCC_PCLK4(__PCLK4__) (((__PCLK4__) == RCC_APB4_DIV1)  || ((__PCLK4__) == RCC_APB4_DIV2) || \
+                                 ((__PCLK4__) == RCC_APB4_DIV4)  || ((__PCLK4__) == RCC_APB4_DIV8) || \
+                                 ((__PCLK4__) == RCC_APB4_DIV16) || ((__PCLK4__) == RCC_APB4_DIV32) || \
+                                 ((__PCLK4__) == RCC_APB4_DIV64) || ((__PCLK4__) == RCC_APB4_DIV128))
+
+#define IS_RCC_PCLK5(__PCLK5__) (((__PCLK5__) == RCC_APB5_DIV1)  || ((__PCLK5__) == RCC_APB5_DIV2) || \
+                                 ((__PCLK5__) == RCC_APB5_DIV4)  || ((__PCLK5__) == RCC_APB5_DIV8) || \
+                                 ((__PCLK5__) == RCC_APB5_DIV16) || ((__PCLK5__) == RCC_APB5_DIV32) || \
+                                 ((__PCLK5__) == RCC_APB5_DIV64) || ((__PCLK5__) == RCC_APB5_DIV128))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)       || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)       || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1)  || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2)  || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3)  || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4)  || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5)  || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6)  || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7)  || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8)  || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9)  || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV33) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV34) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV35) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV36) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV37) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV38) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV39) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV40) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV41) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV42) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV43) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV44) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV45) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV46) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV47) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV48) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV49) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV50) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV51) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV52) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV53) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV54) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV55) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV56) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV57) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV58) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV59) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV60) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV61) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV62) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV63) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV64))
+
+#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_LSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_LSE)  || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI)  || ((__SOURCE__) == RCC_MCO1SOURCE_HSI)  || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO1SOURCE_IC5)  || \
+                                       ((__SOURCE__) == RCC_MCO1SOURCE_IC10) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSA))
+
+#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_LSI)  || ((__SOURCE__) == RCC_MCO2SOURCE_LSE)  || \
+                                       ((__SOURCE__) == RCC_MCO2SOURCE_MSI)  || ((__SOURCE__) == RCC_MCO2SOURCE_HSI)  || \
+                                       ((__SOURCE__) == RCC_MCO2SOURCE_HSE)  || ((__SOURCE__) == RCC_MCO2SOURCE_IC15) || \
+                                       ((__SOURCE__) == RCC_MCO2SOURCE_IC20) || ((__SOURCE__) == RCC_MCO2SOURCE_SYSB))
+
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)  || ((__DIV__) == RCC_MCODIV_2)   || \
+                                ((__DIV__) == RCC_MCODIV_3)  || ((__DIV__) == RCC_MCODIV_4)   || \
+                                ((__DIV__) == RCC_MCODIV_5)  || ((__DIV__) == RCC_MCODIV_6)   || \
+                                ((__DIV__) == RCC_MCODIV_7)  || ((__DIV__) == RCC_MCODIV_8)   || \
+                                ((__DIV__) == RCC_MCODIV_9)  || ((__DIV__) == RCC_MCODIV_10)  || \
+                                ((__DIV__) == RCC_MCODIV_11) || ((__DIV__) == RCC_MCODIV_12)  || \
+                                ((__DIV__) == RCC_MCODIV_13) || ((__DIV__) == RCC_MCODIV_14)  || \
+                                ((__DIV__) == RCC_MCODIV_15) || ((__DIV__) == RCC_MCODIV_16))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU)
+
+#define IS_RCC_MSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
+
+#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
+                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
+
+#define IS_RCC_ICCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ICCLKSOURCE_PLL1) || \
+                                        ((__SOURCE__) == RCC_ICCLKSOURCE_PLL2) || \
+                                        ((__SOURCE__) == RCC_ICCLKSOURCE_PLL3)  || \
+                                        ((__SOURCE__) == RCC_ICCLKSOURCE_PLL4))
+
+#define IS_RCC_ICCLKDIVIDER(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 256U))
+
+#define IS_RCC_ITEM_ATTRIBUTES(ITEM)  ((((ITEM) & RCC_ITEM_ALL) != 0U) && (((ITEM) & ~RCC_ITEM_ALL) == 0U))
+
+#define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_ITEM_LSI)         || \
+                                             ((ITEM) == RCC_ITEM_LSE)         || \
+                                             ((ITEM) == RCC_ITEM_MSI)         || \
+                                             ((ITEM) == RCC_ITEM_HSI)         || \
+                                             ((ITEM) == RCC_ITEM_HSE)         || \
+                                             ((ITEM) == RCC_ITEM_PLL1)        || \
+                                             ((ITEM) == RCC_ITEM_PLL2)        || \
+                                             ((ITEM) == RCC_ITEM_PLL3)        || \
+                                             ((ITEM) == RCC_ITEM_PLL4)        || \
+                                             ((ITEM) == RCC_ITEM_IC1)         || \
+                                             ((ITEM) == RCC_ITEM_IC2)         || \
+                                             ((ITEM) == RCC_ITEM_IC3)         || \
+                                             ((ITEM) == RCC_ITEM_IC4)         || \
+                                             ((ITEM) == RCC_ITEM_IC5)         || \
+                                             ((ITEM) == RCC_ITEM_IC6)         || \
+                                             ((ITEM) == RCC_ITEM_IC7)         || \
+                                             ((ITEM) == RCC_ITEM_IC8)         || \
+                                             ((ITEM) == RCC_ITEM_IC9)         || \
+                                             ((ITEM) == RCC_ITEM_IC10)        || \
+                                             ((ITEM) == RCC_ITEM_IC11)        || \
+                                             ((ITEM) == RCC_ITEM_IC12)        || \
+                                             ((ITEM) == RCC_ITEM_IC13)        || \
+                                             ((ITEM) == RCC_ITEM_IC14)        || \
+                                             ((ITEM) == RCC_ITEM_IC15)        || \
+                                             ((ITEM) == RCC_ITEM_IC16)        || \
+                                             ((ITEM) == RCC_ITEM_IC17)        || \
+                                             ((ITEM) == RCC_ITEM_IC18)        || \
+                                             ((ITEM) == RCC_ITEM_IC19)        || \
+                                             ((ITEM) == RCC_ITEM_IC20)        || \
+                                             ((ITEM) == RCC_ITEM_MOD)         || \
+                                             ((ITEM) == RCC_ITEM_SYS)         || \
+                                             ((ITEM) == RCC_ITEM_BUS)         || \
+                                             ((ITEM) == RCC_ITEM_PER)         || \
+                                             ((ITEM) == RCC_ITEM_INT)         || \
+                                             ((ITEM) == RCC_ITEM_RST)         || \
+                                             ((ITEM) == RCC_ITEM_ACLKN)       || \
+                                             ((ITEM) == RCC_ITEM_ACLKNC)      || \
+                                             ((ITEM) == RCC_ITEM_AHBM)        || \
+                                             ((ITEM) == RCC_ITEM_AHB1)        || \
+                                             ((ITEM) == RCC_ITEM_AHB2)        || \
+                                             ((ITEM) == RCC_ITEM_AHB3)        || \
+                                             ((ITEM) == RCC_ITEM_AHB4)        || \
+                                             ((ITEM) == RCC_ITEM_AHB5)        || \
+                                             ((ITEM) == RCC_ITEM_APB1)        || \
+                                             ((ITEM) == RCC_ITEM_APB2)        || \
+                                             ((ITEM) == RCC_ITEM_APB3)        || \
+                                             ((ITEM) == RCC_ITEM_APB4)        || \
+                                             ((ITEM) == RCC_ITEM_APB5)        || \
+                                             ((ITEM) == RCC_ITEM_NOC)         || \
+                                             ((ITEM) == RCC_ITEM_AXISRAM3)    || \
+                                             ((ITEM) == RCC_ITEM_AXISRAM4)    || \
+                                             ((ITEM) == RCC_ITEM_AXISRAM5)    || \
+                                             ((ITEM) == RCC_ITEM_AXISRAM6)    || \
+                                             ((ITEM) == RCC_ITEM_AHBSRAM1)    || \
+                                             ((ITEM) == RCC_ITEM_AHBSRAM2)    || \
+                                             ((ITEM) == RCC_ITEM_BKPSRAM)     || \
+                                             ((ITEM) == RCC_ITEM_AXISRAM1)    || \
+                                             ((ITEM) == RCC_ITEM_AXISRAM2)    || \
+                                             ((ITEM) == RCC_ITEM_FLEXRAM)     || \
+                                             ((ITEM) == RCC_ITEM_CACHEAXIRAM) || \
+                                             ((ITEM) == RCC_ITEM_VENCRAM))
+
+
+#if defined (CPU_IN_SECURE_STATE)
+#define IS_RCC_ATTRIBUTES(ATTRIBUTE) (((((ATTRIBUTE) & RCC_ATTR_SEC) == RCC_ATTR_SEC)        || \
+                                       (((ATTRIBUTE) & RCC_ATTR_NSEC) == RCC_ATTR_NSEC)      || \
+                                       (((ATTRIBUTE) & RCC_ATTR_PRIV) == RCC_ATTR_PRIV)      || \
+                                       (((ATTRIBUTE) & RCC_ATTR_NPRIV) == RCC_ATTR_NPRIV)    || \
+                                       (((ATTRIBUTE) & RCC_ATTR_PUB)  == RCC_ATTR_PUB)       || \
+                                       (((ATTRIBUTE) & RCC_ATTR_NPUB) == RCC_ATTR_NPUB)      || \
+                                       (((ATTRIBUTE) & RCC_ATTR_LOCK) == RCC_ATTR_LOCK))     && \
+                                      (((ATTRIBUTE) & ~(RCC_ATTR_SEC|RCC_ATTR_NSEC|RCC_ATTR_PRIV|RCC_ATTR_NPRIV|\
+                                                        RCC_ATTR_PUB|RCC_ATTR_NPUB|RCC_ATTR_LOCK)) == 0U))
+#else
+#define IS_RCC_ATTRIBUTES(ATTRIBUTE) (((((ATTRIBUTE) & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) || \
+                                       (((ATTRIBUTE) & RCC_ATTR_NPRIV) == RCC_ATTR_NPRIV)) && \
+                                      (((ATTRIBUTE) & ~(RCC_ATTR_PRIV|RCC_ATTR_NPRIV)) == 0U))
+
+#endif /* CPU_IN_SECURE_STATE */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_RCC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rcc_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rcc_ex.h
new file mode 100644
index 000000000..785ddb84d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rcc_ex.h
@@ -0,0 +1,3138 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RCC_EX_H
+#define STM32N6xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection  Periph Clock Selection
+  * @{
+  */
+#define RCC_PERIPHCLK_ADC         (0x0000000000000001UL)
+#define RCC_PERIPHCLK_ADF1        (0x0000000000000002UL)
+#define RCC_PERIPHCLK_CKPER       (0x0000000000000004UL)
+#define RCC_PERIPHCLK_CSI         (0x0000000000000008UL)
+#define RCC_PERIPHCLK_DCMIPP      (0x0000000000000010UL)
+#define RCC_PERIPHCLK_ETH1        (0x0000000000000020UL)
+#define RCC_PERIPHCLK_ETH1PHY     (0x0000000000000040UL)
+#define RCC_PERIPHCLK_ETH1RX      (0x0000000000000080UL)
+#define RCC_PERIPHCLK_ETH1TX      (0x0000000000000100UL)
+#define RCC_PERIPHCLK_ETH1PTP     (0x0000000000000200UL)
+#define RCC_PERIPHCLK_FDCAN       (0x0000000000000400UL)
+#define RCC_PERIPHCLK_FMC         (0x0000000000000800UL)
+#define RCC_PERIPHCLK_I2C1        (0x0000000000001000UL)
+#define RCC_PERIPHCLK_I2C2        (0x0000000000002000UL)
+#define RCC_PERIPHCLK_I2C3        (0x0000000000004000UL)
+#define RCC_PERIPHCLK_I2C4        (0x0000000000008000UL)
+#define RCC_PERIPHCLK_I3C1        (0x0000000000010000UL)
+#define RCC_PERIPHCLK_I3C2        (0x0000000000020000UL)
+#define RCC_PERIPHCLK_LPTIM1      (0x0000000000040000UL)
+#define RCC_PERIPHCLK_LPTIM2      (0x0000000000080000UL)
+#define RCC_PERIPHCLK_LPTIM3      (0x0000000000100000UL)
+#define RCC_PERIPHCLK_LPTIM4      (0x0000000000200000UL)
+#define RCC_PERIPHCLK_LPTIM5      (0x0000000000400000UL)
+#define RCC_PERIPHCLK_LPUART1     (0x0000000000800000UL)
+#define RCC_PERIPHCLK_LTDC        (0x0000000001000000UL)
+#define RCC_PERIPHCLK_MDF1        (0x0000000002000000UL)
+#define RCC_PERIPHCLK_PSSI        (0x0000000004000000UL)
+#define RCC_PERIPHCLK_RTC         (0x0000000008000000UL)
+#define RCC_PERIPHCLK_SAI1        (0x0000000010000000UL)
+#define RCC_PERIPHCLK_SAI2        (0x0000000020000000UL)
+#define RCC_PERIPHCLK_SDMMC1      (0x0000000040000000UL)
+#define RCC_PERIPHCLK_SDMMC2      (0x0000000080000000UL)
+#define RCC_PERIPHCLK_SPDIFRX1    (0x0000000100000000UL)
+#define RCC_PERIPHCLK_SPI1        (0x0000000200000000UL)
+#define RCC_PERIPHCLK_SPI2        (0x0000000400000000UL)
+#define RCC_PERIPHCLK_SPI3        (0x0000000800000000UL)
+#define RCC_PERIPHCLK_SPI4        (0x0000001000000000UL)
+#define RCC_PERIPHCLK_SPI5        (0x0000002000000000UL)
+#define RCC_PERIPHCLK_SPI6        (0x0000004000000000UL)
+#define RCC_PERIPHCLK_TIM         (0x0000008000000000UL)
+#define RCC_PERIPHCLK_USART1      (0x0000010000000000UL)
+#define RCC_PERIPHCLK_USART2      (0x0000020000000000UL)
+#define RCC_PERIPHCLK_USART3      (0x0000040000000000UL)
+#define RCC_PERIPHCLK_UART4       (0x0000080000000000UL)
+#define RCC_PERIPHCLK_UART5       (0x0000100000000000UL)
+#define RCC_PERIPHCLK_USART6      (0x0000200000000000UL)
+#define RCC_PERIPHCLK_UART7       (0x0000400000000000UL)
+#define RCC_PERIPHCLK_UART8       (0x0000800000000000UL)
+#define RCC_PERIPHCLK_UART9       (0x0001000000000000UL)
+#define RCC_PERIPHCLK_USART10     (0x0002000000000000UL)
+#define RCC_PERIPHCLK_USBPHY1     (0x0004000000000000UL)
+#define RCC_PERIPHCLK_USBOTGHS1   (0x0008000000000000UL)
+#define RCC_PERIPHCLK_USBPHY2     (0x0010000000000000UL)
+#define RCC_PERIPHCLK_USBOTGHS2   (0x0020000000000000UL)
+#define RCC_PERIPHCLK_XSPI1       (0x0040000000000000UL)
+#define RCC_PERIPHCLK_XSPI2       (0x0080000000000000UL)
+#define RCC_PERIPHCLK_XSPI3       (0x0100000000000000UL)
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_ADC_Clock_Source  ADC Clock Source
+  * @{
+  */
+#define RCC_ADCCLKSOURCE_HCLK      LL_RCC_ADC_CLKSOURCE_HCLK
+#define RCC_ADCCLKSOURCE_CLKP      LL_RCC_ADC_CLKSOURCE_CLKP
+#define RCC_ADCCLKSOURCE_IC7       LL_RCC_ADC_CLKSOURCE_IC7
+#define RCC_ADCCLKSOURCE_IC8       LL_RCC_ADC_CLKSOURCE_IC8
+#define RCC_ADCCLKSOURCE_MSI       LL_RCC_ADC_CLKSOURCE_MSI
+#define RCC_ADCCLKSOURCE_HSI       LL_RCC_ADC_CLKSOURCE_HSI
+#define RCC_ADCCLKSOURCE_PIN       LL_RCC_ADC_CLKSOURCE_I2S_CKIN
+#define RCC_ADCCLKSOURCE_TIMG      LL_RCC_ADC_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_ADF1_Clock_Source  ADF1 Clock Source
+  * @{
+  */
+#define RCC_ADF1CLKSOURCE_HCLK     LL_RCC_ADF1_CLKSOURCE_HCLK
+#define RCC_ADF1CLKSOURCE_CLKP     LL_RCC_ADF1_CLKSOURCE_CLKP
+#define RCC_ADF1CLKSOURCE_IC7      LL_RCC_ADF1_CLKSOURCE_IC7
+#define RCC_ADF1CLKSOURCE_IC8      LL_RCC_ADF1_CLKSOURCE_IC8
+#define RCC_ADF1CLKSOURCE_MSI      LL_RCC_ADF1_CLKSOURCE_MSI
+#define RCC_ADF1CLKSOURCE_HSI      LL_RCC_ADF1_CLKSOURCE_HSI
+#define RCC_ADF1CLKSOURCE_PIN      LL_RCC_ADF1_CLKSOURCE_I2S_CKIN
+#define RCC_ADF1CLKSOURCE_TIMG     LL_RCC_ADF1_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CLKP_Clock_Source  CLKP Clock Source
+  * @{
+  */
+#define RCC_CLKPCLKSOURCE_HSI      LL_RCC_CLKP_CLKSOURCE_HSI
+#define RCC_CLKPCLKSOURCE_MSI      LL_RCC_CLKP_CLKSOURCE_MSI
+#define RCC_CLKPCLKSOURCE_HSE      LL_RCC_CLKP_CLKSOURCE_HSE
+#define RCC_CLKPCLKSOURCE_IC5      LL_RCC_CLKP_CLKSOURCE_IC5
+#define RCC_CLKPCLKSOURCE_IC10     LL_RCC_CLKP_CLKSOURCE_IC10
+#define RCC_CLKPCLKSOURCE_IC15     LL_RCC_CLKP_CLKSOURCE_IC15
+#define RCC_CLKPCLKSOURCE_IC19     LL_RCC_CLKP_CLKSOURCE_IC19
+#define RCC_CLKPCLKSOURCE_IC20     LL_RCC_CLKP_CLKSOURCE_IC20
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DCMIPP_Clock_Source DCMIPP Clock Source
+  * @{
+  */
+#define RCC_DCMIPPCLKSOURCE_PCLK5  LL_RCC_DCMIPP_CLKSOURCE_PCLK5
+#define RCC_DCMIPPCLKSOURCE_CLKP   LL_RCC_DCMIPP_CLKSOURCE_CLKP
+#define RCC_DCMIPPCLKSOURCE_IC17   LL_RCC_DCMIPP_CLKSOURCE_IC17
+#define RCC_DCMIPPCLKSOURCE_HSI    LL_RCC_DCMIPP_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_ETH1_Clock_Source  ETH1 Clock Source
+  * @{
+  */
+#define RCC_ETH1CLKSOURCE_HCLK     LL_RCC_ETH1_CLKSOURCE_HCLK
+#define RCC_ETH1CLKSOURCE_CLKP     LL_RCC_ETH1_CLKSOURCE_CLKP
+#define RCC_ETH1CLKSOURCE_IC12     LL_RCC_ETH1_CLKSOURCE_IC12
+#define RCC_ETH1CLKSOURCE_HSE      LL_RCC_ETH1_CLKSOURCE_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_ETH1_PHY_Interface  ETH1 PHY Interface
+  * @{
+  */
+#define RCC_ETH1PHYIF_MII          LL_RCC_ETH1PHY_IF_MII
+#define RCC_ETH1PHYIF_RGMII        LL_RCC_ETH1PHY_IF_RGMII
+#define RCC_ETH1PHYIF_RMII         LL_RCC_ETH1PHY_IF_RMII
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_ETH1_RX_Clock_Source  ETH1 RX Clock Source
+  * @{
+  */
+#define RCC_ETH1RXCLKSOURCE_EXT    LL_RCC_ETH1REFRX_CLKSOURCE_EXT
+#define RCC_ETH1RXCLKSOURCE_INT    LL_RCC_ETH1REFRX_CLKSOURCE_INT
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_ETH1_TX_Clock_Source  ETH1 TX Clock Source
+  * @{
+  */
+#define RCC_ETH1TXCLKSOURCE_EXT    LL_RCC_ETH1REFTX_CLKSOURCE_EXT
+#define RCC_ETH1TXCLKSOURCE_INT    LL_RCC_ETH1REFTX_CLKSOURCE_INT
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_ETH1_PTP_Clock_Source  ETH1 PTP Clock Source
+  * @{
+  */
+#define RCC_ETH1PTPCLKSOURCE_HCLK  LL_RCC_ETH1PTP_CLKSOURCE_HCLK
+#define RCC_ETH1PTPCLKSOURCE_CLKP  LL_RCC_ETH1PTP_CLKSOURCE_CLKP
+#define RCC_ETH1PTPCLKSOURCE_IC13  LL_RCC_ETH1PTP_CLKSOURCE_IC13
+#define RCC_ETH1PTPCLKSOURCE_HSE   LL_RCC_ETH1PTP_CLKSOURCE_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FDCAN_Clock_Source  FDCAN Kernel Clock Source
+  * @{
+  */
+#define RCC_FDCANCLKSOURCE_PCLK1   LL_RCC_FDCAN_CLKSOURCE_PCLK1
+#define RCC_FDCANCLKSOURCE_CLKP    LL_RCC_FDCAN_CLKSOURCE_CLKP
+#define RCC_FDCANCLKSOURCE_IC19    LL_RCC_FDCAN_CLKSOURCE_IC19
+#define RCC_FDCANCLKSOURCE_HSE     LL_RCC_FDCAN_CLKSOURCE_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMC_Clock_Source  FMC Clock Source
+  * @{
+  */
+#define RCC_FMCCLKSOURCE_HCLK      LL_RCC_FMC_CLKSOURCE_HCLK
+#define RCC_FMCCLKSOURCE_CLKP      LL_RCC_FMC_CLKSOURCE_CLKP
+#define RCC_FMCCLKSOURCE_IC3       LL_RCC_FMC_CLKSOURCE_IC3
+#define RCC_FMCCLKSOURCE_IC4       LL_RCC_FMC_CLKSOURCE_IC4
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source  I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_PCLK1    LL_RCC_I2C1_CLKSOURCE_PCLK1
+#define RCC_I2C1CLKSOURCE_CLKP     LL_RCC_I2C1_CLKSOURCE_CLKP
+#define RCC_I2C1CLKSOURCE_IC10     LL_RCC_I2C1_CLKSOURCE_IC10
+#define RCC_I2C1CLKSOURCE_IC15     LL_RCC_I2C1_CLKSOURCE_IC15
+#define RCC_I2C1CLKSOURCE_MSI      LL_RCC_I2C1_CLKSOURCE_MSI
+#define RCC_I2C1CLKSOURCE_HSI      LL_RCC_I2C1_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C2_Clock_Source  I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_PCLK1    LL_RCC_I2C2_CLKSOURCE_PCLK1
+#define RCC_I2C2CLKSOURCE_CLKP     LL_RCC_I2C2_CLKSOURCE_CLKP
+#define RCC_I2C2CLKSOURCE_IC10     LL_RCC_I2C2_CLKSOURCE_IC10
+#define RCC_I2C2CLKSOURCE_IC15     LL_RCC_I2C2_CLKSOURCE_IC15
+#define RCC_I2C2CLKSOURCE_MSI      LL_RCC_I2C2_CLKSOURCE_MSI
+#define RCC_I2C2CLKSOURCE_HSI      LL_RCC_I2C2_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C3_Clock_Source  I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_PCLK1    LL_RCC_I2C3_CLKSOURCE_PCLK1
+#define RCC_I2C3CLKSOURCE_CLKP     LL_RCC_I2C3_CLKSOURCE_CLKP
+#define RCC_I2C3CLKSOURCE_IC10     LL_RCC_I2C3_CLKSOURCE_IC10
+#define RCC_I2C3CLKSOURCE_IC15     LL_RCC_I2C3_CLKSOURCE_IC15
+#define RCC_I2C3CLKSOURCE_MSI      LL_RCC_I2C3_CLKSOURCE_MSI
+#define RCC_I2C3CLKSOURCE_HSI      LL_RCC_I2C3_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C4_Clock_Source  I2C4 Clock Source
+  * @{
+  */
+#define RCC_I2C4CLKSOURCE_PCLK1    LL_RCC_I2C4_CLKSOURCE_PCLK1
+#define RCC_I2C4CLKSOURCE_CLKP     LL_RCC_I2C4_CLKSOURCE_CLKP
+#define RCC_I2C4CLKSOURCE_IC10     LL_RCC_I2C4_CLKSOURCE_IC10
+#define RCC_I2C4CLKSOURCE_IC15     LL_RCC_I2C4_CLKSOURCE_IC15
+#define RCC_I2C4CLKSOURCE_MSI      LL_RCC_I2C4_CLKSOURCE_MSI
+#define RCC_I2C4CLKSOURCE_HSI      LL_RCC_I2C4_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I3C1_Clock_Source  I3C1 Clock Source
+  * @{
+  */
+#define RCC_I3C1CLKSOURCE_PCLK1    LL_RCC_I3C1_CLKSOURCE_PCLK1
+#define RCC_I3C1CLKSOURCE_CLKP     LL_RCC_I3C1_CLKSOURCE_CLKP
+#define RCC_I3C1CLKSOURCE_IC10     LL_RCC_I3C1_CLKSOURCE_IC10
+#define RCC_I3C1CLKSOURCE_IC15     LL_RCC_I3C1_CLKSOURCE_IC15
+#define RCC_I3C1CLKSOURCE_MSI      LL_RCC_I3C1_CLKSOURCE_MSI
+#define RCC_I3C1CLKSOURCE_HSI      LL_RCC_I3C1_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I3C2_Clock_Source  I3C2 Clock Source
+  * @{
+  */
+#define RCC_I3C2CLKSOURCE_PCLK1    LL_RCC_I3C2_CLKSOURCE_PCLK1
+#define RCC_I3C2CLKSOURCE_CLKP     LL_RCC_I3C2_CLKSOURCE_CLKP
+#define RCC_I3C2CLKSOURCE_IC10     LL_RCC_I3C2_CLKSOURCE_IC10
+#define RCC_I3C2CLKSOURCE_IC15     LL_RCC_I3C2_CLKSOURCE_IC15
+#define RCC_I3C2CLKSOURCE_MSI      LL_RCC_I3C2_CLKSOURCE_MSI
+#define RCC_I3C2CLKSOURCE_HSI      LL_RCC_I3C2_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source  LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1  LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_CLKP   LL_RCC_LPTIM1_CLKSOURCE_CLKP
+#define RCC_LPTIM1CLKSOURCE_IC15   LL_RCC_LPTIM1_CLKSOURCE_IC15
+#define RCC_LPTIM1CLKSOURCE_LSE    LL_RCC_LPTIM1_CLKSOURCE_LSE
+#define RCC_LPTIM1CLKSOURCE_LSI    LL_RCC_LPTIM1_CLKSOURCE_LSI
+#define RCC_LPTIM1CLKSOURCE_TIMG   LL_RCC_LPTIM1_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM2_Clock_Source  LPTIM2 Clock Source
+  * @{
+  */
+#define RCC_LPTIM2CLKSOURCE_PCLK4  LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+#define RCC_LPTIM2CLKSOURCE_CLKP   LL_RCC_LPTIM2_CLKSOURCE_CLKP
+#define RCC_LPTIM2CLKSOURCE_IC15   LL_RCC_LPTIM2_CLKSOURCE_IC15
+#define RCC_LPTIM2CLKSOURCE_LSE    LL_RCC_LPTIM2_CLKSOURCE_LSE
+#define RCC_LPTIM2CLKSOURCE_LSI    LL_RCC_LPTIM2_CLKSOURCE_LSI
+#define RCC_LPTIM2CLKSOURCE_TIMG   LL_RCC_LPTIM2_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM3_Clock_Source  LPTIM3 Clock Source
+  * @{
+  */
+#define RCC_LPTIM3CLKSOURCE_PCLK4  LL_RCC_LPTIM3_CLKSOURCE_PCLK4
+#define RCC_LPTIM3CLKSOURCE_CLKP   LL_RCC_LPTIM3_CLKSOURCE_CLKP
+#define RCC_LPTIM3CLKSOURCE_IC15   LL_RCC_LPTIM3_CLKSOURCE_IC15
+#define RCC_LPTIM3CLKSOURCE_LSE    LL_RCC_LPTIM3_CLKSOURCE_LSE
+#define RCC_LPTIM3CLKSOURCE_LSI    LL_RCC_LPTIM3_CLKSOURCE_LSI
+#define RCC_LPTIM3CLKSOURCE_TIMG   LL_RCC_LPTIM3_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM4_Clock_Source  LPTIM4 Clock Source
+  * @{
+  */
+#define RCC_LPTIM4CLKSOURCE_PCLK4  LL_RCC_LPTIM4_CLKSOURCE_PCLK4
+#define RCC_LPTIM4CLKSOURCE_CLKP   LL_RCC_LPTIM4_CLKSOURCE_CLKP
+#define RCC_LPTIM4CLKSOURCE_IC15   LL_RCC_LPTIM4_CLKSOURCE_IC15
+#define RCC_LPTIM4CLKSOURCE_LSE    LL_RCC_LPTIM4_CLKSOURCE_LSE
+#define RCC_LPTIM4CLKSOURCE_LSI    LL_RCC_LPTIM4_CLKSOURCE_LSI
+#define RCC_LPTIM4CLKSOURCE_TIMG   LL_RCC_LPTIM4_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM5_Clock_Source  LPTIM5 Clock Source
+  * @{
+  */
+#define RCC_LPTIM5CLKSOURCE_PCLK4  LL_RCC_LPTIM5_CLKSOURCE_PCLK4
+#define RCC_LPTIM5CLKSOURCE_CLKP   LL_RCC_LPTIM5_CLKSOURCE_CLKP
+#define RCC_LPTIM5CLKSOURCE_IC15   LL_RCC_LPTIM5_CLKSOURCE_IC15
+#define RCC_LPTIM5CLKSOURCE_LSE    LL_RCC_LPTIM5_CLKSOURCE_LSE
+#define RCC_LPTIM5CLKSOURCE_LSI    LL_RCC_LPTIM5_CLKSOURCE_LSI
+#define RCC_LPTIM5CLKSOURCE_TIMG   LL_RCC_LPTIM5_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source  LPUART1 Clock Source
+  * @{
+  */
+#define RCC_LPUART1CLKSOURCE_PCLK4 LL_RCC_LPUART1_CLKSOURCE_PCLK4
+#define RCC_LPUART1CLKSOURCE_CLKP  LL_RCC_LPUART1_CLKSOURCE_CLKP
+#define RCC_LPUART1CLKSOURCE_IC9   LL_RCC_LPUART1_CLKSOURCE_IC9
+#define RCC_LPUART1CLKSOURCE_IC14  LL_RCC_LPUART1_CLKSOURCE_IC14
+#define RCC_LPUART1CLKSOURCE_LSE   LL_RCC_LPUART1_CLKSOURCE_LSE
+#define RCC_LPUART1CLKSOURCE_MSI   LL_RCC_LPUART1_CLKSOURCE_MSI
+#define RCC_LPUART1CLKSOURCE_HSI   LL_RCC_LPUART1_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LTDC_Clock_Source  LTDC Clock Source
+  * @{
+  */
+#define RCC_LTDCCLKSOURCE_PCLK5    LL_RCC_LTDC_CLKSOURCE_PCLK5
+#define RCC_LTDCCLKSOURCE_CLKP     LL_RCC_LTDC_CLKSOURCE_CLKP
+#define RCC_LTDCCLKSOURCE_IC16     LL_RCC_LTDC_CLKSOURCE_IC16
+#define RCC_LTDCCLKSOURCE_HSI      LL_RCC_LTDC_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_MDF1_Clock_Source  MDF1 Clock Source
+  * @{
+  */
+#define RCC_MDF1CLKSOURCE_HCLK     LL_RCC_MDF1_CLKSOURCE_HCLK
+#define RCC_MDF1CLKSOURCE_CLKP     LL_RCC_MDF1_CLKSOURCE_CLKP
+#define RCC_MDF1CLKSOURCE_IC7      LL_RCC_MDF1_CLKSOURCE_IC7
+#define RCC_MDF1CLKSOURCE_IC8      LL_RCC_MDF1_CLKSOURCE_IC8
+#define RCC_MDF1CLKSOURCE_MSI      LL_RCC_MDF1_CLKSOURCE_MSI
+#define RCC_MDF1CLKSOURCE_HSI      LL_RCC_MDF1_CLKSOURCE_HSI
+#define RCC_MDF1CLKSOURCE_PIN      LL_RCC_MDF1_CLKSOURCE_I2S_CKIN
+#define RCC_MDF1CLKSOURCE_TIMG     LL_RCC_MDF1_CLKSOURCE_TIMG
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PSSI_Clock_Source  PSSI Clock Source
+  * @{
+  */
+#define RCC_PSSICLKSOURCE_HCLK     LL_RCC_PSSI_CLKSOURCE_HCLK
+#define RCC_PSSICLKSOURCE_CLKP     LL_RCC_PSSI_CLKSOURCE_CLKP
+#define RCC_PSSICLKSOURCE_IC20     LL_RCC_PSSI_CLKSOURCE_IC20
+#define RCC_PSSICLKSOURCE_HSI      LL_RCC_PSSI_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+  * @{
+  */
+#define RCC_SAI1CLKSOURCE_PCLK2    LL_RCC_SAI1_CLKSOURCE_PCLK2
+#define RCC_SAI1CLKSOURCE_CLKP     LL_RCC_SAI1_CLKSOURCE_CLKP
+#define RCC_SAI1CLKSOURCE_IC7      LL_RCC_SAI1_CLKSOURCE_IC7
+#define RCC_SAI1CLKSOURCE_IC8      LL_RCC_SAI1_CLKSOURCE_IC8
+#define RCC_SAI1CLKSOURCE_MSI      LL_RCC_SAI1_CLKSOURCE_MSI
+#define RCC_SAI1CLKSOURCE_HSI      LL_RCC_SAI1_CLKSOURCE_HSI
+#define RCC_SAI1CLKSOURCE_PIN      LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+#define RCC_SAI1CLKSOURCE_SPDIFRX1 LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PCLK2    LL_RCC_SAI2_CLKSOURCE_PCLK2
+#define RCC_SAI2CLKSOURCE_CLKP     LL_RCC_SAI2_CLKSOURCE_CLKP
+#define RCC_SAI2CLKSOURCE_IC7      LL_RCC_SAI2_CLKSOURCE_IC7
+#define RCC_SAI2CLKSOURCE_IC8      LL_RCC_SAI2_CLKSOURCE_IC8
+#define RCC_SAI2CLKSOURCE_MSI      LL_RCC_SAI2_CLKSOURCE_MSI
+#define RCC_SAI2CLKSOURCE_HSI      LL_RCC_SAI2_CLKSOURCE_HSI
+#define RCC_SAI2CLKSOURCE_PIN      LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
+#define RCC_SAI2CLKSOURCE_SPDIFRX1 LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDMMC1_Clock_Source  SDMMC1 Clock Source
+  * @{
+  */
+#define RCC_SDMMC1CLKSOURCE_HCLK   LL_RCC_SDMMC1_CLKSOURCE_HCLK
+#define RCC_SDMMC1CLKSOURCE_CLKP   LL_RCC_SDMMC1_CLKSOURCE_CLKP
+#define RCC_SDMMC1CLKSOURCE_IC4    LL_RCC_SDMMC1_CLKSOURCE_IC4
+#define RCC_SDMMC1CLKSOURCE_IC5    LL_RCC_SDMMC1_CLKSOURCE_IC5
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDMMC2_Clock_Source  SDMMC2 Clock Source
+  * @{
+  */
+#define RCC_SDMMC2CLKSOURCE_HCLK   LL_RCC_SDMMC2_CLKSOURCE_HCLK
+#define RCC_SDMMC2CLKSOURCE_CLKP   LL_RCC_SDMMC2_CLKSOURCE_CLKP
+#define RCC_SDMMC2CLKSOURCE_IC4    LL_RCC_SDMMC2_CLKSOURCE_IC4
+#define RCC_SDMMC2CLKSOURCE_IC5    LL_RCC_SDMMC2_CLKSOURCE_IC5
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPDIFRX1_Clock_Source  SPDIFRX1 Clock Source
+  * @{
+  */
+#define RCC_SPDIFRX1CLKSOURCE_PCLK1 LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1
+#define RCC_SPDIFRX1CLKSOURCE_CLKP  LL_RCC_SPDIFRX1_CLKSOURCE_CLKP
+#define RCC_SPDIFRX1CLKSOURCE_IC7   LL_RCC_SPDIFRX1_CLKSOURCE_IC7
+#define RCC_SPDIFRX1CLKSOURCE_IC8   LL_RCC_SPDIFRX1_CLKSOURCE_IC8
+#define RCC_SPDIFRX1CLKSOURCE_MSI   LL_RCC_SPDIFRX1_CLKSOURCE_MSI
+#define RCC_SPDIFRX1CLKSOURCE_HSI   LL_RCC_SPDIFRX1_CLKSOURCE_HSI
+#define RCC_SPDIFRX1CLKSOURCE_PIN   LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI1_Clock_Source  SPI1 Clock Source
+  * @{
+  */
+#define RCC_SPI1CLKSOURCE_PCLK2    LL_RCC_SPI1_CLKSOURCE_PCLK2
+#define RCC_SPI1CLKSOURCE_CLKP     LL_RCC_SPI1_CLKSOURCE_CLKP
+#define RCC_SPI1CLKSOURCE_IC8      LL_RCC_SPI1_CLKSOURCE_IC8
+#define RCC_SPI1CLKSOURCE_IC9      LL_RCC_SPI1_CLKSOURCE_IC9
+#define RCC_SPI1CLKSOURCE_MSI      LL_RCC_SPI1_CLKSOURCE_MSI
+#define RCC_SPI1CLKSOURCE_HSI      LL_RCC_SPI1_CLKSOURCE_HSI
+#define RCC_SPI1CLKSOURCE_PIN      LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI2_Clock_Source  SPI2 Clock Source
+  * @{
+  */
+#define RCC_SPI2CLKSOURCE_PCLK1    LL_RCC_SPI2_CLKSOURCE_PCLK1
+#define RCC_SPI2CLKSOURCE_CLKP     LL_RCC_SPI2_CLKSOURCE_CLKP
+#define RCC_SPI2CLKSOURCE_IC8      LL_RCC_SPI2_CLKSOURCE_IC8
+#define RCC_SPI2CLKSOURCE_IC9      LL_RCC_SPI2_CLKSOURCE_IC9
+#define RCC_SPI2CLKSOURCE_MSI      LL_RCC_SPI2_CLKSOURCE_MSI
+#define RCC_SPI2CLKSOURCE_HSI      LL_RCC_SPI2_CLKSOURCE_HSI
+#define RCC_SPI2CLKSOURCE_PIN      LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI3_Clock_Source  SPI3 Clock Source
+  * @{
+  */
+#define RCC_SPI3CLKSOURCE_PCLK1    LL_RCC_SPI3_CLKSOURCE_PCLK1
+#define RCC_SPI3CLKSOURCE_CLKP     LL_RCC_SPI3_CLKSOURCE_CLKP
+#define RCC_SPI3CLKSOURCE_IC8      LL_RCC_SPI3_CLKSOURCE_IC8
+#define RCC_SPI3CLKSOURCE_IC9      LL_RCC_SPI3_CLKSOURCE_IC9
+#define RCC_SPI3CLKSOURCE_MSI      LL_RCC_SPI3_CLKSOURCE_MSI
+#define RCC_SPI3CLKSOURCE_HSI      LL_RCC_SPI3_CLKSOURCE_HSI
+#define RCC_SPI3CLKSOURCE_PIN      LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI4_Clock_Source  SPI4 Clock Source
+  * @{
+  */
+#define RCC_SPI4CLKSOURCE_PCLK2    LL_RCC_SPI4_CLKSOURCE_PCLK2
+#define RCC_SPI4CLKSOURCE_CLKP     LL_RCC_SPI4_CLKSOURCE_CLKP
+#define RCC_SPI4CLKSOURCE_IC9      LL_RCC_SPI4_CLKSOURCE_IC9
+#define RCC_SPI4CLKSOURCE_IC14     LL_RCC_SPI4_CLKSOURCE_IC14
+#define RCC_SPI4CLKSOURCE_MSI      LL_RCC_SPI4_CLKSOURCE_MSI
+#define RCC_SPI4CLKSOURCE_HSI      LL_RCC_SPI4_CLKSOURCE_HSI
+#define RCC_SPI4CLKSOURCE_HSE      LL_RCC_SPI4_CLKSOURCE_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI5_Clock_Source  SPI5 Clock Source
+  * @{
+  */
+#define RCC_SPI5CLKSOURCE_PCLK2    LL_RCC_SPI5_CLKSOURCE_PCLK2
+#define RCC_SPI5CLKSOURCE_CLKP     LL_RCC_SPI5_CLKSOURCE_CLKP
+#define RCC_SPI5CLKSOURCE_IC9      LL_RCC_SPI5_CLKSOURCE_IC9
+#define RCC_SPI5CLKSOURCE_IC14     LL_RCC_SPI5_CLKSOURCE_IC14
+#define RCC_SPI5CLKSOURCE_MSI      LL_RCC_SPI5_CLKSOURCE_MSI
+#define RCC_SPI5CLKSOURCE_HSI      LL_RCC_SPI5_CLKSOURCE_HSI
+#define RCC_SPI5CLKSOURCE_HSE      LL_RCC_SPI5_CLKSOURCE_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI6_Clock_Source  SPI6 Clock Source
+  * @{
+  */
+#define RCC_SPI6CLKSOURCE_PCLK4    LL_RCC_SPI6_CLKSOURCE_PCLK4
+#define RCC_SPI6CLKSOURCE_CLKP     LL_RCC_SPI6_CLKSOURCE_CLKP
+#define RCC_SPI6CLKSOURCE_IC8      LL_RCC_SPI6_CLKSOURCE_IC8
+#define RCC_SPI6CLKSOURCE_IC9      LL_RCC_SPI6_CLKSOURCE_IC9
+#define RCC_SPI6CLKSOURCE_MSI      LL_RCC_SPI6_CLKSOURCE_MSI
+#define RCC_SPI6CLKSOURCE_HSI      LL_RCC_SPI6_CLKSOURCE_HSI
+#define RCC_SPI6CLKSOURCE_PIN      LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART1_Clock_Source  USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_PCLK2  LL_RCC_USART1_CLKSOURCE_PCLK2
+#define RCC_USART1CLKSOURCE_CLKP   LL_RCC_USART1_CLKSOURCE_CLKP
+#define RCC_USART1CLKSOURCE_IC9    LL_RCC_USART1_CLKSOURCE_IC9
+#define RCC_USART1CLKSOURCE_IC14   LL_RCC_USART1_CLKSOURCE_IC14
+#define RCC_USART1CLKSOURCE_LSE    LL_RCC_USART1_CLKSOURCE_LSE
+#define RCC_USART1CLKSOURCE_MSI    LL_RCC_USART1_CLKSOURCE_MSI
+#define RCC_USART1CLKSOURCE_HSI    LL_RCC_USART1_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source  USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_PCLK1  LL_RCC_USART2_CLKSOURCE_PCLK1
+#define RCC_USART2CLKSOURCE_CLKP   LL_RCC_USART2_CLKSOURCE_CLKP
+#define RCC_USART2CLKSOURCE_IC9    LL_RCC_USART2_CLKSOURCE_IC9
+#define RCC_USART2CLKSOURCE_IC14   LL_RCC_USART2_CLKSOURCE_IC14
+#define RCC_USART2CLKSOURCE_LSE    LL_RCC_USART2_CLKSOURCE_LSE
+#define RCC_USART2CLKSOURCE_MSI    LL_RCC_USART2_CLKSOURCE_MSI
+#define RCC_USART2CLKSOURCE_HSI    LL_RCC_USART2_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART3_Clock_Source  USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_PCLK1  LL_RCC_USART3_CLKSOURCE_PCLK1
+#define RCC_USART3CLKSOURCE_CLKP   LL_RCC_USART3_CLKSOURCE_CLKP
+#define RCC_USART3CLKSOURCE_IC9    LL_RCC_USART3_CLKSOURCE_IC9
+#define RCC_USART3CLKSOURCE_IC14   LL_RCC_USART3_CLKSOURCE_IC14
+#define RCC_USART3CLKSOURCE_LSE    LL_RCC_USART3_CLKSOURCE_LSE
+#define RCC_USART3CLKSOURCE_MSI    LL_RCC_USART3_CLKSOURCE_MSI
+#define RCC_USART3CLKSOURCE_HSI    LL_RCC_USART3_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART4_Clock_Source  UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_PCLK1   LL_RCC_UART4_CLKSOURCE_PCLK1
+#define RCC_UART4CLKSOURCE_CLKP    LL_RCC_UART4_CLKSOURCE_CLKP
+#define RCC_UART4CLKSOURCE_IC9     LL_RCC_UART4_CLKSOURCE_IC9
+#define RCC_UART4CLKSOURCE_IC14    LL_RCC_UART4_CLKSOURCE_IC14
+#define RCC_UART4CLKSOURCE_LSE     LL_RCC_UART4_CLKSOURCE_LSE
+#define RCC_UART4CLKSOURCE_MSI     LL_RCC_UART4_CLKSOURCE_MSI
+#define RCC_UART4CLKSOURCE_HSI     LL_RCC_UART4_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART5_Clock_Source  UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_PCLK1   LL_RCC_UART5_CLKSOURCE_PCLK1
+#define RCC_UART5CLKSOURCE_CLKP    LL_RCC_UART5_CLKSOURCE_CLKP
+#define RCC_UART5CLKSOURCE_IC9     LL_RCC_UART5_CLKSOURCE_IC9
+#define RCC_UART5CLKSOURCE_IC14    LL_RCC_UART5_CLKSOURCE_IC14
+#define RCC_UART5CLKSOURCE_LSE     LL_RCC_UART5_CLKSOURCE_LSE
+#define RCC_UART5CLKSOURCE_MSI     LL_RCC_UART5_CLKSOURCE_MSI
+#define RCC_UART5CLKSOURCE_HSI     LL_RCC_UART5_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART6_Clock_Source  USART6 Clock Source
+  * @{
+  */
+#define RCC_USART6CLKSOURCE_PCLK2  LL_RCC_USART6_CLKSOURCE_PCLK2
+#define RCC_USART6CLKSOURCE_CLKP   LL_RCC_USART6_CLKSOURCE_CLKP
+#define RCC_USART6CLKSOURCE_IC9    LL_RCC_USART6_CLKSOURCE_IC9
+#define RCC_USART6CLKSOURCE_IC14   LL_RCC_USART6_CLKSOURCE_IC14
+#define RCC_USART6CLKSOURCE_LSE    LL_RCC_USART6_CLKSOURCE_LSE
+#define RCC_USART6CLKSOURCE_MSI    LL_RCC_USART6_CLKSOURCE_MSI
+#define RCC_USART6CLKSOURCE_HSI    LL_RCC_USART6_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART7_Clock_Source  UART7 Clock Source
+  * @{
+  */
+#define RCC_UART7CLKSOURCE_PCLK1   LL_RCC_UART7_CLKSOURCE_PCLK1
+#define RCC_UART7CLKSOURCE_CLKP    LL_RCC_UART7_CLKSOURCE_CLKP
+#define RCC_UART7CLKSOURCE_IC9     LL_RCC_UART7_CLKSOURCE_IC9
+#define RCC_UART7CLKSOURCE_IC14    LL_RCC_UART7_CLKSOURCE_IC14
+#define RCC_UART7CLKSOURCE_LSE     LL_RCC_UART7_CLKSOURCE_LSE
+#define RCC_UART7CLKSOURCE_MSI     LL_RCC_UART7_CLKSOURCE_MSI
+#define RCC_UART7CLKSOURCE_HSI     LL_RCC_UART7_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART8_Clock_Source  UART8 Clock Source
+  * @{
+  */
+#define RCC_UART8CLKSOURCE_PCLK1   LL_RCC_UART8_CLKSOURCE_PCLK1
+#define RCC_UART8CLKSOURCE_CLKP    LL_RCC_UART8_CLKSOURCE_CLKP
+#define RCC_UART8CLKSOURCE_IC9     LL_RCC_UART8_CLKSOURCE_IC9
+#define RCC_UART8CLKSOURCE_IC14    LL_RCC_UART8_CLKSOURCE_IC14
+#define RCC_UART8CLKSOURCE_LSE     LL_RCC_UART8_CLKSOURCE_LSE
+#define RCC_UART8CLKSOURCE_MSI     LL_RCC_UART8_CLKSOURCE_MSI
+#define RCC_UART8CLKSOURCE_HSI     LL_RCC_UART8_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART9_Clock_Source  UART9 Clock Source
+  * @{
+  */
+#define RCC_UART9CLKSOURCE_PCLK2   LL_RCC_UART9_CLKSOURCE_PCLK2
+#define RCC_UART9CLKSOURCE_CLKP    LL_RCC_UART9_CLKSOURCE_CLKP
+#define RCC_UART9CLKSOURCE_IC9     LL_RCC_UART9_CLKSOURCE_IC9
+#define RCC_UART9CLKSOURCE_IC14    LL_RCC_UART9_CLKSOURCE_IC14
+#define RCC_UART9CLKSOURCE_LSE     LL_RCC_UART9_CLKSOURCE_LSE
+#define RCC_UART9CLKSOURCE_MSI     LL_RCC_UART9_CLKSOURCE_MSI
+#define RCC_UART9CLKSOURCE_HSI     LL_RCC_UART9_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART10_Clock_Source  USART10 Clock Source
+  * @{
+  */
+#define RCC_USART10CLKSOURCE_PCLK2 LL_RCC_USART10_CLKSOURCE_PCLK2
+#define RCC_USART10CLKSOURCE_CLKP  LL_RCC_USART10_CLKSOURCE_CLKP
+#define RCC_USART10CLKSOURCE_IC9   LL_RCC_USART10_CLKSOURCE_IC9
+#define RCC_USART10CLKSOURCE_IC14  LL_RCC_USART10_CLKSOURCE_IC14
+#define RCC_USART10CLKSOURCE_LSE   LL_RCC_USART10_CLKSOURCE_LSE
+#define RCC_USART10CLKSOURCE_MSI   LL_RCC_USART10_CLKSOURCE_MSI
+#define RCC_USART10CLKSOURCE_HSI   LL_RCC_USART10_CLKSOURCE_HSI
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USBPHY1_Clock_Source  USBPHY1 Clock Source
+  * @{
+  */
+#define RCC_USBPHY1REFCLKSOURCE_OTGPHY1             LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
+#define RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT          LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
+#define RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2     (LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USBPHY2_Clock_Source  USBPHY2 Clock Source
+  * @{
+  */
+#define RCC_USBPHY2REFCLKSOURCE_OTGPHY2             LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
+#define RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT          LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
+#define RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2     (LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USB_OTGHS1_Clock_Source  USB OTGHS1 Clock Source
+  * @{
+  */
+#define RCC_USBOTGHS1CLKSOURCE_HSE_DIV2             LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
+#define RCC_USBOTGHS1CLKSOURCE_CLKP                 LL_RCC_OTGPHY1_CLKSOURCE_CLKP
+#define RCC_USBOTGHS1CLKSOURCE_IC15                 LL_RCC_OTGPHY1_CLKSOURCE_IC15
+#define RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT           LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
+#define RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2      (LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USB_OTGHS2_Clock_Source  USB OTGHS2 Clock Source
+  * @{
+  */
+#define RCC_USBOTGHS2CLKSOURCE_HSE_DIV2             LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
+#define RCC_USBOTGHS2CLKSOURCE_CLKP                 LL_RCC_OTGPHY2_CLKSOURCE_CLKP
+#define RCC_USBOTGHS2CLKSOURCE_IC15                 LL_RCC_OTGPHY2_CLKSOURCE_IC15
+#define RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT           LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
+#define RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2      (LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC | 0x80000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_XSPI1_Clock_Source  XSPI1 Clock Source
+  * @{
+  */
+#define RCC_XSPI1CLKSOURCE_HCLK    LL_RCC_XSPI1_CLKSOURCE_HCLK
+#define RCC_XSPI1CLKSOURCE_CLKP    LL_RCC_XSPI1_CLKSOURCE_CLKP
+#define RCC_XSPI1CLKSOURCE_IC3     LL_RCC_XSPI1_CLKSOURCE_IC3
+#define RCC_XSPI1CLKSOURCE_IC4     LL_RCC_XSPI1_CLKSOURCE_IC4
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_XSPI2_Clock_Source  XSPI2 Clock Source
+  * @{
+  */
+#define RCC_XSPI2CLKSOURCE_HCLK    LL_RCC_XSPI2_CLKSOURCE_HCLK
+#define RCC_XSPI2CLKSOURCE_CLKP    LL_RCC_XSPI2_CLKSOURCE_CLKP
+#define RCC_XSPI2CLKSOURCE_IC3     LL_RCC_XSPI2_CLKSOURCE_IC3
+#define RCC_XSPI2CLKSOURCE_IC4     LL_RCC_XSPI2_CLKSOURCE_IC4
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_XSPI3_Clock_Source  XSPI3 Clock Source
+  * @{
+  */
+#define RCC_XSPI3CLKSOURCE_HCLK    LL_RCC_XSPI3_CLKSOURCE_HCLK
+#define RCC_XSPI3CLKSOURCE_CLKP    LL_RCC_XSPI3_CLKSOURCE_CLKP
+#define RCC_XSPI3CLKSOURCE_IC3     LL_RCC_XSPI3_CLKSOURCE_IC3
+#define RCC_XSPI3CLKSOURCE_IC4     LL_RCC_XSPI3_CLKSOURCE_IC4
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_TIM_Prescaler_Selection TIM Prescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DIV1           LL_RCC_TIM_PRESCALER_1     /*!< Timers clocks prescaler divide by 1 */
+#define RCC_TIMPRES_DIV2           LL_RCC_TIM_PRESCALER_2     /*!< Timers clocks prescaler divide by 2 */
+#define RCC_TIMPRES_DIV4           LL_RCC_TIM_PRESCALER_4     /*!< Timers clocks prescaler divide by 4 */
+#define RCC_TIMPRES_DIV8           LL_RCC_TIM_PRESCALER_8     /*!< Timers clocks prescaler divide by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define RCC_PERIPH_FREQUENCY_NO        LL_RCC_PERIPH_FREQUENCY_NO /*!< No clock enabled for the peripheral            */
+#define RCC_PERIPH_FREQUENCY_NA        LL_RCC_PERIPH_FREQUENCY_NA /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_IC_Selection_Max  Maximum IC Selection
+  * @{
+  */
+#define RCC_IC_MAX_NUMBER              20U
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_IC_Selection  IC Selection
+  * @{
+  */
+#define RCC_IC1                         0U   /*!< IC1 source is PLL1 output by default */
+#define RCC_IC2                         1U   /*!< IC2 source is PLL1 output by default */
+#define RCC_IC3                         2U   /*!< IC3 source is PLL1 output by default */
+#define RCC_IC4                         3U   /*!< IC4 source is PLL1 output by default */
+#define RCC_IC5                         4U   /*!< IC5 source is PLL1 output by default */
+#define RCC_IC6                         5U   /*!< IC6 source is PLL1 output by default */
+#define RCC_IC7                         6U   /*!< IC7 source is PLL2 output by default */
+#define RCC_IC8                         7U   /*!< IC8 source is PLL2 output by default */
+#define RCC_IC9                         8U   /*!< IC9 source is PLL2 output by default */
+#define RCC_IC10                        9U   /*!< IC10 source is PLL2 output by default */
+#define RCC_IC11                       10U   /*!< IC11 source is PLL1 output by default */
+#define RCC_IC12                       11U   /*!< IC12 source is PLL3 output by default */
+#define RCC_IC13                       12U   /*!< IC13 source is PLL3 output by default */
+#define RCC_IC14                       13U   /*!< IC14 source is PLL3 output by default */
+#define RCC_IC15                       14U   /*!< IC15 source is PLL3 output by default */
+#define RCC_IC16                       15U   /*!< IC16 source is PLL4 output by default */
+#define RCC_IC17                       16U   /*!< IC17 source is PLL4 output by default */
+#define RCC_IC18                       17U   /*!< IC18 source is PLL4 output by default */
+#define RCC_IC19                       18U   /*!< IC19 source is PLL4 output by default */
+#define RCC_IC20                       19U   /*!< IC20 source is PLL4 output by default */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR3_IM65        /*!< LSE CSS failure interrupt connected to direct EXTI line 65 (Tamper) */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Selection  PLL selection
+  * @{
+  */
+#define RCC_PLL1           0U
+#define RCC_PLL2           1U
+#define RCC_PLL3           2U
+#define RCC_PLL4           3U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_SSCGSpread_Mode  PLL SSCG spread mode selection
+  * @{
+  */
+#define RCC_PLL_SSCG_CENTER            0U                  /*!< PLL SSCG center spread modulation */
+#define RCC_PLL_SSCG_DOWN              1U                  /*!< PLL SSCG down spread modulation */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint64_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_ICInitTypeDef ICSelection[RCC_IC_MAX_NUMBER]; /*!< ICx structure parameters.
+                                        This parameter shall be used when ICx is selected as kernel clock source
+                                        for some peripherals */
+
+  uint32_t FmcClockSelection;      /*!< Specifies FMC clock source.
+                                        This parameter can be a value of @ref RCCEx_FMC_Clock_Source    */
+
+  uint32_t Xspi1ClockSelection;    /*!< Specifies XSPI1 clock source.
+                                        This parameter can be a value of @ref RCCEx_XSPI1_Clock_Source  */
+
+  uint32_t Xspi2ClockSelection;    /*!< Specifies XSPI2 clock source.
+                                        This parameter can be a value of @ref RCCEx_XSPI2_Clock_Source  */
+
+  uint32_t Xspi3ClockSelection;    /*!< Specifies XSPI3 clock source.
+                                        This parameter can be a value of @ref RCCEx_XSPI3_Clock_Source  */
+
+  uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source.
+                                        This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */
+
+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.
+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */
+
+  uint32_t AdcDivider;             /*!< Specifies ADC clock divider.
+                                        This parameter can be a value between 1 to 256 */
+
+  uint32_t Adf1ClockSelection;     /*!< Specifies ADF1 Clock clock source.
+                                        This parameter can be a value of @ref RCCEx_ADF1_Clock_Source    */
+
+  uint32_t DcmippClockSelection;   /*!< Specifies DCMIPP clock source.
+                                        This parameter can be a value of @ref RCCEx_DCMIPP_Clock_Source  */
+
+  uint32_t Eth1ClockSelection;     /*!< Specifies ETH1 clock source.
+                                        This parameter can be a value of @ref RCCEx_ETH1_Clock_Source    */
+
+  uint32_t Eth1PhyInterfaceSelection;  /*!< Specifies ETH1 PHY interface.
+                                        This parameter can be a value of @ref RCCEx_ETH1_PHY_Interface */
+
+  uint32_t Eth1RxClockSelection;    /*!< Specifies ETH1 RX clock source.
+                                        This parameter can be a value of @ref RCCEx_ETH1_RX_Clock_Source */
+
+  uint32_t Eth1TxClockSelection;    /*!< Specifies ETH1 TX clock source.
+                                        This parameter can be a value of @ref RCCEx_ETH1_TX_Clock_Source */
+
+  uint32_t Eth1PtpClockSelection;   /*!< Specifies ETH1 PTP clock source.
+                                        This parameter can be a value of @ref RCCEx_ETH1_PTP_Clock_Source */
+
+  uint32_t Eth1PtpDivider;          /*!< Specifies ETH1 PTP clock divider.
+                                        This parameter can be a value between 1 to 16 */
+
+  uint32_t FdcanClockSelection;    /*!< Specifies FDCAN kernel clock source.
+                                        This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */
+
+  uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source    */
+
+  uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C2_Clock_Source    */
+
+  uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source    */
+
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source.
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */
+
+  uint32_t I3c1ClockSelection;     /*!< Specifies I3C1 clock source.
+                                        This parameter can be a value of @ref RCCEx_I3C1_Clock_Source    */
+
+  uint32_t I3c2ClockSelection;     /*!< Specifies I3C2 clock source.
+                                        This parameter can be a value of @ref RCCEx_I3C2_Clock_Source    */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */
+
+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */
+
+  uint32_t Lptim3ClockSelection;   /*!< Specifies LPTIM3 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source  */
+
+  uint32_t Lptim4ClockSelection;   /*!< Specifies LPTIM4 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM4_Clock_Source  */
+
+  uint32_t Lptim5ClockSelection;   /*!< Specifies LPTIM5 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPTIM5_Clock_Source  */
+
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
+
+  uint32_t LtdcClockSelection;     /*!< Specifies LPUART1 clock source.
+                                        This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */
+
+  uint32_t Mdf1ClockSelection;     /*!< Specifies MDF1 Clock clock source.
+                                        This parameter can be a value of @ref RCCEx_MDF1_Clock_Source  */
+
+  uint32_t PssiClockSelection;     /*!< Specifies PSSI clock source.
+                                        This parameter can be a value of @ref RCCEx_PSSI_Clock_Source   */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source.
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */
+
+  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 clock source.
+                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source    */
+
+  uint32_t Sdmmc1ClockSelection;   /*!< Specifies SDMMC1 clock source.
+                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source  */
+
+  uint32_t Sdmmc2ClockSelection;   /*!< Specifies SDMMC2 clock source.
+                                        This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source  */
+
+  uint32_t Spi1ClockSelection;     /*!< Specifies SPI1 clock source.
+                                        This parameter can be a value of @ref RCCEx_SPI1_Clock_Source    */
+
+  uint32_t Spi2ClockSelection;     /*!< Specifies SPI2 clock source.
+                                        This parameter can be a value of @ref RCCEx_SPI2_Clock_Source    */
+
+  uint32_t Spi3ClockSelection;     /*!< Specifies SPI3 clock source.
+                                        This parameter can be a value of @ref RCCEx_SPI3_Clock_Source    */
+
+  uint32_t Spi4ClockSelection;     /*!< Specifies SPI4 clock source.
+                                        This parameter can be a value of @ref RCCEx_SPI4_Clock_Source    */
+
+  uint32_t Spi5ClockSelection;     /*!< Specifies SPI5 clock source.
+                                        This parameter can be a value of @ref RCCEx_SPI5_Clock_Source    */
+
+  uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source.
+                                        This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */
+
+  uint32_t Spdifrx1ClockSelection; /*!< Specifies SPDIFRX1 Clock clock source.
+                                        This parameter can be a value of @ref RCCEx_SPDIFRX1_Clock_Source */
+
+  uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source  */
+
+  uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source  */
+
+  uint32_t Usart3ClockSelection;   /*!< Specifies USART3 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART3_Clock_Source  */
+
+  uint32_t Uart4ClockSelection;    /*!< Specifies UART4 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART4_Clock_Source  */
+
+  uint32_t Uart5ClockSelection;    /*!< Specifies UART5 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART5_Clock_Source  */
+
+  uint32_t Usart6ClockSelection;   /*!< Specifies USART6 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART6_Clock_Source  */
+
+  uint32_t Uart7ClockSelection;    /*!< Specifies UART7 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART7_Clock_Source  */
+
+  uint32_t Uart8ClockSelection;    /*!< Specifies UART8 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART8_Clock_Source  */
+
+  uint32_t Uart9ClockSelection;    /*!< Specifies UART9 clock source.
+                                        This parameter can be a value of @ref RCCEx_UART9_Clock_Source  */
+
+  uint32_t Usart10ClockSelection;  /*!< Specifies USART10 clock source.
+                                        This parameter can be a value of @ref RCCEx_USART10_Clock_Source  */
+
+  uint32_t UsbPhy1ClockSelection;  /*!< Specifies USBPHY1 clock source.
+                                        This parameter can be a value of @ref RCCEx_USBPHY1_Clock_Source */
+
+  uint32_t UsbOtgHs1ClockSelection; /*!< Specifies USB OTG HS1 clock source.
+                                        This parameter can be a value of @ref RCCEx_USB_OTGHS1_Clock_Source */
+
+  uint32_t UsbPhy2ClockSelection;  /*!< Specifies USBPHY2 clock source.
+                                        This parameter can be a value of @ref RCCEx_USBPHY2_Clock_Source */
+
+  uint32_t UsbOtgHs2ClockSelection; /*!< Specifies USB OTG HS2 clock source.
+                                        This parameter can be a value of @ref RCCEx_USB_OTGHS2_Clock_Source */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source.
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source       */
+
+  uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
+                                        This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
+} RCC_PeriphCLKInitTypeDef;
+
+/**
+  * @brief  RCC Extended PLL configuration structure definition
+  *         (allow to configure the PLL in SSCG mode)
+  */
+typedef struct
+{
+  uint32_t PLLModDiv;                /*!< Modulation division frequency.
+                                      This parameter must be a number between Min_Data = 0 and Max_Data = 0xF */
+  uint32_t PLLModSpreadDepth;        /*!< Modulation spread spectrum depth.
+                                      This parameter must be a number between Min_Data = 0 and Max_Data = 0x1F */
+  uint32_t PLLModSpreadMode;         /*!< Modulation spread spectrum mode.
+                                      This parameter must be a value of @ref RCC_PLL_SSCGSpread_Mode */
+} RCC_PLLSSCGInitTypeDef;
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros  RCCEx Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the PLL1 SSCG Spread Depth
+  * @note   This configuration cannot be requested when the PLL1 has been enabled.
+  *
+  * @param  __PLLMODSPR__ specifies the SSCG modulation spread depth.
+  *                         It should be a value between 0 and 0x1F.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL1_MODSPR_CONFIG(__PLLMODSPR__) \
+  MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL1CFGR3_PLL1MODSPR_Pos)
+
+/**
+  * @brief  Macro to configure the PLL1 SSCG Spread Mode
+  * @note   This configuration cannot be requested when the PLL1 has been enabled.
+  *
+  * @param  __PLLMODSPRDW__ specifies the SSCG modulation spread mode.
+  *                         It should be a value of @ref RCC_PLL_SSCGSpread_Mode
+  * @retval None
+  */
+#define  __HAL_RCC_PLL1_MODSPRDW_CONFIG(__PLLMODSPRDW__) \
+  MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)
+
+
+/**
+  * @brief  Macro to configure the PLL2 SSCG Spread Depth
+  * @note   This configuration cannot be requested when the PLL2 has been enabled.
+  *
+  * @param  __PLLMODSPR__ specifies the SSCG modulation spread depth.
+  *                         It should be a value between 0 and 0x1F.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2_MODSPR_CONFIG(__PLLMODSPR__) \
+  MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL2CFGR3_PLL2MODSPR_Pos)
+
+/**
+  * @brief  Macro to configure the PLL2 SSCG Spread Mode
+  * @note   This configuration cannot be requested when the PLL2 has been enabled.
+  *
+  * @param  __PLLMODSPRDW__ specifies the SSCG modulation spread mode.
+  *                         It should be a value of @ref RCC_PLL_SSCGSpread_Mode
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2_MODSPRDW_CONFIG(__PLLMODSPRDW__) \
+  MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos)
+
+
+/**
+  * @brief  Macro to configure the PLL3 SSCG Spread Depth
+  * @note   This configuration cannot be requested when the PLL3 has been enabled.
+  *
+  * @param  __PLLMODSPR__ specifies the SSCG modulation spread depth.
+  *                         It should be a value between 0 and 0x1F.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL3_MODSPR_CONFIG(__PLLMODSPR__) \
+  MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL3CFGR3_PLL3MODSPR_Pos)
+
+/**
+  * @brief  Macro to configure the PLL3 SSCG Spread Mode
+  * @note   This configuration cannot be requested when the PLL3 has been enabled.
+  *
+  * @param  __PLLMODSPRDW__ specifies the SSCG modulation spread mode.
+  *                         It should be a value of @ref RCC_PLL_SSCGSpread_Mode
+  * @retval None
+  */
+#define  __HAL_RCC_PLL3_MODSPRDW_CONFIG(__PLLMODSPRDW__) \
+  MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos)
+
+
+/**
+  * @brief  Macro to configure the PLL4 SSCG Spread Depth
+  * @note   This configuration cannot be requested when the PLL4 has been enabled.
+  *
+  * @param  __PLLMODSPR__ specifies the SSCG modulation spread depth.
+  *                         It should be a value between 0 and 0x1F.
+  * @retval None
+  */
+#define  __HAL_RCC_PLL4_MODSPR_CONFIG(__PLLMODSPR__) \
+  MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL4CFGR3_PLL4MODSPR_Pos)
+
+/**
+  * @brief  Macro to configure the PLL4 SSCG Spread Mode
+  * @note   This configuration cannot be requested when the PLL4 has been enabled.
+  *
+  * @param  __PLLMODSPRDW__ specifies the SSCG modulation spread mode.
+  *                         It should be a value of @ref RCC_PLL_SSCGSpread_Mode
+  * @retval None
+  */
+#define  __HAL_RCC_PLL4_MODSPRDW_CONFIG(__PLLMODSPRDW__) \
+  MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos)
+
+
+/** @brief  Macro to configure the ADC clock
+  * @param  __ADC_CLKSOURCE__ specifies the ADC  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_HCLK   HCLK Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP   CLKP selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_IC7    IC7 selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_IC8    IC8 selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_MSI    MSI selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_HSI    HSI selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PIN    External I2S_CKIN selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_TIMG   TIMG selected as ADC clock
+  */
+#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
+  LL_RCC_SetADCClockSource((__ADC_CLKSOURCE__))
+
+/** @brief  Macro to get the ADC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_HCLK   HCLK Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP   CLKP selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_IC7    IC7 selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_IC8    IC8 selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_MSI    MSI selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_HSI    HSI selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PIN    External I2S_CKIN selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_TIMG   TIMG selected as ADC clock
+  */
+#define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)
+
+/** @brief  Macro to configure the ADC clock divider.
+  * @param  __ADC_DIVIDER__ specifies  clock divider for ADC.
+  *         This parameter can be a value between 1 and 256.
+  */
+#define __HAL_RCC_ADC_DIVIDER_CONFIG(__ADC_DIVIDER__) LL_RCC_SetADCPrescaler((__ADC_DIVIDER__) - 1U)
+
+/** @brief  Macro to get the ADC clock divider.
+  * @retval The divider can be a value between 1 and 256.
+  */
+#define __HAL_RCC_GET_ADC_DIVIDER() (LL_RCC_GetADCPrescaler() + 1U)
+
+/** @brief  Macro to configure the ADF1 clock
+  * @param  __ADF1_CLKSOURCE__ specifies the ADF1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ADF1CLKSOURCE_HCLK   HCLK Clock selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_CLKP   CLKP selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_IC7    IC7 selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_IC8    IC8 selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_MSI    MSI selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_HSI    HSI selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_PIN    External I2S_CKIN selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_TIMG   TIMG selected as ADF1 clock
+  */
+#define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \
+  LL_RCC_SetADFClockSource((__ADF1_CLKSOURCE__))
+
+/** @brief  Macro to get the ADF1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ADF1CLKSOURCE_HCLK   HCLK Clock selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_CLKP   CLKP selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_IC7    IC7 selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_IC8    IC8 selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_MSI    MSI selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_HSI    HSI selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_PIN    External I2S_CKIN selected as ADF1 clock
+  *            @arg RCC_ADF1CLKSOURCE_TIMG   TIMG selected as ADF1 clock
+  */
+#define __HAL_RCC_GET_ADF1_SOURCE() LL_RCC_GetADFClockSource(LL_RCC_ADF1_CLKSOURCE)
+
+/** @brief  Macro to configure the CLKP clock for peripheral
+  * @param  __CLKP_CLKSOURCE__ specifies the clock for peripheral
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLKPCLKSOURCE_HSI     HSI selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_MSI     MSI selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_HSE     HSE selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC5     IC5 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC10    IC10 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC15    IC15 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC19    IC19 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC20    IC20 selected as CLKP clock
+  */
+#define __HAL_RCC_CLKP_CONFIG(__CLKP_CLKSOURCE__) \
+  LL_RCC_SetCLKPClockSource((__CLKP_CLKSOURCE__))
+
+/** @brief  Macro to get the Oscillator clock for peripheral source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLKPCLKSOURCE_HSI     HSI selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_MSI     MSI selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_HSE     HSE selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC5     IC5 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC10    IC10 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC15    IC15 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC19    IC19 selected as CLKP clock
+  *            @arg RCC_CLKPCLKSOURCE_IC20    IC20 selected as CLKP clock
+  */
+#define __HAL_RCC_GET_CLKP_SOURCE() LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE)
+
+/** @brief  Macro to configure the DCMIPP clock source.
+  *
+  * @param  __DCMIPP_CLKSOURCE__ specifies the DCMIPP clock source.
+  *            @arg RCC_DCMIPPCLKSOURCE_PCLK5 PCLK5 selected as DCMIPP clock
+  *            @arg RCC_DCMIPPCLKSOURCE_CLKP  CLKP selected as DCMIPP clock
+  *            @arg RCC_DCMIPPCLKSOURCE_IC17  IC17 selected as DCMIPP clock
+  *            @arg RCC_DCMIPPCLKSOURCE_HSI   HSI selected as DCMIPP clock
+  */
+#define __HAL_RCC_DCMIPP_CONFIG(__DCMIPP_CLKSOURCE__) \
+  LL_RCC_SetDCMIPPClockSource((__DCMIPP_CLKSOURCE__))
+
+/** @brief  Macro to get the DCMIPP clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DCMIPPCLKSOURCE_PCLK5 PCLK5 selected as DCMIPP clock
+  *            @arg RCC_DCMIPPCLKSOURCE_CLKP  CLKP selected as DCMIPP clock
+  *            @arg RCC_DCMIPPCLKSOURCE_IC17  IC17 elected as DCMIPP clock
+  *            @arg RCC_DCMIPPCLKSOURCE_HSI   HSI selected as DCMIPP clock
+  */
+#define __HAL_RCC_GET_DCMIPP_SOURCE() LL_RCC_GetDCMIPPClockSource(LL_RCC_DCMIPP_CLKSOURCE)
+
+/** @brief  Macro to configure the ETH1 kernel clock source.
+  * @param  __ETH1_CLKSOURCE__ specifies  clock source for ETH1
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ETH1CLKSOURCE_HCLK    HCLK selected as ETH1 clock
+  *            @arg RCC_ETH1CLKSOURCE_CLKP    CLKP selected as ETH1 clock
+  *            @arg RCC_ETH1CLKSOURCE_IC12    IC12 selected as ETH1 clock
+  *            @arg RCC_ETH1CLKSOURCE_HSE     HSE selected as ETH1 clock
+  */
+#define __HAL_RCC_ETH1_CONFIG(__ETH1_CLKSOURCE__) \
+  LL_RCC_SetETHClockSource(__ETH1_CLKSOURCE__)
+
+/** @brief  Macro to get the ETH1 kernel clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ETH1CLKSOURCE_HCLK    HCLK selected as ETH1 clock
+  *            @arg RCC_ETH1CLKSOURCE_CLKP    CLKP selected as ETH1 clock
+  *            @arg RCC_ETH1CLKSOURCE_IC12    IC12 selected as ETH1 clock
+  *            @arg RCC_ETH1CLKSOURCE_HSE     HSE selected as ETH1 clock
+  */
+#define __HAL_RCC_GET_ETH1_SOURCE() LL_RCC_GetETHClockSource(LL_RCC_ETH1_CLKSOURCE)
+
+/** @brief  Macro to configure the ETH1 PHY interface.
+  * @note   This configuration must be done while ETH1 is under reset,
+  *         and before enabling the ETH1 clocks
+  * @param  __ETH1PHY_IF__ specifies  interface for ETH1 PHY
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ETH1PHYIF_MII   MII selected as ETH1 PHY interface
+  *            @arg RCC_ETH1PHYIF_RGMII RGMII selected as ETH1 PHY interface
+  *            @arg RCC_ETH1PHYIF_RMII  RMII selected as ETH1 PHY interface
+  */
+#define __HAL_RCC_ETH1PHY_CONFIG(__ETH1PHY_IF__) \
+  LL_RCC_SetETHPHYInterface(__ETH1PHY_IF__)
+
+/** @brief  Macro to get the ETH PHY clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ETH1PHYIF_MII   MII selected as ETH1 PHY interface
+  *            @arg RCC_ETH1PHYIF_RGMII RGMII selected as ETH1 PHY interface
+  *            @arg RCC_ETH1PHYIF_RMII  RMII selected as ETH1 PHY interface
+  */
+#define __HAL_RCC_GET_ETH1PHY_INTERFACE() LL_RCC_GetETHPHYInterface(LL_RCC_ETH1PHY_IF)
+
+/** @brief  Macro to configure the ETH1 reference Rx clock source.
+  * @param  __ETH1RX_CLKSOURCE__ specifies  clock source for ETH1 reference Rx
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ETH1RXCLKSOURCE_EXT    External clock selected as ETH1 reference Rx clock
+  *            @arg RCC_ETH1RXCLKSOURCE_INT    Internal kernel selected as ETH1 reference Rx clock
+  */
+#define __HAL_RCC_ETH1RX_CONFIG(__ETH1RX_CLKSOURCE__) \
+  LL_RCC_SetETHREFRXClockSource(__ETH1RX_CLKSOURCE__)
+
+/** @brief  Macro to get the ETH1 reference Rx clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ETH1RXCLKSOURCE_EXT    External clock selected as ETH1 reference Rx clock
+  *            @arg RCC_ETH1RXCLKSOURCE_INT    Internal kernel selected as ETH1 reference Rx clock
+  */
+#define __HAL_RCC_GET_ETH1RX_SOURCE() LL_RCC_GetETHREFRXClockSource(LL_RCC_ETH1REFRX_CLKSOURCE)
+
+/** @brief  Macro to configure the ETH1 reference Tx RGMII 125MHz clock source.
+  * @param  __ETH1TX_CLKSOURCE__ specifies  clock source for ETH1 reference Tx
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ETH1TXCLKSOURCE_EXT    External clock selected as ETH1 reference Tx clock
+  *            @arg RCC_ETH1TXCLKSOURCE_INT    Internal kernel selected as ETH1 reference Tx clock
+  */
+#define __HAL_RCC_ETH1TX_CONFIG(__ETH1TX_CLKSOURCE__) \
+  LL_RCC_SetETHREFTXClockSource(__ETH1TX_CLKSOURCE__)
+
+/** @brief  Macro to get the ETH1 reference Tx RGMII 125MHz clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ETH1TXCLKSOURCE_EXT    External clock selected as ETH1 reference Tx clock
+  *            @arg RCC_ETH1TXCLKSOURCE_INT    Internal kernel selected as ETH1 reference Tx clock
+  */
+#define __HAL_RCC_GET_ETH1TX_SOURCE() LL_RCC_GetETHREFTXClockSource(LL_RCC_ETH1REFTX_CLKSOURCE)
+
+/** @brief  Macro to configure the ETH1 PTP clock source.
+  * @param  __ETH1PTP_CLKSOURCE__ specifies  clock source for ETH1 PTP
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ETH1PTPCLKSOURCE_HCLK    HCLK selected as ETH1 PTP clock
+  *            @arg RCC_ETH1PTPCLKSOURCE_CLKP    CLKP selected as ETH1 PTP clock
+  *            @arg RCC_ETH1PTPCLKSOURCE_IC13    IC13 selected as ETH1 PTP clock
+  *            @arg RCC_ETH1PTPCLKSOURCE_HSE     HSE selected as ETH1 PTP clock
+  */
+#define __HAL_RCC_ETH1PTP_CONFIG(__ETH1PTP_CLKSOURCE__) \
+  LL_RCC_SetETHPTPClockSource(__ETH1PTP_CLKSOURCE__)
+
+/** @brief  Macro to get the ETH1 PTP clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ETH1PTPCLKSOURCE_HCLK    HCLK selected as ETH1 PTP clock
+  *            @arg RCC_ETH1PTPCLKSOURCE_CLKP    CLKP selected as ETH1 PTP clock
+  *            @arg RCC_ETH1PTPCLKSOURCE_IC13    IC13 selected as ETH1 PTP clock
+  *            @arg RCC_ETH1PTPCLKSOURCE_HSE     HSE selected as ETH1 PTP clock
+  */
+#define __HAL_RCC_GET_ETH1PTP_SOURCE() LL_RCC_GetETHPTPClockSource(LL_RCC_ETH1PTP_CLKSOURCE)
+
+/** @brief  Macro to configure the ETH1 PTP divider.
+  * @param  __ETH1PTP_DIVIDER__ specifies  clock divider for ETH1 PTP
+  *         This parameter can be a value between 1 and 16.
+  */
+#define __HAL_RCC_ETH1PTP_DIVIDER_CONFIG(__ETH1PTP_DIVIDER__) \
+  LL_RCC_SetETH1PTPDivider(((__ETH1PTP_DIVIDER__) - 1U) << RCC_CCIPR2_ETH1PTPDIV_Pos)
+
+/** @brief  Macro to get the ETH1 PTP divider.
+  * @retval The divider can be a value between 1 and 16.
+  */
+#define __HAL_RCC_GET_ETH1PTP_DIVIDER() \
+  ((LL_RCC_GetETH1PTPDivider() >> RCC_CCIPR2_ETH1PTPDIV_Pos) + 1U)
+
+/** @brief  Macro to configure the FDCAN kernel clock source.
+  * @param  __FDCAN_CLKSOURCE__ specifies  clock source for FDCAN kernel
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_PCLK1  PCLK1 selected as FDCAN kernel clock (default)
+  *            @arg RCC_FDCANCLKSOURCE_CLKP   CLKP selected as FDCAN kernel clock
+  *            @arg RCC_FDCANCLKSOURCE_IC19   IC19 selected as FDCAN kernel clock
+  *            @arg RCC_FDCANCLKSOURCE_HSE    HSE selected as FDCAN kernel clock
+  */
+#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \
+  LL_RCC_SetFDCANClockSource((__FDCAN_CLKSOURCE__))
+
+/** @brief  Macro to get the FDCAN kernel clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_PCLK1  PCLK1 selected as FDCAN kernel clock (default)
+  *            @arg RCC_FDCANCLKSOURCE_CLKP   CLKP selected as FDCAN kernel clock
+  *            @arg RCC_FDCANCLKSOURCE_IC19   IC19 selected as FDCAN kernel clock
+  *            @arg RCC_FDCANCLKSOURCE_HSE    HSE selected as FDCAN kernel clock
+  */
+#define __HAL_RCC_GET_FDCAN_SOURCE() LL_RCC_GetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE)
+
+/** @brief  Macro to configure the FMC clock source.
+  *
+  * @param  __FMC_CLKSOURCE__ specifies the FMC clock source.
+  *            @arg RCC_FMCCLKSOURCE_HCLK  HCLK Clock selected as FMC clock
+  *            @arg RCC_FMCCLKSOURCE_CLKP  CLKP Clock selected as FMC clock
+  *            @arg RCC_FMCCLKSOURCE_IC3   IC3 Clock selected as FMC clock
+  *            @arg RCC_FMCCLKSOURCE_IC4   IC4 selected as FMC clock
+  */
+#define __HAL_RCC_FMC_CONFIG(__FMC_CLKSOURCE__) \
+  LL_RCC_SetFMCClockSource((__FMC_CLKSOURCE__))
+
+/** @brief  Macro to get the FMC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMCCLKSOURCE_HCLK  HCLK Clock selected as FMC clock
+  *            @arg RCC_FMCCLKSOURCE_CLKP  CLKP Clock selected as FMC clock
+  *            @arg RCC_FMCCLKSOURCE_IC3   IC3 Clock selected as FMC clock
+  *            @arg RCC_FMCCLKSOURCE_IC4   IC4 selected as FMC clock
+  */
+#define __HAL_RCC_GET_FMC_SOURCE() LL_RCC_GetFMCClockSource(LL_RCC_FMC_CLKSOURCE)
+
+/** @brief  Macro to configure the I2C1 clock source.
+  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_PCLK1    PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CLKP     CKLP selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_IC10     IC10 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_IC15     IC15 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_MSI      MSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI      HSI selected as I2C1 clock
+  */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+  LL_RCC_SetI2CClockSource((__I2C1_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_PCLK1    PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CLKP     CKLP selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_IC10     IC10 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_IC15     IC15 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_MSI      MSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI      HSI selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)
+
+/** @brief  Macro to configure the I2C2 clock source.
+  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_PCLK1    PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CLKP     CKLP selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_IC10     IC10 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_IC15     IC15 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_MSI      MSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI      HSI selected as I2C2 clock
+  */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
+  LL_RCC_SetI2CClockSource((__I2C2_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_PCLK1    PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CLKP     CKLP selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_IC10     IC10 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_IC15     IC15 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_MSI      MSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI      HSI selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE)
+
+/** @brief  Macro to configure the I2C3 clock source.
+  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_PCLK1    PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CLKP     CKLP selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_IC10     IC10 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_IC15     IC15 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_MSI      MSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI      HSI selected as I2C3 clock
+  */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+  LL_RCC_SetI2CClockSource((__I2C3_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_PCLK1    PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CLKP     CKLP selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_IC10     IC10 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_IC15     IC15 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_MSI      MSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI      HSI selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)
+
+/** @brief  Macro to configure the I2C4 clock source.
+  * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_PCLK1    PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CLKP     CKLP selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_IC10     IC10 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_IC15     IC15 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_MSI      MSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI      HSI selected as I2C4 clock
+  */
+#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
+  LL_RCC_SetI2CClockSource((__I2C4_CLKSOURCE__))
+
+/** @brief  Macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_PCLK1    PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CLKP     CKLP selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_IC10     IC10 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_IC15     IC15 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_MSI      MSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI      HSI selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C4_CLKSOURCE)
+
+/** @brief  Macro to configure the I3C1 clock source.
+  * @param  __I3C1_CLKSOURCE__ specifies the I3C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I3C1CLKSOURCE_PCLK1    PCLK1 selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_CLKP     CKLP selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_IC10     IC10 selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_IC15     IC15 selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_MSI      MSI selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_HSI      HSI selected as I3C1 clock
+  */
+#define __HAL_RCC_I3C1_CONFIG(__I3C1_CLKSOURCE__) \
+  LL_RCC_SetI3CClockSource((__I3C1_CLKSOURCE__))
+
+/** @brief  Macro to get the I3C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I3C1CLKSOURCE_PCLK1    PCLK1 selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_CLKP     CKLP selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_IC10     IC10 selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_IC15     IC15 selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_MSI      MSI selected as I3C1 clock
+  *            @arg RCC_I3C1CLKSOURCE_HSI      HSI selected as I3C1 clock
+  */
+#define __HAL_RCC_GET_I3C1_SOURCE() LL_RCC_GetI3CClockSource(LL_RCC_I3C1_CLKSOURCE)
+
+/** @brief  Macro to configure the I3C2 clock source.
+  * @param  __I3C2_CLKSOURCE__ specifies the I3C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I3C2CLKSOURCE_PCLK1    PCLK1 selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_CLKP     CKLP selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_IC10     IC10 selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_IC15     IC15 selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_MSI      MSI selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_HSI      HSI selected as I3C2 clock
+  */
+#define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \
+  LL_RCC_SetI3CClockSource((__I3C2_CLKSOURCE__))
+
+/** @brief  Macro to get the I3C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I3C2CLKSOURCE_PCLK1    PCLK1 selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_CLKP     CKLP selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_IC10     IC10 selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_IC15     IC15 selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_MSI      MSI selected as I3C2 clock
+  *            @arg RCC_I3C2CLKSOURCE_HSI      HSI selected as I3C2 clock
+  */
+#define __HAL_RCC_GET_I3C2_SOURCE() LL_RCC_GetI3CClockSource(LL_RCC_I3C2_CLKSOURCE)
+
+/** @brief  Macro to configure the LPTIM1 clock source.
+  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP   CLKP clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_IC15   IC15 clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE    LSE clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI    LSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_TIMG   TIMG clock selected as LPTIM1 clock
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+  LL_RCC_SetLPTIMClockSource((__LPTIM1_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1  PCLK1 clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP   CLKP clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_IC15   IC15 clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE    LSE clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI    LSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_TIMG   TIMG clock selected as LPTIM1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE)
+
+/** @brief  Macro to configure the LPTIM2 clock source.
+  * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP   CLKP clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_IC15   IC15 clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE    LSE clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI    LSI clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_TIMG   TIMG clock selected as LPTIM2 clock
+  */
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
+  LL_RCC_SetLPTIMClockSource((__LPTIM2_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP   CLKP clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_IC15   IC15 clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE    LSE clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI    LSI clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_TIMG   TIMG clock selected as LPTIM2 clock
+  */
+#define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE)
+
+/** @brief  Macro to configure the LPTIM3 clock source.
+  * @param  __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM3CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP   CLKP clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_IC15   IC15 clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE    LSE clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI    LSI clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_TIMG   TIMG clock selected as LPTIM3 clock
+  */
+#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \
+  LL_RCC_SetLPTIMClockSource((__LPTIM3_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM3CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP   CLKP clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_IC15   IC15 clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE    LSE clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI    LSI clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_TIMG   TIMG clock selected as LPTIM3 clock
+  */
+#define __HAL_RCC_GET_LPTIM3_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE)
+
+/** @brief  Macro to configure the LPTIM4 clock source.
+  * @param  __LPTIM4_CLKSOURCE__ specifies the LPTIM4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM4CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP   CLKP clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_IC15   IC15 clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE    LSE clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI    LSI clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_TIMG   TIMG clock selected as LPTIM4 clock
+  */
+#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4_CLKSOURCE__) \
+  LL_RCC_SetLPTIMClockSource((__LPTIM4_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM4CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP   CLKP clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_IC15   IC15 clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE    LSE clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI    LSI clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_TIMG   TIMG clock selected as LPTIM4 clock
+  */
+#define __HAL_RCC_GET_LPTIM4_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM4_CLKSOURCE)
+
+/** @brief  Macro to configure the LPTIM5 clock source.
+  * @param  __LPTIM5_CLKSOURCE__ specifies the LPTIM5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM5CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP   CLKP clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_IC15   IC15 clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE    LSE clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI    LSI clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_TIMG   TIMG clock selected as LPTIM5 clock
+  */
+#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5_CLKSOURCE__) \
+  LL_RCC_SetLPTIMClockSource((__LPTIM5_CLKSOURCE__))
+
+/** @brief  Macro to get the LPTIM5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM5CLKSOURCE_PCLK4  PCLK4 clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP   CLKP clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_IC15   IC15 clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE    LSE clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI    LSI clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_TIMG   TIMG clock selected as LPTIM5 clock
+  */
+#define __HAL_RCC_GET_LPTIM5_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM5_CLKSOURCE)
+
+/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
+  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_PCLK4 PCLK4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CLKP  CLKP selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_IC9   IC9 selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_IC14  IC14 selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE   LSE selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_MSI   MSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI   HSI selected as LPUART1 clock
+  */
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
+  LL_RCC_SetLPUARTClockSource((__LPUART1_CLKSOURCE__))
+
+/** @brief  Macro to get the LPUART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_PCLK4 PCLK4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CLKP  CLKP selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_IC9   IC9 selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_IC14  IC14 selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE   LSE selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_MSI   MSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI   HSI selected as LPUART1 clock
+  */
+#define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)
+
+/** @brief  Macro to configure the LTDC clock (LTDCCLK).
+  * @param  __LTDC_CLKSOURCE__ specifies the LTDC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LTDCCLKSOURCE_PCLK5 PCLK5 Clock selected as LTDC clock
+  *            @arg RCC_LTDCCLKSOURCE_CLKP  CLKP selected as LTDC clock
+  *            @arg RCC_LTDCCLKSOURCE_IC16  IC14 selected as LTDC clock
+  *            @arg RCC_LTDCCLKSOURCE_HSI   HSI selected as LTDC clock
+  */
+#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \
+  LL_RCC_SetLTDCClockSource((__LTDC_CLKSOURCE__))
+
+/** @brief  Macro to get the LTDC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LTDCCLKSOURCE_PCLK5 PCLK5 Clock selected as LTDC clock
+  *            @arg RCC_LTDCCLKSOURCE_CLKP  CLKP selected as LTDC clock
+  *            @arg RCC_LTDCCLKSOURCE_IC16  IC14 selected as LTDC clock
+  *            @arg RCC_LTDCCLKSOURCE_HSI   HSI selected as LTDC clock
+  */
+#define __HAL_RCC_GET_LTDC_SOURCE() LL_RCC_GetLTDCClockSource(LL_RCC_LTDC_CLKSOURCE)
+
+/** @brief  Macro to configure the MDF1 clock
+  * @param  __MDF1_CLKSOURCE__ specifies the MDF1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_MDF1CLKSOURCE_HCLK   HCLK Clock selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_CLKP   CLKP selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_IC7    IC7 selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_IC8    IC8 selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_MSI    MSI selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_HSI    HSI selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_PIN    External I2S_CKIN selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_TIMG   TIMG selected as MDF1 clock
+  */
+#define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \
+  LL_RCC_SetMDFClockSource((__MDF1_CLKSOURCE__))
+
+/** @brief  Macro to get the MDF1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_MDF1CLKSOURCE_HCLK   HCLK Clock selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_CLKP   CLKP selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_IC7    IC7 selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_IC8    IC8 selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_MSI    MSI selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_HSI    HSI selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_PIN    External I2S_CKIN selected as MDF1 clock
+  *            @arg RCC_MDF1CLKSOURCE_TIMG   TIMG selected as MDF1 clock
+  */
+#define __HAL_RCC_GET_MDF1_SOURCE() LL_RCC_GetMDFClockSource(LL_RCC_MDF1_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the PSSI clock source.
+  * @param  __PSSI_CLKSOURCE__ defines the PSSI clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PSSICLKSOURCE_HCLK  HCLK selected as PSSI clock
+  *            @arg RCC_PSSICLKSOURCE_CLKP  Peripheral clock CLKP selected as PSSI clock
+  *            @arg RCC_PSSICLKSOURCE_IC20  IC20 selected as PSSI clock
+  *            @arg RCC_PSSICLKSOURCE_HSI   HSI selected as PSSI clock
+  * @retval None
+  */
+#define __HAL_RCC_PSSI_CONFIG(__PSSI_CLKSOURCE__) \
+  LL_RCC_SetPSSIClockSource((__PSSI_CLKSOURCE__))
+
+/** @brief  Macro to get the PSSI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_PSSICLKSOURCE_HCLK  HCLK selected as PSSI clock
+  *            @arg RCC_PSSICLKSOURCE_CLKP  Peripheral clock CLKP selected as PSSI clock
+  *            @arg RCC_PSSICLKSOURCE_IC20  IC20 selected as PSSI clock
+  *            @arg RCC_PSSICLKSOURCE_HSI   HSI selected as PSSI clock
+  */
+#define __HAL_RCC_GET_PSSI_SOURCE() LL_RCC_GetPSSIClockSource(LL_RCC_PSSI_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SAI1 clock source.
+  * @param  __SAI1_CLKSOURCE__ defines the SAI1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PCLK2  PCLK2 Clock selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_CLKP   Peripheral clock CLKP selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_IC7    IC7 selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_IC8    IC8 selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_MSI    MSI selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_HSI    HSI selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_PIN    External I2S_CKIN selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI1 clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) \
+  LL_RCC_SetSAIClockSource((__SAI1_CLKSOURCE__))
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PCLK2  PCLK2 Clock selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_CLKP   Peripheral clock CLKP selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_IC7    IC7 selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_IC8    IC8 selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_MSI    MSI selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_HSI    HSI selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_PIN    External I2S_CKIN selected as SAI1 clock
+  *            @arg RCC_SAI1CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI1 clock
+  */
+#define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SAI2 clock source.
+  * @param  __SAI2_CLKSOURCE__ defines the SAI2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PCLK2  PCLK2 Clock selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_CLKP   Peripheral clock CLKP selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_IC7    IC7 selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_IC8    IC8 selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_MSI    MSI selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_HSI    HSI selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_PIN    External I2S_CKIN selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI2 clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) \
+  LL_RCC_SetSAIClockSource((__SAI2_CLKSOURCE__))
+
+/** @brief  Macro to get the SAI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PCLK2  PCLK2 Clock selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_CLKP   Peripheral clock CLKP selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_IC7    IC7 selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_IC8    IC8 selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_MSI    MSI selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_HSI    HSI selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_PIN    External I2S_CKIN selected as SAI2 clock
+  *            @arg RCC_SAI2CLKSOURCE_SPDIFRX1 SPDIFRX1 selected as SAI2 clock
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI2_CLKSOURCE)
+
+/** @brief  Macro to configure the SDMMC1 kernel clock source.
+  * @param  __SDMMC1_CLKSOURCE__ specifies  clock source  for SDMMC1
+  *        This parameter can be one of the following values:
+  *            @arg RCC_SDMMC1CLKSOURCE_HCLK   HCLK Clock selected as SDMMC1 kernel clock
+  *            @arg RCC_SDMMC1CLKSOURCE_CLKP   Peripheral clock CLKP selected as SDMMC1 kernel clock
+  *            @arg RCC_SDMMC1CLKSOURCE_IC4    IC4 selected as SDMMC1 kernel clock
+  *            @arg RCC_SDMMC1CLKSOURCE_IC5    IC5 selected as SDMMC1 kernel clock
+  */
+#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
+  LL_RCC_SetSDMMCClockSource((__SDMMC1_CLKSOURCE__))
+
+/** @brief  Macro to get the SDMMC1 kernel clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDMMC1CLKSOURCE_HCLK   HCLK Clock selected as SDMMC1 kernel clock
+  *            @arg RCC_SDMMC1CLKSOURCE_CLKP   Peripheral clock CLKP selected as SDMMC1 kernel clock
+  *            @arg RCC_SDMMC1CLKSOURCE_IC4    IC4 selected as SDMMC1 kernel clock
+  *            @arg RCC_SDMMC1CLKSOURCE_IC5    IC5 selected as SDMMC1 kernel clock
+  */
+#define __HAL_RCC_GET_SDMMC1_SOURCE() LL_RCC_GetSDMMCClockSource(LL_RCC_SDMMC1_CLKSOURCE)
+
+/** @brief  Macro to configure the SDMMC2 kernel clock source.
+  * @param  __SDMMC2_CLKSOURCE__ specifies  clock source  for SDMMC2
+  *        This parameter can be one of the following values:
+  *            @arg RCC_SDMMC2CLKSOURCE_HCLK   HCLK Clock selected as SDMMC2 kernel clock
+  *            @arg RCC_SDMMC2CLKSOURCE_CLKP   Peripheral clock CLKP selected as SDMMC2 kernel clock
+  *            @arg RCC_SDMMC2CLKSOURCE_IC4    IC4 selected as SDMMC2 kernel clock
+  *            @arg RCC_SDMMC2CLKSOURCE_IC5    IC5 selected as SDMMC2 kernel clock
+  */
+#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
+  LL_RCC_SetSDMMCClockSource((__SDMMC2_CLKSOURCE__))
+
+/** @brief  Macro to get the SDMMC2 kernel clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDMMC2CLKSOURCE_HCLK   HCLK Clock selected as SDMMC2 kernel clock
+  *            @arg RCC_SDMMC2CLKSOURCE_CLKP   Peripheral clock CLKP selected as SDMMC2 kernel clock
+  *            @arg RCC_SDMMC2CLKSOURCE_IC4    IC4 selected as SDMMC2 kernel clock
+  *            @arg RCC_SDMMC2CLKSOURCE_IC5    IC5 selected as SDMMC2 kernel clock
+  */
+#define __HAL_RCC_GET_SDMMC2_SOURCE() LL_RCC_GetSDMMCClockSource(LL_RCC_SDMMC2_CLKSOURCE)
+
+/**
+  * @brief  Macro to Configure the SPDIFRX1 clock source.
+  * @param  __SPDIFRX_CLKSOURCE__ defines the SPDIFRX1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SPDIFRX1CLKSOURCE_PCLK1  PCLK1 Clock selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_CLKP   Peripheral clock CLKP selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_IC7    IC7 selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_IC8    IC8 selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_MSI    MSI selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_HSI    HSI selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_PIN    External I2S_CKIN selected as SPDIFRX1 clock
+  * @retval None
+  */
+#define __HAL_RCC_SPDIFRX1_CONFIG(__SPDIFRX_CLKSOURCE__ ) \
+  LL_RCC_SetSPDIFRXClockSource((__SPDIFRX_CLKSOURCE__))
+
+/**
+  * @brief  Macro to get the SPDIFRX1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPDIFRX1CLKSOURCE_PCLK1  PCLK1 Clock selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_CLKP   Peripheral clock CLKP selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_IC7    IC7 selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_IC8    IC8 selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_MSI    MSI selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_HSI    HSI selected as SPDIFRX1 clock
+  *            @arg RCC_SPDIFRX1CLKSOURCE_PIN    External I2S_CKIN selected as SPDIFRX1 clock
+  * @retval None
+  */
+#define __HAL_RCC_GET_SPDIFRX1_SOURCE() LL_RCC_GetSPDIFRXClockSource(LL_RCC_SPDIFRX1_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SPI1 clock source.
+  * @param  __SPI1_CLKSOURCE__ defines the SPI1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPI1CLKSOURCE_PCLK2  PCLK2 selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_IC8    IC8 selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_IC9    IC9 selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_MSI    MSI selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_HSI    HSI selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_PIN    External I2S_CKIN selected as SPI1 clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI1_CONFIG(__SPI1_CLKSOURCE__ ) \
+  LL_RCC_SetSPIClockSource((__SPI1_CLKSOURCE__))
+
+/** @brief  Macro to get the SPI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPI1CLKSOURCE_PCLK2  PCLK2 selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_IC8    IC8 selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_IC9    IC9 selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_MSI    MSI selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_HSI    HSI selected as SPI1 clock
+  *            @arg RCC_SPI1CLKSOURCE_PIN    External I2S_CKIN selected as SPI1 clock
+  */
+#define __HAL_RCC_GET_SPI1_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI1_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SPI2 clock source.
+  * @param  __SPI2_CLKSOURCE__ defines the SPI2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPI2CLKSOURCE_PCLK1  PCLK1 selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_IC8    IC8 selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_IC9    IC9 selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_MSI    MSI selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_HSI    HSI selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_PIN    External I2S_CKIN selected as SPI2 clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI2_CONFIG(__SPI2_CLKSOURCE__ ) \
+  LL_RCC_SetSPIClockSource((__SPI2_CLKSOURCE__))
+
+/** @brief  Macro to get the SPI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPI2CLKSOURCE_PCLK1  PCLK1 selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_IC8    IC8 selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_IC9    IC9 selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_MSI    MSI selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_HSI    HSI selected as SPI2 clock
+  *            @arg RCC_SPI2CLKSOURCE_PIN    External I2S_CKIN selected as SPI2 clock
+  */
+#define __HAL_RCC_GET_SPI2_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI2_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SPI3 clock source.
+  * @param  __SPI3_CLKSOURCE__ defines the SPI3 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPI3CLKSOURCE_PCLK1  PCLK1 selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_IC8    IC8 selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_IC9    IC9 selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_MSI    MSI selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_HSI    HSI selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_PIN    External I2S_CKIN selected as SPI3 clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI3_CONFIG(__SPI3_CLKSOURCE__ ) \
+  LL_RCC_SetSPIClockSource((__SPI3_CLKSOURCE__))
+
+/** @brief  Macro to get the SPI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPI3CLKSOURCE_PCLK1  PCLK1 selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_IC8    IC8 selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_IC9    IC9 selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_MSI    MSI selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_HSI    HSI selected as SPI3 clock
+  *            @arg RCC_SPI3CLKSOURCE_PIN    External I2S_CKIN selected as SPI3 clock
+  */
+#define __HAL_RCC_GET_SPI3_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI3_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SPI4 clock source.
+  * @param  __SPI4_CLKSOURCE__ defines the SPI4 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPI4CLKSOURCE_PCLK2  PCLK2 selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_IC8    IC8 selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_IC9    IC9 selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_MSI    MSI selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_HSI    HSI selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_PIN    External I2S_CKIN selected as SPI4 clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI4_CONFIG(__SPI4_CLKSOURCE__ ) \
+  LL_RCC_SetSPIClockSource((__SPI4_CLKSOURCE__))
+
+/** @brief  Macro to get the SPI4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPI4CLKSOURCE_PCLK2  PCLK2 selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_IC8    IC8 selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_IC9    IC9 selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_MSI    MSI selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_HSI    HSI selected as SPI4 clock
+  *            @arg RCC_SPI4CLKSOURCE_PIN    External I2S_CKIN selected as SPI4 clock
+  */
+#define __HAL_RCC_GET_SPI4_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI4_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SPI5 clock source.
+  * @param  __SPI5_CLKSOURCE__ defines the SPI5 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPI5CLKSOURCE_PCLK2  PCLK2 selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_IC8    IC8 selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_IC9    IC9 selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_MSI    MSI selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_HSI    HSI selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_PIN    External I2S_CKIN selected as SPI5 clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI5_CONFIG(__SPI5_CLKSOURCE__ ) \
+  LL_RCC_SetSPIClockSource((__SPI5_CLKSOURCE__))
+
+/** @brief  Macro to get the SPI5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPI5CLKSOURCE_PCLK2  PCLK2 selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_IC8    IC8 selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_IC9    IC9 selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_MSI    MSI selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_HSI    HSI selected as SPI5 clock
+  *            @arg RCC_SPI5CLKSOURCE_PIN    External I2S_CKIN selected as SPI5 clock
+  */
+#define __HAL_RCC_GET_SPI5_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI5_CLKSOURCE)
+
+/**
+  * @brief  Macro to configure the SPI6 clock source.
+  * @param  __SPI6_CLKSOURCE__ defines the SPI6 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPI6CLKSOURCE_PCLK4  PCLK4 selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_IC8    IC8 selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_IC9    IC9 selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_MSI    MSI selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_HSI    HSI selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_PIN    External I2S_CKIN selected as SPI6 clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI6_CONFIG(__SPI6_CLKSOURCE__ ) \
+  LL_RCC_SetSPIClockSource((__SPI6_CLKSOURCE__))
+
+/** @brief  Macro to get the SPI6 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPI6CLKSOURCE_PCLK4  PCLK4 selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_CLKP   Peripheral clock CKLP selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_IC8    IC8 selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_IC9    IC9 selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_MSI    MSI selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_HSI    HSI selected as SPI6 clock
+  *            @arg RCC_SPI6CLKSOURCE_PIN    External I2S_CKIN selected as SPI6 clock
+  */
+#define __HAL_RCC_GET_SPI6_SOURCE() LL_RCC_GetSPIClockSource(LL_RCC_SPI6_CLKSOURCE)
+
+/** @brief  Macro to configure the USART1 clock source.
+  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_IC9    IC9 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_IC14   IC14 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE    LSE selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_MSI    MSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI    HSI selected as USART1 clock
+  */
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__USART1_CLKSOURCE__))
+
+/** @brief  Macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_PCLK2  PCLK2 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_IC9    IC9 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_IC14   IC14 selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE    LSE selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_MSI    MSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI    HSI selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)
+
+/** @brief  Macro to configure the USART2 clock source.
+  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_IC9    IC9 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_IC14   IC14 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE    LSE selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_MSI    MSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI    HSI selected as USART2 clock
+  */
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__USART2_CLKSOURCE__))
+
+/** @brief  Macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_PCLK1  PCLK1 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_IC9    IC9 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_IC14   IC14 selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE    LSE selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_MSI    MSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI    HSI selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE)
+
+/** @brief  Macro to configure the USART3 clock source.
+  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_IC9    IC9 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_IC14   IC14 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE    LSE selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_MSI    MSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI    HSI selected as USART3 clock
+  */
+#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__USART3_CLKSOURCE__))
+
+/** @brief  Macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_PCLK1  PCLK1 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_IC9    IC9 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_IC14   IC14 selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE    LSE selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_MSI    MSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI    HSI selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART3_CLKSOURCE)
+
+/** @brief  Macro to configure the UART4 clock source.
+  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_IC9    IC9 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_IC14   IC14 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE    LSE selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_MSI    MSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI    HSI selected as UART4 clock
+  */
+#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__UART4_CLKSOURCE__))
+
+/** @brief  Macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_PCLK1  PCLK1 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_IC9    IC9 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_IC14   IC14 selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE    LSE selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_MSI    MSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI    HSI selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART4_CLKSOURCE)
+
+/** @brief  Macro to configure the UART5 clock source.
+  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_IC9    IC9 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_IC14   IC14 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE    LSE selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_MSI    MSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI    HSI selected as UART5 clock
+  */
+#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__UART5_CLKSOURCE__))
+
+/** @brief  Macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_PCLK1  PCLK1 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_IC9    IC9 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_IC14   IC14 selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE    LSE selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_MSI    MSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI    HSI selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART5_CLKSOURCE)
+
+/** @brief  Macro to configure the USART6 clock source.
+  * @param  __USART6_CLKSOURCE__ specifies the USART6 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_PCLK2  PCLK2 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_IC9    IC9 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_IC14   IC14 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE    LSE selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_MSI    MSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI    HSI selected as USART6 clock
+  */
+#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__USART6_CLKSOURCE__))
+
+/** @brief  Macro to get the USART6 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_PCLK2  PCLK2 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_IC9    IC9 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_IC14   IC14 selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE    LSE selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_MSI    MSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI    HSI selected as USART6 clock
+  */
+#define __HAL_RCC_GET_USART6_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART6_CLKSOURCE)
+
+/** @brief  Macro to configure the UART7 clock source.
+  * @param  __UART7_CLKSOURCE__ specifies the UART7 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_PCLK1  PCLK1 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_IC9    IC9 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_IC14   IC14 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE    LSE selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_MSI    MSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI    HSI selected as UART7 clock
+  */
+#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__UART7_CLKSOURCE__))
+
+/** @brief  Macro to get the UART7 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_PCLK1  PCLK1 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_IC9    IC9 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_IC14   IC14 selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE    LSE selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_MSI    MSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI    HSI selected as UART7 clock
+  */
+#define __HAL_RCC_GET_UART7_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART7_CLKSOURCE)
+
+/** @brief  Macro to configure the UART8 clock source.
+  * @param  __UART8_CLKSOURCE__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_PCLK1  PCLK1 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_IC9    IC9 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_IC14   IC14 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE    LSE selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_MSI    MSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI    HSI selected as UART8 clock
+  */
+#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__UART8_CLKSOURCE__))
+
+/** @brief  Macro to get the UART8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_PCLK1  PCLK1 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_IC9    IC9 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_IC14   IC14 selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE    LSE selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_MSI    MSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI    HSI selected as UART8 clock
+  */
+#define __HAL_RCC_GET_UART8_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART8_CLKSOURCE)
+
+/** @brief  Macro to configure the UART9 clock source.
+  * @param  __UART9_CLKSOURCE__ specifies the UART9 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_PCLK2  PCLK2 selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_IC9    IC9 selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_IC14   IC14 selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE    LSE selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_MSI    MSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI    HSI selected as UART9 clock
+  */
+#define __HAL_RCC_UART9_CONFIG(__UART9_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__UART9_CLKSOURCE__))
+
+/** @brief  Macro to get the UART9 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_PCLK2  PCLK2 selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CLKP   Peripheral clock CKLP selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_IC9    IC9 selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_IC14   IC14 selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE    LSE selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_MSI    MSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI    HSI selected as UART9 clock
+  */
+#define __HAL_RCC_GET_UART9_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_UART9_CLKSOURCE)
+
+/** @brief  Macro to configure the USART10 clock source.
+  * @param  __USART10_CLKSOURCE__ specifies the USART10 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_PCLK2  PCLK2 selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_IC9    IC9 selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_IC14   IC14 selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE    LSE selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_MSI    MSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI    HSI selected as USART10 clock
+  */
+#define __HAL_RCC_USART10_CONFIG(__USART10_CLKSOURCE__) \
+  LL_RCC_SetUSARTClockSource((__USART10_CLKSOURCE__))
+
+/** @brief  Macro to get the USART10 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_PCLK2  PCLK2 selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CLKP   Peripheral clock CKLP selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_IC9    IC9 selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_IC14   IC14 selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE    LSE selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_MSI    MSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI    HSI selected as USART10 clock
+  */
+#define __HAL_RCC_GET_USART10_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART10_CLKSOURCE)
+
+/** @brief  Macro to configure the XSPI1 clock source.
+  *
+  * @param  __XSPI1_CLKSOURCE__ specifies the XSPI1 clock source.
+  *            @arg RCC_XSPI1CLKSOURCE_HCLK  HCLK selected as XSPI1 clock
+  *            @arg RCC_XSPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI1 clock
+  *            @arg RCC_XSPI1CLKSOURCE_IC3 IC3 selected as XSPI1 clock
+  *            @arg RCC_XSPI1CLKSOURCE_IC4 IC4 selected as XSPI1 clock
+  */
+#define __HAL_RCC_XSPI1_CONFIG(__XSPI1_CLKSOURCE__) \
+  LL_RCC_SetXSPIClockSource((__XSPI1_CLKSOURCE__))
+
+/** @brief  Macro to get the XSPI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_XSPI1CLKSOURCE_HCLK  HCLK selected as XSPI1 clock
+  *            @arg RCC_XSPI1CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI1 clock
+  *            @arg RCC_XSPI1CLKSOURCE_IC3 IC3 selected as XSPI1 clock
+  *            @arg RCC_XSPI1CLKSOURCE_IC4 IC4 selected as XSPI1 clock
+  */
+#define __HAL_RCC_GET_XSPI1_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI1_CLKSOURCE)
+
+/** @brief  Macro to configure the XSPI2 clock source.
+  *
+  * @param  __XSPI2_CLKSOURCE__ specifies the XSPI2 clock source.
+  *            @arg RCC_XSPI2CLKSOURCE_HCLK  HCLK selected as XSPI2 clock
+  *            @arg RCC_XSPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI2 clock
+  *            @arg RCC_XSPI2CLKSOURCE_IC3 IC3 selected as XSPI2 clock
+  *            @arg RCC_XSPI2CLKSOURCE_IC4 IC4 selected as XSPI2 clock
+  */
+#define __HAL_RCC_XSPI2_CONFIG(__XSPI2_CLKSOURCE__) \
+  LL_RCC_SetXSPIClockSource((__XSPI2_CLKSOURCE__))
+
+/** @brief  Macro to get the XSPI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_XSPI2CLKSOURCE_HCLK  HCLK selected as XSPI2 clock
+  *            @arg RCC_XSPI2CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI2 clock
+  *            @arg RCC_XSPI2CLKSOURCE_IC3 IC3 selected as XSPI2 clock
+  *            @arg RCC_XSPI2CLKSOURCE_IC4 IC4 selected as XSPI2 clock
+  */
+#define __HAL_RCC_GET_XSPI2_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI2_CLKSOURCE)
+
+/** @brief  Macro to configure the XSPI3 clock source.
+  *
+  * @param  __XSPI3_CLKSOURCE__ specifies the XSPI3 clock source.
+  *            @arg RCC_XSPI3CLKSOURCE_HCLK  HCLK selected as XSPI3 clock
+  *            @arg RCC_XSPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI3 clock
+  *            @arg RCC_XSPI3CLKSOURCE_IC3 IC3 selected as XSPI3 clock
+  *            @arg RCC_XSPI3CLKSOURCE_IC4 IC4 selected as XSPI3 clock
+  */
+#define __HAL_RCC_XSPI3_CONFIG(__XSPI3_CLKSOURCE__) \
+  LL_RCC_SetXSPIClockSource((__XSPI3_CLKSOURCE__))
+
+/** @brief  Macro to get the XSPI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_XSPI3CLKSOURCE_HCLK  HCLK selected as XSPI3 clock
+  *            @arg RCC_XSPI3CLKSOURCE_CLKP Peripheral clock CKLP selected as XSPI3 clock
+  *            @arg RCC_XSPI3CLKSOURCE_IC3 IC3 selected as XSPI3 clock
+  *            @arg RCC_XSPI3CLKSOURCE_IC4 IC4 selected as XSPI3 clock
+  */
+#define __HAL_RCC_GET_XSPI3_SOURCE() LL_RCC_GetXSPIClockSource(LL_RCC_XSPI3_CLKSOURCE)
+
+/** @brief  Macro to configure the Timers clocks prescaler
+  * @param  __PRESC__  specifies the Timers clocks prescaler selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DIV1 The Timers kernels clocks prescaler is 1
+  *            @arg RCC_TIMPRES_DIV2 The Timers kernels clocks prescaler is 2
+  *            @arg RCC_TIMPRES_DIV4 The Timers kernels clocks prescaler is 4
+  *            @arg RCC_TIMPRES_DIV8 The Timers kernels clocks prescaler is 8
+  */
+#define __HAL_RCC_TIMCLKPRESCALER_CONFIG(__PRESC__) LL_RCC_SetTIMPrescaler((__PRESC__))
+
+/** @brief  Macro to get the Timers clocks prescaler.
+  * @retval Timers clocks prescaler can be one of the following values:
+  *            @arg RCC_TIMPRES_DIV1 The Timers kernels clocks prescaler is 1
+  *            @arg RCC_TIMPRES_DIV2 The Timers kernels clocks prescaler is 2
+  *            @arg RCC_TIMPRES_DIV4 The Timers kernels clocks prescaler is 4
+  *            @arg RCC_TIMPRES_DIV8 The Timers kernels clocks prescaler is 8
+  */
+#define __HAL_RCC_GET_TIMCLKPRESCALER() LL_RCC_GetTIMPrescaler()
+
+/** @brief  Macro to configure the USBPHY1 clock.
+  * @param  __USBPHY1_CLKSOURCE__ specifies the USBPHY1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBPHY1REFCLKSOURCE_OTGPHY1         USB OTGPHY1 kernel clock selected as USBPHY1 clock
+  *            @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT      HSE from oscillator selected as USBPHY1 clock
+  *            @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY1 clock
+  */
+#define __HAL_RCC_USBPHY1_CONFIG(__USBPHY1_CLKSOURCE__)                               \
+  do                                                                                  \
+  {                                                                                   \
+    LL_RCC_SetOTGPHYCKREFClockSource((__USBPHY1_CLKSOURCE__) & 0x7FFFFFFFUL);         \
+    if(((__USBPHY1_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \
+      else {LL_RCC_HSE_SelectHSEAsDiv2Clock();}                                         \
+  } while (0)
+
+
+/** @brief  Macro to get the USBPHY1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBPHY1REFCLKSOURCE_OTGPHY1         USB OTGPHY1 kernel clock selected as USBPHY1 clock
+  *            @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT      HSE from oscillator selected as USBPHY1 clock
+  *            @arg RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY1 clock
+  */
+#define __HAL_RCC_GET_USBPHY1_SOURCE()                       \
+  (LL_RCC_GetOTGPHYCKREFClockSource(LL_RCC_OTGPHY1CKREF_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U))
+
+/** @brief  Macro to configure the USBPHY2 clock.
+  * @param  __USBPHY2_CLKSOURCE__ specifies the USBPHY2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBPHY2REFCLKSOURCE_OTGPHY2         USB OTGPHY2 kernel clock selected as USBPHY2 clock
+  *            @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT      HSE from oscillator selected as USBPHY2 clock
+  *            @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY2 clock
+  */
+#define __HAL_RCC_USBPHY2_CONFIG(__USBPHY2_CLKSOURCE__)                                 \
+  do                                                                                    \
+  {                                                                                     \
+    LL_RCC_SetOTGPHYCKREFClockSource((__USBPHY2_CLKSOURCE__) & 0x7FFFFFFFUL);           \
+    if(((__USBPHY2_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \
+      else {LL_RCC_HSE_SelectHSEAsDiv2Clock();}                                         \
+  } while (0)
+
+/** @brief  Macro to get the USBPHY2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBPHY2REFCLKSOURCE_OTGPHY2         USB OTGPHY2 kernel clock selected as USBPHY2 clock
+  *            @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT      HSE from oscillator selected as USBPHY2 clock
+  *            @arg RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2 HSE from oscillator divided by 2 selected as USBPHY2 clock
+  */
+#define __HAL_RCC_GET_USBPHY2_SOURCE()                       \
+  (LL_RCC_GetOTGPHYCKREFClockSource(LL_RCC_OTGPHY2CKREF_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U))
+
+/** @brief  Macro to configure the USB OTGHS1 clock.
+  * @param  __USBOTGHS1_CLKSOURCE__ specifies the USB OTGHS1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV2      HSE divided by 2 selected as USBOTGHS1 clock
+  *            @arg RCC_USBOTGHS1CLKSOURCE_CLKP          Peripheral clock CKLP selected as USBOTGHS1 clock
+  *            @arg RCC_USBOTGHS1CLKSOURCE_IC15          IC15 selected as USBOTGHS1 clock
+  *            @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS1 clock
+  */
+#define __HAL_RCC_USBOTGHS1_CONFIG(__USBOTGHS1_CLKSOURCE__)                             \
+  do                                                                                    \
+  {                                                                                     \
+    LL_RCC_SetOTGPHYClockSource((__USBOTGHS1_CLKSOURCE__) & 0x7FFFFFFFUL);              \
+    if(((__USBOTGHS1_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \
+      else {LL_RCC_HSE_SelectHSEAsDiv2Clock();}                                           \
+  } while (0)
+
+/** @brief  Macro to get the USB OTGHS1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV2      HSE divided by 2 selected as USBOTGHS1 clock
+  *            @arg RCC_USBOTGHS1CLKSOURCE_CLKP          Peripheral clock CKLP selected as USBOTGHS1 clock
+  *            @arg RCC_USBOTGHS1CLKSOURCE_IC15          IC15 selected as USBOTGHS1 clock
+  *            @arg RCC_USBOTGHS1CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS1 clock
+  */
+#define __HAL_RCC_GET_USBOTGHS1_SOURCE()                       \
+  (LL_RCC_GetOTGPHYClockSource(LL_RCC_OTGPHY1_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U))
+
+/** @brief  Macro to configure the USB OTGHS2 clock.
+  * @param  __USBOTGHS2_CLKSOURCE__ specifies the USB OTGHS2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV2      HSE divided by 2 selected as USBOTGHS2 clock
+  *            @arg RCC_USBOTGHS2CLKSOURCE_CLKP          Peripheral clock CKLP selected as USBOTGHS2 clock
+  *            @arg RCC_USBOTGHS2CLKSOURCE_IC15          IC15 selected as USBOTGHS2 clock
+  *            @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS2 clock
+  */
+#define __HAL_RCC_USBOTGHS2_CONFIG(__USBOTGHS2_CLKSOURCE__)                             \
+  do                                                                                    \
+  {                                                                                     \
+    LL_RCC_SetOTGPHYClockSource((__USBOTGHS2_CLKSOURCE__) & 0x7FFFFFFFUL);              \
+    if(((__USBOTGHS2_CLKSOURCE__)>>31U) == 1UL) {LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();} \
+      else {LL_RCC_HSE_SelectHSEAsDiv2Clock();}                                           \
+  } while (0)
+
+/** @brief  Macro to get the USB OTGHS2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV2      HSE divided by 2 selected as USBOTGHS2 clock
+  *            @arg RCC_USBOTGHS2CLKSOURCE_CLKP          Peripheral clock CKLP selected as USBOTGHS2 clock
+  *            @arg RCC_USBOTGHS2C LKSOURCE_IC15          IC15 selected as USBOTGHS2 clock
+  *            @arg RCC_USBOTGHS2CLKSOURCE_HSE_DIV_2_OSC HSE divided by 2 from oscillator selected as USBOTGHS2 clock
+  */
+#define __HAL_RCC_GET_USBOTGHS2_SOURCE()                       \
+  (LL_RCC_GetOTGPHYClockSource(LL_RCC_OTGPHY2_CLKSOURCE) | (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock()<<31U))
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR3, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR3, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR3, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR3, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk);
+uint32_t HAL_RCCEx_GetPLL1CLKFreq(void);
+uint32_t HAL_RCCEx_GetPLL2CLKFreq(void);
+uint32_t HAL_RCCEx_GetPLL3CLKFreq(void);
+uint32_t HAL_RCCEx_GetPLL4CLKFreq(void);
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+  * @{
+  */
+void     HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
+void     HAL_RCCEx_EnableLSECSS(void);
+void     HAL_RCCEx_DisableLSECSS(void);
+void     HAL_RCCEx_EnableLSECSS_IT(void);
+void     HAL_RCCEx_DisableLSECSS_IT(void);
+void     HAL_RCCEx_ReArmLSECSS(void);
+void     HAL_RCCEx_LSECSS_IRQHandler(void);
+void     HAL_RCCEx_LSECSS_Callback(void);
+HAL_StatusTypeDef HAL_RCCEx_PLLSSCGConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit,
+                                          const RCC_PLLSSCGInitTypeDef *pPLLSSCGInit);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros
+  * @{
+  */
+
+/** @defgroup RCCEx_IS_RCC_Definitions Private macros to check input parameters
+  * @{
+  */
+#define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
+  ((((__SELECTION__) & RCC_PERIPHCLK_FMC)         == RCC_PERIPHCLK_FMC)         || \
+   (((__SELECTION__) & RCC_PERIPHCLK_XSPI1)       == RCC_PERIPHCLK_XSPI1)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_XSPI2)       == RCC_PERIPHCLK_XSPI2)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_XSPI3)       == RCC_PERIPHCLK_XSPI3)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_CKPER)       == RCC_PERIPHCLK_CKPER)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_ADC)         == RCC_PERIPHCLK_ADC)         || \
+   (((__SELECTION__) & RCC_PERIPHCLK_ADF1)        == RCC_PERIPHCLK_ADF1)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_CSI)         == RCC_PERIPHCLK_CSI)         || \
+   (((__SELECTION__) & RCC_PERIPHCLK_DCMIPP)      == RCC_PERIPHCLK_DCMIPP)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_ETH1)        == RCC_PERIPHCLK_ETH1)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_ETH1PHY)     == RCC_PERIPHCLK_ETH1PHY)     || \
+   (((__SELECTION__) & RCC_PERIPHCLK_ETH1RX)      == RCC_PERIPHCLK_ETH1RX)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_ETH1TX)      == RCC_PERIPHCLK_ETH1TX)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_ETH1PTP)     == RCC_PERIPHCLK_ETH1PTP)     || \
+   (((__SELECTION__) & RCC_PERIPHCLK_FDCAN)       == RCC_PERIPHCLK_FDCAN)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_I3C1)        == RCC_PERIPHCLK_I3C1)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_I3C2)        == RCC_PERIPHCLK_I3C2)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2)      == RCC_PERIPHCLK_LPTIM2)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3)      == RCC_PERIPHCLK_LPTIM3)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_LPTIM4)      == RCC_PERIPHCLK_LPTIM4)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_LPTIM5)      == RCC_PERIPHCLK_LPTIM5)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_LPUART1)     == RCC_PERIPHCLK_LPUART1)     || \
+   (((__SELECTION__) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_MDF1)        == RCC_PERIPHCLK_MDF1)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_PSSI)        == RCC_PERIPHCLK_PSSI)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)         || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SPDIFRX1)    == RCC_PERIPHCLK_SPDIFRX1)    || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SPI1)        == RCC_PERIPHCLK_SPI1)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SPI2)        == RCC_PERIPHCLK_SPI2)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SPI3)        == RCC_PERIPHCLK_SPI3)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SPI4)        == RCC_PERIPHCLK_SPI4)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SPI5)        == RCC_PERIPHCLK_SPI5)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_SPI6)        == RCC_PERIPHCLK_SPI6)        || \
+   (((__SELECTION__) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)         || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)      || \
+   (((__SELECTION__) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_UART9)       == RCC_PERIPHCLK_UART9)       || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USART10)     == RCC_PERIPHCLK_USART10)     || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USBPHY1)     == RCC_PERIPHCLK_USBPHY1)     || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USBPHY2)     == RCC_PERIPHCLK_USBPHY2)     || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USBOTGHS1)   == RCC_PERIPHCLK_USBOTGHS1)   || \
+   (((__SELECTION__) & RCC_PERIPHCLK_USBOTGHS2)   == RCC_PERIPHCLK_USBOTGHS2))
+
+#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_ADCCLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_ADCCLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_ADCCLKSOURCE_IC7)  || \
+   ((__SOURCE__) == RCC_ADCCLKSOURCE_IC8)  || \
+   ((__SOURCE__) == RCC_ADCCLKSOURCE_MSI)  || \
+   ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)  || \
+   ((__SOURCE__) == RCC_ADCCLKSOURCE_PIN)  || \
+   ((__SOURCE__) == RCC_ADCCLKSOURCE_TIMG))
+
+#define IS_RCC_ADCDIVIDER(__VALUE__) \
+  ((1U <= (__VALUE__)) && ((__VALUE__) <= 256U))
+
+#define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_ADF1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_ADF1CLKSOURCE_IC7)  || \
+   ((__SOURCE__) == RCC_ADF1CLKSOURCE_IC8)  || \
+   ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSI)  || \
+   ((__SOURCE__) == RCC_ADF1CLKSOURCE_HSI)  || \
+   ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN)  || \
+   ((__SOURCE__) == RCC_ADF1CLKSOURCE_TIMG))
+
+#define IS_RCC_CKPERCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_CLKPCLKSOURCE_HSI) || \
+   ((__SOURCE__) == RCC_CLKPCLKSOURCE_MSI) || \
+   ((__SOURCE__) == RCC_CLKPCLKSOURCE_HSE) || \
+   ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC19) || \
+   ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC5) || \
+   ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC10) || \
+   ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_CLKPCLKSOURCE_IC20))
+
+#define IS_RCC_DCMIPPCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_DCMIPPCLKSOURCE_PCLK5) || \
+   ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_IC17)  || \
+   ((__SOURCE__) == RCC_DCMIPPCLKSOURCE_HSI))
+
+#define IS_RCC_ETH1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_ETH1CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_ETH1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_ETH1CLKSOURCE_IC12) || \
+   ((__SOURCE__) == RCC_ETH1CLKSOURCE_HSE))
+
+#define IS_RCC_ETH1PHYIF(__SOURCE__) \
+  (((__SOURCE__) == RCC_ETH1PHYIF_MII)   || \
+   ((__SOURCE__) == RCC_ETH1PHYIF_RGMII) || \
+   ((__SOURCE__) == RCC_ETH1PHYIF_RMII))
+
+#define IS_RCC_ETH1RXCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_ETH1RXCLKSOURCE_EXT)   || \
+   ((__SOURCE__) == RCC_ETH1RXCLKSOURCE_INT))
+
+#define IS_RCC_ETH1TXCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_ETH1TXCLKSOURCE_EXT)   || \
+   ((__SOURCE__) == RCC_ETH1TXCLKSOURCE_INT))
+
+#define IS_RCC_ETH1PTPCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_IC13) || \
+   ((__SOURCE__) == RCC_ETH1PTPCLKSOURCE_HSE))
+
+#define IS_RCC_ETH1PTPDIVIDER(__VALUE__) \
+  ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
+
+#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_FDCANCLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_FDCANCLKSOURCE_IC19)  || \
+   ((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE))
+
+#define IS_RCC_FMCCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_FMCCLKSOURCE_HCLK)  || \
+   ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_FMCCLKSOURCE_IC3) || \
+   ((__SOURCE__) == RCC_FMCCLKSOURCE_IC4))
+
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_I2C1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_I2C1CLKSOURCE_IC10) || \
+   ((__SOURCE__) == RCC_I2C1CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_I2C2CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_I2C2CLKSOURCE_IC10) || \
+   ((__SOURCE__) == RCC_I2C2CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
+
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_I2C3CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_I2C3CLKSOURCE_IC10) || \
+   ((__SOURCE__) == RCC_I2C3CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+
+#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_I2C4CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_I2C4CLKSOURCE_IC10) || \
+   ((__SOURCE__) == RCC_I2C4CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
+
+#define IS_RCC_I3C1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_I3C1CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_I3C1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_I3C1CLKSOURCE_IC10) || \
+   ((__SOURCE__) == RCC_I3C1CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_I3C1CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_I3C1CLKSOURCE_HSI))
+
+#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_I3C2CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_I3C2CLKSOURCE_IC10) || \
+   ((__SOURCE__) == RCC_I3C2CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_I3C2CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI))
+
+#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)   || \
+   ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_TIMG))
+
+#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK4) || \
+   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)   || \
+   ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_TIMG))
+
+#define IS_RCC_LPTIM3CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK4) || \
+   ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI)   || \
+   ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_TIMG))
+
+#define IS_RCC_LPTIM4CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_LPTIM4CLKSOURCE_PCLK4) || \
+   ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_LSI)   || \
+   ((__SOURCE__) == RCC_LPTIM4CLKSOURCE_TIMG))
+
+#define IS_RCC_LPTIM5CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_LPTIM5CLKSOURCE_PCLK4) || \
+   ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_IC15) || \
+   ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_LSI)   || \
+   ((__SOURCE__) == RCC_LPTIM5CLKSOURCE_TIMG))
+
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK4) || \
+   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_LTDCCLKSOURCE_PCLK5) || \
+   ((__SOURCE__) == RCC_LTDCCLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_LTDCCLKSOURCE_IC16)  || \
+   ((__SOURCE__) == RCC_LTDCCLKSOURCE_HSI))
+
+#define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_MDF1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_MDF1CLKSOURCE_IC7)  || \
+   ((__SOURCE__) == RCC_MDF1CLKSOURCE_IC8)  || \
+   ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSI)  || \
+   ((__SOURCE__) == RCC_MDF1CLKSOURCE_HSI)  || \
+   ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN)  || \
+   ((__SOURCE__) == RCC_MDF1CLKSOURCE_TIMG))
+
+#define IS_RCC_PSSICLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_PSSICLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_PSSICLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_PSSICLKSOURCE_IC20) || \
+   ((__SOURCE__) == RCC_PSSICLKSOURCE_HSI))
+
+#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SAI1CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SAI1CLKSOURCE_IC7)   || \
+   ((__SOURCE__) == RCC_SAI1CLKSOURCE_IC8)   || \
+   ((__SOURCE__) == RCC_SAI1CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)   || \
+   ((__SOURCE__) == RCC_SAI1CLKSOURCE_SPDIFRX1))
+
+#define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SAI2CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SAI2CLKSOURCE_IC7)   || \
+   ((__SOURCE__) == RCC_SAI2CLKSOURCE_IC8)   || \
+   ((__SOURCE__) == RCC_SAI2CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)   || \
+   ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIFRX1))
+
+#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_IC4)  || \
+   ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_IC5))
+
+#define IS_RCC_SDMMC2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SDMMC2CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_IC4)  || \
+   ((__SOURCE__) == RCC_SDMMC2CLKSOURCE_IC5))
+
+#define IS_RCC_SPDIFRX1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_IC7)   || \
+   ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_IC8)   || \
+   ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SPDIFRX1CLKSOURCE_PIN))
+
+#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SPI1CLKSOURCE_IC8)   || \
+   ((__SOURCE__) == RCC_SPI1CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
+
+#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SPI2CLKSOURCE_IC8)   || \
+   ((__SOURCE__) == RCC_SPI2CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
+
+#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SPI3CLKSOURCE_IC8)   || \
+   ((__SOURCE__) == RCC_SPI3CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
+
+#define IS_RCC_SPI4CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SPI4CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_SPI4CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SPI4CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_SPI4CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_SPI4CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
+
+#define IS_RCC_SPI5CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SPI5CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_SPI5CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SPI5CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_SPI5CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_SPI5CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
+
+#define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK4) || \
+   ((__SOURCE__) == RCC_SPI6CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_SPI6CLKSOURCE_IC8)   || \
+   ((__SOURCE__) == RCC_SPI6CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_SPI6CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)   || \
+   ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
+
+#define IS_RCC_TIMPRES(__VALUE__)  \
+  (((__VALUE__) == RCC_TIMPRES_DIV1) || \
+   ((__VALUE__) == RCC_TIMPRES_DIV2) || \
+   ((__VALUE__) == RCC_TIMPRES_DIV4) || \
+   ((__VALUE__) == RCC_TIMPRES_DIV8))
+
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_USART1CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_USART1CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_USART1CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_USART1CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_USART2CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_USART2CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_USART2CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_USART2CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_USART3CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_USART3CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_USART3CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_USART3CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
+
+#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_UART4CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_UART4CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_UART4CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_UART4CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
+
+#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_UART5CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_UART5CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_UART5CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_UART5CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
+
+#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_USART6CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_USART6CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_USART6CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_USART6CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI))
+
+#define IS_RCC_UART7CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_UART7CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_UART7CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_UART7CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_UART7CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_UART7CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_UART7CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_UART7CLKSOURCE_HSI))
+
+#define IS_RCC_UART8CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_UART8CLKSOURCE_PCLK1) || \
+   ((__SOURCE__) == RCC_UART8CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_UART8CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_UART8CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_UART8CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_UART8CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_UART8CLKSOURCE_HSI))
+
+#define IS_RCC_UART9CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_UART9CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_UART9CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_UART9CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_UART9CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_UART9CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_UART9CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_UART9CLKSOURCE_HSI))
+
+#define IS_RCC_USART10CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_USART10CLKSOURCE_PCLK2) || \
+   ((__SOURCE__) == RCC_USART10CLKSOURCE_CLKP)  || \
+   ((__SOURCE__) == RCC_USART10CLKSOURCE_IC9)   || \
+   ((__SOURCE__) == RCC_USART10CLKSOURCE_IC14)  || \
+   ((__SOURCE__) == RCC_USART10CLKSOURCE_LSE)   || \
+   ((__SOURCE__) == RCC_USART10CLKSOURCE_MSI)   || \
+   ((__SOURCE__) == RCC_USART10CLKSOURCE_HSI))
+
+#define IS_RCC_USBPHY1CLKSOURCE(__SOURCE__)                  \
+  (((__SOURCE__) == RCC_USBPHY1REFCLKSOURCE_OTGPHY1)      || \
+   ((__SOURCE__) == RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT)   || \
+   ((__SOURCE__) == RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT_DIV2))
+
+#define IS_RCC_USBPHY2CLKSOURCE(__SOURCE__)                  \
+  (((__SOURCE__) == RCC_USBPHY2REFCLKSOURCE_OTGPHY2)      || \
+   ((__SOURCE__) == RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT)   || \
+   ((__SOURCE__) == RCC_USBPHY2REFCLKSOURCE_HSE_DIRECT_DIV2))
+
+#define IS_RCC_USBOTGHS1CLKSOURCE(__SOURCE__)                \
+  (((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIV2)      || \
+   ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_CLKP)          || \
+   ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_IC15)          || \
+   ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT)    || \
+   ((__SOURCE__) == RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2))
+
+#define IS_RCC_USBOTGHS2CLKSOURCE(__SOURCE__)                \
+  (((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIV2)      || \
+   ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_CLKP)          || \
+   ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_IC15)          || \
+   ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT)    || \
+   ((__SOURCE__) == RCC_USBOTGHS2CLKSOURCE_HSE_DIRECT_DIV2))
+
+#define IS_RCC_XSPI1CLKSOURCE(__SOURCE__)       \
+  (((__SOURCE__) == RCC_XSPI1CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_XSPI1CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_XSPI1CLKSOURCE_IC3)  || \
+   ((__SOURCE__) == RCC_XSPI1CLKSOURCE_IC4))
+
+#define IS_RCC_XSPI2CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_XSPI2CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_XSPI2CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_XSPI2CLKSOURCE_IC3)  || \
+   ((__SOURCE__) == RCC_XSPI2CLKSOURCE_IC4))
+
+#define IS_RCC_XSPI3CLKSOURCE(__SOURCE__) \
+  (((__SOURCE__) == RCC_XSPI3CLKSOURCE_HCLK) || \
+   ((__SOURCE__) == RCC_XSPI3CLKSOURCE_CLKP) || \
+   ((__SOURCE__) == RCC_XSPI3CLKSOURCE_IC3)  || \
+   ((__SOURCE__) == RCC_XSPI3CLKSOURCE_IC4))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_RCC_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rif.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rif.h
new file mode 100644
index 000000000..210dd1822
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rif.h
@@ -0,0 +1,1545 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rif.h
+  * @author  MCD Application Team
+  * @brief   Header file of RIF HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RIF_H
+#define STM32N6xx_HAL_RIF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RIF
+  * @{
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RIF_EXPORTED_CONSTANTS_COMMON RIF exported constants - Common
+  * @{
+  */
+
+/** @defgroup RIF_COMPARTMENT_ID RIF CID number definition
+  * @{
+  */
+#define RIF_CID_NONE                       0x00000000U
+#define RIF_CID_0                          0x00000001U
+#define RIF_CID_1                          0x00000002U
+#define RIF_CID_2                          0x00000004U
+#define RIF_CID_3                          0x00000008U
+#define RIF_CID_4                          0x00000010U
+#define RIF_CID_5                          0x00000020U
+#define RIF_CID_6                          0x00000040U
+#define RIF_CID_7                          0x00000080U
+/**
+  * @}
+  */
+
+/** @defgroup RIF_MASTER_INDEX RIF Master index
+  * @{
+  */
+#define RIF_MASTER_INDEX_ETR               0U
+#if defined(NPU_PRESENT)
+#define RIF_MASTER_INDEX_NPU               1U
+#endif /* defined(NPU_PRESENT) */
+#define RIF_MASTER_INDEX_SDMMC1            2U
+#define RIF_MASTER_INDEX_SDMMC2            3U
+#define RIF_MASTER_INDEX_OTG1              4U
+#define RIF_MASTER_INDEX_OTG2              5U
+#define RIF_MASTER_INDEX_ETH1              6U
+#define RIF_MASTER_INDEX_GPU2D             7U
+#define RIF_MASTER_INDEX_DMA2D             8U
+#define RIF_MASTER_INDEX_DCMIPP            9U
+#define RIF_MASTER_INDEX_LTDC1             10U
+#define RIF_MASTER_INDEX_LTDC2             11U
+#define RIF_MASTER_INDEX_VENC              12U
+/**
+  * @}
+  */
+
+/** @defgroup RIF_PERIPHERAL_INDEX RIF RISUP Peripheral index
+  * @{
+  */
+/** @defgroup RIF_PERIPH_PERIPHERAL_INDEX RIF RISUP Peripheral index
+  * @{
+  */
+#define RIF_RISC_PERIPH_INDEX_SPI1         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC0_Pos)
+#define RIF_RISC_PERIPH_INDEX_SPI2         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC1_Pos)
+#define RIF_RISC_PERIPH_INDEX_SPI3         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC2_Pos)
+#define RIF_RISC_PERIPH_INDEX_SPI4         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC3_Pos)
+#define RIF_RISC_PERIPH_INDEX_SPI5         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC4_Pos)
+#define RIF_RISC_PERIPH_INDEX_SPI6         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC5_Pos)
+#define RIF_RISC_PERIPH_INDEX_SAI1         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC6_Pos)
+#define RIF_RISC_PERIPH_INDEX_SAI2         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC8_Pos)
+#define RIF_RISC_PERIPH_INDEX_I2C1         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC9_Pos)
+#define RIF_RISC_PERIPH_INDEX_I2C2         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC10_Pos)
+#define RIF_RISC_PERIPH_INDEX_I2C3         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC11_Pos)
+#define RIF_RISC_PERIPH_INDEX_I2C4         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC12_Pos)
+#define RIF_RISC_PERIPH_INDEX_I3C1         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC13_Pos)
+#define RIF_RISC_PERIPH_INDEX_I3C2         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC14_Pos)
+#define RIF_RISC_PERIPH_INDEX_USART1       (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC15_Pos)
+#define RIF_RISC_PERIPH_INDEX_USART2       (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC16_Pos)
+#define RIF_RISC_PERIPH_INDEX_USART3       (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC17_Pos)
+#define RIF_RISC_PERIPH_INDEX_UART4        (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC18_Pos)
+#define RIF_RISC_PERIPH_INDEX_UART5        (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC19_Pos)
+#define RIF_RISC_PERIPH_INDEX_USART6       (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC20_Pos)
+#define RIF_RISC_PERIPH_INDEX_UART7        (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC21_Pos)
+#define RIF_RISC_PERIPH_INDEX_UART8        (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC22_Pos)
+#define RIF_RISC_PERIPH_INDEX_UART9        (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC23_Pos)
+#define RIF_RISC_PERIPH_INDEX_USART10      (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC24_Pos)
+#define RIF_RISC_PERIPH_INDEX_LPUART1      (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC25_Pos)
+#define RIF_RISC_PERIPH_INDEX_FDCAN1       (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC26_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM1         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC27_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM2         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC28_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM3         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC29_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM4         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC30_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM5         (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC31_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM6         (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC0_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM7         (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC1_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM8         (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC2_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM9         (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC3_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM10        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC4_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM11        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC5_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM12        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC6_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM13        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC7_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM14        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC8_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM15        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC9_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM16        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC10_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM17        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC11_Pos)
+#define RIF_RISC_PERIPH_INDEX_TIM18        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC12_Pos)
+#define RIF_RISC_PERIPH_INDEX_GFXTIM       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC13_Pos)
+#define RIF_RISC_PERIPH_INDEX_LPTIM1       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC14_Pos)
+#define RIF_RISC_PERIPH_INDEX_LPTIM2       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC15_Pos)
+#define RIF_RISC_PERIPH_INDEX_LPTIM3       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC16_Pos)
+#define RIF_RISC_PERIPH_INDEX_LPTIM4       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC17_Pos)
+#define RIF_RISC_PERIPH_INDEX_LPTIM5       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC18_Pos)
+#define RIF_RISC_PERIPH_INDEX_ADF1         (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC19_Pos)
+#define RIF_RISC_PERIPH_INDEX_MDF1         (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC20_Pos)
+#define RIF_RISC_PERIPH_INDEX_SDMMC1       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC21_Pos)
+#define RIF_RISC_PERIPH_INDEX_SDMMC2       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC22_Pos)
+#define RIF_RISC_PERIPH_INDEX_MDIOS        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC23_Pos)
+#define RIF_RISC_PERIPH_INDEX_OTG1HS       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC24_Pos)
+#define RIF_RISC_PERIPH_INDEX_OTG2HS       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC25_Pos)
+#define RIF_RISC_PERIPH_INDEX_UCPD1        (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC26_Pos)
+#define RIF_RISC_PERIPH_INDEX_ETH1         (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC28_Pos)
+#define RIF_RISC_PERIPH_INDEX_SPDIFRX      (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC29_Pos)
+#define RIF_RISC_PERIPH_INDEX_SYSCFG       (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC30_Pos)
+#define RIF_RISC_PERIPH_INDEX_ADC12        (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC0_Pos)
+#define RIF_RISC_PERIPH_INDEX_VREFBUF      (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC1_Pos)
+#define RIF_RISC_PERIPH_INDEX_CRC          (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC3_Pos)
+#define RIF_RISC_PERIPH_INDEX_IWDG         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC4_Pos)
+#define RIF_RISC_PERIPH_INDEX_WWDG         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC5_Pos)
+#define RIF_RISC_PERIPH_INDEX_RNG          (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC12_Pos)
+#define RIF_RISC_PERIPH_INDEX_PKA          (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC13_Pos)
+#if defined(CRYP)
+#define RIF_RISC_PERIPH_INDEX_SAES         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC14_Pos)
+#endif /* defined(CRYP) */
+#define RIF_RISC_PERIPH_INDEX_HASH         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC15_Pos)
+#if defined(CRYP)
+#define RIF_RISC_PERIPH_INDEX_CRYP         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC16_Pos)
+#define RIF_RISC_PERIPH_INDEX_MCE1         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC17_Pos)
+#define RIF_RISC_PERIPH_INDEX_MCE2         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC18_Pos)
+#define RIF_RISC_PERIPH_INDEX_MCE3         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC19_Pos)
+#define RIF_RISC_PERIPH_INDEX_MCE4         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC20_Pos)
+#endif /* defined(CRYP) */
+#define RIF_RISC_PERIPH_INDEX_XSPI1        (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC22_Pos)
+#define RIF_RISC_PERIPH_INDEX_XSPI2        (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC23_Pos)
+#define RIF_RISC_PERIPH_INDEX_XSPI3        (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC24_Pos)
+#define RIF_RISC_PERIPH_INDEX_XSPIM        (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC25_Pos)
+#define RIF_RISC_PERIPH_INDEX_FMC          (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC26_Pos)
+#define RIF_RISC_PERIPH_INDEX_CSI          (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC28_Pos)
+#define RIF_RISC_PERIPH_INDEX_DCMIPP       (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC29_Pos)
+#define RIF_RISC_PERIPH_INDEX_DCMI         (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC30_Pos)
+#define RIF_RISC_PERIPH_INDEX_JPEG         (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC0_Pos)
+#define RIF_RISC_PERIPH_INDEX_VENC         (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC1_Pos)
+#define RIF_RISC_PERIPH_INDEX_ICACHE       (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC2_Pos)
+#define RIF_RISC_PERIPH_INDEX_GPU2D        (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC3_Pos)
+#define RIF_RISC_PERIPH_INDEX_GFXMMU       (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC4_Pos)
+#define RIF_RISC_PERIPH_INDEX_DMA2D        (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC5_Pos)
+#define RIF_RISC_PERIPH_INDEX_LTDC         (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC6_Pos)
+#define RIF_RISC_PERIPH_INDEX_LTDCL1       (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC7_Pos)
+#define RIF_RISC_PERIPH_INDEX_LTDCL2       (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC8_Pos)
+#if defined(NPU_PRESENT)
+#define RIF_RISC_PERIPH_INDEX_NPU          (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC10_Pos)
+#endif /* defined(NPU_PRESENT) */
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RCC_PERIPHERAL_INDEX RIF RCC Security Control Peripheral index
+  * @{
+  */
+#define RIF_RCC_PERIPH_INDEX_GPDMA1        (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC2_Pos)
+#define RIF_RCC_PERIPH_INDEX_HPDMA1        (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC3_Pos)
+#define RIF_RCC_PERIPH_INDEX_RTC           (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC5_Pos)
+#define RIF_RCC_PERIPH_INDEX_AXISRAM1      (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC12_Pos)
+#define RIF_RCC_PERIPH_INDEX_AXISRAM2      (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC13_Pos)
+#define RIF_RCC_PERIPH_INDEX_FLEXRAM       (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC17_Pos)
+#define RIF_RCC_PERIPH_INDEX_CACHEAXIRAM   (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC18_Pos)
+#define RIF_RCC_PERIPH_INDEX_VENCRAM       (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC19_Pos)
+#if defined(NPU_PRESENT)
+#define RIF_RCC_PERIPH_INDEX_CACHECONFIG   (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC25_Pos)
+#endif /* defined(NPU_PRESENT) */
+#define RIF_RCC_PERIPH_INDEX_AHBRAM1       (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC27_Pos)
+#define RIF_RCC_PERIPH_INDEX_AHBRAM2       (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC28_Pos)
+#define RIF_RCC_PERIPH_INDEX_BKPRAM        (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC29_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOA         (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC31_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOB         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC0_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOC         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC1_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOD         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC2_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOE         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC3_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOF         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC4_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOG         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC5_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOH         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC6_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPION         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC8_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOO         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC9_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOP         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC10_Pos)
+#define RIF_RCC_PERIPH_INDEX_GPIOQ         (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC11_Pos)
+#define RIF_RCC_PERIPH_INDEX_DTS           (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC13_Pos)
+#define RIF_RCC_PERIPH_INDEX_MCO1          (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC14_Pos)
+#define RIF_RCC_PERIPH_INDEX_MCO2          (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC15_Pos)
+#if defined(NPU_PRESENT)
+#define RIF_RCC_PERIPH_INDEX_NPURAM0       (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC17_Pos)
+#define RIF_RCC_PERIPH_INDEX_NPURAM1       (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC18_Pos)
+#define RIF_RCC_PERIPH_INDEX_NPURAM2       (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC19_Pos)
+#define RIF_RCC_PERIPH_INDEX_NPURAM3       (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC20_Pos)
+#endif /* defined(NPU_PRESENT) */
+#define RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP   (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC22_Pos)
+#define RIF_RCC_PERIPH_INDEX_XSPIPHY1      (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC23_Pos)
+#define RIF_RCC_PERIPH_INDEX_XSPIPHY2      (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC24_Pos)
+#define RIF_RCC_PERIPH_INDEX_HDP           (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC27_Pos)
+#define RIF_RCC_PERIPH_INDEX_RAMCFG        (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC30_Pos)
+/**
+  * @}
+  */
+
+/** @defgroup RIF_AWARE_PERIPHERAL_INDEX RIF-aware Peripheral index
+  * @{
+  */
+#define RIF_AWARE_PERIPH_INDEX_CM55        (RIF_PERIPH_REG4 | IAC_IERx_IAIE0_Pos)
+#define RIF_AWARE_PERIPH_INDEX_EXTI        (RIF_PERIPH_REG4 | IAC_IERx_IAIE1_Pos)
+#define RIF_AWARE_PERIPH_INDEX_GPDMA1      RIF_RCC_PERIPH_INDEX_GPDMA1
+#define RIF_AWARE_PERIPH_INDEX_HPDMA1      RIF_RCC_PERIPH_INDEX_HPDMA1
+#define RIF_AWARE_PERIPH_INDEX_RTC         RIF_RCC_PERIPH_INDEX_RTC
+#define RIF_AWARE_PERIPH_INDEX_TAMP        (RIF_PERIPH_REG4 | IAC_IERx_IAIE6_Pos)
+#define RIF_AWARE_PERIPH_INDEX_BSEC        (RIF_PERIPH_REG4 | IAC_IERx_IAIE7_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RCC         (RIF_PERIPH_REG4 | IAC_IERx_IAIE8_Pos)
+#define RIF_AWARE_PERIPH_INDEX_PWR         (RIF_PERIPH_REG4 | IAC_IERx_IAIE9_Pos)
+#define RIF_AWARE_PERIPH_INDEX_IAC         (RIF_PERIPH_REG4 | IAC_IERx_IAIE10_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RISAF1      (RIF_PERIPH_REG4 | IAC_IERx_IAIE11_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RISAF2      RIF_RCC_PERIPH_INDEX_AXISRAM1
+#define RIF_AWARE_PERIPH_INDEX_RISAF3      RIF_RCC_PERIPH_INDEX_AXISRAM2
+#if defined(NPU_PRESENT)
+#define RIF_AWARE_PERIPH_INDEX_RISAF4      (RIF_PERIPH_REG4 | IAC_IERx_IAIE14_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RISAF5      (RIF_PERIPH_REG4 | IAC_IERx_IAIE15_Pos)
+#endif /* if defined(NPU_PRESENT) */
+#define RIF_AWARE_PERIPH_INDEX_RISAF6      (RIF_PERIPH_REG4 | IAC_IERx_IAIE16_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RISAF7      RIF_RCC_PERIPH_INDEX_FLEXRAM
+#define RIF_AWARE_PERIPH_INDEX_RISAF8      RIF_RCC_PERIPH_INDEX_CACHEAXIRAM
+#define RIF_AWARE_PERIPH_INDEX_RISAF9      RIF_RCC_PERIPH_INDEX_VENCRAM
+#define RIF_AWARE_PERIPH_INDEX_RISAF11     (RIF_PERIPH_REG4 | IAC_IERx_IAIE21_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RISAF12     (RIF_PERIPH_REG4 | IAC_IERx_IAIE22_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RISAF13     (RIF_PERIPH_REG4 | IAC_IERx_IAIE23_Pos)
+#define RIF_AWARE_PERIPH_INDEX_RISAF14     (RIF_PERIPH_REG4 | IAC_IERx_IAIE24_Pos)
+#if defined(NPU_PRESENT)
+#define RIF_AWARE_PERIPH_INDEX_RISAF15     RIF_RCC_PERIPH_INDEX_CACHECONFIG
+#endif /* if defined(NPU_PRESENT) */
+#define RIF_AWARE_PERIPH_INDEX_RISAF21     RIF_RCC_PERIPH_INDEX_AHBRAM1
+#define RIF_AWARE_PERIPH_INDEX_RISAF22     RIF_RCC_PERIPH_INDEX_AHBRAM2
+#define RIF_AWARE_PERIPH_INDEX_RISAF23     RIF_RCC_PERIPH_INDEX_BKPRAM
+#define RIF_AWARE_PERIPH_INDEX_RIFSC       (RIF_PERIPH_REG4 | IAC_IERx_IAIE30_Pos)
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/** @defgroup RIF_SEC_PRIV RIF Secure Privileged attributes definitions
+  * @{
+  */
+#define RIF_ATTRIBUTE_NSEC                 0x00000000U
+#define RIF_ATTRIBUTE_SEC                  0x00000001U
+#define RIF_ATTRIBUTE_NPRIV                0x00000000U
+#define RIF_ATTRIBUTE_PRIV                 0x00000002U
+/**
+  * @}
+  */
+
+/** @defgroup RIF_ACCESS_TYPE RIF Access type definitions
+  * @{
+  */
+#define RIF_ACCTYPE_READ_FETCH             0U
+#define RIF_ACCTYPE_WRITE                  1U
+/**
+  * @}
+  */
+
+/** @defgroup RIF_LOCK_STATE RIF Lock states definitions
+  * @{
+  */
+#define RIF_LOCK_DISABLE                   0U
+#define RIF_LOCK_ENABLE                    RIFSC_RIMC_CR_GLOCK
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RIF_EXPORTED_CONSTANTS_RISAF RIF Exported Constants - RISAF
+  * @{
+  */
+
+/** @defgroup RIF_RISAF_REGION RISAF Base region definitions
+  * @{
+  */
+#define RISAF_REGION_1                     0U
+#define RISAF_REGION_2                     1U
+#define RISAF_REGION_3                     2U
+#define RISAF_REGION_4                     3U
+#define RISAF_REGION_5                     4U
+#define RISAF_REGION_6                     5U
+#define RISAF_REGION_7                     6U
+#define RISAF_REGION_8                     7U
+#define RISAF_REGION_9                     8U
+#define RISAF_REGION_10                    9U
+#define RISAF_REGION_11                    10U
+#define RISAF_REGION_12                    11U
+#define RISAF_REGION_13                    12U
+#define RISAF_REGION_14                    13U
+#define RISAF_REGION_15                    14U
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RISAF_GRANULARITY RISAF granularity definitions
+  * @{
+  */
+#if !defined(NPU_PRESENT)
+#define RISAF1_GRANULARITY                 0x1000U
+#define RISAF2_GRANULARITY                 0x1000U
+#define RISAF3_GRANULARITY                 0x1000U
+#define RISAF6_GRANULARITY                 0x1000U
+#define RISAF7_GRANULARITY                 0x1000U
+#define RISAF8_GRANULARITY                 0x1000U
+#define RISAF9_GRANULARITY                 0x1000U
+#define RISAF11_GRANULARITY                0x1000U
+#define RISAF12_GRANULARITY                0x1000U
+#define RISAF13_GRANULARITY                0x1000U
+#define RISAF14_GRANULARITY                0x1000U
+#define RISAF21_GRANULARITY                0x0200U
+#define RISAF22_GRANULARITY                0x0200U
+#define RISAF23_GRANULARITY                0x0200U
+#else
+#define RISAF1_GRANULARITY                 0x1000U
+#define RISAF2_GRANULARITY                 0x1000U
+#define RISAF3_GRANULARITY                 0x1000U
+#define RISAF4_GRANULARITY                 0x1000U
+#define RISAF5_GRANULARITY                 0x1000U
+#define RISAF6_GRANULARITY                 0x1000U
+#define RISAF7_GRANULARITY                 0x1000U
+#define RISAF8_GRANULARITY                 0x1000U
+#define RISAF9_GRANULARITY                 0x1000U
+#define RISAF11_GRANULARITY                0x1000U
+#define RISAF12_GRANULARITY                0x1000U
+#define RISAF13_GRANULARITY                0x1000U
+#define RISAF14_GRANULARITY                0x1000U
+#define RISAF15_GRANULARITY                0x0004U
+#define RISAF21_GRANULARITY                0x0200U
+#define RISAF22_GRANULARITY                0x0200U
+#define RISAF23_GRANULARITY                0x0200U
+#endif /* !defined(NPU_PRESENT) */
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RISAF_ADDSPACE RISAF address space sizes definitions
+  * @{
+  */
+#if !defined(NPU_PRESENT)
+#define RISAF1_LIMIT_ADDRESS_SPACE_SIZE         0x3FFFFFFFU
+#define RISAF2_LIMIT_ADDRESS_SPACE_SIZE         0x000FFFFFU
+#define RISAF3_LIMIT_ADDRESS_SPACE_SIZE         0x000FFFFFU
+#define RISAF6_LIMIT_ADDRESS_SPACE_SIZE         0xFFFFFFFFU
+#define RISAF7_LIMIT_ADDRESS_SPACE_SIZE         0x0007FFFFU
+#define RISAF8_LIMIT_ADDRESS_SPACE_SIZE         0x0003FFFFU
+#define RISAF9_LIMIT_ADDRESS_SPACE_SIZE         0x0001FFFFU
+#define RISAF11_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF12_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF13_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF14_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF21_LIMIT_ADDRESS_SPACE_SIZE        0x00001FFFU
+#define RISAF22_LIMIT_ADDRESS_SPACE_SIZE        0x00001FFFU
+#define RISAF23_LIMIT_ADDRESS_SPACE_SIZE        0x00000FFFU
+#else
+#define RISAF1_LIMIT_ADDRESS_SPACE_SIZE         0x3FFFFFFFU
+#define RISAF2_LIMIT_ADDRESS_SPACE_SIZE         0x000FFFFFU
+#define RISAF3_LIMIT_ADDRESS_SPACE_SIZE         0x000FFFFFU
+#define RISAF4_LIMIT_ADDRESS_SPACE_SIZE         0xFFFFFFFFU
+#define RISAF5_LIMIT_ADDRESS_SPACE_SIZE         0xFFFFFFFFU
+#define RISAF6_LIMIT_ADDRESS_SPACE_SIZE         0xFFFFFFFFU
+#define RISAF7_LIMIT_ADDRESS_SPACE_SIZE         0x0007FFFFU
+#define RISAF8_LIMIT_ADDRESS_SPACE_SIZE         0x0003FFFFU
+#define RISAF9_LIMIT_ADDRESS_SPACE_SIZE         0x0001FFFFU
+#define RISAF11_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF12_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF13_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF14_LIMIT_ADDRESS_SPACE_SIZE        0x0FFFFFFFU
+#define RISAF15_LIMIT_ADDRESS_SPACE_SIZE        0x00000FFFU
+#define RISAF21_LIMIT_ADDRESS_SPACE_SIZE        0x00001FFFU
+#define RISAF22_LIMIT_ADDRESS_SPACE_SIZE        0x00001FFFU
+#define RISAF23_LIMIT_ADDRESS_SPACE_SIZE        0x00000FFFU
+#endif /* !defined(NPU_PRESENT) */
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RISAF_SUBREGION RIF subregion definitions
+  * @{
+  */
+#define RISAF_SUBREGION_A                  0U
+#define RISAF_SUBREGION_B                  1U
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RISAF_FILTERING_MODE RISAF Filtering mode definitions
+  * @{
+  */
+#define RISAF_FILTER_DISABLE               0U
+#define RISAF_FILTER_ENABLE                RISAF_REGx_CFGR_BREN
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RISAF_DELEGATION_MODE RISAF Delegation mode definitions
+  * @{
+  */
+#define RISAF_DELEGATION_DISABLE           0U
+#define RISAF_DELEGATION_ENABLE            RISAF_REGx_zNESTR_DCEN
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RISAF_READ_WRITE RISAF Read/Write definitions
+  * @{
+  */
+#define RISAF_READ_DISABLE                 0U
+#define RISAF_READ_ENABLE                  RISAF_REGx_zCFGR_RDEN
+#define RISAF_WRITE_DISABLE                0U
+#define RISAF_WRITE_ENABLE                 RISAF_REGx_zCFGR_WREN
+/**
+  * @}
+  */
+
+/** @defgroup RIF_RISAF_ILLEGAL_ACCESS RISAF Illegal Access definitions
+  * @{
+  */
+#define RISAF_ILLEGAL_ACCESS_NONE          0U
+#define RISAF_ILLEGAL_CONFIGURATION_ACCESS RISAF_IASR_CAEF
+#define RISAF_ILLEGAL_ACCESS               RISAF_IASR_IAEF
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RIF_Exported_Types RIF Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RIFSC Master CID attributes configuration structure
+  */
+typedef struct
+{
+  uint32_t MasterCID; /*!< One of @ref RIF_COMPARTMENT_ID        */
+  uint32_t SecPriv;   /*!< A combination of @ref RIF_SEC_PRIV    */
+} RIMC_MasterConfig_t;
+
+/**
+  * @brief  RISAF base region configuration structure
+  */
+typedef struct
+{
+  uint32_t Filtering;       /*!< One of @ref RIF_RISAF_FILTERING_MODE      */
+  uint32_t Secure;          /*!< One of @ref RIF_SEC_PRIV                  */
+  uint32_t PrivWhitelist;   /*!< A combination of @ref RIF_COMPARTMENT_ID  */
+  uint32_t ReadWhitelist;   /*!< A combination of @ref RIF_COMPARTMENT_ID  */
+  uint32_t WriteWhitelist;  /*!< A combination of @ref RIF_COMPARTMENT_ID  */
+  uint32_t StartAddress;    /*!< Base region start, address offset to the base address of the protected address space */
+  uint32_t EndAddress;      /*!< Base region end, address offset to the base address of the protected address space   */
+} RISAF_BaseRegionConfig_t;
+
+/**
+  * @brief  RISAF subregion configuration structure
+  */
+typedef struct
+{
+  uint32_t Filtering;    /*!< One of @ref RIF_RISAF_FILTERING_MODE           */
+  uint32_t CID;          /*!< One of @ref RIF_COMPARTMENT_ID                 */
+  uint32_t SecPriv;      /*!< A combination of @ref RIF_SEC_PRIV             */
+  uint32_t ReadWrite;    /*!< A combination of @ref RIF_RISAF_READ_WRITE     */
+  uint32_t Lock;         /*!< One of @ref RIF_LOCK_STATE                     */
+  uint32_t StartAddress; /*!< Subregion start, address offset to the base address of the protected address space */
+  uint32_t EndAddress;   /*!< Subregion end, address offset to the base address of the protected address space   */
+} RISAF_SubRegionConfig_t;
+
+/**
+  * @brief  RISAF delegation structure
+  */
+typedef struct
+{
+  uint32_t Delegation;   /*!< Enable or Disable               */
+  uint32_t DelegatedCID; /*!< One of @ref RIF_COMPARTMENT_ID  */
+} RISAF_DelegationConfig_t;
+
+/**
+  * @brief  RISAF illegal access detection structure
+  */
+/**
+  * @brief  RISAF illegal access detection data structure
+  */
+typedef struct
+{
+  uint32_t CID;        /*!< One of @ref RIF_COMPARTMENT_ID      */
+  uint32_t SecPriv;    /*!< A combination of @ref RIF_SEC_PRIV  */
+  uint32_t AccessType; /*!< One of @ref RIF_ACCESS_TYPE         */
+  uint32_t Address;
+} RISAF_IllegalAccessData_t;
+
+typedef struct
+{
+  uint32_t ErrorType; /*!< One of @ref RIF_RISAF_ILLEGAL_ACCESS      */
+  RISAF_IllegalAccessData_t Data;
+} RISAF_IllegalAccess_t;
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+
+/** @defgroup RIF_REG_INDEX RIF register index definition
+  * @{
+  */
+/* Composition definition for Peripheral identifier parameter (PeriphId) used in
+ * RIF RISC and IAC related functions.
+ * Bitmap Definition
+ *   bits[31:28] Field "register". Define the register index a peripheral belongs to.
+ *   bits[4:0]   Field "bit position". Define the bit position within the
+ *               register dedicated to the peripheral, value from 0 to 31.
+ */
+#define RIF_PERIPH_REG_SHIFT               28U
+#define RIF_PERIPH_REG                     0xF0000000U
+#define RIF_PERIPH_REG0                    0x00000000U
+#define RIF_PERIPH_REG1                    0x10000000U
+#define RIF_PERIPH_REG2                    0x20000000U
+#define RIF_PERIPH_REG3                    0x30000000U
+#define RIF_PERIPH_REG4                    0x40000000U
+#define RIF_PERIPH_REG5                    0x50000000U
+#define RIF_PERIPH_BIT_POSITION            0x0000001FU
+/**
+  * @}
+  */
+
+/** @defgroup RIF_MASK RIF register masks
+  * @{
+  */
+#define RIF_CID_MASK                       0x000000FFU
+#define RIF_ATTRIBUTE_MASK                 0x00000003U
+#define RISAF_READ_WRITE_MASK              (RISAF_READ_ENABLE | RISAF_WRITE_ENABLE)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RIF_Private_Macros_Common RIF Private Macros - Common
+  * @{
+  */
+#define IS_RIF_CID(__CID__)  (((uint32_t)(__CID__) & ~RIF_CID_MASK) == 0x00U)
+
+#define IS_RIF_SINGLE_CID(__CID__)   (((__CID__) == RIF_CID_0)  || \
+                                      ((__CID__) == RIF_CID_1)  || \
+                                      ((__CID__) == RIF_CID_2)  || \
+                                      ((__CID__) == RIF_CID_3)  || \
+                                      ((__CID__) == RIF_CID_4)  || \
+                                      ((__CID__) == RIF_CID_5)  || \
+                                      ((__CID__) == RIF_CID_6)  || \
+                                      ((__CID__) == RIF_CID_7))
+
+#define IS_RIF_MASTER_CID(__CID__)  (((uint32_t)(__CID__) != RIF_CID_7) && \
+                                     (((uint32_t)(__CID__) & ~RIF_CID_MASK) == 0x00U))
+
+
+#if defined(NPU_PRESENT)
+#define IS_RIF_MASTER_INDEX(__INDEX__)  (((__INDEX__) == RIF_MASTER_INDEX_ETR)    || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_NPU)    || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_SDMMC1) || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_SDMMC2) || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_OTG1)   || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_OTG2)   || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_ETH1)   || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_GPU2D)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_DMA2D)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_DCMIPP) || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_LTDC1)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_LTDC2)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_VENC))
+#else
+#define IS_RIF_MASTER_INDEX(__INDEX__)  (((__INDEX__) == RIF_MASTER_INDEX_ETR)    || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_SDMMC1) || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_SDMMC2) || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_OTG1)   || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_OTG2)   || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_ETH1)   || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_GPU2D)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_DMA2D)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_DCMIPP) || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_LTDC1)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_LTDC2)  || \
+                                         ((__INDEX__) == RIF_MASTER_INDEX_VENC))
+#endif /* defined(NPU_PRESENT) */
+
+#if !defined(NPU_PRESENT) && !defined(CRYP)
+#define IS_RIF_RISC_PERIPH_INDEX(__INDEX__)  (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2))
+
+#define IS_RIF_RCC_PERIPH_INDEX(__INDEX__)   (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG))
+
+#define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC))
+#endif /* !defined(NPU_PRESENT) && !defined(CRYP) */
+
+#if defined(NPU_PRESENT) && !defined(CRYP)
+#define IS_RIF_RISC_PERIPH_INDEX(__INDEX__)  (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_NPU))
+
+#define IS_RIF_RCC_PERIPH_INDEX(__INDEX__)   (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHECONFIG)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM0)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM1)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM2)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM3)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG))
+
+#define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF4)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF5)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF15)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC))
+#endif /* defined(NPU_PRESENT) && !defined(CRYP) */
+
+#if !defined(NPU_PRESENT) && defined(CRYP)
+#define IS_RIF_RISC_PERIPH_INDEX(__INDEX__)  (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAES)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRYP)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2))
+
+#define IS_RIF_RCC_PERIPH_INDEX(__INDEX__)   (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG))
+
+#define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC))
+#endif /* !defined(NPU_PRESENT) && defined(CRYP) */
+
+#if defined(NPU_PRESENT) && defined(CRYP)
+#define IS_RIF_RISC_PERIPH_INDEX(__INDEX__)  (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF)       || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAES)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRYP)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE1)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE2)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE3)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE4)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI)           || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D)         || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC)          || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2)        || \
+                                              ((__INDEX__) == RIF_RISC_PERIPH_INDEX_NPU))
+
+#define IS_RIF_RCC_PERIPH_INDEX(__INDEX__)   (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHECONFIG)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM)         || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ)          || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2)           || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM0)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM1)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM2)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM3)        || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP)    || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2)       || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP)            || \
+                                              ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG))
+
+#define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC)         || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC)          || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF4)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF5)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9)       || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF15)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23)      || \
+                                              ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC))
+#endif /* defined(NPU_PRESENT) && defined(CRYP) */
+
+#define IS_RIF_SEC_PRIV_ATTRIBUTE(__ATTRIBUTE__)  (((uint32_t)(__ATTRIBUTE__) & ~RIF_ATTRIBUTE_MASK) == 0x00U)
+
+#define IS_RIF_ACCESS_TYPE(__ACCTYPE__)  (((__ACCTYPE__) == RIF_ACCTYPE_READ_FETCH) || \
+                                          ((__ACCTYPE__) == RIF_ACCTYPE_WRITE))
+
+#define IS_RIF_LOCK_STATE(__LOCK__)  (((__LOCK__) == RIF_LOCK_DISABLE) || \
+                                      ((__LOCK__) == RIF_LOCK_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup RIF_Private_Macros_RISAF RIF Private Macros - RISAF
+  * @{
+  */
+
+#if !defined(NPU_PRESENT)
+#define IS_RISAF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == RISAF1)   || \
+                                         ((__INSTANCE__) == RISAF2)   || \
+                                         ((__INSTANCE__) == RISAF3)   || \
+                                         ((__INSTANCE__) == RISAF6)   || \
+                                         ((__INSTANCE__) == RISAF7)   || \
+                                         ((__INSTANCE__) == RISAF8)   || \
+                                         ((__INSTANCE__) == RISAF9)   || \
+                                         ((__INSTANCE__) == RISAF11)  || \
+                                         ((__INSTANCE__) == RISAF12)  || \
+                                         ((__INSTANCE__) == RISAF13)  || \
+                                         ((__INSTANCE__) == RISAF14)  || \
+                                         ((__INSTANCE__) == RISAF21)  || \
+                                         ((__INSTANCE__) == RISAF22)  || \
+                                         ((__INSTANCE__) == RISAF23))
+#else
+#define IS_RISAF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == RISAF1)   || \
+                                         ((__INSTANCE__) == RISAF2)   || \
+                                         ((__INSTANCE__) == RISAF3)   || \
+                                         ((__INSTANCE__) == RISAF4)   || \
+                                         ((__INSTANCE__) == RISAF5)   || \
+                                         ((__INSTANCE__) == RISAF6)   || \
+                                         ((__INSTANCE__) == RISAF7)   || \
+                                         ((__INSTANCE__) == RISAF8)   || \
+                                         ((__INSTANCE__) == RISAF9)   || \
+                                         ((__INSTANCE__) == RISAF11)  || \
+                                         ((__INSTANCE__) == RISAF12)  || \
+                                         ((__INSTANCE__) == RISAF13)  || \
+                                         ((__INSTANCE__) == RISAF14)  || \
+                                         ((__INSTANCE__) == RISAF15)  || \
+                                         ((__INSTANCE__) == RISAF21)  || \
+                                         ((__INSTANCE__) == RISAF22)  || \
+                                         ((__INSTANCE__) == RISAF23))
+#endif /* !defined(NPU_PRESENT) */
+
+#define IS_RISAF_REGION(__REGION__)  (((__REGION__) == RISAF_REGION_1)  || \
+                                      ((__REGION__) == RISAF_REGION_2)  || \
+                                      ((__REGION__) == RISAF_REGION_3)  || \
+                                      ((__REGION__) == RISAF_REGION_4)  || \
+                                      ((__REGION__) == RISAF_REGION_5)  || \
+                                      ((__REGION__) == RISAF_REGION_6)  || \
+                                      ((__REGION__) == RISAF_REGION_7)  || \
+                                      ((__REGION__) == RISAF_REGION_8)  || \
+                                      ((__REGION__) == RISAF_REGION_9)  || \
+                                      ((__REGION__) == RISAF_REGION_10) || \
+                                      ((__REGION__) == RISAF_REGION_11) || \
+                                      ((__REGION__) == RISAF_REGION_12) || \
+                                      ((__REGION__) == RISAF_REGION_13) || \
+                                      ((__REGION__) == RISAF_REGION_14) || \
+                                      ((__REGION__) == RISAF_REGION_15))
+
+#if !defined(NPU_PRESENT)
+#define IS_RISAF_MAX_REGION(__INSTANCE__, __REGION__)    (((__INSTANCE__) == RISAF1)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF2)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF3)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF6)  ? ((__REGION__) <= RISAF_REGION_11) : \
+                                                          ((__INSTANCE__) == RISAF7)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF8)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF9)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF11) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF12) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF13) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF14) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF21) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF22) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__REGION__) <= RISAF_REGION_3))
+#else
+#define IS_RISAF_MAX_REGION(__INSTANCE__, __REGION__)    (((__INSTANCE__) == RISAF1)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF2)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF3)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF4)  ? ((__REGION__) <= RISAF_REGION_11) : \
+                                                          ((__INSTANCE__) == RISAF5)  ? ((__REGION__) <= RISAF_REGION_11) : \
+                                                          ((__INSTANCE__) == RISAF6)  ? ((__REGION__) <= RISAF_REGION_11) : \
+                                                          ((__INSTANCE__) == RISAF7)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF8)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF9)  ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF11) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF12) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF13) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF14) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF15) ? ((__REGION__) <= RISAF_REGION_2)  : \
+                                                          ((__INSTANCE__) == RISAF21) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__INSTANCE__) == RISAF22) ? ((__REGION__) <= RISAF_REGION_7)  : \
+                                                          ((__REGION__) <= RISAF_REGION_3))
+#endif /* !defined(NPU_PRESENT) */
+
+#if !defined(NPU_PRESENT)
+#define IS_RISAF_GRANULARITY(__INSTANCE__, __ADDRESS__)  ((((__INSTANCE__) == RISAF1)  ? ((__ADDRESS__) % RISAF1_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF2)  ? ((__ADDRESS__) % RISAF2_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF3)  ? ((__ADDRESS__) % RISAF3_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF6)  ? ((__ADDRESS__) % RISAF6_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF7)  ? ((__ADDRESS__) % RISAF7_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF8)  ? ((__ADDRESS__) % RISAF8_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF9)  ? ((__ADDRESS__) % RISAF9_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF11) ? ((__ADDRESS__) % RISAF11_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF12) ? ((__ADDRESS__) % RISAF12_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF13) ? ((__ADDRESS__) % RISAF13_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF14) ? ((__ADDRESS__) % RISAF14_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF21) ? ((__ADDRESS__) % RISAF21_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF22) ? ((__ADDRESS__) % RISAF22_GRANULARITY) : \
+                                                           ((__ADDRESS__) % RISAF23_GRANULARITY)) == 0x00U)
+#else
+#define IS_RISAF_GRANULARITY(__INSTANCE__, __ADDRESS__)  ((((__INSTANCE__) == RISAF1)  ? ((__ADDRESS__) % RISAF1_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF2)  ? ((__ADDRESS__) % RISAF2_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF3)  ? ((__ADDRESS__) % RISAF3_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF4)  ? ((__ADDRESS__) % RISAF4_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF5)  ? ((__ADDRESS__) % RISAF5_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF6)  ? ((__ADDRESS__) % RISAF6_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF7)  ? ((__ADDRESS__) % RISAF7_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF8)  ? ((__ADDRESS__) % RISAF8_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF9)  ? ((__ADDRESS__) % RISAF9_GRANULARITY)  : \
+                                                           ((__INSTANCE__) == RISAF11) ? ((__ADDRESS__) % RISAF11_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF12) ? ((__ADDRESS__) % RISAF12_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF13) ? ((__ADDRESS__) % RISAF13_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF14) ? ((__ADDRESS__) % RISAF14_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF15) ? ((__ADDRESS__) % RISAF15_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF21) ? ((__ADDRESS__) % RISAF21_GRANULARITY) : \
+                                                           ((__INSTANCE__) == RISAF22) ? ((__ADDRESS__) % RISAF22_GRANULARITY) : \
+                                                           ((__ADDRESS__) % RISAF23_GRANULARITY)) == 0x00U)
+#endif /* !defined(NPU_PRESENT) */
+
+#if !defined(NPU_PRESENT)
+#define IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(__INSTANCE__, __ADDRESS__)   ((((__INSTANCE__) == RISAF1)  && ((__ADDRESS__) < (RISAF1_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF2)  && ((__ADDRESS__) < (RISAF2_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF3)  && ((__ADDRESS__) < (RISAF3_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        ((__INSTANCE__) == RISAF6)  || \
+                                                                        (((__INSTANCE__) == RISAF7)  && ((__ADDRESS__) < (RISAF7_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF8)  && ((__ADDRESS__) < (RISAF8_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF9)  && ((__ADDRESS__) < (RISAF9_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF11) && ((__ADDRESS__) < (RISAF11_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF12) && ((__ADDRESS__) < (RISAF12_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF13) && ((__ADDRESS__) < (RISAF13_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF14) && ((__ADDRESS__) < (RISAF14_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF21) && ((__ADDRESS__) < (RISAF21_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF22) && ((__ADDRESS__) < (RISAF22_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF23) && ((__ADDRESS__) < (RISAF23_LIMIT_ADDRESS_SPACE_SIZE + 1U))))
+#else
+#define IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(__INSTANCE__, __ADDRESS__)   ((((__INSTANCE__) == RISAF1)  && ((__ADDRESS__) < (RISAF1_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF2)  && ((__ADDRESS__) < (RISAF2_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF3)  && ((__ADDRESS__) < (RISAF3_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        ((__INSTANCE__) == RISAF4)  || \
+                                                                        ((__INSTANCE__) == RISAF5)  || \
+                                                                        ((__INSTANCE__) == RISAF6)  || \
+                                                                        (((__INSTANCE__) == RISAF7)  && ((__ADDRESS__) < (RISAF7_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF8)  && ((__ADDRESS__) < (RISAF8_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF9)  && ((__ADDRESS__) < (RISAF9_LIMIT_ADDRESS_SPACE_SIZE + 1U)))  || \
+                                                                        (((__INSTANCE__) == RISAF11) && ((__ADDRESS__) < (RISAF11_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF12) && ((__ADDRESS__) < (RISAF12_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF13) && ((__ADDRESS__) < (RISAF13_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF14) && ((__ADDRESS__) < (RISAF14_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF15) && ((__ADDRESS__) < (RISAF15_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF21) && ((__ADDRESS__) < (RISAF21_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF22) && ((__ADDRESS__) < (RISAF22_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \
+                                                                        (((__INSTANCE__) == RISAF23) && ((__ADDRESS__) < (RISAF23_LIMIT_ADDRESS_SPACE_SIZE + 1U))))
+#endif /* !defined(NPU_PRESENT) */
+
+#define IS_RISAF_SUBREGION(__SUBREGION__)  (((__SUBREGION__) == RISAF_SUBREGION_A) || \
+                                            ((__SUBREGION__) == RISAF_SUBREGION_B))
+
+#define IS_RISAF_FILTERING(__FILTERING__)  (((__FILTERING__) == RISAF_FILTER_DISABLE) || \
+                                            ((__FILTERING__) == RISAF_FILTER_ENABLE))
+
+#define IS_RISAF_DELEGATION(__DELEGATION__)  (((__DELEGATION__) == RISAF_DELEGATION_DISABLE) || \
+                                              ((__DELEGATION__) == RISAF_DELEGATION_ENABLE))
+
+
+#define IS_RISAF_READ_WRITE(__RW__)  (((uint32_t)(__RW__) == RISAF_READ_DISABLE) || \
+                                      (((uint32_t)(__RW__) & ~RISAF_READ_WRITE_MASK) == 0x00U))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RIF_Exported_Functions RIF Exported Functions
+  * @{
+  */
+/** @defgroup RIF_Exported_Functions_Group1 RIMC Configuration functions
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void     HAL_RIF_RIMC_Lock(void);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+uint32_t HAL_RIF_RIMC_GetLock(void);
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void     HAL_RIF_RIMC_SetDebugAccessPortCID(uint32_t CID);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+uint32_t HAL_RIF_RIMC_GetDebugAccessPortCID(void);
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void     HAL_RIF_RIMC_ConfigMasterAttributes(uint32_t MasterId, const RIMC_MasterConfig_t *pConfig);
+void     HAL_RIF_RIMC_GetConfigMasterAttributes(uint32_t MasterId, RIMC_MasterConfig_t *pConfig);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+/**
+  * @}
+  */
+
+/** @defgroup RIF_Exported_Functions_Group2 RIFSC Configuration functions
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void       HAL_RIF_RISC_Lock(void);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+uint32_t   HAL_RIF_RISC_GetLock(void);
+void       HAL_RIF_RISC_SetSlaveSecureAttributes(uint32_t PeriphId, uint32_t SecPriv);
+uint32_t   HAL_RIF_RISC_GetSlaveSecureAttributes(uint32_t PeriphId);
+void       HAL_RIF_RISC_SlaveConfigLock(uint32_t PeriphId);
+uint32_t   HAL_RIF_RISC_GetSlaveConfigLock(uint32_t PeriphId);
+/**
+  * @}
+  */
+
+/** @defgroup RIF_Exported_Functions_Group4 RISAF Configuration functions
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void      HAL_RIF_RISAF_Lock(RISAF_TypeDef *RISAFx);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+uint32_t  HAL_RIF_RISAF_GetLock(const RISAF_TypeDef *RISAFx);
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void      HAL_RIF_RISAF_ConfigBaseRegion(RISAF_TypeDef *RISAFx, uint32_t Region,
+                                         const RISAF_BaseRegionConfig_t *pConfig);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+void      HAL_RIF_RISAF_GetConfigBaseRegion(const RISAF_TypeDef *RISAFx, uint32_t Region,
+                                            RISAF_BaseRegionConfig_t *pConfig);
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void HAL_RIF_RISAF_ConfigSubRegionDelegation(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                             const RISAF_DelegationConfig_t *pConfig);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+void      HAL_RIF_RISAF_GetConfigSubRegionDelegation(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                                     RISAF_DelegationConfig_t *pConfig);
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void      HAL_RIF_RISAF_ConfigSubRegion(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                        const RISAF_SubRegionConfig_t *pConfig);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+void      HAL_RIF_RISAF_GetConfigSubRegion(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                           RISAF_SubRegionConfig_t *pConfig);
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+void      HAL_RIF_RISAF_GetIllegalAccess(RISAF_TypeDef *RISAFx, RISAF_IllegalAccess_t *IllegalAccess);
+#endif /* CPU_AS_TRUSTED_DOMAIN */
+/**
+  * @}
+  */
+
+/** @defgroup RIF_Exported_Functions_Group6 IAC Configuration functions
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
+void      HAL_RIF_IAC_EnableIT(uint32_t PeriphId);
+void      HAL_RIF_IAC_DisableIT(uint32_t PeriphId);
+uint32_t  HAL_RIF_IAC_GetFlag(uint32_t PeriphId);
+void      HAL_RIF_IAC_ClearFlag(uint32_t PeriphId);
+void      HAL_RIF_IRQHandler(void);
+void      HAL_RIF_ILA_Callback(uint32_t PeriphId);
+#endif /* CPU_AS_TRUSTED_DOMAIN && CPU_IN_SECURE_STATE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_RIF_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rng.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rng.h
new file mode 100644
index 000000000..fa72d714a
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rng.h
@@ -0,0 +1,389 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rng.h
+  * @author  MCD Application Team
+  * @brief   Header file of RNG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RNG_H
+#define STM32N6xx_HAL_RNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @defgroup RNG RNG
+  * @brief RNG HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RNG_Exported_Types RNG Exported Types
+  * @{
+  */
+
+/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */
+} RNG_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
+  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
+  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
+  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
+  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
+
+} HAL_RNG_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
+  * @{
+  */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+typedef struct  __RNG_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+{
+  RNG_TypeDef                 *Instance;    /*!< Register base address   */
+
+  RNG_InitTypeDef             Init;         /*!< RNG configuration parameters */
+
+  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
+
+  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
+
+  __IO  uint32_t              ErrorCode;    /*!< RNG Error code          */
+
+  uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
+  void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
+
+  void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
+  void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
+#endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+} RNG_HandleTypeDef;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL RNG Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
+
+  HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
+  HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
+
+} HAL_RNG_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL RNG Callback pointer definition
+  */
+typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
+typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
+  * @{
+  */
+
+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
+  * @{
+  */
+#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
+#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
+#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
+  * @{
+  */
+#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
+#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
+#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
+  * @{
+  */
+#define RNG_CED_ENABLE          0x00000000U /*!< Clock error detection Enabled  */
+#define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Error_Definition   RNG Error Definition
+  * @{
+  */
+#define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error          */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+#define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error     */
+#define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
+#define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
+#define  HAL_RNG_ERROR_CLOCK            0x00000010U    /*!< Clock error       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+  * @{
+  */
+
+/** @brief Reset RNG handle state
+  * @param  __HANDLE__ RNG Handle
+  * @retval None
+  */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
+                                                       (__HANDLE__)->MspInitCallback = NULL;            \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                    } while(0U)
+#else
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enables the RNG peripheral.
+  * @param  __HANDLE__ RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
+
+/**
+  * @brief  Disables the RNG peripheral.
+  * @param  __HANDLE__ RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+  * @brief  Check the selected RNG flag status.
+  * @param  __HANDLE__ RNG Handle
+  * @param  __FLAG__ RNG flag
+  *          This parameter can be one of the following values:
+  *            @arg RNG_FLAG_DRDY:  Data ready
+  *            @arg RNG_FLAG_CECS:  Clock error current status
+  *            @arg RNG_FLAG_SECS:  Seed error current status
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clears the selected RNG flag status.
+  * @param  __HANDLE__ RNG handle
+  * @param  __FLAG__ RNG flag to clear
+  * @note   WARNING: This is a dummy macro for HAL code alignment,
+  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
+
+/**
+  * @brief  Enables the RNG interrupts.
+  * @param  __HANDLE__ RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
+
+/**
+  * @brief  Disables the RNG interrupts.
+  * @param  __HANDLE__ RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+  * @brief  Checks whether the specified RNG interrupt has occurred or not.
+  * @param  __HANDLE__ RNG Handle
+  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RNG_IT_DRDY: Data ready interrupt
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clear the RNG interrupt status flags.
+  * @param  __HANDLE__ RNG Handle
+  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Include RNG HAL Extended module */
+#include "stm32n6xx_hal_rng_ex.h"
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+  * @{
+  */
+
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+                                           pRNG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
+
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
+uint32_t             HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_Private_Macros RNG Private Macros
+  * @{
+  */
+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
+                       ((IT) == RNG_IT_SEI))
+
+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
+                           ((FLAG) == RNG_FLAG_CECS) || \
+                           ((FLAG) == RNG_FLAG_SECS))
+
+/**
+  * @brief Verify the RNG Clock Error Detection mode.
+  * @param __MODE__ RNG Clock Error Detection mode
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_RNG_CED(__MODE__)   (((__MODE__) == RNG_CED_ENABLE) || \
+                                ((__MODE__) == RNG_CED_DISABLE))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private functions
+  * @{
+  */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_RNG_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rng_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rng_ex.h
new file mode 100644
index 000000000..d64858a37
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rng_ex.h
@@ -0,0 +1,263 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rng_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RNG HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RNG_EX_H
+#define STM32N6xx_HAL_RNG_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined(RNG)
+#if defined(RNG_CR_CONDRST)
+
+/** @defgroup RNGEx RNGEx
+  * @brief RNG Extension HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
+  * @brief RNGEx Exported types
+  * @{
+  */
+
+/**
+  * @brief RNGEx Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t        Config1;           /*!< Config1 must be a value between 0 and 0x3F */
+  uint32_t        Config2;           /*!< Config2 must be a value between 0 and 0x7 */
+  uint32_t        Config3;           /*!< Config3 must be a value between 0 and 0xF */
+  uint32_t        ClockDivider;      /*!< Clock Divider factor.This parameter can
+                                          be a value of @ref RNGEx_Clock_Divider_Factor   */
+  uint32_t        NistCompliance;    /*!< NIST compliance.This parameter can be a
+                                          value of @ref RNGEx_NIST_Compliance   */
+  uint32_t        AutoReset;         /*!< automatic reset When a noise source error occurs
+                                          value of @ref RNGEx_Auto_Reset   */
+  uint32_t        HealthTest;           /*!< RNG health test control must be a value
+                                             between 0x0FFCABFF and 0x00005200 */
+} RNG_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RNGEx_Clock_Divider_Factor  Value used to configure an internal
+  *            programmable divider acting on the incoming RNG clock
+  * @{
+  */
+#define RNG_CLKDIV_BY_1       (0x00000000UL)      /*!< No clock division  */
+#define RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)
+/*!< 2 RNG clock cycles per internal RNG clock    */
+#define RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)
+/*!< 4 RNG clock cycles per internal RNG clock    */
+#define RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 8 RNG clock cycles per internal RNG clock    */
+#define RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)
+/*!< 16 RNG clock cycles per internal RNG clock   */
+#define RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
+/*!< 32 RNG clock cycles per internal RNG clock   */
+#define RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
+/*!< 64 RNG clock cycles per internal RNG clock   */
+#define RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 128 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)
+/*!< 256 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
+/*!< 512 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
+/*!< 1024 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 2048 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
+/*!< 4096 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
+/*!< 8192 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
+/*!< 16384 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 32768 RNG clock cycles per internal RNG clock */
+/**
+  * @}
+  */
+
+/** @defgroup RNGEx_NIST_Compliance  NIST Compliance configuration
+  * @{
+  */
+#define RNG_NIST_COMPLIANT     (0x00000000UL) /*!< NIST compliant configuration*/
+#define RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
+
+/**
+  * @}
+  */
+/** @defgroup RNGEx_Auto_Reset  Auto Reset configuration
+  * @{
+  */
+#define RNG_ARDIS_ENABLE     (0x00000000UL) /*!< automatic reset after seed error*/
+#define RNG_ARDIS_DISABLE    (RNG_CR_ARDIS) /*!< Disable automatic reset after seed error */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Types RNGEx Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
+  * @{
+  */
+
+#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16)    || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32)    || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64)    || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128)   || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256)   || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512)   || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))
+
+
+#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \
+                                                     ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))
+
+#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
+
+#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
+
+#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
+#define IS_RNG_ARDIS(__ARDIS__) (((__ARDIS__) == RNG_ARDIS_ENABLE) || \
+                                 ((__ARDIS__) == RNG_ARDIS_DISABLE))
+
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RNGEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNGEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RNGEx_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* RNG_CR_CONDRST */
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_RNG_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rtc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rtc.h
new file mode 100644
index 000000000..a28679c89
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rtc.h
@@ -0,0 +1,969 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rtc.h
+  * @author  GPM Application Team
+  * @brief   Header file of RTC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RTC_H
+#define STM32N6xx_HAL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RTC RTC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
+  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
+  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
+  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
+  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
+
+} HAL_RTCStateTypeDef;
+
+/**
+  * @brief  RTC Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t HourFormat;        /*!< Specifies the RTC Hour Format.
+                                 This parameter can be a value of @ref RTC_Hour_Formats */
+
+  uint32_t AsynchPrediv;      /*!< Specifies the RTC Asynchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+  uint32_t SynchPrediv;       /*!< Specifies the RTC Synchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+  uint32_t OutPut;            /*!< Specifies which signal will be routed to the RTC output.
+                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+
+  uint32_t OutPutRemap;       /*!< Specifies the remap for RTC output.
+                                 This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
+
+  uint32_t OutPutPolarity;    /*!< Specifies the polarity of the output signal.
+                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+  uint32_t OutPutType;        /*!< Specifies the RTC Output Pin mode.
+                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+
+  uint32_t OutPutPullUp;      /*!< Specifies the RTC Output Pull-Up mode.
+                                 This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
+
+  uint32_t BinMode;           /*!< Specifies the RTC binary mode.
+                                 This parameter can be a value of @ref RTCEx_Binary_Mode */
+
+  uint32_t BinMixBcdU;        /*!< Specifies the BCD calendar update if and only if BinMode = RTC_BINARY_MIX.
+                                 This parameter can be a value of @ref RTCEx_Binary_mix_BCDU */
+} RTC_InitTypeDef;
+
+/**
+  * @brief  RTC Time structure definition
+  */
+typedef struct
+{
+  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
+                                 This parameter must be a number between:
+                                 Min_Data = 0 and Max_Data = 12 if the RTC_HOURFORMAT_12 is selected.
+                                 This parameter must be a number between:
+                                 Min_Data = 0 and Max_Data = 23 if the RTC_HOURFORMAT_24 is selected */
+
+  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
+                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+  uint32_t SubSeconds;      /*!< Specifies the RTC_SSR RTC Sub Second register content.
+                                 This field is not used by HAL_RTC_SetTime.
+                                 If the free running 32 bit counter is not activated (mode binary none)
+                                    - This parameter corresponds to a time unit range
+                                 between [0-1] Second with [1 Sec / SecondFraction +1] granularity
+                                 else
+                                    - This parameter corresponds to the free running 32 bit counter. */
+
+  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
+                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+                                 This parameter corresponds to a time unit range between [0-1] Second
+                                 with [1 Sec / SecondFraction +1] granularity.
+                                 This field will be used only by HAL_RTC_GetTime function */
+
+  uint32_t DayLightSaving;  /*!< This interface is deprecated.
+                                 To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
+
+  uint32_t StoreOperation;  /*!< This interface is deprecated.
+                                 To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
+} RTC_TimeTypeDef;
+
+/**
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
+                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t Date;     /*!< Specifies the RTC Date.
+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+  uint8_t Year;     /*!< Specifies the RTC Date Year.
+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+} RTC_DateTypeDef;
+
+/**
+  * @brief  RTC Alarm structure definition
+  */
+typedef struct
+{
+  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
+
+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
+                                      if Binary mode is RTC_BINARY_ONLY or is RTC_BINARY_MIX
+                                        This parameter can be a value of
+                                        @ref RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions
+                                      else if Binary mode is RTC_BINARY_NONE
+                                        This parameter can be a value of
+                                        @ref RTC_Alarm_Sub_Seconds_BCD_Masks_Definitions */
+
+  uint32_t BinaryAutoClr;        /*!< Clear synchronously counter (RTC_SSR) on binary alarm.
+                                      RTC_ALARMSUBSECONDBIN_AUTOCLR_YES must only be used if Binary mode
+                                       is RTC_BINARY_ONLY
+                                      This parameter can be a value of
+                                      @ref RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions */
+
+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                      If the Alarm Date is selected, this parameter must be set to a value
+                                       in the 1-31 range.
+                                      If the Alarm WeekDay is selected, this parameter can be a value of
+                                      @ref RTC_WeekDay_Definitions */
+
+  uint32_t FlagAutoClr;          /*!< Specifies the alarm trigger generation. This feature is meaningful
+                                      to avoid any RTC software execution after configuration.
+                                      This parameter can be a value of @ref RTC_ALARM_Flag_AutoClear_Definitions */
+
+  uint32_t Alarm;                /*!< Specifies the alarm.
+                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
+} RTC_AlarmTypeDef;
+
+/**
+  * @brief  RTC Handle Structure definition
+  */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+typedef struct __RTC_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+{
+  RTC_TypeDef               *Instance;  /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */
+
+  RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
+
+  HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
+
+  __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm A Event callback            */
+  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm B Event callback            */
+  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC TimeStamp Event callback          */
+  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);       /*!< RTC WakeUpTimer Event callback        */
+  void (* SSRUEventCallback)(struct __RTC_HandleTypeDef *hrtc);              /*!< RTC SSRU Event callback               */
+  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 1 Event callback           */
+  void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 2 Event callback           */
+  void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 3 Event callback           */
+  void (* Tamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 4 Event callback           */
+  void (* Tamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 5 Event callback           */
+  void (* Tamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 6 Event callback           */
+  void (* Tamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 7 Event callback           */
+  void (* Tamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Tamper 8 Event callback           */
+  void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 1 Event callback  */
+  void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 2 Event callback  */
+  void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 3 Event callback  */
+  void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 4 Event callback  */
+  void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 5 Event callback  */
+  void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 6 Event callback  */
+  void (* InternalTamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 7 Event callback  */
+  void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 8 Event callback  */
+  void (* InternalTamper9EventCallback)(struct __RTC_HandleTypeDef *hrtc);   /*!< RTC Internal Tamper 9 Event callback  */
+  void (* InternalTamper11EventCallback)(struct __RTC_HandleTypeDef *hrtc);  /*!< RTC Internal Tamper 11 Event callback */
+  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);                /*!< RTC Msp Init callback                 */
+  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);              /*!< RTC Msp DeInit callback               */
+
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+} RTC_HandleTypeDef;
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL RTC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0U,   /*!< RTC Alarm A Event Callback ID      */
+  HAL_RTC_ALARM_B_EVENT_CB_ID           = 1U,   /*!< RTC Alarm B Event Callback ID      */
+  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 2U,   /*!< RTC TimeStamp Event Callback ID    */
+  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 3U,   /*!< RTC WakeUp Timer Event Callback ID */
+  HAL_RTC_SSRU_EVENT_CB_ID              = 4U,   /*!< RTC SSRU Event Callback ID         */
+  HAL_RTC_TAMPER1_EVENT_CB_ID           = 5U,   /*!< RTC Tamper 1 Callback ID           */
+  HAL_RTC_TAMPER2_EVENT_CB_ID           = 6U,   /*!< RTC Tamper 2 Callback ID           */
+  HAL_RTC_TAMPER3_EVENT_CB_ID           = 7U,   /*!< RTC Tamper 3 Callback ID           */
+  HAL_RTC_TAMPER4_EVENT_CB_ID           = 8U,   /*!< RTC Tamper 4 Callback ID           */
+  HAL_RTC_TAMPER5_EVENT_CB_ID           = 9U,   /*!< RTC Tamper 5 Callback ID           */
+  HAL_RTC_TAMPER6_EVENT_CB_ID           = 10U,  /*!< RTC Tamper 6 Callback ID           */
+  HAL_RTC_TAMPER7_EVENT_CB_ID           = 11U,  /*!< RTC Tamper 7 Callback ID           */
+  HAL_RTC_TAMPER8_EVENT_CB_ID           = 12U,  /*!< RTC Tamper 8 Callback ID           */
+  HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID  = 13U,  /*!< RTC Internal Tamper 1 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID  = 14U,  /*!< RTC Internal Tamper 2 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  = 15U,  /*!< RTC Internal Tamper 3 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID  = 16U,  /*!< RTC Internal Tamper 4 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  = 17U,  /*!< RTC Internal Tamper 5 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 18U,  /*!< RTC Internal Tamper 6 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID  = 19U,  /*!< RTC Internal Tamper 7 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID  = 20U,  /*!< RTC Internal Tamper 8 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID  = 21U,  /*!< RTC Internal Tamper 9 Callback ID  */
+  HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID = 22U,  /*!< RTC Internal Tamper 11 Callback ID */
+  HAL_RTC_MSPINIT_CB_ID                 = 23U,  /*!< RTC Msp Init callback ID           */
+  HAL_RTC_MSPDEINIT_CB_ID               = 24U   /*!< RTC Msp DeInit callback ID         */
+} HAL_RTC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL RTC Callback pointer definition
+  */
+typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+  * @{
+  */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+  * @{
+  */
+#define RTC_HOURFORMAT_24                   0U
+#define RTC_HOURFORMAT_12                   RTC_CR_FMT
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
+  * @{
+  */
+#define RTC_OUTPUT_DISABLE                  0U
+#define RTC_OUTPUT_ALARMA                   RTC_CR_OSEL_0
+#define RTC_OUTPUT_ALARMB                   RTC_CR_OSEL_1
+#define RTC_OUTPUT_WAKEUP                   RTC_CR_OSEL
+#define RTC_OUTPUT_TAMPER                   RTC_CR_TAMPOE
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+  * @{
+  */
+#define RTC_OUTPUT_POLARITY_HIGH            0U
+#define RTC_OUTPUT_POLARITY_LOW             RTC_CR_POL
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+  * @{
+  */
+#define RTC_OUTPUT_TYPE_PUSHPULL            0U
+#define RTC_OUTPUT_TYPE_OPENDRAIN           RTC_CR_TAMPALRM_TYPE
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
+  * @{
+  */
+#define RTC_OUTPUT_PULLUP_NONE              0U
+#define RTC_OUTPUT_PULLUP_ON                RTC_CR_TAMPALRM_PU
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
+  * @{
+  */
+#define RTC_OUTPUT_REMAP_NONE               0U
+#define RTC_OUTPUT_REMAP_POS1               RTC_CR_OUT2EN
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+  * @{
+  */
+#define RTC_HOURFORMAT12_AM                 0U
+#define RTC_HOURFORMAT12_PM                 1U
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
+  * @{
+  */
+#define RTC_DAYLIGHTSAVING_SUB1H            RTC_CR_SUB1H
+#define RTC_DAYLIGHTSAVING_ADD1H            RTC_CR_ADD1H
+#define RTC_DAYLIGHTSAVING_NONE             0U
+/**
+  * @}
+  */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
+  * @{
+  */
+#define RTC_STOREOPERATION_RESET            0U
+#define RTC_STOREOPERATION_SET              RTC_CR_BKP
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
+  * @{
+  */
+#define RTC_FORMAT_BIN                      0U
+#define RTC_FORMAT_BCD                      1U
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+  * @{
+  */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY                   ((uint8_t)0x01U)
+#define RTC_MONTH_FEBRUARY                  ((uint8_t)0x02U)
+#define RTC_MONTH_MARCH                     ((uint8_t)0x03U)
+#define RTC_MONTH_APRIL                     ((uint8_t)0x04U)
+#define RTC_MONTH_MAY                       ((uint8_t)0x05U)
+#define RTC_MONTH_JUNE                      ((uint8_t)0x06U)
+#define RTC_MONTH_JULY                      ((uint8_t)0x07U)
+#define RTC_MONTH_AUGUST                    ((uint8_t)0x08U)
+#define RTC_MONTH_SEPTEMBER                 ((uint8_t)0x09U)
+#define RTC_MONTH_OCTOBER                   ((uint8_t)0x10U)
+#define RTC_MONTH_NOVEMBER                  ((uint8_t)0x11U)
+#define RTC_MONTH_DECEMBER                  ((uint8_t)0x12U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+  * @{
+  */
+#define RTC_WEEKDAY_MONDAY                  ((uint8_t)0x01U)
+#define RTC_WEEKDAY_TUESDAY                 ((uint8_t)0x02U)
+#define RTC_WEEKDAY_WEDNESDAY               ((uint8_t)0x03U)
+#define RTC_WEEKDAY_THURSDAY                ((uint8_t)0x04U)
+#define RTC_WEEKDAY_FRIDAY                  ((uint8_t)0x05U)
+#define RTC_WEEKDAY_SATURDAY                ((uint8_t)0x06U)
+#define RTC_WEEKDAY_SUNDAY                  ((uint8_t)0x07U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
+  * @{
+  */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE        0U
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY     RTC_ALRMAR_WDSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
+  * @{
+  */
+#define RTC_ALARMMASK_NONE                  0U
+#define RTC_ALARMMASK_DATEWEEKDAY           RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS                 RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES               RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS               RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL                   (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS  | \
+                                             RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+  * @{
+  */
+#define RTC_ALARM_A                         RTC_CR_ALRAE
+#define RTC_ALARM_B                         RTC_CR_ALRBE
+
+/**
+  * @}
+  */
+/** @defgroup RTC_ALARM_Flag_AutoClear_Definitions RTC Alarms Flag Auto Clear Definitions
+  * @{
+  */
+#define ALARM_FLAG_AUTOCLR_ENABLE           1U
+#define ALARM_FLAG_AUTOCLR_DISABLE          0U
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_BCD_Masks_Definitions RTC Alarm Sub Seconds BCD Masks Definitions
+  *           In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared.
+  * @{
+  */
+#define RTC_ALARMSUBSECONDMASK_ALL          0U                                                                       /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1       RTC_ALRMASSR_MASKSS_0                                                    /*!< SS[14:1] not used in Alarmcomparison. Only SS[0] is compared                    */
+#define RTC_ALARMSUBSECONDMASK_SS14_2       RTC_ALRMASSR_MASKSS_1                                                    /*!< SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_3       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)                          /*!< SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_4       RTC_ALRMASSR_MASKSS_2                                                    /*!< SS[14:4] not used in Alarm comparison. Only SS[3:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_5       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:5] not used in Alarm comparison. Only SS[4:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_6       (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:6] not used in Alarm comparison. Only SS[5:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_7       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)  /*!< SS[14:7] not used in Alarm comparison. Only SS[6:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_8       RTC_ALRMASSR_MASKSS_3                                                    /*!< SS[14:8] not used in Alarm comparison. Only SS[7:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_9       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:9] not used in Alarm comparison. Only SS[8:0] are compared                */
+#define RTC_ALARMSUBSECONDMASK_SS14_10      (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:10] not used in Alarm comparison. Only SS[9:0] are compared               */
+#define RTC_ALARMSUBSECONDMASK_SS14_11      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:11] not used in Alarm comparison. Only SS[10:0] are compared              */
+#define RTC_ALARMSUBSECONDMASK_SS14_12      (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:12] not used in Alarm comparison.Only SS[11:0] are compared               */
+#define RTC_ALARMSUBSECONDMASK_SS14_13      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:13] not used in Alarm comparison. Only SS[12:0] are compared              */
+#define RTC_ALARMSUBSECONDMASK_SS14         (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14] not used in Alarm comparison. Only SS[13:0] are compared                 */
+#define RTC_ALARMSUBSECONDMASK_NONE         RTC_ALRMASSR_MASKSS                                                      /*!< SS[14:0] are compared and must match to activate alarm                          */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+  * @{
+  */
+#define RTC_IT_TS                           RTC_CR_TSIE        /*!< Enable Timestamp Interrupt     */
+#define RTC_IT_WUT                          RTC_CR_WUTIE       /*!< Enable Wakeup timer Interrupt  */
+#define RTC_IT_SSRU                         RTC_CR_SSRUIE      /*!< Enable SSR Underflow Interrupt */
+#define RTC_IT_ALRA                         RTC_CR_ALRAIE      /*!< Enable Alarm A Interrupt       */
+#define RTC_IT_ALRB                         RTC_CR_ALRBIE      /*!< Enable Alarm B Interrupt       */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+  * @{
+  */
+#define RTC_FLAG_RECALPF                    (1U)               /*!< Recalibration pending flag     */
+#define RTC_FLAG_INITF                      (2U)               /*!< Initialization flag            */
+#define RTC_FLAG_RSF                        (3U)               /*!< Registers synchronization flag */
+#define RTC_FLAG_INITS                      (4U)               /*!< Initialization status flag     */
+#define RTC_FLAG_SHPF                       (5U)               /*!< Shift operation pending flag   */
+#define RTC_FLAG_WUTWF                      (6U)               /*!< Wakeup timer write flag        */
+#define RTC_FLAG_SSRUF                      (7U)               /*!< SSR underflow flag             */
+#define RTC_FLAG_ITSF                       (8U)               /*!< Internal Time-stamp flag       */
+#define RTC_FLAG_TSOVF                      (9U)               /*!< Time-stamp overflow flag       */
+#define RTC_FLAG_TSF                        (10U)              /*!< Time-stamp flag                */
+#define RTC_FLAG_WUTF                       (11U)              /*!< Wakeup timer flag              */
+#define RTC_FLAG_ALRBF                      (12U)              /*!< Alarm B flag                   */
+#define RTC_FLAG_ALRAF                      (13U)              /*!< Alarm A flag                   */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
+  * @{
+  */
+#define RTC_CLEAR_SSRUF                     RTC_SCR_CSSRUF   /*!< Clear SSR underflow flag       */
+#define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */
+#define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */
+#define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag          */
+#define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag        */
+#define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag             */
+#define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+  * @{
+  */
+
+/** @brief Reset RTC handle state
+  * @param  __HANDLE__ RTC handle.
+  * @retval None
+  */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;\
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                     }while(0)
+#else
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Disable the write protection for RTC registers.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
+  do{                                       \
+    RTC->WPR = 0xCAU;   \
+    RTC->WPR = 0x53U;   \
+  } while(0U)
+
+/**
+  * @brief  Enable the write protection for RTC registers.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
+  do{                                       \
+    RTC->WPR = 0xFFU;   \
+  } while(0U)
+
+/**
+  * @brief  Add 1 hour (summer time change).
+  * @note   This interface is deprecated.
+  *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __BKP__ Backup
+  *         This parameter can be:
+  *            @arg @ref RTC_STOREOPERATION_RESET
+  *            @arg @ref RTC_STOREOPERATION_SET
+  * @retval None
+  */
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)                         \
+  do {                                                              \
+    __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
+    SET_BIT(RTC->CR, RTC_CR_ADD1H);            \
+    MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
+    __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
+  } while(0);
+
+/**
+  * @brief  Subtract 1 hour (winter time change).
+  * @note   This interface is deprecated.
+  *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __BKP__ Backup
+  *         This parameter can be:
+  *            @arg @ref RTC_STOREOPERATION_RESET
+  *            @arg @ref RTC_STOREOPERATION_SET
+  * @retval None
+  */
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)                         \
+  do {                                                              \
+    __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
+    SET_BIT(RTC->CR, RTC_CR_SUB1H);            \
+    MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
+    __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
+  } while(0);
+
+/**
+  * @brief  Enable the RTC ALARMA peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)  (RTC->CR |= (RTC_CR_ALRAE))
+
+/**
+  * @brief  Disable the RTC ALARMA peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)  (RTC->CR &= ~(RTC_CR_ALRAE))
+
+/**
+  * @brief  Enable the RTC ALARMB peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)   (RTC->CR |= (RTC_CR_ALRBE))
+
+/**
+  * @brief  Disable the RTC ALARMB peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)  (RTC->CR &= ~(RTC_CR_ALRBE))
+
+/**
+  * @brief  Enable the RTC Alarm interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *             @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *             @arg @ref RTC_IT_ALRB Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)( \
+                                ((__INTERRUPT__) == RTC_IT_ALRA) ? (SET_BIT(RTC->CR, RTC_CR_ALRAIE)):\
+                                ((__INTERRUPT__) == RTC_IT_ALRB) ? (SET_BIT(RTC->CR, RTC_CR_ALRBIE)):\
+                                (0U)) /* Dummy action because is an invalid parameter value */
+
+/**
+  * @brief  Disable the RTC Alarm interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)( \
+                                ((__INTERRUPT__) == RTC_IT_ALRA) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE)):\
+                                ((__INTERRUPT__) == RTC_IT_ALRB) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE)):\
+                                (0U)) /* Dummy action because is an invalid parameter value */
+
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)( \
+                          ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == RTC_MISR_ALRAMF):\
+                          ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == RTC_MISR_ALRBMF):\
+                          (0U)) /* Return 0 because it is an invalid parameter value */
+
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)( \
+                                ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->CR, RTC_CR_ALRAIE) == RTC_CR_ALRAIE):\
+                                ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->CR, RTC_CR_ALRBIE) == RTC_CR_ALRBIE):\
+                                (0U)) /* Return 0 because it is an invalid parameter value */
+
+/**
+  * @brief  Get the selected RTC Alarms flag status.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_FLAG_ALRAF
+  *            @arg @ref RTC_FLAG_ALRBF
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \
+                                ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == RTC_SR_ALRAF):\
+                                ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == RTC_SR_ALRBF):\
+                                (0U)) /* Return 0 because it is an invalid parameter value */
+
+/**
+  * @brief  Clear the RTC Alarms pending flags.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
+  *          This parameter can be:
+  *             @arg @ref RTC_FLAG_ALRAF
+  *             @arg @ref RTC_FLAG_ALRBF
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \
+                                ((__FLAG__) == RTC_FLAG_ALRAF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CALRAF)):\
+                                ((__FLAG__) == RTC_FLAG_ALRBF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CALRBF)):\
+                                (0U)) /* Dummy action because is an invalid parameter value */
+
+/**
+  * @brief  Check whether if the RTC Calendar is initialized.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval The state of RTC Calendar initialization (TRUE or FALSE).
+  */
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__)  ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS))
+
+/**
+  * @}
+  */
+
+/* Include RTC HAL Extended module */
+#include "stm32n6xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+  * @{
+  */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
+                                           pRTC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+  * @{
+  */
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+void              HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc);
+void              HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc);
+void              HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc);
+void              HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc);
+uint32_t          HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+  * @{
+  */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm,
+                                   uint32_t Format);
+void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+
+/**
+  * @}
+  */
+
+/** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+  * @{
+  */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK                (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
+                                             RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
+                                             RTC_TR_SU)
+#define RTC_DR_RESERVED_MASK                (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
+                                             RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
+                                             RTC_DR_DU)
+#define RTC_INIT_MASK                       0xFFFFFFFFU
+#define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
+
+#define RTC_TIMEOUT_VALUE                   1000U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+  * @{
+  */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+  * @{
+  */
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
+                               ((OUTPUT) == RTC_OUTPUT_WAKEUP)  || \
+                               ((OUTPUT) == RTC_OUTPUT_TAMPER))
+
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
+                                        ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
+                                    ((TYPE) == RTC_OUTPUT_PULLUP_ON))
+
+#define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
+                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))
+
+#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
+                                  ((PM) == RTC_HOURFORMAT12_PM))
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+                                           ((OPERATION) == RTC_STOREOPERATION_SET))
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
+                               ((FORMAT) == RTC_FORMAT_BCD))
+
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99U)
+
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1U) && ((MONTH) <= 12U))
+
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1U) && ((DATE) <= 31U))
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
+
+#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || \
+                                  ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)          (((MASK) == 0UL) || \
+                                                     (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && \
+                                                      ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
+
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
+
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
+
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0U) && ((HOUR) <= 12U))
+
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23U)
+
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59U)
+
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+  * @{
+  */
+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef  RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
+uint8_t            RTC_ByteToBcd2(uint8_t Value);
+uint8_t            RTC_Bcd2ToByte(uint8_t Value);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_RTC_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rtc_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rtc_ex.h
new file mode 100644
index 000000000..1fe8f18c2
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_rtc_ex.h
@@ -0,0 +1,1849 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rtc_ex.h
+  * @author  GPM Application Team
+  * @brief   Header file of RTC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_RTC_EX_H
+#define STM32N6xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RTCEx RTCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+  * @{
+  */
+
+/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Pins */
+
+  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Trigger */
+
+  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
+                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
+
+  uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.
+                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
+
+  uint32_t Filter;                      /*!< Specifies the TAMP Filter Tamper.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Filter */
+
+  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
+                                             This parameter can be a value of
+                                             @ref RTCEx_Tamper_Sampling_Frequencies */
+
+  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration.
+                                             This parameter can be a value of
+                                             @ref RTCEx_Tamper_Pin_Precharge_Duration */
+
+  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp.
+                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */
+
+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
+                                             This parameter can be a value of
+                                              @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+} RTC_TamperTypeDef;
+/**
+  * @}
+  */
+
+
+/** @defgroup RTCEx_Active_Seed_Size Seed size Definitions
+  * @{
+  */
+#define RTC_ATAMP_SEED_NB_UINT32        4U
+/**
+  * @}
+  */
+
+
+/** @defgroup RTCEx_ActiveTamper_structures_definition RTCEx Active Tamper structures definitions
+  * @{
+  */
+typedef struct
+{
+  uint32_t Enable;                      /*!< Specifies the Tamper input is active.
+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Enable */
+
+  uint32_t Interrupt;                    /*!< Specifies the interrupt mode.
+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Interrupt */
+
+  uint32_t Output;                      /*!< Specifies the TAMP output to be compared with.
+                                             The same output can be used for several tamper inputs.
+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */
+
+  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
+                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
+
+  uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.
+                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
+
+} RTC_ATampInputTypeDef;
+
+
+typedef struct
+{
+  uint32_t ActiveFilter;                /*!< Specifies the Active tamper filter enable.
+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Filter */
+
+  uint32_t ActiveAsyncPrescaler;        /*!< Specifies the Active Tamper asynchronous Prescaler clock.
+                                             This parameter can be a value of
+                                             @ref RTCEx_ActiveTamper_Async_prescaler */
+
+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the timeStamp on tamper detection.
+                                             This parameter can be a value of
+                                             @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+
+  uint32_t ActiveOutputChangePeriod;    /*!< Specifies the Active Tamper output change period.
+                                             This parameter can be a value from 0 to 7 */
+
+  uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32];
+  /*!< Specifies the RNG Seed value.
+       This parameter is an array of value from 0 to 0xFFFFFFFF */
+
+  RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB];
+  /*!< Specifies configuration of all active tampers.
+       The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel */
+} RTC_ActiveTampersTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t IntTamper;                   /*!< Specifies the Internal Tamper Pin.
+                                             This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
+
+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
+                                             This parameter can be a value of
+                                             @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+
+  uint32_t NoErase;                     /*!< Specifies the internal Tamper no erase mode.
+                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
+
+} RTC_InternalTamperTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Secure_State_structure_definition RTCEx Secure structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t rtcSecureFull;               /*!< Specifies If the RTC is fully secure or not.
+                                             This parameter can be a value of @ref RTCEx_RTC_Secure_Full */
+
+  uint32_t rtcNonSecureFeatures;        /*!< Specifies the non-secure features.
+                                             This parameter is only relevant if RTC is not fully secure
+                                             (rtcSecureFull == RTC_SECURE_FULL_NO).
+                                             This parameter can be a combination of
+                                             @ref RTCEx_RTC_NonSecure_Features */
+
+  uint32_t tampSecureFull;              /*!< Specifies If the TAMP is fully secure or not execpt monotonic counters
+                                             and BackUp registers.
+                                             This parameter can be a value of @ref RTCEx_TAMP_Secure_Full */
+
+  uint32_t backupRegisterStartZone2;    /*!< Specifies the backup register start zone 2.
+                                             Zone 1 : read secure write secure.
+                                             Zone 2 : read non-secure  write secure.
+                                             This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
+                                             the register.
+                                             Warning : this parameter is shared with RTC_PrivilegeStateTypeDef */
+
+  uint32_t backupRegisterStartZone3;    /*!< Specifies the backup register start zone 3.
+                                             Zone 3 : read non-secure  write non-secure.
+                                             This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to
+                                             specify the register.
+                                             Warning : this parameter is shared with RTC_PrivilegeStateTypeDef */
+
+  uint32_t MonotonicCounterSecure;      /*!< Specifies If the monotonic counter is secure or not.
+                                             This parameter can be a value of
+                                             @ref RTCEx_TAMP_Monotonic_Counter_Secure */
+} RTC_SecureStateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Privilege_State_structure_definition RTCEx Privilege structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t rtcPrivilegeFull;            /*!< Specifies If the RTC is fully privileged or not.
+                                             This parameter can be a value of @ref RTCEx_RTC_Privilege_Full */
+
+  uint32_t rtcPrivilegeFeatures;        /*!< Specifies the privileged features.
+                                             This parameter is only relevant if RTC is not fully privileged
+                                             (rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO).
+                                             This parameter can be a combination of
+                                             @ref RTCEx_RTC_Privilege_Features */
+
+  uint32_t tampPrivilegeFull;           /*!< Specifies If the TAMP is fully privileged or not execpt monotonic
+                                             counters and BackUp registers.
+                                             This parameter can be a value of @ref RTCEx_TAMP_Privilege_Full */
+
+  uint32_t backupRegisterPrivZone;      /*!< Specifies backup register zone to be privileged.
+                                             This parameter can be a combination of
+                                             @ref RTCEx_Backup_Reg_Privilege_zone.
+                                             Warning : this parameter is writable in secure mode or if trustzone is
+                                             disabled */
+
+  uint32_t backupRegisterStartZone2;    /*!< Specifies the backup register start zone 2.
+                                             Zone 1 : read secure, write secure.
+                                             Zone 2 : read non-secure, write secure.
+                                             This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
+                                             the register .
+                                             Warning : this parameter is writable in secure mode or if trustzone is
+                                             disabled.
+                                             Warning : this parameter is shared with RTC_SecureStateTypeDef */
+
+  uint32_t backupRegisterStartZone3;    /*!< Specifies the backup register start zone 3.
+                                             Zone 3 : read non-secure, write non-secure.
+                                             This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify
+                                             the register.
+                                             Warning : this parameter is writable in secure mode or if trustzone is
+                                             disabled.
+                                             Warning : this parameter is shared with RTC_SecureStateTypeDef */
+
+  uint32_t MonotonicCounterPrivilege;   /*!< Specifies If the monotonic counter is privileged or not.
+                                             This parameter can be a value of
+                                             @ref RTCEx_TAMP_Monotonic_Counter_Privilege */
+} RTC_PrivilegeStateTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
+  * @{
+  */
+#define RTC_TIMESTAMPEDGE_RISING           0U
+#define RTC_TIMESTAMPEDGE_FALLING          RTC_CR_TSEDGE
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
+  * @{
+  */
+#define RTC_TIMESTAMPPIN_DEFAULT           0U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
+  * @{
+  */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16       0U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8        RTC_CR_WUCKSEL_0
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4        RTC_CR_WUCKSEL_1
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2        (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS     RTC_CR_WUCKSEL_2
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS     (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
+  * @{
+  */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC       0U                    /*!< If RTCCLK = 32768 Hz, Smooth calibration period
+                                                                      is 32s, else 2exp20 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC       RTC_CALR_CALW16       /*!< If RTCCLK = 32768 Hz, Smooth calibration period
+                                                                      is 16s, else 2exp19 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC        RTC_CALR_CALW8        /*!< If RTCCLK = 32768 Hz, Smooth calibration period
+                                                                      is 8s, else 2exp18 RTCCLK pulses  */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
+  * @{
+  */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET     RTC_CALR_CALP         /*!< The number of RTCCLK pulses added
+                                                                      during a X -second window = Y - CALM[8:0]
+                                                                      with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET   0U                    /*!< The number of RTCCLK pulses subbstited
+                                                                      during a 32-second window = CALM[8:0]     */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions
+  * @{
+  */
+#define RTC_LPCAL_SET                      RTC_CALR_LPCAL        /*!< Calibration window is 2exp20 ck_apre, which is the required configuration for ultra-low consumption mode. */
+#define RTC_LPCAL_RESET                    0U                    /*!< Calibration window is 2exp20 RTCCLK, which is a high-consumption mode.
+                                                                      This mode should be set only when less
+                                                                      than 32s calibration window is required. */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
+  * @{
+  */
+#define RTC_CALIBOUTPUT_512HZ              0U
+#define RTC_CALIBOUTPUT_1HZ                RTC_CR_COSEL
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
+  * @{
+  */
+#define RTC_SHIFTADD1S_RESET               0U
+#define RTC_SHIFTADD1S_SET                 RTC_SHIFTR_ADD1S
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pins  RTCEx Tamper Pins Definition
+  * @{
+  */
+#define RTC_TAMPER_1                       TAMP_CR1_TAMP1E
+#define RTC_TAMPER_2                       TAMP_CR1_TAMP2E
+#define RTC_TAMPER_3                       TAMP_CR1_TAMP3E
+#define RTC_TAMPER_4                       TAMP_CR1_TAMP4E
+#define RTC_TAMPER_5                       TAMP_CR1_TAMP5E
+#define RTC_TAMPER_6                       TAMP_CR1_TAMP6E
+#define RTC_TAMPER_7                       TAMP_CR1_TAMP7E
+#define RTC_TAMPER_ALL                     (RTC_TAMPER_1 | RTC_TAMPER_2 |\
+                                            RTC_TAMPER_3 | RTC_TAMPER_4 |\
+                                            RTC_TAMPER_5 | RTC_TAMPER_6 |\
+                                            RTC_TAMPER_7)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Internal_Tamper_Pins  RTCEx Internal Tamper Pins Definition
+  * @{
+  */
+#define RTC_INT_TAMPER_1                   TAMP_CR1_ITAMP1E
+#define RTC_INT_TAMPER_2                   TAMP_CR1_ITAMP2E
+#define RTC_INT_TAMPER_3                   TAMP_CR1_ITAMP3E
+#define RTC_INT_TAMPER_4                   TAMP_CR1_ITAMP4E
+#define RTC_INT_TAMPER_5                   TAMP_CR1_ITAMP5E
+#define RTC_INT_TAMPER_6                   TAMP_CR1_ITAMP6E
+#define RTC_INT_TAMPER_7                   TAMP_CR1_ITAMP7E
+#define RTC_INT_TAMPER_8                   TAMP_CR1_ITAMP8E
+#define RTC_INT_TAMPER_9                   TAMP_CR1_ITAMP9E
+#define RTC_INT_TAMPER_11                  TAMP_CR1_ITAMP11E
+#define RTC_INT_TAMPER_ALL                 (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
+                                            RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
+                                            RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
+                                            RTC_INT_TAMPER_7 | RTC_INT_TAMPER_8 |\
+                                            RTC_INT_TAMPER_9 | RTC_INT_TAMPER_11)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Trigger  RTCEx Tamper Trigger
+  * @{
+  */
+#define RTC_TAMPERTRIGGER_RISINGEDGE       0U                    /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_FALLINGEDGE      1U                    /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_LOWLEVEL         2U                    /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_HIGHLEVEL        3U                    /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_MaskFlag  RTCEx Tamper MaskFlag
+  * @{
+  */
+#define RTC_TAMPERMASK_FLAG_DISABLE        0U
+#define RTC_TAMPERMASK_FLAG_ENABLE         1U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Maskable_nb  RTCEx Tampers maskable number
+  * @{
+  */
+#define RTC_TAMPER_MASKABLE_NB             3U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_EraseBackUp  RTCEx Tamper EraseBackUp
+  * @{
+  */
+#define RTC_TAMPER_ERASE_BACKUP_ENABLE     0U
+#define RTC_TAMPER_ERASE_BACKUP_DISABLE    1U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Filter  RTCEx Tamper Filter
+  * @{
+  */
+#define RTC_TAMPERFILTER_DISABLE           0U                    /*!< Tamper filter is disabled */
+#define RTC_TAMPERFILTER_2SAMPLE           TAMP_FLTCR_TAMPFLT_0  /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE           TAMP_FLTCR_TAMPFLT_1  /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE           TAMP_FLTCR_TAMPFLT    /*!< Tamper is activated after 8 consecutive samples at the active level */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies  RTCEx Tamper Sampling Frequencies
+  * @{
+  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0U                                                  /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  TAMP_FLTCR_TAMPFREQ_0                               /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   TAMP_FLTCR_TAMPFREQ_1                               /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1)     /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   TAMP_FLTCR_TAMPFREQ_2                               /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2)     /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024  */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2)     /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512   */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
+                                                 TAMP_FLTCR_TAMPFREQ_2)                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256   */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration  RTCEx Tamper Pin Precharge Duration
+  * @{
+  */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK  0U                                              /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK  TAMP_FLTCR_TAMPPRCH_0                           /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK  TAMP_FLTCR_TAMPPRCH_1                           /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK  (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Pull_UP  RTCEx Tamper Pull UP
+  * @{
+  */
+#define RTC_TAMPER_PULLUP_ENABLE           0U                    /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_DISABLE          TAMP_FLTCR_TAMPPUDIS  /*!< Tamper pins pre-charge is disabled          */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions
+  * @{
+  */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0U               /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_CR_TAMPTS    /*!< TimeStamp on Tamper Detection event saved        */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Tamper_Detection_Output RTCEx Tamper detection output Definitions
+  * @{
+  */
+#define RTC_TAMPERDETECTIONOUTPUT_DISABLE  0U                    /*!< Tamper detection output disable on TAMPALRM */
+#define RTC_TAMPERDETECTIONOUTPUT_ENABLE   RTC_CR_TAMPOE         /*!< Tamper detection output enable on TAMPALRM  */
+/**
+  * @}
+  */
+
+
+/** @defgroup RTCEx_Tamper_Interrupt  RTCEx Tamper Interrupt
+  * @{
+  */
+#define RTC_IT_TAMP_1                      TAMP_IER_TAMP1IE      /*!< Tamper 1 Interrupt */
+#define RTC_IT_TAMP_2                      TAMP_IER_TAMP2IE      /*!< Tamper 2 Interrupt */
+#define RTC_IT_TAMP_3                      TAMP_IER_TAMP3IE      /*!< Tamper 3 Interrupt */
+#define RTC_IT_TAMP_4                      TAMP_IER_TAMP4IE      /*!< Tamper 4 Interrupt */
+#define RTC_IT_TAMP_5                      TAMP_IER_TAMP5IE      /*!< Tamper 5 Interrupt */
+#define RTC_IT_TAMP_6                      TAMP_IER_TAMP6IE      /*!< Tamper 6 Interrupt */
+#define RTC_IT_TAMP_7                      TAMP_IER_TAMP7IE      /*!< Tamper 7 Interrupt */
+#define RTC_IT_TAMP_ALL                    (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 |\
+                                            RTC_IT_TAMP_3 | RTC_IT_TAMP_4 |\
+                                            RTC_IT_TAMP_5 | RTC_IT_TAMP_6 |\
+                                            RTC_IT_TAMP_7)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Internal_Tamper_Interrupt  RTCEx Internal Tamper Interrupt
+  * @{
+  */
+#define RTC_IT_INT_TAMP_1                  TAMP_IER_ITAMP1IE     /*!< Tamper 1 internal Interrupt  */
+#define RTC_IT_INT_TAMP_2                  TAMP_IER_ITAMP2IE     /*!< Tamper 2 internal Interrupt  */
+#define RTC_IT_INT_TAMP_3                  TAMP_IER_ITAMP3IE     /*!< Tamper 3 internal Interrupt  */
+#define RTC_IT_INT_TAMP_4                  TAMP_IER_ITAMP4IE     /*!< Tamper 4 internal Interrupt  */
+#define RTC_IT_INT_TAMP_5                  TAMP_IER_ITAMP5IE     /*!< Tamper 5 internal Interrupt  */
+#define RTC_IT_INT_TAMP_6                  TAMP_IER_ITAMP6IE     /*!< Tamper 6 internal Interrupt  */
+#define RTC_IT_INT_TAMP_7                  TAMP_IER_ITAMP7IE     /*!< Tamper 7 internal Interrupt  */
+#define RTC_IT_INT_TAMP_8                  TAMP_IER_ITAMP8IE     /*!< Tamper 8 internal Interrupt  */
+#define RTC_IT_INT_TAMP_9                  TAMP_IER_ITAMP9IE     /*!< Tamper 9 internal Interrupt  */
+#define RTC_IT_INT_TAMP_11                 TAMP_IER_ITAMP11IE    /*!< Tamper 11 internal Interrupt */
+#define RTC_IT_INT_TAMP_ALL                (RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\
+                                            RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_4 |\
+                                            RTC_IT_INT_TAMP_5 | RTC_IT_INT_TAMP_6 |\
+                                            RTC_IT_INT_TAMP_7 | RTC_IT_INT_TAMP_8 |\
+                                            RTC_IT_INT_TAMP_9 | RTC_IT_INT_TAMP_11)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Flags  RTCEx Flags
+  * @{
+  */
+#define RTC_FLAG_TAMP_1                    TAMP_SR_TAMP1F
+#define RTC_FLAG_TAMP_2                    TAMP_SR_TAMP2F
+#define RTC_FLAG_TAMP_3                    TAMP_SR_TAMP3F
+#define RTC_FLAG_TAMP_4                    TAMP_SR_TAMP4F
+#define RTC_FLAG_TAMP_5                    TAMP_SR_TAMP5F
+#define RTC_FLAG_TAMP_6                    TAMP_SR_TAMP6F
+#define RTC_FLAG_TAMP_7                    TAMP_SR_TAMP7F
+#define RTC_FLAG_TAMP_ALL                  (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\
+                                            RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6 |\
+                                            RTC_FLAG_TAMP_7)
+
+#define RTC_FLAG_INT_TAMP_1                TAMP_SR_ITAMP1F
+#define RTC_FLAG_INT_TAMP_2                TAMP_SR_ITAMP2F
+#define RTC_FLAG_INT_TAMP_3                TAMP_SR_ITAMP3F
+#define RTC_FLAG_INT_TAMP_4                TAMP_SR_ITAMP4F
+#define RTC_FLAG_INT_TAMP_5                TAMP_SR_ITAMP5F
+#define RTC_FLAG_INT_TAMP_6                TAMP_SR_ITAMP6F
+#define RTC_FLAG_INT_TAMP_7                TAMP_SR_ITAMP7F
+#define RTC_FLAG_INT_TAMP_8                TAMP_SR_ITAMP8F
+#define RTC_FLAG_INT_TAMP_9                TAMP_SR_ITAMP9F
+#define RTC_FLAG_INT_TAMP_11               TAMP_SR_ITAMP11F
+#define RTC_FLAG_INT_TAMP_ALL              (RTC_FLAG_INT_TAMP_1  | RTC_FLAG_INT_TAMP_2  |\
+                                            RTC_FLAG_INT_TAMP_3  | RTC_FLAG_INT_TAMP_4  |\
+                                            RTC_FLAG_INT_TAMP_5  | RTC_FLAG_INT_TAMP_6  |\
+                                            RTC_FLAG_INT_TAMP_7  | RTC_FLAG_INT_TAMP_8  |\
+                                            RTC_FLAG_INT_TAMP_9  | RTC_FLAG_INT_TAMP_11)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions
+  * @{
+  */
+#define RTC_ATAMP_ENABLE                   1U
+#define RTC_ATAMP_DISABLE                  0U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions
+  * @{
+  */
+#define RTC_ATAMP_INTERRUPT_ENABLE         1U
+#define RTC_ATAMP_INTERRUPT_DISABLE        0U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_ActiveTamper_Filter RTCEx_ActiveTamper_Filter Definitions
+  * @{
+  */
+#define RTC_ATAMP_FILTER_ENABLE            TAMP_ATCR1_FLTEN
+#define RTC_ATAMP_FILTER_DISABLE           0U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions
+  * @{
+  */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK         0U                                                                     /*!< RTCCLK       */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_2       TAMP_ATCR1_ATCKSEL_0                                                   /*!< RTCCLK/2     */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_4       TAMP_ATCR1_ATCKSEL_1                                                   /*!< RTCCLK/4     */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_8       (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)                          /*!< RTCCLK/8     */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_16      TAMP_ATCR1_ATCKSEL_2                                                   /*!< RTCCLK/16    */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_32      (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)                          /*!< RTCCLK/32    */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_64      (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)                          /*!< RTCCLK/64    */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_128     (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)   /*!< RTCCLK/128   */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_256     TAMP_ATCR1_ATCKSEL_3                                                   /*!< RTCCLK/256   */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_512     (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_0)                          /*!< RTCCLK/512   */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_1024    (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1)                          /*!< RTCCLK/1024  */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_2048    (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)   /*!< RTCCLK/2048  */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_4096    (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2)                          /*!< RTCCLK/4096  */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_8192    (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)   /*!< RTCCLK/8192  */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_16384   (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)   /*!< RTCCLK/16384 */
+#define RTC_ATAMP_ASYNCPRES_RTCCLK_32768   (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 |\
+                                            TAMP_ATCR1_ATCKSEL_0)                                                 /*!< RTCCLK/32768 */
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_ActiveTamper_Sel  RTCEx Active Tamper selection Definition
+  * @{
+  */
+#define RTC_ATAMP_1                        0U                    /*!< Tamper 1 */
+#define RTC_ATAMP_2                        1U                    /*!< Tamper 2 */
+#define RTC_ATAMP_3                        2U                    /*!< Tamper 3 */
+#define RTC_ATAMP_4                        3U                    /*!< Tamper 4 */
+#define RTC_ATAMP_5                        4U                    /*!< Tamper 5 */
+#define RTC_ATAMP_6                        5U                    /*!< Tamper 6 */
+#define RTC_ATAMP_7                        6U                    /*!< Tamper 7 */
+#define RTC_ATAMP_8                        7U                    /*!< Tamper 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_MonotonicCounter_Instance  RTCEx Monotonic Counter Instance Definition
+  * @{
+  */
+#define RTC_MONOTONIC_COUNTER_1            0U                    /*!< Monotonic counter 1 */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Backup_Registers  RTCEx Backup Registers Definition
+  * @{
+  */
+#define RTC_BKP_NUMBER                     RTC_BKP_NB
+#define RTC_BKP_DR0                        0x00U
+#define RTC_BKP_DR1                        0x01U
+#define RTC_BKP_DR2                        0x02U
+#define RTC_BKP_DR3                        0x03U
+#define RTC_BKP_DR4                        0x04U
+#define RTC_BKP_DR5                        0x05U
+#define RTC_BKP_DR6                        0x06U
+#define RTC_BKP_DR7                        0x07U
+#define RTC_BKP_DR8                        0x08U
+#define RTC_BKP_DR9                        0x09U
+#define RTC_BKP_DR10                       0x0AU
+#define RTC_BKP_DR11                       0x0BU
+#define RTC_BKP_DR12                       0x0CU
+#define RTC_BKP_DR13                       0x0DU
+#define RTC_BKP_DR14                       0x0EU
+#define RTC_BKP_DR15                       0x0FU
+#define RTC_BKP_DR16                       0x10U
+#define RTC_BKP_DR17                       0x11U
+#define RTC_BKP_DR18                       0x12U
+#define RTC_BKP_DR19                       0x13U
+#define RTC_BKP_DR20                       0x14U
+#define RTC_BKP_DR21                       0x15U
+#define RTC_BKP_DR22                       0x16U
+#define RTC_BKP_DR23                       0x17U
+#define RTC_BKP_DR24                       0x18U
+#define RTC_BKP_DR25                       0x19U
+#define RTC_BKP_DR26                       0x1AU
+#define RTC_BKP_DR27                       0x1BU
+#define RTC_BKP_DR28                       0x1CU
+#define RTC_BKP_DR29                       0x1DU
+#define RTC_BKP_DR30                       0x1EU
+#define RTC_BKP_DR31                       0x1FU
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Binary_Mode RTC Binary Mode (32-bit free-running counter configuration).
+  *           Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions.
+  * @{
+  */
+#define RTC_BINARY_NONE                    0U                    /*!< Free running BCD calendar mode (Binary mode disabled) */
+#define RTC_BINARY_ONLY                    RTC_ICSR_BIN_0        /*!< Free running Binary mode (BCD mode disabled)          */
+#define RTC_BINARY_MIX                     RTC_ICSR_BIN_1        /*!< Free running BCD calendar and Binary modes            */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented
+  *           using the SSR Least Significant Bits.
+  * @{
+  */
+#define RTC_BINARY_MIX_BCDU_0              0U                           /*!<  The 1s BCD calendar increment is generated each time SS[7:0] = 0  */
+#define RTC_BINARY_MIX_BCDU_1              (0x1UL << RTC_ICSR_BCDU_Pos) /*!<  The 1s BCD calendar increment is generated each time SS[8:0] = 0  */
+#define RTC_BINARY_MIX_BCDU_2              (0x2UL << RTC_ICSR_BCDU_Pos) /*!<  The 1s BCD calendar increment is generated each time SS[9:0] = 0  */
+#define RTC_BINARY_MIX_BCDU_3              (0x3UL << RTC_ICSR_BCDU_Pos) /*!<  The 1s BCD calendar increment is generated each time SS[10:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_4              (0x4UL << RTC_ICSR_BCDU_Pos) /*!<  The 1s BCD calendar increment is generated each time SS[11:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_5              (0x5UL << RTC_ICSR_BCDU_Pos) /*!<  The 1s BCD calendar increment is generated each time SS[12:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_6              (0x6UL << RTC_ICSR_BCDU_Pos) /*!<  The 1s BCD calendar increment is generated each time SS[13:0] = 0 */
+#define RTC_BINARY_MIX_BCDU_7              (0x7UL << RTC_ICSR_BCDU_Pos) /*!<  The 1s BCD calendar increment is generated each time SS[14:0] = 0 */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary or mix mode
+  *           Masks Definitions.
+  * @{
+  */
+#define RTC_ALARMSUBSECONDBINMASK_ALL      0U                                /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_1   (1UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:1] are don't care in Alarm comparison. Only SS[0] is compared            */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_2   (2UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:2] are don't care in Alarm comparison. Only SS[1:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_3   (3UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:3] are don't care in Alarm comparison. Only SS[2:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_4   (4UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:4] are don't care in Alarm comparison. Only SS[3:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_5   (5UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:5] are don't care in Alarm comparison. Only SS[4:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_6   (6UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:6] are don't care in Alarm comparison. Only SS[5:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_7   (7UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:7] are don't care in Alarm comparison. Only SS[6:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_8   (8UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:8] are don't care in Alarm comparison. Only SS[7:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_9   (9UL << RTC_ALRMASSR_MASKSS_Pos)  /*!< SS[31:9] are don't care in Alarm comparison. Only SS[8:0] are compared         */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_10  (10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:10] are don't care in Alarm comparison. Only SS[9:0] are compared        */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_11  (11UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:11] are don't care in Alarm comparison. Only SS[10:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_12  (12UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:12] are don't care in Alarm comparison.Only SS[11:0] are compared        */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_13  (13UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:13] are don't care in Alarm comparison. Only SS[12:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_14  (14UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:14] are don't care in Alarm comparison. Only SS[13:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_15  (15UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:15] are don't care in Alarm comparison. Only SS[14:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_16  (16UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:16] are don't care in Alarm comparison. Only SS[15:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_17  (17UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:17] are don't care in Alarm comparison. Only SS[16:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_18  (18UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:18] are don't care in Alarm comparison. Only SS[17:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_19  (19UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:19] are don't care in Alarm comparison. Only SS[18:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_20  (20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:20] are don't care in Alarm comparison. Only SS[19:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_21  (21UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:21] are don't care in Alarm comparison. Only SS[20:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_22  (22UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:22] are don't care in Alarm comparison. Only SS[21:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_23  (23UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:23] are don't care in Alarm comparison. Only SS[22:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_24  (24UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:24] are don't care in Alarm comparison. Only SS[23:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_25  (25UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:25] are don't care in Alarm comparison. Only SS[24:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_26  (26UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:26] are don't care in Alarm comparison. Only SS[25:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_27  (27UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:27] are don't care in Alarm comparison. Only SS[26:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_28  (28UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:28] are don't care in Alarm comparison. Only SS[27:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_29  (29UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:29] are don't care in Alarm comparison. Only SS[28:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31_30  (30UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:30] are don't care in Alarm comparison. Only SS[29:0] are compared       */
+#define RTC_ALARMSUBSECONDBINMASK_SS31     (31UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31] is don't care in Alarm comparison. Only SS[30:0] are compared           */
+#define RTC_ALARMSUBSECONDBINMASK_NONE     RTC_ALRMASSR_MASKSS               /*!< SS[31:0] are compared and must match to activate alarm                         */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions RTC Alarm Sub Seconds
+  *           with binary mode auto clear Definitions
+  * @{
+  */
+#define RTC_ALARMSUBSECONDBIN_AUTOCLR_NO   0UL                   /*!< The synchronous Binary counter(SS[31:0] in RTC_SSR) is free-running */
+#define RTC_ALARMSUBSECONDBIN_AUTOCLR_YES  RTC_ALRMASSR_SSCLR
+/*!< The synchronous Binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0]
+     value and is automatically reloaded with 0xFFFF FFFF whenreaching RTC_ALRMABINR -> SS[31:0]. */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_RTC_Secure_Full  RTCEx Secure Definition
+  * @{
+  */
+#define RTC_SECURE_FULL_YES                RTC_SECCFGR_SEC       /*!< RTC full secure */
+#define RTC_SECURE_FULL_NO                 0U                    /*!< RTC is not full secure, features can be unsecure. See RTCEx_RTC_NonSecure_Features */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_RTC_NonSecure_Features  RTCEx Secure Features Definition
+  * @{
+  */
+#define RTC_NONSECURE_FEATURE_NONE         0U
+#define RTC_NONSECURE_FEATURE_INIT         RTC_SECCFGR_INITSEC   /*!< Initialization */
+#define RTC_NONSECURE_FEATURE_CAL          RTC_SECCFGR_CALSEC    /*!< Calibration    */
+#define RTC_NONSECURE_FEATURE_TS           RTC_SECCFGR_TSSEC     /*!< Time stamp     */
+#define RTC_NONSECURE_FEATURE_WUT          RTC_SECCFGR_WUTSEC    /*!< Wake up timer  */
+#define RTC_NONSECURE_FEATURE_ALRA         RTC_SECCFGR_ALRASEC   /*!< Alarm A        */
+#define RTC_NONSECURE_FEATURE_ALRB         RTC_SECCFGR_ALRBSEC   /*!< Alarm B        */
+
+#define RTC_NONSECURE_FEATURE_ALL          (RTC_SECCFGR_INITSEC |  RTC_SECCFGR_CALSEC | \
+                                            RTC_SECCFGR_TSSEC | RTC_SECCFGR_WUTSEC | \
+                                            RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TAMP_Secure_Full  RTCEx TAMP Secure Definition
+  * @{
+  */
+#define TAMP_SECURE_FULL_YES               TAMP_SECCFGR_TAMPSEC  /*!< TAMPER full secure   */
+#define TAMP_SECURE_FULL_NO                0U                    /*!< TAMPER is not secure */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TAMP_Monotonic_Counter_Secure  RTCEx TAMP Monotonic Counter Secure Definition
+  * @{
+  */
+#define TAMP_MONOTONIC_CNT_SECURE_YES      TAMP_SECCFGR_CNT1SEC  /*!< TAMPER Monotonic Counter secure        */
+#define TAMP_MONOTONIC_CNT_SECURE_NO       0U                    /*!< TAMPER Monotonic Counter is not secure */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_RTC_Privilege_Full  RTCEx Privilege Full Definition
+  * @{
+  */
+#define RTC_PRIVILEGE_FULL_YES             RTC_PRIVCFGR_PRIV
+#define RTC_PRIVILEGE_FULL_NO              0U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_RTC_Privilege_Features  RTCEx Privilege Features Definition
+  * @{
+  */
+#define RTC_PRIVILEGE_FEATURE_NONE         0U
+#define RTC_PRIVILEGE_FEATURE_INIT         RTC_PRIVCFGR_INITPRIV /*!< Initialization */
+#define RTC_PRIVILEGE_FEATURE_CAL          RTC_PRIVCFGR_CALPRIV  /*!< Calibration    */
+#define RTC_PRIVILEGE_FEATURE_TS           RTC_PRIVCFGR_TSPRIV   /*!< Time stamp     */
+#define RTC_PRIVILEGE_FEATURE_WUT          RTC_PRIVCFGR_WUTPRIV  /*!< Wake up timer  */
+#define RTC_PRIVILEGE_FEATURE_ALRA         RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A        */
+#define RTC_PRIVILEGE_FEATURE_ALRB         RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B        */
+
+#define RTC_PRIVILEGE_FEATURE_ALL          (RTC_PRIVCFGR_INITPRIV |  RTC_PRIVCFGR_CALPRIV | \
+                                            RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | \
+                                            RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV)
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TAMP_Privilege_Full  RTCEx TAMP security Definition
+  * @{
+  */
+#define TAMP_PRIVILEGE_FULL_YES            TAMP_PRIVCFGR_TAMPPRIV
+#define TAMP_PRIVILEGE_FULL_NO             0U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TAMP_Device_Secrets_Erase_Conf  RTCEx TAMP Device Secrets Erase Configuration Definition
+  * @{
+  */
+#define TAMP_DEVICESECRETS_ERASE_NONE      0U                   /*!< No Erase    */
+#define TAMP_DEVICESECRETS_ERASE_BKPSRAM   TAMP_RPCFGR_RPCFG0   /*!< Backup SRAM */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_TAMP_Monotonic_Counter_Privilege  RTCEx TAMP Monotonic Counter Privilege Definition
+  * @{
+  */
+#define TAMP_MONOTONIC_CNT_PRIVILEGE_YES   TAMP_PRIVCFGR_CNT1PRIV
+#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO    0U
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Backup_Reg_Privilege_zone  RTCEx Privilege Backup register privilege zone Definition
+  * @{
+  */
+#define RTC_PRIVILEGE_BKUP_ZONE_NONE       0U
+#define RTC_PRIVILEGE_BKUP_ZONE_1          TAMP_PRIVCFGR_BKPRWPRIV
+#define RTC_PRIVILEGE_BKUP_ZONE_2          TAMP_PRIVCFGR_BKPWPRIV
+#define RTC_PRIVILEGE_BKUP_ZONE_ALL        (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+  * @{
+  */
+
+/** @brief  Clear the specified RTC pending flag.
+  * @param  __HANDLE__ specifies the RTC Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref RTC_CLEAR_SSRUF              Clear SSR underflow flag
+  *            @arg @ref RTC_CLEAR_ITSF               Clear Internal Time-stamp flag
+  *            @arg @ref RTC_CLEAR_TSOVF              Clear Time-stamp overflow flag
+  *            @arg @ref RTC_CLEAR_TSF                Clear Time-stamp flag
+  *            @arg @ref RTC_CLEAR_WUTF               Clear Wakeup timer flag
+  *            @arg @ref RTC_CLEAR_ALRBF              Clear Alarm B flag
+  *            @arg @ref RTC_CLEAR_ALRAF              Clear Alarm A flag
+  * @retval None
+  */
+#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__)   (RTC->SCR = (__FLAG__))
+
+/** @brief  Check whether the specified RTC flag is set or not.
+  * @param  __HANDLE__ specifies the RTC Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref RTC_FLAG_RECALPF             Recalibration pending Flag
+  *            @arg @ref RTC_FLAG_INITF               Initialization flag
+  *            @arg @ref RTC_FLAG_RSF                 Registers synchronization flag
+  *            @arg @ref RTC_FLAG_INITS               Initialization status flag
+  *            @arg @ref RTC_FLAG_SHPF                Shift operation pending flag
+  *            @arg @ref RTC_FLAG_WUTWF               Wakeup timer write flag
+  *            @arg @ref RTC_FLAG_ITSF                Internal Time-stamp flag
+  *            @arg @ref RTC_FLAG_TSOVF               Time-stamp overflow flag
+  *            @arg @ref RTC_FLAG_TSF                 Time-stamp flag
+  *            @arg @ref RTC_FLAG_WUTF                Wakeup timer flag
+  *            @arg @ref RTC_FLAG_ALRBF               Alarm B flag
+  *            @arg @ref RTC_FLAG_ALRAF               Alarm A flag
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)( \
+                               ((__FLAG__) == RTC_FLAG_RECALPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == \
+                                                                RTC_ICSR_RECALPF) : \
+                               ((__FLAG__) == RTC_FLAG_INITF)   ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == \
+                                                                RTC_ICSR_INITF) : \
+                               ((__FLAG__) == RTC_FLAG_RSF)     ? (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == \
+                                                                RTC_ICSR_RSF) : \
+                               ((__FLAG__) == RTC_FLAG_INITS)   ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == \
+                                                                RTC_ICSR_INITS) : \
+                               ((__FLAG__) == RTC_FLAG_SHPF)    ? (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == \
+                                                                RTC_ICSR_SHPF) : \
+                               ((__FLAG__) == RTC_FLAG_WUTWF)   ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == \
+                                                                RTC_ICSR_WUTWF) : \
+                               ((__FLAG__) == RTC_FLAG_SSRUF)   ? (READ_BIT(RTC->SR, RTC_SR_SSRUF) == \
+                                                                RTC_SR_SSRUF) : \
+                               ((__FLAG__) == RTC_FLAG_ITSF)    ? (READ_BIT(RTC->SR, RTC_SR_ITSF) == \
+                                                                RTC_SR_ITSF) : \
+                               ((__FLAG__) == RTC_FLAG_TSOVF)   ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == \
+                                                                RTC_SR_TSOVF) : \
+                               ((__FLAG__) == RTC_FLAG_TSF)     ? (READ_BIT(RTC->SR, RTC_SR_TSF) == \
+                                                                RTC_SR_TSF): \
+                               ((__FLAG__) == RTC_FLAG_WUTF)    ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == \
+                                                                RTC_SR_WUTF): \
+                               ((__FLAG__) == RTC_FLAG_ALRBF)   ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == \
+                                                                RTC_SR_ALRBF) : \
+                               ((__FLAG__) == RTC_FLAG_ALRAF)   ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == \
+                                                                RTC_SR_ALRAF) : \
+                               (0U)) /* Return 0 because it is an invalid parameter value */
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+  * @{
+  */
+
+/**
+  * @brief  Enable the RTC WakeUp Timer peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      (RTC->CR |= (RTC_CR_WUTE))
+
+/**
+  * @brief  Disable the RTC WakeUp Timer peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     (RTC->CR &= ~(RTC_CR_WUTE))
+
+/**
+  * @brief  Enable the RTC WakeUpTimer interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (RTC->CR |= (RTC_CR_WUTIE))
+
+/**
+  * @brief  Disable the RTC WakeUpTimer interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   (RTC->CR &= ~(RTC_CR_WUTIE))
+
+/**
+  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((RTC->MISR) & (RTC_MISR_WUTMF)) != 0U)
+
+/**
+  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((RTC->CR) & (RTC_CR_WUTIE)) != 0U)
+
+/**
+  * @brief  Get the selected RTC WakeUpTimers flag status.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
+  *          This parameter can be:
+  *             @arg @ref RTC_FLAG_WUTF
+  *             @arg @ref RTC_FLAG_WUTWF
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \
+                            ((__FLAG__) == RTC_FLAG_WUTF)  ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == RTC_SR_WUTF):\
+                            ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == RTC_ICSR_WUTWF):\
+                            (0U)) /* Return 0 because it is an invalid parameter value */
+
+/**
+  * @brief  Clear the RTC Wake Up timers pending flags.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
+  *         This parameter can be:
+  *            @arg @ref RTC_FLAG_WUTF
+  * @retval None
+  */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)  (WRITE_REG(RTC->SCR, RTC_SCR_CWUTF))
+
+/**
+  * @}
+  */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Timestamp
+  * @{
+  */
+
+/**
+  * @brief  Enable the RTC TimeStamp peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       (RTC->CR |= (RTC_CR_TSE))
+
+/**
+  * @brief  Disable the RTC TimeStamp peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      (RTC->CR &= ~(RTC_CR_TSE))
+
+/**
+  * @brief  Enable the RTC TimeStamp interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_TS TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     (RTC->CR |= (RTC_CR_TSIE))
+
+/**
+  * @brief  Disable the RTC TimeStamp interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_TS TimeStamp interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    (RTC->CR &= ~(RTC_CR_TSIE))
+
+/**
+  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_TS TimeStamp interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((RTC->MISR) & (RTC_MISR_TSMF)) != 0U)
+
+/**
+  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_TS TimeStamp interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((RTC->CR) & (RTC_CR_TSIE)) != 0U)
+
+/**
+  * @brief  Get the selected RTC TimeStamps flag status.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
+  *         This parameter can be:
+  *            @arg @ref RTC_FLAG_TSF
+  *            @arg @ref RTC_FLAG_TSOVF
+  * @retval The state of __FLAG__ (TRUE or FALSE) or 255 if invalid parameter.
+  */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \
+                                ((__FLAG__) == RTC_FLAG_TSF)   ? (READ_BIT(RTC->SR, RTC_SR_TSF) == RTC_SR_TSF):\
+                                ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == RTC_SR_TSOVF):\
+                                (0U)) /* Return 0 because it is an invalid parameter value */
+
+/**
+  * @brief  Clear the RTC Time Stamps pending flags.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC TimeStamp Flag to clear.
+  *          This parameter can be:
+  *             @arg @ref RTC_FLAG_TSF
+  *             @arg @ref RTC_FLAG_TSOVF
+  * @retval None
+  */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \
+                                ((__FLAG__) == RTC_FLAG_TSF)   ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSF)):\
+                                ((__FLAG__) == RTC_FLAG_TSOVF) ? (WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF)):\
+                                (0U)) /* Dummy action because is an invalid parameter value */
+
+/**
+  * @brief  Enable the RTC internal TimeStamp peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                (RTC->CR |= (RTC_CR_ITSE))
+
+/**
+  * @brief  Disable the RTC internal TimeStamp peripheral.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               (RTC->CR &= ~(RTC_CR_ITSE))
+
+/**
+  * @brief  Get the selected RTC Internal Time Stamps flag status.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
+  *         This parameter can be:
+  *            @arg @ref RTC_FLAG_ITSF
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)   ((READ_BIT(RTC->SR, RTC_SR_ITSF) == RTC_SR_ITSF))
+
+/**
+  * @brief  Clear the RTC Internal Time Stamps pending flags.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
+  * This parameter can be:
+  *             @arg @ref RTC_FLAG_ITSF
+  * @retval None
+  */
+#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   (WRITE_REG(RTC->SCR, RTC_SCR_CITSF))
+
+/**
+  * @brief  Enable the RTC TimeStamp on Tamper detection.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       (RTC->CR |= (RTC_CR_TAMPTS))
+
+/**
+  * @brief  Disable the RTC TimeStamp on Tamper detection.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      (RTC->CR &= ~(RTC_CR_TAMPTS))
+
+/**
+  * @brief  Enable the RTC Tamper detection output.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__)                       (RTC->CR |= (RTC_CR_TAMPOE))
+
+/**
+  * @brief  Disable the RTC Tamper detection output.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__)                      (RTC->CR &= ~(RTC_CR_TAMPOE))
+
+/**
+  * @}
+  */
+
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Calibration
+  * @{
+  */
+
+/**
+  * @brief  Enable the RTC calibration output.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)               (RTC->CR |= (RTC_CR_COE))
+
+/**
+  * @brief  Disable the calibration output.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)              (RTC->CR &= ~(RTC_CR_COE))
+
+/**
+  * @brief  Enable the clock reference detection.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)               (RTC->CR |= (RTC_CR_REFCKON))
+
+/**
+  * @brief  Disable the clock reference detection.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)              (RTC->CR &= ~(RTC_CR_REFCKON))
+
+/**
+  * @brief  Get the selected RTC shift operations flag status.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
+  *          This parameter can be:
+  *             @arg @ref RTC_FLAG_SHPF
+  * @retval The state of __FLAG__ (TRUE or FALSE)
+  */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)  ((READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == RTC_ICSR_SHPF))
+/**
+  * @}
+  */
+
+/* ------------------------------Tamper----------------------------------*/
+/** @defgroup RTCEx_Tamper RTCEx tamper
+  * @{
+  */
+
+/**
+  * @brief  Enable the TAMP Tamper input detection.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __TAMPER__ specifies the RTC Tamper source to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg  RTC_TAMPER_ALL: All tampers
+  *            @arg  RTC_TAMPER_1: Tamper1
+  *            @arg  RTC_TAMPER_2: Tamper2
+  *            @arg  RTC_TAMPER_3: Tamper3
+  *            @arg  RTC_TAMPER_4: Tamper4
+  *            @arg  RTC_TAMPER_5: Tamper5
+  *            @arg  RTC_TAMPER_6: Tamper6
+  *            @arg  RTC_TAMPER_7: Tamper7
+  *            @arg  RTC_TAMPER_8: Tamper8
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__)           (TAMP->CR1 |= (__TAMPER__))
+
+/**
+  * @brief  Disable the TAMP Tamper input detection.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __TAMPER__ specifies the RTC Tamper sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg  RTC_TAMPER_ALL: All tampers
+  *            @arg  RTC_TAMPER_1: Tamper1
+  *            @arg  RTC_TAMPER_2: Tamper2
+  *            @arg  RTC_TAMPER_3: Tamper3
+  *            @arg  RTC_TAMPER_4: Tamper4
+  *            @arg  RTC_TAMPER_5: Tamper5
+  *            @arg  RTC_TAMPER_6: Tamper6
+  *            @arg  RTC_TAMPER_7: Tamper7
+  *            @arg  RTC_TAMPER_8: Tamper8
+  */
+#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__)           (TAMP->CR1 &= ~(__TAMPER__))
+
+
+/**************************************************************************************************/
+/**
+  * @brief  Enable the TAMP Tamper interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
+  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
+  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
+  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
+  *            @arg  RTC_IT_TAMP_4: Tamper4 interrupt
+  *            @arg  RTC_IT_TAMP_5: Tamper5 interrupt
+  *            @arg  RTC_IT_TAMP_6: Tamper6 interrupt
+  *            @arg  RTC_IT_TAMP_7: Tamper7 interrupt
+  *            @arg  RTC_IT_TAMP_8: Tamper8 interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        (TAMP->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the TAMP Tamper interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
+  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
+  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
+  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
+  *            @arg  RTC_IT_TAMP_4: Tamper4 interrupt
+  *            @arg  RTC_IT_TAMP_5: Tamper5 interrupt
+  *            @arg  RTC_IT_TAMP_6: Tamper6 interrupt
+  *            @arg  RTC_IT_TAMP_7: Tamper7 interrupt
+  *            @arg  RTC_IT_TAMP_8: Tamper8 interrupt
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       (TAMP->IER &= ~(__INTERRUPT__))
+
+
+/**************************************************************************************************/
+/**
+  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
+  *         This parameter can be:
+  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
+  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
+  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
+  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
+  *            @arg  RTC_IT_TAMP_4: Tamper4 interrupt
+  *            @arg  RTC_IT_TAMP_5: Tamper5 interrupt
+  *            @arg  RTC_IT_TAMP_6: Tamper6 interrupt
+  *            @arg  RTC_IT_TAMP_7: Tamper7 interrupt
+  *            @arg  RTC_IT_TAMP_8: Tamper8 interrupt
+  *            @arg  RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts
+  *            @arg  RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt
+  *            @arg  RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt
+  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
+  *            @arg  RTC_IT_INT_TAMP_4: Internal Tamper4 interrupt
+  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
+  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
+  *            @arg  RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt
+  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
+  *            @arg  RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt
+  *            @arg  RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE)
+  */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)    (((TAMP->MISR) & (__INTERRUPT__)) != 0U)
+
+/**
+  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
+  *         This parameter can be:
+  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
+  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
+  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
+  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
+  *            @arg  RTC_IT_TAMP_4: Tamper4 interrupt
+  *            @arg  RTC_IT_TAMP_5: Tamper5 interrupt
+  *            @arg  RTC_IT_TAMP_6: Tamper6 interrupt
+  *            @arg  RTC_IT_TAMP_7: Tamper7 interrupt
+  *            @arg  RTC_IT_TAMP_8: Tamper8 interrupt
+  *            @arg  RTC_IT_INT_TAMP_ALL: All internal tampers interrupts
+  *            @arg  RTC_IT_INT_TAMP_1: Internal Tamper1 interrupt
+  *            @arg  RTC_IT_INT_TAMP_2: Internal Tamper2 interrupt
+  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
+  *            @arg  RTC_IT_INT_TAMP_4: Internal Tamper4 interrupt
+  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
+  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
+  *            @arg  RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt
+  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
+  *            @arg  RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt
+  *            @arg  RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE)
+  */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((TAMP->IER) & (__INTERRUPT__)) != 0U)
+
+/**
+  * @brief  Get the selected RTC Tampers flag status.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TAMP_ALL: All tampers flag
+  *             @arg RTC_FLAG_TAMP_1: Tamper1 flag
+  *             @arg RTC_FLAG_TAMP_2: Tamper2 flag
+  *             @arg RTC_FLAG_TAMP_3: Tamper3 flag
+  *             @arg RTC_FLAG_TAMP_4: Tamper4 flag
+  *             @arg RTC_FLAG_TAMP_5: Tamper5 flag
+  *             @arg RTC_FLAG_TAMP_6: Tamper6 flag
+  *             @arg RTC_FLAG_TAMP_7: Tamper7 flag
+  *             @arg RTC_FLAG_TAMP_8: Tamper8 flag
+  *             @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag
+  *             @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag
+  *             @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag
+  *             @arg RTC_FLAG_INT_TAMP_4: Internal Tamper4 flag
+  *             @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag
+  *             @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag
+  *             @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag
+  *             @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag
+  *             @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag
+  *             @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag
+  * @retval The state of __FLAG__ (TRUE or FALSE)
+  */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((TAMP->SR) & (__FLAG__)) != 0U)
+
+/**
+  * @brief  Clear the RTC Tamper's pending flags.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_TAMP_ALL: All tampers flag
+  *             @arg RTC_FLAG_TAMP_1: Tamper1 flag
+  *             @arg RTC_FLAG_TAMP_2: Tamper2 flag
+  *             @arg RTC_FLAG_TAMP_3: Tamper3 flag
+  *             @arg RTC_FLAG_TAMP_4: Tamper4 flag
+  *             @arg RTC_FLAG_TAMP_5: Tamper5 flag
+  *             @arg RTC_FLAG_TAMP_6: Tamper6 flag
+  *             @arg RTC_FLAG_TAMP_7: Tamper7 flag
+  *             @arg RTC_FLAG_TAMP_8: Tamper8 flag
+  *             @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags
+  *             @arg RTC_FLAG_INT_TAMP_1: Internal Tamper1 flag
+  *             @arg RTC_FLAG_INT_TAMP_2: Internal Tamper2 flag
+  *             @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag
+  *             @arg RTC_FLAG_INT_TAMP_4: Internal Tamper4 flag
+  *             @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag
+  *             @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag
+  *             @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag
+  *             @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag
+  *             @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag
+  *             @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag
+  * @retval None
+  */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((TAMP->SCR) = (__FLAG__))
+/**
+  * @}
+  */
+
+/* --------------------------------- SSR Underflow ---------------------------------*/
+/** @defgroup RTCEx_SSR_Underflow RTC SSR Underflow
+  * @{
+  */
+
+/**
+  * @brief  Enable the RTC SSRU interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC SSRU interrupt sources to be enabled.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_SSRU SSRU interrupt
+  * @retval None
+  */
+#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (RTC->CR |= (RTC_CR_SSRUIE))
+
+/**
+  * @brief  Disable the RTC SSRU interrupt.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC SSRU interrupt sources to be disabled.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_SSRU SSRU interrupt
+  * @retval None
+  */
+#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__)   (RTC->CR &= ~(RTC_CR_SSRUIE))
+
+
+/**
+  * @brief  Check whether the specified RTC SSRU interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC SSRU interrupt to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_SSRU  SSRU interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE)
+  */
+#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__)       (((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U)
+/**
+  * @brief  Check whether the specified RTC SSRU interrupt has been enabled or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC SSRU interrupt sources to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_SSRU  SSRU interrupt
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE)
+  */
+#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((RTC->CR) & (RTC_CR_SSRUIE)) != 0U)
+
+/**
+  * @brief  Get the selected RTC SSRU's flag status.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC SSRU Flag is pending or not.
+  *          This parameter can be:
+  *             @arg @ref RTC_FLAG_SSRUF
+  * @retval The state of __FLAG__ (TRUE or FALSE)
+  */
+#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__)       ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF))
+
+/**
+  * @brief  Clear the RTC SSRU's pending flags.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC SSRU Flag to clear.
+  *         This parameter can be:
+  *            @arg @ref RTC_FLAG_SSRUF
+  * @retval None
+  */
+#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__)     (WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+  * @{
+  */
+
+/* RTC TimeStamp functions *****************************************/
+/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
+                                         RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+void              HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+
+/* RTC Wake-up functions ******************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock,
+                                              uint32_t WakeUpAutoClr);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t          HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Extended Control functions ************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
+                                           uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(const RTC_HandleTypeDef *hrtc, uint32_t Instance);
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *pValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc);
+
+/**
+  * @}
+  */
+
+/* Extended RTC features functions *******************************************/
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+  * @{
+  */
+
+void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(const RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(const RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc,
+                                              const RTC_InternalTamperTypeDef *sIntTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc,
+                                                 const RTC_InternalTamperTypeDef *sIntTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
+HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper,
+                                                       uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_LockBootHardwareKey(const RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper7EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_Tamper8EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
+  * @{
+  */
+void              HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t          HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+void              HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc);
+void              HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc);
+#ifdef TAMP_RPCFGR_RPCFG0
+void              HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf);
+#endif /* TAMP_RPCFGR_RPCFG0 */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Exported_Functions_Group7 Extended RTC secure functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(const RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef  *secureState);
+#if defined (CPU_IN_SECURE_STATE)
+HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(const RTC_HandleTypeDef *hrtc, const RTC_SecureStateTypeDef  *secureState);
+#endif /* defined (CPU_IN_SECURE_STATE) */
+/**
+  * @}
+  */
+
+/** @defgroup RTCEx_Exported_Functions_Group8 Extended RTC privilege functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(const RTC_HandleTypeDef *hrtc,
+                                             const RTC_PrivilegeStateTypeDef *privilegeState);
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+  * @{
+  */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+  * @{
+  */
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+#define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+
+#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+                                                       ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
+#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)    (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
+                                                      ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
+
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
+
+#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \
+                                       ((LPCAL) == RTC_LPCAL_RESET))
+
+
+#define IS_RTC_TAMPER(__TAMPER__)                ((((__TAMPER__) & RTC_TAMPER_ALL) != 0U) && \
+                                                  (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0U))
+
+#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)   ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0U) && \
+                                                  (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0U))
+
+#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__)       (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)  || \
+                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)    || \
+                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
+#define IS_RTC_TAMPER_ERASE_MODE(__MODE__)       (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
+                                                  ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
+
+#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)  (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
+                                                  ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
+
+#define IS_RTC_TAMPER_FILTER(__FILTER__)         (((__FILTER__) == RTC_TAMPERFILTER_DISABLE)  || \
+                                                  ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
+                                                  ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
+                                                  ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
+
+#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)    (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
+                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)   (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+
+#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__)    (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
+                                                  ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
+
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION)  \
+  (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+   ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
+#define IS_RTC_ATAMPER_FILTER(__FILTER__)                    (((__FILTER__) == RTC_ATAMP_FILTER_ENABLE) || \
+                                                              ((__FILTER__) == RTC_ATAMP_FILTER_DISABLE))
+
+#define IS_RTC_ATAMPER_OUTPUT_CHANGE_PERIOD(__PERIOD__)      ((__PERIOD__) <= 7U)
+
+#define IS_RTC_ATAMPER_ASYNCPRES_RTCCLK(__PRESCALER__)       (((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK)       || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_2)     || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_4)     || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_8)     || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_16)    || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_32)    || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_64)    || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_128)   || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_256)   || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_512)   || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_1024)  || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_2048)  || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_4096)  || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_8192)  || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_16384) || \
+                                                              ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_32768))
+
+
+#define IS_RTC_BKP(__BKP__)   ((__BKP__) < RTC_BKP_NUMBER)
+
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+                                 ((SEL) == RTC_SHIFTADD1S_SET))
+
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
+
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+
+#define IS_RTC_SECURE_FULL(__STATE__) (((__STATE__) == RTC_SECURE_FULL_YES) || \
+                                       ((__STATE__) == RTC_SECURE_FULL_NO))
+
+#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_ALL) == 0U)
+
+#define IS_TAMP_SECURE_FULL(__STATE__) (((__STATE__) == TAMP_SECURE_FULL_YES) || \
+                                        ((__STATE__) == TAMP_SECURE_FULL_NO))
+
+#define IS_TAMP_MONOTONIC_CNT_SECURE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_SECURE_YES) || \
+                                                 ((__STATE__) == TAMP_MONOTONIC_CNT_SECURE_NO))
+
+#define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \
+                                          ((__STATE__) == RTC_PRIVILEGE_FULL_NO))
+
+#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0U)
+
+#define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \
+                                           ((__STATE__) == TAMP_PRIVILEGE_FULL_NO))
+
+#define IS_TAMP_MONOTONIC_CNT_PRIVILEGE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_YES) || \
+                                                    ((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_NO))
+
+#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0U)
+
+#define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \
+                                  ((MODE) == RTC_BINARY_ONLY) || \
+                                  ((MODE) == RTC_BINARY_MIX ))
+
+#define IS_RTC_BINARY_MIX_BCDU(BDCU) (((BDCU) == RTC_BINARY_MIX_BCDU_0) || \
+                                      ((BDCU) == RTC_BINARY_MIX_BCDU_1) || \
+                                      ((BDCU) == RTC_BINARY_MIX_BCDU_2) || \
+                                      ((BDCU) == RTC_BINARY_MIX_BCDU_3) || \
+                                      ((BDCU) == RTC_BINARY_MIX_BCDU_4) || \
+                                      ((BDCU) == RTC_BINARY_MIX_BCDU_5) || \
+                                      ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \
+                                      ((BDCU) == RTC_BINARY_MIX_BCDU_7))
+
+#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK)   (((MASK) == 0U) || \
+                                                     (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) &&\
+                                                      ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE)))
+
+#define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \
+                                               ((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_YES))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_RTC_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sai.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sai.h
new file mode 100644
index 000000000..0ffdda9b0
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sai.h
@@ -0,0 +1,968 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sai.h
+  * @author  MCD Application Team
+  * @brief   Header file of SAI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SAI_H
+#define STM32N6xx_HAL_SAI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SAI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Types SAI Exported Types
+  * @{
+  */
+
+/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
+  * @brief  SAI PDM Init structure definition
+  * @{
+  */
+typedef struct
+{
+  FunctionalState  Activation;  /*!< Enable/disable PDM interface */
+  uint32_t         MicPairsNbr; /*!< Specifies the number of microphone pairs used.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
+  uint32_t         ClockEnable; /*!< Specifies which clock must be enabled.
+                                     This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
+} SAI_PdmInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
+  * @brief  SAI Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.
+                                     This parameter can be a value of @ref SAI_Block_Mode */
+
+  uint32_t Synchro;             /*!< Specifies SAI Block synchronization
+                                     This parameter can be a value of @ref SAI_Block_Synchronization */
+
+  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common
+                                     for BlockA and BlockB
+                                     This parameter can be a value of @ref SAI_Block_SyncExt
+                                     @note If both audio blocks of same SAI are used, this parameter has
+                                           to be set to the same value for each audio block */
+
+  uint32_t MckOutput;           /*!< Specifies whether master clock output will be generated or not.
+                                     This parameter can be a value of @ref SAI_Block_MckOutput */
+
+  uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.
+                                     This parameter can be a value of @ref SAI_Block_Output_Drive
+                                     @note This value has to be set before enabling the audio block
+                                           but after the audio block configuration. */
+
+  uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.
+                                     This parameter can be a value of @ref SAI_Block_NoDivider
+                                     @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
+                                           should be aligned to a number equal to a power of 2, from 8 to 256.
+                                           If bit NODIV in the SAI_xCR1 register is set, the frame length can
+                                           take any of the values from 8 to 256. */
+
+  uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.
+                                     This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
+
+  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
+                                     This parameter can be a value of @ref SAI_Audio_Frequency */
+
+  uint32_t Mckdiv;              /*!< Specifies the master clock divider.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 63.
+                                     @note This parameter is used only if AudioFrequency is set to
+                                           SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
+
+  uint32_t MckOverSampling;     /*!< Specifies the master clock oversampling.
+                                     This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
+
+  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.
+                                     This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
+
+  uint32_t CompandingMode;      /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_Block_Companding_Mode */
+
+  uint32_t TriState;            /*!< Specifies the companding mode type.
+                                     This parameter can be a value of @ref SAI_TRIState_Management */
+
+  SAI_PdmInitTypeDef PdmInit;   /*!< Specifies the PDM configuration. */
+
+  /* This part of the structure is automatically filled if your are using the high level initialisation
+     function HAL_SAI_InitProtocol */
+
+  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.
+                                 This parameter can be a value of @ref SAI_Block_Protocol */
+
+  uint32_t DataSize;        /*!< Specifies the SAI Block data size.
+                                 This parameter can be a value of @ref SAI_Block_Data_Size */
+
+  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
+
+  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.
+                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing */
+} SAI_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */
+  HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */
+  HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */
+  HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
+  HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */
+} HAL_SAI_StateTypeDef;
+
+/**
+  * @brief  SAI Callback prototype
+  */
+typedef void (*SAIcallback)(void);
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
+  * @brief  SAI Frame Init structure definition
+  * @note   For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
+                                    This parameter must be a number between Min_Data = 8 and Max_Data = 256.
+                                    @note If master clock MCLK_x pin is declared as an output, the frame length
+                                          should be aligned to a number equal to power of 2 in order to keep
+                                          in an audio frame, an integer number of MCLK pulses by bit Clock. */
+
+  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.
+                                    This Parameter specifies the length in number of bit clock (SCK + 1)
+                                    of the active level of FS signal in audio frame.
+                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
+
+  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.
+                                    This parameter can be a value of @ref SAI_Block_FS_Definition */
+
+  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.
+                                    This parameter can be a value of @ref SAI_Block_FS_Polarity */
+
+  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.
+                                    This parameter can be a value of @ref SAI_Block_FS_Offset */
+
+} SAI_FrameInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
+  * @brief   SAI Block Slot Init Structure definition
+  * @note    For SPDIF protocol, these parameters are not used (set by hardware).
+  * @note    For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
+  * @{
+  */
+typedef struct
+{
+  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
+
+  uint32_t SlotSize;        /*!< Specifies the Slot Size.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Size */
+
+  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+
+  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.
+                                 This parameter can be a value of @ref SAI_Block_Slot_Active */
+} SAI_SlotInitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
+  * @brief  SAI handle Structure definition
+  * @{
+  */
+typedef struct __SAI_HandleTypeDef
+{
+  SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */
+
+  SAI_InitTypeDef           Init;         /*!< SAI communication parameters */
+
+  SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */
+
+  SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */
+
+  uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */
+
+  uint16_t                  XferSize;     /*!< SAI transfer size */
+
+  uint16_t                  XferCount;    /*!< SAI transfer counter */
+
+  DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */
+
+  DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */
+
+  SAIcallback               mutecallback; /*!< SAI mute callback */
+
+  void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
+
+  HAL_LockTypeDef           Lock;         /*!< SAI locking object */
+
+  __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */
+
+  __IO uint32_t             ErrorCode;    /*!< SAI Error code */
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI receive complete callback */
+  void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI receive half complete callback */
+  void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI transmit complete callback */
+  void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI transmit half complete callback */
+  void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai);       /*!< SAI error callback */
+  void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai);     /*!< SAI MSP init callback */
+  void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai);   /*!< SAI MSP de-init callback */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+} SAI_HandleTypeDef;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  SAI callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SAI_RX_COMPLETE_CB_ID     = 0x00U, /*!< SAI receive complete callback ID */
+  HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
+  HAL_SAI_TX_COMPLETE_CB_ID     = 0x02U, /*!< SAI transmit complete callback ID */
+  HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
+  HAL_SAI_ERROR_CB_ID           = 0x04U, /*!< SAI error callback ID */
+  HAL_SAI_MSPINIT_CB_ID         = 0x05U, /*!< SAI MSP init callback ID */
+  HAL_SAI_MSPDEINIT_CB_ID       = 0x06U  /*!< SAI MSP de-init callback ID */
+} HAL_SAI_CallbackIDTypeDef;
+
+/**
+  * @brief  SAI callback pointer definition
+  */
+typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SAI_Exported_Constants SAI Exported Constants
+  * @{
+  */
+
+/** @defgroup SAI_Error_Code SAI Error Code
+  * @{
+  */
+#define HAL_SAI_ERROR_NONE             0x00000000U  /*!< No error */
+#define HAL_SAI_ERROR_OVR              0x00000001U  /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR              0x00000002U  /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET           0x00000004U  /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET           0x00000008U  /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY          0x00000010U  /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG           0x00000020U  /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT          0x00000040U  /*!< Timeout error */
+#define HAL_SAI_ERROR_DMA              0x00000080U  /*!< DMA error */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U  /*!< Invalid callback error */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
+  * @{
+  */
+#define SAI_SYNCEXT_DISABLE          0U
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
+  * @{
+  */
+#define SAI_MCK_OUTPUT_DISABLE      0x00000000U
+#define SAI_MCK_OUTPUT_ENABLE       SAI_xCR1_MCKEN
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol SAI Supported protocol
+  * @{
+  */
+#define SAI_I2S_STANDARD      0U
+#define SAI_I2S_MSBJUSTIFIED  1U
+#define SAI_I2S_LSBJUSTIFIED  2U
+#define SAI_PCM_LONG          3U
+#define SAI_PCM_SHORT         4U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Protocol_DataSize SAI protocol data size
+  * @{
+  */
+#define SAI_PROTOCOL_DATASIZE_16BIT         0U
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
+#define SAI_PROTOCOL_DATASIZE_24BIT         2U
+#define SAI_PROTOCOL_DATASIZE_32BIT         3U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
+  * @{
+  */
+#define SAI_AUDIO_FREQUENCY_192K          192000U
+#define SAI_AUDIO_FREQUENCY_96K           96000U
+#define SAI_AUDIO_FREQUENCY_48K           48000U
+#define SAI_AUDIO_FREQUENCY_44K           44100U
+#define SAI_AUDIO_FREQUENCY_32K           32000U
+#define SAI_AUDIO_FREQUENCY_22K           22050U
+#define SAI_AUDIO_FREQUENCY_16K           16000U
+#define SAI_AUDIO_FREQUENCY_11K           11025U
+#define SAI_AUDIO_FREQUENCY_8K            8000U
+#define SAI_AUDIO_FREQUENCY_MCKDIV        0U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
+  * @{
+  */
+#define SAI_MCK_OVERSAMPLING_DISABLE      0x00000000U
+#define SAI_MCK_OVERSAMPLING_ENABLE       SAI_xCR1_OSR
+/**
+  * @}
+  */
+
+/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
+  * @{
+  */
+#define SAI_PDM_CLOCK1_ENABLE     SAI_PDMCR_CKEN1
+#define SAI_PDM_CLOCK2_ENABLE     SAI_PDMCR_CKEN2
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mode SAI Block Mode
+  * @{
+  */
+#define SAI_MODEMASTER_TX         0x00000000U
+#define SAI_MODEMASTER_RX         SAI_xCR1_MODE_0
+#define SAI_MODESLAVE_TX          SAI_xCR1_MODE_1
+#define SAI_MODESLAVE_RX          (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Protocol SAI Block Protocol
+  * @{
+  */
+#define SAI_FREE_PROTOCOL                 0x00000000U
+#define SAI_SPDIF_PROTOCOL                SAI_xCR1_PRTCFG_0
+#define SAI_AC97_PROTOCOL                 SAI_xCR1_PRTCFG_1
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Data_Size SAI Block Data Size
+  * @{
+  */
+#define SAI_DATASIZE_8     SAI_xCR1_DS_1
+#define SAI_DATASIZE_10    (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_16    SAI_xCR1_DS_2
+#define SAI_DATASIZE_20    (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_24    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
+#define SAI_DATASIZE_32    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
+  * @{
+  */
+#define SAI_FIRSTBIT_MSB                  0x00000000U
+#define SAI_FIRSTBIT_LSB                  SAI_xCR1_LSBFIRST
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
+  * @{
+  */
+#define SAI_CLOCKSTROBING_FALLINGEDGE     0U
+#define SAI_CLOCKSTROBING_RISINGEDGE      1U
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
+  * @{
+  */
+#define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous */
+#define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2 */
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLE          0x00000000U
+#define SAI_OUTPUTDRIVE_ENABLE           SAI_xCR1_OUTDRIV
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
+  * @{
+  */
+#define SAI_MASTERDIVIDER_ENABLE         0x00000000U
+#define SAI_MASTERDIVIDER_DISABLE        SAI_xCR1_NODIV
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
+  * @{
+  */
+#define SAI_FS_STARTFRAME                 0x00000000U
+#define SAI_FS_CHANNEL_IDENTIFICATION     SAI_xFRCR_FSDEF
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
+  * @{
+  */
+#define SAI_FS_ACTIVE_LOW                  0x00000000U
+#define SAI_FS_ACTIVE_HIGH                 SAI_xFRCR_FSPOL
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
+  * @{
+  */
+#define SAI_FS_FIRSTBIT                   0x00000000U
+#define SAI_FS_BEFOREFIRSTBIT             SAI_xFRCR_FSOFF
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
+  * @{
+  */
+#define SAI_SLOTSIZE_DATASIZE             0x00000000U
+#define SAI_SLOTSIZE_16B                  SAI_xSLOTR_SLOTSZ_0
+#define SAI_SLOTSIZE_32B                  SAI_xSLOTR_SLOTSZ_1
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
+  * @{
+  */
+#define SAI_SLOT_NOTACTIVE           0x00000000U
+#define SAI_SLOTACTIVE_0             0x00000001U
+#define SAI_SLOTACTIVE_1             0x00000002U
+#define SAI_SLOTACTIVE_2             0x00000004U
+#define SAI_SLOTACTIVE_3             0x00000008U
+#define SAI_SLOTACTIVE_4             0x00000010U
+#define SAI_SLOTACTIVE_5             0x00000020U
+#define SAI_SLOTACTIVE_6             0x00000040U
+#define SAI_SLOTACTIVE_7             0x00000080U
+#define SAI_SLOTACTIVE_8             0x00000100U
+#define SAI_SLOTACTIVE_9             0x00000200U
+#define SAI_SLOTACTIVE_10            0x00000400U
+#define SAI_SLOTACTIVE_11            0x00000800U
+#define SAI_SLOTACTIVE_12            0x00001000U
+#define SAI_SLOTACTIVE_13            0x00002000U
+#define SAI_SLOTACTIVE_14            0x00004000U
+#define SAI_SLOTACTIVE_15            0x00008000U
+#define SAI_SLOTACTIVE_ALL           0x0000FFFFU
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
+  * @{
+  */
+#define SAI_STEREOMODE               0x00000000U
+#define SAI_MONOMODE                 SAI_xCR1_MONO
+/**
+  * @}
+  */
+
+/** @defgroup SAI_TRIState_Management SAI TRIState Management
+  * @{
+  */
+#define SAI_OUTPUT_NOTRELEASED    0x00000000U
+#define SAI_OUTPUT_RELEASED       SAI_xCR2_TRIS
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
+  * @{
+  */
+#define SAI_FIFOTHRESHOLD_EMPTY  0x00000000U
+#define SAI_FIFOTHRESHOLD_1QF    SAI_xCR2_FTH_0
+#define SAI_FIFOTHRESHOLD_HF     SAI_xCR2_FTH_1
+#define SAI_FIFOTHRESHOLD_3QF    (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
+#define SAI_FIFOTHRESHOLD_FULL   SAI_xCR2_FTH_2
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
+  * @{
+  */
+#define SAI_NOCOMPANDING                 0x00000000U
+#define SAI_ULAW_1CPL_COMPANDING         SAI_xCR2_COMP_1
+#define SAI_ALAW_1CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
+#define SAI_ULAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
+#define SAI_ALAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
+  * @{
+  */
+#define SAI_ZERO_VALUE                     0x00000000U
+#define SAI_LAST_SENT_VALUE                SAI_xCR2_MUTEVAL
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
+  * @{
+  */
+#define SAI_IT_OVRUDR                     SAI_xIMR_OVRUDRIE
+#define SAI_IT_MUTEDET                    SAI_xIMR_MUTEDETIE
+#define SAI_IT_WCKCFG                     SAI_xIMR_WCKCFGIE
+#define SAI_IT_FREQ                       SAI_xIMR_FREQIE
+#define SAI_IT_CNRDY                      SAI_xIMR_CNRDYIE
+#define SAI_IT_AFSDET                     SAI_xIMR_AFSDETIE
+#define SAI_IT_LFSDET                     SAI_xIMR_LFSDETIE
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
+  * @{
+  */
+#define SAI_FLAG_OVRUDR                   SAI_xSR_OVRUDR
+#define SAI_FLAG_MUTEDET                  SAI_xSR_MUTEDET
+#define SAI_FLAG_WCKCFG                   SAI_xSR_WCKCFG
+#define SAI_FLAG_FREQ                     SAI_xSR_FREQ
+#define SAI_FLAG_CNRDY                    SAI_xSR_CNRDY
+#define SAI_FLAG_AFSDET                   SAI_xSR_AFSDET
+#define SAI_FLAG_LFSDET                   SAI_xSR_LFSDET
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
+  * @{
+  */
+#define SAI_FIFOSTATUS_EMPTY              0x00000000U
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL   0x00010000U
+#define SAI_FIFOSTATUS_1QUARTERFULL       0x00020000U
+#define SAI_FIFOSTATUS_HALFFULL           0x00030000U
+#define SAI_FIFOSTATUS_3QUARTERFULL       0x00040000U
+#define SAI_FIFOSTATUS_FULL               0x00050000U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SAI_Exported_Macros SAI Exported Macros
+  * @brief macros to handle interrupts and specific configurations
+  * @{
+  */
+
+/** @brief Reset SAI handle state.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @retval None
+  */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
+                                                     (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
+                                                     (__HANDLE__)->MspInitCallback = NULL;      \
+                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                   } while(0)
+#else
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified SAI interrupts.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval None
+  */
+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+
+/** @brief  Disable the specified SAI interrupts.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval None
+  */
+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SAI interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __INTERRUPT__ specifies the SAI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable
+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable
+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable
+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & \
+                                                              (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SAI flag is set or not.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
+  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.
+  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
+  *            @arg SAI_FLAG_FREQ: FIFO request flag.
+  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.
+  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
+  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified SAI pending flag.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
+  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection
+  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
+  *            @arg SAI_FLAG_FREQ: Clear FIFO request
+  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready
+  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
+  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
+  *
+  * @retval None
+  */
+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
+
+/** @brief  Enable SAI.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @retval None
+  */
+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)
+
+/** @brief  Disable SAI.
+  * @param  __HANDLE__ specifies the SAI Handle.
+  * @retval None
+  */
+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)
+
+/**
+  * @}
+  */
+
+/* Include SAI HAL Extension module */
+#include "stm32n6xx_hal_sai_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAI_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup SAI_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/* SAI callbacks register/unregister functions ********************************/
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
+                                           HAL_SAI_CallbackIDTypeDef CallbackID,
+                                           pSAI_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
+                                             HAL_SAI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/** @addtogroup SAI_Exported_Functions_Group2
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
+
+/* Abort function */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
+
+/* Mute management */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
+
+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/** @addtogroup SAI_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SAI_Private_Macros SAI Private Macros
+  * @{
+  */
+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
+
+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\
+                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
+                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\
+                                               ((PROTOCOL) == SAI_PCM_SHORT))
+
+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\
+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
+
+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_96K)  || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_44K)  || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_22K)  || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_11K)  || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || \
+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
+
+#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
+                                              ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
+
+#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 3U))
+
+#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
+                                        (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
+
+#define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \
+                                  ((MODE) == SAI_MODEMASTER_RX) || \
+                                  ((MODE) == SAI_MODESLAVE_TX)  || \
+                                  ((MODE) == SAI_MODESLAVE_RX))
+
+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \
+                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))
+
+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \
+                                         ((DATASIZE) == SAI_DATASIZE_10) || \
+                                         ((DATASIZE) == SAI_DATASIZE_16) || \
+                                         ((DATASIZE) == SAI_DATASIZE_20) || \
+                                         ((DATASIZE) == SAI_DATASIZE_24) || \
+                                         ((DATASIZE) == SAI_DATASIZE_32))
+
+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
+                                     ((BIT) == SAI_FIRSTBIT_LSB))
+
+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
+                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
+
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+
+#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
+                                        ((VALUE) == SAI_MCK_OUTPUT_DISABLE))
+
+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
+                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
+
+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
+                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
+
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
+
+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
+                                           ((VALUE) == SAI_LAST_SENT_VALUE))
+
+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \
+                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
+                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))
+
+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \
+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
+
+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
+                                                 ((STATE) == SAI_OUTPUT_RELEASED))
+
+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
+                                       ((MODE) == SAI_STEREOMODE))
+
+#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
+
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
+
+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
+                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \
+                                      ((SIZE) == SAI_SLOTSIZE_32B))
+
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
+
+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
+                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
+
+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
+                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))
+
+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
+                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
+
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
+
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
+
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SAI_Private_Functions SAI Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SAI_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sai_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sai_ex.h
new file mode 100644
index 000000000..50ca488e3
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sai_ex.h
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sai_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SAI HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SAI_EX_H
+#define STM32N6xx_HAL_SAI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SAIEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Types SAIEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PDM microphone delay structure definition
+  */
+typedef struct
+{
+  uint32_t MicPair;     /*!< Specifies which pair of microphones is selected.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
+
+  uint32_t LeftDelay;   /*!< Specifies the delay in PDM clock unit to apply on left microphone.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
+
+  uint32_t RightDelay;  /*!< Specifies the delay in PDM clock unit to apply on right microphone.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
+} SAIEx_PdmMicDelayParamTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai,
+                                              const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
+  * @{
+  */
+#define IS_SAI_PDM_MIC_DELAY(VALUE)   ((VALUE) <= 7U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SAI_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sd.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sd.h
new file mode 100644
index 000000000..06d052557
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sd.h
@@ -0,0 +1,798 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sd.h
+  * @author  MCD Application Team
+  * @brief   Header file of SD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SD_H
+#define STM32N6xx_HAL_SD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_sdmmc.h"
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3)
+#include "stm32n6xx_ll_dlyb.h"
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+
+/** @defgroup SD SD
+  * @brief SD HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SD_Exported_Types SD Exported Types
+  * @{
+  */
+
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+  * @{
+  */
+typedef enum
+{
+  HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */
+  HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */
+  HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */
+  HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */
+  HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */
+  HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receiving State                  */
+  HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfer State                   */
+  HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */
+} HAL_SD_StateTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+  * @{
+  */
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
+#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
+#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
+#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
+#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
+#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
+#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
+  * @{
+  */
+#define SD_InitTypeDef      SDMMC_InitTypeDef
+#define SD_TypeDef          SDMMC_TypeDef
+
+/**
+  * @brief  SD Card Information Structure definition
+  */
+typedef struct
+{
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
+
+  uint32_t CardVersion;                  /*!< Specifies the card version                      */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
+
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
+
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+  uint32_t CardSpeed;                    /*!< Specifies the card Speed                        */
+
+} HAL_SD_CardInfoTypeDef;
+
+/**
+  * @brief  SD handle Structure definition
+  */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+{
+  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
+
+  SD_InitTypeDef               Init;             /*!< SD required parameters              */
+
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
+
+  const uint8_t                *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
+
+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
+
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
+
+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
+
+  __IO uint32_t                Context;          /*!< SD transfer context                 */
+
+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
+
+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */
+
+  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
+
+  uint32_t                     CSD[4];           /*!< SD card specific data table         */
+
+  uint32_t                     CID[4];           /*!< SD card identification number table */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* Read_DMALnkLstBufCpltCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* Write_DMALnkLstBufCpltCallback)(struct __SD_HandleTypeDef *hsd);
+#if (USE_SD_TRANSCEIVER != 0U)
+  void (* DriveTransceiver_1_8V_Callback)(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+
+  void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd);
+  void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+} SD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+} HAL_SD_CardCSDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+} HAL_SD_CardCIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t CardType;               /*!< Carries information about card type                        */
+  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
+  __IO uint8_t  UhsSpeedGrade;          /*!< Carries information about the speed grade of UHS card      */
+  __IO uint8_t  UhsAllocationUnitSize;  /*!< Carries information about the UHS card's allocation unit size  */
+  __IO uint8_t  VideoSpeedClass;        /*!< Carries information about the Video Speed Class of UHS card    */
+} HAL_SD_CardStatusTypeDef;
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
+  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
+  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
+  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
+  HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID  = 0x04U,  /*!< SD DMA Rx Linked List Node buffer Callback ID */
+  HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID = 0x05U,  /*!< SD DMA Tx Linked List Node buffer Callback ID */
+
+  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
+  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
+} HAL_SD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
+  * @{
+  */
+typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd);
+#if (USE_SD_TRANSCEIVER != 0U)
+typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+/**
+  * @}
+  */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants SD Exported Constants
+  * @{
+  */
+
+#define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
+  * @{
+  */
+#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                        /*!< No error                                                     */
+#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL                /*!< Command response received (but CRC check failed)             */
+#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL               /*!< Data block sent/received (CRC check failed)                  */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT             /*!< Command response timeout                                     */
+#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT                /*!< Data timeout                                                 */
+#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN                 /*!< Transmit FIFO underrun                                       */
+#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN                  /*!< Receive FIFO overrun                                         */
+#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED             /*!< Misaligned address                                           */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR               /*!< Transferred block length is not allowed for the card or the  */
+/*!< number of transferred bytes does not match the block length  */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR               /*!< An error in the sequence of erase command occurs             */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM             /*!< An invalid selection for erase groups                        */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION        /*!< Attempt to program a write protect block                     */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED          /*!< Sequence or password error has been detected in unlock       */
+/*!< command or if there was an attempt to access a locked card   */
+#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED              /*!< CRC check of the previous command failed                     */
+#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD                 /*!< Command is not legal for the card state                      */
+#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED             /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                      /*!< Internal card controller error                               */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR         /*!< General or unknown error                                     */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN        /*!< The card could not sustain data reading in stream rmode      */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN        /*!< The card could not sustain data programming in stream mode   */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE           /*!< CID/CSD overwrite error                                      */
+#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP               /*!< Only partial address space was erased                        */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED           /*!< Command has been executed without using internal ECC         */
+#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET                 /*!< Erase sequence was cleared before executing because an out   */
+/*!< of erase sequence command was received                       */
+#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR                 /*!< Error in sequence of authentication                          */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE           /*!< Error in case of invalid voltage range                       */
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE           /*!< Error when addressed block is out of range                   */
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE      /*!< Error when command request is not applicable                 */
+#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER           /*!< the used parameter is not valid                              */
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE         /*!< Error when feature is not insupported                        */
+#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                        /*!< Error when transfer process is busy                          */
+#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                         /*!< Error while DMA transfer                                     */
+#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                     /*!< Timeout error                                                */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+  * @{
+  */
+#define   SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
+#define   SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
+#define   SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
+#define   SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
+#define   SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
+#define   SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
+#define   SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+  * @{
+  */
+#define CARD_NORMAL_SPEED        ((uint32_t)0x00000000U)    /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01    */
+#define CARD_HIGH_SPEED          ((uint32_t)0x00000100U)    /*!< High Speed Card <25Mo/s , Spec version 2.00        */
+#define CARD_ULTRA_HIGH_SPEED    ((uint32_t)0x00000200U)    /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
+                                                                 and <104Mo/s for SDR104, Spec version 3.01          */
+
+#define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */
+#define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
+#define CARD_SECURED               ((uint32_t)0x00000003U)
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+  * @{
+  */
+#define CARD_V1_X                  ((uint32_t)0x00000000U)
+#define CARD_V2_X                  ((uint32_t)0x00000001U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+/** @brief Reset SD handle state.
+  * @param  __HANDLE__ SD Handle.
+  * @retval None
+  */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the SD device interrupt.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SD device interrupt.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SD flag is set or not.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval The new state of SD FLAG (SET or RESET).
+  */
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SD's pending flags.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SD interrupt has occurred or not.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the SD's interrupt pending bits.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Include SD HAL Extension module */
+#include "stm32n6xx_hal_sd_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+  * @{
+  */
+
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd);
+void              HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void              HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+                                    uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                       uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks);
+
+void              HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void              HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void              HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void              HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void              HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/* Callback to switch in 1.8V mode */
+void              HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);
+#endif /* USE_SD_TRANSCEIVER */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+                                          pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);
+#endif /* USE_SD_TRANSCEIVER */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
+  * @{
+  */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd);
+uint32_t            HAL_SD_GetError(const SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_SD_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sd_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sd_ex.h
new file mode 100644
index 000000000..099cc3358
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sd_ex.h
@@ -0,0 +1,119 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sd_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SD HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SD_EX_H
+#define STM32N6xx_HAL_SD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+
+/** @addtogroup SDEx
+  * @brief SD HAL extended module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDEx_Exported_Types SDEx Exported Types
+  * @{
+  */
+
+/** @defgroup SDEx_Exported_Types_Group1 Linked List Wrapper
+  * @{
+  */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* -----------------Linked List Wrapper --------------------------------------*/
+
+#define SD_DMALinkNodeTypeDef        SDMMC_DMALinkNodeTypeDef
+#define SD_DMALinkNodeConfTypeDef    SDMMC_DMALinkNodeConfTypeDef
+#define SD_DMALinkedListTypeDef      SDMMC_DMALinkedListTypeDef
+/* ----------------- Linked Aliases ------------------------------------------*/
+#define HAL_SDEx_DMALinkedList_WriteCpltCallback HAL_SD_TxCpltCallback
+#define HAL_SDEx_DMALinkedList_ReadCpltCallback  HAL_SD_RxCpltCallback
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
+  * @{
+  */
+/** @defgroup SDEx_Exported_Functions_Group1 Linked List functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList,
+                                                    uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList,
+                                                     uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_InsertNode(SD_DMALinkedListTypeDef *pLinkedList,
+                                                    SD_DMALinkNodeTypeDef *pPrevNode, SD_DMALinkNodeTypeDef *pNewNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_RemoveNode(SD_DMALinkedListTypeDef *pLinkedList, SD_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_LockNode(SD_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_UnlockNode(SD_DMALinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_EnableCircularMode(SD_DMALinkedListTypeDef *pLinkedList);
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTypeDef *pLinkedList);
+
+void HAL_SDEx_Read_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* stm32n6xx_HAL_SD_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sdio.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sdio.h
new file mode 100644
index 000000000..384ea9804
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sdio.h
@@ -0,0 +1,606 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_sdio.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDIO HAL module.
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32N6xx_HAL_SDIO_H
+#define STM32N6xx_HAL_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_ll_sdmmc.h"
+
+/** @addtogroup STM32U5xx_HAL_Driver
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+
+/** @defgroup SDIO SDIO
+  * @brief SDIO HAL module driver
+  * @{
+  */
+
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_Types SDIO Exported Types
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Types_Group1 SDIO State enumeration structure
+  * @{
+
+  */
+typedef enum
+{
+  HAL_SDIO_STATE_RESET = 0x00U, /*!< SDIO not yet initialized or disabled */
+  HAL_SDIO_STATE_READY = 0x01U, /*!< SDIO initialized and ready for us    */
+  HAL_SDIO_STATE_BUSY  = 0x02U, /*!< SDIO process ongoing                 */
+} HAL_SDIO_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Types_Group2 SDIO Handle and Structure definition
+  * @{
+  */
+/**
+  * @brief  SDIO Card Common Control Register Structure definition
+  */
+typedef struct
+{
+  uint8_t sdio_revision;     /*!< SDIO revision                */
+  uint8_t cccr_revision;     /*!< CCCR version                 */
+  uint8_t sd_spec_revision;  /*!< SD revision                  */
+  uint8_t bus_width_8Bit;    /*!< SDIO bus width 8 bit support */
+  uint32_t card_capability;  /*!< SDIO card capability         */
+  uint32_t commonCISPointer; /*!< point to common CIS          */
+} HAL_SDIO_CCCR_TypeDef;
+
+/**
+  * @brief sdio card FBR register(Function Basic Register)
+  */
+typedef struct
+{
+  uint8_t flags;             /*!< SDIO current IO flags                  */
+  uint8_t ioStdFunctionCode; /*!< SDIO current IO standard function code */
+  uint8_t ioExtFunctionCode; /*!< SDIO current IO extended function code */
+  uint32_t ioPointerToCIS;   /*!< SDIO current IO pointer to CIS         */
+  uint32_t ioPointerToCSA;   /*!< SDIO current IO pointer to CSA         */
+} HAL_SDIO_FBR_t;
+
+/**
+  * @brief  SDIO CMD52 Structure definition
+  */
+typedef struct
+{
+  uint32_t Reg_Addr;       /*!< This is the address of the byte of data inside of the selected function to read or write */
+  uint8_t  ReadAfterWrite; /*!< This is the read after write flag, it is used for write access only.                     */
+  uint8_t  IOFunctionNbr;  /*!< The number of the function within the IO card you wish to read or write                  */
+} HAL_SDIO_DirectCmd_TypeDef;
+
+/**
+  * @brief  SDIO CMD53 Structure definition
+  */
+typedef struct
+{
+  uint32_t Reg_Addr;      /*!< This is the address of the byte of data inside of the selected function to read or write */
+  uint32_t OpCode;        /*!< Read/Write operation mode                                                                */
+  uint32_t Block_Mode;    /*!< Bytes or Blocks mode                                                                     */
+  uint32_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write                  */
+} HAL_SDIO_ExtendedCmd_TypeDef;
+
+#define SDIO_InitTypeDef      SDMMC_InitTypeDef
+#define SDIO_TypeDef          SDMMC_TypeDef
+
+/**
+  * @brief  SDIO handle Structure definition
+  */
+typedef struct __SDIO_HandleTypeDef
+{
+  SDIO_TypeDef                   *Instance;        /*!< SDIO registers base address                             */
+
+  SDIO_InitTypeDef               Init;              /*!< SDIO required parameters                               */
+
+  HAL_LockTypeDef                Lock;              /*!< SDIO locking object                                    */
+
+  uint8_t                        *pTxBuffPtr;       /*!< Pointer to SDIO Tx transfer Buffer                     */
+
+  uint32_t                       TxXferSize;        /*!< SDIO Tx Transfer size                                  */
+
+  uint8_t                        *pRxBuffPtr;       /*!< Pointer to SDIO Rx transfer Buffer                     */
+
+  uint32_t                       RxXferSize;        /*!< SDIO Rx Transfer size                                  */
+
+  uint32_t                       remaining_data;    /*!< Remaining data to transfer                             */
+
+  uint32_t                       next_data_addr;    /*!< SDIO Next data address                                 */
+
+  __IO uint32_t                  next_reg_addr;     /*!< SDIO Next register address                             */
+
+  uint16_t                       block_size;        /*!< SDIO Block size                                        */
+
+  __IO uint32_t                  Context;           /*!< SDIO transfer context                                  */
+
+  __IO HAL_SDIO_StateTypeDef     State;             /*!< SDIO card State                                        */
+
+  __IO uint32_t                  ErrorCode;         /*!< SDIO Card Error codes                                  */
+
+  uint8_t                        IOFunctionMask;    /*!< SDIO used to record current enabled io interrupt       */
+
+  volatile uint8_t               IOInterruptNbr;    /*!< SDIO used to record total enabled io interrupt numbers */
+
+  void (* SDIO_IOFunction_Callback[SDIO_MAX_IO_NUMBER])(struct __SDIO_HandleTypeDef *hsdio, uint32_t func);
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* RxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio);
+  void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+  void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+  HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio);
+
+} SDIO_HandleTypeDef;
+
+/**
+  * @}
+  */
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+/** @defgroup SDIO_Exported_Types_Group3 SDIO Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_SDIO_TX_CPLT_CB_ID    = 0x00U,  /*!< SDIO Tx Complete Callback ID */
+  HAL_SDIO_RX_CPLT_CB_ID    = 0x01U,  /*!< SDIO Rx Complete Callback ID */
+  HAL_SDIO_ERROR_CB_ID      = 0x02U,  /*!< SDIO Error Callback ID       */
+  HAL_SDIO_MSP_INIT_CB_ID   = 0x10U,  /*!< SDIO MspInit Callback ID     */
+  HAL_SDIO_MSP_DEINIT_CB_ID = 0x11U   /*!< SDIO MspDeInit Callback ID   */
+} HAL_SDIO_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Types_Group4 SDIO Callback pointer definition
+  * @{
+  */
+typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio);
+#if (USE_SDIO_TRANSCEIVER != 0U)
+typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio);
+typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func);
+/**
+  * @}
+  */
+
+/* Exported constants ------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_Constants SDIO Exported Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group1 SDIO Error status Structure definition
+  * @{
+  */
+#define HAL_SDIO_ERROR_NONE             SDMMC_ERROR_NONE              /*!< No error                                    */
+#define HAL_SDIO_ERROR_DATA_CRC_FAIL    SDMMC_ERROR_DATA_CRC_FAIL     /*!< Data block sent/received (CRC check failed) */
+#define HAL_SDIO_ERROR_DATA_TIMEOUT     SDMMC_ERROR_DATA_TIMEOUT      /*!< Data timeout                                */
+#define HAL_SDIO_ERROR_TX_UNDERRUN      SDMMC_ERROR_TX_UNDERRUN       /*!< Transmit FIFO underrun                      */
+#define HAL_SDIO_ERROR_RX_OVERRUN       SDMMC_ERROR_RX_OVERRUN        /*!< Receive FIFO overrun                        */
+#define HAL_SDIO_ERROR_TIMEOUT          SDMMC_ERROR_TIMEOUT           /*!< Timeout error                               */
+#define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error                      */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group2 SDIO context enumeration
+  * @{
+  */
+#define SDIO_CONTEXT_NONE                 0x00U /*!< None                             */
+#define SDIO_CONTEXT_READ_SINGLE_BLOCK    0x01U /*!< Read single block operation      */
+#define SDIO_CONTEXT_READ_MULTIPLE_BLOCK  0x02U /*!< Read multiple blocks operation   */
+#define SDIO_CONTEXT_WRITE_SINGLE_BLOCK   0x10U /*!< Write single block operation     */
+#define SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK 0x20U /*!< Write multiple blocks operation  */
+#define SDIO_CONTEXT_IT                   0x08U /*!< Process in Interrupt mode        */
+#define SDIO_CONTEXT_DMA                  0x80U /*!< Process in DMA mode              */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group3 SDIO Block mode enumeration
+  * @{
+  */
+#define HAL_SDIO_MODE_BYTE   SDMMC_SDIO_MODE_BYTE
+#define HAL_SDIO_MODE_BLOCK  SDMMC_SDIO_MODE_BLOCK
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group4 SDIO operation code enumeration
+  * @{
+  */
+#define HAL_SDIO_OP_CODE_NO_INC    SDMMC_SDIO_NO_INC
+#define HAL_SDIO_OP_CODE_AUTO_INC  SDMMC_SDIO_AUTO_INC
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group5 SDIO Read After Write(RAW) enumeration
+  * @{
+  */
+#define HAL_SDIO_WRITE_ONLY       SDMMC_SDIO_WO  /*!< SDIO Write only       */
+#define HAL_SDIO_READ_AFTER_WRITE SDMMC_SDIO_RAW /*!< SDIO Read after write */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group6 SDIO wire mode enumeration
+  * @{
+  */
+#define HAL_SDIO_1_WIRE_MODE   0U /*!< SDIO wire support 1 wire  */
+#define HAL_SDIO_4_WIRES_MODE  1U /*!< SDIO wire support 4 wires */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group7 SDIO Data block size enumeration
+  * @{
+  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_1BYTE     1U    /*!< SDIO data block size 1 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_2BYTE     2U    /*!< SDIO data block size 2 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_4BYTE     4U    /*!< SDIO data block size 4 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_8BYTE     8U    /*!< SDIO data block size 8 byte    */
+#define HAL_SDIO_DATA_BLOCK_SIZE_16BYTE    16U   /*!< SDIO data block size 16 byte   */
+#define HAL_SDIO_DATA_BLOCK_SIZE_32BYTE    32U   /*!< SDIO data block size 32 byte   */
+#define HAL_SDIO_DATA_BLOCK_SIZE_64BYTE    64U   /*!< SDIO data block size 64 byte   */
+#define HAL_SDIO_DATA_BLOCK_SIZE_128BYTE   128U  /*!< SDIO data block size 128 byte  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_256BYTE   256U  /*!< SDIO data block size 256 byte  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_512BYTE   512U  /*!< SDIO data block size 512 byte  */
+#define HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE  1024U /*!< SDIO data block size 1024 byte */
+#define HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE  2048U /*!< SDIO data block size 2048 byte */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration
+  * @{
+  */
+#define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */
+#define HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED     1U /*!< SDIO bus width 8 bit is supported     */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group9 SDIO Data rate definitions
+  * @{
+  */
+#define HAL_SDIOS_DATA_RATE_SDR12  0U /*!< SDIO Data rate SDR12 */
+#define HAL_SDIOS_DATA_RATE_SDR25  1U /*!< SDIO Data rate SDR25 */
+#define HAL_SDIOS_DATA_RATE_SDR50  2U /*!< SDIO Data rate SDR50 */
+#define HAL_SDIOS_DATA_RATE_DDR50  3U /*!< SDIO Data rate DDR50 */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group10 SDIO Functions definitions
+  * @{
+  */
+#define HAL_SDIO_FUNCTION_0  0U /*!< SDIO function 0 */
+#define HAL_SDIO_FUNCTION_1  1U /*!< SDIO function 1 */
+#define HAL_SDIO_FUNCTION_2  2U /*!< SDIO function 2 */
+#define HAL_SDIO_FUNCTION_3  3U /*!< SDIO function 3 */
+#define HAL_SDIO_FUNCTION_4  4U /*!< SDIO function 4 */
+#define HAL_SDIO_FUNCTION_5  5U /*!< SDIO function 5 */
+#define HAL_SDIO_FUNCTION_6  6U /*!< SDIO function 6 */
+#define HAL_SDIO_FUNCTION_7  7U /*!< SDIO function 7 */
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Constansts_Group11 SDIO FBR definitions
+  * @{
+  */
+#define HAL_SDIO_FBR_SUPPORT_CSA             1U /*!< SDIO function support CSA             */
+#define HAL_SDIO_FBR_SUPPORT_POWER_SELECTION 1U /*!< SDIO function support power selection */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_macros SDIO Exported Macros
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+/**
+  * @brief  Enable the SDIO device interrupt.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources.
+  * @retval None
+  */
+#define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDIO device interrupt.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources.
+  * @retval None
+  */
+#define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SDIO flag is set or not.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of @ref SDMMC_LL_Flags.
+  * @retval The new state of SDIO FLAG (SET or RESET).
+  */
+#define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SDIO's pending flags.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one or a combination of @ref SDMMC_LL_Flags.
+  * @retval None
+  */
+#define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SDIO interrupt has occurred or not.
+  * @param  __HANDLE__ SDIO Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of @ref SDMMC_LL_Interrupt_sources.
+  * @retval The new state of SDIO IT (SET or RESET).
+  */
+#define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt is enabled or not.
+  * @param  __HANDLE__    : SDIO handle.
+  * @param  __INTERRUPT__ : specifies the SDMMC interrupt source to check.
+  * @retval The state of SDIO IT (SET or RESET).
+  */
+#define __HAL_SDIO_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+  __SDMMC_GET_IT_SOURCE((__HANDLE__)->Instance, (__INTERRUPT__))
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Exported_Functions SDIO Exported Functions
+  * @{
+  */
+/** @defgroup SDIO_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio);
+HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio);
+
+void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide);
+HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed);
+
+HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize);
+HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate);
+
+HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio);
+HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr);
+HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group3 Process functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData);
+HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data);
+
+HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                        uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms);
+
+HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                         uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms);
+
+HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                            uint8_t *pData, uint32_t Size_byte);
+
+HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                             uint8_t *pData, uint32_t Size_byte);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group4 IRQHandler and callback functions
+  * @{
+  */
+void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio);
+
+void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio);
+void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func);
+#if (USE_SDIO_TRANSCEIVER != 0U)
+/* Callback to switch in 1.8V mode */
+void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID,
+                                            pSDIO_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio,
+                                                       pSDIO_TransceiverCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio);
+#endif /* USE_SDIO_TRANSCEIVER */
+
+HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction,
+                                                      HAL_SDIO_IOFunction_CallbackTypeDef pCallback);
+
+HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio,
+                                                        pSDIO_IdentifyCardCallbackTypeDef pCallback);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio);
+uint32_t              HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions_Group6 Peripheral IO interrupt
+  * @{
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+
+HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction);
+
+HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio);
+HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio);
+
+/**
+  * @}
+  */
+
+/* Private types -----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Types SDIO Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines ---------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Defines SDIO Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Variables SDIO Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Constants SDIO Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Macros SDIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes --------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Functions_Prototypes SDIO Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Functions SDIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_SDIO_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sdram.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sdram.h
new file mode 100644
index 000000000..6a3d88ee8
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sdram.h
@@ -0,0 +1,236 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sdram.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SDRAM_H
+#define STM32N6xx_HAL_SDRAM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_fmc.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SDRAM
+  * @{
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL SDRAM State structure definition
+  */
+typedef enum
+{
+  HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */
+  HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */
+  HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */
+  HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */
+  HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */
+  HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */
+
+} HAL_SDRAM_StateTypeDef;
+
+/**
+  * @brief  SDRAM handle Structure definition
+  */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SDRAM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS  */
+{
+  FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */
+
+  FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */
+
+  __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */
+
+  HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */
+
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                   */
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram);               /*!< SDRAM Msp Init callback              */
+  void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram);             /*!< SDRAM Msp DeInit callback            */
+  void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram);          /*!< SDRAM Refresh Error callback         */
+  void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                        /*!< SDRAM DMA Xfer Complete callback     */
+  void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                       /*!< SDRAM DMA Xfer Error callback        */
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+} SDRAM_HandleTypeDef;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SDRAM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SDRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SDRAM MspInit Callback ID           */
+  HAL_SDRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SDRAM MspDeInit Callback ID         */
+  HAL_SDRAM_REFRESH_ERR_CB_ID    = 0x02U,  /*!< SDRAM Refresh Error Callback ID     */
+  HAL_SDRAM_DMA_XFER_CPLT_CB_ID  = 0x03U,  /*!< SDRAM DMA Xfer Complete Callback ID */
+  HAL_SDRAM_DMA_XFER_ERR_CB_ID   = 0x04U   /*!< SDRAM DMA Xfer Error Callback ID    */
+} HAL_SDRAM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SDRAM Callback pointer definition
+  */
+typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
+typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
+  * @{
+  */
+
+/** @brief Reset SDRAM handle state
+  * @param  __HANDLE__ specifies the SDRAM handle.
+  * @retval None
+  */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__)        do {                                               \
+                                                               (__HANDLE__)->State = HAL_SDRAM_STATE_RESET;  \
+                                                               (__HANDLE__)->MspInitCallback = NULL;         \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;       \
+                                                             } while(0)
+#else
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
+  * @{
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization/de-initialization functions *********************************/
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
+
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
+void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                      uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize);
+
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize);
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/* SDRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                             pSDRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                                pSDRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group3
+  * @{
+  */
+/* SDRAM Control functions  *****************************************************/
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
+                                        uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
+uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDRAM_Exported_Functions_Group4
+  * @{
+  */
+/* SDRAM State functions ********************************************************/
+HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SDRAM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smartcard.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smartcard.h
new file mode 100644
index 000000000..98b87bbf6
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smartcard.h
@@ -0,0 +1,1163 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smartcard.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMARTCARD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SMARTCARD_H
+#define STM32N6xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+  * @{
+  */
+
+/**
+  * @brief SMARTCARD Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
+                                           where usart_ker_ckpres is the USART input clock divided by a prescaler */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter @ref SMARTCARD_Word_Length can only be
+                                           set to 9 (8 data + 1 parity bits). */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits.
+                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
+
+  uint16_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref SMARTCARD_Parity
+                                           @note The parity is enabled by default (PCE is forced to 1).
+                                                 Since the WordLength is forced to 8 bits + parity, M is
+                                                 forced to 1 and the parity bit is the 9th bit. */
+
+  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Mode */
+
+  uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+  uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+  uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+  uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote
+                                           is selected. Selecting the single sample method increases
+                                           the receiver tolerance to clock deviations. This parameter can be a value
+                                           of @ref SMARTCARD_OneBit_Sampling. */
+
+  uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.
+                                           This parameter can be any value from 0x01 to 0x1F. Prescaler value is
+                                           multiplied by 2 to give the division factor of the source clock frequency */
+
+  uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
+
+  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
+                                           in case of parity error.
+                                           This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+  uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
+                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+  uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
+                                           it is used to implement the Character Wait Time (CWT) and
+                                           Block Wait Time (BWT). It is coded over 24 bits. */
+
+  uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+                                           This parameter can be any value from 0x0 to 0xFF */
+
+  uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
+                                            receive and transmit mode). When set to 0, retransmission is
+                                            disabled. Otherwise, its maximum value is 7 (before signalling
+                                            an error) */
+
+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
+                                           This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
+
+} SMARTCARD_InitTypeDef;
+
+/**
+  * @brief  SMARTCARD advanced features initialization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
+                                           advanced features may be initialized at the same time. This parameter
+                                           can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
+
+  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
+
+  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
+
+  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
+                                           vs negative/inverted logic).
+                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
+                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
+                                           This parameter can be a value of @ref SMARTCARD_MSB_First */
+
+  uint16_t TxCompletionIndication;    /*!< Specifies which transmission completion indication is used: before (when
+                                           relevant flag is available) or once guard time period has elapsed.
+                                           This parameter can be a value
+                                           of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+} SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL SMARTCARD State definition
+  * @note  HAL SMARTCARD State value is a combination of 2 different substates:
+  *        gState and RxState (see @ref SMARTCARD_State_Definition).
+  *        - gState contains SMARTCARD state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_SMARTCARD_StateTypeDef;
+
+/**
+  * @brief  SMARTCARD handle Structure definition
+  */
+typedef struct __SMARTCARD_HandleTypeDef
+{
+  USART_TypeDef                     *Instance;             /*!< USART registers base address                          */
+
+  SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */
+
+  SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
+
+  const uint8_t                     *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
+
+  uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
+
+  __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */
+
+  uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */
+
+  uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */
+
+  __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */
+
+  uint16_t                          NbRxDataToProcess;     /*!< Number of data to process during RX ISR execution     */
+
+  uint16_t                          NbTxDataToProcess;     /*!< Number of data to process during TX ISR execution     */
+
+  uint32_t                          FifoMode;              /*!< Specifies if the FIFO mode will be used.
+                                                                This parameter can be a value of
+                                                                @ref SMARTCARDEx_FIFO_mode.                           */
+
+  void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */
+
+  void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */
+
+  DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+  HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */
+
+  __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global
+                                                                Handle management and also related to Tx operations.
+                                                                This parameter can be a value
+                                                                of @ref HAL_SMARTCARD_StateTypeDef                    */
+
+  __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.
+                                                                This parameter can be a value
+                                                                of @ref HAL_SMARTCARD_StateTypeDef                    */
+
+  __IO uint32_t                     ErrorCode;             /*!< SmartCard Error code                                  */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */
+
+  void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */
+
+  void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */
+
+  void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */
+
+  void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
+
+  void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */
+
+  void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);        /*!< SMARTCARD Rx Fifo Full Callback            */
+
+  void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);       /*!< SMARTCARD Tx Fifo Empty Callback           */
+
+  void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */
+
+  void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */
+#endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+} SMARTCARD_HandleTypeDef;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SMARTCARD Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
+  HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
+  HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
+  HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
+  HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
+  HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
+  HAL_SMARTCARD_RX_FIFO_FULL_CB_ID            = 0x06U,    /*!< SMARTCARD Rx Fifo Full Callback ID            */
+  HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID           = 0x07U,    /*!< SMARTCARD Tx Fifo Empty Callback ID           */
+
+  HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
+  HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
+
+} HAL_SMARTCARD_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SMARTCARD Callback pointer definition
+  */
+typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */
+
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
+  * @{
+  */
+
+/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
+  * @{
+  */
+#define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized. Value
+                                                                                  is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for
+                                                                                  use. Value is allowed for gState
+                                                                                  and RxState                       */
+#define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing
+                                                                                  Value is allowed for gState only  */
+#define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing
+                                                                                  Value is allowed for gState only  */
+#define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing
+                                                                                  Value is allowed for RxState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception
+                                                                                  process is ongoing Not to be used for
+                                                                                  neither gState nor RxState.
+                                                                                  Value is result of combination (Or)
+                                                                                  between gState and RxState values */
+#define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state
+                                                                                  Value is allowed for gState only  */
+#define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error
+                                                                                  Value is allowed for gState only  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
+  * @{
+  */
+#define HAL_SMARTCARD_ERROR_NONE             (0x00000000U)         /*!< No error                */
+#define HAL_SMARTCARD_ERROR_PE               (0x00000001U)         /*!< Parity error            */
+#define HAL_SMARTCARD_ERROR_NE               (0x00000002U)         /*!< Noise error             */
+#define HAL_SMARTCARD_ERROR_FE               (0x00000004U)         /*!< frame error             */
+#define HAL_SMARTCARD_ERROR_ORE              (0x00000008U)         /*!< Overrun error           */
+#if defined(HAL_DMA_MODULE_ENABLED)
+#define HAL_SMARTCARD_ERROR_DMA              (0x00000010U)         /*!< DMA transfer error      */
+#endif /* HAL_DMA_MODULE_ENABLED */
+#define HAL_SMARTCARD_ERROR_RTO              (0x00000020U)         /*!< Receiver TimeOut error  */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U)         /*!< Invalid Callback error  */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+  * @{
+  */
+#define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+  * @{
+  */
+#define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */
+#define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+  * @{
+  */
+#define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+  * @{
+  */
+#define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */
+#define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */
+#define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+  * @{
+  */
+#define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */
+#define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+  * @{
+  */
+#define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */
+#define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+  * @{
+  */
+#define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+  * @{
+  */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+  * @{
+  */
+#define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */
+#define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+  * @{
+  */
+#define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_ClockPrescaler  SMARTCARD Clock Prescaler
+  * @{
+  */
+#define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define SMARTCARD_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define SMARTCARD_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define SMARTCARD_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define SMARTCARD_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define SMARTCARD_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define SMARTCARD_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define SMARTCARD_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define SMARTCARD_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define SMARTCARD_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define SMARTCARD_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define SMARTCARD_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+  * @{
+  */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+  * @{
+  */
+#define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */
+#define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */
+#define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */
+#define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */
+#define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SMARTCARD handle states.
+  * @param  __HANDLE__ SMARTCARD handle.
+  * @retval None
+  */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
+                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
+                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
+                                                            (__HANDLE__)->MspInitCallback = NULL;                 \
+                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \
+                                                          } while(0U)
+#else
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
+                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
+                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
+                                                          } while(0U)
+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
+
+/** @brief  Flush the Smartcard Data registers.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \
+  do{                                                                     \
+    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+  } while(0U)
+
+/** @brief  Clear the specified SMARTCARD pending flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the SMARTCARD PE pending flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+/** @brief  Clear the SMARTCARD FE pending flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief  Clear the SMARTCARD NE pending flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief  Clear the SMARTCARD ORE pending flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief  Clear the SMARTCARD IDLE pending flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
+  *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
+  *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
+  *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
+  *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
+  *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
+  *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
+  *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
+  *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
+  *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
+  *            @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
+  *            @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
+  *            @arg @ref SMARTCARD_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref SMARTCARD_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref SMARTCARD_FLAG_RXFT  SMARTCARD RXFIFO threshold flag
+  *            @arg @ref SMARTCARD_FLAG_TXFT  SMARTCARD TXFIFO threshold flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified SmartCard interrupt.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before
+  *                                          guard time interrupt (when interruption available)
+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+                                                                  SMARTCARD_CR_POS) == 1U)?\
+                                                                ((__HANDLE__)->Instance->CR1 |= (1UL <<\
+                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
+                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+                                                                  SMARTCARD_CR_POS) == 2U)?\
+                                                                ((__HANDLE__)->Instance->CR2 |= (1UL <<\
+                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 |= (1UL <<\
+                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief  Disable the specified SmartCard interrupt.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard
+  *                                          time interrupt (when interruption available)
+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+                                                                  SMARTCARD_CR_POS) == 1U)?\
+                                                                ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+                                                                  SMARTCARD_CR_POS) == 2U)?\
+                                                                ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+                                                                    ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief  Check whether the specified SmartCard interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
+  *                                          interrupt (when interruption available)
+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
+                                                           (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
+                                                               & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
+                                                           ? SET : RESET)
+
+/** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time
+  *                                          interrupt (when interruption available)
+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+                                                                       SMARTCARD_CR_POS) == 0x01U)?\
+                                                                     (__HANDLE__)->Instance->CR1 : \
+                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+                                                                        SMARTCARD_CR_POS) == 0x02U)?\
+                                                                      (__HANDLE__)->Instance->CR2 : \
+                                                                      (__HANDLE__)->Instance->CR3)) &\
+                                                                    (0x01UL << (((uint16_t)(__INTERRUPT__))\
+                                                                                & SMARTCARD_IT_MASK)))  != 0U)\
+                                                                  ? SET : RESET)
+
+/** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific SMARTCARD request flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+  *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable the USART associated to the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable the USART associated to the SMARTCARD Handle
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+  * @{
+  */
+
+/** @brief  Report the SMARTCARD clock source.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+  */
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)      \
+  do {                                                            \
+    if((__HANDLE__)->Instance == USART1)                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART1;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART2)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART2;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART3)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART3;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART6)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART6;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART10)                    \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART10;        \
+    }                                                             \
+    else                                                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = 0U;                                     \
+    }                                                             \
+  } while(0U)
+
+
+/** @brief  Check the Baud rate range.
+  * @note   The maximum Baud Rate is derived from the maximum clock on N6 (100 MHz)
+  *         divided by the oversampling used on the SMARTCARD (i.e. 16).
+  * @param  __BAUDRATE__ Baud rate set by the configuration function.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6250001U)
+
+/** @brief  Check the block length range.
+  * @note   The maximum SMARTCARD block length is 0xFF.
+  * @param  __LENGTH__ block length.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/** @brief  Check the SMARTCARD autoretry counter value.
+  * @note   The maximum number of retransmissions is 0x7.
+  * @param  __COUNT__ number of retransmissions.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
+
+/** @brief Ensure that SMARTCARD frame length is valid.
+  * @param __LENGTH__ SMARTCARD frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
+  * @param __STOPBITS__ SMARTCARD frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/** @brief Ensure that SMARTCARD frame parity is valid.
+  * @param __PARITY__ SMARTCARD frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/** @brief Ensure that SMARTCARD communication mode is valid.
+  * @param __MODE__ SMARTCARD communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/** @brief Ensure that SMARTCARD frame polarity is valid.
+  * @param __CPOL__ SMARTCARD frame polarity.
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
+                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/** @brief Ensure that SMARTCARD frame phase is valid.
+  * @param __CPHA__ SMARTCARD frame phase.
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame sampling is valid.
+  * @param __ONEBIT__ SMARTCARD frame sampling.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
+  * @param __NACK__ SMARTCARD NACK transmission setting.
+  * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+  */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
+  * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/** @brief Ensure that SMARTCARD clock Prescaler is valid.
+  * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
+
+/** @brief Ensure that SMARTCARD advanced features initialization is valid.
+  * @param __INIT__ SMARTCARD advanced features initialization.
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
+                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
+                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
+                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+  * @param __TXINV__ SMARTCARD frame TX inversion setting.
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+  * @param __RXINV__ SMARTCARD frame RX inversion setting.
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
+  * @param __DATAINV__ SMARTCARD frame data inversion setting.
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+  * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/** @brief Ensure that SMARTCARD frame overrun setting is valid.
+  * @param __OVERRUN__ SMARTCARD frame overrun setting.
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+  * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
+  * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/** @brief Ensure that SMARTCARD request parameter is valid.
+  * @param __PARAM__ SMARTCARD request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @}
+  */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32n6xx_hal_smartcard_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+                                                 HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+                                                 pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+                                                   HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+#endif /* HAL_DMA_MODULE_ENABLED */
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
+  * @{
+  */
+
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t                   HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SMARTCARD_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smartcard_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smartcard_ex.h
new file mode 100644
index 000000000..959f86553
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smartcard_ex.h
@@ -0,0 +1,336 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smartcard_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMARTCARD HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SMARTCARD_EX_H
+#define STM32N6xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARDEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+  * @{
+  */
+#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
+  * @brief    SMARTCARD FIFO mode
+  * @{
+  */
+#define SMARTCARD_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
+#define SMARTCARD_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
+  * @brief    SMARTCARD TXFIFO level
+  * @{
+  */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_8    0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                        /*!< TXFIFO reaches 1/4 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                        /*!< TXFIFO reaches 1/2 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)  /*!< TXFIFO reaches 3/4 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                        /*!< TXFIFO reaches 7/8 of its depth */
+#define SMARTCARD_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)  /*!< TXFIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
+  * @brief    SMARTCARD RXFIFO level
+  * @{
+  */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_8   0x00000000U                                /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                        /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                        /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)  /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                        /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define SMARTCARD_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)  /*!< RXFIFO FIFO becomes full             */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */
+#define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */
+#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */
+#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */
+#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */
+#define SMARTCARD_FLAG_TXE            USART_ISR_TXE_TXFNF     /*!< SMARTCARD transmit data register empty     */
+#define SMARTCARD_FLAG_TXFNF          USART_ISR_TXE_TXFNF     /*!< SMARTCARD TXFIFO not full                  */
+#define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */
+#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE_RXFNE    /*!< SMARTCARD read data register not empty     */
+#define SMARTCARD_FLAG_RXFNE          USART_ISR_RXNE_RXFNE    /*!< SMARTCARD RXFIFO not empty                 */
+#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */
+#define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */
+#define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */
+#define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */
+#define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */
+#define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE          /*!< SMARTCARD TXFIFO Empty flag                */
+#define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF          /*!< SMARTCARD RXFIFO Full flag                 */
+#define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT          /*!< SMARTCARD RXFIFO threshold flag            */
+#define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT          /*!< SMARTCARD TXFIFO threshold flag            */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5 bits)
+  *           - XX  : Interrupt source register (2 bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5 bits)
+  * @{
+  */
+#define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */
+#define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TXFNF                  0x0727U           /*!< SMARTCARD TX FIFO not full interruption             */
+#define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */
+#define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_RXFNE                  0x0525U           /*!< SMARTCARD RXFIFO not empty interruption             */
+#define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */
+
+#define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */
+#define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */
+#define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */
+
+#define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */
+#define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */
+#define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */
+
+#define SMARTCARD_IT_RXFF                    0x183FU          /*!< SMARTCARD RXFIFO full interruption                  */
+#define SMARTCARD_IT_TXFE                    0x173EU          /*!< SMARTCARD TXFIFO empty interruption                 */
+#define SMARTCARD_IT_RXFT                    0x1A7CU          /*!< SMARTCARD RXFIFO threshold reached interruption     */
+#define SMARTCARD_IT_TXFT                    0x1B77U          /*!< SMARTCARD TXFIFO threshold reached interruption     */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+  * @{
+  */
+#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
+#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
+#define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF    /*!< SMARTCARD noise error detected clear flag  */
+#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
+#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
+#define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< TXFIFO empty Clear Flag                    */
+#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
+#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
+#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macros -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+  * @{
+  */
+
+/** @brief  Set the Transmission Completion flag
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
+  *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
+  *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
+  * @retval None
+  */
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
+  do {                                                                                                       \
+    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
+    {                                                                                                        \
+      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
+    }                                                                                                        \
+    else                                                                                                     \
+    {                                                                                                        \
+      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+    }                                                                                                        \
+  } while(0U)
+
+/** @brief  Return the transmission completion flag.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+  *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
+  *        reported.
+  * @retval Transmission completion flag
+  */
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)  \
+  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
+
+
+/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+  * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
+  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+  */
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
+                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))
+
+/** @brief Ensure that SMARTCARD FIFO mode is valid.
+  * @param __STATE__ SMARTCARD FIFO mode.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
+                                                ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
+
+/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
+
+/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Peripheral Control functions ***********************************************/
+void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SMARTCARD_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smbus.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smbus.h
new file mode 100644
index 000000000..5744112f3
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smbus.h
@@ -0,0 +1,787 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smbus.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMBUS HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SMBUS_H
+#define STM32N6xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMBUS
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+  * @{
+  */
+
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
+  * @brief  SMBUS Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
+                                        This parameter calculated by referring to SMBUS initialization section
+                                        in Reference manual */
+  uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
+                                        This parameter can be a value of @ref SMBUS_Analog_Filter */
+
+  uint32_t OwnAddress1;            /*!< Specifies the first device own address.
+                                        This parameter can be a 7-bit address. */
+
+  uint32_t AddressingMode;         /*!< Specifies addressing mode selected.
+                                        This parameter can be a value of @ref SMBUS_addressing_mode */
+
+  uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
+                                        This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+  uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
+                                        This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address
+                                        if dual addressing mode is selected
+                                        This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+  uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
+                                        This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+  uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
+                                        This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+  uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
+                                        This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+  uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
+                                        This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+  uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+                                        (Enable bits and different timeout values)
+                                        This parameter calculated by referring to SMBUS initialization section
+                                        in Reference manual */
+} SMBUS_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_definition HAL state definition
+  * @brief  HAL State definition
+  * @{
+  */
+#define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
+#define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
+#define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
+#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)  /*!< Address Listen Mode is ongoing                */
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+  * @brief  SMBUS Error Code definition
+  * @{
+  */
+#define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
+#define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
+#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
+#define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
+#define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
+#define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
+#define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
+#define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)  /*!< Invalid Callback error   */
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+#define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
+  * @brief  SMBUS handle Structure definition
+  * @{
+  */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+typedef struct __SMBUS_HandleTypeDef
+#else
+typedef struct
+#endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+{
+  I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
+
+  SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
+
+  uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
+
+  uint16_t                     XferSize;        /*!< SMBUS transfer size                */
+
+  __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
+
+  __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
+
+  __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
+
+  HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
+
+  __IO uint32_t                State;           /*!< SMBUS communication state          */
+
+  __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Listen Complete callback              */
+  void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Error callback                        */
+
+  void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+  /*!< SMBUS Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Msp DeInit callback                   */
+
+#endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+} SMBUS_HandleTypeDef;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SMBUS Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
+  HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
+  HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
+  HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
+  HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
+  HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
+
+  HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
+  HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
+
+} HAL_SMBUS_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SMBUS Callback pointer definition
+  */
+typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
+/*!< pointer to an SMBUS callback function */
+typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+                                            uint16_t AddrMatchCode);
+/*!< pointer to an SMBUS Address Match callback function */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+  * @{
+  */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+  * @{
+  */
+#define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
+#define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+  * @{
+  */
+#define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+  * @{
+  */
+
+#define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
+#define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
+  * @{
+  */
+
+#define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
+#define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
+#define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
+#define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
+#define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
+#define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
+#define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
+#define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+  * @{
+  */
+#define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
+#define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+  * @{
+  */
+#define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
+#define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+  * @{
+  */
+#define SMBUS_PEC_DISABLE                       (0x00000000U)
+#define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+  * @{
+  */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+  * @{
+  */
+
+#define  SMBUS_SOFTEND_MODE                     (0x00000000U)
+#define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
+#define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
+#define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+  * @{
+  */
+
+#define  SMBUS_NO_STARTSTOP                     (0x00000000U)
+#define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+  * @{
+  */
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
+#define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
+#define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
+#define  SMBUS_FIRST_FRAME_WITH_PEC             ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
+#define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
+#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
+#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+  * @brief SMBUS Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
+#define SMBUS_IT_TCI                            I2C_CR1_TCIE
+#define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI                            I2C_CR1_RXIE
+#define SMBUS_IT_TXI                            I2C_CR1_TXIE
+#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
+                                                 SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
+                                                 SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+  * @brief Flag definition
+  *        Elements values convention: 0xXXXXYYYY
+  *           - XXXXXXXX  : Flag mask
+  * @{
+  */
+
+#define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
+#define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
+#define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
+#define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
+#define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
+#define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
+#define  SMBUS_FLAG_TC                          I2C_ISR_TC
+#define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
+#define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
+#define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
+#define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
+#define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
+#define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
+#define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
+#define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
+#define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SMBUS handle state.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                               \
+                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
+                                                                 (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                 (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                               } while(0)
+#else
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified SMBUS interrupts.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __IT__ (SET or RESET).
+  */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+  ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SMBUS flag is set or not.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
+  *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
+  *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define SMBUS_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
+  (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+    ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+
+/** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
+  *            @arg @ref SMBUS_FLAG_BERR    Bus error
+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) == SMBUS_FLAG_TXE) ? \
+                                                       ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+                                                       ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Disable the specified SMBUS peripheral.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the SMBUS Handle.
+  * @retval None
+  */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+  * @{
+  */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+                                                         ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE)                  ((MODE) == SMBUS_ADDRESSINGMODE_7BIT)
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+                                                         ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
+                                                         ((MASK) == SMBUS_OA2_MASK07))
+
+#define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
+                                                         ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
+                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
+                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_TRANSFER_MODE(MODE)                 (((MODE) == SMBUS_RELOAD_MODE)                          || \
+                                                      ((MODE) == SMBUS_AUTOEND_MODE)                         || \
+                                                      ((MODE) == SMBUS_SOFTEND_MODE)                         || \
+                                                      ((MODE) == SMBUS_SENDPEC_MODE)                         || \
+                                                      ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
+                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
+                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
+                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
+                                                                  SMBUS_RELOAD_MODE )))
+
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
+                                                         ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
+                                                         ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
+                                                         ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)   (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
+                                                      ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
+                                                      ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
+                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
+                                                      ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
+                                                      ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
+                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
+                                                      ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
+                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__)                    ((__HANDLE__)->Instance->CR1 &= \
+                                                        (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
+                                                                               I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 &= \
+                                                        (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+                                                                               I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+                                                                               I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
+                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                       (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+                                                                      (~I2C_CR2_RD_WRN)) : \
+                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & \
+                                                                        (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
+                                                                       (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
+#define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+                                                          ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+/**
+  * @}
+  */
+
+/* Include SMBUS HAL Extended module */
+#include "stm32n6xx_hal_smbus_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+  * @{
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                             HAL_SMBUS_CallbackIDTypeDef CallbackID,
+                                             pSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                               HAL_SMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+                                                 pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+  * @{
+  */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+                                          uint32_t Timeout);
+/**
+  * @}
+  */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+  * @{
+  */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+                                              uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+                                              uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+                                             uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32n6xx_hal_smbus.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_SMBUS_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smbus_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smbus_ex.h
new file mode 100644
index 000000000..b60c73b81
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_smbus_ex.h
@@ -0,0 +1,133 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smbus_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMBUS HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SMBUS_EX_H
+#define STM32N6xx_HAL_SMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMBUSEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
+  * @{
+  */
+#define SMBUS_FASTMODEPLUS_ENABLE         0x00000000U           /*!< Enable Fast Mode Plus                        */
+#define SMBUS_FASTMODEPLUS_DISABLE        0x00000001U           /*!< Disable Fast Mode Plus                       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
+  * @{
+  */
+#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (SMBUS_FASTMODEPLUS_ENABLE))   || \
+                                           ((__CONFIG__) == (SMBUS_FASTMODEPLUS_DISABLE)))
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32n6xx_hal_smbus_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SMBUS_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spdifrx.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spdifrx.h
new file mode 100644
index 000000000..3cd05be48
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spdifrx.h
@@ -0,0 +1,622 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_spdifrx.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPDIFRX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SPDIFRX_H
+#define STM32N6xx_HAL_SPDIFRX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (SPDIFRX)
+
+/** @addtogroup SPDIFRX
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
+  * @{
+  */
+
+/**
+  * @brief SPDIFRX Init structure definition
+  */
+typedef struct
+{
+  uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.
+                                          This parameter can be a value of @ref SPDIFRX_Input_Selection */
+
+  uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.
+                                          This parameter can be a value of @ref SPDIFRX_Max_Retries */
+
+  uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.
+                                          This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
+
+  uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status
+                                          from channel A or B.
+                                          This parameter can be a value of @ref SPDIFRX_Channel_Selection */
+
+  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
+                                          This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
+                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+  uint32_t PreambleTypeMask;         /*!< Specifies whether The preamble type bits are copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+  uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_PE_Mask */
+  FunctionalState SymbolClockGen;     /*!< Enable/Disable the SPDIFRX Symbol Clock generation.
+                                           This parameter can be set to Enable or Disable */
+
+  FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.
+                                             This parameter can be set to Enable or Disable */
+} SPDIFRX_InitTypeDef;
+
+/**
+  * @brief SPDIFRX SetDataFormat structure definition
+  */
+typedef struct
+{
+  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
+                                          This parameter can be a value of @ref SPDIFRX_Data_Format */
+
+  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
+                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
+
+  uint32_t PreambleTypeMask;         /*!< Specifies whether The preamble type bits are copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_PT_Mask */
+
+  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+
+  uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_V_Mask */
+
+  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_PE_Mask */
+
+} SPDIFRX_SetDataFormatTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SPDIFRX_STATE_RESET      = 0x00U,  /*!< SPDIFRX not yet initialized or disabled                */
+  HAL_SPDIFRX_STATE_READY      = 0x01U,  /*!< SPDIFRX initialized and ready for use                  */
+  HAL_SPDIFRX_STATE_BUSY       = 0x02U,  /*!< SPDIFRX internal process is ongoing                    */
+  HAL_SPDIFRX_STATE_BUSY_RX    = 0x03U,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */
+  HAL_SPDIFRX_STATE_BUSY_CX    = 0x04U,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */
+  HAL_SPDIFRX_STATE_ERROR      = 0x07U   /*!< SPDIFRX error state                                    */
+} HAL_SPDIFRX_StateTypeDef;
+
+/**
+  * @brief SPDIFRX handle Structure definition
+  */
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+typedef struct __SPDIFRX_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+{
+  SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */
+
+  SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */
+
+  uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */
+
+  uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */
+
+  __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */
+
+  __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter
+                                              (This field is initialized at the
+                                               same value as transfer size at the
+                                               beginning of the transfer and
+                                               decremented when a sample is received.
+                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+  __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */
+
+  __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter
+                                              (This field is initialized at the
+                                               same value as transfer size at the
+                                               beginning of the transfer and
+                                               decremented when a sample is received.
+                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+  DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information
+                                              DMA handle parameters */
+
+  DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */
+
+  __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */
+
+  __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */
+
+  __IO uint32_t  ErrorCode;                /* SPDIFRX Error code */
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Data flow half completed
+                                                                             callback */
+  void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Data flow completed callback */
+  void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Control flow half completed
+                                                                             callback */
+  void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Control flow completed callback */
+  void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);        /*!< SPDIFRX error callback */
+  void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);     /*!< SPDIFRX Msp Init callback  */
+  void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Msp DeInit callback  */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+} SPDIFRX_HandleTypeDef;
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SPDIFRX Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SPDIFRX_RX_HALF_CB_ID   = 0x00U,    /*!< SPDIFRX Data flow half completed callback ID */
+  HAL_SPDIFRX_RX_CPLT_CB_ID   = 0x01U,    /*!< SPDIFRX Data flow completed callback */
+  HAL_SPDIFRX_CX_HALF_CB_ID   = 0x02U,    /*!< SPDIFRX Control flow half completed callback */
+  HAL_SPDIFRX_CX_CPLT_CB_ID   = 0x03U,    /*!< SPDIFRX Control flow completed callback */
+  HAL_SPDIFRX_ERROR_CB_ID     = 0x04U,    /*!< SPDIFRX error callback */
+  HAL_SPDIFRX_MSPINIT_CB_ID   = 0x05U,    /*!< SPDIFRX Msp Init callback ID     */
+  HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U     /*!< SPDIFRX Msp DeInit callback ID   */
+} HAL_SPDIFRX_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SPDIFRX Callback pointer definition
+  */
+typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif);  /*!< pointer to an SPDIFRX callback
+                                                                                function */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
+  * @{
+  */
+/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
+  * @{
+  */
+#define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */
+#define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */
+#define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */
+#define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004U)  /*!< Parity error       */
+#define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */
+#define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010U)  /*!< Unknown Error error */
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+#define  HAL_SPDIFRX_ERROR_INVALID_CALLBACK   ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
+  * @{
+  */
+#define SPDIFRX_INPUT_IN0   ((uint32_t)0x00000000U)
+#define SPDIFRX_INPUT_IN1   ((uint32_t)0x00010000U)
+#define SPDIFRX_INPUT_IN2   ((uint32_t)0x00020000U)
+#define SPDIFRX_INPUT_IN3   ((uint32_t)0x00030000U)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
+  * @{
+  */
+#define SPDIFRX_MAXRETRIES_NONE   ((uint32_t)0x00000000U)
+#define SPDIFRX_MAXRETRIES_3      ((uint32_t)0x00001000U)
+#define SPDIFRX_MAXRETRIES_15     ((uint32_t)0x00002000U)
+#define SPDIFRX_MAXRETRIES_63     ((uint32_t)0x00003000U)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
+  * @{
+  */
+#define SPDIFRX_WAITFORACTIVITY_OFF   ((uint32_t)0x00000000U)
+#define SPDIFRX_WAITFORACTIVITY_ON    ((uint32_t)SPDIFRX_CR_WFA)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
+  * @{
+  */
+#define SPDIFRX_PREAMBLETYPEMASK_OFF    ((uint32_t)0x00000000U)
+#define SPDIFRX_PREAMBLETYPEMASK_ON     ((uint32_t)SPDIFRX_CR_PTMSK)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask
+  * @{
+  */
+#define SPDIFRX_CHANNELSTATUS_OFF   ((uint32_t)0x00000000U)       /* The channel status and user bits are copied
+                                                                     into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON    ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied
+                                                                     into the SPDIF_DR, zeros are written instead*/
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
+  * @{
+  */
+#define SPDIFRX_VALIDITYMASK_OFF    ((uint32_t)0x00000000U)
+#define SPDIFRX_VALIDITYMASK_ON     ((uint32_t)SPDIFRX_CR_VMSK)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask
+  * @{
+  */
+#define SPDIFRX_PARITYERRORMASK_OFF   ((uint32_t)0x00000000U)
+#define SPDIFRX_PARITYERRORMASK_ON    ((uint32_t)SPDIFRX_CR_PMSK)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection
+  * @{
+  */
+#define SPDIFRX_CHANNEL_A   ((uint32_t)0x00000000U)
+#define SPDIFRX_CHANNEL_B   ((uint32_t)SPDIFRX_CR_CHSEL)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
+  * @{
+  */
+#define SPDIFRX_DATAFORMAT_LSB      ((uint32_t)0x00000000U)
+#define SPDIFRX_DATAFORMAT_MSB      ((uint32_t)0x00000010U)
+#define SPDIFRX_DATAFORMAT_32BITS   ((uint32_t)0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
+  * @{
+  */
+#define SPDIFRX_STEREOMODE_DISABLE    ((uint32_t)0x00000000U)
+#define SPDIFRX_STEREOMODE_ENABLE     ((uint32_t)SPDIFRX_CR_RXSTEO)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_State SPDIFRX State
+  * @{
+  */
+
+#define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFCU)
+#define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001U)
+#define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFRXEN)
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
+  * @{
+  */
+#define SPDIFRX_IT_RXNE       ((uint32_t)SPDIFRX_IMR_RXNEIE)
+#define SPDIFRX_IT_CSRNE      ((uint32_t)SPDIFRX_IMR_CSRNEIE)
+#define SPDIFRX_IT_PERRIE     ((uint32_t)SPDIFRX_IMR_PERRIE)
+#define SPDIFRX_IT_OVRIE      ((uint32_t)SPDIFRX_IMR_OVRIE)
+#define SPDIFRX_IT_SBLKIE     ((uint32_t)SPDIFRX_IMR_SBLKIE)
+#define SPDIFRX_IT_SYNCDIE    ((uint32_t)SPDIFRX_IMR_SYNCDIE)
+#define SPDIFRX_IT_IFEIE      ((uint32_t)SPDIFRX_IMR_IFEIE )
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
+  * @{
+  */
+#define SPDIFRX_FLAG_RXNE     ((uint32_t)SPDIFRX_SR_RXNE)
+#define SPDIFRX_FLAG_CSRNE    ((uint32_t)SPDIFRX_SR_CSRNE)
+#define SPDIFRX_FLAG_PERR     ((uint32_t)SPDIFRX_SR_PERR)
+#define SPDIFRX_FLAG_OVR      ((uint32_t)SPDIFRX_SR_OVR)
+#define SPDIFRX_FLAG_SBD      ((uint32_t)SPDIFRX_SR_SBD)
+#define SPDIFRX_FLAG_SYNCD    ((uint32_t)SPDIFRX_SR_SYNCD)
+#define SPDIFRX_FLAG_FERR     ((uint32_t)SPDIFRX_SR_FERR)
+#define SPDIFRX_FLAG_SERR     ((uint32_t)SPDIFRX_SR_SERR)
+#define SPDIFRX_FLAG_TERR     ((uint32_t)SPDIFRX_SR_TERR)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SPDIFRX handle state
+  * @param  __HANDLE__ SPDIFRX handle.
+  * @retval None
+  */
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                         (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
+                                                         (__HANDLE__)->MspInitCallback = NULL;\
+                                                         (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                       }while(0)
+#else
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+/** @brief  Disable the specified SPDIFRX peripheral (IDLE State).
+  * @param  __HANDLE__ specifies the SPDIFRX Handle.
+  * @retval None
+  */
+#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
+
+/** @brief  Enable the specified SPDIFRX peripheral (SYNC State).
+  * @param  __HANDLE__ specifies the SPDIFRX Handle.
+  * @retval None
+  */
+#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
+
+
+/** @brief  Enable the specified SPDIFRX peripheral (RCV State).
+  * @param  __HANDLE__ specifies the SPDIFRX Handle.
+  * @retval None
+  */
+#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
+
+
+/** @brief  Enable or disable the specified SPDIFRX interrupts.
+  * @param  __HANDLE__    specifies the SPDIFRX Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg SPDIFRX_IT_RXNE
+  *            @arg SPDIFRX_IT_CSRNE
+  *            @arg SPDIFRX_IT_PERRIE
+  *            @arg SPDIFRX_IT_OVRIE
+  *            @arg SPDIFRX_IT_SBLKIE
+  *            @arg SPDIFRX_IT_SYNCDIE
+  *            @arg SPDIFRX_IT_IFEIE
+  * @retval None
+  */
+#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\
+                                                             &= (uint16_t)(~(__INTERRUPT__)))
+
+/** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.
+  * @param  __HANDLE__    specifies the SPDIFRX Handle.
+  * @param  __INTERRUPT__ specifies the SPDIFRX interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SPDIFRX_IT_RXNE
+  *            @arg SPDIFRX_IT_CSRNE
+  *            @arg SPDIFRX_IT_PERRIE
+  *            @arg SPDIFRX_IT_OVRIE
+  *            @arg SPDIFRX_IT_SBLKIE
+  *            @arg SPDIFRX_IT_SYNCDIE
+  *            @arg SPDIFRX_IT_IFEIE
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
+                                                                  & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified SPDIFRX flag is set or not.
+  * @param  __HANDLE__  specifies the SPDIFRX Handle.
+  * @param  __FLAG__    specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg SPDIFRX_FLAG_RXNE
+  *            @arg SPDIFRX_FLAG_CSRNE
+  *            @arg SPDIFRX_FLAG_PERR
+  *            @arg SPDIFRX_FLAG_OVR
+  *            @arg SPDIFRX_FLAG_SBD
+  *            @arg SPDIFRX_FLAG_SYNCD
+  *            @arg SPDIFRX_FLAG_FERR
+  *            @arg SPDIFRX_FLAG_SERR
+  *            @arg SPDIFRX_FLAG_TERR
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
+                                                        & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
+  * @param  __HANDLE__    specifies the USART Handle.
+  * @param  __IT_CLEAR__  specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg SPDIFRX_FLAG_PERR
+  *            @arg SPDIFRX_FLAG_OVR
+  *            @arg SPDIFRX_SR_SBD
+  *            @arg SPDIFRX_SR_SYNCD
+  * @retval None
+  */
+#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPDIFRX_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
+                                               pSPDIFRX_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
+                                                 HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions  ***************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
+/**
+  * @}
+  */
+
+/** @addtogroup SPDIFRX_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control and State functions  ************************************/
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
+  * @{
+  */
+#define IS_SPDIFRX_INPUT_SELECT(INPUT)      (((INPUT) == SPDIFRX_INPUT_IN1) || \
+                                             ((INPUT) == SPDIFRX_INPUT_IN2)  || \
+                                             ((INPUT) == SPDIFRX_INPUT_IN3)  || \
+                                             ((INPUT) == SPDIFRX_INPUT_IN0))
+
+#define IS_SPDIFRX_MAX_RETRIES(RET)         (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
+                                             ((RET) == SPDIFRX_MAXRETRIES_3)     || \
+                                             ((RET) == SPDIFRX_MAXRETRIES_15)    || \
+                                             ((RET) == SPDIFRX_MAXRETRIES_63))
+
+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)   (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
+                                             ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+
+#define IS_PREAMBLE_TYPE_MASK(VAL)          (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
+                                             ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+
+#define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
+                                             ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+
+#define IS_PARITY_ERROR_MASK(VAL)           (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
+                                             ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+
+#define IS_SPDIFRX_CHANNEL(CHANNEL)         (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
+                                             ((CHANNEL) == SPDIFRX_CHANNEL_B))
+
+#define IS_SPDIFRX_DATA_FORMAT(FORMAT)      (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
+                                             ((FORMAT) == SPDIFRX_DATAFORMAT_MSB)  || \
+                                             ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+
+#define IS_STEREO_MODE(MODE)                (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
+                                             ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+
+#define IS_CHANNEL_STATUS_MASK(VAL)         (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
+                                             ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+
+#define IS_SYMBOL_CLOCK_GEN(VAL)            (((VAL) == ENABLE) || ((VAL) == DISABLE))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SPDIFRX */
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_SPDIFRX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spi.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spi.h
new file mode 100644
index 000000000..82b999948
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spi.h
@@ -0,0 +1,1131 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_spi.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SPI_H
+#define STM32N6xx_HAL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Mode;                              /*!< Specifies the SPI operating mode.
+                                                     This parameter can be a value of @ref SPI_Mode */
+
+  uint32_t Direction;                         /*!< Specifies the SPI bidirectional mode state.
+                                                     This parameter can be a value of @ref SPI_Direction */
+
+  uint32_t DataSize;                          /*!< Specifies the SPI data size.
+                                                     This parameter can be a value of @ref SPI_Data_Size */
+
+  uint32_t CLKPolarity;                       /*!< Specifies the serial clock steady state.
+                                                     This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint32_t CLKPhase;                          /*!< Specifies the clock active edge for the bit capture.
+                                                     This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint32_t NSS;                               /*!< Specifies whether the NSS signal is managed by
+                                                     hardware (NSS pin) or by software using the SSI bit.
+                                                     This parameter can be a value of
+                                                     @ref SPI_Slave_Select_Management */
+
+  uint32_t BaudRatePrescaler;                 /*!< Specifies the Baud Rate prescaler value which will be
+                                                     used to configure the transmit and receive SCK clock.
+                                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                                     @note The communication clock is derived from the master
+                                                     clock. The slave clock does not need to be set. */
+
+  uint32_t FirstBit;                          /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                                     This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
+
+  uint32_t TIMode;                            /*!< Specifies if the TI mode is enabled or not.
+                                                     This parameter can be a value of @ref SPI_TI_Mode */
+
+  uint32_t CRCCalculation;                    /*!< Specifies if the CRC calculation is enabled or not.
+                                                     This parameter can be a value of @ref SPI_CRC_Calculation */
+
+  uint32_t CRCPolynomial;                     /*!< Specifies the polynomial used for the CRC calculation.
+                                                     This parameter must be an odd number between
+                                                     Min_Data = 0 and Max_Data = 65535 */
+
+  uint32_t CRCLength;                         /*!< Specifies the CRC Length used for the CRC calculation.
+                                                     This parameter can be a value of @ref SPI_CRC_length */
+
+  uint32_t NSSPMode;                          /*!< Specifies whether the NSSP signal is enabled or not .
+                                                     This parameter can be a value of @ref SPI_NSSP_Mode
+                                                     This mode is activated by the SSOM bit in the SPIx_CR2 register
+                                                     and it takes effect only if the SPI interface is configured
+                                                     as Motorola SPI master (FRF=0). */
+
+  uint32_t NSSPolarity;                       /*!< Specifies which level of SS input/output external signal
+                                                     (present on SS pin) is considered as active one.
+                                                     This parameter can be a value of @ref SPI_NSS_Polarity */
+
+  uint32_t FifoThreshold;                     /*!< Specifies the FIFO threshold level.
+                                                     This parameter can be a value of @ref SPI_Fifo_Threshold */
+
+  uint32_t TxCRCInitializationPattern;        /*!< Specifies the transmitter CRC initialization Pattern used for
+                                                     the CRC calculation. This parameter can be a value of
+                                                     @ref SPI_CRC_Calculation_Initialization_Pattern */
+
+  uint32_t RxCRCInitializationPattern;        /*!< Specifies the receiver CRC initialization Pattern used for
+                                                     the CRC calculation. This parameter can be a value of
+                                                     @ref SPI_CRC_Calculation_Initialization_Pattern */
+
+  uint32_t MasterSSIdleness;                  /*!< Specifies an extra delay, expressed in number of SPI clock cycle
+                                                     periods, inserted additionally between active edge of SS
+                                                     and first data transaction start in master mode.
+                                                     This parameter can be a value of @ref SPI_Master_SS_Idleness */
+
+  uint32_t MasterInterDataIdleness;           /*!< Specifies minimum time delay (expressed in SPI clock cycles periods)
+                                                     inserted between two consecutive data frames in master mode.
+                                                     This parameter can be a value of
+                                                     @ref SPI_Master_InterData_Idleness */
+
+  uint32_t MasterReceiverAutoSusp;            /*!< Control continuous SPI transfer in master receiver mode
+                                                     and automatic management in order to avoid overrun condition.
+                                                     This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
+
+  uint32_t MasterKeepIOState;                 /*!< Control of Alternate function GPIOs state
+                                                     This parameter can be a value of @ref SPI_Master_Keep_IO_State */
+
+  uint32_t IOSwap;                            /*!< Invert MISO/MOSI alternate functions
+                                                     This parameter can be a value of @ref SPI_IO_Swap */
+
+  uint32_t ReadyMasterManagement;             /*!< Specifies if RDY Signal is managed internally or not.
+                                                     This parameter can be a value of @ref SPI_RDY_Master_Management */
+
+  uint32_t ReadyPolarity;                     /*!< Specifies which level of RDY Signal input (present on RDY pin)
+                                                     is considered as active one.
+                                                     This parameter can be a value of @ref SPI_RDY_Polarity */
+} SPI_InitTypeDef;
+
+/**
+  * @brief  HAL SPI State structure definition
+  */
+typedef enum
+{
+  HAL_SPI_STATE_RESET      = 0x00UL,    /*!< Peripheral not Initialized                         */
+  HAL_SPI_STATE_READY      = 0x01UL,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SPI_STATE_BUSY       = 0x02UL,    /*!< an internal process is ongoing                     */
+  HAL_SPI_STATE_BUSY_TX    = 0x03UL,    /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x04UL,    /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x05UL,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_SPI_STATE_ERROR      = 0x06UL,    /*!< SPI error state                                    */
+  HAL_SPI_STATE_ABORT      = 0x07UL     /*!< SPI abort is ongoing                               */
+} HAL_SPI_StateTypeDef;
+
+
+/**
+  * @brief  SPI handle Structure definition
+  */
+typedef struct __SPI_HandleTypeDef
+{
+  SPI_TypeDef                *Instance;                    /*!< SPI registers base address               */
+
+  SPI_InitTypeDef            Init;                         /*!< SPI communication parameters             */
+
+  const uint8_t              *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
+
+  uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size                     */
+
+  __IO uint16_t              TxXferCount;                  /*!< SPI Tx Transfer Counter                  */
+
+  uint8_t                    *pRxBuffPtr;                  /*!< Pointer to SPI Rx transfer Buffer        */
+
+  uint16_t                   RxXferSize;                   /*!< SPI Rx Transfer size                     */
+
+  __IO uint16_t              RxXferCount;                  /*!< SPI Rx Transfer Counter                  */
+
+  uint32_t                   CRCSize;                      /*!< SPI CRC size used for the transfer       */
+
+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Rx ISR               */
+
+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Tx ISR               */
+
+  DMA_HandleTypeDef          *hdmatx;                      /*!< SPI Tx DMA Handle parameters             */
+
+  DMA_HandleTypeDef          *hdmarx;                      /*!< SPI Rx DMA Handle parameters             */
+
+  HAL_LockTypeDef            Lock;                         /*!< Locking object                           */
+
+  __IO HAL_SPI_StateTypeDef  State;                        /*!< SPI communication state                  */
+
+  __IO uint32_t              ErrorCode;                    /*!< SPI Error code                           */
+
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI Tx Completed callback          */
+  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI Rx Completed callback          */
+  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);     /*!< SPI TxRx Completed callback        */
+  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);   /*!< SPI Tx Half Completed callback     */
+  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);   /*!< SPI Rx Half Completed callback     */
+  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback   */
+  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);        /*!< SPI Error callback                 */
+  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Abort callback                 */
+  void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi);      /*!< SPI Suspend callback               */
+  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);      /*!< SPI Msp Init callback              */
+  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Msp DeInit callback            */
+
+#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
+} SPI_HandleTypeDef;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+/**
+  * @brief  HAL SPI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00UL,    /*!< SPI Tx Completed callback ID         */
+  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01UL,    /*!< SPI Rx Completed callback ID         */
+  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02UL,    /*!< SPI TxRx Completed callback ID       */
+  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03UL,    /*!< SPI Tx Half Completed callback ID    */
+  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04UL,    /*!< SPI Rx Half Completed callback ID    */
+  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05UL,    /*!< SPI TxRx Half Completed callback ID  */
+  HAL_SPI_ERROR_CB_ID                   = 0x06UL,    /*!< SPI Error callback ID                */
+  HAL_SPI_ABORT_CB_ID                   = 0x07UL,    /*!< SPI Abort callback ID                */
+  HAL_SPI_SUSPEND_CB_ID                 = 0x08UL,    /*!< SPI Suspend callback ID              */
+  HAL_SPI_MSPINIT_CB_ID                 = 0x09UL,    /*!< SPI Msp Init callback ID             */
+  HAL_SPI_MSPDEINIT_CB_ID               = 0x0AUL     /*!< SPI Msp DeInit callback ID           */
+
+} HAL_SPI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SPI Callback pointer definition
+  */
+typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_FIFO_Type SPI FIFO Type
+  * @{
+  */
+#define SPI_LOWEND_FIFO_SIZE                          8UL
+#define SPI_HIGHEND_FIFO_SIZE                         16UL
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Error_Code SPI Error Codes
+  * @{
+  */
+#define HAL_SPI_ERROR_NONE                            (0x00000000UL)   /*!< No error                               */
+#define HAL_SPI_ERROR_MODF                            (0x00000001UL)   /*!< MODF error                             */
+#define HAL_SPI_ERROR_CRC                             (0x00000002UL)   /*!< CRC error                              */
+#define HAL_SPI_ERROR_OVR                             (0x00000004UL)   /*!< OVR error                              */
+#define HAL_SPI_ERROR_FRE                             (0x00000008UL)   /*!< FRE error                              */
+#define HAL_SPI_ERROR_DMA                             (0x00000010UL)   /*!< DMA transfer error                     */
+#define HAL_SPI_ERROR_FLAG                            (0x00000020UL)   /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag  */
+#define HAL_SPI_ERROR_ABORT                           (0x00000040UL)   /*!< Error during SPI Abort procedure       */
+#define HAL_SPI_ERROR_UDR                             (0x00000080UL)   /*!< Underrun error                         */
+#define HAL_SPI_ERROR_TIMEOUT                         (0x00000100UL)   /*!< Timeout error                          */
+#define HAL_SPI_ERROR_UNKNOW                          (0x00000200UL)   /*!< Unknown error                          */
+#define HAL_SPI_ERROR_NOT_SUPPORTED                   (0x00000400UL)   /*!< Requested operation not supported      */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+#define HAL_SPI_ERROR_INVALID_CALLBACK                (0x00001000UL)   /*!< Invalid Callback error                 */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Mode SPI Mode
+  * @{
+  */
+#define SPI_MODE_SLAVE                                (0x00000000UL)
+#define SPI_MODE_MASTER                               SPI_CFG2_MASTER
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+  * @{
+  */
+#define SPI_DIRECTION_2LINES                          (0x00000000UL)
+#define SPI_DIRECTION_2LINES_TXONLY                   SPI_CFG2_COMM_0
+#define SPI_DIRECTION_2LINES_RXONLY                   SPI_CFG2_COMM_1
+#define SPI_DIRECTION_1LINE                           SPI_CFG2_COMM
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+  * @{
+  */
+#define SPI_DATASIZE_4BIT                             (0x00000003UL)
+#define SPI_DATASIZE_5BIT                             (0x00000004UL)
+#define SPI_DATASIZE_6BIT                             (0x00000005UL)
+#define SPI_DATASIZE_7BIT                             (0x00000006UL)
+#define SPI_DATASIZE_8BIT                             (0x00000007UL)
+#define SPI_DATASIZE_9BIT                             (0x00000008UL)
+#define SPI_DATASIZE_10BIT                            (0x00000009UL)
+#define SPI_DATASIZE_11BIT                            (0x0000000AUL)
+#define SPI_DATASIZE_12BIT                            (0x0000000BUL)
+#define SPI_DATASIZE_13BIT                            (0x0000000CUL)
+#define SPI_DATASIZE_14BIT                            (0x0000000DUL)
+#define SPI_DATASIZE_15BIT                            (0x0000000EUL)
+#define SPI_DATASIZE_16BIT                            (0x0000000FUL)
+#define SPI_DATASIZE_17BIT                            (0x00000010UL)
+#define SPI_DATASIZE_18BIT                            (0x00000011UL)
+#define SPI_DATASIZE_19BIT                            (0x00000012UL)
+#define SPI_DATASIZE_20BIT                            (0x00000013UL)
+#define SPI_DATASIZE_21BIT                            (0x00000014UL)
+#define SPI_DATASIZE_22BIT                            (0x00000015UL)
+#define SPI_DATASIZE_23BIT                            (0x00000016UL)
+#define SPI_DATASIZE_24BIT                            (0x00000017UL)
+#define SPI_DATASIZE_25BIT                            (0x00000018UL)
+#define SPI_DATASIZE_26BIT                            (0x00000019UL)
+#define SPI_DATASIZE_27BIT                            (0x0000001AUL)
+#define SPI_DATASIZE_28BIT                            (0x0000001BUL)
+#define SPI_DATASIZE_29BIT                            (0x0000001CUL)
+#define SPI_DATASIZE_30BIT                            (0x0000001DUL)
+#define SPI_DATASIZE_31BIT                            (0x0000001EUL)
+#define SPI_DATASIZE_32BIT                            (0x0000001FUL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+  * @{
+  */
+#define SPI_POLARITY_LOW                              (0x00000000UL)
+#define SPI_POLARITY_HIGH                             SPI_CFG2_CPOL
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+  * @{
+  */
+#define SPI_PHASE_1EDGE                               (0x00000000UL)
+#define SPI_PHASE_2EDGE                               SPI_CFG2_CPHA
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
+  * @{
+  */
+#define SPI_NSS_SOFT                                  SPI_CFG2_SSM
+#define SPI_NSS_HARD_INPUT                            (0x00000000UL)
+#define SPI_NSS_HARD_OUTPUT                           SPI_CFG2_SSOE
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+  * @{
+  */
+#define SPI_NSS_PULSE_DISABLE                         (0x00000000UL)
+#define SPI_NSS_PULSE_ENABLE                          SPI_CFG2_SSOM
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+  * @{
+  */
+#define SPI_BAUDRATEPRESCALER_BYPASS                  (0x80000000UL)
+#define SPI_BAUDRATEPRESCALER_2                       (0x00000000UL)
+#define SPI_BAUDRATEPRESCALER_4                       (0x10000000UL)
+#define SPI_BAUDRATEPRESCALER_8                       (0x20000000UL)
+#define SPI_BAUDRATEPRESCALER_16                      (0x30000000UL)
+#define SPI_BAUDRATEPRESCALER_32                      (0x40000000UL)
+#define SPI_BAUDRATEPRESCALER_64                      (0x50000000UL)
+#define SPI_BAUDRATEPRESCALER_128                     (0x60000000UL)
+#define SPI_BAUDRATEPRESCALER_256                     (0x70000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
+  * @{
+  */
+#define SPI_FIRSTBIT_MSB                              (0x00000000UL)
+#define SPI_FIRSTBIT_LSB                              SPI_CFG2_LSBFRST
+/**
+  * @}
+  */
+
+/** @defgroup SPI_TI_Mode SPI TI Mode
+  * @{
+  */
+#define SPI_TIMODE_DISABLE                            (0x00000000UL)
+#define SPI_TIMODE_ENABLE                             SPI_CFG2_SP_0
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+  * @{
+  */
+#define SPI_CRCCALCULATION_DISABLE                    (0x00000000UL)
+#define SPI_CRCCALCULATION_ENABLE                     SPI_CFG1_CRCEN
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+  * @{
+  */
+#define SPI_CRC_LENGTH_DATASIZE                       (0x00000000UL)
+#define SPI_CRC_LENGTH_4BIT                           (0x00030000UL)
+#define SPI_CRC_LENGTH_5BIT                           (0x00040000UL)
+#define SPI_CRC_LENGTH_6BIT                           (0x00050000UL)
+#define SPI_CRC_LENGTH_7BIT                           (0x00060000UL)
+#define SPI_CRC_LENGTH_8BIT                           (0x00070000UL)
+#define SPI_CRC_LENGTH_9BIT                           (0x00080000UL)
+#define SPI_CRC_LENGTH_10BIT                          (0x00090000UL)
+#define SPI_CRC_LENGTH_11BIT                          (0x000A0000UL)
+#define SPI_CRC_LENGTH_12BIT                          (0x000B0000UL)
+#define SPI_CRC_LENGTH_13BIT                          (0x000C0000UL)
+#define SPI_CRC_LENGTH_14BIT                          (0x000D0000UL)
+#define SPI_CRC_LENGTH_15BIT                          (0x000E0000UL)
+#define SPI_CRC_LENGTH_16BIT                          (0x000F0000UL)
+#define SPI_CRC_LENGTH_17BIT                          (0x00100000UL)
+#define SPI_CRC_LENGTH_18BIT                          (0x00110000UL)
+#define SPI_CRC_LENGTH_19BIT                          (0x00120000UL)
+#define SPI_CRC_LENGTH_20BIT                          (0x00130000UL)
+#define SPI_CRC_LENGTH_21BIT                          (0x00140000UL)
+#define SPI_CRC_LENGTH_22BIT                          (0x00150000UL)
+#define SPI_CRC_LENGTH_23BIT                          (0x00160000UL)
+#define SPI_CRC_LENGTH_24BIT                          (0x00170000UL)
+#define SPI_CRC_LENGTH_25BIT                          (0x00180000UL)
+#define SPI_CRC_LENGTH_26BIT                          (0x00190000UL)
+#define SPI_CRC_LENGTH_27BIT                          (0x001A0000UL)
+#define SPI_CRC_LENGTH_28BIT                          (0x001B0000UL)
+#define SPI_CRC_LENGTH_29BIT                          (0x001C0000UL)
+#define SPI_CRC_LENGTH_30BIT                          (0x001D0000UL)
+#define SPI_CRC_LENGTH_31BIT                          (0x001E0000UL)
+#define SPI_CRC_LENGTH_32BIT                          (0x001F0000UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
+  * @{
+  */
+#define SPI_FIFO_THRESHOLD_01DATA                     (0x00000000UL)
+#define SPI_FIFO_THRESHOLD_02DATA                     (0x00000020UL)
+#define SPI_FIFO_THRESHOLD_03DATA                     (0x00000040UL)
+#define SPI_FIFO_THRESHOLD_04DATA                     (0x00000060UL)
+#define SPI_FIFO_THRESHOLD_05DATA                     (0x00000080UL)
+#define SPI_FIFO_THRESHOLD_06DATA                     (0x000000A0UL)
+#define SPI_FIFO_THRESHOLD_07DATA                     (0x000000C0UL)
+#define SPI_FIFO_THRESHOLD_08DATA                     (0x000000E0UL)
+#define SPI_FIFO_THRESHOLD_09DATA                     (0x00000100UL)
+#define SPI_FIFO_THRESHOLD_10DATA                     (0x00000120UL)
+#define SPI_FIFO_THRESHOLD_11DATA                     (0x00000140UL)
+#define SPI_FIFO_THRESHOLD_12DATA                     (0x00000160UL)
+#define SPI_FIFO_THRESHOLD_13DATA                     (0x00000180UL)
+#define SPI_FIFO_THRESHOLD_14DATA                     (0x000001A0UL)
+#define SPI_FIFO_THRESHOLD_15DATA                     (0x000001C0UL)
+#define SPI_FIFO_THRESHOLD_16DATA                     (0x000001E0UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
+  * @{
+  */
+#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN       (0x00000000UL)
+#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN        (0x00000001UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_Polarity SPI NSS Polarity
+  * @{
+  */
+#define SPI_NSS_POLARITY_LOW                          (0x00000000UL)
+#define SPI_NSS_POLARITY_HIGH                          SPI_CFG2_SSIOP
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Master_Keep_IO_State Keep IO State
+  * @{
+  */
+#define SPI_MASTER_KEEP_IO_STATE_DISABLE              (0x00000000UL)
+#define SPI_MASTER_KEEP_IO_STATE_ENABLE               SPI_CFG2_AFCNTR
+/**
+  * @}
+  */
+
+/** @defgroup SPI_IO_Swap Control SPI IO Swap
+  * @{
+  */
+#define SPI_IO_SWAP_DISABLE                           (0x00000000UL)
+#define SPI_IO_SWAP_ENABLE                            SPI_CFG2_IOSWP
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness
+  * @{
+  */
+#define SPI_MASTER_SS_IDLENESS_00CYCLE                (0x00000000UL)
+#define SPI_MASTER_SS_IDLENESS_01CYCLE                (0x00000001UL)
+#define SPI_MASTER_SS_IDLENESS_02CYCLE                (0x00000002UL)
+#define SPI_MASTER_SS_IDLENESS_03CYCLE                (0x00000003UL)
+#define SPI_MASTER_SS_IDLENESS_04CYCLE                (0x00000004UL)
+#define SPI_MASTER_SS_IDLENESS_05CYCLE                (0x00000005UL)
+#define SPI_MASTER_SS_IDLENESS_06CYCLE                (0x00000006UL)
+#define SPI_MASTER_SS_IDLENESS_07CYCLE                (0x00000007UL)
+#define SPI_MASTER_SS_IDLENESS_08CYCLE                (0x00000008UL)
+#define SPI_MASTER_SS_IDLENESS_09CYCLE                (0x00000009UL)
+#define SPI_MASTER_SS_IDLENESS_10CYCLE                (0x0000000AUL)
+#define SPI_MASTER_SS_IDLENESS_11CYCLE                (0x0000000BUL)
+#define SPI_MASTER_SS_IDLENESS_12CYCLE                (0x0000000CUL)
+#define SPI_MASTER_SS_IDLENESS_13CYCLE                (0x0000000DUL)
+#define SPI_MASTER_SS_IDLENESS_14CYCLE                (0x0000000EUL)
+#define SPI_MASTER_SS_IDLENESS_15CYCLE                (0x0000000FUL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness
+  * @{
+  */
+#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE         (0x00000000UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE         (0x00000010UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE         (0x00000020UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE         (0x00000030UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE         (0x00000040UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE         (0x00000050UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE         (0x00000060UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE         (0x00000070UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE         (0x00000080UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE         (0x00000090UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE         (0x000000A0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE         (0x000000B0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE         (0x000000C0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE         (0x000000D0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE         (0x000000E0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE         (0x000000F0UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
+  * @{
+  */
+#define SPI_MASTER_RX_AUTOSUSP_DISABLE                (0x00000000UL)
+#define SPI_MASTER_RX_AUTOSUSP_ENABLE                 SPI_CR1_MASRX
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
+  * @{
+  */
+#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN           (0x00000000UL)
+#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED              SPI_CFG1_UDRCFG
+/**
+  * @}
+  */
+
+/** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management
+  * @{
+  */
+#define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY          (0x00000000UL)
+#define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY          SPI_CFG2_RDIOM
+/**
+  * @}
+  */
+
+/** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity
+  * @{
+  */
+#define SPI_RDY_POLARITY_HIGH                         (0x00000000UL)
+#define SPI_RDY_POLARITY_LOW                          SPI_CFG2_RDIOP
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
+  * @{
+  */
+#define SPI_IT_RXP                      SPI_IER_RXPIE
+#define SPI_IT_TXP                      SPI_IER_TXPIE
+#define SPI_IT_DXP                      SPI_IER_DXPIE
+#define SPI_IT_EOT                      SPI_IER_EOTIE
+#define SPI_IT_TXTF                     SPI_IER_TXTFIE
+#define SPI_IT_UDR                      SPI_IER_UDRIE
+#define SPI_IT_OVR                      SPI_IER_OVRIE
+#define SPI_IT_CRCERR                   SPI_IER_CRCEIE
+#define SPI_IT_FRE                      SPI_IER_TIFREIE
+#define SPI_IT_MODF                     SPI_IER_MODFIE
+#define SPI_IT_ERR                      (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Flags_definition SPI Flags Definition
+  * @{
+  */
+#define SPI_FLAG_RXP                    SPI_SR_RXP     /* SPI status flag : Rx-Packet available flag                 */
+#define SPI_FLAG_TXP                    SPI_SR_TXP     /* SPI status flag : Tx-Packet space available flag           */
+#define SPI_FLAG_DXP                    SPI_SR_DXP     /* SPI status flag : Duplex Packet flag                       */
+#define SPI_FLAG_EOT                    SPI_SR_EOT     /* SPI status flag : End of transfer flag                     */
+#define SPI_FLAG_TXTF                   SPI_SR_TXTF    /* SPI status flag : Transmission Transfer Filled flag        */
+#define SPI_FLAG_UDR                    SPI_SR_UDR     /* SPI Error flag  : Underrun flag                            */
+#define SPI_FLAG_OVR                    SPI_SR_OVR     /* SPI Error flag  : Overrun flag                             */
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCE    /* SPI Error flag  : CRC error flag                           */
+#define SPI_FLAG_FRE                    SPI_SR_TIFRE   /* SPI Error flag  : TI mode frame format error flag          */
+#define SPI_FLAG_MODF                   SPI_SR_MODF    /* SPI Error flag  : Mode fault flag                          */
+#define SPI_FLAG_SUSP                   SPI_SR_SUSP    /* SPI status flag : Transfer suspend complete flag           */
+#define SPI_FLAG_TXC                    SPI_SR_TXC     /* SPI status flag : TxFIFO transmission complete flag        */
+#define SPI_FLAG_FRLVL                  SPI_SR_RXPLVL  /* SPI status flag : Fifo reception level flag                */
+#define SPI_FLAG_RXWNE                  SPI_SR_RXWNE   /* SPI status flag : RxFIFO word not empty flag               */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+  * @{
+  */
+#define SPI_RX_FIFO_0PACKET             (0x00000000UL)         /* 0 or multiple of 4 packets available in the RxFIFO */
+#define SPI_RX_FIFO_1PACKET             (SPI_SR_RXPLVL_0)
+#define SPI_RX_FIFO_2PACKET             (SPI_SR_RXPLVL_1)
+#define SPI_RX_FIFO_3PACKET             (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SPI handle state.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+  * @retval None
+  */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)   do{                                                  \
+                                                       (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
+                                                       (__HANDLE__)->MspInitCallback = NULL;            \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                     } while(0)
+#else
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+/** @brief  Enable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_RXP    : Rx-Packet available interrupt
+  *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt
+  *            @arg SPI_IT_DXP    : Duplex Packet interrupt
+  *            @arg SPI_IT_EOT    : End of transfer interrupt
+  *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt
+  *            @arg SPI_IT_UDR    : Underrun interrupt
+  *            @arg SPI_IT_OVR    : Overrun  interrupt
+  *            @arg SPI_IT_CRCERR : CRC error interrupt
+  *            @arg SPI_IT_FRE    : TI mode frame format error interrupt
+  *            @arg SPI_IT_MODF   : Mode fault interrupt
+  *            @arg SPI_IT_ERR    : Error interrupt
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_RXP    : Rx-Packet available interrupt
+  *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt
+  *            @arg SPI_IT_DXP    : Duplex Packet interrupt
+  *            @arg SPI_IT_EOT    : End of transfer interrupt
+  *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt
+  *            @arg SPI_IT_UDR    : Underrun interrupt
+  *            @arg SPI_IT_OVR    : Overrun  interrupt
+  *            @arg SPI_IT_CRCERR : CRC error interrupt
+  *            @arg SPI_IT_FRE    : TI mode frame format error interrupt
+  *            @arg SPI_IT_MODF   : Mode fault interrupt
+  *            @arg SPI_IT_ERR    : Error interrupt
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SPI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_IT_RXP    : Rx-Packet available interrupt
+  *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt
+  *            @arg SPI_IT_DXP    : Duplex Packet interrupt
+  *            @arg SPI_IT_EOT    : End of transfer interrupt
+  *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt
+  *            @arg SPI_IT_UDR    : Underrun interrupt
+  *            @arg SPI_IT_OVR    : Overrun  interrupt
+  *            @arg SPI_IT_CRCERR : CRC error interrupt
+  *            @arg SPI_IT_FRE    : TI mode frame format error interrupt
+  *            @arg SPI_IT_MODF   : Mode fault interrupt
+  *            @arg SPI_IT_ERR    : Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \
+                                                              (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_FLAG_RXP    : Rx-Packet available flag
+  *            @arg SPI_FLAG_TXP    : Tx-Packet space available flag
+  *            @arg SPI_FLAG_DXP    : Duplex Packet flag
+  *            @arg SPI_FLAG_EOT    : End of transfer flag
+  *            @arg SPI_FLAG_TXTF   : Transmission Transfer Filled flag
+  *            @arg SPI_FLAG_UDR    : Underrun flag
+  *            @arg SPI_FLAG_OVR    : Overrun flag
+  *            @arg SPI_FLAG_CRCERR : CRC error flag
+  *            @arg SPI_FLAG_FRE    : TI mode frame format error flag
+  *            @arg SPI_FLAG_MODF   : Mode fault flag
+  *            @arg SPI_FLAG_SUSP   : Transfer suspend complete flag
+  *            @arg SPI_FLAG_TXC    : TxFIFO transmission complete flag
+  *            @arg SPI_FLAG_FRLVL  : Fifo reception level flag
+  *            @arg SPI_FLAG_RXWNE  : RxFIFO word not empty flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the SPI CRCERR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
+
+/** @brief  Clear the SPI MODF pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
+
+/** @brief  Clear the SPI OVR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
+
+/** @brief  Clear the SPI FRE pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
+
+/** @brief  Clear the SPI UDR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
+
+/** @brief  Clear the SPI EOT pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
+
+/** @brief  Clear the SPI UDR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
+
+/** @brief  Clear the SPI SUSP pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
+
+/** @brief  Enable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
+
+/** @brief  Disable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
+/**
+  * @}
+  */
+
+
+/* Include SPI HAL Extension module */
+#include "stm32n6xx_hal_spi_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+                                           pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                          uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                             uint16_t Size);
+
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size);
+
+
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
+uint32_t             HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+  * @{
+  */
+
+/** @brief  Set the SPI transmit-only mode in 1Line configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
+
+/** @brief  Set the SPI receive-only mode in 1Line configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
+
+/** @brief  Set the SPI transmit-only mode in 2Lines configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0)
+
+/** @brief  Set the SPI receive-only mode in 2Lines configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1)
+
+/** @brief  Set the SPI Transmit-Receive mode in 2Lines configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
+
+#define IS_SPI_MODE(MODE)                          (((MODE) == SPI_MODE_SLAVE) || \
+                                                    ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE)                     (((MODE) == SPI_DIRECTION_2LINES)        || \
+                                                    ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+                                                    ((MODE) == SPI_DIRECTION_1LINE)         || \
+                                                    ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+                                                              ((MODE) == SPI_DIRECTION_1LINE) || \
+                                                              ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+                                                              ((MODE) == SPI_DIRECTION_1LINE) || \
+                                                              ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
+
+#define IS_SPI_DATASIZE(DATASIZE)                  (((DATASIZE) == SPI_DATASIZE_32BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_31BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_30BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_29BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_28BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_27BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_26BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_25BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_24BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_23BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_21BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_20BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_19BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_18BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_17BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_16BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
+                                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
+                                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
+                                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
+                                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
+                                                    ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+/**
+  * @brief  DataSize for limited instance
+  */
+#define IS_SPI_LIMITED_DATASIZE(DATASIZE)          (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+                                                    ((DATASIZE) == SPI_DATASIZE_8BIT))
+
+#define IS_SPI_FIFOTHRESHOLD(THRESHOLD)            (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
+
+/**
+  * @brief  FifoThreshold for limited instance
+  */
+#define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD)    (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA))
+
+#define IS_SPI_CPOL(CPOL)                          (((CPOL) == SPI_POLARITY_LOW) || \
+                                                    ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA)                          (((CPHA) == SPI_PHASE_1EDGE) || \
+                                                    ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS)                            (((NSS) == SPI_NSS_SOFT)       || \
+                                                    ((NSS) == SPI_NSS_HARD_INPUT) || \
+                                                    ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_NSSP(NSSP)                          (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+                                                    ((NSSP) == SPI_NSS_PULSE_DISABLE))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)       (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_2)      || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)      || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)      || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)     || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)     || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)     || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_128)    || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT)                      (((BIT) == SPI_FIRSTBIT_MSB) || \
+                                                    ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE)                        (((MODE) == SPI_TIMODE_DISABLE) || \
+                                                    ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION)        (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+                                                    ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
+                                                    ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
+
+#define IS_SPI_CRC_LENGTH(LENGTH)                  (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_32BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_31BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_30BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_29BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_28BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_27BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_26BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_25BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_24BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_23BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_22BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_21BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_20BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_19BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_18BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_17BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_15BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_14BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_13BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_12BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_11BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_10BIT)    || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_9BIT)     || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)     || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_7BIT)     || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_6BIT)     || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_5BIT)     || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_4BIT))
+
+
+/**
+  * @brief  CRC Length for limited instance
+  */
+#define IS_SPI_LIMITED_CRC_LENGTH(LENGTH)          (((LENGTH) == SPI_CRC_LENGTH_8BIT)     || \
+                                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)          ((POLYNOMIAL) > 0x0UL)
+
+#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL)
+
+
+
+#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE)            (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
+                                                    ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED))
+
+#define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT)   (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \
+                                                    ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY))
+
+#define IS_SPI_RDY_POLARITY(POLARITY)              (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \
+                                                    ((POLARITY) == SPI_RDY_POLARITY_LOW))
+
+#define IS_SPI_MASTER_RX_AUTOSUSP(MODE)            (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \
+                                                    ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SPI_H */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spi_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spi_ex.h
new file mode 100644
index 000000000..03d81748d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_spi_ex.h
@@ -0,0 +1,99 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_spi_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPI HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SPI_EX_H
+#define STM32N6xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPIEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Types SPIEx Exported Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+                                              uint32_t UnderrunBehaviour);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SPI_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sram.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sram.h
new file mode 100644
index 000000000..23d370706
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_sram.h
@@ -0,0 +1,230 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sram.h
+  * @author  MCD Application Team
+  * @brief   Header file of SRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_SRAM_H
+#define STM32N6xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_fmc.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+/** @addtogroup SRAM
+  * @{
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+  * @{
+  */
+/**
+  * @brief  HAL SRAM State structures definition
+  */
+typedef enum
+{
+  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
+  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
+  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
+  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
+  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
+
+} HAL_SRAM_StateTypeDef;
+
+/**
+  * @brief  SRAM handle Structure definition
+  */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SRAM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+{
+  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
+
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
+
+  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
+
+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
+
+  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
+
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram);               /*!< SRAM Msp Init callback              */
+  void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram);             /*!< SRAM Msp DeInit callback            */
+  void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                      /*!< SRAM DMA Xfer Complete callback     */
+  void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                     /*!< SRAM DMA Xfer Error callback        */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+} SRAM_HandleTypeDef;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SRAM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
+  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
+  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
+  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
+} HAL_SRAM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SRAM Callback pointer definition
+  */
+typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
+typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+  * @{
+  */
+
+/** @brief Reset SRAM handle state
+  * @param  __HANDLE__ SRAM handle
+  * @retval None
+  */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
+                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+                                FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+  * @{
+  */
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                   uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/* SRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                            pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                               pSRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+  * @{
+  */
+
+/* SRAM Control functions  ****************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+
+/* SRAM  State functions ******************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_SRAM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_tim.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_tim.h
new file mode 100644
index 000000000..8110f0ffc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_tim.h
@@ -0,0 +1,2532 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_TIM_H
+#define STM32N6xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                                   Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                                   (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(),
+                                    __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(),
+                                    __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                     Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                     Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                               (or 0xFFEF if dithering is activated)
+                               Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+                               Pulse value */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+                               (or 0xFFEF if dithering is activated)
+                               Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
+                               Pulse value */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
+                                      ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+  uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t BreakAFMode;          /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
+
+  uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
+
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Break2AFMode;         /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
+
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  TIM Channel States definition
+  */
+typedef enum
+{
+  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
+  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
+  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+  * @brief  DMA Burst States definition
+  */
+typedef enum
+{
+  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
+  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
+  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
+  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
+  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
+  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
+                                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
+  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[6];   /*!< TIM channel operation state                       */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
+  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
+  void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Encoder Index Callback                              */
+  void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Direction Change Callback                           */
+  void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Index Error Callback                                */
+  void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Transition Error Callback                           */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                               */
+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                             */
+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                 */
+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                               */
+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                 */
+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                               */
+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                                */
+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                              */
+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                          */
+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                        */
+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                            */
+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                          */
+  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
+  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
+  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
+  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
+  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
+  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
+  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
+  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
+  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID                         */
+  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
+  , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
+  , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
+  , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
+  , HAL_TIM_BREAK2_CB_ID                  = 0x1BU   /*!< TIM Break2 Callback ID                                     */
+  , HAL_TIM_ENCODER_INDEX_CB_ID           = 0x1CU   /*!< TIM Encoder Index Callback ID                              */
+  , HAL_TIM_DIRECTION_CHANGE_CB_ID        = 0x1DU   /*!< TIM Direction Change Callback ID                           */
+  , HAL_TIM_INDEX_ERROR_CB_ID             = 0x1EU   /*!< TIM Index Error Callback ID                                */
+  , HAL_TIM_TRANSITION_ERROR_CB_ID        = 0x1FU   /*!< TIM Transition Error Callback ID                           */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_CCR5                   0x00000012U
+#define TIM_DMABASE_CCR6                   0x00000013U
+#define TIM_DMABASE_CCMR3                  0x00000014U
+#define TIM_DMABASE_DTR2                   0x00000015U
+#define TIM_DMABASE_ECR                    0x00000016U
+#define TIM_DMABASE_TISEL                  0x00000017U
+#define TIM_DMABASE_AF1                    0x00000018U
+#define TIM_DMABASE_AF2                    0x00000019U
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)                                   /*!< Encoder mode: Clock plus direction, x2 mode */
+#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2      (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)                                   /*!< Encoder mode: Directional Clock, x2 mode */
+#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define TIM_ENCODERMODE_X1_TI1                   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
+#define TIM_ENCODERMODE_X1_TI2                   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+#define TIM_IT_IDX                         TIM_DIER_IDXIE                       /*!< Index interrupt             */
+#define TIM_IT_DIR                         TIM_DIER_DIRIE                       /*!< Direction change interrupt  */
+#define TIM_IT_IERR                        TIM_DIER_IERRIE                      /*!< Index error interrupt       */
+#define TIM_IT_TERR                        TIM_DIER_TERRIE                      /*!< Transition error interrupt  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+  * @{
+  */
+#define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+#define TIM_FLAG_IDX                       TIM_SR_IDXF                          /*!< Encoder index flag            */
+#define TIM_FLAG_DIR                       TIM_SR_DIRF                          /*!< Direction change flag         */
+#define TIM_FLAG_IERR                      TIM_SR_IERRF                         /*!< Index error flag              */
+#define TIM_FLAG_TERR                      TIM_SR_TERRF                         /*!< Transition error flag         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+#define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
+#define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
+#define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
+#define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
+#define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
+#define TIM_CLOCKSOURCE_ITR9        TIM_TS_ITR9          /*!< External clock source mode 1 (ITR9)                   */
+#define TIM_CLOCKSOURCE_ITR10       TIM_TS_ITR10         /*!< External clock source mode 1 (ITR10)                  */
+#define TIM_CLOCKSOURCE_ITR11       TIM_TS_ITR11         /*!< External clock source mode 1 (ITR11)                  */
+#define TIM_CLOCKSOURCE_ITR12       TIM_TS_ITR12         /*!< External clock source mode 1 (ITR12)                  */
+#define TIM_CLOCKSOURCE_ITR13       TIM_TS_ITR13         /*!< External clock source mode 1 (ITR13)                  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
+  * @{
+  */
+#define TIM_BREAK_AFMODE_INPUT             0x00000000U                          /*!< Break input BRK in input mode */
+#define TIM_BREAK_AFMODE_BIDIRECTIONAL     TIM_BDTR_BKBID                       /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
+  * @{
+  */
+#define TIM_BREAK2_AFMODE_INPUT            0x00000000U                          /*!< Break2 input BRK2 in input mode */
+#define TIM_BREAK2_AFMODE_BIDIRECTIONAL    TIM_BDTR_BK2BID                      /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_ENCODER_CLK      TIM_CR2_MMS_3                                    /*!< Encoder clock is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
+#define TIM_SLAVEMODE_COMBINED_GATEDRESET    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)                  /*!< Combined gated + reset mode   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
+#define TIM_OCMODE_ASYMMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASYMMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+#define TIM_OCMODE_PULSE_ON_COMPARE        (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)                     /*!< Pulse on compare (CH3&CH4 only)        */
+#define TIM_OCMODE_DIRECTION_OUTPUT        (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0)  /*!< Direction output (CH3&CH4 only)        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
+#define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
+#define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
+#define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
+#define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
+#define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
+#define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_19TRANSFERS     0x00001200U                          /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_20TRANSFERS     0x00001300U                          /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_21TRANSFERS     0x00001400U                          /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_22TRANSFERS     0x00001500U                          /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_23TRANSFERS     0x00001600U                          /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_24TRANSFERS     0x00001700U                          /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_25TRANSFERS     0x00001800U                          /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_26TRANSFERS     0x00001900U                          /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC_TCM             SYSCFG_CBR_CM55CACHEL  /*!< Enables and locks the Cortex-M55 TCM double ECC error signal connection to TIM1/8/15/16/17 break inputs */
+#define TIM_BREAK_SYSTEM_ECC_CACHE           SYSCFG_CBR_CM55TCML    /*!< Enables and locks the Cortex-M55 cache double ECC error signa connection to TIM1/8/15/16/17 break inputs */
+#define TIM_BREAK_SYSTEM_ECC_BACKUP_RAM      SYSCFG_CBR_BKPRAML     /*!< Enables and locks the Backup RAM ECC double error detection flag connection to TIM1/8/15/16/17 break inputs */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CBR_PVDL_LOCK   /*!< Enables and locks the PVD signal connection to TIM1/8/15/16/17 break inputs */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CBR_CM55L       /*!< Enables and locks the Cortex-M55 lockup signal connection to TIM1/8/15/16/17 break inputs */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                     } while(0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+  *       disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  *            @arg TIM_FLAG_IDX: Index interrupt flag
+  *            @arg TIM_FLAG_DIR: Direction change interrupt flag
+  *            @arg TIM_FLAG_IERR: Index error interrupt flag
+  *            @arg TIM_FLAG_TERR: Transition error interrupt flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  *            @arg TIM_FLAG_IDX: Index interrupt flag
+  *            @arg TIM_FLAG_DIR: Direction change interrupt flag
+  *            @arg TIM_FLAG_IERR: Index error interrupt flag
+  *            @arg TIM_FLAG_TERR: Transition error interrupt flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  *            @arg TIM_IT_IDX: Index interrupt
+  *            @arg TIM_IT_DIR: Direction change interrupt
+  *            @arg TIM_IT_IERR: Index error interrupt
+  *            @arg TIM_IT_TERR: Transition error interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+  *       or Encoder mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
+  *      case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+  *         function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+   ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/** @brief  Select the Capture/compare DMA request source.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __CCDMA__ specifies Capture/compare DMA request source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+  *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+  * @retval None
+  */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
+  MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
+                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
+                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
+                                   ((__BASE__) == TIM_DMABASE_TISEL) || \
+                                   ((__BASE__) == TIM_DMABASE_DTR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_ECR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENABLE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
+                                                       ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
+                                                       ((__CHANNEL__) != (TIM_CHANNEL_6)))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1)                      || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2)                      || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12)                     || \
+                                            ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2)    || \
+                                            ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1)    || \
+                                            ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2)      || \
+                                            ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_X1_TI1)                   || \
+                                            ((__MODE__) == TIM_ENCODERMODE_X1_TI2))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ?  \
+                                               ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \
+                                                (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) :        \
+                                                (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) :       \
+                                               ((__PERIOD__) > 0U ))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR13))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
+                                         ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
+                                          ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)               || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)                 || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)                 || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)               || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)             || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
+                                   ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT)   || \
+                                   ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_TCM)        || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_CACHE)      || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_ECC_BACKUP_RAM) || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)            || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
+   (__HANDLE__)->ChannelState[5])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                       (__HANDLE__)->ChannelState[0]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[1]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[2]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[3]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[4]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[5]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                     } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+   (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
+                                                                         (__HANDLE__)->ChannelNState[0] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[1] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[2] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[3] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                       } while(0)
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32n6xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer,
+                                              uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t BurstLength,  uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions  ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+                                   uint32_t length);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_TIM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_tim_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_tim_ex.h
new file mode 100644
index 000000000..cf5b50ee4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_tim_ex.h
@@ -0,0 +1,1245 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_TIM_EX_H
+#define STM32N6xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
+} TIMEx_BreakInputConfigTypeDef;
+
+/**
+  * @brief  TIM Encoder index configuration
+  */
+typedef struct
+{
+  uint32_t Polarity;                  /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */
+
+  uint32_t Prescaler;                 /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */
+
+  uint32_t Filter;                    /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t  Blanking;                 /*!< Specifies whether or not the encoder index event is conditioned by TI3 or TI4 input.This parameter can be a value of @ref TIMEx_Encoder_Index_Blanking */
+
+  FunctionalState  FirstIndexEnable;  /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */
+
+  uint32_t Position;                  /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */
+
+  uint32_t Direction;                 /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */
+
+} TIMEx_EncoderIndexConfigTypeDef;
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_GPIO           0x00000000UL                                                                 /*!< TIM1_ETR is connected to I/O      */
+#define TIM_TIM1_ETR_ADC1_AWD1      (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                                        /*!< TIM1 ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2      TIM_AF1_ETRSEL_2                                                             /*!< TIM1 ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                                        /*!< TIM1 ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC2_AWD1      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                                        /*!< TIM1 ETR is connected to ADC2 AWD1 */
+#define TIM_TIM1_ETR_ADC2_AWD2      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM1 ETR is connected to ADC2 AWD2 */
+#define TIM_TIM1_ETR_ADC2_AWD3      TIM_AF1_ETRSEL_3                                                             /*!< TIM1 ETR is connected to ADC2 AWD3 */
+
+#define TIM_TIM2_ETR_GPIO           0x00000000UL                                                                 /*!< TIM2 ETR is connected to GPIO */
+#define TIM_TIM2_ETR_DCMIPP_HSYNC   TIM_AF1_ETRSEL_0                                                             /*!< TIM2_ETR is connected to DCMIPP HSYNC */
+#define TIM_TIM2_ETR_LCD_HSYNC      TIM_AF1_ETRSEL_1                                                             /*!< TIM2_ETR is connected to LCD HSYNC */
+#define TIM_TIM2_ETR_SAI1_FSA       TIM_AF1_ETRSEL_2                                                             /*!< TIM2_ETR is connected to SAI1 FS_A */
+#define TIM_TIM2_ETR_SAI1_FSB       (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                                        /*!< TIM2_ETR is connected to SAI1 FS_B */
+#define TIM_TIM2_ETR_GFXTIM_TE      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                                        /*!< TIM2_ETR is connected to GFXTIM TE */
+#define TIM_TIM2_ETR_DCMIPP_VSYNC   (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to DCMIPP VSYNC */
+#define TIM_TIM2_ETR_LCD_VSYNC      TIM_AF1_ETRSEL_3                                                             /*!< TIM2_ETR is connected to LCD VSYNC */
+#define TIM_TIM2_ETR_TIM3_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1)                                        /*!< TIM2_ETR is connected to TIM3_ETR */
+#define TIM_TIM2_ETR_TIM4_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to TIM4_ETR */
+#define TIM_TIM2_ETR_TIM5_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2)                                        /*!< TIM2_ETR is connected to TIM5_ETR */
+#define TIM_TIM2_ETR_ETH1_PPS       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to ETH1 PPS */
+#define TIM_TIM2_ETR_USB1_SOF       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                     /*!< TIM2_ETR is connected to USB1 OTG SOF */
+#define TIM_TIM2_ETR_USB2_SOF       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)  /*!< TIM2_ETR is connected to USB2 OTG SOF */
+
+#define TIM_TIM3_ETR_GPIO           0x00000000UL                                                                 /*!< TIM3 ETR is connected to GPIO */
+#define TIM_TIM3_ETR_DCMIPP_HSYNC   TIM_AF1_ETRSEL_0                                                             /*!< TIM3 ETR is connected to DCMIPP HSYNC */
+#define TIM_TIM3_ETR_LCD_HSYNC      TIM_AF1_ETRSEL_1                                                             /*!< TIM3 ETR is connected to LCD HSYNC */
+#define TIM_TIM3_ETR_GFXTIM_TE      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                                        /*!< TIM3 ETR is connected to GFXTIM TE */
+#define TIM_TIM3_ETR_DCMIPP_VSYNC   (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM3 ETR is connected to DCMIPP VSYNC */
+#define TIM_TIM3_ETR_LCD_VSYNC      TIM_AF1_ETRSEL_3                                                             /*!< TIM3 ETR is connected to LCD VSYNC */
+#define TIM_TIM3_ETR_TIM2_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0)                                        /*!< TIM3 ETR is connected to TIM2 ETR */
+#define TIM_TIM3_ETR_TIM4_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM3 ETR is connected to TIM4_ETR */
+#define TIM_TIM3_ETR_TIM5_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2)                                        /*!< TIM3 ETR is connected to TIM5_ETR */
+#define TIM_TIM3_ETR_ETH1_PPS       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                     /*!< TIM3_ETR is connected to ETH1 PPS */
+
+#define TIM_TIM4_ETR_GPIO           0x00000000UL                                                                 /*!< TIM4 ETR is connected to GPIO */
+#define TIM_TIM4_ETR_DCMIPP_HSYNC   TIM_AF1_ETRSEL_0                                                             /*!< TIM4 ETR is connected to DCMIPP HSYNC */
+#define TIM_TIM4_ETR_LCD_HSYNC      TIM_AF1_ETRSEL_1                                                             /*!< TIM4 ETR is connected to LCD HSYNC */
+#define TIM_TIM4_ETR_GFXTIM_TE      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                                        /*!< TIM4 ETR is connected to GFXTIM TE */
+#define TIM_TIM4_ETR_DCMIPP_VSYNC   (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM4 ETR is connected to DCMIPP VSYNC */
+#define TIM_TIM4_ETR_LCD_VSYNC      TIM_AF1_ETRSEL_3                                                             /*!< TIM4 ETR is connected to LCD VSYNC */
+#define TIM_TIM4_ETR_TIM2_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0)                                        /*!< TIM4 ETR is connected to TIM2 ETR */
+#define TIM_TIM4_ETR_TIM3_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1)                                        /*!< TIM4 ETR is connected to TIM3_ETR */
+#define TIM_TIM4_ETR_TIM5_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2)                                        /*!< TIM4 ETR is connected to TIM5_ETR */
+
+#define TIM_TIM5_ETR_GPIO           0x00000000UL                                                                 /*!< TIM5 ETR is connected to GPIO */
+#define TIM_TIM5_ETR_SAI2_FSA       TIM_AF1_ETRSEL_0                                                             /*!< TIM5_ETR is connected to SAI2 FS_A */
+#define TIM_TIM5_ETR_SAI2_FSB       TIM_AF1_ETRSEL_1                                                             /*!< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_DCMIPP_HSYNC   (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                                        /*!< TIM5 ETR is connected to DCMIPP HSYNC */
+#define TIM_TIM5_ETR_LCD_HSYNC      TIM_AF1_ETRSEL_2                                                             /*!< TIM5 ETR is connected to LCD HSYNC */
+#define TIM_TIM5_ETR_GFXTIM_TE      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                                        /*!< TIM5 ETR is connected to GFXTIM TE */
+#define TIM_TIM5_ETR_DCMIPP_VSYNC   (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM5 ETR is connected to DCMIPP VSYNC */
+#define TIM_TIM5_ETR_LCD_VSYNC      TIM_AF1_ETRSEL_3                                                             /*!< TIM5 ETR is connected to LCD VSYNC */
+#define TIM_TIM5_ETR_TIM2_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0)                                        /*!< TIM5 ETR is connected to TIM2_ETR */
+#define TIM_TIM5_ETR_TIM3_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1)                                        /*!< TIM5 ETR is connected to TIM3_ETR */
+#define TIM_TIM5_ETR_TIM4_ETR       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM5 ETR is connected to TIM4_ETR */
+#define TIM_TIM5_ETR_USB1_SOF       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                     /*!< TIM5_ETR is connected to USB1 OTG SOF */
+#define TIM_TIM5_ETR_USB2_SOF       (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)  /*!< TIM5_ETR is connected to USB2 OTG SOF */
+
+#define TIM_TIM8_ETR_GPIO           0x00000000UL                                                                 /*!< TIM8 ETR is connected to GPIO */
+#define TIM_TIM8_ETR_ADC2_AWD1      (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                                        /*!< TIM8 ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2      TIM_AF1_ETRSEL_2                                                             /*!< TIM8 ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                                        /*!< TIM8 ETR is connected to ADC2 AWD3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /*!< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /*!< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /*!< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_MDF1     0x00000008U                               /*!< The analog watchdog output of the MDF1 peripheral is connected to the break input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /*!< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /*!< Break input source is active_high */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+  * @{
+  */
+#define TIM_TIM2_TI1_GPIO                          0x00000000UL                                                   /*!< TIM2 TI1 is connected to GPIO */
+#define TIM_TIM2_TI1_ETH1_PPS                      TIM_TISEL_TI1SEL_0                                             /*!< TIM2 TI1 is connected to ETH1 PPS */
+
+#define TIM_TIM3_TI1_GPIO                          0x00000000UL                                                   /*!< TIM3 TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_ETH1_PPS                      TIM_TISEL_TI1SEL_0                                             /*!< TIM3 TI1 is connected to ETH1 PPS */
+#define TIM_TIM3_TI1_FDCAN_RTP                     TIM_TISEL_TI1SEL_1                                             /*!< TIM3_TI1 is connected to FDCAN RTP */
+#define TIM_TIM3_TI1_FDCAN_TMP                     (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM3_TI1 is connected to FDCAN TMP */
+#define TIM_TIM3_TI1_FDCAN_SOC                     TIM_TISEL_TI1SEL_2                                             /*!< TIM3_TI1 is connected to FDCAN SOC */
+
+#define TIM_TIM5_TI1_GPIO                          0x00000000UL                                                   /*!< TIM5 TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_FDCAN_RTP                     TIM_TISEL_TI1SEL_1                                             /*!< TIM5_TI1 is connected to FDCAN RTP */
+#define TIM_TIM5_TI1_FDCAN_TMP                     (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM5_TI1 is connected to FDCAN TMP */
+
+#define TIM_TIM9_TI1_GPIO                          0x00000000UL                                                   /*!< TIM9 TI1 is connected to GPIO */
+#define TIM_TIM9_TI1_MCO1                          TIM_TISEL_TI1SEL_2                                             /*!< TIM9 TI1 is connected to MCO1 */
+#define TIM_TIM9_TI1_MCO2                          (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)                      /*!< TIM9 TI1 is connected to MCO2 */
+
+#define TIM_TIM10_TI1_GPIO                         0x00000000UL                                                   /*!< TIM10_TI1 is connected to GPIO */
+#define TIM_TIM10_TI1_I3C1_IBIACK                  TIM_TISEL_TI1SEL_0                                             /*!< TIM10_TI1 is connected to I3C1 IBI ACK */
+
+#define TIM_TIM11_TI1_GPIO                         0x00000000UL                                                   /*!< TIM11_TI1 is connected to GPIO */
+#define TIM_TIM11_TI1_I3C2_IBIACK                  TIM_TISEL_TI1SEL_0                                             /*!< TIM11_TI1 is connected to I3C2 IBI ACK */
+
+#define TIM_TIM12_TI1_GPIO                         0x00000000UL                                                   /*!< TIM12 TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                                             /*!< TIM12 TI1 is connected to SPDIF FS */
+#define TIM_TIM12_TI1_HSI_1024                     TIM_TISEL_TI1SEL_1                                             /*!< TIM12 TI1 is connected to HSI/1024 */
+#define TIM_TIM12_TI1_MSI_128                      (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM12_TI1 is connected to MSI/128 */
+#define TIM_TIM12_TI1_MCO1                         TIM_TISEL_TI1SEL_2                                             /*!< TIM12 TI1 is connected to MCO1 */
+#define TIM_TIM12_TI1_MCO2                         (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)                      /*!< TIM12 TI1 is connected to MCO2 */
+
+#define TIM_TIM13_TI1_GPIO                         0x00000000UL                                                   /*!< TIM13_TI1 is connected to GPIO */
+#define TIM_TIM13_TI1_I3C1_IBIACK                  TIM_TISEL_TI1SEL_0                                             /*!< TIM13_TI1 is connected to I3C1 IBI ACK */
+
+#define TIM_TIM14_TI1_GPIO                         0x00000000UL                                                   /*!< TIM14_TI1 is connected to GPIO */
+#define TIM_TIM14_TI1_I3C2_IBIACK                  TIM_TISEL_TI1SEL_0                                             /*!< TIM14_TI1 is connected to I3C2 IBI ACK */
+
+#define TIM_TIM15_TI1_GPIO                         0x00000000UL                                                   /*!< TIM15 TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                                             /*!< TIM15 TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                                             /*!< TIM15 TI1 is connected to TIM3 CH1 */
+#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM15 TI1 is connected to TIM4 CH1 */
+#define TIM_TIM15_TI1_MCO1                         TIM_TISEL_TI1SEL_2                                             /*!< TIM15 TI1 is connected to MCO1 */
+#define TIM_TIM15_TI1_MCO2                         (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)                      /*!< TIM15 TI1 is connected to MCO2 */
+#define TIM_TIM15_TI2_GPIO                         0x00000000UL                                                   /*!< TIM15 TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2                     TIM_TISEL_TI2SEL_0                                             /*!< TIM15 TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2                     TIM_TISEL_TI2SEL_1                                             /*!< TIM15 TI2 is connected to TIM3 CH2 */
+#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)                      /*!< TIM15 TI2 is connected to TIM4 CH2 */
+
+#define TIM_TIM16_TI1_GPIO                         0x00000000UL                                                   /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_LSI                          TIM_TISEL_TI1SEL_0                                             /*!< TIM16 TI1 is connected to LSI */
+#define TIM_TIM16_TI1_LSE                          TIM_TISEL_TI1SEL_1                                             /*!< TIM16 TI1 is connected to LSE */
+#define TIM_TIM16_TI1_RTC_WKUP                     (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM16 TI1 is connected to RTC wakeup interrupt */
+
+#define TIM_TIM17_TI1_GPIO                         0x00000000UL                                                   /*!< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                                             /*!< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_HSE_1024                     TIM_TISEL_TI1SEL_1                                             /*!< TIM17 TI1 is connected to HSE/1024 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling
+  * @{
+  */
+#define TIM_SMS_PRELOAD_SOURCE_UPDATE     0x00000000U                            /*!< Prelaod of SMS bitfield is disabled */
+#define TIM_SMS_PRELOAD_SOURCE_INDEX      TIM_SMCR_SMSPS                         /*!< Preload of SMS bitfield is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Blanking TIM Extended Encoder index blanking
+  * @{
+  */
+#define TIM_ENCODERINDEX_BLANKING_DISABLE   0x00000000U     /*!< Encoder index blanking is disabled */
+#define TIM_ENCODERINDEX_BLANKING_TI3       TIM_ECR_IBLK_0     /*!< Encoder index blanking is enabled on TI3 */
+#define TIM_ENCODERINDEX_BLANKING_TI4       TIM_ECR_IBLK_1     /*!< Encoder index blanking is enabled on TI4 */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position
+  * @{
+  */
+#define TIM_ENCODERINDEX_POSITION_00        0x00000000U                           /*!< Encoder index position is AB=00 */
+#define TIM_ENCODERINDEX_POSITION_01        TIM_ECR_IPOS_0                        /*!< Encoder index position is AB=01 */
+#define TIM_ENCODERINDEX_POSITION_10        TIM_ECR_IPOS_1                        /*!< Encoder index position is AB=10 */
+#define TIM_ENCODERINDEX_POSITION_11        (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)     /*!< Encoder index position is AB=11 */
+#define TIM_ENCODERINDEX_POSITION_0         0x00000000U                           /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */
+#define TIM_ENCODERINDEX_POSITION_1         TIM_ECR_IPOS_0                        /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction
+  * @{
+  */
+#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U        /*!< Index resets the counter whatever the direction  */
+#define TIM_ENCODERINDEX_DIRECTION_UP      TIM_ECR_IDIR_0     /*!< Index resets the counter when up-counting only   */
+#define TIM_ENCODERINDEX_DIRECTION_DOWN    TIM_ECR_IDIR_1     /*!< Index resets the counter when down-counting only */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity
+  * @{
+  */
+#define TIM_ENCODERINDEX_POLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_ENCODERINDEX_POLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler
+  * @{
+  */
+#define TIM_ENCODERINDEX_PRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_ENCODERINDEX_PRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_ENCODERINDEX_PRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note   ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \
+  (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         output signal frequency.
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
+  * @note   This macro should be used only if dithering is already enabled
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65519)
+  */
+#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+  (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
+  (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note   ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
+  *         output compare active/inactive delay.
+  * @note   ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
+  * @note   This macro should be used only if dithering is already enabled
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65519)
+  */
+#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *        (when the timer operates in one pulse mode).
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         pulse duration (when the timer operates in one pulse mode).
+  * @note   ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
+  * @note   This macro should be used only if dithering is already enabled
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65519)
+  */
+#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                     \
+  ((((INSTANCE) == TIM1)  && (((TIM_REMAP) == TIM_TIM1_ETR_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM1_ETR_ADC1_AWD1)      || \
+                              ((TIM_REMAP) == TIM_TIM1_ETR_ADC1_AWD2)      || \
+                              ((TIM_REMAP) == TIM_TIM1_ETR_ADC1_AWD3)      || \
+                              ((TIM_REMAP) == TIM_TIM1_ETR_ADC2_AWD1)      || \
+                              ((TIM_REMAP) == TIM_TIM1_ETR_ADC2_AWD2)      || \
+                              ((TIM_REMAP) == TIM_TIM1_ETR_ADC2_AWD3)))    || \
+   (((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_ETR_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_DCMIPP_HSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_LCD_HSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_SAI1_FSA)       || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_SAI1_FSB)       || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_GFXTIM_TE)      || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_DCMIPP_VSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_LCD_VSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_TIM3_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_TIM4_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_TIM5_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_ETH1_PPS)       || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_USB1_SOF)       || \
+                              ((TIM_REMAP) == TIM_TIM2_ETR_USB2_SOF)))     || \
+   (((INSTANCE) == TIM3)  && (((TIM_REMAP) == TIM_TIM3_ETR_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_DCMIPP_HSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_LCD_HSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_GFXTIM_TE)      || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_DCMIPP_VSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_LCD_VSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_TIM2_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_TIM4_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_TIM5_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM3_ETR_ETH1_PPS)))     || \
+   (((INSTANCE) == TIM4)  && (((TIM_REMAP) == TIM_TIM4_ETR_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_DCMIPP_HSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_LCD_HSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_GFXTIM_TE)      || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_DCMIPP_VSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_LCD_VSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_TIM2_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_TIM3_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM4_ETR_TIM5_ETR)))     || \
+   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_ETR_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_SAI2_FSA)       || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_SAI2_FSB)       || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_DCMIPP_HSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_LCD_HSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_GFXTIM_TE)      || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_DCMIPP_VSYNC)   || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_LCD_VSYNC)      || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_TIM2_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_TIM3_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_TIM4_ETR)       || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_USB1_SOF)       || \
+                              ((TIM_REMAP) == TIM_TIM5_ETR_USB2_SOF)))     || \
+   (((INSTANCE) == TIM8)  && (((TIM_REMAP) == TIM_TIM8_ETR_GPIO)           || \
+                              ((TIM_REMAP) == TIM_TIM8_ETR_ADC2_AWD1)      || \
+                              ((TIM_REMAP) == TIM_TIM8_ETR_ADC2_AWD2)      || \
+                              ((TIM_REMAP) == TIM_TIM8_ETR_ADC2_AWD3))))
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \
+  (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
+
+#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
+
+#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)))               \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)))               \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)))               \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)))               \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR13)))               \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)))               \
+   ||                                        \
+   (((INSTANCE) == TIM9) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)))               \
+   ||                                         \
+   (((INSTANCE) == TIM12) &&                  \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)))               \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL)  ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)       ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9)      ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)     ||          \
+     ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12))))
+
+#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR13)   ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_ETRF)    ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM9) &&                  \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM12) &&                 \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR10)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2)))            \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_NONE)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR0)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR1)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR2)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR3)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR4)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR5)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR6)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR7)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR8)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR9)    ||          \
+     ((__SELECTION__) == TIM_TS_ITR11)   ||          \
+     ((__SELECTION__) == TIM_TS_ITR12)   ||          \
+     ((__SELECTION__) == TIM_TS_TI1F_ED) ||          \
+     ((__SELECTION__) == TIM_TS_TI1FP1)  ||          \
+     ((__SELECTION__) == TIM_TS_TI2FP2))))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
+  ((((INSTANCE) == TIM1) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM2) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM3) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM4) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM5) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_ITR13) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM8) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM9) &&                  \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM12) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR10) ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE)))           \
+   ||                                        \
+   (((INSTANCE) == TIM15) &&                 \
+    (((__SELECTION__) == TIM_TS_ITR0)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR1)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR2)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR3)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR4)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR5)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR6)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR7)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR8)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR9)  ||         \
+     ((__SELECTION__) == TIM_TS_ITR11) ||         \
+     ((__SELECTION__) == TIM_TS_ITR12) ||         \
+     ((__SELECTION__) == TIM_TS_NONE))))
+
+#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__)   \
+  (IS_TIM_OC_MODE(__MODE__) \
+   && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
+       ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1)))
+
+#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_3) ||    \
+   ((__CHANNEL__) == TIM_CHANNEL_4))
+
+#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE)  IS_TIM_CC3_INSTANCE(INSTANCE)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__)    ((__WIDTH__) <= 0xFFU)
+
+#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__)    ((__PRESCALER__) <= 0x7U)
+
+#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__)    (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \
+                                                    || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))
+
+#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__)        (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED)  || \
+                                                           ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))
+
+#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
+                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
+                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
+                                                           ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))
+
+#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__)            ((__FILTER__) <= 0xFUL)
+
+#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__)        (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0)  || \
+                                                           ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))
+
+#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__)      (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
+                                                           ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP)      || \
+                                                           ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))
+
+#define IS_TIM_ENCODERINDEX_BLANKING(__BLANKING__)      (((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_DISABLE) || \
+                                                         ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI3)     || \
+                                                         ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI4))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
+                                                    uint32_t PulseWidth);
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source);
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime);
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
+                                               TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);
+
+HAL_StatusTypeDef HAL_TIMEx_EnableADCSynchronization(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_DisableADCSynchronization(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32N6xx_HAL_TIM_EX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_uart.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_uart.h
new file mode 100644
index 000000000..97c47f3fc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_uart.h
@@ -0,0 +1,1763 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_UART_H
+#define STM32N6xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
+                                         The baud rate register is computed using the following formula:
+                                         LPUART:
+                                         =======
+                                         Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+                                         UART:
+                                         =====
+                                         - If oversampling is 16 or in LIN mode,
+                                            Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         - If oversampling is 8,
+                                            Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[15:4]
+                                            Baud Rate Register[3] =  0
+                                            Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[3:0]) >> 1
+                                         where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+  uint32_t WordLength;              /*!< Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref UARTEx_Word_Length. */
+
+  uint32_t StopBits;                /*!< Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref UART_Stop_Bits. */
+
+  uint32_t Parity;                  /*!< Specifies the parity mode.
+                                         This parameter can be a value of @ref UART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+
+  uint32_t Mode;                    /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref UART_Mode. */
+
+  uint32_t HwFlowCtl;               /*!< Specifies whether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+  uint32_t OverSampling;            /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+                                         to achieve higher speed (up to f_PCLK/8).
+                                         This parameter can be a value of @ref UART_Over_Sampling. */
+
+  uint32_t OneBitSampling;          /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                         Selecting the single sample method increases the receiver tolerance to clock
+                                         deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+  uint32_t ClockPrescaler;          /*!< Specifies the prescaler value used to divide the UART clock source.
+                                         This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+  * @brief  UART Advanced Features initialization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
+                                       Advanced Features may be initialized at the same time .
+                                       This parameter can be a value of
+                                       @ref UART_Advanced_Features_Initialization_Type. */
+
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Tx_Inv. */
+
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Rx_Inv. */
+
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
+                                       vs negative/inverted logic).
+                                       This parameter can be a value of @ref UART_Data_Inv. */
+
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
+                                       detection is carried out.
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
+                                       This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL UART State definition
+  * @note  HAL UART State value is a combination of 2 different substates:
+  *        gState and RxState (see @ref UART_State_Definition).
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+  * @brief HAL UART Reception type definition
+  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
+  *        This parameter can be a value of @ref UART_Reception_Type_Values :
+  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
+  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
+  *           HAL_UART_RECEPTION_TORTO            = 0x02U,
+  *           HAL_UART_RECEPTION_TOCHARMATCH      = 0x03U,
+  */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+  * @brief HAL UART Rx Event type definition
+  * @note  HAL UART Rx Event type value aims to identify which type of Event has occurred
+  *        leading to call of the RxEvent callback.
+  *        This parameter can be a value of @ref UART_RxEvent_Type_Values :
+  *           HAL_UART_RXEVENT_TC                 = 0x00U,
+  *           HAL_UART_RXEVENT_HT                 = 0x01U,
+  *           HAL_UART_RXEVENT_IDLE               = 0x02U,
+  */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef            *Instance;                /*!< UART registers base address        */
+
+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
+
+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
+
+  const uint8_t            *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
+
+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
+
+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
+
+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
+
+  __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
+
+  __IO HAL_UART_RxEventTypeTypeDef RxEventType;      /*!< Type of Rx Event                   */
+
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
+                                                          and also related to Tx operations. This parameter
+                                                          can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations. This
+                                                          parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
+  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef  void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+  * @{
+  */
+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
+                                                          Value is allowed for RxState only */
+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
+                                                          Not to be used for neither gState nor RxState.Value is result
+                                                          of combination (Or) between gState and RxState values */
+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
+                                                          Value is allowed for gState only */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Definition   UART Error Definition
+  * @{
+  */
+#define  HAL_UART_ERROR_NONE             (0x00000000U)    /*!< No error                */
+#define  HAL_UART_ERROR_PE               (0x00000001U)    /*!< Parity error            */
+#define  HAL_UART_ERROR_NE               (0x00000002U)    /*!< Noise error             */
+#define  HAL_UART_ERROR_FE               (0x00000004U)    /*!< Frame error             */
+#define  HAL_UART_ERROR_ORE              (0x00000008U)    /*!< Overrun error           */
+#if defined(HAL_DMA_MODULE_ENABLED)
+#define  HAL_UART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error      */
+#endif /* HAL_DMA_MODULE_ENABLED */
+#define  HAL_UART_ERROR_RTO              (0x00000020U)    /*!< Receiver Timeout error  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup UART_State  UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+  * @{
+  */
+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler
+  * @{
+  */
+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection
+                                                                              on start bit              */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection
+                                                                              on falling edge           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection
+                                                                              on 0x7F frame detection   */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection
+                                                                              on 0x55 frame detection   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+  * @{
+  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN    UART Local Interconnection Network mode
+  * @{
+  */
+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
+/**
+  * @}
+  */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/** @defgroup UART_DMA_Tx    UART DMA Tx
+  * @{
+  */
+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Rx   UART DMA Rx
+  * @{
+  */
+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
+/**
+  * @}
+  */
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
+  * @{
+  */
+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+  * @{
+  */
+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
+  * @{
+  */
+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
+#if defined(HAL_DMA_MODULE_ENABLED)
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
+#endif /* HAL_DMA_MODULE_ENABLED */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+  * @{
+  */
+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
+  * @{
+  */
+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
+/**
+  * @}
+  */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
+  * @{
+  */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
+  * @{
+  */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received
+                                                                         first disable                      */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received
+                                                                         first enable                       */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
+  * @{
+  */
+#define UART_CR2_ADDRESS_LSB_POS             24U             /*!< UART address-matching LSB position in CR2 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
+  * @{
+  */
+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                     */
+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                   */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register
+                                                                         not empty or RXFIFO is not empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
+  * @{
+  */
+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
+  * @{
+  */
+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
+/**
+  * @}
+  */
+
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
+  * @{
+  */
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags     UART Status Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)
+  *        Elements values convention: 000000000XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *        Elements values convention: 0000ZZZZ00000000b
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define UART_IT_PE                          0x0028U              /*!< UART parity error interruption                 */
+#define UART_IT_TXE                         0x0727U              /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF                       0x0727U              /*!< UART TX FIFO not full interruption             */
+#define UART_IT_TC                          0x0626U              /*!< UART transmission complete interruption        */
+#define UART_IT_RXNE                        0x0525U              /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE                       0x0525U              /*!< UART RXFIFO not empty interruption             */
+#define UART_IT_IDLE                        0x0424U              /*!< UART idle interruption                         */
+#define UART_IT_LBD                         0x0846U              /*!< UART LIN break detection interruption          */
+#define UART_IT_CTS                         0x096AU              /*!< UART CTS interruption                          */
+#define UART_IT_CM                          0x112EU              /*!< UART character match interruption              */
+#define UART_IT_WUF                         0x1476U              /*!< UART wake-up from stop mode interruption       */
+#define UART_IT_RXFF                        0x183FU              /*!< UART RXFIFO full interruption                  */
+#define UART_IT_TXFE                        0x173EU              /*!< UART TXFIFO empty interruption                 */
+#define UART_IT_RXFT                        0x1A7CU              /*!< UART RXFIFO threshold reached interruption     */
+#define UART_IT_TXFT                        0x1B77U              /*!< UART TXFIFO threshold reached interruption     */
+#define UART_IT_RTO                         0x0B3AU              /*!< UART receiver timeout interruption             */
+
+#define UART_IT_ERR                         0x0060U              /*!< UART error interruption                        */
+
+#define UART_IT_ORE                         0x0300U              /*!< UART overrun error interruption                */
+#define UART_IT_NE                          0x0200U              /*!< UART noise error interruption                  */
+#define UART_IT_FE                          0x0100U              /*!< UART frame error interruption                  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
+  * @{
+  */
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Reception_Type_Values  UART Reception type values
+  * @{
+  */
+#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
+#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
+#define HAL_UART_RECEPTION_TORTO             (0x00000002U)             /*!< Reception till completion or RTO event   */
+#define HAL_UART_RECEPTION_TOCHARMATCH       (0x00000003U)             /*!< Reception till completion or CM event    */
+/**
+  * @}
+  */
+
+/** @defgroup UART_RxEvent_Type_Values  UART RxEvent type values
+  * @{
+  */
+#define HAL_UART_RXEVENT_TC                  (0x00000000U)             /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT                  (0x00000001U)             /*!< RxEvent linked to Half Transfer event     */
+#define HAL_UART_RXEVENT_IDLE                (0x00000002U)             /*!< RxEvent linked to IDLE event              */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief  Reset UART handle states.
+  * @param  __HANDLE__ UART handle.
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flush the UART Data registers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+  }  while(0U)
+
+/** @brief  Clear the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief  Clear the UART TX FIFO empty clear flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief  Check whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag
+  *            @arg @ref UART_FLAG_CMF   Character match flag
+  *            @arg @ref UART_FLAG_BUSY  Busy flag
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
+  *            @arg @ref UART_FLAG_NE    Noise Error flag
+  *            @arg @ref UART_FLAG_FE    Framing Error flag
+  *            @arg @ref UART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Check whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief  Check whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
+                                                                (__HANDLE__)->Instance->CR1 : \
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
+                                                                 (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U <<\
+                                                                     (((uint16_t)(__INTERRUPT__)) &\
+                                                                      UART_IT_MASK)))  != RESET) ? SET : RESET)
+
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific UART request flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief  Enable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief  Disable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief  Enable CTS flow control.
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
+  do{                                                             \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
+  } while(0U)
+
+/** @brief  Disable CTS flow control.
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
+  do{                                                              \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
+  } while(0U)
+
+/** @brief  Enable RTS flow control.
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
+  do{                                                            \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
+  } while(0U)
+
+/** @brief  Disable RTS flow control.
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
+  do{                                                             \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
+  } while(0U)
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros   UART Private Macros
+  * @{
+  */
+/** @brief  Get UART clock division factor from clock prescaler value.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval UART clock division factor
+  */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U)
+
+/** @brief  BRR division operation to set BRR register with LPUART.
+  * @param  __PCLK__ LPUART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
+               (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
+  )
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                       \
+  ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  Check whether or not UART instance is Low Power UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+  */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief  Check UART Baud rate.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on N6 (i.e. 100 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+  */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500000U)
+
+/** @brief  Check UART assertion time.
+  * @param  __TIME__ 5-bit value assertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
+
+/** @brief  Check UART deassertion time.
+  * @param  __TIME__ 5-bit value deassertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+  * @brief Ensure that UART frame number of stop bits is valid.
+  * @param __STOPBITS__ UART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that LPUART frame number of stop bits is valid.
+  * @param __STOPBITS__ LPUART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                          ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that UART frame parity is valid.
+  * @param __PARITY__ UART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \
+                                    ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+  * @brief Ensure that UART hardware flow control is valid.
+  * @param __CONTROL__ UART hardware flow control.
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+  */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+  * @brief Ensure that UART communication mode is valid.
+  * @param __MODE__ UART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+  * @brief Ensure that UART state is valid.
+  * @param __STATE__ UART state.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+                                  ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+  * @brief Ensure that UART oversampling is valid.
+  * @param __SAMPLING__ UART oversampling.
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that UART frame sampling is valid.
+  * @param __ONEBIT__ UART frame sampling.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate detection mode is valid.
+  * @param __MODE__ UART auto Baud rate detection mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+  * @brief Ensure that UART receiver timeout setting is valid.
+  * @param __TIMEOUT__ UART receiver timeout setting.
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+  * @brief Ensure that UART LIN state is valid.
+  * @param __LIN__ UART LIN state.
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+  */
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
+                                     ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN break detection length is valid.
+  * @param __LENGTH__ UART LIN break detection length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief Ensure that UART DMA TX state is valid.
+  * @param __DMATX__ UART DMA TX state.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA RX state is valid.
+  * @param __DMARX__ UART DMA RX state.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @brief Ensure that UART half-duplex state is valid.
+  * @param __HDSEL__ UART half-duplex state.
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+  */
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up method is valid.
+  * @param __WAKEUP__ UART wake-up method .
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+  */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+  * @brief Ensure that UART request parameter is valid.
+  * @param __PARAM__ UART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that UART advanced features initialization is valid.
+  * @param __INIT__ UART advanced features initialization.
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#if defined(HAL_DMA_MODULE_ENABLED)
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+#else
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief Ensure that UART frame TX inversion setting is valid.
+  * @param __TXINV__ UART frame TX inversion setting.
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX inversion setting is valid.
+  * @param __RXINV__ UART frame RX inversion setting.
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame data inversion setting is valid.
+  * @param __DATAINV__ UART frame data inversion setting.
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+  * @param __SWAP__ UART frame RX/TX pins swap setting.
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that UART frame overrun setting is valid.
+  * @param __OVERRUN__ UART frame overrun setting.
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate state is valid.
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+                                                           ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+  * @param __DMA__ UART DMA enabling or disabling on error setting.
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief Ensure that UART frame MSB first setting is valid.
+  * @param __MSBFIRST__ UART frame MSB first setting.
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that UART stop mode state is valid.
+  * @param __STOPMODE__ UART stop mode state.
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART mute mode state is valid.
+  * @param __MUTE__ UART mute mode state.
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+  */
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up selection is valid.
+  * @param __WAKE__ UART wake-up selection.
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+  */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+  * @brief Ensure that UART driver enable polarity is valid.
+  * @param __POLARITY__ UART driver enable polarity.
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+  */
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+  * @brief Ensure that UART Prescaler is valid.
+  * @param __CLOCKPRESCALER__ UART Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+  * @}
+  */
+
+/* Include UART HAL Extended module */
+#include "stm32n6xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+#endif /* HAL_DMA_MODULE_ENABLED */
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(const UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void              UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout);
+void              UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/* Private variables -----------------------------------------------------------*/
+/** @defgroup UART_Private_variables UART Private variables
+  * @{
+  */
+/* Prescaler Table used in BRR computation macros.
+   Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_UART_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_uart_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_uart_ex.h
new file mode 100644
index 000000000..f70aa39c7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_uart_ex.h
@@ -0,0 +1,367 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_UART_EX_H
+#define STM32N6xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+  * @brief    UART FIFO mode
+  * @{
+  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+  * @brief    UART TXFIFO threshold level
+  * @{
+  */
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+  * @brief    UART RXFIFO threshold level
+  * @{
+  */
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)           \
+  do {                                                            \
+    if((__HANDLE__)->Instance == USART1)                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART1;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART2)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART2;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART3)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART3;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART4)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART4;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART5)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART5;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART6)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART6;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART7)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART7;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART8)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART8;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == UART9)                      \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_UART9;          \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART10)                    \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART10;        \
+    }                                                             \
+    else if((__HANDLE__)->Instance == LPUART1)                    \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_LPUART1;        \
+    }                                                             \
+    else                                                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = 0U;                                     \
+    }                                                             \
+  } while(0U)
+
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__ UART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__ UART wake-up address length.
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @brief Ensure that UART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that UART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_UART_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_usart.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_usart.h
new file mode 100644
index 000000000..eee6274b6
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_usart.h
@@ -0,0 +1,935 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_USART_H
+#define STM32N6xx_HAL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+  * @{
+  */
+
+/**
+  * @brief USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                              Baud Rate Register[15:4] = ((2 * fclk_pres) /
+                                              ((huart->Init.BaudRate)))[15:4]
+                                              Baud Rate Register[3]    = 0
+                                              Baud Rate Register[2:0]  =  (((2 * fclk_pres) /
+                                              ((huart->Init.BaudRate)))[3:0]) >> 1
+                                              where fclk_pres is the USART input clock frequency (fclk)
+                                              divided by a prescaler.
+                                           @note  Oversampling by 8 is systematically applied to
+                                                  achieve high baud rates. */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USARTEx_Word_Length. */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits. */
+
+  uint32_t Parity;                   /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode. */
+
+  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_Clock_Polarity. */
+
+  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_Clock_Phase. */
+
+  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_Last_Bit. */
+
+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
+                                           This parameter can be a value of @ref USART_ClockPrescaler. */
+} USART_InitTypeDef;
+
+/**
+  * @brief HAL USART State structures definition
+  */
+typedef enum
+{
+  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */
+  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */
+  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */
+  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */
+  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */
+  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
+  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */
+  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */
+} HAL_USART_StateTypeDef;
+
+/**
+  * @brief  USART handle Structure definition
+  */
+typedef struct __USART_HandleTypeDef
+{
+  USART_TypeDef                 *Instance;               /*!< USART registers base address        */
+
+  USART_InitTypeDef             Init;                    /*!< USART communication parameters      */
+
+  const uint8_t                 *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
+
+  uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */
+
+  __IO uint16_t                 TxXferCount;             /*!< USART Tx Transfer Counter           */
+
+  uint8_t                       *pRxBuffPtr;             /*!< Pointer to USART Rx transfer Buffer */
+
+  uint16_t                      RxXferSize;              /*!< USART Rx Transfer size              */
+
+  __IO uint16_t                 RxXferCount;             /*!< USART Rx Transfer Counter           */
+
+  uint16_t                      Mask;                    /*!< USART Rx RDR register mask          */
+
+  uint16_t                      NbRxDataToProcess;       /*!< Number of data to process during RX ISR execution */
+
+  uint16_t                      NbTxDataToProcess;       /*!< Number of data to process during TX ISR execution */
+
+  uint32_t                      SlaveMode;               /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
+                                                              of @ref USARTEx_Slave_Mode */
+
+  uint32_t                      FifoMode;                /*!< Specifies if the FIFO mode will be used. This parameter can be a value
+                                                              of @ref USARTEx_FIFO_mode. */
+
+  void (*RxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Rx IRQ handler  */
+
+  void (*TxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Tx IRQ handler  */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  DMA_HandleTypeDef             *hdmatx;                 /*!< USART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef             *hdmarx;                 /*!< USART Rx DMA Handle parameters      */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+  HAL_LockTypeDef               Lock;                    /*!< Locking object                      */
+
+  __IO HAL_USART_StateTypeDef   State;                   /*!< USART communication state           */
+
+  __IO uint32_t                 ErrorCode;               /*!< USART Error code                    */
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
+  void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
+  void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
+  void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
+  void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Fifo Full Callback            */
+  void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart);       /*!< USART Tx Fifo Empty Callback           */
+
+  void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
+#endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+} USART_HandleTypeDef;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL USART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
+  HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
+  HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
+  HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
+  HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
+  HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
+  HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
+  HAL_USART_RX_FIFO_FULL_CB_ID            = 0x07U,    /*!< USART Rx Fifo Full Callback ID            */
+  HAL_USART_TX_FIFO_EMPTY_CB_ID           = 0x08U,    /*!< USART Tx Fifo Empty Callback ID           */
+
+  HAL_USART_MSPINIT_CB_ID                 = 0x09U,    /*!< USART MspInit callback ID                 */
+  HAL_USART_MSPDEINIT_CB_ID               = 0x0AU     /*!< USART MspDeInit callback ID               */
+
+} HAL_USART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL USART Callback pointer definition
+  */
+typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
+
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_Error_Definition   USART Error Definition
+  * @{
+  */
+#define HAL_USART_ERROR_NONE             (0x00000000U)    /*!< No error                  */
+#define HAL_USART_ERROR_PE               (0x00000001U)    /*!< Parity error              */
+#define HAL_USART_ERROR_NE               (0x00000002U)    /*!< Noise error               */
+#define HAL_USART_ERROR_FE               (0x00000004U)    /*!< Frame error               */
+#define HAL_USART_ERROR_ORE              (0x00000008U)    /*!< Overrun error             */
+#if defined(HAL_DMA_MODULE_ENABLED)
+#define HAL_USART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error        */
+#endif /* HAL_DMA_MODULE_ENABLED */
+#define HAL_USART_ERROR_UDR              (0x00000020U)    /*!< SPI slave underrun error  */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error    */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+#define  HAL_USART_ERROR_RTO              (0x00000080U)    /*!< Receiver Timeout error  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Stop_Bits  USART Number of Stop Bits
+  * @{
+  */
+#define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */
+#define USART_STOPBITS_1                     0x00000000U                          /*!< USART frame with 1 stop bit    */
+#define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
+#define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Parity    USART Parity
+  * @{
+  */
+#define USART_PARITY_NONE                   0x00000000U                      /*!< No parity   */
+#define USART_PARITY_EVEN                   USART_CR1_PCE                    /*!< Even parity */
+#define USART_PARITY_ODD                    (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Mode   USART Mode
+  * @{
+  */
+#define USART_MODE_RX                       USART_CR1_RE                    /*!< RX mode        */
+#define USART_MODE_TX                       USART_CR1_TE                    /*!< TX mode        */
+#define USART_MODE_TX_RX                    (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock  USART Clock
+  * @{
+  */
+#define USART_CLOCK_DISABLE                 0x00000000U       /*!< USART clock disable */
+#define USART_CLOCK_ENABLE                  USART_CR2_CLKEN   /*!< USART clock enable  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Polarity  USART Clock Polarity
+  * @{
+  */
+#define USART_POLARITY_LOW                  0x00000000U      /*!< Driver enable signal is active high */
+#define USART_POLARITY_HIGH                 USART_CR2_CPOL   /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Clock_Phase   USART Clock Phase
+  * @{
+  */
+#define USART_PHASE_1EDGE                   0x00000000U      /*!< USART frame phase on first clock transition  */
+#define USART_PHASE_2EDGE                   USART_CR2_CPHA   /*!< USART frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit  USART Last Bit
+  * @{
+  */
+#define USART_LASTBIT_DISABLE               0x00000000U      /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE                USART_CR2_LBCL   /*!< USART frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup USART_ClockPrescaler  USART Clock Prescaler
+  * @{
+  */
+#define USART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define USART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define USART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define USART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define USART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define USART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define USART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define USART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define USART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define USART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define USART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define USART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Request_Parameters  USART Request Parameters
+  * @{
+  */
+#define USART_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define USART_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Flags      USART Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define USART_FLAG_TXFT                     USART_ISR_TXFT          /*!< USART TXFIFO threshold flag                */
+#define USART_FLAG_RXFT                     USART_ISR_RXFT          /*!< USART RXFIFO threshold flag                */
+#define USART_FLAG_RXFF                     USART_ISR_RXFF          /*!< USART RXFIFO Full flag                     */
+#define USART_FLAG_TXFE                     USART_ISR_TXFE          /*!< USART TXFIFO Empty flag                    */
+#define USART_FLAG_REACK                    USART_ISR_REACK         /*!< USART receive enable acknowledge flag      */
+#define USART_FLAG_TEACK                    USART_ISR_TEACK         /*!< USART transmit enable acknowledge flag     */
+#define USART_FLAG_BUSY                     USART_ISR_BUSY          /*!< USART busy flag                            */
+#define USART_FLAG_UDR                      USART_ISR_UDR           /*!< SPI slave underrun error flag              */
+#define USART_FLAG_TXE                      USART_ISR_TXE_TXFNF     /*!< USART transmit data register empty         */
+#define USART_FLAG_TXFNF                    USART_ISR_TXE_TXFNF     /*!< USART TXFIFO not full                      */
+#define USART_FLAG_RTOF                     USART_ISR_RTOF          /*!< USART receiver timeout flag                */
+#define USART_FLAG_TC                       USART_ISR_TC            /*!< USART transmission complete                */
+#define USART_FLAG_RXNE                     USART_ISR_RXNE_RXFNE    /*!< USART read data register not empty         */
+#define USART_FLAG_RXFNE                    USART_ISR_RXNE_RXFNE    /*!< USART RXFIFO not empty                     */
+#define USART_FLAG_IDLE                     USART_ISR_IDLE          /*!< USART idle flag                            */
+#define USART_FLAG_ORE                      USART_ISR_ORE           /*!< USART overrun error                        */
+#define USART_FLAG_NE                       USART_ISR_NE            /*!< USART noise error                          */
+#define USART_FLAG_FE                       USART_ISR_FE            /*!< USART frame error                          */
+#define USART_FLAG_PE                       USART_ISR_PE            /*!< USART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+  *        Elements values convention: 0000ZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+
+#define USART_IT_PE                          0x0028U     /*!< USART parity error interruption                 */
+#define USART_IT_TXE                         0x0727U     /*!< USART transmit data register empty interruption */
+#define USART_IT_TXFNF                       0x0727U     /*!< USART TX FIFO not full interruption             */
+#define USART_IT_TC                          0x0626U     /*!< USART transmission complete interruption        */
+#define USART_IT_RXNE                        0x0525U     /*!< USART read data register not empty interruption */
+#define USART_IT_RXFNE                       0x0525U     /*!< USART RXFIFO not empty interruption             */
+#define USART_IT_IDLE                        0x0424U     /*!< USART idle interruption                         */
+#define USART_IT_ERR                         0x0060U     /*!< USART error interruption                        */
+#define USART_IT_ORE                         0x0300U     /*!< USART overrun error interruption                */
+#define USART_IT_NE                          0x0200U     /*!< USART noise error interruption                  */
+#define USART_IT_FE                          0x0100U     /*!< USART frame error interruption                  */
+#define USART_IT_RXFF                        0x183FU     /*!< USART RXFIFO full interruption                  */
+#define USART_IT_TXFE                        0x173EU     /*!< USART TXFIFO empty interruption                 */
+#define USART_IT_RXFT                        0x1A7CU     /*!< USART RXFIFO threshold reached interruption     */
+#define USART_IT_TXFT                        0x1B77U     /*!< USART TXFIFO threshold reached interruption     */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags
+  * @{
+  */
+#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag             */
+#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag            */
+#define USART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag     */
+#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag            */
+#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag       */
+#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag    */
+#define USART_CLEAR_UDRF                      USART_ICR_UDRCF           /*!< SPI slave underrun error Clear Flag */
+#define USART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO Empty Clear Flag             */
+#define USART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< USART receiver timeout clear flag  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask
+  * @{
+  */
+#define USART_IT_MASK                             0x001FU     /*!< USART interruptions flags mask */
+#define USART_CR_MASK                             0x00E0U     /*!< USART control register mask */
+#define USART_CR_POS                              5U          /*!< USART control register position */
+#define USART_ISR_MASK                            0x1F00U     /*!< USART ISR register mask         */
+#define USART_ISR_POS                             8U          /*!< USART ISR register position     */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @brief Reset USART handle state.
+  * @param  __HANDLE__ USART handle.
+  * @retval None
+  */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
+                                                        (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+                                                        (__HANDLE__)->MspInitCallback = NULL;        \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;      \
+                                                      } while(0U)
+#else
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/** @brief  Check whether the specified USART flag is set or not.
+  * @param  __HANDLE__ specifies the USART Handle
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref USART_FLAG_TXFT  TXFIFO threshold flag
+  *            @arg @ref USART_FLAG_RXFT  RXFIFO threshold flag
+  *            @arg @ref USART_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref USART_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref USART_FLAG_BUSY  Busy flag
+  *            @arg @ref USART_FLAG_UDR   SPI slave underrun error flag
+  *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
+  *            @arg @ref USART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
+  *            @arg @ref USART_FLAG_RTOF  Receiver Timeout flag
+  *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref USART_FLAG_ORE   OverRun Error flag
+  *            @arg @ref USART_FLAG_NE    Noise Error flag
+  *            @arg @ref USART_FLAG_FE    Framing Error flag
+  *            @arg @ref USART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified USART pending flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref USART_CLEAR_RTOF     Receiver Timeout clear flag
+  *            @arg @ref USART_CLEAR_UDRF     SPI slave underrun error Clear Flag
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the USART PE pending flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief  Clear the USART FE pending flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief  Clear the USART NE pending flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief  Clear the USART ORE pending flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief  Clear the USART IDLE pending flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief  Clear the USART TX FIFO empty clear flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_TXFECF(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
+
+/** @brief  Clear SPI slave underrun error flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
+
+/** @brief  Enable the specified USART interrupt.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __INTERRUPT__ specifies the USART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref USART_IT_TC    Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref USART_IT_PE    Parity Error interrupt
+  *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
+  (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+   ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+   ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+   ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief  Disable the specified USART interrupt.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __INTERRUPT__ specifies the USART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref USART_IT_TC    Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref USART_IT_PE    Parity Error interrupt
+  *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
+  (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+   ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+   ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+   ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+   ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief  Check whether the specified USART interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __INTERRUPT__ specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref USART_IT_TC    Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE   OverRun Error interrupt
+  *            @arg @ref USART_IT_NE    Noise Error interrupt
+  *            @arg @ref USART_IT_FE    Framing Error interrupt
+  *            @arg @ref USART_IT_PE    Parity Error interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                         & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
+                                                                      USART_ISR_POS))) != 0U) ? SET : RESET)
+
+/** @brief  Check whether the specified USART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __INTERRUPT__ specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref USART_IT_TC    Transmission complete interrupt
+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref USART_IT_ORE   OverRun Error interrupt
+  *            @arg @ref USART_IT_NE    Noise Error interrupt
+  *            @arg @ref USART_IT_FE    Framing Error interrupt
+  *            @arg @ref USART_IT_PE    Parity Error interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
+                                                                 (__HANDLE__)->Instance->CR1 : \
+                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
+                                                                  (__HANDLE__)->Instance->CR2 : \
+                                                                  (__HANDLE__)->Instance->CR3)) & (0x01U <<\
+                                                                      (((uint16_t)(__INTERRUPT__)) &\
+                                                                       USART_IT_MASK)))  != 0U) ? SET : RESET)
+
+/** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref USART_CLEAR_RTOF     Receiver timeout clear flag
+  *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag
+  * @retval None
+  */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific USART request flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __REQ__ specifies the request flag to set.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the USART one bit sample method.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the USART one bit sample method.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief  Enable USART.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief  Disable USART.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None
+  */
+#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros   USART Private Macros
+  * @{
+  */
+
+/** @brief  Get USART clock division factor from clock prescaler value.
+  * @param  __CLOCKPRESCALER__ USART prescaler value.
+  * @retval USART clock division factor
+  */
+#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+  (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \
+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U)
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__ USART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ USART prescaler value.
+  * @retval Division result
+  */
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
+  (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+    + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  Report the USART clock source.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval the USART clocking source, written in __CLOCKSOURCE__.
+  */
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)          \
+  do {                                                            \
+    if((__HANDLE__)->Instance == USART1)                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART1;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART2)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART2;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART3)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART3;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART6)                     \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART6;         \
+    }                                                             \
+    else if((__HANDLE__)->Instance == USART10)                    \
+    {                                                             \
+      (__CLOCKSOURCE__) = (uint64_t)RCC_PERIPHCLK_USART10;        \
+    }                                                             \
+    else                                                          \
+    {                                                             \
+      (__CLOCKSOURCE__) = 0U;                                     \
+    }                                                             \
+  } while(0U)
+
+
+/** @brief  Check USART Baud rate.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on N6 (i.e. 100 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)  */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
+
+/**
+  * @brief Ensure that USART frame number of stop bits is valid.
+  * @param __STOPBITS__ USART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \
+                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+                                         ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+  * @brief Ensure that USART frame parity is valid.
+  * @param __PARITY__ USART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+                                     ((__PARITY__) == USART_PARITY_EVEN) || \
+                                     ((__PARITY__) == USART_PARITY_ODD))
+
+/**
+  * @brief Ensure that USART communication mode is valid.
+  * @param __MODE__ USART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+  * @brief Ensure that USART clock state is valid.
+  * @param __CLOCK__ USART clock state.
+  * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+  */
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+                                   ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+  * @brief Ensure that USART frame polarity is valid.
+  * @param __CPOL__ USART frame polarity.
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+  * @brief Ensure that USART frame phase is valid.
+  * @param __CPHA__ USART frame phase.
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+  * @brief Ensure that USART frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__ USART frame last bit clock pulse setting.
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+  * @brief Ensure that USART request parameter is valid.
+  * @param __PARAM__ USART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that USART Prescaler is valid.
+  * @param __CLOCKPRESCALER__ USART Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
+
+/**
+  * @}
+  */
+
+/* Include USART HAL Extended module */
+#include "stm32n6xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+                                             pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+                                     uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+                                            uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+                                               uint16_t Size);
+#if defined(HAL_DMA_MODULE_ENABLED)
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+                                                uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+#endif /* HAL_DMA_MODULE_ENABLED */
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
+uint32_t               HAL_USART_GetError(const USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_USART_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_usart_ex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_usart_ex.h
new file mode 100644
index 000000000..4a837c75f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_usart_ex.h
@@ -0,0 +1,282 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_usart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_USART_EX_H
+#define STM32N6xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+  * @{
+  */
+#define USART_WORDLENGTH_7B                  (USART_CR1_M1)   /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B                  (0x00000000U)    /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B                  (USART_CR1_M0)   /*!< 9-bit long USART frame */
+/**
+  * @}
+  */
+
+/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
+  * @{
+  */
+#define USART_NSS_HARD                        0x00000000U          /*!< SPI slave selection depends on NSS input pin              */
+#define USART_NSS_SOFT                        USART_CR2_DIS_NSS    /*!< SPI slave is always selected and NSS input pin is ignored */
+/**
+  * @}
+  */
+
+
+/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
+  * @brief    USART SLAVE mode
+  * @{
+  */
+#define USART_SLAVEMODE_DISABLE   0x00000000U     /*!< USART SPI Slave Mode Enable  */
+#define USART_SLAVEMODE_ENABLE    USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup USARTEx_FIFO_mode USARTEx FIFO  mode
+  * @brief    USART FIFO  mode
+  * @{
+  */
+#define USART_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
+#define USART_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
+  * @brief    USART TXFIFO level
+  * @{
+  */
+#define USART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
+#define USART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
+#define USART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
+#define USART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define USART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
+#define USART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
+  * @brief    USART RXFIFO level
+  * @{
+  */
+#define USART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define USART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define USART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define USART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define USART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define USART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Compute the USART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the USART Handle.
+  * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define USART_MASK_COMPUTATION(__HANDLE__)                            \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)         \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU;                                 \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU;                                 \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)    \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU;                                 \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU;                                 \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)    \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU;                                 \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU;                                 \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that USART frame length is valid.
+  * @param __LENGTH__ USART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+                                          ((__LENGTH__) == USART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
+  * @param __NSS__ USART Negative Slave Select pin management.
+  * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
+  */
+#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
+                               ((__NSS__) == USART_NSS_SOFT))
+
+/**
+  * @brief Ensure that USART Slave Mode is valid.
+  * @param __STATE__ USART Slave Mode.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_USART_SLAVEMODE(__STATE__)   (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
+                                         ((__STATE__) == USART_SLAVEMODE_ENABLE))
+
+/**
+  * @brief Ensure that USART FIFO mode is valid.
+  * @param __STATE__ USART FIFO mode.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
+                                             ((__STATE__) == USART_FIFOMODE_ENABLE))
+
+/**
+  * @brief Ensure that USART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ USART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \
+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \
+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \
+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \
+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \
+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that USART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ USART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \
+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \
+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \
+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \
+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \
+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
+void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup USARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_USART_EX_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_wwdg.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_wwdg.h
new file mode 100644
index 000000000..4ba6118f7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_wwdg.h
@@ -0,0 +1,307 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_wwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of WWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_WWDG_H
+#define STM32N6xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+  * @{
+  */
+
+/**
+  * @brief  WWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
+                               This parameter can be a value of @ref WWDG_Prescaler */
+
+  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
+                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
+                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
+                               This parameter can be a value of @ref WWDG_EWI_Mode */
+
+} WWDG_InitTypeDef;
+
+/**
+  * @brief  WWDG handle Structure definition
+  */
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+typedef struct __WWDG_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+{
+  WWDG_TypeDef      *Instance;  /*!< Register base address */
+
+  WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+  void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);                  /*!< WWDG Early WakeUp Interrupt callback */
+
+  void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg);              /*!< WWDG Msp Init callback */
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+} WWDG_HandleTypeDef;
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL WWDG common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_WWDG_EWI_CB_ID          = 0x00U,    /*!< WWDG EWI callback ID */
+  HAL_WWDG_MSPINIT_CB_ID      = 0x01U,    /*!< WWDG MspInit callback ID */
+} HAL_WWDG_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL WWDG Callback pointer definition
+  */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
+
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+  * @{
+  */
+#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+  * @brief WWDG Flag definition
+  * @{
+  */
+#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+  * @{
+  */
+#define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define WWDG_PRESCALER_16                   WWDG_CFR_WDGTB_2                         /*!< WWDG counter clock = (PCLK1/4096)/16 */
+#define WWDG_PRESCALER_32                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/32 */
+#define WWDG_PRESCALER_64                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)    /*!< WWDG counter clock = (PCLK1/4096)/64 */
+#define WWDG_PRESCALER_128                  WWDG_CFR_WDGTB                           /*!< WWDG counter clock = (PCLK1/4096)/128 */
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+  * @{
+  */
+#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
+#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+  * @{
+  */
+#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_8)  || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_16) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_32) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_64) || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_128))
+
+#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
+                                             ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+  * @}
+  */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the WWDG peripheral.
+  * @param  __HANDLE__  WWDG handle
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+  * @brief  Enable the WWDG early wakeup interrupt.
+  * @param  __HANDLE__: WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt to enable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @retval None
+  */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the selected WWDG interrupt has occurred or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the it to check.
+  *        This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief  Clear the WWDG interrupt pending bits.
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified WWDG flag is set or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval The new state of WWDG_FLAG (SET or RESET).
+  */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the WWDG's pending flags.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+  * @retval None
+  */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
+  * @param  __HANDLE__  WWDG Handle.
+  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
+  * @retval state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+                                                pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+  * @{
+  */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_WWDG_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_xspi.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_xspi.h
new file mode 100644
index 000000000..21b0fbbd7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_hal_xspi.h
@@ -0,0 +1,1313 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_xspi.h
+  * @author  MCD Application Team
+  * @brief   Header file of XSPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_HAL_XSPI_H
+#define STM32N6xx_HAL_XSPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined(XSPI) || defined(XSPI1) || defined(XSPI2) || defined(XSPI3)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup XSPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup XSPI_Exported_Types XSPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief XSPI Init structure definition
+  */
+typedef struct
+{
+  uint32_t FifoThresholdByte;         /*!< This is the threshold used by the Peripheral to generate the interrupt
+                                           indicating that data are available in reception or free place
+                                           is available in transmission.
+                                           For XSPI, this parameter can be a value between 1 and 64 */
+  uint32_t MemoryMode;                /*!< It Specifies the memory mode.
+                                           This parameter can be a value of @ref XSPI_MemoryMode */
+  uint32_t MemoryType;                /*!< It indicates the external device type connected to the XSPI.
+                                           This parameter can be a value of @ref XSPI_MemoryType */
+  uint32_t MemorySize;                /*!< It defines the size of the external device connected to the XSPI,
+                                           it corresponds to the number of address bits required to access
+                                           the external device.
+                                           This parameter can be a value of @ref XSPI_MemorySize*/
+  uint32_t ChipSelectHighTimeCycle;   /*!< It defines the minimum number of clocks which the chip select
+                                           must remain high between commands.
+                                           This parameter can be a value between 1 and 64U */
+  uint32_t FreeRunningClock;          /*!< It enables or not the free running clock.
+                                           This parameter can be a value of @ref XSPI_FreeRunningClock */
+  uint32_t ClockMode;                 /*!< It indicates the level of clock when the chip select is released.
+                                           This parameter can be a value of @ref XSPI_ClockMode */
+  uint32_t WrapSize;                  /*!< It indicates the wrap-size corresponding the external device configuration.
+                                           This parameter can be a value of @ref XSPI_WrapSize */
+  uint32_t ClockPrescaler;            /*!< It specifies the prescaler factor used for generating
+                                           the external clock based on the AHB clock.
+                                           This parameter can be a value between 0 and 255U */
+  uint32_t SampleShifting;            /*!< It allows to delay to 1/2 cycle the data sampling in order
+                                           to take in account external signal delays.
+                                           This parameter can be a value of @ref XSPI_SampleShifting */
+  uint32_t DelayHoldQuarterCycle;     /*!< It allows to hold to 1/4 cycle the data.
+                                           This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */
+  uint32_t ChipSelectBoundary;        /*!< It enables the transaction boundary feature and
+                                           defines the boundary of bytes to release the chip select.
+                                           This parameter can be a value of @ref XSPI_ChipSelectBoundary  */
+  uint32_t MaxTran;                   /*!< It enables the communication regulation feature. The chip select is
+                                           released every MaxTran+1 bytes when the other XSPI request the access
+                                           to the bus.
+                                           This parameter can be a value between 0 and 255U */
+  uint32_t Refresh;                   /*!< It enables the refresh rate feature. The chip select is released every
+                                           Refresh+1 clock cycles.
+                                           This parameter can be a value between 0 and 0xFFFFFFFF */
+  uint32_t MemorySelect;              /*!< It indicates if the output of nCS.
+                                           This parameter can be a value of @ref XSPI_MemorySelect  */
+  uint32_t MemoryExtended;            /*!< If available, It indicates if NCS1 and NCS2 are software or hardware controlled when one
+                                           XSPI drives two same size external memories located in contiguous places
+                                           in the memory map.
+                                           This parameter can be a value of @ref XSPI_MemoryExtended */
+} XSPI_InitTypeDef;
+
+/**
+  * @brief  HAL XSPI Handle Structure definition
+  */
+#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+typedef struct __XSPI_HandleTypeDef
+#else
+typedef struct
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+{
+  XSPI_TypeDef               *Instance;     /*!< XSPI registers base address                           */
+  XSPI_InitTypeDef           Init;          /*!< XSPI initialization parameters                        */
+  uint8_t                    *pBuffPtr;     /*!< Address of the XSPI buffer for transfer               */
+  __IO uint32_t              XferSize;      /*!< Number of data to transfer                            */
+  __IO uint32_t              XferCount;     /*!< Counter of data transferred                           */
+  DMA_HandleTypeDef          *hdmatx;       /*!< Handle of the DMA channel used for transmit           */
+  DMA_HandleTypeDef          *hdmarx;       /*!< Handle of the DMA channel used for receive            */
+  __IO uint32_t              State;         /*!< Internal state of the XSPI HAL driver                 */
+  __IO uint32_t              ErrorCode;     /*!< Error code in case of HAL driver internal error       */
+  uint32_t                   Timeout;       /*!< Timeout used for the XSPI external device access      */
+#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+  void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi);
+
+  void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi);
+  void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+} XSPI_HandleTypeDef;
+
+/**
+  * @brief  HAL XSPI Regular Command Structure definition
+  */
+typedef struct
+{
+  uint32_t OperationType;             /*!< It indicates if the configuration applies to the common registers or
+                                           to the registers for the write operation (these registers are only
+                                           used for memory-mapped mode).
+                                           This parameter can be a value of @ref XSPI_OperationType */
+  uint32_t IOSelect;                  /*!< It indicates the IOs used to exchange data with external memory.
+                                           This parameter can be a value of @ref XSPI_IOSelect */
+  uint32_t Instruction;               /*!< It contains the instruction to be sent to the device.
+                                           This parameter can be a value between 0 and 0xFFFFFFFFU */
+  uint32_t InstructionMode;           /*!< It indicates the mode of the instruction.
+                                           This parameter can be a value of @ref XSPI_InstructionMode */
+  uint32_t InstructionWidth;          /*!< It indicates the width of the instruction.
+                                           This parameter can be a value of @ref XSPI_InstructionWidth */
+  uint32_t InstructionDTRMode;        /*!< It enables or not the DTR mode for the instruction phase.
+                                           This parameter can be a value of @ref XSPI_InstructionDTRMode */
+  uint32_t Address;                   /*!< It contains the address to be sent to the device.
+                                           This parameter can be a value between 0 and 0xFFFFFFFFU */
+  uint32_t AddressMode;               /*!< It indicates the address mode. Address mode precises number of lines
+                                           for address (except no address).
+                                           This parameter can be a value of @ref XSPI_AddressMode */
+  uint32_t AddressWidth;              /*!< It indicates the width of the address.
+                                           This parameter can be a value of @ref XSPI_AddressWidth */
+  uint32_t AddressDTRMode;            /*!< It enables or not the DTR mode for the address phase.
+                                           This parameter can be a value of @ref XSPI_AddressDTRMode */
+  uint32_t AlternateBytes;            /*!< It contains the alternate bytes to be sent to the device.
+                                           This parameter can be a value between 0 and 0xFFFFFFFFU */
+  uint32_t AlternateBytesMode;        /*!< It indicates the mode of the alternate bytes.
+                                           This parameter can be a value of @ref XSPI_AlternateBytesMode */
+  uint32_t AlternateBytesWidth;       /*!< It indicates the width of the alternate bytes.
+                                           This parameter can be a value of @ref XSPI_AlternateBytesWidth */
+  uint32_t AlternateBytesDTRMode;     /*!< It enables or not the DTR mode for the alternate bytes phase.
+                                           This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */
+  uint32_t DataMode;                  /*!< It indicates the data mode. Data mode precises number of lines
+                                           for data exchange (except no data).
+                                           This parameter can be a value of @ref XSPI_DataMode */
+  uint32_t DataLength;                /*!< It indicates the number of data transferred with this command.
+                                           This field is only used for indirect mode.
+                                           This parameter can be a value between 1 and 0xFFFFFFFFU */
+  uint32_t DataDTRMode;               /*!< It enables or not the DTR mode for the data phase.
+                                           This parameter can be a value of @ref XSPI_DataDTRMode */
+  uint32_t DummyCycles;               /*!< It indicates the number of dummy cycles inserted before data phase.
+                                           This parameter can be a value between 0 and 31U */
+  uint32_t DQSMode;                   /*!< It enables or not the data strobe management.
+                                           This parameter can be a value of @ref XSPI_DQSMode */
+} XSPI_RegularCmdTypeDef;
+/**
+  * @brief  HAL XSPI Hyperbus Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t RWRecoveryTimeCycle;       /*!< It indicates the number of cycles for the device read write recovery time.
+                                           This parameter can be a value between 0 and 255U */
+  uint32_t AccessTimeCycle;           /*!< It indicates the number of cycles for the device access time.
+                                           This parameter can be a value between 0 and 255U */
+  uint32_t WriteZeroLatency;          /*!< It enables or not the latency for the write access.
+                                           This parameter can be a value of @ref XSPI_WriteZeroLatency */
+  uint32_t LatencyMode;               /*!< It configures the latency mode.
+                                           This parameter can be a value of @ref XSPI_LatencyMode */
+} XSPI_HyperbusCfgTypeDef;
+
+/**
+  * @brief  HAL XSPI Hyperbus Command Structure definition
+  */
+typedef struct
+{
+  uint32_t AddressSpace;              /*!< It indicates the address space accessed by the command.
+                                           This parameter can be a value of @ref XSPI_AddressSpace */
+  uint32_t Address;                   /*!< It contains the address to be sent to the device.
+                                           This parameter can be a value between 0 and 0xFFFFFFFFU */
+  uint32_t AddressWidth;              /*!< It indicates the width of the address.
+                                           This parameter can be a value of @ref XSPI_AddressWidth */
+  uint32_t DataLength;                /*!< It indicates the number of data transferred with this command.
+                                           This field is only used for indirect mode.
+                                           This parameter can be a value between 1 and 0xFFFFFFFF
+                                           In case of autopolling mode, this parameter can be
+                                           any value between 1 and 4 */
+  uint32_t DQSMode;                   /*!< It enables or not the data strobe management.
+                                           This parameter can be a value of @ref XSPI_DQSMode */
+  uint32_t DataMode;                  /*!< It indicates the data mode. Data mode precises number of lines
+                                           for data exchange (except no data).
+                                           This parameter can be a value of @ref XSPI_DataMode */
+} XSPI_HyperbusCmdTypeDef;
+
+/**
+  * @brief  HAL XSPI Auto Polling mode configuration structure definition
+  */
+typedef struct
+{
+  uint32_t MatchValue;                /*!< Specifies the value to be compared with the masked status register to get
+                                           a match.
+                                           This parameter can be any value between 0 and 0xFFFFFFFFU */
+  uint32_t MatchMask;                 /*!< Specifies the mask to be applied to the status bytes received.
+                                           This parameter can be any value between 0 and 0xFFFFFFFFU */
+  uint32_t MatchMode;                 /*!< Specifies the method used for determining a match.
+                                           This parameter can be a value of @ref XSPI_MatchMode */
+  uint32_t AutomaticStop;             /*!< Specifies if automatic polling is stopped after a match.
+                                           This parameter can be a value of @ref XSPI_AutomaticStop */
+  uint32_t IntervalTime;              /*!< Specifies the number of clock cycles between two read during automatic
+                                           polling phases.
+                                           This parameter can be any value between 0 and 0xFFFFU */
+} XSPI_AutoPollingTypeDef;
+
+/**
+  * @brief  HAL XSPI Memory Mapped mode configuration structure definition
+  */
+typedef struct
+{
+  uint32_t TimeOutActivation;         /*!< Specifies if the timeout counter is enabled to release the chip select.
+                                           This parameter can be a value of @ref XSPI_TimeOutActivation */
+  uint32_t TimeoutPeriodClock;        /*!< Specifies the number of clock to wait when the FIFO is full before to
+                                           release the chip select.
+                                           This parameter can be any value between 0 and 0xFFFFU */
+  uint32_t NoPrefetchData;            /*!< Specifies if the automatic prefetch in the external memory is enabled or not.
+                                           This parameter can be a value of @ref XSPI_NoPrefetchData */
+  uint32_t NoPrefetchAXI;             /*!< Specifies if the automatic prefetch in the external memory when the corresponding AXI
+                                           transaction is signaled as not-prefetchable, is enabled or not.
+                                           This parameter can be a value of @ref XSPI_NoPrefetchAXI */
+} XSPI_MemoryMappedTypeDef;
+
+/**
+  * @brief HAL XSPI IO Manager Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t nCSOverride;               /*!< It indicates Chip select selector override setting for XSPI.
+                                           This parameter can be a value @ref XSPIM_MemorySelect_Override */
+  uint32_t IOPort;                    /*!< It indicates which port of the XSPI IO Manager is used for the instance.
+                                           This parameter can be a value of @ref XSPI_IO_Manger_IOPort */
+  uint32_t Req2AckTime;               /*!< It indicates the minimum switching duration (in number of clock cycles)
+                                           expected if some signals are multiplexed in the XSPI IO Manager with the
+                                           other XSPI.
+                                           This parameter can be a value between 1 and 256 */
+} XSPIM_CfgTypeDef;
+
+#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  HAL XSPI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_XSPI_ERROR_CB_ID          = 0x00U,  /*!< XSPI Error Callback ID            */
+  HAL_XSPI_ABORT_CB_ID          = 0x01U,  /*!< XSPI Abort Callback ID            */
+  HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< XSPI FIFO Threshold Callback ID   */
+  HAL_XSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< XSPI Command Complete Callback ID */
+  HAL_XSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< XSPI Rx Complete Callback ID      */
+  HAL_XSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< XSPI Tx Complete Callback ID      */
+  HAL_XSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< XSPI Rx Half Complete Callback ID */
+  HAL_XSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< XSPI Tx Half Complete Callback ID */
+  HAL_XSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< XSPI Status Match Callback ID     */
+  HAL_XSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< XSPI Timeout Callback ID          */
+  HAL_XSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< XSPI MspInit Callback ID          */
+  HAL_XSPI_MSP_DEINIT_CB_ID     = 0x0BU   /*!< XSPI MspDeInit Callback ID        */
+} HAL_XSPI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL XSPI Callback pointer definition
+  */
+typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi);
+
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+/**
+  * @brief  HAL XSPI High-speed interface calibration structure definition
+  */
+typedef struct
+{
+  uint32_t DelayValueType;            /*!< It indicates which calibration is concerned by the configuration.
+                                           This parameter can be a value of @ref XSPI_DelayType */
+  uint32_t FineCalibrationUnit;       /*!< It indicates the fine calibration value of the delay.
+                                           This parameter can be a value between 0 and 0x7FU */
+  uint32_t CoarseCalibrationUnit;     /*!< It indicates the coarse calibration value of the delay.
+                                           This parameter can be a value between 0 and 0x1FU */
+  uint32_t MaxCalibration;            /*!< It indicates that the calibration is outside the range of DLL master.
+                                           It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY.
+                                           This parameter can be a value of @ref XSPI_MaxCal */
+} XSPI_HSCalTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup XSPI_Exported_Constants XSPI Exported Constants
+  * @{
+  */
+
+/** @defgroup XSPI_State XSPI State
+  * @{
+  */
+#define HAL_XSPI_STATE_RESET                 (0x00000000U)  /*!< Initial state                                                          */
+#define HAL_XSPI_STATE_READY                 (0x00000002U)  /*!< Driver ready to be used                                                */
+#define HAL_XSPI_STATE_HYPERBUS_INIT         (0x00000001U)  /*!< Initialization done in hyperbus mode but timing configuration not done */
+#define HAL_XSPI_STATE_CMD_CFG               (0x00000004U)  /*!< Command (regular or hyperbus) configured, ready for an action          */
+#define HAL_XSPI_STATE_READ_CMD_CFG          (0x00000014U)  /*!< Read command configuration done, not the write command configuration   */
+#define HAL_XSPI_STATE_WRITE_CMD_CFG         (0x00000024U)  /*!< Write command configuration done, not the read command configuration   */
+#define HAL_XSPI_STATE_BUSY_CMD              (0x00000008U)  /*!< Command without data on-going                                          */
+#define HAL_XSPI_STATE_BUSY_TX               (0x00000018U)  /*!< Indirect Tx on-going                                                   */
+#define HAL_XSPI_STATE_BUSY_RX               (0x00000028U)  /*!< Indirect Rx on-going                                                   */
+#define HAL_XSPI_STATE_BUSY_AUTO_POLLING     (0x00000048U)  /*!< Auto-polling on-going                                                  */
+#define HAL_XSPI_STATE_BUSY_MEM_MAPPED       (0x00000088U)  /*!< Memory-mapped on-going                                                 */
+#define HAL_XSPI_STATE_ABORT                 (0x00000100U)  /*!< Abort on-going                                                         */
+#define HAL_XSPI_STATE_ERROR                 (0x00000200U)  /*!< Blocking error, driver should be re-initialized                        */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_ErrorCode XSPI Error Code
+  * @{
+  */
+#define HAL_XSPI_ERROR_NONE                  (0x00000000U)  /*!< No error                         */
+#define HAL_XSPI_ERROR_TIMEOUT               (0x00000001U)  /*!< Timeout error                    */
+#define HAL_XSPI_ERROR_TRANSFER              (0x00000002U)  /*!< Transfer error                   */
+#define HAL_XSPI_ERROR_DMA                   (0x00000004U)  /*!< DMA transfer error               */
+#define HAL_XSPI_ERROR_INVALID_PARAM         (0x00000008U)  /*!< Invalid parameters error         */
+#define HAL_XSPI_ERROR_INVALID_SEQUENCE      (0x00000010U)  /*!< Sequence is incorrect            */
+#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+#define HAL_XSPI_ERROR_INVALID_CALLBACK      (0x00000020U)  /*!< Invalid callback error           */
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_MemoryMode XSPI Memory Mode
+  * @{
+  */
+#define HAL_XSPI_SINGLE_MEM                  (0x00000000U)  /*!< Dual-memory mode disabled        */
+#define HAL_XSPI_DUAL_MEM                    (XSPI_CR_DMM)  /*!< Dual mode enabled                */
+
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_MemoryType XSPI Memory Type
+  * @{
+  */
+#define HAL_XSPI_MEMTYPE_MICRON              (0x00000000U)                           /*!< Micron mode      */
+#define HAL_XSPI_MEMTYPE_MACRONIX            (XSPI_DCR1_MTYP_0)                      /*!< Macronix mode    */
+#define HAL_XSPI_MEMTYPE_APMEM               (XSPI_DCR1_MTYP_1)                      /*!< AP Memory mode   */
+#define HAL_XSPI_MEMTYPE_MACRONIX_RAM        ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/
+#define HAL_XSPI_MEMTYPE_HYPERBUS            (XSPI_DCR1_MTYP_2)                      /*!< Hyperbus mode    */
+#define HAL_XSPI_MEMTYPE_APMEM_16BITS        ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode   */
+
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_MemorySize XSPI Memory Size
+  * @{
+  */
+#define HAL_XSPI_SIZE_16B                    (0x00000000U)  /*!<  16 bits  (  2  Bytes = 2^( 0+1)) */
+#define HAL_XSPI_SIZE_32B                    (0x00000001U)  /*!<  32 bits  (  4  Bytes = 2^( 1+1)) */
+#define HAL_XSPI_SIZE_64B                    (0x00000002U)  /*!<  64 bits  (  8  Bytes = 2^( 2+1)) */
+#define HAL_XSPI_SIZE_128B                   (0x00000003U)  /*!< 128 bits  ( 16  Bytes = 2^( 3+1)) */
+#define HAL_XSPI_SIZE_256B                   (0x00000004U)  /*!< 256 bits  ( 32  Bytes = 2^( 4+1)) */
+#define HAL_XSPI_SIZE_512B                   (0x00000005U)  /*!< 512 bits  ( 64  Bytes = 2^( 5+1)) */
+#define HAL_XSPI_SIZE_1KB                    (0x00000006U)  /*!<   1 Kbits (128  Bytes = 2^( 6+1)) */
+#define HAL_XSPI_SIZE_2KB                    (0x00000007U)  /*!<   2 Kbits (256  Bytes = 2^( 7+1)) */
+#define HAL_XSPI_SIZE_4KB                    (0x00000008U)  /*!<   4 Kbits (512  Bytes = 2^( 8+1)) */
+#define HAL_XSPI_SIZE_8KB                    (0x00000009U)  /*!<   8 Kbits (  1 KBytes = 2^( 9+1)) */
+#define HAL_XSPI_SIZE_16KB                   (0x0000000AU)  /*!<  16 Kbits (  2 KBytes = 2^(10+1)) */
+#define HAL_XSPI_SIZE_32KB                   (0x0000000BU)  /*!<  32 Kbits (  4 KBytes = 2^(11+1)) */
+#define HAL_XSPI_SIZE_64KB                   (0x0000000CU)  /*!<  64 Kbits (  8 KBytes = 2^(12+1)) */
+#define HAL_XSPI_SIZE_128KB                  (0x0000000DU)  /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */
+#define HAL_XSPI_SIZE_256KB                  (0x0000000EU)  /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */
+#define HAL_XSPI_SIZE_512KB                  (0x0000000FU)  /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */
+#define HAL_XSPI_SIZE_1MB                    (0x00000010U)  /*!<   1 Mbits (128 KBytes = 2^(16+1)) */
+#define HAL_XSPI_SIZE_2MB                    (0x00000011U)  /*!<   2 Mbits (256 KBytes = 2^(17+1)) */
+#define HAL_XSPI_SIZE_4MB                    (0x00000012U)  /*!<   4 Mbits (512 KBytes = 2^(18+1)) */
+#define HAL_XSPI_SIZE_8MB                    (0x00000013U)  /*!<   8 Mbits (  1 MBytes = 2^(19+1)) */
+#define HAL_XSPI_SIZE_16MB                   (0x00000014U)  /*!<  16 Mbits (  2 MBytes = 2^(20+1)) */
+#define HAL_XSPI_SIZE_32MB                   (0x00000015U)  /*!<  32 Mbits (  4 MBytes = 2^(21+1)) */
+#define HAL_XSPI_SIZE_64MB                   (0x00000016U)  /*!<  64 Mbits (  8 MBytes = 2^(22+1)) */
+#define HAL_XSPI_SIZE_128MB                  (0x00000017U)  /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */
+#define HAL_XSPI_SIZE_256MB                  (0x00000018U)  /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */
+#define HAL_XSPI_SIZE_512MB                  (0x00000019U)  /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */
+#define HAL_XSPI_SIZE_1GB                    (0x0000001AU)  /*!<   1 Gbits (128 MBytes = 2^(26+1)) */
+#define HAL_XSPI_SIZE_2GB                    (0x0000001BU)  /*!<   2 Gbits (256 MBytes = 2^(27+1)) */
+#define HAL_XSPI_SIZE_4GB                    (0x0000001CU)  /*!<   4 Gbits (512 MBytes = 2^(28+1)) */
+#define HAL_XSPI_SIZE_8GB                    (0x0000001DU)  /*!<   8 Gbits (  1 GBytes = 2^(29+1)) */
+#define HAL_XSPI_SIZE_16GB                   (0x0000001EU)  /*!<  16 Gbits (  2 GBytes = 2^(30+1)) */
+#define HAL_XSPI_SIZE_32GB                   (0x0000001FU)  /*!<  32 Gbits (  4 GBytes = 2^(31+1)) */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock
+  * @{
+  */
+#define HAL_XSPI_FREERUNCLK_DISABLE          (0x00000000U)               /*!< CLK is not free running            */
+#define HAL_XSPI_FREERUNCLK_ENABLE           ((uint32_t)XSPI_DCR1_FRCK)  /*!< CLK is always provided (running)   */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_ClockMode XSPI Clock Mode
+  * @{
+  */
+#define HAL_XSPI_CLOCK_MODE_0                (0x00000000U)                 /*!< CLK must stay low while nCS is high  */
+#define HAL_XSPI_CLOCK_MODE_3                ((uint32_t)XSPI_DCR1_CKMODE)  /*!< CLK must stay high while nCS is high */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_WrapSize XSPI Wrap-Size
+  * @{
+  */
+#define HAL_XSPI_WRAP_NOT_SUPPORTED          (0x00000000U)                                             /*!< wrapped reads are not supported by the memory   */
+#define HAL_XSPI_WRAP_16_BYTES               ((uint32_t)XSPI_DCR2_WRAPSIZE_1)                          /*!< external memory supports wrap size of 16 bytes  */
+#define HAL_XSPI_WRAP_32_BYTES               ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes  */
+#define HAL_XSPI_WRAP_64_BYTES               ((uint32_t)XSPI_DCR2_WRAPSIZE_2)                          /*!< external memory supports wrap size of 64 bytes  */
+#define HAL_XSPI_WRAP_128_BYTES              ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_SampleShifting XSPI Sample Shifting
+  * @{
+  */
+#define HAL_XSPI_SAMPLE_SHIFT_NONE           (0x00000000U)                /*!< No shift                         */
+#define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE      ((uint32_t)XSPI_TCR_SSHIFT)  /*!< 1/2 cycle shift                  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle
+  * @{
+  */
+#define HAL_XSPI_DHQC_DISABLE                (0x00000000U)              /*!< No Delay                         */
+#define HAL_XSPI_DHQC_ENABLE                 ((uint32_t)XSPI_TCR_DHQC)  /*!< Delay Hold 1/4 cycle             */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary
+  * @{
+  */
+#define HAL_XSPI_BONDARYOF_NONE              (0x00000000U)  /*!     CS boundary disabled         */
+#define HAL_XSPI_BONDARYOF_16B               (0x00000001U)  /*!<  16 bits  (  2  Bytes = 2^(1))  */
+#define HAL_XSPI_BONDARYOF_32B               (0x00000002U)  /*!<  32 bits  (  4  Bytes = 2^(2))  */
+#define HAL_XSPI_BONDARYOF_64B               (0x00000003U)  /*!<  64 bits  (  8  Bytes = 2^(3))  */
+#define HAL_XSPI_BONDARYOF_128B              (0x00000004U)  /*!< 128 bits  ( 16  Bytes = 2^(4))  */
+#define HAL_XSPI_BONDARYOF_256B              (0x00000005U)  /*!< 256 bits  ( 32  Bytes = 2^(5))  */
+#define HAL_XSPI_BONDARYOF_512B              (0x00000006U)  /*!< 512 bits  ( 64  Bytes = 2^(6))  */
+#define HAL_XSPI_BONDARYOF_1KB               (0x00000007U)  /*!<   1 Kbits (128  Bytes = 2^(7))  */
+#define HAL_XSPI_BONDARYOF_2KB               (0x00000008U)  /*!<   2 Kbits (256  Bytes = 2^(8))  */
+#define HAL_XSPI_BONDARYOF_4KB               (0x00000009U)  /*!<   4 Kbits (512  Bytes = 2^(9))  */
+#define HAL_XSPI_BONDARYOF_8KB               (0x0000000AU)  /*!<   8 Kbits (  1 KBytes = 2^(10)) */
+#define HAL_XSPI_BONDARYOF_16KB              (0x0000000BU)  /*!<  16 Kbits (  2 KBytes = 2^(11)) */
+#define HAL_XSPI_BONDARYOF_32KB              (0x0000000CU)  /*!<  32 Kbits (  4 KBytes = 2^(12)) */
+#define HAL_XSPI_BONDARYOF_64KB              (0x0000000DU)  /*!<  64 Kbits (  8 KBytes = 2^(13)) */
+#define HAL_XSPI_BONDARYOF_128KB             (0x0000000EU)  /*!< 128 Kbits ( 16 KBytes = 2^(14)) */
+#define HAL_XSPI_BONDARYOF_256KB             (0x0000000FU)  /*!< 256 Kbits ( 32 KBytes = 2^(15)) */
+#define HAL_XSPI_BONDARYOF_512KB             (0x00000010U)  /*!< 512 Kbits ( 64 KBytes = 2^(16)) */
+#define HAL_XSPI_BONDARYOF_1MB               (0x00000011U)  /*!<   1 Mbits (128 KBytes = 2^(17)) */
+#define HAL_XSPI_BONDARYOF_2MB               (0x00000012U)  /*!<   2 Mbits (256 KBytes = 2^(18)) */
+#define HAL_XSPI_BONDARYOF_4MB               (0x00000013U)  /*!<   4 Mbits (512 KBytes = 2^(19)) */
+#define HAL_XSPI_BONDARYOF_8MB               (0x00000014U)  /*!<   8 Mbits (  1 MBytes = 2^(20)) */
+#define HAL_XSPI_BONDARYOF_16MB              (0x00000015U)  /*!<  16 Mbits (  2 MBytes = 2^(21)) */
+#define HAL_XSPI_BONDARYOF_32MB              (0x00000016U)  /*!<  32 Mbits (  4 MBytes = 2^(22)) */
+#define HAL_XSPI_BONDARYOF_64MB              (0x00000017U)  /*!<  64 Mbits (  8 MBytes = 2^(23)) */
+#define HAL_XSPI_BONDARYOF_128MB             (0x00000018U)  /*!< 128 Mbits ( 16 MBytes = 2^(24)) */
+#define HAL_XSPI_BONDARYOF_256MB             (0x00000019U)  /*!< 256 Mbits ( 32 MBytes = 2^(25)) */
+#define HAL_XSPI_BONDARYOF_512MB             (0x0000001AU)  /*!< 512 Mbits ( 64 MBytes = 2^(26)) */
+#define HAL_XSPI_BONDARYOF_1GB               (0x0000001BU)  /*!<   1 Gbits (128 MBytes = 2^(27)) */
+#define HAL_XSPI_BONDARYOF_2GB               (0x0000001CU)  /*!<   2 Gbits (256 MBytes = 2^(28)) */
+#define HAL_XSPI_BONDARYOF_4GB               (0x0000001DU)  /*!<   4 Gbits (512 MBytes = 2^(29)) */
+#define HAL_XSPI_BONDARYOF_8GB               (0x0000001EU)  /*!<   8 Gbits (  1 GBytes = 2^(30)) */
+#define HAL_XSPI_BONDARYOF_16GB              (0x0000001FU)  /*!<  16 Gbits (  2 GBytes = 2^(31)) */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_MemorySelect XSPI Memory Select
+  * @{
+  */
+#define HAL_XSPI_CSSEL_NCS1                  (0x00000000U)             /*!<  The output of nCS is nCS1       */
+#define HAL_XSPI_CSSEL_NCS2                  ((uint32_t)XSPI_CR_CSSEL) /*!<  The output of nCS is nCS2       */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_MemoryExtended XSPI Memory Extended
+  * @{
+  */
+#define HAL_XSPI_CSSEL_SW                  (0x00000000U)             /*!<  NCS1 and NCS2 are software controlled.      */
+#define HAL_XSPI_CSSEL_HW                  ((uint32_t)XSPI_DCR1_EXTENDMEM) /*!<  NCS1 and NCS2 are hardware controlled.      */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_OperationType XSPI Operation Type
+  * @{
+  */
+#define HAL_XSPI_OPTYPE_COMMON_CFG           (0x00000000U)  /*!< Common configuration (indirect or auto-polling mode) */
+#define HAL_XSPI_OPTYPE_READ_CFG             (0x00000001U)  /*!< Read configuration (memory-mapped mode)              */
+#define HAL_XSPI_OPTYPE_WRITE_CFG            (0x00000002U)  /*!< Write configuration (memory-mapped mode)             */
+#define HAL_XSPI_OPTYPE_WRAP_CFG             (0x00000003U)  /*!< Wrap configuration (memory-mapped mode)              */
+
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_IOSelect XSPI IO Select
+  * @{
+  */
+#define HAL_XSPI_SELECT_IO_3_0               (0x00000000U)                                /*!< Data exchanged over IO[3:0]   */
+#define HAL_XSPI_SELECT_IO_7_4               ((uint32_t)XSPI_CR_MSEL_0)                               /*!< Data exchanged over IO[7:4]   */
+#define HAL_XSPI_SELECT_IO_11_8              ((uint32_t)XSPI_CR_MSEL_1)                               /*!< Data exchanged over IO[11:8]  */
+#define HAL_XSPI_SELECT_IO_15_12             ((uint32_t)XSPI_CR_MSEL )                                /*!< Data exchanged over IO[15:12] */
+#define HAL_XSPI_SELECT_IO_7_0               (0x00000000U)                                                            /*!< Data exchanged over IO[7:0]   */
+#define HAL_XSPI_SELECT_IO_15_8              ((uint32_t)XSPI_CR_MSEL_1)                               /*!< Data exchanged over IO[15:8]  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_InstructionMode XSPI Instruction Mode
+  * @{
+  */
+#define HAL_XSPI_INSTRUCTION_NONE            (0x00000000U)                                     /*!< No instruction               */
+#define HAL_XSPI_INSTRUCTION_1_LINE          ((uint32_t)XSPI_CCR_IMODE_0)                      /*!< Instruction on a single line */
+#define HAL_XSPI_INSTRUCTION_2_LINES         ((uint32_t)XSPI_CCR_IMODE_1)                      /*!< Instruction on two lines     */
+#define HAL_XSPI_INSTRUCTION_4_LINES         ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines    */
+#define HAL_XSPI_INSTRUCTION_8_LINES         ((uint32_t)XSPI_CCR_IMODE_2)                      /*!< Instruction on eight lines   */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_InstructionWidth XSPI Instruction Width
+  * @{
+  */
+#define HAL_XSPI_INSTRUCTION_8_BITS          (0x00000000U)                 /*!< 8-bit instruction  */
+#define HAL_XSPI_INSTRUCTION_16_BITS         ((uint32_t)XSPI_CCR_ISIZE_0)  /*!< 16-bit instruction */
+#define HAL_XSPI_INSTRUCTION_24_BITS         ((uint32_t)XSPI_CCR_ISIZE_1)  /*!< 24-bit instruction */
+#define HAL_XSPI_INSTRUCTION_32_BITS         ((uint32_t)XSPI_CCR_ISIZE)    /*!< 32-bit instruction */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode
+  * @{
+  */
+#define HAL_XSPI_INSTRUCTION_DTR_DISABLE     (0x00000000U)              /*!< DTR mode disabled for instruction phase */
+#define HAL_XSPI_INSTRUCTION_DTR_ENABLE      ((uint32_t)XSPI_CCR_IDTR)  /*!< DTR mode enabled for instruction phase  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AddressMode XSPI Address Mode
+  * @{
+  */
+#define HAL_XSPI_ADDRESS_NONE                (0x00000000U)                                        /*!< No address               */
+#define HAL_XSPI_ADDRESS_1_LINE              ((uint32_t)XSPI_CCR_ADMODE_0)                        /*!< Address on a single line */
+#define HAL_XSPI_ADDRESS_2_LINES             ((uint32_t)XSPI_CCR_ADMODE_1)                        /*!< Address on two lines     */
+#define HAL_XSPI_ADDRESS_4_LINES             ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1))  /*!< Address on four lines    */
+#define HAL_XSPI_ADDRESS_8_LINES             ((uint32_t)XSPI_CCR_ADMODE_2)                        /*!< Address on eight lines   */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AddressWidth XSPI Address width
+  * @{
+  */
+#define HAL_XSPI_ADDRESS_8_BITS              (0x00000000U)                  /*!< 8-bit address  */
+#define HAL_XSPI_ADDRESS_16_BITS             ((uint32_t)XSPI_CCR_ADSIZE_0)  /*!< 16-bit address */
+#define HAL_XSPI_ADDRESS_24_BITS             ((uint32_t)XSPI_CCR_ADSIZE_1)  /*!< 24-bit address */
+#define HAL_XSPI_ADDRESS_32_BITS             ((uint32_t)XSPI_CCR_ADSIZE)    /*!< 32-bit address */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode
+  * @{
+  */
+#define HAL_XSPI_ADDRESS_DTR_DISABLE         (0x00000000U)               /*!< DTR mode disabled for address phase */
+#define HAL_XSPI_ADDRESS_DTR_ENABLE          ((uint32_t)XSPI_CCR_ADDTR)  /*!< DTR mode enabled for address phase  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode
+  * @{
+  */
+#define HAL_XSPI_ALT_BYTES_NONE              (0x00000000U)                                        /*!< No alternate bytes               */
+#define HAL_XSPI_ALT_BYTES_1_LINE            ((uint32_t)XSPI_CCR_ABMODE_0)                        /*!< Alternate bytes on a single line */
+#define HAL_XSPI_ALT_BYTES_2_LINES           ((uint32_t)XSPI_CCR_ABMODE_1)                        /*!< Alternate bytes on two lines     */
+#define HAL_XSPI_ALT_BYTES_4_LINES           ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1))  /*!< Alternate bytes on four lines    */
+#define HAL_XSPI_ALT_BYTES_8_LINES           ((uint32_t)XSPI_CCR_ABMODE_2)                        /*!< Alternate bytes on eight lines   */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width
+  * @{
+  */
+#define HAL_XSPI_ALT_BYTES_8_BITS            (0x00000000U)                  /*!< 8-bit alternate bytes  */
+#define HAL_XSPI_ALT_BYTES_16_BITS           ((uint32_t)XSPI_CCR_ABSIZE_0)  /*!< 16-bit alternate bytes */
+#define HAL_XSPI_ALT_BYTES_24_BITS           ((uint32_t)XSPI_CCR_ABSIZE_1)  /*!< 24-bit alternate bytes */
+#define HAL_XSPI_ALT_BYTES_32_BITS           ((uint32_t)XSPI_CCR_ABSIZE)    /*!< 32-bit alternate bytes */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode
+  * @{
+  */
+#define HAL_XSPI_ALT_BYTES_DTR_DISABLE       (0x00000000U)               /*!< DTR mode disabled for alternate bytes phase */
+#define HAL_XSPI_ALT_BYTES_DTR_ENABLE        ((uint32_t)XSPI_CCR_ABDTR)  /*!< DTR mode enabled for alternate bytes phase  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_DataMode XSPI Data Mode
+  * @{
+  */
+#define HAL_XSPI_DATA_NONE                   (0x00000000U)                                      /*!< No data                                   */
+#define HAL_XSPI_DATA_1_LINE                 ((uint32_t)XSPI_CCR_DMODE_0)                       /*!< Data on a single line                     */
+#define HAL_XSPI_DATA_2_LINES                ((uint32_t)XSPI_CCR_DMODE_1)                       /*!< Data on two lines                         */
+#define HAL_XSPI_DATA_4_LINES                ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1))  /*!< Data on four lines                        */
+#define HAL_XSPI_DATA_8_LINES                ((uint32_t)XSPI_CCR_DMODE_2)                       /*!< Data on eight lines                       */
+#define HAL_XSPI_DATA_16_LINES               ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2))  /*!< Data on sixteen lines valid for HSPI only */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode
+  * @{
+  */
+#define HAL_XSPI_DATA_DTR_DISABLE            (0x00000000U)              /*!< DTR mode disabled for data phase */
+#define HAL_XSPI_DATA_DTR_ENABLE             ((uint32_t)XSPI_CCR_DDTR)  /*!< DTR mode enabled for data phase  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_DQSMode XSPI DQS Mode
+  * @{
+  */
+#define HAL_XSPI_DQS_DISABLE                 (0x00000000U)              /*!< DQS disabled */
+#define HAL_XSPI_DQS_ENABLE                  ((uint32_t)XSPI_CCR_DQSE)  /*!< DQS enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation
+  * @{
+  */
+#define HAL_XSPI_LATENCY_ON_WRITE            (0x00000000U)              /*!< Latency on write accesses    */
+#define HAL_XSPI_NO_LATENCY_ON_WRITE         ((uint32_t)XSPI_HLCR_WZL)  /*!< No latency on write accesses */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode
+  * @{
+  */
+#define HAL_XSPI_VARIABLE_LATENCY            (0x00000000U)             /*!< Variable initial latency */
+#define HAL_XSPI_FIXED_LATENCY               ((uint32_t)XSPI_HLCR_LM)  /*!< Fixed latency            */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space
+  * @{
+  */
+#define HAL_XSPI_MEMORY_ADDRESS_SPACE        (0x00000000U)                 /*!< HyperBus memory mode   */
+#define HAL_XSPI_REGISTER_ADDRESS_SPACE      ((uint32_t)XSPI_DCR1_MTYP_0)  /*!< HyperBus register mode */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_MatchMode XSPI Match Mode
+  * @{
+  */
+#define HAL_XSPI_MATCH_MODE_AND              (0x00000000U)            /*!< AND match mode between unmasked bits */
+#define HAL_XSPI_MATCH_MODE_OR               ((uint32_t)XSPI_CR_PMM)  /*!< OR match mode between unmasked bits  */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_AutomaticStop XSPI Automatic Stop
+  * @{
+  */
+#define HAL_XSPI_AUTOMATIC_STOP_DISABLE      (0x00000000U)             /*!< AutoPolling stops only with abort or XSPI disabling */
+#define HAL_XSPI_AUTOMATIC_STOP_ENABLE       ((uint32_t)XSPI_CR_APMS)  /*!< AutoPolling stops as soon as there is a match       */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation
+  * @{
+  */
+#define HAL_XSPI_TIMEOUT_COUNTER_DISABLE     (0x00000000U)             /*!< Timeout counter disabled, nCS remains active               */
+#define HAL_XSPI_TIMEOUT_COUNTER_ENABLE      ((uint32_t)XSPI_CR_TCEN)  /*!< Timeout counter enabled, nCS released when timeout expires */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_NoPrefetchAXI XSPI No Prefetch AXI
+  * @{
+  */
+#define HAL_XSPI_AXI_PREFETCH_ENABLE     (0x00000000U)             /*!< Prefetch is enabled for AXI signaled transactions               */
+#define HAL_XSPI_AXI_PREFETCH_DISABLE    ((uint32_t)XSPI_CR_NOPREF_AXI)  /*!< Prefetch is disable for AXI signaled transactions */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_NoPrefetchData XSPI No Prefetch Data
+  * @{
+  */
+#define HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE     (0x00000000U)           /*!< Automatic prefetch enabled                               */
+#define HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE    ((uint32_t)XSPI_CR_NOPREF)  /*!< Automatic prefetch disabled             */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_Flags XSPI Flags
+  * @{
+  */
+#define HAL_XSPI_FLAG_BUSY                   XSPI_SR_BUSY  /*!< Busy flag: operation is ongoing                                                                          */
+#define HAL_XSPI_FLAG_TO                     XSPI_SR_TOF   /*!< Timeout flag: timeout occurs in memory-mapped mode                                                       */
+#define HAL_XSPI_FLAG_SM                     XSPI_SR_SMF   /*!< Status match flag: received data matches in autopolling mode                                             */
+#define HAL_XSPI_FLAG_FT                     XSPI_SR_FTF   /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete              */
+#define HAL_XSPI_FLAG_TC                     XSPI_SR_TCF   /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
+#define HAL_XSPI_FLAG_TE                     XSPI_SR_TEF   /*!< Transfer error flag: invalid address is being accessed                                                   */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_Interrupts XSPI Interrupts
+  * @{
+  */
+#define HAL_XSPI_IT_TO                       XSPI_CR_TOIE  /*!< Interrupt on the timeout flag           */
+#define HAL_XSPI_IT_SM                       XSPI_CR_SMIE  /*!< Interrupt on the status match flag      */
+#define HAL_XSPI_IT_FT                       XSPI_CR_FTIE  /*!< Interrupt on the fifo threshold flag    */
+#define HAL_XSPI_IT_TC                       XSPI_CR_TCIE  /*!< Interrupt on the transfer complete flag */
+#define HAL_XSPI_IT_TE                       XSPI_CR_TEIE  /*!< Interrupt on the transfer error flag    */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_Timeout_definition XSPI Timeout definition
+  * @{
+  */
+#define HAL_XSPI_TIMEOUT_DEFAULT_VALUE       (5000U)  /* 5 s */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port
+  * @{
+  */
+#define HAL_XSPIM_IOPORT_1                 (0x00000000U)   /*!< Port 1 */
+#define HAL_XSPIM_IOPORT_2                 (0x00000001U)   /*!< Port 2 */
+/**
+  * @}
+  */
+
+
+/** @defgroup XSPI_DelayType XSPI Calibration Delay Type
+  * @{
+  */
+#define HAL_XSPI_CAL_FULL_CYCLE_DELAY      (0x00000000U)  /*!< Delay value equivalent to full memory-clock cycle                */
+#define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY    (0x00000001U)  /*!< Delay value for the feedback clock when reading without DQS      */
+#define HAL_XSPI_CAL_DATA_OUTPUT_DELAY     (0x00000002U)  /*!< Delay value for output data in DDR mode for write operations     */
+#define HAL_XSPI_CAL_DQS_INPUT_DELAY       (0x00000003U)  /*!< Delay value for DQS input when sampling data for read operations */
+/**
+  * @}
+  */
+
+/** @defgroup XSPIM_MemorySelect_Override XSPIM Memory Select Override
+  * @{
+  */
+#define HAL_XSPI_CSSEL_OVR_DISABLED         (0x00000000U)
+#define HAL_XSPI_CSSEL_OVR_NCS1             (0x00000010U)             /*!< The chip select signal from XSPI is sent to NCS1 */
+#define HAL_XSPI_CSSEL_OVR_NCS2             (0x00000070U)             /*!< The chip select signal from XSPI is sent to NCS2 */
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value
+  * @{
+  */
+#define HAL_XSPI_MAXCAL_NOT_REACHED        (0x00000000U)                   /*!< Memory-clock perido inside the range of DLL master                          */
+#define HAL_XSPI_MAXCAL_REACHED            ((uint32_t)XSPI_CALFCR_CALMAX)  /*!< Memory-clock period outside the range of DLL master (max delay values used) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup XSPI_Exported_Macros XSPI Exported Macros
+  * @{
+  */
+/** @brief Reset XSPI handle state.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @retval None
+  */
+#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                                  (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \
+                                                                  (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                               } while(0)
+#else
+#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_XSPI_STATE_RESET)
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+
+/** @brief  Enable the XSPI peripheral.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @retval None
+  */
+#define HAL_XSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN)
+
+/** @brief  Disable the XSPI peripheral.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @retval None
+  */
+#define HAL_XSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN)
+
+/** @brief  Enable the specified XSPI interrupt.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @param  __INTERRUPT__ specifies the XSPI interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
+  *            @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
+  *            @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
+  *            @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
+  *            @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
+  * @retval None
+  */
+#define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Disable the specified XSPI interrupt.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @param  __INTERRUPT__ specifies the XSPI interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
+  *            @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
+  *            @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
+  *            @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
+  *            @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
+  * @retval None
+  */
+#define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the specified XSPI interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @param  __INTERRUPT__ specifies the XSPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
+  *            @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
+  *            @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
+  *            @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
+  *            @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
+                                                           == (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the selected XSPI flag is set or not.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @param  __FLAG__ specifies the XSPI flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag
+  *            @arg HAL_XSPI_FLAG_TO:   XSPI Timeout flag
+  *            @arg HAL_XSPI_FLAG_SM:   XSPI Status match flag
+  *            @arg HAL_XSPI_FLAG_FT:   XSPI FIFO threshold flag
+  *            @arg HAL_XSPI_FLAG_TC:   XSPI Transfer complete flag
+  *            @arg HAL_XSPI_FLAG_TE:   XSPI Transfer error flag
+  * @retval None
+  */
+#define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
+                                                            != 0U) ? SET : RESET)
+
+/** @brief  Clears the specified XSPI's flag status.
+  * @param  __HANDLE__ specifies the XSPI Handle.
+  * @param  __FLAG__ specifies the XSPI clear register flag that needs to be set
+  *          This parameter can be one of the following values:
+  *            @arg HAL_XSPI_FLAG_TO:   XSPI Timeout flag
+  *            @arg HAL_XSPI_FLAG_SM:   XSPI Status match flag
+  *            @arg HAL_XSPI_FLAG_TC:   XSPI Transfer complete flag
+  *            @arg HAL_XSPI_FLAG_TE:   XSPI Transfer error flag
+  * @retval None
+  */
+#define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup XSPI_Exported_Functions XSPI Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef     HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi);
+HAL_StatusTypeDef     HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi);
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup XSPI_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* XSPI IRQ handler function */
+void                  HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi);
+
+/* XSPI command configuration functions */
+HAL_StatusTypeDef     HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd,
+                                       uint32_t Timeout);
+HAL_StatusTypeDef     HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd);
+HAL_StatusTypeDef     HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef     HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd,
+                                           uint32_t Timeout);
+
+/* XSPI indirect mode functions */
+HAL_StatusTypeDef     HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData);
+HAL_StatusTypeDef     HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
+HAL_StatusTypeDef     HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData);
+HAL_StatusTypeDef     HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
+
+/* XSPI status flag polling mode functions */
+HAL_StatusTypeDef     HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef     HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg);
+
+/* XSPI memory-mapped mode functions */
+HAL_StatusTypeDef     HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi,  XSPI_MemoryMappedTypeDef *const pCfg);
+
+/* Callback functions in non-blocking modes ***********************************/
+void                  HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi);
+
+/* XSPI indirect mode Callback functions */
+void                  HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi);
+void                  HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi);
+
+/* XSPI status flag polling mode functions */
+void                  HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi);
+
+/* XSPI memory-mapped mode functions */
+void                  HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi);
+
+#if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+/* XSPI callback registering/unregistering */
+HAL_StatusTypeDef     HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID,
+                                                pXSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+
+/**
+  * @}
+  */
+
+/* Peripheral Control and State functions  ************************************/
+/** @addtogroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions
+  * @{
+  */
+HAL_StatusTypeDef     HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi);
+HAL_StatusTypeDef     HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi);
+HAL_StatusTypeDef     HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold);
+uint32_t              HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi);
+HAL_StatusTypeDef     HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type);
+HAL_StatusTypeDef     HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size);
+HAL_StatusTypeDef     HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler);
+HAL_StatusTypeDef     HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout);
+uint32_t              HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi);
+uint32_t              HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi);
+
+/**
+  * @}
+  */
+
+/* XSPI IO Manager configuration function  ************************************/
+/** @addtogroup XSPI_Exported_Functions_Group4  IO Manager configuration function
+  * @{
+  */
+HAL_StatusTypeDef     HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/* XSPI high-speed interface and calibration functions  ***********************/
+/** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions
+  * @{
+  */
+HAL_StatusTypeDef     HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg);
+HAL_StatusTypeDef     HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/**
+  @cond 0
+  */
+#define IS_XSPI_FIFO_THRESHOLD_BYTE(THRESHOLD)    (((THRESHOLD) >= 1U) &&\
+                                                   ((THRESHOLD) <= ((XSPI_CR_FTHRES >> XSPI_CR_FTHRES_Pos)+1U)))
+#define IS_XSPI_MEMORY_MODE(MODE)                 (((MODE) == HAL_XSPI_SINGLE_MEM) || \
+                                                   ((MODE) == HAL_XSPI_DUAL_MEM))
+
+#define IS_XSPI_MEMORY_TYPE(TYPE)                 (((TYPE) == HAL_XSPI_MEMTYPE_MICRON)       || \
+                                                   ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX)     || \
+                                                   ((TYPE) == HAL_XSPI_MEMTYPE_APMEM)     || \
+                                                   ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \
+                                                   ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS)     || \
+                                                   ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS))
+
+#define IS_XSPI_MEMORY_SIZE(SIZE)                 (((SIZE) == HAL_XSPI_SIZE_16B)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_32B)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_64B)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_128B)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_256B)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_512B)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_1KB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_2KB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_4KB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_8KB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_16KB)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_32KB)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_64KB)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_128KB)    || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_256KB)    || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_512KB)    || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_1MB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_2MB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_4MB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_8MB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_16MB)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_32MB)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_64MB)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_128MB)    || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_256MB)    || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_512MB)    || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_1GB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_2GB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_4GB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_8GB)      || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_16GB)     || \
+                                                   ((SIZE) == HAL_XSPI_SIZE_32GB))
+
+#define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME)          (((TIME) >= 1U) && ((TIME) <= 64U))
+
+#define IS_XSPI_FREE_RUN_CLK(CLK)                 (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \
+                                                   ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE))
+
+#define IS_XSPI_CLOCK_MODE(MODE)                  (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \
+                                                   ((MODE) == HAL_XSPI_CLOCK_MODE_3))
+
+#define IS_XSPI_WRAP_SIZE(SIZE)                   (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \
+                                                   ((SIZE) == HAL_XSPI_WRAP_16_BYTES)      || \
+                                                   ((SIZE) == HAL_XSPI_WRAP_32_BYTES)      || \
+                                                   ((SIZE) == HAL_XSPI_WRAP_64_BYTES)      || \
+                                                   ((SIZE) == HAL_XSPI_WRAP_128_BYTES))
+
+#define IS_XSPI_CLK_PRESCALER(PRESCALER)          ((PRESCALER) <= 255U)
+
+#define IS_XSPI_SAMPLE_SHIFTING(CYCLE)            (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE)      || \
+                                                   ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE))
+
+#define IS_XSPI_DHQC(CYCLE)                       (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \
+                                                   ((CYCLE) == HAL_XSPI_DHQC_ENABLE))
+
+#define IS_XSPI_CS_BOUND(SIZE)                    (((SIZE) == HAL_XSPI_BONDARYOF_NONE)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_16B)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_32B)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_64B)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_128B)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_256B)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_512B)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_1KB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_2KB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_4KB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_8KB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_16KB)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_32KB)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_64KB)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_128KB)    || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_256KB)    || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_512KB)    || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_1MB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_2MB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_4MB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_8MB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_16MB)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_32MB)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_64MB)     || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_128MB)    || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_256MB)    || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_512MB)    || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_1GB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_2GB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_4GB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_8GB)      || \
+                                                   ((SIZE) == HAL_XSPI_BONDARYOF_16GB))
+
+
+#define IS_XSPI_MAXTRAN(NB_BYTES)                 ((NB_BYTES) <= 255U)
+
+#define IS_XSPI_CSSEL(CSSEL)                      (((CSSEL) == HAL_XSPI_CSSEL_NCS1) || \
+                                                   ((CSSEL) == HAL_XSPI_CSSEL_NCS2))
+
+#define IS_XSPI_EXTENDMEM(EXTENDMEM)              (((EXTENDMEM) == HAL_XSPI_CSSEL_SW) || \
+                                                   ((EXTENDMEM) == HAL_XSPI_CSSEL_HW))
+
+#define IS_XSPI_OPERATION_TYPE(TYPE)              (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \
+                                                   ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG)   || \
+                                                   ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG)  || \
+                                                   ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG))
+
+#define IS_XSPI_IO_SELECT(MEMSEL)                 (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0)   || \
+                                                   ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4)   || \
+                                                   ((MEMSEL) == HAL_XSPI_SELECT_IO_11_8)  || \
+                                                   ((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \
+                                                   ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0)   || \
+                                                   ((MEMSEL) == HAL_XSPI_SELECT_IO_15_8))
+
+#define IS_XSPI_INSTRUCTION(OPCODE)               ((OPCODE) <= 0xFFFFFFFFU)
+
+#define IS_XSPI_INSTRUCTION_MODE(MODE)            (((MODE) == HAL_XSPI_INSTRUCTION_NONE)    || \
+                                                   ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE)  || \
+                                                   ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \
+                                                   ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \
+                                                   ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES))
+
+#define IS_XSPI_INSTRUCTION_WIDTH(WIDTH)          (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS)  || \
+                                                   ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \
+                                                   ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \
+                                                   ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS))
+
+#define IS_XSPI_INSTRUCTION_DTR_MODE(MODE)        (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \
+                                                   ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
+
+#define IS_XSPI_ADDRESS_MODE(MODE)                (((MODE) == HAL_XSPI_ADDRESS_NONE)    || \
+                                                   ((MODE) == HAL_XSPI_ADDRESS_1_LINE)  || \
+                                                   ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \
+                                                   ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \
+                                                   ((MODE) == HAL_XSPI_ADDRESS_8_LINES))
+
+#define IS_XSPI_ADDRESS_WIDTH(WIDTH)              (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS)  || \
+                                                   ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \
+                                                   ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \
+                                                   ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS))
+
+#define IS_XSPI_ADDRESS_DTR_MODE(MODE)            (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \
+                                                   ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE))
+
+#define IS_XSPI_ALT_BYTES_MODE(MODE)              (((MODE) == HAL_XSPI_ALT_BYTES_NONE)    || \
+                                                   ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE)  || \
+                                                   ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \
+                                                   ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \
+                                                   ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES))
+
+#define IS_XSPI_ALT_BYTES_WIDTH(WIDTH)            (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS)  || \
+                                                   ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \
+                                                   ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \
+                                                   ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS))
+
+#define IS_XSPI_ALT_BYTES_DTR_MODE(MODE)          (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \
+                                                   ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE))
+
+#define IS_XSPI_DATA_MODE(TYPE,MODE)              (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \
+                                                   (((MODE) == HAL_XSPI_DATA_NONE)    || \
+                                                    ((MODE) == HAL_XSPI_DATA_8_LINES) || \
+                                                    ((MODE) == HAL_XSPI_DATA_16_LINES)): \
+                                                   (((MODE) == HAL_XSPI_DATA_NONE)    || \
+                                                    ((MODE) == HAL_XSPI_DATA_1_LINE)  || \
+                                                    ((MODE) == HAL_XSPI_DATA_2_LINES) || \
+                                                    ((MODE) == HAL_XSPI_DATA_4_LINES) || \
+                                                    ((MODE) == HAL_XSPI_DATA_8_LINES) || \
+                                                    ((MODE) == HAL_XSPI_DATA_16_LINES)))
+#define IS_XSPI_DATA_LENGTH(NUMBER)               ((NUMBER) >= 1U)
+
+#define IS_XSPI_DATA_DTR_MODE(MODE)               (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \
+                                                   ((MODE) == HAL_XSPI_DATA_DTR_ENABLE))
+
+#define IS_XSPI_DUMMY_CYCLES(NUMBER)              ((NUMBER) <= 31U)
+
+#define IS_XSPI_DQS_MODE(MODE)                    (((MODE) == HAL_XSPI_DQS_DISABLE) || \
+                                                   ((MODE) == HAL_XSPI_DQS_ENABLE))
+
+#define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE)     ((CYCLE) <= 255U)
+
+#define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE)          ((CYCLE) <= 255U)
+
+#define IS_XSPI_WRITE_ZERO_LATENCY(MODE)          (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \
+                                                   ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE))
+
+#define IS_XSPI_LATENCY_MODE(MODE)                (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \
+                                                   ((MODE) == HAL_XSPI_FIXED_LATENCY))
+
+#define IS_XSPI_ADDRESS_SPACE(SPACE)              (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \
+                                                   ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE))
+
+#define IS_XSPI_MATCH_MODE(MODE)                  (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \
+                                                   ((MODE) == HAL_XSPI_MATCH_MODE_OR))
+
+#define IS_XSPI_AUTOMATIC_STOP(MODE)              (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \
+                                                   ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE))
+
+#define IS_XSPI_INTERVAL(INTERVAL)                ((INTERVAL) <= 0xFFFFU)
+
+#define IS_XSPI_STATUS_BYTES_SIZE(SIZE)           (((SIZE) >= 1U) && ((SIZE) <= 4U))
+
+#define IS_XSPI_TIMEOUT_ACTIVATION(MODE)          (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \
+                                                   ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE))
+#define IS_XSPI_NO_PREFETCH_DATA(MODE)            (((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE) || \
+                                                   ((MODE) == HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE))
+
+#define IS_XSPI_NO_PREFETCH_AXI(MODE)             (((MODE) == HAL_XSPI_AXI_PREFETCH_ENABLE) || \
+                                                   ((MODE) == HAL_XSPI_AXI_PREFETCH_DISABLE))
+
+#define IS_XSPI_TIMEOUT_PERIOD(PERIOD)            ((PERIOD) <= 0xFFFFU)
+
+#define IS_XSPIM_IO_PORT(PORT)                    (((PORT) == HAL_XSPIM_IOPORT_1)   || \
+                                                   ((PORT) == HAL_XSPIM_IOPORT_2))
+
+#define IS_XSPIM_NCS_OVR(PORT)                    (((PORT) == HAL_XSPI_CSSEL_OVR_DISABLED) || \
+                                                   ((PORT) == HAL_XSPI_CSSEL_OVR_NCS1)     || \
+                                                   ((PORT) == HAL_XSPI_CSSEL_OVR_NCS2))
+
+#define IS_XSPIM_REQ2ACKTIME(TIME)                (((TIME) >= 1U) && ((TIME) <= 256U))
+
+#define IS_XSPI_DELAY_TYPE(TYPE)                  (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY)   || \
+                                                   ((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \
+                                                   ((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY)  || \
+                                                   ((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY))
+
+#define IS_XSPI_FINECAL_VALUE(VALUE)              ((VALUE) <= 0x7FU)
+
+#define IS_XSPI_COARSECAL_VALUE(VALUE)            ((VALUE) <= 0x1FU)
+
+/**
+  @endcond
+  */
+
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* XSPI || XSPI1 || XSPI2 || XSPI3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_HAL_XSPI_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_adc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_adc.h
new file mode 100644
index 000000000..abfa8a4e4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_adc.h
@@ -0,0 +1,7588 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_ADC_H
+#define STM32N6xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2)
+
+/** @defgroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Internal mask for ADC group regular sequencer:                             */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+/* - sequencer register offset                                                */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET                 (0x00000000UL)
+#define ADC_SQR2_REGOFFSET                 (0x00000100UL)
+#define ADC_SQR3_REGOFFSET                 (0x00000200UL)
+#define ADC_SQR4_REGOFFSET                 (0x00000300UL)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+                                            | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
+#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted  */
+/* into ADC group regular sequencer ranks literals definition.                */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ1_Pos)
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ2_Pos)
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ3_Pos)
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ4_Pos)
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ5_Pos)
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ6_Pos)
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ7_Pos)
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ8_Pos)
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ9_Pos)
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
+
+
+/* Internal mask for ADC group injected sequencer:                            */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
+/* - data register offset                                                     */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET                 (0x00000000UL)
+#define ADC_JDR2_REGOFFSET                 (0x00000100UL)
+#define ADC_JDR3_REGOFFSET                 (0x00000200UL)
+#define ADC_JDR4_REGOFFSET                 (0x00000300UL)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+                                            | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_NUMBER_MASK_POSBIT0)
+#define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition.               */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
+
+/* Internal mask for ADC group regular trigger:                               */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+/* - regular trigger source                                                   */
+/* - regular trigger edge                                                     */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT   (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting
+                                                               for compatibility with some ADC on other STM32
+                                                               series having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
+                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 1UL)) | \
+                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 2UL)) | \
+                                             ((ADC_CFGR1_EXTSEL)                            << (4U * 3UL))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
+
+/* Definition of ADC group regular trigger bits information.                  */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (ADC_CFGR1_EXTSEL_Pos)
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR1_EXTEN_Pos)
+
+
+/* Internal mask for ADC group injected trigger:                              */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
+/* - injected trigger source                                                  */
+/* - injected trigger edge                                                    */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
+                                                                  compatibility with some ADC on other STM32 series
+                                                                  having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
+
+/* Definition of ADC group injected trigger bits information.                 */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (ADC_JSQR_JEXTSEL_Pos)
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
+
+
+/* Internal mask for ADC channel:                                             */
+/* To select into literal ADC_CHANNEL_LUT[] the relevant bits for:         */
+/* - channel identifier defined by bitfield                                   */
+/* - channel sampling time defined by SMPRx register offset                   */
+/*   and SMPx bits positions into SMPRx register                              */
+
+#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB */
+#define ADC_CHANNEL_NUMBER_MASK_POSBIT0    (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
+                                                             >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in
+                                                             register]) */
+
+/* Channel differentiation between external channels (connected to GPIO pins)  */
+/* and internal channels (connected to internal paths)                         */
+#define ADC_CHANNEL_EXTERNAL               (0x00000000UL) /* Marker of external channel */
+#define ADC_CHANNEL_INTERNAL_ADC1          (0x00000400UL) /* Marker of internal channel of ADC1 */
+#define ADC_CHANNEL_INTERNAL_ADC2          (0x00000800UL) /* Marker of internal channel of ADC2 */
+
+#define ADC_CHANNEL_NONE                   (0xFFU)        /* Channel literal used for non connected channels */
+#define ADC_CHANNEL_NUMBER_MASK            (0x0000001FUL) /* Mask of channel number region in LL_ADC_CHANNEL_X
+                                                             bitfield (values as decimal number in range [0; 255]) */
+#define ADC_CHANNEL_INTERNAL_MASK          (0x0000FF00UL) /* Mask of internal channel region in LL_ADC_CHANNEL_X
+                                                             bitfield (values as bitfield for each config) */
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET                (0x00000000UL)
+#define ADC_SMPR2_REGOFFSET                (0x02000000UL)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+#define ADC_SMPRX_REGOFFSET_POS            (25UL)           /* Position of bits ADC_SMPRx_REGOFFSET
+                                                               in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
+                                                               position in register */
+
+/* Definition of channels ID bitfield information to be inserted into         */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
+#define ADC_CHANNEL_19_BITFIELD            (ADC_AWD2CR_AWD2CH_19)
+
+/* Definition of channels sampling time information to be inserted into       */
+/* channels literals definition.                                              */
+/* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position         */
+/* in register.                                                               */
+#define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+
+/* Definition of ADC channel look up table containing channels information */
+static const uint32_t ADC_CHANNEL_LUT[] =
+{
+  (ADC_CHANNEL_0_SMP   | ADC_CHANNEL_0_BITFIELD),    /*!< ADC channel ADCx_IN0  */
+  (ADC_CHANNEL_1_SMP   | ADC_CHANNEL_1_BITFIELD),    /*!< ADC channel ADCx_IN1  */
+  (ADC_CHANNEL_2_SMP   | ADC_CHANNEL_2_BITFIELD),    /*!< ADC channel ADCx_IN2  */
+  (ADC_CHANNEL_3_SMP   | ADC_CHANNEL_3_BITFIELD),    /*!< ADC channel ADCx_IN3  */
+  (ADC_CHANNEL_4_SMP   | ADC_CHANNEL_4_BITFIELD),    /*!< ADC channel ADCx_IN4  */
+  (ADC_CHANNEL_5_SMP   | ADC_CHANNEL_5_BITFIELD),    /*!< ADC channel ADCx_IN5  */
+  (ADC_CHANNEL_6_SMP   | ADC_CHANNEL_6_BITFIELD),    /*!< ADC channel ADCx_IN6  */
+  (ADC_CHANNEL_7_SMP   | ADC_CHANNEL_7_BITFIELD),    /*!< ADC channel ADCx_IN7  */
+  (ADC_CHANNEL_8_SMP   | ADC_CHANNEL_8_BITFIELD),    /*!< ADC channel ADCx_IN9  */
+  (ADC_CHANNEL_9_SMP   | ADC_CHANNEL_9_BITFIELD),    /*!< ADC channel ADCx_IN8  */
+  (ADC_CHANNEL_10_SMP  | ADC_CHANNEL_10_BITFIELD),   /*!< ADC channel ADCx_IN10 */
+  (ADC_CHANNEL_11_SMP  | ADC_CHANNEL_11_BITFIELD),   /*!< ADC channel ADCx_IN11 */
+  (ADC_CHANNEL_12_SMP  | ADC_CHANNEL_12_BITFIELD),   /*!< ADC channel ADCx_IN12 */
+  (ADC_CHANNEL_13_SMP  | ADC_CHANNEL_13_BITFIELD),   /*!< ADC channel ADCx_IN13 */
+  (ADC_CHANNEL_14_SMP  | ADC_CHANNEL_14_BITFIELD),   /*!< ADC channel ADCx_IN14 */
+  (ADC_CHANNEL_15_SMP  | ADC_CHANNEL_15_BITFIELD),   /*!< ADC channel ADCx_IN15 */
+  (ADC_CHANNEL_16_SMP  | ADC_CHANNEL_16_BITFIELD),   /*!< ADC channel ADCx_IN16 */
+  (ADC_CHANNEL_17_SMP  | ADC_CHANNEL_17_BITFIELD),   /*!< ADC channel ADCx_IN17 */
+  (ADC_CHANNEL_18_SMP  | ADC_CHANNEL_18_BITFIELD),   /*!< ADC channel ADCx_IN18 */
+  (ADC_CHANNEL_19_SMP  | ADC_CHANNEL_19_BITFIELD),   /*!< ADC channel ADCx_IN19 */
+};
+
+
+/* Internal mask for ADC mode single or differential ended:                   */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
+/* the relevant bits for:                                                     */
+/* (concatenation of multiple bits used in different registers)               */
+/* - ADC calibration: calibration start, calibration factor get or set        */
+/* - ADC channels: set each ADC channel ending mode                           */
+#define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
+                                            to perform of shift when single mode is selected, shift value out of
+                                            channels bits range. */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
+                                            mask of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)         /* Selection of 1 bit to discriminate differential mode:
+                                            position of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
+                                            ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
+
+/* Internal mask for ADC analog watchdog:                                     */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+/* (concatenation of multiple bits used in different analog watchdogs,        */
+/* (feature of several watchdogs not available on all STM32 series)).       */
+/* - analog watchdog 1: monitored channel defined by number,                  */
+/*   selection of ADC group (ADC groups regular and-or injected).             */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
+/*   selection on groups.                                                     */
+
+/* Definition of channels ID number information to be inserted into           */
+/* analog watchdog channels literals definition.                              */
+#define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
+#define ADC_CHANNEL_1_NUMBER               (ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER               (ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER               (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER               (ADC_CFGR1_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER               (ADC_CFGR1_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER               (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
+                                            ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR1_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_19_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+
+#define ADC_AWD_CHANNEL_NUMBER_MASK           (ADC_CFGR1_AWD1CH)
+#define ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS  (ADC_CFGR1_AWD1CH_Pos)
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
+#define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
+#define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+#define ADC_AWD_CRX_REGOFFSET_POS          (20UL)                      /* Position of bits ADC_AWD_CRx_REGOFFSET
+                                                                          in ADC_AWD_CRX_REGOFFSET_MASK */
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)      /* Position of bits ADC_SQRx_REGOFFSET
+                                                                               in ADC_AWD_TRX_REGOFFSET_MASK */
+#define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate
+                                                                               threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate
+                                                                               threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
+                                                                               position to perform a shift of 4 ranks */
+
+/* Internal mask for ADC offset:                                              */
+/* Internal register offset for ADC offset instance configuration */
+#define ADC_OFR1_REGOFFSET                 (0x00000000UL)
+#define ADC_OFR2_REGOFFSET                 (0x00000001UL)
+#define ADC_OFR3_REGOFFSET                 (0x00000002UL)
+#define ADC_OFR4_REGOFFSET                 (0x00000003UL)
+#define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+                                            | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADEN | ADC_CR_ADDIS        \
+                                            | ADC_CR_JADSTART | ADC_CR_JADSTP \
+                                            | ADC_CR_ADSTART | ADC_CR_ADSTP)            /* ADC register CR bits with
+                                           HW property "rs": Software can read as well as set this bit.
+                                           Writing '0' has no effect on the bit value. */
+
+/* Internal mask for ADC channel internal path*/
+#define ADC_COMMON_PATH_INTERNAL_MASK      (0x7UL << ADC_CCR_VREFEN_Pos)        /*!< ADC measurement path to internal
+                                            channel mask in LL_ADC_CHANNEL bitfield */
+#define ADC_PATH_INTERNAL_POS              (16UL)                               /*!< ADC measurement path to internal
+                                            channel position in LL_ADC_CHANNEL bitfield */
+#define ADC_PATH_INTERNAL_MASK             (0x3UL << ADC_PATH_INTERNAL_POS)  /*!< ADC measurement path to internal
+                                            channel mask in LL_ADC_CHANNEL bitfield */
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x460091B8UL)) /* Internal voltage reference, address of
+                                           parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
+                                           (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV).
+                                           On this STM32 series, it is required to load the OTP110 word before reading
+                                           this address.
+                                           In case of usage with HAL driver, refer to HAL_BSEC_OTP_Reload() */
+#define VREFINT_CAL_VREF                   (1800UL)                     /* Analog voltage reference (Vref+) value
+                                           with which VrefInt has been calibrated in production
+                                           (tolerance: +-10 mV) (unit: mV). */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+  * @{
+  */
+/* Macro reserved for internal LL driver usage, not intended to be used in    */
+/* code of final user.                                                        */
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+  */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+  * @brief Getter to access the ADC instance corresponding index in
+  *        differential channel look up table
+  * @param __INSTANCE__ ADC instance
+  * @retval Look-up table index related to __INSTANCE__
+  */
+#define __ADC_INSTANCE_INDEX(__INSTANCE__)          \
+  ( ((__INSTANCE__) == ADC1)                        \
+    ?                                               \
+    (0UL)                                           \
+    :                                               \
+    (1UL)                                           \
+  )
+
+#define __ADC_CHANNEL_INDEX(__CHANNEL__)                                                \
+  ((__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_0 )) ?  0UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_1 )) ?  1UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_2 )) ?  2UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_3 )) ?  3UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_4 )) ?  4UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_5 )) ?  5UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_6 )) ?  6UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_7 )) ?  7UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_8 )) ?  8UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_9 )) ?  9UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_10)) ? 10UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_11)) ? 11UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_12)) ? 12UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_13)) ? 13UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_14)) ? 14UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_15)) ? 15UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_16)) ? 16UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_17)) ? 17UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_18)) ? 18UL : \
+   (__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) == (LL_ADC_CHANNEL_19)) ? 19UL : 0UL)
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of ADC common parameters
+  *         and multimode
+  *         (all ADC instances belonging to the same ADC common instance).
+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+  *         is conditioned to ADC instances state (all ADC instances
+  *         sharing the same ADC common instance):
+  *         All ADC instances sharing the same ADC common instance must be
+  *         disabled.
+  */
+typedef struct
+{
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode
+                                             (for devices with several ADC instances).
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetMultimode(). */
+
+  uint32_t MultiDataFormat;             /*!< Set ADC multimode conversion data format of ADC group regular: conversion
+                                             data in data register of each ADC instance or ADC common instance.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DATA_FORMAT
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetMultiDataFormat(). */
+
+  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
+                                             Relevant only for multimode modes: interleaved based modes.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 series).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t Resolution;                  /*!< Set ADC resolution.
+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetResolution(). */
+
+  uint32_t LeftBitShift;                /*!< Configures the left shifting applied to the final result with or without
+                                             oversampling.
+                                             This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
+
+  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetLPModeAutoWait(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or
+                                             from external peripheral (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting trigger source to external trigger also
+                                                   set trigger polarity to rising edge(default setting for compatibility
+                                                   with some ADC on other STM32 series having this setting set by HW
+                                                   default value).
+                                                   In case of need to modify trigger edge, use function
+                                                   @ref LL_ADC_REG_SetTriggerEdge().
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
+                                             and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group regular sequencer is
+                                                   enabled (scan length of 2 ranks or more).
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
+                                             conversions are performed in single mode (one conversion per trigger) or in
+                                             continuous mode (after the first trigger, following conversions launched
+                                             successively automatically).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+                                             Note: It is not possible to enable both ADC group regular continuous mode
+                                                   and discontinuous mode.
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetContinuousMode(). */
+
+  uint32_t DataTransferMode;            /*!< Set ADC group regular conversion data transfer: no transfer, transfer
+                                             by DMA or other peripherals.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetDataTransferMode(). */
+
+  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+                                             data preserved or overwritten.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start)
+                                             or from external peripheral (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting trigger source to external trigger also
+                                                   set trigger polarity to rising edge (default setting for
+                                                   compatibility with some ADC on other STM32 series having this
+                                                   setting set by HW default value).
+                                                   In case of need to modify trigger edge, use function
+                                                   @ref LL_ADC_INJ_SetTriggerEdge().
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
+                                             and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group injected sequencer is
+                                                   enabled (scan length of 2 ranks or more).
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group
+                                             regular.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+                                             Note: This parameter must be set to set to independent trigger if injected
+                                                   trigger source is set to an external trigger.
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+  * @{
+  */
+#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary
+                                           conversion */
+#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence
+                                           conversions */
+#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary
+                                           conversion */
+#define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence
+                                           conversions */
+#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of
+                                           unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of
+                                           unitary conversion */
+#define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of
+                                           sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of
+                                           sequence conversions */
+#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular
+                                           overrun */
+#define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular
+                                           overrun */
+#define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of
+                                           sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of
+                                           sampling phase */
+#define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of
+                                           unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of
+                                           unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of
+                                           sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of
+                                           sequence conversions */
+#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1
+                                           of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1
+                                           of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2
+                                           of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2
+                                           of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3
+                                           of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3
+                                           of the ADC slave */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+  * @{
+  */
+#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary
+                                           conversion */
+#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence
+                                           conversions */
+#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling
+                                           phase */
+#define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary
+                                           conversion */
+#define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence
+                                           conversions */
+#define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+  * @{
+  */
+/* List of ADC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+#define LL_ADC_DMA_REG_REGULAR_DATA        (0x00000000UL) /*!< ADC group regular conversion data register
+                                           (corresponding to register DR) to be used with ADC configured in independent
+                                           mode. Without DMA transfer, register accessed by LL function
+                                           @ref LL_ADC_REG_ReadConversionData32() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_MULTI_NO_PACKING (0x00000001UL) /*!< ADC group regular conversion data register
+                                           to be used with ADC configured in multimode (available on STM32 devices
+                                           with several ADC instances), without data packing.
+                                           Register used is CDR2, compliant with all ADC multimode data format
+                                           and data width, refer to description of literals in
+                                           @ref ADC_LL_EC_MULTI_DATA_FORMAT.
+                                           Without DMA transfer, register accessed by LL function
+                                           @ref LL_ADC_REG_ReadMultiConvNoPacking() */
+#define LL_ADC_DMA_REG_REGULAR_MULTI_PACKING    (0x00000002UL) /*!< ADC group regular conversion data register
+                                           to be used with ADC configured in multimode (available on STM32 devices
+                                           with several ADC instances), with data packing.
+                                           Register used is CDR, usable under conditions of ADC multimode data format
+                                           selected and data width, refer to description of literals in
+                                           @ref ADC_LL_EC_MULTI_DATA_FORMAT.
+                                           Without DMA transfer, register accessed by LL function
+                                           @ref LL_ADC_REG_ReadMultiConvPacking() */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)       /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)     /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)     /*!< ADC measurement path to internal channel Vbat    */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_PATH_INTERNAL  ADC instance - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_VDDCORE       (ADC_OR_OP2 << ADC_PATH_INTERNAL_POS)            /*!< ADC measurement path
+                                            to internal channel VddCore */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR1_RES_0)  /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR1_RES_1                 )  /*!< ADC resolution  8 bits */
+#define LL_ADC_RESOLUTION_6B               (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT   ADC left Shift
+  * @{
+  */
+#define LL_ADC_LEFT_BIT_SHIFT_NONE  (0x00000000UL)                                                                       /*!< ADC no bit shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_1     (ADC_CFGR2_LSHIFT_0)                                                                 /*!< ADC 1 bit shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_2     (ADC_CFGR2_LSHIFT_1)                                                                 /*!< ADC 2 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_3     (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 3 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_4     (ADC_CFGR2_LSHIFT_2)                                                                 /*!< ADC 4 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_5     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 5 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_6     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 6 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_7     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 7 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_8     (ADC_CFGR2_LSHIFT_3)                                                                 /*!< ADC 8 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_9     (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 9 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_10    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 10 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_11    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 11 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_12    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)                                            /*!< ADC 12 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_13    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 13 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_14    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                       /*!< ADC 14 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_15    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)  /*!< ADC 15 bits shift left applied on the final ADC conversion data */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+  * @{
+  */
+#define LL_ADC_LP_AUTOWAIT_DISABLE         (0x00000000UL)     /*!< ADC low power mode auto delay disabled. */
+#define LL_ADC_LP_AUTOWAIT_ENABLE          (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay enabled: dynamic
+                                           low power mode, ADC conversions are performed only when necessary
+                                           (when previous ADC conversion data is read).
+                                           See description with function @ref LL_ADC_SetLPModeAutoWait(). */
+/**
+  * @}
+  */
+/* Definitions for backward compatibility with legacy STM32 series */
+#define LL_ADC_LP_MODE_NONE LL_ADC_LP_AUTOWAIT_DISABLE
+#define LL_ADC_LP_AUTOWAIT  LL_ADC_LP_AUTOWAIT_ENABLE
+
+/** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset instance
+  * @{
+  */
+#define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
+to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
+to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
+to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
+to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
+  * @{
+  */
+#define LL_ADC_OFFSET_SIGNED_SAT_DISABLE   (0x00000000UL)     /*!< ADC offset signed saturation is disabled */
+#define LL_ADC_OFFSET_SIGNED_SAT_ENABLE    (ADC_OFCFGR1_SSAT) /*!< ADC offset signed saturation is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_UNSIGNED_SATURATION ADC instance - Offset unsigned saturation mode
+  * @{
+  */
+#define LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE   (0x00000000UL)     /*!< ADC offset unsigned saturation is disabled */
+#define LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE    (ADC_OFCFGR1_USAT) /*!< ADC offset unsigned saturation is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+  * @{
+  */
+#define LL_ADC_OFFSET_SIGN_NEGATIVE        (0x00000000UL)       /*!< ADC offset is negative */
+#define LL_ADC_OFFSET_SIGN_POSITIVE        (ADC_OFCFGR1_POSOFF) /*!< ADC offset is positive */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define LL_ADC_GROUP_REGULAR               (0x00000001UL)     /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED              (0x00000002UL)     /*!< ADC group injected (not available on all STM32
+                                                                   devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL)     /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define LL_ADC_CHANNEL_0            ( 0UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN0  */
+#define LL_ADC_CHANNEL_1            ( 1UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN1  */
+#define LL_ADC_CHANNEL_2            ( 2UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN2  */
+#define LL_ADC_CHANNEL_3            ( 3UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN3  */
+#define LL_ADC_CHANNEL_4            ( 4UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN4  */
+#define LL_ADC_CHANNEL_5            ( 5UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN5  */
+#define LL_ADC_CHANNEL_6            ( 6UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN6  */
+#define LL_ADC_CHANNEL_7            ( 7UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN7  */
+#define LL_ADC_CHANNEL_8            ( 8UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN8  */
+#define LL_ADC_CHANNEL_9            ( 9UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN9  */
+#define LL_ADC_CHANNEL_10           (10UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN10 */
+#define LL_ADC_CHANNEL_11           (11UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN11 */
+#define LL_ADC_CHANNEL_12           (12UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN12 */
+#define LL_ADC_CHANNEL_13           (13UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN13 */
+#define LL_ADC_CHANNEL_14           (14UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN14 */
+#define LL_ADC_CHANNEL_15           (15UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN15 */
+#define LL_ADC_CHANNEL_16           (16UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN16 */
+#define LL_ADC_CHANNEL_17           (17UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN17 */
+#define LL_ADC_CHANNEL_18           (18UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN18 */
+#define LL_ADC_CHANNEL_19           (19UL | ADC_CHANNEL_EXTERNAL | LL_ADC_PATH_INTERNAL_NONE)  /*!< Channel ADCx_IN19 */
+#define LL_ADC_CHANNEL_VREFINT      (17UL \
+                                     | ADC_CHANNEL_INTERNAL_ADC1 \
+                                     | LL_ADC_PATH_INTERNAL_VREFINT)                           /*!< ADC internal channel
+                                     connected to VrefInt: Internal voltage reference.
+                                     On this STM32 series, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_VBAT         (16UL \
+                                     | ADC_CHANNEL_INTERNAL_ADC2 \
+                                     | LL_ADC_PATH_INTERNAL_VBAT)                              /*!< ADC internal channel
+                                     connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have
+                                     channel voltage always below Vdda.
+                                     On this STM32 series, ADC channel available only on ADC instance: ADC2. */
+#define LL_ADC_CHANNEL_VDDCORE      (17UL \
+                                     | ADC_CHANNEL_INTERNAL_ADC2 \
+                                     | LL_ADC_PATH_INTERNAL_VDDCORE)                           /*!< ADC internal channel
+                                     connected to VddCore.
+                                     On this STM32 series, ADC channel available only on ADC instance: ADC2. */
+static const uint8_t ADC_CHANNEL_DIFF_LUT[2][20] =
+{
+  {
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN0  -> VREF-       */
+    (uint8_t)(LL_ADC_CHANNEL_0),        /*!< Channel ADCx_INN1  -> ADCx_INP0   */
+    (uint8_t)(LL_ADC_CHANNEL_6),        /*!< Channel ADCx_INN2  -> ADCx_INP6   */
+    (uint8_t)(LL_ADC_CHANNEL_7),        /*!< Channel ADCx_INN3  -> ADCx_INP7   */
+    (uint8_t)(LL_ADC_CHANNEL_8),        /*!< Channel ADCx_INN4  -> ADCx_INP8   */
+    (uint8_t)(LL_ADC_CHANNEL_9),        /*!< Channel ADCx_INN5  -> ADCx_INP9   */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN6  -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN7  -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN8  -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN9  -> VREF-       */
+    (uint8_t)(LL_ADC_CHANNEL_11),       /*!< Channel ADCx_INN10 -> ADCx_INP11  */
+    (uint8_t)(LL_ADC_CHANNEL_12),       /*!< Channel ADCx_INN11 -> ADCx_INP12  */
+    (uint8_t)(LL_ADC_CHANNEL_13),       /*!< Channel ADCx_INN12 -> ADCx_INP13  */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN13 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN14 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN15 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN16 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN17 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN18 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE)         /*!< Channel ADCx_INN19 -> VREF-       */
+  },
+  {
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN0  -> VREF-       */
+    (uint8_t)(LL_ADC_CHANNEL_0),        /*!< Channel ADCx_INN1  -> ADCx_INP0   */
+    (uint8_t)(LL_ADC_CHANNEL_6),        /*!< Channel ADCx_INN2  -> ADCx_INP6   */
+    (uint8_t)(LL_ADC_CHANNEL_7),        /*!< Channel ADCx_INN3  -> ADCx_INP7   */
+    (uint8_t)(LL_ADC_CHANNEL_8),        /*!< Channel ADCx_INN4  -> ADCx_INP8   */
+    (uint8_t)(LL_ADC_CHANNEL_9),        /*!< Channel ADCx_INN5  -> ADCx_INP9   */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN6  -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN7  -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN8  -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN9  -> VREF-       */
+    (uint8_t)(LL_ADC_CHANNEL_11),       /*!< Channel ADCx_INN10 -> ADCx_INP11  */
+    (uint8_t)(LL_ADC_CHANNEL_12),       /*!< Channel ADCx_INN11 -> ADCx_INP12  */
+    (uint8_t)(LL_ADC_CHANNEL_13),       /*!< Channel ADCx_INN12 -> ADCx_INP13  */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN13 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN14 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN15 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN16 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN17 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE),        /*!< Channel ADCx_INN18 -> VREF-       */
+    (uint8_t)(ADC_CHANNEL_NONE)         /*!< Channel ADCx_INN19 -> VREF-       */
+  }
+};
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                         /*!< ADC group regular
+                                           conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: external interrupt line 11.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 channel 1 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 channel 2 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 channel 3 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 TRGO2 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM2 channel 2 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
+                                            | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM2 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM3 channel 4 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 \
+                                            | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM3 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM4 channel 4 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM4 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM5_TRGO      (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM5 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM6 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO      (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM7 TRGO event. Trigger edge
+                                           set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_0 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM8 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM8 TRGO2 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM9_CH1       (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 \
+                                            | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM9 channel 1 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM9_TRGO      (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM9 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM12_TRGO     (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM12 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM15 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM18_TRGO     (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 \
+                                            | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM18 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1     (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_3 \
+                                            | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular
+                                           conversion trigger from external peripheral: LPTIM1 channel 1 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1     (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_3 \
+                                            | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: LPTIM2 channel 2 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1     (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_3 \
+                                            | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                           conversion trigger from external peripheral: LPTIM3 channel 3 event.
+                                           Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+  * @{
+  */
+#define LL_ADC_REG_TRIG_EXT_RISING         (ADC_CFGR1_EXTEN_0)                     /*!< ADC group regular conversion
+                                           trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR1_EXTEN_1)                     /*!< ADC group regular conversion
+                                           trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
+                                           trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE  ADC group regular - Sampling mode
+  * @{
+  */
+#define LL_ADC_REG_SAMPLING_MODE_NORMAL    (0x00000000UL)     /*!< ADC conversions sampling phase duration
+                                           is defined using  @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. */
+#define LL_ADC_REG_SAMPLING_MODE_BULB      (ADC_CFGR2_BULB)   /*!< ADC conversions sampling phase starts immediately
+                                           after end of conversion, and stops upon trigger event.
+                                           Note: First conversion is using minimal sampling time
+                                           (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME). */
+#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED  (ADC_CFGR2_SMPTRIG)/*!< ADC conversions sampling phase is controlled
+                                           by trigger events: Trigger rising edge  = start sampling,
+                                           Trigger falling edge = stop sampling and start conversion. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+  * @{
+  */
+#define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)     /*!< ADC conversions performed in single mode:
+                                           one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR1_CONT)   /*!< ADC conversions performed in continuous mode:
+                                           after the first trigger, following conversions launched successively
+                                           automatically */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER  ADC group regular - Data transfer mode of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DR_TRANSFER             (0x00000000UL)       /*!< ADC conversions data are available
+                                           in ADC data register only */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (ADC_CFGR1_DMNGT_0)  /*!< ADC conversion data are transferred by DMA,
+                                           in limited mode (one shot mode): DMA transfer requests are stopped when
+                                           number of DMA data transfers (number of ADC conversions) is reached.
+                                           This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR1_DMNGT_1 \
+                                            | ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA,
+                                           in unlimited mode: DMA transfer requests are unlimited, whatever
+                                           number of DMA data transferred (number of ADC conversions).
+                                           This ADC mode is intended to be used with DMA mode circular. */
+#define LL_ADC_REG_MDF_TRANSFER            (ADC_CFGR1_DMNGT_1)  /*!< ADC conversion data are transferred to MDF */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)     /*!< ADC group regular behavior in case of overrun:
+                                                                   data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
+                                                                   data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                 /*!< ADC group regular sequencer disable
+                                           (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (ADC_SQR1_L_0)                 /*!< ADC group regular sequencer enable
+                                           with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (ADC_SQR1_L_1)                 /*!< ADC group regular sequencer enable
+                                           with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (ADC_SQR1_L_1 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
+                                           with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (ADC_SQR1_L_2)                 /*!< ADC group regular sequencer enable
+                                           with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
+                                           with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
+                                           with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
+                                            | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
+                                           with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3)                 /*!< ADC group regular sequencer enable
+                                           with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
+                                           with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1)  /*!< ADC group regular sequencer enable
+                                           with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
+                                            | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
+                                           with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2)  /*!< ADC group regular sequencer enable
+                                           with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
+                                            | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
+                                           with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
+                                            | ADC_SQR1_L_1)                /*!< ADC group regular sequencerenable
+                                           with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
+                                            | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
+                                           with 16 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                            /*!< ADC group regular sequencer
+                                           discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR1_DISCEN)                        /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN)  /*!< ADC group regular sequencer
+                                           discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN)  /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \
+                                            | ADC_CFGR1_DISCEN)                        /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN)   /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 \
+                                            | ADC_CFGR1_DISCEN)                        /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \
+                                            | ADC_CFGR1_DISCEN)                        /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \
+                                            | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN)  /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                        /*!< ADC group inject.
+                                           conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group inject.
+                                           conversion trigger from external peripheral: external interrupt line 15.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM1 channel 4 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM1 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM1 TRGO2 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM2 channel 1 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
+                                            | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM2 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM3 channel 1 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM3 channel 3 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM3 channel 4 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 \
+                                            | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM3 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
+                                            | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM4 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
+                                            | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM5 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 \
+                                            | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM6 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM7 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM8 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM8 TRGO2 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM9_CH2       (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 \
+                                            | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM9 channel 2 event
+                                           (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM9 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM12_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
+                                            | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM12 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
+                                            | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM12 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM18_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 \
+                                            | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: TIM12 TRGO event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 \
+                                            | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group inject.
+                                           conversion trigger from external peripheral: LPTIM1 channel 2 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 \
+                                            | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: LPTIM2 channel 2 event.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 \
+                                            | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group inject.
+                                           conversion trigger from external peripheral: LPTIM3 channel 2 event.
+                                           Trigger edge set to rising edge (default setting). */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_EXT_RISING         (ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity
+                                           set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1) /*!< ADC group injected conversion trigger polarity
+                                           set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 \
+                                            | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity
+                                           set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)     /*!< ADC group injected conversion trigger independent.
+                                           Setting mandatory if ADC group injected injected trigger source is set to
+                                           an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR1_JAUTO)  /*!< ADC group injected conversion trigger from ADC group
+                                           regular. Setting compliant only with group injected trigger source set to
+                                           SW start, without any further action on  ADC group injected conversion start
+                                           or stop: in this case, ADC group injected is controlled only from ADC group
+                                           regular. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)  /*!< ADC group injected sequencer disable
+                                           (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks
+                                           in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1) /*!< ADC group injected sequencer enable with 3 ranks
+                                           in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 \
+                                            | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks
+                                           in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)      /*!< ADC group injected sequencer discontinuous mode
+                                           disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
+                                           enable with sequence interruption every rank */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET \
+                                            | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
+                                           rank 1 */
+#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET \
+                                            | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
+                                           rank 2 */
+#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET \
+                                            | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
+                                           rank 3 */
+#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET \
+                                            | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer
+                                           rank 4 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)           /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (ADC_SMPR2_SMP10_0)      /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_6CYCLES_5      (ADC_SMPR2_SMP10_1)      /*!< Sampling time 6.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_11CYCLES_5     (ADC_SMPR2_SMP10_1   \
+                                            | ADC_SMPR2_SMP10_0)    /*!< Sampling time 11.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_23CYCLES_5     (ADC_SMPR2_SMP10_2)      /*!< Sampling time 23.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_46CYCLES_5     (ADC_SMPR2_SMP10_2   \
+                                            | ADC_SMPR2_SMP10_0)    /*!< Sampling time 46.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_246CYCLES_5    (ADC_SMPR2_SMP10_2   \
+                                            | ADC_SMPR2_SMP10_1)    /*!< Sampling time 246.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_1499CYCLES_5   (ADC_SMPR2_SMP10_2   \
+                                            | ADC_SMPR2_SMP10_1 \
+                                            | ADC_SMPR2_SMP10_0)    /*!< Sampling time 1499.5 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+  * @{
+  */
+
+#define LL_ADC_SINGLE_ENDED                (ADC_CALFACT_CALFACT_S)                   /*!< ADC channel ending set to
+                                           single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to
+                                           differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED \
+                                            | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single
+                                           ended and differential (literal used only to set calibration factors) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK \
+                                            | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+  * @{
+  */
+#define LL_ADC_AWD_DISABLE                 (0x00000000UL)                            /*!< ADC analog watchdog monitoring
+                                           disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_CFGR1_AWD1EN)                      /*!< ADC analog watchdog monitoring
+                                           of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_CFGR1_JAWD1EN)                     /*!< ADC analog watchdog monitoring
+                                           of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)  /*!< ADC analog watchdog monitoring
+                                           of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG           (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ           (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ       (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG           (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ           (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ       (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG           (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ           (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ       (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG           (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ           (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ       (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG           (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ           (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ       (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG           (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ           (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ       (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG           (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ           (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ       (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG           (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ           (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ       (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG           (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ           (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ       (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG           (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ           (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ       (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG          (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ          (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ      (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD\
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG          (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ          (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ      (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG          (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ          (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ      (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG          (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ          (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ      (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG          (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ          (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN14, converted by group only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ      (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG          (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           monitoring of ADC channel ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ          (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ      (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN15, converted by either group
+                                           regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG          (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ          (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ      (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG          (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ          (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ      (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG          (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ          (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ      (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_19_REG          (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_BITFIELD \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_19_INJ          (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN19, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_19_REG_INJ      (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_BITFIELD \
+                                            | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN \
+                                            | ADC_CFGR1_AWD1SGL)                     /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN19, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG          LL_ADC_AWD_CHANNEL_17_REG                 /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VrefInt: Internal voltage reference,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ          LL_ADC_AWD_CHANNEL_17_INJ                 /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VrefInt: Internal voltage reference,
+                                           converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ      LL_ADC_AWD_CHANNEL_17_REG_INJ             /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VrefInt: Internal voltage reference,
+                                           converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG             LL_ADC_AWD_CHANNEL_16_REG                 /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to Vbat/4: Vbat voltage through
+                                           a divider ladder of factor 1/4 to have Vbat always below Vdda,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ             LL_ADC_AWD_CHANNEL_16_INJ                 /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to Vbat/4: Vbat voltage through
+                                           a divider ladder of factor 1/4 to have Vbat always below Vdda,
+                                           converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ         LL_ADC_AWD_CHANNEL_16_REG_INJ             /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to Vbat/4: Vbat voltage through
+                                           a divider ladder of factor 1/4 to have Vbat always below Vdda */
+#define LL_ADC_AWD_CH_VDDCORE_REG          LL_ADC_AWD_CHANNEL_17_REG                 /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VddCore,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_VDDCORE_INJ          LL_ADC_AWD_CHANNEL_17_INJ                 /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VddCore,
+                                           converted by group injected only */
+#define LL_ADC_AWD_CH_VDDCORE_REG_INJ      LL_ADC_AWD_CHANNEL_17_REG_INJ             /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VddCore,
+                                           converted by either group regular or injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+  * @{
+  */
+#define LL_ADC_AWD_THRESHOLD_HIGH          (0x1UL)                     /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (0x0UL)                     /*!< ADC analog watchdog threshold low */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG  Analog watchdog - filtering config
+  * @{
+  */
+#define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)             /*!< ADC analog watchdog filtering disabled:
+                                           one out-of-window sample is needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_2SAMPLES      (ADC_AWD1HTR_AWDFILT_0)    /*!< ADC analog watchdog filtering enabled: 2
+                                           out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_3SAMPLES      (ADC_AWD1HTR_AWDFILT_1)    /*!< ADC analog watchdog filtering enabled: 3
+                                           out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_4SAMPLES      (ADC_AWD1HTR_AWDFILT_1 \
+                                            | ADC_AWD1HTR_AWDFILT_0)   /*!< ADC analog watchdog filtering enabled: 4
+                                           out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC_AWD1HTR_AWDFILT_2)    /*!< ADC analog watchdog filtering enabled: 5
+                                           out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC_AWD1HTR_AWDFILT_2 \
+                                            | ADC_AWD1HTR_AWDFILT_0)   /*!< ADC analog watchdog filtering enabled: 6
+                                           out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC_AWD1HTR_AWDFILT_2 \
+                                            | ADC_AWD1HTR_AWDFILT_1)   /*!< ADC analog watchdog filtering enabled: 7
+                                           out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC_AWD1HTR_AWDFILT_2 \
+                                            | ADC_AWD1HTR_AWDFILT_1 \
+                                            | ADC_AWD1HTR_AWDFILT_0)   /*!< ADC analog watchdog filtering enabled: 8
+                                           out-of-window samples are needed to raise flag or interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+  * @{
+  */
+#define LL_ADC_OVS_DISABLE                 (0x00000000UL)                      /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (ADC_CFGR2_ROVSE)                   /*!< ADC oversampling on conversions of
+                                           ADC group regular. If group injected interrupts group regular:
+                                           when ADC group injected is triggered, the oversampling on ADC group regular
+                                           is temporary stopped and continued afterwards. */
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
+                                           ADC group regular. If group injected interrupts group regular:
+                                           when ADC group injected is triggered, the oversampling on ADC group regular
+                                           is resumed from start (oversampler buffer reset). */
+#define LL_ADC_OVS_GRP_INJECTED            (ADC_CFGR2_JOVSE)                   /*!< ADC oversampling on conversions of
+                                           ADC group injected. */
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
+                                           both ADC groups regular and injected. If group injected interrupting group
+                                           regular: when ADC group injected is triggered, the oversampling on ADC group
+                                           regular is resumed from start (oversampler buffer reset). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define LL_ADC_OVS_REG_CONT                (0x00000000UL)     /*!< ADC oversampling discontinuous mode: continuous mode
+                                           (all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)  /*!< ADC oversampling discontinuous mode: discontinuous
+                                           mode (each conversion of oversampling ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data right shift
+  * @{
+  */
+#define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                        /*!< ADC oversampling no shift
+                                           (sum of the ADC conversions data is not divided to result as oversampling
+                                           conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1           (ADC_CFGR2_OVSS_0)                    /*!< ADC oversampling right shift of 1
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 2
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2           (ADC_CFGR2_OVSS_1)                    /*!< ADC oversampling right shift of 2
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 4
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3           (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 8
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4           (ADC_CFGR2_OVSS_2)                    /*!< ADC oversampling right shift of 4
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 16
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 32
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 64
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
+                                            | ADC_CFGR2_OVSS_0)                   /*!< ADC oversampling right shift of 7
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 128
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3)                    /*!< ADC oversampling right shift of 8
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 256
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_9           (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 8
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 512
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_10          (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 8
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 1024
+                                           to result as oversampling conversion data) */
+/**
+  * @}
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                    /*!< ADC dual mode disabled (ADC
+                                           independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
+                                           simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
+                                            | ADC_CCR_DUAL_0)                  /*!< ADC dual mode enabled: Combined group
+                                           regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
+                                           simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
+                                           alternate trigger. Works only with external triggers (not SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (ADC_CCR_DUAL_0)                  /*!< ADC dual mode enabled: Combined group
+                                           regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (ADC_CCR_DUAL_1)                  /*!< ADC dual mode enabled: Combined group
+                                           regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
+                                           regular interleaved + group injected simultaneous */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_DATA_FORMAT  Multimode - Data format
+  * @{
+  */
+#define LL_ADC_MULTI_REG_DATA_EACH_ADC     (0x00000000UL)                      /*!< ADC multimode group regular
+                                           data format: conversion data in data register of each ADC instance.
+                                           If ADC data transfer by DMA is used: each ADC uses its own DMA channel,
+                                           with its individual DMA transfer settings. */
+#define LL_ADC_MULTI_REG_DATA_COMMON_32B   (ADC_CCR_DAMDF_1)                   /*!< ADC multimode group regular
+                                           data format: conversion data in two ADC common instance data registers
+                                           (CDR, CDR2) with packing option on 32 bit. In register CDR,
+                                           data packing on 32 bit: ADC master and slave data are concatenated
+                                           (data master in [15; 0], data slave in [31; 16]), therefore data width
+                                           must be lower than 16 bit (even with ADC resolution 12 bit,
+                                           higher width reachable by post processing: oversampling, offset, ...).
+                                           In register CDR2, data of master and slave are alternatively set in full
+                                           register width 32 bit, therefore no constraint on data width.
+                                           In case of usage with DMA, CDR generate ones transfer request
+                                           and CDR2 two transfer requests per conversion. */
+#define LL_ADC_MULTI_REG_DATA_COMMON_16B   (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular
+                                           data format: conversion data in two ADC common instance data registers
+                                           (CDR, CDR2) with packing option on 16 bit. In register CDR,
+                                           data packing on 16 bit: ADC master and slave data are concatenated
+                                           (data master in [7; 0], data slave in [15; 8]), therefore data width
+                                           must be lower than 8 bit (even with ADC resolution 8 bit,
+                                           higher width reachable by post processing: oversampling, offset, ...).
+                                           In register CDR2, data of master and slave are alternatively set in full
+                                           register width 32 bit, therefore no constraint on data width.
+                                           In case of usage with DMA, CDR generate ones transfer request
+                                           and CDR2 two transfer requests per conversion. */
+
+/* Legacy literals */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC LL_ADC_MULTI_REG_DATA_EACH_ADC
+#define LL_ADC_MULTI_REG_DMA_RES_32B  LL_ADC_MULTI_REG_DATA_COMMON_32B
+#define LL_ADC_MULTI_REG_DMA_RES_16B  LL_ADC_MULTI_REG_DATA_COMMON_16B
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000UL)                      /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 1 ADC clock cycle */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (ADC_CCR_DELAY_0)                   /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 2 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (ADC_CCR_DELAY_1)                   /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 3 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 4 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (ADC_CCR_DELAY_2)                   /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 5 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
+                                            | ADC_CCR_DELAY_0)                  /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3)                   /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
+                                            | ADC_CCR_DELAY_0)                  /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 12 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2) /*!< ADC multimode interleaved delay
+                                           between two sampling phases: 13 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
+  * @{
+  */
+#define LL_ADC_MULTI_MASTER                (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
+                                           instances: ADC master */
+#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
+                                           instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV \
+                                            | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
+                                           instances: both ADC master and ADC slave */
+/**
+  * @}
+  */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+  * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values.                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Indications for estimation of ADC timeout delays, for this           */
+/*       STM32 series:                                                        */
+/*       - ADC calibration time: maximum delay is 16384/fADC.                 */
+/*         (refer to device datasheet, parameter "tCAL")                      */
+/*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+/*         (refer to device datasheet, parameter "tSTAB")                     */
+/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+/*         cycles                                                             */
+/*       - ADC conversion time: duration depending on ADC clock and ADC       */
+/*         configuration.                                                     */
+/*         (refer to device reference manual, section "Timing")               */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tADCVREG_STUP").                                                */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)           /*!< Delay for ADC stabilization time (ADC voltage
+                                                              regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time.                   */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tstart_vrefint").                                               */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)        /*!< Delay for internal voltage reference stabilization
+                                                                   time */
+
+/* Delay required between ADC end of calibration and ADC enable.              */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles           */
+/*       are required between ADC end of calibration and ADC enable.          */
+/*       Wait time can be computed in user application by waiting for the     */
+/*       equivalent number of CPU cycles, by taking into account              */
+/*       ratio of CPU clock versus ADC clock prescalers.                      */
+/* Unit: ADC clock cycles.                                                    */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  4UL)        /*!< Delay required between ADC end of calibration
+                                                                   and ADC enable */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals LL_ADC_CHANNEL_x.
+  * @note   Example:
+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)  ((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK)
+
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) (__DECIMAL_NB__)
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           LL_ADC_CHANNEL_VREFINT, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, ...),
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+  *         (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_INTERNAL_MASK) != 0UL)
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (LL_ADC_CHANNEL_VREFINT, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK)
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)                                      \
+  ((((__ADC_INSTANCE__) == ADC1)                                                                                   \
+    &&(((__CHANNEL__ & ADC_CHANNEL_INTERNAL_ADC1) == ADC_CHANNEL_INTERNAL_ADC1))                                   \
+   )                                                                                                               \
+   ||                                                                                                              \
+   (((__ADC_INSTANCE__) == ADC2)                                                                                   \
+    &&(((__CHANNEL__ & ADC_CHANNEL_INTERNAL_ADC2) == ADC_CHANNEL_INTERNAL_ADC2))                                   \
+   )                                                                                                               \
+  )
+
+/**
+  * @brief  Helper macro to determine the selected channel corresponding
+  *         negative input on the ADC instance selected.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __LL_ADC_CHANNEL_DIFF_NEG_INPUT(__ADC_INSTANCE__, __CHANNEL__)                                                 \
+  __LL_ADC_DECIMAL_NB_TO_CHANNEL(ADC_CHANNEL_DIFF_LUT[__ADC_INSTANCE_INDEX(__ADC_INSTANCE__)][(uint8_t)(__CHANNEL__)]) \
+
+/**
+  * @brief  Helper macro to define ADC analog watchdog parameter:
+  *         define a single channel to monitor with analog watchdog
+  *         from sequencer channel and groups definition.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+  *         Example:
+  *           LL_ADC_SetAnalogWDMonitChannels(
+  *             ADC1, LL_ADC_AWD1,
+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  * @param  __GROUP__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_GROUP_REGULAR
+  *         @arg @ref LL_ADC_GROUP_INJECTED
+  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)
+  *         @arg @ref LL_ADC_AWD_CH_VDDCORE_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VDDCORE_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VDDCORE_REG_INJ      (1)
+  *
+  *         (0) On this STM32 series, parameter available only on analog watchdog instance: AWD1.\n
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC2, ADC3.
+  */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                        \
+  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                               \
+   ? ((((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK) << ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS)              \
+      | (ADC_CHANNEL_LUT[(uint8_t)(__CHANNEL__)] & ADC_CHANNEL_ID_BITFIELD_MASK)                       \
+      | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)                                                          \
+   :                                                                                                   \
+   ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
+   ? ((((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK) << ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS)              \
+      | (ADC_CHANNEL_LUT[(uint8_t)(__CHANNEL__)] & ADC_CHANNEL_ID_BITFIELD_MASK)                       \
+      | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL)                                                         \
+   :                                                                                                   \
+   ((((__CHANNEL__) & ADC_CHANNEL_NUMBER_MASK) << ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS)                \
+    | (ADC_CHANNEL_LUT[(uint8_t)(__CHANNEL__)] & ADC_CHANNEL_ID_BITFIELD_MASK)                         \
+    | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)                                        \
+  )
+
+/**
+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution when ADC resolution is different of 12 bit.
+  * @note   In case of ADC resolution different of 12 bits, this macro performs the required data formatting:
+  *         - analog watchdog thresholds data aligned to left side (bit 11).
+  *         - bits out of resolution range (LSB) set to value "0".
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to set the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           LL_ADC_SetAnalogWDThresholds
+  *            (< ADCx param >,
+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_data_8_bits>)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  *        (or tigher range for data corresponding to lower ADC resolution)
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_DATA__) \
+  ((__AWD_THRESHOLD_DATA__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
+
+/**
+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to get the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+  *            (LL_ADC_RESOLUTION_8B,
+  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U )))
+
+/**
+  * @brief  Helper macro to set the ADC calibration value with both single ended
+  *         and differential modes calibration factors concatenated.
+  * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
+  *         Example, to set calibration factors single ended to 0x55
+  *         and differential ended to 0x2A:
+  *           LL_ADC_SetCalibrationFactor(
+  *             ADC1,
+  *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+  * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
+  (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref LL_ADC_SetMultiDataFormat().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+  (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to select, from a ADC instance, to which ADC instance
+  *         it has a dependence in multimode (ADC master of the corresponding
+  *         ADC common instance).
+  * @note   In case of device with multimode available and a mix of
+  *         ADC instances compliant and not compliant with multimode feature,
+  *         ADC instances not compliant with multimode feature are
+  *         considered as master instances (do not depend to
+  *         any other ADC instance).
+  * @param  __ADCx__ ADC instance
+  * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+  */
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+  ( ( ((__ADCx__) == ADC2)                                                     \
+    )?                                                                         \
+    (ADC1)                                                                     \
+    :                                                                          \
+    (__ADCx__)                                                                 \
+  )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)    (ADC12_COMMON)
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
+  */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1UL)))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                         __ADC_RESOLUTION_CURRENT__,\
+                                         __ADC_RESOLUTION_TARGET__)          \
+(((__DATA__)                                                                 \
+  << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_Pos - 1UL)))   \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_Pos - 1UL))      \
+)
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                      __ADC_DATA__,\
+                                      __ADC_RESOLUTION__)                    \
+((__ADC_DATA__) * (int32_t)(__VREFANALOG_VOLTAGE__)                          \
+ / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                     \
+)
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value) in
+  *         differential ended mode.
+  * @note   ADC data from ADC data register is unsigned and centered around
+  *         middle code in. Converted voltage can be positive or negative
+  *         depending on differential input voltages.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                           __ADC_DATA__,\
+                                           __ADC_RESOLUTION__)\
+((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
+ / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
+ - (int32_t)(__VREFANALOG_VOLTAGE__))
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+  * @{
+  */
+/* Note: LL ADC functions to set DMA transfer are located into sections of    */
+/*       configuration of ADC instance, groups and multimode (if available):  */
+/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+
+/**
+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+  *         ADC register address from ADC instance and a list of ADC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These ADC registers are data registers:
+  *         when ADC conversion data is available in ADC data registers,
+  *         ADC generates a DMA transfer request.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+  * @note   For devices with several ADC: in multimode, some devices
+  *         use a different data register outside of ADC instance scope
+  *         (common data register). This macro manages this register difference,
+  *         only ADC instance has to be set as parameter.
+  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
+  * @param  ADCx ADC instance
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_MULTI_NO_PACKING (1)
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_MULTI_PACKING (1)
+  *
+  *         (1) Available on devices with several ADC instances.
+  * @retval ADC register address
+  */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
+{
+  uint32_t data_reg_addr;
+
+  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+  {
+    /* Retrieve address of register DR */
+    data_reg_addr = (uint32_t)(&(ADCx->DR));
+  }
+  else /* (Register == LL_ADC_DMA_REG_REGULAR_MULTI_NO_PACKING || LL_ADC_DMA_REG_REGULAR_MULTI_PACKING) */
+  {
+    /* Retrieve address of register CDR */
+    data_reg_addr = (uint32_t)(&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR));
+  }
+
+  return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(Register);
+
+  /* Retrieve address of register DR */
+  return (uint32_t)(&(ADCx->DR));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
+  *           ADC instances
+  * @{
+  */
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Configure all paths (overwrite current configuration).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  *         The values not selected are removed from configuration.
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VBATEN, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Add paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      VBATEN         LL_ADC_SetCommonPathInternalChAdd
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Remove paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      VBATEN         LL_ADC_SetCommonPathInternalChRem
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VBATEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Set parameter on ADC instance scope: measurement path to
+  *         internal channels (Vcore, Vcpu...).
+  *         Configure all paths (overwrite current configuration).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
+  *                   LL_ADC_PATH_INTERNAL_...)
+  *         The values not selected are removed from configuration.
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay may be required required for analog stabilization.
+  *         Refer to device datasheet.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll OR       OP2            LL_ADC_SetPathInternalCh
+  * @param  ADCx ADC instance
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetPathInternalCh(ADC_TypeDef *ADCx, uint32_t PathInternal)
+{
+  MODIFY_REG(ADCx->OR, ADC_OR_OP2, (PathInternal >> ADC_PATH_INTERNAL_POS));
+}
+
+/**
+  * @brief  Set parameter on ADC instance scope: measurement path to
+  *         internal channels (Vcore, Vcpu...).
+  *         Add paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
+  *                   LL_ADC_PATH_INTERNAL_...)
+  *         The values not selected are removed from configuration.
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay may be required required for analog stabilization.
+  *         Refer to device datasheet.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll OR       OP2            LL_ADC_SetPathInternalChAdd
+  * @param  ADCx ADC instance
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetPathInternalChAdd(ADC_TypeDef *ADCx, uint32_t PathInternal)
+{
+  SET_BIT(ADCx->OR, (PathInternal >> ADC_PATH_INTERNAL_POS));
+}
+
+/**
+  * @brief  Set parameter on ADC instance scope: measurement path to
+  *         internal channels (Vcore, Vcpu...).
+  *         Remove paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
+  *                   LL_ADC_PATH_INTERNAL_...)
+  *         The values not selected are removed from configuration.
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay may be required required for analog stabilization.
+  *         Refer to device datasheet.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll OR       OP2            LL_ADC_SetPathInternalChRem
+  * @param  ADCx ADC instance
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetPathInternalChRem(ADC_TypeDef *ADCx, uint32_t PathInternal)
+{
+  CLEAR_BIT(ADCx->OR, (PathInternal >> ADC_PATH_INTERNAL_POS));
+}
+
+/**
+  * @brief  Get parameter on ADC instance scope: measurement path to
+  *         internal channels (Vcore, Vcpu...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VDDCORE |
+  *                   LL_ADC_PATH_INTERNAL_...)
+  * @rmtoll OR       OP2            LL_ADC_GetPathInternalCh
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetPathInternalCh(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->OR, ADC_OR_OP2)) << ADC_PATH_INTERNAL_POS;
+}
+
+/**
+  * @brief  Set ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   This function is intended to set calibration parameters
+  *         without having to perform a new calibration using
+  *         @ref LL_ADC_StartCalibration().
+  * @note   In case of setting calibration factors of both modes single ended
+  *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+  *         both calibration factors must be concatenated.
+  *         To perform this processing, use helper macro
+  *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled, without calibration on going, without conversion
+  *         on going on group regular and group injected.
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+  MODIFY_REG(ADCx->CALFACT,
+             SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+             (CalibrationFactor << (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS & ~(SingleDiff & ADC_CALFACT_CALFACT_S)))
+             & SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK);
+}
+/**
+  * @brief  Get ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   Calibration factors are set by hardware after performing
+  *         a calibration run using function @ref LL_ADC_StartCalibration().
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Retrieve bits with position in register depending on parameter           */
+  /* "SingleDiff".                                                            */
+  /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
+  /* containing other bits reserved for other purpose.                        */
+  return (uint32_t)(READ_BIT(ADCx->CALFACT,
+                             (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
+                    >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+                        ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+}
+/**
+  * @brief  Set ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR1    RES            LL_ADC_SetResolution
+  * @param  ADCx ADC instance
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
+}
+
+/**
+  * @brief  Get ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR1    RES            LL_ADC_GetResolution
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
+}
+
+/**
+  * @brief  Set ADC low power mode.
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR1    AUTDLY         LL_ADC_SetLPModeAutoWait
+  * @param  ADCx ADC instance
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetLPModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+  MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_AUTDLY), LowPowerMode);
+}
+
+/**
+  * @brief  Get ADC low power mode:
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @rmtoll CFGR1    AUTDLY         LL_ADC_GetLPModeAutoWait
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoWait(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_AUTDLY));
+}
+
+/**
+  * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+  *         Channel to which the offset programmed will be applied
+  *         (independently of channel mapped on ADC group regular
+  *         or group injected)
+  * @note   If a channel is mapped on several offsets numbers, only the offset
+  *         with the lowest value is considered for the subtraction.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     OFFSET_CH      LL_ADC_SetOffsetChannel\n
+  *         OFR2     OFFSET_CH      LL_ADC_SetOffsetChannel\n
+  *         OFR3     OFFSET_CH      LL_ADC_SetOffsetChannel\n
+  *         OFR4     OFFSET_CH      LL_ADC_SetOffsetChannel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel)
+{
+  __IO uint32_t *preg_offset_cfg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+
+  MODIFY_REG(*preg_offset_cfg,
+             ADC_OFCFGR1_OFFSET_CH,
+             (Channel & ADC_CHANNEL_NUMBER_MASK) << ADC_OFCFGR1_OFFSET_CH_Pos);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         Channel to which the offset programmed will be applied
+  *         (independently of channel mapped on ADC group regular
+  *         or group injected)
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll OFR1     OFFSET_CH      LL_ADC_SetOffsetChannel\n
+  *         OFR2     OFFSET_CH      LL_ADC_SetOffsetChannel\n
+  *         OFR3     OFFSET_CH      LL_ADC_SetOffsetChannel\n
+  *         OFR4     OFFSET_CH      LL_ADC_SetOffsetChannel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+
+  return (uint32_t) __LL_ADC_DECIMAL_NB_TO_CHANNEL(READ_BIT(*preg, ADC_OFCFGR1_OFFSET_CH) >> ADC_OFCFGR1_OFFSET_CH_Pos);
+}
+
+/**
+  * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:
+  *         Offset level (offset to be subtracted from the raw
+  *         converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     OFFSET1        LL_ADC_SetOffsetLevel\n
+  *         OFR2     OFFSET2        LL_ADC_SetOffsetLevel\n
+  *         OFR3     OFFSET3        LL_ADC_SetOffsetLevel\n
+  *         OFR4     OFFSET4        LL_ADC_SetOffsetLevel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetLevel)
+{
+  __IO uint32_t *preg_offset_val = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg_offset_val,
+             ADC_OFR1_OFFSET,
+             OffsetLevel);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         Offset level (offset to be subtracted from the raw
+  *         converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
+  *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
+  *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
+  *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET);
+}
+
+/**
+  * @brief  Set for the ADC selected offset instance 1, 2, 3 or 4:
+  *         force offset state disable or enable
+  *         without modifying offset channel or offset value.
+  * @note   This function should be needed only in case of offset to be
+  *         enabled-disabled dynamically, and should not be needed in other cases:
+  *         function LL_ADC_SetOffset() automatically enables the offset.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFCFGR1  OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFCFGR2  OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFCFGR3  OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFCFGR4  OFFSETPOS      LL_ADC_SetOffsetSign
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetSign This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+  *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFCFGR1_POSOFF,
+             OffsetSign);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         offset sign if positive or negative.
+  * @rmtoll OFCFGR1  OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFCFGR2  OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFCFGR3  OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFCFGR4  OFFSETPOS      LL_ADC_GetOffsetSign
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+  *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFCFGR1_POSOFF);
+}
+
+/**
+  * @brief  Set Signed saturation for the ADC selected offset instance 1, 2, 3 or 4:
+  *         signed offset saturation if enabled or disabled.
+  * @rmtoll OFCFGR1  SSAT          LL_ADC_SetOffsetSignedSaturation\n
+  *         OFCFGR2  SSAT          LL_ADC_SetOffsetSignedSaturation\n
+  *         OFCFGR3  SSAT          LL_ADC_SetOffsetSignedSaturation\n
+  *         OFCFGR4  SSAT          LL_ADC_SetOffsetSignedSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetSignedSaturation This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SAT_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SAT_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
+                                                      uint32_t OffsetSignedSaturation)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+  MODIFY_REG(*preg, ADC_OFCFGR1_SSAT, OffsetSignedSaturation);
+}
+
+/**
+  * @brief  Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
+  *         signed offset saturation if enabled or disabled.
+  * @rmtoll OFCFGR1  SSAT          LL_ADC_GetOffsetSignedSaturation\n
+  *         OFCFGR2  SSAT          LL_ADC_GetOffsetSignedSaturation\n
+  *         OFCFGR3  SSAT          LL_ADC_GetOffsetSignedSaturation\n
+  *         OFCFGR4  SSAT          LL_ADC_GetOffsetSignedSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SAT_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SAT_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+  return (uint32_t) READ_BIT(*preg, ADC_OFCFGR1_SSAT);
+}
+
+/**
+  * @brief  Set Unsigned saturation for the ADC selected offset instance 1, 2, 3 or 4:
+  *         signed offset saturation if enabled or disabled.
+  * @rmtoll OFCFGR1  USAT          LL_ADC_SetOffsetUnsignedSaturation\n
+  *         OFCFGR2  USAT          LL_ADC_SetOffsetUnsignedSaturation\n
+  *         OFCFGR3  USAT          LL_ADC_SetOffsetUnsignedSaturation\n
+  *         OFCFGR4  USAT          LL_ADC_SetOffsetUnsignedSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetUnsignedSaturation This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
+                                                        uint32_t OffsetUnsignedSaturation)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+  MODIFY_REG(*preg, ADC_OFCFGR1_USAT, OffsetUnsignedSaturation);
+}
+
+/**
+  * @brief  Get Unsigned saturation for the ADC selected offset instance 1, 2, 3 or 4:
+  *         signed offset saturation if enabled or disabled.
+  * @rmtoll OFCFGR1  USAT          LL_ADC_GetOffsetUnsignedSaturation\n
+  *         OFCFGR2  USAT          LL_ADC_GetOffsetUnsignedSaturation\n
+  *         OFCFGR3  USAT          LL_ADC_GetOffsetUnsignedSaturation\n
+  *         OFCFGR4  USAT          LL_ADC_GetOffsetUnsignedSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFCFGR1, Offsety);
+  return (uint32_t) READ_BIT(*preg, ADC_OFCFGR1_USAT);
+}
+
+/**
+  * @brief  Set ADC gain compensation.
+  * @note   This function set the gain compensation coefficient
+  *         that is applied to raw converted data using the formula:
+  *           DATA = DATA(raw) * (gain compensation coef) / 4096
+  * @note   This function enables the gain compensation if given
+  *         coefficient is above 0, otherwise it disables it.
+  * @note   Gain compensation when enabled is applied to all channels.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_SetGainCompensation\n
+  *         CFGR2    GCOMP          LL_ADC_SetGainCompensation
+  * @param  ADCx ADC instance
+  * @param  GainCompensation This parameter can be:
+  *         0           Gain compensation will be disabled and value set to 0
+  *         1 -> 16393  Gain compensation will be enabled with specified value
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
+{
+  MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
+  MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_GCOMP_GCOMP_Pos);
+}
+
+/**
+  * @brief  Get the ADC gain compensation value
+  * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_GetGainCompensation\n
+  *         CFGR2    GCOMP          LL_ADC_GetGainCompensation
+  * @param  ADCx ADC instance
+  * @retval Returned value can be:
+  *         0           Gain compensation is disabled
+  *         1 -> 16393  Gain compensation is enabled with returned value
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP)   \
+          ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 series having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_REG_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_SetTriggerSource\n
+  *         CFGR1    EXTEN          LL_ADC_REG_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM18_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group regular trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to
+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_GetTriggerSource\n
+  *         CFGR1    EXTEN          LL_ADC_REG_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM12_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM18_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
+{
+  __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
+
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}.                            */
+  uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+  /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL       */
+  /* to match with triggers literals definition.                              */
+  return ((trigger_source
+           & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
+          | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source internal (SW start)
+  *         or external.
+  * @note   In case of group regular trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_REG_GetTriggerSource().
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
+}
+
+/**
+  * @brief  Set ADC sampling mode.
+  * @note   This function set the ADC conversion sampling mode
+  * @note   This mode applies to regular group only.
+  * @note   Set sampling mode is applied to all conversion of regular group.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR2    BULB           LL_ADC_REG_SetSamplingMode\n
+  *         CFGR2    SMPTRIG        LL_ADC_REG_SetSamplingMode
+  * @param  ADCx ADC instance
+  * @param  SamplingMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
+}
+
+/**
+  * @brief  Get the ADC sampling mode
+  * @rmtoll CFGR2    BULB           LL_ADC_REG_GetSamplingMode\n
+  *         CFGR2    SMPTRIG        LL_ADC_REG_GetSamplingMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
+}
+
+/**
+  * @brief  Start ADC sampling phase for sampling time trigger mode
+  * @note   This function is relevant only when
+  *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+  *           using @ref LL_ADC_REG_SetSamplingMode
+  *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StartSamplingPhase
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+  * @brief  Stop ADC sampling phase for sampling time trigger mode and start conversion
+  * @note   This function is relevant only when
+  *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+  *           using @ref LL_ADC_REG_SetSamplingMode
+  *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+  *         - @ref LL_ADC_REG_StartSamplingPhase has been called to start
+  *           the sampling phase
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StopSamplingPhase
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+  * @brief  Set ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   It is not possible to enable both ADC auto-injected mode
+  *         and ADC group regular sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+  *         CFGR1    DISCNUM        LL_ADC_REG_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+  *         CFGR1    DISCNUM        LL_ADC_REG_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM));
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   This function performs configuration of:
+  *         - Channels ordering into each rank of scan sequence:
+  *           whatever channel can be placed into whatever rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register and register position depending on parameter "Rank".         */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
+                                             ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             ADC_CHANNEL_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+             (Channel & ADC_CHANNEL_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
+                                                   ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+  return (uint32_t)((READ_BIT(*preg,
+                              ADC_CHANNEL_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                   );
+}
+
+/**
+  * @brief  Set ADC Channel Preselection to LL_ADC_CHANNEL_x, x = 0 to 19.
+  * @note   This function set the the value for the channel preselection register
+  *         corresponding to ADC channel to be selected.
+  * @rmtoll PCSEL   PCSEL          LL_ADC_SetChannelPreselection
+  * @param  ADCx ADC instance.
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  __IO uint32_t channel_preselectione = READ_REG(ADCx->PCSEL);
+  WRITE_REG(ADCx->PCSEL,
+            channel_preselectione | (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)Channel) & 0x1FUL)));
+}
+
+/**
+  * @brief  Get ADC Channel Preselection register value.
+  * @note   This function set the the value for the channel preselection register
+  *         corresponding to ADC channel to be selected.
+  * @rmtoll PCSEL   PCSEL          LL_ADC_GetChannelPreselection
+  * @param  ADCx ADC instance.
+  *
+  * @retval Returned decimal value that can correspend to one or multiple channels:
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL));
+}
+
+/**
+  * @brief  Set ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    CONT           LL_ADC_REG_SetContinuousMode
+  * @param  ADCx ADC instance
+  * @param  Continuous This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
+}
+
+/**
+  * @brief  Get ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @rmtoll CFGR1    CONT           LL_ADC_REG_GetContinuousMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
+}
+
+/**
+  * @brief  Set ADC data transfer mode
+  * @note   Conversion data can be either:
+  *            - Available in Data Register
+  *            - Transferred by DMA in one shot mode
+  *            - Transferred by DMA in circular mode
+  *            - Transferred to MDF data register
+  * @rmtoll CFGR1    DMNGT           LL_ADC_REG_SetDataTransferMode
+  * @param  ADCx ADC instance
+  * @param  DataTransferMode Select Data Management configuration
+  *         @arg @ref LL_ADC_REG_DR_TRANSFER
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  *         @arg @ref LL_ADC_REG_MDF_TRANSFER
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMNGT, DataTransferMode);
+}
+
+/**
+  * @brief  Get ADC data transfer mode
+  * @note   Conversion data can be either:
+  *            - Available in Data Register
+  *            - Transferred by DMA in one shot mode
+  *            - Transferred by DMA in circular mode
+  *            - Transferred to DFSDM data register
+  * @rmtoll CFGR1    DMNGT           LL_ADC_REG_GetDataTransferMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DR_TRANSFER
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  *         @arg @ref LL_ADC_REG_MDF_TRANSFER
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT));
+}
+
+/**
+  * @brief  Set ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @note   Compatibility with devices without feature overrun:
+  *         other devices without this feature have a behavior
+  *         equivalent to data overwritten.
+  *         The default setting of overrun is data preserved.
+  *         Therefore, for compatibility with all devices, parameter
+  *         overrun should be set to data overwritten.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_SetOverrun
+  * @param  ADCx ADC instance
+  * @param  Overrun This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
+}
+
+/**
+  * @brief  Get ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_GetOverrun
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group injected conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 series having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_INJ_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM18_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group injected trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to
+  *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM12_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM18_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
+{
+  __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
+  uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
+  /* to match with triggers literals definition.                              */
+  return ((trigger_source
+           & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
+          | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source internal (SW start)
+            or external
+  * @note   In case of group injected trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_INJ_GetTriggerSource.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer length and scan direction.
+  * @note   This function performs configuration of:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer length and scan direction.
+  * @note   This function retrieves:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @rmtoll CFGR1    JDISCEN        LL_ADC_INJ_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JDISCEN, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR1    JDISCEN        LL_ADC_INJ_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register depending on parameter "Rank".                               */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  MODIFY_REG(ADCx->JSQR,
+             (ADC_CHANNEL_NUMBER_MASK >> ADC_AWD_CHANNEL_NUMBER_BITOFFSET_POS)
+             << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+             (Channel & ADC_CHANNEL_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+  * @brief  Get ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  return (uint32_t)((READ_BIT(ADCx->JSQR,
+                              ADC_CHANNEL_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+                   );
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @note   This mode can be used to extend number of data registers
+  *         updated after one ADC conversion trigger and with data
+  *         permanently kept (not erased by successive conversions of scan of
+  *         ADC sequencer ranks), up to 5 data registers:
+  *         1 data register on ADC group regular, 4 data registers
+  *         on ADC group injected.
+  * @note   If ADC group injected injected trigger source is set to an
+  *         external trigger, this feature must be must be set to
+  *         independent trigger.
+  *         ADC group injected automatic trigger is compliant only with
+  *         group injected trigger source set to SW start, without any
+  *         further action on  ADC group injected conversion start or stop:
+  *         in this case, ADC group injected is controlled only
+  *         from ADC group regular.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR1    JAUTO          LL_ADC_INJ_SetTrigAuto
+  * @param  ADCx ADC instance
+  * @param  TrigAuto This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JAUTO, TrigAuto);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @rmtoll CFGR1    JAUTO          LL_ADC_INJ_GetTrigAuto
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+  * @{
+  */
+
+/**
+  * @brief  Set sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 series, ADC processing time is:
+  *         - 13.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 11.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  * @param  SamplingTime This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_11CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_23CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_46CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_246CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1499CYCLES_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+  /* Set bits with content of parameter "SamplingTime" with bits position     */
+  /* in register and register position depending on parameter "Channel".      */
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
+                                             ((ADC_CHANNEL_LUT[iChannel]
+                                               & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+  MODIFY_REG(*preg,
+             ADC_SMPR1_SMP0 << ((ADC_CHANNEL_LUT[iChannel] & ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+                                >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
+             SamplingTime   << ((ADC_CHANNEL_LUT[iChannel] & ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+                                >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
+}
+
+/**
+  * @brief  Get sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 series, ADC processing time is:
+  *         - 13.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 11.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT     (1)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT        (2)(3)
+  *         @arg @ref LL_ADC_CHANNEL_VDDCORE     (2)(3)
+  *
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n
+  *         (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n
+  *         (3) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_11CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_23CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_46CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_246CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1499CYCLES_5
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
+                                                   ((ADC_CHANNEL_LUT[iChannel]
+                                                     & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_SMPR1_SMP0
+                             << ((ADC_CHANNEL_LUT[iChannel]
+                                  & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
+                    >> ((ADC_CHANNEL_LUT[iChannel] & ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+                        >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
+                   );
+}
+
+/**
+  * @brief  Set mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   Channel ending is on channel scope: independently of channel mapped
+  *         on ADC group regular or injected.
+  *         In differential mode: Differential measurement is carried out
+  *         between the selected channel (positive input) and another
+  *         channel (negative input).
+  *         Only selected channel has to be configured, the other channel
+  *         is configured automatically.
+  * @note   The selected channel and the other other channel have
+  *         not necessarily contiguous channel number.
+  *         To get the other channel number, refer to reference manual
+  *         in section of ADC instance connectivity.
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'inp' in differential mode,
+  *         the channel 'inn' is not usable separately.
+  * @note   Some channels are internally fixed to single-ended inputs
+  *         configuration, refer to device datasheet for more details.
+  * @note   For ADC channels configured in differential mode, both inputs
+  *         should be biased at (Vref+)/2 +/-200mV.
+  *         (Vref+ is the analog voltage reference)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  * @param  SingleDiff This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+  /* Bits of channels in single or differential mode are set only for         */
+  /* differential mode (for single mode, mask of bits allowed to be set is    */
+  /* shifted out of range of bits of channels in single or differential mode. */
+  const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
+  MODIFY_REG(ADCx->DIFSEL,
+             ADC_CHANNEL_LUT[iChannel] & ADC_SINGLEDIFF_CHANNEL_MASK,
+             (ADC_CHANNEL_LUT[iChannel] & ADC_SINGLEDIFF_CHANNEL_MASK)
+             & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Get mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   Channel ending is on channel scope: independently of channel mapped
+  *         on ADC group regular or injected.
+  *         In differential mode: Differential measurement is carried out
+  *         between the selected channel (positive input) and another
+  *         channel (negative input).
+  *         Only selected channel has to be configured, the other channel
+  *         is configured automatically.
+  * @note   The selected channel and the other other channel have
+  *         not necessarily contiguous channel number.
+  *         To get the other channel number, refer to reference manual
+  *         in section of ADC instance connectivity.
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  * @note   Some channels are internally fixed to single-ended inputs
+  *         configuration, refer to device datasheet for more details.
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  * @retval 0: channel in single-ended mode, else: channel in differential mode
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  const uint32_t iChannel = __ADC_CHANNEL_INDEX(Channel);
+  return (uint32_t)(READ_BIT(ADCx->DIFSEL,
+                             (ADC_CHANNEL_LUT[iChannel] & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+  * @{
+  */
+
+/**
+  * @brief  Set ADC analog watchdog monitored channels:
+  *         a single channel, multiple channels or all channels,
+  *         on ADC groups regular and-or injected.
+  * @note   Once monitored channels are selected, analog watchdog
+  *         is enabled.
+  * @note   In case of need to define a single channel to monitor
+  *         with analog watchdog from sequencer channel definition,
+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR1    AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR1    JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDChannelGroup This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)
+  *         @arg @ref LL_ADC_AWD_CH_VDDCORE_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VDDCORE_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VDDCORE_REG_INJ      (1)
+  *
+  *         (0) On this STM32 series, parameter available only on analog watchdog instance: AWD1.\n
+  *         (1) On this STM32 series, parameter available only on ADC instance: ADC2, ADC3.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
+  /* in register and register position depending on parameter "AWDy".         */
+  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
+                                             ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
+                                                * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+  MODIFY_REG(*preg,
+             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+             AWDChannelGroup & AWDy);
+}
+
+/**
+  * @brief  Get ADC analog watchdog monitored channel.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Applicable only when the analog watchdog is set to monitor
+  *           one channel.
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR1    AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR1    JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2 (1)
+  *         @arg @ref LL_ADC_AWD3 (1)
+  *
+  *         (1) On this AWD number, monitored channel can be retrieved
+  *             if only 1 channel is programmed (or none or all channels).
+  *             This function cannot retrieve monitored channel if
+  *             multiple channels are programmed simultaneously
+  *             by bitfield.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+  *
+  *         (0) On this STM32 series, parameter available only on analog watchdog number: AWD1.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  const __IO uint32_t *preg;
+
+  if (AWDy == LL_ADC_AWD1)
+  {
+    /* Set pointer to register of selected analog watchdog */
+    preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
+  }
+  else
+  {
+    /* Set pointer to register of selected analog watchdog */
+    preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK))                                   \
+                                >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
+  }
+
+  uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+  /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled       */
+  /* (parameter value LL_ADC_AWD_DISABLE).                                    */
+  /* Else, the selected AWD is enabled and is monitoring a group of channels  */
+  /* or a single channel.                                                     */
+  if (analog_wd_monit_channels != 0UL)
+  {
+    if (AWDy == LL_ADC_AWD1)
+    {
+      if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
+      {
+        /* AWD monitoring a group of channels */
+        analog_wd_monit_channels = ((analog_wd_monit_channels
+                                     | (ADC_AWD_CR23_CHANNEL_MASK)
+                                    )
+                                    & (~(ADC_CFGR1_AWD1CH))
+                                   );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        analog_wd_monit_channels = (analog_wd_monit_channels
+                                    | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
+                                   );
+      }
+    }
+    else
+    {
+      if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+      {
+        /* AWD monitoring a group of channels */
+        analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
+                                    | ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN))
+                                   );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        /* AWD monitoring a group of channels */
+        analog_wd_monit_channels = (analog_wd_monit_channels
+                                    | (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+                                    | (((uint32_t)(POSITION_VAL(analog_wd_monit_channels))) << ADC_CFGR1_AWD1CH_Pos)
+                                   );
+      }
+    }
+  }
+
+  return analog_wd_monit_channels;
+}
+
+/**
+  * @brief  Set ADC analog watchdog threshold value of threshold
+  *         high or low.
+  * @note   In case of ADC resolution different of 12 bits, specific threshold data formatting is required:
+  *         - analog watchdog thresholds data must be aligned to left side (bit 11).
+  *         - bits out of resolution range (LSB) must be set to value "0".
+  *         To perform this formatting automatically, use helper
+  *         macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+  *         impacted: the comparison of analog watchdog thresholds is done
+  *         on oversampling intermediate computation (after ratio, before shift
+  *         application): intermediate register bitfield [32:7]
+  *         (26 most significant bits).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC can be disabled, enabled with or without conversion on going
+  *         on either ADC groups regular or injected.
+  * @rmtoll AWD1LTR  LTR            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD1HTR  HTR            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD2LTR  LTR            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD2HTR  HTR            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD3LTR  LTR            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD3HTR  HTR            LL_ADC_SetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
+                                                  uint32_t AWDThresholdValue)
+{
+  __IO uint32_t *preg;
+
+  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+  /* position in register and register position depending on parameters       */
+  /* "AWDThresholdsHighLow" and "AWDy".                                       */
+  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+  /* containing other bits reserved for other purpose.                        */
+  if (AWDy == LL_ADC_AWD1)
+  {
+    preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR, (AWDThresholdsHighLow));
+  }
+  else
+  {
+    preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)
+                                                 >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+                                + (AWDThresholdsHighLow));
+  }
+
+  MODIFY_REG(*preg, ADC_AWD1LTR_LTR, AWDThresholdValue);
+}
+
+/**
+  * @brief  Get ADC analog watchdog threshold value of threshold high,
+  *         threshold low or raw data with ADC thresholds high and low
+  *         concatenated.
+  * @note   In case of ADC resolution different of 12 bits, specific threshold data formatting is required:
+  *         - analog watchdog thresholds data must be aligned to left side (bit 11).
+  *         - bits out of resolution range (LSB) must be set to value "0".
+  *         To perform this formatting automatically, use helper
+  *         macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @rmtoll AWD1LTR  LTR            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD1HTR  HTR            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD2LTR  LTR            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD2HTR  HTR            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD3LTR  LTR            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD3HTR  HTR            LL_ADC_GetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
+                                                      uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+  const __IO uint32_t *preg;
+
+  if (AWDy == LL_ADC_AWD1)
+  {
+    preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR, (AWDThresholdsHighLow));
+  }
+  else
+  {
+    preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1LTR,
+                                (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+                                + (AWDThresholdsHighLow));
+  }
+
+  return (uint32_t)(READ_BIT(*preg, ADC_AWD1LTR_LTR));
+}
+
+/**
+  * @brief  Set ADC analog watchdog filtering configuration
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @note   On this STM32 series, this feature is only available on first
+  *         analog watchdog (AWD1)
+  * @rmtoll AWD1HTR  AWDFILT        LL_ADC_SetAWDFilteringConfiguration
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  * @param  FilteringConfig This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+  *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(AWDy);
+  MODIFY_REG(ADCx->AWD1HTR, ADC_AWD1HTR_AWDFILT, FilteringConfig);
+}
+
+/**
+  * @brief  Get ADC analog watchdog filtering configuration
+  * @note   On this STM32 series, this feature is only available on first
+  *         analog watchdog (AWD1)
+  * @rmtoll AWD1HTR  AWDFILT        LL_ADC_GetAWDFilteringConfiguration
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  * @retval Returned value can be:
+  *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+  *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(AWDy);
+  return (uint32_t)(READ_BIT(ADCx->AWD1HTR, ADC_AWD1HTR_AWDFILT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+  * @{
+  */
+
+/**
+  * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 series).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @param  OvsScope This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+}
+
+/**
+  * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 series).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+}
+
+/**
+  * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   On this STM32 series, oversampling discontinuous mode
+  *         (triggered mode) can be used only when oversampling is
+  *         set on group regular only and in resumed mode.
+  * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @param  OverSamplingDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+}
+
+/**
+  * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+}
+
+/**
+  * @brief  Set ADC oversampling
+  *         (impacting both ADC groups regular and injected)
+  * @note   This function set the 2 items of oversampling configuration:
+  *         - ratio
+  *         - shift
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+  * @param  ADCx ADC instance
+  * @param  Ratio This parameter can be in the range from 1 to 1024
+  * @param  Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
+}
+
+/**
+  * @brief  Get ADC oversampling ratio
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+  * @param  ADCx ADC instance
+  * @retval Ratio This parameter can be in the from 1 to 1024.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
+{
+  return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
+}
+
+/**
+  * @brief  Get ADC oversampling shift
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+  * @param  ADCx ADC instance
+  * @retval Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+  * @{
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Set ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  Multimode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+  * @brief  Get ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+  * @brief  Set ADC multimode conversion data format: conversion data in data
+  *         register of each ADC instance or ADC common instance.
+  * @note   If ADC data transfer by DMA is used: data register as DMA source
+  *         and number of DMA requests is impacted, refer to description
+  *         of parameters of this function.
+  * @note   How to retrieve multimode conversion data:
+  *         For multimode data transfer setting 16 bit resolution or less,
+  *         using functions @ref LL_ADC_REG_ReadMultiConvPacking() or @ref LL_ADC_REG_ReadMultiConvNoPacking().
+  *         Conversion data is a raw data with ADC master and slave
+  *         concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled
+  *         or enabled without conversion on going on group regular.
+  * @rmtoll CCR      DAMDF          LL_ADC_SetMultiDataFormat
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiDataFormat This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DATA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_32B
+  *         @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_16B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiDataFormat(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDataFormat)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDataFormat);
+}
+
+/**
+  * @brief  Get ADC multimode conversion data format: conversion data in data
+  *         register of each ADC instance or ADC common instance.
+  * @note   If ADC data transfer by DMA is used: data register as DMA source
+  *         and number of DMA requests is impacted, refer to description
+  *         of parameters of this function.
+  * @note   How to retrieve multimode conversion data:
+  *         For multimode data transfer setting 16 bit resolution or less,
+  *         using functions @ref LL_ADC_REG_ReadMultiConvPacking() or @ref LL_ADC_REG_ReadMultiConvNoPacking().
+  *         Conversion data is a raw data with ADC master and slave
+  *         concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDataFormat
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DATA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_32B
+  *         @arg @ref LL_ADC_MULTI_REG_DATA_COMMON_16B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDataFormat(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
+}
+
+/**
+  * @brief  Set ADC multimode delay between 2 sampling phases.
+  * @note   The sampling delay range depends on ADC resolution:
+  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
+  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
+  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
+  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+  * @brief  Get ADC multimode delay between 2 sampling phases.
+  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Put ADC instance in deep power down state.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_DEEPPWD);
+}
+
+/**
+  * @brief  Disable ADC deep power down mode.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance deep power down state.
+  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Enable the selected ADC instance.
+  * @note   On this STM32 series, after ADC enable, a delay for
+  *         ADC internal analog stabilization is required before performing a
+  *         ADC conversion start.
+  *         Refer to device datasheet, parameter tSTAB.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+  * @rmtoll CR       ADEN           LL_ADC_Enable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADEN);
+}
+
+/**
+  * @brief  Disable the selected ADC instance.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be not disabled. Must be enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CR       ADDIS          LL_ADC_Disable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADDIS);
+}
+
+/**
+  * @brief  Get the selected ADC instance enable state.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the selected ADC instance disable state.
+  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no ADC disable command on going.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Start ADC calibration in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   On this STM32 series, a minimum number of ADC clock cycles
+  *         are required between ADC end of calibration and ADC enable.
+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  *         (calibration run must be performed for each of these
+  *         differential modes, if used afterwards and if the application
+  *         requires their calibration).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
+  *         CR       ADCALDIF       LL_ADC_StartCalibration
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+  * @brief  Get ADC calibration state.
+  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+  * @param  ADCx ADC instance
+  * @retval 0: calibration complete, 1: calibration in progress.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Stop ADC calibration
+  * @note   On this STM32 series, a minimum number of ADC clock cycles
+  *         are required between ADC end of calibration and ADC enable.
+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+  * @rmtoll CR       ADCAL          LL_ADC_StopCalibration\n
+  *         CR       ADCALDIF       LL_ADC_StopCalibration
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_StopCalibration(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  CLEAR_BIT(ADCx->CR, ADC_CR_ADCALDIF | ADC_CR_ADCAL | ADC_CR_BITS_PROPERTY_RS);
+}
+
+/**
+  * @brief  Enable calibration additional offset
+  * @rmtoll CALFACT       CALADDOS       LL_ADC_EnableCalibrationOffset
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableCalibrationOffset(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CALFACT, ADC_CALFACT_CALADDOS);
+}
+
+/**
+  * @brief  Disable calibration additional offset
+  * @rmtoll CALFACT       CALADDOS       LL_ADC_DisableCalibrationOffset
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableCalibrationOffset(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALADDOS);
+}
+
+/**
+  * @brief  Get calibration additional offset state.
+  * @rmtoll CALFACT       CALADDOS          LL_ADC_IsCalibrationOnGoing
+  * @param  ADCx ADC instance
+  * @retval 0: calibration offset disabled, 1: calibration offset enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOffsetEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALADDOS) == (ADC_CALFACT_CALADDOS)) ? 1UL : 0UL);
+}
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group regular conversion.
+  * @note   On this STM32 series, this function is relevant for both
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTART);
+}
+
+/**
+  * @brief  Stop ADC group regular conversion.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTP);
+}
+
+/**
+  * @brief  Get ADC group regular conversion state.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group regular command of conversion stop state
+  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get ADC multimode conversion data of ADC master and ADC slave
+  *         concatenated.
+  * @note   Multimode data concatenation is usable under conditions of
+  *         ADC multimode data format selected and data width,
+  *         refer to description of literals in @ref ADC_LL_EC_MULTI_DATA_FORMAT.
+  * @note   From raw data with ADC master and slave concatenated,
+  *         a macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConvPacking\n
+  *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConvPacking
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConvPacking(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)));
+}
+
+/**
+  * @brief  Get ADC multimode conversion data of ADC master or ADC slave
+  *         (data set alternatively in specific data register).
+  * @note   Multimode data without concatenation is compliant with all
+  *         ADC multimode data format and data width,
+  *         refer to description of literals in @ref ADC_LL_EC_MULTI_DATA_FORMAT.
+  * @note   Multimode data without packing is using a unique data register
+  *         (CDR2) for data of ADC master and slave alternatively.
+  *         Therefore, data can be overwritten very quickly, recommended
+  *         method to retrieve data without risk to miss some occurrences
+  *         is to use DMA transfer.
+  * @rmtoll CDR2     RDATA_ALT      LL_ADC_REG_ReadMultiConvNoPacking
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConvNoPacking(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR2, ADC_CDR2_RDATA_ALT));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group injected conversion.
+  * @note   On this STM32 series, this function is relevant for both
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group injected,
+  *         without conversion stop command on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTART);
+}
+
+/**
+  * @brief  Stop ADC group injected conversion.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTP);
+}
+
+/**
+  * @brief  Get ADC group injected conversion state.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group injected command of conversion stop state
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+  * @{
+  */
+
+/**
+  * @brief  Get flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 1 flag
+  * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+  * @brief  Clear flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 1.
+  * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get flag multimode ADC ready of the ADC master.
+  * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC ready of the ADC slave.
+  * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+  * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_MST) == (LL_ADC_FLAG_EOC_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+  * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC master.
+  * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
+  * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
+  * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
+  * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+  * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+  * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
+  * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
+  * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
+  * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
+  * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
+  * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
+  * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Enable ADC group regular interruption overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Disable interruption ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Get state of interruption ADC ready
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular overrun
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sampling
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC analog watchdog 1
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 2
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 3
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 series) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_ADC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_bus.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_bus.h
new file mode 100644
index 000000000..b6d8edc72
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_bus.h
@@ -0,0 +1,3962 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_bus.h
+  * @author  MCD Application Team
+  * @brief   Header file of BUS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_BUS_H
+#define STM32N6xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AXI  AXI
+  * @{
+  */
+#define LL_ACLKN                           RCC_BUSENR_ACLKNEN
+#define LL_ACLKNC                          RCC_BUSENR_ACLKNCEN
+#define LL_AHBM                            RCC_BUSENR_AHBMEN
+#define LL_AHB1                            RCC_BUSENR_AHB1EN
+#define LL_AHB2                            RCC_BUSENR_AHB2EN
+#define LL_AHB3                            RCC_BUSENR_AHB3EN
+#define LL_AHB4                            RCC_BUSENR_AHB4EN
+#define LL_AHB5                            RCC_BUSENR_AHB5EN
+#define LL_APB1                            RCC_BUSENR_APB1EN
+#define LL_APB2                            RCC_BUSENR_APB2EN
+#define LL_APB3                            RCC_BUSENR_APB3EN
+#define LL_APB4                            RCC_BUSENR_APB4EN
+#define LL_APB5                            RCC_BUSENR_APB5EN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_MEM  MEM
+  * @{
+  */
+#define LL_MEM_AXISRAM1                    RCC_MEMENR_AXISRAM1EN
+#define LL_MEM_AXISRAM2                    RCC_MEMENR_AXISRAM2EN
+#define LL_MEM_AXISRAM3                    RCC_MEMENR_AXISRAM3EN
+#define LL_MEM_AXISRAM4                    RCC_MEMENR_AXISRAM4EN
+#define LL_MEM_AXISRAM5                    RCC_MEMENR_AXISRAM5EN
+#define LL_MEM_AXISRAM6                    RCC_MEMENR_AXISRAM6EN
+#define LL_MEM_AHBSRAM1                    RCC_MEMENR_AHBSRAM1EN
+#define LL_MEM_AHBSRAM2                    RCC_MEMENR_AHBSRAM2EN
+#define LL_MEM_BKPSRAM                     RCC_MEMENR_BKPSRAMEN
+#define LL_MEM_FLEXRAM                     RCC_MEMENR_FLEXRAMEN
+#define LL_MEM_CACHEAXIRAM                 RCC_MEMENR_CACHEAXIRAMEN
+#define LL_MEM_VENCRAM                     RCC_MEMENR_VENCRAMEN
+#define LL_MEM_BOOTROM                     RCC_MEMENR_BOOTROMEN
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN
+#define LL_AHB1_GRP1_PERIPH_GPDMA1         RCC_AHB1ENR_GPDMA1EN
+#define LL_AHB1_GRP1_PERIPH_ALL            (LL_AHB1_GRP1_PERIPH_ADC12 | LL_AHB1_GRP1_PERIPH_GPDMA1)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_ADF1           RCC_AHB2ENR_ADF1EN
+#define LL_AHB2_GRP1_PERIPH_MDF1           RCC_AHB2ENR_MDF1EN
+#define LL_AHB2_GRP1_PERIPH_RAMCFG         RCC_AHB2ENR_RAMCFGEN
+#define LL_AHB2_GRP1_PERIPH_ALL            (LL_AHB2_GRP1_PERIPH_ADF1 | LL_AHB2_GRP1_PERIPH_MDF1 | \
+                                            LL_AHB2_GRP1_PERIPH_RAMCFG)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#if defined(CRYP)
+#define LL_AHB3_GRP1_PERIPH_CRYP           RCC_AHB3ENR_CRYPEN
+#else
+#define LL_AHB3_GRP1_PERIPH_CRYP
+#endif /* CRYP */
+#define LL_AHB3_GRP1_PERIPH_HASH           RCC_AHB3ENR_HASHEN
+#define LL_AHB3_GRP1_PERIPH_IAC            RCC_AHB3ENR_IACEN
+#if defined(PKA)
+#define LL_AHB3_GRP1_PERIPH_PKA            RCC_AHB3ENR_PKAEN
+#else
+#define LL_AHB3_GRP1_PERIPH_PKA
+#endif /* PKA */
+#define LL_AHB3_GRP1_PERIPH_RIFSC          RCC_AHB3ENR_RIFSCEN
+#define LL_AHB3_GRP1_PERIPH_RISAF          RCC_AHB3ENR_RISAFEN
+#define LL_AHB3_GRP1_PERIPH_RNG            RCC_AHB3ENR_RNGEN
+#if defined(SAES)
+#define LL_AHB3_GRP1_PERIPH_SAES           RCC_AHB3ENR_SAESEN
+#else
+#define LL_AHB3_GRP1_PERIPH_SAES
+#endif /* SAES */
+#define LL_AHB3_GRP1_PERIPH_ALL            (LL_AHB3_GRP1_PERIPH_CRYP  | LL_AHB3_GRP1_PERIPH_HASH  | \
+                                            LL_AHB3_GRP1_PERIPH_IAC   | LL_AHB3_GRP1_PERIPH_PKA   | \
+                                            LL_AHB3_GRP1_PERIPH_RIFSC | LL_AHB3_GRP1_PERIPH_RISAF | \
+                                            LL_AHB3_GRP1_PERIPH_RNG   | LL_AHB3_GRP1_PERIPH_SAES)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN
+#define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN
+#define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN
+#define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN
+#define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN
+#define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN
+#define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN
+#define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN
+#define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN
+#define LL_AHB4_GRP1_PERIPH_GPION          RCC_AHB4ENR_GPIONEN
+#define LL_AHB4_GRP1_PERIPH_GPIOO          RCC_AHB4ENR_GPIOOEN
+#define LL_AHB4_GRP1_PERIPH_GPIOP          RCC_AHB4ENR_GPIOPEN
+#define LL_AHB4_GRP1_PERIPH_GPIOQ          RCC_AHB4ENR_GPIOQEN
+#define LL_AHB4_GRP1_PERIPH_PWR            RCC_AHB4ENR_PWREN
+#define LL_AHB4_GRP1_PERIPH_ALL            (LL_AHB4_GRP1_PERIPH_CRC   | LL_AHB4_GRP1_PERIPH_GPIOA | \
+                                            LL_AHB4_GRP1_PERIPH_GPIOB | LL_AHB4_GRP1_PERIPH_GPIOC | \
+                                            LL_AHB4_GRP1_PERIPH_GPIOD | LL_AHB4_GRP1_PERIPH_GPIOE | \
+                                            LL_AHB4_GRP1_PERIPH_GPIOF | LL_AHB4_GRP1_PERIPH_GPIOG | \
+                                            LL_AHB4_GRP1_PERIPH_GPIOH | LL_AHB4_GRP1_PERIPH_GPION | \
+                                            LL_AHB4_GRP1_PERIPH_GPIOO | LL_AHB4_GRP1_PERIPH_GPIOP | \
+                                            LL_AHB4_GRP1_PERIPH_GPIOQ | LL_AHB4_GRP1_PERIPH_PWR)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH  AHB5 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB5_GRP1_PERIPH_DMA2D             RCC_AHB5ENR_DMA2DEN
+#define LL_AHB5_GRP1_PERIPH_ETH1              RCC_AHB5ENR_ETH1EN
+#define LL_AHB5_GRP1_PERIPH_ETH1MAC           RCC_AHB5ENR_ETH1MACEN
+#define LL_AHB5_GRP1_PERIPH_ETH1TX            RCC_AHB5ENR_ETH1TXEN
+#define LL_AHB5_GRP1_PERIPH_ETH1RX            RCC_AHB5ENR_ETH1RXEN
+#define LL_AHB5_GRP1_PERIPH_FMC               RCC_AHB5ENR_FMCEN
+#define LL_AHB5_GRP1_PERIPH_GFXMMU            RCC_AHB5ENR_GFXMMUEN
+#define LL_AHB5_GRP1_PERIPH_GPU2D             RCC_AHB5ENR_GPU2DEN
+#define LL_AHB5_GRP1_PERIPH_HPDMA1            RCC_AHB5ENR_HPDMA1EN
+#define LL_AHB5_GRP1_PERIPH_XSPI1             RCC_AHB5ENR_XSPI1EN
+#define LL_AHB5_GRP1_PERIPH_XSPI2             RCC_AHB5ENR_XSPI2EN
+#define LL_AHB5_GRP1_PERIPH_XSPI3             RCC_AHB5ENR_XSPI3EN
+#define LL_AHB5_GRP1_PERIPH_XSPIM             RCC_AHB5ENR_XSPIMEN
+#define LL_AHB5_GRP1_PERIPH_JPEG              RCC_AHB5ENR_JPEGEN
+#define LL_AHB5_GRP1_PERIPH_MCE1              RCC_AHB5ENR_MCE1EN
+#define LL_AHB5_GRP1_PERIPH_MCE2              RCC_AHB5ENR_MCE2EN
+#define LL_AHB5_GRP1_PERIPH_MCE3              RCC_AHB5ENR_MCE3EN
+#define LL_AHB5_GRP1_PERIPH_MCE4              RCC_AHB5ENR_MCE4EN
+#define LL_AHB5_GRP1_PERIPH_CACHEAXI          RCC_AHB5ENR_CACHEAXIEN
+#define LL_AHB5_GRP1_PERIPH_NPU               RCC_AHB5ENR_NPUEN
+#define LL_AHB5_GRP1_PERIPH_OTG1              RCC_AHB5ENR_OTG1EN
+#define LL_AHB5_GRP1_PERIPH_OTG2              RCC_AHB5ENR_OTG2EN
+#define LL_AHB5_GRP1_PERIPH_OTGPHY1           RCC_AHB5ENR_OTGPHY1EN
+#define LL_AHB5_GRP1_PERIPH_OTGPHY2           RCC_AHB5ENR_OTGPHY2EN
+#define LL_AHB5_GRP1_PERIPH_OTG1PHYCTL        RCC_AHB5RSTR_OTG1PHYCTLRST
+#define LL_AHB5_GRP1_PERIPH_OTG2PHYCTL        RCC_AHB5RSTR_OTG2PHYCTLRST
+#define LL_AHB5_GRP1_PERIPH_PSSI              RCC_AHB5ENR_PSSIEN
+#define LL_AHB5_GRP1_PERIPH_SDMMC1            RCC_AHB5ENR_SDMMC1EN
+#define LL_AHB5_GRP1_PERIPH_SDMMC2            RCC_AHB5ENR_SDMMC2EN
+#define LL_AHB5_GRP1_PERIPH_ALL            (LL_AHB5_GRP1_PERIPH_DMA2D    | LL_AHB5_GRP1_PERIPH_ETH1    | \
+                                            LL_AHB5_GRP1_PERIPH_ETH1MAC  | LL_AHB5_GRP1_PERIPH_ETH1TX  | \
+                                            LL_AHB5_GRP1_PERIPH_ETH1RX   | LL_AHB5_GRP1_PERIPH_FMC     | \
+                                            LL_AHB5_GRP1_PERIPH_GFXMMU   | LL_AHB5_GRP1_PERIPH_GPU2D   | \
+                                            LL_AHB5_GRP1_PERIPH_HPDMA1   | LL_AHB5_GRP1_PERIPH_XSPI1   | \
+                                            LL_AHB5_GRP1_PERIPH_XSPI2    | LL_AHB5_GRP1_PERIPH_XSPI3   | \
+                                            LL_AHB5_GRP1_PERIPH_XSPIM    | LL_AHB5_GRP1_PERIPH_JPEG    | \
+                                            LL_AHB5_GRP1_PERIPH_MCE1     | LL_AHB5_GRP1_PERIPH_MCE2    | \
+                                            LL_AHB5_GRP1_PERIPH_MCE3     | LL_AHB5_GRP1_PERIPH_MCE4    | \
+                                            LL_AHB5_GRP1_PERIPH_CACHEAXI | LL_AHB5_GRP1_PERIPH_NPU     | \
+                                            LL_AHB5_GRP1_PERIPH_OTG1     | LL_AHB5_GRP1_PERIPH_OTG2    | \
+                                            LL_AHB5_GRP1_PERIPH_OTGPHY1  | LL_AHB5_GRP1_PERIPH_OTGPHY2 | \
+                                            LL_AHB5_GRP1_PERIPH_PSSI     | LL_AHB5_GRP1_PERIPH_SDMMC1  | \
+                                            LL_AHB5_GRP1_PERIPH_SDMMC2)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR1_I2C2EN
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN
+#define LL_APB1_GRP1_PERIPH_I3C1           RCC_APB1ENR1_I3C1EN
+#define LL_APB1_GRP1_PERIPH_I3C2           RCC_APB1ENR1_I3C2EN
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN
+#define LL_APB1_GRP1_PERIPH_SPDIFRX1       RCC_APB1ENR1_SPDIFRX1EN
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR1_SPI3EN
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR1_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR1_TIM4EN
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR1_TIM5EN
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR1_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR1_TIM7EN
+#define LL_APB1_GRP1_PERIPH_TIM10          RCC_APB1ENR1_TIM10EN
+#define LL_APB1_GRP1_PERIPH_TIM11          RCC_APB1ENR1_TIM11EN
+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR1_TIM12EN
+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR1_TIM13EN
+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR1_TIM14EN
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR1_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR1_USART3EN
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR1_UART4EN
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR1_UART5EN
+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR1_UART7EN
+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR1_UART8EN
+#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN
+#define LL_APB1_GRP1_PERIPH_ALL            (LL_APB1_GRP1_PERIPH_I2C1     | LL_APB1_GRP1_PERIPH_I2C2   | \
+                                            LL_APB1_GRP1_PERIPH_I2C3     | LL_APB1_GRP1_PERIPH_I3C1   | \
+                                            LL_APB1_GRP1_PERIPH_I3C2     | LL_APB1_GRP1_PERIPH_LPTIM1 | \
+                                            LL_APB1_GRP1_PERIPH_SPDIFRX1 | LL_APB1_GRP1_PERIPH_SPI2   | \
+                                            LL_APB1_GRP1_PERIPH_SPI3     | LL_APB1_GRP1_PERIPH_TIM2   | \
+                                            LL_APB1_GRP1_PERIPH_TIM3     | LL_APB1_GRP1_PERIPH_TIM4   | \
+                                            LL_APB1_GRP1_PERIPH_TIM5     | LL_APB1_GRP1_PERIPH_TIM6   | \
+                                            LL_APB1_GRP1_PERIPH_TIM7     | LL_APB1_GRP1_PERIPH_TIM10  | \
+                                            LL_APB1_GRP1_PERIPH_TIM11    | LL_APB1_GRP1_PERIPH_TIM12  | \
+                                            LL_APB1_GRP1_PERIPH_TIM13    | LL_APB1_GRP1_PERIPH_TIM14  | \
+                                            LL_APB1_GRP1_PERIPH_USART2   | LL_APB1_GRP1_PERIPH_USART3 | \
+                                            LL_APB1_GRP1_PERIPH_UART4    | LL_APB1_GRP1_PERIPH_UART5  | \
+                                            LL_APB1_GRP1_PERIPH_UART7    | LL_APB1_GRP1_PERIPH_UART8  | \
+                                            LL_APB1_GRP1_PERIPH_WWDG)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1ENR2_FDCANEN
+#define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1ENR2_MDIOSEN
+#define LL_APB1_GRP2_PERIPH_UCPD1          RCC_APB1ENR2_UCPD1EN
+#define LL_APB1_GRP2_PERIPH_ALL            (LL_APB1_GRP2_PERIPH_FDCAN | LL_APB1_GRP2_PERIPH_MDIOS | \
+                                            LL_APB1_GRP2_PERIPH_UCPD1)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
+#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
+#define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN
+#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_TIM9           RCC_APB2ENR_TIM9EN
+#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
+#define LL_APB2_GRP1_PERIPH_TIM18          RCC_APB2ENR_TIM18EN
+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN
+#define LL_APB2_GRP1_PERIPH_UART9          RCC_APB2ENR_UART9EN
+#define LL_APB2_GRP1_PERIPH_USART10        RCC_APB2ENR_USART10EN
+#define LL_APB2_GRP1_PERIPH_ALL            (LL_APB2_GRP1_PERIPH_SAI1   | LL_APB2_GRP1_PERIPH_SAI2   | \
+                                            LL_APB2_GRP1_PERIPH_SPI1   | LL_APB2_GRP1_PERIPH_SPI4   | \
+                                            LL_APB2_GRP1_PERIPH_SPI5   | LL_APB2_GRP1_PERIPH_TIM1   | \
+                                            LL_APB2_GRP1_PERIPH_TIM8   | LL_APB2_GRP1_PERIPH_TIM9   | \
+                                            LL_APB2_GRP1_PERIPH_TIM15  | LL_APB2_GRP1_PERIPH_TIM16  | \
+                                            LL_APB2_GRP1_PERIPH_TIM17  | LL_APB2_GRP1_PERIPH_TIM18  | \
+                                            LL_APB2_GRP1_PERIPH_USART1 | LL_APB2_GRP1_PERIPH_USART6 | \
+                                            LL_APB2_GRP1_PERIPH_UART9  | LL_APB2_GRP1_PERIPH_USART10)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB4_GRP1_PERIPH_HDP            RCC_APB4ENR1_HDPEN
+#define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR1_I2C4EN
+#define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR1_LPTIM2EN
+#define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR1_LPTIM3EN
+#define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR1_LPTIM4EN
+#define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR1_LPTIM5EN
+#define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR1_LPUART1EN
+#define LL_APB4_GRP1_PERIPH_RTC            RCC_APB4ENR1_RTCEN
+#define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR1_RTCAPBEN
+#define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR1_SPI6EN
+#define LL_APB4_GRP1_PERIPH_VREFBUF        RCC_APB4ENR1_VREFBUFEN
+#define LL_APB4_GRP1_PERIPH_ALL            (LL_APB4_GRP1_PERIPH_HDP     | LL_APB4_GRP1_PERIPH_I2C4    | \
+                                            LL_APB4_GRP1_PERIPH_LPTIM2  | LL_APB4_GRP1_PERIPH_LPTIM3  | \
+                                            LL_APB4_GRP1_PERIPH_LPTIM4  | LL_APB4_GRP1_PERIPH_LPTIM5  | \
+                                            LL_APB4_GRP1_PERIPH_LPUART1 | LL_APB4_GRP1_PERIPH_RTC     | \
+                                            LL_APB4_GRP1_PERIPH_RTCAPB  | LL_APB4_GRP1_PERIPH_SPI6    | \
+                                            LL_APB4_GRP1_PERIPH_VREFBUF)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB4_GRP2_PERIPH  APB4 GRP2 PERIPH
+  * @{
+  */
+#define LL_APB4_GRP2_PERIPH_BSEC           RCC_APB4ENR2_BSECEN
+#define LL_APB4_GRP2_PERIPH_DTS            RCC_APB4ENR2_DTSEN
+#define LL_APB4_GRP2_PERIPH_SYSCFG         RCC_APB4ENR2_SYSCFGEN
+#define LL_APB4_GRP2_PERIPH_ALL            (LL_APB4_GRP2_PERIPH_BSEC | LL_APB4_GRP2_PERIPH_DTS | \
+                                            LL_APB4_GRP2_PERIPH_SYSCFG)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB5_GRP1_PERIPH  APB5 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB5_GRP1_PERIPH_CSI            RCC_APB5ENR_CSIEN
+#define LL_APB5_GRP1_PERIPH_DCMIPP         RCC_APB5ENR_DCMIPPEN
+#define LL_APB5_GRP1_PERIPH_GFXTIM         RCC_APB5ENR_GFXTIMEN
+#define LL_APB5_GRP1_PERIPH_LTDC           RCC_APB5ENR_LTDCEN
+#if defined(VENC)
+#define LL_APB5_GRP1_PERIPH_VENC           RCC_APB5ENR_VENCEN
+#else
+#define LL_APB5_GRP1_PERIPH_VENC
+#endif /* VENC */
+#define LL_APB5_GRP1_PERIPH_ALL            (LL_APB5_GRP1_PERIPH_CSI    | LL_APB5_GRP1_PERIPH_DCMIPP | \
+                                            LL_APB5_GRP1_PERIPH_GFXTIM | LL_APB5_GRP1_PERIPH_LTDC   | \
+                                            LL_APB5_GRP1_PERIPH_VENC)
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_MISC  MISC
+  * @{
+  */
+#define LL_DBG                             RCC_MISCENR_DBGEN
+#define LL_MCO1                            RCC_MISCENR_MCO1EN
+#define LL_MCO2                            RCC_MISCENR_MCO2EN
+#define LL_XSPIPHYCOMP                     RCC_MISCENR_XSPIPHYCOMPEN
+#define LL_XSPIPHY1                        RCC_MISCRSTR_XSPIPHY1RST
+#define LL_XSPIPHY2                        RCC_MISCRSTR_XSPIPHY2RST
+#define LL_PER                             RCC_MISCENR_PEREN
+#define LL_SDMMC1DLL                       RCC_MISCRSTR_SDMMC1DLLRST
+#define LL_SDMMC2DLL                       RCC_MISCRSTR_SDMMC2DLLRST
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_BUS BUS
+  * @{
+  */
+
+/**
+  * @brief  Enable AXI bus clock.
+  * @rmtoll BUSENSR      ACLKNENS      LL_BUS_EnableClock\n
+  *         BUSENSR      ACLKNCENS     LL_BUS_EnableClock\n
+  *         BUSENSR      AHBMENS       LL_BUS_EnableClock\n
+  *         BUSENSR      AHB1ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      AHB2ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      AHB3ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      AHB4ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      AHB5ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      APB1ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      APB2ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      APB3ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      APB4ENS       LL_BUS_EnableClock\n
+  *         BUSENSR      APB5ENS       LL_BUS_EnableClock
+  * @param  Bus This parameter can be a combination of the following values:
+  *         @arg @ref LL_ACLKN
+  *         @arg @ref LL_ACLKNC
+  *         @arg @ref LL_AHBM
+  *         @arg @ref LL_AHB1
+  *         @arg @ref LL_AHB2
+  *         @arg @ref LL_AHB3
+  *         @arg @ref LL_AHB4
+  *         @arg @ref LL_AHB5
+  *         @arg @ref LL_APB1
+  *         @arg @ref LL_APB2
+  *         @arg @ref LL_APB3
+  *         @arg @ref LL_APB4
+  *         @arg @ref LL_APB5
+  * @retval None
+  */
+__STATIC_INLINE void LL_BUS_EnableClock(uint32_t Bus)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->BUSENSR, Bus);
+  /* Delay after an RCC bus clock enabling */
+  tmpreg = READ_REG(RCC->BUSENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AXI bus clock is enabled or not
+  * @rmtoll BUSENR       ACLKNEN       LL_BUS_IsEnabledClock\n
+  *         BUSENR       ACLKNCEN      LL_BUS_IsEnabledClock\n
+  *         BUSENR       AHBMEN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       AHB1EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       AHB2EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       AHB3EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       AHB4EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       AHB5EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       APB1EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       APB2EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       APB3EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       APB4EN        LL_BUS_IsEnabledClock\n
+  *         BUSENR       APB5EN        LL_BUS_IsEnabledClock
+  * @param  Bus This parameter can be a combination of the following values:
+  *         @arg @ref LL_ACLKN
+  *         @arg @ref LL_ACLKNC
+  *         @arg @ref LL_AHBM
+  *         @arg @ref LL_AHB1
+  *         @arg @ref LL_AHB2
+  *         @arg @ref LL_AHB3
+  *         @arg @ref LL_AHB4
+  *         @arg @ref LL_AHB5
+  *         @arg @ref LL_APB1
+  *         @arg @ref LL_APB2
+  *         @arg @ref LL_APB3
+  *         @arg @ref LL_APB4
+  *         @arg @ref LL_APB5
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_BUS_IsEnabledClock(uint32_t Bus)
+{
+  return ((READ_BIT(RCC->BUSENR, Bus) == Bus) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AXI bus clock.
+  * @rmtoll BUSENCR      ACLKNENC      LL_BUS_DisableClock\n
+  *         BUSENCR      ACLKNCENC     LL_BUS_DisableClock\n
+  *         BUSENCR      AHBMENC       LL_BUS_DisableClock\n
+  *         BUSENCR      AHB1ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      AHB2ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      AHB3ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      AHB4ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      AHB5ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      APB1ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      APB2ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      APB3ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      APB4ENC       LL_BUS_DisableClock\n
+  *         BUSENCR      APB5ENC       LL_BUS_DisableClock
+  * @param  Bus This parameter can be a combination of the following values:
+  *         @arg @ref LL_ACLKN
+  *         @arg @ref LL_ACLKNC
+  *         @arg @ref LL_AHBM
+  *         @arg @ref LL_AHB1
+  *         @arg @ref LL_AHB2
+  *         @arg @ref LL_AHB3
+  *         @arg @ref LL_AHB4
+  *         @arg @ref LL_AHB5
+  *         @arg @ref LL_APB1
+  *         @arg @ref LL_APB2
+  *         @arg @ref LL_APB3
+  *         @arg @ref LL_APB4
+  *         @arg @ref LL_APB5
+  * @retval None
+  */
+__STATIC_INLINE void LL_BUS_DisableClock(uint32_t Bus)
+{
+  WRITE_REG(RCC->BUSENCR, Bus);
+}
+
+/**
+  * @brief  Enable AXI bus clock during Low Power mode.
+  * @rmtoll BUSLPENSR    ACLKNLPENS    LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    ACLKNCLPENS   LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    AHBMLPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    AHB1LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    AHB2LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    AHB3LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    AHB4LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    AHB5LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    APB1LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    APB2LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    APB3LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    APB4LPENS     LL_BUS_EnableClockLowPower\n
+  *         BUSLPENSR    APB5LPENS     LL_BUS_EnableClockLowPower
+  * @param  Bus This parameter can be a combination of the following values:
+  *         @arg @ref LL_ACLKN
+  *         @arg @ref LL_ACLKNC
+  *         @arg @ref LL_AHBM
+  *         @arg @ref LL_AHB1
+  *         @arg @ref LL_AHB2
+  *         @arg @ref LL_AHB3
+  *         @arg @ref LL_AHB4
+  *         @arg @ref LL_AHB5
+  *         @arg @ref LL_APB1
+  *         @arg @ref LL_APB2
+  *         @arg @ref LL_APB3
+  *         @arg @ref LL_APB4
+  *         @arg @ref LL_APB5
+  * @retval None
+  */
+__STATIC_INLINE void LL_BUS_EnableClockLowPower(uint32_t Bus)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->BUSLPENSR, Bus);
+  /* Delay after an RCC bus clock enabling */
+  tmpreg = READ_REG(RCC->BUSLPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AXI bus clock during Low Power mode is enabled or not
+  * @rmtoll BUSLPENR       ACLKNLPEN       LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       ACLKNCLPEN      LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       AHBMLPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       AHB1LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       AHB2LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       AHB3LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       AHB4LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       AHB5LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       APB1LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       APB2LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       APB3LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       APB4LPEN        LL_BUS_IsEnabledClockLowPower\n
+  *         BUSLPENR       APB5LPEN        LL_BUS_IsEnabledClockLowPower
+  * @param  Bus This parameter can be a combination of the following values:
+  *         @arg @ref LL_ACLKN
+  *         @arg @ref LL_ACLKNC
+  *         @arg @ref LL_AHBM
+  *         @arg @ref LL_AHB1
+  *         @arg @ref LL_AHB2
+  *         @arg @ref LL_AHB3
+  *         @arg @ref LL_AHB4
+  *         @arg @ref LL_AHB5
+  *         @arg @ref LL_APB1
+  *         @arg @ref LL_APB2
+  *         @arg @ref LL_APB3
+  *         @arg @ref LL_APB4
+  *         @arg @ref LL_APB5
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_BUS_IsEnabledClockLowPower(uint32_t Bus)
+{
+  return ((READ_BIT(RCC->BUSLPENR, Bus) == Bus) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AXI bus clock during Low Power mode.
+  * @rmtoll BUSLPENCR    ACLKNLPENC    LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    ACLKNCLPENC   LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    AHBMLPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    AHB1LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    AHB2LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    AHB3LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    AHB4LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    AHB5LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    APB1LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    APB2LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    APB3LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    APB4LPENC     LL_BUS_DisableClockLowPower\n
+  *         BUSLPENCR    APB5LPENC     LL_BUS_DisableClockLowPower
+  * @param  Bus This parameter can be a combination of the following values:
+  *         @arg @ref LL_ACLKN
+  *         @arg @ref LL_ACLKNC
+  *         @arg @ref LL_AHBM
+  *         @arg @ref LL_AHB1
+  *         @arg @ref LL_AHB2
+  *         @arg @ref LL_AHB3
+  *         @arg @ref LL_AHB4
+  *         @arg @ref LL_AHB5
+  *         @arg @ref LL_APB1
+  *         @arg @ref LL_APB2
+  *         @arg @ref LL_APB3
+  *         @arg @ref LL_APB4
+  *         @arg @ref LL_APB5
+  * @retval None
+  */
+__STATIC_INLINE void LL_BUS_DisableClockLowPower(uint32_t Bus)
+{
+  WRITE_REG(RCC->BUSLPENCR, Bus);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_MEM MEM
+  * @{
+  */
+
+/**
+  * @brief  Enable memories clock.
+  * @rmtoll MEMENSR      AXISRAM1ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      AXISRAM2ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      AXISRAM3ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      AXISRAM4ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      AXISRAM5ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      AXISRAM6ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      AHBSRAM1ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      AHBSRAM2ENS   LL_MEM_EnableClock\n
+  *         MEMENSR      BKPSRAMENS    LL_MEM_EnableClock\n
+  *         MEMENSR      FLEXRAMENS    LL_MEM_EnableClock\n
+  *         MEMENSR      CACHEAXIRAMENS LL_MEM_EnableClock\n
+  *         MEMENSR      VENCRAMENS    LL_MEM_EnableClock
+  * @param  Memories This parameter can be a combination of the following values:
+  *         @arg @ref LL_MEM_AXISRAM1
+  *         @arg @ref LL_MEM_AXISRAM2
+  *         @arg @ref LL_MEM_AXISRAM3
+  *         @arg @ref LL_MEM_AXISRAM4
+  *         @arg @ref LL_MEM_AXISRAM5
+  *         @arg @ref LL_MEM_AXISRAM6
+  *         @arg @ref LL_MEM_AHBSRAM1
+  *         @arg @ref LL_MEM_AHBSRAM2
+  *         @arg @ref LL_MEM_BKPSRAM
+  *         @arg @ref LL_MEM_FLEXRAM
+  *         @arg @ref LL_MEM_CACHEAXIRAM
+  *         @arg @ref LL_MEM_VENCRAM
+  * @retval None
+  */
+__STATIC_INLINE void LL_MEM_EnableClock(uint32_t Memories)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->MEMENSR, Memories);
+  /* Delay after an RCC memories clock enabling */
+  tmpreg = READ_REG(RCC->MEMENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if memory clock is enabled or not
+  * @rmtoll MEMENR       AXISRAM1EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       AXISRAM2EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       AXISRAM3EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       AXISRAM4EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       AXISRAM5EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       AXISRAM6EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       AHBSRAM1EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       AHBSRAM2EN    LL_MEM_IsEnabledClock\n
+  *         MEMENR       BKPSRAMEN     LL_MEM_IsEnabledClock\n
+  *         MEMENR       FLEXRAMEN     LL_MEM_IsEnabledClock\n
+  *         MEMENR       CACHEAXIRAMEN LL_MEM_IsEnabledClock\n
+  *         MEMENR       VENCRAMEN     LL_MEM_IsEnabledClock
+  * @param  Memories This parameter can be a combination of the following values:
+  *         @arg @ref LL_MEM_AXISRAM1
+  *         @arg @ref LL_MEM_AXISRAM2
+  *         @arg @ref LL_MEM_AXISRAM3
+  *         @arg @ref LL_MEM_AXISRAM4
+  *         @arg @ref LL_MEM_AXISRAM5
+  *         @arg @ref LL_MEM_AXISRAM6
+  *         @arg @ref LL_MEM_AHBSRAM1
+  *         @arg @ref LL_MEM_AHBSRAM2
+  *         @arg @ref LL_MEM_BKPSRAM
+  *         @arg @ref LL_MEM_FLEXRAM
+  *         @arg @ref LL_MEM_CACHEAXIRAM
+  *         @arg @ref LL_MEM_VENCRAM
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_MEM_IsEnabledClock(uint32_t Memories)
+{
+  return ((READ_BIT(RCC->MEMENR, Memories) == Memories) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable memories clock.
+  * @rmtoll MEMENCR      AXISRAM1ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      AXISRAM2ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      AXISRAM3ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      AXISRAM4ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      AXISRAM5ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      AXISRAM6ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      AHBSRAM1ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      AHBSRAM2ENC   LL_MEM_DisableClock\n
+  *         MEMENCR      BKPSRAMENC    LL_MEM_DisableClock\n
+  *         MEMENCR      FLEXRAMENC    LL_MEM_DisableClock\n
+  *         MEMENCR      CACHEAXIRAMENC LL_MEM_DisableClock\n
+  *         MEMENCR      VENCRAMENC    LL_MEM_DisableClock
+  * @param  Memories This parameter can be a combination of the following values:
+  *         @arg @ref LL_MEM_AXISRAM1
+  *         @arg @ref LL_MEM_AXISRAM2
+  *         @arg @ref LL_MEM_AXISRAM3
+  *         @arg @ref LL_MEM_AXISRAM4
+  *         @arg @ref LL_MEM_AXISRAM5
+  *         @arg @ref LL_MEM_AXISRAM6
+  *         @arg @ref LL_MEM_AHBSRAM1
+  *         @arg @ref LL_MEM_AHBSRAM2
+  *         @arg @ref LL_MEM_BKPSRAM
+  *         @arg @ref LL_MEM_FLEXRAM
+  *         @arg @ref LL_MEM_CACHEAXIRAM
+  *         @arg @ref LL_MEM_VENCRAM
+  * @retval None
+  */
+__STATIC_INLINE void LL_MEM_DisableClock(uint32_t Memories)
+{
+  WRITE_REG(RCC->MEMENCR, Memories);
+}
+
+/**
+  * @brief  Enable memories clock during Low Power mode.
+  * @rmtoll MEMLPENSR    AXISRAM1LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    AXISRAM2LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    AXISRAM3LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    AXISRAM4LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    AXISRAM5LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    AXISRAM6LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    AHBSRAM1LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    AHBSRAM2LPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    BKPSRAMLPENS  LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    FLEXRAMLPENS  LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    CACHEAXIRAMLPENS LL_MEM_EnableClockLowPower\n
+  *         MEMLPENSR    VENCRAMLPENS  LL_MEM_EnableClockLowPower
+  * @param  Memories This parameter can be a combination of the following values:
+  *         @arg @ref LL_MEM_AXISRAM1
+  *         @arg @ref LL_MEM_AXISRAM2
+  *         @arg @ref LL_MEM_AXISRAM3
+  *         @arg @ref LL_MEM_AXISRAM4
+  *         @arg @ref LL_MEM_AXISRAM5
+  *         @arg @ref LL_MEM_AXISRAM6
+  *         @arg @ref LL_MEM_AHBSRAM1
+  *         @arg @ref LL_MEM_AHBSRAM2
+  *         @arg @ref LL_MEM_BKPSRAM
+  *         @arg @ref LL_MEM_FLEXRAM
+  *         @arg @ref LL_MEM_CACHEAXIRAM
+  *         @arg @ref LL_MEM_VENCRAM
+  * @retval None
+  */
+__STATIC_INLINE void LL_MEM_EnableClockLowPower(uint32_t Memories)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->MEMLPENSR, Memories);
+  /* Delay after an RCC memories clock enabling */
+  tmpreg = READ_REG(RCC->MEMLPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if memories clock during Low Power mode is enabled or not .
+  * @rmtoll MEMLPENR      AXISRAM1LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      AXISRAM2LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      AXISRAM3LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      AXISRAM4LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      AXISRAM5LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      AXISRAM6LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      AHBSRAM1LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      AHBSRAM2LPEN    LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      BKPSRAMLPEN     LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      FLEXRAMLPEN     LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      CACHEAXIRAMLPEN LL_MEM_IsEnabledClockLowPower\n
+  *         MEMLPENR      VENCRAMLPEN     LL_MEM_IsEnabledClockLowPower
+  * @param  Memories This parameter can be a combination of the following values:
+  *         @arg @ref LL_MEM_AXISRAM1
+  *         @arg @ref LL_MEM_AXISRAM2
+  *         @arg @ref LL_MEM_AXISRAM3
+  *         @arg @ref LL_MEM_AXISRAM4
+  *         @arg @ref LL_MEM_AXISRAM5
+  *         @arg @ref LL_MEM_AXISRAM6
+  *         @arg @ref LL_MEM_AHBSRAM1
+  *         @arg @ref LL_MEM_AHBSRAM2
+  *         @arg @ref LL_MEM_BKPSRAM
+  *         @arg @ref LL_MEM_FLEXRAM
+  *         @arg @ref LL_MEM_CACHEAXIRAM
+  *         @arg @ref LL_MEM_VENCRAM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_MEM_IsEnabledClockLowPower(uint32_t Memories)
+{
+  return ((READ_BIT(RCC->MEMLPENR, Memories) == Memories) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable memories clock during Low Power mode.
+  * @rmtoll MEMLPENCR    AXISRAM1LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    AXISRAM2LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    AXISRAM3LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    AXISRAM4LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    AXISRAM5LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    AXISRAM6LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    AHBSRAM1LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    AHBSRAM2LPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    BKPSRAMLPENC  LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    FLEXRAMLPENC  LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    CACHEAXIRAMLPENC LL_MEM_DisableClockLowPower\n
+  *         MEMLPENCR    VENCRAMLPENC  LL_MEM_DisableClockLowPower
+  * @param  Memories This parameter can be a combination of the following values:
+  *         @arg @ref LL_MEM_AXISRAM1
+  *         @arg @ref LL_MEM_AXISRAM2
+  *         @arg @ref LL_MEM_AXISRAM3
+  *         @arg @ref LL_MEM_AXISRAM4
+  *         @arg @ref LL_MEM_AXISRAM5
+  *         @arg @ref LL_MEM_AXISRAM6
+  *         @arg @ref LL_MEM_AHBSRAM1
+  *         @arg @ref LL_MEM_AHBSRAM2
+  *         @arg @ref LL_MEM_BKPSRAM
+  *         @arg @ref LL_MEM_FLEXRAM
+  *         @arg @ref LL_MEM_CACHEAXIRAM
+  *         @arg @ref LL_MEM_VENCRAM
+  * @retval None
+  */
+__STATIC_INLINE void LL_MEM_DisableClockLowPower(uint32_t Memories)
+{
+  WRITE_REG(RCC->MEMLPENCR, Memories);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENSR     GPDMA1ENS     LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENSR     ADC12ENS      LL_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB1ENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB1ENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      GPDMA1EN      LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENCR     GPDMA1ENC     LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENCR     ADC12ENC      LL_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB1ENCR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTSR    GPDMA1RSTS    LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTSR    ADC12RSTS     LL_AHB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB1RSTSR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTCR    GPDMA1RSTC    LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTCR    ADC12RSTC     LL_AHB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB1RSTCR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripherals clock during Low Power mode.
+  * @rmtoll AHB1LPENSR   GPDMA1LPENS   LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENSR   ADC12LPENS    LL_AHB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB1LPENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB1LPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll AHB1LPENR    GPDMA1LPEN    LL_AHB1_GRP1_IsEnabledClockLowPower\n
+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB1LPENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock during Low Power mode.
+  * @rmtoll AHB1LPENCR   GPDMA1LPENC   LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENCR   ADC12LPENC    LL_AHB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB1LPENCR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENSR     RAMCFGENS     LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENSR     MDF1ENS       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENSR     ADF1ENS       LL_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB2ENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB2ENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      RAMCFGEN      LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      MDF1EN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      ADF1EN        LL_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENCR     RAMCFGENC     LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENCR     MDF1ENC       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENCR     ADF1ENC       LL_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB2ENCR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTSR    RAMCFGRSTS     LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTSR    MDF1RSTS       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTSR    ADF1RSTS       LL_AHB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB2RSTSR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTCR     RAMCFGRSTC    LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTCR     MDF1RSTC      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTCR     ADF1RSTC      LL_AHB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB2RSTCR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripherals clock during Low Power mode.
+  * @rmtoll AHB2LPENSR   RAMCFGLPENC   LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENSR   MDF1LPENC     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENSR   ADF1LPENC     LL_AHB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB2LPENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB2LPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll AHB2LPENR    RAMCFGLPEN    LL_AHB2_GRP1_IsEnabledClockLowPower\n
+  *         AHB2LPENR    MDF1LPEN      LL_AHB2_GRP1_IsEnabledClockLowPower\n
+  *         AHB2LPENR    ADF1LPEN      LL_AHB2_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock during Low Power mode.
+  * @rmtoll AHB2LPENCR   RAMCFGLPENC   LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENCR   MDF1LPENC     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENCR   ADF1LPENC     LL_AHB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RAMCFG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_MDF1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB2LPENCR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENSR     RNGENS        LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENSR     HASHENS       LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENSR     CRYPENS       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENSR     SAESENS       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENSR     PKAENS        LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENSR     RIFSCENS      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENSR     RISAFENS      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENSR     IACENS        LL_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB3ENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB3ENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      RNGEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      HASHEN        LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      CRYPEN        LL_AHB3_GRP1_IsEnabledClock\n  (*)
+  *         AHB3ENR      SAESEN        LL_AHB3_GRP1_IsEnabledClock\n  (*)
+  *         AHB3ENR      PKAEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      RIFSCEN       LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      RISAFEN       LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      IACEN         LL_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENCR     RNGENC        LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENCR     HASHENC       LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENCR     CRYPENC       LL_AHB3_GRP1_DisableClock\n  (*)
+  *         AHB3ENCR     SAESENC       LL_AHB3_GRP1_DisableClock\n  (*)
+  *         AHB3ENCR     PKAENC        LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENCR     RIFSCENC      LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENCR     RISAFENC      LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENCR     IACENC        LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB3ENCR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTSR    RNGRSTS       LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTSR    HASHRSTS      LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTSR    CRYPRSTS      LL_AHB3_GRP1_ForceReset\n  (*)
+  *         AHB3RSTSR    SAESRSTS      LL_AHB3_GRP1_ForceReset\n  (*)
+  *         AHB3RSTSR    PKARSTS       LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTSR    IACRSTS       LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB3RSTSR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTCR    RNGRSTC       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTCR    HASHRSTC      LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTCR    CRYPRSTC      LL_AHB3_GRP1_ReleaseReset\n  (*)
+  *         AHB3RSTCR    SAESRSTC      LL_AHB3_GRP1_ReleaseReset\n  (*)
+  *         AHB3RSTCR    PKARSTC       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTCR    IACRSTC       LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB3RSTCR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripherals clock during Low Power mode.
+  * @rmtoll AHB3LPENSR   RNGLPENS      LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENSR   HASHLPENS     LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENSR   CRYPLPENS     LL_AHB3_GRP1_EnableClockLowPower\n  (*)
+  *         AHB3LPENSR   SAESLPENS     LL_AHB3_GRP1_EnableClockLowPower\n  (*)
+  *         AHB3LPENSR   PKALPENS      LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENSR   RIFSCLPENS    LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENSR   RISAFLPENS    LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENSR   IACLPENS      LL_AHB3_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB3LPENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB3LPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll AHB3LPENR    RNGLPEN       LL_AHB3_GRP1_IsEnabledClockLowPower\n
+  *         AHB3LPENR    HASHLPEN      LL_AHB3_GRP1_IsEnabledClockLowPower\n
+  *         AHB3LPENR    CRYPLPEN      LL_AHB3_GRP1_IsEnabledClockLowPower\n  (*)
+  *         AHB3LPENR    SAESLPEN      LL_AHB3_GRP1_IsEnabledClockLowPower\n  (*)
+  *         AHB3LPENR    PKALPEN       LL_AHB3_GRP1_IsEnabledClockLowPower\n
+  *         AHB3LPENR    RIFSCLPEN     LL_AHB3_GRP1_IsEnabledClockLowPower\n
+  *         AHB3LPENR    RISAFLPEN     LL_AHB3_GRP1_IsEnabledClockLowPower\n
+  *         AHB3LPENR    IACLPEN       LL_AHB3_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB3LPENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock during Low Power mode.
+  * @rmtoll AHB3LPENCR   RNGLPENC      LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENCR   HASHLPENC     LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENCR   CRYPLPENC     LL_AHB3_GRP1_DisableClockLowPower\n  (*)
+  *         AHB3LPENCR   SAESLPENC     LL_AHB3_GRP1_DisableClockLowPower\n  (*)
+  *         AHB3LPENCR   PKALPENC      LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENCR   RIFSCLPENC    LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENCR   RISAFLPENC    LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENCR   IACLPENC      LL_AHB3_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_HASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SAES (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_PKA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RIFSC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_RISAF
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IAC
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB3LPENCR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB4 peripherals clock.
+  * @rmtoll AHB4ENSR     GPIOAENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOBENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOCENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIODENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOEENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOFENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOGENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOHENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIONENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOOENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOPENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     GPIOQENS      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     PWRENS        LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENSR     CRCENS        LL_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB4ENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB4ENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIONEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOOEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOPEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOQEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      PWREN         LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock.
+  * @rmtoll AHB4ENCR     GPIOAENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOBENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOCENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIODENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOEENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOFENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOGENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOHENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIONENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOOENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOPENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     GPIOQENC      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     PWRENC        LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENCR     CRCENC        LL_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB4ENCR, Periphs);
+}
+
+/**
+  * @brief  Force AHB4 peripherals reset.
+  * @rmtoll AHB4RSTSR     GPIOARSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOBRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOCRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIODRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOERSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOFRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOGRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOHRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIONRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOORSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOPRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     GPIOQRSTS      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     CRCRSTS        LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTSR     BKPRAMRSTS     LL_AHB4_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB4RSTSR, Periphs);
+}
+
+/**
+  * @brief  Release AHB4 peripherals reset.
+  * @rmtoll AHB4RSTCR     GPIOARSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOBRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOCRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIODRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOERSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOFRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOGRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOHRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIONRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOORSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOPRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     GPIOQRSTC      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     CRCRSTC        LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTCR     BKPRAMRSTC     LL_AHB4_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB4RSTCR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB4 peripherals clock during Low Power mode.
+  * @rmtoll AHB4LPENSR    GPIOALPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOBLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOCLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIODLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOELPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOFLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOGLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOHLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIONLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOOLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOPLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    GPIOQLPENS     LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    CRCLPENS       LL_AHB4_GRP1_EnableClockLowPower\n
+  *         AHB4LPENSR    BKPRAMLPENS    LL_AHB4_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB4LPENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB4LPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB4 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll AHB4LPENR     GPIOALPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOBLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOCLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIODLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOELPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOFLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOGLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOHLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIONLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOOLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOPLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     GPIOQLPEN      LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     PWRLPEN        LL_AHB4_GRP1_IsEnabledClockLowPower\n
+  *         AHB4LPENR     CRCLPEN        LL_AHB4_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB4LPENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock during Low Power mode.
+  * @rmtoll AHB4LPENCR    GPIOALPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOBLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOCLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIODLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOELPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOFLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOGLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOHLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIONLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOOLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOPLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    GPIOQLPENC     LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    PWRLPENC       LL_AHB4_GRP1_DisableClockLowPower\n
+  *         AHB4LPENCR    CRCLPENC       LL_AHB4_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPION
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOO
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOP
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOQ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_PWR
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB4LPENCR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB5 AHB5
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB5 peripherals clock.
+  * @rmtoll AHB5ENSR     HPDMA1ENS     LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     DMA2DENS      LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     JPEGENS       LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     FMCENS        LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     XSPI1ENS      LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     PSSIENS       LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     SDMMC2ENS     LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     SDMMC1ENS     LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     XSPI2ENS      LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     XSPIMENS      LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     MCE1ENS       LL_AHB5_GRP1_EnableClock\n (*)
+  *         AHB5ENSR     MCE2ENS       LL_AHB5_GRP1_EnableClock\n (*)
+  *         AHB5ENSR     MCE3ENS       LL_AHB5_GRP1_EnableClock\n (*)
+  *         AHB5ENSR     XSPI3ENS      LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     MCE4ENS       LL_AHB5_GRP1_EnableClock\n (*)
+  *         AHB5ENSR     GFXMMUENS     LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     GPU2DENS      LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     ETH1MACENS    LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     ETH1TXENS     LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     ETH1RXENS     LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     ETH1ENS       LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     OTG1ENS       LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     OTGPHY1ENS    LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     OTGPHY2ENS    LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     OTG2ENS       LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     CACHEAXIENS   LL_AHB5_GRP1_EnableClock\n
+  *         AHB5ENSR     NPUENS        LL_AHB5_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB5ENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB5ENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB5 peripheral clock is enabled or not
+  * @rmtoll AHB5ENR      HPDMA1EN      LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      DMA2DEN       LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      JPEGEN        LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      FMCEN         LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      XSPI1EN       LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      PSSIEN        LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      SDMMC2EN      LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      SDMMC1EN      LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      XSPI2EN       LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      XSPIMEN       LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      MCE1EN        LL_AHB5_GRP1_IsEnabledClock\n (*)
+  *         AHB5ENR      MCE2EN        LL_AHB5_GRP1_IsEnabledClock\n (*)
+  *         AHB5ENR      MCE3EN        LL_AHB5_GRP1_IsEnabledClock\n (*)
+  *         AHB5ENR      XSPI3EN       LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      MCE4EN        LL_AHB5_GRP1_IsEnabledClock\n (*)
+  *         AHB5ENR      GFXMMUEN      LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      GPU2DEN       LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      ETH1MACEN     LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      ETH1TXEN      LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      ETH1RXEN      LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      ETH1EN        LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      OTG1EN        LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      OTGPHY1EN     LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      OTGPHY2EN     LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      OTG2EN        LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      CACHEAXIEN    LL_AHB5_GRP1_IsEnabledClock\n
+  *         AHB5ENR      NPUEN         LL_AHB5_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB5 peripherals clock.
+  * @rmtoll AHB5ENCR     HPDMA1ENC     LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     DMA2DENC      LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     JPEGENC       LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     FMCENC        LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     XSPI1ENC      LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     PSSIENC       LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     SDMMC2ENC     LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     SDMMC1ENC     LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     XSPI2ENC      LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     XSPIMENC      LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     MCE1ENC       LL_AHB5_GRP1_DisableClock\n (*)
+  *         AHB5ENCR     MCE2ENC       LL_AHB5_GRP1_DisableClock\n (*)
+  *         AHB5ENCR     MCE3ENC       LL_AHB5_GRP1_DisableClock\n (*)
+  *         AHB5ENCR     XSPI3ENC      LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     MCE4ENC       LL_AHB5_GRP1_DisableClock\n (*)
+  *         AHB5ENCR     GFXMMUENC     LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     GPU2DENC      LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     ETH1MACENC    LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     ETH1TXENC     LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     ETH1RXENC     LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     ETH1ENC       LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     OTG1ENC       LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     OTGPHY1ENC    LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     OTGPHY2ENC    LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     OTG2ENC       LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     CACHEAXIENC   LL_AHB5_GRP1_DisableClock\n
+  *         AHB5ENCR     NPUENC        LL_AHB5_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB5ENCR, Periphs);
+}
+
+/**
+  * @brief  Force AHB5 peripherals reset.
+  * @rmtoll AHB5RSTSR    HPDMA1RSTS      LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    DMA2DRSTS       LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    JPEGRSTS        LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    FMCRSTS         LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    XSPI1RSTS       LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    PSSIRSTS        LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    SDMMC2RSTS      LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    SDMMC1RSTS      LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    XSPI2RSTS       LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    XSPIMRSTS       LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    XSPI3RSTS       LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    GFXMMURSTS      LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    GPU2DRSTS       LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    OTG1PHYCTLRSTS  LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    OTG2PHYCTLRSTS  LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    ETH1RSTS        LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    OTG1RSTS        LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    OTGPHY1RSTS     LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    OTGPHY2RSTS     LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    OTG2RSTS        LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    CACHEAXIRSTS    LL_AHB5_GRP1_ForceReset\n
+  *         AHB5RSTSR    NPURSTS         LL_AHB5_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1PHYCTL
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2PHYCTL
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB5RSTSR, Periphs);
+}
+
+/**
+  * @brief  Release AHB5 peripherals reset.
+  * @rmtoll AHB5RSTCR    HPDMA1RSTC      LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    DMA2DRSTC       LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    JPEGRSTC        LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    FMCRSTC         LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    XSPI1RSTC       LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    PSSIRSTC        LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    SDMMC2RSTC      LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    SDMMC1RSTC      LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    XSPI2RSTC       LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    XSPIMRSTC       LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    XSPI3RSTC       LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    GFXMMURSTC      LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    GPU2DRSTC       LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    OTG1PHYCTLRSTC  LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    OTG2PHYCTLRSTC  LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    ETH1RSTC        LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    OTG1RSTC        LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    OTGPHY1RSTC     LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    OTGPHY2RSTC     LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    OTG2RSTC        LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    CACHEAXIRSTC    LL_AHB5_GRP1_ReleaseReset\n
+  *         AHB5RSTCR    NPURSTS         LL_AHB5_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1PHYCTL
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2PHYCTL
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB5RSTCR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB5 peripherals clock during Low Power mode.
+  * @rmtoll AHB5LPENSR   HPDMA1LPENS   LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   DMA2DLPENS    LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   JPEGLPENS     LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   FMCLPENS      LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   XSPI1LPENS    LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   PSSILPENS     LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   SDMMC2LPENS   LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   SDMMC1LPENS   LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   XSPI2LPENS    LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   XSPIMLPENS    LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   MCE1LPENS     LL_AHB5_GRP1_EnableClockLowPower\n (*)
+  *         AHB5LPENSR   MCE2LPENS     LL_AHB5_GRP1_EnableClockLowPower\n (*)
+  *         AHB5LPENSR   MCE3LPENS     LL_AHB5_GRP1_EnableClockLowPower\n (*)
+  *         AHB5LPENSR   XSPI3LPENS    LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   MCE4LPENS     LL_AHB5_GRP1_EnableClockLowPower\n (*)
+  *         AHB5LPENSR   GFXMMULPENS   LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   GPU2DLPENS    LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   ETH1MACLPENS  LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   ETH1TXLPENS   LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   ETH1RXLPENS   LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   ETH1LPENS     LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   OTG1LPENS     LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   OTGPHY1LPENS  LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   OTGPHY2LPENS  LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   OTG2LPENS     LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   CACHEAXILPENS LL_AHB5_GRP1_EnableClockLowPower\n
+  *         AHB5LPENSR   NPULPENS      LL_AHB5_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB5_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->AHB5LPENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->AHB5LPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB5 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll AHB5LPENR    HPDMA1LPEN    LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    DMA2DLPEN     LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    JPEGLPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    FMCLPEN       LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    XSPI1LPEN     LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    PSSILPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    SDMMC2LPEN    LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    SDMMC1LPEN    LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    XSPI2LPEN     LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    XSPIMLPEN     LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    MCE1LPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
+  *         AHB5LPENR    MCE2LPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
+  *         AHB5LPENR    MCE3LPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
+  *         AHB5LPENR    XSPI3LPEN     LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    MCE4LPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n (*)
+  *         AHB5LPENR    GFXMMULPEN    LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    GPU2DLPEN     LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    ETH1MACLPEN   LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    ETH1TXLPEN    LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    ETH1RXLPEN    LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    ETH1LPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    OTG1LPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    OTGPHY1LPEN   LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    OTGPHY2LPEN   LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    OTG2LPEN      LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    CACHEAXILPEN  LL_AHB5_GRP1_IsEnabledClockLowPower\n
+  *         AHB5LPENR    NPULPEN       LL_AHB5_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB5LPENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable AHB5 peripherals clock during Low Power mode.
+  * @rmtoll AHB5LPENCR   HPDMA1LPENC   LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   DMA2DLPENC    LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   JPEGLPENC     LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   FMCLPENC      LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   XSPI1LPENC    LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   PSSILPENC     LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   SDMMC2LPENC   LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   SDMMC1LPENC   LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   XSPI2LPENC    LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   XSPIMLPENC    LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   MCE1LPENC     LL_AHB5_GRP1_DisableClockLowPower\n (*)
+  *         AHB5LPENCR   MCE2LPENC     LL_AHB5_GRP1_DisableClockLowPower\n (*)
+  *         AHB5LPENCR   MCE3LPENC     LL_AHB5_GRP1_DisableClockLowPower\n (*)
+  *         AHB5LPENCR   XSPI3LPENC    LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   MCE4LPENC     LL_AHB5_GRP1_DisableClockLowPower\n (*)
+  *         AHB5LPENCR   GFXMMULPENC   LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   GPU2DLPENC    LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   ETH1MACLPENC  LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   ETH1TXLPENC   LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   ETH1RXLPENC   LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   ETH1LPENC     LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   OTG1LPENC     LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   OTGPHY1LPENC  LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   OTGPHY2LPENC  LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   OTG2LPENC     LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   CACHEAXILPENC LL_AHB5_GRP1_DisableClockLowPower\n
+  *         AHB5LPENCR   NPULPENC      LL_AHB5_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_HPDMA1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_JPEG
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPI3
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_XSPIM
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_PSSI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE1 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE2 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE3 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_MCE4 (*)
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GFXMMU
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_GPU2D
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTG2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY1
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_OTGPHY2
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_CACHEAXI
+  *         @arg @ref LL_AHB5_GRP1_PERIPH_NPU
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_AHB5_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->AHB5LPENCR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENSR1    TIM2ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM3ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM4ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM5ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM6ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM7ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM12ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM13ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM14ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    LPTIM1ENS     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    WWDGENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM10ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    TIM11ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    SPI2ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    SPI3ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    SPDIFRX1ENS   LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    USART2ENS     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    USART3ENS     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    UART4ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    UART5ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    I2C1ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    I2C2ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    I2C3ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    I3C1ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    I3C2ENS       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    UART7ENS      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENSR1    UART8ENS      LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB1ENSR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB1ENR1);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM10EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     TIM11EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     SPDIFRX1EN    LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I3C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     I3C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR1     UART8EN       LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENCR1    TIM2ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM3ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM4ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM5ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM6ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM7ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM12ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM13ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM14ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    LPTIM1ENC     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM10ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    TIM11ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    SPI2ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    SPI3ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    SPDIFRX1ENC   LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    USART2ENC     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    USART3ENC     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    UART4ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    UART5ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    I2C1ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    I2C2ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    I2C3ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    I3C1ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    I3C2ENC       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    UART7ENC      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENCR1    UART8ENC      LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1ENCR1, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTSR1   TIM2RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM3RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM4RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM5RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM6RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM7RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM12RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM13RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM14RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   LPTIM1RSTS    LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM10RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   TIM11RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   SPI2RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   SPI3RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   SPDIFRX1RSTS  LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   USART2RSTS    LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   USART3RSTS    LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   UART4RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   UART5RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   I2C1RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   I2C2RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   I2C3RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   I3C1RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   I3C2RSTS      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   UART7RSTS     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTSR1   UART8RSTS     LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1RSTSR1, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTCR1   TIM2RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM3RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM4RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM5RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM6RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM7RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM12RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM13RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM14RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   LPTIM1RSTC    LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM10RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   TIM11RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   SPI2RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   SPI3RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   SPDIFRX1RSTC  LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   USART2RSTC    LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   USART3RSTC    LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   UART4RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   UART5RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   I2C1RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   I2C2RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   I2C3RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   I3C1RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   I3C2RSTC      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   UART7RSTC     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTCR1   UART8RSTC     LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1RSTCR1, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power mode.
+  * @rmtoll APB1LPENSR1  TIM2LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM3LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM4LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM5LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM6LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM7LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM12LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM13LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM14LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  LPTIM1LPENS   LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  WWDGLPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM10LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  TIM11LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  SPI2LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  SPI3LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  SPDIFRX1LPENS LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  USART2LPENS   LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  USART3LPENS   LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  UART4LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  UART5LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  I2C1LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  I2C2LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  I2C3LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  I3C1LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  I3C2LPENS     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  UART7LPENS    LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENSR1  UART8LPENS    LL_APB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB1LPENSR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB1LPENR1);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll APB1LPENR1   TIM2LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM3LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM4LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM5LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM6LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM7LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM12LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM13LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM14LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   LPTIM1LPEN    LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   WWDGLPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM10LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   TIM11LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   SPI2LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   SPI3LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   SPDIFRX1LPEN  LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   USART2LPEN    LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   USART3LPEN    LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   UART4LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   UART5LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   I2C1LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   I2C2LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   I2C3LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   I3C1LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   I3C2LPEN      LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   UART7LPEN     LL_APB1_GRP1_IsEnabledClockLowPower\n
+  *         APB1LPENR1   UART8LPEN     LL_APB1_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1LPENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power mode.
+  * @rmtoll APB1LPENCR1  TIM2LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM3LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM4LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM5LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM6LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM7LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM12LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM13LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM14LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  LPTIM1LPENC   LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  WWDGLPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM10LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  TIM11LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  SPI2LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  SPI3LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  SPDIFRX1LPENC LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  USART2LPENC   LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  USART3LPENC   LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  UART4LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  UART5LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  I2C1LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  I2C2LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  I2C3LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  I3C1LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  I3C2LPENC     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  UART7LPENC    LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENCR1  UART8LPENC    LL_APB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I3C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM10
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1LPENCR1, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENSR2    MDIOSENS      LL_APB1_GRP2_EnableClock\n
+  *         APB1ENSR2    FDCANENS      LL_APB1_GRP2_EnableClock\n
+  *         APB1ENSR2    UCPD1ENS      LL_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB1ENSR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB1ENR2);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR2     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1ENR2     FDCANEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1ENR2     UCPD1EN       LL_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENCR2    MDIOSENC      LL_APB1_GRP2_DisableClock\n
+  *         APB1ENCR2    FDCANENC      LL_APB1_GRP2_DisableClock\n
+  *         APB1ENCR2    UCPD1ENC      LL_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1ENCR2, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTSR2   MDIOSRSTS     LL_APB1_GRP2_ForceReset\n
+  *         APB1RSTSR2   FDCANRSTS     LL_APB1_GRP2_ForceReset\n
+  *         APB1RSTSR2   UCPD1RSTS     LL_APB1_GRP2_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1RSTSR2, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTCR2   MDIOSRSTC     LL_APB1_GRP2_ReleaseReset\n
+  *         APB1RSTCR2   FDCANRSTC     LL_APB1_GRP2_ReleaseReset\n
+  *         APB1RSTCR2   UCPD1RSTC     LL_APB1_GRP2_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1RSTCR2, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power mode.
+  * @rmtoll APB1LPENSR2  MDIOSLPENS    LL_APB1_GRP2_EnableClockLowPower\n
+  *         APB1LPENSR2  FDCANLPENS    LL_APB1_GRP2_EnableClockLowPower\n
+  *         APB1LPENSR2  UCPD1LPENS    LL_APB1_GRP2_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB1LPENSR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB1LPENR2);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll APB1LPENR2   MDIOSLPEN     LL_APB1_GRP2_IsEnabledClockLowPower\n
+  *         APB1LPENR2   FDCANLPEN     LL_APB1_GRP2_IsEnabledClockLowPower\n
+  *         APB1LPENR2   UCPD1LPEN     LL_APB1_GRP2_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1LPENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power mode.
+  * @rmtoll APB1LPENCR2  MDIOSLPENC    LL_APB1_GRP2_DisableClockLowPower\n
+  *         APB1LPENCR2  FDCANLPENC    LL_APB1_GRP2_DisableClockLowPower\n
+  *         APB1LPENCR2  UCPD1LPENC    LL_APB1_GRP2_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB1LPENCR2, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENSR     TIM1ENS       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     TIM8ENS       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     USART1ENS     LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     USART6ENS     LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     UART9ENS      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     USART10ENS    LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     SPI1ENS       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     SPI4ENS       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     TIM18ENS      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     TIM15ENS      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     TIM16ENS      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     TIM17ENS      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     TIM9ENS       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     SPI5ENS       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     SAI1ENS       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENSR     SAI2ENS       LL_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB2ENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB2ENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM18EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENCR     TIM1ENC       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     TIM8ENC       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     USART1ENC     LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     USART6ENC     LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     UART9ENC      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     USART10ENC    LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     SPI1ENC       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     SPI4ENC       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     TIM18ENC      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     TIM15ENC      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     TIM16ENC      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     TIM17ENC      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     TIM9ENC       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     SPI5ENC       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     SAI1ENC       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENCR     SAI2ENC       LL_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB2ENCR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTSR    TIM1RSTS      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    TIM8RSTS      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    USART1RSTS    LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    USART6RSTS    LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    UART9RSTS     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    USART10RSTS   LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    SPI1RSTS      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    SPI4RSTS      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    TIM18RSTS     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    TIM15RSTS     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    TIM16RSTS     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    TIM17RSTS     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    TIM9RSTS      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    SPI5RSTS      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    SAI1RSTS      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTSR    SAI2RSTS      LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB2RSTSR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTCR    TIM1RSTC      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    TIM8RSTC      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    USART1RSTC    LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    USART6RSTC    LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    UART9RSTC     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    USART10RSTC   LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    SPI1RSTC      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    SPI4RSTC      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    TIM18RSTC     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    TIM15RSTC     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    TIM16RSTC     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    TIM17RSTC     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    TIM9RSTC      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    SPI5RSTC      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    SAI1RSTC      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTCR    SAI2RSTC      LL_APB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB2RSTCR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripherals clock during Low Power mode.
+  * @rmtoll APB2LPENSR   TIM1LPENS     LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   TIM8LPENS     LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   USART1LPENS   LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   USART6LPENS   LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   UART9LPENS    LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   USART10LPENS  LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   SPI1LPENS     LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   SPI4LPENS     LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   TIM18LPENS    LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   TIM15LPENS    LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   TIM16LPENS    LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   TIM17LPENS    LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   TIM9LPENS     LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   SPI5LPENS     LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   SAI1LPENS     LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENSR   SAI2LPENS     LL_APB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB2LPENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB2LPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    UART9LPEN     LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    USART10LPEN   LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    TIM18LPEN     LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    TIM9LPEN      LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_IsEnabledClockLowPower\n
+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB2LPENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock during Low Power mode.
+  * @rmtoll APB2LPENCR   TIM1LPENC     LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   TIM8LPENC     LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   USART1LPENC   LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   USART6LPENC   LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   UART9LPENC    LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   USART10LPENC  LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   SPI1LPENC     LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   SPI4LPENC     LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   TIM18LPENC    LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   TIM15LPENC    LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   TIM16LPENC    LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   TIM17LPENC    LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   TIM9LPENC     LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   SPI5LPENC     LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   SAI1LPENC     LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENCR   SAI2LPENC     LL_APB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM18
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB2LPENCR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable APB4 peripherals clock.
+  * @rmtoll APB4ENSR1    HDPENS        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    LPUART1ENS    LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    SPI6ENS       LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    I2C4ENS       LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    LPTIM2ENS     LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    LPTIM3ENS     LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    LPTIM4ENS     LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    LPTIM5ENS     LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    VREFBUFENS    LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    RTCENS        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENSR1    RTCAPBENS     LL_APB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTC
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB4ENSR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB4ENR1);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR1     HDPEN         LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     SPI6EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     I2C4EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     VREFBUFEN     LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     RTCEN         LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR1     RTCAPBEN      LL_APB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTC
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB4ENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock.
+  * @rmtoll APB4ENCR1    HDPENC        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    LPUART1ENC    LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    SPI6ENC       LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    I2C4ENC       LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    LPTIM2ENC     LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    LPTIM3ENC     LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    LPTIM4ENC     LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    LPTIM5ENC     LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    VREFBUFENC    LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    RTCENC        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENCR1    RTCAPBENC     LL_APB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTC
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4ENCR1, Periphs);
+}
+
+/**
+  * @brief  Force APB4 peripherals reset.
+  * @rmtoll APB4RSTSR1   HDPRSTS       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   LPUART1RSTS   LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   SPI6RSTS      LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   I2C4RSTS      LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   LPTIM2RSTS    LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   LPTIM3RSTS    LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   LPTIM4RSTS    LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   LPTIM5RSTS    LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   VREFBUFRSTS   LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTSR1   RTCAPBRSTS    LL_APB4_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4RSTSR1, Periphs);
+}
+
+/**
+  * @brief  Release APB4 peripherals reset.
+  * @rmtoll APB4RSTCR1   HDPRSTC       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   LPUART1RSTC   LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   SPI6RSTC      LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   I2C4RSTC      LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   LPTIM2RSTC    LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   LPTIM3RSTC    LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   LPTIM4RSTC    LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   LPTIM5RSTC    LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   VREFBUFRSTC   LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTCR1   RTCAPBRSTC    LL_APB4_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4RSTCR1, Periphs);
+}
+
+/**
+  * @brief  Enable APB4 peripherals clock during Low Power mode.
+  * @rmtoll APB4LPENSR1  HDPLPENS      LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  LPUART1LPENS  LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  SPI6LPENS     LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  I2C4LPENS     LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  LPTIM2LPENS   LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  LPTIM3LPENS   LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  LPTIM4LPENS   LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  LPTIM5LPENS   LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  VREFBUFLPENS  LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  RTCLPENS      LL_APB4_GRP1_EnableClockLowPower\n
+  *         APB4LPENSR1  RTCAPBLPENS   LL_APB4_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTC
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB4LPENSR1, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB4LPENR1);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB4 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll APB4LPENR1   HDPLPEN       LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   LPUART1LPEN   LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   SPI6LPEN      LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   I2C4LPEN      LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   LPTIM2LPEN    LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   LPTIM3LPEN    LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   LPTIM4LPEN    LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   LPTIM5LPEN    LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   VREFBUFLPEN   LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   RTCLPEN       LL_APB4_GRP1_IsEnabledClockLowPower\n
+  *         APB4LPENR1   RTCAPBLPEN    LL_APB4_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTC
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB4LPENR1, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock during Low Power mode.
+  * @rmtoll APB4LPENCR1  HDPLPENC      LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  LPUART1LPENC  LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  SPI6LPENC     LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  I2C4LPENC     LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  LPTIM2LPENC   LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  LPTIM3LPENC   LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  LPTIM4LPENC   LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  LPTIM5LPENC   LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  VREFBUFLPENC  LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  RTCLPENC      LL_APB4_GRP1_DisableClockLowPower\n
+  *         APB4LPENCR1  RTCAPBLPENC   LL_APB4_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_HDP
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTC
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREFBUF
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4LPENCR1, Periphs);
+}
+
+/**
+  * @brief  Enable APB4 peripherals clock.
+  * @rmtoll APB4ENSR2    SYSCFGENS     LL_APB4_GRP2_EnableClock\n
+  *         APB4ENSR2    BSECENS       LL_APB4_GRP2_EnableClock\n
+  *         APB4ENSR2    DTSENS        LL_APB4_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_BSEC
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB4ENSR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB4ENR2);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR2     SYSCFGEN      LL_APB4_GRP2_IsEnabledClock\n
+  *         APB4ENR2     BSECEN        LL_APB4_GRP2_IsEnabledClock\n
+  *         APB4ENR2     DTSEN         LL_APB4_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_BSEC
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB4ENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock.
+  * @rmtoll APB4ENCR2    SYSCFGENC     LL_APB4_GRP2_DisableClock\n
+  *         APB4ENCR2    BSECENC       LL_APB4_GRP2_DisableClock\n
+  *         APB4ENCR2    DTSENC        LL_APB4_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_BSEC
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP2_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4ENCR2, Periphs);
+}
+
+/**
+  * @brief  Force APB4 peripherals reset.
+  * @rmtoll APB4RSTR2   SYSCFGRSTS    LL_APB4_GRP2_ForceReset\n
+  *         APB4RSTR2   DTSRSTS       LL_APB4_GRP2_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP2_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4RSTSR2, Periphs);
+}
+
+/**
+  * @brief  Release APB4 peripherals reset.
+  * @rmtoll APB4RSTCR2   SYSCFGRSTC    LL_APB4_GRP2_ReleaseReset\n
+  *         APB4RSTCR2   DTSRSTC       LL_APB4_GRP2_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP2_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4RSTCR2, Periphs);
+}
+
+/**
+  * @brief  Enable APB4 peripherals clock during Low Power mode.
+  * @rmtoll APB4LPENSR2  SYSCFGLPENS   LL_APB4_GRP2_EnableClockLowPower\n
+  *         APB4LPENSR2  BSECLPENS     LL_APB4_GRP2_EnableClockLowPower\n
+  *         APB4LPENSR2  DTSLPENS      LL_APB4_GRP2_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_BSEC
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP2_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB4LPENSR2, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB4LPENR2);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB4 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll APB4LPENR2   SYSCFGLPEN    LL_APB4_GRP2_IsEnabledClockLowPower\n
+  *         APB4LPENR2   BSECLPEN      LL_APB4_GRP2_IsEnabledClockLowPower\n
+  *         APB4LPENR2   DTSLPEN       LL_APB4_GRP2_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_BSEC
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB4_GRP2_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB4LPENR2, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock during Low Power mode.
+  * @rmtoll APB4LPENCR2  SYSCFGLPENC   LL_APB4_GRP2_DisableClockLowPower\n
+  *         APB4LPENCR2  BSECLPENC     LL_APB4_GRP2_DisableClockLowPower\n
+  *         APB4LPENCR2  DTSLPENC      LL_APB4_GRP2_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP2_PERIPH_BSEC
+  *         @arg @ref LL_APB4_GRP2_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP2_PERIPH_DTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB4_GRP2_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB4LPENCR2, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB5 APB5
+  * @{
+  */
+
+/**
+  * @brief  Enable APB5 peripherals clock.
+  * @rmtoll APB5ENSR     LTDCENS       LL_APB5_GRP1_EnableClock\n
+  *         APB5ENSR     DCMIPPENS     LL_APB5_GRP1_EnableClock\n
+  *         APB5ENSR     GFXTIMENS     LL_APB5_GRP1_EnableClock\n
+  *         APB5ENSR     VENCENS       LL_APB5_GRP1_EnableClock\n (*)
+  *         APB5ENSR     CSIENS        LL_APB5_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB5ENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB5ENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB5 peripheral clock is enabled or not
+  * @rmtoll APB5ENR      LTDCEN        LL_APB5_GRP1_IsEnabledClock\n
+  *         APB5ENR      DCMIPPEN      LL_APB5_GRP1_IsEnabledClock\n
+  *         APB5ENR      GFXTIMEN      LL_APB5_GRP1_IsEnabledClock\n
+  *         APB5ENR      VENCEN        LL_APB5_GRP1_IsEnabledClock\n (*)
+  *         APB5ENR      CSIEN         LL_APB5_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB5ENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB5 peripherals clock.
+  * @rmtoll APB5ENCR     LTDCENC       LL_APB5_GRP1_DisableClock\n
+  *         APB5ENCR     DCMIPPENC     LL_APB5_GRP1_DisableClock\n
+  *         APB5ENCR     GFXTIMENC     LL_APB5_GRP1_DisableClock\n
+  *         APB5ENCR     VENCENC       LL_APB5_GRP1_DisableClock\n (*)
+  *         APB5ENCR     CSIENC        LL_APB5_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB5ENCR, Periphs);
+}
+
+/**
+  * @brief  Force APB5 peripherals reset.
+  * @rmtoll APB5RSTSR     LTDCRSTS       LL_APB5_GRP1_ForceReset\n
+  *         APB5RSTSR     DCMIPPRSTS     LL_APB5_GRP1_ForceReset\n
+  *         APB5RSTSR     GFXTIMRSTS     LL_APB5_GRP1_ForceReset\n
+  *         APB5RSTSR     VENCRSTS       LL_APB5_GRP1_ForceReset\n (*)
+  *         APB5RSTSR     CSIRSTS        LL_APB5_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB5RSTSR, Periphs);
+}
+
+/**
+  * @brief  Release APB5 peripherals reset.
+  * @rmtoll APB5RSTCR     LTDCRSTC       LL_APB5_GRP1_ReleaseReset\n
+  *         APB5RSTCR     DCMIPPRSTC     LL_APB5_GRP1_ReleaseReset\n
+  *         APB5RSTCR     GFXTIMRSTC     LL_APB5_GRP1_ReleaseReset\n
+  *         APB5RSTCR     VENCRSTC       LL_APB5_GRP1_ReleaseReset\n (*)
+  *         APB5RSTCR     CSIRSTC        LL_APB5_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB5RSTCR, Periphs);
+}
+
+/**
+  * @brief  Enable APB5 peripherals clock during Low Power mode.
+  * @rmtoll APB5LPENSR    LTDCLPENS      LL_APB5_GRP1_EnableClockLowPower\n
+  *         APB5LPENSR    DCMIPPLPENS    LL_APB5_GRP1_EnableClockLowPower\n
+  *         APB5LPENSR    GFXTIMLPENS    LL_APB5_GRP1_EnableClockLowPower\n
+  *         APB5LPENSR    VENCLPENS      LL_APB5_GRP1_EnableClockLowPower\n (*)
+  *         APB5LPENSR    CSILPENS       LL_APB5_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB5_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->APB5LPENSR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_REG(RCC->APB5LPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB5 peripheral clock during Low Power mode is enabled or not .
+  * @rmtoll APB5LPENR     LTDCLPEN       LL_APB5_GRP1_IsEnabledClockLowPower\n
+  *         APB5LPENR     DCMIPPLPEN     LL_APB5_GRP1_IsEnabledClockLowPower\n
+  *         APB5LPENR     GFXTIMLPEN     LL_APB5_GRP1_IsEnabledClockLowPower\n
+  *         APB5LPENR     VENCLPEN       LL_APB5_GRP1_IsEnabledClockLowPower\n (*)
+  *         APB5LPENR     CSILPEN        LL_APB5_GRP1_IsEnabledClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClockLowPower(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB5LPENR, Periphs) == Periphs) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable APB5 peripherals clock during Low Power mode.
+  * @rmtoll APB5LPENCR    LTDCLPENC      LL_APB5_GRP1_DisableClockLowPower\n
+  *         APB5LPENCR    DCMIPPLPENC    LL_APB5_GRP1_DisableClockLowPower\n
+  *         APB5LPENCR    GFXTIMLPENC    LL_APB5_GRP1_DisableClockLowPower\n
+  *         APB5LPENCR    VENCLPENC      LL_APB5_GRP1_DisableClockLowPower\n (*)
+  *         APB5LPENCR    CSILPENC       LL_APB5_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB5_GRP1_PERIPH_CSI
+  *         @arg @ref LL_APB5_GRP1_PERIPH_DCMIPP
+  *         @arg @ref LL_APB5_GRP1_PERIPH_GFXTIM
+  *         @arg @ref LL_APB5_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB5_GRP1_PERIPH_VENC
+  * @retval None
+  */
+__STATIC_INLINE void LL_APB5_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  WRITE_REG(RCC->APB5LPENCR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_MISC MISC
+  * @{
+  */
+
+/**
+  * @brief  Enable miscellaneous clock.
+  * @rmtoll MISCENSR     DBGENS        LL_MISC_EnableClock\n
+  *         MISCENSR     MCO1ENS       LL_MISC_EnableClock\n
+  *         MISCENSR     MCO2ENS       LL_MISC_EnableClock\n
+  *         MISCENSR     XSPIPHYCOMPENS LL_MISC_EnableClock\n
+  *         MISCENSR     PERENS        LL_MISC_EnableClock
+  * @param  Misc This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBG
+  *         @arg @ref LL_MCO1
+  *         @arg @ref LL_MCO2
+  *         @arg @ref LL_XSPIPHYCOMP
+  *         @arg @ref LL_PER
+  * @retval None
+  */
+__STATIC_INLINE void LL_MISC_EnableClock(uint32_t Misc)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->MISCENSR, Misc);
+  /* Delay after an RCC miscellaneous clock enabling */
+  tmpreg = READ_REG(RCC->MISCENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if miscellaneous clock is enabled or not
+  * @rmtoll MISCENR      DBGEN         LL_MISC_IsEnabledClock\n
+  *         MISCENR      MCO1EN        LL_MISC_IsEnabledClock\n
+  *         MISCENR      MCO2EN        LL_MISC_IsEnabledClock\n
+  *         MISCENR      XSPIPHYCOMPEN LL_MISC_IsEnabledClock\n
+  *         MISCENR      PEREN         LL_MISC_IsEnabledClock
+  * @param  Misc This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBG
+  *         @arg @ref LL_MCO1
+  *         @arg @ref LL_MCO2
+  *         @arg @ref LL_XSPIPHYCOMP
+  *         @arg @ref LL_PER
+  * @retval uint32_t
+  */
+__STATIC_INLINE uint32_t LL_MISC_IsEnabledClock(uint32_t Misc)
+{
+  return ((READ_BIT(RCC->MISCENR, Misc) == Misc) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Disable miscellaneous clock.
+  * @rmtoll MISCENCR     DBGENC        LL_MISC_DisableClock\n
+  *         MISCENCR     MCO1ENC       LL_MISC_DisableClock\n
+  *         MISCENCR     MCO2ENC       LL_MISC_DisableClock\n
+  *         MISCENCR     XSPIPHYCOMPENC LL_MISC_DisableClock\n
+  *         MISCENCR     PERENC        LL_MISC_DisableClock
+  * @param  Misc This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBG
+  *         @arg @ref LL_MCO1
+  *         @arg @ref LL_MCO2
+  *         @arg @ref LL_XSPIPHYCOMP
+  *         @arg @ref LL_PER
+  * @retval None
+  */
+__STATIC_INLINE void LL_MISC_DisableClock(uint32_t Misc)
+{
+  WRITE_REG(RCC->MISCENCR, Misc);
+}
+
+/**
+  * @brief  Force miscellaneous reset.
+  * @rmtoll MISCRSTSR    DBGRSTS       LL_MISC_ForceReset\n
+  *         MISCRSTSR    XSPIPHY1RSTS  LL_MISC_ForceReset\n
+  *         MISCRSTSR    XSPIPHY2RSTS  LL_MISC_ForceReset\n
+  *         MISCRSTSR    SDMMC1DLLRSTS LL_MISC_ForceReset\n
+  *         MISCRSTSR    SDMMC2DLLRSTS LL_MISC_ForceReset
+  * @param  Misc This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBG
+  *         @arg @ref LL_XSPIPHY1
+  *         @arg @ref LL_XSPIPHY2
+  *         @arg @ref LL_SDMMC1DLL
+  *         @arg @ref LL_SDMMC2DLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_MISC_ForceReset(uint32_t Misc)
+{
+  WRITE_REG(RCC->MISCRSTSR, Misc);
+}
+
+/**
+  * @brief  Release miscellaneous reset.
+  * @rmtoll MISCRSTCR    DBGRSTC       LL_MISC_ReleaseReset\n
+  *         MISCRSTCR    XSPIPHY1RSTC  LL_MISC_ReleaseReset\n
+  *         MISCRSTCR    XSPIPHY2RSTC  LL_MISC_ReleaseReset\n
+  *         MISCRSTCR    SDMMC1DLLRSTC LL_MISC_ReleaseReset\n
+  *         MISCRSTCR    SDMMC2DLLRSTC LL_MISC_ReleaseReset
+  * @param  Misc This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBG
+  *         @arg @ref LL_XSPIPHY1
+  *         @arg @ref LL_XSPIPHY2
+  *         @arg @ref LL_SDMMC1DLL
+  *         @arg @ref LL_SDMMC2DLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_MISC_ReleaseReset(uint32_t Misc)
+{
+  WRITE_REG(RCC->MISCRSTCR, Misc);
+}
+
+/**
+  * @brief  Enable bus clock during Low Power mode.
+  * @rmtoll MISCLPENSR   DBGLPENS      LL_MISC_EnableClockLowPower\n
+  *         MISCLPENSR   XSPIPHYCOMPLPENS LL_MISC_EnableClockLowPower\n
+  *         MISCLPENSR   PERLPENS      LL_MISC_EnableClockLowPower
+  * @param  Misc This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBG
+  *         @arg @ref LL_XSPIPHYCOMP
+  *         @arg @ref LL_PER
+  * @retval None
+  */
+__STATIC_INLINE void LL_MISC_EnableClockLowPower(uint32_t Misc)
+{
+  __IO uint32_t tmpreg;
+  WRITE_REG(RCC->MISCLPENSR, Misc);
+  /* Delay after an RCC miscellaneous clock enabling */
+  tmpreg = READ_REG(RCC->MISCLPENR);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable bus clock during Low Power mode.
+  * @rmtoll MISCLPENCR   DBGLPENC      LL_MISC_DisableClockLowPower\n
+  *         MISCLPENCR   XSPIPHYCOMPLPENC LL_MISC_DisableClockLowPower\n
+  *         MISCLPENCR   PERLPENC      LL_MISC_DisableClockLowPower
+  * @param  Misc This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBG
+  *         @arg @ref LL_XSPIPHYCOMP
+  *         @arg @ref LL_PER
+  * @retval None
+  */
+__STATIC_INLINE void LL_MISC_DisableClockLowPower(uint32_t Misc)
+{
+  WRITE_REG(RCC->MISCLPENCR, Misc);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_BUS_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_cacheaxi.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_cacheaxi.h
new file mode 100644
index 000000000..11501594a
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_cacheaxi.h
@@ -0,0 +1,691 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_cacheaxi.h
+  * @author  MCD Application Team
+  * @brief   Header file of CACHEAXI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32N6xx_LL_CACHEAXI_H
+#define STM32N6xx_LL_CACHEAXI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CACHEAXI_LL CACHEAXI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CACHEAXI_Exported_Constants CACHEAXI Exported Constants
+  * @{
+  */
+/** @defgroup CACHEAXI_Command_Operation Command Operation
+  * @{
+  */
+#define LL_CACHEAXI_COMMAND_NO_OPERATION                    (0x00000000)
+#define LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR                   CACHEAXI_CR2_CACHECMD_0
+#define LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR        (CACHEAXI_CR2_CACHECMD_0|CACHEAXI_CR2_CACHECMD_1)
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CACHEAXI_ReadReg function
+  * @{
+  */
+#define LL_CACHEAXI_SR_ERRF              CACHEAXI_SR_ERRF      /*!< Cache error flag */
+#define LL_CACHEAXI_SR_BUSYF             CACHEAXI_SR_BUSYF     /*!< Busy flag */
+#define LL_CACHEAXI_SR_CMDENDF           CACHEAXI_SR_CMDENDF   /*!< Command end flag */
+#define LL_CACHEAXI_SR_BSYENDF           CACHEAXI_SR_BSYENDF   /*!< Full invalidate busy end flag */
+#define LL_CACHEAXI_SR_BUSYCMDF          CACHEAXI_SR_BUSYCMDF  /*!< Command busy flag */
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_CACHEAXI_WriteReg function
+  * @{
+  */
+#define LL_CACHEAXI_FCR_CERRF            CACHEAXI_FCR_CERRF    /*!< Cache error flag */
+#define LL_CACHEAXI_FCR_CBSYENDF         CACHEAXI_FCR_CBSYENDF /*!< Full invalidate busy end flag */
+#define LL_CACHEAXI_FCR_CCMDENDF         CACHEAXI_FCR_CCMDENDF /*!< Command end flag*/
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CACHEAXI_ReadReg and  LL_CACHEAXI_WriteReg functions
+  * @{
+  */
+#define LL_CACHEAXI_IER_BSYENDIE         CACHEAXI_IER_BSYENDIE /*!< Busy end interrupt */
+#define LL_CACHEAXI_IER_ERRIE            CACHEAXI_IER_ERRIE    /*!< Cache error interrupt */
+#define LL_CACHEAXI_IER_CMDENDIE         CACHEAXI_IER_CMDENDIE /*!< Command end interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_Monitor_Type Monitor type
+  * @{
+  */
+#define LL_CACHEAXI_MONITOR_READ_HIT         CACHEAXI_CR1_RHITMEN   /*!< Read Hit monitoring */
+#define LL_CACHEAXI_MONITOR_READ_MISS        CACHEAXI_CR1_RMISSMEN  /*!< Read Miss monitoring */
+#define LL_CACHEAXI_MONITOR_WRITE_HIT        CACHEAXI_CR1_WHITMEN   /*!< Write Hit monitoring */
+#define LL_CACHEAXI_MONITOR_WRITE_MISS       CACHEAXI_CR1_WMISSMEN  /*!< Write Miss monitoring */
+#define LL_CACHEAXI_MONITOR_READALLOC_MISS   CACHEAXI_CR1_RAMMEN /*!< Read-alloc Miss monitoring */
+#define LL_CACHEAXI_MONITOR_WRITEALLOC_MISS  CACHEAXI_CR1_WAMMEN /*!< Write-alloc Miss monitoring */
+#define LL_CACHEAXI_MONITOR_WRITETHROUGH     CACHEAXI_CR1_WTMEN     /*!< Write-through monitoring */
+#define LL_CACHEAXI_MONITOR_EVICTION         CACHEAXI_CR1_EVIMEN    /*!< Eviction monitoring */
+#define LL_CACHEAXI_MONITOR_ALL             (CACHEAXI_CR1_RHITMEN | CACHEAXI_CR1_RMISSMEN   \
+                                             | CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_WMISSMEN \
+                                             | CACHEAXI_CR1_RAMMEN  | CACHEAXI_CR1_WAMMEN   \
+                                             | CACHEAXI_CR1_WTMEN   | CACHEAXI_CR1_EVIMEN)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros --------------------------------------------------------*/
+/** @defgroup CACHEAXI_LL_Exported_Macros CACHEAXI Exported Macros
+  * @{
+  */
+
+/** @defgroup CACHEAXI_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CACHEAXI register
+  * @param  __INSTANCE__ CACHEAXI Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CACHEAXI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CACHEAXI register
+  * @param  __INSTANCE__ CACHEAXI Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CACHEAXI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CACHEAXI_LL_Exported_Functions CACHEAXI Exported Functions
+  * @{
+  */
+
+/** @defgroup CACHEAXI_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the selected CACHEAXI instance.
+  * @rmtoll CR1       EN           LL_CACHEAXI_Enable
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_Enable(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);
+}
+
+/**
+  * @brief  Disable the selected CACHEAXI instance.
+  * @rmtoll CR1       EN           LL_CACHEAXI_Disable
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_Disable(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  CLEAR_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);
+}
+
+/**
+  * @brief  Get the selected CACHEAXI instance enable state.
+  * @rmtoll CR1       EN           LL_CACHEAXI_IsEnabled
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval 0: CACHEAXI is disabled, 1: CACHEAXI is enabled.
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabled(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN) == (CACHEAXI_CR1_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the cacheaxi instance start command address.
+  * @rmtoll CR2       CMDRSADDRR          LL_CACHEAXI_SetStartAddress
+  * @param  addr cacheaxi command start address(Clean, Invalidate or Clean and Invalidate).
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_SetStartAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)
+{
+  WRITE_REG(CACHEAXIx->CMDRSADDRR, addr);
+}
+
+/**
+  * @brief  Get the cacheaxi command start address.
+  * @rmtoll CR2       CMDRSADDRR         LL_CACHEAXI_GetStartAddress
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Start address of cacheaxi command
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_GetStartAddress(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return (uint32_t)(READ_REG(CACHEAXIx->CMDRSADDRR));
+}
+
+/**
+  * @brief  Set the cacheaxi instance End command address.
+  * @rmtoll CR2       CMDREADDRR          LL_CACHEAXI_SetEndAddress
+  * @param  CACHEAXIx CACHEAXI instance
+  * @param  addr cacheaxi command end address(Clean, Invalidate or Clean and Invalidate).
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_SetEndAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)
+{
+  WRITE_REG(CACHEAXIx->CMDREADDRR, addr);
+}
+
+/**
+  * @brief  Get the cacheaxi command End address.
+  * @rmtoll CR2       CMDREADDRR          LL_CACHEAXI_GetEndAddress
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval End address of cacheaxi command
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_GetEndAddress(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return (uint32_t)(READ_REG(CACHEAXIx->CMDREADDRR));
+}
+
+/**
+  * @brief  Set Dcache command.
+  * @rmtoll CR2       CACHECMD          LL_CACHEAXI_SetCommand
+  * @param  CACHEAXIx CACHEAXI instance
+  * @param  Command command to be applied for the cacheaxi
+  *         Command can be one of the following values:
+  *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR
+  *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR
+  *         @arg @ref LL_CACHEAXI_COMMAND_NO_OPERATION
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_SetCommand(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Command)
+{
+  /* Set cacheaxi command */
+  MODIFY_REG(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD, Command);
+}
+
+/**
+  * @brief  Set Dcache command.
+  * @rmtoll CR2       CACHECMD          LL_CACHEAXI_GetCommand
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CACHEAXI_COMMAND_NO_OPERATION
+  *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR
+  *         @arg @ref LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_GetCommand(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  /*Get Dcache Command */
+  return (uint32_t)(READ_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD));
+}
+
+/**
+  * @brief  Launch Dcache Command.
+  * @rmtoll CR2       CACHECMD          LL_CACHEAXI_StartCommand
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_StartCommand(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  SET_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_STARTCMD);
+}
+
+/**
+  * @brief  Invalidate the Data cache.
+  * @rmtoll CR1       CACHEINV          LL_CACHEAXI_Invalidate
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_Invalidate(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_CACHEINV);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup CACHEAXI_LL_EF_Monitor Monitor
+  * @{
+  */
+
+/**
+  * @brief  Enable the hit/miss monitor(s).
+  * @rmtoll CR1  (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN)   LL_CACHEAXI_EnableMonitors
+  * @param  CACHEAXIx CACHEAXI instance
+  * @param  Monitors This parameter can be one or a combination of the following values:
+  *            @arg LL_CACHEAXI_MONITOR_READ_HIT
+  *            @arg LL_CACHEAXI_MONITOR_READ_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
+  *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
+  *            @arg LL_CACHEAXI_MONITOR_EVICTION
+  *            @arg LL_CACHEAXI_MONITOR_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_EnableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
+{
+  SET_BIT(CACHEAXIx->CR1, Monitors);
+}
+
+/**
+  * @brief  Disable the hit/miss monitor(s).
+  * @rmtoll CR1  (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN)   LL_CACHEAXI_DisableMonitors
+  * @param  CACHEAXIx CACHEAXI instance
+  * @param  Monitors This parameter can be one or a combination of the following values:
+  *            @arg LL_CACHEAXI_MONITOR_READ_HIT
+  *            @arg LL_CACHEAXI_MONITOR_READ_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
+  *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
+  *            @arg LL_CACHEAXI_MONITOR_EVICTION
+  *            @arg LL_CACHEAXI_MONITOR_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_DisableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
+{
+  CLEAR_BIT(CACHEAXIx->CR1, Monitors);
+}
+
+/**
+  * @brief  Return the hit/miss monitor(s) enable state.
+  * @rmtoll CR1  (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN)   LL_CACHEAXI_IsEnabledMonitors
+  * @param  CACHEAXIx CACHEAXI instance
+  * @param  Monitors This parameter can be one or a combination of the following values:
+  *            @arg LL_CACHEAXI_MONITOR_READ_HIT
+  *            @arg LL_CACHEAXI_MONITOR_READ_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
+  *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
+  *            @arg LL_CACHEAXI_MONITOR_EVICTION
+  *            @arg LL_CACHEAXI_MONITOR_ALL
+  * @retval State of parameter value (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledMonitors(const CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
+{
+  return (((READ_BIT(CACHEAXIx->CR1, (CACHEAXI_CR1_WMISSMEN | CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_RMISSMEN | \
+                                      CACHEAXI_CR1_RHITMEN  | CACHEAXI_CR1_RAMMEN  | CACHEAXI_CR1_WAMMEN   | \
+                                      CACHEAXI_CR1_WTMEN    | CACHEAXI_CR1_EVIMEN))\
+            & Monitors) == (Monitors)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Reset the Data Cache performance monitoring.
+  * @rmtoll CR1  (RHITMRST/RMISSMRST/WHITMRST/WMISSMRST/RAMMRST/WAMMRST/WTMRST/EVIMRST)   LL_CACHEAXI_ResetMonitors
+  * @param  CACHEAXIx CACHEAXI instance
+  * @param  Monitors Monitoring type
+  *         This parameter can be a combination of the following values:
+  *            @arg LL_CACHEAXI_MONITOR_READ_HIT
+  *            @arg LL_CACHEAXI_MONITOR_READ_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_HIT
+  *            @arg LL_CACHEAXI_MONITOR_WRITE_MISS
+  *            @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
+  *            @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
+  *            @arg LL_CACHEAXI_MONITOR_EVICTION
+  *            @arg LL_CACHEAXI_MONITOR_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_ResetMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
+{
+  /* Reset */
+  SET_BIT(CACHEAXIx->CR1, (Monitors << 2U));
+
+  /* Release reset */
+  CLEAR_BIT(CACHEAXIx->CR1, (Monitors << 2U));
+}
+
+/**
+  * @brief  Get the Read Hit monitor Value
+  * @rmtoll RHMONR       LL_CACHEAXI_Monitor_GetReadHitValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadHitValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->RHMONR;
+}
+
+/**
+  * @brief  Get the Read Miss monitor Value
+  * @rmtoll RMMONR       LL_CACHEAXI_Monitor_GetReadMissValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadMissValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->RMMONR;
+}
+
+/**
+  * @brief  Get the Write Hit monitor Value
+  * @rmtoll WHMONR       LL_CACHEAXI_Monitor_GetWriteHitValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteHitValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->WHMONR;
+}
+
+/**
+  * @brief  Get the Write Miss monitor Value
+  * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetWriteMissValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteMissValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->WMMONR;
+}
+
+/**
+  * @brief  Get the Read-allocate Miss monitor Value
+  * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetReadAllocMissValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->RAMMONR;
+}
+
+/**
+  * @brief  Get the Write-allocate Miss monitor Value
+  * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetWriteAllocMissValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->WAMMONR;
+}
+
+/**
+  * @brief  Get the Write-through monitor Value
+  * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetWriteThroughValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteThroughValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->WTMONR;
+}
+
+/**
+  * @brief  Get the Eviction monitor Value
+  * @rmtoll WMMONR       LL_CACHEAXI_Monitor_GetEvictionValue
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetEvictionValue(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return CACHEAXIx->EVIMONR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CACHEAXI_LL_EF_IT_Management IT-Management
+  * @{
+  */
+
+/**
+  * @brief  Enable BusyEnd interrupt.
+  * @rmtoll IER         BSYENDIE          LL_CACHEAXI_EnableIT_BSYEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_EnableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);
+}
+
+/**
+  * @brief  Disable BusyEnd interrupt.
+  * @rmtoll IER         BSYENDIE          LL_CACHEAXI_DisableIT_BSYEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_DisableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);
+}
+
+/**
+  * @brief  Indicates whether the Busyend interrupt is enabled.
+  * @rmtoll IER         BSYENDIE          LL_CACHEAXI_IsEnabledIT_BSYEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE) == (CACHEAXI_IER_BSYENDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Error interrupt.
+  * @rmtoll IER         ERRIE          LL_CACHEAXI_EnableIT_ERR
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_EnableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);
+}
+
+/**
+  * @brief  Disable Error interrupt.
+  * @rmtoll IER         ERRIE          LL_CACHEAXI_DisableIT_ERR
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_DisableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);
+}
+
+/**
+  * @brief  Indicates whether the Error interrupt is enabled.
+  * @rmtoll IER         ERRIE          LL_CACHEAXI_IsEnabledIT_ERR
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_ERR(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE) == (CACHEAXI_IER_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable command end interrupt.
+  * @rmtoll IER         CMDENDIE         LL_CACHEAXI_EnableIT_CMDEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_EnableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);
+}
+
+/**
+  * @brief  Disable command end interrupt.
+  * @rmtoll IER         CMDENDIE         LL_CACHEAXI_DisableIT_CMDEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_DisableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);
+}
+
+/**
+  * @brief  Indicates whether the command end interrupt is enabled.
+  * @rmtoll IER         CMDENDIE          LL_CACHEAXI_IsEnabledIT_CMDEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE) == (CACHEAXI_IER_CMDENDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear full invalidate busy end flag.
+  * @rmtoll FCR      CBSYENDF         LL_CACHEAXI_ClearFlag_BSYEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_ClearFlag_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CBSYENDF);
+}
+
+/**
+  * @brief  Clear cache error flag.
+  * @rmtoll FCR      CERRF        LL_CACHEAXI_ClearFlag_ERR
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_ClearFlag_ERR(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CERRF);
+}
+
+/**
+  * @brief  Clear command end flag.
+  * @rmtoll FCR      CCMDENDF        LL_CACHEAXI_ClearFlag_CMDEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CACHEAXI_ClearFlag_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
+{
+  WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CCMDENDF);
+}
+
+/**
+  * @brief  Get flag Dcache BUSY.
+  * @rmtoll SR      BUSYF            LL_CACHEAXI_IsActiveFlag_BUSY
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSY(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYF) == (CACHEAXI_SR_BUSYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag Dcache Busyend.
+  * @rmtoll SR      BSYENDF            LL_CACHEAXI_IsActiveFlag_BSYEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BSYENDF) == (CACHEAXI_SR_BSYENDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag Dcache Error.
+  * @rmtoll SR      ERRF            LL_CACHEAXI_IsActiveFlag_ERR
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_ERR(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_ERRF) == (CACHEAXI_SR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag Dcache Busy command.
+  * @rmtoll SR      BUSYCMDF            LL_CACHEAXI_IsActiveFlag_BUSYCMD
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSYCMD(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYCMDF) == (CACHEAXI_SR_BUSYCMDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag Dcache command end.
+  * @rmtoll SR      CMDENDF            LL_CACHEAXI_IsActiveFlag_CMDEND
+  * @param  CACHEAXIx CACHEAXI instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)
+{
+  return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_CMDENDF) == (CACHEAXI_SR_CMDENDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_CACHEAXI_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_cortex.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_cortex.h
new file mode 100644
index 000000000..c0ec0a6e9
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_cortex.h
@@ -0,0 +1,1482 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+      (+) API to enable and disable the MPU secure and non-secure
+      (+) API to configure the region of MPU secure and non-secure
+      (+) API to configure the attributes region of MPU secure and non-secure
+
+  @endverbatim
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_CORTEX_H
+#define STM32N6xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
+  * @{
+  */
+/* Register MPU_RBAR (Cortex-M55) : bits [4:0] */
+#define MPU_ACCESS_MSK                     (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK CORTEX LL SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0U                          /*!< AHB clock divided by 8 selected as SysTick
+                                                                            clock source */
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick
+                                                                            clock source */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT CORTEX LL Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+#define LL_HANDLER_FAULT_SECURE            SCB_SHCSR_SECUREFAULTENA_Msk           /*!< Secure fault */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0U                                                /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
+  * @{
+  */
+#define  LL_MPU_DEVICE_NGNRNE          0x0U  /* Device, noGather, noReorder, noEarly acknowledge. */
+#define  LL_MPU_DEVICE_NGNRE           0x4U  /* Device, noGather, noReorder, Early acknowledge.   */
+#define  LL_MPU_DEVICE_NGRE            0x8U  /* Device, noGather, Reorder, Early acknowledge.     */
+#define  LL_MPU_DEVICE_GRE             0xCU  /* Device, Gather, Reorder, Early acknowledge.       */
+
+#define  LL_MPU_WRITE_THROUGH          0x0U  /* Normal memory, write-through. */
+#define  LL_MPU_NOT_CACHEABLE          0x4U  /* Normal memory, non-cacheable. */
+#define  LL_MPU_WRITE_BACK             0x4U  /* Normal memory, write-back.    */
+
+#define  LL_MPU_TRANSIENT              0x0U  /* Normal memory, transient.     */
+#define  LL_MPU_NON_TRANSIENT          0x8U  /* Normal memory, non-transient. */
+
+#define  LL_MPU_NO_ALLOCATE            0x0U  /* Normal memory, no allocate.         */
+#define  LL_MPU_W_ALLOCATE             0x1U  /* Normal memory, write allocate.      */
+#define  LL_MPU_R_ALLOCATE             0x2U  /* Normal memory, read allocate.       */
+#define  LL_MPU_RW_ALLOCATE            0x3U  /* Normal memory, read/write allocate. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
+  * @{
+  */
+#define LL_MPU_REGION_ENABLE               1U
+#define LL_MPU_REGION_DISABLE              0U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   (0U << MPU_RBAR_XN_Pos)
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  (1U << MPU_RBAR_XN_Pos)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
+  * @{
+  */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        (0U << MPU_RBAR_SH_Pos)
+#define LL_MPU_ACCESS_OUTER_SHAREABLE      (2U << MPU_RBAR_SH_Pos)
+#define LL_MPU_ACCESS_INNER_SHAREABLE      (3U << MPU_RBAR_SH_Pos)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
+  * @{
+  */
+#define LL_MPU_REGION_PRIV_RW              (0U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_ALL_RW               (1U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_PRIV_RO              (2U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_ALL_RO               (3U << MPU_RBAR_AP_Pos)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0U
+#define LL_MPU_REGION_NUMBER1              1U
+#define LL_MPU_REGION_NUMBER2              2U
+#define LL_MPU_REGION_NUMBER3              3U
+#define LL_MPU_REGION_NUMBER4              4U
+#define LL_MPU_REGION_NUMBER5              5U
+#define LL_MPU_REGION_NUMBER6              6U
+#define LL_MPU_REGION_NUMBER7              7U
+#define LL_MPU_REGION_NUMBER8              8U
+#define LL_MPU_REGION_NUMBER9              9U
+#define LL_MPU_REGION_NUMBER10             10U
+#define LL_MPU_REGION_NUMBER11             11U
+#define LL_MPU_REGION_NUMBER12             12U
+#define LL_MPU_REGION_NUMBER13             13U
+#define LL_MPU_REGION_NUMBER14             14U
+#define LL_MPU_REGION_NUMBER15             15U
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
+  * @{
+  */
+#define LL_MPU_ATTRIBUTES_NUMBER0          0U
+#define LL_MPU_ATTRIBUTES_NUMBER1          1U
+#define LL_MPU_ATTRIBUTES_NUMBER2          2U
+#define LL_MPU_ATTRIBUTES_NUMBER3          3U
+#define LL_MPU_ATTRIBUTES_NUMBER4          4U
+#define LL_MPU_ATTRIBUTES_NUMBER5          5U
+#define LL_MPU_ATTRIBUTES_NUMBER6          6U
+#define LL_MPU_ATTRIBUTES_NUMBER7          7U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK CORTEX LL SYSTICK
+  * @brief CORTEX SYSTICK LL module driver
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    USGFAULTENA     LL_HANDLER_EnableFault\n
+  *         SCB_SHCSR    BUSFAULTENA     LL_HANDLER_EnableFault\n
+  *         SCB_SHCSR    MEMFAULTENA     LL_HANDLER_EnableFault\n
+  *         SCB_SHCSR    SECUREFAULTENA  LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  *         @arg @ref LL_HANDLER_FAULT_SECURE (*)
+  *
+  *         (*) value applicable in secure when the system implements the security.
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    USGFAULTENA     LL_HANDLER_DisableFault\n
+  *         SCB_SHCSR    BUSFAULTENA     LL_HANDLER_DisableFault\n
+  *         SCB_SHCSR    MEMFAULTENA     LL_HANDLER_DisableFault\n
+  *         SCB_SHCSR    SECUREFAULTENA  LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  *         @arg @ref LL_HANDLER_FAULT_SECURE (*)
+  *
+  *         (*) value applicable in secure when the system implements the security.
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Architecture version
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetArchitecture
+  * @retval Value should be equal to 0xF for Cortex-M55 ("ARMv8-M with Main Extension")
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xD22 for Cortex-M55
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  MPU_Control This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB(); /* Force any outstanding transfers to complete before enabling MPU */
+
+  /* Enable the MPU */
+  MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
+
+  /* Ensure MPU settings take effects */
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Enable non-secure MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  MPU_Control This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB(); /* Force any outstanding transfers to complete before enabling MPU */
+  /* Enable the MPU */
+  MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
+
+  /* Ensure MPU settings take effects */
+  __DSB();
+  __ISB();
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+  /* Disable MPU_NS */
+  WRITE_REG(MPU->CTRL, 0U);
+
+  /* Ensure MPU settings take effects */
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Disable the non-secure MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable_NS
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable_NS(void)
+{
+  __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+  /* Disable MPU_NS */
+  WRITE_REG(MPU_NS->CTRL, 0U);
+
+  /* Ensure MPU settings take effects */
+  __DSB();
+  __ISB();
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Check if non-secure MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled_NS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
+{
+  return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RLAR     EN        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Enable the MPU region */
+  SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+  * @brief  Check if MPU region is enabled or not
+  * @rmtoll MPU_RNR     EN         LL_MPU_IsEnabledRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region)
+{
+  /* Set region index */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Return MPU region status */
+  return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Enable a non-secure MPU region
+  * @rmtoll MPU_RLAR     EN        LL_MPU_EnableRegion_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Enable the MPU region */
+  SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+  * @brief  Check if non-secure MPU region is enabled or not
+  * @rmtoll MPU_RNR     EN        LL_MPU_IsEnabledRegion_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region)
+{
+  /* Set region index */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Return non-secure MPU region status */
+  return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Disable a MPU region
+  * @rmtoll MPU_RNR      REGION    LL_MPU_DisableRegion\n
+  *         MPU_RLAR     EN        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Disable a non-secure MPU region
+  * @rmtoll MPU_RNR      REGION    LL_MPU_DisableRegion_NS\n
+  *         MPU_RLAR     EN        LL_MPU_DisableRegion_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Configure and enable a MPU region
+  * @rmtoll MPU_RNR      REGION    LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     BASE      LL_MPU_ConfigRegion\n
+  *         MPU_RLAR     LIMIT     LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     XN        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     AP        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     SH        LL_MPU_ConfigRegion\n
+  *         MPU_RLAR     EN        LL_MPU_ConfigRegion\n
+  *         MPU_RLAR     AttrX     LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+  *              or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+  *         @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+  *              or @ref LL_MPU_REGION_ALL_RO
+  * @param  AttrIndx This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+  * @param  BaseAddress Value of region base address
+  * @param  LimitAddress Value of region limit address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
+                                         uint32_t LimitAddress)
+{
+  /* Set region index */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Set region base address and region access attributes */
+  WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
+
+  /* Set region limit address, memory attributes index and enable region */
+  WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Configure and enable a non-secure MPU region
+  * @rmtoll MPU_RNR      REGION    LL_MPU_ConfigRegion_NS\n
+  *         MPU_RBAR     BASE      LL_MPU_ConfigRegion_NS\n
+  *         MPU_RLAR     LIMIT     LL_MPU_ConfigRegion_NS\n
+  *         MPU_RBAR     XN        LL_MPU_ConfigRegion_NS\n
+  *         MPU_RBAR     AP        LL_MPU_ConfigRegion_NS\n
+  *         MPU_RBAR     SH        LL_MPU_ConfigRegion_NS\n
+  *         MPU_RLAR     EN        LL_MPU_ConfigRegion_NS\n
+  *         MPU_RLAR     AttrX     LL_MPU_ConfigRegion_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+  *              or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+  *         @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+  *              or @ref LL_MPU_REGION_ALL_RO
+  * @param  AttrIndx This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+  * @param  BaseAddress Value of region base address
+  * @param  LimitAddress Value of region limit address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
+                                            uint32_t BaseAddress, uint32_t LimitAddress)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Set region base address and region access attributes */
+  WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
+
+  /* Set region limit address, memory attributes index and enable region */
+  WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Configure a MPU region address range
+  * @rmtoll MPU_RNR      REGION    LL_MPU_ConfigRegionAddress\n
+  *         MPU_RBAR     BASE      LL_MPU_ConfigRegionAddress\n
+  *         MPU_RLAR     LIMIT     LL_MPU_ConfigRegionAddress
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  BaseAddress Value of region base address
+  * @param  LimitAddress Value of region limit address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Modify region base address */
+  MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
+
+  /* Modify region limit address */
+  MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Configure a non-secure MPU region address range
+  * @rmtoll MPU_RNR      REGION    LL_MPU_ConfigRegionAddress_NS\n
+  *         MPU_RBAR     BASE      LL_MPU_ConfigRegionAddress_NS\n
+  *         MPU_RLAR     LIMIT     LL_MPU_ConfigRegionAddress_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  BaseAddress Value of region base address
+  * @param  LimitAddress Value of region limit address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Set base address */
+  MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
+
+  /* Set limit address */
+  MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Configure a MPU attributes index
+  * @rmtoll MPU_MAIR0    AttrX     LL_MPU_ConfigAttributes\n
+  *         MPU_MAIR1    AttrX     LL_MPU_ConfigAttributes
+  * @param  AttIndex This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+  * @param  Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t  Attributes)
+{
+  /* When selected index is in range [0;3] */
+  if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
+  {
+    /* Modify Attr<i> field of MPU_MAIR0 accordingly */
+    MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
+  }
+  /* When selected index is in range [4;7] */
+  else
+  {
+    /* Modify Attr<i> field of MPU_MAIR1 accordingly */
+    MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
+  }
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Configure a non-secure MPU attributes index
+  * @rmtoll MPU_MAIR0    AttrX     LL_MPU_ConfigAttributes_NS\n
+  *         MPU_MAIR1    AttrX     LL_MPU_ConfigAttributes_NS
+  * @param  AttIndex This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+  *         @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+  * @param  Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t  Attributes)
+{
+  /* When selected index is in range [0;3] */
+  if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
+  {
+    /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
+    MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
+  }
+  /* When selected index is in range [4;7] */
+  else
+  {
+    /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
+    MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
+  }
+}
+#endif /* MPU_NS */
+
+/**
+  * @brief  Configure a MPU region limit address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_SetRegionLimitAddress\n
+  *         MPU_RLAR     LIMIT     LL_MPU_SetRegionLimitAddress
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  LimitAddress Value of region limit address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Set limit address */
+  MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+  * @brief  Get a MPU region limit address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_GetRegionLimitAddress\n
+  *         MPU_RLAR     LIMIT     LL_MPU_GetRegionLimitAddress
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @retval MPU region limit address
+  */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+  * @brief  Configure a MPU region base address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_SetRegionBaseAddress\n
+  *         MPU_RBAR     BASE      LL_MPU_SetRegionBaseAddress
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  BaseAddress Value of region base address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Set base address */
+  MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
+}
+
+/**
+  * @brief  Get a MPU region base address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_GetRegionBaseAddress\n
+  *         MPU_RBAR     BASE      LL_MPU_GetRegionBaseAddress
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @retval MPU region base address
+  */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
+}
+
+/**
+  * @brief  Configure a MPU region access attributes and enable a region
+  * @rmtoll MPU_RNR      REGION    LL_MPU_SetRegionAccess\n
+  *         MPU_RBAR     XN        LL_MPU_SetRegionAccess\n
+  *         MPU_RBAR     AP        LL_MPU_SetRegionAccess\n
+  *         MPU_RBAR     SH        LL_MPU_SetRegionAccess
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+  *              or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+  *         @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+  *              or @ref LL_MPU_REGION_ALL_RO
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  /* Set base address */
+  MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
+}
+
+/**
+  * @brief  Get a MPU region access attributes
+  * @rmtoll MPU_RNR      REGION    LL_MPU_GetRegionAccess\n
+  *         MPU_RBAR     XN        LL_MPU_GetRegionAccess\n
+  *         MPU_RBAR     AP        LL_MPU_GetRegionAccess\n
+  *         MPU_RBAR     SH        LL_MPU_GetRegionAccess
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @retval MPU region access attributes
+  */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+
+  return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
+}
+
+#ifdef MPU_NS
+/**
+  * @brief  Configure a non-secure MPU region limit address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_SetRegionLimitAddress_NS\n
+  *         MPU_RLAR     LIMIT     LL_MPU_SetRegionLimitAddress_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  LimitAddress Value of region limit address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Set limit address */
+  MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+  * @brief  Get a non-secure MPU region limit address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_GetRegionLimitAddress_NS\n
+  *         MPU_RLAR     LIMIT     LL_MPU_GetRegionLimitAddress_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @retval Non-secure MPU region limit address
+  */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+  * @brief  Configure a non-secure MPU region base address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_SetRegionBaseAddress_NS\n
+  *         MPU_RBAR     BASE      LL_MPU_SetRegionBaseAddress_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  BaseAddress Value of region base address
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Set base address */
+  MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
+}
+
+/**
+  * @brief  Get a non-secure MPU region base address
+  * @rmtoll MPU_RNR      REGION    LL_MPU_GetRegionBaseAddress_NS\n
+  *         MPU_RBAR     BASE      LL_MPU_GetRegionBaseAddress_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @retval Non-secure MPU region base address
+  */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
+}
+
+/**
+  * @brief  Configure a non-secure MPU region access attributes and enable a region
+  * @rmtoll MPU_RNR      REGION    LL_MPU_SetRegionAccess_NS\n
+  *         MPU_RBAR     XN        LL_MPU_SetRegionAccess_NS\n
+  *         MPU_RBAR     AP        LL_MPU_SetRegionAccess_NS\n
+  *         MPU_RBAR     SH        LL_MPU_SetRegionAccess_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
+  *              or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+  *         @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
+  *              or @ref LL_MPU_REGION_ALL_RO
+  * @note   Cortex-M55 supports 16 secure and 16 non secure regions.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  /* Set base address Attributes */
+  MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
+}
+
+/**
+  * @brief  Get a non-secure MPU region access attributes
+  * @rmtoll MPU_RNR      REGION    LL_MPU_GetRegionAccess_NS\n
+  *         MPU_RBAR     XN        LL_MPU_GetRegionAccess_NS\n
+  *         MPU_RBAR     AP        LL_MPU_GetRegionAccess_NS\n
+  *         MPU_RBAR     SH        LL_MPU_GetRegionAccess_NS
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @retval Non-secure MPU region access attributes
+  */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU_NS->RNR, Region);
+
+  return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
+}
+#endif /* MPU_NS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_CORTEX_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_crc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_crc.h
new file mode 100644
index 000000000..51bc7876f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_crc.h
@@ -0,0 +1,548 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_CRC_H
+#define STM32N6xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
+  * @{
+  */
+#define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_INPUT_REVERSE_TYPE Input Reverse Type
+  * @{
+  */
+#define LL_CRC_INDATA_REVERSETYPE_BIT             0x00000000U               /*!< Input Data reverse type at bit level granularity */
+#define LL_CRC_INDATA_REVERSETYPE_BYTE_HALFWORD   CRC_CR_RTYPE_IN           /*!< Input Data reverse type at byte or half-word level granularity */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_OUTPUT_REVERSE_TYPE Output Reverse Type
+  * @{
+  */
+#define LL_CRC_OUTDATA_REVERSETYPE_BIT            0x00000000U              /*!< Output Data reverse type at bit level granularity */
+#define LL_CRC_OUTDATA_REVERSETYPE_BYTE_HALFWORD  CRC_CR_RTYPE_OUT         /*!< Output Data reverse type at byte or half-word level granularity */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
+  * @{
+  */
+#define LL_CRC_INDATA_REVERSE_NONE             0x00000000U                          /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_BIT_BYBYTE       CRC_CR_REV_IN_0                      /*!< Input Data bit reversal done by byte */
+#define LL_CRC_INDATA_REVERSE_BYTE             LL_CRC_INDATA_REVERSE_BIT_BYBYTE     /*!< Definition for compatibility with legacy code */
+#define LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD  (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_0)  /*!< Input Data half-word reversal done by word */
+#define LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD   CRC_CR_REV_IN_1                      /*!< Input Data bit reversal done by half-word */
+#define LL_CRC_INDATA_REVERSE_HALFWORD         LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD /*!< Definition for compatibility with legacy code */
+#define LL_CRC_INDATA_REVERSE_BYTE_BYWORD      (CRC_CR_RTYPE_IN | CRC_CR_REV_IN_1)  /*!< Input Data byte reversal done by word */
+#define LL_CRC_INDATA_REVERSE_BIT_BYWORD       (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)  /*!< Input Data bit reversal done by word */
+#define LL_CRC_INDATA_REVERSE_WORD             LL_CRC_INDATA_REVERSE_BIT_BYWORD     /*!< Definition for compatibility with legacy code */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
+  * @{
+  */
+#define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                           /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT_0                      /*!< Output Data bit reversal done by bit */
+#define LL_CRC_OUTDATA_REVERSE_HALFWORD    (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_0) /*!< Output Data half-word reversal done by word */
+#define LL_CRC_OUTDATA_REVERSE_BYTE        (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT_1) /*!< Output Data byte reversal done by word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value
+  * @brief    Normal representation of this polynomial value is
+  *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
+
+/**
+  * @brief  Read a value in CRC register
+  * @param  __INSTANCE__ CRC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Reset the CRC calculation unit.
+  * @note   If Programmable Initial CRC value feature
+  *         is available, also set the Data Register to the value stored in the
+  *         CRC_INIT register, otherwise, reset Data Register to its default value.
+  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
+  * @param  CRCx CRC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+  SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+  * @brief  Configure size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @param  PolySize This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
+}
+
+/**
+  * @brief  Return size of the polynomial.
+  * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_POLYLENGTH_32B
+  *         @arg @ref LL_CRC_POLYLENGTH_16B
+  *         @arg @ref LL_CRC_POLYLENGTH_8B
+  *         @arg @ref LL_CRC_POLYLENGTH_7B
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
+}
+
+/**
+  * @brief  Configure the reversal type of the input data
+  * @rmtoll CR           RTYPE_IN        LL_CRC_SetInputDataReverseType
+  * @param  CRCx CRC Instance
+  * @param  ReverseType This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSETYPE_BIT
+  *         @arg @ref LL_CRC_INDATA_REVERSETYPE_BYTE_HALFWORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseType(CRC_TypeDef *CRCx, uint32_t ReverseType)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_RTYPE_IN, ReverseType);
+}
+
+/**
+  * @brief  Return input data type of reversal
+  * @rmtoll CR           RTYPE_IN        LL_CRC_GetInputDataReverseType
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSETYPE_BIT
+  *         @arg @ref LL_CRC_INDATA_REVERSETYPE_BYTE_HALFWORD
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseType(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RTYPE_IN));
+}
+
+/**
+  * @brief  Configure the reversal type of the output data
+  * @rmtoll CR           RTYPE_OUT        LL_CRC_SetOutputDataReverseType
+  * @param  CRCx CRC Instance
+  * @param  ReverseType This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BIT
+  *         @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BYTE_HALFWORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseType(CRC_TypeDef *CRCx, uint32_t ReverseType)
+{
+  MODIFY_REG(CRCx->CR, CRC_CR_RTYPE_OUT, ReverseType);
+}
+
+/**
+  * @brief  Return output data type of reversal
+  * @rmtoll CR           RTYPE_OUT        LL_CRC_GetOutputDataReverseType
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BIT
+  *         @arg @ref LL_CRC_OUTDATA_REVERSETYPE_BYTE_HALFWORD
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseType(CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_RTYPE_OUT));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the input data
+  * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYBYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE_BYWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYWORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, (CRC_CR_RTYPE_IN | CRC_CR_REV_IN), ReverseMode);
+}
+
+/**
+  * @brief  Return mode of reversal for input data bit order
+  * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYBYTE
+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD_BYWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYHALFWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE_BYWORD
+  *         @arg @ref LL_CRC_INDATA_REVERSE_BIT_BYWORD
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, (CRC_CR_RTYPE_IN | CRC_CR_REV_IN)));
+}
+
+/**
+  * @brief  Configure the reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @param  ReverseMode This parameter can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BYTE
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+  MODIFY_REG(CRCx->CR, (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT), ReverseMode);
+}
+
+/**
+  * @brief Return mode of reversal of the bit order of the Output data
+  * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
+  * @param  CRCx CRC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_HALFWORD
+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BYTE
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_BIT(CRCx->CR, (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT)));
+}
+
+/**
+  * @brief  Initialize the Programmable initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to write the correct value
+  * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
+  * @rmtoll INIT         INIT          LL_CRC_SetInitialData
+  * @param  CRCx CRC Instance
+  * @param  InitCrc Value to be programmed in Programmable initial CRC value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
+{
+  WRITE_REG(CRCx->INIT, InitCrc);
+}
+
+/**
+  * @brief  Return current Initial CRC value.
+  * @note   If the CRC size is less than 32 bits, the least significant bits
+  *         are used to read the correct value
+  * @rmtoll INIT         INIT          LL_CRC_GetInitialData
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable initial CRC value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->INIT));
+}
+
+/**
+  * @brief  Initialize the Programmable polynomial value
+  *         (coefficients of the polynomial to be used for CRC calculation).
+  * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
+{
+  WRITE_REG(CRCx->POL, PolynomCoef);
+}
+
+/**
+  * @brief  Return current Programmable polynomial value
+  * @note   Please check Reference Manual and existing Errata Sheets,
+  *         regarding possible limitations for Polynomial values usage.
+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef
+  * @param  CRCx CRC Instance
+  * @retval Value programmed in Programmable Polynomial value register
+  */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->POL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Write given 32-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData32
+  * @param  CRCx CRC Instance
+  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+  * @brief  Write given 16-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData16
+  * @param  CRCx CRC Instance
+  * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
+{
+  __IO uint16_t *pReg;
+
+  pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);                             /* Derogation MisraC2012 R.11.5 */
+  *pReg = InData;
+}
+
+/**
+  * @brief  Write given 8-bit data to the CRC calculator
+  * @rmtoll DR           DR            LL_CRC_FeedData8
+  * @param  CRCx CRC Instance
+  * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
+{
+  *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
+}
+
+/**
+  * @brief  Return current CRC calculation result. 32 bits value is returned.
+  * @rmtoll DR           DR            LL_CRC_ReadData32
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+  */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+  * @brief  Return current CRC calculation result. 16 bits value is returned.
+  * @note   This function is expected to be used in a 16 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData16
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
+  */
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
+{
+  return (uint16_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 8 bits value is returned.
+  * @note   This function is expected to be used in a 8 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData8
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
+{
+  return (uint8_t)READ_REG(CRCx->DR);
+}
+
+/**
+  * @brief  Return current CRC calculation result. 7 bits value is returned.
+  * @note   This function is expected to be used in a 7 bits CRC polynomial size context.
+  * @rmtoll DR           DR            LL_CRC_ReadData7
+  * @param  CRCx CRC Instance
+  * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
+  */
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
+{
+  return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
+}
+
+/**
+  * @brief  Return data stored in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one 32-bit long data.
+  * @rmtoll IDR          IDR           LL_CRC_Read_IDR
+  * @param  CRCx CRC Instance
+  * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
+  */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
+{
+  return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+  * @brief  Store data in the Independent Data(IDR) register.
+  * @note   This register can be used as a temporary storage location for one 32-bit long data.
+  * @rmtoll IDR          IDR           LL_CRC_Write_IDR
+  * @param  CRCx CRC Instance
+  * @param  InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+  *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_CRC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dlyb.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dlyb.h
new file mode 100644
index 000000000..4be189400
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dlyb.h
@@ -0,0 +1,143 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_dlyb.h
+  * @author  MCD Application Team
+  * @brief   Header file of DelayBlock module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_DLYB_H
+#define STM32N6xx_LL_DLYB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED)
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2)
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DLYB_LL DLYB
+  * @{
+  */
+
+/**
+  * @brief  DLYB Configuration Structure definition
+ */
+
+typedef struct
+{
+  uint32_t Units;                  /*!< Specifies the Delay of a unit delay cell.
+                                        This parameter can be a value between 0 and DLYB_MAX_UNIT               */
+
+  uint32_t PhaseSel;               /*!< Specifies the Phase for the output clock.
+                                        This parameter can be a value between 0 and DLYB_MAX_SELECT             */
+} LL_DLYB_CfgTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DLYB_Exported_Constants DLYB Exported Constants
+  * @{
+  */
+
+#define DLYB_MAX_UNIT   ((uint32_t)0x00000080U) /*!< Max UNIT value (128)  */
+#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */
+
+/**
+  * @}
+  */
+
+/** @defgroup DLYB_LL_Flags DLYB Flags
+  * @{
+  */
+
+#define DLYB_FLAG_LNGF DLYB_CFGR_LNGF
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DLYB_LL_Exported_Functions DLYB Exported Functions
+  * @{
+  */
+
+/** @defgroup DLYB_LL_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  DLYB Enable
+  * @param  DLYBx DLYB Instance
+  * @retval None
+  */
+
+__STATIC_INLINE void LL_DLYB_Enable(DLYB_TypeDef *DLYBx)
+{
+  SET_BIT(DLYBx->CR, DLYB_CR_DEN);
+}
+
+/** @brief  Disable the DLYB.
+  * @param  DLYBx DLYB Instance.
+  * @retval None
+  */
+
+__STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx)
+{
+  CLEAR_BIT(DLYBx->CR, DLYB_CR_DEN);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DLYB_Control_Functions DLYB Control functions
+  * @{
+  */
+
+void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, const LL_DLYB_CfgTypeDef  *pdlyb_cfg);
+void LL_DLYB_GetDelay(const DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
+uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */
+#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_DLYB_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dma.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dma.h
new file mode 100644
index 000000000..78e78c94a
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dma.h
@@ -0,0 +1,8115 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+ @verbatim
+  ==============================================================================
+                        ##### LL DMA driver acronyms #####
+  ==============================================================================
+  [..]  Acronyms table :
+                   =========================================
+                   || Acronym ||                          ||
+                   =========================================
+                   || SRC     ||  Source                  ||
+                   || DEST    ||  Destination             ||
+                   || ADDR    ||  Address                 ||
+                   || ADDRS   ||  Addresses               ||
+                   || INC     ||  Increment / Incremented ||
+                   || DEC     ||  Decrement / Decremented ||
+                   || BLK     ||  Block                   ||
+                   || RPT     ||  Repeat / Repeated       ||
+                   || TRIG    ||  Trigger                 ||
+                   =========================================
+ @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_DMA_H
+#define STM32N6xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if (defined (GPDMA1) || defined (HPDMA1))
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+#define DMA_CHANNEL0_OFFSET  (0x00000050UL)
+#define DMA_CHANNEL1_OFFSET  (0x000000D0UL)
+#define DMA_CHANNEL2_OFFSET  (0x00000150UL)
+#define DMA_CHANNEL3_OFFSET  (0x000001D0UL)
+#define DMA_CHANNEL4_OFFSET  (0x00000250UL)
+#define DMA_CHANNEL5_OFFSET  (0x000002D0UL)
+#define DMA_CHANNEL6_OFFSET  (0x00000350UL)
+#define DMA_CHANNEL7_OFFSET  (0x000003D0UL)
+#define DMA_CHANNEL8_OFFSET  (0x00000450UL)
+#define DMA_CHANNEL9_OFFSET  (0x000004D0UL)
+#define DMA_CHANNEL10_OFFSET (0x00000550UL)
+#define DMA_CHANNEL11_OFFSET (0x000005D0UL)
+#define DMA_CHANNEL12_OFFSET (0x00000650UL)
+#define DMA_CHANNEL13_OFFSET (0x000006D0UL)
+#define DMA_CHANNEL14_OFFSET (0x00000750UL)
+#define DMA_CHANNEL15_OFFSET (0x000007D0UL)
+
+/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
+static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
+{
+  DMA_CHANNEL0_OFFSET,  DMA_CHANNEL1_OFFSET,  DMA_CHANNEL2_OFFSET,  DMA_CHANNEL3_OFFSET,
+  DMA_CHANNEL4_OFFSET,  DMA_CHANNEL5_OFFSET,  DMA_CHANNEL6_OFFSET,  DMA_CHANNEL7_OFFSET,
+  DMA_CHANNEL8_OFFSET,  DMA_CHANNEL9_OFFSET,  DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET,
+  DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET,
+};
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  LL DMA init structure definition.
+  */
+typedef struct
+{
+  uint32_t SrcAddress;               /*!< This field specify the data transfer source address.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcAddress().                                                */
+
+  uint32_t DestAddress;              /*!< This field specify the data transfer destination address.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestAddress().                                               */
+
+  uint32_t Direction;                /*!< This field specify the data transfer direction.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDataTransferDirection().                                     */
+
+  uint32_t BlkHWRequest;             /*!< This field specify the hardware request unity.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetBlkHWRequest().                                              */
+
+  uint32_t DataAlignment;            /*!< This field specify the transfer data alignment.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDataAlignment().                                             */
+
+  uint32_t SrcBurstLength;           /*!< This field specify the source burst length of transfer in bytes.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter must be a value between Min_Data = 1 and Max_Data = 64.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcBurstLength().                                            */
+
+  uint32_t DestBurstLength;          /*!< This field specify the destination burst length of transfer in bytes.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter must be a value between Min_Data = 1 and Max_Data = 64.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestBurstLength().                                           */
+
+  uint32_t SrcDataWidth;             /*!< This field specify the source data width.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcDataWidth().                                              */
+
+  uint32_t DestDataWidth;            /*!< This field specify the destination data width.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestDataWidth().                                             */
+
+  uint32_t SrcIncMode;               /*!< This field specify the source burst increment mode.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcIncMode().                                                */
+
+  uint32_t DestIncMode;              /*!< This field specify the destination burst increment mode.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestIncMode().                                               */
+
+  uint32_t Priority;                 /*!< This field specify the channel priority level.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetChannelPriorityLevel().                                      */
+
+  uint32_t BlkDataLength;            /*!< This field specify the length of a block transfer in bytes.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetBlkDataLength().                                             */
+
+  uint32_t BlkRptCount;              /*!< This field specify the number of repetitions of the current block.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value between 1 and 2048 Min_Data = 0
+                                          and Max_Data = 0x000007FF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetBlkRptCount().                                               */
+
+  uint32_t TriggerMode;              /*!< This field specify the trigger mode.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetTriggerMode().                                               */
+
+  uint32_t TriggerPolarity;          /*!< This field specify the trigger event polarity.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetTriggerPolarity().                                           */
+
+  uint32_t TriggerSelection;         /*!< This field specify the trigger event selection.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetHWTrigger().                                                 */
+
+  uint32_t Request;                  /*!< This field specify the peripheral request selection.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetPeriphRequest().                                             */
+
+  uint32_t TransferEventMode;        /*!< This field specify the transfer event mode.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetTransferEventMode().                                         */
+
+  uint32_t DestWordExchange;         /*!< This field specify the destination  word exchange.
+                                          Programming this field is mandatory for all available HPDMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestWordExchange().                                          */
+
+  uint32_t DestHWordExchange;        /*!< This field specify the destination half word exchange.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestHWordExchange().                                         */
+
+  uint32_t DestByteExchange;         /*!< This field specify the destination byte exchange.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestByteExchange().                                          */
+
+  uint32_t SrcByteExchange;          /*!< This field specify the source byte exchange.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcByteExchange().                                           */
+
+  uint32_t SrcAllocatedPort;         /*!< This field specify the source allocated port.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcAllocatedPort().                                          */
+
+  uint32_t DestAllocatedPort;        /*!< This field specify the destination allocated port.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestAllocatedPort().                                         */
+
+  uint32_t LinkAllocatedPort;        /*!< This field specify the linked-list allocated port.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetLinkAllocatedPort().                                         */
+
+  uint32_t LinkStepMode;             /*!< This field specify the link step mode.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetLinkStepMode().                                              */
+
+  uint32_t SrcAddrUpdateMode;        /*!< This field specify the source address update mode.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcAddrUpdate().                                             */
+
+  uint32_t DestAddrUpdateMode;       /*!< This field specify the destination address update mode.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestAddrUpdate().                                            */
+
+  uint32_t SrcAddrOffset;            /*!< This field specifies the source address offset.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value Between 0 to 0x00001FFF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetSrcAddrUpdateValue().                                        */
+
+  uint32_t DestAddrOffset;           /*!< This field specifies the destination address offset.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value Between 0 to 0x00001FFF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetDestAddrUpdateValue().                                       */
+
+  uint32_t BlkRptSrcAddrUpdateMode;  /*!< This field specifies the block repeat source address update mode.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetBlkRptSrcAddrUpdate().                                       */
+
+  uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetBlkRptDestAddrUpdate().                                      */
+
+  uint32_t BlkRptSrcAddrOffset;      /*!< This field specifies the block repeat source address offset.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value Between 0 to 0x0000FFFF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetBlkRptSrcAddrUpdateValue().                                  */
+
+  uint32_t BlkRptDestAddrOffset;     /*!< This field specifies the block repeat destination address offset.
+                                          Programming this field is mandatory only for 2D addressing channels.
+                                          This parameter can be a value Between 0 to 0x0000FFFF.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetBlkRptDestAddrUpdateValue().                                 */
+
+  uint32_t LinkedListBaseAddr;       /*!< This field specify the linked list base address.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
+                                          bytes are always forced to 0).
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetLinkedListBaseAddr().                                        */
+
+  uint32_t LinkedListAddrOffset;     /*!< Specifies the linked list address offset.
+                                          Programming this field is mandatory for all available DMA channels.
+                                          This parameter can be a value Between 0 to 0x0000FFFC.
+                                          This feature can be modified afterwards using unitary function
+                                          @ref LL_DMA_SetLinkedListAddrOffset().                                      */
+
+  uint32_t Mode;                     /*!< Specifies the transfer mode for the DMA channel.
+                                          This parameter can be a value of @ref DMA_LL_TRANSFER_MODE                  */
+} LL_DMA_InitTypeDef;
+
+
+/**
+  * @brief  LL DMA init linked list structure definition.
+  */
+typedef struct
+{
+  uint32_t Priority;             /*!< This field specify the channel priority level.
+                                      Programming this field is mandatory for all available DMA channels.
+                                      This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_DMA_SetChannelPriorityLevel().                                          */
+
+  uint32_t LinkStepMode;         /*!< This field specify the link step mode.
+                                      Programming this field is mandatory for all available DMA channels.
+                                      This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_DMA_SetLinkStepMode().                                                  */
+
+  uint32_t LinkAllocatedPort;    /*!< This field specify the linked-list allocated port.
+                                      Programming this field is mandatory for all available DMA channels.
+                                      This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_DMA_SetLinkAllocatedPort().                                             */
+
+  uint32_t TransferEventMode;    /*!< This field specify the transfer event mode.
+                                      Programming this field is mandatory for all available DMA channels.
+                                      This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_DMA_SetTransferEventMode().                                             */
+} LL_DMA_InitLinkedListTypeDef;
+
+
+/**
+  * @brief  LL DMA node init structure definition.
+  */
+typedef struct
+{
+  /* CTR1 register fields ******************************************************
+     If any CTR1 fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CTR1 register fields and enable update
+     CTR1 register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+  */
+#if defined (CPU_IN_SECURE_STATE)
+  uint32_t DestSecure;           /*!< This field specify the destination secure.
+                                      This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
+#endif /* CPU_IN_SECURE_STATE */
+
+  uint32_t DestAllocatedPort;    /*!< This field specify the destination allocated port.
+                                      This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.     */
+
+  uint32_t DestWordExchange;     /*!< This field specify the destination word exchange.
+                                      This parameter can be a value of @ref DMA_LL_EC_DEST_WORD_EXCHANGE.             */
+
+  uint32_t DestHWordExchange;    /*!< This field specify the destination half word exchange.
+                                      This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.         */
+
+  uint32_t DestByteExchange;     /*!< This field specify the destination byte exchange.
+                                      This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.             */
+
+  uint32_t DestBurstLength;      /*!< This field specify the destination burst length of transfer in bytes.
+                                      This parameter must be a value between Min_Data = 1 and Max_Data = 64.          */
+
+  uint32_t DestIncMode;          /*!< This field specify the destination increment mode.
+                                      This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.     */
+
+  uint32_t DestDataWidth;        /*!< This field specify the destination data width.
+                                      This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.         */
+
+#if defined (CPU_IN_SECURE_STATE)
+  uint32_t SrcSecure;            /*!< This field specify the source secure.
+                                      This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE.      */
+#endif /* CPU_IN_SECURE_STATE */
+
+  uint32_t SrcAllocatedPort;     /*!< This field specify the source allocated port.
+                                      This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.          */
+
+  uint32_t SrcByteExchange;      /*!< This field specify the source byte exchange.
+                                      This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.              */
+
+  uint32_t DataAlignment;        /*!< This field specify the transfer data alignment.
+                                      This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.                 */
+
+  uint32_t SrcBurstLength;       /*!< This field specify the source burst length of transfer in bytes.
+                                      This parameter must be a value between Min_Data = 1 and Max_Data = 64.          */
+
+  uint32_t SrcIncMode;           /*!< This field specify the source increment mode.
+                                      This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.          */
+
+  uint32_t SrcDataWidth;         /*!< This field specify the source data width.
+                                      This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.              */
+
+
+  /* CTR2 register fields ******************************************************
+     If any CTR2 fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CTR2 register fields and enable update
+     CTR2 register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+     For all node created, filling all fields is mandatory.
+  */
+  uint32_t TransferEventMode;    /*!< This field specify the transfer event mode.
+                                      This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.            */
+
+  uint32_t TriggerPolarity;      /*!< This field specify the trigger event polarity.
+                                      This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.               */
+
+  uint32_t TriggerSelection;     /*!< This field specify the trigger event selection.
+                                      This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.              */
+
+  uint32_t TriggerMode;          /*!< This field specify the trigger mode.
+                                      This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.                   */
+
+  uint32_t BlkHWRequest;         /*!< This field specify the hardware request unity.
+                                      This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.                  */
+
+  uint32_t Direction;            /*!< This field specify the transfer direction.
+                                      This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.             */
+
+  uint32_t Request;              /*!< This field specify the peripheral request selection.
+                                      This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.              */
+
+  uint32_t Mode;                  /*!< This field DMA Transfer Mode.
+                                      This parameter can be a value of @ref DMA_LL_TRANSFER_MODE.                     */
+
+  /* CBR1 register fields ******************************************************
+     If any CBR1 fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CBR1 register fields and enable update
+     CBR1 register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+     If the node to be created is not for 2D addressing channels, there is no
+     need to fill the following fields for CBR1 register :
+     - BlkReptDestAddrUpdate.
+     - BlkRptSrcAddrUpdate.
+     - DestAddrUpdate.
+     - SrcAddrUpdate.
+     - BlkRptCount.
+  */
+  uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
+                                          This parameter can be a value of
+                                          @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.                               */
+
+  uint32_t BlkRptSrcAddrUpdateMode;  /*!< This field specifies the block repeat source address update mode.
+                                          This parameter can be a value of
+                                          @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.                                */
+
+  uint32_t DestAddrUpdateMode;       /*!< This field specify the Destination address update mode.
+                                          This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.      */
+
+  uint32_t SrcAddrUpdateMode;        /*!< This field specify the Source address update mode.
+                                          This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.       */
+
+  uint32_t BlkRptCount;              /*!< This field specify the number of repetitions of the current block.
+                                          This parameter can be a value between 1 and 2048 Min_Data = 0
+                                          and Max_Data = 0x000007FF.                                                  */
+
+  uint32_t BlkDataLength;            /*!< This field specify the length of a block transfer in bytes.
+                                          This parameter must be a value between Min_Data = 0
+                                          and Max_Data = 0x0000FFFF.                                                  */
+
+  /* CSAR register fields ******************************************************
+     If any CSAR fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CSAR register fields and enable update
+     CSAR register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+     For all node created, filling all fields is mandatory.
+  */
+  uint32_t SrcAddress;              /*!< This field specify the transfer source address.
+                                         This parameter must be a value between Min_Data = 0
+                                         and Max_Data = 0xFFFFFFFF.                                                   */
+
+
+  /* CDAR register fields ******************************************************
+     If any CDAR fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CDAR register fields and enable update
+     CDAR register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+     For all node created, filling all fields is mandatory.
+  */
+  uint32_t DestAddress;             /*!< This field specify the transfer destination address.
+                                         This parameter must be a value between Min_Data = 0
+                                         and Max_Data = 0xFFFFFFFF.                                                   */
+
+  /* CTR3 register fields ******************************************************
+     If any CTR3 fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CTR3 register fields and enable update
+     CTR3 register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+     This register is used only for 2D addressing channels.
+     If used channel is linear addressing, this register will be overwritten by
+     CLLR register in memory.
+     When this register is enabled on UpdateRegisters and the selected channel
+     is linear addressing, LL APIs will discard this register update in memory.
+  */
+  uint32_t DestAddrOffset;       /*!< This field specifies the destination address offset.
+                                      This parameter can be a value Between 0 to 0x00001FFF.                          */
+
+  uint32_t SrcAddrOffset;        /*!< This field specifies the source address offset.
+                                      This parameter can be a value Between 0 to 0x00001FFF.                          */
+
+
+  /* CBR2 register fields ******************************************************
+     If any CBR2 fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CBR2 register fields and enable update
+     CBR2 register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+     This register is used only for 2D addressing channels.
+     If used channel is linear addressing, this register will be discarded in
+     memory. When this register is enabled on UpdateRegisters and the selected
+     channel is linear addressing, LL APIs will discard this register update in
+     memory.
+  */
+  uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
+                                      This parameter can be a value Between 0 to 0x0000FFFF.                          */
+
+  uint32_t BlkRptSrcAddrOffset;  /*!< This field specifies the block repeat source address offset.
+                                      This parameter can be a value Between 0 to 0x0000FFFF.                          */
+
+  /* CLLR register fields ******************************************************
+     If any CLLR fields need to be updated comparing to previous node, it is
+     mandatory to update the new value in CLLR register fields and enable update
+     CLLR register in UpdateRegisters fields if it is not enabled in the
+     previous node.
+
+     If used channel is linear addressing, there is no need to enable/disable
+     CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
+     by LL APIs.
+  */
+  uint32_t UpdateRegisters;      /*!< Specifies the linked list register update.
+                                      This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE.     */
+
+  /* DMA Node type field *******************************************************
+     This parameter defines node types as node size and node content varies
+     between channels.
+     Thanks to this fields, linked list queue could be created independently
+     from channel selection. So, one queue could be executed by all DMA channels.
+  */
+  uint32_t NodeType;             /*!< Specifies the node type to be created.
+                                      This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE.           */
+} LL_DMA_InitNodeTypeDef;
+
+/**
+  * @brief  LL DMA linked list node structure definition.
+  * @note   For 2D addressing channels, the maximum node size is :
+  *         (4 Bytes * 8 registers = 32 Bytes).
+  *         For GPDMA & HPDMA linear addressing channels, the maximum node size is :
+  *         (4 Bytes * 6 registers = 24 Bytes).
+  */
+typedef struct
+{
+  __IO uint32_t LinkRegisters[8U];
+
+} LL_DMA_LinkNodeTypeDef;
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_DMA_CHANNEL_0   (0x00U)
+#define LL_DMA_CHANNEL_1   (0x01U)
+#define LL_DMA_CHANNEL_2   (0x02U)
+#define LL_DMA_CHANNEL_3   (0x03U)
+#define LL_DMA_CHANNEL_4   (0x04U)
+#define LL_DMA_CHANNEL_5   (0x05U)
+#define LL_DMA_CHANNEL_6   (0x06U)
+#define LL_DMA_CHANNEL_7   (0x07U)
+#define LL_DMA_CHANNEL_8   (0x08U)
+#define LL_DMA_CHANNEL_9   (0x09U)
+#define LL_DMA_CHANNEL_10  (0x0AU)
+#define LL_DMA_CHANNEL_11  (0x0BU)
+#define LL_DMA_CHANNEL_12  (0x0CU)
+#define LL_DMA_CHANNEL_13  (0x0DU)
+#define LL_DMA_CHANNEL_14  (0x0EU)
+#define LL_DMA_CHANNEL_15  (0x0FU)
+#if defined (USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL (0x10U)
+#endif /* USE_FULL_LL_DRIVER */
+/**
+  * @}
+  */
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
+  * @{
+  */
+#define LL_DMA_CLLR_OFFSET0 (0x00U)
+#define LL_DMA_CLLR_OFFSET1 (0x01U)
+#define LL_DMA_CLLR_OFFSET2 (0x02U)
+#define LL_DMA_CLLR_OFFSET3 (0x03U)
+#define LL_DMA_CLLR_OFFSET4 (0x04U)
+#define LL_DMA_CLLR_OFFSET5 (0x05U)
+#define LL_DMA_CLLR_OFFSET6 (0x06U)
+#define LL_DMA_CLLR_OFFSET7 (0x07U)
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup DMA_LL_EC_CID Priority Level
+  * @{
+  */
+#define LL_DMA_CHANNEL_STATIC_CID_0             (0U<<DMA_CCIDCFGR_SCID_Pos)         /*!< Channel is assigned to CID0 */
+#define LL_DMA_CHANNEL_STATIC_CID_1             (1U<<DMA_CCIDCFGR_SCID_Pos)         /*!< Channel is assigned to CID1 */
+#define LL_DMA_CHANNEL_STATIC_CID_2             (2U<<DMA_CCIDCFGR_SCID_Pos)         /*!< Channel is assigned to CID2 */
+#define LL_DMA_CHANNEL_STATIC_CID_3             (3U<<DMA_CCIDCFGR_SCID_Pos)         /*!< Channel is assigned to CID3 */
+#define LL_DMA_CHANNEL_STATIC_CID_4             (4U<<DMA_CCIDCFGR_SCID_Pos)         /*!< Channel is assigned to CID4 */
+#define LL_DMA_CHANNEL_STATIC_CID_5             (5U<<DMA_CCIDCFGR_SCID_Pos)         /*!< Channel is assigned to CID5 */
+#define LL_DMA_CHANNEL_STATIC_CID_6             (6U<<DMA_CCIDCFGR_SCID_Pos)         /*!< Channel is assigned to CID6 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY_LEVEL DMA Priority Level
+  * @{
+  */
+#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT  0x00000000U    /*!< Priority level : Low Priority, Low Weight  */
+#define LL_DMA_LOW_PRIORITY_MID_WEIGHT  DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight  */
+#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
+#define LL_DMA_HIGH_PRIORITY            DMA_CCR_PRIO   /*!< Priority level : High Priority             */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
+  * @{
+  */
+#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
+#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
+  * @{
+  */
+#define LL_DMA_LSM_FULL_EXECUTION  0x00000000U /*!< Channel execute the full linked list        */
+#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DEST_WORD_EXCHANGE Destination Word Exchange
+  * @{
+  */
+#define LL_DMA_DEST_WORD_PRESERVE     0x00000000U  /*!< No destination Word exchange when destination data width
+                                                        is double-word                                                */
+#define LL_DMA_DEST_WORD_EXCHANGE     DMA_CTR1_DWX /*!< Destination Word exchange when destination data width
+                                                        is double-word                                                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
+  * @{
+  */
+#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U  /*!< No destination Half-Word exchange when destination data width
+                                                        is word                                                       */
+#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width
+                                                        is word                                                       */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
+  * @{
+  */
+#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U  /*!< No destination Byte exchange when destination data width > Byte */
+#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
+  * @{
+  */
+#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U  /*!< No source Byte exchange when source data width is word */
+#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
+  * @{
+  */
+#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U  /*!< Source Allocated Port 0 */
+#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
+  * @{
+  */
+#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U  /*!< Destination Allocated Port 0 */
+#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
+  * @{
+  */
+#define LL_DMA_DEST_FIXED       0x00000000U   /*!< Destination fixed single/burst       */
+#define LL_DMA_DEST_INCREMENT   DMA_CTR1_DINC /*!< Destination incremented single/burst */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
+  * @{
+  */
+#define LL_DMA_DEST_DATAWIDTH_BYTE       0x00000000U         /*!< Destination Data Width : Byte       */
+#define LL_DMA_DEST_DATAWIDTH_HALFWORD   DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord   */
+#define LL_DMA_DEST_DATAWIDTH_WORD       DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word       */
+#define LL_DMA_DEST_DATAWIDTH_DOUBLEWORD DMA_CTR1_DDW_LOG2   /*!< Destination Data Width : DoubleWord */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
+  * @{
+  */
+#define LL_DMA_DATA_ALIGN_ZEROPADD    0x00000000U    /*!< If src data width < dest data width :
+                                                          => Right Aligned padded with 0 up to destination
+                                                             data width.
+                                                          If src data width > dest data width :
+                                                          => Right Aligned Left Truncated down to destination
+                                                             data width.                                              */
+#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
+                                                          => Right Aligned padded with sign extended up to destination
+                                                             data width.
+                                                          If src data width > dest data width :
+                                                          => Left Aligned Right Truncated down to the destination
+                                                             data width                                               */
+#define LL_DMA_DATA_PACK_UNPACK       DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
+                                                          => Packed at the destination data width
+                                                          If src data width > dest data width :
+                                                          => Unpacked at the destination data width                   */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
+  * @{
+  */
+#define LL_DMA_SRC_FIXED     0x00000000U   /*!< Source fixed single/burst */
+#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
+  * @{
+  */
+#define LL_DMA_SRC_DATAWIDTH_BYTE        0x00000000U         /*!< Source Data Width : Byte       */
+#define LL_DMA_SRC_DATAWIDTH_HALFWORD    DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord   */
+#define LL_DMA_SRC_DATAWIDTH_WORD        DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word       */
+#define LL_DMA_SRC_DATAWIDTH_DOUBLEWORD  DMA_CTR1_SDW_LOG2   /*!< Source Data Width : DoubleWord */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
+  * @{
+  */
+#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U   /*!< Hardware request is driven by a peripheral with a hardware
+                                                        request/acknowledge protocol at a burst level                 */
+#define LL_DMA_HWREQUEST_BLK         DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
+                                                        request/acknowledge protocol at a block level                 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
+  * @{
+  */
+#define LL_DMA_TCEM_BLK_TRANSFER         0x00000000U       /*!< The TC (and the HT) event is generated at the
+                                                                (respectively half) end of each block                 */
+#define LL_DMA_TCEM_RPT_BLK_TRANSFER     DMA_CTR2_TCEM_0   /*!< The TC (and the HT) event is generated at the
+                                                                (respectively half) end of the repeated block         */
+#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1   /*!< The TC (and the HT) event is generated at the
+                                                                (respectively half) end of each linked-list item      */
+#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM     /*!< The TC (and the HT) event is generated at the
+                                                                (respectively half) end of the last linked-list item  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
+  * @{
+  */
+#define LL_DMA_TRIG_POLARITY_MASKED    0x00000000U         /*!< No trigger of the selected DMA request.
+                                                                Masked trigger event                                  */
+#define LL_DMA_TRIG_POLARITY_RISING    DMA_CTR2_TRIGPOL_0  /*!< Trigger of the selected DMA request on the rising
+                                                                edge of the selected trigger event input              */
+#define LL_DMA_TRIG_POLARITY_FALLING   DMA_CTR2_TRIGPOL_1  /*!< Trigger of the selected DMA request on the falling
+                                                                edge of the selected trigger event input              */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
+  * @{
+  */
+#define LL_DMA_TRIGM_BLK_TRANSFER        0x00000000U      /*!< A block transfer is conditioned by (at least)
+                                                               one hit trigger                                        */
+#define LL_DMA_TRIGM_RPT_BLK_TRANSFER    DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
+                                                               one hit trigger                                        */
+#define LL_DMA_TRIGM_LLI_LINK_TRANSFER   DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
+                                                               one hit trigger                                        */
+#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM   /*!< A Single/Burst transfer is conditioned by (at least)
+                                                               one hit trigger                                        */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
+  * @{
+  */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction     */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U    /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ  /*!< Memory to peripheral direction */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_TRANSFER_MODE Transfer Mode
+  * @{
+  */
+#define LL_DMA_NORMAL          0x00000000U       /*!< Normal DMA transfer                     */
+#define LL_DMA_PFCTRL       DMA_CTR2_PFREQ       /*!< HW request peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
+  * @{
+  */
+#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U     /*!< Source address pointer is incremented after each block
+                                                              transfer by source update value                         */
+#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
+                                                              transfer by source update value                         */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
+  * @{
+  */
+#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U     /*!< Destination address is incremented after each block
+                                                               transfer by destination update value                   */
+#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
+                                                               transfer by destination update value                   */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
+  * @{
+  */
+#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U   /*!< Source address pointer is incremented after each burst
+                                                           transfer by source update value                            */
+#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
+                                                           transfer by source update value                            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
+  * @{
+  */
+#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U   /*!< Destination address pointer is incremented after each
+                                                            burst transfer by destination update value                */
+#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
+                                                            burst transfer by destination update value                */
+/**
+  * @}
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
+  * @{
+  */
+#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
+#define LL_DMA_CHANNEL_SEC  0x00000001U /*!< Secure channel  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
+  * @{
+  */
+#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U   /*!< NSecure transfer from the source */
+#define LL_DMA_CHANNEL_SRC_SEC  DMA_CTR1_SSEC /*!< Secure transfer from the source  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
+  * @{
+  */
+#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U   /*!< NSecure transfer from the destination */
+#define LL_DMA_CHANNEL_DEST_SEC  DMA_CTR1_DSEC /*!< Secure transfer from the destination  */
+/**
+  * @}
+  */
+#endif /* CPU_IN_SECURE_STATE */
+
+/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
+  * @{
+  */
+#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node      */
+#define LL_DMA_GPDMA_2D_NODE     0x02U /*!< GPDMA node : 2 dimension addressing node */
+#define LL_DMA_HPDMA_LINEAR_NODE 0x04U /*!< HPDMA node : linear addressing node      */
+#define LL_DMA_HPDMA_2D_NODE     0x08U /*!< HPDMA node : 2 dimension addressing node */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
+  * @{
+  */
+#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
+                                             available for all DMA channels                */
+#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
+                                             available for all DMA channels                */
+#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
+                                             available for all DMA channels                */
+#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
+                                             available for all DMA channels                */
+#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
+                                             available for all DMA channels                */
+#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
+                                             available only for 2D addressing DMA channels */
+#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
+                                             available only for 2D addressing DMA channels */
+#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
+                                             available for all DMA channels                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
+  * @{
+  */
+/* HPDMA1 requests */
+#define LL_HPDMA1_REQUEST_JPEG_RX       0U       /*!< HPDMA1 HW request is JPEG_RX        */
+#define LL_HPDMA1_REQUEST_JPEG_TX       1U       /*!< HPDMA1 HW request is JPEG_TX        */
+#define LL_HPDMA1_REQUEST_OCTOSPI1      2U       /*!< HPDMA1 HW request is OCTOSPI1       */
+#define LL_HPDMA1_REQUEST_OCTOSPI2      3U       /*!< HPDMA1 HW request is OCTOSPI2       */
+#define LL_HPDMA1_REQUEST_OCTOSPI3      4U       /*!< HPDMA1 HW request is OCTOSPI3       */
+#define LL_HPDMA1_REQUEST_FMC2_TXRX     5U       /*!< HPDMA1 HW request is FMC2_TXRX      */
+#define LL_HPDMA1_REQUEST_FMC2_BCH      6U       /*!< HPDMA1 HW request is FMC2_BCH       */
+#define LL_HPDMA1_REQUEST_ADC1          7U       /*!< HPDMA1 HW request is ADC1           */
+#define LL_HPDMA1_REQUEST_ADC2          8U       /*!< HPDMA1 HW request is ADC2           */
+#define LL_HPDMA1_REQUEST_CRYP_IN       9U       /*!< HPDMA1 HW request is CRYP_IN        */
+#define LL_HPDMA1_REQUEST_CRYP_OUT      10U      /*!< HPDMA1 HW request is CRYP_OUT       */
+#define LL_HPDMA1_REQUEST_SAES_OUT      11U      /*!< HPDMA1 HW request is SAES_OUT       */
+#define LL_HPDMA1_REQUEST_SAES_IN       12U      /*!< HPDMA1 HW request is SAES_IN        */
+#define LL_HPDMA1_REQUEST_HASH_IN       13U      /*!< HPDMA1 HW request is HASH_IN        */
+
+#define LL_HPDMA1_REQUEST_TIM1_CH1      14U      /*!< HPDMA1 HW request is TIM1_CH1       */
+#define LL_HPDMA1_REQUEST_TIM1_CH2      15U      /*!< HPDMA1 HW request is TIM1_CH2       */
+#define LL_HPDMA1_REQUEST_TIM1_CH3      16U      /*!< HPDMA1 HW request is TIM1_CH3       */
+#define LL_HPDMA1_REQUEST_TIM1_CH4      17U      /*!< HPDMA1 HW request is TIM1_CH4       */
+#define LL_HPDMA1_REQUEST_TIM1_UP       18U      /*!< HPDMA1 HW request is TIM1_UP        */
+#define LL_HPDMA1_REQUEST_TIM1_TRIG     19U      /*!< HPDMA1 HW request is TIM1_TRIG      */
+#define LL_HPDMA1_REQUEST_TIM1_COM      20U      /*!< HPDMA1 HW request is TIM1_COM       */
+
+#define LL_HPDMA1_REQUEST_TIM2_CH1      21U      /*!< HPDMA1 HW request is TIM2_CH1       */
+#define LL_HPDMA1_REQUEST_TIM2_CH2      22U      /*!< HPDMA1 HW request is TIM2_CH2       */
+#define LL_HPDMA1_REQUEST_TIM2_CH3      23U      /*!< HPDMA1 HW request is TIM2_CH3       */
+#define LL_HPDMA1_REQUEST_TIM2_CH4      24U      /*!< HPDMA1 HW request is TIM2_CH4       */
+#define LL_HPDMA1_REQUEST_TIM2_UP       25U      /*!< HPDMA1 HW request is TIM2_UP        */
+#define LL_HPDMA1_REQUEST_TIM2_TRIG     26U      /*!< HPDMA1 HW request is TIM2_TRIG      */
+
+#define LL_HPDMA1_REQUEST_TIM3_CH1      27U      /*!< HPDMA1 HW request is TIM3_CH1       */
+#define LL_HPDMA1_REQUEST_TIM3_CH2      28U      /*!< HPDMA1 HW request is TIM3_CH2       */
+#define LL_HPDMA1_REQUEST_TIM3_CH3      29U      /*!< HPDMA1 HW request is TIM3_CH3       */
+#define LL_HPDMA1_REQUEST_TIM3_CH4      30U      /*!< HPDMA1 HW request is TIM3_CH4       */
+#define LL_HPDMA1_REQUEST_TIM3_UP       31U      /*!< HPDMA1 HW request is TIM3_UP        */
+#define LL_HPDMA1_REQUEST_TIM3_TRIG     32U      /*!< HPDMA1 HW request is TIM3_TRIG      */
+
+#define LL_HPDMA1_REQUEST_TIM4_CH1      33U      /*!< HPDMA1 HW request is TIM4_CH1       */
+#define LL_HPDMA1_REQUEST_TIM4_CH2      34U      /*!< HPDMA1 HW request is TIM4_CH2       */
+#define LL_HPDMA1_REQUEST_TIM4_CH3      35U      /*!< HPDMA1 HW request is TIM4_CH3       */
+#define LL_HPDMA1_REQUEST_TIM4_CH4      36U      /*!< HPDMA1 HW request is TIM4_CH4       */
+#define LL_HPDMA1_REQUEST_TIM4_UP       37U      /*!< HPDMA1 HW request is TIM4_UP        */
+#define LL_HPDMA1_REQUEST_TIM4_TRIG     38U      /*!< HPDMA1 HW request is TIM4_TRIG      */
+
+#define LL_HPDMA1_REQUEST_TIM5_CH1      39U      /*!< HPDMA1 HW request is TIM5_CH1       */
+#define LL_HPDMA1_REQUEST_TIM5_CH2      40U      /*!< HPDMA1 HW request is TIM5_CH2       */
+#define LL_HPDMA1_REQUEST_TIM5_CH3      41U      /*!< HPDMA1 HW request is TIM5_CH3       */
+#define LL_HPDMA1_REQUEST_TIM5_CH4      42U      /*!< HPDMA1 HW request is TIM5_CH4       */
+#define LL_HPDMA1_REQUEST_TIM5_UP       43U      /*!< HPDMA1 HW request is TIM5_UP        */
+#define LL_HPDMA1_REQUEST_TIM5_TRIG     44U      /*!< HPDMA1 HW request is TIM5_TRIG      */
+
+#define LL_HPDMA1_REQUEST_TIM6_UP       45U      /*!< HPDMA1 HW request is TIM6_UP        */
+#define LL_HPDMA1_REQUEST_TIM7_UP       46U      /*!< HPDMA1 HW request is TIM7_UP        */
+
+#define LL_HPDMA1_REQUEST_TIM8_CH1      47U      /*!< HPDMA1 HW request is TIM8_CH1       */
+#define LL_HPDMA1_REQUEST_TIM8_CH2      48U      /*!< HPDMA1 HW request is TIM8_CH2       */
+#define LL_HPDMA1_REQUEST_TIM8_CH3      49U      /*!< HPDMA1 HW request is TIM8_CH3       */
+#define LL_HPDMA1_REQUEST_TIM8_CH4      50U      /*!< HPDMA1 HW request is TIM8_CH4       */
+#define LL_HPDMA1_REQUEST_TIM8_UP       51U      /*!< HPDMA1 HW request is TIM8_UP        */
+#define LL_HPDMA1_REQUEST_TIM8_TRIG     52U      /*!< HPDMA1 HW request is TIM8_TRIG      */
+#define LL_HPDMA1_REQUEST_TIM8_COM      53U      /*!< HPDMA1 HW request is TIM8_COM       */
+
+/* reserved                             54U                                               */
+/* reserved                             55U                                               */
+
+#define LL_HPDMA1_REQUEST_TIM15_CH1     56U      /*!< HPDMA1 HW request is TIM15_CH1      */
+#define LL_HPDMA1_REQUEST_TIM15_CH2     57U      /*!< HPDMA1 HW request is TIM15_CH2      */
+#define LL_HPDMA1_REQUEST_TIM15_UP      58U      /*!< HPDMA1 HW request is TIM15_UP       */
+#define LL_HPDMA1_REQUEST_TIM15_TRIG    59U      /*!< HPDMA1 HW request is TIM15_TRIG     */
+#define LL_HPDMA1_REQUEST_TIM15_COM     60U      /*!< HPDMA1 HW request is TIM15_COM      */
+
+#define LL_HPDMA1_REQUEST_TIM16_CH1     61U      /*!< HPDMA1 HW request is TIM16_CH1      */
+#define LL_HPDMA1_REQUEST_TIM16_UP      62U      /*!< HPDMA1 HW request is TIM16_UP       */
+#define LL_HPDMA1_REQUEST_TIM16_COM     63U      /*!< HPDMA1 HW request is TIM16_COM      */
+
+#define LL_HPDMA1_REQUEST_TIM17_CH1     64U      /*!< HPDMA1 HW request is TIM17_CH1      */
+#define LL_HPDMA1_REQUEST_TIM17_UP      65U      /*!< HPDMA1 HW request is TIM17_UP       */
+#define LL_HPDMA1_REQUEST_TIM17_COM     66U      /*!< HPDMA1 HW request is TIM17_COM      */
+
+#define LL_HPDMA1_REQUEST_TIM18_CH1     67U      /*!< HPDMA1 HW request is TIM18_CH1      */
+#define LL_HPDMA1_REQUEST_TIM18_UP      68U      /*!< HPDMA1 HW request is TIM18_UP       */
+#define LL_HPDMA1_REQUEST_TIM18_COM     69U      /*!< HPDMA1 HW request is TIM18_COM      */
+
+#define LL_HPDMA1_REQUEST_LPTIM1_IC1    70U      /*!< HPDMA1 HW request is LPTIM1_IC1     */
+#define LL_HPDMA1_REQUEST_LPTIM1_IC2    71U      /*!< HPDMA1 HW request is LPTIM1_IC2     */
+#define LL_HPDMA1_REQUEST_LPTIM1_UE     72U      /*!< HPDMA1 HW request is LPTIM1_UE      */
+#define LL_HPDMA1_REQUEST_LPTIM2_IC1    73U      /*!< HPDMA1 HW request is LPTIM2_IC1     */
+#define LL_HPDMA1_REQUEST_LPTIM2_IC2    74U      /*!< HPDMA1 HW request is LPTIM2_IC2     */
+#define LL_HPDMA1_REQUEST_LPTIM2_UE     75U      /*!< HPDMA1 HW request is LPTIM2_UE      */
+#define LL_HPDMA1_REQUEST_LPTIM3_IC1    76U      /*!< HPDMA1 HW request is LPTIM3_IC1     */
+#define LL_HPDMA1_REQUEST_LPTIM3_IC2    77U      /*!< HPDMA1 HW request is LPTIM3_IC2     */
+#define LL_HPDMA1_REQUEST_LPTIM3_UE     78U      /*!< HPDMA1 HW request is LPTIM3_UE      */
+
+#define LL_HPDMA1_REQUEST_SPI1_RX       79U      /*!< HPDMA1 HW request is SPI1_RX        */
+#define LL_HPDMA1_REQUEST_SPI1_TX       80U      /*!< HPDMA1 HW request is SPI1_TX        */
+#define LL_HPDMA1_REQUEST_SPI2_RX       81U      /*!< HPDMA1 HW request is SPI2_RX        */
+#define LL_HPDMA1_REQUEST_SPI2_TX       82U      /*!< HPDMA1 HW request is SPI2_TX        */
+#define LL_HPDMA1_REQUEST_SPI3_RX       83U      /*!< HPDMA1 HW request is SPI3_RX        */
+#define LL_HPDMA1_REQUEST_SPI3_TX       84U      /*!< HPDMA1 HW request is SPI3_TX        */
+#define LL_HPDMA1_REQUEST_SPI4_RX       85U      /*!< HPDMA1 HW request is SPI4_RX        */
+#define LL_HPDMA1_REQUEST_SPI4_TX       86U      /*!< HPDMA1 HW request is SPI4_TX        */
+#define LL_HPDMA1_REQUEST_SPI5_RX       87U      /*!< HPDMA1 HW request is SPI5_RX        */
+#define LL_HPDMA1_REQUEST_SPI5_TX       88U      /*!< HPDMA1 HW request is SPI5_TX        */
+#define LL_HPDMA1_REQUEST_SPI6_RX       89U      /*!< HPDMA1 HW request is SPI6_RX        */
+#define LL_HPDMA1_REQUEST_SPI6_TX       90U      /*!< HPDMA1 HW request is SPI6_TX        */
+
+#define LL_HPDMA1_REQUEST_SAI1_A        91U      /*!< HPDMA1 HW request is SAI1_A         */
+#define LL_HPDMA1_REQUEST_SAI1_B        92U      /*!< HPDMA1 HW request is SAI1_B         */
+#define LL_HPDMA1_REQUEST_SAI2_A        93U      /*!< HPDMA1 HW request is SAI2_A         */
+#define LL_HPDMA1_REQUEST_SAI2_B        94U      /*!< HPDMA1 HW request is SAI2_B         */
+
+#define LL_HPDMA1_REQUEST_I2C1_RX       95U      /*!< HPDMA1 HW request is I2C1_RX        */
+#define LL_HPDMA1_REQUEST_I2C1_TX       96U      /*!< HPDMA1 HW request is I2C1_TX        */
+#define LL_HPDMA1_REQUEST_I2C2_RX       97U      /*!< HPDMA1 HW request is I2C2_RX        */
+#define LL_HPDMA1_REQUEST_I2C2_TX       98U      /*!< HPDMA1 HW request is I2C2_TX        */
+#define LL_HPDMA1_REQUEST_I2C3_RX       99U      /*!< HPDMA1 HW request is I2C3_RX        */
+#define LL_HPDMA1_REQUEST_I2C3_TX       100U     /*!< HPDMA1 HW request is I2C3_TX        */
+
+#define LL_HPDMA1_REQUEST_I2C4_RX       101U     /*!< HPDMA1 HW request is I2C4_RX        */
+#define LL_HPDMA1_REQUEST_I2C4_TX       102U     /*!< HPDMA1 HW request is I2C4_TX        */
+
+#define LL_HPDMA1_REQUEST_I3C1_RX       103U     /*!< HPDMA1 HW request is I3C1_RX        */
+#define LL_HPDMA1_REQUEST_I3C1_TX       104U     /*!< HPDMA1 HW request is I3C1_TX        */
+#define LL_HPDMA1_REQUEST_I3C2_RX       105U     /*!< HPDMA1 HW request is I3C2_RX        */
+#define LL_HPDMA1_REQUEST_I3C2_TX       106U     /*!< HPDMA1 HW request is I3C2_TX        */
+
+#define LL_HPDMA1_REQUEST_USART1_RX     107U     /*!< HPDMA1 HW request is USART1_RX      */
+#define LL_HPDMA1_REQUEST_USART1_TX     108U     /*!< HPDMA1 HW request is USART1_TX      */
+#define LL_HPDMA1_REQUEST_USART2_RX     109U     /*!< HPDMA1 HW request is USART2_RX      */
+#define LL_HPDMA1_REQUEST_USART2_TX     110U     /*!< HPDMA1 HW request is USART2_TX      */
+#define LL_HPDMA1_REQUEST_USART3_RX     111U     /*!< HPDMA1 HW request is USART3_RX      */
+#define LL_HPDMA1_REQUEST_USART3_TX     112U     /*!< HPDMA1 HW request is USART3_TX      */
+#define LL_HPDMA1_REQUEST_UART4_RX      113U     /*!< HPDMA1 HW request is UART4_RX       */
+#define LL_HPDMA1_REQUEST_UART4_TX      114U     /*!< HPDMA1 HW request is UART4_TX       */
+#define LL_HPDMA1_REQUEST_UART5_RX      115U     /*!< HPDMA1 HW request is UART5_RX       */
+#define LL_HPDMA1_REQUEST_UART5_TX      116U     /*!< HPDMA1 HW request is UART5_TX       */
+#define LL_HPDMA1_REQUEST_USART6_RX     117U     /*!< HPDMA1 HW request is USART6_RX      */
+#define LL_HPDMA1_REQUEST_USART6_TX     118U     /*!< HPDMA1 HW request is USART6_TX      */
+#define LL_HPDMA1_REQUEST_UART7_RX      119U     /*!< HPDMA1 HW request is UART7_RX       */
+#define LL_HPDMA1_REQUEST_UART7_TX      120U     /*!< HPDMA1 HW request is UART7_TX       */
+#define LL_HPDMA1_REQUEST_UART8_RX      121U     /*!< HPDMA1 HW request is UART8_RX       */
+#define LL_HPDMA1_REQUEST_UART8_TX      122U     /*!< HPDMA1 HW request is UART8_TX       */
+#define LL_HPDMA1_REQUEST_UART9_RX      123U     /*!< HPDMA1 HW request is UART9_RX       */
+#define LL_HPDMA1_REQUEST_UART9_TX      124U     /*!< HPDMA1 HW request is UART9_TX       */
+#define LL_HPDMA1_REQUEST_USART10_RX    125U     /*!< HPDMA1 HW request is USART10_RX     */
+#define LL_HPDMA1_REQUEST_USART10_TX    126U     /*!< HPDMA1 HW request is USART10_TX     */
+
+#define LL_HPDMA1_REQUEST_LPUART1_RX    127U     /*!< HPDMA1 HW request is LPUART1_RX     */
+#define LL_HPDMA1_REQUEST_LPUART1_TX    128U     /*!< HPDMA1 HW request is LPUART1_TX     */
+
+#define LL_HPDMA1_REQUEST_SPDIFRX_CS    129U     /*!< HPDMA1 HW request is SPDIFRX_CS     */
+#define LL_HPDMA1_REQUEST_SPDIFRX_DT    130U     /*!< HPDMA1 HW request is SPDIFRX_DT     */
+
+#define LL_HPDMA1_REQUEST_ADF1_FLT0     131U     /*!< HPDMA1 HW request is ADF1_FLT0      */
+
+#define LL_HPDMA1_REQUEST_MDF1_FLT0     132U     /*!< HPDMA1 HW request is MDF1_FLT0      */
+#define LL_HPDMA1_REQUEST_MDF1_FLT1     133U     /*!< HPDMA1 HW request is MDF1_FLT1      */
+#define LL_HPDMA1_REQUEST_MDF1_FLT2     134U     /*!< HPDMA1 HW request is MDF1_FLT2      */
+#define LL_HPDMA1_REQUEST_MDF1_FLT3     135U     /*!< HPDMA1 HW request is MDF1_FLT3      */
+#define LL_HPDMA1_REQUEST_MDF1_FLT4     136U     /*!< HPDMA1 HW request is MDF1_FLT4      */
+#define LL_HPDMA1_REQUEST_MDF1_FLT5     137U     /*!< HPDMA1 HW request is MDF1_FLT5      */
+
+#define LL_HPDMA1_REQUEST_UCPD1_TX      138U     /*!< HPDMA1 HW request is UCPD1_TX       */
+#define LL_HPDMA1_REQUEST_UCPD1_RX      139U     /*!< HPDMA1 HW request is UCPD1_RX       */
+
+#define LL_HPDMA1_REQUEST_DCMI_PSSI     140U     /*!< HPDMA1 HW request is DCMI_PSSI      */
+
+#define LL_HPDMA1_REQUEST_I3C1_TC       141U     /*!< HPDMA1 HW request is I3C1_TC        */
+#define LL_HPDMA1_REQUEST_I3C1_RS       142U     /*!< HPDMA1 HW request is I3C1_RS        */
+
+#define LL_HPDMA1_REQUEST_I3C2_TC       143U     /*!< HPDMA1 HW request is I3C2_TC        */
+#define LL_HPDMA1_REQUEST_I3C2_RS       144U     /*!< HPDMA1 HW request is I3C2_RS        */
+
+
+/* GPDMA1 requests */
+#define LL_GPDMA1_REQUEST_JPEG_RX       0U       /*!< GPDMA1 HW request is JPEG_DMA_RX    */
+#define LL_GPDMA1_REQUEST_JPEG_TX       1U       /*!< GPDMA1 HW request is JPEG_DMA_TX    */
+#define LL_GPDMA1_REQUEST_OCTOSPI1      2U       /*!< GPDMA1 HW request is OCTOSPI1       */
+#define LL_GPDMA1_REQUEST_OCTOSPI2      3U       /*!< GPDMA1 HW request is OCTOSPI2       */
+#define LL_GPDMA1_REQUEST_OCTOSPI3      4U       /*!< GPDMA1 HW request is OCTOSPI3       */
+#define LL_GPDMA1_REQUEST_FMC2_TXRX     5U       /*!< GPDMA1 HW request is FMC2_TXRX      */
+#define LL_GPDMA1_REQUEST_FMC2_BCH      6U       /*!< GPDMA1 HW request is FMC2_BCH       */
+#define LL_GPDMA1_REQUEST_ADC1          7U       /*!< GPDMA1 HW request is ADC1           */
+#define LL_GPDMA1_REQUEST_ADC2          8U       /*!< GPDMA1 HW request is ADC2           */
+#define LL_GPDMA1_REQUEST_CRYP_IN       9U       /*!< GPDMA1 HW request is CRYP_IN        */
+#define LL_GPDMA1_REQUEST_CRYP_OUT      10U      /*!< GPDMA1 HW request is CRYP_OUT       */
+#define LL_GPDMA1_REQUEST_SAES_OUT      11U      /*!< GPDMA1 HW request is SAES_OUT       */
+#define LL_GPDMA1_REQUEST_SAES_IN       12U      /*!< GPDMA1 HW request is SAES_IN        */
+#define LL_GPDMA1_REQUEST_HASH_IN       13U      /*!< GPDMA1 HW request is HASH_IN        */
+
+#define LL_GPDMA1_REQUEST_TIM1_CH1      14U      /*!< GPDMA1 HW request is TIM1_CH1       */
+#define LL_GPDMA1_REQUEST_TIM1_CH2      15U      /*!< GPDMA1 HW request is TIM1_CH2       */
+#define LL_GPDMA1_REQUEST_TIM1_CH3      16U      /*!< GPDMA1 HW request is TIM1_CH3       */
+#define LL_GPDMA1_REQUEST_TIM1_CH4      17U      /*!< GPDMA1 HW request is TIM1_CH4       */
+#define LL_GPDMA1_REQUEST_TIM1_UP       18U      /*!< GPDMA1 HW request is TIM1_UP        */
+#define LL_GPDMA1_REQUEST_TIM1_TRIG     19U      /*!< GPDMA1 HW request is TIM1_TRIG      */
+#define LL_GPDMA1_REQUEST_TIM1_COM      20U      /*!< GPDMA1 HW request is TIM1_COM       */
+
+#define LL_GPDMA1_REQUEST_TIM2_CH1      21U      /*!< GPDMA1 HW request is TIM2_CH1       */
+#define LL_GPDMA1_REQUEST_TIM2_CH2      22U      /*!< GPDMA1 HW request is TIM2_CH2       */
+#define LL_GPDMA1_REQUEST_TIM2_CH3      23U      /*!< GPDMA1 HW request is TIM2_CH3       */
+#define LL_GPDMA1_REQUEST_TIM2_CH4      24U      /*!< GPDMA1 HW request is TIM2_CH4       */
+#define LL_GPDMA1_REQUEST_TIM2_UP       25U      /*!< GPDMA1 HW request is TIM2_UP        */
+#define LL_GPDMA1_REQUEST_TIM2_TRIG     26U      /*!< GPDMA1 HW request is TIM2_TRIG      */
+
+#define LL_GPDMA1_REQUEST_TIM3_CH1      27U      /*!< GPDMA1 HW request is TIM3_CH1       */
+#define LL_GPDMA1_REQUEST_TIM3_CH2      28U      /*!< GPDMA1 HW request is TIM3_CH2       */
+#define LL_GPDMA1_REQUEST_TIM3_CH3      29U      /*!< GPDMA1 HW request is TIM3_CH3       */
+#define LL_GPDMA1_REQUEST_TIM3_CH4      30U      /*!< GPDMA1 HW request is TIM3_CH4       */
+#define LL_GPDMA1_REQUEST_TIM3_UP       31U      /*!< GPDMA1 HW request is TIM3_UP        */
+#define LL_GPDMA1_REQUEST_TIM3_TRIG     32U      /*!< GPDMA1 HW request is TIM3_TRIG      */
+
+#define LL_GPDMA1_REQUEST_TIM4_CH1      33U      /*!< GPDMA1 HW request is TIM4_CH1       */
+#define LL_GPDMA1_REQUEST_TIM4_CH2      34U      /*!< GPDMA1 HW request is TIM4_CH2       */
+#define LL_GPDMA1_REQUEST_TIM4_CH3      35U      /*!< GPDMA1 HW request is TIM4_CH3       */
+#define LL_GPDMA1_REQUEST_TIM4_CH4      36U      /*!< GPDMA1 HW request is TIM4_CH4       */
+#define LL_GPDMA1_REQUEST_TIM4_UP       37U      /*!< GPDMA1 HW request is TIM4_UP        */
+#define LL_GPDMA1_REQUEST_TIM4_TRIG     38U      /*!< GPDMA1 HW request is TIM4_TRIG      */
+
+#define LL_GPDMA1_REQUEST_TIM5_CH1      39U      /*!< GPDMA1 HW request is TIM5_CH1       */
+#define LL_GPDMA1_REQUEST_TIM5_CH2      40U      /*!< GPDMA1 HW request is TIM5_CH2       */
+#define LL_GPDMA1_REQUEST_TIM5_CH3      41U      /*!< GPDMA1 HW request is TIM5_CH3       */
+#define LL_GPDMA1_REQUEST_TIM5_CH4      42U      /*!< GPDMA1 HW request is TIM5_CH4       */
+#define LL_GPDMA1_REQUEST_TIM5_UP       43U      /*!< GPDMA1 HW request is TIM5_UP        */
+#define LL_GPDMA1_REQUEST_TIM5_TRIG     44U      /*!< GPDMA1 HW request is TIM5_TRIG      */
+
+#define LL_GPDMA1_REQUEST_TIM6_UP       45U      /*!< GPDMA1 HW request is TIM6_UP        */
+#define LL_GPDMA1_REQUEST_TIM7_UP       46U      /*!< GPDMA1 HW request is TIM6_UP        */
+
+#define LL_GPDMA1_REQUEST_TIM8_CH1      47U      /*!< GPDMA1 HW request is TIM8_CH1       */
+#define LL_GPDMA1_REQUEST_TIM8_CH2      48U      /*!< GPDMA1 HW request is TIM8_CH2       */
+#define LL_GPDMA1_REQUEST_TIM8_CH3      49U      /*!< GPDMA1 HW request is TIM8_CH3       */
+#define LL_GPDMA1_REQUEST_TIM8_CH4      50U      /*!< GPDMA1 HW request is TIM8_CH4       */
+#define LL_GPDMA1_REQUEST_TIM8_UP       51U      /*!< GPDMA1 HW request is TIM8_UP        */
+#define LL_GPDMA1_REQUEST_TIM8_TRIG     52U      /*!< GPDMA1 HW request is TIM8_TRIG      */
+#define LL_GPDMA1_REQUEST_TIM8_COM      53U      /*!< GPDMA1 HW request is TIM8_COM       */
+
+/* reserved                             54U                                               */
+/* reserved                             55U                                               */
+
+#define LL_GPDMA1_REQUEST_TIM15_CH1     56U      /*!< GPDMA1 HW request is TIM15_CH1      */
+#define LL_GPDMA1_REQUEST_TIM15_CH2     57U      /*!< GPDMA1 HW request is TIM15_CH2      */
+#define LL_GPDMA1_REQUEST_TIM15_UP      58U      /*!< GPDMA1 HW request is TIM15_UP       */
+#define LL_GPDMA1_REQUEST_TIM15_TRIG    59U      /*!< GPDMA1 HW request is TIM15_TRIG     */
+#define LL_GPDMA1_REQUEST_TIM15_COM     60U      /*!< GPDMA1 HW request is TIM15_COM      */
+
+#define LL_GPDMA1_REQUEST_TIM16_CH1     61U      /*!< GPDMA1 HW request is TIM16_CH1      */
+#define LL_GPDMA1_REQUEST_TIM16_UP      62U      /*!< GPDMA1 HW request is TIM16_UP       */
+#define LL_GPDMA1_REQUEST_TIM16_COM     63U      /*!< GPDMA1 HW request is TIM16_COM      */
+
+#define LL_GPDMA1_REQUEST_TIM17_CH1     64U      /*!< GPDMA1 HW request is TIM17_CH1      */
+#define LL_GPDMA1_REQUEST_TIM17_UP      65U      /*!< GPDMA1 HW request is TIM17_UP       */
+#define LL_GPDMA1_REQUEST_TIM17_COM     66U      /*!< GPDMA1 HW request is TIM17_COM      */
+
+#define LL_GPDMA1_REQUEST_TIM18_CH1     67U      /*!< GPDMA1 HW request is TIM18_CH1      */
+#define LL_GPDMA1_REQUEST_TIM18_UP      68U      /*!< GPDMA1 HW request is TIM18_UP       */
+#define LL_GPDMA1_REQUEST_TIM18_COM     69U      /*!< GPDMA1 HW request is TIM18_COM      */
+
+#define LL_GPDMA1_REQUEST_LPTIM1_IC1    70U      /*!< GPDMA1 HW request is LPTIM1_IC1     */
+#define LL_GPDMA1_REQUEST_LPTIM1_IC2    71U      /*!< GPDMA1 HW request is LPTIM1_IC2     */
+#define LL_GPDMA1_REQUEST_LPTIM1_UE     72U      /*!< GPDMA1 HW request is LPTIM1_UE      */
+#define LL_GPDMA1_REQUEST_LPTIM2_IC1    73U      /*!< GPDMA1 HW request is LPTIM2_IC1     */
+#define LL_GPDMA1_REQUEST_LPTIM2_IC2    74U      /*!< GPDMA1 HW request is LPTIM2_IC2     */
+#define LL_GPDMA1_REQUEST_LPTIM2_UE     75U      /*!< GPDMA1 HW request is LPTIM2_UE      */
+#define LL_GPDMA1_REQUEST_LPTIM3_IC1    76U      /*!< GPDMA1 HW request is LPTIM3_IC1     */
+#define LL_GPDMA1_REQUEST_LPTIM3_IC2    77U      /*!< GPDMA1 HW request is LPTIM3_IC2     */
+#define LL_GPDMA1_REQUEST_LPTIM3_UE     78U      /*!< GPDMA1 HW request is LPTIM3_UE      */
+
+#define LL_GPDMA1_REQUEST_SPI1_RX       79U      /*!< GPDMA1 HW request is SPI1_RX        */
+#define LL_GPDMA1_REQUEST_SPI1_TX       80U      /*!< GPDMA1 HW request is SPI1_TX        */
+#define LL_GPDMA1_REQUEST_SPI2_RX       81U      /*!< GPDMA1 HW request is SPI2_RX        */
+#define LL_GPDMA1_REQUEST_SPI2_TX       82U      /*!< GPDMA1 HW request is SPI2_TX        */
+#define LL_GPDMA1_REQUEST_SPI3_RX       83U      /*!< GPDMA1 HW request is SPI3_RX        */
+#define LL_GPDMA1_REQUEST_SPI3_TX       84U      /*!< GPDMA1 HW request is SPI3_TX        */
+#define LL_GPDMA1_REQUEST_SPI4_RX       85U      /*!< GPDMA1 HW request is SPI4_RX        */
+#define LL_GPDMA1_REQUEST_SPI4_TX       86U      /*!< GPDMA1 HW request is SPI4_TX        */
+#define LL_GPDMA1_REQUEST_SPI5_RX       87U      /*!< GPDMA1 HW request is SPI5_RX        */
+#define LL_GPDMA1_REQUEST_SPI5_TX       88U      /*!< GPDMA1 HW request is SPI5_TX        */
+#define LL_GPDMA1_REQUEST_SPI6_RX       89U      /*!< GPDMA1 HW request is SPI6_RX        */
+#define LL_GPDMA1_REQUEST_SPI6_TX       90U      /*!< GPDMA1 HW request is SPI6_TX        */
+
+#define LL_GPDMA1_REQUEST_SAI1_A        91U      /*!< GPDMA1 HW request is SAI1_A         */
+#define LL_GPDMA1_REQUEST_SAI1_B        92U      /*!< GPDMA1 HW request is SAI1_B         */
+#define LL_GPDMA1_REQUEST_SAI2_A        93U      /*!< GPDMA1 HW request is SAI2_A         */
+#define LL_GPDMA1_REQUEST_SAI2_B        94U      /*!< GPDMA1 HW request is SAI2_B         */
+
+#define LL_GPDMA1_REQUEST_I2C1_RX       95U      /*!< GPDMA1 HW request is I2C1_RX        */
+#define LL_GPDMA1_REQUEST_I2C1_TX       96U      /*!< GPDMA1 HW request is I2C1_TX        */
+#define LL_GPDMA1_REQUEST_I2C2_RX       97U      /*!< GPDMA1 HW request is I2C2_RX        */
+#define LL_GPDMA1_REQUEST_I2C2_TX       98U      /*!< GPDMA1 HW request is I2C2_TX        */
+#define LL_GPDMA1_REQUEST_I2C3_RX       99U      /*!< GPDMA1 HW request is I2C3_RX        */
+#define LL_GPDMA1_REQUEST_I2C3_TX       100U     /*!< GPDMA1 HW request is I2C3_TX        */
+
+#define LL_GPDMA1_REQUEST_I2C4_RX       101U     /*!< GPDMA1 HW request is I2C4_RX        */
+#define LL_GPDMA1_REQUEST_I2C4_TX       102U     /*!< GPDMA1 HW request is I2C4_TX        */
+
+#define LL_GPDMA1_REQUEST_I3C1_RX       103U     /*!< GPDMA1 HW request is I3C1_RX        */
+#define LL_GPDMA1_REQUEST_I3C1_TX       104U     /*!< GPDMA1 HW request is I3C1_TX        */
+#define LL_GPDMA1_REQUEST_I3C2_RX       105U     /*!< GPDMA1 HW request is I3C2_RX        */
+#define LL_GPDMA1_REQUEST_I3C2_TX       106U     /*!< GPDMA1 HW request is I3C2_TX        */
+
+#define LL_GPDMA1_REQUEST_USART1_RX     107U     /*!< GPDMA1 HW request is USART1_RX      */
+#define LL_GPDMA1_REQUEST_USART1_TX     108U     /*!< GPDMA1 HW request is USART1_TX      */
+#define LL_GPDMA1_REQUEST_USART2_RX     109U     /*!< GPDMA1 HW request is USART2_RX      */
+#define LL_GPDMA1_REQUEST_USART2_TX     110U     /*!< GPDMA1 HW request is USART2_TX      */
+#define LL_GPDMA1_REQUEST_USART3_RX     111U     /*!< GPDMA1 HW request is USART3_RX      */
+#define LL_GPDMA1_REQUEST_USART3_TX     112U     /*!< GPDMA1 HW request is USART3_TX      */
+#define LL_GPDMA1_REQUEST_UART4_RX      113U     /*!< GPDMA1 HW request is UART4_RX       */
+#define LL_GPDMA1_REQUEST_UART4_TX      114U     /*!< GPDMA1 HW request is UART4_TX       */
+#define LL_GPDMA1_REQUEST_UART5_RX      115U     /*!< GPDMA1 HW request is UART5_RX       */
+#define LL_GPDMA1_REQUEST_UART5_TX      116U     /*!< GPDMA1 HW request is UART5_TX       */
+#define LL_GPDMA1_REQUEST_USART6_RX     117U     /*!< GPDMA1 HW request is USART6_RX      */
+#define LL_GPDMA1_REQUEST_USART6_TX     118U     /*!< GPDMA1 HW request is USART6_TX      */
+#define LL_GPDMA1_REQUEST_UART7_RX      119U     /*!< GPDMA1 HW request is UART7_RX       */
+#define LL_GPDMA1_REQUEST_UART7_TX      120U     /*!< GPDMA1 HW request is UART7_TX       */
+#define LL_GPDMA1_REQUEST_UART8_RX      121U     /*!< GPDMA1 HW request is UART8_RX       */
+#define LL_GPDMA1_REQUEST_UART8_TX      122U     /*!< GPDMA1 HW request is UART8_TX       */
+#define LL_GPDMA1_REQUEST_UART9_RX      123U     /*!< GPDMA1 HW request is UART9_RX       */
+#define LL_GPDMA1_REQUEST_UART9_TX      124U     /*!< GPDMA1 HW request is UART9_TX       */
+#define LL_GPDMA1_REQUEST_USART10_RX    125U     /*!< GPDMA1 HW request is USART10_RX     */
+#define LL_GPDMA1_REQUEST_USART10_TX    126U     /*!< GPDMA1 HW request is USART10_TX     */
+
+#define LL_GPDMA1_REQUEST_LPUART1_RX    127U     /*!< GPDMA1 HW request is LPUART1_RX     */
+#define LL_GPDMA1_REQUEST_LPUART1_TX    128U     /*!< GPDMA1 HW request is LPUART1_TX     */
+
+#define LL_GPDMA1_REQUEST_SPDIFRX_CS    129U     /*!< GPDMA1 HW request is SPDIFRX_CS     */
+#define LL_GPDMA1_REQUEST_SPDIFRX_DT    130U     /*!< GPDMA1 HW request is SPDIFRX_DT     */
+
+#define LL_GPDMA1_REQUEST_ADF1_FLT0     131U     /*!< GPDMA1 HW request is ADF1_FLT0      */
+
+#define LL_GPDMA1_REQUEST_MDF1_FLT0     132U     /*!< GPDMA1 HW request is MDF1_FLT0      */
+#define LL_GPDMA1_REQUEST_MDF1_FLT1     133U     /*!< GPDMA1 HW request is MDF1_FLT1      */
+#define LL_GPDMA1_REQUEST_MDF1_FLT2     134U     /*!< GPDMA1 HW request is MDF1_FLT2      */
+#define LL_GPDMA1_REQUEST_MDF1_FLT3     135U     /*!< GPDMA1 HW request is MDF1_FLT3      */
+#define LL_GPDMA1_REQUEST_MDF1_FLT4     136U     /*!< GPDMA1 HW request is MDF1_FLT4      */
+#define LL_GPDMA1_REQUEST_MDF1_FLT5     137U     /*!< GPDMA1 HW request is MDF1_FLT5      */
+
+#define LL_GPDMA1_REQUEST_UCPD1_TX      138U     /*!< GPDMA1 HW request is UCPD1_TX       */
+#define LL_GPDMA1_REQUEST_UCPD1_RX      139U     /*!< GPDMA1 HW request is UCPD1_RX       */
+
+#define LL_GPDMA1_REQUEST_DCMI_PSSI     140U     /*!< GPDMA1 HW request is DCMI_PSSI      */
+
+#define LL_GPDMA1_REQUEST_I3C1_TC       141U     /*!< GPDMA1 HW request is I3C1_TC        */
+#define LL_GPDMA1_REQUEST_I3C1_RS       142U     /*!< GPDMA1 HW request is I3C1_RS        */
+
+#define LL_GPDMA1_REQUEST_I3C2_TC       143U     /*!< GPDMA1 HW request is I3C2_TC        */
+#define LL_GPDMA1_REQUEST_I3C2_RS       144U     /*!< GPDMA1 HW request is I3C2_RS        */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
+  * @{
+  */
+/* HPDMA1 triggers */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND           0U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_FEND           */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND           1U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_LEND           */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC          2U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC          */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC          3U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC          */
+
+#define LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND           4U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_FEND           */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND           5U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_LEND           */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC          6U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC          */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC          7U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC          */
+
+#define LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND           8U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_FEND           */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND           9U   /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_LEND           */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC          10U  /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC          */
+#define LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC          11U  /*!< HPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC          */
+
+#define LL_HPDMA1_TRIGGER_DMA2D_CTC                12U  /*!< HPDMA1 HW Trigger signal is DMA2D_CTC                */
+#define LL_HPDMA1_TRIGGER_DMA2D_TC                 13U  /*!< HPDMA1 HW Trigger signal is DMA2D_TC                 */
+#define LL_HPDMA1_TRIGGER_DMA2D_TW                 14U  /*!< HPDMA1 HW Trigger signal is DMA2D_TW                 */
+
+#define LL_HPDMA1_TRIGGER_JPEG_EOC                 15U  /*!< HPDMA1 HW Trigger signal is JPEG_EOC                 */
+#define LL_HPDMA1_TRIGGER_JPEG_IFNF                16U  /*!< HPDMA1 HW Trigger signal is JPEG_IFNF                */
+#define LL_HPDMA1_TRIGGER_JPEG_IFT                 17U  /*!< HPDMA1 HW Trigger signal is JPEG_IFT                 */
+#define LL_HPDMA1_TRIGGER_JPEG_OFNE                18U  /*!< HPDMA1 HW Trigger signal is JPEG_OFNE                */
+#define LL_HPDMA1_TRIGGER_JPEG_OFT                 19U  /*!< HPDMA1 HW Trigger signal is JPEG_OFT                 */
+
+#define LL_HPDMA1_TRIGGER_LCD_LI                   20U  /*!< HPDMA1 HW Trigger signal is LCD_LI                   */
+
+#define LL_HPDMA1_TRIGGER_GPU2D1_GP_0              21U  /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_0              */
+#define LL_HPDMA1_TRIGGER_GPU2D1_GP_1              22U  /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_1              */
+#define LL_HPDMA1_TRIGGER_GPU2D1_GP_2              23U  /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_2              */
+#define LL_HPDMA1_TRIGGER_GPU2D1_GP_3              24U  /*!< HPDMA1 HW Trigger signal is GPU2D1_GP_3              */
+
+#define LL_HPDMA1_TRIGGER_GFXTIM_3                 25U  /*!< HPDMA1 HW Trigger signal is GFXTIM_3                 */
+#define LL_HPDMA1_TRIGGER_GFXTIM_2                 26U  /*!< HPDMA1 HW Trigger signal is GFXTIM_2                 */
+#define LL_HPDMA1_TRIGGER_GFXTIM_1                 27U  /*!< HPDMA1 HW Trigger signal is GFXTIM_1                 */
+#define LL_HPDMA1_TRIGGER_GFXTIM_0                 28U  /*!< HPDMA1 HW Trigger signal is GFXTIM_0                 */
+
+/* reserved                                        29U                                                            */
+
+#define LL_HPDMA1_TRIGGER_LPTIM1_CH1               30U  /*!< HPDMA1 HW Trigger signal is LPTIM1_CH1               */
+#define LL_HPDMA1_TRIGGER_LPTIM1_CH2               31U  /*!< HPDMA1 HW Trigger signal is LPTIM1_CH2               */
+#define LL_HPDMA1_TRIGGER_LPTIM2_CH1               32U  /*!< HPDMA1 HW Trigger signal is LPTIM2_CH1               */
+#define LL_HPDMA1_TRIGGER_LPTIM2_CH2               33U  /*!< HPDMA1 HW Trigger signal is LPTIM2_CH2               */
+#define LL_HPDMA1_TRIGGER_LPTIM3_CH1               34U  /*!< HPDMA1 HW Trigger signal is LPTIM3_CH1               */
+#define LL_HPDMA1_TRIGGER_LPTIM3_CH2               35U  /*!< HPDMA1 HW Trigger signal is LPTIM3_CH2               */
+#define LL_HPDMA1_TRIGGER_LPTIM4_OUT               36U  /*!< HPDMA1 HW Trigger signal is LPTIM4_OUT               */
+#define LL_HPDMA1_TRIGGER_LPTIM5_OUT               37U  /*!< HPDMA1 HW Trigger signal is LPTIM5_OUT               */
+
+/* reserved                                        38U                                                            */
+
+#define LL_HPDMA1_TRIGGER_RTC_WKUP                 39U  /*!< HPDMA1 HW Trigger signal is RTC_WKUP                 */
+
+#define LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC   40U  /*!< HPDMA1 HW Trigger signal is IT_R_WUP_ASYNC           */
+#define LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC   41U  /*!< HPDMA1 HW Trigger signal is IT_T_WUP_ASYNC           */
+
+#define LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U  /*!< HPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */
+
+/* reserved                                        43U                                                            */
+
+#define LL_HPDMA1_TRIGGER_TIM1_TRGO                44U  /*!< HPDMA1 HW Trigger signal is TIM1_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM1_TRGO2               45U  /*!< HPDMA1 HW Trigger signal is TIM1_TRGO2               */
+#define LL_HPDMA1_TRIGGER_TIM2_TRGO                46U  /*!< HPDMA1 HW Trigger signal is TIM2_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM3_TRGO                47U  /*!< HPDMA1 HW Trigger signal is TIM3_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM4_TRGO                48U  /*!< HPDMA1 HW Trigger signal is TIM4_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM5_TRGO                49U  /*!< HPDMA1 HW Trigger signal is TIM5_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM6_TRGO                50U  /*!< HPDMA1 HW Trigger signal is TIM6_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM7_TRGO                51U  /*!< HPDMA1 HW Trigger signal is TIM7_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM8_TRGO                52U  /*!< HPDMA1 HW Trigger signal is TIM8_TRGO                */
+#define LL_HPDMA1_TRIGGER_TIM8_TRGO2               53U  /*!< HPDMA1 HW Trigger signal is TIM8_TRGO2               */
+
+/* reserved                                        54U                                                            */
+/* reserved                                        55U                                                            */
+/* reserved                                        56U                                                            */
+
+#define LL_HPDMA1_TRIGGER_TIM12_TRGO               57U  /*!< HPDMA1 HW Trigger signal is TIM12_TRGO               */
+#define LL_HPDMA1_TRIGGER_TIM15_TRGO               58U  /*!< HPDMA1 HW Trigger signal is TIM15_TRGO               */
+
+/* reserved                                        59U                                                            */
+
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF           60U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH0_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF           61U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH1_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF           62U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH2_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF           63U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH3_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF           64U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH4_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF           65U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH5_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF           66U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH6_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF           67U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH7_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF           68U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH8_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF           69U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH9_TCF           */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF          70U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH10_TCF          */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF          71U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH11_TCF          */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF          72U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH12_TCF          */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF          73U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH13_TCF          */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF          74U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH14_TCF          */
+#define LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF          75U  /*!< HPDMA1 HW Trigger signal is HPDMA1_CH15_TCF          */
+
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF           76U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH0_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF           77U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH1_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF           78U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH2_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF           79U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH3_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF           80U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH4_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF           81U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH5_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF           82U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH6_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF           83U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH7_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF           84U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH8_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF           85U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH9_TCF           */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF          86U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH10_TCF          */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF          87U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH11_TCF          */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF          88U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH12_TCF          */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF          89U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH13_TCF          */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF          90U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH14_TCF          */
+#define LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF          91U  /*!< HPDMA1 HW Trigger signal is GPDMA1_CH15_TCF          */
+
+/* reserved                                        92U                                                            */
+
+#define LL_HPDMA1_TRIGGER_EXTIT0_SYNC              93U  /*!< HPDMA1 HW Trigger signal is EXTIT0_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT1_SYNC              94U  /*!< HPDMA1 HW Trigger signal is EXTIT1_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT2_SYNC              95U  /*!< HPDMA1 HW Trigger signal is EXTIT2_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT3_SYNC              96U  /*!< HPDMA1 HW Trigger signal is EXTIT3_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT4_SYNC              97U  /*!< HPDMA1 HW Trigger signal is EXTIT4_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT5_SYNC              98U  /*!< HPDMA1 HW Trigger signal is EXTIT5_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT6_SYNC              99U  /*!< HPDMA1 HW Trigger signal is EXTIT6_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT7_SYNC              100U /*!< HPDMA1 HW Trigger signal is EXTIT7_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT8_SYNC              101U /*!< HPDMA1 HW Trigger signal is EXTIT8_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT9_SYNC              102U /*!< HPDMA1 HW Trigger signal is EXTIT9_SYNC              */
+#define LL_HPDMA1_TRIGGER_EXTIT10_SYNC             103U /*!< HPDMA1 HW Trigger signal is EXTIT10_SYNC             */
+#define LL_HPDMA1_TRIGGER_EXTIT11_SYNC             104U /*!< HPDMA1 HW Trigger signal is EXTIT11_SYNC             */
+#define LL_HPDMA1_TRIGGER_EXTIT12_SYNC             105U /*!< HPDMA1 HW Trigger signal is EXTIT12_SYNC             */
+#define LL_HPDMA1_TRIGGER_EXTIT13_SYNC             106U /*!< HPDMA1 HW Trigger signal is EXTIT13_SYNC             */
+#define LL_HPDMA1_TRIGGER_EXTIT14_SYNC             107U /*!< HPDMA1 HW Trigger signal is EXTIT14_SYNC             */
+#define LL_HPDMA1_TRIGGER_EXTIT15_SYNC             108U /*!< HPDMA1 HW Trigger signal is EXTIT15_SYNC             */
+
+
+/* GPDMA1 triggers */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND           0U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_FEND           */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND           1U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_LEND           */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC          2U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_HSYNC          */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC          3U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P0_VSYNC          */
+
+#define LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND           4U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_FEND           */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND           5U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_LEND           */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC          6U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_HSYNC          */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC          7U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P1_VSYNC          */
+
+#define LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND           8U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_FEND           */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND           9U   /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_LEND           */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC          10U  /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_HSYNC          */
+#define LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC          11U  /*!< GPDMA1 HW Trigger signal is DCMIPP_P2_VSYNC          */
+
+#define LL_GPDMA1_TRIGGER_DMA2D_CTC                12U  /*!< GPDMA1 HW Trigger signal is DMA2D_CTC                */
+#define LL_GPDMA1_TRIGGER_DMA2D_TC                 13U  /*!< GPDMA1 HW Trigger signal is DMA2D_TC                 */
+#define LL_GPDMA1_TRIGGER_DMA2D_TW                 14U  /*!< GPDMA1 HW Trigger signal is DMA2D_TW                 */
+
+#define LL_GPDMA1_TRIGGER_JPEG_EOC                 15U  /*!< GPDMA1 HW Trigger signal is JPEG_EOC                 */
+#define LL_GPDMA1_TRIGGER_JPEG_IFNF                16U  /*!< GPDMA1 HW Trigger signal is JPEG_IFNF                */
+#define LL_GPDMA1_TRIGGER_JPEG_IFT                 17U  /*!< GPDMA1 HW Trigger signal is JPEG_IFT                 */
+#define LL_GPDMA1_TRIGGER_JPEG_OFNE                18U  /*!< GPDMA1 HW Trigger signal is JPEG_OFNE                */
+#define LL_GPDMA1_TRIGGER_JPEG_OFT                 19U  /*!< GPDMA1 HW Trigger signal is JPEG_OFT                 */
+
+#define LL_GPDMA1_TRIGGER_LCD_LI                   20U  /*!< GPDMA1 HW Trigger signal is LCD_LI                   */
+
+#define LL_GPDMA1_TRIGGER_GPU2D1_GP_0              21U  /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_0              */
+#define LL_GPDMA1_TRIGGER_GPU2D1_GP_1              22U  /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_1              */
+#define LL_GPDMA1_TRIGGER_GPU2D1_GP_2              23U  /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_2              */
+#define LL_GPDMA1_TRIGGER_GPU2D1_GP_3              24U  /*!< GPDMA1 HW Trigger signal is GPU2D1_GP_3              */
+
+#define LL_GPDMA1_TRIGGER_GFXTIM_3                 25U  /*!< GPDMA1 HW Trigger signal is GFXTIM_3                 */
+#define LL_GPDMA1_TRIGGER_GFXTIM_2                 26U  /*!< GPDMA1 HW Trigger signal is GFXTIM_2                 */
+#define LL_GPDMA1_TRIGGER_GFXTIM_1                 27U  /*!< GPDMA1 HW Trigger signal is GFXTIM_1                 */
+#define LL_GPDMA1_TRIGGER_GFXTIM_0                 28U  /*!< GPDMA1 HW Trigger signal is GFXTIM_0                 */
+
+/* reserved                                        29U                                                            */
+
+#define LL_GPDMA1_TRIGGER_LPTIM1_CH1               30U  /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1               */
+#define LL_GPDMA1_TRIGGER_LPTIM1_CH2               31U  /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2               */
+#define LL_GPDMA1_TRIGGER_LPTIM2_CH1               32U  /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1               */
+#define LL_GPDMA1_TRIGGER_LPTIM2_CH2               33U  /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2               */
+#define LL_GPDMA1_TRIGGER_LPTIM3_CH1               34U  /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1               */
+#define LL_GPDMA1_TRIGGER_LPTIM3_CH2               35U  /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2               */
+#define LL_GPDMA1_TRIGGER_LPTIM4_OUT               36U  /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT               */
+#define LL_GPDMA1_TRIGGER_LPTIM5_OUT               37U  /*!< GPDMA1 HW Trigger signal is LPTIM5_OUT               */
+
+/* reserved                                        38U                                                            */
+
+#define LL_GPDMA1_TRIGGER_RTC_WKUP                 39U  /*!< GPDMA1 HW Trigger signal is RTC_WKUP                 */
+
+#define LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC   40U  /*!< GPDMA1 HW Trigger signal is IT_R_WUP_ASYNC           */
+#define LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC   41U  /*!< GPDMA1 HW Trigger signal is IT_T_WUP_ASYNC           */
+
+#define LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC 42U  /*!< GPDMA1 HW Trigger signal is SPI6_IT_OR_SPI6_AIT_SYNC */
+
+/* reserved                                        43U                                                            */
+
+#define LL_GPDMA1_TRIGGER_TIM1_TRGO                44U  /*!< GPDMA1 HW Trigger signal is TIM1_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM1_TRGO2               45U  /*!< GPDMA1 HW Trigger signal is TIM1_TRGO2               */
+#define LL_GPDMA1_TRIGGER_TIM2_TRGO                46U  /*!< GPDMA1 HW Trigger signal is TIM2_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM3_TRGO                47U  /*!< GPDMA1 HW Trigger signal is TIM3_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM4_TRGO                48U  /*!< GPDMA1 HW Trigger signal is TIM4_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM5_TRGO                49U  /*!< GPDMA1 HW Trigger signal is TIM5_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM6_TRGO                50U  /*!< GPDMA1 HW Trigger signal is TIM6_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM7_TRGO                51U  /*!< GPDMA1 HW Trigger signal is TIM7_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM8_TRGO                52U  /*!< GPDMA1 HW Trigger signal is TIM8_TRGO                */
+#define LL_GPDMA1_TRIGGER_TIM8_TRGO2               53U  /*!< GPDMA1 HW Trigger signal is TIM8_TRGO2               */
+
+/* reserved                                        54U                                                            */
+/* reserved                                        55U                                                            */
+/* reserved                                        56U                                                            */
+
+#define LL_GPDMA1_TRIGGER_TIM12_TRGO               57U  /*!< GPDMA1 HW Trigger signal is TIM12_TRGO               */
+#define LL_GPDMA1_TRIGGER_TIM15_TRGO               58U  /*!< GPDMA1 HW Trigger signal is TIM15_TRGO               */
+
+/* reserved                                        59U                                                            */
+
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF           60U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH0_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF           61U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH1_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF           62U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH2_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF           63U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH3_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF           64U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH4_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF           65U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH5_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF           66U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH6_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF           67U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH7_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF           68U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH8_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF           69U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH9_TCF           */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF          70U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH10_TCF          */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF          71U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH11_TCF          */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF          72U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH12_TCF          */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF          73U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH13_TCF          */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF          74U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH14_TCF          */
+#define LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF          75U  /*!< GPDMA1 HW Trigger signal is HPDMA1_CH15_TCF          */
+
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF           76U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF           77U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF           78U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF           79U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF           80U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF           81U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF           82U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF           83U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF           84U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF           85U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF           */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF          86U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF          */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF          87U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF          */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF          88U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF          */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF          89U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF          */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF          90U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF          */
+#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF          91U  /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF          */
+
+/* reserved                                        92U                                                            */
+
+#define LL_GPDMA1_TRIGGER_EXTIT0_SYNC              93U  /*!< GPDMA1 HW Trigger signal is EXTIT0_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT1_SYNC              94U  /*!< GPDMA1 HW Trigger signal is EXTIT1_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT2_SYNC              95U  /*!< GPDMA1 HW Trigger signal is EXTIT2_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT3_SYNC              96U  /*!< GPDMA1 HW Trigger signal is EXTIT3_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT4_SYNC              97U  /*!< GPDMA1 HW Trigger signal is EXTIT4_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT5_SYNC              98U  /*!< GPDMA1 HW Trigger signal is EXTIT5_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT6_SYNC              99U  /*!< GPDMA1 HW Trigger signal is EXTIT6_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT7_SYNC              100U /*!< GPDMA1 HW Trigger signal is EXTIT7_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT8_SYNC              101U /*!< GPDMA1 HW Trigger signal is EXTIT8_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT9_SYNC              102U /*!< GPDMA1 HW Trigger signal is EXTIT9_SYNC              */
+#define LL_GPDMA1_TRIGGER_EXTIT10_SYNC             103U /*!< GPDMA1 HW Trigger signal is EXTIT10_SYNC             */
+#define LL_GPDMA1_TRIGGER_EXTIT11_SYNC             104U /*!< GPDMA1 HW Trigger signal is EXTIT11_SYNC             */
+#define LL_GPDMA1_TRIGGER_EXTIT12_SYNC             105U /*!< GPDMA1 HW Trigger signal is EXTIT12_SYNC             */
+#define LL_GPDMA1_TRIGGER_EXTIT13_SYNC             106U /*!< GPDMA1 HW Trigger signal is EXTIT13_SYNC             */
+#define LL_GPDMA1_TRIGGER_EXTIT14_SYNC             107U /*!< GPDMA1 HW Trigger signal is EXTIT14_SYNC             */
+#define LL_GPDMA1_TRIGGER_EXTIT15_SYNC             108U /*!< GPDMA1 HW Trigger signal is EXTIT15_SYNC             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register.
+  * @param  __INSTANCE__ DMA Instance.
+  * @param  __REG__      Register to be written.
+  * @param  __VALUE__    Value to be written in the register.
+  * @retval None.
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register.
+  * @param  __INSTANCE__ DMA Instance.
+  * @param  __REG__      Register to be read.
+  * @retval Register value.
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Channely into DMAx.
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely.
+  * @retval DMAx.
+  */
+#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+  (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ?  HPDMA1 : GPDMA1)
+
+/**
+  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y.
+  * @param  __CHANNEL_INSTANCE__ DMAx_Channely.
+  * @retval LL_DMA_CHANNEL_y.
+  */
+#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+  (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel0))  ? LL_DMA_CHANNEL_0  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0))  ? LL_DMA_CHANNEL_0  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel1))  ? LL_DMA_CHANNEL_1  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1))  ? LL_DMA_CHANNEL_1  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel2))  ? LL_DMA_CHANNEL_2  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2))  ? LL_DMA_CHANNEL_2  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel3))  ? LL_DMA_CHANNEL_3  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3))  ? LL_DMA_CHANNEL_3  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel4))  ? LL_DMA_CHANNEL_4  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4))  ? LL_DMA_CHANNEL_4  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel5))  ? LL_DMA_CHANNEL_5  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5))  ? LL_DMA_CHANNEL_5  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel6))  ? LL_DMA_CHANNEL_6  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6))  ? LL_DMA_CHANNEL_6  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel7))  ? LL_DMA_CHANNEL_7  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7))  ? LL_DMA_CHANNEL_7  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel8))  ? LL_DMA_CHANNEL_8  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8))  ? LL_DMA_CHANNEL_8  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel9))  ? LL_DMA_CHANNEL_9  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9))  ? LL_DMA_CHANNEL_9  : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)HPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
+   ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
+   LL_DMA_CHANNEL_15)
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
+  * @param  __DMA_INSTANCE__ DMAx.
+  * @param  __CHANNEL__      LL_DMA_CHANNEL_y.
+  * @retval DMAx_Channely.
+  */
+#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+  ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
+   ? HPDMA1_Channel0  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
+   ? GPDMA1_Channel0  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+   ? HPDMA1_Channel1  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
+   ? GPDMA1_Channel1  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+   ? HPDMA1_Channel2  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
+   ? GPDMA1_Channel2  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+   ? HPDMA1_Channel3  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
+   ? GPDMA1_Channel3  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
+   ? HPDMA1_Channel4  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
+   ? GPDMA1_Channel4  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
+   ? HPDMA1_Channel5  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
+   ? GPDMA1_Channel5  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
+   ? HPDMA1_Channel6  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
+   ? GPDMA1_Channel6  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
+   ? HPDMA1_Channel7  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
+   ? GPDMA1_Channel7  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
+   ? HPDMA1_Channel8  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
+   ? GPDMA1_Channel8  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
+   ? HPDMA1_Channel9  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
+   ? GPDMA1_Channel9  :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
+   ? HPDMA1_Channel10 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
+   ? GPDMA1_Channel10 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
+   ? HPDMA1_Channel11 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
+   ? GPDMA1_Channel11 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
+   ? HPDMA1_Channel12 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
+   ? GPDMA1_Channel12 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
+   ? HPDMA1_Channel13 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
+   ? GPDMA1_Channel13 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
+   ? HPDMA1_Channel14 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
+   ? GPDMA1_Channel14 :                                                                                                \
+   (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)HPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_15)))\
+   ? HPDMA1_Channel15 :  GPDMA1_Channel15)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief Enable channel.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          EN            LL_DMA_EnableChannel
+  * @param  DMAx DMAx Instance.
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
+}
+
+/**
+  * @brief Disable channel.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          EN            LL_DMA_DisableChannel
+  * @param  DMAx DMAx Instance.
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
+          (DMA_CCR_SUSP | DMA_CCR_RESET));
+}
+
+/**
+  * @brief Check if channel is enabled or disabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
+           == (DMA_CCR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Reset channel.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          RESET            LL_DMA_ResetChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
+}
+
+/**
+  * @brief Suspend channel.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          SUSP            LL_DMA_SuspendChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
+}
+
+/**
+  * @brief Resume channel.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          SUSP            LL_DMA_ResumeChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
+}
+
+/**
+  * @brief Check if channel is suspended.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          SUSP            LL_DMA_IsSuspendedChannel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
+           == (DMA_CCR_SUSP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Set linked-list base address.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLBAR          LBA           LL_DMA_SetLinkedListBaseAddr
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
+  *         are always 0)
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel,
+                                                  uint32_t LinkedListBaseAddr)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
+             (LinkedListBaseAddr & DMA_CLBAR_LBA));
+}
+
+/**
+  * @brief Get linked-list base address.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLBAR          LBA           LL_DMA_GetLinkedListBaseAddr
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
+}
+
+/**
+  * @brief Configure all parameters linked to channel control.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR         PRIO           LL_DMA_ConfigControl\n
+  *         CCR         LAP            LL_DMA_ConfigControl\n
+  *         CCR         LSM            LL_DMA_ConfigControl
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT  or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
+  *              @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
+  *         @arg @ref LL_DMA_LINK_ALLOCATED_PORT0     or @ref LL_DMA_LINK_ALLOCATED_PORT1
+  *         @arg @ref LL_DMA_LSM_FULL_EXECUTION       or @ref LL_DMA_LSM_1LINK_EXECUTION
+  *@retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
+             (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
+}
+
+/**
+  * @brief Set priority level.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          PRIO           LL_DMA_SetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
+  *         @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
+  *         @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
+  *         @arg @ref LL_DMA_HIGH_PRIORITY
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t  Priority)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
+}
+
+/**
+  * @brief Get Channel priority level.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          PRIO           LL_DMA_GetChannelPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
+  *         @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
+  *         @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
+  *         @arg @ref LL_DMA_HIGH_PRIORITY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
+}
+
+/**
+  * @brief Set linked-list allocated port.
+  * @rmtoll CCR          LAP           LL_DMA_SetLinkAllocatedPort
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  LinkAllocatedPort This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
+  *         @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t  LinkAllocatedPort)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
+             DMA_CCR_LAP, LinkAllocatedPort);
+}
+
+/**
+  * @brief Get linked-list allocated port.
+  * @rmtoll CCR          LAP           LL_DMA_GetLinkAllocatedPort
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
+  *         @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
+}
+
+/**
+  * @brief Set link step mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          LSM           LL_DMA_SetLinkStepMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+    *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  LinkStepMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_LSM_FULL_EXECUTION
+  *         @arg @ref LL_DMA_LSM_1LINK_EXECUTION
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
+}
+
+/**
+  * @brief Get Link step mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR          LSM           LL_DMA_GetLinkStepMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_LSM_FULL_EXECUTION
+  *         @arg @ref LL_DMA_LSM_1LINK_EXECUTION
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
+}
+
+/**
+  * @brief Configure data transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          DAP           LL_DMA_ConfigTransfer\n
+  *         CTR1          DWX           LL_DMA_ConfigTransfer\n
+  *         CTR1          DHX           LL_DMA_ConfigTransfer\n
+  *         CTR1          DBX           LL_DMA_ConfigTransfer\n
+  *         CTR1          DINC          LL_DMA_ConfigTransfer\n
+  *         CTR1          SAP           LL_DMA_ConfigTransfer\n
+  *         CTR1          SBX           LL_DMA_ConfigTransfer\n
+  *         CTR1          PAM           LL_DMA_ConfigTransfer\n
+  *         CTR1          SINC          LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DEST_ALLOCATED_PORT0     or @ref LL_DMA_DEST_ALLOCATED_PORT1
+  *         @arg @ref LL_DMA_DEST_WORD_PRESERVE       or @ref LL_DMA_DEST_WORD_EXCHANGE
+  *         @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE   or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
+  *         @arg @ref LL_DMA_DEST_BYTE_PRESERVE       or @ref LL_DMA_DEST_BYTE_EXCHANGE
+  *         @arg @ref LL_DMA_SRC_BYTE_PRESERVE        or @ref LL_DMA_SRC_BYTE_EXCHANGE
+  *         @arg @ref LL_DMA_DEST_FIXED               or @ref LL_DMA_DEST_INCREMENT
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE      or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
+  *              @ref LL_DMA_DEST_DATAWIDTH_WORD      or @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
+  *         @arg @ref LL_DMA_SRC_ALLOCATED_PORT0      or @ref LL_DMA_SRC_ALLOCATED_PORT1
+  *         @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD      or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD  or
+  *              @ref LL_DMA_DATA_PACK_UNPACK
+  *         @arg @ref LL_DMA_SRC_FIXED                or @ref LL_DMA_SRC_INCREMENT
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE       or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD  or
+  *              @ref LL_DMA_SRC_DATAWIDTH_WORD       or @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
+  *@retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+             DMA_CTR1_DAP | DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | \
+             DMA_CTR1_SINC | DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
+}
+
+/**
+  * @brief Configure source and destination burst length.
+  * @rmtoll CTR1          DBL_1           LL_DMA_SetDestBurstLength\n
+  * @rmtoll CTR1          SBL_1           LL_DMA_SetDestBurstLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcBurstLength Between 1 to 64
+  * @param  DestBurstLength Between 1 to 64
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
+                                              uint32_t DestBurstLength)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+             (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
+             (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
+}
+
+#if defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief Set the static isolation attribute (CID) of the DMA channel.
+  * @note  This API is used for HPDMA channels.
+  * @rmtoll CCIDCFGR      SCID           LL_DMA_SetStaticIsolation\n
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Cid This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_0
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_1
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_2
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_3
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_4
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_5
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_6
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetStaticIsolation(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Cid)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR,
+             DMA_CCIDCFGR_SCID, Cid);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief Get the static isolation attribute (CID) of the DMA channel.
+  * @note  This API is used for HPDMA channels.
+  * @rmtoll CCIDCFGR      SCID           LL_DMA_GetStaticIsolation\n
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_0
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_1
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_2
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_3
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_4
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_5
+  *         @arg @ref LL_DMA_CHANNEL_STATIC_CID_6
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetStaticIsolation(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR,
+                   DMA_CCIDCFGR_SCID));
+}
+
+/**
+  * @brief Enable the isolation (CID filtering) of the DMA channel.
+  * @note  This API is used for HPDMA channels.
+  * @rmtoll CCIDCFGR          CFEN       LL_DMA_EnableIsolation
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIsolation(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, DMA_CCIDCFGR_CFEN);
+}
+
+/**
+  * @brief Disable the isolation (CID filtering) of the DMA channel.
+  * @note  This API is used for HPDMA channels.
+  * @rmtoll CCIDCFGR          CFEN       LL_DMA_DisableIsolation
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIsolation(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR, DMA_CCIDCFGR_CFEN);
+}
+
+/**
+  * @brief Check isolation (CID filtering) of the DMA channel.
+  * @note  This API is used for HPDMA channels.
+  * @rmtoll CCIDCFGR       CFEN           LL_DMA_IsEnabledIsolation
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIsolation(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCIDCFGR,
+                    DMA_CCIDCFGR_CFEN) == (DMA_CCIDCFGR_CFEN)) ? 1UL : 0UL);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief Configure all secure parameters linked to DMA channel.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll SECCFGR       SEC            LL_DMA_ConfigChannelSecure\n
+  * @rmtoll CTR1          SSEC           LL_DMA_ConfigChannelSecure\n
+  * @rmtoll CTR1          DSEC           LL_DMA_ConfigChannelSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_CHANNEL_NSEC      or @ref LL_DMA_CHANNEL_SEC
+  *         @arg @ref LL_DMA_CHANNEL_SRC_NSEC  or @ref LL_DMA_CHANNEL_SRC_SEC
+  *         @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+             (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
+}
+
+/**
+  * @brief Enable security attribute of the DMA transfer to the destination.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          DSEC           LL_DMA_EnableChannelDestSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
+}
+
+/**
+  * @brief Disable security attribute of the DMA transfer to the destination.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          DSEC           LL_DMA_DisableChannelDestSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief Check security attribute of the DMA transfer to the destination.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          DSEC           LL_DMA_IsEnabledChannelDestSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
+           == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief Enable security attribute of the DMA transfer from the source.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          SSEC           LL_DMA_EnableChannelSrcSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
+}
+
+/**
+  * @brief Disable security attribute of the DMA transfer from the source.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          SSEC           LL_DMA_DisableChannelSrcSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief Check security attribute of the DMA transfer from the source.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          SSEC           LL_DMA_IsEnabledChannelSrcSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
+           == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Set destination allocated port.
+  * @rmtoll CTR1          DAP           LL_DMA_SetDestAllocatedPort
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestAllocatedPort This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
+  *         @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
+             DestAllocatedPort);
+}
+
+/**
+  * @brief Get destination allocated port.
+  * @rmtoll CTR1          DAP           LL_DMA_GetDestAllocatedPort
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
+  *         @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
+}
+
+/**
+  * @brief Set destination word exchange.
+  * @rmtoll CTR1          DWX            LL_DMA_SetDestWordExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestWordExchange This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_WORD_PRESERVE
+  *         @arg @ref LL_DMA_DEST_WORD_EXCHANGE
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestWordExchange)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX,
+             DestWordExchange);
+}
+
+/**
+  * @brief Get destination word exchange.
+  * @rmtoll CTR1          DWX            LL_DMA_GetDestWordExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_WORD_PRESERVE
+  *         @arg @ref LL_DMA_DEST_WORD_EXCHANGE
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DWX));
+}
+
+/**
+  * @brief Set destination half-word exchange.
+  * @rmtoll CTR1          DHX            LL_DMA_SetDestHWordExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestHWordExchange This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
+  *         @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
+             DestHWordExchange);
+}
+
+/**
+  * @brief Get destination half-word exchange.
+  * @rmtoll CTR1          DHX            LL_DMA_GetDestHWordExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
+  *         @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
+}
+
+/**
+  * @brief Set destination byte exchange.
+  * @rmtoll CTR1          DBX            LL_DMA_SetDestByteExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestByteExchange This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_BYTE_PRESERVE
+  *         @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
+             DestByteExchange);
+}
+
+/**
+  * @brief Get destination byte exchange.
+  * @rmtoll CTR1          DBX            LL_DMA_GetDestByteExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_BYTE_PRESERVE
+  *         @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
+}
+
+/**
+  * @brief Set source byte exchange.
+  * @rmtoll CTR1          SBX            LL_DMA_SetSrcByteExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcByteExchange This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_BYTE_PRESERVE
+  *         @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
+             SrcByteExchange);
+}
+
+/**
+  * @brief Get source byte exchange.
+  * @rmtoll CTR1          SBX            LL_DMA_GetSrcByteExchange
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_BYTE_PRESERVE
+  *         @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
+}
+
+/**
+  * @brief Set destination burst length.
+  * @rmtoll CTR1          DBL_1           LL_DMA_SetDestBurstLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestBurstLength Between 1 to 64
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
+             ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
+}
+
+/**
+  * @brief Get destination burst length.
+  * @rmtoll CTR1          DBL_1           LL_DMA_GetDestBurstLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 1 to 64.
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+                    DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
+}
+
+/**
+  * @brief Set destination increment mode.
+  * @rmtoll CTR1          DINC           LL_DMA_SetDestIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestInc This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_FIXED
+  *         @arg @ref LL_DMA_DEST_INCREMENT
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
+}
+
+/**
+  * @brief Get destination increment mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          DINC           LL_DMA_GetDestIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_FIXED
+  *         @arg @ref LL_DMA_DEST_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
+}
+
+/**
+  * @brief Set destination data width.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          DDW_LOG2           LL_DMA_SetDestDataWidth
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestDataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t  DestDataWidth)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
+             DestDataWidth);
+}
+
+/**
+  * @brief Get destination data width.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          DDW_LOG2           LL_DMA_GetDestDataWidth
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
+  *         @arg @ref LL_DMA_DEST_DATAWIDTH_DOUBLEWORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
+}
+
+/**
+  * @brief Set source allocated port.
+  * @rmtoll CTR1          SAP           LL_DMA_SetSrcAllocatedPort
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcAllocatedPort This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
+  *         @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
+             SrcAllocatedPort);
+}
+
+/**
+  * @brief Get source allocated port.
+  * @rmtoll CTR1          SAP           LL_DMA_GetSrcAllocatedPort
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
+  *         @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
+}
+
+/**
+  * @brief Set data alignment mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          PAM           LL_DMA_SetDataAlignment
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DataAlignment This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
+  *         @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
+  *         @arg @ref LL_DMA_DATA_PACK_UNPACK
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
+             DataAlignment);
+}
+
+/**
+  * @brief Get data alignment mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          PAM           LL_DMA_GetDataAlignment
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
+  *         @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
+  *         @arg @ref LL_DMA_DATA_PACK_UNPACK
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
+}
+
+/**
+  * @brief Set source burst length.
+  * @rmtoll CTR1          SBL_1           LL_DMA_SetSrcBurstLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcBurstLength Between 1 to 64
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
+             ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
+}
+
+/**
+  * @brief Get source burst length.
+  * @rmtoll CTR1          SBL_1           LL_DMA_GetSrcBurstLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 1 to 64
+  * @retval None.
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
+                    DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
+}
+
+/**
+  * @brief Set source increment mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          SINC           LL_DMA_SetSrcIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcInc This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_FIXED
+  *         @arg @ref LL_DMA_SRC_INCREMENT
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
+}
+
+/**
+  * @brief Get source increment mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          SINC           LL_DMA_GetSrcIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_FIXED
+  *         @arg @ref LL_DMA_SRC_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
+}
+
+/**
+  * @brief Set source data width.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          SDW_LOG2           LL_DMA_SetSrcDataWidth
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcDataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t  SrcDataWidth)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
+             SrcDataWidth);
+}
+
+/**
+  * @brief Get Source Data width.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR1          SDW_LOG2           LL_DMA_GetSrcDataWidth
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
+  *         @arg @ref LL_DMA_SRC_DATAWIDTH_DOUBLEWORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
+}
+
+/**
+  * @brief Configure channel transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2        TCEM               LL_DMA_ConfigChannelTransfer\n
+  *         CTR2        TRIGPOL            LL_DMA_ConfigChannelTransfer\n
+  *         CTR2        TRIGM              LL_DMA_ConfigChannelTransfer\n
+  *         CTR2        BREQ               LL_DMA_ConfigChannelTransfer\n
+  *         CTR2        DREQ               LL_DMA_ConfigChannelTransfer\n
+  *         CTR2        SWREQ              LL_DMA_ConfigChannelTransfer\n
+  *         CTR2        PFREQ              LL_DMA_ConfigChannelTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_TCEM_BLK_TRANSFER          or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER      or
+  *              @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER  or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
+  *         @arg @ref LL_DMA_HWREQUEST_SINGLEBURST      or @ref LL_DMA_HWREQUEST_BLK
+  *         @arg @ref LL_DMA_TRIG_POLARITY_MASKED       or @ref LL_DMA_TRIG_POLARITY_RISING       or
+  *              @ref LL_DMA_TRIG_POLARITY_FALLING
+  *         @arg @ref LL_DMA_TRIGM_BLK_TRANSFER         or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER     or
+  *              @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER    or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
+  *              @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_NORMAL                     or @ref LL_DMA_PFCTRL
+  *@retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+             (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ |
+              DMA_CTR2_PFREQ), Configuration);
+}
+
+/**
+  * @brief Set transfer event mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          TCEM           LL_DMA_SetTransferEventMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  TransferEventMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_TCEM_BLK_TRANSFER
+  *         @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
+  *         @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
+  *         @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t  TransferEventMode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
+             TransferEventMode);
+}
+
+/**
+  * @brief Get transfer event mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          TCEM           LL_DMA_GetTransferEventMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_TCEM_BLK_TRANSFER
+  *         @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
+  *         @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
+  *         @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
+}
+
+/**
+  * @brief Set trigger polarity.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          TRIGPOL            LL_DMA_SetTriggerPolarity
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  TriggerPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_TRIG_POLARITY_MASKED
+  *         @arg @ref LL_DMA_TRIG_POLARITY_RISING
+  *         @arg @ref LL_DMA_TRIG_POLARITY_FALLING
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
+             TriggerPolarity);
+}
+
+/**
+  * @brief Get trigger polarity.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          TRIGPOL            LL_DMA_GetTriggerPolarity
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_TRIG_POLARITY_MASKED
+  *         @arg @ref LL_DMA_TRIG_POLARITY_RISING
+  *         @arg @ref LL_DMA_TRIG_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
+}
+
+/**
+  * @brief Set trigger Mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          TRIGM            LL_DMA_SetTriggerMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  TriggerMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
+  *         @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
+  *         @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
+  *         @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
+             TriggerMode);
+}
+
+/**
+  * @brief Get trigger Mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          TRIGM            LL_DMA_GetTriggerMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
+  *         @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
+  *         @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
+  *         @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
+}
+
+/**
+  * @brief Set destination hardware and software transfer request.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          DREQ           LL_DMA_SetDataTransferDirection\n
+  * @rmtoll CTR2          SWREQ          LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+             DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
+}
+
+/**
+  * @brief Get destination hardware and software transfer request.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          DREQ           LL_DMA_GetDataTransferDirection\n
+  * @rmtoll CTR2          SWREQ          LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+                   DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
+}
+
+/**
+  * @brief Set block hardware request.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          BREQ           LL_DMA_SetBlkHWRequest\n
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkHWRequest This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
+  *         @arg @ref LL_DMA_HWREQUEST_BLK
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
+             BlkHWRequest);
+}
+
+/**
+  * @brief Get block hardware request.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2          BREQ           LL_DMA_GetBlkHWRequest\n
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
+  *         @arg @ref LL_DMA_HWREQUEST_BLK
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
+}
+
+/**
+  * @brief Set hardware request.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2         REQSEL     LL_DMA_SetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_HPDMA1_REQUEST_JPEG_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_JPEG_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_OCTOSPI1
+  *         @arg @ref LL_HPDMA1_REQUEST_OCTOSPI2
+  *         @arg @ref LL_HPDMA1_REQUEST_OCTOSPI3
+  *         @arg @ref LL_HPDMA1_REQUEST_FMC2_TXRX
+  *         @arg @ref LL_HPDMA1_REQUEST_FMC2_BCH
+  *         @arg @ref LL_HPDMA1_REQUEST_ADC1
+  *         @arg @ref LL_HPDMA1_REQUEST_ADC2
+  *         @arg @ref LL_HPDMA1_REQUEST_CRYP_IN
+  *         @arg @ref LL_HPDMA1_REQUEST_CRYP_OUT
+  *         @arg @ref LL_HPDMA1_REQUEST_SAES_OUT
+  *         @arg @ref LL_HPDMA1_REQUEST_SAES_IN
+  *         @arg @ref LL_HPDMA1_REQUEST_HASH_IN
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM6_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM7_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM16_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM16_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM16_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM17_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM17_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM17_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM18_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM18_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM18_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC1
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC2
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM1_UE
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC1
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC2
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM3_UE
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI3_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI3_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI4_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI4_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI5_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI5_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI6_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI6_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C3_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C3_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C4_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C4_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART3_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART3_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART4_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART4_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART5_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART5_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART6_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART6_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART7_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART7_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART8_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART8_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART9_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART9_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART10_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART10_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_LPUART1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_LPUART1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_CS
+  *         @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_DT
+  *         @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT0
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT1
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT2
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT3
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT4
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT5
+  *         @arg @ref LL_HPDMA1_REQUEST_UCPD1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UCPD1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_DCMI_PSSI
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_TC
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_RS
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_TC
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_RS
+  *         @arg @ref LL_GPDMA1_REQUEST_JPEG_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_JPEG_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
+  *         @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
+  *         @arg @ref LL_GPDMA1_REQUEST_OCTOSPI3
+  *         @arg @ref LL_GPDMA1_REQUEST_FMC2_TXRX
+  *         @arg @ref LL_GPDMA1_REQUEST_FMC2_BCH
+  *         @arg @ref LL_GPDMA1_REQUEST_ADC1
+  *         @arg @ref LL_GPDMA1_REQUEST_ADC2
+  *         @arg @ref LL_GPDMA1_REQUEST_CRYP_IN
+  *         @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT
+  *         @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
+  *         @arg @ref LL_GPDMA1_REQUEST_SAES_IN
+  *         @arg @ref LL_GPDMA1_REQUEST_HASH_IN
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM16_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM17_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM18_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM18_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM18_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI4_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI4_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI5_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI5_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI6_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI6_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART3_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART3_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART4_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART4_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART5_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART5_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART6_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART6_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART7_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART7_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART8_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART8_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART9_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART9_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART10_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART10_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_DT
+  *         @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_CS
+  *         @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
+  *         @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_TC
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_RS
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
+}
+
+/**
+  * @brief  Get hardware request.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2         REQSEL     LL_DMA_GetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_HPDMA1_REQUEST_JPEG_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_JPEG_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_OCTOSPI1
+  *         @arg @ref LL_HPDMA1_REQUEST_OCTOSPI2
+  *         @arg @ref LL_HPDMA1_REQUEST_OCTOSPI3
+  *         @arg @ref LL_HPDMA1_REQUEST_FMC2_TXRX
+  *         @arg @ref LL_HPDMA1_REQUEST_FMC2_BCH
+  *         @arg @ref LL_HPDMA1_REQUEST_ADC1
+  *         @arg @ref LL_HPDMA1_REQUEST_ADC2
+  *         @arg @ref LL_HPDMA1_REQUEST_CRYP_IN
+  *         @arg @ref LL_HPDMA1_REQUEST_CRYP_OUT
+  *         @arg @ref LL_HPDMA1_REQUEST_SAES_OUT
+  *         @arg @ref LL_HPDMA1_REQUEST_SAES_IN
+  *         @arg @ref LL_HPDMA1_REQUEST_HASH_IN
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM1_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM2_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM3_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM4_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM5_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM6_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM7_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH3
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_CH4
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM8_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_CH2
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_TRIG
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM15_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM16_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM16_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM16_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM17_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM17_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM17_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM18_CH1
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM18_UP
+  *         @arg @ref LL_HPDMA1_REQUEST_TIM18_COM
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC1
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM1_IC2
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM1_UE
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC1
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM2_IC2
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM2_UE
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC1
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM3_IC2
+  *         @arg @ref LL_HPDMA1_REQUEST_LPTIM3_UE
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI3_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI3_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI4_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI4_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI5_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI5_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI6_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPI6_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_HPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C3_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C3_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C4_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I2C4_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART2_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART2_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART3_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART3_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART4_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART4_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART5_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART5_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART6_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART6_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART7_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART7_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART8_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART8_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART9_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_UART9_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART10_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_USART10_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_LPUART1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_LPUART1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_CS
+  *         @arg @ref LL_HPDMA1_REQUEST_SPDIFRX_DT
+  *         @arg @ref LL_HPDMA1_REQUEST_ADF1_FLT0
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT0
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT1
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT2
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT3
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT4
+  *         @arg @ref LL_HPDMA1_REQUEST_MDF1_FLT5
+  *         @arg @ref LL_HPDMA1_REQUEST_UCPD1_TX
+  *         @arg @ref LL_HPDMA1_REQUEST_UCPD1_RX
+  *         @arg @ref LL_HPDMA1_REQUEST_DCMI_PSSI
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_TC
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C1_RS
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_TC
+  *         @arg @ref LL_HPDMA1_REQUEST_I3C2_RS
+  *         @arg @ref LL_GPDMA1_REQUEST_JPEG_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_JPEG_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
+  *         @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
+  *         @arg @ref LL_GPDMA1_REQUEST_OCTOSPI3
+  *         @arg @ref LL_GPDMA1_REQUEST_FMC2_TXRX
+  *         @arg @ref LL_GPDMA1_REQUEST_FMC2_BCH
+  *         @arg @ref LL_GPDMA1_REQUEST_ADC1
+  *         @arg @ref LL_GPDMA1_REQUEST_ADC2
+  *         @arg @ref LL_GPDMA1_REQUEST_CRYP_IN
+  *         @arg @ref LL_GPDMA1_REQUEST_CRYP_OUT
+  *         @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
+  *         @arg @ref LL_GPDMA1_REQUEST_SAES_IN
+  *         @arg @ref LL_GPDMA1_REQUEST_HASH_IN
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM2_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM4_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_CH2
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM16_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM17_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM18_CH1
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM18_UP
+  *         @arg @ref LL_GPDMA1_REQUEST_TIM18_COM
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
+  *         @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI4_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI4_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI5_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI5_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI6_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPI6_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_A
+  *         @arg @ref LL_GPDMA1_REQUEST_SAI1_B
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART2_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART2_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART3_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART3_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART4_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART4_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART5_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART5_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART6_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART6_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART7_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART7_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART8_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART8_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART9_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_UART9_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART10_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_USART10_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_DT
+  *         @arg @ref LL_GPDMA1_REQUEST_SPDIFRX_CS
+  *         @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
+  *         @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
+  *         @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
+  *         @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
+  *         @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_TC
+  *         @arg @ref LL_GPDMA1_REQUEST_I3C2_RS
+  */
+__STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
+}
+
+/**
+  * @brief Set hardware trigger.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2         TRIGSEL     LL_DMA_SetHWTrigger
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Trigger This parameter can be one of the following values:
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT
+  *         @arg @ref LL_HPDMA1_TRIGGER_LCD_LI
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_0
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_1
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_2
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_3
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_3
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_2
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_1
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH1
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH2
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH1
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH2
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH1
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH2
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM4_OUT
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM5_OUT
+  *         @arg @ref LL_HPDMA1_TRIGGER_RTC_WKUP
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO2
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM2_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM3_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM4_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM5_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM6_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM7_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO2
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM12_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM15_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT0_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT1_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT2_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT3_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT4_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT5_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT6_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT7_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT8_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT9_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT10_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT11_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT12_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT13_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT14_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT15_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT
+  *         @arg @ref LL_GPDMA1_TRIGGER_LCD_LI
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_0
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_1
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_2
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_3
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_3
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_2
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_1
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_0
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT
+  *         @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO2
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT1_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT2_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT3_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT4_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT5_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT6_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT7_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT8_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT9_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT10_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT11_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT12_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT13_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT14_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT15_SYNC
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
+             (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
+}
+
+/**
+  * @brief Get hardware triggers.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2         TRIGSEL     LL_DMA_GetHWTrigger
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_FEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_LEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_HSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P0_VSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_FEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_LEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_HSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P1_VSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_FEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_LEND
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_HSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DCMIPP_P2_VSYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DMA2D_CTC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TC
+  *         @arg @ref LL_HPDMA1_TRIGGER_DMA2D_TW
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_EOC
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFNF
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_IFT
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFNE
+  *         @arg @ref LL_HPDMA1_TRIGGER_JPEG_OFT
+  *         @arg @ref LL_HPDMA1_TRIGGER_LCD_LI
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_0
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_1
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_2
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPU2D1_GP_3
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_3
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_2
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_1
+  *         @arg @ref LL_HPDMA1_TRIGGER_GFXTIM_0
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH1
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM1_CH2
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH1
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM2_CH2
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH1
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM3_CH2
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM4_OUT
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPTIM5_OUT
+  *         @arg @ref LL_HPDMA1_TRIGGER_RTC_WKUP
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM1_TRGO2
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM2_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM3_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM4_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM5_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM6_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM7_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM8_TRGO2
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM12_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_TIM15_TRGO
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH0_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH1_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH2_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH3_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH4_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH5_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH6_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH7_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH8_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH9_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH10_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH11_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH12_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH13_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH14_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_HPDMA1_CH15_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH0_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH1_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH2_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH3_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH4_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH5_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH6_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH7_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH8_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH9_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH10_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH11_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH12_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH13_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH14_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_GPDMA1_CH15_TCF
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT0_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT1_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT2_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT3_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT4_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT5_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT6_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT7_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT8_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT9_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT10_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT11_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT12_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT13_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT14_SYNC
+  *         @arg @ref LL_HPDMA1_TRIGGER_EXTIT15_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_FEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_LEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_HSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P0_VSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_FEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_LEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_HSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P1_VSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_FEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_LEND
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_HSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DCMIPP_P2_VSYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC
+  *         @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE
+  *         @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT
+  *         @arg @ref LL_GPDMA1_TRIGGER_LCD_LI
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_0
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_1
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_2
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPU2D1_GP_3
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_3
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_2
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_1
+  *         @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_0
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_OUT
+  *         @arg @ref LL_GPDMA1_TRIGGER_RTC_WKUP
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_R_WUP_ASYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_LPUART1_IT_T_WUP_ASYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_SPI6_IT_OR_SPI6_AIT_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM1_TRGO2
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM6_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM7_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM8_TRGO2
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH0_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH1_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH2_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH3_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH4_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH5_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH6_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH7_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH8_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH9_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH10_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH11_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH12_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH13_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH14_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_HPDMA1_CH15_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT0_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT1_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT2_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT3_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT4_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT5_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT6_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT7_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT8_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT9_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT10_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT11_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT12_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT13_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT14_SYNC
+  *         @arg @ref LL_GPDMA1_TRIGGER_EXTIT15_SYNC
+  */
+__STATIC_INLINE  uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+                   DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
+}
+
+/**
+  * @brief Set DMA transfer mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2         PFREQ     LL_DMA_SetTransferMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_NORMAL
+  *         @arg @ref LL_DMA_PFCTRL
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_PFREQ,
+             Mode & DMA_CTR2_PFREQ);
+}
+
+/**
+  * @brief Get DMA transfer mode.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CTR2         TRIGSEL     LL_DMA_GetTransferMode
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_NORMAL
+  *         @arg @ref LL_DMA_PFCTRL
+  */
+__STATIC_INLINE  uint32_t LL_DMA_GetTransferMode(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
+                   DMA_CTR2_PFREQ));
+}
+
+/**
+  * @brief Configure addresses update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1         BRDDEC            LL_DMA_ConfigBlkRptAddrUpdate\n
+  *         CBR1         BRSDEC            LL_DMA_ConfigBlkRptAddrUpdate\n
+  *         CBR1         DDEC              LL_DMA_ConfigBlkRptAddrUpdate\n
+  *         CBR1         SDEC              LL_DMA_ConfigBlkRptAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
+  *         @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT  or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
+  *         @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT  or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
+  *         @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT   or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
+  *@retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
+             DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
+}
+
+/**
+  * @brief Configure DMA Block number of data and repeat Count.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1         BNDT                     LL_DMA_ConfigBlkCounters\n
+  *         CBR1         BRC                      LL_DMA_ConfigBlkCounters
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkDataLength Block transfer length
+                          Value between 0 to 0x0000FFFF
+  * @param  BlkRptCount Block repeat counter
+  *                     Value between 0 to 0x000007FF
+  *@retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
+                                              uint32_t BlkRptCount)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
+             (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
+}
+
+/**
+  * @brief Set block repeat destination address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          BRDDEC           LL_DMA_SetBlkRptDestAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkRptDestAddrUpdate This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
+                                                    uint32_t BlkRptDestAddrUpdate)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
+             BlkRptDestAddrUpdate);
+}
+
+/**
+  * @brief Get block repeat destination address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          BRDDEC           LL_DMA_GetBlkRptDestAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
+}
+
+/**
+  * @brief Set block repeat source address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          BRSDEC           LL_DMA_SetBlkRptSrcAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkRptSrcAddrUpdate This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel,
+                                                   uint32_t BlkRptSrcAddrUpdate)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
+             BlkRptSrcAddrUpdate);
+}
+
+/**
+  * @brief Get block repeat source address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          BRSDEC           LL_DMA_GetBlkRptSrcAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
+}
+
+/**
+  * @brief Set destination address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          DDEC           LL_DMA_SetDestAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestAddrUpdate This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
+             DestAddrUpdate);
+}
+
+/**
+  * @brief Get destination address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          DDEC           LL_DMA_GetDestAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
+}
+
+/**
+  * @brief Set source address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          SDEC           LL_DMA_SetSrcAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcAddrUpdate This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
+             SrcAddrUpdate);
+}
+
+/**
+  * @brief Get source address update.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1          SDEC           LL_DMA_GetSrcAddrUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
+  *         @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
+}
+
+/**
+  * @brief Set block repeat count.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1        BRC            LL_DMA_SetBlkRptCount
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkRptCount Block repeat counter
+  *                     Value between 0 to 0x000007FF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
+             (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
+}
+
+/**
+  * @brief Get block repeat count.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR1        BRC            LL_DMA_GetBlkRptCount
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x000007FF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
+                   DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
+}
+
+/**
+  * @brief  Set block data length in bytes to transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CBR1        BNDT         LL_DMA_SetBlkDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkDataLength Between 0 to 0x0000FFFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
+             BlkDataLength);
+}
+
+/**
+  * @brief  Get block data length in bytes to transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CBR1        BNDT         LL_DMA_GetBlkDataLength
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x0000FFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
+}
+
+/**
+  * @brief Configure the source and destination addresses.
+  * @note  This API is used for all available DMA channels.
+  * @note   This API must not be called when the DMA Channel is enabled.
+  * @rmtoll CSAR        SA          LL_DMA_ConfigAddresses\n
+  *         CDAR        DA          LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @param  DestAddress Between 0 to 0xFFFFFFFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
+                                            DestAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
+}
+
+/**
+  * @brief Set source address.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSAR        SA         LL_DMA_SetSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
+}
+
+/**
+  * @brief  Get source address.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSAR        SA         LL_DMA_GetSrcAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
+}
+
+/**
+  * @brief  Set destination address.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CDAR        DA         LL_DMA_SetDestAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestAddress Between 0 to 0xFFFFFFFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
+}
+
+/**
+  * @brief  Get destination address.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CDAR        DA         LL_DMA_GetDestAddress
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
+}
+
+/**
+  * @brief Configure source and destination addresses offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @note   This API must not be called when the DMA Channel is enabled.
+  * @rmtoll CTR3        DAO          LL_DMA_ConfigAddrUpdateValue\n
+  *         CTR3        SAO          LL_DMA_ConfigAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestAddrOffset Between 0 to 0x00001FFF
+  * @param  SrcAddrOffset Between 0 to 0x00001FFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
+                                                  uint32_t DestAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
+            (SrcAddrOffset  & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
+}
+
+/**
+  * @brief Set destination address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CTR3       DAO         LL_DMA_SetDestAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DestAddrOffset Between 0 to 0x00001FFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
+             ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
+}
+
+/**
+  * @brief Get destination address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CDAR        DAO         LL_DMA_GetDestAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x00001FFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
+                   DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
+}
+
+/**
+  * @brief Set source address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CTR3        SAO         LL_DMA_SetSrcAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  SrcAddrOffset Between 0 to 0x00001FFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
+             SrcAddrOffset & DMA_CTR3_SAO);
+}
+
+/**
+  * @brief Get source address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CTR3        SAO         LL_DMA_GetSrcAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x00001FFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
+}
+
+/**
+  * @brief Configure the block repeated source and destination addresses offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @note   This API must not be called when the DMA Channel is enabled.
+  * @rmtoll CBR2        BRDAO          LL_DMA_ConfigBlkRptAddrUpdateValue\n
+  *         CBR2        BRSAO          LL_DMA_ConfigBlkRptAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkRptDestAddrOffset Between 0 to 0x0000FFFF
+  * @param  BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
+                                                        uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
+            ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset  & DMA_CBR2_BRSAO));
+}
+
+/**
+  * @brief Set block repeated destination address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR2       BRDAO         LL_DMA_SetBlkRptDestAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkRptDestAddrOffset Between 0 to 0x0000FFFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
+                                                         uint32_t BlkRptDestAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
+             ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
+}
+
+/**
+  * @brief Get block repeated destination address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR2        BRDAO         LL_DMA_GetBlkRptDestAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x0000FFFF.
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
+                   DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
+}
+
+/**
+  * @brief Set block repeated source address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR2        BRSAO         LL_DMA_SetBlkRptSrcAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel,
+                                                        uint32_t BlkRptSrcAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
+             BlkRptSrcAddrOffset);
+}
+
+/**
+  * @brief Get block repeated source address offset.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CBR2        BRSAO         LL_DMA_GetBlkRptSrcAddrUpdateValue
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x0000FFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
+}
+
+/**
+  * @brief Configure registers update and node address offset during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  *        For linear addressing channels, UT3 and UB2 fields are discarded.
+  * @rmtoll CLLR          UT1            LL_DMA_ConfigLinkUpdate\n
+  * @rmtoll CLLR          UT2            LL_DMA_ConfigLinkUpdate\n
+  * @rmtoll CLLR          UB1            LL_DMA_ConfigLinkUpdate\n
+  * @rmtoll CLLR          USA            LL_DMA_ConfigLinkUpdate\n
+  * @rmtoll CLLR          UDA            LL_DMA_ConfigLinkUpdate\n
+  * @rmtoll CLLR          UT3            LL_DMA_ConfigLinkUpdate\n
+  * @rmtoll CLLR          UB2            LL_DMA_ConfigLinkUpdate\n
+  * @rmtoll CLLR          ULL            LL_DMA_ConfigLinkUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  RegistersUpdate This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_UPDATE_CTR1
+  *         @arg @ref LL_DMA_UPDATE_CTR2
+  *         @arg @ref LL_DMA_UPDATE_CBR1
+  *         @arg @ref LL_DMA_UPDATE_CSAR
+  *         @arg @ref LL_DMA_UPDATE_CDAR
+  *         @arg @ref LL_DMA_UPDATE_CTR3  (This value is allowed only for 2D addressing channels)
+  *         @arg @ref LL_DMA_UPDATE_CBR2  (This value is allowed only for 2D addressing channels)
+  *         @arg @ref LL_DMA_UPDATE_CLLR
+  * @param  LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
+                                             uint32_t LinkedListAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
+             (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
+              DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
+}
+
+/**
+  * @brief Enable CTR1 update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UT1            LL_DMA_EnableCTR1Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
+}
+
+/**
+  * @brief Disable CTR1 update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UT1            LL_DMA_DisableCTR1Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
+}
+
+/**
+  * @brief Check if CTR1 update during the link transfer is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UT1            LL_DMA_IsEnabledCTR1Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
+           == (DMA_CLLR_UT1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable CTR2 update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UT2            LL_DMA_EnableCTR2Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
+}
+
+/**
+  * @brief Disable CTR2 update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UT2            LL_DMA_DisableCTR2Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
+}
+
+/**
+  * @brief Check if CTR2 update during the link transfer is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UT2            LL_DMA_IsEnabledCTR2Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
+           == (DMA_CLLR_UT2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable CBR1 update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UB1            LL_DMA_EnableCBR1Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
+}
+
+/**
+  * @brief Disable CBR1 update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UB1            LL_DMA_DisableCBR1Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
+}
+
+/**
+  * @brief Check if CBR1 update during the link transfer is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UB1            LL_DMA_IsEnabledCBR1Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
+           == (DMA_CLLR_UB1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable CSAR update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          USA            LL_DMA_EnableCSARUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
+}
+
+/**
+  * @brief Disable CSAR update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          USA            LL_DMA_DisableCSARUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
+}
+
+/**
+  * @brief Check if CSAR update during the link transfer is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          USA            LL_DMA_IsEnabledCSARUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
+           == (DMA_CLLR_USA)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable CDAR update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UDA            LL_DMA_EnableCDARUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
+}
+
+/**
+  * @brief Disable CDAR update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UDA            LL_DMA_DisableCDARUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
+}
+
+/**
+  * @brief Check if CDAR update during the link transfer is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          UDA            LL_DMA_IsEnabledCDARUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
+           == (DMA_CLLR_UDA)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable CTR3 update during the link transfer.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CLLR          UT3            LL_DMA_EnableCTR3Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
+}
+
+/**
+  * @brief Disable CTR3 update during the link transfer.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CLLR          UT3            LL_DMA_DisableCTR3Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
+}
+
+/**
+  * @brief Check if CTR3 update during the link transfer is enabled.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CLLR          UT3            LL_DMA_IsEnabledCTR3Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
+           == (DMA_CLLR_UT3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable CBR2 update during the link transfer.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CLLR          UB2            LL_DMA_EnableCBR2Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
+}
+
+/**
+  * @brief Disable CBR2 update during the link transfer.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CLLR          UB2            LL_DMA_DisableCBR2Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
+}
+
+/**
+  * @brief Check if CBR2 update during the link transfer is enabled.
+  * @note  This API is used only for 2D addressing channels.
+  * @rmtoll CLLR          UB2            LL_DMA_IsEnabledCBR2Update
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
+           == (DMA_CLLR_UB2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable CLLR update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          ULL            LL_DMA_EnableCLLRUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
+}
+
+/**
+  * @brief Disable CLLR update during the link transfer.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          ULL            LL_DMA_DisableCLLRUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
+}
+
+/**
+  * @brief Check if CLLR update during the link transfer is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          ULL            LL_DMA_IsEnabledCLLRUpdate
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
+           == (DMA_CLLR_ULL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Set linked list address offset.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          LA           LL_DMA_SetLinkedListAddrOffset
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes.
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel,
+                                                    uint32_t  LinkedListAddrOffset)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
+             (LinkedListAddrOffset & DMA_CLLR_LA));
+}
+
+/**
+  * @brief Get linked list address offset.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CLLR          LA           LL_DMA_GetLinkedListAddrOffset
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x0000FFFC.
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
+                   DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
+}
+
+/**
+  * @brief Get FIFO level.
+  * @rmtoll CSR          FIFOL           LL_DMA_GetFIFOLevel
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval Between 0 to 0x000000FF.
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
+                   DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief Enable the DMA channel secure attribute.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll SECCFGR  SECx    LL_DMA_EnableChannelSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
+}
+
+/**
+  * @brief Disable the DMA channel secure attribute.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll SECCFGR  SECx    LL_DMA_DisableChannelSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief Check if DMA channel secure is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll SECCFGR             SECx          LL_DMA_IsEnabledChannelSecure
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
+           == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Enable the DMA channel privilege attribute.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll PRIVCFGR          PRIVx      LL_DMA_EnableChannelPrivilege
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
+}
+
+/**
+  * @brief Disable the DMA channel privilege attribute.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll PRIVCFGR          PRIVx      LL_DMA_DisableChannelPrivilege
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
+}
+
+/**
+  * @brief Check if DMA Channel privilege is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll PRIVCFGR          PRIVx      LL_DMA_IsEnabledChannelPrivilege
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
+           == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief Enable the DMA channel lock attributes.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll RCFGLOCKR           LOCKx         LL_DMA_EnableChannelLockAttribute
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief Check if DMA channel attributes are locked.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll SECCFGR            LOCKx       LL_DMA_IsEnabledChannelLockAttribute
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
+           == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management Flag Management
+  * @{
+  */
+
+/**
+  * @brief Clear trigger overrun flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CFCR          TOF        LL_DMA_ClearFlag_TO
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
+}
+
+/**
+  * @brief Clear suspension flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CFCR          SUSPF        LL_DMA_ClearFlag_SUSP
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
+}
+
+/**
+  * @brief Clear user setting error flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CFCR          USEF         LL_DMA_ClearFlag_USE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
+}
+
+/**
+  * @brief Clear link transfer error flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CFCR          ULEF         LL_DMA_ClearFlag_ULE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
+}
+
+/**
+  * @brief Clear data transfer error flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CFCR          DTEF         LL_DMA_ClearFlag_DTE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
+}
+
+/**
+  * @brief Clear half transfer flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CFCR          HTF          LL_DMA_ClearFlag_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
+}
+
+/**
+  * @brief Clear transfer complete flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CFCR          TCF          LL_DMA_ClearFlag_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
+}
+
+/**
+  * @brief Get trigger overrun flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           TOF        LL_DMA_IsActiveFlag_TO
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
+           == (DMA_CSR_TOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get suspension flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           SUSPF        LL_DMA_IsActiveFlag_SUSP
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
+           == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get user setting error flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           USEF         LL_DMA_IsActiveFlag_USE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
+           == (DMA_CSR_USEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get user setting error flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           ULEF         LL_DMA_IsActiveFlag_ULE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
+           == (DMA_CSR_ULEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get data transfer error flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           DTEF         LL_DMA_IsActiveFlag_DTE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
+           == (DMA_CSR_DTEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get half transfer flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           HTF          LL_DMA_IsActiveFlag_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
+           == (DMA_CSR_HTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get transfer complete flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           TCF          LL_DMA_IsActiveFlag_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
+           == (DMA_CSR_TCF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get idle flag.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CSR           IDLEF        LL_DMA_IsActiveFlag_IDLE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
+           == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if nsecure masked interrupt is active.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll MISR  MISx    LL_DMA_IsActiveFlag_MIS
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
+           == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief Check if secure masked interrupt is active.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll SMISR  MISx    LL_DMA_IsActiveFlag_SMIS
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
+           == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
+}
+#endif /* CPU_IN_SECURE_STATE */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief Enable trigger overrun interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           TOIE       LL_DMA_EnableIT_TO
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
+}
+
+/**
+  * @brief Enable suspension interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           SUSPIE       LL_DMA_EnableIT_SUSP
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
+}
+
+/**
+  * @brief Enable user setting error interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           USEIE        LL_DMA_EnableIT_USE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
+}
+
+/**
+  * @brief Enable update link transfer error interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           ULEIE        LL_DMA_EnableIT_ULE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
+}
+
+/**
+  * @brief Enable data transfer error interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           DTEIE        LL_DMA_EnableIT_DTE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
+}
+
+/**
+  * @brief Enable half transfer complete interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           HTIE         LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief Enable transfer complete interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           TCIE         LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief Disable trigger overrun interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           TOIE       LL_DMA_DisableIT_TO
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
+}
+
+/**
+  * @brief Disable suspension interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           SUSPIE       LL_DMA_DisableIT_SUSP
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
+}
+
+/**
+  * @brief Disable user setting error interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           USEIE        LL_DMA_DisableIT_USE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
+}
+
+/**
+  * @brief Disable update link transfer error interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           ULEIE        LL_DMA_DisableIT_ULE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
+}
+
+/**
+  * @brief Disable data transfer error interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           DTEIE        LL_DMA_DisableIT_DTE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
+}
+
+/**
+  * @brief Disable half transfer complete interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           HTIE         LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+  * @brief Disable transfer complete interrupt.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           TCIE         LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval None.
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+  * @brief Check if trigger overrun interrupt is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           TOIE       LL_DMA_IsEnabledIT_TO
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
+           == DMA_CCR_TOIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if suspension interrupt is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           SUSPIE       LL_DMA_IsEnabledIT_SUSP
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
+           == DMA_CCR_SUSPIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if user setting error interrupt is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR           USEIE        LL_DMA_IsEnabledIT_USE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
+           == DMA_CCR_USEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if update link transfer error interrupt is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR        ULEIE         LL_DMA_IsEnabledIT_ULE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
+           == DMA_CCR_ULEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if data transfer error interrupt is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR        DTEIE         LL_DMA_IsEnabledIT_DTE
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
+           == DMA_CCR_DTEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if half transfer complete interrupt is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR        HTIE         LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
+           == DMA_CCR_HTIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if transfer complete interrupt is enabled.
+  * @note  This API is used for all available DMA channels.
+  * @rmtoll CCR        TCIE         LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
+           == DMA_CCR_TCIE) ? 1UL : 0UL);
+}
+/**
+  * @}
+  */
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+
+void     LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+void     LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
+void     LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
+
+uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
+                          LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
+uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+
+uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
+void     LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
+                                LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
+void     LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* GPDMA1 || HPDMA1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32N6xx_LL_DMA_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dma2d.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dma2d.h
new file mode 100644
index 000000000..1493a413f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_dma2d.h
@@ -0,0 +1,2230 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_dma2d.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA2D LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_DMA2D_H
+#define STM32N6xx_LL_DMA2D_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA2D)
+
+/** @defgroup DMA2D_LL DMA2D
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL DMA2D Init Structure Definition
+  */
+typedef struct
+{
+  uint32_t Mode;                 /*!< Specifies the DMA2D transfer mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetMode(). */
+
+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputMemoryAddress;  /*!< Specifies the memory address.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+
+  uint32_t OutputSwapMode;             /*!< Specifies the output swap mode color format of the output image.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
+
+  uint32_t LineOffsetMode;       /*!< Specifies the output line offset mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
+
+  uint32_t LineOffset;           /*!< Specifies the output line offset value.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetLineOffset(). */
+
+  uint32_t NbrOfLines;           /*!< Specifies the number of lines of the area to be transferred.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+
+  uint32_t NbrOfPixelsPerLines;  /*!< Specifies the number of pixels per lines of the area to be transferred.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+
+  uint32_t AlphaInversionMode;   /*!< Specifies the output alpha inversion mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
+
+  uint32_t RBSwapMode;           /*!< Specifies the output Red Blue swap mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
+
+} LL_DMA2D_InitTypeDef;
+
+/**
+  * @brief LL DMA2D Layer Configuration Structure Definition
+  */
+typedef struct
+{
+  uint32_t MemoryAddress;        /*!< Specifies the foreground or background memory address.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
+
+  uint32_t LineOffset;           /*!< Specifies the foreground or background line offset value.
+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
+
+  uint32_t ColorMode;            /*!< Specifies the foreground or background color mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
+
+  uint32_t CLUTColorMode;        /*!< Specifies the foreground or background CLUT color mode.
+                                       - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
+
+  uint32_t CLUTSize;             /*!< Specifies the foreground or background CLUT size.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
+
+  uint32_t AlphaMode;            /*!< Specifies the foreground or background alpha mode.
+                                       - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
+
+  uint32_t Alpha;                /*!< Specifies the foreground or background Alpha value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
+
+  uint32_t Blue;                 /*!< Specifies the foreground or background Blue color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
+
+  uint32_t Green;                /*!< Specifies the foreground or background Green color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
+
+  uint32_t Red;                  /*!< Specifies the foreground or background Red color value.
+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
+
+  uint32_t CLUTMemoryAddress;    /*!< Specifies the foreground or background CLUT memory address.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
+
+  uint32_t AlphaInversionMode;   /*!< Specifies the foreground or background alpha inversion mode.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
+
+  uint32_t RBSwapMode;           /*!< Specifies the foreground or background Red Blue swap mode.
+                                      This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
+
+                                      This parameter can be modified afterwards using unitary functions
+                                      - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
+                                      - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
+
+  uint32_t ChromaSubSampling;   /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
+                                     This parameter is applicable for foreground layer only.
+                                     This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING
+
+                                     This parameter can be modified afterwards using unitary functions
+                                     - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */
+
+} LL_DMA2D_LayerCfgTypeDef;
+
+/**
+  * @brief LL DMA2D Output Color Structure Definition
+  */
+typedef struct
+{
+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.
+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
+
+                                      This parameter can be modified afterwards using
+                    unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+
+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards using,
+                                      unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+                                      - This parameter must be a number between:
+                                        Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.
+
+                                      This parameter can be modified afterwards,
+                                      using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+                                      function @ref LL_DMA2D_ConfigOutputColor(). */
+
+} LL_DMA2D_ColorTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMA2D_ReadReg function
+  * @{
+  */
+#define LL_DMA2D_FLAG_CEIF          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */
+#define LL_DMA2D_FLAG_CTCIF         DMA2D_ISR_CTCIF    /*!< CLUT Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_CAEIF         DMA2D_ISR_CAEIF    /*!< CLUT Access Error Interrupt Flag */
+#define LL_DMA2D_FLAG_TWIF          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */
+#define LL_DMA2D_FLAG_TCIF          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */
+#define LL_DMA2D_FLAG_TEIF          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA2D_ReadReg and  LL_DMA2D_WriteReg functions
+  * @{
+  */
+#define LL_DMA2D_IT_CEIE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */
+#define LL_DMA2D_IT_CTCIE            DMA2D_CR_CTCIE   /*!< CLUT Transfer Complete Interrupt */
+#define LL_DMA2D_IT_CAEIE            DMA2D_CR_CAEIE   /*!< CLUT Access Error Interrupt */
+#define LL_DMA2D_IT_TWIE             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */
+#define LL_DMA2D_IT_TCIE             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */
+#define LL_DMA2D_IT_TEIE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_DMA2D_MODE_M2M                       0x00000000U                       /*!< DMA2D memory to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_PFC                   DMA2D_CR_MODE_0                   /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND                 DMA2D_CR_MODE_1                   /*!< DMA2D memory to memory with blending transfer mode */
+#define LL_DMA2D_MODE_R2M                       (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG  DMA2D_CR_MODE_2                   /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
+#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG  (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
+  * @{
+  */
+#define LL_DMA2D_OUTPUT_MODE_ARGB8888     0x00000000U                           /*!< ARGB8888 */
+#define LL_DMA2D_OUTPUT_MODE_RGB888       DMA2D_OPFCCR_CM_0                     /*!< RGB888   */
+#define LL_DMA2D_OUTPUT_MODE_RGB565       DMA2D_OPFCCR_CM_1                     /*!< RGB565   */
+#define LL_DMA2D_OUTPUT_MODE_ARGB1555     (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
+#define LL_DMA2D_OUTPUT_MODE_ARGB4444     DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
+  * @{
+  */
+#define LL_DMA2D_INPUT_MODE_ARGB8888      0x00000000U                                                /*!< ARGB8888 */
+#define LL_DMA2D_INPUT_MODE_RGB888        DMA2D_FGPFCCR_CM_0                                         /*!< RGB888   */
+#define LL_DMA2D_INPUT_MODE_RGB565        DMA2D_FGPFCCR_CM_1                                         /*!< RGB565   */
+#define LL_DMA2D_INPUT_MODE_ARGB1555      (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)                    /*!< ARGB1555 */
+#define LL_DMA2D_INPUT_MODE_ARGB4444      DMA2D_FGPFCCR_CM_2                                         /*!< ARGB4444 */
+#define LL_DMA2D_INPUT_MODE_L8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)                    /*!< L8       */
+#define LL_DMA2D_INPUT_MODE_AL44          (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)                    /*!< AL44     */
+#define LL_DMA2D_INPUT_MODE_AL88          (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88     */
+#define LL_DMA2D_INPUT_MODE_L4            DMA2D_FGPFCCR_CM_3                                         /*!< L4       */
+#define LL_DMA2D_INPUT_MODE_A8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)                    /*!< A8       */
+#define LL_DMA2D_INPUT_MODE_A4            (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)                    /*!< A4       */
+#define LL_DMA2D_INPUT_MODE_YCBCR         (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr    */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
+  * @{
+  */
+#define LL_DMA2D_ALPHA_MODE_NO_MODIF       0x00000000U             /*!< No modification of the alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE        DMA2D_FGPFCCR_AM_0      /*!< Replace original alpha channel value by
+                                                                        programmed alpha value                     */
+#define LL_DMA2D_ALPHA_MODE_COMBINE        DMA2D_FGPFCCR_AM_1      /*!< Replace original alpha channel value by
+                                                                        programmed alpha value with,
+                                                                        original alpha channel value               */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
+  * @{
+  */
+#define LL_DMA2D_SWAP_MODE_REGULAR        0x00000000U                      /*!< Regular order */
+#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO     DMA2D_OPFCCR_SB                  /*!< Bytes swapped two by two */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
+  * @{
+  */
+#define LL_DMA2D_RB_MODE_REGULAR          0x00000000U                      /*!< RGB or ARGB */
+#define LL_DMA2D_RB_MODE_SWAP             DMA2D_FGPFCCR_RBS                /*!< BGR or ABGR */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
+  * @{
+  */
+#define LL_DMA2D_ALPHA_REGULAR          0x00000000U                     /*!< Regular alpha  */
+#define LL_DMA2D_ALPHA_INVERTED         DMA2D_FGPFCCR_AI                /*!< Inverted alpha */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
+  * @{
+  */
+#define LL_DMA2D_LINE_OFFSET_PIXELS     0x00000000U                     /*!< Line offsets are expressed in pixels  */
+#define LL_DMA2D_LINE_OFFSET_BYTES      DMA2D_CR_LOM                    /*!< Line offsets are expressed in bytes   */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
+  * @{
+  */
+#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888          0x00000000U                     /*!< ARGB8888 */
+#define LL_DMA2D_CLUT_COLOR_MODE_RGB888            DMA2D_FGPFCCR_CCM               /*!< RGB888   */
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling
+  * @{
+  */
+#define LL_DMA2D_CSS_444              0x00000000U             /*!< No chroma sub-sampling 4:4:4 */
+#define LL_DMA2D_CSS_422              DMA2D_FGPFCCR_CSS_0     /*!< chroma sub-sampling 4:2:2 */
+#define LL_DMA2D_CSS_420              DMA2D_FGPFCCR_CSS_1     /*!< chroma sub-sampling 4:2:0 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in DMA2D register.
+  * @param  __INSTANCE__ DMA2D Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA2D register.
+  * @param  __INSTANCE__ DMA2D Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Start a DMA2D transfer.
+  * @rmtoll CR          START            LL_DMA2D_Start
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
+}
+
+/**
+  * @brief  Indicate if a DMA2D transfer is ongoing.
+  * @rmtoll CR          START            LL_DMA2D_IsTransferOngoing
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Suspend DMA2D transfer.
+  * @note   This API can be used to suspend automatic foreground or background CLUT loading.
+  * @rmtoll CR          SUSP            LL_DMA2D_Suspend
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+}
+
+/**
+  * @brief  Resume DMA2D transfer.
+  * @note   This API can be used to resume automatic foreground or background CLUT loading.
+  * @rmtoll CR          SUSP            LL_DMA2D_Resume
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D transfer is suspended.
+  * @note   This API can be used to indicate whether or not automatic foreground or
+  *         background CLUT loading is suspended.
+  * @rmtoll CR          SUSP            LL_DMA2D_IsSuspended
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Abort DMA2D transfer.
+  * @note   This API can be used to abort automatic foreground or background CLUT loading.
+  * @rmtoll CR          ABORT            LL_DMA2D_Abort
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+}
+
+/**
+  * @brief  Indicate if DMA2D transfer is aborted.
+  * @note   This API can be used to indicate whether or not automatic foreground or
+  *         background CLUT loading is aborted.
+  * @rmtoll CR          ABORT            LL_DMA2D_IsAborted
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMA2D mode.
+  * @rmtoll CR          MODE          LL_DMA2D_SetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_MODE_M2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
+  *         @arg @ref LL_DMA2D_MODE_R2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
+}
+
+/**
+  * @brief  Return DMA2D mode
+  * @rmtoll CR          MODE         LL_DMA2D_GetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_MODE_M2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND
+  *         @arg @ref LL_DMA2D_MODE_R2M
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
+}
+
+/**
+  * @brief  Set DMA2D output color mode.
+  * @rmtoll OPFCCR          CM          LL_DMA2D_SetOutputColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D output color mode.
+  * @rmtoll OPFCCR          CM         LL_DMA2D_GetOutputColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D output Red Blue swap mode.
+  * @rmtoll OPFCCR          RBS          LL_DMA2D_SetOutputRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  RBSwapMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
+}
+
+/**
+  * @brief  Return DMA2D output Red Blue swap mode.
+  * @rmtoll OPFCCR          RBS         LL_DMA2D_GetOutputRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
+}
+
+/**
+  * @brief  Set DMA2D output alpha inversion mode.
+  * @rmtoll OPFCCR          AI          LL_DMA2D_SetOutputAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AlphaInversionMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+  * @brief  Return DMA2D output alpha inversion mode.
+  * @rmtoll OPFCCR          AI         LL_DMA2D_GetOutputAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
+}
+
+
+/**
+  * @brief  Set DMA2D output swap mode.
+  * @rmtoll OPFCCR          SB          LL_DMA2D_SetOutputSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  OutputSwapMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
+{
+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
+}
+
+/**
+  * @brief  Return DMA2D output swap mode.
+  * @rmtoll OPFCCR          SB         LL_DMA2D_GetOutputSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
+}
+
+/**
+  * @brief  Set DMA2D line offset mode.
+  * @rmtoll CR          LOM          LL_DMA2D_SetLineOffsetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffsetMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
+  *         @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
+{
+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
+}
+
+/**
+  * @brief  Return DMA2D line offset mode.
+  * @rmtoll CR          LOM         LL_DMA2D_GetLineOffsetMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
+  *         @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
+}
+
+/**
+  * @brief  Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll OOR          LO          LL_DMA2D_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll OOR          LO         LL_DMA2D_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
+  * @rmtoll NLR          PL          LL_DMA2D_SetNbrOfPixelsPerLines
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
+}
+
+/**
+  * @brief  Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
+  * @rmtoll NLR          PL          LL_DMA2D_GetNbrOfPixelsPerLines
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
+}
+
+/**
+  * @brief  Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+  * @rmtoll NLR          NL          LL_DMA2D_SetNbrOfLines
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
+}
+
+/**
+  * @brief  Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
+  * @rmtoll NLR          NL          LL_DMA2D_GetNbrOfLines
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
+}
+
+/**
+  * @brief  Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll OMAR          MA          LL_DMA2D_SetOutputMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll OMAR          MA          LL_DMA2D_GetOutputMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
+}
+
+/**
+  * @brief  Set DMA2D output color, expressed on 32 bits ([31:0] bits).
+  * @note   Output color format depends on output color mode, ARGB8888, RGB888,
+  *         RGB565, ARGB1555 or ARGB4444.
+  * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
+  *       with respect to color mode is not done by the user code.
+  * @rmtoll OCOLR        BLUE        LL_DMA2D_SetOutputColor\n
+  *         OCOLR        GREEN       LL_DMA2D_SetOutputColor\n
+  *         OCOLR        RED         LL_DMA2D_SetOutputColor\n
+  *         OCOLR        ALPHA       LL_DMA2D_SetOutputColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
+{
+  WRITE_REG(DMA2Dx->OCOLR, OutputColor);
+}
+
+/**
+  * @brief  Get DMA2D output color, expressed on 32 bits ([31:0] bits).
+  * @note   Alpha channel and red, green, blue color values must be retrieved from the returned
+  *         value based on the output color mode (ARGB8888, RGB888,  RGB565, ARGB1555 or ARGB4444)
+  *         as set by @ref LL_DMA2D_SetOutputColorMode.
+  * @rmtoll OCOLR        BLUE        LL_DMA2D_GetOutputColor\n
+  *         OCOLR        GREEN       LL_DMA2D_GetOutputColor\n
+  *         OCOLR        RED         LL_DMA2D_GetOutputColor\n
+  *         OCOLR        ALPHA       LL_DMA2D_GetOutputColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
+                             (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
+}
+
+/**
+  * @brief  Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+  * @rmtoll LWR          LW          LL_DMA2D_SetLineWatermark
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
+{
+  MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
+}
+
+/**
+  * @brief  Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
+  * @rmtoll LWR          LW          LL_DMA2D_GetLineWatermark
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
+}
+
+/**
+  * @brief  Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
+  * @rmtoll AMTCR          DT          LL_DMA2D_SetDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DeadTime Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
+{
+  MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
+}
+
+/**
+  * @brief  Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
+  * @rmtoll AMTCR          DT          LL_DMA2D_GetDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
+}
+
+/**
+  * @brief  Enable DMA2D dead time functionality.
+  * @rmtoll AMTCR          EN            LL_DMA2D_EnableDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+  * @brief  Disable DMA2D dead time functionality.
+  * @rmtoll AMTCR          EN            LL_DMA2D_DisableDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
+}
+
+/**
+  * @brief  Indicate if DMA2D dead time functionality is enabled.
+  * @rmtoll AMTCR          EN            LL_DMA2D_IsEnabledDeadTime
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
+}
+
+/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_SetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_GetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
+}
+
+/**
+  * @brief  Enable DMA2D foreground CLUT loading.
+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_EnableCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D foreground CLUT loading is enabled.
+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_IsEnabledCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMA2D foreground color mode.
+  * @rmtoll FGPFCCR          CM          LL_DMA2D_FGND_SetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground color mode.
+  * @rmtoll FGPFCCR          CM         LL_DMA2D_FGND_GetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha mode.
+  * @rmtoll FGPFCCR          AM          LL_DMA2D_FGND_SetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AphaMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha mode.
+  * @rmtoll FGPFCCR          AM         LL_DMA2D_FGND_GetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          ALPHA          LL_DMA2D_FGND_SetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          ALPHA         LL_DMA2D_FGND_GetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground Red Blue swap mode.
+  * @rmtoll FGPFCCR          RBS          LL_DMA2D_FGND_SetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  RBSwapMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground Red Blue swap mode.
+  * @rmtoll FGPFCCR          RBS         LL_DMA2D_FGND_GetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
+}
+
+/**
+  * @brief  Set DMA2D foreground alpha inversion mode.
+  * @rmtoll FGPFCCR          AI          LL_DMA2D_FGND_SetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AlphaInversionMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground alpha inversion mode.
+  * @rmtoll FGPFCCR          AI         LL_DMA2D_FGND_GetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
+}
+
+/**
+  * @brief  Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll FGOR          LO          LL_DMA2D_FGND_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll FGOR          LO         LL_DMA2D_FGND_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetColor
+  * @rmtoll FGCOLR          GREEN        LL_DMA2D_FGND_SetColor
+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_SetColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
+             ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+  * @brief  Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          RED         LL_DMA2D_FGND_GetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          GREEN          LL_DMA2D_FGND_SetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
+}
+
+/**
+  * @brief  Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          GREEN         LL_DMA2D_FGND_GetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          BLUE          LL_DMA2D_FGND_SetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
+}
+
+/**
+  * @brief  Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_GetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_SetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_GetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_SetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
+}
+
+/**
+  * @brief  Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_GetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
+}
+
+/**
+  * @brief  Set DMA2D foreground CLUT color mode.
+  * @rmtoll FGPFCCR          CCM          LL_DMA2D_FGND_SetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+  * @brief  Return DMA2D foreground CLUT color mode.
+  * @rmtoll FGPFCCR          CCM         LL_DMA2D_FGND_GetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
+}
+
+/**
+  * @brief  Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
+  * @rmtoll FGPFCCR          CSS          LL_DMA2D_FGND_SetChrSubSampling
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ChromaSubSampling This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_CSS_444
+  *         @arg @ref LL_DMA2D_CSS_422
+  *         @arg @ref LL_DMA2D_CSS_420
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
+{
+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);
+}
+
+/**
+  * @brief  Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
+  * @rmtoll FGPFCCR          CSS         LL_DMA2D_FGND_GetChrSubSampling
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_CSS_444
+  *         @arg @ref LL_DMA2D_CSS_422
+  *         @arg @ref LL_DMA2D_CSS_420
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));
+}
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
+  * @{
+  */
+
+/**
+  * @brief  Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_SetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_GetMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
+}
+
+/**
+  * @brief  Enable DMA2D background CLUT loading.
+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_EnableCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
+}
+
+/**
+  * @brief  Indicate if DMA2D background CLUT loading is enabled.
+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_IsEnabledCLUTLoad
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMA2D background color mode.
+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_SetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
+}
+
+/**
+  * @brief  Return DMA2D background color mode.
+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_GetColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44
+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88
+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8
+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
+}
+
+/**
+  * @brief  Set DMA2D background alpha mode.
+  * @rmtoll BGPFCCR          AM         LL_DMA2D_BGND_SetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AphaMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
+}
+
+/**
+  * @brief  Return DMA2D background alpha mode.
+  * @rmtoll BGPFCCR          AM          LL_DMA2D_BGND_GetAlphaMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
+}
+
+/**
+  * @brief  Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          ALPHA         LL_DMA2D_BGND_SetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          ALPHA          LL_DMA2D_BGND_GetAlpha
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background Red Blue swap mode.
+  * @rmtoll BGPFCCR          RBS         LL_DMA2D_BGND_SetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  RBSwapMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
+}
+
+/**
+  * @brief  Return DMA2D background Red Blue swap mode.
+  * @rmtoll BGPFCCR          RBS          LL_DMA2D_BGND_GetRBSwapMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR
+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
+}
+
+/**
+  * @brief  Set DMA2D background alpha inversion mode.
+  * @rmtoll BGPFCCR          AI         LL_DMA2D_BGND_SetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  AlphaInversionMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
+}
+
+/**
+  * @brief  Return DMA2D background alpha inversion mode.
+  * @rmtoll BGPFCCR          AI          LL_DMA2D_BGND_GetAlphaInvMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR
+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
+}
+
+/**
+  * @brief  Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll BGOR          LO         LL_DMA2D_BGND_SetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
+{
+  MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
+}
+
+/**
+  * @brief  Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
+  * @rmtoll BGOR          LO          LL_DMA2D_BGND_GetLineOffset
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
+}
+
+/**
+  * @brief  Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_SetColor
+  * @rmtoll BGCOLR          GREEN        LL_DMA2D_BGND_SetColor
+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
+             ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
+}
+
+/**
+  * @brief  Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          RED         LL_DMA2D_BGND_SetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_GetRedColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          GREEN         LL_DMA2D_BGND_SetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
+}
+
+/**
+  * @brief  Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          GREEN          LL_DMA2D_BGND_GetGreenColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
+{
+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
+}
+
+/**
+  * @brief  Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGCOLR          BLUE          LL_DMA2D_BGND_GetBlueColor
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
+}
+
+/**
+  * @brief  Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGCMAR          MA         LL_DMA2D_BGND_SetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
+{
+  LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
+}
+
+/**
+  * @brief  Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
+  * @rmtoll BGCMAR          MA           LL_DMA2D_BGND_GetCLUTMemAddr
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
+}
+
+/**
+  * @brief  Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          CS         LL_DMA2D_BGND_SetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
+}
+
+/**
+  * @brief  Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
+  * @rmtoll BGPFCCR          CS           LL_DMA2D_BGND_GetCLUTSize
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
+}
+
+/**
+  * @brief  Set DMA2D background CLUT color mode.
+  * @rmtoll BGPFCCR          CCM         LL_DMA2D_BGND_SetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @param  CLUTColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
+{
+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
+}
+
+/**
+  * @brief  Return DMA2D background CLUT color mode.
+  * @rmtoll BGPFCCR          CCM          LL_DMA2D_BGND_GetCLUTColorMode
+  * @param  DMA2Dx DMA2D Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
+  */
+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
+{
+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the DMA2D Configuration Error Interrupt Flag is set or not
+  * @rmtoll ISR          CEIF            LL_DMA2D_IsActiveFlag_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
+  * @rmtoll ISR          CTCIF            LL_DMA2D_IsActiveFlag_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
+  * @rmtoll ISR          CAEIF            LL_DMA2D_IsActiveFlag_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
+  * @rmtoll ISR          TWIF            LL_DMA2D_IsActiveFlag_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Complete Interrupt Flag is set or not
+  * @rmtoll ISR          TCIF            LL_DMA2D_IsActiveFlag_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Error Interrupt Flag is set or not
+  * @rmtoll ISR          TEIF            LL_DMA2D_IsActiveFlag_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear DMA2D Configuration Error Interrupt Flag
+  * @rmtoll IFCR          CCEIF          LL_DMA2D_ClearFlag_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
+}
+
+/**
+  * @brief  Clear DMA2D CLUT Transfer Complete Interrupt Flag
+  * @rmtoll IFCR          CCTCIF          LL_DMA2D_ClearFlag_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
+}
+
+/**
+  * @brief  Clear DMA2D CLUT Access Error Interrupt Flag
+  * @rmtoll IFCR          CAECIF          LL_DMA2D_ClearFlag_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Watermark Interrupt Flag
+  * @rmtoll IFCR          CTWIF          LL_DMA2D_ClearFlag_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Complete Interrupt Flag
+  * @rmtoll IFCR          CTCIF          LL_DMA2D_ClearFlag_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
+}
+
+/**
+  * @brief  Clear DMA2D Transfer Error Interrupt Flag
+  * @rmtoll IFCR          CTEIF          LL_DMA2D_ClearFlag_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Configuration Error Interrupt
+  * @rmtoll CR          CEIE        LL_DMA2D_EnableIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+  * @brief  Enable CLUT Transfer Complete Interrupt
+  * @rmtoll CR          CTCIE        LL_DMA2D_EnableIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+  * @brief  Enable CLUT Access Error Interrupt
+  * @rmtoll CR          CAEIE        LL_DMA2D_EnableIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+  * @brief  Enable Transfer Watermark Interrupt
+  * @rmtoll CR          TWIE        LL_DMA2D_EnableIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+  * @brief  Enable Transfer Complete Interrupt
+  * @rmtoll CR          TCIE        LL_DMA2D_EnableIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+  * @brief  Enable Transfer Error Interrupt
+  * @rmtoll CR          TEIE        LL_DMA2D_EnableIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+  * @brief  Disable Configuration Error Interrupt
+  * @rmtoll CR          CEIE        LL_DMA2D_DisableIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
+}
+
+/**
+  * @brief  Disable CLUT Transfer Complete Interrupt
+  * @rmtoll CR          CTCIE        LL_DMA2D_DisableIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
+}
+
+/**
+  * @brief  Disable CLUT Access Error Interrupt
+  * @rmtoll CR          CAEIE        LL_DMA2D_DisableIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
+}
+
+/**
+  * @brief  Disable Transfer Watermark Interrupt
+  * @rmtoll CR          TWIE        LL_DMA2D_DisableIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete Interrupt
+  * @rmtoll CR          TCIE        LL_DMA2D_DisableIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Error Interrupt
+  * @rmtoll CR          TEIE        LL_DMA2D_DisableIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
+{
+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
+}
+
+/**
+  * @brief  Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
+  * @rmtoll CR          CEIE        LL_DMA2D_IsEnabledIT_CE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
+  * @rmtoll CR          CTCIE        LL_DMA2D_IsEnabledIT_CTC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
+  * @rmtoll CR          CAEIE        LL_DMA2D_IsEnabledIT_CAE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
+  * @rmtoll CR          TWIE        LL_DMA2D_IsEnabledIT_TW
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
+  * @rmtoll CR          TCIE        LL_DMA2D_IsEnabledIT_TC
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
+  * @rmtoll CR          TEIE        LL_DMA2D_IsEnabledIT_TE
+  * @param  DMA2Dx DMA2D Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx)
+{
+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
+}
+
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+  * @{
+  */
+
+ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx);
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
+uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (DMA2D) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_DMA2D_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_exti.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_exti.h
new file mode 100644
index 000000000..95040fb10
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_exti.h
@@ -0,0 +1,2896 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_exti.h
+  * @author  GPM Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef  STM32N6xx_LL_EXTI_H
+#define  STM32N6xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+#define LL_EXTI_REGISTER_PINPOS_SHFT        16U   /*!< Define used to shift pin position in EXTICR register */
+
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_64_95;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
+#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
+#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
+#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
+#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
+#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
+#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
+#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
+#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
+#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
+#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
+#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
+#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
+#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
+#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
+#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< ALL Extended line */
+
+#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
+#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
+#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
+#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
+#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
+#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
+#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
+#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
+#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
+#define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
+#define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
+#define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */
+#define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */
+#define LL_EXTI_LINE_45                EXTI_IMR2_IM45          /*!< Extended line 45 */
+#define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */
+#define LL_EXTI_LINE_47                EXTI_IMR2_IM47          /*!< Extended line 47 */
+#define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */
+#define LL_EXTI_LINE_49                EXTI_IMR2_IM49          /*!< Extended line 49 */
+#define LL_EXTI_LINE_50                EXTI_IMR2_IM50          /*!< Extended line 50 */
+#define LL_EXTI_LINE_51                EXTI_IMR2_IM51          /*!< Extended line 51 */
+#define LL_EXTI_LINE_52                EXTI_IMR2_IM52          /*!< Extended line 52 */
+#define LL_EXTI_LINE_53                EXTI_IMR2_IM53          /*!< Extended line 53 */
+#define LL_EXTI_LINE_54                EXTI_IMR2_IM54          /*!< Extended line 54 */
+#define LL_EXTI_LINE_55                EXTI_IMR2_IM55          /*!< Extended line 55 */
+#define LL_EXTI_LINE_56                EXTI_IMR2_IM56          /*!< Extended line 56 */
+#define LL_EXTI_LINE_57                EXTI_IMR2_IM57          /*!< Extended line 57 */
+#define LL_EXTI_LINE_58                EXTI_IMR2_IM58          /*!< Extended line 58 */
+#define LL_EXTI_LINE_60                EXTI_IMR2_IM60          /*!< Extended line 60 */
+#define LL_EXTI_LINE_61                EXTI_IMR2_IM61          /*!< Extended line 61 */
+#define LL_EXTI_LINE_62                EXTI_IMR2_IM62          /*!< Extended line 62 */
+#define LL_EXTI_LINE_63                EXTI_IMR2_IM63          /*!< Extended line 63 */
+#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_64                EXTI_IMR3_IM64          /*!< Extended line 64 */
+#define LL_EXTI_LINE_65                EXTI_IMR3_IM65          /*!< Extended line 65 */
+#define LL_EXTI_LINE_66                EXTI_IMR3_IM66          /*!< Extended line 66 */
+#define LL_EXTI_LINE_68                EXTI_IMR3_IM68          /*!< Extended line 68 */
+#define LL_EXTI_LINE_69                EXTI_IMR3_IM69          /*!< Extended line 69 */
+#define LL_EXTI_LINE_70                EXTI_IMR3_IM70          /*!< Extended line 70 */
+#define LL_EXTI_LINE_71                EXTI_IMR3_IM71          /*!< Extended line 71 */
+#define LL_EXTI_LINE_72                EXTI_IMR3_IM72          /*!< Extended line 72 */
+#define LL_EXTI_LINE_73                EXTI_IMR3_IM73          /*!< Extended line 73 */
+#define LL_EXTI_LINE_74                EXTI_IMR3_IM74          /*!< Extended line 74 */
+#define LL_EXTI_LINE_77                EXTI_IMR3_IM77          /*!< Extended line 77 */
+#define LL_EXTI_LINE_ALL_64_95         EXTI_IMR3_IM            /*!< All Extended line not reserved*/
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              0x00000000U             /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT
+  * @{
+  */
+#define LL_EXTI_EXTI_PORTA               0U                                                               /*!< EXTI PORT A */
+#define LL_EXTI_EXTI_PORTB               EXTI_EXTICR1_EXTI0_0                                             /*!< EXTI PORT B */
+#define LL_EXTI_EXTI_PORTC               EXTI_EXTICR1_EXTI0_1                                             /*!< EXTI PORT C */
+#define LL_EXTI_EXTI_PORTD               (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0)                      /*!< EXTI PORT D */
+#define LL_EXTI_EXTI_PORTE               EXTI_EXTICR1_EXTI0_2                                             /*!< EXTI PORT E */
+#define LL_EXTI_EXTI_PORTF               (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0)                      /*!< EXTI PORT F */
+#define LL_EXTI_EXTI_PORTG               (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1)                      /*!< EXTI PORT G */
+#define LL_EXTI_EXTI_PORTH               (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */
+#define LL_EXTI_EXTI_PORTN               EXTI_EXTICR1_EXTI0_3                                             /*!< EXTI PORT N */
+#define LL_EXTI_EXTI_PORTO               (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_0)                      /*!< EXTI PORT O */
+#define LL_EXTI_EXTI_PORTP               (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_1)                      /*!< EXTI PORT P */
+#define LL_EXTI_EXTI_PORTQ               (EXTI_EXTICR1_EXTI0_3|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT Q */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE
+  * @{
+  */
+#define LL_EXTI_EXTI_LINE0               (0U  << LL_EXTI_REGISTER_PINPOS_SHFT | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE1               (8U  << LL_EXTI_REGISTER_PINPOS_SHFT | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE2               (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U)  /*!< EXTI_POSITION_16 | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE3               (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U)  /*!< EXTI_POSITION_24 | EXTICR[0] */
+#define LL_EXTI_EXTI_LINE4               (0U  << LL_EXTI_REGISTER_PINPOS_SHFT | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE5               (8U  << LL_EXTI_REGISTER_PINPOS_SHFT | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE6               (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U)  /*!< EXTI_POSITION_16 | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE7               (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U)  /*!< EXTI_POSITION_24 | EXTICR[1] */
+#define LL_EXTI_EXTI_LINE8               (0U  << LL_EXTI_REGISTER_PINPOS_SHFT | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE9               (8U  << LL_EXTI_REGISTER_PINPOS_SHFT | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE10              (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U)  /*!< EXTI_POSITION_16 | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE11              (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U)  /*!< EXTI_POSITION_24 | EXTICR[2] */
+#define LL_EXTI_EXTI_LINE12              (0U  << LL_EXTI_REGISTER_PINPOS_SHFT | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_EXTI_EXTI_LINE13              (8U  << LL_EXTI_REGISTER_PINPOS_SHFT | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_EXTI_EXTI_LINE14              (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U)  /*!< EXTI_POSITION_16 | EXTICR[3] */
+#define LL_EXTI_EXTI_LINE15              (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U)  /*!< EXTI_POSITION_24 | EXTICR[3] */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+  * @{
+  */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @note The reset value for the direct lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @note The reset value for the direct lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR3         IMx           LL_EXTI_EnableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @note The reset value for the direct lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @note The reset value for the direct lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR3         IMx           LL_EXTI_DisableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR3, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+  * @note The reset value for the direct lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
+  * @note The reset value for the direct lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR3         IMx           LL_EXTI_IsEnabledIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_EnableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_DisableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_IsEnabledEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_EnableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_DisableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll RTSR3        RTx           LL_EXTI_IsEnabledRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_EnableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_DisableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll FTSR3        FTx           LL_EXTI_IsEnabledFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 64 to 95
+  * @note If the interrupt is enabled on this line in the EXTI_IMR3, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR3
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR3
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER3, ExtiLine);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the falling edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR1          FPIFx           LL_EXTI_IsActiveFallingFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR2          FPIFx           LL_EXTI_IsActiveFallingFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR3          FPIFx           LL_EXTI_IsActiveFallingFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FPR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Read ExtLine Combination Falling Flag for Lines in range 0 to 31
+  * @note This bit is set when the falling edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR1          FPIFx           LL_EXTI_ReadFallingFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR2          FPIFx           LL_EXTI_ReadFallingFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->FPR2, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR3          FPIFx           LL_EXTI_ReadFallingFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->FPR3, ExtiLine));
+}
+
+
+/**
+  * @brief  Clear ExtLine Falling Flags  for Lines in range 0 to 31
+  * @note This bit is set when the falling edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR1          FPIFx           LL_EXTI_ClearFallingFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->FPR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR2          FPIFx           LL_EXTI_ClearFallingFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->FPR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll FPR3          FPIFx           LL_EXTI_ClearFallingFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFallingFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->FPR3, ExtiLine);
+}
+
+/**
+  * @brief  Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR1          RPIFx           LL_EXTI_IsActiveRisingFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR2          RPIFx           LL_EXTI_IsActiveRisingFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the ExtLine Rising Flag is set or not for Lines in range 64 to 95
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR3          RPIFx           LL_EXTI_IsActiveRisingFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RPR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Read ExtLine Combination Rising Flag for Lines in range 0 to 31
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR1          RPIFx           LL_EXTI_ReadRisingFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Rising Flag for Lines in range 32 to 63
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR2          RPIFx           LL_EXTI_ReadRisingFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->RPR2, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Rising Flag for Lines in range 64 to 95
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR3          RPIFx           LL_EXTI_ReadRisingFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->RPR3, ExtiLine));
+}
+
+/**
+  * @brief  Clear ExtLine Rising Flags  for Lines in range 0 to 31
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR1          RPIFx           LL_EXTI_ClearRisingFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->RPR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Rising Flags  for Lines in range 32 to 63
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR2          RPIFx           LL_EXTI_ClearRisingFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_56
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->RPR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Rising Flags  for Lines in range 64 to 95
+  * @note This bit is set when the Rising edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll RPR3          RPIFx           LL_EXTI_ClearRisingFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearRisingFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->RPR3, ExtiLine);
+}
+
+/**
+  * @}
+  */
+/** @defgroup EXTI_LL_EF_Config EF configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll EXTI_EXTICR1 EXTI0         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR1 EXTI1         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR1 EXTI2         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR1 EXTI3         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR2 EXTI4         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR2 EXTI5         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR2 EXTI6         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR2 EXTI7         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR3 EXTI8         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR3 EXTI9         LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR3 EXTI10        LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR3 EXTI11        LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR4 EXTI12        LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR4 EXTI13        LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR4 EXTI14        LL_EXTI_SetEXTISource\n
+  *         EXTI_EXTICR4 EXTI15        LL_EXTI_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_EXTI_PORTA
+  *         @arg @ref LL_EXTI_EXTI_PORTB
+  *         @arg @ref LL_EXTI_EXTI_PORTC
+  *         @arg @ref LL_EXTI_EXTI_PORTD
+  *         @arg @ref LL_EXTI_EXTI_PORTE
+  *         @arg @ref LL_EXTI_EXTI_PORTF
+  *         @arg @ref LL_EXTI_EXTI_PORTG
+  *         @arg @ref LL_EXTI_EXTI_PORTH
+  *         @arg @ref LL_EXTI_EXTI_PORTN
+  *         @arg @ref LL_EXTI_EXTI_PORTO
+  *         @arg @ref LL_EXTI_EXTI_PORTP
+  *         @arg @ref LL_EXTI_EXTI_PORTQ
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_EXTI_LINE0
+  *         @arg @ref LL_EXTI_EXTI_LINE1
+  *         @arg @ref LL_EXTI_EXTI_LINE2
+  *         @arg @ref LL_EXTI_EXTI_LINE3
+  *         @arg @ref LL_EXTI_EXTI_LINE4
+  *         @arg @ref LL_EXTI_EXTI_LINE5
+  *         @arg @ref LL_EXTI_EXTI_LINE6
+  *         @arg @ref LL_EXTI_EXTI_LINE7
+  *         @arg @ref LL_EXTI_EXTI_LINE8
+  *         @arg @ref LL_EXTI_EXTI_LINE9
+  *         @arg @ref LL_EXTI_EXTI_LINE10
+  *         @arg @ref LL_EXTI_EXTI_LINE11
+  *         @arg @ref LL_EXTI_EXTI_LINE12
+  *         @arg @ref LL_EXTI_EXTI_LINE13
+  *         @arg @ref LL_EXTI_EXTI_LINE14
+  *         @arg @ref LL_EXTI_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT),
+             Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll EXTI_EXTICR1 EXTI0         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR1 EXTI1         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR1 EXTI2         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR1 EXTI3         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR2 EXTI4         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR2 EXTI5         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR2 EXTI6         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR2 EXTI7         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR3 EXTI8         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR3 EXTI9         LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR3 EXTI10        LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR3 EXTI11        LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR4 EXTI12        LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR4 EXTI13        LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR4 EXTI14        LL_EXTI_GetEXTISource\n
+  *         EXTI_EXTICR4 EXTI15        LL_EXTI_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_EXTI_LINE0
+  *         @arg @ref LL_EXTI_EXTI_LINE1
+  *         @arg @ref LL_EXTI_EXTI_LINE2
+  *         @arg @ref LL_EXTI_EXTI_LINE3
+  *         @arg @ref LL_EXTI_EXTI_LINE4
+  *         @arg @ref LL_EXTI_EXTI_LINE5
+  *         @arg @ref LL_EXTI_EXTI_LINE6
+  *         @arg @ref LL_EXTI_EXTI_LINE7
+  *         @arg @ref LL_EXTI_EXTI_LINE8
+  *         @arg @ref LL_EXTI_EXTI_LINE9
+  *         @arg @ref LL_EXTI_EXTI_LINE10
+  *         @arg @ref LL_EXTI_EXTI_LINE11
+  *         @arg @ref LL_EXTI_EXTI_LINE12
+  *         @arg @ref LL_EXTI_EXTI_LINE13
+  *         @arg @ref LL_EXTI_EXTI_LINE14
+  *         @arg @ref LL_EXTI_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_EXTI_PORTA
+  *         @arg @ref LL_EXTI_EXTI_PORTB
+  *         @arg @ref LL_EXTI_EXTI_PORTC
+  *         @arg @ref LL_EXTI_EXTI_PORTD
+  *         @arg @ref LL_EXTI_EXTI_PORTE
+  *         @arg @ref LL_EXTI_EXTI_PORTF
+  *         @arg @ref LL_EXTI_EXTI_PORTG
+  *         @arg @ref LL_EXTI_EXTI_PORTH
+  *         @arg @ref LL_EXTI_EXTI_PORTN
+  *         @arg @ref LL_EXTI_EXTI_PORTO
+  *         @arg @ref LL_EXTI_EXTI_PORTP
+  *         @arg @ref LL_EXTI_EXTI_PORTQ
+  */
+__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U],
+                             (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
+}
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management
+  * @{
+  */
+
+#if defined CPU_IN_SECURE_STATE
+
+/**
+  * @brief  Enable ExtiLine Secure attribute for Lines in range 0 to 31
+  * @rmtoll SECCFGR1     SECx          LL_EXTI_EnableSecure_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SECCFGR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Secure attribute for Lines in range 32 to 63
+  * @rmtoll SECCFGR2     SECx          LL_EXTI_EnableSecure_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableSecure_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SECCFGR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Secure attribute for Lines in range 64 to 95
+  * @rmtoll SECCFGR3     SECx          LL_EXTI_EnableSecure_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableSecure_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SECCFGR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Secure attribute for Lines in range 0 to 31
+  * @rmtoll SECCFGR1     SECx          LL_EXTI_DisableSecure_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->SECCFGR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Secure attribute for Lines in range 32 to 63
+  * @rmtoll SECCFGR2     SECx          LL_EXTI_DisableSecure_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableSecure_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->SECCFGR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Secure attribute for Lines in range 64 to 95
+  * @rmtoll SECCFGR3     SECx          LL_EXTI_DisableSecure_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableSecure_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->SECCFGR3, ExtiLine);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31
+  * @rmtoll SECCFGR1     SECx          LL_EXTI_IsEnabledSecure_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Secure attribute is enabled for Lines in range 32 to 63
+  * @rmtoll SECCFGR2     SECx          LL_EXTI_IsEnabledSecure_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->SECCFGR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Secure attribute is enabled for Lines in range 64 to 95
+  * @rmtoll SECCFGR3     SECx          LL_EXTI_IsEnabledSecure_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->SECCFGR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Privilege attribute for Lines in range 0 to 31
+  * @rmtoll PRIVCFGR1    PRIVx         LL_EXTI_EnablePrivilege_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->PRIVCFGR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Privilege attribute for Lines in range 32 to 63
+  * @rmtoll PRIVCFGR2    PRIVx         LL_EXTI_EnablePrivilege_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnablePrivilege_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->PRIVCFGR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Privilege attribute for Lines in range 64 to 95
+  * @rmtoll PRIVCFGR3    PRIVx         LL_EXTI_EnablePrivilege_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnablePrivilege_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->PRIVCFGR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Privilege attribute for Lines in range 0 to 31
+  * @rmtoll PRIVCFGR1    PRIVx         LL_EXTI_DisablePrivilege_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Privilege attribute for Lines in range 32 to 63
+  * @rmtoll PRIVCFGR2    PRIVx         LL_EXTI_DisablePrivilege_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisablePrivilege_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->PRIVCFGR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Privilege attribute for Lines in range 64 to 95
+  * @rmtoll PRIVCFGR3    PRIVx         LL_EXTI_DisablePrivilege_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisablePrivilege_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->PRIVCFGR3, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31
+  * @rmtoll PRIVCFGR1    PRIVx         LL_EXTI_IsEnabledPrivilege_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Privilege attribute is enabled for Lines in range 32 to 63
+  * @rmtoll PRIVCFGR2    PRIVx         LL_EXTI_IsEnabledPrivilege_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_45
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PRIVCFGR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Privilege attribute is enabled for Lines in range 64 to 95
+  * @rmtoll PRIVCFGR3    PRIVx         LL_EXTI_IsEnabledPrivilege_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PRIVCFGR3, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined CPU_IN_SECURE_STATE
+/**
+  * @brief  Lock the secure and privilege configuration registers.
+  * @rmtoll LOCKR    LOCK     LL_EXTI_LockAttributes
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_LockAttributes(void)
+{
+  SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
+}
+
+/**
+  * @brief  Return the secure and privilege configuration registers LOCK status
+  * @rmtoll LOCKR    LOCK     LL_EXTI_GetLockAttributes
+  * @retval 1 if the secure and privilege configuration registers have been locked else 0.
+  */
+__STATIC_INLINE uint32_t LL_EXTI_GetLockAttributes(void)
+{
+  return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void     LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_EXTI_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_fmc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_fmc.h
new file mode 100644
index 000000000..d6085e94c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_fmc.h
@@ -0,0 +1,1163 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_fmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of FMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_FMC_H
+#define STM32N6xx_LL_FMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FMC_LL
+  * @{
+  */
+
+/** @addtogroup FMC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+                                       ((__BANK__) == FMC_NORSRAM_BANK2) || \
+                                       ((__BANK__) == FMC_NORSRAM_BANK3) || \
+                                       ((__BANK__) == FMC_NORSRAM_BANK4))
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+                             ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+                                   ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+                                   ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                                ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                                ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_512) || \
+                                   ((__SIZE__) == FMC_PAGE_SIZE_1024))
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+                                      ((__MODE__) == FMC_ACCESS_MODE_B) || \
+                                      ((__MODE__) == FMC_ACCESS_MODE_C) || \
+                                      ((__MODE__) == FMC_ACCESS_MODE_D))
+#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
+                                       ((__NBL__) == FMC_NBL_SETUPTIME_1) || \
+                                       ((__NBL__) == FMC_NBL_SETUPTIME_2) || \
+                                       ((__NBL__) == FMC_NBL_SETUPTIME_3))
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+                                     ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                            ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+                                               ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+                                               ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+                                         ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+                                        ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                    ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+                                       ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                            ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+
+#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK1) || \
+                                    ((__BANK__) == FMC_NAND_BANK2) || \
+                                    ((__BANK__) == FMC_NAND_BANK3) || \
+                                    ((__BANK__) == FMC_NAND_BANK4))
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
+                                          ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
+                                             ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+                                     ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+
+
+#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8)  || \
+                                          ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+                                          ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
+                                            ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
+#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE)  || \
+                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
+                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
+#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
+                                       ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
+#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
+                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
+                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
+#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE)      || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE)       || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_PALL)             || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE)        || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
+                                          ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
+#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
+                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
+                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
+#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
+#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
+#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
+#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))
+#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)
+#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
+#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
+#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \
+                                     ((__BANK__) == FMC_SDRAM_BANK2))
+#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8)  || \
+                                              ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9)  || \
+                                              ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+                                              ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
+                                        ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+                                        ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
+#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
+                                                ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
+                                         ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
+                                         ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
+
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
+  * @{
+  */
+
+#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef
+#define FMC_COMMON_TypeDef             FMC_Common_TypeDef
+#define FMC_SDRAM_TypeDef              FMC_Bank5_6_TypeDef
+
+#define FMC_NORSRAM_DEVICE             FMC_Bank1_R
+#define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E_R
+#define FMC_NAND_DEVICE                FMC_Bank3_R
+#define FMC_COMMON_DEVICE              FMC_Common_R
+#define FMC_SDRAM_DEVICE               FMC_Bank5_6_R
+
+/**
+  * @brief  FMC NORSRAM Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                 */
+
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
+                                              multiplexed on the data bus or not.
+                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/
+
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
+                                              the corresponding memory device.
+                                              This parameter can be a value of @ref FMC_Memory_Type                  */
+
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
+                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width           */
+
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
+                                              valid only with synchronous burst Flash memories.
+                                              This parameter can be a value of @ref FMC_Burst_Access_Mode            */
+
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
+                                              the Flash memory in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity         */
+
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
+                                              clock cycle before the wait state or during the wait state,
+                                              valid only when accessing memories in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Timing                  */
+
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device
+                                              by the FMC.
+                                              This parameter can be a value of @ref FMC_Write_Operation              */
+
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
+                                              signal, valid for Flash memory access in burst mode.
+                                              This parameter can be a value of @ref FMC_Wait_Signal                  */
+
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
+                                              This parameter can be a value of @ref FMC_Extended_Mode                */
+
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
+                                              valid only with asynchronous Flash memories.
+                                              This parameter can be a value of @ref FMC_AsynchronousWait             */
+
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
+                                              This parameter can be a value of @ref FMC_Write_Burst                  */
+
+  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
+                                              This parameter is only enabled through the FMC_BCR1 register,
+                                              and don't care through FMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FMC_Continous_Clock              */
+
+  uint32_t PageSize;                     /*!< Specifies the memory page size.
+                                              This parameter can be a value of @ref FMC_Page_Size                    */
+
+  uint32_t NBLSetupTime;                 /*!< Specifies the NBL setup timing clock cycle number
+                                              This parameter can be a value of @ref FMC_Byte_Lane                    */
+} FMC_NORSRAM_InitTypeDef;
+
+/**
+  * @brief  FMC NORSRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address setup time.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.   */
+
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address hold time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.   */
+
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data setup time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+                                              NOR Flash memories.                                                     */
+
+  uint32_t DataHoldTime;                 /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data hold time.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 3.
+                                              @note This parameter is used for used in asynchronous accesses.         */
+
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the bus turnaround.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is only used for multiplexed NOR Flash memories.   */
+
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and
+                                              Max_Data = 16.
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+                                              accesses.                                                               */
+
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
+                                              to the memory before getting the first data.
+                                              The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17
+                                                in NOR Flash memories with synchronous burst mode enable              */
+
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
+                                              This parameter can be a value of @ref FMC_Access_Mode                  */
+} FMC_NORSRAM_TimingTypeDef;
+
+/**
+  * @brief  FMC NAND Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
+                                        This parameter can be a value of @ref FMC_NAND_Bank                  */
+
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
+                                        This parameter can be any value of @ref FMC_Wait_feature             */
+
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
+                                        This parameter can be any value of @ref FMC_NAND_Data_Width          */
+
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
+                                        This parameter can be any value of @ref FMC_ECC                      */
+
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
+                                        This parameter can be any value of @ref FMC_ECC_Page_Size            */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+} FMC_NAND_InitTypeDef;
+
+/**
+  * @brief  FMC NAND Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
+                                      the command assertion for NAND-Flash read or write access
+                                      to common/Attribute or I/O memory space (depending on
+                                      the memory space timing to be configured).
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */
+
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
+                                      command for NAND-Flash read or write access to
+                                      common/Attribute or I/O memory space (depending on the
+                                      memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
+                                      (and data for write access) after the command de-assertion
+                                      for NAND-Flash read or write access to common/Attribute
+                                      or I/O memory space (depending on the memory space timing
+                                      to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
+                                      data bus is kept in HiZ after the start of a NAND-Flash
+                                      write access to common/Attribute or I/O memory space (depending
+                                      on the memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+} FMC_NAND_PCC_TimingTypeDef;
+
+
+/**
+  * @brief  FMC SDRAM Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t SDBank;                      /*!< Specifies the SDRAM memory device that will be used.
+                                             This parameter can be a value of @ref FMC_SDRAM_Bank                */
+
+  uint32_t ColumnBitsNumber;            /*!< Defines the number of bits of column address.
+                                             This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
+
+  uint32_t RowBitsNumber;               /*!< Defines the number of bits of column address.
+                                             This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number.    */
+
+  uint32_t MemoryDataWidth;             /*!< Defines the memory device width.
+                                             This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width.   */
+
+  uint32_t InternalBankNumber;          /*!< Defines the number of the device's internal banks.
+                                             This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number.      */
+
+  uint32_t CASLatency;                  /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
+                                             This parameter can be a value of @ref FMC_SDRAM_CAS_Latency.        */
+
+  uint32_t WriteProtection;             /*!< Enables the SDRAM device to be accessed in write mode.
+                                             This parameter can be a value of @ref FMC_SDRAM_Write_Protection.   */
+
+  uint32_t SDClockPeriod;               /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
+                                             to disable the clock before changing frequency.
+                                             This parameter can be a value of @ref FMC_SDRAM_Clock_Period.       */
+
+  uint32_t ReadPipeDelay;               /*!< Define the delay in system clock cycles on read data path.
+                                             This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay.    */
+} FMC_SDRAM_InitTypeDef;
+
+/**
+  * @brief FMC SDRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t LoadToActiveDelay;            /*!< Defines the delay between a Load Mode Register command and
+                                              an active or Refresh command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t ExitSelfRefreshDelay;         /*!< Defines the delay from releasing the self refresh command to
+                                              issuing the Activate command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t SelfRefreshTime;              /*!< Defines the minimum Self Refresh period in number of memory clock
+                                              cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RowCycleDelay;                /*!< Defines the delay between the Refresh command and the Activate command
+                                              and the delay between two consecutive Refresh commands in number of
+                                              memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t WriteRecoveryTime;            /*!< Defines the Write recovery Time in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RPDelay;                      /*!< Defines the delay between a Precharge Command and an other command
+                                              in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+
+  uint32_t RCDDelay;                     /*!< Defines the delay between the Activate Command and a Read/Write
+                                              command in number of memory clock cycles.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */
+} FMC_SDRAM_TimingTypeDef;
+
+/**
+  * @brief SDRAM command parameters structure definition
+  */
+typedef struct
+{
+  uint32_t CommandMode;                  /*!< Defines the command issued to the SDRAM device.
+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Mode.          */
+
+  uint32_t CommandTarget;                /*!< Defines which device (1 or 2) the command will be issued to.
+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Target.        */
+
+  uint32_t AutoRefreshNumber;            /*!< Defines the number of consecutive auto refresh command issued
+                                              in auto refresh mode.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15   */
+
+  uint32_t ModeRegisterDefinition;       /*!< Defines the SDRAM Mode register content                                */
+} FMC_SDRAM_CommandTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
+  * @{
+  */
+
+/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
+  * @{
+  */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+  * @{
+  */
+#define FMC_NORSRAM_BANK1                       (0x00000000U)
+#define FMC_NORSRAM_BANK2                       (0x00000002U)
+#define FMC_NORSRAM_BANK3                       (0x00000004U)
+#define FMC_NORSRAM_BANK4                       (0x00000006U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+  * @{
+  */
+#define FMC_DATA_ADDRESS_MUX_DISABLE            (0x00000000U)
+#define FMC_DATA_ADDRESS_MUX_ENABLE             (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+  * @{
+  */
+#define FMC_MEMORY_TYPE_SRAM                    (0x00000000U)
+#define FMC_MEMORY_TYPE_PSRAM                   (0x00000004U)
+#define FMC_MEMORY_TYPE_NOR                     (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
+  * @{
+  */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8             (0x00000000U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16            (0x00000010U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32            (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
+  * @{
+  */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         (0x00000040U)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+  * @{
+  */
+#define FMC_BURST_ACCESS_MODE_DISABLE           (0x00000000U)
+#define FMC_BURST_ACCESS_MODE_ENABLE            (0x00000100U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+  * @{
+  */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW            (0x00000000U)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH           (0x00000200U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+  * @{
+  */
+#define FMC_WAIT_TIMING_BEFORE_WS               (0x00000000U)
+#define FMC_WAIT_TIMING_DURING_WS               (0x00000800U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+  * @{
+  */
+#define FMC_WRITE_OPERATION_DISABLE             (0x00000000U)
+#define FMC_WRITE_OPERATION_ENABLE              (0x00001000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+  * @{
+  */
+#define FMC_WAIT_SIGNAL_DISABLE                 (0x00000000U)
+#define FMC_WAIT_SIGNAL_ENABLE                  (0x00002000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+  * @{
+  */
+#define FMC_EXTENDED_MODE_DISABLE               (0x00000000U)
+#define FMC_EXTENDED_MODE_ENABLE                (0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+  * @{
+  */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE           (0x00000000U)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE            (0x00008000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Page_Size FMC Page Size
+  * @{
+  */
+#define FMC_PAGE_SIZE_NONE                      (0x00000000U)
+#define FMC_PAGE_SIZE_128                       FMC_BCRx_CPSIZE_0
+#define FMC_PAGE_SIZE_256                       FMC_BCRx_CPSIZE_1
+#define FMC_PAGE_SIZE_512                       (FMC_BCRx_CPSIZE_0\
+                                                 | FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024                      FMC_BCRx_CPSIZE_2
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+  * @{
+  */
+#define FMC_WRITE_BURST_DISABLE                 (0x00000000U)
+#define FMC_WRITE_BURST_ENABLE                  (0x00080000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Continous_Clock FMC Continuous Clock
+  * @{
+  */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          (0x00000000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         (0x00100000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Access_Mode FMC Access Mode
+  * @{
+  */
+#define FMC_ACCESS_MODE_A                       (0x00000000U)
+#define FMC_ACCESS_MODE_B                       (0x10000000U)
+#define FMC_ACCESS_MODE_C                       (0x20000000U)
+#define FMC_ACCESS_MODE_D                       (0x30000000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
+  * @{
+  */
+#define FMC_NBL_SETUPTIME_0                     (0x00000000U)
+#define FMC_NBL_SETUPTIME_1                     (0x00400000U)
+#define FMC_NBL_SETUPTIME_2                     (0x00800000U)
+#define FMC_NBL_SETUPTIME_3                     (0x00C00000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
+  * @{
+  */
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+  * @{
+  */
+#define FMC_NAND_BANK1                          (0x00000000U)
+#define FMC_NAND_BANK2                          (0x00000400U)
+#define FMC_NAND_BANK3                          (0x00000800U)
+#define FMC_NAND_BANK4                          (0x00000C00U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+  * @{
+  */
+#define FMC_NAND_WAIT_FEATURE_DISABLE           (0x00000000U)
+#define FMC_NAND_WAIT_FEATURE_ENABLE            (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+  * @{
+  */
+#define FMC_PCR_MEMORY_TYPE_NAND                (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+  * @{
+  */
+#define FMC_NAND_MEM_BUS_WIDTH_8                (0x00000000U)
+#define FMC_NAND_MEM_BUS_WIDTH_16               (0x00000010U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC FMC ECC
+  * @{
+  */
+#define FMC_NAND_ECC_DISABLE                    (0x00000000U)
+#define FMC_NAND_ECC_ENABLE                     (0x00000040U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
+  * @{
+  */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          (0x00000000U)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          (0x00020000U)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         (0x00040000U)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         (0x00060000U)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         (0x00080000U)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         (0x000A0000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
+  * @{
+  */
+/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
+  * @{
+  */
+#define FMC_SDRAM_BANK1                         (0x00000000U)
+#define FMC_SDRAM_BANK2                         (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
+  * @{
+  */
+#define FMC_SDRAM_COLUMN_BITS_NUM_8             (0x00000000U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9             (0x00000001U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10            (0x00000002U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11            (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
+  * @{
+  */
+#define FMC_SDRAM_ROW_BITS_NUM_11               (0x00000000U)
+#define FMC_SDRAM_ROW_BITS_NUM_12               (0x00000004U)
+#define FMC_SDRAM_ROW_BITS_NUM_13               (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
+  * @{
+  */
+#define FMC_SDRAM_MEM_BUS_WIDTH_8               (0x00000000U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16              (0x00000010U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32              (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
+  * @{
+  */
+#define FMC_SDRAM_INTERN_BANKS_NUM_2            (0x00000000U)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4            (0x00000040U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
+  * @{
+  */
+#define FMC_SDRAM_CAS_LATENCY_1                 (0x00000080U)
+#define FMC_SDRAM_CAS_LATENCY_2                 (0x00000100U)
+#define FMC_SDRAM_CAS_LATENCY_3                 (0x00000180U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
+  * @{
+  */
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE      (0x00000000U)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE       (0x00000200U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
+  * @{
+  */
+#define FMC_SDRAM_CLOCK_DISABLE                 (0x00000000U)
+#define FMC_SDRAM_CLOCK_PERIOD_2                (0x00000800U)
+#define FMC_SDRAM_CLOCK_PERIOD_3                (0x00000C00U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
+  * @{
+  */
+#define FMC_SDRAM_RPIPE_DELAY_0                 (0x00000000U)
+#define FMC_SDRAM_RPIPE_DELAY_1                 (0x00002000U)
+#define FMC_SDRAM_RPIPE_DELAY_2                 (0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
+  * @{
+  */
+#define FMC_SDRAM_CMD_NORMAL_MODE               (0x00000000U)
+#define FMC_SDRAM_CMD_CLK_ENABLE                (0x00000001U)
+#define FMC_SDRAM_CMD_PALL                      (0x00000002U)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE          (0x00000003U)
+#define FMC_SDRAM_CMD_LOAD_MODE                 (0x00000004U)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE          (0x00000005U)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE            (0x00000006U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
+  * @{
+  */
+#define FMC_SDRAM_CMD_TARGET_BANK2              FMC_SDCMR_DS2
+#define FMC_SDRAM_CMD_TARGET_BANK1              FMC_SDCMR_DS1
+#define FMC_SDRAM_CMD_TARGET_BANK1_2            (FMC_SDCMR_DS2|FMC_SDCMR_DS1)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
+  * @{
+  */
+#define FMC_SDRAM_NORMAL_MODE                   (0x00000000U)
+#define FMC_SDRAM_SELF_REFRESH_MODE             FMC_SDSR_MODES1_0
+#define FMC_SDRAM_POWER_DOWN_MODE               FMC_SDSR_MODES1_1
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
+  * @{
+  */
+#define FMC_IT_RISING_EDGE                      (0x00000001U)
+#define FMC_IT_LEVEL                            (0x00000002U)
+#define FMC_IT_FALLING_EDGE                     (0x00000004U)
+#define FMC_IT_REFRESH_ERROR                    (0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
+  * @{
+  */
+#define FMC_FLAG_RISING_EDGE                    (0x00000001U)
+#define FMC_FLAG_LEVEL                          (0x00000002U)
+#define FMC_FLAG_FALLING_EDGE                   (0x00000004U)
+#define FMC_FLAG_FEMPT                          (0x00000040U)
+#define FMC_SDRAM_FLAG_REFRESH_IT               FMC_SDSR_RE
+#define FMC_SDRAM_FLAG_BUSY                     FMC_SDSR_BUSY
+#define FMC_SDRAM_FLAG_REFRESH_ERROR            FMC_SDRTR_CRE
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC_LL  Private Macros
+  * @{
+  */
+/**
+  * @brief  Enable the FMC Peripheral.
+  * @retval None
+  */
+#define __FMC_ENABLE()  (FMC_COMMON_DEVICE->CFGR |= FMC_CFGR_FMCEN)
+
+/**
+  * @brief  Disable the FMC Peripheral.
+  * @retval None
+  */
+#define __FMC_DISABLE()  (FMC_COMMON_DEVICE->CFGR &= ~FMC_CFGR_FMCEN)
+/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
+  * @brief macros to handle NOR device enable/disable and read/write operations
+  * @{
+  */
+
+/**
+  * @brief  Enable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval None
+  */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)]\
+                                                       |= FMC_BCRx_MBKEN)
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  __INSTANCE__ FMC_NORSRAM Instance
+  * @param  __BANK__ FMC_NORSRAM Bank
+  * @retval None
+  */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+                                                       &= ~FMC_BCRx_MBKEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
+  *  @brief macros to handle NAND device enable/disable
+  *  @{
+  */
+
+/**
+  * @brief  Enable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @retval None
+  */
+#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
+
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
+  * @brief macros to handle NAND interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND instance
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  __INSTANCE__  FMC_NAND Instance
+  * @param  __INTERRUPT__ FMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FMC_IT_LEVEL: Interrupt level.
+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __BANK__     FMC_NAND Bank
+  * @param  __FLAG__     FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->ISR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  __INSTANCE__ FMC_NAND Instance
+  * @param  __FLAG__     FMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval None
+  */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR |= (__FLAG__))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt
+  * @brief macros to handle SDRAM interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the SDRAM device interrupt.
+  * @param  __INSTANCE__  FMC_SDRAM instance
+  * @param  __INTERRUPT__ FMC_SDRAM interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+  * @retval None
+  */
+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDRAM device interrupt.
+  * @param  __INSTANCE__  FMC_SDRAM instance
+  * @param  __INTERRUPT__ FMC_SDRAM interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
+  * @retval None
+  */
+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the SDRAM device.
+  * @param  __INSTANCE__ FMC_SDRAM instance
+  * @param  __FLAG__     FMC_SDRAM flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
+  *            @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
+  *            @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the SDRAM device.
+  * @param  __INSTANCE__ FMC_SDRAM instance
+  * @param  __FLAG__     FMC_SDRAM flag
+  *         This parameter can be any combination of the following values:
+  *           @arg FMC_SDRAM_FLAG_REFRESH_ERROR
+  * @retval None
+  */
+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SDRTR |= (__FLAG__))
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
+  *  @{
+  */
+
+/** @defgroup FMC_LL_NORSRAM  NOR SRAM
+  *  @{
+  */
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+                                    const FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+                                           const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+                                                    const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+                                                    uint32_t ExtendedMode);
+HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+                                      FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_NAND NAND
+  *  @{
+  */
+/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                    const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                       const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+                                   uint32_t Timeout);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_LL_SDRAM SDRAM
+  *  @{
+  */
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
+                                         const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
+                                         const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
+HAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
+                                                  uint32_t AutoRefreshNumber);
+uint32_t           FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_FMC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_gpio.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_gpio.h
new file mode 100644
index 000000000..06bf32c6f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_gpio.h
@@ -0,0 +1,1537 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_gpio.h
+  * @author  GPM Application Team
+  * @brief   Header for ll_gpio.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_GPIO_H
+#define STM32N6xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPION) || defined (GPIOO) || defined (GPIOP) || defined (GPIOQ)
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
+  * which may be out of array bounds [..,UNKNOWN] in following APIs:
+  * LL_GPIO_GetAFPin_0_7
+  * LL_GPIO_SetAFPin_0_7
+  * LL_GPIO_SetAFPin_8_15
+  * LL_GPIO_GetAFPin_8_15
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function
+                              @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function
+                              @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function
+                              @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function
+                              @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function
+                              @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (LL_GPIO_PIN_0 | LL_GPIO_PIN_1  | LL_GPIO_PIN_2  | \
+                                            LL_GPIO_PIN_3  | LL_GPIO_PIN_4  | LL_GPIO_PIN_5  | \
+                                            LL_GPIO_PIN_6  | LL_GPIO_PIN_7  | LL_GPIO_PIN_8  | \
+                                            LL_GPIO_PIN_9  | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
+                                            LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
+                                            LL_GPIO_PIN_15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_DELAY Delay
+  * @{
+  */
+#define LL_GPIO_DELAY_0                       (0x0000000U) /*!< Select no delay */
+#define LL_GPIO_DELAY_300                     (0x0000001U) /*!< Select 0.3 ns   */
+#define LL_GPIO_DELAY_500                     (0x0000002U) /*!< Select 0.5 ns   */
+#define LL_GPIO_DELAY_750                     (0x0000003U) /*!< Select 0.75 ns  */
+#define LL_GPIO_DELAY_1000                    (0x0000004U) /*!< Select 1 ns     */
+#define LL_GPIO_DELAY_1250                    (0x0000005U) /*!< Select 1.25 ns  */
+#define LL_GPIO_DELAY_1500                    (0x0000006U) /*!< Select 1.5 ns   */
+#define LL_GPIO_DELAY_1750                    (0x0000007U) /*!< Select 1.75 ns  */
+#define LL_GPIO_DELAY_2000                    (0x0000008U) /*!< Select 2 ns     */
+#define LL_GPIO_DELAY_2250                    (0x0000009U) /*!< Select 2.25 ns  */
+#define LL_GPIO_DELAY_2500                    (0x000000AU) /*!< Select 2.5 ns   */
+#define LL_GPIO_DELAY_2750                    (0x000000BU) /*!< Select 2.75 ns  */
+#define LL_GPIO_DELAY_3000                    (0x000000CU) /*!< Select 3 ns     */
+#define LL_GPIO_DELAY_3250                    (0x000000DU) /*!< Select 3.25 ns  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)),
+             (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)))
+                    >> (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)),
+             (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)))
+                    >> (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)),
+             (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)))
+                    >> (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)),
+             (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)))
+                    >> (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)),
+             (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)))
+                    >> (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx)
+{
+  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Lock resource configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a security configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockResourcePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  MODIFY_REG(GPIOx->RCFGLOCKR, 0U, PinMask);
+}
+
+/**
+  * @brief  Return 1 if all resource pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsResourcePinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->RCFGLOCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Return 1 if one of the resource pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyResourcePinLocked(const GPIO_TypeDef *GPIOx)
+{
+  return ((GPIOx->RCFGLOCKR == 0x00000000U) ? 0UL : 1UL);
+}
+
+
+/**
+  * @brief  Configure gpio delay of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Delay This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_DELAY_0
+  *         @arg @ref LL_GPIO_DELAY_300
+  *         @arg @ref LL_GPIO_DELAY_500
+  *         @arg @ref LL_GPIO_DELAY_750
+  *         @arg @ref LL_GPIO_DELAY_1000
+  *         @arg @ref LL_GPIO_DELAY_1250
+  *         @arg @ref LL_GPIO_DELAY_1500
+  *         @arg @ref LL_GPIO_DELAY_1750
+  *         @arg @ref LL_GPIO_DELAY_2000
+  *         @arg @ref LL_GPIO_DELAY_2250
+  *         @arg @ref LL_GPIO_DELAY_2500
+  *         @arg @ref LL_GPIO_DELAY_2750
+  *         @arg @ref LL_GPIO_DELAY_3000
+  *         @arg @ref LL_GPIO_DELAY_3250
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetDelayPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Delay)
+{
+  MODIFY_REG(GPIOx->DELAYR[0], GPIO_DELAYRL_DLY0 << (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos),
+             (Delay << (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos)));
+}
+
+/**
+  * @brief  Return gpio delay of a dedicated pin from 0 to 7 for a dedicated port.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_DELAY_0
+  *         @arg @ref LL_GPIO_DELAY_300
+  *         @arg @ref LL_GPIO_DELAY_500
+  *         @arg @ref LL_GPIO_DELAY_750
+  *         @arg @ref LL_GPIO_DELAY_1000
+  *         @arg @ref LL_GPIO_DELAY_1250
+  *         @arg @ref LL_GPIO_DELAY_1500
+  *         @arg @ref LL_GPIO_DELAY_1750
+  *         @arg @ref LL_GPIO_DELAY_2000
+  *         @arg @ref LL_GPIO_DELAY_2250
+  *         @arg @ref LL_GPIO_DELAY_2500
+  *         @arg @ref LL_GPIO_DELAY_2750
+  *         @arg @ref LL_GPIO_DELAY_3000
+  *         @arg @ref LL_GPIO_DELAY_3250
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetDelayPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->DELAYR[0], (GPIO_DELAYRL_DLY0 << (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos)))
+                    >> (POSITION_VAL(Pin) * GPIO_DELAYRL_DLY1_Pos));
+}
+
+/**
+  * @brief  Configure gpio delay of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Delay This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_DELAY_0
+  *         @arg @ref LL_GPIO_DELAY_300
+  *         @arg @ref LL_GPIO_DELAY_500
+  *         @arg @ref LL_GPIO_DELAY_750
+  *         @arg @ref LL_GPIO_DELAY_1000
+  *         @arg @ref LL_GPIO_DELAY_1250
+  *         @arg @ref LL_GPIO_DELAY_1500
+  *         @arg @ref LL_GPIO_DELAY_1750
+  *         @arg @ref LL_GPIO_DELAY_2000
+  *         @arg @ref LL_GPIO_DELAY_2250
+  *         @arg @ref LL_GPIO_DELAY_2500
+  *         @arg @ref LL_GPIO_DELAY_2750
+  *         @arg @ref LL_GPIO_DELAY_3000
+  *         @arg @ref LL_GPIO_DELAY_3250
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetDelayPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Delay)
+{
+  MODIFY_REG(GPIOx->DELAYR[1], GPIO_DELAYRH_DLY8 << ((POSITION_VAL(Pin) & 0x07U)  * GPIO_DELAYRH_DLY9_Pos),
+             (Delay << ((POSITION_VAL(Pin) & 0x07U)  * GPIO_DELAYRH_DLY9_Pos)));
+}
+
+/**
+  * @brief  Return gpio delay of a dedicated pin from 8 to 15 for a dedicated port.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_DELAY_0
+  *         @arg @ref LL_GPIO_DELAY_300
+  *         @arg @ref LL_GPIO_DELAY_500
+  *         @arg @ref LL_GPIO_DELAY_750
+  *         @arg @ref LL_GPIO_DELAY_1000
+  *         @arg @ref LL_GPIO_DELAY_1250
+  *         @arg @ref LL_GPIO_DELAY_1500
+  *         @arg @ref LL_GPIO_DELAY_1750
+  *         @arg @ref LL_GPIO_DELAY_2000
+  *         @arg @ref LL_GPIO_DELAY_2250
+  *         @arg @ref LL_GPIO_DELAY_2500
+  *         @arg @ref LL_GPIO_DELAY_2750
+  *         @arg @ref LL_GPIO_DELAY_3000
+  *         @arg @ref LL_GPIO_DELAY_3250
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetDelayPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->DELAYR[1],
+                             (GPIO_DELAYRH_DLY8 << ((POSITION_VAL(Pin) & 0x07U) * GPIO_DELAYRH_DLY9_Pos)))
+                    >> ((POSITION_VAL(Pin) & 0x07U)  * GPIO_DELAYRH_DLY9_Pos));
+}
+
+/**
+  * @brief  Configure gpio delay of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  CfgMask:
+  *         ADVCFG[0] : Delay on ouptput path
+  *         ADVCFG[1] : input and ouptput data are double edge
+  *         ADVCFG[2] : I/O clocks are inverted
+  *         ADVCFG[3] : input and ouptput data are retimed
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPIOControlPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t CfgMask)
+{
+  MODIFY_REG(GPIOx->ADVCFGR[0], GPIO_ADVCFGRL_0 << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos),
+             (CfgMask << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos)));
+}
+
+/**
+  * @brief  Return gpio delay of a dedicated pin from 0 to 7 for a dedicated port.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         ADVCFG[0] : Delay on ouptput path
+  *         ADVCFG[1] : input and ouptput data are double edge
+  *         ADVCFG[2] : I/O clocks are inverted
+  *         ADVCFG[3] : input and ouptput data are retimed
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPIOControlPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->ADVCFGR[0],
+                             (GPIO_ADVCFGRL_0 << (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos)))
+                    >> (POSITION_VAL(Pin) * GPIO_ADVCFGRL_1_Pos));
+}
+
+/**
+  * @brief  Configure gpio delay of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  CfgMask:
+  *         ADVCFG[0] : Delay on ouptput path
+  *         ADVCFG[1] : input and ouptput data are double edge
+  *         ADVCFG[2] : I/O clocks are inverted
+  *         ADVCFG[3] : input and ouptput data are retimed
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPIOControlPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t CfgMask)
+{
+  MODIFY_REG(GPIOx->ADVCFGR[1], GPIO_ADVCFGRH_8 << ((POSITION_VAL(Pin) & 0x07U)  * GPIO_ADVCFGRH_9_Pos),
+             (CfgMask << ((POSITION_VAL(Pin) & 0x07U)  * GPIO_ADVCFGRH_9_Pos)));
+}
+
+/**
+  * @brief  Return gpio delay of a dedicated pin from 8 to 15 for a dedicated port.
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         ADVCFG[0] : Delay on ouptput path
+  *         ADVCFG[1] : input and ouptput data are double edge
+  *         ADVCFG[2] : I/O clocks are inverted
+  *         ADVCFG[3] : input and ouptput data are retimed
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPIOControlPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->ADVCFGR[1],
+                             (GPIO_ADVCFGRH_8 << ((POSITION_VAL(Pin) & 0x07U) * GPIO_ADVCFGRH_9_Pos)))
+                    >> ((POSITION_VAL(Pin) & 0x07U)  * GPIO_ADVCFGRH_9_Pos));
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  uint32_t odr = READ_REG(GPIOx->ODR);
+  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+
+#if defined CPU_IN_SECURE_STATE
+
+/**
+  * @brief  Enable secure write only access for several pin of dedicated port.
+  * @rmtoll SECCFGR      SECy           LL_GPIO_EnablePinSecure
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  SET_BIT(GPIOx->SECCFGR, PinMask);
+}
+
+
+/**
+  * @brief  Disable secure write only access for several pin of dedicated port.
+  * @rmtoll SECCFGR      SECy           LL_GPIO_DisablePinSecure
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  CLEAR_BIT(GPIOx->SECCFGR, PinMask);
+}
+
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Return if secure write only access for several pin of dedicated port is enabled or not.
+  * @rmtoll SECCFGR      SECy           LL_GPIO_IsEnabledPinSecure
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+
+
+#if defined CPU_IN_SECURE_STATE
+
+/**
+  * @brief  Enable secure write only access for several pin of dedicated port.
+  * @rmtoll SECCFGR      SECy           LL_GPIO_EnablePinPrivilege
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_EnablePinPrivilege(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  SET_BIT(GPIOx->PRIVCFGR, PinMask);
+}
+
+
+/**
+  * @brief  Disable secure write only access for several pin of dedicated port.
+  * @rmtoll SECCFGR      SECy           LL_GPIO_DisablePinPrivilege
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_DisablePinPrivilege(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  CLEAR_BIT(GPIOx->PRIVCFGR, PinMask);
+}
+
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Return if privilege write only access for several pin of dedicated port is enabled or not.
+  * @rmtoll SECCFGR      SECy           LL_GPIO_IsEnabledPinSecure
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinPrivilege(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->PRIVCFGR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, const LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPION) || defined (GPIOO) || defined (GPIOP) || defined (GPIOQ) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_GPIO_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_i2c.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_i2c.h
new file mode 100644
index 000000000..52dcb20d2
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_i2c.h
@@ -0,0 +1,2380 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_I2C_H
+#define STM32N6xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
+                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetMode(). */
+
+  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+                                     This parameter must be set by referring to the STM32CubeMX Tool and
+                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetTiming(). */
+
+  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
+
+                                     This feature can be modified afterwards using unitary functions
+                                     @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
+                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetDigitalFilter(). */
+
+  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
+                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
+
+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
+                                     match code or next received byte.
+                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_AcknowledgeNextData(). */
+
+  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
+  * @{
+  */
+#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
+#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
+#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
+#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
+#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
+#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
+#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
+#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
+  * @{
+  */
+#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
+#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
+#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
+#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
+#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
+#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
+#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
+#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
+#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
+#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
+#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
+#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
+#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
+  * @{
+  */
+#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
+#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
+#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
+#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
+#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
+#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+  * @{
+  */
+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
+#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
+                                                                         (Default address not acknowledge)        */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+  * @{
+  */
+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
+#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+  * @{
+  */
+#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+  * @{
+  */
+#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+  * @{
+  */
+#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
+#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
+#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
+                                                                         All Address2 are acknowledged.        */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+  * @{
+  */
+#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+  * @{
+  */
+#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+  * @{
+  */
+#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+  * @{
+  */
+#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
+#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+  * @{
+  */
+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
+/*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
+/*!< Generate Stop condition (Size should be set to 0).      */
+#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Restart for read request, slave 7Bit address.  */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
+                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
+/*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+  * @{
+  */
+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
+                                                                          slave enters receiver mode.  */
+#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
+                                                                          slave enters transmitter mode.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
+                                                                          transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
+                                                                          reception */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
+                                                                          SCL low level timeout.              */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
+                                                                          both SCL and SDA high level timeout.*/
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+  * @{
+  */
+#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
+#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
+                                                                                       enable bit                   */
+#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
+                                                       I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
+(extended clock) enable bits */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2C register
+  * @param  __INSTANCE__ I2C Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+  * @{
+  */
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
+  * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tscldel = (SCLDEL+1)xtpresc)
+  * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tsdadel = SDADELxtpresc)
+  * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+                            (tsclh = (SCLH+1)xtpresc)
+  * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
+                            (tscll = (SCLL+1)xtpresc)
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
+  ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
+   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
+   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
+   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
+   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C peripheral (PE = 1).
+  * @rmtoll CR1          PE            LL_I2C_Enable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Disable I2C peripheral (PE = 0).
+  * @note   When PE = 0, the I2C SCL and SDA lines are released.
+  *         Internal state machines and status bits are put back to their reset value.
+  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
+  * @rmtoll CR1          PE            LL_I2C_Disable
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+  * @brief  Check if the I2C peripheral is enabled or disabled.
+  * @rmtoll CR1          PE            LL_I2C_IsEnabled
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Noise Filters (Analog and Digital).
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         The filters can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
+  *         CR1          DNF           LL_I2C_ConfigFilters
+  * @param  I2Cx I2C Instance.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+  * @brief  Configure Digital Noise Filter.
+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
+  *         This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Get the current Digital Noise Filter configuration.
+  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+  * @brief  Enable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Disable Analog Noise Filter.
+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+  * @brief  Check if Analog Noise Filter is enabled or disabled.
+  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA transmission requests.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA transmission requests are enabled or disabled.
+  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA reception requests.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA reception requests are enabled or disabled.
+  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
+  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
+  * @param  I2Cx I2C Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TXDR register */
+    data_reg_addr = (uint32_t) &(I2Cx->TXDR);
+  }
+  else
+  {
+    /* return address of RXDR register */
+    data_reg_addr = (uint32_t) &(I2Cx->RXDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @brief  Enable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Disable Clock stretching.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+  * @brief  Check if Clock stretching is enabled or disabled.
+  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Disable hardware byte control in slave mode.
+  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
+  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Wakeup from STOP.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when Digital Filter is disabled.
+  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Disable Wakeup from STOP.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+  * @brief  Check if Wakeup from STOP is enabled or disabled.
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  *         WakeUpFromStop feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable General Call.
+  * @note   When enabled the Address 0x00 is ACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Disable General Call.
+  * @note   When disabled the Address 0x00 is NACKed.
+  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+  * @brief  Check if General Call is enabled or disabled.
+  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable I2C Fast Mode Plus (FMP = 1).
+  * @note   20mA I/O drive enable
+  * @rmtoll CR1          FMP           LL_I2C_EnableFastModePlus
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
+}
+
+/**
+  * @brief  Disable I2C Fast Mode Plus (FMP = 0).
+  * @note   20mA I/O drive disable
+  * @rmtoll CR1          FMP           LL_I2C_DisableFastModePlus
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
+}
+
+/**
+  * @brief  Check if the I2C Fast Mode Plus is enabled or disabled.
+  * @rmtoll CR1          FMP           LL_I2C_IsEnabledFastModePlus
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable automatic clear of ADDR flag.
+  * @rmtoll CR1          ADDRACLR      LL_I2C_EnableAutoClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
+}
+
+/**
+  * @brief  Disable automatic clear of ADDR flag.
+  * @rmtoll CR1          ADDRACLR      LL_I2C_DisableAutoClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
+}
+
+/**
+  * @brief  Check if the automatic clear of ADDR flag is enabled or disabled.
+  * @rmtoll CR1          ADDRACLR      LL_I2C_IsEnabledAutoClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable automatic clear of STOP flag.
+  * @rmtoll CR1          STOPFACLR     LL_I2C_EnableAutoClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
+}
+
+/**
+  * @brief  Disable automatic clear of STOP flag.
+  * @rmtoll CR1          STOPFACLR     LL_I2C_DisableAutoClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
+}
+
+/**
+  * @brief  Check if the automatic clear of STOP flag is enabled or disabled.
+  * @rmtoll CR1          STOPFACLR     LL_I2C_IsEnabledAutoClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
+  * @note   Changing this bit is not allowed, when the START bit is set.
+  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @param  AddressingMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+  * @brief  Get the Master addressing mode.
+  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+  * @brief  Set the Own Address1.
+  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
+  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+  * @param  OwnAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
+  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Disable acknowledge on Own Address1 match address.
+  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the 7bits Own Address2.
+  * @note   This action has no effect if own address2 is enabled.
+  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
+  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+  * @param  OwnAddrMask This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+  * @brief  Enable acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Disable  acknowledge on Own Address2 match address.
+  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
+  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
+  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
+  * @param  I2Cx I2C Instance.
+  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+  WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+  * @brief  Get the Timing Prescaler setting.
+  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+  * @brief  Get the SCL low period setting.
+  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+  * @brief  Get the SCL high period setting.
+  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+  * @brief  Get the SDA hold time.
+  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+  * @brief  Get the SDA setup time.
+  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+  * @brief  Configure peripheral mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
+  *         CR1          SMBDEN        LL_I2C_SetMode
+  * @param  I2Cx I2C Instance.
+  * @param  PeripheralMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+  * @brief  Get peripheral mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
+  *         CR1          SMBDEN        LL_I2C_GetMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_I2C
+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+  * @brief  Enable SMBus alert (Host or Device mode)
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is drived low and
+  *           Alert Response Address Header acknowledge is enabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Disable SMBus alert (Host or Device mode)
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   SMBus Device mode:
+  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+  *           Alert Response Address Header acknowledge is disabled.
+  *         SMBus Host mode:
+  *         - SMBus Alert pin management is not supported.
+  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SMBus Packet Error Calculation (PEC).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Disable SMBus Packet Error Calculation (PEC).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
+  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @param  TimeoutB
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+                                               uint32_t TimeoutB)
+{
+  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA setting.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+  * @brief  Set the SMBus Clock TimeoutA mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This bit can only be programmed when TimeoutA is disabled.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutAMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+  * @brief  Get the SMBus Clock TimeoutA mode.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   These bits can only be programmed when TimeoutB is disabled.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+  * @brief  Enable the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Disable the SMBus Clock Timeout.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
+  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
+  * @param  I2Cx I2C Instance.
+  * @param  ClockTimeout This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
+           (ClockTimeout)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Disable TXIS interrupt.
+  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+  * @brief  Check if the TXIS Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Disable RXNE interrupt.
+  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+  * @brief  Check if the RXNE Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Disable Address match interrupt (slave mode only).
+  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+  * @brief  Check if Address match interrupt is enabled or disabled.
+  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Disable Not acknowledge received interrupt.
+  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
+  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Disable STOP detection interrupt.
+  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+  * @brief  Check if STOP detection interrupt is enabled or disabled.
+  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable Transfer Complete interrupt.
+  * @note   Any of these events will generate interrupt :
+  *         Transfer Complete (TC)
+  *         Transfer Complete Reload (TCR)
+  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Error interrupts.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Disable Error interrupts.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   Any of these errors will generate interrupt :
+  *         Arbitration Loss (ARLO)
+  *         Bus Error detection (BERR)
+  *         Overrun/Underrun (OVR)
+  *         SMBus Timeout detection (TIMEOUT)
+  *         SMBus PEC error detection (PECERR)
+  *         SMBus Alert pin event detection (ALERT)
+  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+  * @brief  Check if Error interrupts are enabled or disabled.
+  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Indicate the status of Transmit data register empty flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transmit interrupt flag.
+  * @note   RESET: When next data is written in Transmit data register.
+  *         SET: When Transmit data register is empty.
+  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Receive data register not empty flag.
+  * @note   RESET: When Receive data register is read.
+  *         SET: When the received data is copied in Receive data register.
+  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Address matched flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When the received slave address matched with one of the enabled slave address.
+  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Not Acknowledge received flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a NACK is received after a byte transmission.
+  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Stop detection flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Stop condition is detected.
+  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Transfer complete flag (master mode).
+  * @note   RESET: Clear default value.
+  *         SET: When RELOAD=1 and NBYTES date have been transferred.
+  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Bus error flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a misplaced Start or Stop condition is detected.
+  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Arbitration lost flag.
+  * @note   RESET: Clear default value.
+  *         SET: When arbitration lost.
+  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
+  * @note   RESET: Clear default value.
+  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus PEC error flag in reception.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When the received PEC does not match with the PEC register content.
+  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus Timeout detection flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When a timeout or extended clock timeout occurs.
+  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of SMBus alert flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   RESET: Clear default value.
+  *         SET: When SMBus host configuration, SMBus alert enabled and
+  *              a falling edge event occurs on SMBA pin.
+  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of Bus Busy flag.
+  * @note   RESET: Clear default value.
+  *         SET: When a Start condition is detected.
+  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Address Matched flag.
+  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+  * @brief  Clear Not Acknowledge flag.
+  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+  * @brief  Clear Stop detection flag.
+  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+  * @brief  Clear Transmit data register empty flag (TXE).
+  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
+  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+  * @brief  Clear Bus error flag.
+  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+  * @brief  Clear Arbitration lost flag.
+  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+  * @brief  Clear Overrun/Underrun flag.
+  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+  * @brief  Clear SMBus PEC error flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+  * @brief  Clear SMBus Timeout detection flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+  * @brief  Clear SMBus Alert flag.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable automatic STOP condition generation (master mode).
+  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+  *         This bit has no effect in slave mode or when RELOAD bit is set.
+  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Disable automatic STOP condition generation (master mode).
+  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+  * @brief  Check if automatic STOP condition is enabled or disabled.
+  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable reload mode (master mode).
+  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Disable reload mode (master mode).
+  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+  * @brief  Check if reload mode is enabled or disabled.
+  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the number of bytes for transfer.
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Get the number of bytes configured for transfer.
+  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
+            or next received byte.
+  * @note   Usage in Slave mode only.
+  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
+  * @param  I2Cx I2C Instance.
+  * @param  TypeAcknowledge This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ACK
+  *         @arg @ref LL_I2C_NACK
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+  * @brief  Generate a START or RESTART condition
+  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
+  *         This action has no effect when RELOAD is set.
+  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+  * @brief  Generate a STOP condition after the current byte transfer (master mode).
+  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master sends the complete 10bit slave address read sequence :
+  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
+            in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
+  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
+  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the transfer direction (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @param  TransferRequest This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+  * @brief  Get the transfer direction requested (master mode).
+  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_REQUEST_WRITE
+  *         @arg @ref LL_I2C_REQUEST_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+  * @brief  Configure the slave address for transfer (master mode).
+  * @note   Changing these bits when START bit is set is not allowed.
+  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+  * @brief  Get the slave address programmed for transfer.
+  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
+  *         CR2          ADD10         LL_I2C_HandleTransfer\n
+  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
+  *         CR2          START         LL_I2C_HandleTransfer\n
+  *         CR2          STOP          LL_I2C_HandleTransfer\n
+  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
+  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
+  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
+  *         CR2          HEAD10R       LL_I2C_HandleTransfer
+  * @param  I2Cx I2C Instance.
+  * @param  SlaveAddr Specifies the slave address to be programmed.
+  * @param  SlaveAddrSize This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
+  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
+  * @param  TransferSize Specifies the number of bytes to be programmed.
+  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
+  * @param  EndMode This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_MODE_RELOAD
+  *         @arg @ref LL_I2C_MODE_AUTOEND
+  *         @arg @ref LL_I2C_MODE_SOFTEND
+  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+  *         @arg @ref LL_I2C_GENERATE_STOP
+  *         @arg @ref LL_I2C_GENERATE_START_READ
+  *         @arg @ref LL_I2C_GENERATE_START_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
+                             ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
+                             (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                             (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
+
+  /* update CR2 register */
+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+             (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
+             I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+             tmp);
+}
+
+/**
+  * @brief  Indicate the value of transfer direction (slave mode).
+  * @note   RESET: Write transfer, Slave enters in receiver mode.
+  *         SET: Read transfer, Slave enters in transmitter mode.
+  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
+  * @param  I2Cx I2C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2C_DIRECTION_WRITE
+  *         @arg @ref LL_I2C_DIRECTION_READ
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+  * @brief  Return the slave matched address.
+  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
+            or an Address Matched is received.
+  *         This bit has no effect when RELOAD bit is set.
+  *         This bit has no effect in device mode when SBC bit is not set.
+  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
+  * @param  I2Cx I2C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
+{
+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the SMBus Packet Error byte calculated.
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  *         SMBus feature is supported by the I2Cx Instance.
+  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
+{
+  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+  * @brief  Read Receive Data register.
+  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
+  * @param  I2Cx I2C Instance.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
+{
+  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+  * @brief  Write in Transmit Data Register .
+  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
+  * @param  I2Cx I2C Instance.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+  WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_I2C_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_i3c.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_i3c.h
new file mode 100644
index 000000000..960aa88b2
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_i3c.h
@@ -0,0 +1,4404 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_i3c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I3C LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_I3C_H
+#define STM32N6xx_LL_I3C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (I3C1) || defined (I3C2)
+
+/** @defgroup I3C_LL I3C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I3C_LL_Private_Macros I3C Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I3C_LL_ES_CONTROLLER_BUS_CONFIG_STRUCTURE_DEFINITION I3C Controller Bus Configuration Structure definition
+  * @brief    I3C LL Controller Bus Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t SDAHoldTime;         /*!< Specifies the I3C SDA hold time.
+                                     This parameter must be a value of @ref I3C_LL_EC_SDA_HOLD_TIME                   */
+
+  uint32_t WaitTime;            /*!< Specifies the time that the main and the new controllers should wait before
+                                     issuing a start.
+                                     This parameter must be a value of @ref I3C_LL_EC_OWN_ACTIVITY_STATE              */
+
+  uint8_t SCLPPLowDuration;     /*!< Specifies the I3C SCL low duration in number of kernel clock cycles
+                                     in I3C push-pull phases.
+                                     This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
+
+  uint8_t SCLI3CHighDuration;   /*!< Specifies the I3C SCL high duration in number of kernel clock cycles,
+                                     used for I3C messages for I3C open-drain and push pull phases.
+                                     This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
+
+  uint8_t SCLODLowDuration;     /*!< Specifies the I3C SCL low duration in number of kernel clock cycles in
+                                     open-drain phases, used for legacy I2C commands and for I3C open-drain phases.
+                                     This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
+
+  uint8_t SCLI2CHighDuration;   /*!< Specifies the I3C SCL high duration in number of kernel clock cycles, used
+                                     for legacy I2C commands.
+                                     This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
+
+  uint8_t BusFreeDuration;      /*!< Specifies the I3C controller duration in number of kernel clock cycles, after
+                                     a stop and before a start.
+                                     This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
+
+  uint8_t BusIdleDuration;      /*!< Specifies the I3C controller duration in number of kernel clock cycles to be
+                                     elapsed, after that both SDA and SCL are continuously high and stable
+                                     before issuing a hot-join event.
+                                     This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
+} LL_I3C_CtrlBusConfTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_ES_TARGET_BUS_CONFIG_STRUCTURE_DEFINITION I3C Target Bus Configuration Structure definition
+  * @brief    I3C LL Target Bus Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t BusAvailableDuration; /*!< Specifies the I3C target duration in number of kernel clock cycles, when
+                                     the SDA and the SCL are high for at least taval.
+                                     This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
+} LL_I3C_TgtBusConfTypeDef;
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I3C_LL_ES_INIT I3C Exported Init structure
+  * @brief    I3C LL Init Structure definition
+  * @{
+  */
+typedef struct
+{
+  LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration
+                                                        when Controller mode                                          */
+
+  LL_I3C_TgtBusConfTypeDef  TgtBusCharacteristic;  /*!< Specifies the I3C target bus characteristic configuration
+                                                        when Target mode                                              */
+
+} LL_I3C_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I3C_LL_Exported_Constants I3C Exported Constants
+  * @{
+  */
+
+/** @defgroup I3C_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_I3C_ReadReg function
+  * @{
+  */
+#define LL_I3C_EVR_CFEF                    I3C_EVR_CFEF
+#define LL_I3C_EVR_TXFEF                   I3C_EVR_TXFEF
+#define LL_I3C_EVR_CFNFF                   I3C_EVR_CFNFF
+#define LL_I3C_EVR_SFNEF                   I3C_EVR_SFNEF
+#define LL_I3C_EVR_TXFNFF                  I3C_EVR_TXFNFF
+#define LL_I3C_EVR_RXFNEF                  I3C_EVR_RXFNEF
+#define LL_I3C_EVR_RXLASTF                 I3C_EVR_RXLASTF
+#define LL_I3C_EVR_TXLASTF                 I3C_EVR_TXLASTF
+#define LL_I3C_EVR_FCF                     I3C_EVR_FCF
+#define LL_I3C_EVR_RXTGTENDF               I3C_EVR_RXTGTENDF
+#define LL_I3C_EVR_ERRF                    I3C_EVR_ERRF
+#define LL_I3C_EVR_IBIF                    I3C_EVR_IBIF
+#define LL_I3C_EVR_IBIENDF                 I3C_EVR_IBIENDF
+#define LL_I3C_EVR_CRF                     I3C_EVR_CRF
+#define LL_I3C_EVR_CRUPDF                  I3C_EVR_CRUPDF
+#define LL_I3C_EVR_HJF                     I3C_EVR_HJF
+#define LL_I3C_EVR_WKPF                    I3C_EVR_WKPF
+#define LL_I3C_EVR_GETF                    I3C_EVR_GETF
+#define LL_I3C_EVR_STAF                    I3C_EVR_STAF
+#define LL_I3C_EVR_DAUPDF                  I3C_EVR_DAUPDF
+#define LL_I3C_EVR_MWLUPDF                 I3C_EVR_MWLUPDF
+#define LL_I3C_EVR_MRLUPDF                 I3C_EVR_MRLUPDF
+#define LL_I3C_EVR_RSTF                    I3C_EVR_RSTF
+#define LL_I3C_EVR_ASUPDF                  I3C_EVR_ASUPDF
+#define LL_I3C_EVR_INTUPDF                 I3C_EVR_INTUPDF
+#define LL_I3C_EVR_DEFF                    I3C_EVR_DEFF
+#define LL_I3C_EVR_GRPF                    I3C_EVR_GRPF
+#define LL_I3C_SER_PERR                    I3C_SER_PERR
+#define LL_I3C_SER_STALL                   I3C_SER_STALL
+#define LL_I3C_SER_DOVR                    I3C_SER_DOVR
+#define LL_I3C_SER_COVR                    I3C_SER_COVR
+#define LL_I3C_SER_ANACK                   I3C_SER_ANACK
+#define LL_I3C_SER_DNACK                   I3C_SER_DNACK
+#define LL_I3C_SER_DERR                    I3C_SER_DERR
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_I3C_ReadReg and  LL_I3C_WriteReg functions
+  * @{
+  */
+#define LL_I3C_IER_CFNFIE                  I3C_IER_CFNFIE
+#define LL_I3C_IER_SFNEIE                  I3C_IER_SFNEIE
+#define LL_I3C_IER_TXFNFIE                 I3C_IER_TXFNFIE
+#define LL_I3C_IER_RXFNEIE                 I3C_IER_RXFNEIE
+#define LL_I3C_IER_FCIE                    I3C_IER_FCIE
+#define LL_I3C_IER_RXTGTENDIE              I3C_IER_RXTGTENDIE
+#define LL_I3C_IER_ERRIE                   I3C_IER_ERRIE
+#define LL_I3C_IER_IBIIE                   I3C_IER_IBIIE
+#define LL_I3C_IER_IBIENDIE                I3C_IER_IBIENDIE
+#define LL_I3C_IER_CRIE                    I3C_IER_CRIE
+#define LL_I3C_IER_CRUPDIE                 I3C_IER_CRUPDIE
+#define LL_I3C_IER_HJIE                    I3C_IER_HJIE
+#define LL_I3C_IER_WKPIE                   I3C_IER_WKPIE
+#define LL_I3C_IER_GETIE                   I3C_IER_GETIE
+#define LL_I3C_IER_STAIE                   I3C_IER_STAIE
+#define LL_I3C_IER_DAUPDIE                 I3C_IER_DAUPDIE
+#define LL_I3C_IER_MWLUPDIE                I3C_IER_MWLUPDIE
+#define LL_I3C_IER_MRLUPDIE                I3C_IER_MRLUPDIE
+#define LL_I3C_IER_RSTIE                   I3C_IER_RSTIE
+#define LL_I3C_IER_ASUPDIE                 I3C_IER_ASUPDIE
+#define LL_I3C_IER_INTUPDIE                I3C_IER_INTUPDIE
+#define LL_I3C_IER_DEFIE                   I3C_IER_DEFIE
+#define LL_I3C_IER_GRPIE                   I3C_IER_GRPIE
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_MODE MODE
+  * @{
+  */
+#define LL_I3C_MODE_CONTROLLER              I3C_CFGR_CRINIT         /*!< I3C Controller mode */
+#define LL_I3C_MODE_TARGET                  0x00000000U             /*!< I3C Target (Controller capable) mode */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE   0x00000000U              /*!< Get address of data register used
+                                                                          for transmission in Byte */
+#define LL_I3C_DMA_REG_DATA_RECEIVE_BYTE    0x00000001U              /*!< Get address of data register used
+                                                                          for reception in Byte */
+#define LL_I3C_DMA_REG_DATA_TRANSMIT_WORD   0x00000002U              /*!< Get address of data register used for
+                                                                          transmission in Word */
+#define LL_I3C_DMA_REG_DATA_RECEIVE_WORD    0x00000003U              /*!< Get address of data register used
+                                                                          for reception in Word */
+#define LL_I3C_DMA_REG_STATUS               0x00000004U              /*!< Get address of status register used
+                                                                          for transfer status in Word */
+#define LL_I3C_DMA_REG_CONTROL              0x00000005U              /*!< Get address of control register used
+                                                                          for transfer control in Word */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_RX_THRESHOLD RX THRESHOLD
+  * @{
+  */
+#define LL_I3C_RXFIFO_THRESHOLD_1_4         0x00000000U
+/*!< Rx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */
+#define LL_I3C_RXFIFO_THRESHOLD_4_4         I3C_CFGR_RXTHRES
+/*!< Rx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_TX_THRESHOLD TX THRESHOLD
+  * @{
+  */
+#define LL_I3C_TXFIFO_THRESHOLD_1_4         0x00000000U
+/*!< Tx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */
+#define LL_I3C_TXFIFO_THRESHOLD_4_4         I3C_CFGR_TXTHRES
+/*!< Tx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_PAYLOAD PAYLOAD
+  * @{
+  */
+#define LL_I3C_PAYLOAD_EMPTY               0x00000000U
+/*!< Empty payload, no additional data after IBI acknowledge */
+#define LL_I3C_PAYLOAD_1_BYTE              I3C_MAXRLR_IBIP_0
+/*!< One additional data byte after IBI acknowledge */
+#define LL_I3C_PAYLOAD_2_BYTES             I3C_MAXRLR_IBIP_1
+/*!< Two additional data bytes after IBI acknowledge */
+#define LL_I3C_PAYLOAD_3_BYTES             (I3C_MAXRLR_IBIP_1 | I3C_MAXRLR_IBIP_0)
+/*!< Three additional data bytes after IBI acknowledge */
+#define LL_I3C_PAYLOAD_4_BYTES             I3C_MAXRLR_IBIP_2
+/*!< Four additional data bytes after IBI acknowledge */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_SDA_HOLD_TIME SDA HOLD TIME 0
+  * @{
+  */
+#define LL_I3C_SDA_HOLD_TIME_0_5           0x00000000U               /*!< SDA hold time is 0.5 x ti3cclk */
+#define LL_I3C_SDA_HOLD_TIME_1_5           I3C_TIMINGR1_SDA_HD       /*!< SDA hold time is 1.5 x ti3cclk */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_OWN_ACTIVITY_STATE OWN ACTIVITY STATE
+  * @{
+  */
+#define LL_I3C_OWN_ACTIVITY_STATE_0        0x00000000U
+/*!< Own Controller Activity state 0 */
+#define LL_I3C_OWN_ACTIVITY_STATE_1        I3C_TIMINGR1_ASNCR_0
+/*!< Own Controller Activity state 1 */
+#define LL_I3C_OWN_ACTIVITY_STATE_2        I3C_TIMINGR1_ASNCR_1
+/*!< Own Controller Activity state 2 */
+#define LL_I3C_OWN_ACTIVITY_STATE_3        (I3C_TIMINGR1_ASNCR_1 | I3C_TIMINGR1_ASNCR_0)
+/*!< Own Controller Activity state 3 */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_DEVICE_ROLE_AS DEVICE ROLE AS
+  * @{
+  */
+#define LL_I3C_DEVICE_ROLE_AS_TARGET        0x00000000U              /*!< I3C Target */
+#define LL_I3C_DEVICE_ROLE_AS_CONTROLLER    I3C_BCR_BCR6             /*!< I3C Controller */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_IBI_NO_ADDITIONAL IBI NO ADDITIONAL
+  * @{
+  */
+#define LL_I3C_IBI_NO_ADDITIONAL_DATA      0x00000000U               /*!< No data byte follows the accepted IBI */
+#define LL_I3C_IBI_ADDITIONAL_DATA         I3C_BCR_BCR2              /*!< A Mandatory Data Byte (MDB)
+                                                                          follows the accepted IBI */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_MAX_DATA_SPEED_LIMITATION MAX DATA SPEED LIMITATION
+  * @{
+  */
+#define LL_I3C_NO_DATA_SPEED_LIMITATION    0x00000000U               /*!< No max data speed limitation */
+#define LL_I3C_MAX_DATA_SPEED_LIMITATION   I3C_BCR_BCR0              /*!< Max data speed limitation */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_IBI_MDB_READ_NOTIFICATION IBI MDB READ NOTIFICATION
+  * @{
+  */
+#define LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION  0x00000000U
+/*!< No support of pending read notification via the IBI MDB[7:0] value */
+#define LL_I3C_MDB_PENDING_READ_NOTIFICATION     I3C_GETCAPR_CAPPEND
+/*!< Support of pending read notification via the IBI MDB[7:0] value    */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_HANDOFF_GRP_ADDR_NOT HANDOFF GRP ADDR NOT
+  * @{
+  */
+#define LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED 0x00000000U            /*!< Group Address Handoff is not supported */
+#define LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED     I3C_CRCAPR_CAPGRP      /*!< Group Address Handoff is supported     */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_HANDOFF HANDOFF
+  * @{
+  */
+#define LL_I3C_HANDOFF_NOT_DELAYED         0x00000000U
+/*!< Additional time to process controllership handoff is not needed */
+#define LL_I3C_HANDOFF_DELAYED             I3C_CRCAPR_CAPDHOFF
+/*!< Additional time to process controllership handoff is needed */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE
+  * @{
+  */
+#define LL_I3C_HANDOFF_ACTIVITY_STATE_0    0x00000000U
+/*!< Indicates that will act according to Activity State 0 after controllership handoff */
+#define LL_I3C_HANDOFF_ACTIVITY_STATE_1    I3C_GETMXDSR_HOFFAS_0
+/*!< Indicates that will act according to Activity State 1 after controllership handoff */
+#define LL_I3C_HANDOFF_ACTIVITY_STATE_2    I3C_GETMXDSR_HOFFAS_1
+/*!< Indicates that will act according to Activity State 2 after controllership handoff */
+#define LL_I3C_HANDOFF_ACTIVITY_STATE_3    (I3C_GETMXDSR_HOFFAS_1 | I3C_GETMXDSR_HOFFAS_0)
+/*!< Indicates that will act according to Activity State 3 after controllership handoff */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_GETMXDS_FORMAT GETMXDS FORMAT
+  * @{
+  */
+#define LL_I3C_GETMXDS_FORMAT_1            0x00000000U
+/*!< GETMXDS CCC Format 1 is used, no MaxRdTurn field in response */
+#define LL_I3C_GETMXDS_FORMAT_2_LSB        I3C_GETMXDSR_FMT_0
+/*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, LSB = RDTURN[7:0] */
+#define LL_I3C_GETMXDS_FORMAT_2_MID        I3C_GETMXDSR_FMT_1
+/*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, Middle byte = RDTURN[7:0] */
+#define LL_I3C_GETMXDS_FORMAT_2_MSB        (I3C_GETMXDSR_FMT_1 | I3C_GETMXDSR_FMT_0)
+/*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, MSB = RDTURN[7:0] */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_GETMXDS_TSCO GETMXDS TSCO
+  * @{
+  */
+#define LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS     0x00000000U         /*!< clock-to-data turnaround time tSCO <= 12ns */
+#define LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS  I3C_GETMXDSR_TSCO   /*!< clock-to-data turnaround time tSCO > 12ns  */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_BUS_ACTIVITY_STATE BUS ACTIVITY STATE
+  * @{
+  */
+#define LL_I3C_BUS_ACTIVITY_STATE_0        0x00000000U
+/*!< Controller on the Bus Activity State 0 */
+#define LL_I3C_BUS_ACTIVITY_STATE_1        I3C_DEVR0_AS_0
+/*!< Controller on the Bus Activity State 1 */
+#define LL_I3C_BUS_ACTIVITY_STATE_2        I3C_DEVR0_AS_1
+/*!< Controller on the Bus Activity State 2 */
+#define LL_I3C_BUS_ACTIVITY_STATE_3        (I3C_DEVR0_AS_1 | I3C_DEVR0_AS_0)
+/*!< Controller on the Bus Activity State 3 */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_RESET_ACTION RESET ACTION
+  * @{
+  */
+#define LL_I3C_RESET_ACTION_NONE           0x00000000U
+/*!< No Reset Action Required */
+#define LL_I3C_RESET_ACTION_PARTIAL        I3C_DEVR0_RSTACT_0
+/*!< Reset of some internal registers of the peripheral*/
+#define LL_I3C_RESET_ACTION_FULL           I3C_DEVR0_RSTACT_1
+/*!< Reset all internal registers of the peripheral */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_DIRECTION DIRECTION
+  * @{
+  */
+#define LL_I3C_DIRECTION_WRITE             0x00000000U               /*!< Write transfer      */
+#define LL_I3C_DIRECTION_READ              I3C_CR_RNW                /*!< Read transfer       */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_GENERATE GENERATE
+  * @{
+  */
+#define LL_I3C_GENERATE_STOP               I3C_CR_MEND
+/*!< Generate Stop condition after sending a message */
+#define LL_I3C_GENERATE_RESTART            0x00000000U
+/*!< Generate Restart condition after sending a message */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_CONTROLLER_MTYPE CONTROLLER MTYPE
+  * @{
+  */
+#define LL_I3C_CONTROLLER_MTYPE_RELEASE        0x00000000U
+/*!< SCL output clock stops running until next instruction executed       */
+#define LL_I3C_CONTROLLER_MTYPE_HEADER         I3C_CR_MTYPE_0
+/*!< Header Message */
+#define LL_I3C_CONTROLLER_MTYPE_PRIVATE        I3C_CR_MTYPE_1
+/*!< Private Message Type */
+#define LL_I3C_CONTROLLER_MTYPE_DIRECT         (I3C_CR_MTYPE_1 | I3C_CR_MTYPE_0)
+/*!< Direct Message Type */
+#define LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C     I3C_CR_MTYPE_2
+/*!< Legacy I2C Message Type */
+#define LL_I3C_CONTROLLER_MTYPE_CCC            (I3C_CR_MTYPE_2 | I3C_CR_MTYPE_1)
+/*!< Common Command Code */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_TARGET_MTYPE_HOT TARGET MTYPE HOT
+  * @{
+  */
+#define LL_I3C_TARGET_MTYPE_HOT_JOIN            I3C_CR_MTYPE_3                     /*!< Hot Join*/
+#define LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_0)  /*!< Controller-role Request */
+#define LL_I3C_TARGET_MTYPE_IBI                 (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_1)  /*!< In Band Interrupt (IBI) */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_MESSAGE MESSAGE
+  * @{
+  */
+#define LL_I3C_MESSAGE_ERROR               0x00000000U               /*!< An error has been detected in the message */
+#define LL_I3C_MESSAGE_SUCCESS             I3C_SR_OK                 /*!< The message ended with success       */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_MESSAGE_DIRECTION MESSAGE DIRECTION
+  * @{
+  */
+#define LL_I3C_MESSAGE_DIRECTION_WRITE     0x00000000U               /*!< Write data or command      */
+#define LL_I3C_MESSAGE_DIRECTION_READ      I3C_SR_DIR                /*!< Read data       */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_CONTROLLER_ERROR CONTROLLER ERROR
+  * @{
+  */
+#define LL_I3C_CONTROLLER_ERROR_CE0        0x00000000U
+/*!< Controller detected an illegally formatted CCC    */
+#define LL_I3C_CONTROLLER_ERROR_CE1        I3C_SER_CODERR_0
+/*!< Controller detected that transmitted data on the bus is different than expected    */
+#define LL_I3C_CONTROLLER_ERROR_CE2        I3C_SER_CODERR_1
+/*!< Controller detected that broadcast address 7'h7E has been nacked    */
+#define LL_I3C_CONTROLLER_ERROR_CE3        (I3C_SER_CODERR_1 | I3C_SER_CODERR_0)
+/*!< Controller detected that new Controller did not drive the bus after Controller-role handoff    */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_TARGET_ERROR TARGET ERROR
+  * @{
+  */
+#define LL_I3C_TARGET_ERROR_TE0            I3C_SER_CODERR_3
+/*!< Target detected an invalid broadcast address    */
+#define LL_I3C_TARGET_ERROR_TE1            (I3C_SER_CODERR_3  | I3C_SER_CODERR_0)
+/*!< Target detected an invalid CCC Code    */
+#define LL_I3C_TARGET_ERROR_TE2            (I3C_SER_CODERR_3  | I3C_SER_CODERR_1)
+/*!< Target detected an invalid write data    */
+#define LL_I3C_TARGET_ERROR_TE3            (I3C_SER_CODERR_3  | I3C_SER_CODERR_1 | I3C_SER_CODERR_0)
+/*!< Target detected an invalid assigned address during Dynamic Address Assignment procedure    */
+#define LL_I3C_TARGET_ERROR_TE4            (I3C_SER_CODERR_3  | I3C_SER_CODERR_2)
+/*!< Target detected 7'h7E missing after Restart during Dynamic Address Assignment procedure    */
+#define LL_I3C_TARGET_ERROR_TE5            (I3C_SER_CODERR_3  | I3C_SER_CODERR_2 | I3C_SER_CODERR_0)
+/*!< Target detected an illegally formatted CCC     */
+#define LL_I3C_TARGET_ERROR_TE6            (I3C_SER_CODERR_3  | I3C_SER_CODERR_2 | I3C_SER_CODERR_1)
+/*!< Target detected that transmitted data on the bus is different than expected     */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD
+  * @{
+  */
+#define LL_I3C_BCR_IN_PAYLOAD_SHIFT        48  /*!< BCR field in target payload */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_IBI_CAPABILITY IBI CAPABILITY
+  * @{
+  */
+#define LL_I3C_IBI_CAPABILITY              I3C_DEVRX_IBIACK
+/*!< Controller acknowledge Target In Band Interrupt capable */
+#define LL_I3C_IBI_NO_CAPABILITY           0x00000000U
+/*!< Controller no acknowledge Target In Band Interrupt capable */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_IBI_ADDITIONAL_DATA IBI ADDITIONAL DATA
+  * @{
+  */
+#define LL_I3C_IBI_DATA_ENABLE             I3C_DEVRX_IBIDEN
+/*!< A mandatory data byte follows the IBI acknowledgement */
+#define LL_I3C_IBI_DATA_DISABLE            0x00000000U
+/*!< No mandatory data byte follows the IBI acknowledgement */
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EC_CR_CAPABILITY CR CAPABILITY
+  * @{
+  */
+#define LL_I3C_CR_CAPABILITY               I3C_DEVRX_CRACK
+/*!< Controller acknowledge Target Controller Role capable */
+#define LL_I3C_CR_NO_CAPABILITY            0x00000000U
+/*!< Controller no acknowledge Target Controller Role capable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I3C_LL_Exported_Macros I3C Exported Macros
+  * @{
+  */
+
+/** @defgroup I3C_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/** @brief  Get Bus Characterics in payload (64bits) receive during ENTDAA procedure.
+  * @param  __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF.
+  * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF.
+  */
+#define LL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> LL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \
+                                     I3C_BCR_BCR)
+
+/** @brief  Check IBI request capabilities.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval Value of @ref I3C_LL_EC_IBI_CAPABILITY.
+  */
+#define LL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \
+                                         ? LL_I3C_IBI_CAPABILITY : LL_I3C_IBI_NO_CAPABILITY)
+
+/** @brief  Check IBI additional data byte capabilities.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval Value of @ref I3C_LL_EC_IBI_ADDITIONAL_DATA.
+  */
+#define LL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \
+                                         ? LL_I3C_IBI_DATA_ENABLE : LL_I3C_IBI_DATA_DISABLE)
+
+/** @brief  Check Controller role request capabilities.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval Value of @ref I3C_LL_EC_CR_CAPABILITY.
+  */
+#define LL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \
+                                        ? LL_I3C_CR_CAPABILITY : LL_I3C_CR_NO_CAPABILITY)
+
+/**
+  * @brief  Write a value in I3C register
+  * @param  __INSTANCE__ I3C Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I3C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I3C register
+  * @param  __INSTANCE__ I3C Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I3C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I3C_LL_Exported_Functions I3C Exported Functions
+  * @{
+  */
+
+/** @defgroup I3C_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable I3C peripheral (EN = 1).
+  * @rmtoll CFGR      EN            LL_I3C_Enable
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_Enable(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_EN);
+}
+
+/**
+  * @brief  Disable I3C peripheral (EN = 0).
+  * @note   Controller mode: before clearing EN, all possible target requests must be disabled using DISEC CCC.
+  *         Target mode: software is not expected clearing EN unless a partial reset of the IP is needed
+  * @rmtoll CFGR      EN            LL_I3C_Disable
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_Disable(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EN);
+}
+
+/**
+  * @brief  Check if the I3C peripheral is enabled or disabled.
+  * @rmtoll CFGR      EN            LL_I3C_IsEnabled
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabled(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EN) == (I3C_CFGR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Reset action is required or not required.
+  * @note   This bit indicates if Reset Action field has been updated by HW upon reception
+  *         of RSTACT during current frame.
+  * @rmtoll DEVR0        RSTVAL        LL_I3C_IsEnabledReset
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledReset(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTVAL) == (I3C_DEVR0_RSTVAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure peripheral mode.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll CFGR      CRINIT       LL_I3C_SetMode
+  * @param  I3Cx I3C Instance.
+  * @param  PeripheralMode This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_MODE_CONTROLLER
+  *         @arg @ref LL_I3C_MODE_TARGET
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetMode(I3C_TypeDef *I3Cx, uint32_t PeripheralMode)
+{
+  MODIFY_REG(I3Cx->CFGR, I3C_CFGR_CRINIT, PeripheralMode);
+}
+
+/**
+  * @brief  Get peripheral mode.
+  * @rmtoll CFGR      CRINIT       LL_I3C_GetMode
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_MODE_CONTROLLER
+  *         @arg @ref LL_I3C_MODE_TARGET
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMode(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)((READ_BIT(I3Cx->CFGR, I3C_CFGR_CRINIT) == (I3C_CFGR_CRINIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  An arbitration header (7'h7E) is sent after Start in case of legacy I2C or I3C private transfers.
+  * @note   This bit can be modified only when there is no frame ongoing
+  * @rmtoll CFGR      NOARBH        LL_I3C_EnableArbitrationHeader
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableArbitrationHeader(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH);
+}
+
+/**
+  * @brief  Target address is sent directly after a Start in case of legacy I2C or I3C private transfers.
+  * @note   This bit can be modified only when there is no frame ongoing
+  * @rmtoll CFGR      NOARBH        LL_I3C_DisableArbitrationHeader
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableArbitrationHeader(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH);
+}
+
+/**
+  * @brief  Check if the arbitration header is enabled of disabled.
+  * @rmtoll CFGR      NOARBH        LL_I3C_IsEnabledArbitrationHeader
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH) == (I3C_CFGR_NOARBH)) ? 0UL : 1UL);
+}
+
+/**
+  * @brief  A Reset Pattern is inserted before the STOP at the end of a frame when the last CCC
+  *         of the frame was RSTACT CCC.
+  * @note   This bit can be modified only when there is no frame ongoing
+  * @rmtoll CFGR      RSTPTRN       LL_I3C_EnableResetPattern
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableResetPattern(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN);
+}
+
+/**
+  * @brief  A single STOP is emitted at the end of a frame.
+  * @note   This bit can be modified only when there is no frame ongoing
+  * @rmtoll CFGR      RSTPTRN       LL_I3C_DisableResetPattern
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableResetPattern(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN);
+}
+
+/**
+  * @brief  Check if Reset Pattern is enabled of disabled.
+  * @rmtoll CFGR      RSTPTRN       LL_I3C_IsEnabledResetPattern
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledResetPattern(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN) == (I3C_CFGR_RSTPTRN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  An Exit Pattern is sent after header (MTYPE = header) to program an escalation fault.
+  * @note   This bit can be modified only when there is no frame ongoing
+  * @rmtoll CFGR      EXITPTRN      LL_I3C_EnableExitPattern
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableExitPattern(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN);
+}
+
+/**
+  * @brief  An Exit Pattern is not sent after header (MTYPE = header).
+  * @note   This bit can be modified only when there is no frame ongoing
+  * @rmtoll CFGR      EXITPTRN      LL_I3C_DisableExitPattern
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableExitPattern(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN);
+}
+
+/**
+  * @brief  Check if Exit Pattern is enabled or disabled.
+  * @rmtoll CFGR      EXITPTRN      LL_I3C_IsEnabledExitPattern
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledExitPattern(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN) == (I3C_CFGR_EXITPTRN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  High Keeper is enabled and will be used in place of standard Open drain Pull Up device
+  *         during handoff procedures.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll CFGR      HKSDAEN       LL_I3C_EnableHighKeeperSDA
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableHighKeeperSDA(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN);
+}
+
+/**
+  * @brief  High Keeper is disabled.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll CFGR      HKSDAEN       LL_I3C_DisableHighKeeperSDA
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableHighKeeperSDA(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN);
+}
+
+/**
+  * @brief  Check if High Keeper is enabled or disabled.
+  * @rmtoll CFGR      HKSDAEN       LL_I3C_IsEnabledHighKeeperSDA
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledHighKeeperSDA(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN) == (I3C_CFGR_HKSDAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Hot Join Request is Acked. Current frame on the bus is continued.
+  *         An Hot Join interrupt is sent through HJF flag.
+  * @note   This bit can be used when I3C is acting as a Controller.
+  * @rmtoll CFGR      HJACK         LL_I3C_EnableHJAck
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableHJAck(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_HJACK);
+}
+
+/**
+  * @brief  Hot Join Request is Nacked. Current frame on the bus is continued.
+  *         No Hot Join interrupt is generated.
+  * @note   This bit can be used when I3C is acting as a Controller.
+  * @rmtoll CFGR      HJACK         LL_I3C_DisableHJAck
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableHJAck(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HJACK);
+}
+
+/**
+  * @brief  Check if Hot Join Request Acknowledgement is enabled or disabled.
+  * @rmtoll CFGR      HJACK         LL_I3C_IsEnabledHJAck
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledHJAck(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HJACK) == (I3C_CFGR_HJACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TDR          TDB0         LL_I3C_DMA_GetRegAddr\n
+  *         TDWR         TDWR          LL_I3C_DMA_GetRegAddr\n
+  *         RDR          RXRB0         LL_I3C_DMA_GetRegAddr\n
+  *         RDWR         RDWR          LL_I3C_DMA_GetRegAddr\n
+  *         SR           SR            LL_I3C_DMA_GetRegAddr\n
+  *         CR           CR            LL_I3C_DMA_GetRegAddr
+  * @param  I3Cx I3C Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE
+  *         @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_BYTE
+  *         @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_WORD
+  *         @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_WORD
+  *         @arg @ref LL_I3C_DMA_REG_STATUS
+  *         @arg @ref LL_I3C_DMA_REG_CONTROL
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_I3C_DMA_GetRegAddr(const I3C_TypeDef *I3Cx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr;
+
+  if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(I3Cx->TDR);
+  }
+  else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_BYTE)
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(I3Cx->RDR);
+  }
+  else if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_WORD)
+  {
+    /* return address of TDWR register */
+    data_reg_addr = (uint32_t) &(I3Cx->TDWR);
+  }
+  else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_WORD)
+  {
+    /* return address of RDWR register */
+    data_reg_addr = (uint32_t) &(I3Cx->RDWR);
+  }
+  else if (Direction == LL_I3C_DMA_REG_STATUS)
+  {
+    /* return address of SR register */
+    data_reg_addr = (uint32_t) &(I3Cx->SR);
+  }
+  else
+  {
+    /* return address of CR register */
+    data_reg_addr = (uint32_t) &(I3Cx->CR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @brief  Enable DMA FIFO reception requests.
+  * @rmtoll CFGR      RXDMAEN       LL_I3C_EnableDMAReq_RX
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableDMAReq_RX(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA FIFO reception requests.
+  * @rmtoll CFGR      RXDMAEN       LL_I3C_DisableDMAReq_RX
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableDMAReq_RX(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA FIFO reception requests are enabled or disabled.
+  * @rmtoll CFGR      RXDMAEN       LL_I3C_IsEnabledDMAReq_RX
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_RX(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN) == (I3C_CFGR_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Receive FIFO Threshold level.
+  * @rmtoll CFGR      RXTHRES       LL_I3C_SetRxFIFOThreshold
+  * @param  I3Cx I3C Instance.
+  * @param  RxFIFOThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4
+  *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetRxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t RxFIFOThreshold)
+{
+  MODIFY_REG(I3Cx->CFGR, I3C_CFGR_RXTHRES, RxFIFOThreshold);
+}
+
+/**
+  * @brief  Get the Receive FIFO Threshold level.
+  * @rmtoll CFGR      RXTHRES       LL_I3C_GetRxFIFOThreshold
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4
+  *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetRxFIFOThreshold(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_RXTHRES));
+}
+
+/**
+  * @brief  Enable DMA FIFO transmission requests.
+  * @rmtoll CFGR      TXDMAEN       LL_I3C_EnableDMAReq_TX
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableDMAReq_TX(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA FIFO transmission requests.
+  * @rmtoll CFGR      TXDMAEN       LL_I3C_DisableDMAReq_TX
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableDMAReq_TX(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA FIFO transmission requests are enabled or disabled.
+  * @rmtoll CFGR      TXDMAEN       LL_I3C_IsEnabledDMAReq_TX
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_TX(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN) == (I3C_CFGR_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Transmit FIFO Threshold level.
+  * @rmtoll CFGR      TXTHRES       LL_I3C_SetTxFIFOThreshold
+  * @param  I3Cx I3C Instance.
+  * @param  TxFIFOThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4
+  *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetTxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t TxFIFOThreshold)
+{
+  MODIFY_REG(I3Cx->CFGR, I3C_CFGR_TXTHRES, TxFIFOThreshold);
+}
+
+/**
+  * @brief  Get the Transmit FIFO Threshold level.
+  * @rmtoll CFGR      TXTHRES       LL_I3C_GetTxFIFOThreshold
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4
+  *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetTxFIFOThreshold(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_TXTHRES));
+}
+
+/**
+  * @brief  Enable DMA FIFO Status requests.
+  * @rmtoll CFGR      SDMAEN        LL_I3C_EnableDMAReq_Status
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableDMAReq_Status(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN);
+}
+
+/**
+  * @brief  Disable DMA FIFO Status requests.
+  * @rmtoll CFGR      SDMAEN        LL_I3C_DisableDMAReq_Status
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableDMAReq_Status(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN);
+}
+
+/**
+  * @brief  Check if DMA FIFO Status requests are enabled or disabled.
+  * @rmtoll CFGR      SDMAEN        LL_I3C_IsEnabledDMAReq_Status
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Status(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN) == (I3C_CFGR_SDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Status FIFO.
+  * @note   Not applicable in target mode. Status FIFO always disabled in target mode.
+  * @rmtoll CFGR      SMODE         LL_I3C_EnableStatusFIFO
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableStatusFIFO(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_SMODE);
+}
+
+/**
+  * @brief  Disable the Status FIFO Threshold.
+  * @rmtoll CFGR      SMODE         LL_I3C_DisableStatusFIFO
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableStatusFIFO(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SMODE);
+}
+
+/**
+  * @brief  Check if the Status FIFO Threshold is enabled or disabled.
+  * @rmtoll CFGR      SMODE         LL_I3C_IsEnabledStatusFIFO
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledStatusFIFO(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SMODE) == (I3C_CFGR_SMODE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus.
+  * @note   Not applicable in target mode. Control FIFO always disabled in target mode.
+  * @rmtoll CFGR      TMODE         LL_I3C_EnableControlFIFO
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableControlFIFO(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_TMODE);
+}
+
+/**
+  * @brief  Disable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus.
+  * @rmtoll CFGR      TMODE         LL_I3C_DisableControlFIFO
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableControlFIFO(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TMODE);
+}
+
+/**
+  * @brief  Check if the Control and Transmit FIFO preloaded is enabled or disabled.
+  * @rmtoll CFGR      TMODE         LL_I3C_IsEnabledControlFIFO
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledControlFIFO(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TMODE) == (I3C_CFGR_TMODE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA FIFO Control word transfer requests.
+  * @rmtoll CFGR      CDMAEN        LL_I3C_EnableDMAReq_Control
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableDMAReq_Control(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN);
+}
+
+/**
+  * @brief  Disable DMA FIFO Control word transfer requests.
+  * @rmtoll CFGR      CDMAEN        LL_I3C_DisableDMAReq_Control
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableDMAReq_Control(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN);
+}
+
+/**
+  * @brief  Check if DMA FIFO Control word transfer requests are enabled or disabled.
+  * @rmtoll CFGR      CDMAEN        LL_I3C_IsEnabledDMAReq_Control
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Control(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN) == (I3C_CFGR_CDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Own Dynamic Address as Valid.
+  * @rmtoll DEVR0        DAVAL         LL_I3C_EnableOwnDynAddress
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableOwnDynAddress(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL);
+}
+
+/**
+  * @brief  Set Own Dynamic Address as Not-Valid.
+  * @rmtoll DEVR0        DAVAL         LL_I3C_DisableOwnDynAddress
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableOwnDynAddress(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL);
+}
+
+/**
+  * @brief  Check if Own Dynamic address is Valid or Not-Valid.
+  * @rmtoll DEVR0        DAVAL         LL_I3C_IsEnabledOwnDynAddress
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledOwnDynAddress(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL) == (I3C_DEVR0_DAVAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Own Dynamic Address.
+  * @note   This bit can be programmed in controller mode or during Dynamic Address procedure from current controller.
+  * @rmtoll DEVR0        DA            LL_I3C_SetOwnDynamicAddress
+  * @param  I3Cx I3C Instance.
+  * @param  OwnDynamicAddress This parameter must be a value between Min_Data=0 and Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetOwnDynamicAddress(I3C_TypeDef *I3Cx, uint32_t OwnDynamicAddress)
+{
+  MODIFY_REG(I3Cx->DEVR0, I3C_DEVR0_DA, (OwnDynamicAddress << I3C_DEVR0_DA_Pos));
+}
+
+/**
+  * @brief  Get Own Dynamic Address.
+  * @rmtoll DEVR0        DA            LL_I3C_GetOwnDynamicAddress
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0x7F
+  */
+__STATIC_INLINE uint8_t LL_I3C_GetOwnDynamicAddress(const I3C_TypeDef *I3Cx)
+{
+  return (uint8_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DA) >> I3C_DEVR0_DA_Pos);
+}
+
+/**
+  * @brief  Set IBI procedure allowed (when the I3C is acting as target).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
+  * @rmtoll DEVR0        IBIEN         LL_I3C_EnableIBI
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIBI(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN);
+}
+
+/**
+  * @brief  Set IBI procedure not-allowed (when the I3C is acting as target).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
+  * @rmtoll DEVR0        IBIEN         LL_I3C_DisableIBI
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIBI(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN);
+}
+
+/**
+  * @brief  Check if IBI procedure is allowed or not allowed.
+  * @rmtoll DEVR0        IBIEN         LL_I3C_IsEnabledIBI
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIBI(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN) == (I3C_DEVR0_IBIEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Controller-role Request allowed (when the I3C is acting as target).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
+  * @rmtoll DEVR0        CREN          LL_I3C_EnableControllerRoleReq
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableControllerRoleReq(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN);
+}
+
+/**
+  * @brief  Set Controller-role Request as not-allowed (when the I3C is acting as target).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
+  * @rmtoll DEVR0        CREN          LL_I3C_DisableControllerRoleReq
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableControllerRoleReq(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN);
+}
+
+/**
+  * @brief  Check if Controller-role Request is allowed or not-allowed.
+  * @rmtoll DEVR0        CREN          LL_I3C_IsEnabledControllerRoleReq
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledControllerRoleReq(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN) == (I3C_DEVR0_CREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Hot Join allowed (when the I3C is acting as target).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
+  * @rmtoll DEVR0        HJEN          LL_I3C_EnableHotJoin
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableHotJoin(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN);
+}
+
+/**
+  * @brief  Set Hot Join as not-allowed (when the I3C is acting as target).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
+  * @rmtoll DEVR0        HJEN          LL_I3C_DisableHotJoin
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableHotJoin(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN);
+}
+
+/**
+  * @brief  Check if Hot Join is allowed or not-allowed.
+  * @rmtoll DEVR0        HJEN          LL_I3C_IsEnabledHotJoin
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledHotJoin(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN) == (I3C_DEVR0_HJEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Maximum Read Length (target mode).
+  * @note   Those bits can be updated by HW upon reception of GETMRL CCC.
+  * @rmtoll MAXRLR       MRL           LL_I3C_SetMaxReadLength
+  * @param  I3Cx I3C Instance.
+  * @param  MaxReadLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetMaxReadLength(I3C_TypeDef *I3Cx, uint16_t MaxReadLength)
+{
+  MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_MRL, MaxReadLength);
+}
+
+/**
+  * @brief  Return Maximum Read Length (target mode).
+  * @rmtoll MAXRLR       MRL           LL_I3C_GetMaxReadLength
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMaxReadLength(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_MRL));
+}
+
+/**
+  * @brief  Configure the number of additional Mandatory Data Byte (MDB) sent to the controller
+  *         after an acknowledge of the IBI (target mode).
+  * @rmtoll MAXRLR       IBIP          LL_I3C_ConfigNbIBIAddData
+  * @param  I3Cx I3C Instance.
+  * @param  NbIBIAddData This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_PAYLOAD_EMPTY
+  *         @arg @ref LL_I3C_PAYLOAD_1_BYTE
+  *         @arg @ref LL_I3C_PAYLOAD_2_BYTES
+  *         @arg @ref LL_I3C_PAYLOAD_3_BYTES
+  *         @arg @ref LL_I3C_PAYLOAD_4_BYTES
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ConfigNbIBIAddData(I3C_TypeDef *I3Cx, uint32_t NbIBIAddData)
+{
+  MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_IBIP, NbIBIAddData);
+}
+
+/**
+  * @brief  Return the number of additional Mandatory Data Byte (MDB) sent to the controller
+  *         after an acknowledge of the IBI (target mode).
+  * @rmtoll MAXRLR       IBIP          LL_I3C_GetConfigNbIBIAddData
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_PAYLOAD_EMPTY
+  *         @arg @ref LL_I3C_PAYLOAD_1_BYTE
+  *         @arg @ref LL_I3C_PAYLOAD_2_BYTES
+  *         @arg @ref LL_I3C_PAYLOAD_3_BYTES
+  *         @arg @ref LL_I3C_PAYLOAD_4_BYTES
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetConfigNbIBIAddData(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_IBIP));
+}
+
+/**
+  * @brief  Configure Maximum Write Length (target mode).
+  * @note   Those bits can be updated by HW upon reception of GETMWL CCC.
+  * @rmtoll MAXWLR       MWL           LL_I3C_SetMaxWriteLength
+  * @param  I3Cx I3C Instance.
+  * @param  MaxWriteLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetMaxWriteLength(I3C_TypeDef *I3Cx, uint16_t MaxWriteLength)
+{
+  MODIFY_REG(I3Cx->MAXWLR, I3C_MAXWLR_MWL, MaxWriteLength);
+}
+
+/**
+  * @brief  Return Maximum Write Length (target mode).
+  * @rmtoll MAXWLR       MWL           LL_I3C_GetMaxWriteLength
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMaxWriteLength(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->MAXWLR, I3C_MAXWLR_MWL));
+}
+
+/**
+  * @brief  Configure the SCL clock signal waveform.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR0     TIMINGR0      LL_I3C_ConfigClockWaveForm
+  * @param  I3Cx I3C Instance.
+  * @param  ClockWaveForm This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ConfigClockWaveForm(I3C_TypeDef *I3Cx, uint32_t ClockWaveForm)
+{
+  WRITE_REG(I3Cx->TIMINGR0, ClockWaveForm);
+}
+
+/**
+  * @brief  Get the SCL clock signal waveform.
+  * @rmtoll TIMINGR0     TIMINGR0      LL_I3C_GetClockWaveForm
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetClockWaveForm(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_REG(I3Cx->TIMINGR0));
+}
+
+/**
+  * @brief  Configure the SCL clock low period during I3C push-pull phases.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR0     SCLL_PP       LL_I3C_SetPeriodClockLowPP
+  * @param  I3Cx I3C Instance.
+  * @param  PeriodClockLowPP This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetPeriodClockLowPP(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowPP)
+{
+  MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP, (PeriodClockLowPP << I3C_TIMINGR0_SCLL_PP_Pos));
+}
+
+/**
+  * @brief  Get the SCL clock low period during I3C push-pull phases.
+  * @rmtoll TIMINGR0     SCLL_PP       LL_I3C_GetPeriodClockLowPP
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowPP(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP) >> I3C_TIMINGR0_SCLL_PP_Pos);
+}
+
+/**
+  * @brief  Configure the SCL clock High period during I3C open drain and push-pull phases.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR0     SCLH_I3C      LL_I3C_SetPeriodClockHighI3C
+  * @param  I3Cx I3C Instance.
+  * @param  PeriodClockHighI3C This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetPeriodClockHighI3C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI3C)
+{
+  MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C, (PeriodClockHighI3C << I3C_TIMINGR0_SCLH_I3C_Pos));
+}
+
+/**
+  * @brief  Get the SCL clock high period during I3C open drain and push-pull phases.
+  * @rmtoll TIMINGR0     SCLH_I3C      LL_I3C_GetPeriodClockHighI3C
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI3C(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C) >> I3C_TIMINGR0_SCLH_I3C_Pos);
+}
+
+/**
+  * @brief  Configure the SCL clock low period during I3C open drain phases.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR0     SCLL_OD       LL_I3C_SetPeriodClockLowOD
+  * @param  I3Cx I3C Instance.
+  * @param  PeriodClockLowOD This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetPeriodClockLowOD(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowOD)
+{
+  MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD, (PeriodClockLowOD << I3C_TIMINGR0_SCLL_OD_Pos));
+}
+
+/**
+  * @brief  Get the SCL clock low period during I3C open phases.
+  * @rmtoll TIMINGR0     SCLL_OD       LL_I3C_GetPeriodClockLowOD
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowOD(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD) >> I3C_TIMINGR0_SCLL_OD_Pos);
+}
+
+/**
+  * @brief  Configure the SCL clock High period during I2C open drain phases.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR0     SCLH_I2C      LL_I3C_SetPeriodClockHighI2C
+  * @param  I3Cx I3C Instance.
+  * @param  PeriodClockHighI2C This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetPeriodClockHighI2C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI2C)
+{
+  MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C, PeriodClockHighI2C << I3C_TIMINGR0_SCLH_I2C_Pos);
+}
+
+/**
+  * @brief  Get the SCL clock high period during I2C open drain phases.
+  * @rmtoll TIMINGR0     SCLH_I2C      LL_I3C_GetPeriodClockHighI2C
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C) >> I3C_TIMINGR0_SCLH_I2C_Pos);
+}
+
+/**
+  * @brief  Configure the Controller additional hold time on SDA line.
+  * @rmtoll TIMINGR1     SDA_HD        LL_I3C_SetDataHoldTime
+  * @param  I3Cx I3C Instance.
+  * @param  DataHoldTime This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_SDA_HOLD_TIME_0_5
+  *         @arg @ref LL_I3C_SDA_HOLD_TIME_1_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetDataHoldTime(I3C_TypeDef *I3Cx, uint32_t DataHoldTime)
+{
+  MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD, DataHoldTime);
+}
+
+/**
+  * @brief  Get the Controller additional hold time on SDA line.
+  * @rmtoll TIMINGR1     SDA_HD        LL_I3C_GetDataHoldTime
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_SDA_HOLD_TIME_0_5
+  *         @arg @ref LL_I3C_SDA_HOLD_TIME_1_5
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetDataHoldTime(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD));
+}
+
+/**
+  * @brief  Configure the Idle, Available state.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR1     AVAL          LL_I3C_SetAvalTiming
+  * @param  I3Cx I3C Instance.
+  * @param  AvalTiming This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetAvalTiming(I3C_TypeDef *I3Cx, uint32_t AvalTiming)
+{
+  MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (AvalTiming << I3C_TIMINGR1_AVAL_Pos));
+}
+
+/**
+  * @brief  Get the Idle, Available integer value state.
+  * @rmtoll TIMINGR1     AVAL          LL_I3C_GetAvalTiming
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetAvalTiming(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL) >> I3C_TIMINGR1_AVAL_Pos);
+}
+
+/**
+  * @brief  Configure the Free state.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR1     FREE          LL_I3C_SetFreeTiming
+  * @param  I3Cx I3C Instance.
+  * @param  FreeTiming This parameter must be a value between Min_Data=0 and Max_Data=0x3F.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetFreeTiming(I3C_TypeDef *I3Cx, uint32_t FreeTiming)
+{
+  MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE, (FreeTiming << I3C_TIMINGR1_FREE_Pos));
+}
+
+/**
+  * @brief  Get the Free integeter value state.
+  * @rmtoll TIMINGR1     FREE          LL_I3C_GetFreeTiming
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0x3F.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetFreeTiming(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE) >> I3C_TIMINGR1_FREE_Pos);
+}
+
+/**
+  * @brief  Configure the activity state of the new controller.
+  * @note   Refer to MIPI I3C specification (https:__www.mipi.org_specifications)
+  *         for more details related to Activity State.
+  * @rmtoll TIMINGR1     ASNCR            LL_I3C_SetControllerActivityState
+  * @param  I3Cx I3C Instance.
+  * @param  ControllerActivityState This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetControllerActivityState(I3C_TypeDef *I3Cx, uint32_t ControllerActivityState)
+{
+  MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR, ControllerActivityState);
+}
+
+/**
+  * @brief  Get the activity state of the new controller.
+  * @note   Refer to MIPI I3C specification (https:__www.mipi.org_specifications)
+  *         for more details related to Activity State.
+  * @rmtoll TIMINGR1     ASNCR            LL_I3C_GetControllerActivityState
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2
+  *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetControllerActivityState(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR));
+}
+
+/**
+  * @brief  Configure the Controller SDA Hold time, Bus Free, Activity state, Idle state.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR1     SDA_HD        LL_I3C_SetCtrlBusCharacteristic\n
+  *         TIMINGR1     FREE          LL_I3C_SetCtrlBusCharacteristic\n
+  *         TIMINGR1     ASNCR         LL_I3C_SetCtrlBusCharacteristic\n
+  *         TIMINGR1     IDLE          LL_I3C_SetCtrlBusCharacteristic
+  * @param  I3Cx I3C Instance.
+  * @param  CtrlBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0x107F03FF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetCtrlBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t CtrlBusCharacteristic)
+{
+  WRITE_REG(I3Cx->TIMINGR1, CtrlBusCharacteristic);
+}
+
+/**
+  * @brief  Get the Controller SDA Hold time, Bus Free, Activity state, Idle state.
+  * @rmtoll TIMINGR1     SDA_HD        LL_I3C_GetCtrlBusCharacteristic\n
+  *         TIMINGR1     FREE          LL_I3C_GetCtrlBusCharacteristic\n
+  *         TIMINGR1     ASNCR         LL_I3C_GetCtrlBusCharacteristic\n
+  *         TIMINGR1     IDLE          LL_I3C_GetCtrlBusCharacteristic
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0x107F03FF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetCtrlBusCharacteristic(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_REG(I3Cx->TIMINGR1));
+}
+
+/**
+  * @brief  Configure the Target Available state.
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR1     IDLE          LL_I3C_SetTgtBusCharacteristic
+  * @param  I3Cx I3C Instance.
+  * @param  TgtBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetTgtBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t TgtBusCharacteristic)
+{
+  MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (TgtBusCharacteristic & I3C_TIMINGR1_AVAL));
+}
+
+/**
+  * @brief  Get the Target Available state.
+  * @rmtoll TIMINGR1     IDLE          LL_I3C_GetTgtBusCharacteristic
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetTgtBusCharacteristic(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL));
+}
+
+/**
+  * @brief  Configure the SCL clock stalling time on I3C Bus (controller mode).
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   This parameter is computed with the STM32CubeMX Tool.
+  * @rmtoll TIMINGR2     STALL        LL_I3C_SetStallTime
+  * @param  I3Cx I3C Instance.
+  * @param  ControllerStallTime This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetStallTime(I3C_TypeDef *I3Cx, uint32_t ControllerStallTime)
+{
+  MODIFY_REG(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL, (ControllerStallTime << I3C_TIMINGR2_STALL_Pos));
+}
+
+/**
+  * @brief  Get the SCL clock stalling time on I3C Bus (controller mode).
+  * @rmtoll TIMINGR2     STALL        LL_I3C_GetStallTime
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetStallTime(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL));
+}
+
+/**
+  * @brief  Set stall on ACK bit (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLA       LL_I3C_EnableStallACK
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableStallACK(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA);
+}
+
+/**
+  * @brief  Disable stall on ACK bit (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLA       LL_I3C_DisableStallACK
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableStallACK(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA);
+}
+
+/**
+  * @brief  Check if stall on ACK bit is enabled or disabled (controller mode).
+  * @rmtoll TIMINGR2     STALLA       LL_I3C_IsEnabledStallACK
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACK(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA) == (I3C_TIMINGR2_STALLA)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set stall on Parity bit of Command Code byte (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLC       LL_I3C_EnableStallParityCCC
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableStallParityCCC(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC);
+}
+
+/**
+  * @brief  Disable stall on Parity bit of Command Code byte (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLC       LL_I3C_DisableStallParityCCC
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableStallParityCCC(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC);
+}
+
+/**
+  * @brief  Check if stall on Parity bit of Command Code byte is enabled or disabled (controller mode).
+  * @rmtoll TIMINGR2     STALLC       LL_I3C_IsEnabledStallParityCCC
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityCCC(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC) == (I3C_TIMINGR2_STALLC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set stall on Parity bit of Data bytes (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLD       LL_I3C_EnableStallParityData
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableStallParityData(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD);
+}
+
+/**
+  * @brief  Disable stall on Parity bit of Data bytes (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLD       LL_I3C_DisableStallParityData
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableStallParityData(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD);
+}
+
+/**
+  * @brief  Check if stall on Parity bit of Data bytes is enabled or disabled (controller mode).
+  * @rmtoll TIMINGR2     STALLD       LL_I3C_IsEnabledStallParityData
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityData(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD) == (I3C_TIMINGR2_STALLD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set stall on T bit (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLT       LL_I3C_EnableStallTbit
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableStallTbit(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT);
+}
+
+/**
+  * @brief  Disable stall on T bit (controller mode).
+  * @note   This bit can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll TIMINGR2     STALLT       LL_I3C_DisableStallTbit
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableStallTbit(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT);
+}
+
+/**
+  * @brief  Check if stall on T bit is enabled or disabled (controller mode).
+  * @rmtoll TIMINGR2     STALLT       LL_I3C_IsEnabledStallTbit
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledStallTbit(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT) == (I3C_TIMINGR2_STALLT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6).
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll BCR          BCR6          LL_I3C_SetDeviceCapabilityOnBus
+  * @param  I3Cx I3C Instance.
+  * @param  DeviceCapabilityOnBus This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET
+  *         @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetDeviceCapabilityOnBus(I3C_TypeDef *I3Cx, uint32_t DeviceCapabilityOnBus)
+{
+  MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR6, DeviceCapabilityOnBus);
+}
+
+/**
+  * @brief  Get the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6).
+  * @rmtoll BCR          BCR6          LL_I3C_GetDeviceCapabilityOnBus
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET
+  *         @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetDeviceCapabilityOnBus(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR6));
+}
+
+/**
+  * @brief  Configure the Device IBI Payload (MIPI Bus Characteristics Register BCR2).
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll BCR          BCR2          LL_I3C_SetDeviceIBIPayload
+  * @param  I3Cx I3C Instance.
+  * @param  DeviceIBIPayload This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA
+  *         @arg @ref LL_I3C_IBI_ADDITIONAL_DATA
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetDeviceIBIPayload(I3C_TypeDef *I3Cx, uint32_t DeviceIBIPayload)
+{
+  MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR2, DeviceIBIPayload);
+}
+
+/**
+  * @brief  Get the Device IBI Payload (MIPI Bus Characteristics Register BCR2).
+  * @rmtoll BCR          BCR2          LL_I3C_GetDeviceIBIPayload
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA
+  *         @arg @ref LL_I3C_IBI_ADDITIONAL_DATA
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetDeviceIBIPayload(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR2));
+}
+
+/**
+  * @brief  Configure the Data Speed Limitation (limitation, as described by I3C_GETMXDSR).
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll BCR          BCR0          LL_I3C_SetDataSpeedLimitation
+  * @param  I3Cx I3C Instance.
+  * @param  DataSpeedLimitation This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION
+  *         @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetDataSpeedLimitation(I3C_TypeDef *I3Cx, uint32_t DataSpeedLimitation)
+{
+  MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR0, DataSpeedLimitation);
+}
+
+/**
+  * @brief  Get  the Data Speed Limitation (limitation, as described by I3C_GETMXDSR).
+  * @rmtoll BCR          BCR0          LL_I3C_GetDataSpeedLimitation
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION
+  *         @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetDataSpeedLimitation(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR0));
+}
+
+/**
+  * @brief  Configure the Device Characteristics Register (DCR).
+  * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
+  *
+  * @note   Refer MIPI web site for the list of device code available.
+  * @rmtoll DCR          DC            LL_I3C_SetDeviceCharacteristics
+  * @param  I3Cx I3C Instance.
+  * @param  DeviceCharacteristics This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetDeviceCharacteristics(I3C_TypeDef *I3Cx, uint32_t DeviceCharacteristics)
+{
+  MODIFY_REG(I3Cx->DCR, I3C_DCR_DCR, DeviceCharacteristics);
+}
+
+/**
+  * @brief  Get the Device Characteristics Register (DCR).
+  * @note   Refer MIPI web site to associated value with the list of device code available.
+  * @rmtoll DCR          DCR            LL_I3C_GetDeviceCharacteristics
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetDeviceCharacteristics(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->DCR, I3C_DCR_DCR));
+}
+
+/**
+  * @brief  Configure IBI MDB support for pending read notification.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll GETCAPR     CAPPEND          LL_I3C_SetPendingReadMDB
+  * @param  I3Cx I3C Instance.
+  * @param  PendingReadMDB This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION
+  *         @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetPendingReadMDB(I3C_TypeDef *I3Cx, uint32_t PendingReadMDB)
+{
+  MODIFY_REG(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND, PendingReadMDB);
+}
+
+/**
+  * @brief  Get IBI MDB support for pending read notification value.
+  * @rmtoll GETCAPR     CAPPEND          LL_I3C_GetPendingReadMDB
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION
+  *         @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetPendingReadMDB(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND));
+}
+
+/**
+  * @brief  Configure the Group Management Support bit of MSTCAP1.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll CRCAPR      CAPGRP        LL_I3C_SetGrpAddrHandoffSupport
+  * @param  I3Cx I3C Instance.
+  * @param  GrpAddrHandoffSupport This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED
+  *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetGrpAddrHandoffSupport(I3C_TypeDef *I3Cx, uint32_t GrpAddrHandoffSupport)
+{
+  MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP, GrpAddrHandoffSupport);
+}
+
+/**
+  * @brief  Get the Group Management Support bit of MSTCAP1.
+  * @rmtoll CRCAPR      CAPGRP        LL_I3C_GetGrpAddrHandoffSupport
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED
+  *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetGrpAddrHandoffSupport(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP));
+}
+
+/**
+  * @brief  Configure the Delayed Controller Handoff bit in MSTCAP2.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll CRCAPR      CAPDHOFF      LL_I3C_SetControllerHandoffDelayed
+  * @param  I3Cx I3C Instance.
+  * @param  ControllerHandoffDelayed This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_HANDOFF_NOT_DELAYED
+  *         @arg @ref LL_I3C_HANDOFF_DELAYED
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetControllerHandoffDelayed(I3C_TypeDef *I3Cx, uint32_t ControllerHandoffDelayed)
+{
+  MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF, ControllerHandoffDelayed);
+}
+
+/**
+  * @brief  Get the Delayed Controller Handoff bit in MSTCAP2.
+  * @rmtoll CRCAPR      CAPDHOFF      LL_I3C_GetControllerHandoffDelayed
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_HANDOFF_NOT_DELAYED
+  *         @arg @ref LL_I3C_HANDOFF_DELAYED
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetControllerHandoffDelayed(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF));
+}
+
+/**
+  * @brief  Configure the Activity State after controllership handoff.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll GETMXDSR     HOFFAS        LL_I3C_SetHandoffActivityState
+  * @param  I3Cx I3C Instance.
+  * @param  HandoffActivityState This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetHandoffActivityState(I3C_TypeDef *I3Cx, uint32_t HandoffActivityState)
+{
+  MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS, HandoffActivityState);
+}
+
+/**
+  * @brief  Get the Activity State after controllership handoff.
+  * @rmtoll GETMXDSR     HOFFAS        LL_I3C_GetHandoffActivityState
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2
+  *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetHandoffActivityState(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS));
+}
+
+/**
+  * @brief  Configure the Max Data Speed Format response for GETMXDS CCC.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll GETMXDSR     FMT          LL_I3C_SetMaxDataSpeedFormat
+  * @param  I3Cx I3C Instance.
+  * @param  MaxDataSpeedFormat This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_1
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetMaxDataSpeedFormat(I3C_TypeDef *I3Cx, uint32_t MaxDataSpeedFormat)
+{
+  MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT, MaxDataSpeedFormat);
+}
+
+/**
+  * @brief  Get the Max Data Speed Format response for GETMXDS CCC.
+  * @rmtoll GETMXDSR     FMT          LL_I3C_GetMaxDataSpeedFormat
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_1
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID
+  *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMaxDataSpeedFormat(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT));
+}
+
+/**
+  * @brief  Configure the Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll GETMXDSR     RDTURN        LL_I3C_SetMiddleByteTurnAround
+  * @param  I3Cx I3C Instance.
+  * @param  MiddleByteTurnAround This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetMiddleByteTurnAround(I3C_TypeDef *I3Cx, uint32_t MiddleByteTurnAround)
+{
+  MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN, (MiddleByteTurnAround << I3C_GETMXDSR_RDTURN_Pos));
+}
+
+/**
+  * @brief  Get the value of Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround.
+  * @rmtoll GETMXDSR     RDTURN        LL_I3C_GetMiddleByteTurnAround
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMiddleByteTurnAround(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN));
+}
+
+/**
+  * @brief  Configure clock-to-data turnaround time.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll GETMXDSR     TSCO          LL_I3C_SetDataTurnAroundTime
+  * @param  I3Cx I3C Instance.
+  * @param  DataTurnAroundTime This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS
+  *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetDataTurnAroundTime(I3C_TypeDef *I3Cx, uint32_t DataTurnAroundTime)
+{
+  MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO, DataTurnAroundTime);
+}
+
+/**
+  * @brief  Get clock-to-data turnaround time.
+  * @rmtoll GETMXDSR     TSCO          LL_I3C_GetDataTurnAroundTime
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS
+  *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetDataTurnAroundTime(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO));
+}
+
+/**
+  * @brief  Configure the MIPI Instance ID.
+  * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
+  * @rmtoll EPIDR        MIPIID       LL_I3C_SetMIPIInstanceID
+  * @param  I3Cx I3C Instance.
+  * @param  MIPIInstanceID This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetMIPIInstanceID(I3C_TypeDef *I3Cx, uint32_t MIPIInstanceID)
+{
+  MODIFY_REG(I3Cx->EPIDR, I3C_EPIDR_MIPIID, (MIPIInstanceID << I3C_EPIDR_MIPIID_Pos));
+}
+
+/**
+  * @brief  Get the MIPI Instance ID.
+  * @rmtoll EPIDR        MIPIID       LL_I3C_GetMIPIInstanceID
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0xF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMIPIInstanceID(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIID) >> I3C_EPIDR_MIPIID_Pos);
+}
+
+/**
+  * @brief  Get the ID type selector.
+  * @rmtoll EPIDR        IDTSEL        LL_I3C_GetIDTypeSelector
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0x0 and Max_Data=0x1
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetIDTypeSelector(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_IDTSEL) >> I3C_EPIDR_IDTSEL_Pos);
+}
+
+/**
+  * @brief  Get the MIPI Manufacturer ID.
+  * @rmtoll EPIDR        MIPIMID       LL_I3C_GetMIPIManufacturerID
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 and Max_Data=0x7FFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMIPIManufacturerID(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIMID) >> I3C_EPIDR_MIPIMID_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EF_Data Management
+  * @{
+  */
+
+/**
+  * @brief  Request a reception Data FIFO Flush.
+  * @rmtoll CFGR      RXFLUSH       LL_I3C_RequestRxFIFOFlush
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_RequestRxFIFOFlush(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_RXFLUSH);
+}
+
+/**
+  * @brief  Request a transmission Data FIFO Flush.
+  * @rmtoll CFGR      TXFLUSH       LL_I3C_RequestTxFIFOFlush
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_RequestTxFIFOFlush(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_TXFLUSH);
+}
+
+/**
+  * @brief  Request a Status Data FIFO Flush.
+  * @rmtoll CFGR      SFLUSH        LL_I3C_RequestStatusFIFOFlush
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_SFLUSH);
+}
+
+/**
+  * @brief  Get Activity state of Controller on the I3C Bus (Target only).
+  * @rmtoll DEVR0        AS            LL_I3C_GetActivityState
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_0
+  *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_1
+  *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_2
+  *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_3
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetActivityState(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_AS));
+}
+
+/**
+  * @brief  Get Reset Action (Target only).
+  * @rmtoll DEVR0        RSTACT        LL_I3C_GetResetAction
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_RESET_ACTION_NONE
+  *         @arg @ref LL_I3C_RESET_ACTION_PARTIAL
+  *         @arg @ref LL_I3C_RESET_ACTION_FULL
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetResetAction(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTACT));
+}
+
+/**
+  * @brief  Request a Control word FIFO Flush.
+  * @rmtoll CFGR      CFLUSH        LL_I3C_RequestControlFIFOFlush
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_RequestControlFIFOFlush(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_CFLUSH);
+}
+
+/**
+  * @brief  Request a Transfer start.
+  * @note   After request, the current instruction in Control Register is executed on I3C Bus.
+  * @rmtoll CFGR      TSFSET        LL_I3C_RequestTransfer
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_RequestTransfer(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->CFGR, I3C_CFGR_TSFSET);
+}
+
+/**
+  * @brief  Handles I3C Message content on the I3C Bus as Controller.
+  * @rmtoll CR           ADD           LL_I3C_ControllerHandleMessage\n
+  *         CR           DCNT          LL_I3C_ControllerHandleMessage\n
+  *         CR           RNW           LL_I3C_ControllerHandleMessage\n
+  *         CR           MTYPE         LL_I3C_ControllerHandleMessage\n
+  *         CR           MEND          LL_I3C_ControllerHandleMessage
+  * @param  I3Cx I3C Instance.
+  * @param  TargetAddr Specifies the target address to be programmed.
+  *               This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @param  TransferSize Specifies the number of bytes to be programmed.
+  *               This parameter must be a value between Min_Data=0 and Max_Data=65535.
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_DIRECTION_WRITE
+  *         @arg @ref LL_I3C_DIRECTION_READ
+  * @param  MessageType This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_CONTROLLER_MTYPE_RELEASE
+  *         @arg @ref LL_I3C_CONTROLLER_MTYPE_HEADER
+  *         @arg @ref LL_I3C_CONTROLLER_MTYPE_PRIVATE
+  *         @arg @ref LL_I3C_CONTROLLER_MTYPE_DIRECT
+  *         @arg @ref LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C
+  * @param  EndMode This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_GENERATE_STOP
+  *         @arg @ref LL_I3C_GENERATE_RESTART
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ControllerHandleMessage(I3C_TypeDef *I3Cx, uint32_t TargetAddr, uint32_t TransferSize,
+                                                    uint32_t Direction, uint32_t MessageType, uint32_t EndMode)
+{
+  WRITE_REG(I3Cx->CR, ((TargetAddr << I3C_CR_ADD_Pos) | TransferSize | Direction | MessageType | EndMode) \
+            & (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | I3C_CR_MEND));
+}
+
+/**
+  * @brief  Handles I3C Common Command Code content on the I3C Bus as Controller.
+  * @rmtoll CR           CCC           LL_I3C_ControllerHandleCCC\n
+  *         CR           DCNT          LL_I3C_ControllerHandleCCC\n
+  *         CR           MTYPE         LL_I3C_ControllerHandleCCC\n
+  *         CR           MEND          LL_I3C_ControllerHandleCCC
+  * @param  I3Cx I3C Instance.
+  * @param  CCCValue Specifies the Command Code to be programmed.
+  *               This parameter must be a value between Min_Data=0 and Max_Data=0x1FF.
+  * @param  AddByteSize Specifies the number of CCC additional bytes to be programmed.
+  *               This parameter must be a value between Min_Data=0 and Max_Data=65535.
+  * @param  EndMode This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_GENERATE_STOP
+  *         @arg @ref LL_I3C_GENERATE_RESTART
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ControllerHandleCCC(I3C_TypeDef *I3Cx, uint32_t CCCValue,
+                                                uint32_t AddByteSize, uint32_t EndMode)
+{
+  WRITE_REG(I3Cx->CR, ((CCCValue << I3C_CR_CCC_Pos) | AddByteSize | EndMode | LL_I3C_CONTROLLER_MTYPE_CCC) \
+            & (I3C_CR_CCC | I3C_CR_DCNT | I3C_CR_MTYPE | I3C_CR_MEND));
+}
+
+/**
+  * @brief  Handles I3C Message content on the I3C Bus as Target.
+  * @rmtoll CR           MTYPE         LL_I3C_TargetHandleMessage\n
+  *         CR           DCNT       LL_I3C_TargetHandleMessage
+  * @param  I3Cx I3C Instance.
+  * @param  MessageType This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_TARGET_MTYPE_HOT_JOIN
+  *         @arg @ref LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ
+  *         @arg @ref LL_I3C_TARGET_MTYPE_IBI
+  * @param  IBISize Specifies the number of IBI bytes.
+  *               This parameter must be a value between Min_Data=0 and Max_Data=65535.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_TargetHandleMessage(I3C_TypeDef *I3Cx, uint32_t MessageType, uint32_t IBISize)
+{
+  WRITE_REG(I3Cx->CR, (MessageType | IBISize) & (I3C_CR_DCNT | I3C_CR_MTYPE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receive Data Byte register.
+  * @rmtoll RDR          RDB0         LL_I3C_ReceiveData8
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_I3C_ReceiveData8(const I3C_TypeDef *I3Cx)
+{
+  return (uint8_t)(READ_BIT(I3Cx->RDR, I3C_RDR_RDB0));
+}
+
+/**
+  * @brief  Write in Transmit Data Byte Register.
+  * @rmtoll TDR          TDB0         LL_I3C_TransmitData8
+  * @param  I3Cx I3C Instance.
+  * @param  Data This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_TransmitData8(I3C_TypeDef *I3Cx, uint8_t Data)
+{
+  WRITE_REG(I3Cx->TDR, Data);
+}
+
+/**
+  * @brief  Read Receive Data Word register.
+  * @note   Content of register is filled in Little Endian.
+  *         Mean MSB correspond to last data byte received,
+  *         LSB correspond to first data byte received.
+  * @rmtoll RDWR         RDWR          LL_I3C_ReceiveData32
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_I3C_ReceiveData32(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_REG(I3Cx->RDWR));
+}
+
+/**
+  * @brief  Write in Transmit Data Word Register.
+  * @note   Content of register is filled in Little Endian.
+  *         Mean MSB correspond to last data byte transmitted,
+  *         LSB correspond to first data byte transmitted.
+  * @rmtoll TDWR         TDWR          LL_I3C_TransmitData32
+  * @param  I3Cx I3C Instance.
+  * @param  Data This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_TransmitData32(I3C_TypeDef *I3Cx, uint32_t Data)
+{
+  WRITE_REG(I3Cx->TDWR, Data);
+}
+
+/**
+  * @brief  Configure the IBI data payload to be sent during IBI (target mode).
+  * @note   Content of register is filled in Little Endian.
+  *         Mean MSB correspond to last IBI data byte,
+  *         LSB correspond to first IBI data byte.
+  * @rmtoll IBIDR        IBIDR         LL_I3C_SetIBIPayload
+  * @param  I3Cx I3C Instance.
+  * @param  OwnIBIPayload This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetIBIPayload(I3C_TypeDef *I3Cx, uint32_t OwnIBIPayload)
+{
+  WRITE_REG(I3Cx->IBIDR, OwnIBIPayload);
+}
+
+/**
+  * @brief  Get the own IBI data payload (target mode), or get the Target IBI received (controller mode).
+  * @note   Content of register is filled in Little Endian.
+  *         Mean MSB correspond to last IBI data byte,
+  *         LSB correspond to first IBI data byte.
+  * @rmtoll IBIDR        IBIDR         LL_I3C_GetIBIPayload
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetIBIPayload(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_REG(I3Cx->IBIDR));
+}
+
+/**
+  * @brief  Get the number of data bytes received when reading IBI data (controller mode).
+  * @rmtoll RMR         IBIRDCNT     LL_I3C_GetNbIBIAddData
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0x7
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetNbIBIAddData(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_IBIRDCNT));
+}
+
+/**
+  * @brief  Get the target address received during accepted IBI or Controller-role request.
+  * @rmtoll RMR         RADD         LL_I3C_GetIBITargetAddr
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetIBITargetAddr(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RADD) >> I3C_RMR_RADD_Pos);
+}
+
+/**
+  * @brief  Set TX FIFO Preload (target mode).
+  * @note   Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO.
+  * @rmtoll TGTTDR       PRELOAD       LL_I3C_ConfigTxPreload
+  * @rmtoll TGTTDR       TDCNT        LL_I3C_ConfigTxPreload
+  * @param  I3Cx I3C Instance.
+  * @param  TxDataCount This parameter must be a value between Min_Data=0 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ConfigTxPreload(I3C_TypeDef *I3Cx, uint16_t TxDataCount)
+{
+  MODIFY_REG(I3Cx->TGTTDR, (I3C_TGTTDR_PRELOAD | I3C_TGTTDR_TGTTDCNT), (I3C_TGTTDR_PRELOAD | TxDataCount));
+}
+
+/**
+  * @brief  Indicates the status of TX FIFO preload (target mode).
+  *         RESET: No preload of TX FIFO.
+  *         SET: Preload of TX FIFO ongoing.
+  * @note   Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO.
+  * @rmtoll TGTTDR       PRELOAD       LL_I3C_IsActiveTxPreload
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveTxPreload(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_PRELOAD) == (I3C_TGTTDR_PRELOAD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the number of bytes to transmit (target mode).
+  * @note   The return value correspond to the remaining number of bytes to load in TX FIFO.
+  * @rmtoll TGTTDR       TDCNT        LL_I3C_GetTxPreloadDataCount
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_I3C_GetTxPreloadDataCount(const I3C_TypeDef *I3Cx)
+{
+  return (uint16_t)(READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_TGTTDCNT));
+}
+
+/**
+  * @brief  Get the number of data during a Transfer.
+  * @note   The return value correspond to number of transmitted bytes reported
+  *         during Address Assignment process in Target mode.
+  * The return value  correspond to number of target detected
+  * during Address Assignment process in Controller mode.
+  * The return value  correspond to number of data bytes read from or sent to the I3C bus
+  * during the message link to MID current value.
+  * @rmtoll SR           XDCNT      LL_I3C_GetXferDataCount
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetXferDataCount(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_XDCNT));
+}
+
+/**
+  * @brief  Indicates if a Target abort a private read command.
+  * @rmtoll SR           ABT           LL_I3C_IsTargetAbortPrivateRead
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsTargetAbortPrivateRead(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SR, I3C_SR_ABT) == (I3C_SR_ABT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Direction of the Message.
+  * @rmtoll SR           DIR           LL_I3C_GetMessageDirection
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_MESSAGE_DIRECTION_WRITE
+  *         @arg @ref LL_I3C_MESSAGE_DIRECTION_READ
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMessageDirection(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_DIR));
+}
+
+/**
+  * @brief  Get Message identifier.
+  * @rmtoll SR           MID           LL_I3C_GetMessageIdentifier
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0xFF, representing the internal hardware counter value.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMessageIdentifier(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_MID));
+}
+
+/**
+  * @brief  Get Message error code.
+  * @rmtoll SER          CODERR        LL_I3C_GetMessageErrorCode
+  * @param  I3Cx I3C Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE0
+  *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE1
+  *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE2
+  *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE3
+  *         @arg @ref LL_I3C_TARGET_ERROR_TE0
+  *         @arg @ref LL_I3C_TARGET_ERROR_TE1
+  *         @arg @ref LL_I3C_TARGET_ERROR_TE2
+  *         @arg @ref LL_I3C_TARGET_ERROR_TE3
+  *         @arg @ref LL_I3C_TARGET_ERROR_TE4
+  *         @arg @ref LL_I3C_TARGET_ERROR_TE5
+  *         @arg @ref LL_I3C_TARGET_ERROR_TE6
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetMessageErrorCode(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->SER, I3C_SER_CODERR));
+}
+
+/**
+  * @brief  Get CCC code of received command.
+  * @rmtoll RMR         RCODE        LL_I3C_GetReceiveCommandCode
+  * @param  I3Cx I3C Instance.
+  * @retval Value between Min_Data=0 to Max_Data=0xFF.
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetReceiveCommandCode(const I3C_TypeDef *I3Cx)
+{
+  return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RCODE) >> I3C_RMR_RCODE_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EF_Target Payload
+  * @{
+  */
+
+/**
+  * @brief  Set Dynamic Address assigned to target x.
+  * @rmtoll DEVRX        DA            LL_I3C_SetTargetDynamicAddress
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @param  DynamicAddr Value between Min_Data=0 to Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_SetTargetDynamicAddress(I3C_TypeDef *I3Cx, uint32_t TargetId, uint32_t DynamicAddr)
+{
+  MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA, (DynamicAddr << I3C_DEVRX_DA_Pos));
+}
+
+/**
+  * @brief  Get Dynamic Address assigned to target x.
+  * @rmtoll DEVRX        DA            LL_I3C_GetTargetDynamicAddress
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval Value between Min_Data=0 to Max_Data=0x7F
+  */
+__STATIC_INLINE uint32_t LL_I3C_GetTargetDynamicAddress(const I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  return (uint32_t)((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA)) >> I3C_DEVRX_DA_Pos);
+}
+
+/**
+  * @brief  Enable IBI Acknowledgement from target x(controller mode).
+  * @note   The bit DIS is automatically set when CRACK or IBIACK are set.
+  *         This mean DEVRX register access is not allowed.
+  *         Reset CRACK and IBIACK will reset DIS bit.
+  * @rmtoll DEVRX        IBIACK        LL_I3C_EnableTargetIBIAck
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK);
+}
+
+/**
+  * @brief  Disable IBI Acknowledgement from target x (controller mode).
+  * @rmtoll DEVRX        IBIACK        LL_I3C_DisableTargetIBIAck
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK);
+}
+
+/**
+  * @brief  Indicates if IBI from target x will be Acknowledged or Not Acknowledged (controller mode).
+  *         RESET: IBI Not Acknowledged.
+  *         SET: IBI Acknowledged.
+  * @rmtoll DEVRX        IBIACK        LL_I3C_IsEnabledTargetIBIAck
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetIBIAck(const I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK) == I3C_DEVRX_IBIACK) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Controller-role Request Acknowledgement from target x(controller mode).
+  * @note   The bit DIS is automatically set when CRACK or IBIACK are set.
+  *         This mean DEVRX register access is not allowed.
+  *         Reset CRACK and IBIACK will reset DIS bit.
+  * @rmtoll DEVRX        CRACK         LL_I3C_EnableTargetCRAck
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK);
+}
+
+/**
+  * @brief  Disable Controller-role Request Acknowledgement from target x (controller mode).
+  * @rmtoll DEVRX        CRACK         LL_I3C_DisableTargetCRAck
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK);
+}
+
+/**
+  * @brief  Indicates if Controller-role Request from target x will be
+  *         Acknowledged or Not Acknowledged (controller mode).
+  *         RESET: Controller-role Request Not Acknowledged.
+  *         SET: Controller-role Request Acknowledged.
+  * @rmtoll DEVRX        CRACK         LL_I3C_IsEnabledTargetCRAck
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetCRAck(const I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK) == I3C_DEVRX_CRACK) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
+  * @rmtoll DEVRX        IBIDEN          LL_I3C_EnableIBIAddData
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN);
+}
+
+/**
+  * @brief  Disable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
+  * @rmtoll DEVRX        IBIDEN          LL_I3C_DisableIBIAddData
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN);
+}
+
+/**
+  * @brief  Indicates if additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
+  *         RESET: No Mandatory Data Byte follows IBI.
+  *         SET: Mandatory Data Byte follows IBI.
+  * @rmtoll DEVRX        IBIDEN          LL_I3C_IsEnabledIBIAddData
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIBIAddData(const I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN) == I3C_DEVRX_IBIDEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Suspension of Current transfer during IBI treatment.
+  * @note   When set, this feature will allow controller to send
+  *         a Stop condition and CR FIFO is flushed after IBI treatment.
+  *         Software has to rewrite instructions in Control Register to start a new transfer.
+  * @rmtoll DEVRX        SUSP          LL_I3C_EnableFrameSuspend
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP);
+}
+
+/**
+  * @brief  Disable Suspension of Current transfer during IBI treatment.
+  * @note   When set, this feature will allow controller to continue CR FIFO treatment after IBI treatment.
+  * @rmtoll DEVRX        SUSP          LL_I3C_DisableFrameSuspend
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP);
+}
+
+/**
+  * @brief  Indicates if I3C transfer must be Suspended or not Suspended during IBI treatment from target x.
+  *         RESET: Transfer is not suspended. Instruction in CR FIFO are executed after IBI.
+  *         SET: Transfer is suspended (a Stop condition is sent). CR FIFO is flushed.
+  * @rmtoll DEVRX        SUSP          LL_I3C_IsFrameMustBeSuspended
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsFrameMustBeSuspended(const I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP) == I3C_DEVRX_SUSP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if update of the Device Characteristics Register is Allowed or Not Allowed.
+  *         RESET: Device Characteristics Register update is Not Allowed.
+  *         SET: Device Characteristics Register update is Allowed.
+  * @note   Used to prevent software writing during reception of an IBI or Controller-role Request from target x.
+  * @rmtoll DEVRX        DIS           LL_I3C_IsAllowedPayloadUpdate
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsAllowedPayloadUpdate(const I3C_TypeDef *I3Cx, uint32_t TargetId)
+{
+  return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DIS) != I3C_DEVRX_DIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set I3C bus devices configuration.
+  * @note   This function is called only when the I3C instance is initialized as controller.
+  *         This function can be called by the controller application to help the automatic treatment when target have
+  *         capability of IBI and/or Control-Role.
+  * @rmtoll DEVRX        DA            LL_I3C_ConfigDeviceCapabilities
+  * @rmtoll DEVRX        IBIACK        LL_I3C_ConfigDeviceCapabilities
+  * @rmtoll DEVRX        IBIDEN        LL_I3C_ConfigDeviceCapabilities
+  * @rmtoll DEVRX        CRACK         LL_I3C_ConfigDeviceCapabilities
+  * @param  I3Cx I3C Instance.
+  * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
+  * @param  DynamicAddr Value between Min_Data=0 to Max_Data=0x7F
+  * @param  IBIAck Value This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_IBI_CAPABILITY
+  *         @arg @ref LL_I3C_IBI_NO_CAPABILITY
+  * @param  IBIAddData This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_IBI_DATA_ENABLE
+  *         @arg @ref LL_I3C_IBI_DATA_DISABLE
+  * @param  CRAck This parameter can be one of the following values:
+  *         @arg @ref LL_I3C_CR_CAPABILITY
+  *         @arg @ref LL_I3C_CR_NO_CAPABILITY
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ConfigDeviceCapabilities(I3C_TypeDef *I3Cx,
+                                                     uint32_t TargetId,
+                                                     uint32_t DynamicAddr,
+                                                     uint32_t IBIAck,
+                                                     uint32_t IBIAddData,
+                                                     uint32_t CRAck)
+{
+  MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], \
+             (I3C_DEVRX_DA | I3C_DEVRX_IBIACK | I3C_DEVRX_CRACK | I3C_DEVRX_IBIDEN), \
+             ((DynamicAddr << I3C_DEVRX_DA_Pos) | IBIAck | IBIAddData | CRAck));
+}
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Indicates the status of Control FIFO Empty flag.
+  *         RESET: One or more data are available in Control FIFO.
+  *         SET: No more data available in Control FIFO.
+  * @rmtoll EVR          CFEF          LL_I3C_IsActiveFlag_CFE
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFE(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFEF) == (I3C_EVR_CFEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Transmit FIFO Empty flag.
+  *         RESET: One or more data are available in Transmit FIFO.
+  *         SET: No more data available in Transmit FIFO.
+  * @rmtoll EVR          TXFEF         LL_I3C_IsActiveFlag_TXFE
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFE(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFEF) == (I3C_EVR_TXFEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Control FIFO Not Full flag.
+  *         RESET: One or more free space available in Control FIFO.
+  *         SET: No more free space available in Control FIFO.
+  * @note   When a transfer is ongoing, the Control FIFO shall not be written unless this flag is set.
+  * @rmtoll EVR          CFNFF         LL_I3C_IsActiveFlag_CFNF
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFNF(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFNFF) == (I3C_EVR_CFNFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Status FIFO Not Empty flag.
+  *         RESET: One or more free space available in Status FIFO.
+  *         SET: No more free space available in Status FIFO.
+  * @note   This flag is updated only when the FIFO is used, mean SMODE = 1.
+  * @rmtoll EVR          SFNEF         LL_I3C_IsActiveFlag_SFNE
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_SFNE(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_SFNEF) == (I3C_EVR_SFNEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Transmit FIFO Not Full flag.
+  *         RESET: One or more free space available in Transmit FIFO.
+  *         SET: No more free space available in Transmit FIFO.
+  * @note   When a transfer is ongoing, the Transmit FIFO shall not be written unless this flag is set.
+  * @rmtoll EVR          TXFNFF        LL_I3C_IsActiveFlag_TXFNF
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFNF(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFNFF) == (I3C_EVR_TXFNFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Receive FIFO Not Full flag.
+  *         RESET: One or more data are available in Receive FIFO.
+  *         SET: No more data available in Receive FIFO.
+  * @rmtoll EVR          RXFNEF        LL_I3C_IsActiveFlag_RXFNE
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXFNE(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXFNEF) == (I3C_EVR_RXFNEF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates that the last Receive byte is available.
+  *         RESET: Clear default value.
+  *         SET: Last Receive byte ready to read from Receive FIFO.
+  * @rmtoll EVR          RXLASTF       LL_I3C_IsActiveFlag_RXLAST
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXLAST(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXLASTF) == (I3C_EVR_RXLASTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates that the last Transmit byte is written in FIFO.
+  *         RESET: Transmission is not finalized.
+  *         SET: Last Transmit byte is written in transmit FIFO.
+  * @rmtoll EVR          TXLASTF       LL_I3C_IsActiveFlag_TXLAST
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXLAST(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXLASTF) == (I3C_EVR_TXLASTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Frame Complete flag (controller and target mode).
+  *         RESET: Current Frame transfer is not finalized.
+  *         SET: Current Frame transfer is completed.
+  * @rmtoll EVR          FCF           LL_I3C_IsActiveFlag_FC
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_FC(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_FCF) == (I3C_EVR_FCF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Reception Target End flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: Target prematurely ended a Read Command.
+  * @note   This flag is set only when status FIFO is not used, mean SMODE = 0.
+  * @rmtoll EVR          RXTGTENDF     LL_I3C_IsActiveFlag_RXTGTEND
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXTGTEND(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXTGTENDF) == (I3C_EVR_RXTGTENDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Error flag (controller and target mode).
+  *         RESET: Clear default value.
+  *         SET: One or more Errors are detected.
+  * @rmtoll EVR          ERRF          LL_I3C_IsActiveFlag_ERR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ERR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_ERRF) == (I3C_EVR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of IBI flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: An IBI have been received.
+  * @rmtoll EVR          IBIF          LL_I3C_IsActiveFlag_IBI
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBI(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIF) == (I3C_EVR_IBIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of IBI End flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: IBI procedure is finished.
+  * @rmtoll EVR          IBIENDF       LL_I3C_IsActiveFlag_IBIEND
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBIEND(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIENDF) == (I3C_EVR_IBIENDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Controller-role Request flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: A Controller-role request procedure have been received.
+  * @rmtoll EVR          CRF           LL_I3C_IsActiveFlag_CR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRF) == (I3C_EVR_CRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Controller-role Request Update flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: I3C device have gained Controller-role of the I3C Bus.
+  * @rmtoll EVR          BCUPDF        LL_I3C_IsActiveFlag_CRUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CRUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRUPDF) == (I3C_EVR_CRUPDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Hot Join flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: A Hot Join request have been received.
+  * @rmtoll EVR          HJF           LL_I3C_IsActiveFlag_HJ
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_HJ(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_HJF) == (I3C_EVR_HJF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Wake Up flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: I3C Internal clock not available on time to treat the falling edge on SCL.
+  * @rmtoll EVR          WKPF          LL_I3C_IsActiveFlag_WKP
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_WKP(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_WKPF) == (I3C_EVR_WKPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Get flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: A "get" type CCC have been received.
+  * @rmtoll EVR          GETF          LL_I3C_IsActiveFlag_GET
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GET(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_GETF) == (I3C_EVR_GETF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Get Status flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: A GETSTATUS Command have been received.
+  * @rmtoll EVR          STAF          LL_I3C_IsActiveFlag_STA
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STA(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_STAF) == (I3C_EVR_STAF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Dynamic Address Update flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: Own Dynamic Address have been updated.
+  * @rmtoll EVR          DAUPDF        LL_I3C_IsActiveFlag_DAUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DAUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_DAUPDF) == (I3C_EVR_DAUPDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Max Write Length flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: Max Write Length have been updated.
+  * @rmtoll EVR          MWLUPDF       LL_I3C_IsActiveFlag_MWLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MWLUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_MWLUPDF) == (I3C_EVR_MWLUPDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Max Read Length flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: Max Read Length have been updated.
+  * @rmtoll EVR          MRLUPDF       LL_I3C_IsActiveFlag_MRLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MRLUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_MRLUPDF) == (I3C_EVR_MRLUPDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Reset flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: A Reset Pattern have been received.
+  * @rmtoll EVR          RSTF          LL_I3C_IsActiveFlag_RST
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RST(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_RSTF) == (I3C_EVR_RSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Active State flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: The Activity State have been updated.
+  * @rmtoll EVR          ASUPDF        LL_I3C_IsActiveFlag_ASUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ASUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_ASUPDF) == (I3C_EVR_ASUPDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Interrupt Update flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: One or more Interrupt autorized have been updated.
+  * @rmtoll EVR          INTUPDF       LL_I3C_IsActiveFlag_INTUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_INTUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_INTUPDF) == (I3C_EVR_INTUPDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Define List Targets flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: A Define List Targets Command have been received.
+  * @rmtoll EVR          DEFF          LL_I3C_IsActiveFlag_DEF
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DEF(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_DEFF) == (I3C_EVR_DEFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Define List Group Addresses flag.
+  *         RESET: Clear default value.
+  *         SET: A Define List Group Addresses have been received.
+  * @rmtoll EVR          GRPF          LL_I3C_IsActiveFlag_GRP
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GRP(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->EVR, I3C_EVR_GRPF) == (I3C_EVR_GRPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Protocol Error flag.
+  *         RESET: Clear default value.
+  *         SET: Protocol error detected.
+  * @rmtoll SER          PERR          LL_I3C_IsActiveFlag_PERR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_PERR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SER, I3C_SER_PERR) == (I3C_SER_PERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of SCL Stall Error flag (target mode).
+  *         RESET: Clear default value.
+  *         SET: Target detected that SCL was stable for more than 125us during I3C SDR read.
+  * @rmtoll SER          STALL         LL_I3C_IsActiveFlag_STALL
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STALL(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SER, I3C_SER_STALL) == (I3C_SER_STALL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of RX or TX FIFO Overrun flag.
+  *         RESET: Clear default value.
+  *         SET: RX FIFO Full or TX FIFO Empty depending of direction of message.
+  * @rmtoll SER          DOVR          LL_I3C_IsActiveFlag_DOVR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DOVR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SER, I3C_SER_DOVR) == (I3C_SER_DOVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Control or Status FIFO Overrun flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: Status FIFO Full or Control FIFO Empty after Restart.
+  * @rmtoll SER          COVR          LL_I3C_IsActiveFlag_COVR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_COVR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SER, I3C_SER_COVR) == (I3C_SER_COVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Address not acknowledged flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: Controller detected that Target nacked static or dynamic address.
+  * @rmtoll SER          ANACK         LL_I3C_IsActiveFlag_ANACK
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ANACK(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SER, I3C_SER_ANACK) == (I3C_SER_ANACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Data not acknowledged flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: Controller detected that Target nacked Data byte.
+  * @rmtoll SER          DNACK         LL_I3C_IsActiveFlag_DNACK
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DNACK(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SER, I3C_SER_DNACK) == (I3C_SER_DNACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates the status of Data error flag (controller mode).
+  *         RESET: Clear default value.
+  *         SET: Controller detected data error during Controller-role handoff process.
+  * @rmtoll SER          DERR          LL_I3C_IsActiveFlag_DERR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DERR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->SER, I3C_SER_DERR) == (I3C_SER_DERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I3C_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Control FIFO Not Full interrupt.
+  * @rmtoll IER          CFNFIE        LL_I3C_EnableIT_CFNF
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_CFNF(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_CFNFIE);
+}
+
+/**
+  * @brief  Disable Control FIFO Not Full interrupt.
+  * @rmtoll IER          CFNFIE        LL_I3C_DisableIT_CFNF
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_CFNF(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_CFNFIE);
+}
+
+/**
+  * @brief  Check if Control FIFO Not Full interrupt is enabled or disabled.
+  * @rmtoll IER          CFNFIE        LL_I3C_IsEnabledIT_CFNF
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CFNF(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_CFNFIE) == (I3C_IER_CFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Status FIFO Not Empty interrupt.
+  * @rmtoll IER          SFNEIE        LL_I3C_EnableIT_SFNE
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_SFNE(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_SFNEIE);
+}
+
+/**
+  * @brief  Disable Status FIFO Not Empty interrupt.
+  * @rmtoll IER          SFNEIE        LL_I3C_DisableIT_SFNE
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_SFNE(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_SFNEIE);
+}
+
+/**
+  * @brief  Check if Status FIFO Not Empty interrupt is enabled or disabled.
+  * @rmtoll IER          SFNEIE        LL_I3C_IsEnabledIT_SFNE
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_SFNE(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_SFNEIE) == (I3C_IER_SFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Transmit FIFO Not Full interrupt.
+  * @rmtoll IER          TXFNFIE       LL_I3C_EnableIT_TXFNF
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_TXFNF(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Transmit FIFO Not Full interrupt.
+  * @rmtoll IER          TXFNFIE       LL_I3C_DisableIT_TXFNF
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_TXFNF(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_TXFNFIE);
+}
+
+/**
+  * @brief  Check if Transmit FIFO Not Full interrupt is enabled or disabled.
+  * @rmtoll IER          TXFNFIE       LL_I3C_IsEnabledIT_TXFNF
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_TXFNF(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_TXFNFIE) == (I3C_IER_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Receive FIFO Not Empty interrupt.
+  * @rmtoll IER          RXFNEIE       LL_I3C_EnableIT_RXFNE
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_RXFNE(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Receive FIFO Not Empty interrupt.
+  * @rmtoll IER          RXFNEIE       LL_I3C_DisableIT_RXFNE
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_RXFNE(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_RXFNEIE);
+}
+
+/**
+  * @brief  Check if Receive FIFO Not Empty interrupt is enabled or disabled.
+  * @rmtoll IER          RXFNEIE       LL_I3C_IsEnabledIT_RXFNE
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXFNE(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_RXFNEIE) == (I3C_IER_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Frame Complete interrupt.
+  * @rmtoll IER          FCIE          LL_I3C_EnableIT_FC
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_FC(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_FCIE);
+}
+
+/**
+  * @brief  Disable Frame Complete interrupt.
+  * @rmtoll IER          FCIE          LL_I3C_DisableIT_FC
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_FC(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_FCIE);
+}
+
+/**
+  * @brief  Check if Frame Complete interrupt is enabled or disabled.
+  * @rmtoll IER          FCIE          LL_I3C_IsEnabledIT_FC
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_FC(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_FCIE) == (I3C_IER_FCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Reception Target End interrupt.
+  * @rmtoll IER          RXTGTENDIE    LL_I3C_EnableIT_RXTGTEND
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_RXTGTEND(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE);
+}
+
+/**
+  * @brief  Disable Reception Target End interrupt.
+  * @rmtoll IER          RXTGTENDIE    LL_I3C_DisableIT_RXTGTEND
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_RXTGTEND(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE);
+}
+
+/**
+  * @brief  Check if Reception Target End interrupt is enabled or disabled.
+  * @rmtoll IER          RXTGTENDIE    LL_I3C_IsEnabledIT_RXTGTEND
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXTGTEND(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE) == (I3C_IER_RXTGTENDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Error interrupt.
+  * @rmtoll IER          ERRIE         LL_I3C_EnableIT_ERR
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_ERR(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_ERRIE);
+}
+
+/**
+  * @brief  Disable Error interrupt.
+  * @rmtoll IER          ERRIE         LL_I3C_DisableIT_ERR
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_ERR(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_ERRIE);
+}
+
+/**
+  * @brief  Check if Error interrupt is enabled or disabled.
+  * @rmtoll IER          ERRIE         LL_I3C_IsEnabledIT_ERR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ERR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_ERRIE) == (I3C_IER_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable IBI interrupt.
+  * @rmtoll IER          IBIIE         LL_I3C_EnableIT_IBI
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_IBI(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_IBIIE);
+}
+
+/**
+  * @brief  Disable IBI interrupt.
+  * @rmtoll IER          IBIIE         LL_I3C_DisableIT_IBI
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_IBI(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_IBIIE);
+}
+
+/**
+  * @brief  Check if IBI interrupt is enabled or disabled.
+  * @rmtoll IER          IBIIE         LL_I3C_IsEnabledIT_IBI
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBI(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_IBIIE) == (I3C_IER_IBIIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable IBI End interrupt.
+  * @rmtoll IER          IBIENDIE      LL_I3C_EnableIT_IBIEND
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_IBIEND(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_IBIENDIE);
+}
+
+/**
+  * @brief  Disable IBI End interrupt.
+  * @rmtoll IER          IBIENDIE      LL_I3C_DisableIT_IBIEND
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_IBIEND(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_IBIENDIE);
+}
+
+/**
+  * @brief  Check if IBI End interrupt is enabled or disabled.
+  * @rmtoll IER          IBIENDIE      LL_I3C_IsEnabledIT_IBIEND
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBIEND(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_IBIENDIE) == (I3C_IER_IBIENDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Controller-role interrupt.
+  * @rmtoll IER          CRIE          LL_I3C_EnableIT_CR
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_CR(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_CRIE);
+}
+
+/**
+  * @brief  Disable Controller-role interrupt.
+  * @rmtoll IER          CRIE          LL_I3C_DisableIT_CR
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_CR(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_CRIE);
+}
+
+/**
+  * @brief  Check if Controller-role interrupt is enabled or disabled.
+  * @rmtoll IER          CRIE          LL_I3C_IsEnabledIT_CR
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CR(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_CRIE) == (I3C_IER_CRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Controller-role Update interrupt.
+  * @rmtoll IER          CRUPDIE       LL_I3C_EnableIT_CRUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_CRUPD(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_CRUPDIE);
+}
+
+/**
+  * @brief  Disable Controller-role Update interrupt.
+  * @rmtoll IER          CRUPDIE       LL_I3C_DisableIT_CRUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_CRUPD(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_CRUPDIE);
+}
+
+/**
+  * @brief  Check if Controller-role Update interrupt is enabled or disabled.
+  * @rmtoll IER          CRUPDIE       LL_I3C_IsEnabledIT_CRUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CRUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_CRUPDIE) == (I3C_IER_CRUPDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Hot Join interrupt.
+  * @rmtoll IER          HJIE          LL_I3C_EnableIT_HJ
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_HJ(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_HJIE);
+}
+
+/**
+  * @brief  Disable Hot Join interrupt.
+  * @rmtoll IER          HJIE          LL_I3C_DisableIT_HJ
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_HJ(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_HJIE);
+}
+
+/**
+  * @brief  Check if Hot Join interrupt is enabled or disabled.
+  * @rmtoll IER          HJIE          LL_I3C_IsEnabledIT_HJ
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_HJ(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_HJIE) == (I3C_IER_HJIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Wake Up interrupt.
+  * @rmtoll IER          WKPIE         LL_I3C_EnableIT_WKP
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_WKP(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_WKPIE);
+}
+
+/**
+  * @brief  Disable Wake Up interrupt.
+  * @rmtoll IER          WKPIE         LL_I3C_DisableIT_WKP
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_WKP(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_WKPIE);
+}
+
+/**
+  * @brief  Check if Wake Up is enabled or disabled.
+  * @rmtoll IER          WKPIE         LL_I3C_IsEnabledIT_WKP
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_WKP(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_WKPIE) == (I3C_IER_WKPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Get Command interrupt.
+  * @rmtoll IER          GETIE         LL_I3C_EnableIT_GET
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_GET(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_GETIE);
+}
+
+/**
+  * @brief  Disable Get Command interrupt.
+  * @rmtoll IER          GETIE         LL_I3C_DisableIT_GET
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_GET(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_GETIE);
+}
+
+/**
+  * @brief  Check if Get Command is enabled or disabled.
+  * @rmtoll IER          GETIE         LL_I3C_IsEnabledIT_GET
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GET(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_GETIE) == (I3C_IER_GETIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Get Status interrupt.
+  * @rmtoll IER          STAIE         LL_I3C_EnableIT_STA
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_STA(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_STAIE);
+}
+
+/**
+  * @brief  Disable Get Status interrupt.
+  * @rmtoll IER          STAIE         LL_I3C_DisableIT_STA
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_STA(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_STAIE);
+}
+
+/**
+  * @brief  Check if Get Status interrupt is enabled or disabled.
+  * @rmtoll IER          STAIE         LL_I3C_IsEnabledIT_STA
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_STA(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_STAIE) == (I3C_IER_STAIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Dynamic Address Update interrupt.
+  * @rmtoll IER          DAUPDIE       LL_I3C_EnableIT_DAUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_DAUPD(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_DAUPDIE);
+}
+
+/**
+  * @brief  Disable Dynamic Address Update interrupt.
+  * @rmtoll IER          DAUPDIE       LL_I3C_DisableIT_DAUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_DAUPD(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_DAUPDIE);
+}
+
+/**
+  * @brief  Check if Dynamic Address Update interrupt is enabled or disabled.
+  * @rmtoll IER          DAUPDIE       LL_I3C_IsEnabledIT_DAUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DAUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_DAUPDIE) == (I3C_IER_DAUPDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Max Write Length Update interrupt.
+  * @rmtoll IER          MWLUPDIE      LL_I3C_EnableIT_MWLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_MWLUPD(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_MWLUPDIE);
+}
+
+/**
+  * @brief  Disable Max Write Length Update interrupt.
+  * @rmtoll IER          MWLUPDIE      LL_I3C_DisableIT_MWLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_MWLUPD(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_MWLUPDIE);
+}
+
+/**
+  * @brief  Check if Max Write Length Update interrupt is enabled or disabled.
+  * @rmtoll IER          MWLUPDIE      LL_I3C_IsEnabledIT_MWLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MWLUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_MWLUPDIE) == (I3C_IER_MWLUPDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Max Read Length Update interrupt.
+  * @rmtoll IER          MRLUPDIE      LL_I3C_EnableIT_MRLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_MRLUPD(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_MRLUPDIE);
+}
+
+/**
+  * @brief  Disable Max Read Length Update interrupt.
+  * @rmtoll IER          MRLUPDIE      LL_I3C_DisableIT_MRLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_MRLUPD(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_MRLUPDIE);
+}
+
+/**
+  * @brief  Check if Max Read Length Update interrupt is enabled or disabled.
+  * @rmtoll IER          MRLUPDIE      LL_I3C_IsEnabledIT_MRLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MRLUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_MRLUPDIE) == (I3C_IER_MRLUPDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Reset interrupt.
+  * @rmtoll IER          RSTIE         LL_I3C_EnableIT_RST
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_RST(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_RSTIE);
+}
+
+/**
+  * @brief  Disable Reset interrupt.
+  * @rmtoll IER          RSTIE         LL_I3C_DisableIT_RST
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_RST(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_RSTIE);
+}
+
+/**
+  * @brief  Check if Reset interrupt is enabled or disabled.
+  * @rmtoll IER          RSTIE         LL_I3C_IsEnabledIT_RST
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RST(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_RSTIE) == (I3C_IER_RSTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Activity State Update interrupt.
+  * @rmtoll IER          ASUPDIE       LL_I3C_EnableIT_ASUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_ASUPD(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_ASUPDIE);
+}
+
+/**
+  * @brief  Disable Activity State Update interrupt.
+  * @rmtoll IER          ASUPDIE       LL_I3C_DisableIT_ASUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_ASUPD(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_ASUPDIE);
+}
+
+/**
+  * @brief  Check if Activity State Update interrupt is enabled or disabled.
+  * @rmtoll IER          ASUPDIE       LL_I3C_IsEnabledIT_ASUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ASUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_ASUPDIE) == (I3C_IER_ASUPDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Interrupt Update interrupt.
+  * @rmtoll IER          INTUPDIE      LL_I3C_EnableIT_INTUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_INTUPD(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_INTUPDIE);
+}
+
+/**
+  * @brief  Disable Interrupt Update interrupt.
+  * @rmtoll IER          INTUPDIE      LL_I3C_DisableIT_INTUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_INTUPD(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_INTUPDIE);
+}
+
+/**
+  * @brief  Check if Interrupt Update interrupt is enabled or disabled.
+  * @rmtoll IER          INTUPDIE      LL_I3C_IsEnabledIT_INTUPD
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_INTUPD(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_INTUPDIE) == (I3C_IER_INTUPDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Define List Target interrupt.
+  * @rmtoll IER          DEFIE         LL_I3C_EnableIT_DEF
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_DEF(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_DEFIE);
+}
+
+/**
+  * @brief  Disable Define List Target interrupt.
+  * @rmtoll IER          DEFIE         LL_I3C_DisableIT_DEF
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_DEF(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_DEFIE);
+}
+
+/**
+  * @brief  Check if Define List Target interrupt is enabled or disabled.
+  * @rmtoll IER          DEFIE         LL_I3C_IsEnabledIT_DEF
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DEF(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_DEFIE) == (I3C_IER_DEFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Define List Group Addresses interrupt.
+  * @rmtoll IER          GRPIE         LL_I3C_EnableIT_GRP
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_EnableIT_GRP(I3C_TypeDef *I3Cx)
+{
+  SET_BIT(I3Cx->IER, I3C_IER_GRPIE);
+}
+
+/**
+  * @brief  Disable Define List Group Addresses interrupt.
+  * @rmtoll IER          GRPIE         LL_I3C_DisableIT_GRP
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_DisableIT_GRP(I3C_TypeDef *I3Cx)
+{
+  CLEAR_BIT(I3Cx->IER, I3C_IER_GRPIE);
+}
+
+/**
+  * @brief  Check if Define List Group Addresses interrupt is enabled or disabled.
+  * @rmtoll IER          GRPIE         LL_I3C_IsEnabledIT_GRP
+  * @param  I3Cx I3C Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GRP(const I3C_TypeDef *I3Cx)
+{
+  return ((READ_BIT(I3Cx->IER, I3C_IER_GRPIE) == (I3C_IER_GRPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup I3C_LL_EF_FLAG_management FLAG_management
+  * @{
+  */
+
+/**
+  * @brief  Clear Frame Complete flag (controller and target mode).
+  * @rmtoll CEVR         CFCF          LL_I3C_ClearFlag_FC
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_FC(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CFCF);
+}
+
+/**
+  * @brief  Clear Reception Target End flag (controller mode).
+  * @rmtoll CEVR         CRXTGTENDF    LL_I3C_ClearFlag_RXTGTEND
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_RXTGTEND(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRXTGTENDF);
+}
+
+/**
+  * @brief  Clear Error flag (controller and target mode).
+  * @rmtoll CEVR         CERRF         LL_I3C_ClearFlag_ERR
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_ERR(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CERRF);
+}
+
+/**
+  * @brief  Clear IBI flag (controller mode).
+  * @rmtoll CEVR         CIBIF         LL_I3C_ClearFlag_IBI
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_IBI(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIF);
+}
+
+/**
+  * @brief  Clear IBI End flag (target mode).
+  * @rmtoll CEVR         CIBIENDF      LL_I3C_ClearFlag_IBIEND
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_IBIEND(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIENDF);
+}
+
+/**
+  * @brief  Clear Controller-role Request flag (controller mode).
+  * @rmtoll CEVR         CCRF          LL_I3C_ClearFlag_CR
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_CR(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRF);
+}
+
+/**
+  * @brief  Clear Controller-role Request Update flag (target mode).
+  * @rmtoll CEVR         CCRUPDF       LL_I3C_ClearFlag_CRUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_CRUPD(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRUPDF);
+}
+
+/**
+  * @brief  Clear Hot Join flag (controller mode).
+  * @rmtoll CEVR         CHJF          LL_I3C_ClearFlag_HJ
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_HJ(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CHJF);
+}
+
+/**
+  * @brief  Clear Wake Up flag (target mode).
+  * @rmtoll CEVR         CWKPF         LL_I3C_ClearFlag_WKP
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_WKP(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CWKPF);
+}
+
+/**
+  * @brief  Clear Get flag (target mode).
+  * @rmtoll CEVR         CGETF         LL_I3C_ClearFlag_GET
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_GET(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGETF);
+}
+
+/**
+  * @brief  Clear Get Status flag (target mode).
+  * @rmtoll CEVR         CSTAF         LL_I3C_ClearFlag_STA
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_STA(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CSTAF);
+}
+
+/**
+  * @brief  Clear Dynamic Address Update flag (target mode).
+  * @rmtoll CEVR         CDAUPDF       LL_I3C_ClearFlag_DAUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_DAUPD(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDAUPDF);
+}
+
+/**
+  * @brief  Clear Max Write Length flag (target mode).
+  * @rmtoll CEVR         CMWLUPDF      LL_I3C_ClearFlag_MWLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_MWLUPD(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMWLUPDF);
+}
+
+/**
+  * @brief  Clear Max Read Length flag (target mode).
+  * @rmtoll CEVR         CMRLUPDF      LL_I3C_ClearFlag_MRLUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_MRLUPD(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMRLUPDF);
+}
+
+/**
+  * @brief  Clear Reset flag (target mode).
+  * @rmtoll CEVR         CRSTF         LL_I3C_ClearFlag_RST
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_RST(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRSTF);
+}
+
+/**
+  * @brief  Clear Active State flag (target mode).
+  * @rmtoll CEVR         CASUPDF       LL_I3C_ClearFlag_ASUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_ASUPD(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CASUPDF);
+}
+
+/**
+  * @brief  Clear Interrupt Update flag (target mode).
+  * @rmtoll CEVR         CINTUPDF      LL_I3C_ClearFlag_INTUPD
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_INTUPD(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CINTUPDF);
+}
+
+/**
+  * @brief  Clear Define List Targets flag (target mode).
+  * @rmtoll CEVR         CDEFF         LL_I3C_ClearFlag_DEF
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_DEF(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDEFF);
+}
+
+/**
+  * @brief  Clear Define List Group Addresses flag.
+  * @rmtoll CEVR         CGRPF         LL_I3C_ClearFlag_GRP
+  * @param  I3Cx I3C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I3C_ClearFlag_GRP(I3C_TypeDef *I3Cx)
+{
+  WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGRPF);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I3C_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_I3C_Init(I3C_TypeDef *I3Cx, LL_I3C_InitTypeDef *I3C_InitStruct, uint32_t Mode);
+ErrorStatus LL_I3C_DeInit(const I3C_TypeDef *I3Cx);
+void LL_I3C_StructInit(LL_I3C_InitTypeDef *I3C_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I3C1 || I3C2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32N6xx_LL_I3C_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_icache.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_icache.h
new file mode 100644
index 000000000..8da956812
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_icache.h
@@ -0,0 +1,453 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_icache.h
+  * @author  MCD Application Team
+  * @brief   Header file of ICACHE LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32N6xx_LL_ICACHE_H
+#define STM32N6xx_LL_ICACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(ICACHE)
+
+/** @defgroup ICACHE_LL ICACHE
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants -------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
+  * @{
+  */
+
+/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
+  * @{
+  */
+#define LL_ICACHE_1WAY                 0U                /*!< 1-way cache (direct mapped cache) */
+#define LL_ICACHE_4WAYS                ICACHE_CR_WAYSEL  /*!< 4-ways set associative cache (default) */
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
+  * @{
+  */
+#define LL_ICACHE_MONITOR_HIT          ICACHE_CR_HITMEN                       /*!< Hit monitor counter */
+#define LL_ICACHE_MONITOR_MISS         ICACHE_CR_MISSMEN                      /*!< Miss monitor counter */
+#define LL_ICACHE_MONITOR_ALL          (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_ICACHE_ReadReg function
+  * @{
+  */
+#define LL_ICACHE_SR_BUSYF             ICACHE_SR_BUSYF     /*!< Busy flag */
+#define LL_ICACHE_SR_BSYENDF           ICACHE_SR_BSYENDF   /*!< Busy end flag */
+#define LL_ICACHE_SR_ERRF              ICACHE_SR_ERRF      /*!< Cache error flag */
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_ICACHE_WriteReg function
+  * @{
+  */
+#define LL_ICACHE_FCR_CBSYENDF         ICACHE_FCR_CBSYENDF /*!< Busy end flag */
+#define LL_ICACHE_FCR_CERRF            ICACHE_FCR_CERRF    /*!< Cache error flag */
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_ICACHE_ReadReg and  LL_ICACHE_WriteReg functions
+  * @{
+  */
+#define LL_ICACHE_IER_BSYENDIE         ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
+#define LL_ICACHE_IER_ERRIE            ICACHE_IER_ERRIE    /*!< Cache error interrupt */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macros ----------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
+  * @{
+  */
+
+/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ICACHE register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ICACHE register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
+  * @{
+  */
+
+/** @defgroup ICACHE_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the ICACHE.
+  * @rmtoll CR           EN            LL_ICACHE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_Enable(void)
+{
+  SET_BIT(ICACHE->CR, ICACHE_CR_EN);
+}
+
+/**
+  * @brief  Disable the ICACHE.
+  * @rmtoll CR           EN            LL_ICACHE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_Disable(void)
+{
+  CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
+}
+
+/**
+  * @brief  Return if ICACHE is enabled or not.
+  * @rmtoll CR           EN            LL_ICACHE_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
+{
+  return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select the ICACHE operating mode.
+  * @rmtoll CR           WAYSEL        LL_ICACHE_SetMode
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_ICACHE_1WAY
+  *         @arg @ref LL_ICACHE_4WAYS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
+{
+  MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
+}
+
+/**
+  * @brief  Get the selected ICACHE operating mode.
+  * @rmtoll CR           WAYSEL        LL_ICACHE_GetMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ICACHE_1WAY
+  *         @arg @ref LL_ICACHE_4WAYS
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
+{
+  return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
+}
+
+/**
+  * @brief  Invalidate the ICACHE.
+  * @note   Until the BSYEND flag is set, the cache is bypassed.
+  * @rmtoll CR           CACHEINV      LL_ICACHE_Invalidate
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_Invalidate(void)
+{
+  SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_LL_EF_Monitors Monitors
+  * @{
+  */
+
+/**
+  * @brief  Enable the hit/miss monitor(s).
+  * @rmtoll CR           HITMEN        LL_ICACHE_EnableMonitors
+  * @rmtoll CR           MISSMEN       LL_ICACHE_EnableMonitors
+  * @param  Monitors This parameter can be one or a combination of the following values:
+  *         @arg @ref LL_ICACHE_MONITOR_HIT
+  *         @arg @ref LL_ICACHE_MONITOR_MISS
+  *         @arg @ref LL_ICACHE_MONITOR_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
+{
+  SET_BIT(ICACHE->CR, Monitors);
+}
+
+/**
+  * @brief  Disable the hit/miss monitor(s).
+  * @rmtoll CR           HITMEN        LL_ICACHE_DisableMonitors
+  * @rmtoll CR           MISSMEN       LL_ICACHE_DisableMonitors
+  * @param  Monitors This parameter can be one or a combination of the following values:
+  *         @arg @ref LL_ICACHE_MONITOR_HIT
+  *         @arg @ref LL_ICACHE_MONITOR_MISS
+  *         @arg @ref LL_ICACHE_MONITOR_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
+{
+  CLEAR_BIT(ICACHE->CR, Monitors);
+}
+
+/**
+  * @brief  Check if the monitor(s) is(are) enabled or disabled.
+  * @rmtoll CR           HITMEN        LL_ICACHE_IsEnabledMonitors
+  * @rmtoll CR           MISSMEN       LL_ICACHE_IsEnabledMonitors
+  * @param  Monitors This parameter can be one or a combination of the following values:
+  *         @arg @ref LL_ICACHE_MONITOR_HIT
+  *         @arg @ref LL_ICACHE_MONITOR_MISS
+  *         @arg @ref LL_ICACHE_MONITOR_ALL
+  * @retval State of parameter value (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
+{
+  return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Reset the hit/miss monitor(s).
+  * @rmtoll CR           HITMRST       LL_ICACHE_ResetMonitors
+  * @rmtoll CR           MISSMRST      LL_ICACHE_ResetMonitors
+  * @param  Monitors This parameter can be one or a combination of the following values:
+  *         @arg @ref LL_ICACHE_MONITOR_HIT
+  *         @arg @ref LL_ICACHE_MONITOR_MISS
+  *         @arg @ref LL_ICACHE_MONITOR_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
+{
+  /* Reset */
+  SET_BIT(ICACHE->CR, (Monitors << 2U));
+  /* Release reset */
+  CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
+}
+
+/**
+  * @brief  Get the Hit monitor.
+  * @note   Upon reaching the 32-bit maximum value, hit monitor does not wrap.
+  * @rmtoll HMONR        HITMON        LL_ICACHE_GetHitMonitor
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
+{
+  return (ICACHE->HMONR);
+}
+
+/**
+  * @brief  Get the Miss monitor.
+  * @note   Upon reaching the 16-bit maximum value, miss monitor does not wrap.
+  * @rmtoll MMONR        MISSMON       LL_ICACHE_GetMissMonitor
+  * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
+{
+  return (ICACHE->MMONR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable BSYEND interrupt.
+  * @rmtoll IER          BSYENDIE      LL_ICACHE_EnableIT_BSYEND
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
+{
+  SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+}
+
+/**
+  * @brief  Disable BSYEND interrupt.
+  * @rmtoll IER          BSYENDIE      LL_ICACHE_DisableIT_BSYEND
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
+{
+  CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+}
+
+/**
+  * @brief  Check if the BSYEND Interrupt is enabled or disabled.
+  * @rmtoll IER          BSYENDIE      LL_ICACHE_IsEnabledIT_BSYEND
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
+{
+  return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable ERR interrupt.
+  * @rmtoll IER          ERRIE         LL_ICACHE_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
+{
+  SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+}
+
+/**
+  * @brief  Disable ERR interrupt.
+  * @rmtoll IER          ERRIE        LL_ICACHE_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
+{
+  CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+}
+
+/**
+  * @brief  Check if the ERR Interrupt is enabled or disabled.
+  * @rmtoll IER          ERRIE         LL_ICACHE_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
+{
+  return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate the status of an ongoing operation flag.
+  * @rmtoll SR           BUSYF         LL_ICACHE_IsActiveFlag_BUSY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
+{
+  return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of an operation end flag.
+  * @rmtoll SR           BSYEND       LL_ICACHE_IsActiveFlag_BSYEND
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
+{
+  return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate the status of an error flag.
+  * @rmtoll SR           ERRF          LL_ICACHE_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
+{
+  return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear busy end of operation flag.
+  * @rmtoll FCR          CBSYENDF      LL_ICACHE_ClearFlag_BSYEND
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
+{
+  WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+}
+
+/**
+  * @brief  Clear error flag.
+  * @rmtoll FCR          ERRF          LL_ICACHE_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
+{
+  WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ICACHE */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_ICACHE_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_iwdg.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_iwdg.h
new file mode 100644
index 000000000..5f384cd7d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_iwdg.h
@@ -0,0 +1,453 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_iwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of IWDG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_IWDG_H
+#define STM32N6xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+  * @{
+  */
+#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
+#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
+  * @{
+  */
+#define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
+#define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
+  * @{
+  */
+#define LL_IWDG_PRESCALER_4                0x00000000U                                   /*!< Divider by 4    */
+#define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                                /*!< Divider by 8    */
+#define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                                /*!< Divider by 16   */
+#define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                 /*!< Divider by 32   */
+#define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                                /*!< Divider by 64   */
+#define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                 /*!< Divider by 128  */
+#define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                 /*!< Divider by 256  */
+#define LL_IWDG_PRESCALER_512              (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0)  /*!< Divider by 512  */
+#define LL_IWDG_PRESCALER_1024             IWDG_PR_PR_3                                  /*!< Divider by 1024 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in IWDG register
+  * @param  __INSTANCE__ IWDG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+  * @{
+  */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Start the Independent Watchdog
+  * @note   Except if the hardware watchdog option is selected
+  * @rmtoll KR           KEY           LL_IWDG_Enable
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+  * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+  * @brief  Select the prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_SetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  *         @arg @ref LL_IWDG_PRESCALER_512
+  *         @arg @ref LL_IWDG_PRESCALER_1024
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+  WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+  * @brief  Get the selected prescaler of the IWDG
+  * @rmtoll PR           PR            LL_IWDG_GetPrescaler
+  * @param  IWDGx IWDG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_IWDG_PRESCALER_4
+  *         @arg @ref LL_IWDG_PRESCALER_8
+  *         @arg @ref LL_IWDG_PRESCALER_16
+  *         @arg @ref LL_IWDG_PRESCALER_32
+  *         @arg @ref LL_IWDG_PRESCALER_64
+  *         @arg @ref LL_IWDG_PRESCALER_128
+  *         @arg @ref LL_IWDG_PRESCALER_256
+  *         @arg @ref LL_IWDG_PRESCALER_512
+  *         @arg @ref LL_IWDG_PRESCALER_1024
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
+{
+  return (READ_REG(IWDGx->PR));
+}
+
+/**
+  * @brief  Specify the IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+  WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+  * @brief  Get the specified IWDG down-counter reload value
+  * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
+{
+  return (READ_REG(IWDGx->RLR));
+}
+
+/**
+  * @brief  Specify high limit of the window value to be compared to the down-counter.
+  * @rmtoll WINR         WIN           LL_IWDG_SetWindow
+  * @param  IWDGx IWDG Instance
+  * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
+{
+  WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+  * @brief  Get the high limit of the window value specified.
+  * @rmtoll WINR         WIN           LL_IWDG_GetWindow
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx)
+{
+  return (READ_REG(IWDGx->WINR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Specify comparator value that will be used to trig Early Wakeup interrupt
+  * @rmtoll EWCR         EWIT          LL_IWDG_SetEwiTime
+  * @param  IWDGx IWDG Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=0x0FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_SetEwiTime(IWDG_TypeDef *IWDGx, uint32_t Time)
+{
+  MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time);
+}
+
+/**
+  * @brief  Get the Early Wakeup interrupt comparator value
+  * @rmtoll EWCR         EWIT          LL_IWDG_GetEwiTime
+  * @param  IWDGx IWDG Instance
+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+  */
+__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(const IWDG_TypeDef *IWDGx)
+{
+  return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT));
+}
+
+/**
+  * @brief  Enable Early wakeup interrupt
+  * @rmtoll EWCR         EWIE          LL_IWDG_EnableIT_EWI
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_EnableIT_EWI(IWDG_TypeDef *IWDGx)
+{
+  SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE);
+}
+
+/**
+  * @brief  Disable Early wakeup interrupt
+  * @rmtoll EWCR         EWIE          LL_IWDG_DisableIT_EWI
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_DisableIT_EWI(IWDG_TypeDef *IWDGx)
+{
+  CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE);
+}
+
+/**
+  * @brief  Indicates whether Early wakeup interrupt is enable
+  * @rmtoll EWCR         EWIE          LL_IWDG_IsEnabledIT_EWI
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsEnabledIT_EWI(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if flag Prescaler Value Update is set or not
+  * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if flag Reload Value Update is set or not
+  * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if flag Window Value Update is set or not
+  * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if flag EWI Value Update is set or not
+  * @rmtoll SR           EVU           LL_IWDG_IsActiveFlag_EWU
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->SR, IWDG_SR_EWU) == (IWDG_SR_EWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if all flags Prescaler, Reload, Window & Early Interrupt Value Update are reset or not
+  * @rmtoll SR           PVU           LL_IWDG_IsReady\n
+  *         SR           RVU           LL_IWDG_IsReady\n
+  *         SR           WVU           LL_IWDG_IsReady\n
+  *         SR           EWU           LL_IWDG_IsReady
+  * @param  IWDGx IWDG Instance
+  * @retval State of bits (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | IWDG_SR_EWU) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if IWDG has been started or not
+  * @rmtoll SR           ONF           LL_IWDG_IsActiveFlag_ONF
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_ONF(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Early Wakeup interrupt flag is set or not
+  * @rmtoll SR           EWIF          LL_IWDG_IsActiveFlag_EWIF
+  * @param  IWDGx IWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(const IWDG_TypeDef *IWDGx)
+{
+  return ((READ_BIT(IWDGx->SR, IWDG_SR_EWIF) == (IWDG_SR_EWIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Early Wakeup interrupt flag
+  * @rmtoll EWCR         ICR          LL_IWDG_ClearFlag_EWIF
+  * @param  IWDGx IWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_IWDG_ClearFlag_EWIF(IWDG_TypeDef *IWDGx)
+{
+  WRITE_REG(IWDGx->ICR, IWDG_ICR_EWIC);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* IWDG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_IWDG_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_lptim.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_lptim.h
new file mode 100644
index 000000000..b98701859
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_lptim.h
@@ -0,0 +1,2447 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_lptim.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPTIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_LPTIM_H
+#define STM32N6xx_LL_LPTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
+
+/** @defgroup LPTIM_LL LPTIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
+  * @{
+  */
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
+{
+  0U,                              /* CC1P */
+  16U                              /* CC2P */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
+{
+  0U,                              /* IC1F */
+  16U                              /* IC2F */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
+{
+  0U,                              /* IC1PSC */
+  16U                              /* IC2PSC */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
+{
+  0U,                              /* CC1SEL */
+  16U                              /* CC2SEL */
+};
+
+static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
+{
+  LPTIM_CCMR1_CC1E_Pos,            /* CC1E */
+  LPTIM_CCMR1_CC2E_Pos             /* CC2E */
+};
+
+static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
+{
+  {2, 7, 9, 13},
+  {3, 5, 6, 8},
+  {2, 3, 4, 5},
+  {2, 2, 3, 3},
+  {2, 2, 2, 2},
+  {2, 2, 2, 2},
+  {2, 2, 2, 2},
+  {2, 2, 2, 2}
+
+};
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  LPTIM Init structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
+                                This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
+
+                                This feature can be modified afterwards using unitary
+                                function @ref LL_LPTIM_SetClockSource().*/
+
+  uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
+                                This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
+
+                                This feature can be modified afterwards using using unitary
+                                function @ref LL_LPTIM_SetPrescaler().*/
+
+  uint32_t Waveform;       /*!< Specifies the waveform shape.
+                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
+
+                                This feature can be modified afterwards using unitary
+                                function @ref LL_LPTIM_SetWaveform().*/
+} LL_LPTIM_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function
+  * @{
+  */
+#define LL_LPTIM_ISR_CMP1OK                   LPTIM_ISR_CMP1OK   /*!< Compare register 1 update OK */
+#define LL_LPTIM_ISR_CMP2OK                   LPTIM_ISR_CMP2OK   /*!< Compare register 2 update OK */
+#define LL_LPTIM_ISR_CC1IF                    LPTIM_ISR_CC1IF    /*!< Capture/Compare 1 interrupt flag */
+#define LL_LPTIM_ISR_CC2IF                    LPTIM_ISR_CC2IF    /*!< Capture/Compare 2 interrupt flag */
+#define LL_LPTIM_ISR_CC1OF                    LPTIM_ISR_CC1OF    /*!< Capture/Compare 1 over-capture flag */
+#define LL_LPTIM_ISR_CC2OF                    LPTIM_ISR_CC2OF    /*!< Capture/Compare 2 over-capture flag */
+#define LL_LPTIM_ISR_DIEROK                   LPTIM_ISR_DIEROK   /*!< Interrupt enable register update OK */
+#define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */
+#define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */
+#define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */
+#define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */
+#define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */
+#define LL_LPTIM_ISR_UE                       LPTIM_ISR_UE       /*!< Update event */
+#define LL_LPTIM_ISR_REPOK                    LPTIM_ISR_REPOK    /*!< Repetition register update OK */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions
+  * @{
+  */
+#define LL_LPTIM_DIER_CMP1OKIE                 LPTIM_DIER_CMP1OKIE   /*!< Compare register 1 update OK */
+#define LL_LPTIM_DIER_CMP2OKIE                 LPTIM_DIER_CMP2OKIE   /*!< Compare register 2 update OK */
+#define LL_LPTIM_DIER_CC1IFIE                  LPTIM_DIER_CC1IE      /*!< Capture/Compare 1 interrupt flag */
+#define LL_LPTIM_DIER_CC2IFIE                  LPTIM_DIER_CC2IE      /*!< Capture/Compare 2 interrupt flag */
+#define LL_LPTIM_DIER_CC1OFIE                  LPTIM_DIER_CC1OIE     /*!< Capture/Compare 1 over-capture flag */
+#define LL_LPTIM_DIER_CC2OFIE                  LPTIM_DIER_CC2OIE     /*!< Capture/Compare 2 over-capture flag */
+#define LL_LPTIM_DIER_ARRMIE                   LPTIM_DIER_ARRMIE     /*!< Autoreload match */
+#define LL_LPTIM_DIER_EXTTRIGIE                LPTIM_DIER_EXTTRIGIE  /*!< External trigger edge event */
+#define LL_LPTIM_DIER_ARROKIE                  LPTIM_DIER_ARROKIE    /*!< Autoreload register update OK */
+#define LL_LPTIM_DIER_UPIE                     LPTIM_DIER_UPIE       /*!< Counter direction change down to up */
+#define LL_LPTIM_DIER_DOWNIE                   LPTIM_DIER_DOWNIE     /*!< Counter direction change up to down */
+#define LL_LPTIM_DIER_UEIE                     LPTIM_DIER_UEIE       /*!< Update event */
+#define LL_LPTIM_DIER_REPOKIE                  LPTIM_DIER_REPOKIE    /*!< Repetition register update OK */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
+  * @{
+  */
+#define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
+#define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
+  * @{
+  */
+#define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/
+#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
+  * @{
+  */
+#define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/
+#define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
+  * @{
+  */
+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE /*!<LPTIM  generates a Set Once waveform*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
+  * @{
+  */
+#define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
+#define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CCMR1_CC1P_0      /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_LPTIM_CHANNEL_CH1                  0x00000000U     /*!< LPTIM input/output channel 1 */
+#define LL_LPTIM_CHANNEL_CH2                  0x00000001U     /*!< LPTIM input/output channel 2 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
+  * @{
+  */
+#define LL_LPTIM_ICPSC_DIV1                   0x00000000UL                                  /*!< Capture performed each time an edge is detected on the capture input */
+#define LL_LPTIM_ICPSC_DIV2                   LPTIM_CCMR1_IC1PSC_0                          /*!< Capture performed once every 2 events                                */
+#define LL_LPTIM_ICPSC_DIV4                   LPTIM_CCMR1_IC1PSC_1                          /*!< Capture performed once every 4 events                                */
+#define LL_LPTIM_ICPSC_DIV8                   (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1)   /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
+  * @{
+  */
+#define LL_LPTIM_ICFLT_CLOCK_DIV1             0x00000000UL                            /*!< any external input capture signal level change is considered as a valid transition */
+#define LL_LPTIM_ICFLT_CLOCK_DIV2             LPTIM_CCMR1_IC1F_0                      /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
+#define LL_LPTIM_ICFLT_CLOCK_DIV4             LPTIM_CCMR1_IC1F_1                      /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
+#define LL_LPTIM_ICFLT_CLOCK_DIV8             (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY  Input Capture Polarity
+  * @{
+  */
+#define LL_LPTIM_ICPOLARITY_RISING            0x00000000UL                              /*!< Capture/Compare input rising polarity */
+#define LL_LPTIM_ICPOLARITY_FALLING           LPTIM_CCMR1_CC1P_0                        /*!< Capture/Compare input falling polarity */
+#define LL_LPTIM_ICPOLARITY_RISING_FALLING    (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1)   /*!< Capture/Compare input rising and falling polarities */
+/**
+  * @}
+  */
+/** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection  Input Capture selection
+  * @{
+  */
+#define LL_LPTIM_CCMODE_OUTPUT_PWM            0x00000000UL                              /*!< Select PWM mode */
+#define LL_LPTIM_CCMODE_INPUTCAPTURE          LPTIM_CCMR1_CC1SEL                        /*!< Select Input Capture mode*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
+  * @{
+  */
+#define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/
+#define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/
+#define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/
+#define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
+#define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/
+#define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
+#define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
+#define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
+  * @{
+  */
+#define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                                          /*!<External input trigger is connected to TIMx_ETR input*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to RTC Alarm A*/
+#define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to RTC Alarm B*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 1*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to RTC Tamper 2*/
+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 3*/
+#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A        (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to SAI2 FS A output */
+#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B        (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to SAI2 FS B output */
+#define LL_LPTIM_TRIG_SOURCE_LPTIM2_CH1       LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to LPTIM2 Channel 1 */
+#define LL_LPTIM_TRIG_SOURCE_LPTIM3_CH1       LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to LPTIM3 Channel 1 */
+#define LL_LPTIM_TRIG_SOURCE_LPTIM4_OUT       (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to LPTIM4 Output */
+#define LL_LPTIM_TRIG_SOURCE_LPTIM5_OUT       LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to LPTIM5 Output */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
+  * @{
+  */
+#define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U         /*!<Any trigger active level change is considered as a valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
+#define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
+  * @{
+  */
+#define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
+#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
+  * @{
+  */
+#define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U      /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
+#define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
+  * @{
+  */
+#define LL_LPTIM_CLK_FILTER_NONE              0x00000000U        /*!<Any external clock signal level change is considered as a valid transition*/
+#define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
+#define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
+  * @{
+  */
+#define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
+#define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
+  * @{
+  */
+#define LL_LPTIM_INPUT1_SRC_GPIO         0x00000000UL                  /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
+  * @{
+  */
+#define LL_LPTIM_INPUT2_SRC_GPIO         0x00000000UL                  /*!< For LPTIM1, LPTIM2 and LPTIM3 */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
+  * @{
+  */
+#define LL_LPTIM_LPTIM1_IC1_RMP_GPIO     0x00000000UL                 /*!< IC1 connected to GPIO */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
+  * @{
+  */
+#define LL_LPTIM_LPTIM1_IC2_RMP_GPIO     0x00000000UL                 /*!< IC2 connected to GPIO */
+#define LL_LPTIM_LPTIM1_IC2_RMP_LSI      LPTIM_CFGR2_IC2SEL_0         /*!< IC2 connected to LSI */
+#define LL_LPTIM_LPTIM1_IC2_RMP_LSE      LPTIM_CFGR2_IC2SEL_1         /*!< IC2 connected to LSE */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
+  * @{
+  */
+#define LL_LPTIM_LPTIM2_IC1_RMP_GPIO           0x00000000UL                 /*!< IC1 connected to GPIO */
+#define LL_LPTIM_LPTIM2_IC1_RMP_I3C1_IBIACK    LPTIM_CFGR2_IC1SEL_0         /*!< IC1 connected to I3C1 IBI ACK */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
+  * @{
+  */
+#define LL_LPTIM_LPTIM2_IC2_RMP_GPIO         0x00000000UL                                  /*!< IC2 connected to GPIO */
+#define LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024     LPTIM_CFGR2_IC2SEL_0                          /*!< IC2 connected to HSI/1024 */
+#define LL_LPTIM_LPTIM2_IC2_RMP_MSI_128      LPTIM_CFGR2_IC2SEL_1                          /*!< IC2 connected to MSI/128 */
+#define LL_LPTIM_LPTIM2_IC2_RMP_I3C2_IBIACK  (LPTIM_CFGR2_IC2SEL_1 | LPTIM_CFGR2_IC2SEL_0) /*!< IC2 connected to I3C2 IBI ACK */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
+  * @{
+  */
+#define LL_LPTIM_LPTIM3_IC1_RMP_GPIO           0x00000000UL                 /*!< IC1 connected to GPIO */
+#define LL_LPTIM_LPTIM3_IC1_RMP_I3C1_IBIACK    LPTIM_CFGR2_IC1SEL_0         /*!< IC1 connected to I3C1 IBI ACK */
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_EC_LPTIM3_IC2_RMP LPTIM3 Input Ch2 Remap
+  * @{
+  */
+
+#define LL_LPTIM_LPTIM3_IC2_RMP_GPIO           0x00000000UL                            /*!< IC2 connected to GPIO */
+#define LL_LPTIM_LPTIM3_IC2_RMP_I3C2_IBIACK    LPTIM_CFGR2_IC2SEL_0                    /*!< IC2 connected to I3C2 IBI ACK */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
+  * @{
+  */
+
+/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPTIM register
+  * @param  __INSTANCE__ LPTIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+
+/**
+  * @brief  LPTimer Input Capture Get Offset(in counter step unit)
+  * @note   The real capture value corresponding to the input capture trigger can be calculated using
+  *         the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
+  *         The Offset value is depending on the glitch filter value for the channel
+  *         and the value of the prescaler for the kernel clock.
+  *         Please check Errata Sheet V1_8 for more details under "variable latency
+  *         on input capture channel" section.
+  * @param  __PSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
+  * @param  __FLT__ This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
+  * @retval offset value
+  */
+#define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
+  [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
+  [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_LPTIM_ClearFLAG_CMPM  LL_LPTIM_ClearFlag_CMPM
+#define LL_LPTIM_ClearFLAG_CC1   LL_LPTIM_ClearFlag_CC1
+#define LL_LPTIM_ClearFLAG_CC2   LL_LPTIM_ClearFlag_CC2
+#define LL_LPTIM_ClearFLAG_CC1O  LL_LPTIM_ClearFlag_CC1O
+#define LL_LPTIM_ClearFLAG_CC2O  LL_LPTIM_ClearFlag_CC2O
+#define LL_LPTIM_ClearFLAG_ARRM  LL_LPTIM_ClearFlag_ARRM
+/**
+@endcond
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the LPTIM instance
+  * @note After setting the ENABLE bit, a delay of two counter clock is needed
+  *       before the LPTIM instance is actually enabled.
+  * @rmtoll CR           ENABLE        LL_LPTIM_Enable
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+  * @brief  Disable the LPTIM instance
+  * @rmtoll CR           ENABLE        LL_LPTIM_Disable
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM instance is enabled.
+  * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Starts the LPTIM counter in the desired mode.
+  * @note LPTIM instance must be enabled before starting the counter.
+  * @note It is possible to change on the fly from One Shot mode to
+  *       Continuous mode.
+  * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n
+  *         CR           SNGSTRT       LL_LPTIM_StartCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  OperatingMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
+  *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
+{
+  MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
+}
+
+/**
+  * @brief  Enable reset after read.
+  * @note After calling this function any read access to LPTIM_CNT
+  *        register will asynchronously reset the LPTIM_CNT register content.
+  * @rmtoll CR           RSTARE        LL_LPTIM_EnableResetAfterRead
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
+}
+
+/**
+  * @brief  Disable reset after read.
+  * @rmtoll CR           RSTARE        LL_LPTIM_DisableResetAfterRead
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
+}
+
+/**
+  * @brief  Indicate whether the reset after read feature is enabled.
+  * @rmtoll CR           RSTARE        LL_LPTIM_IsEnabledResetAfterRead
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Reset of the LPTIM_CNT counter register (synchronous).
+  * @note Due to the synchronous nature of this reset, it only takes
+  *       place after a synchronization delay of 3 LPTIM core clock cycles
+  *      (LPTIM core clock may be different from APB clock).
+  * @note COUNTRST is automatically cleared by hardware
+  * @rmtoll CR           COUNTRST       LL_LPTIM_ResetCounter\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
+}
+
+/**
+  * @brief  Set the LPTIM registers update mode (enable/disable register preload)
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  UpdateMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
+}
+
+/**
+  * @brief  Get the LPTIM registers update mode
+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
+}
+
+/**
+  * @brief  Set the auto reload value
+  * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
+  * @note After a write to the LPTIMx_ARR register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before  the ARROK flag is set, will
+  *       lead to unpredictable results.
+  * @note autoreload value be strictly greater than the compare value.
+  * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
+{
+  MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
+}
+
+/**
+  * @brief  Get actual auto reload value
+  * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
+}
+
+/**
+  * @brief  Set the repetition value
+  * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
+  * @rmtoll RCR          REP           LL_LPTIM_SetRepetition
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Repetition Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
+{
+  MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
+}
+
+/**
+  * @brief  Get the repetition value
+  * @rmtoll RCR          REP           LL_LPTIM_GetRepetition
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
+}
+
+/**
+  * @brief  Enable capture/compare channel.
+  * @rmtoll CCMR1         CC1E          LL_LPTIM_CC_EnableChannel\n
+  *         CCMR1         CC2E          LL_LPTIM_CC_EnableChannel
+  * @param  LPTIMx LPTimer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
+}
+
+/**
+  * @brief  Disable capture/compare channel.
+  * @rmtoll CCMR1         CC1E          LL_LPTIM_CC_DisableChannel\n
+  *         CCMR1         CC2E          LL_LPTIM_CC_DisableChannel
+  * @param  LPTIMx LPTimer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
+}
+
+/**
+  * @brief  Indicate whether channel is enabled.
+  * @rmtoll CCMR1         CC1E          LL_LPTIM_CC_IsEnabledChannel\n
+  *         CCMR1         CC2E          LL_LPTIM_CC_IsEnabledChannel
+  * @param  LPTIMx LPTimer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) ==                                       \
+           (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
+
+}
+
+/**
+  * @brief  Set the compare value
+  * @note After a write to the LPTIMx_CCR1 register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before the CMP1OK flag is set, will
+  *       lead to unpredictable results.
+  * @rmtoll CCR1          CCR1           LL_LPTIM_OC_SetCompareCH1
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value
+  * @rmtoll CCR1          CCR1           LL_LPTIM_OC_GetCompareCH1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
+}
+
+/**
+  * @brief  Set the compare value
+  * @note After a write to the LPTIMx_CCR2 register a new write operation to the
+  *       same register can only be performed when the previous write operation
+  *       is completed. Any successive write before the CMP2OK flag is set, will
+  *       lead to unpredictable results.
+  * @rmtoll CCR2          CCR2           LL_LPTIM_OC_SetCompareCH2
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value
+  * @rmtoll CCR2          CCR2           LL_LPTIM_OC_GetCompareCH2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
+}
+
+/**
+  * @brief  Get actual counter value
+  * @note When the LPTIM instance is running with an asynchronous clock, reading
+  *       the LPTIMx_CNT register may return unreliable values. So in this case
+  *       it is necessary to perform two consecutive read accesses and verify
+  *       that the two returned values are identical.
+  * @rmtoll CNT          CNT           LL_LPTIM_GetCounter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Counter value
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
+}
+
+/**
+  * @brief  Set the counter mode (selection of the LPTIM counter clock source).
+  * @note The counter mode can be set only when the LPTIM instance is disabled.
+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
+}
+
+/**
+  * @brief  Get the counter mode
+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
+}
+
+/**
+  * @brief  Set  waveform shape
+  * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Waveform This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
+}
+
+/**
+  * @brief  Get actual waveform shape
+  * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCMR1         CC1P          LL_LPTIM_OC_SetPolarity\n
+  * @rmtoll CCMR1         CC2P          LL_LPTIM_OC_SetPolarity\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
+{
+  if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5))
+  {
+    MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
+  }
+  else
+  {
+    MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
+               (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
+  }
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCMR1         CC1P          LL_LPTIM_OC_GetPolarity\n
+  * @rmtoll CCMR1         CC2P          LL_LPTIM_OC_GetPolarity\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  if ((LPTIMx == LPTIM4) || (LPTIMx == LPTIM5))
+  {
+    return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
+  }
+  else
+  {
+    return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >>                 \
+                      LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
+  }
+}
+
+/**
+  * @brief  Set actual prescaler division ratio.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When the LPTIM is configured to be clocked by an internal clock source
+  *       and the LPTIM counter is configured to be updated by active edges
+  *       detected on the LPTIM external Input1, the internal clock provided to
+  *       the LPTIM must be not be prescaled.
+  * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
+}
+
+/**
+  * @brief  Get actual prescaler division ratio.
+  * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64
+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
+}
+
+/**
+  * @brief  Set LPTIM input 1 source (default GPIO).
+  * @rmtoll CFGR2      IN1SEL       LL_LPTIM_SetInput1Src
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Src This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+  MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
+}
+
+/**
+  * @brief  Set LPTIM input 2 source (default GPIO).
+  * @rmtoll CFGR2      IN2SEL       LL_LPTIM_SetInput2Src
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Src This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+  MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
+}
+
+/**
+  * @brief  Set LPTIM input source (default GPIO).
+  * @rmtoll CFGR2      IC1SEL        LL_LPTIM_SetRemap
+  * @rmtoll CFGR2      IC2SEL        LL_LPTIM_SetRemap
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Src This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
+  *         @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
+  *         @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
+  *         @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
+  *         @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
+  *         @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_I3C1_IBIACK
+  *         @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
+  *         @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024
+  *         @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSI_128
+  *         @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_I3C2_IBIACK
+  *         @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO
+  *         @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_I3C1_IBIACK
+  *         @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_GPIO
+  *         @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_I3C2_IBIACK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+  MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
+}
+
+/**
+  * @brief  Set the polarity of IC channel 1.
+  * @rmtoll CCMR1         CC1P          LL_LPTIM_IC_SetPolarity\n
+  * @rmtoll CCMR1         CC2P          LL_LPTIM_IC_SetPolarity\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_ICPOLARITY_RISING
+  *         @arg @ref LL_LPTIM_ICPOLARITY_FALLING
+  *         @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
+             Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
+}
+
+/**
+  * @brief  Get the polarity of IC channels.
+  * @rmtoll CCMR1         CC1P          LL_LPTIM_IC_GetPolarity\n
+  * @rmtoll CCMR1         CC2P          LL_LPTIM_IC_GetPolarity\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_ICPOLARITY_RISING
+  *         @arg @ref LL_LPTIM_ICPOLARITY_FALLING
+  *         @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >>                 \
+                    LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
+
+}
+
+/**
+  * @brief  Set the filter of IC channels.
+  * @rmtoll CCMR1         IC1F          LL_LPTIM_IC_SetFilter\n
+  * @rmtoll CCMR1         IC2F          LL_LPTIM_IC_SetFilter\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
+{
+  MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
+             Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
+}
+
+/**
+  * @brief  Get the filter of IC channels.
+  * @rmtoll CCMR1         IC1F          LL_LPTIM_IC_GetFilter\n
+  * @rmtoll CCMR1         IC2F          LL_LPTIM_IC_GetFilter\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
+  *         @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >>                 \
+                    LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
+}
+
+/**
+  * @brief  Set the prescaler of IC channels.
+  * @rmtoll CCMR1         IC1PSC        LL_LPTIM_IC_SetPrescaler\n
+  * @rmtoll CCMR1         IC2PSC        LL_LPTIM_IC_SetPrescaler\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_ICPSC_DIV1
+  *         @arg @ref LL_LPTIM_ICPSC_DIV2
+  *         @arg @ref LL_LPTIM_ICPSC_DIV4
+  *         @arg @ref LL_LPTIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
+{
+  MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
+             Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
+}
+
+/**
+  * @brief  Get the prescaler of IC channels.
+  * @rmtoll CCMR1         IC1PSC        LL_LPTIM_IC_GetPrescaler\n
+  * @rmtoll CCMR1         IC2PSC        LL_LPTIM_IC_GetPrescaler\n
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_ICPSC_DIV1
+  *         @arg @ref LL_LPTIM_ICPSC_DIV2
+  *         @arg @ref LL_LPTIM_ICPSC_DIV4
+  *         @arg @ref LL_LPTIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >>             \
+                    LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
+}
+
+/**
+  * @brief  Set the Channel  Mode.
+  * @rmtoll CCMR1         CC1SEL          LL_LPTIM_CC_SetChannelMode\n
+  *         CCMR1         CC2SEL          LL_LPTIM_CC_SetChannelMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @param  CCMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
+  *         @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
+  * @retval None
+  */
+__STATIC_INLINE void  LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
+{
+  SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
+}
+
+/**
+  * @brief  Get the Channel  Mode.
+  * @rmtoll CCMR1         CC1SEL          LL_LPTIM_CC_GetChannelMode\n
+  *         CCMR1         CC2SEL          LL_LPTIM_CC_GetChannelMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CHANNEL_CH1
+  *         @arg @ref LL_LPTIM_CHANNEL_CH2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
+  *         @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
+  */
+__STATIC_INLINE uint32_t  LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
+{
+  return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >>             \
+                    LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @rmtoll CCR1         CCR1          LL_LPTIM_IC_GetCaptureCH1
+  * @note   The real capture value corresponding to the input capture trigger can be calculated using
+  *         the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
+  *         where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @rmtoll CCR2         CCR2          LL_LPTIM_IC_GetCaptureCH2
+  * @note   The real capture value corresponding to the input capture trigger can be calculated using
+  *         the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
+  *         where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note The first trigger event will start the timer, any successive trigger
+  *       event will reset the counter and the timer will restart.
+  * @note The timeout value corresponds to the compare value; if no trigger
+  *       occurs within the expected time frame, the MCU is waked-up by the
+  *       compare match event.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+  * @brief  Disable the timeout function
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note A trigger event arriving when the timer is already started will be
+  *       ignored.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
+}
+
+/**
+  * @brief  Indicate whether the timeout function is enabled.
+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Start the LPTIM counter
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
+}
+
+/**
+  * @brief  Configure the external trigger used as a trigger event for the LPTIM.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for the trigger.
+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n
+  *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n
+  *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2_CH1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3_CH1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4_OUT
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5_OUT
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
+}
+
+/**
+  * @brief  Get actual external trigger source.
+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2_CH1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3_CH1
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4_OUT
+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5_OUT
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
+}
+
+/**
+  * @brief  Get actual external trigger filter.
+  * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4
+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
+}
+
+/**
+  * @brief  Get actual external trigger polarity.
+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set the source of the clock used by the LPTIM instance.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
+}
+
+/**
+  * @brief  Get actual LPTIM instance clock source.
+  * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
+}
+
+/**
+  * @brief  Configure the active edge or edges used by the counter when
+            the LPTIM is clocked by an external clock source.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note When both external clock signal edges are considered active ones,
+  *       the LPTIM must also be clocked by an internal clock source with a
+  *       frequency equal to at least four times the external clock frequency.
+  * @note An internal clock source must be present when a digital filter is
+  *       required for external clock.
+  * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n
+  *         CFGR         CKPOL         LL_LPTIM_ConfigClock
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  ClockFilter This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LL_LPTIM_CLK_FILTER_2
+  *         @arg @ref LL_LPTIM_CLK_FILTER_4
+  *         @arg @ref LL_LPTIM_CLK_FILTER_8
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
+}
+
+/**
+  * @brief  Get actual clock polarity
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+  * @brief  Get actual clock digital filter
+  * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE
+  *         @arg @ref LL_LPTIM_CLK_FILTER_2
+  *         @arg @ref LL_LPTIM_CLK_FILTER_4
+  *         @arg @ref LL_LPTIM_CLK_FILTER_8
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
+  * @{
+  */
+
+/**
+  * @brief  Configure the encoder mode.
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
+}
+
+/**
+  * @brief  Get actual encoder mode.
+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
+{
+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
+}
+
+/**
+  * @brief  Enable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @note In this mode the LPTIM instance must be clocked by an internal clock
+  *       source. Also, the prescaler division ratio must be equal to 1.
+  * @note LPTIM instance must be configured in continuous mode prior enabling
+  *       the encoder mode.
+  * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+  * @brief  Disable the encoder mode
+  * @note This function must be called when the LPTIM instance is disabled.
+  * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
+}
+
+/**
+  * @brief  Indicates whether the LPTIM operates in encoder mode.
+  * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear the compare match flag for channel 1 (CC1CF)
+  * @rmtoll ICR          CC1CF        LL_LPTIM_ClearFlag_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
+}
+
+/**
+  * @brief  Inform application whether a capture/compare interrupt has occurred for channel 1.
+  * @rmtoll ISR          CC1IF         LL_LPTIM_IsActiveFlag_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the compare match flag for channel 2 (CC2CF)
+  * @rmtoll ICR          CC2CF        LL_LPTIM_ClearFlag_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
+}
+
+/**
+  * @brief  Inform application whether a capture/compare interrupt has occurred for channel 2.
+  * @rmtoll ISR          CC2IF          LL_LPTIM_IsActiveFlag_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
+  * @rmtoll ICR          CC1OCF       LL_LPTIM_ClearFlag_CC1O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
+}
+
+/**
+  * @brief  Inform application whether a Capture/Compare 1 over-capture  has occurred for channel 1.
+  * @rmtoll ISR          CC1OF          LL_LPTIM_IsActiveFlag_CC1O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
+  * @rmtoll ICR          CC2OCF       LL_LPTIM_ClearFlag_CC2O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
+}
+
+/**
+  * @brief  Inform application whether a Capture/Compare 2 over-capture  has occurred for channel 2.
+  * @rmtoll ISR          CC2OF          LL_LPTIM_IsActiveFlag_CC2O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
+}
+/**
+  * @brief  Clear the autoreload match flag (ARRMCF)
+  * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFlag_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
+}
+
+/**
+  * @brief  Inform application whether a autoreload match interrupt has occurred.
+  * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).
+  * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
+}
+
+/**
+  * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.
+  * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the compare register update interrupt flag (CMP1OKCF).
+  * @rmtoll ICR          CMP1OKCF       LL_LPTIM_ClearFlag_CMP1OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
+            completed. If so, a new one can be initiated.
+  * @rmtoll ISR          CMP1OK         LL_LPTIM_IsActiveFlag_CMP1OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the compare register update interrupt flag (CMP2OKCF).
+  * @rmtoll ICR          CMP2OKCF       LL_LPTIM_ClearFlag_CMP2OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
+            completed. If so, a new one can be initiated.
+  * @rmtoll ISR          CMP2OK         LL_LPTIM_IsActiveFlag_CMP2OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the interrupt register update interrupt flag (DIEROKCF).
+  * @rmtoll ICR       DIEROKCF          LL_LPTIM_ClearFlag_DIEROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
+            completed. If so, a new one can be initiated.
+  * @rmtoll ISR          DIEROK            LL_LPTIM_IsActiveFlag_DIEROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the autoreload register update interrupt flag (ARROKCF).
+  * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
+            completed. If so, a new one can be initiated.
+  * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the counter direction change to up interrupt flag (UPCF).
+  * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
+            operates in encoder mode).
+  * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).
+  * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
+}
+
+/**
+  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
+            operates in encoder mode).
+  * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Clear the repetition register update interrupt flag (REPOKCF).
+  * @rmtoll ICR          REPOKCF       LL_LPTIM_ClearFlag_REPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
+}
+
+/**
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
+            completed; If so, a new one can be initiated.
+  * @rmtoll ISR          REPOK         LL_LPTIM_IsActiveFlag_REPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the update event flag (UECF).
+  * @rmtoll ICR          UECF          LL_LPTIM_ClearFlag_UE
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
+}
+
+/**
+  * @brief  Informs application whether the LPTIMx update event has occurred.
+  * @rmtoll ISR          UE            LL_LPTIM_IsActiveFlag_UE
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE        LL_LPTIM_EnableIT_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER          CC1IE        LL_LPTIM_DisableIT_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER          CC1IE        LL_LPTIM_IsEnabledIT_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE        LL_LPTIM_EnableIT_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER          CC2IE        LL_LPTIM_DisableIT_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER          CC2IE        LL_LPTIM_IsEnabledIT_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable capture/compare 1 over-capture interrupt (CC1OIE).
+  * @rmtoll DIER         CC1OIE        LL_LPTIM_EnableIT_CC1O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
+}
+
+/**
+  * @brief  Disable capture/compare 1 over-capture interrupt (CC1OIE).
+  * @rmtoll DIER          CC1OIE        LL_LPTIM_DisableIT_CC1O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
+  * @rmtoll DIER          CC1OIE        LL_LPTIM_IsEnabledIT_CC1O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable capture/compare 1 over-capture interrupt (CC2OIE).
+  * @rmtoll DIER         CC2OIE        LL_LPTIM_EnableIT_CC2O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
+}
+
+/**
+  * @brief  Disable capture/compare 1 over-capture interrupt (CC2OIE).
+  * @rmtoll DIER          CC2OIE        LL_LPTIM_DisableIT_CC2O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
+  * @rmtoll DIER          CC2OIE        LL_LPTIM_IsEnabledIT_CC2O
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable autoreload match interrupt (ARRMIE).
+  * @rmtoll DIER          ARRMIE        LL_LPTIM_EnableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
+}
+
+/**
+  * @brief  Disable autoreload match interrupt (ARRMIE).
+  * @rmtoll DIER          ARRMIE        LL_LPTIM_DisableIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
+  * @rmtoll DIER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll DIER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
+}
+
+/**
+  * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).
+  * @rmtoll DIER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
+}
+
+/**
+  * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
+  * @rmtoll DIER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable compare register write completed interrupt (CMP1OKIE).
+  * @rmtoll IER          CMP1OKIE       LL_LPTIM_EnableIT_CMP1OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
+}
+
+/**
+  * @brief  Disable compare register write completed interrupt (CMP1OKIE).
+  * @rmtoll IER          CMPO1KIE       LL_LPTIM_DisableIT_CMP1OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
+}
+
+/**
+  * @brief  Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
+  * @rmtoll IER          CMP1OKIE       LL_LPTIM_IsEnabledIT_CMP1OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable compare register write completed interrupt (CMP2OKIE).
+  * @rmtoll IER          CMP2OKIE       LL_LPTIM_EnableIT_CMP2OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
+}
+
+/**
+  * @brief  Disable compare register write completed interrupt (CMP2OKIE).
+  * @rmtoll IER          CMP2OKIE       LL_LPTIM_DisableIT_CMP2OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
+}
+
+/**
+  * @brief  Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
+  * @rmtoll IER          CMP2OKIE       LL_LPTIM_IsEnabledIT_CMP2OK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll DIER         ARROKIE       LL_LPTIM_EnableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
+}
+
+/**
+  * @brief  Disable autoreload register write completed interrupt (ARROKIE).
+  * @rmtoll DIER         ARROKIE       LL_LPTIM_DisableIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
+}
+
+/**
+  * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
+  * @rmtoll DIER         ARROKIE       LL_LPTIM_IsEnabledIT_ARROK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit(1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable direction change to up interrupt (UPIE).
+  * @rmtoll DIER         UPIE          LL_LPTIM_EnableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
+}
+
+/**
+  * @brief  Disable direction change to up interrupt (UPIE).
+  * @rmtoll DIER         UPIE          LL_LPTIM_DisableIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.
+  * @rmtoll DIER         UPIE          LL_LPTIM_IsEnabledIT_UP
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit(1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
+{
+  return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
+}
+
+/**
+  * @brief  Enable direction change to down interrupt (DOWNIE).
+  * @rmtoll DIER         DOWNIE        LL_LPTIM_EnableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
+}
+
+/**
+  * @brief  Disable direction change to down interrupt (DOWNIE).
+  * @rmtoll DIER         DOWNIE        LL_LPTIM_DisableIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
+  * @rmtoll DIER         DOWNIE        LL_LPTIM_IsEnabledIT_DOWN
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit(1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable repetition register update successfully completed interrupt (REPOKIE).
+  * @rmtoll DIER         REPOKIE       LL_LPTIM_EnableIT_REPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
+}
+
+/**
+  * @brief  Disable repetition register update successfully completed interrupt (REPOKIE).
+  * @rmtoll DIER         REPOKIE       LL_LPTIM_DisableIT_REPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
+}
+
+/**
+  * @brief  Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
+  * @rmtoll DIER         REPOKIE       LL_LPTIM_IsEnabledIT_REPOK
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit(1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event interrupt (UEIE).
+  * @rmtoll DIER         UEIE          LL_LPTIM_EnableIT_UE
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
+}
+
+/**
+  * @brief  Disable update event interrupt (UEIE).
+  * @rmtoll DIER          UEIE         LL_LPTIM_DisableIT_UE
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
+}
+
+/**
+  * @brief  Indicates whether the update event interrupt (UEIE) is enabled.
+  * @rmtoll DIER         UEIE          LL_LPTIM_IsEnabledIT_UE
+  * @param  LPTIMx Low-Power Timer instance
+  *@ retval State of bit(1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request.
+  * @rmtoll DIER         UEDE          LL_LPTIM_EnableDMAReq_UPDATE
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
+}
+
+/**
+  * @brief  Disable update DMA request.
+  * @rmtoll DIER         UEDE          LL_LPTIM_DisableDMAReq_UPDATE
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request is enabled.
+  * @rmtoll DIER         UEDE          LL_LPTIM_IsEnabledDMAReq_UPDATE
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_LPTIM_EnableDMAReq_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_LPTIM_DisableDMAReq_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_LPTIM_IsEnabledDMAReq_CC1
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_LPTIM_EnableDMAReq_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
+{
+  SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_LPTIM_DisableDMAReq_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
+{
+  CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_LPTIM_IsEnabledDMAReq_CC2
+  * @param  LPTIMx Low-Power Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
+{
+  return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_LPTIM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_lpuart.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_lpuart.h
new file mode 100644
index 000000000..86469ba8f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_lpuart.h
@@ -0,0 +1,2658 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_lpuart.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPUART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_LPUART_H
+#define STM32N6xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
+  * @{
+  */
+/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
+static const uint16_t LPUART_PRESCALER_TAB[] =
+{
+  (uint16_t)1,
+  (uint16_t)2,
+  (uint16_t)4,
+  (uint16_t)6,
+  (uint16_t)8,
+  (uint16_t)10,
+  (uint16_t)12,
+  (uint16_t)16,
+  (uint16_t)32,
+  (uint16_t)64,
+  (uint16_t)128,
+  (uint16_t)256
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+  * @{
+  */
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL     256U
+#define LPUART_BRR_MASK               0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE          0x00000300U
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL LPUART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
+  * @{
+  */
+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
+  * @{
+  */
+#define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
+#define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
+#define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
+#define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
+#define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
+  * @{
+  */
+#define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+                                                                   interrupt enable */
+#define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
+                                                                   not full interrupt enable */
+#define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
+#define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+  * @{
+  */
+#define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
+#define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
+#define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
+#define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
+#define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
+#define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
+#define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
+                                                               in positive/direct logic. (1=H, 0=L)                  */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+                                                               in negative/inverse logic. (1=L, 0=H).
+                                                               The parity bit is also inverted.                      */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
+                                                            following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+                                                            following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
+                                                                           when there is space in the receive buffer  */
+#define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
+                                                                           when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud Rate value to achieve
+  * @retval LPUARTDIV value to be used for BRR register filling
+  */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
+  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
+      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  LPUART Enable
+  * @rmtoll CR1          UE            LL_LPUART_Enable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  LPUART Disable
+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
+  *         flags, in the LPUARTx_ISR are set to their default values.
+  * @note   In order to go into low-power mode without generating errors on the line,
+  *         the TE bit must be reset before and the software must wait
+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+  *         The DMA requests are also reset when UE = 0 so the DMA channel must
+  *         be disabled before resetting the UE bit.
+  * @rmtoll CR1          UE            LL_LPUART_Disable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled
+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  LPUART enabled in STOP Mode
+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+  *         LPUART clock selection is HSI or LSE in RCC.
+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  LPUART disabled in STOP Mode
+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled in STOP Mode
+  *         (able to wake up MCU from Stop mode or not)
+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
+  *         CR1          TE            LL_LPUART_SetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
+  *         CR1          TE            LL_LPUART_GetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
+  *         CR1          PCE           LL_LPUART_SetParity
+  * @param  LPUARTx LPUART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
+  *         CR1          PCE           LL_LPUART_GetParity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
+  *         CR1          M             LL_LPUART_ConfigCharacter\n
+  *         CR2          STOP          LL_LPUART_ConfigCharacter
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+                                               uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  *
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Set Address of the LPUART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
+  *
+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock and expected Baud Rate values
+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
+  *         (Baud rate value != 0).
+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+  *         a care should be taken when generating high baud rates using high PeriphClk
+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                           uint32_t BaudRate)
+{
+  if (BaudRate != 0U)
+  {
+    LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
+                                               uint32_t PrescalerValue)
+{
+  uint32_t lpuartdiv;
+  uint32_t brrresult;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+
+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+  {
+    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+  }
+  else
+  {
+    brrresult = 0x0UL;
+  }
+
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : c
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the LPUART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
+  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS interrupt Flag is set or not
+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Flag is set or not
+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
+  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Flag is set or not
+  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
+  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
+  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the LPUART data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
+  * @param  LPUARTx LPUART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
+{
+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
+{
+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+  LPUARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+  LPUARTx->TDR = Value & 0x1FFUL;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put LPUART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data FIFO flush
+  * @note   TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
+  *         also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_LPUART_RequestTxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_LPUART_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_pka.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_pka.h
new file mode 100644
index 000000000..19d6c893f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_pka.h
@@ -0,0 +1,601 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_pka.h
+  * @author  MCD Application Team
+  * @brief   Header file of PKA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_PKA_H
+#define STM32N6xx_LL_PKA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(PKA)
+
+/** @defgroup PKA_LL PKA
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PKA_LL_ES_INIT PKA Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  PKA Init structures definition
+  */
+typedef struct
+{
+  uint32_t Mode;          /*!< Specifies the PKA operation mode.
+                               This parameter can be a value of @ref PKA_LL_EC_MODE.
+
+                               This feature can be modified afterwards using unitary function @ref LL_PKA_SetMode(). */
+} LL_PKA_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PKA_LL_Exported_Constants PKA Exported Constants
+  * @{
+  */
+
+/** @defgroup PKA_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PKA_ReadReg function
+  * @{
+  */
+#define LL_PKA_SR_ADDRERRF                 PKA_SR_ADDRERRF
+#define LL_PKA_SR_RAMERRF                  PKA_SR_RAMERRF
+#define LL_PKA_SR_PROCENDF                 PKA_SR_PROCENDF
+#define LL_PKA_SR_BUSY                     PKA_SR_BUSY
+#define LL_PKA_SR_INITOK                   PKA_SR_INITOK
+#define LL_PKA_SR_OPERRF                   PKA_SR_OPERRF
+/**
+  * @}
+  */
+
+/** @defgroup PKA_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_PKA_ReadReg and  LL_PKA_WriteReg functions
+  * @{
+  */
+#define LL_PKA_CR_ADDRERRIE                PKA_CR_ADDRERRIE
+#define LL_PKA_CR_RAMERRIE                 PKA_CR_RAMERRIE
+#define LL_PKA_CR_PROCENDIE                PKA_CR_PROCENDIE
+#define LL_PKA_CLRFR_PROCENDFC             PKA_CLRFR_PROCENDFC
+#define LL_PKA_CLRFR_RAMERRFC              PKA_CLRFR_RAMERRFC
+#define LL_PKA_CLRFR_ADDRERRFC             PKA_CLRFR_ADDRERRFC
+#define LL_PKA_CR_OPERRIE                  PKA_CR_OPERRIE
+#define LL_PKA_CLRFR_OPERRFC               PKA_CLRFR_OPERRFC
+/**
+  * @}
+  */
+
+/** @defgroup PKA_LL_EC_MODE Operation Mode
+  * @brief    List of operation mode.
+  * @{
+  */
+#define LL_PKA_MODE_MODULAR_EXP              ((uint32_t)0x00000000U)   /*!< modular exponentiation */
+#define LL_PKA_MODE_MONTGOMERY_PARAM         ((uint32_t)0x00000001U)   /*!< Compute Montgomery parameter only */
+#define LL_PKA_MODE_MODULAR_EXP_FAST         ((uint32_t)0x00000002U)   /*!< modular exponentiation fast mode */
+#define LL_PKA_MODE_MODULAR_EXP_PROTECT      ((uint32_t)0x00000003U)   /*!< modular exponentiation protect mode */
+#define LL_PKA_MODE_ECC_MUL                  ((uint32_t)0x00000020U)   /*!< compute ECC kP operation */
+#define LL_PKA_MODE_ECC_COMPLETE_ADD         ((uint32_t)0x00000023U)   /*!< ECC complete addition */
+#define LL_PKA_MODE_ECDSA_SIGNATURE          ((uint32_t)0x00000024U)   /*!< ECDSA signature */
+#define LL_PKA_MODE_ECDSA_VERIFICATION       ((uint32_t)0x00000026U)   /*!< ECDSA verification */
+#define LL_PKA_MODE_POINT_CHECK              ((uint32_t)0x00000028U)   /*!< Point check */
+#define LL_PKA_MODE_RSA_CRT_EXP              ((uint32_t)0x00000007U)   /*!< RSA CRT exponentiation */
+#define LL_PKA_MODE_MODULAR_INV              ((uint32_t)0x00000008U)   /*!< Modular inversion */
+#define LL_PKA_MODE_ARITHMETIC_ADD           ((uint32_t)0x00000009U)   /*!< Arithmetic addition */
+#define LL_PKA_MODE_ARITHMETIC_SUB           ((uint32_t)0x0000000AU)   /*!< Arithmetic subtraction */
+#define LL_PKA_MODE_ARITHMETIC_MUL           ((uint32_t)0x0000000BU)   /*!< Arithmetic multiplication */
+#define LL_PKA_MODE_COMPARISON               ((uint32_t)0x0000000CU)   /*!< Comparison */
+#define LL_PKA_MODE_MODULAR_REDUC            ((uint32_t)0x0000000DU)   /*!< Modular reduction */
+#define LL_PKA_MODE_MODULAR_ADD              ((uint32_t)0x0000000EU)   /*!< Modular addition */
+#define LL_PKA_MODE_MODULAR_SUB              ((uint32_t)0x0000000FU)   /*!< Modular subtraction */
+#define LL_PKA_MODE_MONTGOMERY_MUL           ((uint32_t)0x00000010U)   /*!< Montgomery multiplication */
+#define LL_PKA_MODE_DOUBLE_BASE_LADDER       ((uint32_t)0x00000027U)   /*!< Double base ladder */
+#define LL_PKA_MODE_ECC_PROJECTIVE_AFF       ((uint32_t)0x0000002FU)   /*!< ECC projective to affine */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PKA_LL_Exported_Macros PKA Exported Macros
+  * @{
+  */
+
+/** @defgroup PKA_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PKA register
+  * @param  __INSTANCE__ PKA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PKA register
+  * @param  __INSTANCE__ PKA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PKA_LL_Exported_Functions PKA Exported Functions
+  * @{
+  */
+
+/** @defgroup PKA_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure PKA peripheral.
+  * @brief  Set PKA operating mode.
+  * @rmtoll CR           MODE          LL_PKA_Config
+  * @param  PKAx PKA Instance.
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP
+  *         @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
+  *         @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
+  *         @arg @ref LL_PKA_MODE_POINT_CHECK
+  *         @arg @ref LL_PKA_MODE_RSA_CRT_EXP
+  *         @arg @ref LL_PKA_MODE_MODULAR_INV
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
+  *         @arg @ref LL_PKA_MODE_COMPARISON
+  *         @arg @ref LL_PKA_MODE_MODULAR_REDUC
+  *         @arg @ref LL_PKA_MODE_MODULAR_ADD
+  *         @arg @ref LL_PKA_MODE_MODULAR_SUB
+  *         @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
+  *         @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
+  *         @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
+  *         @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
+  *         @arg @ref LL_PKA_MODE_ECC_MUL
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
+  */
+__STATIC_INLINE void LL_PKA_Config(PKA_TypeDef *PKAx, uint32_t Mode)
+{
+  MODIFY_REG(PKAx->CR, (PKA_CR_MODE), (Mode << PKA_CR_MODE_Pos));
+}
+
+/**
+  * @brief  Enable PKA peripheral.
+  * @rmtoll CR           EN            LL_PKA_Enable
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_Enable(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CR, PKA_CR_EN);
+}
+
+/**
+  * @brief  Disable PKA peripheral.
+  * @rmtoll CR           EN            LL_PKA_Disable
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx)
+{
+  CLEAR_BIT(PKAx->CR, PKA_CR_EN);
+}
+
+/**
+  * @brief  Check if the PKA peripheral is enabled or disabled.
+  * @rmtoll CR           EN            LL_PKA_IsEnabled
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PKA operating mode.
+  * @rmtoll CR           MODE          LL_PKA_SetMode
+  * @param  PKAx PKA Instance.
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP
+  *         @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
+  *         @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
+  *         @arg @ref LL_PKA_MODE_POINT_CHECK
+  *         @arg @ref LL_PKA_MODE_RSA_CRT_EXP
+  *         @arg @ref LL_PKA_MODE_MODULAR_INV
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
+  *         @arg @ref LL_PKA_MODE_COMPARISON
+  *         @arg @ref LL_PKA_MODE_MODULAR_REDUC
+  *         @arg @ref LL_PKA_MODE_MODULAR_ADD
+  *         @arg @ref LL_PKA_MODE_MODULAR_SUB
+  *         @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
+  *         @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
+  *         @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
+  *         @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
+  *         @arg @ref LL_PKA_MODE_ECC_MUL
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode)
+{
+  MODIFY_REG(PKAx->CR, PKA_CR_MODE, Mode << PKA_CR_MODE_Pos);
+}
+
+/**
+  * @brief  Get PKA operating mode.
+  * @rmtoll CR           MODE          LL_PKA_GetMode
+  * @param  PKAx PKA Instance.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP
+  *         @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
+  *         @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
+  *         @arg @ref LL_PKA_MODE_POINT_CHECK
+  *         @arg @ref LL_PKA_MODE_RSA_CRT_EXP
+  *         @arg @ref LL_PKA_MODE_MODULAR_INV
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
+  *         @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
+  *         @arg @ref LL_PKA_MODE_COMPARISON
+  *         @arg @ref LL_PKA_MODE_MODULAR_REDUC
+  *         @arg @ref LL_PKA_MODE_MODULAR_ADD
+  *         @arg @ref LL_PKA_MODE_MODULAR_SUB
+  *         @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
+  *         @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
+  *         @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
+  *         @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
+  *         @arg @ref LL_PKA_MODE_ECC_MUL
+  *         @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
+  */
+__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *PKAx)
+{
+  return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
+}
+
+/**
+  * @brief  Start the operation selected using LL_PKA_SetMode.
+  * @rmtoll CR           START         LL_PKA_Start
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_Start(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CR, PKA_CR_START);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PKA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable address error interrupt.
+  * @rmtoll CR           ADDRERRIE     LL_PKA_EnableIT_ADDRERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_EnableIT_ADDRERR(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
+}
+
+/**
+  * @brief  Enable RAM error interrupt.
+  * @rmtoll CR           RAMERRIE      LL_PKA_EnableIT_RAMERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_EnableIT_RAMERR(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CR, PKA_CR_RAMERRIE);
+}
+
+/**
+  * @brief  Enable OPERATION error interrupt.
+  * @rmtoll CR           OPERRIE      LL_PKA_EnableIT_OPERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_EnableIT_OPERR(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CR, PKA_CR_OPERRIE);
+}
+
+/**
+  * @brief  Enable end of operation interrupt.
+  * @rmtoll CR           PROCENDIE     LL_PKA_EnableIT_PROCEND
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_EnableIT_PROCEND(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CR, PKA_CR_PROCENDIE);
+}
+
+/**
+  * @brief  Disable address error interrupt.
+  * @rmtoll CR           ADDRERRIE     LL_PKA_DisableIT_ADDERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_DisableIT_ADDERR(PKA_TypeDef *PKAx)
+{
+  CLEAR_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
+}
+
+/**
+  * @brief  Disable RAM error interrupt.
+  * @rmtoll CR           RAMERRIE      LL_PKA_DisableIT_RAMERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_DisableIT_RAMERR(PKA_TypeDef *PKAx)
+{
+  CLEAR_BIT(PKAx->CR, PKA_CR_RAMERRIE);
+}
+
+/**
+  * @brief  Disable End of operation interrupt.
+  * @rmtoll CR           PROCENDIE     LL_PKA_DisableIT_PROCEND
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx)
+{
+  CLEAR_BIT(PKAx->CR, PKA_CR_PROCENDIE);
+}
+
+/**
+  * @brief  Disable OPERATION error interrupt.
+  * @rmtoll CR           OPERRIE      LL_PKA_EnableIT_OPERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_DisableIT_OPERR(PKA_TypeDef *PKAx)
+{
+  CLEAR_BIT(PKAx->CR, PKA_CR_OPERRIE);
+}
+
+/**
+  * @brief  Check if address error interrupt is enabled.
+  * @rmtoll CR           ADDRERRIE     LL_PKA_IsEnabledIT_ADDRERR
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RAM error interrupt is enabled.
+  * @rmtoll CR           RAMERRIE      LL_PKA_IsEnabledIT_RAMERR
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if OPERATION error interrupt is enabled.
+  * @rmtoll CR           OPERRIE      LL_PKA_IsEnabledIT_OPERR
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->CR, PKA_CR_OPERRIE) == (PKA_CR_OPERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if end of operation interrupt is enabled.
+  * @rmtoll CR           PROCENDIE     LL_PKA_IsEnabledIT_PROCEND
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PKA_LL_EF_FLAG_Management PKA flag management
+  * @{
+  */
+
+/**
+  * @brief  Get PKA address error flag.
+  * @rmtoll SR           ADDRERRF      LL_PKA_IsActiveFlag_ADDRERR
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get PKA RAM error flag.
+  * @rmtoll SR           RAMERRF       LL_PKA_IsActiveFlag_RAMERR
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get PKA OPERATION error flag.
+  * @rmtoll SR           OPERRF       LL_PKA_IsActiveFlag_OPERR
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->SR, PKA_SR_OPERRF) == (PKA_SR_OPERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get PKA end of operation flag.
+  * @rmtoll SR           PROCENDF      LL_PKA_IsActiveFlag_PROCEND
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get PKA busy flag.
+  * @rmtoll SR           BUSY          LL_PKA_IsActiveFlag_BUSY
+  * @param  PKAx PKA Instance.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx)
+{
+  return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear PKA address error flag.
+  * @rmtoll CLRFR        ADDRERRFC     LL_PKA_ClearFlag_ADDERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_ClearFlag_ADDERR(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CLRFR, PKA_CLRFR_ADDRERRFC);
+}
+
+/**
+  * @brief  Clear PKA RAM error flag.
+  * @rmtoll CLRFR        RAMERRFC      LL_PKA_ClearFlag_RAMERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_ClearFlag_RAMERR(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CLRFR, PKA_CLRFR_RAMERRFC);
+}
+
+/**
+  * @brief  Clear PKA OPERATION error flag.
+  * @rmtoll CLRFR        OPERRFC      LL_PKA_ClearFlag_OPERR
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_ClearFlag_OPERR(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CLRFR, PKA_CLRFR_OPERRFC);
+}
+
+/**
+  * @brief  Clear PKA end of operation flag.
+  * @rmtoll CLRFR        PROCENDFC     LL_PKA_ClearFlag_PROCEND
+  * @param  PKAx PKA Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx)
+{
+  SET_BIT(PKAx->CLRFR, PKA_CLRFR_PROCENDFC);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup PKA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx);
+ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct);
+void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct);
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PKA) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_PKA_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_pwr.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_pwr.h
new file mode 100644
index 000000000..b599507fd
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_pwr.h
@@ -0,0 +1,1868 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_PWR_H
+#define STM32N6xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup PWR_LL_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+/* Wake-Up Pins PWR register offsets */
+#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    (2UL)
+#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       (0x1FU)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
+  * @{
+  */
+#define LL_PWR_SMPS_SUPPLY             PWR_CR1_SDEN                            /*!< Core domains are supplied from the SMPS                                     */
+#define LL_PWR_EXTERNAL_SOURCE_SUPPLY  (0U)                                    /*!< The SMPS is Bypassed. The Core domains are supplied from an external source */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
+  * @{
+  */
+#define LL_PWR_VCOREMON_LEVEL_SCALE1  (0U)                                     /*!< VDDCORE low-voltage threshold 1 selected (VOS 1) */
+#define LL_PWR_VCOREMON_LEVEL_SCALE0  PWR_CR3_VCORELLS                         /*!< VDDCORE low-voltage threshold 2 selected (VOS 0) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SCALE0     PWR_VOSCR_VOS                           /*!< Voltage scaling range 0 (highest frequency) */
+#define LL_PWR_REGU_VOLTAGE_SCALE1     (0U)                                    /*!< Voltage scaling range 1 (lowest power)      */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Power Down Mode In Deep Sleep Mode
+  * @{
+  */
+#define LL_PWR_POWERDOWN_MODE_DS_STOP     (0U)                                 /*!< Enter to Stop mode when the CPU enters deepsleep    */
+#define LL_PWR_POWERDOWN_MODE_DS_STANDBY  PWR_CPUCR_PDDS                       /*!< Enter to Standby mode when the CPU enters deepsleep */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
+  * @{
+  */
+#define LL_PWR_REGU_STOP_VOLTAGE_SCALE3     PWR_CPUCR_SVOS                     /*!< Voltage scaling range 3 (highest frequency) when system enters STOP mode */
+#define LL_PWR_REGU_STOP_VOLTAGE_SCALE5     (0U)                               /*!< Voltage scaling range 5 (lowest power) when system enters STOP mode      */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_VDDIO_VOLTAGE_RANGE VDD I/O voltage range selection
+  * @{
+  */
+#define LL_PWR_VDDIO_VOLTAGE_RANGE_1V8    (1U)                                 /*!< 1v8 voltage range */
+#define LL_PWR_VDDIO_VOLTAGE_RANGE_3V3    (0U)                                 /*!< 3v3 voltage range  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1             PWR_WKUPEPR_WKUPEN1                     /*!< Wake-Up pin 1 : PA0  */
+#define LL_PWR_WAKEUP_PIN2             PWR_WKUPEPR_WKUPEN2                     /*!< Wake-Up pin 2 : PA2  */
+#define LL_PWR_WAKEUP_PIN3             PWR_WKUPEPR_WKUPEN3                     /*!< Wake-Up pin 3 : PC13 */
+#define LL_PWR_WAKEUP_PIN4             PWR_WKUPEPR_WKUPEN4                     /*!< Wake-Up pin 4 : PD2  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN_NOPULL       (0UL)                                   /*!< Configure Wake-Up pin in no pull   */
+#define LL_PWR_WAKEUP_PIN_PULLUP       (1UL)                                   /*!< Configure Wake-Up pin in pull Up   */
+#define LL_PWR_WAKEUP_PIN_PULLDOWN     (2UL)                                   /*!< Configure Wake-Up pin in pull Down */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_ITEMS_PRIVILEGE_ATTRIBUTE PWR Items Privilege Attribute
+  * @{
+  */
+#define LL_PWR_PRIV0_NPRIV             (0U)                                    /*!< System supply configuration non privilege mode                       */
+#define LL_PWR_PRIV0_PRIV              PWR_PRIVCFGR_PRIV0                      /*!< System supply configuration privilege mode                           */
+#define LL_PWR_PRIV1_NPRIV             (0U)                                    /*!< Programmable voltage detector non privilege mode                     */
+#define LL_PWR_PRIV1_PRIV              PWR_PRIVCFGR_PRIV1                      /*!< Programmable voltage detect privilege mode                           */
+#define LL_PWR_PRIV2_NPRIV             (0U)                                    /*!< VDDCORE monitor non privilege mode                                   */
+#define LL_PWR_PRIV2_PRIV              PWR_PRIVCFGR_PRIV2                      /*!< VDDCORE monitor privilege mode                                       */
+#define LL_PWR_PRIV3_NPRIV             (0U)                                    /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control non privilege mode */
+#define LL_PWR_PRIV3_PRIV              PWR_PRIVCFGR_PRIV3                      /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control privilege mode     */
+#define LL_PWR_PRIV4_NPRIV             (0U)                                    /*!< Voltage scaling selection nprivilege mode                            */
+#define LL_PWR_PRIV4_PRIV              PWR_PRIVCFGR_PRIV4                      /*!< Voltage scaling selection privilege mode                             */
+#define LL_PWR_PRIV5_NPRIV             (0U)                                    /*!< Backup domain non privilege mode                                     */
+#define LL_PWR_PRIV5_PRIV              PWR_PRIVCFGR_PRIV5                      /*!< Backup domain privilege mode                                         */
+#define LL_PWR_PRIV6_NPRIV             (0U)                                    /*!< CPU power control non privilege mode                                 */
+#define LL_PWR_PRIV6_PRIV              PWR_PRIVCFGR_PRIV6                      /*!< CPU power control privilege mode                                     */
+#define LL_PWR_PRIV7_NPRIV             (0U)                                    /*!< Peripheral voltage monitor non privilege mode                        */
+#define LL_PWR_PRIV7_PRIV              PWR_PRIVCFGR_PRIV7                      /*!< Peripheral voltage monitor privilege mode                            */
+#define LL_PWR_WAKEUP_PIN1_NPRIV       (0U)                                    /*!< Wake up pin 1 non privilege mode                                     */
+#define LL_PWR_WAKEUP_PIN1_PRIV        PWR_PRIVCFGR_WKUPPRIV1                  /*!< Wake up pin 1 privilege mode                                         */
+#define LL_PWR_WAKEUP_PIN2_NPRIV       (0U)                                    /*!< Wake up pin 2 non privilege mode                                     */
+#define LL_PWR_WAKEUP_PIN2_PRIV        PWR_PRIVCFGR_WKUPPRIV2                  /*!< Wake up pin 2 privilege mode                                         */
+#define LL_PWR_WAKEUP_PIN3_NPRIV       (0U)                                    /*!< Wake up pin 3 non privilege mode                                     */
+#define LL_PWR_WAKEUP_PIN3_PRIV        PWR_PRIVCFGR_WKUPPRIV3                  /*!< Wake up pin 3 privilege mode                                         */
+#define LL_PWR_WAKEUP_PIN4_NPRIV       (0U)                                    /*!< Wake up pin 4 non privilege mode                                     */
+#define LL_PWR_WAKEUP_PIN4_PRIV        PWR_PRIVCFGR_WKUPPRIV4                  /*!< Wake up pin 4 privilege mode                                         */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
+  * @{
+  */
+#define LL_PWR_SEC0_NSEC               (0U)                                    /*!< System supply configuration non secure mode                       */
+#define LL_PWR_SEC0_SEC                PWR_SECCFGR_SEC0                        /*!< System supply configuration secure mode                           */
+#define LL_PWR_SEC1_NSEC               (0U)                                    /*!< Programmable voltage detector non secure mode                     */
+#define LL_PWR_SEC1_SEC                PWR_SECCFGR_SEC1                        /*!< Programmable voltage detect secure mode                           */
+#define LL_PWR_SEC2_NSEC               (0U)                                    /*!< VDDCORE monitor non secure mode                                   */
+#define LL_PWR_SEC2_SEC                PWR_SECCFGR_SEC2                        /*!< VDDCORE monitor secure mode                                       */
+#define LL_PWR_SEC3_NSEC               (0U)                                    /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control non secure mode */
+#define LL_PWR_SEC3_SEC                PWR_SECCFGR_SEC3                        /*!< I-TCM, D-TCM, and I-TCM FLEXMEM low power control secure mode     */
+#define LL_PWR_SEC4_NSEC               (0U)                                    /*!< Voltage scaling selection nsecure mode                            */
+#define LL_PWR_SEC4_SEC                PWR_SECCFGR_SEC4                        /*!< Voltage scaling selection secure mode                             */
+#define LL_PWR_SEC5_NSEC               (0U)                                    /*!< Backup domain non secure mode                                     */
+#define LL_PWR_SEC5_SEC                PWR_SECCFGR_SEC5                        /*!< Backup domain secure mode                                         */
+#define LL_PWR_SEC6_NSEC               (0U)                                    /*!< CPU power control non secure mode                                 */
+#define LL_PWR_SEC6_SEC                PWR_SECCFGR_SEC6                        /*!< CPU power control secure mode                                     */
+#define LL_PWR_SEC7_NSEC               (0U)                                    /*!< Peripheral voltage monitor non secure mode                        */
+#define LL_PWR_SEC7_SEC                PWR_SECCFGR_SEC7                        /*!< Peripheral voltage monitor secure mode                            */
+#define LL_PWR_WAKEUP_PIN1_NSEC        (0U)                                    /*!< Wake up pin 1 non secure mode                                     */
+#define LL_PWR_WAKEUP_PIN1_SEC         PWR_SECCFGR_WKUPSEC1                    /*!< Wake up pin 1 secure mode                                         */
+#define LL_PWR_WAKEUP_PIN2_NSEC        (0U)                                    /*!< Wake up pin 2 non secure mode                                     */
+#define LL_PWR_WAKEUP_PIN2_SEC         PWR_SECCFGR_WKUPSEC2                    /*!< Wake up pin 2 secure mode                                         */
+#define LL_PWR_WAKEUP_PIN3_NSEC        (0U)                                    /*!< Wake up pin 3 non secure mode                                     */
+#define LL_PWR_WAKEUP_PIN3_SEC         PWR_SECCFGR_WKUPSEC3                    /*!< Wake up pin 3 secure mode                                         */
+#define LL_PWR_WAKEUP_PIN4_NSEC        (0U)                                    /*!< Wake up pin 4 non secure mode                                     */
+#define LL_PWR_WAKEUP_PIN4_SEC         PWR_SECCFGR_WKUPSEC4                    /*!< Wake up pin 4 secure mode                                         */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration PWR Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure the PWR supply
+  * @rmtoll CR1       SDEN             LL_PWR_ConfigSupply
+  * @param  SupplySource This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
+{
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR1, PWR_CR1_SDEN, SupplySource);
+}
+
+/**
+  * @brief  Get the PWR supply
+  * @rmtoll CR1       SDEN             LL_PWR_GetSupply
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
+{
+  /* Get the power supply configuration */
+  return READ_BIT(PWR->CR1, PWR_CR1_SDEN);
+}
+
+/**
+  * @brief  Enable the SMPS low-power mode.
+  * @rmtoll CR1        LPDS08V         LL_PWR_EnableSMPSLPMode
+  * @note This bit is used to keep the SMPS in PWM mode (MR)
+  * in Stop SVOS 3.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableSMPSLPMode(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_LPDS08V);
+}
+
+/**
+  * @brief  Disable the SMPS low-power mode.
+  * @rmtoll CR1        LPDS08V         LL_PWR_DisableSMPSLPMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableSMPSLPMode(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS08V);
+}
+
+/**
+  * @brief  Check if the SMPS low-power mode is enabled.
+  * @rmtoll CR1        LPDS08V         LL_PWR_IsEnabledSMPSLPMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSLPMode(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_LPDS08V) == (PWR_CR1_LPDS08V)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the pull down on output voltage during power-down mode.
+  * @rmtoll CR2        MODE_PDN         LL_PWR_EnablePullDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePullDown(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
+}
+
+/**
+  * @brief  Disable the pull down on output voltage during power-down mode.
+  * @rmtoll CR1        MODE_PDN         LL_PWR_DisablePullDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePullDown(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
+}
+
+/**
+  * @brief  Check if the pull down on output voltage during power-down mode is enabled.
+  * @rmtoll CR1        MODE_PDN         LL_PWR_IsEnabledPullDown
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPullDown(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_MODE_PDN) == (PWR_CR1_MODE_PDN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the pwr_on pulse low time
+  * @rmtoll CR1        POPL            LL_PWR_SetPwrONPulseLowTime
+  * @param  PulseTime Value between Min_Data = 0 and Max_Data = 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPwrONPulseLowTime(uint32_t PulseTime)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_POPL, (PulseTime << PWR_CR1_POPL_Pos));
+}
+
+/**
+  * @brief  Get the pwr_on pulse low time
+  * @rmtoll CR1        POPL            LL_PWR_GetPwrONPulseLowTime
+  * @retval Value between Min_Data = 0 and Max_Data = 31
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPwrONPulseLowTime(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_POPL) >> PWR_CR1_POPL_Pos);
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR2        PVDEN           LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_PVDEN);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR2        PVDEN           LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDEN);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR2        PVDEN           LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_PVDEN) == (PWR_CR2_PVDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable VCORE monitoring
+  * @rmtoll CR3        VCOREMONEN      LL_PWR_EnableVCOREMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVCOREMonitoring(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
+}
+
+/**
+  * @brief  Disable VCORE monitoring
+  * @rmtoll CR3        VCOREMONEN      LL_PWR_DisableVCOREMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVCOREMonitoring(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
+}
+
+/**
+  * @brief  Check if the VCORE monitoring is enabled
+  * @rmtoll CR3        VCOREMONEN      LL_PWR_IsEnabledVCOREMonitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVCOREMonitoring(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREMONEN) == (PWR_CR3_VCOREMONEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the VDDCORE voltage detector low-level selection
+  * @rmtoll CR3        VCORELLS        LL_PWR_SetVCORELowLevelDetection
+  * @param  Lowlevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE1
+  *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE0
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetVCORELowLevelDetection(uint32_t Lowlevel)
+{
+  MODIFY_REG(PWR->CR3, PWR_CR3_VCORELLS, Lowlevel);
+}
+
+/**
+  * @brief  Get the VDDCORE voltage detector low-level selection
+  * @rmtoll CR3        VCORELLS        LL_PWR_GetVCORELowLevelDetection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE1
+  *         @arg @ref LL_PWR_VCOREMON_LEVEL_SCALE0
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetVCORELowLevelDetection(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VCORELLS));
+}
+
+/**
+  * @brief  Enable I-TCM and D-TCM RAMs retention in Standby mode.
+  * @rmtoll CR4        TCMRBSEN        LL_PWR_EnableTCMSBRetention
+  * @note   When this bit is set, I-TCM and D-TCM RAMs are supplied
+  *         from backup regulator in Standby mode.
+  *         When this bit is reset, I-TCM and D-TCM RAMs can still
+  *         be used in Run and Stop modes, but their content is lost
+  *         in Standby mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableTCMSBRetention(void)
+{
+  SET_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
+}
+
+/**
+  * @brief  Disable I-TCM and D-TCM RAMs retention in Standby mode.
+  * @rmtoll CR4        TCMRBSEN        LL_PWR_DisableTCMSBRetention
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableTCMSBRetention(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
+}
+
+/**
+  * @brief  Check if the I-TCM and D-TCM RAMs retention in Standby mode is enabled
+  * @rmtoll CR4        TCMRBSEN          LL_PWR_IsEnabledTCMSBRetention
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledTCMSBRetention(void)
+{
+  return ((READ_BIT(PWR->CR4, PWR_CR4_TCMRBSEN) == (PWR_CR4_TCMRBSEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable I-TCM FLEXMEM retention in Standby mode.
+  * @rmtoll CR4        TCMFLXRBSEN     LL_PWR_EnableTCMFLXSBRetention
+  * @note   When this bit is set, the I-TCM FLEXMEM is supplied
+  *         from backup regulator in Standby mode.
+  *         When this bit is reset, the I-TCM FLEXMEM can still
+  *         be used in Run and Stop modes, but its content is lost
+  *         in Standby mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableTCMFLXSBRetention(void)
+{
+  SET_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
+}
+
+/**
+  * @brief  Disable I-TCM FLEXMEM RAMs retention in Standby mode.
+  * @rmtoll CR4        TCMFLXRBSEN     LL_PWR_DisableTCMFLXSBRetention
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableTCMFLXSBRetention(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
+}
+
+/**
+  * @brief  Check if the I-TCM FLEXMEM retention in Standby mode is enabled
+  * @rmtoll CR4        TCMFLXRBSEN     LL_PWR_IsEnabledTCMFLXSBRetention
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledTCMFLXSBRetention(void)
+{
+  return ((READ_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN) == (PWR_CR4_TCMFLXRBSEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the main internal Regulator output voltage
+  * @rmtoll VOSCR       VOS            LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the main internal Regulator output voltage. Reflecting the last
+  *         VOS value applied to the PMU.
+  * @rmtoll VOSCR       ACTVOS         LL_PWR_GetRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+  return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOS) == (PWR_VOSCR_ACTVOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable VBAT and Temperature monitoring
+  * @rmtoll BDCR1      MONEN           LL_PWR_EnableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
+{
+  SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+  * @brief  Disable VBAT and Temperature monitoring
+  * @rmtoll BDCR1      MONEN           LL_PWR_DisableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
+{
+  CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+  * @brief  Check if the VBAT and Temperature monitoring is enabled
+  * @rmtoll BDCR1      MONEN           LL_PWR_IsEnabledMonitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
+{
+  return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable BKPSRAM retention in Standby mode.
+  * @rmtoll BDCR2      BKPRBSEN        LL_PWR_EnableBkpSRAMSBRetention
+  * @note   When this bit is set, the backup ram is supplied from backup regulator in Standby and
+  *         VBAT modes.
+  *         When this bit is reset, the backup ram can still be used in Run and Stop modes,
+  *         but its content is lost in Standby and VBAT modes.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkpSRAMSBRetention(void)
+{
+  SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
+}
+
+/**
+  * @brief  Disable BKPSRAM retention in Standby mode.
+  * @rmtoll BDCR2      BKPRBSEN           LL_PWR_DisableBkpSRAMSBRetention
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkpSRAMSBRetention(void)
+{
+  CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
+}
+
+/**
+  * @brief  Check if the BKPSRAM retention in Standby mode is enabled
+  * @rmtoll BDCR2      BKPRBSEN           LL_PWR_IsEnabledBkpSRAMSBRetention
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkpSRAMSBRetention(void)
+{
+  return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN) == (PWR_BDCR2_BKPRBSEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll DBPCR      DBP             LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll DBPCR      DBP             LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll DBPCR      DBP             LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the internal Regulator output voltage in STOP mode
+  * @rmtoll CPUCR      SVOS            LL_PWR_SetStopModeRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3
+  *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the internal Regulator output voltage in STOP mode
+  * @rmtoll CPUCR      SVOS            LL_PWR_GetStopModeRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE3
+  *         @arg @ref LL_PWR_REGU_STOP_VOLTAGE_SCALE5
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
+{
+  return READ_BIT(PWR->CPUCR, PWR_CPUCR_SVOS);
+}
+
+/**
+  * @brief  Set the Power Down mode when device enters deepsleep mode
+  * @rmtoll CPUCR      PDDS            LL_PWR_SetPowerDownModeDS
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP
+  *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPowerDownModeDS(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS, PDMode);
+}
+
+/**
+  * @brief  Get the Power Down mode when device enters deepsleep mode
+  * @rmtoll CPUCR      PDDS            LL_PWR_GetPowerDownModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STOP
+  *         @arg @ref LL_PWR_POWERDOWN_MODE_DS_STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerDownModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS));
+}
+
+/**
+  * @brief  Enable Vdd IO2 voltage supply
+  * @rmtoll SVMCR3     VDDIO2SV        LL_PWR_EnableVddIO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
+}
+
+/**
+  * @brief  Disable Vdd IO2 voltage supply
+  * @rmtoll SVMCR3     VDDIO2SV        LL_PWR_DisableVddIO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
+}
+
+/**
+  * @brief  Check if the Vdd IO2 voltage supply is enabled
+  * @rmtoll SVMCR3     VDDIO2SV        LL_PWR_IsEnabledVddIO2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV) == (PWR_SVMCR3_VDDIO2SV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO3 voltage supply
+  * @rmtoll SVMCR3     VDDIO3SV        LL_PWR_EnableVddIO3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO3(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
+}
+
+/**
+  * @brief  Disable Vdd IO3 voltage supply
+  * @rmtoll SVMCR3     VDDIO3SV        LL_PWR_DisableVddIO3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO3(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
+}
+
+/**
+  * @brief  Check if the Vdd IO3 voltage supply is enabled
+  * @rmtoll SVMCR3     VDDIO3SV        LL_PWR_IsEnabledVddIO3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO3(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV) == (PWR_SVMCR3_VDDIO3SV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO4 voltage supply
+  * @rmtoll SVMCR1     VDDIO4SV        LL_PWR_EnableVddIO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO4(void)
+{
+  SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
+}
+
+/**
+  * @brief  Disable Vdd IO4 voltage supply
+  * @rmtoll SVMCR1     VDDIO4SV        LL_PWR_DisableVddIO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO4(void)
+{
+  CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
+}
+
+/**
+  * @brief  Check if the Vdd IO4 voltage supply is enabled
+  * @rmtoll SVMCR1     VDDIO4SV        LL_PWR_IsEnabledVddIO4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4(void)
+{
+  return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV) == (PWR_SVMCR1_VDDIO4SV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO5 voltage supply
+  * @rmtoll SVMCR2     VDDIO5SV        LL_PWR_EnableVddIO5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO5(void)
+{
+  SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
+}
+
+/**
+  * @brief  Disable Vdd IO5 voltage supply
+  * @rmtoll SVMCR2     VDDIO5SV        LL_PWR_DisableVddIO5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO5(void)
+{
+  CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
+}
+
+/**
+  * @brief  Check if the Vdd IO5 voltage supply is enabled
+  * @rmtoll SVMCR2     VDDIO5SV        LL_PWR_IsEnabledVddIO5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5(void)
+{
+  return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV) == (PWR_SVMCR2_VDDIO5SV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd USB voltage supply
+  * @rmtoll SVMCR3     USB33SV         LL_PWR_EnableVddUSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
+}
+
+/**
+  * @brief  Disable Vdd USB voltage supply
+  * @rmtoll SVMCR3     USB33SV         LL_PWR_DisableVddUSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
+}
+
+/**
+  * @brief  Check if the Vdd USB voltage supply is enabled
+  * @rmtoll SVMCR3     USB33SV         LL_PWR_IsEnabledVddUSB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV) == (PWR_SVMCR3_USB33SV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd ADC voltage supply
+  * @rmtoll SVMCR3     ASV             LL_PWR_EnableVddADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddADC(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
+}
+
+/**
+  * @brief  Disable Vdd ADC voltage supply
+  * @rmtoll SVMCR3     ASV             LL_PWR_DisableVddADC
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddADC(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
+}
+
+/**
+  * @brief  Check if the Vdd ADC voltage supply is enabled
+  * @rmtoll SVMCR3     ASV             LL_PWR_IsEnabledVddADC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddADC(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV) == (PWR_SVMCR3_ASV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO2 voltage monitoring
+  * @rmtoll SVMCR3     VDDIO2VMEN      LL_PWR_EnableVddIO2Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO2Monitoring(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
+}
+
+/**
+  * @brief  Disable Vdd IO2 voltage monitoring
+  * @rmtoll SVMCR3     VDDIO2VMEN      LL_PWR_DisableVddIO2Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO2Monitoring(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
+}
+
+/**
+  * @brief  Check if the Vdd IO2 voltage monitoring is enabled
+  * @rmtoll SVMCR3     VDDIO2VMEN      LL_PWR_IsEnabledVddIO2Monitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2Monitoring(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN) == (PWR_SVMCR3_VDDIO2VMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO3 voltage monitoring
+  * @rmtoll SVMCR3     VDDIO3VMEN      LL_PWR_EnableVddIO3Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO3Monitoring(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
+}
+
+/**
+  * @brief  Disable Vdd IO3 voltage monitoring
+  * @rmtoll SVMCR3     VDDIO3VMEN      LL_PWR_DisableVddIO3Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO3Monitoring(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
+}
+
+/**
+  * @brief  Check if the Vdd IO3 voltage monitoring is enabled
+  * @rmtoll SVMCR3     VDDIO3VMEN      LL_PWR_IsEnabledVddIO3Monitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO3Monitoring(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN) == (PWR_SVMCR3_VDDIO3VMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO4 voltage monitoring
+  * @rmtoll SVMCR1     VDDIO4VMEN      LL_PWR_EnableVddIO4Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO4Monitoring(void)
+{
+  SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
+}
+
+/**
+  * @brief  Disable Vdd IO4 voltage monitoring
+  * @rmtoll SVMCR1     VDDIO4VMEN      LL_PWR_DisableVddIO4Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO4Monitoring(void)
+{
+  CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
+}
+
+/**
+  * @brief  Check if the Vdd IO4 voltage monitoring is enabled
+  * @rmtoll SVMCR1     VDDIO4VMEN      LL_PWR_IsEnabledVddIO4Monitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4Monitoring(void)
+{
+  return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN) == (PWR_SVMCR1_VDDIO4VMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO5 voltage monitoring
+  * @rmtoll SVMCR2     VDDIO5VMEN      LL_PWR_EnableVddIO5Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO5Monitoring(void)
+{
+  SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
+}
+
+/**
+  * @brief  Disable Vdd IO5 voltage monitoring
+  * @rmtoll SVMCR2     VDDIO5VMEN      LL_PWR_DisableVddIO5Monitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO5Monitoring(void)
+{
+  CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
+}
+
+/**
+  * @brief  Check if the Vdd IO5 voltage monitoring is enabled
+  * @rmtoll SVMCR2     VDDIO5VMEN      LL_PWR_IsEnabledVddIO5Monitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5Monitoring(void)
+{
+  return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN) == (PWR_SVMCR2_VDDIO5VMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd ADC voltage monitoring
+  * @rmtoll SVMCR3     AVMEN           LL_PWR_EnableVddADCMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddADCMonitoring(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
+}
+
+/**
+  * @brief  Disable Vdd ADC voltage monitoring
+  * @rmtoll SVMCR3     AVMEN           LL_PWR_DisableVddADCMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddADCMonitoring(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
+}
+
+/**
+  * @brief  Check if the Vdd ADC voltage monitoring is enabled
+  * @rmtoll SVMCR3     AVMEN           LL_PWR_IsEnabledVddADCMonitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddADCMonitoring(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN) == (PWR_SVMCR3_AVMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd USB voltage monitoring
+  * @rmtoll SVMCR3     USB33VMEN       LL_PWR_EnableVddUSBMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddUSBMonitoring(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
+}
+
+/**
+  * @brief  Disable Vdd USB voltage monitoring
+  * @rmtoll SVMCR3     USB33VMEN       LL_PWR_DisableVddUSBMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddUSBMonitoring(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
+}
+
+/**
+  * @brief  Check if the Vdd USB voltage monitoring is enabled
+  * @rmtoll SVMCR3     USB33VMEN       LL_PWR_IsEnabledVddUSBMonitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSBMonitoring(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN) == (PWR_SVMCR3_USB33VMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the VDD I/O voltage range
+  * @rmtoll SVMCR3     VDDIOVRSEL      LL_PWR_SetVddIOVoltageRange
+  * @param  VoltageRange This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
+  *         operation.
+  *         Setting this configuration while VDD is in 3v3 range damages the device.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetVddIOVoltageRange(uint32_t VoltageRange)
+{
+  MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL, (VoltageRange << PWR_SVMCR3_VDDIOVRSEL_Pos));
+}
+
+/**
+  * @brief  Get the VDD IO voltage range
+  * @rmtoll SVMCR3     VDDIOVRSEL      LL_PWR_GetVddIOVoltageRange
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetVddIOVoltageRange(void)
+{
+  return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL) >> PWR_SVMCR3_VDDIOVRSEL_Pos);
+}
+
+/**
+  * @brief  Set the VDD IO2 voltage range
+  * @rmtoll SVMCR3     VDDIO2VRSEL     LL_PWR_SetVddIO2VoltageRange
+  * @param  VoltageRange This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
+  *         operation.
+  *         Setting this configuration while VDD is in 3v3 range damages the device.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetVddIO2VoltageRange(uint32_t VoltageRange)
+{
+  MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO2VRSEL_Pos));
+}
+
+/**
+  * @brief  Get the VDD IO2 voltage range
+  * @rmtoll SVMCR3     VDDIO2VRSEL     LL_PWR_GetVddIO2VoltageRange
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetVddIO2VoltageRange(void)
+{
+  return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL) >> PWR_SVMCR3_VDDIO2VRSEL_Pos);
+}
+
+/**
+  * @brief  Set the VDD IO3 voltage range
+  * @rmtoll SVMCR3     VDDIO3VRSEL     LL_PWR_SetVddIO3VoltageRange
+  * @param  VoltageRange This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
+  *         operation.
+  *         Setting this configuration while VDD is in 3v3 range damages the device.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetVddIO3VoltageRange(uint32_t VoltageRange)
+{
+  MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL, (VoltageRange << PWR_SVMCR3_VDDIO3VRSEL_Pos));
+}
+
+/**
+  * @brief  Get the VDD IO3 voltage range
+  * @rmtoll SVMCR3     VDDIO3VRSEL     LL_PWR_GetVddIO3VoltageRange
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetVddIO3VoltageRange(void)
+{
+  return (uint32_t)(READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL) >> PWR_SVMCR3_VDDIO3VRSEL_Pos);
+}
+
+/**
+  * @brief  Set the VDD IO4 voltage range
+  * @rmtoll SVMCR1     VDDIO4VRSEL     LL_PWR_SetVddIO4VoltageRange
+  * @param  VoltageRange This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
+  *         operation.
+  *         Setting this configuration while VDD is in 3v3 range damages the device.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetVddIO4VoltageRange(uint32_t VoltageRange)
+{
+  MODIFY_REG(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL, (VoltageRange << PWR_SVMCR1_VDDIO4VRSEL_Pos));
+}
+
+/**
+  * @brief  Get the VDD IO4 voltage range
+  * @rmtoll SVMCR1     VDDIO4VRSEL     LL_PWR_GetVddIO4VoltageRange
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetVddIO4VoltageRange(void)
+{
+  return (uint32_t)(READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL) >> PWR_SVMCR1_VDDIO4VRSEL_Pos);
+}
+
+/**
+  * @brief  Set the VDD IO5 voltage range
+  * @rmtoll SVMCR2     VDDIO5VRSEL     LL_PWR_SetVddIO5VoltageRange
+  * @param  VoltageRange This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  * @note   HSLV_VDD option bit must be set to allow 1v8 voltage range
+  *         operation.
+  *         Setting this configuration while VDD is in 3v3 range damages the device.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetVddIO5VoltageRange(uint32_t VoltageRange)
+{
+  MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, (VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos));
+}
+
+/**
+  * @brief  Get the VDD IO5 voltage range
+  * @rmtoll SVMCR2     VDDIO5VRSEL     LL_PWR_GetVddIO5VoltageRange
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_3V3
+  *         @arg @ref LL_PWR_VDDIO_VOLTAGE_RANGE_1V8
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetVddIO5VoltageRange(void)
+{
+  return (uint32_t)(READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos);
+}
+
+/**
+  * @brief  Enable Vdd IO4 voltage range retained in Standby mode
+  * @rmtoll SVMCR1     VDDIO4VRSTBY    LL_PWR_EnableVddIO4VoltageRangeSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO4VoltageRangeSB(void)
+{
+  SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
+}
+
+/**
+  * @brief  Disable Vdd IO4 voltage range retained in Standby mode
+  * @rmtoll SVMCR1     VDDIO4VRSTBY    LL_PWR_DisableVddIO4VoltageRangeSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO4VoltageRangeSB(void)
+{
+  CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
+}
+
+/**
+  * @brief  Check if the Vdd IO4 voltage range retained in Standby mode  is enabled
+  * @rmtoll SVMCR1     VDDIO4VRSTBY    LL_PWR_IsEnabledVddIO4VoltageRangeSB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO4VoltageRangeSB(void)
+{
+  return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY) == (PWR_SVMCR1_VDDIO4VRSTBY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Vdd IO5 voltage range retained in Standby mode
+  * @rmtoll SVMCR2     VDDIO5VRSTBY    LL_PWR_EnableVddIO5VoltageRangeSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableVddIO5VoltageRangeSB(void)
+{
+  SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
+}
+
+/**
+  * @brief  Disable Vdd IO5 voltage range retained in Standby mode
+  * @rmtoll SVMCR2     VDDIO5VRSTBY    LL_PWR_DisableVddIO5VoltageRangeSB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableVddIO5VoltageRangeSB(void)
+{
+  CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
+}
+
+/**
+  * @brief  Check if the Vdd IO5 voltage range retained in Standby mode  is enabled
+  * @rmtoll SVMCR2     VDDIO5VRSTBY    LL_PWR_IsEnabledVddIO5VoltageRangeSB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO5VoltageRangeSB(void)
+{
+  return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY) == (PWR_SVMCR2_VDDIO5VRSTBY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR    WKUPEN1         LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR    WKUPEN2         LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR    WKUPEN3         LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR    WKUPEN4         LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR   WKUPEN1          LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN2          LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN3          LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN4          LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll WKUPEPR    WKUPEN1         LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR    WKUPEN2         LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR    WKUPEN3         LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR    WKUPEN4         LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity low for the event detection
+  * @rmtoll WKUPEPR    WKUPP1          LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR    WKUPP2          LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR    WKUPP3          LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR    WKUPP4          LL_PWR_SetWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity high for the event detection
+  * @rmtoll WKUPEPR    WKUPP1          LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR    WKUPP2          LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR    WKUPP3          LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR    WKUPP4          LL_PWR_SetWakeUpPinPolarityHigh
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Check if the Wake-Up pin polarity is low for event detection
+  * @rmtoll WKUPEPR    WKUPP1          LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR    WKUPP2          LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR    WKUPP3          LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR    WKUPP4          LL_PWR_IsWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull None
+  * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR    WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR    WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR    WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+             (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+             (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Up
+  * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR    WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR    WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR    WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+             (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+             (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Down
+  * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR    WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR    WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR    WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+             (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+             (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Get the Wake-Up pin pull
+  * @rmtoll WKUPEPR    WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR    WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR    WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR    WKUPPUPD4       LL_PWR_GetWakeUpPinPull\
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
+{
+  uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+
+  return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(
+                                                                 WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate whether the voltage level is ready for current actual used VOS
+  * @rmtoll VOSCR        ACTVOSRDY     LL_PWR_IsActiveFlag_ACTVOSRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOSRDY(void)
+{
+  return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_ACTVOSRDY) == (PWR_VOSCR_ACTVOSRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CR2        PVDO            LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_PVDO) == (PWR_CR2_PVDO)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VCORE level is above or below low threshold
+  * @rmtoll CR3      VCOREL           LL_PWR_IsActiveFlag_VCOREL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VCOREL(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREL) == (PWR_CR3_VCOREL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VCORE level is above or below high threshold
+  * @rmtoll CR3      VCOREH           LL_PWR_IsActiveFlag_VCOREH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VCOREH(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_VCOREH) == (PWR_CR3_VCOREH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range
+  *         or if its output voltage is still changing to the required voltage level
+  * @rmtoll VOSCR      VOSRDY          LL_PWR_IsActiveFlag_VOSRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSRDY(void)
+{
+  return ((READ_BIT(PWR->VOSCR, PWR_VOSCR_VOSRDY) == (PWR_VOSCR_VOSRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below low threshold
+  * @rmtoll BDCR1      VBATL           LL_PWR_IsActiveFlag_VBATL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
+{
+  return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATL) == (PWR_BDCR1_VBATL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below high threshold
+  * @rmtoll BDCR1      VBATH           LL_PWR_IsActiveFlag_VBATH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
+{
+  return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATH) == (PWR_BDCR1_VBATH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below low threshold
+  * @rmtoll BDCR1      TEMPL           LL_PWR_IsActiveFlag_TEMPL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
+{
+  return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPL) == (PWR_BDCR1_TEMPL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below high threshold
+  * @rmtoll BDCR1      TEMPH           LL_PWR_IsActiveFlag_TEMPH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
+{
+  return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPH) == (PWR_BDCR1_TEMPH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get System Stop Flag
+  * @rmtoll CPUCR      STOPF           LL_PWR_IsActiveFlag_STOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get System Standby Flag
+  * @rmtoll CPUCR      SBF             LL_PWR_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get VDDIO2 ready Flag
+  * @rmtoll SVMCR3     VDDIO2RDY       LL_PWR_IsActiveFlag_VDDIO2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2RDY(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2RDY) == (PWR_SVMCR3_VDDIO2RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get VDDIO3 ready Flag
+  * @rmtoll SVMCR3     VDDIO3RDY       LL_PWR_IsActiveFlag_VDDIO3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO3RDY(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3RDY) == (PWR_SVMCR3_VDDIO3RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get VDDIO4 ready Flag
+  * @rmtoll SVMCR1     VDDIO4RDY       LL_PWR_IsActiveFlag_VDDIO4RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO4RDY(void)
+{
+  return ((READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4RDY) == (PWR_SVMCR1_VDDIO4RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get VDDIO5 ready Flag
+  * @rmtoll SVMCR2     VDDIO5RDY       LL_PWR_IsActiveFlag_VDDIO5RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO5RDY(void)
+{
+  return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5RDY) == (PWR_SVMCR2_VDDIO5RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get VDD ADC ready Flag
+  * @rmtoll SVMCR3     ARDY            LL_PWR_IsActiveFlag_ARDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ARDY(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_ARDY) == (PWR_SVMCR3_ARDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get VDD USB33 ready Flag
+  * @rmtoll SVMCR3     USB33RDY        LL_PWR_IsActiveFlag_USB33RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB33RDY(void)
+{
+  return ((READ_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33RDY) == (PWR_SVMCR3_USB33RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 1
+  * @rmtoll WKUPSR     WKUPF1          LL_PWR_IsActiveFlag_WU1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+  return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF1) == (PWR_WKUPSR_WKUPF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 2
+  * @rmtoll WKUPSR     WKUPF2          LL_PWR_IsActiveFlag_WU2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+  return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF2) == (PWR_WKUPSR_WKUPF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 3
+  * @rmtoll WKUPSR     WKUPF3          LL_PWR_IsActiveFlag_WU3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+  return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF3) == (PWR_WKUPSR_WKUPF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 4
+  * @rmtoll WKUPSR     WKUPF4          LL_PWR_IsActiveFlag_WU4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+  return ((READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF4) == (PWR_WKUPSR_WKUPF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear STOP and STANDBY and flags
+  * @rmtoll CPUCR      CSSF            LL_PWR_ClearFlag_STOP_SB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_STOP_SB(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 1
+  * @rmtoll WKUPCR     WKUPC1          LL_PWR_ClearFlag_WU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 2
+  * @rmtoll WKUPCR     WKUPC2          LL_PWR_ClearFlag_WU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 3
+  * @rmtoll WKUPCR     WKUPC3          LL_PWR_ClearFlag_WU3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 4
+  * @rmtoll WKUPCR     WKUPC4          LL_PWR_ClearFlag_WU4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
+}
+
+/**
+  * @brief  Clear all wake up flags.
+  * @rmtoll WUSCR          WKUPC         LL_PWR_ClearFlag_WU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
+  * @{
+  */
+
+/**
+  * @brief  Configure privilege attribute mode.
+  * @note   This API can be executed only by CPU in privilege mode.
+  * @rmtoll PRIVCFGR   PRIV0           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   PRIV1           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   PRIV2           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   PRIV3           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   PRIV4           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   PRIV5           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   PRIV6           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   PRIV7           LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   WKUPPRIV1       LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   WKUPPRIV2       LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   WKUPPRIV3       LL_PWR_ConfigPrivilege\n
+  *         PRIVCFGR   WKUPPRIV4       LL_PWR_ConfigPrivilege
+  * @param  PrivilegeConfig This parameter can be the full combination
+  *         of the following values:
+  *         @arg @ref LL_PWR_PRIV0_PRIV or LL_PWR_PRIV0_NPRIV
+  *         @arg @ref LL_PWR_PRIV1_PRIV or LL_PWR_PRIV1_NPRIV
+  *         @arg @ref LL_PWR_PRIV2_PRIV or LL_PWR_PRIV2_NPRIV
+  *         @arg @ref LL_PWR_PRIV3_PRIV or LL_PWR_PRIV3_NPRIV
+  *         @arg @ref LL_PWR_PRIV4_PRIV or LL_PWR_PRIV4_NPRIV
+  *         @arg @ref LL_PWR_PRIV5_PRIV or LL_PWR_PRIV5_NPRIV
+  *         @arg @ref LL_PWR_PRIV6_PRIV or LL_PWR_PRIV6_NPRIV
+  *         @arg @ref LL_PWR_PRIV7_PRIV or LL_PWR_PRIV7_NPRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN1_NPRIV or LL_PWR_WAKEUP_PIN1_PRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN2_NPRIV or LL_PWR_WAKEUP_PIN2_PRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN3_NPRIV or LL_PWR_WAKEUP_PIN3_PRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN4_NPRIV or LL_PWR_WAKEUP_PIN4_PRIV
+  * @retval None.
+  */
+__STATIC_INLINE void LL_PWR_ConfigPrivilege(uint32_t PrivilegeConfig)
+{
+  WRITE_REG(PWR->PRIVCFGR, PrivilegeConfig);
+}
+
+/**
+  * @brief  Get privilege attribute configuration.
+  * @rmtoll PRIVCFGR    PRIV0            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    PRIV1            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    PRIV2            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    PRIV3            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    PRIV4            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    PRIV5            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    PRIV6            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    PRIV7            LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    WKUPPRIV1        LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    WKUPPRIV2        LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    WKUPPRIV3        LL_PWR_GetConfigPrivilege\n
+  *         PRIVCFGR    WKUPPRIV4        LL_PWR_GetConfigPrivilege
+  * @retval Returned value is the combination of the following values:
+  *         @arg @ref LL_PWR_PRIV0_PRIV or LL_PWR_PRIV0_NPRIV
+  *         @arg @ref LL_PWR_PRIV1_PRIV or LL_PWR_PRIV1_NPRIV
+  *         @arg @ref LL_PWR_PRIV2_PRIV or LL_PWR_PRIV2_NPRIV
+  *         @arg @ref LL_PWR_PRIV3_PRIV or LL_PWR_PRIV3_NPRIV
+  *         @arg @ref LL_PWR_PRIV4_PRIV or LL_PWR_PRIV4_NPRIV
+  *         @arg @ref LL_PWR_PRIV5_PRIV or LL_PWR_PRIV5_NPRIV
+  *         @arg @ref LL_PWR_PRIV6_PRIV or LL_PWR_PRIV6_NPRIV
+  *         @arg @ref LL_PWR_PRIV7_PRIV or LL_PWR_PRIV7_NPRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN1_NPRIV or LL_PWR_WAKEUP_PIN1_PRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN2_NPRIV or LL_PWR_WAKEUP_PIN2_PRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN3_NPRIV or LL_PWR_WAKEUP_PIN3_PRIV
+  *         @arg @ref LL_PWR_WAKEUP_PIN4_NPRIV or LL_PWR_WAKEUP_PIN4_PRIV
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetConfigPrivilege(void)
+{
+  return (READ_REG(PWR->PRIVCFGR));
+}
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+/**
+  * @brief  Configure secure attribute mode.
+  * @note   This API can be executed only by CPU in secure mode.
+  * @rmtoll SECCFGR    SEC0            LL_PWR_ConfigSecure\n
+  *         SECCFGR    SEC1            LL_PWR_ConfigSecure\n
+  *         SECCFGR    SEC2            LL_PWR_ConfigSecure\n
+  *         SECCFGR    SEC3            LL_PWR_ConfigSecure\n
+  *         SECCFGR    SEC4            LL_PWR_ConfigSecure\n
+  *         SECCFGR    SEC5            LL_PWR_ConfigSecure\n
+  *         SECCFGR    SEC6            LL_PWR_ConfigSecure\n
+  *         SECCFGR    SEC7            LL_PWR_ConfigSecure\n
+  *         SECCFGR    WKUPSEC1        LL_PWR_ConfigSecure\n
+  *         SECCFGR    WKUPSEC2        LL_PWR_ConfigSecure\n
+  *         SECCFGR    WKUPSEC3        LL_PWR_ConfigSecure\n
+  *         SECCFGR    WKUPSEC4        LL_PWR_ConfigSecure
+  * @param  SecureConfig This parameter can be the full combination
+  *         of the following values:
+  *         @arg @ref LL_PWR_SEC0_SEC or LL_PWR_SEC0_NSEC
+  *         @arg @ref LL_PWR_SEC1_SEC or LL_PWR_SEC1_NSEC
+  *         @arg @ref LL_PWR_SEC2_SEC or LL_PWR_SEC2_NSEC
+  *         @arg @ref LL_PWR_SEC3_SEC or LL_PWR_SEC3_NSEC
+  *         @arg @ref LL_PWR_SEC4_SEC or LL_PWR_SEC4_NSEC
+  *         @arg @ref LL_PWR_SEC5_SEC or LL_PWR_SEC5_NSEC
+  *         @arg @ref LL_PWR_SEC6_SEC or LL_PWR_SEC6_NSEC
+  *         @arg @ref LL_PWR_SEC7_SEC or LL_PWR_SEC7_NSEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
+  * @retval None.
+  */
+__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
+{
+  WRITE_REG(PWR->SECCFGR, SecureConfig);
+}
+
+/**
+  * @brief  Get secure attribute configuration.
+  * @note   This API can be executed only by CPU in secure mode.
+  * @rmtoll SECCFGR    SEC0            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    SEC1            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    SEC2            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    SEC3            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    SEC4            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    SEC5            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    SEC6            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    SEC7            LL_PWR_GetConfigSecure\n
+  *         SECCFGR    WKUPSEC1        LL_PWR_GetConfigSecure\n
+  *         SECCFGR    WKUPSEC2        LL_PWR_GetConfigSecure\n
+  *         SECCFGR    WKUPSEC3        LL_PWR_GetConfigSecure\n
+  *         SECCFGR    WKUPSEC4        LL_PWR_GetConfigSecure
+  * @retval Returned value is the combination of the following values:
+  *         @arg @ref LL_PWR_SEC0_SEC or LL_PWR_SEC0_NSEC
+  *         @arg @ref LL_PWR_SEC1_SEC or LL_PWR_SEC1_NSEC
+  *         @arg @ref LL_PWR_SEC2_SEC or LL_PWR_SEC2_NSEC
+  *         @arg @ref LL_PWR_SEC3_SEC or LL_PWR_SEC3_NSEC
+  *         @arg @ref LL_PWR_SEC4_SEC or LL_PWR_SEC4_NSEC
+  *         @arg @ref LL_PWR_SEC5_SEC or LL_PWR_SEC5_NSEC
+  *         @arg @ref LL_PWR_SEC6_SEC or LL_PWR_SEC6_NSEC
+  *         @arg @ref LL_PWR_SEC7_SEC or LL_PWR_SEC7_NSEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
+  *         @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
+{
+  return (READ_REG(PWR->SECCFGR));
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U) */
+/**
+  * @}
+  */
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* defined (USE_FULL_LL_DRIVER) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32N6xx_LL_PWR_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rcc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rcc.h
new file mode 100644
index 000000000..657089df7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rcc.h
@@ -0,0 +1,8774 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_RCC_H
+#define STM32N6xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+#include <math.h>
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+  * @{
+  */
+/* Constants for LL_CLKSOURCE_xxx() macros
+   31           24            16           8             0
+   --------------------------------------------------------
+   | Mask        | ClkSource   |  Bit       | Register    |
+   |             |  Config     | Position   | Offset      |
+   --------------------------------------------------------*/
+
+/* Clock source register offset Vs CCIPR1 register */
+#define CCIPR1_OFFSET      0x0UL
+#define CCIPR2_OFFSET      0x4UL
+#define CCIPR3_OFFSET      0x8UL
+#define CCIPR4_OFFSET      0xCUL
+#define CCIPR5_OFFSET      0x10UL
+#define CCIPR6_OFFSET      0x14UL
+#define CCIPR7_OFFSET      0x18UL
+#define CCIPR8_OFFSET      0x1CUL
+#define CCIPR9_OFFSET      0x20UL
+#define CCIPR12_OFFSET     0x2CUL
+#define CCIPR13_OFFSET     0x30UL
+#define CCIPR14_OFFSET     0x34UL
+
+#define LL_RCC_REG_SHIFT     0U
+#define LL_RCC_POS_SHIFT     8U
+#define LL_RCC_CONFIG_SHIFT  16U
+#define LL_RCC_MASK_SHIFT    24U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+#if !defined(UNUSED)
+#define UNUSED(x) ((void)(x))
+#endif /* UNUSED */
+
+#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)
+
+#define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) &\
+                                             0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\
+                                             0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)
+
+#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
+                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
+                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
+                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;
+  uint32_t CPUCLK_Frequency;
+  uint32_t HCLK_Frequency;
+  uint32_t PCLK1_Frequency;
+  uint32_t PCLK2_Frequency;
+  uint32_t PCLK4_Frequency;
+  uint32_t PCLK5_Frequency;
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    48000000U  /*!< Value of the HSE oscillator in Hz */  /* N6 FPGA was 30 MHz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */  /* N6 FPGA was 48 MHz */
+#endif /* HSI_VALUE */
+
+#if !defined  (MSI_VALUE)
+#define MSI_VALUE    4000000U   /*!< Value of the MSI oscillator in Hz */
+#endif /* MSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */  /* N6 FPGA was 32 KHz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
+  * @{
+  */
+#define LL_RCC_HSI_DIV_1                   0U
+#define LL_RCC_HSI_DIV_2                   RCC_HSICFGR_HSIDIV_0
+#define LL_RCC_HSI_DIV_4                   RCC_HSICFGR_HSIDIV_1
+#define LL_RCC_HSI_DIV_8                   RCC_HSICFGR_HSIDIV
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MSIFREQ  MSI oscillator frequency select
+  * @{
+  */
+#define LL_RCC_MSI_FREQ_4MHZ               0U
+#define LL_RCC_MSI_FREQ_16MHZ              RCC_MSICFGR_MSIFREQSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                0U
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_LSECFGR_LSEDRV_1
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_LSECFGR_LSEDRV_0
+#define LL_RCC_LSEDRIVE_HIGH               RCC_LSECFGR_LSEDRV
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_HSECSSBYP_DIV  HSI divider to apply for replacement of HSE on CSS bypass
+  * @{
+  */
+#define LL_RCC_HSECSSBYP_DIV_1             0U
+#define LL_RCC_HSECSSBYP_DIV_2             RCC_HSECFGR_HSECSSBPRE_0
+#define LL_RCC_HSECSSBYP_DIV_3             RCC_HSECFGR_HSECSSBPRE_1
+#define LL_RCC_HSECSSBYP_DIV_4             (RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
+#define LL_RCC_HSECSSBYP_DIV_5             RCC_HSECFGR_HSECSSBPRE_2
+#define LL_RCC_HSECSSBYP_DIV_6             (RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_0)
+#define LL_RCC_HSECSSBYP_DIV_7             (RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_1)
+#define LL_RCC_HSECSSBYP_DIV_8             (RCC_HSECFGR_HSECSSBPRE_2 |\
+                                            RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
+#define LL_RCC_HSECSSBYP_DIV_9             RCC_HSECFGR_HSECSSBPRE_3
+#define LL_RCC_HSECSSBYP_DIV_10            (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_0)
+#define LL_RCC_HSECSSBYP_DIV_11            (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_1)
+#define LL_RCC_HSECSSBYP_DIV_12            (RCC_HSECFGR_HSECSSBPRE_3 |\
+                                            RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
+#define LL_RCC_HSECSSBYP_DIV_13            (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_2)
+#define LL_RCC_HSECSSBYP_DIV_14            (RCC_HSECFGR_HSECSSBPRE_3 |\
+                                            RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_0)
+#define LL_RCC_HSECSSBYP_DIV_15            (RCC_HSECFGR_HSECSSBPRE_3 |\
+                                            RCC_HSECFGR_HSECSSBPRE_2 | RCC_HSECFGR_HSECSSBPRE_1)
+#define LL_RCC_HSECSSBYP_DIV_16            (RCC_HSECFGR_HSECSSBPRE_3 | RCC_HSECFGR_HSECSSBPRE_2 |\
+                                            RCC_HSECFGR_HSECSSBPRE_1 | RCC_HSECFGR_HSECSSBPRE_0)
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EC_CPU_CLKSOURCE  CPU clock switch
+  * @{
+  */
+#define LL_RCC_CPU_CLKSOURCE_HSI           0U                                       /*!< Select HSI as CPU clock */
+#define LL_RCC_CPU_CLKSOURCE_MSI           RCC_CFGR1_CPUSW_0                        /*!< Select MSI as CPU clock */
+#define LL_RCC_CPU_CLKSOURCE_HSE           RCC_CFGR1_CPUSW_1                        /*!< Select HSE as CPU clock */
+#define LL_RCC_CPU_CLKSOURCE_IC1           (RCC_CFGR1_CPUSW_1 | RCC_CFGR1_CPUSW_0)  /*!< Select IC1 as CPU clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CPU_CLKSOURCE_STATUS  CPU clock switch status
+  * @{
+  */
+#define LL_RCC_CPU_CLKSOURCE_STATUS_HSI    0U                                        /*!< HSI used as CPU clock */
+#define LL_RCC_CPU_CLKSOURCE_STATUS_MSI    RCC_CFGR1_CPUSWS_0                        /*!< MSI used as CPU clock */
+#define LL_RCC_CPU_CLKSOURCE_STATUS_HSE    RCC_CFGR1_CPUSWS_1                        /*!< HSE used as CPU clock */
+#define LL_RCC_CPU_CLKSOURCE_STATUS_IC1    (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0) /*!< IC1 used as CPU clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System bus clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           0U                                        /*!< Select HSI as system bus clocks */
+#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR1_SYSSW_0                         /*!< Select MSI as system bus clocks */
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR1_SYSSW_1                         /*!< Select HSE as system bus clocks */
+#define LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11  (RCC_CFGR1_SYSSW_1 | RCC_CFGR1_SYSSW_0)   /*!< Select IC2/IC6/IC11 as system bus clocks */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System bus clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    0U                                        /*!< HSI used as system bus clocks */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR1_SYSSWS_0                        /*!< MSI used as system bus clocks */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR1_SYSSWS_1                        /*!< HSE used as system bus clocks */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11 (RCC_CFGR1_SYSSWS_1 | RCC_CFGR1_SYSSWS_0) /*!< IC2/IC6/IC11 used as system bus clocks */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source
+  * @{
+  */
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     0U
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_MSI     RCC_CFGR1_STOPWUCK
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler
+  * @{
+  */
+#define LL_RCC_AHB_DIV_1                   0U
+#define LL_RCC_AHB_DIV_2                   RCC_CFGR2_HPRE_0
+#define LL_RCC_AHB_DIV_4                   RCC_CFGR2_HPRE_1
+#define LL_RCC_AHB_DIV_8                   (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)
+#define LL_RCC_AHB_DIV_16                  RCC_CFGR2_HPRE_2
+#define LL_RCC_AHB_DIV_32                  (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0)
+#define LL_RCC_AHB_DIV_64                  (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1)
+#define LL_RCC_AHB_DIV_128                 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB1 prescaler
+  * @{
+  */
+#define LL_RCC_APB1_DIV_1                  0U
+#define LL_RCC_APB1_DIV_2                  RCC_CFGR2_PPRE1_0
+#define LL_RCC_APB1_DIV_4                  RCC_CFGR2_PPRE1_1
+#define LL_RCC_APB1_DIV_8                  (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0)
+#define LL_RCC_APB1_DIV_16                 RCC_CFGR2_PPRE1_2
+#define LL_RCC_APB1_DIV_32                 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0)
+#define LL_RCC_APB1_DIV_64                 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1)
+#define LL_RCC_APB1_DIV_128                (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB2 prescaler
+  * @{
+  */
+#define LL_RCC_APB2_DIV_1                  0U
+#define LL_RCC_APB2_DIV_2                  RCC_CFGR2_PPRE2_0
+#define LL_RCC_APB2_DIV_4                  RCC_CFGR2_PPRE2_1
+#define LL_RCC_APB2_DIV_8                  (RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)
+#define LL_RCC_APB2_DIV_16                 RCC_CFGR2_PPRE2_2
+#define LL_RCC_APB2_DIV_32                 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0)
+#define LL_RCC_APB2_DIV_64                 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1)
+#define LL_RCC_APB2_DIV_128                (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB4_DIV  APB4 prescaler
+  * @{
+  */
+#define LL_RCC_APB4_DIV_1                  0U
+#define LL_RCC_APB4_DIV_2                  RCC_CFGR2_PPRE4_0
+#define LL_RCC_APB4_DIV_4                  RCC_CFGR2_PPRE4_1
+#define LL_RCC_APB4_DIV_8                  (RCC_CFGR2_PPRE4_1 | RCC_CFGR2_PPRE4_0)
+#define LL_RCC_APB4_DIV_16                 RCC_CFGR2_PPRE4_2
+#define LL_RCC_APB4_DIV_32                 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_0)
+#define LL_RCC_APB4_DIV_64                 (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_1)
+#define LL_RCC_APB4_DIV_128                (RCC_CFGR2_PPRE4_2 | RCC_CFGR2_PPRE4_1 | RCC_CFGR2_PPRE4_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB5_DIV  APB5 prescaler
+  * @{
+  */
+#define LL_RCC_APB5_DIV_1                  0U
+#define LL_RCC_APB5_DIV_2                  RCC_CFGR2_PPRE5_0
+#define LL_RCC_APB5_DIV_4                  RCC_CFGR2_PPRE5_1
+#define LL_RCC_APB5_DIV_8                  (RCC_CFGR2_PPRE5_1 | RCC_CFGR2_PPRE5_0)
+#define LL_RCC_APB5_DIV_16                 RCC_CFGR2_PPRE5_2
+#define LL_RCC_APB5_DIV_32                 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_0)
+#define LL_RCC_APB5_DIV_64                 (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_1)
+#define LL_RCC_APB5_DIV_128                (RCC_CFGR2_PPRE5_2 | RCC_CFGR2_PPRE5_1 | RCC_CFGR2_PPRE5_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx  MCO selection
+  * @{
+  */
+#define LL_RCC_MCO1                        RCC_MISCENR_MCO1EN
+#define LL_RCC_MCO2                        RCC_MISCENR_MCO2EN
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_HSI              ((RCC_CCIPR5_MCO1SEL<<16U) | 0U)
+#define LL_RCC_MCO1SOURCE_LSE              ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_0)
+#define LL_RCC_MCO1SOURCE_MSI              ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_1)
+#define LL_RCC_MCO1SOURCE_LSI              ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_1 | RCC_CCIPR5_MCO1SEL_0)
+#define LL_RCC_MCO1SOURCE_HSE              ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2)
+#define LL_RCC_MCO1SOURCE_IC5              ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_0)
+#define LL_RCC_MCO1SOURCE_IC10             ((RCC_CCIPR5_MCO1SEL<<16U) | RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_1)
+#define LL_RCC_MCO1SOURCE_SYSA             ((RCC_CCIPR5_MCO1SEL<<16U) |\
+                                            RCC_CCIPR5_MCO1SEL_2 | RCC_CCIPR5_MCO1SEL_1 | RCC_CCIPR5_MCO1SEL_0)
+#define LL_RCC_MCO2SOURCE_HSI              ((RCC_CCIPR5_MCO2SEL<<16U) | 0U)
+#define LL_RCC_MCO2SOURCE_LSE              ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_0)
+#define LL_RCC_MCO2SOURCE_MSI              ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_1)
+#define LL_RCC_MCO2SOURCE_LSI              ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_1 | RCC_CCIPR5_MCO2SEL_0)
+#define LL_RCC_MCO2SOURCE_HSE              ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2)
+#define LL_RCC_MCO2SOURCE_IC15             ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_0)
+#define LL_RCC_MCO2SOURCE_IC20             ((RCC_CCIPR5_MCO2SEL<<16U) | RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_1)
+#define LL_RCC_MCO2SOURCE_SYSB             ((RCC_CCIPR5_MCO2SEL<<16U) |\
+                                            RCC_CCIPR5_MCO2SEL_2 | RCC_CCIPR5_MCO2SEL_1 | RCC_CCIPR5_MCO2SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  (RCC_CCIPR5_MCO1PRE<<16U)
+#define LL_RCC_MCO1_DIV_2                  ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_3                  ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_4                  ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_5                  ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_6                  ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_7                  ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_8                  ((RCC_CCIPR5_MCO1PRE<<16U) |\
+                                            RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_9                  ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_10                 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_11                 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_12                 ((RCC_CCIPR5_MCO1PRE<<16U) |\
+                                            RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_1 | RCC_CCIPR5_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_13                 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_14                 ((RCC_CCIPR5_MCO1PRE<<16U) |\
+                                            RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_15                 ((RCC_CCIPR5_MCO1PRE<<16U) |\
+                                            RCC_CCIPR5_MCO1PRE_3 | RCC_CCIPR5_MCO1PRE_2 | RCC_CCIPR5_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_16                 ((RCC_CCIPR5_MCO1PRE<<16U) | RCC_CCIPR5_MCO1PRE)
+#define LL_RCC_MCO2_DIV_1                  (RCC_CCIPR5_MCO2PRE<<16U)
+#define LL_RCC_MCO2_DIV_2                  ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_3                  ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_4                  ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_5                  ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_6                  ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_7                  ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_8                  ((RCC_CCIPR5_MCO2PRE<<16U) |\
+                                            RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_9                  ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_10                 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_11                 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_12                 ((RCC_CCIPR5_MCO2PRE<<16U) |\
+                                            RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_1 | RCC_CCIPR5_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_13                 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_14                 ((RCC_CCIPR5_MCO2PRE<<16U) |\
+                                            RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_15                 ((RCC_CCIPR5_MCO2PRE<<16U) |\
+                                            RCC_CCIPR5_MCO2PRE_3 | RCC_CCIPR5_MCO2PRE_2 | RCC_CCIPR5_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_16                 ((RCC_CCIPR5_MCO2PRE<<16U) | RCC_CCIPR5_MCO2PRE)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSE_DIV  Prescaler for RTC clock
+  * @{
+  */
+#define LL_RCC_RTC_HSE_DIV_1               0U
+#define LL_RCC_RTC_HSE_DIV_2               RCC_CCIPR7_RTCPRE_0
+#define LL_RCC_RTC_HSE_DIV_3               RCC_CCIPR7_RTCPRE_1
+#define LL_RCC_RTC_HSE_DIV_4               (RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_5               RCC_CCIPR7_RTCPRE_2
+#define LL_RCC_RTC_HSE_DIV_6               (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_7               (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_8               (RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_9               RCC_CCIPR7_RTCPRE_3
+#define LL_RCC_RTC_HSE_DIV_10              (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_11              (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_12              (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_13              (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_14              (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_15              (RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_16              (RCC_CCIPR7_RTCPRE_3 |\
+                                            RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_17              RCC_CCIPR7_RTCPRE_4
+#define LL_RCC_RTC_HSE_DIV_18              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_19              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_20              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_21              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_22              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_23              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_24              (RCC_CCIPR7_RTCPRE_4 |\
+                                            RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_25              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_26              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_27              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_28              (RCC_CCIPR7_RTCPRE_4 |\
+                                            RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_29              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_30              (RCC_CCIPR7_RTCPRE_4 |\
+                                            RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_31              (RCC_CCIPR7_RTCPRE_4 |\
+                                            RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_32              (RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 |\
+                                            RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_33              RCC_CCIPR7_RTCPRE_5
+#define LL_RCC_RTC_HSE_DIV_34              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_35              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_36              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_37              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_38              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_39              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_40              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_41              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_42              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_43              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_44              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_45              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_46              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_47              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_48              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2 |\
+                                            RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_49              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4)
+#define LL_RCC_RTC_HSE_DIV_50              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_51              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_52              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_53              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_54              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_55              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_56              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_2 |\
+                                            RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_57              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_58              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_59              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_60              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
+                                            RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_61              (RCC_CCIPR7_RTCPRE_5 |\
+                                            RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 | RCC_CCIPR7_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_62              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
+                                            RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_63              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
+                                            RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_64              (RCC_CCIPR7_RTCPRE_5 | RCC_CCIPR7_RTCPRE_4 | RCC_CCIPR7_RTCPRE_3 |\
+                                            RCC_CCIPR7_RTCPRE_2 | RCC_CCIPR7_RTCPRE_1 | RCC_CCIPR7_RTCPRE_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
+  * @{
+  */
+#define LL_RCC_ADC_CLKSOURCE_HCLK          0U
+#define LL_RCC_ADC_CLKSOURCE_CLKP          RCC_CCIPR1_ADC12SEL_0
+#define LL_RCC_ADC_CLKSOURCE_IC7           RCC_CCIPR1_ADC12SEL_1
+#define LL_RCC_ADC_CLKSOURCE_IC8           (RCC_CCIPR1_ADC12SEL_1 | RCC_CCIPR1_ADC12SEL_0)
+#define LL_RCC_ADC_CLKSOURCE_MSI           RCC_CCIPR1_ADC12SEL_2
+#define LL_RCC_ADC_CLKSOURCE_HSI           (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_0)
+#define LL_RCC_ADC_CLKSOURCE_I2S_CKIN      (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_1)
+#define LL_RCC_ADC_CLKSOURCE_TIMG          (RCC_CCIPR1_ADC12SEL_2 | RCC_CCIPR1_ADC12SEL_1 | RCC_CCIPR1_ADC12SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADF_CLKSOURCE  Peripheral ADF clock source selection
+  * @{
+  */
+#define LL_RCC_ADF1_CLKSOURCE_HCLK         0U
+#define LL_RCC_ADF1_CLKSOURCE_CLKP         RCC_CCIPR1_ADF1SEL_0
+#define LL_RCC_ADF1_CLKSOURCE_IC7          RCC_CCIPR1_ADF1SEL_1
+#define LL_RCC_ADF1_CLKSOURCE_IC8          (RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0)
+#define LL_RCC_ADF1_CLKSOURCE_MSI          RCC_CCIPR1_ADF1SEL_2
+#define LL_RCC_ADF1_CLKSOURCE_HSI          (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_0)
+#define LL_RCC_ADF1_CLKSOURCE_I2S_CKIN     (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_1)
+#define LL_RCC_ADF1_CLKSOURCE_TIMG         (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection
+  * @{
+  */
+#define LL_RCC_CLKP_CLKSOURCE_HSI          0U
+#define LL_RCC_CLKP_CLKSOURCE_MSI          RCC_CCIPR7_PERSEL_0
+#define LL_RCC_CLKP_CLKSOURCE_HSE          RCC_CCIPR7_PERSEL_1
+#define LL_RCC_CLKP_CLKSOURCE_IC19         (RCC_CCIPR7_PERSEL_1 | RCC_CCIPR7_PERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_IC5          RCC_CCIPR7_PERSEL_2
+#define LL_RCC_CLKP_CLKSOURCE_IC10         (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_IC15         (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_1)
+#define LL_RCC_CLKP_CLKSOURCE_IC20         (RCC_CCIPR7_PERSEL_2 | RCC_CCIPR7_PERSEL_1 | RCC_CCIPR7_PERSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DCMIPP_CLKSOURCE  Peripheral DCMIPP clock source selection
+  * @{
+  */
+#define LL_RCC_DCMIPP_CLKSOURCE_PCLK5      0U
+#define LL_RCC_DCMIPP_CLKSOURCE_CLKP       RCC_CCIPR1_DCMIPPSEL_0
+#define LL_RCC_DCMIPP_CLKSOURCE_IC17       RCC_CCIPR1_DCMIPPSEL_1
+#define LL_RCC_DCMIPP_CLKSOURCE_HSI        (RCC_CCIPR1_DCMIPPSEL_1 | RCC_CCIPR1_DCMIPPSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETH_CLKSOURCE  Peripheral ETH kernel clock source selection
+  * @{
+  */
+#define LL_RCC_ETH1_CLKSOURCE_HCLK         0U
+#define LL_RCC_ETH1_CLKSOURCE_CLKP         RCC_CCIPR2_ETH1CLKSEL_0
+#define LL_RCC_ETH1_CLKSOURCE_IC12         RCC_CCIPR2_ETH1CLKSEL_1
+#define LL_RCC_ETH1_CLKSOURCE_HSE          (RCC_CCIPR2_ETH1CLKSEL_1 | RCC_CCIPR2_ETH1CLKSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHPHY_IF  Peripheral ETH PHY interface selection
+  * @{
+  */
+#define LL_RCC_ETH1PHY_IF_MII              0U
+#define LL_RCC_ETH1PHY_IF_RGMII            RCC_CCIPR2_ETH1SEL_0
+#define LL_RCC_ETH1PHY_IF_RMII             RCC_CCIPR2_ETH1SEL_2
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHREFRX_CLKSOURCE  Peripheral ETH Reference RX clock source selection
+  * @{
+  */
+#define LL_RCC_ETH1REFRX_CLKSOURCE_EXT     0U
+#define LL_RCC_ETH1REFRX_CLKSOURCE_INT     RCC_CCIPR2_ETH1REFCLKSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHREFTX_CLKSOURCE  Peripheral ETH Reference TX clock source selection
+  * @{
+  */
+#define LL_RCC_ETH1REFTX_CLKSOURCE_EXT     0U
+#define LL_RCC_ETH1REFTX_CLKSOURCE_INT     RCC_CCIPR2_ETH1GTXCLKSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHPTP_CLKSOURCE  Peripheral ETH PTP kernel clock source selection
+  * @{
+  */
+#define LL_RCC_ETH1PTP_CLKSOURCE_HCLK      0U
+#define LL_RCC_ETH1PTP_CLKSOURCE_CLKP      RCC_CCIPR2_ETH1PTPSEL_0
+#define LL_RCC_ETH1PTP_CLKSOURCE_IC13      RCC_CCIPR2_ETH1PTPSEL_1
+#define LL_RCC_ETH1PTP_CLKSOURCE_HSE       (RCC_CCIPR2_ETH1PTPSEL_1 | RCC_CCIPR2_ETH1PTPSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETH1PTP_DIV  ETH1 PTP kernel clock divider selection
+  * @{
+  */
+#define LL_RCC_ETH1PTP_DIV_1               0U
+#define LL_RCC_ETH1PTP_DIV_2               RCC_CCIPR2_ETH1PTPDIV_0
+#define LL_RCC_ETH1PTP_DIV_3               RCC_CCIPR2_ETH1PTPDIV_1
+#define LL_RCC_ETH1PTP_DIV_4               (RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
+#define LL_RCC_ETH1PTP_DIV_5               RCC_CCIPR2_ETH1PTPDIV_2
+#define LL_RCC_ETH1PTP_DIV_6               (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_0)
+#define LL_RCC_ETH1PTP_DIV_7               (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1)
+#define LL_RCC_ETH1PTP_DIV_8               (RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
+#define LL_RCC_ETH1PTP_DIV_9               RCC_CCIPR2_ETH1PTPDIV_3
+#define LL_RCC_ETH1PTP_DIV_10              (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_0)
+#define LL_RCC_ETH1PTP_DIV_11              (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_1)
+#define LL_RCC_ETH1PTP_DIV_12              (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
+#define LL_RCC_ETH1PTP_DIV_13              (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2)
+#define LL_RCC_ETH1PTP_DIV_14              (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_0)
+#define LL_RCC_ETH1PTP_DIV_15              (RCC_CCIPR2_ETH1PTPDIV_3 | RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1)
+#define LL_RCC_ETH1PTP_DIV_16              (RCC_CCIPR2_ETH1PTPDIV_3 |\
+                                            RCC_CCIPR2_ETH1PTPDIV_2 | RCC_CCIPR2_ETH1PTPDIV_1 | RCC_CCIPR2_ETH1PTPDIV_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
+  * @{
+  */
+#define LL_RCC_FDCAN_CLKSOURCE_PCLK1       0U
+#define LL_RCC_FDCAN_CLKSOURCE_CLKP        RCC_CCIPR3_FDCANSEL_0
+#define LL_RCC_FDCAN_CLKSOURCE_IC19        RCC_CCIPR3_FDCANSEL_1
+#define LL_RCC_FDCAN_CLKSOURCE_HSE         (RCC_CCIPR3_FDCANSEL_1 | RCC_CCIPR3_FDCANSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
+  * @{
+  */
+#define LL_RCC_FMC_CLKSOURCE_HCLK          0U
+#define LL_RCC_FMC_CLKSOURCE_CLKP          RCC_CCIPR3_FMCSEL_0
+#define LL_RCC_FMC_CLKSOURCE_IC3           RCC_CCIPR3_FMCSEL_1
+#define LL_RCC_FMC_CLKSOURCE_IC4           (RCC_CCIPR3_FMCSEL_1 | RCC_CCIPR3_FMCSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2C_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0U)
+#define LL_RCC_I2C1_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
+                                                        RCC_CCIPR4_I2C1SEL_0)
+#define LL_RCC_I2C1_CLKSOURCE_IC10         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
+                                                        RCC_CCIPR4_I2C1SEL_1)
+#define LL_RCC_I2C1_CLKSOURCE_IC15         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
+                                                        RCC_CCIPR4_I2C1SEL_1 | RCC_CCIPR4_I2C1SEL_0)
+#define LL_RCC_I2C1_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
+                                                        RCC_CCIPR4_I2C1SEL_2)
+#define LL_RCC_I2C1_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos,\
+                                                        RCC_CCIPR4_I2C1SEL_2| RCC_CCIPR4_I2C1SEL_0)
+
+#define LL_RCC_I2C2_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0U)
+#define LL_RCC_I2C2_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
+                                                        RCC_CCIPR4_I2C2SEL_0)
+#define LL_RCC_I2C2_CLKSOURCE_IC10         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
+                                                        RCC_CCIPR4_I2C2SEL_1)
+#define LL_RCC_I2C2_CLKSOURCE_IC15         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
+                                                        RCC_CCIPR4_I2C2SEL_1 | RCC_CCIPR4_I2C2SEL_0)
+#define LL_RCC_I2C2_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
+                                                        RCC_CCIPR4_I2C2SEL_2)
+#define LL_RCC_I2C2_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\
+                                                        RCC_CCIPR4_I2C2SEL_2 | RCC_CCIPR4_I2C2SEL_0)
+
+#define LL_RCC_I2C3_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0U)
+#define LL_RCC_I2C3_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
+                                                        RCC_CCIPR4_I2C3SEL_0)
+#define LL_RCC_I2C3_CLKSOURCE_IC10         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
+                                                        RCC_CCIPR4_I2C3SEL_1)
+#define LL_RCC_I2C3_CLKSOURCE_IC15         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
+                                                        RCC_CCIPR4_I2C3SEL_1 | RCC_CCIPR4_I2C3SEL_0)
+#define LL_RCC_I2C3_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
+                                                        RCC_CCIPR4_I2C3SEL_2)
+#define LL_RCC_I2C3_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\
+                                                        RCC_CCIPR4_I2C3SEL_2| RCC_CCIPR4_I2C3SEL_0)
+
+#define LL_RCC_I2C4_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0U)
+#define LL_RCC_I2C4_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
+                                                        RCC_CCIPR4_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_IC10         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
+                                                        RCC_CCIPR4_I2C4SEL_1)
+#define LL_RCC_I2C4_CLKSOURCE_IC15         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
+                                                        RCC_CCIPR4_I2C4SEL_1 | RCC_CCIPR4_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
+                                                        RCC_CCIPR4_I2C4SEL_2)
+#define LL_RCC_I2C4_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\
+                                                        RCC_CCIPR4_I2C4SEL_2| RCC_CCIPR4_I2C4SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I3C_CLKSOURCE  Peripheral I3C clock source selection
+  * @{
+  */
+#define LL_RCC_I3C1_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U)
+#define LL_RCC_I3C1_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
+                                                        RCC_CCIPR4_I3C1SEL_0)
+#define LL_RCC_I3C1_CLKSOURCE_IC10         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
+                                                        RCC_CCIPR4_I3C1SEL_1)
+#define LL_RCC_I3C1_CLKSOURCE_IC15         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
+                                                        RCC_CCIPR4_I3C1SEL_1 | RCC_CCIPR4_I3C1SEL_0)
+#define LL_RCC_I3C1_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
+                                                        RCC_CCIPR4_I3C1SEL_2)
+#define LL_RCC_I3C1_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
+                                                        RCC_CCIPR4_I3C1SEL_2| RCC_CCIPR4_I3C1SEL_0)
+
+#define LL_RCC_I3C2_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0U)
+#define LL_RCC_I3C2_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
+                                                        RCC_CCIPR4_I3C2SEL_0)
+#define LL_RCC_I3C2_CLKSOURCE_IC10         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
+                                                        RCC_CCIPR4_I3C2SEL_1)
+#define LL_RCC_I3C2_CLKSOURCE_IC15         LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
+                                                        RCC_CCIPR4_I3C2SEL_1 | RCC_CCIPR4_I3C2SEL_0)
+#define LL_RCC_I3C2_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
+                                                        RCC_CCIPR4_I3C2SEL_2)
+#define LL_RCC_I3C2_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\
+                                                        RCC_CCIPR4_I3C2SEL_2 | RCC_CCIPR4_I3C2SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL,  RCC_CCIPR12_LPTIM1SEL_Pos,  0U)
+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL,  RCC_CCIPR12_LPTIM1SEL_Pos,  RCC_CCIPR12_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_IC15       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL,  RCC_CCIPR12_LPTIM1SEL_Pos,  RCC_CCIPR12_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL,  RCC_CCIPR12_LPTIM1SEL_Pos,  RCC_CCIPR12_LPTIM1SEL_1 |\
+                                                        RCC_CCIPR12_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL,  RCC_CCIPR12_LPTIM1SEL_Pos,  RCC_CCIPR12_LPTIM1SEL_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_TIMG       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL,  RCC_CCIPR12_LPTIM1SEL_Pos,  RCC_CCIPR12_LPTIM1SEL_2 |\
+                                                        RCC_CCIPR12_LPTIM1SEL_0)
+
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4      LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL,  RCC_CCIPR12_LPTIM2SEL_Pos,  0U)
+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL,  RCC_CCIPR12_LPTIM2SEL_Pos,  RCC_CCIPR12_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_IC15       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL,  RCC_CCIPR12_LPTIM2SEL_Pos,  RCC_CCIPR12_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL,  RCC_CCIPR12_LPTIM2SEL_Pos,  RCC_CCIPR12_LPTIM2SEL_1 |\
+                                                        RCC_CCIPR12_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL,  RCC_CCIPR12_LPTIM2SEL_Pos,  RCC_CCIPR12_LPTIM2SEL_2)
+#define LL_RCC_LPTIM2_CLKSOURCE_TIMG       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL,  RCC_CCIPR12_LPTIM2SEL_Pos,  RCC_CCIPR12_LPTIM2SEL_2 |\
+                                                        RCC_CCIPR12_LPTIM2SEL_0)
+
+#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4      LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL,  RCC_CCIPR12_LPTIM3SEL_Pos,  0U)
+#define LL_RCC_LPTIM3_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL,  RCC_CCIPR12_LPTIM3SEL_Pos,  RCC_CCIPR12_LPTIM3SEL_0)
+#define LL_RCC_LPTIM3_CLKSOURCE_IC15       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL,  RCC_CCIPR12_LPTIM3SEL_Pos,  RCC_CCIPR12_LPTIM3SEL_1)
+#define LL_RCC_LPTIM3_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL,  RCC_CCIPR12_LPTIM3SEL_Pos,  RCC_CCIPR12_LPTIM3SEL_1 |\
+                                                        RCC_CCIPR12_LPTIM3SEL_0)
+#define LL_RCC_LPTIM3_CLKSOURCE_LSI        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL,  RCC_CCIPR12_LPTIM3SEL_Pos,  RCC_CCIPR12_LPTIM3SEL_2)
+#define LL_RCC_LPTIM3_CLKSOURCE_TIMG       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL,  RCC_CCIPR12_LPTIM3SEL_Pos,  RCC_CCIPR12_LPTIM3SEL_2 |\
+                                                        RCC_CCIPR12_LPTIM3SEL_0)
+
+#define LL_RCC_LPTIM4_CLKSOURCE_PCLK4      LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL,  RCC_CCIPR12_LPTIM4SEL_Pos,  0U)
+#define LL_RCC_LPTIM4_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL,  RCC_CCIPR12_LPTIM4SEL_Pos,  RCC_CCIPR12_LPTIM4SEL_0)
+#define LL_RCC_LPTIM4_CLKSOURCE_IC15       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL,  RCC_CCIPR12_LPTIM4SEL_Pos,  RCC_CCIPR12_LPTIM4SEL_1)
+#define LL_RCC_LPTIM4_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL,  RCC_CCIPR12_LPTIM4SEL_Pos,  RCC_CCIPR12_LPTIM4SEL_1 |\
+                                                        RCC_CCIPR12_LPTIM4SEL_0)
+#define LL_RCC_LPTIM4_CLKSOURCE_LSI        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL,  RCC_CCIPR12_LPTIM4SEL_Pos,  RCC_CCIPR12_LPTIM4SEL_2)
+#define LL_RCC_LPTIM4_CLKSOURCE_TIMG       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL,  RCC_CCIPR12_LPTIM4SEL_Pos,  RCC_CCIPR12_LPTIM4SEL_2 |\
+                                                        RCC_CCIPR12_LPTIM4SEL_0)
+
+#define LL_RCC_LPTIM5_CLKSOURCE_PCLK4      LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL,  RCC_CCIPR12_LPTIM5SEL_Pos,  0U)
+#define LL_RCC_LPTIM5_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL,  RCC_CCIPR12_LPTIM5SEL_Pos,  RCC_CCIPR12_LPTIM5SEL_0)
+#define LL_RCC_LPTIM5_CLKSOURCE_IC15       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL,  RCC_CCIPR12_LPTIM5SEL_Pos,  RCC_CCIPR12_LPTIM5SEL_1)
+#define LL_RCC_LPTIM5_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL,  RCC_CCIPR12_LPTIM5SEL_Pos,  RCC_CCIPR12_LPTIM5SEL_1 |\
+                                                        RCC_CCIPR12_LPTIM5SEL_0)
+#define LL_RCC_LPTIM5_CLKSOURCE_LSI        LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL,  RCC_CCIPR12_LPTIM5SEL_Pos,  RCC_CCIPR12_LPTIM5SEL_2)
+#define LL_RCC_LPTIM5_CLKSOURCE_TIMG       LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL,  RCC_CCIPR12_LPTIM5SEL_Pos,  RCC_CCIPR12_LPTIM5SEL_2 |\
+                                                        RCC_CCIPR12_LPTIM5SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE  Peripheral LPUART clock source selection
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4     0U
+#define LL_RCC_LPUART1_CLKSOURCE_CLKP      RCC_CCIPR14_LPUART1SEL_0
+#define LL_RCC_LPUART1_CLKSOURCE_IC9       RCC_CCIPR14_LPUART1SEL_1
+#define LL_RCC_LPUART1_CLKSOURCE_IC14      (RCC_CCIPR14_LPUART1SEL_1 | RCC_CCIPR14_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR14_LPUART1SEL_2
+#define LL_RCC_LPUART1_CLKSOURCE_MSI       (RCC_CCIPR14_LPUART1SEL_2 | RCC_CCIPR14_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_HSI       (RCC_CCIPR14_LPUART1SEL_2 | RCC_CCIPR14_LPUART1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE  Peripheral LTDC clock source selection
+  * @{
+  */
+#define LL_RCC_LTDC_CLKSOURCE_PCLK5        0U
+#define LL_RCC_LTDC_CLKSOURCE_CLKP         RCC_CCIPR4_LTDCSEL_0
+#define LL_RCC_LTDC_CLKSOURCE_IC16         RCC_CCIPR4_LTDCSEL_1
+#define LL_RCC_LTDC_CLKSOURCE_HSI          (RCC_CCIPR4_LTDCSEL_1 | RCC_CCIPR4_LTDCSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MDF_CLKSOURCE  Peripheral MDF clock source selection
+  * @{
+  */
+#define LL_RCC_MDF1_CLKSOURCE_HCLK         0U
+#define LL_RCC_MDF1_CLKSOURCE_CLKP         RCC_CCIPR5_MDF1SEL_0
+#define LL_RCC_MDF1_CLKSOURCE_IC7          RCC_CCIPR5_MDF1SEL_1
+#define LL_RCC_MDF1_CLKSOURCE_IC8          (RCC_CCIPR5_MDF1SEL_1 | RCC_CCIPR5_MDF1SEL_0)
+#define LL_RCC_MDF1_CLKSOURCE_MSI          RCC_CCIPR5_MDF1SEL_2
+#define LL_RCC_MDF1_CLKSOURCE_HSI          (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_0)
+#define LL_RCC_MDF1_CLKSOURCE_I2S_CKIN     (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_1)
+#define LL_RCC_MDF1_CLKSOURCE_TIMG         (RCC_CCIPR5_MDF1SEL_2 | RCC_CCIPR5_MDF1SEL_1 | RCC_CCIPR5_MDF1SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_OTGPHY_CLKSOURCE  Peripheral OTGPHY clock source selection
+  * @{
+  */
+#define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2     LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0U)
+#define LL_RCC_OTGPHY1_CLKSOURCE_CLKP          LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_0)
+#define LL_RCC_OTGPHY1_CLKSOURCE_IC15          LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1)
+#define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1 |\
+                                                            RCC_CCIPR6_OTGPHY1SEL_0)
+
+#define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2     LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0U)
+#define LL_RCC_OTGPHY2_CLKSOURCE_CLKP          LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_0)
+#define LL_RCC_OTGPHY2_CLKSOURCE_IC15          LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1)
+#define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1 |\
+                                                            RCC_CCIPR6_OTGPHY2SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_OTGPHYCKREF_CLKSOURCE  Peripheral OTGPHYCKREF clock source selection
+  * @{
+  */
+#define LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1       LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0U)
+#define LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, RCC_CCIPR6_OTGPHY1CKREFSEL)
+
+#define LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2       LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0U)
+#define LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, RCC_CCIPR6_OTGPHY2CKREFSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PSSI_CLKSOURCE  Peripheral PSSI clock source selection
+  * @{
+  */
+#define LL_RCC_PSSI_CLKSOURCE_HCLK         0U
+#define LL_RCC_PSSI_CLKSOURCE_CLKP         RCC_CCIPR7_PSSISEL_0
+#define LL_RCC_PSSI_CLKSOURCE_IC20         RCC_CCIPR7_PSSISEL_1
+#define LL_RCC_PSSI_CLKSOURCE_HSI          (RCC_CCIPR7_PSSISEL_1 | RCC_CCIPR7_PSSISEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0U
+#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_CCIPR7_RTCSEL_0
+#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_CCIPR7_RTCSEL_1
+#define LL_RCC_RTC_CLKSOURCE_HSE           (RCC_CCIPR7_RTCSEL_1 | RCC_CCIPR7_RTCSEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAI_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE_PCLK2        LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0U)
+#define LL_RCC_SAI1_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_IC7          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_IC8          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1 |\
+                                                        RCC_CCIPR7_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2)
+#define LL_RCC_SAI1_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\
+                                                        RCC_CCIPR7_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN     LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\
+                                                        RCC_CCIPR7_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_SPDIFRX1     LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\
+                                                        RCC_CCIPR7_SAI1SEL_1 | RCC_CCIPR7_SAI1SEL_0)
+
+#define LL_RCC_SAI2_CLKSOURCE_PCLK2        LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0U)
+#define LL_RCC_SAI2_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_0)
+#define LL_RCC_SAI2_CLKSOURCE_IC7          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1)
+#define LL_RCC_SAI2_CLKSOURCE_IC8          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1 |\
+                                                        RCC_CCIPR7_SAI2SEL_0)
+#define LL_RCC_SAI2_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2)
+#define LL_RCC_SAI2_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\
+                                                        RCC_CCIPR7_SAI2SEL_0)
+#define LL_RCC_SAI2_CLKSOURCE_I2S_CKIN     LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\
+                                                        RCC_CCIPR7_SAI2SEL_1)
+#define LL_RCC_SAI2_CLKSOURCE_SPDIFRX1     LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_2 |\
+                                                        RCC_CCIPR7_SAI2SEL_1 | RCC_CCIPR7_SAI2SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection
+  * @{
+  */
+#define LL_RCC_SDMMC1_CLKSOURCE_HCLK       LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0U)
+#define LL_RCC_SDMMC1_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_0)
+#define LL_RCC_SDMMC1_CLKSOURCE_IC4        LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1)
+#define LL_RCC_SDMMC1_CLKSOURCE_IC5        LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1 |\
+                                                        RCC_CCIPR8_SDMMC1SEL_0)
+
+#define LL_RCC_SDMMC2_CLKSOURCE_HCLK       LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0U)
+#define LL_RCC_SDMMC2_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_0)
+#define LL_RCC_SDMMC2_CLKSOURCE_IC4        LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1)
+#define LL_RCC_SDMMC2_CLKSOURCE_IC5        LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1 |\
+                                                        RCC_CCIPR8_SDMMC2SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection
+  * @{
+  */
+#define LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1    0U
+#define LL_RCC_SPDIFRX1_CLKSOURCE_CLKP     RCC_CCIPR9_SPDIFRX1SEL_0
+#define LL_RCC_SPDIFRX1_CLKSOURCE_IC7      RCC_CCIPR9_SPDIFRX1SEL_1
+#define LL_RCC_SPDIFRX1_CLKSOURCE_IC8      (RCC_CCIPR9_SPDIFRX1SEL_1 | RCC_CCIPR9_SPDIFRX1SEL_0)
+#define LL_RCC_SPDIFRX1_CLKSOURCE_MSI      RCC_CCIPR9_SPDIFRX1SEL_2
+#define LL_RCC_SPDIFRX1_CLKSOURCE_HSI      (RCC_CCIPR9_SPDIFRX1SEL_2 | RCC_CCIPR9_SPDIFRX1SEL_0)
+#define LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN (RCC_CCIPR9_SPDIFRX1SEL_2 | RCC_CCIPR9_SPDIFRX1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPI_CLKSOURCE  Peripheral SPI clock source selection
+  * @{
+  */
+#define LL_RCC_SPI1_CLKSOURCE_PCLK2        LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0U)
+#define LL_RCC_SPI1_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_0)
+#define LL_RCC_SPI1_CLKSOURCE_IC8          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1)
+#define LL_RCC_SPI1_CLKSOURCE_IC9          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1 |\
+                                                        RCC_CCIPR9_SPI1SEL_0)
+#define LL_RCC_SPI1_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2)
+#define LL_RCC_SPI1_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2 |\
+                                                        RCC_CCIPR9_SPI1SEL_0)
+#define LL_RCC_SPI1_CLKSOURCE_I2S_CKIN     LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2 |\
+                                                        RCC_CCIPR9_SPI1SEL_1)
+
+#define LL_RCC_SPI2_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0U)
+#define LL_RCC_SPI2_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_0)
+#define LL_RCC_SPI2_CLKSOURCE_IC8          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1)
+#define LL_RCC_SPI2_CLKSOURCE_IC9          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1 |\
+                                                        RCC_CCIPR9_SPI2SEL_0)
+#define LL_RCC_SPI2_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2)
+#define LL_RCC_SPI2_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2 |\
+                                                        RCC_CCIPR9_SPI2SEL_0)
+#define LL_RCC_SPI2_CLKSOURCE_I2S_CKIN     LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2 |\
+                                                        RCC_CCIPR9_SPI2SEL_1)
+
+#define LL_RCC_SPI3_CLKSOURCE_PCLK1        LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0U)
+#define LL_RCC_SPI3_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_0)
+#define LL_RCC_SPI3_CLKSOURCE_IC8          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1)
+#define LL_RCC_SPI3_CLKSOURCE_IC9          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1 |\
+                                                        RCC_CCIPR9_SPI3SEL_0)
+#define LL_RCC_SPI3_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2)
+#define LL_RCC_SPI3_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2 |\
+                                                        RCC_CCIPR9_SPI3SEL_0)
+#define LL_RCC_SPI3_CLKSOURCE_I2S_CKIN     LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2 |\
+                                                        RCC_CCIPR9_SPI3SEL_1)
+
+#define LL_RCC_SPI4_CLKSOURCE_PCLK2        LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0U)
+#define LL_RCC_SPI4_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_0)
+#define LL_RCC_SPI4_CLKSOURCE_IC9          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1)
+#define LL_RCC_SPI4_CLKSOURCE_IC14         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1 |\
+                                                        RCC_CCIPR9_SPI4SEL_0)
+#define LL_RCC_SPI4_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2)
+#define LL_RCC_SPI4_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2 |\
+                                                        RCC_CCIPR9_SPI4SEL_0)
+#define LL_RCC_SPI4_CLKSOURCE_HSE          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2 |\
+                                                        RCC_CCIPR9_SPI4SEL_1)
+
+#define LL_RCC_SPI5_CLKSOURCE_PCLK2        LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0U)
+#define LL_RCC_SPI5_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_0)
+#define LL_RCC_SPI5_CLKSOURCE_IC9          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1)
+#define LL_RCC_SPI5_CLKSOURCE_IC14         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1 |\
+                                                        RCC_CCIPR9_SPI5SEL_0)
+#define LL_RCC_SPI5_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2)
+#define LL_RCC_SPI5_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2 |\
+                                                        RCC_CCIPR9_SPI5SEL_0)
+#define LL_RCC_SPI5_CLKSOURCE_HSE          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2 |\
+                                                        RCC_CCIPR9_SPI5SEL_1)
+
+#define LL_RCC_SPI6_CLKSOURCE_PCLK4        LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0U)
+#define LL_RCC_SPI6_CLKSOURCE_CLKP         LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_IC8          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_IC9          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1 |\
+                                                        RCC_CCIPR9_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_MSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_HSI          LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2 |\
+                                                        RCC_CCIPR9_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN     LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_2 |\
+                                                        RCC_CCIPR9_SPI6SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_UART_CLKSOURCE  Peripheral UART clock source selection
+  * @{
+  */
+#define LL_RCC_UART4_CLKSOURCE_PCLK1       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0U)
+#define LL_RCC_UART4_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_0)
+#define LL_RCC_UART4_CLKSOURCE_IC9         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1)
+#define LL_RCC_UART4_CLKSOURCE_IC14        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1 |\
+                                                        RCC_CCIPR13_UART4SEL_0)
+#define LL_RCC_UART4_CLKSOURCE_LSE         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2)
+#define LL_RCC_UART4_CLKSOURCE_MSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2 |\
+                                                        RCC_CCIPR13_UART4SEL_0)
+#define LL_RCC_UART4_CLKSOURCE_HSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2 |\
+                                                        RCC_CCIPR13_UART4SEL_1)
+
+#define LL_RCC_UART5_CLKSOURCE_PCLK1       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0U)
+#define LL_RCC_UART5_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_0)
+#define LL_RCC_UART5_CLKSOURCE_IC9         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1)
+#define LL_RCC_UART5_CLKSOURCE_IC14        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1 |\
+                                                        RCC_CCIPR13_UART5SEL_0)
+#define LL_RCC_UART5_CLKSOURCE_LSE         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2)
+#define LL_RCC_UART5_CLKSOURCE_MSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2 |\
+                                                        RCC_CCIPR13_UART5SEL_0)
+#define LL_RCC_UART5_CLKSOURCE_HSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2 |\
+                                                        RCC_CCIPR13_UART5SEL_1)
+
+#define LL_RCC_UART7_CLKSOURCE_PCLK1       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0U)
+#define LL_RCC_UART7_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_0)
+#define LL_RCC_UART7_CLKSOURCE_IC9         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1)
+#define LL_RCC_UART7_CLKSOURCE_IC14        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1 |\
+                                                        RCC_CCIPR13_UART7SEL_0)
+#define LL_RCC_UART7_CLKSOURCE_LSE         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2)
+#define LL_RCC_UART7_CLKSOURCE_MSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2 |\
+                                                        RCC_CCIPR13_UART7SEL_0)
+#define LL_RCC_UART7_CLKSOURCE_HSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2 |\
+                                                        RCC_CCIPR13_UART7SEL_1)
+
+#define LL_RCC_UART8_CLKSOURCE_PCLK1       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0U)
+#define LL_RCC_UART8_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_0)
+#define LL_RCC_UART8_CLKSOURCE_IC9         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1)
+#define LL_RCC_UART8_CLKSOURCE_IC14        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1 |\
+                                                        RCC_CCIPR13_UART8SEL_0)
+#define LL_RCC_UART8_CLKSOURCE_LSE         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2)
+#define LL_RCC_UART8_CLKSOURCE_MSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2 |\
+                                                        RCC_CCIPR13_UART8SEL_0)
+#define LL_RCC_UART8_CLKSOURCE_HSI         LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2 |\
+                                                        RCC_CCIPR13_UART8SEL_1)
+
+#define LL_RCC_UART9_CLKSOURCE_PCLK2       LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0U)
+#define LL_RCC_UART9_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_0)
+#define LL_RCC_UART9_CLKSOURCE_IC9         LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1)
+#define LL_RCC_UART9_CLKSOURCE_IC14        LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1 |\
+                                                        RCC_CCIPR14_UART9SEL_0)
+#define LL_RCC_UART9_CLKSOURCE_LSE         LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2)
+#define LL_RCC_UART9_CLKSOURCE_MSI         LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2 |\
+                                                        RCC_CCIPR14_UART9SEL_0)
+#define LL_RCC_UART9_CLKSOURCE_HSI         LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_2 |\
+                                                        RCC_CCIPR14_UART9SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USART_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE_PCLK2      LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0U)
+#define LL_RCC_USART1_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_0)
+#define LL_RCC_USART1_CLKSOURCE_IC9        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1)
+#define LL_RCC_USART1_CLKSOURCE_IC14       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1 |\
+                                                        RCC_CCIPR13_USART1SEL_0)
+#define LL_RCC_USART1_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2)
+#define LL_RCC_USART1_CLKSOURCE_MSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2 |\
+                                                        RCC_CCIPR13_USART1SEL_0)
+#define LL_RCC_USART1_CLKSOURCE_HSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2 |\
+                                                        RCC_CCIPR13_USART1SEL_1)
+
+#define LL_RCC_USART2_CLKSOURCE_PCLK1      LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0U)
+#define LL_RCC_USART2_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_0)
+#define LL_RCC_USART2_CLKSOURCE_IC9        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1)
+#define LL_RCC_USART2_CLKSOURCE_IC14       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1 |\
+                                                        RCC_CCIPR13_USART2SEL_0)
+#define LL_RCC_USART2_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2)
+#define LL_RCC_USART2_CLKSOURCE_MSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2 |\
+                                                        RCC_CCIPR13_USART2SEL_0)
+#define LL_RCC_USART2_CLKSOURCE_HSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2 |\
+                                                        RCC_CCIPR13_USART2SEL_1)
+
+#define LL_RCC_USART3_CLKSOURCE_PCLK1      LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0U)
+#define LL_RCC_USART3_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_0)
+#define LL_RCC_USART3_CLKSOURCE_IC9        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1)
+#define LL_RCC_USART3_CLKSOURCE_IC14       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1 |\
+                                                        RCC_CCIPR13_USART3SEL_0)
+#define LL_RCC_USART3_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2)
+#define LL_RCC_USART3_CLKSOURCE_MSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2 |\
+                                                        RCC_CCIPR13_USART3SEL_0)
+#define LL_RCC_USART3_CLKSOURCE_HSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2 |\
+                                                        RCC_CCIPR13_USART3SEL_1)
+
+#define LL_RCC_USART6_CLKSOURCE_PCLK2      LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0U)
+#define LL_RCC_USART6_CLKSOURCE_CLKP       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_0)
+#define LL_RCC_USART6_CLKSOURCE_IC9        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1)
+#define LL_RCC_USART6_CLKSOURCE_IC14       LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1 |\
+                                                        RCC_CCIPR13_USART6SEL_0)
+#define LL_RCC_USART6_CLKSOURCE_LSE        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2)
+#define LL_RCC_USART6_CLKSOURCE_MSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2 |\
+                                                        RCC_CCIPR13_USART6SEL_0)
+#define LL_RCC_USART6_CLKSOURCE_HSI        LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2 |\
+                                                        RCC_CCIPR13_USART6SEL_1)
+
+#define LL_RCC_USART10_CLKSOURCE_PCLK2     LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0U)
+#define LL_RCC_USART10_CLKSOURCE_CLKP      LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_0)
+#define LL_RCC_USART10_CLKSOURCE_IC9       LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1)
+#define LL_RCC_USART10_CLKSOURCE_IC14      LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1 |\
+                                                        RCC_CCIPR14_USART10SEL_0)
+#define LL_RCC_USART10_CLKSOURCE_LSE       LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2)
+#define LL_RCC_USART10_CLKSOURCE_MSI       LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2 |\
+                                                        RCC_CCIPR14_USART10SEL_0)
+#define LL_RCC_USART10_CLKSOURCE_HSI       LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_2 |\
+                                                        RCC_CCIPR14_USART10SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_XSPI_CLKSOURCE  Peripheral XSPI clock source selection
+  * @{
+  */
+#define LL_RCC_XSPI1_CLKSOURCE_HCLK        LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0U)
+#define LL_RCC_XSPI1_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_0)
+#define LL_RCC_XSPI1_CLKSOURCE_IC3         LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1)
+#define LL_RCC_XSPI1_CLKSOURCE_IC4         LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1 |\
+                                                        RCC_CCIPR6_XSPI1SEL_0)
+
+#define LL_RCC_XSPI2_CLKSOURCE_HCLK        LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0U)
+#define LL_RCC_XSPI2_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_0)
+#define LL_RCC_XSPI2_CLKSOURCE_IC3         LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1)
+#define LL_RCC_XSPI2_CLKSOURCE_IC4         LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1 |\
+                                                        RCC_CCIPR6_XSPI2SEL_0)
+
+#define LL_RCC_XSPI3_CLKSOURCE_HCLK        LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0U)
+#define LL_RCC_XSPI3_CLKSOURCE_CLKP        LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_0)
+#define LL_RCC_XSPI3_CLKSOURCE_IC3         LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1)
+#define LL_RCC_XSPI3_CLKSOURCE_IC4         LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1 |\
+                                                        RCC_CCIPR6_XSPI3SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
+  * @{
+  */
+#define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR1_ADC12SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADF  Peripheral ADF get clock source
+  * @{
+  */
+#define LL_RCC_ADF1_CLKSOURCE              RCC_CCIPR1_ADF1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLKP  Peripheral CLKP get clock source
+  * @{
+  */
+#define LL_RCC_CLKP_CLKSOURCE              RCC_CCIPR7_PERSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DCMIPP  Peripheral DCMIPP get clock source
+  * @{
+  */
+#define LL_RCC_DCMIPP_CLKSOURCE             RCC_CCIPR1_DCMIPPSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETH  Peripheral ETH get clock source
+  * @{
+  */
+#define LL_RCC_ETH1_CLKSOURCE              RCC_CCIPR2_ETH1CLKSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHPHY  Peripheral ETH PHY get interface
+  * @{
+  */
+#define LL_RCC_ETH1PHY_IF                  RCC_CCIPR2_ETH1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHPTP  Peripheral ETHPTP get clock source
+  * @{
+  */
+#define LL_RCC_ETH1PTP_CLKSOURCE           RCC_CCIPR2_ETH1PTPSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHREFRX  Peripheral ETH Reference RX get clock source
+  * @{
+  */
+#define LL_RCC_ETH1REFRX_CLKSOURCE         RCC_CCIPR2_ETH1REFCLKSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ETHREFTX  Peripheral ETH Reference TX get clock source
+  * @{
+  */
+#define LL_RCC_ETH1REFTX_CLKSOURCE         RCC_CCIPR2_ETH1GTXCLKSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_FDCAN  Peripheral FDCAN get clock source
+  * @{
+  */
+#define LL_RCC_FDCAN_CLKSOURCE             RCC_CCIPR3_FDCANSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_FMC  Peripheral FMC get clock source
+  * @{
+  */
+#define LL_RCC_FMC_CLKSOURCE               RCC_CCIPR3_FMCSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2C  Peripheral I2C get clock source
+  * @{
+  */
+#define LL_RCC_I2C1_CLKSOURCE              LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0U)
+#define LL_RCC_I2C2_CLKSOURCE              LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0U)
+#define LL_RCC_I2C3_CLKSOURCE              LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0U)
+#define LL_RCC_I2C4_CLKSOURCE              LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I3C  Peripheral I3C get clock source
+  * @{
+  */
+#define LL_RCC_I3C1_CLKSOURCE              LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U)
+#define LL_RCC_I3C2_CLKSOURCE              LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIM  Peripheral LPTIM get clock source
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE            LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0U)
+#define LL_RCC_LPTIM2_CLKSOURCE            LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0U)
+#define LL_RCC_LPTIM3_CLKSOURCE            LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0U)
+#define LL_RCC_LPTIM4_CLKSOURCE            LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0U)
+#define LL_RCC_LPTIM5_CLKSOURCE            LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUART  Peripheral LPUART get clock source
+  * @{
+  */
+#define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR14_LPUART1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source
+  * @{
+  */
+#define LL_RCC_LTDC_CLKSOURCE              RCC_CCIPR4_LTDCSEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MDF  Peripheral MDF get clock source
+  * @{
+  */
+#define LL_RCC_MDF1_CLKSOURCE              RCC_CCIPR5_MDF1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_OTGPHY  Peripheral OTGPHY get clock source
+  * @{
+  */
+#define LL_RCC_OTGPHY1_CLKSOURCE           LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0U)
+#define LL_RCC_OTGPHY2_CLKSOURCE           LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_OTGPHYCKREF  Peripheral OTGPHYCKREF get clock source
+  * @{
+  */
+#define LL_RCC_OTGPHY1CKREF_CLKSOURCE      LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0U)
+#define LL_RCC_OTGPHY2CKREF_CLKSOURCE      LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PSSI  Peripheral PSSI get clock source
+  * @{
+  */
+#define LL_RCC_PSSI_CLKSOURCE              RCC_CCIPR7_PSSISEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAI  Peripheral SAI get clock source
+  * @{
+  */
+#define LL_RCC_SAI1_CLKSOURCE              LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0U)
+#define LL_RCC_SAI2_CLKSOURCE              LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC  Peripheral SDMMC get clock source
+  * @{
+  */
+#define LL_RCC_SDMMC1_CLKSOURCE            LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0U)
+#define LL_RCC_SDMMC2_CLKSOURCE            LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
+  * @{
+  */
+#define LL_RCC_SPDIFRX1_CLKSOURCE          RCC_CCIPR9_SPDIFRX1SEL
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPI  Peripheral SPI get clock source
+  * @{
+  */
+#define LL_RCC_SPI1_CLKSOURCE              LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0U)
+#define LL_RCC_SPI2_CLKSOURCE              LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0U)
+#define LL_RCC_SPI3_CLKSOURCE              LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0U)
+#define LL_RCC_SPI4_CLKSOURCE              LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0U)
+#define LL_RCC_SPI5_CLKSOURCE              LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0U)
+#define LL_RCC_SPI6_CLKSOURCE              LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_UART  Peripheral UART get clock source
+  * @{
+  */
+#define LL_RCC_UART4_CLKSOURCE             LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0U)
+#define LL_RCC_UART5_CLKSOURCE             LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0U)
+#define LL_RCC_UART7_CLKSOURCE             LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0U)
+#define LL_RCC_UART8_CLKSOURCE             LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0U)
+#define LL_RCC_UART9_CLKSOURCE             LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USART  Peripheral USART get clock source
+  * @{
+  */
+#define LL_RCC_USART1_CLKSOURCE            LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0U)
+#define LL_RCC_USART2_CLKSOURCE            LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0U)
+#define LL_RCC_USART3_CLKSOURCE            LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0U)
+#define LL_RCC_USART6_CLKSOURCE            LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0U)
+#define LL_RCC_USART10_CLKSOURCE           LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_XSPI  Peripheral XSPI get clock source
+  * @{
+  */
+#define LL_RCC_XSPI1_CLKSOURCE             LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0U)
+#define LL_RCC_XSPI2_CLKSOURCE             LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0U)
+#define LL_RCC_XSPI3_CLKSOURCE             LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+  * @{
+  */
+#define LL_RCC_TIM_PRESCALER_1             0U
+#define LL_RCC_TIM_PRESCALER_2             1U
+#define LL_RCC_TIM_PRESCALER_4             2U
+#define LL_RCC_TIM_PRESCALER_8             3U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               0U
+#define LL_RCC_PLLSOURCE_MSI               RCC_PLL1CFGR1_PLL1SEL_0
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLL1CFGR1_PLL1SEL_1
+#define LL_RCC_PLLSOURCE_I2S_CKIN          (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ICSOURCE   All ICs entry clock source
+  * @{
+  */
+#define LL_RCC_ICCLKSOURCE_PLL1               0U
+#define LL_RCC_ICCLKSOURCE_PLL2               RCC_IC1CFGR_IC1SEL_0
+#define LL_RCC_ICCLKSOURCE_PLL3               RCC_IC1CFGR_IC1SEL_1
+#define LL_RCC_ICCLKSOURCE_PLL4               (RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency.
+  * @param  __HPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_32
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  * @retval HCLK clock frequency (in Hz)
+  */
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> (((__HPRESCALER__) &\
+                                                               RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos))
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  *         @arg @ref LL_RCC_APB1_DIV_32
+  *         @arg @ref LL_RCC_APB1_DIV_64
+  *         @arg @ref LL_RCC_APB1_DIV_128
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (((__APB1PRESCALER__) &\
+                                                                 RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos))
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  *         @arg @ref LL_RCC_APB2_DIV_32
+  *         @arg @ref LL_RCC_APB2_DIV_64
+  *         @arg @ref LL_RCC_APB2_DIV_128
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (((__APB2PRESCALER__) &\
+                                                                 RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos))
+
+/**
+  * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB4PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  *         @arg @ref LL_RCC_APB4_DIV_32
+  *         @arg @ref LL_RCC_APB4_DIV_64
+  *         @arg @ref LL_RCC_APB4_DIV_128
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> (((__APB4PRESCALER__) &\
+                                                                 RCC_CFGR2_PPRE4) >> RCC_CFGR2_PPRE4_Pos))
+
+/**
+  * @brief  Helper macro to calculate the PCLK5 frequency (APB5)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB5PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB5_DIV_1
+  *         @arg @ref LL_RCC_APB5_DIV_2
+  *         @arg @ref LL_RCC_APB5_DIV_4
+  *         @arg @ref LL_RCC_APB5_DIV_8
+  *         @arg @ref LL_RCC_APB5_DIV_16
+  *         @arg @ref LL_RCC_APB5_DIV_32
+  *         @arg @ref LL_RCC_APB5_DIV_64
+  *         @arg @ref LL_RCC_APB5_DIV_128
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define LL_RCC_CALC_PCLK5_FREQ(__HCLKFREQ__, __APB5PRESCALER__) ((__HCLKFREQ__) >> (((__APB5PRESCALER__) &\
+                                                                 RCC_CFGR2_PPRE5) >> RCC_CFGR2_PPRE5_Pos))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFUL       /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the HSE Clock Security System.
+  * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a reset occurs or system enter in standby mode.
+  * @rmtoll HSECFGR      HSECSSON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSON);
+}
+
+/**
+  * @brief  Check if HSE failure is detected by Clock Security System
+  * @rmtoll HSECFGR      HSECSSD       LL_RCC_HSE_IsFailureDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsFailureDetected(void)
+{
+  return ((READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSD) != 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the HSE Clock Security System bypass.
+  * @note Bypass the HSE oscillator when a failure is detected and get the clock from
+  *       the HSI oscillator (HSI injection)
+  * @rmtoll HSECFGR      HSECSSBYP     LL_RCC_HSE_EnableCSSBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSSBypass(void)
+{
+  SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBYP);
+}
+
+/**
+  * @brief  Disable the HSE Clock Security System bypass.
+  * @rmtoll HSECFGR      HSECSSBYP     LL_RCC_HSE_DisableCSSBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableCSSBypass(void)
+{
+  CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBYP);
+}
+
+/**
+  * @brief  Set HSE Clock Security System bypass divider
+  * @note   To divide the replacement internal HSI oscillator that
+  *         bypasses the HSE oscillator when a failure is detected
+  * @rmtoll HSECFGR      HSECSSBPRE    LL_RCC_HSE_SetCSSBypassDivider
+  * @param  Divider This parameter can be a value from RCC_LL_EC_HSECSSBYP_DIV.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SetCSSBypassDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->HSECFGR, RCC_HSECFGR_HSECSSBPRE, Divider);
+}
+
+/**
+  * @brief  Get HSE Clock Security System bypass divider
+  * @note   To divide the replacement internal HSI oscillator that
+  *         bypasses the HSE oscillator when a failure is detected
+  * @rmtoll HSECFGR      HSECSSBPRE    LL_RCC_HSE_GetCSSBypassDivider
+  * @retval can be a value from RCC_LL_EC_HSECSSBYP_DIV.
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_GetCSSBypassDivider(void)
+{
+  return (READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSBPRE));
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll HSECFGR      HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll HSECFGR      HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP);
+}
+
+/**
+  * @brief  Select the Analog HSE external clock type in Bypass mode
+  * @rmtoll HSECFGR      HSEEXT        LL_RCC_HSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT);
+}
+
+/**
+  * @brief  Select the Digital HSE external clock type in Bypass mode
+  * @rmtoll HSECFGR      HSEEXT        LL_RCC_HSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT);
+}
+
+/**
+  * @brief  Select the HSE as hse_div2_osc_ck output clock
+  * @rmtoll HSECFGR      HSEDIV2SEL    LL_RCC_HSE_SelectHSEAsDiv2Clock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectHSEAsDiv2Clock(void)
+{
+  CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL);
+}
+
+/**
+  * @brief  Select the HSE divided by 2 as hse_div2_osc_ck output clock
+  * @rmtoll HSECFGR      HSEDIV2SEL    LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(void)
+{
+  SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL);
+}
+
+/**
+  * @brief  Check if hse_div2_osc_ck output clock is divided by 2
+  * @rmtoll HSECFGR      HSEDIV2SEL    LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock(void)
+{
+  return ((READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEDIV2SEL) == RCC_HSECFGR_HSEDIV2SEL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CSR          HSEONS        LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_HSEONS);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CCR          HSEONC        LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_HSEONC);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll SR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_HSERDY) != 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CSR          HSIONS        LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_HSIONS);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CCR          HSIONC        LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_HSIONC);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll SR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_HSIRDY) != 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set HSI divider
+  * @rmtoll HSICFGR      HSIDIV        LL_RCC_HSI_SetDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV_1
+  *         @arg @ref LL_RCC_HSI_DIV_2
+  *         @arg @ref LL_RCC_HSI_DIV_4
+  *         @arg @ref LL_RCC_HSI_DIV_8
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSIDIV, Divider);
+}
+
+/**
+  * @brief  Get HSI divider
+  * @rmtoll HSICFGR      HSIDIV        LL_RCC_HSI_GetDivider
+  * @retval can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV_1
+  *         @arg @ref LL_RCC_HSI_DIV_2
+  *         @arg @ref LL_RCC_HSI_DIV_4
+  *         @arg @ref LL_RCC_HSI_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
+{
+  return (READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSIDIV));
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll HSICFGR      HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval A value between 0 and 511 (0x1FF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 32, which, when added to the HSICAL value,
+  *       should trim the HSI to 32 MHz +/- 1 %
+  * @rmtoll HSICFGR      HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value This parameter can be a value between 0 and 63
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll HSICFGR      HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+}
+
+/**
+  * @brief  Enable HSI even in stop mode
+  * @note HSI oscillator is forced ON even in Stop mode
+  * @rmtoll STOPCR       HSISTOPEN     LL_RCC_HSI_EnableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
+{
+  SET_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN);
+}
+
+/**
+  * @brief  Disable HSI in stop mode
+  * @rmtoll STOPCR       HSISTOPEN     LL_RCC_HSI_DisableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
+{
+  CLEAR_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN);
+}
+
+/**
+  * @brief  Check if HSI is enabled in stop mode
+  * @rmtoll STOPCR       HSISTOPEN     LL_RCC_HSI_IsEnabledInStopMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
+{
+  return ((READ_BIT(RCC->STOPCR, RCC_STOPCR_HSISTOPEN) == RCC_STOPCR_HSISTOPEN) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MSI MSI
+  * @{
+  */
+
+/**
+  * @brief  Enable MSI oscillator
+  * @rmtoll CSR          MSIONS        LL_RCC_MSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_MSIONS);
+}
+
+/**
+  * @brief  Disable MSI oscillator
+  * @rmtoll CCR          MSIONC        LL_RCC_MSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_MSIONC);
+}
+
+/**
+  * @brief  Check if MSI clock is ready
+  * @rmtoll SR           MSIRDY        LL_RCC_MSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_MSIRDY) != 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set MSI frequency
+  * @rmtoll MSICFGR      MSIFREQSEL    LL_RCC_MSI_SetFrequency
+  * @param  Value This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MSI_FREQ_4MHZ
+  *         @arg @ref LL_RCC_MSI_FREQ_16MHZ
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_MSI_SetFrequency(uint32_t Value)
+{
+  MODIFY_REG(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL, Value);
+}
+
+/**
+  * @brief  Get HSI divider
+  * @rmtoll MSICFGR      MSIFREQSEL    LL_RCC_MSI_GetFrequency
+  * @retval can be one of the following values:
+  *         @arg @ref LL_RCC_MSI_FREQ_4MHZ
+  *         @arg @ref LL_RCC_MSI_FREQ_16MHZ
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetFrequency(void)
+{
+  return (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL));
+}
+
+
+/**
+  * @brief  Get MSI Calibration value
+  * @note When MSITRIM is written, MSICAL is updated with the sum of
+  *       MSITRIM and the factory trim value
+  * @rmtoll MSICFGR      MSICAL        LL_RCC_MSI_GetCalibration
+  * @retval A value between 0 and 255 (0xFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSICAL) >> RCC_MSICFGR_MSICAL_Pos);
+}
+
+/**
+  * @brief  Set MSI Calibration trimming
+  * @note user-programmable trimming value that is added to the MSICAL
+  * @note Default value is 16, which, when added to the MSICAL value,
+  *       should trim the MSI to 4 MHz +/- 1 %
+  * @rmtoll MSICFGR      MSITRIM       LL_RCC_MSI_SetCalibTrimming
+  * @param  Value can be a value between 0 and 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->MSICFGR, RCC_MSICFGR_MSITRIM, Value << RCC_MSICFGR_MSITRIM_Pos);
+}
+
+/**
+  * @brief  Get MSI Calibration trimming
+  * @rmtoll MSICFGR      MSITRIM       LL_RCC_MSI_GetCalibTrimming
+  * @retval A value between 0 and 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSITRIM) >> RCC_MSICFGR_MSITRIM_Pos);
+}
+
+/**
+  * @brief  Enable MSI even in stop mode
+  * @note MSI oscillator is forced ON even in Stop mode
+  * @rmtoll STOPCR       MSISTOPEN     LL_RCC_MSI_EnableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_EnableInStopMode(void)
+{
+  SET_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN);
+}
+
+/**
+  * @brief  Disable MSI in stop mode
+  * @rmtoll STOPCR       MSISTOPEN     LL_RCC_MSI_DisableInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MSI_DisableInStopMode(void)
+{
+  CLEAR_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN);
+}
+
+/**
+  * @brief  Check if MSI is enabled in stop mode
+  * @rmtoll STOPCR       MSISTOPEN     LL_RCC_MSI_IsEnabledInStopMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledInStopMode(void)
+{
+  return ((READ_BIT(RCC->STOPCR, RCC_STOPCR_MSISTOPEN) == RCC_STOPCR_MSISTOPEN) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System on LSE
+  * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a clock failure is detected.
+  * @rmtoll LSECFGR      LSECSSON         LL_RCC_LSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+  SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON);
+}
+
+/**
+  * @brief  Disable the Clock Security System on LSE
+  * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a clock failure is detected.
+  * @rmtoll LSECFGR      LSECSSON         LL_RCC_LSE_DisableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON);
+}
+
+/**
+  * @brief  Check if LSE failure is detected by Clock Security System
+  * @rmtoll LSECFGR      LSECSSD       LL_RCC_LSE_IsFailureDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
+{
+  return ((READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSD) != 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Re-arm the Clock Security System on LSE
+  * @note Once a clock failure is detected, the LSE Clock Security System can be re-armed providing that
+  *       LSECSSON is disabled.
+  * @rmtoll LSECFGR      LSECSSRA         LL_RCC_LSE_ReArmCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_ReArmCSS(void)
+{
+  SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSRA);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass)
+  * @rmtoll LSECFGR      LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass)
+  * @rmtoll LSECFGR      LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP);
+}
+
+/**
+  * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll LSECFGR      LSEEXT        LL_RCC_LSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);
+}
+
+/**
+  * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll LSECFGR      LSEEXT        LL_RCC_LSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT);
+}
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll LSECFGR      LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->LSECFGR, RCC_LSECFGR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll LSECFGR      LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEDRV));
+}
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal
+  * @rmtoll CSR          LSEONS        LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_LSEONS);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal
+  * @rmtoll CCR          LSEONC        LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_LSEONC);
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll SR           LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_LSERDY) != 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the LSE clock glitch filter
+  * @note   This API shall be called only when LSE is disabled.
+  * @rmtoll LSECFGR      LSEGFON          LL_RCC_LSE_EnableGlitchFilter
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void)
+{
+  SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEGFON);
+}
+
+/**
+  * @brief  Disable the LSE clock glitch filter
+  * @note   This API shall be called only when LSE is disabled.
+  * @rmtoll LSECFGR      LSEGFON         LL_RCC_LSE_DisableGlitchFilter
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void)
+{
+  CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEGFON);
+}
+
+/**
+  * @brief  Check if LSE clock glitch filter is enabled
+  * @rmtoll LSECFGR      LSEGFON         LL_RCC_LSE_IsEnabledGlitchFilter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabledGlitchFilter(void)
+{
+  return ((READ_BIT(RCC->STOPCR, RCC_LSECFGR_LSEGFON) == RCC_LSECFGR_LSEGFON) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSIONS        LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_LSIONS);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CCR          LSIONC        LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_LSIONC);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll SR           LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_LSIRDY) != 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the CPU clock source
+  * @rmtoll CFGR1        CPUSW         LL_RCC_SetCpuClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_IC1
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCpuClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR1, RCC_CFGR1_CPUSW, Source);
+}
+
+/**
+  * @brief  Get the CPU clock source
+  * @rmtoll CFGR1        CPUSWS        LL_RCC_GetCpuClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_MSI
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_CPU_CLKSOURCE_STATUS_IC1
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCpuClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_CPUSWS));
+}
+
+/**
+  * @brief  Configure the system clock source (bus clock)
+  * @rmtoll CFGR1        SYSSW         LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SYSSW, Source);
+}
+
+/**
+  * @brief  Get the system clock source (bus clock)
+  * @rmtoll CFGR1        SYSSWS        LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SYSSWS));
+}
+
+/**
+  * @brief  Configure the system wakeup clock source
+  * @rmtoll CFGR1        STOPWUCK       LL_RCC_SetSysWakeUpClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_MSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Source);
+}
+
+/**
+  * @brief  Get the system wakeup clock source
+  * @rmtoll CFGR1        STOPWUCK           LL_RCC_GetSysWakeUpClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_MSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK));
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll CFGR2         HPRE          LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_32
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll CFGR2         HPRE          LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_32
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll CFGR2         PPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  *         @arg @ref LL_RCC_APB1_DIV_32
+  *         @arg @ref LL_RCC_APB1_DIV_64
+  *         @arg @ref LL_RCC_APB1_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll CFGR2         PPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  *         @arg @ref LL_RCC_APB1_DIV_32
+  *         @arg @ref LL_RCC_APB1_DIV_64
+  *         @arg @ref LL_RCC_APB1_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll CFGR2         PPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  *         @arg @ref LL_RCC_APB2_DIV_32
+  *         @arg @ref LL_RCC_APB2_DIV_64
+  *         @arg @ref LL_RCC_APB2_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll CFGR2         PPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  *         @arg @ref LL_RCC_APB2_DIV_32
+  *         @arg @ref LL_RCC_APB2_DIV_64
+  *         @arg @ref LL_RCC_APB2_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
+}
+
+/**
+  * @brief  Set APB4 prescaler
+  * @rmtoll CFGR2         PPRE4         LL_RCC_SetAPB4Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  *         @arg @ref LL_RCC_APB4_DIV_32
+  *         @arg @ref LL_RCC_APB4_DIV_64
+  *         @arg @ref LL_RCC_APB4_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, Prescaler);
+}
+
+/**
+  * @brief  Get APB4 prescaler
+  * @rmtoll CFGR2         PPRE4         LL_RCC_GetAPB4Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  *         @arg @ref LL_RCC_APB4_DIV_32
+  *         @arg @ref LL_RCC_APB4_DIV_64
+  *         @arg @ref LL_RCC_APB4_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE4));
+}
+
+/**
+  * @brief  Set APB5 prescaler
+  * @rmtoll CFGR2        PPRE5         LL_RCC_SetAPB5Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB5_DIV_1
+  *         @arg @ref LL_RCC_APB5_DIV_2
+  *         @arg @ref LL_RCC_APB5_DIV_4
+  *         @arg @ref LL_RCC_APB5_DIV_8
+  *         @arg @ref LL_RCC_APB5_DIV_16
+  *         @arg @ref LL_RCC_APB5_DIV_32
+  *         @arg @ref LL_RCC_APB5_DIV_64
+  *         @arg @ref LL_RCC_APB5_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB5Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, Prescaler);
+}
+
+/**
+  * @brief  Get APB5 prescaler
+  * @rmtoll CFGR2        PPRE5         LL_RCC_GetAPB5Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB5_DIV_1
+  *         @arg @ref LL_RCC_APB5_DIV_2
+  *         @arg @ref LL_RCC_APB5_DIV_4
+  *         @arg @ref LL_RCC_APB5_DIV_8
+  *         @arg @ref LL_RCC_APB5_DIV_16
+  *         @arg @ref LL_RCC_APB5_DIV_32
+  *         @arg @ref LL_RCC_APB5_DIV_64
+  *         @arg @ref LL_RCC_APB5_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB5Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE5));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Enable MCOx output
+  * @note   The clock provided to the MCOx outputs must not exceed the maximum IO speed,
+  *         refer to the product datasheet for information about the supported IO speed.
+  * @rmtoll MISCENSR     MCO1ENS       LL_RCC_EnableMCO\n
+  *         MISCENSR     MCO2ENS       LL_RCC_EnableMCO
+  * @param  MCOx  This parameter can be one or a combination of the following values:
+  *         @arg @ref LL_RCC_MCO1
+  *         @arg @ref LL_RCC_MCO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableMCO(uint32_t MCOx)
+{
+  WRITE_REG(RCC->MISCENSR, MCOx);
+}
+
+/**
+  * @brief  Disable MCOx output
+  * @rmtoll MISCENCR     MCO1ENC       LL_RCC_DisableMCO\n
+  *         MISCENCR     MCO2ENC       LL_RCC_DisableMCO
+  * @param  MCOx  This parameter can be one or a combination of the following values:
+  *         @arg @ref LL_RCC_MCO1
+  *         @arg @ref LL_RCC_MCO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableMCO(uint32_t MCOx)
+{
+  WRITE_REG(RCC->MISCENCR, MCOx);
+}
+
+/**
+  * @brief  Configure MCOx
+  * @note   The clock provided to the MCOx outputs must not exceed the maximum IO speed,
+  *         refer to the product datasheet for information about the supported IO speed.
+  * @note   The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch).
+  * @rmtoll CCIPR5       MCO1SEL       LL_RCC_ConfigMCO\n
+  *         CCIPR5       MCO1PRE       LL_RCC_ConfigMCO\n
+  *         CCIPR5       MCO2SEL       LL_RCC_ConfigMCO\n
+  *         CCIPR5       MCO2PRE       LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_MSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_IC5
+  *         @arg @ref LL_RCC_MCO1SOURCE_IC10
+  *         @arg @ref LL_RCC_MCO1SOURCE_SYSA
+  *         @arg @ref LL_RCC_MCO2SOURCE_LSI
+  *         @arg @ref LL_RCC_MCO2SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_MSI
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_IC15
+  *         @arg @ref LL_RCC_MCO2SOURCE_IC20
+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSB
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_3
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_5
+  *         @arg @ref LL_RCC_MCO1_DIV_6
+  *         @arg @ref LL_RCC_MCO1_DIV_7
+  *         @arg @ref LL_RCC_MCO1_DIV_8
+  *         @arg @ref LL_RCC_MCO1_DIV_9
+  *         @arg @ref LL_RCC_MCO1_DIV_10
+  *         @arg @ref LL_RCC_MCO1_DIV_11
+  *         @arg @ref LL_RCC_MCO1_DIV_12
+  *         @arg @ref LL_RCC_MCO1_DIV_13
+  *         @arg @ref LL_RCC_MCO1_DIV_14
+  *         @arg @ref LL_RCC_MCO1_DIV_15
+  *         @arg @ref LL_RCC_MCO2_DIV_1
+  *         @arg @ref LL_RCC_MCO2_DIV_2
+  *         @arg @ref LL_RCC_MCO2_DIV_3
+  *         @arg @ref LL_RCC_MCO2_DIV_4
+  *         @arg @ref LL_RCC_MCO2_DIV_5
+  *         @arg @ref LL_RCC_MCO2_DIV_6
+  *         @arg @ref LL_RCC_MCO2_DIV_7
+  *         @arg @ref LL_RCC_MCO2_DIV_8
+  *         @arg @ref LL_RCC_MCO2_DIV_9
+  *         @arg @ref LL_RCC_MCO2_DIV_10
+  *         @arg @ref LL_RCC_MCO2_DIV_11
+  *         @arg @ref LL_RCC_MCO2_DIV_12
+  *         @arg @ref LL_RCC_MCO2_DIV_13
+  *         @arg @ref LL_RCC_MCO2_DIV_14
+  *         @arg @ref LL_RCC_MCO2_DIV_15
+  *         @arg @ref LL_RCC_MCO2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CCIPR5, ((MCOxSource | MCOxPrescaler) >> 16U), \
+             (MCOxSource & (RCC_CCIPR5_MCO1SEL | RCC_CCIPR5_MCO2SEL)) | (MCOxPrescaler & (RCC_CCIPR5_MCO1PRE | RCC_CCIPR5_MCO2PRE)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure periph clock source
+  * @rmtoll CCIPR4        *     LL_RCC_SetClockSource\n
+  *         CCIPR6        *     LL_RCC_SetClockSource\n
+  *         CCIPR8        *     LL_RCC_SetClockSource\n
+  *         CCIPR9        *     LL_RCC_SetClockSource\n
+  *         CCIPR12       *     LL_RCC_SetClockSource\n
+  *         CCIPR13       *     LL_RCC_SetClockSource\n
+  *         CCIPR14       *     LL_RCC_SetClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
+{
+  volatile uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource));
+  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
+}
+
+/**
+  * @brief  Set ADC prescaler
+  * @rmtoll CCIPR1        ADCPRE        LL_RCC_SetADCPrescaler
+  * @param  Prescaler This parameter must be a number between Min_Data = 0 and Max_Data = 255 for prescaler 1 to 256
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADCPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCPRE, (Prescaler << RCC_CCIPR1_ADCPRE_Pos));
+}
+
+/**
+  * @brief  Get ADC prescaler
+  * @rmtoll CCIPR1        ADCPRE        LL_RCC_GetADCPrescaler
+  * @retval Returned value between Min_Data = 0 and Max_Data = 255 for prescaler 1 to 256
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADCPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCPRE) >> RCC_CCIPR1_ADCPRE_Pos);
+}
+
+/**
+  * @brief  Configure ADCx Kernel clock source
+  * @rmtoll CCIPR1        ADC12SEL        LL_RCC_SetADCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_TIMG
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADC12SEL, ClkSource);
+}
+
+/**
+  * @brief  Configure ADFx Kernel clock source
+  * @rmtoll CCIPR1         ADF1SEL        LL_RCC_SetADFClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_TIMG
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADFClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL, ClkSource);
+}
+
+/**
+  * @brief  Configure CLKP Kernel clock source
+  * @rmtoll CCIPR7         PERSEL         LL_RCC_SetCLKPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC19
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC20
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PERSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure DCMIPP Kernel clock source
+  * @rmtoll CCIPR1         DCMIPPSEL        LL_RCC_SetDCMIPPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_PCLK5
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_IC17
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDCMIPPClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_DCMIPPSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure ETHx Kernel clock source
+  * @rmtoll CCIPR2        ETH1CLKSEL     LL_RCC_SetETHClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_IC12
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetETHClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1CLKSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure ETHx PTP Kernel clock source
+  * @rmtoll CCIPR2        ETH1PTPSEL     LL_RCC_SetETHPTPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_IC13
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetETHPTPClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure ETHx PHY interface
+  * @rmtoll CCIPR2        ETH1SEL        LL_RCC_SetETHPHYInterface
+  * @param  Interface This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PHY_IF_MII
+  *         @arg @ref LL_RCC_ETH1PHY_IF_RGMII
+  *         @arg @ref LL_RCC_ETH1PHY_IF_RMII
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetETHPHYInterface(uint32_t Interface)
+{
+  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1SEL, Interface);
+}
+
+/**
+  * @brief  Set ETH1 PTP Kernel clock divider
+  * @rmtoll CCIPR2       ETH1PTPDIV    LL_RCC_SetETH1PTPDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_1
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_2
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_3
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_4
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_5
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_6
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_7
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_8
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_9
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_10
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_11
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_12
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_13
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_14
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_15
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_16
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_SetETH1PTPDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPDIV, Divider);
+}
+
+/**
+  * @brief  Get ETH1 PTP Kernel clock divider
+  * @rmtoll CCIPR2       ETH1PTPDIV    LL_RCC_GetETH1PTPDivider
+  * @retval can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_1
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_2
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_3
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_4
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_5
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_6
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_7
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_8
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_9
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_10
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_11
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_12
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_13
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_14
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_15
+  *         @arg @ref LL_RCC_ETH1PTP_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetETH1PTPDivider(void)
+{
+  return (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPDIV));
+}
+
+/**
+  * @brief  Configure ETHx Reference RX Kernel clock source
+  * @rmtoll CCIPR2        ETH1REFCLKSEL  LL_RCC_SetETHREFRXClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_EXT
+  *         @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_INT
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetETHREFRXClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1REFCLKSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure ETHx Reference TX Kernel clock source
+  * @rmtoll CCIPR2        ETH1GTXCLKSEL  LL_RCC_SetETHREFTXClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_EXT
+  *         @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_INT
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetETHREFTXClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ETH1GTXCLKSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure FDCANx Kernel clock source
+  * @rmtoll CCIPR3        FDCANSEL        LL_RCC_SetFDCANClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_IC19
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_FDCANSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure FMCx Kernel clock source
+  * @rmtoll CCIPR3       FMCSEL        LL_RCC_SetFMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_IC4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_FMCSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll CCIPR4       I2C1SEL       LL_RCC_SetI2CClockSource\n
+  * @rmtoll CCIPR4       I2C2SEL       LL_RCC_SetI2CClockSource\n
+  * @rmtoll CCIPR4       I2C3SEL       LL_RCC_SetI2CClockSource\n
+  * @rmtoll CCIPR4       I2C4SEL       LL_RCC_SetI2CClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure I3Cx clock source
+  * @rmtoll CCIPR4       I3C1SEL       LL_RCC_SetI3CClockSource\n
+  * @rmtoll CCIPR4       I3C2SEL       LL_RCC_SetI3CClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll CCIPR12      LPTIM1SEL     LL_RCC_SetLPTIMClockSource\n
+  *         CCIPR12      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n
+  *         CCIPR12      LPTIM3SEL     LL_RCC_SetLPTIMClockSource\n
+  *         CCIPR12      LPTIM4SEL     LL_RCC_SetLPTIMClockSource\n
+  *         CCIPR12      LPTIM5SEL     LL_RCC_SetLPTIMClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPUARTx clock source
+  * @rmtoll CCIPR14        LPUART1SEL     LL_RCC_SetLPUARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR14, RCC_CCIPR14_LPUART1SEL, ClkSource);
+}
+
+/**
+  * @brief  Configure LTDC clock source
+  * @rmtoll CCIPR4         LTDCSEL     LL_RCC_SetLTDCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PCLK5
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_IC16
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LTDCSEL, ClkSource);
+}
+
+/**
+  * @brief  Configure MDFx Kernel clock source
+  * @rmtoll CCIPR5         MDF1SEL        LL_RCC_SetMDFClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_TIMG
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetMDFClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL, ClkSource);
+}
+
+/**
+  * @brief  Configure OTGPHY clock source
+  * @rmtoll CCIPR6       OTGPHY1SEL        LL_RCC_SetOTGPHYClockSource\n
+  *         CCIPR6       OTGPHY2SEL        LL_RCC_SetOTGPHYClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetOTGPHYClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure OTGPHYCKREF clock source
+  * @rmtoll CCIPR6       OTGPHY1CKREFSEL   LL_RCC_SetOTGPHYCKREFClockSource\n
+  *         CCIPR6       OTGPHY2CKREFSEL   LL_RCC_SetOTGPHYCKREFClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetOTGPHYCKREFClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure PSSI clock source
+  * @rmtoll CCIPR7       PSSISEL        LL_RCC_SetPSSIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_IC20
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetPSSIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PSSISEL, ClkSource);
+}
+
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll CCIPR7       SAI1SEL      LL_RCC_SetSAIClockSource\n
+  *         CCIPR7       SAI2SEL      LL_RCC_SetSAIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SDMMCx clock source
+  * @rmtoll CCIPR8       SDMMC1SEL      LL_RCC_SetSDMMCClockSource\n
+  *         CCIPR8       SDMMC2SEL      LL_RCC_SetSDMMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SPDIFRX1 Kernel clock source
+  * @rmtoll CCIPR9       SPDIFRX1SEL        LL_RCC_SetSPDIFRXClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CCIPR9, RCC_CCIPR9_SPDIFRX1SEL, ClkSource);
+}
+
+/**
+  * @brief  Configure SPIx Kernel clock source
+  * @rmtoll CCIPR9       SPI1SEL        LL_RCC_SetSPIClockSource\n
+  *         CCIPR9       SPI2SEL        LL_RCC_SetSPIClockSource\n
+  *         CCIPR9       SPI3SEL        LL_RCC_SetSPIClockSource\n
+  *         CCIPR9       SPI4SEL        LL_RCC_SetSPIClockSource\n
+  *         CCIPR9       SPI5SEL        LL_RCC_SetSPIClockSource\n
+  *         CCIPR9       SPI6SEL        LL_RCC_SetSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll CCIPR13        USART1SEL      LL_RCC_SetUSARTClockSource\n
+  *         CCIPR13        USART2SEL      LL_RCC_SetUSARTClockSource\n
+  *         CCIPR13        USART3SEL      LL_RCC_SetUSARTClockSource\n
+  *         CCIPR13        USART6SEL      LL_RCC_SetUSARTClockSource\n
+  *         CCIPR14        USART10SEL     LL_RCC_SetUSARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure UARTx clock source
+  * @rmtoll CCIPR13      UART4SEL      LL_RCC_SetUARTClockSource\n
+  *         CCIPR13      UART5SEL      LL_RCC_SetUARTClockSource\n
+  *         CCIPR13      UART7SEL      LL_RCC_SetUARTClockSource\n
+  *         CCIPR13      UART8SEL      LL_RCC_SetUARTClockSource\n
+  *         CCIPR14      UART9SEL      LL_RCC_SetUARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure USBx clock source
+  * @rmtoll CCIPR6      OTGPHY1SEL        LL_RCC_GetUSBClockSource\n
+  *         CCIPR6      OTGPHY1CKREFSEL   LL_RCC_GetUSBClockSource\n
+  *         CCIPR6      OTGPHY2SEL        LL_RCC_GetUSBClockSource\n
+  *         CCIPR6      OTGPHY2CKREFSEL   LL_RCC_GetUSBClockSource\n
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure XSPIx Kernel clock source
+  * @rmtoll CCIPR6         XSPI1SEL        LL_RCC_SetXSPIClockSource\n
+  *         CCIPR6         XSPI2SEL        LL_RCC_SetXSPIClockSource\n
+  *         CCIPR6         XSPI3SEL        LL_RCC_SetXSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetXSPIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Get periph clock source
+  * @rmtoll CCIPR1      *     LL_RCC_GetClockSource\n
+  *         CCIPR3      *     LL_RCC_GetClockSource\n
+  *         CCIPR4      *     LL_RCC_GetClockSource\n
+  *         CCIPR6      *     LL_RCC_GetClockSource\n
+  *         CCIPR7      *     LL_RCC_GetClockSource\n
+  *         CCIPR8      *     LL_RCC_GetClockSource\n
+  *         CCIPR9      *     LL_RCC_GetClockSource\n
+  *         CCIPR12     *     LL_RCC_GetClockSource\n
+  *         CCIPR13     *     LL_RCC_GetClockSource\n
+  *         CCIPR14     *     LL_RCC_GetClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
+{
+  const volatile uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph)));
+  return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
+}
+
+/**
+  * @brief  Get ADC Kernel clock source
+  * @rmtoll CCIPR1       ADC12SEL       LL_RCC_GetADCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_TIMG
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADC12SEL));
+}
+
+/**
+  * @brief  Get ADFx clock source
+  * @rmtoll CCIPR1       ADF1SEL        LL_RCC_GetADFClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE_TIMG
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADFClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL));
+}
+
+/**
+  * @brief  Get CLKP Kernel clock source
+  * @rmtoll CCIPR7         PERSEL         LL_RCC_GetCLKPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC19
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_IC20
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_PERSEL));
+}
+
+/**
+  * @brief  Get DCMIPP clock source
+  * @rmtoll CCIPR1       DCMIPPSEL        LL_RCC_GetDCMIPPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_PCLK5
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_IC17
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDCMIPPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_DCMIPPSEL));
+}
+
+/**
+  * @brief  Get ETHx Kernel clock source
+  * @rmtoll CCIPR2        ETH1CLKSEL     LL_RCC_GetETHClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_IC12
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetETHClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1CLKSEL));
+}
+
+/**
+  * @brief  Get ETHx PTP Kernel clock source
+  * @rmtoll CCIPR2        ETH1PTPSEL     LL_RCC_GetETHPTPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_IC13
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetETHPTPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PTPSEL));
+}
+
+/**
+  * @brief  Get ETHx PHY interface
+  * @rmtoll CCIPR2        ETH1SEL        LL_RCC_GetETHPHYInterface
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PHY_IF
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PHY_IF_MII
+  *         @arg @ref LL_RCC_ETH1PHY_IF_RGMII
+  *         @arg @ref LL_RCC_ETH1PHY_IF_RMII
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetETHPHYInterface(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1SEL));
+}
+
+/**
+  * @brief  Get ETHx Reference RX Kernel clock source
+  * @rmtoll CCIPR2        ETH1REFCLKSEL  LL_RCC_GetETHREFRXClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_EXT
+  *         @arg @ref LL_RCC_ETH1REFRX_CLKSOURCE_INT
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetETHREFRXClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1REFCLKSEL));
+}
+
+/**
+  * @brief  Get ETHx Reference TX Kernel clock source
+  * @rmtoll CCIPR2        ETH1GTXCLKSEL  LL_RCC_GetETHREFTXClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_EXT
+  *         @arg @ref LL_RCC_ETH1REFTX_CLKSOURCE_INT
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetETHREFTXClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1GTXCLKSEL));
+}
+
+/**
+  * @brief  Get FDCAN Kernel clock source
+  * @rmtoll CCIPR3       FDCANSEL        LL_RCC_GetFDCANClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_IC19
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_FDCANSEL));
+}
+
+/**
+  * @brief  Get FMC Kernel clock source
+  * @rmtoll CCIPR3         FMCSEL        LL_RCC_GetFMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_IC4
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_FMCSEL));
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll CCIPR4       I2C1SEL       LL_RCC_GetI2CClockSource\n
+  * @rmtoll CCIPR4       I2C2SEL       LL_RCC_GetI2CClockSource\n
+  * @rmtoll CCIPR4       I2C3SEL       LL_RCC_GetI2CClockSource\n
+  * @rmtoll CCIPR4       I2C4SEL       LL_RCC_GetI2CClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get I3Cx clock source
+  * @rmtoll CCIPR4       I3C1SEL       LL_RCC_GetI3CClockSource\n
+  * @rmtoll CCIPR4       I3C2SEL       LL_RCC_GetI3CClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC10
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPTIM clock source
+  * @rmtoll CCIPR12      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
+  *         CCIPR12      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n
+  *         CCIPR12      LPTIM3SEL     LL_RCC_GetLPTIMClockSource\n
+  *         CCIPR12      LPTIM4SEL     LL_RCC_GetLPTIMClockSource\n
+  *         CCIPR12      LPTIM5SEL     LL_RCC_GetLPTIMClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE_TIMG
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE_TIMG
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPUART clock source
+  * @rmtoll CCIPR14       LPUART1SEL     LL_RCC_GetLPUARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR14, RCC_CCIPR14_LPUART1SEL));
+}
+
+/**
+  * @brief  Get LTDC clock source
+  * @rmtoll CCIPR4        LTDCSEL     LL_RCC_GetLTDCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PCLK5
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_IC16
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LTDCSEL));
+}
+
+/**
+  * @brief  Get MDFx clock source
+  * @rmtoll CCIPR5       MDF1SEL        LL_RCC_GetMDFClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE_TIMG
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetMDFClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL));
+}
+
+/**
+  * @brief  Get OTGPHY clock source
+  * @rmtoll CCIPR6       OTGPHY1SEL        LL_RCC_GetOTGPHYClockSource\n
+  *         CCIPR6       OTGPHY2SEL        LL_RCC_GetOTGPHYClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetOTGPHYClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get OTGPHYCKREF clock source
+  * @rmtoll CCIPR6       OTGPHY1CKREFSEL   LL_RCC_GetOTGPHYCKREFClockSource\n
+  *         CCIPR6       OTGPHY2CKREFSEL   LL_RCC_GetOTGPHYCKREFClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetOTGPHYCKREFClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get PSSI clock source
+  * @rmtoll CCIPR7      PSSISEL      LL_RCC_GetPSSIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_IC20
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetPSSIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_PSSISEL));
+}
+
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll CCIPR7     SAI1SEL      LL_RCC_GetSAIClockSource\n
+  *         CCIPR7     SAI2SEL      LL_RCC_GetSAIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_SPDIFRX1
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX1
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SDMMC clock source
+  * @rmtoll CCIPR8      SDMMC1SEL      LL_RCC_GetSDMMCClockSource\n
+  *         CCIPR8      SDMMC2SEL      LL_RCC_GetSDMMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_IC5
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE_IC5
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SPDIFRX Kernel clock source
+  * @rmtoll CCIPR9      SPDIFRX1SEL        LL_RCC_GetSPDIFRXClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC7
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CCIPR9, RCC_CCIPR9_SPDIFRX1SEL));
+}
+
+/**
+  * @brief  Get SPIx Kernel clock source
+  * @rmtoll CCIPR9     SPI1SEL         LL_RCC_GetSPIClockSource\n
+  *         CCIPR9     SPI2SEL         LL_RCC_GetSPIClockSource\n
+  *         CCIPR9     SPI3SEL         LL_RCC_GetSPIClockSource\n
+  *         CCIPR9     SPI4SEL         LL_RCC_GetSPIClockSource\n
+  *         CCIPR9     SPI5SEL         LL_RCC_GetSPIClockSource\n
+  *         CCIPR9     SPI6SEL         LL_RCC_GetSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC8
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll CCIPR13        USART1SEL      LL_RCC_GetUSARTClockSource\n
+  *         CCIPR13        USART2SEL      LL_RCC_GetUSARTClockSource\n
+  *         CCIPR13        USART3SEL      LL_RCC_GetUSARTClockSource\n
+  *         CCIPR13        USART6SEL      LL_RCC_GetUSARTClockSource\n
+  *         CCIPR14        USART10SEL     LL_RCC_GetUSARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll CCIPR13        UART4SEL      LL_RCC_GetUARTClockSource\n
+  *         CCIPR13        UART5SEL      LL_RCC_GetUARTClockSource\n
+  *         CCIPR13        UART7SEL      LL_RCC_GetUARTClockSource\n
+  *         CCIPR13        UART8SEL      LL_RCC_GetUARTClockSource\n
+  *         CCIPR14        UART9SEL      LL_RCC_GetUARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC9
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_IC14
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_MSI
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get USB clock source
+  * @rmtoll CCIPR6      OTGPHY1SEL        LL_RCC_GetUSBClockSource\n
+  *         CCIPR6      OTGPHY1CKREFSEL   LL_RCC_GetUSBClockSource\n
+  *         CCIPR6      OTGPHY2SEL        LL_RCC_GetUSBClockSource\n
+  *         CCIPR6      OTGPHY2CKREFSEL   LL_RCC_GetUSBClockSource\n
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_IC15
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+
+/**
+  * @brief  Get XSPI Kernel clock source
+  * @rmtoll CCIPR6      XSPI1SEL        LL_RCC_GetXSPIClockSource\n
+  *         CCIPR6      XSPI2SEL        LL_RCC_GetXSPIClockSource\n
+  *         CCIPR6      XSPI3SEL        LL_RCC_GetXSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE_IC4
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC3
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE_IC4
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetXSPIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *         set).
+  * @rmtoll CCIPR7         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll CCIPR7       RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll APB4ENSR1    RTCENS        LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  WRITE_REG(RCC->APB4ENSR1, RCC_APB4ENSR1_RTCENS);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll APB4ENCR1    RTCENC        LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  WRITE_REG(RCC->APB4ENCR1, RCC_APB4ENCR1_RTCENC);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll APB4ENR1       RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return ((READ_BIT(RCC->APB4ENR1, RCC_APB4ENR1_RTCEN) == (RCC_APB4ENR1_RTCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         VSWRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         VSWRST          LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
+}
+
+/**
+  * @brief  Set HSE Prescaler for RTC Clock
+  * @rmtoll CCIPR7       RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_1
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_RTCPRE, Prescaler);
+}
+
+/**
+  * @brief  Get HSE Prescaler for RTC Clock
+  * @rmtoll CCIPR7       RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_1
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+  * @{
+  */
+
+/**
+  * @brief  Set Timers Clock Prescalers
+  * @rmtoll CFGR2          TIMPRE        LL_RCC_SetTIMPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_1
+  *         @arg @ref LL_RCC_TIM_PRESCALER_2
+  *         @arg @ref LL_RCC_TIM_PRESCALER_4
+  *         @arg @ref LL_RCC_TIM_PRESCALER_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_TIMPRE, Prescaler << RCC_CFGR2_TIMPRE_Pos);
+}
+
+/**
+  * @brief  Get Timers Clock Prescalers
+  * @rmtoll CFGR2          TIMPRE        LL_RCC_GetTIMPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_1
+  *         @arg @ref LL_RCC_TIM_PRESCALER_2
+  *         @arg @ref LL_RCC_TIM_PRESCALER_4
+  *         @arg @ref LL_RCC_TIM_PRESCALER_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_TIMPRE) >> RCC_CFGR2_TIMPRE_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Set the oscillator used as PLL clock source.
+  * @note   PLL1SEL can be written only when All PLLs are disabled.
+  * @rmtoll PLL1CFGR1      PLL1SEL        LL_RCC_PLL1_SetSource
+  * @param  PLLSource parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1SEL, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLL1CFGR1      PLL1SEL        LL_RCC_PLL1_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1SEL));
+}
+
+/**
+  * @brief  Enable PLL1
+  * @rmtoll CSR          PLL1ONS         LL_RCC_PLL1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS);
+}
+
+/**
+  * @brief  Disable PLL1
+  * @note Cannot be disabled if the PLL1 clock is used as the system clock
+  * @rmtoll CCR          PLL1ONC         LL_RCC_PLL1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC);
+}
+
+/**
+  * @brief  Check if PLL1 Ready
+  * @rmtoll SR           PLL1RDY         LL_RCC_PLL1_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_PLL1RDY) == (RCC_SR_PLL1RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL1 bypass (PLL1 output is driven by the PLL1 reference clock)
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR1    PLL1BYP         LL_RCC_PLL1_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_EnableBypass(void)
+{
+  SET_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP);
+}
+
+/**
+  * @brief  Disable PLL1 bypass (PLL1 output is driven by the VCO)
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR1    PLL1BYP         LL_RCC_PLL1_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP);
+}
+
+/**
+  * @brief  Check if PLL1 bypass is enabled
+  * @rmtoll PLL1CFGR1    PLL1BYP         LL_RCC_PLL1_IsEnabledBypass
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledBypass(void)
+{
+  return ((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1BYP) == RCC_PLL1CFGR1_PLL1BYP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Assert PLL1 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1MODSSRST    LL_RCC_PLL1_AssertModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_AssertModulationSpreadSpectrumReset(void)
+{
+  SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST);
+}
+
+/**
+  * @brief  Release PLL1 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1MODSSRST    LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_ReleaseModulationSpreadSpectrumReset(void)
+{
+  CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSRST);
+}
+
+/**
+  * @brief  Enable PLL1 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1DACEN       LL_RCC_PLL1_EnableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_EnableDAC(void)
+{
+  SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN);
+}
+
+/**
+  * @brief  Disable PLL1 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1DACEN     LL_RCC_PLL1_DisableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_DisableDAC(void)
+{
+  CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN);
+}
+
+/**
+  * @brief  Check if PLL1 noise canceling DAC in fractional mode is enabled
+  * @rmtoll PLL1CFGR3    PLL1DACEN     LL_RCC_PLL1_IsEnabledDAC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDAC(void)
+{
+  return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1DACEN) == RCC_PLL1CFGR3_PLL1DACEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL1 modulation spread-spectrum with fractional divide inactive
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1MODSSDIS    LL_RCC_PLL1_EnableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_EnableModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS);
+}
+
+/**
+  * @brief  Disable PLL1 modulation spread-spectrum but active fractional divide
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1MODSSDIS    LL_RCC_PLL1_DisableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_DisableModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS);
+}
+
+/**
+  * @brief  Check if PLL1 modulation spread-spectrum and inactive fractional divide is enabled
+  * @rmtoll PLL1CFGR3    PLL1MODSSDIS    LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODSSDIS) == 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL1 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1MODDSEN     LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN);
+}
+
+/**
+  * @brief  Disable PLL1 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1MODDSEN     LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN);
+}
+
+/**
+  * @brief  Check if PLL1 fractional divide and modulation spread-spectrum is enabled
+  * @rmtoll PLL1CFGR3    PLL1MODDSEN     LL_RCC_PLL1_IsEnabledFractionalModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledFractionalModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1MODDSEN) == RCC_PLL1CFGR3_PLL1MODDSEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL1 DIVN Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR1    PLL1DIVN        LL_RCC_PLL1_SetN
+  * @param  N  In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN, N << RCC_PLL1CFGR1_PLL1DIVN_Pos);
+}
+
+/**
+  * @brief  Get PLL1 DIVN Coefficient
+  * @rmtoll PLL1CFGR1    PLL1DIVN        LL_RCC_PLL1_GetN
+  * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos));
+}
+
+/**
+  * @brief  Set PLL1 DIVM Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR1    PLL1DIVM        LL_RCC_PLL1_SetM
+  * @param  M parameter can be a value between 1 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM, M << RCC_PLL1CFGR1_PLL1DIVM_Pos);
+}
+
+/**
+  * @brief  Get PLL1 DIVM Coefficient
+  * @rmtoll PLL1CFGR1    PLL1DIVM        LL_RCC_PLL1_GetM
+  * @retval A value between 1 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos);
+}
+
+/**
+  * @brief  Set PLL1 PDIV1 Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1PDIV1       LL_RCC_PLL1_SetP1
+  * @param  P1 parameter can be a value between 1 and 7 when PLL1 is enabled, 0 when disabled
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetP1(uint32_t P1)
+{
+  MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV1, P1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos);
+}
+
+/**
+  * @brief  Get PLL1 PDIV2 Coefficient
+  * @rmtoll PLL1CFGR3    PLL1PDIV1       LL_RCC_PLL1_GetP1
+  * @retval A value between 0 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP1(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 PDIV2 Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3    PLL1PDIV2       LL_RCC_PLL1_SetP2
+  * @param  P2 parameter can be a value between 1 and 7
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetP2(uint32_t P2)
+{
+  MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2, P2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos);
+}
+
+/**
+  * @brief  Get PLL1 PDIV2 Coefficient
+  * @rmtoll PLL1CFGR3    PLL1PDIV2       LL_RCC_PLL1_GetP2
+  * @retval A value between 1 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP2(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos);
+}
+
+/**
+  * @brief  Enable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3           PLL1PDIVEN         LL_RCC_PLL1P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
+{
+  SET_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN);
+}
+
+/**
+  * @brief  Disable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR3           PLL1PDIVEN         LL_RCC_PLL1P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN);
+}
+
+/**
+  * @brief  Check if PLL1 P is enabled
+  * @rmtoll PLL1CFGR3           PLL1PDIVEN         LL_RCC_PLL1P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIVEN) == RCC_PLL1CFGR3_PLL1PDIVEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL1 FRACN Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1CFGR2        PLL1DIVNFRAC    LL_RCC_PLL1_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC, FRACN << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Get PLL1 FRACN Coefficient
+  * @rmtoll PLL1CFGR2        PLL1DIVNFRAC    LL_RCC_PLL1_GetFRACN
+  * @retval A value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Set the oscillator used as PLL clock source.
+  * @note   PLL2SEL can be written only when All PLLs are disabled.
+  * @rmtoll PLL2CFGR1      PLL2SEL        LL_RCC_PLL2_SetSource
+  * @param  PLLSource parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLL2CFGR1      PLL2SEL        LL_RCC_PLL2_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL));
+}
+
+/**
+  * @brief  Enable PLL2
+  * @rmtoll CSR          PLL2ONS         LL_RCC_PLL2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_PLL2ONS);
+}
+
+/**
+  * @brief  Disable PLL2
+  * @note Cannot be disabled if the PLL2 clock is used as the system clock
+  * @rmtoll CCR          PLL2ONC         LL_RCC_PLL2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_PLL2ONC);
+}
+
+/**
+  * @brief  Check if PLL2 Ready
+  * @rmtoll SR           PLL2RDY         LL_RCC_PLL2_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_PLL2RDY) == (RCC_SR_PLL2RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL2 bypass (PLL2 output is driven by the PLL2 reference clock)
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR1    PLL2BYP         LL_RCC_PLL2_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_EnableBypass(void)
+{
+  SET_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP);
+}
+
+/**
+  * @brief  Disable PLL2 bypass (PLL2 output is driven by the VCO)
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR1    PLL2BYP         LL_RCC_PLL2_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP);
+}
+
+/**
+  * @brief  Check if PLL2 bypass is enabled
+  * @rmtoll PLL2CFGR1    PLL2BYP         LL_RCC_PLL2_IsEnabledBypass
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledBypass(void)
+{
+  return ((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP) == RCC_PLL2CFGR1_PLL2BYP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Assert PLL2 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2MODSSRST    LL_RCC_PLL2_AssertModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_AssertModulationSpreadSpectrumReset(void)
+{
+  SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST);
+}
+
+/**
+  * @brief  Release PLL2 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2MODSSRST    LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset(void)
+{
+  CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST);
+}
+
+/**
+  * @brief  Enable PLL2 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2DACEN       LL_RCC_PLL2_EnableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_EnableDAC(void)
+{
+  SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN);
+}
+
+/**
+  * @brief  Disable PLL2 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2DACEN     LL_RCC_PLL2_DisableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_DisableDAC(void)
+{
+  CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN);
+}
+
+/**
+  * @brief  Check if PLL2 noise canceling DAC in fractional mode is enabled
+  * @rmtoll PLL2CFGR3    PLL2DACEN     LL_RCC_PLL2_IsEnabledDAC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDAC(void)
+{
+  return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN) == RCC_PLL2CFGR3_PLL2DACEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL2 modulation spread-spectrum with fractional divide inactive
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2MODSSDIS    LL_RCC_PLL2_EnableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_EnableModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS);
+}
+
+/**
+  * @brief  Disable PLL2 modulation spread-spectrum but active fractional divide
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2MODSSDIS    LL_RCC_PLL2_DisableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_DisableModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS);
+}
+
+/**
+  * @brief  Check if PLL2 modulation spread-spectrum and inactive fractional divide is enabled
+  * @rmtoll PLL2CFGR3    PLL2MODSSDIS    LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS) == 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL2 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2MODDSEN     LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN);
+}
+
+/**
+  * @brief  Disable PLL2 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2MODDSEN     LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN);
+}
+
+/**
+  * @brief  Check if PLL2 fractional divide and modulation spread-spectrum is enabled
+  * @rmtoll PLL2CFGR3    PLL2MODDSEN     LL_RCC_PLL2_IsEnabledFractionalModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledFractionalModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN) == RCC_PLL2CFGR3_PLL2MODDSEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL2 DIVN Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR1    PLL2DIVN        LL_RCC_PLL2_SetN
+  * @param  N  In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN, N << RCC_PLL2CFGR1_PLL2DIVN_Pos);
+}
+
+/**
+  * @brief  Get PLL2 DIVN Coefficient
+  * @rmtoll PLL2CFGR1    PLL2DIVN        LL_RCC_PLL2_GetN
+  * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos));
+}
+
+/**
+  * @brief  Set PLL2 DIVM Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR1    PLL2DIVM        LL_RCC_PLL2_SetM
+  * @param  M parameter can be a value between 1 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM, M << RCC_PLL2CFGR1_PLL2DIVM_Pos);
+}
+
+/**
+  * @brief  Get PLL2 DIVM Coefficient
+  * @rmtoll PLL2CFGR1    PLL2DIVM        LL_RCC_PLL2_GetM
+  * @retval A value between 1 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos);
+}
+
+/**
+  * @brief  Set PLL2 PDIV1 Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2PDIV1       LL_RCC_PLL2_SetP1
+  * @param  P1 parameter can be a value between 1 and 7 when PLL2 is enabled, 0 when disabled
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetP1(uint32_t P1)
+{
+  MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1, P1 << RCC_PLL2CFGR3_PLL2PDIV1_Pos);
+}
+
+/**
+  * @brief  Get PLL2 PDIV2 Coefficient
+  * @rmtoll PLL2CFGR3    PLL2PDIV1       LL_RCC_PLL2_GetP1
+  * @retval A value between 0 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP1(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos);
+}
+
+/**
+  * @brief  Set PLL2 PDIV2 Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3    PLL2PDIV2       LL_RCC_PLL2_SetP2
+  * @param  P2 parameter can be a value between 1 and 7
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetP2(uint32_t P2)
+{
+  MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV2, P2 << RCC_PLL2CFGR3_PLL2PDIV2_Pos);
+}
+
+/**
+  * @brief  Get PLL2 PDIV2 Coefficient
+  * @rmtoll PLL2CFGR3    PLL2PDIV2       LL_RCC_PLL2_GetP2
+  * @retval A value between 1 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP2(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos);
+}
+
+/**
+  * @brief  Enable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3           PLL2PDIVEN         LL_RCC_PLL2P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
+{
+  SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN);
+}
+
+/**
+  * @brief  Disable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR3           PLL2PDIVEN         LL_RCC_PLL2P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN);
+}
+
+/**
+  * @brief  Check if PLL2 P is enabled
+  * @rmtoll PLL2CFGR3           PLL2PDIVEN         LL_RCC_PLL2P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2PDIVEN) == RCC_PLL2CFGR3_PLL2PDIVEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL2 FRACN Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2CFGR2        PLL2DIVNFRAC    LL_RCC_PLL2_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC, FRACN << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Get PLL2 FRACN Coefficient
+  * @rmtoll PLL2CFGR2        PLL2DIVNFRAC    LL_RCC_PLL2_GetFRACN
+  * @retval A value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Set the oscillator used as PLL clock source.
+  * @note   PLL3SEL can be written only when All PLLs are disabled.
+  * @rmtoll PLL3CFGR1      PLL3SEL        LL_RCC_PLL3_SetSource
+  * @param  PLLSource parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3SEL, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLL3CFGR1      PLL3SEL        LL_RCC_PLL3_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3SEL));
+}
+
+/**
+  * @brief  Enable PLL3
+  * @rmtoll CSR          PLL3ONS         LL_RCC_PLL3_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_PLL3ONS);
+}
+
+/**
+  * @brief  Disable PLL3
+  * @note Cannot be disabled if the PLL3 clock is used as the system clock
+  * @rmtoll CCR          PLL3ONC         LL_RCC_PLL3_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_PLL3ONC);
+}
+
+/**
+  * @brief  Check if PLL3 Ready
+  * @rmtoll SR           PLL3RDY         LL_RCC_PLL3_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_PLL3RDY) == (RCC_SR_PLL3RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL3 bypass (PLL3 output is driven by the PLL3 reference clock)
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR1    PLL3BYP         LL_RCC_PLL3_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_EnableBypass(void)
+{
+  SET_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP);
+}
+
+/**
+  * @brief  Disable PLL3 bypass (PLL3 output is driven by the VCO)
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR1    PLL3BYP         LL_RCC_PLL3_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP);
+}
+
+/**
+  * @brief  Check if PLL3 bypass is enabled
+  * @rmtoll PLL3CFGR1    PLL3BYP         LL_RCC_PLL3_IsEnabledBypass
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledBypass(void)
+{
+  return ((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3BYP) == RCC_PLL3CFGR1_PLL3BYP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Assert PLL3 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3MODSSRST    LL_RCC_PLL3_AssertModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_AssertModulationSpreadSpectrumReset(void)
+{
+  SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSRST);
+}
+
+/**
+  * @brief  Release PLL3 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3MODSSRST    LL_RCC_PLL3_ReleaseModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_ReleaseModulationSpreadSpectrumReset(void)
+{
+  CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSRST);
+}
+
+/**
+  * @brief  Enable PLL3 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3DACEN       LL_RCC_PLL3_EnableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_EnableDAC(void)
+{
+  SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN);
+}
+
+/**
+  * @brief  Disable PLL3 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3DACEN     LL_RCC_PLL3_DisableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_DisableDAC(void)
+{
+  CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN);
+}
+
+/**
+  * @brief  Check if PLL3 noise canceling DAC in fractional mode is enabled
+  * @rmtoll PLL3CFGR3    PLL3DACEN     LL_RCC_PLL3_IsEnabledDAC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDAC(void)
+{
+  return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3DACEN) == RCC_PLL3CFGR3_PLL3DACEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL3 modulation spread-spectrum with fractional divide inactive
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3MODSSDIS    LL_RCC_PLL3_EnableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_EnableModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS);
+}
+
+/**
+  * @brief  Disable PLL3 modulation spread-spectrum but active fractional divide
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3MODSSDIS    LL_RCC_PLL3_DisableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_DisableModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS);
+}
+
+/**
+  * @brief  Check if PLL3 modulation spread-spectrum and inactive fractional divide is enabled
+  * @rmtoll PLL3CFGR3    PLL3MODSSDIS    LL_RCC_PLL3_IsEnabledModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODSSDIS) == 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL3 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3MODDSEN     LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN);
+}
+
+/**
+  * @brief  Disable PLL3 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3MODDSEN     LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN);
+}
+
+/**
+  * @brief  Check if PLL3 fractional divide and modulation spread-spectrum is enabled
+  * @rmtoll PLL3CFGR3    PLL3MODDSEN     LL_RCC_PLL3_IsEnabledFractionalModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledFractionalModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3MODDSEN) == RCC_PLL3CFGR3_PLL3MODDSEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL3 DIVN Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR1    PLL3DIVN        LL_RCC_PLL3_SetN
+  * @param  N  In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN, N << RCC_PLL3CFGR1_PLL3DIVN_Pos);
+}
+
+/**
+  * @brief  Get PLL3 DIVN Coefficient
+  * @rmtoll PLL3CFGR1    PLL3DIVN        LL_RCC_PLL3_GetN
+  * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos));
+}
+
+/**
+  * @brief  Set PLL3 DIVM Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR1    PLL3DIVM        LL_RCC_PLL3_SetM
+  * @param  M parameter can be a value between 1 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM, M << RCC_PLL3CFGR1_PLL3DIVM_Pos);
+}
+
+/**
+  * @brief  Get PLL3 DIVM Coefficient
+  * @rmtoll PLL3CFGR1    PLL3DIVM        LL_RCC_PLL3_GetM
+  * @retval A value between 1 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3CFGR1, RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos);
+}
+
+/**
+  * @brief  Set PLL3 PDIV1 Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3PDIV1       LL_RCC_PLL3_SetP1
+  * @param  P1 parameter can be a value between 1 and 7 when PLL3 is enabled, 0 when disabled
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetP1(uint32_t P1)
+{
+  MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1, P1 << RCC_PLL3CFGR3_PLL3PDIV1_Pos);
+}
+
+/**
+  * @brief  Get PLL3 PDIV2 Coefficient
+  * @rmtoll PLL3CFGR3    PLL3PDIV1       LL_RCC_PLL3_GetP1
+  * @retval A value between 1 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP1(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos);
+}
+
+/**
+  * @brief  Set PLL3 PDIV2 Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3    PLL3PDIV2       LL_RCC_PLL3_SetP2
+  * @param  P2 parameter can be a value between 0 and 7
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetP2(uint32_t P2)
+{
+  MODIFY_REG(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2, P2 << RCC_PLL3CFGR3_PLL3PDIV2_Pos);
+}
+
+/**
+  * @brief  Get PLL3 PDIV2 Coefficient
+  * @rmtoll PLL3CFGR3    PLL3PDIV2       LL_RCC_PLL3_GetP2
+  * @retval A value between 1 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP2(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos);
+}
+
+/**
+  * @brief  Enable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3           PLL3PDIVEN         LL_RCC_PLL3P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
+{
+  SET_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN);
+}
+
+/**
+  * @brief  Disable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR3           PLL3PDIVEN         LL_RCC_PLL3P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN);
+}
+
+/**
+  * @brief  Check if PLL3 P is enabled
+  * @rmtoll PLL3CFGR3           PLL3PDIVEN         LL_RCC_PLL3P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLL3CFGR3, RCC_PLL3CFGR3_PLL3PDIVEN) == RCC_PLL3CFGR3_PLL3PDIVEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL3 FRACN Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3CFGR2        PLL3DIVNFRAC    LL_RCC_PLL3_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC, FRACN << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Get PLL3 FRACN Coefficient
+  * @rmtoll PLL3CFGR2        PLL3DIVNFRAC    LL_RCC_PLL3_GetFRACN
+  * @retval A value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Set the oscillator used as PLL clock source.
+  * @note   PLL4SEL can be written only when All PLLs are disabled.
+  * @rmtoll PLL4CFGR1      PLL4SEL        LL_RCC_PLL4_SetSource
+  * @param  PLLSource parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_SetSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLL4CFGR1      PLL4SEL        LL_RCC_PLL4_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_MSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_I2S_CKIN
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL));
+}
+
+/**
+  * @brief  Enable PLL4
+  * @rmtoll CSR          PLL4ONS         LL_RCC_PLL4_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_Enable(void)
+{
+  WRITE_REG(RCC->CSR, RCC_CSR_PLL4ONS);
+}
+
+/**
+  * @brief  Disable PLL4
+  * @note Cannot be disabled if the PLL4 clock is used as the system clock
+  * @rmtoll CCR          PLL4ONC         LL_RCC_PLL4_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_Disable(void)
+{
+  WRITE_REG(RCC->CCR, RCC_CCR_PLL4ONC);
+}
+
+/**
+  * @brief  Check if PLL4 Ready
+  * @rmtoll SR           PLL4RDY         LL_RCC_PLL4_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_IsReady(void)
+{
+  return ((READ_BIT(RCC->SR, RCC_SR_PLL4RDY) == (RCC_SR_PLL4RDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL4 bypass (PLL4 output is driven by the PLL4 reference clock)
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR1    PLL4BYP         LL_RCC_PLL4_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_EnableBypass(void)
+{
+  SET_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP);
+}
+
+/**
+  * @brief  Disable PLL4 bypass (PLL4 output is driven by the VCO)
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR1    PLL4BYP         LL_RCC_PLL4_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP);
+}
+
+/**
+  * @brief  Check if PLL4 bypass is enabled
+  * @rmtoll PLL4CFGR1    PLL4BYP         LL_RCC_PLL4_IsEnabledBypass
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledBypass(void)
+{
+  return ((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP) == RCC_PLL4CFGR1_PLL4BYP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Assert PLL4 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4MODSSRST    LL_RCC_PLL4_AssertModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_AssertModulationSpreadSpectrumReset(void)
+{
+  SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST);
+}
+
+/**
+  * @brief  Release PLL4 modulation spread-spectrum reset
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4MODSSRST    LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_ReleaseModulationSpreadSpectrumReset(void)
+{
+  CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSRST);
+}
+
+/**
+  * @brief  Enable PLL4 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4DACEN       LL_RCC_PLL4_EnableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_EnableDAC(void)
+{
+  SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN);
+}
+
+/**
+  * @brief  Disable PLL4 noise canceling DAC in fractional mode
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4DACEN     LL_RCC_PLL4_DisableDAC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_DisableDAC(void)
+{
+  CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN);
+}
+
+/**
+  * @brief  Check if PLL4 noise canceling DAC in fractional mode is enabled
+  * @rmtoll PLL4CFGR3    PLL4DACEN     LL_RCC_PLL4_IsEnabledDAC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledDAC(void)
+{
+  return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4DACEN) == RCC_PLL4CFGR3_PLL4DACEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL4 modulation spread-spectrum with fractional divide inactive
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4MODSSDIS    LL_RCC_PLL4_EnableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_EnableModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS);
+}
+
+/**
+  * @brief  Disable PLL4 modulation spread-spectrum but active fractional divide
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4MODSSDIS    LL_RCC_PLL4_DisableModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_DisableModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS);
+}
+
+/**
+  * @brief  Check if PLL4 modulation spread-spectrum and inactive fractional divide is enabled
+  * @rmtoll PLL4CFGR3    PLL4MODSSDIS    LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODSSDIS) == 0UL) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable PLL4 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4MODDSEN     LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum(void)
+{
+  SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN);
+}
+
+/**
+  * @brief  Disable PLL4 fractional divide and modulation spread-spectrum
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4MODDSEN     LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum(void)
+{
+  CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN);
+}
+
+/**
+  * @brief  Check if PLL4 fractional divide and modulation spread-spectrum is enabled
+  * @rmtoll PLL4CFGR3    PLL4MODDSEN     LL_RCC_PLL4_IsEnabledFractionalModulationSpreadSpectrum
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_IsEnabledFractionalModulationSpreadSpectrum(void)
+{
+  return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4MODDSEN) == RCC_PLL4CFGR3_PLL4MODDSEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL4 DIVN Coefficient
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR1    PLL4DIVN        LL_RCC_PLL4_SetN
+  * @param  N  In integer mode, N parameter can be a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, N parameter can be a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE void LL_RCC_PLL4_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN, N << RCC_PLL4CFGR1_PLL4DIVN_Pos);
+}
+
+/**
+  * @brief  Get PLL4 DIVN Coefficient
+  * @rmtoll PLL4CFGR1    PLL4DIVN        LL_RCC_PLL4_GetN
+  * @retval In integer mode, a value between 16 (0x10) and 2500 (0x9C4).
+  *         In fractional mode, a value between 20 (0x14) and 500 (0x1F4).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos));
+}
+
+/**
+  * @brief  Set PLL4 DIVM Coefficient
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR1    PLL4DIVM        LL_RCC_PLL4_SetM
+  * @param  M parameter can be a value between 1 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL4_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM, M << RCC_PLL4CFGR1_PLL4DIVM_Pos);
+}
+
+/**
+  * @brief  Get PLL4 DIVM Coefficient
+  * @rmtoll PLL4CFGR1    PLL4DIVM        LL_RCC_PLL4_GetM
+  * @retval A value between 1 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos);
+}
+
+/**
+  * @brief  Set PLL4 PDIV1 Coefficient
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4PDIV1       LL_RCC_PLL4_SetP1
+  * @param  P1 parameter can be a value between 1 and 7 when PLL4 is enabled, 0 when disabled
+  */
+__STATIC_INLINE void LL_RCC_PLL4_SetP1(uint32_t P1)
+{
+  MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1, P1 << RCC_PLL4CFGR3_PLL4PDIV1_Pos);
+}
+
+/**
+  * @brief  Get PLL4 PDIV2 Coefficient
+  * @rmtoll PLL4CFGR3    PLL4PDIV1       LL_RCC_PLL4_GetP1
+  * @retval A value between 0 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_GetP1(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos);
+}
+
+/**
+  * @brief  Set PLL4 PDIV2 Coefficient
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3    PLL4PDIV2       LL_RCC_PLL4_SetP2
+  * @param  P2 parameter can be a value between 1 and 7
+  */
+__STATIC_INLINE void LL_RCC_PLL4_SetP2(uint32_t P2)
+{
+  MODIFY_REG(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2, P2 << RCC_PLL4CFGR3_PLL4PDIV2_Pos);
+}
+
+/**
+  * @brief  Get PLL4 PDIV2 Coefficient
+  * @rmtoll PLL4CFGR3    PLL4PDIV2       LL_RCC_PLL4_GetP2
+  * @retval A value between 1 and 7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_GetP2(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos);
+}
+
+/**
+  * @brief  Enable PLL4P
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3           PLL4PDIVEN         LL_RCC_PLL4P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4P_Enable(void)
+{
+  SET_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN);
+}
+
+/**
+  * @brief  Disable PLL4P
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR3           PLL4PDIVEN         LL_RCC_PLL4P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL4P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN);
+}
+
+/**
+  * @brief  Check if PLL4 P is enabled
+  * @rmtoll PLL4CFGR3           PLL4PDIVEN         LL_RCC_PLL4P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLL4CFGR3, RCC_PLL4CFGR3_PLL4PDIVEN) == RCC_PLL4CFGR3_PLL4PDIVEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set PLL4 FRACN Coefficient
+  * @note   This API shall be called only when PLL4 is disabled.
+  * @rmtoll PLL4CFGR2        PLL4DIVNFRAC    LL_RCC_PLL4_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL4_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC, FRACN << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Get PLL4 FRACN Coefficient
+  * @rmtoll PLL4CFGR2        PLL4DIVNFRAC    LL_RCC_PLL4_GetFRACN
+  * @retval A value between 0 and 2^24 (0xFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL4_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos);
+}
+
+/**
+  * @brief  Enable IC1
+  * @rmtoll DIVENSR      IC1ENS        LL_RCC_IC1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC1_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC1ENS);
+}
+
+/**
+  * @brief  Disable IC1
+  * @rmtoll DIVENCR      IC1ENC        LL_RCC_IC1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC1_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC1ENC);
+}
+
+/**
+  * @brief  Check if IC1 is enabled
+  * @rmtoll DIVENR       IC1EN         LL_RCC_IC1_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC1_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC1EN) == RCC_DIVENR_IC1EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC1 clock source.
+  * @rmtoll IC1CFGR      IC1SEL        LL_RCC_IC1_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC1_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC1 clock source.
+  * @rmtoll IC1CFGR      IC1SEL        LL_RCC_IC1_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC1_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC1CFGR      IC1INT        LL_RCC_IC1_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC1_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT, (Divider - 1UL) << RCC_IC1CFGR_IC1INT_Pos);
+}
+
+/**
+  * @brief  Get IC1 divider
+  * @rmtoll IC1CFGR      IC1INT        LL_RCC_IC1_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC1_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC2
+  * @rmtoll DIVENSR       IC2ENS        LL_RCC_IC2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC2_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC2ENS);
+}
+
+/**
+  * @brief  Disable IC2
+  * @rmtoll DIVENCR       IC2ENC        LL_RCC_IC2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC2_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC2ENC);
+}
+
+/**
+  * @brief  Check if IC2 is enabled
+  * @rmtoll DIVENR       IC2EN         LL_RCC_IC2_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC2_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC2EN) == RCC_DIVENR_IC2EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC2 clock source.
+  * @rmtoll IC2CFGR      IC2SEL        LL_RCC_IC2_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC2_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC2CFGR, RCC_IC2CFGR_IC2SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC2 clock source.
+  * @rmtoll IC2CFGR      IC2SEL        LL_RCC_IC2_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC2_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC2CFGR, RCC_IC2CFGR_IC2SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC2CFGR      IC2INT        LL_RCC_IC2_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC2_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC2CFGR, RCC_IC2CFGR_IC2INT, (Divider - 1UL) << RCC_IC2CFGR_IC2INT_Pos);
+}
+
+/**
+  * @brief  Get IC2 divider
+  * @rmtoll IC2CFGR      IC2INT        LL_RCC_IC2_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC2_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC2CFGR, RCC_IC2CFGR_IC2INT) >> RCC_IC2CFGR_IC2INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC3
+  * @rmtoll DIVENSR       IC3ENS        LL_RCC_IC3_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC3_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC3ENS);
+}
+
+/**
+  * @brief  Disable IC3
+  * @rmtoll DIVENCR       IC3ENC        LL_RCC_IC3_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC3_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC3ENC);
+}
+
+/**
+  * @brief  Check if IC3 is enabled
+  * @rmtoll DIVENR       IC3EN         LL_RCC_IC3_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC3_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC3EN) == RCC_DIVENR_IC3EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC3 clock source.
+  * @rmtoll IC3CFGR      IC3SEL        LL_RCC_IC3_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC3_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC3 clock source.
+  * @rmtoll IC3CFGR      IC3SEL        LL_RCC_IC3_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC3_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC3CFGR      IC3INT        LL_RCC_IC3_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC3_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3INT, (Divider - 1UL) << RCC_IC3CFGR_IC3INT_Pos);
+}
+
+/**
+  * @brief  Get IC3 divider
+  * @rmtoll IC3CFGR      IC3INT        LL_RCC_IC3_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC3_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC3CFGR, RCC_IC3CFGR_IC3INT) >> RCC_IC3CFGR_IC3INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC4
+  * @rmtoll DIVENSR       IC4ENS        LL_RCC_IC4_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC4_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC4ENS);
+}
+
+/**
+  * @brief  Disable IC4
+  * @rmtoll DIVENCR       IC4ENC        LL_RCC_IC4_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC4_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC4ENC);
+}
+
+/**
+  * @brief  Check if IC4 is enabled
+  * @rmtoll DIVENR       IC4EN         LL_RCC_IC4_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC4_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC4EN) == RCC_DIVENR_IC4EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC4 clock source.
+  * @rmtoll IC4CFGR      IC4SEL        LL_RCC_IC4_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC4_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC4 clock source.
+  * @rmtoll IC4CFGR      IC4SEL        LL_RCC_IC4_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC4_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC4CFGR      IC4INT        LL_RCC_IC4_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC4_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4INT, (Divider - 1UL) << RCC_IC4CFGR_IC4INT_Pos);
+}
+
+/**
+  * @brief  Get IC4 divider
+  * @rmtoll IC4CFGR      IC4INT        LL_RCC_IC4_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC4_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC4CFGR, RCC_IC4CFGR_IC4INT) >> RCC_IC4CFGR_IC4INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC5
+  * @rmtoll DIVENSR       IC5ENS        LL_RCC_IC5_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC5_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC5ENS);
+}
+
+/**
+  * @brief  Disable IC5
+  * @rmtoll DIVENCR       IC5ENC        LL_RCC_IC5_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC5_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC5ENC);
+}
+
+/**
+  * @brief  Check if IC5 is enabled
+  * @rmtoll DIVENR       IC5EN         LL_RCC_IC5_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC5_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC5EN) == RCC_DIVENR_IC5EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC5 clock source.
+  * @rmtoll IC5CFGR      IC5SEL        LL_RCC_IC5_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC5_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC5 clock source.
+  * @rmtoll IC5CFGR      IC5SEL        LL_RCC_IC5_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC5_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC5CFGR      IC5INT        LL_RCC_IC5_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC5_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5INT, (Divider - 1UL) << RCC_IC5CFGR_IC5INT_Pos);
+}
+
+/**
+  * @brief  Get IC5 divider
+  * @rmtoll IC5CFGR      IC5INT        LL_RCC_IC5_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC5_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC5CFGR, RCC_IC5CFGR_IC5INT) >> RCC_IC5CFGR_IC5INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC6
+  * @rmtoll DIVENSR       IC6ENS        LL_RCC_IC6_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC6_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC6ENS);
+}
+
+/**
+  * @brief  Disable IC6
+  * @rmtoll DIVENCR       IC6ENC        LL_RCC_IC6_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC6_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC6ENC);
+}
+
+/**
+  * @brief  Check if IC6 is enabled
+  * @rmtoll DIVENR       IC6EN         LL_RCC_IC6_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC6_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC6EN) == RCC_DIVENR_IC6EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC6 clock source.
+  * @rmtoll IC6CFGR      IC6SEL        LL_RCC_IC6_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC6_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC6CFGR, RCC_IC6CFGR_IC6SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC6 clock source.
+  * @rmtoll IC6CFGR      IC6SEL        LL_RCC_IC6_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC6_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC6CFGR, RCC_IC6CFGR_IC6SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC6CFGR      IC6INT        LL_RCC_IC6_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC6_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC6CFGR, RCC_IC6CFGR_IC6INT, (Divider - 1UL) << RCC_IC6CFGR_IC6INT_Pos);
+}
+
+/**
+  * @brief  Get IC6 divider
+  * @rmtoll IC6CFGR      IC6INT        LL_RCC_IC6_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC6_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC6CFGR, RCC_IC6CFGR_IC6INT) >> RCC_IC6CFGR_IC6INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC7
+  * @rmtoll DIVENSR       IC7ENS        LL_RCC_IC7_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC7_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC7ENS);
+}
+
+/**
+  * @brief  Disable IC7
+  * @rmtoll DIVENCR       IC7ENC        LL_RCC_IC7_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC7_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC7ENC);
+}
+
+/**
+  * @brief  Check if IC7 is enabled
+  * @rmtoll DIVENR       IC7EN         LL_RCC_IC7_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC7_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC7EN) == RCC_DIVENR_IC7EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC7 clock source.
+  * @rmtoll IC7CFGR      IC7SEL        LL_RCC_IC7_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC7_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC7 clock source.
+  * @rmtoll IC7CFGR      IC7SEL        LL_RCC_IC7_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC7_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC7CFGR      IC7INT        LL_RCC_IC7_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC7_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7INT, (Divider - 1UL) << RCC_IC7CFGR_IC7INT_Pos);
+}
+
+/**
+  * @brief  Get IC7 divider
+  * @rmtoll IC7CFGR      IC7INT        LL_RCC_IC7_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC7_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC7CFGR, RCC_IC7CFGR_IC7INT) >> RCC_IC7CFGR_IC7INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC8
+  * @rmtoll DIVENSR       IC8ENS        LL_RCC_IC8_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC8_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC8ENS);
+}
+
+/**
+  * @brief  Disable IC8
+  * @rmtoll DIVENCR       IC8ENC        LL_RCC_IC8_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC8_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC8ENC);
+}
+
+/**
+  * @brief  Check if IC8 is enabled
+  * @rmtoll DIVENR       IC8EN         LL_RCC_IC8_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC8_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC8EN) == RCC_DIVENR_IC8EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC8 clock source.
+  * @rmtoll IC8CFGR      IC8SEL        LL_RCC_IC8_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC8_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC8 clock source.
+  * @rmtoll IC8CFGR      IC8SEL        LL_RCC_IC8_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC8_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC8CFGR      IC8INT        LL_RCC_IC8_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC8_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8INT, (Divider - 1UL) << RCC_IC8CFGR_IC8INT_Pos);
+}
+
+/**
+  * @brief  Get IC8 divider
+  * @rmtoll IC8CFGR      IC8INT        LL_RCC_IC8_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC8_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC8CFGR, RCC_IC8CFGR_IC8INT) >> RCC_IC8CFGR_IC8INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC9
+  * @rmtoll DIVENSR       IC9ENS        LL_RCC_IC9_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC9_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC9ENS);
+}
+
+/**
+  * @brief  Disable IC9
+  * @rmtoll DIVENCR       IC9ENC        LL_RCC_IC9_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC9_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC9ENC);
+}
+
+/**
+  * @brief  Check if IC9 is enabled
+  * @rmtoll DIVENR       IC9EN         LL_RCC_IC9_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC9_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC9EN) == RCC_DIVENR_IC9EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC9 clock source.
+  * @rmtoll IC9CFGR      IC9SEL        LL_RCC_IC9_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC9_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC9 clock source.
+  * @rmtoll IC9CFGR      IC9SEL        LL_RCC_IC9_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC9_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC9CFGR      IC9INT        LL_RCC_IC9_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC9_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9INT, (Divider - 1UL) << RCC_IC9CFGR_IC9INT_Pos);
+}
+
+/**
+  * @brief  Get IC9 divider
+  * @rmtoll IC9CFGR      IC9INT        LL_RCC_IC9_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC9_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC9CFGR, RCC_IC9CFGR_IC9INT) >> RCC_IC9CFGR_IC9INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC10
+  * @rmtoll DIVENSR       IC10ENS        LL_RCC_IC10_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC10_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC10ENS);
+}
+
+/**
+  * @brief  Disable IC10
+  * @rmtoll DIVENCR       IC10ENC        LL_RCC_IC10_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC10_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC10ENC);
+}
+
+/**
+  * @brief  Check if IC10 is enabled
+  * @rmtoll DIVENR       IC10EN         LL_RCC_IC10_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC10_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC10EN) == RCC_DIVENR_IC10EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC10 clock source.
+  * @rmtoll IC10CFGR      IC10SEL        LL_RCC_IC10_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC10_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC10 clock source.
+  * @rmtoll IC10CFGR      IC10SEL        LL_RCC_IC10_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC10_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC10CFGR      IC10INT        LL_RCC_IC10_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC10_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10INT, (Divider - 1UL) << RCC_IC10CFGR_IC10INT_Pos);
+}
+
+/**
+  * @brief  Get IC10 divider
+  * @rmtoll IC10CFGR      IC10INT        LL_RCC_IC10_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC10_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC10CFGR, RCC_IC10CFGR_IC10INT) >> RCC_IC10CFGR_IC10INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC11
+  * @rmtoll DIVENSR       IC11ENS        LL_RCC_IC11_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC11_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC11ENS);
+}
+
+/**
+  * @brief  Disable IC11
+  * @rmtoll DIVENCR       IC11ENC        LL_RCC_IC11_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC11_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC11ENC);
+}
+
+/**
+  * @brief  Check if IC11 is enabled
+  * @rmtoll DIVENR       IC11EN         LL_RCC_IC11_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC11_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC11EN) == RCC_DIVENR_IC11EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC11 clock source.
+  * @rmtoll IC11CFGR      IC11SEL        LL_RCC_IC11_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC11_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC11CFGR, RCC_IC11CFGR_IC11SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC11 clock source.
+  * @rmtoll IC11CFGR      IC11SEL        LL_RCC_IC11_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC11_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC11CFGR, RCC_IC11CFGR_IC11SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC11CFGR      IC11INT        LL_RCC_IC11_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC11_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC11CFGR, RCC_IC11CFGR_IC11INT, (Divider - 1UL) << RCC_IC11CFGR_IC11INT_Pos);
+}
+
+/**
+  * @brief  Get IC11 divider
+  * @rmtoll IC11CFGR      IC11INT        LL_RCC_IC11_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC11_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC11CFGR, RCC_IC11CFGR_IC11INT) >> RCC_IC11CFGR_IC11INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC12
+  * @rmtoll DIVENSR       IC12ENS        LL_RCC_IC12_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC12_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC12ENS);
+}
+
+/**
+  * @brief  Disable IC12
+  * @rmtoll DIVENCR       IC12ENC        LL_RCC_IC12_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC12_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC12ENC);
+}
+
+/**
+  * @brief  Check if IC12 is enabled
+  * @rmtoll DIVENR       IC12EN         LL_RCC_IC12_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC12_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC12EN) == RCC_DIVENR_IC12EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC12 clock source.
+  * @rmtoll IC12CFGR      IC12SEL        LL_RCC_IC12_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC12_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC12 clock source.
+  * @rmtoll IC12CFGR      IC12SEL        LL_RCC_IC12_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC12_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC12CFGR      IC12INT        LL_RCC_IC12_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC12_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12INT, (Divider - 1UL) << RCC_IC12CFGR_IC12INT_Pos);
+}
+
+/**
+  * @brief  Get IC12 divider
+  * @rmtoll IC12CFGR      IC12INT        LL_RCC_IC12_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC12_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC12CFGR, RCC_IC12CFGR_IC12INT) >> RCC_IC12CFGR_IC12INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC13
+  * @rmtoll DIVENSR       IC13ENS        LL_RCC_IC13_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC13_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC13ENS);
+}
+
+/**
+  * @brief  Disable IC13
+  * @rmtoll DIVENCR       IC13ENC        LL_RCC_IC13_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC13_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC13ENC);
+}
+
+/**
+  * @brief  Check if IC13 is enabled
+  * @rmtoll DIVENR       IC13EN         LL_RCC_IC13_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC13_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC13EN) == RCC_DIVENR_IC13EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC13 clock source.
+  * @rmtoll IC13CFGR      IC13SEL        LL_RCC_IC13_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC13_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC13 clock source.
+  * @rmtoll IC13CFGR      IC13SEL        LL_RCC_IC13_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC13_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC13CFGR      IC13INT        LL_RCC_IC13_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC13_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13INT, (Divider - 1UL) << RCC_IC13CFGR_IC13INT_Pos);
+}
+
+/**
+  * @brief  Get IC13 divider
+  * @rmtoll IC13CFGR      IC13INT        LL_RCC_IC13_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC13_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC13CFGR, RCC_IC13CFGR_IC13INT) >> RCC_IC13CFGR_IC13INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC14
+  * @rmtoll DIVENSR       IC14ENS        LL_RCC_IC14_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC14_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC14ENS);
+}
+
+/**
+  * @brief  Disable IC14
+  * @rmtoll DIVENCR       IC14ENC        LL_RCC_IC14_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC14_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC14ENC);
+}
+
+/**
+  * @brief  Check if IC14 is enabled
+  * @rmtoll DIVENR       IC14EN         LL_RCC_IC14_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC14_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC14EN) == RCC_DIVENR_IC14EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC14 clock source.
+  * @rmtoll IC14CFGR      IC14SEL        LL_RCC_IC14_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC14_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC14 clock source.
+  * @rmtoll IC14CFGR      IC14SEL        LL_RCC_IC14_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC14_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC14CFGR      IC14INT        LL_RCC_IC14_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC14_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14INT, (Divider - 1UL) << RCC_IC14CFGR_IC14INT_Pos);
+}
+
+/**
+  * @brief  Get IC14 divider
+  * @rmtoll IC14CFGR      IC14INT        LL_RCC_IC14_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC14_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC14CFGR, RCC_IC14CFGR_IC14INT) >> RCC_IC14CFGR_IC14INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC15
+  * @rmtoll DIVENSR       IC15ENS        LL_RCC_IC15_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC15_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC15ENS);
+}
+
+/**
+  * @brief  Disable IC15
+  * @rmtoll DIVENCR       IC15ENC        LL_RCC_IC15_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC15_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC15ENC);
+}
+
+/**
+  * @brief  Check if IC15 is enabled
+  * @rmtoll DIVENR       IC15EN         LL_RCC_IC15_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC15_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC15EN) == RCC_DIVENR_IC15EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC15 clock source.
+  * @rmtoll IC15CFGR      IC15SEL        LL_RCC_IC15_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC15_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC15 clock source.
+  * @rmtoll IC15CFGR      IC15SEL        LL_RCC_IC15_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC15_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC15CFGR      IC15INT        LL_RCC_IC15_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC15_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15INT, (Divider - 1UL) << RCC_IC15CFGR_IC15INT_Pos);
+}
+
+/**
+  * @brief  Get IC15 divider
+  * @rmtoll IC15CFGR      IC15INT        LL_RCC_IC15_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC15_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC15CFGR, RCC_IC15CFGR_IC15INT) >> RCC_IC15CFGR_IC15INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC16
+  * @rmtoll DIVENSR       IC16ENS        LL_RCC_IC16_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC16_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC16ENS);
+}
+
+/**
+  * @brief  Disable IC16
+  * @rmtoll DIVENCR       IC16ENC        LL_RCC_IC16_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC16_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC16ENC);
+}
+
+/**
+  * @brief  Check if IC16 is enabled
+  * @rmtoll DIVENR       IC16EN         LL_RCC_IC16_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC16_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC16EN) == RCC_DIVENR_IC16EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC16 clock source.
+  * @rmtoll IC16CFGR      IC16SEL        LL_RCC_IC16_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC16_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC16 clock source.
+  * @rmtoll IC16CFGR      IC16SEL        LL_RCC_IC16_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC16_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC16CFGR      IC16INT        LL_RCC_IC16_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC16_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16INT, (Divider - 1UL) << RCC_IC16CFGR_IC16INT_Pos);
+}
+
+/**
+  * @brief  Get IC16 divider
+  * @rmtoll IC16CFGR      IC16INT        LL_RCC_IC16_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC16_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC16CFGR, RCC_IC16CFGR_IC16INT) >> RCC_IC16CFGR_IC16INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC17
+  * @rmtoll DIVENSR       IC17ENS        LL_RCC_IC17_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC17_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC17ENS);
+}
+
+/**
+  * @brief  Disable IC17
+  * @rmtoll DIVENCR       IC17ENC        LL_RCC_IC17_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC17_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC17ENC);
+}
+
+/**
+  * @brief  Check if IC17 is enabled
+  * @rmtoll DIVENR       IC17EN         LL_RCC_IC17_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC17_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC17EN) == RCC_DIVENR_IC17EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC17 clock source.
+  * @rmtoll IC17CFGR      IC17SEL        LL_RCC_IC17_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC17_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC17 clock source.
+  * @rmtoll IC17CFGR      IC17SEL        LL_RCC_IC17_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC17_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC17CFGR      IC17INT        LL_RCC_IC17_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC17_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17INT, (Divider - 1UL) << RCC_IC17CFGR_IC17INT_Pos);
+}
+
+/**
+  * @brief  Get IC17 divider
+  * @rmtoll IC17CFGR      IC17INT        LL_RCC_IC17_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC17_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC17CFGR, RCC_IC17CFGR_IC17INT) >> RCC_IC17CFGR_IC17INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC18
+  * @rmtoll DIVENSR       IC18ENS        LL_RCC_IC18_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC18_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC18ENS);
+}
+
+/**
+  * @brief  Disable IC18
+  * @rmtoll DIVENCR       IC18ENC        LL_RCC_IC18_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC18_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC18ENC);
+}
+
+/**
+  * @brief  Check if IC18 is enabled
+  * @rmtoll DIVENR       IC18EN         LL_RCC_IC18_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC18_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC18EN) == RCC_DIVENR_IC18EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC18 clock source.
+  * @rmtoll IC18CFGR      IC18SEL        LL_RCC_IC18_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC18_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC18 clock source.
+  * @rmtoll IC18CFGR      IC18SEL        LL_RCC_IC18_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC18_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC18CFGR      IC18INT        LL_RCC_IC18_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC18_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18INT, (Divider - 1UL) << RCC_IC18CFGR_IC18INT_Pos);
+}
+
+/**
+  * @brief  Get IC18 divider
+  * @rmtoll IC18CFGR      IC18INT        LL_RCC_IC18_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC18_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC18CFGR, RCC_IC18CFGR_IC18INT) >> RCC_IC18CFGR_IC18INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC19
+  * @rmtoll DIVENSR       IC19ENS        LL_RCC_IC19_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC19_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC19ENS);
+}
+
+/**
+  * @brief  Disable IC19
+  * @rmtoll DIVENCR       IC19ENC        LL_RCC_IC19_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC19_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC19ENC);
+}
+
+/**
+  * @brief  Check if IC19 is enabled
+  * @rmtoll DIVENR       IC19EN         LL_RCC_IC19_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC19_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC19EN) == RCC_DIVENR_IC19EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC19 clock source.
+  * @rmtoll IC19CFGR      IC19SEL        LL_RCC_IC19_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC19_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC19 clock source.
+  * @rmtoll IC19CFGR      IC19SEL        LL_RCC_IC19_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC19_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC19CFGR      IC19INT        LL_RCC_IC19_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC19_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19INT, (Divider - 1UL) << RCC_IC19CFGR_IC19INT_Pos);
+}
+
+/**
+  * @brief  Get IC19 divider
+  * @rmtoll IC19CFGR      IC19INT        LL_RCC_IC19_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC19_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC19CFGR, RCC_IC19CFGR_IC19INT) >> RCC_IC19CFGR_IC19INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable IC20
+  * @rmtoll DIVENSR       IC20ENS        LL_RCC_IC20_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC20_Enable(void)
+{
+  WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC20ENS);
+}
+
+/**
+  * @brief  Disable IC20
+  * @rmtoll DIVENCR       IC20ENC        LL_RCC_IC20_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC20_Disable(void)
+{
+  WRITE_REG(RCC->DIVENCR, RCC_DIVENCR_IC20ENC);
+}
+
+/**
+  * @brief  Check if IC20 is enabled
+  * @rmtoll DIVENR       IC20EN         LL_RCC_IC20_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC20_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->DIVENR, RCC_DIVENR_IC20EN) == RCC_DIVENR_IC20EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the PLL source used as IC20 clock source.
+  * @rmtoll IC20CFGR      IC20SEL        LL_RCC_IC20_SetSource
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC20_SetSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL, Source);
+}
+
+/**
+  * @brief  Get the PLL source used as IC20 clock source.
+  * @rmtoll IC20CFGR      IC20SEL        LL_RCC_IC20_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL1
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL2
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL3
+  *         @arg @ref LL_RCC_ICCLKSOURCE_PLL4
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC20_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL));
+}
+
+/**
+  * @brief  Set  divider
+  * @rmtoll IC20CFGR      IC20INT        LL_RCC_IC20_SetDivider
+  * @param  Divider This parameter can be a value between 1 and 256.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_IC20_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20INT, (Divider - 1UL) << RCC_IC20CFGR_IC20INT_Pos);
+}
+
+/**
+  * @brief  Get IC20 divider
+  * @rmtoll IC20CFGR      IC20INT        LL_RCC_IC20_GetDivider
+  * @retval can be a value between 1 and 256.
+  */
+__STATIC_INLINE uint32_t LL_RCC_IC20_GetDivider(void)
+{
+  return ((READ_BIT(RCC->IC20CFGR, RCC_IC20CFGR_IC20INT) >> RCC_IC20CFGR_IC20INT_Pos) + 1UL);
+}
+
+/**
+  * @brief  Enable CLKP
+  * @rmtoll MISCENSR      PERENS        LL_RCC_CLKP_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CLKP_Enable(void)
+{
+  WRITE_REG(RCC->MISCENSR, RCC_MISCENSR_PERENS);
+}
+
+/**
+  * @brief  Disable CLKP
+  * @rmtoll MISCENCR      PERENC        LL_RCC_CLKP_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CLKP_Disable(void)
+{
+  WRITE_REG(RCC->MISCENCR, RCC_MISCENCR_PERENC);
+}
+
+/**
+  * @brief  Check if CLKP is enabled
+  * @rmtoll MISCENR       PEREN         LL_RCC_CLKP_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CLKP_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->MISCENR, RCC_MISCENR_PEREN) == RCC_MISCENR_PEREN) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+  * @brief  Clear MSI ready interrupt flag
+  * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_MSIRDYC);
+}
+
+/**
+  * @brief  Clear PLL1 ready interrupt flag
+  * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_PLL1RDYC);
+}
+
+/**
+  * @brief  Clear PLL2 ready interrupt flag
+  * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_PLL2RDYC);
+}
+
+/**
+  * @brief  Clear PLL3 ready interrupt flag
+  * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_PLL3RDYC);
+}
+
+/**
+  * @brief  Clear PLL4 ready interrupt flag
+  * @rmtoll CICR         PLL4RDYC       LL_RCC_ClearFlag_PLL4RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL4RDY(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_PLL4RDYC);
+}
+
+/**
+  * @brief  Clear LSE Clock security system interrupt flag
+  * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+  * @brief  Clear HSE Clock security system interrupt flag
+  * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
+}
+
+/**
+  * @brief  Clear WKUP ready interrupt flag
+  * @rmtoll CICR         WKUPFC          LL_RCC_ClearFlag_WKUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_WKUP(void)
+{
+  WRITE_REG(RCC->CICR, RCC_CICR_WKUPFC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIFR         LSIRDYF         LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIFR         LSERDYF         LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIFR         HSIRDYF         LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIFR         HSERDYF         LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if MSI ready interrupt occurred or not
+  * @rmtoll CIFR         MSIRDYF         LL_RCC_IsActiveFlag_MSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if PLL1 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL1RDYF        LL_RCC_IsActiveFlag_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if PLL2 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL2RDYF        LL_RCC_IsActiveFlag_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if PLL3 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL3RDYF        LL_RCC_IsActiveFlag_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if PLL4 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL4RDYF        LL_RCC_IsActiveFlag_PLL4RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL4RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL4RDYF) == RCC_CIFR_PLL4RDYF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         LSECSSF         LL_RCC_IsActiveFlag_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if HSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         HSECSSF         LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if WKUP from STOP interrupt occurred or not
+  * @rmtoll CIFR         WKUPF           LL_RCC_IsActiveFlag_WKUP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WKUP(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_WKUPF) == RCC_CIFR_WKUPF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Window Watchdog reset is set or not.
+  * @rmtoll RSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
+  * @rmtoll RSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == RCC_RSR_PORRSTF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC flag CPU Lockup reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_LCKRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LCKRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LCKRSTF) == (RCC_RSR_LCKRSTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if RCC ETH1 power-down start acknowledged is set or not.
+  * @rmtoll CCIPR2       ETH1PWRDOWNACK LL_RCC_IsActiveFlag_ETH1PWRDOWNACK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_ETH1PWRDOWNACK(void)
+{
+  return ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ETH1PWRDOWNACK) == (RCC_CCIPR2_ETH1PWRDOWNACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear all reset flags.
+  * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE        LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE        LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Enable MSI ready interrupt
+  * @rmtoll CIER         MSIRDYIE        LL_RCC_EnableIT_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE        LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE        LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Enable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE       LL_RCC_EnableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Enable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE       LL_RCC_EnableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Enable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE       LL_RCC_EnableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Enable PLL4 ready interrupt
+  * @rmtoll CIER         PLL4RDYIE       LL_RCC_EnableIT_PLL4RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL4RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE);
+}
+
+/**
+  * @brief  Enable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE        LL_RCC_EnableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Enable HSECSS interrupt
+  * @rmtoll CIER         HSECSSIE        LL_RCC_EnableIT_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSECSSIE);
+}
+
+/**
+  * @brief  Enable WKUP interrupt
+  * @rmtoll CIER         WKUPIE          LL_RCC_EnableIT_WKUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_WKUP(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_WKUPIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE        LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE        LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Disable MSI ready interrupt
+  * @rmtoll CIER         MSIRDYIE        LL_RCC_DisableIT_MSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE        LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE        LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Disable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE       LL_RCC_DisableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Disable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE       LL_RCC_DisableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Disable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE       LL_RCC_DisableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Disable PLL4 ready interrupt
+  * @rmtoll CIER         PLL4RDYIE       LL_RCC_DisableIT_PLL4RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL4RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE);
+}
+
+/**
+  * @brief  Disable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE        LL_RCC_DisableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Disable HSECSS interrupt
+  * @rmtoll CIER         HSECSSIE        LL_RCC_DisableIT_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSECSSIE);
+}
+
+/**
+  * @brief  Disable WKUP interrupt
+  * @rmtoll CIER         WKUPIE          LL_RCC_DisableIT_WKUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_WKUP(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_WKUPIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSIRDYIE        LL_RCC_IsEnabledIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSERDYIE        LL_RCC_IsEnabledIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if MSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         MSIRDYIE        LL_RCC_IsEnabledIT_MSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSIRDYIE        LL_RCC_IsEnabledIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSERDYIE        LL_RCC_IsEnabledIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL1RDYIE       LL_RCC_IsEnabledIT_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL2RDYIE       LL_RCC_IsEnabledIT_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL3RDYIE       LL_RCC_IsEnabledIT_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if PLL4 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL4RDYIE       LL_RCC_IsEnabledIT_PLL4RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL4RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL4RDYIE) == RCC_CIER_PLL4RDYIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSECSSIE        LL_RCC_IsEnabledIT_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if HSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSECSSIE        LL_RCC_IsEnabledIT_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSECSS(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSECSSIE) == RCC_CIER_HSECSSIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Checks if WKUP interrupt source is enabled or disabled.
+  * @rmtoll CIER         WKUPIE          LL_RCC_IsEnabledIT_WKUP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_WKUP(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_WKUPIE) == RCC_CIER_WKUPIE) ? 1UL : 0UL);
+}
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+void LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+
+uint32_t    LL_RCC_GetCpuClockFreq(void);
+uint32_t    LL_RCC_GetSystemClockFreq(void);
+uint32_t    LL_RCC_GetPLL1ClockFreq(void);
+uint32_t    LL_RCC_GetPLL2ClockFreq(void);
+uint32_t    LL_RCC_GetPLL3ClockFreq(void);
+uint32_t    LL_RCC_GetPLL4ClockFreq(void);
+uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1,
+                                    uint32_t P2);
+
+uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+uint32_t    LL_RCC_GetADFClockFreq(uint32_t ADFxSource);
+uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
+uint32_t    LL_RCC_GetDCMIPPClockFreq(uint32_t DCMIPPxSource);
+uint32_t    LL_RCC_GetETHClockFreq(uint32_t ETHxSource);
+uint32_t    LL_RCC_GetETHPTPClockFreq(uint32_t ETHxPTPSource);
+uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
+uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetI3CClockFreq(uint32_t I3CxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
+uint32_t    LL_RCC_GetMDFClockFreq(uint32_t MDFxSource);
+uint32_t    LL_RCC_GetOTGPHYClockFreq(uint32_t OTGPHYxSource);
+uint32_t    LL_RCC_GetOTGPHYCKREFClockFreq(uint32_t OTGPHYxCKREFSource);
+uint32_t    LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource);
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+uint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
+uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
+uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+uint32_t    LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_RCC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rng.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rng.h
new file mode 100644
index 000000000..c16e356f4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rng.h
@@ -0,0 +1,726 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_rng.h
+  * @author  MCD Application Team
+  * @brief   Header file of RNG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_RNG_H
+#define STM32N6xx_LL_RNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @defgroup RNG_LL RNG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
+  * @{
+  */
+
+
+/**
+  * @brief LL RNG Init Structure Definition
+  */
+typedef struct
+{
+  uint32_t         ClockErrorDetection; /*!< Clock error detection.
+                                      This parameter can be one value of @ref RNG_LL_CED.
+                                      This parameter can be modified using unitary
+                                      functions @ref LL_RNG_EnableClkErrorDetect(). */
+} LL_RNG_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
+  * @{
+  */
+
+/** @defgroup RNG_LL_CED Clock Error Detection
+  * @{
+  */
+#define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */
+#define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */
+/**
+  * @}
+  */
+/** @defgroup RNG_LL_ARDIS Auto reset disable
+  * @{
+  */
+#define LL_RNG_ARDIS_ENABLE         0x00000000U              /*!< ARDIS enabled automatic reset to clear SECS bit*/
+#define LL_RNG_ARDIS_DISABLE        RNG_CR_ARDIS             /*!< ARDIS disabled no automatic reset to clear SECS bit*/
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_Clock_Divider_Factor  Value used to configure an internal
+  *            programmable divider acting on the incoming RNG clock
+  * @{
+  */
+#define LL_RNG_CLKDIV_BY_1       (0x00000000UL)                                                           /*!< No clock division                             */
+#define LL_RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)                                                        /*!< 2 RNG clock cycles per internal RNG clock     */
+#define LL_RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)                                                        /*!< 4 RNG clock cycles per internal RNG clock     */
+#define LL_RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                                      /*!< 8 RNG clock cycles per internal RNG clock     */
+#define LL_RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)                                                        /*!< 16 RNG clock cycles per internal RNG clock    */
+#define LL_RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                                      /*!< 32 RNG clock cycles per internal RNG clock    */
+#define LL_RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                                      /*!< 64 RNG clock cycles per internal RNG clock    */
+#define LL_RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 128 RNG clock cycles per internal RNG clock   */
+#define LL_RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)                                                        /*!< 256 RNG clock cycles per internal RNG clock   */
+#define LL_RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)                                      /*!< 512 RNG clock cycles per internal RNG clock   */
+#define LL_RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)                                      /*!< 1024 RNG clock cycles per internal RNG clock  */
+#define LL_RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 2048 RNG clock cycles per internal RNG clock  */
+#define LL_RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)                                      /*!< 4096 RNG clock cycles per internal RNG clock  */
+#define LL_RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                    /*!< 8192 RNG clock cycles per internal RNG clock  */
+#define LL_RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                    /*!< 16384 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)  /*!< 32768 RNG clock cycles per internal RNG clock */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_NIST_Compliance  NIST Compliance configuration
+  * @{
+  */
+#define LL_RNG_NIST_COMPLIANT     (0x00000000UL) /*!< Default NIST compliant configuration*/
+#define LL_RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RNG_ReadReg function
+  * @{
+  */
+#define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */
+#define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */
+#define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */
+#define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */
+#define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros
+  * @{
+  */
+#define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
+  * @{
+  */
+
+/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RNG register
+  * @param  __INSTANCE__ RNG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RNG register
+  * @param  __INSTANCE__ RNG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
+  * @{
+  */
+/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Enable Random Number Generation
+  * @rmtoll CR           RNGEN         LL_RNG_Enable
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+  * @brief  Disable Random Number Generation
+  * @rmtoll CR           RNGEN         LL_RNG_Disable
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
+{
+  CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
+}
+
+/**
+  * @brief  Check if Random Number Generator is enabled
+  * @rmtoll CR           RNGEN         LL_RNG_IsEnabled
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Clock Error Detection
+  * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Disable RNG Clock Error Detection
+  * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Check if RNG Clock Error Detection is enabled
+  * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set RNG Conditioning Soft Reset bit
+  * @rmtoll CR           CONDRST          LL_RNG_EnableCondReset
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Reset RNG  Conditioning Soft Reset bit
+  * @rmtoll CR           CONDRST         LL_RNG_DisableCondReset
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
+{
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Check if RNG Conditioning Soft Reset bit is set
+  * @rmtoll CR           CONDRST         LL_RNG_IsEnabledCondReset
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable RNG Config Lock
+  * @rmtoll CR           CONFIGLOCK          LL_RNG_ConfigLock
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
+}
+
+/**
+  * @brief  Check if RNG Config Lock is enabled
+  * @rmtoll CR           CONFIGLOCK         LL_RNG_IsConfigLocked
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable NIST Compliance
+  * @rmtoll CR           NISTC         LL_RNG_EnableNistCompliance
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Disable NIST Compliance
+  * @rmtoll CR           NISTC         LL_RNG_DisableNistCompliance
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Check if NIST Compliance is enabled
+  * @rmtoll CR           NISTC         LL_RNG_IsEnabledNistCompliance
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set RNG  Config1 Configuration field value
+  * @rmtoll CR           RNG_CONFIG1         LL_RNG_SetConfig1
+  * @param  RNGx RNG Instance
+  * @param  Config1 Value between 0 and 0x3F
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Get RNG  Config1 Configuration field value
+  * @rmtoll CR           RNG_CONFIG1         LL_RNG_GetConfig1
+  * @param  RNGx RNG Instance
+  * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
+  */
+__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
+{
+  return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
+}
+
+/**
+  * @brief  Set RNG  Config2 Configuration field value
+  * @rmtoll CR           RNG_CONFIG2         LL_RNG_SetConfig2
+  * @param  RNGx RNG Instance
+  * @param  Config2 Value between 0 and 0x7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Get RNG  Config2 Configuration field value
+  * @rmtoll CR           RNG_CONFIG2         LL_RNG_GetConfig2
+  * @param  RNGx RNG Instance
+  * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
+  */
+__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
+{
+  return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
+}
+
+/**
+  * @brief  Set RNG  Config3 Configuration field value
+  * @rmtoll CR           RNG_CONFIG3         LL_RNG_SetConfig3
+  * @param  RNGx RNG Instance
+  * @param  Config3 Value between 0 and 0xF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Get RNG  Config3 Configuration field value
+  * @rmtoll CR           RNG_CONFIG3         LL_RNG_GetConfig3
+  * @param  RNGx RNG Instance
+  * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
+  */
+__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
+{
+  return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
+}
+
+/**
+  * @brief  Set RNG  Clock divider factor
+  * @rmtoll CR           CLKDIV         LL_RNG_SetClockDivider
+  * @param  RNGx RNG Instance
+  * @param  Divider can be one of the following values:
+  *         @arg @ref LL_RNG_CLKDIV_BY_1
+  *         @arg @ref LL_RNG_CLKDIV_BY_2
+  *         @arg @ref LL_RNG_CLKDIV_BY_4
+  *         @arg @ref LL_RNG_CLKDIV_BY_8
+  *         @arg @ref LL_RNG_CLKDIV_BY_16
+  *         @arg @ref LL_RNG_CLKDIV_BY_32
+  *         @arg @ref LL_RNG_CLKDIV_BY_64
+  *         @arg @ref LL_RNG_CLKDIV_BY_128
+  *         @arg @ref LL_RNG_CLKDIV_BY_256
+  *         @arg @ref LL_RNG_CLKDIV_BY_512
+  *         @arg @ref LL_RNG_CLKDIV_BY_1024
+  *         @arg @ref LL_RNG_CLKDIV_BY_2048
+  *         @arg @ref LL_RNG_CLKDIV_BY_4096
+  *         @arg @ref LL_RNG_CLKDIV_BY_8192
+  *         @arg @ref LL_RNG_CLKDIV_BY_16384
+  *         @arg @ref LL_RNG_CLKDIV_BY_32768
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Get RNG  Clock divider factor
+  * @rmtoll CR           CLKDIV         LL_RNG_GetClockDivider
+  * @param  RNGx RNG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RNG_CLKDIV_BY_1
+  *         @arg @ref LL_RNG_CLKDIV_BY_2
+  *         @arg @ref LL_RNG_CLKDIV_BY_4
+  *         @arg @ref LL_RNG_CLKDIV_BY_8
+  *         @arg @ref LL_RNG_CLKDIV_BY_16
+  *         @arg @ref LL_RNG_CLKDIV_BY_32
+  *         @arg @ref LL_RNG_CLKDIV_BY_64
+  *         @arg @ref LL_RNG_CLKDIV_BY_128
+  *         @arg @ref LL_RNG_CLKDIV_BY_256
+  *         @arg @ref LL_RNG_CLKDIV_BY_512
+  *         @arg @ref LL_RNG_CLKDIV_BY_1024
+  *         @arg @ref LL_RNG_CLKDIV_BY_2048
+  *         @arg @ref LL_RNG_CLKDIV_BY_4096
+  *         @arg @ref LL_RNG_CLKDIV_BY_8192
+  *         @arg @ref LL_RNG_CLKDIV_BY_16384
+  *         @arg @ref LL_RNG_CLKDIV_BY_32768
+  */
+__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
+{
+  return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
+}
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate if the RNG Data ready Flag is set or not
+  * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if the Clock Error Current Status Flag is set or not
+  * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if the Seed Error Current Status Flag is set or not
+  * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not
+  * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not
+  * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Clock Error interrupt Status (CEIS) Flag
+  * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
+{
+  WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
+}
+
+/**
+  * @brief  Clear Seed Error interrupt Status (SEIS) Flag
+  * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
+{
+  WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Random Number Generator Interrupt
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_EnableIT
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
+{
+  SET_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+  * @brief  Disable Random Number Generator Interrupt
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_DisableIT
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
+{
+  CLEAR_BIT(RNGx->CR, RNG_CR_IE);
+}
+
+/**
+  * @brief  Check if Random Number Generator Interrupt is enabled
+  *         (applies for either Seed error, Clock Error or Data ready interrupts)
+  * @rmtoll CR           IE            LL_RNG_IsEnabledIT
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_LL_EF_Data_Management Data Management
+  * @{
+  */
+
+/**
+  * @brief  Return32-bit Random Number value
+  * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32
+  * @param  RNGx RNG Instance
+  * @retval Generated 32-bit random value
+  */
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
+{
+  return (uint32_t)(READ_REG(RNGx->DR));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enable Auto reset
+  * @rmtoll CR           ARDIS           LL_RNG_EnableArdis
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Disable Auto reset
+  * @rmtoll CR           ARDIS         LL_RNG_DisableArdis
+  * @param  RNGx RNG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx)
+{
+  MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+}
+
+/**
+  * @brief  Check if RNG Auto reset is enabled
+  * @rmtoll CR           ARDIS         LL_RNG_IsEnabledArdis
+  * @param  RNGx RNG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx)
+{
+  return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL);
+}
+
+/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
+  * @{
+  */
+
+/**
+  * @brief  Set RNG Health Test Control
+  * @rmtoll HTCR       HTCFG       LL_RNG_SetHealthConfig
+  * @param  RNGx RNG Instance
+  * @param  HTCFG can be values of 32 bits
+  * @retval None
+  */
+__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
+{
+  WRITE_REG(RNGx->HTCR, HTCFG);
+}
+
+/**
+  * @brief  Get RNG Health Test Control
+  * @rmtoll HTCR         HTCFG        LL_RNG_GetHealthConfig
+  * @param  RNGx RNG Instance
+  * @retval Return 32-bit RNG Health Test configuration
+  */
+__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx)
+{
+  return (uint32_t)READ_REG(RNGx->HTCR);
+}
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct);
+void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32N6xx_LL_RNG_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rtc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rtc.h
new file mode 100644
index 000000000..88694f245
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_rtc.h
@@ -0,0 +1,6061 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_rtc.h
+  * @author  GPM Application Team
+  * @brief   Header file of RTC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_RTC_H
+#define STM32N6xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_LL_Private_Constants RTC Private Constants
+  * @{
+  */
+/* Masks Definition */
+#define RTC_LL_INIT_MASK              0xFFFFFFFFU
+#define RTC_LL_RSF_MASK               0xFFFFFF5FU
+
+/* Write protection defines */
+#define RTC_WRITE_PROTECTION_DISABLE  (uint8_t)0xFF
+#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA
+#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53
+
+/* Defines used to combine date & time */
+#define RTC_OFFSET_WEEKDAY            24U
+#define RTC_OFFSET_DAY                16U
+#define RTC_OFFSET_MONTH              8U
+#define RTC_OFFSET_HOUR               16U
+#define RTC_OFFSET_MINUTE             8U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+#if !defined (UNUSED)
+#define UNUSED(x) ((void)(x))
+#endif /* !defined (UNUSED) */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  RTC Init structures definition
+  */
+typedef struct
+{
+  uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.
+                              This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
+
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetHourFormat(). */
+
+  uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetAsynchPrescaler(). */
+
+  uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.
+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
+
+                              This feature can be modified afterwards using unitary function
+                              @ref LL_RTC_SetSynchPrescaler(). */
+} LL_RTC_InitTypeDef;
+
+/**
+  * @brief  RTC Time structure definition
+  */
+typedef struct
+{
+  uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+                            This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
+
+                            This feature can be modified afterwards using unitary function
+                            @ref LL_RTC_TIME_SetFormat(). */
+
+  uint8_t Hours;       /*!< Specifies the RTC Time Hours.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 12
+                            if the @ref LL_RTC_TIME_FORMAT_PM is selected.
+
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 23
+                            if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
+
+                            This feature can be modified afterwards using unitary function
+                            @ref LL_RTC_TIME_SetHour(). */
+
+  uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+                            This feature can be modified afterwards using unitary function
+                            @ref LL_RTC_TIME_SetMinute(). */
+
+  uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+                            This feature can be modified afterwards using unitary function
+                            @ref LL_RTC_TIME_SetSecond(). */
+} LL_RTC_TimeTypeDef;
+
+/**
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                         This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
+
+                         This feature can be modified afterwards using unitary function
+                         @ref LL_RTC_DATE_SetWeekDay(). */
+
+  uint8_t Month;    /*!< Specifies the RTC Date Month.
+                         This parameter can be a value of @ref RTC_LL_EC_MONTH
+
+                         This feature can be modified afterwards using unitary function
+                         @ref LL_RTC_DATE_SetMonth(). */
+
+  uint8_t Day;      /*!< Specifies the RTC Date Day.
+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31
+
+                         This feature can be modified afterwards using unitary function
+                         @ref LL_RTC_DATE_SetDay(). */
+
+  uint8_t Year;     /*!< Specifies the RTC Date Year.
+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99
+
+                         This feature can be modified afterwards using unitary function
+                         @ref LL_RTC_DATE_SetYear(). */
+} LL_RTC_DateTypeDef;
+
+/**
+  * @brief  RTC Alarm structure definition
+  */
+typedef struct
+{
+  LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or
+                                      @ref RTC_LL_EC_ALMB_MASK for ALARM B.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_RTC_ALMA_SetMask() for ALARM A or @ref LL_RTC_ALMB_SetMask() for ALARM B.
+                                 */
+
+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.
+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION
+                                      for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() for ALARM A
+                                      or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday()
+                                      for ALARM B.
+                                 */
+
+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.
+                                      If AlarmDateWeekDaySel set to day, this parameter must be a number
+                                      between Min_Data = 1 and Max_Data = 31.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_RTC_ALMA_SetDay() for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
+
+                                      If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of
+                                      @ref RTC_LL_EC_WEEKDAY.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_RTC_ALMA_SetWeekDay() for ALARM A or
+                                      @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
+                                 */
+} LL_RTC_AlarmTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+  * @{
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+  * @{
+  */
+#define LL_RTC_FORMAT_BIN                  0U                    /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD                  1U                    /*!< BCD data format    */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
+  * @{
+  */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0U                    /*!< Alarm A Date is selected    */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL      /*!< Alarm A WeekDay is selected */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
+  * @{
+  */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0U                    /*!< Alarm B Date is selected    */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL      /*!< Alarm B WeekDay is selected */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RTC_ReadReg function
+  * @{
+  */
+#define LL_RTC_SCR_SSRUF                   RTC_SCR_CSSRUF
+#define LL_RTC_SCR_ITSF                    RTC_SCR_CITSF
+#define LL_RTC_SCR_TSOVF                   RTC_SCR_CTSOVF
+#define LL_RTC_SCR_TSF                     RTC_SCR_CTSF
+#define LL_RTC_SCR_WUTF                    RTC_SCR_CWUTF
+#define LL_RTC_SCR_ALRBF                   RTC_SCR_CALRBF
+#define LL_RTC_SCR_ALRAF                   RTC_SCR_CALRAF
+
+#define LL_RTC_ICSR_RECALPF                RTC_ICSR_RECALPF
+#define LL_RTC_ICSR_BCDU_2                 RTC_ICSR_BCDU_2
+#define LL_RTC_ICSR_BCDU_1                 RTC_ICSR_BCDU_1
+#define LL_RTC_ICSR_BCDU_0                 RTC_ICSR_BCDU_0
+#define LL_RTC_ICSR_BIN_1                  RTC_ICSR_BIN_1
+#define LL_RTC_ICSR_BIN_0                  RTC_ICSR_BIN_0
+#define LL_RTC_ICSR_INITF                  RTC_ICSR_INITF
+#define LL_RTC_ICSR_RSF                    RTC_ICSR_RSF
+#define LL_RTC_ICSR_INITS                  RTC_ICSR_INITS
+#define LL_RTC_ICSR_SHPF                   RTC_ICSR_SHPF
+#define LL_RTC_ICSR_WUTWF                  RTC_ICSR_WUTWF
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions
+  * @{
+  */
+#define LL_RTC_CR_TSIE                     RTC_CR_TSIE
+#define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
+#define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
+#define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY
+  * @{
+  */
+#define LL_RTC_WEEKDAY_MONDAY              (uint8_t)0x01         /*!< Monday    */
+#define LL_RTC_WEEKDAY_TUESDAY             (uint8_t)0x02         /*!< Tuesday   */
+#define LL_RTC_WEEKDAY_WEDNESDAY           (uint8_t)0x03         /*!< Wednesday */
+#define LL_RTC_WEEKDAY_THURSDAY            (uint8_t)0x04         /*!< Thrusday  */
+#define LL_RTC_WEEKDAY_FRIDAY              (uint8_t)0x05         /*!< Friday    */
+#define LL_RTC_WEEKDAY_SATURDAY            (uint8_t)0x06         /*!< Saturday  */
+#define LL_RTC_WEEKDAY_SUNDAY              (uint8_t)0x07         /*!< Sunday    */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_MONTH  MONTH
+  * @{
+  */
+#define LL_RTC_MONTH_JANUARY               (uint8_t)0x01         /*!< January   */
+#define LL_RTC_MONTH_FEBRUARY              (uint8_t)0x02         /*!< February  */
+#define LL_RTC_MONTH_MARCH                 (uint8_t)0x03         /*!< March     */
+#define LL_RTC_MONTH_APRIL                 (uint8_t)0x04         /*!< April     */
+#define LL_RTC_MONTH_MAY                   (uint8_t)0x05         /*!< May       */
+#define LL_RTC_MONTH_JUNE                  (uint8_t)0x06         /*!< June      */
+#define LL_RTC_MONTH_JULY                  (uint8_t)0x07         /*!< July      */
+#define LL_RTC_MONTH_AUGUST                (uint8_t)0x08         /*!< August    */
+#define LL_RTC_MONTH_SEPTEMBER             (uint8_t)0x09         /*!< September */
+#define LL_RTC_MONTH_OCTOBER               (uint8_t)0x10         /*!< October   */
+#define LL_RTC_MONTH_NOVEMBER              (uint8_t)0x11         /*!< November  */
+#define LL_RTC_MONTH_DECEMBER              (uint8_t)0x12         /*!< December  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
+  * @{
+  */
+#define LL_RTC_HOURFORMAT_24HOUR           0U                    /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
+  * @{
+  */
+#define LL_RTC_ALARMOUT_DISABLE            0U                    /*!< Output disabled        */
+#define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0         /*!< Alarm A output enabled */
+#define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1         /*!< Alarm B output enabled */
+#define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL           /*!< Wakeup output enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
+  * @{
+  */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   0U                      /*!< RTC_ALARM is push-pull output  */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  RTC_CR_TAMPALRM_TYPE    /*!< RTC_ALARM is open-drain output */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
+  * @{
+  */
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0U                    /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
+  * @{
+  */
+#define LL_RTC_TIME_FORMAT_AM_OR_24        0U                    /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM                   */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
+  * @{
+  */
+#define LL_RTC_SHIFT_SECOND_DELAY          0U                    /*!< Delay (seconds) = SUBFS / (PREDIV_S + 1)           */
+#define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /*!< Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
+  * @{
+  */
+#define LL_RTC_ALMA_MASK_NONE              0U                    /*!< No masks applied on Alarm A                */
+#define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4       /*!< Date/day do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3       /*!< Hours do not care in Alarm A comparison    */
+#define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2       /*!< Minutes do not care in Alarm A comparison  */
+#define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1       /*!< Seconds do not care in Alarm A comparison  */
+#define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
+  * @{
+  */
+#define LL_RTC_ALMA_TIME_FORMAT_AM         0U                    /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM                   */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMA_SUBSECONDBIN_AUTOCLR  RTC Alarm Sub Seconds with binary mode auto clear Definitions
+  * @{
+  */
+#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO    0UL
+/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */
+
+#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES   RTC_ALRMASSR_SSCLR
+/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0]
+     value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR -> SS[31:0]. */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
+  * @{
+  */
+#define LL_RTC_ALMB_MASK_NONE              0U                    /*!< No masks applied on Alarm B                */
+#define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4       /*!< Date/day do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3       /*!< Hours do not care in Alarm B comparison    */
+#define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2       /*!< Minutes do not care in Alarm B comparison  */
+#define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1       /*!< Seconds do not care in Alarm B comparison  */
+#define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
+  * @{
+  */
+#define LL_RTC_ALMB_TIME_FORMAT_AM         0U                    /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ALMB_SUBSECONDBIN_AUTOCLR  Alarm Sub Seconds with binary mode auto clear Definitions
+  * @{
+  */
+#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO    0UL
+/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */
+
+#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES   RTC_ALRMBSSR_SSCLR
+/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMBBINR -> SS[31:0]
+     value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMBBINR -> SS[31:0]. */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
+  * @{
+  */
+#define LL_RTC_TIMESTAMP_EDGE_RISING       0U                    /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
+  * @{
+  */
+#define LL_RTC_TS_TIME_FORMAT_AM           0U                    /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER  TAMPER
+  * @{
+  */
+#define LL_RTC_TAMPER_1                    TAMP_CR1_TAMP1E       /*!< Tamper 1 input detection */
+#define LL_RTC_TAMPER_2                    TAMP_CR1_TAMP2E       /*!< Tamper 2 input detection */
+#define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E       /*!< Tamper 3  input detection */
+#define LL_RTC_TAMPER_4                    TAMP_CR1_TAMP4E       /*!< Tamper 4  input detection */
+#define LL_RTC_TAMPER_5                    TAMP_CR1_TAMP5E       /*!< Tamper 5  input detection */
+#define LL_RTC_TAMPER_6                    TAMP_CR1_TAMP6E       /*!< Tamper 6  input detection */
+#define LL_RTC_TAMPER_7                    TAMP_CR1_TAMP7E       /*!< Tamper 7  input detection */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
+  * @{
+  */
+#define LL_RTC_TAMPER_MASK_TAMPER1         TAMP_CR2_TAMP1MSK     /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */
+#define LL_RTC_TAMPER_MASK_TAMPER2         TAMP_CR2_TAMP2MSK     /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased */
+#define LL_RTC_TAMPER_MASK_TAMPER3         TAMP_CR2_TAMP3MSK     /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
+  * @{
+  */
+#define LL_RTC_TAMPER_NOERASE_TAMPER1      TAMP_CR2_TAMP1POM     /*!< Tamper 1 event does not erase the backup registers */
+#define LL_RTC_TAMPER_NOERASE_TAMPER2      TAMP_CR2_TAMP2POM     /*!< Tamper 2 event does not erase the backup registers */
+#define LL_RTC_TAMPER_NOERASE_TAMPER3      TAMP_CR2_TAMP3POM     /*!< Tamper 3 event does not erase the backup registers */
+#define LL_RTC_TAMPER_NOERASE_TAMPER4      TAMP_CR2_TAMP4POM     /*!< Tamper 4 event does not erase the backup registers */
+#define LL_RTC_TAMPER_NOERASE_TAMPER5      TAMP_CR2_TAMP5POM     /*!< Tamper 5 event does not erase the backup registers */
+#define LL_RTC_TAMPER_NOERASE_TAMPER6      TAMP_CR2_TAMP6POM     /*!< Tamper 6 event does not erase the backup registers */
+#define LL_RTC_TAMPER_NOERASE_TAMPER7      TAMP_CR2_TAMP7POM     /*!< Tamper 7 event does not erase the backup registers */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
+  * @{
+  */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK     0U                    /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
+#define LL_RTC_TAMPER_DURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_8RTCCLK     TAMP_FLTCR_TAMPPRCH   /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
+  * @{
+  */
+#define LL_RTC_TAMPER_FILTER_DISABLE       0U                    /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_2SAMPLE       TAMP_FLTCR_TAMPFLT_0  /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_4SAMPLE       TAMP_FLTCR_TAMPFLT_1  /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_8SAMPLE       TAMP_FLTCR_TAMPFLT    /*!< Tamper is activated after 8 consecutive samples at the active level */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
+  * @{
+  */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0U                                              /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384   TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192    TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192  */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096  */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048    TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048  */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024  */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_512     (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512   */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_256     TAMP_FLTCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256   */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
+  * @{
+  */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    TAMP_CR2_TAMP1TRG     /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    TAMP_CR2_TAMP2TRG     /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    TAMP_CR2_TAMP3TRG     /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP4    TAMP_CR2_TAMP4TRG     /*!< Tamper 4 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP5    TAMP_CR2_TAMP5TRG     /*!< Tamper 5 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP6    TAMP_CR2_TAMP6TRG     /*!< Tamper 6 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP7    TAMP_CR2_TAMP7TRG     /*!< Tamper 7 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_INTERNAL  INTERNAL TAMPER
+  * @{
+  */
+#define LL_RTC_TAMPER_ITAMP1               TAMP_CR1_ITAMP1E      /*!< Internal tamper 1: RTC supply voltage monitoring                                   */
+#define LL_RTC_TAMPER_ITAMP2               TAMP_CR1_ITAMP2E      /*!< Internal tamper 2: Temperature monitoring                                          */
+#define LL_RTC_TAMPER_ITAMP3               TAMP_CR1_ITAMP3E      /*!< Internal tamper 3: LSE monitoring                                                  */
+#define LL_RTC_TAMPER_ITAMP4               TAMP_CR1_ITAMP4E      /*!< Internal tamper 4: HSE monitoring                                                  */
+#define LL_RTC_TAMPER_ITAMP5               TAMP_CR1_ITAMP5E      /*!< Internal tamper 5: RTC calendar overflow                                           */
+#define LL_RTC_TAMPER_ITAMP6               TAMP_CR1_ITAMP6E      /*!< Internal tamper 6: JTAG/SWD access when RDP > 0                                    */
+#define LL_RTC_TAMPER_ITAMP7               TAMP_CR1_ITAMP7E      /*!< Internal tamper 7: Voltage monitoring (VCORE, VREF+), through ADC analog watchdog  */
+#define LL_RTC_TAMPER_ITAMP8               TAMP_CR1_ITAMP8E      /*!< Internal tamper 8: Monotonic counter overflow                                      */
+#define LL_RTC_TAMPER_ITAMP9               TAMP_CR1_ITAMP9E      /*!< Internal tamper 9: Cryptographic IPs fault                                         */
+#define LL_RTC_TAMPER_ITAMP11              TAMP_CR1_ITAMP11E     /*!< Internal tamper 11: IWDG reset when tamper flag is set                             */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ITAMPER_NOERASE  INTERNAL TAMPER NO ERASE
+  * @{
+  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER1     TAMP_CR3_ITAMP1POM    /*!< Internal tamper 1 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER2     TAMP_CR3_ITAMP2POM    /*!< Internal tamper 2 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER3     TAMP_CR3_ITAMP3POM    /*!< Internal tamper 3 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER4     TAMP_CR3_ITAMP4POM    /*!< Internal tamper 4 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER5     TAMP_CR3_ITAMP5POM    /*!< Internal tamper 5 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER6     TAMP_CR3_ITAMP6POM    /*!< Internal tamper 6 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER7     TAMP_CR3_ITAMP7POM    /*!< Internal tamper 7 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER8     TAMP_CR3_ITAMP8POM    /*!< Internal tamper 8 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER9     TAMP_CR3_ITAMP9POM    /*!< Internal tamper 9 event does not erase the backup registers  */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER11    TAMP_CR3_ITAMP11POM   /*!< Internal tamper 11 event does not erase the backup registers */
+#define LL_RTC_TAMPER_NOERASE_ITAMPER15    TAMP_CR3_ITAMP15POM   /*!< Internal tamper 15 event does not erase the backup registers */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ACTIVE_MODE   ACTIVE TAMPER MODE
+  * @{
+  */
+#define LL_RTC_TAMPER_ATAMP_TAMP1AM        TAMP_ATCR1_TAMP1AM    /*!< Tamper 1 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP2AM        TAMP_ATCR1_TAMP2AM    /*!< Tamper 2 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP3AM        TAMP_ATCR1_TAMP3AM    /*!< Tamper 3 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP4AM        TAMP_ATCR1_TAMP4AM    /*!< Tamper 4 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP5AM        TAMP_ATCR1_TAMP5AM    /*!< Tamper 5 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP6AM        TAMP_ATCR1_TAMP6AM    /*!< Tamper 6 is active */
+#define LL_RTC_TAMPER_ATAMP_TAMP7AM        TAMP_ATCR1_TAMP7AM    /*!< Tamper 7 is active */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER   ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
+  * @{
+  */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK        0U                                                                      /*!< RTCCLK       */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2      TAMP_ATCR1_ATCKSEL_0                                                    /*!< RTCCLK/2     */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4      TAMP_ATCR1_ATCKSEL_1                                                    /*!< RTCCLK/4     */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8      (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)                           /*!< RTCCLK/8     */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16     TAMP_ATCR1_ATCKSEL_2                                                    /*!< RTCCLK/16    */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32     (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)                           /*!< RTCCLK/32    */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64     (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)                           /*!< RTCCLK/64    */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128    (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)    /*!< RTCCLK/128   */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_256    TAMP_ATCR1_ATCKSEL_3                                                    /*!< RTCCLK/256   */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_512    (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_0)                           /*!< RTCCLK/512   */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_1024   (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1)                           /*!< RTCCLK/1024  */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2048   (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)    /*!< RTCCLK/2048  */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4096   (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2)                           /*!< RTCCLK/4096  */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8192   (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)    /*!< RTCCLK/8192  */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16384  (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)    /*!< RTCCLK/16384 */
+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32768  (TAMP_ATCR1_ATCKSEL_3 | TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 |\
+                                                     TAMP_ATCR1_ATCKSEL_0)                                                  /*!< RTCCLK/32768 */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION   ACTIVE TAMPER OUTPUT SELECTION
+  * @{
+  */
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT   (0U << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT   (1U << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT   (2U << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP4OUT   (3U << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP5OUT   (4U << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP6OUT   (5U << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP7OUT   (6U << TAMP_ATCR2_ATOSEL1_Pos)
+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP8OUT   (7U << TAMP_ATCR2_ATOSEL1_Pos)
+
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT   (0U << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT   (1U << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT   (2U << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP4OUT   (3U << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP5OUT   (4U << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP6OUT   (5U << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP7OUT   (6U << TAMP_ATCR2_ATOSEL2_Pos)
+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP8OUT   (7U << TAMP_ATCR2_ATOSEL2_Pos)
+
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT   (0U << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT   (1U << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT   (2U << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP4OUT   (3U << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP5OUT   (4U << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP6OUT   (5U << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP7OUT   (6U << TAMP_ATCR2_ATOSEL3_Pos)
+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP8OUT   (7U << TAMP_ATCR2_ATOSEL3_Pos)
+
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP1OUT   (0U << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP2OUT   (1U << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP3OUT   (2U << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP4OUT   (3U << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP5OUT   (4U << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP6OUT   (5U << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP7OUT   (6U << TAMP_ATCR2_ATOSEL4_Pos)
+#define LL_RTC_TAMPER_ATAMP4IN_ATAMP8OUT   (7U << TAMP_ATCR2_ATOSEL4_Pos)
+
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP1OUT   (0U << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP2OUT   (1U << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP3OUT   (2U << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP4OUT   (3U << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP5OUT   (4U << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP6OUT   (5U << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP7OUT   (6U << TAMP_ATCR2_ATOSEL5_Pos)
+#define LL_RTC_TAMPER_ATAMP5IN_ATAMP8OUT   (7U << TAMP_ATCR2_ATOSEL5_Pos)
+
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP1OUT   (0U << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP2OUT   (1U << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP3OUT   (2U << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP4OUT   (3U << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP5OUT   (4U << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP6OUT   (5U << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP7OUT   (6U << TAMP_ATCR2_ATOSEL6_Pos)
+#define LL_RTC_TAMPER_ATAMP6IN_ATAMP8OUT   (7U << TAMP_ATCR2_ATOSEL6_Pos)
+
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP1OUT   (0U << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP2OUT   (1U << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP3OUT   (2U << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP4OUT   (3U << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP5OUT   (4U << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP6OUT   (5U << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP7OUT   (6U << TAMP_ATCR2_ATOSEL7_Pos)
+#define LL_RTC_TAMPER_ATAMP7IN_ATAMP8OUT   (7U << TAMP_ATCR2_ATOSEL7_Pos)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_BKP  BACKUP
+  * @{
+  */
+#define LL_RTC_BKP_NUMBER                  RTC_BACKUP_NB
+#define LL_RTC_BKP_DR0                     0U
+#define LL_RTC_BKP_DR1                     1U
+#define LL_RTC_BKP_DR2                     2U
+#define LL_RTC_BKP_DR3                     3U
+#define LL_RTC_BKP_DR4                     4U
+#define LL_RTC_BKP_DR5                     5U
+#define LL_RTC_BKP_DR6                     6U
+#define LL_RTC_BKP_DR7                     7U
+#define LL_RTC_BKP_DR8                     8U
+#define LL_RTC_BKP_DR9                     9U
+#define LL_RTC_BKP_DR10                    10U
+#define LL_RTC_BKP_DR11                    11U
+#define LL_RTC_BKP_DR12                    12U
+#define LL_RTC_BKP_DR13                    13U
+#define LL_RTC_BKP_DR14                    14U
+#define LL_RTC_BKP_DR15                    15U
+#define LL_RTC_BKP_DR16                    16U
+#define LL_RTC_BKP_DR17                    17U
+#define LL_RTC_BKP_DR18                    18U
+#define LL_RTC_BKP_DR19                    19U
+#define LL_RTC_BKP_DR20                    20U
+#define LL_RTC_BKP_DR21                    21U
+#define LL_RTC_BKP_DR22                    22U
+#define LL_RTC_BKP_DR23                    23U
+#define LL_RTC_BKP_DR24                    24U
+#define LL_RTC_BKP_DR25                    25U
+#define LL_RTC_BKP_DR26                    26U
+#define LL_RTC_BKP_DR27                    27U
+#define LL_RTC_BKP_DR28                    28U
+#define LL_RTC_BKP_DR29                    29U
+#define LL_RTC_BKP_DR30                    30U
+#define LL_RTC_BKP_DR31                    31U
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
+  * @{
+  */
+#define LL_RTC_WAKEUPCLOCK_DIV_16          0U                                    /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_8           RTC_CR_WUCKSEL_0                      /*!< RTC/8 clock is selected  */
+#define LL_RTC_WAKEUPCLOCK_DIV_4           RTC_CR_WUCKSEL_1                      /*!< RTC/4 clock is selected  */
+#define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected  */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE          RTC_CR_WUCKSEL_2                      /*!< ck_spre (usually 1 Hz) clock is selected                                              */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
+  * @{
+  */
+#define LL_RTC_CALIB_OUTPUT_NONE           0U                          /*!< Calibration output disabled  */
+#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz   */
+#define LL_RTC_CALIB_OUTPUT_512HZ          RTC_CR_COE                  /*!< Calibration output is 512 Hz */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion
+  * @{
+  */
+#define LL_RTC_CALIB_INSERTPULSE_NONE      0U                    /*!< No RTCCLK pulses are added                                                                      */
+#define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
+  * @{
+  */
+#define LL_RTC_CALIB_PERIOD_32SEC          0U                    /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_CALIB_LOWPOWER  Calibration low power
+  * @{
+  */
+#define LL_RTC_CALIB_LOWPOWER_NONE         0U                    /*!< High conso mode */
+#define LL_RTC_CALIB_LOWPOWER_SET          RTC_CALR_LPCAL        /*!< Low power mode  */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_BINARY_MODE  Binary mode (Sub Second Register)
+  * @{
+  */
+#define LL_RTC_BINARY_NONE                 0U                    /*!< Free running BCD calendar mode (Binary mode disabled) */
+#define LL_RTC_BINARY_ONLY                 RTC_ICSR_BIN_0        /*!< Free running Binary mode (BCD mode disabled)          */
+#define LL_RTC_BINARY_MIX                  RTC_ICSR_BIN_1        /*!< Free running BCD calendar and Binary mode enable      */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_BINARY_MIX_BCDU  Calendar second incrementation in Binary mix mode
+  * @{
+  */
+#define LL_RTC_BINARY_MIX_BCDU_0           0U                            /*!< 1s calendar increment is generated each time SS[7:0] = 0  */
+#define LL_RTC_BINARY_MIX_BCDU_1           (0x1UL << RTC_ICSR_BCDU_Pos)  /*!< 1s calendar increment is generated each time SS[8:0] = 0  */
+#define LL_RTC_BINARY_MIX_BCDU_2           (0x2UL << RTC_ICSR_BCDU_Pos)  /*!< 1s calendar increment is generated each time SS[9:0] = 0  */
+#define LL_RTC_BINARY_MIX_BCDU_3           (0x3UL << RTC_ICSR_BCDU_Pos)  /*!< 1s calendar increment is generated each time SS[10:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_4           (0x4UL << RTC_ICSR_BCDU_Pos)  /*!< 1s calendar increment is generated each time SS[11:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_5           (0x5UL << RTC_ICSR_BCDU_Pos)  /*!< 1s calendar increment is generated each time SS[12:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_6           (0x6UL << RTC_ICSR_BCDU_Pos)  /*!< 1s calendar increment is generated each time SS[13:0] = 0 */
+#define LL_RTC_BINARY_MIX_BCDU_7           (0x7UL << RTC_ICSR_BCDU_Pos)  /*!< 1s calendar increment is generated each time SS[14:0] = 0 */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_SECURE_RTC_FULL  Secure full rtc
+  * @{
+  */
+#define LL_RTC_SECURE_FULL_YES             RTC_SECCFGR_SEC       /*!< RTC full secure                                                                  */
+#define LL_RTC_SECURE_FULL_NO              0U                    /*!< RTC is not full secure, features can be secure. See RTC_LL_EC_SECURE_RTC_FEATURE */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_SECURE_RTC_FEATURE  Secure features rtc in case of LL_RTC_SECURE_FULL_NO.
+  * @{
+  */
+#define LL_RTC_SECURE_FEATURE_INIT         RTC_SECCFGR_INITSEC   /*!< Initialization feature is secure */
+#define LL_RTC_SECURE_FEATURE_CAL          RTC_SECCFGR_CALSEC    /*!< Calibration feature is secure    */
+#define LL_RTC_SECURE_FEATURE_TS           RTC_SECCFGR_TSSEC     /*!< Time stamp feature is secure     */
+#define LL_RTC_SECURE_FEATURE_WUT          RTC_SECCFGR_WUTSEC    /*!< Wake up timer feature is secure  */
+#define LL_RTC_SECURE_FEATURE_ALRA         RTC_SECCFGR_ALRASEC   /*!< Alarm A feature is secure        */
+#define LL_RTC_SECURE_FEATURE_ALRB         RTC_SECCFGR_ALRBSEC   /*!< Alarm B feature is secure        */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_SECURE_TAMP  Secure tamp
+  * @{
+  */
+#define LL_TAMP_SECURE_FULL_YES            TAMP_SECCFGR_TAMPSEC  /*!< TAMP full secure   */
+#define LL_TAMP_SECURE_FULL_NO             0U                    /*!< TAMP is not secure */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FULL  Privilege full rtc
+  * @{
+  */
+#define LL_RTC_PRIVILEGE_FULL_YES          RTC_PRIVCFGR_PRIV     /*!< RTC full privilege                                                                          */
+#define LL_RTC_PRIVILEGE_FULL_NO           0U                    /*!< RTC is not full privilege, features can be unprivilege. See RTC_LL_EC_PRIVILEGE_RTC_FEATURE */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FEATURE  Privilege rtc features in case of LL_RTC_PRIVILEGE_FULL_NO.
+  * @{
+  */
+#define LL_RTC_PRIVILEGE_FEATURE_INIT      RTC_PRIVCFGR_INITPRIV /*!< Initialization feature is privilege */
+#define LL_RTC_PRIVILEGE_FEATURE_CAL       RTC_PRIVCFGR_CALPRIV  /*!< Calibration feature is privilege    */
+#define LL_RTC_PRIVILEGE_FEATURE_TS        RTC_PRIVCFGR_TSPRIV   /*!< Time stamp feature is privilege     */
+#define LL_RTC_PRIVILEGE_FEATURE_WUT       RTC_PRIVCFGR_WUTPRIV  /*!< Wake up timer feature is privilege  */
+#define LL_RTC_PRIVILEGE_FEATURE_ALRA      RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A feature is privilege        */
+#define LL_RTC_PRIVILEGE_FEATURE_ALRB      RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B feature is privilege        */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_TAMP_FULL  Privilege full tamp
+  * @{
+  */
+#define LL_TAMP_PRIVILEGE_FULL_YES         TAMP_PRIVCFGR_TAMPPRIV /*!< TAMP full privilege   */
+#define LL_TAMP_PRIVILEGE_FULL_NO          0U                     /*!< TAMP is not privilege */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EC_PRIVILEGE_BACKUP_REG_ZONE  Privilege Backup register privilege zone
+  * @{
+  */
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_NONE    0U
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_1       TAMP_PRIVCFGR_BKPRWPRIV
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_2       TAMP_PRIVCFGR_BKPWPRIV
+#define LL_RTC_PRIVILEGE_BKUP_ZONE_ALL     (LL_RTC_PRIVILEGE_BKUP_ZONE_1 |  LL_RTC_PRIVILEGE_BKUP_ZONE_2)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+  * @{
+  */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RTC register
+  * @param  __INSTANCE__ RTC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RTC register
+  * @param  __INSTANCE__ RTC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format
+  * @param  __VALUE__ Byte to be converted
+  * @retval Converted byte
+  */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) ((uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)))
+
+/**
+  * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format
+  * @param  __VALUE__ BCD value to be converted
+  * @retval Converted byte
+  */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__)  \
+  ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Date Date helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to retrieve weekday.
+  * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Year in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Year in BCD format (0x00 . . . 0x99)
+  */
+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Month in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve Day in BCD format
+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get
+  * @retval Day in BCD format (0x01 . . . 0x31)
+  */
+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EM_Time Time helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to retrieve hour in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
+  */
+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve minute in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Minutes in BCD format (0x00. . .0x59)
+  */
+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
+
+/**
+  * @brief  Helper macro to retrieve second in BCD format
+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+  * @retval Seconds in  format (0x00. . .0x59)
+  */
+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+  * @{
+  */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set Hours format (24 hour/day or AM/PM hour format)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll RTC_CR           FMT           LL_RTC_SetHourFormat
+  * @param  RTCx RTC Instance
+  * @param  HourFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
+}
+
+/**
+  * @brief  Get Hours format (24 hour/day or AM/PM hour format)
+  * @rmtoll RTC_CR           FMT           LL_RTC_GetHourFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR
+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
+}
+
+/**
+  * @brief  Select the flag to be routed to RTC_ALARM output
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           OSEL          LL_RTC_SetAlarmOutEvent
+  * @param  RTCx RTC Instance
+  * @param  AlarmOutput This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
+  *         @arg @ref LL_RTC_ALARMOUT_ALMA
+  *         @arg @ref LL_RTC_ALARMOUT_ALMB
+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
+}
+
+/**
+  * @brief  Get the flag to be routed to RTC_ALARM output
+  * @rmtoll RTC_CR           OSEL          LL_RTC_GetAlarmOutEvent
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE
+  *         @arg @ref LL_RTC_ALARMOUT_ALMA
+  *         @arg @ref LL_RTC_ALARMOUT_ALMB
+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
+}
+
+/**
+  * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
+  * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
+  * @param  RTCx RTC Instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
+}
+
+/**
+  * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
+  * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_GetAlarmOutputType
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
+}
+
+/**
+  * @brief  Enable initialization mode
+  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+  *         and prescaler register (RTC_PRER).
+  *         Counters are stopped and start counting from the new value when INIT is reset.
+  * @rmtoll RTC_ICSR          INIT          LL_RTC_EnableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Set the Initialization mode */
+  SET_BIT(RTCx->ICSR, RTC_ICSR_INIT);
+}
+
+/**
+  * @brief  Disable initialization mode (Free running mode)
+  * @rmtoll RTC_ICSR          INIT          LL_RTC_DisableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Exit Initialization mode */
+  CLEAR_BIT(RTCx->ICSR, RTC_ICSR_INIT);
+
+}
+
+/**
+  * @brief  Set Binary mode (Sub Second Register)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function).
+  * @rmtoll RTC_ICSR           BIN           LL_RTC_SetBinaryMode
+  * @param  RTCx RTC Instance
+  * @param  BinaryMode can be one of the following values:
+  *         @arg @ref LL_RTC_BINARY_NONE
+  *         @arg @ref LL_RTC_BINARY_ONLY
+  *         @arg @ref LL_RTC_BINARY_MIX
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode)
+{
+  MODIFY_REG(RTCx->ICSR, RTC_ICSR_BIN, BinaryMode);
+}
+
+/**
+  * @brief  Get Binary mode (Sub Second Register)
+  * @rmtoll RTC_ICSR           BIN           LL_RTC_GetBinaryMode
+  * @param  RTCx RTC Instance
+  * @retval This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BINARY_NONE
+  *         @arg @ref LL_RTC_BINARY_ONLY
+  *         @arg @ref LL_RTC_BINARY_MIX
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN));
+}
+
+/**
+  * @brief  Set Binary Mix mode BCDU
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function).
+  * @rmtoll RTC_ICSR           BCDU          LL_RTC_SetBinMixBCDU
+  * @param  RTCx RTC Instance
+  * @param  BinMixBcdU can be one of the following values:
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_0
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_1
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_2
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_3
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_4
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_5
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_6
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU)
+{
+  MODIFY_REG(RTCx->ICSR, RTC_ICSR_BCDU, BinMixBcdU);
+}
+
+/**
+  * @brief  Get Binary Mix mode BCDU
+  * @rmtoll RTC_ICSR           BCDU          LL_RTC_GetBinMixBCDU
+  * @param  RTCx RTC Instance
+  * @retval This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_0
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_1
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_2
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_3
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_4
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_5
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_6
+  *         @arg @ref LL_RTC_BINARY_MIX_BCDU_7
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU));
+}
+
+/**
+  * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           POL           LL_RTC_SetOutputPolarity
+  * @param  RTCx RTC Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
+}
+
+/**
+  * @brief  Get Output polarity
+  * @rmtoll RTC_CR           POL           LL_RTC_GetOutputPolarity
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
+}
+
+/**
+  * @brief  Enable Bypass the shadow registers
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           BYPSHAD       LL_RTC_EnableShadowRegBypass
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+  * @brief  Disable Bypass the shadow registers
+  * @rmtoll RTC_CR           BYPSHAD       LL_RTC_DisableShadowRegBypass
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+  * @brief  Check if Shadow registers bypass is enabled or not.
+  * @rmtoll RTC_CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll RTC_CR           REFCKON       LL_RTC_EnableRefClock
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+  * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll RTC_CR           REFCKON       LL_RTC_DisableRefClock
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+  * @brief  Set Asynchronous prescaler factor
+  * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler
+  * @param  RTCx RTC Instance
+  * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+  * @brief  Set Synchronous prescaler factor
+  * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_SetSynchPrescaler
+  * @param  RTCx RTC Instance
+  * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
+{
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
+}
+
+/**
+  * @brief  Get Asynchronous prescaler factor
+  * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data = 0 and Max_Data = 0x7F
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
+}
+
+/**
+  * @brief  Get Synchronous prescaler factor
+  * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_GetSynchPrescaler
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
+}
+
+/**
+  * @brief  Enable the write protection for RTC registers.
+  * @rmtoll RTC_WPR          KEY           LL_RTC_EnableWriteProtection
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
+}
+
+/**
+  * @brief  Disable the write protection for RTC registers.
+  * @rmtoll RTC_WPR          KEY           LL_RTC_DisableWriteProtection
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
+}
+
+/**
+  * @brief  Enable tamper output.
+  * @note When the tamper output is enabled, all external and internal tamper flags
+  *       are ORed and routed to the TAMPALRM output.
+  * @rmtoll RTC_CR           TAMPOE       LL_RTC_EnableTamperOutput
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
+}
+
+/**
+  * @brief  Disable tamper output.
+  * @rmtoll RTC_CR           TAMPOE       LL_RTC_DisableTamperOutput
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
+}
+
+/**
+  * @brief  Check if tamper output is enabled or not.
+  * @rmtoll RTC_CR           TAMPOE       LL_RTC_IsTamperOutputEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Enable internal pull-up in output mode.
+  * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
+}
+
+/**
+  * @brief  Disable internal pull-up in output mode.
+  * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
+}
+
+/**
+  * @brief  Check if internal pull-up in output mode is enabled or not.
+  * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_IsAlarmPullUpEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Enable RTC_OUT2 output
+  * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
+  *       and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.
+  * @note RTC_OUT2 is not available in VBAT mode.
+  * @rmtoll RTC_CR           OUT2EN       LL_RTC_EnableOutput2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
+}
+
+/**
+  * @brief  Disable RTC_OUT2 output
+  * @rmtoll RTC_CR           OUT2EN       LL_RTC_DisableOutput2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
+}
+
+/**
+  * @brief  Check if RTC_OUT2 output is enabled or not.
+  * @rmtoll RTC_CR           OUT2EN       LL_RTC_IsOutput2Enabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U);
+}
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Time Time
+  * @{
+  */
+
+/**
+  * @brief  Set time format (AM/24-hour or PM notation)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @rmtoll RTC_TR           PM            LL_RTC_TIME_SetFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get time format (AM or PM notation)
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @rmtoll RTC_TR           PM            LL_RTC_TIME_GetFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
+}
+
+/**
+  * @brief  Set Hours in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
+  * @rmtoll RTC_TR           HT            LL_RTC_TIME_SetHour\n
+  *         RTC_TR           HU            LL_RTC_TIME_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
+             (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
+}
+
+/**
+  * @brief  Get Hours in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
+  *       Binary format
+  * @rmtoll RTC_TR           HT            LL_RTC_TIME_GetHour\n
+  *         RTC_TR           HU            LL_RTC_TIME_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
+}
+
+/**
+  * @brief  Set Minutes in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll RTC_TR           MNT           LL_RTC_TIME_SetMinute\n
+  *         RTC_TR           MNU           LL_RTC_TIME_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
+             (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
+}
+
+/**
+  * @brief  Get Minutes in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
+  *       to Binary format
+  * @rmtoll RTC_TR           MNT           LL_RTC_TIME_GetMinute\n
+  *         RTC_TR           MNU           LL_RTC_TIME_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+}
+
+/**
+  * @brief  Set Seconds in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll RTC_TR           ST            LL_RTC_TIME_SetSecond\n
+  *         RTC_TR           SU            LL_RTC_TIME_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
+             (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
+}
+
+/**
+  * @brief  Get Seconds in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
+  *       to Binary format
+  * @rmtoll RTC_TR           ST            LL_RTC_TIME_GetSecond\n
+  *         RTC_TR           SU            LL_RTC_TIME_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
+}
+
+/**
+  * @brief  Set time (hour, minute and second) in BCD format
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+  * @note TimeFormat and Hours should follow the same format
+  * @rmtoll RTC_TR           PM            LL_RTC_TIME_Config\n
+  *         RTC_TR           HT            LL_RTC_TIME_Config\n
+  *         RTC_TR           HU            LL_RTC_TIME_Config\n
+  *         RTC_TR           MNT           LL_RTC_TIME_Config\n
+  *         RTC_TR           MNU           LL_RTC_TIME_Config\n
+  *         RTC_TR           ST            LL_RTC_TIME_Config\n
+  *         RTC_TR           SU            LL_RTC_TIME_Config
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+  *         @arg @ref LL_RTC_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx,
+                                        uint32_t Format12_24,
+                                        uint32_t Hours,
+                                        uint32_t Minutes,
+                                        uint32_t Seconds)
+{
+  uint32_t temp;
+
+  temp = Format12_24                                                                                    | \
+         (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
+         (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
+  MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
+}
+
+/**
+  * @brief  Get time (hour, minute and second) in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  *       are available to get independently each parameter.
+  * @rmtoll RTC_TR           HT            LL_RTC_TIME_Get\n
+  *         RTC_TR           HU            LL_RTC_TIME_Get\n
+  *         RTC_TR           MNT           LL_RTC_TIME_Get\n
+  *         RTC_TR           MNU           LL_RTC_TIME_Get\n
+  *         RTC_TR           ST            LL_RTC_TIME_Get\n
+  *         RTC_TR           SU            LL_RTC_TIME_Get
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx)
+{
+  uint32_t temp;
+
+  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
+  return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U)                  | \
+                      ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR)     | \
+                    (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U)                | \
+                      ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
+                    ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
+}
+
+/**
+  * @brief  Memorize whether the daylight saving time change has been performed
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           BKP           LL_RTC_TIME_EnableDayLightStore
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+  * @brief  Disable memorization whether the daylight saving time change has been performed.
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           BKP           LL_RTC_TIME_DisableDayLightStore
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
+}
+
+/**
+  * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
+  * @rmtoll RTC_CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Subtract 1 hour (winter time change)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           SUB1H         LL_RTC_TIME_DecHour
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_SUB1H);
+}
+
+/**
+  * @brief  Add 1 hour (summer time change)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ADD1H         LL_RTC_TIME_IncHour
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ADD1H);
+}
+
+/**
+  * @brief  Get Sub second value in the synchronous prescaler counter.
+  * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through
+  *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
+  *        SubSeconds value in second fraction ratio with time unit following
+  *        generic formula:
+  *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+  *        This conversion can be performed only if no shift operation is pending
+  *        (ie. SHFP=0) when PREDIV_S >= SS.
+  * @rmtoll RTC_SSR          SS            LL_RTC_TIME_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+  *         else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
+}
+
+/**
+  * @brief  Synchronize to a remote clock with a high degree of precision.
+  * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   When REFCKON is set, firmware must not write to Shift control register.
+  * @rmtoll RTC_SHIFTR       ADD1S         LL_RTC_TIME_Synchronize\n
+  *         RTC_SHIFTR       SUBFS         LL_RTC_TIME_Synchronize
+  * @param  RTCx RTC Instance
+  * @param  ShiftSecond This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY
+  *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
+  * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
+{
+  WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Date Date
+  * @{
+  */
+
+/**
+  * @brief  Set Year in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
+  * @rmtoll RTC_DR           YT            LL_RTC_DATE_SetYear\n
+  *         RTC_DR           YU            LL_RTC_DATE_SetYear
+  * @param  RTCx RTC Instance
+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
+             (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
+}
+
+/**
+  * @brief  Get Year in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
+  * @rmtoll RTC_DR           YT            LL_RTC_DATE_GetYear\n
+  *         RTC_DR           YU            LL_RTC_DATE_GetYear
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x99
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
+}
+
+/**
+  * @brief  Set Week day
+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
+}
+
+/**
+  * @brief  Get Week day
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
+}
+
+/**
+  * @brief  Set Month in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
+  * @rmtoll RTC_DR           MT            LL_RTC_DATE_SetMonth\n
+  *         RTC_DR           MU            LL_RTC_DATE_SetMonth
+  * @param  RTCx RTC Instance
+  * @param  Month This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
+             (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
+}
+
+/**
+  * @brief  Get Month in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+  * @rmtoll RTC_DR           MT            LL_RTC_DATE_GetMonth\n
+  *         RTC_DR           MU            LL_RTC_DATE_GetMonth
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
+}
+
+/**
+  * @brief  Set Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll RTC_DR           DT            LL_RTC_DATE_SetDay\n
+  *         RTC_DR           DU            LL_RTC_DATE_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
+             (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
+}
+
+/**
+  * @brief  Get Day in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll RTC_DR           DT            LL_RTC_DATE_GetDay\n
+  *         RTC_DR           DU            LL_RTC_DATE_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
+}
+
+/**
+  * @brief  Set date (WeekDay, Day, Month and Year) in BCD format
+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Config\n
+  *         RTC_DR           MT            LL_RTC_DATE_Config\n
+  *         RTC_DR           MU            LL_RTC_DATE_Config\n
+  *         RTC_DR           DT            LL_RTC_DATE_Config\n
+  *         RTC_DR           DU            LL_RTC_DATE_Config\n
+  *         RTC_DR           YT            LL_RTC_DATE_Config\n
+  *         RTC_DR           YU            LL_RTC_DATE_Config
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @param  Month This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx,
+                                        uint32_t WeekDay,
+                                        uint32_t Day,
+                                        uint32_t Month,
+                                        uint32_t Year)
+{
+  uint32_t temp;
+
+  temp = (WeekDay << RTC_DR_WDU_Pos)                                                      | \
+         (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
+         (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
+         (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
+
+  MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
+}
+
+/**
+  * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
+  *       before reading this bit
+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
+  * and __LL_RTC_GET_DAY are available to get independently each parameter.
+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Get\n
+  *         RTC_DR           MT            LL_RTC_DATE_Get\n
+  *         RTC_DR           MU            LL_RTC_DATE_Get\n
+  *         RTC_DR           DT            LL_RTC_DATE_Get\n
+  *         RTC_DR           DU            LL_RTC_DATE_Get\n
+  *         RTC_DR           YT            LL_RTC_DATE_Get\n
+  *         RTC_DR           YU            LL_RTC_DATE_Get
+  * @param  RTCx RTC Instance
+  * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
+  */
+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx)
+{
+  uint32_t temp;
+
+  temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
+  return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+                    (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U)                 | \
+                      ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY)       | \
+                    (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U)                 | \
+                      ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH)     | \
+                    ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_ALARMA ALARMA
+  * @{
+  */
+
+/**
+  * @brief  Enable Alarm A
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+  * @brief  Disable Alarm A
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+  * @brief  Specify the Alarm A masks.
+  * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_SetMask\n
+  *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_SetMask\n
+  *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_SetMask\n
+  *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_SetMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMA_MASK_NONE
+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMA_MASK_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
+}
+
+/**
+  * @brief  Get the Alarm A masks.
+  * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_GetMask\n
+  *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_GetMask\n
+  *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_GetMask\n
+  *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_GetMask
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMA_MASK_NONE
+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMA_MASK_ALL
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
+}
+
+/**
+  * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+  * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+  * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )
+  * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+  * @brief  Set ALARM A Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_SetDay\n
+  *         RTC_ALRMAR       DU            LL_RTC_ALMA_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
+             (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_GetDay\n
+  *         RTC_ALRMAR       DU            LL_RTC_ALMA_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+  * @brief  Set ALARM A Weekday
+  * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
+}
+
+/**
+  * @brief  Get ALARM A Weekday
+  * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
+}
+
+/**
+  * @brief  Set Alarm A time format (AM/24-hour or PM notation)
+  * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get Alarm A time format (AM or PM notation)
+  * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
+}
+
+/**
+  * @brief  Set ALARM A Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+  * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_SetHour\n
+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
+             (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetHour\n
+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
+}
+
+/**
+  * @brief  Set ALARM A Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_SetMinute\n
+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
+             (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_GetMinute\n
+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
+}
+
+/**
+  * @brief  Set ALARM A Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_SetSecond\n
+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
+             (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM A Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_GetSecond\n
+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
+}
+
+/**
+  * @brief  Set Alarm A Time (hour, minute and second) in BCD format
+  * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_ConfigTime\n
+  *         RTC_ALRMAR       HT            LL_RTC_ALMA_ConfigTime\n
+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_ConfigTime\n
+  *         RTC_ALRMAR       MNT           LL_RTC_ALMA_ConfigTime\n
+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_ConfigTime\n
+  *         RTC_ALRMAR       ST            LL_RTC_ALMA_ConfigTime\n
+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_ConfigTime
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx,
+                                            uint32_t Format12_24,
+                                            uint32_t Hours,
+                                            uint32_t Minutes,
+                                            uint32_t Seconds)
+{
+  uint32_t temp;
+
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
+         (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
+
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | \
+             RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
+}
+
+/**
+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetTime\n
+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetTime\n
+  *         RTC_ALRMAR       MNT           LL_RTC_ALMA_GetTime\n
+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetTime\n
+  *         RTC_ALRMAR       ST            LL_RTC_ALMA_GetTime\n
+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) |
+                    (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Set Alarm A Mask the most-significant bits starting at this bit
+  * @note This register can be written only when ALRAE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @param  Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+  *              else Value between Min_Data=0x0 and Max_Data=0x3F
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Get Alarm A Mask the most-significant bits starting at this bit
+  * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+  *         else Value between Min_Data=0x0 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Set Alarm A Binary mode auto clear
+  * @note This register can be written only when ALRAE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll RTC_ALRABINR     SSCLR        LL_RTC_ALMA_SetBinAutoClr
+  * @param  RTCx RTC Instance
+  * @param  BinaryAutoClr This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO
+  *         @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr)
+{
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR, BinaryAutoClr);
+}
+
+/**
+  * @brief  Get Alarm A Binary mode auto clear
+  * @rmtoll RTC_ALRABINR     SSCLR        LL_RTC_ALMA_GetBinAutoClr
+  * @param  RTCx RTC Instance
+  * @retval It can be one of the following values:
+  *         @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO
+  *         @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR));
+}
+
+/**
+  * @brief  Set Alarm A Sub seconds value
+  * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond
+  * @param  RTCx RTC Instance
+  * @param  Subsecond  If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+  *                    else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
+}
+
+/**
+  * @brief  Get Alarm A Sub seconds value
+  * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+  *         else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_ALARMB ALARMB
+  * @{
+  */
+
+/**
+  * @brief  Enable Alarm B
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+  * @brief  Disable Alarm B
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+  * @brief  Specify the Alarm B masks.
+  * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_SetMask\n
+  *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_SetMask\n
+  *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_SetMask\n
+  *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_SetMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMB_MASK_NONE
+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMB_MASK_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
+}
+
+/**
+  * @brief  Get the Alarm B masks.
+  * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_GetMask\n
+  *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_GetMask\n
+  *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_GetMask\n
+  *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_GetMask
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_RTC_ALMB_MASK_NONE
+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS
+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES
+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS
+  *         @arg @ref LL_RTC_ALMB_MASK_ALL
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
+}
+
+/**
+  * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+  * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+  * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )
+  * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+  * @brief  Set ALARM B Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+  * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_SetDay\n
+  *         RTC_ALRMBR       DU            LL_RTC_ALMB_SetDay
+  * @param  RTCx RTC Instance
+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
+             (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_GetDay\n
+  *         RTC_ALRMBR       DU            LL_RTC_ALMB_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+  * @brief  Set ALARM B Weekday
+  * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_SetWeekDay
+  * @param  RTCx RTC Instance
+  * @param  WeekDay This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
+}
+
+/**
+  * @brief  Get ALARM B Weekday
+  * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
+}
+
+/**
+  * @brief  Set ALARM B time format (AM/24-hour or PM notation)
+  * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat
+  * @param  RTCx RTC Instance
+  * @param  TimeFormat This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
+}
+
+/**
+  * @brief  Get ALARM B time format (AM or PM notation)
+  * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
+}
+
+/**
+  * @brief  Set ALARM B Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+  * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_SetHour\n
+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_SetHour
+  * @param  RTCx RTC Instance
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
+             (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetHour\n
+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
+}
+
+/**
+  * @brief  Set ALARM B Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+  * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_SetMinute\n
+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_SetMinute
+  * @param  RTCx RTC Instance
+  * @param  Minutes between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
+             (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_GetMinute\n
+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
+}
+
+/**
+  * @brief  Set ALARM B Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+  * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_SetSecond\n
+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_SetSecond
+  * @param  RTCx RTC Instance
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
+             (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
+}
+
+/**
+  * @brief  Get ALARM B Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_GetSecond\n
+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
+}
+
+/**
+  * @brief  Set Alarm B Time (hour, minute and second) in BCD format
+  * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_ConfigTime\n
+  *         RTC_ALRMBR       HT            LL_RTC_ALMB_ConfigTime\n
+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_ConfigTime\n
+  *         RTC_ALRMBR       MNT           LL_RTC_ALMB_ConfigTime\n
+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_ConfigTime\n
+  *         RTC_ALRMBR       ST            LL_RTC_ALMB_ConfigTime\n
+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_ConfigTime
+  * @param  RTCx RTC Instance
+  * @param  Format12_24 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59
+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx,
+                                            uint32_t Format12_24,
+                                            uint32_t Hours,
+                                            uint32_t Minutes,
+                                            uint32_t Seconds)
+{
+  uint32_t temp;
+
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
+         (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
+
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | \
+             RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
+}
+
+/**
+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetTime\n
+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetTime\n
+  *         RTC_ALRMBR       MNT           LL_RTC_ALMB_GetTime\n
+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetTime\n
+  *         RTC_ALRMBR       ST            LL_RTC_ALMB_GetTime\n
+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | \
+                    (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
+}
+
+/**
+  * @brief  Set Alarm B Mask the most-significant bits starting at this bit
+  * @note This register can be written only when ALRBE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @param  Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+  *              else Value between Min_Data=0x0 and Max_Data=0x3F
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Get Alarm B Mask the most-significant bits starting at this bit
+  * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask
+  * @param  RTCx RTC Instance
+  * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
+  *         else Value between Min_Data=0x0 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
+}
+
+/**
+  * @brief  Set Alarm B Binary mode auto clear
+  * @note This register can be written only when ALRBE is reset in RTC_CR register,
+  *       or in initialization mode.
+  * @rmtoll RTC_ALRBBINR     SSCLR        LL_RTC_ALMB_SetBinAutoClr
+  * @param  RTCx RTC Instance
+  * @param  BinaryAutoClr This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO
+  *         @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr)
+{
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR, BinaryAutoClr);
+}
+
+/**
+  * @brief  Get Alarm B Binary mode auto clear
+  * @rmtoll RTC_ALRBBINR     SSCLR        LL_RTC_ALMB_GetBinAutoClr
+  * @param  RTCx RTC Instance
+  * @retval It can be one of the following values:
+  *         @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO
+  *         @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR));
+}
+
+/**
+  * @brief  Set Alarm B Sub seconds value
+  * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond
+  * @param  RTCx RTC Instance
+  * @param  Subsecond  If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+  *                    else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
+}
+
+/**
+  * @brief  Get Alarm B Sub seconds value
+  * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+  *         else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Timestamp Timestamp
+  * @{
+  */
+
+/**
+  * @brief  Enable internal event timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ITSE          LL_RTC_TS_EnableInternalEvent
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ITSE);
+}
+
+/**
+  * @brief  Disable internal event timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ITSE          LL_RTC_TS_DisableInternalEvent
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
+}
+
+/**
+  * @brief  Enable Timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           TSE           LL_RTC_TS_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+  * @brief  Disable Timestamp
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           TSE           LL_RTC_TS_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+  * @brief  Set Time-stamp event active edge
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
+  * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_SetActiveEdge
+  * @param  RTCx RTC Instance
+  * @param  Edge This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
+}
+
+/**
+  * @brief  Get Time-stamp event active edge
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_GetActiveEdge
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
+}
+
+/**
+  * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)
+  * @rmtoll RTC_TSTR         PM            LL_RTC_TS_GetTimeFormat
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM
+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
+}
+
+/**
+  * @brief  Get Timestamp Hours in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+  * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetHour\n
+  *         RTC_TSTR         HU            LL_RTC_TS_GetHour
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Minutes in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+  * @rmtoll RTC_TSTR         MNT           LL_RTC_TS_GetMinute\n
+  *         RTC_TSTR         MNU           LL_RTC_TS_GetMinute
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Seconds in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+  * @rmtoll RTC_TSTR         ST            LL_RTC_TS_GetSecond\n
+  *         RTC_TSTR         SU            LL_RTC_TS_GetSecond
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x59
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+  * @brief  Get Timestamp time (hour, minute and second) in BCD format
+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+  * are available to get independently each parameter.
+  * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetTime\n
+  *         RTC_TSTR         HU            LL_RTC_TS_GetTime\n
+  *         RTC_TSTR         MNT           LL_RTC_TS_GetTime\n
+  *         RTC_TSTR         MNU           LL_RTC_TS_GetTime\n
+  *         RTC_TSTR         ST            LL_RTC_TS_GetTime\n
+  *         RTC_TSTR         SU            LL_RTC_TS_GetTime
+  * @param  RTCx RTC Instance
+  * @retval Combination of hours, minutes and seconds.
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSTR,
+                             RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+  * @brief  Get Timestamp Week day
+  * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetWeekDay
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY
+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY
+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY
+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Month in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+  * @rmtoll RTC_TSDR         MT            LL_RTC_TS_GetMonth\n
+  *         RTC_TSDR         MU            LL_RTC_TS_GetMonth
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_MONTH_JANUARY
+  *         @arg @ref LL_RTC_MONTH_FEBRUARY
+  *         @arg @ref LL_RTC_MONTH_MARCH
+  *         @arg @ref LL_RTC_MONTH_APRIL
+  *         @arg @ref LL_RTC_MONTH_MAY
+  *         @arg @ref LL_RTC_MONTH_JUNE
+  *         @arg @ref LL_RTC_MONTH_JULY
+  *         @arg @ref LL_RTC_MONTH_AUGUST
+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER
+  *         @arg @ref LL_RTC_MONTH_OCTOBER
+  *         @arg @ref LL_RTC_MONTH_NOVEMBER
+  *         @arg @ref LL_RTC_MONTH_DECEMBER
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
+}
+
+/**
+  * @brief  Get Timestamp Day in BCD format
+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+  * @rmtoll RTC_TSDR         DT            LL_RTC_TS_GetDay\n
+  *         RTC_TSDR         DU            LL_RTC_TS_GetDay
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x01 and Max_Data=0x31
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+  * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format
+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
+  * and __LL_RTC_GET_DAY are available to get independently each parameter.
+  * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetDate\n
+  *         RTC_TSDR         MT            LL_RTC_TS_GetDate\n
+  *         RTC_TSDR         MU            LL_RTC_TS_GetDate\n
+  *         RTC_TSDR         DT            LL_RTC_TS_GetDate\n
+  *         RTC_TSDR         DU            LL_RTC_TS_GetDate
+  * @param  RTCx RTC Instance
+  * @retval Combination of Weekday, Day and Month
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+  * @brief  Get time-stamp sub second value
+  * @rmtoll RTC_TSDR         SS            LL_RTC_TS_GetSubSecond
+  * @param  RTCx RTC Instance
+  * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
+  *         else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
+}
+
+/**
+  * @brief  Activate timestamp on tamper detection event
+  * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
+}
+
+/**
+  * @brief  Disable timestamp on tamper detection event
+  * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_DisableOnTamper
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+  * @{
+  */
+
+/**
+  * @brief  Enable TAMPx input detection
+  * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Enable\n
+  *         TAMP_CR1       TAMP2E...     LL_RTC_TAMPER_Enable\n
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(const RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->CR1, Tamper);
+}
+
+/**
+  * @brief  Clear TAMPx input detection
+  * @rmtoll TAMP_CR1       TAMP1E         LL_RTC_TAMPER_Disable\n
+  *         TAMP_CR1       TAMP2E...      LL_RTC_TAMPER_Disable
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(const RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->CR1, Tamper);
+}
+
+/**
+  * @brief  Enable Tamper mask flag
+  * @note Associated Tamper IT must not enabled when tamper mask is set.
+  * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_EnableMask\n
+  *         TAMP_CR2       TAMP2MF...    LL_RTC_TAMPER_EnableMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER_MASK
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(const RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->CR2, Mask);
+}
+
+/**
+  * @brief  Disable Tamper mask flag
+  * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_DisableMask\n
+  *         TAMP_CR2       TAMP2MF...    LL_RTC_TAMPER_DisableMask
+  * @param  RTCx RTC Instance
+  * @param  Mask This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER_MASK
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(const RTC_TypeDef *RTCx, uint32_t Mask)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->CR2, Mask);
+}
+
+/**
+  * @brief  Enable backup register erase after Tamper event detection
+  * @rmtoll TAMP_CR2       TAMP1POM     LL_RTC_TAMPER_EnableEraseBKP\n
+  *         TAMP_CR2       TAMP2POM...  LL_RTC_TAMPER_EnableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER_NOERASE
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+  * @brief  Disable backup register erase after Tamper event detection
+  * @rmtoll TAMP_CR2       TAMP1POM     LL_RTC_TAMPER_DisableEraseBKP\n
+  *         TAMP_CR2       TAMP2POM...  LL_RTC_TAMPER_DisableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER_NOERASE
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+  * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
+  * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
+}
+
+/**
+  * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
+  * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
+}
+
+/**
+  * @brief  Set RTC_TAMPx precharge duration
+  * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
+  * @param  RTCx RTC Instance
+  * @param  Duration This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(const RTC_TypeDef *RTCx, uint32_t Duration)
+{
+  UNUSED(RTCx);
+  MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
+}
+
+/**
+  * @brief  Get RTC_TAMPx precharge duration
+  * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH));
+}
+
+/**
+  * @brief  Set RTC_TAMPx filter count
+  * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
+  * @param  RTCx RTC Instance
+  * @param  FilterCount This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(const RTC_TypeDef *RTCx, uint32_t FilterCount)
+{
+  UNUSED(RTCx);
+  MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
+}
+
+/**
+  * @brief  Get RTC_TAMPx filter count
+  * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT));
+}
+
+/**
+  * @brief  Set Tamper sampling frequency
+  * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
+  * @param  RTCx RTC Instance
+  * @param  SamplingFreq This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(const RTC_TypeDef *RTCx, uint32_t SamplingFreq)
+{
+  UNUSED(RTCx);
+  MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
+}
+
+/**
+  * @brief  Get Tamper sampling frequency
+  * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ));
+}
+
+/**
+  * @brief  Enable Active level for Tamper input
+  * @rmtoll TAMP_CR2       TAMP1TRG       LL_RTC_TAMPER_EnableActiveLevel\n
+  *         TAMP_CR2       TAMP2TRG       LL_RTC_TAMPER_EnableActiveLevel\n
+  *         TAMP_CR2       TAMPxTRG       LL_RTC_TAMPER_EnableActiveLevel\n
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+  * @brief  Disable Active level for Tamper input
+  * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel\n
+  *         TAMP_CR2       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel\n
+  *         TAMP_CR2       TAMPxTRG      LL_RTC_TAMPER_DisableActiveLevel\n
+  * @param  RTCx RTC Instance
+  * @param  Tamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->CR2, Tamper);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper
+  * @{
+  */
+
+/**
+  * @brief  Enable internal tamper detection.
+  * @rmtoll TAMP_CR1       ITAMP1E       LL_RTC_TAMPER_ITAMP_Enable\n
+  *         TAMP_CR1       ITAMP2E       LL_RTC_TAMPER_ITAMP_Enable\n
+  *         TAMP_CR1       ITAMPxE       LL_RTC_TAMPER_ITAMP_Enable
+  * @param  RTCx RTC Instance
+  * @param  InternalTamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_INTERNAL
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(const RTC_TypeDef *RTCx, uint32_t InternalTamper)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->CR1, InternalTamper);
+}
+
+/**
+  * @brief  Disable internal tamper detection.
+  * @rmtoll TAMP_CR1       ITAMP1E       LL_RTC_TAMPER_ITAMP_Disable\n
+  *         TAMP_CR1       ITAMP2E       LL_RTC_TAMPER_ITAMP_Disable\n
+  *         TAMP_CR1       ITAMPxE       LL_RTC_TAMPER_ITAMP_Disable\n
+  * @param  RTCx RTC Instance
+  * @param  InternalTamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_INTERNAL
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32_t InternalTamper)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->CR1, InternalTamper);
+}
+
+/**
+  * @brief  Enable backup register erase after internal tamper event detection
+  * @rmtoll TAMP_CR3       ITAMP1POM     LL_RTC_TAMPER_ITAMP_EnableEraseBKP
+  *         TAMP_CR3       ITAMP2POM...  LL_RTC_TAMPER_ITAMP_EnableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  InternalTamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_ITAMPER_NOERASE
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t InternalTamper)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->CR3, InternalTamper);
+}
+
+/**
+  * @brief  Disable backup register erase after internal tamper event detection
+  * @rmtoll TAMP_CR3       ITAMP1POM     LL_RTC_TAMPER_ITAMP_DisableEraseBKP
+  *         TAMP_CR3       ITAMP2POM...  LL_RTC_TAMPER_ITAMP_DisableEraseBKP
+  * @param  RTCx RTC Instance
+  * @param  InternalTamper This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_ITAMPER_NOERASE
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t InternalTamper)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->CR3, InternalTamper);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper
+  * @{
+  */
+/**
+  * @brief  Enable tamper active mode.
+  * @rmtoll TAMP_ATCR1     TAMP1AM       LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
+  * @rmtoll TAMP_ATCR1     TAMP2AM       LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
+  * @rmtoll TAMP_ATCR1     TAMPxAM       LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
+  * @param  Tamper to configure as active. This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_ACTIVE_MODE
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)
+{
+  SET_BIT(TAMP->ATCR1, Tamper);
+}
+
+/**
+  * @brief  Disable tamper active mode.
+  * @rmtoll TAMP_ATCR1     TAMP1AM       LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
+  * @rmtoll TAMP_ATCR1     TAMP2AM       LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
+  * @rmtoll TAMP_ATCR1     TAMPxAM       LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
+  * @param  Tamper to configure as active. This parameter can be a combination of the following values:
+  *         @arg @ref RTC_LL_EC_ACTIVE_MODE
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)
+{
+  CLEAR_BIT(TAMP->ATCR1, Tamper);
+}
+
+/**
+  * @brief  Enable active tamper filter.
+  * @rmtoll TAMP_ATCR1     FLTEN         LL_RTC_TAMPER_ATAMP_EnableFilter\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void)
+{
+  SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
+}
+
+/**
+  * @brief  Disable active tamper filter.
+  * @rmtoll TAMP_ATCR1     FLTEN         LL_RTC_TAMPER_ATAMP_DisableFilter\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void)
+{
+  CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
+}
+
+/**
+  * @brief  Set Active tamper output change period.
+  * @rmtoll TAMP_ATCR1     ATPER         LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod\n
+  * @param  ActiveOutputChangePeriod This parameter can be a value from 0 to 7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)
+{
+  MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));
+}
+
+/**
+  * @brief  Get Active tamper output change period.
+  * @rmtoll TAMP_ATCR1     ATPER         LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod\n
+  * @retval Output change period. This parameter can be a value from 0 to 7.
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void)
+{
+  return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
+}
+
+/**
+  * @brief  Set Active tamper asynchronous prescaler clock selection.
+  * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler\n
+  * @param  ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock.
+            This parameter can be a value of the following values:
+  *         @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)
+{
+  MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);
+}
+
+/**
+  * @brief  Get Active tamper asynchronous prescaler clock selection.
+  * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n
+  * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void)
+{
+  return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));
+}
+
+/**
+  * @brief  Enable active tamper output sharing.
+  * @rmtoll TAMP_ATCR1     ATOSHARE      LL_RTC_TAMPER_ATAMP_EnableOutputSharing\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void)
+{
+  SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
+}
+
+/**
+  * @brief  Disable active tamper output sharing.
+  * @rmtoll TAMP_ATCR1     ATOSHARE      LL_RTC_TAMPER_ATAMP_DisableOutputSharing\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void)
+{
+  CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
+}
+
+/**
+  * @brief  Set Active tamper shared output selection.
+  * @rmtoll TAMP_ATCR2     ATOSELx       LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection\n
+  * @param  OutputSelection Specifies all the output selection of the Active Tamper.
+            This parameter is a combinasation of the following values:
+  *         One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)
+{
+  MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \
+                           TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7), \
+             OutputSelection);
+}
+
+/**
+  * @brief  Get Active tamper shared output selection.
+  * @rmtoll TAMP_ATCR2     ATOSELx       LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection\n
+  * @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
+  */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void)
+{
+  return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \
+                                 TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7)));
+}
+
+/**
+  * @brief  Write active tamper seed.
+  * @rmtoll TAMP_ATSEEDR   SEED          LL_RTC_TAMPER_ATAMP_WriteSeed\n
+  * @param  Seed
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)
+{
+  WRITE_REG(TAMP->ATSEEDR, Seed);
+}
+
+/**
+  * @brief  Get active tamper initialization status flag.
+  * @rmtoll TAMP_ATOR      INITS         LL_RTC_IsActiveFlag_ATAMP_INITS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void)
+{
+  return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get active tamper seed running status flag.
+  * @rmtoll TAMP_ATOR      SEEDF         LL_RTC_IsActiveFlag_ATAMP_SEEDF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void)
+{
+  return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Wakeup Wakeup
+  * @{
+  */
+
+/**
+  * @brief  Enable Wakeup timer
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+  * @brief  Disable Wakeup timer
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+  * @brief  Check if Wakeup timer is enabled or not
+  * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_IsEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Select Wakeup clock
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1
+  * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_SetClock
+  * @param  RTCx RTC Instance
+  * @param  WakeupClock This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
+}
+
+/**
+  * @brief  Get Wakeup clock
+  * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_GetClock
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
+}
+
+/**
+  * @brief  Set Wakeup auto-reload value
+  * @note   Bit can be written only when WUTWF is set to 1 in RTC_ICSR
+  * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload
+  * @param  RTCx RTC Instance
+  * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
+{
+  MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
+}
+
+/**
+  * @brief  Get Wakeup auto-reload value
+  * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified Backup data register.
+  * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_SetRegister
+  * @param  RTCx RTC Instance
+  * @param  BackupRegister This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  *         @arg      LL_RTC_BKP_DRx ...
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_BKP_SetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
+{
+  __IO uint32_t tmp;
+
+  UNUSED(RTCx);
+
+  tmp = (uint32_t)(&(TAMP->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_GetRegister
+  * @param  RTCx RTC Instance
+  * @param  BackupRegister This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  *         @arg      LL_RTC_BKP_DRx ...
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister)
+{
+  uint32_t tmp;
+
+  UNUSED(RTCx);
+
+  tmp = (uint32_t)(&(TAMP->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+  * @{
+  */
+
+/**
+  * @brief  Set Calibration output frequency (1 Hz or 512 Hz)
+  * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           COE           LL_RTC_CAL_SetOutputFreq\n
+  *         RTC_CR           COSEL         LL_RTC_CAL_SetOutputFreq
+  * @param  RTCx RTC Instance
+  * @param  Frequency This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
+{
+  MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
+}
+
+/**
+  * @brief  Get Calibration output frequency (1 Hz or 512 Hz)
+  * @rmtoll RTC_CR           COE           LL_RTC_CAL_GetOutputFreq\n
+  *         RTC_CR           COSEL         LL_RTC_CAL_GetOutputFreq
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
+}
+
+/**
+  * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
+  * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_SetPulse
+  * @param  RTCx RTC Instance
+  * @param  Pulse This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
+}
+
+/**
+  * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
+  * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_IsPulseInserted
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Set the calibration cycle period
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ICSR
+  * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_SetPeriod\n
+  *         RTC_CALR         CALW16        LL_RTC_CAL_SetPeriod
+  * @param  RTCx RTC Instance
+  * @param  Period This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
+}
+
+/**
+  * @brief  Get the calibration cycle period
+  * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_GetPeriod\n
+  *         RTC_CALR         CALW16        LL_RTC_CAL_GetPeriod
+  * @param  RTCx RTC Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
+}
+
+/**
+  * @brief  Set Calibration minus
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ICSR
+  * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_SetMinus
+  * @param  RTCx RTC Instance
+  * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
+{
+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
+}
+
+/**
+  * @brief  Get Calibration minus
+  * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_GetMinus
+  * @param  RTCx RTC Instance
+  * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx)
+{
+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
+}
+
+/**
+  * @brief  Enable Calibration Low Power
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0
+  * @rmtoll RTC_CALR         LPCAL          LL_RTC_CAL_LowPower_Enable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CALR, RTC_CALR_LPCAL);
+}
+
+/**
+  * @brief  Disable Calibration Low Power
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @note   Bit can be written only when RECALPF is set to 0
+  * @rmtoll RTC_CALR         LPCAL          LL_RTC_CAL_LowPower_Disable
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL);
+}
+
+/**
+  * @brief  Check if Calibration Low Power is enabled or not
+  * @rmtoll RTC_CALR         LPCAL          LL_RTC_CAL_LowPower_IsEnabled
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Internal Time-stamp flag
+  * @rmtoll RTC_SR          ITSF          LL_RTC_IsActiveFlag_ITS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Recalibration pending Flag
+  * @rmtoll RTC_ICSR          RECALPF       LL_RTC_IsActiveFlag_RECALP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Time-stamp overflow flag
+  * @rmtoll RTC_SR          TSOVF         LL_RTC_IsActiveFlag_TSOV
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Time-stamp flag
+  * @rmtoll RTC_SR          TSF           LL_RTC_IsActiveFlag_TS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Wakeup timer flag
+  * @rmtoll RTC_SR          WUTF          LL_RTC_IsActiveFlag_WUT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Alarm B flag
+  * @rmtoll RTC_SR          ALRBF         LL_RTC_IsActiveFlag_ALRB
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Alarm A flag
+  * @rmtoll RTC_SR          ALRAF         LL_RTC_IsActiveFlag_ALRA
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get SSR Underflow flag
+  * @rmtoll RTC_SR          SSRUF         LL_RTC_IsActiveFlag_SSRU
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Clear Internal Time-stamp flag
+  * @rmtoll RTC_SCR          CITSF          LL_RTC_ClearFlag_ITS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->SCR, RTC_SCR_CITSF);
+}
+
+/**
+  * @brief  Clear Time-stamp overflow flag
+  * @rmtoll RTC_SCR          CTSOVF         LL_RTC_ClearFlag_TSOV
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->SCR, RTC_SCR_CTSOVF);
+}
+
+/**
+  * @brief  Clear Time-stamp flag
+  * @rmtoll RTC_SCR          CTSF           LL_RTC_ClearFlag_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->SCR, RTC_SCR_CTSF);
+}
+
+/**
+  * @brief  Clear Wakeup timer flag
+  * @rmtoll RTC_SCR          CWUTF          LL_RTC_ClearFlag_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->SCR, RTC_SCR_CWUTF);
+}
+
+/**
+  * @brief  Clear Alarm B flag
+  * @rmtoll RTC_SCR          CALRBF         LL_RTC_ClearFlag_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->SCR, RTC_SCR_CALRBF);
+}
+
+/**
+  * @brief  Clear Alarm A flag
+  * @rmtoll RTC_SCR          CALRAF         LL_RTC_ClearFlag_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->SCR, RTC_SCR_CALRAF);
+}
+
+/**
+  * @brief  Clear SSR Underflow flag
+  * @rmtoll RTC_SCR          CSSRUF         LL_RTC_ClearFlag_SSRU
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->SCR, RTC_SCR_CSSRUF);
+}
+
+/**
+  * @brief  Get Initialization flag
+  * @rmtoll RTC_ICSR          INITF         LL_RTC_IsActiveFlag_INIT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Registers synchronization flag
+  * @rmtoll RTC_ICSR          RSF           LL_RTC_IsActiveFlag_RS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Clear Registers synchronization flag
+  * @rmtoll RTC_ICSR          RSF           LL_RTC_ClearFlag_RS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+  WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
+}
+
+/**
+  * @brief  Get Initialization status flag
+  * @rmtoll RTC_ICSR          INITS         LL_RTC_IsActiveFlag_INITS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Shift operation pending flag
+  * @rmtoll RTC_ICSR          SHPF          LL_RTC_IsActiveFlag_SHP
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Wakeup timer write flag
+  * @rmtoll RTC_ICSR          WUTWF         LL_RTC_IsActiveFlag_WUTW
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Alarm A masked flag.
+  * @rmtoll RTC_MISR          ALRAMF        LL_RTC_IsActiveFlag_ALRAM
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get SSR Underflow masked flag.
+  * @rmtoll RTC_MISR          SSRUMF        LL_RTC_IsActiveFlag_SSRUM
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Alarm B masked flag.
+  * @rmtoll RTC_MISR          ALRBMF        LL_RTC_IsActiveFlag_ALRBM
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Wakeup timer masked flag.
+  * @rmtoll RTC_MISR          WUTMF        LL_RTC_IsActiveFlag_WUTM
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Time-stamp masked flag.
+  * @rmtoll RTC_MISR          TSMF        LL_RTC_IsActiveFlag_TSM
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Time-stamp overflow masked flag.
+  * @rmtoll RTC_MISR          TSOVMF        LL_RTC_IsActiveFlag_TSOVM
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get Internal Time-stamp masked flag.
+  * @rmtoll RTC_MISR          ITSMF        LL_RTC_IsActiveFlag_ITSM
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 1 detection flag.
+  * @rmtoll TAMP_SR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 2 detection flag.
+  * @rmtoll TAMP_SR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 3 detection flag.
+  * @rmtoll TAMP_SR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 4 detection flag.
+  * @rmtoll TAMP_SR          TAMP4F        LL_RTC_IsActiveFlag_TAMP4
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 5 detection flag.
+  * @rmtoll TAMP_SR          TAMP5F        LL_RTC_IsActiveFlag_TAMP5
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 6 detection flag.
+  * @rmtoll TAMP_SR          TAMP6F        LL_RTC_IsActiveFlag_TAMP6
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 7 detection flag.
+  * @rmtoll TAMP_SR          TAMP7F        LL_RTC_IsActiveFlag_TAMP7
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 1 detection flag.
+  * @rmtoll TAMP_SR          ITAMP1F        LL_RTC_IsActiveFlag_ITAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 2 detection flag.
+  * @rmtoll TAMP_SR          ITAMP2F        LL_RTC_IsActiveFlag_ITAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 3 detection flag.
+  * @rmtoll TAMP_SR          ITAMP3F        LL_RTC_IsActiveFlag_ITAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 4 detection flag.
+  * @rmtoll TAMP_SR          ITAMP4F        LL_RTC_IsActiveFlag_ITAMP4
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP4F) == (TAMP_SR_ITAMP4F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 5 detection flag.
+  * @rmtoll TAMP_SR          ITAMP5F        LL_RTC_IsActiveFlag_ITAMP5
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 6 detection flag.
+  * @rmtoll TAMP_SR          ITAMP6F        LL_RTC_IsActiveFlag_ITAMP6
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 7 detection flag.
+  * @rmtoll TAMP_SR          ITAMP7F        LL_RTC_IsActiveFlag_ITAMP7
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP7F) == (TAMP_SR_ITAMP7F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 8 detection flag.
+  * @rmtoll TAMP_SR          ITAMP8F        LL_RTC_IsActiveFlag_ITAMP8
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 9 detection flag.
+  * @rmtoll TAMP_SR          ITAMP9F        LL_RTC_IsActiveFlag_ITAMP9
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 11 detection flag.
+  * @rmtoll TAMP_SR          ITAMP11F        LL_RTC_IsActiveFlag_ITAMP11
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 1 interrupt masked flag.
+  * @rmtoll TAMP_MISR          TAMP1MF        LL_RTC_IsActiveFlag_TAMP1M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 2 interrupt masked flag.
+  * @rmtoll TAMP_MISR          TAMP2MF        LL_RTC_IsActiveFlag_TAMP2M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 3 interrupt masked flag.
+  * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP3M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 4 interrupt masked flag.
+  * @rmtoll TAMP_MISR          TAMP4MF        LL_RTC_IsActiveFlag_TAMP4M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 5 interrupt masked flag.
+  * @rmtoll TAMP_MISR          TAMP5MF        LL_RTC_IsActiveFlag_TAMP5M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 6 interrupt masked flag.
+  * @rmtoll TAMP_MISR          TAMP6MF        LL_RTC_IsActiveFlag_TAMP6M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get tamper 7 interrupt masked flag.
+  * @rmtoll TAMP_MISR          TAMP7MF        LL_RTC_IsActiveFlag_TAMP7M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 1 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP1MF        LL_RTC_IsActiveFlag_ITAMP1M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 2 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP2MF        LL_RTC_IsActiveFlag_ITAMP2M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 3 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP3MF        LL_RTC_IsActiveFlag_ITAMP3M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 4 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP4MF        LL_RTC_IsActiveFlag_ITAMP4M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP4MF) == (TAMP_MISR_ITAMP4MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 5 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP5MF        LL_RTC_IsActiveFlag_ITAMP5M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 6 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP6MF        LL_RTC_IsActiveFlag_ITAMP6M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 7 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP7MF        LL_RTC_IsActiveFlag_ITAMP7M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP7MF) == (TAMP_MISR_ITAMP7MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 8 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP8MF        LL_RTC_IsActiveFlag_ITAMP8M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 9 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP9MF        LL_RTC_IsActiveFlag_ITAMP9M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP9MF) == (TAMP_MISR_ITAMP9MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Get internal tamper 11 interrupt masked flag.
+  * @rmtoll TAMP_MISR          ITAMP11MF        LL_RTC_IsActiveFlag_ITAMP11M
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11M(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP11MF) == (TAMP_MISR_ITAMP11MF)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Clear tamper 1 detection flag.
+  * @rmtoll TAMP_SCR          CTAMP1F         LL_RTC_ClearFlag_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F);
+}
+
+/**
+  * @brief  Clear tamper 2 detection flag.
+  * @rmtoll TAMP_SCR          CTAMP2F         LL_RTC_ClearFlag_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F);
+}
+
+/**
+  * @brief  Clear tamper 3 detection flag.
+  * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F);
+}
+
+/**
+  * @brief  Clear tamper 4 detection flag.
+  * @rmtoll TAMP_SCR          CTAMP4F         LL_RTC_ClearFlag_TAMP4
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP4F);
+}
+
+/**
+  * @brief  Clear tamper 5 detection flag.
+  * @rmtoll TAMP_SCR          CTAMP5F         LL_RTC_ClearFlag_TAMP5
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP5F);
+}
+
+/**
+  * @brief  Clear tamper 6 detection flag.
+  * @rmtoll TAMP_SCR          CTAMP6F         LL_RTC_ClearFlag_TAMP6
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP6F);
+}
+
+/**
+  * @brief  Clear tamper 7 detection flag.
+  * @rmtoll TAMP_SCR          CTAMP7F         LL_RTC_ClearFlag_TAMP7
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP7F);
+}
+
+/**
+  * @brief  Clear internal tamper 1 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP1F         LL_RTC_ClearFlag_ITAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP1F);
+}
+
+/**
+  * @brief  Clear internal tamper 2 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP2F         LL_RTC_ClearFlag_ITAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP2F);
+}
+
+/**
+  * @brief  Clear internal tamper 3 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP3F         LL_RTC_ClearFlag_ITAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F);
+}
+
+/**
+  * @brief  Clear internal tamper 4 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP4F         LL_RTC_ClearFlag_ITAMP4
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP4F);
+}
+
+/**
+  * @brief  Clear internal tamper 5 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP5F         LL_RTC_ClearFlag_ITAMP5
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F);
+}
+
+/**
+  * @brief  Clear internal tamper 6 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP6F         LL_RTC_ClearFlag_ITAMP6
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP6F);
+}
+
+/**
+  * @brief  Clear internal tamper 7 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP7F         LL_RTC_ClearFlag_ITAMP7
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP7F);
+}
+
+/**
+  * @brief  Clear internal tamper 8 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP8F         LL_RTC_ClearFlag_ITAMP8
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F);
+}
+
+/**
+  * @brief  Clear internal tamper 9 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP9F         LL_RTC_ClearFlag_ITAMP9
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP9(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP9F);
+}
+
+/**
+  * @brief  Clear internal tamper 11 detection flag.
+  * @rmtoll TAMP_SCR          CITAMP11F         LL_RTC_ClearFlag_ITAMP11
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP11(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP11F);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_SECURITY SECURITY_Management
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Set RTC secure level.
+  * @note   secure features are relevant if LL_RTC_SECURE_FULL_NO.
+  * @rmtoll RTC_SECCFGR           SEC           LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           INITSEC       LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           CALSEC        LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           TSSEC         LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           WUTSEC        LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           ALRASEC       LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           ALRBSEC       LL_RTC_SetRtcSecure
+  * @param  RTCx RTC Instance
+  * @param  rtcSecure This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_SECURE_FULL_YES
+  *         @arg @ref LL_RTC_SECURE_FULL_NO
+  *         @arg @ref LL_RTC_SECURE_FEATURE_INIT
+  *         @arg @ref LL_RTC_SECURE_FEATURE_CAL
+  *         @arg @ref LL_RTC_SECURE_FEATURE_TS
+  *         @arg @ref LL_RTC_SECURE_FEATURE_WUT
+  *         @arg @ref LL_RTC_SECURE_FEATURE_ALRA
+  *         @arg @ref LL_RTC_SECURE_FEATURE_ALRB
+
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetRtcSecure(RTC_TypeDef *RTCx, uint32_t rtcSecure)
+{
+  MODIFY_REG(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \
+             RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC, rtcSecure);
+}
+#endif /* defined (CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Get RTC secure level.
+  * @note   Secure features is relevant if LL_RTC_SECURE_FULL_NO.
+  * @rmtoll RTC_SECCFGR           SEC           LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           INISEC        LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           CALSEC        LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           TSSEC         LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           WUTSEC        LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           ALRASEC       LL_RTC_SetRtcSecure
+  * @rmtoll RTC_SECCFGR           ALRBSEC       LL_RTC_SetRtcSecure
+  * @param  RTCx RTC Instance
+  * @retval Combination of the following values:
+  *         @arg @ref LL_RTC_SECURE_FULL_YES
+  *         @arg @ref LL_RTC_SECURE_FULL_NO
+  *         @arg @ref LL_RTC_SECURE_FEATURE_INIT
+  *         @arg @ref LL_RTC_SECURE_FEATURE_CAL
+  *         @arg @ref LL_RTC_SECURE_FEATURE_TS
+  *         @arg @ref LL_RTC_SECURE_FEATURE_WUT
+  *         @arg @ref LL_RTC_SECURE_FEATURE_ALRA
+  *         @arg @ref LL_RTC_SECURE_FEATURE_ALRB
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(const RTC_TypeDef *RTCx)
+{
+  return READ_BIT(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \
+                  RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Set TAMPER secure level.
+  * @rmtoll TAMP_SECCFGR          TAMPSEC           LL_RTC_SetTampSecure
+  * @param  RTCx RTC Instance
+  * @param  tampSecure This parameter can be one of the following values:
+  *         @arg @ref LL_TAMP_SECURE_FULL_YES
+  *         @arg @ref LL_TAMP_SECURE_FULL_NO
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetTampSecure(const RTC_TypeDef *RTCx, uint32_t tampSecure)
+{
+  UNUSED(RTCx);
+  MODIFY_REG(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC, tampSecure);
+}
+#endif /* defined (CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Get TAMPER secure level.
+  * @rmtoll TAMP_SECCFGR          TAMPSEC           LL_RTC_GetTampSecure
+  * @param  RTCx RTC Instance
+  * @retval This parameter can be one of the following values:
+  *         @arg @ref LL_TAMP_SECURE_FULL_YES
+  *         @arg @ref LL_TAMP_SECURE_FULL_NO
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_PRIVILEGE PRIVILEGE_Management
+  * @{
+  */
+
+/**
+  * @brief  Set RTC privilege level.
+  * @note   Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO.
+  * @rmtoll RTC_PRIVCFGR           PRIV              LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           INITPRIV          LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           CALPRIV           LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           TSPRIV            LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           WUTPRIV           LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           ALRAPRIV          LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           ALRBPRIV          LL_RTC_SetRtcPrivilege
+  * @param  RTCx RTC Instance
+  * @param  rtcPrivilege This parameter can be a combination of the following values:
+  *         @arg @ref LL_RTC_PRIVILEGE_FULL_YES
+  *         @arg @ref LL_RTC_PRIVILEGE_FULL_NO
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetRtcPrivilege(RTC_TypeDef *RTCx, uint32_t rtcPrivilege)
+{
+  MODIFY_REG(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | RTC_PRIVCFGR_TSPRIV | \
+             RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV, rtcPrivilege);
+}
+
+/**
+  * @brief  Get RTC privilege level.
+  * @note   Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO.
+  * @rmtoll RTC_PRIVCFGR           PRIV              LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           INITPRIV          LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           CALPRIV           LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           TSPRIV            LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           WUTPRIV           LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           ALRAPRIV          LL_RTC_SetRtcPrivilege
+  * @rmtoll RTC_PRIVCFGR           ALRBPRIV          LL_RTC_SetRtcPrivilege
+  * @param  RTCx RTC Instance
+  * @retval Combination of the following values:
+  *         @arg @ref LL_RTC_PRIVILEGE_FULL_YES
+  *         @arg @ref LL_RTC_PRIVILEGE_FULL_NO
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA
+  *         @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(const RTC_TypeDef *RTCx)
+{
+  return READ_BIT(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV   | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV  | \
+                  RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV  | RTC_PRIVCFGR_ALRAPRIV | \
+                  RTC_PRIVCFGR_ALRBPRIV);
+}
+
+/**
+  * @brief  Set TAMPER privilege level.
+  * @rmtoll TAMP_PRIVCFGR          TAMPPRIV           LL_RTC_SetTampPrivilege
+  * @param  RTCx RTC Instance
+  * @param  tampPrivilege This parameter can be one of the following values:
+  *         @arg @ref LL_TAMP_PRIVILEGE_FULL_YES
+  *         @arg @ref LL_TAMP_PRIVILEGE_FULL_NO
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetTampPrivilege(const RTC_TypeDef *RTCx, uint32_t tampPrivilege)
+{
+  UNUSED(RTCx);
+  MODIFY_REG(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV, tampPrivilege);
+}
+
+/**
+  * @brief  Get TAMPER privilege level.
+  * @rmtoll TAMP_PRIVCFGR          TAMPPRIV           LL_RTC_GetTampPrivilege
+  * @param  RTCx RTC Instance
+  * @retval This parameter can be one of the following values:
+  *         @arg @ref LL_TAMP_PRIVILEGE_FULL_YES
+  *         @arg @ref LL_TAMP_PRIVILEGE_FULL_NO
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return READ_BIT(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV);
+}
+
+/**
+  * @brief  Set Backup Registers privilege level.
+  * @note   bckupRegisterPrivilege is only writable in secure mode or if trustzone is disabled
+  * @rmtoll TAMP_PRIVCFGR          BKPWPRIV           LL_RTC_SetBackupRegisterPrivilege
+  * @rmtoll TAMP_PRIVCFGR          BKPRWPRIV          LL_RTC_SetBackupRegisterPrivilege
+  * @param  RTCx RTC Instance
+  * @param  bckupRegisterPrivilege This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(const RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege)
+{
+  UNUSED(RTCx);
+  MODIFY_REG(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV), bckupRegisterPrivilege);
+}
+
+/**
+  * @brief  Get Backup Registers privilege level.
+  * @rmtoll TAMP_PRIVCFGR          BKPWPRIV           LL_RTC_GetBackupRegisterPrivilege
+  * @rmtoll TAMP_PRIVCFGR          BKPRWPRIV          LL_RTC_GetBackupRegisterPrivilege
+  * @param  RTCx RTC Instance
+  * @retval This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2
+  *         @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return READ_BIT(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV));
+}
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_BACKUP_REG_PROTECTION PROTECTION_BACKUP_REG_Management
+  * @brief    Backup register protection is common to security and privilege.
+  * @{
+  */
+
+/**
+  * @brief  Set Backup registers protection level.
+  * @note   Zone 1 : read protection write protection
+  * @note   Zone 2 : read non-protection  write protection
+  * @note   Zone 3 : read non-protection  write non-protection
+  * @note   zone 1 : start from 0 to startZone2 start value
+  * @note   zone 2 : start from startZone2 start value to startZone3 start value
+  * @note   zone 3 : start from to startZone3 to the end of BACKUPREG
+  * @note   Warning : this parameter is only writable in secure mode or if trustzone is disabled
+  * @rmtoll TAMP_SECCFGR          BKPWSEC           LL_RTC_SetBackupRegProtection
+  * @rmtoll TAMP_SECCFGR          BKPRWSEC          LL_RTC_SetBackupRegProtection
+  * @param  RTCx RTC Instance
+  * @param  startZone2 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  *         @arg      LL_RTC_BKP_DRx ...
+  * @param  startZone3 This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_BKP_DR0
+  *         @arg @ref LL_RTC_BKP_DR1
+  *         @arg @ref LL_RTC_BKP_DR2
+  *         @arg @ref LL_RTC_BKP_DR3
+  *         @arg @ref LL_RTC_BKP_DR4
+  *         @arg      LL_RTC_BKP_DRx ...
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_SetBackupRegProtection(const RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3)
+{
+  UNUSED(RTCx);
+  MODIFY_REG(TAMP->SECCFGR, (TAMP_SECCFGR_BKPRWSEC_Msk | TAMP_SECCFGR_BKPWSEC_Msk),
+             (startZone2 << TAMP_SECCFGR_BKPRWSEC_Pos) | (startZone3 << TAMP_SECCFGR_BKPWSEC_Pos));
+}
+
+/**
+  * @brief  Get Backup registers protection level start zone 2.
+  * @note   Zone 1 : read protection write protection
+  * @note   Zone 2 : read non-protection/non-privile  write protection
+  * @note   Zone 3 : read non-protection  write non-protection
+  * @rmtoll TAMP_SECCFGR          BKPRWSEC         LL_RTC_GetBackupRegProtectionStartZone2
+  * @param  RTCx RTC Instance
+  * @retval Start zone 2
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPRWSEC_Msk) >> TAMP_SECCFGR_BKPRWSEC_Pos;
+}
+
+/**
+  * @brief  Get Backup registers protection level start zone 3.
+  * @note   Zone 1 : read protection write protection
+  * @note   Zone 2 : read non-protection  write protection
+  * @note   Zone 3 : read non-protection  write non-protection
+  * @rmtoll TAMP_SECCFGR          BKPWSEC           LL_RTC_GetBackupRegProtectionStartZone3
+  * @param  RTCx RTC Instance
+  * @retval Start zone 2
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPWSEC_Msk) >> TAMP_SECCFGR_BKPWSEC_Pos;
+}
+/**
+  * @}
+  */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Time-stamp interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR          TSIE         LL_RTC_EnableIT_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+  * @brief  Disable Time-stamp interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR          TSIE         LL_RTC_DisableIT_TS
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+  * @brief  Enable Wakeup timer interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR          WUTIE         LL_RTC_EnableIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+  * @brief  Disable Wakeup timer interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR          WUTIE         LL_RTC_DisableIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+  * @brief  Enable Alarm B interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRBIE        LL_RTC_EnableIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+  * @brief  Disable Alarm B interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRBIE        LL_RTC_DisableIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+  * @brief  Enable Alarm A interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRAIE        LL_RTC_EnableIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+  * @brief  Disable Alarm A interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           ALRAIE        LL_RTC_DisableIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+  * @brief  Enable SSR Underflow interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           SSRUIE        LL_RTC_EnableIT_SSRU
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_SSRU(RTC_TypeDef *RTCx)
+{
+  SET_BIT(RTCx->CR, RTC_CR_SSRUIE);
+}
+
+/**
+  * @brief  Disable SSR Underflow interrupt
+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+  * @rmtoll RTC_CR           SSRUIE        LL_RTC_DisableIT_SSRU
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx)
+{
+  CLEAR_BIT(RTCx->CR, RTC_CR_SSRUIE);
+}
+
+/**
+  * @brief  Check if Time-stamp interrupt is enabled or not
+  * @rmtoll RTC_CR           TSIE          LL_RTC_IsEnabledIT_TS
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if Wakeup timer interrupt is enabled or not
+  * @rmtoll RTC_CR           WUTIE         LL_RTC_IsEnabledIT_WUT
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if Alarm B interrupt is enabled or not
+  * @rmtoll RTC_CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if Alarm A interrupt is enabled or not
+  * @rmtoll RTC_CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if SSR Underflow interrupt is enabled or not
+  * @rmtoll RTC_CR           SSRUIE        LL_RTC_IsEnabledIT_SSRU
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(const RTC_TypeDef *RTCx)
+{
+  return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Enable tamper 1 interrupt.
+  * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_EnableIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
+}
+
+/**
+  * @brief  Disable tamper 1 interrupt.
+  * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_DisableIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
+}
+
+/**
+  * @brief  Enable tamper 2 interrupt.
+  * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_EnableIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
+}
+
+/**
+  * @brief  Disable tamper 2 interrupt.
+  * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_DisableIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
+}
+
+/**
+  * @brief  Enable tamper 3 interrupt.
+  * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_EnableIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
+}
+
+/**
+  * @brief  Disable tamper 3 interrupt.
+  * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_DisableIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
+}
+
+/**
+  * @brief  Enable tamper 4 interrupt.
+  * @rmtoll TAMP_IER           TAMP4IE          LL_RTC_EnableIT_TAMP4
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
+}
+
+/**
+  * @brief  Disable tamper 4 interrupt.
+  * @rmtoll TAMP_IER           TAMP4IE          LL_RTC_DisableIT_TAMP4
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
+}
+
+/**
+  * @brief  Enable tamper 5 interrupt.
+  * @rmtoll TAMP_IER           TAMP5IE          LL_RTC_EnableIT_TAMP5
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
+}
+
+/**
+  * @brief  Disable tamper 5 interrupt.
+  * @rmtoll TAMP_IER           TAMP5IE          LL_RTC_DisableIT_TAMP5
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
+}
+
+/**
+  * @brief  Enable tamper 6 interrupt.
+  * @rmtoll TAMP_IER           TAMP6IE          LL_RTC_EnableIT_TAMP6
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
+}
+
+/**
+  * @brief  Disable tamper 6 interrupt.
+  * @rmtoll TAMP_IER           TAMP6IE          LL_RTC_DisableIT_TAMP6
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
+}
+
+/**
+  * @brief  Enable tamper 7 interrupt.
+  * @rmtoll TAMP_IER           TAMP7IE          LL_RTC_EnableIT_TAMP7
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
+}
+
+/**
+  * @brief  Disable tamper 7 interrupt.
+  * @rmtoll TAMP_IER           TAMP7IE          LL_RTC_DisableIT_TAMP7
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
+}
+
+/**
+  * @brief  Enable internal tamper 1 interrupt.
+  * @rmtoll TAMP_IER           ITAMP1IE          LL_RTC_EnableIT_ITAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
+}
+
+/**
+  * @brief  Disable internal tamper 1 interrupt.
+  * @rmtoll TAMP_IER           ITAMP1IE          LL_RTC_DisableIT_ITAMP1
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
+}
+
+/**
+  * @brief  Enable internal tamper 2 interrupt.
+  * @rmtoll TAMP_IER           ITAMP2IE          LL_RTC_EnableIT_ITAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
+}
+
+/**
+  * @brief  Disable internal tamper 2 interrupt.
+  * @rmtoll TAMP_IER           ITAMP2IE          LL_RTC_DisableIT_ITAMP2
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
+}
+
+/**
+  * @brief  Enable internal tamper 3 interrupt.
+  * @rmtoll TAMP_IER           ITAMP3IE          LL_RTC_EnableIT_ITAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
+}
+
+/**
+  * @brief  Disable internal tamper 3 interrupt.
+  * @rmtoll TAMP_IER           ITAMP3IE          LL_RTC_DisableIT_ITAMP3
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
+}
+
+/**
+  * @brief  Enable internal tamper 4 interrupt.
+  * @rmtoll TAMP_IER           ITAMP4IE          LL_RTC_EnableIT_ITAMP4
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP4IE);
+}
+
+/**
+  * @brief  Disable internal tamper 4 interrupt.
+  * @rmtoll TAMP_IER           ITAMP4IE          LL_RTC_DisableIT_ITAMP4
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP4IE);
+}
+
+/**
+  * @brief  Enable internal tamper 5 interrupt.
+  * @rmtoll TAMP_IER           ITAMP5IE          LL_RTC_EnableIT_ITAMP5
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
+}
+
+/**
+  * @brief  Disable internal tamper 5 interrupt.
+  * @rmtoll TAMP_IER           ITAMP5IE          LL_RTC_DisableIT_ITAMP5
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
+}
+
+/**
+  * @brief  Enable internal tamper 6 interrupt.
+  * @rmtoll TAMP_IER           ITAMP6IE          LL_RTC_EnableIT_ITAMP6
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
+}
+
+/**
+  * @brief  Disable internal tamper 6 interrupt.
+  * @rmtoll TAMP_IER           ITAMP6IE          LL_RTC_DisableIT_ITAMP6
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
+}
+
+/**
+  * @brief  Enable internal tamper 7 interrupt.
+  * @rmtoll TAMP_IER           ITAMP7IE          LL_RTC_EnableIT_ITAMP7
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
+}
+
+/**
+  * @brief  Disable internal tamper 7 interrupt.
+  * @rmtoll TAMP_IER           ITAMP7IE          LL_RTC_DisableIT_ITAMP7
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
+}
+
+/**
+  * @brief  Enable internal tamper 8 interrupt.
+  * @rmtoll TAMP_IER           ITAMP8IE          LL_RTC_EnableIT_ITAMP8
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
+}
+
+/**
+  * @brief  Disable internal tamper 8 interrupt.
+  * @rmtoll TAMP_IER           ITAMP8IE          LL_RTC_DisableIT_ITAMP8
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
+}
+
+/**
+  * @brief  Enable internal tamper 9 interrupt.
+  * @rmtoll TAMP_IER           ITAMP9IE          LL_RTC_EnableIT_ITAMP9
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
+}
+
+/**
+  * @brief  Disable internal tamper 9 interrupt.
+  * @rmtoll TAMP_IER           ITAMP9IE          LL_RTC_DisableIT_ITAMP9
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
+}
+
+/**
+  * @brief  Enable internal tamper 11 interrupt.
+  * @rmtoll TAMP_IER           ITAMP11IE          LL_RTC_EnableIT_ITAMP11
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
+}
+
+/**
+  * @brief  Disable internal tamper 11 interrupt.
+  * @rmtoll TAMP_IER           ITAMP11IE          LL_RTC_DisableIT_ITAMP11
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
+}
+
+/**
+  * @brief  Check if tamper 1 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if tamper 2 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           TAMP2IE        LL_RTC_IsEnabledIT_TAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if tamper 3 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           TAMP3IE        LL_RTC_IsEnabledIT_TAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if tamper 4 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           TAMP4IE        LL_RTC_IsEnabledIT_TAMP4
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if tamper 5 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           TAMP5IE        LL_RTC_IsEnabledIT_TAMP5
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if tamper 6 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           TAMP6IE        LL_RTC_IsEnabledIT_TAMP6
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if tamper 7 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           TAMP7IE        LL_RTC_IsEnabledIT_TAMP7
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 1 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP1IE        LL_RTC_IsEnabledIT_ITAMP1
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 2 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP2IE        LL_RTC_IsEnabledIT_ITAMP2
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 3 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP3IE        LL_RTC_IsEnabledIT_ITAMP3
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 4 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP4IE        LL_RTC_IsEnabledIT_ITAMP4
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP4IE) == (TAMP_IER_ITAMP4IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 5 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP5IE        LL_RTC_IsEnabledIT_ITAMP5
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 6 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP6IE        LL_RTC_IsEnabledIT_ITAMP6
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 7 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP7IE        LL_RTC_IsEnabledIT_ITAMP7
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 8 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP8IE        LL_RTC_IsEnabledIT_ITAMP8
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 9 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP9IE        LL_RTC_IsEnabledIT_ITAMP9
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP9IE) == (TAMP_IER_ITAMP9IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if internal tamper 11 interrupt is enabled or not.
+  * @rmtoll TAMP_IER           ITAMP11IE        LL_RTC_IsEnabledIT_ITAMP11
+  * @param  RTCx RTC Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP11IE) == (TAMP_IER_ITAMP11IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Increment Monotonic counter.
+  * @rmtoll TAMP_COUNT1R         COUNT        LL_RTC_IncrementMonotonicCounter
+  * @param  RTCx RTC Instance
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  WRITE_REG(TAMP->COUNT1R, 0U);
+}
+
+/**
+  * @brief  Increment Monotonic counter.
+  * @rmtoll TAMP_COUNT1R         COUNT        LL_RTC_GetMonotonicCounter
+  * @param  RTCx RTC Instance
+  * @retval Monotonic counter value.
+  */
+__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx)
+{
+  UNUSED(RTCx);
+  return READ_REG(TAMP->COUNT1R);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
+void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RTC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_RTC_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_sdmmc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_sdmmc.h
new file mode 100644
index 000000000..a091d50b1
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_sdmmc.h
@@ -0,0 +1,1321 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_sdmmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of SDMMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_SDMMC_H
+#define STM32N6xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+/** @addtogroup STM32N6xx_Driver
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+/** @addtogroup SDMMC_LL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SDMMC Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockEdge;            /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
+
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
+                                      disabled when the bus is idle.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
+
+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
+
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
+
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 1023   */
+
+#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U)
+  uint32_t TranceiverPresent;    /*!< Specifies if there is a 1V8 Transceiver/Switcher.
+                                      This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT       */
+#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */
+} SDMMC_InitTypeDef;
+
+
+/**
+  * @brief  SDMMC Command Control structure
+  */
+typedef struct
+{
+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
+                                     to a card as part of a command message. If a command
+                                     contains an argument, it must be loaded into this register
+                                     before writing the command to the command register.              */
+
+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
+                                     Max_Data = 64                                                    */
+
+  uint32_t Response;            /*!< Specifies the SDMMC response type.
+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
+
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is
+                                     enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
+
+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
+} SDMMC_CmdInitTypeDef;
+
+
+/**
+  * @brief  SDMMC Data Control structure
+  */
+typedef struct
+{
+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
+
+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
+
+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
+
+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+
+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
+
+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
+} SDMMC_DataInitTypeDef;
+
+/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
+  * @{
+  */
+typedef struct
+{
+  __IO uint32_t IDMALAR;              /*!< SDMMC DMA linked list configuration register  */
+  __IO uint32_t IDMABASER;            /*!< SDMMC DMA buffer base address register        */
+  __IO uint32_t IDMABSIZE;            /*!< SDMMC DMA buffer size register                */
+} SDMMC_DMALinkNodeTypeDef;
+
+typedef struct
+{
+  uint32_t BufferAddress;              /*!<  Node Buffer address                          */
+  uint32_t BufferSize ;                /*!<  Node Buffer size                             */
+} SDMMC_DMALinkNodeConfTypeDef;
+
+typedef struct
+{
+  SDMMC_DMALinkNodeTypeDef *pHeadNode;  /*!<  Linked List Node Head                        */
+  SDMMC_DMALinkNodeTypeDef *pTailNode;  /*!<  Linked List Node Head                        */
+  uint32_t NodesCounter ;               /*!<  Node is ready for execution                  */
+} SDMMC_DMALinkedListTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+  * @{
+  */
+#define SDMMC_ERROR_NONE                     ((uint32_t)0x00000000U)   /*!< No error                                                      */
+#define SDMMC_ERROR_CMD_CRC_FAIL             ((uint32_t)0x00000001U)   /*!< Command response received (but CRC check failed)              */
+#define SDMMC_ERROR_DATA_CRC_FAIL            ((uint32_t)0x00000002U)   /*!< Data block sent/received (CRC check failed)                   */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT          ((uint32_t)0x00000004U)   /*!< Command response timeout                                      */
+#define SDMMC_ERROR_DATA_TIMEOUT             ((uint32_t)0x00000008U)   /*!< Data timeout                                                  */
+#define SDMMC_ERROR_TX_UNDERRUN              ((uint32_t)0x00000010U)   /*!< Transmit FIFO underrun                                        */
+#define SDMMC_ERROR_RX_OVERRUN               ((uint32_t)0x00000020U)   /*!< Receive FIFO overrun                                          */
+#define SDMMC_ERROR_ADDR_MISALIGNED          ((uint32_t)0x00000040U)   /*!< Misaligned address                                            */
+#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length   */
+#define SDMMC_ERROR_ERASE_SEQ_ERR            ((uint32_t)0x00000100U)   /*!< An error in the sequence of erase command occurs              */
+#define SDMMC_ERROR_BAD_ERASE_PARAM          ((uint32_t)0x00000200U)   /*!< An invalid selection for erase groups                         */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION     ((uint32_t)0x00000400U)   /*!< Attempt to program a write protect block                      */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card    */
+#define SDMMC_ERROR_COM_CRC_FAILED           ((uint32_t)0x00001000U)   /*!< CRC check of the previous command failed                      */
+#define SDMMC_ERROR_ILLEGAL_CMD              ((uint32_t)0x00002000U)   /*!< Command is not legal for the card state                       */
+#define SDMMC_ERROR_CARD_ECC_FAILED          ((uint32_t)0x00004000U)   /*!< Card internal ECC was applied but failed to correct the data  */
+#define SDMMC_ERROR_CC_ERR                   ((uint32_t)0x00008000U)   /*!< Internal card controller error                                */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR      ((uint32_t)0x00010000U)   /*!< General or unknown error                                      */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN     ((uint32_t)0x00020000U)   /*!< The card could not sustain data reading in stream rmode       */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00040000U)   /*!< The card could not sustain data programming in stream mode    */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE        ((uint32_t)0x00080000U)   /*!< CID/CSD overwrite error                                       */
+#define SDMMC_ERROR_WP_ERASE_SKIP            ((uint32_t)0x00100000U)   /*!< Only partial address space was erased                         */
+#define SDMMC_ERROR_CARD_ECC_DISABLED        ((uint32_t)0x00200000U)   /*!< Command has been executed without using internal ECC          */
+#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out of erase sequence command was received                        */
+#define SDMMC_ERROR_AKE_SEQ_ERR              ((uint32_t)0x00800000U)   /*!< Error in sequence of authentication                           */
+#define SDMMC_ERROR_INVALID_VOLTRANGE        ((uint32_t)0x01000000U)   /*!< Error in case of invalid voltage range                        */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE        ((uint32_t)0x02000000U)   /*!< Error when addressed block is out of range                    */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE   ((uint32_t)0x04000000U)   /*!< Error when command request is not applicable                  */
+#define SDMMC_ERROR_INVALID_PARAMETER        ((uint32_t)0x08000000U)   /*!< the used parameter is not valid                               */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE      ((uint32_t)0x10000000U)   /*!< Error when feature is not insupported                         */
+#define SDMMC_ERROR_BUSY                     ((uint32_t)0x20000000U)   /*!< Error when transfer process is busy                           */
+#define SDMMC_ERROR_DMA                      ((uint32_t)0x40000000U)   /*!< Error while DMA transfer                                      */
+#define SDMMC_ERROR_TIMEOUT                  ((uint32_t)0x80000000U)   /*!< Timeout error                                                 */
+
+/**
+  * @brief  Masks for R5 Response
+  */
+/** this is the reserved for future use in spec RFU */
+#define SDMMC_SDIO_R5_ERROR                          ((uint32_t)0x00000400U)
+/** Out of range error */
+#define SDMMC_SDIO_R5_OUT_OF_RANGE                   ((uint32_t)0x00000100U)
+/** Invalid function number */
+#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER        ((uint32_t)0x00000200U)
+/** General or an unknown error */
+#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR          ((uint32_t)0x00000800U)
+/** SDIO Card current state
+  * 00=DIS (card not selected)
+  * 01=CMD (data line free)
+  * 10=TRN (transfer on data lines) */
+#define SDMMC_SDIO_R5_IO_CURRENT_STATE               ((uint32_t)0x00003000U)
+/** Illegal command error */
+#define SDMMC_SDIO_R5_ILLEGAL_CMD                    ((uint32_t)0x00004000U)
+/** CRC check of previous cmd failed */
+#define SDMMC_SDIO_R5_COM_CRC_FAILED                 ((uint32_t)0x00008000U)
+
+#define SDMMC_SDIO_R5_ERRORBITS                      (SDMMC_SDIO_R5_COM_CRC_FAILED          | \
+                                                      SDMMC_SDIO_R5_ILLEGAL_CMD             | \
+                                                      SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR   | \
+                                                      SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \
+                                                      SDMMC_SDIO_R5_OUT_OF_RANGE)
+/**
+  * @brief SDIO_CMD53_MODE
+  */
+#define SDMMC_SDIO_MODE_BYTE                         0x00U  /*!< Byte Mode  */
+#define SDMMC_SDIO_MODE_BLOCK                        0x01U  /*!< Block Mode */
+
+/**
+  * @brief SDIO_CMD53_OP_CODE
+  */
+#define SDMMC_SDIO_NO_INC                            0x00U  /*!< No auto indentation */
+#define SDMMC_SDIO_AUTO_INC                          0x01U  /*!< Auto indentation    */
+
+/**
+  * @brief SDIO_CMD53_RAW
+  */
+#define SDMMC_SDIO_WO                                0x00U  /*!< Write only Flag       */
+#define SDMMC_SDIO_RAW                               0x01U  /*!< Read after write Flag */
+
+/**
+  * @brief SDMMC Commands Index
+  */
+#define SDMMC_CMD_GO_IDLE_STATE                       0U   /*!< Resets the SD memory card.                                                               */
+#define SDMMC_CMD_SEND_OP_COND                        1U   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID                        2U   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SDMMC_CMD_SET_REL_ADDR                        3U   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SDMMC_CMD_SET_DSR                             4U   /*!< Programs the DSR of all cards.                                                           */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                   5U   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
+#define SDMMC_CMD_HS_SWITCH                           6U   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SDMMC_CMD_SEL_DESEL_CARD                      7U   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                     8U   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information  and asks the card whether card supports voltage.                      */
+#define SDMMC_CMD_SEND_CSD                            9U   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SDMMC_CMD_SEND_CID                            10U  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SDMMC_CMD_VOLTAGE_SWITCH                      11U  /*!< SD card Voltage switch to 1.8V mode.                                                     */
+#define SDMMC_CMD_STOP_TRANSMISSION                   12U  /*!< Forces the card to stop transmission.                                                    */
+#define SDMMC_CMD_SEND_STATUS                         13U  /*!< Addressed card sends its status register.                                                */
+#define SDMMC_CMD_HS_BUSTEST_READ                     14U  /*!< Reserved                                                                                 */
+#define SDMMC_CMD_GO_INACTIVE_STATE                   15U  /*!< Sends an addressed card into the inactive state.                                         */
+#define SDMMC_CMD_SET_BLOCKLEN                        16U  /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective        */
+/*!< for SDHS and SDXC.                                                                       */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                   17U  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                    */
+#define SDMMC_CMD_READ_MULT_BLOCK                     18U  /*!< Continuously transfers data blocks from card to host until interrupted by  STOP_TRANSMISSION command.                                                            */
+#define SDMMC_CMD_HS_BUSTEST_WRITE                    19U  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                20U  /*!< Speed class control command.                                                             */
+#define SDMMC_CMD_SET_BLOCK_COUNT                     23U  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  24U  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                   */
+#define SDMMC_CMD_WRITE_MULT_BLOCK                    25U  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SDMMC_CMD_PROG_CID                            26U  /*!< Reserved for manufacturers.                                                              */
+#define SDMMC_CMD_PROG_CSD                            27U  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SDMMC_CMD_SET_WRITE_PROT                      28U  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SDMMC_CMD_CLR_WRITE_PROT                      29U  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SDMMC_CMD_SEND_WRITE_PROT                     30U  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SDMMC_CMD_SD_ERASE_GRP_START                  32U  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SDMMC_CMD_SD_ERASE_GRP_END                    33U  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SDMMC_CMD_ERASE_GRP_START                     35U  /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6).                                  */
+#define SDMMC_CMD_ERASE_GRP_END                       36U  /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6).           */
+#define SDMMC_CMD_ERASE                               38U  /*!< Reserved for SD security applications.                                                   */
+#define SDMMC_CMD_FAST_IO                             39U  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_GO_IRQ_STATE                        40U  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_LOCK_UNLOCK                         42U  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.                                                */
+#define SDMMC_CMD_APP_CMD                             55U  /*!< Indicates to the card that the next command is an application specific command rather than a standard command.                                                   */
+#define SDMMC_CMD_GEN_CMD                             56U  /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands.                         */
+#define SDMMC_CMD_NO_CMD                              64U  /*!< No command                                                                               */
+
+/**
+  * @brief Following commands are SD Card Specific commands.
+  *        SDMMC_APP_CMD should be sent before sending these commands.
+  */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 6U   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register.                                                   */
+#define SDMMC_CMD_SD_APP_STATUS                       13U  /*!< (ACMD13) Sends the SD status.                                                            */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        22U  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block.                                                               */
+#define SDMMC_CMD_SD_APP_OP_COND                      41U  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          42U  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
+#define SDMMC_CMD_SD_APP_SEND_SCR                     51U  /*!< Reads the SD Configuration Register (SCR).                                               */
+#define SDMMC_CMD_SDMMC_RW_DIRECT                     52U  /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED                   53U  /*!< For SD I/O card only, reserved for security specification.                               */
+
+/**
+  * @brief Following commands are MMC Specific commands.
+  */
+#define SDMMC_CMD_MMC_SLEEP_AWAKE                     5U   /*!< Toggle the device between Sleep state and Standby state.                                 */
+
+/**
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDMMC_CMD_APP_CMD should be sent before sending these commands.
+  */
+#define SDMMC_CMD_SD_APP_GET_MKB                      43U
+#define SDMMC_CMD_SD_APP_GET_MID                      44U
+#define SDMMC_CMD_SD_APP_SET_CER_RN1                  45U
+#define SDMMC_CMD_SD_APP_GET_CER_RN2                  46U
+#define SDMMC_CMD_SD_APP_SET_CER_RES2                 47U
+#define SDMMC_CMD_SD_APP_GET_CER_RES1                 48U
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   18U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  25U
+#define SDMMC_CMD_SD_APP_SECURE_ERASE                 38U
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           49U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             48U
+
+/**
+  * @brief  Masks for errors Card Status R1 (OCR Register)
+  */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)
+#define SDMMC_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)
+#define SDMMC_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)
+#define SDMMC_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)
+#define SDMMC_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)
+#define SDMMC_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)
+#define SDMMC_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)
+#define SDMMC_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)
+#define SDMMC_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)
+#define SDMMC_OCR_CC_ERROR                 ((uint32_t)0x00100000U)
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)
+#define SDMMC_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)
+#define SDMMC_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)
+#define SDMMC_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)
+#define SDMMC_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)
+#define SDMMC_OCR_ERASE_RESET              ((uint32_t)0x00002000U)
+#define SDMMC_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)
+#define SDMMC_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)
+
+/**
+  * @brief  Masks for R6 Response
+  */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)
+#define SDMMC_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)
+#define SDMMC_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)
+
+#define SDMMC_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)
+#define SDMMC_HIGH_CAPACITY                ((uint32_t)0x40000000U)
+#define SDMMC_STD_CAPACITY                 ((uint32_t)0x00000000U)
+#define SDMMC_CHECK_PATTERN                ((uint32_t)0x000001AAU)
+#define SD_SWITCH_1_8V_CAPACITY            ((uint32_t)0x01000000U)
+#define SDMMC_DDR50_SWITCH_PATTERN         ((uint32_t)0x80FFFF04U)
+#define SDMMC_SDR104_SWITCH_PATTERN        ((uint32_t)0x80FF1F03U)
+#define SDMMC_SDR50_SWITCH_PATTERN         ((uint32_t)0x80FF1F02U)
+#define SDMMC_SDR25_SWITCH_PATTERN         ((uint32_t)0x80FFFF01U)
+#define SDMMC_SDR12_SWITCH_PATTERN         ((uint32_t)0x80FFFF00U)
+
+#define SDMMC_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_MAX_TRIAL                    ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_ALLZERO                      ((uint32_t)0x00000000U)
+
+#define SDMMC_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)
+#define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
+#define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)
+
+#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */
+#define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
+#endif /* SDMMC_DATATIMEOUT */
+
+#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
+#define SDMMC_SWDATATIMEOUT                ((uint32_t)0xFFFFFFFFU)
+#endif /* SDMMC_SWDATATIMEOUT */
+
+#define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)
+#define SDMMC_8TO15BITS                    ((uint32_t)0x0000FF00U)
+#define SDMMC_16TO23BITS                   ((uint32_t)0x00FF0000U)
+#define SDMMC_24TO31BITS                   ((uint32_t)0xFF000000U)
+#define SDMMC_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)
+
+#define SDMMC_HALFFIFO                     ((uint32_t)0x00000008U)
+#define SDMMC_HALFFIFOBYTES                ((uint32_t)0x00000020U)
+
+/* SDMMC FIFO Size */
+#define SDMMC_FIFO_SIZE 512U
+/**
+  * @brief  Command Class supported
+  */
+#define SDMMC_CCCC_ERASE                   ((uint32_t)0x00000020U)
+
+#define SDMMC_CMDTIMEOUT                   ((uint32_t)5000U)        /* Command send and response timeout     */
+#define SDMMC_MAXERASETIMEOUT              ((uint32_t)63000U)       /* Max erase Timeout 63 s                */
+#define SDMMC_STOPTRANSFERTIMEOUT          ((uint32_t)100000000U)   /* Timeout for STOP TRANSMISSION command */
+
+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
+  * @{
+  */
+#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
+
+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
+                                   ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
+  * @{
+  */
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)
+#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
+
+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
+                                         ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Bus_Wide Bus Width
+  * @{
+  */
+#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000U)
+#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
+#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
+
+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
+                                 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+                                 ((WIDE) == SDMMC_BUS_WIDE_8B))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Speed_Mode
+  * @{
+  */
+#define SDMMC_SPEED_MODE_AUTO                  ((uint32_t)0x00000000U)
+#define SDMMC_SPEED_MODE_DEFAULT               ((uint32_t)0x00000001U)
+#define SDMMC_SPEED_MODE_HIGH                  ((uint32_t)0x00000002U)
+#define SDMMC_SPEED_MODE_ULTRA                 ((uint32_t)0x00000003U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR104          SDMMC_SPEED_MODE_ULTRA
+#define SDMMC_SPEED_MODE_DDR                   ((uint32_t)0x00000004U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR50           ((uint32_t)0x00000005U)
+
+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO)         || \
+                                   ((MODE) == SDMMC_SPEED_MODE_DEFAULT)      || \
+                                   ((MODE) == SDMMC_SPEED_MODE_HIGH)         || \
+                                   ((MODE) == SDMMC_SPEED_MODE_ULTRA)        || \
+                                   ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50)  || \
+                                   ((MODE) == SDMMC_SPEED_MODE_DDR))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
+  * @{
+  */
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)
+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
+
+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
+                                                 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Clock_Division Clock Division
+  * @{
+  */
+/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
+#define IS_SDMMC_CLKDIV(DIV)   ((DIV) < 0x400U)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present
+  * @{
+  */
+#define SDMMC_TRANSCEIVER_UNKNOWN             ((uint32_t)0x00000000U)
+#define SDMMC_TRANSCEIVER_NOT_PRESENT         ((uint32_t)0x00000001U)
+#define SDMMC_TRANSCEIVER_PRESENT             ((uint32_t)0x00000002U)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Command_Index Command Index
+  * @{
+  */
+#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Response_Type Response Type
+  * @{
+  */
+#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000U)
+#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
+#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
+
+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
+                                     ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+                                     ((RESPONSE) == SDMMC_RESPONSE_LONG))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
+  * @{
+  */
+#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000U)
+#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT
+#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
+
+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
+                             ((WAIT) == SDMMC_WAIT_IT) || \
+                             ((WAIT) == SDMMC_WAIT_PEND))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_CPSM_State CPSM State
+  * @{
+  */
+#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000U)
+#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
+
+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
+                             ((CPSM) == SDMMC_CPSM_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Response_Registers Response Register
+  * @{
+  */
+#define SDMMC_RESP1                          ((uint32_t)0x00000000U)
+#define SDMMC_RESP2                          ((uint32_t)0x00000004U)
+#define SDMMC_RESP3                          ((uint32_t)0x00000008U)
+#define SDMMC_RESP4                          ((uint32_t)0x0000000CU)
+
+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
+                             ((RESP) == SDMMC_RESP2) || \
+                             ((RESP) == SDMMC_RESP3) || \
+                             ((RESP) == SDMMC_RESP4))
+
+/** @defgroup SDMMC_Internal_DMA_Mode  SDMMC Internal DMA Mode
+  * @{
+  */
+#define SDMMC_DISABLE_IDMA              ((uint32_t)0x00000000)
+#define SDMMC_ENABLE_IDMA_SINGLE_BUFF   (SDMMC_IDMA_IDMAEN)
+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0  (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1  (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Length Data Length
+  * @{
+  */
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
+  * @{
+  */
+#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)
+#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
+#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
+#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
+#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
+#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
+#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1| \
+                                               SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
+  * @{
+  */
+#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR
+
+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
+                                    ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
+  * @{
+  */
+#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)
+#define SDMMC_TRANSFER_MODE_SDIO              SDMMC_DCTRL_DTMODE_0
+#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE_1
+
+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
+                                      ((MODE) == SDMMC_TRANSFER_MODE_SDIO)  || \
+                                      ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_DPSM_State DPSM State
+  * @{
+  */
+#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000U)
+#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
+
+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
+                             ((DPSM) == SDMMC_DPSM_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
+  * @{
+  */
+#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)
+#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
+
+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
+                                      ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
+  * @{
+  */
+#define SDMMC_IT_CCRCFAIL                  SDMMC_MASK_CCRCFAILIE
+#define SDMMC_IT_DCRCFAIL                  SDMMC_MASK_DCRCFAILIE
+#define SDMMC_IT_CTIMEOUT                  SDMMC_MASK_CTIMEOUTIE
+#define SDMMC_IT_DTIMEOUT                  SDMMC_MASK_DTIMEOUTIE
+#define SDMMC_IT_TXUNDERR                  SDMMC_MASK_TXUNDERRIE
+#define SDMMC_IT_RXOVERR                   SDMMC_MASK_RXOVERRIE
+#define SDMMC_IT_CMDREND                   SDMMC_MASK_CMDRENDIE
+#define SDMMC_IT_CMDSENT                   SDMMC_MASK_CMDSENTIE
+#define SDMMC_IT_DATAEND                   SDMMC_MASK_DATAENDIE
+#define SDMMC_IT_DHOLD                     SDMMC_MASK_DHOLDIE
+#define SDMMC_IT_DBCKEND                   SDMMC_MASK_DBCKENDIE
+#define SDMMC_IT_DABORT                    SDMMC_MASK_DABORTIE
+#define SDMMC_IT_TXFIFOHE                  SDMMC_MASK_TXFIFOHEIE
+#define SDMMC_IT_RXFIFOHF                  SDMMC_MASK_RXFIFOHFIE
+#define SDMMC_IT_RXFIFOF                   SDMMC_MASK_RXFIFOFIE
+#define SDMMC_IT_TXFIFOE                   SDMMC_MASK_TXFIFOEIE
+#define SDMMC_IT_BUSYD0END                 SDMMC_MASK_BUSYD0ENDIE
+#define SDMMC_IT_SDIOIT                    SDMMC_MASK_SDIOITIE
+#define SDMMC_IT_ACKFAIL                   SDMMC_MASK_ACKFAILIE
+#define SDMMC_IT_ACKTIMEOUT                SDMMC_MASK_ACKTIMEOUTIE
+#define SDMMC_IT_VSWEND                    SDMMC_MASK_VSWENDIE
+#define SDMMC_IT_CKSTOP                    SDMMC_MASK_CKSTOPIE
+#define SDMMC_IT_IDMABTC                   SDMMC_MASK_IDMABTCIE
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Flags Flags
+  * @{
+  */
+#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
+#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
+#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
+#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
+#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
+#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
+#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
+#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
+#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
+#define SDMMC_FLAG_DHOLD                     SDMMC_STA_DHOLD
+#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
+#define SDMMC_FLAG_DABORT                    SDMMC_STA_DABORT
+#define SDMMC_FLAG_DPSMACT                   SDMMC_STA_DPSMACT
+#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CPSMACT
+#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
+#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
+#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
+#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
+#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
+#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
+#define SDMMC_FLAG_BUSYD0                    SDMMC_STA_BUSYD0
+#define SDMMC_FLAG_BUSYD0END                 SDMMC_STA_BUSYD0END
+#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
+#define SDMMC_FLAG_ACKFAIL                   SDMMC_STA_ACKFAIL
+#define SDMMC_FLAG_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT
+#define SDMMC_FLAG_VSWEND                    SDMMC_STA_VSWEND
+#define SDMMC_FLAG_CKSTOP                    SDMMC_STA_CKSTOP
+#define SDMMC_FLAG_IDMATE                    SDMMC_STA_IDMATE
+#define SDMMC_FLAG_IDMABTC                   SDMMC_STA_IDMABTC
+
+#define SDMMC_STATIC_FLAGS             ((uint32_t)(SDMMC_FLAG_CCRCFAIL   | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+                                                   SDMMC_FLAG_DTIMEOUT   | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\
+                                                   SDMMC_FLAG_CMDREND    | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\
+                                                   SDMMC_FLAG_DHOLD      | SDMMC_FLAG_DBCKEND  | SDMMC_FLAG_DABORT   |\
+                                                   SDMMC_FLAG_BUSYD0END  | SDMMC_FLAG_SDIOIT   | SDMMC_FLAG_ACKFAIL  |\
+                                                   SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND   | SDMMC_FLAG_CKSTOP   |\
+                                                   SDMMC_FLAG_IDMATE     | SDMMC_FLAG_IDMABTC))
+
+#define SDMMC_STATIC_CMD_FLAGS         ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT  | SDMMC_FLAG_CMDREND   |\
+                                                   SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_BUSYD0END))
+
+#define SDMMC_STATIC_DATA_FLAGS        ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR   |\
+                                                   SDMMC_FLAG_RXOVERR  | SDMMC_FLAG_DATAEND  | SDMMC_FLAG_DHOLD      |\
+                                                   SDMMC_FLAG_DBCKEND  | SDMMC_FLAG_DABORT   | SDMMC_FLAG_IDMATE     |\
+                                                   SDMMC_FLAG_IDMABTC))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_SDIO_CCCR_Registers
+  * @{
+  */
+/*-------------------------------- CCCR0 ----------------------------------*/
+#define SDMMC_SDIO_CCCR0                     0x000U  /*!< SDIOS Card Common Control Register 0        */
+#define SDMMC_SDIO_CCCR0_SD_BYTE0            0x000U  /*!< SDIOS Card Common Control Register 0 Byte 0 */
+#define SDMMC_SDIO_CCCR0_SD_BYTE1            0x001U  /*!< SDIOS Card Common Control Register 0 Byte 1 */
+#define SDMMC_SDIO_CCCR0_SD_BYTE2            0x002U  /*!< SDIOS Card Common Control Register 0 Byte 2 */
+#define SDMMC_SDIO_CCCR0_SD_BYTE3            0x003U  /*!< SDIOS Card Common Control Register 0 Byte 3 */
+
+/*-------------------------------- CCCR4 ----------------------------------*/
+#define SDMMC_SDIO_CCCR4                     0x004U  /*!< SDIOS Card Common Control Register 4        */
+#define SDMMC_SDIO_CCCR4_SD_BYTE0            0x004U  /*!< SDIOS Card Common Control Register 4 Byte 0 */
+#define SDMMC_SDIO_CCCR4_SD_BYTE1            0x005U  /*!< SDIOS Card Common Control Register 4 Byte 1 */
+#define SDMMC_SDIO_CCCR4_SD_BYTE2            0x006U  /*!< SDIOS Card Common Control Register 4 Byte 2 */
+#define SDMMC_SDIO_CCCR4_SD_BYTE3            0x007U  /*!< SDIOS Card Common Control Register 4 Byte 3 */
+
+/*-------------------------------- CCCR8 ----------------------------------*/
+#define SDMMC_SDIO_CCCR8                     0x008U  /*!< SDIOS Card Common Control Register 8        */
+#define SDMMC_SDIO_CCCR8_SD_BYTE0            0x008U  /*!< SDIOS Card Common Control Register 8 Byte 0 */
+#define SDMMC_SDIO_CCCR8_SD_BYTE1            0x009U  /*!< SDIOS Card Common Control Register 8 Byte 1 */
+#define SDMMC_SDIO_CCCR8_SD_BYTE2            0x00AU  /*!< SDIOS Card Common Control Register 8 Byte 2 */
+#define SDMMC_SDIO_CCCR8_SD_BYTE3            0x00BU  /*!< SDIOS Card Common Control Register 8 Byte 3 */
+
+/*-------------------------------- CCCR12 ---------------------------------*/
+#define SDMMC_SDIO_CCCR12                    0x00CU  /*!< SDIOS Card Common Control Register 12        */
+#define SDMMC_SDIO_CCCR12_SD_BYTE0           0x00CU  /*!< SDIOS Card Common Control Register 12 Byte 0 */
+#define SDMMC_SDIO_CCCR12_SD_BYTE1           0x00DU  /*!< SDIOS Card Common Control Register 12 Byte 1 */
+#define SDMMC_SDIO_CCCR12_SD_BYTE2           0x00EU  /*!< SDIOS Card Common Control Register 12 Byte 2 */
+#define SDMMC_SDIO_CCCR12_SD_BYTE3           0x00FU  /*!< SDIOS Card Common Control Register 12 Byte 3 */
+
+/*-------------------------------- CCCR16 ---------------------------------*/
+#define SDMMC_SDIO_CCCR16                    0x010U  /*!< SDIOS Card Common Control Register 16        */
+#define SDMMC_SDIO_CCCR16_SD_BYTE0           0x010U  /*!< SDIOS Card Common Control Register 16 Byte 0 */
+#define SDMMC_SDIO_CCCR16_SD_BYTE1           0x011U  /*!< SDIOS Card Common Control Register 16 Byte 1 */
+#define SDMMC_SDIO_CCCR16_SD_BYTE2           0x012U  /*!< SDIOS Card Common Control Register 16 Byte 2 */
+#define SDMMC_SDIO_CCCR16_SD_BYTE3           0x013U  /*!< SDIOS Card Common Control Register 16 Byte 3 */
+
+/*-------------------------------- CCCR20 ---------------------------------*/
+#define SDMMC_SDIO_CCCR20                    0x014U  /*!< SDIOS Card Common Control Register 20        */
+#define SDMMC_SDIO_CCCR20_SD_BYTE0           0x014U  /*!< SDIOS Card Common Control Register 20 Byte 0 */
+#define SDMMC_SDIO_CCCR20_SD_BYTE1           0x015U  /*!< SDIOS Card Common Control Register 20 Byte 1 */
+#define SDMMC_SDIO_CCCR20_SD_BYTE2           0x016U  /*!< SDIOS Card Common Control Register 20 Byte 2 */
+#define SDMMC_SDIO_CCCR20_SD_BYTE3           0x017U  /*!< SDIOS Card Common Control Register 20 Byte 3 */
+
+/*-------------------------------- F1BR0 ----------------------------------*/
+#define SDMMC_SDIO_F1BR0                     0x100U  /*!< SDIOS Function 1 Basic Register 0        */
+#define SDMMC_SDIO_F1BR0_SD_BYTE0            0x100U  /*!< SDIOS Function 1 Basic Register 0 Byte 0 */
+#define SDMMC_SDIO_F1BR0_SD_BYTE1            0x101U  /*!< SDIOS Function 1 Basic Register 0 Byte 1 */
+#define SDMMC_SDIO_F1BR0_SD_BYTE2            0x102U  /*!< SDIOS Function 1 Basic Register 0 Byte 2 */
+#define SDMMC_SDIO_F1BR0_SD_BYTE3            0x103U  /*!< SDIOS Function 1 Basic Register 0 Byte 3 */
+
+/*-------------------------------- F1BR8 ----------------------------------*/
+#define SDMMC_SDIO_F1BR8                     0x108U  /*!< SDIOS Function 1 Basic Register 8        */
+#define SDMMC_SDIO_F1BR8_SD_BYTE0            0x108U  /*!< SDIOS Function 1 Basic Register 8 Byte 0 */
+#define SDMMC_SDIO_F1BR8_SD_BYTE1            0x109U  /*!< SDIOS Function 1 Basic Register 8 Byte 1 */
+#define SDMMC_SDIO_F1BR8_SD_BYTE2            0x10AU  /*!< SDIOS Function 1 Basic Register 8 Byte 2 */
+#define SDMMC_SDIO_F1BR8_SD_BYTE3            0x10BU  /*!< SDIOS Function 1 Basic Register 8 Byte 3 */
+
+/*-------------------------------- F1BR12 ---------------------------------*/
+#define SDMMC_SDIO_F1BR12                    0x10CU  /*!< SDIOS Function 1 Basic Register 12        */
+#define SDMMC_SDIO_F1BR12_SD_BYTE0           0x10CU  /*!< SDIOS Function 1 Basic Register 12 Byte 0 */
+#define SDMMC_SDIO_F1BR12_SD_BYTE1           0x10DU  /*!< SDIOS Function 1 Basic Register 12 Byte 1 */
+#define SDMMC_SDIO_F1BR12_SD_BYTE2           0x10EU  /*!< SDIOS Function 1 Basic Register 12 Byte 2 */
+#define SDMMC_SDIO_F1BR12_SD_BYTE3           0x10FU  /*!< SDIOS Function 1 Basic Register 12 Byte 3 */
+
+/*-------------------------------- F1BR16 ---------------------------------*/
+#define SDMMC_SDIO_F1BR16                    0x110U  /*!< SDIOS Function 1 Basic Register 16        */
+#define SDMMC_SDIO_F1BR16_SD_BYTE0           0x110U  /*!< SDIOS Function 1 Basic Register 16 Byte 0 */
+#define SDMMC_SDIO_F1BR16_SD_BYTE1           0x111U  /*!< SDIOS Function 1 Basic Register 16 Byte 1 */
+#define SDMMC_SDIO_F1BR16_SD_BYTE2           0x112U  /*!< SDIOS Function 1 Basic Register 16 Byte 2 */
+#define SDMMC_SDIO_F1BR16_SD_BYTE3           0x113U  /*!< SDIOS Function 1 Basic Register 16 Byte 3 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+  * @{
+  */
+
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+  * @brief SDMMC_LL registers bit address in the alias region
+  * @{
+  */
+/* ---------------------- SDMMC registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
+                                             SDMMC_CLKCR_WIDBUS |\
+                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\
+                                             SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\
+                                             SDMMC_CLKCR_SELCLKRX))
+
+/* --- DCTRL Register ---*/
+/* SDMMC DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
+                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
+                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
+                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_CMDSUSPEND))
+
+/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
+
+/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
+#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4)
+
+/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
+#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+  *  @brief macros to handle interrupts and specific clock configurations
+  * @{
+  */
+
+/**
+  * @brief  Enable the SDMMC device interrupt.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDMMC device interrupt.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDMMC flag is set or not.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty
+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval The new state of SDMMC_FLAG (SET or RESET).
+  */
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
+
+
+/**
+  * @brief  Clears the SDMMC pending flags.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)
+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected
+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received
+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received
+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion
+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure
+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error
+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete
+  * @retval None
+  */
+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval The new state of SDMMC_IT (SET or RESET).
+  */
+#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Checks the source of specified interrupt.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval The new state of SDMMC_IT (SET or RESET).
+  */
+#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__)))
+
+/**
+  * @brief  Clears the SDMMC's interrupt pending bits.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
+  * @retval None
+  */
+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Enable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
+
+/**
+  * @brief  Disable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
+
+/**
+  * @brief  Enable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
+
+/**
+  * @brief  Disable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
+
+/**
+  * @brief  Enable the CMDTRANS mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
+
+/**
+  * @brief  Disable the CMDTRANS mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
+
+/**
+  * @brief  Enable the CMDSTOP mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)
+
+/**
+  * @brief  Disable the CMDSTOP mode.
+  * @param  __INSTANCE__ Pointer to SDMMC register base
+  * @retval None
+  */
+#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
+/**
+  * @}
+  */
+
+/* I/O operation functions  *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+  * @{
+  */
+uint32_t          SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command);
+uint8_t           SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data);
+uint32_t          SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+/**
+  * @}
+  */
+
+/* SDMMC Commands management functions ******************************************/
+/** @addtogroup HAL_SDMMC_LL_Group4
+  * @{
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount);
+uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse);
+uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp);
+/**
+  * @}
+  */
+
+/* SDMMC Responses management functions *****************************************/
+/** @addtogroup HAL_SDMMC_LL_Group5
+  * @{
+  */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp);
+uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData);
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
+/**
+  * @}
+  */
+
+/* Linked List functions  *******************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group6
+  * @{
+  */
+uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf);
+uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode,
+                                        SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode);
+uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SDMMC1 || SDMMC2 */
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_SDMMC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_spi.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_spi.h
new file mode 100644
index 000000000..07feba444
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_spi.h
@@ -0,0 +1,3662 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_spi.h
+  * @author  MCD Application Team
+  * @brief   Header file of SPI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_SPI_H
+#define STM32N6xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
+
+/** @defgroup SPI_LL SPI
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_Exported_Types SPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Init structures definition
+  */
+typedef struct
+{
+  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetTransferDirection().*/
+
+  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetMode().*/
+
+  uint32_t DataWidth;               /*!< Specifies the SPI data width.
+                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetDataWidth().*/
+
+  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetClockPolarity().*/
+
+  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetClockPhase().*/
+
+  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
+                                         or by software using the SSI bit.
+
+                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetNSSMode().*/
+
+  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure
+                                         the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+                                         @note The communication clock is derived from the master clock.
+                                         The slave clock does not need to be set.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetBaudRatePrescaler().*/
+
+  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetTransferBitOrder().*/
+
+  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
+                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+                                         This feature can be modified afterwards using unitary functions
+                                         @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
+                                         This parameter must be a number between Min_Data = 0x00
+                                         and Max_Data = 0xFFFFFFFF.
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
+  * @{
+  */
+#define LL_SPI_SR_RXP                              (SPI_SR_RXP)
+#define LL_SPI_SR_TXP                              (SPI_SR_TXP)
+#define LL_SPI_SR_DXP                              (SPI_SR_DXP)
+#define LL_SPI_SR_EOT                              (SPI_SR_EOT)
+#define LL_SPI_SR_TXTF                             (SPI_SR_TXTF)
+#define LL_SPI_SR_UDR                              (SPI_SR_UDR)
+#define LL_SPI_SR_CRCE                             (SPI_SR_CRCE)
+#define LL_SPI_SR_MODF                             (SPI_SR_MODF)
+#define LL_SPI_SR_OVR                              (SPI_SR_OVR)
+#define LL_SPI_SR_TIFRE                            (SPI_SR_TIFRE)
+#define LL_SPI_SR_SUSP                             (SPI_SR_SUSP)
+#define LL_SPI_SR_TXC                              (SPI_SR_TXC)
+#define LL_SPI_SR_RXWNE                            (SPI_SR_RXWNE)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
+  * @{
+  */
+#define LL_SPI_IER_RXPIE                           (SPI_IER_RXPIE)
+#define LL_SPI_IER_TXPIE                           (SPI_IER_TXPIE)
+#define LL_SPI_IER_DXPIE                           (SPI_IER_DXPIE)
+#define LL_SPI_IER_EOTIE                           (SPI_IER_EOTIE)
+#define LL_SPI_IER_TXTFIE                          (SPI_IER_TXTFIE)
+#define LL_SPI_IER_UDRIE                           (SPI_IER_UDRIE)
+#define LL_SPI_IER_OVRIE                           (SPI_IER_OVRIE)
+#define LL_SPI_IER_CRCEIE                          (SPI_IER_CRCEIE)
+#define LL_SPI_IER_TIFREIE                         (SPI_IER_TIFREIE)
+#define LL_SPI_IER_MODFIE                          (SPI_IER_MODFIE)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_SPI_MODE_MASTER                         (SPI_CFG2_MASTER)
+#define LL_SPI_MODE_SLAVE                          (0x00000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_SS_LEVEL SS Level
+  * @{
+  */
+#define LL_SPI_SS_LEVEL_HIGH                       (SPI_CR1_SSI)
+#define LL_SPI_SS_LEVEL_LOW                        (0x00000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
+  * @{
+  */
+#define LL_SPI_SS_IDLENESS_00CYCLE                 (0x00000000UL)
+#define LL_SPI_SS_IDLENESS_01CYCLE                 (SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_02CYCLE                 (SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_03CYCLE                 (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_04CYCLE                 (SPI_CFG2_MSSI_2)
+#define LL_SPI_SS_IDLENESS_05CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_06CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_07CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_08CYCLE                 (SPI_CFG2_MSSI_3)
+#define LL_SPI_SS_IDLENESS_09CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_10CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_11CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_12CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
+#define LL_SPI_SS_IDLENESS_13CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_14CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
+#define LL_SPI_SS_IDLENESS_15CYCLE                 (SPI_CFG2_MSSI_3\
+                                                    | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
+  * @{
+  */
+#define LL_SPI_ID_IDLENESS_00CYCLE                 (0x00000000UL)
+#define LL_SPI_ID_IDLENESS_01CYCLE                 (SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_02CYCLE                 (SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_03CYCLE                 (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_04CYCLE                 (SPI_CFG2_MIDI_2)
+#define LL_SPI_ID_IDLENESS_05CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_06CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_07CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_08CYCLE                 (SPI_CFG2_MIDI_3)
+#define LL_SPI_ID_IDLENESS_09CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_10CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_11CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_12CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
+#define LL_SPI_ID_IDLENESS_13CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_14CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
+#define LL_SPI_ID_IDLENESS_15CYCLE                 (SPI_CFG2_MIDI_3\
+                                                    | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
+  * @{
+  */
+#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN          (0x00000000UL)
+#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN          (SPI_CR1_TCRCINI)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
+  * @{
+  */
+#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN          (0x00000000UL)
+#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN          (SPI_CR1_RCRCINI)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
+  * @{
+  */
+#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN         (0x00000000UL)
+#define LL_SPI_UDR_CONFIG_LAST_RECEIVED            (SPI_CFG1_UDRCFG)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Protocol
+  * @{
+  */
+#define LL_SPI_PROTOCOL_MOTOROLA                   (0x00000000UL)
+#define LL_SPI_PROTOCOL_TI                         (SPI_CFG2_SP_0)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_PHASE Phase
+  * @{
+  */
+#define LL_SPI_PHASE_1EDGE                         (0x00000000UL)
+#define LL_SPI_PHASE_2EDGE                         (SPI_CFG2_CPHA)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_POLARITY Polarity
+  * @{
+  */
+#define LL_SPI_POLARITY_LOW                        (0x00000000UL)
+#define LL_SPI_POLARITY_HIGH                       (SPI_CFG2_CPOL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
+  * @{
+  */
+#define LL_SPI_NSS_POLARITY_LOW                    (0x00000000UL)
+#define LL_SPI_NSS_POLARITY_HIGH                   (SPI_CFG2_SSIOP)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+  * @{
+  */
+#define LL_SPI_BAUDRATEPRESCALER_BYPASS            (SPI_CFG1_BPASS)
+#define LL_SPI_BAUDRATEPRESCALER_DIV2              (0x00000000UL)
+#define LL_SPI_BAUDRATEPRESCALER_DIV4              (SPI_CFG1_MBR_0)
+#define LL_SPI_BAUDRATEPRESCALER_DIV8              (SPI_CFG1_MBR_1)
+#define LL_SPI_BAUDRATEPRESCALER_DIV16             (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
+#define LL_SPI_BAUDRATEPRESCALER_DIV32             (SPI_CFG1_MBR_2)
+#define LL_SPI_BAUDRATEPRESCALER_DIV64             (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
+#define LL_SPI_BAUDRATEPRESCALER_DIV128            (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
+#define LL_SPI_BAUDRATEPRESCALER_DIV256            (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
+  * @{
+  */
+#define LL_SPI_LSB_FIRST                           (SPI_CFG2_LSBFRST)
+#define LL_SPI_MSB_FIRST                           (0x00000000UL)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+  * @{
+  */
+#define LL_SPI_FULL_DUPLEX                         (0x00000000UL)
+#define LL_SPI_SIMPLEX_TX                          (SPI_CFG2_COMM_0)
+#define LL_SPI_SIMPLEX_RX                          (SPI_CFG2_COMM_1)
+#define LL_SPI_HALF_DUPLEX_RX                      (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
+#define LL_SPI_HALF_DUPLEX_TX                      (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Data Width
+  * @{
+  */
+#define LL_SPI_DATAWIDTH_4BIT                      (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_5BIT                      (SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_6BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_7BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_8BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_9BIT                      (SPI_CFG1_DSIZE_3)
+#define LL_SPI_DATAWIDTH_10BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_11BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_12BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_13BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_14BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_15BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_16BIT                     (SPI_CFG1_DSIZE_3\
+                                                    | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_17BIT                     (SPI_CFG1_DSIZE_4)
+#define LL_SPI_DATAWIDTH_18BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_19BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_20BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_21BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_22BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_23BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_24BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_25BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
+#define LL_SPI_DATAWIDTH_26BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_27BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_28BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_29BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
+#define LL_SPI_DATAWIDTH_30BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_31BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_32BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
+                                                    | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
+  * @{
+  */
+#define LL_SPI_FIFO_TH_01DATA                      (0x00000000UL)
+#define LL_SPI_FIFO_TH_02DATA                      (SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_03DATA                      (SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_04DATA                      (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_05DATA                      (SPI_CFG1_FTHLV_2)
+#define LL_SPI_FIFO_TH_06DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_07DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_08DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_09DATA                      (SPI_CFG1_FTHLV_3)
+#define LL_SPI_FIFO_TH_10DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_11DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_12DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_13DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
+#define LL_SPI_FIFO_TH_14DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_15DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
+#define LL_SPI_FIFO_TH_16DATA                      (SPI_CFG1_FTHLV_3\
+                                                    | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+  * @{
+  */
+#define LL_SPI_CRCCALCULATION_DISABLE              (0x00000000UL)            /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE               (SPI_CFG1_CRCEN)          /*!< CRC calculation enabled  */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC CRC
+  * @{
+  */
+#define LL_SPI_CRC_4BIT                            (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_5BIT                            (SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_6BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_7BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_8BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_9BIT                            (SPI_CFG1_CRCSIZE_3)
+#define LL_SPI_CRC_10BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_11BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_12BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_13BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_14BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_15BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_16BIT                           (SPI_CFG1_CRCSIZE_3\
+                                                    | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_17BIT                           (SPI_CFG1_CRCSIZE_4)
+#define LL_SPI_CRC_18BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_19BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_20BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_21BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_22BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_23BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_24BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_25BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
+#define LL_SPI_CRC_26BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_27BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_28BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_29BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
+#define LL_SPI_CRC_30BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_31BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_32BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
+                                                    | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
+  * @{
+  */
+#define LL_SPI_NSS_SOFT                            (SPI_CFG2_SSM)
+#define LL_SPI_NSS_HARD_INPUT                      (0x00000000UL)
+#define LL_SPI_NSS_HARD_OUTPUT                     (SPI_CFG2_SSOE)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
+  * @{
+  */
+#define LL_SPI_RX_FIFO_0PACKET               (0x00000000UL)    /* 0 or multiple of 4 packet available is the RxFIFO */
+#define LL_SPI_RX_FIFO_1PACKET               (SPI_SR_RXPLVL_0)
+#define LL_SPI_RX_FIFO_2PACKET               (SPI_SR_RXPLVL_1)
+#define LL_SPI_RX_FIFO_3PACKET               (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in SPI register
+  * @param  __INSTANCE__ SPI Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable SPI peripheral
+  * @rmtoll CR1          SPE           LL_SPI_Enable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Disable SPI peripheral
+  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
+  * @rmtoll CR1          SPE           LL_SPI_Disable
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Check if SPI peripheral is enabled
+  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Swap the MOSI and MISO pin
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG2         IOSWP         LL_SPI_EnableIOSwap
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
+}
+
+/**
+  * @brief  Restore default function for MOSI and MISO pin
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG2         IOSWP         LL_SPI_DisableIOSwap
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
+}
+
+/**
+  * @brief  Check if MOSI and MISO pin are swapped
+  * @rmtoll CFG2         IOSWP         LL_SPI_IsEnabledIOSwap
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable GPIO control
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG2         AFCNTR        LL_SPI_EnableGPIOControl
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
+}
+
+/**
+  * @brief  Disable GPIO control
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG2         AFCNTR        LL_SPI_DisableGPIOControl
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
+}
+
+/**
+  * @brief  Check if GPIO control is active
+  * @rmtoll CFG2         AFCNTR        LL_SPI_IsEnabledGPIOControl
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set SPI Mode to Master or Slave
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG2         MASTER        LL_SPI_SetMode
+  * @param  SPIx SPI Instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
+}
+
+/**
+  * @brief  Get SPI Mode (Master or Slave)
+  * @rmtoll CFG2         MASTER        LL_SPI_GetMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_MODE_MASTER
+  *         @arg @ref LL_SPI_MODE_SLAVE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
+}
+
+/**
+  * @brief  Configure the Idleness applied by master between active edge of SS and first send data
+  * @rmtoll CFG2         MSSI          LL_SPI_SetMasterSSIdleness
+  * @param  SPIx SPI Instance
+  * @param  MasterSSIdleness This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
+}
+
+/**
+  * @brief  Get the configured Idleness applied by master
+  * @rmtoll CFG2         MSSI          LL_SPI_GetMasterSSIdleness
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
+  *         @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
+}
+
+/**
+  * @brief  Configure the idleness applied by master between data frame
+  * @rmtoll CFG2         MIDI          LL_SPI_SetInterDataIdleness
+  * @param  SPIx SPI Instance
+  * @param  MasterInterDataIdleness This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
+}
+
+/**
+  * @brief  Get the configured inter data idleness
+  * @rmtoll CFG2         MIDI          LL_SPI_SetInterDataIdleness
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
+  *         @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
+}
+
+/**
+  * @brief  Set transfer size
+  * @note    Count is the number of frame to be transferred
+  * @rmtoll CR2          TSIZE         LL_SPI_SetTransferSize
+  * @param  SPIx SPI Instance
+  * @param  Count 0..0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
+{
+  MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
+}
+
+/**
+  * @brief  Get transfer size
+  * @note    Count is the number of frame to be transferred
+  * @rmtoll CR2          TSIZE         LL_SPI_GetTransferSize
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
+}
+
+/**
+  * @brief  Lock the AF configuration of associated IOs
+  * @note   Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
+  *         the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
+  * @rmtoll CR1          IOLOCK        LL_SPI_EnableIOLock
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
+}
+
+/**
+  * @brief  Check if the AF configuration is locked.
+  * @rmtoll CR1          IOLOCK        LL_SPI_IsEnabledIOLock
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Tx CRC Initialization Pattern
+  * @rmtoll CR1          TCRCINI         LL_SPI_SetTxCRCInitPattern
+  * @param  SPIx SPI Instance
+  * @param  TXCRCInitAll This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll);
+}
+
+/**
+  * @brief  Get Tx CRC Initialization Pattern
+  * @rmtoll CR1          TCRCINI         LL_SPI_GetTxCRCInitPattern
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
+}
+
+/**
+  * @brief  Set Rx CRC Initialization Pattern
+  * @rmtoll CR1          RCRCINI         LL_SPI_SetRxCRCInitPattern
+  * @param  SPIx SPI Instance
+  * @param  RXCRCInitAll This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
+}
+
+/**
+  * @brief  Get Rx CRC Initialization Pattern
+  * @rmtoll CR1          RCRCINI         LL_SPI_GetRxCRCInitPattern
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
+}
+
+/**
+  * @brief  Set internal SS input level ignoring what comes from PIN.
+  * @note   This configuration has effect only with config LL_SPI_NSS_SOFT
+  * @rmtoll CR1          SSI           LL_SPI_SetInternalSSLevel
+  * @param  SPIx SPI Instance
+  * @param  SSLevel This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_SS_LEVEL_HIGH
+  *         @arg @ref LL_SPI_SS_LEVEL_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
+}
+
+/**
+  * @brief  Get internal SS input level
+  * @rmtoll CR1          SSI           LL_SPI_GetInternalSSLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_SS_LEVEL_HIGH
+  *         @arg @ref LL_SPI_SS_LEVEL_LOW
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
+}
+
+/**
+  * @brief  Enable CRC computation on 33/17 bits
+  * @rmtoll CR1          CRC33_17      LL_SPI_EnableFullSizeCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
+}
+
+/**
+  * @brief  Disable CRC computation on 33/17 bits
+  * @rmtoll CR1          CRC33_17      LL_SPI_DisableFullSizeCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
+}
+
+/**
+  * @brief  Check if Enable CRC computation on 33/17 bits is enabled
+  * @rmtoll CR1          CRC33_17      LL_SPI_IsEnabledFullSizeCRC
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Suspend an ongoing transfer for Master configuration
+  * @rmtoll CR1          CSUSP         LL_SPI_SuspendMasterTransfer
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
+}
+
+/**
+  * @brief  Start effective transfer on wire for Master configuration
+  * @rmtoll CR1          CSTART        LL_SPI_StartMasterTransfer
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
+}
+
+/**
+  * @brief  Check if there is an unfinished master transfer
+  * @rmtoll CR1          CSTART        LL_SPI_IsActiveMasterTransfer
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Master Rx auto suspend in case of overrun
+  * @rmtoll CR1          MASRX         LL_SPI_EnableMasterRxAutoSuspend
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
+}
+
+/**
+  * @brief  Disable Master Rx auto suspend in case of overrun
+  * @rmtoll CR1          MASRX         LL_SPI_DisableMasterRxAutoSuspend
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
+}
+
+/**
+  * @brief  Check if Master Rx auto suspend is activated
+  * @rmtoll CR1          MASRX         LL_SPI_IsEnabledMasterRxAutoSuspend
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Underrun behavior
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG1         UDRCFG        LL_SPI_SetUDRConfiguration
+  * @param  SPIx SPI Instance
+  * @param  UDRConfig This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
+  *         @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
+{
+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
+}
+
+/**
+  * @brief  Get Underrun behavior
+  * @rmtoll CFG1         UDRCFG        LL_SPI_GetUDRConfiguration
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
+  *         @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
+}
+
+
+/**
+  * @brief  Set Serial protocol used
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG2         SP            LL_SPI_SetStandard
+  * @param  SPIx SPI Instance
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
+}
+
+/**
+  * @brief  Get Serial protocol used
+  * @rmtoll CFG2         SP            LL_SPI_GetStandard
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+  *         @arg @ref LL_SPI_PROTOCOL_TI
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
+}
+
+/**
+  * @brief  Set Clock phase
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CFG2         CPHA          LL_SPI_SetClockPhase
+  * @param  SPIx SPI Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Get Clock phase
+  * @rmtoll CFG2         CPHA          LL_SPI_GetClockPhase
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_PHASE_1EDGE
+  *         @arg @ref LL_SPI_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
+}
+
+/**
+  * @brief  Set Clock polarity
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CFG2         CPOL          LL_SPI_SetClockPolarity
+  * @param  SPIx SPI Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Get Clock polarity
+  * @rmtoll CFG2         CPOL          LL_SPI_GetClockPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_POLARITY_LOW
+  *         @arg @ref LL_SPI_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
+}
+
+/**
+  * @brief  Set NSS polarity
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CFG2         SSIOP          LL_SPI_SetNSSPolarity
+  * @param  SPIx SPI Instance
+  * @param  NSSPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_POLARITY_LOW
+  *         @arg @ref LL_SPI_NSS_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
+}
+
+/**
+  * @brief  Get NSS polarity
+  * @rmtoll CFG2         SSIOP          LL_SPI_GetNSSPolarity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_POLARITY_LOW
+  *         @arg @ref LL_SPI_NSS_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
+}
+
+/**
+  * @brief  Set Baudrate Prescaler
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         SPI BaudRate = fPCLK/Pescaler.
+  * @rmtoll CFG1         MBR            LL_SPI_SetBaudRatePrescaler\n
+  *         CFG1         BPASS          LL_SPI_SetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @param  Baudrate This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
+{
+  MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
+}
+
+/**
+  * @brief  Get Baudrate Prescaler
+  * @rmtoll CFG1         MBR           LL_SPI_GetBaudRatePrescaler\n
+  *         CFG1         BPASS         LL_SPI_GetBaudRatePrescaler
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
+}
+
+/**
+  * @brief  Set Transfer Bit Order
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CFG2         LSBFRST       LL_SPI_SetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
+}
+
+/**
+  * @brief  Get Transfer Bit Order
+  * @rmtoll CFG2         LSBFRST       LL_SPI_GetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_LSB_FIRST
+  *         @arg @ref LL_SPI_MSB_FIRST
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
+}
+
+/**
+  * @brief  Set Transfer Mode
+  * @note   This configuration can not be changed when SPI is enabled except for half duplex direction
+  *         using LL_SPI_SetHalfDuplexDirection.
+  * @rmtoll CR1          HDDIR         LL_SPI_SetTransferDirection\n
+  *         CFG2         COMM          LL_SPI_SetTransferDirection
+  * @param  SPIx SPI Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_TX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR,  TransferDirection & SPI_CR1_HDDIR);
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
+}
+
+/**
+  * @brief  Get Transfer Mode
+  * @rmtoll CR1          HDDIR         LL_SPI_GetTransferDirection\n
+  *         CFG2         COMM          LL_SPI_GetTransferDirection
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_FULL_DUPLEX
+  *         @arg @ref LL_SPI_SIMPLEX_TX
+  *         @arg @ref LL_SPI_SIMPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
+{
+  uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
+  uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
+  return (Hddir | Comm);
+}
+
+/**
+  * @brief  Set direction for Half-Duplex Mode
+  * @note   In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
+  * @rmtoll CR1          HDDIR         LL_SPI_SetHalfDuplexDirection
+  * @param  SPIx SPI Instance
+  * @param  HalfDuplexDirection This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
+{
+  MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
+}
+
+/**
+  * @brief  Get direction for Half-Duplex Mode
+  * @note   In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
+  * @rmtoll CR1          HDDIR         LL_SPI_GetHalfDuplexDirection
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
+}
+
+/**
+  * @brief  Set Frame Data Size
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG1         DSIZE         LL_SPI_SetDataWidth
+  * @param  SPIx SPI Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_17BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_18BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_19BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_20BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_21BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_22BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_23BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_24BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_25BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_26BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_27BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_28BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_29BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_30BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_31BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_32BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
+}
+
+/**
+  * @brief  Get Frame Data Size
+  * @rmtoll CFG1         DSIZE         LL_SPI_GetDataWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_17BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_18BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_19BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_20BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_21BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_22BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_23BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_24BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_25BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_26BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_27BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_28BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_29BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_30BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_31BIT
+  *         @arg @ref LL_SPI_DATAWIDTH_32BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
+}
+
+/**
+  * @brief  Set threshold of FIFO that triggers a transfer event
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG1         FTHLV         LL_SPI_SetFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_FIFO_TH_01DATA
+  *         @arg @ref LL_SPI_FIFO_TH_02DATA
+  *         @arg @ref LL_SPI_FIFO_TH_03DATA
+  *         @arg @ref LL_SPI_FIFO_TH_04DATA
+  *         @arg @ref LL_SPI_FIFO_TH_05DATA
+  *         @arg @ref LL_SPI_FIFO_TH_06DATA
+  *         @arg @ref LL_SPI_FIFO_TH_07DATA
+  *         @arg @ref LL_SPI_FIFO_TH_08DATA
+  *         @arg @ref LL_SPI_FIFO_TH_09DATA
+  *         @arg @ref LL_SPI_FIFO_TH_10DATA
+  *         @arg @ref LL_SPI_FIFO_TH_11DATA
+  *         @arg @ref LL_SPI_FIFO_TH_12DATA
+  *         @arg @ref LL_SPI_FIFO_TH_13DATA
+  *         @arg @ref LL_SPI_FIFO_TH_14DATA
+  *         @arg @ref LL_SPI_FIFO_TH_15DATA
+  *         @arg @ref LL_SPI_FIFO_TH_16DATA
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
+}
+
+/**
+  * @brief  Get threshold of FIFO that triggers a transfer event
+  * @rmtoll CFG1         FTHLV         LL_SPI_GetFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_FIFO_TH_01DATA
+  *         @arg @ref LL_SPI_FIFO_TH_02DATA
+  *         @arg @ref LL_SPI_FIFO_TH_03DATA
+  *         @arg @ref LL_SPI_FIFO_TH_04DATA
+  *         @arg @ref LL_SPI_FIFO_TH_05DATA
+  *         @arg @ref LL_SPI_FIFO_TH_06DATA
+  *         @arg @ref LL_SPI_FIFO_TH_07DATA
+  *         @arg @ref LL_SPI_FIFO_TH_08DATA
+  *         @arg @ref LL_SPI_FIFO_TH_09DATA
+  *         @arg @ref LL_SPI_FIFO_TH_10DATA
+  *         @arg @ref LL_SPI_FIFO_TH_11DATA
+  *         @arg @ref LL_SPI_FIFO_TH_12DATA
+  *         @arg @ref LL_SPI_FIFO_TH_13DATA
+  *         @arg @ref LL_SPI_FIFO_TH_14DATA
+  *         @arg @ref LL_SPI_FIFO_TH_15DATA
+  *         @arg @ref LL_SPI_FIFO_TH_16DATA
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
+}
+
+/**
+  * @brief  Enable CRC
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG1         CRCEN         LL_SPI_EnableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
+}
+
+/**
+  * @brief  Disable CRC
+  * @rmtoll CFG1         CRCEN         LL_SPI_DisableCRC
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
+}
+
+/**
+  * @brief  Check if CRC is enabled
+  * @rmtoll CFG1         CRCEN         LL_SPI_IsEnabledCRC
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set CRC Length
+  * @note   This configuration can not be changed when SPI is enabled.
+  * @rmtoll CFG1         CRCSIZE       LL_SPI_SetCRCWidth
+  * @param  SPIx SPI Instance
+  * @param  CRCLength This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_4BIT
+  *         @arg @ref LL_SPI_CRC_5BIT
+  *         @arg @ref LL_SPI_CRC_6BIT
+  *         @arg @ref LL_SPI_CRC_7BIT
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_9BIT
+  *         @arg @ref LL_SPI_CRC_10BIT
+  *         @arg @ref LL_SPI_CRC_11BIT
+  *         @arg @ref LL_SPI_CRC_12BIT
+  *         @arg @ref LL_SPI_CRC_13BIT
+  *         @arg @ref LL_SPI_CRC_14BIT
+  *         @arg @ref LL_SPI_CRC_15BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  *         @arg @ref LL_SPI_CRC_17BIT
+  *         @arg @ref LL_SPI_CRC_18BIT
+  *         @arg @ref LL_SPI_CRC_19BIT
+  *         @arg @ref LL_SPI_CRC_20BIT
+  *         @arg @ref LL_SPI_CRC_21BIT
+  *         @arg @ref LL_SPI_CRC_22BIT
+  *         @arg @ref LL_SPI_CRC_23BIT
+  *         @arg @ref LL_SPI_CRC_24BIT
+  *         @arg @ref LL_SPI_CRC_25BIT
+  *         @arg @ref LL_SPI_CRC_26BIT
+  *         @arg @ref LL_SPI_CRC_27BIT
+  *         @arg @ref LL_SPI_CRC_28BIT
+  *         @arg @ref LL_SPI_CRC_29BIT
+  *         @arg @ref LL_SPI_CRC_30BIT
+  *         @arg @ref LL_SPI_CRC_31BIT
+  *         @arg @ref LL_SPI_CRC_32BIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
+}
+
+/**
+  * @brief  Get CRC Length
+  * @rmtoll CFG1          CRCSIZE       LL_SPI_GetCRCWidth
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_CRC_4BIT
+  *         @arg @ref LL_SPI_CRC_5BIT
+  *         @arg @ref LL_SPI_CRC_6BIT
+  *         @arg @ref LL_SPI_CRC_7BIT
+  *         @arg @ref LL_SPI_CRC_8BIT
+  *         @arg @ref LL_SPI_CRC_9BIT
+  *         @arg @ref LL_SPI_CRC_10BIT
+  *         @arg @ref LL_SPI_CRC_11BIT
+  *         @arg @ref LL_SPI_CRC_12BIT
+  *         @arg @ref LL_SPI_CRC_13BIT
+  *         @arg @ref LL_SPI_CRC_14BIT
+  *         @arg @ref LL_SPI_CRC_15BIT
+  *         @arg @ref LL_SPI_CRC_16BIT
+  *         @arg @ref LL_SPI_CRC_17BIT
+  *         @arg @ref LL_SPI_CRC_18BIT
+  *         @arg @ref LL_SPI_CRC_19BIT
+  *         @arg @ref LL_SPI_CRC_20BIT
+  *         @arg @ref LL_SPI_CRC_21BIT
+  *         @arg @ref LL_SPI_CRC_22BIT
+  *         @arg @ref LL_SPI_CRC_23BIT
+  *         @arg @ref LL_SPI_CRC_24BIT
+  *         @arg @ref LL_SPI_CRC_25BIT
+  *         @arg @ref LL_SPI_CRC_26BIT
+  *         @arg @ref LL_SPI_CRC_27BIT
+  *         @arg @ref LL_SPI_CRC_28BIT
+  *         @arg @ref LL_SPI_CRC_29BIT
+  *         @arg @ref LL_SPI_CRC_30BIT
+  *         @arg @ref LL_SPI_CRC_31BIT
+  *         @arg @ref LL_SPI_CRC_32BIT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
+}
+
+/**
+  * @brief  Set NSS Mode
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CFG2         SSM           LL_SPI_SetNSSMode\n
+  *         CFG2         SSOE          LL_SPI_SetNSSMode
+  * @param  SPIx SPI Instance
+  * @param  NSS This parameter can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
+}
+
+/**
+  * @brief  Set NSS Mode
+  * @rmtoll CFG2         SSM           LL_SPI_GetNSSMode\n
+  *         CFG2         SSOE          LL_SPI_GetNSSMode
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_NSS_SOFT
+  *         @arg @ref LL_SPI_NSS_HARD_INPUT
+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
+}
+
+/**
+  * @brief  Enable NSS pulse mgt
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CFG2         SSOM          LL_SPI_EnableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
+}
+
+/**
+  * @brief  Disable NSS pulse mgt
+  * @note   This configuration can not be changed when SPI is enabled.
+  *         This bit is not used in SPI TI mode.
+  * @rmtoll CFG2         SSOM          LL_SPI_DisableNSSPulseMgt
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
+}
+
+/**
+  * @brief  Check if NSS pulse is enabled
+  * @rmtoll CFG2         SSOM          LL_SPI_IsEnabledNSSPulse
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if there is enough data in FIFO to read a full packet
+  * @rmtoll SR           RXP           LL_SPI_IsActiveFlag_RXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if there is enough space in FIFO to hold a full packet
+  * @rmtoll SR           TXP           LL_SPI_IsActiveFlag_TXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
+  * @rmtoll SR           DXP           LL_SPI_IsActiveFlag_DXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check that end of transfer event occurred
+  * @rmtoll SR           EOT           LL_SPI_IsActiveFlag_EOT
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check that all required data has been filled in the fifo according to transfer size
+  * @rmtoll SR           TXTF          LL_SPI_IsActiveFlag_TXTF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Underrun error flag
+  * @rmtoll SR           UDR           LL_SPI_IsActiveFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get CRC error flag
+  * @rmtoll SR           CRCE        LL_SPI_IsActiveFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get  Mode fault error flag
+  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Overrun error flag
+  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get TI Frame format error flag
+  * @rmtoll SR           TIFRE         LL_SPI_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if a suspend operation is done
+  * @rmtoll SR           SUSP          LL_SPI_IsActiveFlag_SUSP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if last TxFIFO or CRC frame transmission is completed
+  * @rmtoll SR           TXC           LL_SPI_IsActiveFlag_TXC
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if at least one 32-bit data is available in RxFIFO
+  * @rmtoll SR           RXWNE         LL_SPI_IsActiveFlag_RXWNE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get number of data framed remaining in current TSIZE
+  * @rmtoll SR           CTSIZE           LL_SPI_GetRemainingDataFrames
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
+}
+
+/**
+  * @brief  Get RxFIFO packing Level
+  * @rmtoll SR           RXPLVL        LL_SPI_GetRxFIFOPackingLevel
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SPI_RX_FIFO_0PACKET
+  *         @arg @ref LL_SPI_RX_FIFO_1PACKET
+  *         @arg @ref LL_SPI_RX_FIFO_2PACKET
+  *         @arg @ref LL_SPI_RX_FIFO_3PACKET
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
+}
+
+/**
+  * @brief  Clear End Of Transfer flag
+  * @rmtoll IFCR         EOTC          LL_SPI_ClearFlag_EOT
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
+}
+
+/**
+  * @brief  Clear TXTF flag
+  * @rmtoll IFCR         TXTFC         LL_SPI_ClearFlag_TXTF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
+}
+
+/**
+  * @brief  Clear Underrun error flag
+  * @rmtoll IFCR         UDRC          LL_SPI_ClearFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
+}
+
+/**
+  * @brief  Clear Overrun error flag
+  * @rmtoll IFCR         OVRC          LL_SPI_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
+}
+
+/**
+  * @brief  Clear CRC error flag
+  * @rmtoll IFCR         CRCEC        LL_SPI_ClearFlag_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
+}
+
+/**
+  * @brief  Clear  Mode fault error flag
+  * @rmtoll IFCR         MODFC         LL_SPI_ClearFlag_MODF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
+}
+
+/**
+  * @brief  Clear Frame format error flag
+  * @rmtoll IFCR         TIFREC        LL_SPI_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
+}
+
+/**
+  * @brief  Clear SUSP flag
+  * @rmtoll IFCR         SUSPC         LL_SPI_ClearFlag_SUSP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Rx Packet available IT
+  * @rmtoll IER          RXPIE         LL_SPI_EnableIT_RXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_RXPIE);
+}
+
+/**
+  * @brief  Enable Tx Packet space available IT
+  * @rmtoll IER          TXPIE         LL_SPI_EnableIT_TXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_TXPIE);
+}
+
+/**
+  * @brief  Enable Duplex Packet available IT
+  * @rmtoll IER          DXPIE         LL_SPI_EnableIT_DXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_DXPIE);
+}
+
+/**
+  * @brief  Enable End Of Transfer IT
+  * @rmtoll IER          EOTIE         LL_SPI_EnableIT_EOT
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_EOTIE);
+}
+
+/**
+  * @brief  Enable TXTF IT
+  * @rmtoll IER          TXTFIE        LL_SPI_EnableIT_TXTF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
+}
+
+/**
+  * @brief  Enable Underrun IT
+  * @rmtoll IER          UDRIE         LL_SPI_EnableIT_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_UDRIE);
+}
+
+/**
+  * @brief  Enable Overrun IT
+  * @rmtoll IER          OVRIE         LL_SPI_EnableIT_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_OVRIE);
+}
+
+/**
+  * @brief  Enable CRC Error IT
+  * @rmtoll IER          CRCEIE        LL_SPI_EnableIT_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
+}
+
+/**
+  * @brief  Enable TI Frame Format Error IT
+  * @rmtoll IER          TIFREIE       LL_SPI_EnableIT_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
+}
+
+/**
+  * @brief  Enable MODF IT
+  * @rmtoll IER          MODFIE        LL_SPI_EnableIT_MODF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->IER, SPI_IER_MODFIE);
+}
+
+/**
+  * @brief  Disable Rx Packet available IT
+  * @rmtoll IER          RXPIE         LL_SPI_DisableIT_RXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
+}
+
+/**
+  * @brief  Disable Tx Packet space available IT
+  * @rmtoll IER          TXPIE         LL_SPI_DisableIT_TXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
+}
+
+/**
+  * @brief  Disable Duplex Packet available IT
+  * @rmtoll IER          DXPIE         LL_SPI_DisableIT_DXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
+}
+
+/**
+  * @brief  Disable End Of Transfer IT
+  * @rmtoll IER          EOTIE         LL_SPI_DisableIT_EOT
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
+}
+
+/**
+  * @brief  Disable TXTF IT
+  * @rmtoll IER          TXTFIE        LL_SPI_DisableIT_TXTF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
+}
+
+/**
+  * @brief  Disable Underrun IT
+  * @rmtoll IER          UDRIE         LL_SPI_DisableIT_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
+}
+
+/**
+  * @brief  Disable Overrun IT
+  * @rmtoll IER          OVRIE         LL_SPI_DisableIT_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
+}
+
+/**
+  * @brief  Disable CRC Error IT
+  * @rmtoll IER          CRCEIE        LL_SPI_DisableIT_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
+}
+
+/**
+  * @brief  Disable TI Frame Format Error IT
+  * @rmtoll IER          TIFREIE       LL_SPI_DisableIT_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
+}
+
+/**
+  * @brief  Disable MODF IT
+  * @rmtoll IER          MODFIE        LL_SPI_DisableIT_MODF
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
+}
+
+/**
+  * @brief  Check if Rx Packet available IT is enabled
+  * @rmtoll IER          RXPIE         LL_SPI_IsEnabledIT_RXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx Packet space available IT is enabled
+  * @rmtoll IER          TXPIE         LL_SPI_IsEnabledIT_TXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Duplex Packet available IT is enabled
+  * @rmtoll IER          DXPIE         LL_SPI_IsEnabledIT_DXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if End Of Transfer IT is enabled
+  * @rmtoll IER          EOTIE         LL_SPI_IsEnabledIT_EOT
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if TXTF IT is enabled
+  * @rmtoll IER          TXTFIE        LL_SPI_IsEnabledIT_TXTF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Underrun IT is enabled
+  * @rmtoll IER          UDRIE         LL_SPI_IsEnabledIT_UDR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Overrun IT is enabled
+  * @rmtoll IER          OVRIE         LL_SPI_IsEnabledIT_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if CRC Error IT is enabled
+  * @rmtoll IER          CRCEIE        LL_SPI_IsEnabledIT_CRCERR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if TI Frame Format Error IT is enabled
+  * @rmtoll IER          TIFREIE       LL_SPI_IsEnabledIT_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if MODF IT is enabled
+  * @rmtoll IER          MODFIE        LL_SPI_IsEnabledIT_MODF
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CFG1         RXDMAEN       LL_SPI_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CFG1         RXDMAEN       LL_SPI_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CFG1         RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CFG1         TXDMAEN       LL_SPI_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CFG1         TXDMAEN       LL_SPI_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CFG1         TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
+}
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TXDR           TXDR            LL_SPI_DMA_GetTxRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t) &(SPIx->TXDR);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RXDR           RXDR            LL_SPI_DMA_GetRxRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t) &(SPIx->RXDR);
+}
+/**
+  * @}
+  */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Data Register
+  * @rmtoll RXDR         .       LL_SPI_ReceiveData8
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFF
+  */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  return (*((__IO uint8_t *)&SPIx->RXDR));
+}
+
+/**
+  * @brief  Read Data Register
+  * @rmtoll RXDR         .       LL_SPI_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
+{
+#if defined (__GNUC__)
+  __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
+  return (*spirxdr);
+#else
+  return (*((__IO uint16_t *)&SPIx->RXDR));
+#endif /* __GNUC__ */
+}
+
+/**
+  * @brief  Read Data Register
+  * @rmtoll RXDR         .       LL_SPI_ReceiveData32
+  * @param  SPIx SPI Instance
+  * @retval  0..0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  return (*((__IO uint32_t *)&SPIx->RXDR));
+}
+
+/**
+  * @brief  Write Data Register
+  * @rmtoll TXDR         .       LL_SPI_TransmitData8
+  * @param  SPIx SPI Instance
+  * @param  TxData 0..0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+  *((__IO uint8_t *)&SPIx->TXDR) = TxData;
+}
+
+/**
+  * @brief  Write Data Register
+  * @rmtoll TXDR         .       LL_SPI_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData 0..0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+#if defined (__GNUC__)
+  __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
+  *spitxdr = TxData;
+#else
+  *((__IO uint16_t *)&SPIx->TXDR) = TxData;
+#endif /* __GNUC__ */
+}
+
+/**
+  * @brief  Write Data Register
+  * @rmtoll TXDR         .       LL_SPI_TransmitData32
+  * @param  SPIx SPI Instance
+  * @param  TxData 0..0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
+{
+  *((__IO uint32_t *)&SPIx->TXDR) = TxData;
+}
+
+/**
+  * @brief  Set polynomial for CRC calcul
+  * @rmtoll CRCPOLY      CRCPOLY       LL_SPI_SetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @param  CRCPoly 0..0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+  WRITE_REG(SPIx->CRCPOLY, CRCPoly);
+}
+
+/**
+  * @brief  Get polynomial for CRC calcul
+  * @rmtoll CRCPOLY      CRCPOLY       LL_SPI_GetCRCPolynomial
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->CRCPOLY));
+}
+
+/**
+  * @brief  Set the underrun pattern
+  * @rmtoll UDRDR        UDRDR         LL_SPI_SetUDRPattern
+  * @param  SPIx SPI Instance
+  * @param  Pattern 0..0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
+{
+  WRITE_REG(SPIx->UDRDR, Pattern);
+}
+
+/**
+  * @brief  Get the underrun pattern
+  * @rmtoll UDRDR        UDRDR         LL_SPI_GetUDRPattern
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->UDRDR));
+}
+
+/**
+  * @brief  Get Rx CRC
+  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->RXCRC));
+}
+
+/**
+  * @brief  Get Tx CRC
+  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_REG(SPIx->TXCRC));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL I2S
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  I2S Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t Mode;                    /*!< Specifies the I2S operating mode.
+                                         This parameter can be a value of @ref I2S_LL_EC_MODE
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetTransferMode().*/
+
+  uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetStandard().*/
+
+
+  uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetDataFormat().*/
+
+
+  uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                         This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+                                         This feature can be modified afterwards using unitary functions
+                                         @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+  uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
+                                         This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+                                         Audio Frequency can be modified afterwards using Reference manual formulas
+                                         to calculate Prescaler Linear, Parity and unitary functions
+                                         @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity()
+                                         to set it.*/
+
+
+  uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
+                                         This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+  * @{
+  */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
+  * @{
+  */
+#define LL_I2S_DATAFORMAT_16B               (0x00000000UL)
+#define LL_I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
+#define LL_I2S_DATAFORMAT_24B               (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
+#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED  (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
+#define LL_I2S_DATAFORMAT_32B               (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
+  * @{
+  */
+#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH     (0x00000000UL)
+#define LL_I2S_SLAVE_FIXED_CH_LENGTH        (SPI_I2SCFGR_FIXCH)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_I2S_POLARITY_LOW                 (0x00000000UL)
+#define LL_I2S_POLARITY_HIGH                (SPI_I2SCFGR_CKPOL)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_STANDARD I2S Standard
+  * @{
+  */
+#define LL_I2S_STANDARD_PHILIPS             (0x00000000UL)
+#define LL_I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
+#define LL_I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
+#define LL_I2S_STANDARD_PCM_SHORT           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
+#define LL_I2S_STANDARD_PCM_LONG            (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+  * @{
+  */
+#define LL_I2S_MODE_SLAVE_TX                (0x00000000UL)
+#define LL_I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
+#define LL_I2S_MODE_SLAVE_FULL_DUPLEX       (SPI_I2SCFGR_I2SCFG_2)
+#define LL_I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
+#define LL_I2S_MODE_MASTER_RX               (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
+#define LL_I2S_MODE_MASTER_FULL_DUPLEX      (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
+  * @{
+  */
+#define LL_I2S_PRESCALER_PARITY_EVEN        (0x00000000UL)   /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
+#define LL_I2S_PRESCALER_PARITY_ODD         (0x00000001UL)   /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
+  * @{
+  */
+#define LL_I2S_FIFO_TH_01DATA               (LL_SPI_FIFO_TH_01DATA)
+#define LL_I2S_FIFO_TH_02DATA               (LL_SPI_FIFO_TH_02DATA)
+#define LL_I2S_FIFO_TH_03DATA               (LL_SPI_FIFO_TH_03DATA)
+#define LL_I2S_FIFO_TH_04DATA               (LL_SPI_FIFO_TH_04DATA)
+#define LL_I2S_FIFO_TH_05DATA               (LL_SPI_FIFO_TH_05DATA)
+#define LL_I2S_FIFO_TH_06DATA               (LL_SPI_FIFO_TH_06DATA)
+#define LL_I2S_FIFO_TH_07DATA               (LL_SPI_FIFO_TH_07DATA)
+#define LL_I2S_FIFO_TH_08DATA               (LL_SPI_FIFO_TH_08DATA)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
+  * @{
+  */
+#define LL_I2S_LSB_FIRST                    (LL_SPI_LSB_FIRST)
+#define LL_I2S_MSB_FIRST                    (LL_SPI_MSB_FIRST)
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+  * @{
+  */
+#define LL_I2S_MCLK_OUTPUT_DISABLE          (0x00000000UL)
+#define LL_I2S_MCLK_OUTPUT_ENABLE           (SPI_I2SCFGR_MCKOE)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+  * @{
+  */
+
+#define LL_I2S_AUDIOFREQ_192K               192000UL       /*!< Audio Frequency configuration 192000 Hz       */
+#define LL_I2S_AUDIOFREQ_96K                96000UL        /*!< Audio Frequency configuration  96000 Hz       */
+#define LL_I2S_AUDIOFREQ_48K                48000UL        /*!< Audio Frequency configuration  48000 Hz       */
+#define LL_I2S_AUDIOFREQ_44K                44100UL        /*!< Audio Frequency configuration  44100 Hz       */
+#define LL_I2S_AUDIOFREQ_32K                32000UL        /*!< Audio Frequency configuration  32000 Hz       */
+#define LL_I2S_AUDIOFREQ_22K                22050UL        /*!< Audio Frequency configuration  22050 Hz       */
+#define LL_I2S_AUDIOFREQ_16K                16000UL        /*!< Audio Frequency configuration  16000 Hz       */
+#define LL_I2S_AUDIOFREQ_11K                11025UL        /*!< Audio Frequency configuration  11025 Hz       */
+#define LL_I2S_AUDIOFREQ_8K                 8000UL         /*!< Audio Frequency configuration   8000 Hz       */
+#define LL_I2S_AUDIOFREQ_DEFAULT            0UL            /*!< Audio Freq not specified. Register I2SDIV = 0 */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+  * @{
+  */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in I2S register
+  * @param  __INSTANCE__ I2S Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in I2S register
+  * @param  __INSTANCE__ I2S Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+  * @{
+  */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Set I2S Data frame format
+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
+  *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat\n
+  *         I2SCFGR      DATFMT        LL_I2S_SetDataFormat
+  * @param  SPIx SPI Handle
+  * @param  DataLength This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_DATAFORMAT_16B
+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+  *         @arg @ref LL_I2S_DATAFORMAT_24B
+  *         @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
+  *         @arg @ref LL_I2S_DATAFORMAT_32B
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
+}
+
+/**
+  * @brief  Get I2S Data frame format
+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
+  *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat\n
+  *         I2SCFGR      DATFMT        LL_I2S_GetDataFormat
+  * @param  SPIx SPI Handle
+  * @retval Return value can be one of the following values:
+  *         @arg @ref LL_I2S_DATAFORMAT_16B
+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+  *         @arg @ref LL_I2S_DATAFORMAT_24B
+  *         @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
+  *         @arg @ref LL_I2S_DATAFORMAT_32B
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
+}
+
+/**
+  * @brief  Set I2S Channel Length Type
+  * @note   This feature is useful with SLAVE only
+  * @rmtoll I2SCFGR      FIXCH        LL_I2S_SetChannelLengthType
+  * @param  SPIx SPI Handle
+  * @param  ChannelLengthType This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
+  *         @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
+}
+
+/**
+  * @brief  Get I2S Channel Length Type
+  * @note   This feature is useful with SLAVE only
+  * @rmtoll I2SCFGR      FIXCH         LL_I2S_GetChannelLengthType
+  * @param  SPIx SPI Handle
+  * @retval Return value can be one of the following values:
+  *         @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
+  *         @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
+}
+
+/**
+  * @brief  Invert the default polarity of WS signal
+  * @rmtoll I2SCFGR      WSINV         LL_I2S_EnableWordSelectInversion
+  * @param  SPIx SPI Handle
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
+}
+
+/**
+  * @brief  Use the default polarity of WS signal
+  * @rmtoll I2SCFGR      WSINV         LL_I2S_DisableWordSelectInversion
+  * @param  SPIx SPI Handle
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
+}
+
+/**
+  * @brief  Check if polarity of WS signal is inverted
+  * @rmtoll I2SCFGR      WSINV         LL_I2S_IsEnabledWordSelectInversion
+  * @param  SPIx SPI Handle
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set 2S Clock Polarity
+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
+  * @param  SPIx SPI Handle
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_POLARITY_LOW
+  *         @arg @ref LL_I2S_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Get 2S Clock Polarity
+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
+  * @param  SPIx SPI Handle
+  * @retval Return value can be one of the following values:
+  *         @arg @ref LL_I2S_POLARITY_LOW
+  *         @arg @ref LL_I2S_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+  * @brief  Set I2S standard
+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
+  *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
+  * @param  SPIx SPI Handle
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_STANDARD_PHILIPS
+  *         @arg @ref LL_I2S_STANDARD_MSB
+  *         @arg @ref LL_I2S_STANDARD_LSB
+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+  * @brief  Get I2S standard
+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
+  *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
+  * @param  SPIx SPI Handle
+  * @retval Return value can be one of the following values:
+  *         @arg @ref LL_I2S_STANDARD_PHILIPS
+  *         @arg @ref LL_I2S_STANDARD_MSB
+  *         @arg @ref LL_I2S_STANDARD_LSB
+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+  * @brief  Set I2S config
+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
+  * @param  SPIx SPI Handle
+  * @param  Standard This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_MODE_SLAVE_TX
+  *         @arg @ref LL_I2S_MODE_SLAVE_RX
+  *         @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
+  *         @arg @ref LL_I2S_MODE_MASTER_TX
+  *         @arg @ref LL_I2S_MODE_MASTER_RX
+  *         @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
+}
+
+/**
+  * @brief  Get I2S config
+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
+  * @param  SPIx SPI Handle
+  * @retval Return value can be one of the following values:
+  *         @arg @ref LL_I2S_MODE_SLAVE_TX
+  *         @arg @ref LL_I2S_MODE_SLAVE_RX
+  *         @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
+  *         @arg @ref LL_I2S_MODE_MASTER_TX
+  *         @arg @ref LL_I2S_MODE_MASTER_RX
+  *         @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+  * @brief  Select I2S mode and Enable I2S peripheral
+  * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
+  *         CR1          SPE           LL_I2S_Enable
+  * @param  SPIx SPI Handle
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+  * @brief  Disable I2S peripheral and disable I2S mode
+  * @rmtoll CR1          SPE           LL_I2S_Disable\n
+  *         I2SCFGR      I2SMOD        LL_I2S_Disable
+  * @param  SPIx SPI Handle
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+}
+
+/**
+  * @brief  Swap the SDO and SDI pin
+  * @note   This configuration can not be changed when I2S is enabled.
+  * @rmtoll CFG2         IOSWP         LL_I2S_EnableIOSwap
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIOSwap(SPIx);
+}
+
+/**
+  * @brief  Restore default function for SDO and SDI pin
+  * @note   This configuration can not be changed when I2S is enabled.
+  * @rmtoll CFG2         IOSWP         LL_I2S_DisableIOSwap
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIOSwap(SPIx);
+}
+
+/**
+  * @brief  Check if SDO and SDI pin are swapped
+  * @rmtoll CFG2         IOSWP         LL_I2S_IsEnabledIOSwap
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIOSwap(SPIx);
+}
+
+/**
+  * @brief  Enable GPIO control
+  * @note   This configuration can not be changed when I2S is enabled.
+  * @rmtoll CFG2         AFCNTR        LL_I2S_EnableGPIOControl
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableGPIOControl(SPIx);
+}
+
+/**
+  * @brief  Disable GPIO control
+  * @note   This configuration can not be changed when I2S is enabled.
+  * @rmtoll CFG2         AFCNTR        LL_I2S_DisableGPIOControl
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableGPIOControl(SPIx);
+}
+
+/**
+  * @brief  Check if GPIO control is active
+  * @rmtoll CFG2         AFCNTR        LL_I2S_IsEnabledGPIOControl
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledGPIOControl(SPIx);
+}
+
+/**
+  * @brief  Lock the AF configuration of associated IOs
+  * @note   Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
+  *         The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
+  * @rmtoll CR1          IOLOCK        LL_SPI_EnableIOLock
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIOLock(SPIx);
+}
+
+/**
+  * @brief  Check if the the SPI_CFG2 register is locked
+  * @rmtoll CR1          IOLOCK        LL_I2S_IsEnabledIOLock
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIOLock(SPIx);
+}
+
+/**
+  * @brief  Set Transfer Bit Order
+  * @note   This configuration can not be changed when I2S is enabled.
+  * @rmtoll CFG2         LSBFRST       LL_I2S_SetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_LSB_FIRST
+  *         @arg @ref LL_I2S_MSB_FIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+  LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
+}
+/**
+  * @brief  Get Transfer Bit Order
+  * @rmtoll CFG2         LSBFRST       LL_I2S_GetTransferBitOrder
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_LSB_FIRST
+  *         @arg @ref LL_I2S_MSB_FIRST
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_GetTransferBitOrder(SPIx);
+}
+
+/**
+  * @brief  Start effective transfer on wire
+  * @rmtoll CR1          CSTART        LL_I2S_StartTransfer
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
+{
+  LL_SPI_StartMasterTransfer(SPIx);
+}
+
+/**
+  * @brief  Check if there is an unfinished transfer
+  * @rmtoll CR1          CSTART        LL_I2S_IsActiveTransfer
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveMasterTransfer(SPIx);
+}
+
+/**
+  * @brief  Set threshold of FIFO that triggers a transfer event
+  * @note   This configuration can not be changed when I2S is enabled.
+  * @rmtoll CFG1         FTHLV         LL_I2S_SetFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_FIFO_TH_01DATA
+  *         @arg @ref LL_I2S_FIFO_TH_02DATA
+  *         @arg @ref LL_I2S_FIFO_TH_03DATA
+  *         @arg @ref LL_I2S_FIFO_TH_04DATA
+  *         @arg @ref LL_I2S_FIFO_TH_05DATA
+  *         @arg @ref LL_I2S_FIFO_TH_06DATA
+  *         @arg @ref LL_I2S_FIFO_TH_07DATA
+  *         @arg @ref LL_I2S_FIFO_TH_08DATA
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+  LL_SPI_SetFIFOThreshold(SPIx, Threshold);
+}
+
+/**
+  * @brief  Get threshold of FIFO that triggers a transfer event
+  * @rmtoll CFG1         FTHLV         LL_I2S_GetFIFOThreshold
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_FIFO_TH_01DATA
+  *         @arg @ref LL_I2S_FIFO_TH_02DATA
+  *         @arg @ref LL_I2S_FIFO_TH_03DATA
+  *         @arg @ref LL_I2S_FIFO_TH_04DATA
+  *         @arg @ref LL_I2S_FIFO_TH_05DATA
+  *         @arg @ref LL_I2S_FIFO_TH_06DATA
+  *         @arg @ref LL_I2S_FIFO_TH_07DATA
+  *         @arg @ref LL_I2S_FIFO_TH_08DATA
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_GetFIFOThreshold(SPIx);
+}
+
+/**
+  * @brief  Set I2S linear prescaler
+  * @rmtoll I2SCFGR        I2SDIV        LL_I2S_SetPrescalerLinear
+  * @param  SPIx SPI Instance
+  * @param  PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
+  * @note   PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
+}
+
+/**
+  * @brief  Get I2S linear prescaler
+  * @rmtoll I2SCFGR        I2SDIV        LL_I2S_GetPrescalerLinear
+  * @param  SPIx SPI Instance
+  * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
+}
+
+/**
+  * @brief  Set I2S parity prescaler
+  * @rmtoll I2SCFGR        ODD           LL_I2S_SetPrescalerParity
+  * @param  SPIx SPI Instance
+  * @param  PrescalerParity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
+}
+
+/**
+  * @brief  Get I2S parity prescaler
+  * @rmtoll I2SCFGR        ODD           LL_I2S_GetPrescalerParity
+  * @param  SPIx SPI Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
+}
+
+/**
+  * @brief  Enable the Master Clock Output (Pin MCK)
+  * @rmtoll I2SCFGR      MCKOE         LL_I2S_EnableMasterClock
+  * @param  SPIx SPI Handle
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
+}
+
+/**
+  * @brief  Disable the Master Clock Output (Pin MCK)
+  * @rmtoll I2SCFGR      MCKOE         LL_I2S_DisableMasterClock
+  * @param  SPIx SPI Handle
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
+}
+
+/**
+  * @brief  Check if the master clock output (Pin MCK) is enabled
+  * @rmtoll I2SCFGR        MCKOE         LL_I2S_IsEnabledMasterClock
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
+{
+  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if there enough data in FIFO to read a full packet
+  * @rmtoll SR           RXP           LL_I2S_IsActiveFlag_RXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_RXP(SPIx);
+}
+
+/**
+  * @brief  Check if there enough space in FIFO to hold a full packet
+  * @rmtoll SR           TXP           LL_I2S_IsActiveFlag_TXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_TXP(SPIx);
+}
+
+/**
+  * @brief  Get Underrun error flag
+  * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_UDR(SPIx);
+}
+
+/**
+  * @brief  Get Overrun error flag
+  * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+  * @brief  Get TI Frame format error flag
+  * @rmtoll SR           TIFRE         LL_I2S_IsActiveFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+  * @brief  Clear Underrun error flag
+  * @rmtoll IFCR         UDRC          LL_I2S_ClearFlag_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_ClearFlag_UDR(SPIx);
+}
+
+/**
+  * @brief  Clear Overrun error flag
+  * @rmtoll IFCR         OVRC          LL_I2S_ClearFlag_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+  * @brief  Clear Frame format error flag
+  * @rmtoll IFCR         TIFREC        LL_I2S_ClearFlag_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable Rx Packet available IT
+  * @rmtoll IER          RXPIE         LL_I2S_EnableIT_RXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_RXP(SPIx);
+}
+
+/**
+  * @brief  Enable Tx Packet space available IT
+  * @rmtoll IER          TXPIE         LL_I2S_EnableIT_TXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_TXP(SPIx);
+}
+
+/**
+  * @brief  Enable Underrun IT
+  * @rmtoll IER          UDRIE         LL_I2S_EnableIT_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_UDR(SPIx);
+}
+
+/**
+  * @brief  Enable Overrun IT
+  * @rmtoll IER          OVRIE         LL_I2S_EnableIT_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_OVR(SPIx);
+}
+
+/**
+  * @brief  Enable TI Frame Format Error IT
+  * @rmtoll IER          TIFREIE       LL_I2S_EnableIT_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableIT_FRE(SPIx);
+}
+
+/**
+  * @brief  Disable Rx Packet available IT
+  * @rmtoll IER          RXPIE         LL_I2S_DisableIT_RXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_RXP(SPIx);
+}
+
+/**
+  * @brief  Disable Tx Packet space available IT
+  * @rmtoll IER          TXPIE         LL_I2S_DisableIT_TXP
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_TXP(SPIx);
+}
+
+/**
+  * @brief  Disable Underrun IT
+  * @rmtoll IER          UDRIE         LL_I2S_DisableIT_UDR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_UDR(SPIx);
+}
+
+/**
+  * @brief  Disable Overrun IT
+  * @rmtoll IER          OVRIE         LL_I2S_DisableIT_OVR
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_OVR(SPIx);
+}
+
+/**
+  * @brief  Disable TI Frame Format Error IT
+  * @rmtoll IER          TIFREIE       LL_I2S_DisableIT_FRE
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableIT_FRE(SPIx);
+}
+
+/**
+  * @brief  Check if Rx Packet available IT is enabled
+  * @rmtoll IER          RXPIE         LL_I2S_IsEnabledIT_RXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_RXP(SPIx);
+}
+
+/**
+  * @brief  Check if Tx Packet space available IT is enabled
+  * @rmtoll IER          TXPIE         LL_I2S_IsEnabledIT_TXP
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_TXP(SPIx);
+}
+
+/**
+  * @brief  Check if Underrun IT is enabled
+  * @rmtoll IER          UDRIE         LL_I2S_IsEnabledIT_UDR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_UDR(SPIx);
+}
+
+/**
+  * @brief  Check if Overrun IT is enabled
+  * @rmtoll IER          OVRIE         LL_I2S_IsEnabledIT_OVR
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_OVR(SPIx);
+}
+
+/**
+  * @brief  Check if TI Frame Format Error IT is enabled
+  * @rmtoll IER          TIFREIE       LL_I2S_IsEnabledIT_FRE
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledIT_FRE(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Rx
+  * @rmtoll CFG1         RXDMAEN       LL_I2S_EnableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Disable DMA Rx
+  * @rmtoll CFG1         RXDMAEN       LL_I2S_DisableDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CFG1         RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+  * @brief  Enable DMA Tx
+  * @rmtoll CFG1         TXDMAEN       LL_I2S_EnableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+  * @brief  Disable DMA Tx
+  * @rmtoll CFG1         TXDMAEN       LL_I2S_DisableDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+  LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CFG1         TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
+  * @param  SPIx SPI Instance
+  * @retval State of bit (1 or 0)
+  */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_LL_EF_DATA_Management DATA_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Data Register
+  * @rmtoll RXDR         .       LL_I2S_ReceiveData16
+  * @param  SPIx SPI Instance
+  * @retval 0..0xFFFF
+  */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+  * @brief  Read Data Register
+  * @rmtoll RXDR         .       LL_I2S_ReceiveData32
+  * @param  SPIx SPI Instance
+  * @retval  0..0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  return LL_SPI_ReceiveData32(SPIx);
+}
+
+/**
+  * @brief  Write Data Register
+  * @rmtoll TXDR         .       LL_I2S_TransmitData16
+  * @param  SPIx SPI Instance
+  * @param  TxData 0..0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+  LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+  * @brief  Write Data Register
+  * @rmtoll TXDR         .       LL_I2S_TransmitData32
+  * @param  SPIx SPI Instance
+  * @param  TxData 0..0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
+{
+  LL_SPI_TransmitData32(SPIx, TxData);
+}
+
+
+/**
+  * @}
+  */
+
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct);
+void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_SPI_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_system.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_system.h
new file mode 100644
index 000000000..ed92ab541
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_system.h
@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+  @endverbatim
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_SYSTEM_H
+#define STM32N6xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
+  * @{
+  */
+#define LL_SYSCFG_VDD_CELL_CODE                  0U               /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/
+#define LL_SYSCFG_VDD_REGISTER_CODE              SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PA6     SYSCFG_CFGR1_PA6_FMP   /*!< Enable Fast Mode Plus on PA6  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PA7     SYSCFG_CFGR1_PA7_FMP   /*!< Enable Fast Mode Plus on PA7  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PA15    SYSCFG_CFGR1_PA15_FMP  /*!< Enable Fast Mode Plus on PA15 */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB3     SYSCFG_CFGR1_PB3_FMP   /*!< Enable Fast Mode Plus on PB3  */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal
+                                                                   with Break Input of TIM1/16/17                       */
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection
+                                                                   with TIM1/16/17 Break Input and also
+                                                                   the PVDE and PLS bits of the Power Control Interface */
+#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK   SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM ECC double error signal
+                                                                   with Break Input of TIM1/16/17                       */
+#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM33
+                                                                   with Break Input of TIM1/16/17                       */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
+  * @note Only available when system implements security (TZEN=1)
+  * @{
+  */
+#define LL_SYSCFG_CLOCK_SEC                SYSCFG_SECCFGR_SYSCFGSEC  /*!< SYSCFG clock configuration secure-only access */
+#define LL_SYSCFG_CLOCK_NSEC               0U                        /*!< SYSCFG clock configuration secure/non-secure access */
+#define LL_SYSCFG_CLASSB_SEC               SYSCFG_SECCFGR_CLASSBSEC  /*!< Class B configuration secure-only access */
+#define LL_SYSCFG_CLASSB_NSEC              0U                        /*!< Class B configuration secure/non-secure access */
+#define LL_SYSCFG_FPU_SEC                  SYSCFG_SECCFGR_FPUSEC     /*!< FPU configuration secure-only access */
+#define LL_SYSCFG_FPU_NSEC                 0U                        /*!< FPU configuration secure/non-secure access */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#define LL_DBGMCU_DBTRGIN                  0U                  /*!< DBTRGIO connected to DBTRGIN   */
+#define LL_DBGMCU_DBTRGOUT                 DBGMCU_CR_DBTRGOEN  /*!<  DBTRGIO connected to DBTRGOUT */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP          DBGMCU_APB1LFZ1_DBG_TIM2_STOP
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP          DBGMCU_APB1LFZ1_DBG_TIM3_STOP         /*!< TIM3 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP          DBGMCU_APB1LFZ1_DBG_TIM4_STOP         /*!< TIM4 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP          DBGMCU_APB1LFZ1_DBG_TIM5_STOP         /*!< TIM5 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP          DBGMCU_APB1LFZ1_DBG_TIM6_STOP         /*!< TIM6 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP          DBGMCU_APB1LFZ1_DBG_TIM7_STOP         /*!< TIM7 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP         DBGMCU_APB1LFZ1_DBG_TIM12_STOP        /*!< TIM12 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP         DBGMCU_APB1LFZ1_DBG_TIM13_STOP        /*!< TIM13 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP         DBGMCU_APB1LFZ1_DBG_TIM14_STOP        /*!< TIM14 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP        DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP       /*!< LPTIM1 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP          DBGMCU_APB1LFZ1_DBG_WWDG1_STOP        /*!< WWDG1 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM10_STOP         DBGMCU_APB1LFZ1_DBG_TIM10_STOP        /*!< TIM10 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_TIM11_STOP         DBGMCU_APB1LFZ1_DBG_TIM11_STOP        /*!< TIM11 stop in debug */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP          DBGMCU_APB1LFZ1_DBG_I2C1_STOP         /*!< I2C1 SMBUS timeout stop in debug */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP          DBGMCU_APB1LFZ1_DBG_I2C2_STOP         /*!< I2C2 SMBUS timeout stop in debug */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP          DBGMCU_APB1LFZ1_DBG_I2C3_STOP         /*!< I2C3 SMBUS timeout stop in debug */
+#define LL_DBGMCU_APB1_GRP1_I3C1_STOP          DBGMCU_APB1LFZ1_DBG_I3C1_STOP         /*!< I3C1 SMBUS timeout stop in debug */
+#define LL_DBGMCU_APB1_GRP1_I3C2_STOP          DBGMCU_APB1LFZ1_DBG_I3C2_STOP         /*!< I3C2 SMBUS timeout stop in debug */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP         DBGMCU_APB1HFZ1_DBG_FDCAN_STOP       /*!< FDCAN stop in debug */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP         DBGMCU_APB2FZ1_DBG_TIM1_STOP            /*!< TIM1 stop in debug */
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP         DBGMCU_APB2FZ1_DBG_TIM8_STOP            /*!< TIM8 stop in debug */
+#define LL_DBGMCU_APB2_GRP1_TIM18_STOP        DBGMCU_APB2FZ1_DBG_TIM18_STOP           /*!< TIM18 stop in debug */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP        DBGMCU_APB2FZ1_DBG_TIM15_STOP           /*!< TIM15 stop in debug */
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP        DBGMCU_APB2FZ1_DBG_TIM16_STOP           /*!< TIM16 stop in debug */
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP        DBGMCU_APB2FZ1_DBG_TIM17_STOP           /*!< TIM17 stop in debug */
+#define LL_DBGMCU_APB2_GRP1_TIM9_STOP         DBGMCU_APB2FZ1_DBG_TIM9_STOP            /*!< TIM9 stop in debug */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB4_GRP1_I2C4_STOP         DBGMCU_APB4FZ1_DBG_I2C4_STOP            /*!< I2C4 stop in debug */
+#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP       DBGMCU_APB4FZ1_DBG_LPTIM2_STOP          /*!< LPTIM2 stop in debug */
+#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP       DBGMCU_APB4FZ1_DBG_LPTIM3_STOP          /*!< LPTIM3 stop in debug */
+#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP       DBGMCU_APB4FZ1_DBG_LPTIM4_STOP          /*!< LPTIM4 stop in debug */
+#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP       DBGMCU_APB4FZ1_DBG_LPTIM5_STOP          /*!< LPTIM5 stop in debug */
+#define LL_DBGMCU_APB4_GRP1_RTC_STOP          DBGMCU_APB4FZ1_DBG_RTC_STOP             /*!< RTC stop in debug */
+#define LL_DBGMCU_APB4_GRP1_IWDG_STOP         DBGMCU_APB4FZ1_DBG_IWDG_STOP            /*!< IWDG stop in debug */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB5_GRP1_STOP_IP DBGMCU APB5 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB5_GRP1_GFXTIM_STOP       DBGMCU_APB5FZ1_DBG_GFXTIM_STOP          /*!< GFXTIM stop in debug */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP      /*!< GPDMA1_CH0 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP      /*!< GPDMA1_CH1 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP      /*!< GPDMA1_CH2 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP      /*!< GPDMA1_CH3 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP      /*!< GPDMA1_CH4 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP      /*!< GPDMA1_CH5 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP      /*!< GPDMA1_CH6 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP      /*!< GPDMA1_CH7 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP      /*!< GPDMA1_CH8 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP   DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP      /*!< GPDMA1_CH9 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP  DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP     /*!< GPDMA1_CH10 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP  DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP     /*!< GPDMA1_CH11 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP  DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP     /*!< GPDMA1_CH12 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP  DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP     /*!< GPDMA1_CH13 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP  DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP     /*!< GPDMA1_CH14 suspend in debug */
+#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP  DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP     /*!< GPDMA1_CH15 suspend in debug */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_AHB5_GRP1_STOP_IP DBGMCU AHB5 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP      /*!< HPDMA1_CH0 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP      /*!< HPDMA1_CH1 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP      /*!< HPDMA1_CH2 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP      /*!< HPDMA1_CH3 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP      /*!< HPDMA1_CH4 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP      /*!< HPDMA1_CH5 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP      /*!< HPDMA1_CH6 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP      /*!< HPDMA1_CH7 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP      /*!< HPDMA1_CH8 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP   DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP      /*!< HPDMA1_CH9 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP  DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP     /*!< HPDMA1_CH10 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP  DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP     /*!< HPDMA1_CH11 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP  DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP     /*!< HPDMA1_CH12 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP  DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP     /*!< HPDMA1_CH13 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP  DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP     /*!< HPDMA1_CH14 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP  DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP     /*!< HPDMA1_CH15 suspend in debug */
+#define LL_DBGMCU_AHB5_GRP1_NPU_STOP          DBGMCU_AHB5FZ1_NPU_DBG_FREEZE           /*!< NPU stop in debug mode */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Returns the device identifier
+  * @note The BSEC clock must be enabled before calling this function
+  *       Returned Device ID can be
+  *       0x00006200 for STM32N645xx
+  *       0x00006000 for STM32N655xx
+  *       0x00002200 for STM32N647xx
+  *       0x00002000 for STM32N657xx
+  *       0xffffffff if an error occurs
+  * @retval Device identifier
+  */
+__STATIC_INLINE uint32_t LL_GetDeviceID(void)
+{
+  return (uint32_t)(READ_REG(BSEC->FVRw[9]));
+}
+
+
+/**
+  * @brief  Returns the device revision identifier
+  * @note Returned Revision ID can be
+  *       0x00000100 for Cut1.0
+  *       0x00000101 for Cut1.1
+  *       0x00000200 for Cut2.0
+  * @retval Device revision identifier
+  */
+__STATIC_INLINE uint32_t LL_GetRevisionID(void)
+{
+  return *(uint32_t *)(REVID_BASE);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP      LL_DBGMCU_EnableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP      LL_DBGMCU_DisableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Enable the Debug clock through software
+  * @rmtoll DBGMCU_CR    DBGCLKEN   LL_DBGMCU_EnableDBGClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN);
+}
+
+/**
+  * @brief  Disable the Debug clock through software
+  * @rmtoll DBGMCU_CR    DBGCLKEN   LL_DBGMCU_DisableDBGClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN);
+}
+
+/**
+  * @brief  Enable the TPIU export clock enable through software
+  * @rmtoll DBGMCU_CR    TRACECLKEN   LL_DBGMCU_EnableTPIUExportClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableTPIUExportClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
+}
+
+/**
+  * @brief  Disable the TPIU export clock enable through software
+  * @rmtoll DBGMCU_CR    TRACECLKEN   LL_DBGMCU_DisableTPIUExportClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableTPIUExportClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
+}
+
+/**
+  * @brief  Set DBTRGIO connection control
+  * @rmtoll DBGMCU_CR    DBTRGOEN   LL_DBGMCU_SetDBTRGIOConnectionControl
+  * @param  ConfigDBTRGIO This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_DBTRGIN
+  *         @arg @ref LL_DBGMCU_DBTRGOUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetDBTRGIOConnectionControl(uint32_t ConfigDBTRGIO)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBTRGOEN, ConfigDBTRGIO);
+}
+
+/**
+  * @brief  Get DBTRGIO connection control
+  * @rmtoll DBGMCU_CR    DBTRGOEN   LL_DBGMCU_GetDBTRGIOConnectionControl
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_DBTRGIN
+  *         @arg @ref LL_DBGMCU_DBTRGOUT
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDBTRGIOConnectionControl(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBTRGOEN));
+}
+
+/**
+  * @brief  Enable TSGEN halt
+  * @rmtoll DBGMCU_CR    HLT_TSGEN_EN   LL_DBGMCU_EnableTSGENHalt
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableTSGENHalt(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN);
+}
+
+/**
+  * @brief  Disable TSGEN halt
+  * @rmtoll DBGMCU_CR    HLT_TSGEN_EN   LL_DBGMCU_DisableTSGENHalt
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableTSGENHalt(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN);
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1LFZ1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1LFZ DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group2 peripherals)
+  * @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group2 peripherals)
+  * @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP  LL_DBGMCU_APB2_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP  LL_DBGMCU_APB2_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_UnFreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP  LL_DBGMCU_APB4_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+
+/**
+  * @brief  Unreeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP  LL_DBGMCU_APB4_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_UnFreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB5 peripherals
+  * @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP  LL_DBGMCU_APB5_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB5_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB5FZ1, Periphs);
+}
+
+/**
+  * @brief  Unreeze APB5 peripherals
+  * @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP  LL_DBGMCU_APB5_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB5_UnFreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB5FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze AHB1 peripherals
+  * @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP  LL_DBGMCU_AHB1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_AHB1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->AHB1FZ1, Periphs);
+}
+
+/**
+  * @brief  Unreeze AHB1 peripherals
+  * @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP  LL_DBGMCU_AHB1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP
+  *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_AHB1_UnFreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->AHB1FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze AHB5 peripherals
+  * @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP  LL_DBGMCU_AHB5_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_AHB5_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->AHB5FZ1, Periphs);
+}
+
+/**
+  * @brief  Unreeze AHB5 peripherals
+  * @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP  LL_DBGMCU_AHB5_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP
+  *         @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_AHB5_UnFreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->AHB5FZ1, Periphs);
+}
+
+
+/**
+  * @}
+  */
+
+#endif /* defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_SYSTEM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_tim.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_tim.h
new file mode 100644
index 000000000..6e6656696
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_tim.h
@@ -0,0 +1,6272 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32N6xx_LL_TIM_H
+#define __STM32N6xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1)  \
+ || defined (TIM2)  \
+ || defined (TIM3)  \
+ || defined (TIM4)  \
+ || defined (TIM5)  \
+ || defined (TIM6)  \
+ || defined (TIM7)  \
+ || defined (TIM8)  \
+ || defined (TIM9)  \
+ || defined (TIM10) \
+ || defined (TIM11) \
+ || defined (TIM12) \
+ || defined (TIM13) \
+ || defined (TIM14) \
+ || defined (TIM15) \
+ || defined (TIM16) \
+ || defined (TIM17) \
+ || defined (TIM18)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U,   /* 6: TIMx_CH4  */
+  0x04U,   /* 7: TIMx_CH4N */
+  0x38U,   /* 8: TIMx_CH5  */
+  0x38U    /* 9: TIMx_CH6  */
+
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U,            /* 6: OC4M, OC4FE, OC4PE */
+  0U,            /* 7: - NA */
+  0U,            /* 8: OC5M, OC5FE, OC5PE */
+  8U             /* 9: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U,            /* 6: CC4S, IC4PSC, IC4F */
+  0U,            /* 7: - NA */
+  0U,            /* 8: - NA */
+  0U             /* 9: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U,           /* 6: CC4P */
+  14U,           /* 7: CC4NP */
+  16U,           /* 8: CC5P */
+  20U            /* 9: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U,            /* 6: OIS4 */
+  7U,            /* 7: OIS4N */
+  8U,            /* 8: OIS5 */
+  10U            /* 9: OIS6 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP     TIM_AF1_BKINP     /*!< BRK BKIN input polarity */
+#define TIMx_AF1_ETRSEL    TIM_AF1_ETRSEL    /*!< TIMx ETR source selection */
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+/**
+@endcond
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
+#define LL_TIM_SR_IDXF                         TIM_SR_IDXF          /*!< Index interrupt flag  */
+#define LL_TIM_SR_DIRF                         TIM_SR_DIRF          /*!< Direction Change interrupt flag  */
+#define LL_TIM_SR_IERRF                        TIM_SR_IERRF         /*!< Index Error flag  */
+#define LL_TIM_SR_TERRF                        TIM_SR_TERRF         /*!< Transition Error flag  */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+  * @{
+  */
+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+#define LL_TIM_DIER_IDXIE                      TIM_DIER_IDXIE       /*!< Index interrupt enable */
+#define LL_TIM_DIER_DIRIE                      TIM_DIER_DIRIE       /*!< Direction Change interrupt enable */
+#define LL_TIM_DIER_IERRIE                     TIM_DIER_IERRIE      /*!< Index Error interrupt enable */
+#define LL_TIM_DIER_TERRIE                     TIM_DIER_TERRIE      /*!< Transition Error interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH4N                    TIM_CCER_CC4NE     /*!< Timer complementary output channel 4 */
+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+@endcond
+  */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
+#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
+#define LL_TIM_OCMODE_PULSE_ON_COMPARE         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)                    /*!<Pulse on Compare mode */
+#define LL_TIM_OCMODE_DIRECTION_OUTPUT         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+  * @{
+  */
+#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)                                   /*!< Encoder mode: Clock plus direction - x2 mode */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2       (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)                                   /*!< Encoder mode: Directional Clock, x2 mode */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12  (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define LL_TIM_ENCODERMODE_X1_TI1                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
+#define LL_TIM_ENCODERMODE_X1_TI2                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+#define LL_TIM_TRGO_ENCODERCLK                 TIM_CR2_MMS_3                                   /*!< Encoder clock signal is used as trigger output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+  * @{
+  */
+#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
+#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)   /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
+                                                                                        the counter are controlled. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
+  * @{
+  */
+#define LL_TIM_SMSPS_TIMUPDATE                 0x00000000U                         /*!< The SMS preload transfer is triggered by the Timer's Update event */
+#define LL_TIM_SMSPS_INDEX                     TIM_SMCR_SMSPS                      /*!< The SMS preload transfer is triggered by the Index event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
+#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_0)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
+#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
+#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
+#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_2)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
+#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
+#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
+#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
+#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
+#define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_4 | TIM_SMCR_TS_0)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
+  * @{
+  */
+#define LL_TIM_TIM1_ETRSOURCE_GPIO           0x00000000UL                                                /*!< TIM1_ETR is connected to I/O */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1      (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                       /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2      TIM_AF1_ETRSEL_2                                            /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                       /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                       /*!< TIM1_ETR is connected to ADC2 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)    /*!< TIM1_ETR is connected to ADC2 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3      TIM_AF1_ETRSEL_3                                            /*!< TIM1_ETR is connected to ADC2 AWD3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
+  * @{
+  */
+#define LL_TIM_TIM2_ETRSOURCE_GPIO          0x00000000UL                                                                 /*!< TIM2_ETR is connected to I/O */
+#define LL_TIM_TIM2_ETRSOURCE_DCMIPP_HSYNC  TIM_AF1_ETRSEL_0                                                             /*!< TIM2_ETR is connected to DCMIPP HSYNC */
+#define LL_TIM_TIM2_ETRSOURCE_LCD_HSYNC     TIM_AF1_ETRSEL_1                                                             /*!< TIM2_ETR is connected to LCD HSYNC      */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA      TIM_AF1_ETRSEL_2                                                             /*!< TIM2_ETR is connected to SAI1 FS_A      */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                                        /*!< TIM2_ETR is connected to SAI1 FS_B */
+#define LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE     (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                                        /*!< TIM2_ETR is connected to GFXTIM TE */
+#define LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC  (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to DCMIPP VSYNC */
+#define LL_TIM_TIM2_ETRSOURCE_LCD_VSYNC     TIM_AF1_ETRSEL_3                                                             /*!< TIM2_ETR is connected to LCD VSYNC */
+#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1)                                        /*!< TIM2_ETR is connected to TIM3 ETR */
+#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to TIM4 ETR */
+#define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2)                                        /*!< TIM2_ETR is connected to TIM5 ETR */
+#define LL_TIM_TIM2_ETRSOURCE_ETH1_PPS      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to ETH1 PPS */
+#define LL_TIM_TIM2_ETRSOURCE_USB1_SOF      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                     /*!< TIM2_ETR is connected to USB1 OTG SOF */
+#define LL_TIM_TIM2_ETRSOURCE_USB2_SOF      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)  /*!< TIM2_ETR is connected to USB2 OTG SOF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
+  * @{
+  */
+#define LL_TIM_TIM3_ETRSOURCE_GPIO          0x00000000UL                                                /*!< TIM3_ETR is connected to I/O */
+#define LL_TIM_TIM3_ETRSOURCE_DCMIPP_HSYNC  TIM_AF1_ETRSEL_0                                            /*!< TIM3_ETR is connected to DCMIPP HSYNC */
+#define LL_TIM_TIM3_ETRSOURCE_LCD_HSYNC     TIM_AF1_ETRSEL_1                                            /*!< TIM3_ETR is connected to LCD HSYNC */
+#define LL_TIM_TIM3_ETRSOURCE_GFXTIM_TE     (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                       /*!< TIM3_ETR is connected to GFXTIM TE */
+#define LL_TIM_TIM3_ETRSOURCE_DCMIPP_VSYNC  (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)    /*!< TIM3_ETR is connected to DCMIPP VSYNC */
+#define LL_TIM_TIM3_ETRSOURCE_LCD_VSYNC     TIM_AF1_ETRSEL_3                                            /*!< TIM3_ETR is connected to LCD VSYNC */
+#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0)                       /*!< TIM3_ETR is connected to TIM2 ETR */
+#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)    /*!< TIM3_ETR is connected to TIM4 ETR */
+#define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2)                       /*!< TIM3_ETR is connected to TIM5 ETR */
+#define LL_TIM_TIM3_ETRSOURCE_ETH1_PPS      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)    /*!< TIM3_ETR is connected to ETH1 PPS */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
+  * @{
+  */
+#define LL_TIM_TIM4_ETRSOURCE_GPIO          0x00000000UL                                                /*!< TIM4_ETR is connected to I/O */
+#define LL_TIM_TIM4_ETRSOURCE_DCMIPP_HSYNC  TIM_AF1_ETRSEL_0                                            /*!< TIM4_ETR is connected to DCMIPP HSYNC */
+#define LL_TIM_TIM4_ETRSOURCE_LCD_HSYNC     TIM_AF1_ETRSEL_1                                            /*!< TIM4_ETR is connected to LCD HSYNC */
+#define LL_TIM_TIM4_ETRSOURCE_GFXTIM_TE     (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                       /*!< TIM4_ETR is connected to GFXTIM TE */
+#define LL_TIM_TIM4_ETRSOURCE_DCMIPP_VSYNC  (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)    /*!< TIM4_ETR is connected to DCMIPP VSYNC */
+#define LL_TIM_TIM4_ETRSOURCE_LCD_VSYNC     TIM_AF1_ETRSEL_3                                            /*!< TIM4_ETR is connected to LCD VSYNC */
+#define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0)                       /*!< TIM4_ETR is connected to TIM2 ETR */
+#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1)                       /*!< TIM4_ETR is connected to TIM3 ETR */
+#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2)                       /*!< TIM4_ETR is connected to TIM5 ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
+  * @{
+  */
+#define LL_TIM_TIM5_ETRSOURCE_GPIO          0x00000000UL                                                                 /*!< TIM5_ETR is connected to I/O */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA      TIM_AF1_ETRSEL_0                                                             /*!< TIM5_ETR is connected to SAI2 FS_A */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB      TIM_AF1_ETRSEL_1                                                             /*!< TIM5_ETR is connected to SAI2 FS_B */
+#define LL_TIM_TIM5_ETRSOURCE_DCMIPP_HSYNC  (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                                        /*!< TIM5_ETR is connected to DCMIPP HSYNC */
+#define LL_TIM_TIM5_ETRSOURCE_LCD_HSYNC     TIM_AF1_ETRSEL_2                                                             /*!< TIM5_ETR is connected to LCD HSYNC */
+#define LL_TIM_TIM5_ETRSOURCE_GFXTIM_TE     (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                                        /*!< TIM5_ETR is connected to GFXTIM TE */
+#define LL_TIM_TIM5_ETRSOURCE_DCMIPP_VSYNC  (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM5_ETR is connected to DCMIPP VSYNC */
+#define LL_TIM_TIM5_ETRSOURCE_LCD_VSYNC     TIM_AF1_ETRSEL_3                                                             /*!< TIM5_ETR is connected to LCD VSYNC */
+#define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0)                                        /*!< TIM5_ETR is connected to TIM2 ETR */
+#define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1)                                        /*!< TIM5_ETR is connected to TIM3 ETR */
+#define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                     /*!< TIM5_ETR is connected to TIM5 ETR */
+#define LL_TIM_TIM5_ETRSOURCE_USB1_SOF      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1)                     /*!< TIM5_ETR is connected to USB1 OTG SOF */
+#define LL_TIM_TIM5_ETRSOURCE_USB2_SOF      (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)  /*!< TIM5_ETR is connected to USB2 OTG SOF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
+  * @{
+  */
+#define LL_TIM_TIM8_ETRSOURCE_GPIO           0x00000000UL                                                /*!< TIM8_ETR is connected to I/O */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1      (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)                       /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2      TIM_AF1_ETRSEL_2                                            /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3      (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)                       /*!< TIM8_ETR is connected to ADC2 AWD3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+  * @{
+  */
+#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+  * @{
+  */
+#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+  * @{
+  */
+#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
+  * @{
+  */
+#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
+#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
+  * @{
+  */
+#define LL_TIM_BKIN_SOURCE_BKIN                TIM_AF1_BKINE      /*!< BKIN input from AF controller */
+#define LL_TIM_BKIN_SOURCE_MDF1                TIM_AF1_BKCMP8E    /*!< internal signal: MDF1 output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
+  * @{
+  */
+#define LL_TIM_BKIN_POLARITY_LOW               TIM_AF1_BKINP           /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_ReArmBRK(_PARAM_)
+#define LL_TIM_ReArmBRK2(_PARAM_)
+/**
+@endcond
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DTR2          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ECR           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_ECR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_19TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 19 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_20TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 20 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_21TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 21 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_22TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 22 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_23TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 23 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_24TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_25TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_3)                                 /*!< Transfer is done to 25 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_26TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 26 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
+  * @{
+  */
+#define LL_TIM_DMA_UPDATE                      TIM_DCR_DBSS_0                                                  /*!< Transfer source is update event */
+#define LL_TIM_DMA_CC1                         TIM_DCR_DBSS_1                                                  /*!< Transfer source is CC1 event */
+#define LL_TIM_DMA_CC2                         (TIM_DCR_DBSS_1 |  TIM_DCR_DBSS_0)                              /*!< Transfer source is CC2 event */
+#define LL_TIM_DMA_CC3                         TIM_DCR_DBSS_2                                                  /*!< Transfer source is CC3 event */
+#define LL_TIM_DMA_CC4                         (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0)                               /*!< Transfer source is CC4 event */
+#define LL_TIM_DMA_COM                         (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1)                               /*!< Transfer source is COM event */
+#define LL_TIM_DMA_TRIGGER                     (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0)              /*!< Transfer source is trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI1_RMP  TIM2 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI1_RMP_GPIO                0x00000000UL                                               /*!< TIM2_TI1 is connected to GPIO */
+#define LL_TIM_TIM2_TI1_RMP_ETH1_PPS            TIM_TISEL_TI1SEL_0                                         /*!< TIM2_TI1 is connected to ETH1 PPS */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI1_RMP_GPIO                0x00000000UL                                               /*!< TIM3_TI1 is connected to GPIO */
+#define LL_TIM_TIM3_TI1_RMP_ETH1_PPS            TIM_TISEL_TI1SEL_0                                         /*!< TIM3_TI1 is connected to ETH1 PPS */
+#define LL_TIM_TIM3_TI1_RMP_FDCAN_RTP           TIM_TISEL_TI1SEL_1                                         /*!< TIM3_TI1 is connected to FDCAN RTP */
+#define LL_TIM_TIM3_TI1_RMP_FDCAN_TMP           (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                  /*!< TIM3_TI1 is connected to FDCAN TMP */
+#define LL_TIM_TIM3_TI1_RMP_FDCAN_SOC           TIM_TISEL_TI1SEL_2                                         /*!< TIM3_TI1 is connected to FDCAN SOC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM5_TI1_RMP_GPIO                0x00000000UL                                               /*!< TIM5_TI1 is connected to GPIO */
+#define LL_TIM_TIM5_TI1_RMP_FDCAN_RTP           TIM_TISEL_TI1SEL_1                                         /*!< TIM5_TI1 is connected to FDCAN RTP */
+#define LL_TIM_TIM5_TI1_RMP_FDCAN_TMP           (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                  /*!< TIM5_TI1 is connected to FDCAN TMP */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM9_TI1_RMP  TIM9 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM9_TI1_RMP_GPIO            0x00000000UL                                                   /*!< TIM9_TI1 is connected to GPIO */
+#define LL_TIM_TIM9_TI1_RMP_MCO1            TIM_TISEL_TI1SEL_2                                             /*!< TIM9_TI1 is connected to MCO1 */
+#define LL_TIM_TIM9_TI1_RMP_MCO2            (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)                      /*!< TIM9_TI1 is connected to MCO2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM10_TI1_RMP  TIM10 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM10_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM10_TI1 is connected to GPIO */
+#define LL_TIM_TIM10_TI1_RMP_I3C1_IBIACK    TIM_TISEL_TI1SEL_0                                             /*!< TIM10_TI1 is connected to I3C1 IBI ACK */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM11_TI1_RMP  TIM11 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM11_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM11_TI1 is connected to GPIO */
+#define LL_TIM_TIM11_TI1_RMP_I3C2_IBIACK    TIM_TISEL_TI1SEL_0                                             /*!< TIM11_TI1 is connected to I3C2 IBI ACK */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM12_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM12_TI1 is connected to GPIO */
+#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS       TIM_TISEL_TI1SEL_0                                             /*!< TIM12 TI1 is connected to SPDIF FS */
+#define LL_TIM_TIM12_TI1_RMP_HSI_1024       TIM_TISEL_TI1SEL_1                                             /*!< TIM12_TI1 is connected to HSI/1024 */
+#define LL_TIM_TIM12_TI1_RMP_MSI_128        (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM12_TI1 is connected to MSI/128 */
+#define LL_TIM_TIM12_TI1_RMP_MCO1           TIM_TISEL_TI1SEL_2                                             /*!< TIM12_TI1 is connected to MCO1 */
+#define LL_TIM_TIM12_TI1_RMP_MCO2           (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)                      /*!< TIM12_TI1 is connected to MCO2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM13_TI1_RMP  TIM13 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM13_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM13_TI1 is connected to GPIO */
+#define LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK    TIM_TISEL_TI1SEL_0                                             /*!< TIM13_TI1 is connected to I3C1 IBI ACK */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM14_TI1_RMP  TIM14 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM14_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM14_TI1 is connected to GPIO */
+#define LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK    TIM_TISEL_TI1SEL_0                                             /*!< TIM14_TI1 is connected to I3C2 IBI ACK */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM15_TI1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1       TIM_TISEL_TI1SEL_0                                             /*!< TIM15_TI1 is connected to TIM2 CH1 GPIO */
+#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1       TIM_TISEL_TI1SEL_1                                             /*!< TIM15_TI1 is connected to TIM3 CH1 GPIO */
+#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1       (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM15_TI1 is connected to TIM4 CH1 GPIO */
+#define LL_TIM_TIM15_TI1_RMP_MCO1           TIM_TISEL_TI1SEL_2                                             /*!< TIM15_TI1 is connected to MCO1 */
+#define LL_TIM_TIM15_TI1_RMP_MCO2           (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)                      /*!< TIM15_TI1 is connected to MCO2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 External Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI2_RMP_GPIO           0x00000000UL                                                   /*!< TIM15_TI2 is connected to GPIO */
+#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2       TIM_TISEL_TI2SEL_0                                             /*!< TIM15_TI2 is connected to TIM2 CH2 GPIO */
+#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2       TIM_TISEL_TI2SEL_1                                             /*!< TIM15_TI2 is connected to TIM3 CH2 GPIO */
+#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2       (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)                      /*!< TIM15_TI2 is connected to TIM4 CH2 GPIO */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM16_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM16_TI1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_LSI            TIM_TISEL_TI1SEL_0                                             /*!< TIM16 TI1 is connected to LSI */
+#define LL_TIM_TIM16_TI1_RMP_LSE            TIM_TISEL_TI1SEL_1                                             /*!< TIM16 TI1 is connected to LSE */
+#define LL_TIM_TIM16_TI1_RMP_RTC_WKUP       (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)                      /*!< TIM16_TI1 is connected to RTC Wakeup */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM17_TI1_RMP_GPIO           0x00000000UL                                                   /*!< TIM17_TI1 is connected to GPIO */
+#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS       TIM_TISEL_TI1SEL_0                                             /*!< TIM17_TI1 is connected to SPDIFRX FS */
+#define LL_TIM_TIM17_TI1_RMP_HSE_1024       TIM_TISEL_TI1SEL_1                                             /*!< TIM17 TI1 is connected to HSE/1024 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
+  * @{
+  */
+#define LL_TIM_INDEX_UP_DOWN     0x00000000U         /*!< Index resets the counter whatever the direction */
+#define LL_TIM_INDEX_UP          TIM_ECR_IDIR_0      /*!< Index resets the counter when up-counting only */
+#define LL_TIM_INDEX_DOWN        TIM_ECR_IDIR_1      /*!< Index resets the counter when down-counting only */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
+  * @{
+  */
+#define LL_TIM_INDEX_BLANK_ALWAYS     0x00000000U         /*!< Index always active */
+#define LL_TIM_INDEX_BLANK_TI3        TIM_ECR_IBLK_0      /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
+#define LL_TIM_INDEX_BLANK_TI4        TIM_ECR_IBLK_1      /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
+  * @{
+  */
+#define LL_TIM_INDEX_POSITION_DOWN_DOWN    0x00000000U                           /*!< Index resets the counter when AB = 00 */
+#define LL_TIM_INDEX_POSITION_DOWN_UP      TIM_ECR_IPOS_0                        /*!< Index resets the counter when AB = 01 */
+#define LL_TIM_INDEX_POSITION_UP_DOWN      TIM_ECR_IPOS_1                        /*!< Index resets the counter when AB = 10 */
+#define LL_TIM_INDEX_POSITION_UP_UP        (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)     /*!< Index resets the counter when AB = 11 */
+#define LL_TIM_INDEX_POSITION_DOWN         0x00000000U                           /*!< Index resets the counter when clock is 0 */
+#define LL_TIM_INDEX_POSITION_UP           TIM_ECR_IPOS_0                        /*!< Index resets the counter when clock is 1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
+  * @{
+  */
+#define LL_TIM_INDEX_ALL           0x00000000U                           /*!< Index is always active */
+#define LL_TIM_INDEX_FIRST_ONLY    TIM_ECR_FIDX                          /*!< The first Index only resets the counter */
+/**
+  * @}
+  */
+/** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
+  * @{
+  */
+#define LL_TIM_PWPRSC_X1     0x00000000U                                              /*!< Pulse on compare pulse width prescaler 1 */
+#define LL_TIM_PWPRSC_X2     TIM_ECR_PWPRSC_0                                         /*!< Pulse on compare pulse width prescaler 2 */
+#define LL_TIM_PWPRSC_X4     TIM_ECR_PWPRSC_1                                         /*!< Pulse on compare pulse width prescaler 4 */
+#define LL_TIM_PWPRSC_X8     (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 8 */
+#define LL_TIM_PWPRSC_X16    TIM_ECR_PWPRSC_2                                         /*!< Pulse on compare pulse width prescaler 16 */
+#define LL_TIM_PWPRSC_X32    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 32 */
+#define LL_TIM_PWPRSC_X64    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1)                    /*!< Pulse on compare pulse width prescaler 64 */
+#define LL_TIM_PWPRSC_X128   (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
+/**
+@endcond
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+  *        to TIMx_CNT register bit 31)
+  * @param  __CNT__ Counter value
+  * @retval UIF status bit
+  */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
+   (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
+  *         output compare active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         pulse duration (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the Counter value interpretation
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the Counter value interpretation
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  *       In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
+  *       parameter.
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the returned value interpretation
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note For advanced timer instances RepetitionCounter can be up to 65535.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+  * @param  Counter Counter value
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
+{
+  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable dithering.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_EnableDithering
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+  * @brief  Disable dithering.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_DisableDithering
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+  * @brief  Indicates whether dithering is activated.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_IsEnabledDithering
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
+  *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
+  *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+  * @brief  Select on which reference signal the OC5REF is combined to.
+  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the combined 3-phase PWM mode.
+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+  * @param  TIMx Timer instance
+  * @param  GroupCH5 This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_GROUPCH5_NONE
+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+  * @brief  Set the pulse on compare pulse width prescaler.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PWPRSC           LL_TIM_OC_SetPulseWidthPrescaler
+  * @param  TIMx Timer instance
+  * @param  PulseWidthPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_PWPRSC_X1
+  *         @arg @ref LL_TIM_PWPRSC_X2
+  *         @arg @ref LL_TIM_PWPRSC_X4
+  *         @arg @ref LL_TIM_PWPRSC_X8
+  *         @arg @ref LL_TIM_PWPRSC_X16
+  *         @arg @ref LL_TIM_PWPRSC_X32
+  *         @arg @ref LL_TIM_PWPRSC_X64
+  *         @arg @ref LL_TIM_PWPRSC_X128
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
+}
+
+/**
+  * @brief  Get the pulse on compare pulse width prescaler.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PWPRSC           LL_TIM_OC_GetPulseWidthPrescaler
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_PWPRSC_X1
+  *         @arg @ref LL_TIM_PWPRSC_X2
+  *         @arg @ref LL_TIM_PWPRSC_X4
+  *         @arg @ref LL_TIM_PWPRSC_X8
+  *         @arg @ref LL_TIM_PWPRSC_X16
+  *         @arg @ref LL_TIM_PWPRSC_X32
+  *         @arg @ref LL_TIM_PWPRSC_X64
+  *         @arg @ref LL_TIM_PWPRSC_X128
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
+}
+
+/**
+  * @brief  Set the pulse on compare pulse width duration.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PW           LL_TIM_OC_SetPulseWidth
+  * @param  TIMx Timer instance
+  * @param  PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
+}
+
+/**
+  * @brief  Get the pulse on compare pulse width duration.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PW           LL_TIM_OC_GetPulseWidth
+  * @param  TIMx Timer instance
+  * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+  *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
+  *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
+  *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
+  *         @arg @ref LL_TIM_ENCODERMODE_X1_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X1_TI2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  *         @arg @ref LL_TIM_TRGO_ENCODERCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can be used for ADC synchronization.
+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+  * @param  TIMx Timer Instance
+  * @param  ADCSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO2_RESET
+  *         @arg @ref LL_TIM_TRGO2_ENABLE
+  *         @arg @ref LL_TIM_TRGO2_UPDATE
+  *         @arg @ref LL_TIM_TRGO2_CC1F
+  *         @arg @ref LL_TIM_TRGO2_OC1
+  *         @arg @ref LL_TIM_TRGO2_OC2
+  *         @arg @ref LL_TIM_TRGO2_OC3
+  *         @arg @ref LL_TIM_TRGO2_OC4
+  *         @arg @ref LL_TIM_TRGO2_OC5
+  *         @arg @ref LL_TIM_TRGO2_OC6
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_ITR4
+  *         @arg @ref LL_TIM_TS_ITR5
+  *         @arg @ref LL_TIM_TS_ITR6
+  *         @arg @ref LL_TIM_TS_ITR7
+  *         @arg @ref LL_TIM_TS_ITR8
+  *         @arg @ref LL_TIM_TS_ITR9
+  *         @arg @ref LL_TIM_TS_ITR10
+  *         @arg @ref LL_TIM_TS_ITR11
+  *         @arg @ref LL_TIM_TS_ITR12
+  *         @arg @ref LL_TIM_TS_ITR13
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @brief  Select the external trigger (ETR) input source.
+  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports ETR source selection.
+  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
+  * @param  TIMx Timer instance
+  * @param  ETRSource This parameter can be one of the following values:
+  *
+  *         For TIM1, the parameter is one of the following values:
+  *
+  *         @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
+  *         @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
+  *         @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
+  *         @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
+  *         @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1
+  *         @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2
+  *         @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_HSYNC
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_LCD_HSYNC
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_LCD_VSYNC
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_USB1_SOF
+  *         @arg @ref LL_TIM_TIM2_ETRSOURCE_USB2_SOF
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_HSYNC
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_LCD_HSYNC
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_GFXTIM_TE
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_VSYNC
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_LCD_VSYNC
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
+  *         @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR
+  *
+  *         For TIM4, the parameter is one of the following values:
+  *
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_HSYNC
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_LCD_HSYNC
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_GFXTIM_TE
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_VSYNC
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_LCD_VSYNC
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
+  *         @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_HSYNC
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_LCD_HSYNC
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_GFXTIM_TE
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_VSYNC
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_LCD_VSYNC
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_USB1_SOF
+  *         @arg @ref LL_TIM_TIM5_ETRSOURCE_USB2_SOF
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *
+  *         @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
+  *         @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
+  *         @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
+  *         @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
+}
+
+/**
+  * @brief  Enable SMS preload.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_EnableSMSPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+  * @brief  Disable SMS preload.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_DisableSMSPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+  * @brief  Indicate whether  SMS preload is enabled.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_IsEnabledSMSPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the preload source of SMS.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPS        LL_TIM_SetSMSPreloadSource\n
+  * @param  TIMx Timer instance
+  * @param  PreloadSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
+  *         @arg @ref LL_TIM_SMSPS_INDEX
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
+}
+
+/**
+  * @brief  Get the preload source of SMS.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPS        LL_TIM_GetSMSPreloadSource\n
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
+  *         @arg @ref LL_TIM_SMSPS_INDEX
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
+}
+
+
+/**
+  * @brief  Enable ADC synchronization.
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports ADC synchronization.
+  * @rmtoll CR2         ADSYNC           LL_TIM_EnableADCSynchronization
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableADCSynchronization(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_ADSYNC);
+}
+
+/**
+  * @brief  Enable ADC synchronization.
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports ADC synchronization.
+  * @rmtoll CR2         ADSYNC           LL_TIM_DisableADCSynchronization
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableADCSynchronization(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_ADSYNC);
+}
+
+/**
+  * @brief  Indicate whether ADC sycnhronization is enabled.
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports ADC synchronization.
+  * @rmtoll CR2         ADSYNC           LL_TIM_IsEnabledADCSynchronization
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledADCSynchronization(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_ADSYNC) == (TIM_CR2_ADSYNC)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+  *       LL_TIM_BREAK_AFMODE_INPUT.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK\n
+  *         BDTR         BKBID         LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @param  BreakAFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+                                      uint32_t BreakAFMode)
+{
+  __IO uint32_t tmpreg;
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+  /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Disarm the break input (when it operates in bidirectional mode).
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+  * @brief  Enable the break 2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Disable the break  2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+  __IO uint32_t tmpreg;
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+  /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break 2 input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+  *       LL_TIM_BREAK2_AFMODE_INPUT.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @param  Break2AFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+                                       uint32_t Break2AFMode)
+{
+  __IO uint32_t tmpreg;
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+  /* Note: Any write operation to BK2P bit takes a delay of 1 APB clock cycle to become effective. */
+  tmpreg = READ_REG(TIMx->BDTR);
+  (void)(tmpreg);
+}
+
+/**
+  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
+  * @note  The break 2 input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP8E       LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP8E      LL_TIM_EnableBreakInputSource\n
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_MDF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  SET_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Disable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP8E       LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP8E      LL_TIM_DisableBreakInputSource\n
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_MDF1
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  CLEAR_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Set the polarity of the break signal for the timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+                                                        uint32_t Polarity)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+/**
+  * @brief  Enable asymmetrical deadtime.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_EnableAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+  * @brief  Disable asymmetrical dead-time.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_DisableAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+  * @brief  Indicates whether asymmetrical deadtime is activated.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_IsEnabledAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
+  *         rising edge of OCxN signals).
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       asymmetrical dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+  *       (LOCK bits in TIMx_BDTR register).
+  * @rmtoll DTR2         DTGF           LL_TIM_SetFallingDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
+}
+
+/**
+  * @brief  Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
+  *         the rising edge of OCxN signals).
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       asymmetrical dead-time insertion feature is supported by a timer instance.
+  * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+  *       (LOCK bits in TIMx_BDTR register).
+  * @rmtoll DTR2          DTGF           LL_TIM_GetFallingDeadTime
+  * @param  TIMx Timer instance
+  * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
+}
+
+/**
+  * @brief  Enable deadtime preload.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_EnableDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+  * @brief  Disable dead-time preload.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_DisableDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+  * @brief  Indicates whether deadtime preload is activated.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_IsEnabledDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
+  * @param  DMABurstSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMA_UPDATE
+  *         @arg @ref LL_TIM_DMA_CC1
+  *         @arg @ref LL_TIM_DMA_CC2
+  *         @arg @ref LL_TIM_DMA_CC3
+  *         @arg @ref LL_TIM_DMA_CC4
+  *         @arg @ref LL_TIM_DMA_COM
+  *         @arg @ref LL_TIM_DMA_TRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
+                                           uint32_t DMABurstSource)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
+             (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Encoder Encoder configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_EnableEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+  * @brief  Disable encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_DisableEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+  * @brief  Indicate whether encoder index is enabled.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_IsEnabledEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Set index direction
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR           LL_TIM_SetIndexDirection
+  * @param  TIMx Timer instance
+  * @param  IndexDirection This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_UP
+  *         @arg @ref LL_TIM_INDEX_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
+}
+
+/**
+  * @brief  Get actual index direction
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR           LL_TIM_GetIndexDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_UP
+  *         @arg @ref LL_TIM_INDEX_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
+}
+
+/**
+  * @brief  Set index blanking
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IBLK           LL_TIM_SetIndexblanking
+  * @param  TIMx Timer instance
+  * @param  Indexblanking This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI3
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
+}
+
+/**
+  * @brief  Get actual index blanking
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IBLK           LL_TIM_GetIndexblanking
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI3
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
+}
+
+
+/**
+  * @brief  Enable first index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_EnableFirstIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+  * @brief  Disable first index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_DisableFirstIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+  * @brief  Indicates whether first index is enabled.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_IsEnabledFirstIndex
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set index positioning
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IPOS           LL_TIM_SetIndexPositionning
+  * @param  TIMx Timer instance
+  * @param  IndexPositionning This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
+}
+
+/**
+  * @brief  Get actual index positioning
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IPOS           LL_TIM_GetIndexPositionning
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
+}
+
+/**
+  * @brief  Configure encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR          LL_TIM_ConfigIDX\n
+  *         ECR          IBLK          LL_TIM_ConfigIDX\n
+  *         ECR          FIDX          LL_TIM_ConfigIDX\n
+  *         ECR          IPOS          LL_TIM_ConfigIDX
+  * @param  TIMx Timer instance
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
+  *         @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  * @rmtoll TIM3_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM5_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM9_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM10_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM11_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM12_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM13_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM14_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM15_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM16_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM17_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *
+  * @param  TIMx Timer instance
+  * @param  Remap Remap param depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of TISEL registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  *         TIM3: one of the following values:
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_ETH1_PPS
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_FDCAN_RTP
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_FDCAN_TMP
+  *            @arg @ref LL_TIM_TIM3_TI1_RMP_FDCAN_SOC
+  *
+  *         TIM5: one of the following values:
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_FDCAN_RTP
+  *            @arg @ref LL_TIM_TIM5_TI1_RMP_FDCAN_TMP
+  *
+  *         TIM9: one of the following values:
+  *            @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM9_TI1_RMP_MCO1
+  *            @arg @ref LL_TIM_TIM9_TI1_RMP_MCO2
+  *
+  *         TIM10: one of the following values:
+  *            @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM10_TI1_RMP_I3C1_IBIACK
+  *
+  *         TIM11: one of the following values:
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_I3C2_IBIACK
+  *
+  *         TIM12: one of the following values:
+  *            @arg @ref LL_TIM_TIM12_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM12_TI1_RMP_SPDIF_FS
+  *            @arg @ref LL_TIM_TIM12_TI1_RMP_HSI_1024
+  *            @arg @ref LL_TIM_TIM12_TI1_RMP_MSI_128
+  *            @arg @ref LL_TIM_TIM12_TI1_RMP_MCO1
+  *            @arg @ref LL_TIM_TIM12_TI1_RMP_MCO2
+  *
+  *         TIM13: one of the following values:
+  *            @arg @ref LL_TIM_TIM13_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK
+  *
+  *         TIM14: one of the following values:
+  *            @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK
+  *
+  *         TIM15: any combination of TI1_RMP and TI2_RMP where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_CH1
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_CH1
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_TIM4_CH1
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_MCO1
+  *            @arg @ref LL_TIM_TIM15_TI1_RMP_MCO2
+  *
+  *            . . TI2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_CH2
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_CH2
+  *            @arg @ref LL_TIM_TIM15_TI2_RMP_TIM4_CH2
+  *
+  *         TIM16: one of the following values:
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WKUP
+  *
+  *         TIM17: one of the following values:
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_SPDIF_FS
+  *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_1024
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break 2 interrupt flag (B2IF).
+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the system break interrupt flag (SBIF).
+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the transition error interrupt flag (TERRF).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           TERRF           LL_TIM_ClearFlag_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
+}
+
+/**
+  * @brief  Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           TERRF           LL_TIM_IsActiveFlag_TERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the index error interrupt flag (IERRF).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           IERRF           LL_TIM_ClearFlag_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
+}
+
+/**
+  * @brief  Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           IERRF           LL_TIM_IsActiveFlag_IERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the direction change interrupt flag (DIRF).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           DIRF           LL_TIM_ClearFlag_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
+}
+
+/**
+  * @brief  Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           DIRF           LL_TIM_IsActiveFlag_DIR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the index interrupt flag (IDXF).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           IDXF           LL_TIM_ClearFlag_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
+}
+
+/**
+  * @brief  Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           IDXF           LL_TIM_IsActiveFlag_IDX
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable transition error interrupt (TERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_EnableIT_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+  * @brief  Disable transition error interrupt (TERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_DisableIT_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+  * @brief  Indicates whether the transition error interrupt (TERRIE) is enabled.
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_IsEnabledIT_TERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable index error interrupt (IERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_EnableIT_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+  * @brief  Disable index error interrupt (IERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_DisableIT_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+  * @brief  Indicates whether the index error interrupt (IERRIE) is enabled.
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_IsEnabledIT_IERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable direction change interrupt (DIRIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_EnableIT_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+  * @brief  Disable direction change interrupt (DIRIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_DisableIT_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change interrupt (DIRIE) is enabled.
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_IsEnabledIT_DIR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable index interrupt (IDXIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_EnableIT_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+  * @brief  Disable index interrupt (IDXIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_DisableIT_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+  * @brief  Indicates whether the index interrupt (IDXIE) is enabled.
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_IsEnabledIT_IDX
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @brief  Generate break 2 event.
+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32N6xx_LL_TIM_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_ucpd.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_ucpd.h
new file mode 100644
index 000000000..30f985708
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_ucpd.h
@@ -0,0 +1,1817 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_ucpd.h
+  * @author  MCD Application Team
+  * @brief   Header file of UCPD LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_UCPD_H
+#define STM32N6xx_LL_UCPD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (UCPD1)
+
+/** @defgroup UCPD_LL UCPD
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  UCPD Init structures definition
+  */
+typedef struct
+{
+  uint32_t psc_ucpdclk;         /*!< Specify the prescaler for the UCPD clock.
+                                     This parameter can be a value of @ref UCPD_LL_EC_PSC.
+                                     This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
+                                */
+
+  uint32_t transwin;            /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
+                                   to achieve a legal tTransitionWindow (set according to peripheral clock to define
+                                    an interval of between 12 and 20 us).
+                                    This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
+                                    This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
+                                */
+
+  uint32_t IfrGap;              /*!< Specify the definition of the clock divider (minus 1) in order to generate
+                                    tInterframeGap from the peripheral clock.
+                                    This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
+                                    This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
+                                */
+
+  uint32_t HbitClockDiv;        /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
+                                     e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
+                                     "UCPD1_CLK".
+                                     This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
+                                     This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
+                                */
+
+} LL_UCPD_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
+  * @{
+  */
+
+/** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_ucpd_ReadReg function
+  * @{
+  */
+#define LL_UCPD_SR_TXIS             UCPD_SR_TXIS                  /*!< Transmit interrupt status                      */
+#define LL_UCPD_SR_TXMSGDISC        UCPD_SR_TXMSGDISC             /*!< Transmit message discarded interrupt           */
+#define LL_UCPD_SR_TXMSGSENT        UCPD_SR_TXMSGSENT             /*!< Transmit message sent interrupt                */
+#define LL_UCPD_SR_TXMSGABT         UCPD_SR_TXMSGABT              /*!< Transmit message abort interrupt               */
+#define LL_UCPD_SR_HRSTDISC         UCPD_SR_HRSTDISC              /*!< HRST discarded interrupt                       */
+#define LL_UCPD_SR_HRSTSENT         UCPD_SR_HRSTSENT              /*!< HRST sent interrupt                            */
+#define LL_UCPD_SR_TXUND            UCPD_SR_TXUND                 /*!< Tx data underrun condition interrupt           */
+#define LL_UCPD_SR_RXNE             UCPD_SR_RXNE                  /*!< Receive data register not empty interrupt      */
+#define LL_UCPD_SR_RXORDDET         UCPD_SR_RXORDDET              /*!< Rx ordered set (4 K-codes) detected interrupt  */
+#define LL_UCPD_SR_RXHRSTDET        UCPD_SR_RXHRSTDET             /*!< Rx Hard Reset detect interrupt                 */
+#define LL_UCPD_SR_RXOVR            UCPD_SR_RXOVR                 /*!< Rx data overflow interrupt                     */
+#define LL_UCPD_SR_RXMSGEND         UCPD_SR_RXMSGEND              /*!< Rx message received                            */
+#define LL_UCPD_SR_RXERR            UCPD_SR_RXERR                 /*!< Rx error                                       */
+#define LL_UCPD_SR_TYPECEVT1        UCPD_SR_TYPECEVT1             /*!< Type C voltage level event on CC1              */
+#define LL_UCPD_SR_TYPECEVT2        UCPD_SR_TYPECEVT2             /*!< Type C voltage level event on CC2              */
+#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1      /*!<Status of DC level on CC1 pin                   */
+#define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2      /*!<Status of DC level on CC2 pin                   */
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_UCPD_ReadReg and  LL_UCPD_WriteReg functions
+  * @{
+  */
+#define LL_UCPD_IMR_TXIS             UCPD_IMR_TXISIE              /*!< Enable transmit interrupt status                     */
+#define LL_UCPD_IMR_TXMSGDISC        UCPD_IMR_TXMSGDISCIE         /*!< Enable transmit message discarded interrupt          */
+#define LL_UCPD_IMR_TXMSGSENT        UCPD_IMR_TXMSGSENTIE         /*!< Enable transmit message sent interrupt               */
+#define LL_UCPD_IMR_TXMSGABT         UCPD_IMR_TXMSGABTIE          /*!< Enable transmit message abort interrupt              */
+#define LL_UCPD_IMR_HRSTDISC         UCPD_IMR_HRSTDISCIE          /*!< Enable HRST discarded interrupt                      */
+#define LL_UCPD_IMR_HRSTSENT         UCPD_IMR_HRSTSENTIE          /*!< Enable HRST sent interrupt                           */
+#define LL_UCPD_IMR_TXUND            UCPD_IMR_TXUNDIE             /*!< Enable tx data underrun condition interrupt          */
+#define LL_UCPD_IMR_RXNE             UCPD_IMR_RXNEIE              /*!< Enable Receive data register not empty interrupt     */
+#define LL_UCPD_IMR_RXORDDET         UCPD_IMR_RXORDDETIE          /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
+#define LL_UCPD_IMR_RXHRSTDET        UCPD_IMR_RXHRSTDETIE         /*!< Enable Rx Hard Reset detect interrupt                */
+#define LL_UCPD_IMR_RXOVR            UCPD_IMR_RXOVRIE             /*!< Enable Rx data overflow interrupt                    */
+#define LL_UCPD_IMR_RXMSGEND         UCPD_IMR_RXMSGENDIE          /*!< Enable Rx message received                           */
+#define LL_UCPD_IMR_TYPECEVT1        UCPD_IMR_TYPECEVT1IE         /*!< Enable Type C voltage level event on CC1             */
+#define LL_UCPD_IMR_TYPECEVT2        UCPD_IMR_TYPECEVT2IE         /*!< Enable Type C voltage level event on CC2             */
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
+  * @brief    definition of the usual Ordered sets
+  * @{
+  */
+#define LL_UCPD_SYNC1 0x18u                                       /*!< K-code for Startsynch #1                             */
+#define LL_UCPD_SYNC2 0x11u                                       /*!< K-code for Startsynch #2                             */
+#define LL_UCPD_SYNC3 0x06u                                       /*!< K-code for Startsynch #3                             */
+#define LL_UCPD_RST1  0x07u                                       /*!< K-code for Hard Reset #1                             */
+#define LL_UCPD_RST2  0x19u                                       /*!< K-code for Hard Reset #2                             */
+#define LL_UCPD_EOP   0x0Du                                       /*!< K-code for EOP End of Packet                         */
+
+#define LL_UCPD_ORDERED_SET_SOP         (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding         */
+#define LL_UCPD_ORDERED_SET_SOP1        (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding        */
+#define LL_UCPD_ORDERED_SET_SOP2        (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding       */
+#define LL_UCPD_ORDERED_SET_HARD_RESET  (LL_UCPD_RST1  | (LL_UCPD_RST1<<5u)  | (LL_UCPD_RST1<<10u)  | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding  */
+#define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1  | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u)  | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
+#define LL_UCPD_ORDERED_SET_SOP1_DEBUG  (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u)  | (LL_UCPD_RST2<<10u)  | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding  */
+#define LL_UCPD_ORDERED_SET_SOP2_DEBUG  (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u)  | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_MODE Role Mode
+  * @{
+  */
+#define LL_UCPD_ROLE_SNK             UCPD_CR_ANAMODE              /*!< Mode SNK Rd                                    */
+#define LL_UCPD_ROLE_SRC             0x0U                         /*!< Mode SRC Rp                                    */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_RESISTOR Resistor value
+  * @{
+  */
+#define LL_UCPD_RESISTOR_DEFAULT    UCPD_CR_ANASUBMODE_0          /*!< Rp default                                     */
+#define LL_UCPD_RESISTOR_1_5A       UCPD_CR_ANASUBMODE_1          /*!< Rp 1.5 A                                       */
+#define LL_UCPD_RESISTOR_3_0A       UCPD_CR_ANASUBMODE            /*!< Rp 3.0 A                                       */
+#define LL_UCPD_RESISTOR_NONE       0x0U                          /*!< No resistor                                    */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
+  * @{
+  */
+#define LL_UCPD_ORDERSET_SOP         UCPD_CFG1_RXORDSETEN_0       /*!< SOP Ordered set detection enabled              */
+#define LL_UCPD_ORDERSET_SOP1        UCPD_CFG1_RXORDSETEN_1       /*!< SOP' Ordered set detection enabled             */
+#define LL_UCPD_ORDERSET_SOP2        UCPD_CFG1_RXORDSETEN_2       /*!< SOP'' Ordered set detection enabled            */
+#define LL_UCPD_ORDERSET_HARDRST     UCPD_CFG1_RXORDSETEN_3       /*!< Hard Reset Ordered set detection enabled       */
+#define LL_UCPD_ORDERSET_CABLERST    UCPD_CFG1_RXORDSETEN_4       /*!< Cable Reset Ordered set detection enabled      */
+#define LL_UCPD_ORDERSET_SOP1_DEBUG  UCPD_CFG1_RXORDSETEN_5       /*!< SOP' Debug Ordered set detection enabled       */
+#define LL_UCPD_ORDERSET_SOP2_DEBUG  UCPD_CFG1_RXORDSETEN_6       /*!< SOP'' Debug Ordered set detection enabled      */
+#define LL_UCPD_ORDERSET_SOP_EXT1    UCPD_CFG1_RXORDSETEN_7       /*!< SOP extension#1 Ordered set detection enabled  */
+#define LL_UCPD_ORDERSET_SOP_EXT2    UCPD_CFG1_RXORDSETEN_8       /*!< SOP extension#2 Ordered set detection enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_CCxEVT  CCx event
+  * @{
+  */
+#define LL_UCPD_SNK_CC1_VOPEN      0x00u                                                      /*!< CC1 Sink Open state              */
+#define LL_UCPD_SNK_CC1_VRP        UCPD_SR_TYPEC_VSTATE_CC1_0                                 /*!< CC1 Sink vRP default state       */
+#define LL_UCPD_SNK_CC1_VRP15A     UCPD_SR_TYPEC_VSTATE_CC1_1                                 /*!< CC1 Sink vRP 1.5A state          */
+#define LL_UCPD_SNK_CC1_VRP30A     (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)  /*!< CC1 Sink vRP 3.0A state          */
+
+#define LL_UCPD_SNK_CC2_VOPEN      0x00u                                                      /*!< CC2 Sink Open state              */
+#define LL_UCPD_SNK_CC2_VRP        UCPD_SR_TYPEC_VSTATE_CC2_0                                 /*!< CC2 Sink vRP default state       */
+#define LL_UCPD_SNK_CC2_VRP15A     UCPD_SR_TYPEC_VSTATE_CC2_1                                 /*!< CC2 Sink vRP 1.5A state          */
+#define LL_UCPD_SNK_CC2_VRP30A     (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)  /*!< CC2 Sink vRP 3.0A state          */
+
+#define LL_UCPD_SRC_CC1_VRA        0x0U                                                      /*!< CC1 Source vRA state              */
+#define LL_UCPD_SRC_CC1_VRD        UCPD_SR_TYPEC_VSTATE_CC1_0                                /*!< CC1 Source vRD state              */
+#define LL_UCPD_SRC_CC1_OPEN       UCPD_SR_TYPEC_VSTATE_CC1_1                                /*!< CC1 Source Open state             */
+
+#define LL_UCPD_SRC_CC2_VRA        0x0U                                                      /*!< CC2 Source vRA state              */
+#define LL_UCPD_SRC_CC2_VRD        UCPD_SR_TYPEC_VSTATE_CC2_0                                /*!< CC2 Source vRD state              */
+#define LL_UCPD_SRC_CC2_OPEN       UCPD_SR_TYPEC_VSTATE_CC2_1                                /*!< CC2 Source Open state             */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
+  * @{
+  */
+#define LL_UCPD_PSC_DIV1            0x0u                                                     /*!< Bypass pre-scaling / divide by 1  */
+#define LL_UCPD_PSC_DIV2            UCPD_CFG1_PSC_UCPDCLK_0                                  /*!< Pre-scale clock by dividing by 2  */
+#define LL_UCPD_PSC_DIV4            UCPD_CFG1_PSC_UCPDCLK_1                                  /*!< Pre-scale clock by dividing by 4  */
+#define LL_UCPD_PSC_DIV8            (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)      /*!< Pre-scale clock by dividing by 8  */
+#define LL_UCPD_PSC_DIV16           UCPD_CFG1_PSC_UCPDCLK_2                                  /*!< Pre-scale clock by dividing by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
+  * @{
+  */
+#define LL_UCPD_CCENABLE_NONE       0x0U                                                     /*!< Neither PHY is activated (e.g. disabled state of source)          */
+#define LL_UCPD_CCENABLE_CC1        UCPD_CR_CCENABLE_0                                       /*!< Controls apply to only CC1                                        */
+#define LL_UCPD_CCENABLE_CC2        UCPD_CR_CCENABLE_1                                       /*!< Controls apply to only CC1                                        */
+#define LL_UCPD_CCENABLE_CC1CC2     (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)                /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_CCPIN CC pin selection
+  * @{
+  */
+#define LL_UCPD_CCPIN_CC1           0x0U                    /*!< Use CC1 IO for power delivery communication              */
+#define LL_UCPD_CCPIN_CC2           UCPD_CR_PHYCCSEL        /*!< Use CC2 IO for power delivery communication              */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_RXMODE Receiver mode
+  * @{
+  */
+#define LL_UCPD_RXMODE_NORMAL           0x0U                /*!< Normal receive mode                                      */
+#define LL_UCPD_RXMODE_BIST_TEST_DATA   UCPD_CR_RXMODE      /*!< BIST receive mode (BIST Test Data Mode)                  */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
+  * @{
+  */
+#define LL_UCPD_TXMODE_NORMAL           0x0U                /*!< Initiate the transfer of a Tx message                    */
+#define LL_UCPD_TXMODE_CABLE_RESET      UCPD_CR_TXMODE_0    /*!< Trigger a the transfer of a Cable Reset sequence         */
+#define LL_UCPD_TXMODE_BIST_CARRIER2    UCPD_CR_TXMODE_1    /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2)  */
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
+  * @{
+  */
+#define LL_UCPD_RXORDSET_SOP             0x0U                                                                                 /*!< SOP code detected in receiver              */
+#define LL_UCPD_RXORDSET_SOP1            UCPD_RX_ORDSET_RXORDSET_0                                                            /*!< SOP' code detected in receiver             */
+#define LL_UCPD_RXORDSET_SOP2            UCPD_RX_ORDSET_RXORDSET_1                                                            /*!< SOP'' code detected in receiver            */
+#define LL_UCPD_RXORDSET_SOP1_DEBUG      (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)                              /*!< SOP' Debug code detected in receiver       */
+#define LL_UCPD_RXORDSET_SOP2_DEBUG      UCPD_RX_ORDSET_RXORDSET_2                                                            /*!< SOP'' Debug code detected in receiver      */
+#define LL_UCPD_RXORDSET_CABLE_RESET     (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)                              /*!< Cable Reset code detected in receiver      */
+#define LL_UCPD_RXORDSET_SOPEXT1         (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)                              /*!< SOP extension#1 code detected in receiver  */
+#define LL_UCPD_RXORDSET_SOPEXT2         (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)  /*!< SOP extension#2 code detected in receiver  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
+  * @{
+  */
+
+/** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in UCPD register
+  * @param  __INSTANCE__ UCPD Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in UCPD register
+  * @param  __INSTANCE__ UCPD Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
+  * @{
+  */
+
+/** @defgroup UCPD_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/** @defgroup UCPD_LL_EF_CFG1 CFG1 register
+  * @{
+  */
+/**
+  * @brief  Enable UCPD peripheral
+  * @rmtoll CFG1          UCPDEN           LL_UCPD_Enable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
+}
+
+/**
+  * @brief  Disable UCPD peripheral
+  * @note   When disabling the UCPD, follow the procedure described in the Reference Manual.
+  * @rmtoll CFG1          UCPDEN           LL_UCPD_Disable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
+}
+
+/**
+  * @brief  Check if UCPD peripheral is enabled
+  * @rmtoll CFG1          UCPDEN           LL_UCPD_IsEnabled
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the receiver ordered set detection enable
+  * @rmtoll CFG1          RXORDSETEN          LL_UCPD_SetRxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @param  OrderSet This parameter can be combination of the following values:
+  *         @arg @ref LL_UCPD_ORDERSET_SOP
+  *         @arg @ref LL_UCPD_ORDERSET_SOP1
+  *         @arg @ref LL_UCPD_ORDERSET_SOP2
+  *         @arg @ref LL_UCPD_ORDERSET_HARDRST
+  *         @arg @ref LL_UCPD_ORDERSET_CABLERST
+  *         @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
+  *         @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
+  *         @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
+  *         @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
+{
+  MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
+}
+
+/**
+  * @brief  Set the prescaler for ucpd clock
+  * @rmtoll CFG1          UCPDCLK          LL_UCPD_SetPSCClk
+  * @param  UCPDx UCPD Instance
+  * @param  Psc This parameter can be one of the following values:
+  *         @arg @ref LL_UCPD_PSC_DIV1
+  *         @arg @ref LL_UCPD_PSC_DIV2
+  *         @arg @ref LL_UCPD_PSC_DIV4
+  *         @arg @ref LL_UCPD_PSC_DIV8
+  *         @arg @ref LL_UCPD_PSC_DIV16
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
+{
+  MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
+}
+
+/**
+  * @brief  Set the number of cycles (minus 1) of the half bit clock
+  * @rmtoll CFG1          TRANSWIN          LL_UCPD_SetTransWin
+  * @param  UCPDx UCPD Instance
+  * @param  TransWin a value between Min_Data=0x1 and Max_Data=0x1F
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
+{
+  MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
+}
+
+/**
+  * @brief  Set the clock divider value to generate an interframe gap
+  * @rmtoll CFG1          IFRGAP          LL_UCPD_SetIfrGap
+  * @param  UCPDx UCPD Instance
+  * @param  IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
+{
+  MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
+}
+
+/**
+  * @brief  Set the clock divider value to generate an interframe gap
+  * @rmtoll CFG1          HBITCLKDIV          LL_UCPD_SetHbitClockDiv
+  * @param  UCPDx UCPD Instance
+  * @param  HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
+{
+  MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EF_CFG2 CFG2 register
+  * @{
+  */
+
+/**
+  * @brief  Enable Rx Analog Filter
+  * @rmtoll CFG2          RXAFILTEN          LL_UCPD_RxAnalogFilterEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxAnalogFilterEnable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
+}
+
+/**
+  * @brief  Disable Rx Analog Filter
+  * @rmtoll CFG2          RXAFILTEN          LL_UCPD_RxAnalogFilterDisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxAnalogFilterDisable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
+}
+
+/**
+  * @brief  Enable the wakeup mode
+  * @rmtoll CFG2          WUPEN          LL_UCPD_WakeUpEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
+}
+
+/**
+  * @brief  Disable the wakeup mode
+  * @rmtoll CFG2          WUPEN          LL_UCPD_WakeUpDisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
+}
+
+/**
+  * @brief  Force clock enable
+  * @rmtoll CFG2          FORCECLK          LL_UCPD_ForceClockEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
+}
+
+/**
+  * @brief  Force clock disable
+  * @rmtoll CFG2          FORCECLK          LL_UCPD_ForceClockDisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
+}
+
+/**
+  * @brief  RxFilter enable
+  * @rmtoll CFG2          RXFILTDIS          LL_UCPD_RxFilterEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
+}
+
+/**
+  * @brief  RxFilter disable
+  * @rmtoll CFG2          RXFILTDIS          LL_UCPD_RxFilterDisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EF_CR CR register
+  * @{
+  */
+/**
+  * @brief  Type C detector for CC2 enable
+  * @rmtoll CR          CC2TCDIS          LL_UCPD_TypeCDetectionCC2Enable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
+}
+
+/**
+  * @brief  Type C detector for CC2 disable
+  * @rmtoll CR          CC2TCDIS          LL_UCPD_TypeCDetectionCC2Disable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
+}
+
+/**
+  * @brief  Type C detector for CC1 enable
+  * @rmtoll CR          CC1TCDIS          LL_UCPD_TypeCDetectionCC1Enable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
+}
+
+/**
+  * @brief  Type C detector for CC1 disable
+  * @rmtoll CR          CC1TCDIS          LL_UCPD_TypeCDetectionCC1Disable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
+}
+
+/**
+  * @brief  Source Vconn discharge enable
+  * @rmtoll CR          RDCH          LL_UCPD_VconnDischargeEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
+}
+
+/**
+  * @brief  Source Vconn discharge disable
+  * @rmtoll CR          RDCH          LL_UCPD_VconnDischargeDisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
+}
+
+/**
+  * @brief  Signal Fast Role Swap request
+  * @rmtoll CR          FRSTX          LL_UCPD_VconnDischargeDisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
+}
+
+/**
+  * @brief  Set cc enable
+  * @rmtoll CR          CC1VCONNEN          LL_UCPD_SetccEnable
+  * @param  UCPDx UCPD Instance
+  * @param  CCEnable This parameter can be one of the following values:
+  *         @arg @ref LL_UCPD_CCENABLE_NONE
+  *         @arg @ref LL_UCPD_CCENABLE_CC1
+  *         @arg @ref LL_UCPD_CCENABLE_CC2
+  *         @arg @ref LL_UCPD_CCENABLE_CC1CC2
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
+{
+  MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
+}
+
+/**
+  * @brief  Set UCPD SNK role
+  * @rmtoll CR        ANAMODE          LL_UCPD_SetSNKRole
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
+}
+
+/**
+  * @brief  Set UCPD SRC role
+  * @rmtoll CR        ANAMODE          LL_UCPD_SetSRCRole
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
+}
+
+/**
+  * @brief  Get UCPD Role
+  * @rmtoll CR          ANAMODE          LL_UCPD_GetRole
+  * @param  UCPDx UCPD Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UCPD_ROLE_SNK
+  *         @arg @ref LL_UCPD_ROLE_SRC
+  */
+__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
+{
+  return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
+}
+
+/**
+  * @brief  Set Rp resistor
+  * @rmtoll CR        ANASUBMODE          LL_UCPD_SetRpResistor
+  * @param  UCPDx UCPD Instance
+  * @param  Resistor This parameter can be one of the following values:
+  *         @arg @ref LL_UCPD_RESISTOR_DEFAULT
+  *         @arg @ref LL_UCPD_RESISTOR_1_5A
+  *         @arg @ref LL_UCPD_RESISTOR_3_0A
+  *         @arg @ref LL_UCPD_RESISTOR_NONE
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
+{
+  MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE,  Resistor);
+}
+
+/**
+  * @brief  Set CC pin
+  * @rmtoll CR        PHYCCSEL          LL_UCPD_SetCCPin
+  * @param  UCPDx UCPD Instance
+  * @param  CCPin This parameter can be one of the following values:
+  *         @arg @ref LL_UCPD_CCPIN_CC1
+  *         @arg @ref LL_UCPD_CCPIN_CC2
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
+{
+  MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL,  CCPin);
+}
+
+/**
+  * @brief  Rx enable
+  * @rmtoll CR        PHYRXEN          LL_UCPD_RxEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
+}
+
+/**
+  * @brief  Rx disable
+  * @rmtoll CR        PHYRXEN          LL_UCPD_RxDisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
+}
+
+/**
+  * @brief  Set Rx mode
+  * @rmtoll CR        RXMODE          LL_UCPD_SetRxMode
+  * @param  UCPDx UCPD Instance
+  * @param  RxMode This parameter can be one of the following values:
+  *         @arg @ref LL_UCPD_RXMODE_NORMAL
+  *         @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
+{
+  MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
+}
+
+/**
+  * @brief  Send Hard Reset
+  * @rmtoll CR        TXHRST          LL_UCPD_SendHardReset
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
+}
+
+/**
+  * @brief  Send message
+  * @rmtoll CR        TXSEND          LL_UCPD_SendMessage
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
+}
+
+/**
+  * @brief  Set Tx mode
+  * @rmtoll CR        TXMODE          LL_UCPD_SetTxMode
+  * @param  UCPDx UCPD Instance
+  * @param  TxMode This parameter can be one of the following values:
+  *         @arg @ref LL_UCPD_TXMODE_NORMAL
+  *         @arg @ref LL_UCPD_TXMODE_CABLE_RESET
+  *         @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
+{
+  MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
+  * @{
+  */
+
+/**
+  * @brief  Enable type c event on CC2
+  * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_EnableIT_TypeCEventCC2
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
+}
+
+/**
+  * @brief  Enable type c event on CC1
+  * @rmtoll IMR          TYPECEVT1IE        LL_UCPD_EnableIT_TypeCEventCC1
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
+}
+
+/**
+  * @brief  Enable Rx message end interrupt
+  * @rmtoll IMR          RXMSGENDIE         LL_UCPD_EnableIT_RxMsgEnd
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
+}
+
+/**
+  * @brief  Enable Rx overrun interrupt
+  * @rmtoll IMR          RXOVRIE         LL_UCPD_EnableIT_RxOvr
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
+}
+
+/**
+  * @brief  Enable Rx hard reset interrupt
+  * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_EnableIT_RxHRST
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
+}
+
+/**
+  * @brief  Enable Rx orderset interrupt
+  * @rmtoll IMR          RXORDDETIE         LL_UCPD_EnableIT_RxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
+}
+
+/**
+  * @brief  Enable Rx non empty interrupt
+  * @rmtoll IMR          RXNEIE         LL_UCPD_EnableIT_RxNE
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
+}
+
+/**
+  * @brief  Enable TX underrun interrupt
+  * @rmtoll IMR          TXUNDIE         LL_UCPD_EnableIT_TxUND
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
+}
+
+/**
+  * @brief  Enable hard reset sent interrupt
+  * @rmtoll IMR          HRSTSENTIE         LL_UCPD_EnableIT_TxHRSTSENT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
+}
+
+/**
+  * @brief  Enable hard reset discard interrupt
+  * @rmtoll IMR          HRSTDISCIE         LL_UCPD_EnableIT_TxHRSTDISC
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
+}
+
+/**
+  * @brief  Enable Tx message abort interrupt
+  * @rmtoll IMR          TXMSGABTIE         LL_UCPD_EnableIT_TxMSGABT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
+}
+
+/**
+  * @brief  Enable Tx message sent interrupt
+  * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_EnableIT_TxMSGSENT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
+}
+
+/**
+  * @brief  Enable Tx message discarded interrupt
+  * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_EnableIT_TxMSGDISC
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
+}
+
+/**
+  * @brief  Enable Tx data receive interrupt
+  * @rmtoll IMR          TXISIE         LL_UCPD_EnableIT_TxIS
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
+}
+
+/**
+  * @brief  Disable type c event on CC2
+  * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_DisableIT_TypeCEventCC2
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
+}
+
+/**
+  * @brief  Disable type c event on CC1
+  * @rmtoll IMR          TYPECEVT1IE        LL_UCPD_DisableIT_TypeCEventCC1
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
+}
+
+/**
+  * @brief  Disable Rx message end interrupt
+  * @rmtoll IMR          RXMSGENDIE         LL_UCPD_DisableIT_RxMsgEnd
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
+}
+
+/**
+  * @brief  Disable Rx overrun interrupt
+  * @rmtoll IMR          RXOVRIE         LL_UCPD_DisableIT_RxOvr
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
+}
+
+/**
+  * @brief  Disable Rx hard reset interrupt
+  * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_DisableIT_RxHRST
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
+}
+
+/**
+  * @brief  Disable Rx orderset interrupt
+  * @rmtoll IMR          RXORDDETIE         LL_UCPD_DisableIT_RxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
+}
+
+/**
+  * @brief  Disable Rx non empty interrupt
+  * @rmtoll IMR          RXNEIE         LL_UCPD_DisableIT_RxNE
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
+}
+
+/**
+  * @brief  Disable TX underrun interrupt
+  * @rmtoll IMR          TXUNDIE         LL_UCPD_DisableIT_TxUND
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
+}
+
+/**
+  * @brief  Disable hard reset sent interrupt
+  * @rmtoll IMR          HRSTSENTIE         LL_UCPD_DisableIT_TxHRSTSENT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
+}
+
+/**
+  * @brief  Disable hard reset discard interrupt
+  * @rmtoll IMR          HRSTDISCIE         LL_UCPD_DisableIT_TxHRSTDISC
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
+}
+
+/**
+  * @brief  Disable Tx message abort interrupt
+  * @rmtoll IMR          TXMSGABTIE         LL_UCPD_DisableIT_TxMSGABT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
+}
+
+/**
+  * @brief  Disable Tx message sent interrupt
+  * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_DisableIT_TxMSGSENT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
+}
+
+/**
+  * @brief  Disable Tx message discarded interrupt
+  * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_DisableIT_TxMSGDISC
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
+}
+
+/**
+  * @brief  Disable Tx data receive interrupt
+  * @rmtoll IMR          TXISIE         LL_UCPD_DisableIT_TxIS
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
+}
+
+/**
+  * @brief  Check if type c event on CC2 enabled
+  * @rmtoll IMR          TYPECEVT2IE        LL_UCPD_DisableIT_TypeCEventCC2
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if type c event on CC1 enabled
+  * @rmtoll IMR2          TYPECEVT1IE        LL_UCPD_IsEnableIT_TypeCEventCC1
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx message end interrupt enabled
+  * @rmtoll IMR          RXMSGENDIE         LL_UCPD_IsEnableIT_RxMsgEnd
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx overrun interrupt enabled
+  * @rmtoll IMR          RXOVRIE         LL_UCPD_IsEnableIT_RxOvr
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx hard reset interrupt enabled
+  * @rmtoll IMR          RXHRSTDETIE         LL_UCPD_IsEnableIT_RxHRST
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx orderset interrupt enabled
+  * @rmtoll IMR          RXORDDETIE         LL_UCPD_IsEnableIT_RxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx non empty interrupt enabled
+  * @rmtoll IMR          RXNEIE         LL_UCPD_IsEnableIT_RxNE
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if TX underrun interrupt enabled
+  * @rmtoll IMR          TXUNDIE         LL_UCPD_IsEnableIT_TxUND
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if hard reset sent interrupt enabled
+  * @rmtoll IMR          HRSTSENTIE         LL_UCPD_IsEnableIT_TxHRSTSENT
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if hard reset discard interrupt enabled
+  * @rmtoll IMR          HRSTDISCIE         LL_UCPD_IsEnableIT_TxHRSTDISC
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx message abort interrupt enabled
+  * @rmtoll IMR          TXMSGABTIE         LL_UCPD_IsEnableIT_TxMSGABT
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx message sent interrupt enabled
+  * @rmtoll IMR          TXMSGSENTIE         LL_UCPD_IsEnableIT_TxMSGSENT
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx message discarded interrupt enabled
+  * @rmtoll IMR          TXMSGDISCIE         LL_UCPD_IsEnableIT_TxMSGDISC
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx data receive interrupt enabled
+  * @rmtoll IMR          TXISIE         LL_UCPD_IsEnableIT_TxIS
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
+  * @{
+  */
+
+/**
+  * @brief  Clear type c event on CC2
+  * @rmtoll IIMR          TYPECEVT2IE        LL_UCPD_ClearFlag_TypeCEventCC2
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
+}
+
+/**
+  * @brief  Clear type c event on CC1
+  * @rmtoll IIMR          TYPECEVT1IE        LL_UCPD_ClearFlag_TypeCEventCC1
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
+}
+
+/**
+  * @brief  Clear Rx message end interrupt
+  * @rmtoll ICR          RXMSGENDIE         LL_UCPD_ClearFlag_RxMsgEnd
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
+}
+
+/**
+  * @brief  Clear Rx overrun interrupt
+  * @rmtoll ICR          RXOVRIE         LL_UCPD_ClearFlag_RxOvr
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
+}
+
+/**
+  * @brief  Clear Rx hard reset interrupt
+  * @rmtoll ICR          RXHRSTDETIE         LL_UCPD_ClearFlag_RxHRST
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
+}
+
+/**
+  * @brief  Clear Rx orderset interrupt
+  * @rmtoll ICR          RXORDDETIE         LL_UCPD_ClearFlag_RxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
+}
+
+/**
+  * @brief  Clear TX underrun interrupt
+  * @rmtoll ICR          TXUNDIE         LL_UCPD_ClearFlag_TxUND
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
+}
+
+/**
+  * @brief  Clear hard reset sent interrupt
+  * @rmtoll ICR          HRSTSENTIE         LL_UCPD_ClearFlag_TxHRSTSENT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
+}
+
+/**
+  * @brief  Clear hard reset discard interrupt
+  * @rmtoll ICR          HRSTDISCIE         LL_UCPD_ClearFlag_TxHRSTDISC
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
+}
+
+/**
+  * @brief  Clear Tx message abort interrupt
+  * @rmtoll ICR          TXMSGABTIE         LL_UCPD_ClearFlag_TxMSGABT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
+}
+
+/**
+  * @brief  Clear Tx message sent interrupt
+  * @rmtoll ICR          TXMSGSENTIE         LL_UCPD_ClearFlag_TxMSGSENT
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
+}
+
+/**
+  * @brief  Clear Tx message discarded interrupt
+  * @rmtoll ICR          TXMSGDISCIE         LL_UCPD_ClearFlag_TxMSGDISC
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Check if type c event on CC2
+  * @rmtoll SR          TYPECEVT2        LL_UCPD_IsActiveFlag_TypeCEventCC2
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if type c event on CC1
+  * @rmtoll SR          TYPECEVT1        LL_UCPD_IsActiveFlag_TypeCEventCC1
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx error flag is active
+  * @rmtoll SR          RXERR         LL_UCPD_IsActiveFlag_RxErr
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx message end flag is active
+  * @rmtoll SR          RXMSGEND         LL_UCPD_IsActiveFlag_RxMsgEnd
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx overrun flag is active
+  * @rmtoll SR          RXOVR         LL_UCPD_IsActiveFlag_RxOvr
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx hard reset flag is active
+  * @rmtoll SR          RXHRSTDET         LL_UCPD_IsActiveFlag_RxHRST
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx orderset flag is active
+  * @rmtoll SR          RXORDDET         LL_UCPD_IsActiveFlag_RxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Rx non empty flag is active
+  * @rmtoll SR          RXNE         LL_UCPD_IsActiveFlag_RxNE
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if TX underrun flag is active
+  * @rmtoll SR          TXUND         LL_UCPD_IsActiveFlag_TxUND
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if hard reset sent flag is active
+  * @rmtoll SR          HRSTSENT         LL_UCPD_IsActiveFlag_TxHRSTSENT
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if hard reset discard flag is active
+  * @rmtoll SR          HRSTDISC         LL_UCPD_IsActiveFlag_TxHRSTDISC
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx message abort flag is active
+  * @rmtoll SR          TXMSGABT         LL_UCPD_IsActiveFlag_TxMSGABT
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx message sent flag is active
+  * @rmtoll SR          TXMSGSENT         LL_UCPD_IsActiveFlag_TxMSGSENT
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx message discarded flag is active
+  * @rmtoll SR         TXMSGDISC         LL_UCPD_IsActiveFlag_TxMSGDISC
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Tx data interrupt flag is active
+  * @rmtoll SR          TXIS         LL_UCPD_IsActiveFlag_TxIS
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  return the vstate value for CC2
+  * @rmtoll SR          TXIS         LL_UCPD_GetTypeCVstateCC2
+  * @param  UCPDx UCPD Instance
+  * @retval val
+  */
+__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
+{
+  return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
+}
+
+/**
+  * @brief  return the vstate value for CC1
+  * @rmtoll SR          TXIS         LL_UCPD_GetTypeCVstateCC1
+  * @param  UCPDx UCPD Instance
+  * @retval val
+  */
+__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
+{
+  return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup UCPD_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Rx DMA Enable
+  * @rmtoll CFG1          RXDMAEN          LL_UCPD_RxDMAEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
+}
+
+/**
+  * @brief  Rx DMA Disable
+  * @rmtoll CFG1          RXDMAEN          LL_UCPD_RxDMADisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
+}
+
+/**
+  * @brief  Tx DMA Enable
+  * @rmtoll CFG1          TXDMAEN          LL_UCPD_TxDMAEnable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
+{
+  SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
+}
+
+/**
+  * @brief  Tx DMA Disable
+  * @rmtoll CFG1          TXDMAEN          LL_UCPD_TxDMADisable
+  * @param  UCPDx UCPD Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
+{
+  CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
+}
+
+/**
+  * @brief  Check if DMA Tx is enabled
+  * @rmtoll CR2          TXDMAEN       LL_UCPD_IsEnabledTxDMA
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if DMA Rx is enabled
+  * @rmtoll CR2          RXDMAEN       LL_UCPD_IsEnabledRxDMA
+  * @param  UCPDx UCPD Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
+{
+  return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UCPD_LL_EF_DATA_Management DATA Management
+  * @{
+  */
+
+/**
+  * @brief  write the orderset for Tx message
+  * @rmtoll TX_ORDSET           TXORDSET            LL_UCPD_WriteTxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @param  TxOrderSet one of the following value
+  *         @arg @ref LL_UCPD_ORDERED_SET_SOP
+  *         @arg @ref LL_UCPD_ORDERED_SET_SOP1
+  *         @arg @ref LL_UCPD_ORDERED_SET_SOP2
+  *         @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
+  *         @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
+  *         @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
+  *         @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
+{
+  WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
+}
+
+/**
+  * @brief  write the Tx paysize
+  * @rmtoll TX_PAYSZ          TXPAYSZ            LL_UCPD_WriteTxPaySize
+  * @param  UCPDx UCPD Instance
+  * @param  TxPaySize
+  * @retval None.
+  */
+__STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
+{
+  WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
+}
+
+/**
+  * @brief  Write data
+  * @rmtoll TXDR           DR            LL_UCPD_WriteData
+  * @param  UCPDx UCPD Instance
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None.
+  */
+__STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
+{
+  WRITE_REG(UCPDx->TXDR, Data);
+}
+
+/**
+  * @brief  read RX the orderset
+  * @rmtoll RX_ORDSET           RXORDSET            LL_UCPD_ReadRxOrderSet
+  * @param  UCPDx UCPD Instance
+  * @retval RxOrderSet one of the following value
+  *         @arg @ref LL_UCPD_RXORDSET_SOP
+  *         @arg @ref LL_UCPD_RXORDSET_SOP1
+  *         @arg @ref LL_UCPD_RXORDSET_SOP2
+  *         @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
+  *         @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
+  *         @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
+  *         @arg @ref LL_UCPD_RXORDSET_SOPEXT1
+  *         @arg @ref LL_UCPD_RXORDSET_SOPEXT2
+  */
+__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
+{
+  return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
+}
+
+/**
+  * @brief  Read the Rx paysize
+  * @rmtoll RX_PAYSZ          RXPAYSZ            LL_UCPD_ReadRxPaySize
+  * @param  UCPDx UCPD Instance
+  * @retval RXPaysize.
+  */
+__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
+{
+  return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
+}
+
+/**
+  * @brief  Read data
+  * @rmtoll RXDR           RXDATA            LL_UCPD_ReadData
+  * @param  UCPDx UCPD Instance
+  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
+{
+  return READ_REG(UCPDx->RXDR);
+}
+
+/**
+  * @brief  Set Rx OrderSet Ext1
+  * @rmtoll RX_ORDEXT1           RXSOPX1            LL_UCPD_SetRxOrdExt1
+  * @param  UCPDx UCPD Instance
+  * @param  SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
+{
+  WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
+}
+
+/**
+  * @brief  Set Rx OrderSet Ext2
+  * @rmtoll RX_ORDEXT2           RXSOPX2            LL_UCPD_SetRxOrdExt2
+  * @param  UCPDx UCPD Instance
+  * @param  SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
+{
+  WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct);
+void        LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+#endif /* defined (UCPD1) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_UCPD_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_usart.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_usart.h
new file mode 100644
index 000000000..055a1ec38
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_usart.h
@@ -0,0 +1,4400 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_USART_H
+#define STM32N6xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \
+ || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+  * @{
+  */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+  1UL,
+  2UL,
+  4UL,
+  6UL,
+  8UL,
+  10UL,
+  12UL,
+  16UL,
+  32UL,
+  64UL,
+  128UL,
+  256UL
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
+  * @param  USARTx USART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                          uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  uint32_t brrtemp;
+
+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+  {
+    /* Do not overstep the size of USART_PRESCALER_TAB */
+  }
+  else if (BaudRate == 0U)
+  {
+    /* Can Not divide per 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                              uint32_t OverSampling)
+{
+  uint32_t usartdiv;
+  uint32_t brrresult = 0x0U;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (periphclkpresc * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = periphclkpresc / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+  * @{
+  */
+/**
+  * @brief  Enable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Disable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave Selection depends on NSS input pin
+  *         (The slave is selected when NSS is low and deselected when NSS is high).
+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Disable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the SPI Slave Underrun error flag is set or not
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear TX FIFO Empty Flag
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear SPI Slave Underrun Flag
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_USART_H */
+
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_usb.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_usb.h
new file mode 100644
index 000000000..d74933770
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_usb.h
@@ -0,0 +1,577 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_usb.h
+  * @author  MCD Application Team
+  * @brief   Header file of USB Low Layer HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_USB_H
+#define STM32N6xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal_def.h"
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USB_LL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+#ifndef HAL_USB_TIMEOUT
+#define HAL_USB_TIMEOUT                                       0xF000000U
+#endif /* define HAL_USB_TIMEOUT */
+
+#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
+#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS                           200U
+#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
+
+/**
+  * @brief  USB Mode definition
+  */
+
+typedef enum
+{
+  USB_DEVICE_MODE = 0,
+  USB_HOST_MODE   = 1,
+  USB_DRD_MODE    = 2
+} USB_ModeTypeDef;
+
+/**
+  * @brief  URB States definition
+  */
+typedef enum
+{
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_NYET,
+  URB_ERROR,
+  URB_STALL
+} USB_URBStateTypeDef;
+
+/**
+  * @brief  Host channel States  definition
+  */
+typedef enum
+{
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_ACK,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,
+  HC_BBLERR,
+  HC_DATATGLERR
+} USB_HCStateTypeDef;
+
+
+/**
+  * @brief  USB Instance Initialization Structure definition
+  */
+typedef struct
+{
+  uint8_t dev_endpoints;            /*!< Device Endpoints number.
+                                         This parameter depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint8_t Host_channels;            /*!< Host Channels number.
+                                         This parameter Depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint8_t dma_enable;              /*!< USB DMA state.
+                                         If DMA is not supported this parameter shall be set by default to zero */
+
+  uint8_t speed;                   /*!< USB Core speed.
+                                        This parameter can be any value of @ref PCD_Speed/HCD_Speed
+                                                                                (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+
+  uint8_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
+
+  uint8_t phy_itface;              /*!< Select the used PHY interface.
+                                        This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module  */
+
+  uint8_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
+
+  uint8_t low_power_enable;        /*!< Enable or disable the low Power Mode.                                  */
+
+  uint8_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
+
+  uint8_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
+
+  uint8_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
+
+  uint8_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
+
+  uint8_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
+
+} USB_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;                  /*!< Endpoint number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint8_t   is_in;                /*!< Endpoint direction
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   is_stall;             /*!< Endpoint stall condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   is_iso_incomplete;    /*!< Endpoint isoc condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   type;                 /*!< Endpoint type
+                                       This parameter can be any value of @ref USB_LL_EP_Type                   */
+
+  uint8_t   data_pid_start;       /*!< Initial data PID
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint32_t  maxpacket;            /*!< Endpoint Max packet size
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
+
+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
+
+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
+
+  uint8_t   even_odd_frame;       /*!< IFrame parity
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */
+
+  uint32_t  xfer_size;            /*!< requested transfer size                                                  */
+} USB_EPTypeDef;
+
+typedef struct
+{
+  uint8_t   dev_addr;           /*!< USB device address.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
+
+  uint8_t   ch_num;             /*!< Host channel number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_num;             /*!< Endpoint number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_is_in;           /*!< Endpoint direction
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   speed;              /*!< USB Host Channel speed.
+                                     This parameter can be any value of @ref HCD_Device_Speed:
+                                                                             (HCD_DEVICE_SPEED_xxx)             */
+
+  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */
+  uint8_t   do_ssplit;          /*!< Enable start split transaction in HS mode.                                 */
+  uint8_t   do_csplit;          /*!< Enable complete split transaction in HS mode.                              */
+  uint8_t   ep_ss_schedule;     /*!< Enable periodic endpoint start split schedule .                            */
+  uint32_t  iso_splt_xactPos;   /*!< iso split transfer transaction position.                                   */
+
+  uint8_t   hub_port_nbr;       /*!< USB HUB port number                                                        */
+  uint8_t   hub_addr;           /*!< USB HUB address                                                            */
+
+  uint8_t   ep_type;            /*!< Endpoint Type.
+                                     This parameter can be any value of @ref USB_LL_EP_Type                     */
+
+  uint16_t  max_packet;         /*!< Endpoint Max packet size.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+
+  uint8_t   data_pid;           /*!< Initial data PID.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
+
+  uint32_t  XferSize;           /*!< OTG Channel transfer size.                                                 */
+
+  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
+
+  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */
+
+  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */
+
+  uint32_t  ErrCnt;             /*!< Host channel error count.                                                  */
+  uint32_t  NyetErrCnt;         /*!< Complete Split NYET Host channel error count.                              */
+
+  USB_URBStateTypeDef urb_state;  /*!< URB state.
+                                       This parameter can be any value of @ref USB_URBStateTypeDef              */
+
+  USB_HCStateTypeDef state;       /*!< Host Channel state.
+                                       This parameter can be any value of @ref USB_HCStateTypeDef               */
+} USB_HCTypeDef;
+
+typedef USB_ModeTypeDef     USB_OTG_ModeTypeDef;
+typedef USB_CfgTypeDef      USB_OTG_CfgTypeDef;
+typedef USB_EPTypeDef       USB_OTG_EPTypeDef;
+typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef;
+typedef USB_HCStateTypeDef  USB_OTG_HCStateTypeDef;
+typedef USB_HCTypeDef       USB_OTG_HCTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+  * @{
+  */
+#define USB_OTG_CORE_ID_300A          0x4F54300AU
+#define USB_OTG_CORE_ID_310A          0x4F54310AU
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Mode_ USB Core Mode
+  * @{
+  */
+#define USB_OTG_MODE_DEVICE                    0U
+#define USB_OTG_MODE_HOST                      1U
+#define USB_OTG_MODE_DRD                       2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
+  * @{
+  */
+#define USB_OTG_SPEED_HIGH                     0U
+#define USB_OTG_SPEED_HIGH_IN_FULL             1U
+#define USB_OTG_SPEED_FULL                     3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
+  * @{
+  */
+#define USB_OTG_HS_EMBEDDED_PHY                3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
+  * @{
+  */
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE                     9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE                     5U
+#define USBD_DEFAULT_TRDT_VALUE                9U
+#endif /* USBD_HS_TRDT_VALUE */
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
+  * @{
+  */
+#define USB_OTG_HS_MAX_PACKET_SIZE           512U
+#define USB_OTG_FS_MAX_PACKET_SIZE            64U
+#define USB_OTG_MAX_EP0_SIZE                  64U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
+  * @{
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
+  * @{
+  */
+#define DCFG_FRAME_INTERVAL_80                 0U
+#define DCFG_FRAME_INTERVAL_85                 1U
+#define DCFG_FRAME_INTERVAL_90                 2U
+#define DCFG_FRAME_INTERVAL_95                 3U
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+  * @{
+  */
+#define EP_MPS_64                              0U
+#define EP_MPS_32                              1U
+#define EP_MPS_16                              2U
+#define EP_MPS_8                               3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0U
+#define EP_TYPE_ISOC                           1U
+#define EP_TYPE_BULK                           2U
+#define EP_TYPE_INTR                           3U
+#define EP_TYPE_MSK                            3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
+  * @{
+  */
+#define EP_SPEED_LOW                           0U
+#define EP_SPEED_FULL                          1U
+#define EP_SPEED_HIGH                          2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type
+  * @{
+  */
+#define HC_PID_DATA0                           0U
+#define HC_PID_DATA2                           1U
+#define HC_PID_DATA1                           2U
+#define HC_PID_SETUP                           3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL Device Speed
+  * @{
+  */
+#define USBD_HS_SPEED                          0U
+#define USBD_HSINFS_SPEED                      1U
+#define USBH_HS_SPEED                          0U
+#define USBD_FS_SPEED                          2U
+#define USBH_FSLS_SPEED                        1U
+/**
+  * @}
+  */
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
+  * @{
+  */
+#define STS_GOUT_NAK                           1U
+#define STS_DATA_UPDT                          2U
+#define STS_XFER_COMP                          3U
+#define STS_SETUP_COMP                         4U
+#define STS_SETUP_UPDT                         6U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
+  * @{
+  */
+#define HCFG_30_60_MHZ                         0U
+#define HCFG_48_MHZ                            1U
+#define HCFG_6_MHZ                             2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines
+  * @{
+  */
+#define HFIR_6_MHZ                          6000U
+#define HFIR_60_MHZ                        60000U
+#define HFIR_48_MHZ                        48000U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
+  * @{
+  */
+#define HPRT0_PRTSPD_HIGH_SPEED                0U
+#define HPRT0_PRTSPD_FULL_SPEED                1U
+#define HPRT0_PRTSPD_LOW_SPEED                 2U
+/**
+  * @}
+  */
+
+#define HCCHAR_CTRL                            0U
+#define HCCHAR_ISOC                            1U
+#define HCCHAR_BULK                            2U
+#define HCCHAR_INTR                            3U
+
+#define GRXSTS_PKTSTS_IN                       2U
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3U
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
+#define GRXSTS_PKTSTS_CH_HALTED                7U
+
+#define CLEAR_INTERRUPT_MASK          0xFFFFFFFFU
+
+#define HC_MAX_PKT_CNT                       256U
+#define ISO_SPLT_MPS                         188U
+
+#define HCSPLT_BEGIN                           1U
+#define HCSPLT_MIDDLE                          2U
+#define HCSPLT_END                             3U
+#define HCSPLT_FULL                            4U
+
+#define TEST_J                                 1U
+#define TEST_K                                 2U
+#define TEST_SE0_NAK                           3U
+#define TEST_PACKET                            4U
+#define TEST_FORCE_EN                          5U
+
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+                                                       + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+                                                        + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+                                                        + USB_OTG_HOST_CHANNEL_BASE\
+                                                        + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+
+
+#define EP_ADDR_MSK                            0xFU
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
+  * @{
+  */
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+                                  uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+
+void             *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
+uint32_t          USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
+uint32_t          USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+                              uint8_t epnum, uint8_t dev_address, uint8_t speed,
+                              uint8_t ep_type, uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
+                                   USB_OTG_HCTypeDef *hc, uint8_t dma);
+
+uint32_t          USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32N6xx_LL_USB_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_utils.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_utils.h
new file mode 100644
index 000000000..f33d40a6d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_utils.h
@@ -0,0 +1,372 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_UTILS_H
+#define STM32N6xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+#include "stm32n6xx_ll_system.h"
+#include "stm32n6xx_ll_bus.h"
+#include "stm32n6xx_ll_rcc.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFUL
+
+/**
+  * @brief Unique device ID register base address
+  *        Available from BSEC_OTP_DATA5...BSEC_OTP_DATA7
+  */
+#define UID_BASE_ADDRESS              (BSEC_BASE + 0x14U)
+
+/**
+  * @brief Device RPN register base address
+  *        Available from BSEC_OTP_DATA9
+  */
+#define RPN_BASE_ADDRESS              (BSEC_BASE + 0x24U)
+
+/**
+  * @brief Package data register base address
+  *        Available from BSEC_OTP_DATA122
+  */
+#define PACKAGE_BASE_ADDRESS          (BSEC_BASE + 0x1E8U)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor M for PLL VCO input clock.
+                        This parameter must be a number between Min_Data = 1 and Max_Data = 63
+                        and shall ensure that VCO input is below 50 MHz.
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetM(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor N for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 16 and Max_Data = 640
+                        in integer mode and between Min_Data = 20 and Max_Data = 320 in fractional mode
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetN(). */
+
+  uint32_t PLLP1;   /*!< Division factor level 1 for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 1 and Max_Data = 7
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetP1(). */
+
+  uint32_t PLLP2;   /*!< Division factor level 2 for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 1 and Max_Data = 7
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetP2(). */
+
+  uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
+                        This parameter can be a value between 0 and (2^24)-1
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetFRACN(). */
+
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS IC structure definition
+  */
+typedef struct
+{
+  uint32_t IC1Source;   /*!< The IC1 clock source for sysa_ck(cpu_ck) */
+  uint32_t IC1Divider;  /*!< The IC1 clock divider for sysa_ck(cpu_ck) */
+  uint32_t IC2Source;   /*!< The IC2 clock source for sysb_ck */
+  uint32_t IC2Divider;  /*!< The IC2 clock divider for sysb_ck */
+  uint32_t IC6Source;   /*!< The IC6 clock source for sysc_ck */
+  uint32_t IC6Divider;  /*!< The IC6 clock divider for sysc_ck */
+  uint32_t IC11Source;  /*!< The IC11 clock source for sysd_ck */
+  uint32_t IC11Divider; /*!< The IC11 clock divider for sysd_ck */
+
+} LL_UTILS_ICInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+  uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB4Prescaler(). */
+
+  uint32_t APB5CLKDivider;        /*!< The APB5 clock (PCLK5) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB5_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB5Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0U  /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON         1U  /*!< HSE Bypass is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_DEVICE_RPN DEVICE RPN
+  * @{
+  */
+#define LL_UTILS_DEVICE_STM32N657     0x2000U  /*!< STM32N657 */
+#define LL_UTILS_DEVICE_STM32N647     0x2200U  /*!< STM32N647 */
+#define LL_UTILS_DEVICE_STM32N655     0x6000U  /*!< STM32N655 */
+#define LL_UTILS_DEVICE_STM32N645     0x6200U  /*!< STM32N645 */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#define LL_UTILS_PACKAGETYPE_BGA142   2U  /*!< BGA142 package type */
+#define LL_UTILS_PACKAGETYPE_BGA169   4U  /*!< BGA169 package type */
+#define LL_UTILS_PACKAGETYPE_BGA178   6U  /*!< BGA178 package type */
+#define LL_UTILS_PACKAGETYPE_BGA198   8U  /*!< BGA198 package type */
+#define LL_UTILS_PACKAGETYPE_BGA223  10U  /*!< BGA223 package type */
+#define LL_UTILS_PACKAGETYPE_BGA264  12U  /*!< BGA264 package type */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @note  The application must ensures that SYSCFG clock is enabled.
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((__IO uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @note  The application must ensures that SYSCFG clock is enabled.
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @note  The application must ensures that SYSCFG clock is enabled.
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Package type
+  * @note  The application must ensures that SYSCFG clock is enabled.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA142
+  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA169
+  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA178
+  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA198
+  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA223
+  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA264
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+  return (uint32_t)(READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0FUL);
+}
+
+/**
+  * @brief  Get Device Part Number (RPN)
+  * @note  The application must ensures that SYSCFG clock is enabled.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_DEVICE_STM32N657
+  *         @arg @ref LL_UTILS_DEVICE_STM32N647
+  *         @arg @ref LL_UTILS_DEVICE_STM32N645
+  */
+__STATIC_INLINE uint32_t LL_GetDevicePartNumber(void)
+{
+  return (uint32_t)(READ_REG(*((__IO uint32_t *)RPN_BASE_ADDRESS)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  if (Ticks > 0U)
+  {
+    /* Configure the SysTick to have interrupt in 1ms time base */
+    SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+    SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+  }
+}
+
+void        LL_Init1msTick(uint32_t CPU_Frequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
+                                         const LL_UTILS_ICInitTypeDef  *pUTILS_ICInitStruct,
+                                         const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
+                                         const LL_UTILS_ICInitTypeDef  *pUTILS_ICInitStruct,
+                                         const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
+                                         uint32_t HSEBypass,
+                                         const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
+                                         const LL_UTILS_ICInitTypeDef  *pUTILS_ICInitStruct,
+                                         const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_UTILS_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_venc.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_venc.h
new file mode 100644
index 000000000..333f5a21f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_venc.h
@@ -0,0 +1,138 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_venc.h
+  * @author  GPM Application Team
+  * @brief   Header file of VENC module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_VENC_H
+#define STM32N6xx_LL_VENC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup VENC_LL VENC
+  * @{
+  */
+
+#if defined(VENC)
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup VENC_Exported_Types VENC Exported Types
+  * @{
+
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup VENC_Exported_Constants VENC Exported Constants
+  * @{
+
+  */
+/**
+  * @}
+  */
+
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup VENC_Global_Variables VENC Global Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup VENC_Exported_Macros VENC Exported Macros
+  * @{
+  */
+
+#define LL_VENC_IS_VENCRAM_SYSTEM_ACCESSIBLE() ((SYSCFG->VENCRAMCR & 0b1)!=0)
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+#define VENC_REG(x) (*(__IO uint32_t *) (VENC_BASE + (4UL*(x))))
+/**
+  * @brief  Write a value in VENC register
+  * @param  __REG__ Number of the register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_VENC_WriteRegister(__REG__, __VALUE__) WRITE_REG(VENC_REG(__REG__), (__VALUE__))
+
+/**
+  * @brief  Read a value in VENC register
+  * @param  __REG__ Number of the register to be read
+  * @retval Register value
+  */
+#define LL_VENC_ReadRegister(__REG__) READ_REG(VENC_REG(__REG__))
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup VENC_Exported_Functions VENC Exported Functions
+  * @{
+  */
+
+/** @defgroup VENC_LL_EF_Init Init and De-Init functions
+  * @{
+  */
+void LL_VENC_Init(void);
+void LL_VENC_DeInit(void);
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /*VENC */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32N6xx_LL_VENC_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_wwdg.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_wwdg.h
new file mode 100644
index 000000000..51590d967
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_ll_wwdg.h
@@ -0,0 +1,328 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_wwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of WWDG LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32N6xx_LL_WWDG_H
+#define STM32N6xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
+  * @{
+  */
+#define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
+  * @{
+  */
+#define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define LL_WWDG_PRESCALER_16                WWDG_CFR_WDGTB_2                                          /*!< WWDG counter clock = (PCLK1/4096)/16 */
+#define LL_WWDG_PRESCALER_32                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)                     /*!< WWDG counter clock = (PCLK1/4096)/32 */
+#define LL_WWDG_PRESCALER_64                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/64 */
+#define LL_WWDG_PRESCALER_128               (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)  /*!< WWDG counter clock = (PCLK1/4096)/128 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+  * @{
+  */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in WWDG register
+  * @param  __INSTANCE__ WWDG Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in WWDG register
+  * @param  __INSTANCE__ WWDG Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
+  * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
+  *         then it cannot be disabled again except by a reset.
+  *         This bit is set by software and only cleared by hardware after a reset.
+  *         When WDGA = 1, the watchdog can generate a reset.
+  * @rmtoll CR           WDGA          LL_WWDG_Enable
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+  SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+  * @brief  Checks if Window Watchdog is enabled
+  * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
+{
+  return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
+  * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+  *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+  *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+  *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+  * @rmtoll CR           T             LL_WWDG_SetCounter
+  * @param  WWDGx WWDG Instance
+  * @param  Counter 0..0x7F (7 bit counter value)
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+  MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+  * @brief  Return current Watchdog Counter Value (7 bits counter value)
+  * @rmtoll CR           T             LL_WWDG_GetCounter
+  * @param  WWDGx WWDG Instance
+  * @retval 7 bit Watchdog Counter value
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+  * @brief  Set the time base of the prescaler (WDGTB).
+  * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+  *         is decremented every (4096 x 2expWDGTB) PCLK cycles
+  * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
+  * @param  WWDGx WWDG Instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_WWDG_PRESCALER_1
+  *         @arg @ref LL_WWDG_PRESCALER_2
+  *         @arg @ref LL_WWDG_PRESCALER_4
+  *         @arg @ref LL_WWDG_PRESCALER_8
+  *         @arg @ref LL_WWDG_PRESCALER_16
+  *         @arg @ref LL_WWDG_PRESCALER_32
+  *         @arg @ref LL_WWDG_PRESCALER_64
+  *         @arg @ref LL_WWDG_PRESCALER_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+  * @brief  Return current Watchdog Prescaler Value
+  * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
+  * @param  WWDGx WWDG Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_WWDG_PRESCALER_1
+  *         @arg @ref LL_WWDG_PRESCALER_2
+  *         @arg @ref LL_WWDG_PRESCALER_4
+  *         @arg @ref LL_WWDG_PRESCALER_8
+  *         @arg @ref LL_WWDG_PRESCALER_16
+  *         @arg @ref LL_WWDG_PRESCALER_32
+  *         @arg @ref LL_WWDG_PRESCALER_64
+  *         @arg @ref LL_WWDG_PRESCALER_128
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+  * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+  * @note   This window value defines when write in the WWDG_CR register
+  *         to program Watchdog counter is allowed.
+  *         Watchdog counter value update must occur only when the counter value
+  *         is lower than the Watchdog window register value.
+  *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+  *         (in the control register) is refreshed before the downcounter has reached
+  *         the watchdog window register value.
+  *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
+  *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+  * @rmtoll CFR          W             LL_WWDG_SetWindow
+  * @param  WWDGx WWDG Instance
+  * @param  Window 0x00..0x7F (7 bit Window value)
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+  * @brief  Return current Watchdog Window Value (7 bits value)
+  * @rmtoll CFR          W             LL_WWDG_GetWindow
+  * @param  WWDGx WWDG Instance
+  * @retval 7 bit Watchdog Window value
+  */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
+{
+  return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+/**
+  * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+  * @note   This bit is set by hardware when the counter has reached the value 0x40.
+  *         It must be cleared by software by writing 0.
+  *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+  * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
+{
+  return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+  * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+  * @{
+  */
+/**
+  * @brief  Enable the Early Wakeup Interrupt.
+  * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
+  *         This interrupt is only cleared by hardware after a reset
+  * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+  SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+  * @brief  Check if Early Wakeup Interrupt is enabled
+  * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
+  * @param  WWDGx WWDG Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
+{
+  return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* WWDG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32N6xx_LL_WWDG_H */
diff --git a/stm32cube/stm32n6xx/drivers/include/stm32n6xx_util_i3c.h b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_util_i3c.h
new file mode 100644
index 000000000..fe750b4cf
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/include/stm32n6xx_util_i3c.h
@@ -0,0 +1,137 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_util_i3c.h
+  * @author  MCD Application Team
+  * @brief   Header of stm32n6xx_util_i3c.c
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
+#ifndef STM32N6xx_UTIL_I3C_H
+#define STM32N6xx_UTIL_I3C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#if defined (USE_HAL_DRIVER)
+#include "stm32n6xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#if defined (USE_FULL_LL_DRIVER)
+#include "stm32n6xx_ll_i3c.h"
+#endif /* USE_FULL_LL_DRIVER */
+
+#if (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER)
+/** @addtogroup STM32N6xx_UTIL_Driver
+  * @{
+  */
+
+/** @defgroup UTILITY_I3C I3C Utility
+  * @{
+  */
+/* Exported types ----------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_UTIL_Exported_Types I3C Utility Exported Types
+  * @{
+  */
+
+/** @defgroup I3C_Controller_Timing_Structure_definition I3C Controller Timing Structure definition
+  * @brief    I3C Controller Timing Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t clockSrcFreq; /*!< Specifies the I3C clock source (in Hz).                                                 */
+
+  uint32_t i3cPPFreq;   /*!< Specifies the I3C required bus clock for Push-Pull phase (in Hz).                        */
+
+  uint32_t i2cODFreq;   /*!< Specifies I2C required bus clock for Open-Drain phase (in Hz).                           */
+
+  uint32_t dutyCycle;   /*!< Specifies the I3C duty cycle for Pure I3C bus or I2C duty cycle for Mixed bus in percent
+                             This parameter must be a value less than or equal to 50 percent.                         */
+
+  uint32_t busType;     /*!< Specifies the Bus configuration type.
+                             This parameter must be a value of @ref I3C_UTIL_EC_BUS_TYPE                              */
+} I3C_CtrlTimingTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Target_Timing_Structure_definition I3C Target Timing Structure definition
+  * @brief    I3C Target Timing Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t clockSrcFreq; /*!< Specifies the I3C clock source (in Hz).                                                 */
+} I3C_TgtTimingTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported define ---------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_UTIL_Exported_Define I3C Utility Exported Define
+  * @{
+  */
+
+/** @defgroup I3C_UTIL_EC_BUS_TYPE I3C Utility Bus Type
+  * @brief    Bus type defines which can be used with I3C_CtrlTimingComputation function
+  * @{
+  */
+#define I3C_PURE_I3C_BUS        0U      /*!< Pure I3C bus, no I2C    */
+#define I3C_MIXED_BUS           1U      /*!< Mixed bus I3C and I2C   */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @addtogroup I3C_UTIL_Exported_Functions
+  * @{
+  */
+/** @addtogroup I3C_UTIL_EF_Computation
+  * @{
+  */
+ErrorStatus I3C_CtrlTimingComputation(const I3C_CtrlTimingTypeDef *pInputTiming,
+                                      LL_I3C_CtrlBusConfTypeDef *pOutputConfig);
+ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming,
+                                     LL_I3C_TgtBusConfTypeDef *pOutputConfig);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32N6xx_UTIL_I3C_H */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal.c
new file mode 100644
index 000000000..fbf8e4eef
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal.c
@@ -0,0 +1,2105 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+    [..]
+    All the SYSCFG functions have the same privilege and security attributes.
+         (+) Functions can operate in non-privileged code should
+             privileged and unprivileged data access are granted to the
+             peripheral (see HAL_RIF_RISC_SetSlaveSecureAttributes)
+
+         (+) Functions  can operate in non-secure code should
+             secure and non-secure data access are granted to the peripheral
+             (see HAL_RIF_RISC_SetSlaveSecureAttributes).
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @brief HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HAL_TIMEOUT_SYSCFG_ABORT        5U    /* 5 ms */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+  * @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the NVIC allocation and initial clock configuration.
+          It initializes the systick also when timeout is needed
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the time base source, NVIC and any required global low
+  *         level hardware by calling the HAL_MspInit() callback function to be optionally defined
+  *         in user file stm32n6xx_hal_msp.c.
+  *
+  * @note   HAL_Init() function is called at the beginning of program after reset and before
+  *         the clock configuration.
+  *
+  * @note   In the default implementation the System Timer (Systick) is used as source of time base.
+  *         The Systick configuration is based on HSI clock, as HSI is the clock
+  *         used after a system Reset and the NVIC configuration is set to Priority group 4.
+  *         Once done, time base tick starts incrementing: the tick variable counter is incremented
+  *         each 1ms in the SysTick_Handler() interrupt handler.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Ensure time base clock coherency in SystemCoreClock global variable */
+  SystemCoreClockUpdate();
+
+  /* Initialize 1ms tick time base (default SysTick based on HSI clock after Reset) */
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-initializes all peripherals and low level hardware resources.
+  * @note   This function should only be called from code running in internal RAM
+  *         since it resets the external peripheral memory interfaces.
+  * @note   This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_APB4_FORCE_RESET();
+  __HAL_RCC_APB4_RELEASE_RESET();
+
+  __HAL_RCC_APB5_FORCE_RESET();
+  __HAL_RCC_APB5_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  __HAL_RCC_AHB4_FORCE_RESET();
+  __HAL_RCC_AHB4_RELEASE_RESET();
+
+  __HAL_RCC_AHB5_FORCE_RESET();
+  __HAL_RCC_AHB5_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+  if ((uint32_t)uwTickFreq == 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Group2 HAL Control functions
+  *  @brief    HAL Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in Systick ISR.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @param Freq Tick frequency, value of @ref HAL_TickFreqTypeDef.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval Tick frequency.
+  *         Value of @ref HAL_TickFreqTypeDef.
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay Specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+  return __STM32N6xx_HAL_VERSION;
+}
+
+#if defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief  Returns the device revision identifier
+  * @note Returned Revision ID can be
+  *       0x00000100 for Cut1.0
+  *       0x00000101 for Cut1.1
+  *       0x00000200 for Cut2.0
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+  return *(uint32_t *)(REVID_BASE);
+}
+
+/**
+  * @brief  Returns the device identifier
+  * @note This function can only be used if the HAL BSEC module is enabled in the hal configuration file.
+  *       The BSEC clock must be enabled before calling this function
+  *       Returned Device ID can be
+  *       0x00006200 for STM32N645xx
+  *       0x00006000 for STM32N655xx
+  *       0x00002200 for STM32N647xx
+  *       0x00002000 for STM32N657xx
+  *       0xFFFFFFFF if an error occurs
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+#if defined(HAL_BSEC_MODULE_ENABLED)
+#define BSEC_FUSE_ADDRESS               9U
+  uint32_t data;
+  if(__HAL_RCC_BSEC_IS_CLK_ENABLED() == 0UL){
+    data = 0xFFFFFFFFU;
+  }
+  else
+  {
+    BSEC_HandleTypeDef sBsecHandler = {0};
+    sBsecHandler.Instance = BSEC;
+
+    if(HAL_BSEC_OTP_Read(&sBsecHandler, BSEC_FUSE_ADDRESS, &data) != HAL_OK){
+      data = 0xFFFFFFFFU;
+    }
+  }
+  return data;
+#else
+  return 0xFFFFFFFFU;
+#endif /* HAL_BSEC_MODULE_ENABLED */
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
+  * @note   The application must ensures that SYSCFG clock is enabled.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
+  * @note   The application must ensures that SYSCFG clock is enabled.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
+  * @note   The application must ensures that SYSCFG clock is enabled.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+  *  @brief    HAL Debug functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### HAL Debug functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable/Disable Debug module during Sleep mode
+      (+) Enable/Disable Debug module during Stop modes
+      (+) Enable/Disable Debug module during Stanby mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Debug Module during Sleep mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during Sleep mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during Stop mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during Stop mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during Stanby mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during Stanby mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+  *  @brief    HAL SYSCFG configuration functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable or disable BOOT pins pull-down.
+      (+) Lock and get locks status of system items.
+      (+) Set (and get) TCM size and DTCM size.
+      (+) Lock (and get) write accesses.
+      (+) Enable or disable wait state on extended ITCM and DTCM.
+      (+) Enable or disable external RW margin input for TCM memories.
+      (+) Set and get the TCM biasing level.
+      (+) Enable or disable the external RW for caches memories.
+      (+) Set and get the cache biasing level.
+      (+) Enable or disable the Power-on reset upon SW system request.
+      (+) Enable or disable that Lockup requests a warm reset to the RCC
+      (+) Enable or disable that Lockup generates a NMI on the core
+      (+) Clear Error capture in write posting buffer
+      (+) Reserve VENCRAM for VENC or release it (any use allowed)
+      (+) Enable or disable PKA, SAES, CRYP1/2 and HASH reset in case of potential tamper
+      (+) Set/Get write/read Qos for NP1, NP2 or CPU.
+      (+) Enable or disable SDMMC early-write response.
+      (+) Enable or disable USB early-write response.
+      (+) Enable or disable the NPU NIC, NPU NOC or CPU NOC clock gating.
+      (+) Enable or disable the VDDIOx compensation cell.
+      (+) Configure or get VDDIOx compensation cells.
+      (+) Get VDDIOx compensation ready status.
+      (+) Enable or disable the VDD compensation cell.
+      (+) Configure or get VDD compensation cells.
+      (+) Configure or get the Timer Break input for error flag
+      (+) Set and get secure OS allocation of specific CID to the DMA channel
+      (+) Set and get non-secure OS allocation of specific CID to the DMA channel
+      (+) Enable or disable Retiming on RX path.
+      (+) Enable or disable Retiming on TX path.
+      (+) Set and get Delay on feedback clock.
+      (+) Enable or disable the interleaving on NPU RAM.
+      (+) Get BOOT pin connection status
+      (+) Get the address of first error in P-AHB write-posting buffer
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Pull Down on BOOT pin.
+  * @param  BootId Specifies the boot pins.
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_BOOT_0 boot 0 pin
+  *            @arg SYSCFG_BOOT_1 boot 1 pin
+  * @retval None
+  */
+void HAL_SYSCFG_EnablePullDown(uint32_t BootId)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_ID(BootId));
+
+  SET_BIT(SYSCFG->BOOTCR, BootId);
+}
+
+/**
+  * @brief  Disable the Pull Down on BOOT pin.
+  * @param  BootId Specifies the boot pins.
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_BOOT_0 boot 0 pin
+  *            @arg SYSCFG_BOOT_1 boot 1 pin
+  * @retval None
+  */
+void HAL_SYSCFG_DisablePullDown(uint32_t BootId)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_ID(BootId));
+
+  CLEAR_BIT(SYSCFG->BOOTCR, BootId);
+}
+
+/**
+  * @brief  Lock the SYSCFG item(s).
+  * @note   Lock(s) cleared only at system reset
+  * @param  Item Item(s) to set lock on.
+  *         This parameter can be a combination of @ref SYSCFG_Lock_items
+  * @retval None
+  */
+void HAL_SYSCFG_Lock(uint32_t Item)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_LOCK_ITEMS(Item));
+
+  MODIFY_REG(SYSCFG->CM55CR, SYSCFG_LOCK_ALL, Item);
+}
+
+/**
+  * @brief  Get the lock state of SYSCFG item.
+  * @param  pItem Pointer to return locked items
+  *         the return value can be a combination of @ref SYSCFG_Lock_items
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem)
+{
+  /* Check null pointer */
+  if (pItem == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the non-secure lock state */
+  *pItem = READ_BIT(SYSCFG->CM55CR, SYSCFG_LOCK_ALL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the DTCM and ITCM memory sizes.
+  * @note   Write-once TCM configuration change.
+  * @note   Effective change applied upon new power-on reset by calling
+  *         HAL_SYSCFG_EnablePowerOnReset() and NVIC_SystemReset()
+  * @param  DtcmSize DTCM memory size
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_DTCM_128K 128K
+  *            @arg SYSCFG_DTCM_256K 256K
+  * @param  ItcmSize ITCM memory size
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_ITCM_64K  64K
+  *            @arg SYSCFG_ITCM_128K 128K
+  *            @arg SYSCFG_ITCM_256K 256K
+  * @retval None
+  */
+void HAL_SYSCFG_SetTCMSize(uint32_t DtcmSize, uint32_t ItcmSize)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_DTCM_SIZE(DtcmSize));
+  assert_param(IS_SYSCFG_ITCM_SIZE(ItcmSize));
+
+  MODIFY_REG(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_CFGDTCMSZ | SYSCFG_CM55TCMCR_CFGITCMSZ, DtcmSize | ItcmSize);
+}
+
+/**
+  * @brief  Get the DTCM and ITCM memory sizes.
+  * @param  pDtcmSize Pointer to return DTCM memory size
+  *         This return value can be one of
+  *            @arg SYSCFG_DTCM_128K 128K
+  *            @arg SYSCFG_DTCM_256K 256K
+  * @param  pItcmSize Pointer to return ITCM memory size
+  *         This return value can be one of
+  *            @arg SYSCFG_ITCM_64K  64K
+  *            @arg SYSCFG_ITCM_128K 128K
+  *            @arg SYSCFG_ITCM_256K 256K
+  * @retval HAL status
+   */
+HAL_StatusTypeDef HAL_SYSCFG_GetTCMSize(uint32_t *pDtcmSize, uint32_t *pItcmSize)
+{
+  uint32_t values;
+
+  /* Check null pointer */
+  if ((pDtcmSize == NULL) || (pItcmSize == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  values = READ_REG(SYSCFG->CM55TCMCR);
+  *pDtcmSize = (values & 0xF0U);
+  *pItcmSize = (values & 0xFU);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the SYSCFG write access item(s).
+  * @note   Lock(s) cleared only at system reset
+  * @param  Item Item(s) to set lock on.
+  *         This parameter can be a combination of @ref SYSCFG_WRITE_access
+  * @retval None
+  */
+void HAL_SYSCFG_LockWriteAccess(uint32_t Item)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_LOCK_WRACCESS(Item));
+
+  MODIFY_REG(SYSCFG->CM55TCMCR, SYSCFG_LOCK_WR_ALL, Item);
+}
+
+/**
+  * @brief  Get the lock state of SYSCFG  write access item.
+  * @param  pItem pointer to return locked items
+  *         the return value can be a combination of @ref SYSCFG_WRITE_access
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetLockWriteAccess(uint32_t *pItem)
+{
+  /* Check null pointer */
+  if (pItem == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the non-secure lock state */
+  *pItem = READ_BIT(SYSCFG->CM55TCMCR, SYSCFG_LOCK_WR_ALL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the ITCM Wait State.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableITCMWaiteState(void)
+{
+  SET_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_ITCMWSDISABLE);
+}
+
+/**
+  * @brief  Disable the ITCM Wait State.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableITCMWaiteState(void)
+{
+  CLEAR_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_ITCMWSDISABLE);
+}
+
+/**
+  * @brief  Enable the DTCM Wait State.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableDTCMWaiteState(void)
+{
+  SET_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_DTCMWSDISABLE);
+}
+
+/**
+  * @brief  Disable the DTCM Wait State.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableDTCMWaiteState(void)
+{
+  CLEAR_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_DTCMWSDISABLE);
+}
+
+/**
+  * @brief  Enable external RW margin inputs for TCM memories
+  * @retval None
+  */
+void HAL_SYSCFG_EnableTCMExternalMargin(void)
+{
+  SET_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_TCM);
+}
+
+/**
+  * @brief  Disable external RW margin inputs for TCM memories
+  * @retval None
+  */
+void HAL_SYSCFG_DisableTCMExternalMargin(void)
+{
+  CLEAR_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_TCM);
+}
+
+/**
+  * @brief  Set external RW margin inputs for TCM memories.
+  * @param  TcmRwMarginInput Input Margin.
+  * @retval None
+  */
+void HAL_SYSCFG_SetTCMRWMarginInput(uint32_t TcmRwMarginInput)
+{
+  assert_param(IS_TCM_MARGIN_INPUT(TcmRwMarginInput));
+
+  MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_TCM, (TcmRwMarginInput << 1U));
+}
+
+/**
+  * @brief  Get the External RW margin inputs for TCM memories.
+  * @param  pTcmRwMarginInput pointer to return Input Margin.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetTCMRWMarginInput(uint32_t *pTcmRwMarginInput)
+{
+  /* Check null pointer */
+  if (pTcmRwMarginInput == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the non-secure lock state */
+  *pTcmRwMarginInput = (READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_TCM) >> 1U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TCM biasing level adjust input.
+  * @param  Level Biaising level adjust input
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_TCM_BIAS_VNOM : Biasing level adjust input recommended for Vnom
+  *            @arg SYSCFG_TCM_BIAS_VNOM_10_PERCENT : Biasing level adjust input recommended for Vnom + 10%
+  * @retval None
+  */
+void HAL_SYSCFG_SetTCMBiasingLevel(uint32_t Level)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_TCM_BIASING_LEVEL(Level));
+
+  MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_TCM | SYSCFG_CM55RWMCR_BC1_TCM, Level);
+}
+
+/**
+  * @brief  Get the TCM biasing level adjust input.
+  * @param  pLevel Pointer to return biasing level adjust input.
+  *         The return value can be one of the following values:
+  *            @arg SYSCFG_CACHE_BIAS_VNOM boot 0 pin: Biasing level adjust input recommended for Vnom
+  *            @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10%
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetTCMBiasingLevel(uint32_t *pLevel)
+{
+  /* Check null pointer */
+  if (pLevel == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the non-secure lock state */
+  *pLevel = READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_TCM | SYSCFG_CM55RWMCR_BC1_TCM);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable external RW margin inputs for Cache memories
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCacheExternalMargin(void)
+{
+  SET_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_CACHE);
+}
+
+/**
+  * @brief  Disable external RW margin inputs for Cache memories
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCacheExternalMargin(void)
+{
+  CLEAR_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_CACHE);
+}
+
+/**
+  * @brief  Set External RW margin inputs for Cache memories.
+  * @param  CacheRWMarginInput Input Margin.
+  * @retval None
+  */
+void HAL_SYSCFG_SetCacheRWMarginInput(uint32_t CacheRWMarginInput)
+{
+  assert_param(IS_TCM_MARGIN_INPUT(CacheRWMarginInput));
+
+  MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_CACHE, (CacheRWMarginInput << 8U));
+}
+
+/**
+  * @brief  Get the External RW margin inputs for Cache memories.
+  * @param  pCacheRWMarginInput Pointer to return Input Margin.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetCacheRWMarginInput(uint32_t *pCacheRWMarginInput)
+{
+  /* Check null pointer */
+  if (pCacheRWMarginInput == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the non-secure lock state */
+  *pCacheRWMarginInput = (READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_CACHE) >> 8U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Cache biasing level adjust input.
+  * @param  Level the biaising level adjust input
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_CACHE_BIAS_VNOM: Biasing level adjust input recommended for Vnom
+  *            @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10%
+  * @retval None
+  */
+void HAL_SYSCFG_SetCacheBiasingLevel(uint32_t Level)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_CACHE_BIASING_LEVEL(Level));
+
+  MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_CACHE | SYSCFG_CM55RWMCR_BC1_CACHE, Level);
+}
+
+/**
+  * @brief  Get the Cache biasing level adjust input.
+  * @param  pLevel Pointer to return Cache biasing level adjust input.
+  *         The return value can be onr of the following values:
+  *            @arg SYSCFG_CACHE_BIAS_VNOM boot: Biasing level adjust input recommended for Vnom
+  *            @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10%
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetCacheBiasingLevel(uint32_t *pLevel)
+{
+  /* Check null pointer */
+  if (pLevel == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the cache biaising */
+  *pLevel = READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_CACHE | SYSCFG_CM55RWMCR_BC1_CACHE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the secure vector table (VTOR) address.
+  * @note   Secure vector table address must be set to ensure return from STANDBY state.
+  * @param  Address Secure VTOR address
+  * @retval None
+  */
+void HAL_SYSCFG_SetSVTORAddress(uint32_t Address)
+{
+  /* Check the parameters */
+  assert_param(IS_VTOR_ADDRESS(Address));
+
+  WRITE_REG(SYSCFG->INITSVTORCR, Address);
+}
+
+/**
+  * @brief  Get the secure vector table (VTOR) address.
+  * @param  pAddress  Pointer to return the secure vector table address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetSVTORAddress(uint32_t *pAddress)
+{
+  /* Check null pointer */
+  if (pAddress == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the secure VTOR address */
+  *pAddress = READ_REG(SYSCFG->INITSVTORCR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the non secure vector table (VTOR) address.
+  * @param  Address Non-secure VTOR address
+  * @retval None
+  */
+void HAL_SYSCFG_SetNSVTORAddress(uint32_t Address)
+{
+  /* Check the parameters */
+  assert_param(IS_VTOR_ADDRESS(Address));
+
+  WRITE_REG(SYSCFG->INITNSVTORCR, Address);
+}
+
+/**
+  * @brief  Get the non secure VTOR address.
+  * @param  pAddress  Pointer to return the non-secure vector table address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetNSVTORAddress(uint32_t *pAddress)
+{
+  /* Check null pointer */
+  if (pAddress == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the non-secure VTOR address */
+  *pAddress = READ_REG(SYSCFG->INITNSVTORCR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the Power-on reset.
+  * @note   Select power-on reset to apply on core upon SYSRESETREQ (NVIC_SystemReset())
+  * @retval None
+  */
+void HAL_SYSCFG_EnablePowerOnReset(void)
+{
+  SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_CORE_RESET_TYPE);
+}
+
+/**
+  * @brief  Disable the Power-on reset.
+  * @note   Select warm reset to apply on core upon SYSRESETREQ (NVIC_SystemReset())
+  * @retval None
+  */
+void HAL_SYSCFG_DisablePowerOnReset(void)
+{
+  CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_CORE_RESET_TYPE);
+}
+
+/**
+  * @brief  Enable Lockup requests a warm reset to the RCC.
+  * @note   Select action to perform on a lockup state on the core
+  * @retval None
+  */
+void HAL_SYSCFG_EnableLockupWarmResetonRCC(void)
+{
+  SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_RST_EN);
+}
+
+/**
+  * @brief  Disable Lockup requests a warm reset to the RCC.
+  * @note   Select action to perform on a lockup state on the core
+  * @retval None
+  */
+void HAL_SYSCFG_DisableLockupWarmResetonRCC(void)
+{
+  CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_RST_EN);
+}
+
+/**
+  * @brief  Enable Lockup generates a NMI on the core.
+  * @note   Select action to perform on a lockup state on the core
+  * @retval None
+  */
+void HAL_SYSCFG_EnableLockupGenerateNMI(void)
+{
+  SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_NMI_EN);
+}
+
+/**
+  * @brief  Disable Lockup generates a NMI on the core.
+  * @note   Select action to perform on a lockup state on the core
+  * @retval None
+  */
+void HAL_SYSCFG_DisableLockupGenerateNMI(void)
+{
+  CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_NMI_EN);
+}
+
+/**
+  * @brief   Enable the capture mechanism upon write posting buffer error.
+  * @note    Upon error detection, the erroneous address is logged on and
+  *          the capture mechanism is on hold.
+  *          The address error can be read thanks to
+  *          HAL_SYSCFG_GetAddressWritePostingBuffer.
+  *  @note   This function enables the error capture mechanism again.
+  *  @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_SYSCFG_ReEnableWritePostingErrorCapture(void)
+{
+  /* Re-enable HW write posting detection mechanism */
+  SET_BIT(SYSCFG->CM55PAHBWPR, SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK);
+
+  CLEAR_BIT(SYSCFG->CM55PAHBWPR, SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK);
+
+  return HAL_OK;
+}
+
+#if defined(VENC)
+/**
+  * @brief  Reserve the VENCRAM allocation to VENC.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableVENCRAMReserved(void)
+{
+  CLEAR_BIT(SYSCFG->VENCRAMCR, SYSCFG_VENCRAMCR_VENCRAM_EN);
+}
+
+/**
+  * @brief  Release the VENCRAM allocation to VENC (any use allowed).
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVENCRAMReserved(void)
+{
+  SET_BIT(SYSCFG->VENCRAMCR, SYSCFG_VENCRAMCR_VENCRAM_EN);
+}
+
+#endif /* VENC */
+
+/**
+  * @brief  Enable PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCRYPPotentialTamper(void)
+{
+  CLEAR_BIT(SYSCFG->POTTAMPRSTCR, SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK);
+}
+
+/**
+  * @brief  Disable PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCRYPPotentialTamper(void)
+{
+  SET_BIT(SYSCFG->POTTAMPRSTCR, SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK);
+}
+
+#if defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR)
+/**
+  * @brief  Set write QoS information for master port from NP1 NPUNIC
+  * @param  QosValue Write QoS value (0 to 15).
+  * @retval None
+  */
+void HAL_SYSCFG_SetWriteQosNP1(uint32_t QosValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_QOS_CPU(QosValue));
+
+  MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSW, QosValue << 4U);
+}
+
+/**
+  * @brief  Get write QoS information for master port from NP1 NPUNIC
+  * @param  pQosValue Pointer to return write QOS value (0 to 15)
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP1(uint32_t *pQosValue)
+{
+  /* Check null pointer */
+  if (pQosValue == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the QOS */
+  *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSW) >> 4U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set read QoS information for master port from NP1 NPUNIC
+  * @param  QosValue Read QoS value (0 to 15)
+  * @retval None
+  */
+void HAL_SYSCFG_SetReadQosNP1(uint32_t QosValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_QOS_CPU(QosValue));
+
+  MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSR, QosValue);
+}
+
+/**
+  * @brief  Get read QoS information for master port from NP1 NPUNIC
+  * @param  pQosValue Pointer to return read QOS value (0 to 15)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP1(uint32_t *pQosValue)
+{
+  /* Check null pointer */
+  if (pQosValue == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the QOS */
+  *pQosValue = READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set write QoS information for master port from NP2 NPUNIC
+  * @param  QosValue Write Qos value (0 to 15)
+  * @retval None
+  */
+void HAL_SYSCFG_SetWriteQosNP2(uint32_t QosValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_QOS_CPU(QosValue));
+
+  MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSW, QosValue << 12U);
+}
+
+/**
+  * @brief  Get write QoS information for master port from NP2 NPUNIC
+  * @param  pQosValue Pointer to return write QOS value (0 to 15)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP2(uint32_t *pQosValue)
+{
+  /* Check null pointer */
+  if (pQosValue == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the QOS */
+  *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSW) >> 12U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set read QoS information for master port from NP2 NPUNIC
+  * @param  QosValue Read Qos value (0 to 15)
+  * @retval None
+  */
+void HAL_SYSCFG_SetReadQosNP2(uint32_t QosValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_QOS_CPU(QosValue));
+
+  MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSR, QosValue << 8U);
+}
+
+/**
+  * @brief  Get read QoS information for master port from NP2 NPUNIC
+  * @param  pQosValue Pointer to return read QOS value (0 to 15)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP2(uint32_t *pQosValue)
+{
+  /* Check null pointer */
+  if (pQosValue == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the QOS */
+  *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSR) >> 8U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set write QoS information for master port from CPUSS NPUNIC
+  * @param  QosValue Write QoS value (0 to 15)
+  * @retval None
+  */
+void HAL_SYSCFG_SetWriteQosCPUSS(uint32_t QosValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_QOS_CPU(QosValue));
+
+  MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW, QosValue << 20U);
+}
+
+/**
+  * @brief  Get write QoS information for master port from CPUSS NPUNIC
+  * @param  pQosValue Pointer to return write QOS value (0 to 15)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetwriteQosCPUSS(uint32_t *pQosValue)
+{
+  /* Check null pointer */
+  if (pQosValue == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the QOS */
+  *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW) >> 20U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set read QoS information for master port from CPUSS NPUNIC
+  * @param  QosValue Read QoS value (0 to 15)
+  * @retval None
+  */
+void HAL_SYSCFG_SetReadQosCPUSS(uint32_t QosValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_QOS_CPU(QosValue));
+
+  MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR, QosValue << 16U);
+}
+
+/**
+  * @brief  Get read QoS information for master port from CPUSS NPUNIC
+  * @param  pQosValue Pointer to return read QOS value (0 to 15)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetReadQosCPUSS(uint32_t *pQosValue)
+{
+  /* Check null pointer */
+  if (pQosValue == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the QOS */
+  *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR) >> 16U);
+
+  return HAL_OK;
+}
+#endif /* defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR) */
+
+/**
+  * @brief  Enable SDMMC early-write response.
+  * @param  Sdmmc Selected SDMMC instance(s).
+  *               This parameter can be a one of @ref SYSCFG_SDMMCId
+  * @retval None
+  */
+void HAL_SYSCFG_EnableSDMMCEarlyWRRESP(uint32_t Sdmmc)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_SDMMC(Sdmmc));
+
+  SET_BIT(SYSCFG->ICNEWRCR, Sdmmc);
+}
+
+/**
+  * @brief  Disable SDMMC early-write response.
+  * @param  Sdmmc Selected SDMMC instance(s).
+  *               This parameter can be a one of @ref SYSCFG_SDMMCId
+  * @retval None
+  */
+void HAL_SYSCFG_DisableSDMMCEarlyWRRSP(uint32_t Sdmmc)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_SDMMC(Sdmmc));
+
+  CLEAR_BIT(SYSCFG->ICNEWRCR, Sdmmc);
+}
+
+/**
+  * @brief  Enable USB early-write response.
+  * @param  Usb Selected USB instance(s).
+  *             This parameter can be a one of @ref SYSCFG_USBId
+  * @retval None
+  */
+void HAL_SYSCFG_EnableUSBEarlyEarlyWRRESP(uint32_t Usb)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_USB(Usb));
+
+  SET_BIT(SYSCFG->ICNEWRCR, Usb);
+}
+
+/**
+  * @brief  Disable USB early-write response.
+  * @param  Usb Selected USB instance(s).
+  *             This parameter can be a one of @ref SYSCFG_USBId
+  * @retval None
+  */
+void HAL_SYSCFG_DisableUSBEarlyEarlyWRRESP(uint32_t Usb)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_USB(Usb));
+
+  CLEAR_BIT(SYSCFG->ICNEWRCR, Usb);
+}
+
+/**
+  * @brief  Enable xPU clock gating.
+  * @param  Xpu Selected CPU(s).
+  *             This parameter can be a one of @ref SYSCFG_XPUId
+  * @retval None
+  */
+void HAL_SYSCFG_EnablexPUClockGating(uint32_t Xpu)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_CPU_CLK_GATING(Xpu));
+
+  SET_BIT(SYSCFG->ICNCGCR, Xpu);
+}
+
+/**
+  * @brief  Disable xPU clock gating.
+  * @param  Xpu Selected CPU(s).
+  *             This parameter can be a one of @ref SYSCFG_XPUId
+  * @retval None
+  */
+void HAL_SYSCFG_DisablexPUClockGating(uint32_t Xpu)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_CPU_CLK_GATING(Xpu));
+
+  CLEAR_BIT(SYSCFG->ICNCGCR, Xpu);
+}
+
+/**
+  * @brief  Enable the VDDIO2 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableVDDIO2CompensationCell(void)
+{
+  SET_BIT(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_EN);
+}
+
+/**
+  * @brief  Disable the VDDIO2 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVDDIO2CompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_EN);
+}
+
+/**
+  * @brief  Enable the VDDIO3 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableVDDIO3CompensationCell(void)
+{
+  SET_BIT(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_EN);
+}
+
+/**
+  * @brief  Disable the VDDIO3 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVDDIO3CompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_EN);
+}
+
+/**
+  * @brief  Enable the VDDIO4 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableVDDIO4CompensationCell(void)
+{
+  SET_BIT(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_EN);
+}
+
+/**
+  * @brief  Disable the VDDIO4 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVDDIO4CompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_EN);
+}
+
+/**
+  * @brief  Enable the VDDIO5 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableVDDIO5CompensationCell(void)
+{
+  SET_BIT(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_EN);
+}
+
+/**
+  * @brief  Disable the VDDIO5 compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVDDIO5CompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_EN);
+}
+
+/**
+  * @brief  Configure the code selection for the compensation cell
+  * @param  Selection specifies the concerned compensation cell
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the VDDIO2
+  *            @arg SYSCFG_IO_VDDIO3_CELL Compensation cell for the VDDIO3
+  *            @arg SYSCFG_IO_VDDIO4_CELL Compensation cell for the VDDIO4
+  *            @arg SYSCFG_IO_VDDIO5_CELL Compensation cell for the VDDIO5
+  * @param  Code code selection to be applied for the I/O compensation cell
+  *         This parameter can be one of the following values:
+  *            @arg SYSCFG_IO_CELL_CODE  Code from the cell (available in the SYSCFG_VDDIOxCCSR)
+  *            @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
+  * @param  NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it  provides the Nmos value
+  *                   to apply in range 0 to 15 else this parameter is not used
+  * @param  PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it  provides the Pmos value
+  *                   to apply in range 0 to 15 else this parameter is not used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDIOCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue,
+                                                         uint32_t PmosValue)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
+  assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code));
+
+  if (Code == SYSCFG_IO_REGISTER_CODE)
+  {
+    /* Check the parameters */
+    assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue));
+    assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue));
+
+    /* Reject forbidden Nmos = 0 and Pmos = 15 */
+    if ((NmosValue == 0U) || (PmosValue == 0xFU))
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      switch (Selection)
+      {
+        case SYSCFG_IO_VDDIO2_CELL:
+        {
+          MODIFY_REG(SYSCFG->VDDIO2CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO2CCCR_CS));
+          break;
+        }
+        case SYSCFG_IO_VDDIO3_CELL:
+        {
+          MODIFY_REG(SYSCFG->VDDIO3CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO3CCCR_CS));
+          break;
+        }
+        case SYSCFG_IO_VDDIO4_CELL:
+        {
+          MODIFY_REG(SYSCFG->VDDIO4CCCR, 0x2FFU, ((NmosValue) | (PmosValue << (4U)) | SYSCFG_VDDIO4CCCR_CS));
+          break;
+        }
+        case SYSCFG_IO_VDDIO5_CELL:
+        {
+          MODIFY_REG(SYSCFG->VDDIO5CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO5CCCR_CS));
+          break;
+        }
+        default:
+        {
+          /* Update error status */
+          status = HAL_ERROR;
+          break;
+        }
+      }
+    }
+  }
+  else
+  {
+    switch (Selection)
+    {
+
+      case SYSCFG_IO_VDDIO2_CELL:
+      {
+        MODIFY_REG(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_CS, 0U);
+        break;
+      }
+      case SYSCFG_IO_VDDIO3_CELL:
+      {
+        MODIFY_REG(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_CS, 0U);
+        break;
+      }
+      case SYSCFG_IO_VDDIO4_CELL:
+      {
+        MODIFY_REG(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_CS, 0U);
+        break;
+      }
+      case SYSCFG_IO_VDDIO5_CELL:
+      {
+        MODIFY_REG(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_CS, 0U);
+        break;
+      }
+      default:
+      {
+        /* Update error status */
+        status = HAL_ERROR;
+        break;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Get the code selection for the compensation cell
+  * @param  Selection specifies the concerned compensation cell
+  *         This parameter can one of the following values:
+  *            @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the VDDIO2
+  *            @arg SYSCFG_IO_VDDIO3_CELL Compensation cell for the VDDIO3
+  *            @arg SYSCFG_IO_VDDIO4_CELL Compensation cell for the VDDIO4
+  *            @arg SYSCFG_IO_VDDIO5_CELL Compensation cell for the VDDIO5
+  * @param  pCode pointer to code selection
+  *         This parameter can be one of the following values:
+  *            @arg SYSCFG_IO_CELL_CODE  Code from the cell (available in the SYSCFG_VDDIOxCCSR)
+  *            @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
+  * @param  pNmosValue pointer to the Nmos value in range 0 to 15
+  * @param  pPmosValue pointer to the Pmos value in range 0 to 15
+  * @retval  HAL_OK (all values available) or HAL_ERROR (check parameters)
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetVDDIOCompensationCell(uint32_t Selection, const uint32_t *pCode, uint32_t *pNmosValue,
+                                                      uint32_t *pPmosValue)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t values = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
+  assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(*pCode));
+
+  if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL))
+  {
+    status = HAL_OK;
+
+    if (*pCode == SYSCFG_IO_REGISTER_CODE)
+    {
+      switch (Selection)
+      {
+        case SYSCFG_IO_VDDIO2_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO2CCCR) & 0xFFU;
+          break;
+        }
+        case SYSCFG_IO_VDDIO3_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO3CCCR) & 0xFFU;
+          break;
+        }
+        case SYSCFG_IO_VDDIO4_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO4CCCR) & 0xFFU;
+          break;
+        }
+        case SYSCFG_IO_VDDIO5_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO5CCCR) & 0xFFU;
+          break;
+        }
+        default:
+        {
+          /* Update error status */
+          status = HAL_ERROR;
+          break;
+        }
+      }
+    }
+    else
+    {
+      switch (Selection)
+      {
+        case SYSCFG_IO_VDDIO2_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO2CCSR) & 0xFFU;
+          break;
+        }
+        case SYSCFG_IO_VDDIO3_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO3CCSR) & 0xFFU;
+          break;
+        }
+        case SYSCFG_IO_VDDIO4_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO4CCSR) & 0xFFU;
+          break;
+        }
+        case SYSCFG_IO_VDDIO5_CELL:
+        {
+          values = READ_REG(SYSCFG->VDDIO5CCSR) & 0xFFU;
+          break;
+        }
+        default:
+        {
+          /* Update error status */
+          status = HAL_ERROR;
+          break;
+        }
+      }
+    }
+    *pNmosValue = (values & 0xFU);
+    *pPmosValue = ((values & 0xF0U) >> 4U);
+  }
+  return status;
+}
+
+/**
+  * @brief  Get the compensation cell ready status of VDDIO2.
+  * @retval Ready status (0 (not ready) or !=0 (ready))
+  */
+uint32_t HAL_SYSCFG_GetCompVDDIO2CellReadyStatus(void)
+{
+  return READ_BIT(SYSCFG->VDDIO2CCSR, SYSCFG_VDDIO2CCSR_READY);
+}
+
+/**
+  * @brief  Get the compensation cell ready status of VDDIO3.
+  * @retval Ready status (0 (not ready) or !=0 (ready))
+  */
+uint32_t HAL_SYSCFG_GetCompVDDIO3CellReadyStatus(void)
+{
+  return READ_BIT(SYSCFG->VDDIO3CCSR, SYSCFG_VDDIO3CCSR_READY);
+}
+
+/**
+  * @brief Get the compensation cell ready status of VDDIO4.
+  * @retval Ready status (0 (not ready) or !=0 (ready))
+  */
+uint32_t HAL_SYSCFG_GetCompVDDIO4CellReadyStatus(void)
+{
+  return READ_BIT(SYSCFG->VDDIO4CCSR, SYSCFG_VDDIO4CCSR_READY);
+}
+
+/**
+  * @brief Get the compensation cell ready status of VDDIO5.
+  * @retval Ready status (0 (not ready) or !=0 (ready))
+  */
+uint32_t HAL_SYSCFG_GetCompVDDIO5CellReadyStatus(void)
+{
+  return READ_BIT(SYSCFG->VDDIO5CCSR, SYSCFG_VDDIO5CCSR_READY);
+}
+
+/**
+  * @brief  Configure the code selection for the compensation cell of VDD
+  * @param  Code code selection to be applied for the I/O compensation cell
+  *         This parameter can be one of the following values:
+  *            @arg SYSCFG_IO_CELL_CODE  Code from the cell (available in the SYSCFG_VDDIOxCCSR)
+  *            @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
+  * @param  NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it  provides the Nmos value
+  *                   to apply in range 0 to 15 else this parameter is not used
+  * @param  PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it  provides the Pmos value
+  *                   to apply in range 0 to 15 else this parameter is not used
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDCompensationCell(uint32_t Code, uint32_t NmosValue, uint32_t PmosValue)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code));
+
+  if (Code == SYSCFG_IO_REGISTER_CODE)
+  {
+    /* Check the parameters */
+    assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue));
+    assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue));
+
+    MODIFY_REG(SYSCFG->VDDCCCR, 0xFFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDCCCR_CS));
+
+    status = HAL_OK;
+  }
+  else
+  {
+    MODIFY_REG(SYSCFG->VDDCCCR, 0x200U, 0U);
+    status = HAL_OK;
+  }
+  return status;
+}
+
+/**
+  * @brief  Enable the VDD compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableVDDCompensationCell(void)
+{
+  SET_BIT(SYSCFG->VDDCCCR, SYSCFG_VDDCCCR_EN);
+}
+
+/**
+  * @brief  Disable the VDD compensation cell.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVDDCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->VDDCCCR, SYSCFG_VDDCCCR_EN);
+}
+
+/**
+  * @brief  Get the code selection for the compensation cell of VDD
+  * @param  Code code selection
+  *         This parameter can be one of the following values:
+  *            @arg SYSCFG_IO_CELL_CODE  Code from the cell (available in the SYSCFG_VDDIOxCCSR)
+  *            @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
+  * @param  pNmosValue pointer to the Nmos value in range 0 to 15
+  * @param  pPmosValue pointer to the Pmos value in range 0 to 15
+  * @retval HAL_OK (all values available) or HAL_ERROR (check parameters)
+  */
+HAL_StatusTypeDef HAL_SYSCFG_GetVDDCompensationCell(uint32_t Code, uint32_t *pNmosValue,
+                                                    uint32_t *pPmosValue)
+{
+  uint32_t values;
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code));
+
+  if ((pNmosValue != NULL) && (pPmosValue != NULL))
+  {
+    if (Code == SYSCFG_IO_REGISTER_CODE)
+    {
+      values = READ_REG(SYSCFG->VDDCCCR) & 0xFFU;
+    }
+    else
+    {
+      values = READ_REG(SYSCFG->VDDCCSR) & 0xFFU;
+    }
+
+    *pNmosValue = (values & 0xFU);
+    *pPmosValue = ((values >> 4U) & 0xFU);
+
+    status = HAL_OK;
+  }
+  return status;
+}
+
+/**
+  * @brief  Get the compensation cell ready status of VDD.
+  * @retval Ready status (0 (not ready) or !=0 (ready))
+  */
+uint32_t HAL_SYSCFG_GetCompensationVDDCellReadyStatus(void)
+{
+  return READ_BIT(SYSCFG->VDDCCSR, SYSCFG_VDDCCSR_READY);
+}
+
+/**
+  * @brief  Configure the Timer Break input for error flag(s).
+  * @note   When a configuration is set, only a system reset can reset it.
+  * @param  Input Input configuration
+  *              This parameter can be one or a combination of the following values:
+  *                @arg SYSCFG_CBR_BREAK_LOCK_CORE       Cortex-CM55 lockup
+  *                @arg SYSCFG_CBR_BREAK_LOCK_PVD        PVD lock
+  *                @arg SYSCFG_CBR_BREAK_LOCK_BKPRAM     Backup SRAM ECC error
+  *                @arg SYSCFG_CBR_BREAK_LOCK_CM55_CACHE CM55 cache double ECC error
+  *                @arg SYSCFG_CBR_BREAK_LOCK_CM55_TCM   DTCM double ECC error
+  * @retval None
+  */
+void HAL_SYSCFG_ConfigTimerBreakInput(uint32_t Input)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CBR_BREAK_INPUT(Input));
+
+  MODIFY_REG(SYSCFG->CBR, Input, Input);
+}
+
+/**
+  * @brief  Get the Timer Break input configuration.
+  * @note   When a configuration is set, only a system reset can reset it.
+  * @retval Timer break input configuration
+  *              This return value can be one or a combination of the following values:
+  *                @arg SYSCFG_CBR_BREAK_LOCK_CORE       Cortex-CM55 lockup
+  *                @arg SYSCFG_CBR_BREAK_LOCK_PVD        PVD lock
+  *                @arg SYSCFG_CBR_BREAK_LOCK_BKPRAM     Backup SRAM ECC error
+  *                @arg SYSCFG_CBR_BREAK_LOCK_CM55_CACHE CM55 cache double ECC error
+  *                @arg SYSCFG_CBR_BREAK_LOCK_CM55_TCM   DTCM double ECC error
+  */
+uint32_t HAL_SYSCFG_GetTimerBreakInputConfig(void)
+{
+  return (SYSCFG->CBR & SYSCFG_CBR_BREAK_LOCK_ALL);
+}
+
+/**
+  * @brief  Set the perceived CID of the peripheral.
+  * @note   Set the perceived CID so that all accesses which arrive at the peripheral
+  *         (here HPDMA) appear to carry that CID.
+  *         See Multi-tenancy section of the reference manual for further information.
+  * @param  Cid CID in range 0 to 7
+  * @retval None
+  */
+void HAL_SYSCFG_SetPerceivedCID(uint32_t Cid)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_DMA_CID_SEC(Cid));
+
+  MODIFY_REG(SYSCFG->SEC_AIDCR, SYSCFG_SEC_AIDCR_DMACID_SEC, Cid);
+}
+
+/**
+  * @brief  Get the perceived CID of the peripheral.
+  * @retval CID in range 0 to 7
+  */
+uint32_t HAL_SYSCFG_GetPerceivedCID(void)
+{
+  return (SYSCFG->SEC_AIDCR & SYSCFG_SEC_AIDCR_DMACID_SEC);
+}
+
+/**
+  * @brief  Set the perceived CID of the peripheral as privileged.
+  * @note   Set the perceived CID so that all accesses which arrive at the peripheral
+  *         (here HPDMA) appear to carry that CID.
+  *         This function shall be called in case of DMA channel interrupt (privileged) code
+  *         to read the registers and clear the interrupt of this DMA channel.
+  *         See Multi-tenancy section of the reference manual for forther information.
+  * @param  Cid in range 0 to 7
+  * @retval None
+  */
+void HAL_SYSCFG_SetPerceivedPrivCID(uint32_t Cid)
+{
+  MODIFY_REG(SYSCFG->SECPRIV_AIDCR, SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC, Cid);
+}
+
+/**
+  * @brief   Get the perceived CID of the peripheral as privileged.
+  * @retval  CID in range 0 to 7
+  */
+uint32_t HAL_SYSCFG_GetPerceivedPrivCID(void)
+{
+  return (SYSCFG->SECPRIV_AIDCR & SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC);
+}
+
+/**
+  * @brief  Enable Retiming on RX path.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableReTimingRXpath(void)
+{
+  SET_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_RX);
+}
+
+/**
+  * @brief  Disable Retiming on RX path.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableReTimingRXpath(void)
+{
+  CLEAR_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_RX);
+}
+
+/**
+  * @brief  Enable Retiming on TX path.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableReTimingTXpath(void)
+{
+  SET_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_TX);
+}
+
+/**
+  * @brief  Disable Retiming on TX path.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableReTimingTXpath(void)
+{
+  CLEAR_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_TX);
+}
+
+/**
+  * @brief  Set delay on feedback clock.
+  * @param  Delay Delay on feedback clock
+  *                @arg SYSCFG_DELAY_FEEDBACK_NONE             None
+  *                @arg SYSCFG_DELAY_FEEDBACK_HALF_CYCLE       Half a cycle delay
+  * @retval None
+  */
+void HAL_SYSCFG_SetDelayOnFeedbackClock(uint32_t Delay)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_DMA_DELAY_FEEDBACK_CLOCK(Delay));
+
+  MODIFY_REG(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_SDFBCLK_180, Delay);
+}
+
+/**
+  * @brief  Get delay on feedback clock.
+  * @retval Delay on feedback clock
+  *                @arg SYSCFG_DELAY_FEEDBACK_NONE             None
+  *                @arg SYSCFG_DELAY_FEEDBACK_HALF_CYCLE       Half a cycle delay
+  */
+uint32_t HAL_SYSCFG_GetDelayOnFeedbackClock(void)
+{
+  return (SYSCFG->FMC_RETIMECR & SYSCFG_FMC_RETIMECR_SDFBCLK_180);
+}
+
+#if defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR)
+/**
+  * @brief  Enable the interleaving on NPU RAM.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableInterleavingCpuRam(void)
+{
+  SET_BIT(SYSCFG->NPU_ICNCR, SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE);
+}
+
+/**
+  * @brief  Disable the interleaving on NPU RAM.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableInterleavingCpuRam(void)
+{
+  CLEAR_BIT(SYSCFG->NPU_ICNCR, SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE);
+}
+#endif /* SYSCFG_NPUNICQOSCR_NPU1_ARQOSR */
+
+/**
+  * @brief  Get BOOT pin connection status
+  * @param  BootId specifies the boot pins.
+  * @retval BOOT pin connection configuration
+  *              This return value can be one of the following values:
+  *                @arg SYSCFG_BOOT_CONNECTION_VSS       pin connected to VSS
+  *                @arg SYSCFG_BOOT_CONNECTION_VDD       pin connected to VDD
+  */
+uint32_t HAL_SYSCFG_GetBootPinConnection(uint32_t BootId)
+{
+  uint32_t Connection;
+
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_ID(BootId));
+
+  Connection = READ_BIT(SYSCFG->BOOTSR, BootId);
+
+  if (BootId == SYSCFG_BOOTCR_BOOT0_PD)
+  {
+    return Connection;
+  }
+  else
+  {
+    return (Connection >> 1U);
+  }
+}
+
+/**
+  * @brief  Get address of first error in P-AHB write-posting buffer
+  * @retval Address of the first error in P-AHB write-posting buffer
+  */
+uint32_t HAL_SYSCFG_GetAddressWritePostingBuffer(void)
+{
+  return READ_BIT(SYSCFG->AHBWP_ERROR_SR, SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_adc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_adc.c
new file mode 100644
index 000000000..d5e02f882
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_adc.c
@@ -0,0 +1,3682 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_adc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *          Other functions (extended functions) are available in file
+  *          "stm32n6xx_hal_adc_ex.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### ADC peripheral features #####
+  ==============================================================================
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+  (+) Interrupt generation at the end of regular conversion and in case of
+      analog watchdog or overrun events.
+
+  (+) Single and continuous conversion modes.
+
+  (+) Scan mode for conversion of several channels sequentially.
+
+  (+) Data alignment with in-built data coherency.
+
+  (+) Programmable sampling time (channel wise)
+
+  (+) External trigger (timer or EXTI) with configurable polarity
+
+  (+) DMA request generation for transfer of conversions data of regular group.
+
+  (+) Configurable delay between conversions in Dual interleaved mode.
+
+  (+) ADC channels selectable single/differential input.
+
+  (+) ADC offset shared on 4 offset instances.
+
+  (+) ADC gain compensation
+
+  (+) ADC calibration
+
+  (+) ADC conversion of regular group.
+
+  (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+      Vdda or to an external voltage reference).
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Configuration of top level parameters related to ADC ***
+     ============================================================
+     [..]
+
+    (#) Enable the ADC interface
+        (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+        (++) Two clock settings are mandatory:
+             (+++) ADC clock (core clock, also possibly conversion clock).
+
+             (+++) ADC clock (conversions clock).
+                   Two possible clock sources: synchronous clock derived from AHB clock
+                   or asynchronous clock derived from system clock, PLL2 or PLL3.
+
+             (+++) Example:
+                   Into HAL_ADC_MspInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
+
+               RCC_ADCCLKSOURCE_PLL2 enable:                   (optional: if asynchronous clock selected)
+               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
+               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL2;
+               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+        (++) ADC clock source and clock prescaler are configured at ADC level with
+             parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+    (#) ADC pins configuration
+         (++) Enable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+         (++) Configure these ADC pins in analog mode
+              using function HAL_GPIO_Init()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Configure the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding ADC interruption vector
+              ADCx_IRQHandler().
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+              using function HAL_DMA_Init().
+         (++) Configure the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding DMA interruption vector
+              DMAx_Channelx_IRQHandler().
+
+     *** Configuration of ADC, group regular, channels parameters ***
+     ================================================================
+     [..]
+
+    (#) Configure the ADC parameters (resolution, data alignment, ...)
+        and regular group parameters (conversion trigger, sequencer, ...)
+        using function HAL_ADC_Init().
+
+    (#) Configure the channels for regular group parameters (channel number,
+        channel rank into sequencer, ..., into regular group)
+        using function HAL_ADC_ConfigChannel().
+
+    (#) Optionally, configure the analog watchdog parameters (channels
+        monitored, thresholds, ...)
+        using function HAL_ADC_AnalogWDGConfig().
+
+     *** Execution of ADC conversions ***
+     ====================================
+     [..]
+
+    (#) Optionally, perform an automatic ADC calibration to improve the
+        conversion accuracy
+        using function HAL_ADCEx_Calibration_Start().
+
+    (#) ADC driver can be used among three modes: polling, interruption,
+        transfer by DMA.
+
+        (++) ADC conversion by polling:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start()
+          (+++) Wait for ADC conversion completion
+                using function HAL_ADC_PollForConversion()
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop()
+
+        (++) ADC conversion by interruption:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_IT()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback()
+                (this function must be implemented in user program)
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_IT()
+
+        (++) ADC conversion with transfer by DMA:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_DMA()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+                (these functions must be implemented in user program)
+          (+++) Conversion results are automatically transferred by DMA into
+                destination variable address.
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_DMA()
+
+     [..]
+
+    (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+     *** Deinitialization of ADC ***
+     ============================================================
+     [..]
+
+    (#) Disable the ADC interface
+      (++) ADC clock can be hard reset and disabled at RCC top level.
+        (++) Hard reset of ADC peripherals
+             using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
+        (++) ADC clock disable
+             using the equivalent macro/functions as configuration step.
+             (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC_CLK_DISABLE();                  (if not used anymore)
+               RCC_ADCCLKSOURCE_CLKP restore:                      (optional)
+               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
+               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_CLKP;
+               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+    (#) ADC pins configuration
+         (++) Disable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Disable the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Deinitialize the DMA
+              using function HAL_DMA_Init().
+         (++) Disable the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+    [..]
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_ADC_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     [..]
+
+     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+     or @ref HAL_ADC_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+#define ADC_CFGR1_FIELDS_1                 ((uint32_t)(ADC_CFGR1_RES    |\
+                                                       ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD  |\
+                                                       ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM |\
+                                                       ADC_CFGR1_EXTEN  | ADC_CFGR1_EXTSEL)) /*!< ADC_CFGR1 fields of
+                                           parameters that can be updated when no regular conversion is on-going */
+
+#define ADC_CFGR2_FIELDS                   ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
+                                                       ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
+                                                       ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of
+                                           parameters that can be updated when no conversion (neither regular
+                                           nor injected) is on-going  */
+
+/* Timeout values for ADC operations (enable settling time,                   */
+/*   disable settling time, ...).                                             */
+/*   Values defined to be higher than worst cases: low clock frequency,       */
+/*   maximum prescalers.                                                      */
+#define ADC_ENABLE_TIMEOUT              (2UL)    /*!< ADC enable time-out value  */
+#define ADC_DISABLE_TIMEOUT             (2UL)    /*!< ADC disable time-out value */
+
+/* Timeout to wait for current conversion on going to be completed.           */
+/* Timeout fixed to longest ADC conversion possible, for 1 channel:           */
+/*   - maximum sampling time (640.5 adc_clk)                                  */
+/*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
+/*   - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio)   */
+/*   - ADC oversampling ratio 256                                             */
+/*   Calculation: 653 * 4096 * 256 CPU clock cycles max                       */
+/* Unit: cycles of CPU clock.                                                 */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)  /*!< ADC conversion completion time-out value */
+
+#define ADC_LDO_RDY_TIMEOUT             (1UL) /* Note: Timeout value independent of ADC clock frequency, for more
+                                                       accurate value refer to LL_ADC_DELAY_INTERNAL_REGUL_STAB_US */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    ADC Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC.
+      (+) De-initialize the ADC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the ADC peripheral and regular group according to
+  *         parameters specified in structure "ADC_InitTypeDef".
+  * @note   As prerequisite, ADC clock must be configured at RCC top level
+  *         (refer to description of RCC configuration for ADC
+  *         in header of this file).
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+  *         coming from ADC state reset. Following calls to this function can
+  *         be used to reconfigure some parameters of ADC_InitTypeDef
+  *         structure on the fly, without modifying MSP configuration. If ADC
+  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+  *         before HAL_ADC_Init().
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_InitTypeDef".
+  * @note   This function configures the ADC within 2 scopes: scope of entire
+  *         ADC and scope of regular group. For parameters details, see comments
+  *         of structure "ADC_InitTypeDef".
+  * @note   Parameters related to common ADC registers (ADC clock mode) are set
+  *         only if all ADCs are disabled.
+  *         If this is not the case, these common parameters setting are
+  *         bypassed without error reporting: it can be the intended behaviour in
+  *         case of update of a parameter of ADC_InitTypeDef on the fly,
+  *         without disabling the other ADCs sharing the same ADC common instance.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpCFGR1;
+  uint32_t tmp_adc_reg_is_conversion_on_going;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+  assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
+  assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
+  assert_param(IS_ADC_EXTTRIG(hadc->Instance, hadc->Init.ExternalTrigConv));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+    }
+  }
+
+  /* DISCEN and CONT bits cannot be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+  {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    /* Init the ADC Callback settings */
+    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
+    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
+    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
+    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
+    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
+    hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
+    hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
+    hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
+
+    if (hadc->MspInitCallback == NULL)
+    {
+      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+
+    /* Initialize Lock */
+    hadc->Lock = HAL_UNLOCKED;
+  }
+
+  /* ADC must be disabled to set configuration bits                            */
+  if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
+  if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+  {
+    /* Disable ADC deep power down mode */
+    LL_ADC_DisableDeepPowerDown(hadc->Instance);
+
+    /* System was in deep power down mode, calibration must
+     be relaunched or a previously saved calibration factor
+     re-applied once the ADC voltage regulator is enabled */
+  }
+  /* Configuration of ADC parameters if previous preliminary actions are      */
+  /* correctly completed and if there is no conversion on going on regular    */
+  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+  /* called to update a parameter on the fly).                                */
+  tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+      && (tmp_adc_reg_is_conversion_on_going == 0UL)
+     )
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Configuration of common ADC parameters                                 */
+    /* (None) */
+
+    /* Configuration of ADC instance:                                         */
+    /*  - resolution                               Init.Resolution            */
+    /*  - external trigger to start conversion     Init.ExternalTrigConv      */
+    /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
+    /*  - continuous conversion mode               Init.ContinuousConvMode    */
+    /*  - overrun                                  Init.Overrun               */
+    /*  - discontinuous mode                       Init.DiscontinuousConvMode */
+    /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
+
+    tmpCFGR1 = (ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)         |
+                hadc->Init.Overrun                                                    |
+                hadc->Init.Resolution                                                 |
+                ADC_CFGR1_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      tmpCFGR1 |= ADC_CFGR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+    }
+
+    /* Enable external trigger if trigger selection is different of software  */
+    /* start.                                                                 */
+    /* Note: This configuration keeps the hardware feature of parameter       */
+    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+    /*       software start.                                                  */
+    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+    {
+      tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL)
+                   | hadc->Init.ExternalTrigConvEdge
+                  );
+    }
+
+    /* Update Configuration Register CFGR */
+    MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_FIELDS_1, tmpCFGR1);
+
+    /* Configuration of sampling mode */
+    MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated when ADC is disabled or enabled without */
+    /* conversion on going on regular and injected groups:                    */
+    /*  - Conversion data management      Init.ConversionDataManagement       */
+    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
+    /*  - Oversampling parameters         Init.Oversampling                   */
+    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+       )
+    {
+      tmpCFGR1 = (
+                   ADC_CFGR1_AUTODELAY((uint32_t)hadc->Init.LowPowerAutoWait)        |
+                   ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+
+      MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_FIELDS_2, tmpCFGR1);
+
+      LL_ADC_SetGainCompensation(hadc->Instance, hadc->Init.GainCompensation);
+
+      if (hadc->Init.OversamplingMode == ENABLE)
+      {
+        assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+
+        if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
+            || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+        {
+          /* Multi trigger is not applicable to software-triggered conversions */
+          assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
+        }
+
+        /* Configuration of Oversampler:                                       */
+        /*  - Oversampling Ratio                                               */
+        /*  - Right bit shift                                                  */
+        /*  - Left bit shift                                                   */
+        /*  - Triggered mode                                                   */
+        /*  - Oversampling mode (continued/resumed)                            */
+        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
+                   ADC_CFGR2_ROVSE                       |
+                   ((hadc->Init.Oversampling.Ratio - 1UL)  << ADC_CFGR2_OVSR_Pos) |
+                   hadc->Init.Oversampling.RightBitShift |
+                   hadc->Init.Oversampling.TriggeredMode |
+                   hadc->Init.Oversampling.OversamplingStopReset);
+
+      }
+      else
+      {
+        /* Disable ADC oversampling scope on ADC group regular */
+        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+      }
+
+      /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
+      MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
+    }
+
+    /* Configuration of regular group sequencer:                              */
+    /* - if scan mode is disabled, regular channels sequence length is set to */
+    /*   0x00: 1 channel converted (channel on regular rank 1)                */
+    /*   Parameter "NbrOfConversion" is discarded.                            */
+    /*   Note: Scan mode is not present by hardware on this device, but       */
+    /*   emulated by software for alignment over all STM32 devices.           */
+    /* - if scan mode is enabled, regular channels sequence length is set to  */
+    /*   parameter "NbrOfConversion".                                         */
+
+    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+    {
+      /* Set number of ranks in regular group sequencer */
+      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+    }
+    else
+    {
+      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+    }
+
+    /* Initialize the ADC state */
+    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Deinitialize the ADC peripheral registers to their default reset
+  *         values, with deinitialization of the ADC MSP.
+  * @note   For devices with several ADCs: reset of ADC common registers is done
+  *         only if all ADCs sharing the same common group are disabled.
+  *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+  *         all ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  *         If this is not the case, reset of these common parameters reset is
+  *         bypassed without error reporting: it can be the intended behavior in
+  *         case of reset of a single ADC while the other ADCs sharing the same
+  *         common group is still running.
+  * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+  *         this saves more power by reducing leakage currents
+  *         and is particularly interesting before entering MCU low-power modes.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+  /* Stop potential conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_READY;
+    }
+  }
+
+  /* Enable ADC deep power down mode */
+  LL_ADC_EnableDeepPowerDown(hadc->Instance);
+
+  /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
+  /*       and disable return status. In case of status fail, attempt to      */
+  /*       perform deinitialization anyway and it is up user code in          */
+  /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
+  /*       system RCC hard reset.                                             */
+
+  /* ========== Reset ADC registers ========== */
+  /* Reset register IER */
+  __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
+                              ADC_IT_OVR   |
+                              ADC_IT_JEOS  | ADC_IT_JEOC |
+                              ADC_IT_EOS   | ADC_IT_EOC  |
+                              ADC_IT_EOSMP | ADC_IT_RDY));
+
+  /* Reset register ISR */
+  __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+                              ADC_FLAG_OVR   |
+                              ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
+                              ADC_FLAG_EOS   | ADC_FLAG_EOC  |
+                              ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+  /* Reset register CR */
+  /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+     ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+     no direct reset applicable.
+     Update CR register to reset value where doable by software */
+  CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADCALDIF);
+  SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+  /* Reset register CFGR1 */
+  CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_AWD1CH  | ADC_CFGR1_JAUTO |
+            ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN  | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
+            ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN  | ADC_CFGR1_AUTDLY  |
+            ADC_CFGR1_CONT    | ADC_CFGR1_OVRMOD  |
+            ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL  |
+            ADC_CFGR1_RES     | ADC_CFGR1_DMNGT);
+
+  /* Reset register CFGR2 */
+  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SMPTRIG |
+            ADC_CFGR2_SWTRIG  | ADC_CFGR2_BULB  |
+            ADC_CFGR2_ROVSM   | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
+            ADC_CFGR2_OVSR    | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+  /* Reset register SMPR1 */
+  CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+
+  /* Reset register SMPR2 */
+  CLEAR_BIT(hadc->Instance->SMPR2,
+            ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+            ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+            ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+  /* Reset registers of AWD1 thresholds */
+  CLEAR_BIT(hadc->Instance->AWD1LTR, ADC_AWD1LTR_LTR);
+  SET_BIT(hadc->Instance->AWD1HTR, ADC_AWD1HTR_HTR);
+
+  /* Reset registers of AWD2 thresholds */
+  CLEAR_BIT(hadc->Instance->AWD2LTR, ADC_AWD2LTR_LTR);
+  SET_BIT(hadc->Instance->AWD2HTR, ADC_AWD2HTR_HTR);
+
+  /* Reset registers of AWD3 thresholds */
+  CLEAR_BIT(hadc->Instance->AWD3LTR, ADC_AWD3LTR_LTR);
+  SET_BIT(hadc->Instance->AWD3HTR, ADC_AWD3HTR_HTR);
+
+  /* Reset register SQR1 */
+  CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+            ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+  /* Reset register SQR2 */
+  CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+            ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+  /* Reset register SQR3 */
+  CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+            ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+  /* Reset register SQR4 */
+  CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+  /* Register JSQR was reset when the ADC was disabled */
+
+  /* Reset register DR */
+  /* bits in access mode read only, no direct reset applicable*/
+
+  /* Reset register OFR1 */
+  CLEAR_BIT(hadc->Instance->OFCFGR1, ADC_OFCFGR1_SSAT | ADC_OFCFGR1_OFFSET_CH);
+  CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET);
+  /* Reset register OFR2 */
+  CLEAR_BIT(hadc->Instance->OFCFGR2, ADC_OFCFGR2_SSAT | ADC_OFCFGR2_OFFSET_CH);
+  CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET);
+  /* Reset register OFR3 */
+  CLEAR_BIT(hadc->Instance->OFCFGR3, ADC_OFCFGR3_SSAT | ADC_OFCFGR3_OFFSET_CH);
+  CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET);
+  /* Reset register OFR4 */
+  CLEAR_BIT(hadc->Instance->OFCFGR4, ADC_OFCFGR4_SSAT | ADC_OFCFGR4_OFFSET_CH);
+  CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET);
+
+  /* Reset register GCOMP */
+  CLEAR_BIT(hadc->Instance->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF);
+
+  /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+  /* bits in access mode read only, no direct reset applicable*/
+
+  /* Reset register AWD2CR */
+  CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+  /* Reset register AWD3CR */
+  CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+  /* Reset register DIFSEL */
+  CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+  /* Reset register PCSEL */
+  CLEAR_BIT(hadc->Instance->PCSEL, ADC_PCSEL_PCSEL);
+
+  /* Reset register CALFACT */
+  CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+
+  /* ========== Reset common ADC registers ========== */
+
+  /* Software is allowed to change common parameters only when all the other
+     ADCs are disabled.   */
+  if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+  {
+    /* Reset configuration of ADC common register CCR:
+      - clock mode: CKMODE, PRESCEN
+      - multimode related parameters (when this feature is available): MDMA,
+        DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+      - internal measurement paths: Vbat, temperature sensor, Vref (set into
+        HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+    */
+    ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+  }
+
+  /* ========== Hard reset ADC peripheral ========== */
+  /* Performs a global reset of the entire ADC peripherals instances        */
+  /* sharing the same common ADC instance: ADC state is forced to           */
+  /* a similar state as after device power-on.                              */
+  /* Note: A possible implementation is to add RCC bus reset of ADC         */
+  /* (for example, using macro                                              */
+  /*  __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+  /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)":         */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  if (hadc->MspDeInitCallback == NULL)
+  {
+    hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hadc->MspDeInitCallback(hadc);
+#else
+  /* DeInit the low level hardware */
+  HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+  /* Set ADC error code to none */
+  ADC_CLEAR_ERRORCODE(hadc);
+
+  /* Set ADC state */
+  hadc->State = HAL_ADC_STATE_RESET;
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Initialize the ADC MSP.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the ADC MSP.
+  * @param hadc ADC handle
+  * @note   All ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspDeInit must be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ADC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = pCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = pCallback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a ADC Callback
+  *         ADC callback is redirected to the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+  * @brief    ADC IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular group.
+      (+) Stop conversion of regular group.
+      (+) Poll for conversion complete on regular group.
+      (+) Poll for conversion event.
+      (+) Get result of regular channel conversion.
+      (+) Start conversion of regular group and enable interruptions.
+      (+) Stop conversion of regular group and disable interruptions.
+      (+) Handle ADC interrupt request
+      (+) Start conversion of regular group and enable DMA transfer.
+      (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC, start conversion of regular group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *           if ADC is Slave, ADC is enabled but conversion is not started,
+  *           if ADC is master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Set ADC error code */
+      /* Check if a conversion is on going on ADC group injected */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+      }
+      else
+      {
+        /* Reset all ADC error code fields */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+        if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+        }
+
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, update Slave State in setting
+           HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        if (READ_BIT(tmpADC_Master->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+        }
+
+      }
+#else
+      if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+      {
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+      }
+
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+    }
+    else
+    {
+      __HAL_UNLOCK(hadc);
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in
+  *         case of auto_injection mode), disable ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential
+  *         conversion on injected group. If injected group is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for regular group conversion to be completed.
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function, with an exception:
+  *         if low power feature "LowPowerAutoWait" is enabled, flags are
+  *         not cleared to not interfere with this feature until data register
+  *         is read using function HAL_ADC_GetValue().
+  * @note   This function cannot be used in a particular setup: ADC configured
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still
+  *         be performed on the complete sequence (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+  * @param hadc ADC handle
+  * @param Timeout Timeout value in millisecond.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_Flag_End;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of conversion selected to end of sequence conversions */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_End = ADC_FLAG_EOS;
+  }
+  /* If end of conversion selected to end of unitary conversion */
+  else /* ADC_EOC_SINGLE_CONV */
+  {
+    /* Verification that ADC configuration is compliant with polling for      */
+    /* each conversion:                                                       */
+    /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+    /* several ranks and polling for end of each conversion.                  */
+    /* For code simplicity sake, this particular case is generalized to       */
+    /* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+       )
+    {
+      /* Check ADC DMA mode in independent mode on ADC group regular */
+      if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      }
+      else
+      {
+        tmp_Flag_End = (ADC_FLAG_EOC);
+      }
+    }
+    else
+    {
+      /* Check ADC DMA mode in multimode on ADC group regular */
+      if (LL_ADC_GetMultiDataFormat(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DATA_EACH_ADC)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      }
+      else
+      {
+        tmp_Flag_End = (ADC_FLAG_EOC);
+      }
+    }
+#else
+    /* Check ADC DMA mode */
+    if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      return HAL_ERROR;
+    }
+    else
+    {
+      tmp_Flag_End = (ADC_FLAG_EOC);
+    }
+#endif /* ADC_MULTIMODE_SUPPORT */
+  }
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Wait until End of unitary conversion or sequence conversions flag is raised */
+  while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+      && (hadc->Init.ContinuousConvMode == DISABLE)
+     )
+  {
+    /* Check whether end of sequence is reached */
+    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+      if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+  }
+
+  /* Get relevant register CFGR in ADC instance of ADC master or slave        */
+  /* in function of multimode state (for devices with multimode               */
+  /* available).                                                              */
+#if defined(ADC_MULTIMODE_SUPPORT)
+  if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+      || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+     )
+  {
+    /* Retrieve ADC CFGR1 register */
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+  }
+  else
+  {
+    /* Retrieve Master ADC CFGR register */
+    tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+  }
+#else
+  /* Retrieve ADC CFGR1 register */
+  tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Clear polled flag */
+  if (tmp_Flag_End == ADC_FLAG_EOS)
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+  }
+  else
+  {
+    /* Clear end of conversion EOC flag of regular group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
+    /* until data register is read using function HAL_ADC_GetValue().         */
+    if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for ADC event.
+  * @param hadc ADC handle
+  * @param EventType the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
+  *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on
+  *                                       all STM32 series)
+  *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on
+  *                                       all STM32 series)
+  *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on
+  *                                       all STM32 series)
+  *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
+  * @param Timeout Timeout value in millisecond.
+  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
+  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+  *         by a new converted data as soon as OVR is cleared.
+  *         To reset OVR flag once the preserved data is retrieved, the user can resort
+  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Check selected event flag */
+  while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  switch (EventType)
+  {
+    /* End Of Sampling event */
+    case ADC_EOSMP_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+      /* Clear the End Of Sampling flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+      break;
+
+    /* Analog watchdog (level out of window) event */
+    /* Note: In case of several analog watchdog enabled, if needed to know      */
+    /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+    /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
+    /* For example:                                                             */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
+
+    /* Check analog watchdog 1 flag */
+    case ADC_AWD_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+      break;
+
+    /* Check analog watchdog 2 flag */
+    case ADC_AWD2_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+      break;
+
+    /* Check analog watchdog 3 flag */
+    case ADC_AWD3_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+      break;
+
+    /* Overrun event */
+    default: /* Case ADC_OVR_EVENT */
+      /* If overrun is set to overwrite previous data, overrun event is not     */
+      /* considered as an error.                                                */
+      /* (cf ref manual "Managing conversions without using the DMA and without */
+      /* overrun ")                                                             */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        /* Set ADC state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+        /* Set ADC error code to overrun */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+      }
+      else
+      {
+        /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+           otherwise, data register is potentially overwritten by new converted data as soon
+           as OVR is cleared. */
+        __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+      }
+      break;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : EOC (end of conversion), EOS (end of sequence),
+  *         OVR overrun.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+  *         ADC Master.
+  *         For ADC Slave, ADC is enabled only (conversion is not started).
+  *         For ADC Master, ADC is enabled and multimode conversion is started.
+  * @note   To guarantee a proper reset of all interruptions once all the needed
+  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+  *         a correct stop of the IT-based conversions.
+  * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+  *         interruption. If required (e.g. in case of oversampling with trigger
+  *         mode), the user must:
+  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+  *          before calling HAL_ADC_Start_IT().
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Set ADC error code */
+      /* Check if a conversion is on going on ADC group injected */
+      if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+      }
+      else
+      {
+        /* Reset all ADC error code fields */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Disable all interruptions before enabling the desired ones */
+      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+      /* Enable ADC end of conversion interrupt */
+      switch (hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+          break;
+      }
+
+      /* Enable ADC overrun interrupt */
+      /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+         ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+         behavior and no CPU time is lost for a non-processed interruption */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+      }
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+        if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+          /* Enable as well injected interruptions in case
+           HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+           allows to start regular and injected conversions when JAUTO is
+           set with a single call to HAL_ADC_Start_IT() */
+          switch (hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+              break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+              break;
+          }
+        }
+
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, Slave injected interruptions
+           are enabled nevertheless (for same reason as above) */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        if (READ_BIT(tmpADC_Master->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+        {
+          /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
+             and in resetting HAL_ADC_STATE_INJ_EOC bit */
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+          /* Next, set Slave injected interruptions */
+          switch (hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+              break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+              break;
+          }
+        }
+      }
+#else
+      /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+      if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
+      {
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+        /* Enable as well injected interruptions in case
+         HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+         allows to start regular and injected conversions when JAUTO is
+         set with a single call to HAL_ADC_Start_IT() */
+        switch (hadc->Init.EOCSelection)
+        {
+          case ADC_EOC_SEQ_CONV:
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+            __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+            break;
+          /* case ADC_EOC_SINGLE_CONV */
+          default:
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+            __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+            break;
+        }
+      }
+
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+    }
+    else
+    {
+      __HAL_UNLOCK(hadc);
+    }
+
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable interrution of
+  *         end-of-conversion, disable ADC peripheral.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for regular group */
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
+  * @note   Interruptions enabled in this function:
+  *         overrun (if applicable), DMA half transfer, DMA transfer complete.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
+  *         is designed for single-ADC mode only. For multimode, the dedicated
+  *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
+  * @param hadc ADC handle
+  * @param pData Destination Buffer address.
+  * @param Length Number of data to be transferred from ADC peripheral to memory
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+  uint32_t LengthInBytes;
+  DMA_NodeConfTypeDef node_conf;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+    /* Ensure that multimode regular conversions are not enabled.   */
+    /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
+    if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+       )
+#endif /* ADC_MULTIMODE_SUPPORT */
+    {
+      /* Enable the ADC peripheral */
+      tmp_hal_status = ADC_Enable(hadc);
+
+      /* Start conversion if ADC is effectively enabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state                                                        */
+        /* - Clear state bitfield related to regular group conversion results   */
+        /* - Set state bitfield related to regular operation                    */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                          HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+        /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+          - if ADC instance is master or if multimode feature is not available
+          - if multimode setting is disabled (ADC instance slave in independent mode) */
+        if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+            || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+           )
+        {
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+        /* Check if a conversion is on going on ADC group injected */
+        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+        {
+          /* Reset ADC error code fields related to regular conversions only */
+          CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+        }
+        else
+        {
+          /* Reset all ADC error code fields */
+          ADC_CLEAR_ERRORCODE(hadc);
+        }
+
+        /* Set the DMA transfer complete callback */
+        hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+        /* Set the DMA half transfer complete callback */
+        hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+        /* Set the DMA error callback */
+        hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+        /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
+        /* ADC start (in case of SW start):                                   */
+
+        /* Clear regular group conversion flag and overrun flag               */
+        /* (To ensure of no unknown state from potential previous ADC         */
+        /* operations)                                                        */
+        __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+        /* Unlock before starting ADC conversions: in case of potential         */
+        /* interruption, to let the process to ADC IRQ Handler.                 */
+        __HAL_UNLOCK(hadc);
+
+        /* With DMA, overrun event is always considered as an error even if
+           hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+           ADC_IT_OVR is enabled. */
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+        /* Start the DMA channel */
+        /* Check linkedlist mode */
+        if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
+          {
+            /* Length should be converted to number of bytes */
+            if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
+            {
+              return HAL_ERROR;
+            }
+
+            /* Length should be converted to number of bytes */
+            if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+            {
+              /* Word -> Bytes */
+              LengthInBytes = Length * 4U;
+            }
+            else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+            {
+              /* Halfword -> Bytes */
+              LengthInBytes = Length * 2U;
+            }
+            else /* Bytes */
+            {
+              /* Same size already expressed in Bytes */
+              LengthInBytes = Length;
+            }
+
+            hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
+            hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =                  \
+                (uint32_t)&hadc->Instance->DR;
+            hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+            tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
+          }
+          else
+          {
+            tmp_hal_status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /* Length should be converted to number of bytes */
+          if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+          {
+            /* Word -> Bytes */
+            LengthInBytes = Length * 4U;
+          }
+          else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+          {
+            /* Halfword -> Bytes */
+            LengthInBytes = Length * 2U;
+          }
+          else /* Bytes */
+          {
+            /* Same size already expressed in Bytes */
+            LengthInBytes = Length;
+          }
+
+          /* Start the DMA channel */
+          tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData,        \
+                                            LengthInBytes);
+        }
+
+        if (tmp_hal_status != HAL_ERROR)
+        {
+          /* Enable conversion of regular group.                                  */
+          /* If software start has been selected, conversion starts immediately.  */
+          /* If external trigger has been selected, conversion will start at next */
+          /* trigger event.                                                       */
+          /* Start ADC group regular conversion */
+          LL_ADC_REG_StartConversion(hadc->Instance);
+        }
+      }
+      else
+      {
+        __HAL_UNLOCK(hadc);
+      }
+    }
+#if defined(ADC_MULTIMODE_SUPPORT)
+    else
+    {
+      tmp_hal_status = HAL_ERROR;
+      __HAL_UNLOCK(hadc);
+    }
+#endif /* ADC_MULTIMODE_SUPPORT */
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
+  *         ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential
+  *         conversion on ADC group injected. If ADC group injected is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+  *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential ADC group regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+    MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+    {
+      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+      /* Check if DMA channel effectively disabled */
+      if (tmp_hal_status != HAL_OK)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+      }
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+    /* to keep in memory a potential failing status.                          */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+    }
+    else
+    {
+      (void)ADC_Disable(hadc);
+    }
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function returns an unsigned value. Using the ADC offset
+  *         feature can result in negative conversion data.
+  *         To read conversion data with ADC offset enabled
+  *         use function @ref HAL_ADC_GetSignedValue.
+  * @note   This function does not clear ADC flag EOS
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param hadc ADC handle
+  * @retval ADC group regular conversion data
+  */
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+
+  /* Return ADC converted value */
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function does not clear ADC flag EOS
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param hadc ADC handle
+  * @retval ADC group regular conversion data
+  */
+int32_t HAL_ADC_GetSignedValue(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+
+  /* Return ADC converted value */
+  return (int32_t)(hadc->Instance->DR);
+}
+
+/**
+  * @brief  Start ADC conversion sampling phase of regular group
+  * @note:  This function should only be called to start sampling when
+  *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+  *         mode has been selected
+  *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Start sampling */
+  SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop ADC conversion sampling phase of regular group and start conversion
+  * @note:  This function should only be called to stop sampling when
+  *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+  *         mode has been selected
+  *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+  *         - after sampling has been started using @ref HAL_ADC_StartSampling.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Start sampling */
+  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle ADC interrupt request.
+  * @param hadc ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+  uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+  uint32_t tmp_isr = hadc->Instance->ISR;
+  uint32_t tmp_ier = hadc->Instance->IER;
+  uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+  uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+  /* ========== Check End of Sampling flag for ADC group regular ========== */
+  if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+  {
+    /* Update state machine on end of sampling status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+    }
+
+    /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->EndOfSamplingCallback(hadc);
+#else
+    HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+  }
+
+  /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+  if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+      (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+  {
+    /* Update state machine on conversion status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    }
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+    {
+      /* Get relevant register CFGR in ADC instance of ADC master or slave    */
+      /* in function of multimode state (for devices with multimode           */
+      /* available).                                                          */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* check CONT bit directly in handle ADC CFGR register */
+        tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+      }
+      else
+      {
+        /* else need to check Master ADC CONT bit */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+      }
+#else
+      tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Carry on if continuous mode is disabled */
+      if (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) != ADC_CFGR1_CONT)
+      {
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+        {
+          /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit         */
+          /* ADSTART==0 (no conversion on going)                              */
+          if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+          {
+            /* Disable ADC end of sequence conversion interrupt */
+            /* Note: Overrun interrupt was enabled with EOC interrupt in      */
+            /* HAL_Start_IT(), but is not disabled here because can be used   */
+            /* by overrun IRQ process below.                                  */
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+            /* Set ADC state */
+            CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+            if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+            {
+              SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+            }
+          }
+          else
+          {
+            /* Change ADC state to error state */
+            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+            /* Set ADC error code to ADC peripheral internal error */
+            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+          }
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+    /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
+    /*       to determine if conversion has been triggered from EOC or EOS,   */
+    /*       possibility to use:                                              */
+    /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
+    /*       conversion flags clear induces the release of the preserved data.*/
+    /*       Therefore, if the preserved data value is needed, it must be     */
+    /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+  }
+
+  /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
+  if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+      (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+  {
+    /* Update state machine on conversion status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+    }
+
+    /* Retrieve ADC configuration */
+    tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+    tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+    /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+    /* in function of multimode state (for devices with multimode         */
+    /* available).                                                        */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+        || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+       )
+    {
+      tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+    }
+    else
+    {
+      tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+      tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+    }
+#else
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+    /* Disable interruption if no further conversion upcoming by injected     */
+    /* external trigger or by automatic injected conversion with regular      */
+    /* group having no further conversion upcoming (same conditions as        */
+    /* regular group interruption disabling above),                           */
+    /* and if injected scan sequence is completed.                            */
+    if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
+    {
+      if (((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) ||
+           ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
+            (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL))))
+      {
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+        {
+          if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+          {
+            /* Disable ADC end of sequence conversion interrupt  */
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+            /* Set ADC state */
+            CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+            if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+            {
+              SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+            }
+          }
+        }
+      }
+    }
+
+    /* Injected Conversion complete callback */
+    /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+              interruption has been triggered by end of conversion or end of
+              sequence.    */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->InjectedConvCpltCallback(hadc);
+#else
+    HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear injected group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+  }
+
+  /* ========== Check Analog watchdog 1 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+    /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindowCallback(hadc);
+#else
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+  }
+
+  /* ========== Check analog watchdog 2 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+    /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow2Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+  }
+
+  /* ========== Check analog watchdog 3 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+    /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow3Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+  }
+
+  /* ========== Check Overrun flag ========== */
+  if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+  {
+    /* If overrun is set to overwrite previous data (default setting),        */
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      overrun_error = 1UL;
+    }
+    else
+    {
+      /* Check DMA configuration */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
+      {
+        overrun_error = 1UL;
+
+        /* Multimode (when feature is available) is enabled,
+           Common Control Register MDMA bits must be checked. */
+        if (LL_ADC_GetMultiDataFormat(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DATA_EACH_ADC)
+        {
+          overrun_error = 1UL;
+        }
+      }
+      else
+#endif /* ADC_MULTIMODE_SUPPORT */
+      {
+        /* Multimode not set or feature not available or ADC independent */
+        if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMNGT) != 0UL)
+        {
+          overrun_error = 1UL;
+        }
+      }
+    }
+
+    if (overrun_error == 1UL)
+    {
+      /* Change ADC state to error state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+      /* Error callback */
+      /* Note: In case of overrun, ADC conversion data is preserved until     */
+      /*       flag OVR is reset.                                             */
+      /*       Therefore, old ADC conversion data can be retrieved in         */
+      /*       function "HAL_ADC_ErrorCallback()".                            */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+
+}
+
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 1 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC error callback in non-blocking mode
+  *         (ADC conversion with interruption or transfer by DMA).
+  * @note   In case of error due to overrun when using ADC with DMA transfer
+  *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on regular group
+      (+) Configure the analog watchdog
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group regular.
+  * @note   In case of usage of internal measurement channels (VrefInt, ...):
+  *         These internal paths can be disabled using function
+  *         HAL_ADC_DeInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes channel into ADC group regular,
+  *         following calls to this function can be used to reconfigure
+  *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+  *         without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_ChannelConfTypeDef".
+  * @param hadc ADC handle
+  * @param pConfig Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpOffsetShifted;
+  uint32_t tmp_config_common_path_internal_channel;
+  uint32_t tmp_config_path_internal_channel;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
+  assert_param(IS_ADC_SAMPLING_TIME(pConfig->SamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
+  assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
+  assert_param(IS_ADC_OFFSET(pConfig->Offset));
+  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+     ignored (considered as reset) */
+  assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
+
+  /* Verification of channel number */
+  if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
+  }
+
+  /* ADC must be disabled to set configuration bits                           */
+  if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel rank                                                          */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* ADC channels preselection */
+    LL_ADC_SetChannelPreselection(hadc->Instance, pConfig->Channel);
+
+    /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+    LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
+
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated when ADC is disabled or enabled without   */
+    /* conversion on going on regular group:                                    */
+    /*  - Channel sampling time                                                 */
+    /*  - Channel offset                                                        */
+    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+       )
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
+
+      /* Configure the offset: offset enable/disable, channel, offset value */
+
+      /* Shift the offset with respect to the selected ADC resolution. */
+      /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+      tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
+
+      if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
+      {
+        /* Set ADC selected offset number */
+        LL_ADC_SetOffsetChannel(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel);
+        LL_ADC_SetOffsetLevel(hadc->Instance, pConfig->OffsetNumber, tmpOffsetShifted);
+
+        assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
+        assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSignedSaturation));
+        assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
+        /* Signed and unsigned saturation cannot be set at the same time */
+        assert_param(!((pConfig->OffsetSignedSaturation == ENABLE) && (pConfig->OffsetSaturation == ENABLE)));
+
+
+        /* Set ADC offset sign */
+        LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
+        /* Set ADC offset signed saturation */
+        LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber,      \
+                                         (pConfig->OffsetSignedSaturation == ENABLE) \
+                                         ? LL_ADC_OFFSET_SIGNED_SAT_ENABLE           \
+                                         : LL_ADC_OFFSET_SIGNED_SAT_DISABLE);
+        /* Set ADC offset unsigned saturation */
+        LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfig->OffsetNumber,    \
+                                           (pConfig->OffsetSaturation == ENABLE)     \
+                                           ? LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE       \
+                                           : LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE);
+      }
+      else
+      {
+        /* Scan each offset register to check if the selected channel is targeted.
+           If this is the case, the corresponding offset number is disabled.       */
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+            == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1, 0UL);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+            == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2, 0UL);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+            == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3, 0UL);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+            == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4, 0UL);
+        }
+      }
+    }
+
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated only when ADC is disabled:                */
+    /*  - Single or differential mode                                           */
+    /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+    {
+      /* Set mode single-ended or differential input of the selected ADC channel */
+      LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
+
+      /* Configuration of differential mode */
+      if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
+      {
+        /* Set ADC channel preselection of corresponding negative channel */
+        LL_ADC_SetChannelPreselection(hadc->Instance,
+                                      __HAL_ADC_CHANNEL_DIFF_NEG_INPUT(hadc, pConfig->Channel));
+      }
+
+    }
+    /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
+    /* If internal channel selected, enable dedicated internal buffers and    */
+    /* paths.                                                                 */
+    /* Note: these internal measurement paths can be disabled using           */
+    /* HAL_ADC_DeInit().                                                      */
+
+    if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
+    {
+      tmp_config_common_path_internal_channel =
+        LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+      tmp_config_path_internal_channel = LL_ADC_GetPathInternalCh(hadc->Instance);
+      /* If the requested internal measurement path has already been enabled, */
+      /* bypass the configuration processing.                                 */
+      if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
+          && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+      {
+        if (ADC_VREFINT_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_common_path_internal_channel);
+        }
+      }
+      else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
+               && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+      {
+        if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_VBAT | tmp_config_common_path_internal_channel);
+        }
+      }
+      else if (((pConfig->Channel == ADC_CHANNEL_VDDCORE)
+                && ((tmp_config_path_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)))
+      {
+        if (ADC_VDDCORE_INSTANCE(hadc))
+        {
+          LL_ADC_SetPathInternalCh(hadc->Instance, LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_path_internal_channel);
+        }
+      }
+      else
+      {
+        /* nothing to do */
+      }
+    }
+  }
+
+  /* If a conversion is on going on regular group, no update on regular       */
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Configure the analog watchdog.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the selected analog watchdog, successive
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_AnalogWDGConfTypeDef".
+  * @note   On this STM32 series, analog watchdog thresholds can be modified
+  *         while ADC conversion is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
+  * @param hadc ADC handle
+  * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_awd_high_threshold_shifted;
+  uint32_t tmp_awd_low_threshold_shifted;
+  uint32_t tmp_adc_resolution;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
+  assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
+
+  if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
+      (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
+      (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
+  }
+
+  /* Verify thresholds range */
+  if (hadc->Init.OversamplingMode == ENABLE)
+  {
+    /* Case of oversampling enabled: thresholds are compared to oversampling
+       intermediate computation (after ratio, before shift application) */
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc),
+                              pAnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc),
+                              pAnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+  }
+  else
+  {
+    /* Verify if thresholds are within the selected ADC resolution */
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
+  }
+
+  /* ADC must be disabled to set configuration bits                           */
+  if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on ADC groups regular and injected:                  */
+  /*  - Analog watchdog channels                                              */
+  /*  - Analog watchdog thresholds                                            */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* Format analog watchdog thresholds data in function of the selected ADC resolution */
+    tmp_adc_resolution = LL_ADC_GetResolution(hadc->Instance);
+    tmp_awd_high_threshold_shifted = __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(tmp_adc_resolution,
+                                                                                pAnalogWDGConfig->HighThreshold);
+    tmp_awd_low_threshold_shifted = __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(tmp_adc_resolution,
+                                                                               pAnalogWDGConfig->LowThreshold);
+
+    /* Analog watchdog configuration */
+    if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+    {
+      /* Configuration of analog watchdog:                                    */
+      /*  - Set the analog watchdog enable mode: one or overall group of      */
+      /*    channels, on groups regular and-or injected.                      */
+      switch (pAnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+                                          __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+                                                                          LL_ADC_GROUP_REGULAR));
+          break;
+
+        case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+                                          __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+                                                                          LL_ADC_GROUP_INJECTED));
+          break;
+
+        case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+                                          __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+                                                                          LL_ADC_GROUP_REGULAR_INJECTED));
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_INJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      /* Set the filtering configuration */
+      assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig));
+      LL_ADC_SetAWDFilteringConfiguration(hadc->Instance, hadc->Instance->AWD1HTR, pAnalogWDGConfig->FilteringConfig);
+
+      /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+      LL_ADC_SetAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber,
+                                   LL_ADC_AWD_THRESHOLD_HIGH, tmp_awd_high_threshold_shifted);
+      LL_ADC_SetAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber,
+                                   LL_ADC_AWD_THRESHOLD_LOW, tmp_awd_low_threshold_shifted);
+
+      /* Update state, clear previous result related to AWD1 */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear flag ADC analog watchdog */
+      /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+      /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+      /* (in case left enabled by previous ADC operations).                 */
+      LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+      /* Configure ADC analog watchdog interrupt */
+      if (pAnalogWDGConfig->ITMode == ENABLE)
+      {
+        LL_ADC_EnableIT_AWD1(hadc->Instance);
+      }
+      else
+      {
+        LL_ADC_DisableIT_AWD1(hadc->Instance);
+      }
+    }
+    /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+    else
+    {
+      switch (pAnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+        case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+        case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+          /* Update AWD by bitfield to keep the possibility to monitor        */
+          /* several channels by successive calls of this function.           */
+          if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+          {
+            SET_BIT(hadc->Instance->AWD2CR, (1UL                                                       \
+                                             << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          else
+          {
+            SET_BIT(hadc->Instance->AWD3CR, (1UL                                                      \
+                                             << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+        case ADC_ANALOGWATCHDOG_ALL_INJEC:
+        case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+          /* Update AWD by bitfield to keep the possibility to monitor        */
+          /* several channels by successive calls of this function.           */
+          if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+          {
+            SET_BIT(hadc->Instance->AWD2CR, (1UL                                                           \
+                                             << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          else
+          {
+            SET_BIT(hadc->Instance->AWD3CR, (1UL                                                        \
+                                             << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+      {
+        /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+        MODIFY_REG(hadc->Instance->AWD2LTR, ADC_AWD2LTR_LTR, tmp_awd_low_threshold_shifted);
+        MODIFY_REG(hadc->Instance->AWD2HTR, ADC_AWD2HTR_HTR, tmp_awd_high_threshold_shifted);
+      }
+      else
+      {
+        /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+        MODIFY_REG(hadc->Instance->AWD3LTR, ADC_AWD3LTR_LTR, tmp_awd_low_threshold_shifted);
+        MODIFY_REG(hadc->Instance->AWD3HTR, ADC_AWD3HTR_HTR, tmp_awd_high_threshold_shifted);
+      }
+
+      if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+      {
+        /* Update state, clear previous result related to AWD2 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (pAnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD2(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD2(hadc->Instance);
+        }
+      }
+      /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+      else
+      {
+        /* Update state, clear previous result related to AWD3 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (pAnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD3(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD3(hadc->Instance);
+        }
+      }
+    }
+
+  }
+  /* If a conversion is on going on ADC group regular or injected, no update  */
+  /* could be done on neither of the AWD configuration structure parameters.  */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+  *  @brief    ADC Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral state and errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions to get in run-time the status of the
+    peripheral.
+      (+) Check the ADC state
+      (+) Check the ADC error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ADC handle state.
+  * @note   ADC state machine is managed by bitfields, ADC status must be
+  *         compared with states bits.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  * @param hadc ADC handle
+  * @retval ADC handle state (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Return ADC handle state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code.
+  * @param hadc ADC handle
+  * @retval ADC error code (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Stop ADC conversion.
+  * @param hadc ADC handle
+  * @param ConversionGroup ADC group regular and/or injected.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
+  *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
+  *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
+{
+  uint32_t tickstart;
+  uint32_t conversion_timeout_cpu_cycles = 0UL;
+  uint32_t conversion_group_reassigned = ConversionGroup;
+  uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+  /* Verification if ADC is not already stopped (on regular and injected      */
+  /* groups) to bypass this function if not needed.                           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+  if ((tmp_adc_is_conversion_on_going_regular != 0UL)
+      || (tmp_adc_is_conversion_on_going_injected != 0UL)
+     )
+  {
+    /* Particular case of continuous auto-injection mode combined with        */
+    /* auto-delay mode.                                                       */
+    /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
+    /* injected group stop ADC_CR_JADSTP).                                    */
+    /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
+    /* (see reference manual).                                                */
+    if (((hadc->Instance->CFGR1 & ADC_CFGR1_JAUTO) != 0UL)
+        && (hadc->Init.ContinuousConvMode == ENABLE)
+        && (hadc->Init.LowPowerAutoWait == ENABLE)
+       )
+    {
+      /* Use stop of regular group */
+      conversion_group_reassigned = ADC_REGULAR_GROUP;
+
+      /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
+      {
+        if (conversion_timeout_cpu_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+        conversion_timeout_cpu_cycles ++;
+      }
+
+      /* Clear JEOS */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+    }
+
+    /* Stop potential conversion on going on ADC group regular */
+    if (conversion_group_reassigned != ADC_INJECTED_GROUP)
+    {
+      /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+      if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+      {
+        if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+        {
+          /* Stop ADC group regular conversion */
+          LL_ADC_REG_StopConversion(hadc->Instance);
+        }
+      }
+    }
+
+    /* Stop potential conversion on going on ADC group injected */
+    if (conversion_group_reassigned != ADC_REGULAR_GROUP)
+    {
+      /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+      if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+      {
+        if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+        {
+          /* Stop ADC group injected conversion */
+          LL_ADC_INJ_StopConversion(hadc->Instance);
+        }
+      }
+    }
+
+    /* Selection of start and stop bits with respect to the regular or injected group */
+    switch (conversion_group_reassigned)
+    {
+      case ADC_REGULAR_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+        break;
+      case ADC_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+        break;
+      /* Case ADC_REGULAR_GROUP only*/
+      default:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+        break;
+    }
+
+    /* Wait for conversion effectively stopped */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC must be disabled
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Check if conditions to enable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+                               | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the ADC peripheral */
+    LL_ADC_Enable(hadc->Instance);
+
+    /* Wait for ADC effectively enabled */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+    {
+      /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+          has been cleared (after a calibration), ADEN bit is reset by the
+          calibration logic.
+          The workaround is to continue setting ADEN until ADRDY is becomes 1.
+          Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+          4 ADC clock cycle duration */
+      /* Note: Test of ADC enabled required due to hardware constraint to     */
+      /*       not enable ADC if already enabled.                             */
+      if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+      {
+        LL_ADC_Enable(hadc->Instance);
+      }
+
+      if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+  const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+  /* Verification if ADC is not already disabled:                             */
+  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+  /*       disabled.                                                          */
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_disable_on_going == 0UL)
+     )
+  {
+    /* Check if conditions to disable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+    {
+      /* Disable the ADC peripheral */
+      LL_ADC_Disable(hadc->Instance);
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Wait for ADC effectively disabled */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Update state machine on conversion status if not in error state */
+  if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    /* Is it the end of the regular sequence ? */
+    if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
+    {
+      /* Are conversions software-triggered ? */
+      if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+      {
+        /* Is CONT bit set ? */
+        if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_CONT) == 0UL)
+        {
+          /* CONT bit is not set, no more conversions expected */
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+          if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+          {
+            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* DMA End of Transfer interrupt was triggered but conversions sequence
+         is not over. If DMACFG is set to 0, conversions are stopped. */
+      if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT) == 0UL)
+      {
+        /* DMACFG bit is not set, conversions are stopped. */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+        {
+          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+  else /* DMA and-or internal error occurred */
+  {
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+    {
+      /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Call ADC DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+  /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_adc_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_adc_ex.c
new file mode 100644
index 000000000..5532de28f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_adc_ex.c
@@ -0,0 +1,2406 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Peripheral Control functions
+  *          Other functions (generic functions) are available in file
+  *          "stm32n6xx_hal_adc.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  [..]
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32n6xx_hal_adc.c".
+  [..]
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  * @{
+  */
+
+#define ADC_JSQR_FIELDS  ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+                           ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
+                           ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
+                                                                  once the ADC is enabled */
+
+#define ADC_JSQR_LOW_FIELDS  (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN)  /*!< ADC_JSQR fields of parameters that can be updated anytime
+                                                                  once the ADC is enabled */
+
+/* Fixed timeout value for ADC calibration.                                   */
+/* Values defined to be higher than worst cases: low clock frequency          */
+/* Ex of profile low frequency: (refer to device datasheet, parameter "fADC") */
+/*     Conversion_cycle = (12.5 + 1499.5) = 1512                              */
+/* Calibration_time MAX = Conversion_cycle / fADC_min                         */
+/*                      = 1512 / (0.7MHz) = 2.16 ms                           */
+/* Used timeout value includes a margin versus theoretical max value          */
+#define ADC_CALIBRATION_TIMEOUT         (5UL)        /*!< ADC calibration time-out value (unit: ms) */
+
+#define ADC_CALIBRATION_STEPS           (8UL)        /*!< Number of ADC measurement during calibration procedure */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef ADC_Calibration_MeasureOffset(ADC_HandleTypeDef *hadc,
+                                                       uint32_t SingleDiff,
+                                                       uint32_t *pCalibrationFactor);
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @brief    Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+      (+) Perform the ADC self-calibration for single and differential ending.
+      (+) Get calibration factors for single or differential ending.
+      (+) Set calibration factors for single or differential ending.
+
+      (+) Start conversion of ADC group injected.
+      (+) Stop conversion of ADC group injected.
+      (+) Poll for conversion complete on ADC group injected.
+      (+) Get result of ADC group injected channel conversion.
+      (+) Start conversion of ADC group injected and enable interruptions.
+      (+) Stop conversion of ADC group injected and disable interruptions.
+
+      (+) When multimode feature is available, start multimode and enable DMA transfer.
+      (+) Stop multimode and disable ADC DMA transfer.
+      (+) Get result of multimode conversion.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @note   Note: This calibration may reduce ADC full range. It is only
+  *         recommended for application that needs precise measurement and not
+  *         on full range (Vref+ minus few hundreds of mV, refer to reference
+  *         manual).
+  *         The calibration procedure removes ADC conversion offset error. After
+  *         calibration ADC full range is reduced to
+  *         [Vref-; (Vref+)-CALFACT_x].
+  * @param  hadc       ADC handle
+  * @param  SingleDiff Selection of single-ended or differential input
+  *         This parameter can be one of the following values:
+  *           @arg @ref ADC_SINGLE_ENDED      Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input
+  *           single ended and differential ended
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t calibration_factor;
+  uint32_t offset_required_single_end = 0UL;
+  uint32_t backup_trigger_settings;
+  uint32_t backup_offset_config[4];
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Enable ADC if not already enabled */
+  tmp_hal_status = ADC_Enable(hadc);
+
+  /* Ensure no conversion is ongoing and ADC enabled correctly */
+  if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+      && (tmp_hal_status == HAL_OK))
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Save ADC to current configuration */
+    backup_trigger_settings = READ_REG(hadc->Instance->CFGR1);
+    backup_offset_config[0] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1);
+    backup_offset_config[1] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2);
+    backup_offset_config[2] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3);
+    backup_offset_config[3] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4);
+
+    /* Force ADC configuration for calibration */
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT | ADC_CFGR1_EXTEN | ADC_CFGR1_CONT | ADC_CFGR1_RES);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1, 0);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2, 0);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3, 0);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4, 0);
+
+    /* Disable additional offset before calibration start */
+    LL_ADC_DisableCalibrationOffset(hadc->Instance);
+
+    /* Start ADC offset measurement in single ended mode */
+    tmp_hal_status = ADC_Calibration_MeasureOffset(hadc, ADC_SINGLE_ENDED, &calibration_factor);
+
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Store the singled-ended calibration factor in CALFACT_S[8:0]. */
+      LL_ADC_SetCalibrationFactor(hadc->Instance, LL_ADC_SINGLE_ENDED, calibration_factor);
+
+      if ((SingleDiff & ADC_DIFFERENTIAL_ENDED) == ADC_DIFFERENTIAL_ENDED)
+      {
+        /* Store calibration offset state after single-ended calibration.     */
+        /* keep the same setting for differential-ended calibration.          */
+        offset_required_single_end = LL_ADC_IsCalibrationOffsetEnabled(hadc->Instance);
+
+        /* Start ADC offset measurement in differential ended mode */
+        tmp_hal_status = ADC_Calibration_MeasureOffset(hadc, ADC_DIFFERENTIAL_ENDED, &calibration_factor);
+
+        if (tmp_hal_status == HAL_OK)
+        {
+          /* Store the differential-ended calibration factor in CALFACT_D[8:0]. */
+          LL_ADC_SetCalibrationFactor(hadc->Instance, LL_ADC_DIFFERENTIAL_ENDED, calibration_factor);
+
+          /* Additional calibration offset is applied to both single-ended    */
+          /* and differential-ended conversion mode.                          */
+          /* If calibration offset was enabled by differential-ended          */
+          /* calibration, single-ended mode should be recalibrated using with */
+          /* calibration offset enabled.                                      */
+          if (offset_required_single_end != LL_ADC_IsCalibrationOffsetEnabled(hadc->Instance))
+          {
+            /* Start ADC offset measurement in single-ended mode */
+            tmp_hal_status = ADC_Calibration_MeasureOffset(hadc, ADC_SINGLE_ENDED, &calibration_factor);
+
+            if (tmp_hal_status == HAL_OK)
+            {
+              /* Store the singled-ended calibration factor in CALFACT_S[8:0]. */
+              LL_ADC_SetCalibrationFactor(hadc->Instance, LL_ADC_SINGLE_ENDED, calibration_factor);
+            }
+            else
+            {
+              SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+              /* Note: No need to update variable "tmp_hal_status" here:      */
+              /*       already set to state "HAL_ERROR" by function disabling */
+              /*       the ADC.                                               */
+            }
+          }
+          else
+          {
+            /* nothing to do */
+          }
+        }
+        else
+        {
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Note: No need to update variable "tmp_hal_status" here: already  */
+          /*       set to state "HAL_ERROR" by function disabling the ADC.    */
+        }
+      }
+      else
+      {
+        /* Prevent unused argument(s) compilation warning if no assert_param  */
+        /* check (Only used for differential mode calibration)                */
+        UNUSED(offset_required_single_end);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Note: No need to update variable "tmp_hal_status" here: already set  */
+      /*       to state "HAL_ERROR" by function disabling the ADC.            */
+    }
+
+    /* End of calibration procedure */
+    LL_ADC_StopCalibration(hadc->Instance);
+
+    /* Restore ADC configuration to previous state */
+    WRITE_REG(hadc->Instance->CFGR1, backup_trigger_settings);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1, backup_offset_config[0]);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2, backup_offset_config[1]);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3, backup_offset_config[2]);
+    LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4, backup_offset_config[3]);
+
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Note: No need to update variable "tmp_hal_status" here: already set    */
+    /*       to state "HAL_ERROR" by function disabling the ADC.              */
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get the calibration factor.
+  * @param hadc ADC handle.
+  * @param SingleDiff This parameter can be only:
+  *           @arg @ref ADC_SINGLE_ENDED      Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input
+  *           differential ended
+  * @retval Calibration value.
+  */
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+  /* Return the selected ADC calibration value */
+  return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+}
+
+/**
+  * @brief  Set the calibration factor to overwrite automatic conversion result.
+  *         ADC must be enabled and no conversion is ongoing.
+  * @param hadc ADC handle
+  * @param SingleDiff This parameter can be only:
+  *           @arg @ref ADC_SINGLE_ENDED      Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input
+  *           differential ended
+  * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+                                                 uint32_t CalibrationFactor)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+  assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Verification of hardware constraints before modifying the calibration    */
+  /* factors register: ADC must be enabled, no conversion on going.           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* Set the selected ADC calibration value */
+    LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+  }
+  else
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    /* Update ADC error code */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    /* Update ADC state machine to error */
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+/**
+  * @brief  Enable ADC, start conversion of injected group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled when multimode feature is available:
+  *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+  *         then for ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to injected group conversion results  */
+      /* - Set state bitfield related to injected operation                   */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                        HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Clear ADC group injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started),                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+        {
+          LL_ADC_INJ_StartConversion(hadc->Instance);
+        }
+      }
+      else
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#else
+      if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+      {
+        /* Start ADC group injected conversion */
+        LL_ADC_INJ_StartConversion(hadc->Instance);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+    }
+    else
+    {
+      __HAL_UNLOCK(hadc);
+    }
+
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+  *         no regular conversion is on going.
+  * @note   If ADC must be disabled and if conversion is on going on
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   In case of multimode enabled (when multimode feature is available),
+  *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled.
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @param hadc ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on regular group is on-going                       */
+  if (tmp_hal_status == HAL_OK)
+  {
+    if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for injected group conversion to be completed.
+  * @param hadc ADC handle
+  * @param Timeout Timeout value in millisecond.
+  * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+  *         checked and cleared depending on AUTDLY bit status.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_Flag_End;
+  uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+  uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of sequence selected */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_End = ADC_FLAG_JEOS;
+  }
+  else /* end of conversion selected */
+  {
+    tmp_Flag_End = ADC_FLAG_JEOC;
+  }
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait until End of Conversion or Sequence flag is raised */
+  while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Retrieve ADC configuration */
+  tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+  tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+  /* Get relevant register CFGR1 in ADC instance of ADC master or slave  */
+  /* in function of multimode state (for devices with multimode         */
+  /* available).                                                        */
+#if defined(ADC_MULTIMODE_SUPPORT)
+  if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+      || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+     )
+  {
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+  }
+  else
+  {
+    tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR1);
+  }
+#else
+  tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+  /* Determine whether any further conversion upcoming on group injected      */
+  /* by external trigger or by automatic injected conversion                  */
+  /* from group regular.                                                      */
+  if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
+      ((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL)      &&
+       ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
+        (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL))))
+  {
+    /* Check whether end of sequence is reached */
+    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+      if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+
+    }
+  }
+
+  /* Clear polled flag */
+  if (tmp_Flag_End == ADC_FLAG_JEOS)
+  {
+    /* Clear end of sequence JEOS flag of injected group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
+    /* For injected groups, no new conversion will start before JEOS is       */
+    /* cleared.                                                               */
+    if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+    }
+  }
+  else
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+  }
+
+  /* Return API HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of injected group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : JEOC (end of conversion) or JEOS (end of sequence)
+  * @note   Case of multimode enabled (when multimode feature is enabled):
+  *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+  *         then for ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to injected group conversion results  */
+      /* - Set state bitfield related to injected operation                   */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                        HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Clear ADC group injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable ADC end of conversion interrupt */
+      switch (hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV:
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+          break;
+      }
+
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started),                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+        {
+          LL_ADC_INJ_StartConversion(hadc->Instance);
+        }
+      }
+      else
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#else
+      if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+      {
+        /* Start ADC group injected conversion */
+        LL_ADC_INJ_StartConversion(hadc->Instance);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+    }
+    else
+    {
+      __HAL_UNLOCK(hadc);
+    }
+
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop conversion of injected channels, disable interruption of
+  *         end-of-conversion. Disable ADC peripheral if no regular conversion
+  *         is on going.
+  * @note   If ADC must be disabled and if conversion is on going on
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+  *         then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled.
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on the other group (regular group) is intended to   */
+  /* continue.                                                                */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for injected channels */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS));
+
+    if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+  * @note   Multimode must have been previously configured using
+  *         HAL_ADCEx_MultiModeConfigChannel() function.
+  *         Interruptions enabled in this function:
+  *          overrun, DMA half transfer, DMA transfer complete.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Conversion data of both multimode ADC instances will take each one buffer element, therefore
+            buffer total size should be doubled to get similar data size for each ADC instance vs independent mode.
+  * @note   State field of Slave ADC handle is not updated in this configuration:
+  *          user should not rely on it for information related to Slave regular
+  *         conversions.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param pData Destination Buffer address.
+  * @param Length Length of data to be transferred from ADC peripheral to memory (unit: number of transfers)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  ADC_HandleTypeDef tmphadcSlave;
+  ADC_Common_TypeDef *tmp_adc_common;
+  uint32_t LengthInBytes;
+  DMA_NodeConfTypeDef node_conf;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+    ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the ADC peripherals: master and slave (in case if not already   */
+    /* enabled previously)                                                    */
+    tmp_hal_status = ADC_Enable(hadc);
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Enable(&tmphadcSlave);
+    }
+
+    /* Start multimode conversion of ADCs pair */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
+                        HAL_ADC_STATE_REG_BUSY);
+
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+
+      /* Pointer to the common control register  */
+      tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+      /* start (in case of SW start):                                           */
+
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable ADC overrun interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+      /* Start the DMA channel */
+      if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
+        {
+          /* Length should be converted to number of bytes */
+          if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
+          {
+            return HAL_ERROR;
+          }
+
+          /* Length should be converted to number of bytes */
+          if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+          {
+            /* Word -> Bytes */
+            LengthInBytes = Length * 4U;
+          }
+          else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+          {
+            /* Halfword -> Bytes */
+            LengthInBytes = Length * 2U;
+          }
+          else /* Bytes */
+          {
+            /* Same size already expressed in Bytes */
+            LengthInBytes = Length;
+          }
+
+          hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
+          hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+            (uint32_t)&tmp_adc_common->CDR;
+          hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+          tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
+        }
+        else
+        {
+          tmp_hal_status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Length should be converted to number of bytes */
+        if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+        {
+          /* Word -> Bytes */
+          LengthInBytes = Length * 4U;
+        }
+        else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+        {
+          /* Halfword -> Bytes */
+          LengthInBytes = Length * 2U;
+        }
+        else /* Bytes */
+        {
+          /* Same size already expressed in Bytes */
+          LengthInBytes = Length;
+        }
+
+        tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData,
+                                          LengthInBytes);
+      }
+
+      if (tmp_hal_status != HAL_ERROR)
+      {
+        /* Enable conversion of regular group.                                    */
+        /* If software start has been selected, conversion starts immediately.    */
+        /* If external trigger has been selected, conversion will start at next   */
+        /* trigger event.                                                         */
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+    }
+    else
+    {
+      __HAL_UNLOCK(hadc);
+    }
+
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+  * @note   Multimode is kept enabled after this function. MultiMode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+  *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.
+  * @note   In case of DMA configured in circular mode, function
+  *         HAL_ADC_Stop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmphadcSlave;
+  uint32_t tmphadcSlave_conversion_on_going;
+  HAL_StatusTypeDef tmphadcSlave_disable_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+
+  /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+    ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+
+    /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+    tickstart = HAL_GetTick();
+
+    tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+           || (tmphadcSlave_conversion_on_going == 1UL)
+          )
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+        if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+            || (tmphadcSlave_conversion_on_going == 1UL)
+           )
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+
+      tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    }
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /*       with HAL_ADC_Stop_DMA() API.                                     */
+    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+    {
+      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+      /* Check if DMA channel effectively disabled */
+      if (tmp_hal_status == HAL_ERROR)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+      }
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripherals: master and slave */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
+      if ((ADC_Disable(hadc) == HAL_OK)           &&
+          (tmphadcSlave_disable_status == HAL_OK))
+      {
+        tmp_hal_status = HAL_OK;
+      }
+    }
+    else
+    {
+      /* In case of error, attempt to disable ADC master and slave without status assert */
+      (void) ADC_Disable(hadc);
+      (void) ADC_Disable(&tmphadcSlave);
+    }
+
+    /* Set ADC state (ADC master) */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
+  * @note   Multimode data contains ADC master and slave conversion data
+  *         concatenated. Data is usable under conditions of ADC multimode
+  *         data format selected and data width,
+  *         refer to @ref ADCEx_Dual_Mode_Data_Format.
+  *         The recommended method, without any constraint, is to use
+  *         DMA transfer. refer to @ref HAL_ADCEx_MultiModeStart_DMA.
+  * @note   Another solution exists to retrieve multimode conversion data
+  *         without packing (refer to @ref LL_ADC_REG_ReadMultiConvNoPacking)
+  *         but with timing constraints.
+  *         The recommended method, without any constraint, is to use
+  *         DMA transfer. refer to @ref HAL_ADCEx_MultiModeStart_DMA.
+  * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+  * @retval The converted data values.
+  */
+uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
+{
+  const ADC_Common_TypeDef *tmpADC_Common;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below               */
+  UNUSED(hadc);
+
+  /* Pointer to the common control register  */
+  tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+  /* Return the multi mode conversion value */
+  return tmpADC_Common->CDR;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Get ADC injected group conversion result.
+  * @note   Reading register JDRx automatically clears ADC flag JEOC
+  *         (ADC group injected end of unitary conversion).
+  * @note   This function returns an unsigned value. Using the ADC offset
+  *         feature can result in negative conversion data.
+  *         To read conversion data with ADC offset enabled
+  *         use function @ref HAL_ADCEx_InjectedGetSignedValue.
+  * @note   This function does not clear ADC flag JEOS
+  *         (ADC group injected end of sequence conversion)
+  *         Occurrence of flag JEOS rising:
+  *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
+  *            to flag JEOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag JEOC only is raised, at the end of the scan sequence
+  *            both flags JEOC and EOS are raised.
+  *         Flag JEOS must not be cleared by this function because
+  *         it would not be compliant with low power features
+  *         (feature low power auto-wait, not available on all STM32 families).
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+  * @param hadc ADC handle
+  * @param InjectedRank the converted ADC injected rank.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+  *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+  *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+  *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+  * @retval ADC group injected conversion data
+  */
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+  uint32_t tmp_jdr;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+  /* Get ADC converted value */
+  switch (InjectedRank)
+  {
+    case ADC_INJECTED_RANK_4:
+      tmp_jdr = hadc->Instance->JDR4;
+      break;
+    case ADC_INJECTED_RANK_3:
+      tmp_jdr = hadc->Instance->JDR3;
+      break;
+    case ADC_INJECTED_RANK_2:
+      tmp_jdr = hadc->Instance->JDR2;
+      break;
+    case ADC_INJECTED_RANK_1:
+    default:
+      tmp_jdr = hadc->Instance->JDR1;
+      break;
+  }
+
+  /* Return ADC converted value */
+  return tmp_jdr;
+}
+
+/**
+  * @brief  Get ADC injected group conversion result.
+  * @note   Reading register JDRx automatically clears ADC flag JEOC
+  *         (ADC group injected end of unitary conversion).
+  * @note   This function does not clear ADC flag JEOS
+  *         (ADC group injected end of sequence conversion)
+  *         Occurrence of flag JEOS rising:
+  *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
+  *            to flag JEOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag JEOC only is raised, at the end of the scan sequence
+  *            both flags JEOC and EOS are raised.
+  *         Flag JEOS must not be cleared by this function because
+  *         it would not be compliant with low power features
+  *         (feature low power auto-wait, not available on all STM32 families).
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+  * @param hadc ADC handle
+  * @param InjectedRank the converted ADC injected rank.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+  *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+  *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+  *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+  * @retval ADC group injected conversion data
+  */
+int32_t HAL_ADCEx_InjectedGetSignedValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+  int32_t tmp_jdr;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+  /* Get ADC converted value */
+  switch (InjectedRank)
+  {
+    case ADC_INJECTED_RANK_4:
+      tmp_jdr = (int32_t)(hadc->Instance->JDR4);
+      break;
+    case ADC_INJECTED_RANK_3:
+      tmp_jdr = (int32_t)(hadc->Instance->JDR3);
+      break;
+    case ADC_INJECTED_RANK_2:
+      tmp_jdr = (int32_t)(hadc->Instance->JDR2);
+      break;
+    case ADC_INJECTED_RANK_1:
+    default:
+      tmp_jdr = (int32_t)(hadc->Instance->JDR1);
+      break;
+  }
+
+  /* Return ADC converted value */
+  return tmp_jdr;
+}
+
+/**
+  * @brief  Injected conversion complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 2 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 3 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+  */
+}
+
+
+/**
+  * @brief  End Of Sampling callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in
+  *         case of auto_injection mode), disable ADC peripheral if no
+  *         conversion is on going on injected group.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if regular conversions are effectively stopped
+     and if no injected conversions are on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+
+/**
+  * @brief  Stop ADC conversion of ADC groups regular and injected,
+  *         disable interrution of end-of-conversion,
+  *         disable ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped
+    and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Disable all regular-related interrupts */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+    /* 2. Disable ADC peripheral if no injected conversions are on-going */
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+      /* if no issue reported */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
+  *         ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
+  *         For multimode (when multimode feature is available),
+  *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped
+     and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR1_DMACFG is kept) */
+    MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* while DMA transfer is on going)                                        */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+    /* to keep in memory a potential failing status.                          */
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      if (tmp_hal_status == HAL_OK)
+      {
+        tmp_hal_status = ADC_Disable(hadc);
+      }
+      else
+      {
+        (void)ADC_Disable(hadc);
+      }
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
+  *         conversion is on-going.
+  * @note   Multimode is kept enabled after this function. Multimode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+  *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.
+  * @note   In case of DMA configured in circular mode, function
+  *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmphadcSlave;
+  uint32_t tmphadcSlave_conversion_on_going;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+
+  /* 1. Stop potential multimode conversion on going, on regular groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+    ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+    if (tmphadcSlave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+
+    /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+    tickstart = HAL_GetTick();
+
+    tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+           || (tmphadcSlave_conversion_on_going == 1UL)
+          )
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+        if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+            || (tmphadcSlave_conversion_on_going == 1UL)
+           )
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+
+      tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+    }
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripherals: master and slave if no injected        */
+    /*   conversion is on-going.                                              */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+      if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+      {
+        tmp_hal_status =  ADC_Disable(hadc);
+        if (tmp_hal_status == HAL_OK)
+        {
+          if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
+          {
+            tmp_hal_status =  ADC_Disable(&tmphadcSlave);
+          }
+        }
+      }
+
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Both Master and Slave ADC's could be disabled. Update Master State */
+        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+      }
+      else
+      {
+        /* injected (Master or Slave) conversions are still on-going,
+           no Master State change */
+      }
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+  * @brief    ADC Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on injected group
+      (+) Configure multimode (when multimode feature is available)
+      (+) Disable ADC voltage regulator
+      (+) Enter ADC deep-power-down mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group injected.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes injected group, following calls to this
+  *         function can be used to reconfigure some parameters of structure
+  *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_InjectionConfTypeDef".
+  * @note   In case of usage of internal measurement channels (VrefInt, ...):
+  *         These internal paths can be disabled using function
+  *         HAL_ADC_DeInit().
+  * @param hadc ADC handle
+  * @param pConfigInjected Structure of ADC injected group and ADC channel for
+  *         injected group.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+                                                  const ADC_InjectionConfTypeDef *pConfigInjected)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpOffsetShifted;
+  uint32_t tmp_config_common_path_internal_channel;
+  uint32_t tmp_config_path_internal_channel;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SAMPLING_TIME(pConfigInjected->InjectedSamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
+  assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
+  assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
+  assert_param(IS_ADC_EXTTRIGINJEC(hadc->Instance, pConfigInjected->ExternalTrigInjecConv));
+  assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+  assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
+  assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
+    assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
+  }
+
+  /* Check offset range according to oversampling setting */
+  if (hadc->Init.OversamplingMode == ENABLE)
+  {
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc),
+                              pConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
+  }
+  else
+  {
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+  }
+
+  /* JDISCEN and JAUTO bits can't be set at the same time  */
+  assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)                                 \
+                 && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+  /*  DISCEN and JAUTO bits can't be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+  /* Verification of channel number */
+  if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
+  }
+
+  /* ADC must be disabled to set configuration bits                           */
+  if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Configuration of injected group sequencer:                               */
+  /* - if scan mode is disabled:                                              */
+  /*    * Injected channels sequence length is set to 0x00: 1 channel         */
+  /*      converted (channel on injected rank 1)                              */
+  /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
+  /* - if scan mode is enabled:                                               */
+  /*    * Injected channels sequence length is set to parameter               */
+  /*      "InjectedNbrOfConversion".                                          */
+  /*   Note: Scan mode is not present by hardware on this device, but used    */
+  /*   by software for alignment over all STM32 devices.                      */
+
+  if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
+      (pConfigInjected->InjectedNbrOfConversion == 1U))
+  {
+    /* Configuration of context register JSQR:                                */
+    /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
+    /*    (scan mode disabled, only rank 1 used)                              */
+    /*  - external trigger to start conversion                                */
+    /*  - external trigger polarity                                           */
+    /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+
+    if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+    {
+      /* Enable external trigger if trigger selection is different of         */
+      /* software start.                                                      */
+      /* Note: This configuration keeps the hardware feature of parameter     */
+      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+      /*       software start.                                                */
+      if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+      {
+        MODIFY_REG(hadc->Instance->JSQR,
+                   ADC_JSQR_FIELDS,
+                   ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
+                   | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+                   | pConfigInjected->ExternalTrigInjecConvEdge);
+      }
+      else
+      {
+        MODIFY_REG(hadc->Instance->JSQR,
+                   ADC_JSQR_FIELDS,
+                   ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
+      }
+    }
+  }
+  else
+  {
+    /* Case of scan mode enabled, several channels to set into injected group */
+    /* sequencer.                                                             */
+
+    MODIFY_REG(hadc->Instance->JSQR,
+               ADC_JSQR_LOW_FIELDS,
+               ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank)
+               | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+               | pConfigInjected->ExternalTrigInjecConvEdge
+               | ((pConfigInjected->InjectedNbrOfConversion - 1U) & ADC_JSQR_JL));
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on injected group:                                   */
+  /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
+  /*    mode is disabled.                                                     */
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* ADC channels preselection */
+    LL_ADC_SetChannelPreselection(hadc->Instance, pConfigInjected->InjectedChannel);
+
+    /* If auto-injected mode is disabled: no constraint                       */
+    if (pConfigInjected->AutoInjectedConv == DISABLE)
+    {
+      MODIFY_REG(hadc->Instance->CFGR1,
+                 ADC_CFGR1_JDISCEN,
+                 ADC_CFGR1_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+    }
+    /* If auto-injected mode is enabled: Injected discontinuous setting is    */
+    /* discarded.                                                             */
+    else
+    {
+      MODIFY_REG(hadc->Instance->CFGR1,
+                 ADC_CFGR1_JDISCEN,
+                 ADC_CFGR1_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+    }
+
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular and injected groups:                      */
+  /*  - Automatic injected conversion: can be enabled if injected group       */
+  /*    external triggers are disabled.                                       */
+  /*  - Channel sampling time                                                 */
+  /*  - Channel offset                                                        */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* If injected group external triggers are disabled (set to injected      */
+    /* software start): no constraint                                         */
+    if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+        || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+    {
+      if (pConfigInjected->AutoInjectedConv == ENABLE)
+      {
+        SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+      }
+    }
+    /* If Automatic injected conversion was intended to be set and could not  */
+    /* due to injected group external triggers enabled, error is reported.    */
+    else
+    {
+      if (pConfigInjected->AutoInjectedConv == ENABLE)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+        tmp_hal_status = HAL_ERROR;
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
+      }
+    }
+
+    if (pConfigInjected->InjecOversamplingMode == ENABLE)
+    {
+      assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
+      assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
+
+      /*  JOVSE must be reset in case of triggered regular mode  */
+      assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
+                     (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
+
+      /* Configuration of Injected Oversampler:                                 */
+      /*  - Oversampling Ratio                                                  */
+      /*  - Right bit shift                                                     */
+
+      /* Enable OverSampling mode */
+      MODIFY_REG(hadc->Instance->CFGR2,
+                 ADC_CFGR2_JOVSE |
+                 ADC_CFGR2_OVSR  |
+                 ADC_CFGR2_OVSS,
+                 ADC_CFGR2_JOVSE                                  |
+                 ((pConfigInjected->InjecOversampling.Ratio - 1UL)  << ADC_CFGR2_OVSR_Pos) |
+                 pConfigInjected->InjecOversampling.RightBitShift
+                );
+    }
+    else
+    {
+      /* Disable Regular OverSampling */
+      CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+    }
+
+    /* Set sampling time of the selected ADC channel */
+    LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
+                                  pConfigInjected->InjectedSamplingTime);
+
+    /* Configure the offset: offset enable/disable, channel, offset value */
+
+    /* Shift the offset with respect to the selected ADC resolution. */
+    /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+    tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
+
+    if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+    {
+      /* Set ADC selected offset number */
+      LL_ADC_SetOffsetChannel(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel);
+      LL_ADC_SetOffsetLevel(hadc->Instance, pConfigInjected->InjectedOffsetNumber, tmpOffsetShifted);
+
+      assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
+      assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSignedSaturation));
+      assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation));
+      /* Signed and unsigned saturation cannot be set at the same time */
+      assert_param(!((pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
+                     && (pConfigInjected->InjectedOffsetSaturation == ENABLE)));
+
+      /* Set ADC selected offset sign  */
+      LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
+      /* Set ADC selected offset signed saturation */
+      LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
+                                       (pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
+                                       ? LL_ADC_OFFSET_SIGNED_SAT_ENABLE                           \
+                                       : LL_ADC_OFFSET_SIGNED_SAT_DISABLE);
+      /* Set ADC offset unsigned saturation */
+      LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,    \
+                                         (pConfigInjected->InjectedOffsetSaturation == ENABLE)     \
+                                         ? LL_ADC_OFFSET_UNSIGNED_SAT_ENABLE                       \
+                                         : LL_ADC_OFFSET_UNSIGNED_SAT_DISABLE);
+    }
+    else
+    {
+      /* Scan each offset register to check if the selected channel is targeted. */
+      /* If this is the case, the corresponding offset number is disabled.       */
+      /* Scan each offset register to check if the selected channel is targeted.
+         If this is the case, the corresponding offset number is disabled.       */
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+          == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1, 0UL);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+          == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2, 0UL);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+          == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3, 0UL);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+          == __HAL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4, 0UL);
+      }
+    }
+
+  }
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated only when ADC is disabled:                */
+  /*  - Single or differential mode                                           */
+  /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Set mode single-ended or differential input of the selected ADC channel */
+    LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
+
+    /* Configuration of differential mode */
+    if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
+    {
+      /* Set ADC channel preselection of corresponding negative channel */
+      LL_ADC_SetChannelPreselection(hadc->Instance,
+                                    __HAL_ADC_CHANNEL_DIFF_NEG_INPUT(hadc, pConfigInjected->InjectedChannel));
+    }
+
+  }
+
+  /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
+  /* internal measurement paths enable: If internal channel selected,       */
+  /* enable dedicated internal buffers and path.                            */
+  /* Note: these internal measurement paths can be disabled using           */
+  /* HAL_ADC_DeInit().                                                      */
+
+  if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
+  {
+    tmp_config_common_path_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+    tmp_config_path_internal_channel = LL_ADC_GetPathInternalCh(hadc->Instance);
+
+    /* If the requested internal measurement path has already been enabled,   */
+    /* bypass the configuration processing.                                   */
+    if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+        && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+    {
+      if (ADC_VREFINT_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_common_path_internal_channel);
+      }
+    }
+    else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+             && ((tmp_config_common_path_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+    {
+      if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_VBAT | tmp_config_common_path_internal_channel);
+      }
+    }
+    else if (((pConfigInjected->InjectedChannel == ADC_CHANNEL_VDDCORE)
+              && ((tmp_config_path_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL)))
+    {
+      if (ADC_VDDCORE_INSTANCE(hadc))
+      {
+        LL_ADC_SetPathInternalCh(hadc->Instance, LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_path_internal_channel);
+      }
+    }
+    else
+    {
+      /* nothing to do */
+    }
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Enable ADC multimode and configure multimode parameters
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes multimode parameters, following
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+  *         the ADCs.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_MultiModeTypeDef".
+  * @note   To move back configuration from multimode to single mode, ADC must
+  *         be reset (using function HAL_ADC_Init() ).
+  * @param hadc Master ADC handle
+  * @param pMultimode Structure of ADC multimode configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
+                                                   const ADC_MultiModeTypeDef *pMultimode)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_Common_TypeDef *tmpADC_Common;
+  ADC_HandleTypeDef tmphadcSlave;
+  uint32_t tmphadcSlave_conversion_on_going;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
+  if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+  {
+    assert_param(IS_ADC_DUAL_DATA_MODE(pMultimode->DualModeData));
+    assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Temporary handle minimum initialization */
+  __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+  ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
+  ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+  if (tmphadcSlave.Instance == NULL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    __HAL_UNLOCK(hadc);
+
+    return HAL_ERROR;
+  }
+
+  /* ADC must be disabled to set configuration bits */
+  if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+  {
+    if (LL_ADC_IsEnabled(tmphadcSlave.Instance) != 0UL)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Multimode DMA configuration                                           */
+  /*  - Multimode DMA mode                                                    */
+  tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+  if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+      && (tmphadcSlave_conversion_on_going == 0UL))
+  {
+    /* Pointer to the common control register */
+    tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+    /* If multimode is selected, configure all multimode parameters.          */
+    /* Otherwise, reset multimode parameters (can be used in case of          */
+    /* transition from multimode to independent mode).                        */
+    if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+    {
+      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData);
+
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      /*    Note: Delay range depends on selected resolution:                     */
+      /*      from 1 to 12 clock cycles for 12 bits                               */
+      /*      from 1 to 10 clock cycles for 10 bits,                              */
+      /*      from 1 to 8 clock cycles for 8 bits                                 */
+      /*      from 1 to 6 clock cycles for 6 bits                                 */
+      /*    If a higher delay is selected, it will be clipped to maximum delay    */
+      /*    range                                                                 */
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        MODIFY_REG(tmpADC_Common->CCR,
+                   ADC_CCR_DUAL |
+                   ADC_CCR_DELAY,
+                   pMultimode->Mode |
+                   pMultimode->TwoSamplingDelay
+                  );
+      }
+    }
+    else /* ADC_MODE_INDEPENDENT */
+    {
+      CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
+
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+      }
+    }
+  }
+  /* If one of the ADC sharing the same common group is enabled, no update    */
+  /* could be done on neither of the multimode structure parameters.          */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Enter ADC deep-power-down mode
+  * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
+  *         in reducing leakage currents. It is particularly interesting before
+  *         entering stop modes.
+  * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+  *         ADC voltage regulator. This means that this API encompasses
+  *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+  *         calibration is lost.
+  * @note   To exit the ADC deep-power-down mode, the user is expected to
+  *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
+  *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+  *         saved calibration factor.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    LL_ADC_EnableDeepPowerDown(hadc->Instance);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief Measure ADC offset during calibration
+  * @note  To measure ADC calibration offset ADC must be enabled and calibration
+  *         mode should be enabled. This function is intended to be used inside
+  *         function @ref HAL_ADCEx_Calibration_Start
+  * @param hadc ADC handle
+  * @param SingleDiff
+  * @param pCalibrationFactor ADC measurement offset
+  * @retval HAL status
+  */
+HAL_StatusTypeDef ADC_Calibration_MeasureOffset(ADC_HandleTypeDef *hadc,
+                                                uint32_t SingleDiff,
+                                                uint32_t *pCalibrationFactor)
+{
+  int32_t  calib_factor_avg = 0;
+  uint32_t calibration_step;
+  uint32_t tickstart;
+
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+  if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+  {
+    /* Start ADC calibration */
+    LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
+
+    do
+    {
+      /* Measure current ADC offset */
+
+      /* With calibration mode enabled, start multiple conversion and           */
+      /* accumulate data to compute ADC conversion offset.                      */
+      /* The calibration factor will be the averaged converted value            */
+      for (calibration_step = 0; calibration_step < ADC_CALIBRATION_STEPS; calibration_step++)
+      {
+        LL_ADC_REG_StartConversion(hadc->Instance);
+
+        /* Wait for ADC conversion to end */
+        /* Get tick count */
+        tickstart = HAL_GetTick();
+        while (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+        {
+          if ((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+          {
+            /* New check to avoid false timeout detection in case of preemption */
+            if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+            {
+              /* Update ADC state machine to error */
+              SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+              /* Set ADC error code to ADC peripheral internal error */
+              SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+              return HAL_ERROR;
+            }
+          }
+        }
+
+        calib_factor_avg += (int32_t)(LL_ADC_REG_ReadConversionData32(hadc->Instance));
+      } /* end of calibration steps */
+
+      /* Compute the average data */
+      calib_factor_avg = calib_factor_avg / (int32_t)(calibration_step);
+
+      if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+      {
+        /* In differential mode, subtract averaged data by 0x7FF (middle      */
+        /* value for differential ended corresponding to a null offset)      */
+        calib_factor_avg = calib_factor_avg - 0x7FF;
+      }
+      else
+      {
+        /* nothing to do */
+      }
+      if (calib_factor_avg <= 0)
+      {
+        if (LL_ADC_IsCalibrationOffsetEnabled(hadc->Instance) == 0UL)
+        {
+          LL_ADC_EnableCalibrationOffset(hadc->Instance);
+        }
+        else
+        {
+          /* If calibration additional offset is enabled, measured calibration */
+          /* factor should be different than 0.                                */
+          tmp_hal_status = HAL_ERROR;
+
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+        }
+      }
+      else
+      {
+        *pCalibrationFactor = (uint32_t)(calib_factor_avg);
+      }
+    } while ((calib_factor_avg <= 0) && (tmp_hal_status == HAL_OK));
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_bsec.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_bsec.c
new file mode 100644
index 000000000..0402762e4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_bsec.c
@@ -0,0 +1,1825 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_bsec.c
+  * @author  MCD Application Team
+  * @brief   BSEC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of Boot and SECurity (BSEC):
+  *           + Initialization and de-initialization functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+     *** General Configuration ***
+    ============================================================
+    [..]
+
+      (+) Call the function HAL_BSEC_GetStatus() to get the status of BSEC
+    peripheral.
+
+      (+) Call the function HAL_BSEC_GlobalLock() to lock the write to BSEC
+    registers.
+
+      (+) Call the function HAL_BSEC_GetGlobalLockStatus() to get the global
+    write registers lock status.
+
+      (+) Call the function HAL_BSEC_GetErrorCode() to get the error code
+    raised when API return HAL_ERROR.
+
+     *** OTP Management ***
+    ============================================================
+    [..]
+
+      (+) Call the function HAL_BSEC_OTP_Read() to read the value of
+    an OTP fuse.
+
+      (+) Call the function HAL_BSEC_OTP_Program() to program an OTP
+    fuse with or without permanent lock.
+
+      (+) Call the function HAL_BSEC_OTP_Reload() to reload an OTP
+    fuse value.
+
+      (+) Call the function HAL_BSEC_OTP_Lock() to sticky lock
+    an OTP fuse programming, writing shadowed register or reload.
+
+      (+) Call the function HAL_BSEC_OTP_GetState() to get the sticky lock
+    status (programming, writing shadowed register or reload), the permanent
+    lock status, the shadow configuration, the ECC or hidden status of an
+    OTP fuse.
+
+
+     *** Shadow fuse register management ***
+    [..]
+
+      (+) Call the function HAL_BSEC_OTP_ReadShadow() to read the value of
+    a shadow fuse register.
+
+      (+) Call the function HAL_BSEC_OTP_WriteShadow() to write in a shadow
+    fuse register.
+
+      (+) Call the function HAL_BSEC_OTP_GetShadowState() to
+    get the validity status of a shadow fuse register.
+
+     *** Device lifecycle management ***
+    ============================================================
+    [..]
+
+      (+) Call the function HAL_BSEC_GetDeviceLifeCycleState() to get the
+    BSEC device lifecycle state.
+
+      (+) Call the function HAL_BSEC_ReadEpochCounter() to read the value
+    of epoch counter.
+
+      (+) Call the function HAL_BSEC_SelectEpochCounter() to select the
+    epoch counter used by SAES.
+
+      (+) Call the function HAL_BSEC_GetEpochCounterSelection() to get
+    the epoch counter selection for SAES.
+
+     *** HDPL management ***
+    ============================================================
+        [..]
+
+      (+) Call the function HAL_BSEC_GetHDPLValue() to get the current HDPL.
+
+      (+) Call the function HAL_BSEC_IncrementHDPLValue() to increment the HDPL.
+
+      (+) Call the function HAL_BSEC_ConfigSAESHDPLIncrementValue() to configure
+    the increment of HDPL sent to SAES.
+
+      (+) Call the function HAL_BSEC_GetSAESHDPLIncrementValue() to get the SAES
+    increment to HDPL.
+
+         *** Scratch register management ***
+    ============================================================
+    [..]
+
+      (+) Call the function HAL_BSEC_WriteScratchValue() to write a value in
+    write once scratch or scratch register.
+
+      (+) Call the function HAL_BSEC_ReadScratchValue() to read a value from
+    write once scratch or scratch register.
+
+
+         *** Debug management ***
+    ============================================================
+    [..]
+
+      (+) Call the function HAL_BSEC_GetDebugRequest() to get the debug
+    request of host debugger.
+
+      (+) Call the function HAL_BSEC_SendJTAGData() to send data via JTAG.
+
+      (+) Call the function HAL_BSEC_ReceiveJTAGData() to receive data
+    via JTAG.
+
+      (+) Call the function HAL_BSEC_ConfigDebug() to configure the HDPL,
+    secure and non-secure authorization for debugger.
+
+      (+) Call the function HAL_BSEC_GetDebugConfig() to get the HDPL,
+    secure and non-secure authorization of debug.
+
+      (+) Call the function HAL_BSEC_LockDebug() to lock the debug.
+
+      (+) Call the function HAL_BSEC_UnlockDebug() to unlock the debug.
+
+      (+) Call the function HAL_BSEC_GetDebugLockState() to get the debug
+    lock status.
+
+         *** DHUK management ***
+    ============================================================
+        [..]
+
+      (+) Call the function HAL_BSEC_GetDHUKValidity() to get the validity
+    of DHUK.
+
+      (+) Call the function HAL_BSEC_LockDHUKUse() to lock the DHUK use.
+
+      (+) Call the function HAL_BSEC_GetDHUKLockStatus() to get the DHUK
+    lock status.
+
+         *** Reset counter ***
+    ============================================================
+        [..]
+
+      (+) Call the function HAL_BSEC_GetNumberOfResets() to get the number
+    of hot or warm resets.
+  @endverbatim
+
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined(HAL_BSEC_MODULE_ENABLED)
+
+/** @defgroup BSEC BSEC
+  * @brief BSEC HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup BSEC_Private_Constants BSEC Private Constants
+  * @{
+  */
+#define BSEC_HDPL_INCREMENT_CODE     0x60B166E7U
+#define BSEC_NB_FUSES                376U
+#define BSEC_LIMIT_UPPER_FUSES       256U
+#define BSEC_NB_SHADOW_REG           BSEC_NB_FUSES
+#define BSEC_NB_EPOCH_COUNTER        2U
+#define BSEC_NB_SCRATCH_REG          4U
+#define BSEC_NB_WOSCR_REG            8U
+#define BSEC_OTPSR_RELOAD_ERRORS     (BSEC_OTPSR_DISTURBF | BSEC_OTPSR_DEDF | BSEC_OTPSR_AMEF)
+#define BSEC_SHADOW_REG_WRITE_LIMIT  9U
+#define BSEC_TIMEOUT                 1000U
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup BSEC_Private_Functions BSEC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup BSEC_Exported_Functions BSEC Exported Functions
+  * @{
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group1 General configuration functions
+ *  @brief   General configuration functions
+ *
+@verbatim
+ ===============================================================================
+                ##### General configuration functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to perform global
+  configuration of BSEC.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the status of BSEC peripheral.
+  *
+  * @param  hbsec   BSEC handle
+  * @param  pStatus  Returned value of BSEC status. The returned value is @ref BSEC_Status
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetStatus(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+ if ((pStatus == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  *pStatus = (hbsec->Instance->OTPSR & (BSEC_OTPSR_INIT_DONE | BSEC_OTPSR_HIDEUP | BSEC_OTPSR_OTPNVIR));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the write to BSEC registers.
+  *
+  * @param  hbsec  BSEC handle
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GlobalLock(BSEC_HandleTypeDef *hbsec)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+  if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Set the value of global lock */
+  SET_BIT(hbsec->Instance->LOCKR, BSEC_LOCKR_GWLOCK);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the global write registers lock status.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  pStatus  Returned value of global lock status. The returned value is @ref BSEC_Global_Lock
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetGlobalLockStatus(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pStatus == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Get the global lock status */
+  *pStatus = (hbsec->Instance->LOCKR & BSEC_LOCKR_GWLOCK);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the error code of BSEC driver.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  pError  Returned value of error code. The returned value is @ref BSEC_Error_Code
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetErrorCode(BSEC_HandleTypeDef * hbsec, uint32_t *pError)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value */
+ if (pError == NULL)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  *pError = hbsec->ErrorCode;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group2 OTP fuse management functions
+ *  @brief   OTP fuse management functions
+ *
+@verbatim
+ ===============================================================================
+                  ##### OTP fuse management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the OTP fuses.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read OTP fuse value.
+  *
+  * @param  hbsec     BSEC handle
+  * @param  FuseId     Fuse to be read, this parameter value is between 0 and BSEC_NB_FUSES-1
+  * @param  pFuseData  Returned value of fuse. The returned value is between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_Read(BSEC_HandleTypeDef * hbsec, uint32_t FuseId, uint32_t *pFuseData)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+ if ((pFuseData == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (FuseId < BSEC_NB_FUSES)
+  {
+    /* Reload the data :
+       - Unshadowed fuse are not automatically reload and data no more available after register read
+       - Shadowed fuse contains by default the shadow value in the register */
+    if (HAL_BSEC_OTP_Reload(hbsec, FuseId) == HAL_OK)
+    {
+      /* Read data from shadow register */
+      *pFuseData = hbsec->Instance->FVRw[FuseId];
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Program an OTP fuse with or without permanent lock.
+  *
+  * @param  hbsec    BSEC handle
+  * @param  FuseId    Fuse to be written, this parameter value is between 0 and BSEC_NB_FUSES-1
+  * @param  FuseData  Data to be written in fuse, this parameter value is between 0 and 0xFFFFFFFFU
+  * @param  Lock      Permanent lock value, this parameter is @ref BSEC_Permanent_Lock
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_Program(BSEC_HandleTypeDef *hbsec, uint32_t FuseId, uint32_t FuseData, uint32_t Lock)
+{
+  uint32_t status_reg;
+  uint32_t status_bit;
+  uint32_t read_data;
+  uint32_t tick_start = HAL_GetTick();
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+ if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the permanent lock */
+  assert_param(IS_BSEC_PERMANENT_LOCK(Lock));
+
+  /* Get the correct register value */
+  if (FuseId < BSEC_NB_FUSES)
+  {
+    status_reg = FuseId / 32U;
+    status_bit = (uint32_t)(1UL << (FuseId % 32U));
+
+    if ((hbsec->Instance->SPLOCKx[status_reg] & status_bit) == 0U)
+    {
+      /* Write data in register */
+      hbsec->Instance->WDR = FuseData;
+
+      /* Perform a program of the fuse register */
+      MODIFY_REG(hbsec->Instance->OTPCR, (BSEC_OTPCR_PPLOCK | BSEC_OTPCR_PROG | BSEC_OTPCR_ADDR),
+                                         (FuseId | BSEC_OTPCR_PROG | Lock));
+
+      /* Wait the operation is finished */
+      while ((hbsec->Instance->OTPSR & BSEC_OTPSR_BUSY) != 0U)
+      {
+        if ((HAL_GetTick() - tick_start) > BSEC_TIMEOUT)
+        {
+          hbsec->ErrorCode = HAL_BSEC_ERROR_TIMEOUT;
+          return HAL_ERROR;
+        }
+      }
+
+      /* Check programming errors */
+      if ((hbsec->Instance->OTPSR & BSEC_OTPSR_PROGFAIL) != 0U)
+      {
+        hbsec->ErrorCode = HAL_BSEC_ERROR_PROGFAIL;
+        return HAL_ERROR;
+      }
+
+      /* Read back programmed data */
+      if (HAL_BSEC_OTP_Read(hbsec, FuseId, &read_data) == HAL_OK)
+      {
+        /* Verify programmed data */
+        if (read_data != FuseData)
+        {
+          hbsec->ErrorCode = HAL_BSEC_ERROR_PROGFAIL;
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Fuse is sticky programming locked */
+      hbsec->ErrorCode = HAL_BSEC_ERROR_LOCK;
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reload a OTP fuse value.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  FuseId  Fuse to be reload, this parameter value is between 0 and BSEC_NB_FUSES-1
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_Reload(BSEC_HandleTypeDef *hbsec, uint32_t FuseId)
+{
+  uint32_t status_reg;
+  uint32_t status_bit;
+  uint32_t tick_start = HAL_GetTick();
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+ if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (FuseId < BSEC_NB_FUSES)
+  {
+    status_reg = FuseId / 32U;
+    status_bit = (uint32_t)(1UL << (FuseId % 32U));
+
+    if ((hbsec->Instance->SRLOCKx[status_reg] & status_bit) == 0U)
+    {
+      /* Perform a reload of the fuse register */
+      MODIFY_REG(hbsec->Instance->OTPCR, (BSEC_OTPCR_PPLOCK | BSEC_OTPCR_PROG | BSEC_OTPCR_ADDR), FuseId);
+
+      /* Wait the operation is finished */
+      while ((hbsec->Instance->OTPSR & BSEC_OTPSR_BUSY) != 0U)
+      {
+        if ((HAL_GetTick() - tick_start) > BSEC_TIMEOUT)
+        {
+          hbsec->ErrorCode = HAL_BSEC_ERROR_TIMEOUT;
+          return HAL_ERROR;
+        }
+      }
+
+      if ((hbsec->Instance->OTPSR & BSEC_OTPSR_RELOAD_ERRORS) != 0U)
+      {
+        /* An error occurred during reloading, value can't be relied on */
+        hbsec->ErrorCode = (hbsec->Instance->OTPSR & BSEC_OTPSR_RELOAD_ERRORS);
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Shadow register is sticky reload locked */
+      hbsec->ErrorCode = HAL_BSEC_ERROR_LOCK;
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sticky lock an OTP fuse programming, writing shadowed register or reload.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  FuseId  Fuse to lock, this parameter value is between 0 and BSEC_NB_FUSES-1
+  * @param  Lock    Lock status of the fuse, this parameter is a combination of
+  *                   @ref HAL_BSEC_FUSE_PROG_LOCKED,
+  *                   @ref HAL_BSEC_FUSE_WRITE_LOCKED,
+  *                   @ref HAL_BSEC_FUSE_RELOAD_LOCKED
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_Lock(BSEC_HandleTypeDef *hbsec, uint32_t FuseId, uint32_t Lock)
+{
+  uint32_t status_reg;
+  uint32_t status_bit;
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+ if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the lock configuration */
+  assert_param(IS_BSEC_LOCK_CFG(Lock));
+
+  if (FuseId < BSEC_NB_FUSES)
+  {
+    status_reg = FuseId / 32U;
+    status_bit = (uint32_t)(1UL << (FuseId % 32U));
+
+    if ((Lock & HAL_BSEC_FUSE_PROG_LOCKED) != 0U)
+    {
+      /* Programming lock */
+      SET_BIT(hbsec->Instance->SPLOCKx[status_reg], status_bit);
+    }
+
+    if ((Lock & HAL_BSEC_FUSE_WRITE_LOCKED) != 0U)
+    {
+      /* Write lock */
+      SET_BIT(hbsec->Instance->SWLOCKx[status_reg], status_bit);
+    }
+
+    if ((Lock & HAL_BSEC_FUSE_RELOAD_LOCKED) != 0U)
+    {
+      /* Reload lock */
+      SET_BIT(hbsec->Instance->SRLOCKx[status_reg], status_bit);
+    }
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the sticky lock status (programming, writing shadowed register
+  *         or reload), the permanent lock status, the shadow configuration,
+  *         the ECC or hidden status of an OTP fuse.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  FuseId  Fuse to get the state, this parameter value is between 0 and BSEC_NB_FUSES-1
+  * @param  pState  Returned value of state. The returned value is a combination of @ref BSEC_State
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_GetState(BSEC_HandleTypeDef * hbsec, uint32_t FuseId, uint32_t *pState)
+{
+  uint32_t status_reg;
+  uint32_t status_bit;
+  uint32_t otpsr_reg;
+  uint32_t state;
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+ if ((pState == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (FuseId < BSEC_NB_FUSES)
+  {
+    status_reg = FuseId / 32U;
+    status_bit = (uint32_t)(1UL << (FuseId % 32U));
+
+    /* Initialize return value */
+    state = 0U;
+
+    /* Check sticky programming lock */
+    if ((hbsec->Instance->SPLOCKx[status_reg] & status_bit) != 0U)
+    {
+      state |= HAL_BSEC_FUSE_PROG_LOCKED;
+    }
+
+    /* Check sticky write lock */
+    if ((hbsec->Instance->SWLOCKx[status_reg] & status_bit) != 0U)
+    {
+      state |= HAL_BSEC_FUSE_WRITE_LOCKED;
+    }
+
+    /* Check sticky reload lock */
+    if ((hbsec->Instance->SRLOCKx[status_reg] & status_bit) != 0U)
+    {
+      state |= HAL_BSEC_FUSE_RELOAD_LOCKED;
+    }
+    else
+    {
+      /* Check permanent lock : only in case of reload allowed as OTPSR reflect
+         status of most recently read word */
+      if (HAL_BSEC_OTP_Reload(hbsec, FuseId) == HAL_OK)
+      {
+        otpsr_reg = hbsec->Instance->OTPSR;
+
+        if ((otpsr_reg & BSEC_OTPSR_PPLF) != 0u)
+        {
+          /* Permanent programming lock detected */
+          state |= HAL_BSEC_FUSE_LOCKED;
+        }
+        else if ((otpsr_reg & BSEC_OTPSR_PPLMF) != 0U)
+        {
+          /* Permanent programming lock on the two lower fuse values in the array are not identical */
+          hbsec->ErrorCode = HAL_BSEC_ERROR_PPLM;
+          return HAL_ERROR;
+        }
+        else
+        {
+          /* No permanent programming lock detected */
+        }
+      }
+    }
+
+    /* Check shadow configuration */
+    if ((hbsec->Instance->SFSRx[status_reg] & status_bit) != 0U)
+    {
+      state |= HAL_BSEC_FUSE_SHADOWED;
+    }
+
+    /* Check hidden status */
+    if (((hbsec->Instance->OTPSR & BSEC_OTPSR_HIDEUP) != 0U) &&
+        (FuseId >= BSEC_LIMIT_UPPER_FUSES))
+    {
+      state |= HAL_BSEC_FUSE_HIDDEN;
+    }
+
+    /* Check ECC errors on all OTP fuses */
+    state |= (hbsec->Instance->OTPSR & (BSEC_OTPSR_OTPERR | BSEC_OTPSR_OTPSEC));
+
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+  *pState = state;
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group3 Shadow fuse register management functions
+ *  @brief   Shadow fuse register management functions
+ *
+@verbatim
+ ===============================================================================
+             ##### Shadow fuse register management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the
+  shadow fuse registers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the value of a shadow fuse register.
+  *
+  * @param  hbsec    BSEC handle
+  * @param  RegId     Shadow register to be read, this parameter value is between 0 and BSEC_NB_FUSES-1
+  * @param  pRegData  Returned value of register data. The returned value is between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_ReadShadow(BSEC_HandleTypeDef * hbsec, uint32_t RegId, uint32_t *pRegData)
+{
+  uint32_t status_reg;
+  uint32_t status_bit;
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pRegData == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (RegId < BSEC_NB_SHADOW_REG)
+  {
+    status_reg = RegId / 32U;
+    status_bit = (uint32_t)(1UL << (RegId % 32U));
+
+    if ((hbsec->Instance->SFSRx[status_reg] & status_bit) != 0U)
+    {
+      /* Read data from shadow register */
+      *pRegData = hbsec->Instance->FVRw[RegId];
+    }
+    else
+    {
+      /* Fuse is not shadowed */
+      hbsec->ErrorCode = HAL_BSEC_ERROR_UNALLOWED;
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write in a shadow fuse register.
+  *
+  * @param  hbsec    BSEC handle
+  * @param  RegId     Shadow register to be written, this parameter value is between 0 and BSEC_NB_FUSES-1
+  * @param  RegData   Data to be written in shadow register, this parameter value is between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_WriteShadow(BSEC_HandleTypeDef *hbsec, uint32_t RegId, uint32_t RegData)
+{
+  uint32_t status_reg;
+  uint32_t status_bit;
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+ if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Get the correct register value */
+  if ((RegId > BSEC_SHADOW_REG_WRITE_LIMIT) && (RegId < BSEC_NB_SHADOW_REG))
+  {
+    status_reg = RegId / 32U;
+    status_bit = (uint32_t)(1UL << (RegId % 32U));
+
+    if ((hbsec->Instance->SFSRx[status_reg] & status_bit) != 0U)
+    {
+      if ((hbsec->Instance->SWLOCKx[status_reg] & status_bit) == 0U)
+      {
+        /* Value is written in register */
+        hbsec->Instance->FVRw[RegId] = RegData;
+      }
+      else
+      {
+        /* Shadow register is sticky write locked */
+        hbsec->ErrorCode = HAL_BSEC_ERROR_LOCK;
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Fuse is not shadowed */
+      hbsec->ErrorCode = HAL_BSEC_ERROR_UNALLOWED;
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the validity status of a shadow register.
+  *
+  * @param  hbsec     BSEC handle
+  * @param  RegId      Shadow register to be checked, this parameter value is between 0 and BSEC_NB_FUSES-1
+  * @param  pValidity  Returned value of validity status. The returned value is @ref BSEC_Reload_Validity
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_OTP_GetShadowState(BSEC_HandleTypeDef * hbsec, uint32_t RegId, uint32_t *pValidity)
+{
+  uint32_t status_reg;
+  uint32_t status_bit;
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+ if ((pValidity == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (RegId < BSEC_NB_SHADOW_REG)
+  {
+    status_reg = RegId / 32U;
+    status_bit = (uint32_t)(1UL << (RegId % 32U));
+
+    if ((hbsec->Instance->SFSRx[status_reg] & status_bit) != 0U)
+    {
+      if ((hbsec->Instance->OTPVLDRx[status_reg] & status_bit) != 0U)
+      {
+        *pValidity = HAL_BSEC_RELOAD_DONE;
+      }
+      else
+      {
+        *pValidity = HAL_BSEC_RELOAD_ERROR;
+      }
+    }
+    else
+    {
+      /* Fuse is not shadowed */
+      hbsec->ErrorCode = HAL_BSEC_ERROR_UNALLOWED;
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group4 Device lifecycle management functions
+ *  @brief   Device lifecycle management functions
+ *
+@verbatim
+ ===============================================================================
+               ##### Device lifecycle management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the
+  device lifecycle.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the BSEC device lifecycle state.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  pState  Returned value of device lifecycle state. The returned value is @ref BSEC_Lifecycle_State
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDeviceLifeCycleState(BSEC_HandleTypeDef * hbsec, uint32_t *pState)
+{
+
+  uint32_t state;
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+ if ((pState == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Return the state */
+  state = (hbsec->Instance->SR & BSEC_SR_NVSTATE);
+
+  if (IS_BSEC_STATE(state))
+  {
+    *pState = state;
+    return HAL_OK;
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_UNDEFINED_VALUE;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Read the value of epoch counter.
+  *
+  * @param  hbsec        BSEC handle
+  * @param  CounterId     Identifier of the epoch counter to be read, this parameter can be @ref BSEC_Epoch_Select
+  * @param  pCounterData  Returned value of epoch counter data. The returned value is between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_ReadEpochCounter(BSEC_HandleTypeDef * hbsec, uint32_t CounterId, uint32_t *pCounterData)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+ if ((pCounterData == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Get the correct register value */
+  if (CounterId < BSEC_NB_EPOCH_COUNTER)
+  {
+    *pCounterData = hbsec->Instance->EPOCHRx[CounterId];
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the epoch counter used by SAES.
+  *
+  * @param  hbsec            BSEC handle
+  * @param  SelectedCounter   Epoch selected counter, this parameter can be @ref BSEC_Epoch_Select
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_SelectEpochCounter(BSEC_HandleTypeDef *hbsec, uint32_t SelectedCounter)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+ if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the epoch counter selection */
+  assert_param(IS_BSEC_EPOCHSEL(SelectedCounter));
+
+  /* Update the selected epoch counter value */
+  MODIFY_REG(hbsec->Instance->EPOCHSELR, BSEC_EPOCHSELR_EPSEL, SelectedCounter);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the epoch counter selection for SAES.
+  *
+  * @param  hbsec            BSEC handle
+  * @param  pSelectedCounter  Returned value of epoch selected counter. The returned value is @ref BSEC_Epoch_Select
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetEpochCounterSelection(BSEC_HandleTypeDef * hbsec, uint32_t *pSelectedCounter)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pSelectedCounter == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Return the debug request */
+  *pSelectedCounter = (hbsec->Instance->EPOCHSELR & BSEC_EPOCHSELR_EPSEL);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group5 HDPL management functions
+ *  @brief   HDPL management functions
+ *
+@verbatim
+ ===============================================================================
+                     ##### HDPL management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the
+  HDPL (Hide Protection Level).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the current HDPL.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  pHDPL   Returned value of current HDPL. The returned value is @ref BSEC_HDPL
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetHDPLValue(BSEC_HandleTypeDef * hbsec, uint32_t *pHDPL)
+{
+
+  uint32_t hdpl;
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pHDPL == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Return the HDPL */
+  hdpl = (hbsec->Instance->HDPLSR & BSEC_HDPLSR_HDPL);
+
+  if (IS_BSEC_HDPL(hdpl))
+  {
+    *pHDPL = hdpl;
+    return HAL_OK;
+  }
+  else
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_UNDEFINED_VALUE;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Increment the HDPL.
+  *
+  * @param  hbsec  BSEC handle
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_IncrementHDPLValue(BSEC_HandleTypeDef *hbsec)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+ if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Increment HDPL value */
+  hbsec->Instance->HDPLCR = BSEC_HDPL_INCREMENT_CODE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the increment of HDPL sent to SAES.
+  *
+  * @param  hbsec      BSEC handle
+  * @param  Increment   Value of HDPL increment, this parameter can be a value of @ref BSEC_INCR_HDPL
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_ConfigSAESHDPLIncrementValue(BSEC_HandleTypeDef *hbsec, uint32_t Increment)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+ if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the debug configuration */
+  assert_param(IS_BSEC_NEXTHDPL(Increment));
+
+  /* Write HDPL increment value */
+  MODIFY_REG(hbsec->Instance->NEXTLR, BSEC_NEXTLR_INCR, Increment);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the SAES increment to HDPL.
+  *
+  * @param  hbsec      BSEC handle
+  * @param  pIncrement  Returned value of HDPL increment. The returned value is a value of @ref BSEC_INCR_HDPL
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetSAESHDPLIncrementValue(BSEC_HandleTypeDef * hbsec, uint32_t *pIncrement)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pIncrement == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Return the debug request */
+  *pIncrement = (hbsec->Instance->NEXTLR & BSEC_NEXTLR_INCR);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group6 Scratch registers management functions
+ *  @brief   Scratch registers management functions
+ *
+@verbatim
+ ===============================================================================
+               ##### Scratch registers management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the
+  write once scratch and scratch registers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Write a value in write once scratch or scratch register.
+  *
+  * @param  hbsec     BSEC handle
+  * @param  pRegAddr  Register to be written
+  * @param  Value     Value to be written, this parameter can be a value between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_WriteScratchValue(BSEC_HandleTypeDef *hbsec, const BSEC_ScratchRegTypeDef *pRegAddr, uint32_t Value)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the register configuration and instance */
+ if ((pRegAddr == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the debug configuration */
+  assert_param(IS_BSEC_REGTYPE(pRegAddr->RegType));
+
+  /* Write data in correct register */
+  if (pRegAddr->RegType == HAL_BSEC_SCRATCH_REG)
+  {
+    if (pRegAddr->RegNumber < BSEC_NB_SCRATCH_REG)
+    {
+      hbsec->Instance->SCRATCHRx[pRegAddr->RegNumber] = Value;
+    }
+    else
+    {
+      hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if (pRegAddr->RegNumber < BSEC_NB_WOSCR_REG)
+    {
+      hbsec->Instance->WOSCRx[pRegAddr->RegNumber] = Value;
+    }
+    else
+    {
+      hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read a value from write once scratch or scratch register.
+  *
+  * @param  hbsec    BSEC handle
+  * @param  pRegAddr  Register to be read
+  * @param  pValue  Returned value of register data. The returned value is between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_ReadScratchValue(BSEC_HandleTypeDef * hbsec, const BSEC_ScratchRegTypeDef *pRegAddr, uint32_t *pValue)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the register configuration, address of returned value and instance */
+ if ((pRegAddr == NULL) || (pValue == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the debug configuration */
+  assert_param(IS_BSEC_REGTYPE(pRegAddr->RegType));
+
+  /* Get the correct register value */
+  if (pRegAddr->RegType == HAL_BSEC_SCRATCH_REG)
+  {
+    if (pRegAddr->RegNumber < BSEC_NB_SCRATCH_REG)
+    {
+      *pValue = hbsec->Instance->SCRATCHRx[pRegAddr->RegNumber];
+    }
+    else
+    {
+      hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if (pRegAddr->RegNumber < BSEC_NB_WOSCR_REG)
+    {
+      *pValue = hbsec->Instance->WOSCRx[pRegAddr->RegNumber];
+    }
+    else
+    {
+      hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group7 Debug management functions
+ *  @brief   Debug management functions
+ *
+@verbatim
+ ===============================================================================
+                   ##### Debug management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the
+  debug functionalities.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the debug request of host debugger.
+  *
+  * @param  hbsec   BSEC handle
+  * @param  pDbgReq  Returned value of debug request. The returned value is @ref BSEC_Debug_Req
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDebugRequest(BSEC_HandleTypeDef * hbsec, uint32_t *pDbgReq)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pDbgReq == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Return the debug request */
+  *pDbgReq = (hbsec->Instance->SR & BSEC_SR_DBGREQ);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Send data via JTAG.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  Data    Data to be sent via JTAG, this parameter can be a value between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_SendJTAGData(BSEC_HandleTypeDef *hbsec, uint32_t Data)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+  if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Send the data */
+  hbsec->Instance->JTAGOUTR = Data;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive data via JTAG.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  pData   Returned value of received data. The returned value is between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_ReceiveJTAGData(BSEC_HandleTypeDef * hbsec, uint32_t *pData)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pData == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Return the received data */
+  *pData = hbsec->Instance->JTAGINR;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the HDPL, secure and non-secure authorization
+  *         for debugger.
+  *
+  * @param  hbsec  BSEC handle
+  * @param  pCfg    Configuration of debug
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_ConfigDebug(BSEC_HandleTypeDef *hbsec, const BSEC_DebugCfgTypeDef *pCfg)
+{
+  uint32_t cfg_reg;
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the configuration pointer and instance */
+  if ((pCfg == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the debug configuration */
+  assert_param(IS_BSEC_OPENDBG(pCfg->HDPL_Open_Dbg));
+  assert_param(IS_BSEC_SECDBGAUTH(pCfg->Sec_Dbg_Auth));
+  assert_param(IS_BSEC_NSDBGAUTH(pCfg->NonSec_Dbg_Auth));
+
+  cfg_reg = ((pCfg->HDPL_Open_Dbg   & BSEC_DBGCR_AUTH_HDPL) \
+           | (pCfg->Sec_Dbg_Auth    & BSEC_DBGCR_AUTH_SEC)  \
+           | (pCfg->NonSec_Dbg_Auth & BSEC_DBGCR_UNLOCK));
+
+  hbsec->Instance->DBGCR = cfg_reg;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the HDPL, secure and non-secure authorization of debug.
+  *
+  * @param  hbsec   BSEC handle
+  * @param  pDbgCfg  Returned value of debug configuration
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDebugConfig(BSEC_HandleTypeDef * hbsec, BSEC_DebugCfgTypeDef *pDbgCfg)
+{
+  uint32_t cfg_reg;
+
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pDbgCfg == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Get the debug configuration */
+  cfg_reg = hbsec->Instance->DBGCR;
+  pDbgCfg->HDPL_Open_Dbg = (cfg_reg & BSEC_DBGCR_AUTH_HDPL);
+  pDbgCfg->Sec_Dbg_Auth = (cfg_reg & BSEC_DBGCR_AUTH_SEC);
+  pDbgCfg->NonSec_Dbg_Auth = (cfg_reg & BSEC_DBGCR_UNLOCK);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the debug.
+  *
+  * @param  hbsec  BSEC handle
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_LockDebug(BSEC_HandleTypeDef *hbsec)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+  if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Set the value of the debug lock */
+  MODIFY_REG(hbsec->Instance->AP_UNLOCK, BSEC_AP_UNLOCK_UNLOCK, HAL_BSEC_DEBUG_LOCKED);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the debug.
+  *
+  * @param  hbsec  BSEC handle
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_UnlockDebug(BSEC_HandleTypeDef *hbsec)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+  if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Set the value of the debug lock */
+  MODIFY_REG(hbsec->Instance->AP_UNLOCK, BSEC_AP_UNLOCK_UNLOCK, HAL_BSEC_DEBUG_UNLOCKED);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the debug lock status.
+  *
+  * @param  hbsec   BSEC handle
+  * @param  pStatus  Returned value of debug lock status. The returned value is @ref BSEC_Debug_Lock
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDebugLockState(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pStatus == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Get the debug lock status */
+  *pStatus = (hbsec->Instance->AP_UNLOCK & BSEC_AP_UNLOCK_UNLOCK);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group8 DHUK management functions
+ *  @brief   DHUK management functions
+ *
+@verbatim
+ ===============================================================================
+                    ##### DHUK management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the
+  DHUK (Derived Hardware Unique Key).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the validity of DHUK.
+  *
+  * @param  hbsec     BSEC handle
+  * @param  pValidity  Returned value of DHUK validity. The returned value is @ref BSEC_DHUK_Validity
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDHUKValidity(BSEC_HandleTypeDef * hbsec, uint32_t *pValidity)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pValidity == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Get the DHUK validity */
+  *pValidity = (hbsec->Instance->SR & BSEC_SR_HVALID);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the DHUK use.
+  *
+  * @param  hbsec  BSEC handle
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_LockDHUKUse(BSEC_HandleTypeDef *hbsec)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the instance */
+  if (hbsec->Instance != BSEC)
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Set the value of the DHUK lock */
+  SET_BIT(hbsec->Instance->LOCKR, BSEC_LOCKR_HKLOCK);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the DHUK lock status.
+  *
+  * @param  hbsec   BSEC handle
+  * @param  pStatus  Returned value of DHUK lock status. The returned value is @ref BSEC_DHUK_Lock
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetDHUKLockStatus(BSEC_HandleTypeDef * hbsec, uint32_t *pStatus)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pStatus == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Get the DHUK lock status */
+  *pStatus = (hbsec->Instance->LOCKR & BSEC_LOCKR_HKLOCK);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BSEC_Exported_Functions_Group9 Reset management functions
+ *  @brief   Reset management functions
+ *
+@verbatim
+ ===============================================================================
+                    ##### Reset management functions #####
+ ===============================================================================
+    [..]
+  This subsection provides a set of functions allowing to manage the reset.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the number of hot or warm resets.
+  *
+  * @param  hbsec        BSEC handle
+  * @param  ResetType     Type of the reset, this parameter can be a value of @ref BSEC_Reset_Type
+  * @param  pResetNumber  Returned value of number of reset. The returned value is between 0 and 0xFFFFFFFFU
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_BSEC_GetNumberOfResets(BSEC_HandleTypeDef * hbsec, uint32_t ResetType, uint32_t *pResetNumber)
+{
+  /* Check the handle pointer */
+  if (hbsec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address of returned value and instance */
+  if ((pResetNumber == NULL) || (hbsec->Instance != BSEC))
+  {
+    hbsec->ErrorCode = HAL_BSEC_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check the reset type */
+  assert_param(IS_BSEC_RESETTYPE(ResetType));
+
+  /* Get the correct register value */
+  if (ResetType == HAL_BSEC_HOT_RESET)
+  {
+    *pResetNumber = hbsec->Instance->HRCR;
+  }
+  else
+  {
+    *pResetNumber = hbsec->Instance->WRCR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* HAL_BSEC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cacheaxi.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cacheaxi.c
new file mode 100644
index 000000000..2e05acbd0
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cacheaxi.c
@@ -0,0 +1,1461 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cacheaxi.c
+  * @author  MCD Application Team
+  * @brief   CACHEAXI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CACHEAXI.
+  *           + Initialization and Configuration
+  *           + Cache coherency command
+  *           + Monitoring management
+  ******************************************************************************
+    * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+   (#) Configure and enable the MPU to override default config if needed, please refers to
+       ARM manual for default memory attribute. Then enable CACHEAXI with HAL_CACHEAXI_Init()
+       to cache memories data when accessed by a master peripheral through an AXI interconnect.
+
+    [..]
+        (+) Use HAL_CACHEAXI_Invalidate() to invalidate the full cache content:
+            (++) Cache content is lost, and reloaded when needed.
+            (++) Blocking call until operation is done.
+        (+) Use HAL_CACHEAXI_CleanByAddr() to clean cache content for a specific memory range:
+            (++) Cache content for specific range is written back to specific memory range.
+            (++) Used when buffer is updated by CPU before usage by a peripheral (typically DMA transfer)
+            (++) Blocking call until operation is done.
+        (+) Use HAL_CACHEAXI_CleanInvalidateByAddr() to clean and invalidate cache content for a specific memory range:
+            (++) Cache content for specific range is written back to specific memory range, and reloaded when needed.
+            (++) Recommended to use for MPU reprogramming.
+            (++) Blocking call until operation is done.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+        (+) Configure the CACHEAXI interrupt priority using HAL_NVIC_SetPriority()
+        (+) Enable the CACHEAXI IRQ handler using HAL_NVIC_EnableIRQ()
+        (+) Override weak definition for following callbacks (if needed):
+            (++)HAL_CACHEAXI_CleanAndInvalidateByAddrCallback()
+            (++)HAL_CACHEAXI_InvalidateCompleteCallback()
+            (++)HAL_CACHEAXI_CleanByAddrCallback()
+            (++)HAL_CACHEAXI_ErrorCallback()
+        (+) Use HAL_CACHEAXI_<COMMAND>_IT() to start a CACHEAXI operation with IT enabled.
+        (+) Use HAL_CACHEAXI_IRQHandler() called under CACHEAXIx_IRQHandler() Interrupt subroutine
+
+    [..]  Use HAL_CACHEAXI_GetState() function to return the CACHEAXI state and HAL_CACHEAXI_GetError()
+          in case of error detection.
+
+     *** CACHEAXI HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of macros defined in the CACHEAXI HAL driver.
+
+      (+) __HAL_CACHEAXI_ENABLE_IT    : Enable CACHEAXI interrupts.
+      (+) __HAL_CACHEAXI_DISABLE_IT   : Disable CACHEAXI interrupts.
+      (+) __HAL_CACHEAXI_GET_IT_SOURCE: Check whether the specified CACHEAXI interrupt source is enabled or not.
+      (+) __HAL_CACHEAXI_GET_FLAG     : Check whether the selected CACHEAXI flag is set or not.
+      (+) __HAL_CACHEAXI_CLEAR_FLAG   : Clear the selected CACHEAXI flags.
+
+     [..]
+      (@) You can refer to the header file of the CACHEAXI HAL driver for more useful macros.
+
+    [..]
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (CACHEAXI)
+/** @defgroup CACHEAXI CACHEAXI
+  * @brief HAL CACHEAXI module driver
+  * @{
+  */
+
+#ifdef HAL_CACHEAXI_MODULE_ENABLED
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup CACHEAXI_Private_Macros CACHEAXI Private Macros
+  * @{
+  */
+#define IS_CACHEAXI_REGION_SIZE(__SIZE__)                ((__SIZE__) > 0U)
+
+#define IS_CACHEAXI_MONITOR_TYPE(__TYPE__)               (((__TYPE__) & ~CACHEAXI_MONITOR_ALL) == 0U)
+
+#define IS_CACHEAXI_SINGLE_MONITOR_TYPE(__TYPE__)      (((__TYPE__) == CACHEAXI_MONITOR_READ_HIT)       || \
+                                                        ((__TYPE__) == CACHEAXI_MONITOR_READ_MISS)      || \
+                                                        ((__TYPE__) == CACHEAXI_MONITOR_WRITE_HIT)      || \
+                                                        ((__TYPE__) == CACHEAXI_MONITOR_WRITE_MISS)     || \
+                                                        ((__TYPE__) == CACHEAXI_MONITOR_READALLOC_MISS) || \
+                                                        ((__TYPE__) == CACHEAXI_MONITOR_WRITEALLOC_MISS)|| \
+                                                        ((__TYPE__) == CACHEAXI_MONITOR_WRITETHROUGH)   || \
+                                                        ((__TYPE__) == CACHEAXI_MONITOR_EVICTION))
+
+/**
+  * @}
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup CACHEAXI_Private_Constants CACHEAXI Private Constants
+  * @{
+  */
+#define CACHEAXI_COMMAND_TIMEOUT_VALUE           200U    /* 200ms*/
+#define CACHEAXI_ENABLE_TIMEOUT_VALUE            1U      /* 1ms  */
+#define CACHEAXI_DISABLE_TIMEOUT_VALUE           1U      /* 1ms  */
+
+#define CACHEAXI_COMMAND_CLEAN                   CACHEAXI_CR2_CACHECMD_0
+#define CACHEAXI_COMMAND_CLEAN_INVALIDATE        (CACHEAXI_CR2_CACHECMD_0|CACHEAXI_CR2_CACHECMD_1)
+
+#define CACHEAXI_POLLING_MODE                    0U
+#define CACHEAXI_IT_MODE                         1U
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef CACHEAXI_CommandByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t Command,
+                                                const uint32_t *pAddr, uint32_t dSize, uint32_t mode);
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CACHEAXI_Exported_Functions CACHEAXI Exported Functions
+  * @{
+  */
+
+/** @addtogroup CACHEAXI_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the CACHEAXIx peripheral:
+
+      (+) User must implement HAL_CACHEAXI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, MPU, IT and NVIC ).
+
+      (+) Call the function HAL_CACHEAXI_Init() to initialize the CACHEAXIx handle and
+          enable the CACHEAXI
+
+      (+) Call the function HAL_CACHEAXI_DeInit() to restore the reset configuration
+          of the selected CACHEAXIx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CACHEAXI handle and enables the CACHEAXI.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXI.
+  * @retval HAL status
+  * @note   In case HAL_CACHEAXI_Init() returns HAL_BUSY because an invalidation
+  *         procedure is ongoing, the application should call again HAL_CACHEAXI_Init()
+  *         until it returns HAL_OK to have the CACHEAXI enabled
+  */
+HAL_StatusTypeDef  HAL_CACHEAXI_Init(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the CACHEAXI handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  if (hcacheaxi->State == HAL_CACHEAXI_STATE_RESET)
+  {
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+    /* Init the CACHEAXI Callback settings with legacy weak */
+    hcacheaxi->ErrorCallback                      = HAL_CACHEAXI_ErrorCallback;
+    hcacheaxi->CleanByAddrCallback                = HAL_CACHEAXI_CleanByAddrCallback;
+    hcacheaxi->InvalidateCompleteCallback         = HAL_CACHEAXI_InvalidateCompleteCallback;
+    hcacheaxi->CleanAndInvalidateByAddrCallback   = HAL_CACHEAXI_CleanAndInvalidateByAddrCallback;
+
+    if (hcacheaxi->MspInitCallback == NULL)
+    {
+      hcacheaxi->MspInitCallback = HAL_CACHEAXI_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hcacheaxi->MspInitCallback(hcacheaxi);
+#else
+    /* Init the low level hardware */
+    HAL_CACHEAXI_MspInit(hcacheaxi);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+  }
+
+  /* Init the error code */
+  hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE;
+
+  /* Init the CACHEAXI handle state */
+  hcacheaxi->State = HAL_CACHEAXI_STATE_READY;
+
+  /* Enable the selected CACHEAXI peripheral */
+  status = HAL_CACHEAXI_Enable(hcacheaxi);
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the Data cache.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_DeInit(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /* Update the error code */
+  hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE;
+
+  /* Return to the reset state */
+  hcacheaxi->State = HAL_CACHEAXI_STATE_RESET;
+
+  /* Disable cache */
+  status = HAL_CACHEAXI_Disable(hcacheaxi);
+
+  /* reset monitor values */
+  (void)HAL_CACHEAXI_Monitor_Reset(hcacheaxi, CACHEAXI_MONITOR_ALL);
+
+  /* Reset all remaining bit */
+  WRITE_REG(hcacheaxi->Instance->CR1, 0U);
+  WRITE_REG(hcacheaxi->Instance->CR2, 0U);
+  WRITE_REG(hcacheaxi->Instance->CMDRSADDRR, 0U);
+  WRITE_REG(hcacheaxi->Instance->CMDREADDRR, 0U);
+  WRITE_REG(hcacheaxi->Instance->FCR, 0U);
+  WRITE_REG(hcacheaxi->Instance->IER, 0U);
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+  if (hcacheaxi->MspDeInitCallback == NULL)
+  {
+    hcacheaxi->MspDeInitCallback = HAL_CACHEAXI_MspDeInit;
+  }
+
+  /* DeInitialize the low level hardware */
+  hcacheaxi->MspDeInitCallback(hcacheaxi);
+#else
+  /* DeInitialize the low level hardware */
+  HAL_CACHEAXI_MspDeInit(hcacheaxi);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+
+  return status;
+}
+
+/**
+  * @brief Initialize the CACHEAXI MSP.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval None
+  */
+__weak void HAL_CACHEAXI_MspInit(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcacheaxi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CACHEAXI_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the CACHEAXI MSP.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                 the configuration information for the specified CACHEAXIx peripheral.
+  * @retval None
+  */
+__weak void HAL_CACHEAXI_MspDeInit(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcacheaxi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CACHEAXI_MspDeInit can be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @addtogroup CACHEAXI_Exported_Functions_Group2
+  *
+@verbatim
+  ==============================================================================
+             ##### IO operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable CACHEAXI.
+      (+) Disable CACHEAXI.
+      (+) Invalidate the CACHEAXI.
+      (+) Invalidate the CACHEAXI with interrupt.
+      (+) Clean the CACHEAXI by Addr.
+      (+) Clean and Invalidate the CACHEAXI by Addr.
+      (+) Clean the CACHEAXI by Addr with interrupt.
+      (+) Clean and Invalidate the CACHEAXI by Addr with interrupt.
+      (+) Start the CACHEAXI performance monitoring.
+      (+) Stop the CACHEAXI performance monitoring.
+      (+) Reset the CACHEAXI performance monitoring values.
+      (+) Get the CACHEAXI performance Read Hit monitoring value.
+      (+) Get the CACHEAXI performance Read Miss monitoring value.
+      (+) Get the CACHEAXI performance Write Hit monitoring value.
+      (+) Get the CACHEAXI performance Write Miss monitoring value.
+      (+) Get the CACHEAXI performance Read Allocation Miss monitoring value.
+      (+) Get the CACHEAXI performance Write Allocation Miss monitoring value.
+      (+) Get the CACHEAXI performance Write Through monitoring value.
+      (+) Get the CACHEAXI performance Eviction monitoring value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Data cache.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Enable(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /* Check if ongoing full invalidation operation */
+  if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U)
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > CACHEAXI_ENABLE_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) == 0U)
+        {
+          /* Update error code */
+          hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT;
+          /* Return error status */
+          status =  HAL_ERROR;
+          break;
+        }
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE;
+    /* Enable the selected CACHEAXI peripheral */
+    SET_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_EN);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Disable the Data cache.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Disable(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  uint32_t tickstart;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /* Check CACHEAXI handle status */
+  if (HAL_CACHEAXI_IsEnabled(hcacheaxi) != 0U)
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE;
+
+    /* Change CACHEAXI handle state */
+    hcacheaxi->State = HAL_CACHEAXI_STATE_READY;
+
+    /* Disable the selected CACHEAXI peripheral */
+    CLEAR_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_EN);
+
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Wait for end of data cache disabling */
+    while (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > CACHEAXI_DISABLE_TIMEOUT_VALUE)
+      {
+        if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U)
+        {
+          /* Update error code */
+          hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT;
+
+          /* Change the CACHEAXI handle state */
+          hcacheaxi->State = HAL_CACHEAXI_STATE_READY;
+
+          /* Return error status */
+          status =  HAL_ERROR;
+          break;
+        }
+      }
+    }
+  }
+
+  return status;
+}
+/**
+  * @brief  Check whether the CACHEAXI is enabled or not.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval Status (0: disabled, 1: enabled)
+  */
+uint32_t HAL_CACHEAXI_IsEnabled(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  return ((READ_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_EN) != 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Invalidate the Data cache.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                 the configuration information for the specified CACHEAXIx peripheral.
+  * @note   This function waits for end of full cache invalidation
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Invalidate(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /* Check no ongoing operation */
+  if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U)
+  {
+    /* Return busy status */
+    status =  HAL_BUSY;
+  }
+  else
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE;
+
+    /* Change CACHEAXI Handle state */
+    hcacheaxi->State = HAL_CACHEAXI_STATE_READY;
+
+    /* Make sure flags are reset */
+    WRITE_REG(hcacheaxi->Instance->FCR, (CACHEAXI_FCR_CBSYENDF | CACHEAXI_FCR_CCMDENDF));
+
+    /* Set no operation on address range */
+    MODIFY_REG(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD, 0U);
+
+    /* Launch cache invalidation */
+    SET_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_CACHEINV);
+
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    /* Wait for end of cache invalidation */
+    while (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > CACHEAXI_COMMAND_TIMEOUT_VALUE)
+      {
+        if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_BUSYF) != 0U)
+        {
+          /* Update error code */
+          hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT;
+
+          /* Change the CACHEAXI state */
+          hcacheaxi->State = HAL_CACHEAXI_STATE_ERROR;
+
+          /* Return error status */
+          status =  HAL_ERROR;
+          break;
+        }
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Clean the Data cache by Addr.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  pAddr Start address of the region to be Cleaned
+  * @param  dSize Size of the region to be Cleaned (in bytes)
+  * @note   This function waits for end of cache Clean
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                           uint32_t dSize)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+  assert_param(IS_CACHEAXI_REGION_SIZE(dSize));
+
+  status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN, pAddr, dSize, CACHEAXI_POLLING_MODE);
+
+  return status;
+}
+
+/**
+  * @brief  Clean and Invalidate the Data cache by Addr.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  pAddr Start address of the region to be Cleaned and Invalidated
+  * @param  dSize Size of the region to be Cleaned and Invalidated (in bytes)
+  * @note   This function waits for end of cache Clean and Invalidation
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                                  uint32_t dSize)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+  assert_param(IS_CACHEAXI_REGION_SIZE(dSize));
+
+  status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, CACHEAXI_POLLING_MODE);
+
+  return status;
+}
+
+/**
+  * @brief  Invalidate the Data cache with interrupt.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   This function launches maintenance operation and returns immediately.
+  *         User application shall resort to interrupt generation to check
+  *         the end of operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Invalidate_IT(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /* Check no ongoing operation */
+  if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U)
+  {
+    /* Return busy status */
+    status =  HAL_BUSY;
+  }
+  else
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE;
+
+    /* Change CACHEAXI Handle state */
+    hcacheaxi->State = HAL_CACHEAXI_STATE_READY;
+
+    /* Make sure BSYENDF is reset */
+    WRITE_REG(hcacheaxi->Instance->FCR, (CACHEAXI_FCR_CBSYENDF | CACHEAXI_FCR_CCMDENDF));
+
+    /* Set no operation on address range for callback under interrupt */
+    MODIFY_REG(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD, 0U);
+
+    /* Enable end of cache invalidation interrupt */
+    SET_BIT(hcacheaxi->Instance->IER, CACHEAXI_IER_BSYENDIE);
+
+    /* Launch cache invalidation */
+    SET_BIT(hcacheaxi->Instance->CR1, CACHEAXI_CR1_CACHEINV);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Clean the Data cache by Addr with interrupt.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  pAddr Start address of the region to be Cleaned
+  * @param  dSize Size of the region to be Cleaned
+  * @note   This function launches maintenance operation and returns immediately.
+  *         User application shall resort to interrupt generation to check
+  *         the end of operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                              uint32_t dSize)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+  assert_param(IS_CACHEAXI_REGION_SIZE(dSize));
+
+  status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN, pAddr, dSize, CACHEAXI_IT_MODE);
+
+  return status;
+}
+
+/**
+  * @brief  Clean and Invalidate the Data cache by Addr with interrupt.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  pAddr Start address of the region to be Cleaned and Invalidated
+  * @param  dSize Size of the region to be Cleaned and Invalidated
+  * @note   This function launches maintenance operation and returns immediately.
+  *         User application shall resort to interrupt generation to check
+  *         the end of operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
+                                                     uint32_t dSize)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+  assert_param(IS_CACHEAXI_REGION_SIZE(dSize));
+
+  status = CACHEAXI_CommandByAddr(hcacheaxi, CACHEAXI_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, CACHEAXI_IT_MODE);
+
+  return status;
+}
+
+/**
+  * @brief  Start the CACHEAXI performance monitoring.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  MonitorType Monitoring type
+  *         This parameter can be a combination of the following values:
+  *            @arg CACHEAXI_MONITOR_READ_HIT
+  *            @arg CACHEAXI_MONITOR_READ_MISS
+  *            @arg CACHEAXI_MONITOR_WRITE_HIT
+  *            @arg CACHEAXI_MONITOR_WRITE_MISS
+  *            @arg CACHEAXI_MONITOR_READALLOC_MISS
+  *            @arg CACHEAXI_MONITOR_WRITEALLOC_MISS
+  *            @arg CACHEAXI_MONITOR_WRITETHROUGH
+  *            @arg CACHEAXI_MONITOR_EVICTION
+  *            @arg CACHEAXI_MONITOR_ALL
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Start(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType)
+{
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+  assert_param(IS_CACHEAXI_MONITOR_TYPE(MonitorType));
+
+  SET_BIT(hcacheaxi->Instance->CR1, MonitorType);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the CACHEAXI performance monitoring.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Stopping the monitoring does not reset the values.
+  * @param  MonitorType Monitoring type
+  *         This parameter can be a combination of the following values:
+  *            @arg CACHEAXI_MONITOR_READ_HIT
+  *            @arg CACHEAXI_MONITOR_READ_MISS
+  *            @arg CACHEAXI_MONITOR_WRITE_HIT
+  *            @arg CACHEAXI_MONITOR_WRITE_MISS
+  *            @arg CACHEAXI_MONITOR_READALLOC_MISS
+  *            @arg CACHEAXI_MONITOR_WRITEALLOC_MISS
+  *            @arg CACHEAXI_MONITOR_WRITETHROUGH
+  *            @arg CACHEAXI_MONITOR_EVICTION
+  *            @arg CACHEAXI_MONITOR_ALL
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Stop(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType)
+{
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+  assert_param(IS_CACHEAXI_MONITOR_TYPE(MonitorType));
+
+  CLEAR_BIT(hcacheaxi->Instance->CR1, MonitorType);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the CACHEAXI performance monitoring values.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  MonitorType Monitoring type
+  *         This parameter can be a combination of the following values:
+  *            @arg CACHEAXI_MONITOR_READ_HIT
+  *            @arg CACHEAXI_MONITOR_READ_MISS
+  *            @arg CACHEAXI_MONITOR_WRITE_HIT
+  *            @arg CACHEAXI_MONITOR_WRITE_MISS
+  *            @arg CACHEAXI_MONITOR_READALLOC_MISS
+  *            @arg CACHEAXI_MONITOR_WRITEALLOC_MISS
+  *            @arg CACHEAXI_MONITOR_WRITETHROUGH
+  *            @arg CACHEAXI_MONITOR_EVICTION
+  *            @arg CACHEAXI_MONITOR_ALL
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Reset(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType)
+{
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+  assert_param(IS_CACHEAXI_MONITOR_TYPE(MonitorType));
+
+  /* Force/Release reset */
+  SET_BIT(hcacheaxi->Instance->CR1, (MonitorType << 2U));
+  CLEAR_BIT(hcacheaxi->Instance->CR1, (MonitorType << 2U));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Read Hit monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 32-bit maximum value, monitor does not wrap.
+  * @retval Read Hit monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetReadHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the Read Hit monitor value*/
+  return hcacheaxi->Instance->RHMONR;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Read Miss monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 16-bit maximum value, monitor does not wrap.
+  * @retval Read Miss monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetReadMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the Read Miss monitor value*/
+  return hcacheaxi->Instance->RMMONR;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Write Hit monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 32-bit maximum value, monitor does not wrap.
+  * @retval Write Hit monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetWriteHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the Write Hit monitor value*/
+  return hcacheaxi->Instance->WHMONR;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Write Miss monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 16-bit maximum value, monitor does not wrap.
+  * @retval Write Miss monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetWriteMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the Write Miss monitor value*/
+  return hcacheaxi->Instance->WMMONR;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Read-allocate Miss monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 16-bit maximum value, monitor does not wrap.
+  * @retval Read-allocate Miss monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetReadAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the read-allocate Miss monitor value*/
+  return hcacheaxi->Instance->RAMMONR;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Write-allocate Miss monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 16-bit maximum value, monitor does not wrap.
+  * @retval Write-allocate Miss monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetWriteAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the write-allocate Miss monitor value*/
+  return hcacheaxi->Instance->WAMMONR;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Write-through monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 16-bit maximum value, monitor does not wrap.
+  * @retval Write-through monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetWriteThroughValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the Write-through monitor value*/
+  return hcacheaxi->Instance->WTMONR;
+}
+
+/**
+  * @brief  Get the CACHEAXI performance Eviction Miss monitoring value.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note   Upon reaching the 16-bit maximum value, monitor does not wrap.
+  * @retval Eviction monitoring value
+  */
+uint32_t HAL_CACHEAXI_Monitor_GetEvictionValue(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /*return the Eviction  monitor value*/
+  return hcacheaxi->Instance->EVIMONR;
+}
+
+/**
+  * @brief Handle the CACHEAXI interrupt request.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @note  This API should be called under the CACHEAXIx_IRQHandler().
+  * @retval None
+  */
+void HAL_CACHEAXI_IRQHandler(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  uint32_t itflags;
+  uint32_t itsources;
+
+  /* Check the parameters */
+  assert_param(IS_CACHEAXI_ALL_INSTANCE(hcacheaxi->Instance));
+
+  /* Get current interrupt flags and interrupt sources value */
+  itflags   = READ_REG(hcacheaxi->Instance->SR);
+  itsources = READ_REG(hcacheaxi->Instance->IER);
+
+  /* Check Data cache Error interrupt flag  */
+  if (((itflags & itsources) & CACHEAXI_FLAG_ERROR) != 0U)
+  {
+    /* Clear CACHEAXI error pending flag */
+    __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_ERROR);
+
+    /* Update data cache error code */
+    hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_EVICTION_CLEAN;
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+    /* Data cache error interrupt user callback */
+    hcacheaxi->ErrorCallback(hcacheaxi);
+#else
+    /* Data cache error interrupt user callback */
+    HAL_CACHEAXI_ErrorCallback(hcacheaxi);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+  }
+  /* Check for end of full invalidate operation */
+  if (READ_BIT(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD) == 0U)
+  {
+    /* Clear CACHEAXI busyend pending flag */
+    __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_BUSYEND);
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+    /* Data cache invalidate complete interrupt user callback */
+    hcacheaxi->InvalidateCompleteCallback(hcacheaxi);
+#else
+    /* Data cache invalidate complete interrupt user callback */
+    HAL_CACHEAXI_InvalidateCompleteCallback(hcacheaxi);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+  }
+
+  /* Check for end of clean and invalidate by address operation */
+  else if (READ_BIT(hcacheaxi->Instance->CR1, CACHEAXI_COMMAND_CLEAN_INVALIDATE) == \
+           (CACHEAXI_COMMAND_CLEAN_INVALIDATE))
+  {
+    /* Clear CACHEAXI cmdend pending flag */
+    __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_CMDEND);
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+    /* Data cache clean and invalidate range cmdend interrupt user callback */
+    hcacheaxi->CleanAndInvalidateByAddrCallback(hcacheaxi);
+#else
+    /* Data cache clean and invalidate range cmdend interrupt user callback */
+    HAL_CACHEAXI_CleanAndInvalidateByAddrCallback(hcacheaxi);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+  }
+
+  /* Check for end of clean by address operation */
+  else
+  {
+    /* Clear CACHEAXI cmdend pending flag */
+    __HAL_CACHEAXI_CLEAR_FLAG(hcacheaxi, CACHEAXI_FLAG_CMDEND);
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+    /* Data cache clean range cmdend interrupt user callback */
+    hcacheaxi->CleanByAddrCallback(hcacheaxi);
+#else
+    /* Data cache clean range cmdend interrupt user callback */
+    HAL_CACHEAXI_CleanByAddrCallback(hcacheaxi);
+#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+  }
+}
+
+#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User CACHEAXI Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_CACHEAXI_CLEAN_BY_ADDRESS_CB_ID Clean By Addr callback ID
+  *          @arg @ref HAL_CACHEAXI_INVALIDATE_BY_ADDRESS_CB_ID Invalidate By Addr callback ID
+  *          @arg @ref HAL_CACHEAXI_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID Clean and Invalidate By Addr callback ID
+  *          @arg @ref HAL_CACHEAXI_INVALIDATE_COMPLETE_CB_ID Invalidate Complete ID
+  *          @arg @ref HAL_CACHEAXI_ERROR_CB_ID  Error callback ID
+  *          @arg @ref HAL_CACHEAXI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_CACHEAXI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_RegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi,
+                                                HAL_CACHEAXI_CallbackIDTypeDef CallbackID,
+                                                pCACHEAXI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  if (hcacheaxi->State == HAL_CACHEAXI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CACHEAXI_CLEAN_BY_ADDRESS_CB_ID :
+        hcacheaxi->CleanByAddrCallback = pCallback;
+        break;
+
+      case HAL_CACHEAXI_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID :
+        hcacheaxi->CleanAndInvalidateByAddrCallback = pCallback;
+        break;
+
+      case HAL_CACHEAXI_INVALIDATE_COMPLETE_CB_ID :
+        hcacheaxi->InvalidateCompleteCallback = pCallback;
+        break;
+
+      case HAL_CACHEAXI_ERROR_CB_ID :
+        hcacheaxi->ErrorCallback = pCallback;
+        break;
+
+      case HAL_CACHEAXI_MSPINIT_CB_ID :
+        hcacheaxi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CACHEAXI_MSPDEINIT_CB_ID :
+        hcacheaxi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hcacheaxi->State == HAL_CACHEAXI_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CACHEAXI_MSPINIT_CB_ID :
+        hcacheaxi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CACHEAXI_MSPDEINIT_CB_ID :
+        hcacheaxi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an CACHEAXI Callback
+  *         CACHEAXI callback is redirected to the weak predefined callback
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_CACHEAXI_CLEAN_BY_ADDRESS_CB_ID Clean By Addr callback ID
+  *          @arg @ref HAL_CACHEAXI_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID Clean and Invalidate By Addr callback ID
+  *          @arg @ref HAL_CACHEAXI_INVALIDATE_COMPLETE_CB_ID Invalidate Complete callback ID
+  *          @arg @ref HAL_CACHEAXI_ERROR_CB_ID  Error callback ID
+  *          @arg @ref HAL_CACHEAXI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_CACHEAXI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CACHEAXI_UnRegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi,
+                                                  HAL_CACHEAXI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the cacheaxi handle allocation */
+  if (hcacheaxi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hcacheaxi->State == HAL_CACHEAXI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CACHEAXI_CLEAN_BY_ADDRESS_CB_ID :
+        /* Legacy weak Clean By Addr Callback */
+        hcacheaxi->CleanByAddrCallback = HAL_CACHEAXI_CleanByAddrCallback;
+        break;
+
+      case HAL_CACHEAXI_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID :
+        /* Legacy weak Clean and Invalidate By Addr Callback */
+        hcacheaxi->CleanAndInvalidateByAddrCallback = HAL_CACHEAXI_CleanAndInvalidateByAddrCallback;
+        break;
+
+      case HAL_CACHEAXI_INVALIDATE_COMPLETE_CB_ID :
+        /* Legacy weak Invalidate Complete Callback */
+        hcacheaxi->InvalidateCompleteCallback = HAL_CACHEAXI_InvalidateCompleteCallback;
+        break;
+
+      case HAL_CACHEAXI_ERROR_CB_ID :
+        /* Legacy weak ErrorCallback */
+        hcacheaxi->ErrorCallback = HAL_CACHEAXI_ErrorCallback;
+        break;
+
+      case HAL_CACHEAXI_MSPINIT_CB_ID :
+        /* Legacy weak MspInit */
+        hcacheaxi->MspInitCallback = HAL_CACHEAXI_MspInit;
+        break;
+
+      case HAL_CACHEAXI_MSPDEINIT_CB_ID :
+        /* Legacy weak MspDeInit */
+        hcacheaxi->MspDeInitCallback = HAL_CACHEAXI_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_CACHEAXI_STATE_RESET == hcacheaxi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CACHEAXI_MSPINIT_CB_ID :
+        /* Legacy weak MspInit */
+        hcacheaxi->MspInitCallback = HAL_CACHEAXI_MspInit;
+        break;
+
+      case HAL_CACHEAXI_MSPDEINIT_CB_ID :
+        /* Legacy weak MspDeInit */
+        hcacheaxi->MspDeInitCallback = HAL_CACHEAXI_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode |= HAL_CACHEAXI_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif  /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Cache clean  command  by address callback.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval None
+  */
+__weak void HAL_CACHEAXI_CleanByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcacheaxi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CACHEAXI_CleanByAddrCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Cache clean and Invalidate command  by address callback.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval None
+  */
+__weak void HAL_CACHEAXI_CleanAndInvalidateByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcacheaxi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CACHEAXI_CleanAndInvalidateByAddrCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Cache full invalidation complete callback.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval None
+  */
+__weak void HAL_CACHEAXI_InvalidateCompleteCallback(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcacheaxi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CACHEAXI_InvalidateCompleteCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval None
+  */
+__weak void HAL_CACHEAXI_ErrorCallback(CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcacheaxi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CACHEAXI_ErrorCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup CACHEAXI_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+            #####          Peripheral State          #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CACHEAXI handle state.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @retval HAL state
+  */
+HAL_CACHEAXI_StateTypeDef HAL_CACHEAXI_GetState(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Return CACHEAXI handle state */
+  return hcacheaxi->State;
+}
+
+/**
+  * @brief  Return the CACHEAXI error code
+  * @param  hcacheaxi pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXI.
+  * @retval CACHEAXI Error Code
+  */
+uint32_t HAL_CACHEAXI_GetError(const CACHEAXI_HandleTypeDef *hcacheaxi)
+{
+  /* Return CACHEAXI handle error code */
+  return hcacheaxi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup CACHEAXI_Private_Functions CACHEAXI Private Functions
+  * @brief    CACHEAXI Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Launch CACHEAXI command Clean, Invalidate or clean and invalidate by Addr.
+  * @param  hcacheaxi Pointer to a CACHEAXI_HandleTypeDef structure that contains
+  *                   the configuration information for the specified CACHEAXIx peripheral.
+  * @param  Command command to be applied for the CACHEAXI
+  *                       CACHEAXI_COMMAND_CLEAN, CACHEAXI_COMMAND_CLEAN_INVALIDATE
+  * @param  pAddr Start address of region to be Cleaned, Invalidated or Cleaned and Invalidated.
+  * @param  dSize Size of the region to be Cleaned, Invalidated or Cleaned and Invalidated (in bytes).
+  * @param  mode mode to be applied for the CACHEAXI
+  *                       CACHEAXI_IT_MODE, CACHEAXI_POLLING_MODE.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CACHEAXI_CommandByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t Command,
+                                                const uint32_t *pAddr, uint32_t dSize, uint32_t mode)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t op_addr = (uint32_t)pAddr;
+  uint32_t tickstart;
+
+  /* Check no ongoing operation */
+  if (READ_BIT(hcacheaxi->Instance->SR, (CACHEAXI_SR_BUSYF | CACHEAXI_SR_BUSYCMDF)) != 0U)
+  {
+    /* Return busy status */
+    status =  HAL_BUSY;
+  }
+  else
+  {
+    /* Update the error code */
+    hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_NONE;
+
+    /* Update the CACHEAXI handle State */
+    hcacheaxi->State = HAL_CACHEAXI_STATE_READY;
+
+    /* Make sure flags are reset */
+    WRITE_REG(hcacheaxi->Instance->FCR, (CACHEAXI_FCR_CBSYENDF | CACHEAXI_FCR_CCMDENDF));
+
+    /* Fill area start address */
+    WRITE_REG(hcacheaxi->Instance->CMDRSADDRR, op_addr);
+
+    /* Fill area end address */
+    WRITE_REG(hcacheaxi->Instance->CMDREADDRR, (op_addr + dSize - 1U));
+
+    /* Set command */
+    MODIFY_REG(hcacheaxi->Instance->CR2, CACHEAXI_CR2_CACHECMD, Command);
+
+    /* Enable IT if required */
+    if (mode == CACHEAXI_IT_MODE)
+    {
+      /* Enable end of cache command interrupt */
+      SET_BIT(hcacheaxi->Instance->IER, CACHEAXI_IER_CMDENDIE);
+
+      /* Launch cache command */
+      SET_BIT(hcacheaxi->Instance->CR2, CACHEAXI_CR2_STARTCMD);
+    }
+    else
+    {
+      /* Make sure that end of cache command interrupt is disabled */
+      CLEAR_BIT(hcacheaxi->Instance->IER, CACHEAXI_IER_CMDENDIE);
+
+      /* Launch cache command */
+      SET_BIT(hcacheaxi->Instance->CR2, CACHEAXI_CR2_STARTCMD);
+
+      /* Get timeout */
+      tickstart = HAL_GetTick();
+
+      /* Wait for end of cache command */
+      while (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_CMDENDF) == 0U)
+      {
+        if ((HAL_GetTick() - tickstart) > CACHEAXI_COMMAND_TIMEOUT_VALUE)
+        {
+          if (READ_BIT(hcacheaxi->Instance->SR, CACHEAXI_SR_CMDENDF) == 0U)
+          {
+            /* Update error code */
+            hcacheaxi->ErrorCode = HAL_CACHEAXI_ERROR_TIMEOUT;
+
+            /* Change the CACHEAXI state */
+            hcacheaxi->State = HAL_CACHEAXI_STATE_ERROR;
+
+            /* Return error status */
+            status =  HAL_ERROR;
+            break;
+          }
+        }
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CACHEAXI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* CACHEAXI */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cortex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cortex.c
new file mode 100644
index 000000000..7ab3f182a
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cortex.c
@@ -0,0 +1,786 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and Configuration functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M55 exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest pre-emption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure SysTick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32n6xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+    [..]
+    *** How to configure MPU (secure and non secure) using CORTEX HAL driver ***
+    ============================================================================
+    [..]
+    This section provides functions allowing to configure both secure and non-secure MPUs.
+
+    (#) Enable the MPU using HAL_MPU_Enable() function.
+    (#) Disable the MPU using HAL_MPU_Disable() function.
+    (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU.
+    (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU.
+    (#) Configure the MPU region using HAL_MPU_ConfigRegion()
+        and HAL_MPU_ConfigRegion_NS() to address the non secure MPU.
+    (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes()
+        and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU.
+
+    A device memory has the following attributes:
+    (#) G or nG: gathering or non-gathering. (multiple accesses to a device can be merged into a single
+    transaction except for operations with memory ordering semantics, for example, memory barrier
+    instructions, load acquire/store release).
+    (#) R or nR: reordering
+    (#) E or nE: early write acknowledge (similar to bufferable)
+
+    Only four combinations of these attributes are valid:
+    (#) device-nGnRnE: equivalent to Armv7-M strongly ordered memory type
+    (#) device-nGnRE: equivalent to Armv7-M device memory
+    (#) device-nGRE: new to Armv8-M
+    (#) device-GRE: new to Armv8-M
+
+    A normal memory has the following attributes:
+    (#) Cache Allocation attribute : set when a cache line is allocated (no allocation, read/write/read-write allocation)
+    (#) Cache write policy : write through (write to cache AND memory), write back (memory is written when the cache line is evicted)
+    (#) Transient : indicates that the region will be used for a short period of time
+    For normal memory, attributes can be set for inner and outer caches separately.
+    Note that outer attributes set to 0 change the memory to device mode. Both inner and outer attributes should be set for normal memory.
+
+    Sample configurations
+    (#) Inner-outer cacheable, write back, read-write allocate INNER_OUTER(MPU_RW_ALLOCATE | MPU_WRITE_BACK)
+    (#) Inner write back, read allocation, outer non-cacheable (MPU_R_ALLOCATE | MPU_WRITE_BACK) | OUTER(MPU_NOT_CACHEABLE)
+    For detail on memory attributes, refer to the ARMv8-m MPU documentation.
+
+    On STM32N6xx, the MPUs are split memory into regions (up to sixteen for both Secure and Non-Secure domains)
+    The secure MPU is only available when TrustZone is activated.
+
+    (#) Enable the MPU using HAL_MPU_Enable() function or HAL_MPU_Enable_NS function for non-secure MPU.
+    (#) Disable the MPU using HAL_MPU_Disable() function or HAL_MPU_Disable_NS function for non-secure MPU.
+    (#) Enable the MPU region using HAL_MPU_EnableRegion() function or HAL_MPU_EnableRegion_NS function for non-secure MPU region.
+    (#) Disable the MPU region using HAL_MPU_DisableRegion() function or HAL_MPU_DisableRegion_NS function for non-secure MPU region.
+    (#) Configure the MPU region using HAL_MPU_ConfigRegion() function or HAL_MPU_ConfigRegion_NS function
+        for non-secure MPU.
+    (#) Configure the MPU memory attributes using HAL_MPU_ConfigMemoryAttributes() function or
+        HAL_MPU_ConfigMemoryAttributes_NS function for non-secure MPU.
+
+    (#) The HAL_MPU_XXX_NS functions are only available when TrustZone is activated and CPU in secure state.
+        _NS functions are targeting non secure MPU, in any other cases APIs without NS shall be used.
+
+  @endverbatim
+  ******************************************************************************
+
+  The table below gives the allowed values of the pre-emption priority and subpriority according
+  to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+
+    ==========================================================================================================================
+      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+    ==========================================================================================================================
+     NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
+                           |                                   |                             | 4 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------
+     NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
+                           |                                   |                             | 3 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------
+     NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+                           |                                   |                             | 2 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------
+     NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+                           |                                   |                             | 1 bit for subpriority
+    --------------------------------------------------------------------------------------------------------------------------
+     NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
+                           |                                   |                             | 0 bit for subpriority
+    ==========================================================================================================================
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+  * @{
+  */
+static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_RegionInit);
+static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *pMPU_AttributesInit);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      SysTick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Set the priority grouping field (pre-emption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0  0 bit  for pre-emption priority,
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1  1 bit  for pre-emption priority,
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2  2 bits for pre-emption priority,
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3  3 bits for pre-emption priority,
+  *                                    1 bit  for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4  4 bits for pre-emption priority,
+  *                                    0 bit  for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Set the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @param  PreemptPriority The pre-emption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_INTERRUPT(IRQn));
+
+  prioritygroup = (NVIC_GetPriorityGrouping() & 0x7U);
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup));
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiate a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+  return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+  *  @brief   Cortex control functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Get the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0  0 bit for pre-emption priority,
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1  1 bit for pre-emption priority,
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2  2 bits for pre-emption priority,
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3  3 bits for pre-emption priority,
+  *                                      1 bit for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4  4 bits for pre-emption priority,
+  *                                      0 bit for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_INTERRUPT(IRQn));
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Set Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Get Pending Interrupt (read the pending register in the NVIC
+  *         and return the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clear the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Get active interrupt (read the active register in NVIC and return the active bit).
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer
+  *         to the appropriate CMSIS device file (stm32n6xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configure the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *         This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8 AHB clock divided by 8 selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+
+  MODIFY_REG(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk, CLKSource);
+}
+
+/**
+  * @brief  Handle SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Clear pending event(s).
+  * @retval None
+  */
+void HAL_CORTEX_ClearEvent(void)
+{
+  __SEV();
+  __WFE();
+}
+
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *                     NMI, FAULTMASK and privileged access to the default memory
+  *         This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB(); /* Force any outstanding transfers to complete before enabling MPU */
+
+  /* Enable the MPU */
+  MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Enable the non-secure MPU.
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
+  *                      NMI, FAULTMASK and privileged access to the default memory
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB(); /* Force any outstanding transfers to complete before enabling MPU */
+
+  /* Enable the MPU */
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+  /* Enable fault exceptions */
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Disable the MPU.
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Disable the MPU */
+  MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Disable the non-secure MPU.
+  * @retval None
+  */
+void HAL_MPU_Disable_NS(void)
+{
+  __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+  /* Disable fault exceptions */
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Disable the MPU */
+  MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Enable the MPU Region.
+  * @retval None
+  */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU->RNR = RegionNumber;
+
+  /* Enable the Region */
+  SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Enable the non-secure MPU Region.
+  * @retval None
+  */
+void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)
+{
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU_NS->RNR = RegionNumber;
+
+  /* Enable the Region */
+  SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Disable the MPU Region.
+  * @retval None
+  */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU->RNR = RegionNumber;
+
+  /* Disable the Region */
+  CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Disable the non-secure MPU Region.
+  * @retval None
+  */
+void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU_NS->RNR = RegionNumber;
+
+  /* Disable the Region */
+  CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+
+/**
+  * @brief  Initialize and configure the Region and the memory to be protected.
+  * @param  pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                         the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit)
+{
+  MPU_ConfigRegion(MPU, pMPU_RegionInit);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Initialize and configure the Region and the memory to be protected for non-secure MPU.
+  * @param  pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                         the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *pMPU_RegionInit)
+{
+  MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Initialize and configure the memory attributes.
+  * @param  pMPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains
+  *                             the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit)
+{
+  MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Initialize and configure the memory attributes for non-secure MPU.
+  * @param  pMPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains
+  *                             the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_AttributesInit)
+{
+  MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Private_Functions
+  * @{
+  */
+static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_RegionInit)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
+  assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
+
+  /* Set the Region number */
+  MPUx->RNR = pMPU_RegionInit->Number;
+
+  /* Disable the Region */
+  CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk);
+
+  /* Check the parameters */
+  assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
+  assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
+  assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
+  assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_RegionInit->AttributesIndex));
+
+  MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL)  |
+                ((uint32_t)pMPU_RegionInit->IsShareable      << MPU_RBAR_SH_Pos)  |
+                ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos)  |
+                ((uint32_t)pMPU_RegionInit->DisableExec      << MPU_RBAR_XN_Pos));
+
+  MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
+                ((uint32_t)pMPU_RegionInit->AttributesIndex  << MPU_RLAR_AttrIndx_Pos) |
+                ((uint32_t)pMPU_RegionInit->Enable           << MPU_RLAR_EN_Pos));
+}
+
+static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *pMPU_AttributesInit)
+{
+  __IO uint32_t *p_mair;
+  uint32_t      attr_values;
+  uint32_t      attr_number;
+
+  /* Check the parameters */
+  assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
+  /* No need to check Attributes value as all 0x0..0xFF possible */
+
+  if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
+  {
+    /* Program MPU_MAIR0 */
+    p_mair = &(MPUx->MAIR0);
+    attr_number = pMPU_AttributesInit->Number;
+  }
+  else
+  {
+    /* Program MPU_MAIR1 */
+    p_mair = &(MPUx->MAIR1);
+    attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
+  }
+
+  attr_values = *(p_mair);
+  attr_values &=  ~(0xFFU << (attr_number * 8U));
+  *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_crc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_crc.c
new file mode 100644
index 000000000..2c6558598
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_crc.c
@@ -0,0 +1,516 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_crc.c
+  * @author  MCD Application Team
+  * @brief   CRC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+         (+) Initialize CRC calculator
+             (++) specify generating polynomial (peripheral default or non-default one)
+             (++) specify initialization value (peripheral default or non-default one)
+             (++) specify input data format
+             (++) specify input or output data inversion mode if any
+         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+             input data buffer starting with the previously computed CRC as
+             initialization value
+         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+             input data buffer starting with the defined initialization value
+             (default or non-default) to initiate CRC calculation
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRC CRC
+  * @brief CRC HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+  * @{
+  */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRC according to the specified parameters
+          in the CRC_InitTypeDef and create the associated handle
+      (+) DeInitialize the CRC peripheral
+      (+) Initialize the CRC MSP (MCU Specific Package)
+      (+) DeInitialize the CRC MSP
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and create the associated handle.
+  * @param  hcrc CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if (hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  if (hcrc->State == HAL_CRC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcrc->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_CRC_MspInit(hcrc);
+  }
+
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* check whether or not non-default generating polynomial has been
+   * picked up by user */
+  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+  {
+    /* initialize peripheral with default generating polynomial */
+    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+  }
+  else
+  {
+    /* initialize CRC peripheral with generating polynomial defined by user */
+    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /* check whether or not non-default CRC initial value has been
+   * picked up by user */
+  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+  {
+    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+  }
+  else
+  {
+    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+  }
+
+
+  /* set input data inversion mode */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+  MODIFY_REG(hcrc->Instance->CR, (CRC_CR_RTYPE_IN | CRC_CR_REV_IN), hcrc->Init.InputDataInversionMode);
+
+  /* set output data inversion mode */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+  MODIFY_REG(hcrc->Instance->CR, (CRC_CR_RTYPE_OUT | CRC_CR_REV_OUT), hcrc->Init.OutputDataInversionMode);
+
+  /* makes sure the input data format (bytes, halfwords or words stream)
+   * is properly specified by user */
+  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the CRC peripheral.
+  * @param  hcrc CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if (hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  /* Check the CRC peripheral state */
+  if (hcrc->State == HAL_CRC_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Reset CRC calculation unit */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  /* Reset IDR register content */
+  CLEAR_REG(hcrc->Instance->IDR);
+
+  /* DeInit the low level hardware */
+  HAL_CRC_MspDeInit(hcrc);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRC MSP.
+  * @param  hcrc CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the CRC MSP.
+  * @param  hcrc CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief    management functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          using combination of the previous CRC value and the new one.
+
+       [..]  or
+
+      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          independently of the previous CRC value.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with the previously computed CRC as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the
+  *        handle field hcrc->InputDataFormat.
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:
+      /* Enter Data to the CRC calculator */
+      for (index = 0U; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+
+    case CRC_INPUTDATA_FORMAT_BYTES:
+      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+      break;
+
+    case CRC_INPUTDATA_FORMAT_HALFWORDS:
+      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
+      break;
+    default:
+      break;
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return the CRC computed value */
+  return temp;
+}
+
+/**
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with hcrc->Instance->INIT as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the
+  *        handle field hcrc->InputDataFormat.
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+  *  written in hcrc->Instance->DR) */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:
+      /* Enter 32-bit input data to the CRC calculator */
+      for (index = 0U; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+
+    case CRC_INPUTDATA_FORMAT_BYTES:
+      /* Specific 8-bit input data handling  */
+      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+      break;
+
+    case CRC_INPUTDATA_FORMAT_HALFWORDS:
+      /* Specific 16-bit input data handling  */
+      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
+      break;
+
+    default:
+      break;
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return the CRC computed value */
+  return temp;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  *  @brief    Peripheral State functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CRC handle state.
+  * @param  hcrc CRC handle
+  * @retval HAL state
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
+{
+  /* Return CRC handle state */
+  return hcrc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enter 8-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer
+  * @param  BufferLength input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t i; /* input data buffer index */
+  uint16_t data;
+  __IO uint16_t *pReg;
+
+  /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+   * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+   * handling by the peripheral */
+  for (i = 0U; i < (BufferLength / 4U); i++)
+  {
+    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
+                         ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
+                         ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
+                         (uint32_t)pBuffer[(4U * i) + 3U];
+  }
+  /* last bytes specific handling */
+  if ((BufferLength % 4U) != 0U)
+  {
+    if ((BufferLength % 4U) == 1U)
+    {
+      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
+    }
+    if ((BufferLength % 4U) == 2U)
+    {
+      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
+      *pReg = data;
+    }
+    if ((BufferLength % 4U) == 3U)
+    {
+      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
+      *pReg = data;
+
+      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
+    }
+  }
+
+  /* Return the CRC computed value */
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @brief  Enter 16-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer
+  * @param  BufferLength input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t i;  /* input data buffer index */
+  __IO uint16_t *pReg;
+
+  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+   * a correct type handling by the peripheral */
+  for (i = 0U; i < (BufferLength / 2U); i++)
+  {
+    hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
+  }
+  if ((BufferLength % 2U) != 0U)
+  {
+    pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
+    *pReg = pBuffer[2U * i];
+  }
+
+  /* Return the CRC computed value */
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_crc_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_crc_ex.c
new file mode 100644
index 000000000..5ce043a38
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_crc_ex.c
@@ -0,0 +1,230 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_crc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended CRC HAL module driver.
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the CRC peripheral.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+================================================================================
+            ##### How to use this driver #####
+================================================================================
+    [..]
+         (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
+         (+) Configure Input or Output data inversion
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRCEx CRCEx
+  * @brief CRC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+  * @brief    Extended Initialization and Configuration functions.
+  *
+@verbatim
+ ===============================================================================
+            ##### Extended configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the generating polynomial
+      (+) Configure the input data inversion
+      (+) Configure the output data inversion
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initialize the CRC polynomial if different from default one.
+  * @param  hcrc CRC handle
+  * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
+  *         This parameter is written in normal representation, e.g.
+  *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+  * @param  PolyLength CRC polynomial length.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
+  *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
+  *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
+  *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+  /* Check the parameters */
+  assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+  /* Ensure that the generating polynomial is odd */
+  if ((Pol & (uint32_t)(0x1U)) ==  0U)
+  {
+    status =  HAL_ERROR;
+  }
+  else
+  {
+    /* check polynomial definition vs polynomial size:
+     * polynomial length must be aligned with polynomial
+     * definition. HAL_ERROR is reported if Pol degree is
+     * larger than that indicated by PolyLength.
+     * Look for MSB position: msb will contain the degree of
+     *  the second to the largest polynomial member. E.g., for
+     *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+    while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+    {
+    }
+
+    switch (PolyLength)
+    {
+
+      case CRC_POLYLENGTH_7B:
+        if (msb >= HAL_CRC_LENGTH_7B)
+        {
+          status =   HAL_ERROR;
+        }
+        break;
+      case CRC_POLYLENGTH_8B:
+        if (msb >= HAL_CRC_LENGTH_8B)
+        {
+          status =   HAL_ERROR;
+        }
+        break;
+      case CRC_POLYLENGTH_16B:
+        if (msb >= HAL_CRC_LENGTH_16B)
+        {
+          status =   HAL_ERROR;
+        }
+        break;
+
+      case CRC_POLYLENGTH_32B:
+        /* no polynomial definition vs. polynomial length issue possible */
+        break;
+      default:
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  if (status == HAL_OK)
+  {
+    /* set generating polynomial */
+    WRITE_REG(hcrc->Instance->POL, Pol);
+
+    /* set generating polynomial size */
+    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Set the Reverse Input data mode.
+  * @param  hcrc CRC handle
+  * @param  InputReverseMode Input Data inversion mode.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
+  *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
+  *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
+  *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+  /* Check the parameters */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set input data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Reverse Output data mode.
+  * @param  hcrc CRC handle
+  * @param  OutputReverseMode Output Data inversion mode.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
+  *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+  /* Check the parameters */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set output data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cryp.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cryp.c
new file mode 100644
index 000000000..85209f9a4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cryp.c
@@ -0,0 +1,8119 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cryp.c
+  * @author  MCD Application Team
+  * @brief   CRYP HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Cryptography (CRYP) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + AES processing functions
+  *           + DMA callback functions
+  *           + CRYP IRQ handler management
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The CRYP HAL driver can be used in CRYP IP as follows:
+
+      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
+         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
+         (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
+             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
+             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
+         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
+             (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
+             (+++) Configure and enable two DMA streams one for managing data transfer from
+                 memory to peripheral (input stream) and another stream for managing data
+                 transfer from peripheral to memory (output stream)
+             (+++) Associate the initialized DMA handle to the CRYP DMA handle
+                 using  __HAL_LINKDMA()
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                 interrupt on the two DMA Streams. The output stream should have higher
+                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+      (#)Initialize the CRYP according to the specified parameters :
+         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
+         (##) The key size: 128, 192 or 256.
+         (##) The AlgoMode AES Algorithm ECB/CBC/CTR/GCM or CCM.
+         (##) The initialization vector (counter). It is not used in ECB mode.
+         (##) The key buffer used for encryption/decryption.
+         (##) The Header used only in AES GCM and CCM Algorithm for authentication.
+         (##) The HeaderSize used to give size of header buffer in words or bytes, depending upon
+              HeaderWidthUnit field.
+         (##) The HeaderWidthUnit field. It specifies whether the header length
+         (##) The HeaderSize The size of header buffer in word.
+         (##) The B0 block is the first authentication block used only in AES CCM mode.
+
+      (#)Three processing (encryption/decryption) functions are available:
+         (##) Polling mode: encryption and decryption APIs are blocking functions
+              i.e. they process the data and wait till the processing is finished,
+              e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
+         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
+              i.e. they process the data under interrupt,
+              e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
+         (##) DMA mode: encryption and decryption APIs are not blocking functions
+              i.e. the data transfer is ensured by DMA,
+              e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
+
+      (#)When the processing function is called at first time after HAL_CRYP_Init()
+         the CRYP peripheral is configured and processes the buffer in input.
+         At second call, no need to Initialize the CRYP, user have to get current configuration via
+         HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
+         new parameters, finally user can  start encryption/decryption.
+
+       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+
+       (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
+          without having to configure again the Key or the Initialization Vector between each API call,
+          the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
+          Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(),
+          HAL_CRYP_Encrypt_DMA()or HAL_CRYP_Decrypt_DMA().
+
+    [..]
+      The cryptographic processor supports following standards:
+      (#) The advanced encryption standard (AES) supported by CRYP:
+         (##)128-bit data block processing
+         (##) chaining modes supported :
+             (+++)  Electronic Code Book(ECB)
+             (+++)  Cipher Block Chaining (CBC)
+             (+++)  Counter mode (CTR)
+             (+++)  Galois/counter mode (GCM/GMAC)
+             (+++)  Counter with Cipher Block Chaining-Message(CCM)
+         (##) keys length Supported :
+             (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
+
+    [..]  This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
+      (#)  Algorithm supported :
+         (##) Galois/counter mode (GCM)
+         (##) Galois message authentication code (GMAC) :is exactly the same as
+              GCM algorithm composed only by an header.
+      (#)  Four phases are performed in GCM :
+         (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
+         (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
+          computation only.
+         (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
+          encryption + data XORing. It works in a similar way for ciphertext (C).
+         (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+          HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond
+          to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits.
+      (#)  structure of message construction in GCM is defined as below  :
+         (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
+         (##) The authenticated header A (also knows as Additional Authentication Data AAD)
+          this part of the message is only authenticated, not encrypted.
+         (##) The plaintext message P is both authenticated and encrypted as ciphertext.
+          GCM standard specifies that ciphertext has same bit length as the plaintext.
+         (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
+          (on 64 bits)
+
+    [..]  This section describe The AES Counter with Cipher Block Chaining-Message
+          Authentication Code (CCM) supported by both CRYP IP:
+      (#)  Specific parameters for CCM  :
+
+         (##) B0 block  : According to NIST Special Publication 800-38C,
+            The first block B0 is formatted as follows, where l(m) is encoded in
+            most-significant-byte first order(see below table 3)
+
+              (+++)  Q: a bit string representation of the octet length of P (plaintext)
+              (+++)  q The octet length of the binary representation of the octet length of the payload
+              (+++)  A nonce (N), n The octet length of the where n+q=15.
+              (+++)  Flags: most significant octet containing four flags for control information,
+              (+++)  t The octet length of the MAC.
+         (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
+              the associated data length expressed in bytes (a) defined as below:
+            (+++)  If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
+            (+++)  If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
+            (+++)  If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
+         (##) CTRx block  : control blocks
+            (+++) Generation of CTR1 from first block B0 information :
+              equal to B0 with first 5 bits zeroed and most significant bits storing octet
+              length of P also zeroed, then incremented by one ( see below Table 4)
+            (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
+
+      (#)  Four phases are performed in CCM for CRYP IP:
+         (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
+         (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
+          computation only.
+         (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
+          encryption + data XORing. It works in a similar way for ciphertext (C).
+         (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+         HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
+         user should consider only part of this 4 words, if Tag length is less than 128 bits
+
+  *** Callback registration ***
+  =============================
+
+  [..]
+  The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  [..]
+  Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
+    (+) InCpltCallback     :  Input FIFO transfer completed callback.
+    (+) OutCpltCallback    : Output FIFO transfer completed callback.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : CRYP MspInit.
+    (+) MspDeInitCallback  : CRYP MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  [..]
+  Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) InCpltCallback     :  Input FIFO transfer completed callback.
+    (+) OutCpltCallback    : Output FIFO transfer completed callback.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : CRYP MspInit.
+    (+) MspDeInitCallback  : CRYP MspDeInit.
+
+  [..]
+  By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
+  all callbacks are set to the corresponding weak functions :
+  examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
+  keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+  [..]
+  Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
+  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+  in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
+  or @ref HAL_CRYP_Init() function.
+
+  [..]
+  When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+
+  Table 1. Initial Counter Block (ICB)
+          +-------------------------------------------------------+
+          |       Initialization vector (IV)      |  Counter      |
+          |----------------|----------------|-----------|---------|
+         127              95                63            31       0
+
+
+              Bit Number    Register           Contents
+              ----------   ---------------       -----------
+              127 ...96    CRYP_IV1R[31:0]     ICB[127:96]
+              95  ...64    CRYP_IV1L[31:0]     B0[95:64]
+              63 ... 32    CRYP_IV0R[31:0]     ICB[63:32]
+              31 ... 0     CRYP_IV0L[31:0]     ICB[31:0], where 32-bit counter= 0x2
+
+  Table 2.  GCM last block definition
+
+          +-------------------------------------------------------------------+
+          |  Bit[0]   |  Bit[32]           |  Bit[64]  | Bit[96]              |
+          |-----------|--------------------|-----------|----------------------|
+          |   0x0     | Header length[31:0]|     0x0   | Payload length[31:0] |
+          |-----------|--------------------|-----------|----------------------|
+
+  Table 3. B0 block
+                Octet Number   Contents
+                ------------   ---------
+                0              Flags
+                1 ... 15-q     Nonce N
+                16-q ... 15    Q
+
+            the Flags field is formatted as follows:
+
+                Bit Number   Contents
+                ----------   ----------------------
+                7            Reserved (always zero)
+                6            Adata
+                5 ... 3      (t-2)/2
+                2 ... 0      [q-1]3
+
+ Table 4. CTRx block
+                Bit Number    Register           Contents
+                ----------   ---------------       -----------
+                127 ...96    CRYP_IV1R[31:0]     B0[127:96], where Q length bits are set to 0, except for
+                                                 bit 0 that is set to 1
+                95  ...64    CRYP_IV1L[31:0]     B0[95:64]
+                63 ... 32    CRYP_IV0R[31:0]     B0[63:32]
+                31 ... 0     CRYP_IV0L[31:0]     B0[31:0], where flag bits set to 0
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (CRYP)
+
+/** @defgroup CRYP CRYP
+  * @brief CRYP HAL module driver.
+  * @{
+  */
+
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Defines
+  * @{
+  */
+#define CRYP_TIMEOUT_KEYPREPARATION      82U         /* The latency of key preparation operation is 82 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /* The latency of  GCM/CCM init phase to prepare hash subkey is 
+                                                        299 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /* The latency of  GCM/CCM header phase is 290 clock cycles.*/
+
+#define CRYP_GENERAL_TIMEOUT             500U
+
+#define  CRYP_PHASE_READY                0x00000001U /*!< CRYP peripheral is ready for initialization. */
+#define  CRYP_PHASE_PROCESS              0x00000002U /*!< CRYP peripheral is in processing phase */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+#define  CRYP_PHASE_HEADER_SUSPENDED     0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
+#define  CRYP_PHASE_PAYLOAD_SUSPENDED    0x00000005U /*!< GCM/CCM payload phase is suspended     */
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+#define  CRYP_PHASE_HEADER_DMA_FEED      0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in 
+                                                          DMA mode */
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+#define CRYP_PHASE_INIT                  0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER                CRYP_CR_GCM_CCMPH_0     /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD               CRYP_CR_GCM_CCMPH_1     /*!< GCM(/CCM) payload phase      */
+#define CRYP_PHASE_FINAL                 CRYP_CR_GCM_CCMPH       /*!< GCM/GMAC or CCM  final phase */
+#endif /* USE_HAL_CRYP_ONLY */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+#define SAES_PHASE_INIT                  0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
+#define SAES_PHASE_HEADER                SAES_CR_GCMPH_0         /*!< GCM/GMAC or CCM header phase */
+#define SAES_PHASE_PAYLOAD               SAES_CR_GCMPH_1         /*!< GCM(/CCM) payload phase      */
+#define SAES_PHASE_FINAL                 SAES_CR_GCMPH           /*!< GCM/GMAC or CCM  final phase */
+#endif /* USE_HAL_SAES_ONLY */
+
+/*  CTR1 information to use in CCM algorithm */
+#define CRYP_CCM_CTR1_0                  0x07FFFFFFU
+#define CRYP_CCM_CTR1_1                  0xFFFFFF00U
+#define CRYP_CCM_CTR1_2                  0x00000001U
+
+#define IT_SUSPENDED                     0x00000000U
+#define DMA_SUSPENDED                    0x00000001U
+
+#define ALGOMODE_CRYP_TO_CHMOD_SAES     0
+#define ALGOMODE_SAES_TO_CHMOD_CRYP     1
+/**
+  * @}
+  */
+
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Macros
+  * @{
+  */
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{MODIFY_REG(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR, \
+                                                             CRYP_CR_GCM_CCMPH, (__PHASE__));                \
+                                                                               }while(0)
+#endif /* USE_HAL_CRYP_ONLY */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+#define SAES_SET_PHASE(__HANDLE__, __PHASE__)  do{MODIFY_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
+                                                             SAES_CR_GCMPH, (__PHASE__));                    \
+                                                                               }while(0)
+#endif /* USE_HAL_SAES_ONLY */
+
+#define CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |=  CRYP_CR_FFLUSH)
+
+#define SAES_IP_RESET(__HANDLE__)   do { \
+                                         __IO uint32_t tmpreg; \
+                                         SET_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
+                                         /* Delay after an SAES peripheral IPRST */ \
+                                         tmpreg = READ_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
+                                         SAES_CR_IPRST); \
+                                         CLEAR_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
+                                         UNUSED(tmpreg); \
+                                          } while(0)
+
+/**
+  * @}
+  */
+
+/* Private struct -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions_prototypes
+  * @{
+  */
+
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#endif /* USE_HAL_CRYP_ONLY */
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#endif /* USE_HAL_SAES_ONLY */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output);
+static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input);
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm);
+#endif /* USE_HAL_CRYP_ONLY */
+static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm);
+static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order);
+#endif /* USE_HAL_SAES_ONLY */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    CRYP  Initialization and Configuration functions.
+  *
+@verbatim
+  ========================================================================================
+     ##### Initialization, de-initialization and Set and Get configuration functions #####
+  ========================================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRYP
+      (+) DeInitialize the CRYP
+      (+) Initialize the CRYP MSP
+      (+) DeInitialize the CRYP MSP
+      (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
+          Parameters which are configured in This section are :
+          (++) Key size
+          (++) Data Type : 32, 16, 8 or 1 bit
+                 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
+      (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
+
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the CRYP according to the specified
+  *         parameters in the CRYP_ConfigTypeDef and creates the associated handle.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check the CRYP handle allocation */
+  if (hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+#if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0))
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    return HAL_ERROR;
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+
+#if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1))
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    return HAL_ERROR;
+  }
+#endif /* USE_HAL_SAES_ONLY */
+
+  /* Check parameters */
+#ifdef USE_FULL_ASSERT
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+    assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
+    assert_param(IS_CRYP_KEYMODE(hcryp->Init.KeyMode));
+    if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
+    {
+      return HAL_ERROR; /* CRYP does not support BYTE as header width unit */
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    assert_param(IS_SAES_KEYSIZE(hcryp->Init.KeySize));
+    assert_param(IS_SAES_ALGORITHM(hcryp->Init.Algorithm));
+    assert_param(IS_SAES_KEYMODE(hcryp->Init.KeyMode));
+    assert_param(IS_SAES_KEYPROT(hcryp->Init.KeyProtection));
+    assert_param(IS_SAES_KEYSEL(hcryp->Init.KeySelect));
+  }
+#endif /* USE_HAL_SAES_ONLY */
+  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+  assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
+#endif /* USE_FULL_ASSERT */
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+  if (hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcryp->Lock = HAL_UNLOCKED;
+
+    hcryp->InCpltCallback  = HAL_CRYP_InCpltCallback;  /* Legacy InCpltCallback  */
+    hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy OutCpltCallback */
+    hcryp->ErrorCallback   = HAL_CRYP_ErrorCallback;   /* Legacy ErrorCallback   */
+
+    if (hcryp->MspInitCallback == NULL)
+    {
+      hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hcryp->MspInitCallback(hcryp);
+  }
+#else
+  if (hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcryp->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_CRYP_MspInit(hcryp);
+  }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+  /* Set the key size, data type and algorithm */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR,
+               CRYP_CR_KMOD | CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
+               hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    /* Reset of SAES */
+    SAES_IP_RESET(hcryp);
+
+    /* Wait for BUSY flag to go to 0 */
+    if (CRYP_WaitOnBUSYFlag(hcryp, CRYP_GENERAL_TIMEOUT) != HAL_OK)
+    {
+      /* Disable the CRYP peripheral clock */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Change state */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      return HAL_ERROR;
+    }
+
+    MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR,
+               SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_KEYPROT | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD,
+               hcryp->Init.KeySelect | hcryp->Init.KeyMode | hcryp->Init.KeyProtection | \
+               SAES_CONV_DATATYPE(hcryp->Init.DataType) | SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | \
+               CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm, ALGOMODE_CRYP_TO_CHMOD_SAES));
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+
+  /* Read Device ID to indicate CRYP1 IP Version */
+  hcryp->Version = HAL_GetREVID();
+
+  /* Reset Error Code field */
+  hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+  /* Reset peripheral Key and IV configuration flag */
+  hcryp->KeyIVConfig = 0U;
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* Set the default CRYP phase */
+  hcryp->Phase = CRYP_PHASE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the CRYP peripheral.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check the CRYP handle allocation */
+  if (hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+#if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0))
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    return HAL_ERROR;
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+
+#if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1))
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    return HAL_ERROR;
+  }
+#endif /* USE_HAL_SAES_ONLY */
+
+  /* Set the default CRYP phase */
+  hcryp->Phase = CRYP_PHASE_READY;
+
+  /* Reset CrypInCount and CrypOutCount */
+  hcryp->CrypInCount = 0;
+  hcryp->CrypOutCount = 0;
+  hcryp->CrypHeaderCount = 0;
+
+  /* Disable the CRYP peripheral clock */
+  __HAL_CRYP_DISABLE(hcryp);
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+  if (hcryp->MspDeInitCallback == NULL)
+  {
+    hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy MspDeInit  */
+  }
+  /* DeInit the low level hardware */
+  hcryp->MspDeInitCallback(hcryp);
+
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_CRYP_MspDeInit(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the CRYP according to the specified
+  *         parameters in the CRYP_ConfigTypeDef
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
+  * @param  pConf: pointer to a CRYP_ConfigTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
+  /* Check the CRYP handle allocation */
+  if ((hcryp == NULL) || (pConf == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+#ifdef USE_FULL_ASSERT
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
+    assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
+    assert_param(IS_CRYP_KEYMODE(pConf->KeyMode));
+    if (pConf->HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
+    {
+      return HAL_ERROR; /* CRYP does not support BYTE as header width unit */
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    assert_param(IS_SAES_KEYSIZE(pConf->KeySize));
+    assert_param(IS_SAES_ALGORITHM(pConf->Algorithm));
+    assert_param(IS_SAES_KEYMODE(pConf->KeyMode));
+    assert_param(IS_SAES_KEYPROT(hcryp->Init.KeyProtection));
+    assert_param(IS_SAES_KEYSEL(pConf->KeySelect));
+  }
+#endif /* USE_HAL_SAES_ONLY */
+  assert_param(IS_CRYP_DATATYPE(pConf->DataType));
+  assert_param(IS_CRYP_INIT(pConf->KeyIVConfigSkip));
+#endif /* USE_FULL_ASSERT */
+
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /* Set  CRYP parameters  */
+    hcryp->Init.DataType        = pConf->DataType;
+    hcryp->Init.pKey            = pConf->pKey;
+    hcryp->Init.Algorithm       = pConf->Algorithm;
+    hcryp->Init.KeySize         = pConf->KeySize;
+    hcryp->Init.pInitVect       = pConf->pInitVect;
+    hcryp->Init.Header          = pConf->Header;
+    hcryp->Init.HeaderSize      = pConf->HeaderSize;
+    hcryp->Init.B0              = pConf->B0;
+    hcryp->Init.DataWidthUnit   = pConf->DataWidthUnit;
+    hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
+    hcryp->Init.KeyMode         = pConf->KeyMode;
+    hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
+    hcryp->Init.KeySelect       = pConf->KeySelect;
+    hcryp->Init.KeyProtection   = pConf->KeyProtection;
+
+    /* Set the key size, data type, algo Mode and operating mode*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
+                 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /*in case of HSW, HW, SW or AHK key selection, we should specify Key mode selection (SAES_CR_KMOD) */
+      if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED))
+      {
+        /* Set key mode selection (Normal, Wrapped or Shared key )*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
+      }
+
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, \
+                 SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_KEYPROT | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD,
+                 hcryp->Init.KeySelect | hcryp->Init.KeyMode | hcryp->Init.KeyProtection | \
+                 SAES_CONV_DATATYPE(hcryp->Init.DataType) | SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | \
+                 CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm, ALGOMODE_CRYP_TO_CHMOD_SAES));
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Reset Error Code field */
+    hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Set the default CRYP phase */
+    hcryp->Phase = CRYP_PHASE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get CRYP Configuration parameters in associated handle.
+  * @param  pConf: pointer to a CRYP_ConfigTypeDef structure
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
+{
+  /* Check the CRYP handle allocation */
+  if ((hcryp == NULL) || (pConf == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /* Get  CRYP parameters  */
+    pConf->DataType        = hcryp->Init.DataType;
+    pConf->pKey            = hcryp->Init.pKey;
+    pConf->Algorithm       = hcryp->Init.Algorithm;
+    pConf->KeySize         = hcryp->Init.KeySize ;
+    pConf->pInitVect       = hcryp->Init.pInitVect;
+    pConf->Header          = hcryp->Init.Header ;
+    pConf->HeaderSize      = hcryp->Init.HeaderSize;
+    pConf->B0              = hcryp->Init.B0;
+    pConf->DataWidthUnit   = hcryp->Init.DataWidthUnit;
+    pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
+    pConf->KeyMode         = hcryp->Init.KeyMode;
+    pConf->KeySelect       = hcryp->Init.KeySelect;
+    hcryp->Init.KeyProtection   = pConf->KeyProtection;
+    pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+/**
+  * @brief  Initializes the CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes CRYP MSP.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User CRYP Callback
+  *         To be used instead of the weak predefined callback
+  * @param hcryp cryp handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
+  *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
+                                            pCRYP_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hcryp);
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+        hcryp->InCpltCallback = pCallback;
+        break;
+
+      case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+        hcryp->OutCpltCallback = pCallback;
+        break;
+
+      case HAL_CRYP_ERROR_CB_ID :
+        hcryp->ErrorCallback = pCallback;
+        break;
+
+      case HAL_CRYP_MSPINIT_CB_ID :
+        hcryp->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CRYP_MSPDEINIT_CB_ID :
+        hcryp->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CRYP_MSPINIT_CB_ID :
+        hcryp->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CRYP_MSPDEINIT_CB_ID :
+        hcryp->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an CRYP Callback
+  *         CRYP callback is redirected to the weak predefined callback
+  * @param hcryp cryp handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
+  *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hcryp);
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+        hcryp->InCpltCallback = HAL_CRYP_InCpltCallback;    /* Legacy InCpltCallback */
+        break;
+
+      case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+        hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback;  /* Legacy OutCpltCallback */
+        break;
+
+      case HAL_CRYP_ERROR_CB_ID :
+        hcryp->ErrorCallback = HAL_CRYP_ErrorCallback;      /* Legacy ErrorCallback */
+        break;
+
+      case HAL_CRYP_MSPINIT_CB_ID :
+        hcryp->MspInitCallback = HAL_CRYP_MspInit;
+        break;
+
+      case HAL_CRYP_MSPDEINIT_CB_ID :
+        hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CRYP_MSPINIT_CB_ID :
+        hcryp->MspInitCallback = HAL_CRYP_MspInit;
+        break;
+
+      case HAL_CRYP_MSPDEINIT_CB_ID :
+        hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+
+  return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+/**
+  * @brief  Request CRYP processing suspension when in interruption mode.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @note   Set the handle field SuspendRequest to the appropriate value so that
+  *         the on-going CRYP processing is suspended as soon as the required
+  *         conditions are met.
+  * @note   HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
+  *         in non-blocking interrupt mode.
+  * @retval None
+  */
+void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
+{
+  /* Set Handle SuspendRequest field */
+  hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
+}
+
+/**
+  * @brief  Request CRYP processing suspension when in DMA mode.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @note   Set the handle field SuspendRequest to the appropriate value so that
+  *         the on-going CRYP processing is suspended as soon as the required
+  *         conditions are met.
+  * @note   HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
+  *         in non-blocking DMA mode.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef *hcryp)
+{
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
+#endif /* USE_HAL_SAES_ONLY */
+  uint32_t tmp_remaining_DMATransferSize_inWords;
+  uint32_t tmp_initial_DMATransferSize_inWords;
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    /* Stop the DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in
+       the CRYP_DMACR register */
+    ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DIEN);
+
+    /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
+       CRYP_SR) and the BUSY bit is cleared */
+    while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM)
+    {
+      /* nothing todo */
+    }
+
+    /* Stop the DMA transfers from the OUT FIFO by clearing to 0 the DOEN
+      bit in the CRYP_DMACR register */
+    ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DOEN);
+
+    /* Disable the CRYP peripheral */
+    __HAL_CRYP_DISABLE(hcryp);
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    /* Stop the DMA transfer to the IN FIFO by clearing the DMAINEN bit of the SAES_CR register */
+    (((SAES_TypeDef *)(hcryp->Instance)))->CR &= (~SAES_CR_DMAINEN);
+
+    /* Wait for CCF flag to be raised */
+    if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+    {
+      /* Disable the CRYP peripheral clock */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Change state */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      /*Call registered error callback*/
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+      hcryp->ErrorCallback(hcryp);
+#else
+      /*Call legacy error callback*/
+      HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+    }
+
+    /* Stop the DMA transfer from the OUT FIFO by clearing the DMAOUTEN bit of the SAES_CR register */
+    ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_DMAOUTEN);
+
+    /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+  }
+#endif /* USE_HAL_SAES_ONLY */
+
+  /* At this point, DMA interface is disabled and no transfer is on-going */
+  /* Retrieve from the DMA handle how many words remain to be read and written */
+  /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */
+  tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CBR1) & \
+                                           DMA_CBR1_BNDT) / 4U;
+  tmp_remaining_DMATransferSize_inWords += ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CSR) & \
+                                            DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos;
+
+  /* Disable DMA channels */
+  /* Note that the Abort function will
+    - Clear the transfer error flags
+    - Unlock
+    - Set the State
+  */
+  if (HAL_DMA_Abort(hcryp->hdmain) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  if (HAL_DMA_Abort(hcryp->hdmaout) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Compute how many words were supposed to be transferred by DMA */
+  /* hcryp->CrypInCount is in bytes, must be a multiple of 4 (no padding handled for ECB or CBC) */
+  tmp_initial_DMATransferSize_inWords = ((uint32_t) hcryp->Size / 4U);
+
+  /* Accordingly, update the input and output pointers that points at the next word to be
+     transferred to the Peripheral by DMA or read from the Peripheral by the DMA */
+  hcryp->pCrypInBuffPtr  += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
+  hcryp->pCrypOutBuffPtr += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
+
+  /* And store in CrypInCount the remaining size to transfer (in words) */
+  hcryp->CrypInCount  = (uint16_t)tmp_remaining_DMATransferSize_inWords;
+  hcryp->CrypOutCount = (uint16_t)tmp_remaining_DMATransferSize_inWords;
+  hcryp->State =  HAL_CRYP_STATE_SUSPENDED;
+
+  return HAL_OK;
+
+}
+
+
+/**
+  * @brief  CRYP processing suspension and peripheral internal parameters storage.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @note   peripheral internal parameters are stored to be readily available when
+  *         suspended processing is resumed later on.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
+{
+  HAL_CRYP_STATETypeDef state;
+  uint32_t tmp_SAES_CR_DMAIN_bit;
+
+  /* Request suspension */
+  /* Check whether the processing is in DMA mode or not */
+  tmp_SAES_CR_DMAIN_bit = (((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_DMAINEN);
+  if ((((((CRYP_TypeDef *)(hcryp->Instance))->DMACR & CRYP_DMACR_DIEN) == CRYP_DMACR_DIEN) \
+       && (IS_CRYP_INSTANCE(hcryp->Instance))) || \
+      ((tmp_SAES_CR_DMAIN_bit == SAES_CR_DMAINEN) && (IS_SAES_INSTANCE(hcryp->Instance))))
+  {
+    if (HAL_CRYP_DMAProcessSuspend(hcryp) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+    hcryp->SuspendedProcessing = DMA_SUSPENDED;
+  }
+  else
+  {
+    HAL_CRYP_ProcessSuspend(hcryp);
+    hcryp->SuspendedProcessing = IT_SUSPENDED;
+  }
+
+  do
+  {
+    state = HAL_CRYP_GetState(hcryp);
+  } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
+
+  /* Make sure there is no unwanted suspension */
+  hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+  if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
+  {
+    /* Processing was already over or was about to end. No suspension done */
+    return HAL_ERROR;
+  }
+  else
+  {
+    if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+        (hcryp->Init.Algorithm == CRYP_AES_CTR) || \
+        (hcryp->Init.Algorithm == CRYP_AES_GCM) || \
+        (hcryp->Init.Algorithm == CRYP_AES_CCM))
+    {
+      /* Save Initialisation Vector registers */
+      CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
+    }
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Save Control register */
+      hcryp->CR_saved = ((CRYP_TypeDef *)(hcryp->Instance))->CR;
+
+      /* Save context swap registers */
+      if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
+      {
+        CRYP_Read_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm);
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Disable AES */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Clear keys */
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = 0x0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = 0x0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = 0x0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = 0x0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = 0x0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = 0x0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = 0x0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = 0x0U;
+
+      /* Save Control register */
+      hcryp->CR_saved = ((SAES_TypeDef *)(hcryp->Instance))->CR;
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Save low-priority block CRYP handle parameters */
+    hcryp->Init_saved              = hcryp->Init;
+    hcryp->pCrypInBuffPtr_saved    = hcryp->pCrypInBuffPtr;
+    hcryp->pCrypOutBuffPtr_saved   = hcryp->pCrypOutBuffPtr;
+    hcryp->CrypInCount_saved       = hcryp->CrypInCount;
+    hcryp->CrypOutCount_saved      = hcryp->CrypOutCount;
+    hcryp->Phase_saved             = hcryp->Phase;
+    hcryp->State_saved             = hcryp->State;
+    hcryp->Size_saved              = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \
+                                      (hcryp->Size / 4U) : hcryp->Size);
+    hcryp->SizesSum_saved          = hcryp->SizesSum;
+    hcryp->CrypHeaderCount_saved   = hcryp->CrypHeaderCount;
+    hcryp->SuspendRequest          = HAL_CRYP_SUSPEND_NONE;
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  CRYP processing resumption.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @note   Processing restarts at the exact point where it was suspended, based
+  *         on the parameters saved at suspension time.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
+{
+  /* Check the CRYP handle allocation */
+  if (hcryp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
+  {
+    /* CRYP was not suspended */
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Restore low-priority block CRYP handle parameters */
+    hcryp->Init            = hcryp->Init_saved;
+    hcryp->State           = hcryp->State_saved;
+    hcryp->Phase           = hcryp->Phase_saved;
+    hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
+
+    /* Restore low-priority block CRYP handle parameters */
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      hcryp->Init.pInitVect = hcryp->IV_saved;
+    }
+    /* Set State to reset to trigger a HAL_CRYP_MspInit() call in HAL_CRYP_Init() */
+    __HAL_CRYP_RESET_HANDLE_STATE(hcryp);
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      ((CRYP_TypeDef *)(hcryp->Instance))->CR |= CRYP_CR_IPRST;
+      ((CRYP_TypeDef *)(hcryp->Instance))->CR &= (~CRYP_CR_IPRST);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      ((SAES_TypeDef *)(hcryp->Instance))->CR |= SAES_CR_IPRST;
+      ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_IPRST);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Peripheral must be disabled */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || \
+        (hcryp->Init.Algorithm == CRYP_AES_CBC) || \
+        (hcryp->Init.Algorithm == CRYP_AES_CTR))
+    {
+      (void) HAL_CRYP_Init(hcryp);
+    }
+    else
+    {
+      /* The following lines are applicable to CRYP peripheral only */
+
+      /* Configure again the cryptographic processor with the initial setting in CRYP_CR */
+      ((CRYP_TypeDef *)(hcryp->Instance))->CR = hcryp->CR_saved;
+
+      /* Configure again the key registers */
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+      /* Restore context swap registers */
+      CRYP_Write_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm);
+
+      /* Restore IV registers */
+      CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
+
+      /* At the same time, set handle state back to READY to be able to resume the AES calculations
+      without the processing APIs returning HAL_BUSY when called. */
+      hcryp->State = HAL_CRYP_STATE_READY;
+    }
+
+    if (hcryp->SuspendedProcessing == DMA_SUSPENDED)
+    {
+      if (((IS_CRYP_INSTANCE(hcryp->Instance)) && \
+           (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \
+          ((IS_SAES_INSTANCE(hcryp->Instance)) && \
+           (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)))
+      {
+        if (HAL_CRYP_Encrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved,
+                                 hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        if (HAL_CRYP_Decrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved,
+                                 hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+    else
+    {
+      /* Resume low-priority block processing under IT */
+      hcryp->ResumingFlag = 1U;
+
+      if (((IS_CRYP_INSTANCE(hcryp->Instance)) &&
+           (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \
+          ((IS_SAES_INSTANCE(hcryp->Instance)) && \
+           (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)))
+      {
+        if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved,
+                                hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved,
+                                hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group2  Encrypt Decrypt functions
+  *  @brief   CRYP processing functions.
+  *
+@verbatim
+  ==============================================================================
+                      ##### Encrypt Decrypt  functions #####
+  ==============================================================================
+    [..]  This section provides API allowing to Encrypt/Decrypt Data following
+          Standard AES algorithm configured by the user:
+
+      (+) Standard AES  supported by CRYP1 IP, list of Algorithm supported:
+           (++) Electronic Code Book(ECB)
+           (++) Cipher Block Chaining (CBC)
+           (++) Counter mode (CTR)
+           (++) Cipher Block Chaining (CBC)
+           (++) Counter mode (CTR)
+           (++) Galois/counter mode (GCM)
+           (++) Counter with Cipher Block Chaining-Message(CCM)
+    [..]  Three processing functions are available:
+      (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
+      (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
+      (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Encryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the input buffer (plaintext)
+  * @param  Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit.
+  * @param  Output: Pointer to the output buffer(ciphertext)
+  * @param  Timeout: Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+                                   uint32_t Timeout)
+{
+  uint32_t algo = 0U;
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set Encryption operating mode*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+      /* algo get algorithm selected */
+      algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
+
+      /* algo get algorithm selected */
+      algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
+                                      ALGOMODE_SAES_TO_CHMOD_CRYP);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    switch (algo)
+    {
+      case CRYP_AES_ECB:
+      case CRYP_AES_CBC:
+      case CRYP_AES_CTR:
+
+        /* AES encryption */
+        status = CRYP_AES_Encrypt(hcryp, Timeout);
+        break;
+
+      case CRYP_AES_GCM:
+
+        /* AES GCM encryption */
+        status = CRYP_AESGCM_Process(hcryp, Timeout);
+        break;
+
+      case CRYP_AES_CCM:
+
+        /* AES CCM encryption */
+        status = CRYP_AESCCM_Process(hcryp, Timeout);
+        break;
+
+      default:
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status ;
+}
+
+/**
+  * @brief  Decryption mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the input buffer (ciphertext )
+  * @param  Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
+  * @param  Output: Pointer to the output buffer(plaintext)
+  * @param  Timeout: Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
+                                   uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t algo = 0U;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set Decryption operating mode*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+      /* algo get algorithm selected */
+      algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
+
+      /* algo get algorithm selected */
+      algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
+                                      ALGOMODE_SAES_TO_CHMOD_CRYP);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    switch (algo)
+    {
+      case CRYP_AES_ECB:
+      case CRYP_AES_CBC:
+      case CRYP_AES_CTR:
+
+        /* AES decryption */
+        status = CRYP_AES_Decrypt(hcryp, Timeout);
+        break;
+
+      case CRYP_AES_GCM:
+
+        /* AES GCM decryption */
+        status = CRYP_AESGCM_Process(hcryp, Timeout) ;
+        break;
+
+      case CRYP_AES_CCM:
+
+        /* AES CCM decryption */
+        status = CRYP_AESCCM_Process(hcryp, Timeout);
+        break;
+
+      default:
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Encryption in interrupt mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the input buffer (plaintext)
+  * @param  Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
+  * @param  Output: Pointer to the output buffer(ciphertext)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
+{
+  uint32_t algo = 0U;
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+    if (hcryp->ResumingFlag == 1U)
+    {
+      hcryp->ResumingFlag = 0U;
+      hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+      hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
+    }
+    else
+#endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
+    {
+      hcryp->CrypInCount = 0U;
+      hcryp->CrypOutCount = 0U;
+    }
+
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set encryption operating mode*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+      /* algo get algorithm selected */
+      algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
+
+      /* algo get algorithm selected */
+      algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
+                                      ALGOMODE_SAES_TO_CHMOD_CRYP);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    switch (algo)
+    {
+      case CRYP_AES_ECB:
+      case CRYP_AES_CBC:
+      case CRYP_AES_CTR:
+
+        status = CRYP_AES_Encrypt_IT(hcryp);
+        break;
+
+      case CRYP_AES_GCM:
+
+        status = CRYP_AESGCM_Process_IT(hcryp) ;
+        break;
+
+      case CRYP_AES_CCM:
+
+        status = CRYP_AESCCM_Process_IT(hcryp);
+        break;
+
+      default:
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status ;
+}
+
+/**
+  * @brief  Decryption in interrupt mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the input buffer (ciphertext )
+  * @param  Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
+  * @param  Output: Pointer to the output buffer(plaintext)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
+{
+  uint32_t algo = 0U;
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+    if (hcryp->ResumingFlag == 1U)
+    {
+      hcryp->ResumingFlag = 0U;
+      hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+      hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
+    }
+    else
+#endif  /* USE_HAL_CRYP_SUSPEND_RESUME */
+    {
+      hcryp->CrypInCount = 0U;
+      hcryp->CrypOutCount = 0U;
+    }
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set decryption operating mode*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+      /* algo get algorithm selected */
+      algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
+
+      /* algo get algorithm selected */
+      algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
+                                      ALGOMODE_SAES_TO_CHMOD_CRYP);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    switch (algo)
+    {
+      case CRYP_AES_ECB:
+      case CRYP_AES_CBC:
+      case CRYP_AES_CTR:
+
+        /* AES decryption */
+        status = CRYP_AES_Decrypt_IT(hcryp);
+        break;
+
+      case CRYP_AES_GCM:
+
+        /* AES GCM decryption */
+        status = CRYP_AESGCM_Process_IT(hcryp) ;
+        break;
+
+      case CRYP_AES_CCM:
+
+        /* AES CCMdecryption */
+        status = CRYP_AESCCM_Process_IT(hcryp);
+        break;
+
+      default:
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Encryption in DMA mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the input buffer (plaintext)
+  * @param  Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
+  * @param  Output: Pointer to the output buffer(ciphertext)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t algo = 0U;
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t tickstart;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set Encryption operating mode*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+      /* algo get algorithm selected */
+      algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
+
+      /* algo get algorithm selected */
+      algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
+                                      ALGOMODE_SAES_TO_CHMOD_CRYP);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    switch (algo)
+    {
+      case CRYP_AES_ECB:
+      case CRYP_AES_CBC:
+      case CRYP_AES_CTR:
+
+        if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+        {
+          if (hcryp->KeyIVConfig == 1U)
+          {
+            /* If the Key and IV configuration has to be done only once
+               and if it has already been done, skip it */
+            DoKeyIVConfig = 0U;
+          }
+          else
+          {
+            /* If the Key and IV configuration has to be done only once
+               and if it has not been done already, do it and set KeyIVConfig
+               to keep track it won't have to be done again next time */
+            hcryp->KeyIVConfig = 1U;
+          }
+        }
+
+        if (DoKeyIVConfig == 1U)
+        {
+          /* Set the Key */
+          if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+
+          /* Get tick */
+          tickstart = HAL_GetTick();
+
+          while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
+          {
+            /* Check for the Timeout */
+            if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
+            {
+              /* Disable the CRYP peripheral clock */
+              __HAL_CRYP_DISABLE(hcryp);
+
+              /* Change state */
+              hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+              hcryp->State = HAL_CRYP_STATE_READY;
+
+              /* Process unlocked */
+              __HAL_UNLOCK(hcryp);
+              return HAL_ERROR;
+            }
+          }
+
+          /* Set the Initialization Vector*/
+          if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+          {
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+            if (IS_CRYP_INSTANCE(hcryp->Instance))
+            {
+              ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+              ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+              ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+              ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+            }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+            if (IS_SAES_INSTANCE(hcryp->Instance))
+            {
+              ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+              ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+              ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+              ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+            }
+#endif /* USE_HAL_SAES_ONLY */
+          }
+
+        } /* if (DoKeyIVConfig == 1U) */
+
+        /* Set the phase */
+        hcryp->Phase = CRYP_PHASE_PROCESS;
+
+        /* Start DMA process transfer for AES */
+        CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
+        break;
+
+      case CRYP_AES_GCM:
+
+        /* AES GCM encryption */
+        status = CRYP_AESGCM_Process_DMA(hcryp);
+        break;
+
+      case CRYP_AES_CCM:
+
+        /* AES CCM encryption */
+        status = CRYP_AESCCM_Process_DMA(hcryp);
+        break;
+
+      default:
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status =  HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Decryption in DMA mode.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input: Pointer to the input buffer (ciphertext )
+  * @param  Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
+  * @param  Output: Pointer to the output buffer(plaintext)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
+{
+  uint32_t algo = 0U;
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set decryption operating mode*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+      /* algo get algorithm selected */
+      algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
+
+      /* algo get algorithm selected */
+      algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
+                                      ALGOMODE_SAES_TO_CHMOD_CRYP);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    switch (algo)
+    {
+      case CRYP_AES_ECB:
+      case CRYP_AES_CBC:
+      case CRYP_AES_CTR:
+
+        /* AES decryption */
+        status = CRYP_AES_Decrypt_DMA(hcryp);
+        break;
+
+      case CRYP_AES_GCM:
+
+        /* AES GCM decryption */
+        status = CRYP_AESGCM_Process_DMA(hcryp);
+
+        break;
+
+      case CRYP_AES_CCM:
+
+        /* AES CCM decryption */
+        status = CRYP_AESCCM_Process_DMA(hcryp);
+        break;
+
+      default:
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
+  *  @brief    CRYP IRQ handler.
+  *
+@verbatim
+  ==============================================================================
+                ##### CRYP IRQ handler management #####
+  ==============================================================================
+[..]  This section provides CRYP IRQ handler and callback functions.
+      (+) HAL_CRYP_IRQHandler CRYP interrupt request
+      (+) HAL_CRYP_InCpltCallback input data transfer complete callback
+      (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
+      (+) HAL_CRYP_ErrorCallback  CRYP error callback
+      (+) HAL_CRYP_GetState return the CRYP state
+      (+) HAL_CRYP_GetError return the CRYP error code
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles cryptographic interrupt request.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval None
+  */
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+{
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    uint32_t itstatus = ((CRYP_TypeDef *)(hcryp->Instance))->MISR;
+
+    if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
+    {
+      if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
+          || (hcryp->Init.Algorithm == CRYP_AES_CTR))
+      {
+        CRYP_AES_IT(hcryp); /*AES*/
+      }
+
+      else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
+      {
+        /* if header phase */
+        if ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
+        {
+          CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+        }
+        else  /* if payload phase */
+        {
+          CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    /* Check if Read or write error occurred */
+    if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET)
+    {
+      /* If write Error occurred */
+      if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET)
+      {
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
+      }
+      /* If read Error occurred */
+      if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET)
+      {
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
+      }
+      /*Call error callback*/
+      HAL_CRYP_ErrorCallback(hcryp);
+    }
+    /* Check if Key error occurred */
+    if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET)
+    {
+      if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET)
+      {
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY;
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF);
+        /*Call error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+      }
+    }
+    /* Check if RNG error occurred */
+    if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RNGEIE) != RESET)
+    {
+      if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RNGEIF) != RESET)
+      {
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_RNG;
+        /*Call error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RNGEIF);
+      }
+    }
+    if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
+    {
+      if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
+      {
+        /* Clear computation complete flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+        if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
+        {
+          /* if header phase */
+          if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_PHASE_HEADER) == SAES_PHASE_HEADER)
+          {
+            CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+          }
+          else  /* if payload phase */
+          {
+            CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+          }
+        }
+        else  /* AES Algorithm ECB,CBC or CTR*/
+        {
+          CRYP_AES_IT(hcryp);
+        }
+      }
+    }
+  }  /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+/**
+  * @brief  Return the CRYP error code.
+  * @param  hcryp : pointer to a CRYP_HandleTypeDef structure that contains
+  *                 the configuration information for the  CRYP IP
+  * @retval CRYP error code
+  */
+uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp)
+{
+  return hcryp->ErrorCode;
+}
+
+/**
+  * @brief  Returns the CRYP state.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval HAL state
+  */
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp)
+{
+  return hcryp->State;
+}
+
+/**
+  * @brief  Input FIFO transfer completed callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval None
+  */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_InCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output FIFO transfer completed callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval None
+  */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_OutCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  CRYP error callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval None
+  */
+__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_ErrorCallback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Encryption in ECB/CBC & CTR Algorithm with AES Standard
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
+  * @param  Timeout: specify Timeout value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t tickstart;
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /* Set the Key */
+    if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+    {
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    }
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED)
+      {
+        /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key.
+          The application can proceed with the processing of data, setting KMOD[1:0]to 00 */
+        CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD);
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_SAES_ONLY */
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+  /*Temporary CrypOutCount Value */
+  outcount = hcryp->CrypOutCount;
+
+  while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+  {
+    /* Write plain Ddta and get cipher data */
+    CRYP_AES_ProcessData(hcryp, Timeout);
+    /*Temporary CrypOutCount Value */
+    outcount = hcryp->CrypOutCount;
+  }
+
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t tickstart;
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /* Set the Key */
+    if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+    {
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    }
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED)
+      {
+        /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key.
+           The application can proceed with the processing of data, setting KMOD[1:0]to 00 */
+        CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD);
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_SAES_ONLY */
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  if (hcryp->Size != 0U)
+  {
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Write the input block in the IN FIFO */
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Enable interrupts */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+  }
+  else
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Decryption in ECB/CBC & CTR mode with AES Standard
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
+  * @param  Timeout: Specify Timeout value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Key preparation for ECB/CBC */
+    if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
+    {
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        /* change ALGOMODE to key preparation for decryption*/
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
+
+        /* Set the Key */
+        if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+        {
+          if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+        }
+
+        /* Enable CRYP */
+        __HAL_CRYP_ENABLE(hcryp);
+
+        /* Wait for BUSY flag go to 0 */
+        if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+        /* Turn back to ALGOMODE of the configuration */
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        /* When KMOD[1:0] = 01 (wrapped key) or  KMOD[1:0] = 01 (shared key)
+           and MODE[1:0] = 10 (decryption), then a read access to
+          SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
+        if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
+        {
+          MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
+        }
+        /* key preparation for decryption, operating mode 2*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
+
+        /* we should re-write Key, in the case where we change key after first operation*/
+        if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+        {
+          if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+        }
+
+        /* Enable SAES */
+        __HAL_CRYP_ENABLE(hcryp);
+
+        /* Wait for CCF flag to be raised */
+        if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state & update error code */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+        /*  End of Key preparation for ECB/CBC */
+        /* Return to decryption operating mode(Mode 3)*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
+      } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+    }
+    else  /*Algorithm CTR */
+    {
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        /* Set the Key */
+        if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+        {
+          if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+          else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+          {
+            ((CRYP_TypeDef *)(hcryp->Instance))->CR &=  ~CRYP_KEYMODE_SHARED;
+          }
+        }
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      }
+#endif /* USE_HAL_SAES_ONLY */
+    }
+
+    /* Set IV */
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_SAES_ONLY */
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+
+  /*Temporary CrypOutCount Value */
+  outcount = hcryp->CrypOutCount;
+
+  while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
+  {
+    /* Write plain data and get cipher data */
+    CRYP_AES_ProcessData(hcryp, Timeout);
+    /*Temporary CrypOutCount Value */
+    outcount = hcryp->CrypOutCount;
+  }
+
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Key preparation for ECB/CBC */
+    if (hcryp->Init.Algorithm != CRYP_AES_CTR)
+    {
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        /* change ALGOMODE to key preparation for decryption*/
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
+
+        /* Set the Key */
+        if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+        {
+          if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+          else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+          {
+            ((CRYP_TypeDef *)(hcryp->Instance))->CR &=  ~CRYP_KEYMODE_SHARED;
+          }
+        }
+
+        /* Enable CRYP */
+        __HAL_CRYP_ENABLE(hcryp);
+
+        /* Wait for BUSY flag go to 0 */
+        if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+
+        /* Turn back to ALGOMODE of the configuration */
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        /* When KMOD[1:0] = 01 (wrapped key) or  KMOD[1:0] = 01 (shared key)
+           and MODE[1:0] = 10 (decryption), then a read access to
+          SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
+        if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
+        {
+          MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
+        }
+        /* key preparation for decryption, operating mode 2*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
+
+        /* we should re-write Key, in the case where we change key after first operation*/
+        if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+        {
+          if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+        }
+
+        /* Enable SAES */
+        __HAL_CRYP_ENABLE(hcryp);
+
+        /* Wait for CCF flag to be raised */
+        if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state & update error code */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+        /*  End of Key preparation for ECB/CBC */
+        /* Return to decryption operating mode(Mode 3)*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
+      } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+    }
+    else  /*Algorithm CTR */
+    {
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        /* Set the Key */
+        if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+        {
+          if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+          else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+          {
+            ((CRYP_TypeDef *)(hcryp->Instance))->CR &=  ~CRYP_KEYMODE_SHARED;
+          }
+        }
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      }
+#endif /* USE_HAL_SAES_ONLY */
+    } /* if (hcryp->Init.Algorithm != CRYP_AES_CTR) */
+
+    /* Set IV */
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_SAES_ONLY */
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+  if (hcryp->Size != 0U)
+  {
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Write the input block in the IN FIFO */
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Enable interrupts */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
+    {
+      /*  Key preparation for ECB/CBC */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        /* change ALGOMODE to key preparation for decryption*/
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
+
+        /* Set the Key */
+        if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+        {
+          if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+          else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+          {
+            ((CRYP_TypeDef *)(hcryp->Instance))->CR &=  ~CRYP_KEYMODE_SHARED;
+          }
+        }
+
+        /* Enable CRYP */
+        __HAL_CRYP_ENABLE(hcryp);
+
+        /* Wait for BUSY flag go to 0 */
+        if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+        /* Turn back to ALGOMODE of the configuration */
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        /* When KMOD[1:0] = 01 (wrapped key) or  KMOD[1:0] = 01 (shared key)
+           and MODE[1:0] = 10 (decryption), then a read access to
+          SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
+        if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
+        {
+          MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
+        }
+        /* key preparation for decryption, operating mode 2*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
+
+        /* we should re-write Key, in the case where we change key after first operation*/
+        if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+        {
+          if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+        }
+
+        /* Enable SAES */
+        __HAL_CRYP_ENABLE(hcryp);
+
+        /* Wait for CCF flag to be raised */
+        if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state & update error code */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+        /*  End of Key preparation for ECB/CBC */
+        /* Return to decryption operating mode(Mode 3) */
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
+
+      } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+    }
+    else  /*Algorithm CTR */
+    {
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        /* Set the Key */
+        if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+        {
+          if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+          {
+            CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+          }
+          else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+          {
+            ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
+          }
+        }
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      }
+#endif /* USE_HAL_SAES_ONLY */
+    }
+
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+      if (IS_CRYP_INSTANCE(hcryp->Instance))
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+      if (IS_SAES_INSTANCE(hcryp->Instance))
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+        ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+      }
+#endif /* IS_SAES_INSTANCE */
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  if (hcryp->Size != 0U)
+  {
+    /* Start DMA process transfer for AES */
+    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA CRYP input data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+       in the DMACR register */
+    ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    /* Disable the DMA transfer for input FIFO request by resetting the DMAINEN bit
+       in the CR register */
+    ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAINEN);
+  }
+#endif /* USE_HAL_SAES_ONLY */
+
+  /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+  /*Call registered Input complete callback*/
+  hcryp->InCpltCallback(hcryp);
+#else
+  /*Call legacy Input complete callback*/
+  HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA CRYP output data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+  uint32_t count;
+  uint32_t npblb;
+  uint32_t lastwordsize;
+  uint32_t temp;            /* Temporary CrypOutBuff */
+  uint32_t mode;
+
+  CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+
+  /* Disable the DMA transfer for output FIFO */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAOUTEN);
+
+    /* Disable the DMA transfer for output FIFO request by resetting
+    the DOEN bit in the DMACR register */
+    CLEAR_BIT(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_DMAOUTEN);
+  }
+#endif /* USE_HAL_SAES_ONLY */
+
+  /* Last block transfer in case of GCM or CCM with Size not %16 */
+  /* Applicable to CRYP peripheral only */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    if (((hcryp->Size) % 16U) != 0U)
+    {
+      /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA  */
+      hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
+      hcryp->CrypOutCount = hcryp->CrypInCount;
+
+      /* Compute the number of padding bytes in last block of payload */
+      npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+      /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+      if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+          ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+      {
+        /* Disable the CRYP */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
+
+        /* Enable CRYP to start the final phase */
+        __HAL_CRYP_ENABLE(hcryp);
+      }
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+      /* Write the last input block in the IN FIFO */
+      for (count = 0U; count < lastwordsize; count ++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+      /* Pad the data with zeros to have a complete block */
+      while (count < 4U)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+        count++;
+      }
+      /* Wait for OFNE flag to be raised */
+      count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+      do
+      {
+        count-- ;
+        if (count == 0U)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+          /*Call registered error callback*/
+          hcryp->ErrorCallback(hcryp);
+#else
+          /*Call legacy error callback*/
+          HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+        }
+      } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE));
+
+      /*Read the output block from the output FIFO */
+      for (count = 0U; count < 4U; count++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+           temporary buffer */
+        temp = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+
+        *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+        hcryp->CrypOutCount++;
+      }
+    } /*End of last block transfer in case of GCM or CCM */
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    temp = 0;
+    /* Last block transfer in case of GCM or CCM with Size not %16*/
+    if (((hcryp->Size) % 16U) != 0U)
+    {
+      /* set CrypInCount and CrypOutCount to exact number of words already computed via DMA */
+      hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
+      hcryp->CrypOutCount = hcryp->CrypInCount;
+
+      /* Compute the number of padding bytes in last block of payload */
+      npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
+
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+      if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+          ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+      {
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
+      }
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /*  Last block optionally pad the data with zeros*/
+      for (count = 0U; count < lastwordsize; count++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+      while (count < 4U)
+      {
+        /* Pad the data with zeros to have a complete block */
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+        count++;
+      }
+
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+      /*Read the output block from the output FIFO */
+      for (count = 0U; count < 4U; count++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer
+           then get CrypOutBuff from temporary buffer */
+        temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+      }
+
+      count = 0U;
+      while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U))
+      {
+        *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+        hcryp->CrypOutCount++;
+        count++;
+      }
+    }
+  } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+
+  if (((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
+      && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
+  {
+    /* Disable CRYP  (not allowed in GCM) */
+    __HAL_CRYP_DISABLE(hcryp);
+  }
+
+  /* Change the CRYP state to ready */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcryp);
+
+  /* Call output data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+  /*Call registered Output complete callback*/
+  hcryp->OutCpltCallback(hcryp);
+#else
+  /*Call legacy Output complete callback*/
+  HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA CRYP communication error callback.
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the CRYP peripheral state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* DMA error code field */
+  hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+  /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+  /*Call registered error callback*/
+  hcryp->ErrorCallback(hcryp);
+#else
+  /*Call legacy error callback*/
+  HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Set the DMA configuration and start the DMA transfer
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  inputaddr: address of the input buffer
+  * @param  Size: size of the input buffer, must be a multiple of 16.
+  * @param  outputaddr: address of the output buffer
+  * @retval None
+  */
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+{
+  HAL_StatusTypeDef status;
+  uint32_t peripheral_in_address = 0U;
+  uint32_t peripheral_out_address = 0U;
+
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+  /* Set the DMA input error callback */
+  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+
+  /* Set the DMA output error callback */
+  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    peripheral_in_address  = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DIN;
+    peripheral_out_address = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    peripheral_in_address  = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DINR;
+    peripheral_out_address = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+  }
+#endif /* USE_HAL_SAES_ONLY */
+
+  /* Enable the DMA input channel */
+  if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL))
+    {
+      /* Enable the DMA channel */
+      hcryp->hdmain->LinkedListQueue->Head->\
+      LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */
+      hcryp->hdmain->LinkedListQueue->Head->\
+      LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */
+      hcryp->hdmain->LinkedListQueue->Head->\
+      LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = peripheral_in_address; /* Set DMA destination address */
+
+      status = HAL_DMAEx_List_Start_IT(hcryp->hdmain);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, peripheral_in_address, Size);
+  }
+
+  if (status != HAL_OK)
+  {
+    /* DMA error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+    /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
+
+  /* Enable the DMA output channel */
+  if ((hcryp->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if ((hcryp->hdmaout->LinkedListQueue != NULL) && (hcryp->hdmaout->LinkedListQueue->Head != NULL))
+    {
+      /* Enable the DMA channel */
+      hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = \
+          Size; /* Set DMA data size           */
+      hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+          peripheral_out_address;    /* Set DMA source address      */
+      hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
+          outputaddr;   /* Set DMA destination address */
+
+      status = HAL_DMAEx_List_Start_IT(hcryp->hdmaout);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hcryp->hdmaout, peripheral_out_address, outputaddr, Size);
+  }
+
+  if (status != HAL_OK)
+  {
+    /* DMA error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+    /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
+
+  /* Enable In/Out DMA request */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    ((CRYP_TypeDef *)(hcryp->Instance))->DMACR = (CRYP_DMACR_DOEN | CRYP_DMACR_DIEN);
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    ((SAES_TypeDef *)(hcryp->Instance))->CR |= (SAES_CR_DMAINEN | SAES_CR_DMAOUTEN);
+  }
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+/**
+  * @brief  Process Data: Write Input data in polling mode and used in AES functions.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Timeout: Specify Timeout value
+  * @retval None
+  */
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  uint16_t incount;  /* Temporary CrypInCount Value */
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+#endif /* USE_HAL_CRYP_ONLY */
+  uint32_t i;
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    /*Temporary CrypOutCount Value */
+    incount = hcryp->CrypInCount;
+
+    if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < ((hcryp->Size) / 4U)))
+    {
+      /* Write the input block in the IN FIFO */
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+      hcryp->CrypInCount++;
+    }
+
+    /* Wait for OFNE flag to be raised */
+    if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+    {
+      /* Disable the CRYP peripheral clock */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Change state & update error code */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+      /*Call registered error callback*/
+      hcryp->ErrorCallback(hcryp);
+#else
+      /*Call legacy error callback*/
+      HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+    }
+    /*Temporary CrypOutCount Value */
+    outcount = hcryp->CrypOutCount;
+
+    if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
+    {
+      /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from
+         temporary buffer  */
+      for (i = 0U; i < 4U; i++)
+      {
+        temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+      }
+      i = 0U;
+      while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+      {
+        *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+        hcryp->CrypOutCount++;
+        i++;
+      }
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    /* Write the input block in the IN FIFO */
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+
+    /* Wait for CCF flag to be raised */
+    if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+    {
+      /* Disable the CRYP peripheral clock */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Change state */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      /*Call registered error callback*/
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+      hcryp->ErrorCallback(hcryp);
+#else
+      /*Call legacy error callback*/
+      HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+    }
+
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+    /* Read the output block from the output FIFO and put them in temporary buffer then
+       get CrypOutBuff from temporary buffer*/
+    for (i = 0U; i < 4U; i++)
+    {
+      temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+    }
+    i = 0U;
+    while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+      hcryp->CrypOutCount++;
+      i++;
+    }
+  } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+/**
+  * @brief  Handle CRYP block input/output data handling under interruption.
+  * @note   The function is called under interruption only, once
+  *         interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval HAL status
+  */
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  uint16_t incount;  /* Temporary CrypInCount Value */
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+#endif /* USE_HAL_CRYP_ONLY */
+  uint32_t i;
+
+  if (hcryp->State == HAL_CRYP_STATE_BUSY)
+  {
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+      /* If suspension flag has been raised, suspend processing
+         only if not already at the end of the payload */
+      if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+      {
+        /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
+           CRYP_SR) and the BUSY bit is cleared */
+        while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \
+                                                             CRYP_SR_BUSY)) != CRYP_SR_IFEM)
+        {
+          /* Nothing to do */
+        }
+
+        /* Disable interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+        /* Disable CRYP */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* reset SuspendRequest */
+        hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+      }
+      else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+      {
+        /*Temporary CrypOutCount Value */
+        incount = hcryp->CrypInCount;
+
+        if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
+        {
+          /* Write the input block in the IN FIFO */
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          if (hcryp->CrypInCount == (hcryp->Size / 4U))
+          {
+            /* Disable interrupts */
+            __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+
+            /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+            /*Call registered Input complete callback*/
+            hcryp->InCpltCallback(hcryp);
+#else
+            /*Call legacy Input complete callback*/
+            HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+          }
+        }
+
+        /*Temporary CrypOutCount Value */
+        outcount = hcryp->CrypOutCount;
+
+        if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
+        {
+          /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+             temporary buffer  */
+          for (i = 0U; i < 4U; i++)
+          {
+            temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+          }
+          i = 0U;
+          while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+          {
+            *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+            hcryp->CrypOutCount++;
+            i++;
+          }
+          if (hcryp->CrypOutCount == (hcryp->Size / 4U))
+          {
+            /* Disable interrupts */
+            __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+
+            /* Change the CRYP state */
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Disable CRYP */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+
+            /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+            /*Call registered Output complete callback*/
+            hcryp->OutCpltCallback(hcryp);
+#else
+            /*Call legacy Output complete callback*/
+            HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+          }
+        }
+      } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Read the output block from the output FIFO and put them in temporary buffer then
+      get CrypOutBuff from temporary buffer*/
+      for (i = 0U; i < 4U; i++)
+      {
+        temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+      }
+      i = 0U;
+      while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+      {
+        *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+        hcryp->CrypOutCount++;
+        i++;
+      }
+      if (hcryp->CrypOutCount == (hcryp->Size / 4U))
+      {
+        /* Disable Computation Complete flag and errors interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Disable CRYP */
+        __HAL_CRYP_DISABLE(hcryp);
+        __HAL_UNLOCK(hcryp);
+
+        /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered Output complete callback*/
+        hcryp->OutCpltCallback(hcryp);
+#else
+        /*Call legacy Output complete callback*/
+        HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+        /* If suspension flag has been raised, suspend processing
+           only if not already at the end of the payload */
+        if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+        {
+          /* Clear CCF Flag */
+          __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+          /* reset SuspendRequest */
+          hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+          /* Disable Computation Complete Flag and Errors Interrupts */
+          __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+          /* Change the CRYP state */
+          hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+
+          /* Mark that the payload phase is suspended */
+          hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
+
+          __HAL_UNLOCK(hcryp);
+        }
+        else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+        {
+          /* Write the input block in the IN FIFO */
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+
+          if (hcryp->CrypInCount == (hcryp->Size / 4U))
+          {
+            /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+            /*Call registered Input complete callback*/
+            hcryp->InCpltCallback(hcryp);
+#else
+            /*Call legacy Input complete callback*/
+            HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+          }
+        }
+      } /* if (hcryp->CrypOutCount == (hcryp->Size / 4U)) */
+    } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Writes Key in Key registers.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  KeySize: Size of Key
+  * @retval None
+  */
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
+{
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    switch (KeySize)
+    {
+      case CRYP_KEYSIZE_256B:
+        ((CRYP_TypeDef *)(hcryp->Instance))->K0LR = *(uint32_t *)(hcryp->Init.pKey);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
+        break;
+
+      case CRYP_KEYSIZE_192B:
+        ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
+        break;
+
+      case CRYP_KEYSIZE_128B:
+        ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
+        ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
+        break;
+
+      default:
+        break;
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    if (hcryp->Init.pKey != NULL)
+    {
+      switch (KeySize)
+      {
+        case CRYP_KEYSIZE_256B:
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
+          break;
+        case CRYP_KEYSIZE_128B:
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+          ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+
+          break;
+        default:
+          break;
+      }
+    } /*  if (hcryp->Init.pKey != NULL) */
+  } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+/**
+  * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
+  uint32_t npblb ;
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+  uint32_t index ;
+  uint32_t lastwordsize ;
+  uint32_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t mode;
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
+
+    /****************************** Init phase **********************************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+      /* Set the Key */
+      if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+      {
+        if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+        {
+          CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+        }
+        else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->CR &=  ~CRYP_KEYMODE_SHARED;
+        }
+      }
+
+      /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /*Wait for the CRYPEN bit to be cleared*/
+      while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Disable the CRYP peripheral clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
+
+      /* We should re-write Key, in the case where we change key after first operation */
+      if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      }
+
+      /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* just wait for hash computation */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /************************ Header phase *************************************/
+
+    if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /*************************Payload phase ************************************/
+
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
+
+    /* Select payload phase once the header phase is performed */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Select payload phase once the header phase is performed */
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Select payload phase once the header phase is performed */
+      SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+  } /* if (DoKeyIVConfig == 1U) */
+
+  if ((hcryp->Size % 16U) != 0U)
+  {
+    /* recalculate  wordsize */
+    wordsize = ((wordsize / 4U) * 4U) ;
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /*Temporary CrypOutCount Value */
+  outcount = hcryp->CrypOutCount;
+  /* Write input data and get output data */
+  while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+  {
+    /* Write plain data and get cipher data */
+    CRYP_AES_ProcessData(hcryp, Timeout);
+
+    /*Temporary CrypOutCount Value */
+    outcount = hcryp->CrypOutCount;
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  if ((hcryp->Size % 16U) != 0U)
+  {
+    /* Compute the number of padding bytes in last block of payload */
+    npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+    /*  Set Npblb in case of AES GCM payload encryption to get right tag */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
+      if (mode == CRYP_OPERATINGMODE_ENCRYPT)
+      {
+        /* Disable the CRYP */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Specify the number of non-valid bytes using NPBLB register */
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U);
+
+        /* Enable CRYP to start the final phase */
+        __HAL_CRYP_ENABLE(hcryp);
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+      if (mode == CRYP_OPERATINGMODE_ENCRYPT)
+      {
+        /* Specify the number of non-valid bytes using NPBLB register */
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U);
+      }
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Number of valid words (lastwordsize) in last block */
+    if ((npblb % 4U) == 0U)
+    {
+      lastwordsize = (16U - npblb) / 4U;
+    }
+    else
+    {
+      lastwordsize = ((16U - npblb) / 4U) + 1U;
+    }
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Write the last input block in the IN FIFO */
+      for (index = 0U; index < lastwordsize; index ++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+
+      /* Pad the data with zeros to have a complete block */
+      while (index < 4U)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+        index++;
+      }
+
+      /* Wait for OFNE flag to be raised */
+      if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered error callback*/
+        hcryp->ErrorCallback(hcryp);
+#else
+        /*Call legacy error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+
+      /*Read the output block from the output FIFO */
+      if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
+      {
+        for (index = 0U; index < 4U; index++)
+        {
+          /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+             temporary buffer */
+          temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+        }
+      }
+      else
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Write the last input block in the IN FIFO */
+      for (index = 0U; index < lastwordsize; index ++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+      while (index < 4U)
+      {
+        /* pad the data with zeros to have a complete block */
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
+        index++;
+      }
+      /* Wait for CCF flag to be raised */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered error callback*/
+        hcryp->ErrorCallback(hcryp);
+#else
+        /*Call legacy error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+      /*Read the output block from the output FIFO */
+      for (index = 0U; index < 4U; index++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer then
+           get CrypOutBuff from temporary buffer */
+        temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+      }
+    }
+#endif /* USE_HAL_SAES_ONLY */
+    for (index = 0U; index < lastwordsize; index++)
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
+      hcryp->CrypOutCount++;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
+  uint32_t tickstart;
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  uint32_t count;
+  uint32_t loopcounter;
+  uint32_t lastwordsize;
+  uint32_t headersize_in_bytes;
+  uint32_t tmp;
+  uint32_t npblb;
+  const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
+                             0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
+                             0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+                            }; /*  8-bit data type */
+#endif /* USE_HAL_SAES_ONLY */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+  if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
+  {
+    CRYP_PhaseProcessingResume(hcryp);
+    return HAL_OK;
+  }
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  /* Manage header size given in bytes to handle cases where
+     header size is not a multiple of 4 bytes */
+  if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+  {
+    headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+  }
+  else
+  {
+    headersize_in_bytes = hcryp->Init.HeaderSize;
+  }
+#endif /* USE_HAL_SAES_ONLY */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  /* Configure Key, IV and process message (header and payload) */
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
+
+    /******************************* Init phase *********************************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+      /* Set the Key */
+      if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+      {
+        if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+        {
+          CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+        }
+        else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
+        }
+      }
+      /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+      /*Wait for the CRYPEN bit to be cleared */
+      while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
+
+      /* We should re-write Key, in the case where we change key after first operation */
+      if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      }
+      else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
+      }
+
+      /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Wait for KEYVALID flag to be set */
+      count = CRYP_TIMEOUT_KEYPREPARATION;
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          /* Disable the SAES peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_KEYVALID));
+
+      /* just wait for hash computation */
+      count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF));
+
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /***************************** Header phase *********************************/
+
+    /* Select header phase */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      if (headersize_in_bytes == 0U) /*header phase is skipped*/
+      {
+        /* Set the phase */
+        hcryp->Phase = CRYP_PHASE_PROCESS;
+
+        /* Select payload phase once the header phase is performed */
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD);
+
+        /* Set to 0 the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+
+        /* Write the payload Input block in the IN FIFO */
+        if (hcryp->Size == 0U)
+        {
+          /* Disable interrupts */
+          __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+          /* Change the CRYP state */
+          hcryp->State = HAL_CRYP_STATE_READY;
+          __HAL_UNLOCK(hcryp);
+        }
+        else if (hcryp->Size >= 16U)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+          {
+            /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+            /*Call registered Input complete callback*/
+            hcryp->InCpltCallback(hcryp);
+#else
+            /*Call legacy Input complete callback*/
+            HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+          }
+
+          /* Enable computation complete flag and error interrupts */
+          __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+        }
+        else /* Size < 16Bytes  : first block is the last block*/
+        {
+          /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
+          Workaround is implemented in polling mode, so if last block of
+          payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+
+
+          /* Compute the number of padding bytes in last block of payload */
+          npblb = 16U - ((uint32_t)hcryp->Size);
+
+          if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+          {
+            /* Set to 0 the number of non-valid bytes using NPBLB register*/
+            MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
+          }
+
+          /* Number of valid words (lastwordsize) in last block */
+          if ((npblb % 4U) == 0U)
+          {
+            lastwordsize = (16U - npblb) / 4U;
+          }
+          else
+          {
+            lastwordsize = ((16U - npblb) / 4U) + 1U;
+          }
+
+          /*  last block optionally pad the data with zeros*/
+          for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+            hcryp->CrypInCount++;
+          }
+          while (loopcounter < 4U)
+          {
+            /* pad the data with zeros to have a complete block */
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+          }
+          /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+          /*Call registered Input complete callback*/
+          hcryp->InCpltCallback(hcryp);
+#else
+          /*Call legacy Input complete callback*/
+          HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+          /* Enable computation complete flag and error interrupts */
+          __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+        }
+      }
+      /* Enter header data */
+      /* Cher first whether header length is small enough to enter the full header in one shot */
+      else if (headersize_in_bytes <= 16U)
+      {
+        /* Write header data, padded with zeros if need be */
+        for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+        }
+        /* If the header size is a multiple of words */
+        if ((headersize_in_bytes % 4U) == 0U)
+        {
+          /* Pad the data with zeros to have a complete block */
+          while (loopcounter < 4U)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+            hcryp->CrypHeaderCount++;
+          }
+        }
+        else
+        {
+          /* Enter last bytes, padded with zeros */
+          tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
+          loopcounter++;
+          hcryp->CrypHeaderCount++ ;
+          /* Pad the data with zeros to have a complete block */
+          while (loopcounter < 4U)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+            hcryp->CrypHeaderCount++;
+          }
+        }
+        /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered Input complete callback*/
+        hcryp->InCpltCallback(hcryp);
+#else
+        /*Call legacy Input complete callback*/
+        HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        /* Write the first input header block in the Input FIFO,
+           the following header data will be fed after interrupt occurrence */
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+      }
+    }
+#endif /* USE_HAL_SAES_ONLY */
+  } /* end of if (DoKeyIVConfig == 1U) */
+  else  /* Key and IV have already been configured,
+          header has already been processed;
+          only process here message payload */
+  {
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Enable computation complete flag and error interrupts */
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+
+      /* Write the payload Input block in the IN FIFO */
+      if (hcryp->Size == 0U)
+      {
+        /* Disable interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+        __HAL_UNLOCK(hcryp);
+      }
+      else if (hcryp->Size >= 16U)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        if (hcryp->CrypInCount == (hcryp->Size / 4U))
+        {
+          /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+          /*Call registered Input complete callback*/
+          hcryp->InCpltCallback(hcryp);
+#else
+          /*Call legacy Input complete callback*/
+          HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+        }
+      }
+      else /* Size < 16Bytes  : first block is the last block*/
+      {
+        /* Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
+        Workaround is implemented in polling mode, so if last block of
+        payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+
+        /* Compute the number of padding bytes in last block of payload */
+        npblb = 16U - ((uint32_t)hcryp->Size);
+
+        if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+        {
+          /* Set to 0 the number of non-valid bytes using NPBLB register*/
+          MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
+        }
+
+        /* Number of valid words (lastwordsize) in last block */
+        if ((npblb % 4U) == 0U)
+        {
+          lastwordsize = (16U - npblb) / 4U;
+        }
+        else
+        {
+          lastwordsize = ((16U - npblb) / 4U) + 1U;
+        }
+
+        /*  last block optionally pad the data with zeros*/
+        for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+        }
+        while (loopcounter < 4U)
+        {
+          /* pad the data with zeros to have a complete block */
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+          loopcounter++;
+        }
+      }
+    } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+  } /* if (DoKeyIVConfig != 1U) */
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+    /* Enable interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
+
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
+{
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  __IO uint32_t count = 0U;
+#endif /* USE_HAL_CRYP_ONLY */
+  uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
+  uint32_t index;
+  uint32_t npblb;
+  uint32_t lastwordsize = 0U;
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t mode;
+  uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  uint32_t tickstart;
+#endif /* USE_HAL_CRYP_ONLY */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
+
+    /*************************** Init phase ************************************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+      /* Set the Key */
+      if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+      {
+        if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+        {
+          CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+        }
+        else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
+        }
+      }
+
+      /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+      /*Wait for the CRYPEN bit to be cleared */
+      while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+        }
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
+
+      /* Set the Key */
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+      /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Wait for CCF to be raised */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+    /************************ Header phase *************************************/
+
+    if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /************************ Payload phase ************************************/
+
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
+
+    /* Select payload phase once the header phase is performed */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+  } /* if (DoKeyIVConfig == 1U) */
+
+  if (hcryp->Size == 0U)
+  {
+    /* Process unLocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Change the CRYP state and phase */
+    hcryp->State = HAL_CRYP_STATE_READY;
+  }
+  else if (hcryp->Size >= 16U)
+  {
+    /* DMA transfer must not include the last block in case of Size is not %16 */
+    wordsize = wordsize - (wordsize % 4U);
+
+    /* DMA transfer */
+    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize * 4U,
+                      (uint32_t)(hcryp->pCrypOutBuffPtr));
+  }
+  else /* length of input data is < 16 */
+  {
+    /* Compute the number of padding bytes in last block of payload */
+    npblb = 16U - (uint32_t)hcryp->Size;
+
+    /* Set Npblb in case of AES GCM payload encryption to get right tag*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
+
+      if (mode == CRYP_OPERATINGMODE_ENCRYPT)
+      {
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
+      }
+
+      /* Enable CRYP to start the final phase */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /* Write the last input block in the IN FIFO */
+      for (index = 0; index < lastwordsize; index ++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+
+      /* Pad the data with zeros to have a complete block */
+      while (index < 4U)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+        index++;
+      }
+
+      /* Wait for OFNE flag to be raised */
+      count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+      do
+      {
+        count-- ;
+        if (count == 0U)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+          /*Call registered error callback*/
+          hcryp->ErrorCallback(hcryp);
+#else
+          /*Call legacy error callback*/
+          HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+        }
+      } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE));
+
+      /*Read the output block from the output FIFO */
+      for (index = 0U; index < 4U; index++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+           temporary buffer */
+        temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+      if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+          ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+      {
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
+      }
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /* Write the last input block in the IN FIFO */
+      for (index = 0; index < lastwordsize; index ++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+
+      /* Pad the data with zeros to have a complete block */
+      while (index < 4U)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
+        index++;
+      }
+
+      /* Wait for CCF flag to be raised */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        /*Call registered error callback*/
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        hcryp->ErrorCallback(hcryp);
+#else
+        /*Call legacy error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+      /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+      /*Read the output block from the output FIFO */
+      for (index = 0U; index < 4U; index++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+           temporary buffer */
+        temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+      }
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    for (index = 0; index < lastwordsize; index++)
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+      hcryp->CrypOutCount++;
+    }
+
+    /* Change the CRYP state to ready */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  AES CCM encryption/decryption processing in polling mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
+  uint32_t npblb ;
+  uint32_t lastwordsize ;
+  uint32_t temp[4] ;  /* Temporary CrypOutBuff */
+  uint32_t index ;
+  uint32_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t mode;
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
+
+    /********************** Init phase ******************************************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+      /* Set the Key */
+      if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+      {
+        if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+        {
+          CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+        }
+        else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->CR &=  ~CRYP_KEYMODE_SHARED;
+        }
+      }
+      /* Set the initialization vector (IV) with CTR1 information */
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Set the initialization vector (IV) with B0 */
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /*Wait for the CRYPEN bit to be cleared*/
+      while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Disable the CRYP peripheral clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
+
+      /* We should re-write Key, in the case where we change key after first operation */
+      if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      }
+
+      /* Set the initialization vector (IV) with B0 */
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* just wait for hash computation */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /************************* Header phase *************************************/
+    /* Header block(B1) : associated data length expressed in bytes concatenated
+    with Associated Data (A)*/
+
+    if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+    /********************** Payload phase ***************************************/
+
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    /* Select payload phase once the header phase is performed */
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
+
+      /* Select payload phase once the header phase is performed */
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+
+      /* Select payload phase once the header phase is performed */
+      SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+  } /* if (DoKeyIVConfig == 1U) */
+
+  if ((hcryp->Size % 16U) != 0U)
+  {
+    /* recalculate  wordsize */
+    wordsize = ((wordsize / 4U) * 4U) ;
+  }
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /*Temporary CrypOutCount Value */
+  outcount = hcryp->CrypOutCount;
+  /* Write input data and get output data */
+  while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+  {
+    /* Write plain data and get cipher data */
+    CRYP_AES_ProcessData(hcryp, Timeout);
+
+    /*Temporary CrypOutCount Value */
+    outcount = hcryp->CrypOutCount;
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+  }
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    if ((hcryp->Size % 16U) != 0U)
+    {
+      /* Compute the number of padding bytes in last block of payload */
+      npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+      mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
+      if (mode == CRYP_OPERATINGMODE_DECRYPT)
+      {
+        /* Disable the CRYP */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Set Npblb in case of AES CCM payload decryption to get right tag  */
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
+
+        /* Enable CRYP to start the final phase */
+        __HAL_CRYP_ENABLE(hcryp);
+      }
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /* Write the last input block in the IN FIFO */
+      for (index = 0U; index < lastwordsize; index ++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+
+      /* Pad the data with zeros to have a complete block */
+      while (index < 4U)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+        index++;
+      }
+
+      /* Wait for OFNE flag to be raised */
+      if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered error callback*/
+        hcryp->ErrorCallback(hcryp);
+#else
+        /*Call legacy error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+
+      /*Read the output block from the output FIFO */
+      if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
+      {
+        for (index = 0U; index < 4U; index++)
+        {
+          /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+             temporary buffer */
+          temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+        }
+        for (index = 0; index < lastwordsize; index++)
+        {
+          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+          hcryp->CrypOutCount++;
+        }
+      }
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+
+    if ((hcryp->Size % 16U) != 0U)
+    {
+      /* Compute the number of padding bytes in last block of payload */
+      npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
+
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+      if (mode == CRYP_OPERATINGMODE_DECRYPT)
+      {
+        /* Set Npblb in case of AES CCM payload decryption to get right tag  */
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
+      }
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /* Write the last input block in the IN FIFO */
+      for (index = 0U; index < lastwordsize; index ++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+
+      /* Pad the data with zeros to have a complete block */
+      while (index < 4U)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
+        index++;
+      }
+      /* just wait for hash computation */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered error callback*/
+        hcryp->ErrorCallback(hcryp);
+#else
+        /*Call legacy error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+      for (index = 0U; index < 4U; index++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer then
+           get CrypOutBuff from temporary buffer */
+        temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+      }
+      for (index = 0U; index < lastwordsize; index++)
+      {
+        *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+        hcryp->CrypOutCount++;
+      }
+    }
+  }
+#endif /* USE_HAL_SAES_ONLY */
+  /* Wait until the complete message has been processed */
+  if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+  {
+    /* Disable the CRYP peripheral clock */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Change state */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked & return error */
+    __HAL_UNLOCK(hcryp);
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  AES CCM encryption/decryption process in interrupt mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  uint32_t tickstart;
+#endif /* USE_HAL_CRYP_ONLY */
+  uint32_t loopcounter;
+  uint32_t lastwordsize;
+  uint32_t npblb;
+  uint32_t mode;
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  uint32_t headersize_in_bytes;
+  uint32_t tmp;
+  const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
+                             0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
+                             0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+                            }; /*  8-bit data type */
+#endif /* USE_HAL_SAES_ONLY */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+  if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
+  {
+    CRYP_PhaseProcessingResume(hcryp);
+    return HAL_OK;
+  }
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  /* Configure Key, IV and process message (header and payload) */
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
+
+    /************ Init phase ************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+      /* Set the Key */
+      if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+      {
+        if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+        {
+          CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+        }
+        else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
+        }
+      }
+
+      /* Set the initialization vector (IV) with CTR1 information */
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /*Write the B0 packet into CRYP_DR*/
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /*Wait for the CRYPEN bit to be cleared */
+      while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
+
+      /* We should re-write Key, in the case where we change key after first operation */
+      if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      }
+
+      /* Set the initialization vector (IV) with B0 */
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* just wait for hash computation */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /***************************** Header phase *********************************/
+
+    /* Select header phase */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+      /* Enable interrupts */
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
+
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Select header phase */
+      SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
+
+      /* Enable computation complete flag and error interrupts */
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+      if (headersize_in_bytes == 0U) /* Header phase is  skipped */
+      {
+        /* Set the phase */
+        hcryp->Phase = CRYP_PHASE_PROCESS;
+
+        /* Select payload phase once the header phase is performed */
+        SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
+
+        /* Set to 0 the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+
+        if (hcryp->Init.Algorithm == CRYP_AES_CCM)
+        {
+          /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
+          hcryp->CrypHeaderCount++;
+        }
+        /* Write the payload Input block in the IN FIFO */
+        if (hcryp->Size == 0U)
+        {
+          /* Disable interrupts */
+          __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+          /* Change the CRYP state */
+          hcryp->State = HAL_CRYP_STATE_READY;
+          __HAL_UNLOCK(hcryp);
+        }
+        else if (hcryp->Size >= 16U)
+        {
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+          hcryp->CrypInCount++;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+
+          if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+          {
+            /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+            /*Call registered Input complete callback*/
+            hcryp->InCpltCallback(hcryp);
+#else
+            /*Call legacy Input complete callback*/
+            HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+          }
+        }
+        else /* Size < 4 words  : first block is the last block*/
+        {
+          /* Compute the number of padding bytes in last block of payload */
+          npblb = 16U - (uint32_t)hcryp->Size;
+
+          mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+          if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+              ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+          {
+            /* Specify the number of non-valid bytes using NPBLB register*/
+            MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
+          }
+
+          /* Number of valid words (lastwordsize) in last block */
+          if ((npblb % 4U) == 0U)
+          {
+            lastwordsize = (16U - npblb) / 4U;
+          }
+          else
+          {
+            lastwordsize = ((16U - npblb) / 4U) + 1U;
+          }
+
+          /*  Last block optionally pad the data with zeros*/
+          for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+            hcryp->CrypInCount++;
+          }
+          while (loopcounter < 4U)
+          {
+            /* Pad the data with zeros to have a complete block */
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+          }
+          /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+          /*Call registered Input complete callback*/
+          hcryp->InCpltCallback(hcryp);
+#else
+          /*Call legacy Input complete callback*/
+          HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+        }
+      }
+      /* Enter header data */
+      /* Check first whether header length is small enough to enter the full header in one shot */
+      else if (headersize_in_bytes <= 16U)
+      {
+        for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++;
+        }
+        /* If the header size is a multiple of words */
+        if ((headersize_in_bytes % 4U) == 0U)
+        {
+          /* Pad the data with zeros to have a complete block */
+          while (loopcounter < 4U)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+          }
+        }
+        else
+        {
+          /* Enter last bytes, padded with zeros */
+          tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
+          hcryp->CrypHeaderCount++;
+          loopcounter++;
+          /* Pad the data with zeros to have a complete block */
+          while (loopcounter < 4U)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+          }
+        }
+        /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered Input complete callback*/
+        hcryp->InCpltCallback(hcryp);
+#else
+        /*Call legacy Input complete callback*/
+        HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        /* Write the first input header block in the Input FIFO,
+           the following header data will be fed after interrupt occurrence */
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
+      } /* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is  skipped*/
+    } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+  } /* end of if (dokeyivconfig == 1U) */
+  else  /* Key and IV have already been configured,
+          header has already been processed;
+          only process here message payload */
+  {
+    /* Write the payload Input block in the IN FIFO */
+    if (hcryp->Size == 0U)
+    {
+      /* Disable interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      __HAL_UNLOCK(hcryp);
+    }
+    else if (hcryp->Size >= 16U)
+    {
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+      hcryp->CrypInCount++;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
+
+      if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+      {
+        /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered Input complete callback*/
+        hcryp->InCpltCallback(hcryp);
+#else
+        /*Call legacy Input complete callback*/
+        HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+    }
+    else /* Size < 4 words  : first block is the last block*/
+    {
+      /* Compute the number of padding bytes in last block of payload */
+      npblb = 16U - (uint32_t)hcryp->Size;
+
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+      if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+          ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+      {
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
+      }
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /*  Last block optionally pad the data with zeros*/
+      for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+      while (loopcounter < 4U)
+      {
+        /* Pad the data with zeros to have a complete block */
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+        loopcounter++;
+      }
+      /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+      /*Call registered Input complete callback*/
+      hcryp->InCpltCallback(hcryp);
+#else
+      /*Call legacy Input complete callback*/
+      HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+    }
+  } /* end of if (DoKeyIVConfig == 1U) */
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  AES CCM encryption/decryption process in DMA mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
+  uint32_t index;
+  uint32_t npblb;
+  uint32_t lastwordsize = 0U;
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t mode;
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  uint32_t tickstart;
+#endif /* USE_HAL_CRYP_ONLY */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
+
+    /************************** Init phase **************************************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+      /* Set the Key */
+      if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
+      {
+        if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
+        {
+          CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+        }
+        else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->CR &=  ~CRYP_KEYMODE_SHARED;
+        }
+      }
+      /* Set the initialization vector (IV) with CTR1 information */
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
+      ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /*Write the B0 packet into CRYP_DR*/
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /*Wait for the CRYPEN bit to be cleared*/
+      while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+      {
+        /* Check for the Timeout */
+        if ((HAL_GetTick() - tickstart) > CRYP_TIMEOUT_GCMCCMINITPHASE)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
+
+      /* We should re-write Key, in the case where we change key after first operation */
+      if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
+      {
+        /* Set the Key */
+        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+      };
+
+      /* Set the initialization vector (IV) with B0 */
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
+      ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* just wait for hash computation */
+      if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /********************* Header phase *****************************************/
+
+    if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /******************** Payload phase *****************************************/
+
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
+
+    /* Select payload phase once the header phase is performed */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+    }
+#endif /* USE_CRYP_INSTANCE */
+  } /* if (DoKeyIVConfig == 1U) */
+
+  if (hcryp->Size == 0U)
+  {
+    /* Process unLocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Change the CRYP state and phase */
+    hcryp->State = HAL_CRYP_STATE_READY;
+  }
+  else if (hcryp->Size >= 16U)
+  {
+    wordsize = wordsize - (wordsize % 4U);
+    /* DMA transfer */
+    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize * 4U,
+                      (uint32_t)(hcryp->pCrypOutBuffPtr));
+  }
+  else /* length of input data is  < 16U */
+  {
+    /* Compute the number of padding bytes in last block of payload */
+    npblb = 16U - (uint32_t)(hcryp->Size);
+
+    /* Set Npblb in case of AES CCM payload decryption to get right tag*/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
+
+      if (mode == CRYP_OPERATINGMODE_DECRYPT)
+      {
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
+      }
+
+      /* Enable CRYP to start the final phase */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /* Write the last input block in the IN FIFO */
+      for (index = 0U; index < lastwordsize; index ++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+
+      /* Pad the data with zeros to have a complete block */
+      while (index < 4U)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+        index++;
+      }
+
+      /* Wait for OFNE flag to be raised */
+      if (CRYP_WaitOnOFNEFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state & update error code */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered error callback*/
+        hcryp->ErrorCallback(hcryp);
+#else
+        /*Call legacy error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+
+      /*Read the output block from the output FIFO */
+      for (index = 0U; index < 4U; index++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+           temporary buffer */
+        temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+      }
+    } /* SAES peripheral */
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+
+      if (mode == CRYP_OPERATINGMODE_DECRYPT)
+      {
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
+      }
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /* Write the last input block in the IN FIFO */
+      for (index = 0U; index < lastwordsize; index ++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+
+      /* Pad the data with zeros to have a complete block */
+      while (index < 4U)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
+        index++;
+      }
+      /* just wait for hash computation */
+      if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state & update error code */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered error callback*/
+        hcryp->ErrorCallback(hcryp);
+#else
+        /*Call legacy error callback*/
+        HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+      /*Read the output block from the output FIFO */
+      for (index = 0U; index < 4U; index++)
+      {
+        /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
+           temporary buffer */
+        temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+      }
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    for (index = 0; index < lastwordsize; index++)
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+      hcryp->CrypOutCount++;
+    }
+
+    /* Change the CRYP state to ready */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the payload phase in interrupt mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @retval state
+  */
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t loopcounter;
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+  uint32_t lastwordsize;
+  uint32_t npblb;
+  uint32_t mode;
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  uint8_t negative = 0U;
+#endif /* USE_HAL_CRYP_ONLY */
+  uint32_t i;
+
+  /***************************** Payload phase *******************************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    if ((hcryp->Size / 4U) < hcryp->CrypInCount)
+    {
+      negative = 1U;
+    }
+
+    if (hcryp->Size == 0U)
+    {
+      /* Disable interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+    }
+
+    else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
+             (negative == 0U))
+    {
+      if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
+      {
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+        /* If suspension flag has been raised, suspend processing
+           only if not already at the end of the payload */
+        if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+        {
+          /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
+             CRYP_SR) and the BUSY bit is cleared */
+          while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \
+                                                               CRYP_SR_BUSY)) != CRYP_SR_IFEM)
+          {
+            /* Nothing to do */
+          }
+
+          /* Disable interrupts */
+          __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+          /* Disable CRYP */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* reset SuspendRequest */
+          hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+
+          /* Change the CRYP state */
+          hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+
+          /* Mark that the payload phase is suspended */
+          hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hcryp);
+        }
+        else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+        {
+          /* Write the input block in the IN FIFO */
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+          if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
+          {
+            /* Disable interrupts */
+            __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+            /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+            /*Call registered Input complete callback*/
+            hcryp->InCpltCallback(hcryp);
+#else
+            /*Call legacy Input complete callback*/
+            HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+          }
+
+          if (hcryp->CrypOutCount < (hcryp->Size / 4U))
+          {
+            if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
+            {
+              /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from
+                 temporary buffer  */
+              for (i = 0U; i < 4U; i++)
+              {
+                temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+              }
+              i = 0U;
+              while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+              {
+                *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+                hcryp->CrypOutCount++;
+                i++;
+              }
+              if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
+              {
+                /* Disable interrupts */
+                __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+
+                /* Change the CRYP state */
+                hcryp->State = HAL_CRYP_STATE_READY;
+
+                /* Disable CRYP */
+                __HAL_CRYP_DISABLE(hcryp);
+
+                /* Process unlocked */
+                __HAL_UNLOCK(hcryp);
+
+                /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+                /*Call registered Output complete callback*/
+                hcryp->OutCpltCallback(hcryp);
+#else
+                /*Call legacy Output complete callback*/
+                HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+              }
+            }
+          }
+        } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */
+      }
+    }
+    else if ((hcryp->Size % 16U) != 0U)
+    {
+      /* Set padding only in case of input fifo interrupt */
+      if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
+      {
+        /* Compute the number of padding bytes in last block of payload */
+        npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
+        mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
+        if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+            ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+        {
+          /* Disable the CRYP */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Specify the number of non-valid bytes using NPBLB register*/
+          MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
+
+          /* Enable CRYP to start the final phase */
+          __HAL_CRYP_ENABLE(hcryp);
+        }
+
+
+        /* Number of valid words (lastwordsize) in last block */
+        if ((npblb % 4U) == 0U)
+        {
+          lastwordsize = (16U - npblb) / 4U;
+        }
+        else
+        {
+          lastwordsize = ((16U - npblb) / 4U) + 1U;
+        }
+
+        /* Write the last input block in the IN FIFO */
+        for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+        }
+        /* Pad the data with zeros to have a complete block */
+        while (loopcounter < 4U)
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+          loopcounter++;
+        }
+
+        /* Disable the input FIFO Interrupt */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+      }
+
+      /*Read the output block from the output FIFO */
+      if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
+      {
+        for (i = 0U; i < 4U; i++)
+        {
+          temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+        }
+        if (((hcryp->Size) / 4U) == 0U)
+        {
+          for (i = 0U; (uint16_t)i < ((hcryp->Size) % 4U); i++)
+          {
+            *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+            hcryp->CrypOutCount++;
+          }
+        }
+        i = 0U;
+        while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
+        {
+          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+          hcryp->CrypOutCount++;
+          i++;
+        }
+      }
+
+      /* Disable the output FIFO Interrupt */
+      if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U))
+      {
+        /* Disable interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
+
+        /* Change the CRYP peripheral state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+
+        /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered Output complete callback*/
+        hcryp->OutCpltCallback(hcryp);
+#else
+        /*Call legacy Output complete callback*/
+        HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    uint32_t incount;
+    uint32_t outcount;
+
+    /* Read the output block from the output FIFO and put them in temporary buffer then
+       get CrypOutBuff from temporary buffer*/
+    for (i = 0U; i < 4U; i++)
+    {
+      temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+    }
+    i = 0U;
+    while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+      hcryp->CrypOutCount++;
+      i++;
+    }
+    incount = hcryp->CrypInCount;
+    outcount = hcryp->CrypOutCount;
+    if ((outcount >= ((uint32_t)(hcryp->Size) / 4U)) && ((incount * 4U) >= (uint32_t)(hcryp->Size)))
+    {
+
+      /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
+      if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
+      {
+        /* Disable computation complete flag and errors interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+      }
+
+      /* Change the CRYP state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+      __HAL_UNLOCK(hcryp);
+
+      /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+      /*Call registered Output complete callback*/
+      hcryp->OutCpltCallback(hcryp);
+#else
+      /*Call legacy Output complete callback*/
+      HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+    }
+
+    else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
+    {
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+      /* If suspension flag has been raised, suspend processing
+         only if not already at the end of the payload */
+      if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+      {
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+        /* reset SuspendRequest */
+        hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+        /* Disable Computation Complete Flag and Errors Interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+        /* Mark that the payload phase is suspended */
+        hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
+        __HAL_UNLOCK(hcryp);
+      }
+      else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+      {
+        /* Write the input block in the IN FIFO */
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        if ((hcryp->CrypInCount ==  hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM))
+        {
+          /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+          /*Call registered Input complete callback*/
+          hcryp->InCpltCallback(hcryp);
+#else
+          /*Call legacy Input complete callback*/
+          HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+        }
+      }
+    }
+    else /* Last block of payload < 128bit*/
+    {
+      /* Compute the number of padding bytes in last block of payload */
+      npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
+
+      mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+      if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+          ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+      {
+        /* Specify the number of non-valid bytes using NPBLB register*/
+        MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
+      }
+
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
+
+      /*  Last block optionally pad the data with zeros*/
+      for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+      while (loopcounter < 4U)
+      {
+        /* pad the data with zeros to have a complete block */
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+        loopcounter++;
+      }
+    }
+  } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+
+/**
+  * @brief  Sets the header phase in polling mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module(Header & HeaderSize)
+  * @param  Timeout: Timeout value
+  * @retval state
+  */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t loopcounter;
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  uint32_t headersize_in_bytes;
+  uint32_t tmp;
+  const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
+                             0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
+                             0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+                            }; /*  8-bit data type */
+#endif /* USE_HAL_SAES_ONLY */
+
+  /***************************** Header phase for GCM/GMAC or CCM *********************************/
+
+  /* Select header phase */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
+
+    if ((hcryp->Init.HeaderSize % 4U) == 0U)
+    {
+      /* HeaderSize %4, no padding */
+      for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+
+        /* Wait for IFEM to be raised */
+        if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+    else
+    {
+      /*Write header block in the IN FIFO without last block */
+      for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
+           loopcounter += 4U)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+
+        /* Wait for IFEM to be raised */
+        if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+      /*  Last block optionally pad the data with zeros*/
+      for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+      }
+      while (loopcounter < 4U)
+      {
+        /* pad the data with zeros to have a complete block */
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
+        loopcounter++;
+      }
+      /* Wait for IFEM to be raised */
+      if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+    {
+      headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+    }
+    else
+    {
+      headersize_in_bytes = hcryp->Init.HeaderSize;
+    }
+
+    /* Set Header phase */
+    SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
+
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
+
+    if ((headersize_in_bytes % 16U) == 0U)
+    {
+      /* HeaderSize %4, no padding */
+      for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+
+        /* Wait for CCF to be raised */
+        if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+        /* Clear CCF flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+      }
+    }
+    else
+    {
+      /*Write header block in the IN FIFO without last block */
+      for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+
+        /* Wait for CCF to be raised */
+        if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+        /* Clear CCF flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+      }
+      /* Write last complete words */
+      for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+      }
+      /* If the header size is a multiple of words */
+      if ((headersize_in_bytes % 4U) == 0U)
+      {
+        /* Pad the data with zeros to have a complete block */
+        while (loopcounter < 4U)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+          loopcounter++;
+        }
+      }
+      else
+      {
+        /* Enter last bytes, padded with zeros */
+        tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)];
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
+        loopcounter++;
+        /* Pad the data with zeros to have a complete block */
+        while (loopcounter < 4U)
+        {
+          /* pad the data with zeros to have a complete block */
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+          loopcounter++;
+        }
+      }
+
+      /* Wait for CCF to be raised */
+      if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+  }
+#endif /* USE_HAL_SAES_ONLY */
+  /* Wait until the complete message has been processed */
+  if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+  {
+    /* Disable the CRYP peripheral clock */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Change state */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked & return error */
+    __HAL_UNLOCK(hcryp);
+    return HAL_ERROR;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Sets the header phase when using DMA in process
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module(Header & HeaderSize)
+  * @retval None
+  */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t loopcounter;
+  uint32_t Timeout = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  uint32_t headersize_in_bytes;
+  uint32_t tmp;
+  const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
+                             0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
+                             0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+                            }; /*  8-bit data type */
+#endif /* USE_HAL_SAES_ONLY */
+
+  /***************************** Header phase for GCM/GMAC or CCM *********************************/
+  if ((hcryp->Init.HeaderSize != 0U))
+  {
+    /* Select header phase */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      if ((hcryp->Init.HeaderSize % 4U) == 0U)
+      {
+        /* HeaderSize %4, no padding */
+        for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+
+          /* Wait for IFEM to be raised */
+          if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+          {
+            /* Disable the CRYP peripheral clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+      else
+      {
+        /*Write header block in the IN FIFO without last block */
+        for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
+             loopcounter += 4U)
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+
+          /* Wait for IFEM to be raised */
+          if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+          {
+            /* Disable the CRYP peripheral clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+        /*  Last block optionally pad the data with zeros*/
+        for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+        {
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+        }
+        while (loopcounter < 4U)
+        {
+          /* Pad the data with zeros to have a complete block */
+          ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
+          loopcounter++;
+        }
+
+        /* Wait for IFEM to be raised */
+        if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+      {
+        headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+      }
+      else
+      {
+        headersize_in_bytes = hcryp->Init.HeaderSize;
+      }
+      /* Set header phase*/
+      SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      if ((headersize_in_bytes % 16U) == 0U)
+      {
+        /* HeaderSize %4, no padding */
+        for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+
+          /* Wait for CCF to be raised */
+          if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+          {
+            /* Disable the CRYP peripheral clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+      else
+      {
+        /*Write header block in the IN FIFO without last block */
+        for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++ ;
+
+          /* Wait for CCF to be raised */
+          if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+          {
+            /* Disable the CRYP peripheral clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+        /* Write last complete words */
+        for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          hcryp->CrypHeaderCount++;
+        }
+        /* If the header size is a multiple of words */
+        if ((headersize_in_bytes % 4U) == 0U)
+        {
+          /* Pad the data with zeros to have a complete block */
+          while (loopcounter < 4U)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+          }
+        }
+        else
+        {
+          /* Enter last bytes, padded with zeros */
+          tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+          tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)];
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
+          loopcounter++;
+          /* Pad the data with zeros to have a complete block */
+          while (loopcounter < 4U)
+          {
+            ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+            loopcounter++;
+          }
+        }
+
+        /* Wait for CCF to be raised */
+        if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+#endif /* USE_HAL_SAES_ONLY */
+    /* Wait until the complete message has been processed */
+    Timeout = CRYP_GENERAL_TIMEOUT;
+    if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+    {
+      /* Disable the CRYP peripheral clock */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Change state */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the header phase in interrupt mode
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module(Header & HeaderSize)
+  * @retval None
+  */
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t loopcounter;
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  uint32_t lastwordsize;
+  uint32_t npblb;
+  uint32_t mode;
+  uint32_t headersize_in_bytes;
+  uint32_t tmp;
+  const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U,  /* 32-bit data type */
+                             0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU,  /* 16-bit data type */
+                             0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
+                            }; /*  8-bit data type */
+#endif /* USE_HAL_SAES_ONLY */
+
+  /***************************** Header phase *********************************/
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+    {
+      /* Disable interrupts */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+
+      /* Disable the CRYP peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Select payload phase once the header phase is performed */
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+      /* Enable Interrupts */
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+    }
+    else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
+
+    {
+      /* HeaderSize %4, no padding */
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+      hcryp->CrypHeaderCount++ ;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+      hcryp->CrypHeaderCount++ ;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+      hcryp->CrypHeaderCount++ ;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+      hcryp->CrypHeaderCount++ ;
+    }
+    else
+    {
+      /*  Last block optionally pad the data with zeros*/
+      for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+      }
+      while (loopcounter < 4U)
+      {
+        /* Pad the data with zeros to have a complete block */
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
+        loopcounter++ ;
+      }
+    }
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+    {
+      headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+    }
+    else
+    {
+      headersize_in_bytes = hcryp->Init.HeaderSize;
+    }
+    /***************************** Header phase *********************************/
+    /* Test whether or not the header phase is over.
+       If the test below is true, move to payload phase */
+    if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
+    {
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+      /* Select payload phase */
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD);
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
+
+      if (hcryp->Init.Algorithm == CRYP_AES_CCM)
+      {
+        /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
+        hcryp->CrypHeaderCount++;
+      }
+      /* Write the payload Input block in the IN FIFO */
+      if (hcryp->Size == 0U)
+      {
+        /* Disable interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+        __HAL_UNLOCK(hcryp);
+      }
+      else if (hcryp->Size >= 16U)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+
+        if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
+        {
+          /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+          /*Call registered Input complete callback*/
+          hcryp->InCpltCallback(hcryp);
+#else
+          /*Call legacy Input complete callback*/
+          HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+        }
+      }
+      else /* Size < 4 words  : first block is the last block*/
+      {
+        /* Compute the number of padding bytes in last block of payload */
+        npblb = 16U - ((uint32_t)hcryp->Size);
+        mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
+        if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+            ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+        {
+          /* Specify the number of non-valid bytes using NPBLB register*/
+          MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
+        }
+
+        /* Number of valid words (lastwordsize) in last block */
+        if ((npblb % 4U) == 0U)
+        {
+          lastwordsize = (16U - npblb) / 4U;
+        }
+        else
+        {
+          lastwordsize = ((16U - npblb) / 4U) + 1U;
+        }
+
+        /*  Last block optionally pad the data with zeros*/
+        for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+          hcryp->CrypInCount++;
+        }
+        while (loopcounter < 4U)
+        {
+          /* Pad the data with zeros to have a complete block */
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+          loopcounter++;
+        }
+        /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+        /*Call registered Input complete callback*/
+        hcryp->InCpltCallback(hcryp);
+#else
+        /*Call legacy Input complete callback*/
+        HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+    }
+    else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
+    {
+      /* Can enter full 4 header words */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+      /* If suspension flag has been raised, suspend processing
+         only if not already at the end of the header */
+      if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+      {
+        /* Clear CCF Flag */
+        __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+        /* reset SuspendRequest */
+        hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+        /* Disable Computation Complete Flag and Errors Interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+        /* Mark that the payload phase is suspended */
+        hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
+        __HAL_UNLOCK(hcryp);
+      }
+      else
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+      {
+        /* Write the input block in the IN FIFO */
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++;
+      }
+    }
+    else /* Write last header block (4 words), padded with zeros if needed */
+    {
+      for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        hcryp->CrypHeaderCount++ ;
+      }
+      /* If the header size is a multiple of words */
+      if ((headersize_in_bytes % 4U) == 0U)
+      {
+        /* Pad the data with zeros to have a complete block */
+        while (loopcounter < 4U)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+          loopcounter++;
+          hcryp->CrypHeaderCount++;
+        }
+      }
+      else
+      {
+        /* Enter last bytes, padded with zeros */
+        tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)];
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
+        loopcounter++;
+        hcryp->CrypHeaderCount++;
+        /* Pad the data with zeros to have a complete block */
+        while (loopcounter < 4U)
+        {
+          ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
+          loopcounter++;
+          hcryp->CrypHeaderCount++;
+        }
+      }
+    }
+  } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+/**
+  * @brief  Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_IFEM))
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+#endif /* USE_HAL_CRYP_ONLY */
+
+/**
+  * @brief  Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t flag_busy = 0U;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    flag_busy = CRYP_FLAG_BUSY;
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    flag_busy = SAES_FLAG_BUSY;
+  }
+#endif /* USE_HAL_SAES_ONLY */
+  while (HAL_IS_BIT_SET(((CRYP_TypeDef *)(hcryp->Instance))->SR, flag_busy))
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+/**
+  * @brief  Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef  *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE))
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+#endif /* USE_HAL_CRYP_ONLY */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+/**
+  * @brief  Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF))
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+#endif /* USE_HAL_SAES_ONLY */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+/**
+  * @brief  In case of message processing suspension, read the Initialization Vector.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Output Pointer to the buffer containing the saved Initialization Vector.
+  * @note   This value has to be stored for reuse by writing the AES_IVRx registers
+  *         as soon as the suspended processing has to be resumed.
+  * @retval None
+  */
+static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output)
+{
+  uint32_t outputaddr = (uint32_t)Output;
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR;
+    outputaddr += 4U;
+    *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR;
+    outputaddr += 4U;
+    *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR;
+    outputaddr += 4U;
+    *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR;
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR3;
+    outputaddr += 4U;
+    *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR2;
+    outputaddr += 4U;
+    *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR1;
+    outputaddr += 4U;
+    *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR0;
+  }
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+/**
+  * @brief  In case of GCM/GMAC/CCM processing resumption, rewrite the Initialization
+  *         Vector in the SAES_IVx registers.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Input Pointer to the buffer containing the saved Initialization Vector to
+  *         write back in the CRYP hardware block.
+  * @note   Applicable only to CRYP peripheral
+  * @note   CRYP must be disabled when reconfiguring the IV values.
+  * @retval None
+  */
+static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input)
+{
+  uint32_t ivaddr = (uint32_t)Input;
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+  if (IS_CRYP_INSTANCE(hcryp->Instance))
+  {
+    ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(ivaddr);
+    ivaddr += 4U;
+    ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(ivaddr);
+    ivaddr += 4U;
+    ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(ivaddr);
+    ivaddr += 4U;
+    ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(ivaddr);
+  }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+  if (IS_SAES_INSTANCE(hcryp->Instance))
+  {
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(ivaddr);
+    ivaddr += 4U;
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(ivaddr);
+    ivaddr += 4U;
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(ivaddr);
+    ivaddr += 4U;
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(ivaddr);
+  }
+#endif /* USE_HAL_SAES_ONLY */
+}
+
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+/**
+  * @brief  In case of message GCM/GMAC/CCM processing suspension,
+  *         read the context swap Registers.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Output Pointer to the buffer containing the saved Suspend Registers.
+  * @param  Algorithm specifies whether CCM or GCM/GMAC is suspended.
+  * @note   These values have to be stored for reuse by writing back the CRYP_CSGCMCCMxR CRYP_CSGCMxR registers
+  *         as soon as the suspended processing has to be resumed.
+  * @retval None
+  */
+static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm)
+{
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t inputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R);
+  uint32_t i;
+
+  for (i = 0; i < 8U; i++)
+  {
+    *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
+    outputaddr += 4U;
+    inputaddr  += 4U;
+  }
+  if (Algorithm == CRYP_AES_GCM)
+  {
+    for (i = 0; i < 8U; i++)
+    {
+      *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
+      outputaddr += 4U;
+      inputaddr  += 4U;
+    }
+  }
+}
+#endif /* USE_HAL_CRYP_ONLY */
+
+/**
+  * @brief  In case of message GCM/GMAC/CCM processing resumption, rewrite the context swap registers.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Input Pointer to the buffer containing the saved suspend registers to
+  *         write back in the CRYP hardware block.
+  * @param  Algorithm specifies whether CCM or GCM/GMAC is suspended.
+  * @note   AES must be disabled when reconfiguring the suspend registers.
+  * @retval None
+  */
+static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm)
+{
+  uint32_t inputaddr = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R);
+  uint32_t i;
+
+  for (i = 0; i < 8U; i++)
+  {
+    *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
+    outputaddr += 4U;
+    inputaddr  += 4U;
+  }
+  if (Algorithm == CRYP_AES_GCM)
+  {
+    for (i = 0; i < 8U; i++)
+    {
+      *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
+      outputaddr += 4U;
+      inputaddr  += 4U;
+    }
+  }
+}
+
+/**
+  * @brief  Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module(Header & HeaderSize)
+  * @retval None
+  */
+static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
+{
+  /* Case of header phase resumption =================================================*/
+  if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
+  {
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
+
+    /* Select header phase */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Enable interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
+
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+
+  }
+  /* Case of payload phase resumption =================================================*/
+  else
+  {
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
+
+    /* Select payload phase once the header phase is performed */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Enable Interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
+
+  }
+}
+
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+/*
+ * @brief  Adaptation needed do differentiate between CRYP and SAES CR_CHMOD fields
+ * @param  algo: corresponds to the algorithm to set
+ *         order: determines if conversion is done from CRYP to SAES and vice versa
+                  order = ALGOMODE_CRYP_TO_CHMOD_SAES means from algomode CRYP to chmod SAES
+                  order = ALGOMODE_SAES_TO_CHMOD_CRYP means from algomode SAES to chmod CRYP
+ * @retval new_algo: correspond to the CR_CHMOD setting applied
+ */
+static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order)
+{
+  uint32_t new_algo = 0x0;
+
+  if (order == 0U) /* from algomode CRYP to chmod SAES */
+  {
+    switch (algo)
+    {
+      case CRYP_AES_ECB :
+        new_algo = SAES_CR_CHMOD_AES_ECB;
+        break;
+      case CRYP_AES_CBC :
+        new_algo = SAES_CR_CHMOD_AES_CBC;
+        break;
+      case CRYP_AES_CTR :
+        new_algo = SAES_CR_CHMOD_AES_CTR;
+        break;
+      case CRYP_AES_GCM :
+        new_algo = SAES_CR_CHMOD_AES_GCM;
+        break;
+      case CRYP_AES_CCM :
+        new_algo = SAES_CR_CHMOD_AES_CCM;
+        break;
+      default :
+        break;
+    }
+
+  }
+  else /* order == 1 , from chmod SAES to algomode CRYP */
+  {
+    switch (algo)
+    {
+      case SAES_CR_CHMOD_AES_ECB :
+        new_algo = CRYP_AES_ECB;
+        break;
+      case SAES_CR_CHMOD_AES_CBC :
+        new_algo = CRYP_AES_CBC;
+        break;
+      case SAES_CR_CHMOD_AES_CTR :
+        new_algo = CRYP_AES_CTR;
+        break;
+      case SAES_CR_CHMOD_AES_GCM :
+        new_algo = CRYP_AES_GCM;
+        break;
+      case SAES_CR_CHMOD_AES_CCM :
+        new_algo = CRYP_AES_CCM;
+        break;
+      default :
+        break;
+    }
+  }
+
+  return new_algo;
+}
+#endif /* USE_HAL_SAES_ONLY */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+
+/**
+  * @}
+  */
+#endif /* CRYP */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cryp_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cryp_ex.c
new file mode 100644
index 000000000..3b30d3674
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_cryp_ex.c
@@ -0,0 +1,1016 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_cryp_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended CRYP HAL module driver
+  *          This file provides firmware functions to manage the following
+  *          functionalities of CRYP extension peripheral:
+  *           + Extended AES processing functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
+    Encryption/Decryption to get the authentication messages.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (CRYP)
+/** @defgroup CRYPEx CRYPEx
+  * @brief CRYP Extension HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Defines
+  * @{
+  */
+
+#define CRYP_PHASE_INIT                 0x00000000U
+#define CRYP_PHASE_HEADER               CRYP_CR_GCM_CCMPH_0
+#define CRYP_PHASE_PAYLOAD              CRYP_CR_GCM_CCMPH_1
+#define CRYP_PHASE_FINAL                CRYP_CR_GCM_CCMPH
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+#define SAES_PHASE_INIT                  0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
+#define SAES_PHASE_HEADER                SAES_CR_GCMPH_0         /*!< GCM/GMAC or CCM header phase */
+#define SAES_PHASE_PAYLOAD               SAES_CR_GCMPH_1         /*!< GCM(/CCM) payload phase      */
+#define SAES_PHASE_FINAL                 SAES_CR_GCMPH           /*!< GCM/GMAC or CCM  final phase */
+#endif /* USE_HAL_SAES_ONLY */
+
+#define  CRYPEx_PHASE_PROCESS       0x02U     /*!< CRYP peripheral is in processing phase */
+#define  CRYPEx_PHASE_FINAL         0x03U     /*!< CRYP peripheral is in final phase this is relevant 
+                                                   only with CCM and GCM modes */
+
+/*  CTR0 information to use in CCM algorithm */
+#define CRYP_CCM_CTR0_0            0x07FFFFFFU
+#define CRYP_CCM_CTR0_3            0xFFFFFF00U
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYPEx_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
+#endif /* USE_HAL_SAES_ONLY */
+/* Exported functions---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Exported_Functions
+  * @{
+  */
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+  *  @brief    CRYPEx Extended processing functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### Extended AES processing functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to generate the authentication
+          TAG in Polling mode
+      (+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
+      (+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
+         they should be used after Encrypt/Decrypt operation.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  generate the GCM authentication TAG.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pAuthTag: Pointer to the authentication buffer
+  *         the AuthTag generated here is 128bits length, if the TAG length is
+  *         less than 128bits, user should consider only the valid part of AuthTag
+  *         buffer which correspond exactly to TAG length.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+                                                    uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint64_t headerlength;
+  uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
+  uint32_t tagaddr = (uint32_t)pAuthTag;
+  uint8_t i;
+
+
+  if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+  {
+    headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
+  }
+  else
+  {
+    headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 8U;  /* Header length in bits */
+  }
+
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Check if initialization phase has already been performed */
+    if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
+    {
+      /* Change the CRYP phase */
+      hcryp->Phase = CRYPEx_PHASE_FINAL;
+    }
+    else /* Initialization phase has not been performed*/
+    {
+      /* Disable the Peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Sequence error code field */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      return HAL_ERROR;
+    }
+
+    /* Select final phase */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Disable CRYP to start the final phase */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* ALGODIR bit must be set to '0'. */
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+      ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_CR_ALGODIR;
+
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Write the number of bits in header (64 bits) followed by the number of bits
+      in the payload */
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = (uint32_t)(headerlength);
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
+      ((CRYP_TypeDef *)(hcryp->Instance))->DIN = (uint32_t)(inputlength);
+
+      /* Wait for OFNE flag to be raised */
+      tickstart = HAL_GetTick();
+      while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE))
+      {
+        /* Check for the Timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Disable the CRYP Peripheral Clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+      /* Read the authentication TAG in the output FIFO */
+      for (i = 0U; i < 4U; i++)
+      {
+        *(uint32_t *)(tagaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+        tagaddr += 4U;
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Select final phase */
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_FINAL);
+
+      /* Write the number of bits in header (64 bits) followed by the number of bits
+      in the payload */
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = (uint32_t)(headerlength);
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
+      ((SAES_TypeDef *)(hcryp->Instance))->DINR = (uint32_t)(inputlength);
+
+      /* Wait for CCF flag to be raised */
+      tickstart = HAL_GetTick();
+      while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF))
+      {
+        /* Check for the Timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Disable the CRYP peripheral Clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+
+      /* Read the authentication TAG in the output FIFO */
+      for (i = 0U; i < 4U; i++)
+      {
+        *(uint32_t *)(tagaddr) = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+        tagaddr += 4U;
+      }
+
+      /* Clear CCF Flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Disable the peripheral */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  AES CCM Authentication TAG generation.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  pAuthTag: Pointer to the authentication buffer
+  *         the AuthTag generated here is 128bits length, if the TAG length is
+  *         less than 128bits, user should consider only the valid part of AuthTag
+  *         buffer which correspond exactly to TAG length.
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag,
+                                                    uint32_t Timeout)
+{
+  uint32_t tagaddr = (uint32_t)pAuthTag;
+  uint32_t ctr0 [4] = {0};
+  uint32_t ctr0addr = (uint32_t)ctr0;
+  uint32_t tickstart;
+  uint8_t i;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Disable interrupts, we are now in polling mode to TAG generation */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Check if initialization phase has already been performed */
+    if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
+    {
+      /* Change the CRYP phase */
+      hcryp->Phase = CRYPEx_PHASE_FINAL;
+    }
+    else /* Initialization phase has not been performed*/
+    {
+      /* Disable the peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Sequence error code field */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      return HAL_ERROR;
+    }
+
+    /* Select final phase */
+#if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
+    if (IS_CRYP_INSTANCE(hcryp->Instance))
+    {
+      /* Disable CRYP to start the final phase */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* ALGODIR bit must be set to '0' */
+      MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+      ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_CR_ALGODIR;
+
+      /* Write the counter block in the IN FIFO, CTR0 information from B0
+      data has to be swapped according to the DATATYPE*/
+      ctr0[0] = hcryp->Init.B0[0] & CRYP_CCM_CTR0_0;
+      ctr0[1] = hcryp->Init.B0[1];
+      ctr0[2] = hcryp->Init.B0[2];
+      ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
+
+      for (i = 0U; i < 4U; i++)
+      {
+        ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(ctr0addr);
+        ctr0addr += 4U;
+      }
+      /* Enable the CRYP peripheral */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Wait for OFNE flag to be raised */
+      tickstart = HAL_GetTick();
+      while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)((hcryp->Instance)))->SR, CRYP_FLAG_OFNE))
+      {
+        /* Check for the Timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Disable the CRYP peripheral Clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+      /* Read the authentication TAG in the output FIFO */
+      for (i = 0U; i < 4U; i++)
+      {
+        *(uint32_t *)(tagaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
+        tagaddr += 4U;
+      }
+    }
+#endif /* USE_HAL_CRYP_ONLY */
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+    if (IS_SAES_INSTANCE(hcryp->Instance))
+    {
+      /* Change SAES final phase */
+      MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_FINAL);
+
+      for (i = 0U; i < 4U; i++)
+      {
+        ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(ctr0addr);
+        ctr0addr += 4U;
+      }
+
+      /* Wait for CCF flag to be raised */
+      tickstart = HAL_GetTick();
+      while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_CCF))
+      {
+        /* Check for the Timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Disable the CRYP peripheral Clock */
+            __HAL_CRYP_DISABLE(hcryp);
+
+            /* Change state */
+            hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+            hcryp->State = HAL_CRYP_STATE_READY;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hcryp);
+            return HAL_ERROR;
+          }
+        }
+      }
+      /* Read the authentication TAG in the output FIFO */
+      for (i = 0U; i < 4U; i++)
+      {
+        *(uint32_t *)(tagaddr) = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+        tagaddr += 4U;
+      }
+      /* Clear CCF flag */
+      __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+    }
+#endif /* USE_HAL_SAES_ONLY */
+
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Disable CRYP  */
+    __HAL_CRYP_DISABLE(hcryp);
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/** @defgroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions
+  * @brief    Wrap and Unwrap key functions.
+  *
+@verbatim
+  ==============================================================================
+                      ##### Wrap and Unwrap key #####
+  ==============================================================================
+    [..]  This section provides API allowing to wrap (encrypt) and unwrap (decrypt)
+          key using one of the following keys, and AES Algorithm.
+          Key selection :
+           - Derived hardware unique key (DHUK)
+           - XOR of DHUK and BHK
+           - Boot hardware key (BHK)
+           - Key registers AES_KEYx
+
+@endverbatim
+  * @{
+  */
+
+#if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
+/**
+  * @brief  Wrap (encrypt) application keys .
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input Pointer to the Key buffer to encrypt
+  * @param  Output Pointer to the Key buffer encrypted
+  * @param  Timeout Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t *Output, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /* Disable the CRYP peripheral clock */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Set the operating mode*/
+    MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
+
+    status = CRYPEx_KeyEncrypt(hcryp, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Unwrap (Decrypt) application keys .
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Input Pointer to the Key buffer to decrypt
+  * @param  Timeout Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+
+    /* Disable the CRYP peripheral clock */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Set the operating mode*/
+    MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
+
+    status = CRYPEx_KeyDecrypt(hcryp, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt/Decrypt Shared key functions
+  * @brief    Encrypt/Decrypt Shared key functions.
+  *
+@verbatim
+  ==============================================================================
+                      ##### Encrypt/Decrypt Shared key functions #####
+  ==============================================================================
+    [..]  This section provides API allowing to Encrypt/Decrypt Shared key
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Encrypt Shared key.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Key Pointer to the Key buffer to share
+  * @param  Output buffer pointer
+  * @param  ID Key share identification
+  * @param  Timeout Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t *Output, uint32_t ID,
+                                              uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Key;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /* Disable the CRYP peripheral clock */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Set the operating mode*/
+    MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD | SAES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID);
+
+    status = CRYPEx_KeyEncrypt(hcryp, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Decrypt Shared key.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  Key Pointer to the Key buffer to share
+  * @param  ID Key share identification
+  * @param  Timeout Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *Key, uint32_t ID, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change state Busy */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Key;
+
+    /* Disable the CRYP peripheral clock */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Set the operating mode*/
+    MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD | SAES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID);
+
+    status = CRYPEx_KeyDecrypt(hcryp, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+    }
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Key Decryption
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure
+  * @param  Timeout specify Timeout value
+  * @note   It is strongly recommended to select hardware secret keys
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t incount;  /* Temporary CrypInCount Value */
+  uint32_t tickstart;
+
+  /* key preparation for decryption, operating mode 2*/
+  MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
+
+  /*It is strongly recommended to select hardware secret keys*/
+  if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
+  {
+    /*  Set the Key*/
+    CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
+  }
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+
+  /* Wait for CCF flag to be raised */
+  tickstart = HAL_GetTick();
+  while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF))
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+  }
+  /* Clear CCF Flag */
+  __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+  /*  End of Key preparation for ECB/CBC */
+  /* Return to decryption operating mode(Mode 3)*/
+  MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
+
+
+  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+  {
+    /* Set the Initialization Vector*/
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+  }
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+
+  /* Set the phase */
+  hcryp->Phase = CRYPEx_PHASE_PROCESS;
+
+  if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B)
+  {
+    incount = 4;
+  }
+  else
+  {
+    incount = 8;
+  }
+  while (hcryp->CrypInCount < incount)
+  {
+    /* Write four times to input the key to encrypt */
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+
+    /* Wait for CCF flag to be raised */
+    tickstart = HAL_GetTick();
+    while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+  }
+
+  /* Disable the CRYP peripheral clock */
+  __HAL_CRYP_DISABLE(hcryp);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Key Encryption
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure
+  * @param  Timeout specify Timeout value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t incount;  /* Temporary CrypInCount Value */
+  uint32_t tickstart;
+  uint32_t temp;  /* Temporary CrypOutBuff */
+
+  MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+  {
+    /* Set the Initialization Vector*/
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+    ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+  }
+  /*It is strongly recommended to select hardware secret keys*/
+  if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
+  {
+    /*  Set the Key*/
+    CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
+  }
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for Valid KEY flag to set  */
+  while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_KEYVALID))
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+        /* Process unlocked */
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+
+  /* Set the phase */
+  hcryp->Phase = CRYPEx_PHASE_PROCESS;
+
+  if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B)
+  {
+    incount = 4;
+  }
+  else
+  {
+    incount = 8;
+  }
+  while (hcryp->CrypInCount < incount)
+  {
+    /* Write four times to input the key to encrypt */
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+    ((SAES_TypeDef *)(hcryp->Instance))->DINR  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+    hcryp->CrypInCount++;
+
+    /* Wait for CCF flag to be raised */
+    tickstart = HAL_GetTick();
+    while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
+
+    /* Read the output block from the output FIFO and put them in temporary buffer then
+       get CrypOutBuff from temporary buffer*/
+    temp  = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+    hcryp->CrypOutCount++;
+    temp  = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
+    hcryp->CrypOutCount++;
+    temp  = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+    hcryp->CrypOutCount++;
+    temp  = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount)   = temp;
+    hcryp->CrypOutCount++;
+  }
+
+  /* Disable the CRYP peripheral clock */
+  __HAL_CRYP_DISABLE(hcryp);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write Key in Key registers.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  KeySize Size of Key
+  * @note   If pKey is NULL, the Key registers are not written.
+  * @retval None
+  */
+static void CRYPEx_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
+{
+  if (hcryp->Init.pKey != NULL)
+  {
+    switch (KeySize)
+    {
+      case CRYP_KEYSIZE_256B:
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
+        break;
+      case CRYP_KEYSIZE_128B:
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
+        ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
+
+        break;
+      default:
+        break;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* USE_HAL_SAES_ONLY */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* CRYP */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dcmi.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dcmi.c
new file mode 100644
index 000000000..2b35444c1
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dcmi.c
@@ -0,0 +1,1374 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_dcmi.c
+  * @author  MCD Application Team
+  * @brief   DCMI HAL module driver
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Digital Camera Interface (DCMI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The sequence below describes how to use this driver to capture image
+      from a camera module connected to the DCMI Interface.
+      This sequence does not take into account the configuration of the
+      camera module, which should be made before to configure and enable
+      the DCMI to capture images.
+
+    (#) Program the required configuration through following parameters:
+        horizontal and vertical polarity, pixel clock polarity, Capture Rate,
+        Synchronization Mode, code of the frame delimiter and data width
+        using HAL_DCMI_Init() function.
+
+    (#) Configure the selected DMA stream to transfer Data from DCMI DR
+        register to the destination memory buffer.
+
+    (#) Program the required configuration through following parameters:
+        DCMI mode, destination memory Buffer address and the data length
+        and enable capture using HAL_DCMI_Start_DMA() function.
+
+    (#) Optionally, configure and Enable the CROP feature to select a rectangular
+        window from the received image using HAL_DCMI_ConfigCrop()
+        and HAL_DCMI_EnableCrop() functions
+
+    (#) The capture can be stopped using HAL_DCMI_Stop() function.
+
+    (#) To control DCMI state you can use the function HAL_DCMI_GetState().
+
+     *** DCMI HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DCMI HAL driver.
+
+      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
+      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
+      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
+      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
+      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
+      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
+      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
+
+     [..]
+       (@) You can refer to the DCMI HAL driver header file for more useful macros
+
+    *** Callback registration ***
+    =============================
+
+    The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+    Use functions HAL_DCMI_RegisterCallback() to register a user callback.
+
+    Function HAL_DCMI_RegisterCallback() allows to register following callbacks:
+      (+) FrameEventCallback : callback for DCMI Frame Event.
+      (+) VsyncEventCallback : callback for DCMI Vsync Event.
+      (+) LineEventCallback  : callback for DCMI Line Event.
+      (+) ErrorCallback      : callback for DCMI error detection.
+      (+) MspInitCallback    : callback for DCMI MspInit.
+      (+) MspDeInitCallback  : callback for DCMI MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function.
+    HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the callback ID.
+    This function allows to reset following callbacks:
+      (+) FrameEventCallback : callback for DCMI Frame Event.
+      (+) VsyncEventCallback : callback for DCMI Vsync Event.
+      (+) LineEventCallback  : callback for DCMI Line Event.
+      (+) ErrorCallback      : callback for DCMI error.
+      (+) MspInitCallback    : callback for DCMI MspInit.
+      (+) MspDeInitCallback  : callback for DCMI MspDeInit.
+
+    By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (overridden) functions:
+    examples FrameEventCallback(), HAL_DCMI_ErrorCallback().
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (overridden) functions in the HAL_DCMI_Init
+    and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_DCMI_RegisterCallback before calling HAL_DCMI_DeInit
+    or HAL_DCMI_Init function.
+
+    When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+#ifdef HAL_DCMI_MODULE_ENABLED
+#if defined (DCMI)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+/** @defgroup DCMI DCMI
+  * @brief DCMI HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Stop_TimeOut DCMI Stop Time Out
+  * @{
+  */
+#define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000) /* Set timeout to 1s  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DCMI_Private_Functions DCMI Private Functions
+  * @{
+  */
+static void       DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
+  * @{
+  */
+
+/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DCMI
+      (+) De-initialize the DCMI
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the DCMI according to the specified
+  *         parameters in the DCMI_InitTypeDef and create the associated handle.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Check the DCMI peripheral state */
+  if (hdcmi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
+  assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
+  assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
+  assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
+  assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
+  assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
+  assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
+  assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
+
+  assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
+  assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
+  assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
+  assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
+
+  if (hdcmi->State == HAL_DCMI_STATE_RESET)
+  {
+    /* Init the DCMI Callback settings */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    /* Reset callback pointers to the weak predefined callbacks */
+    hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback  */
+    hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback  */
+    hdcmi->LineEventCallback  = HAL_DCMI_LineEventCallback;  /* Legacy weak LineEventCallback   */
+    hdcmi->ErrorCallback      = HAL_DCMI_ErrorCallback;      /* Legacy weak ErrorCallback       */
+
+    if (hdcmi->MspInitCallback == NULL)
+    {
+      /* Legacy weak MspInit Callback        */
+      hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+    }
+    /* Initialize the low level hardware (MSP) */
+    hdcmi->MspInitCallback(hdcmi);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_DCMI_MspInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
+  }
+
+  /* Change the DCMI state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B)
+  {
+    /* Byte select mode must be programmed to the reset value if the extended mode
+    is not set to 8-bit data capture on every pixel clock */
+    hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL;
+  }
+  /* Configures the HS, VS, DE and PC polarity */
+  hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 | \
+                           DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  | \
+                           DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \
+                           DCMI_CR_LSM | DCMI_CR_OELS);
+
+  hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
+                                    hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  | \
+                                    hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
+                                    hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \
+                                    hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \
+                                    hdcmi->Init.LineSelectStart);
+
+  if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+  {
+    hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    | \
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \
+                             ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
+
+  }
+
+  /* Enable the Line, Vsync, Error and Overrun interrupts */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+
+  /* Update error code */
+  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+  /* Initialize the DCMI state*/
+  hdcmi->State  = HAL_DCMI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DCMI peripheral registers to their default reset
+  *         values.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
+{
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+  if (hdcmi->MspDeInitCallback == NULL)
+  {
+    hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+  }
+  /* De-Initialize the low level hardware (MSP) */
+  hdcmi->MspDeInitCallback(hdcmi);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_DCMI_MspDeInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
+
+  /* Update error code */
+  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
+
+  /* Initialize the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DCMI MSP.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the DCMI MSP.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure destination address and data length and
+          Enables DCMI DMA request and enables DCMI capture
+      (+) Stop the DCMI capture.
+      (+) Handles DCMI interrupt request.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables DCMI DMA request and enables DCMI capture
+  * @param  hdcmi     pointer to a DCMI_HandleTypeDef structure that contains
+  *                    the configuration information for DCMI.
+  * @param  DCMI_Mode DCMI capture mode snapshot or continuous grab.
+  * @param  pData     The destination memory Buffer address (LCD Frame buffer).
+  * @param  Length    The length of capture to be transferred.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
+{
+  uint32_t tmp_length = Length;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cllr_offset;
+  uint32_t tmp1;
+  uint32_t tmp2;
+
+  /* Check function parameters */
+  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Enable DCMI by setting DCMIEN bit */
+  __HAL_DCMI_ENABLE(hdcmi);
+
+  /* Configure the DCMI Mode */
+  hdcmi->Instance->CR &= ~(DCMI_CR_CM);
+  hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
+
+  /* Set the DMA memory0 conversion complete callback */
+  hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
+
+  /* Set the DMA error callback */
+  hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
+
+  /* Set the dma abort callback */
+  hdcmi->DMA_Handle->XferAbortCallback = NULL;
+
+  /* Reset transfer counters value */
+  hdcmi->XferCount = 0;
+  hdcmi->XferTransferNumber = 0;
+  hdcmi->XferSize = 0;
+  hdcmi->pBuffPtr = 0;
+
+  /* Length should be converted to number of bytes */
+  tmp_length = tmp_length * 4U;
+
+  if (tmp_length <= 0xFFFFU)
+  {
+    /* Continuoues Mode */
+    /* Enable the DMA Stream */
+    if ((hdcmi->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hdcmi->DMA_Handle->LinkedListQueue != 0U) && (hdcmi->DMA_Handle->LinkedListQueue->Head != 0U))
+      {
+        /* Set Source , Destination , Length for DMA Xfer */
+
+        /* Set DMA data size           */
+        hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = tmp_length;
+        /* Set DMA source address      */
+        hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+            (uint32_t)&hdcmi->Instance->DR;
+        /* Set DMA destination address */
+        hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+        status = HAL_DMAEx_List_Start_IT(hdcmi->DMA_Handle);
+      }
+      else
+      {
+        /* Set Error Code */
+        hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+        /* Change DCMI state */
+        hdcmi->State = HAL_DCMI_STATE_READY;
+        /* Release Lock */
+        __HAL_UNLOCK(hdcmi);
+        /* Return function status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, tmp_length);
+    }
+  }
+  else /* DCMI_DOUBLE_BUFFER Mode */
+  {
+    /* Double buffering is used through 2 Nodes
+       Calculate the elementary size to be transferred by each node */
+
+    /* Initialize transfer parameters */
+    hdcmi->XferCount = 1;
+    hdcmi->XferSize = tmp_length;
+    hdcmi->pBuffPtr = pData;
+
+    /* Get the number of buffer */
+    while (hdcmi->XferSize > 0xFFFFU)
+    {
+      hdcmi->XferSize = (hdcmi->XferSize / 2U);
+      hdcmi->XferCount = hdcmi->XferCount * 2U;
+    }
+
+    /* Update DCMI counter  and transfer number*/
+    hdcmi->XferCount = (hdcmi->XferCount - 1U);
+    hdcmi->XferTransferNumber = hdcmi->XferCount;
+
+    if ((hdcmi->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hdcmi->DMA_Handle->LinkedListQueue != 0U) && (hdcmi->DMA_Handle->LinkedListQueue->Head != 0U))
+      {
+        /* Update first node */
+
+        /* Set DMA Data size */
+        hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hdcmi->XferSize ;
+
+        /* Set DMA Source address */
+        hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+            (uint32_t)&hdcmi->Instance->DR;
+
+        /* Set DMA Destination address */
+        hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+        /* Get CLLR offset */
+        cllr_offset = (hdcmi->DMA_Handle->LinkedListQueue->Head->NodeInfo & NODE_CLLR_IDX) >> 8U;
+
+        /* Update second node */
+        if (hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[cllr_offset] != 0U)
+        {
+          tmp1 = (uint32_t)hdcmi->DMA_Handle->LinkedListQueue->Head ;
+          tmp2 = hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[cllr_offset];
+          /* Update second node */
+
+          /* Set DMA Data size */
+          ((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
+                               (tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hdcmi->XferSize;
+
+          /* Set DMA Source address */
+          ((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
+                               (tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
+                                   (uint32_t)&hdcmi->Instance->DR;
+
+          /* Set DMA Destination address */
+          ((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
+                               (tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
+                                   (uint32_t)pData + hdcmi->XferSize;
+
+          if (HAL_DMAEx_List_Start_IT(hdcmi->DMA_Handle) != HAL_OK)
+          {
+            /* Set Error Code */
+            hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+            /* Change DCMI state */
+            hdcmi->State = HAL_DCMI_STATE_READY;
+            /* Release Lock */
+            __HAL_UNLOCK(hdcmi);
+            /* Return function status */
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /* Set Error Code */
+          hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+          /* Change DCMI state */
+          hdcmi->State = HAL_DCMI_STATE_READY;
+          /* Release Lock */
+          __HAL_UNLOCK(hdcmi);
+          /* Return function status */
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Set Error Code */
+        hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+        /* Change DCMI state */
+        hdcmi->State = HAL_DCMI_STATE_READY;
+        /* Release Lock */
+        __HAL_UNLOCK(hdcmi);
+        /* Return function status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set Error Code */
+      hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+      /* Change DCMI state */
+      hdcmi->State = HAL_DCMI_STATE_READY;
+      /* Release Lock */
+      __HAL_UNLOCK(hdcmi);
+      /* Return function status */
+      status = HAL_ERROR;
+    }
+  }
+  if (status == HAL_OK)
+  {
+    /* Enable Capture */
+    hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hdcmi);
+  }
+  else
+  {
+    /* Set Error Code */
+    hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_READY;
+    /* Release Lock */
+    __HAL_UNLOCK(hdcmi);
+    /* Return function status */
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Disable DCMI DMA request and Disable DCMI capture
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
+{
+  uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Disable Capture */
+  hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+  /* Check if the DCMI capture effectively disabled */
+  do
+  {
+    count-- ;
+    if (count == 0U)
+    {
+      /* Update error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+
+      status = HAL_TIMEOUT;
+      break;
+    }
+  } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+
+  /* Disable the DCMI */
+  __HAL_DCMI_DISABLE(hdcmi);
+
+  /* Disable the DMA */
+  (void)HAL_DMA_Abort(hdcmi->DMA_Handle);
+
+  /* Update error code */
+  hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
+
+  /* Change DCMI state */
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Suspend DCMI capture
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
+{
+  uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  if (hdcmi->State == HAL_DCMI_STATE_BUSY)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
+
+    /* Disable Capture */
+    hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+    /* Check if the DCMI capture effectively disabled */
+    do
+    {
+      count-- ;
+      if (count == 0U)
+      {
+        /* Update error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+
+        /* Change DCMI state */
+        hdcmi->State = HAL_DCMI_STATE_READY;
+
+        status = HAL_TIMEOUT;
+        break;
+      }
+    } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Resume DCMI capture
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+    /* Enable Capture */
+    hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles DCMI interrupt request.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for the DCMI.
+  * @retval None
+  */
+void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
+{
+  uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
+
+  /* Synchronization error interrupt management *******************************/
+  if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
+  {
+    /* Clear the Synchronization error flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
+
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
+
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+    /* Set the synchronization error callback */
+    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
+
+    /* Abort the DMA Transfer */
+    if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
+    {
+      DCMI_DMAError(hdcmi->DMA_Handle);
+    }
+  }
+  /* Overflow interrupt management ********************************************/
+  if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
+  {
+    /* Clear the Overflow flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
+
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
+
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_ERROR;
+
+    /* Set the overflow callback */
+    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
+
+    /* Abort the DMA Transfer */
+    if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
+    {
+      DCMI_DMAError(hdcmi->DMA_Handle);
+    }
+  }
+  /* Line Interrupt management ************************************************/
+  if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
+  {
+    /* Clear the Line interrupt flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
+
+    /* Line interrupt Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    /*Call registered DCMI line event callback*/
+    hdcmi->LineEventCallback(hdcmi);
+#else
+    HAL_DCMI_LineEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+  }
+  /* VSYNC interrupt management ***********************************************/
+  if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
+  {
+    /* Clear the VSYNC flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
+
+    /* VSYNC Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    /*Call registered DCMI vsync event callback*/
+    hdcmi->VsyncEventCallback(hdcmi);
+#else
+    HAL_DCMI_VsyncEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+  }
+  /* FRAME interrupt management ***********************************************/
+  if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
+  {
+    /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+    if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+    {
+      /* Disable the Line, Vsync, Error and Overrun interrupts */
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+    }
+
+    /* Disable the Frame interrupt */
+    __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+    /* Clear the End of Frame flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
+
+    /* Frame Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    /*Call registered DCMI frame event callback*/
+    hdcmi->FrameEventCallback(hdcmi);
+#else
+    HAL_DCMI_FrameEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Error DCMI callback.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Line Event callback.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_LineEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  VSYNC Event callback.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_VsyncEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Frame Event callback.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval None
+  */
+__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMI_FrameEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================
+[..]  This section provides functions allowing to:
+      (+) Configure the CROP feature.
+      (+) Enable/Disable the CROP feature.
+      (+) Set embedded synchronization delimiters unmasks.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DCMI CROP coordinate.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @param  YSize DCMI Line number
+  * @param  XSize DCMI Pixel per line
+  * @param  X0    DCMI window X offset
+  * @param  Y0    DCMI window Y offset
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
+                                      uint32_t YSize)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
+  assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
+
+  /* Configure CROP */
+  hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
+  hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
+
+  /* Initialize the DCMI state*/
+  hdcmi->State  = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Crop feature.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Disable DCMI Crop feature */
+  hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the Crop feature.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Enable DCMI Crop feature */
+  hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set embedded synchronization delimiters unmasks.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *               the configuration information for DCMI.
+  * @param  SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
+  *                    the embedded synchronization delimiters unmasks.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Write DCMI embedded synchronization unmask register */
+  hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \
+                           ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \
+                           ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \
+                           ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
+  *  @brief    Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+               ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DCMI state.
+      (+) Get the specific DCMI error flag.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the DCMI state
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL state
+  */
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi)
+{
+  return hdcmi->State;
+}
+
+/**
+  * @brief  Return the DCMI error code
+  * @param  hdcmi  pointer to a DCMI_HandleTypeDef structure that contains
+  *               the configuration information for DCMI.
+  * @retval DCMI Error Code
+  */
+uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi)
+{
+  return hdcmi->ErrorCode;
+}
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User DCMI Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hdcmi DCMI handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
+  *          @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
+  *          @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
+  *          @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
+                                            pDCMI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* update the error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hdcmi->State == HAL_DCMI_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DCMI_FRAME_EVENT_CB_ID :
+          hdcmi->FrameEventCallback = pCallback;
+          break;
+
+        case HAL_DCMI_VSYNC_EVENT_CB_ID :
+          hdcmi->VsyncEventCallback = pCallback;
+          break;
+
+        case HAL_DCMI_LINE_EVENT_CB_ID :
+          hdcmi->LineEventCallback = pCallback;
+          break;
+
+        case HAL_DCMI_ERROR_CB_ID :
+          hdcmi->ErrorCallback = pCallback;
+          break;
+
+        case HAL_DCMI_MSPINIT_CB_ID :
+          hdcmi->MspInitCallback = pCallback;
+          break;
+
+        case HAL_DCMI_MSPDEINIT_CB_ID :
+          hdcmi->MspDeInitCallback = pCallback;
+          break;
+
+        default :
+          /* Return error status */
+          status =  HAL_ERROR;
+          break;
+      }
+    }
+    else if (hdcmi->State == HAL_DCMI_STATE_RESET)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DCMI_MSPINIT_CB_ID :
+          hdcmi->MspInitCallback = pCallback;
+          break;
+
+        case HAL_DCMI_MSPDEINIT_CB_ID :
+          hdcmi->MspDeInitCallback = pCallback;
+          break;
+
+        default :
+          /* update the error code */
+          hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* update the error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a DCMI Callback
+  *         DCMI callback is redirected to the weak predefined callback
+  * @param  hdcmi DCMI handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
+  *          @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
+  *          @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
+  *          @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hdcmi->State == HAL_DCMI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMI_FRAME_EVENT_CB_ID :
+        hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback;  /* Legacy weak  FrameEventCallback  */
+        break;
+
+      case HAL_DCMI_VSYNC_EVENT_CB_ID :
+        hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback;  /* Legacy weak VsyncEventCallback   */
+        break;
+
+      case HAL_DCMI_LINE_EVENT_CB_ID :
+        hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback;    /* Legacy weak LineEventCallback    */
+        break;
+
+      case HAL_DCMI_ERROR_CB_ID :
+        hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback;           /* Legacy weak ErrorCallback         */
+        break;
+
+      case HAL_DCMI_MSPINIT_CB_ID :
+        hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+        break;
+
+      case HAL_DCMI_MSPDEINIT_CB_ID :
+        hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+        break;
+
+      default :
+        /* update the error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdcmi->State == HAL_DCMI_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMI_MSPINIT_CB_ID :
+        hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+        break;
+
+      case HAL_DCMI_MSPDEINIT_CB_ID :
+        hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+        break;
+
+      default :
+        /* update the error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update the error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Functions DCMI Private Functions
+  * @{
+  */
+/**
+  * @brief  DMA conversion complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+
+  DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  uint32_t tmp1;
+  uint32_t tmp2;
+  DMA_NodeTypeDef *pnode;
+  uint32_t pbuff;
+  uint32_t transfernumber;
+  uint32_t transfercount;
+  uint32_t transfersize ;
+
+  /* Update Nodes destinations */
+  if (hdcmi->XferSize != 0U)
+  {
+    pbuff          = hdcmi->pBuffPtr;
+    transfernumber = hdcmi->XferTransferNumber;
+    transfercount  = hdcmi->XferCount;
+    transfersize   = hdcmi->XferSize;
+
+    tmp1 = hdcmi->DMA_Handle->Instance->CLLR & DMA_CLLR_LA;
+    tmp2 = hdcmi->DMA_Handle->Instance->CLBAR & DMA_CLBAR_LBA;
+    pnode = (DMA_NodeTypeDef *)(uint32_t)(tmp1 | tmp2);
+
+    if (hdcmi->XferCount > 1U)
+    {
+      pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pbuff + ((transfernumber - transfercount + 2U) * transfersize);
+      hdcmi->XferCount--;
+    }
+
+    else if (hdcmi->XferCount == 1U)
+    {
+      pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = hdcmi->pBuffPtr;
+      hdcmi->XferCount--;
+    }
+    else
+    {
+      pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = hdcmi->pBuffPtr + hdcmi->XferSize;
+
+      /* When Continuous mode, re-set dcmi XferCount */
+      if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_CONTINUOUS)
+      {
+        hdcmi->XferCount = hdcmi->XferTransferNumber ;
+      }
+      /* When snapshot mode, set dcmi state to ready */
+      else
+      {
+        hdcmi->State = HAL_DCMI_STATE_READY;
+      }
+
+      __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+    }
+  }
+  else  /* Snapshot Mode */
+  {
+    /* Enable the Frame interrupt */
+    __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
+
+    /* When snapshot mode, set dcmi state to ready */
+    if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+    {
+      hdcmi->State = HAL_DCMI_STATE_READY;
+    }
+  }
+}
+
+/**
+  * @brief  DMA error callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_ULE)
+  {
+    /* Initialize the DCMI state*/
+    hdcmi->State = HAL_DCMI_STATE_READY;
+
+    /* Set DCMI Error Code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+  }
+
+  /* DCMI error Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+  /*Call registered DCMI error callback*/
+  hdcmi->ErrorCallback(hdcmi);
+#else
+  HAL_DCMI_ErrorCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+}
+
+/**
+  * @}
+  */
+#endif /* DCMI */
+#endif /* HAL_DCMI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dcmipp.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dcmipp.c
new file mode 100644
index 000000000..71982873c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dcmipp.c
@@ -0,0 +1,8530 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_dcmipp.c
+  * @author  MCD Application Team
+  * @brief   DCMIPP HAL module driver
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DCMIPP (Digital Camera Interface Pixel Pipeline)  peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+     The sequence below describes how to use this driver to capture image
+     from a camera module connected to the DCMIPP Interface.
+     This sequence does not take into account the configuration of the
+     camera module, which should be made before to configure and enable
+     the DCMIPP to capture images.
+
+
+
+Initialize the DCMIPP and the CSI through HAL_DCMIPP_Init() function.
+
+  *** Mandatory Configuration ***
+  ===================================
+The configuration of the camera sensor interface, in Parallel or CSI (Camera Serial Interface) modes,
+involves programming specific parameters to ensure proper functionality.
+Below is the structured process for configuring each interface type:
+
+     (#)Parallel Mode configuration
+        To configure the camera sensor in Parallel mode, program the following parameters:
+        the Format, the VSPolarity,the HSPolarity, the PCKPolarity, the ExtendedDataMode the SynchroMode,
+        the SynchroCodes of the frame delimiter, the SwapBits and the SwapCycles
+        using HAL_DCMIPP_PARALLEL_SetConfig() function.
+
+     (#)Serial Mode configuration (CSI)
+        To configure the camera in Serial mode, use the following functions to set the corresponding parameters:
+         + The NumberOfLanes, the DataLaneMapping and the PHYBitrate using HAL_DCMIPP_CSI_SetConfig() function.
+         + The DataTypeFormat for the selected Virtual Channel HAL_DCMIPP_CSI_SetVCConfig() function or
+           the DataTypeNB, the DataTypeClass and the DataTypeFormat for the selected Virtual Channel
+           using HAL_DCMIPP_CSI_SetVCFilteringConfig() function.
+         + The DataTypeMode, the DataTypeIDA, the DataTypeIDB using HAL_DCMIPP_CSI_PIPE_SetConfig() function.
+
+     (#)Pipe configuration
+Regardless of the interface type, the pipe configuration is necessary:
+         + To configure the Pipe , program the following parameters:
+           the FrameRate, the PixelPipePitch and PixelPackerFormat for pixel Pipes using
+           HAL_DCMIPP_PIPE_SetConfig() function.
+
+     (#)Default Shared Data Flow
+        By default, or by invoking HAL_DCMIPP_PIPE_CSI_EnableShare() ,the dataflow of PIPE1 is shared with PIPE2.
+        In this case the VC and DataType are the same as those configured for PIPE1 thus
+        data acquistion can be started for PIPE2 without any additional configuration.
+     (#)Disabling Shared Data Flow
+        The shared dataflow between Pixel Pipes can be disabled by calling HAL_DCMIPP_PIPE_CSI_DisableShare().
+        This action must be performed before starting data acquisition on either pipe
+        In this case the VC and DataType must be configured for Pipe2 separately.
+
+  *** Interrupt mode IO operation ***
+  ===================================
+
+    (##) Parallel Mode
+     (#) Configure Pipe parameters, destination (one or two) and Capture Mode (Snapshot or Continuous) and enable
+         the capture request using one from the following functions:
+         HAL_DCMIPP_PIPE_Start() or HAL_DCMIPP_PIPE_DoubleBufferStart().
+
+         Configure DCMIPP_PIPE1, destination addresses (Y and UV addresses) and Capture Mode (Snapshot or Continuous)
+         and enable the capture request for Semi-planar using one from the following functions :
+         HAL_DCMIPP_PIPE_SemiPlanarStart() or HAL_DCMIPP_PIPE_SemiPlanarDoubleBufferStart().
+
+         Configure DCMIPP_PIPE1, destination addresses (Y, U and V addresses) and Capture Mode (Snapshot or Continuous)
+         and enable the capture request for full-planar buffer using one from the following functions:
+         HAL_DCMIPP_PIPE_FullPlanarStart() or HAL_DCMIPP_PIPE_FullPlanarDoubleBufferStart().
+
+    (##) Serial Mode
+     (#) Configure Pipe parameter, Virtual Channel, destination (one or two) and Capture Mode (Snapshot or Continuous)
+         and enable the capture request using the following functions:
+         HAL_DCMIPP_CSI_PIPE_Start() or HAL_DCMIPP_CSI_PIPE_DoubleBufferStart().
+
+         Configure DCMIPP_PIPE1, Virtual Channel, destination addresses (Y and UV addresses) and Capture Mode
+        (Snapshot or Continuous) and enable the capture request for Semi-planar buffer using
+         the following functions:
+         HAL_DCMIPP_CSI_PIPE_SemiPlanarStart() or HAL_DCMIPP_CSI_PIPE_SemiPlanarDoubleBufferStart().
+
+         Configure DCMIPP_PIPE1, Virtual Channel, destination addresses (Y, U and V addresses) and Capture Mode
+        (Snapshot or Continuous) and enable the capture request for Semi-planar buffer
+         using the following functions:
+         HAL_DCMIPP_CSI_PIPE_FullPlanarStart() or HAL_DCMIPP_CSI_PIPE_FullPlanarDoubleBufferStart().
+
+     (#) Use HAL_DCMIPP_IRQHandler() called under DCMIPP_IRQHandler() interrupt subroutine.
+     (#) At the end of frame capture request HAL_DCMIPP_IRQHandler() function is executed and user can
+         add his own function by customization of function pointer PipeFrameEventCallback (member
+         of DCMIPP handle structure).
+
+   (#) Use HAL_DCMIPP_CSI_IRQHandler() called under CSI_IRQHandler() interrupt subroutine.
+   (#) At the start or the end of frame capture HAL_DCMIPP_CSI_IRQHandler() function is executed and user can
+       add his own function by customization of function pointer StartOfFrameEventCallback or EndOfFrameEventCallback.
+
+    (#) In case of common error, the HAL_DCMIPP_IRQHandler() function calls the callback
+         ErrorCallback, in case of Pipe error the HAL_DCMIPP_IRQHandler() function calls the callback PIPE_ErrorCallback
+     and in case of CSI Line error the HAL_DCMIPP_CSI_IRQHandler() function calls the callback
+         LineErrorCallback.
+
+    (#) The Pipe capture can be suspended and resumed using the following functions
+        HAL_DCMIPP_PIPE_Suspend() and HAL_DCMIPP_PIPE_Resume().
+
+    (#) For Snapshot Mode the capture can be re-enabled using the HAL_DCMIPP_PIPE_EnableCapture();
+
+    (#) Optionally, Program the required configuration through the following parameters:
+        Client, MemoryPageSize, Traffic, MaxOutstandingTransactions, DPREGStart, DPREGEnd
+        and WLRURatio using HAL_DCMIPP_SetIPPlugConfig().
+
+    (#) Optionally, configure and Enable the CROP feature to select a rectangular
+        window from the received image using HAL_DCMIPP_PIPE_SetCropConfig()
+        and HAL_DCMIPP_PIPE_EnableCrop() functions.
+
+    (#) Optionally, configure and Enable the line and bytes decimation features
+        using the following functions HAL_DCMIPP_PIPE_SetLinesDecimationConfig and
+        HAL_DCMIPP_PIPE_SetBytesDecimationConfig.
+
+    (#) Optionally, configure and enable the line event using the function HAL_DCMIPP_PIPE_EnableLineEvent().
+
+    (#) Optionally, configure and enable the Limit event using the function HAL_DCMIPP_PIPE_EnableLimitEvent().
+
+    (#) If needed, reconfigure and change the input pixel format value, the frame rate
+        value, the capture Mode , the destination memory address , the syncunmask values,
+        Multiline value and Limit value using respectively
+        the following functions: HAL_DCMIPP_PIPE_SetInputPixelFormat(), HAL_DCMIPP_PIPE_SetFrameRate(),
+        HAL_DCMIPP_PIPE_SetCaptureMode(), HAL_DCMIPP_PIPE_SetMemoryAddress(), HAL_DCMIPP_SetSyncUnmask(),
+        HAL_DCMIPP_PIPE_EnableLineEvent() and HAL_DCMIPP_PIPE_EnableLimitEvent().
+
+    (#) To read the transferred data counter , use the HAL_DCMIPP_PIPE_GetDataCounter()
+
+    (#) To read and reset the Frame counter of the pipe, use the following functions:
+        HAL_DCMIPP_PIPE_ReadFrameCounter() and HAL_DCMIPP_PIPE_ResetFrameCounter().
+
+    (#) The Pipe capture in parallel mode can be Stopped using HAL_DCMIPP_PIPE_Stop() function.
+    (#) The Pipe capture in serial mode can be Stopped using HAL_DCMIPP_CSI_PIPE_Stop() function.
+    (#) To control the DCMIPP state, use the following function: HAL_DCMIPP_GetState().
+
+    (#) To control the DCMIPP Pipe state, use the following function: HAL_DCMIPP_PIPE_GetState().
+
+    (#) To read the DCMIPP error code, use the following function: HAL_DCMIPP_GetError().
+
+  *** DCMIPP HAL driver macros list ***
+  =============================================
+  [..]
+     Below the list of most used macros in DCMIPP HAL driver :
+
+     (+) __HAL_DCMIPP_GET_FLAG: Get the DCMIPP pending flags.
+     (+) __HAL_DCMIPP_CLEAR_FLAG: Clear the DCMIPP pending flags.
+     (+) __HAL_DCMIPP_ENABLE_IT: Enable the specified DCMIPP interrupts.
+     (+) __HAL_DCMIPP_DISABLE_IT: Disable the specified DCMIPP interrupts.
+     (+) __HAL_DCMIPP_GET_IT_SOURCE: Check whether the specified DCMIPP interrupt is enabled or not.
+     (+) __HAL_DCMIPP_CSI_GET_FLAG: Get the CSI pending flags.
+     (+) __HAL_DCMIPP_CSI_CLEAR_FLAG: Clear the CSI pending flags.
+     (+) __HAL_DCMIPP_CSI_ENABLE_IT: Enable the specified CSI interrupts.
+     (+) __HAL_DCMIPP_CSI_DISABLE_IT: Disable the specified CSI interrupts.
+     (+) __HAL_DCMIPP_CSI_GET_IT_SOURCE: Check whether the specified CSI interrupt is enabled or not.
+
+  *** Callback registration ***
+  ===================================
+  [..]
+     (#) The compilation define  USE_HAL_DCMIPP_REGISTER_CALLBACKS when set to 1
+          allows the user to configure dynamically the driver callbacks.
+          Use function @ref HAL_DCMIPP_RegisterCallback() to register a user callback.
+          Use function @ref HAL_DCMIPP_PIPE_RegisterCallback() to register a user pipe callback.
+
+     (#) Function @ref HAL_DCMIPP_RegisterCallback() allows to register following callbacks:
+         (+) ErrorCallback          : callback for Error
+         (+) MspInitCallback        : DCMIPP MspInit.
+         (+) MspDeInitCallback      : DCMIPP MspDeInit.
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+     (#) Function @ref HAL_DCMIPP_PIPE_RegisterCallback() allows to register following callbacks:
+         (+) PIPE_FrameEventCallback : callback for Pipe Frame Event.
+         (+) PIPE_VsyncEventCallback : callback for Pipe Vsync Event.
+         (+) PIPE_LineEventCallback  : callback for Pipe Line Event.
+         (+) PIPE_LimitEventCallback : callback for Pipe Limit Event.
+         (+) PIPE_ErrorCallback      : callback for Pipe Error
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+     (#) Use function @ref HAL_DCMIPP_UnRegisterCallback() to reset a callback to the default
+         weak (surcharged) function.
+         @ref HAL_DCMIPP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+         and the Callback ID.
+         This function allows to reset following callbacks:
+         (+) ErrorCallback          : callback for Error
+         (+) MspInitCallback        : DCMIPP MspInit.
+         (+) MspDeInitCallback      : DCMIPP MspDeInit.
+     (#) Use function @ref HAL_DCMIPP_PIPE_UnRegisterCallback() to reset a pipe callback to the default
+         weak (surcharged) function.
+         @ref HAL_DCMIPP_PIPE_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+         and the Callback ID.
+         This function allows to reset following callbacks:
+         (+) PIPE_FrameEventCallback : callback for Pipe Frame Event.
+         (+) PIPE_VsyncEventCallback : callback for Pipe Vsync Event.
+         (+) PIPE_LineEventCallback  : callback for Pipe Line Event.
+         (+) PIPE_LimitEventCallback : callback for Pipe Limit Event.
+         (+) PIPE_ErrorCallback      : callback for Pipe Error
+
+     (#) By default, after the @ref HAL_DCMIPP_Init and if the state is HAL_DCMIPP_STATE_RESET
+         all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+         examples @ref PipeFrameEventCallback(), @ref PipeVsyncEventCallback()
+         Exception done for MspInit and MspDeInit callbacks that are respectively
+         reset to the legacy weak (surcharged) functions in the @ref HAL_DCMIPP_Init
+         and @ref HAL_DCMIPP_DeInit only when these callbacks are null (not registered beforehand)
+         If not, MspInit or MspDeInit are not null, the @ref HAL_DCMIPP_Init and @ref HAL_DCMIPP_DeInit
+         keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+         Callbacks can be registered/unregistered in READY state only.
+         Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+         in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+         during the Init/DeInit.
+         In that case first register the MspInit/MspDeInit user callbacks
+         using @ref HAL_DCMIPP_RegisterCallback before calling @ref HAL_DCMIPP_DeInit
+         or @ref HAL_DCMIPP_Init function.
+
+         When The compilation define USE_HAL_DCMIPP_REGISTER_CALLBACKS is set to 0 or
+         not defined, the callback registering feature is not available
+         and weak (surcharged) callbacks are used.
+
+     [..]
+      (@) You can refer to the DCMIPP HAL driver header file for more useful macros
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+#ifdef HAL_DCMIPP_MODULE_ENABLED
+#if defined (DCMIPP)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+/** @defgroup DCMIPP DCMIPP
+  * @brief DCMIPP HAL module driver
+  * @{
+  */
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DCMIPP_Private_Constants DCMIPP Private Constants
+  * @{
+  */
+#define READ_FIELD(REG, MASK)  ((REG) & (MASK))
+
+#define MATRIX_VALUE11(value) ((((value) & 0x8000U) == 0x8000U) ? ((value) & 0x07FFU) : (value))
+#define MATRIX_VALUE10(value) ((((value) & 0x8000U) == 0x8000U) ? ((value) & 0x03FFU) : (value))
+#define GET_MATRIX_VALUE11(value) ((((value) & 0x400U) == 0x400U) ? ((uint16_t)((value) | 0xF800U)) : (value))
+#define GET_MATRIX_VALUE10(value) ((((value) & 0x200U) == 0x200U) ? ((uint16_t)((value) | 0xFC00U)) : (value))
+#define DCMIPP_TIMEOUT 1000U  /*!<  1s  */
+/**
+  * @}
+  */
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup DCMIPP_Private_TypeDef DCMIPP Private TypeDef
+  * @{
+  */
+/*
+ * Table of hsfreqrange & osc_freq_target for the Synopsis D-PHY
+ */
+typedef struct
+{
+  uint32_t hsfreqrange;
+  uint32_t osc_freq_target;
+} SNPS_FreqsTypeDef;
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions
+  * @{
+  */
+static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig);
+static void DCMIPP_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, uint32_t CaptureMode);
+static void DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
+                                uint32_t DstAddress1, uint32_t CaptureMode);
+static void DCMIPP_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+static HAL_StatusTypeDef DCMIPP_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
+static void DCMIPP_CSI_WritePHYReg(CSI_TypeDef *hcsi, uint32_t reg_msb, uint32_t reg_lsb, uint32_t val);
+static HAL_StatusTypeDef DCMIPP_CSI_SetVCConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel);
+static HAL_StatusTypeDef DCMIPP_CSI_VCStop(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DCMIPP_Exported_Functions DCMIPP Exported Functions
+  * @{
+  */
+
+/** @addtogroup DCMIPP_Initialization_De-Initialization_Functions DCMIPP Initialization De-Initialization Functions
+  *  @brief     Initialization and De-Initialization Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the selected HAL DCMIPP handle and associate a DCMIPP peripheral instance.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_Init(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  uint32_t pipe_index;
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_RESET)
+  {
+    /* Init the DCMIPP Callback settings */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+    /* Reset callback pointers to the weak predefined callbacks */
+    hdcmipp->PIPE_FrameEventCallback = HAL_DCMIPP_PIPE_FrameEventCallback;
+    hdcmipp->PIPE_VsyncEventCallback = HAL_DCMIPP_PIPE_VsyncEventCallback;
+    hdcmipp->PIPE_LineEventCallback  = HAL_DCMIPP_PIPE_LineEventCallback;
+    hdcmipp->PIPE_LimitEventCallback = HAL_DCMIPP_PIPE_LimitEventCallback;
+    hdcmipp->PIPE_ErrorCallback      = HAL_DCMIPP_PIPE_ErrorCallback;
+    hdcmipp->ErrorCallback           = HAL_DCMIPP_ErrorCallback;
+    hdcmipp->LineErrorCallback         = HAL_DCMIPP_CSI_LineErrorCallback;
+    hdcmipp->EndOfFrameEventCallback   = HAL_DCMIPP_CSI_EndOfFrameEventCallback;
+    hdcmipp->TimerCounterEventCallback = HAL_DCMIPP_CSI_TimerCounterEventCallback;
+    hdcmipp->StartOfFrameEventCallback = HAL_DCMIPP_CSI_StartOfFrameEventCallback;
+    hdcmipp->LineByteEventCallback     = HAL_DCMIPP_CSI_LineByteEventCallback;
+    hdcmipp->ClockChangerFifoFullEventCallback = HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback;
+    hdcmipp->ShortPacketDetectionEventCallback = HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback;
+    if (hdcmipp->MspInitCallback == NULL)
+    {
+      /* Legacy weak MspInit Callback        */
+      hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit;
+    }
+    /* Initialize the low level hardware (MSP) */
+    hdcmipp->MspInitCallback(hdcmipp);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_DCMIPP_MspInit(hdcmipp);
+#endif /* (USE_HAL_DCMIPP_REGISTER_CALLBACKS) */
+  }
+
+  /* Change the DCMIPP state */
+  hdcmipp->State = HAL_DCMIPP_STATE_BUSY;
+
+  /* Reset DCMIPP Pipe state */
+  for (pipe_index = 0U; pipe_index < DCMIPP_NUM_OF_PIPES; pipe_index++)
+  {
+    hdcmipp->PipeState[pipe_index] = HAL_DCMIPP_PIPE_STATE_RESET;
+  }
+
+  /* Update error code */
+  hdcmipp->ErrorCode = HAL_DCMIPP_ERROR_NONE;
+
+  /* Update the DCMIPP state*/
+  hdcmipp->State = HAL_DCMIPP_STATE_INIT;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initializes the DCMIPP peripheral registers to their default reset values.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_DeInit(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  uint32_t pipe_index;
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the parallel Interface */
+  if ((hdcmipp->Instance->CMCR & DCMIPP_CMCR_INSEL) == DCMIPP_PARALLEL_MODE)
+  {
+    CLEAR_BIT(hdcmipp->Instance->PRCR, DCMIPP_PRCR_ENABLE);
+  }
+  else
+  {
+    CLEAR_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+  }
+
+  /* Reset flow selection configuration register for all the available pipes */
+  hdcmipp->Instance->P0FSCR = 0;
+  hdcmipp->Instance->P1FSCR = 0;
+  hdcmipp->Instance->P2FSCR = 0;
+  /* PowerDown the D-PHY_RX lane(s) etc */
+  CLEAR_REG(csi_instance->PCR);
+
+  /* Disable the CSI */
+  CLEAR_BIT(csi_instance->CR, CSI_CR_CSIEN);
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+  if (hdcmipp->MspDeInitCallback == NULL)
+  {
+    hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hdcmipp->MspDeInitCallback(hdcmipp);
+#else
+  /* DeInit the low level hardware */
+  HAL_DCMIPP_MspDeInit(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+
+  /* Update error code */
+  hdcmipp->ErrorCode = HAL_DCMIPP_ERROR_NONE;
+
+  /* Initialize the DCMIPP state*/
+  hdcmipp->State = HAL_DCMIPP_STATE_RESET;
+
+  /* Reset DCMIPP Pipe state */
+  for (pipe_index = 0U; pipe_index < DCMIPP_NUM_OF_PIPES; pipe_index++)
+  {
+    hdcmipp->PipeState[pipe_index] = HAL_DCMIPP_PIPE_STATE_RESET;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DCMIPP MSP.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval None
+  */
+__weak void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmipp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initializes the DCMIPP MSP.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval None
+  */
+__weak void HAL_DCMIPP_MspDeInit(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmipp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_MspDeInit could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Configuration_Functions DCMIPP Configuration Functions
+  * @brief    Configuration Functions
+  * @{
+  */
+/**
+  * @brief  Configure the DCMIPP Parallel Interface according to the user parameters.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  pParallelConfig pointer to DCMIPP_ParallelConfTypeDef that contains
+  *                         the parallel Interface configuration information for DCMIPP.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetConfig(DCMIPP_HandleTypeDef *hdcmipp,
+                                                const DCMIPP_ParallelConfTypeDef *pParallelConfig)
+{
+  uint32_t prcr_reg;
+  uint32_t prescr_reg;
+
+  /* Check parameters */
+  if ((hdcmipp == NULL) || (pParallelConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_DCMIPP_FORMAT(pParallelConfig->Format));
+  assert_param(IS_DCMIPP_VSPOLARITY(pParallelConfig->VSPolarity));
+  assert_param(IS_DCMIPP_HSPOLARITY(pParallelConfig->HSPolarity));
+  assert_param(IS_DCMIPP_PCKPOLARITY(pParallelConfig->PCKPolarity));
+  assert_param(IS_DCMIPP_EXTENDED_DATA_MODE(pParallelConfig->ExtendedDataMode));
+  assert_param(IS_DCMIPP_SYNC_MODE(pParallelConfig->SynchroMode));
+  assert_param(IS_DCMIPP_SWAP_BITS(pParallelConfig->SwapBits));
+  assert_param(IS_DCMIPP_SWAP_CYCLES(pParallelConfig->SwapCycles));
+
+  /* Check DCMIPP state */
+  if (hdcmipp->State != HAL_DCMIPP_STATE_INIT)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Configures the Format, VS, HS, PCK polarity, ExtendedDataMode, SynchronisationMode, Swap Cycles and bits */
+    prcr_reg  = ((pParallelConfig->Format)           | \
+                 (pParallelConfig->VSPolarity)       | \
+                 (pParallelConfig->HSPolarity)       | \
+                 (pParallelConfig->PCKPolarity)      | \
+                 (pParallelConfig->ExtendedDataMode) | \
+                 (pParallelConfig->SynchroMode)      | \
+                 (pParallelConfig->SwapCycles)       | \
+                 (pParallelConfig->SwapBits));
+
+    WRITE_REG(hdcmipp->Instance->PRCR, prcr_reg);
+
+    if (pParallelConfig->SynchroMode == DCMIPP_SYNCHRO_EMBEDDED)
+    {
+      /* Set Embedded Sync codes */
+      prescr_reg = (((uint32_t)pParallelConfig->SynchroCodes.FrameEndCode << DCMIPP_PRESCR_FEC_Pos)   | \
+                    ((uint32_t)pParallelConfig->SynchroCodes.LineEndCode << DCMIPP_PRESCR_LEC_Pos)    | \
+                    ((uint32_t)pParallelConfig->SynchroCodes.FrameStartCode << DCMIPP_PRESCR_FSC_Pos) | \
+                    ((uint32_t)pParallelConfig->SynchroCodes.LineStartCode << DCMIPP_PRESCR_LSC_Pos));
+
+      WRITE_REG(hdcmipp->Instance->PRESCR, prescr_reg);
+
+      /* Set Embedded Sync Unmask codes : All codes are unmasked */
+      WRITE_REG(hdcmipp->Instance->PRESUR, 0xFFFFFFFFU);
+    }
+
+    /* Enable the Synchronization error interrupt on parallel interface */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PARALLEL_SYNC_ERROR);
+
+    /* Enable Parallel interface */
+    SET_BIT(hdcmipp->Instance->PRCR, DCMIPP_PRCR_ENABLE);
+
+    /* Set Parallel Input Selection */
+    CLEAR_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+  }
+
+  /* Update the DCMIPP state */
+  hdcmipp->State = HAL_DCMIPP_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DCMIPP Serial Interface according to the user parameters.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  pCSI_Config pointer to DCMIPP_CSI_ConfTypeDef that contains the Serial Interface
+  *                     configuration information for DCMIPP.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetConfig(const DCMIPP_HandleTypeDef *hdcmipp,
+                                           const DCMIPP_CSI_ConfTypeDef *pCSI_Config)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  const SNPS_FreqsTypeDef SNPS_Freqs[63] =
+  {
+    { 0x00U, 460U },  /* HAL_CSI_BT_80 */
+    { 0x10U, 460U },  /* HAL_CSI_BT_90 */
+    { 0x20U, 460U },  /* HAL_CSI_BT_100 */
+    { 0x30U, 460U },  /* HAL_CSI_BT_110 */
+    { 0x01U, 460U },  /* HAL_CSI_BT_120 */
+    { 0x11U, 460U },  /* HAL_CSI_BT_130 */
+    { 0x21U, 460U },  /* HAL_CSI_BT_140 */
+    { 0x31U, 460U },  /* HAL_CSI_BT_150 */
+    { 0x02U, 460U },  /* HAL_CSI_BT_160 */
+    { 0x12U, 460U },  /* HAL_CSI_BT_170 */
+    { 0x22U, 460U },  /* HAL_CSI_BT_180 */
+    { 0x32U, 460U },  /* HAL_CSI_BT_190 */
+    { 0x03U, 460U },  /* HAL_CSI_BT_205 */
+    { 0x13U, 460U },  /* HAL_CSI_BT_220 */
+    { 0x23U, 460U },  /* HAL_CSI_BT_235 */
+    { 0x33U, 460U },  /* HAL_CSI_BT_250 */
+    { 0x04U, 460U },  /* HAL_CSI_BT_275 */
+    { 0x14U, 460U },  /* HAL_CSI_BT_300 */
+    { 0x25U, 460U },  /* HAL_CSI_BT_325 */
+    { 0x35U, 460U },  /* HAL_CSI_BT_350 */
+    { 0x05U, 460U },  /* HAL_CSI_BT_400 */
+    { 0x16U, 460U },  /* HAL_CSI_BT_450 */
+    { 0x26U, 460U },  /* HAL_CSI_BT_500 */
+    { 0x37U, 460U },  /* HAL_CSI_BT_550 */
+    { 0x07U, 460U },  /* HAL_CSI_BT_600 */
+    { 0x18U, 460U },  /* HAL_CSI_BT_650 */
+    { 0x28U, 460U },  /* HAL_CSI_BT_700 */
+    { 0x39U, 460U },  /* HAL_CSI_BT_750 */
+    { 0x09U, 460U },  /* HAL_CSI_BT_800 */
+    { 0x19U, 460U },  /* HAL_CSI_BT_850 */
+    { 0x29U, 460U },  /* HAL_CSI_BT_900 */
+    { 0x3AU, 460U },  /* HAL_CSI_BT_950 */
+    { 0x0AU, 460U },  /* HAL_CSI_BT_1000 */
+    { 0x1AU, 460U },  /* HAL_CSI_BT_1050 */
+    { 0x2AU, 460U },  /* HAL_CSI_BT_1100 */
+    { 0x3BU, 460U },  /* HAL_CSI_BT_1150 */
+    { 0x0BU, 460U },  /* HAL_CSI_BT_1200 */
+    { 0x1BU, 460U },  /* HAL_CSI_BT_1250 */
+    { 0x2BU, 460U },  /* HAL_CSI_BT_1300 */
+    { 0x3CU, 460U },  /* HAL_CSI_BT_1350 */
+    { 0x0CU, 460U },  /* HAL_CSI_BT_1400 */
+    { 0x1CU, 460U },  /* HAL_CSI_BT_1450 */
+    { 0x2CU, 460U },  /* HAL_CSI_BT_1500 */
+    { 0x3DU, 285U },  /* HAL_CSI_BT_1550 */
+    { 0x0DU, 295U },  /* HAL_CSI_BT_1600 */
+    { 0x1DU, 304U },  /* HAL_CSI_BT_1650 */
+    { 0x2EU, 313U },  /* HAL_CSI_BT_1700 */
+    { 0x3EU, 322U },  /* HAL_CSI_BT_1750 */
+    { 0x0EU, 331U },  /* HAL_CSI_BT_1800 */
+    { 0x1EU, 341U },  /* HAL_CSI_BT_1850 */
+    { 0x2FU, 350U },  /* HAL_CSI_BT_1900 */
+    { 0x3FU, 359U },  /* HAL_CSI_BT_1950 */
+    { 0x0FU, 368U },  /* HAL_CSI_BT_2000 */
+    { 0x40U, 377U },  /* HAL_CSI_BT_2050 */
+    { 0x41U, 387U },  /* HAL_CSI_BT_2100 */
+    { 0x42U, 396U },  /* HAL_CSI_BT_2150 */
+    { 0x43U, 405U },  /* HAL_CSI_BT_2200 */
+    { 0x44U, 414U },  /* HAL_CSI_BT_2250 */
+    { 0x45U, 423U },  /* HAL_CSI_BT_2300 */
+    { 0x46U, 432U },  /* HAL_CSI_BT_2350 */
+    { 0x47U, 442U },  /* HAL_CSI_BT_2400 */
+    { 0x48U, 451U },  /* HAL_CSI_BT_2450 */
+    { 0x49U, 460U },  /* HAL_CSI_BT_2500 */
+  };
+
+  /* Check parameters */
+  if ((hdcmipp == NULL) || (pCSI_Config == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_NUMBER_OF_LANES(pCSI_Config->NumberOfLanes));
+  assert_param(IS_DCMIPP_CSI_DATA_LANE_MAPPING(pCSI_Config->DataLaneMapping));
+  assert_param(IS_DCMIPP_CSI_DATA_PHY_BITRATE(pCSI_Config->PHYBitrate));
+
+  /* Ensure the CSI is disabled */
+  CLEAR_BIT(csi_instance->CR, CSI_CR_CSIEN);
+
+  /* Configure the Lane Merger */
+  if (pCSI_Config->DataLaneMapping == DCMIPP_CSI_PHYSICAL_DATA_LANES)
+  {
+    WRITE_REG(csi_instance->LMCFGR, pCSI_Config->NumberOfLanes | (DCMIPP_CSI_DATA_LANE0 << CSI_LMCFGR_DL0MAP_Pos) | \
+              (DCMIPP_CSI_DATA_LANE1 << CSI_LMCFGR_DL1MAP_Pos));
+  }
+  else if (pCSI_Config->DataLaneMapping == DCMIPP_CSI_INVERTED_DATA_LANES)
+  {
+    WRITE_REG(csi_instance->LMCFGR, pCSI_Config->NumberOfLanes | (DCMIPP_CSI_DATA_LANE1 << CSI_LMCFGR_DL0MAP_Pos) | \
+              (DCMIPP_CSI_DATA_LANE0 << CSI_LMCFGR_DL1MAP_Pos));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the CSI */
+  SET_BIT(csi_instance->CR, CSI_CR_CSIEN);
+
+  /* Enable some interrupts, not related to virtual channels - all error cases */
+  __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_CCFIFO |  DCMIPP_CSI_IT_SYNCERR | \
+                             DCMIPP_CSI_IT_SPKTERR | DCMIPP_CSI_IT_IDERR | \
+                             DCMIPP_CSI_IT_SPKT);
+
+  /* Enable D-PHY Interrupts */
+  if (pCSI_Config->NumberOfLanes == DCMIPP_CSI_ONE_DATA_LANE)
+  {
+    if (pCSI_Config->DataLaneMapping == DCMIPP_CSI_PHYSICAL_DATA_LANES)
+    {
+      __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL0 | DCMIPP_CSI_IT_ESOTSYNCDL0 |
+                                      DCMIPP_CSI_IT_EESCDL0 | DCMIPP_CSI_IT_ESYNCESCDL0 |
+                                      DCMIPP_CSI_IT_ECTRLDL0);
+    }
+    else
+    {
+      __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL1 | DCMIPP_CSI_IT_ESOTSYNCDL1 |
+                                      DCMIPP_CSI_IT_EESCDL1 | DCMIPP_CSI_IT_ESYNCESCDL1 |
+                                      DCMIPP_CSI_IT_ECTRLDL1);
+    }
+  }
+  else
+  {
+    __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL1 | DCMIPP_CSI_IT_ESOTSYNCDL1 |
+                                    DCMIPP_CSI_IT_EESCDL1 | DCMIPP_CSI_IT_ESYNCESCDL1 |
+                                    DCMIPP_CSI_IT_ECTRLDL1 |
+                                    DCMIPP_CSI_IT_ESOTDL0 | DCMIPP_CSI_IT_ESOTSYNCDL0 |
+                                    DCMIPP_CSI_IT_EESCDL0 | DCMIPP_CSI_IT_ESYNCESCDL0 |
+                                    DCMIPP_CSI_IT_ECTRLDL0);
+  }
+
+  /* Start D-PHY Configuration */
+  /* Stop the D-PHY */
+  CLEAR_BIT(csi_instance->PRCR, CSI_PRCR_PEN);
+
+  /* Get the D-PHY enabledb but with all lanes disabled */
+  CLEAR_REG(csi_instance-> PCR);
+
+  /* Set the testclk (clock enable) on during 15ns */
+  SET_BIT(csi_instance->PTCR0, CSI_PTCR0_TCKEN);
+
+  HAL_Delay(1);
+
+  CLEAR_REG(csi_instance->PTCR0);
+
+  /* Set hsfreqrange */
+  MODIFY_REG(csi_instance->PFCR, CSI_PFCR_HSFR, (0x28U << CSI_PFCR_CCFR_Pos) |
+             (SNPS_Freqs[pCSI_Config->PHYBitrate].hsfreqrange << CSI_PFCR_HSFR_Pos));
+
+  /* set reg @08 deskew_polarity_rw 1'b1 */
+  DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0x08, 0x38);
+
+  /* set reg @0xE4 counter_for_des_en_config_if_rx 0x10 + DLL prog EN */
+  /* This is because 13<= cfgclkfreqrange[5:0]<=38 */
+  DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0xe4, 0x11);
+
+  /* set reg @0xe3 & reg @0xe2 value DLL target oscilation freq */
+  /* Based on the table page 77, osc_freq_target */
+  DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0xe3, SNPS_Freqs[pCSI_Config->PHYBitrate].osc_freq_target >> 8);
+  DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0xe3, SNPS_Freqs[pCSI_Config->PHYBitrate].osc_freq_target & 0xFFU);
+
+  /* set basedir_0 to RX DLD 0 RX, 1 TX. Synopsys 1 RX 0 TX  + freq range */
+  WRITE_REG(csi_instance-> PFCR, (0x28U << CSI_PFCR_CCFR_Pos) |
+            (SNPS_Freqs[pCSI_Config->PHYBitrate].hsfreqrange << CSI_PFCR_HSFR_Pos) | CSI_PFCR_DLD);
+
+  /* Enable the D-PHY_RX lane(s) etc */
+  if (pCSI_Config->NumberOfLanes == DCMIPP_CSI_ONE_DATA_LANE)
+  {
+    WRITE_REG(csi_instance->PCR, CSI_PCR_DL0EN | CSI_PCR_CLEN | CSI_PCR_PWRDOWN);
+  }
+  else
+  {
+    WRITE_REG(csi_instance->PCR, CSI_PCR_DL0EN | CSI_PCR_DL1EN | CSI_PCR_CLEN | CSI_PCR_PWRDOWN);
+  }
+
+
+  /* Enable PHY, out of reset */
+  SET_BIT(csi_instance->PRCR, CSI_PRCR_PEN);
+
+  /* Remove the force */
+  CLEAR_REG(csi_instance->PMCR);
+
+  return HAL_OK;
+
+}
+/**
+  * @brief  Configure the DCMIPP Pipe according to the user parameters.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Pipe            Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pCSI_PipeConfig pointer to DCMIPP_CSI_PIPE_ConfTypeDef that contains
+  *                         the CSI Pipe configuration information for DCMIPP.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                const DCMIPP_CSI_PIPE_ConfTypeDef *pCSI_PipeConfig)
+{
+  uint32_t pxfscr_reg = 0;
+  HAL_DCMIPP_StateTypeDef state;
+
+  /* Check the DCMIPP peripheral handle parameter and pCSI_Config parameter */
+  if ((hdcmipp == NULL) || (pCSI_PipeConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_DATA_TYPE_MODE(pCSI_PipeConfig->DataTypeMode));
+
+  if (Pipe != DCMIPP_PIPE2)
+  {
+    assert_param(IS_DCMIPP_DATA_TYPE_MODE(pCSI_PipeConfig->DataTypeMode));
+
+    if ((pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_DTIDA_OR_DTIDB)
+        || (pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB))
+    {
+      assert_param(IS_DCMIPP_DATA_TYPE(pCSI_PipeConfig->DataTypeIDB));
+    }
+  }
+
+  if (pCSI_PipeConfig->DataTypeMode != DCMIPP_DTMODE_ALL)
+  {
+    assert_param(IS_DCMIPP_DATA_TYPE(pCSI_PipeConfig->DataTypeIDA));
+  }
+
+  state = hdcmipp->State;
+  if ((state == HAL_DCMIPP_STATE_INIT) || (state == HAL_DCMIPP_STATE_READY))
+  {
+    if (((pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL) || \
+         (pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB)) && (Pipe != DCMIPP_PIPE0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Add Data Type Mode for the selected Pipe except Pipe2 */
+    if (Pipe != DCMIPP_PIPE2)
+    {
+      pxfscr_reg |= (uint32_t)(pCSI_PipeConfig->DataTypeMode);
+    }
+
+    if (pCSI_PipeConfig->DataTypeMode != DCMIPP_DTMODE_ALL)
+    {
+      /* Add Data Type IDA for the selected Pipe */
+      pxfscr_reg |= (uint32_t)(pCSI_PipeConfig->DataTypeIDA << DCMIPP_P0FSCR_DTIDA_Pos);
+    }
+
+    if ((pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_DTIDA_OR_DTIDB)
+        || (pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB))
+    {
+      if (Pipe != DCMIPP_PIPE2)
+      {
+        /* Add Data Type IDB for the selected Pipe except Pipe2 */
+        pxfscr_reg |= (uint32_t)(pCSI_PipeConfig->DataTypeIDB << DCMIPP_P0FSCR_DTIDB_Pos);
+      }
+    }
+
+    if (Pipe == DCMIPP_PIPE0)
+    {
+      MODIFY_REG(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_DTMODE | DCMIPP_P0FSCR_DTIDA |
+                 DCMIPP_P0FSCR_DTIDB, pxfscr_reg);
+    }
+    else if (Pipe == DCMIPP_PIPE1)
+    {
+      MODIFY_REG(hdcmipp->Instance->P1FSCR, (DCMIPP_P1FSCR_DTIDA | DCMIPP_P1FSCR_DTIDB |
+                                             DCMIPP_P1FSCR_DTMODE), pxfscr_reg);
+    }
+    else
+    {
+      MODIFY_REG(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_DTIDA, pxfscr_reg);
+    }
+
+    /* Disable Parallel interface */
+    CLEAR_BIT(hdcmipp->Instance->PRCR, DCMIPP_PRCR_ENABLE);
+
+    /* Set CSI Input Selection  */
+    SET_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+  }
+
+  /* Update the DCMIPP state */
+  hdcmipp->State = HAL_DCMIPP_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DCMIPP Virtual Channel according to the user parameters.
+  * @param  hdcmipp            Pointer to DCMIPP handle
+  * @param  VirtualChannel     Specifies the virtual channel, can be a value @ref DCMIPP_Virtual_Channel
+  * @param  pVCFilteringConfig pointer to DCMIPP_CSI_VCFilteringConfTypeDef that contains
+  *                            the Virtual Channel Filtering configuration information.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetVCFilteringConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel,
+                                                      const DCMIPP_CSI_VCFilteringConfTypeDef *pVCFilteringConfig)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+  uint32_t cfgr1 = 0;
+  uint32_t cfgr2 = 0;
+  uint32_t cfgr3 = 0;
+  uint32_t cfgr4 = 0;
+  uint32_t i;
+  struct dt_cfg
+  {
+    uint32_t *reg;
+    uint32_t offset;
+  } DTCFG[MAX_DATATYPE_NB] =
+  {
+    { &cfgr1, 16 }, /* DT0 */
+    { &cfgr2, 0 },  /* DT1 */
+    { &cfgr2, 16 }, /* DT2 */
+    { &cfgr3, 0 },  /* DT3 */
+    { &cfgr3, 16 }, /* DT4 */
+    { &cfgr4, 0 },  /* DT5 */
+    { &cfgr4, 16 }, /* DT6 */
+  };
+
+  /* Check pointer and input values validity */
+  if ((hdcmipp == NULL) || (pVCFilteringConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_CSI_DATA_TYPE_NB(pVCFilteringConfig->DataTypeNB));
+
+  for (i = 0; i < pVCFilteringConfig->DataTypeNB; i++)
+  {
+    assert_param(IS_DCMIPP_CSI_DATA_TYPE_FORMAT(pVCFilteringConfig->DataTypeFormat[i]));
+    assert_param(IS_DCMIPP_CSI_DATA_CLASS(pVCFilteringConfig->DataTypeClass[i]));
+
+    *(DTCFG[i].reg) |= (((pVCFilteringConfig->DataTypeClass[i]) << (DTCFG[i].offset)) | \
+                        (pVCFilteringConfig->DataTypeFormat[i] << (DTCFG[i].offset + 8U)));
+    cfgr1 |= ((uint32_t)1U << (CSI_VC0CFGR1_DT0EN_Pos + i));
+  }
+
+  switch (VirtualChannel)
+  {
+    case DCMIPP_VIRTUAL_CHANNEL0:
+    {
+      WRITE_REG(csi_instance->VC0CFGR1, cfgr1);
+      WRITE_REG(csi_instance->VC0CFGR2, cfgr2);
+      WRITE_REG(csi_instance->VC0CFGR3, cfgr3);
+      WRITE_REG(csi_instance->VC0CFGR4, cfgr4);
+      break;
+    }
+    case DCMIPP_VIRTUAL_CHANNEL1:
+    {
+      WRITE_REG(csi_instance->VC1CFGR1, cfgr1);
+      WRITE_REG(csi_instance->VC1CFGR2, cfgr2);
+      WRITE_REG(csi_instance->VC1CFGR3, cfgr3);
+      WRITE_REG(csi_instance->VC1CFGR4, cfgr4);
+      break;
+    }
+    case DCMIPP_VIRTUAL_CHANNEL2:
+    {
+      WRITE_REG(csi_instance->VC2CFGR1, cfgr1);
+      WRITE_REG(csi_instance->VC2CFGR2, cfgr2);
+      WRITE_REG(csi_instance->VC2CFGR3, cfgr3);
+      WRITE_REG(csi_instance->VC2CFGR4, cfgr4);
+      break;
+    }
+    case DCMIPP_VIRTUAL_CHANNEL3:
+    {
+      WRITE_REG(csi_instance->VC3CFGR1, cfgr1);
+      WRITE_REG(csi_instance->VC3CFGR2, cfgr2);
+      WRITE_REG(csi_instance->VC3CFGR3, cfgr3);
+      WRITE_REG(csi_instance->VC3CFGR4, cfgr4);
+      break;
+    }
+    default:
+      break;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DCMIPP Virtual Channel with the selected Data Type format.
+  * @param  hdcmipp        Pointer to DCMIPP handle
+  * @param  VirtualChannel Specifies the virtual channel, can be a value from @ref DCMIPP_Virtual_Channel
+  * @param  DataTypeFormat Specifies the Data Type Format, can be a value from @ref DCMIPP_CSI_DataTypeFormat.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetVCConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel,
+                                             uint32_t DataTypeFormat)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+  assert_param(IS_DCMIPP_CSI_DATA_TYPE_FORMAT(DataTypeFormat));
+
+  /* Check pointer and input values validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the common format for all data type for the selected virtual channel */
+  switch (VirtualChannel)
+  {
+    case DCMIPP_VIRTUAL_CHANNEL0:
+    {
+      WRITE_REG(csi_instance->VC0CFGR1, (DataTypeFormat << CSI_VC0CFGR1_CDTFT_Pos) | CSI_VC0CFGR1_ALLDT);
+      break;
+    }
+    case DCMIPP_VIRTUAL_CHANNEL1:
+    {
+      WRITE_REG(csi_instance->VC1CFGR1, (DataTypeFormat << CSI_VC1CFGR1_CDTFT_Pos) | CSI_VC1CFGR1_ALLDT);
+      break;
+    }
+    case DCMIPP_VIRTUAL_CHANNEL2:
+    {
+      WRITE_REG(csi_instance->VC2CFGR1, (DataTypeFormat << CSI_VC2CFGR1_CDTFT_Pos) | CSI_VC2CFGR1_ALLDT);
+      break;
+    }
+    case DCMIPP_VIRTUAL_CHANNEL3:
+    {
+      WRITE_REG(csi_instance->VC3CFGR1, (DataTypeFormat << CSI_VC3CFGR1_CDTFT_Pos) | CSI_VC3CFGR1_ALLDT);
+      break;
+    }
+    default:
+      break;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the pipe according to the user parameters.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pPipeConfig pointer to pipe configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                            const DCMIPP_PipeConfTypeDef *pPipeConfig)
+{
+  HAL_DCMIPP_PipeStateTypeDef pipe_state;
+
+  /* Check the DCMIPP peripheral handle parameter and pPipeConfig parameter */
+  if ((hdcmipp == NULL) || (pPipeConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_FRAME_RATE(pPipeConfig->FrameRate));
+  if (Pipe != DCMIPP_PIPE0)
+  {
+    assert_param(IS_DCMIPP_PIXEL_PACKER_FORMAT(pPipeConfig->PixelPackerFormat));
+    assert_param(IS_DCMIPP_PIXEL_PIPE_PITCH(pPipeConfig->PixelPipePitch));
+  }
+
+  if ((Pipe == DCMIPP_PIPE2) && ((pPipeConfig->PixelPackerFormat) > DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1))
+  {
+    return HAL_ERROR;
+  }
+  /* Get Pipe State */
+  pipe_state = hdcmipp->PipeState[Pipe];
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if ((pipe_state == HAL_DCMIPP_PIPE_STATE_RESET) || (pipe_state == HAL_DCMIPP_PIPE_STATE_ERROR))
+    {
+      /* Update the DCMIPP PIPE state */
+      hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+      /* Initialize the DCMIPP Pipe registers */
+      Pipe_Config(hdcmipp, Pipe, pPipeConfig);
+
+      /* Update the DCMIPP pipe state */
+      hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY;
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DCMIPP AXI master memory IP-Plug.
+  * @param  hdcmipp       Pointer to DCMIPP handle
+  * @param  pIPPlugConfig pointer to IPPLUG configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_SetIPPlugConfig(DCMIPP_HandleTypeDef *hdcmipp,
+                                             const DCMIPP_IPPlugConfTypeDef *pIPPlugConfig)
+{
+  uint32_t tickstart;
+
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pIPPlugConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DCMIPP_CLIENT(pIPPlugConfig->Client));
+  assert_param(IS_DCMIPP_DPREG_END(pIPPlugConfig->DPREGEnd));
+  assert_param(IS_DCMIPP_DPREG_START(pIPPlugConfig->DPREGStart));
+  assert_param(IS_DCMIPP_MAX_OUTSTANDING_TRANSACTIONS(pIPPlugConfig->MaxOutstandingTransactions));
+  assert_param(IS_DCMIPP_MEMORY_PAGE_SIZE(pIPPlugConfig->MemoryPageSize));
+  assert_param(IS_DCMIPP_TRAFFIC(pIPPlugConfig->Traffic));
+  assert_param(IS_DCMIPP_WLRU_RATIO(pIPPlugConfig->WLRURatio));
+
+
+  if (hdcmipp->State != HAL_DCMIPP_STATE_RESET)
+  {
+    /* Request to lock the IP-Plug, to allow reconfiguration */
+    SET_BIT(hdcmipp->Instance->IPGR2, DCMIPP_IPGR2_PSTART);
+
+    tickstart = HAL_GetTick();
+    do
+    {
+      if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+    } while ((hdcmipp->Instance->IPGR3 & DCMIPP_IPGR3_IDLE) != DCMIPP_IPGR3_IDLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* IP-Plug is currently locked and can be reconfigured */
+
+  /* Set Memory page size */
+  hdcmipp->Instance->IPGR1 = (pIPPlugConfig->MemoryPageSize);
+
+  /* IP-PLUG Client1 configuration */
+  switch (pIPPlugConfig->Client)
+  {
+    case DCMIPP_CLIENT1:
+    {
+      /* Set Traffic : Burst size and Maximum Outstanding transactions */
+      hdcmipp->Instance->IPC1R1 = (pIPPlugConfig->Traffic |
+                                   (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC1R1_OTR_Pos));
+
+      /* Set Ratio arbitration */
+      hdcmipp->Instance->IPC1R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC1R2_WLRU_Pos);
+
+      /* Set End word and Start Word of the FIFO of the Clientx */
+      hdcmipp->Instance->IPC1R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC1R3_DPREGSTART_Pos) |
+                                   (pIPPlugConfig->DPREGEnd << DCMIPP_IPC1R3_DPREGEND_Pos));
+      break;
+    }
+    case DCMIPP_CLIENT2:
+    {
+      /* Set Traffic : Burst size and Maximum Outstanding transactions */
+      hdcmipp->Instance->IPC2R1 = (pIPPlugConfig->Traffic |
+                                   (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC2R1_OTR_Pos));
+
+      /* Set Ratio arbitration */
+      hdcmipp->Instance->IPC2R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC2R2_WLRU_Pos);
+
+      /* Set End word and Start Word of the FIFO of the Clientx */
+      hdcmipp->Instance->IPC2R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC2R3_DPREGSTART_Pos) |
+                                   (pIPPlugConfig->DPREGEnd << DCMIPP_IPC2R3_DPREGEND_Pos));
+      break;
+    }
+    case DCMIPP_CLIENT3:
+    {
+      /* Set Traffic : Burst size and Maximum Outstanding transactions */
+      hdcmipp->Instance->IPC3R1 = (pIPPlugConfig->Traffic |
+                                   (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC3R1_OTR_Pos));
+
+      /* Set Ratio arbitration */
+      hdcmipp->Instance->IPC3R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC3R2_WLRU_Pos);
+
+      /* Set End word and Start Word of the FIFO of the Clientx */
+      hdcmipp->Instance->IPC3R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC3R3_DPREGSTART_Pos) |
+                                   (pIPPlugConfig->DPREGEnd << DCMIPP_IPC3R3_DPREGEND_Pos));
+      break;
+    }
+    case DCMIPP_CLIENT4:
+    {
+      /* Set Traffic : Burst size and Maximum Outstanding transactions */
+      hdcmipp->Instance->IPC4R1 = (pIPPlugConfig->Traffic |
+                                   (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC4R1_OTR_Pos));
+
+      /* Set Ratio arbitration */
+      hdcmipp->Instance->IPC4R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC4R2_WLRU_Pos);
+
+      /* Set End word and Start Word of the FIFO of the Clientx */
+      hdcmipp->Instance->IPC4R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC4R3_DPREGSTART_Pos) |
+                                   (pIPPlugConfig->DPREGEnd << DCMIPP_IPC4R3_DPREGEND_Pos));
+      break;
+    }
+    case DCMIPP_CLIENT5:
+    {
+      /* Set Traffic : Burst size and Maximum Outstanding transactions */
+      hdcmipp->Instance->IPC5R1 = (pIPPlugConfig->Traffic |
+                                   (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC5R1_OTR_Pos));
+
+      /* Set Ratio arbitration */
+      hdcmipp->Instance->IPC5R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC5R2_WLRU_Pos);
+
+      /* Set End word and Start Word of the FIFO of the Clientx */
+      hdcmipp->Instance->IPC5R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC5R3_DPREGSTART_Pos) |
+                                   (pIPPlugConfig->DPREGEnd << DCMIPP_IPC5R3_DPREGEND_Pos));
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* No lock requested, IP-Plug runs on demand by background HW */
+  CLEAR_BIT(hdcmipp->Instance->IPGR2, DCMIPP_IPGR2_PSTART);
+
+  /* Enable DCMIPP_IT_AXI_TRANSFER_ERR */
+  __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_AXI_TRANSFER_ERROR);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DCMIPP_IO_operation_Functions DCMIPP IO operation Functions
+  *  @brief     IO operation functions
+  * @{
+  */
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DstAddress  the destination address
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress,
+                                        uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((DstAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+  if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Capture Mode and Destination address for the selected pipe */
+  DCMIPP_SetConfig(hdcmipp, Pipe, DstAddress, CaptureMode);
+
+  /* Enable Capture for the selected Pipe */
+  DCMIPP_EnableCapture(hdcmipp, Pipe);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe with double buffering Mode
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DstAddress0 the first destination address
+  * @param  DstAddress1 the second destination address
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
+                                                    uint32_t DstAddress1, uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((DstAddress0 & 0xFU) != 0U) || ((DstAddress1 & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+  if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Capture Mode and Destination addresses for the selected pipe */
+  DCMIPP_SetDBMConfig(hdcmipp, Pipe, DstAddress0, DstAddress1, CaptureMode);
+
+  /* Enable Capture for the selected Pipe */
+  DCMIPP_EnableCapture(hdcmipp, Pipe);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop DCMIPP capture on the specified pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  HAL_DCMIPP_PipeStateTypeDef pipe_state;
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((hdcmipp->Instance->CMCR & DCMIPP_CMCR_INSEL) != DCMIPP_PARALLEL_MODE)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get Pipe State */
+  pipe_state = hdcmipp->PipeState[Pipe];
+
+  /* Check DCMIPP Pipe state */
+  if (pipe_state != HAL_DCMIPP_PIPE_STATE_RESET)
+  {
+    if (DCMIPP_Stop(hdcmipp, Pipe) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe for semi-planar
+  * @param  hdcmipp               Pointer to DCMIPP handle
+  * @param  Pipe                  Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pSemiPlanarDstAddress Pointer to the destination addresses
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows semi-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                  DCMIPP_SemiPlanarDstAddressTypeDef *pSemiPlanarDstAddress,
+                                                  uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress->UVAddress & 0xFU) != 0U) || \
+      ((pSemiPlanarDstAddress->YAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
+    {
+      return HAL_ERROR;
+    }
+    /* Set Capture Mode and Destination address for the selected pipe */
+    DCMIPP_SetConfig(hdcmipp, Pipe, pSemiPlanarDstAddress->YAddress, CaptureMode);
+
+    /* Set Auxiliary Destination addresses */
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress->UVAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe with double buffering Mode
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pSemiPlanarDstAddress0  Pointer to the first destination addresses
+  * @param  pSemiPlanarDstAddress1  Pointer to the second destination addresses
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows semi-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              DCMIPP_SemiPlanarDstAddressTypeDef
+                                                              *pSemiPlanarDstAddress0,
+                                                              DCMIPP_SemiPlanarDstAddressTypeDef
+                                                              *pSemiPlanarDstAddress1,
+                                                              uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress0->YAddress & 0xFU)  != 0U) ||
+      ((pSemiPlanarDstAddress0->UVAddress & 0xFU) != 0U) || ((pSemiPlanarDstAddress1->YAddress & 0xFU)  != 0U) ||
+      ((pSemiPlanarDstAddress1->UVAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Capture Mode and Destination addresses for the selected pipe */
+    DCMIPP_SetDBMConfig(hdcmipp, Pipe, pSemiPlanarDstAddress0->YAddress, pSemiPlanarDstAddress1->YAddress, CaptureMode);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress0->UVAddress);
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pSemiPlanarDstAddress1->UVAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe for semi-planar
+  * @param  hdcmipp               Pointer to DCMIPP handle
+  * @param  Pipe                  Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pFullPlanarDstAddress Pointer to the destination addresses
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows Full-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                  DCMIPP_FullPlanarDstAddressTypeDef *pFullPlanarDstAddress,
+                                                  uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pFullPlanarDstAddress->YAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress->UAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress->VAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Capture Mode and Destination address for the selected pipe */
+    DCMIPP_SetConfig(hdcmipp, Pipe, pFullPlanarDstAddress->YAddress, CaptureMode);
+
+    /* Set Auxiliary Destination addresses */
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress->UAddress);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress->VAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe with double buffering Mode
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pFullPlanarDstAddress0 Pointer to the first destination addresses
+  * @param  pFullPlanarDstAddress1 Pointer to the second destination addresses
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows Full-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              DCMIPP_FullPlanarDstAddressTypeDef
+                                                              *pFullPlanarDstAddress0,
+                                                              DCMIPP_FullPlanarDstAddressTypeDef
+                                                              *pFullPlanarDstAddress1, uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pFullPlanarDstAddress0->YAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress0->UAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress0->VAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress1->YAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress1->UAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress1->VAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Capture Mode and Destination addresses for the selected pipe */
+    DCMIPP_SetDBMConfig(hdcmipp, Pipe, pFullPlanarDstAddress0->YAddress, pFullPlanarDstAddress1->YAddress, CaptureMode);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress0->UAddress);
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pFullPlanarDstAddress1->UAddress);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress0->VAddress);
+    WRITE_REG(hdcmipp->Instance->P1PPM2AR2, pFullPlanarDstAddress1->VAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start DCMIPP capture on the specified pipe and the specified Virtual Channel in Serial Mode
+  * @param  hdcmipp        Pointer to DCMIPP handle
+  * @param  Pipe           Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
+  * @param  DstAddress     the destination address
+  * @param  CaptureMode    DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel,
+                                            uint32_t DstAddress, uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((DstAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+  if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Virtual Channel for the selected Pipe */
+  if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Capture Mode and Destination address for the selected pipe */
+  DCMIPP_SetConfig(hdcmipp, Pipe, DstAddress, CaptureMode);
+
+  /* Enable Capture for the selected Pipe */
+  DCMIPP_EnableCapture(hdcmipp, Pipe);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start DCMIPP capture on the specified pipe and the specified Virtual Channel in Serial Mode
+  *         with double buffering Mode Enabled
+  * @param  hdcmipp        Pointer to DCMIPP handle
+  * @param  Pipe           Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
+  * @param  DstAddress0    1st destination address
+  * @param  DstAddress1    2nd destination address
+  * @param  CaptureMode    DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                        uint32_t VirtualChannel, uint32_t DstAddress0,
+                                                        uint32_t DstAddress1, uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((DstAddress0 & 0xFU) != 0U) || ((DstAddress1 & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+  if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Virtual Channel for the selected Pipe */
+  if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the Address and CaptureMode for the selected Pipe */
+  DCMIPP_SetDBMConfig(hdcmipp, Pipe, DstAddress0, DstAddress1, CaptureMode);
+
+  /* Enable Capture for the selected Pipe */
+  DCMIPP_EnableCapture(hdcmipp, Pipe);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Stop DCMIPP capture on the specified pipe and the specified Virtual Channel
+  * @param  hdcmipp        Pointer to DCMIPP handle
+  * @param  Pipe           Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel Virtual Channel to be stopped can be a value from @ref DCMIPP_Virtual_Channel
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel)
+{
+  HAL_DCMIPP_PipeStateTypeDef pipe_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((hdcmipp->Instance->CMCR & DCMIPP_CMCR_INSEL) != DCMIPP_SERIAL_MODE)
+  {
+    return HAL_ERROR;
+  }
+
+  pipe_state = hdcmipp->PipeState[Pipe];
+
+  /* Check DCMIPP Pipe state */
+  if (pipe_state != HAL_DCMIPP_PIPE_STATE_RESET)
+  {
+    if (DCMIPP_Stop(hdcmipp, Pipe) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    if (DCMIPP_CSI_VCStop(hdcmipp, VirtualChannel) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe for semi-planar in Serial Mode
+  * @param  hdcmipp               Pointer to DCMIPP handle
+  * @param  Pipe                  Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel        Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
+  * @param  pSemiPlanarDstAddress Pointer to the destination addresses
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows semi-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                      uint32_t VirtualChannel,
+                                                      DCMIPP_SemiPlanarDstAddressTypeDef *pSemiPlanarDstAddress,
+                                                      uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress->UVAddress & 0xFU) != 0U) || \
+      ((pSemiPlanarDstAddress->YAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Virtual Channel for the selected Pipe */
+    if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Capture Mode and Destination address for the selected pipe */
+    DCMIPP_SetConfig(hdcmipp, Pipe, pSemiPlanarDstAddress->YAddress, CaptureMode);
+
+    /* Set Auxiliary Destination addresses */
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress->UVAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe with double buffering Mode in Serial Mode
+  * @param  hdcmipp                 Pointer to DCMIPP handle
+  * @param  Pipe                    Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel          Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
+  * @param  pSemiPlanarDstAddress0  Pointer to the first destination addresses
+  * @param  pSemiPlanarDstAddress1  Pointer to the second destination addresses
+  * @param  CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows semi-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                  uint32_t VirtualChannel,
+                                                                  DCMIPP_SemiPlanarDstAddressTypeDef
+                                                                  *pSemiPlanarDstAddress0,
+                                                                  DCMIPP_SemiPlanarDstAddressTypeDef
+                                                                  *pSemiPlanarDstAddress1, uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress0->YAddress & 0xFU)  != 0U) ||
+      ((pSemiPlanarDstAddress0->UVAddress & 0xFU) != 0U) ||
+      ((pSemiPlanarDstAddress1->YAddress & 0xFU)  != 0U) ||
+      ((pSemiPlanarDstAddress1->UVAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Virtual Channel for the selected Pipe */
+    if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Capture Mode and Destination addresses for the selected pipe */
+    DCMIPP_SetDBMConfig(hdcmipp, Pipe, pSemiPlanarDstAddress0->YAddress, pSemiPlanarDstAddress1->YAddress, CaptureMode);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress0->UVAddress);
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pSemiPlanarDstAddress1->UVAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe for semi-planar in Serial Mode
+  * @param  hdcmipp               Pointer to DCMIPP handle
+  * @param  Pipe                  Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel        Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
+  * @param  pFullPlanarDstAddress Pointer to the destination addresses
+  * @param  CaptureMode DCMIPP    capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows Full-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                      uint32_t VirtualChannel,
+                                                      DCMIPP_FullPlanarDstAddressTypeDef *pFullPlanarDstAddress,
+                                                      uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pFullPlanarDstAddress->YAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress->UAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress->VAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Virtual Channel for the selected Pipe */
+    if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Capture Mode and Destination address for the selected pipe */
+    DCMIPP_SetConfig(hdcmipp, Pipe, pFullPlanarDstAddress->YAddress, CaptureMode);
+
+    /* Set Auxiliary Destination addresses */
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress->UAddress);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress->VAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Start the DCMIPP capture on the specified pipe with double buffering Mode in Serial Mode
+  * @param  hdcmipp               Pointer to DCMIPP handle
+  * @param  Pipe                  Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel        Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
+  * @param  pFullPlanarDstAddress0 Pointer to the first destination addresses
+  * @param  pFullPlanarDstAddress1 Pointer to the second destination addresses
+  * @param  CaptureMode           capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
+  * @note   Only DCMIPP_PIPE1 allows Full-planar buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                  uint32_t VirtualChannel,
+                                                                  DCMIPP_FullPlanarDstAddressTypeDef
+                                                                  *pFullPlanarDstAddress0,
+                                                                  DCMIPP_FullPlanarDstAddressTypeDef
+                                                                  *pFullPlanarDstAddress1, uint32_t CaptureMode)
+{
+  uint32_t mode;
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VCID(VirtualChannel));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || ((pFullPlanarDstAddress0->YAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress0->UAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress0->VAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress1->YAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress1->UAddress & 0xFU) != 0U) ||
+      ((pFullPlanarDstAddress1->VAddress & 0xFU) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
+    if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Virtual Channel for the selected Pipe */
+    if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Capture Mode and Destination addresses for the selected pipe */
+    DCMIPP_SetDBMConfig(hdcmipp, Pipe, pFullPlanarDstAddress0->YAddress, pFullPlanarDstAddress1->YAddress, CaptureMode);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress0->UAddress);
+    WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pFullPlanarDstAddress1->UAddress);
+
+    WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress0->VAddress);
+    WRITE_REG(hdcmipp->Instance->P1PPM2AR2, pFullPlanarDstAddress1->VAddress);
+
+    /* Enable Capture for the selected Pipe */
+    DCMIPP_EnableCapture(hdcmipp, Pipe);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Suspend DCMIPP capture on the specified pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Suspend(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  HAL_DCMIPP_PipeStateTypeDef pipe_state;
+  uint32_t tickstart;
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    /* Return Function Status */
+    return HAL_ERROR;
+  }
+
+  pipe_state = hdcmipp->PipeState[Pipe];
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Check Pipe0 State */
+    if (pipe_state == HAL_DCMIPP_PIPE_STATE_BUSY)
+    {
+      /* Disable Capture Request */
+      CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
+
+      /* Change Pipe State */
+      hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_SUSPEND;
+
+      /* Poll CPTACT status till No capture currently active */
+      tickstart = HAL_GetTick();
+      do
+      {
+        if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+        {
+          /* Change Pipe State */
+          hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+      } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P0CPTACT) != 0U);
+    }
+    else
+    {
+      /* Return Function Status */
+      return HAL_ERROR;
+    }
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    if (pipe_state == HAL_DCMIPP_PIPE_STATE_BUSY)
+    {
+      /* Disable Capture Request */
+      CLEAR_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
+      /* Change Pipe State */
+      hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_SUSPEND;
+
+      /* Poll CPTACT status till No capture currently active */
+      tickstart = HAL_GetTick();
+      do
+      {
+        if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+        {
+          /* Change Pipe State */
+          hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+      } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P1CPTACT) != 0U);
+    }
+    else
+    {
+      /* Return Function Status */
+      return HAL_ERROR;
+    }
+
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    if (pipe_state == HAL_DCMIPP_PIPE_STATE_BUSY)
+    {
+      /* Disable Capture Request */
+      CLEAR_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
+      /* Change Pipe State */
+      hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_SUSPEND;
+
+      /* Poll CPTACT status till No capture currently active */
+      tickstart = HAL_GetTick();
+      do
+      {
+        if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+        {
+          /* Change Pipe State */
+          hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+      } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P2CPTACT) != 0U);
+    }
+    else
+    {
+      /* Return Function Status */
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return Function Status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume DCMIPP capture on the specified pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_Resume(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  HAL_DCMIPP_PipeStateTypeDef pipe_state ;
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  pipe_state = hdcmipp->PipeState[Pipe];
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Check Pipe0 State */
+    if (pipe_state == HAL_DCMIPP_PIPE_STATE_SUSPEND)
+    {
+      /* Enable Capture Request */
+      SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
+
+      /* Change Pipe State */
+      hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_BUSY;
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    if (pipe_state == HAL_DCMIPP_PIPE_STATE_SUSPEND)
+    {
+      /* Enable Capture Request */
+      SET_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
+      /* Change Pipe State */
+      hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_BUSY;
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    if (pipe_state == HAL_DCMIPP_PIPE_STATE_SUSPEND)
+    {
+      /* Enable Capture Request */
+      SET_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
+      /* Change Pipe State */
+      hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_BUSY;
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DCMIPP_IRQ_and_Callbacks_Functions DCMIPP IRQ and Callbacks Functions
+  * @brief      IRQ and Callbacks functions
+  * @{
+  */
+
+/** @addtogroup DCMIPP_IRQHandler_Function IRQHandler Function
+  * @{
+  */
+/**
+  * @brief  Handles DCMIPP interrupt request.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval None
+  */
+void HAL_DCMIPP_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  uint32_t cmsr2flags = READ_REG(hdcmipp->Instance->CMSR2);
+  uint32_t cmierflags = READ_REG(hdcmipp->Instance->CMIER);
+
+  /* ========================= PIPE0 INTERRUPTS ==================== */
+  /* Limit error on the PIPE0 ********************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE0_LIMIT) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE0_LIMIT) != 0U)
+    {
+      /* Disable Limit error Interrupt for pipe0 */
+      __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE0_LIMIT;
+
+      /* Clear the Limit error flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_LIMIT);
+
+      /* LIMIT Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_LimitEventCallback(hdcmipp, DCMIPP_PIPE0);
+#else
+      HAL_DCMIPP_PIPE_LimitEventCallback(hdcmipp, DCMIPP_PIPE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* VSYNC interrupt management **********************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE0_VSYNC) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE0_VSYNC) != 0U)
+    {
+      /* Clear the VSYNC flag for pipe0 */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_VSYNC);
+
+      /* VSYNC Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE0);
+#else
+      HAL_DCMIPP_PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* FRAME interrupt management ****************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE0_FRAME) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE0_FRAME) != 0U)
+    {
+      /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR);
+
+        /* Update Pipe State */
+        hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_READY;
+      }
+
+      /* Clear the End of Frame flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_FRAME);
+
+      /* Frame Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE0);
+#else
+      HAL_DCMIPP_PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* LINE interrupt management **********************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE0_LINE) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE0_LINE) != 0U)
+    {
+      /* Clear the LINE flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_LINE);
+
+      /* LINE Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE0);
+#else
+      HAL_DCMIPP_PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Overrun error interrupt for Pipe0 ***************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE0_OVR) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE0_OVR) != 0U)
+    {
+      /* Disable Overrun Error Interrupt for pipe0 */
+      __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_OVR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE0_OVR;
+
+      /* Clear the overrun error flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_OVR);
+
+      /* Change DCMIPP Pipe state */
+      hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE0);
+#else
+      HAL_DCMIPP_PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* ========================= PIPE1 INTERRUPTS ==================== */
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE1_LINE) != 0U)
+  {
+    if ((cmierflags & DCMIPP_FLAG_PIPE1_LINE) != 0U)
+    {
+      /* Clear the End of Frame flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_LINE);
+
+      /* Frame Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE1);
+#else
+      HAL_DCMIPP_PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* VSYNC interrupt management **********************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE1_VSYNC) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE1_VSYNC) != 0U)
+    {
+      /* Clear the VSYNC flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_VSYNC);
+
+      /* VSYNC Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE1);
+#else
+      HAL_DCMIPP_PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE1_FRAME) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE1_FRAME) != 0U)
+    {
+      /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+      if ((hdcmipp->Instance->P1FCTCR & DCMIPP_P1FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME | DCMIPP_IT_PIPE1_VSYNC | DCMIPP_IT_PIPE1_OVR);
+
+        /* Update Pipe State */
+        hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_READY;
+      }
+
+      /* Clear the End of Frame flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_FRAME);
+
+      /* Frame Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE1);
+#else
+      HAL_DCMIPP_PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Overrun error on the PIPE1 **************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE1_OVR) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE1_OVR) != 0U)
+    {
+      /* Disable Overrun Error Interrupt for pipe1 */
+      __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_OVR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE1_OVR;
+
+      /* Clear the overrun error flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_OVR);
+
+      /* Change DCMIPP state */
+      hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE1);
+#else
+      HAL_DCMIPP_PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* ========================= PIPE2 INTERRUPTS ==================== */
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE2_LINE) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE2_LINE) != 0U)
+    {
+      /* Clear the End of Line flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_LINE);
+
+      /* Frame Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE2);
+#else
+      HAL_DCMIPP_PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* VSYNC interrupt management **********************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE2_VSYNC) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE2_VSYNC) != 0U)
+    {
+      /* Clear the VSYNC flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_VSYNC);
+
+      /* VSYNC Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE2);
+#else
+      HAL_DCMIPP_PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE2_FRAME) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE2_FRAME) != 0U)
+    {
+      /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+      if ((hdcmipp->Instance->P2FCTCR & DCMIPP_P2FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_VSYNC | DCMIPP_IT_PIPE2_OVR);
+
+        /* Update Pipe State */
+        hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_READY;
+      }
+
+      /* Clear the End of Frame flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_FRAME);
+
+      /* Frame Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE2);
+#else
+      HAL_DCMIPP_PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+  /* Overrun error on the PIPE2 **************************************/
+  if ((cmsr2flags & DCMIPP_FLAG_PIPE2_OVR) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PIPE2_OVR) != 0U)
+    {
+      /* Disable Overrun Error Interrupt for pipe1 */
+      __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_OVR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE2_OVR;
+
+      /* Clear the overrun error flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_OVR);
+
+      /* Change DCMIPP state */
+      hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE2);
+#else
+      HAL_DCMIPP_PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Synchronization Error Interrupt on the parallel interface  **************/
+  if ((cmsr2flags & DCMIPP_FLAG_PARALLEL_SYNC_ERROR) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_PARALLEL_SYNC_ERROR) != 0U)
+    {
+      /* Disable Synchronization error interrupt on parallel interface */
+      __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PARALLEL_SYNC_ERROR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PARALLEL_SYNC;
+
+      /* Clear the synchronization error flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PARALLEL_SYNC_ERROR);
+
+      /* Change DCMIPP state */
+      hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* IPPLUG AXI transfer Error Interrupt     *********************************/
+  if ((cmsr2flags & DCMIPP_FLAG_AXI_TRANSFER_ERROR) != 0U)
+  {
+    if ((cmierflags & DCMIPP_IT_AXI_TRANSFER_ERROR) != 0U)
+    {
+      /* Disable IPPLUG AXI transfer Error Interrupt */
+      __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_AXI_TRANSFER_ERROR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_AXI_TRANSFER;
+
+      /* Clear the AXI transfer error flag */
+      __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_AXI_TRANSFER_ERROR);
+
+      /* Change DCMIPP state */
+      hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Handles DCMIPP CSI interrupt request.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval None
+  */
+void HAL_DCMIPP_CSI_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  /* Read the SR0 register once */
+  uint32_t sr0flags = READ_REG(csi_instance->SR0);
+  uint32_t sr1flags = READ_REG(csi_instance->SR1);
+
+  uint32_t ier0_flags = READ_REG(csi_instance->IER0);
+  uint32_t ier1_flags = READ_REG(csi_instance->IER1);
+
+  /* Clock changer FIFO full event */
+  if ((sr0flags & DCMIPP_CSI_FLAG_CCFIFO) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_CCFIFO) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_CCFIFO);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_CCFIFO);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ClockChangerFifoFullEventCallback(hdcmipp);
+#else
+      HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /*###############################
+     Byte/Line Counter Interrupt
+  ##############################*/
+  if ((sr0flags & DCMIPP_CSI_FLAG_LB3) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_LB3) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB3);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB3);
+
+      /* LineByte Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER3);
+#else
+      HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER3);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_LB2) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_LB2) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB2);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB2);
+
+      /* LineByte Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER2);
+#else
+      HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_LB1) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_LB1) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB1);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB1);
+
+      /* LineByte Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER1);
+#else
+      HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_LB0) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_LB0) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB0);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB0);
+
+      /* LineByte Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER0);
+#else
+      HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /*###############################
+            End Of Frame
+    ##############################*/
+  if ((sr0flags & DCMIPP_CSI_FLAG_EOF3) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_EOF3) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF3);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF3);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
+#else
+      HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_EOF2) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_EOF2) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF2);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF2);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
+#else
+      HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_EOF1) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_EOF1) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF1);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF1);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
+#else
+      HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_EOF0) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_EOF0) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF0);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF0);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_CSIREGISTER_CALLBACKS == 1)
+      hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
+#else
+      HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /*###############################
+           Start Of Frame
+  ##############################*/
+  if ((sr0flags & DCMIPP_CSI_FLAG_SOF3) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_SOF3) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF3);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF3);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
+#else
+      HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_SOF2) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_SOF2) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF2);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF2);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
+#else
+      HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_SOF1) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_SOF1) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF1);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF1);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
+#else
+      HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_SOF0) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_SOF0) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF0);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF0);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
+#else
+      HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /*###############################
+           Timer Interrupt
+  ##############################*/
+  if ((sr0flags & DCMIPP_CSI_FLAG_TIM3) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_TIM3) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM3);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM3);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER3);
+#else
+      HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER3);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_TIM2) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_TIM2) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM2);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM2);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER2);
+#else
+      HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER2);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_TIM1) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_TIM1) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM1);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM1);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER1);
+#else
+      HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_TIM0) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_TIM0) != 0U)
+    {
+      if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
+      {
+        /* Disable IT */
+        __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM0);
+      }
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM0);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER0);
+#else
+      HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Synchronization error  */
+  if ((sr0flags & DCMIPP_CSI_FLAG_SYNCERR) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_SYNCERR) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SYNCERR);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SYNCERR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SYNC;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_WDERR) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_WDERR) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_WDERR);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_WDERR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_WDG;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_SPKTERR) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_SPKTERR) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SPKTERR);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SPKTERR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SPKT;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_IDERR) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_IDERR) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_IDERR);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_IDERR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DATA_ID;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_CECCERR) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_CECCERR) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_CECCERR);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_CECCERR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_CECC;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_ECCERR) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_ECCERR) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ECCERR);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_ECCERR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_ECC;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_CRCERR) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_CRCERR) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_CRCERR);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_CRCERR);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_CRC;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ErrorCallback(hdcmipp);
+#else
+      HAL_DCMIPP_ErrorCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Lane 0 Errors */
+  /* Start Of Transmission error  */
+  if ((sr1flags & DCMIPP_CSI_FLAG_ESOTDL0) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ESOTDL0) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL0);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTDL0);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT;
+
+      /* Change CSI state */
+      hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Start Of Transmission Synchronisation error   */
+  if ((sr1flags & DCMIPP_CSI_FLAG_ESOTSYNCDL0) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ESOTSYNCDL0) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTSYNCDL0);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTSYNCDL0);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT_SYNC;
+
+      /* Change CSI state */
+      hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Escape entry error   */
+  if ((sr1flags & DCMIPP_CSI_FLAG_EESCDL0) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_EESCDL0) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EESCDL0);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_EESCDL0);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_ESCAPE;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Low power data transmission synchronization error  */
+  if ((sr1flags & DCMIPP_CSI_FLAG_ESYNCESCDL0) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ESYNCESCDL0) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESYNCESCDL0);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESYNCESCDL0);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_LP_SYNC;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Error control on data line */
+  if ((sr1flags & DCMIPP_CSI_FLAG_ECTRLDL0) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ECTRLDL0) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ECTRLDL0);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ECTRLDL0);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_CTRL;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Lane 1 Errors */
+  /* Start Of Transmission error  */
+  if ((sr1flags & DCMIPP_CSI_FLAG_ESOTDL1) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ESOTDL1) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL1);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTDL1);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT;
+
+      /* Change CSI state */
+      hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Start Of Transmission Synchronisation error   */
+  if ((sr1flags & DCMIPP_CSI_FLAG_ESOTSYNCDL1) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ESOTSYNCDL1) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTSYNCDL1);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTSYNCDL1);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT_SYNC;
+
+      /* Change CSI state */
+      hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Escape entry error   */
+  if ((sr1flags & DCMIPP_CSI_FLAG_EESCDL1) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_EESCDL1) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EESCDL1);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_EESCDL1);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_ESCAPE;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Low power data transmission synchronization error  */
+  if ((sr1flags & DCMIPP_CSI_FLAG_ESYNCESCDL1) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ESYNCESCDL1) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESYNCESCDL1);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESYNCESCDL1);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_LP_SYNC;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Error control on data line */
+  if ((sr1flags & DCMIPP_CSI_IT_ECTRLDL1) != 0U)
+  {
+    if ((ier1_flags & DCMIPP_CSI_IT_ECTRLDL1) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ECTRLDL1);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_IT_ECTRLDL1);
+
+      /* Update error code */
+      hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_CTRL;
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#else
+      HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+
+  if ((sr0flags & DCMIPP_CSI_FLAG_SPKT) != 0U)
+  {
+    if ((ier0_flags & DCMIPP_CSI_IT_SPKT) != 0U)
+    {
+      /* Disable IT */
+      __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SPKT);
+
+      /* Clear Flag */
+      __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SPKT);
+
+      /* Error Callback */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+      hdcmipp->ShortPacketDetectionEventCallback(hdcmipp);
+#else
+      HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback(hdcmipp);
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+    }
+  }
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DCMIPP_Callback_Functions Callback Functions
+  * @{
+  */
+/**
+  * @brief  Frame Event callback on the pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval None
+  */
+__weak void HAL_DCMIPP_PIPE_FrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_FrameEventDumpPipeCallback could be implemented in the user file
+   */
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Pipe);
+  UNUSED(hdcmipp);
+}
+
+/**
+  * @brief  Vsync Event callback on pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval None
+  */
+__weak void HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_VsyncEventDumpPipeCallback could be implemented in the user file
+   */
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Pipe);
+  UNUSED(hdcmipp);
+}
+
+
+/**
+  * @brief  Line Event callback on the pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval None
+  */
+__weak void HAL_DCMIPP_PIPE_LineEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_LineEventMainPipeCallback could be implemented in the user file
+   */
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Pipe);
+  UNUSED(hdcmipp);
+}
+
+/**
+  * @brief  Limit callback on the Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval None
+  */
+__weak void HAL_DCMIPP_PIPE_LimitEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_LimitEventDumpPipeCallback could be implemented in the user file
+   */
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Pipe);
+  UNUSED(hdcmipp);
+}
+
+/**
+  * @brief  Error callback on the pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval None
+  */
+__weak void HAL_DCMIPP_PIPE_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_SyncErrorEventCallback could be implemented in the user file
+   */
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Pipe);
+  UNUSED(hdcmipp);
+}
+
+
+/**
+  * @brief  Error callback on DCMIPP
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval None
+  */
+__weak void HAL_DCMIPP_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_ErrorCallback could be implemented in the user file
+   */
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmipp);
+}
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_CSI_Exported_Functions_Group3 Callback functions
+  *  @brief   Callback (event / error) functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Callback functions #####
+ ===============================================================================
+    [..]  This section provides function called upon:
+      (+) events triggered by the CSI
+      (+) errors triggered by the CSI
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Line Error callback on the Data Lane
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  DataLane
+  * @retval None
+  */
+__weak void HAL_DCMIPP_CSI_LineErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t DataLane)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_CSI_LineErrorCallback could be implemented in the user file
+   */
+  UNUSED(DataLane);
+  UNUSED(hdcmipp);
+}
+/**
+  * @brief  Clock Changer Fifo Full Event Callback
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval None
+  */
+__weak void HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback could be implemented in the user file
+   */
+  UNUSED(hdcmipp);
+}
+/**
+  * @brief  Short Packet Detection Event Callback
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval None
+  */
+__weak void HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback(DCMIPP_HandleTypeDef *hdcmipp)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback could be implemented in the user file
+   */
+  UNUSED(hdcmipp);
+}
+/**
+  * @brief  End Of Frame Event Callback
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  VirtualChannel
+  * @retval None
+  */
+__weak void HAL_DCMIPP_CSI_EndOfFrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_CSI_EndOfFrameEventCallback could be implemented in the user file
+   */
+  UNUSED(hdcmipp);
+  UNUSED(VirtualChannel);
+}
+/**
+  * @brief  Start Of Frame Event Callback
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  VirtualChannel
+  * @retval None
+  */
+__weak void HAL_DCMIPP_CSI_StartOfFrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_CSI_StartOfFrameEventCallback could be implemented in the user file
+   */
+  UNUSED(hdcmipp);
+  UNUSED(VirtualChannel);
+}
+/**
+  * @brief  Timer Counter Event Callback
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Timer
+  * @retval None
+  */
+__weak void HAL_DCMIPP_CSI_TimerCounterEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_DCMIPP_CSI_TimerCounterEventCallback could be implemented in the user file
+   */
+  UNUSED(hdcmipp);
+  UNUSED(Timer);
+}
+/**
+  * @brief  Line Byte Event Callback
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Counter
+  * @retval None
+  */
+__weak void HAL_DCMIPP_CSI_LineByteEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+          the HAL_DCMIPP_CSI_LineByteEventCallback could be implemented in the user file
+  */
+  UNUSED(hdcmipp);
+  UNUSED(Counter);
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DCMIPP_RegisterCallback_Functions Register Callback Functions
+  * @{
+  */
+#if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User DCMIPP Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref  HAL_DCMIPP_ERROR_CB_ID DCMIPP Error callback ID
+  *          @arg @ref  HAL_DCMIPP_MSPINIT_CB_ID DCMIPP MspInit callback ID
+  *          @arg @ref  HAL_DCMIPP_MSPDEINIT_CB_ID DCMIPP MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID,
+                                              pDCMIPP_CallbackTypeDef pCallback)
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMIPP_MSPINIT_CB_ID :
+        hdcmipp->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DCMIPP_MSPDEINIT_CB_ID :
+        hdcmipp->MspDeInitCallback = pCallback;
+        break;
+
+      case HAL_DCMIPP_ERROR_CB_ID :
+        hdcmipp->ErrorCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdcmipp->State == HAL_DCMIPP_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMIPP_MSPINIT_CB_ID :
+        hdcmipp->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DCMIPP_MSPDEINIT_CB_ID :
+        hdcmipp->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User DCMIPP Callback
+  *         DCMIPP Callback is redirected to the weak (surcharged) predefined callback
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref  HAL_DCMIPP_ERROR_CB_ID DCMIPP Error callback ID
+  *          @arg @ref  HAL_DCMIPP_MSPINIT_CB_ID DCMIPP MspInit callback ID
+  *          @arg @ref  HAL_DCMIPP_MSPDEINIT_CB_ID DCMIPP MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMIPP_MSPINIT_CB_ID :
+        hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit; /* Legacy weak (surcharged) Msp Init */
+        break;
+
+      case HAL_DCMIPP_MSPDEINIT_CB_ID :
+        hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdcmipp->State == HAL_DCMIPP_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMIPP_MSPINIT_CB_ID :
+        hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit;   /* Legacy weak (surcharged) Msp Init */
+        break;
+
+      case HAL_DCMIPP_MSPDEINIT_CB_ID :
+        hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User DCMIPP Pipe Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref  HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID DCMIPP Pipe Frame event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID DCMIPP Pipe Vsync event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID DCMIPP Pipe Line event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID DCMIPP Pipe Limit event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_ERROR_CB_ID DCMIPP Pipe Error callback ID
+  * @param pCallback pointer to the Pipe Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
+                                                   HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID,
+                                                   pDCMIPP_PIPE_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID :
+        hdcmipp->PIPE_FrameEventCallback = pCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID :
+        hdcmipp->PIPE_VsyncEventCallback = pCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID :
+        hdcmipp->PIPE_LineEventCallback = pCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID :
+        hdcmipp->PIPE_LimitEventCallback = pCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_ERROR_CB_ID :
+        hdcmipp->PIPE_ErrorCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister a User DCMIPP Pipe Callback
+  *         DCMIPP Callback is redirected to the weak (surcharged) predefined callback
+  * @param  hdcmipp   Pointer to DCMIPP handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref  HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID DCMIPP Pipe Frame event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID DCMIPP Pipe Vsync event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID DCMIPP Pipe Line event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID DCMIPP Pipe Limit event callback ID
+  *          @arg @ref  HAL_DCMIPP_PIPE_ERROR_CB_ID DCMIPP Pipe Error callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
+                                                     HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID :
+        hdcmipp->PIPE_FrameEventCallback = HAL_DCMIPP_PIPE_FrameEventCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID :
+        hdcmipp->PIPE_VsyncEventCallback = HAL_DCMIPP_PIPE_VsyncEventCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID :
+        hdcmipp->PIPE_LineEventCallback = HAL_DCMIPP_PIPE_LineEventCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID :
+        hdcmipp->PIPE_LimitEventCallback = HAL_DCMIPP_PIPE_LimitEventCallback;
+        break;
+
+      case HAL_DCMIPP_PIPE_ERROR_CB_ID :
+        hdcmipp->PIPE_ErrorCallback = HAL_DCMIPP_PIPE_ErrorCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/**
+  * The DCMIPP pipe peripheral can be configured using a set of functions that allow
+  *
+  */
+
+/**
+  * Crop Feature : Allows setting and managing the crop coordinates to capture a specific area of the image.
+  *    - HAL_DCMIPP_PIPE_SetCropConfig() : Configure the DCMI crop coordinates.
+  *    - HAL_DCMIPP_PIPE_EnableCrop()    : Enable the cropping feature.
+  *    - HAL_DCMIPP_PIPE_DisableCrop()   : Disable the cropping feature.
+  */
+/** @defgroup DCMIPP_Crop_Functions DCMIPP Crop Functions
+  * @{
+  */
+/**
+  * @brief  Configures cropping for the specified DCMIPP pipe according to the user parameters
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pCropConfig pointer to DCMIPP_CropConfTypeDef structure that contains
+  *                     the configuration information for Crop.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCropConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                const DCMIPP_CropConfTypeDef *pCropConfig)
+{
+  uint32_t tmp;
+
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pCropConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_PIPE_CROP_AREA(pCropConfig->PipeArea));
+  assert_param(IS_DCMIPP_PIPE_CROP_HSTART(pCropConfig->HStart));
+  assert_param(IS_DCMIPP_PIPE_CROP_HSIZE(pCropConfig->HSize));
+  assert_param(IS_DCMIPP_PIPE_CROP_VSIZE(pCropConfig->VSize));
+  assert_param(IS_DCMIPP_PIPE_CROP_VSTART(pCropConfig->VStart));
+
+  /* Check the DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+
+    if (Pipe == DCMIPP_PIPE0)
+    {
+      tmp = READ_REG(hdcmipp->Instance->PRCR);
+
+      /* Verify for parallel mode with jpeg format , no Line Crop enable  */
+      if (((tmp & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE) && ((tmp & DCMIPP_PRCR_FORMAT) == DCMIPP_FORMAT_BYTE))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Set Cropping horizontal and vertical start for Pipe0 */
+        MODIFY_REG(hdcmipp->Instance->P0SCSTR, DCMIPP_P0SCSTR_HSTART | DCMIPP_P0SCSTR_VSTART,
+                   (pCropConfig->HStart << DCMIPP_P0SCSTR_HSTART_Pos) |
+                   (pCropConfig->VStart << DCMIPP_P0SCSTR_VSTART_Pos));
+
+        /* Set Cropping horizontal and vertical width for Pipe0 */
+        /* Set crop Area (Inner or outer) for Pipe0 */
+        MODIFY_REG(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_HSIZE | DCMIPP_P0SCSZR_VSIZE | DCMIPP_P0SCSZR_POSNEG,
+                   (pCropConfig->HSize << DCMIPP_P0SCSZR_HSIZE_Pos) | (pCropConfig->VSize << DCMIPP_P0SCSZR_VSIZE_Pos) |
+                   (pCropConfig->PipeArea));
+      }
+    }
+    else if (Pipe == DCMIPP_PIPE1)
+    {
+      /* Set Cropping horizontal and vertical start for Pipe1 */
+      MODIFY_REG(hdcmipp->Instance->P1CRSTR, DCMIPP_P1CRSTR_HSTART | DCMIPP_P1CRSTR_VSTART,
+                 (pCropConfig->HStart << DCMIPP_P1CRSTR_HSTART_Pos) | \
+                 (pCropConfig->VStart << DCMIPP_P1CRSTR_VSTART_Pos));
+
+      /* Set Cropping horizontal and vertical width for Pipe1 */
+      MODIFY_REG(hdcmipp->Instance->P1CRSZR, DCMIPP_P1CRSZR_HSIZE | DCMIPP_P1CRSZR_VSIZE,
+                 (pCropConfig->HSize << DCMIPP_P1CRSZR_HSIZE_Pos) | (pCropConfig->VSize << DCMIPP_P1CRSZR_VSIZE_Pos));
+    }
+    else if (Pipe == DCMIPP_PIPE2)
+    {
+      /* Set Cropping horizontal and vertical start for Pipe2 */
+      MODIFY_REG(hdcmipp->Instance->P2CRSTR, DCMIPP_P2CRSTR_HSTART | DCMIPP_P2CRSTR_VSTART,
+                 (pCropConfig->HStart << DCMIPP_P2CRSTR_HSTART_Pos) | \
+                 (pCropConfig->VStart << DCMIPP_P2CRSTR_VSTART_Pos));
+
+      /* Set Cropping horizontal and vertical width for Pipe2 */
+      MODIFY_REG(hdcmipp->Instance->P2CRSZR, DCMIPP_P2CRSZR_HSIZE | DCMIPP_P2CRSZR_VSIZE,
+                 (pCropConfig->HSize << DCMIPP_P2CRSZR_HSIZE_Pos) | (pCropConfig->VSize << DCMIPP_P2CRSZR_VSIZE_Pos));
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the cropping for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @note   Cropping cannot be enabled in parallel mode with JPEG Format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  uint32_t tmp;
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if (Pipe == DCMIPP_PIPE0)
+    {
+      /* This bit must be kept cleared if the input format is JPEG */
+      /* Verify for parallel mode with jpeg format , no Line Crop enable  */
+
+      tmp = READ_REG(hdcmipp->Instance->PRCR);
+
+      if (((tmp & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE) && ((tmp & DCMIPP_PRCR_FORMAT) == DCMIPP_FORMAT_BYTE))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        SET_BIT(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_ENABLE);
+      }
+    }
+    else if (Pipe == DCMIPP_PIPE1)
+    {
+      /* Verify Crop line is disabled */
+      if (hdcmipp->Instance->P1SRCR != DCMIPP_P1SRCR_CROPEN)
+      {
+        SET_BIT(hdcmipp->Instance->P1CRSZR, DCMIPP_P1CRSZR_ENABLE);
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+    else if (Pipe == DCMIPP_PIPE2)
+    {
+      SET_BIT(hdcmipp->Instance->P2CRSZR, DCMIPP_P2CRSZR_ENABLE);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the cropping for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1CRSZR, DCMIPP_P1CRSZR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P2CRSZR, DCMIPP_P2CRSZR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Decimation_Functions DCMIPP Decimation Functions
+  * @{
+  */
+/**
+  * Decimation Feature
+  *     - Horizontal resolution :
+  *       - HAL_DCMIPP_PIPE_SetBytesDecimationConfig() : Set the bytes decimation.
+  *     - Vertical resolution :
+  *       - HAL_DCMIPP_PIPE_SetLinesDecimationConfig() : Set the lines decimation.
+  */
+/**
+  * @brief  Configure the Bytes decimation for the selected Pipe.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  SelectStart can a be value from @ref DCMIPP_Byte_Start_Mode
+  * @param  SelectMode  can be a value from @ref DCMIPP_Byte_Select_Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetBytesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           uint32_t SelectStart, uint32_t SelectMode)
+{
+  uint32_t tmp;
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_BYTE_SELECT_START(SelectStart));
+  assert_param(IS_DCMIPP_BYTE_SELECT_MODE(SelectMode));
+
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* OEBS : This bit works in conjunction with BSM field (BSM != 00) */
+    /* Modes 10 and 11 work only with EDM [2:0] = 000 into the DCMIPP_PRCR */
+    tmp = (hdcmipp->Instance->PRCR & DCMIPP_PRCR_EDM);
+
+    if (((SelectStart  == DCMIPP_OEBS_EVEN) && (SelectMode > DCMIPP_BSM_ALL)) || \
+        ((SelectMode > DCMIPP_BSM_DATA_OUT_2) && (tmp != DCMIPP_INTERFACE_8BITS)))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Set Bytes select Start and Bytes select Mode */
+      MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_BSM | DCMIPP_P0PPCR_OEBS, (SelectStart | SelectMode));
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Lines decimation for the selected Pipe.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  SelectStart can a be value from @ref DCMIPP_Line_Start_Mode
+  * @param  SelectMode  can be a value from @ref DCMIPP_Line_Select_Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLinesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           uint32_t SelectStart, uint32_t SelectMode)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_LINE_SELECT_MODE(SelectMode));
+  assert_param(IS_DCMIPP_LINE_SELECT_START(SelectStart));
+
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* This bit works in conjunction with LSM field (LSM = 1) */
+    if ((SelectStart == DCMIPP_OELS_EVEN) && (SelectMode == DCMIPP_LSM_ALTERNATE_2))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Set Lines select Start and Bytes select Mode */
+      MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_LSM | DCMIPP_P0PPCR_OELS, (SelectStart | SelectMode));
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_LimitEvent_Functions DCMIPP Limit Event Functions
+  * @{
+  */
+/**
+  * @brief  Define the Data dump limit for the selected Pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  Limit    Data dump Limit.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Limit)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_DATA_LIMIT(Limit));
+
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Set and enable data limit on Pipe 0 */
+    WRITE_REG(hdcmipp->Instance->P0DCLMTR, (Limit << DCMIPP_P0DCLMTR_LIMIT_Pos) | DCMIPP_P0DCLMTR_ENABLE);
+
+    /* Enable Limit Interrupt for pipe0 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the the Limit interrupt.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Disable data limit on Pipe 0 */
+    CLEAR_BIT(hdcmipp->Instance->P0DCLMTR, DCMIPP_P0DCLMTR_ENABLE);
+
+    /* Disable Limit Interrupt for pipe0 */
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the ISP decimation for the specified pipe according to the used parameters.
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  Pipe       Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pDecConfig pointer to DCMIPP_DecimationConfTypeDef structure that contains the decimation information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         const DCMIPP_DecimationConfTypeDef *pDecConfig)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VRATIO(pDecConfig->VRatio));
+  assert_param(IS_DCMIPP_HRATIO(pDecConfig->HRatio));
+
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pDecConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Decimation Type , Vertical and Horizontal Ratio */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if (Pipe == DCMIPP_PIPE1)
+    {
+      MODIFY_REG(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_VDEC | DCMIPP_P1DECR_HDEC,
+                 (pDecConfig->VRatio | pDecConfig->HRatio));
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the ISP decimation for the specified pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable decimation */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the ISP decimation for the specified pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable decimation */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the decimation for the specified pipe according to the used parameters.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pDecConfig pointer to DCMIPP_DecimationConfTypeDef structure that contains the decimation information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                      const DCMIPP_DecimationConfTypeDef *pDecConfig)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_VRATIO(pDecConfig->VRatio));
+  assert_param(IS_DCMIPP_HRATIO(pDecConfig->HRatio));
+
+  /* Check DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    /* Set Decimation Type , Vertical and Horizontal Ratio */
+    if (Pipe == DCMIPP_PIPE1)
+    {
+      MODIFY_REG(hdcmipp->Instance->P1DCCR, DCMIPP_P1DCCR_VDEC | DCMIPP_P1DCCR_HDEC,
+                 (pDecConfig->VRatio | pDecConfig->HRatio));
+    }
+    else if (Pipe == DCMIPP_PIPE2)
+    {
+      MODIFY_REG(hdcmipp->Instance->P2DCCR, DCMIPP_P2DCCR_VDEC | DCMIPP_P2DCCR_HDEC,
+                 (pDecConfig->VRatio | pDecConfig->HRatio));
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the DCMIPP Decimation for the specified pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Enable decimation */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1DCCR, DCMIPP_P1DCCR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    SET_BIT(hdcmipp->Instance->P2DCCR, DCMIPP_P2DCCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the DCMIPP Decimation for the specified pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Enable decimation */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1DCCR, DCMIPP_P1DCCR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P2DCCR, DCMIPP_P2DCCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * Downsize Feature :
+  *     - HAL_DCMIPP_PIPE_SetDownsizeConfig() : Set the Downsize configuration.
+  *     - HAL_DCMIPP_PIPE_EnableDownsize()    : Enable the Downsize feature.
+  *     - HAL_DCMIPP_PIPE_DisableDownsize()   : Disable the Downsize feature.
+  */
+/**
+  * @brief  Configures Downsize for the specified DCMIPP pipe according to the user parameters
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pDownsizeConfig pointer to the DCMIPP_DownsizeTypeDef structure that contains Downsize information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetDownsizeConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                    const DCMIPP_DownsizeTypeDef *pDownsizeConfig)
+{
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pDownsizeConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_DOWSIZE_DIV_FACTOR(pDownsizeConfig->HDivFactor));
+  assert_param(IS_DCMIPP_DOWSIZE_DIV_FACTOR(pDownsizeConfig->VDivFactor));
+  assert_param(IS_DCMIPP_DOWSIZE_RATIO(pDownsizeConfig->HRatio));
+  assert_param(IS_DCMIPP_DOWSIZE_RATIO(pDownsizeConfig->VRatio));
+  assert_param(IS_DCMIPP_DOWSIZE_SIZE(pDownsizeConfig->HSize));
+  assert_param(IS_DCMIPP_DOWSIZE_SIZE(pDownsizeConfig->VSize));
+
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if (Pipe == DCMIPP_PIPE1)
+    {
+      /* Set Vertical and Horizontal division */
+      MODIFY_REG(hdcmipp->Instance->P1DSCR, (DCMIPP_P1DSCR_HDIV | DCMIPP_P1DSCR_VDIV),
+                 ((pDownsizeConfig->HDivFactor << DCMIPP_P1DSCR_HDIV_Pos) | \
+                  (pDownsizeConfig->VDivFactor << DCMIPP_P1DSCR_VDIV_Pos)));
+
+      /* Set Vertical and Horizontal Ratio */
+      WRITE_REG(hdcmipp->Instance->P1DSRTIOR, (pDownsizeConfig->HRatio << DCMIPP_P1DSRTIOR_HRATIO_Pos) | \
+                (pDownsizeConfig->VRatio << DCMIPP_P1DSRTIOR_VRATIO_Pos));
+
+      /* Set Downsize Destination size */
+      MODIFY_REG(hdcmipp->Instance->P1DSSZR, DCMIPP_P1DSSZR_HSIZE | DCMIPP_P1DSSZR_VSIZE,
+                 (pDownsizeConfig->HSize << DCMIPP_P1DSSZR_HSIZE_Pos) | \
+                 (pDownsizeConfig->VSize << DCMIPP_P1DSSZR_VSIZE_Pos));
+    }
+    else if (Pipe == DCMIPP_PIPE2)
+    {
+      /* Set Vertical and Horizontal division */
+      MODIFY_REG(hdcmipp->Instance->P2DSCR, DCMIPP_P2DSCR_HDIV | DCMIPP_P2DSCR_VDIV,
+                 (pDownsizeConfig->HDivFactor << DCMIPP_P2DSCR_HDIV_Pos) | \
+                 (pDownsizeConfig->VDivFactor << DCMIPP_P2DSCR_VDIV_Pos));
+
+      /* Set Vertical and Horizontal Ratio */
+      WRITE_REG(hdcmipp->Instance->P2DSRTIOR, (pDownsizeConfig->HRatio << DCMIPP_P2DSRTIOR_HRATIO_Pos) | \
+                (pDownsizeConfig->VRatio << DCMIPP_P2DSRTIOR_VRATIO_Pos));
+
+      /* Set Downsize Destination size */
+      MODIFY_REG(hdcmipp->Instance->P2DSSZR, DCMIPP_P2DSSZR_HSIZE | DCMIPP_P2DSSZR_VSIZE,
+                 (pDownsizeConfig->HSize << DCMIPP_P2DSSZR_HSIZE_Pos) | \
+                 (pDownsizeConfig->VSize << DCMIPP_P2DSSZR_VSIZE_Pos));
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the Downsize for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableDownsize(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1DSCR, DCMIPP_P1DSCR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    SET_BIT(hdcmipp->Instance->P2DSCR, DCMIPP_P2DSCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Downsize for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableDownsize(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1DSCR, DCMIPP_P1DSCR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P2DSCR, DCMIPP_P2DSCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the Gamma Conversion for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableGammaConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1GMCR, DCMIPP_P1GMCR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    SET_BIT(hdcmipp->Instance->P2GMCR, DCMIPP_P2GMCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Gamma Conversion for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableGammaConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1GMCR, DCMIPP_P1GMCR_ENABLE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P2GMCR, DCMIPP_P2GMCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if Gamma Conversion is enabled.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledGammaConversion(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1GMCR, DCMIPP_P1GMCR_ENABLE) == DCMIPP_P1GMCR_ENABLE) ? 1U : 0U);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P2GMCR, DCMIPP_P2GMCR_ENABLE) == DCMIPP_P2GMCR_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Configures the ISP Raw Bayer to RGB for the specified DCMIPP pipe according to the user parameters
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pRawBayer2RGBConfig pointer to DCMIPP_RawBayer2RGBConfTypeDef structure that contains the Raw Bayer to RGB
+  *         information.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPRawBayer2RGBConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           const DCMIPP_RawBayer2RGBConfTypeDef *pRawBayer2RGBConfig)
+{
+  uint32_t p1dmcr_reg;
+
+  /* Check handles validity */
+  if ((hdcmipp == NULL) || (pRawBayer2RGBConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_RAWBAYER2RGB_RAW_TYPE(pRawBayer2RGBConfig->RawBayerType));
+  assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->PeakStrength));
+  assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->VLineStrength));
+  assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->HLineStrength));
+  assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->EdgeStrength));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+
+    p1dmcr_reg = ((pRawBayer2RGBConfig->RawBayerType)                               | \
+                  (pRawBayer2RGBConfig->PeakStrength << DCMIPP_P1DMCR_PEAK_Pos)     | \
+                  (pRawBayer2RGBConfig->EdgeStrength << DCMIPP_P1DMCR_EDGE_Pos)     | \
+                  (pRawBayer2RGBConfig->VLineStrength << DCMIPP_P1DMCR_LINEV_Pos)   | \
+                  (pRawBayer2RGBConfig->HLineStrength << DCMIPP_P1DMCR_LINEH_Pos));
+
+
+    MODIFY_REG(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_TYPE | DCMIPP_P1DMCR_PEAK | DCMIPP_P1DMCR_LINEV | \
+               DCMIPP_P1DMCR_LINEH | DCMIPP_P1DMCR_EDGE, p1dmcr_reg);
+
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the ISP Raw Bayer to RGB for the specified DCMIPP pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPRawBayer2RGB(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the ISP Raw Bayer to RGB for the specified DCMIPP pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPRawBayer2RGB(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the ISP Statistic Removal for the specified DCMIPP pipe.
+  * @param  hdcmipp      Pointer to DCMIPP handle
+  * @param  Pipe         Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  NbFirstLines number of lines to skip at the top of the image
+  * @param  NbLastLines  number of valid image line to keep after the skipped first lines
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPRemovalStatisticConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint32_t NbFirstLines, uint32_t NbLastLines)
+{
+  uint32_t p1srcr_reg;
+
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_NB_FIRST_LINES(NbFirstLines));
+  assert_param(IS_DCMIPP_NB_LAST_LINES(NbLastLines));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    p1srcr_reg = ((NbFirstLines << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) | (NbLastLines << DCMIPP_P1SRCR_LASTLINE_Pos));
+
+    MODIFY_REG(hdcmipp->Instance->P1SRCR, (DCMIPP_P1SRCR_FIRSTLINEDEL | DCMIPP_P1SRCR_LASTLINE), p1srcr_reg);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the ISP Statisic Removal for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPRemovalStatistic(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1SRCR, DCMIPP_P1SRCR_CROPEN);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the ISP Statisic Removal for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPRemovalStatistic(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1SRCR, DCMIPP_P1SRCR_CROPEN);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * A set of functions allowing to configure the DCMIPP pipe peripheral for the ISP block:
+  *  - ISP Bad Pixel Removal Feature:
+  *    HAL_DCMIPP_PIPE_SetISPBadPixelRemovalConfig()  : Set the Bad Pixel Removal configuration.
+  *    HAL_DCMIPP_PIPE_EnableISPBadPixelRemoval()     : Enable the Bad Pixel Removal.
+  *    HAL_DCMIPP_PIPE_DisableISPBadPixelRemoval()    : Disable the Bad Pixel Removal.
+  *    HAL_DCMIPP_PIPE_GetISPBadPixelRemovalConfig()  : Get the Bad Pixel Removal configuration.
+  *    HAL_DCMIPP_PIPE_IsEnabledISPBadPixelRemoval()  : Check the status of Bad Pixel Removal.
+  *    HAL_DCMIPP_PIPE_GetISPRemovedBadPixelCounter() : Get the Bad Pixel Removal counter.
+  */
+/**
+  * @brief  Configure the ISP Bad Pixel Removal for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  Strength Specifies the removal strength, can be a value from @ref DCMIPP_Bad_Pixel_Removal_Strength
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPBadPixelRemovalConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              uint32_t Strength)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_BAD_PXL_REMOVAL_STRENGTH(Strength));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_STRENGTH, Strength << DCMIPP_P1BPRCR_STRENGTH_Pos);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the ISP Bad Pixel Removal for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPBadPixelRemoval(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the ISP Bad Pixel Removal for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPBadPixelRemoval(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Retrieve the ISP bad pixel removal strength configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval  The strength of the bad pixel removal process.
+  */
+uint32_t HAL_DCMIPP_PIPE_GetISPBadPixelRemovalConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  return (((READ_REG(hdcmipp->Instance->P1BPRCR)) & DCMIPP_P1BPRCR_STRENGTH) >> DCMIPP_P1BPRCR_STRENGTH_Pos);
+}
+/**
+  * @brief  Check if ISP Bad Pixel Removal is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPBadPixelRemoval(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_ENABLE) == DCMIPP_P1BPRCR_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Get the number of the corrected Bad Pixel in the last frame
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pCounter pointer receiving the number of corrected bad pixels
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetISPRemovedBadPixelCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint32_t *pCounter)
+{
+  /* Check handles validity */
+  if ((hdcmipp == NULL) || (pCounter == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check the DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    *pCounter = READ_REG(hdcmipp->Instance->P1BPRSR & DCMIPP_P1BPRSR_BADCNT);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * Region Of Interest Feature :
+  *     - HAL_DCMIPP_PIPE_SetRegionOfInterestConfig() : Set the Region Of Interest configuration.
+  *     - HAL_DCMIPP_PIPE_EnableRegionOfInterest()    : Enable the Region Of Interest.
+  *     - HAL_DCMIPP_PIPE_DisableRegionOfInterest()   : Disable the Region Of Interest.
+  */
+/**
+  * @brief  Configure the Region Of Interest for the specified DCMIPP pipe according to the user parameters
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  Pipe       Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pROIConfig pointer to a DCMIPP_RegionOfInterestConfTypeDef structure that contains
+  *                    the configuration information for the ROI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetRegionOfInterestConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                            const DCMIPP_RegionOfInterestConfTypeDef *pROIConfig)
+{
+  uint32_t region_index;
+  DCMIPP_Region_TypeDef *region;
+  uint32_t address;
+
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_ROI(pROIConfig->RegionOfInterest));
+  assert_param(IS_DCMIPP_ROI_START(pROIConfig->HStart));
+  assert_param(IS_DCMIPP_ROI_START(pROIConfig->VStart));
+  assert_param(IS_DCMIPP_ROI_SIZE(pROIConfig->HSize));
+  assert_param(IS_DCMIPP_ROI_SIZE(pROIConfig->VSize));
+  assert_param(IS_DCMIPP_ROI_COLOR(pROIConfig->ColorLineBlue));
+  assert_param(IS_DCMIPP_ROI_COLOR(pROIConfig->ColorLineGreen));
+  assert_param(IS_DCMIPP_ROI_COLOR(pROIConfig->ColorLineRed));
+  assert_param(IS_DCMIPP_ROI_LINE_WIDTH(pROIConfig->LineSizeWidth));
+
+  region_index = pROIConfig->RegionOfInterest;
+
+  if ((Pipe == DCMIPP_PIPE1) || (Pipe == DCMIPP_PIPE2))
+  {
+
+    if (Pipe == DCMIPP_PIPE1)
+    {
+      address = (uint32_t) &(hdcmipp->Instance->P1RIxCR1) + (0x8U * (region_index - 1U));
+
+      region = (DCMIPP_Region_TypeDef *)address;
+
+      /* Set Line Width for the selected ROI */
+      MODIFY_REG(hdcmipp->Instance->P1CMRICR, 0x000003U, pROIConfig->LineSizeWidth);
+    }
+    else
+    {
+      address = (uint32_t)&hdcmipp->Instance->P2RIxCR1  + (0x8U * (region_index - 1U));
+
+      region = (DCMIPP_Region_TypeDef *)address;
+
+      /* Set Line Width for the selected ROI */
+      MODIFY_REG(hdcmipp->Instance->P2CMRICR, 0x000003U, pROIConfig->LineSizeWidth);
+    }
+
+    /* Set Offsets Linesize and color */
+    MODIFY_REG(region->PxRIxCR1, 0x3FFFFFFFU, (((uint32_t)pROIConfig->ColorLineBlue << 12U) |
+                                               ((uint32_t)pROIConfig->ColorLineGreen << 14U) |
+                                               ((uint32_t)pROIConfig->ColorLineRed << 28U) | \
+                                               ((uint32_t)pROIConfig->VStart << 16U) | (pROIConfig->HStart)));
+
+    /* Set window size */
+    MODIFY_REG(region->PxRIxCR2, 0xFFF0FFFU, ((uint32_t)pROIConfig->VSize << 16U) | pROIConfig->HSize);
+
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the Region Of Interest for the specified DCMIPP pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  Region   Specifies the region, can be a value from @ref DCMIPP_Region_Of_Interest
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableRegionOfInterest(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Region)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Enable ROI */
+    MODIFY_REG(hdcmipp->Instance->P1CMRICR, 0xFF0001U, ((uint32_t)1U << (16U + (Region - 1U))));
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    /* Enable ROI */
+    MODIFY_REG(hdcmipp->Instance->P2CMRICR, 0xFF0001U, ((uint32_t)1U << (16U + (Region - 1U))));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Region Of Interest for the specified DCMIPP pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  Region   Specifies the region, can be a value from @ref DCMIPP_Region_Of_Interest
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableRegionOfInterest(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                          uint32_t Region)
+{
+  /* Check handles validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Disable ROI */
+    hdcmipp->Instance->P1CMRICR &= ~(1U << (16U + (Region - 1U)));
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    /* Disable ROI */
+    hdcmipp->Instance->P2CMRICR &= ~(1U << (16U + (Region - 1U)));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the ISP Color conversion for the selected DCMIPP Pipe according to the user parameters.
+  * @param  hdcmipp                Pointer to DCMIPP handle
+  * @param  Pipe                   Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pColorConversionConfig pointer to DCMIPP_ColorConversionConfTypeDef structure that contains
+  *                                color conversion information.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPColorConversionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                              const DCMIPP_ColorConversionConfTypeDef
+                                                              *pColorConversionConfig)
+{
+  uint32_t p1cccr_reg;
+  uint16_t tmp1;
+  uint16_t tmp2;
+
+  /* Check handles validity */
+  if ((hdcmipp == NULL) || (pColorConversionConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_FUNCTIONAL_STATE(pColorConversionConfig->ClampOutputSamples));
+  assert_param(IS_DCMIPP_OUTPUT_SAMPLES_TYPES(pColorConversionConfig->OutputSamplesType));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RR));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RG));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RB));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RA));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GR));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GG));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GB));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GA));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BR));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BG));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BB));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BA));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Set Clamp and Type */
+    p1cccr_reg = ((uint32_t)pColorConversionConfig->ClampOutputSamples << DCMIPP_P1CCCR_CLAMP_Pos) | \
+                 ((uint32_t)pColorConversionConfig->OutputSamplesType);
+
+    MODIFY_REG(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_CLAMP | DCMIPP_P1CCCR_TYPE, p1cccr_reg);
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RR);
+    tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RG);
+
+    /* Set Coefficient row 1 columns 1 2 3 and the added column of the matrix */
+    MODIFY_REG(hdcmipp->Instance->P1CCRR1, DCMIPP_P1CCRR1_RR | DCMIPP_P1CCRR1_RG,
+               (((uint32_t)tmp1) << DCMIPP_P1CCRR1_RR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1CCRR1_RG_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RB);
+    tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->RA);
+
+    MODIFY_REG(hdcmipp->Instance->P1CCRR2, DCMIPP_P1CCRR2_RB | DCMIPP_P1CCRR2_RA,
+               ((uint32_t)tmp1 << DCMIPP_P1CCRR2_RB_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCRR2_RA_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GG);
+    tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GR);
+
+
+    /* Set Coefficient row 2 columns 1 2 3 and the added column of the matrix  */
+    MODIFY_REG(hdcmipp->Instance->P1CCGR1, DCMIPP_P1CCGR1_GR | DCMIPP_P1CCGR1_GG,
+               ((uint32_t)tmp1 << DCMIPP_P1CCGR1_GG_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCGR1_GR_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GB);
+    tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->GA);
+
+    MODIFY_REG(hdcmipp->Instance->P1CCGR2, DCMIPP_P1CCGR2_GB | DCMIPP_P1CCGR2_GA,
+               ((uint32_t)tmp1 << DCMIPP_P1CCGR2_GB_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCGR2_GA_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BR);
+    tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BG);
+
+    /* Set Coefficient row 3 columns 1 2 3 and the added column of the matrix  */
+    MODIFY_REG(hdcmipp->Instance->P1CCBR1, DCMIPP_P1CCBR1_BR | DCMIPP_P1CCBR1_BG,
+               ((uint32_t)tmp1 << DCMIPP_P1CCBR1_BR_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCBR1_BG_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BB);
+    tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->BA);
+
+    MODIFY_REG(hdcmipp->Instance->P1CCBR2, DCMIPP_P1CCBR2_BB | DCMIPP_P1CCBR2_BA,
+               (((uint32_t)tmp1) << DCMIPP_P1CCBR2_BB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1CCBR2_BA_Pos));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the ISP Color conversion for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPColorConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the ISP Color conversion for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPColorConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * YUV Conversion Feature :
+  *     - HAL_DCMIPP_PIPE_SetYUVConversionConfig() : Set the YUV conversion configuration.
+  *     - HAL_DCMIPP_PIPE_EnableYUVConversion()    : Enable YUV conversion configuration.
+  *     - HAL_DCMIPP_PIPE_DisableYUVConversion()   : Disable YUV conversion configuration.
+  */
+/**
+  * @brief  Configure the YUV conversion for the selected DCMIPP Pipe according to the user parameters.
+  * @param  hdcmipp                Pointer to DCMIPP handle
+  * @param  Pipe                   Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pColorConversionConfig pointer to DCMIPP_ColorConversionConfTypeDef structure that contains
+  *                                color conversion information.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetYUVConversionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         const DCMIPP_ColorConversionConfTypeDef
+                                                         *pColorConversionConfig)
+{
+  uint32_t p1yuvcr_reg;
+  uint16_t tmp1;
+  uint16_t tmp2;
+
+  /* Check handles validity */
+  if ((hdcmipp == NULL) || (pColorConversionConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_FUNCTIONAL_STATE(pColorConversionConfig->ClampOutputSamples));
+  assert_param(IS_DCMIPP_OUTPUT_SAMPLES_TYPES(pColorConversionConfig->OutputSamplesType));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RR));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RG));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RB));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RA));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GR));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GG));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GB));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GA));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BR));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BG));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BB));
+  assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BA));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Set Clamp and Type */
+    p1yuvcr_reg = ((uint32_t)pColorConversionConfig->OutputSamplesType | \
+                   ((uint32_t)pColorConversionConfig->ClampOutputSamples << DCMIPP_P1YUVCR_CLAMP_Pos));
+
+    MODIFY_REG(hdcmipp->Instance->P1YUVCR, DCMIPP_P1YUVCR_CLAMP | DCMIPP_P1YUVCR_TYPE, p1yuvcr_reg);
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RR);
+    tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RG);
+
+    /* Set Coefficient row 1 columns 1 2 3 and the added column of the matrix */
+    MODIFY_REG(hdcmipp->Instance->P1YUVRR1, DCMIPP_P1YUVRR1_RR | DCMIPP_P1YUVRR1_RG,
+               (((uint32_t)tmp1) << DCMIPP_P1YUVRR1_RR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVRR1_RG_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RB);
+    tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->RA);
+
+    MODIFY_REG(hdcmipp->Instance->P1YUVRR2, DCMIPP_P1YUVRR2_RB | DCMIPP_P1YUVRR2_RA,
+               (((uint32_t)tmp1) << DCMIPP_P1YUVRR2_RB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVRR2_RA_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GR);
+    tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GG);
+
+    /* Set Coefficient row 2 columns 1 2 3 and the added column of the matrix  */
+    MODIFY_REG(hdcmipp->Instance->P1YUVGR1, DCMIPP_P1YUVGR1_GR | DCMIPP_P1YUVGR1_GG,
+               (((uint32_t)tmp1) << DCMIPP_P1YUVGR1_GR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVGR1_GG_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GB);
+    tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->GA);
+
+    MODIFY_REG(hdcmipp->Instance->P1YUVGR2, DCMIPP_P1YUVGR2_GB | DCMIPP_P1YUVGR2_GA,
+               (((uint32_t)tmp1) << DCMIPP_P1YUVGR2_GB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVGR2_GA_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BR);
+    tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BG);
+
+    /* Set Coefficient row 3 columns 1 2 3 and the added column of the matrix  */
+    MODIFY_REG(hdcmipp->Instance->P1YUVBR1, DCMIPP_P1YUVBR1_BR | DCMIPP_P1YUVBR1_BG,
+               (((uint32_t)tmp1) << DCMIPP_P1YUVBR1_BR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVBR1_BG_Pos));
+
+    tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BB);
+    tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->BA);
+
+    MODIFY_REG(hdcmipp->Instance->P1YUVBR2, DCMIPP_P1YUVBR2_BB | DCMIPP_P1YUVBR2_BA,
+               (((uint32_t)tmp1) << DCMIPP_P1YUVBR2_BB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVBR2_BA_Pos));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the YUV conversion for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableYUVConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1YUVCR, DCMIPP_P1YUVCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the YUV conversion for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableYUVConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1YUVCR, DCMIPP_P1YUVCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * A set of functions allowing to configure the DCMIPP pipe peripheral for the ISP block:
+  *  - ISP Black Level Calibration Feature:
+  *    HAL_DCMIPP_PIPE_SetISPBlackLevelCalibrationConfig() : Set the Black Level Calibration configuration.
+  *    HAL_DCMIPP_PIPE_EnableISPBlackLevelCalibration()    : Enable the Black Level Calibration.
+  *    HAL_DCMIPP_PIPE_DisableISPBlackLevelCalibration()   : Disable the Black Level Calibration.
+  *    HAL_DCMIPP_PIPE_GetISPBlackLevelCalibrationConfig() : Get the Black Level Calibration configuration.
+  *    HAL_DCMIPP_PIPE_IsEnabledISPBlackLevelCalibration() : Check the status of Black Level Calibration.
+  */
+/**
+  * @brief  Configure the ISP Black Level Calibration for the selected DCMIPP Pipe according to the user parameters.
+  * @param  hdcmipp           Pointer to DCMIPP handle
+  * @param  Pipe              Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pBlackLevelConfig pointer to DCMIPP_BlackLevelConfTypeDef structure that contains black level
+  *                           calibration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPBlackLevelCalibrationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                    const DCMIPP_BlackLevelConfTypeDef
+                                                                    *pBlackLevelConfig)
+{
+  /* Check handles validity */
+  if ((hdcmipp == NULL) || (pBlackLevelConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_BLCR | DCMIPP_P1BLCCR_BLCG | DCMIPP_P1BLCCR_BLCB,
+               (((uint32_t)pBlackLevelConfig->RedCompBlackLevel << DCMIPP_P1BLCCR_BLCR_Pos) | \
+                ((uint32_t)pBlackLevelConfig->GreenCompBlackLevel << DCMIPP_P1BLCCR_BLCG_Pos) | \
+                ((uint32_t)pBlackLevelConfig->BlueCompBlackLevel << DCMIPP_P1BLCCR_BLCB_Pos)));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the ISP Black Level Calibration for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPBlackLevelCalibration(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the ISP Black Level Calibration for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPBlackLevelCalibration(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Retrieve the ISP black level calibration configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp            Pointer to DCMIPP handle
+  * @param  Pipe               Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pBlackLevelConfig  Pointer to a DCMIPP_BlackLevelConfTypeDef structure that will be
+  *                            filled with the black level calibration configuration of the specified pipe.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPBlackLevelCalibrationConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                       DCMIPP_BlackLevelConfTypeDef *pBlackLevelConfig)
+{
+  uint32_t p1blccr_reg;
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    p1blccr_reg = READ_REG(hdcmipp->Instance->P1BLCCR);
+    pBlackLevelConfig->BlueCompBlackLevel = (uint8_t)((p1blccr_reg & DCMIPP_P1BLCCR_BLCB) >> DCMIPP_P1BLCCR_BLCB_Pos);
+    pBlackLevelConfig->GreenCompBlackLevel = (uint8_t)((p1blccr_reg & DCMIPP_P1BLCCR_BLCG) >> DCMIPP_P1BLCCR_BLCG_Pos);
+    pBlackLevelConfig->RedCompBlackLevel = (uint8_t)((p1blccr_reg & DCMIPP_P1BLCCR_BLCR) >> DCMIPP_P1BLCCR_BLCR_Pos);
+  }
+}
+
+/**
+  * @brief  Check if ISP Black Level Calibration is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPBlackLevelCalibration(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_ENABLE) == DCMIPP_P1BLCCR_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Configure the ISP statistic extraction module for the selected DCMIPP Pipe according to the user parameters.
+  * @param  hdcmipp                           Pointer to DCMIPP handle
+  * @param  Pipe                              Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  ModuleID                          Specifies the Module ID, can be a value from
+  *                                           @ref DCMIPP_Statistics_Extraction_Module_ID.
+  * @param  pStatisticExtractionConfig Pointer to DCMIPP_StatisticExtractionConfTypeDef structure
+                                              that contains statistic extraction information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPStatisticExtractionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                  uint8_t ModuleID, const
+                                                                  DCMIPP_StatisticExtractionConfTypeDef
+                                                                  *pStatisticExtractionConfig)
+{
+  uint32_t p1stxcr_reg;
+
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pStatisticExtractionConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
+  assert_param(IS_DCMIPP_STAT_EXTRACTION_BINS(pStatisticExtractionConfig->Bins));
+  assert_param(IS_DCMIPP_STAT_EXTRACTION_SOURCE(pStatisticExtractionConfig->Source));
+  assert_param(IS_DCMIPP_STAT_EXTRACTION_MODE(pStatisticExtractionConfig->Mode));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    p1stxcr_reg = (pStatisticExtractionConfig->Mode) | (pStatisticExtractionConfig->Source) | \
+                  (pStatisticExtractionConfig->Bins);
+
+    switch (ModuleID)
+    {
+      case DCMIPP_STATEXT_MODULE1:
+        MODIFY_REG(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_BINS | DCMIPP_P1ST1CR_SRC | \
+                   DCMIPP_P1ST1CR_MODE, p1stxcr_reg);
+        break;
+      case DCMIPP_STATEXT_MODULE2:
+        MODIFY_REG(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_BINS | DCMIPP_P1ST2CR_SRC | \
+                   DCMIPP_P1ST2CR_MODE, p1stxcr_reg);
+        break;
+      default:
+        /* DCMIPP_STATEXT_MODULE3 */
+        MODIFY_REG(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_BINS | DCMIPP_P1ST3CR_SRC | \
+                   DCMIPP_P1ST3CR_MODE, p1stxcr_reg);
+        break;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Configures the area for statistics extraction for the selected DCMIPP Pipe according to the user parameters.
+  * @param  hdcmipp                        Pointer to DCMIPP handle
+  * @param  Pipe                           Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pStatisticExtractionAreaConfig Pointer to DCMIPP_StatisticExtractionAreaConfTypeDef structure
+                                           that contains statistic extraction Area information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPAreaStatisticExtractionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                      const DCMIPP_StatisticExtractionAreaConfTypeDef
+                                                                      *pStatisticExtractionAreaConfig)
+{
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pStatisticExtractionAreaConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_START(pStatisticExtractionAreaConfig->HStart));
+  assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_START(pStatisticExtractionAreaConfig->VStart));
+  assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_SIZE(pStatisticExtractionAreaConfig->HSize));
+  assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_SIZE(pStatisticExtractionAreaConfig->VSize));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1STSTR, DCMIPP_P1STSTR_HSTART | DCMIPP_P1STSTR_VSTART,
+               (pStatisticExtractionAreaConfig->HStart << DCMIPP_P1STSTR_HSTART_Pos) | \
+               (pStatisticExtractionAreaConfig->VStart << DCMIPP_P1STSTR_VSTART_Pos));
+
+    MODIFY_REG(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_HSIZE | DCMIPP_P1STSZR_VSIZE,
+               (pStatisticExtractionAreaConfig->HSize << DCMIPP_P1STSZR_HSIZE_Pos) | \
+               (pStatisticExtractionAreaConfig->VSize << DCMIPP_P1STSZR_VSIZE_Pos));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the selected statistic extraction module for the selected DCMIPP Pipe
+  * @param  hdcmipp   Pointer to DCMIPP handle
+  * @param  Pipe      Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  ModuleID  Specifies the Module ID, can be a value from @ref DCMIPP_Statistics_Extraction_Module_ID.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint8_t ModuleID)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    switch (ModuleID)
+    {
+      case DCMIPP_STATEXT_MODULE1:
+        SET_BIT(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_ENABLE);
+        break;
+      case DCMIPP_STATEXT_MODULE2:
+        SET_BIT(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_ENABLE);
+        break;
+      default:
+        /* DCMIPP_STATEXT_MODULE3 */
+        SET_BIT(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_ENABLE);
+        break;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected statistic extraction module for the selected DCMIPP Pipe
+  * @param  hdcmipp   Pointer to DCMIPP handle
+  * @param  Pipe      Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  ModuleID  Specifies the Module ID, can be a value from @ref DCMIPP_Statistics_Extraction_Module_ID.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                uint8_t ModuleID)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    switch (ModuleID)
+    {
+      case DCMIPP_STATEXT_MODULE1:
+        CLEAR_BIT(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_ENABLE);
+        break;
+      case DCMIPP_STATEXT_MODULE2:
+        CLEAR_BIT(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_ENABLE);
+        break;
+      case DCMIPP_STATEXT_MODULE3:
+        CLEAR_BIT(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_ENABLE);
+        break;
+      default:
+        break;
+    }
+
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the ISP statistic extraction for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Crop line enable */
+    SET_BIT(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_CROPEN);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the ISP statistic extraction for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_CROPEN);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Configure the ISP Exposure for the selected DCMIPP Pipe according to the user parameters
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Pipe            Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pExposureConfig pointer to the DCMIPP_ExposureConfTypeDef structure that contains the exposure information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPExposureConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                       const DCMIPP_ExposureConfTypeDef *pExposureConfig)
+{
+
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pExposureConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_EXPOSURE_SHF(pExposureConfig->ShiftRed));
+  assert_param(IS_DCMIPP_EXPOSURE_SHF(pExposureConfig->ShiftGreen));
+  assert_param(IS_DCMIPP_EXPOSURE_SHF(pExposureConfig->ShiftBlue));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_SHFR | DCMIPP_P1EXCR1_MULTR,
+               (((uint32_t)pExposureConfig->ShiftRed << DCMIPP_P1EXCR1_SHFR_Pos) | \
+                ((uint32_t)pExposureConfig->MultiplierRed << DCMIPP_P1EXCR1_MULTR_Pos)));
+
+    WRITE_REG(hdcmipp->Instance->P1EXCR2, (((uint32_t)pExposureConfig->ShiftGreen << DCMIPP_P1EXCR2_SHFG_Pos) | \
+                                           ((uint32_t)pExposureConfig->MultiplierGreen << DCMIPP_P1EXCR2_MULTG_Pos) | \
+                                           ((uint32_t)pExposureConfig->ShiftBlue << DCMIPP_P1EXCR2_SHFB_Pos) | \
+                                           ((uint32_t)pExposureConfig->MultiplierBlue << DCMIPP_P1EXCR2_MULTB_Pos)));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the ISP Exposure for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPExposure(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the ISP Exposure for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPExposure(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Configure the ISP Contrast for the selected DCMIPP Pipe according to the user parameters
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Pipe            Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pContrastConfig pointer to the DCMIPP_ContrastConfTypeDef structure that contains contrast information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPCtrlContrastConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                           const DCMIPP_ContrastConfTypeDef *pContrastConfig)
+{
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pContrastConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_0));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_32));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_64));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_96));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_128));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_160));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_192));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_224));
+  assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_256));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+
+    MODIFY_REG(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_LUM0,
+               (uint32_t)pContrastConfig->LUM_0 << DCMIPP_P1CTCR1_LUM0_Pos);
+
+    WRITE_REG(hdcmipp->Instance->P1CTCR2, (((uint32_t)pContrastConfig->LUM_32 << DCMIPP_P1CTCR2_LUM1_Pos) |
+                                           ((uint32_t)pContrastConfig->LUM_64 << DCMIPP_P1CTCR2_LUM2_Pos) |
+                                           ((uint32_t)pContrastConfig->LUM_96 << DCMIPP_P1CTCR2_LUM3_Pos) |
+                                           ((uint32_t)pContrastConfig->LUM_128 << DCMIPP_P1CTCR2_LUM4_Pos)));
+
+    WRITE_REG(hdcmipp->Instance->P1CTCR3, (((uint32_t)pContrastConfig->LUM_160 << DCMIPP_P1CTCR3_LUM5_Pos) |
+                                           ((uint32_t)pContrastConfig->LUM_192 << DCMIPP_P1CTCR3_LUM6_Pos) |
+                                           ((uint32_t)pContrastConfig->LUM_224 << DCMIPP_P1CTCR3_LUM7_Pos) |
+                                           ((uint32_t)pContrastConfig->LUM_256 << DCMIPP_P1CTCR3_LUM8_Pos)));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the ISP Contrast for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPCtrlContrast(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the ISP Contrast for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPCtrlContrast(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check handle validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_ENABLE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_PeripheralControl_Functions DCMIPP Peripheral Control Functions
+  * @{
+  */
+/**
+  * @brief  Reconfigure the Frame Rate for the selected pipe
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  Pipe       Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  FrameRate  the new Frame Rate, can be a value from @ref DCMIPP_Frame_Rates
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameRate(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t FrameRate)
+{
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_FRAME_RATE(FrameRate));
+
+  /* Set Frame Rate for the Pipe */
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, FrameRate);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_FRATE, FrameRate);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    MODIFY_REG(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_FRATE, FrameRate);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure the Pitch for the selected pipe
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  Pipe       Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  LinePitch  the new Pitch value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetPitch(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t LinePitch)
+{
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_PIXEL_PIPE_PITCH(LinePitch));
+
+  /* Set Pixel Pipe Pitch for the Pipe */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1PPM0PR, DCMIPP_P1PPM0PR_PITCH, LinePitch << DCMIPP_P1PPM0PR_PITCH_Pos);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    MODIFY_REG(hdcmipp->Instance->P2PPM0PR, DCMIPP_P2PPM0PR_PITCH, LinePitch << DCMIPP_P2PPM0PR_PITCH_Pos);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure the PixelPackerFormat for the selected pipe
+  * @param  hdcmipp           Pointer to DCMIPP handle
+  * @param  Pipe              Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  PixelPackerFormat the new Pixel Packer Format value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetPixelPackerFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                       uint32_t PixelPackerFormat)
+{
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_PIXEL_PACKER_FORMAT(PixelPackerFormat));
+
+  /* Set Pixel Pipe Pitch for the Pipe */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Configure the pixel packer */
+    MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_FORMAT, PixelPackerFormat);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_FORMAT, PixelPackerFormat);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure Capture Mode for the selected pipe
+  * @param  hdcmipp      Pointer to DCMIPP handle
+  * @param  Pipe         Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  CaptureMode  the new Capture Mode, can be a value from @ref DCMIPP_Capture_Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCaptureMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t CaptureMode)
+{
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
+
+
+  /* Set Capture Mode */
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTMODE, CaptureMode);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTMODE, CaptureMode);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    MODIFY_REG(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTMODE, CaptureMode);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Re-Enable Capture for the selected pipe
+  * @param  hdcmipp   Pointer to DCMIPP handle
+  * @param  Pipe      Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Request Capture for the chosen Pipe */
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    SET_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure the destination memory address for the selected pipe
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  Pipe       Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  Memory     the destination address to be changed can be value from @ref DCMIPP_Memory.
+  * @param  DstAddress the new destination address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetMemoryAddress(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Memory,
+                                                   uint32_t DstAddress)
+{
+  /* Check Parameters */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_MEMORY_ADDRESS(Memory));
+
+  /* Request Capture for the chosen Pipe */
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    if (Memory == DCMIPP_MEMORY_ADDRESS_0)
+    {
+      /* Set Memory0 destination addresses for pipe0 */
+      WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress);
+    }
+    else
+    {
+      if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM)
+      {
+        /* Set Memory1 destination addresses for pipe0 */
+        WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress);
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    if (Memory == DCMIPP_MEMORY_ADDRESS_0)
+    {
+      /* Set Memory0 destination addresses for pipe1 */
+      WRITE_REG(hdcmipp->Instance->P1PPM0AR1, DstAddress);
+    }
+    else
+    {
+      /* Set Memory1 destination addresses for pipe1 */
+      WRITE_REG(hdcmipp->Instance->P1PPM0AR2, DstAddress);
+    }
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    if (Memory == DCMIPP_MEMORY_ADDRESS_0)
+    {
+      /* Set Memory0 destination addresses for pipe2 */
+      WRITE_REG(hdcmipp->Instance->P2PPM0AR1, DstAddress);
+    }
+    else
+    {
+      /* Set Memory1 destination addresses for pipe2 */
+      WRITE_REG(hdcmipp->Instance->P2PPM0AR2, DstAddress);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+
+}
+/**
+  * @brief  Reconfigure the input pixel format for the selected pipe
+  * @param  hdcmipp           Pointer to DCMIPP handle
+  * @param  Pipe              Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  InputPixelFormat  new pixel format, can be a value from @ref DCMIPP_Format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_PARALLEL_SetInputPixelFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                               uint32_t InputPixelFormat)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_FORMAT(InputPixelFormat));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Set Frame Rate */
+    MODIFY_REG(hdcmipp->Instance->PRCR, DCMIPP_PRCR_FORMAT, InputPixelFormat);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Set embedded synchronization delimiters unmasks.
+  * @param  hdcmipp    Pointer to DCMIPP handle
+  * @param  SyncUnmask Pointer to a DCMIPP_EmbeddedSyncUnmaskTypeDef structure that contains
+  *                    the embedded synchronization delimiters unmasks.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef *hdcmipp,
+                                                    const DCMIPP_EmbeddedSyncUnmaskTypeDef *SyncUnmask)
+{
+  uint32_t presur_reg;
+  uint32_t prcr_reg;
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || (SyncUnmask == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    prcr_reg = hdcmipp->Instance->PRCR;
+    /* Check that parallel and Embedded synchronisation modes are configured */
+    if (((prcr_reg & DCMIPP_PRCR_ESS) == DCMIPP_SYNCHRO_EMBEDDED) && \
+        ((prcr_reg & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE))
+    {
+      /* Configure DCMIPP embedded synchronization unmask register */
+      presur_reg = (((uint32_t)SyncUnmask->FrameStartUnmask << DCMIPP_PRESUR_FSU_Pos) | \
+                    ((uint32_t)SyncUnmask->LineStartUnmask << DCMIPP_PRESUR_LSU_Pos)  | \
+                    ((uint32_t)SyncUnmask->LineEndUnmask << DCMIPP_PRESUR_LEU_Pos)    | \
+                    ((uint32_t)SyncUnmask->FrameEndUnmask << DCMIPP_PRESUR_FEU_Pos));
+
+      WRITE_REG(hdcmipp->Instance->PRESUR, presur_reg);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the swapping of color components for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableComponentsSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((Pipe == DCMIPP_PIPE1) || (Pipe == DCMIPP_PIPE2))
+  {
+    /* Verify DCMIPP State */
+    if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+    {
+      SET_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_SWAPRB);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the swapping of color components for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableComponentsSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((Pipe == DCMIPP_PIPE1) || (Pipe == DCMIPP_PIPE2))
+  {
+    /* Verify DCMIPP State */
+    if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+    {
+      CLEAR_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_SWAPRB);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the swapping of red and blue color components for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableRedBlueSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Verify DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if (Pipe == DCMIPP_PIPE1)
+    {
+      SET_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_SWAPRB);
+    }
+    else if (Pipe == DCMIPP_PIPE2)
+    {
+      SET_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_SWAPRB);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the swapping of red and blue color components for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableRedBlueSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Verify DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if (Pipe == DCMIPP_PIPE1)
+    {
+      CLEAR_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_SWAPRB);
+    }
+    else if (Pipe == DCMIPP_PIPE2)
+    {
+      CLEAR_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_SWAPRB);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the swapping of YUV color components for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableYUVSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Verify DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if (Pipe == DCMIPP_PIPE0)
+    {
+      SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_SWAPYUV);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the swapping of YUV color components for the specified DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableYUVSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Verify DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    if (Pipe == DCMIPP_PIPE0)
+    {
+      CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_SWAPYUV);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Line_Event_Functions DCMIPP Line Event Functions
+  * @{
+  */
+/**
+  * Lines Event Feature:
+  *     - HAL_DCMIPP_PIPE_EnableLineEvent()    : Enable the Line event for the selected Line.
+  *     - HAL_DCMIPP_PIPE_DisableLineEvent()   : Disable the Line event for the selected Line.
+  * Lines Wrapping Feature:
+  *     - HAL_DCMIPP_PIPE_SetLineWrappingConfig(): Configure the Line Mult Address Wrapping.
+  *     - HAL_DCMIPP_PIPE_EnableLineWrapping()   : Enable the Line Mult Address Wrapping.
+  *     - HAL_DCMIPP_PIPE_DisableLineWrapping()  : Disable the Line Mult Address Wrapping.
+  */
+/**
+  * @brief  Configures the position of the line interrupt.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  Line     Line Interrupt Position.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Line)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_PIPE_MULTILINE(Line));
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Set MultiLine configuration */
+    MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_LINEMULT, Line);
+
+    /* Enable Multiline Interrupt */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LINE);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Set MultiLine configuration */
+    MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LINEMULT, Line);
+
+    /* Enable Multiline Interrupt */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_LINE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    /* Set MultiLine configuration */
+    MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LINEMULT, Line);
+
+    /* Enable Multiline Interrupt */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_LINE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the the line event interrupt.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Disable Multiline Interrupt */
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LINE);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_LINE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_LINE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Configure the DCMIPP Line Mult Address Wrapping for the the specified DCMIPP pipe
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  AddressWrap Line Mult Address Wrapping Modulo can be a value from @ref DCMIPP_LineWrapAddress
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLineWrappingConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                        uint32_t AddressWrap)
+{
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_ADDRESS_WRAP(AddressWrap));
+
+  /* Line Wrappping Modulo configuration */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LMAWM, AddressWrap);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LMAWM, AddressWrap);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the DCMIPP Line Mult Address Wrapping for the chosen Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineWrapping(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /*  Line Wrappping Modulo Enable */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    SET_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LMAWE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    SET_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LMAWE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the DCMIPP Line Mult Address Wrapping for the the specified DCMIPP pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineWrapping(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Line Multt Address Wrapping Enable */
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LMAWE);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LMAWE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * A set of functions allowing to configure the DCMIPP CSI pipe peripheral:
+  *     - HAL_DCMIPP_PIPE_CSI_EnableShare()          : Enable sharing the image processing block for PIPE2
+  *     - HAL_DCMIPP_PIPE_CSI_DisableShare()         : Disable sharing the image processing block for PIPE2
+  *     - HAL_DCMIPP_PIPE_CSI_ForceDataTypeFormat()  : Forces a specific data type format
+  *     - HAL_DCMIPP_PIPE_CSI_EnableHeader()         : Enable the header dump for PIPE0
+  *     - HAL_DCMIPP_PIPE_CSI_DisableHeader()        : Disable the header dump for PIPE0
+  */
+/**
+  * @brief  Enable Share between DCMIPP_PIPE1 and DCMIPP_PIPE2
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_EnableShare(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  uint32_t tmp1;
+  uint32_t tmp2;
+
+  if (Pipe == DCMIPP_PIPE2)
+  {
+    /* check that Pipe1 and pipe2 are disabled */
+    tmp1 = hdcmipp->Instance->P2FSCR;
+    tmp2 = hdcmipp->Instance->P1FSCR;
+    if (((tmp1 & DCMIPP_P2FSCR_PIPEN) == DCMIPP_P2FSCR_PIPEN) || ((tmp2 & DCMIPP_P1FSCR_PIPEN) == DCMIPP_P1FSCR_PIPEN))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Pipe2 receives the same data as Pipe1 */
+      CLEAR_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEDIFF);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable Share between DCMIPP_PIPE1 and DCMIPP_PIPE2
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_DisableShare(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  uint32_t tmp1;
+  uint32_t tmp2;
+
+  if (Pipe == DCMIPP_PIPE2)
+  {
+    tmp1 = hdcmipp->Instance->P2FSCR;
+    tmp2 = hdcmipp->Instance->P1FSCR;
+    /* check that Pipe1 and pipe2 are disabled */
+    if (((tmp1 & DCMIPP_P2FSCR_PIPEN) == DCMIPP_P2FSCR_PIPEN) || ((tmp2 & DCMIPP_P1FSCR_PIPEN) == DCMIPP_P1FSCR_PIPEN))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Differentiates Pipe2 from pipe1 */
+      SET_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEDIFF);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Force Data Type Format for the selected Pipe
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Pipe            Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DataTypeFormat  Specifies the Data Type Format, can be a value from @ref DCMIPP_DataType
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_ForceDataTypeFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                          uint32_t DataTypeFormat)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_DATA_TYPE(DataTypeFormat));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Force data type format */
+    MODIFY_REG(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_FDTF,  DataTypeFormat << DCMIPP_P1FSCR_FDTF_Pos);
+
+    /* Force data type format enable */
+    SET_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_FDTFEN);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    /* Check that PIPEDIFF is enabled */
+    if ((hdcmipp->Instance->P2FSCR & DCMIPP_P1FSCR_PIPEDIFF) == DCMIPP_P1FSCR_PIPEDIFF)
+    {
+      /* Force data type format */
+      MODIFY_REG(hdcmipp->Instance->P2FSCR, DCMIPP_P1FSCR_FDTF,  DataTypeFormat << DCMIPP_P1FSCR_FDTF_Pos);
+
+      /* Force data type format enable */
+      SET_BIT(hdcmipp->Instance->P2FSCR, DCMIPP_P1FSCR_FDTFEN);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure the Data Type Mode
+  * @param  hdcmipp       Pointer to DCMIPP handle
+  * @param  Pipe          Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DataTypeMode  Specifies the Data Type Mode, can be a value from @ref DCMIPP_DataTypeMode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_SetDTMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DataTypeMode)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_DATA_TYPE_MODE(DataTypeMode));
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    MODIFY_REG(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_DTMODE,  DataTypeMode << DCMIPP_P0FSCR_DTMODE_Pos);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_DTMODE,  DataTypeMode << DCMIPP_P1FSCR_DTMODE_Pos);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reconfigure the Data Type Selection
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DataTypeID  Specifies the Data Type ID, can be a value from @ref DCMIPP_DataTypeSelection
+  * @param  DataType    Specifies the Data Type Format, can be a value from @ref DCMIPP_DataType
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_SetDTSelection(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DataTypeID,
+                                                     uint32_t DataType)
+{
+  uint32_t pxfscr_dtid_Msk;
+
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_DATA_TYPE(DataType));
+
+  if (DataTypeID == DCMIPP_DTSELECT_IDA)
+  {
+    pxfscr_dtid_Msk = DCMIPP_P0FSCR_DTIDA_Msk;
+  }
+  else /* DATA_TYPE_SELECTION_IDB */
+  {
+    pxfscr_dtid_Msk = DCMIPP_P0FSCR_DTIDB_Pos;
+  }
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    MODIFY_REG(hdcmipp->Instance->P0FSCR, pxfscr_dtid_Msk,  DataType << DataTypeID);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1FSCR, pxfscr_dtid_Msk,  DataType << DataTypeID);
+  }
+  else if (Pipe == DCMIPP_PIPE2)
+  {
+    if (DataTypeID == DCMIPP_DTSELECT_IDA)
+    {
+      MODIFY_REG(hdcmipp->Instance->P2FSCR, pxfscr_dtid_Msk,  DataType << DataTypeID);
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable CSI Header dump for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_EnableHeader(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_HEADEREN);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable CSI Header dump for the selected DCMIPP Pipe
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_DisableHeader(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_HEADEREN);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Frame_Counter_Functions DCMIPP Frame Counter Functions
+  * @{
+  */
+/**
+  * @brief  Associate the frame counter to the selected DCMIPP pipe.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameCounterConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check the DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    /* Configure Pipe Selection for the frame counter */
+    MODIFY_REG(hdcmipp->Instance->CMCR, DCMIPP_CMCR_PSFC, Pipe << DCMIPP_CMCR_PSFC_Pos);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Reset the DCMIPP Pipe frame counter
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_ResetFrameCounter(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check the DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    /* Clear Frame counter */
+    SET_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_CFC);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Read the DCMIPP frame counter
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pCounter pointer to store the value of the frame counter
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_ReadFrameCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                   uint32_t *pCounter)
+{
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || (pCounter == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    /* Read frame counter */
+    *pCounter = READ_REG(hdcmipp->Instance->CMFRCR);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_Data_Counter_Functions DCMIPP Data Counter Functions
+  * @{
+  */
+/**
+  * @brief  Read Number of data dumped during the frame.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pCounter pointer to amount of word transferred
+  * @note   Data Counter is available only on DCMIPP_PIPE0. The counter saturates at 0x3FFFFFF.
+  * @note   Granularity is 32-bit for all the formats except for the
+  *         byte stream formats (e.g. JPEG) having byte granularity
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetDataCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                 uint32_t *pCounter)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || (pCounter == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DCMIPP State */
+  if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
+  {
+    /* Read  Pipe0 dump counter register */
+    *pCounter = READ_REG(hdcmipp->Instance->P0DCCNTR);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Get the Statistic accumulated value for the selected module
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  ModuleID Specifies the Module ID, can be a value from @ref DCMIPP_Statistics_Extraction_Module_ID.
+  * @param  pCounter pointer to receive the accumulated value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetISPAccumulatedStatisticsCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                                     uint8_t ModuleID, uint32_t *pCounter)
+{
+
+  /* Check handle validity */
+  if ((hdcmipp == NULL) || (pCounter == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    switch (ModuleID)
+    {
+      case DCMIPP_STATEXT_MODULE1:
+        *pCounter = (READ_REG(hdcmipp->Instance->P1ST1SR & DCMIPP_P1ST1SR_ACCU));
+        break;
+      case DCMIPP_STATEXT_MODULE2:
+        *pCounter = (READ_REG(hdcmipp->Instance->P1ST2SR & DCMIPP_P1ST2SR_ACCU));
+        break;
+      case DCMIPP_STATEXT_MODULE3:
+        *pCounter = (READ_REG(hdcmipp->Instance->P1ST3SR & DCMIPP_P1ST3SR_ACCU));
+        break;
+      default:
+        break;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Get the current operating mode of the DCMIPP
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval Returns  the current operating mode of the DCMIPP can be a value from @ref DCMIPP_modes.
+  */
+uint32_t HAL_DCMIPP_GetMode(const DCMIPP_HandleTypeDef *hdcmipp)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+
+  /* Read the configured Mode */
+  return READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL) ;
+}
+/**
+  * @brief  Get the destination address of the last captured frame
+  * @param  hdcmipp        Pointer to DCMIPP handle
+  * @param  Pipe           Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  MemoryAddress  Specifies the memory address to be retrieved , can be a value from @ref DCMIPP_Memory
+  * @retval Returns  the last destination address.
+  */
+uint32_t HAL_DCMIPP_PIPE_GetMemoryAddress(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t MemoryAddress)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+  assert_param(IS_DCMIPP_MEMORY_ADDRESS(MemoryAddress));
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+
+  /* Get the memory address status */
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* DCMIPP Pipe0 status Memory0 address */
+    return READ_REG(hdcmipp->Instance->P0STM0AR);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    if (MemoryAddress == DCMIPP_MEMORY_ADDRESS_0)
+    {
+      /* DCMIPP Pipe1 status Memory0 address */
+      return READ_REG(hdcmipp->Instance->P1STM0AR);
+    }
+    else if (MemoryAddress == DCMIPP_MEMORY_ADDRESS_1)
+    {
+      /* DCMIPP Pipe1 status Memory1 address */
+      return READ_REG(hdcmipp->Instance->P1STM1AR);
+    }
+    else /* DCMIPP_MEMORY2_ADDRESS */
+    {
+      return READ_REG(hdcmipp->Instance->P1STM2AR);
+    }
+  }
+  else
+  {
+    /* DCMIPP Pipe2 status Memory0 address */
+    return READ_REG(hdcmipp->Instance->P2STM0AR);
+  }
+}
+/**
+  * @}
+  */
+/** @defgroup DCMIPP_Exported_Functions_Group6 Peripheral get config functions
+  * @{
+  */
+/**
+  * @brief  Retrieve the ISP decimation configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp      Pointer to DCMIPP handle
+  * @param  Pipe         Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pDecConfig   Pointer to a DCMIPP_DecimationConfTypeDef structure that will be
+  *                      filled with the decimation configuration of the specified pipe.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPDecimationConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                            DCMIPP_DecimationConfTypeDef *pDecConfig)
+{
+  uint32_t p1decr;
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    p1decr = READ_REG(hdcmipp->Instance->P1DECR);
+    pDecConfig->HRatio = (p1decr & DCMIPP_P1DECR_HDEC);
+    pDecConfig->VRatio = (p1decr & DCMIPP_P1DECR_VDEC);
+  }
+}
+
+/**
+  * @brief  Retrieve the ISP control statistic extraction configuration for a specified DCMIPP pipe and module.
+  * @param  hdcmipp                             Pointer to DCMIPP handle
+  * @param  Pipe                                Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  ModuleID                            Specifies the Module ID, can be a value from
+  *                                             DCMIPP_Statistics_Extraction_Module_ID.
+  * @param  pStatisticExtractionConfig   Pointer to a DCMIPP_StatisticExtractionConfTypeDef structure
+  *                                             that will be filled with the statistic extraction configuration
+  *                                             of the specified module.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPStatisticExtractionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                     uint8_t ModuleID,
+                                                     DCMIPP_StatisticExtractionConfTypeDef
+                                                     *pStatisticExtractionConfig)
+{
+  uint32_t tmp;
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    switch (ModuleID)
+    {
+      case DCMIPP_STATEXT_MODULE1:
+        tmp = READ_REG(hdcmipp->Instance->P1ST1CR);
+        break;
+      case DCMIPP_STATEXT_MODULE2:
+        tmp = READ_REG(hdcmipp->Instance->P1ST2CR);
+        break;
+      default:
+        /* DCMIPP_STATEXT_MODULE3 */
+        tmp = READ_REG(hdcmipp->Instance->P1ST3CR);
+        break;
+    }
+
+    pStatisticExtractionConfig->Bins   = ((tmp & DCMIPP_P1ST1CR_BINS));
+    pStatisticExtractionConfig->Mode   = ((tmp & DCMIPP_P1ST1CR_MODE));
+    pStatisticExtractionConfig->Source = ((tmp & DCMIPP_P1ST1CR_SRC));
+  }
+}
+/**
+  * @brief  Retrieve the ISP area statistic extraction configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp                          Pointer to DCMIPP handle
+  * @param  Pipe                             Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes.
+  * @param  pStatisticExtractionAreaConfig   Pointer to a DCMIPP_StatisticExtractionAreaConfTypeDef structure
+  *                                          that will be filled with the area statistic extraction configuration
+  *                                          of the specified pipe.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPAreaStatisticExtractionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         DCMIPP_StatisticExtractionAreaConfTypeDef
+                                                         *pStatisticExtractionAreaConfig)
+{
+  uint32_t tmp;
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    tmp = READ_REG(hdcmipp->Instance->P1STSTR);
+    pStatisticExtractionAreaConfig->HStart = ((tmp & DCMIPP_P1STSTR_HSTART) >> DCMIPP_P1STSTR_HSTART_Pos);
+    pStatisticExtractionAreaConfig->VStart = ((tmp & DCMIPP_P1STSTR_VSTART) >> DCMIPP_P1STSTR_VSTART_Pos);
+
+    tmp = READ_REG(hdcmipp->Instance->P1STSZR);
+    pStatisticExtractionAreaConfig->VSize  = ((tmp & DCMIPP_P1STSZR_VSIZE) >> DCMIPP_P1STSZR_VSIZE_Pos);
+    pStatisticExtractionAreaConfig->HSize  = ((tmp & DCMIPP_P1STSZR_HSIZE) >> DCMIPP_P1STSZR_HSIZE_Pos);
+  }
+}
+/**
+  * @brief  Retrieve the ISP control contrast configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp          Pointer to DCMIPP handle
+  * @param  Pipe             Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pContrastConfig  Pointer to a DCMIPP_ContrastConfTypeDef structure that will be
+  *                          filled with the contrast configuration of the specified pipe.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPCtrlContrastConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                              DCMIPP_ContrastConfTypeDef *pContrastConfig)
+{
+  uint32_t tmp;
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    tmp = READ_REG(hdcmipp->Instance->P1CTCR1);
+
+    pContrastConfig->LUM_0    = (uint8_t)((tmp & DCMIPP_P1CTCR1_LUM0) >> DCMIPP_P1CTCR1_LUM0_Pos);
+
+    tmp = READ_REG(hdcmipp->Instance->P1CTCR2);
+    pContrastConfig->LUM_32   = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM1) >> DCMIPP_P1CTCR2_LUM1_Pos);
+    pContrastConfig->LUM_64   = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM2) >> DCMIPP_P1CTCR2_LUM2_Pos);
+    pContrastConfig->LUM_96   = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM3) >> DCMIPP_P1CTCR2_LUM3_Pos);
+    pContrastConfig->LUM_128  = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM4) >> DCMIPP_P1CTCR2_LUM4_Pos);
+
+    tmp = READ_REG(hdcmipp->Instance->P1CTCR3);
+    pContrastConfig->LUM_160  = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM5) >> DCMIPP_P1CTCR3_LUM5_Pos);
+    pContrastConfig->LUM_192  = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM6) >> DCMIPP_P1CTCR3_LUM6_Pos);
+    pContrastConfig->LUM_224  = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM7) >> DCMIPP_P1CTCR3_LUM7_Pos);
+    pContrastConfig->LUM_256  = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM8) >> DCMIPP_P1CTCR3_LUM8_Pos);
+  }
+}
+/**
+  * @brief  Retrieve the ISP exposure configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Pipe            Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pExposureConfig Pointer to a DCMIPP_ExposureConfTypeDef structure that will be
+  *                         filled with the exposure configuration of the specified pipe.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPExposureConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                          DCMIPP_ExposureConfTypeDef *pExposureConfig)
+{
+  uint32_t tmp;
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    tmp = READ_REG(hdcmipp->Instance->P1EXCR2);
+
+    pExposureConfig->MultiplierBlue  = (uint8_t)((tmp & DCMIPP_P1EXCR2_MULTB) >> DCMIPP_P1EXCR2_MULTB_Pos);
+    pExposureConfig->ShiftBlue       = (uint8_t)((tmp & DCMIPP_P1EXCR2_SHFB) >> DCMIPP_P1EXCR2_SHFB_Pos);
+    pExposureConfig->ShiftGreen      = (uint8_t)((tmp & DCMIPP_P1EXCR2_SHFG) >> DCMIPP_P1EXCR2_SHFG_Pos);
+    pExposureConfig->MultiplierGreen = (uint8_t)((tmp & DCMIPP_P1EXCR2_MULTG) >> DCMIPP_P1EXCR2_MULTG_Pos);
+
+    tmp = READ_REG(hdcmipp->Instance->P1EXCR1);
+
+    pExposureConfig->MultiplierRed   = (uint8_t)((tmp & DCMIPP_P1EXCR1_MULTR) >> DCMIPP_P1EXCR1_MULTR_Pos);
+    pExposureConfig->ShiftRed        = (uint8_t)((tmp & DCMIPP_P1EXCR1_SHFR) >> DCMIPP_P1EXCR1_SHFR_Pos);
+  }
+}
+/**
+  * @brief  Retrieve the ISP Raw Bayer to RGB conversion configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp             Pointer to DCMIPP handle
+  * @param  Pipe                Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pRawBayer2RGBConfig Pointer to a DCMIPP_RawBayer2RGBConfTypeDef structure that will be
+  *                             filled with the Raw Bayer to RGB conversion configuration of the specified pipe.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPRawBayer2RGBConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                              DCMIPP_RawBayer2RGBConfTypeDef *pRawBayer2RGBConfig)
+{
+  uint32_t p1dmcr_reg;
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    p1dmcr_reg = READ_REG(hdcmipp->Instance->P1DMCR);
+
+    pRawBayer2RGBConfig->EdgeStrength  = ((p1dmcr_reg & DCMIPP_P1DMCR_EDGE) >> DCMIPP_P1DMCR_EDGE_Pos);
+    pRawBayer2RGBConfig->HLineStrength = ((p1dmcr_reg & DCMIPP_P1DMCR_LINEH) >> DCMIPP_P1DMCR_LINEH_Pos);
+    pRawBayer2RGBConfig->PeakStrength  = ((p1dmcr_reg & DCMIPP_P1DMCR_PEAK) >> DCMIPP_P1DMCR_PEAK_Pos);
+    pRawBayer2RGBConfig->RawBayerType  = (p1dmcr_reg & DCMIPP_P1DMCR_TYPE);
+    pRawBayer2RGBConfig->VLineStrength = ((p1dmcr_reg & DCMIPP_P1DMCR_LINEV) >> DCMIPP_P1DMCR_LINEV_Pos);
+  }
+}
+/**
+  * @brief  Retrieve the ISP color conversion configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp                 Pointer to DCMIPP handle
+  * @param  Pipe                    Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pColorConversionConfig  Pointer to a DCMIPP_ColorConversionConfTypeDef structure that will be
+  *                                 filled with the color conversion configuration of the specified pipe.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPColorConversionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                 DCMIPP_ColorConversionConfTypeDef *pColorConversionConfig)
+{
+  uint16_t tmp;
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    tmp = (uint16_t)READ_REG(hdcmipp->Instance->P1CCCR);
+
+    UNUSED(tmp);
+
+    pColorConversionConfig->ClampOutputSamples = (((tmp & DCMIPP_P1CCCR_CLAMP) >> DCMIPP_P1YUVCR_CLAMP_Pos) != 0U)
+                                                 ? ENABLE : DISABLE;
+    pColorConversionConfig->OutputSamplesType  = (uint8_t)(tmp & DCMIPP_P1CCCR_TYPE);
+
+    /* Get Coefficient row 1 columns 1 2 3 and the added column of the matrix */
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR1, DCMIPP_P1CCRR1_RG) >> DCMIPP_P1CCRR1_RG_Pos);
+    pColorConversionConfig->RG = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR1, DCMIPP_P1CCRR1_RR) >> DCMIPP_P1CCRR1_RR_Pos);
+    pColorConversionConfig->RR = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR2, DCMIPP_P1CCRR2_RA) >> DCMIPP_P1CCRR2_RA_Pos);
+    pColorConversionConfig->RA = (int16_t)GET_MATRIX_VALUE10(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR2, DCMIPP_P1CCRR2_RB) >> DCMIPP_P1CCRR2_RB_Pos);
+    pColorConversionConfig->RB = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    /* Get Coefficient row 2 columns 1 2 3 and the added column of the matrix  */
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR1, DCMIPP_P1CCGR1_GG) >> DCMIPP_P1CCGR1_GG_Pos);
+    pColorConversionConfig->GG = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR1, DCMIPP_P1CCGR1_GR) >> DCMIPP_P1CCGR1_GR_Pos);
+    pColorConversionConfig->GR = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR2, DCMIPP_P1CCGR2_GA) >> DCMIPP_P1CCGR2_GA_Pos);
+    pColorConversionConfig->GA = (int16_t)GET_MATRIX_VALUE10(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR2, DCMIPP_P1CCGR2_GB) >> DCMIPP_P1CCGR2_GB_Pos);
+    pColorConversionConfig->GB = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    /* Get Coefficient row 3 columns 1 2 3 and the added column of the matrix  */
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR2, DCMIPP_P1CCBR2_BA) >> DCMIPP_P1CCBR2_BA_Pos);
+    pColorConversionConfig->BA = (int16_t)GET_MATRIX_VALUE10(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR2, DCMIPP_P1CCBR2_BB) >> DCMIPP_P1CCBR2_BB_Pos);
+    pColorConversionConfig->BB = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR1, DCMIPP_P1CCBR1_BG) >> DCMIPP_P1CCBR1_BG_Pos);
+    pColorConversionConfig->BG = (int16_t)GET_MATRIX_VALUE11(tmp);
+
+    tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR1, DCMIPP_P1CCBR1_BR) >> DCMIPP_P1CCBR1_BR_Pos);
+    pColorConversionConfig->BR = (int16_t)GET_MATRIX_VALUE11(tmp);
+  }
+}
+/**
+  * @brief  Retrieve the ISP Statistic Removal configuration for a specified DCMIPP pipe.
+  * @param  hdcmipp       Pointer to DCMIPP handle
+  * @param  Pipe          Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  NbFirstLines  Pointer to a uint32_t variable that will be filled with the number
+  *                       of first lines to be removed from the statistics computation.
+  * @param  NbLastLines   Pointer to a uint32_t variable that will be filled with the number
+  *                       of last lines to be removed from the statistics computation.
+  * @retval None
+  */
+void HAL_DCMIPP_PIPE_GetISPRemovalStatisticConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                  uint32_t *NbFirstLines, uint32_t *NbLastLines)
+{
+  uint32_t tmp;
+
+  /* Check parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    tmp = READ_REG(hdcmipp->Instance->P1SRCR);
+
+    *NbFirstLines  = ((tmp & DCMIPP_P1SRCR_FIRSTLINEDEL) >> DCMIPP_P1SRCR_FIRSTLINEDEL_Pos);
+
+    *NbLastLines = (tmp & DCMIPP_P1SRCR_LASTLINE);
+  }
+}
+/**
+  * @brief  Check if the ISP Statistic Removal is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPRemovalStatistic(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  return ((READ_BIT(hdcmipp->Instance->P1SRCR, DCMIPP_P1SRCR_CROPEN) == DCMIPP_P1SRCR_CROPEN) ? 1U : 0U);
+}
+/**
+  * @brief  Check if ISP Decimation is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPDecimation(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_ENABLE) == DCMIPP_P1DECR_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Check if ISP Exposure is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPExposure(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_ENABLE) == DCMIPP_P1EXCR1_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Check if ISP RawBayer to RGB is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPRawBayer2RGB(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_ENABLE) == DCMIPP_P1DMCR_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Check if ISP color conversion is enabled
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Pipe to be checked
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPColorConversion(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_ENABLE) == DCMIPP_P1CCCR_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Check if ISP contrast is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPCtrlContrast(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_ENABLE) == DCMIPP_P1CTCR1_ENABLE) ? 1U : 0U);
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Check if ISP Statistic Extraction Module is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  ModuleID                          Specifies the Module ID, can be a value from
+  *                                           @ref DCMIPP_Statistics_Extraction_Module_ID.
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPStatisticExtraction(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
+                                                         uint8_t ModuleID)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    switch (ModuleID)
+    {
+      case DCMIPP_STATEXT_MODULE2:
+        return ((READ_BIT(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_ENABLE) == DCMIPP_P1ST2CR_ENABLE) ? 1U : 0U);
+        break;
+      case DCMIPP_STATEXT_MODULE3:
+        return ((READ_BIT(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_ENABLE) == DCMIPP_P1ST3CR_ENABLE) ? 1U : 0U);
+        break;
+      default:
+        /* DCMIPP_STATEXT_MODULE1 */
+        return ((READ_BIT(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_ENABLE) == DCMIPP_P1ST1CR_ENABLE) ? 1U : 0U);
+        break;
+    }
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * @brief  Check if ISP Area Statistic Extraction is enabled or not
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_DCMIPP_PIPE_IsEnabledISPAreaStatisticExtraction(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check parameters */
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  if (Pipe == DCMIPP_PIPE1)
+  {
+    return ((READ_BIT(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_CROPEN) == DCMIPP_P1STSZR_CROPEN) ? 1UL : 0UL);
+
+  }
+  else
+  {
+    /* State Disabled */
+    return 0;
+  }
+}
+/**
+  * A set of functions allowing to configure the DCMIPP CSI Virtual Channel:
+  *     - HAL_DCMIPP_CSI_SetLineByteCounterConfig() : Set Line/Byte counter configuration per virtual Channel
+  *     - HAL_DCMIPP_CSI_EnableLineByteCounter()    : Enable Line/Byte counter per counter (up to 4)
+  *     - HAL_DCMIPP_CSI_DisableLineByteCounter()   : Disable Line/Byte counter per counter (up to 4)
+  *
+  *     - HAL_DCMIPP_CSI_SetTimerConfig()           : Set timer configuration per virtual Channel
+  *     - HAL_DCMIPP_CSI_EnableTimer()              : Enable timer (up to 4)
+  *     - HAL_DCMIPP_CSI_DisableTimer()             : Disable timer (up to 4)
+  *     - HAL_DCMIPP_CSI_SetWatchdogCounterConfig() : Set Watchdog configuration
+  */
+/**
+  * @brief  Configure the DCMIPP CSI Line/Byte Counter for the selected counter according to the user parameters.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Counter         Specifies the counter, can be a value from @ref DCMIPP_CSI_Counter
+  * @param  pLineByteConfig Pointer to DCMIPP_CSI_LineByteCounterConfTypeDef that contains the Line/Byte Counter
+  *                         configuration information for CSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetLineByteCounterConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter,
+                                                          const DCMIPP_CSI_LineByteCounterConfTypeDef *pLineByteConfig)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+  uint32_t prgitr_lbxvc_msk = (CSI_PRGITR_LB0VC << (Counter * 4U));
+  uint32_t prgitr_lbxvc_pos = CSI_PRGITR_LB0VC_Pos + (Counter * 4U);
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || (pLineByteConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
+  assert_param(IS_DCMIPP_CSI_COUNTER(Counter));
+  assert_param(IS_DCMIPP_CSI_LINE_COUNTER(pLineByteConfig->LineCounter));
+  assert_param(IS_DCMIPP_CSI_BYTE_COUNTER(pLineByteConfig->ByteCounter));
+  assert_param(IS_DCMIPP_VCID(pLineByteConfig->VirtualChannel));
+
+  switch (Counter)
+  {
+    case DCMIPP_CSI_COUNTER0:
+      WRITE_REG(csi_instance->LB0CFGR, (pLineByteConfig->LineCounter << CSI_LB0CFGR_LINECNT_Pos) | \
+                pLineByteConfig->ByteCounter);
+      break;
+    case DCMIPP_CSI_COUNTER1:
+      WRITE_REG(csi_instance->LB1CFGR, (pLineByteConfig->LineCounter << CSI_LB1CFGR_LINECNT_Pos) | \
+                pLineByteConfig->ByteCounter);
+      break;
+    case DCMIPP_CSI_COUNTER2:
+      WRITE_REG(csi_instance->LB2CFGR, (pLineByteConfig->LineCounter << CSI_LB2CFGR_LINECNT_Pos) | \
+                pLineByteConfig->ByteCounter);
+      break;
+    case DCMIPP_CSI_COUNTER3:
+      WRITE_REG(csi_instance->LB3CFGR, (pLineByteConfig->LineCounter << CSI_LB3CFGR_LINECNT_Pos) | \
+                pLineByteConfig->ByteCounter);
+      break;
+    default:
+      break;
+  }
+
+  /* Link the Line/Byte Counter to the selected virtual channel */
+  MODIFY_REG(csi_instance->PRGITR, prgitr_lbxvc_msk, pLineByteConfig->VirtualChannel << prgitr_lbxvc_pos);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Enable the selected DCMIPP CSI Line/Byte Counter.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Counter         Specifies the counter, can be a value from @ref DCMIPP_CSI_Counter
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_EnableLineByteCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  assert_param(IS_DCMIPP_CSI_COUNTER(Counter));
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Line/Byte Counter IT */
+  __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_LB0 << Counter);
+
+  /* Enable the selected counter */
+  SET_BIT(csi_instance->PRGITR, CSI_PRGITR_LB0EN << (Counter * 4U));
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the selected DCMIPP CSI Line/Byte Counter.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Counter         Specifies the counter, can be a value from @ref DCMIPP_CSI_Counter
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_DisableLineByteCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  assert_param(IS_DCMIPP_CSI_COUNTER(Counter));
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the Line/Byte Counter IT */
+  __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB0 << Counter);
+
+  /* Disable the selected counter */
+  CLEAR_BIT(csi_instance->PRGITR, CSI_PRGITR_LB0EN << (Counter * 4U));
+
+  return HAL_OK;
+}
+/**
+  * @brief  Configure the DCMIPP CSI Timer for the selected timer according to the user parameters.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Timer       Specifies the Timer, can be a value from @ref DCMIPP_CSI_Timer
+  * @param  TimerConfig Pointer to DCMIPP_CSI_TimerConfTypeDef that contains the timer
+  *                     configuration information for CSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetTimerConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer,
+                                                const DCMIPP_CSI_TimerConfTypeDef *TimerConfig)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  uint32_t prgitr_lbx_index = CSI_PRGITR_TIM0VC_Pos + (Timer * 4U);
+  uint32_t prgitr_lbxvc_msk = (CSI_PRGITR_TIM0VC << (Timer * 4U));
+  uint32_t startpoint_pos = CSI_PRGITR_TIM0EOF_Pos + (Timer * 4U);
+
+  /* Check pointer validity */
+  if ((hdcmipp == NULL) || (TimerConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  assert_param(IS_DCMIPP_VCID(TimerConfig->VirtualChannel));
+  assert_param(IS_DCMIPP_CSI_TIMER(Timer));
+  assert_param(IS_DCMIPP_CSI_TIMER_START(TimerConfig->StartPoint));
+
+  /* Set counter value and the start point for the selected timer */
+  switch (Timer)
+  {
+    case DCMIPP_CSI_TIMER0:
+      WRITE_REG(csi_instance->TIM0CFGR, TimerConfig->Count);
+      break;
+    case DCMIPP_CSI_TIMER1:
+      WRITE_REG(csi_instance->TIM1CFGR, TimerConfig->Count);
+      break;
+    case DCMIPP_CSI_TIMER2:
+      WRITE_REG(csi_instance->TIM2CFGR, TimerConfig->Count);
+      break;
+    case DCMIPP_CSI_TIMER3:
+      WRITE_REG(csi_instance->TIM3CFGR, TimerConfig->Count);
+      break;
+    default:
+      break;
+  }
+
+  SET_BIT(csi_instance->PRGITR, TimerConfig->StartPoint << startpoint_pos);
+
+  /* Link the timer to the selected virtual channel */
+  MODIFY_REG(csi_instance->PRGITR, prgitr_lbxvc_msk, (TimerConfig->VirtualChannel) << prgitr_lbx_index);
+
+  return HAL_OK;
+
+}
+/**
+  * @brief  Enable the selected DCMIPP CSI Timer.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Timer       Specifies the Timer, can be a value from @ref DCMIPP_CSI_Timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_EnableTimer(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  assert_param(IS_DCMIPP_CSI_TIMER(Timer));
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Timer x IT */
+  __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM0 << Timer);
+
+  /* Enable the selected timer */
+  SET_BIT(csi_instance->PRGITR, CSI_PRGITR_TIM0EN << (Timer * 4U));
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the selected DCMIPP CSI Timer.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Timer       Specifies the Timer, can be a value from @ref DCMIPP_CSI_Timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_DisableTimer(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  assert_param(IS_DCMIPP_CSI_TIMER(Timer));
+
+  /* Check pointer validity */
+  if (hdcmipp == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the Line/Byte Counter IT */
+  __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM0 << Timer);
+
+  /* Disable the selected counter */
+  CLEAR_BIT(csi_instance->PRGITR, CSI_PRGITR_TIM0EN << (Timer * 4U));
+
+  return HAL_OK;
+}
+/**
+  * @brief  Configure the DCMIPP CSI Watchdog counter.
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Counter  Specifies the watchdog counter value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMIPP_CSI_SetWatchdogCounterConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+
+  UNUSED(hdcmipp);
+
+  /* Configure the watchdog counter */
+  WRITE_REG(csi_instance->WDR, Counter);
+
+  /* Enable the watchdog IT */
+  __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_WDERR);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DCMIPP_State_and_Error_Functions DCMIPP State and Error Functions
+  * @{
+  */
+
+/**
+  * @brief  Return the DCMIPP state
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval HAL state
+  */
+HAL_DCMIPP_StateTypeDef HAL_DCMIPP_GetState(const DCMIPP_HandleTypeDef *hdcmipp)
+{
+  return hdcmipp->State;
+}
+/**
+  * @brief  Return the DCMIPP error code
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @retval DCMIPP Error Code
+  */
+uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp)
+{
+  return hdcmipp->ErrorCode;
+}
+/**
+  * @brief  Return the DCMIPP state
+  * @param  hdcmipp  Pointer to DCMIPP handle
+  * @param  Pipe     Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL state
+  */
+HAL_DCMIPP_PipeStateTypeDef HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  /* Check Parameters */
+  assert_param(IS_DCMIPP_PIPE(Pipe));
+
+  return hdcmipp->PipeState[Pipe];
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions
+  * @{
+  */
+/**
+  * @brief  Configure the selected Pipe
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  pPipeConfig pointer to the DCMIPP_PipeConfTypeDef structure that contains
+  *                     the configuration information for the pipe.
+  * @retval None
+  */
+static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Configure Pipe0 */
+    /* Configure Frame Rate */
+    MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, pPipeConfig->FrameRate);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Configure Pipe1 */
+    /* Configure Frame Rate */
+    MODIFY_REG(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_FRATE, pPipeConfig->FrameRate);
+
+    /* Configure the pixel packer */
+    MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_FORMAT, pPipeConfig->PixelPackerFormat);
+
+    /* Configure Pixel Pipe Pitch */
+    MODIFY_REG(hdcmipp->Instance->P1PPM0PR, DCMIPP_P1PPM0PR_PITCH,
+               pPipeConfig->PixelPipePitch << DCMIPP_P1PPM0PR_PITCH_Pos);
+
+    if ((pPipeConfig->PixelPackerFormat == DCMIPP_PIXEL_PACKER_FORMAT_YUV422_2) ||
+        (pPipeConfig->PixelPackerFormat == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_2))
+    {
+      MODIFY_REG(hdcmipp->Instance->P1PPM1PR, DCMIPP_P1PPM1PR_PITCH,
+                 pPipeConfig->PixelPipePitch << DCMIPP_P1PPM1PR_PITCH_Pos);
+    }
+    else if (pPipeConfig->PixelPackerFormat == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_3)
+    {
+      MODIFY_REG(hdcmipp->Instance->P1PPM1PR, DCMIPP_P1PPM1PR_PITCH,
+                 ((pPipeConfig->PixelPipePitch) / 2U) << DCMIPP_P1PPM1PR_PITCH_Pos);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else
+  {
+    /* Configure Pipe2 */
+    /* Configure Frame Rate */
+    MODIFY_REG(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_FRATE, pPipeConfig->FrameRate);
+
+    /* Configure the pixel packer */
+    MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_FORMAT, pPipeConfig->PixelPackerFormat);
+
+    /* Configure Pixel Pipe Pitch */
+    MODIFY_REG(hdcmipp->Instance->P2PPM0PR, DCMIPP_P2PPM0PR_PITCH,
+               pPipeConfig->PixelPipePitch << DCMIPP_P2PPM0PR_PITCH_Pos);
+  }
+}
+/**
+  * @brief  Write   register into the D-PHY via the Test registers
+  * @param  hcsi    Pointer to CSI_TypeDef instance registers structure
+  * @param  reg_msb specifies the test code MSB in testdin (PHY Control Interface)
+  * @param  reg_lsb specifies the testcode LSB in testdin
+  * @param  val     specifies the page offset in testdin
+  * @retval None
+  */
+static void DCMIPP_CSI_WritePHYReg(CSI_TypeDef *hcsi, uint32_t reg_msb, uint32_t reg_lsb, uint32_t val)
+{
+  /* Based on sequence described at section 5.2.3.2 of DesignWave document */
+  /* For writing the 4-bit testcode MSBs */
+  /* Set testen to high */
+  SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM);
+
+  /* Set testclk to high */
+  SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
+
+  /* Place 0x00 in testdin */
+  SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM);
+
+  /* Set testclk to low (with the falling edge on testclk, the testdin signal content is latched internally) */
+  CLEAR_REG(hcsi->PTCR0);
+
+  /* Set testen to low */
+  CLEAR_REG(hcsi->PTCR1);
+
+  /* Place the 8-bit word corresponding to the testcode MSBs in testdin */
+  SET_BIT(hcsi->PTCR1, reg_msb & 0xFFU);
+
+  /* Set testclk to high */
+  SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
+
+  /* For writing the 8-bit testcode LSBs */
+  /* Set testclk to low */
+  CLEAR_REG(hcsi->PTCR0);
+
+  /* Set testen to high */
+  SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM);
+
+  /* Set testclk to high */
+  SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
+
+  /* Place the 8-bit word test data in testdin */
+  SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM | (reg_lsb & 0xFFU));
+
+  /* Set testclk to low (with the falling edge on testclk, the testdin signal content is latched internally) */
+  CLEAR_REG(hcsi->PTCR0);
+
+  /* Set testen to low */
+  CLEAR_REG(hcsi->PTCR1);
+
+  /* For writing the data */
+  /* Place the 8-bit word corresponding to the page offset in testdin */
+  SET_BIT(hcsi->PTCR1, val & 0xFFU);
+
+  /* Set testclk to high (test data is programmed internally */
+  SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
+
+  /* Finish by setting testclk to low */
+  CLEAR_REG(hcsi->PTCR0);
+}
+/**
+  * @brief  Configure the destination address and capture mode for the selected pipe
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DstAddress  Specifies the destination memory address for the captured data.
+  * @param  CaptureMode Specifies the capture mode to be set for the pipe.
+  * @retval None
+  */
+static void DCMIPP_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, uint32_t CaptureMode)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P0FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress);
+
+    /* Enable all required interrupts lines for the PIPE0 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR |
+                           DCMIPP_IT_AXI_TRANSFER_ERROR);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P1FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P1PPM0AR1, DstAddress);
+
+    /* Enable all required interrupts lines for the PIPE1 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME  | DCMIPP_IT_PIPE1_OVR | DCMIPP_IT_PIPE1_VSYNC |
+                           DCMIPP_IT_AXI_TRANSFER_ERROR);
+  }
+  else
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P2FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P2PPM0AR1, DstAddress);
+
+    /* Enable all required interrupts lines for the PIPE2 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_OVR | DCMIPP_IT_PIPE2_VSYNC |
+                           DCMIPP_IT_AXI_TRANSFER_ERROR);
+  }
+}
+/**
+  * @brief  Configure the destination addresses and capture mode for the selected pipe for Double Buffering Mode
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  DstAddress0 Specifies the first destination memory address for the captured data.
+  * @param  DstAddress1 Specifies the second destination memory address for the captured data.
+  * @param  CaptureMode Specifies the capture mode to be set for the pipe.
+  * @retval None
+  */
+static void DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
+                                uint32_t DstAddress1, uint32_t CaptureMode)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P0FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress0);
+
+    /* Set the second destination address */
+    WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress1);
+
+    /* Enable Double buffering Mode */
+    SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
+
+    /* Enable all required interrupts lines for the Pipe0 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P1FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P1PPM0AR1, DstAddress0);
+
+    /* Set the second destination address */
+    WRITE_REG(hdcmipp->Instance->P1PPM0AR2, DstAddress1);
+
+    /* Enable Double buffering Mode */
+    SET_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_DBM);
+
+    /* Enable all required interrupts lines for the Pipe1 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME | DCMIPP_IT_PIPE1_VSYNC | DCMIPP_IT_PIPE1_OVR);
+  }
+  else
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Set the capture mode */
+    hdcmipp->Instance->P2FCTCR |= CaptureMode;
+
+    /* Set the destination address */
+    WRITE_REG(hdcmipp->Instance->P2PPM0AR1, DstAddress0);
+
+    /* Set the second destination address */
+    WRITE_REG(hdcmipp->Instance->P2PPM0AR2, DstAddress1);
+
+    /* Enable Double buffering Mode */
+    SET_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_DBM);
+
+    /* Enable all required interrupts lines for the Pipe2 */
+    __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_VSYNC | DCMIPP_IT_PIPE2_OVR);
+  }
+}
+/**
+  * @brief  Enable the capture for the specified DCMIPP pipe.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval None
+  */
+static void DCMIPP_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Activate the Pipe */
+    SET_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
+
+    /* Start the capture */
+    SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Update the DCMIPP pipe State */
+    hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
+
+    /* Activate the Pipe */
+    SET_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEN);
+
+    /* Start the capture */
+    SET_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
+  }
+  else
+  {
+    /* Activate the Pipe */
+    SET_BIT(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_PIPEN);
+
+    /* Start the capture */
+    SET_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
+  }
+}
+/**
+  * @brief  Stop the capture for the specified DCMIPP pipe.
+  * @param  hdcmipp     Pointer to DCMIPP handle
+  * @param  Pipe        Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DCMIPP_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
+{
+  uint32_t tickstart;
+
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    /* Stop the capture */
+    CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
+
+    /* Poll CPTACT status till No capture currently active */
+    tickstart = HAL_GetTick();
+    do
+    {
+      if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+    } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P0CPTACT) != 0U);
+
+    /* Disable DBM when enabled */
+    if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM)
+    {
+      CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
+    }
+
+    /* Disable the pipe */
+    CLEAR_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
+
+    /* Disable all interrupts for this pipe */
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_LINE | \
+                            DCMIPP_IT_PIPE0_LIMIT | DCMIPP_IT_PIPE0_OVR);
+
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    /* Stop the capture */
+    CLEAR_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
+
+    /* Poll CPTACT status till No capture currently active */
+    tickstart = HAL_GetTick();
+    do
+    {
+      if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+    } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P1CPTACT) != 0U);
+
+    /* Disable DBM when enabled */
+    if ((hdcmipp->Instance->P1PPCR & DCMIPP_P1PPCR_DBM) == DCMIPP_P1PPCR_DBM)
+    {
+      CLEAR_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_DBM);
+    }
+
+    /* Disable the pipe */
+    CLEAR_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEN);
+
+    /* Disable all interrupts for this pipe */
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME | DCMIPP_IT_PIPE1_VSYNC | DCMIPP_IT_PIPE1_LINE | \
+                            DCMIPP_IT_PIPE1_OVR);
+
+  }
+  else
+  {
+    /* Stop the capture */
+    CLEAR_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
+
+    /* Poll CPTACT status till No capture currently active */
+    tickstart = HAL_GetTick();
+    do
+    {
+      if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+    } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P2CPTACT) != 0U);
+
+    /* Disable the pipe */
+    CLEAR_BIT(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_PIPEN);
+
+    /* Disable DBM when enabled */
+    if ((hdcmipp->Instance->P2PPCR & DCMIPP_P2PPCR_DBM) == DCMIPP_P2PPCR_DBM)
+    {
+      CLEAR_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_DBM);
+    }
+
+    /* Disable all interrupts for this pipe */
+    __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_VSYNC | DCMIPP_IT_PIPE2_LINE | \
+                            DCMIPP_IT_PIPE2_OVR);
+
+  }
+
+  return HAL_OK;
+}
+/**
+  * @brief  Configure and enable the specified CSI virtual channel for a DCMIPP pipe.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  Pipe            Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
+  * @param  VirtualChannel  Specifies the virtual channel, can be a value from @ref DCMIPP_Virtual_Channel
+  */
+static HAL_StatusTypeDef DCMIPP_CSI_SetVCConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+  uint32_t tickstart;
+
+  /* Set Virtual Channel ID for the selected Pipe */
+  if (Pipe == DCMIPP_PIPE0)
+  {
+    MODIFY_REG(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_VC, VirtualChannel << DCMIPP_P0FSCR_VC_Pos);
+  }
+  else if (Pipe == DCMIPP_PIPE1)
+  {
+    MODIFY_REG(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_VC, VirtualChannel << DCMIPP_P1FSCR_VC_Pos);
+  }
+  else
+  {
+    /* Those bit fields are meaningful when PIPEDIFF = 1: Pipe1, Pipe2 is fully independent */
+    if ((hdcmipp->Instance->P1FSCR & DCMIPP_P1FSCR_PIPEDIFF) == DCMIPP_P1FSCR_PIPEDIFF)
+    {
+      /* Set Virtual Channel ID and DTIDA for Pipe2 */
+      MODIFY_REG(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_VC, VirtualChannel << DCMIPP_P2FSCR_VC_Pos);
+    }
+  }
+
+  /* Enable the selected virtual channel */
+  switch (VirtualChannel)
+  {
+    case DCMIPP_VIRTUAL_CHANNEL1:
+      SET_BIT(csi_instance->CR, CSI_CR_VC1START);
+      break;
+    case DCMIPP_VIRTUAL_CHANNEL2:
+      SET_BIT(csi_instance->CR, CSI_CR_VC2START);
+      break;
+    case DCMIPP_VIRTUAL_CHANNEL3:
+      SET_BIT(csi_instance->CR, CSI_CR_VC3START);
+      break;
+    default:
+      /* DCMIPP_VIRTUAL_CHANNEL0: */
+      SET_BIT(csi_instance->CR, CSI_CR_VC0START);
+      break;
+  }
+
+  /* wait for the selected virtual channel active state */
+  tickstart = HAL_GetTick();
+  do
+  {
+    if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+    {
+      return HAL_ERROR;
+    }
+  } while ((csi_instance->SR0 & (CSI_SR0_VC0STATEF << VirtualChannel)) != (CSI_SR0_VC0STATEF << VirtualChannel));
+
+  /* Enable the SOF and EOF interrupts for the selected virtual channel */
+  __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, (DCMIPP_CSI_IT_EOF0 << VirtualChannel) | \
+                             (DCMIPP_CSI_IT_SOF0 << VirtualChannel));
+  return HAL_OK;
+}
+/**
+  * @brief  Stop the specified CSI virtual channel.
+  * @param  hdcmipp         Pointer to DCMIPP handle
+  * @param  VirtualChannel  Specifies the virtual channel, can be a value from @ref DCMIPP_Virtual_Channel
+  */
+static HAL_StatusTypeDef DCMIPP_CSI_VCStop(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel)
+{
+  CSI_TypeDef *csi_instance;
+  csi_instance = CSI;
+  uint32_t tickstart;
+
+  UNUSED(hdcmipp);
+
+  /* Enable the selected virtual channel */
+  switch (VirtualChannel)
+  {
+    case DCMIPP_VIRTUAL_CHANNEL1:
+      SET_BIT(csi_instance->CR, CSI_CR_VC1STOP);
+      break;
+    case DCMIPP_VIRTUAL_CHANNEL2:
+      SET_BIT(csi_instance->CR, CSI_CR_VC2STOP);
+      break;
+    case DCMIPP_VIRTUAL_CHANNEL3:
+      SET_BIT(csi_instance->CR, CSI_CR_VC3STOP);
+      break;
+    default:
+      /* DCMIPP_VIRTUAL_CHANNEL0: */
+      SET_BIT(csi_instance->CR, CSI_CR_VC0STOP);
+      break;
+  }
+
+  /* wait for the selected virtual channel active state */
+  tickstart = HAL_GetTick();
+  do
+  {
+    if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
+    {
+      return HAL_ERROR;
+    }
+  } while ((csi_instance->SR0 & (CSI_SR0_VC0STATEF << VirtualChannel)) == (CSI_SR0_VC0STATEF << VirtualChannel));
+
+
+  /* Enable the SOF and EOF interrupts for the selected virtual channel */
+  __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, (DCMIPP_CSI_IT_EOF0 << VirtualChannel) | \
+                              (DCMIPP_CSI_IT_SOF0 << VirtualChannel));
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* DCMIPP */
+#endif /* HAL_DCMIPP_MODULE_ENABLED */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma.c
new file mode 100644
index 000000000..3217e5bee
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma.c
@@ -0,0 +1,1803 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following functionalities of the Direct Memory Access
+  *          (DMA) peripheral:
+  *            + Initialization/De-Initialization Functions
+  *            + I/O Operation Functions
+  *            + State and Errors Functions
+  *            + DMA Attributes Functions
+  *
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  @verbatim
+  ======================================================================================================================
+                       ##### How to use this driver #####
+  ======================================================================================================================
+  [..]
+   (#) GPDMA and HPDMA are made available on this series.
+       Transfer could be done thanks to AXI or AHB ports.
+
+       HPDMA support transmission through:
+         AXI port 0.
+         AHB port 1.
+       GPDMA allows transmission through:
+         GPDMA_P = port-0.
+         GPDMA_M = port-1
+
+       The supported configurations for GPDMA and HPDMA can be found
+       in the Connectivity matrix table of the reference manual.
+       Mind that DTCM and ITCM can be only be accessed thanks to HPDMA
+       AXI port 0.
+    [..]
+      DMA transfer modes are divided to 2 major categories :
+          (+) Normal transfers (legacy)
+          (+) Linked-list transfers
+
+    [..]
+      Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended
+      module.
+
+    [..]
+      Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended
+      module as extensions to normal mode.
+      Advanced features are :
+          (+) Repeated block feature.
+          (+) Trigger feature.
+          (+) Data handling feature.
+
+    [..]
+      DMA Legacy circular transfer, is replaced by circular linked-list configuration.
+
+
+    *** Initialization and De-Initialization ***
+    ============================================
+    [..]
+      For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal
+      SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between
+      peripherals and DMA requests.
+
+    [..]
+      For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through
+      the following parameters:
+
+          (+) Request               : Specifies the DMA channel request
+              Request parameters    :
+              (++) can be a value of DMA_Request_Selection
+
+          (+) BlkHWRequest          : Specifies the Block hardware request mode for DMA channel
+              (++) can be a value of DMA_Block_Request
+
+          (+) Direction             : Specifies the transfer direction for DMA channel
+              (++) can be a value of DMA_Transfer_Direction
+
+          (+) SrcInc                : Specifies the source increment mode for the DMA channel
+              (++) can be a value of DMA_Source_Increment_Mode
+
+          (+) DestInc               : Specifies the destination increment mode for the DMA channel
+              (++) can be a value of DMA_Destination_Increment_Mode
+
+          (+) SrcDataWidth          : Specifies the source data width for the DMA channel
+              (++) can be a value of DMA_Source_Data_Width
+
+          (+) DestDataWidth         : Specifies the destination data width for the DMA channel
+              (++) can be a value of DMA_Destination_Data_Width
+
+          (+) Priority              : Specifies the priority for the DMA channel
+              (++) can be a value of DMA_Priority_Level
+
+          (+) SrcBurstLength        : Specifies the source burst length (number of beats) for the DMA channel
+              (++) can be a value of between 1 and 64
+
+          (+) DestBurstLength       : Specifies the destination burst length (number of beats) for the DMA channel
+              (++) can be a value of between 1 and 64
+
+          (+) TransferAllocatedPort : Specifies the source and destination allocated ports
+              (++) can be a value of DMA_Transfer_Allocated_Port
+
+          (+) TransferEventMode     : Specifies the transfer event mode for the DMA channel
+              (++) can be a value of DMA_Transfer_Event_Mode
+
+          (+) Mode                  : Specifies the transfer mode for the DMA channel
+              (++) can be one of the following modes :
+                  (+++) DMA_NORMAL : Normal Mode
+                  (+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination
+              address and the size of data to be transferred.
+
+          (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be
+              configured by User depending on his application.
+              Transfer level can be :
+              (++) HAL_DMA_HALF_TRANSFER
+              (++) HAL_DMA_FULL_TRANSFER
+              For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code.
+
+          (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode.
+              This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA
+              channel. (This API should not be called from an interrupt service routine)
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+
+          (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list :
+              (++) XferCpltCallback     : transfer complete callback.
+              (++) XferHalfCpltCallback : half transfer complete callback.
+              (++) XferErrorCallback    : transfer error callback.
+              (++) XferAbortCallback    : transfer abort complete callback.
+              (++) XferSuspendCallback  : transfer suspend complete callback.
+
+          (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration
+              of source address,destination address and the size of data to be transferred.
+
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt.
+
+          (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode.
+              This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended,
+              an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback
+              XferAbortCallback. (This API could be called from an interrupt service routine)
+
+
+    *** State and errors ***
+    ========================
+    [..]
+          (+) Use HAL_DMA_GetState() function to get the DMA state.
+          (+) Use HAL_DMA_GetError() function to get the DMA error code.
+
+
+    *** Security and privilege attributes ***
+    =========================================
+    [..]
+          (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes.
+              (++) Security  : at channel level, at source level and at destination level.
+              (++) Privilege : at channel level.
+          (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes.
+          (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes
+              configuration. This API can be called once after each system boot.
+              If called again, HAL_DMA_ConfigChannelAttributes() API has no effect.
+              Unlock is done either by a system boot or a by an RCC reset.
+          (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status.
+          (+) Use HAL_DMA_SetIsolationAttributes() function to configure the HPDMA channel isolation attribute.
+          (+) Use HAL_DMA_GetIsolationAttributes() function to get the HPDMA channel isolation attribute.
+
+    *** Isolation attributes ***
+    ==================================
+    It is recommended to always enable the isolation feature of the DMA (CFEN = 1) of the HPDMA channel.
+    The default isolation shall be 1. i.e. the Cortex CID.
+    Indeed, should the isolation bit CFEN be equal to 0, a default isolation CID is still carried out and is 0 (zero).
+    the CID generated by a channel access is zero-ed when CFEN=0, even if SCID is different from 000.
+
+    Similarly, it is recommended that all RIMU related IP (SDMMC, OTG, ETH, GPU, DMA2D, ...) to always enable and
+    generate (CID = 1).
+
+    *** DMA HAL driver macros list ***
+    ==================================
+    [..]
+      Below the list of most used macros in DMA HAL driver.
+
+          (+) __HAL_DMA_ENABLE        : Enable the specified DMA Channel.
+          (+) __HAL_DMA_DISABLE       : Disable the specified DMA Channel.
+          (+) __HAL_DMA_GET_FLAG      : Get the DMA Channel pending flags.
+          (+) __HAL_DMA_CLEAR_FLAG    : Clear the DMA Channel pending flags.
+          (+) __HAL_DMA_ENABLE_IT     : Enable the specified DMA Channel interrupts.
+          (+) __HAL_DMA_DISABLE_IT    : Disable the specified DMA Channel interrupts.
+          (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not.
+
+    *** Valid burst length ***
+    ==================================
+    [..]
+      HPDMA allowed AXI maximum burst length
+    (+) The maximum allowed AXI burst length shall not exceed 16.
+            (++) If either selected source or destination length is above 16, HAL_DMA_Init will return HAL_ERROR.
+
+    [..]
+     (@) You can refer to the header file of the DMA HAL driver for more useful macros.
+
+    @endverbatim
+  **********************************************************************************************************************
+  */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef ---------------------------------------------------------------------------------------------------*/
+/* Private constants -------------------------------------------------------------------------------------------------*/
+/* Private macro -----------------------------------------------------------------------------------------------------*/
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/* Private function prototypes ---------------------------------------------------------------------------------------*/
+static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
+                          uint32_t SrcAddress,
+                          uint32_t DstAddress,
+                          uint32_t SrcDataSize);
+static void DMA_Init(DMA_HandleTypeDef const *const hdma);
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+  ======================================================================================================================
+                       ##### Initialization and de-initialization functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode.
+
+    [..]
+      (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual.
+      (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and
+  *         create the associated handle.
+  * @note   Warning: the maximum allowed AXI burst length shall not exceed 16.
+  *         Otherwise, an error will be returned and no initialization performed.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
+{
+  /* Get tick number */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
+  {
+    assert_param(IS_DMA_REQUEST(hdma->Init.Request));
+  }
+  assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest));
+  assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc));
+  assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc));
+  assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth));
+  assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+  assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  if (hdma->Init.Mode == DMA_PFCTRL)
+  {
+    assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance));
+  }
+  /* Check DMA channel instance */
+  if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
+  {
+    assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength));
+    assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength));
+    assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort));
+  }
+
+  /* Check if the burst length may face DMA AXI limitation */
+  if (IS_HPDMA_INSTANCE(hdma->Instance) != 0U)
+  {
+    if (((hdma->Init.TransferAllocatedPort & DMA_CTR1_SAP) == DMA_SRC_ALLOCATED_PORT0) &&
+        (hdma->Init.SrcBurstLength > 16U))
+    {
+      return HAL_ERROR;
+    }
+    if (((hdma->Init.TransferAllocatedPort & DMA_CTR1_DAP) == DMA_DEST_ALLOCATED_PORT0) &&
+        (hdma->Init.DestBurstLength > 16U))
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hdma);
+
+  /* Update the DMA channel state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Check if the DMA channel is effectively disabled */
+  while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update the DMA channel error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+      /* Update the DMA channel state */
+      hdma->State = HAL_DMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Initialize the DMA channel registers */
+  DMA_Init(hdma);
+
+  /* Update DMA channel operation mode */
+  hdma->Mode = hdma->Init.Mode;
+
+  /* Update the DMA channel error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Update the DMA channel state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the DMA channel when it is configured in normal mode.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  /* Disable the selected DMA Channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Check if the DMA channel is effectively disabled */
+  while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update the DMA channel error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+      /* Update the DMA channel state */
+      hdma->State = HAL_DMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Reset DMA Channel registers */
+  hdma->Instance->CLBAR = 0U;
+  hdma->Instance->CCR   = 0U;
+  /* As secure, privilege and CID configuration, bit field DSEC and SSEC are managed in   */
+  /* HAL_DMA_ConfigChannelAttributes function, so it mustn't be cleaned in HAL_DMA_DeInit */
+  hdma->Instance->CTR1  = hdma->Instance->CTR1 & (0U | DMA_CTR1_DSEC | DMA_CTR1_SSEC);
+  hdma->Instance->CTR2  = 0U;
+  hdma->Instance->CBR1  = 0U;
+  hdma->Instance->CSAR  = 0U;
+  hdma->Instance->CDAR  = 0U;
+  hdma->Instance->CLLR  = 0U;
+
+  /* Reset 2D Addressing registers */
+  if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+  {
+    hdma->Instance->CTR3 = 0U;
+    hdma->Instance->CBR2 = 0U;
+  }
+
+  /* Clear all flags */
+  __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+                              DMA_FLAG_TO));
+
+  /* Clean all callbacks */
+  hdma->XferCpltCallback     = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferErrorCallback    = NULL;
+  hdma->XferAbortCallback    = NULL;
+  hdma->XferSuspendCallback  = NULL;
+
+  /* Clean DMA queue */
+  hdma->LinkedListQueue = NULL;
+
+  /* Clean DMA parent */
+  if (hdma->Parent != NULL)
+  {
+    hdma->Parent = NULL;
+  }
+
+  /* Update DMA channel operation mode */
+  hdma->Mode = DMA_NORMAL;
+
+  /* Update the DMA channel error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Update the DMA channel state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim
+  ======================================================================================================================
+                                ##### IO operation functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to :
+      (+) Configure the source, destination address and data size and Start DMA transfer in normal mode
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+      (+) Register and Unregister DMA callbacks
+
+    [..]
+      (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode).
+      (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode).
+      (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode).
+      (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode).
+      (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode).
+          This API cannot be used for circular transfers.
+      (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode).
+      (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and
+          unregister user customized callbacks.
+          User callbacks are called under HAL_DMA_IRQHandler().
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA channel transfer in normal mode (Blocking mode).
+  * @param  hdma        : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
+  *                       the specified DMA Channel.
+  * @param  SrcAddress  : The source data address.
+  * @param  DstAddress  : The destination data address.
+  * @param  SrcDataSize : The length of data to be transferred from source to destination in bytes.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
+                                uint32_t SrcAddress,
+                                uint32_t DstAddress,
+                                uint32_t SrcDataSize)
+{
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  /* Check DMA channel state */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Configure the source address, destination address, the data size and clear flags */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
+
+    /* Enable DMA channel */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode).
+  * @param  hdma         : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                        specified DMA Channel.
+  * @param  SrcAddress   : The source data address.
+  * @param  DstAddress   : The destination data address.
+  * @param  SrcDataSize  : The length of data to be transferred from source to destination in bytes.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
+                                   uint32_t SrcAddress,
+                                   uint32_t DstAddress,
+                                   uint32_t SrcDataSize)
+{
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  /* Check DMA channel state */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Configure the source address, destination address, the data size and clear flags */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
+
+    /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
+    __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
+
+    /* Check half transfer complete callback */
+    if (hdma->XferHalfCpltCallback != NULL)
+    {
+      /* If Half Transfer complete callback is set, enable the corresponding IT */
+      __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+    }
+
+    /* Check Half suspend callback */
+    if (hdma->XferSuspendCallback != NULL)
+    {
+      /* If Transfer suspend callback is set, enable the corresponding IT */
+      __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
+    }
+
+    /* Enable DMA channel */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort any on-going DMA channel transfer (Blocking mode).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @note   After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel
+  *         is suspended while a data transfer is on-going, the current data will be transferred and the channel will be
+  *         effectively suspended only after the transfer of any on-going data is finished.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma)
+{
+  /* Get tick number */
+  uint32_t tickstart =  HAL_GetTick();
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  if (hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Suspend the channel */
+    hdma->Instance->CCR |= DMA_CCR_SUSP;
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_SUSPEND;
+
+    /* Check if the DMA Channel is suspended */
+    while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update the DMA channel error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+        /* Update the DMA channel state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        /* Check DMA channel transfer mode */
+        if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          /* Update the linked-list queue state */
+          hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Reset the channel */
+    hdma->Instance->CCR |= DMA_CCR_RESET;
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_ABORT;
+
+    /* Clear all status flags */
+    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+                                DMA_FLAG_TO));
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Check DMA channel transfer mode */
+    if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      /* Update the linked-list queue state */
+      hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+
+      /* Clear remaining data size to ensure loading linked-list from memory next start */
+      hdma->Instance->CBR1 = 0U;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma)
+{
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  if (hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_ABORT;
+
+    /* Suspend the channel and activate suspend interrupt */
+    hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer status (Blocking mode).
+  * @param  hdma          : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                         specified DMA Channel.
+  * @param  CompleteLevel : Specifies the DMA level complete.
+  * @param  Timeout       : Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
+                                          HAL_DMA_LevelCompleteTypeDef CompleteLevel,
+                                          uint32_t Timeout)
+{
+  /* Get tick number */
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t level_flag;
+  uint32_t tmp_csr;
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel));
+
+  /* Check DMA channel state */
+  if (hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  /* Polling mode is not supported in circular mode */
+  if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Get the level transfer complete flag */
+  level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT);
+
+  /* Get DMA channel status */
+  tmp_csr = hdma->Instance->CSR;
+
+  while ((tmp_csr & level_flag) == 0U)
+  {
+    /* Check for the timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Update the DMA channel error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+        /*
+          If timeout, abort the current transfer.
+          Note that the Abort function will
+          - Clear all transfer flags.
+          - Unlock.
+          - Set the State.
+        */
+        (void)HAL_DMA_Abort(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get a newer CSR register value */
+    tmp_csr = hdma->Instance->CSR;
+  }
+
+  /* Check trigger overrun flag */
+  if ((tmp_csr & DMA_FLAG_TO) != 0U)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_TO;
+
+    /* Clear the error flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
+  }
+
+  /* Check error flags */
+  if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U)
+  {
+    /* Check the data transfer error flag */
+    if ((tmp_csr & DMA_FLAG_DTE) != 0U)
+    {
+      /* Update the DMA channel error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
+
+      /* Clear the error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
+    }
+
+    /* Check the update link error flag */
+    if ((tmp_csr & DMA_FLAG_ULE) != 0U)
+    {
+      /* Update the DMA channel error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
+
+      /* Clear the error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
+    }
+
+    /* Check the user setting error flag */
+    if ((tmp_csr & DMA_FLAG_USE) != 0U)
+    {
+      /* Update the DMA channel error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_USE;
+
+      /* Clear the error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
+    }
+
+    /* Reset the channel */
+    hdma->Instance->CCR |= DMA_CCR_RESET;
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Check DMA channel transfer mode */
+    if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      /* Update the linked-list queue state */
+      hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  /* Clear the transfer level flag */
+  if (CompleteLevel == HAL_DMA_HALF_TRANSFER)
+  {
+    /* Clear the Half Transfer flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
+  }
+  else if (CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the transfer flags */
+    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Check DMA channel transfer mode */
+    if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      /* Update the linked-list queue state */
+      hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle DMA interrupt request (Non-blocking mode).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval None.
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
+{
+  const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
+  uint32_t global_it_flag =  1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+  uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag);
+#if defined (CPU_IN_SECURE_STATE)
+  uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag);
+#endif /* CPU_IN_SECURE_STATE */
+
+  /* Global Interrupt Flag management *********************************************************************************/
+#if defined (CPU_IN_SECURE_STATE)
+  if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U))
+#else
+  if (global_active_flag_ns == 0U)
+#endif /* CPU_IN_SECURE_STATE */
+  {
+    return; /* the global interrupt flag for the current channel is down , nothing to do */
+  }
+
+  /* Data Transfer Error Interrupt management *************************************************************************/
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)
+  {
+    /* Check if interrupt source is enabled */
+    if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U)
+    {
+      /* Clear the transfer error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
+
+      /* Update the DMA channel error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
+    }
+  }
+
+  /* Update Linked-list Error Interrupt management ********************************************************************/
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)
+  {
+    /* Check if interrupt source is enabled */
+    if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U)
+    {
+      /* Clear the update linked-list error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
+
+      /* Update the DMA channel error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
+    }
+  }
+
+  /* User Setting Error Interrupt management **************************************************************************/
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)
+  {
+    /* Check if interrupt source is enabled */
+    if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U)
+    {
+      /* Clear the user setting error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
+
+      /* Update the DMA channel error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_USE;
+    }
+  }
+
+  /* Trigger Overrun Interrupt management *****************************************************************************/
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)
+  {
+    /* Check if interrupt source is enabled */
+    if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U)
+    {
+      /* Clear the trigger overrun flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
+
+      /* Update the DMA channel error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TO;
+    }
+  }
+
+  /* Half Transfer Complete Interrupt management **********************************************************************/
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)
+  {
+    /* Check if interrupt source is enabled */
+    if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+    {
+      /* Clear the half transfer flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
+
+      /* Check half transfer complete callback */
+      if (hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Half transfer callback */
+        hdma->XferHalfCpltCallback(hdma);
+      }
+    }
+  }
+
+  /* Suspend Transfer Interrupt management ****************************************************************************/
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)
+  {
+    /* Check if interrupt source is enabled */
+    if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U)
+    {
+      /* Clear the block transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP);
+
+      /* Check DMA channel state */
+      if (hdma->State == HAL_DMA_STATE_ABORT)
+      {
+        /* Disable the suspend transfer interrupt */
+        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP);
+
+        /* Reset the channel internal state and reset the FIFO */
+        hdma->Instance->CCR |= DMA_CCR_RESET;
+
+        /* Update the DMA channel state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Check DMA channel transfer mode */
+        if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          /* Update the linked-list queue state */
+          hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+
+          /* Clear remaining data size to ensure loading linked-list from memory next start */
+          hdma->Instance->CBR1 = 0U;
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Check transfer abort callback */
+        if (hdma->XferAbortCallback != NULL)
+        {
+          /* Transfer abort callback */
+          hdma->XferAbortCallback(hdma);
+        }
+
+        return;
+      }
+      else
+      {
+        /* Update the DMA channel state */
+        hdma->State = HAL_DMA_STATE_SUSPEND;
+
+        /* Check transfer suspend callback */
+        if (hdma->XferSuspendCallback != NULL)
+        {
+          /* Transfer suspend callback */
+          hdma->XferSuspendCallback(hdma);
+        }
+      }
+    }
+  }
+
+  /* Transfer Complete Interrupt management ***************************************************************************/
+  if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)
+  {
+    /* Check if interrupt source is enabled */
+    if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+    {
+      /* Check DMA channel transfer mode */
+      if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        /* If linked-list transfer */
+        if (hdma->Instance->CLLR == 0U)
+        {
+          if (hdma->Instance->CBR1 == 0U)
+          {
+            /* Update the DMA channel state */
+            hdma->State = HAL_DMA_STATE_READY;
+
+            /* Update the linked-list queue state */
+            hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+          }
+        }
+      }
+      else
+      {
+        /* If normal transfer */
+        if (hdma->Instance->CBR1 == 0U)
+        {
+          /* Update the DMA channel state */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+      }
+
+      /* Clear TC and HT transfer flags */
+      __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Check transfer complete callback */
+      if (hdma->XferCpltCallback != NULL)
+      {
+        /* Channel Transfer Complete callback */
+        hdma->XferCpltCallback(hdma);
+      }
+    }
+  }
+
+  /* Manage error case ************************************************************************************************/
+  if (hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    /* Reset the channel internal state and reset the FIFO */
+    hdma->Instance->CCR |= DMA_CCR_RESET;
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_READY;
+
+    /* Check DMA channel transfer mode */
+    if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      /* Update the linked-list queue state */
+      hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Check transfer error callback */
+    if (hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  Register callback according to specified ID.
+  * @note   The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
+  *         to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
+  * @param  hdma       : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                      specified DMA Channel.
+  * @param  CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration.
+  * @param  pCallback  : Pointer to private callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
+                                           HAL_DMA_CallbackIDTypeDef CallbackID,
+                                           void (*const pCallback)(DMA_HandleTypeDef *const _hdma))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Check callback ID */
+    switch (CallbackID)
+    {
+      case HAL_DMA_XFER_CPLT_CB_ID:
+      {
+        /* Register transfer complete callback */
+        hdma->XferCpltCallback = pCallback;
+        break;
+      }
+
+      case HAL_DMA_XFER_HALFCPLT_CB_ID:
+      {
+        /* Register half transfer callback */
+        hdma->XferHalfCpltCallback = pCallback;
+        break;
+      }
+
+      case HAL_DMA_XFER_ERROR_CB_ID:
+      {
+        /* Register transfer error callback */
+        hdma->XferErrorCallback = pCallback;
+        break;
+      }
+
+      case HAL_DMA_XFER_ABORT_CB_ID:
+      {
+        /* Register abort callback */
+        hdma->XferAbortCallback = pCallback;
+        break;
+      }
+
+      case HAL_DMA_XFER_SUSPEND_CB_ID:
+      {
+        /* Register suspend callback */
+        hdma->XferSuspendCallback = pCallback;
+        break;
+      }
+
+      default:
+      {
+        /* Update error status */
+        status = HAL_ERROR;
+        break;
+      }
+    }
+  }
+  else
+  {
+    /* Update error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister callback according to specified ID.
+  * @note   The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
+  *         to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
+  * @param  hdma       : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                      specified DMA Channel.
+  * @param  CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
+                                             HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Check callback ID */
+    switch (CallbackID)
+    {
+      case HAL_DMA_XFER_CPLT_CB_ID:
+      {
+        /* UnRegister transfer complete callback */
+        hdma->XferCpltCallback = NULL;
+        break;
+      }
+
+      case HAL_DMA_XFER_HALFCPLT_CB_ID:
+      {
+        /* UnRegister half transfer callback */
+        hdma->XferHalfCpltCallback = NULL;
+        break;
+      }
+
+      case HAL_DMA_XFER_ERROR_CB_ID:
+      {
+        /* UnRegister transfer error callback */
+        hdma->XferErrorCallback = NULL;
+        break;
+      }
+
+      case HAL_DMA_XFER_ABORT_CB_ID:
+      {
+        /* UnRegister abort callback */
+        hdma->XferAbortCallback = NULL;
+        break;
+      }
+
+      case HAL_DMA_XFER_SUSPEND_CB_ID:
+      {
+        /* UnRegister suspend callback */
+        hdma->XferSuspendCallback = NULL;
+        break;
+      }
+
+      case HAL_DMA_XFER_ALL_CB_ID:
+      {
+        /* UnRegister all available callbacks */
+        hdma->XferCpltCallback     = NULL;
+        hdma->XferHalfCpltCallback = NULL;
+        hdma->XferErrorCallback    = NULL;
+        hdma->XferAbortCallback    = NULL;
+        hdma->XferSuspendCallback  = NULL;
+        break;
+      }
+
+      default:
+      {
+        /* Update error status */
+        status = HAL_ERROR;
+        break;
+      }
+    }
+  }
+  else
+  {
+    /* Update error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+  ======================================================================================================================
+                              ##### State and Errors functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to :
+      (+) Check the DMA state
+      (+) Get error code
+
+    [..]
+      (+) The HAL_DMA_GetState() function allows to get the DMA channel state.
+      (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA channel state.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval DMA state.
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma)
+{
+  /* Return the DMA channel state */
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA channel error code.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval DMA Error Code.
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma)
+{
+  /* Return the DMA channel error code */
+  return hdma->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group4
+  *
+@verbatim
+  ======================================================================================================================
+                           ##### DMA Attributes functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to :
+      (+) Configure DMA channel secure and privilege attributes.
+      (+) Get DMA channel secure and privilege attributes.
+      (+) Lock DMA channel secure and privilege attributes configuration.
+      (+) Check whether DMA channel secure and privilege attributes configuration is locked or not.
+
+    [..]
+      (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege
+          attributes.
+      (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes
+          configuration.
+      (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes.
+      (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege
+          attributes lock status.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DMA channel security and privilege attribute(s).
+  * @note   These attributes cannot be modified when the corresponding lock state is enabled.
+  * @param  hdma              : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
+  *                             the specified DMA Channel.
+  * @param  ChannelAttributes : Specifies the DMA channel secure/privilege attributes.
+  *                             This parameter can be a one or a combination of @ref DMA_Channel_Attributes.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes)
+{
+  DMA_TypeDef *p_dma_instance;
+  uint32_t channel_idx;
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes));
+
+  /* Get DMA instance */
+  p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+  /* Get channel index */
+  channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+  /* Check DMA channel privilege attribute management */
+  if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK)
+  {
+    /* Configure DMA channel privilege attribute */
+    if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV)
+    {
+      p_dma_instance->PRIVCFGR |= channel_idx;
+    }
+    else
+    {
+      p_dma_instance->PRIVCFGR &= (~channel_idx);
+    }
+  }
+
+#if defined (CPU_IN_SECURE_STATE)
+  /* Check DMA channel security attribute management */
+  if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK)
+  {
+    /* Configure DMA channel security attribute */
+    if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC)
+    {
+      p_dma_instance->SECCFGR |= channel_idx;
+    }
+    else
+    {
+      p_dma_instance->SECCFGR &= (~channel_idx);
+    }
+  }
+
+  /* Channel source security attribute management */
+  if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK)
+  {
+    /* Configure DMA channel source security attribute */
+    if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC)
+    {
+      hdma->Instance->CTR1 |= DMA_CTR1_SSEC;
+    }
+    else
+    {
+      hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC);
+    }
+  }
+
+  /* Channel destination security attribute management */
+  if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK)
+  {
+    /* Configure DMA channel destination security attribute */
+    if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC)
+    {
+      hdma->Instance->CTR1 |= DMA_CTR1_DSEC;
+    }
+    else
+    {
+      hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC);
+    }
+  }
+#endif /* CPU_IN_SECURE_STATE */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the DMA channel security and privilege attributes.
+  * @param  hdma               : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                              for the specified DMA Channel.
+  * @param  pChannelAttributes : Pointer to the returned attributes.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
+                                                     uint32_t *const pChannelAttributes)
+{
+  const DMA_TypeDef *p_dma_instance;
+  uint32_t attributes;
+  uint32_t channel_idx;
+
+  /* Check the DMA peripheral handle and channel attributes parameters */
+  if ((hdma == NULL) || (pChannelAttributes == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get DMA instance */
+  p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+  /* Get channel index */
+  channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+  /* Get DMA channel privilege attribute */
+  attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV;
+
+  /* Get DMA channel security attribute */
+  attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC;
+
+  /* Get DMA channel source security attribute */
+  attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC;
+
+  /* Get DMA channel destination security attribute */
+  attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC;
+
+  /* return value */
+  *pChannelAttributes = attributes;
+
+  return HAL_OK;
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Set the DMA channel filtering CID (Isolation configuration). It can be
+  *             - static: the CID passed as parameter is programmed;
+  *             - disabled: the whole register is cleared.
+  * @param  hdma    : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                of the HPDMA channel.
+  * @param  pConfig : Pointer on the DMA Isolation structure
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_DMA_SetIsolationAttributes(DMA_HandleTypeDef *const hdma,
+                                                 DMA_IsolationConfigTypeDef const *const pConfig)
+{
+  /* Check the DMA peripheral handle parameter */
+  if ((hdma == NULL) || (pConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_HPDMA_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_ISOLATION_MODE(pConfig->CidFiltering));
+  assert_param(IS_DMA_ISOLATION_STATIC_CID(pConfig->StaticCid));
+
+  /* static CID field value used when filtering is enable */
+  if ((pConfig->CidFiltering) == DMA_ISOLATION_ON)
+  {
+    /* Write static CID configuration */
+    hdma->Instance->CCIDCFGR = ((pConfig->StaticCid & DMA_CCIDCFGR_SCID_Msk) | DMA_CCIDCFGR_CFEN);
+  }
+  else
+  {
+    /* CID configuration is off */
+    hdma->Instance->CCIDCFGR = 0U;
+  }
+
+  return HAL_OK;
+}
+#endif /* CPU_IN_SECURE_STATE */
+/**
+  * @brief  Read the DMA channel filtering CID (Isolation configuration). It can be
+  *             - static: the CID passed as parameter is programmed;
+  *             - disabled: the whole register is cleared.
+  * @param  hdma    : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                of the HPDMA channel.
+  * @param  pConfig : Pointer on the DMA Isolation structure
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const *const hdma,
+                                                 DMA_IsolationConfigTypeDef *const pConfig)
+{
+  uint32_t ccidcfgr;
+
+  /* Check the DMA peripheral handle parameter */
+  if ((hdma == NULL) || (pConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  ccidcfgr = hdma->Instance->CCIDCFGR;
+
+  /* Check the parameters */
+  assert_param(IS_HPDMA_INSTANCE(hdma->Instance));
+
+  if ((ccidcfgr & DMA_CCIDCFGR_CFEN) == DMA_CCIDCFGR_CFEN)
+  {
+    pConfig->CidFiltering = DMA_ISOLATION_ON;
+  }
+  else
+  {
+    pConfig->CidFiltering = DMA_ISOLATION_OFF;
+  }
+  pConfig->StaticCid = (ccidcfgr & DMA_CCIDCFGR_SCID_Msk);
+
+  return HAL_OK;
+}
+
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Lock the DMA channel security and privilege attribute(s).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma)
+{
+  DMA_TypeDef *p_dma_instance;
+  uint32_t channel_idx;
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get DMA instance */
+  p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+  /* Get channel index */
+  channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+  /* Lock the DMA channel privilege and security attributes */
+  p_dma_instance->RCFGLOCKR |= channel_idx;
+
+  return HAL_OK;
+}
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Get the security and privilege attribute lock state of a DMA channel.
+  * @param  hdma       : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                      specified DMA Channel.
+  * @param  pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or
+  *                      DMA_CHANNEL_ATTRIBUTE_LOCKED).
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState)
+{
+  const DMA_TypeDef *p_dma_instance;
+  uint32_t channel_idx;
+
+  /* Check the DMA peripheral handle and lock state parameters */
+  if ((hdma == NULL) || (pLockState == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get DMA instance */
+  p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+  /* Get channel index */
+  channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
+
+  /* Get channel lock attribute state */
+  *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \
+                DMA_CHANNEL_ATTRIBUTE_LOCKED;
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA channel normal transfer parameters.
+  * @param  hdma        : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                       specified DMA Channel.
+  * @param  SrcAddress  : The source data address.
+  * @param  DstAddress  : The destination data address.
+  * @param  SrcDataSize : The length of data to be transferred from source to destination in bytes.
+  * @retval None.
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
+                          uint32_t SrcAddress,
+                          uint32_t DstAddress,
+                          uint32_t SrcDataSize)
+{
+  /* Configure the DMA channel data size */
+  MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT));
+
+  /* Clear all interrupt flags */
+  __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+                       DMA_FLAG_TO);
+
+  /* Configure DMA channel source address */
+  hdma->Instance->CSAR = SrcAddress;
+
+  /* Configure DMA channel destination address */
+  hdma->Instance->CDAR = DstAddress;
+}
+
+/**
+  * @brief  Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval None.
+  */
+static void DMA_Init(DMA_HandleTypeDef const *const hdma)
+{
+  uint32_t tmpreg;
+
+  /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/
+  tmpreg = hdma->Init.Priority;
+
+  /* Write DMA Channel Control Register (CCR) */
+  MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
+
+  /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/
+  tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth;
+
+  /* Add parameters specific to HPDMA and GPDMA */
+  if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
+  {
+    tmpreg |= (hdma->Init.TransferAllocatedPort                                             |
+               (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) |
+               (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
+  }
+
+  /* Write DMA Channel Transfer Register 1 (CTR1) */
+  MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg);
+
+  /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/
+  tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode;
+
+  /* Memory to Peripheral Transfer */
+  if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
+    {
+      tmpreg |= DMA_CTR2_DREQ;
+    }
+  }
+  /* Memory to Memory Transfer */
+  else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY)
+  {
+    tmpreg |= DMA_CTR2_SWREQ;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Set DMA channel operation mode */
+  tmpreg |= hdma->Init.Mode;
+
+  /* Write DMA Channel Transfer Register 2 (CTR2) */
+  MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM  | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM |
+                                    DMA_CTR2_PFREQ | DMA_CTR2_BREQ  | DMA_CTR2_DREQ    | DMA_CTR2_SWREQ   |
+                                    DMA_CTR2_REQSEL), tmpreg);
+
+
+  /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/
+  WRITE_REG(hdma->Instance->CBR1, 0U);
+
+  /* If 2D Addressing is supported by current channel */
+  if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+  {
+    /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/
+    WRITE_REG(hdma->Instance->CTR3, 0U);
+
+    /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/
+    WRITE_REG(hdma->Instance->CBR2, 0U);
+  }
+
+  /* Write DMA Channel linked-list address register (CLLR) ************************************************************/
+  WRITE_REG(hdma->Instance->CLLR, 0U);
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma2d.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma2d.c
new file mode 100644
index 000000000..86cbd721d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma2d.c
@@ -0,0 +1,2186 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_dma2d.c
+  * @author  MCD Application Team
+  * @brief   DMA2D HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DMA2D peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Program the required configuration through the following parameters:
+          the transfer mode, the output color mode and the output offset using
+          HAL_DMA2D_Init() function.
+
+      (#) Program the required configuration through the following parameters:
+          the input color mode, the input color, the input alpha value, the alpha mode,
+          the red/blue swap mode, the inverted alpha mode and the input offset using
+          HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+       (#) Configure pdata parameter (explained hereafter), destination and data length
+           and enable the transfer using HAL_DMA2D_Start().
+       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
+           user can specify the value of timeout according to his end application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (#) Configure pdata parameter, destination and data length and enable
+           the transfer using HAL_DMA2D_Start_IT().
+       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
+       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
+           add his own function by customization of function pointer XferCpltCallback (member
+           of DMA2D handle structure).
+       (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
+           XferErrorCallback.
+
+         -@-   In Register-to-Memory transfer mode, pdata parameter is the register
+               color, in Memory-to-memory or Memory-to-Memory with pixel format
+               conversion pdata is the source address.
+
+         -@-   Configure the foreground source address, the background source address,
+               the destination and data length then Enable the transfer using
+               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
+               in interrupt mode.
+
+         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
+               are used if the memory to memory with blending transfer mode is selected.
+
+      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
+          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
+
+      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
+
+      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
+          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
+          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
+          HAL_DMA2D_DisableDeadTime().
+
+      (#) The transfer can be suspended, resumed and aborted using the following
+          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
+
+      (#) The CLUT loading can be suspended, resumed and aborted using the following
+          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
+          HAL_DMA2D_CLUTLoading_Abort().
+
+      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
+
+      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
+
+     *** DMA2D HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA2D HAL driver :
+
+      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
+      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
+      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
+      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
+      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
+
+     *** Callback registration ***
+     ===================================
+     [..]
+      (#) The compilation define  USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
+          allows the user to configure dynamically the driver callbacks.
+          Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
+
+      (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
+            (+) XferCpltCallback : callback for transfer complete.
+            (+) XferErrorCallback : callback for transfer error.
+            (+) LineEventCallback : callback for line event.
+            (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+            (+) MspInitCallback    : DMA2D MspInit.
+            (+) MspDeInitCallback  : DMA2D MspDeInit.
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+      (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
+          weak (surcharged) function.
+          @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (+) XferCpltCallback : callback for transfer complete.
+            (+) XferErrorCallback : callback for transfer error.
+            (+) LineEventCallback : callback for line event.
+            (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+            (+) MspInitCallback    : DMA2D MspInit.
+            (+) MspDeInitCallback  : DMA2D MspDeInit.
+
+      (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
+          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+          examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
+          Exception done for MspInit and MspDeInit callbacks that are respectively
+          reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+          and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
+          If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
+          keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+          Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
+          as weak (surcharged) functions. They must be defined by the user to be resorted to.
+
+          Callbacks can be registered/unregistered in READY state only.
+          Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+          in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+          during the Init/DeInit.
+          In that case first register the MspInit/MspDeInit user callbacks
+          using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
+          or @ref HAL_DMA2D_Init function.
+
+          When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
+          not defined, the callback registering feature is not available
+          and weak (surcharged) callbacks are used.
+
+     [..]
+      (@) You can refer to the DMA2D HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#if defined (DMA2D)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA2D  DMA2D
+  * @brief DMA2D HAL module driver
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
+  * @{
+  */
+
+/** @defgroup DMA2D_TimeOut DMA2D Time Out
+  * @{
+  */
+#define DMA2D_TIMEOUT_ABORT           (1000U)  /*!<  1s  */
+#define DMA2D_TIMEOUT_SUSPEND         (1000U)  /*!<  1s  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
+  * @{
+  */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                            uint32_t Height);
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DMA2D
+      (+) De-initialize the DMA2D
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA2D according to the specified
+  *         parameters in the DMA2D_InitTypeDef and create the associated handle.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Check the DMA2D peripheral state */
+  if (hdma2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
+  assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
+  assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
+  assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+  assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
+  assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
+  assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
+  assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+  if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+  {
+    /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
+    hdma2d->LineEventCallback       = HAL_DMA2D_LineEventCallback;
+    hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+    if (hdma2d->MspInitCallback == NULL)
+    {
+      hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hdma2d->MspInitCallback(hdma2d);
+  }
+#else
+  if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hdma2d->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_DMA2D_MspInit(hdma2d);
+  }
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* DMA2D CR register configuration -------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
+
+  /* DMA2D OPFCCR register configuration ---------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB,
+             hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
+
+  /* DMA2D OOR register configuration ------------------------------------------*/
+  MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
+  /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
+  MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS),
+             ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \
+              (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
+
+
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the DMA2D peripheral registers to their default reset
+  *         values.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+
+  /* Check the DMA2D peripheral state */
+  if (hdma2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Before aborting any DMA2D transfer or CLUT loading, check
+     first whether or not DMA2D clock is enabled */
+  if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U)
+  {
+    /* Abort DMA2D transfer if any */
+    if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
+    {
+      if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
+      {
+        /* Issue when aborting DMA2D transfer */
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Abort background CLUT loading if any */
+      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+      {
+        if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
+        {
+          /* Issue when aborting background CLUT loading */
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Abort foreground CLUT loading if any */
+        if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+        {
+          if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
+          {
+            /* Issue when aborting foreground CLUT loading */
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+  }
+
+  /* Reset DMA2D control registers*/
+  hdma2d->Instance->CR       =    0U;
+  hdma2d->Instance->IFCR     = 0x3FU;
+  hdma2d->Instance->FGOR     =    0U;
+  hdma2d->Instance->BGOR     =    0U;
+  hdma2d->Instance->FGPFCCR  =    0U;
+  hdma2d->Instance->BGPFCCR  =    0U;
+  hdma2d->Instance->OPFCCR   =    0U;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+
+  if (hdma2d->MspDeInitCallback == NULL)
+  {
+    hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hdma2d->MspDeInitCallback(hdma2d);
+
+#else
+  /* Carry on with de-initialization of low level hardware */
+  HAL_DMA2D_MspDeInit(hdma2d);
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+  /* Update error code */
+  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
+
+  /* Initialize the DMA2D state*/
+  hdma2d->State  = HAL_DMA2D_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the DMA2D MSP.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspInit can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitializes the DMA2D MSP.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_MspDeInit can be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User DMA2D Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hdma2d DMA2D handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+  *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+  *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+  *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+  *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+  *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+                                             pDMA2D_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  if (HAL_DMA2D_STATE_READY == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+        hdma2d->XferCpltCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_TRANSFERERROR_CB_ID :
+        hdma2d->XferErrorCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_LINEEVENT_CB_ID :
+        hdma2d->LineEventCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+        hdma2d->CLUTLoadingCpltCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = pCallback;
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+  return status;
+}
+
+/**
+  * @brief  Unregister a DMA2D Callback
+  *         DMA2D Callback is redirected to the weak (surcharged) predefined callback
+  * @param hdma2d DMA2D handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+  *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+  *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+  *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+  *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+  *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+  * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  if (HAL_DMA2D_STATE_READY == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+        hdma2d->XferCpltCallback = NULL;
+        break;
+
+      case HAL_DMA2D_TRANSFERERROR_CB_ID :
+        hdma2d->XferErrorCallback = NULL;
+        break;
+
+      case HAL_DMA2D_LINEEVENT_CB_ID :
+        hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+        break;
+
+      case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+        hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+        break;
+
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DMA2D_MSPINIT_CB_ID :
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (surcharged) Msp Init */
+        break;
+
+      case HAL_DMA2D_MSPDEINIT_CB_ID :
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma2d);
+  return status;
+}
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the pdata, destination address and data size then
+          start the DMA2D transfer.
+      (+) Configure the source for foreground and background, destination address
+          and data size then start a MultiBuffer DMA2D transfer.
+      (+) Configure the pdata, destination address and data size then
+          start the DMA2D transfer with interrupt.
+      (+) Configure the source for foreground and background, destination address
+          and data size then start a MultiBuffer DMA2D transfer with interrupt.
+      (+) Abort DMA2D transfer.
+      (+) Suspend DMA2D transfer.
+      (+) Resume DMA2D transfer.
+      (+) Enable CLUT transfer.
+      (+) Configure CLUT loading then start transfer in polling mode.
+      (+) Configure CLUT loading then start transfer in interrupt mode.
+      (+) Abort DMA2D CLUT loading.
+      (+) Suspend DMA2D CLUT loading.
+      (+) Resume DMA2D CLUT loading.
+      (+) Poll for transfer complete.
+      (+) handle DMA2D interrupt request.
+      (+) Transfer watermark callback.
+      (+) CLUT Transfer Complete callback.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA2D Transfer.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  pdata      Configure the source memory Buffer address if
+  *                     Memory-to-Memory or Memory-to-Memory with pixel format
+  *                     conversion mode is selected, or configure
+  *                     the color value if Register-to-Memory mode is selected.
+  * @param  DstAddress The destination memory Buffer address.
+  * @param  Width      The width of data to be transferred from source
+  *                    to destination (expressed in number of pixels per line).
+  * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  pdata      Configure the source memory Buffer address if
+  *                     the Memory-to-Memory or Memory-to-Memory with pixel format
+  *                     conversion mode is selected, or configure
+  *                     the color value if Register-to-Memory mode is selected.
+  * @param  DstAddress The destination memory Buffer address.
+  * @param  Width      The width of data to be transferred from source
+  *                    to destination (expressed in number of pixels per line).
+  * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                                     uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the source, destination address and the data size */
+  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
+
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer.
+  * @param  hdma2d      Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                      the configuration information for the DMA2D.
+  * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2 The source memory Buffer address for the background layer.
+  * @param  DstAddress  The destination memory Buffer address.
+  * @param  Width       The width of data to be transferred from source
+  *                     to destination (expressed in number of pixels per line).
+  * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2,
+                                          uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+  {
+    /*blending & fixed FG*/
+    WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
+    /* Configure the source, destination address and the data size */
+    DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
+  }
+  else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
+  {
+    /*blending & fixed BG*/
+    WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
+    /* Configure the source, destination address and the data size */
+    DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+  }
+  else
+  {
+    /* Configure DMA2D Stream source2 address */
+    WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+    /* Configure the source, destination address and the data size */
+    DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the DMA2D.
+  * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
+  * @param  SrcAddress2 The source memory Buffer address for the background layer.
+  * @param  DstAddress  The destination memory Buffer address.
+  * @param  Width       The width of data to be transferred from source
+  *                     to destination (expressed in number of pixels per line).
+  * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2,
+                                             uint32_t DstAddress, uint32_t Width,  uint32_t Height)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LINE(Height));
+  assert_param(IS_DMA2D_PIXEL(Width));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+  {
+    /*blending & fixed FG*/
+    WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
+    /* Configure the source, destination address and the data size */
+    DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
+  }
+  else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
+  {
+    /*blending & fixed BG*/
+    WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
+    /* Configure the source, destination address and the data size */
+    DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+  }
+  else
+  {
+    WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+
+    /* Configure the source, destination address and the data size */
+    DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+  }
+
+  /* Enable the transfer complete, transfer error and configuration error interrupts */
+  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+  /* Enable the Peripheral */
+  __HAL_DMA2D_ENABLE(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D Transfer.
+  * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t tickstart;
+
+  /* Abort the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing 0 has no
+     effect on START bitvalue) */
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DMA2D is effectively disabled */
+  while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D Transfer.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t tickstart;
+
+  /* Suspend the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing 0 has no
+     effect on START bitvalue). */
+  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DMA2D is effectively suspended */
+  while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  {
+    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+  }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless
+       when no transfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D Transfer.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Check the SUSP and START bits */
+  if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
+  {
+    /* Ongoing transfer is suspended: change the DMA2D state before resuming */
+    hdma2d->State = HAL_DMA2D_STATE_BUSY;
+  }
+
+  /* Resume the DMA2D transfer */
+  /* START bit is reset to make sure not to set it again, in the event the HW clears it
+     between the register read and the register write by the CPU (writing 0 has no
+     effect on START bitvalue). */
+  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Enable the DMA2D CLUT Transfer.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Enable the background CLUT loading */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  else
+  {
+    /* Enable the foreground CLUT loading */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
+                                          uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading with interrupt enabled.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
+                                             uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @note API obsolete and maintained for compatibility with legacy. User is
+  *      invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
+  *      code compactness, code size and improved heap usage.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start DMA2D CLUT Loading with interrupt enabled.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @note API obsolete and maintained for compatibility with legacy. User is
+  *      invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
+  *      from code compactness, code size and improved heap usage.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the background */
+    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+    /* Enable the CLUT loading for the foreground */
+    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA2D CLUT loading.
+  * @param  hdma2d  Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                  the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart;
+  const __IO uint32_t *reg =  &(hdma2d->Instance->BGPFCCR);  /* by default, point at background register */
+
+  /* Abort the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
+
+  /* If foreground CLUT loading is considered, update local variables */
+  if (LayerIdx == DMA2D_FOREGROUND_LAYER)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }
+
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the CLUT loading is aborted */
+  while ((*reg & DMA2D_BGPFCCR_START) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
+  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
+
+  /* Change the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend the DMA2D CLUT loading.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  uint32_t tickstart;
+  uint32_t loadsuspended;
+  const __IO uint32_t *reg =  &(hdma2d->Instance->BGPFCCR);  /* by default, point at background register */
+
+  /* Suspend the CLUT loading */
+  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+  /* If foreground CLUT loading is considered, update local variables */
+  if (LayerIdx == DMA2D_FOREGROUND_LAYER)
+  {
+    reg  = &(hdma2d->Instance->FGPFCCR);
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the CLUT loading is suspended */
+  /* 1st condition: Suspend Check */
+  loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+  /* 2nd condition: Not Start Check */
+  loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
+  while (loadsuspended == 0UL)
+  {
+    if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
+    {
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+      /* Change the DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+      return HAL_TIMEOUT;
+    }
+    /* 1st condition: Suspend Check */
+    loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+    /* 2nd condition: Not Start Check */
+    loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
+  }
+
+  /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+  if ((*reg & DMA2D_BGPFCCR_START) != 0U)
+  {
+    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
+  }
+  else
+  {
+    /* Make sure SUSP bit is cleared since it is meaningless
+       when no transfer is on-going */
+    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the DMA2D CLUT loading.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  /* Check the SUSP and START bits for background or foreground CLUT loading */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Background CLUT loading suspension check */
+    if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+    {
+      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+      {
+        /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+        hdma2d->State = HAL_DMA2D_STATE_BUSY;
+      }
+    }
+  }
+  else
+  {
+    /* Foreground CLUT loading suspension check */
+    if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
+    {
+      if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+      {
+        /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+        hdma2d->State = HAL_DMA2D_STATE_BUSY;
+      }
+    }
+  }
+
+  /* Resume the CLUT loading */
+  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
+
+  return HAL_OK;
+}
+
+
+/**
+
+  * @brief  Polling for transfer complete or CLUT loading.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t layer_start;
+  __IO uint32_t isrflags = 0x0U;
+
+  /* Polling for DMA2D transfer */
+  if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
+    {
+      isrflags = READ_REG(hdma2d->Instance->ISR);
+      if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
+      {
+        if ((isrflags & DMA2D_FLAG_CE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+        }
+        if ((isrflags & DMA2D_FLAG_TE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+        }
+        /* Clear the transfer and configuration error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+        /* Change DMA2D state */
+        hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+
+        return HAL_ERROR;
+      }
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+          /* Change the DMA2D state */
+          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Polling for CLUT loading (foreground or background) */
+  layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
+  layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
+  if (layer_start != 0U)
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
+    {
+      isrflags = READ_REG(hdma2d->Instance->ISR);
+      if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
+      {
+        if ((isrflags & DMA2D_FLAG_CAE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+        }
+        if ((isrflags & DMA2D_FLAG_CE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+        }
+        if ((isrflags & DMA2D_FLAG_TE) != 0U)
+        {
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+        }
+        /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
+        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
+
+        /* Change DMA2D state */
+        hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hdma2d);
+
+        return HAL_ERROR;
+      }
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Update error code */
+          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
+
+          /* Change the DMA2D state */
+          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hdma2d);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Clear the transfer complete and CLUT loading flags */
+  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
+
+  /* Change DMA2D state */
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Handle DMA2D interrupt request.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL status
+  */
+void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
+{
+  uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
+  uint32_t crflags = READ_REG(hdma2d->Instance->CR);
+
+  /* Transfer Error Interrupt management ***************************************/
+  if ((isrflags & DMA2D_FLAG_TE) != 0U)
+  {
+    if ((crflags & DMA2D_IT_TE) != 0U)
+    {
+      /* Disable the transfer Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
+
+      /* Clear the transfer error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* Configuration Error Interrupt management **********************************/
+  if ((isrflags & DMA2D_FLAG_CE) != 0U)
+  {
+    if ((crflags & DMA2D_IT_CE) != 0U)
+    {
+      /* Disable the Configuration Error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
+
+      /* Clear the Configuration error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* CLUT access Error Interrupt management ***********************************/
+  if ((isrflags & DMA2D_FLAG_CAE) != 0U)
+  {
+    if ((crflags & DMA2D_IT_CAE) != 0U)
+    {
+      /* Disable the CLUT access error interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
+
+      /* Clear the CLUT access error flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferErrorCallback != NULL)
+      {
+        /* Transfer error Callback */
+        hdma2d->XferErrorCallback(hdma2d);
+      }
+    }
+  }
+  /* Transfer watermark Interrupt management **********************************/
+  if ((isrflags & DMA2D_FLAG_TW) != 0U)
+  {
+    if ((crflags & DMA2D_IT_TW) != 0U)
+    {
+      /* Disable the transfer watermark interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
+
+      /* Clear the transfer watermark flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
+
+      /* Transfer watermark Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+      hdma2d->LineEventCallback(hdma2d);
+#else
+      HAL_DMA2D_LineEventCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+    }
+  }
+  /* Transfer Complete Interrupt management ************************************/
+  if ((isrflags & DMA2D_FLAG_TC) != 0U)
+  {
+    if ((crflags & DMA2D_IT_TC) != 0U)
+    {
+      /* Disable the transfer complete interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
+
+      /* Clear the transfer complete flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      if (hdma2d->XferCpltCallback != NULL)
+      {
+        /* Transfer complete Callback */
+        hdma2d->XferCpltCallback(hdma2d);
+      }
+    }
+  }
+  /* CLUT Transfer Complete Interrupt management ******************************/
+  if ((isrflags & DMA2D_FLAG_CTC) != 0U)
+  {
+    if ((crflags & DMA2D_IT_CTC) != 0U)
+    {
+      /* Disable the CLUT transfer complete interrupt */
+      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
+
+      /* Clear the CLUT transfer complete flag */
+      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
+
+      /* Update error code */
+      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
+
+      /* Change DMA2D state */
+      hdma2d->State = HAL_DMA2D_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma2d);
+
+      /* CLUT Transfer complete Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+      hdma2d->CLUTLoadingCpltCallback(hdma2d);
+#else
+      HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+    }
+  }
+
+}
+
+/**
+  * @brief  Transfer watermark callback.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_LineEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  CLUT Transfer Complete callback.
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval None
+  */
+__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the DMA2D foreground or background layer parameters.
+      (+) Configure the DMA2D CLUT transfer.
+      (+) Configure the line watermark
+      (+) Configure the dead time value.
+      (+) Enable or disable the dead time value functionality.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DMA2D Layer according to the specified
+  *         parameters in the DMA2D_HandleTypeDef.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
+{
+  const DMA2D_LayerCfgTypeDef *pLayerCfg;
+  uint32_t regMask;
+  uint32_t regValue;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
+  if (hdma2d->Init.Mode != DMA2D_R2M)
+  {
+    assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
+    if (hdma2d->Init.Mode != DMA2D_M2M)
+    {
+      assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
+    }
+  }
+  assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
+  assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
+
+  if ((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR))
+  {
+    assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
+
+  /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
+  regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
+             (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
+  regMask  = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
+
+
+  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+  {
+    regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
+  }
+  else
+  {
+    regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
+  }
+
+  /* Configure the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write DMA2D BGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
+
+    /* DMA2D BGOR register configuration -------------------------------------*/
+    WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
+
+    /* DMA2D BGCOLR register configuration -------------------------------------*/
+    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {
+      WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
+                                                                   DMA2D_BGCOLR_RED));
+    }
+  }
+  /* Configure the foreground DMA2D layer */
+  else
+  {
+
+    if (pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
+    {
+      regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos);
+      regMask  |= DMA2D_FGPFCCR_CSS;
+    }
+
+    /* Write DMA2D FGPFCCR register */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
+
+    /* DMA2D FGOR register configuration -------------------------------------*/
+    WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
+
+    /* DMA2D FGCOLR register configuration -------------------------------------*/
+    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
+    {
+      WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
+                                                                   DMA2D_FGCOLR_RED));
+    }
+  }
+  /* Initialize the DMA2D state*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMA2D CLUT Transfer.
+  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                   the configuration information for the DMA2D.
+  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+  *                   the configuration information for the color look up table.
+  * @param  LayerIdx DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+  * @note API obsolete and maintained for compatibility with legacy. User is invited
+  *      to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
+  *      code size and improved heap usage.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA2D_LAYER(LayerIdx));
+  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
+  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
+
+  /* Process locked */
+  __HAL_LOCK(hdma2d);
+
+  /* Change DMA2D peripheral state */
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Configure the CLUT of the background DMA2D layer */
+  if (LayerIdx == DMA2D_BACKGROUND_LAYER)
+  {
+    /* Write background CLUT memory address */
+    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write background CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+  }
+  /* Configure the CLUT of the foreground DMA2D layer */
+  else
+  {
+    /* Write foreground CLUT memory address */
+    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
+
+    /* Write foreground CLUT size and CLUT color mode */
+    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+               ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+  }
+
+  /* Set the DMA2D state to Ready*/
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Configure the line watermark.
+  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @param  Line   Line Watermark configuration (maximum 16-bit long value expected).
+  * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
+  * @note   The transfer watermark interrupt is disabled once it has occurred.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
+{
+  /* Check the parameters */
+  if (Line > DMA2D_LWR_LW)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdma2d);
+
+    /* Change DMA2D peripheral state */
+    hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+    /* Sets the Line watermark configuration */
+    WRITE_REG(hdma2d->Instance->LWR, Line);
+
+    /* Enable the Line interrupt */
+    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
+
+    /* Initialize the DMA2D state*/
+    hdma2d->State = HAL_DMA2D_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma2d);
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief Enable DMA2D dead time feature.
+  * @param hdma2d DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Set DMA2D_AMTCR EN bit */
+  SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable DMA2D dead time feature.
+  * @param hdma2d DMA2D handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Clear DMA2D_AMTCR EN bit */
+  CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure dead time.
+  * @note The dead time value represents the guaranteed minimum number of cycles between
+  *       two consecutive transactions on the AHB bus.
+  * @param hdma2d DMA2D handle.
+  * @param DeadTime dead time value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdma2d);
+
+  hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+  /* Set DMA2D_AMTCR DT field */
+  MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
+
+  hdma2d->State = HAL_DMA2D_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief    Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to:
+      (+) Get the DMA2D state
+      (+) Get the DMA2D error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the DMA2D state
+  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+  *                 the configuration information for the DMA2D.
+  * @retval HAL state
+  */
+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d)
+{
+  return hdma2d->State;
+}
+
+/**
+  * @brief  Return the DMA2D error code
+  * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
+  *               the configuration information for DMA2D.
+  * @retval DMA2D Error Code
+  */
+uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d)
+{
+  return hdma2d->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA2D transfer parameters.
+  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA2D.
+  * @param  pdata      The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  Width      The width of data to be transferred from source to destination.
+  * @param  Height     The height of data to be transferred from source to destination.
+  * @retval HAL status
+  */
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+                            uint32_t Height)
+{
+  uint32_t tmp;
+  uint32_t tmp1;
+  uint32_t tmp2;
+  uint32_t tmp3;
+  uint32_t tmp4;
+
+  /* Configure DMA2D data size */
+  MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
+
+  /* Configure DMA2D destination address */
+  WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
+
+  /* Register to memory DMA2D mode selected */
+  if (hdma2d->Init.Mode == DMA2D_R2M)
+  {
+    tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
+    tmp2 = pdata & DMA2D_OCOLR_RED_1;
+    tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
+    tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
+
+    /* Prepare the value to be written to the OCOLR register according to the color mode */
+    if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
+    {
+      tmp = (tmp3 | tmp2 | tmp1 | tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
+    {
+      tmp = (tmp3 | tmp2 | tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
+    {
+      tmp2 = (tmp2 >> 19U);
+      tmp3 = (tmp3 >> 10U);
+      tmp4 = (tmp4 >> 3U);
+      tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
+    }
+    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
+    {
+      tmp1 = (tmp1 >> 31U);
+      tmp2 = (tmp2 >> 19U);
+      tmp3 = (tmp3 >> 11U);
+      tmp4 = (tmp4 >> 3U);
+      tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
+    }
+    else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
+    {
+      tmp1 = (tmp1 >> 28U);
+      tmp2 = (tmp2 >> 20U);
+      tmp3 = (tmp3 >> 12U);
+      tmp4 = (tmp4 >> 4U);
+      tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
+    }
+    /* Write to DMA2D OCOLR register */
+    WRITE_REG(hdma2d->Instance->OCOLR, tmp);
+  }
+  else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
+  {
+    WRITE_REG(hdma2d->Instance->BGMAR, pdata);
+  }
+  else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
+  {
+    /* Configure DMA2D source address */
+    WRITE_REG(hdma2d->Instance->FGMAR, pdata);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* DMA2D */
+#endif /* HAL_DMA2D_MODULE_ENABLED */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma_ex.c
new file mode 100644
index 000000000..71c10570d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dma_ex.c
@@ -0,0 +1,4740 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *          This file provides firmware functions to manage the following functionalities of the DMA extension
+  *          peripheral:
+  *           + Linked-List Initialization and De-Initialization Functions
+  *           + Linked-List I/O Operation Functions
+  *           + Linked-List Management Functions
+  *           + Data Handling, Repeated Block and Trigger Configuration Functions
+  *           + Suspend and Resume Operation Functions
+  *           + FIFO Status Function
+  *
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  @verbatim
+  ======================================================================================================================
+                                 ##### How to use this driver #####
+  ======================================================================================================================
+    [..]
+      Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as
+      linked-list (list of Node items). Each node is defined by its data structure.
+      Each node specifies a standalone DMA channel.
+      When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the
+      next linked list node will be fetched and executed. This operation is repeated until the end of the whole
+      linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked
+      to another queue node or circular where the last linked-list node is linked to any linked-list queue node.
+
+          (+) Linear linked-list:
+              The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node
+              (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another
+              transfer can be lunched.
+
+          (+) Circular linked-list:
+              The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail
+              node). When last node is executed, the DMA channel fetches the first circular node another time and repeat
+              the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is
+              required. This linked-list mode replaces the legacy circular transfers.
+
+    [..]
+      In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the
+      dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and
+      dynamic.
+
+          (+) Static linked-list:
+              The static linked-list format refers to the full linked-list node where all DMA channel parameters are
+              fetched and executed independently of the redundancy of information.
+
+          (+) Dynamic linked-list:
+              The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary
+              parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the
+              current node => No need to update it).
+
+      For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named
+      link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory
+      then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the
+      DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is
+      circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature
+      is useful for debug purpose or asynchronously executing queue nodes.
+
+    [..]
+      Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance
+      integrated in devices. These configuration can be :
+
+          (+) Repeated block configuration :
+              If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2
+              dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block
+              transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can
+              jump after at burst and block level. The jump length is a programmable parameter defined by DMA user.
+               (++) Jump at burst level :
+                    The DMA channel keep an empty area, between each 2 consecutive bursts transmitted.
+               (++) Jump at block level :
+                    The DMA channel keep an empty area, between each 2 consecutive blocks transmitted.
+
+          (+) Trigger :
+              The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware
+              triggers. Trigger condition can be applied at :
+               (++) Single/Burst level :
+                    Each single/burst data transmission is conditioned by a signal trigger hit.
+               (++) Block level :
+                    Each block data transmission is conditioned by a signal trigger hit.
+               (++) Repeated block level :
+                    Each repeated block data transmission is conditioned by a signal trigger hit.
+               (++) Node level :
+                    Each node execution is conditioned by a signal trigger hit.
+              The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before
+              executing the current transfer.
+
+          (+) Data handling :
+              The data handling feature is a FIFO capability that can be :
+                (++) Padding pattern :
+                     Padding selected pattern (zero padding or sign extension) when the source data width is smaller
+                     than the destination data width at single level.
+                (++) Truncation :
+                     Truncate section from the source data single when the source data width is bigger than the
+                     destination data width.
+                (++) Pack/Unpack :
+                     Pack a set of data when source data width is smaller than the destination data width.
+                     Unpack a set of data when source data width is bigger than the destination data width.
+                (++) Exchange :
+                     Exchange data at byte, half-word and word on the destination and at byte level on the source.
+
+    [..]
+      Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time
+      application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete
+      the current ongoing single/burst then it stops.
+      When the DMA channel is suspended, the current transfer can be resumed instantly.
+
+    [..]
+      The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output)
+      FIFO level.
+
+    *** Linked-List Initialization and De-Initialization operation ***
+    ==================================================================
+    [..]
+      Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the
+      remaining transfer parameters are defined by linked-list nodes.
+
+          (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields.
+              When called, the DMA channel will be ready to execute linked-list queues.
+
+          (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode.
+              When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer.
+
+    *** Linked-List I/O Operation ***
+    =================================
+    [..]
+          (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of
+              linked-list queue base address and offset in polling mode (Blocking mode).
+
+          (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of
+              linked-list queue base address and offset in interrupt mode (Non-blocking mode).
+
+    *** Linked-List Management ***
+    ==============================
+    [..]
+      The linked-list management is a software processing independently of DMA channel hardware. It allows to reset,
+      build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA
+      channel transfers in linked-list mode.
+      Linked-list APIs and types are adapted to reduce memory footprint.
+
+    *** Linked-list nodes building ***
+    [..]
+      At node level, the operations that can be done are building a new linked-list node or get a linked-list node
+      information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing
+      capability. The linear addressing nodes contains the information of all DMA channel features except the 2
+      dimension addressing features and the 2 dimensions addressing nodes contain the information of all available
+      features.
+
+          (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters.
+              Build operation allow to convert the specified parameter in values known by the DMA channel and place them
+              in memory.
+              Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the
+              link access port can access to the specified SRAM.
+              (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte
+              addressable space.
+
+          (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node.
+              This API can be used when need to change few parameter to build new node.
+
+    *** Inserting nodes to linked-list queue ***
+    [..]
+      In order to build a sequence of DMA transaction with different configuration, we need to insert built node at
+      linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the
+      full flexibility of ordering nodes or extend the sequence of queue transactions.
+
+          (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue
+              according to selecting previous node. When calling this API with previous node parameter is NULL, the
+              inserted node will be placed at the head of the linked-list queue.
+              (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
+              (++) This API must be called for static queues format.
+              (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of
+                   footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail()
+                   instead).
+
+          (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head
+              node will not be overwritten but will be the second queue node.
+              (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
+              (++) This API must be called for static queues format.
+
+          (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail
+              node will not be overwritten but will be the penultimate queue node.
+              (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
+              (++) This API must be called for static queues format.
+
+    *** Removing nodes from linked-list queue ***
+    [..]
+      There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA
+      transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node
+      can be reused for another queue or to be added to the same queue without need to rebuild it in next step.
+
+          (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according
+              to selected node.
+              (++) This API must be called for static queues format.
+              (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of
+                   footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail()
+                   instead).
+
+          (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue.
+              (++) This API must be called for static queues format.
+
+          (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue.
+              (++) This API must be called for static queues format.
+
+    *** Replacing nodes on linked-list queue ***
+    [..]
+      There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA
+      transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be
+      replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused
+      for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot
+      be reused except when remove it or replaced in next step.
+
+          (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according
+              to selected node.
+              (++) This API must be called for static queues format.
+              (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of
+                   footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or
+                   HAL_DMAEx_List_ReplaceNode_Tail() instead).
+
+          (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue.
+              (++) This API must be called for static queues format.
+
+          (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue.
+              (++) This API must be called for static queues format.
+
+    *** Reset linked-list queue ***
+    [..]
+      After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be
+      unlinked (NOT DELETED) and reused on another queue.
+
+          (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes.
+              (++) This API must be called for ready state queues.
+              (++) This API must be called for static queues format.
+
+    *** Inserting linked-list queue ***
+    [..]
+      To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for
+      action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and
+      a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where
+      the management of linked-list at queue granularity is needed.
+
+          (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue
+              according to selecting previous node.
+              (++) This API must be called for static queues format.
+              (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of
+                   destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or
+                   HAL_DMAEx_List_InsertQ_Tail() instead).
+
+          (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list
+              destination queue.
+              (++) This API must be called for static queues format.
+
+          (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list
+              destination queue.
+              (++) This API must be called for static queues format.
+
+    *** Circularizing linked-list queue ***
+    [..]
+      In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues.
+      Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node
+      is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be
+      executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed
+      once and all remaining nodes are executed in an infinite loop.
+
+          (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first
+              circular node selected.
+              (++) This API must be called for static queues format.
+              (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of
+                   footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead).
+
+          (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node
+              with first queue node.
+              (++) This API must be called for static queues format.
+
+          (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration.
+              (++) This API must be called for static queues format.
+
+
+    *** Converting linked-list queue ***
+    [..]
+      To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue
+      to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are
+      optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes
+      parameters instead of the whole node.
+
+          (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format.
+              (++) This API must be called for ready state queues.
+              (++) This API must be called for static queues format.
+              (++) This API must be called as the last API before starting the DMA channel in linked-list mode.
+
+          (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format.
+              (++) This API must be called for ready state queues.
+              (++) This API must be called for dynamic queues format.
+              (++) This API must be called as the first API after the full execution of linked-list queue when the
+                   execution mode is linear (not circular) if it is dynamic and a linked-list queue management is
+                   needed.
+              (++) This API must be called as the first API after the aborting the execution of the current linked-list
+                   queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue
+                   management is needed.
+
+    [..]
+      When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is
+      recommended to duplicate the last circular node in order to ensure the full optimization when calling
+      HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce
+      4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per
+      node execution.
+
+
+    *** Linking linked-list queue to DMA channel ***
+    [..]
+      In order to have the possibility of the creation of an infinity queues (limited by available memory size), the
+      building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if
+      their size is less then available memory at startup time, then linking each time when needed a linked-list queue
+      to an idle DMA channel.
+
+          (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel.
+              (++) This API supports the two format of linked-list (Static and dynamic).
+              (++) This API must be called for ready state queues and DMA channels.
+
+          (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel.
+              (++) This API supports the two format of linked-list (Static and dynamic).
+              (++) This API must be called for ready state queues and DMA channels.
+
+    *** User sequence ***
+    [..]
+      To use cleanly the DMA linked-list library, ensure to apply the following call sequences :
+
+          (+) Linear transfer :
+              Linked-list queue building
+              (++) HAL_DMAEx_List_BuildNode()
+              (++) HAL_DMAEx_List_InsertNode_Tail()
+                              .
+                              .
+                              .
+              (++) HAL_DMAEx_List_BuildNode()
+              (++) HAL_DMAEx_List_InsertNode_Tail()
+              (++) HAL_DMAEx_List_ConvertQToDynamic()
+              Linked-list queue execution
+              (++) HAL_DMAEx_List_Init()
+              (++) HAL_DMAEx_List_LinkQ()
+              (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT()
+              (++) HAL_DMAEx_List_UnLinkQ()
+              (++) HAL_DMAEx_List_DeInit()
+
+          (+) Circular transfer :
+              Linked-list queue building
+              (++) HAL_DMAEx_List_BuildNode()
+              (++) HAL_DMAEx_List_InsertNode_Tail()
+                              .
+                              .
+                              .
+              (++) HAL_DMAEx_List_BuildNode()
+              (++) HAL_DMAEx_List_InsertNode_Tail()
+              (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode()
+              (++) HAL_DMAEx_List_ConvertQToDynamic()
+              Linked-list queue execution
+              (++) HAL_DMAEx_List_Init()
+              (++) HAL_DMAEx_List_LinkQ()
+              (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT()
+              (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT()
+              (++) HAL_DMAEx_List_UnLinkQ()
+              (++) HAL_DMAEx_List_DeInit()
+
+
+    *** Data Handling ***
+    =====================
+    [..]
+      In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to
+      FIFO capabilities titled data handling.
+                (++) Padding pattern
+                     Padding selected pattern (zero padding or sign extension) when the source data width is smaller
+                     than the destination data width at single level.
+                     Zero padding       (Source : 0xABAB ------> Destination : 0xABAB0000)
+                     Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA)
+                                        (Source : 0xFABA ------> Destination : 0xFFFFFABA)
+                (++) Truncation :
+                     Truncate section from the source data single when the source data width is bigger than the
+                     destination data width.
+                     Left truncation  (Source : 0xABABCDCD ------> Destination : 0xCDCD)
+                     Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB)
+                (++) Pack/Unpack :
+                     Pack a set of data when source data width is smaller than the destination data width.
+                     Unpack a set of data when source data width is bigger than the destination data width.
+                     Pack   (Source : 0xAB, 0xCD ------> Destination : 0xABCD)
+                     UnPack (Source : 0xABCD     ------> Destination : 0xAB, 0xCD)
+                (++) Exchange :
+                     Exchange data at byte and half-word on the destination and at byte level on the source.
+                     Considering source and destination are both word type. Exchange operation can be as follows.
+                     In examples below, one exchange setting is enabled at a time.
+                     Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234)
+                     Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD)
+                     Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12)
+                     In addition, in case of double-word, Exchange data at word level on the destination is also
+                     available.
+                     Considering source and destination are both double-word type.
+                     word exchange only (Source : 0xAB12CD34EF567890 ------> Destination : 0xEF567890AB12CD34)
+
+          (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained
+              can be combined according to application needs.
+              (++) This API is complementary of normal transfers.
+              (++) This API must not be called for linked-list transfers as data handling information are configured at
+                   node level.
+
+    *** User sequence ***
+    [..]
+      To configure cleanly the DMA channel data handling, ensure to apply the following call sequence :
+
+          (+) Linear transfer :
+              (++) HAL_DMA_Init()
+              (++) HAL_DMAEx_ConfigDataHandling()
+              (++) HAL_DMA_Start()
+
+    *** Repeated Block ***
+    ======================
+    [..]
+      When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for
+      scattering / gathering data.
+                (++) Gather data
+                     Source            Destination
+                     0xAA              0xAA
+                     0xBB              0xAA
+                     0xAA      ==>     0xAA
+                     0xCC
+                     0xAA
+                (++) Scatter data
+                     Source            Destination
+                     0xAA              0xAA
+                     0xAA              0xBB
+                     0xAA      ==>     0xAA
+                                       0xBB
+                                       0xAA
+
+          (+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and
+              incrementing or decrementing on source and destination can be combined to have the need application
+              behavior.
+              (++) This API is complementary of normal transfers.
+              (++) This API must not be called for linked-list transfers as repeated block information are configured at
+                   node level.
+              (++) This API must be called only for DMA channel that supports repeated block feature.
+
+    *** User sequence ***
+    [..]
+      To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence :
+
+          (+) Linear transfer :
+              (++) HAL_DMA_Init()
+              (++) HAL_DMAEx_ConfigRepeatBlock()
+              (++) HAL_DMA_Start()
+
+    *** Trigger Configuration ***
+    =============================
+    [..]
+      When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can
+      do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the
+      DMA transfers.
+      To setup a trigger transfers, three DMA channel parameters are needed:
+
+          (+) Trigger mode
+              This parameter specifies the trig level.
+               (++) Block level
+               (++) Repeated block level
+               (++) Node level
+               (++) Single / Burst level
+
+          (+) Trigger polarity
+              This parameter specifies the DMA trigger sensitivity (Rising or falling).
+
+          (+) Trigger selection
+              This parameter specifies the DMA trigger hardware signal.
+
+          (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature.
+              (++) This API is complementary to normal transfers APIs.
+              (++) This API must not be called for linked-list transfers as trigger information are configured at
+                   node level.
+
+    *** User sequence ***
+    [..]
+      To configure cleanly the DMA channel trigger, ensure to apply the following call sequence :
+          (+) Linear transfer :
+              (++) HAL_DMA_Init()
+              (++) HAL_DMAEx_ConfigTrigger()
+              (++) HAL_DMA_Start()
+
+    *** Suspend and resume operation ***
+    ====================================
+    [..]
+      There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more
+      priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and
+      interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed.
+
+          (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode).
+
+          (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking
+              mode).
+
+          (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution.
+
+    *** FIFO status ***
+    ===================
+    [..]
+      In several cases, the information of FIFO level is useful to inform at application level how to process remaining
+      data. When not empty, the DMA channel FIFO cannot be flashed only by reset.
+
+          (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO).
+
+    @endverbatim
+  **********************************************************************************************************************
+  */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -----------------------------------------------------------------------------------------------------*/
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/* Private Constants -------------------------------------------------------------------------------------------------*/
+/* Private macros ----------------------------------------------------------------------------------------------------*/
+/* Private function prototypes ---------------------------------------------------------------------------------------*/
+static void DMA_List_Init(DMA_HandleTypeDef const *const hdma);
+static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+                               DMA_NodeTypeDef *const pNode);
+static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+                                   DMA_NodeTypeDef const *const pNode);
+static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
+                                                 DMA_NodeTypeDef const *const pNode2,
+                                                 DMA_NodeTypeDef const *const pNode3);
+static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
+                                         DMA_NodeTypeDef const *const pNode2,
+                                         DMA_NodeTypeDef const *const pNode3);
+static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
+                                     uint32_t *const cllr_mask,
+                                     uint32_t *const cllr_offset);
+static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList,
+                                  DMA_NodeTypeDef const *const pNode,
+                                  DMA_NodeInQInfoTypeDef *const NodeInfo);
+static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList,
+                                     DMA_NodeInQInfoTypeDef const *const NodeInfo);
+static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode,
+                              DMA_NodeTypeDef *const pDestNode);
+static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr,
+                                          uint32_t CurrentNodeAddr,
+                                          uint32_t RegisterNumber);
+static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr,
+                                         uint32_t CurrentNodeAddr,
+                                         uint32_t RegisterNumber);
+static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+                                                 uint32_t LastNode_IsCircular);
+static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+                                                uint32_t operation);
+static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode,
+                                uint32_t RegisterIdx,
+                                uint32_t RegisterNumber,
+                                uint32_t Format);
+static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode,
+                                       uint32_t FirstUnusedField);
+static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList);
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim
+  ======================================================================================================================
+                 ##### Linked-List Initialization and De-Initialization Functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode.
+    [..]
+      (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as
+          described in reference manual.
+      (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA channel in linked-list mode according to the specified parameters in the
+  *         DMA_InitLinkedListTypeDef and create the associated handle.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma)
+{
+  /* Get tick number */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the DMA channel handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority));
+  assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode));
+  assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode));
+  assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode));
+  /* Check DMA channel instance */
+  if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
+  {
+    assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort));
+  }
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hdma);
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Check if the DMA channel is effectively disabled */
+  while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Initialize the DMA channel registers */
+  DMA_List_Init(hdma);
+
+  /* Update DMA channel operation mode */
+  hdma->Mode = hdma->InitLinkedList.LinkedListMode;
+
+  /* Update the DMA channel error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Update the DMA channel state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the DMA channel when it is configured in linked-list mode.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
+{
+
+  /* Get DMA instance */
+  DMA_TypeDef *p_dma_instance;
+
+  /* Get tick number */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+
+  /* Get DMA instance */
+  p_dma_instance = GET_DMA_INSTANCE(hdma);
+
+  /* Disable the selected DMA Channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Check if the DMA channel is effectively disabled */
+  while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Reset DMA Channel registers */
+  hdma->Instance->CCR   = 0U;
+  hdma->Instance->CLBAR = 0U;
+  hdma->Instance->CTR1  = 0U;
+  hdma->Instance->CTR2  = 0U;
+  hdma->Instance->CBR1  = 0U;
+  hdma->Instance->CSAR  = 0U;
+  hdma->Instance->CDAR  = 0U;
+  hdma->Instance->CLLR  = 0U;
+
+  /* Reset 2D Addressing registers */
+  if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+  {
+    hdma->Instance->CTR3 = 0U;
+    hdma->Instance->CBR2 = 0U;
+  }
+
+
+  /* Clear privilege attribute */
+  CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
+
+
+#if defined (CPU_IN_SECURE_STATE)
+  /* Clear secure attribute */
+  CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
+#endif /* CPU_IN_SECURE_STATE */
+
+  /* Clear all flags */
+  __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
+                              DMA_FLAG_TO));
+
+  /* Clean all callbacks */
+  hdma->XferCpltCallback     = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferErrorCallback    = NULL;
+  hdma->XferAbortCallback    = NULL;
+  hdma->XferSuspendCallback  = NULL;
+
+  /* Check the linked-list queue */
+  if (hdma->LinkedListQueue != NULL)
+  {
+    /* Update the queue state and error code */
+    hdma->LinkedListQueue->State     = HAL_DMA_QUEUE_STATE_READY;
+    hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+    /* Clean DMA queue */
+    hdma->LinkedListQueue = NULL;
+  }
+
+  /* Clean DMA parent */
+  if (hdma->Parent != NULL)
+  {
+    hdma->Parent = NULL;
+  }
+
+  /* Update DMA channel operation mode */
+  hdma->Mode = DMA_NORMAL;
+
+  /* Update the DMA channel error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Update the DMA channel state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Exported_Functions_Group2
+  *
+@verbatim
+  ======================================================================================================================
+                         ##### Linked-List IO Operation Functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to :
+      (+) Configure to start DMA transfer in linked-list mode.
+
+    [..]
+      (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking
+          mode).
+      (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode
+          (Non-blocking mode).
+              (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting
+                   transfer otherwise a HAL_ERROR will be returned.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA channel transfer in linked-list mode (Blocking mode).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma)
+{
+  HAL_DMA_StateTypeDef dma_state;
+  uint32_t ccr_value;
+  uint32_t cllr_mask;
+
+  /* Check the DMA peripheral handle and the linked-list queue parameters */
+  if ((hdma == NULL) || (hdma->LinkedListQueue == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  dma_state = hdma->State;
+  ccr_value = hdma->Instance->CCR & DMA_CCR_LSM;
+  if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U)))
+  {
+    /* Check DMA channel state is ready */
+    if (hdma->State == HAL_DMA_STATE_READY)
+    {
+      /* Process locked */
+      __HAL_LOCK(hdma);
+
+      /* Update the DMA channel and the queue states */
+      hdma->State                  = HAL_DMA_STATE_BUSY;
+      hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+      /* Update the DMA channel and the queue error codes */
+      hdma->ErrorCode                  = HAL_DMA_ERROR_NONE;
+      hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+      /* Get CLLR register mask and offset */
+      DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL);
+
+      /* Update DMA registers for linked-list transfer */
+      hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA);
+      hdma->Instance->CLLR  = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask;
+    }
+
+    /* Enable DMA channel */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma)
+{
+  HAL_DMA_StateTypeDef dma_state;
+  uint32_t ccr_value;
+  uint32_t cllr_mask;
+
+  /* Check the DMA peripheral handle and the linked-list queue parameters */
+  if ((hdma == NULL) || (hdma->LinkedListQueue == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  dma_state = hdma->State;
+  ccr_value = hdma->Instance->CCR & DMA_CCR_LSM;
+  if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U)))
+  {
+    /* Check DMA channel state is ready */
+    if (hdma->State == HAL_DMA_STATE_READY)
+    {
+      /* Process locked */
+      __HAL_LOCK(hdma);
+
+      /* Update the DMA channel and the queue states */
+      hdma->State                  = HAL_DMA_STATE_BUSY;
+      hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+      /* Update the DMA channel and the queue error codes */
+      hdma->ErrorCode                  = HAL_DMA_ERROR_NONE;
+      hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+      /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
+
+      /* Check half transfer complete callback */
+      if (hdma->XferHalfCpltCallback != NULL)
+      {
+        /* If half transfer complete callback is set, enable the corresponding IT */
+        __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+      }
+
+      /* Check suspend callback */
+      if (hdma->XferSuspendCallback != NULL)
+      {
+        /* If transfer suspend callback is set, enable the corresponding IT */
+        __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
+      }
+
+      /* Get CLLR register mask and offset */
+      DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL);
+
+      /* Update DMA registers for linked-list transfer */
+      hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA);
+      hdma->Instance->CLLR  = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask;
+    }
+
+    /* Enable DMA channel */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Change the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Exported_Functions_Group3
+  *
+@verbatim
+  ======================================================================================================================
+                         ##### Linked-List Management Functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to :
+      (+) Build linked-list node.
+      (+) Get linked-list node configuration.
+      (+) Insert node to linked-list queue in any queue position.
+      (+) Remove any node from linked-list queue.
+      (+) Replace any node from linked-list queue.
+      (+) Reset linked-list queue.
+      (+) Insert linked-list queue in any queue position.
+      (+) Set circular mode configuration to linked-list queue.
+      (+) Clear circular mode configuration from linked-list queue.
+      (+) Convert static linked-list queue to dynamic format.
+      (+) Convert dynamic linked-list queue to static format.
+      (+) Link linked-list queue to DMA channel.
+      (+) Unlink linked-list queue from DMA channel.
+
+    [..]
+      (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node.
+          Node type can be :
+              (++) 2 dimensions addressing node.
+              (++) Linear addressing node.
+
+      (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node.
+
+      (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue
+          according to selected position.
+
+      (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built
+          linked-list node to the head (respectively the tail) of static linked-list queue.
+
+      (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static
+          linked-list queue.
+
+      (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head
+          (respectively the tail) built linked-list node from static linked-list queue.
+
+      (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static
+          linked-list queue.
+
+      (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the
+          head (respectively the tail) built linked-list node of static linked-list queue.
+
+      (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list
+          nodes.
+
+      (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list
+          destination queue according to selected position.
+
+      (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static
+          linked-list source queue to the head (respectively the tail) of static linked-list destination queue.
+
+      (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to
+          the selected first circular node.
+
+      (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the
+          first static linked-list queue node.
+
+      (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from
+          any first circular node position.
+
+      (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic
+          format. (Optimized queue execution)
+
+      (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static
+          format. (Not optimized queue execution)
+
+      (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to
+          be executed.
+
+      (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA
+          channel when execution is completed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef.
+  * @param  pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+  *                       specified DMA linked-list Node.
+  * @param  pNode       : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+  *                       configurations.
+  * @note   The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte
+  *         addressable space.
+  * @note   Warning if AXI port is selected with HPDMA, the maximum source (and destination) length should be less
+  *         than 17. Otherwise, an error will be returned and no initialization performed.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+                                           DMA_NodeTypeDef *const pNode)
+{
+  /* Check the node configuration and physical node parameters */
+  if ((pNodeConfig == NULL) || (pNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check node type parameter */
+  assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType));
+
+  /* Check DMA channel basic transfer parameters */
+  assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc));
+  assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc));
+  assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth));
+  assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth));
+  assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment));
+  assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request));
+  assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction));
+  assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode));
+  assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest));
+  assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode));
+
+  /* Check DMA channel parameters */
+  if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U)
+  {
+    assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength));
+    assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength));
+    assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange));
+    assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort));
+  }
+
+  /* Check DMA channel trigger parameters */
+  assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity));
+  if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED)
+  {
+    assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode));
+    assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection));
+  }
+
+  /* Check DMA channel repeated block parameters */
+  if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+  {
+    assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount));
+    assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset));
+    assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset));
+    assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset));
+    assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset));
+  }
+
+  /* Check DMA channel security and privilege attributes parameters */
+#if defined (CPU_IN_SECURE_STATE)
+  assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure));
+  assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure));
+#endif /* CPU_IN_SECURE_STATE */
+
+  if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_HPDMA) == DMA_CHANNEL_TYPE_HPDMA)
+  {
+    if (((pNodeConfig->Init.TransferAllocatedPort & DMA_CTR1_SAP) == DMA_SRC_ALLOCATED_PORT0) &&
+        (pNodeConfig->Init.SrcBurstLength > 16U))
+    {
+      return HAL_ERROR;
+    }
+    if (((pNodeConfig->Init.TransferAllocatedPort & DMA_CTR1_DAP) == DMA_DEST_ALLOCATED_PORT0) &&
+        (pNodeConfig->Init.DestBurstLength > 16U))
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /* Build the DMA channel node */
+  DMA_List_BuildNode(pNodeConfig, pNode);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get a DMA channel node configuration.
+  * @param  pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+  *                       specified DMA linked-list Node.
+  * @param  pNode       : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+  *                       configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+                                               DMA_NodeTypeDef const *const pNode)
+{
+  /* Check the node configuration and physical node parameters */
+  if ((pNodeConfig == NULL) || (pNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the DMA channel node configuration */
+  DMA_List_GetNodeConfig(pNodeConfig, pNode);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Insert new node in any queue position of linked-list queue according to selecting previous node.
+  * @param  pQList    : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
+  *                     configurations.
+  * @param  pNewNode  : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+  *                     configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
+                                            DMA_NodeTypeDef *const pPrevNode,
+                                            DMA_NodeTypeDef *const pNewNode)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue and the new node parameters */
+  if ((pQList == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+  /* Empty queue */
+  if (pQList->Head == NULL)
+  {
+    /* Add only new node to queue */
+    if (pPrevNode == NULL)
+    {
+      pQList->Head       = pNewNode;
+      pQList->NodeNumber = 1U;
+    }
+    /* Add previous node then new node to queue */
+    else
+    {
+      pQList->Head                          = pPrevNode;
+      pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+      pQList->NodeNumber                    = 2U;
+    }
+  }
+  /* Not empty queue */
+  else
+  {
+    /* Add new node at the head of queue */
+    if (pPrevNode == NULL)
+    {
+      pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+      pQList->Head                         = pNewNode;
+    }
+    /* Add new node according to selected position */
+    else
+    {
+      /* Find node and get its position in selected queue */
+      node_info.cllr_offset = cllr_offset;
+      if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U)
+      {
+        /* Selected node is the last queue node */
+        if (node_info.currentnode_pos == pQList->NodeNumber)
+        {
+          /* Check if queue is circular */
+          if (pQList->FirstCircularNode != NULL)
+          {
+            pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+          }
+
+          pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+        }
+        /* Selected node is not the last queue node */
+        else
+        {
+          pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset];
+          pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+        }
+      }
+      else
+      {
+        /* Update the queue error code */
+        pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Increment queue node number */
+    pQList->NodeNumber++;
+  }
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Insert new node at the head of linked-list queue.
+  * @param  pQList    : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pNewNode  : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+  *                     configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
+                                                 DMA_NodeTypeDef *const pNewNode)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+
+  /* Check the queue and the new node parameters */
+  if ((pQList == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Empty queue */
+  if (pQList->Head == NULL)
+  {
+    pQList->Head = pNewNode;
+  }
+  /* Not empty queue */
+  else
+  {
+    /* Get CLLR register mask and offset */
+    DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+    pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+    pQList->Head                         = pNewNode;
+  }
+
+  /* Increment queue node number */
+  pQList->NodeNumber++;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Insert new node at the tail of linked-list queue.
+  * @param  pQList    : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pNewNode  : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+  *                     configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
+                                                 DMA_NodeTypeDef *const pNewNode)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue and the new node parameters */
+  if ((pQList == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Empty queue */
+  if (pQList->Head == NULL)
+  {
+    pQList->Head = pNewNode;
+  }
+  /* Not empty queue */
+  else
+  {
+    /* Get CLLR register mask and offset */
+    DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+    /* Find node and get its position in selected queue */
+    node_info.cllr_offset = cllr_offset;
+    (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+    /* Check if queue is circular */
+    if (pQList->FirstCircularNode != NULL)
+    {
+      pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+    }
+
+    ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+      ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+  }
+
+  /* Increment queue node number */
+  pQList->NodeNumber++;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Remove node from any linked-list queue position.
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pNode  : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
+  *                  configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
+                                            DMA_NodeTypeDef *const pNode)
+{
+  uint32_t previousnode_addr;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue and the node parameters */
+  if ((pQList == NULL) || (pNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset);
+
+  /* Find node and get its position in selected queue */
+  node_info.cllr_offset = cllr_offset;
+  if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U)
+  {
+    /* Removed node is the head node */
+    if (node_info.currentnode_pos == 1U)
+    {
+      /* Check if first circular node queue is the first node */
+      if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
+      {
+        /* Find last queue node */
+        (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+        /* Clear last node link */
+        ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+        /* Clear first circular node */
+        pQList->FirstCircularNode = NULL;
+      }
+
+      /* Update the queue head node */
+      pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) +
+                                         (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA));
+      /* Unlink node to be removed */
+      pNode->LinkRegisters[cllr_offset] = 0U;
+    }
+    /* Removed node is the last node */
+    else if (node_info.currentnode_pos == pQList->NodeNumber)
+    {
+      /* Clear CLLR for previous node */
+      ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+      /* Clear CLLR for last node */
+      ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+      /* Clear first circular node */
+      pQList->FirstCircularNode = NULL;
+    }
+    /* Removed node is in the middle */
+    else
+    {
+      /* Store previous node address to be updated later */
+      previousnode_addr = node_info.previousnode_addr;
+
+      /* Check if first circular node queue is the current node */
+      if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
+      {
+        /* Find last queue node */
+        (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+        /* Clear last node link */
+        ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+        /* Clear first circular node */
+        pQList->FirstCircularNode = NULL;
+      }
+
+      /* Link previous node */
+      ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset];
+
+      /* Unlink node to be removed */
+      pNode->LinkRegisters[cllr_offset] = 0U;
+    }
+
+    /* Decrement node number */
+    pQList->NodeNumber--;
+  }
+  else
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+    return HAL_ERROR;
+  }
+
+  /* Check if queue is empty */
+  if (pQList->NodeNumber == 0U)
+  {
+    /* Clean empty queue parameter */
+    DMA_List_CleanQueue(pQList);
+  }
+  else
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+    /* Update the queue state */
+    pQList->State = HAL_DMA_QUEUE_STATE_READY;
+  }
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Remove the head node from linked-list queue.
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList)
+{
+  uint32_t cllr_offset;
+  uint32_t current_addr;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue parameter */
+  if (pQList == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+  /* Queue contains only one node */
+  if (pQList->NodeNumber == 1U)
+  {
+    pQList->Head->LinkRegisters[cllr_offset] = 0U;
+    pQList->FirstCircularNode = 0U;
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+  }
+  /* Queue contains more then one node */
+  else
+  {
+    /* Check if first circular node queue is the first node */
+    if (pQList->FirstCircularNode == pQList->Head)
+    {
+      /* Find last queue node */
+      node_info.cllr_offset = cllr_offset;
+      (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+      /* Clear last node link */
+      ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+      /* Clear first circular node */
+      pQList->FirstCircularNode = NULL;
+    }
+
+    current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+    pQList->Head->LinkRegisters[cllr_offset] = 0U;
+    pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)));
+  }
+
+  /* Decrement node number */
+  pQList->NodeNumber--;
+
+  /* Check if queue is empty */
+  if (pQList->NodeNumber == 0U)
+  {
+    /* Clean empty queue parameter */
+    DMA_List_CleanQueue(pQList);
+  }
+  else
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+    /* Update the queue state */
+    pQList->State = HAL_DMA_QUEUE_STATE_READY;
+  }
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Remove the tail node from linked-list queue.
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList)
+{
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue parameter */
+  if (pQList == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+  /* Queue contains only one node */
+  if (pQList->NodeNumber == 1U)
+  {
+    pQList->Head->LinkRegisters[cllr_offset] = 0U;
+    pQList->FirstCircularNode = 0U;
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+  }
+  /* Queue contains more then one node */
+  else
+  {
+    /* Find node and get its position in selected queue */
+    node_info.cllr_offset = cllr_offset;
+    (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+    /* Clear CLLR for previous node */
+    ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+    /* Clear CLLR for last node */
+    ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+    /* Clear first circular node */
+    pQList->FirstCircularNode = NULL;
+  }
+
+  /* Decrement node number */
+  pQList->NodeNumber--;
+
+  /* Check if queue is empty */
+  if (pQList->NodeNumber == 0U)
+  {
+    /* Clean empty queue parameter */
+    DMA_List_CleanQueue(pQList);
+  }
+  else
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+    /* Update the queue state */
+    pQList->State = HAL_DMA_QUEUE_STATE_READY;
+  }
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Replace node in linked-list queue.
+  * @param  pQList   : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers
+  *                    configurations.
+  * @param  pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+  *                    configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
+                                             DMA_NodeTypeDef *const pOldNode,
+                                             DMA_NodeTypeDef *const pNewNode)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue and the nodes parameters */
+  if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+  /* Find node and get its position in selected queue */
+  node_info.cllr_offset = cllr_offset;
+  if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U)
+  {
+    /* Replaced node is the head node */
+    if (node_info.currentnode_pos == 1U)
+    {
+      pNewNode->LinkRegisters[cllr_offset] =
+        ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset];
+      pQList->Head = pNewNode;
+      ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+      /* Check if first circular node queue is the first node */
+      if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
+      {
+        /* Find last queue node */
+        (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+        /* Clear last node link */
+        ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+          ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+        /* Set new node as first circular node */
+        pQList->FirstCircularNode = pNewNode;
+      }
+    }
+    /* Replaced node is the last */
+    else if (node_info.currentnode_pos == pQList->NodeNumber)
+    {
+      ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
+        ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+      ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+      /* Check if first circular node queue is the last node */
+      if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
+      {
+        /* Link first circular node to new node */
+        pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+        /* Set new node as first circular node */
+        pQList->FirstCircularNode = pNewNode;
+      }
+      /* Check if first circular node queue is not the last node */
+      else if (pQList->FirstCircularNode != NULL)
+      {
+        /* Link first circular node to new node */
+        pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+      }
+      else
+      {
+        /* Prevent MISRA-C2012-Rule-15.7 */
+      }
+    }
+    /* Replaced node is in the middle */
+    else
+    {
+      ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
+        ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+      pNewNode->LinkRegisters[cllr_offset] =
+        ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset];
+      ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+      /* Check if first circular node queue is the current node */
+      if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
+      {
+        /* Find last node and get its position in selected queue */
+        (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+        /* Link last queue node to new node */
+        ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+          ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+        /* Set new node as first circular node */
+        pQList->FirstCircularNode = pNewNode;
+      }
+    }
+  }
+  else
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Replace the head node of linked-list queue.
+  * @param  pQList   : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+  *                    configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
+                                                  DMA_NodeTypeDef *const pNewNode)
+{
+  uint32_t cllr_offset;
+  uint32_t cllr_mask;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue and the new node parameters */
+  if ((pQList == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+  /* Check if first circular node queue is the first node */
+  if (pQList->FirstCircularNode == pQList->Head)
+  {
+    /* Find last queue node */
+    node_info.cllr_offset = cllr_offset;
+    (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+    /* Clear last node link */
+    ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+      ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+    /* Set new node as first circular node */
+    pQList->FirstCircularNode = pNewNode;
+  }
+
+  /* Replace head node */
+  pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset];
+  pQList->Head->LinkRegisters[cllr_offset] = 0U;
+  pQList->Head = pNewNode;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Replace the tail node of linked-list queue.
+  * @param  pQList   : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
+  *                    configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
+                                                  DMA_NodeTypeDef *const pNewNode)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue and the new node parameters */
+  if ((pQList == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
+
+  /* Find last node and get its position in selected queue */
+  node_info.cllr_offset = cllr_offset;
+  (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+  /* Link previous node to new node */
+  ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
+    ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+  /* Clear CLLR for current node */
+  ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+  /* Check if first circular node queue is the last node */
+  if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
+  {
+    /* Link first circular node to new node */
+    pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
+
+    /* Set new node as first circular node */
+    pQList->FirstCircularNode = pNewNode;
+  }
+  /* Check if first circular node queue is not the last node */
+  else if (pQList->FirstCircularNode != NULL)
+  {
+    /* Link first circular node to new node */
+    pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+  }
+  else
+  {
+    /* Prevent MISRA-C2012-Rule-15.7 */
+  }
+
+  /* Check if queue contains one node */
+  if (pQList->NodeNumber == 1U)
+  {
+    pQList->Head = pNewNode;
+  }
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the linked-list queue and unlink queue nodes.
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList)
+{
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue parameter */
+  if (pQList == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check queue state */
+  if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Check the queue */
+  if (pQList->Head != NULL)
+  {
+    /* Get CLLR register mask and offset */
+    DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+    /* Reset selected queue nodes */
+    node_info.cllr_offset = cllr_offset;
+    DMA_List_ResetQueueNodes(pQList, &node_info);
+  }
+
+  /* Reset head node address */
+  pQList->Head = NULL;
+
+  /* Reset node number */
+  pQList->NodeNumber = 0U;
+
+  /* Reset first circular node */
+  pQList->FirstCircularNode = NULL;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Insert a source linked-list queue to a destination linked-list queue according to selecting previous node.
+  * @param  pSrcQList  : Pointer to a DMA_QListTypeDef structure that contains source queue information.
+  * @param  pPrevNode  : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
+  *                      configurations.
+  * @param  pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
+                                         DMA_NodeTypeDef const *const pPrevNode,
+                                         DMA_QListTypeDef *const pDestQList)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef src_q_node_info;
+  DMA_NodeInQInfoTypeDef dest_q_node_info;
+
+  /* Check the source and destination queues and the previous node parameters */
+  if ((pSrcQList == NULL) || (pDestQList == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the source queue */
+  if (pSrcQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check the source queue type */
+  if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check the destination queue type */
+  if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check the source queue circularity */
+  if (pSrcQList->FirstCircularNode != NULL)
+  {
+    /* Update the source queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
+  {
+    /* Update the source queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    /* Update the destination queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
+  {
+    /* Update the source queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    /* Update the destination queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the source queue state */
+  pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the source queue error code */
+  pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the destination queue state */
+  pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the destination queue error code */
+  pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
+
+  /* Empty destination queue */
+  if (pDestQList->Head == NULL)
+  {
+    pDestQList->Head       = pSrcQList->Head;
+    pDestQList->NodeNumber = pSrcQList->NodeNumber;
+  }
+  /* Not empty destination queue */
+  else
+  {
+    /* Previous node is empty */
+    if (pPrevNode == NULL)
+    {
+      /* Find node and get its position in selected queue */
+      src_q_node_info.cllr_offset = cllr_offset;
+      (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+      /* Check if first circular node queue is the first node */
+      if (pDestQList->FirstCircularNode == pDestQList->Head)
+      {
+        /* Find node and get its position in selected queue */
+        dest_q_node_info.cllr_offset = cllr_offset;
+        (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
+
+        /* Link destination queue tail node to new first circular node */
+        ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+          ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+        /* Set the head node of source queue as the first circular node */
+        pDestQList->FirstCircularNode = pSrcQList->Head;
+      }
+
+      /* Link the last node of source queue to the fist node of destination queue */
+      ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+        ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask;
+      pDestQList->Head        = pSrcQList->Head;
+      pDestQList->NodeNumber += pSrcQList->NodeNumber;
+    }
+    /* Previous node is not empty */
+    else
+    {
+      /* Find node and get its position in selected queue */
+      dest_q_node_info.cllr_offset = cllr_offset;
+      if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U)
+      {
+        /* Selected node is the last destination queue node */
+        if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber)
+        {
+          /* Link the first node of source queue to the last node of destination queue */
+          ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+            ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+          pDestQList->NodeNumber += pSrcQList->NodeNumber;
+
+          /* Check if first circular node queue is not empty */
+          if (pDestQList->FirstCircularNode != NULL)
+          {
+            /* Find node and get its position in selected queue */
+            src_q_node_info.cllr_offset = cllr_offset;
+            (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+            /* Find first circular node */
+            (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info);
+
+            /* Link last source queue node to first destination queue */
+            ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+              (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask;
+          }
+        }
+        /* Selected node is not the last destination queue node */
+        else
+        {
+          /* Link the first node of source queue to the previous node of destination queue */
+          ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+            ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+          /* Find node and get its position in selected queue */
+          src_q_node_info.cllr_offset = cllr_offset;
+          (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+          /* Link the last node of source queue to the next node of destination queue */
+          ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+            (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask;
+
+          /* Update queues counter */
+          pDestQList->NodeNumber += pSrcQList->NodeNumber;
+        }
+      }
+      else
+      {
+        /* Update the destination queue error code */
+        pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Clean the source queue variable as it is obsolete */
+  DMA_List_CleanQueue(pSrcQList);
+
+  /* Update the destination queue error code */
+  pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the destination queue state */
+  pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(src_q_node_info);
+  UNUSED(dest_q_node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Insert a source linked-list queue at the head of destination queue.
+  * @param  pSrcQList  : Pointer to a DMA_QListTypeDef structure that contains source queue information.
+  * @param  pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
+                                              DMA_QListTypeDef *const pDestQList)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef src_q_node_info;
+  DMA_NodeInQInfoTypeDef dest_q_node_info;
+
+  /* Check the source and destination queues and the previous node parameters */
+  if ((pSrcQList == NULL) || (pDestQList == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the source queue */
+  if (pSrcQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check the source queue type */
+  if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check the destination queue type */
+  if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+  {
+    /* Update the source queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    /* Update the destination queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+  {
+    /* Update the source queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    /* Update the destination queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the source queue state */
+  pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the source queue error code */
+  pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the destination queue state */
+  pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the destination queue error code */
+  pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
+
+  /* Empty destination queue */
+  if (pDestQList->Head == NULL)
+  {
+    pDestQList->Head       = pSrcQList->Head;
+    pDestQList->NodeNumber = pSrcQList->NodeNumber;
+  }
+  /* Not empty destination queue */
+  else
+  {
+    /* Find node and get its position in selected queue */
+    src_q_node_info.cllr_offset = cllr_offset;
+    (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+    /* Check if first circular node queue is the first node */
+    if (pDestQList->FirstCircularNode == pDestQList->Head)
+    {
+      /* Find node and get its position in selected queue */
+      dest_q_node_info.cllr_offset = cllr_offset;
+      (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
+
+      /* Link destination queue tail node to new first circular node */
+      ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+        ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+      /* Set the head node of source queue as the first circular node */
+      pDestQList->FirstCircularNode = pSrcQList->Head;
+    }
+
+    /* Link the last node of source queue to the fist node of destination queue */
+    ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+      ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask;
+    pDestQList->Head        = pSrcQList->Head;
+    pDestQList->NodeNumber += pSrcQList->NodeNumber;
+  }
+
+  /* Clean the source queue variable as it is obsolete */
+  DMA_List_CleanQueue(pSrcQList);
+
+  /* Update the destination queue error code */
+  pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the destination queue state */
+  pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(src_q_node_info);
+  UNUSED(dest_q_node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Insert a source linked-list queue at the tail of destination queue.
+  * @param  pSrcQList  : Pointer to a DMA_QListTypeDef structure that contains source queue information.
+  * @param  pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
+                                              DMA_QListTypeDef *const pDestQList)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef src_q_node_info;
+  DMA_NodeInQInfoTypeDef dest_q_node_info;
+
+  /* Check the source and destination queues and the previous node parameters */
+  if ((pSrcQList == NULL) || (pDestQList == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the source queue */
+  if (pSrcQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check the source queue type */
+  if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check the destination queue type */
+  if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes base addresses */
+  if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+  {
+    /* Update the source queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    /* Update the destination queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
+
+    return HAL_ERROR;
+  }
+
+  /* Check nodes types compatibility */
+  if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
+  {
+    /* Update the source queue error code */
+    pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    /* Update the destination queue error code */
+    pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the source queue state */
+  pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the source queue error code */
+  pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the destination queue state */
+  pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the destination queue error code */
+  pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
+
+  /* Empty destination queue */
+  if (pDestQList->Head == NULL)
+  {
+    pDestQList->Head       = pSrcQList->Head;
+    pDestQList->NodeNumber = pSrcQList->NodeNumber;
+  }
+  /* Not empty destination queue */
+  else
+  {
+    /* Find node and get its position in selected queue */
+    dest_q_node_info.cllr_offset = cllr_offset;
+    (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
+
+    /* Update source queue last node CLLR to link it with destination first node */
+    ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+      ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
+    pDestQList->NodeNumber += pSrcQList->NodeNumber;
+
+    /* Check if first circular node queue is not empty */
+    if (pDestQList->FirstCircularNode != NULL)
+    {
+      /* Find node and get its position in selected queue */
+      src_q_node_info.cllr_offset = cllr_offset;
+      (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
+
+      /* Find first circular node */
+      (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info);
+
+      /* Link last source queue node to first destination queue */
+      ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
+        (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask;
+    }
+  }
+
+  /* Clean the source queue variable as it is obsolete */
+  DMA_List_CleanQueue(pSrcQList);
+
+  /* Update the destination queue error code */
+  pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the destination queue state */
+  pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(src_q_node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set circular mode configuration for linked-list queue.
+  * @param  pQList             : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node
+  *                              registers configurations.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
+                                                       DMA_NodeTypeDef *const pFirstCircularNode)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue and the first circular node parameters */
+  if ((pQList == NULL) || (pFirstCircularNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue circular mode */
+  if (pQList->FirstCircularNode != NULL)
+  {
+    if (pQList->FirstCircularNode == pFirstCircularNode)
+    {
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update the queue error code */
+      pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset);
+
+  /* Find the first circular node and get its position in selected queue */
+  node_info.cllr_offset = cllr_offset;
+  if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U)
+  {
+    /* Find the last queue node and get its position in selected queue */
+    (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+    /* Set circular mode */
+    ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+      ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask;
+
+    /* Update first circular node in queue */
+    pQList->FirstCircularNode = pFirstCircularNode;
+  }
+  else
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set circular mode for linked-list queue.
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList)
+{
+  uint32_t cllr_mask;
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue parameter */
+  if (pQList == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue circular mode */
+  if (pQList->FirstCircularNode != NULL)
+  {
+    if (pQList->FirstCircularNode == pQList->Head)
+    {
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update the queue error code */
+      pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset);
+
+  /* Find the last queue node and get its position in selected queue */
+  node_info.cllr_offset = cllr_offset;
+  (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+  /* Set circular mode */
+  ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
+    ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+
+  /* Update linked-list circular state */
+  pQList->FirstCircularNode = pQList->Head;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear circular mode for linked-list queue.
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList)
+{
+  uint32_t cllr_offset;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue parameter */
+  if (pQList == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue circular mode */
+  if (pQList->FirstCircularNode == NULL)
+  {
+    return HAL_OK;
+  }
+
+  /* Check queue type */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+    return HAL_ERROR;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register offset */
+  DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+  /* Find the last queue node and get its position in selected queue */
+  node_info.cllr_offset = cllr_offset;
+  (void)DMA_List_FindNode(pQList, NULL, &node_info);
+
+  /* Clear circular mode */
+  ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
+
+  /* Update linked-list circular configuration */
+  pQList->FirstCircularNode = NULL;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  /* Prevent MISRA-C2012-Rule-2.2_b */
+  UNUSED(node_info);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Convert a linked-list queue to dynamic (Optimized DMA queue execution).
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList)
+{
+  uint32_t cllr_offset;
+  uint32_t currentnode_addr;
+  DMA_NodeTypeDef context_node;
+  DMA_NodeInQInfoTypeDef node_info;
+
+  /* Check the queue parameter */
+  if (pQList == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check if queue is dynamic */
+  if (pQList->Type == QUEUE_TYPE_DYNAMIC)
+  {
+    return HAL_OK;
+  }
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+  /* Check queue circularity */
+  if (pQList->FirstCircularNode != 0U)
+  {
+    /* Find the last queue node and get its position in selected queue */
+    node_info.cllr_offset = cllr_offset;
+    (void)DMA_List_FindNode(pQList, NULL, &node_info);
+  }
+
+  /* Set current node address */
+  currentnode_addr = (uint32_t)pQList->Head;
+
+  /* Store register value */
+  DMA_List_FillNode(pQList->Head, &context_node);
+
+  /* Convert all nodes to dyncamic (Bypass head node) */
+  for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++)
+  {
+    /* Update node address */
+    MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA));
+
+    /* Bypass the first circular node when first circular node isn't the last queue node */
+    if (((uint32_t)pQList->FirstCircularNode != 0U)                         &&
+        ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) &&
+        ((uint32_t)pQList->FirstCircularNode == currentnode_addr))
+    {
+      /* Copy first circular node to context node */
+      DMA_List_FillNode(pQList->FirstCircularNode, &context_node);
+    }
+    else
+    {
+      /* Convert current node to dynamic */
+      DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U));
+    }
+  }
+
+  /* Check if first circular node is the last node queue */
+  if (((uint32_t)pQList->FirstCircularNode != 0U) &&
+      ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr))
+  {
+    /* Update all queue nodes CLLR */
+    DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR);
+  }
+  else
+  {
+    /* Update all queue nodes CLLR */
+    DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR);
+  }
+
+  /* Set queue type */
+  pQList->Type = QUEUE_TYPE_DYNAMIC;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Convert a linked-list queue to static (Not optimized DMA queue execution).
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList)
+{
+  uint32_t cllr_offset;
+  uint32_t currentnode_addr;
+  DMA_NodeTypeDef context_node;
+
+  /* Check the queue parameter */
+  if (pQList == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the queue */
+  if (pQList->Head == NULL)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check if queue is static */
+  if (pQList->Type == QUEUE_TYPE_STATIC)
+  {
+    return HAL_OK;
+  }
+
+  /* Set current node address */
+  currentnode_addr = (uint32_t)pQList->Head;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Get CLLR register mask and offset */
+  DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
+
+  /* Set all CLLR queue nodes to their default positions */
+  DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION);
+
+  /* Convert all nodes to static (Bypass head node) */
+  for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++)
+  {
+    /* Update context node register values */
+    DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node);
+
+    /* Update node address */
+    MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA));
+
+    /* Convert current node to static */
+    DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U));
+  }
+
+  /* Set all CLLR queue nodes to their default values */
+  DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE);
+
+  /* Set queue type */
+  pQList->Type = QUEUE_TYPE_STATIC;
+
+  /* Update the queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Update the queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Link linked-list queue to a DMA channel.
+  * @param  hdma   : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                  specified DMA Channel.
+  * @param  pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
+                                       DMA_QListTypeDef *const pQList)
+{
+  HAL_DMA_StateTypeDef state;
+
+  /* Check the DMA channel handle and the queue parameters */
+  if ((hdma == NULL) || (pQList == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get DMA state */
+  state = hdma->State;
+
+  /* Check DMA channel state */
+  if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND))
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  /* Check queue state */
+  if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY)
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY;
+
+    return HAL_ERROR;
+  }
+
+  /* Check linearity compatibility */
+  if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) &&
+      ((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR))
+  {
+    /* Update the queue error code */
+    pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Check circularity compatibility */
+  if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR)
+  {
+    /* Check first circular node */
+    if (pQList->FirstCircularNode == NULL)
+    {
+      /* Update the queue error code */
+      pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Check first circular node */
+    if (pQList->FirstCircularNode != NULL)
+    {
+      /* Update the queue error code */
+      pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Register queue to DMA handle */
+  hdma->LinkedListQueue = pQList;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlink linked-list queue from a DMA channel.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma)
+{
+  HAL_DMA_StateTypeDef state;
+
+  /* Check the DMA channel parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get DMA state */
+  state = hdma->State;
+
+  /* Check DMA channel state */
+  if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND))
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  /* Clear queue information from DMA channel handle */
+  hdma->LinkedListQueue = NULL;
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Exported_Functions_Group4
+  *
+@verbatim
+  ======================================================================================================================
+             ##### Data handling, repeated block and trigger configuration functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to :
+      (+) Configure DMA channel data handling.
+      (+) Configure DMA channel repeated block.
+      (+) Configure DMA channel trigger.
+
+    [..]
+      (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling.
+              (++) GPDMA or HPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation,
+                                                  sign extension and left/right alignment.
+
+      (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers.
+
+      (+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block.
+              (++) This feature is available only for channel that supports 2 dimensions addressing capability.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the DMA channel data handling according to the specified parameters in the
+  *         DMA_DataHandlingConfTypeDef.
+  * @param  hdma                : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                               for the specified DMA Channel.
+  * @param  pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling
+  *                               configuration.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
+                                               DMA_DataHandlingConfTypeDef const *const pConfigDataHandling)
+{
+  /* Check the DMA peripheral handle and data handling parameters */
+  if ((hdma == NULL) || (pConfigDataHandling == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment));
+  assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange));
+
+  /* Check DMA channel state */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DWX | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM),
+               (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange));
+  }
+  else
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef.
+  * @param  hdma           : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
+  *                          the specified DMA Channel.
+  * @param  pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
+                                          DMA_TriggerConfTypeDef const *const pConfigTrigger)
+{
+  /* Check the DMA peripheral handle and trigger parameters */
+  if ((hdma == NULL) || (pConfigTrigger == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity));
+  assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode));
+  assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection));
+
+  /* Check DMA channel state */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM),
+               (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode |
+                (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos)));
+  }
+  else
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMA channel repeated block according to the specified parameters in the
+  *         DMA_RepeatBlockConfTypeDef.
+  * @param  hdma               : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                              for the specified DMA Channel.
+  * @param  pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block
+  *                              configuration.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
+                                              DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock)
+{
+  uint32_t tmpreg1;
+  uint32_t tmpreg2;
+
+  /* Check the DMA peripheral handle and repeated block parameters */
+  if ((hdma == NULL) || (pConfigRepeatBlock == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount));
+  assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset));
+  assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset));
+  assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset));
+  assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset));
+
+  /* Check DMA channel state */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Store repeat block count */
+    tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos);
+
+    /* Check the sign of single/burst destination address offset value */
+    if (pConfigRepeatBlock->DestAddrOffset < 0)
+    {
+      /* Store single/burst destination address offset configuration (signed case) */
+      tmpreg1 |= DMA_CBR1_DDEC;
+      tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset);
+      tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos;
+    }
+    else
+    {
+      /* Store single/burst destination address offset configuration (unsigned case) */
+      tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos);
+    }
+
+    /* Check the sign of single/burst source address offset value */
+    if (pConfigRepeatBlock->SrcAddrOffset < 0)
+    {
+      /* Store single/burst source address offset configuration (signed case) */
+      tmpreg1 |= DMA_CBR1_SDEC;
+      tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset);
+    }
+    else
+    {
+      /* Store single/burst source address offset configuration (unsigned case) */
+      tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset;
+    }
+
+    /* Write DMA Channel Transfer Register 3 (CTR3) */
+    WRITE_REG(hdma->Instance->CTR3, tmpreg2);
+
+    /* Check the sign of block destination address offset value */
+    if (pConfigRepeatBlock->BlkDestAddrOffset < 0)
+    {
+      /* Store block destination address offset configuration (signed case) */
+      tmpreg1 |= DMA_CBR1_BRDDEC;
+      tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset);
+      tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos;
+    }
+    else
+    {
+      /* Store block destination address offset configuration (unsigned case) */
+      tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos);
+    }
+
+    /* Check the sign of block source address offset value */
+    if (pConfigRepeatBlock->BlkSrcAddrOffset < 0)
+    {
+      /* Store block source address offset configuration (signed case) */
+      tmpreg1 |= DMA_CBR1_BRSDEC;
+      tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset);
+    }
+    else
+    {
+      /* Store block source address offset configuration (unsigned case) */
+      tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset;
+    }
+
+    /* Write DMA Channel block register 2 (CBR2) */
+    WRITE_REG(hdma->Instance->CBR2, tmpreg2);
+
+    /* Write DMA Channel block register 1 (CBR1) */
+    WRITE_REG(hdma->Instance->CBR1, tmpreg1);
+  }
+  else
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Exported_Functions_Group5
+  *
+@verbatim
+  ======================================================================================================================
+                         ##### Suspend and resume operation functions #####
+  ======================================================================================================================
+    [..]
+      This section provides functions allowing to :
+      (+) Suspend any ongoing DMA channel transfer.
+      (+) Resume any suspended DMA channel transfer.
+
+    [..]
+      (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking
+          mode).
+
+      (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode
+         (Non-blocking mode).
+
+      (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Suspend any ongoing DMA channel transfer in polling mode (Blocking mode).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA channel.
+  * @note   After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If
+  *         a channel is suspended while a data transfer is ongoing, the current data will be transferred and the
+  *         channel will be effectively suspended only after the transfer of this single/burst data is finished.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma)
+{
+  /* Get tick number */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the DMA peripheral handle */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  if (hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Suspend the channel */
+    hdma->Instance->CCR |= DMA_CCR_SUSP;
+
+    /* Check if the DMA channel is suspended */
+    while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
+    {
+      /* Check for the timeout */
+      if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update the DMA channel error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+        /* Update the DMA channel state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_SUSPEND;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode).
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma)
+{
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  if (hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Suspend the DMA channel and activate suspend interrupt */
+    hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume any suspended DMA channel transfer.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma)
+{
+  /* Check the DMA peripheral handle parameter */
+  if (hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check DMA channel state */
+  if (hdma->State != HAL_DMA_STATE_SUSPEND)
+  {
+    /* Update the DMA channel error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Resume the DMA channel */
+    hdma->Instance->CCR &= (~DMA_CCR_SUSP);
+
+    /* Clear the suspend flag */
+    hdma->Instance->CFCR |= DMA_CFCR_SUSPF;
+
+    /* Update the DMA channel state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Exported_Functions_Group6
+  *
+@verbatim
+  ======================================================================================================================
+                               ##### Fifo status function #####
+  ======================================================================================================================
+    [..]
+      This section provides function allowing to get DMA channel FIFO level.
+
+    [..]
+      (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in
+          units of the programmed destination data.
+              (++) This API is available only for DMA channels that supports FIFO.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get and returns the DMA channel FIFO level.
+  * @param  hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval Returns the number of available beats in FIFO.
+  */
+uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma)
+{
+  return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief    DMAEx Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
+  *                specified DMA Channel.
+  * @retval None.
+  */
+static void DMA_List_Init(DMA_HandleTypeDef const *const hdma)
+{
+  uint32_t tmpreg;
+
+  /* Prepare DMA Channel Control Register (CCR) value */
+  tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode;
+
+  /* Check DMA channel instance */
+  if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
+  {
+    tmpreg |= hdma->InitLinkedList.LinkAllocatedPort;
+  }
+
+  /* Write DMA Channel Control Register (CCR) */
+  MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
+
+  /* Write DMA Channel Control Register (CTR1) */
+  WRITE_REG(hdma->Instance->CTR1, 0U);
+
+  /* Write DMA Channel Control Register (CTR2) */
+  WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode);
+
+  /* Write DMA Channel Control Register (CBR1) */
+  WRITE_REG(hdma->Instance->CBR1, 0U);
+
+  /* Write DMA Channel Control Register (CSAR) */
+  WRITE_REG(hdma->Instance->CSAR, 0U);
+
+  /* Write DMA Channel Control Register (CDAR) */
+  WRITE_REG(hdma->Instance->CDAR, 0U);
+
+  /* If 2D Addressing is supported by current channel */
+  if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
+  {
+    /* Write DMA Channel Control Register (CTR3) */
+    WRITE_REG(hdma->Instance->CTR3, 0U);
+
+    /* Write DMA Channel Control Register (CBR2) */
+    WRITE_REG(hdma->Instance->CBR2, 0U);
+  }
+
+  /* Write DMA Channel linked-list address register (CLLR) */
+  WRITE_REG(hdma->Instance->CLLR, 0U);
+}
+
+/**
+  * @brief  Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef.
+  * @param  pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+  *                       specified DMA linked-list Node.
+  * @param  pNode       : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+  *                       configurations.
+  * @retval None.
+  */
+static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
+                               DMA_NodeTypeDef *const pNode)
+{
+  int32_t blockoffset;
+
+  /* Update CTR1 register value ***************************************************************************************/
+  /* Prepare DMA channel transfer register (CTR1) value */
+  pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc                     |
+                                                   pNodeConfig->Init.DestDataWidth               |
+                                                   pNodeConfig->DataHandlingConfig.DataAlignment |
+                                                   pNodeConfig->Init.SrcInc                      |
+                                                   pNodeConfig->Init.SrcDataWidth;
+
+#if defined (CPU_IN_SECURE_STATE)
+  /* set source channel security attribute */
+  if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC)
+  {
+    pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC;
+  }
+
+  /* set destination channel security attribute */
+  if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC)
+  {
+    pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC;
+  }
+#endif /* CPU_IN_SECURE_STATE */
+
+  /* Add parameters related to DMA configuration */
+  if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U)
+  {
+    /* Prepare DMA channel transfer register (CTR1) value */
+    pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |=
+      (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange |
+       (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)    |
+       (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
+  }
+  /*********************************************************************************** CTR1 register value is updated */
+
+
+  /* Update CTR2 register value ***************************************************************************************/
+  /* Prepare DMA channel transfer register 2 (CTR2) value */
+  pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode |
+                                                   (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ));
+
+  /* Check for memory to peripheral transfer */
+  if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Check for GPDMA OR HPDMA */
+    if ((pNodeConfig->NodeType & (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_HPDMA)) != 0U)
+    {
+      pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ;
+    }
+  }
+  /* Memory to memory transfer */
+  else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY)
+  {
+    pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ;
+  }
+  else
+  {
+    /* Prevent MISRA-C2012-Rule-15.7 */
+  }
+
+  /* Configure HW Peripheral flow control selection */
+  pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= pNodeConfig->Init.Mode;
+
+  /* Check if trigger feature is active */
+  if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED)
+  {
+    /* Prepare DMA channel transfer register 2 (CTR2) value */
+    pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |=
+      pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity |
+      ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
+  }
+  /*********************************************************************************** CTR2 register value is updated */
+
+
+  /* Update CBR1 register value ***************************************************************************************/
+  /* Prepare DMA channel block register 1 (CBR1) value */
+  pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT);
+
+  /* If 2D addressing is supported by the selected DMA channel */
+  if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+  {
+    /* Set the new CBR1 Register value */
+    pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |=
+      (((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
+
+    /* If the source address offset is negative, set SDEC bit */
+    if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0)
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC;
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC);
+    }
+
+    /* If the destination address offset is negative, set DDEC bit */
+    if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0)
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC;
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC);
+    }
+
+    /* If the repeated block source address offset is negative, set BRSEC bit */
+    if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0)
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC;
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC);
+    }
+
+    /* if the repeated block destination address offset is negative, set BRDEC bit */
+    if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0)
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC;
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC);
+    }
+  }
+  /*********************************************************************************** CBR1 register value is updated */
+
+
+  /* Update CSAR register value ***************************************************************************************/
+  pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress;
+  /*********************************************************************************** CSAR register value is updated */
+
+
+  /* Update CDAR register value ***************************************************************************************/
+  pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress;
+  /*********************************************************************************** CDAR register value is updated */
+
+  /* Check if the selected channel is 2D addressing */
+  if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+  {
+    /* Update CTR3 register value *************************************************************************************/
+    /* Write new CTR3 Register value : source address offset */
+    if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0)
+    {
+      blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset);
+      pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO);
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] =
+        ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO);
+    }
+
+    /* Write new CTR3 Register value : destination address offset */
+    if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0)
+    {
+      blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset);
+      pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO);
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |=
+        (((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO);
+    }
+    /********************************************************************************* CTR3 register value is updated */
+
+
+    /* Update CBR2 register value *************************************************************************************/
+    /* Write new CBR2 Register value : repeated block source address offset */
+    if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0)
+    {
+      blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset);
+      pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO);
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] =
+        ((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO);
+    }
+
+    /* Write new CBR2 Register value : repeated block destination address offset */
+    if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0)
+    {
+      blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset);
+      pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |=
+        (((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos);
+    }
+    else
+    {
+      pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |=
+        (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO);
+    }
+    /********************************************************************************* CBR2 register value is updated */
+
+    /* Update CLLR register value *************************************************************************************/
+    /* Reset CLLR Register value : channel linked-list address register offset */
+    pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U;
+    /********************************************************************************* CLLR register value is cleared */
+  }
+  else
+  {
+    /* Update CLLR register value *************************************************************************************/
+    /* Reset CLLR Register value : channel linked-list address register offset */
+    pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U;
+    /********************************************************************************* CLLR register value is cleared */
+  }
+
+  /* Update node information value ************************************************************************************/
+  /* Set node information */
+  pNode->NodeInfo = pNodeConfig->NodeType;
+  if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+  {
+    pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS);
+  }
+  else
+  {
+    pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS);
+  }
+  /******************************************************************************** Node information value is updated */
+}
+
+/**
+  * @brief  Get a DMA channel node configuration.
+  * @param  pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
+  *                       specified DMA linked-list Node.
+  * @param  pNode       : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+  *                       configurations.
+  * @retval None.
+  */
+static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
+                                   DMA_NodeTypeDef const *const pNode)
+{
+  uint16_t offset;
+
+  /* Get node information *********************************************************************************************/
+  pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK);
+  /*************************************************************************************** Node type value is updated */
+
+
+  /* Get CTR1 fields values *******************************************************************************************/
+  pNodeConfig->Init.SrcInc                      = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET]   & DMA_CTR1_SINC;
+  pNodeConfig->Init.DestInc                     = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET]   & DMA_CTR1_DINC;
+  pNodeConfig->Init.SrcDataWidth                = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET]   & DMA_CTR1_SDW_LOG2;
+  pNodeConfig->Init.DestDataWidth               = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET]   & DMA_CTR1_DDW_LOG2;
+  pNodeConfig->Init.SrcBurstLength              = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
+                                                    DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U;
+  pNodeConfig->Init.DestBurstLength             = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
+                                                    DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U;
+  pNodeConfig->Init.TransferAllocatedPort       = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET]   &
+                                                  (DMA_CTR1_SAP | DMA_CTR1_DAP);
+  pNodeConfig->DataHandlingConfig.DataExchange  = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET]   &
+                                                  (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX | DMA_CTR1_DWX);
+  pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET]   & DMA_CTR1_PAM;
+#if defined (CPU_IN_SECURE_STATE)
+  if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U)
+  {
+    pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC;
+  }
+  else
+  {
+    pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC;
+  }
+
+  if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U)
+  {
+    pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC;
+  }
+  else
+  {
+    pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC;
+  }
+#endif /* CPU_IN_SECURE_STATE */
+  /*********************************************************************************** CTR1 fields values are updated */
+
+
+  /* Get CTR2 fields values *******************************************************************************************/
+  if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U)
+  {
+    pNodeConfig->Init.Request   = DMA_REQUEST_SW;
+    pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY;
+  }
+  else
+  {
+    pNodeConfig->Init.Request   = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL;
+
+    if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U)
+    {
+      pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH;
+    }
+    else
+    {
+      pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY;
+    }
+  }
+
+  pNodeConfig->Init.BlkHWRequest              = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ);
+  pNodeConfig->TriggerConfig.TriggerMode      = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET]  & DMA_CTR2_TRIGM;
+  pNodeConfig->TriggerConfig.TriggerPolarity  = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET]  & DMA_CTR2_TRIGPOL;
+  pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] &
+                                                 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos;
+  pNodeConfig->Init.TransferEventMode         = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET]  & DMA_CTR2_TCEM;
+  /*********************************************************************************** CTR2 fields values are updated */
+
+
+  /* Get CBR1 fields **************************************************************************************************/
+  pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT;
+
+  if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+  {
+    pNodeConfig->RepeatBlockConfig.RepeatCount =
+      ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U;
+  }
+  else
+  {
+    pNodeConfig->RepeatBlockConfig.RepeatCount = 1U;
+  }
+  /*********************************************************************************** CBR1 fields values are updated */
+
+
+  /* Get CSAR field ***************************************************************************************************/
+  pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET];
+  /************************************************************************************** CSAR field value is updated */
+
+
+  /* Get CDAR field ***************************************************************************************************/
+  pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET];
+  /************************************************************************************** CDAR field value is updated */
+
+  /* Check if the selected channel is 2D addressing */
+  if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+  {
+    /* Get CTR3 field *************************************************************************************************/
+    offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO);
+    pNodeConfig->RepeatBlockConfig.SrcAddrOffset  = (int32_t)offset;
+
+    offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
+    pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset;
+
+    if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U)
+    {
+      pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1);
+    }
+
+    if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U)
+    {
+      pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1);
+    }
+    /************************************************************************************ CTR3 field value is updated */
+
+
+    /* Get CBR2 fields ************************************************************************************************/
+    offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO);
+    pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset;
+
+    offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
+    pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset;
+
+    if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U)
+    {
+      pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1);
+    }
+
+    if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U)
+    {
+      pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1);
+    }
+    /************************************************************************************ CBR2 field value is updated */
+  }
+  else
+  {
+    /* Get CTR3 field *************************************************************************************************/
+    pNodeConfig->RepeatBlockConfig.SrcAddrOffset     = 0;
+    pNodeConfig->RepeatBlockConfig.DestAddrOffset    = 0;
+    /************************************************************************************ CTR3 field value is updated */
+
+
+    /* Get CBR2 fields ************************************************************************************************/
+    pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset  = 0;
+    pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0;
+    /************************************************************************************ CBR2 field value is updated */
+  }
+}
+
+/**
+  * @brief  Check nodes base addresses compatibility.
+  * @param  pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
+  * @param  pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
+  * @param  pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
+  * @retval Return 0 when nodes addresses are compatible, 1 otherwise.
+  */
+static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
+                                                 DMA_NodeTypeDef const *const pNode2,
+                                                 DMA_NodeTypeDef const *const pNode3)
+{
+  uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA);
+  uint32_t ref  = 0U;
+
+  /* Check node 1 address */
+  if ((uint32_t)pNode1 != 0U)
+  {
+    ref = (uint32_t)pNode1;
+  }
+  /* Check node 2 address */
+  else if ((uint32_t)pNode2 != 0U)
+  {
+    ref = (uint32_t)pNode2;
+  }
+  /* Check node 3 address */
+  else if ((uint32_t)pNode3 != 0U)
+  {
+    ref = (uint32_t)pNode3;
+  }
+  else
+  {
+    /* Prevent MISRA-C2012-Rule-15.7 */
+  }
+
+  /* Check addresses compatibility */
+  if (temp != ((uint32_t)ref & DMA_CLBAR_LBA))
+  {
+    return 1U;
+  }
+
+  return 0U;
+}
+
+/**
+  * @brief  Check nodes types compatibility.
+  * @param  pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
+  * @param  pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
+  * @param  pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
+  * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible.
+  */
+static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
+                                         DMA_NodeTypeDef const *const pNode2,
+                                         DMA_NodeTypeDef const *const pNode3)
+{
+  uint32_t ref = 0U;
+
+  /* Check node 1 parameter */
+  if (pNode1 != NULL)
+  {
+    ref = pNode1->NodeInfo & NODE_TYPE_MASK;
+  }
+  /* Check node 2 parameter */
+  else if (pNode2 != NULL)
+  {
+    ref = pNode2->NodeInfo & NODE_TYPE_MASK;
+  }
+  /* Check node 3 parameter */
+  else if (pNode3 != NULL)
+  {
+    ref = pNode3->NodeInfo & NODE_TYPE_MASK;
+  }
+  else
+  {
+    /* Prevent MISRA-C2012-Rule-15.7 */
+  }
+
+  /* Check node 2 parameter */
+  if (pNode2 != NULL)
+  {
+    /* Check node type compatibility */
+    if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK))
+    {
+      return 2U;
+    }
+  }
+
+  /* Check node 3 parameter */
+  if (pNode3 != NULL)
+  {
+    /* Check node type compatibility */
+    if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK))
+    {
+      return 3U;
+    }
+  }
+
+  return 0U;
+}
+
+/**
+  * @brief  Check nodes types compatibility.
+  * @param  pNode       : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+  *                       configurations.
+  * @param  cllr_mask   : Pointer to CLLR register mask value.
+  * @param  cllr_offset : Pointer to CLLR register offset value.
+  * @retval None.
+  */
+static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
+                                     uint32_t *const cllr_mask,
+                                     uint32_t *const cllr_offset)
+{
+  /* Check node type */
+  if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
+  {
+    /* Update CLLR register mask value */
+    if (cllr_mask != NULL)
+    {
+      *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 |
+                   DMA_CLLR_UB2 | DMA_CLLR_ULL;
+    }
+
+    /* Update CLLR register offset */
+    if (cllr_offset != NULL)
+    {
+      *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET;
+    }
+  }
+  /* Update CLLR and register number for linear addressing node */
+  else
+  {
+    /* Update CLLR register mask value */
+    if (cllr_mask != NULL)
+    {
+      *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL;
+    }
+
+    /* Update CLLR register offset */
+    if (cllr_offset != NULL)
+    {
+      *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET;
+    }
+  }
+}
+
+/**
+  * @brief  Find node in queue.
+  * @param  pQList   : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  pNode    : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations.
+  * @param  NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information.
+  * @retval Return 0 when node is found in selected queue, otherwise node is not found.
+  */
+static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList,
+                                  DMA_NodeTypeDef const *const pNode,
+                                  DMA_NodeInQInfoTypeDef *const NodeInfo)
+{
+  uint32_t node_idx = 0U;
+  uint32_t currentnode_address  = 0U;
+  uint32_t previousnode_address  = 0U;
+  uint32_t cllr_offset = NodeInfo->cllr_offset;
+
+  /* Find last node in queue */
+  if (pNode ==  NULL)
+  {
+    /* Check that previous node is linked to the selected queue */
+    while (node_idx < pQList->NodeNumber)
+    {
+      /* Get head node address */
+      if (node_idx == 0U)
+      {
+        currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
+      }
+      /* Calculate nodes addresses */
+      else
+      {
+        previousnode_address = currentnode_address;
+        currentnode_address =
+          ((DMA_NodeTypeDef *)(currentnode_address +
+                               ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+      }
+
+      /* Increment node index */
+      node_idx++;
+    }
+  }
+  /* Find selected node node in queue */
+  else
+  {
+    /* Check that previous node is linked to the selected queue */
+    while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)))
+    {
+      /* Get head node address */
+      if (node_idx == 0U)
+      {
+        currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
+      }
+      /* Calculate nodes addresses */
+      else
+      {
+        previousnode_address = currentnode_address;
+        currentnode_address =
+          ((DMA_NodeTypeDef *)(currentnode_address +
+                               ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+      }
+
+      /* Increment node index */
+      node_idx++;
+    }
+  }
+
+  /* Check stored address */
+  if (pNode != NULL)
+  {
+    if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))
+    {
+      return 1U;
+    }
+  }
+
+  /* Update current node position */
+  NodeInfo->currentnode_pos = node_idx;
+
+  /* Update previous node address */
+  NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+
+  /* Update current node address */
+  NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+
+  /* Update next node address */
+  if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U)
+  {
+    NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] &
+                               DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+  }
+
+  return 0U;
+}
+
+/**
+  * @brief  Reset queue nodes.
+  * @param  pQList   : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information.
+  * @retval None.
+  */
+static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList,
+                                     DMA_NodeInQInfoTypeDef const *const NodeInfo)
+{
+  uint32_t node_idx = 0U;
+  uint32_t currentnode_address  = 0U;
+  uint32_t previousnode_address;
+  uint32_t cllr_offset = NodeInfo->cllr_offset;
+
+  /* Check that previous node is linked to the selected queue */
+  while (node_idx < pQList->NodeNumber)
+  {
+    /* Get head node address */
+    if (node_idx == 0U)
+    {
+      previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
+      currentnode_address  = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA);
+    }
+    /* Calculate nodes addresses */
+    else
+    {
+      previousnode_address = currentnode_address;
+      currentnode_address =
+        ((DMA_NodeTypeDef *)(currentnode_address +
+                             ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
+    }
+
+    /* Reset node */
+    ((DMA_NodeTypeDef *)(previousnode_address +
+                         ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U;
+
+    /* Increment node index */
+    node_idx++;
+  }
+}
+
+/**
+  * @brief  Fill source node registers values by destination nodes registers values.
+  * @param  pSrcNode  : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers
+  *                     configurations.
+  * @param  pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers
+  *                     configurations.
+  * @retval None.
+  */
+static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode,
+                              DMA_NodeTypeDef *const pDestNode)
+{
+  /* Repeat for all register nodes */
+  for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++)
+  {
+    pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx];
+  }
+
+  /* Fill node information */
+  pDestNode->NodeInfo = pSrcNode->NodeInfo;
+}
+
+/**
+  * @brief  Convert node to dynamic.
+  * @param  ContextNodeAddr : The context node address.
+  * @param  CurrentNodeAddr : The current node address to be converted.
+  * @param  RegisterNumber  : The register number to be converted.
+  * @retval None.
+  */
+static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr,
+                                          uint32_t CurrentNodeAddr,
+                                          uint32_t RegisterNumber)
+{
+  uint32_t currentnode_reg_counter = 0U;
+  uint32_t contextnode_reg_counter = 0U;
+  uint32_t cllr_idx = RegisterNumber - 1U;
+  DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
+  DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
+  uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
+                                             DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
+                                            };
+
+  /* Update ULL position according to register number */
+  update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U];
+
+  /* Repeat for all node registers */
+  while (contextnode_reg_counter != RegisterNumber)
+  {
+    /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */
+    if ((context_node->LinkRegisters[contextnode_reg_counter]  ==
+         current_node->LinkRegisters[currentnode_reg_counter]) &&
+        (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET)  &&
+        (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET)  &&
+        (contextnode_reg_counter != (RegisterNumber - 1U)))
+    {
+      /* Format the node according to unused registers */
+      DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT);
+
+      /* Update CLLR index */
+      cllr_idx --;
+
+      /* Update CLLR fields */
+      current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter];
+    }
+    else
+    {
+      /* Update context node register fields with new values */
+      context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter];
+
+      /* Update CLLR fields */
+      current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter];
+
+      /* Increment current node number register counter */
+      currentnode_reg_counter++;
+    }
+
+    /* Increment context node number register counter */
+    contextnode_reg_counter++;
+  }
+
+  /* Update node information */
+  MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS));
+
+  /* Clear unused node fields */
+  DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter);
+}
+
+/**
+  * @brief  Convert node to static.
+  * @param  ContextNodeAddr : The context node address.
+  * @param  CurrentNodeAddr : The current node address to be converted.
+  * @param  RegisterNumber  : The register number to be converted.
+  * @retval None.
+  */
+static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr,
+                                         uint32_t CurrentNodeAddr,
+                                         uint32_t RegisterNumber)
+{
+  uint32_t contextnode_reg_counter = 0U;
+  uint32_t cllr_idx;
+  uint32_t cllr_mask;
+  const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
+  DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
+  uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
+                                             DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
+                                            };
+
+  /* Update ULL position according to register number */
+  update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U];
+
+  /* Get context node CLLR information */
+  cllr_idx  = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+  cllr_mask = context_node->LinkRegisters[cllr_idx];
+
+  /* Repeat for all node registers */
+  while (contextnode_reg_counter != RegisterNumber)
+  {
+    /* Check if node field is dynamic */
+    if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U)
+    {
+      /* Format the node according to unused registers */
+      DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT);
+
+      /* Update node field */
+      current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter];
+    }
+
+    /* Increment context node number register counter */
+    contextnode_reg_counter++;
+  }
+
+  /* Update node information */
+  MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS));
+}
+
+/**
+  * @brief  Format the node according to unused registers.
+  * @param  pNode           : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+  *                           configurations.
+  * @param  RegisterIdx     : The first register index to be formatted.
+  * @param  RegisterNumber  : The number of node registers.
+  * @param  Format          : The format type.
+  * @retval None.
+  */
+static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode,
+                                uint32_t RegisterIdx,
+                                uint32_t RegisterNumber,
+                                uint32_t Format)
+{
+  if (Format == NODE_DYNAMIC_FORMAT)
+  {
+    /* Repeat for all registers to be formatted */
+    for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++)
+    {
+      pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U];
+    }
+  }
+  else
+  {
+    /* Repeat for all registers to be formatted */
+    for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--)
+    {
+      pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U];
+    }
+  }
+}
+
+/**
+  * @brief  Clear unused register fields.
+  * @param  pNode            : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
+  *                            configurations.
+  * @param  FirstUnusedField : The first unused field to be cleared.
+  * @retval None.
+  */
+static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode,
+                                       uint32_t FirstUnusedField)
+{
+  /* Repeat for all unused fields */
+  for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++)
+  {
+    pNode->LinkRegisters[reg_idx] = 0U;
+  }
+}
+
+/**
+  * @brief  Update CLLR for all dynamic queue nodes.
+  * @param  pQList :              Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  LastNode_IsCircular : The first circular node is the last queue node or not.
+  * @retval None.
+  */
+static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+                                                 uint32_t LastNode_IsCircular)
+{
+  uint32_t previous_cllr_offset;
+  uint32_t current_cllr_offset = 0U;
+  uint32_t previousnode_addr;
+  uint32_t currentnode_addr = (uint32_t)pQList->Head;
+  uint32_t cllr_mask;
+  uint32_t node_idx = 0U;
+
+  /*  Repeat for all register nodes */
+  while (node_idx < pQList->NodeNumber)
+  {
+    /* Get head node address */
+    if (node_idx == 0U)
+    {
+      /* Get current node information */
+      current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+    }
+    /* Calculate nodes addresses */
+    else
+    {
+      /* Get previous node information */
+      previousnode_addr = currentnode_addr;
+      previous_cllr_offset = current_cllr_offset;
+
+      /* Get current node information */
+      currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) +
+                         ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
+      current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+
+      /* Calculate CLLR register value to be updated */
+      cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) |
+                  (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA);
+
+      /* Set new CLLR value to previous node */
+      ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask;
+    }
+
+    /* Increment node index */
+    node_idx++;
+  }
+
+  /* Check queue circularity */
+  if (pQList->FirstCircularNode != 0U)
+  {
+    /* First circular queue is not last queue node */
+    if (LastNode_IsCircular == 0U)
+    {
+      /* Get CLLR node information */
+      DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL);
+
+      /* Update CLLR register for last circular node */
+      ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] =
+        ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
+    }
+    /* First circular queue is last queue node */
+    else
+    {
+      /* Disable CLLR updating */
+      ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL;
+    }
+  }
+  else
+  {
+    /* Clear CLLR register for last node */
+    ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U;
+  }
+}
+
+/**
+  * @brief  Update CLLR for all static queue nodes.
+  * @param  pQList    : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @param  operation : The operation type.
+  * @retval None.
+  */
+static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
+                                                uint32_t operation)
+{
+  uint32_t currentnode_addr = (uint32_t)pQList->Head;
+  uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+  uint32_t cllr_default_offset;
+  uint32_t cllr_default_mask;
+  uint32_t cllr_mask;
+  uint32_t node_idx = 0U;
+
+  /* Get CLLR node information */
+  DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset);
+
+  /*  Repeat for all register nodes (Bypass last queue node) */
+  while (node_idx < pQList->NodeNumber)
+  {
+    if (operation == UPDATE_CLLR_POSITION)
+    {
+      /* Get CLLR value */
+      cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset];
+    }
+    else
+    {
+      /* Calculate CLLR value */
+      cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) |
+                  cllr_default_mask;
+    }
+
+    /* Set new CLLR value to default position */
+    if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL))
+    {
+      ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U;
+    }
+    else
+    {
+      ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask;
+    }
+
+    /* Update current node address with next node address */
+    currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA);
+
+    /* Update current CLLR offset with next CLLR offset */
+    current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
+
+    /* Increment node index */
+    node_idx++;
+  }
+}
+
+/**
+  * @brief  Clean linked-list queue variable.
+  * @param  pQList    : Pointer to a DMA_QListTypeDef structure that contains queue information.
+  * @retval None.
+  */
+static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList)
+{
+  /* Clear head node */
+  pQList->Head = NULL;
+
+  /* Clear first circular queue node */
+  pQList->FirstCircularNode = NULL;
+
+  /* Reset node number */
+  pQList->NodeNumber = 0U;
+
+  /* Reset queue state */
+  pQList->State = HAL_DMA_QUEUE_STATE_RESET;
+
+  /* Reset queue error code */
+  pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
+
+  /* Reset queue type */
+  pQList->Type = QUEUE_TYPE_STATIC;
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dts.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dts.c
new file mode 100644
index 000000000..55ef60c39
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_dts.c
@@ -0,0 +1,1915 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_dts.c
+  * @author  MCD Application Team
+  * @brief   DTS HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DTS peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Temperature measurement functions.
+  *           + Alarms functions.
+  *           + Sample counter functions.
+  *           + Get extreme temperatures and handle state functions.
+  *
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  @verbatim
+  ======================================================================================================================
+                                      ##### DTS Peripheral features #####
+  ======================================================================================================================
+
+  [..]
+      The DTS hardware IP is a high-precision low-power junction temperature sensor (TS). It is composed of a
+      configurable controller plus two embedded temperature sensors.
+      In addition of temperature measurements, we have following features for each temperature sensor:
+
+      (+) Two programmable alarms incorporating hysteresis.
+      (+) Recording of the minimum and maximum temperatures measured.
+
+      A sample counter is also available.
+
+  ======================================================================================================================
+                                      ##### How to use this driver #####
+  ======================================================================================================================
+  [..]
+    *** Initialization and de-initialization ***
+    ============================================
+    [..]
+      (#) User has first to initialize DTS instance.
+      (#) As prerequisite, fill in the HAL_DTS_MspInit():
+        (++) Enable DTS clock interface with __HAL_RCC_DTS_CLK_ENABLE().
+        (++) If interrupt mode is used, enable and configure DTS interrupt with HAL_NVIC_SetPriority()
+             and HAL_NVIC_EnableIRQ().
+      (#) Call HAL_DTS_Init() function.
+
+    [..]
+      (#) User can de-initialize DTS instance with HAL_DTS_DeInit() function.
+
+    *** Temperature measurement ***
+    ===============================
+    [..]
+      (#) Configure senors using HAL_DTS_ConfigSensor() for each sensor.
+      (#) In polling mode:
+            (++) Use HAL_DTS_Start() to start temperature measurement.
+            (++) Use HAL_DTS_PollForTemperature() to detect the end of measurement.
+                 Use HAL_DTS_GetTemperature to get measured temperature.
+      (#) In interrupt mode:
+            (++) Use HAL_DTS_Start_IT() to start temperature measurement.
+            (++) HAL_DTS_TemperatureCallback() will be called at the end of measurement.
+                 Use HAL_DTS_GetTemperature to get measured temperature.
+      (#) Use HAL_DTS_GetExtremeTemperatures() to get the extreme measured temperatures.
+      (#) Stop measurement using HAL_DTS_Stop() or HAL_DTS_Stop_IT().
+      (#) Configure sample counter using HAL_DTS_ConfigSampleCounter().
+      (#) Get sample counter value using HAL_DTS_GetSampleCounter().
+      (#) Activate sample discard using HAL_DTS_ConfigSampleDiscard().
+
+    *** Alarms usage ***
+    ====================
+    [..]
+      (#) Configure alarms using HAL_DTS_ConfigAlarmX() for each sensor (X is A or B).
+      (#] HAL_DTS_AlarmXCallback() will be called when alarm X occurs (X is A or B).
+      (#) Disable alarms using HAL_DTS_ConfigAlarmX() (X is A or B).
+
+    *** generic functions ***
+    =========================
+    [..]
+      (#) HAL_DTS_IRQHandler will be called when DTS interrupt occurs.
+      (#) HAL_DTS_ErrorCallback will be called when DTS error occurs.
+      (#) Use HAL_DTS_GetState() to get the current DTS instance state.
+
+    *** Callback registration ***
+    =============================
+    [..]
+      The compilation define USE_HAL_DTS_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+      Use functions HAL_DTS_RegisterCallback() to register a user callback.
+
+    [..]
+      Functions HAL_DTS_RegisterCallback() and HAL_DTS_UnRegisterCallback allow to register
+      and unregister following callbacks:
+        (+) MspInitCallback     : MSP init callback.
+        (+) MspDeInitCallback   : MSP de-init callback.
+
+    [..]
+      For temperature measurement complete callback use dedicated register
+      and unregister callback functions:
+        (+) HAL_DTS_RegisterTemperatureCallback().
+        (+) HAL_DTS_UnRegisterTemperatureCallback().
+
+    [..]
+      For alarms callback use dedicated register and unregister callback functions:
+        (+) HAL_DTS_RegisterAlarmACallback().
+        (+) HAL_DTS_RegisterAlarmBCallback().
+        (+) HAL_DTS_UnRegisterAlarmACallback().
+        (+) HAL_DTS_UnRegisterAlarmBCallback().
+
+    [..]
+      For error callback use dedicated register and unregister callback functions:
+        (+) HAL_DTS_RegisterErrorCallback().
+        (+) HAL_DTS_UnRegisterErrorCallback().
+
+    [..]
+      By default, after the call of init function and if the state is RESET
+      all callbacks are reset to the corresponding legacy weak functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak functions in the init and de-init only when these
+      callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the init and de-init keep and use
+      the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the init/de-init.
+      In that case first register the MspInit/MspDeInit user callbacks using
+      HAL_DTS_RegisterCallback() before calling init or de-init function.
+
+    [..]
+      When the compilation define USE_HAL_DTS_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak callbacks are used.
+
+  @endverbatim
+  **********************************************************************************************************************
+  */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+
+/** @defgroup DTS DTS
+  * @brief DTS HAL module driver
+  * @{
+  */
+
+/* Private typedef ---------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DTS_Private_Types  DTS Private Types
+  * @{
+  */
+/**
+  * @brief  DTS SDA registers
+  */
+typedef enum
+{
+  DTS_SDATS_CR_REG     = 0x00000000U, /*!< SDA TS control register */
+  DTS_SDATS_CFGR_REG   = 0x01000000U, /*!< SDA TS configuration register */
+  DTS_SDATS_TIMERR_REG = 0x05000000U, /*!< SDA TS timer register */
+} DTS_SdaRegisterTypeDef;
+/**
+  * @}
+  */
+
+/* Private define ----------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DTS_Private_Define  DTS Private Define
+  * @{
+  */
+#define DTS_SENSOR_ALL            2U          /* DTS sensor 0 and sensor 1 */
+#define DTS_MAXIMUM_TIMEOUT       1000U       /* DTS maximum timeout of 1 second */
+#define DTS_SDA_SENSOR_POWER_DOWN 0x00000001U /* Value to set on SDATS_CR register to power down sensor */
+#define DTS_SDA_POWER_UP_DELAY    256U        /* Value to set on SDATS_TIMERR register for power-up typical delay */
+#define DTS_CAL5_PARAM            4094.0f     /* Cal5 parameter used for temperature ccomputation */
+#define DTS_J_PARAM               -0.1f       /* J parameter used for temperature ccomputation */
+#define DTS_H_PARAM               200.0f      /* H parameter used for temperature ccomputation */
+#define DTS_G_PARAM               60.0f       /* G parameter used for temperature ccomputation */
+/**
+  * @}
+  */
+
+/* Private macro -----------------------------------------------------------------------------------------------------*/
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/* Private function prototypes ---------------------------------------------------------------------------------------*/
+
+/** @defgroup DTS_Private_Functions  DTS Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef DTS_ProgramSdaRegister(DTS_HandleTypeDef *hdts, uint32_t Sensor,
+                                                DTS_SdaRegisterTypeDef Reg, uint32_t Value);
+static float_t           DTS_ConvertToCelsiusDegree(uint32_t sample);
+static uint32_t          DTS_ConvertFromCelsiusDegree(float_t temperature);
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+
+/** @defgroup DTS_Exported_Functions  DTS Exported Functions
+  * @{
+  */
+
+/** @defgroup DTS_Exported_Functions_Group1  Initialization and de-initialization functions
+  * @brief    Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Initialize the DTS instance.
+      (+) De-initialize the DTS instance.
+      (+) Register and unregister callbacks.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DTS instance and configure DTS system clock.
+  * @param  hdts DTS handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check DTS handle */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check that instance has not been already initialized */
+    if (hdts->State != HAL_DTS_STATE_RESET)
+    {
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+    else
+    {
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+      /* Reset callback pointers to the weak predefined callbacks */
+      hdts->TemperatureCallback = HAL_DTS_TemperatureCallback;
+      hdts->AlarmACallback      = HAL_DTS_AlarmACallback;
+      hdts->AlarmBCallback      = HAL_DTS_AlarmBCallback;
+      hdts->ErrorCallback       = HAL_DTS_ErrorCallback;
+
+      /* Call DTS MSP init function */
+      if (hdts->MspInitCallback == NULL)
+      {
+        hdts->MspInitCallback = HAL_DTS_MspInit;
+      }
+      hdts->MspInitCallback(hdts);
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+      /* Call DTS MSP init function */
+      HAL_DTS_MspInit(hdts);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
+      /* Configure DTS TS clock to TS operating frequency range (4MHz to 8MHz). */
+      /* DTS kernel clock (hsi_div8_ck clock) is divided by (CLK_SYNTH_HI + 1) + (CLK_SYNTH_LO + 1). */
+      /* Because HSI frequency is 64MHz, hsi_div8_ck frequency is 8MHz. */
+      /* So CLK_SYNTH_HI and CLK_SYNTH_LO have to be set to 0 on TSCCLKSYNTHR register */
+      /* in order to have TS clock frequency at 4MHz. */
+      hdts->Instance->TSCCLKSYNTHR = (DTS_TSCCLKSYNTHR_CLK_SYNTH_EN |
+                                      (1U << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos));
+
+      /* Program typical power-up delay for all sensors */
+      status = DTS_ProgramSdaRegister(hdts, DTS_SENSOR_ALL, DTS_SDATS_TIMERR_REG, DTS_SDA_POWER_UP_DELAY);
+
+      if (status == HAL_OK)
+      {
+        /* Enable TS interrupt */
+        hdts->Instance->PVT_IER = DTS_PVT_IER_TS_IRQ_ENABLE;
+
+        /* Reset sensor modes and error code and update state */
+        hdts->SensorMode[0U] = DTS_SENSOR_MODE_DISABLE;
+        hdts->SensorMode[1U] = DTS_SENSOR_MODE_DISABLE;
+        hdts->ErrorCode      = HAL_DTS_ERROR_NONE;
+        /* Update state */
+        hdts->State = HAL_DTS_STATE_READY;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  De-initialize the DTS instance.
+  * @param  hdts DTS handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check DTS handle */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check that instance has not been already deinitialized */
+    if (hdts->State == HAL_DTS_STATE_RESET)
+    {
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Power down temperature sensors */
+      status = DTS_ProgramSdaRegister(hdts, DTS_SENSOR_ALL, DTS_SDATS_CR_REG, DTS_SDA_SENSOR_POWER_DOWN);
+
+      if (status == HAL_OK)
+      {
+        /* Disable all interrupts */
+        DTS_Sensor0->TS_IER = 0U;
+        DTS_Sensor1->TS_IER = 0U;
+
+        /* Clear all pendings flags */
+        DTS_Sensor0->TS_ICR = (DTS_TS_ICR_IRQ_CLEAR_FAULT  | DTS_TS_ICR_IRQ_CLEAR_DONE |
+                               DTS_TS_ICR_IRQ_CLEAR_ALARMA | DTS_TS_ICR_IRQ_CLEAR_ALARMB);
+        DTS_Sensor1->TS_ICR = (DTS_TS_ICR_IRQ_CLEAR_FAULT  | DTS_TS_ICR_IRQ_CLEAR_DONE |
+                               DTS_TS_ICR_IRQ_CLEAR_ALARMA | DTS_TS_ICR_IRQ_CLEAR_ALARMB);
+
+        /* Disable TS interrupt */
+        hdts->Instance->PVT_IER = 0U;
+
+        /* Disable DTS system clock */
+        hdts->Instance->TSCCLKSYNTHR &= ~(DTS_TSCCLKSYNTHR_CLK_SYNTH_EN);
+
+        /* Call DTS MSP deinit function */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+        if (hdts->MspDeInitCallback == NULL)
+        {
+          hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
+        }
+        hdts->MspDeInitCallback(hdts);
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+        HAL_DTS_MspDeInit(hdts);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
+        /*Update state */
+        hdts->State = HAL_DTS_STATE_RESET;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Initialize the DTS instance MSP.
+  * @param  hdts DTS handle.
+  * @retval None.
+  */
+__weak void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdts);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DTS_MspInit could be implemented in the user file */
+}
+
+/**
+  * @brief  De-initialize the DTS instance MSP.
+  * @param  hdts DTS handle.
+  * @retval None.
+  */
+__weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdts);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DTS_MspDeInit could be implemented in the user file */
+}
+
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a user DTS callback to be used instead of the weak predefined callback.
+  * @param  hdts DTS handle.
+  * @param  CallbackID ID of the callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @param  pCallback pointer to the callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef        *hdts,
+                                           HAL_DTS_CallbackIDTypeDef CallbackID,
+                                           pDTS_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pCallback == NULL)
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    if ((temp_state == HAL_DTS_STATE_READY) || (temp_state == HAL_DTS_STATE_RESET))
+    {
+      switch (CallbackID)
+      {
+        case HAL_DTS_MSPINIT_CB_ID :
+          hdts->MspInitCallback = pCallback;
+          break;
+        case HAL_DTS_MSPDEINIT_CB_ID :
+          hdts->MspDeInitCallback = pCallback;
+          break;
+        default :
+          hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Unregister a user DTS callback.
+  *         DTS callback is redirected to the weak predefined callback.
+  * @param  hdts DTS handle.
+  * @param  CallbackID ID of the callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef        *hdts,
+                                             HAL_DTS_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    if ((temp_state == HAL_DTS_STATE_READY) || (temp_state == HAL_DTS_STATE_RESET))
+    {
+      switch (CallbackID)
+      {
+        case HAL_DTS_MSPINIT_CB_ID :
+          hdts->MspInitCallback = HAL_DTS_MspInit;
+          break;
+        case HAL_DTS_MSPDEINIT_CB_ID :
+          hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
+          break;
+        default :
+          hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Register a user DTS sensor callback to be used instead of the weak predefined callback.
+  * @param  hdts DTS handle.
+  * @param  CallbackID ID of the sensor callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_DTS_SENSOR_TEMPERATURE_CB_ID Sensor temperature callback ID.
+  *           @arg @ref HAL_DTS_SENSOR_ALARMA_CB_ID Sensor alarm A callback ID.
+  *           @arg @ref HAL_DTS_SENSOR_ALARMB_CB_ID Sensor alarm B callback ID.
+  *           @arg @ref HAL_DTS_SENSOR_ERROR_CB_ID Sensor error callback ID.
+  * @param  pCallback pointer to the sensor callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_RegisterSensorCallback(DTS_HandleTypeDef              *hdts,
+                                                 HAL_DTS_SensorCallbackIDTypeDef CallbackID,
+                                                 pDTS_SensorCallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pCallback == NULL)
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hdts->State == HAL_DTS_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DTS_SENSOR_TEMPERATURE_CB_ID :
+          hdts->TemperatureCallback = pCallback;
+          break;
+        case HAL_DTS_SENSOR_ALARMA_CB_ID :
+          hdts->AlarmACallback = pCallback;
+          break;
+        case HAL_DTS_SENSOR_ALARMB_CB_ID :
+          hdts->AlarmBCallback = pCallback;
+          break;
+        case HAL_DTS_SENSOR_ERROR_CB_ID :
+          hdts->ErrorCallback = pCallback;
+          break;
+        default :
+          hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Unregister a user DTS sensor callback.
+  *         DTS sensor callback is redirected to the weak predefined callback.
+  * @param  hdts DTS handle.
+  * @param  CallbackID ID of the sensor callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_DTS_SENSOR_TEMPERATURE_CB_ID Sensor temperature callback ID.
+  *           @arg @ref HAL_DTS_SENSOR_ALARMA_CB_ID Sensor alarm A callback ID.
+  *           @arg @ref HAL_DTS_SENSOR_ALARMB_CB_ID Sensor alarm B callback ID.
+  *           @arg @ref HAL_DTS_SENSOR_ERROR_CB_ID Sensor error callback ID.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_UnRegisterSensorCallback(DTS_HandleTypeDef              *hdts,
+                                                   HAL_DTS_SensorCallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hdts->State == HAL_DTS_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DTS_SENSOR_TEMPERATURE_CB_ID :
+          hdts->TemperatureCallback = HAL_DTS_TemperatureCallback;
+          break;
+        case HAL_DTS_SENSOR_ALARMA_CB_ID :
+          hdts->AlarmACallback = HAL_DTS_AlarmACallback;
+          break;
+        case HAL_DTS_SENSOR_ALARMB_CB_ID :
+          hdts->AlarmBCallback = HAL_DTS_AlarmBCallback;
+          break;
+        case HAL_DTS_SENSOR_ERROR_CB_ID :
+          hdts->ErrorCallback = HAL_DTS_ErrorCallback;
+          break;
+        default :
+          hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup DTS_Exported_Functions_Group2  Temperature measurement functions
+  * @brief    Temperature measuremen functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Temperature measurement functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) configure sensor.
+      (+) Start and stop temperature measurement in polling or interrupt mode.
+      (+) Wait and get temperature values.
+      (+) Get extreme temperature values.
+      (+) Configure and get sample counter.
+      (+) Configure sample discard.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a sensor.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor to configure.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @param  pSensorParams Sensor parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_ConfigSensor(DTS_HandleTypeDef       *hdts,
+                                       HAL_DTS_Sensor           Sensor,
+                                       DTS_SensorConfigTypeDef *pSensorParams)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pSensorParams == NULL)
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    /* Check parameters */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+    assert_param(IS_DTS_SENSOR_MODE(pSensorParams->Mode));
+
+    /* Check current state */
+    if ((temp_state == HAL_DTS_STATE_READY) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_1) && (Sensor == DTS_SENSOR_0)) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_0) && (Sensor == DTS_SENSOR_1)))
+    {
+      if (pSensorParams->Mode != DTS_SENSOR_MODE_DISABLE)
+      {
+        /* Check resolution parameter */
+        assert_param(IS_DTS_SENSOR_RESOLUTION(pSensorParams->Resolution));
+
+        /* Program sensor trigger and resolution */
+        if (pSensorParams->Mode == DTS_SENSOR_MODE_TRIGGER)
+        {
+          /* Check sensor trigger parameter */
+          assert_param(IS_DTS_SENSOR_TRIGGER(pSensorParams->Trigger));
+          status = DTS_ProgramSdaRegister(hdts, (uint32_t) Sensor, DTS_SDATS_CFGR_REG,
+                                          (pSensorParams->Trigger | pSensorParams->Resolution));
+        }
+        else
+        {
+          status = DTS_ProgramSdaRegister(hdts, (uint32_t) Sensor, DTS_SDATS_CFGR_REG, pSensorParams->Resolution);
+        }
+
+        if (status == HAL_OK)
+        {
+          /* Remove potential sensor disabling in TSCSDIFDISABLER register */
+          hdts->Instance->TSCSDIFDISABLER &= (Sensor == DTS_SENSOR_0) ? ~(DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE) :
+                                             ~(DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE);
+
+          /* Update sensor mode */
+          hdts->SensorMode[Sensor] = pSensorParams->Mode;
+        }
+      }
+      else
+      {
+        /* Disable sensor */
+        hdts->Instance->TSCSDIFDISABLER |= (Sensor == DTS_SENSOR_0) ? DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE :
+                                           DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE;
+
+        /* Update sensor mode */
+        hdts->SensorMode[Sensor] = DTS_SENSOR_MODE_DISABLE;
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Start temperature measurement on one sensor in polling mode.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts,
+                                HAL_DTS_Sensor     Sensor)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if ((temp_state == HAL_DTS_STATE_READY) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_1) && (Sensor == DTS_SENSOR_0)) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_0) && (Sensor == DTS_SENSOR_1)))
+    {
+      /* Check sensor mode */
+      if (hdts->SensorMode[Sensor] == DTS_SENSOR_MODE_DISABLE)
+      {
+        hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_SENSOR_MODE;
+        status = HAL_ERROR;
+      }
+      else
+      {
+        DTS_SensorTypeDef *psensor;
+
+        psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+        /* Reset min and max measured values for this sensor */
+        psensor->TSHILORESETR = (DTS_TSHILORESETR_SMPL_LO_SET | DTS_TSHILORESETR_SMPL_HI_CLR);
+
+        /* Start sensor with associated mode */
+        status = DTS_ProgramSdaRegister(hdts, (uint32_t) Sensor, DTS_SDATS_CR_REG, hdts->SensorMode[Sensor]);
+
+        if (status == HAL_OK)
+        {
+          /* Update state */
+          if (hdts->State == HAL_DTS_STATE_READY)
+          {
+            hdts->State = (Sensor == DTS_SENSOR_0) ? HAL_DTS_STATE_RUNNING_0 : HAL_DTS_STATE_RUNNING_1;
+          }
+          else
+          {
+            hdts->State = HAL_DTS_STATE_RUNNING_BOTH;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Poll for available temperature measurement on one sensor.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @param  Timeout Timeout value in milliseconds.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_PollForTemperature(DTS_HandleTypeDef *hdts,
+                                             HAL_DTS_Sensor     Sensor,
+                                             uint32_t           Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if ((temp_state == HAL_DTS_STATE_RUNNING_BOTH) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_0) && (Sensor == DTS_SENSOR_0)) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_1) && (Sensor == DTS_SENSOR_1)))
+    {
+      uint32_t tickstart = HAL_GetTick();
+      const DTS_SensorTypeDef *psensor;
+
+      psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+      /* Wait for available temperature measurement */
+      while (((psensor->TSSDIFDONER & DTS_TSSDIFDONER_SDIF_SMPL_DONE) != DTS_TSSDIFDONER_SDIF_SMPL_DONE) &&
+             (status == HAL_OK))
+      {
+        /* Check the timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            status = HAL_TIMEOUT;
+          }
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        if (hdts->SensorMode[Sensor] == DTS_SENSOR_MODE_SINGLE)
+        {
+          if (hdts->State == HAL_DTS_STATE_RUNNING_BOTH)
+          {
+            hdts->State = (Sensor == DTS_SENSOR_0) ? HAL_DTS_STATE_RUNNING_1 : HAL_DTS_STATE_RUNNING_0;
+          }
+          else
+          {
+            hdts->State = HAL_DTS_STATE_READY;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Get temperature measurement on one sensor.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @param  pTemperature Pointer to temperature in celsius degree.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts,
+                                         HAL_DTS_Sensor     Sensor,
+                                         float_t           *pTemperature)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pTemperature == NULL)
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if (hdts->State != HAL_DTS_STATE_RESET)
+    {
+      const DTS_SensorTypeDef *psensor;
+      uint32_t sample;
+
+      psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+      /* Get sample */
+      sample = psensor->TSSDIFDATAR;
+
+      /* Check if sample is valid */
+      if ((sample & (DTS_TSSDIFDATAR_SAMPLE_TYPE | DTS_TSSDIFDATAR_SAMPLE_FAULT)) == 0U)
+      {
+        /* Convert sample in celsius degree */
+        *pTemperature = DTS_ConvertToCelsiusDegree((sample & DTS_TSSDIFDATAR_SAMPLE_DATA_Msk));
+      }
+      else
+      {
+        /* Invalid sample or fault*/
+        if ((sample & DTS_TSSDIFDATAR_SAMPLE_TYPE) != 0U)
+        {
+          hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_SAMPLE;
+        }
+        else
+        {
+          hdts->ErrorCode |= HAL_DTS_ERROR_FAULT;
+        }
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop temperature measurement on one sensor in polling mode.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts,
+                               HAL_DTS_Sensor     Sensor)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if ((temp_state == HAL_DTS_STATE_RUNNING_BOTH) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_0) && (Sensor == DTS_SENSOR_0)) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_1) && (Sensor == DTS_SENSOR_1)))
+    {
+      /* Power down sensor */
+      status = DTS_ProgramSdaRegister(hdts, (uint32_t) Sensor, DTS_SDATS_CR_REG, DTS_SDA_SENSOR_POWER_DOWN);
+
+      if (status == HAL_OK)
+      {
+        /* Update state */
+        if (hdts->State == HAL_DTS_STATE_RUNNING_BOTH)
+        {
+          hdts->State = (Sensor == DTS_SENSOR_0) ? HAL_DTS_STATE_RUNNING_1 : HAL_DTS_STATE_RUNNING_0;
+        }
+        else
+        {
+          hdts->State = HAL_DTS_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Start temperature measurement on one sensor in interrupt mode.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts,
+                                   HAL_DTS_Sensor     Sensor)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if ((temp_state == HAL_DTS_STATE_READY) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_1) && (Sensor == DTS_SENSOR_0)) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_0) && (Sensor == DTS_SENSOR_1)))
+    {
+      /* Check sensor mode */
+      if (hdts->SensorMode[Sensor] == DTS_SENSOR_MODE_DISABLE)
+      {
+        hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_SENSOR_MODE;
+        status = HAL_ERROR;
+      }
+      else
+      {
+        DTS_SensorTypeDef *psensor;
+
+        psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+        /* Enable sample done and fault interrupts */
+        psensor->TS_IER |= (DTS_TS_IER_IRQ_EN_FAULT | DTS_TS_IER_IRQ_EN_DONE);
+
+        /* Reset min and max measured values for this sensor */
+        psensor->TSHILORESETR = (DTS_TSHILORESETR_SMPL_LO_SET | DTS_TSHILORESETR_SMPL_HI_CLR);
+
+        /* Start sensor with associated mode */
+        status = DTS_ProgramSdaRegister(hdts, (uint32_t) Sensor, DTS_SDATS_CR_REG, hdts->SensorMode[Sensor]);
+
+        if (status == HAL_OK)
+        {
+          /* Update state */
+          if (hdts->State == HAL_DTS_STATE_READY)
+          {
+            hdts->State = (Sensor == DTS_SENSOR_0) ? HAL_DTS_STATE_RUNNING_0 : HAL_DTS_STATE_RUNNING_1;
+          }
+          else
+          {
+            hdts->State = HAL_DTS_STATE_RUNNING_BOTH;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop temperature measurement on one sensor in interrupt mode.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts,
+                                  HAL_DTS_Sensor     Sensor)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    const HAL_DTS_StateTypeDef temp_state = hdts->State;
+
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if ((temp_state == HAL_DTS_STATE_RUNNING_BOTH) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_0) && (Sensor == DTS_SENSOR_0)) ||
+        ((temp_state == HAL_DTS_STATE_RUNNING_1) && (Sensor == DTS_SENSOR_1)))
+    {
+      DTS_SensorTypeDef *psensor;
+
+      psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+      /* Power down sensor */
+      status = DTS_ProgramSdaRegister(hdts, (uint32_t) Sensor, DTS_SDATS_CR_REG, DTS_SDA_SENSOR_POWER_DOWN);
+
+      if (status == HAL_OK)
+      {
+        /* Disable sample done and fault interrupts */
+        psensor->TS_IER &= ~(DTS_TS_IER_IRQ_EN_FAULT | DTS_TS_IER_IRQ_EN_DONE);
+
+        /* Clear potential sample done and fault interrupt flags */
+        psensor->TS_ICR |= (DTS_TS_ICR_IRQ_CLEAR_FAULT | DTS_TS_ICR_IRQ_CLEAR_DONE);
+
+        /* Update state */
+        if (hdts->State == HAL_DTS_STATE_RUNNING_BOTH)
+        {
+          hdts->State = (Sensor == DTS_SENSOR_0) ? HAL_DTS_STATE_RUNNING_1 : HAL_DTS_STATE_RUNNING_0;
+        }
+        else
+        {
+          hdts->State = HAL_DTS_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  DTS temperature callback.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval None.
+  */
+__weak void HAL_DTS_TemperatureCallback(DTS_HandleTypeDef *hdts,
+                                        HAL_DTS_Sensor     Sensor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdts);
+  UNUSED(Sensor);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DTS_TemperatureCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  Get extreme temperatures on one sensor.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @param  pMin Pointer to minimum temperature in celsius degree.
+  * @param  pMax Pointer to maximum temperature in celsius degree.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_GetExtremeTemperatures(DTS_HandleTypeDef *hdts,
+                                                 HAL_DTS_Sensor     Sensor,
+                                                 float_t           *pMin,
+                                                 float_t           *pMax)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if ((pMin == NULL) || (pMax == NULL))
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if (hdts->State != HAL_DTS_STATE_RESET)
+    {
+      const DTS_SensorTypeDef *psensor;
+      uint32_t sample;
+
+      psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+      /* Get min and max samples then convert it */
+      sample = psensor->TSHLSAMPLER;
+      *pMin = DTS_ConvertToCelsiusDegree((sample & DTS_TSHLSAMPLER_SMPL_LO_Msk));
+      *pMax = DTS_ConvertToCelsiusDegree((sample & DTS_TSHLSAMPLER_SMPL_HI_Msk) >> DTS_TSHLSAMPLER_SMPL_HI_Pos);
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure sample counter.
+  * @param  hdts DTS handle.
+  * @param  Enable Enable sample counter.
+  * @param  Clear Clear sample counter.
+  * @param  Hold Set sample counter on hold.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_ConfigSampleCounter(DTS_HandleTypeDef *hdts,
+                                              FunctionalState    Enable,
+                                              FunctionalState    Clear,
+                                              FunctionalState    Hold)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if (hdts->State != HAL_DTS_STATE_RESET)
+    {
+      /* Enable or disable sample counter */
+      if (Enable == ENABLE)
+      {
+        hdts->Instance->TSCSMPL_CR &= ~(DTS_TSCSMPL_CR_SMPL_CTR_DISABLE);
+      }
+      else
+      {
+        hdts->Instance->TSCSMPL_CR |= DTS_TSCSMPL_CR_SMPL_CTR_DISABLE;
+      }
+
+      /* Clear sample counter */
+      if (Clear == ENABLE)
+      {
+        hdts->Instance->TSCSDIFSMPLCLRR |= DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR;
+      }
+
+      /* Configure hold status for sample counter */
+      if (Hold == ENABLE)
+      {
+        hdts->Instance->TSCSMPL_CR |= DTS_TSCSMPL_CR_SMPL_CTR_HOLD;
+      }
+      else
+      {
+        hdts->Instance->TSCSMPL_CR &= ~(DTS_TSCSMPL_CR_SMPL_CTR_HOLD);
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Get sample counter value.
+  * @param  hdts DTS handle.
+  * @param  pNumber Pointer to sample counter value.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_GetSampleCounterValue(DTS_HandleTypeDef *hdts,
+                                                uint32_t          *pNumber)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pNumber == NULL)
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+
+    /* Check current state */
+    if (hdts->State != HAL_DTS_STATE_RESET)
+    {
+      /* Get sample counter value */
+      *pNumber = hdts->Instance->TSCSMPLCNTR;
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure sample discard.
+  * @param  hdts DTS handle.
+  * @param  Status Enable or disable.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_ConfigSampleDiscard(DTS_HandleTypeDef *hdts,
+                                              FunctionalState    Status)
+{
+  HAL_StatusTypeDef retVal = HAL_OK;
+
+  /* Check parameter */
+  if (hdts == NULL)
+  {
+    retVal = HAL_ERROR;
+  }
+  else
+  {
+    /* Check current state */
+    if (hdts->State != HAL_DTS_STATE_RESET)
+    {
+      /* Configure sample discard */
+      if (Status == ENABLE)
+      {
+        hdts->Instance->TSCSMPL_CR |= DTS_TSCSMPL_CR_SMPL_DISCARD;
+      }
+      else
+      {
+        hdts->Instance->TSCSMPL_CR &= ~(DTS_TSCSMPL_CR_SMPL_DISCARD);
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      retVal = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return retVal;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DTS_Exported_Functions_Group3  Alarm functions
+  * @brief    Alarm functions
+  *
+@verbatim
+  ==============================================================================
+                       ##### Alarms functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Configure alarms.
+      (+) Manage alarm callbacks.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure alarmA for one sensor.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @param  pAlarmParams Pointer to alarm parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_ConfigAlarmA(DTS_HandleTypeDef            *hdts,
+                                       HAL_DTS_Sensor                Sensor,
+                                       const DTS_AlarmConfigTypeDef *pAlarmParams)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pAlarmParams == NULL)
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+    assert_param(IS_FUNCTIONAL_STATE(pAlarmParams->Enable));
+
+    /* Check current state */
+    if (hdts->State == HAL_DTS_STATE_READY)
+    {
+      uint32_t alarmThreshold;
+      uint32_t alarmHysteresis;
+      DTS_SensorTypeDef *psensor;
+
+      psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+      /* Configure alarm A */
+      if (pAlarmParams->Enable == ENABLE)
+      {
+        /* Check threshold and hysteresis parameters */
+        assert_param(IS_DTS_ALARM_PARAM(pAlarmParams->Threshold));
+        assert_param(IS_DTS_ALARM_PARAM(pAlarmParams->Hysteresis));
+
+        /* Convert threshold and hysteresis from celsius degree  and store it on DTS register */
+        alarmThreshold = DTS_ConvertFromCelsiusDegree(pAlarmParams->Threshold);
+        alarmHysteresis = DTS_ConvertFromCelsiusDegree(pAlarmParams->Hysteresis);
+        psensor->TSALARMA_CFGR = (alarmThreshold << DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos) |
+                                 (alarmHysteresis << DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos);
+
+        /* Enable alarm A interrupt */
+        psensor->TS_IER |= DTS_TS_IER_IRQ_EN_ALARMA;
+      }
+      else
+      {
+        /* Disable alarm A interrupt */
+        psensor->TS_IER &= ~(DTS_TS_IER_IRQ_EN_ALARMA);
+
+        /* Clear potential alarm A pending flag */
+        psensor->TS_ICR |= DTS_TS_ICR_IRQ_CLEAR_ALARMA;
+
+        /* Disable alarm A */
+        psensor->TSALARMA_CFGR = 0U;
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure alarmB for one sensor.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @param  pAlarmParams Pointer to alarm parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_ConfigAlarmB(DTS_HandleTypeDef            *hdts,
+                                       HAL_DTS_Sensor                Sensor,
+                                       const DTS_AlarmConfigTypeDef *pAlarmParams)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (hdts == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pAlarmParams == NULL)
+  {
+    hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameter */
+    assert_param(IS_DTS_ALL_INSTANCE(hdts->Instance));
+    assert_param(IS_FUNCTIONAL_STATE(pAlarmParams->Enable));
+
+    /* Check current state */
+    if (hdts->State == HAL_DTS_STATE_READY)
+    {
+      uint32_t alarmThreshold;
+      uint32_t alarmHysteresis;
+      DTS_SensorTypeDef *psensor;
+
+      psensor = (Sensor == DTS_SENSOR_0) ? DTS_Sensor0 : DTS_Sensor1;
+
+      /* Configure alarm B */
+      if (pAlarmParams->Enable == ENABLE)
+      {
+        /* Check threshold and hysteresis parameters */
+        assert_param(IS_DTS_ALARM_PARAM(pAlarmParams->Threshold));
+        assert_param(IS_DTS_ALARM_PARAM(pAlarmParams->Hysteresis));
+
+        /* Convert threshold and hysteresis from celsius degree and store it on DTS register */
+        alarmThreshold = DTS_ConvertFromCelsiusDegree(pAlarmParams->Threshold);
+        alarmHysteresis = DTS_ConvertFromCelsiusDegree(pAlarmParams->Hysteresis);
+        psensor->TSALARMB_CFGR = (alarmThreshold << DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos) |
+                                 (alarmHysteresis << DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos);
+
+        /* Enable alarm B interrupt */
+        psensor->TS_IER |= DTS_TS_IER_IRQ_EN_ALARMB;
+      }
+      else
+      {
+        /* Disable alarm B interrupt */
+        psensor->TS_IER &= ~(DTS_TS_IER_IRQ_EN_ALARMB);
+
+        /* Clear potential alarm B pending flag */
+        psensor->TS_ICR |= DTS_TS_ICR_IRQ_CLEAR_ALARMB;
+
+        /* Disable alarm A */
+        psensor->TSALARMB_CFGR = 0U;
+      }
+    }
+    else
+    {
+      /* function call in wrong state */
+      hdts->ErrorCode |= HAL_DTS_ERROR_INVALID_STATE;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  DTS alarm A callback.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval None.
+  */
+__weak void HAL_DTS_AlarmACallback(DTS_HandleTypeDef *hdts,
+                                   HAL_DTS_Sensor     Sensor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdts);
+  UNUSED(Sensor);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DTS_AlarmACallback could be implemented in the user file */
+}
+
+/**
+  * @brief  DTS alarm B callback.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval None.
+  */
+__weak void HAL_DTS_AlarmBCallback(DTS_HandleTypeDef *hdts,
+                                   HAL_DTS_Sensor     Sensor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdts);
+  UNUSED(Sensor);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DTS_AlarmBCallback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DTS_Exported_Functions_Group4  Generic functions
+  * @brief    Generic functions
+  *
+@verbatim
+  ==============================================================================
+                       ##### Generic functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Handle DTS interrupt.
+      (+) Inform user that error occurs.
+      (+) Get the current DTS instance state.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle DTS interrupts.
+  * @param  hdts DTS handle.
+  * @retval None.
+  */
+void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts)
+{
+  DTS_SensorTypeDef *psensor;
+  HAL_DTS_Sensor Sensor;
+  uint32_t tmp_reg1;
+  uint32_t tmp_reg2;
+  uint32_t interrupts;
+
+  /* Check on which sensor interrupt occurs */
+  if ((hdts->Instance->TS_ISR & DTS_TS_ISR_TS0_IRQ_STATUS) == DTS_TS_ISR_TS0_IRQ_STATUS)
+  {
+    psensor = DTS_Sensor0;
+    Sensor = DTS_SENSOR_0;
+  }
+  else
+  {
+    psensor = DTS_Sensor1;
+    Sensor = DTS_SENSOR_1;
+  }
+
+  /* Read current flags and interrupts on sensor */
+  tmp_reg1 = psensor->TS_IER;
+  tmp_reg2 = psensor->TS_ISR;
+  interrupts = (tmp_reg1 & tmp_reg2);
+
+  /* Check if sample done occurs */
+  if ((interrupts & DTS_TS_ISR_IRQ_STATUS_DONE) == DTS_TS_ISR_IRQ_STATUS_DONE)
+  {
+    /* Clear corresponding flag */
+    psensor->TS_ICR |= DTS_TS_ICR_IRQ_CLEAR_DONE;
+
+    /* Call temperature callback */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+    hdts->TemperatureCallback(hdts, Sensor);
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+    HAL_DTS_TemperatureCallback(hdts, Sensor);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
+    /* Update state */
+    if (hdts->SensorMode[Sensor] == DTS_SENSOR_MODE_SINGLE)
+    {
+      /* Disable sample done interrupt */
+      psensor->TS_IER &= ~(DTS_TS_IER_IRQ_EN_DONE);
+
+      if (hdts->State == HAL_DTS_STATE_RUNNING_BOTH)
+      {
+        hdts->State = (Sensor == DTS_SENSOR_0) ? HAL_DTS_STATE_RUNNING_1 : HAL_DTS_STATE_RUNNING_0;
+      }
+      else
+      {
+        hdts->State = HAL_DTS_STATE_READY;
+      }
+    }
+  }
+  /* Check if alarm A occurs */
+  if ((interrupts & DTS_TS_ISR_IRQ_STATUS_ALARMA) == DTS_TS_ISR_IRQ_STATUS_ALARMA)
+  {
+    /* Clear corresponding flag */
+    psensor->TS_ICR |= DTS_TS_ICR_IRQ_CLEAR_ALARMA;
+
+    /* Call alarm A callback */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+    hdts->AlarmACallback(hdts, Sensor);
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+    HAL_DTS_AlarmACallback(hdts, Sensor);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+  }
+  /* Check if alarm B occurs */
+  if ((interrupts & DTS_TS_ISR_IRQ_STATUS_ALARMB) == DTS_TS_ISR_IRQ_STATUS_ALARMB)
+  {
+    /* Clear corresponding flag */
+    psensor->TS_ICR |= DTS_TS_ICR_IRQ_CLEAR_ALARMB;
+
+    /* Call alarm B callback */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+    hdts->AlarmBCallback(hdts, Sensor);
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+    HAL_DTS_AlarmBCallback(hdts, Sensor);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+  }
+  /* Check if fault occurs */
+  if ((interrupts & DTS_TS_ISR_IRQ_STATUS_FAULT) == DTS_TS_ISR_IRQ_STATUS_FAULT)
+  {
+    /* Clear corresponding flag */
+    psensor->TS_ICR |= DTS_TS_ICR_IRQ_CLEAR_FAULT;
+
+    /* Update error code */
+    hdts->ErrorCode |= HAL_DTS_ERROR_FAULT;
+
+    /* Call error callback */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+    hdts->ErrorCallback(hdts, Sensor);
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
+    HAL_DTS_ErrorCallback(hdts, Sensor);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  DTS error callback.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @retval None.
+  */
+__weak void HAL_DTS_ErrorCallback(DTS_HandleTypeDef *hdts,
+                                  HAL_DTS_Sensor     Sensor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdts);
+  UNUSED(Sensor);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_DTS_ErrorCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  Get current DTS handle state.
+  * @param  hdts DTS handle.
+  * @retval DTS state.
+  */
+HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts)
+{
+  /* Return DTS state */
+  return hdts->State;
+}
+
+/**
+  * @brief  Get DTS error code.
+  * @param  hdts DTS handle.
+  * @retval DTS error code.
+  */
+uint32_t HAL_DTS_GetError(const DTS_HandleTypeDef *hdts)
+{
+  return hdts->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+
+/** @addtogroup DTS_Private_Functions
+  * @brief      Private functions
+  * @{
+  */
+
+/**
+  * @brief  Program SDA register.
+  * @param  hdts DTS handle.
+  * @param  Sensor Sensor.
+  *         This parameter can be one of the following values:
+  *           @arg @ref DTS_SENSOR_0 Sensor 0.
+  *           @arg @ref DTS_SENSOR_1 Sensor 1.
+  * @param  Reg SDA register to program.
+  * @param  Value Value to program on SDA register.
+  * @retval HAL status.
+  */
+static HAL_StatusTypeDef DTS_ProgramSdaRegister(DTS_HandleTypeDef *hdts, uint32_t Sensor,
+                                                DTS_SdaRegisterTypeDef Reg, uint32_t Value)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check that serial data interface is not busy */
+  while (((hdts->Instance->TSCSDIF_SR & DTS_TSCSDIF_SR_SDIF_BUSY) != 0U) && (status == HAL_OK))
+  {
+    if ((HAL_GetTick() - tickstart) > DTS_MAXIMUM_TIMEOUT)
+    {
+      status = HAL_TIMEOUT;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    if (Sensor == DTS_SENSOR_ALL)
+    {
+      hdts->Instance->TSCSDIF_CFGR = 0U;
+    }
+    else
+    {
+      /* Inhibit serial programming of other sensor */
+      hdts->Instance->TSCSDIF_CFGR = (Sensor == (uint32_t) DTS_SENSOR_0) ? DTS_TSCSDIF_CFGR_SDIF_INHIBIT_1 :
+                                     DTS_TSCSDIF_CFGR_SDIF_INHIBIT_0;
+    }
+
+    /* program value on SDA register using DTS_TSCSDIF_CR */
+    hdts->Instance->TSCSDIF_CR = (DTS_TSCSDIF_CR_SDIF_PROG | DTS_TSCSDIF_CR_SDIF_WRN | (uint32_t) Reg | Value);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Convert DTS sample to celsius degree.
+  * @param  sample DTS sample.
+  * @retval Temperature in celsius degree.
+  */
+static float_t DTS_ConvertToCelsiusDegree(uint32_t sample)
+{
+  float_t value;
+
+  /* The temperature computation is Temp (celsius degree) = G + (H x Eqbs) + (J x Fclk_ts) */
+  /* where Eqbs is equal to (sample/Cal5) - 0.5 */
+  /* and Fclk_ts is 4MHz */
+
+  /* Computation of Eqbs */
+  value = ((((float_t) sample) / DTS_CAL5_PARAM) - 0.5f);
+
+  /* Computation of temperature */
+  value = DTS_G_PARAM + (DTS_H_PARAM * value) + (DTS_J_PARAM * 4.0f);
+
+  /* Return temperature value */
+  return value;
+}
+
+/**
+  * @brief  Convert DTS sample from celsius degree.
+  * @param  temperature Temperature in celsius degree.
+  * @retval DTS sample.
+  */
+static uint32_t DTS_ConvertFromCelsiusDegree(float_t temperature)
+{
+  float_t value;
+
+  /* The temperature computation is Temp (celsius degree) = G + (H x Eqbs) + (J x Fclk_ts) */
+  /* where Eqbs = (sample/Cal5) - 0.5 */
+  /* and Fclk_ts is 4MHz. */
+  /* So we have sample = (Eqbs + 0.5) x Cal5 */
+  /* and Eqbs = (Temp - G - (J x Fclk_ts)) / H. */
+
+  /* Computation of Eqbs */
+  value = (temperature - DTS_G_PARAM - (DTS_J_PARAM * 4.0f)) / DTS_H_PARAM;
+
+  /* Computation of sample */
+  value = (value + 0.5f) * DTS_CAL5_PARAM;
+
+  /* Return sample value */
+  return (uint32_t) value;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_eth.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_eth.c
new file mode 100644
index 000000000..609118bb6
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_eth.c
@@ -0,0 +1,3601 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_eth.c
+  * @author  MCD Application Team
+  * @brief   ETH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Ethernet (ETH) peripheral:
+  *           + Initialization and deinitialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+     [..]
+     The ETH HAL driver can be used as follows:
+
+      (#)Declare a ETH_HandleTypeDef handle structure, for example:
+         ETH_HandleTypeDef  heth;
+
+      (#)Fill parameters of Init structure in heth handle
+
+      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
+
+      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
+          (##) Enable the Ethernet interface clock using
+                (+++)  __HAL_RCC_ETH1MAC_CLK_ENABLE()
+                (+++)  __HAL_RCC_ETH1TX_CLK_ENABLE()
+                (+++)  __HAL_RCC_ETH1RX_CLK_ENABLE()
+
+          (##) Initialize the related GPIO clocks
+          (##) Configure Ethernet pinout
+          (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
+
+      (#) Ethernet data reception is asynchronous, so call the following API
+          to start the listening mode:
+          (##) HAL_ETH_Start():
+               This API starts the MAC and DMA transmission and reception process,
+               without enabling end of transfer interrupts, in this mode user
+               has to poll for data reception by calling HAL_ETH_ReadData()
+          (##) HAL_ETH_Start_IT():
+               This API starts the MAC and DMA transmission and reception process,
+               end of transfer interrupts are enabled in this mode,
+               HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
+
+      (#) When data is received user can call the following API to get received data:
+          (##) HAL_ETH_ReadData(): Read a received packet
+
+      (#) For transmission path, two APIs are available:
+         (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
+         (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
+              HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
+
+      (#) Communication with an external PHY device:
+         (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
+         (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
+
+      (#) Configure the Ethernet MAC after ETH peripheral initialization
+          (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
+          (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
+
+      (#) Configure the Ethernet DMA after ETH peripheral initialization
+          (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
+          (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
+
+      (#) Configure the Ethernet PTP after ETH peripheral initialization
+          (##) Define HAL_ETH_USE_PTP to use PTP APIs.
+          (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef
+          (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef
+          (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers
+          (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers
+          (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers
+          (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission
+          (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp
+          (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp
+
+      -@- The ARP offload feature is not supported in this driver.
+
+      -@- The PTP offload feature is not supported in this driver.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function HAL_ETH_RegisterCallback() to register an interrupt callback.
+
+  Function HAL_ETH_RegisterCallback() allows to register following callbacks:
+    (+) TxCpltCallback   : Tx Complete Callback.
+    (+) RxCpltCallback   : Rx Complete Callback.
+    (+) ErrorCallback    : Error Callback.
+    (+) PMTCallback      : Power Management Callback
+    (+) EEECallback      : EEE Callback.
+    (+) WakeUpCallback   : Wake UP Callback
+    (+) MspInitCallback  : MspInit Callback.
+    (+) MspDeInitCallback: MspDeInit Callback.
+
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks RxAllocateCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterRxAllocateCallback().
+
+  For specific callbacks RxLinkCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterRxLinkCallback().
+
+  For specific callbacks TxFreeCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterTxFreeCallback().
+
+  For specific callbacks TxPtpCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterTxPtpCallback().
+
+  Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxCpltCallback   : Tx Complete Callback.
+    (+) RxCpltCallback   : Rx Complete Callback.
+    (+) ErrorCallback    : Error Callback.
+    (+) PMTCallback      : Power Management Callback
+    (+) EEECallback      : EEE Callback.
+    (+) WakeUpCallback   : Wake UP Callback
+    (+) MspInitCallback  : MspInit Callback.
+    (+) MspDeInitCallback: MspDeInit Callback.
+
+  For specific callbacks RxAllocateCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterRxAllocateCallback().
+
+  For specific callbacks RxLinkCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterRxLinkCallback().
+
+  For specific callbacks TxFreeCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterTxFreeCallback().
+
+  For specific callbacks TxPtpCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterTxPtpCallback().
+
+  By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
+  all callbacks are set to the corresponding weak functions:
+  examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit
+  or HAL_ETH_Init function.
+
+  When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_ETH_MODULE_ENABLED
+
+#if defined(ETH1)
+
+/** @defgroup ETH ETH
+  * @brief ETH HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup ETH_Private_Constants ETH Private Constants
+  * @{
+  */
+#define ETH_MACCR_MASK                0xFFFBFF7CU
+#define ETH_MACECR_MASK               0x7F073FFFU
+#define ETH_MACPFR_MASK               0x803107FFU
+#define ETH_MACWTR_MASK               0x0000010FU
+#define ETH_MACQ0TXFCR_MASK           0xFFFF00F3U
+#define ETH_MACRXFCR_MASK             0x00000003U
+
+#define ETH_MTLRXQDMAMR_MASK          0x00001111U
+
+#define ETH_MACVTDR_MASK              0x031FFFFFU
+#define ETH_MACVTCR_MASK              0xBF7F000FU
+
+#define ETH_MACRXQCR_MASK             0x00030303U
+#define ETH_MACRXQC0R_MASK            0x0000000FU
+#define ETH_MACRXQC1R_MASK            0x37F77077U
+
+#define ETH_DMAMR_MASK                0x0003091DU
+#define ETH_DMASBMR_MASK              0xC30334FFU
+#define ETH_DMACxCR_MASK              0x001D3FFFU
+#define ETH_MACPCSR_MASK              (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
+                                       ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
+                                       ETH_MACPCSR_RWKPFE)
+
+/* Timeout values */
+#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
+                                                  ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
+                                                  ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
+
+#define ETH_MACTSCR_MASK              0x1107FF2FU
+
+#define ETH_MACSTSUR_VALUE            0xFFFFFFFFU
+#define ETH_MACSTNUR_VALUE            0xBB9ACA00U
+#define ETH_SEGMENT_SIZE_DEFAULT      0x218U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ETH_Private_Macros ETH Private Macros
+  * @{
+  */
+/* Helper macros for TX descriptor handling */
+#define INCR_TX_DESC_INDEX(inx, offset) do {\
+                                             (inx) += (offset);\
+                                             if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
+                                             (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
+                                           } while (0)
+
+/* Helper macros for RX descriptor handling */
+#define INCR_RX_DESC_INDEX(inx, offset) do {\
+                                             (inx) += (offset);\
+                                             if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
+                                             (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
+                                           } while (0)
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ETH_Private_Functions   ETH Private Functions
+  * @{
+  */
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
+                                           uint32_t ItMode);
+static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup ETH_Exported_Functions ETH Exported Functions
+  * @{
+  */
+
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the ETH peripheral:
+
+      (+) User must Implement HAL_ETH_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO and NVIC ).
+
+      (+) Call the function HAL_ETH_Init() to configure the selected device with
+          the selected configuration:
+        (++) MAC address
+        (++) Media interface (MII or RMII)
+        (++) Rx DMA Descriptors Tab
+        (++) Tx DMA Descriptors Tab
+        (++) Length of Rx Buffers
+
+      (+) Call the function HAL_ETH_DeInit() to restore the default configuration
+          of the selected ETH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the Ethernet peripheral registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+  uint32_t tickstart;
+  uint32_t ch;
+
+  if (heth == NULL)
+  {
+    return HAL_ERROR;
+  }
+  if (heth->gState == HAL_ETH_STATE_RESET)
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+    ETH_InitCallbacksToDefault(heth);
+
+    if (heth->MspInitCallback == NULL)
+    {
+      heth->MspInitCallback = HAL_ETH_MspInit;
+    }
+
+    /* Init the low level hardware */
+    heth->MspInitCallback(heth);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+    HAL_ETH_MspInit(heth);
+
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+  }
+
+  if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
+  {
+    SET_BIT(RCC->CCIPR2, RCC_ETH1PHYIF_MII);
+  }
+  else if (heth->Init.MediaInterface == HAL_ETH_RGMII_MODE)
+  {
+    SET_BIT(RCC->CCIPR2, RCC_ETH1PHYIF_RGMII);
+  }
+  else
+  {
+    SET_BIT(RCC->CCIPR2, RCC_ETH1PHYIF_RMII);
+  }
+
+  /* Ethernet Software reset */
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for software reset */
+  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
+  {
+    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
+    {
+      /* Set Error Code */
+      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
+      /* Set State as Error */
+      heth->gState = HAL_ETH_STATE_ERROR;
+      /* Return Error */
+      return HAL_ERROR;
+    }
+  }
+
+  /*------------------ MDIO CSR Clock Range Configuration --------------------*/
+  HAL_ETH_SetMDIOClockRange(heth);
+
+  /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
+  WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
+
+  /*------------------ MAC, MTL and DMA default Configuration ----------------*/
+  ETH_MACDMAConfig(heth);
+
+  /*------------------ DMA Tx Descriptors Configuration ----------------------*/
+  ETH_DMATxDescListInit(heth);
+
+  /*------------------ DMA Rx Descriptors Configuration ----------------------*/
+  ETH_DMARxDescListInit(heth);
+
+  /* Set Receive Buffers Length (must be a multiple of 4) */
+  if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
+  {
+    /* Set Error Code */
+    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+    /* Set State as Error */
+    heth->gState = HAL_ETH_STATE_ERROR;
+    /* Return Error */
+    return HAL_ERROR;
+  }
+  else
+  {
+    for (ch = 0; ch < ETH_DMA_RX_CH_CNT; ch++)
+    {
+      MODIFY_REG(heth->Instance->DMA_CH[ch].DMACRXCR, ETH_DMACxRXCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
+    }
+  }
+  /*--------------------- ETHERNET MAC Address Configuration ------------------*/
+  /* Set MAC addr bits 32 to 47 */
+  heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
+  /* Set MAC addr bits 0 to 31 */
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+
+
+  /* Disable Rx MMC Interrupts */
+  SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
+          ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
+
+  /* Disable Tx MMC Interrupts */
+  SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
+          ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
+
+  heth->ErrorCode = HAL_ETH_ERROR_NONE;
+  heth->gState = HAL_ETH_STATE_READY;
+
+  return HAL_OK;
+}
+/**
+  * @brief  DeInitializes the ETH peripheral.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
+{
+  /* Set the ETH peripheral state to BUSY */
+  heth->gState = HAL_ETH_STATE_BUSY;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+  if (heth->MspDeInitCallback == NULL)
+  {
+    heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  heth->MspDeInitCallback(heth);
+#else
+
+  /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+  HAL_ETH_MspDeInit(heth);
+
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+
+  /* Set ETH HAL state to Disabled */
+  heth->gState = HAL_ETH_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the ETH MSP.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_MspInit could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  DeInitializes ETH MSP.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_MspDeInit could be implemented in the user file
+  */
+}
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ETH Callback
+  *         To be used instead of the weak predefined callback
+  * @param heth eth handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *          @arg @ref HAL_ETH_ERROR_CB_ID       Error Callback ID
+  *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
+  *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
+  *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
+  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
+  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
+                                           pETH_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_TX_COMPLETE_CB_ID :
+        heth->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_ETH_RX_COMPLETE_CB_ID :
+        heth->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_ETH_ERROR_CB_ID :
+        heth->ErrorCallback = pCallback;
+        break;
+
+      case HAL_ETH_PMT_CB_ID :
+        heth->PMTCallback = pCallback;
+        break;
+
+      case HAL_ETH_EEE_CB_ID :
+        heth->EEECallback = pCallback;
+        break;
+
+      case HAL_ETH_WAKEUP_CB_ID :
+        heth->WakeUpCallback = pCallback;
+        break;
+
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (heth->gState == HAL_ETH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an ETH Callback
+  *         ETH callback is redirected to the weak predefined callback
+  * @param heth eth handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *          @arg @ref HAL_ETH_ERROR_CB_ID       Error Callback ID
+  *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
+  *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
+  *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
+  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
+  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_TX_COMPLETE_CB_ID :
+        heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+        break;
+
+      case HAL_ETH_RX_COMPLETE_CB_ID :
+        heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+        break;
+
+      case HAL_ETH_ERROR_CB_ID :
+        heth->ErrorCallback = HAL_ETH_ErrorCallback;
+        break;
+
+      case HAL_ETH_PMT_CB_ID :
+        heth->PMTCallback = HAL_ETH_PMTCallback;
+        break;
+
+      case HAL_ETH_EEE_CB_ID :
+        heth->EEECallback = HAL_ETH_EEECallback;
+        break;
+
+      case HAL_ETH_WAKEUP_CB_ID :
+        heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
+        break;
+
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = HAL_ETH_MspInit;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (heth->gState == HAL_ETH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = HAL_ETH_MspInit;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
+  *  @brief ETH Transmit and Receive functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the ETH
+    data transfer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables Ethernet MAC and DMA reception and transmission
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
+{
+  uint32_t ch;
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    /* Set number of descriptors to build */
+    for (ch = 0; ch < ETH_DMA_CH_CNT; ch++)
+    {
+      heth->RxOpCH = ch;
+      heth->RxDescList[ch].RxBuildDescCnt = ETH_RX_DESC_CNT;
+      /* Build all descriptors */
+      ETH_UpdateDescriptor(heth);
+    }
+
+    /* Reset Rx Operation Channel to 0 */
+    heth->RxOpCH = 0;
+
+    for (ch = 0; ch < ETH_MTL_TX_Q_CNT; ch++)
+    {
+      /* Set the Flush Transmit FIFO bit */
+      SET_BIT(heth->Instance->MTL_QUEUE[ch].MTLTXQOMR, ETH_MTLTXQxOMR_FTQ);
+      /* Enable the DMA transmission */
+      SET_BIT(heth->Instance->DMA_CH[ch].DMACTXCR, ETH_DMACxTXCR_ST);
+      /* Enable the DMA reception */
+      SET_BIT(heth->Instance->DMA_CH[ch].DMACRXCR, ETH_DMACxRXCR_SR);
+      /* Clear Tx and Rx process stopped flags */
+      heth->Instance->DMA_CH[ch].DMACSR |= (ETH_DMACxSR_TPS | ETH_DMACxSR_RPS);
+    }
+
+    /* Enable the MAC transmission */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+    heth->gState = HAL_ETH_STATE_STARTED;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
+{
+  uint32_t ch;
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    /* save IT mode to ETH Handle */
+    for (ch = 0; ch < ETH_DMA_CH_CNT; ch++)
+    {
+      /* Set the DMA channel to configure */
+      heth->RxOpCH = ch;
+      heth->RxDescList[ch].ItMode = 1U;
+      /* Set number of descriptors to build */
+      heth->RxDescList[ch].RxBuildDescCnt = ETH_RX_DESC_CNT;
+      /* Build all descriptors */
+      ETH_UpdateDescriptor(heth);
+
+      /* Enable ETH DMA interrupts:
+      - Tx complete interrupt
+      - Rx complete interrupt
+      - Fatal bus interrupt
+      */
+      __HAL_ETH_DMA_CH_ENABLE_IT(heth, (ETH_DMACxIER_NIE | ETH_DMACxIER_RIE | ETH_DMACxIER_TIE  |
+                                        ETH_DMACxIER_FBEE | ETH_DMACxIER_AIE | ETH_DMACxIER_RBUE), ch);
+      /* Enable the DMA reception */
+      SET_BIT(heth->Instance->DMA_CH[ch].DMACRXCR, ETH_DMACxRXCR_SR);
+      /* Clear Tx and Rx process stopped flags */
+      heth->Instance->DMA_CH[ch].DMACSR |= (ETH_DMACxSR_TPS | ETH_DMACxSR_RPS);
+      /* Set the Flush Transmit FIFO bit */
+      SET_BIT(heth->Instance->MTL_QUEUE[ch].MTLTXQOMR, ETH_MTLTXQxOMR_FTQ);
+      /* Enable the DMA transmission */
+      SET_BIT(heth->Instance->DMA_CH[ch].DMACTXCR, ETH_DMACxTXCR_ST);
+    }
+
+    /* Reset Rx Operation Channel to 0 */
+    heth->RxOpCH = 0;
+
+    /* Enable the MAC transmission */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+    heth->gState = HAL_ETH_STATE_STARTED;
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop Ethernet MAC and DMA reception/transmission
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
+{
+  uint32_t ch;
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    /* Set the ETH peripheral state to BUSY */
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    for (ch = 0; ch < ETH_MTL_TX_Q_CNT; ch++)
+    {
+      /* Disable the DMA transmission */
+      CLEAR_BIT(heth->Instance->DMA_CH[ch].DMACTXCR, ETH_DMACxTXCR_ST);
+      /* Disable the DMA reception */
+      CLEAR_BIT(heth->Instance->DMA_CH[ch].DMACRXCR, ETH_DMACxRXCR_SR);
+      /* Set the Flush Transmit FIFO bit */
+      SET_BIT(heth->Instance->MTL_QUEUE[ch].MTLTXQOMR, ETH_MTLTXQxOMR_FTQ);
+    }
+
+    /* Disable the MAC reception */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+    /* Disable the MAC transmission */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    heth->gState = HAL_ETH_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
+{
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t descindex;
+  uint32_t ch;
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    /* Set the ETH peripheral state to BUSY */
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    /* Disable interrupts:
+    - Tx complete interrupt
+    - Rx complete interrupt
+    - Fatal bus interrupt
+    */
+
+    for (ch = 0; ch < ETH_MTL_TX_Q_CNT; ch++)
+    {
+      __HAL_ETH_DMA_CH_DISABLE_IT(heth, (ETH_DMACxIER_NIE | ETH_DMACxIER_RIE | ETH_DMACxIER_TIE  |
+                                         ETH_DMACxIER_FBEE | ETH_DMACxIER_AIE | ETH_DMACxIER_RBUE), ch);
+
+      /* Disable the DMA transmission */
+      CLEAR_BIT(heth->Instance->DMA_CH[ch].DMACTXCR, ETH_DMACxTXCR_ST);
+
+      /* Disable the DMA reception */
+      CLEAR_BIT(heth->Instance->DMA_CH[ch].DMACRXCR, ETH_DMACxRXCR_SR);
+
+      /* Set the Flush Transmit FIFO bit */
+      SET_BIT(heth->Instance->MTL_QUEUE[ch].MTLTXQOMR, ETH_MTLTXQxOMR_FTQ);
+
+    }
+
+    /* Disable the MAC reception */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+    /* Disable the MAC transmission */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    for (ch = 0; ch < ETH_DMA_CH_CNT; ch++)
+    {
+      /* Clear IOC bit to all Ch0 Rx descriptors */
+      for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+      {
+        dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList[ch].RxDesc[descindex];
+        CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+        heth->RxDescList[ch].ItMode = 0U;
+      }
+    }
+
+    heth->gState = HAL_ETH_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sends an Ethernet Packet in polling mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pTxConfig: Hold the configuration of packet to be transmitted
+  * @param  Timeout: timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
+{
+  uint32_t ch;
+  uint32_t tickstart;
+  ETH_DMADescTypeDef *dmatxdesc;
+
+  if (pTxConfig == NULL)
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    ch = pTxConfig->TxDMACh;
+
+    /* Config DMA Tx descriptor by Tx Packet info */
+    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
+    {
+      /* Set the ETH error code */
+      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
+      return HAL_ERROR;
+    }
+
+    /* Ensure completion of descriptor preparation before transmission start */
+    __DSB();
+
+    dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList[ch])->
+                TxDesc[heth->TxDescList[ch].CurTxDesc];
+
+    /* Incr current tx desc index */
+    INCR_TX_DESC_INDEX(heth->TxDescList[ch].CurTxDesc, 1U);
+
+    /* Start transmission */
+    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACTXDTPR,
+              (uint32_t)(heth->TxDescList[ch].TxDesc[heth->TxDescList[ch].CurTxDesc]));
+
+    tickstart = HAL_GetTick();
+
+    /* Wait for data to be transmitted or timeout occurred */
+    while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
+    {
+      if ((heth->Instance->DMA_CH[ch].DMACSR & ETH_DMACxSR_FBE) != (uint32_t)RESET)
+      {
+        heth->ErrorCode |= (uint32_t)HAL_ETH_ERROR_DMA;
+        heth->DMAErrorCode = heth->Instance->DMA_CH[ch].DMACSR;
+        /* Return function status */
+        return HAL_ERROR;
+      }
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
+          /* Clear TX descriptor so that we can proceed */
+          dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sends an Ethernet Packet in interrupt mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pTxConfig: Hold the configuration of packet to be transmitted
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
+{
+  uint32_t ch;
+
+  if (pTxConfig == NULL)
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    ch = pTxConfig->TxDMACh;
+
+    /* Save the packet pointer to release.  */
+    heth->TxDescList[ch].CurrentPacketAddress = (uint32_t *)pTxConfig->pData;
+
+    /* Config DMA Tx descriptor by Tx Packet info */
+    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
+    {
+      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
+      return HAL_ERROR;
+    }
+
+    /* Incr current tx desc for Ch index */
+    INCR_TX_DESC_INDEX(heth->TxDescList[ch].CurTxDesc, 1U);
+
+    /* Ensure completion of descriptor preparation before transmission start */
+    __DSB();
+
+    /* Start transmission */
+    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACTXDTPR,
+              (uint32_t)(heth->TxDescList[ch].TxDesc[heth->TxDescList[ch].CurTxDesc]));
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Read a received packet.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pAppBuff: Pointer to an application buffer to receive the packet.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
+{
+  uint32_t ch = heth->RxOpCH;
+  uint32_t descidx;
+  uint32_t descidx_next;
+  ETH_DMADescTypeDef *dmarxdesc;
+  ETH_DMADescTypeDef *dmarxdesc_next;
+  uint32_t desccnt = 0U;
+  uint32_t desccntmax;
+  uint32_t bufflength;
+  uint8_t rxdataready = 0U;
+
+  if (pAppBuff == NULL)
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (heth->gState != HAL_ETH_STATE_STARTED)
+  {
+    return HAL_ERROR;
+  }
+
+  descidx = heth->RxDescList[ch].RxDescIdx;
+  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList[ch].RxDesc[descidx];
+  desccntmax = ETH_RX_DESC_CNT - heth->RxDescList[ch].RxBuildDescCnt;
+
+  /* Check if descriptor is not owned by DMA */
+  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
+         && (rxdataready == 0U))
+  {
+    if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) ||
+        (heth->RxDescList[ch].pRxStart != NULL))
+    {
+      /* Check if first descriptor */
+      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
+      {
+        heth->RxDescList[ch].RxDescCnt = 0;
+        heth->RxDescList[ch].RxDataLength = 0;
+      }
+
+      /* Get the Frame Length of the received packet */
+      bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList[ch].RxDataLength;
+
+      /* Check if last descriptor */
+      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
+      {
+        /* Save Last descriptor index */
+        heth->RxDescList[ch].pRxLastRxDesc = dmarxdesc->DESC3;
+
+        /* Packet ready */
+        rxdataready = 1;
+
+        if (READ_BIT(dmarxdesc->DESC1, ETH_DMARXNDESCWBF_TSA) != (uint32_t)RESET)
+        {
+          descidx_next = descidx;
+          INCR_RX_DESC_INDEX(descidx_next, 1U);
+
+          dmarxdesc_next = (ETH_DMADescTypeDef *)heth->RxDescList[ch].RxDesc[descidx_next];
+
+          if (READ_BIT(dmarxdesc_next->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
+          {
+            /* Get timestamp high */
+            heth->RxDescList[ch].TimeStamp.TimeStampHigh = dmarxdesc_next->DESC1;
+            /* Get timestamp low */
+            heth->RxDescList[ch].TimeStamp.TimeStampLow  = dmarxdesc_next->DESC0;
+          }
+        }
+      }
+
+      /* Link data */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Link callback*/
+      heth->rxLinkCallback(&heth->RxDescList[ch].pRxStart, &heth->RxDescList[ch].pRxEnd,
+                           (uint8_t *)dmarxdesc->BackupAddr0, bufflength);
+#else
+      /* Link callback */
+      HAL_ETH_RxLinkCallback(&heth->RxDescList[ch].pRxStart, &heth->RxDescList[ch].pRxEnd,
+                             (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+      heth->RxDescList[ch].RxDescCnt++;
+      heth->RxDescList[ch].RxDataLength += bufflength;
+
+      /* Clear buffer pointer */
+      dmarxdesc->BackupAddr0 = 0;
+    }
+
+    /* Increment current rx descriptor index */
+    INCR_RX_DESC_INDEX(descidx, 1U);
+    /* Get current descriptor address */
+    dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList[ch].RxDesc[descidx];
+    desccnt++;
+  }
+
+  heth->RxDescList[ch].RxBuildDescCnt += desccnt;
+  if ((heth->RxDescList[ch].RxBuildDescCnt) != 0U)
+  {
+    /* Update Descriptors */
+    ETH_UpdateDescriptor(heth);
+  }
+
+  heth->RxDescList[ch].RxDescIdx = descidx;
+
+  if (rxdataready == 1U)
+  {
+    /* Return received packet */
+    *pAppBuff = heth->RxDescList[ch].pRxStart;
+    /* Reset first element */
+    heth->RxDescList[ch].pRxStart = NULL;
+
+    return HAL_OK;
+  }
+
+  /* Packet not ready */
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  This function gives back Rx Desc of the last received Packet
+  *         to the DMA, so ETH DMA will be able to use these descriptors
+  *         to receive next Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
+{
+  uint32_t ch = heth -> RxOpCH;
+  uint32_t descidx;
+  uint32_t tailidx;
+  uint32_t desccount;
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint8_t *buff = NULL;
+  uint8_t allocStatus = 1U;
+
+  descidx = heth->RxDescList[ch].RxBuildDescIdx;
+  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList[ch].RxDesc[descidx];
+  desccount = heth->RxDescList[ch].RxBuildDescCnt;
+
+  while ((desccount > 0U) && (allocStatus != 0U))
+  {
+    /* Check if a buffer's attached the descriptor */
+    if (READ_REG(dmarxdesc->BackupAddr0) == 0U)
+    {
+      /* Get a new buffer. */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Allocate callback*/
+      heth->rxAllocateCallback(&buff);
+#else
+      /* Allocate callback */
+      HAL_ETH_RxAllocateCallback(&buff);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+      if (buff == NULL)
+      {
+        allocStatus = 0U;
+      }
+      else
+      {
+        WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff);
+        WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff);
+      }
+    }
+    else
+    {
+      /* Descriptor was used as a context descriptor, buffer still unused */
+      WRITE_REG(dmarxdesc->DESC0, (uint32_t)dmarxdesc->BackupAddr0);
+    }
+
+    if (allocStatus != 0U)
+    {
+
+      if (heth->RxDescList[ch].ItMode != 0U)
+      {
+        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC);
+      }
+      else
+      {
+        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V);
+      }
+
+      /* Increment current rx descriptor index */
+      INCR_RX_DESC_INDEX(descidx, 1U);
+      /* Get current descriptor address */
+      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList[ch].RxDesc[descidx];
+      desccount--;
+    }
+  }
+
+  if (heth->RxDescList[ch].RxBuildDescCnt != desccount)
+  {
+    /* Set the tail pointer index */
+    tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT;
+
+    /* DMB instruction to avoid race condition */
+    __DMB();
+
+    /* Set the Tail pointer address */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACRXDTPR, ((uint32_t)(heth->Init.RxDesc[ch] + (tailidx))));
+
+    heth->RxDescList[ch].RxBuildDescIdx = descidx;
+    heth->RxDescList[ch].RxBuildDescCnt = desccount;
+  }
+}
+
+/**
+  * @brief  Register the Rx alloc callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  rxAllocateCallback: pointer to function to alloc buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
+                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback)
+{
+  if (rxAllocateCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+
+  /* Set function to allocate buffer */
+  heth->rxAllocateCallback = rxAllocateCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unregister the Rx alloc callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth)
+{
+  /* Set function to allocate buffer */
+  heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Rx Allocate callback.
+  * @param  buff: pointer to allocated buffer
+  * @retval None
+  */
+__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(buff);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_RxAllocateCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Rx Link callback.
+  * @param  pStart: pointer to packet start
+  * @param  pEnd: pointer to packet end
+  * @param  buff: pointer to received data
+  * @param  Length: received data length
+  * @retval None
+  */
+__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(pStart);
+  UNUSED(pEnd);
+  UNUSED(buff);
+  UNUSED(Length);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_RxLinkCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Set the Rx link data function.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  rxLinkCallback: pointer to function to link data
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback)
+{
+  if (rxLinkCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+
+  /* Set function to link data */
+  heth->rxLinkCallback = rxLinkCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unregister the Rx link callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
+{
+  /* Set function to allocate buffer */
+  heth->rxLinkCallback = HAL_ETH_RxLinkCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the error state of the last received packet.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pErrorCode: pointer to uint32_t to hold the error code
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
+{
+  uint32_t ch = heth->RxOpCH;
+  /* Get error bits. */
+  *pErrorCode = READ_BIT(heth->RxDescList[ch].pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Tx free function.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  txFreeCallback: pointer to function to release the packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback)
+{
+  if (txFreeCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+
+  /* Set function to free transmmitted packet */
+  heth->txFreeCallback = txFreeCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unregister the Tx free callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth)
+{
+  /* Set function to allocate buffer */
+  heth->txFreeCallback = HAL_ETH_TxFreeCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Tx Free callback.
+  * @param  buff: pointer to buffer to free
+  * @retval None
+  */
+__weak void HAL_ETH_TxFreeCallback(uint32_t *buff)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(buff);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxFreeCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Release transmitted Tx packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
+{
+  uint32_t ch = heth->TxOpCH;
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList[ch];
+  uint32_t numOfBuf =  dmatxdesclist->BuffersInUse;
+  uint32_t idx =       dmatxdesclist->releaseIndex;
+  uint8_t pktTxStatus = 1U;
+  uint8_t pktInUse;
+#ifdef HAL_ETH_USE_PTP
+  ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp;
+#endif /* HAL_ETH_USE_PTP */
+
+  /* Loop through buffers in use.  */
+  while ((numOfBuf != 0U) && (pktTxStatus != 0U))
+  {
+    pktInUse = 1U;
+    numOfBuf--;
+    /* If no packet, just examine the next packet.  */
+    if (dmatxdesclist->PacketAddress[idx] == NULL)
+    {
+      /* No packet in use, skip to next.  */
+      INCR_TX_DESC_INDEX(idx, 1U);
+      pktInUse = 0U;
+    }
+
+    if (pktInUse != 0U)
+    {
+      /* Determine if the packet has been transmitted.  */
+      if ((heth->Init.TxDesc[ch][idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U)
+      {
+#ifdef HAL_ETH_USE_PTP
+        /* Disable Ptp transmission */
+        CLEAR_BIT(heth->Init.TxDesc[ch][idx].DESC2, ETH_DMATXNDESCRF_TTSE);
+
+        if ((heth->Init.TxDesc[ch][idx].DESC3 & ETH_DMATXNDESCWBF_LD)
+            && (heth->Init.TxDesc[ch][idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
+        {
+          /* Get timestamp low */
+          timestamp->TimeStampLow = heth->Init.TxDesc[ch][idx].DESC0;
+          /* Get timestamp high */
+          timestamp->TimeStampHigh = heth->Init.TxDesc[ch][idx].DESC1;
+        }
+        else
+        {
+          timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX;
+        }
+
+#endif /* HAL_ETH_USE_PTP */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+        /*Call registered callbacks*/
+#ifdef HAL_ETH_USE_PTP
+        /* Handle Ptp  */
+        if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
+        {
+          heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
+        }
+#endif  /* HAL_ETH_USE_PTP */
+        /* Release the packet.  */
+        heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
+#else
+        /* Call callbacks */
+#ifdef HAL_ETH_USE_PTP
+        /* Handle Ptp  */
+        if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
+        {
+          HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
+        }
+#endif  /* HAL_ETH_USE_PTP */
+        /* Release the packet.  */
+        HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+        /* Clear the entry in the in-use array.  */
+        dmatxdesclist->PacketAddress[idx] = NULL;
+
+        /* Update the transmit relesae index and number of buffers in use.  */
+        INCR_TX_DESC_INDEX(idx, 1U);
+        dmatxdesclist->BuffersInUse = numOfBuf;
+        dmatxdesclist->releaseIndex = idx;
+      }
+      else
+      {
+        /* Get out of the loop!  */
+        pktTxStatus = 0U;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  Set the Ethernet PTP configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
+  *         the configuration information for PTP
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
+{
+  uint32_t tmpTSCR;
+  ETH_TimeTypeDef time;
+
+  if (ptpconfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Mask the Timestamp Trigger interrupt */
+  CLEAR_BIT(heth->Instance->MACIER, ETH_MACIER_TSIE);
+
+  tmpTSCR = ((uint32_t)ptpconfig->AV8021ASMEN << ETH_MACTSCR_AV8021ASMEN_Pos) |
+            ((uint32_t)ptpconfig->Timestamp << ETH_MACTSCR_TSENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) |
+            ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) |
+            ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_MACTSCR_TSCTRLSSR_Pos) |
+            ((uint32_t)ptpconfig->TimestampV2 << ETH_MACTSCR_TSVER2ENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampEthernet << ETH_MACTSCR_TSIPENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampIPv6 << ETH_MACTSCR_TSIPV6ENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampIPv4 << ETH_MACTSCR_TSIPV4ENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampEvent << ETH_MACTSCR_TSEVNTENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) |
+            (uint32_t)ptpconfig->TimestampSnapshots |
+            ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) |
+            ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos) |
+            ((uint32_t)ptpconfig->TimestampUpdateMode);
+
+  /* Write to MACTSCR */
+  MODIFY_REG(heth->Instance->MACTSCR, ETH_MACTSCR_MASK, tmpTSCR);
+
+  /* Enable Timestamp */
+  SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA);
+  WRITE_REG(heth->Instance->MACSSIR, ptpconfig->TimestampSubsecondInc);
+  WRITE_REG(heth->Instance->MACTSAR, ptpconfig->TimestampAddend);
+
+  /* Enable Timestamp */
+  if (ptpconfig->TimestampAddendUpdate == ENABLE)
+  {
+    SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG);
+    while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0)
+    {
+
+    }
+  }
+
+  /* Set PTP Configuration done */
+  heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
+
+  /* Set Seconds */
+  time.Seconds = heth->Instance->MACSTSR;
+  /* Set NanoSeconds */
+  time.NanoSeconds = heth->Instance->MACSTNR;
+
+  HAL_ETH_PTP_SetTime(heth, &time);
+
+  /* Ptp Init */
+  SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the Ethernet PTP configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
+  *         the configuration information for PTP
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
+{
+  if (ptpconfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+  ptpconfig->AV8021ASMEN = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_AV8021ASMEN) >>
+                             ETH_MACTSCR_AV8021ASMEN_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->Timestamp = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA) >>
+                           ETH_MACTSCR_TSENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT) >>
+                                 ETH_MACTSCR_TSUPDT_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENALL) >>
+                              ETH_MACTSCR_TSENALL_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) >>
+                                       ETH_MACTSCR_TSCTRLSSR_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSVER2ENA) >>
+                             ETH_MACTSCR_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSIPENA) >>
+                                   ETH_MACTSCR_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSIPV6ENA) >>
+                               ETH_MACTSCR_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSIPV4ENA) >>
+                               ETH_MACTSCR_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSEVNTENA) >>
+                                ETH_MACTSCR_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSMSTRENA) >>
+                                 ETH_MACTSCR_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampSnapshots = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_SNAPTYPSEL) >>
+                                    ETH_MACTSCR_SNAPTYPSEL_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENMACADDR) >>
+                                 ETH_MACTSCR_TSENMACADDR_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TXTSSTSM) >>
+                                     ETH_MACTSCR_TXTSSTSM_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampExternalSystemTime = ((READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_ESTI) >>
+                                             ETH_MACTSCR_ESTI_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampAddend = READ_BIT(heth->Instance->MACTSAR, ETH_MACTSAR_TSAR);
+  ptpconfig->TimestampSubsecondInc = READ_BIT(heth->Instance->MACSSIR, ETH_MACSTSR_TSS);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Seconds and Nanoseconds for the Ethernet PTP registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  time: pointer to a ETH_TimeTypeDef structure that contains
+  *         time to set
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
+{
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Set Seconds */
+    heth->Instance->MACSTSUR = time->Seconds;
+
+    /* Set NanoSeconds */
+    heth->Instance->MACSTNUR = time->NanoSeconds;
+
+    /* the system time is updated */
+    SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Seconds and Nanoseconds for the Ethernet PTP registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  time: pointer to a ETH_TimeTypeDef structure that contains
+  *         time to get
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
+{
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Get Seconds */
+    time->Seconds = heth->Instance->MACSTSR;
+    /* Get NanoSeconds */
+    time->NanoSeconds = heth->Instance->MACSTNR;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Update time for the Ethernet PTP registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
+  *         the time update information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
+                                            ETH_TimeTypeDef *timeoffset)
+{
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    if (ptpoffsettype ==  HAL_ETH_PTP_NEGATIVE_UPDATE)
+    {
+      /* Set Seconds update */
+      heth->Instance->MACSTSUR = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U;
+
+      if (READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) == ETH_MACTSCR_TSCTRLSSR)
+      {
+        /* Set nanoSeconds update */
+        heth->Instance->MACSTNUR = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds;
+      }
+      else
+      {
+        /* Set nanoSeconds update */
+        heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U;
+      }
+    }
+    else
+    {
+      /* Set Seconds update */
+      heth->Instance->MACSTSUR = timeoffset->Seconds;
+      /* Set nanoSeconds update */
+      heth->Instance->MACSTNUR = timeoffset->NanoSeconds;
+    }
+
+    SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Insert Timestamp in transmission.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
+{
+  uint32_t ch = heth->TxOpCH;
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList[ch];
+  uint32_t descidx = dmatxdesclist->CurTxDesc;
+  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Enable Time Stamp transmission */
+    SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get transmission timestamp.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
+  *         transmission timestamp
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
+{
+  uint32_t ch = heth->TxOpCH;
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList[ch];
+  uint32_t idx =       dmatxdesclist->releaseIndex;
+  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
+
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Get timestamp low */
+    timestamp->TimeStampLow = dmatxdesc->DESC0;
+    /* Get timestamp high */
+    timestamp->TimeStampHigh = dmatxdesc->DESC1;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get receive timestamp.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
+  *         receive timestamp
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
+{
+  uint32_t ch = heth->RxOpCH;
+
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Get timestamp low */
+    timestamp->TimeStampLow = heth->RxDescList[ch].TimeStamp.TimeStampLow;
+    /* Get timestamp high */
+    timestamp->TimeStampHigh = heth->RxDescList[ch].TimeStamp.TimeStampHigh;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Register the Tx Ptp callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  txPtpCallback: Function to handle Ptp transmission
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback)
+{
+  if (txPtpCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+  /* Set Function to handle Tx Ptp */
+  heth->txPtpCallback = txPtpCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unregister the Tx Ptp callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
+{
+  /* Set function to allocate buffer */
+  heth->txPtpCallback = HAL_ETH_TxPtpCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Tx Ptp callback.
+  * @param  buff: pointer to application buffer
+  * @param  timestamp: pointer to ETH_TimeStampTypeDef structure that contains
+  *         transmission timestamp
+  * @retval None
+  */
+__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(buff);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxPtpCallback could be implemented in the user file
+  */
+}
+#endif  /* HAL_ETH_USE_PTP */
+
+/**
+  * @brief  This function handles ETH interrupt request.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+  uint32_t mac_flag = READ_REG(heth->Instance->MACISR);
+
+  uint32_t dma_ch0_flag = READ_REG(heth->Instance->DMA_CH[ETH_DMA_CH0_IDX].DMACSR);
+  uint32_t dma_ch1_flag = READ_REG(heth->Instance->DMA_CH[ETH_DMA_CH1_IDX].DMACSR);
+  uint32_t dma_ch0_itsource = READ_REG(heth->Instance->DMA_CH[ETH_DMA_CH0_IDX].DMACIER);
+  uint32_t dma_ch1_itsource = READ_REG(heth->Instance->DMA_CH[ETH_DMA_CH1_IDX].DMACIER);
+
+  uint32_t exti_flag = READ_REG(EXTI->IMR2);
+
+  /* Packet received in DMA Channel 0 */
+  if (((dma_ch0_flag & ETH_DMACxSR_RI) != 0U) && ((dma_ch0_itsource & ETH_DMACxIER_RIE) != 0U))
+  {
+    /* Clear the Eth DMA Rx IT pending bits */
+    __HAL_ETH_DMA_CH_CLEAR_IT(heth, ETH_DMACxSR_RI | ETH_DMACxSR_NIS, ETH_DMA_CH0_IDX);
+
+    /* Set RxCH ETH_DMA_CH0 event*/
+    SET_BIT(heth->RxCH, ETH_DMA_CH0);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Receive complete callback*/
+    heth->RxCpltCallback(heth);
+#else
+    /* Receive complete callback */
+    HAL_ETH_RxCpltCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    /* Clear RX ETH_DMA_CH0 event */
+    CLEAR_BIT(heth->RxCH, ETH_DMA_CH0);
+  }
+
+  /* Packet received in DMA Channel 1 */
+  if (((dma_ch1_flag & ETH_DMACxSR_RI) != 0U) && ((dma_ch1_itsource & ETH_DMACxIER_RIE) != 0U))
+  {
+    /* Clear the Eth DMA Rx IT pending bits */
+    __HAL_ETH_DMA_CH_CLEAR_IT(heth, ETH_DMACxSR_RI | ETH_DMACxSR_NIS, ETH_DMA_CH1_IDX);
+
+    /* Set RxCH ETH_DMA_CH1 event*/
+    SET_BIT(heth->RxCH, ETH_DMA_CH1);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Receive complete callback*/
+    heth->RxCpltCallback(heth);
+#else
+    /* Receive complete callback */
+    HAL_ETH_RxCpltCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    /* Clear RX ETH_DMA_CH1 event */
+    CLEAR_BIT(heth->RxCH, ETH_DMA_CH1);
+  }
+
+  /* Packet transmitted by DMA Channel 0 */
+  if (((dma_ch0_flag & ETH_DMACxSR_TI) != 0U) && ((dma_ch0_itsource & ETH_DMACxIER_TIE) != 0U))
+  {
+    /* Clear the Eth DMA Tx IT pending bits */
+    __HAL_ETH_DMA_CH_CLEAR_IT(heth, ETH_DMACxSR_TI | ETH_DMACxSR_NIS, ETH_DMA_CH0_IDX);
+
+    /* Set TxCH ETH_DMA_CH0 event*/
+    SET_BIT(heth->TxCH, ETH_DMA_CH0);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Transmit complete callback*/
+    heth->TxCpltCallback(heth);
+#else
+    /* Transfer complete callback */
+    HAL_ETH_TxCpltCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    /* Clear TX ETH_DMA_CH0 event */
+    CLEAR_BIT(heth->TxCH, ETH_DMA_CH0);
+  }
+
+  /* Packet transmitted by DMA Channel 1 */
+  if (((dma_ch1_flag & ETH_DMACxSR_TI) != 0U) && ((dma_ch1_itsource & ETH_DMACxIER_TIE) != 0U))
+  {
+    /* Clear the Eth DMA Tx IT pending bits */
+    __HAL_ETH_DMA_CH_CLEAR_IT(heth, ETH_DMACxSR_TI | ETH_DMACxSR_NIS, ETH_DMA_CH1_IDX);
+
+    /* Set TxCH ETH_DMA_CH1 event*/
+    SET_BIT(heth->TxCH, ETH_DMA_CH1);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Transmit complete callback*/
+    heth->TxCpltCallback(heth);
+#else
+    /* Transfer complete callback */
+    HAL_ETH_TxCpltCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    /* Clear TX ETH_DMA_CH1 event */
+    CLEAR_BIT(heth->TxCH, ETH_DMA_CH1);
+  }
+
+  /* ETH DMA Channel 0 Error */
+  if (((dma_ch0_flag & ETH_DMACxSR_AIS) != 0U) && ((dma_ch0_itsource & ETH_DMACxIER_AIE) != 0U))
+  {
+    heth->ErrorCode |= (uint32_t)HAL_ETH_ERROR_DMA_CH0;
+    /* if fatal bus error occurred */
+    if ((dma_ch0_flag & ETH_DMACxSR_FBE) != 0U)
+    {
+      /* Get DMA error code  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMA_CH[ETH_DMA_CH0_IDX].DMACSR,
+                                    (ETH_DMACxSR_FBE | ETH_DMACxSR_TPS | ETH_DMACxSR_RPS));
+      /* Disable all interrupts */
+      __HAL_ETH_DMA_CH_DISABLE_IT(heth, ETH_DMACxIER_NIE | ETH_DMACxIER_AIE, ETH_DMA_CH0_IDX);
+
+      /* Set HAL state to ERROR */
+      heth->gState = HAL_ETH_STATE_ERROR;
+    }
+    else
+    {
+      /* Get DMA error status  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMA_CH[ETH_DMA_CH0_IDX].DMACSR,
+                                    (ETH_DMACxSR_CDE | ETH_DMACxSR_ETI | ETH_DMACxSR_RWT |
+                                     ETH_DMACxSR_RBU | ETH_DMACxSR_AIS));
+
+      /* Clear the interrupt summary flag */
+      __HAL_ETH_DMA_CH_CLEAR_IT(heth, (ETH_DMACxSR_CDE | ETH_DMACxSR_ETI | ETH_DMACxSR_RWT |
+                                       ETH_DMACxSR_RBU | ETH_DMACxSR_AIS), ETH_DMA_CH0_IDX);
+    }
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
+#else
+    /* Ethernet DMA Error callback */
+    HAL_ETH_ErrorCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+
+  /* ETH DMA Channel 1 Error */
+  if (((dma_ch1_flag & ETH_DMACxSR_AIS) != 0U) && ((dma_ch1_itsource & ETH_DMACxIER_AIE) != 0U))
+  {
+    heth->ErrorCode |= (uint32_t)HAL_ETH_ERROR_DMA_CH1;
+    /* if fatal bus error occurred */
+    if ((dma_ch1_flag & ETH_DMACxSR_FBE) != 0U)
+    {
+      /* Get DMA error code  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMA_CH[ETH_DMA_CH1_IDX].DMACSR,
+                                    (ETH_DMACxSR_FBE | ETH_DMACxSR_TPS | ETH_DMACxSR_RPS));
+      /* Disable all interrupts */
+      __HAL_ETH_DMA_CH_DISABLE_IT(heth, ETH_DMACxIER_NIE | ETH_DMACxIER_AIE, ETH_DMA_CH1_IDX);
+
+      /* Set HAL state to ERROR */
+      heth->gState = HAL_ETH_STATE_ERROR;
+    }
+    else
+    {
+      /* Get DMA error status  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMA_CH[ETH_DMA_CH1_IDX].DMACSR,
+                                    (ETH_DMACxSR_CDE | ETH_DMACxSR_ETI | ETH_DMACxSR_RWT |
+                                     ETH_DMACxSR_RBU | ETH_DMACxSR_AIS));
+
+      /* Clear the interrupt summary flag */
+      __HAL_ETH_DMA_CH_CLEAR_IT(heth, (ETH_DMACxSR_CDE | ETH_DMACxSR_ETI | ETH_DMACxSR_RWT |
+                                       ETH_DMACxSR_RBU | ETH_DMACxSR_AIS), ETH_DMA_CH1_IDX);
+    }
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
+#else
+    /* Ethernet DMA Error callback */
+    HAL_ETH_ErrorCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+
+  /* ETH MAC Error IT */
+  if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+      ((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_MAC;
+
+    /* Get MAC Rx Tx status and clear Status register pending bit */
+    heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
+
+    heth->gState = HAL_ETH_STATE_ERROR;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
+#else
+    /* Ethernet Error callback */
+    HAL_ETH_ErrorCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+    heth->MACErrorCode = (uint32_t)(0x0U);
+  }
+
+  /* ETH PMT IT */
+  if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
+  {
+    /* Get MAC Wake-up source and clear the status register pending bit */
+    heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered PMT callback*/
+    heth->PMTCallback(heth);
+#else
+    /* Ethernet PMT callback */
+    HAL_ETH_PMTCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACWakeUpEvent = (uint32_t)(0x0U);
+  }
+
+  /* ETH EEE IT */
+  if ((mac_flag & ETH_MAC_LPI_IT) != 0U)
+  {
+    /* Get MAC LPI interrupt source and clear the status register pending bit */
+    heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered EEE callback*/
+    heth->EEECallback(heth);
+#else
+    /* Ethernet EEE callback */
+    HAL_ETH_EEECallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACLPIEvent = (uint32_t)(0x0U);
+  }
+
+  /* check ETH WAKEUP exti flag */
+  if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
+  {
+    /* Clear ETH WAKEUP Exti pending bit */
+    __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered WakeUp callback*/
+    heth->WakeUpCallback(heth);
+#else
+    /* ETH WAKEUP callback */
+    HAL_ETH_WakeUpCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_RxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Ethernet transfer error callbacks
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_ErrorCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Ethernet Power Management module IT callback
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_PMTCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Energy Efficient Etherent IT callback
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_EEECallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  ETH WAKEUP interrupt callback
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ETH_WakeUpCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Read a PHY register
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  PHYAddr: PHY port address, must be a value from 0 to 31
+  * @param  PHYReg: PHY register address, must be a value from 0 to 31
+  * @param pRegValue: parameter to hold read value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                          uint32_t *pRegValue)
+{
+  uint32_t tickstart;
+  uint32_t tmpreg;
+
+  /* Check for the Busy flag */
+  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_GB) != (uint32_t)RESET)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the  MACMDIOAR value */
+  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+
+  /* Prepare the MDIO Address Register value
+     - Set the PHY device address
+     - Set the PHY register address
+     - Set the read mode
+     - Set the MII Busy bit */
+
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_GOC, (ETH_MACMDIOAR_GOC_1 | ETH_MACMDIOAR_GOC_0));
+  SET_BIT(tmpreg, ETH_MACMDIOAR_GB);
+
+  /* Write the result value into the MDII Address register */
+  WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait for the Busy flag */
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_GB) > 0U)
+  {
+    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /* Get MACMIIDR value */
+  WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes to a PHY register.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  PHYAddr: PHY port address, must be a value from 0 to 31
+  * @param  PHYReg: PHY register address, must be a value from 0 to 31
+  * @param  RegValue: the value to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                           uint32_t RegValue)
+{
+  uint32_t tickstart;
+  uint32_t tmpreg;
+
+  /* Check for the Busy flag */
+  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_GB) != (uint32_t)RESET)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the  MACMDIOAR value */
+  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+
+  /* Prepare the MDIO Address Register value
+     - Set the PHY device address
+     - Set the PHY register address
+     - Set the write mode
+     - Set the MII Busy bit */
+
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_GOC, ETH_MACMDIOAR_GOC_0);
+  SET_BIT(tmpreg, ETH_MACMDIOAR_GB);
+
+  /* Give the value to the MII data register */
+  WRITE_REG(heth->Instance->MACMDIODR, (uint16_t)RegValue);
+
+  /* Write the result value into the MII Address register */
+  WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait for the Busy flag */
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_GB) > 0U)
+  {
+    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   ETH control functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the ETH
+    peripheral.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Get the configuration of the MAC and MTL subsystems.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
+  *         the configuration of the MAC.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+{
+  if (macconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get MAC parameters */
+  macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
+  macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE;
+  macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
+  macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
+  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR,
+                                                   ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
+  macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
+  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
+                                                   ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
+  macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
+  macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
+  macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
+  macconf->PortSelect = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_PS) >> 15) > 0U) ? ENABLE : DISABLE;
+  macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
+  macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE;
+  macconf->PacketBurst = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_PB) >> 18) > 0U) ? ENABLE : DISABLE;
+  macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE;
+  macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
+  macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
+  macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
+  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
+                                                    ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
+  macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
+  macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
+  macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
+  macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
+  macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR,
+                                             ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
+  macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
+  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
+                                                        ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
+  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR,
+                                               ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
+  macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
+  macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
+  macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
+  macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACQ0TXFCR,
+                                            ETH_MACQ0TXFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
+  macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACQ0TXFCR,
+                                        ETH_MACQ0TXFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
+  macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACQ0TXFCR, ETH_MACQ0TXFCR_PLT);
+  macconf->PauseTime = (READ_BIT(heth->Instance->MACQ0TXFCR, ETH_MACQ0TXFCR_PT) >> 16);
+  macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRXFCR, ETH_MACRXFCR_RFE) > 0U) ? ENABLE : DISABLE;
+  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRXFCR,
+                                                 ETH_MACRXFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the configuration of the DMA.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
+  *         the configuration of the ETH DMA.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+{
+  uint32_t ch;
+
+  if (dmaconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
+  dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB);
+  dmaconf->RxOSRLimit = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RD_OSR_LMT_1 | ETH_DMASBMR_RD_OSR_LMT_0);
+  dmaconf->TxOSRLimit = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_WR_OSR_LMT_1 | ETH_DMASBMR_WR_OSR_LMT_0);
+  dmaconf->TransmitArbitrationAlgorithm = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TAA_WRR | ETH_DMAMR_TAA_WSP));
+  dmaconf->TransmitPriority = ((READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_TXPR) >> 11) > 0U) ? ENABLE : DISABLE;
+  dmaconf->AXIBLENMaxSize = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_BLEN256 | ETH_DMASBMR_BLEN128 |
+                                     ETH_DMASBMR_BLEN64 | ETH_DMASBMR_BLEN32 |
+                                     ETH_DMASBMR_BLEN16 | ETH_DMASBMR_BLEN8 | ETH_DMASBMR_BLEN4);
+
+  for (ch = 0; ch < ETH_DMA_CH_CNT; ch++)
+  {
+    dmaconf->DMACh[ch].RxDMABurstLength = READ_BIT(heth->Instance->DMA_CH[ch].DMACRXCR, ETH_DMACxRXCR_RXPBL);
+    dmaconf->DMACh[ch].SecondPacketOperate = ((READ_BIT(heth->Instance->DMA_CH[ch].DMACTXCR,
+                                                        ETH_DMACxTXCR_OSF) >> 4) > 0U) ? ENABLE : DISABLE;
+    dmaconf->DMACh[ch].TCPSegmentation = ((READ_BIT(heth->Instance->DMA_CH[ch].DMACTXCR,
+                                                    ETH_DMACxTXCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
+    dmaconf->DMACh[ch].TxDMABurstLength = READ_BIT(heth->Instance->DMA_CH[ch].DMACTXCR, ETH_DMACxTXCR_TXPBL);
+    dmaconf->DMACh[ch].DescriptorSkipLength = READ_BIT(heth->Instance->DMA_CH[ch].DMACCR, ETH_DMACxCR_DSL);
+    dmaconf->DMACh[ch].PBLx8Mode = ((READ_BIT(heth->Instance->DMA_CH[ch].DMACCR,
+                                              ETH_DMACxCR_PBLX8) >> 16) > 0U) ? ENABLE : DISABLE;
+    dmaconf->DMACh[ch].FlushRxPacket = ((READ_BIT(heth->Instance->DMA_CH[ch].DMACRXCR,
+                                                  ETH_DMACxRXCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
+    dmaconf->DMACh[ch].MaximumSegmentSize = READ_BIT(heth->Instance->DMA_CH[ch].DMACCR, ETH_DMACxCR_MSS);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the MAC configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that contains
+  *         the configuration of the MAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
+{
+  if (macconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    ETH_SetMACConfig(heth, macconf);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Set the ETH DMA configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
+  *         the configuration of the ETH DMA.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
+{
+  if (dmaconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    ETH_SetDMAConfig(heth, dmaconf);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configures the Clock range of ETH MDIO interface.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
+{
+  uint32_t hclk;
+  uint32_t tmpreg;
+
+  /* Get the ETHERNET MACMDIOAR value */
+  tmpreg = (heth->Instance)->MACMDIOAR;
+
+  /* Clear CSR Clock Range bits */
+  tmpreg &= ~ETH_MACMDIOAR_CR;
+
+  /* Get hclk frequency value */
+  hclk = HAL_RCC_GetHCLKFreq();
+
+  /* Set CR bits depending on hclk value */
+  if (hclk < 35000000U)
+  {
+    /* CSR Clock Range between 0-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
+  }
+  else if (hclk < 60000000U)
+  {
+    /* CSR Clock Range between 35-60 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
+  }
+  else if (hclk < 100000000U)
+  {
+    /* CSR Clock Range between 60-100 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+  }
+  else if (hclk < 150000000U)
+  {
+    /* CSR Clock Range between 100-150 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
+  }
+  else if (hclk < 250000000U)
+  {
+    /* CSR Clock Range between 150-250 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
+  }
+  else if (hclk < 300000000U)
+  {
+    /* CSR Clock Range between 250-300 MHz */
+    tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124);
+  }
+  else if (hclk < 500000000U)
+  {
+    /* CSR Clock Range between 300-500 MHz */
+    tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV204);
+  }
+  else /* (hclk >= 500000000U)  */
+  {
+    /* CSR Clock >= 500 MHz */
+    tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV324);
+  }
+
+  /* Configure the CSR Clock Range */
+  (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
+}
+
+/**
+  * @brief  Set the ETH MAC (L2) Filters configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
+  *         the configuration of the ETH MAC filters.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
+{
+  uint32_t filterconfig;
+
+  if (pFilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
+                  ((uint32_t)pFilterConfig->HashUnicast << 1) |
+                  ((uint32_t)pFilterConfig->HashMulticast << 2)  |
+                  ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
+                  ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
+                  ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) |
+                  ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
+                  ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
+                  ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
+                  ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
+                  pFilterConfig->ControlPacketsFilter);
+
+  MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the ETH MAC (L2) Filters configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
+  *         the configuration of the ETH MAC filters.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+{
+  if (pFilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
+                                                       ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
+  pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
+                                                      ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U)
+                                       ? ENABLE : DISABLE;
+  pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the source MAC Address to be matched.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  AddrNbr: The MAC address to configure
+  *          This parameter must be a value of the following:
+  *            ETH_MAC_ADDRESS1
+  *            ETH_MAC_ADDRESS2
+  *            ETH_MAC_ADDRESS3
+  * @param  pMACAddr: Pointer to MAC address buffer data (6 bytes)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
+                                                const uint8_t *pMACAddr)
+{
+  uint32_t macaddrlr;
+  uint32_t macaddrhr;
+
+  if (pMACAddr == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get mac addr high reg offset */
+  macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr);
+  /* Get mac addr low reg offset */
+  macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr);
+
+  /* Set MAC addr bits 32 to 47 */
+  (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
+  /* Set MAC addr bits 0 to 31 */
+  (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
+                                   ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
+
+  /* Enable address and set source address bit */
+  (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAxHR_SA | ETH_MACAxHR_AE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the ETH Hash Table Value.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pHashTable: pointer to a table of two 32 bit values, that contains
+  *         the 64 bits of the hash table.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
+{
+  if (pHashTable == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  heth->Instance->MACHT0R = pHashTable[0];
+  heth->Instance->MACHT1R = pHashTable[1];
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Identifier for Rx packets
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  ComparisonBits: 12 or 16 bit comparison mode
+            must be a value of @ref ETH_VLAN_Tag_Comparison
+  * @param  VLANIdentifier: VLAN Identifier value
+  * @retval None
+  */
+void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
+{
+  if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
+  {
+    MODIFY_REG(heth->Instance->MACVTDR, ETH_MACVTDR_VID_16BIT, VLANIdentifier);
+    CLEAR_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_ETV);
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->MACVTDR, ETH_MACVTDR_VID_12BIT, VLANIdentifier);
+    SET_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_ETV);
+  }
+}
+
+/**
+  * @brief  Enters the Power down mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
+  *         that contains the Power Down configuration
+  * @retval None.
+  */
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
+{
+  uint32_t powerdownconfig;
+
+  powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
+                     ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
+                     ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
+                     ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
+                     ETH_MACPCSR_PWRDWN);
+
+  /* Enable PMT interrupt */
+  __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
+
+  MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
+}
+
+/**
+  * @brief  Exits from the Power down mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
+{
+  /* clear wake up sources */
+  CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST |
+            ETH_MACPCSR_RWKPFE);
+
+  if (READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != (uint32_t)RESET)
+  {
+    /* Exit power down mode */
+    CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
+  }
+
+  /* Disable PMT interrupt */
+  __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
+}
+
+/**
+  * @brief  Set the WakeUp filter.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pFilter: pointer to filter registers values
+  * @param  Count: number of filter registers, must be from 1 to 8.
+  * @retval None.
+  */
+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
+{
+  uint32_t regindex;
+
+  if (pFilter == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Reset Filter Pointer */
+  SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
+
+  /* Wake up packet filter config */
+  for (regindex = 0; regindex < Count; regindex++)
+  {
+    /* Write filter regs */
+    WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   ETH State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Peripheral State and Errors functions #####
+  ==============================================================================
+ [..]
+   This subsection provides a set of functions allowing to return the State of
+   ETH communication process, return Peripheral Errors occurred during communication
+   process
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the ETH state.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL state
+  */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
+{
+  return heth->gState;
+}
+
+/**
+  * @brief  Returns the ETH error code
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH Error Code
+  */
+uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
+{
+  return heth->ErrorCode;
+}
+
+/**
+  * @brief  Returns the ETH DMA error code
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH DMA Error Code
+  */
+uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
+{
+  return heth->DMAErrorCode;
+}
+
+/**
+  * @brief  Returns the ETH MAC error code
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MAC Error Code
+  */
+uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
+{
+  return heth->MACErrorCode;
+}
+
+/**
+  * @brief  Returns the ETH MAC WakeUp event source
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MAC WakeUp event source
+  */
+uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
+{
+  return heth->MACWakeUpEvent;
+}
+
+/**
+  * @brief  Returns the ETH Tx Buffers in use number
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH Tx Buffers in use number
+  */
+uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth)
+{
+  uint32_t ch = heth->TxOpCH;
+
+  return heth->TxDescList[ch].BuffersInUse;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Private_Functions   ETH Private Functions
+  * @{
+  */
+
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
+{
+  uint32_t macregval;
+
+  /*------------------------ MACCR Configuration --------------------*/
+  macregval = (macconf->InterPacketGapVal |
+               macconf->SourceAddrControl |
+               ((uint32_t)macconf->ChecksumOffload << 27) |
+               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+               ((uint32_t)macconf->Support2KPacket  << 22) |
+               ((uint32_t)macconf->CRCStripTypePacket << 21) |
+               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+               ((uint32_t)macconf->PacketBurst << 18) |
+               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+               ((uint32_t)macconf->JumboPacket << 16) |
+               ((uint32_t)macconf->PortSelect << 15) |
+               macconf->Speed |
+               macconf->DuplexMode |
+               ((uint32_t)macconf->LoopbackMode << 12) |
+               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
+               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
+               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
+               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
+               macconf->BackOffLimit |
+               ((uint32_t)macconf->DeferralCheck << 4) |
+               macconf->PreambleLength);
+
+  /* Write to MACCR */
+  MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
+
+  /*------------------------ MACECR Configuration --------------------*/
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
+               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
+               ((uint32_t)macconf->SlowProtocolDetect << 17) |
+               ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) |
+               macconf->GiantPacketSizeLimit);
+
+  /* Write to MACECR */
+  MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
+
+  /*------------------------ MACWTR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
+               macconf->WatchdogTimeout);
+
+  /* Write to MACWTR */
+  MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
+
+  /*------------------------ MACQ0TXFCR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+               macconf->PauseLowThreshold |
+               ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) |
+               (macconf->PauseTime << 16));
+
+  /* Write to MACQ0TXFCR */
+  MODIFY_REG(heth->Instance->MACQ0TXFCR, ETH_MACQ0TXFCR_MASK, macregval);
+
+  /*------------------------ MACRXFCR Configuration --------------------*/
+  macregval = ((uint32_t)macconf->ReceiveFlowControl |
+               ((uint32_t)macconf->UnicastPausePacketDetect << 1));
+
+  /* Write to MACRXFCR */
+  MODIFY_REG(heth->Instance->MACRXFCR, ETH_MACRXFCR_MASK, macregval);
+
+}
+
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
+{
+  uint32_t dmaregval;
+  uint32_t ch;
+
+  /*------------------------ DMAMR Configuration --------------------*/
+  dmaregval = (dmaconf->TransmitArbitrationAlgorithm |
+               ((uint32_t)dmaconf->TransmitPriority << 11)) ;
+
+  MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaregval);
+
+  /*------------------------ DMASBMR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+               dmaconf->BurstMode  |
+               dmaconf->RxOSRLimit |
+               dmaconf->TxOSRLimit |
+               dmaconf->AXIBLENMaxSize);
+
+  MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
+
+  for (ch = 0; ch < ETH_DMA_CH_CNT; ch++)
+  {
+    /*------------------------ DMACCR Configuration --------------------*/
+    dmaregval = (((uint32_t)(dmaconf->DMACh[ch]).PBLx8Mode << 16)          |
+                 (dmaconf->DMACh[ch]).DescriptorSkipLength      |
+                 (dmaconf->DMACh[ch]).MaximumSegmentSize);
+
+    MODIFY_REG(heth->Instance->DMA_CH[ch].DMACCR, ETH_DMACxCR_MASK, dmaregval);
+
+    /*------------------------ DMACTXCR Configuration --------------------*/
+    dmaregval = (((dmaconf->DMACh[ch]).TxDMABurstLength) |
+                 ((uint32_t)(dmaconf->DMACh[ch]).SecondPacketOperate << 4) |
+                 ((uint32_t)(dmaconf->DMACh[ch]).TCPSegmentation << 12));
+
+    MODIFY_REG(heth->Instance->DMA_CH[ch].DMACTXCR,
+               (ETH_DMACxTXCR_TXPBL_Msk | ETH_DMACxTXCR_OSF_Msk | ETH_DMACxTXCR_TSE_Msk), dmaregval);
+
+    /*------------------------ DMACRXCR Configuration --------------------*/
+    dmaregval = (((uint32_t)(dmaconf->DMACh[ch]).FlushRxPacket  << 31) |
+                 (dmaconf->DMACh[ch]).RxDMABurstLength);
+
+    MODIFY_REG(heth->Instance->DMA_CH[ch].DMACRXCR, (ETH_DMACxRXCR_RXPBL_Msk | ETH_DMACxRXCR_RPF_Msk), dmaregval);
+  }
+
+}
+
+/**
+  * @brief  Configures Ethernet MAC and DMA with default parameters.
+  *         called by HAL_ETH_Init() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
+{
+  ETH_MACConfigTypeDef macDefaultConf = {0};
+  ETH_MTLConfigTypeDef mtlDefaultConf = {0};
+  ETH_DMAConfigTypeDef dmaDefaultConf;
+  uint32_t queue;
+  uint32_t ch;
+
+  /*--------------- ETHERNET MAC registers default Configuration --------------*/
+  macDefaultConf.AutomaticPadCRCStrip = ENABLE;
+  macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
+  macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
+  macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
+  macDefaultConf.ChecksumOffload = ENABLE;
+  macDefaultConf.CRCCheckingRxPackets = ENABLE;
+  macDefaultConf.CRCStripTypePacket = ENABLE;
+  macDefaultConf.DeferralCheck = DISABLE;
+  macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
+  macDefaultConf.ExtendedInterPacketGap = DISABLE;
+  macDefaultConf.ExtendedInterPacketGapVal = 0x0U;
+  macDefaultConf.GiantPacketSizeLimit = 0x618U;
+  macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
+  macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
+  macDefaultConf.Jabber = ENABLE;
+  macDefaultConf.JumboPacket = DISABLE;
+  macDefaultConf.LoopbackMode = DISABLE;
+  macDefaultConf.PacketBurst = DISABLE;
+  if (heth->Init.MediaInterface == HAL_ETH_RGMII_MODE)
+  {
+    macDefaultConf.PortSelect = DISABLE;
+  }
+  else
+  {
+    /* force it for 10/100m */
+    macDefaultConf.PortSelect = ENABLE;
+  }
+  macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
+  macDefaultConf.PauseTime = 0x0U;
+  macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
+  macDefaultConf.ProgrammableWatchdog = DISABLE;
+  macDefaultConf.ReceiveFlowControl = DISABLE;
+  macDefaultConf.ReceiveOwn = ENABLE;
+  macDefaultConf.RetryTransmission = ENABLE;
+  macDefaultConf.SlowProtocolDetect = DISABLE;
+  macDefaultConf.SourceAddrControl = ETH_MACCR_SARC_REPADDR0;
+  macDefaultConf.Speed = ETH_SPEED_1000M;
+  macDefaultConf.Support2KPacket = DISABLE;
+  macDefaultConf.TransmitFlowControl = DISABLE;
+  macDefaultConf.UnicastPausePacketDetect = DISABLE;
+  macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
+  macDefaultConf.Watchdog = ENABLE;
+  macDefaultConf.WatchdogTimeout =  ETH_MACWTR_WTO_2KB;
+  macDefaultConf.ZeroQuantaPause = ENABLE;
+
+  /* MAC default configuration */
+  ETH_SetMACConfig(heth, &macDefaultConf);
+
+  /*--------------- ETHERNET MTL registers default Configuration --------------*/
+  /* Common configuration for Q0 and Q1*/
+  mtlDefaultConf.RxQ[0].MappedToDMACh = ETH_MTL_Q0_MAPPED_TO_DMA_CH0;
+#if ETH_MTL_RX_Q_CNT == 2
+  mtlDefaultConf.RxQ[1].MappedToDMACh = ETH_MTL_Q1_MAPPED_TO_DMA_CH1;
+#endif /* ETH_MTL_TX_Q_CNT == 2 */
+  mtlDefaultConf.ReceiveArbitrationAlgorithm = ETH_MTLOMR_RAA_SP;
+  mtlDefaultConf.TxSchedulingAlgorithm = ETH_MTLOMR_SCHALG_SP;
+  mtlDefaultConf.TransmitStatus = ENABLE;
+
+  /* RxQ & TxQ configuration */
+  mtlDefaultConf.RxQ[0].QueueOpMode = ETH_RX_QUEUE0_ENABLED;
+  mtlDefaultConf.RxQ[1].QueueOpMode = ETH_RX_QUEUE1_ENABLED;
+  mtlDefaultConf.TxQ[1].AVAlgorithm = ETH_TX_QUEUE_AV_ALGO_SP;
+
+  for (queue = 0; queue < ETH_MTL_RX_Q_CNT; queue++)
+  {
+    /* RxQ configuration */
+    mtlDefaultConf.RxQ[queue].DropTCPIPChecksumErrorPacket = ENABLE;
+    mtlDefaultConf.RxQ[queue].ForwardRxErrorPacket = DISABLE;
+    mtlDefaultConf.RxQ[queue].ForwardRxUndersizedGoodPacket = DISABLE;
+    mtlDefaultConf.RxQ[queue].ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
+    mtlDefaultConf.RxQ[queue].RxQueueSize = ETH_RECEIVE_QUEUE_SIZE_4096;
+
+    /* TxQ configuration */
+    mtlDefaultConf.TxQ[queue].TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
+    mtlDefaultConf.TxQ[queue].QueueOpMode = ETH_TX_QUEUE_ENABLED;
+    mtlDefaultConf.TxQ[queue].TxQueueSize = ETH_TRANSMIT_QUEUE_SIZE_2048;
+  }
+
+  /* MTL default configuration */
+  ETHEx_SetMTLConfig(heth, &mtlDefaultConf);
+
+  /*--------------- ETHERNET DMA registers default Configuration --------------*/
+  /* Common DMA configuration */
+  dmaDefaultConf.AddressAlignedBeats = ENABLE;
+  dmaDefaultConf.AXIBLENMaxSize = ETH_BLEN_MAX_SIZE_4;
+  dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
+  dmaDefaultConf.RxOSRLimit = ETH_RX_OSR_LIMIT_3;
+  dmaDefaultConf.TxOSRLimit = ETH_TX_OSR_LIMIT_3;
+  dmaDefaultConf.TransmitArbitrationAlgorithm = ETH_DMATXARBITRATION_FIXED_PRIO;
+  dmaDefaultConf.TransmitPriority = DISABLE;
+
+  for (ch = 0; ch < ETH_DMA_CH_CNT; ch++)
+  {
+    /* DMA CH configuration */
+    dmaDefaultConf.DMACh[ch].FlushRxPacket = DISABLE;
+    dmaDefaultConf.DMACh[ch].PBLx8Mode = DISABLE;
+    dmaDefaultConf.DMACh[ch].RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+    dmaDefaultConf.DMACh[ch].SecondPacketOperate = DISABLE;
+    dmaDefaultConf.DMACh[ch].TCPSegmentation = DISABLE;
+    dmaDefaultConf.DMACh[ch].TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+    dmaDefaultConf.DMACh[ch].DescriptorSkipLength = ETH_DMA_DESC_SKIP_LENGTH_32;
+    dmaDefaultConf.DMACh[ch].MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT;
+  }
+  /* DMA default configuration */
+  ETH_SetDMAConfig(heth, &dmaDefaultConf);
+}
+
+
+/**
+  * @brief  Initializes the DMA Tx descriptors.
+  *         called by HAL_ETH_Init() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
+{
+  ETH_DMADescTypeDef *dmatxdesc;
+  uint32_t i;
+  uint32_t ch;
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for (ch = 0; ch < (uint32_t)ETH_DMA_TX_CH_CNT; ch++)
+  {
+    for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+    {
+      dmatxdesc = heth->Init.TxDesc[ch] + i;
+
+      WRITE_REG(dmatxdesc->DESC0, 0x0U);
+      WRITE_REG(dmatxdesc->DESC1, 0x0U);
+      WRITE_REG(dmatxdesc->DESC2, 0x0U);
+      WRITE_REG(dmatxdesc->DESC3, 0x0U);
+
+      WRITE_REG(heth->TxDescList[ch].TxDesc[i], (uint32_t)dmatxdesc);
+    }
+
+    heth->TxDescList[ch].CurTxDesc = 0;
+  }
+
+  for (ch = 0; ch < ETH_DMA_CH_CNT; ch++)
+  {
+    /* Set Transmit Descriptor Ring Length for DMA Channel  */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACTXRLR, (ETH_TX_DESC_CNT - 1U));
+
+    /* Set Transmit Descriptor List Address for DMA Channel */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACTXDLAR, (uint32_t) heth->Init.TxDesc[ch]);
+
+    /* Set Transmit Descriptor Tail pointer for DMA Channel  */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACTXDTPR, (uint32_t) heth->Init.TxDesc[ch]);
+  }
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  *         called by HAL_ETH_Init() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
+{
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t i;
+  uint32_t ch;
+
+  for (ch = 0; ch < (uint32_t)ETH_DMA_RX_CH_CNT; ch++)
+  {
+    /* Fill each DMACxRxDesc descriptor with the right values */
+    for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+    {
+      dmarxdesc =  heth->Init.RxDesc[ch] + i;
+
+      WRITE_REG(dmarxdesc->DESC0, 0x0U);
+      WRITE_REG(dmarxdesc->DESC1, 0x0U);
+      WRITE_REG(dmarxdesc->DESC2, 0x0U);
+      WRITE_REG(dmarxdesc->DESC3, 0x0U);
+      WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
+      WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
+
+      /* Set Rx descritors addresses */
+      WRITE_REG(heth->RxDescList[ch].RxDesc[i], (uint32_t)dmarxdesc);
+    }
+
+    /* Initialize DMA Ch Rx parameters */
+    WRITE_REG(heth->RxDescList[ch].RxDescIdx, 0U);
+    WRITE_REG(heth->RxDescList[ch].RxDescCnt, 0U);
+    WRITE_REG(heth->RxDescList[ch].RxBuildDescIdx, 0U);
+    WRITE_REG(heth->RxDescList[ch].RxBuildDescCnt, 0U);
+    WRITE_REG(heth->RxDescList[ch].ItMode, 0U);
+
+    /* Set Receive Descriptor Ring Length for DMA Channel */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACRXRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
+
+    /* Set Receive Descriptor List Address for DMA Channel */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACRXDLAR, (uint32_t) heth->Init.RxDesc[ch]);
+
+    /* Set Receive Descriptor Tail pointer Address for DMA Channel */
+    WRITE_REG(heth->Instance->DMA_CH[ch].DMACRXDTPR,
+              ((uint32_t)(heth->Init.RxDesc[ch] + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
+  }
+}
+
+/**
+  * @brief  Prepare Tx DMA descriptor before transmission.
+  *         called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pTxConfig: Tx packet configuration
+  * @param  ItMode: Enable or disable Tx EOT interrupt
+  * @retval Status
+  */
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
+                                           uint32_t ItMode)
+{
+  uint32_t ch = pTxConfig->TxDMACh;
+
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList[ch];
+
+  uint32_t descidx = dmatxdesclist->CurTxDesc;
+  uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
+
+  uint32_t idx;
+  uint32_t descnbr = 0;
+  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+  ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
+  uint32_t           bd_count = 0;
+  uint32_t primask_bit;
+
+  /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+  if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+      || (dmatxdesclist->PacketAddress[descidx] != NULL))
+  {
+    return HAL_ETH_ERROR_BUSY;
+  }
+
+  /***************************************************************************/
+  /*****************    Context descriptor configuration (Optional) **********/
+  /***************************************************************************/
+  /* If VLAN tag is enabled for this packet */
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+  {
+    /* Set vlan tag value */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
+    /* Set vlan tag valid bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
+    /* Set the descriptor as the vlan input source */
+    SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
+
+    /* if inner VLAN is enabled */
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET)
+    {
+      /* Set inner vlan tag value */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
+      /* Set inner vlan tag valid bit */
+      SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
+
+      /* Set Vlan Tag control */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
+
+      /* Set the descriptor as the inner vlan input source */
+      SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
+      /* Enable double VLAN processing */
+      SET_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_EDVLP);
+    }
+  }
+
+  /* if tcp segmentation is enabled for this packet */
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
+  {
+    /* Set MSS value */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
+    /* Set MSS valid bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
+  }
+
+  if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+      || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET))
+  {
+    /* Set as context descriptor */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
+    /* Ensure rest of descriptor is written to RAM before the OWN bit */
+    __DMB();
+    /* Set own bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+    /* Increment current tx descriptor index */
+    INCR_TX_DESC_INDEX(descidx, 1U);
+    /* Get current descriptor address */
+    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+    descnbr += 1U;
+
+    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+    if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+    {
+      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
+      /* Ensure rest of descriptor is written to RAM before the OWN bit */
+      __DMB();
+      /* Clear own bit */
+      CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+
+      return HAL_ETH_ERROR_BUSY;
+    }
+  }
+
+  /***************************************************************************/
+  /*****************    Normal descriptors configuration     *****************/
+  /***************************************************************************/
+
+  descnbr += 1U;
+
+  /* Set header or buffer 1 address */
+  WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+  /* Set header or buffer 1 Length */
+  MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+
+  if (txbuffer->next != NULL)
+  {
+    txbuffer = txbuffer->next;
+    /* Set buffer 2 address */
+    WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+    /* Set buffer 2 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+  }
+  else
+  {
+    WRITE_REG(dmatxdesc->DESC1, 0x0U);
+    /* Set buffer 2 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+  }
+
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
+  {
+    /* Set TCP Header length */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
+    /* Set TCP payload length */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+    /* Set TCP Segmentation Enabled bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+  }
+  else
+  {
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
+    {
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+    }
+
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET)
+    {
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
+    }
+  }
+
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+  {
+    /* Set Vlan Tag control */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
+  }
+
+  /* Mark it as First Descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+  /* Mark it as NORMAL descriptor */
+  CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+  /* Ensure rest of descriptor is written to RAM before the OWN bit */
+  __DMB();
+  /* set OWN bit of FIRST descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+
+  /* If source address insertion/replacement is enabled for this packet */
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET)
+  {
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
+  }
+
+  /* only if the packet is split into more than one descriptors > 1 */
+  while (txbuffer->next != NULL)
+  {
+    /* Clear the LD bit of previous descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+
+    /* Increment current tx descriptor index */
+    INCR_TX_DESC_INDEX(descidx, 1U);
+
+    /* Get current descriptor address */
+    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+    /* Clear the FD bit of new Descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+
+    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+    if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
+        || (dmatxdesclist->PacketAddress[descidx] != NULL))
+    {
+      descidx = firstdescidx;
+      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+      /* clear previous desc own bit */
+      for (idx = 0; idx < descnbr; idx ++)
+      {
+        /* Ensure rest of descriptor is written to RAM before the OWN bit */
+        __DMB();
+
+        CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+
+        /* Increment current tx descriptor index */
+        INCR_TX_DESC_INDEX(descidx, 1U);
+        /* Get current descriptor address */
+        dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+      }
+
+      return HAL_ETH_ERROR_BUSY;
+    }
+
+    descnbr += 1U;
+
+    /* Get the next Tx buffer in the list */
+    txbuffer = txbuffer->next;
+
+    /* Set header or buffer 1 address */
+    WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+    /* Set header or buffer 1 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+
+    if (txbuffer->next != NULL)
+    {
+      /* Get the next Tx buffer in the list */
+      txbuffer = txbuffer->next;
+      /* Set buffer 2 address */
+      WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+      /* Set buffer 2 Length */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+    }
+    else
+    {
+      WRITE_REG(dmatxdesc->DESC1, 0x0U);
+      /* Set buffer 2 Length */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+    }
+
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
+    {
+      /* Set TCP payload length */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+      /* Set TCP Segmentation Enabled bit */
+      SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+    }
+    else
+    {
+      /* Set the packet length */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+
+      if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
+      {
+        /* Checksum Insertion Control */
+        MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+      }
+    }
+
+    bd_count += 1U;
+
+    /* Ensure rest of descriptor is written to RAM before the OWN bit */
+    __DMB();
+    /* Set Own bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+    /* Mark it as NORMAL descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+  }
+
+  if (ItMode != ((uint32_t)RESET))
+  {
+    /* Set Interrupt on completion bit */
+    SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+  }
+  else
+  {
+    /* Clear Interrupt on completion bit */
+    CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+  }
+
+  /* Mark it as LAST descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+  /* Save the current packet address to expose it to the application */
+  dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
+
+  dmatxdesclist->CurTxDesc = descidx;
+
+  /* Enter critical section */
+  primask_bit = __get_PRIMASK();
+  __set_PRIMASK(1);
+
+  dmatxdesclist->BuffersInUse += bd_count + 1U;
+
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
+
+  /* Return function status */
+  return HAL_ETH_ERROR_NONE;
+}
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
+{
+  /* Init the ETH Callback settings */
+  heth->TxCpltCallback   = HAL_ETH_TxCpltCallback;    /* Legacy weak TxCpltCallback   */
+  heth->RxCpltCallback   = HAL_ETH_RxCpltCallback;    /* Legacy weak RxCpltCallback   */
+  heth->ErrorCallback    = HAL_ETH_ErrorCallback;     /* Legacy weak ErrorCallback */
+  heth->PMTCallback      = HAL_ETH_PMTCallback;       /* Legacy weak PMTCallback      */
+  heth->EEECallback      = HAL_ETH_EEECallback;       /* Legacy weak EEECallback      */
+  heth->WakeUpCallback   = HAL_ETH_WakeUpCallback;    /* Legacy weak WakeUpCallback   */
+  heth->rxLinkCallback   = HAL_ETH_RxLinkCallback;    /* Legacy weak RxLinkCallback   */
+  heth->txFreeCallback   = HAL_ETH_TxFreeCallback;    /* Legacy weak TxFreeCallback   */
+#ifdef HAL_ETH_USE_PTP
+  heth->txPtpCallback    = HAL_ETH_TxPtpCallback;     /* Legacy weak TxPtpCallback   */
+#endif /* HAL_ETH_USE_PTP */
+  heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH1 */
+
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_eth_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_eth_ex.c
new file mode 100644
index 000000000..b24c2de26
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_eth_ex.c
@@ -0,0 +1,1856 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_eth_ex.c
+  * @author  MCD Application Team
+  * @brief   ETH HAL Extended module driver.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+
+#if defined(ETH1)
+
+/** @defgroup ETHEx ETHEx
+  * @brief ETH HAL Extended module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
+  * @{
+  */
+#define ETH_MACL4CR_MASK     (ETH_MACL3L4C0R_L4PEN0 | ETH_MACL3L4C0R_L4SPM0 | \
+                              ETH_MACL3L4C0R_L4SPIM0 | ETH_MACL3L4C0R_L4DPM0 | \
+                              ETH_MACL3L4C0R_L4DPIM0)
+
+#define ETH_MACL3CR_MASK     (ETH_MACL3L4C0R_L3PEN0 | ETH_MACL3L4C0R_L3SAM0 | \
+                              ETH_MACL3L4C0R_L3SAIM0 | ETH_MACL3L4C0R_L3DAM0 | \
+                              ETH_MACL3L4C0R_L3DAIM0 | ETH_MACL3L4C0R_L3HSBM0 | \
+                              ETH_MACL3L4C0R_L3HDBM0)
+
+
+#define ETH_MACRXVLAN_MASK (ETH_MACVTCR_EIVLRXS | ETH_MACVTCR_EIVLS | \
+                            ETH_MACVTCR_ERIVLT | ETH_MACVTCR_EDVLP | \
+                            ETH_MACVTCR_VTHM | ETH_MACVTCR_EVLRXS | \
+                            ETH_MACVTCR_EVLS | ETH_MACVTCR_DOVLTC | \
+                            ETH_MACVTCR_ERSVLM | ETH_MACVTCR_ESVL | \
+                            ETH_MACVTCR_VTIM | ETH_MACVTCR_ETV)
+
+#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
+                            ETH_MACVIR_VLP | ETH_MACVIR_VLC)
+
+#define ETH_MACRXQC1R_MASK            0x37F77877U
+#define ETH_MACRXQCR_MASK             0x00030303U
+#define ETH_MTLOMR_MASK               0x00000366U
+#define ETH_MTLTXQxOMR_MASK           0x000F007FU
+#define ETH_MTLRXQxOMR_MASK           0x00F1C7FBU
+#define ETH_MACRXQC2R_PSRQ_MASK       0x0000FFFFU
+#define ETH_MAC_TMRQR_MASK            0x0017FFFFU
+#define ETH_MAC_IACR_MASK             0x0000FF03U
+
+#define ETH_OP_BUSY_TIMEOUT           0x000000FFU
+
+#define ETH_MAC_L4_SRSP_MASK          0x0000FFFFU
+#define ETH_MAC_L4_DSTP_MASK          0xFFFF0000U
+#ifdef HAL_ETH_USE_TAS
+#define ETH_MTLESTCR_MASK             0xFFFFF7F2U
+/* Maximum Width of the time interval in Gate Control List */
+#define ETH_EST_WID_MAX               (24U)
+/* Maximum depth of Gate Control List */
+#define ETH_EST_DEP_MAX               (64U)
+#endif /* HAL_ETH_USE_TAS */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure ARP offload module
+      (+) Configure L3 and L4 filters
+      (+) Configure Extended VLAN features
+      (+) Configure Energy Efficient Ethernet module
+      (+) Configure the Ethernet MTL after ETH peripheral initialization
+      (+) HAL_ETHEx_GetMTLConfig(): Get MTL actual configuration into ETH_MTLConfigTypeDef
+      (+) HAL_ETHEx_SetMTLConfig(): Set MTL configuration based on ETH_MTLConfigTypeDef
+      (+) HAL_ETHEx_SetMACMTLMappingConfig(): Set MAC MTL Mapping configuration based on ETH_MACMTLMappingTypeDef
+      (+) HAL_ETHEx_GetMACMTLMappingConfig(): Get MAC MTL Mapping configuration based on ETH_MACMTLMappingTypeDef
+      (+) HAL_ETHEx_SetUserTagPriorityQueue(): Set User Tag Priority Queue
+      (+) HAL_ETHEx_GetUserTagPriorityQueue(): Get User Tag Priority Queue
+      (+) HAL_ETHEx_SetPacketTypeQueue() : Set Packet Type Queueing
+      (+) HAL_ETHEx_GetPacketTypeQueue() : Get Packet Type Queueing
+      (+) HAL_ETHEx_EnableCBS() : Enable Qav "Credit Based Sahper" feature
+      (+) HAL_ETHEx_SetCBSConfig() : Set Credit Based Shaper parameters
+      (+) HAL_ETHEx_GetCBSConfig() : Get Credit Based Shaper parameters
+      (+) HAL_ETHEx_GetGCLDepth() : Get the GCL List depth
+      (+) HAL_ETHEx_GetGCLWidthTimeInterval() : Get the GCL Width Time interval
+      (+) HAL_ETHEx_EnableEST() : Enable Qbv feature
+      (+) HAL_ETHEx_DisableEST() : Disable Qbv "Enhancement Scheduled Traffic" feature
+      (+) HAL_ETHEx_SetESTConfig() : Set Qbv parameters
+      (+) HAL_ETHEx_SetGCLRegisters() : Set Gate Control List registers
+      (+) HAL_ETHEx_SetGCLConfig() : Set Gate Control List configuration
+      (+) HAL_ETHEx_GetGCLRegisters() : Get Gate Control List configuration
+      (+) HAL_ETHEx_EnableFPE() : Enable Qbu "Frame Preemption" feature
+      (+) HAL_ETHEx_DisableFPE() : Disable Qbu "Frame Preemption" feature
+      (+) HAL_ETHEx_GetFPEConfig() : Get Frame Preemption configuration
+      (+) HAL_ETHEx_SetFPEConfig() : Set Frame Preemption configuration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables ARP Offload.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+
+void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
+{
+  SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
+}
+
+/**
+  * @brief  Disables ARP Offload.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
+{
+  CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
+}
+
+/**
+  * @brief  Set the ARP Match IP address
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  IpAddress: IP Address to be matched for incoming ARP requests
+  * @retval None
+  */
+void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
+{
+  WRITE_REG(heth->Instance->MACARPAR, IpAddress);
+}
+
+/**
+  * @brief  Configures the L4 Filter, this function allow to:
+  *         set the layer 4 protocol to be matched (TCP or UDP)
+  *         enable/disable L4 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L4 filter to configured, this parameter must be one of the following
+  *           ETH_L4_FILTER_0
+  *           ETH_L4_FILTER_1
+  * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
+  *         that contains L4 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+{
+  if (pL4FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Filter == ETH_L4_FILTER_0)
+  {
+    /* Write configuration to MACL3L4C0R register */
+    MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
+                                                              pL4FilterConfig->SrcPortFilterMatch |
+                                                              pL4FilterConfig->DestPortFilterMatch));
+
+    /* Write configuration to MACL4A0R register */
+    WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
+
+  }
+  else /* Filter == ETH_L4_FILTER_1 */
+  {
+    /* Write configuration to MACL3L4C1R register */
+    MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
+                                                              pL4FilterConfig->SrcPortFilterMatch |
+                                                              pL4FilterConfig->DestPortFilterMatch));
+
+    /* Write configuration to MACL4A1R register */
+    WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
+  }
+
+  /* Enable L4 filter */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the L4 Filter, this function allow to:
+  *         set the layer 4 protocol to be matched (TCP or UDP)
+  *         enable/disable L4 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L4 filter to configured, this parameter must be one of the following
+  *           ETH_L4_FILTER_0
+  *           ETH_L4_FILTER_1
+  * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
+  *         that contains L4 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+{
+  if (pL4FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Filter == ETH_L4_FILTER_0)
+  {
+    /* Get configuration from MACL3L4C0R register */
+    pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4C0R_L4PEN0);
+    pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
+                                                    (ETH_MACL3L4C0R_L4DPM0 | ETH_MACL3L4C0R_L4DPIM0));
+    pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
+                                                   (ETH_MACL3L4C0R_L4SPM0 | ETH_MACL3L4C0R_L4SPIM0));
+
+    /* Get configuration from MACL4A0R register */
+    pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16);
+    pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK);
+  }
+  else /* Filter == ETH_L4_FILTER_1 */
+  {
+    /* Get configuration from MACL3L4C1R register */
+    pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4C0R_L4PEN0);
+    pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
+                                                    (ETH_MACL3L4C0R_L4DPM0 | ETH_MACL3L4C0R_L4DPIM0));
+    pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
+                                                   (ETH_MACL3L4C0R_L4SPM0 | ETH_MACL3L4C0R_L4SPIM0));
+
+    /* Get configuration from MACL4A1R register */
+    pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16);
+    pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the L3 Filter, this function allow to:
+  *         set the layer 3 protocol to be matched (IPv4 or IPv6)
+  *         enable/disable L3 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L3 filter to configured, this parameter must be one of the following
+  *           ETH_L3_FILTER_0
+  *           ETH_L3_FILTER_1
+  * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
+  *         that contains L3 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+{
+  if (pL3FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (Filter == ETH_L3_FILTER_0)
+  {
+    /* Write configuration to MACL3L4C0R register */
+    MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+                                                              pL3FilterConfig->SrcAddrFilterMatch |
+                                                              pL3FilterConfig->DestAddrFilterMatch |
+                                                              (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+                                                              (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+  }
+  else  /* Filter == ETH_L3_FILTER_1 */
+  {
+    /* Write configuration to MACL3L4C1R register */
+    MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+                                                              pL3FilterConfig->SrcAddrFilterMatch |
+                                                              pL3FilterConfig->DestAddrFilterMatch |
+                                                              (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+                                                              (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+  }
+
+  if (Filter == ETH_L3_FILTER_0)
+  {
+    /* Check if IPv6 protocol is selected */
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      /* Set the IPv6 address match */
+      /* Set Bits[31:0] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]);
+      /* Set Bits[63:32] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]);
+      /* update Bits[95:64] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]);
+      /* update Bits[127:96] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]);
+    }
+    else /* IPv4 protocol is selected */
+    {
+      /* Set the IPv4 source address match */
+      WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr);
+      /* Set the IPv4 destination address match */
+      WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr);
+    }
+  }
+  else  /* Filter == ETH_L3_FILTER_1 */
+  {
+    /* Check if IPv6 protocol is selected */
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      /* Set the IPv6 address match */
+      /* Set Bits[31:0] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A01R, pL3FilterConfig->Ip6Addr[0]);
+      /* Set Bits[63:32] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A11R, pL3FilterConfig->Ip6Addr[1]);
+      /* update Bits[95:64] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A21R, pL3FilterConfig->Ip6Addr[2]);
+      /* update Bits[127:96] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A31R, pL3FilterConfig->Ip6Addr[3]);
+    }
+    else /* IPv4 protocol is selected */
+    {
+      /* Set the IPv4 source address match */
+      WRITE_REG(heth->Instance->MACL3A01R, pL3FilterConfig->Ip4SrcAddr);
+      /* Set the IPv4 destination address match */
+      WRITE_REG(heth->Instance->MACL3A11R, pL3FilterConfig->Ip4DestAddr);
+
+    }
+  }
+
+  /* Enable L3 filter */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the L3 Filter, this function allow to:
+  *         set the layer 3 protocol to be matched (IPv4 or IPv6)
+  *         enable/disable L3 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L3 filter to configured, this parameter must be one of the following
+  *           ETH_L3_FILTER_0
+  *           ETH_L3_FILTER_1
+  * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
+  *         that will contain the L3 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+{
+  if (pL3FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+  pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                       ETH_MACL3L4C0R_L3PEN0);
+  pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                 (ETH_MACL3L4C0R_L3SAM0 | ETH_MACL3L4C0R_L3SAIM0));
+  pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                  (ETH_MACL3L4C0R_L3DAM0 | ETH_MACL3L4C0R_L3DAIM0));
+  pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                      ETH_MACL3L4C0R_L3HSBM0) >> 6);
+  pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                       ETH_MACL3L4C0R_L3HDBM0) >> 11);
+
+  if (Filter == ETH_L3_FILTER_0)
+  {
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R);
+    }
+    else
+    {
+      WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R);
+      WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R);
+    }
+  }
+  else /* ETH_L3_FILTER_1 */
+  {
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A01R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A11R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A21R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A31R);
+    }
+    else
+    {
+      WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A01R);
+      WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A11R);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables L3 and L4 filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
+{
+  /* Enable L3/L4 filter */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+}
+
+/**
+  * @brief  Disables L3 and L4 filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
+{
+  /* Disable L3/L4 filter */
+  CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+}
+
+/**
+  * @brief  Get the VLAN Configuration for Receive Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
+  *         that will contain the VLAN filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+{
+  if (pVlanConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTCR,
+                                                 ETH_MACVTCR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->StripInnerVLANTag  = READ_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_EIVLS);
+  pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTCR,
+                                                 ETH_MACVTCR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTCR,
+                                                  ETH_MACVTCR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_EVLRXS) >> 24) == 0U)
+                                 ? DISABLE : ENABLE;
+  pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_EVLS);
+  pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTCR,
+                                        (ETH_MACVTCR_DOVLTC | ETH_MACVTCR_ERSVLM | ETH_MACVTCR_ESVL));
+  pVlanConfig->VLANTagInverseMatch = ((READ_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_VTIM) >> 17) == 0U)
+                                     ? DISABLE : ENABLE;
+  pVlanConfig->BitVLANcomparison = ((READ_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_ETV) >> 16) == 0U)
+                                   ? DISABLE : ENABLE;
+  pVlanConfig->VLANTagEnable = ((READ_BIT(heth->Instance->MACVTDR, ETH_MACVTDR_VEN) >> 16) == 0U)
+                               ? DISABLE : ENABLE;
+  pVlanConfig->VLANcomparison = READ_BIT(heth->Instance->MACVTDR, ETH_MACVTDR_ETV);
+
+  pVlanConfig->DMAChannelNumberEnable = ((READ_BIT(heth->Instance->MACVTDR, ETH_MACVTDR_DMACHEN) >> 24) == 0U)
+                                        ? DISABLE : ENABLE;
+  pVlanConfig->RxDMAChannelNumber = READ_BIT(heth->Instance->MACVTDR, ETH_MACVTDR_DMACHN);
+
+  pVlanConfig->VLANTagID = READ_BIT(heth->Instance->MACVTDR, ETH_MACVTDR_VID);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Configuration for Receive Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
+  *         that contains VLAN filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+{
+  if (pVlanConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Write config to MACVTCR */
+  MODIFY_REG(heth->Instance->MACVTCR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
+                                                           pVlanConfig->StripInnerVLANTag |
+                                                           ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
+                                                           ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
+                                                           ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
+                                                           ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
+                                                           pVlanConfig->StripVLANTag |
+                                                           pVlanConfig->VLANTypeCheck |
+                                                           ((uint32_t)pVlanConfig->VLANTagInverseMatch << 17) |
+                                                           ((uint32_t)pVlanConfig->BitVLANcomparison << 16)));
+  /* Write config to MACVTDR */
+  MODIFY_REG(heth->Instance->MACVTDR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->VLANTagEnable << 16) |
+                                                           ((uint32_t)pVlanConfig->VLANcomparison << 17) |
+                                                           ((uint32_t)pVlanConfig->DMAChannelNumberEnable << 24) |
+                                                           (pVlanConfig->RxDMAChannelNumber << 25)));
+
+  HAL_ETH_SetRxVLANIdentifier(heth, (uint32_t)pVlanConfig->VLANcomparison, pVlanConfig->VLANTagID);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Hash Table
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANHashTable: VLAN hash table 16 bit value
+  * @retval None
+  */
+void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
+{
+  MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
+}
+
+/**
+  * @brief  Get the VLAN Configuration for Transmit Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
+  *                 ETH_OUTER_TX_VLANTAG
+  *                 ETH_INNER_TX_VLANTAG
+  * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
+  *         that will contain the Tx VLAN filter configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            ETH_TxVLANConfigTypeDef *pVlanConfig)
+{
+  if (pVlanConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (VLANTag == ETH_INNER_TX_VLANTAG)
+  {
+    pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
+  }
+  else
+  {
+    pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
+  }
+
+  return HAL_OK;;
+}
+
+/**
+  * @brief  Set the VLAN Configuration for Transmit Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
+  *                 ETH_OUTER_TX_VLANTAG
+  *                 ETH_INNER_TX_VLANTAG
+  * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
+  *         that contains Tx VLAN filter configuration.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            const ETH_TxVLANConfigTypeDef *pVlanConfig)
+{
+  if (VLANTag == ETH_INNER_TX_VLANTAG)
+  {
+    MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
+                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
+                                                             pVlanConfig->VLANTagControl));
+    /* Enable Double VLAN processing */
+    SET_BIT(heth->Instance->MACVTCR, ETH_MACVTCR_EDVLP);
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
+                                                            ((uint32_t)pVlanConfig->SVLANType << 19) |
+                                                            pVlanConfig->VLANTagControl));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Tag Identifier for Transmit Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
+  *                 ETH_OUTER_TX_VLANTAG
+  *                 ETH_INNER_TX_VLANTAG
+  * @param  VLANIdentifier: VLAN Identifier 16 bit value
+  * @retval None
+  */
+void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
+{
+  if (VLANTag == ETH_INNER_TX_VLANTAG)
+  {
+    MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
+  }
+}
+
+/**
+  * @brief  Enables the VLAN Tag Filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
+{
+  /* Enable VLAN processing */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
+}
+
+/**
+  * @brief  Disables the VLAN Tag Filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
+{
+  /* Disable VLAN processing */
+  CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
+}
+
+/**
+  * @brief  Enters the Low Power Idle (LPI) mode
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  TxAutomate: Enable/Disable automate enter/exit LPI mode.
+  * @param  TxClockStop: Enable/Disable Tx clock stop in LPI mode.
+  * @retval None
+  */
+void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
+{
+  /* Enable LPI Interrupts */
+  __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
+
+  /* Write to LPI Control register: Enter low power mode */
+  MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE),
+             (((uint32_t)TxAutomate << 19) |
+              ((uint32_t)TxClockStop << 21) |
+              ETH_MACLCSR_LPIEN));
+}
+
+/**
+  * @brief  Exits the Low Power Idle (LPI) mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
+{
+  /* Clear the LPI Config and exit low power mode */
+  CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
+
+  /* Enable LPI Interrupts */
+  __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
+}
+
+/**
+  * @brief  Returns the ETH MAC LPI event
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MAC WakeUp event
+  */
+uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth)
+{
+  return heth->MACLPIEvent;
+}
+
+/**
+  * @brief  Returns the ETH DMA Receive Channels Number Available
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH DMA Rx Channels Number
+  */
+uint32_t HAL_ETHEx_GetRxDMAChNumber(const ETH_HandleTypeDef *heth)
+{
+  uint32_t nbr;
+  nbr = (READ_BIT(heth->Instance->MACHWF2R, ETH_MACHWF2R_RXCHCNT) >> 12) + 1U;
+  return nbr;
+}
+
+/**
+  * @brief  Returns the ETH DMA Transmit Channels Number
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH DMA Tx Channels Number
+  */
+uint32_t HAL_ETHEx_GetTxDMAChNumber(const ETH_HandleTypeDef *heth)
+{
+  uint32_t nbr;
+  nbr = (READ_BIT(heth->Instance->MACHWF2R, ETH_MACHWF2R_TXCHCNT) >> 18) + 1U;
+  return nbr;
+}
+
+/**
+  * @brief  Returns the ETH MTL Receive Queues Number
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MTL Rx Queues Number
+  */
+uint32_t HAL_ETHEx_GetRxMTLQNumber(const ETH_HandleTypeDef *heth)
+{
+  uint32_t nbr;
+  nbr = READ_BIT(heth->Instance->MACHWF2R, ETH_MACHWF2R_RXQCNT) + 1U;
+  return nbr;
+}
+
+/**
+  * @brief  Returns the ETH MTL Transmit Queues Number
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MTL Tx Queues Number
+  */
+uint32_t HAL_ETHEx_GetTxMTLQNumber(const ETH_HandleTypeDef *heth)
+{
+  uint32_t nbr;
+  nbr = (READ_BIT(heth->Instance->MACHWF2R, ETH_MACHWF2R_TXQCNT) >> 6) + 1U;
+  return nbr;
+}
+
+/**
+  * @brief  Get the configuration of the MTL.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  mtlconf: pointer to a ETH_MACConfigTypeDef structure that will hold
+  *         the configuration of the MTL.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetMTLConfig(const ETH_HandleTypeDef *heth, ETH_MTLConfigTypeDef *mtlconf)
+{
+  uint32_t queue;
+
+  if (mtlconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  mtlconf->ReceiveArbitrationAlgorithm = READ_BIT(heth->Instance->MTLOMR, ETH_MTLOMR_RAA_Msk);
+  mtlconf->TxSchedulingAlgorithm = READ_BIT(heth->Instance->MTLOMR, ETH_MTLOMR_SCHALG_Msk);
+  mtlconf->TransmitStatus = ((READ_BIT(heth->Instance->MTLOMR, ETH_MTLOMR_DTXSTS_Msk) >> 1) > 0U) ? ENABLE : DISABLE;
+
+  (mtlconf->RxQ[0]).QueueOpMode = READ_BIT(heth->Instance->MACRXQC0R,
+                                           ETH_MACRXQC0R_RXQ0EN_NOT | ETH_MACRXQC0R_RXQ0EN_GT |
+                                           ETH_MACRXQC0R_RXQ0EN_AV);
+  (mtlconf->RxQ[1]).QueueOpMode = READ_BIT(heth->Instance->MACRXQC0R,
+                                           ETH_MACRXQC0R_RXQ1EN_NOT | ETH_MACRXQC0R_RXQ1EN_GT |
+                                           ETH_MACRXQC0R_RXQ1EN_AV);
+
+  (mtlconf->RxQ[0]).MappedToDMACh = READ_BIT(heth->Instance->MTLRXQDMAMR, ETH_MTLRXQDMAMR_Q0MDMACH_Msk);
+  (mtlconf->RxQ[1]).MappedToDMACh = READ_BIT(heth->Instance->MTLRXQDMAMR, ETH_MTLRXQDMAMR_Q1MDMACH_Msk);
+
+  /* Get MTL parameters */
+  for (queue = 0; queue < ETH_MTL_RX_Q_CNT; queue++)
+  {
+    (mtlconf->RxQ[queue]).RxQueueSize = READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLRXQOMR,
+                                                 (ETH_MTLRXQxOMR_RQS_0 | ETH_MTLRXQxOMR_RQS_1 | ETH_MTLRXQxOMR_RQS_2 |
+                                                  ETH_MTLRXQxOMR_RQS_3));
+    (mtlconf->RxQ[queue]).ReceiveQueueMode = READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLRXQOMR, (ETH_MTLRXQxOMR_RTC |
+                                                      ETH_MTLRXQxOMR_RSF));
+    (mtlconf->RxQ[queue]).ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLRXQOMR,
+                                                                     ETH_MTLRXQxOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
+    (mtlconf->RxQ[queue]).ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLRXQOMR,
+                                                            ETH_MTLRXQxOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
+    (mtlconf->RxQ[queue]).DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLRXQOMR,
+                                                                    ETH_MTLRXQxOMR_DISTCPEF) >>
+                                                           6) == 0U) ? ENABLE : DISABLE;
+  }
+
+  for (queue = 0; queue < ETH_MTL_TX_Q_CNT; queue++)
+  {
+    (mtlconf->TxQ[queue]).TxQueueSize = READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLTXQOMR,
+                                                 (ETH_MTLTXQxOMR_TQS_0 | ETH_MTLTXQxOMR_TQS_1 | ETH_MTLTXQxOMR_TQS_2 |
+                                                  ETH_MTLTXQxOMR_TQS_3));
+    (mtlconf->TxQ[queue]).TransmitQueueMode = READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLTXQOMR, (ETH_MTLTXQxOMR_TTC |
+                                                       ETH_MTLTXQxOMR_TSF));
+    (mtlconf->TxQ[queue]).QueueOpMode = READ_BIT(heth->Instance->MTL_QUEUE[queue].MTLTXQOMR, ETH_MTLTXQxOMR_TXQEN_NOT |
+                                                 ETH_MTLTXQxOMR_TXQEN_EN | ETH_MTLTXQxOMR_TXQEN_AVMODE);
+  }
+
+  (mtlconf->TxQ[1]).AVAlgorithm = READ_BIT(heth->Instance->MTL_QUEUE[1].MTLTXQ1ECR, ETH_MTLTXQ1ECR_AVALG);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the configuration of the MTL.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  mtlconf: pointer to a ETH_MACConfigTypeDef structure that will hold
+  *         the configuration of the MTL.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetMACMTLMappingConfig(const ETH_HandleTypeDef *heth, ETH_MACMTLMappingTypeDef *macmtlconf)
+{
+  if (macmtlconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  macmtlconf->VLANTagFilterFailPacketsQueue = READ_BIT(heth->Instance->MACRXQCR, ETH_MACRXQCR_VFFQ);
+  macmtlconf->VLANTagFilterFailPacketsQueuingEnable = ((READ_BIT(heth->Instance->MACRXQCR,
+                                                                 ETH_MACRXQCR_VFFQE_Msk) >> 16) > 0U)
+                                                      ? ENABLE : DISABLE;
+  macmtlconf->MulticastAddFilterFailPacketsQueue = READ_BIT(heth->Instance->MACRXQCR, ETH_MACRXQCR_MFFQ);
+  macmtlconf->MulticastAddrFilterFailPacketsQueuingEnable = ((READ_BIT(heth->Instance->MACRXQCR,
+                                                                       ETH_MACRXQCR_MFFQE_Msk) >> 8) > 0U)
+                                                            ? ENABLE : DISABLE;
+  macmtlconf->UnicastAddrFilterFailPacketsQueue = READ_BIT(heth->Instance->MACRXQCR, ETH_MACRXQCR_UFFQ);
+  macmtlconf->UnicastAddrFilterFailPacketsQueuingEnable = (READ_BIT(heth->Instance->MACRXQCR,
+                                                                    ETH_MACRXQCR_UFFQE_Msk) > 0U) ? ENABLE : DISABLE;
+  macmtlconf->TypeFieldBasedRxQueuingEnable = (READ_BIT(heth->Instance->MACRXQC1R,
+                                                        ETH_MACRXQC1R_TBRQE_Msk) > 0U) ? ENABLE : DISABLE;
+  macmtlconf->OverridingMCBCQueuePrioritySelect = READ_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_OMCBCQ);
+  macmtlconf->FramePreemptionResidueQueue = READ_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_FPRQ);
+  macmtlconf->TaggedPTPoEPacketsQueuingControl = READ_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_TPQC);
+  macmtlconf->TaggedAVControlPacketsQueuingEnable = (READ_BIT(heth->Instance->MACRXQC1R,
+                                                              ETH_MACRXQC1R_TACPQE_Msk) > 0U) ? ENABLE : DISABLE;
+  macmtlconf->MulticastBroadcastQueueEnable = (READ_BIT(heth->Instance->MACRXQC1R,
+                                                        ETH_MACRXQC1R_MCBCQEN_Msk) > 0U) ? ENABLE : DISABLE;
+  macmtlconf->MulticastBroadcastQueue = READ_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_MCBCQ);
+  macmtlconf->UntaggedPacketQueue = READ_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_UPQ);
+  macmtlconf->PTPPacketsQueue = READ_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_PTPQ);
+  macmtlconf->AVUntaggedControlPacketsQueue = READ_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_AVCPQ);
+
+  if (HAL_ETHEx_GetUserTagPriorityQueue(heth, &(macmtlconf->PrioritiesSelectedRxQ0), ETH_RX_QUEUE0) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (HAL_ETHEx_GetUserTagPriorityQueue(heth, &(macmtlconf->PrioritiesSelectedRxQ1), ETH_RX_QUEUE1) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+HAL_StatusTypeDef ETHEx_SetMACMTLMappingConfig(ETH_HandleTypeDef *heth, const ETH_MACMTLMappingTypeDef *macmtlconf)
+{
+  uint32_t macmtlregval;
+
+  /*------------------------ MACRXQC1R Configuration --------------------*/
+  macmtlregval = ((uint32_t)(macmtlconf->AVUntaggedControlPacketsQueue) |
+                  ((uint32_t)(macmtlconf->PTPPacketsQueue) << 4)         |
+                  ((uint32_t)(macmtlconf->UntaggedPacketQueue) << 12)    |
+                  ((uint32_t)(macmtlconf->MulticastBroadcastQueue) << 16) |
+                  ((uint32_t)((macmtlconf->MulticastBroadcastQueueEnable == DISABLE) ? 0U : 1U) << 20) |
+                  ((uint32_t)((macmtlconf->TaggedAVControlPacketsQueuingEnable == DISABLE) ? 0U : 1U) << 21) |
+                  (uint32_t)(macmtlconf->TaggedPTPoEPacketsQueuingControl) |
+                  (uint32_t)(macmtlconf->FramePreemptionResidueQueue) |
+                  (uint32_t)(macmtlconf->OverridingMCBCQueuePrioritySelect) |
+                  ((uint32_t)((macmtlconf->TypeFieldBasedRxQueuingEnable == DISABLE) ? 0U : 1U) << 29));
+
+  /* Write to MACRXQC1R */
+  MODIFY_REG(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_MASK, macmtlregval);
+
+  /*------------------------ MACRXQC2R Configuration --------------------*/
+  /* Write to MACRXQC2R */
+  if (HAL_ETHEx_SetUserTagPriorityQueue(heth, macmtlconf->PrioritiesSelectedRxQ0, ETH_RX_QUEUE0) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (HAL_ETHEx_SetUserTagPriorityQueue(heth, macmtlconf->PrioritiesSelectedRxQ1, ETH_RX_QUEUE1) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /*------------------------ MACRXQCR Configuration --------------------*/
+  macmtlregval = (((uint32_t)((macmtlconf->UnicastAddrFilterFailPacketsQueuingEnable == DISABLE) ? 0U : 1U)) |
+                  ((uint32_t)(macmtlconf->UnicastAddrFilterFailPacketsQueue) << 1)         |
+                  ((uint32_t)((macmtlconf->MulticastAddrFilterFailPacketsQueuingEnable == DISABLE) ? 0U : 1U) << 8) |
+                  ((uint32_t)(macmtlconf->MulticastAddFilterFailPacketsQueue) << 9)         |
+                  ((uint32_t)((macmtlconf->VLANTagFilterFailPacketsQueuingEnable == DISABLE) ? 0U : 1U) << 16) |
+                  ((uint32_t)(macmtlconf->VLANTagFilterFailPacketsQueue) << 17));
+
+  /* Write to MACRXQCR */
+  MODIFY_REG(heth->Instance->MACRXQCR, ETH_MACRXQCR_MASK, macmtlregval);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the MAC MTL Mapping configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  macmtlconf: pointer to a ETH_MACMTLMappingTypeDef structure that contains
+  *         the configuration of the MAC MTL mapping.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetMACMTLMappingConfig(ETH_HandleTypeDef *heth, const ETH_MACMTLMappingTypeDef *macmtlconf)
+{
+  if (macmtlconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    if (ETHEx_SetMACMTLMappingConfig(heth, macmtlconf) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+
+void ETHEx_SetMTLConfig(ETH_HandleTypeDef *heth, const ETH_MTLConfigTypeDef *mtlconf)
+{
+  uint32_t queue;
+  uint32_t mtlregval;
+
+  /*------------------------ MTLOMR Configuration --------------------*/
+  mtlregval = (mtlconf->TxSchedulingAlgorithm) |
+              (mtlconf->ReceiveArbitrationAlgorithm) |
+              ((uint32_t)((mtlconf->TransmitStatus == DISABLE) ? 1U : 0U) << 1);
+
+  /* Write to MTLOMR */
+  MODIFY_REG(heth->Instance->MTLOMR, ETH_MTLOMR_MASK, mtlregval);
+
+  /*------------------------ MTLRXQDMAMR Configuration --------------------*/
+  mtlregval = (mtlconf->RxQ[0]).MappedToDMACh |
+              (mtlconf->RxQ[1]).MappedToDMACh;
+
+  /* Write to MTLRXQDMAMR */
+  MODIFY_REG(heth->Instance->MTLRXQDMAMR, ETH_MTLRXQDMAMR_Q0MDMACH_Msk | ETH_MTLRXQDMAMR_Q1MDMACH_Msk, mtlregval);
+
+  /*------------------------ MTLTXQOMR Configuration --------------------*/
+  for (queue = 0; queue < ETH_MTL_TX_Q_CNT; queue++)
+  {
+    mtlregval = ((mtlconf->TxQ[queue]).QueueOpMode)         |
+                ((mtlconf->TxQ[queue]).TransmitQueueMode) |
+                ((mtlconf->TxQ[queue]).TxQueueSize);
+
+    /* Write to MTLTXQ0OMR */
+    MODIFY_REG(heth->Instance->MTL_QUEUE[queue].MTLTXQOMR, ETH_MTLTXQxOMR_MASK, mtlregval);
+  }
+
+  /*------------------------ MACRXQC0R Configuration --------------------*/
+  mtlregval = (((mtlconf->RxQ[0]).QueueOpMode)  |
+               ((mtlconf->RxQ[1]).QueueOpMode));
+
+  /* Write to MACRXQC0R */
+  MODIFY_REG(heth->Instance->MACRXQC0R, ETH_MACRXQC0R_RXQ1EN_Msk | ETH_MACRXQC0R_RXQ0EN_Msk, mtlregval);
+
+  /*------------------------ MTLRXQOMR Configuration --------------------*/
+  for (queue = 0; queue < ETH_MTL_RX_Q_CNT; queue++)
+  {
+
+    mtlregval = (((mtlconf->RxQ[queue]).ReceiveQueueMode)  |
+                 ((mtlconf->RxQ[queue]).RxQueueSize)       |
+                 ((uint32_t)(((mtlconf->RxQ[queue]).DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
+                 ((uint32_t)(mtlconf->RxQ[queue]).ForwardRxErrorPacket << 4) |
+                 ((uint32_t)(mtlconf->RxQ[queue]).ForwardRxUndersizedGoodPacket << 3));
+
+    /* Write to MTLRXQOMR */
+    MODIFY_REG(heth->Instance->MTL_QUEUE[queue].MTLRXQOMR, ETH_MTLRXQxOMR_MASK, mtlregval);
+  }
+  /*------------------------ MTLTXQ1ECR Configuration --------------------*/
+  mtlregval = ((mtlconf->TxQ[1]).AVAlgorithm);
+
+  /* Write to MTLTXQ1ECR */
+  MODIFY_REG(heth->Instance->MTL_QUEUE[1].MTLTXQ1ECR, ETH_MTLTXQ1ECR_AVALG_Msk, mtlregval);
+}
+
+/**
+  * @brief  Set the MTL configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  mtlconf: pointer to a ETH_MTLConfigTypeDef structure that contains
+  *         the configuration of the MAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetMTLConfig(ETH_HandleTypeDef *heth,  ETH_MTLConfigTypeDef *mtlconf)
+{
+  if (mtlconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_READY)
+  {
+    ETHEx_SetMTLConfig(heth, mtlconf);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the User Tag Priority Queueing.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  psrq: user priority
+  * @param  queue: queue index
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetUserTagPriorityQueue(const ETH_HandleTypeDef *heth, uint32_t *psrq, uint32_t queue)
+{
+  if (psrq == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (queue == ETH_RX_QUEUE0)
+  {
+    *psrq = (uint32_t)(READ_BIT(heth->Instance->MACRXQC2R, ETH_MACRXQC2R_PSRQ0) >> ETH_MACRXQC2R_PSRQ0_Pos);
+    return HAL_OK;
+  }
+
+  if (queue == ETH_RX_QUEUE1)
+  {
+    *psrq = (uint32_t)(READ_BIT(heth->Instance->MACRXQC2R, ETH_MACRXQC2R_PSRQ1) >> ETH_MACRXQC2R_PSRQ1_Pos);
+    return HAL_OK;
+  }
+
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Set the User Tag Priority Queueing.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  psrq: user priority
+  * @param  queue: queue index
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetUserTagPriorityQueue(ETH_HandleTypeDef *heth, uint32_t psrq, uint32_t queue)
+{
+  uint32_t idx;
+  uint32_t tmppsrq;
+  uint32_t pos;
+
+  for (idx = 0; idx < ETH_MTL_RX_Q_CNT; idx++)
+  {
+    pos = idx * 8U;
+
+    if (idx != queue)
+    {
+      /* Ensure that the same priority PSR is not mapped to multiple Rx queues. */
+      if (HAL_ETHEx_GetUserTagPriorityQueue(heth, &tmppsrq, idx) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      if ((tmppsrq & psrq) != 0U)
+      {
+        CLEAR_BIT(heth->Instance->MACRXQC2R, (psrq << (queue * 8U)));
+        /* PSR is already mapped to another queue */
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      MODIFY_REG(heth->Instance->MACRXQC2R, (psrq << pos), (uint32_t)(psrq << pos));
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Packet Type Queueing.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  typequeueconf: pointer to a ETH_PacketTypeQueueConfigTypeDef structure that contains
+  *         the configuration of the MAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetPacketTypeQueue(ETH_HandleTypeDef *heth,
+                                               const ETH_PacketTypeQueueConfigTypeDef *typequeueconf)
+{
+  uint32_t cmd;
+  uint32_t config;
+
+  if (typequeueconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (heth->gState != HAL_ETH_STATE_STARTED)
+  {
+    return HAL_ERROR;
+  }
+
+  cmd = ETH_WRITE_OPERATION | ETH_MACIACR_OB | ((uint32_t)(typequeueconf->Address) << 8);
+  config = typequeueconf->Preemption | (typequeueconf->Queue << 16) | typequeueconf->Type;
+
+  /* Enable Type field based Rx queuing */
+  SET_BIT(heth->Instance->MACRXQC1R, ETH_MACRXQC1R_TBRQE);
+
+  /* Set configuration to MACTMRQR */
+  WRITE_REG(heth->Instance->MACTMRQR, config);
+
+  /* Set command to MACIACR */
+  MODIFY_REG(heth->Instance->MACIACR, ETH_MAC_IACR_MASK, cmd);
+
+  /* Get tick */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* wait until the Operation reset is done */
+  while (READ_BIT(heth->Instance->MACIACR, ETH_MACIACR_OB) != (uint32_t)RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > ETH_OP_BUSY_TIMEOUT)
+    {
+      /* Set Error Code */
+      heth->MACErrorCode = HAL_ETH_ERROR_TIMEOUT;
+      /* Set State as Error */
+      heth->gState = HAL_ETH_STATE_ERROR;
+      /* Return Error */
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the Packet Type Queueing.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  typequeueconf: pointer to a ETH_PacketTypeQueueConfigTypeDef structure that contains
+  *         the configuration of the MAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetPacketTypeQueue(ETH_HandleTypeDef *heth, ETH_PacketTypeQueueConfigTypeDef *typequeueconf)
+{
+  uint32_t cmd;
+
+  if (heth->gState != HAL_ETH_STATE_STARTED)
+  {
+    return HAL_ERROR;
+  }
+
+  if (typequeueconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  cmd = ETH_READ_OPERATION | ETH_MACIACR_OB | ((uint32_t)(typequeueconf->Address) << 8);
+
+  /* Set command to MACIACR */
+  MODIFY_REG(heth->Instance->MACIACR, ETH_MAC_IACR_MASK, cmd);
+
+  /* Get tick */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* wait until the Operation reset is done */
+  while (READ_BIT(heth->Instance->MACIACR, ETH_MACIACR_OB) != (uint32_t)RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > ETH_OP_BUSY_TIMEOUT)
+    {
+      /* Set Error Code */
+      heth->MACErrorCode = HAL_ETH_ERROR_TIMEOUT;
+      /* Set State as Error */
+      heth->gState = HAL_ETH_STATE_ERROR;
+      /* Return Error */
+      return HAL_ERROR;
+    }
+  }
+
+  /* Get configuration from MACTMRQR */
+  typequeueconf->Preemption = READ_BIT(heth->Instance->MACTMRQR, ETH_MACTMRQR_PFEX_Msk);
+  typequeueconf->Queue = (READ_BIT(heth->Instance->MACTMRQR, ETH_MACTMRQR_TMRQ_Msk) >> 16);
+  typequeueconf->Type = READ_BIT(heth->Instance->MACTMRQR, ETH_MACTMRQR_TYP_Msk);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#ifdef HAL_ETH_USE_CBS
+/**
+  * @brief  Enable the CBS Algorithm.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  queueIndex: contains the AV queue index which will support the CBS algorithm
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_EnableCBS(ETH_HandleTypeDef *heth, uint8_t queueIndex)
+{
+  /* Enable AV mode for Queue x */
+  MODIFY_REG(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQOMR, ETH_MTLTXQxOMR_TXQEN_Msk, ETH_TX_QUEUE_AV_ENABLED);
+
+  /* Enable CBS Algorithm for Queue x */
+  SET_BIT(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQ1ECR, ETH_TX_QUEUE_AV_ALGO_CBS);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+static void ETHEx_SetCBSConfig(ETH_HandleTypeDef *heth, ETH_CBSConfigTypeDef *cbsconf)
+{
+  uint32_t cbsregval;
+  cbsregval = (uint32_t)(cbsconf->SlotCount | cbsconf->CreditControl);
+  /* Write to MTLTXQ1ECR */
+  MODIFY_REG(heth->Instance->MTL_QUEUE[cbsconf->QueueIdx].MTLTXQ1ECR, ETH_MTLTXQ1ECR_SLC_Msk | ETH_MTLTXQ1ECR_CC_Msk,
+             cbsregval);
+
+  cbsregval = (uint32_t)cbsconf->IdleSlope;
+  /* Write to MTLTXQ1QWR */
+  MODIFY_REG(heth->Instance->MTL_QUEUE[cbsconf->QueueIdx].MTLTXQQWR, ETH_MTLTXQ1QWR_ISCQW_Msk, cbsregval);
+
+  cbsregval = (uint32_t)cbsconf->SendSlope;
+  /* Write to MTLTXQ1SSCR */
+  MODIFY_REG(heth->Instance->MTL_QUEUE[cbsconf->QueueIdx].MTLTXQ1SSCR, ETH_MTLTXQ1SSCR_SSC_Msk, cbsregval);
+
+  cbsregval = (uint32_t)cbsconf->HiCredit;
+  /* Write to MTLTXQ1HCR */
+  MODIFY_REG(heth->Instance->MTL_QUEUE[cbsconf->QueueIdx].MTLTXQ1HCR, ETH_MTLTXQ1HCR_HC_Msk, cbsregval);
+
+  cbsregval = (uint32_t)cbsconf->LoCredit;
+  /* Write to MTLTXQ1LCR */
+  MODIFY_REG(heth->Instance->MTL_QUEUE[cbsconf->QueueIdx].MTLTXQ1LCR, ETH_MTLTXQ1LCR_LC_Msk, cbsregval);
+}
+
+/**
+  * @brief  Set the CBS configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  cbsconf: pointer to a ETH_CBSConfigTypeDef structure that contains
+  *         the configuration of the CBS algorithm.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetCBSConfig(ETH_HandleTypeDef *heth,  ETH_CBSConfigTypeDef *cbsconf)
+{
+  if (cbsconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((READ_BIT(heth->Instance->MTL_QUEUE[cbsconf->QueueIdx].MTLTXQOMR, ETH_TX_QUEUE_AV_ENABLED) != (uint32_t)RESET) &&
+      (READ_BIT(heth->Instance->MTL_QUEUE[cbsconf->QueueIdx].MTLTXQ1ECR, ETH_TX_QUEUE_AV_ALGO_CBS) != (uint32_t)RESET))
+  {
+    ETHEx_SetCBSConfig(heth, cbsconf);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL ETH Get CBS Config.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pCBSConfig: pointer to a ETH_CBSConfigTypeDef structure that will hold
+  *         the configuration of the CBS Algorithm.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetCBSConfig(const ETH_HandleTypeDef *heth, ETH_CBSConfigTypeDef *pCBSConfig,
+                                         uint8_t queueIndex)
+{
+  if (pCBSConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  pCBSConfig->QueueIdx = queueIndex;
+  pCBSConfig->SlotCount = READ_BIT(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQ1ECR, ETH_MTLTXQ1ECR_SLC);
+  pCBSConfig->CreditControl = READ_BIT(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQ1ECR, ETH_MTLTXQ1ECR_CC);
+  pCBSConfig->IdleSlope = READ_BIT(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQQWR, ETH_MTLTXQ1QWR_ISCQW);
+  pCBSConfig->SendSlope = READ_BIT(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQ1SSCR, ETH_MTLTXQ1SSCR_SSC);
+  pCBSConfig->HiCredit = READ_BIT(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQ1HCR, ETH_MTLTXQ1HCR_HC);
+  pCBSConfig->LoCredit = READ_BIT(heth->Instance->MTL_QUEUE[queueIndex].MTLTXQ1LCR, ETH_MTLTXQ1LCR_LC);
+
+  return HAL_OK;
+}
+#endif /* HAL_ETH_USE_CBS */
+
+#ifdef HAL_ETH_USE_TAS
+/**
+  * @brief  HAL ETH Enable EST feature.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_EnableEST(ETH_HandleTypeDef *heth)
+{
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    /* Enable Enhancement Scheduling Transmission */
+    SET_BIT(heth->Instance->MTLESTCR, ETH_MTLESTCR_EEST);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL ETH Disable EST feature.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_DisableEST(ETH_HandleTypeDef *heth)
+{
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    /* Disable Enhancement Scheduling Transmission */
+    CLEAR_BIT(heth->Instance->MTLESTCR, ETH_MTLESTCR_EEST);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL ETH Get the HW Depth of the Gate Control List.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval Depth of the Gate Control List
+  */
+uint32_t HAL_ETHEx_GetGCLDepth(const ETH_HandleTypeDef *heth)
+{
+  uint32_t gcldepth;
+
+  /* get HW GCL depth from HW configuration */
+  gcldepth = READ_BIT(heth->Instance->MACHWF3R, ETH_MACHWF3R_ESTDEP_Msk);
+
+  switch (gcldepth)
+  {
+    case ETH_MACHWF3R_ESTDEP_64 :
+      return 64;
+    case ETH_MACHWF3R_ESTDEP_128 :
+      return 128;
+    case ETH_MACHWF3R_ESTDEP_256 :
+      return 256;
+    case ETH_MACHWF3R_ESTDEP_512 :
+      return 512;
+    case ETH_MACHWF3R_ESTDEP_1024 :
+      return 1024;
+    default :
+      return 0;
+  }
+}
+
+/**
+  * @brief  HAL ETH Get the HW Width of the Time Interval field in the Gate Control List
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval Width of the Time Interval field in the Gate Control List
+  */
+uint32_t HAL_ETHEx_GetGCLWidthTimeInterval(const ETH_HandleTypeDef *heth)
+{
+  uint32_t gclwidth;
+
+  /* get HW GCL Width from HW configuration */
+  gclwidth = READ_BIT(heth->Instance->MACHWF3R, ETH_MACHWF3R_ESTWID_Msk);
+
+  switch (gclwidth)
+  {
+    case ETH_MACHWF3R_ESTWID_16 :
+      return 16;
+    case ETH_MACHWF3R_ESTWID_20 :
+      return 20;
+    case ETH_MACHWF3R_ESTWID_24 :
+      return 24;
+    default :
+      return 0;
+  }
+}
+
+/**
+  * @brief  HAL ETH Check HW Completion Check
+  */
+static HAL_StatusTypeDef ETHEx_ESTHWCompletionCheck(ETH_HandleTypeDef *heth)
+{
+  /* Get tick */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* wait until the reset is done by Hardware */
+  while (READ_BIT(heth->Instance->MTLESTGCLCR, ETH_MTLESTGCLCR_SRWO) != (uint32_t)RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > ETH_HWRESET_TIMEOUT)
+    {
+      /* Set State as Error */
+      heth->gState = HAL_ETH_STATE_ERROR;
+      /* Return Error */
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL ETH Get GCL Registers values
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetGCLRegisters(ETH_HandleTypeDef *heth, ETH_GCLConfigTypeDef *gclconf)
+{
+  uint32_t mtlestgclctrl = ETH_MTLESTGCLCR_GCRR | ETH_MTLESTGCLCR_SRWO | ETH_MTLESTGCLCR_R1W0;
+  uint32_t mtlestgclctrl_mask = ETH_MTLESTGCLCR_ADDR_Msk | ETH_MTLESTGCLCR_GCRR_Msk | ETH_MTLESTGCLCR_SRWO_Msk;
+
+  /* Set BTR Low Address and start read operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_BTRLOW);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get BTR Low value */
+  gclconf->BaseTimeRegister = (uint32_t)READ_REG(heth->Instance->MTLESTGCLDR);
+
+  /* Set BTR High Address and start read operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_BTRHIGH);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get BTR High value */
+  gclconf->BaseTimeRegister |= ((uint64_t)READ_REG(heth->Instance->MTLESTGCLDR) << 32U);
+
+  /* Set CTR Low Address and start read operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_CTRLOW);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get CTR Low value */
+  gclconf->CycleTimeRegister = (uint32_t)READ_REG(heth->Instance->MTLESTGCLDR);
+
+  /* Set CTR High Address and start read operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_CTRHIGH);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get CTR High value */
+  gclconf->CycleTimeRegister |= ((uint64_t)READ_REG(heth->Instance->MTLESTGCLDR) << 32U);
+
+  /* Set TER Address and start read operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_TER);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get TER value */
+  gclconf->TimeExtensionRegister = (uint32_t)READ_REG(heth->Instance->MTLESTGCLDR);
+
+  /* Set LLR Address and start read operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_LLR);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get TER value */
+  gclconf->ListLengthRegister = (uint32_t)READ_REG(heth->Instance->MTLESTGCLDR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL ETH Set GCL Registers values
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetGCLRegisters(ETH_HandleTypeDef *heth, const ETH_GCLConfigTypeDef *gclconf)
+{
+  uint32_t mtlestgclctrl = ETH_MTLESTGCLCR_GCRR | ETH_MTLESTGCLCR_SRWO;
+  uint32_t mtlestgclctrl_mask = ETH_MTLESTGCLCR_ADDR_Msk | ETH_MTLESTGCLCR_GCRR_Msk | ETH_MTLESTGCLCR_SRWO_Msk;
+
+  /* Set BTR Low value */
+  WRITE_REG(heth->Instance->MTLESTGCLDR, (uint32_t)gclconf->BaseTimeRegister);
+
+  /* Set BTR Low Address and start write operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_BTRLOW);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set BTR High value */
+  WRITE_REG(heth->Instance->MTLESTGCLDR, ((uint32_t)(gclconf->BaseTimeRegister >> 32)));
+
+  /* Set BTR High Address and start write operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_BTRHIGH);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set CTR Low value */
+  WRITE_REG(heth->Instance->MTLESTGCLDR, (uint32_t)gclconf->CycleTimeRegister);
+
+  /* Set CTR Low Address and start write operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_CTRLOW);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set CTR High value */
+  WRITE_REG(heth->Instance->MTLESTGCLDR, ((uint32_t)(gclconf->CycleTimeRegister >> 32)));
+
+  /* Set CTR High Address and start write operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_CTRHIGH);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set TER value */
+  WRITE_REG(heth->Instance->MTLESTGCLDR, (uint32_t)gclconf->TimeExtensionRegister);
+
+  /* Set TER Address and start write operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_TER);
+
+  /* Set LLR value */
+  WRITE_REG(heth->Instance->MTLESTGCLDR, (uint32_t)gclconf->ListLengthRegister);
+
+  /* Set LLR Address and start write operation */
+  MODIFY_REG(heth->Instance->MTLESTGCLCR, mtlestgclctrl_mask, mtlestgclctrl | ETH_MTLESTGCLCR_ADDR_LLR);
+
+  /* wait for a HW reset Check */
+  if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL ETH Set GCL configuration
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetGCLConfig(ETH_HandleTypeDef *heth, ETH_GCLConfigTypeDef *gclconf)
+{
+  uint32_t glcidx;
+  uint32_t data;
+
+  for (glcidx = 0; glcidx < gclconf->ListLengthRegister; glcidx++)
+  {
+    /* Set data : TC1 + TC0 + TimeInterval */
+    data = gclconf->opList->Interval | (gclconf->opList->Gate << ETH_EST_WID_MAX);
+
+    /* Set data to MTLESTGCLDR register */
+    WRITE_REG(heth->Instance->MTLESTGCLDR, data);
+
+    /* Set Address and start write operation */
+    MODIFY_REG(heth->Instance->MTLESTGCLCR, ETH_MTLESTGCLCR_ADDR_Msk | ETH_MTLESTGCLCR_SRWO_Msk,
+               (glcidx << ETH_MTLESTGCLCR_ADDR_Pos) | ETH_MTLESTGCLCR_SRWO);
+
+    /* wait for a HW completion Check */
+    if (ETHEx_ESTHWCompletionCheck(heth) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* If ok, Move to the next GLC in the list */
+    (gclconf->opList)++;
+  }
+
+  if (HAL_ETHEx_SetGCLRegisters(heth, gclconf) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  HAL ETH Set Enhancement Scheduling Traffic Configuration
+  */
+static HAL_StatusTypeDef ETHEx_SetESTConfig(ETH_HandleTypeDef *heth, ETH_ESTConfigTypeDef *estconf)
+{
+  uint32_t estregval;
+
+  /* Check on GCL list Length */
+  if (estconf->GCLRegisters.ListLengthRegister > ETH_EST_DEP_MAX)
+  {
+    return HAL_ERROR;
+  }
+  /* Check on opList */
+  if (estconf->GCLRegisters.opList == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check on completion of switch to the S/W owned list */
+  if (READ_BIT(heth->Instance->MTLESTCR, ETH_MTLESTCR_SSWL) != (uint32_t)RESET)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Programming the GCL and GCL-linked registers */
+  if (HAL_ETHEx_SetGCLConfig(heth, &estconf->GCLRegisters) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set EST Configuration */
+  estregval = ((estconf->SwitchToSWOL << 1) |
+               ((uint32_t)estconf->NotDropFramesDuringFrameSizeError << 4) |
+               ((uint32_t)estconf->DropFramesCausingError << 5) |
+               (estconf->LoopCountSchedulingError) |
+               (estconf->TimeIntervalLeftShift << 8) |
+               (estconf->CurrentTimeOffset << 12) |
+               (((uint32_t)(1000000000U / estconf->PTPTimeOffset) * 6U) << 24));
+
+  /* Write to MTLESTCR */
+  MODIFY_REG(heth->Instance->MTLESTCR, ETH_MTLESTCR_MASK, estregval);
+
+  /* Get Overhead bytes value */
+  estregval = estconf->OverheadBytesValue;
+
+  /* Write to MTLESTECR */
+  MODIFY_REG(heth->Instance->MTLESTECR, ETH_MTLESTECR_OVHD_Msk, estregval);
+
+  /* Enable Enhancement Scheduling Traffic feature */
+  if (HAL_ETHEx_EnableEST(heth) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the EST configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  estconf: pointer to a ETH_ESTConfigTypeDef structure that contains
+  *         the configuration of the EST algorithm.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetESTConfig(ETH_HandleTypeDef *heth,  ETH_ESTConfigTypeDef *estconf)
+{
+  if (estconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    if (ETHEx_SetESTConfig(heth, estconf) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+#endif /* HAL_ETH_USE_TAS */
+
+#ifdef HAL_ETH_USE_FPE
+/**
+  * @brief  Enable FPE feature.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_EnableFPE(ETH_HandleTypeDef *heth)
+{
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    /* Enable Tx Frame Preemption feature */
+    SET_BIT(heth->Instance->MACFPECSR, ETH_MACFPECSR_EFPE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable FPE feature.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_DisableFPE(ETH_HandleTypeDef *heth)
+{
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    /* Disable Tx Frame Preemption feature */
+    CLEAR_BIT(heth->Instance->MACFPECSR, ETH_MACFPECSR_EFPE);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the FPE configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  fpeconf: pointer to a ETH_FPEConfigTypeDef structure that contains
+  *         the configuration of the FPE Feature.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetFPEConfig(ETH_HandleTypeDef *heth,  ETH_FPEConfigTypeDef *fpeconf)
+{
+  if (fpeconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  fpeconf->AdditionalFragmentSize = READ_BIT(heth->Instance->MTLFPECSR, ETH_MTLFPECSR_AFSZ);
+  fpeconf->PreemptionClassification = READ_BIT(heth->Instance->MTLFPECSR, ETH_MTLFPECSR_PEC);
+  fpeconf->HoldReleaseStatus = READ_BIT(heth->Instance->MTLFPECSR, ETH_MTLFPECSR_HRS);
+
+  fpeconf->HoldAdvance = READ_BIT(heth->Instance->MTLFPEAR, ETH_MTLFPEAR_HADV);
+  fpeconf->ReleaseAdvance = READ_BIT(heth->Instance->MTLFPEAR, ETH_MTLFPEAR_RADV);
+
+  fpeconf->SendVerifymPacket = ((READ_BIT(heth->Instance->MACFPECSR,
+                                          ETH_MACFPECSR_SVER) >> ETH_MACFPECSR_SVER_Pos) > 0U) ? ENABLE : DISABLE;
+  fpeconf->SendRespondmPacket = ((READ_BIT(heth->Instance->MACFPECSR,
+                                           ETH_MACFPECSR_SRSP) >> ETH_MACFPECSR_SRSP_Pos) > 0U) ? ENABLE : DISABLE;
+  return HAL_OK;
+}
+
+static void ETHEx_SetFPEConfig(ETH_HandleTypeDef *heth, ETH_FPEConfigTypeDef *fpeconf)
+{
+  uint32_t fperegval;
+
+  fperegval = fpeconf->PreemptionClassification | fpeconf->AdditionalFragmentSize;
+
+  /* Write to MTLFPECSR */
+  WRITE_REG(heth->Instance->MTLFPECSR, fperegval);
+
+  fperegval = fpeconf->HoldAdvance | fpeconf->ReleaseAdvance;
+
+  /* Write to MTLFPEAR */
+  WRITE_REG(heth->Instance->MTLFPEAR, fperegval);
+
+  fperegval = ((uint32_t)((fpeconf->SendVerifymPacket == ENABLE) ? 1U : 0U) << 1) |
+              ((uint32_t)((fpeconf->SendRespondmPacket == ENABLE) ? 1U : 0U) << 2);
+
+  /* Write to MACFPECSR */
+  MODIFY_REG(heth->Instance->MACFPECSR, ETH_MACFPECSR_SVER_Msk | ETH_MACFPECSR_SRSP_Msk, fperegval);
+}
+
+/**
+  * @brief  Set the FPE configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  fpeconf: pointer to a ETH_FPEConfigTypeDef structure that contains
+  *         the configuration of the FPE Feature.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetFPEConfig(ETH_HandleTypeDef *heth,  ETH_FPEConfigTypeDef *fpeconf)
+{
+  if (fpeconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (heth->gState == HAL_ETH_STATE_STARTED)
+  {
+    ETHEx_SetFPEConfig(heth, fpeconf);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+#endif /* HAL_ETH_USE_FPE */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH1 */
+
+#endif /* HAL_ETH_MODULE_ENABLED */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_exti.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_exti.c
new file mode 100644
index 000000000..b44745085
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_exti.c
@@ -0,0 +1,849 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_exti.c
+  * @author  GPM Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt
+        (++) Event
+        (++) Both of them
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two different
+        interrupt pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected through multiplexer.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+#define EXTI_MODE_OFFSET                    0x04U   /* byte offset between IMRx/EMRx registers */
+#define EXTI_CONFIG_OFFSET                  0x08U   /* byte offset between Rising/Falling configuration registers */
+#define EXTI_PRIVCFGR_OFFSET                0x08U   /* byte offset between PRIVCFGRx/PRIVCFGRx registers */
+#define EXTI_SECCFGR_OFFSET                 0x08U   /* byte offset between SECCFGRx/SECCFGRx registers */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+  *  @brief    Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store rising trigger mode */
+    *regaddr = regval;
+
+    /* Configure falling trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store falling trigger mode */
+    *regaddr = regval;
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  const __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Get core mode : interrupt */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+  else
+  {
+    pExtiConfig->Mode = EXTI_MODE_NONE;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0U)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+    else
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    }
+
+    /* Get falling configuration */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0U)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+      pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & EXTI_EXTICR1_EXTI0;
+    }
+    else
+    {
+      pExtiConfig->GPIOSel = 0U;
+    }
+  }
+  else
+  {
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    pExtiConfig->GPIOSel = 0U;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Clear interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
+                                            void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->RisingCallback = pPendingCbfn;
+      hexti->FallingCallback = pPendingCbfn;
+      break;
+
+    case  HAL_EXTI_RISING_CB_ID:
+      hexti->RisingCallback = pPendingCbfn;
+      break;
+
+    case  HAL_EXTI_FALLING_CB_ID:
+      hexti->FallingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+  *  @brief EXTI IO functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get rising edge pending bit  */
+  regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+  regval = (*regaddr & maskline);
+
+  if (regval != 0U)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call rising callback */
+    if (hexti->RisingCallback != NULL)
+    {
+      hexti->RisingCallback();
+    }
+  }
+
+  /* Get falling edge pending bit  */
+  regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+  regval = (*regaddr & maskline);
+
+  if (regval != 0U)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call falling callback */
+    if (hexti->FallingCallback != NULL)
+    {
+      hexti->FallingCallback();
+    }
+  }
+}
+
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING
+  *           @arg @ref EXTI_TRIGGER_FALLING
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  const __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  if (Edge != EXTI_TRIGGER_RISING)
+  {
+    /* Get falling edge pending bit */
+    regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+  else
+  {
+    /* Get rising edge pending bit */
+    regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+
+  /* return 1 if bit is set else 0 */
+  regval = ((*regaddr & maskline) >> linepos);
+  return regval;
+}
+
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING
+  *           @arg @ref EXTI_TRIGGER_FALLING
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+  if (Edge != EXTI_TRIGGER_RISING)
+  {
+    /* Get falling edge pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+  else
+  {
+    /* Get rising edge pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+
+  /* Clear Pending bit */
+  *regaddr =  maskline;
+}
+
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+  regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+  *regaddr = maskline;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
+  *  @brief EXTI attributes management functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### EXTI attributes functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the EXTI line attribute(s).
+  * @note   Available attributes are to secure EXTI line and set EXTI line as privileged.
+  *         Default state is not secure and unprivileged access allowed.
+  * @note   Set an EXTI line to secure is only available in secure and privilege
+  *         Set an EXTI line to privilege is only available in privilege
+  * @note   Security and privilege attributes can be set independently.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @param  LineAttributes can be one or a combination of the following values:
+  *            @arg @ref EXTI_LINE_PRIV         Privileged-only access
+  *            @arg @ref EXTI_LINE_NPRIV        Privileged/Non-privileged access
+  *            @arg @ref EXTI_LINE_SEC          Secure-only access
+  *            @arg @ref EXTI_LINE_NSEC         Secure/Non-secure access
+  * @retval None
+  */
+void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+  assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes));
+
+  /* compute line register offset and line mask */
+  offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (ExtiLine & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* Configure privilege or non-privilege attributes */
+  regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV)
+  {
+    regval |= maskline;
+  }
+  else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)
+  {
+    regval &= ~maskline;
+  }
+  else
+  {
+    /* do nothing */
+  }
+
+  /* Store privilege or non-privilege attribute */
+  *regaddr = regval;
+
+#if defined CPU_IN_SECURE_STATE
+  /* Configure secure or non-secure attributes */
+  regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC)
+  {
+    regval |= maskline;
+  }
+  else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC)
+  {
+    regval &= ~maskline;
+  }
+  else
+  {
+    /* do nothing */
+  }
+
+  /* Store secure or non-secure attribute */
+  *regaddr = regval;
+#endif /* CPU_IN_SECURE_STATE */
+
+}
+
+/**
+  * @brief  Get the EXTI line attribute(s).
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @param  pLineAttributes: pointer to return line attributes.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes)
+{
+  const __IO uint32_t *regaddr;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t attributes;
+
+  /* Check null pointer */
+  if (pLineAttributes == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Compute line register offset and line mask */
+  offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (ExtiLine & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* Get privilege or non-privilege attribute */
+  regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
+
+  if ((*regaddr & maskline) != 0U)
+  {
+    attributes = EXTI_LINE_PRIV;
+  }
+  else
+  {
+    attributes = EXTI_LINE_NPRIV;
+  }
+
+  /* Get secure or non-secure attribute */
+  regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
+
+  if ((*regaddr & maskline) != 0U)
+  {
+    attributes |= EXTI_LINE_SEC;
+  }
+  else
+  {
+    attributes |= EXTI_LINE_NSEC;
+  }
+
+  /* return value */
+  *pLineAttributes = attributes;
+
+  return HAL_OK;
+}
+
+#if defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief  Lock the secure and privilege configuration registers.
+  * @retval None
+  */
+void HAL_EXTI_LockAttributes(void)
+{
+  SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
+}
+
+/**
+  * @brief  Return the secure and privilege configuration registers LOCK status
+  * @retval 1 if the secure and privilege configuration registers have been locked else 0.
+  */
+uint32_t HAL_EXTI_GetLockAttributes(void)
+{
+  return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK);
+}
+
+#endif /* CPU_IN_SECURE_STATE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_fdcan.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_fdcan.c
new file mode 100644
index 000000000..dc4d35d52
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_fdcan.c
@@ -0,0 +1,6257 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_fdcan.c
+  * @author  MCD Application Team
+  * @brief   FDCAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible DataRate Controller Area Network
+  *          (FDCAN) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Configuration and Control functions
+  *           + Peripheral State and Error functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+      (#) If needed , configure the reception filters and optional features using
+          the following configuration functions:
+            (++) HAL_FDCAN_ConfigClockCalibration
+            (++) HAL_FDCAN_ConfigFilter
+            (++) HAL_FDCAN_ConfigGlobalFilter
+            (++) HAL_FDCAN_ConfigExtendedIdMask
+            (++) HAL_FDCAN_ConfigRxFifoOverwrite
+            (++) HAL_FDCAN_ConfigFifoWatermark
+            (++) HAL_FDCAN_ConfigRamWatchdog
+            (++) HAL_FDCAN_ConfigTimestampCounter
+            (++) HAL_FDCAN_EnableTimestampCounter
+            (++) HAL_FDCAN_DisableTimestampCounter
+            (++) HAL_FDCAN_ConfigTimeoutCounter
+            (++) HAL_FDCAN_EnableTimeoutCounter
+            (++) HAL_FDCAN_DisableTimeoutCounter
+            (++) HAL_FDCAN_ConfigTxDelayCompensation
+            (++) HAL_FDCAN_EnableTxDelayCompensation
+            (++) HAL_FDCAN_DisableTxDelayCompensation
+            (++) HAL_FDCAN_EnableISOMode
+            (++) HAL_FDCAN_DisableISOMode
+            (++) HAL_FDCAN_EnableEdgeFiltering
+            (++) HAL_FDCAN_DisableEdgeFiltering
+            (++) HAL_FDCAN_TT_ConfigOperation
+            (++) HAL_FDCAN_TT_ConfigReferenceMessage
+            (++) HAL_FDCAN_TT_ConfigTrigger
+
+      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+          the node is active on the bus: it can send and receive messages.
+
+      (#) The following Tx control functions can only be called when the FDCAN
+          module is started:
+            (++) HAL_FDCAN_AddMessageToTxFifoQ
+            (++) HAL_FDCAN_EnableTxBufferRequest
+            (++) HAL_FDCAN_AbortTxRequest
+
+      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+          get Tx buffer location used to place the Tx request thanks to
+          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+          It is then possible to abort later on the corresponding Tx Request using
+          HAL_FDCAN_AbortTxRequest API.
+
+      (#) When a message is received into the FDCAN message RAM, it can be
+          retrieved using the HAL_FDCAN_GetRxMessage function.
+
+      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+          it to initialization mode and re-enabling access to configuration
+          registers through the configuration functions listed here above.
+
+      (#) All other control functions can be called any time after initialization
+          phase, no matter if the FDCAN module is started or stopped.
+
+      *** Polling mode operation ***
+      ==============================
+    [..]
+        (#) Reception and transmission states can be monitored via the following
+            functions:
+              (++) HAL_FDCAN_IsRxBufferMessageAvailable
+              (++) HAL_FDCAN_IsTxBufferMessagePending
+              (++) HAL_FDCAN_GetRxFifoFillLevel
+              (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+      *** Interrupt mode operation ***
+      ================================
+      [..]
+        (#) There are two interrupt lines: line 0 and 1.
+            By default, all interrupts are assigned to line 0. Interrupt lines
+            can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+            function. Then, the process can be controlled through one of the
+            available user callbacks: HAL_FDCAN_xxxCallback.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+  TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
+  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks:
+  respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(),
+  HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
+  HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(),
+  HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+  HAL_FDCAN_TT_RegisterTimeMarkCallback(), HAL_FDCAN_TT_RegisterStopWatchCallback() and
+  HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+
+  Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
+  RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
+  TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
+  register callbacks: respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+  HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(),
+  HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+  HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(),
+  HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+  HAL_FDCAN_TT_UnRegisterStopWatchCallback() and HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+
+  By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  examples HAL_FDCAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
+  or HAL_FDCAN_Init() function.
+
+  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FDCAN FDCAN
+  * @brief FDCAN HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+  * @{
+  */
+#define FDCAN_TIMEOUT_VALUE 10U
+#define FDCAN_TIMEOUT_COUNT 50U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
+#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
+#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
+#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
+                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
+#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
+#define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
+#define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
+#define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
+#define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
+#define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
+#define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
+#define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
+#define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
+
+#define FDCAN_MESSAGE_RAM_SIZE 0x2800U
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* Message RAM width is 4 Bytes */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Variables
+  * @{
+  */
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+  * @{
+  */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                   const uint8_t *pTxData, uint32_t BufferIndex);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+  * @{
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the FDCAN.
+      (+) De-initialize the FDCAN.
+      (+) Enter FDCAN peripheral in power down mode.
+      (+) Exit power down mode.
+      (+) Register callbacks.
+      (+) Unregister callbacks.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FDCAN peripheral according to the specified
+  *         parameters in the FDCAN_InitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+  assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+  assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+  assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+  assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+  assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+    assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+    assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+    assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
+  assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+  }
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
+  }
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Reset callbacks to legacy functions */
+    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* ClockCalibrationCallback    */
+    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* TxEventFifoCallback         */
+    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* RxFifo0Callback             */
+    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* RxFifo1Callback             */
+    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* TxFifoEmptyCallback         */
+    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* TxBufferCompleteCallback    */
+    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* TxBufferAbortCallback       */
+    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* RxBufferNewMessageCallback  */
+    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */
+    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */
+    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* TimeoutOccurredCallback     */
+    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* ErrorCallback               */
+    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* ErrorStatusCallback         */
+    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* TT_ScheduleSyncCallback     */
+    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* TT_TimeMarkCallback         */
+    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* TT_StopWatchCallback        */
+    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* TT_GlobalTimeCallback       */
+
+    if (hfdcan->MspInitCallback == NULL)
+    {
+      hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+  /* Set FDCAN Operating Mode:
+               | Normal | Restricted |    Bus     | Internal | External
+               |        | Operation  | Monitoring | LoopBack | LoopBack
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+    }
+  }
+  else
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)     | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)     | \
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS,
+               (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS,
+               (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS,
+               (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+  /* Stop the FDCAN module: return value is voluntary ignored */
+  (void)HAL_FDCAN_Stop(hfdcan);
+
+  /* Disable Interrupt lines */
+  CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->MspDeInitCallback == NULL)
+  {
+    hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hfdcan->MspDeInitCallback(hfdcan);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Reset the FDCAN ErrorCode */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Change FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Enter FDCAN peripheral in sleep mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Request clock stop */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN is ready for power down */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit power down mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Reset clock stop request */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN exits sleep mode */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enter normal operation */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  Register a FDCAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+                                             void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a FDCAN CallBack.
+  *         FDCAN callback is redirected to the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Clock Calibration FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Clock Calibration Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Clock Calibration FDCAN Callback
+  *         Clock Calibration FDCAN Callback is redirected to the weak
+  *         HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Event Fifo FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Event Fifo Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Event Fifo FDCAN Callback
+  *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 0 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 0 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo0CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
+  *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 1 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 1 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo1CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
+  *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Complete FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Complete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
+  *         Tx Buffer Complete FDCAN Callback is redirected to
+  *         the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Abort FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Abort Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                          pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
+  *         Tx Buffer Abort FDCAN Callback is redirected to
+  *         the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Error Status FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Error Status Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Error Status FDCAN Callback
+  *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Schedule Synchronization FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Schedule Synchronization Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                           pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
+  *         TT Schedule Synchronization Callback is redirected to the weak
+  *         HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Time Mark FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Time Mark Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                       pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Time Mark FDCAN Callback
+  *         TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Stop Watch FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Stop Watch Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Stop Watch FDCAN Callback
+  *         TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Global Time FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Global Time Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                         pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Global Time FDCAN Callback
+  *         TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+  *  @brief    FDCAN Configuration functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
+        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
+        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
+        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
+      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
+      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
+      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
+      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
+      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
+      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
+      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
+        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
+        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
+        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
+        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
+      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
+        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
+        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
+        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
+        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
+      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
+        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
+        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
+      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
+      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the FDCAN clock calibration unit according to the specified
+  *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
+  *         contains the clock calibration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
+                                                   const FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
+  if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+  {
+    assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
+    assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
+    assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
+  }
+
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+    {
+      /* Bypass clock calibration */
+      SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock divider */
+      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV,
+                 (sCcuConfig->ClockDivider << FDCANCCU_CCFG_CDIV_Pos));
+    }
+    else /* sCcuConfig->ClockCalibration == ENABLE */
+    {
+      /* Clock calibration unit generates time quanta clock */
+      CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock calibration unit */
+      MODIFY_REG(FDCAN_CCU->CCFG,
+                 (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
+                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) |
+                  sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+
+      /* Configure the start value of the calibration watchdog counter */
+      MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
+}
+
+/**
+  * @brief  Reset the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calibration software reset */
+    SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Counter clock calibration counter.
+  *         This parameter can be a value of @arg FDCAN_calibration_counter.
+  * @retval Value clock calibration counter value
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
+
+  if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
+  {
+    return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
+  }
+  else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
+  {
+    return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
+  }
+  else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
+  {
+    return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN reception filter according to the specified
+  *         parameters in the FDCAN_FilterTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+  *         contains the filter configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
+{
+  uint32_t FilterElementW1;
+  uint32_t FilterElementW2;
+  uint32_t *FilterAddress;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check function parameters */
+    assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+    assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+    if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
+    }
+
+    if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+        assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U)       |
+                           (sFilterConfig->FilterID1 << 16U)       |
+                           (sFilterConfig->IsCalibrationMsg << 8U) |
+                           sFilterConfig->RxBufferIndex);
+      }
+      else
+      {
+        FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
+                           (sFilterConfig->FilterConfig << 27U) |
+                           (sFilterConfig->FilterID1 << 16U)    |
+                           sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+    }
+    else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+        assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build first word of filter element */
+      FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+      /* Build second word of filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW2 = sFilterConfig->RxBufferIndex;
+      }
+      else
+      {
+        FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+      FilterAddress++;
+      *FilterAddress = FilterElementW2;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN global filter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+                                               uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt,
+                                               uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure global filter */
+    hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos)  |
+                             (NonMatchingExt << FDCAN_GFC_ANFE_Pos)  |
+                             (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
+                             (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the extended ID mask.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Mask Extended ID Mask.
+  *         This parameter must be a number between 0 and 0x1FFFFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the extended ID mask */
+    hfdcan->Instance->XIDAM = Mask;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the Rx FIFO operation mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @param  OperationMode operation mode.
+  *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+  assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (RxFifo == FDCAN_RX_FIFO0)
+    {
+      /* Select FIFO 0 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, (OperationMode << FDCAN_RXF0C_F0OM_Pos));
+    }
+    else /* RxFifo == FDCAN_RX_FIFO1 */
+    {
+      /* Select FIFO 1 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, (OperationMode << FDCAN_RXF1C_F1OM_Pos));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FIFO watermark.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  FIFO select the FIFO to be configured.
+  *         This parameter can be a value of @arg FDCAN_FIFO_watermark.
+  * @param  Watermark level for FIFO watermark interrupt.
+  *         This parameter must be a number between:
+  *           - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
+  *           - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
+  if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
+  }
+  else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Set the level for FIFO watermark interrupt */
+    if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+    {
+      MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
+    }
+    else if (FIFO == FDCAN_CFG_RX_FIFO0)
+    {
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
+    }
+    else /* FIFO == FDCAN_CFG_RX_FIFO1 */
+    {
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the RAM watchdog.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
+  *         This parameter must be a number between 0x00 and 0xFF,
+  *         with the reset value of 0x00 the counter is disabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the RAM watchdog counter start value */
+    MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampPrescaler Timestamp Counter Prescaler.
+  *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure prescaler */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampOperation Timestamp counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timestamp.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timestamp counter */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timestamp counter */
+    CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timestamp counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Timestamp counter value
+  */
+uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+  * @brief  Reset the timestamp counter to zero.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+  {
+    /* Reset timestamp counter.
+       Actually any write operation to TSCV clears the counter */
+    CLEAR_REG(hfdcan->Instance->TSCV);
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset external counter */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeoutOperation Timeout counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
+  * @param  TimeoutPeriod Start value of the timeout down-counter.
+  *         This parameter must be a number between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+                                                 uint32_t TimeoutPeriod)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Select timeout operation and configure period */
+    MODIFY_REG(hfdcan->Instance->TOCC,
+               (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timeout counter */
+    SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timeout counter */
+    CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timeout counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Timeout counter value
+  */
+uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+  * @brief  Reset the timeout counter to its start value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+  {
+    /* Reset timeout counter to start value */
+    CLEAR_REG(hfdcan->Instance->TOCV);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset counter: controlled only by FIFO empty state */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TdcOffset Transmitter Delay Compensation Offset.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+                                                      uint32_t TdcFilter)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+  assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure TDC offset and filter window */
+    hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable transmitter delay compensation */
+    SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable transmitter delay compensation */
+    CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to ISO 11898-1 standard.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable Non ISO protocol mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable Non ISO protocol mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable edge filtering during bus integration.
+  *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable edge filtering */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable edge filtering during bus integration.
+  *         One dominant tq is required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable edge filtering */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+  *  @brief    Control functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_Start                         : Start the FDCAN module
+      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
+      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding
+                                                    transmission request
+      (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
+      (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
+      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
+      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the
+                                                    message RAM
+      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone
+                                                    into the message RAM
+      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
+      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
+      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
+      (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
+      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending
+                                                    on the selected Tx buffer
+      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
+      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
+      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
+      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the FDCAN module.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Reset the FDCAN ErrorCode */
+    hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the FDCAN module and enable access to configuration registers.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Request initialisation */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Wait until the INIT bit into CCCR register is set */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Reset counter */
+    Counter = 0U;
+
+    /* Exit from Sleep mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+    /* Wait until FDCAN exits sleep mode */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable configuration change */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+    /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+    hfdcan->LatestTxFifoQRequest = 0U;
+
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                const uint8_t *pTxData)
+{
+  uint32_t PutIndex;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx FIFO/Queue is not full */
+    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Retrieve the Tx FIFO PutIndex */
+      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+      /* Add the message to the Tx FIFO/Queue */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+      /* Activate the corresponding transmission request */
+      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to a dedicated Tx buffer
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  *         This parameter can be a value of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                 const uint8_t *pTxData, uint32_t BufferIndex)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+  assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the selected buffer has an allocated area into the RAM */
+    if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that there is no transmission request pending for the selected buffer */
+    if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Add the message to the Tx buffer */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable transmission request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add transmission request */
+    hfdcan->Instance->TXBAR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Tx buffer index of last Tx FIFO/Queue request
+  *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+  *          - 0 if no Tx FIFO/Queue request have been submitted.
+  */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return Last Tx FIFO/Queue Request Buffer */
+  return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+  * @brief  Abort transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add cancellation request */
+    hfdcan->Instance->TXBCR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxLocation Location of the received message to be read.
+  *         This parameter can be a value of @arg FDCAN_Rx_location.
+  * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+  * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+                                         FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+  uint32_t *RxAddress;
+  uint8_t  *pData;
+  uint32_t ByteCounter;
+  uint32_t GetIndex = 0;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Check that the Rx FIFO 0 is full & overwrite mode is on */
+        if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
+        {
+          if (((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+          {
+            /* When overwrite status is on discard first message in FIFO */
+            GetIndex = 1U;
+          }
+        }
+
+        /* Calculate Rx FIFO 0 element index */
+        GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+
+        /* Calculate Rx FIFO 0 element address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+      }
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 1 is not empty */
+      if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Check that the Rx FIFO 1 is full & overwrite mode is on */
+        if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
+        {
+          if (((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+          {
+            /* When overwrite status is on discard first message in FIFO */
+            GetIndex = 1U;
+          }
+        }
+
+        /* Calculate Rx FIFO 1 element index */
+        GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+
+        /* Calculate Rx FIFO 1 element address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+      }
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Check that the selected buffer has an allocated area into the RAM */
+      if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx buffer address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+      }
+    }
+
+    /* Retrieve IdType */
+    pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+    }
+    else /* Extended ID element */
+    {
+      pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment RxAddress pointer to second word of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve RxTimestamp */
+    pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
+
+    /* Retrieve BitRateSwitch */
+    pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve FilterIndex */
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
+
+    /* Retrieve NonMatchingFrame */
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
+
+    /* Increment RxAddress pointer to payload of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve Rx payload */
+    pData = (uint8_t *)RxAddress;
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
+    {
+      pRxData[ByteCounter] = pData[ByteCounter];
+    }
+
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF0A = GetIndex;
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF1A = GetIndex;
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Clear the New Data flag of the current Rx buffer */
+      if (RxLocation < FDCAN_RX_BUFFER32)
+      {
+        hfdcan->Instance->NDAT1 = ((uint32_t)1U << RxLocation);
+      }
+      else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+      {
+        hfdcan->Instance->NDAT2 = ((uint32_t)1U << (RxLocation & 0x1FU));
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+  uint32_t *TxEventAddress;
+  uint32_t GetIndex;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx Event FIFO has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx event FIFO is not empty */
+    if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+      return HAL_ERROR;
+    }
+
+    /* Calculate Tx event FIFO element address */
+    GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+    TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
+
+    /* Retrieve IdType */
+    pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+    }
+    else /* Extended ID element */
+    {
+      pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve TxFrameType */
+    pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+    TxEventAddress++;
+
+    /* Retrieve TxTimestamp */
+    pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
+
+    /* Retrieve BitRateSwitch */
+    pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve EventType */
+    pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+    /* Retrieve MessageMarker */
+    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
+
+    /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+    hfdcan->Instance->TXEFA = GetIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get high priority message status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                         FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+  HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+  HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+  HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+  HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get protocol status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                              FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+  uint32_t StatusReg;
+
+  /* Read the protocol status register */
+  StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+  /* Fill the protocol status structure */
+  ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+  ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+  ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+  ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+  ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+  ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+  ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+  ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+  ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+  ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+  ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get error counter values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
+                                             FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+  uint32_t CountersReg;
+
+  /* Read the error counters register */
+  CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+  /* Fill the error counters structure */
+  ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+  ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+  ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+  ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if a new message is received in the selected Rx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxBufferIndex Rx buffer index.
+  *         This parameter must be a number between 0 and 63.
+  * @retval Status
+  *          - 0 : No new message on RxBufferIndex.
+  *          - 1 : New message received on RxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
+  uint32_t NewData1 = hfdcan->Instance->NDAT1;
+  uint32_t NewData2 = hfdcan->Instance->NDAT2;
+
+  /* Check new message reception on the selected buffer */
+  if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
+      ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
+  {
+    return 0;
+  }
+
+  /* Clear the New Data flag of the current Rx buffer */
+  if (RxBufferIndex < 32U)
+  {
+    hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
+  }
+  else /* 32 <= RxBufferIndex <= 63 */
+  {
+    hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
+  }
+
+  return 1;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxBufferIndex Tx buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval Status
+  *          - 0 : No pending transmission request on TxBufferIndex.
+  *          - 1 : Pending transmission request on TxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+  /* Check pending transmission request on the selected buffer */
+  if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+  {
+    return 0;
+  }
+  return 1;
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @retval Rx FIFO fill level.
+  */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+  uint32_t FillLevel;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+  if (RxFifo == FDCAN_RX_FIFO0)
+  {
+    FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+  }
+  else /* RxFifo == FDCAN_RX_FIFO1 */
+  {
+    FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+  }
+
+  /* Return Rx FIFO fill level */
+  return FillLevel;
+}
+
+/**
+  * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
+  *         elements starting from Tx FIFO GetIndex.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Tx FIFO free level.
+  */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t FreeLevel;
+
+  FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+  /* Return Tx FIFO free level */
+  return FreeLevel;
+}
+
+/**
+  * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Status
+  *          - 0 : Normal FDCAN operation.
+  *          - 1 : Restricted Operation Mode active.
+  */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t OperationMode;
+
+  /* Get Operation Mode */
+  OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+  return OperationMode;
+}
+
+/**
+  * @brief  Exit Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Exit Restricted Operation mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
+  *  @brief    TT Configuration and control functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TT Configuration and control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
+      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
+      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
+      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
+      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
+      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
+      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
+        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
+        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark IT
+      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
+      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
+      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
+      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
+        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external
+                                                            schedule
+        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
+      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize TT operation parameters.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams)
+{
+  uint32_t tickstart;
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
+  assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
+  assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
+  assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
+  assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
+  if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+  {
+    assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+  {
+    assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
+    assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
+    assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
+    assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
+    assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
+    assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Stop local time in order to enable write access to the other bits of TURCF register */
+    CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until the ELT bit into TURCF register is reset */
+    while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Configure TUR (Time Unit Ratio) */
+    MODIFY_REG(hfdcan->ttcan->TURCF,
+               (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
+               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) |
+                (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+
+    /* Enable local time */
+    SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Configure TT operation */
+    MODIFY_REG(hfdcan->ttcan->TTOCF,
+               (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
+               (pTTParams->OperationMode                           | \
+                pTTParams->TimeMaster                              | \
+                (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
+                (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
+                 (pTTParams->GapEnable                            | \
+                  (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
+                  pTTParams->EvtTrigPolarity));
+    }
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
+                 (pTTParams->ExternalClkSync  | \
+                  pTTParams->GlobalTimeFilter | \
+                  pTTParams->ClockCalibration));
+    }
+
+    /* Configure system matrix limits */
+    MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM,
+                 (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
+                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) |
+                  (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+    }
+    if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
+    }
+
+    /* Configure input triggers: Stop watch and Event */
+    MODIFY_REG(hfdcan->ttcan->TTTS,
+               (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
+               (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
+
+    /* Configure trigger memory start address */
+    StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
+
+    /* Trigger memory elements number */
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
+
+    /* Recalculate End Address */
+    hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
+    hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
+
+    if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+    {
+      /* Update error code.
+         Message RAM overflow */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the allocated Message RAM area */
+      for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+      {
+        *(uint32_t *)(RAMcounter) = 0x00000000;
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  IdType Identifier Type.
+  *         This parameter can be a value of @arg FDCAN_id_type.
+  * @param  Identifier Reference Identifier.
+  *         This parameter must be a number between:
+  *           - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+  *           - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
+  * @param  Payload Enable or disable the additional payload.
+  *         This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
+  *         This parameter is ignored in case of time slaves.
+  *         If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
+  *         following elements are taken from Tx Buffer 0:
+  *          - MessageMarker
+  *          - TxEventFifoControl
+  *          - DataLength
+  *          - Data Bytes (payload):
+  *             - bytes 2-8, for Level 1
+  *             - bytes 5-8, for Level 0 and Level 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType,
+                                                      uint32_t Identifier, uint32_t Payload)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_ID_TYPE(IdType));
+  if (IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
+  }
+  else /* IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure reference message identifier type, identifier and payload */
+    if (IdType == FDCAN_EXTENDED_ID)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS),
+                 (Payload | IdType | Identifier));
+    }
+    else /* IdType == FDCAN_STANDARD_ID */
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS),
+                 (Payload | IdType | (Identifier << 18)));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN trigger according to the specified
+  *         parameters in the FDCAN_TriggerTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
+  *         contains the trigger configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig)
+{
+  uint32_t CycleCode;
+  uint32_t MessageNumber;
+  uint32_t TriggerElementW1;
+  uint32_t TriggerElementW2;
+  uint32_t *TriggerAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
+  if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
+  }
+  assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
+  assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
+  assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
+  assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
+  if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+  {
+    assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
+  }
+  if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+  {
+    if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
+    }
+    else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
+    }
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calculate cycle code */
+    if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+    {
+      CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+    }
+    else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+    {
+      CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
+    }
+
+    /* Build first word of trigger element */
+    TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
+                        (CycleCode << 8)                 | \
+                        sTriggerConfig->TmEventInt       | \
+                        sTriggerConfig->TmEventExt       | \
+                        sTriggerConfig->TriggerType);
+
+    /* Select message number depending on trigger type (transmission or reception) */
+    if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+    {
+      MessageNumber = sTriggerConfig->FilterIndex;
+    }
+    else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+    {
+      MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
+    }
+    else
+    {
+      MessageNumber = 0U;
+    }
+
+    /* Build second word of trigger element */
+    TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
+
+    /* Calculate trigger address */
+    TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
+
+    /* Write trigger element to the message RAM */
+    *TriggerAddress = TriggerElementW1;
+    TriggerAddress++;
+    *TriggerAddress = TriggerElementW2;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule global time adjustment for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimePreset time preset value.
+  *         This parameter must be a number between:
+  *           - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
+  *           or
+  *           - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no global time preset is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure time preset */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule time preset to take effect by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule TUR numerator update for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NewTURNumerator new value of the TUR numerator.
+  *         This parameter must be a number between 0x10000 and 0x1FFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no external clock synchronization is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure new TUR numerator */
+    MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule TUR numerator update by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure stop watch source and polarity.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Source stop watch source.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
+  * @param  Polarity stop watch polarity.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Select stop watch source and polarity */
+    MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeMarkSource time mark source.
+  *         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
+  * @param  TimeMarkValue time mark value (reference).
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @param  RepeatFactor repeat factor of the cycle for which the time mark is valid.
+  *         This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
+  * @param  StartCycle index of the first cycle in which the time mark becomes valid.
+  *         This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+  *         This parameter must be a number between 0 and RepeatFactor.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
+                                                      uint32_t TimeMarkSource, uint32_t TimeMarkValue,
+                                                      uint32_t RepeatFactor, uint32_t StartCycle)
+{
+  uint32_t Counter = 0U;
+  uint32_t CycleCode;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
+  if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
+  }
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable the time mark compare function */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
+
+    if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
+    {
+      /* Calculate cycle code */
+      if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+      {
+        CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+      }
+      else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+      {
+        CycleCode = RepeatFactor + StartCycle;
+      }
+
+      Counter = 0U;
+
+      /* Wait until the LCKM bit into TTTMK register is reset */
+      while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Configure time mark value and cycle code */
+      hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
+
+      Counter = 0U;
+
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Update the register time mark compare source */
+      MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by pin fdcan1_evt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by pin fdcan1_evt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control (finish only) by register time mark interrupt.
+  *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
+  *         the Gap and start the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by register time mark interrupt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by register time mark interrupt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by register time mark interrupt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Transmit next reference message with Next_is_Gap = "1".
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Next is Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Finish a Gap by requesting start of reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_COUNT)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Finish Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure target phase used for external synchronization by event
+  *         trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TargetPhase defines target value of cycle time when a rising edge
+  *         of fdcan1_evt is expected.
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that no external schedule synchronization is pending */
+    if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure cycle time target phase */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
+  *         using event trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable external synchronization */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable external schedule synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_COUNT)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable external synchronization */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get TT operation status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                  FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+{
+  uint32_t TTStatusReg;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  /* Read the TT operation status register */
+  TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
+
+  /* Fill the TT operation status structure */
+  TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
+  TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
+  TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
+  TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
+  TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
+  TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
+  TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
+  TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
+  TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
+  TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
+  TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
+  TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
+  TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
+  TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
+  *  @brief    Interrupts management
+  *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
+      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
+      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
+      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Assign interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->Instance->ILS, ITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList,
+                                                    uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(TTITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  BufferIndexes Tx Buffer Indexes.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  *         This parameter is ignored if ActiveITs does not include one of the following:
+  *           - FDCAN_IT_TX_COMPLETE
+  *           - FDCAN_IT_TX_ABORT_COMPLETE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+                                                 uint32_t BufferIndexes)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ActiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+         but interrupt will only occur if TC is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+         but interrupt will only occur if TCF is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+    }
+
+    /* Enable the selected interrupts */
+    __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(InactiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected interrupts */
+    __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+    if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Transmission Interrupts */
+      CLEAR_REG(hfdcan->Instance->TXBTIE);
+    }
+
+    if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Cancellation Finished Interrupt */
+      CLEAR_REG(hfdcan->Instance->TXBCIE);
+    }
+
+    ITLineSelection = hfdcan->Instance->ILS;
+
+    if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveTTITs indicates which TT interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Enable the selected TT interrupts */
+    __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveTTITs indicates which TT interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected TT interrupts */
+    __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
+
+    ITLineSelection = hfdcan->ttcan->TTILS;
+
+    if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
+    {
+      /* Disable interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles FDCAN interrupt request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t ClkCalibrationITs;
+  uint32_t TxEventFifoITs;
+  uint32_t RxFifo0ITs;
+  uint32_t RxFifo1ITs;
+  uint32_t Errors;
+  uint32_t ErrorStatusITs;
+  uint32_t TransmittedBuffers;
+  uint32_t AbortedBuffers;
+  uint32_t TTSchedSyncITs;
+  uint32_t TTTimeMarkITs;
+  uint32_t TTGlobTimeITs;
+  uint32_t TTDistErrors;
+  uint32_t TTFatalErrors;
+  uint32_t SWTime;
+  uint32_t SWCycleCount;
+  uint32_t itsourceIE;
+  uint32_t itsourceTTIE;
+  uint32_t itflagIR;
+  uint32_t itflagTTIR;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+  TxEventFifoITs &= hfdcan->Instance->IE;
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+  RxFifo0ITs &= hfdcan->Instance->IE;
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+  RxFifo1ITs &= hfdcan->Instance->IE;
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+  Errors &= hfdcan->Instance->IE;
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+  ErrorStatusITs &= hfdcan->Instance->IE;
+  itsourceIE = hfdcan->Instance->IE;
+  itflagIR = hfdcan->Instance->IR;
+
+  /* High Priority Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET)
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+      itsourceTTIE = hfdcan->ttcan->TTIE;
+      itflagTTIR = hfdcan->ttcan->TTIR;
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET)
+      {
+        if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+  {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
+  *  @brief   FDCAN Callback functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_FDCAN_ClockCalibrationCallback
+      (+) HAL_FDCAN_TxEventFifoCallback
+      (+) HAL_FDCAN_RxFifo0Callback
+      (+) HAL_FDCAN_RxFifo1Callback
+      (+) HAL_FDCAN_TxFifoEmptyCallback
+      (+) HAL_FDCAN_TxBufferCompleteCallback
+      (+) HAL_FDCAN_TxBufferAbortCallback
+      (+) HAL_FDCAN_RxBufferNewMessageCallback
+      (+) HAL_FDCAN_HighPriorityMessageCallback
+      (+) HAL_FDCAN_TimestampWraparoundCallback
+      (+) HAL_FDCAN_TimeoutOccurredCallback
+      (+) HAL_FDCAN_ErrorCallback
+      (+) HAL_FDCAN_ErrorStatusCallback
+      (+) HAL_FDCAN_TT_ScheduleSyncCallback
+      (+) HAL_FDCAN_TT_TimeMarkCallback
+      (+) HAL_FDCAN_TT_StopWatchCallback
+      (+) HAL_FDCAN_TT_GlobalTimeCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Clock Calibration callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Event callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo0ITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx FIFO Empty callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Complete callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Cancellation callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Buffer New Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timestamp Wraparound callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout Occurred callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  High Priority Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error status callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ErrorStatusITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Schedule Synchronization callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Time Mark callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Stop Watch callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
+  *         edge (as configured via HAL_FDCAN_TTConfigStopWatch).
+  *         This parameter is a number between 0 and 0xFFFF.
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(SWTime);
+  UNUSED(SWCycleCount);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Global Time callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
+  *  @brief   FDCAN Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
+      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the FDCAN state
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL state
+  */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN state */
+  return hfdcan->State;
+}
+
+/**
+  * @brief  Return the FDCAN error code
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval FDCAN Error Code
+  */
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN error code */
+  return hfdcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate each RAM block start address and size
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA +
+                             (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA +
+                              (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA +
+                                 (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA +
+                              (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Copy Tx message to the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  * @retval none
+ */
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                   const uint8_t *pTxData, uint32_t BufferIndex)
+{
+  uint32_t TxElementW1;
+  uint32_t TxElementW2;
+  uint32_t *TxAddress;
+  uint32_t ByteCounter;
+
+  /* Build first word of Tx header element */
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_STANDARD_ID |
+                   pTxHeader->TxFrameType |
+                   (pTxHeader->Identifier << 18U));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_EXTENDED_ID |
+                   pTxHeader->TxFrameType |
+                   pTxHeader->Identifier);
+  }
+
+  /* Build second word of Tx header element */
+  TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
+                 pTxHeader->TxEventFifoControl |
+                 pTxHeader->FDFormat |
+                 pTxHeader->BitRateSwitch |
+                 (pTxHeader->DataLength << 16U));
+
+  /* Calculate Tx element address */
+  TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+
+  /* Write Tx element header to the message RAM */
+  *TxAddress = TxElementW1;
+  TxAddress++;
+  *TxAddress = TxElementW2;
+  TxAddress++;
+
+  /* Write Tx payload to the message RAM */
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
+  {
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8U)  |
+                  (uint32_t)pTxData[ByteCounter]);
+    TxAddress++;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FDCAN1 */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gfxmmu.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gfxmmu.c
new file mode 100644
index 000000000..fab8cd68d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gfxmmu.c
@@ -0,0 +1,872 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gfxmmu.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Graphic MMU (GFXMMU) peripheral:
+  *           + Initialization and De-initialization.
+  *           + LUT configuration.
+  *           + Modify physical buffer addresses.
+  *           + Packing configuration.
+  *           + Error management.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    *** Initialization ***
+    ======================
+    [..]
+      (#) As prerequisite, fill in the HAL_GFXMMU_MspInit() :
+        (++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
+        (++) If interrupts are used, enable and configure GFXMMU global
+            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+      (#) Configure the number of blocks per line, default value, physical
+          buffer addresses and interrupts using the HAL_GFXMMU_Init() function.
+
+    *** LUT configuration ***
+    =========================
+    [..]
+      (#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a
+          range of lines).
+      (#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
+      (#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.
+
+    *** Modify physical buffer addresses ***
+    ========================================
+    [..]
+      (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
+
+    *** Packing configuration ***
+    =============================
+    [..]
+      (#) Use HAL_GFXMMU_ConfigPacking() to configure packing.
+
+    *** Error management ***
+    ========================
+    [..]
+      (#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when
+          an error occurs. This function will call HAL_GFXMMU_ErrorCallback().
+          Use HAL_GFXMMU_GetError() to get the error code.
+
+    *** De-initialization ***
+    =========================
+    [..]
+      (#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() :
+        (++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
+        (++) If interrupts has been used, disable GFXMMU global interrupt with
+             HAL_NVIC_DisableIRQ().
+      (#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function.
+
+    *** Callback registration ***
+    =============================
+    [..]
+    The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+    Use functions HAL_GFXMMU_RegisterCallback() to register a user callback.
+
+    [..]
+    Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks:
+      (+) ErrorCallback      : GFXMMU error.
+      (+) MspInitCallback    : GFXMMU MspInit.
+      (+) MspDeInitCallback  : GFXMMU MspDeInit.
+    [..]
+    This function takes as parameters the HAL peripheral handle, the callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function.
+    HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the callback ID.
+    [..]
+    This function allows to reset following callbacks:
+      (+) ErrorCallback      : GFXMMU error.
+      (+) MspInitCallback    : GFXMMU MspInit.
+      (+) MspDeInitCallback  : GFXMMU MspDeInit.
+
+    [..]
+    By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (overridden) functions:
+    examples HAL_GFXMMU_ErrorCallback().
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (overridden) functions in the HAL_GFXMMU_Init
+    and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit
+    or HAL_GFXMMU_Init function.
+
+    [..]
+    When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+#if defined(GFXMMU)
+/** @defgroup GFXMMU GFXMMU
+  * @brief GFXMMU HAL driver module
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup GFXMMU_Private_Constants GFXMMU Private Constants
+  * @{
+  */
+#define GFXMMU_LUTXL_FVB_OFFSET     8U
+#define GFXMMU_LUTXL_LVB_OFFSET     16U
+#define GFXMMU_CR_ITS_MASK          0x1FU
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions
+  * @{
+  */
+
+/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the GFXMMU.
+      (+) De-initialize the GFXMMU.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GFXMMU according to the specified parameters in the
+  *         GFXMMU_InitTypeDef structure and initialize the associated handle.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check GFXMMU handle */
+  if (hgfxmmu == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
+    assert_param(IS_GFXMMU_BLOCK_SIZE(hgfxmmu->Init.BlockSize));
+    assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.AddressTranslation));
+    assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address));
+    assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address));
+    assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address));
+    assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address));
+    assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation));
+
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+    /* Reset callback pointers to the weak predefined callbacks */
+    hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
+
+    /* Call GFXMMU MSP init function */
+    if (hgfxmmu->MspInitCallback == NULL)
+    {
+      hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
+    }
+    hgfxmmu->MspInitCallback(hgfxmmu);
+#else
+    /* Call GFXMMU MSP init function */
+    HAL_GFXMMU_MspInit(hgfxmmu);
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
+
+    /* Configure GFXMMU_CR register */
+    hgfxmmu->Instance->CR = 0U;
+    hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlockSize);
+    if (hgfxmmu->Init.AddressTranslation == ENABLE)
+    {
+      hgfxmmu->Instance->CR |= GFXMMU_CR_ATE;
+    }
+    if (hgfxmmu->Init.Interrupts.Activation == ENABLE)
+    {
+      assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts));
+      hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts;
+    }
+
+    /* Configure default value on GFXMMU_DVR register */
+    hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
+
+    /* Configure physical buffer addresses on GFXMMU_BxCR registers */
+    hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
+    hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
+    hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
+    hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address;
+
+    /* Reset GFXMMU error code */
+    hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
+
+    /* Set GFXMMU to ready state */
+    hgfxmmu->State = HAL_GFXMMU_STATE_READY;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  De-initialize the GFXMMU.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check GFXMMU handle */
+  if (hgfxmmu == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
+
+    /* Disable all interrupts on GFXMMU_CR register */
+    hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
+                               GFXMMU_CR_AMEIE);
+
+    /* Call GFXMMU MSP de-init function */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+    if (hgfxmmu->MspDeInitCallback == NULL)
+    {
+      hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
+    }
+    hgfxmmu->MspDeInitCallback(hgfxmmu);
+#else
+    HAL_GFXMMU_MspDeInit(hgfxmmu);
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
+
+    /* Set GFXMMU to reset state */
+    hgfxmmu->State = HAL_GFXMMU_STATE_RESET;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Initialize the GFXMMU MSP.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval None.
+  */
+__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxmmu);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXMMU_MspInit could be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  De-initialize the GFXMMU MSP.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval None.
+  */
+__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxmmu);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXMMU_MspDeInit could be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a user GFXMMU callback
+  *         to be used instead of the weak predefined callback.
+  * @param  hgfxmmu GFXMMU handle.
+  * @param  CallbackID ID of the callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @param  pCallback pointer to the callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
+                                              HAL_GFXMMU_CallbackIDTypeDef CallbackID,
+                                              pGFXMMU_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* update the error code */
+    hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (HAL_GFXMMU_STATE_READY == hgfxmmu->State)
+    {
+      switch (CallbackID)
+      {
+        case HAL_GFXMMU_ERROR_CB_ID :
+          hgfxmmu->ErrorCallback = pCallback;
+          break;
+        case HAL_GFXMMU_MSPINIT_CB_ID :
+          hgfxmmu->MspInitCallback = pCallback;
+          break;
+        case HAL_GFXMMU_MSPDEINIT_CB_ID :
+          hgfxmmu->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
+    {
+      switch (CallbackID)
+      {
+        case HAL_GFXMMU_MSPINIT_CB_ID :
+          hgfxmmu->MspInitCallback = pCallback;
+          break;
+        case HAL_GFXMMU_MSPDEINIT_CB_ID :
+          hgfxmmu->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* update the error code */
+      hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Unregister a user GFXMMU callback.
+  *         GFXMMU callback is redirected to the weak predefined callback.
+  * @param  hgfxmmu GFXMMU handle.
+  * @param  CallbackID ID of the callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
+                                                HAL_GFXMMU_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_GFXMMU_STATE_READY == hgfxmmu->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_GFXMMU_ERROR_CB_ID :
+        hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
+        break;
+      case HAL_GFXMMU_MSPINIT_CB_ID :
+        hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
+        break;
+      case HAL_GFXMMU_MSPDEINIT_CB_ID :
+        hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_GFXMMU_MSPINIT_CB_ID :
+        hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
+        break;
+      case HAL_GFXMMU_MSPDEINIT_CB_ID :
+        hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update the error code */
+    hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions
+  *  @brief    GFXMMU operation functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure LUT.
+      (+) Modify physical buffer addresses.
+      (+) Configure packing.
+      (+) Manage error.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to copy LUT from flash to look up RAM.
+  * @param  hgfxmmu GFXMMU handle.
+  * @param  FirstLine First line enabled on LUT.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
+  * @param  LinesNumber Number of lines enabled on LUT.
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
+  * @param  Address Start address of LUT in flash.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu,
+                                       uint32_t FirstLine,
+                                       uint32_t LinesNumber,
+                                       uint32_t Address)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
+  assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
+  assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
+
+  /* Check GFXMMU state and coherent parameters */
+  if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check address translation status */
+  else if ((hgfxmmu->Instance->CR & GFXMMU_CR_ATE) == 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t current_address;
+    uint32_t current_line;
+    uint32_t lutxl_address;
+    uint32_t lutxh_address;
+
+    /* Initialize local variables */
+    current_address = Address;
+    current_line    = 0U;
+    lutxl_address   = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
+    lutxh_address   = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
+
+    /* Copy LUT from flash to look up RAM */
+    while (current_line < LinesNumber)
+    {
+      *((uint32_t *)lutxl_address) = *((uint32_t *)current_address);
+      current_address += 4U;
+      *((uint32_t *)lutxh_address) = *((uint32_t *)current_address);
+      current_address += 4U;
+      lutxl_address += 8U;
+      lutxh_address += 8U;
+      current_line++;
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to disable a range of LUT lines.
+  * @param  hgfxmmu GFXMMU handle.
+  * @param  FirstLine First line to disable on LUT.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
+  * @param  LinesNumber Number of lines to disable on LUT.
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu,
+                                             uint32_t FirstLine,
+                                             uint32_t LinesNumber)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
+  assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
+  assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
+
+  /* Check GFXMMU state and coherent parameters */
+  if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check address translation status */
+  else if ((hgfxmmu->Instance->CR & GFXMMU_CR_ATE) == 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t current_line;
+    uint32_t lutxl_address;
+    uint32_t lutxh_address;
+
+    /* Initialize local variables */
+    current_line    = 0U;
+    lutxl_address   = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
+    lutxh_address   = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
+
+    /* Disable LUT lines */
+    while (current_line < LinesNumber)
+    {
+      *((uint32_t *)lutxl_address) = 0U;
+      *((uint32_t *)lutxh_address) = 0U;
+      lutxl_address += 8U;
+      lutxh_address += 8U;
+      current_line++;
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to configure one line of LUT.
+  * @param  hgfxmmu GFXMMU handle.
+  * @param  lutLine LUT line parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
+  assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber));
+  assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus));
+  assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock));
+  assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock));
+  assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset));
+
+  /* Check GFXMMU state */
+  if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check address translation status */
+  else if ((hgfxmmu->Instance->CR & GFXMMU_CR_ATE) == 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t lutxl_address;
+    uint32_t lutxh_address;
+
+    /* Initialize local variables */
+    lutxl_address   = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]);
+    lutxh_address   = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]);
+
+    /* Configure LUT line */
+    if (lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE)
+    {
+      /* Enable and configure LUT line */
+      *((uint32_t *)lutxl_address) = (lutLine->LineStatus |
+                                      (lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) |
+                                      (lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET));
+      *((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset;
+    }
+    else
+    {
+      /* Disable LUT line */
+      *((uint32_t *)lutxl_address) = 0U;
+      *((uint32_t *)lutxh_address) = 0U;
+    }
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to modify physical buffer addresses.
+  * @param  hgfxmmu GFXMMU handle.
+  * @param  Buffers Buffers parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
+  assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address));
+  assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address));
+  assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address));
+  assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address));
+
+  /* Check GFXMMU state */
+  if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Modify physical buffer addresses on GFXMMU_BxCR registers */
+    hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
+    hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
+    hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
+    hgfxmmu->Instance->B3CR = Buffers->Buf3Address;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to configure packing.
+  * @param  hgfxmmu GFXMMU handle.
+  * @param  pPacking Packing parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXMMU_ConfigPacking(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_PackingTypeDef *pPacking)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer0Activation));
+  assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer1Activation));
+  assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer2Activation));
+  assert_param(IS_FUNCTIONAL_STATE(pPacking->Buffer3Activation));
+  assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer0Mode));
+  assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer1Mode));
+  assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer2Mode));
+  assert_param(IS_GFXMMU_PACKING_MODE(pPacking->Buffer3Mode));
+  assert_param(IS_GFXMMU_DEFAULT_ALPHA_VALUE(pPacking->DefaultAlpha));
+
+  /* Check GFXMMU state */
+  if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check block size is set to 12-byte*/
+  else if ((hgfxmmu->Instance->CR & GFXMMU_CR_BS) == 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t reg_value = 0U;
+
+    /* Configure packing for all buffers on GFXMMU_CR register */
+    if (pPacking->Buffer0Activation == ENABLE)
+    {
+      reg_value |= ((pPacking->Buffer0Mode << GFXMMU_CR_B0PM_Pos) | GFXMMU_CR_B0PE);
+    }
+    if (pPacking->Buffer1Activation == ENABLE)
+    {
+      reg_value |= ((pPacking->Buffer1Mode << GFXMMU_CR_B1PM_Pos) | GFXMMU_CR_B1PE);
+    }
+    if (pPacking->Buffer2Activation == ENABLE)
+    {
+      reg_value |= ((pPacking->Buffer2Mode << GFXMMU_CR_B2PM_Pos) | GFXMMU_CR_B2PE);
+    }
+    if (pPacking->Buffer3Activation == ENABLE)
+    {
+      reg_value |= ((pPacking->Buffer3Mode << GFXMMU_CR_B3PM_Pos) | GFXMMU_CR_B3PE);
+    }
+    hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0PE_Msk | GFXMMU_CR_B0PM_Msk |
+                               GFXMMU_CR_B1PE_Msk | GFXMMU_CR_B1PM_Msk |
+                               GFXMMU_CR_B2PE_Msk | GFXMMU_CR_B2PM_Msk |
+                               GFXMMU_CR_B3PE_Msk | GFXMMU_CR_B3PM_Msk);
+    hgfxmmu->Instance->CR |= reg_value;
+
+    /* Configure default alpha value on GFXMMU_DAR register */
+    hgfxmmu->Instance->DAR = pPacking->DefaultAlpha;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function handles the GFXMMU interrupts.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval None.
+  */
+void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  uint32_t flags, interrupts, error;
+
+  /* Read current flags and interrupts and determine which error occurs */
+  flags = hgfxmmu->Instance->SR;
+  interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK);
+  error = (flags & interrupts);
+
+  if (error != 0U)
+  {
+    /* Clear flags on GFXMMU_FCR register */
+    hgfxmmu->Instance->FCR = error;
+
+    /* Update GFXMMU error code */
+    hgfxmmu->ErrorCode |= error;
+
+    /* Call GFXMMU error callback */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+    hgfxmmu->ErrorCallback(hgfxmmu);
+#else
+    HAL_GFXMMU_ErrorCallback(hgfxmmu);
+#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
+  }
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval None.
+  */
+__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxmmu);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_GFXMMU_ErrorCallback could be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
+  *  @brief    GFXMMU state functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### State functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Get GFXMMU handle state.
+      (+) Get GFXMMU error code.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to get the current GFXMMU handle state.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval GFXMMU state.
+  */
+HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  /* Return GFXMMU handle state */
+  return hgfxmmu->State;
+}
+
+/**
+  * @brief  This function allows to get the current GFXMMU error code.
+  * @param  hgfxmmu GFXMMU handle.
+  * @retval GFXMMU error code.
+  */
+uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
+{
+  uint32_t error_code;
+
+  /* Enter in critical section */
+  __disable_irq();
+
+  /* Store and reset GFXMMU error code */
+  error_code = hgfxmmu->ErrorCode;
+  hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
+
+  /* Exit from critical section */
+  __enable_irq();
+
+  /* Return GFXMMU error code */
+  return error_code;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+#endif /* GFXMMU */
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gfxtim.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gfxtim.c
new file mode 100644
index 000000000..769e3d90c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gfxtim.c
@@ -0,0 +1,2032 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gfxtim.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Multi-function Digital Filter (GFXTIM)
+  *          peripheral:
+  *           + Initialization and de-initialization
+  *           + Integrated frame and line clock generation
+  *           + One absolute frame counter with one compare channel
+  *           + Two auto reload relative frame counter
+  *           + One line timer with two compare channel
+  *           + External Tearing Effect line management & synchronization
+  *           + Four programmable event generators with external trigger generation
+  *           + One watchdog counter
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    *** Initialization and de-initialization ***
+    ============================================
+    [..]
+      (#) User has first to initialize GFXTIM.
+      (#) As prerequisite, fill in the HAL_GFXTIM_MspInit() :
+        (++) Enable GFXTIM with __HAL_RCC_GFXTIM_CLK_ENABLE
+        (++) Enable the clocks for the used GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure GFXTIM
+             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+
+    [..]
+      (#) User can de-initialize GFXTIM with HAL_GFXTIM_DeInit() function.
+
+    *** generic functions ***
+    =========================
+    [..]
+      (#) HAL_GFXTIM_IRQHandler will be called when GFXTIM interrupt occurs.
+      (#) HAL_GFXTIM_ErrorCallback will be called when GFXTIM or ADF error occurs.
+      (#) Use HAL_GFXTIM_GetState() to get the current GFXTIM or ADF instance state.
+      (#) Use HAL_GFXTIM_GetErrorCode() to get the current GFXTIM or ADF instance error code.
+
+
+
+#if defined(GENERATOR_CALLBACKS_REGISTERING_AVAILABLE)
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_GFXTIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_GFXTIM_RegisterCallback() to register an interrupt callback.
+
+  Function @ref HAL_GFXTIM_RegisterCallback() registers following callbacks:
+      (+) HAL_GFXTIM_AbsoluteTimer_AFCC1Callback
+      (+) HAL_GFXTIM_AbsoluteTimer_AFCOFCallback
+      (+) HAL_GFXTIM_AbsoluteTimer_ALCC1Callback
+      (+) HAL_GFXTIM_AbsoluteTimer_ALCC2Callback
+      (+) HAL_GFXTIM_AbsoluteTimer_ALCOFCallback
+      (+) HAL_GFXTIM_RelativeTimer_RFC1RCallback
+      (+) HAL_GFXTIM_RelativeTimer_RFC2RCallback
+      (+) HAL_GFXTIM_TECallback
+      (+) HAL_GFXTIM_EventGenerator_EV1Callback
+      (+) HAL_GFXTIM_EventGenerator_EV2Callback
+      (+) HAL_GFXTIM_EventGenerator_EV3Callback
+      (+) HAL_GFXTIM_EventGenerator_EV4Callback
+      (+) HAL_GFXTIM_WatchdogTimer_AlarmCallback
+      (+) HAL_GFXTIM_WatchdogTimer_PreAlarmCallback
+      (+) MspInitCallback
+      (+) MspDeInitCallback
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use function @ref HAL_GFXTIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_GFXTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function resets following callbacks:
+      (+) HAL_GFXTIM_AbsoluteTimer_AFCC1Callback
+      (+) HAL_GFXTIM_AbsoluteTimer_AFCOFCallback
+      (+) HAL_GFXTIM_AbsoluteTimer_ALCC1Callback
+      (+) HAL_GFXTIM_AbsoluteTimer_ALCC2Callback
+      (+) HAL_GFXTIM_AbsoluteTimer_ALCOFCallback
+      (+) HAL_GFXTIM_RelativeTimer_RFC1RCallback
+      (+) HAL_GFXTIM_RelativeTimer_RFC2RCallback
+      (+) HAL_GFXTIM_TECallback
+      (+) HAL_GFXTIM_EventGenerator_EV1Callback
+      (+) HAL_GFXTIM_EventGenerator_EV2Callback
+      (+) HAL_GFXTIM_EventGenerator_EV3Callback
+      (+) HAL_GFXTIM_EventGenerator_EV4Callback
+      (+) HAL_GFXTIM_WatchdogTimer_AlarmCallback
+      (+) HAL_GFXTIM_WatchdogTimer_PreAlarmCallback
+      (+) MspInitCallback
+      (+) MspDeInitCallback
+
+  By default, after the HAL_GFXTIM_Init() and when the state is HAL_GFXTIM_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_GFXTIM_ErrorCallback(), @ref HAL_GFXTIM_CalculateCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_GFXTIM_Init()/ @ref HAL_GFXTIM_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_GFXTIM_Init()/ @ref HAL_GFXTIM_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_GFXTIM_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_GFXTIM_STATE_READY or HAL_GFXTIM_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_GFXTIM_RegisterCallback() before calling @ref HAL_GFXTIM_DeInit()
+  or HAL_GFXTIM_Init() function.
+
+  When The compilation define USE_HAL_GFXTIM_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+#endif
+
+    @endverbatim
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_GFXTIM_MODULE_ENABLED
+#if defined(GFXTIM)
+/** @defgroup GFXTIM GFXTIM
+  * @brief GFXTIM HAL module driver
+  * @{
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup GFXTIM_Exported_Functions  GFXTIM Exported Functions
+  * @{
+  */
+
+/** @defgroup GFXTIM_Exported_Functions_Group1  Initialization and de-initialization functions
+  * @brief    Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Initialize the GFXTIM instance.
+      (+) De-initialize the GFXTIM instance.
+      (+) Register and unregister callbacks.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GFXTIM instance according to the specified parameters
+  *         in the GFXTIM_InitTypeDef structure and initialize the associated handle.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_Init(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  if (hgfxtim != NULL)
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_SYNC_SRC(hgfxtim->Init.SynchroSrc));
+    assert_param(IS_GFXTIM_TE_SRC(hgfxtim->Init.TearingEffectSrc));
+    assert_param(IS_GFXTIM_TE_POLARITY(hgfxtim->Init.TearingEffectPolarity));
+    assert_param(IS_GFXTIM_INTERRUPT(hgfxtim->Init.TearingEffectInterrupt));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_RESET)
+    {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+      /* Reset callback pointers to the weak predefined callbacks */
+      hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback = HAL_GFXTIM_AbsoluteTimer_AFCC1Callback;
+      hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback = HAL_GFXTIM_AbsoluteTimer_AFCOFCallback;
+      hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback = HAL_GFXTIM_AbsoluteTimer_ALCC1Callback;
+      hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback = HAL_GFXTIM_AbsoluteTimer_ALCC2Callback;
+      hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback = HAL_GFXTIM_AbsoluteTimer_ALCOFCallback;
+      hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback = HAL_GFXTIM_RelativeTimer_RFC1RCallback;
+      hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback = HAL_GFXTIM_RelativeTimer_RFC2RCallback;
+      hgfxtim->HAL_GFXTIM_TECallback = HAL_GFXTIM_TECallback;
+      hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback = HAL_GFXTIM_EventGenerator_EV1Callback;
+      hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback = HAL_GFXTIM_EventGenerator_EV2Callback;
+      hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback = HAL_GFXTIM_EventGenerator_EV3Callback;
+      hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback = HAL_GFXTIM_EventGenerator_EV4Callback;
+      hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback = HAL_GFXTIM_WatchdogTimer_AlarmCallback;
+      hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback = HAL_GFXTIM_WatchdogTimer_PreAlarmCallback;
+      hgfxtim->ErrorCallback = HAL_GFXTIM_ErrorCallback;
+
+      /* Call GFXTIM MSP init function */
+      if (hgfxtim->MspInitCallback == NULL)
+      {
+        hgfxtim->MspInitCallback = HAL_GFXTIM_MspInit;
+      }
+      hgfxtim->MspInitCallback(hgfxtim);
+#else /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+      /* Call GFXTIM MSP init function */
+      HAL_GFXTIM_MspInit(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+
+      /* Set Synchronization signals sources (HSYNC and VSYNC), Tearing Effect source and polarity,  */
+      MODIFY_REG(hgfxtim->Instance->CR, \
+                 GFXTIM_CR_SYNCS | GFXTIM_CR_TES | GFXTIM_CR_TEPOL,
+                 hgfxtim->Init.SynchroSrc | hgfxtim->Init.TearingEffectSrc | hgfxtim->Init.TearingEffectPolarity);
+
+      /* Set tearing effect interrupt */
+      MODIFY_REG(hgfxtim->Instance->IER, GFXTIM_IER_TEIE,
+                 (hgfxtim->Init.TearingEffectInterrupt << GFXTIM_IER_TEIE_Pos));
+
+      /* Update error code and state */
+      hgfxtim->ErrorCode = GFXTIM_ERROR_NONE;
+      hgfxtim->State = HAL_GFXTIM_STATE_READY;
+      status = HAL_OK;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  De-initialize the GFXTIM instance.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_DeInit(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  if (hgfxtim != NULL)
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Call GFXTIM MSP deinit function */
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+      if (hgfxtim->MspDeInitCallback == NULL)
+      {
+        hgfxtim->MspDeInitCallback = HAL_GFXTIM_MspDeInit;
+      }
+      hgfxtim->MspDeInitCallback(hgfxtim);
+#else /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+      HAL_GFXTIM_MspDeInit(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+
+      /* Update state */
+      hgfxtim->State = HAL_GFXTIM_STATE_RESET;
+      status = HAL_OK;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the GFXTIM instance MSP.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_MspInit(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_MspInit could be implemented in the user file */
+}
+
+/**
+  * @brief  De-initialize the GFXTIM instance MSP.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_MspDeInit(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_MspDeInit could be implemented in the user file */
+}
+
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a user GFXTIM callback to be used instead of the weak predefined callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  CallbackID ID of the callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_GFXTIM_AFC_COMPARE1_CB_ID   Absolute frame counter compare 1 callback ID
+  *           @arg @ref HAL_GFXTIM_AFC_OVERFLOW_CB_ID   Absolute frame counter overflow callback ID
+  *           @arg @ref HAL_GFXTIM_ALC_COMPARE1_CB_ID   Absolute line counter compare 1 callback ID
+  *           @arg @ref HAL_GFXTIM_ALC_COMPARE2_CB_ID   Absolute line counter compare 2 callback ID
+  *           @arg @ref HAL_GFXTIM_ALC_OVERFLOW_CB_ID   Absolute line counter overflow callback ID
+  *           @arg @ref HAL_GFXTIM_RFC1_RELOAD_CB_ID    Relative frame counter 1 reload callback ID
+  *           @arg @ref HAL_GFXTIM_RFC2_RELOAD_CB_ID    Relative frame counter 2 reload callback ID
+  *           @arg @ref HAL_GFXTIM_TE_CB_ID             External tearing effect callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT1_CB_ID         Event events 1 callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT2_CB_ID         Event events 2 callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT3_CB_ID         Event events 3 callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT4_CB_ID         Event events 4 callback ID
+  *           @arg @ref HAL_GFXTIM_WDG_ALARM_CB_ID      Watchdog alarm callback ID
+  *           @arg @ref HAL_GFXTIM_WDG_PREALARM_CB_ID   Watchdog pre alarm callback ID
+  *           @arg @ref HAL_GFXTIM_ERROR_CB_ID          error callback ID
+  *           @arg @ref HAL_GFXTIM_MSP_INIT_CB_ID       MSP initialization user callback ID
+  *           @arg @ref HAL_GFXTIM_MSP_DEINIT_CB_ID     MSP de-initialization user callback ID
+  * @param  pCallback pointer to the callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RegisterCallback(GFXTIM_HandleTypeDef *hgfxtim,
+                                              HAL_GFXTIM_CallbackIDTypeDef CallbackID,
+                                              pGFXTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (pCallback == NULL)
+  {
+    /* Update error code and status */
+    hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_GFXTIM_AFC_COMPARE1_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback = pCallback;
+          break;
+        case HAL_GFXTIM_AFC_OVERFLOW_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback = pCallback;
+          break;
+        case HAL_GFXTIM_ALC_COMPARE1_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback = pCallback;
+          break;
+        case HAL_GFXTIM_ALC_COMPARE2_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback = pCallback;
+          break;
+        case HAL_GFXTIM_ALC_OVERFLOW_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback = pCallback;
+          break;
+        case HAL_GFXTIM_RFC1_RELOAD_CB_ID :
+          hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback = pCallback;
+          break;
+        case HAL_GFXTIM_RFC2_RELOAD_CB_ID :
+          hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback = pCallback;
+          break;
+        case HAL_GFXTIM_TE_CB_ID :
+          hgfxtim->HAL_GFXTIM_TECallback = pCallback;
+          break;
+        case HAL_GFXTIM_EVENT1_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback = pCallback;
+          break;
+        case HAL_GFXTIM_EVENT2_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback = pCallback;
+          break;
+        case HAL_GFXTIM_EVENT3_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback = pCallback;
+          break;
+        case HAL_GFXTIM_EVENT4_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback = pCallback;
+          break;
+        case HAL_GFXTIM_WDG_ALARM_CB_ID :
+          hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback = pCallback;
+          break;
+        case HAL_GFXTIM_WDG_PREALARM_CB_ID :
+          hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback = pCallback;
+          break;
+        case HAL_GFXTIM_ERROR_CB_ID :
+          hgfxtim->ErrorCallback = pCallback;
+          break;
+        case HAL_GFXTIM_MSP_INIT_CB_ID :
+          hgfxtim->MspInitCallback = pCallback;
+          break;
+        case HAL_GFXTIM_MSP_DEINIT_CB_ID :
+          hgfxtim->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* Update error code and status */
+          hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else if (hgfxtim->State == HAL_GFXTIM_STATE_RESET)
+    {
+      switch (CallbackID)
+      {
+        case HAL_GFXTIM_MSP_INIT_CB_ID :
+          hgfxtim->MspInitCallback = pCallback;
+          break;
+        case HAL_GFXTIM_MSP_DEINIT_CB_ID :
+          hgfxtim->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* Update error code and status */
+          hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* Update error code and status */
+      hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK;
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a user GFXTIM callback.
+  *         GFXTIM callback is redirected to the weak predefined callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  CallbackID ID of the callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_GFXTIM_AFC_COMPARE1_CB_ID   Absolute frame counter compare 1 callback ID
+  *           @arg @ref HAL_GFXTIM_AFC_OVERFLOW_CB_ID   Absolute frame counter overflow callback ID
+  *           @arg @ref HAL_GFXTIM_ALC_COMPARE1_CB_ID   Absolute line counter compare 1 callback ID
+  *           @arg @ref HAL_GFXTIM_ALC_COMPARE2_CB_ID   Absolute line counter compare 2 callback ID
+  *           @arg @ref HAL_GFXTIM_ALC_OVERFLOW_CB_ID   Absolute line counter overflow callback ID
+  *           @arg @ref HAL_GFXTIM_RFC1_RELOAD_CB_ID    Relative frame counter 1 reload callback ID
+  *           @arg @ref HAL_GFXTIM_RFC2_RELOAD_CB_ID    Relative frame counter 2 reload callback ID
+  *           @arg @ref HAL_GFXTIM_TE_CB_ID             External tearing effect callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT1_CB_ID         Event events 1 callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT2_CB_ID         Event events 2 callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT3_CB_ID         Event events 3 callback ID
+  *           @arg @ref HAL_GFXTIM_EVENT4_CB_ID         Event events 4 callback ID
+  *           @arg @ref HAL_GFXTIM_WDG_ALARM_CB_ID      Watchdog alarm callback ID
+  *           @arg @ref HAL_GFXTIM_WDG_PREALARM_CB_ID   Watchdog pre alarm callback ID
+  *           @arg @ref HAL_GFXTIM_ERROR_CB_ID          error callback ID
+  *           @arg @ref HAL_GFXTIM_MSP_INIT_CB_ID       MSP initialization user callback ID
+  *           @arg @ref HAL_GFXTIM_MSP_DEINIT_CB_ID     MSP de-initialization user callback ID
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_UnRegisterCallback(GFXTIM_HandleTypeDef *hgfxtim,
+                                                HAL_GFXTIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_GFXTIM_AFC_COMPARE1_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback = HAL_GFXTIM_AbsoluteTimer_AFCC1Callback;
+          break;
+        case HAL_GFXTIM_AFC_OVERFLOW_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback = HAL_GFXTIM_AbsoluteTimer_AFCOFCallback;
+          break;
+        case HAL_GFXTIM_ALC_COMPARE1_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback = HAL_GFXTIM_AbsoluteTimer_ALCC1Callback;
+          break;
+        case HAL_GFXTIM_ALC_COMPARE2_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback = HAL_GFXTIM_AbsoluteTimer_ALCC2Callback;
+          break;
+        case HAL_GFXTIM_ALC_OVERFLOW_CB_ID :
+          hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback = HAL_GFXTIM_AbsoluteTimer_ALCOFCallback;
+          break;
+        case HAL_GFXTIM_RFC1_RELOAD_CB_ID :
+          hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback = HAL_GFXTIM_RelativeTimer_RFC1RCallback;
+          break;
+        case HAL_GFXTIM_RFC2_RELOAD_CB_ID :
+          hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback = HAL_GFXTIM_RelativeTimer_RFC2RCallback;
+          break;
+        case HAL_GFXTIM_TE_CB_ID :
+          hgfxtim->HAL_GFXTIM_TECallback = HAL_GFXTIM_TECallback;
+          break;
+        case HAL_GFXTIM_EVENT1_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback = HAL_GFXTIM_EventGenerator_EV1Callback;
+          break;
+        case HAL_GFXTIM_EVENT2_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback = HAL_GFXTIM_EventGenerator_EV2Callback;
+          break;
+        case HAL_GFXTIM_EVENT3_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback = HAL_GFXTIM_EventGenerator_EV3Callback;
+          break;
+        case HAL_GFXTIM_EVENT4_CB_ID :
+          hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback = HAL_GFXTIM_EventGenerator_EV4Callback;
+          break;
+        case HAL_GFXTIM_WDG_ALARM_CB_ID :
+          hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback = HAL_GFXTIM_WatchdogTimer_AlarmCallback;
+          break;
+        case HAL_GFXTIM_WDG_PREALARM_CB_ID :
+          hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback = HAL_GFXTIM_WatchdogTimer_PreAlarmCallback;
+          break;
+        case HAL_GFXTIM_ERROR_CB_ID :
+          hgfxtim->ErrorCallback = HAL_GFXTIM_ErrorCallback;
+          break;
+        case HAL_GFXTIM_MSP_INIT_CB_ID :
+          hgfxtim->MspInitCallback = HAL_GFXTIM_MspInit;
+          break;
+        case HAL_GFXTIM_MSP_DEINIT_CB_ID :
+          hgfxtim->MspDeInitCallback = HAL_GFXTIM_MspDeInit;
+          break;
+        default :
+          /* Update error code and status */
+          hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else if (hgfxtim->State == HAL_GFXTIM_STATE_RESET)
+    {
+      switch (CallbackID)
+      {
+        case HAL_GFXTIM_MSP_INIT_CB_ID :
+          hgfxtim->MspInitCallback = HAL_GFXTIM_MspInit;
+          break;
+        case HAL_GFXTIM_MSP_DEINIT_CB_ID :
+          hgfxtim->MspDeInitCallback = HAL_GFXTIM_MspDeInit;
+          break;
+        default :
+          /* Update error code and status */
+          hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* Update error code and status */
+      hgfxtim->ErrorCode |= GFXTIM_ERROR_INVALID_CALLBACK;
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+#endif /* #if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1) */
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Exported_Functions_Group2  Clock Generator functions
+  * @brief    Clock Generator functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Clock Generator functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Configure the clock generator.
+      (+) Force reload of FCC and LCC.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function configures the clock generator.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  pClockGeneratorConfig Clock Generator configuration parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                   const GFXTIM_ClockGeneratorConfigTypeDef *pClockGeneratorConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hgfxtim == NULL) || (pClockGeneratorConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_LCC_HW_RELOAD_SRC(pClockGeneratorConfig->LCCHwReloadSrc));
+    assert_param(IS_GFXTIM_LCC_RELOAD_VALUE(pClockGeneratorConfig->LCCReloadValue));
+    assert_param(IS_GFXTIM_LCC_CLK_SRC(pClockGeneratorConfig->LCCClockSrc));
+    assert_param(IS_GFXTIM_LINE_CLK_SRC(pClockGeneratorConfig->LineClockSrc));
+    assert_param(IS_GFXTIM_FCC_HW_RELOAD_SRC(pClockGeneratorConfig->FCCHwReloadSrc));
+    assert_param(IS_GFXTIM_FCC_RELOAD_VALUE(pClockGeneratorConfig->FCCReloadValue));
+    assert_param(IS_GFXTIM_FCC_CLK_SRC(pClockGeneratorConfig->FCCClockSrc));
+    assert_param(IS_GFXTIM_FRAME_CLK_SRC(pClockGeneratorConfig->FrameClockSrc));
+    assert_param(IS_GFXTIM_LINE_CLK_CALIB(pClockGeneratorConfig->LineClockCalib));
+    assert_param(IS_GFXTIM_FRAME_CLK_CALIB(pClockGeneratorConfig->FrameClockCalib));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Disable FCC and LCC */
+      CLEAR_BIT(hgfxtim->Instance->CGCR,
+                GFXTIM_CGCR_LCCCS | GFXTIM_CGCR_FCCCS);
+
+      /* Set Line Clock Counter (LCC) reload value (22 bits) */
+      MODIFY_REG(hgfxtim->Instance->LCCRR, GFXTIM_LCCRR_RELOAD,
+                 (pClockGeneratorConfig->LCCReloadValue << GFXTIM_LCCRR_RELOAD_Pos));
+
+      /* Set Frame Clock Counter (FCC) reload value (12 bits) */
+      MODIFY_REG(hgfxtim->Instance->FCCRR, GFXTIM_FCCRR_RELOAD,
+                 (pClockGeneratorConfig->FCCReloadValue << GFXTIM_FCCRR_RELOAD_Pos));
+
+      /* Set line and frame config */
+      MODIFY_REG(hgfxtim->Instance->CGCR,
+                 GFXTIM_CGCR_LCCHRS | GFXTIM_CGCR_LCCCS | GFXTIM_CGCR_LCS |
+                 GFXTIM_CGCR_FCCHRS | GFXTIM_CGCR_FCCCS | GFXTIM_CGCR_FCS,
+                 pClockGeneratorConfig->LCCHwReloadSrc | pClockGeneratorConfig->LCCClockSrc |
+                 pClockGeneratorConfig->LineClockSrc | pClockGeneratorConfig->FCCHwReloadSrc |
+                 pClockGeneratorConfig->FCCClockSrc | pClockGeneratorConfig->FrameClockSrc);
+
+      /* Set debug output config for Line and frame clocks */
+      MODIFY_REG(hgfxtim->Instance->CR,
+                 GFXTIM_CR_LCCOE | GFXTIM_CR_FCCOE,
+                 pClockGeneratorConfig->LineClockCalib | pClockGeneratorConfig->FrameClockCalib);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function force clock generator counter(s) reload
+  * @param  hgfxtim GFXTIM handle.
+  * @param  ClockGeneratorCounter Clock Generator counter
+  *          This parameter can be a value of @ref GFXTIM_ClockGeneratorCounter.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_ClockGenerator_Reload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t ClockGeneratorCounter)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_CLOCK_GENERATOR_COUNTER(ClockGeneratorCounter));
+
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      SET_BIT(hgfxtim->Instance->CGCR, ClockGeneratorCounter);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  GFXTIM Tearing effect callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_TECallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_TECallback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Exported_Functions_Group3 Absolute Timer functions
+  * @brief    Absolute Timer functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Absolute Timers functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Configure the absolute timer.
+      (+) Start the absolute timer.
+      (+) Stop the absolute timer.
+      (+) Reset the absolute timer counters.
+      (+) Get the absolute time value.
+      (+) Set the absolute frame compare value.
+      (+) Set the absolute line compare value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function configures an absolute Timer.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  pAbsoluteTimerConfig pointer to a GFXTIM_AbsoluteTimerConfigTypeDef structure that
+  *         contains absoluite timer comparators and counters values.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                  const GFXTIM_AbsoluteTimerConfigTypeDef *pAbsoluteTimerConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hgfxtim == NULL) || (pAbsoluteTimerConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_ABSOLUTE_FRAME_VALUE(pAbsoluteTimerConfig->FrameCompare1Value));
+    assert_param(IS_GFXTIM_ABSOLUTE_FRAME_VALUE(pAbsoluteTimerConfig->FrameCounterValue));
+    assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->FrameOverflowInterrupt));
+    assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->FrameCompare1Interrupt));
+    assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(pAbsoluteTimerConfig->LineCompare1Value));
+    assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(pAbsoluteTimerConfig->LineCompare2Value));
+    assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(pAbsoluteTimerConfig->LineCounterValue));
+    assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->LineOverflowInterrupt));
+    assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->LineCompare1Interrupt));
+    assert_param(IS_GFXTIM_INTERRUPT(pAbsoluteTimerConfig->LineCompare2Interrupt));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+
+      /* Set AFC compare 1 value */
+      MODIFY_REG(hgfxtim->Instance->AFCC1R, GFXTIM_AFCC1R_FRAME,
+                 (pAbsoluteTimerConfig->FrameCompare1Value << GFXTIM_AFCC1R_FRAME_Pos));
+
+      /* Set AFC counter value */
+      MODIFY_REG(hgfxtim->Instance->AFCR, GFXTIM_AFCR_FRAME,
+                 (pAbsoluteTimerConfig->FrameCounterValue << GFXTIM_AFCR_FRAME_Pos));
+
+      /* Set ALC compare 1 value */
+      MODIFY_REG(hgfxtim->Instance->ALCC1R, GFXTIM_ALCC1R_LINE,
+                 (pAbsoluteTimerConfig->LineCompare1Value << GFXTIM_ALCC1R_LINE_Pos));
+
+      /* Set ALC compare 2 value */
+      MODIFY_REG(hgfxtim->Instance->ALCC2R, GFXTIM_ALCC2R_LINE,
+                 (pAbsoluteTimerConfig->LineCompare2Value << GFXTIM_ALCC2R_LINE_Pos));
+
+      /* Set ALC counter value */
+      MODIFY_REG(hgfxtim->Instance->ALCR, GFXTIM_ALCR_LINE,
+                 (pAbsoluteTimerConfig->LineCounterValue << GFXTIM_ALCR_LINE_Pos));
+
+      /* Set ALC compare 1, compare 2, overflow interrupts, AFC compare 1 and overflow interrupts */
+      MODIFY_REG(hgfxtim->Instance->IER,
+                 GFXTIM_IER_ALCC1IE | GFXTIM_IER_ALCC2IE | GFXTIM_IER_ALCOIE | GFXTIM_IER_AFCC1IE | GFXTIM_IER_AFCOIE,
+                 (pAbsoluteTimerConfig->FrameOverflowInterrupt << GFXTIM_IER_AFCOIE_Pos) |
+                 (pAbsoluteTimerConfig->FrameCompare1Interrupt << GFXTIM_IER_AFCC1IE_Pos) |
+                 (pAbsoluteTimerConfig->LineOverflowInterrupt << GFXTIM_IER_ALCOIE_Pos) |
+                 (pAbsoluteTimerConfig->LineCompare1Interrupt << GFXTIM_IER_ALCC1IE_Pos) |
+                 (pAbsoluteTimerConfig->LineCompare2Interrupt << GFXTIM_IER_ALCC2IE_Pos));
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function starts absolute timer.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Start(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Enable absolute Timer */
+      SET_BIT(hgfxtim->Instance->TCR, (GFXTIM_TCR_AFCEN | GFXTIM_TCR_ALCEN));
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function stops absolute timer counter(s).
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Disable absolute counter(s) */
+      SET_BIT(hgfxtim->Instance->TDR, (GFXTIM_TDR_ALCDIS | GFXTIM_TDR_AFCDIS));
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function resets absolute timer counters.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_Reset(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Disable absolute counter(s) */
+      SET_BIT(hgfxtim->Instance->TCR, (GFXTIM_TCR_FAFCR | GFXTIM_TCR_FALCR));
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function gets absolute timer value.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  AbsoluteTime absolute time
+  *         This parameter can be a value of @ref GFXTIM_AbsoluteTime.
+  * @param  pValue Absolute time value
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t AbsoluteTime,
+                                                      uint32_t *pValue)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hgfxtim == NULL) || (pValue == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_ABSOLUTE_TIME(AbsoluteTime));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      switch (AbsoluteTime)
+      {
+        case GFXTIM_ABSOLUTE_GLOBAL_TIME:
+          *pValue = READ_REG(hgfxtim->Instance->ATR);
+          break;
+        case GFXTIM_ABSOLUTE_FRAME_TIME:
+          *pValue = READ_REG(hgfxtim->Instance->AFCR);
+          break;
+        default:
+          /* GFXTIM_ABSOLUTE_LINE_TIME */
+          *pValue = READ_REG(hgfxtim->Instance->ALCR);
+          break;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  This function sets absolute frame compare value.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  Value Absolute frame compare 1 value
+  *         This parameter can be a number between Min_Data = 0x00000 and Max_Data = 0xFFFFF
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetFrameCompare(GFXTIM_HandleTypeDef *hgfxtim, uint32_t Value)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Set absolute frame counter compare 1 register value */
+      MODIFY_REG(hgfxtim->Instance->AFCC1R, GFXTIM_AFCC1R_FRAME,
+                 (Value << GFXTIM_AFCC1R_FRAME_Pos));
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function sets line compare value.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  AbsoluteLineComparator Absolute line compare value
+  *         This parameter can be a value of @ref GFXTIM_AbsoluteLineComparator.
+  * @param  Value Absolute line compare value
+  *         This parameter can be a number between Min_Data = 0x000 and Max_Data = 0xFFF
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_AbsoluteTimer_SetLineCompare(GFXTIM_HandleTypeDef *hgfxtim,
+                                                          uint32_t AbsoluteLineComparator, uint32_t Value)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_ABSOLUTE_LINE_COMPARATOR(AbsoluteLineComparator));
+    assert_param(IS_GFXTIM_ABSOLUTE_LINE_VALUE(Value));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      switch (AbsoluteLineComparator)
+      {
+        case GFXTIM_ABSOLUTE_LINE_COMPARE1:
+          WRITE_REG(hgfxtim->Instance->ALCC1R, Value);
+          break;
+        default:
+          /* GFXTIM_ABSOLUTE_LINE_COMPARE2 */
+          WRITE_REG(hgfxtim->Instance->ALCC2R, Value);
+          break;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  GFXTIM Absolute frame counter overflow callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_AbsoluteTimer_AFCOFCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Absolute frame counter compare 1 callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_AbsoluteTimer_AFCC1Callback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Absolute line counter compare 1 callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_AbsoluteTimer_ALCC1Callback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Absolute line counter compare 2 callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_AbsoluteTimer_ALCC2Callback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Absolute line counter overflow callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_AbsoluteTimer_ALCOFCallback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Exported_Functions_Group4 Relative Timer functions
+  * @brief    Clock Generator functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Relative Timer functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Configure a relative timer.
+      (+) Start a relative timer counter.
+      (+) Stop a relative timer counter.
+      (+) Force a relative timer counter reload.
+      (+) Set a relative timer reload value.
+      (+) Get a relative timer counter value.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function configures a Relative Timer.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  pRelativeTimerConfig pointer to a GFXTIM_RelativeTimerConfigTypeDef structure that
+  *         contains relative timer comparators and counters values.
+  * @param  RelativeTimer Relative Timer identifier
+  *         This parameter can be a value of @ref GFXTIM_RelativeTimer.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                  const GFXTIM_RelativeTimerConfigTypeDef *pRelativeTimerConfig,
+                                                  uint32_t RelativeTimer)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hgfxtim == NULL) || (pRelativeTimerConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_RELATIVE_FRAME_VALUE(pRelativeTimerConfig->AutoReloadValue));
+    assert_param(IS_GFXTIM_RELATIVE_FRAME_VALUE(pRelativeTimerConfig->CounterMode));
+    assert_param(IS_GFXTIM_INTERRUPT(pRelativeTimerConfig->ReloadInterrupt));
+    assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      if (RelativeTimer == GFXTIM_RELATIVE_TIMER1)
+      {
+        /* Set RFC1 auto reload */
+        MODIFY_REG(hgfxtim->Instance->RFC1RR, GFXTIM_RFC1RR_FRAME,
+                   pRelativeTimerConfig->AutoReloadValue << GFXTIM_RFC1RR_FRAME_Pos);
+
+        /* Set relative timer mode */
+        MODIFY_REG(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC1CM,
+                   (pRelativeTimerConfig->CounterMode << GFXTIM_TCR_RFC1CM_Pos));
+
+        /* Set relative timer 1 interrupt */
+        MODIFY_REG(hgfxtim->Instance->IER, GFXTIM_IER_RFC1RIE_Msk,
+                   (pRelativeTimerConfig->ReloadInterrupt << GFXTIM_IER_RFC1RIE_Pos));
+      }
+      else
+      {
+        /* Set RFC2 auto reload */
+        MODIFY_REG(hgfxtim->Instance->RFC2RR, GFXTIM_RFC2RR_FRAME,
+                   pRelativeTimerConfig->AutoReloadValue << GFXTIM_RFC2RR_FRAME_Pos);
+
+        /* Set relative timer mode */
+        MODIFY_REG(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC2CM,
+                   (pRelativeTimerConfig->CounterMode << GFXTIM_TCR_RFC2CM_Pos));
+
+        /* Set relative timer 2 interrupt */
+        MODIFY_REG(hgfxtim->Instance->IER, GFXTIM_IER_RFC2RIE_Msk,
+                   (pRelativeTimerConfig->ReloadInterrupt << GFXTIM_IER_RFC2RIE_Pos));
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function starts a relative Timer.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  RelativeTimer Relative timer counter to Enable
+  *         This parameter can be a value of @ref GFXTIM_RelativeTimer.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Start(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      if (RelativeTimer == GFXTIM_RELATIVE_TIMER1)
+      {
+        /* Enable relative timer 1 */
+        SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC1EN);
+      }
+      else
+      {
+        /* Enable relative timer 2 */
+        SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_RFC2EN);
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function stops a relative Timer counter.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  RelativeTimer Relative timer counter to Disable
+  *         This parameter can be a value of @ref GFXTIM_RelativeTimer.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_Stop(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      if (RelativeTimer == GFXTIM_RELATIVE_TIMER1)
+      {
+        /* Disable relative timer 1 */
+        SET_BIT(hgfxtim->Instance->TDR, GFXTIM_TDR_RFC1DIS);
+      }
+      else
+      {
+        /* Disable relative timer 2 */
+        SET_BIT(hgfxtim->Instance->TDR, GFXTIM_TDR_RFC2DIS);
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  This function force a relative Timer reload.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  RelativeTimer Relative timer to Foce Reload
+  *           This parameter can be a value of @ref GFXTIM_RelativeTimer.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_ForceReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      if (RelativeTimer == GFXTIM_RELATIVE_TIMER1)
+      {
+        /* Force relative timer 1 reload */
+        SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_FRFC1R);
+      }
+      else
+      {
+        /* Force relative timer 2 reload*/
+        SET_BIT(hgfxtim->Instance->TCR, GFXTIM_TCR_FRFC2R);
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  This function sets Relative frame timer reload value.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  RelativeTimer specifies the Auto-reload register to be modified.
+  *         This parameter can be a value of @ref GFXTIM_RelativeTimer.
+  * @param  Value Reload value
+  *         This parameter can be a number between Min_Data = 0x000 and Max_Data = 0xFFF
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_SetReload(GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer,
+                                                     uint32_t Value)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_RELATIVE_FRAME_VALUE(Value));
+    assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      if (RelativeTimer == GFXTIM_RELATIVE_TIMER1)
+      {
+        /* Set RFC1 auto reload */
+        WRITE_REG(hgfxtim->Instance->RFC1RR, Value);
+      }
+      else
+      {
+        /* Set RFC2 auto reload */
+        WRITE_REG(hgfxtim->Instance->RFC2RR, Value);
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function sets Relative frame timer compare value.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  RelativeTimer Relative frame counter reload
+  *         This parameter can be a value of @ref GFXTIM_RelativeTimer.
+  * @param  pValue pointer to a relative frame counter value
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_RelativeTimer_GetCounter(const GFXTIM_HandleTypeDef *hgfxtim, uint32_t RelativeTimer,
+                                                      uint32_t *pValue)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hgfxtim == NULL) || (pValue == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_RELATIVE_TIMER(RelativeTimer));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      if (RelativeTimer == GFXTIM_RELATIVE_TIMER1)
+      {
+        /* Set RFC1 auto reload */
+        *pValue = READ_REG(hgfxtim->Instance->RFC1R);
+      }
+      else
+      {
+        /* Set RFC2 auto reload */
+        *pValue = READ_REG(hgfxtim->Instance->RFC2R);
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+
+
+
+/**
+  * @brief  GFXTIM Relative frame counter 1 reload callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_RelativeTimer_RFC1RCallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_RelativeTimer_RFC1RCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Relative frame counter 2 reload callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_RelativeTimer_RFC2RCallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_RelativeTimer_RFC2RCallback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Exported_Functions_Group5 Event Generator functions
+  * @brief    Event Generator functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Event Generator functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Configure an Event Generator.
+      (+) Enable an Event Generator.
+      (+) Disable an Event Generator.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function configures an Event Generator.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  EventGenerator Event Generator
+  *           This parameter can be a value of @ref GFXTIM_EventGenerator.
+  * @param  pEventGeneratorConfig pointer to a GFXTIM_EventGeneratorConfigTypeDef structure that
+  *         contains Event Generator configuration parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Config(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator,
+                                                   const GFXTIM_EventGeneratorConfigTypeDef *pEventGeneratorConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t shift;
+
+  if ((hgfxtim == NULL) || (pEventGeneratorConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_EVENT_GENERATOR(EventGenerator));
+    assert_param(IS_GFXTIM_EVENT_LINE(pEventGeneratorConfig->LineEvent));
+    assert_param(IS_GFXTIM_EVENT_FRAME(pEventGeneratorConfig->FrameEvent));
+    assert_param(IS_GFXTIM_INTERRUPT(pEventGeneratorConfig->EventInterrupt));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Select frame and line events */
+      shift = (EventGenerator) * 8U;
+      MODIFY_REG(hgfxtim->Instance->EVSR, \
+                 ((GFXTIM_EVSR_LES1 | GFXTIM_EVSR_FES1) << shift),
+                 ((pEventGeneratorConfig->LineEvent | pEventGeneratorConfig->FrameEvent) << shift));
+
+      /* Event interrupt */
+      MODIFY_REG(hgfxtim->Instance->IER, \
+                 (GFXTIM_IER_EV1IE << (EventGenerator)), \
+                 (pEventGeneratorConfig->EventInterrupt << (EventGenerator + GFXTIM_IER_EV1IE_Pos)));
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function enables an Event Generator.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  EventGenerator Event Generator
+  *           This parameter can be a value of @ref GFXTIM_EventGenerator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Enable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_EVENT_GENERATOR(EventGenerator));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Enable event generator */
+      SET_BIT(hgfxtim->Instance->EVCR, GFXTIM_EVCR_EV1EN << EventGenerator);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function disables an Event Generator.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  EventGenerator Event Generator
+  *           This parameter can be a value of @ref GFXTIM_EventGenerator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_EventGenerator_Disable(GFXTIM_HandleTypeDef *hgfxtim, uint32_t EventGenerator)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_EVENT_GENERATOR(EventGenerator));
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Disable event generator */
+      CLEAR_BIT(hgfxtim->Instance->EVCR, GFXTIM_EVCR_EV1EN << EventGenerator);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+
+
+/**
+  * @brief  GFXTIM Combined events 1 callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_EventGenerator_EV1Callback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_EventGenerator_EV1Callback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Combined events 2 callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_EventGenerator_EV2Callback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_EventGenerator_EV2Callback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Combined events 3 callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_EventGenerator_EV3Callback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_EventGenerator_EV3Callback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Combined events 4 callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_EventGenerator_EV4Callback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_EventGenerator_EV4Callback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Exported_Functions_Group6 Watchdog functions
+  * @brief    Event Generator functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Watchdog functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Configure the Watchdog.
+      (+) Enable the Watchdog
+      (+) Disable the Watchdog.
+      (+) Refresh the Watchdog.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Watchdog.
+  * @param  hgfxtim GFXTIM handle.
+  * @param  pWatchdogConfig Watchdog configuration parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Config(GFXTIM_HandleTypeDef *hgfxtim,
+                                                  const GFXTIM_WatchdogConfigTypeDef *pWatchdogConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hgfxtim == NULL) || (pWatchdogConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+    assert_param(IS_GFXTIM_WATCHDOG_CLOCK_SRC(pWatchdogConfig->ClockSrc));
+    assert_param(IS_GFXTIM_WATCHDOG_HW_RELOAD_CONFIG(pWatchdogConfig->HwReloadConfig));
+
+    assert_param(IS_GFXTIM_WATCHDOG_VALUE(pWatchdogConfig->AutoReloadValue));
+    assert_param(IS_GFXTIM_WATCHDOG_VALUE(pWatchdogConfig->PreAlarmValue));
+
+    assert_param(IS_GFXTIM_INTERRUPT(pWatchdogConfig->AlarmInterrupt));
+    assert_param(IS_GFXTIM_INTERRUPT(pWatchdogConfig->PreAlarmInterrupt));
+
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Set watchdog auto reload value */
+      MODIFY_REG(hgfxtim->Instance->WDGRR, GFXTIM_WDGRR_RELOAD,
+                 (pWatchdogConfig->AutoReloadValue << GFXTIM_WDGRR_RELOAD_Pos));
+
+      /* Set watchdog pre alarm value */
+      MODIFY_REG(hgfxtim->Instance->WDGPAR, GFXTIM_WDGPAR_PREALARM,
+                 pWatchdogConfig->PreAlarmValue << GFXTIM_WDGPAR_PREALARM_Pos);
+
+      /* Set watchdog clock source and hardware reload */
+      MODIFY_REG(hgfxtim->Instance->WDGTCR, (GFXTIM_WDGTCR_WDGCS | GFXTIM_WDGTCR_WDGHRC),
+                 (pWatchdogConfig->ClockSrc | pWatchdogConfig->HwReloadConfig));
+
+      /* Set watchdog interrupts */
+      MODIFY_REG(hgfxtim->Instance->IER, \
+                 (GFXTIM_IER_WDGAIE | GFXTIM_IER_WDGPIE), \
+                 ((pWatchdogConfig->AlarmInterrupt << GFXTIM_IER_WDGAIE_Pos) | \
+                  (pWatchdogConfig->PreAlarmInterrupt << GFXTIM_IER_WDGPIE_Pos)));
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function Enable the Watchdog Counter.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Enable(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Set watchdog enable bit */
+      SET_BIT(hgfxtim->Instance->WDGTCR, GFXTIM_WDGTCR_WDGEN);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function Disable the Watchdog Counter.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Disable(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Set watchdog disable bit */
+      SET_BIT(hgfxtim->Instance->WDGTCR, GFXTIM_WDGTCR_WDGDIS);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function refresh the Watchdog counter.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_GFXTIM_WatchdogTimer_Refresh(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hgfxtim == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_GFXTIM_ALL_INSTANCE(hgfxtim->Instance));
+
+
+    if (hgfxtim->State == HAL_GFXTIM_STATE_READY)
+    {
+      /* Set watchdog SW relaod */
+      SET_BIT(hgfxtim->Instance->WDGTCR, GFXTIM_WDGTCR_FWDGR);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  GFXTIM Watchdog alarm callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_WatchdogTimer_AlarmCallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_WatchdogTimer_AlarmCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  GFXTIM Watchdog pre alarm callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_WatchdogTimer_PreAlarmCallback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GFXTIM_Exported_Functions_Group7  Generic functions
+  * @brief    Generic functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### Generic functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Handle GFXTIM interrupt.
+      (+) Inform user that error occurs.
+      (+) Get the current GFXTIM instance state
+      (+) Get the current GFXTIM instance error code.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles the GFXTIM interrupts.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+void HAL_GFXTIM_IRQHandler(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  uint32_t tmp_reg1;
+  uint32_t tmp_reg2;
+  uint32_t interrupts;
+
+  /* Read all pending interrupts */
+  tmp_reg1 = READ_REG(hgfxtim->Instance->ISR);
+  tmp_reg2 = READ_REG(hgfxtim->Instance->IER);
+  interrupts = tmp_reg1 & tmp_reg2;
+
+  if ((interrupts & GFXTIM_ISR_AFCC1F) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(hgfxtim);
+#else
+    HAL_GFXTIM_AbsoluteTimer_AFCC1Callback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_AFCOF) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(hgfxtim);
+#else
+    HAL_GFXTIM_AbsoluteTimer_AFCOFCallback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_ALCC1F) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(hgfxtim);
+#else
+    HAL_GFXTIM_AbsoluteTimer_ALCC1Callback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_ALCC2F) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(hgfxtim);
+#else
+    HAL_GFXTIM_AbsoluteTimer_ALCC2Callback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_ALCOF) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(hgfxtim);
+#else
+    HAL_GFXTIM_AbsoluteTimer_ALCOFCallback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_TEF) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_TECallback(hgfxtim);
+#else
+    HAL_GFXTIM_TECallback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_RFC1RF) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_RelativeTimer_RFC1RCallback(hgfxtim);
+#else
+    HAL_GFXTIM_RelativeTimer_RFC1RCallback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_RFC2RF) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_RelativeTimer_RFC2RCallback(hgfxtim);
+#else
+    HAL_GFXTIM_RelativeTimer_RFC2RCallback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_EV1F) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_EventGenerator_EV1Callback(hgfxtim);
+#else
+    HAL_GFXTIM_EventGenerator_EV1Callback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_EV2F) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_EventGenerator_EV2Callback(hgfxtim);
+#else
+    HAL_GFXTIM_EventGenerator_EV2Callback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_EV3F) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_EventGenerator_EV3Callback(hgfxtim);
+#else
+    HAL_GFXTIM_EventGenerator_EV3Callback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_EV4F) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_EventGenerator_EV4Callback(hgfxtim);
+#else
+    HAL_GFXTIM_EventGenerator_EV4Callback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_WDGAF) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_WatchdogTimer_AlarmCallback(hgfxtim);
+#else
+    HAL_GFXTIM_WatchdogTimer_AlarmCallback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+
+  if ((interrupts & GFXTIM_ISR_WDGPF) != 0U)
+  {
+#if (USE_HAL_GFXTIM_REGISTER_CALLBACKS == 1U)
+    hgfxtim->HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(hgfxtim);
+#else
+    HAL_GFXTIM_WatchdogTimer_PreAlarmCallback(hgfxtim);
+#endif /* USE_HAL_GFXTIM_REGISTER_CALLBACKS */
+  }
+  /* Clear all pending interrupts */
+  WRITE_REG(hgfxtim->Instance->ICR, interrupts);
+}
+
+/**
+  * @brief  GFXTIM error callback.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval None.
+  */
+__weak void HAL_GFXTIM_ErrorCallback(GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgfxtim);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_GFXTIM_ErrorCallback could be implemented in the user file. */
+}
+
+/**
+  * @brief  This function get the current GFXTIM state.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval GFXTIM state.
+  */
+HAL_GFXTIM_StateTypeDef HAL_GFXTIM_GetState(const GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Return GFXTIM state */
+  return hgfxtim->State;
+}
+
+/**
+  * @brief  This function get the current GFXTIM error.
+  * @param  hgfxtim GFXTIM handle.
+  * @retval GFXTIM error code.
+  */
+uint32_t HAL_GFXTIM_GetError(const GFXTIM_HandleTypeDef *hgfxtim)
+{
+  /* Return GFXTIM error code */
+  return hgfxtim->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* GFXTIM */
+#endif /* HAL_GFXTIM_MODULE_ENABLED */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gpio.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gpio.c
new file mode 100644
index 000000000..2e002bbc0
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gpio.c
@@ -0,0 +1,897 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gpio.c
+  * @author  GPM Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in analog mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+        to an IO pin at a time. In this way, there can be no conflict between peripherals
+        sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+    (+) The external interrupt/event controller consists of up to 73 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+    (#) To set the level of several pins and reset level of several other pins in
+        same cycle, use HAL_GPIO_WriteMultipleStatePin().
+
+    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in analog mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+  * range of the shift operator in following API :
+  * HAL_GPIO_Init
+  * HAL_GPIO_DeInit
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants
+  * @{
+  */
+#define GPIO_NUMBER           (16u)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @note   If GPIOx peripheral pin is used in EXTI_MODE and the pin is secure/privilege, it is up
+  *         to the application to insure that the corresponding EXTI line is set secure/privilege.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, const GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t temp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1uL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
+        temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
+          (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
+      {
+        /* Check the Pull parameter */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+        temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
+        temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
+        GPIOx->PUPDR = temp;
+      }
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3u];
+        temp &= ~(0xFu << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos));
+        GPIOx->AFR[position >> 3u] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
+      {
+        temp = EXTI->EXTICR[position >> 2u];
+        temp &= ~(0x0FuL << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos));
+        temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos));
+        EXTI->EXTICR[position >> 2u] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR1 = temp;
+
+        temp = EXTI->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00u)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1uL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+
+      tmp = EXTI->EXTICR[position >> 2u];
+      tmp &= (0x0FuL << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos)))
+      {
+        /* Clear EXTI line configuration */
+        EXTI->IMR1 &= ~(iocurrent);
+        EXTI->EMR1 &= ~(iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~(iocurrent);
+        EXTI->FTSR1 &= ~(iocurrent);
+
+        tmp = 0x0FuL << ((position & 0x03u) * EXTI_EXTICR1_EXTI1_Pos);
+        EXTI->EXTICR[position >> 2u] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * GPIO_AFRL_AFSEL1_Pos)) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
+
+      /* Reset delay settings for the current IO */
+      GPIOx->DELAYR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * GPIO_DELAYRL_DLY1_Pos)) ;
+
+      /* Reset control settings for the current IO */
+      GPIOx->ADVCFGR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos)) ;
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the specified input port pin.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Set or clear the selected data port bit.
+  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @param  PinState specifies the value to be written to the selected bit.
+  *         This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Toggle the specified GPIO pin.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Pin specifies the pin to be toggled.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t odr;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* get current Output Data Register value */
+  odr = GPIOx->ODR;
+
+  /* Set selected pins that were at low level, and reset ones that were high */
+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+  * @brief  Set and clear several pins of a dedicated port in same cycle.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  PinReset specifies the port bits to be reset
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
+  * @param  PinSet specifies the port bits to be set
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
+  * @note   Both PinReset and PinSet combinations shall not get any common bit, else
+  *         assert would be triggered.
+  * @note   At least one of the two parameters used to set or reset shall be different from zero.
+  * @retval None
+  */
+void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  /* Make sure at least one parameter is different from zero and that there is no common pin */
+  assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet));
+  assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet));
+
+  tmp = (((uint32_t)PinReset << 16) | PinSet);
+  GPIOx->BSRR = tmp;
+}
+
+/**
+  * @brief  Lock GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL, GPIOx_AFRH, GPIOx_DELAYRL, GPIOx_DELAYRH, GPIOx_ADVCFGRL, GPIOx_ADVCFGRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified until the next reset.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Pin specifies the port bits to be locked.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval HAL_OK if success, HAL_ERROR otherwise
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure GPIO retime on specified GPIO pin.
+  * @param  GPIOx where x can be (A..H and N..Q)
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @param  pRet_Init pointer to a GPIO_RetimeTypeDef structure that contains
+  *         the retime configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_SetRetime(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_RetimeTypeDef *pRet_Init)
+{
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t temp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_RETIME(pRet_Init->Retime));
+  assert_param(IS_GPIO_CLOCK(pRet_Init->Edge));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00u)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1uL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /* Configure the IO Retime */
+      temp = GPIOx->ADVCFGR[position >> 3u];
+      temp &= ~((GPIO_ADVCFGRL_RET0 | GPIO_ADVCFGRL_INVCLK0 | GPIO_ADVCFGRL_DE0)
+                << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos));
+      temp |= (pRet_Init->Retime << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos));
+      temp |= (pRet_Init->Edge << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos));
+      GPIOx->ADVCFGR[position >> 3u] = temp;
+    }
+    position++;
+  }
+}
+
+/**
+  * @brief  Get GPIO retime configuration on specified GPIO pin.
+  * @param  GPIOx where x can be (A..H and N..Q)
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @param  pRet_Init pointer to the return GPIO_RetimeTypeDef structure that contains the retime information
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_GPIO_GetRetime(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_RetimeTypeDef *pRet_Init)
+{
+  uint32_t position;
+  uint32_t index;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin));
+
+  /* Check null pointer */
+  if (pRet_Init == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* get IO position */
+  position = POSITION_VAL(GPIO_Pin);
+
+  /* Get the IO advanced configuration */
+  index = (position & 0x07u) * GPIO_ADVCFGRL_1_Pos;
+  pRet_Init->Edge = ((GPIOx->ADVCFGR[position >> 3u]
+                      & ((GPIO_ADVCFGRL_DE0 << index) | (GPIO_ADVCFGRL_INVCLK0 << index))) >> index);
+  pRet_Init->Retime = ((GPIOx->ADVCFGR[position >> 3u] & (GPIO_ADVCFGRL_RET0 << index)) >> index);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Configure GPIO delay on specified GPIO pin.
+  * @param  GPIOx where x can be (A..H and N..Q)
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @param  pDly_Init pointer to a GPIO_DelayTypeDef structure that contains
+  *         the delay configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_SetDelay(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, const GPIO_DelayTypeDef *pDly_Init)
+{
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t temp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_DELAY(pDly_Init->Delay));
+  assert_param(IS_GPIO_PATH(pDly_Init->Path));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00u)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1uL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /* Configure the IO Delay path */
+      temp = GPIOx->ADVCFGR[position >> 3u];
+      temp &= ~(GPIO_ADVCFGRL_DLYPATH0 << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos));
+      temp |= (pDly_Init->Path << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos));
+      GPIOx->ADVCFGR[position >> 3u] = temp;
+
+      /* Configure the IO Delay */
+      temp = GPIOx->DELAYR[position >> 3u];
+      temp &= ~(GPIO_DELAYRL_DLY0_Msk << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos));
+      temp |= (pDly_Init->Delay << ((position & 0x07u) * GPIO_ADVCFGRL_1_Pos));
+      GPIOx->DELAYR[position >> 3u] = temp;
+    }
+    position++;
+  }
+}
+
+/**
+  * @brief  Get GPIO delay configuration on specified GPIO pin.
+  * @param  GPIOx where x can be (A..H and N..Q)
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @param  pDly_Init pointer to the return GPIO_DelayTypeDef structure that contains the delay information
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_GPIO_GetDelay(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_DelayTypeDef *pDly_Init)
+{
+  uint32_t position;
+  uint32_t index;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin));
+
+  /* Check null pointer */
+  if (pDly_Init == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* get IO position */
+  position = POSITION_VAL(GPIO_Pin);
+
+  /* Get the IO advanced configuration */
+  index = (position & 0x07u) * GPIO_ADVCFGRL_1_Pos;
+  pDly_Init->Delay = ((GPIOx->DELAYR[position >> 3u] & (GPIO_DELAYRL_DLY0_Msk << index)) >> index);
+  pDly_Init->Path = ((GPIOx->ADVCFGR[position >> 3u] & (GPIO_ADVCFGRL_DLYPATH0 << index)) >> index);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u)
+  {
+    __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
+  }
+
+  if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u)
+  {
+    __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line rising detection callback.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  EXTI line falling detection callback.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions
+  *  @brief GPIO attributes management functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO attributes functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+#if defined (CPU_IN_SECURE_STATE)
+
+/**
+  * @brief  Lock security and privilege configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the value of this port bit can no longer
+  *         be modified until the next reset. Set sequence only available in secure and privilege.
+  * @note   Each lock bit freezes a security configuration register (control and alternate function registers).
+  * @param  GPIOx GPIO Port
+  * @param  GPIO_Pin specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_LockPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Lock the pins */
+  GPIOx->RCFGLOCKR = (uint32_t)GPIO_Pin;
+}
+
+/**
+  * @brief  Get lock security and privilege configuration of several pins for a dedicated port.
+  * @param  GPIOx GPIO Port
+  * @retval Lock status for all pins. Bitx are set to 1 for pinx locked, otherwise 0.
+  */
+uint32_t HAL_GPIO_GetLockPinAttributes(const GPIO_TypeDef *GPIOx)
+{
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Lock the pins */
+  return (GPIOx->RCFGLOCKR);
+
+}
+
+#endif /* CPU_IN_SECURE_STATE */
+
+/**
+  * @brief  Configure the GPIO pins attributes.
+  * @note   Set a pin to secure is only available in secure and privilege
+  *         Set a pin to privilege is only available in privilege
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Pin : GPIO_Pin specifies the pin(s) to configure the secure/privilege attribute
+  * @param  PinAttributes: PinAttributes can be one or a combination of the following values :
+  *            @arg @ref GPIO_PIN_PRIV         Privileged-only access
+  *            @arg @ref GPIO_PIN_NPRIV        Privileged/Non-privileged access
+  *            @arg @ref GPIO_PIN_SEC          Secure-only access
+  *            @arg @ref GPIO_PIN_NSEC         Secure/Non-secure access
+  * @retval None.
+  */
+void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes)
+{
+#if defined CPU_IN_SECURE_STATE
+  uint32_t sec;
+#endif /* CPU_IN_SECURE_STATE */
+  uint32_t priv;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes));
+
+#if defined CPU_IN_SECURE_STATE
+  /* Configure the port pins */
+  sec = GPIOx->SECCFGR;
+  if ((PinAttributes & GPIO_PIN_SEC) == GPIO_PIN_SEC)
+  {
+    sec |= (uint32_t)GPIO_Pin;
+  }
+  else if ((PinAttributes & GPIO_PIN_NSEC) == GPIO_PIN_NSEC)
+  {
+    sec &= ~((uint32_t)GPIO_Pin);
+  }
+  else
+  {
+    /* do nothing */
+  }
+  GPIOx->SECCFGR = sec;
+#endif /* CPU_IN_SECURE_STATE */
+
+  priv = GPIOx->PRIVCFGR;
+  if ((PinAttributes & GPIO_PIN_PRIV) == GPIO_PIN_PRIV)
+  {
+    priv |= (uint32_t)GPIO_Pin;
+  }
+  else if ((PinAttributes & GPIO_PIN_NPRIV) == GPIO_PIN_NPRIV)
+  {
+    priv &= ~((uint32_t)GPIO_Pin);
+  }
+  else
+  {
+    /* do nothing */
+  }
+
+  GPIOx->PRIVCFGR = priv;
+}
+
+/**
+  * @brief  Get the GPIO pins attributes.
+  * @param  GPIOx where x can be (A..H and N..Q) to select the GPIO peripheral for STM32N6xx family
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @param  pPinAttributes: pPinAttributes pointer to return the pin attributes.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
+                                                  uint32_t *pPinAttributes)
+{
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin));
+
+  /* Check null pointer */
+  if (pPinAttributes == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((GPIOx->SECCFGR & GPIO_Pin) != 0x00U)
+  {
+    *pPinAttributes = GPIO_PIN_SEC;
+  }
+  else
+  {
+    *pPinAttributes = GPIO_PIN_NSEC;
+  }
+
+  if ((GPIOx->PRIVCFGR & GPIO_Pin) != 0x00U)
+  {
+    *pPinAttributes |= GPIO_PIN_PRIV;
+  }
+  else
+  {
+    *pPinAttributes |= GPIO_PIN_NPRIV;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gpu2d.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gpu2d.c
new file mode 100644
index 000000000..f90cfeeee
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_gpu2d.c
@@ -0,0 +1,752 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_gpu2d.c
+  * @author  MCD Application Team
+  * @brief   GPU2D HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the GPU2D peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Peripheral control is exclusively done by the accompanying middleware library.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (#) Configure the GPU2D hardware to perform graphics operation using the Third Party MW
+           Library APIs.
+       (#) Submit command List to the hardware.
+       (#) Wait indefinitely for the completion of submitted Command List by GPU2D hardware.
+       (#) Use HAL_GPU2D_IRQHandler() called under GPU2D_IRQHandler() interrupt subroutine.
+       (#) At the end of Command List execution HAL_GPU2D_IRQHandler() function is executed
+           and user can add his own function by customization of function pointer
+       (#) CommandListCpltCallback (member of GPU2D handle structure) to notify the upper level
+           about the completion of Command List execution.
+
+     (#) Callback HAL_GPU2D_CommandListCpltCallback is invoked when the GPU2D hardware executes
+         the programmed command list (Command List execution completion).
+
+    (++) This callback is called when the compilation defines USE_HAL_GPU2D_REGISTER_CALLBACKS
+         is set to 0 or not defined.
+
+        (++) This callback should be implemented in the application side. It should notify
+             the upper level that the programmed command list is completed.
+
+      (#) To control the GPU2D state, use the following function: HAL_GPU2D_GetState().
+
+      (#) To read the GPU2D error code, use the following function: HAL_GPU2D_GetError().
+
+     *** GPU2D HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in GPU2D HAL driver :
+
+      (+) __HAL_GPU2D_RESET_HANDLE_STATE: Reset GPU2D handle state.
+      (+) __HAL_GPU2D_GET_FLAG: Get the GPU2D pending flags.
+      (+) __HAL_GPU2D_CLEAR_FLAG: Clear the GPU2D pending flags.
+      (+) __HAL_GPU2D_GET_IT_SOURCE: Check whether the specified GPU2D interrupt is enabled or not.
+
+     *** Callback registration ***
+     ===================================
+     [..]
+      (#) The compilation define  USE_HAL_GPU2D_REGISTER_CALLBACKS when set to 1
+          allows the user to configure dynamically the driver callbacks.
+          Use function @ref HAL_GPU2D_RegisterCallback() to register a user callback.
+
+      (#) Function @ref HAL_GPU2D_RegisterCallback() allows to register following callbacks:
+            (+) CommandListCpltCallback : callback for Command List completion.
+            (+) MspInitCallback    : GPU2D MspInit.
+            (+) MspDeInitCallback  : GPU2D MspDeInit.
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+      (#) Use function @ref HAL_GPU2D_UnRegisterCallback() to reset a callback to the default
+          weak (surcharged) function.
+          @ref HAL_GPU2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (+) CommandListCpltCallback : callback for Command List completion.
+            (+) MspInitCallback    : GPU2D MspInit.
+            (+) MspDeInitCallback  : GPU2D MspDeInit.
+
+          Callbacks can be registered/unregistered in READY state only.
+          Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+          in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+          during the Init/DeInit.
+          In that case first register the MspInit/MspDeInit user callbacks
+          using @ref HAL_GPU2D_RegisterCallback before calling @ref HAL_GPU2D_DeInit
+          or @ref HAL_GPU2D_Init function.
+
+          When The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS is set to 0 or
+          not defined, the callback registering feature is not available
+          and weak (surcharged) callbacks are used.
+
+     [..]
+      (@) You can refer to the GPU2D HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+#ifdef HAL_GPU2D_MODULE_ENABLED
+#if defined (GPU2D)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPU2D  GPU2D
+  * @brief GPU2D HAL module driver
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
+  * @{
+  */
+
+/** @defgroup GPU2D_Write_Read Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPU2D register
+  * @param  __INSTANCE__ GPU2D Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define GPU2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(*(__IO uint32_t *)(__INSTANCE__\
+                                                                   + __REG__), __VALUE__)
+
+/**
+  * @brief  Read a value in GPU2D register
+  * @param  __INSTANCE__ GPU2D Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define GPU2D_ReadReg(__INSTANCE__, __REG__) READ_REG(*(__IO uint32_t *)(__INSTANCE__ + __REG__))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPU2D_Exported_Functions GPU2D Exported Functions
+  * @{
+  */
+
+/** @defgroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the GPU2D
+      (+) De-initialize the GPU2D
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GPU2D according to the specified
+  *         parameters in the GPU2D_InitTypeDef and create the associated handle.
+  * @param  hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d)
+{
+  /* Check the GPU2D handle validity */
+  if (hgpu2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
+
+  if (hgpu2d->State == HAL_GPU2D_STATE_RESET)
+  {
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+    /* Reset Callback pointers in HAL_GPU2D_STATE_RESET only */
+    hgpu2d->CommandListCpltCallback = HAL_GPU2D_CommandListCpltCallback;
+    if (hgpu2d->MspInitCallback == NULL)
+    {
+      hgpu2d->MspInitCallback = HAL_GPU2D_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hgpu2d->MspInitCallback(hgpu2d);
+#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
+    /* Init the low level hardware */
+    HAL_GPU2D_MspInit(hgpu2d);
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+
+    /* Allocate lock resource and initialize it */
+    hgpu2d->Lock = HAL_UNLOCKED;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hgpu2d);
+
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+  /* Reset the CommandListCpltCallback handler */
+  hgpu2d->CommandListCpltCallback = NULL;
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+
+  /* Update error code */
+  hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
+
+  /* Initialize the GPU2D state*/
+  hgpu2d->State = HAL_GPU2D_STATE_READY;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hgpu2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the GPU2D peripheral registers to their default reset
+  *         values.
+  * @param  hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d)
+{
+  /* Check the GPU2D handle validity */
+  if (hgpu2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hgpu2d);
+
+  if (hgpu2d->State == HAL_GPU2D_STATE_READY)
+  {
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+    if (hgpu2d->MspDeInitCallback == NULL)
+    {
+      hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit;
+    }
+
+    /* DeInit the low level hardware */
+    hgpu2d->MspDeInitCallback(hgpu2d);
+#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
+    /* Carry on with de-initialization of low level hardware */
+    HAL_GPU2D_MspDeInit(hgpu2d);
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+  }
+
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+  /* Reset the CommandListCpltCallback handler */
+  hgpu2d->CommandListCpltCallback = NULL;
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+
+  /* Update error code */
+  hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
+
+  /* Reset the GPU2D state*/
+  hgpu2d->State = HAL_GPU2D_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hgpu2d);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the GPU2D MSP.
+  * @param  hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @retval None
+  */
+__weak void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgpu2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_GPU2D_MspInit can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitializes the GPU2D MSP.
+  * @param  hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
+  *                 the configuration information for the GPU2D.
+  * @retval None
+  */
+__weak void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgpu2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_GPU2D_MspDeInit can be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User GPU2D callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hgpu2d GPU2D handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
+  *          @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
+  * @param pCallback pointer to the callback function
+  * @note Weak predefined callback is defined for HAL_GPU2D_MSPINIT_CB_ID and HAL_GPU2D_MSPDEINIT_CB_ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
+                                             pGPU2D_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the GPU2D handle validity */
+  if (hgpu2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hgpu2d);
+
+  /* Check the pCallback parameter is valid or not */
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
+        || (hgpu2d->State == HAL_GPU2D_STATE_RESET))
+    {
+      switch (CallbackID)
+      {
+        case HAL_GPU2D_MSPINIT_CB_ID:
+          hgpu2d->MspInitCallback = pCallback;
+          break;
+
+        case HAL_GPU2D_MSPDEINIT_CB_ID:
+          hgpu2d->MspDeInitCallback = pCallback;
+          break;
+
+        default :
+          /* Update the error code */
+          hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Release lock */
+  __HAL_UNLOCK(hgpu2d);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a GPU2D callback
+  *         GPU2D Callback is redirected to the weak (surcharged) predefined callback
+  * @param hgpu2d GPU2D handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
+  *          @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
+  * @note Callback pointers will be set to legacy weak predefined callbacks for HAL_GPU2D_MSPINIT_CB_ID and
+  *       HAL_GPU2D_MSPDEINIT_CB_ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the GPU2D handle validity */
+  if (hgpu2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hgpu2d);
+
+  if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
+      || (HAL_GPU2D_STATE_RESET == hgpu2d->State))
+  {
+    switch (CallbackID)
+    {
+      case HAL_GPU2D_MSPINIT_CB_ID:
+        hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; /* Legacy weak Msp Init */
+        break;
+
+      case HAL_GPU2D_MSPDEINIT_CB_ID:
+        hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; /* Legacy weak Msp DeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release lock */
+  __HAL_UNLOCK(hgpu2d);
+
+  return status;
+}
+
+/**
+  * @brief  Register GPU2D Command List Complete Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hgpu2d GPU2D handle
+  * @param pCallback pointer to the Command List Complete Callback function
+  * @note Weak predefined callback is defined for Command List Complete
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
+                                                            pGPU2D_CommandListCpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the GPU2D handle validity */
+  if (hgpu2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hgpu2d);
+
+  /* Check the CallbackID is valid or not */
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
+        || (HAL_GPU2D_STATE_RESET == hgpu2d->State))
+    {
+      hgpu2d->CommandListCpltCallback = pCallback;
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Release lock */
+  __HAL_UNLOCK(hgpu2d);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a GPU2D Command List Complete Callback
+  *         GPU2D Command List Complete Callback is redirected to the weak (surcharged) predefined callback
+  * @param hgpu2d GPU2D handle
+  * @note Callback pointer will be invalidate (NULL value)
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the GPU2D handle validity */
+  if (hgpu2d == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hgpu2d);
+
+  if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
+      || (hgpu2d->State == HAL_GPU2D_STATE_RESET))
+  {
+    hgpu2d->CommandListCpltCallback = NULL; /* Invalidate the Callback pointer */
+  }
+  else
+  {
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hgpu2d);
+
+  return status;
+}
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup GPU2D_Exported_Functions_Group2 IO operation functions
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Read GPU2D Register value.
+      (+) Write a value to GPU2D Register.
+      (+) handle GPU2D interrupt request.
+      (+) Command List Complete Transfer Complete callback.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read GPU2D Register. Helper function for the higher-level library.
+  * @param  hgpu2d    Pointer to a GPU2D_HandleTypeDef structure that contains
+  *                   the configuration information for the GPU2D.
+  * @param  offset    The register offset from GPU2D base address to read.
+  * @retval Register value
+  */
+uint32_t HAL_GPU2D_ReadRegister(const GPU2D_HandleTypeDef *hgpu2d, uint32_t offset)
+{
+  uint32_t value;
+
+  /* Check the GPU2D handle validity */
+  assert_param(hgpu2d != NULL);
+
+  /* Check the parameters */
+  assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
+  assert_param(IS_GPU2D_OFFSET(offset));
+
+  /* No locking is required since reading a register is an atomic operation
+   * and doesn't incur a state change in hal_gpu2d. */
+  value = GPU2D_ReadReg(hgpu2d->Instance, offset);
+
+  return value;
+}
+
+/**
+  * @brief  Write a value to GPU2D Register. Helper function for the higher-level library.
+  * @param  hgpu2d    Pointer to a GPU2D_HandleTypeDef structure that contains
+  *                   the configuration information for the GPU2D.
+  * @param  offset    The register offset from GPU2D base address to write.
+  * @param  value     The value to be written to provided register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value)
+{
+  /* Check the GPU2D handle validity */
+  assert_param(hgpu2d != NULL);
+
+  /* Check the parameters */
+  assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
+  assert_param(IS_GPU2D_OFFSET(offset));
+
+  /* No locking is required since writing a register is an atomic operation
+   * and doesn't incur a state change in hal_gpu2d. */
+  GPU2D_WriteReg(hgpu2d->Instance, offset, value);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle GPU2D interrupt request.
+  * @param  hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @retval None
+  */
+void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
+{
+  uint32_t isr_flags = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_ITCTRL);
+
+  /* Command List Complete Interrupt management */
+  if ((isr_flags & GPU2D_FLAG_CLC) != 0U)
+  {
+    uint32_t last_cl_id;
+
+    /* Clear the completion flag */
+    __HAL_GPU2D_CLEAR_FLAG(hgpu2d, GPU2D_FLAG_CLC);
+
+    last_cl_id = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_CLID);
+
+    /* Command List Complete Callback */
+#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
+    if (hgpu2d->CommandListCpltCallback != NULL)
+    {
+      hgpu2d->CommandListCpltCallback(hgpu2d, last_cl_id);
+    }
+#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
+    HAL_GPU2D_CommandListCpltCallback(hgpu2d, last_cl_id);
+#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
+  }
+}
+
+/**
+  * @brief  Handle GPU2D Error interrupt request.
+  * @param  hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @retval None
+  */
+void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
+{
+  HAL_GPU2D_ErrorCallback(hgpu2d);
+}
+
+/**
+  * @brief  Command List Complete callback.
+  * @param  hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @param  CmdListID Command list ID that got completed.
+  * @retval None
+  */
+__weak void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgpu2d);
+  UNUSED(CmdListID);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_GPU2D_CommandListCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Error handler callback.
+  * @param  hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @retval None
+  */
+__weak void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hgpu2d);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_GPU2D_ErrorCallback can be implemented in the user file.
+            The default implementation stops the execution as an error is considered
+            fatal and non recoverable.
+   */
+
+  for (;;)
+  {
+    /* infinite loop */
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
+  *  @brief    Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to:
+      (+) Get the GPU2D state
+      (+) Get the GPU2D error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the GPU2D state
+  * @param  hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
+  *                the configuration information for the GPU2D.
+  * @retval GPU2D state
+  */
+HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d)
+{
+  return hgpu2d->State;
+}
+
+/**
+  * @brief  Return the GPU2D error code
+  * @param  hgpu2d  pointer to a GPU2D_HandleTypeDef structure that contains
+  *                 the configuration information for GPU2D.
+  * @retval GPU2D Error Code
+  */
+uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d)
+{
+  return hgpu2d->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* GPU2D */
+#endif /* HAL_GPU2D_MODULE_ENABLED */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_hash.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_hash.c
new file mode 100644
index 000000000..ca3e8befa
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_hash.c
@@ -0,0 +1,3147 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_hash.c
+  * @author  MCD Application Team
+  * @brief   HASH HAL module driver.
+  *          This file provides firmware functions to manage HASH peripheral
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+   [..]
+    The HASH HAL driver can be used as follows:
+
+    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
+        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
+        (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_Start_IT())
+            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
+            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
+            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
+        (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_Start_DMA())
+            (+++) Enable the DMA interface clock
+            (+++) Configure and enable one DMA to manage data transfer from
+                memory to peripheral (input DMA). Managing data transfer from
+                peripheral to memory can be performed only using CPU.
+            (+++) Associate the initialized DMA handle to the HASH DMA handle
+                using  __HAL_LINKDMA()
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                interrupt on the DMA: use
+                 HAL_NVIC_SetPriority() and
+                 HAL_NVIC_EnableIRQ()
+
+    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
+        (##) resorts to HAL_HASH_MspInit() for low-level initialization,
+        (##) configures the data type: no swap, half word swap, bit swap or byte swap,
+        (##) configures the Algorithm : MD5, SHA1 or SHA2
+
+    (#)Three processing schemes are available:
+        (##) Polling mode: processing APIs are blocking functions
+             i.e. they process the data and wait till the digest computation is finished,
+             e.g. HAL_HASH_Start() for HASH or HAL_HMAC_Start() for HMAC
+        (##) Interrupt mode: processing APIs are not blocking functions
+                i.e. they process the data under interrupt,
+                e.g. HAL_HASH_Start_IT() for HASH or HAL_HMAC_Start_IT() for HMAC
+        (##) DMA mode: processing APIs are not blocking functions and the CPU is
+             not used for data transfer i.e. the data transfer is ensured by DMA,
+                e.g. HAL_HASH_Start_DMA() for HASH or HAL_HMAC_Start_DMA() for HMAC.
+
+    (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
+       initialized and processes the buffer fed in input. When the input data have all been
+       fed to the Peripheral, the digest computation can start.
+
+    (#)Multi-buffer processing HASH and HMAC are possible in polling, interrupt and DMA modes.
+        (##) In polling mode, API HAL_HASH_Accumulate()/HAL_HASH_HMAC_Accumulate() must be called
+             for each input buffer, except for the last one.
+             User must resort to HAL_HASH_AccumulateLast()/HAL_HASH_HMAC_AccumulateLast()
+             to enter the last one and retrieve as well the computed digest.
+
+        (##) In interrupt mode, API HAL_HASH_Accumulate_IT()/HAL_HASH_HMAC_Accumulate_IT() must
+             be called for each input buffer, except for the last one.
+             User must resort to HAL_HASH_AccumulateLast_IT()/HAL_HASH_HMAC_AccumulateLast_IT()
+             to enter the last one and retrieve as well the computed digest.
+
+        (##) In DMA mode, once initialization is done, MDMAT bit must be set through
+             __HAL_HASH_SET_MDMAT() macro.
+             From that point, each buffer can be fed to the Peripheral through HAL_HASH_Start_DMA() API
+             for HASH and HAL_HASH_HMAC_Start_DMA() API for HMAC .
+             Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+             macro then wrap-up the HASH processing in feeding the last input buffer through the
+             same API HAL_HASH_Start_DMA()for HASH and HAL_HASH_HMAC_Start_DMA() API for HMAC and
+             retrieve as well the computed digest.
+
+    (#)To use this driver (version 2.0.0) with application developed with old driver (version 1.0.0) user have to:
+        (##) Add Algorithm as parameter like DataType or KeySize.
+        (##) Use new API HAL_HASH_Start() for HASH and HAL_HASH_HMAC_Start() for HMAC processing instead of old API
+             like HAL_HASH_SHA1_Start and HAL_HMAC_SHA1_Start.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (HASH)
+
+/** @defgroup HASH  HASH
+  * @brief HASH HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HASH_Private_Defines HASH Private Defines
+  * @{
+  */
+#define HASH_TIMEOUTVALUE                         1000U  /*!< Time-out value  */
+#define BLOCK_64B                                 64U    /*!< block Size equal to 64 bytes */
+#define BLOCK_128B                                128U   /*!< block Size equal to 128 bytes */
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
+  * @{
+  */
+#define HASH_NUMBER_OF_CSR_REGISTERS              103U /*!< Number of Context Swap Registers */
+/**
+  * @}
+  */
+
+/* Private Constants ---------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */
+static void HASH_GetDigest(const HASH_HandleTypeDef *hhash, const uint8_t *pMsgDigest, uint8_t Size);
+static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, uint32_t Size);
+static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash);
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
+  * @{
+  */
+
+/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and configuration functions.
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the HASH according to the specified parameters
+          in the HASH_InitTypeDef and create the associated handle
+      (+) DeInitialize the HASH peripheral
+      (+) Initialize the HASH MCU Specific Package (MSP)
+      (+) DeInitialize the HASH MSP
+      (+) Configure HASH (HAL_HASH_SetConfig) with the specified parameters in the HASH_ConfigTypeDef
+          Parameters which are configured in This section are :
+          (+) Data Type : no swap, half word swap, bit swap or byte swap
+          (+) Algorithm : MD5,SHA1 or SHA2
+      (+) Get HASH configuration (HAL_HASH_GetConfig) from the specified parameters in the HASH_HandleTypeDef
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HASH according to the specified parameters in the
+            HASH_HandleTypeDef and create the associated handle.
+  * @note   Only Algorithm and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(),
+  *         other configuration bits are set by HASH or HMAC processing APIs.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
+{
+  uint32_t cr_value;
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+  assert_param(IS_HASH_ALGORITHM(hhash->Init.Algorithm));
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+  if (hhash->State == HAL_HASH_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhash->Lock = HAL_UNLOCKED;
+
+    /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
+    hhash->InCpltCallback =  HAL_HASH_InCpltCallback;     /* Legacy weak InCpltCallback */
+    hhash->DgstCpltCallback =  HAL_HASH_DgstCpltCallback; /* Legacy weak DgstCpltCallback */
+    hhash->ErrorCallback =  HAL_HASH_ErrorCallback;       /* Legacy weak ErrorCallback */
+    if (hhash->MspInitCallback == NULL)
+    {
+      hhash->MspInitCallback = HAL_HASH_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hhash->MspInitCallback(hhash);
+  }
+#else
+  if (hhash->State == HAL_HASH_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhash->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_HASH_MspInit(hhash);
+  }
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+
+  /* Set the key size, data type and Algorithm */
+  cr_value = (uint32_t)(hhash->Init.DataType | hhash->Init.Algorithm);
+  /* Set the key size, data type, algorithm and mode */
+  MODIFY_REG(hhash->Instance->CR, HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, cr_value);
+
+  /* Change HASH phase to Ready */
+  hhash->Phase = HAL_HASH_PHASE_READY;
+
+  /* Change HASH state to Ready */
+  hhash->State = HAL_HASH_STATE_READY;
+
+  /* Reset error code field */
+  hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+  /* Reset suspension request flag */
+  hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+#endif /* (USE_HAL_HASH_SUSPEND_RESUME) */
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the HASH peripheral.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
+{
+  /* Check the HASH handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Change the default HASH phase */
+  hhash->Phase = HAL_HASH_PHASE_READY;
+
+  /* Reset HashInCount */
+  hhash->HashInCount = 0U;
+
+  /* Reset multi buffers accumulation flag */
+  hhash->Accumulation = 0U;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+  if (hhash->MspDeInitCallback == NULL)
+  {
+    hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hhash->MspDeInitCallback(hhash);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_HASH_MspDeInit(hhash);
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+
+  /* Set the HASH state to Ready */
+  hhash->State = HAL_HASH_STATE_RESET;
+
+  __HAL_UNLOCK(hhash);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the HASH according to the specified
+  *         parameters in the HASH_ConfigTypeDef
+  * @param  hhash pointer to a HASH_HandleTypeDef structure
+  * @param  pConf pointer to a HASH_ConfigTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf)
+{
+  uint32_t cr_value;
+
+  /* Check the HASH handle allocation */
+  if ((hhash == NULL) || (pConf == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_HASH_DATATYPE(pConf->DataType));
+  assert_param(IS_HASH_ALGORITHM(pConf->Algorithm));
+
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    __HAL_LOCK(hhash);
+
+    /* Set HASH parameters */
+    hhash->Init.DataType   = pConf->DataType;
+    hhash->Init.pKey       = pConf->pKey;
+    hhash->Init.Algorithm  = pConf->Algorithm;
+    hhash->Init.KeySize    = pConf->KeySize;
+
+    /* Set the key size, data type and Algorithm */
+    cr_value = (uint32_t)(hhash->Init.DataType | hhash->Init.Algorithm);
+    /* Set the key size, data type, algorithm and mode */
+    MODIFY_REG(hhash->Instance->CR, HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, cr_value);
+
+    /* Change HASH phase to Ready */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+
+    /* Change HASH state to Ready */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Reset error code field */
+    hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+
+    __HAL_UNLOCK(hhash);
+
+    return HAL_OK;
+
+  }
+  else
+  {
+    /* Busy error code field */
+    hhash->ErrorCode |= HAL_HASH_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get HASH Configuration parameters in associated handle
+  * @param  pConf pointer to a HASH_HandleTypeDef structure
+  * @param  hhash pointer to a HASH_ConfigTypeDef structure that contains
+  *         the configuration information for HASH module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf)
+{
+
+  /* Check the HASH handle allocation */
+  if ((hhash == NULL) || (pConf == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    __HAL_LOCK(hhash);
+
+    /* Set HASH parameters */
+    pConf->DataType   = hhash->Init.DataType;
+    pConf->pKey       = hhash->Init.pKey;
+    pConf->Algorithm  = hhash->Init.Algorithm;
+    pConf->KeySize    = hhash->Init.KeySize;
+
+    /* Change HASH state to Ready */
+    hhash->State = HAL_HASH_STATE_READY;
+    __HAL_UNLOCK(hhash);
+
+    return HAL_OK;
+
+  }
+  else
+  {
+    /* Busy error code field */
+    hhash->ErrorCode |= HAL_HASH_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Initialize the HASH MSP.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module.
+  * @retval None
+  */
+__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_MspInit() can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the HASH MSP.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module.
+  * @retval None
+  */
+__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_MspDeInit() can be implemented in the user file.
+   */
+}
+
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User HASH Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @param hhash HASH handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg HAL_HASH_INPUTCPLT_CB_ID input completion callback ID
+  *          @arg HAL_HASH_DGSTCPLT_CB_ID digest computation completion callback ID
+  *          @arg HAL_HASH_ERROR_CB_ID error callback ID
+  *          @arg HAL_HASH_MSPINIT_CB_ID MspInit callback ID
+  *          @arg HAL_HASH_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+                                            pHASH_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HASH_INPUTCPLT_CB_ID :
+        hhash->InCpltCallback = pCallback;
+        break;
+
+      case HAL_HASH_DGSTCPLT_CB_ID :
+        hhash->DgstCpltCallback = pCallback;
+        break;
+
+      case HAL_HASH_ERROR_CB_ID :
+        hhash->ErrorCallback = pCallback;
+        break;
+
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhash->State == HAL_HASH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a HASH Callback
+  *         HASH Callback is redirected to the weak (overridden) predefined callback
+  * @param hhash HASH handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+  *          @arg HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+  *          @arg HAL_HASH_ERROR_CB_ID HASH error Callback ID
+  *          @arg HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+  *          @arg HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HASH_INPUTCPLT_CB_ID :
+        hhash->InCpltCallback = HAL_HASH_InCpltCallback;     /* Legacy weak input completion callback */
+        break;
+
+      case HAL_HASH_DGSTCPLT_CB_ID :
+        hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak digest computation
+      completion callback */
+        break;
+
+      case HAL_HASH_ERROR_CB_ID :
+        hhash->ErrorCallback = HAL_HASH_ErrorCallback;       /* Legacy weak error callback */
+        break;
+
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak MspInit Callback */
+        break;
+
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak MspDeInit Callback */
+        break;
+
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhash->State == HAL_HASH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak MspInit Callback */
+        break;
+
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak MspDeInit Callback */
+        break;
+
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+/**
+  * @brief  Save the HASH context in case of processing suspension.
+  * @param  hhash HASH handle.
+  * @param  pMemBuffer pointer to the memory buffer where the HASH context
+  *         is saved.
+  * @note   The IMR, STR, CR then all the CSR registers are saved
+  *         in that order. Only the r/w bits are read to be restored later on.
+  * @note   By default, all the context swap registers (there are
+  *         HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
+  * @note   pMemBuffer points to a buffer allocated by the user. The buffer size
+  *         must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
+  * @retval None
+  */
+void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
+{
+  uint32_t mem_ptr = (uint32_t)pMemBuffer;
+  uint32_t csr_ptr = (uint32_t)(hhash->Instance->CSR);
+  uint32_t i;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* Save IMR register content */
+  *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->IMR, HASH_IT_DINI | HASH_IT_DCI);
+  mem_ptr += 4U;
+  /* Save STR register content */
+  *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->STR, HASH_STR_NBLW);
+  mem_ptr += 4U;
+  /* Save CR register content */
+  *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO |
+                                    HASH_CR_LKEY | HASH_CR_MDMAT);
+
+  mem_ptr += 4U;
+  /* By default, save all CSRs registers */
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
+  {
+    *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr);
+    mem_ptr += 4U;
+    csr_ptr += 4U;
+  }
+  /* Save low-priority block HASH handle parameters */
+  hhash->Init_saved              = hhash->Init;
+  hhash->pHashOutBuffPtr_saved   = hhash->pHashOutBuffPtr;
+  hhash->HashInCount_saved       = hhash->HashInCount;
+  hhash->Size_saved              = hhash->Size;
+  hhash->pHashInBuffPtr_saved    = hhash->pHashInBuffPtr;
+  hhash->Phase_saved             = hhash->Phase;
+  hhash->pHashKeyBuffPtr_saved   = hhash->pHashKeyBuffPtr;
+}
+
+
+/**
+  * @brief  Restore the HASH context in case of processing resumption.
+  * @param  hhash HASH handle.
+  * @param  pMemBuffer pointer to the memory buffer where the HASH context
+  *         is stored.
+  * @note   The IMR, STR, CR then all the CSR registers are restored
+  *         in that order. Only the r/w bits are restored.
+  * @note   By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
+  *         of those) are restored (all of them have been saved by default
+  *         beforehand).
+  * @retval None
+  */
+void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
+{
+  uint32_t mem_ptr = (uint32_t)pMemBuffer;
+  uint32_t csr_ptr = (uint32_t)(hhash->Instance->CSR);
+  uint32_t i;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* Restore IMR register content */
+  WRITE_REG(hhash->Instance->IMR, (*(uint32_t *)(mem_ptr)));
+  mem_ptr += 4U;
+  /* Restore STR register content */
+  WRITE_REG(hhash->Instance->STR, (*(uint32_t *)(mem_ptr)));
+  mem_ptr += 4U;
+  /* Restore CR register content */
+  WRITE_REG(hhash->Instance->CR, (*(uint32_t *)(mem_ptr)));
+  mem_ptr += 4U;
+
+  /* Reset the HASH processor before restoring the Context
+  Swap Registers (CSR) */
+  SET_BIT(hhash->Instance->CR, HASH_CR_INIT);
+
+
+  /* By default, restore all CSR registers */
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
+  {
+    WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr)));
+    mem_ptr += 4U;
+    csr_ptr += 4U;
+  }
+
+  /* Restore low-priority block HASH handle parameters */
+  hhash->Init              = hhash->Init_saved;
+  hhash->pHashOutBuffPtr   = hhash->pHashOutBuffPtr_saved;
+  hhash->HashInCount       = hhash->HashInCount_saved;
+  hhash->Size              = hhash->Size_saved;
+  hhash->pHashInBuffPtr    = hhash->pHashInBuffPtr_saved;
+  hhash->Phase             = hhash->Phase_saved;
+  hhash->State             = HAL_HASH_STATE_SUSPENDED;
+  hhash->pHashKeyBuffPtr   = hhash->pHashKeyBuffPtr_saved;
+}
+
+/**
+  * @brief  Initiate HASH processing suspension when in interruption mode.
+  * @param  hhash HASH handle.
+  * @note   Set the handle field SuspendRequest to the appropriate value so that
+  *         the on-going HASH processing is suspended as soon as the required
+  *         conditions are met. Note that the actual suspension is carried out
+  *         by the functions HASH_WriteData() in polling mode and HASH_IT() in
+  *         interruption mode.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+  uint32_t remainingwords; /*remaining number in of source block to be transferred.*/
+  uint32_t nbbytePartialHash  = (((hhash->Instance->SR) >> 16U) * 4U); /* Nb byte  to enter in HASH fifo
+                                                                      to trig a partial HASH computation*/
+  uint32_t sizeinwords;/* number in word of source block to be transferred.*/
+
+  /* suspension in DMA mode*/
+  if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DMAS) != RESET)
+  {
+    if (hhash->State == HAL_HASH_STATE_READY)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+
+      /* Clear the DMAE bit to disable the DMA interface */
+      CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
+
+      /* Wait until the last DMA transfer is complete (DMAS = 0 in the HASH_SR register) */
+      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DMAS, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* At this point, DMA interface is disabled and no transfer is on-going */
+      /* Retrieve from the DMA handle how many words remain to be written */
+      /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */
+      remainingwords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \
+                        & DMA_CBR1_BNDT) / 4U;
+      remainingwords += ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CSR) \
+                         & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos;
+
+      if (remainingwords <= nbbytePartialHash)
+      {
+        /* No suspension attempted since almost to the end of the transferred data. */
+        /* Best option for user code is to wrap up low priority message hashing     */
+        return HAL_ERROR;
+      }
+
+      /* Disable DMA channel */
+      /* Note that the Abort function will
+        - Clear the transfer error flags
+        - Unlock
+        - Set the State
+      */
+      if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DCIS) != RESET)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Wait until the hash processor is ready (no block is being processed), that is wait for DINIS=1 in HASH_SR */
+      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DINIS, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      /* Compute how many words were supposed to be transferred by DMA */
+      sizeinwords = (((hhash->Size % 4U) != 0U) ? \
+                     ((hhash->Size + 3U) / 4U) : (hhash->Size / 4U));
+      /* Accordingly, update the input pointer that points at the next word to be
+         transferred to the Peripheral by DMA */
+      hhash->pHashInBuffPtr +=  4U * (sizeinwords - remainingwords) ;
+
+      /* And store in HashInCount the remaining size to transfer (in bytes) */
+      hhash->HashInCount = 4U * remainingwords;
+
+
+      hhash->State = HAL_HASH_STATE_SUSPENDED;
+      __HAL_UNLOCK(hhash);
+      return HAL_OK;
+    }
+
+  }
+  else /* suspension when in interruption mode*/
+  {
+    /* Set Handle Suspend Request field */
+    hhash->SuspendRequest = HAL_HASH_SUSPEND;
+    return HAL_OK;
+  }
+}
+#endif /* USE_HAL_HASH_SUSPEND_RESUME */
+/**
+  * @}
+  */
+
+
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions
+  *  @brief   HASH processing functions using different mode.
+  *
+@verbatim
+ ===============================================================================
+                 ##### HASH processing functions #####
+ ===============================================================================
+    [..]  This section provides API allowing to calculate the hash value using
+          one of the HASH algorithms supported by the peripheral.
+
+    [..] For a single buffer to be hashed, user can resort to one of three processing
+         functions available .
+      (+) Polling mode : HAL_HASH_Start()
+      (+) Interrupt mode : HAL_HASH_Start_IT()
+      (+) DMA mode : HAL_HASH_Start_DMA()
+
+    [..]  In case of multi-buffer HASH processing (a single digest is computed while
+          several buffers are fed to the Peripheral), the user can resort to successive calls
+          to :
+      (+) Polling mode : HAL_HASH_Accumulate() and wrap-up the digest computation by a call
+          to HAL_HASH_AccumulateLast()
+      (+) Interrupt mode : HAL_HASH_Accumulate_IT() and wrap-up the digest computation by a call
+          to HAL_HASH_AccumulateLast_IT()
+      (+) DMA mode : HAL_HASH_Start_DMA(), MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro,
+          before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+          macro then wrap-up the HASH processing in feeding the last input buffer through the
+          same API HAL_HASH_Start_DMA()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  HASH peripheral processes in polling mode pInBuffer then reads the computed digest.
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @param  Timeout specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                 uint8_t *const pOutBuffer, uint32_t Timeout)
+{
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+
+    /* Set HASH mode */
+    CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE);
+    /* Reset the HASH processor core */
+    MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT);
+
+    /* Configure the number of valid bits in last word of the message */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U));
+
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+    HASH_WriteData(hhash, pInBuffer, Size);
+
+    /* Start the message padding then the Digest calculation */
+    SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+    /* Wait for digest calculation completion status(DCIS) flag to be set */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Read the message digest */
+    HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash));
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Reset HASH state machine */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  HASH peripheral processes in interrupt mode pInBuffer then reads the computed digest.
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                    uint8_t *const pOutBuffer)
+{
+  HAL_StatusTypeDef status;
+  HAL_HASH_StateTypeDef temp_state;
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process or suspended */
+  temp_state = hhash->State;
+  if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    if (hhash->State == HAL_HASH_STATE_READY)
+    {
+      /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+      hhash->HashInCount =  0U;
+      hhash->pHashInBuffPtr = pInBuffer;
+      hhash->pHashOutBuffPtr = pOutBuffer;
+      hhash->Size = Size;
+
+      /* Set HASH mode */
+      CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE);
+      /* Reset the HASH processor core */
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT);
+
+      /* Configure the number of valid bits in last word of the message */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U));
+    }
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+    /* Enable the specified HASH interrupt*/
+    __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+    status = HASH_WriteData_IT(hhash);
+  }
+  else
+  {
+    status =  HAL_BUSY;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  HASH peripheral processes in DMA mode pInBuffer then reads the computed digest.
+  * @note   Multi-buffer HASH processing is possible, consecutive calls to HAL_HASH_Start_DMA
+  *         (MDMAT bit must be set) can be used to feed several input buffers
+  *         back-to-back to the Peripheral that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_Start_DMA (MDMAT bit must be reset).
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes (must be a multiple of 4 in
+  *         case of Multi-buffer and not last buffer).
+  * @param  pOutBuffer pointer to the computed digest.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint8_t *const pOutBuffer)
+{
+  HAL_StatusTypeDef status;
+  HAL_HASH_StateTypeDef temp_state;
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process or suspended  */
+  temp_state = hhash->State;
+  if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED))
+  {
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Check if initialization phase has not been already performed */
+    if (hhash->State == HAL_HASH_STATE_READY)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+      hhash->HashInCount =  0U;
+      hhash->pHashInBuffPtr = pInBuffer;
+      hhash->pHashOutBuffPtr = pOutBuffer;
+      hhash->HashInCount =  0U;
+      hhash->Size = Size;
+
+      /* Check if initialization phase has already been performed.
+      If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
+      API is processing a new input data message in case of multi-buffer HASH
+      computation. */
+      if (hhash->Phase == HAL_HASH_PHASE_READY)
+      {
+        /* Set HASH mode */
+        CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE);
+        /* Reset the HASH processor core */
+        MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT);
+
+        /* Set the phase */
+        hhash->Phase = HAL_HASH_PHASE_PROCESS;
+      }
+      /* Configure the number of valid bits in last word of the message */
+      if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U)
+      {
+        /* Configure the number of valid bits in last word of the message */
+        MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Size) % 4U));
+      }
+      else
+      {
+        /* Configure the number of valid bits in last word of the message */
+        MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U);
+      }
+
+    }
+    else /* HAL_HASH_STATE_SUSPENDED */
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+      /*only part not yet hashed to compute  */
+      hhash->Size = hhash->HashInCount;
+    }
+    /* Set the HASH DMA transfer complete callback */
+    hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+    /* Set the DMA error callback */
+    hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+    if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
+      {
+        /* Enable the DMA channel */
+        hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
+          = ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : (hhash->Size));
+        hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\
+          = (uint32_t)(hhash->pHashInBuffPtr);  /* Set DMA source address */
+        hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\
+          = (uint32_t)&hhash->Instance->DIN; /* Set DMA destination address */
+
+        status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
+      }
+      else
+      {
+        /* Return error status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_DMA_Start_IT(hhash->hdmain, (uint32_t)pInBuffer, (uint32_t)&hhash->Instance->DIN, \
+                                ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : \
+                                 (hhash->Size)));
+    }
+    if (status != HAL_OK)
+    {
+      /* DMA error code field */
+      hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+
+      /* Return error */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+      /*Call registered error callback*/
+      hhash->ErrorCallback(hhash);
+#else
+      /*Call legacy weak error callback*/
+      HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Enable DMA requests */
+      SET_BIT(hhash->Instance->CR, HASH_CR_DMAE);
+    }
+  }
+  else
+  {
+    status =  HAL_BUSY;
+
+  }
+
+  /* Return function status */
+  return status;
+}
+
+
+/**
+  * @brief  HASH peripheral processes in polling mode several input buffers.
+  * @note   Consecutive calls to HAL_HASH_Accumulate() can be used to feed
+  *         several input buffers back-to-back to the Peripheral that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_AccumulateLast()
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes and a multiple of 4.
+  * @param  Timeout specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint32_t Timeout)
+{
+  HAL_HASH_StateTypeDef temp_state;
+
+  /* Check the hash handle allocation and buffer length multiple of 4 */
+  if ((hhash == NULL) || ((Size % 4U) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process or suspended  */
+  temp_state = hhash->State;
+  if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Set HASH mode */
+      CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE);
+      /* Reset the HASH processor core */
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT);
+
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    }
+    HASH_WriteData(hhash, pInBuffer, Size);
+
+    /* Wait for BUSY flag to be cleared */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  End computation of a single HASH signature after several calls to HAL_HASH_Accumulate() API.
+  * @note   Digest is available in pOutBuffer
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @param  Timeout specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *const pOutBuffer, uint32_t Timeout)
+{
+  HAL_HASH_StateTypeDef temp_state;
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process or suspended */
+  temp_state = hhash->State;
+  if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Set HASH mode */
+      CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE);
+      /* Reset the HASH processor core */
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT);
+
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    }
+    /* Configure the number of valid bits in last word of the message */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U));
+
+
+    HASH_WriteData(hhash, pInBuffer, Size);
+
+    /* Start the message padding then the Digest calculation */
+    SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+    /* Wait for digest calculation completion status(DCIS) flag to be set */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+    /* Read the message digest */
+    HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash));
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Reset HASH state machine */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+    hhash->Accumulation = 0;
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  HASH peripheral processes in interrupt mode several input buffers.
+  * @note   Consecutive calls to HAL_HASH_Accumulate_IT() can be used to feed
+  *         several input buffers back-to-back to the Peripheral that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_AccumulateLast_IT()
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes and a multiple of 4.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the hash handle allocation */
+  if ((hhash == NULL) || ((Size % 4U) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size and pHashInBuffPtr parameters  */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+    /* Set multi buffers accumulation flag */
+    hhash->Accumulation = 1U;
+
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Set HASH mode */
+      CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE);
+      /* Reset the HASH processor core */
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT);
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    }
+    /* Enable the specified HASH interrupt*/
+    __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI);
+
+    status = HASH_WriteData_IT(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+  }
+  else
+  {
+    status = HAL_BUSY;
+  }
+  /* Return function status */
+  return status;
+}
+
+
+/**
+  * @brief  End computation of a single HASH signature after several calls to HAL_HASH_Accumulate_IT() API.
+  * @note   Digest is available in pOutBuffer
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *const pOutBuffer)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Set HASH mode */
+      CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE);
+      /* Reset the HASH processor core */
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT);
+
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    }
+    /* Configure the number of valid bits in last word of the message */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U));
+
+    /* Enable the specified HASH interrupt*/
+    __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+    status = HASH_WriteData_IT(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Reset HASH state machine */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+  }
+  else
+  {
+    status =  HAL_BUSY;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HASH_Exported_Functions_Group3 HMAC processing functions
+  *  @brief   HMAC processing functions using different mode.
+  *
+@verbatim
+ ===============================================================================
+                 ##### HMAC processing functions #####
+ ===============================================================================
+    [..]  This section provides API allowing to calculate the HMAC (keyed-hash
+          message authentication code) value using:
+      (+) one of the algorithms supported by the peripheral
+      (+) Key selection
+         (++) Long key : HMAC key is longer than the block size
+         (++) Short key : HMAC key is shorter or equal to the block size
+
+    [..] To calculate the HMAC for a single buffer, user can resort to one of three processing
+         functions available .
+      (+) Polling mode : HAL_HASH_HMAC_Start()
+      (+) Interrupt mode : HAL_HASH_HMAC_Start_IT()
+      (+) DMA mode : HAL_HASH_HMAC_Start_DMA()
+
+    [..]  In case of multi-buffer HMAC processing (a single digest is computed while
+          several buffers are fed to the Peripheral), the user can resort to successive calls
+          to :
+      (+) Polling mode : HAL_HASH_HMAC_Accumulate() and wrap-up the digest computation by a call
+          to HAL_HASH_HMAC_AccumulateLast()
+      (+) Interrupt mode : HAL_HASH_HMAC_Accumulate_IT() and wrap-up the digest computation by a call
+          to HAL_HASH_HMAC_AccumulateLast_IT()
+      (+) DMA mode : HAL_HASH_HMAC_Start_DMA(),MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro,
+          before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+          macro then wrap-up the HMAC processing in feeding the last input buffer through the
+          same API HAL_HASH_HMAC_Start_DMA()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  HMAC in polling mode, HASH peripheral processes Key then pInBuffer then reads the computed digest.
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @param  Timeout specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint8_t *const pOutBuffer, uint32_t Timeout)
+{
+  uint32_t blocksize; /* Block size in bytes */
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HASH Phase */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+
+    /* Reset HashInCount and Initialize Size, pHashKeyBuffPtr, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->pHashKeyBuffPtr =  hhash->Init.pKey;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+
+    /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting bits */
+    if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) ||
+        (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) ||
+        (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256))
+    {
+      blocksize = BLOCK_64B;
+    }
+    else
+    {
+      blocksize = BLOCK_128B;
+    }
+    if (hhash->Init.KeySize > blocksize)
+    {
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                 HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT);
+    }
+    else
+    {
+
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                 HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+    }
+
+    /* Configure the number of valid bits in last word of the Key */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    /* Write Key */
+    HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize);
+
+    /* Start the Key padding then the Digest calculation */
+    SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+    /* Wait for BUSY flag to be cleared */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Configure the number of valid bits in last word of the message */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U));
+
+    /* Write message */
+    HASH_WriteData(hhash, pInBuffer, Size);
+
+    /* Start the message padding then the Digest calculation */
+    SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+    /* Wait for BUSY flag to be cleared */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+    /* Configure the number of valid bits in last word of the Key */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+    /* Write Key */
+    HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize);
+
+    /* Start the Key padding then the Digest calculation */
+    SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+    /* Wait for digest calculation completion status(DCIS) flag to be set */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Read the message digest */
+    HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash));
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Change the HASH phase  */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+
+    /* Return function status */
+    return HAL_OK;
+
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  HMAC accumulate mode, HASH peripheral processes Key then  several input buffers.
+  * @note   Consecutive calls to HAL_HASH_HMAC_Accumulate() can be used to feed
+  *         several input buffers back-to-back to the Peripheral that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_HMAC_AccumulateLast()
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes and a multiple of 4
+  * @param  Timeout specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                           uint32_t Timeout)
+{
+  uint32_t blocksize; /* Block size in bytes */
+
+  /* Check the hash handle allocation and buffer length multiple of 4 */
+  if ((hhash == NULL) || ((Size % 4U) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Initialize Size, pHashInBuffPtr and pHashKeyBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashKeyBuffPtr =  hhash->Init.pKey;
+    hhash->Size = Size;
+
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Reset HashInCount parameter */
+      hhash->HashInCount =  0U;
+      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+      /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */
+      if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) ||
+          (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) ||
+          (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256))
+      {
+        blocksize = BLOCK_64B;
+      }
+      else
+      {
+        blocksize = BLOCK_128B;
+      }
+      if (hhash->Init.KeySize > blocksize)
+      {
+        MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                   HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT);
+      }
+      else
+      {
+
+        MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                   HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+      }
+      /* Set phase process */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+      /* Configure the number of valid bits in last word of the Key */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+      /* Write Key */
+      HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize);
+
+      /* Start the Key padding then the Digest calculation */
+      SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+      /* Wait for BUSY flag to be cleared */
+      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Change the number of valid bits in last word of the message */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U);
+
+    /* Write message */
+    HASH_WriteData(hhash, pInBuffer, Size);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+
+    /* Return function status */
+    return HAL_OK;
+
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  End computation of a single HMAC signature after several calls to HAL_HASH_HMAC_Accumulate() API.
+  * @note   Digest is available in pOutBuffer
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @param  Timeout specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                               uint8_t *const pOutBuffer, uint32_t Timeout)
+{
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Initialize Size, pHashInBuffPtr, pHashKeyBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->pHashKeyBuffPtr =  hhash->Init.pKey;
+    hhash->Size = Size;
+
+    if (hhash->Phase != HAL_HASH_PHASE_PROCESS)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Configure the number of valid bits in last word of the message */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U));
+
+      /* Write message */
+      HASH_WriteData(hhash, pInBuffer, Size);
+
+      /* Start the message padding then the Digest calculation */
+      SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+      /* Wait for BUSY flag to be cleared */
+      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Configure the number of valid bits in last word of the Key */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+      /* Write Key */
+      HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize);
+
+      /* Start the Key padding then the Digest calculation */
+      SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+      /* Wait for digest calculation completion status(DCIS) flag to be set */
+      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read the message digest */
+      HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash));
+    }
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Reset HASH state machine */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  HMAC in interrupt mode, HASH peripheral process Key then pInBuffer then read the computed digest.
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                         uint8_t *const pOutBuffer)
+{
+  HAL_StatusTypeDef status;
+  uint32_t blocksize; /* Block size in bytes */
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HASH Phase */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+
+    /* Reset HashInCount and Initialize Size, pHashKeyBuffPtr, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->pHashKeyBuffPtr =  hhash->Init.pKey;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+
+    /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting bits */
+    if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) ||
+        (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) ||
+        (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256))
+    {
+      blocksize = BLOCK_64B;
+    }
+    else
+    {
+      blocksize = BLOCK_128B;
+    }
+    if (hhash->Init.KeySize > blocksize)
+    {
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                 HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT);
+    }
+    else
+    {
+
+      MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                 HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+    }
+
+    /* Configure the number of valid bits in last word of the Key */
+    MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+  }
+  else if (hhash->State ==  HAL_HASH_STATE_SUSPENDED)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  /* Enable the specified HASH interrupt*/
+  __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+  status = HASH_WriteData_IT(hhash);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  HMAC accumulate in interrupt mode, HASH peripheral processes Key then several input buffers.
+  * @note   Consecutive calls to HAL_HASH_HMAC_Accumulate_IT() can be used to feed
+  *         several input buffers back-to-back to the Peripheral that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_HMAC_AccumulateLast_IT()
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes and a multiple of 4.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
+{
+  HAL_StatusTypeDef status;
+  uint32_t blocksize; /* Block size in bytes */
+
+  /* Check the hash handle allocation and buffer length multiple of 4 */
+  if ((hhash == NULL) || ((Size % 4U) != 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process */
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashKeyBuffPtr =  hhash->Init.pKey;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+    /* Set multi buffers accumulation flag */
+    hhash->Accumulation = 1U;
+
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */
+      if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) ||
+          (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) ||
+          (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256))
+      {
+        blocksize = BLOCK_64B;
+      }
+      else
+      {
+        blocksize = BLOCK_128B;
+      }
+      if (hhash->Init.KeySize > blocksize)
+      {
+        MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                   HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT);
+      }
+      else
+      {
+
+        MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                   HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+      }
+
+      /* Configure the number of valid bits in last word of the Key */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    }
+    /* Enable the specified HASH interrupt*/
+    __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+    status = HASH_WriteData_IT(hhash);
+  }
+  else
+  {
+    status =  HAL_BUSY;
+  }
+  /* Return function status */
+  return status;
+}
+/**
+  * @brief  End computation of a single HMAC signature in interrupt mode, after
+  *         several calls to HAL_HASH_HMAC_Accumulate() API.
+  * @note   Digest is available in pOutBuffer
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                  uint32_t Size, uint8_t *const pOutBuffer)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process*/
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->pHashKeyBuffPtr =  hhash->Init.pKey;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+    /* Set multi buffers accumulation flag */
+    hhash->Accumulation = 0U;
+    /* Enable the specified HASH interrupt*/
+    __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+    status = HASH_WriteData_IT(hhash);
+  }
+  else
+  {
+    status =  HAL_BUSY;
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  HMAC in DMA mode,HASH peripheral processes Key then pInBuffer in DMA mode
+  *         then read the computed digest.
+  * @note   Multi-buffer HMAC processing is possible, consecutive calls to HAL_HASH_HMAC_Start_DMA
+  *         (MDMAT bit must be set) can be used to feed several input buffers
+  *         back-to-back to the Peripheral that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_HMAC_Start_DMA (MDMAT bit must be reset).
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to the input buffer (buffer to be hashed).
+  * @param  Size length of the input buffer in bytes.
+  * @param  pOutBuffer pointer to the computed digest.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *const pOutBuffer)
+{
+  HAL_StatusTypeDef status;
+  uint32_t count;
+  uint32_t blocksize; /* Block size in bytes */
+
+  /* Check the hash handle allocation */
+  if (hhash == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check if peripheral is ready to start process*/
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */
+    hhash->pHashInBuffPtr = pInBuffer;
+    hhash->pHashOutBuffPtr = pOutBuffer;
+    hhash->pHashKeyBuffPtr =  hhash->Init.pKey;
+    hhash->HashInCount =  0U;
+    hhash->Size = Size;
+
+    /* Set the phase */
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */
+      if ((hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA1) ||
+          (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA224) ||
+          (hhash->Init.Algorithm == HASH_ALGOSELECTION_SHA256))
+      {
+        blocksize = BLOCK_64B;
+      }
+      else
+      {
+        blocksize = BLOCK_128B;
+      }
+      if (hhash->Init.KeySize > blocksize)
+      {
+        MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                   HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT);
+      }
+      else
+      {
+
+        MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT,
+                   HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+      }
+
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+
+      /* Configure the number of valid bits in last word of the Key */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+      /* Write Key */
+      HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize);
+
+      /* Start the Key padding then the Digest calculation */
+      SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+      /* Wait for DCIS flag to be set */
+      count = HASH_TIMEOUTVALUE;
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          /* Change state */
+          hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+          hhash->State = HAL_HASH_STATE_READY;
+          __HAL_UNLOCK(hhash);
+          return HAL_ERROR;
+        }
+      } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_BUSY));
+    }
+
+    hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
+    if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U)
+    {
+      /* Configure the number of valid bits in last word of the message */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Size) % 4U));
+    }
+    else
+    {
+      /* Configure the number of valid bits in last word of the message */
+      MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U);
+    }
+  }
+  else if (hhash->State ==  HAL_HASH_STATE_SUSPENDED)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /*only part not yet hashed to compute  */
+    hhash->Size = hhash->HashInCount;
+  }
+
+  else
+  {
+    /* Return busy status */
+    return HAL_BUSY;
+  }
+
+  /* Set the HASH DMA transfer complete callback */
+  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+  /* Set the DMA error callback */
+  hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+  if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
+    {
+      /* Enable the DMA channel */
+      hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
+        = ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : ((hhash->Size)));
+      hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\
+        = (uint32_t)(hhash->pHashInBuffPtr);  /* Set DMA source address */
+      hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\
+        = (uint32_t)&hhash->Instance->DIN; /* Set DMA destination address */
+
+      status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hhash->hdmain, (uint32_t)(hhash->pHashInBuffPtr), (uint32_t)&hhash->Instance->DIN, \
+                              ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : \
+                               ((hhash->Size))));
+  }
+  if (status != HAL_OK)
+  {
+    /* DMA error code field */
+    hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+
+    /* Return error */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+    /*Call registered error callback*/
+    hhash->ErrorCallback(hhash);
+#else
+    /*Call legacy weak error callback*/
+    HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Enable DMA requests */
+    SET_BIT(hhash->Instance->CR, HASH_CR_DMAE);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH IRQ handler management
+  * @brief    HASH IRQ handler.
+  *
+@verbatim
+  ==============================================================================
+                ##### HASH IRQ handler management #####
+  ==============================================================================
+[..]  This section provides HASH IRQ handler and callback functions.
+      (+) HAL_HASH_IRQHandler HASH interrupt request
+      (+) HAL_HASH_InCpltCallback input data transfer complete callback
+      (+) HAL_HASH_DgstCpltCallback digest computation complete callback
+      (+) HAL_HASH_ErrorCallback  HASH error callback
+      (+) HAL_HASH_GetState return the HASH state
+      (+) HAL_HASH_GetError return the HASH error code
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Handle HASH interrupt request.
+  * @param hhash HASH handle.
+  * @note  HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
+  * @retval None
+  */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+  HAL_StatusTypeDef status;
+  uint32_t itsource = hhash->Instance->IMR;
+  uint32_t itflag   = hhash->Instance->SR;
+
+  /* If digest is ready */
+  if ((itflag & HASH_FLAG_DCIS) == HASH_FLAG_DCIS)
+  {
+    /* Read the digest */
+    HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash));
+
+    /* Disable Interrupts */
+    __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+    /* Reset HASH state machine */
+    hhash->Phase = HAL_HASH_PHASE_READY;
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    /* Call digest computation complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+    hhash->DgstCpltCallback(hhash);
+#else
+    HAL_HASH_DgstCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+  }
+  /* If Peripheral ready to accept new data */
+  if ((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS)
+  {
+    if ((itsource & HASH_IT_DINI) == HASH_IT_DINI)
+    {
+      status = HASH_WriteData_IT(hhash);
+      if (status != HAL_OK)
+      {
+        /* Call error callback */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+        hhash->ErrorCallback(hhash);
+#else
+        HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Input data transfer complete call back.
+  * @note   HAL_HASH_InCpltCallback() is called when the complete input message
+  *         has been fed to the Peripheral. This API is invoked only when input data are
+  *         entered under interruption or through DMA.
+  * @note   In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
+  *         HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
+  *         to the Peripheral.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module.
+  * @retval None
+  */
+__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_InCpltCallback() can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Digest computation complete call back.
+  * @note   HAL_HASH_DgstCpltCallback() is used under interruption, is not
+  *         relevant with DMA.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module.
+  * @retval None
+  */
+__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_DgstCpltCallback() can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  HASH error callback.
+  * @note   Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
+  *         to retrieve the error type.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains
+  *         the configuration information for HASH module.
+  * @retval None
+  */
+__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_ErrorCallback() can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Return the HASH handle state.
+  * @note   The API yields the current state of the handle (BUSY, READY,...).
+  * @param  hhash HASH handle.
+  * @retval HAL HASH state
+  */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash)
+{
+  return hhash->State;
+}
+
+/**
+  * @brief  Return the HASH handle error code.
+  * @param  hhash pointer to a HASH_HandleTypeDef structure.
+  * @retval HASH Error Code
+  */
+uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash)
+{
+  /* Return HASH Error Code */
+  return hhash->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup HASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief DMA HASH Input Data transfer completion callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  uint32_t count;
+
+  if (READ_BIT(hhash->Instance->CR, HASH_CR_MODE) == 0U)
+  {
+    if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U)
+    {
+      /* Disable the DMA transfer */
+      CLEAR_BIT(hhash->Instance->CR, HASH_CR_DMAE);
+
+
+      /* Wait for DCIS flag to be set */
+      count = HASH_TIMEOUTVALUE;
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          /* Change state */
+          hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+          hhash->State = HAL_HASH_STATE_READY;
+          __HAL_UNLOCK(hhash);
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+          hhash->ErrorCallback(hhash);
+#else
+          HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+        }
+      } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS));
+      /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+      hhash->InCpltCallback(hhash);
+#else
+      HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+      /* Read the message digest */
+      HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash));
+
+      /* Change the HASH state to ready */
+      hhash->State = HAL_HASH_STATE_READY;
+
+      /* Reset HASH state machine */
+      hhash->Phase = HAL_HASH_PHASE_READY;
+
+      /* Process UnLock */
+      __HAL_UNLOCK(hhash);
+
+      /* Call digest complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+      hhash->DgstCpltCallback(hhash);
+#else
+      HAL_HASH_DgstCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      __HAL_UNLOCK(hhash);
+    }
+  }
+  else /*HMAC DMA*/
+  {
+    if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+    {
+      if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U)
+      {
+        /* Set the phase */
+        hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
+        /* Configure the number of valid bits in last word of the Key */
+        MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+        /* Write Key */
+        HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize);
+
+        /* Start the Key padding then the Digest calculation */
+        SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+        /* Wait for DCIS flag to be set */
+        count = HASH_TIMEOUTVALUE;
+        do
+        {
+          count--;
+          if (count == 0U)
+          {
+            /* Disable the DMA transfer */
+            CLEAR_BIT(hhash->Instance->CR, HASH_CR_DMAE);
+
+            /* Change state */
+            hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+            hhash->State = HAL_HASH_STATE_READY;
+            __HAL_UNLOCK(hhash);
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+            hhash->ErrorCallback(hhash);
+#else
+            HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+          }
+        } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS));
+
+        /* Read the message digest */
+        HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash));
+
+        /* Change the HASH state to ready */
+        hhash->State = HAL_HASH_STATE_READY;
+
+        /* Reset HASH state machine */
+        hhash->Phase = HAL_HASH_PHASE_READY;
+
+        /* Process UnLock */
+        __HAL_UNLOCK(hhash);
+
+        /* Call digest complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+        hhash->DgstCpltCallback(hhash);
+#else
+        HAL_HASH_DgstCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+      }
+      else
+      {
+        hhash->State = HAL_HASH_STATE_READY;
+        __HAL_UNLOCK(hhash);
+        hhash->Accumulation = 1;
+      }
+    }
+  }
+}
+
+/**
+  * @brief DMA HASH communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+  /* Set HASH state to ready to prevent any blocking issue in user code
+  present in HAL_HASH_ErrorCallback() */
+  hhash->State = HAL_HASH_STATE_READY;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+  hhash->ErrorCallback(hhash);
+#else
+  HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Feed the input buffer to the HASH peripheral in polling.
+  * @param  hhash HASH handle.
+  * @param  pInBuffer pointer to input buffer.
+  * @param  Size the size of input buffer in bytes.
+  * @retval HAL status
+  */
+static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t buffercounter;
+  __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+  uint8_t tmp1;
+  uint8_t tmp2;
+  uint8_t tmp3;
+
+  for (buffercounter = 0U; buffercounter < (Size / 4U) ; buffercounter++)
+  {
+    /* Write input data 4 bytes at a time */
+    hhash->Instance->DIN = *(uint32_t *)inputaddr;
+    inputaddr += 4U;
+    hhash->HashInCount += 4U;
+  }
+
+  if ((Size % 4U) != 0U)
+  {
+    if (hhash->Init.DataType == HASH_HALFWORD_SWAP)
+    {
+      /* Write remaining input data */
+      if ((Size % 4U) <= 2U)
+      {
+        hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr;
+      }
+      if ((Size % 4U) == 3U)
+      {
+        hhash->Instance->DIN = *(uint32_t *)inputaddr;
+      }
+    }
+    else if ((hhash->Init.DataType == HASH_BYTE_SWAP)
+             || (hhash->Init.DataType == HASH_BIT_SWAP))  /* byte swap or bit swap or */
+    {
+      /* Write remaining input data */
+      if ((Size % 4U) == 1U)
+      {
+        hhash->Instance->DIN = (uint32_t) * (uint8_t *)inputaddr;
+      }
+      if ((Size % 4U) == 2U)
+      {
+        hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr;
+      }
+      if ((Size % 4U) == 3U)
+      {
+        tmp1 = *(uint8_t *)inputaddr;
+        tmp2 = *(((uint8_t *)inputaddr) + 1U);
+        tmp3 = *(((uint8_t *)inputaddr) + 2U);
+        hhash->Instance->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U);
+      }
+    }
+    else
+    {
+      hhash->Instance->DIN = *(uint32_t *)inputaddr;
+    }
+    hhash->HashInCount += 4U;
+  }
+}
+
+/**
+  * @brief  Feed the input buffer to the HASH peripheral in interruption mode.
+  * @param  hhash HASH handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash)
+{
+  uint32_t buffercounter;
+  uint32_t count;
+  __IO uint32_t keyaddr = (uint32_t)(hhash->pHashKeyBuffPtr);
+  __IO uint32_t inputaddr = (uint32_t)(hhash->pHashInBuffPtr);
+  uint32_t nbbytePartialHash  = (((hhash->Instance->SR) >> 16U) * 4U); /* Nb byte  to enter in HASH fifo to trig
+                                                                      a partial HASH computation*/
+
+  if (hhash->State == HAL_HASH_STATE_BUSY)
+  {
+    if ((hhash->Instance->CR & HASH_CR_MODE) == 0U)
+    {
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+      /* If suspension flag has been raised, suspend processing */
+      if (hhash->SuspendRequest == HAL_HASH_SUSPEND)
+      {
+        /* reset SuspendRequest */
+        hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+        /* Disable Computation Complete Flag and Errors Interrupts */
+        __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+        /* Change the HASH state */
+        hhash->State = HAL_HASH_STATE_SUSPENDED;
+        __HAL_UNLOCK(hhash);
+      }
+      else
+      {
+#endif /* USE_HAL_HASH_SUSPEND_RESUME */
+
+        if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Size))
+        {
+          for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U)
+          {
+            /* Write input data 4 bytes at a time */
+            hhash->Instance->DIN = *(uint32_t *)inputaddr;
+            inputaddr += 4U;
+            hhash->HashInCount += 4U;
+            hhash->pHashInBuffPtr += 4U;
+          }
+          /* Wait for HASH_IT_DINI flag to be set */
+          count = HASH_TIMEOUTVALUE;
+          do
+          {
+            count--;
+            if (count == 0U)
+            {
+              /* Disable Interrupts */
+              __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+              /* Change state */
+              hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+              hhash->State = HAL_HASH_STATE_READY;
+              __HAL_UNLOCK(hhash);
+              return HAL_ERROR;
+            }
+          } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS));
+        }
+        else
+        {
+          while ((hhash->HashInCount) < hhash->Size)
+          {
+            /* Write input data 4 bytes at a time */
+            hhash->Instance->DIN = *(uint32_t *)inputaddr;
+            inputaddr += 4U;
+            hhash->HashInCount += 4U;
+            hhash->pHashInBuffPtr += 4U;
+          }
+          /* Call Input transfer complete callback */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+          /*Call registered Input complete callback*/
+          hhash->InCpltCallback(hhash);
+#else
+          /*Call legacy weak Input complete callback*/
+          HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+          if (hhash->Accumulation == 0U)
+          {
+            if (__HAL_HASH_GET_IT_SOURCE(hhash, HASH_IT_DINI))
+            {
+              /* Start the message padding then the Digest calculation */
+              SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+              /* Wait for HASH_FLAG_DCIS flag to be set */
+              count = HASH_TIMEOUTVALUE;
+              do
+              {
+                count--;
+                if (count == 0U)
+                {
+                  /* Disable Interrupts */
+                  __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+                  /* Change state */
+                  hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+                  hhash->State = HAL_HASH_STATE_READY;
+                  __HAL_UNLOCK(hhash);
+                  return HAL_ERROR;
+                }
+              } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS));
+            }
+          }
+          else
+          {
+            /* Reset multi buffers accumulation flag */
+            hhash->Accumulation = 0U;
+            /* Disable Interrupts */
+            __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI);
+          }
+        }
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+      }
+#endif /* USE_HAL_HASH_SUSPEND_RESUME */
+    }
+    else /*HMAC */
+    {
+      if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) /* loading input*/
+      {
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+        /* If suspension flag has been raised, suspend processing */
+        if (hhash->SuspendRequest == HAL_HASH_SUSPEND)
+        {
+          /* reset SuspendRequest */
+          hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+          /* Disable Computation Complete Flag and Errors Interrupts */
+          __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+          /* Change the HASH state */
+          hhash->State = HAL_HASH_STATE_SUSPENDED;
+          __HAL_UNLOCK(hhash);
+        }
+        else
+        {
+#endif /* USE_HAL_HASH_SUSPEND_RESUME */
+          if (hhash->Accumulation == 1U)
+          {
+            /* Configure the number of valid bits in last word of the message */
+            MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U);
+          }
+          else
+          {
+            /* Configure the number of valid bits in last word of the message */
+            MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (hhash->Size % 4U));
+          }
+          if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Size))
+          {
+            for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U)
+            {
+              /* Write input data 4 bytes at a time */
+              hhash->Instance->DIN = *(uint32_t *)inputaddr;
+              inputaddr += 4U;
+              hhash->HashInCount += 4U;
+              hhash->pHashInBuffPtr += 4U;
+            }
+            /* Wait for HASH_IT_DINI flag to be set */
+            count = HASH_TIMEOUTVALUE;
+            do
+            {
+              count--;
+              if (count == 0U)
+              {
+                /* Disable Interrupts */
+                __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+                /* Change state */
+                hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+                hhash->State = HAL_HASH_STATE_READY;
+                __HAL_UNLOCK(hhash);
+                return HAL_ERROR;
+              }
+            } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS));
+          }
+          else
+          {
+            while ((hhash->HashInCount) < hhash->Size)
+            {
+              /* Write input data 4 bytes at a time */
+              hhash->Instance->DIN = *(uint32_t *)inputaddr;
+              inputaddr += 4U;
+              hhash->HashInCount += 4U;
+              hhash->pHashInBuffPtr += 4U;
+            }
+            /* Call Input transfer complete callback */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+            /*Call registered Input complete callback*/
+            hhash->InCpltCallback(hhash);
+#else
+            /*Call legacy weak Input complete callback*/
+            HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+            if (hhash->Accumulation == 0U)
+            {
+              if (__HAL_HASH_GET_IT_SOURCE(hhash, HASH_IT_DINI))
+              {
+                /* Start the message padding then the Digest calculation */
+                SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+                /* Wait for HASH_FLAG_BUSY flag to be set */
+                count = HASH_TIMEOUTVALUE;
+                do
+                {
+                  count--;
+                  if (count == 0U)
+                  {
+                    /* Disable Interrupts */
+                    __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+                    /* Change state */
+                    hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+                    hhash->State = HAL_HASH_STATE_READY;
+                    __HAL_UNLOCK(hhash);
+                    return HAL_ERROR;
+                  }
+                } while (HAL_IS_BIT_SET(hhash->Instance->SR, HASH_FLAG_BUSY));
+
+                hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
+                hhash->HashInCount = 0U;
+                hhash->pHashKeyBuffPtr = hhash->Init.pKey;
+              }
+            }
+
+            else
+            {
+              /* Disable Interrupts */
+              __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+              hhash->State = HAL_HASH_STATE_READY;
+              __HAL_UNLOCK(hhash);
+              return HAL_OK;
+            }
+          }
+#if (USE_HAL_HASH_SUSPEND_RESUME == 1U)
+        }
+#endif /* USE_HAL_HASH_SUSPEND_RESUME */
+      }
+
+      else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)/* loading Key*/
+      {
+
+        /* Configure the number of valid bits in last word of the Key */
+        MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U));
+
+        if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Init.KeySize))
+        {
+          for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U)
+          {
+            /* Write input data 4 bytes at a time */
+            hhash->Instance->DIN = *(uint32_t *)keyaddr;
+            keyaddr += 4U;
+            hhash->HashInCount += 4U;
+            hhash->pHashKeyBuffPtr += 4U;
+          }
+          /* Wait for HASH_IT_DINI flag to be set */
+          count = HASH_TIMEOUTVALUE;
+          do
+          {
+            count--;
+            if (count == 0U)
+            {
+              /* Disable Interrupts */
+              __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+              /* Change state */
+              hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+              hhash->State = HAL_HASH_STATE_READY;
+              __HAL_UNLOCK(hhash);
+              return HAL_ERROR;
+            }
+          } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS));
+        }
+        else
+        {
+          while ((hhash->HashInCount) < (hhash->Init.KeySize))
+          {
+            /* Write input data 4 bytes at a time */
+            hhash->Instance->DIN = *(uint32_t *)keyaddr;
+            keyaddr += 4U;
+            hhash->HashInCount += 4U;
+          }
+          /* Start the message padding then the Digest calculation */
+          SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+          /* Wait for HASH_FLAG_DCIS flag to be set */
+          count = HASH_TIMEOUTVALUE;
+          do
+          {
+            count--;
+            if (count == 0U)
+            {
+              /* Disable Interrupts */
+              __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+              /* Change state */
+              hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+              hhash->State = HAL_HASH_STATE_READY;
+              __HAL_UNLOCK(hhash);
+              return HAL_ERROR;
+            }
+          } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS));
+        }
+      }
+      else  /*first step , loading key*/
+      {
+
+        hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+
+        if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Init.KeySize))
+        {
+          for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U)
+          {
+            /* Write input data 4 bytes at a time */
+            hhash->Instance->DIN = *(uint32_t *)keyaddr;
+            keyaddr += 4U;
+            hhash->HashInCount += 4U;
+            hhash->pHashKeyBuffPtr += 4U;
+          }
+          /* Wait for HASH_IT_DINI flag to be set */
+          count = HASH_TIMEOUTVALUE;
+          do
+          {
+            count--;
+            if (count == 0U)
+            {
+              /* Disable Interrupts */
+              __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+              /* Change state */
+              hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+              hhash->State = HAL_HASH_STATE_READY;
+              __HAL_UNLOCK(hhash);
+              return HAL_ERROR;
+            }
+          } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS));
+        }
+        else
+        {
+          while ((hhash->HashInCount) < (hhash->Init.KeySize))
+          {
+            /* Write input data 4 bytes at a time */
+            hhash->Instance->DIN = *(uint32_t *)keyaddr;
+            keyaddr += 4U;
+            hhash->HashInCount += 4U;
+            hhash->pHashKeyBuffPtr += 4U;
+          }
+          /* Start the message padding then the Digest calculation */
+          SET_BIT(hhash->Instance->STR, HASH_STR_DCAL);
+
+          /* Wait for HASH_FLAG_BUSY flag to be set */
+          count = HASH_TIMEOUTVALUE;
+          do
+          {
+            count--;
+            if (count == 0U)
+            {
+              /* Disable Interrupts */
+              __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
+
+              /* Change state */
+              hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+              hhash->State = HAL_HASH_STATE_READY;
+              __HAL_UNLOCK(hhash);
+              return HAL_ERROR;
+            }
+          } while (HAL_IS_BIT_SET(hhash->Instance->SR, HASH_FLAG_BUSY));
+          /*change Phase to step 2*/
+          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
+          hhash->HashInCount = 0U;
+        }
+      }
+    }
+  }
+  else if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    /* Busy error code field */
+    hhash->ErrorCode |= HAL_HASH_ERROR_BUSY;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+    /*Call registered error callback*/
+    hhash->ErrorCallback(hhash);
+#else
+    /*Call legacy weak error callback*/
+    HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Retrieve the message digest.
+  * @param hhash HASH handle
+  * @param  pMsgDigest pointer to the computed digest.
+  * @param  Size message digest size in bytes.
+  * @retval None
+  */
+static void HASH_GetDigest(const HASH_HandleTypeDef *hhash, const uint8_t *pMsgDigest, uint8_t Size)
+{
+  uint32_t msgdigest = (uint32_t)pMsgDigest;
+
+  switch (Size)
+  {
+    case 20:  /* SHA1 */
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]);
+      break;
+
+    case 28:  /* SHA224 */
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+
+      break;
+    case 32:   /* SHA256 */
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+      break;
+    case 48:   /* SHA384 */
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[8]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[9]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[10]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[11]);
+      break;
+
+    case 64:   /* SHA 512 */
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[8]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[9]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[10]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[11]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[12]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[13]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[14]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[15]);
+
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Handle HASH processing Timeout.
+  * @param  hhash HASH handle.
+  * @param  Flag specifies the HASH flag to check.
+  * @param  Status the Flag status (SET or RESET).
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  while (__HAL_HASH_GET_FLAG(hhash, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Set State to Ready to be able to restart later on */
+        hhash->State  = HAL_HASH_STATE_READY;
+        hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#endif /*  HASH*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_hcd.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_hcd.c
new file mode 100644
index 000000000..b0c17e8e6
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_hcd.c
@@ -0,0 +1,1953 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_hcd.c
+  * @author  MCD Application Team
+  * @brief   HCD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#)Declare a HCD_HandleTypeDef handle structure, for example:
+       HCD_HandleTypeDef  hhcd;
+
+    (#)Fill parameters of Init structure in HCD handle
+
+    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
+
+    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
+        (##) Enable the HCD/USB Low Level interface clock using the following macros
+             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
+
+        (##) Initialize the related GPIO clocks
+        (##) Configure HCD pin-out
+        (##) Configure HCD NVIC interrupt
+
+    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
+        (##) hhcd.pData = phost;
+
+    (#)Enable HCD transmission and reception:
+        (##) HAL_HCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+
+/** @defgroup HCD HCD
+  * @brief HCD HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+  * @{
+  */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HCD_Exported_Functions HCD Exported Functions
+  * @{
+  */
+
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
+{
+  /* Check the HCD handle allocation */
+  if (hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+
+  if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+    hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+    hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+    hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+    hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+    hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
+
+    if (hhcd->MspInitCallback == NULL)
+    {
+      hhcd->MspInitCallback = HAL_HCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hhcd->MspInitCallback(hhcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_HCD_MspInit(hhcd);
+#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
+  }
+
+  hhcd->State = HAL_HCD_STATE_BUSY;
+
+  /* Disable the Interrupts */
+  __HAL_HCD_DISABLE(hhcd);
+
+  /* Init the Core (common init.) */
+  if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+  {
+    hhcd->State = HAL_HCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  /* Force Host Mode */
+  if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
+  {
+    hhcd->State = HAL_HCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  /* Init Host */
+  if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+  {
+    hhcd->State = HAL_HCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  hhcd->State = HAL_HCD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize a host channel.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum Endpoint number.
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed Current device speed.
+  *          This parameter can be one of these values:
+  *            HCD_DEVICE_SPEED_HIGH: High speed mode,
+  *            HCD_DEVICE_SPEED_FULL: Full speed mode,
+  *            HCD_DEVICE_SPEED_LOW: Low speed mode
+  * @param  ep_type Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type,
+  *            EP_TYPE_ISOC: Isochronous type,
+  *            EP_TYPE_BULK: Bulk type,
+  *            EP_TYPE_INTR: Interrupt type
+  * @param  mps Max Packet Size.
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum,
+                                  uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
+{
+  HAL_StatusTypeDef status;
+  uint32_t HostCoreSpeed;
+  uint32_t HCcharMps = mps;
+
+  __HAL_LOCK(hhcd);
+  hhcd->hc[ch_num].do_ping = 0U;
+  hhcd->hc[ch_num].dev_addr = dev_address;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].ep_type = ep_type;
+  hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
+
+  (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num);
+
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    hhcd->hc[ch_num].ep_is_in = 1U;
+  }
+  else
+  {
+    hhcd->hc[ch_num].ep_is_in = 0U;
+  }
+
+  HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
+
+  if (ep_type == EP_TYPE_ISOC)
+  {
+    /* FS device plugged to HS HUB */
+    if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
+    {
+      if (HCcharMps > ISO_SPLT_MPS)
+      {
+        /* ISO Max Packet Size for Split mode */
+        HCcharMps = ISO_SPLT_MPS;
+      }
+    }
+  }
+
+  hhcd->hc[ch_num].speed = speed;
+  hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps;
+
+  status =  USB_HC_Init(hhcd->Instance, ch_num, epnum,
+                        dev_address, speed, ep_type, (uint16_t)HCcharMps);
+
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+
+/**
+  * @brief  Halt a host channel.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  __HAL_LOCK(hhcd);
+  (void)USB_HC_Halt(hhcd->Instance, ch_num);
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Check the HCD handle allocation */
+  if (hhcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hhcd->State = HAL_HCD_STATE_BUSY;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+  if (hhcd->MspDeInitCallback == NULL)
+  {
+    hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hhcd->MspDeInitCallback(hhcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_HCD_MspDeInit(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+  __HAL_HCD_DISABLE(hhcd);
+
+  hhcd->State = HAL_HCD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the HCD MSP.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the HCD MSP.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   HCD IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
+    Transfer
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Submit a new URB for processing.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  direction Channel number.
+  *          This parameter can be one of these values:
+  *           0 : Output / 1 : Input
+  * @param  ep_type Endpoint Type.
+  *          This parameter can be one of these values:
+  *            EP_TYPE_CTRL: Control type/
+  *            EP_TYPE_ISOC: Isochronous type/
+  *            EP_TYPE_BULK: Bulk type/
+  *            EP_TYPE_INTR: Interrupt type/
+  * @param  token Endpoint Type.
+  *          This parameter can be one of these values:
+  *            0: HC_PID_SETUP / 1: HC_PID_DATA1
+  * @param  pbuff pointer to URB data
+  * @param  length Length of URB data
+  * @param  do_ping activate do ping protocol (for high speed only).
+  *          This parameter can be one of these values:
+  *           0 : do ping inactive / 1 : do ping active
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                           uint8_t ch_num,
+                                           uint8_t direction,
+                                           uint8_t ep_type,
+                                           uint8_t token,
+                                           uint8_t *pbuff,
+                                           uint16_t length,
+                                           uint8_t do_ping)
+{
+  hhcd->hc[ch_num].ep_is_in = direction;
+  hhcd->hc[ch_num].ep_type  = ep_type;
+
+  if (token == 0U)
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+    hhcd->hc[ch_num].do_ping = do_ping;
+  }
+  else
+  {
+    hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+  }
+
+  /* Manage Data Toggle */
+  switch (ep_type)
+  {
+    case EP_TYPE_CTRL:
+      if (token == 1U) /* send data */
+      {
+        if (direction == 0U)
+        {
+          if (length == 0U)
+          {
+            /* For Status OUT stage, Length == 0U, Status Out PID = 1 */
+            hhcd->hc[ch_num].toggle_out = 1U;
+          }
+
+          /* Set the Data Toggle bit as per the Flag */
+          if (hhcd->hc[ch_num].toggle_out == 0U)
+          {
+            /* Put the PID 0 */
+            hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+          }
+          else
+          {
+            /* Put the PID 1 */
+            hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+          }
+        }
+        else
+        {
+          if (hhcd->hc[ch_num].do_ssplit == 1U)
+          {
+            if (hhcd->hc[ch_num].toggle_in == 0U)
+            {
+              hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+            }
+            else
+            {
+              hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+            }
+          }
+        }
+      }
+      break;
+
+    case EP_TYPE_BULK:
+      if (direction == 0U)
+      {
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+      else
+      {
+        if (hhcd->hc[ch_num].toggle_in == 0U)
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+
+      break;
+    case EP_TYPE_INTR:
+      if (direction == 0U)
+      {
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+      else
+      {
+        if (hhcd->hc[ch_num].toggle_in == 0U)
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
+      }
+      break;
+
+    case EP_TYPE_ISOC:
+      hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      break;
+
+    default:
+      break;
+  }
+
+  hhcd->hc[ch_num].xfer_buff = pbuff;
+  hhcd->hc[ch_num].xfer_len  = length;
+  hhcd->hc[ch_num].urb_state = URB_IDLE;
+  hhcd->hc[ch_num].xfer_count = 0U;
+  hhcd->hc[ch_num].ch_num = ch_num;
+  hhcd->hc[ch_num].state = HC_IDLE;
+
+  return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
+}
+
+/**
+  * @brief  Handle HCD interrupt request.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+  uint32_t interrupt;
+
+  /* Ensure that we are in device mode */
+  if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
+  {
+    /* Avoid spurious interrupt */
+    if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+    {
+      return;
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+    {
+      /* Incorrect mode, acknowledge the interrupt */
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
+    }
+
+    /* Handle Host Disconnect Interrupts */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+    {
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+
+      if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
+      {
+        /* Flush USB Fifo */
+        (void)USB_FlushTxFifo(USBx, 0x10U);
+        (void)USB_FlushRxFifo(USBx);
+
+
+        /* Handle Host Port Disconnect Interrupt */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+        hhcd->DisconnectCallback(hhcd);
+#else
+        HAL_HCD_Disconnect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+      }
+    }
+
+    /* Handle Host Port Interrupts */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+    {
+      HCD_Port_IRQHandler(hhcd);
+    }
+
+    /* Handle Host SOF Interrupt */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+    {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->SOFCallback(hhcd);
+#else
+      HAL_HCD_SOF_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
+    }
+
+    /* Handle Host channel Interrupt */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+    {
+      interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
+      for (i = 0U; i < hhcd->Init.Host_channels; i++)
+      {
+        if ((interrupt & (1UL << (i & 0xFU))) != 0U)
+        {
+          if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
+          {
+            HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
+          }
+          else
+          {
+            HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
+          }
+        }
+      }
+      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
+    }
+
+    /* Handle Rx Queue Level Interrupts */
+    if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
+    {
+      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+      HCD_RXQLVL_IRQHandler(hhcd);
+
+      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+  }
+}
+
+
+/**
+  * @brief  SOF callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_SOF_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Connection Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Connect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Disconnection Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Port Enabled  Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Port Disabled  Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Notify URB state change callback.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  urb_state:
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/
+  *            URB_ERROR/
+  *            URB_STALL/
+  * @retval None
+  */
+__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  UNUSED(chnum);
+  UNUSED(urb_state);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB HCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hhcd USB HCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+  *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+  *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+  *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
+  *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
+  *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+                                           HAL_HCD_CallbackIDTypeDef CallbackID,
+                                           pHCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_SOF_CB_ID :
+        hhcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_HCD_CONNECT_CB_ID :
+        hhcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_HCD_DISCONNECT_CB_ID :
+        hhcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_HCD_PORT_ENABLED_CB_ID :
+        hhcd->PortEnabledCallback = pCallback;
+        break;
+
+      case HAL_HCD_PORT_DISABLED_CB_ID :
+        hhcd->PortDisabledCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB HCD Callback
+  *         USB HCD callback is redirected to the weak predefined callback
+  * @param  hhcd USB HCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+  *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+  *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+  *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
+  *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
+  *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_SOF_CB_ID :
+        hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+        break;
+
+      case HAL_HCD_CONNECT_CB_ID :
+        hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+        break;
+
+      case HAL_HCD_DISCONNECT_CB_ID :
+        hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+        break;
+
+      case HAL_HCD_PORT_ENABLED_CB_ID :
+        hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+        break;
+
+      case HAL_HCD_PORT_DISABLED_CB_ID :
+        hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+        break;
+
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = HAL_HCD_MspInit;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = HAL_HCD_MspInit;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB HCD Host Channel Notify URB Change Callback
+  *         To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+  * @param  hhcd HCD handle
+  * @param  pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+                                                             pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    hhcd->HC_NotifyURBChangeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB HCD Host Channel Notify URB Change Callback
+  *         USB HCD Host Channel Notify URB Change Callback is redirected
+  *         to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   Management functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the HCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
+{
+  __HAL_LOCK(hhcd);
+  /* Enable port power */
+  (void)USB_DriveVbus(hhcd->Instance, 1U);
+
+  /* Enable global interrupt */
+  __HAL_HCD_ENABLE(hhcd);
+  __HAL_UNLOCK(hhcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the host driver.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
+{
+  __HAL_LOCK(hhcd);
+  (void)USB_StopHost(hhcd->Instance);
+  __HAL_UNLOCK(hhcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the host port.
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_ResetPort(hhcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the HCD handle state.
+  * @param  hhcd HCD handle
+  * @retval HAL state
+  */
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd)
+{
+  return hhcd->State;
+}
+
+/**
+  * @brief  Return  URB state for a channel.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval URB state.
+  *          This parameter can be one of these values:
+  *            URB_IDLE/
+  *            URB_DONE/
+  *            URB_NOTREADY/
+  *            URB_NYET/
+  *            URB_ERROR/
+  *            URB_STALL
+  */
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].urb_state;
+}
+
+
+/**
+  * @brief  Return the last host transfer size.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval last transfer size in byte
+  */
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].xfer_count;
+}
+
+/**
+  * @brief  Return the Host Channel state.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval Host channel state
+  *          This parameter can be one of these values:
+  *            HC_IDLE/
+  *            HC_XFRC/
+  *            HC_HALTED/
+  *            HC_NYET/
+  *            HC_NAK/
+  *            HC_STALL/
+  *            HC_XACTERR/
+  *            HC_BBLERR/
+  *            HC_DATATGLERR
+  */
+HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
+{
+  return hhcd->hc[chnum].state;
+}
+
+/**
+  * @brief  Return the current Host frame number.
+  * @param  hhcd HCD handle
+  * @retval Current Host frame number
+  */
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetCurrentFrame(hhcd->Instance));
+}
+
+/**
+  * @brief  Return the Host enumeration speed.
+  * @param  hhcd HCD handle
+  * @retval Enumeration speed
+  */
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
+{
+  return (USB_GetHostSpeed(hhcd->Instance));
+}
+
+/**
+  * @brief  Set host channel Hub information.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  addr Hub address
+  * @param  PortNbr Hub port number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                        uint8_t addr, uint8_t PortNbr)
+{
+  uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
+
+  /* LS/FS device plugged to HS HUB */
+  if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
+  {
+    hhcd->hc[ch_num].do_ssplit = 1U;
+
+    if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U))
+    {
+      hhcd->hc[ch_num].toggle_in = 1U;
+    }
+  }
+
+  hhcd->hc[ch_num].hub_addr = addr;
+  hhcd->hc[ch_num].hub_port_nbr = PortNbr;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear host channel hub information.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+  hhcd->hc[ch_num].do_ssplit = 0U;
+  hhcd->hc[ch_num].do_csplit = 0U;
+  hhcd->hc[ch_num].hub_addr = 0U;
+  hhcd->hc[ch_num].hub_port_nbr = 0U;
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup HCD_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Handle Host Channel IN interrupt requests.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    hhcd->hc[chnum].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR);
+    hhcd->hc[chnum].state = HC_BBLERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+    hhcd->hc[chnum].state = HC_STALL;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+    hhcd->hc[chnum].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else
+  {
+    /* ... */
+  }
+
+  if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
+  {
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
+  {
+    /* Clear any pending ACK IT */
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+
+    if (hhcd->hc[chnum].do_csplit == 1U)
+    {
+      hhcd->hc[chnum].do_csplit = 0U;
+      __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+    }
+
+    if (hhcd->Init.dma_enable != 0U)
+    {
+      hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+    }
+
+    hhcd->hc[chnum].state = HC_XFRC;
+    hhcd->hc[chnum].ErrCnt = 0U;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+
+    if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+        (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    {
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+    }
+    else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
+             (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC))
+    {
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+      hhcd->hc[chnum].urb_state = URB_DONE;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#else
+      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* ... */
+    }
+
+    if (hhcd->Init.dma_enable == 1U)
+    {
+      if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U)
+      {
+        hhcd->hc[chnum].toggle_in ^= 1U;
+      }
+    }
+    else
+    {
+      hhcd->hc[chnum].toggle_in ^= 1U;
+    }
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+
+    if (hhcd->hc[chnum].do_ssplit == 1U)
+    {
+      hhcd->hc[chnum].do_csplit = 1U;
+      hhcd->hc[chnum].state = HC_ACK;
+
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+    }
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+
+    if (hhcd->hc[chnum].state == HC_XFRC)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_DONE;
+    }
+    else if (hhcd->hc[chnum].state == HC_STALL)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_STALL;
+    }
+    else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
+             (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].ErrCnt++;
+      if (hhcd->hc[chnum].ErrCnt > 2U)
+      {
+        hhcd->hc[chnum].ErrCnt = 0U;
+
+        if (hhcd->hc[chnum].do_ssplit == 1U)
+        {
+          hhcd->hc[chnum].do_csplit = 0U;
+          hhcd->hc[chnum].ep_ss_schedule = 0U;
+          __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+        }
+
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+        if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+            (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+        {
+          /* re-activate the channel */
+          tmpreg = USBx_HC(chnum)->HCCHAR;
+          tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+          tmpreg |= USB_OTG_HCCHAR_CHENA;
+          USBx_HC(chnum)->HCCHAR = tmpreg;
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NYET)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+        {
+          hhcd->hc[chnum].NyetErrCnt++;
+          if (hhcd->hc[chnum].NyetErrCnt > 2U)
+          {
+            hhcd->hc[chnum].NyetErrCnt = 0U;
+            hhcd->hc[chnum].do_csplit = 0U;
+
+            if (hhcd->hc[chnum].ErrCnt < 3U)
+            {
+              hhcd->hc[chnum].ep_ss_schedule = 1U;
+            }
+            __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+            hhcd->hc[chnum].urb_state = URB_ERROR;
+          }
+          else
+          {
+            hhcd->hc[chnum].urb_state = URB_NOTREADY;
+          }
+        }
+        else
+        {
+          hhcd->hc[chnum].urb_state = URB_NOTREADY;
+        }
+
+        if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+            (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+        {
+          /* re-activate the channel */
+          tmpreg = USBx_HC(chnum)->HCCHAR;
+          tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+          tmpreg |= USB_OTG_HCCHAR_CHENA;
+          USBx_HC(chnum)->HCCHAR = tmpreg;
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_ACK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+        /* Set Complete split and re-activate the channel */
+        USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+        USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
+        USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK;
+
+        if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+            (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+        {
+          /* re-activate the channel */
+          tmpreg = USBx_HC(chnum)->HCCHAR;
+          tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+          tmpreg |= USB_OTG_HCCHAR_CHENA;
+          USBx_HC(chnum)->HCCHAR = tmpreg;
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NAK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+      if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+          (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+      {
+        /* re-activate the channel */
+        tmpreg = USBx_HC(chnum)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(chnum)->HCCHAR = tmpreg;
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_BBLERR)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].ErrCnt++;
+      hhcd->hc[chnum].urb_state = URB_ERROR;
+    }
+    else
+    {
+      if (hhcd->hc[chnum].state == HC_HALTED)
+      {
+        return;
+      }
+    }
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#else
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+    hhcd->hc[chnum].state = HC_NYET;
+
+    if (hhcd->hc[chnum].do_ssplit == 0U)
+    {
+      hhcd->hc[chnum].ErrCnt = 0U;
+    }
+
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
+  {
+    if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+    {
+      hhcd->hc[chnum].ErrCnt = 0U;
+      hhcd->hc[chnum].state = HC_NAK;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+    }
+    else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+             (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    {
+      hhcd->hc[chnum].ErrCnt = 0U;
+
+      if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U))
+      {
+        hhcd->hc[chnum].state = HC_NAK;
+        (void)USB_HC_Halt(hhcd->Instance, chnum);
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+
+    if (hhcd->hc[chnum].do_csplit == 1U)
+    {
+      hhcd->hc[chnum].do_csplit = 0U;
+      __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+      __HAL_HCD_UNMASK_ACK_HC_INT(chnum);
+    }
+
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+  }
+  else
+  {
+    /* ... */
+  }
+}
+
+/**
+  * @brief  Handle Host Channel OUT interrupt requests.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval none
+  */
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+{
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+  uint32_t num_packets;
+
+  if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    hhcd->hc[chnum].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+
+    if (hhcd->hc[chnum].do_ping == 1U)
+    {
+      hhcd->hc[chnum].do_ping = 0U;
+      hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      hhcd->hc[chnum].state = HC_ACK;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+    }
+
+    if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U))
+    {
+      if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
+      {
+        hhcd->hc[chnum].do_csplit = 1U;
+      }
+
+      hhcd->hc[chnum].state = HC_ACK;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+
+      /* reset error_count */
+      hhcd->hc[chnum].ErrCnt = 0U;
+    }
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
+  {
+    hhcd->hc[chnum].ErrCnt = 0U;
+
+    /* transaction completed with NYET state, update do ping state */
+    if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
+    {
+      hhcd->hc[chnum].do_ping = 1U;
+      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+    }
+
+    if (hhcd->hc[chnum].do_csplit != 0U)
+    {
+      hhcd->hc[chnum].do_csplit = 0U;
+      __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+    }
+
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+    hhcd->hc[chnum].state = HC_XFRC;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
+  {
+    hhcd->hc[chnum].state = HC_NYET;
+
+    if (hhcd->hc[chnum].do_ssplit == 0U)
+    {
+      hhcd->hc[chnum].do_ping = 1U;
+    }
+
+    hhcd->hc[chnum].ErrCnt = 0U;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+    hhcd->hc[chnum].state = HC_STALL;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
+  {
+    hhcd->hc[chnum].ErrCnt = 0U;
+    hhcd->hc[chnum].state = HC_NAK;
+
+    if (hhcd->hc[chnum].do_ping == 0U)
+    {
+      if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH)
+      {
+        hhcd->hc[chnum].do_ping = 1U;
+      }
+    }
+
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
+  {
+    if (hhcd->Init.dma_enable == 0U)
+    {
+      hhcd->hc[chnum].state = HC_XACTERR;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+    }
+    else
+    {
+      hhcd->hc[chnum].ErrCnt++;
+      if (hhcd->hc[chnum].ErrCnt > 2U)
+      {
+        hhcd->hc[chnum].ErrCnt = 0U;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+        hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#else
+        HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+        /* Re-activate the channel  */
+        tmpreg = USBx_HC(chnum)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(chnum)->HCCHAR = tmpreg;
+      }
+    }
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
+  {
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+
+    if (hhcd->hc[chnum].state == HC_XFRC)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_DONE;
+
+      if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
+          (hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
+      {
+        if (hhcd->Init.dma_enable == 0U)
+        {
+          hhcd->hc[chnum].toggle_out ^= 1U;
+        }
+
+        if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U))
+        {
+          num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet;
+
+          if ((num_packets & 1U) != 0U)
+          {
+            hhcd->hc[chnum].toggle_out ^= 1U;
+          }
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_ACK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NAK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        hhcd->hc[chnum].do_csplit = 0U;
+        __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NYET)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+    }
+    else if (hhcd->hc[chnum].state == HC_STALL)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state  = URB_STALL;
+    }
+    else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
+             (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].ErrCnt++;
+      if (hhcd->hc[chnum].ErrCnt > 2U)
+      {
+        hhcd->hc[chnum].ErrCnt = 0U;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+        /* re-activate the channel  */
+        tmpreg = USBx_HC(chnum)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(chnum)->HCCHAR = tmpreg;
+      }
+    }
+    else
+    {
+      return;
+    }
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#else
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    return;
+  }
+}
+
+/**
+  * @brief  Handle Rx Queue Level interrupt requests.
+  * @param  hhcd HCD handle
+  * @retval none
+  */
+static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t pktsts;
+  uint32_t pktcnt;
+  uint32_t GrxstspReg;
+  uint32_t xferSizePktCnt;
+  uint32_t tmpreg;
+  uint32_t chnum;
+
+  GrxstspReg = hhcd->Instance->GRXSTSP;
+  chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
+  pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
+  pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
+
+  switch (pktsts)
+  {
+    case GRXSTS_PKTSTS_IN:
+      /* Read the data into the host buffer. */
+      if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0))
+      {
+        if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len)
+        {
+          (void)USB_ReadPacket(hhcd->Instance,
+                               hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt);
+
+          /* manage multiple Xfer */
+          hhcd->hc[chnum].xfer_buff += pktcnt;
+          hhcd->hc[chnum].xfer_count += pktcnt;
+
+          /* get transfer size packet count */
+          xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
+
+          if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U))
+          {
+            /* re-activate the channel when more packets are expected */
+            tmpreg = USBx_HC(chnum)->HCCHAR;
+            tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+            tmpreg |= USB_OTG_HCCHAR_CHENA;
+            USBx_HC(chnum)->HCCHAR = tmpreg;
+            hhcd->hc[chnum].toggle_in ^= 1U;
+          }
+        }
+        else
+        {
+          hhcd->hc[chnum].urb_state = URB_ERROR;
+        }
+      }
+      break;
+
+    case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+      break;
+
+    case GRXSTS_PKTSTS_IN_XFER_COMP:
+    case GRXSTS_PKTSTS_CH_HALTED:
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Handle Host Port interrupt requests.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
+{
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0;
+  __IO uint32_t hprt0_dup;
+
+  /* Handle Host Port Interrupts */
+  hprt0 = USBx_HPRT0;
+  hprt0_dup = USBx_HPRT0;
+
+  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  /* Check whether Port Connect detected */
+  if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+  {
+    if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+    {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->ConnectCallback(hhcd);
+#else
+      HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+    }
+    hprt0_dup |= USB_OTG_HPRT_PCDET;
+  }
+
+  /* Check whether Port Enable Changed */
+  if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_PENCHNG;
+
+    if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+    {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->PortEnabledCallback(hhcd);
+#else
+      HAL_HCD_PortEnabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+    }
+    else
+    {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->PortDisabledCallback(hhcd);
+#else
+      HAL_HCD_PortDisabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Check for an overcurrent */
+  if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+  {
+    hprt0_dup |= USB_OTG_HPRT_POCCHNG;
+  }
+
+  /* Clear Port Interrupts */
+  USBx_HPRT0 = hprt0_dup;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2c.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2c.c
new file mode 100644
index 000000000..a109ee51e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2c.c
@@ -0,0 +1,7840 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the transmit or receive channel
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx channel
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx channel
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
+           no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
+                            start condition, address and data to transfer without a final stop condition,
+                            an then permit a call the same master sequential interface several times
+                            (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+                            after several call of the same master sequential interface several times
+                            (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
+                              Receive sequence permit to call the opposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+                            each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between
+                            each bytes using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+                            generation of STOP condition.
+
+      (+) Different sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+            HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+           add their own code to check the Address Match Code and the transmission direction request by master
+           (Write/Read).
+      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+          add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+     or HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SLAVE_ADDR_SHIFT     7U
+#define SLAVE_ADDR_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
+                                                         and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of global Error
+                                                         and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Macro
+  * @{
+  */
+#if defined(HAL_DMA_MODULE_ENABLED)
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+#if defined(HAL_DMA_MODULE_ENABLED)
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                        uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                         uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                             uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+                               uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+  }
+  else
+  {
+    /* Clear the I2C ADD10 bit */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+                          (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @note   The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+  *         to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+                                           pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @note   The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+  *         to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint16_t tmpXferCount;
+  HAL_StatusTypeDef error;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      /* Flush TX register */
+      I2C_Flush_TXDR(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      /* Flush TX register */
+      I2C_Flush_TXDR(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until AF flag is set */
+    error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+    if (error != HAL_OK)
+    {
+      /* Check that I2C transfer finished */
+      /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+      /* Mean XferCount == 0 */
+
+      tmpXferCount = hi2c->XferCount;
+      if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+      {
+        /* Reset ErrorCode to NONE */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+      else
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Flush TX register */
+      I2C_Flush_TXDR(hi2c);
+
+      /* Clear AF flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Wait until STOP flag is set */
+      if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        return HAL_ERROR;
+      }
+
+      /* Clear STOP flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    }
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferSize = hi2c->XferCount;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          hi2c->XferCount--;
+          hi2c->XferSize--;
+        }
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                            uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                              uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hi2c->hdmatx->LinkedListQueue != NULL)
+          {
+            /* Set DMA data size */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+            /* Set DMA source address */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+            /* Set DMA destination address */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+              = (uint32_t)&hi2c->Instance->TXDR;
+
+            dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+          }
+          else
+          {
+            /* Update I2C state */
+            hi2c->State     = HAL_I2C_STATE_READY;
+            hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+        else
+        {
+          dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                           hi2c->XferSize);
+        }
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                             uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hi2c->hdmarx->LinkedListQueue != NULL)
+          {
+            /* Set DMA data size */
+            hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+            /* Set DMA source address */
+            hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+              = (uint32_t)&hi2c->Instance->RXDR;
+
+            /* Set DMA destination address */
+            hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+            dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+          }
+          else
+          {
+            /* Update I2C state */
+            hi2c->State     = HAL_I2C_STATE_READY;
+            hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+        else
+        {
+          dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                           hi2c->XferSize);
+        }
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    if (hi2c->XferCount != 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hi2c->hdmatx->LinkedListQueue != NULL)
+          {
+            /* Set DMA data size */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+            /* Set DMA source address */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
+
+            /* Set DMA destination address */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+              = (uint32_t)&hi2c->Instance->TXDR;
+
+            dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+          }
+          else
+          {
+            /* Update I2C state */
+            hi2c->State     = HAL_I2C_STATE_LISTEN;
+            hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+        else
+        {
+          dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
+                                           (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+                                           hi2c->XferSize);
+        }
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_LISTEN;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Enable Address Acknowledge */
+        hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR, STOP, NACK, ADDR interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_LISTEN;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if (hi2c->hdmarx->LinkedListQueue != NULL)
+        {
+          /* Set DMA data size */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+          /* Set DMA source address */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+            = (uint32_t)&hi2c->Instance->RXDR;
+
+          /* Set DMA destination address */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+          dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+        }
+        else
+        {
+          /* Update I2C state */
+          hi2c->State     = HAL_I2C_STATE_LISTEN;
+          hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+          /* Update I2C error code */
+          hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
+      }
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+
+    } while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
+        }
+      }
+    } while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->XferSize    = 0U;
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_IT;
+    hi2c->Devaddress  = DevAddress;
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+    /* Send Slave Address and Memory Address */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_IT;
+    hi2c->Devaddress  = DevAddress;
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+    /* Send Slave Address and Memory Address */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_DMA;
+    hi2c->Devaddress  = DevAddress;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if (hi2c->hdmatx->LinkedListQueue != NULL)
+        {
+          /* Set DMA data size */
+          hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+          /* Set DMA source address */
+          hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+          /* Set DMA destination address */
+          hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+            = (uint32_t)&hi2c->Instance->TXDR;
+
+          dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+        }
+        else
+        {
+          /* Update I2C state */
+          hi2c->State     = HAL_I2C_STATE_READY;
+          hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+          /* Update I2C error code */
+          hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                         hi2c->XferSize);
+      }
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address and Memory Address */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Mem_ISR_DMA;
+    hi2c->Devaddress  = DevAddress;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+    {
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if (hi2c->hdmarx->LinkedListQueue != NULL)
+        {
+          /* Set DMA data size */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+          /* Set DMA source address */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+            = (uint32_t)&hi2c->Instance->RXDR;
+
+          /* Set DMA destination address */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+          dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+        }
+        else
+        {
+          /* Update I2C state */
+          hi2c->State     = HAL_I2C_STATE_READY;
+          hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+          /* Update I2C error code */
+          hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
+      }
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address and Memory Address */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+                                        uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t I2C_Trials = 0UL;
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Update I2C state */
+            hi2c->State = HAL_I2C_STATE_READY;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */
+          if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+          {
+            /* Clear STOP Flag */
+            __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+            /* Reset the error code for next trial */
+            hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+          }
+          else
+          {
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
+
+          /* Clear STOP Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+          /* Device is ready */
+          hi2c->State = HAL_I2C_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_OK;
+        }
+      }
+      else
+      {
+        /* A non acknowledge is detected, this mean that device not respond to its address,
+           a new trial must be performed */
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Clear STOP Flag, auto generated with autoend*/
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+        }
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+
+      if ((I2C_Trials < Trials) && (status == HAL_ERROR))
+      {
+        status = HAL_OK;
+      }
+
+    } while (I2C_Trials < Trials);
+
+    /* Update I2C state */
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Update I2C error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                  uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hi2c->hdmatx->LinkedListQueue != NULL)
+          {
+            /* Set DMA data size */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+            /* Set DMA source address */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+            /* Set DMA destination address */
+            hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+              = (uint32_t)&hi2c->Instance->TXDR;
+
+            dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+          }
+          else
+          {
+            /* Update I2C state */
+            hi2c->State     = HAL_I2C_STATE_READY;
+            hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+        else
+        {
+          dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                           hi2c->XferSize);
+        }
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to write */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                                 uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount <= MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA channel */
+        if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hi2c->hdmarx->LinkedListQueue != NULL)
+          {
+            /* Set DMA data size */
+            hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+            /* Set DMA source address */
+            hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+              = (uint32_t)&hi2c->Instance->RXDR;
+
+            /* Set DMA destination address */
+            hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+            dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+          }
+          else
+          {
+            hi2c->State     = HAL_I2C_STATE_READY;
+            hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+        else
+        {
+          dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                           hi2c->XferSize);
+        }
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to read */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+      /* Abort DMA Xfer if any */
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+#endif /* HAL_DMA_MODULE_ENABLED */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                 uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+          will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+          will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if (hi2c->hdmatx->LinkedListQueue != NULL)
+        {
+          /* Set DMA data size */
+          hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+          /* Set DMA source address */
+          hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+          /* Set DMA destination address */
+          hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
+            = (uint32_t)&hi2c->Instance->TXDR;
+
+          dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+        }
+        else
+        {
+          /* Update I2C state */
+          hi2c->State     = HAL_I2C_STATE_LISTEN;
+          hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+          /* Update I2C error code */
+          hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                         hi2c->XferSize);
+      }
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                               uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+#endif /* HAL_DMA_MODULE_ENABLED */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                                uint32_t XferOptions)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if (hi2c->hdmarx->LinkedListQueue != NULL)
+        {
+          /* Set DMA data size */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+          /* Set DMA source address */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
+            = (uint32_t)&hi2c->Instance->RXDR;
+
+          /* Set DMA destination address */
+          hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+          dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+        }
+        else
+        {
+          /* Update I2C state */
+          hi2c->State     = HAL_I2C_STATE_LISTEN;
+          hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+          /* Update I2C error code */
+          hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
+      }
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master or memory I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+
+  if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts and Store Previous state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, tmperror);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  *  @brief   Peripheral State, Mode and Error functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+  * @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+  * @retval I2C Error Code
+  */
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR */
+    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                        uint32_t ITSources)
+{
+  uint32_t direction = I2C_GENERATE_START_WRITE;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    if (hi2c->Memaddress == 0xFFFFFFFFU)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+    else
+    {
+      /* Write LSB part of Memory Address */
+      hi2c->Instance->TXDR = hi2c->Memaddress;
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      direction = I2C_GENERATE_START_READ;
+    }
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_RELOAD_MODE, direction);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+
+      /* Set NBYTES to write and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_AUTOEND_MODE, direction);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    if (hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Data have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t xfermode;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          xfermode = hi2c->XferOptions;
+        }
+        else
+        {
+          xfermode = I2C_AUTOEND_MODE;
+        }
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                         uint32_t ITSources)
+{
+  uint32_t direction = I2C_GENERATE_START_WRITE;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write LSB part of Memory Address */
+    hi2c->Instance->TXDR = hi2c->Memaddress;
+
+    /* Reset Memaddress content */
+    hi2c->Memaddress = 0xFFFFFFFFU;
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable only Error interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+      }
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable only Error and NACK interrupt for data transfer */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      direction = I2C_GENERATE_START_READ;
+    }
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_RELOAD_MODE, direction);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+
+      /* Set NBYTES to write and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_AUTOEND_MODE, direction);
+    }
+
+    /* Update XferCount value */
+    hi2c->XferCount -= hi2c->XferSize;
+
+    /* Enable DMA Request */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t treatdmanack = 0U;
+  HAL_I2C_StateTypeDef tmpstate;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+    {
+      /* Split check of hdmarx, for MISRA compliance */
+      if (hi2c->hdmarx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+        {
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      /* Split check of hdmatx, for MISRA compliance  */
+      if (hi2c->hdmatx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+        {
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      if (treatdmanack == 1U)
+      {
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+          /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+             Warning[Pa134]: left and right operands are identical */
+        {
+          /* Call I2C Listen complete process */
+          I2C_ITListenCplt(hi2c, ITFlags);
+        }
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+          /* Flush TX register */
+          I2C_Flush_TXDR(hi2c);
+
+          /* Last Byte is Transmitted */
+          /* Call I2C Slave Sequential complete process */
+          I2C_ITSlaveSeqCplt(hi2c);
+        }
+        else
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        }
+      }
+      else
+      {
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+        tmpstate = hi2c->State;
+
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+        {
+          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+          }
+          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+          I2C_ITError(hi2c, hi2c->ErrorCode);
+        }
+      }
+    }
+    else
+    {
+      /* Only Clear NACK Flag, no DMA treatment is pending */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection;
+  uint16_t slaveaddrcode;
+  uint16_t ownadd1code;
+  uint16_t ownadd2code;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if (hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterTxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterRxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmperror;
+  uint32_t tmpITFlags = ITFlags;
+  __IO uint32_t tmpreg;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+  }
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Fetch Last receive data if any */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    tmpreg = (uint8_t)hi2c->Instance->RXDR;
+    UNUSED(tmpreg);
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmpITFlags = ITFlags;
+  uint32_t tmpoptions = hi2c->XferOptions;
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+  }
+  else if (tmpstate == HAL_I2C_STATE_LISTEN)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_NONE;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if (hi2c->XferSize > 0U)
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+    }
+  }
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
+    I2C_ITSlaveSeqCplt(hi2c);
+
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if (hi2c->XferSize > 0U)
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  uint32_t tmppreviousstate;
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* If state is an abort treatment on going, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+
+      /* Check if a STOPF is detected */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+      {
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+        {
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+    }
+    hi2c->XferISR       = NULL;
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+                                 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+                                      (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  else
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    I2C_TreatErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+    hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef dmaxferstatus = HAL_OK;
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA channel */
+    if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if (hi2c->hdmatx->LinkedListQueue != NULL)
+      {
+        /* Set DMA data size */
+        hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+        /* Set DMA source address */
+        hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
+
+        /* Set DMA destination address */
+        hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
+
+        dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
+      }
+      else
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+      }
+    }
+    else
+    {
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
+    }
+
+    if (dmaxferstatus != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Last Byte is Transmitted */
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef dmaxferstatus = HAL_OK;
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA channel */
+    if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if (hi2c->hdmarx->LinkedListQueue != NULL)
+      {
+        /* Set DMA data size */
+        hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
+
+        /* Set DMA source address */
+        hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
+
+        /* Set DMA destination address */
+        hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
+
+        dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
+      }
+      else
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+      }
+    }
+    else
+    {
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+                                       hi2c->XferSize);
+    }
+
+    if (dmaxferstatus != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
+      (tmpoptions != I2C_NO_OPTION_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+}
+
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+}
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  This function handles I2C Communication Timeout. It waits
+  *                until a flag is no longer in the specified status.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The actual Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
+    {
+      /* Check if an RXNE is pending */
+      /* Store Last receive data if any */
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+      {
+        /* Return HAL_OK */
+        /* The Reading of data from RXDR will be done in caller function */
+        status = HAL_OK;
+      }
+
+      /* Check a no-acknowledge have been detected */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+      {
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Clear Configuration Register 2 */
+        I2C_RESET_CR2(hi2c);
+
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        status = HAL_ERROR;
+      }
+      else
+      {
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+    }
+
+    /* Check for the Timeout */
+    if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
+    {
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        status = HAL_ERROR;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  This function handles errors detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t itflag   = hi2c->Instance->ISR;
+  uint32_t error_code = 0;
+  uint32_t tickstart = Tickstart;
+  uint32_t tmp1;
+  HAL_I2C_ModeTypeDef tmp2;
+
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
+  {
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Wait until STOP Flag is set or timeout occurred */
+    /* AutoEnd should be initiate after AF */
+    while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+          tmp2 = hi2c->Mode;
+
+          /* In case of I2C still busy, try to regenerate a STOP manually */
+          if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+              (tmp1 != I2C_CR2_STOP) && \
+              (tmp2 != HAL_I2C_MODE_SLAVE))
+          {
+            /* Generate Stop */
+            hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+            /* Update Tick with new reference */
+            tickstart = HAL_GetTick();
+          }
+
+          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+          {
+            /* Check for the Timeout */
+            if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+            {
+              error_code |= HAL_I2C_ERROR_TIMEOUT;
+
+              status = HAL_ERROR;
+
+              break;
+            }
+          }
+        }
+      }
+    }
+
+    /* In case STOP Flag is detected, clear it */
+    if (status == HAL_OK)
+    {
+      /* Clear STOP Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    }
+
+    error_code |= HAL_I2C_ERROR_AF;
+
+    status = HAL_ERROR;
+  }
+
+  /* Refresh Content of Status register */
+  itflag = hi2c->Instance->ISR;
+
+  /* Then verify if an additional errors occurs */
+  /* Check if a Bus error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+  {
+    error_code |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Over-Run/Under-Run error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+  {
+    error_code |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Arbitration Loss error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+  {
+    error_code |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+    status = HAL_ERROR;
+  }
+
+  if (status != HAL_OK)
+  {
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode |= error_code;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+                               uint32_t Request)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+                    (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                    (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
+  /* update CR2 register */
+  MODIFY_REG(hi2c->Instance->CR2, \
+             ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+               I2C_CR2_START | I2C_CR2_STOP)), tmp);
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+      (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+      (hi2c->XferISR != I2C_Mem_ISR_DMA))
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+    }
+
+    if (InterruptRequest == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2c_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2c_ex.c
new file mode 100644
index 000000000..945480e32
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2c_ex.c
@@ -0,0 +1,359 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Filter Mode Functions
+  *           + WakeUp Mode Functions
+  *           + FastModePlus Functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32N6xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_ConfigFastModePlus()
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  * @brief    Filter Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Filter Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @brief    WakeUp Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### WakeUp Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Wake Up Feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @brief    Fast Mode Plus Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Fast Mode Plus Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Fast Mode Plus.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  FastModePlus New state of the Fast Mode Plus.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_FASTMODEPLUS(FastModePlus));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    if (FastModePlus == I2C_FASTMODEPLUS_ENABLE)
+    {
+      /* Set I2Cx FMP bit */
+      hi2c->Instance->CR1 |= (I2C_CR1_FMP);
+    }
+    else
+    {
+      /* Reset I2Cx FMP bit */
+      hi2c->Instance->CR1 &= ~(I2C_CR1_FMP);
+    }
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2s.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2s.c
new file mode 100644
index 000000000..2e9f86eb4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2s.c
@@ -0,0 +1,2635 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2s.c
+  * @author  MCD Application Team
+  * @brief   I2S HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                  ##### How to use this driver #####
+ ===============================================================================
+ [..]
+    The I2S HAL driver can be used as follow:
+
+    (#) Declare a I2S_HandleTypeDef handle structure.
+    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+        (##) Enable the SPIx interface clock.
+        (##) I2S pins configuration:
+            (+++) Enable the clock for the I2S GPIOs.
+            (+++) Configure these I2S pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+             and HAL_I2S_Receive_IT() APIs).
+            (+++) Configure the I2Sx interrupt priority.
+            (+++) Enable the NVIC I2S IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+             and HAL_I2S_Receive_DMA() APIs:
+            (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx Stream/Channel.
+            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+                  DMA Tx/Rx Stream/Channel.
+
+   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+       using HAL_I2S_Init() function.
+
+   -@- The specific I2S interrupts (Transmission complete interrupt,
+       RXNE interrupt and Error Interrupts) will be managed using the macros
+       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+
+        (+@) External clock source is configured after setting correctly
+             the define constant EXTERNAL_CLOCK_VALUE in the stm32n6xx_hal_conf.h file.
+
+    (#) Three mode of operations are available within this driver :
+
+   *** Polling mode IO operation ***
+   =================================
+   [..]
+     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+   *** Interrupt mode IO operation ***
+   ===================================
+   [..]
+     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+   *** DMA mode IO operation ***
+   ==============================
+   [..]
+     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+         add his own code by customization of function pointer HAL_I2S_ErrorCallback
+     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+   *** I2S HAL driver macros list ***
+   ===================================
+   [..]
+     Below the list of most used macros in I2S HAL driver.
+
+      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+    [..]
+      (@) You can refer to the I2S HAL driver header file for more useful macros
+
+   *** I2S HAL driver macros list ***
+   ===================================
+   [..]
+       Callback registration:
+
+      (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL
+          allows the user to configure dynamically the driver callbacks.
+          Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
+
+          Function HAL_I2S_RegisterCallback() allows to register following callbacks:
+            (+) TxCpltCallback        : I2S Tx Completed callback
+            (+) RxCpltCallback        : I2S Rx Completed callback
+            (+) TxRxCpltCallback      : I2S TxRx Completed callback
+            (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
+            (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
+            (+) TxRxHalfCpltCallback  : I2S TxRx Half Completed callback
+            (+) ErrorCallback         : I2S Error callback
+            (+) MspInitCallback       : I2S Msp Init callback
+            (+) MspDeInitCallback     : I2S Msp DeInit callback
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+
+      (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
+          weak function.
+          HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (+) TxCpltCallback        : I2S Tx Completed callback
+            (+) RxCpltCallback        : I2S Rx Completed callback
+            (+) TxRxCpltCallback      : I2S TxRx Completed callback
+            (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
+            (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
+            (+) TxRxHalfCpltCallback  : I2S TxRx Half Completed callback
+            (+) ErrorCallback         : I2S Error callback
+            (+) MspInitCallback       : I2S Msp Init callback
+            (+) MspDeInitCallback     : I2S Msp DeInit callback
+
+       By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
+       all callbacks are set to the corresponding weak functions:
+       examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
+       Exception done for MspInit and MspDeInit functions that are
+       reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
+       these callbacks are null (not registered beforehand).
+       If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
+       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+       Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
+       Exception done MspInit/MspDeInit functions that can be registered/unregistered
+       in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
+       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+       Then, the user first registers the MspInit/MspDeInit user callbacks
+       using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
+       or HAL_I2S_Init() function.
+
+       When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+       not defined, the callback registering feature is not available
+       and weak callbacks are used.
+
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2S I2S
+  * @brief I2S HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Define I2S Private Define
+  * @{
+  */
+#define I2S_TIMEOUT 0xFFFFUL
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+  * @{
+  */
+static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void               I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma);
+static void               I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void               I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s);
+static void               I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
+static void               I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s);
+static void               I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+                                                        uint32_t Tickstart, uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+  * @{
+  */
+
+/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          de-initialize the I2Sx peripheral in simplex mode:
+
+      (+) User must Implement HAL_I2S_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2S_Init() to configure the selected device with
+          the selected configuration:
+        (++) Mode
+        (++) Standard
+        (++) Data Format
+        (++) MCLK Output
+        (++) Audio frequency
+        (++) Polarity
+
+     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+          of the selected I2Sx peripheral.
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2S according to the specified parameters
+  *         in the I2S_InitTypeDef and create the associated handle.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+  uint32_t i2sdiv;
+  uint32_t i2sodd;
+  uint32_t packetlength;
+  uint32_t tmp;
+  uint32_t i2sclk;
+  uint32_t ispcm;
+
+  /* Check the I2S handle allocation */
+  if (hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+  assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
+  assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
+  assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
+  assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
+
+  if (hi2s->State == HAL_I2S_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2s->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+    /* Init the I2S Callback settings */
+    hi2s->TxCpltCallback       = HAL_I2S_TxCpltCallback;          /* Legacy weak TxCpltCallback       */
+    hi2s->RxCpltCallback       = HAL_I2S_RxCpltCallback;          /* Legacy weak RxCpltCallback       */
+    hi2s->TxRxCpltCallback     = HAL_I2SEx_TxRxCpltCallback;      /* Legacy weak TxRxCpltCallback     */
+    hi2s->TxHalfCpltCallback   = HAL_I2S_TxHalfCpltCallback;      /* Legacy weak TxHalfCpltCallback   */
+    hi2s->RxHalfCpltCallback   = HAL_I2S_RxHalfCpltCallback;      /* Legacy weak RxHalfCpltCallback   */
+    hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback;  /* Legacy weak TxRxHalfCpltCallback */
+    hi2s->ErrorCallback        = HAL_I2S_ErrorCallback;           /* Legacy weak ErrorCallback        */
+
+    if (hi2s->MspInitCallback == NULL)
+    {
+      hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    hi2s->MspInitCallback(hi2s);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2S_MspInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+  }
+
+  hi2s->State = HAL_I2S_STATE_BUSY;
+
+  /* Disable the selected I2S peripheral */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
+  {
+    /* Disable I2S peripheral */
+    __HAL_I2S_DISABLE(hi2s);
+  }
+
+  /* Clear I2S configuration register */
+  CLEAR_REG(hi2s->Instance->I2SCFGR);
+
+  if (IS_I2S_MASTER(hi2s->Init.Mode))
+  {
+    /*------------------------- I2SDIV and ODD Calculation ---------------------*/
+    /* If the requested audio frequency is not the default, compute the prescaler */
+    if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+    {
+      /* Check the frame length (For the Prescaler computing) ********************/
+      if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+      {
+        /* Channel length is 32 bits */
+        packetlength = 2UL;
+      }
+      else
+      {
+        /* Channel length is 16 bits */
+        packetlength = 1UL;
+      }
+
+      /* Check if PCM standard is used */
+      if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||
+          (hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
+      {
+        ispcm = 1UL;
+      }
+      else
+      {
+        ispcm = 0UL;
+      }
+
+      /* Get the source clock value: based on System Clock value */
+      if (hi2s->Instance == SPI1)
+      {
+        i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
+      }
+      else if (hi2s->Instance == SPI2)
+      {
+        i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI2);
+      }
+      else if (hi2s->Instance == SPI3)
+      {
+        i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI3);
+      }
+      else /* SPI6 source clock */
+      {
+        i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
+      }
+
+      /* Compute the Real divider depending on the MCLK output state, with a floating point */
+      if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+      {
+        /* MCLK output is enabled */
+        tmp = (uint32_t)((((i2sclk / (256UL >> ispcm)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
+      }
+      else
+      {
+        /* MCLK output is disabled */
+        tmp = (uint32_t)((((i2sclk / ((32UL >> ispcm) * packetlength)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
+      }
+
+      /* Remove the flatting point */
+      tmp = tmp / 10UL;
+
+      /* Check the parity of the divider */
+      i2sodd = (uint32_t)(tmp & (uint32_t)1UL);
+
+      /* Compute the i2sdiv prescaler */
+      i2sdiv = (uint32_t)((tmp - i2sodd) / 2UL);
+    }
+    else
+    {
+      /* Set the default values */
+      i2sdiv = 2UL;
+      i2sodd = 0UL;
+    }
+
+    /* Test if the obtain values are forbidden or out of range */
+    if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
+    {
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+      return  HAL_ERROR;
+    }
+
+    /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */
+    if (i2sdiv == 0UL)
+    {
+      i2sodd = 1UL;
+    }
+
+    MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV                 | SPI_I2SCFGR_ODD),
+               ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
+  }
+
+  /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
+  /* Configure I2SMOD, I2SCFG, I2SSTD, PCMSYNC, DATLEN ,CHLEN ,CKPOL, WSINV, DATAFMT, I2SDIV, ODD and MCKOE bits bits */
+  /* And configure the I2S with the I2S_InitStruct values */
+  MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD   | SPI_I2SCFGR_I2SCFG     | \
+                                       SPI_I2SCFGR_I2SSTD   | SPI_I2SCFGR_PCMSYNC    | \
+                                       SPI_I2SCFGR_DATLEN   | SPI_I2SCFGR_CHLEN      | \
+                                       SPI_I2SCFGR_CKPOL    | SPI_I2SCFGR_WSINV      | \
+                                       SPI_I2SCFGR_DATFMT   | SPI_I2SCFGR_MCKOE),
+             (SPI_I2SCFGR_I2SMOD   | hi2s->Init.Mode        | \
+              hi2s->Init.Standard  | hi2s->Init.DataFormat  | \
+              hi2s->Init.CPOL      | hi2s->Init.WSInversion | \
+              hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
+  /*Clear status register*/
+  WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
+
+  /*---------------------------- I2Sx CFG2 Configuration ----------------------*/
+
+  /* Unlock the AF configuration to configure CFG2 register*/
+  CLEAR_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK);
+
+  MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit);
+
+  /* Insure that AFCNTR is managed only by Master */
+  if (IS_I2S_MASTER(hi2s->Init.Mode))
+  {
+    /* Alternate function GPIOs control */
+    MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
+  }
+
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State     = HAL_I2S_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief DeInitializes the I2S peripheral
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+  /* Check the I2S handle allocation */
+  if (hi2s == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
+  hi2s->State = HAL_I2S_STATE_BUSY;
+
+  /* Disable the I2S Peripheral Clock */
+  __HAL_I2S_DISABLE(hi2s);
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+  if (hi2s->MspDeInitCallback == NULL)
+  {
+    hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  hi2s->MspDeInitCallback(hi2s);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_I2S_MspDeInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State     = HAL_I2S_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2s);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief I2S MSP Init
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief I2S MSP DeInit
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+/**
+  * @brief  Register a User I2S Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2S.
+  * @param  CallbackID ID of the callback to be registered
+  * @param  pCallback pointer to the Callback function
+  * @note   The HAL_I2S_RegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+  *         to register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+                                           pI2S_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_I2S_STATE_READY == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_TX_COMPLETE_CB_ID :
+        hi2s->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_RX_COMPLETE_CB_ID :
+        hi2s->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_TX_RX_COMPLETE_CB_ID :
+        hi2s->TxRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+        hi2s->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+        hi2s->RxHalfCpltCallback = pCallback;
+        break;
+
+
+      case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
+        hi2s->TxRxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_ERROR_CB_ID :
+        hi2s->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2S_STATE_RESET == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2S Callback
+  *         I2S callback is redirected to the weak predefined callback
+  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2S.
+  * @param  CallbackID ID of the callback to be unregistered
+  * @note   The HAL_I2S_UnRegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+  *         to un-register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_I2S_STATE_READY == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_TX_COMPLETE_CB_ID :
+        hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback;                /* Legacy weak TxCpltCallback       */
+        break;
+
+      case HAL_I2S_RX_COMPLETE_CB_ID :
+        hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback;                /* Legacy weak RxCpltCallback       */
+        break;
+
+      case HAL_I2S_TX_RX_COMPLETE_CB_ID :
+        hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback     */
+        break;
+
+      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+        hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback   */
+        break;
+
+      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+        hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback   */
+        break;
+
+      case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
+        hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback;  /* Legacy weak TxRxHalfCpltCallback */
+        break;
+
+      case HAL_I2S_ERROR_CB_ID :
+        hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2S_STATE_RESET == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+  *  @brief Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2S data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2S_Transmit()
+        (++) HAL_I2S_Receive()
+        (++) HAL_I2SEx_TransmitReceive()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2S_Transmit_IT()
+        (++) HAL_I2S_Receive_IT()
+        (++) HAL_I2SEx_TransmitReceive_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2S_Transmit_DMA()
+        (++) HAL_I2S_Receive_DMA()
+        (++) HAL_I2SEx_TransmitReceive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2S_TxCpltCallback()
+        (++) HAL_I2S_RxCpltCallback()
+        (++) HAL_I2SEx_TxRxCpltCallback()
+        (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pData a 16-bit pointer to data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @param  Timeout Timeout duration
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if defined (__GNUC__)
+  __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
+#endif /* __GNUC__ */
+  uint32_t tickstart;
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  /* Set state and reset error code */
+  hi2s->State       = HAL_I2S_STATE_BUSY_TX;
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pData;
+  hi2s->TxXferSize  = Size;
+  hi2s->TxXferCount = Size;
+
+  /* Initialize fields not used in handle to zero */
+  hi2s->pRxBuffPtr  = NULL;
+  hi2s->RxXferSize  = (uint16_t) 0UL;
+  hi2s->RxXferCount = (uint16_t) 0UL;
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+
+  /* Wait until TXP flag is set */
+  if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
+  {
+    /* Set the error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+    hi2s->State = HAL_I2S_STATE_READY;
+    __HAL_UNLOCK(hi2s);
+    return HAL_TIMEOUT;
+  }
+
+  while (hi2s->TxXferCount > 0UL)
+  {
+    if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+    {
+      /* Transmit data in 32 Bit mode */
+      hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
+      hi2s->pTxBuffPtr += 2;
+      hi2s->TxXferCount--;
+    }
+    else
+    {
+      /* Transmit data in 16 Bit mode */
+#if defined (__GNUC__)
+      *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
+#else
+      *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
+#endif /* __GNUC__ */
+
+      hi2s->pTxBuffPtr++;
+      hi2s->TxXferCount--;
+    }
+
+    /* Wait until TXP flag is set */
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
+    {
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+      hi2s->State = HAL_I2S_STATE_READY;
+      __HAL_UNLOCK(hi2s);
+      return HAL_TIMEOUT;
+    }
+  }
+
+  hi2s->State = HAL_I2S_STATE_READY;
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pData a 16-bit pointer to data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @param  Timeout Timeout duration
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+  *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if defined (__GNUC__)
+  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
+#endif /* __GNUC__ */
+  uint32_t tickstart;
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  /* Set state and reset error code */
+  hi2s->State       = HAL_I2S_STATE_BUSY_RX;
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+  hi2s->pRxBuffPtr  = pData;
+  hi2s->RxXferSize  = Size;
+  hi2s->RxXferCount = Size;
+
+  /* Initialize fields not used in handle to zero */
+  hi2s->pTxBuffPtr  = NULL;
+  hi2s->TxXferSize  = (uint16_t) 0UL;
+  hi2s->TxXferCount = (uint16_t) 0UL;
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  /* Receive data */
+  while (hi2s->RxXferCount > 0UL)
+  {
+    /* Wait until RXP flag is set */
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, tickstart, Timeout) != HAL_OK)
+    {
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+      hi2s->State = HAL_I2S_STATE_READY;
+      __HAL_UNLOCK(hi2s);
+      return HAL_TIMEOUT;
+    }
+
+    if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+    {
+      /* Receive data in 32 Bit mode */
+      *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
+      hi2s->pRxBuffPtr += 2;
+      hi2s->RxXferCount--;
+    }
+    else
+    {
+      /* Receive data in 16 Bit mode */
+#if defined (__GNUC__)
+      *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
+#else
+      *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
+#endif /* __GNUC__ */
+      hi2s->pRxBuffPtr++;
+      hi2s->RxXferCount--;
+    }
+  }
+
+  hi2s->State = HAL_I2S_STATE_READY;
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Full-Duplex Transmit/Receive data in blocking mode.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pTxData a 16-bit pointer to the Transmit data buffer.
+  * @param  pRxData a 16-bit pointer to the Receive data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @param  Timeout Timeout duration
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
+                                            uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tmp_TxXferCount;
+  uint32_t tmp_RxXferCount;
+  uint32_t tickstart;
+
+#if defined (__GNUC__)
+  __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
+  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
+#endif /* __GNUC__ */
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  hi2s->TxXferSize  = Size;
+  hi2s->TxXferCount = Size;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pTxData;
+  hi2s->RxXferSize  = Size;
+  hi2s->RxXferCount = Size;
+  hi2s->pRxBuffPtr  = pRxData;
+
+  tmp_TxXferCount = hi2s->TxXferCount;
+  tmp_RxXferCount = hi2s->RxXferCount;
+
+  /* Set state and reset error code */
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  while ((tmp_TxXferCount > 0UL) || (tmp_RxXferCount > 0UL))
+  {
+    if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXP) == SET) && (tmp_TxXferCount != 0UL))
+    {
+      if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+      {
+        /* Transmit data in 32 Bit mode */
+        hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
+        hi2s->pTxBuffPtr += 2;
+        tmp_TxXferCount--;
+      }
+      else
+      {
+        /* Transmit data in 16 Bit mode */
+#if defined (__GNUC__)
+        *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
+#else
+        *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
+#endif /* __GNUC__ */
+
+        hi2s->pTxBuffPtr++;
+        tmp_TxXferCount--;
+      }
+    }
+
+    if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXP) == SET) && (tmp_RxXferCount != 0UL))
+    {
+      if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+      {
+        /* Receive data in 32 Bit mode */
+        *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
+        hi2s->pRxBuffPtr += 2;
+        tmp_RxXferCount--;
+      }
+      else
+      {
+        /* Receive data in 16 Bit mode */
+#if defined (__GNUC__)
+        *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
+#endif /* __GNUC__ */
+        hi2s->pRxBuffPtr++;
+        tmp_RxXferCount--;
+      }
+    }
+
+    /* Timeout management */
+    if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+    {
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+      hi2s->State = HAL_I2S_STATE_READY;
+      __HAL_UNLOCK(hi2s);
+      return HAL_TIMEOUT;
+    }
+  }
+
+  hi2s->State = HAL_I2S_STATE_READY;
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pData a 16-bit pointer to data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
+{
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  /* Set state and reset error code */
+  hi2s->State       = HAL_I2S_STATE_BUSY_TX;
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pData;
+  hi2s->TxXferSize  = Size;
+  hi2s->TxXferCount = Size;
+
+  /* Initialize fields not used in handle to zero */
+  hi2s->pRxBuffPtr  = NULL;
+  hi2s->RxXferSize  = (uint16_t) 0UL;
+  hi2s->RxXferCount = (uint16_t) 0UL;
+
+  /* Set the function for IT treatment */
+  if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+  {
+    hi2s->TxISR = I2S_Transmit_32Bit_IT;
+  }
+  else
+  {
+    hi2s->TxISR = I2S_Transmit_16Bit_IT;
+  }
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Enable TXP interrupt */
+  __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_TXP);
+
+#if (USE_I2S_OVR_UDR_ERRORS != 0UL)
+  /* Enable UDR interrupt */
+  __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_UDR);
+#endif /* USE_I2S_OVR_UDR_ERRORS */
+
+  /* Enable TIFRE interrupt if the mode is Slave  */
+  if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
+  {
+    __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pData a 16-bit pointer to the Receive data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @note   It is recommended to use DMA for the I2S receiver to avoid de-synchronization
+  * between Master and Slave otherwise the I2S interrupt should be optimized.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  /* Set state and reset error code */
+  hi2s->State       = HAL_I2S_STATE_BUSY_RX;
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+  hi2s->pRxBuffPtr  = pData;
+  hi2s->RxXferSize  = Size;
+  hi2s->RxXferCount = Size;
+
+  /* Initialize fields not used in handle to zero */
+  hi2s->pTxBuffPtr  = NULL;
+  hi2s->TxXferSize  = (uint16_t) 0UL;
+  hi2s->TxXferCount = (uint16_t) 0UL;
+
+  /* Set the function for IT treatment */
+  if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+  {
+    hi2s->RxISR = I2S_Receive_32Bit_IT;
+  }
+  else
+  {
+    hi2s->RxISR = I2S_Receive_16Bit_IT;
+  }
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+  /* Enable RXP interrupt */
+  __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_RXP);
+
+#if (USE_I2S_OVR_UDR_ERRORS != 0UL)
+  /* Enable OVR interrupt */
+  __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_OVR);
+#endif /* USE_I2S_OVR_UDR_ERRORS */
+
+  /* Enable TIFRE interrupt if the mode is Slave  */
+  if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
+  {
+    __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pTxData a 16-bit pointer to the Transmit data buffer.
+  * @param  pRxData a 16-bit pointer to the Receive data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
+                                               uint16_t Size)
+{
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  hi2s->pTxBuffPtr  = (const uint16_t *)pTxData;
+  hi2s->pRxBuffPtr  = pRxData;
+
+  hi2s->TxXferSize  = Size;
+  hi2s->TxXferCount = Size;
+  hi2s->RxXferSize  = Size;
+  hi2s->RxXferCount = Size;
+
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->State     = HAL_I2S_STATE_BUSY_TX_RX;
+
+
+  /* Set the function for IT treatment */
+  if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
+  {
+    hi2s->TxISR = I2S_Transmit_32Bit_IT;
+    hi2s->RxISR = I2S_Receive_32Bit_IT;
+  }
+  else
+  {
+    hi2s->TxISR = I2S_Transmit_16Bit_IT;
+    hi2s->RxISR = I2S_Receive_16Bit_IT;
+  }
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Enable TXP, RXP, DXP interrupts */
+  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP));
+
+#if (USE_I2S_OVR_UDR_ERRORS != 0UL)
+  /* Enable UDR, OVR interrupts */
+  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_UDR | I2S_IT_OVR));
+#endif /* USE_I2S_OVR_UDR_ERRORS */
+
+  /* Enable TIFRE interrupt if the mode is Slave  */
+  if (hi2s->Init.Mode == I2S_MODE_SLAVE_FULLDUPLEX)
+  {
+    __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pData a 16-bit pointer to the Transmit data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode;
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  /* Set state and reset error code */
+  hi2s->State       = HAL_I2S_STATE_BUSY_TX;
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pData;
+  hi2s->TxXferSize  = Size;
+  hi2s->TxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hi2s->pRxBuffPtr  = NULL;
+  hi2s->RxXferSize  = (uint16_t)0UL;
+  hi2s->RxXferCount = (uint16_t)0UL;
+
+  /* Set the I2S Tx DMA Half transfer complete callback */
+  hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+  /* Set the I2S Tx DMA transfer complete callback */
+  hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+  /* Set the DMA error callback */
+  hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+  if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
+  {
+    hi2s->TxXferCount = Size * 2U;
+  }
+  else
+  {
+    hi2s->TxXferCount = Size * 4U;
+  }
+
+  /* Enable the Tx DMA Stream/Channel */
+  if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hi2s->hdmatx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount;
+
+      /* Set DMA source address */
+      hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr;
+
+      /* Set DMA destination address */
+      hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR;
+
+      errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx);
+    }
+    else
+    {
+      /* Update SPI error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+
+      /* Unlock the process */
+      __HAL_UNLOCK(hi2s);
+
+      hi2s->State = HAL_I2S_STATE_READY;
+      errorcode = HAL_ERROR;
+      return errorcode;
+    }
+  }
+  else
+  {
+    errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
+                                 hi2s->TxXferCount);
+  }
+
+  /* Check status */
+  if (errorcode != HAL_OK)
+  {
+    /* Update I2S error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+    hi2s->State = HAL_I2S_STATE_READY;
+
+    __HAL_UNLOCK(hi2s);
+    errorcode = HAL_ERROR;
+    return errorcode;
+  }
+
+#if (USE_I2S_OVR_UDR_ERRORS != 0UL)
+  /* Enable UDR interrupt */
+  __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_UDR);
+#endif /* USE_I2S_OVR_UDR_ERRORS */
+
+  /* Check if the I2S Tx request is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
+  {
+    /* Enable Tx DMA Request */
+    SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
+  }
+
+  /* Check if the I2S is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  __HAL_UNLOCK(hi2s);
+  return errorcode;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pData a 16-bit pointer to the Receive data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode;
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  /* Set state and reset error code */
+  hi2s->State       = HAL_I2S_STATE_BUSY_RX;
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+  hi2s->pRxBuffPtr  = pData;
+  hi2s->RxXferSize  = Size;
+  hi2s->RxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hi2s->pTxBuffPtr  = NULL;
+  hi2s->TxXferSize  = (uint16_t)0UL;
+  hi2s->TxXferCount = (uint16_t)0UL;
+
+
+  /* Set the I2S Rx DMA Half transfer complete callback */
+  hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+  /* Set the I2S Rx DMA transfer complete callback */
+  hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+  /* Set the DMA error callback */
+  hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+  if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
+  {
+    hi2s->RxXferCount = Size * 2U;
+  }
+  else
+  {
+    hi2s->RxXferCount = Size * 4U;
+  }
+
+  /* Enable the Rx DMA Stream/Channel */
+  if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hi2s->hdmarx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount;
+
+      /* Set DMA source address */
+      hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR;
+
+      /* Set DMA destination address */
+      hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr;
+
+      errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx);
+    }
+    else
+    {
+      /* Update SPI error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+
+      /* Unlock the process */
+      __HAL_UNLOCK(hi2s);
+
+      hi2s->State = HAL_I2S_STATE_READY;
+      errorcode = HAL_ERROR;
+      return errorcode;
+    }
+  }
+  else
+  {
+    errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
+                                 hi2s->RxXferCount);
+  }
+
+  /* Check status */
+  if (errorcode != HAL_OK)
+  {
+    /* Update I2S error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+    hi2s->State = HAL_I2S_STATE_READY;
+    errorcode = HAL_ERROR;
+    __HAL_UNLOCK(hi2s);
+    return errorcode;
+  }
+
+#if (USE_I2S_OVR_UDR_ERRORS != 0UL)
+  /* Enable OVR interrupts */
+  __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_OVR);
+#endif /* USE_I2S_OVR_UDR_ERRORS */
+
+  /* Check if the I2S Rx request is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
+  {
+    /* Enable Rx DMA Request */
+    SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
+  }
+
+  /* Check if the I2S is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  __HAL_UNLOCK(hi2s);
+  return errorcode;
+}
+
+/**
+  * @brief  Full-Duplex Transmit/Receive data in non-blocking mode using DMA
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  pTxData a 16-bit pointer to the Transmit data buffer.
+  * @param  pRxData a 16-bit pointer to the Receive data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
+                                                uint16_t Size)
+{
+  HAL_StatusTypeDef errorcode;
+
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
+  hi2s->pRxBuffPtr = pRxData;
+
+  hi2s->TxXferSize  = Size;
+  hi2s->TxXferCount = Size;
+  hi2s->RxXferSize  = Size;
+  hi2s->RxXferCount = Size;
+
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+  hi2s->State       = HAL_I2S_STATE_BUSY_TX_RX;
+
+  /* Reset the Tx/Rx DMA bits */
+  CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+  /* Set the I2S Rx DMA Half transfer complete callback */
+  hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;
+
+  /* Set the I2S Rx DMA transfer complete callback */
+  hi2s->hdmarx->XferCpltCallback  = I2SEx_DMATxRxCplt;
+
+  /* Set the I2S Rx DMA error callback */
+  hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+  if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
+  {
+    hi2s->TxXferCount = Size * 2U;
+  }
+  else
+  {
+    hi2s->TxXferCount = Size * 4U;
+  }
+
+  /* Enable the Tx DMA Stream/Channel */
+  if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hi2s->hdmatx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount;
+
+      /* Set DMA source address */
+      hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr;
+
+      /* Set DMA destination address */
+      hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR;
+
+      errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx);
+    }
+    else
+    {
+      /* Update SPI error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+
+      /* Unlock the process */
+      __HAL_UNLOCK(hi2s);
+
+      hi2s->State = HAL_I2S_STATE_READY;
+      errorcode = HAL_ERROR;
+      return errorcode;
+    }
+  }
+  else
+  {
+    errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
+                                 hi2s->TxXferCount);
+  }
+
+  /* Check status */
+  if (errorcode != HAL_OK)
+  {
+    /* Update I2S error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+    hi2s->State = HAL_I2S_STATE_READY;
+
+    __HAL_UNLOCK(hi2s);
+    errorcode = HAL_ERROR;
+    return errorcode;
+  }
+
+  /* Check if the I2S Tx request is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
+  {
+    /* Enable Tx DMA Request */
+    SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
+  }
+
+  if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
+  {
+    hi2s->RxXferCount = Size * 2U;
+  }
+  else
+  {
+    hi2s->RxXferCount = Size * 4U;
+  }
+
+  /* Enable the Rx DMA Stream/Channel */
+  if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hi2s->hdmarx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount;
+
+      /* Set DMA source address */
+      hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR;
+
+      /* Set DMA destination address */
+      hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr;
+
+      errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx);
+    }
+    else
+    {
+      /* Update SPI error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+
+      /* Unlock the process */
+      __HAL_UNLOCK(hi2s);
+
+      hi2s->State = HAL_I2S_STATE_READY;
+      errorcode = HAL_ERROR;
+      return errorcode;
+    }
+  }
+  else
+  {
+    errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
+                                 hi2s->RxXferCount);
+  }
+
+  /* Check status */
+  if (errorcode != HAL_OK)
+  {
+    /* Update I2S error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+    hi2s->State = HAL_I2S_STATE_READY;
+    errorcode = HAL_ERROR;
+    __HAL_UNLOCK(hi2s);
+    return errorcode;
+  }
+
+#if (USE_I2S_OVR_UDR_ERRORS != 0UL)
+  /* Enable UDR, OVR interrupts */
+  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_UDR | I2S_IT_OVR));
+#endif /* USE_I2S_OVR_UDR_ERRORS */
+
+  /* Check if the I2S Rx request is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
+  {
+    /* Enable Rx DMA Request */
+    SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
+  }
+
+  /* Check if the I2S is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  __HAL_UNLOCK(hi2s);
+  return errorcode;
+}
+
+/**
+  * @brief  Pauses the audio DMA Stream/Channel playing from the Media.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  uint32_t tickstart;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+
+  /* Check if the I2S peripheral is in master mode */
+  if (IS_I2S_MASTER(hi2s->Init.Mode))
+  {
+    /* Check if there is a transfer on-going */
+    if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL)
+    {
+      /* Set error code to no on going transfer */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT);
+      hi2s->State = HAL_I2S_STATE_READY;
+
+      __HAL_UNLOCK(hi2s);
+      return HAL_ERROR;
+    }
+
+    SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
+
+    while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
+    {
+      if ((((HAL_GetTick() - tickstart) >=  I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U))
+      {
+        /* Set the I2S State ready */
+        hi2s->State = HAL_I2S_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2s);
+
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+        hi2s->State = HAL_I2S_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Disable I2S peripheral */
+    __HAL_I2S_DISABLE(hi2s);
+
+    hi2s->State = HAL_I2S_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set error code to not supported */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
+    hi2s->State = HAL_I2S_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2s);
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Resumes the audio DMA Stream/Channel playing from the Media.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    hi2s->State = HAL_I2S_STATE_READY;
+
+    __HAL_UNLOCK(hi2s);
+    return HAL_ERROR;
+  }
+
+  /* Set state and reset error code */
+  hi2s->State       = HAL_I2S_STATE_BUSY;
+  hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
+
+  /* Enable I2S peripheral */
+  __HAL_I2S_ENABLE(hi2s);
+
+  /* Start the transfer */
+  SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2s);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the audio DMA Stream/Channel playing from the Media.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL I2S API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+     when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
+     and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+     */
+
+  /* Disable the I2S Tx/Rx DMA requests */
+  CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
+  CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+  /* Abort the I2S DMA tx Stream/Channel */
+  if (hi2s->hdmatx != NULL)
+  {
+    /* Disable the I2S DMA tx Stream/Channel */
+    if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+    {
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+      errorcode = HAL_ERROR;
+    }
+  }
+
+  /* Abort the I2S DMA rx Stream/Channel */
+  if (hi2s->hdmarx != NULL)
+  {
+    /* Disable the I2S DMA rx Stream/Channel */
+    if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+    {
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+      errorcode = HAL_ERROR;
+    }
+  }
+
+  /* Disable I2S peripheral */
+  __HAL_I2S_DISABLE(hi2s);
+
+  hi2s->State = HAL_I2S_STATE_READY;
+
+  return errorcode;
+}
+
+/**
+  * @brief  This function handles I2S interrupt request.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+  uint32_t i2sier   = hi2s->Instance->IER;
+  uint32_t i2ssr    = hi2s->Instance->SR;
+  uint32_t trigger  = i2sier & i2ssr;
+
+  /* I2S in mode Transmitter -----------------------------------------------*/
+  if (HAL_IS_BIT_SET(trigger, I2S_FLAG_DXP))
+  {
+    hi2s->TxISR(hi2s);
+    hi2s->RxISR(hi2s);
+  }
+  /* I2S in mode Receiver ------------------------------------------------*/
+  if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
+  {
+    hi2s->RxISR(hi2s);
+  }
+  /* I2S in mode Transmitter -----------------------------------------------*/
+  if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
+  {
+    hi2s->TxISR(hi2s);
+  }
+#if (USE_I2S_OVR_UDR_ERRORS != 0UL)
+  /* I2S Underrun error interrupt occurred --------------------------------*/
+  if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
+  {
+    /* Disable TXP, RXP and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
+
+    /* Clear Underrun flag */
+    __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+    /* Set the I2S State ready */
+    hi2s->State = HAL_I2S_STATE_READY;
+
+    /* Set the error code and execute error callback*/
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+    /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+    hi2s->ErrorCallback(hi2s);
+#else
+    HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+  }
+
+  /* I2S Overrun error interrupt occurred -------------------------------------*/
+  if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
+  {
+    /* Disable TXP, RXP and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
+
+    /* Clear Overrun flag */
+    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+    /* Set the I2S State ready */
+    hi2s->State = HAL_I2S_STATE_READY;
+
+
+    /* Set the error code and execute error callback*/
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+
+    /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+    hi2s->ErrorCallback(hi2s);
+#else
+    HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+  }
+#endif /* USE_I2S_OVR_UDR_ERRORS */
+}
+
+/**
+  * @brief  Tx Transfer Half completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer half completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer half completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2S error callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2S state
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval HAL state
+  */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s)
+{
+  return hi2s->State;
+}
+
+/**
+  * @brief  Return the I2S error code
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval I2S Error Code
+  */
+uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s)
+{
+  return hi2s->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2S_Private_Functions
+  * @{
+  */
+/**
+  * @brief  DMA I2S transmit process complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* if DMA is configured in DMA_NORMAL Mode */
+  if (hdma->Init.Mode == DMA_NORMAL)
+  {
+    /* Disable Tx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+    hi2s->TxXferCount = (uint16_t) 0UL;
+    hi2s->State = HAL_I2S_STATE_READY;
+  }
+  /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+  hi2s->TxCpltCallback(hi2s);
+#else
+  HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA I2S transmit process half complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Call user Tx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+  hi2s->TxHalfCpltCallback(hi2s);
+#else
+  HAL_I2S_TxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA I2S receive process complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* if DMA is configured in DMA_NORMAL Mode */
+  if (hdma->Init.Mode == DMA_NORMAL)
+  {
+    /* Disable Rx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
+    hi2s->RxXferCount = (uint16_t)0UL;
+    hi2s->State = HAL_I2S_STATE_READY;
+  }
+  /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+  hi2s->RxCpltCallback(hi2s);
+#else
+  HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA I2S receive process half complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Call user Rx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+  hi2s->RxHalfCpltCallback(hi2s);
+#else
+  HAL_I2S_RxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA I2S transmit receive process complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* if DMA is configured in DMA_NORMAL Mode */
+  if (hdma->Init.Mode == DMA_NORMAL)
+  {
+    /* Disable Tx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
+    hi2s->TxXferCount = (uint16_t) 0UL;
+
+    /* Disable Rx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
+    hi2s->RxXferCount = (uint16_t)0UL;
+
+    /* Updated HAL State */
+    hi2s->State = HAL_I2S_STATE_READY;
+  }
+
+  /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  hi2s->TxRxCpltCallback(hi2s);
+#else
+  HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA I2S transmit receive process half complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Call user TxRx Half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  hi2s->TxRxHalfCpltCallback(hi2s);
+#else
+  HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA I2S communication error callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *         the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable Rx and Tx DMA Request */
+  CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
+  hi2s->TxXferCount = (uint16_t) 0UL;
+  hi2s->RxXferCount = (uint16_t) 0UL;
+
+  hi2s->State = HAL_I2S_STATE_READY;
+
+  /* Set the error code and execute error callback*/
+  SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+  /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+  hi2s->ErrorCallback(hi2s);
+#else
+  HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Manage the transmission 16-bit in Interrupt context
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
+{
+  /* Transmit data */
+#if defined (__GNUC__)
+  __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
+
+  *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
+#else
+  *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
+#endif /* __GNUC__ */
+  hi2s->pTxBuffPtr++;
+  hi2s->TxXferCount--;
+
+  if (hi2s->TxXferCount == 0UL)
+  {
+    /* Disable TXP and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
+
+    if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+    {
+      hi2s->State = HAL_I2S_STATE_READY;
+
+      /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+      hi2s->TxCpltCallback(hi2s);
+#else
+      HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Manage the transmission 32-bit in Interrupt context
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
+{
+  /* Transmit data */
+  hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
+  hi2s->pTxBuffPtr += 2;
+  hi2s->TxXferCount--;
+
+  if (hi2s->TxXferCount == 0UL)
+  {
+    /* Disable TXP and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
+
+    if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+    {
+      hi2s->State = HAL_I2S_STATE_READY;
+
+      /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+      hi2s->TxCpltCallback(hi2s);
+#else
+      HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Manage the reception 16-bit in Interrupt context
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s)
+{
+  /* Receive data */
+#if defined (__GNUC__)
+  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
+
+  *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
+#else
+  *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
+#endif /* __GNUC__ */
+  hi2s->pRxBuffPtr++;
+  hi2s->RxXferCount--;
+
+  if (hi2s->RxXferCount == 0UL)
+  {
+    if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+    {
+      /* Disable TXP, RXP, DXP, ERR interrupts */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
+    }
+    else
+    {
+      /* Disable RXP and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+    }
+
+    hi2s->State = HAL_I2S_STATE_READY;
+    /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+    if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+    {
+      hi2s->TxRxCpltCallback(hi2s);
+    }
+    else
+    {
+      hi2s->RxCpltCallback(hi2s);
+    }
+#else
+    if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+    {
+      HAL_I2SEx_TxRxCpltCallback(hi2s);
+    }
+    else
+    {
+      HAL_I2S_RxCpltCallback(hi2s);
+    }
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Manage the reception 32-bit in Interrupt context
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @retval None
+  */
+static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s)
+{
+  /* Receive data */
+  *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
+  hi2s->pRxBuffPtr += 2;
+  hi2s->RxXferCount--;
+
+  if (hi2s->RxXferCount == 0UL)
+  {
+    if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+    {
+      /* Disable TXP, RXP, DXP, ERR interrupts */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
+    }
+    else
+    {
+      /* Disable RXP and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+    }
+
+    hi2s->State = HAL_I2S_STATE_READY;
+    /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
+    if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+    {
+      hi2s->TxRxCpltCallback(hi2s);
+    }
+    else
+    {
+      hi2s->RxCpltCallback(hi2s);
+    }
+#else
+    if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
+    {
+      HAL_I2SEx_TxRxCpltCallback(hi2s);
+    }
+    else
+    {
+      HAL_I2S_RxCpltCallback(hi2s);
+    }
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  This function handles I2S Communication Timeout.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
+  *         the configuration information for I2S module
+  * @param  Flag Flag checked
+  * @param  State Value of the flag expected
+  * @param  Tickstart Tick start value
+  * @param  Timeout Duration of the timeout
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+                                                       uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set to status*/
+  while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0UL))
+      {
+        /* Set the I2S State ready */
+        hi2s->State = HAL_I2S_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2s);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2s_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2s_ex.c
new file mode 100644
index 000000000..78e90619e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i2s_ex.c
@@ -0,0 +1,31 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_i2s_ex.c
+  * @author  MCD Application Team
+  * @brief   I2S HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2S extension peripheral:
+  *           + Extension features Functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/**
+  ******************************************************************************
+                      ===== I2S FULL DUPLEX FEATURE =====
+       I2S Full Duplex APIs are available in stm32n6xx_hal_i2s.c/.h
+  ******************************************************************************
+  */
+
+
+
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i3c.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i3c.c
new file mode 100644
index 000000000..939a63c04
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_i3c.c
@@ -0,0 +1,9841 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_hal_i3c.c
+  * @author  MCD Application Team
+  * @brief   I3C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Improvement Inter Integrated Circuit (I3C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  @verbatim
+  ======================================================================================================================
+                                           ##### How to use this driver #####
+  ======================================================================================================================
+    [..]
+    The I3C HAL driver can be used as follows:
+
+    (#) Declare a I3C_HandleTypeDef handle structure, for example:
+        I3C_HandleTypeDef  hi3c;
+
+    (#) Declare a I3C_XferTypeDef transfer descriptor structure, for example:
+        I3C_XferTypeDef  ContextBuffers;
+
+    (#)Initialize the I3C low level resources by implementing the HAL_I3C_MspInit() API:
+        (##) Enable the I3Cx interface clock
+        (##) I3C pins configuration
+            (+++) Enable the clock for the I3C GPIOs
+            (+++) Configure I3C pins as alternate function push-pull with no-pull
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I3Cx interrupt priority
+            (+++) Enable the NVIC I3C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the Command Common Code (CCC) management channel
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the transmit channel
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the receive channel
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the status channel
+            (+++) Enable the DMAx interface clock
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Command Common Code (CCC) channel
+            (+++) Configure the DMA Tx channel
+            (+++) Configure the DMA Rx channel
+            (+++) Configure the DMA Status channel
+            (+++) Associate the initialized DMA handle to the hi3c DMA CCC, Tx, Rx or Status handle as necessary
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA CCC, Tx, Rx or Status instance
+
+    (#) Configure the HAL I3C Communication Mode as Controller or Target in the hi3c Init structure.
+
+    (#) Configure the Controller Communication Bus characterics for Controller mode.
+        This mean, configure the parameters SDAHoldTime, WaitTime, SCLPPLowDuration,
+        SCLI3CHighDuration, SCLODLowDuration, SCLI2CHighDuration, BusFreeDuration,
+        BusIdleDuration in the LL_I3C_CtrlBusConfTypeDef structure through h3c Init structure.
+
+    (#) Configure the Target Communication Bus characterics for Target mode.
+        This mean, configure the parameter BusAvailableDuration in the LL_I3C_TgtBusConfTypeDef structure
+        through h3c Init structure.
+
+        All these parameters for Controller or Target can be configured directly in user code or
+        by using CubeMx generation.
+        To help the computation of the different parameters, the recommendation is to use CubeMx.
+
+        Those parameters can be modified after the hi3c initialization by using
+        HAL_I3C_Ctrl_BusCharacteristicConfig() for controller and
+        HAL_I3C_Tgt_BusCharacteristicConfig() for target.
+
+    (#) Initialize the I3C registers by calling the HAL_I3C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I3C_MspInit(&hi3c) API.
+
+    (#) Configure the different FIFO parameters in I3C_FifoConfTypeDef structure as RxFifoThreshold, TxFifoThreshold
+        for Controller or Target mode.
+        And enable/disable the Control or Status FIFO only for Controller Mode.
+        Use HAL_I3C_SetConfigFifo() function to finalize the configuration, and HAL_I3C_GetConfigFifo() to retrieve
+        FIFO configuration.
+        Possibility to clear the FIFO configuration by using HAL_I3C_ClearConfigFifo() which reset the configuration
+        FIFO to their default hardware value
+
+    (#) Configure the different additional Controller configuration in I3C_CtrlConfTypeDef structure as DynamicAddr,
+        StallTime, HotJoinAllowed, ACKStallState, CCCStallState, TxStallState, RxStallState, HighKeeperSDA.
+        Use HAL_I3C_Ctrl_Config() function to finalize the Controller configuration.
+
+    (#) Configure the different additional Target configuration in I3C_TgtConfTypeDef structure as Identifier,
+        MIPIIdentifier, CtrlRoleRequest, HotJoinRequest, IBIRequest, IBIPayload, IBIPayloadSize, MaxReadDataSize,
+        MaxWriteDataSize, CtrlCapability, GroupAddrCapability, DataTurnAroundDuration, MaxReadTurnAround,
+        MaxDataSpeed, MaxSpeedLimitation, HandOffActivityState, HandOffDelay, PendingReadMDB.
+        Use HAL_I3C_Tgt_Config() function to finalize the Target configuration.
+
+    (#) Before initiate any IO operation, the application must launch an assignment of the different
+        Target dynamic address by using HAL_I3C_Ctrl_DynAddrAssign() in polling mode or
+        HAL_I3C_Ctrl_DynAddrAssign_IT() in interrupt mode.
+        This procedure is named Enter Dynamic Address Assignment (ENTDAA CCC command).
+        For the initiation of ENTDAA procedure from the controller, each target connected and powered on the I3C bus
+        must repond to this particular Command Common Code by sending its proper Payload (a amount of 48bits which
+        contain the target characteristics)
+        Each time a target responds to ENTDAA sequence, the application is informed through
+        HAL_I3C_TgtReqDynamicAddrCallback() of the reception of the target paylaod.
+        And then application must send a associated dynamic address through HAL_I3C_Ctrl_SetDynAddr().
+        This procedure in loop automatically in hardware side until a target respond to repeated ENTDAA sequence.
+        The application is informed of the end of the procedure at reception of HAL_I3C_CtrlDAACpltCallback().
+        Then application can easily retrieve ENTDAA payload information through HAL_I3C_Get_ENTDAA_Payload_Info()
+        function.
+        At the end of procedure, the function HAL_I3C_Ctrl_ConfigBusDevices() must be called to store in hardware
+        register part the target capabilities as Dynamic address, IBI support with or without additional data byte,
+        Controller role request support, Controller stop transfer after IBI through I3C_DeviceConfTypeDef structure.
+
+    (#) Other action to be done, before initiate any IO operation, the application must prepare the different frame
+        descriptor with its associated buffer allocation in their side.
+        Configure the different information related to CCC transfer through I3C_CCCTypeDef structure
+        Configure the different information related to Private or I2C transfer through I3C_PrivateTypeDef structure
+        Configure the different buffer pointers and associated size needed for the driver communication
+        through I3C_XferTypeDef structure
+        The I3C_XferTypeDef structure contains different parameters about Control, Status buffer,
+        and Transmit and Receive buffer.
+        Use HAL_I3C_AddDescToFrame() function each time application add a descriptor in the frame before call
+        a Controller IO operation interface
+        One element of the frame descriptor correspond to one frame to manage through IO operation.
+
+    (#) To check if I3C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI3C_Ready()
+
+    (#) To check if I2C target device is ready for communication, use the function HAL_I3C_Ctrl_IsDeviceI2C_Ready()
+
+    (#) To send a message header {S + 0x7E + W + STOP}, use the function HAL_I3C_Ctrl_GenerateArbitration().
+    (#) To insert a target reset pattern before the STOP of a transmitted frame containing a RSTACT CCC command,
+        the application must enable the reset pattern configuration using HAL_I3C_Ctrl_SetConfigResetPattern()
+        before calling HAL_I3C_Ctrl_TransmitCCC() or HAL_I3C_Ctrl_ReceiveCCC() interfaces.
+
+        To have a standard STOP emitted at the end of a frame containing a RSTACT CCC command, the application must
+        disable the reset pattern configuration using HAL_I3C_Ctrl_SetConfigResetPattern() before calling
+        HAL_I3C_Ctrl_TransmitCCC() or HAL_I3C_Ctrl_ReceiveCCC() interfaces.
+
+        Use HAL_I3C_Ctrl_SetConfigResetPattern() function to configure the insertion of the reset pattern at
+        the end of a Frame, and HAL_I3C_Ctrl_GetConfigResetPattern() to retrieve reset pattern configuration.
+
+    (#) For I3C IO operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Activate asynchronous event in controller or target mode a Common Command Code in a broadcast
+          or a direct communication in blocking mode using HAL_I3C_Ctrl_TransmitCCC()
+      (+) Transmit in controller mode a Common Command Code in a broadcast or a direct communication in blocking mode
+          using HAL_I3C_Ctrl_TransmitCCC()
+      (+) Receive in controller mode a Common Command Code in a direct communication in blocking mode
+          using HAL_I3C_Ctrl_ReceiveCCC()
+      (+) Transmit in controller mode an amount of private data in an I3C or an I2C communication in blocking mode
+          using HAL_I3C_Ctrl_Transmit()
+      (+) Receive in controller mode an amount of private data in an I3C or an I2C communication in blocking mode
+          using HAL_I3C_Ctrl_Receive()
+      (+) Transmit in target mode an amount of private data in an I3C communication in blocking mode
+          using HAL_I3C_Tgt_Transmit()
+      (+) Receive in target mode an amount of private data in an I3C communication in blocking mode
+          using HAL_I3C_Tgt_Receive()
+      (+) At the end of a transfer, the different FIFO can be flushed if necessary by using HAL_I3C_FlushAllFifo() for
+          flush all the FIFO, or flush individually y using HAL_I3C_FlushTxFifo(), HAL_I3C_FlushRxFifo(),
+          HAL_I3C_FlushControlFifo(), HAL_I3C_FlushStatusFifo().
+      (+) Request a HotJoin in target mode in blocking mode using HAL_I3C_Tgt_HotJoinReq()
+      (+) Request a In Band Interrupt in target mode in blocking mode using HAL_I3C_Tgt_IBIReq()
+      (+) Request a Controller Role in target mode in blocking mode using HAL_I3C_Tgt_ControlRoleReq()
+
+
+    *** DMA and Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in controller mode a Common Command Code in a broadcast or a direct communication in non-blocking
+          mode using HAL_I3C_Ctrl_TransmitCCC_IT() or HAL_I3C_Ctrl_TransmitCCC_DMA()
+      (+) At transmission end of transfer, HAL_I3C_CtrlTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_CtrlTxCpltCallback()
+      (+) Receive in controller mode a Common Command Code in a direct communication in non-blocking
+          mode using HAL_I3C_Ctrl_ReceiveCCC_IT() or HAL_I3C_Ctrl_ReceiveCCC_DMA()
+      (+) At reception end of transfer, HAL_I3C_CtrlRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_CtrlRxCpltCallback()
+      (+) Transmit in controller mode an amount of private data in an I3C or an I2C communication in non-blocking mode
+          using HAL_I3C_Ctrl_Transmit_IT() or HAL_I3C_Ctrl_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I3C_CtrlTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_CtrlTxCpltCallback()
+      (+) Receive in controller mode an amount of private data in an I3C or an I2C communication in non-blocking mode
+          using HAL_I3C_Ctrl_Receive_IT() or HAL_I3C_Ctrl_Receive_DMA()
+      (+) At reception end of transfer, HAL_I3C_CtrlRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_CtrlRxCpltCallback()
+      (+) Transfer in multiple direction (transmit/receive) in controller mode a Common Command Code in a direct
+          communication or an amount of private data in an I2C or I3C communication in non-blocking mode using
+          HAL_I3C_Ctrl_MultipleTransfer_IT() or HAL_I3C_Ctrl_MultipleTransfer_DMA()
+      (+) At the end of transfer, HAL_I3C_CtrlMultipleXferCpltCallback() is executed and users can
+          add their own code by customization of function pointer HAL_I3C_CtrlMultipleXferCpltCallback()
+      (+) Transmit in target mode an amount of private data in an I3C communication in non-blocking mode
+          using HAL_I3C_Tgt_Transmit_IT() or HAL_I3C_Tgt_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I3C_TgtTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_TgtTxCpltCallback()
+      (+) Receive in target mode an amount of private data in an I3C communication in non-blocking mode
+          using HAL_I3C_Tgt_Receive_IT() or HAL_I3C_Tgt_Receive_DMA()
+      (+) At reception end of transfer, HAL_I3C_TgtRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_TgtRxCpltCallback()
+      (+) To treat asynchronous event, HAL_I3C_ActivateNotification() or HAL_I3C_DeactivateNotification() function is
+          used for enable or disable one or more notification related to specific asynchronous event.
+          Each time one or more event detected by hardware the associated HAL_I3C_NotifyCallback() is executed
+           and users can add their own code by customization of function pointer HAL_I3C_NotifyCallback().
+          Then application can easily retrieve some specific associated event data through HAL_I3C_GetCCCInfo() function
+      (+) At the end of a transfer, the different FIFO can be flushed if necessary by using HAL_I3C_FlushAllFifo() for
+          flush all the FIFO, or flush individually y using HAL_I3C_FlushTxFifo(), HAL_I3C_FlushRxFifo(),
+          HAL_I3C_FlushControlFifo(), HAL_I3C_FlushStatusFifo().
+      (+) Request a HotJoin in target mode in non-blocking mode using HAL_I3C_Tgt_HotJoinReq_IT
+      (+) At completion, HAL_I3C_TgtHotJoinCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_TgtHotJoinCallback()
+      (+) Request an In Band Interrupt in target mode in non-blocking mode using HAL_I3C_Tgt_IBIReq_IT()
+      (+) At completion, HAL_I3C_NotifyCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_NotifyCallback()
+      (+) Request a Controller Role in target mode in non-blocking mode using HAL_I3C_Tgt_ControlRoleReq_IT()
+      (+) At completion, HAL_I3C_NotifyCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_NotifyCallback()
+      (+) To manage the wakeup capability, HAL_I3C_ActivateNotification() or HAL_I3C_DeactivateNotification() function
+          is used for enable or disable Wake Up interrupt.
+          At wakeup detection the associated HAL_I3C_NotifyCallback() is executed.
+      (+) In case of transfer Error, HAL_I3C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I3C_ErrorCallback()
+      (+) Abort an I3C process communication with Interrupt using HAL_I3C_Abort_IT()
+      (+) End of abort process, HAL_I3C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I3C_AbortCpltCallback()
+
+
+     *** I3C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I3C HAL driver.
+
+      (+) __HAL_I3C_ENABLE: Enable the I3C peripheral
+      (+) __HAL_I3C_DISABLE: Disable the I3C peripheral
+      (+) __HAL_I3C_RESET_HANDLE_STATE: Reset the I3C handle state
+      (+) __HAL_I3C_GET_FLAG: Check whether the specified I3C flag is set or not
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I3C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_I3C_RegisterCallback() or HAL_I3C_RegisterNotifyCallback()
+     or HAL_I3C_RegisterTgtReqDynamicAddrCallback() or HAL_I3C_RegisterTgtHotJoinCallback()
+     to register an interrupt callback.
+    [..]
+     Function HAL_I3C_RegisterCallback() allows to register following callbacks:
+       (+) CtrlTxCpltCallback   : callback for Controller transmission CCC, I3C private or I2C end of transfer.
+       (+) CtrlRxCpltCallback   : callback for Controller reception CCC, I3C private or I2C end of transfer.
+       (+) CtrlMultipleXferCpltCallback : callback for Controller multiple Direct CCC, I3C private or I2C
+           end of transfer.
+       (+) CtrlDAACpltCallback  : callback for Controller Enter Dynamic Address Assignment end of transfer.
+       (+) TgtTxCpltCallback    : callback for Target transmission I3C private end of transfer.
+       (+) TgtRxCpltCallback    : callback for Target reception I3C private end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback NotifyCallback
+     use dedicated register callbacks : HAL_I3C_RegisterNotifyCallback().
+    [..]
+     For specific callback TgtReqDynamicAddrCallback
+     use dedicated register callbacks : HAL_I3C_RegisterTgtReqDynamicAddrCallback().
+    [..]
+     For specific callback TgtHotJoinCallback
+     use dedicated register callbacks : HAL_I3C_RegisterTgtHotJoinCallback().
+    [..]
+     Use function HAL_I3C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     HAL_I3C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) CtrlTxCpltCallback   : callback for Controller transmission CCC, I3C private or I2C end of transfer.
+       (+) CtrlRxCpltCallback   : callback for Controller reception CCC, I3C private or I2C end of transfer.
+       (+) CtrlMultipleXferCpltCallback : callback for Controller multiple Direct CCC, I3C private or I2C
+           end of transfer.
+       (+) CtrlDAACpltCallback  : callback for Controller Enter Dynamic Address Assignment end of transfer.
+       (+) TgtTxCpltCallback    : callback for Target transmission I3C private end of transfer.
+       (+) TgtRxCpltCallback    : callback for Target reception I3C private end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+       (+) NotifyCallback       : callback for Controller and Target notification process.
+       (+) TgtReqDynamicAddrCallback  : callback for controller application
+            when a target sent its payload to the controller during Dynamic Address Assignment process.
+       (+) TgtHotJoinCallback   : callback for Target Hotjoin completion process.
+    [..]
+     By default, after the HAL_I3C_Init() and when the state is HAL_I3C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_I3C_CtrlTxCpltCallback(), HAL_I3C_CtrlRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_I3C_Init()/ HAL_I3C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the HAL_I3C_Init()/ HAL_I3C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in HAL_I3C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_I3C_STATE_READY or HAL_I3C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_I3C_RegisterCallback() before calling HAL_I3C_DeInit()
+     or HAL_I3C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I3C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I3C HAL driver header file for more useful macros
+
+  @endverbatim
+  **********************************************************************************************************************
+  */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I3C I3C
+  * @brief I3C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I3C_MODULE_ENABLED
+
+/* Private typedef ---------------------------------------------------------------------------------------------------*/
+/* Private define ----------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Private_Define I3C Private Define
+  * @{
+  */
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I3C_XFER_LISTEN_IT            (0x00000001U)
+#define I3C_XFER_TARGET_TX_IT         (0x00000002U)
+#define I3C_XFER_TARGET_RX_IT         (0x00000004U)
+#define I3C_XFER_DMA                  (0x00000008U)
+#define I3C_XFER_TARGET_CTRLROLE      (0x00000010U)
+#define I3C_XFER_TARGET_HOTJOIN       (0x00000020U)
+#define I3C_XFER_TARGET_IBI           (0x00000040U)
+#define I3C_XFER_CONTROLLER_TX_IT     (0x00000080U)
+#define I3C_XFER_CONTROLLER_RX_IT     (0x00000100U)
+#define I3C_XFER_CONTROLLER_RX_CCC_IT (0x00000400U)
+#define I3C_XFER_CONTROLLER_DAA_IT    (0x00001000U)
+
+/* Private defines for control buffer prior preparation */
+#define I3C_OPERATION_TYPE_MASK       (0x78000000U)
+#define I3C_RESTART_STOP_MASK         (0x80000000U)
+#define I3C_ARBITRATION_HEADER_MASK   (0x00000004U)
+#define I3C_DEFINE_BYTE_MASK          (0x00000001U)
+
+/* Private define for CCC command */
+#define I3C_BROADCAST_RSTDAA          (0x00000006U)
+#define I3C_BROADCAST_ENTDAA          (0x00000007U)
+
+/* Private define to split ENTDAA payload */
+#define I3C_DCR_IN_PAYLOAD_SHIFT       56
+#define I3C_PID_IN_PAYLOAD_MASK        0xFFFFFFFFFFFFU
+
+/* Private define to split PID */
+/* Bits[47:33]: MIPI Manufacturer ID */
+#define I3C_MIPIMID_PID_SHIFT          33
+#define I3C_MIPIMID_PID_MASK           0x7FFFU
+
+/* Bit[32]: Provisioned ID Type Selector */
+#define I3C_IDTSEL_PID_SHIFT           32
+#define I3C_IDTSEL_PID_MASK            0x01U
+
+/* Bits[31:16]: Part ID */
+#define I3C_PART_ID_PID_SHIFT          16
+#define I3C_PART_ID_PID_MASK           0xFFFFU
+
+/* Bits[15:12]: MIPI Instance ID */
+#define I3C_MIPIID_PID_SHIFT           12
+#define I3C_MIPIID_PID_MASK            0xFU
+/**
+  * @}
+  */
+
+/* Private macro -----------------------------------------------------------------------------------------------------*/
+
+/** @brief  Get Provisioned ID in payload (64bits) receive during ENTDAA procedure.
+  * @param  __PAYLOAD__ specifies the Device Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFF.
+  * @retval The value of PID Return value between Min_Data=0x00 and Max_Data=0xFFFFFFFFFFFF.
+  */
+#define I3C_GET_PID(__PAYLOAD__) ((uint64_t)(__PAYLOAD__) & I3C_PID_IN_PAYLOAD_MASK)
+
+/** @brief  Get MIPI Manufacturer ID in PID (48bits).
+  * @param  __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF.
+  * @retval The value of MIPI ID Return value between Min_Data=0x00 and Max_Data=0x7FFF.
+  */
+#define I3C_GET_MIPIMID(__PID__) ((uint16_t)((uint64_t)(__PID__) >> I3C_MIPIMID_PID_SHIFT) & \
+                                  I3C_MIPIMID_PID_MASK)
+
+/** @brief  Get Type Selector in PID (48bits).
+  * @param  __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF.
+  * @retval The value of Type Selector Return 0 or 1.
+  */
+#define I3C_GET_IDTSEL(__PID__) ((uint8_t)((uint64_t)(__PID__) >> I3C_IDTSEL_PID_SHIFT) & \
+                                 I3C_IDTSEL_PID_MASK)
+
+/** @brief  Get Part ID in PID (48bits).
+  * @param  __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF.
+  * @retval The value of Part ID Return value between Min_Data=0x00 and Max_Data=0xFFFF.
+  */
+#define I3C_GET_PART_ID(__PID__) ((uint16_t)((uint64_t)(__PID__) >> I3C_PART_ID_PID_SHIFT) & \
+                                  I3C_PART_ID_PID_MASK)
+
+/** @brief  Get Instance ID in PID (48bits).
+  * @param  __PID__ specifies the Provisioned ID retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFF.
+  * @retval The value of Instance ID Return value between Min_Data=0x00 and Max_Data=0xF.
+  */
+#define I3C_GET_MIPIID(__PID__) ((uint8_t)((uint64_t)(__PID__) >> I3C_MIPIID_PID_SHIFT) & \
+                                 I3C_MIPIID_PID_MASK)
+
+/** @brief  Get Device Characterics in payload (64bits) receive during ENTDAA procedure.
+  * @param  __PAYLOAD__ specifies the Device Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF.
+  * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF.
+  */
+#define I3C_GET_DCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> I3C_DCR_IN_PAYLOAD_SHIFT)) & \
+                                  I3C_DCR_DCR)
+
+/** @brief  Get Advanced Capabilities.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval The value of advanced capabilities:
+  *           ENABLE: supports optional advanced capabilities.
+  *           DISABLE: not supports optional advanced capabilities.
+  */
+#define I3C_GET_ADVANCED_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR5_Msk) >> \
+                                             I3C_BCR_BCR5_Pos) == 1U) ? ENABLE : DISABLE)
+
+/** @brief  Get virtual target support.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval The value of offline capable:
+  *           ENABLE: is a Virtual Target
+  *           DISABLE: is not a Virtual Target
+  */
+#define I3C_GET_VIRTUAL_TGT(__BCR__) (((((__BCR__) & I3C_BCR_BCR4_Msk) >> \
+                                        I3C_BCR_BCR4_Pos) == 1U) ? ENABLE : DISABLE)
+
+/** @brief  Get offline capable.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval The value of offline capable
+  *           ENABLE: Device will not always respond to I3C Bus commands
+  *           DISABLE: Device will always respond to I3C Bus commands
+  */
+#define I3C_GET_OFFLINE_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR3_Msk) >> \
+                                            I3C_BCR_BCR3_Pos) == 1U) ? ENABLE : DISABLE)
+
+/** @brief  Get Max data speed limitation.
+  * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
+  *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
+  * @retval The value of offline capable:
+  *           ENABLE: Limitation
+  *           DISABLE: No Limitation
+  */
+#define I3C_GET_MAX_DATA_SPEED_LIMIT(__BCR__) (((((__BCR__) & I3C_BCR_BCR0_Msk) >> \
+                                                 I3C_BCR_BCR0_Pos) == 1U) ? ENABLE : DISABLE)
+
+/** @brief  Change uint32_t variable form big endian to little endian.
+  * @param  __DATA__ .uint32_t variable in big endian.
+  *         This parameter must be a number between Min_Data=0x00(uint32_t) and Max_Data=0xFFFFFFFF.
+  * @retval uint32_t variable in little endian.
+  */
+#define I3C_BIG_TO_LITTLE_ENDIAN(__DATA__) ((uint32_t)((((__DATA__) & 0xff000000U) >> 24) | \
+                                                       (((__DATA__) & 0x00ff0000U) >> 8)  | \
+                                                       (((__DATA__) & 0x0000ff00U) << 8)  | \
+                                                       (((__DATA__) & 0x000000ffU) << 24)))
+
+/* Private variables -------------------------------------------------------------------------------------------------*/
+/** @addtogroup  I3C_Private_Variables
+  * @{
+  */
+/* Structure containing address device and message type used for the private function I3C_Ctrl_IsDevice_Ready() */
+typedef struct
+{
+  uint8_t   Address;            /* Dynamic or Static target Address */
+  uint32_t  MessageType;        /* Message Type */
+
+} I3C_DeviceTypeDef;
+/**
+  * @}
+  */
+
+/* Private function prototypes ---------------------------------------------------------------------------------------*/
+/** @addtogroup I3C_Private_Functions
+  * @{
+  */
+static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks);
+
+static HAL_StatusTypeDef I3C_WaitOnDAAUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t timeout, uint32_t tickstart);
+static HAL_StatusTypeDef I3C_WaitOnFlagUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t flag, FlagStatus flagstatus,
+                                                    uint32_t timeout, uint32_t tickstart);
+static void I3C_TransmitByteTreatment(I3C_HandleTypeDef *hi3c);
+static void I3C_TransmitWordTreatment(I3C_HandleTypeDef *hi3c);
+static void I3C_ReceiveByteTreatment(I3C_HandleTypeDef *hi3c);
+static void I3C_ReceiveWordTreatment(I3C_HandleTypeDef *hi3c);
+static void I3C_ControlDataTreatment(I3C_HandleTypeDef *hi3c);
+static void I3C_ErrorTreatment(I3C_HandleTypeDef *hi3c);
+static void I3C_GetErrorSources(I3C_HandleTypeDef *hi3c);
+static void I3C_StateUpdate(I3C_HandleTypeDef *hi3c);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void I3C_DMAAbort(DMA_HandleTypeDef *hdma);
+static void I3C_DMAControlTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I3C_DMADataTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I3C_DMADataReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I3C_DMAError(DMA_HandleTypeDef *hdma);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static void I3C_Enable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest);
+static void I3C_Disable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest);
+static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option);
+static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c,
+                                     uint32_t           indexDesc,
+                                     uint32_t           txSize,
+                                     uint32_t           txCurrentIndex);
+static uint32_t I3C_FillTxBuffer_Private(I3C_HandleTypeDef *hi3c,
+                                         uint32_t           indexDesc,
+                                         uint32_t           txSize,
+                                         uint32_t           txCurrentIndex);
+static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *hi3c,
+                                                            uint8_t            counter,
+                                                            uint32_t           option);
+static HAL_StatusTypeDef I3C_Ctrl_IsDevice_Ready(I3C_HandleTypeDef *hi3c,
+                                                 const I3C_DeviceTypeDef *pDevice,
+                                                 uint32_t           trials,
+                                                 uint32_t           timeout);
+static void I3C_TreatErrorCallback(I3C_HandleTypeDef *hi3c);
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @addtogroup I3C_Exported_Functions I3C Exported Functions
+  * @{
+  */
+
+/** @defgroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions.
+  * @brief    I3C initialization and de-initialization functions
+  *
+@verbatim
+ =======================================================================================================================
+                              ##### Initialization and de-initialization functions #####
+ =======================================================================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and deinitialize the I3Cx peripheral:
+
+         (+) Users must implement HAL_I3C_MspInit() function in which they configure all related peripherals
+             resources (APB and Kernel CLOCK, GPIO, DMA, IT and NVIC).
+
+         (+) Call the function HAL_I3C_Init() to configure the bus characteristic depends on the device mode
+             with the selected configuration below:
+
+             (++) Controller mode, Serial source clock wave form configuration:
+                  (+++) SCL push pull low duration
+                  (+++) SCL I3C high duration
+                  (+++) SCL open drain low duration
+                  (+++) SCL I2C high duration
+
+             (++) Controller mode, Bus timing configuration:
+                  (+++) SDA hold time
+                  (+++) Wait time
+                  (+++) Bus free duration
+                  (+++) Bus available duration
+
+             (++) Target mode, Bus timing configuration:
+                  (+++) Bus available duration
+
+         (+) Call the function HAL_I3C_DeInit() to restore the default configuration of the selected I3Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I3C instance by activating the low-level hardware and configuring the bus
+  *         characteristic according to the specified parameters in the I3C_InitTypeDef.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Init(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t waveform_value;
+  uint32_t timing_value;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check the I3C state */
+    if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      /* Init the I3C Callback settings */
+      /* Legacy weak CtrlTxCpltCallback            */
+      hi3c->CtrlTxCpltCallback            = HAL_I3C_CtrlTxCpltCallback;
+      /* Legacy weak CtrlRxCpltCallback            */
+      hi3c->CtrlRxCpltCallback            = HAL_I3C_CtrlRxCpltCallback;
+      /* Legacy weak CtrlMultipleXferCpltCallback  */
+      hi3c->CtrlMultipleXferCpltCallback  = HAL_I3C_CtrlMultipleXferCpltCallback;
+      /* Legacy weak CtrlDAACpltCallback           */
+      hi3c->CtrlDAACpltCallback           = HAL_I3C_CtrlDAACpltCallback;
+      /* Legacy weak TgtReqDynamicAddrCallback     */
+      hi3c->TgtReqDynamicAddrCallback     = HAL_I3C_TgtReqDynamicAddrCallback;
+      /* Legacy weak TgtTxCpltCallback             */
+      hi3c->TgtTxCpltCallback             = HAL_I3C_TgtTxCpltCallback;
+      /* Legacy weak TgtRxCpltCallback             */
+      hi3c->TgtRxCpltCallback             = HAL_I3C_TgtRxCpltCallback;
+      /* Legacy weak TgtHotJoinCallback            */
+      hi3c->TgtHotJoinCallback            = HAL_I3C_TgtHotJoinCallback;
+      /* Legacy weak NotifyCallback                */
+      hi3c->NotifyCallback                = HAL_I3C_NotifyCallback;
+      /* Legacy weak ErrorCallback                 */
+      hi3c->ErrorCallback                 = HAL_I3C_ErrorCallback;
+      /* Legacy weak AbortCpltCallback             */
+      hi3c->AbortCpltCallback             = HAL_I3C_AbortCpltCallback;
+
+      /* Check on the MSP init callback */
+      if (hi3c->MspInitCallback == NULL)
+      {
+        /* Legacy weak MspInit  */
+        hi3c->MspInitCallback = HAL_I3C_MspInit;
+      }
+
+      /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+      hi3c->MspInitCallback(hi3c);
+#else
+      /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+      HAL_I3C_MspInit(hi3c);
+
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */
+    }
+
+    /* Update the I3C state to busy */
+    hi3c->State = HAL_I3C_STATE_BUSY;
+
+    /* Disable the selected I3C peripheral */
+    LL_I3C_Disable(hi3c->Instance);
+
+    /* Check on the I3C mode: initialization depends on the mode */
+    if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER)
+    {
+      /* Check the parameters */
+      assert_param(IS_I3C_SDAHOLDTIME_VALUE(hi3c->Init.CtrlBusCharacteristic.SDAHoldTime));
+      assert_param(IS_I3C_WAITTIME_VALUE(hi3c->Init.CtrlBusCharacteristic.WaitTime));
+
+      /* Set Controller mode */
+      LL_I3C_SetMode(hi3c->Instance, LL_I3C_MODE_CONTROLLER);
+
+      /*----------------- SCL signal waveform configuration : I3C timing register 0 (I3C_TIMINGR0) ------------------ */
+      /* Set the controller SCL waveform */
+      waveform_value = ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLPPLowDuration                                   |
+                        ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLI3CHighDuration << I3C_TIMINGR0_SCLH_I3C_Pos)  |
+                        ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLODLowDuration << I3C_TIMINGR0_SCLL_OD_Pos)     |
+                        ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SCLI2CHighDuration << I3C_TIMINGR0_SCLH_I2C_Pos));
+
+      LL_I3C_ConfigClockWaveForm(hi3c->Instance, waveform_value);
+
+      /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------ */
+      /* Set SDA hold time, activity state, bus free duration and bus available duration */
+      timing_value = ((uint32_t)hi3c->Init.CtrlBusCharacteristic.SDAHoldTime                                 |
+                      (uint32_t)hi3c->Init.CtrlBusCharacteristic.WaitTime                                    |
+                      ((uint32_t)hi3c->Init.CtrlBusCharacteristic.BusFreeDuration <<  I3C_TIMINGR1_FREE_Pos) |
+                      (uint32_t)hi3c->Init.CtrlBusCharacteristic.BusIdleDuration);
+
+      LL_I3C_SetCtrlBusCharacteristic(hi3c->Instance, timing_value);
+    }
+    else
+    {
+      /* Set target mode */
+      LL_I3C_SetMode(hi3c->Instance, LL_I3C_MODE_TARGET);
+
+      /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------ */
+      /* Set the number of kernel clocks cycles for the bus available condition time */
+      LL_I3C_SetAvalTiming(hi3c->Instance, hi3c->Init.TgtBusCharacteristic.BusAvailableDuration);
+    }
+
+    /* Enable the selected I3C peripheral */
+    LL_I3C_Enable(hi3c->Instance);
+
+    hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+    /* Update I3C state */
+    hi3c->State = HAL_I3C_STATE_READY;
+    hi3c->PreviousState = HAL_I3C_STATE_READY;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the I3C peripheral.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_DeInit(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+
+    /* Update the I3C state to busy */
+    hi3c->State = HAL_I3C_STATE_BUSY;
+
+    /* Disable the selected I3C peripheral */
+    LL_I3C_Disable(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Check on the MSP init callback */
+    if (hi3c->MspDeInitCallback == NULL)
+    {
+      /* Legacy weak MspDeInit  */
+      hi3c->MspDeInitCallback = HAL_I3C_MspDeInit;
+    }
+
+    /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+    hi3c->MspDeInitCallback(hi3c);
+#else
+    /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+    HAL_I3C_MspDeInit(hi3c);
+
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */
+
+    /* Update the I3C Error code, state and mode */
+    hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+    hi3c->State         = HAL_I3C_STATE_RESET;
+    hi3c->PreviousState = HAL_I3C_STATE_RESET;
+    hi3c->Mode          = HAL_I3C_MODE_NONE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief Initialize the I3C MSP.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_MspInit(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I3C_MspInit could be implemented in the user file */
+}
+
+/**
+  * @brief DeInitialize the I3C MSP.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I3C_MspDeInit could be implemented in the user file */
+}
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Exported_Functions_Group2 Interrupt and callback functions.
+  * @brief    I3C interrupt and callback functions.
+  *
+@verbatim
+ =======================================================================================================================
+                                    ##### Interrupt and callback functions #####
+ =======================================================================================================================
+    [..]  This subsection provides a set of functions allowing to manage callbacks and interrupts request:
+
+         (+) Register/Unregister callback function:
+             (++) Call the function HAL_I3C_RegisterCallback() to register an I3C user callback.
+             (++) Call the function HAL_I3C_RegisterNotifyCallback() to register an I3C user notification callback.
+             (++) Call the function HAL_I3C_RegisterDynamicAddrCallback() to register an I3C user address callback.
+             (++) Call the function HAL_I3C_RegisterHotJoinCallback() to register an I3C user hot join callback.
+             (++) Call the function HAL_I3C_UnRegisterCallback() to unregister an I3C user callback.
+
+         (+) Notification management function:
+             (++) Call the function HAL_I3C_ActivateNotification() to activate the I3C notifications.
+             (++) Call the function HAL_I3C_DeactivateNotification() to deactivate the I3C notifications.
+
+         (+) Controller callback functions:
+             (++) Users must implement HAL_I3C_CtrlTxCpltCallback() function when the transmission of private data or
+                  Tx CCC transfer is completed.
+             (++) Users must implement HAL_I3C_CtrlRxCpltCallback() function when the reception of private data or
+                  Rx CCC transfer is completed.
+             (++) Users must implement HAL_I3C_CtrlMultipleXferCpltCallback() function when the multiple
+                  transfer of CCC, I3C private or I2C transfer is completed.
+             (++) Users must implement HAL_I3C_CtrlDAACpltCallback() function when Dynamic Address Assignment
+                  procedure is completed.
+             (++) Users must implement HAL_I3C_TgtReqDynamicAddrCallback() function in the controller application
+                  when a target sent its payload to the controller during Dynamic Address Assignment procedure.
+
+         (+) Target callback functions:
+             (++) Users must implement HAL_I3C_TgtTxCpltCallback() function when the transmission of private
+                  data is completed.
+             (++) Users must implement HAL_I3C_TgtRxCpltCallback() function when the reception of private
+                  data is completed.
+             (++) Users must implement HAL_I3C_TgtHotJoinCallback() function when a target hot join process
+                  is completed.
+
+         (+) Common callback functions:
+             (++) Users must implement HAL_I3C_NotifyCallback() function when the device receives
+                  an asynchronous event like IBI, a Hot-join, CCC command for target...
+             (++) Users must implement HAL_I3C_AbortCpltCallback() function when an abort process is completed.
+             (++) Users must implement HAL_I3C_ErrorCallback() function when an error is occurred.
+
+         (+) Interrupt and event function:
+             (++) Call the function HAL_I3C_ER_IRQHandler() in the ISR file to handle I3C error interrupts request.
+             (++) Call the function HAL_I3C_EV_IRQHandler() in the ISR file to handle I3C event interrupts request.
+@endverbatim
+  * @{
+  */
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User I3C Callback to be used instead of the weak predefined callback.
+  * @note   The HAL_I3C_RegisterCallback() may be called before HAL_I3C_Init() in HAL_I3C_STATE_RESET
+  *         to register callbacks for HAL_I3C_MSPINIT_CB_ID and HAL_I3C_MSPDEINIT_CB_ID
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  callbackID : [IN]  ID of the callback to be registered.
+  *                            This parameter can be one of the following values:
+  *                            @arg @ref HAL_I3C_CTRL_TX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_CTRL_RX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_CTRL_DAA_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_TGT_TX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_TGT_RX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_ERROR_CB_ID
+  *                            @arg @ref HAL_I3C_ABORT_CB_ID
+  *                            @arg @ref HAL_I3C_MSPINIT_CB_ID
+  *                            @arg @ref HAL_I3C_MSPDEINIT_CB_ID
+  * @param  pCallback  : [IN]  Pointer to the Callback function.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_RegisterCallback(I3C_HandleTypeDef *hi3c,
+                                           HAL_I3C_CallbackIDTypeDef callbackID,
+                                           pI3C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the user callback allocation */
+    if (pCallback == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else if (HAL_I3C_STATE_READY == hi3c->State)
+    {
+      switch (callbackID)
+      {
+        case HAL_I3C_CTRL_TX_COMPLETE_CB_ID :
+          hi3c->CtrlTxCpltCallback = pCallback;
+          break;
+
+        case HAL_I3C_CTRL_RX_COMPLETE_CB_ID :
+          hi3c->CtrlRxCpltCallback = pCallback;
+          break;
+
+        case HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID :
+          hi3c->CtrlMultipleXferCpltCallback = pCallback;
+          break;
+
+        case HAL_I3C_CTRL_DAA_COMPLETE_CB_ID :
+          hi3c->CtrlDAACpltCallback = pCallback;
+          break;
+
+        case HAL_I3C_TGT_TX_COMPLETE_CB_ID :
+          hi3c->TgtTxCpltCallback = pCallback;
+          break;
+
+        case HAL_I3C_TGT_RX_COMPLETE_CB_ID :
+          hi3c->TgtRxCpltCallback = pCallback;
+          break;
+
+        case HAL_I3C_ERROR_CB_ID :
+          hi3c->ErrorCallback = pCallback;
+          break;
+
+        case HAL_I3C_ABORT_CB_ID :
+          hi3c->AbortCpltCallback = pCallback;
+          break;
+
+        case HAL_I3C_MSPINIT_CB_ID :
+          hi3c->MspInitCallback = pCallback;
+          break;
+
+        case HAL_I3C_MSPDEINIT_CB_ID :
+          hi3c->MspDeInitCallback = pCallback;
+          break;
+
+        default :
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK;
+          status =  HAL_ERROR;
+          break;
+      }
+    }
+    else if (HAL_I3C_STATE_RESET == hi3c->State)
+    {
+      switch (callbackID)
+      {
+        case HAL_I3C_MSPINIT_CB_ID :
+          hi3c->MspInitCallback = pCallback;
+          break;
+
+        case HAL_I3C_MSPDEINIT_CB_ID :
+          hi3c->MspDeInitCallback = pCallback;
+          break;
+
+        default :
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK;
+          status =  HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status =  HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User I3C Notify Callback to be used instead of the weak predefined callback.
+  * @param  hi3c            : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                 information for the specified I3C.
+  * @param  pNotifyCallback : [IN]  Pointer to the Callback function.
+  * @retval HAL Status      :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_RegisterNotifyCallback(I3C_HandleTypeDef *hi3c, pI3C_NotifyCallbackTypeDef pNotifyCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the user callback allocation */
+    if (pNotifyCallback == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else if (HAL_I3C_STATE_READY == hi3c->State)
+    {
+      hi3c->NotifyCallback = pNotifyCallback;
+    }
+    else
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User I3C dynamic address Callback to be used instead of the weak predefined callback.
+  * @param  hi3c                : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                     information for the specified I3C.
+  * @param  pTgtReqAddrCallback : [IN]  Pointer to the Callback function.
+  * @retval HAL Status          :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_RegisterTgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c,
+                                                            pI3C_TgtReqDynamicAddrCallbackTypeDef pTgtReqAddrCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the user callback allocation */
+    if (pTgtReqAddrCallback == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else if (HAL_I3C_STATE_READY == hi3c->State)
+    {
+      hi3c->TgtReqDynamicAddrCallback = pTgtReqAddrCallback;
+    }
+    else
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User I3C hot join Callback to be used instead of the weak predefined callback.
+  * @param  hi3c                : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                     information for the specified I3C.
+  * @param  pTgtHotJoinCallback : [IN]  Pointer to the Callback function.
+  * @retval HAL Status          :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_RegisterTgtHotJoinCallback(I3C_HandleTypeDef *hi3c,
+                                                     pI3C_TgtHotJoinCallbackTypeDef pTgtHotJoinCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the user callback allocation */
+    if (pTgtHotJoinCallback == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else if (HAL_I3C_STATE_READY == hi3c->State)
+    {
+      hi3c->TgtHotJoinCallback = pTgtHotJoinCallback;
+    }
+    else
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a user I3C Callback.
+  *         The I3C callback is redirected to the weak predefined callback
+  * @note   The HAL_I3C_UnRegisterCallback() may be called before HAL_I3C_Init() in HAL_I3C_STATE_RESET
+  *         to un-register callbacks for HAL_I3C_MSPINIT_CB_ID and HAL_I3C_MSPDEINIT_CB_ID
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  callbackID : [IN]  ID of the callback to be unregistered.
+  *                            This parameter can be one of the following values:
+  *                            @arg @ref HAL_I3C_CTRL_TX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_CTRL_RX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_CTRL_DAA_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID
+  *                            @arg @ref HAL_I3C_TGT_TX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_TGT_RX_COMPLETE_CB_ID
+  *                            @arg @ref HAL_I3C_TGT_HOTJOIN_CB_ID
+  *                            @arg @ref HAL_I3C_NOTIFY_CB_ID
+  *                            @arg @ref HAL_I3C_ERROR_CB_ID
+  *                            @arg @ref HAL_I3C_ABORT_CB_ID
+  *                            @arg @ref HAL_I3C_MSPINIT_CB_ID
+  *                            @arg @ref HAL_I3C_MSPDEINIT_CB_ID
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_CallbackIDTypeDef callbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (HAL_I3C_STATE_READY == hi3c->State)
+    {
+      switch (callbackID)
+      {
+        case HAL_I3C_CTRL_TX_COMPLETE_CB_ID :
+          /* Legacy weak CtrlTxCpltCallback               */
+          hi3c->CtrlTxCpltCallback = HAL_I3C_CtrlTxCpltCallback;
+          break;
+
+        case HAL_I3C_CTRL_RX_COMPLETE_CB_ID :
+          /* Legacy weak CtrlRxCpltCallback               */
+          hi3c->CtrlRxCpltCallback = HAL_I3C_CtrlRxCpltCallback;
+          break;
+
+        case HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID :
+          /* Legacy weak CtrlMultipleXferCpltCallback     */
+          hi3c->CtrlMultipleXferCpltCallback = HAL_I3C_CtrlMultipleXferCpltCallback;
+          break;
+
+        case HAL_I3C_CTRL_DAA_COMPLETE_CB_ID :
+          /* Legacy weak CtrlDAACpltCallback              */
+          hi3c->CtrlDAACpltCallback = HAL_I3C_CtrlDAACpltCallback;
+          break;
+
+        case HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID :
+          /*Legacy weak TgtReqDynamicAddrCallback          */
+          hi3c->TgtReqDynamicAddrCallback = HAL_I3C_TgtReqDynamicAddrCallback;
+          break;
+
+        case HAL_I3C_TGT_TX_COMPLETE_CB_ID :
+          /* Legacy weak TgtTxCpltCallback                 */
+          hi3c->TgtTxCpltCallback = HAL_I3C_TgtTxCpltCallback;
+          break;
+
+        case HAL_I3C_TGT_RX_COMPLETE_CB_ID :
+          /* Legacy weak TgtRxCpltCallback                 */
+          hi3c->TgtRxCpltCallback = HAL_I3C_TgtRxCpltCallback;
+          break;
+
+        case HAL_I3C_TGT_HOTJOIN_CB_ID :
+          /* Legacy weak TgtHotJoinCallback                */
+          hi3c->TgtHotJoinCallback = HAL_I3C_TgtHotJoinCallback;
+          break;
+
+        case HAL_I3C_NOTIFY_CB_ID :
+          /* Legacy weak NotifyCallback                    */
+          hi3c->NotifyCallback = HAL_I3C_NotifyCallback;
+          break;
+
+        case HAL_I3C_ERROR_CB_ID :
+          /* Legacy weak ErrorCallback                     */
+          hi3c->ErrorCallback = HAL_I3C_ErrorCallback;
+          break;
+
+        case HAL_I3C_ABORT_CB_ID :
+          /* Legacy weak AbortCpltCallback                 */
+          hi3c->AbortCpltCallback = HAL_I3C_AbortCpltCallback;
+          break;
+
+        case HAL_I3C_MSPINIT_CB_ID :
+          /* Legacy weak MspInit                           */
+          hi3c->MspInitCallback = HAL_I3C_MspInit;
+          break;
+
+        case HAL_I3C_MSPDEINIT_CB_ID :
+          /* Legacy weak MspDeInit                         */
+          hi3c->MspDeInitCallback = HAL_I3C_MspDeInit;
+          break;
+
+        default :
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK;
+          status =  HAL_ERROR;
+          break;
+      }
+    }
+    else if (HAL_I3C_STATE_RESET == hi3c->State)
+    {
+      switch (callbackID)
+      {
+        case HAL_I3C_MSPINIT_CB_ID :
+          /* Legacy weak MspInit                           */
+          hi3c->MspInitCallback = HAL_I3C_MspInit;
+          break;
+
+        case HAL_I3C_MSPDEINIT_CB_ID :
+          /* Legacy weak MspDeInit                         */
+          hi3c->MspDeInitCallback = HAL_I3C_MspDeInit;
+          break;
+
+        default :
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_CALLBACK;
+          status =  HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status =  HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+/**
+  * @brief  This function permits to activate the I3C notifications.
+  * @param  hi3c          : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                               information for the specified I3C.
+  * @param  pXferData     : [IN/OUT] Pointer to an I3C_XferTypeDef structure that contains the reception buffer to
+  *                               retrieve data during broadcast CCC DEFTGTS and DEFGRPA when Target mode only.
+  * @param  interruptMask : [IN]  Parameter indicates which interrupts will be enabled.
+  *                               This parameter can be any combination of @arg I3C_TARGET_INTERRUPT when
+  *                               the I3C is in target mode or a combination of @arg I3C_CONTROLLER_INTERRUPT
+  *                               when it is in controller mode.
+  * @retval HAL Status    :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData,
+                                               uint32_t interruptMask)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+    assert_param(IS_I3C_INTERRUPTMASK(hi3c->Mode, interruptMask));
+
+    /* Check the I3C state and mode */
+    if ((hi3c->State == HAL_I3C_STATE_RESET) ||
+        ((hi3c->Mode != HAL_I3C_MODE_CONTROLLER) && (hi3c->Mode != HAL_I3C_MODE_TARGET)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C mode */
+    else if ((hi3c->Mode == HAL_I3C_MODE_TARGET) &&
+             ((interruptMask & (HAL_I3C_IT_DEFIE | HAL_I3C_IT_GRPIE)) != 0U) &&
+             (pXferData == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check the I3C mode */
+      if (hi3c->Mode == HAL_I3C_MODE_TARGET)
+      {
+        if ((interruptMask & (HAL_I3C_IT_DEFIE | HAL_I3C_IT_GRPIE)) != 0U)
+        {
+          hi3c->pXferData = pXferData;
+          hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size;
+
+          /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+          if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+          {
+            /* Set byte treatment function pointer */
+            hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+          }
+          else
+          {
+            /* Set word treatment function pointer */
+            hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+          }
+        }
+        /* Store the target event treatment function */
+        hi3c->XferISR = I3C_Tgt_Event_ISR;
+      }
+      else
+      {
+        /* Store the controller event treatment function */
+        hi3c->XferISR = I3C_Ctrl_Event_ISR;
+      }
+
+      /* Update handle parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      hi3c->State         = HAL_I3C_STATE_LISTEN;
+      hi3c->PreviousState = HAL_I3C_STATE_LISTEN;
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+      /* Enable selected notifications */
+      I3C_Enable_IRQ(hi3c, (interruptMask | I3C_XFER_LISTEN_IT));
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function permits to deactivate the I3C notifications.
+  * @param  hi3c          : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                               information for the specified I3C.
+  * @param  interruptMask : [IN]  Parameter indicates which interrupts will be disabled.
+  *                               This parameter can be any combination of @arg I3C_TARGET_INTERRUPT when
+  *                               the I3C is in target mode or a combination of @arg I3C_CONTROLLER_INTERRUPT
+  *                               when it is in controller mode.
+  * @retval HAL Status    :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_DeactivateNotification(I3C_HandleTypeDef *hi3c, uint32_t interruptMask)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance parameter */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+
+    /* Check on the State */
+    if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Disable selected notifications */
+      I3C_Disable_IRQ(hi3c, (interruptMask | I3C_XFER_LISTEN_IT));
+
+      if (READ_REG(hi3c->Instance->IER) == 0U)
+      {
+        /* Update the XferISR pointer */
+        hi3c->XferISR = NULL;
+
+        /* Update I3C state */
+        hi3c->State         = HAL_I3C_STATE_READY;
+        hi3c->PreviousState = HAL_I3C_STATE_READY;
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Controller Transmission Complete callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_CtrlTxCpltCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_CtrlTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Controller Reception Complete callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_CtrlRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Controller multiple Direct CCC Command, I3C private or I2C transfer Complete callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_CtrlMultipleXferCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Controller dynamic address assignment Complete callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_CtrlDAACpltCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_CtrlDAACpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Target Request Dynamic Address callback.
+  * @param  hi3c          : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                              for the specified I3C.
+  * @param  targetPayload : [IN] Parameter indicates the target payload.
+  * @retval None
+  */
+__weak void HAL_I3C_TgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, uint64_t targetPayload)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+  UNUSED(targetPayload);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_TgtReqDynamicAddrCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Target Transmission Complete callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_TgtTxCpltCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_TgtTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Target Reception Complete callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_TgtRxCpltCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_TgtRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Target Hot join process Complete callback.
+  * @param  hi3c           : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                               information for the specified I3C.
+  * @param  dynamicAddress : [IN] The returned dynamic address value after the hot join process.
+  * @retval None
+  */
+__weak void HAL_I3C_TgtHotJoinCallback(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+  UNUSED(dynamicAddress);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_TgtHotJoinCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Target/Controller Notification event callback.
+  * @param  hi3c     : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                         for the specified I3C.
+  * @param  eventId  : [IN] Parameter indicates which notification is signaled.
+  *                         It can be a combination value of @ref HAL_I3C_Notification_ID_definition.
+  * @retval None
+  */
+__weak void HAL_I3C_NotifyCallback(I3C_HandleTypeDef *hi3c, uint32_t eventId)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+  UNUSED(eventId);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_NotifyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Abort complete callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_AbortCpltCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                     for the specified I3C.
+  * @retval None
+  */
+__weak void HAL_I3C_ErrorCallback(I3C_HandleTypeDef *hi3c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi3c);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I3C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function handles I3C error interrupt request.
+  * @param  hi3c : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                      for the specified I3C.
+  * @retval None
+  */
+void HAL_I3C_ER_IRQHandler(I3C_HandleTypeDef *hi3c)
+{
+  uint32_t it_flag   = READ_REG(hi3c->Instance->EVR);
+  uint32_t it_source = READ_REG(hi3c->Instance->IER);
+
+  /* Check on the error interrupt flag and source */
+  if ((I3C_CHECK_FLAG(it_flag, HAL_I3C_FLAG_ERRF) != RESET) &&
+      (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_ERRIE) != RESET))
+  {
+    /* Clear the error flag */
+    LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+    if (hi3c->State != HAL_I3C_STATE_ABORT)
+    {
+      /* Get error sources */
+      I3C_GetErrorSources(hi3c);
+    }
+
+    /* Errors treatment */
+    I3C_ErrorTreatment(hi3c);
+  }
+}
+
+/**
+  * @brief  This function handles I3C event interrupt request.
+  * @param  hi3c : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                      for the specified I3C.
+  * @retval None
+  */
+void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  uint32_t it_flags   = READ_REG(hi3c->Instance->EVR);
+  uint32_t it_sources = READ_REG(hi3c->Instance->IER);
+
+  uint32_t it_masks   = (uint32_t)(it_flags & it_sources);
+
+  /* I3C events treatment */
+  if (hi3c->XferISR != NULL)
+  {
+    hi3c->XferISR(hi3c, it_masks);
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Exported_Functions_Group3 Configuration functions.
+  * @brief    I3C configuration functions.
+  *
+@verbatim
+ =======================================================================================================================
+                                       ##### Configuration functions #####
+ =======================================================================================================================
+    [..]  This subsection provides a set of functions allowing to configure the I3C instances.
+
+         (+) Call the function HAL_I3C_Ctrl_BusCharacteristicConfig() to modify the controller Bus Characteristics
+             after initialize the bus through HAL_I3C_Init.
+
+         (+) Call the function HAL_I3C_Tgt_BusCharacteristicConfig() to modify the target Bus Characteristics
+             after initialize the bus through HAL_I3C_Init.
+
+         (+) Call the function HAL_I3C_SetConfigFifo() to set FIFOs configuration (enabled FIFOs and
+             threshold level) with the selected parameters in the configuration structure I3C_FifoConfTypeDef.
+
+         (+) Call the function HAL_I3C_Ctrl_Config() to configure the I3C Controller instances with the selected
+             parameters in the configuration structure I3C_CtrlConfTypeDef.
+             This function is called only when mode is Controller.
+
+         (+) Call the function HAL_I3C_Tgt_Config() to configure the I3C Target instances with the selected
+             parameters in the configuration structure I3C_TgtConfTypeDef.
+             This function is called only when mode is Target.
+
+         (+) Call the function HAL_I3C_Ctrl_ConfigBusDevices() to configure Hardware device characteristics register
+             with Devices capabilities present on the Bus.
+             All different characteristics must be fill through structure I3C_DeviceConfTypeDef.
+             This function is called only when mode is Controller.
+
+         (+) Call the function HAL_I3C_AddDescToFrame() to prepare the full transfer usecase in a Controller transfer
+             descriptor which contained different buffer pointers and their associated size through I3C_XferTypeDef.
+             This function must be called before initiate any communication transfer.
+         (+) Call the function HAL_I3C_Ctrl_SetConfigResetPattern() to configure the insertion of the reset pattern
+             at the end of a Frame.
+         (+) Call the function HAL_I3C_Ctrl_GetConfigResetPattern() to get the current reset pattern configuration
+
+     [..]
+       (@) Users must call all above functions after I3C initialization.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the Controller Bus characterics.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pConfig    : [IN]  Pointer to an LL_I3C_CtrlBusConfTypeDef structure contains controller bus configuration.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c,
+                                                       const LL_I3C_CtrlBusConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t waveform_value;
+  uint32_t timing_value;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check on user parameters */
+    if (pConfig == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C state and mode */
+    else if ((hi3c->State != HAL_I3C_STATE_READY) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_I3C_SDAHOLDTIME_VALUE(pConfig->SDAHoldTime));
+      assert_param(IS_I3C_WAITTIME_VALUE(pConfig->WaitTime));
+
+      /* Disable the selected I3C peripheral */
+      LL_I3C_Disable(hi3c->Instance);
+
+      /*----------------- SCL signal waveform configuration : I3C timing register 0 (I3C_TIMINGR0) ------------------ */
+      /* Set the controller SCL waveform */
+      waveform_value = ((uint32_t)pConfig->SCLPPLowDuration                                    |
+                        ((uint32_t)pConfig->SCLI3CHighDuration << I3C_TIMINGR0_SCLH_I3C_Pos)   |
+                        ((uint32_t)pConfig->SCLODLowDuration << I3C_TIMINGR0_SCLL_OD_Pos)      |
+                        ((uint32_t)pConfig->SCLI2CHighDuration << I3C_TIMINGR0_SCLH_I2C_Pos));
+
+      LL_I3C_ConfigClockWaveForm(hi3c->Instance, waveform_value);
+
+      /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------ */
+      /* Set SDA hold time, activity state, bus free duration and bus available duration */
+      timing_value = ((uint32_t)pConfig->SDAHoldTime                                 |
+                      (uint32_t)pConfig->WaitTime                                    |
+                      ((uint32_t)pConfig->BusFreeDuration <<  I3C_TIMINGR1_FREE_Pos) |
+                      (uint32_t)pConfig->BusIdleDuration);
+
+      LL_I3C_SetCtrlBusCharacteristic(hi3c->Instance, timing_value);
+
+      /* Enable the selected I3C peripheral */
+      LL_I3C_Enable(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the target Bus characterics.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pConfig    : [IN]  Pointer to an LL_I3C_TgtBusConfTypeDef structure contains target bus configuration.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c,
+                                                      const LL_I3C_TgtBusConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check on user parameters */
+    if (pConfig == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check the instance and the mode parameters */
+      assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+      assert_param(IS_I3C_MODE(hi3c->Mode));
+
+      /* Check the I3C state and mode */
+      if ((hi3c->State != HAL_I3C_STATE_READY) || (hi3c->Mode != HAL_I3C_MODE_TARGET))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Disable the selected I3C peripheral */
+        LL_I3C_Disable(hi3c->Instance);
+
+        /*------------------ Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ---------------------------- */
+        /* Set the number of kernel clocks cycles for the bus available condition time */
+        LL_I3C_SetAvalTiming(hi3c->Instance, pConfig->BusAvailableDuration);
+
+        /* Enable the selected I3C peripheral */
+        LL_I3C_Enable(hi3c->Instance);
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set I3C FIFOs configuration.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pConfig    : [IN]  Pointer to an I3C_FifoConfTypeDef structure contains FIFOs configuration.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_SetConfigFifo(I3C_HandleTypeDef *hi3c, const I3C_FifoConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cfgr_value;
+  uint32_t cfgr_mask;
+
+  /* Check the I3C handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check on user parameters */
+    if (pConfig == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C state */
+    else if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check the instance and the mode parameters */
+      assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+      assert_param(IS_I3C_MODE(hi3c->Mode));
+
+      /* Check configuration parameters */
+      assert_param(IS_I3C_TXFIFOTHRESHOLD_VALUE(pConfig->TxFifoThreshold));
+      assert_param(IS_I3C_RXFIFOTHRESHOLD_VALUE(pConfig->RxFifoThreshold));
+
+      /* Set Tx and Rx Fifo threshold */
+      cfgr_value = (pConfig->TxFifoThreshold | pConfig->RxFifoThreshold);
+      cfgr_mask  = (I3C_CFGR_TXTHRES | I3C_CFGR_RXTHRES);
+
+      /* Check on the I3C mode: Control and status FIFOs available only with controller mode */
+      if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER)
+      {
+        /* Check configuration parameters */
+        assert_param(IS_I3C_CONTROLFIFOSTATE_VALUE(pConfig->ControlFifo));
+        assert_param(IS_I3C_STATUSFIFOSTATE_VALUE(pConfig->StatusFifo));
+
+        /* Set Control and Status Fifo states */
+        cfgr_value |= (pConfig->StatusFifo | pConfig->ControlFifo);
+        cfgr_mask  |= (I3C_CFGR_TMODE | I3C_CFGR_SMODE);
+      }
+
+      /* Set configuration in the CFGR register */
+      MODIFY_REG(hi3c->Instance->CFGR, cfgr_mask, cfgr_value);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set I3C controller configuration.
+  * @note   This function is called only when the I3C instance is initialized as controller.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pConfig    : [IN]  Pointer to an I3C_CtrlConfTypeDef structure that contains controller configuration.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t timing2_value;
+  uint32_t cfgr_value;
+
+  /* Check the I3C handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check on user parameters */
+    if (pConfig == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C state and mode */
+    else if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check configuration parameters values */
+      assert_param(IS_I3C_DYNAMICADDRESS_VALUE(pConfig->DynamicAddr));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HighKeeperSDA));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HotJoinAllowed));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->ACKStallState));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->CCCStallState));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->TxStallState));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->RxStallState));
+
+      /* Disable the selected I3C peripheral */
+      LL_I3C_Disable(hi3c->Instance);
+
+      /* Calculate value to be written in timing register 2 */
+      timing2_value = (((uint32_t)pConfig->StallTime << I3C_TIMINGR2_STALL_Pos)      |
+                       ((uint32_t)pConfig->ACKStallState << I3C_TIMINGR2_STALLA_Pos) |
+                       ((uint32_t)pConfig->CCCStallState << I3C_TIMINGR2_STALLC_Pos) |
+                       ((uint32_t)pConfig->TxStallState << I3C_TIMINGR2_STALLD_Pos)  |
+                       ((uint32_t)pConfig->RxStallState << I3C_TIMINGR2_STALLT_Pos));
+
+      /* Set value in timing 2 register */
+      WRITE_REG(hi3c->Instance->TIMINGR2, timing2_value);
+
+      /* Calculate value to be written in CFGR register */
+      cfgr_value = (((uint32_t)pConfig->HighKeeperSDA << I3C_CFGR_HKSDAEN_Pos) |
+                    ((uint32_t)pConfig->HotJoinAllowed << I3C_CFGR_HJACK_Pos));
+
+      /* Set hot join acknowledge and high keeper values */
+      MODIFY_REG(hi3c->Instance->CFGR, I3C_CFGR_HKSDAEN | I3C_CFGR_HJACK, cfgr_value);
+
+      /* Set dynamic address value */
+      LL_I3C_SetOwnDynamicAddress(hi3c->Instance, pConfig->DynamicAddr);
+
+      /* Validate the controller dynamic address */
+      LL_I3C_EnableOwnDynAddress(hi3c->Instance);
+
+      /* Enable the selected I3C peripheral */
+      LL_I3C_Enable(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set I3C target configuration.
+  * @note   This function is called only when the I3C instance is initialized as target.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pConfig    : [IN]  Pointer to an I3C_TgtConfTypeDef structure that contains target configuration.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Config(I3C_HandleTypeDef *hi3c, const I3C_TgtConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t getmxdsr_value;
+  uint32_t maxrlr_value;
+  uint32_t crccapr_value;
+  uint32_t bcr_value;
+  uint32_t devr0_value;
+
+  /* Check the I3C handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check on user parameters */
+    if (pConfig == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C state and mode */
+    else if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_TARGET))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check configuration parameters values */
+      assert_param(IS_I3C_HANDOFFACTIVITYSTATE_VALUE(pConfig->HandOffActivityState));
+      assert_param(IS_I3C_TSCOTIME_VALUE(pConfig->DataTurnAroundDuration));
+      assert_param(IS_I3C_MAXSPEEDDATA_VALUE(pConfig->MaxDataSpeed));
+      assert_param(IS_I3C_IBIPAYLOADSIZE_VALUE(pConfig->IBIPayloadSize));
+      assert_param(IS_I3C_MIPIIDENTIFIER_VALUE(pConfig->MIPIIdentifier));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HandOffDelay));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->GroupAddrCapability));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->PendingReadMDB));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->IBIPayload));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->MaxSpeedLimitation));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->CtrlCapability));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->IBIRequest));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->CtrlRoleRequest));
+      assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pConfig->HotJoinRequest));
+
+      /* Disable the selected I3C peripheral */
+      LL_I3C_Disable(hi3c->Instance);
+
+      /* Calculate value to be written in the GETMXDSR register */
+      getmxdsr_value = (pConfig->HandOffActivityState | pConfig->MaxDataSpeed | pConfig->DataTurnAroundDuration |
+                        ((uint32_t)pConfig->MaxReadTurnAround << I3C_GETMXDSR_RDTURN_Pos));
+
+      /* Set value in GETMXDSR register */
+      WRITE_REG(hi3c->Instance->GETMXDSR, getmxdsr_value);
+
+      /* Calculate value to be written in MAXRLR register */
+      maxrlr_value = (pConfig->IBIPayloadSize | (pConfig->MaxReadDataSize & I3C_MAXRLR_MRL));
+
+      /* Set payload size and max read data size in MAXRLR register */
+      WRITE_REG(hi3c->Instance->MAXRLR, maxrlr_value);
+
+      /* Set max write data size in MAXWLR register */
+      LL_I3C_SetMaxWriteLength(hi3c->Instance, pConfig->MaxWriteDataSize);
+
+      /* Set MIPI identifier value in EPIDR register */
+      LL_I3C_SetMIPIInstanceID(hi3c->Instance, pConfig->MIPIIdentifier);
+
+      /* Set identifier value in DCR register */
+      LL_I3C_SetDeviceCharacteristics(hi3c->Instance, pConfig->Identifier);
+
+      /* Calculate value to be written in CRCCAPR register */
+      crccapr_value = (((uint32_t)pConfig->HandOffDelay << I3C_CRCAPR_CAPDHOFF_Pos) |
+                       ((uint32_t)pConfig->GroupAddrCapability << I3C_CRCAPR_CAPGRP_Pos));
+
+      /* Set hand off dealy and group address capability in CRCCAPR register */
+      WRITE_REG(hi3c->Instance->CRCAPR, crccapr_value);
+
+      /* Set pending read MDB notification value in GETCAPR register */
+      LL_I3C_SetPendingReadMDB(hi3c->Instance, ((uint32_t)pConfig->PendingReadMDB << I3C_GETCAPR_CAPPEND_Pos));
+
+      /* Calculate value to be written in BCR register */
+      bcr_value = (((uint32_t)pConfig->MaxSpeedLimitation << I3C_BCR_BCR0_Pos) |
+                   ((uint32_t)pConfig->IBIPayload << I3C_BCR_BCR2_Pos)         |
+                   ((uint32_t)pConfig->CtrlCapability << I3C_BCR_BCR6_Pos));
+
+      /* Set control capability, IBI payload support and max speed limitation in BCR register */
+      WRITE_REG(hi3c->Instance->BCR, bcr_value);
+
+      /* Calculate value to be written in CFGR register */
+      devr0_value = (((uint32_t)pConfig->IBIRequest << I3C_DEVR0_IBIEN_Pos)     |
+                     ((uint32_t)pConfig->CtrlRoleRequest << I3C_DEVR0_CREN_Pos) |
+                     ((uint32_t)pConfig->HotJoinRequest << I3C_DEVR0_HJEN_Pos));
+
+      /* Set IBI request, control role request and hot join request in DEVR0 register */
+      MODIFY_REG(hi3c->Instance->DEVR0, (I3C_DEVR0_HJEN | I3C_DEVR0_IBIEN | I3C_DEVR0_CREN), devr0_value);
+
+      /* Enable the selected I3C peripheral */
+      LL_I3C_Enable(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set I3C bus devices configuration.
+  * @note   This function is called only when the I3C instance is initialized as controller.
+  *         This function can be called by the controller application to help the automatic treatment when target have
+  *         capability of IBI and/or Control-Role.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pDesc      : [IN]  Pointer to an I3C_DeviceConfTypeDef descriptor that contains the bus devices
+  *                            configurations.
+  * @param  nbDevice   : [IN]  Value specifies the number of devices to be treated.
+  *                            This parameter must be a number between Min_Data=1U and Max_Data=4U.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef           *hi3c,
+                                                const I3C_DeviceConfTypeDef *pDesc,
+                                                uint8_t                      nbDevice)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t write_value;
+
+  /* Check the I3C handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check on user parameters */
+    if (pDesc == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C state and mode */
+    else if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check the instance and the mode parameters */
+      assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+      assert_param(IS_I3C_MODE(hi3c->Mode));
+      assert_param(IS_I3C_DEVICE_VALUE(nbDevice));
+
+      /* Loop on the nbDevice to be treated */
+      for (uint32_t index = 0U; index < nbDevice; index++)
+      {
+        /* Check configuration parameters values */
+        assert_param(IS_I3C_DEVICE_VALUE(pDesc[index].DeviceIndex));
+        assert_param(IS_I3C_DYNAMICADDRESS_VALUE(pDesc[index].TargetDynamicAddr));
+        assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].IBIAck));
+        assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].CtrlRoleReqAck));
+        assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].CtrlStopTransfer));
+        assert_param(IS_I3C_FUNCTIONALSTATE_VALUE(pDesc[index].IBIPayload));
+
+        /* Set value to be written */
+        write_value = (((uint32_t)pDesc[index].TargetDynamicAddr << I3C_DEVRX_DA_Pos)     |
+                       ((uint32_t)pDesc[index].IBIAck            << I3C_DEVRX_IBIACK_Pos) |
+                       ((uint32_t)pDesc[index].CtrlRoleReqAck    << I3C_DEVRX_CRACK_Pos)  |
+                       ((uint32_t)pDesc[index].CtrlStopTransfer  << I3C_DEVRX_SUSP_Pos)   |
+                       ((uint32_t)pDesc[index].IBIPayload        << I3C_DEVRX_IBIDEN_Pos));
+
+        /* Write configuration in the DEVRx register */
+        WRITE_REG(hi3c->Instance->DEVRX[(pDesc[index].DeviceIndex - 1U)], write_value);
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Add Private or CCC descriptor in the user data transfer controller descriptor.
+  * @note   This function must be called before initiate initiate any controller communication transfer. This function
+  *         help the preparation of the full transfer usecase in a transfer descriptor which contained different buffer
+  *         pointers and their associated size through I3C_XferTypeDef.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @param  hi3c          : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                               for the specified I3C.
+  * @param  pCCCDesc      : [IN]  Pointer to an I3C_CCCTypeDef structure that contains the CCC descriptor information.
+  * @param  pPrivateDesc  : [IN]  Pointer to an I3C_PrivateTypeDef structure that contains the transfer descriptor.
+  * @param  pXferData     : [IN/OUT] Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                                  (control buffer, data buffer and status buffer).
+  * @param  nbFrame       : [IN]  The number of CCC commands or the number of device to treat.
+  * @param  option        : [IN]  Value indicates the transfer option. It can be one value of @ref I3C_OPTION_DEFINITION
+  * @retval HAL Status    :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef         *hi3c,
+                                         const I3C_CCCTypeDef      *pCCCDesc,
+                                         const I3C_PrivateTypeDef  *pPrivateDesc,
+                                         I3C_XferTypeDef           *pXferData,
+                                         uint8_t                    nbFrame,
+                                         uint32_t                   option)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Set handle transfer parameters */
+    hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+    hi3c->pCCCDesc      = pCCCDesc;
+    hi3c->pPrivateDesc  = pPrivateDesc;
+    hi3c->pXferData     = pXferData;
+    hi3c->RxXferCount   = 0;
+    hi3c->TxXferCount   = 0;
+
+    /* Prepare Direction, and Check on user parameters */
+    if (((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC) ||
+        ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT))
+    {
+      /* Check on user parameters */
+      if ((pCCCDesc == NULL)  ||
+          (pXferData == NULL) ||
+          (nbFrame < 1U)      ||
+          (((option & (I3C_OPERATION_TYPE_MASK        | I3C_DEFINE_BYTE_MASK)) == \
+            (LL_I3C_CONTROLLER_MTYPE_DIRECT | I3C_DEFINE_BYTE_MASK)) && (pCCCDesc->CCCBuf.Size == 0U)))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Check on user parameters */
+      if ((pPrivateDesc == NULL) || (pXferData == NULL) || (nbFrame <= 0U))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* check on the State */
+      if ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN))
+      {
+        /* I3C control buffer prior preparation */
+        if (I3C_ControlBuffer_PriorPreparation(hi3c, nbFrame, option) != HAL_OK)
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+        }
+
+        /* I3C Tx Buffer prior preparation, set and check RxCount */
+        if (I3C_Xfer_PriorPreparation(hi3c, nbFrame, option) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        status = HAL_BUSY;
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Set the configuration of the inserted reset pattern at the end of a Frame.
+  * @note  When the transfer descriptor contains multiple frames with RESTART option, the reset pattern at the end of
+  *        RSTACT CCC frame is not possible.
+  * @param  hi3c         : [IN] Pointer to an I3C_HandleTypeDef structure that contains
+  *                             the configuration information for the specified I3C.
+  * @param  resetPattern : [IN] Specifies the reset pattern configuration.
+  *                             It can be a value of @ref I3C_RESET_PATTERN
+  * @retval HAL Status   :      Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_SetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t resetPattern)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+    assert_param(IS_I3C_RESET_PATTERN(resetPattern));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      hi3c->State = HAL_I3C_STATE_BUSY;
+
+      if (resetPattern == HAL_I3C_RESET_PATTERN_ENABLE)
+      {
+        LL_I3C_EnableResetPattern(hi3c->Instance);
+      }
+      else
+      {
+        LL_I3C_DisableResetPattern(hi3c->Instance);
+      }
+
+      /* At the end of process update state to Previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Get the configuration of the inserted reset pattern at the end of a Frame.
+  * @param  hi3c          : [IN] Pointer to an I3C_HandleTypeDef structure that contains
+  *                              the configuration information for the specified I3C.
+  * @param  pResetPattern : [OUT] Pointer to the current reset pattern configuration.
+  *                               It can be a value of @ref I3C_RESET_PATTERN
+  * @retval HAL Status    :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_GetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t *pResetPattern)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check on user parameters */
+  else if (pResetPattern == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check if the reset pattern configuration is enabled */
+    if (LL_I3C_IsEnabledResetPattern(hi3c->Instance) == 1U)
+    {
+      *pResetPattern     = HAL_I3C_RESET_PATTERN_ENABLE;
+    }
+    else
+    {
+      *pResetPattern     = HAL_I3C_RESET_PATTERN_DISABLE;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Exported_Functions_Group4 FIFO Management functions.
+  * @brief    I3C FIFO management functions.
+  *
+@verbatim
+ =======================================================================================================================
+                                      ##### FIFO Management functions #####
+ =======================================================================================================================
+    [..]  This subsection provides a set of functions allowing to manage I3C FIFOs.
+
+         (+) Call the function HAL_I3C_FlushAllFifo() to flush the content of all used FIFOs (Control, Status,
+             Tx and Rx FIFO).
+         (+) Call the function HAL_I3C_FlushTxFifo() to flush only the content of Tx FIFO.
+         (+) Call the function HAL_I3C_FlushRxFifo() to flush only the content of Rx FIFO.
+         (+) Call the function HAL_I3C_FlushControlFifo() to flush only the content of Control FIFO.
+             This function is called only when mode is controller.
+         (+) Call the function HAL_I3C_FlushStatusFifo() to flush only the content of Status FIFO.
+             This function is called only when mode is controller.
+         (+) Call the function HAL_I3C_ClearConfigFifo() to clear the FIFOs configuration and set it to default values.
+         (+) Call the function HAL_I3C_GetConfigFifo() to get the current FIFOs configuration (enabled FIFOs and
+             threshold level).
+
+         (+) Users must not call all above functions before I3C initialization.
+
+         (+) Users should call Flush APIs after an end of process, before starting a transfer or in case of bus
+             failure and error detection.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Flush all I3C FIFOs content.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_FlushAllFifo(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cfgr_value;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check the I3C state */
+    if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the content of Tx and Rx Fifo */
+      cfgr_value = (I3C_CFGR_TXFLUSH | I3C_CFGR_RXFLUSH);
+
+      /* Check on the I3C mode: Control and status FIFOs available only with controller mode */
+      if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER)
+      {
+        /* Flush the content of Control and Status Fifo */
+        cfgr_value = (I3C_CFGR_SFLUSH | I3C_CFGR_CFLUSH);
+      }
+
+      /* Set configuration in the CFGR register */
+      MODIFY_REG(hi3c->Instance->CFGR, cfgr_value, cfgr_value);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Flush I3C Tx FIFO content.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_FlushTxFifo(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check the I3C state */
+    if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the content of Tx Fifo */
+      LL_I3C_RequestTxFIFOFlush(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Flush I3C Rx FIFO content.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_FlushRxFifo(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check the I3C state */
+    if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the content of Rx Fifo */
+      LL_I3C_RequestRxFIFOFlush(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Flush I3C control FIFO content.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_FlushControlFifo(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check the I3C state and mode */
+    if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the content of Control Fifo */
+      LL_I3C_RequestControlFIFOFlush(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Flush I3C status FIFO content.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_FlushStatusFifo(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check the I3C state and mode */
+    if ((hi3c->State == HAL_I3C_STATE_RESET) || (hi3c->Mode != HAL_I3C_MODE_CONTROLLER))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the content of Control Fifo */
+      LL_I3C_RequestStatusFIFOFlush(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Clear I3C FIFOs configuration and set it to default values.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_ClearConfigFifo(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cfgr_value;
+  uint32_t cfgr_mask;
+
+  /* Check the I3C handle allocation */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check the I3C state */
+    if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Clear Tx Fifo and Rx Fifo threshold and set it to default value */
+      cfgr_value = (LL_I3C_TXFIFO_THRESHOLD_1_4 | LL_I3C_RXFIFO_THRESHOLD_1_4);
+      cfgr_mask  = (I3C_CFGR_TXTHRES | I3C_CFGR_RXTHRES);
+
+      /* Check on the I3C mode: Control and status FIFOs available only with controller mode */
+      if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER)
+      {
+        /* Disable the status and Control Fifo state */
+        cfgr_value |= (HAL_I3C_STATUSFIFO_DISABLE | HAL_I3C_CONTROLFIFO_DISABLE);
+        cfgr_mask  |= (I3C_CFGR_TMODE | I3C_CFGR_SMODE);
+      }
+
+      /* Set configuration in the CFGR register */
+      MODIFY_REG(hi3c->Instance->CFGR, cfgr_mask, cfgr_value);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Get I3C FIFOs current configuration.
+  * @param  hi3c       : [IN]     Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                               for the specified I3C.
+  * @param  pConfig    : [IN/OUT] Pointer to an I3C_FifoConfTypeDef structure that returns current FIFOs configuration.
+  * @retval HAL Status :          Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the I3C handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Check on user parameters */
+    if (pConfig == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C state */
+    else if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Get Tx Fifo threshold */
+      pConfig->TxFifoThreshold = LL_I3C_GetTxFIFOThreshold(hi3c->Instance);
+
+      /* Get Rx Fifo threshold */
+      pConfig->RxFifoThreshold = LL_I3C_GetRxFIFOThreshold(hi3c->Instance);
+
+      /* Get the Control Fifo state */
+      pConfig->ControlFifo = (uint32_t)(LL_I3C_IsEnabledControlFIFO(hi3c->Instance) << I3C_CFGR_TMODE_Pos);
+
+      /* Get the status Fifo state */
+      pConfig->StatusFifo = (uint32_t)(LL_I3C_IsEnabledStatusFIFO(hi3c->Instance) << I3C_CFGR_SMODE_Pos);
+    }
+  }
+
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Exported_Functions_Group5 Controller operational functions.
+  * @brief    I3C controller operational functions.
+  *
+@verbatim
+ =======================================================================================================================
+                                  ##### Controller operational functions #####
+ =======================================================================================================================
+    [..]  This subsection provides a set of functions allowing to manage controller I3C operation.
+
+         (+) Call the function HAL_I3C_Ctrl_TransmitCCC() to transmit direct write or a broadcast
+             CCC command in polling mode.
+         (+) Call the function HAL_I3C_Ctrl_TransmitCCC_IT() to transmit direct write or a broadcast
+             CCC command in interrupt mode.
+         (+) Call the function HAL_I3C_Ctrl_TransmitCCC_DMA() to transmit direct write or a broadcast
+             CCC command in DMA mode.
+         (+) Call the function HAL_I3C_Ctrl_ReceiveCCC() to transmit direct read CCC command in polling mode.
+         (+) Call the function HAL_I3C_Ctrl_ReceiveCCC_IT() to transmit direct read CCC command in interrupt mode.
+         (+) Call the function HAL_I3C_Ctrl_ReceiveCCC_DMA() to transmit direct read CCC command in DMA mode.
+         (+) Call the function HAL_I3C_Ctrl_Transmit() to transmit private data in polling mode.
+         (+) Call the function HAL_I3C_Ctrl_Transmit_IT() to transmit private data in interrupt mode.
+         (+) Call the function HAL_I3C_Ctrl_Transmit_DMA() to transmit private data in DMA mode.
+         (+) Call the function HAL_I3C_Ctrl_Receive() to receive private data in polling mode.
+         (+) Call the function HAL_I3C_Ctrl_Receive_IT() to receive private data in interrupt mode.
+         (+) Call the function HAL_I3C_Ctrl_Receive_DMA() to receive private data in DMA mode.
+         (+) Call the function HAL_I3C_Ctrl_MultipleTransfer_IT() to transfer I3C or I2C private data or CCC command
+             in multiple direction in interrupt mode.
+         (+) Call the function HAL_I3C_Ctrl_MultipleTransfer_DMA() to transfer I3C or I2C private data or CCC command
+             in multiple direction in DMA mode.
+         (+) Call the function HAL_I3C_Ctrl_DynAddrAssign() to send a broadcast ENTDAA CCC
+             command in polling mode.
+         (+) Call the function HAL_I3C_Ctrl_DynAddrAssign_IT() to send a broadcast ENTDAA CCC
+             command in interrupt mode.
+         (+) Call the function HAL_I3C_Ctrl_SetDynAddr() to set, asscociate the target dynamic address
+             during the Dynamic Address Assignment processus.
+         (+) Call the function HAL_I3C_Ctrl_IsDeviceI3C_Ready() to check if I3C target device is ready.
+         (+) Call the function HAL_I3C_Ctrl_IsDeviceI2C_Ready() to check if I2C target device is ready.
+         (+) Call the function HAL_I3C_Ctrl_GenerateArbitration to send arbitration
+            (message header {S + 0x7E + W + STOP}) in polling mode
+
+         (+) Those functions are called only when mode is Controller.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Controller transmit direct write or a broadcast CCC command in polling mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c,
+                                           I3C_XferTypeDef   *pXferData,
+                                           uint32_t           timeout)
+{
+  uint32_t tickstart;
+  uint32_t exit_condition;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) ||
+        ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      /* Update returned status value */
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY_TX;
+      hi3c->pXferData = pXferData;
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+      }
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Check on control FIFO enable/disable state */
+      if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U)
+      {
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Decrement remaining control buffer data counter */
+        hi3c->ControlXferCount--;
+
+        /* Initiate a start condition by writing in the CR register */
+        WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer);
+
+        /* Increment Buffer pointer */
+        hi3c->pXferData->CtrlBuf.pBuffer++;
+      }
+
+      /* Do while until FC (Frame Complete) is set or timeout */
+      do
+      {
+        /* Check if hardware asks for control data */
+        if (hi3c->ControlXferCount > 0U)
+        {
+          /* Call control data treatment function */
+          I3C_ControlDataTreatment(hi3c);
+        }
+
+        /* Check if hardware asks for Tx data */
+        if (hi3c->TxXferCount > 0U)
+        {
+          /* Call transmit treatment function */
+          hi3c->ptrTxFunc(hi3c);
+        }
+
+        /* Check for the timeout */
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+            break;
+          }
+        }
+
+        if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U))
+        {
+          /* Clear frame complete flag */
+          LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+          /* Then Initiate a Start condition */
+          LL_I3C_RequestTransfer(hi3c->Instance);
+        }
+
+        /* Calculate exit_condition value based on Frame complete and error flags */
+        exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+      } while ((exit_condition == 0U) ||
+               ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U)));
+
+      /* Clear frame complete flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+      {
+        LL_I3C_ClearFlag_FC(hi3c->Instance);
+      }
+
+      /* Check on error flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        /* Update returned status value */
+        status = HAL_ERROR;
+      }
+
+      /* At the end of Tx process update state to Previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Controller transmit direct write or a broadcast CCC command in interrupt mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c,
+                                              I3C_XferTypeDef   *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) ||
+        ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+      if (handle_state == HAL_I3C_STATE_LISTEN)
+      {
+        hi3c->XferISR = I3C_Ctrl_Tx_Listen_Event_ISR;
+      }
+      else
+      {
+        hi3c->XferISR = I3C_Ctrl_Tx_ISR;
+      }
+
+      hi3c->pXferData = pXferData;
+      hi3c->State     = HAL_I3C_STATE_BUSY_TX;
+
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+      }
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Tx process interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT);
+
+      /* Initiate a Start condition */
+      LL_I3C_RequestTransfer(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Controller transmit direct write or a broadcast CCC command in DMA mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c,
+                                               I3C_XferTypeDef   *pXferData)
+{
+  HAL_StatusTypeDef control_dma_status;
+  HAL_StatusTypeDef tx_dma_status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t size_align_word;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) ||
+        ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on hdmatx and hdmacr handle */
+    else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      hi3c->XferISR       = I3C_Ctrl_Tx_DMA_ISR;
+      hi3c->pXferData     = pXferData;
+      hi3c->State         = HAL_I3C_STATE_BUSY_TX;
+
+      /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/
+      /* Set the I3C DMA transfer complete callback */
+      hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi3c->hdmacr->XferErrorCallback = I3C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi3c->hdmacr->XferHalfCpltCallback = NULL;
+      hi3c->hdmacr->XferAbortCallback    = NULL;
+
+      /* assert that DMA source and destination width are configured in word */
+      assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth));
+      assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth));
+
+      /* Enable the control data DMA channel */
+      control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer,
+                                            (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U));
+
+      /*------------------------------------ I3C DMA channel for the Tx Data -----------------------------------------*/
+      /* Check if Tx counter different from zero */
+      if (hi3c->TxXferCount != 0U)
+      {
+        /* Set the I3C DMA transfer complete callback */
+        hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi3c->hdmatx->XferErrorCallback = I3C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi3c->hdmatx->XferHalfCpltCallback = NULL;
+        hi3c->hdmatx->XferAbortCallback    = NULL;
+
+        /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+        if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+        {
+          /* assert that DMA source and destination width are configured in byte */
+          assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size);
+        }
+        else
+        {
+          /* assert that DMA source and destination width are configured in word */
+          assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Check to align data size in words */
+          if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U)
+          {
+            /* Keep the same size */
+            size_align_word = hi3c->pXferData->TxBuf.Size;
+          }
+          else
+          {
+            /* Modify size to be multiple of 4 */
+            size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U));
+          }
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDWR, size_align_word);
+        }
+      }
+
+      /* Check if DMA process is well started */
+      if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK))
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+        of I3C interrupt handle execution before current process unlock */
+
+        /* Enable Tx process interrupts */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update the number of remaining data bytes */
+        hi3c->ControlXferCount = 0U;
+
+        /* Enable control DMA Request */
+        LL_I3C_EnableDMAReq_Control(hi3c->Instance);
+
+        /* Check if Tx counter different from zero */
+        if (hi3c->TxXferCount != 0U)
+        {
+          /* Update the number of remaining data bytes */
+          hi3c->TxXferCount = 0U;
+
+          /* Enable Tx data DMA Request */
+          LL_I3C_EnableDMAReq_TX(hi3c->Instance);
+        }
+
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK)
+        {
+          hi3c->hdmacr->XferCpltCallback = NULL;
+          hi3c->hdmacr->XferErrorCallback = NULL;
+        }
+
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK)
+        {
+          hi3c->hdmatx->XferCpltCallback = NULL;
+          hi3c->hdmatx->XferErrorCallback = NULL;
+        }
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_DMA;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+    }
+  }
+
+  return status;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Controller transmit direct read CCC command in polling mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c,
+                                          I3C_XferTypeDef   *pXferData,
+                                          uint32_t           timeout)
+{
+  uint32_t tickstart;
+  uint32_t exit_condition;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL)                     ||
+        (pXferData->RxBuf.pBuffer == NULL)      ||
+        ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->State       = HAL_I3C_STATE_BUSY_RX;
+      hi3c->pXferData   = pXferData;
+      hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size;
+
+      /* Check on CCC defining byte */
+      if (hi3c->TxXferCount != 0U)
+      {
+        /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+        if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+        {
+          /* Set byte treatment function pointer */
+          hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+        }
+        else
+        {
+          /* Set word treatment function pointer */
+          hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+        }
+      }
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+      }
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Check on control FIFO enable/disable state */
+      if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U)
+      {
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Decrement remaining control buffer data counter */
+        hi3c->ControlXferCount--;
+
+        /* Initiate a start condition by writing in the CR register */
+        WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer);
+
+        /* Increment Buffer pointer */
+        hi3c->pXferData->CtrlBuf.pBuffer++;
+      }
+
+      /* Do while until FC (Frame Complete) is set or timeout */
+      do
+      {
+        /* Call control data treatment function */
+        I3C_ControlDataTreatment(hi3c);
+
+        if (hi3c->TxXferCount != 0U)
+        {
+          /* Call transmit treatment function */
+          hi3c->ptrTxFunc(hi3c);
+        }
+
+        /* Call receive treatment function */
+        hi3c->ptrRxFunc(hi3c);
+
+        /* Check for the timeout */
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+
+            break;
+          }
+        }
+
+        if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U))
+        {
+          /* Clear frame complete flag */
+          LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+          /* Then Initiate a Start condition */
+          LL_I3C_RequestTransfer(hi3c->Instance);
+        }
+
+        /* Calculate exit_condition value based on Frame complete and error flags */
+        exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+      } while ((exit_condition == 0U) ||
+               ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U)));
+
+      /* Clear frame complete flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+      {
+        LL_I3C_ClearFlag_FC(hi3c->Instance);
+      }
+
+      /* Check if all data bytes are received */
+      if ((hi3c->RxXferCount != 0U) && (status == HAL_OK))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+        status = HAL_ERROR;
+      }
+
+      /* Check on error flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        /* Update returned status value */
+        status = HAL_ERROR;
+      }
+
+      /* At the end of Rx process update state to Previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Controller transmit direct read CCC command in interrupt mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c,
+                                             I3C_XferTypeDef   *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL)                     ||
+        (pXferData->RxBuf.pBuffer == NULL)      ||
+        ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      if (handle_state == HAL_I3C_STATE_LISTEN)
+      {
+        hi3c->XferISR   = I3C_Ctrl_Rx_Listen_Event_ISR;
+      }
+      else
+      {
+        hi3c->XferISR   = I3C_Ctrl_Rx_ISR;
+      }
+      hi3c->pXferData   = pXferData;
+      hi3c->RxXferCount = pXferData->RxBuf.Size;
+      hi3c->State       = HAL_I3C_STATE_BUSY_RX;
+
+      /* Check on CCC defining byte */
+      if (hi3c->TxXferCount != 0U)
+      {
+        /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+        if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+        {
+          /* Set byte treatment function pointer */
+          hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+        }
+        else
+        {
+          /* Set word treatment function pointer */
+          hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+        }
+      }
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+      }
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Rx process interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT);
+
+      /* Initiate a Start condition */
+      LL_I3C_RequestTransfer(hi3c->Instance);
+
+    }
+  }
+
+  return status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Controller transmit direct read CCC command in DMA mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c,
+                                              I3C_XferTypeDef   *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_StatusTypeDef control_dma_status;
+  HAL_StatusTypeDef tx_dma_status = HAL_OK;
+  HAL_StatusTypeDef rx_dma_status = HAL_OK;
+  uint32_t size_align_word;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL)                     ||
+        (pXferData->RxBuf.pBuffer == NULL)      ||
+        ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on hdmarx and hdmacr handle */
+    else if ((hi3c->hdmarx == NULL) || (hi3c->hdmacr == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+    }
+    else if ((hi3c->TxXferCount != 0U) && (hi3c->hdmatx == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->XferISR     = I3C_Ctrl_Rx_DMA_ISR;
+      hi3c->pXferData   = pXferData;
+      hi3c->RxXferCount = hi3c->pXferData->RxBuf.Size;
+      hi3c->State       = HAL_I3C_STATE_BUSY_RX;
+
+      /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/
+      /* Set the I3C DMA transfer complete callback */
+      hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi3c->hdmacr->XferErrorCallback = I3C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi3c->hdmacr->XferHalfCpltCallback = NULL;
+      hi3c->hdmacr->XferAbortCallback    = NULL;
+
+      /* assert that DMA source and destination width are configured in word */
+      assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth));
+      assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth));
+
+      /* Enable the control data DMA channel */
+      control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer,
+                                            (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U));
+
+      /*------------------------------------ I3C DMA channel for defining byte ---------------------------------------*/
+      /* Check if Tx counter different from zero */
+      if (hi3c->TxXferCount != 0U)
+      {
+        /* Set the I3C DMA transfer complete callback */
+        hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi3c->hdmatx->XferErrorCallback = I3C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi3c->hdmatx->XferHalfCpltCallback = NULL;
+        hi3c->hdmatx->XferAbortCallback    = NULL;
+
+        /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+        if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+        {
+          /* assert that DMA source and destination width are configured in byte */
+          assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size);
+        }
+        else
+        {
+          /* assert that DMA source and destination width are configured in word */
+          assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Modify size to be multiple of 4 */
+          size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U));
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDWR, size_align_word);
+        }
+      }
+      /*------------------------------------ I3C DMA channel for the Rx Data -----------------------------------------*/
+      /* Check if Rx counter different from zero */
+      if (hi3c->RxXferCount != 0U)
+      {
+        /* Set the I3C DMA transfer complete callback */
+        hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi3c->hdmarx->XferErrorCallback = I3C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi3c->hdmarx->XferHalfCpltCallback = NULL;
+        hi3c->hdmarx->XferAbortCallback    = NULL;
+
+        /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+        if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+        {
+          /* assert that DMA source and destination width are configured in byte */
+          assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+          /* Enable the Rx data DMA channel */
+          rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR,
+                                           (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size);
+        }
+        else
+        {
+          /* assert that DMA source and destination width are configured in word */
+          assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+          /* Check to align data size in words */
+          if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U)
+          {
+            /* Keep the same size */
+            size_align_word = hi3c->pXferData->RxBuf.Size;
+          }
+          else
+          {
+            /* Modify size to be multiple of 4 */
+            size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U));
+          }
+
+          /* Enable the Rx data DMA channel */
+          rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR,
+                                           (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word);
+        }
+      }
+
+      /* Check if DMA process is well started */
+      if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK) && (rx_dma_status == HAL_OK))
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+        of I3C interrupt handle execution before current process unlock */
+
+        /* Enable Rx process interrupts */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update the number of remaining data bytes */
+        hi3c->ControlXferCount = 0U;
+
+        /* Enable control DMA Request */
+        LL_I3C_EnableDMAReq_Control(hi3c->Instance);
+
+        /* Check if Tx counter different from zero */
+        if (hi3c->TxXferCount != 0U)
+        {
+          /* Update the number of remaining data bytes */
+          hi3c->TxXferCount = 0U;
+
+          /* Enable Tx data DMA Request */
+          LL_I3C_EnableDMAReq_TX(hi3c->Instance);
+        }
+
+        /* Check if Rx counter different from zero */
+        if (hi3c->RxXferCount != 0U)
+        {
+          /* Update the number of remaining data bytes */
+          hi3c->RxXferCount = 0U;
+
+          /* Enable Rx data DMA Request */
+          LL_I3C_EnableDMAReq_RX(hi3c->Instance);
+        }
+
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK)
+        {
+          hi3c->hdmacr->XferCpltCallback = NULL;
+          hi3c->hdmacr->XferErrorCallback = NULL;
+        }
+
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK)
+        {
+          hi3c->hdmatx->XferCpltCallback = NULL;
+          hi3c->hdmatx->XferErrorCallback = NULL;
+        }
+
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmarx) == HAL_OK)
+        {
+          hi3c->hdmarx->XferCpltCallback = NULL;
+          hi3c->hdmarx->XferErrorCallback = NULL;
+        }
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_DMA;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+    }
+  }
+
+  return status;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Controller private write in polling mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @note   The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef   *hi3c,
+                                        I3C_XferTypeDef     *pXferData,
+                                        uint32_t             timeout)
+{
+  uint32_t tickstart;
+  uint32_t exit_condition;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) ||
+        ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      hi3c->State         = HAL_I3C_STATE_BUSY_TX;
+      hi3c->pXferData     = pXferData;
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+      }
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Check on control FIFO enable/disable state */
+      if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U)
+      {
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Decrement remaining control buffer data counter */
+        hi3c->ControlXferCount--;
+
+        /* Initiate a start condition by writing in the CR register */
+        WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer);
+
+        /* Increment Buffer pointer */
+        hi3c->pXferData->CtrlBuf.pBuffer++;
+      }
+
+      /* Do while until FC (Frame Complete) is set or timeout */
+      do
+      {
+        /* Call control data treatment function */
+        I3C_ControlDataTreatment(hi3c);
+
+        /* Call transmit treatment function */
+        hi3c->ptrTxFunc(hi3c);
+
+        /* Check for the timeout */
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+
+            break;
+          }
+        }
+
+        if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U))
+        {
+          /* Clear frame complete flag */
+          LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+          /* Then Initiate a Start condition */
+          LL_I3C_RequestTransfer(hi3c->Instance);
+        }
+
+        /* Calculate exit_condition value based on Frame complete and error flags */
+        exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+      } while ((exit_condition == 0U) ||
+               ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U)));
+
+      /* Clear frame complete flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+      {
+        LL_I3C_ClearFlag_FC(hi3c->Instance);
+      }
+
+      /* Check if all data bytes are transmitted */
+      if ((hi3c->TxXferCount != 0U) && (status == HAL_OK))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+        status = HAL_ERROR;
+      }
+
+      /* Check on error flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        /* Update returned status value */
+        status = HAL_ERROR;
+      }
+
+      /* At the end of Tx process update state to Previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Controller private write in interrupt mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @note   The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef   *hi3c,
+                                           I3C_XferTypeDef     *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) ||
+        ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      if (handle_state == HAL_I3C_STATE_LISTEN)
+      {
+        hi3c->XferISR     = I3C_Ctrl_Tx_Listen_Event_ISR;
+      }
+      else
+      {
+        hi3c->XferISR     = I3C_Ctrl_Tx_ISR;
+      }
+      hi3c->pXferData     = pXferData;
+      hi3c->State         = HAL_I3C_STATE_BUSY_TX;
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+      }
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Tx process interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT);
+
+      /* Initiate a Start condition */
+      LL_I3C_RequestTransfer(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Controller private write in DMA mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @note   The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef   *hi3c,
+                                            I3C_XferTypeDef     *pXferData)
+{
+  HAL_StatusTypeDef control_dma_status;
+  HAL_StatusTypeDef tx_dma_status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t size_align_word;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) ||
+        ((hi3c->TxXferCount != 0U) && (pXferData->TxBuf.pBuffer == NULL)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on hdmatx and hdmacr handle */
+    else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      hi3c->XferISR       = I3C_Ctrl_Tx_DMA_ISR;
+      hi3c->State         = HAL_I3C_STATE_BUSY_TX;
+      hi3c->pXferData     = pXferData;
+
+      /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/
+      /* Set the I3C DMA transfer complete callback */
+      hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi3c->hdmacr->XferErrorCallback = I3C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi3c->hdmacr->XferHalfCpltCallback = NULL;
+      hi3c->hdmacr->XferAbortCallback    = NULL;
+
+      /* assert that DMA source and destination width are configured in word */
+      assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth));
+      assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth));
+
+      /* Enable the control data DMA channel */
+      control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer,
+                                            (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U));
+
+      /*------------------------------------ I3C DMA channel for the Tx Data -----------------------------------------*/
+      /* Check if Tx counter different from zero */
+      if (hi3c->TxXferCount != 0U)
+      {
+        /* Set the I3C DMA transfer complete callback */
+        hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi3c->hdmatx->XferErrorCallback = I3C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi3c->hdmatx->XferHalfCpltCallback = NULL;
+        hi3c->hdmatx->XferAbortCallback    = NULL;
+
+        /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+        if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+        {
+          /* assert that DMA source and destination width are configured in byte */
+          assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size);
+        }
+        else
+        {
+          /* assert that DMA source and destination width are configured in word */
+          assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Check to align data size in words */
+          if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U)
+          {
+            /* Keep the same size */
+            size_align_word = hi3c->pXferData->TxBuf.Size;
+          }
+          else
+          {
+            /* Modify size to be multiple of 4 */
+            size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U));
+          }
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDWR, size_align_word);
+        }
+      }
+
+      /* Check if DMA process is well started */
+      if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK))
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+        of I3C interrupt handle execution before current process unlock */
+
+        /* Enable Tx process interrupts */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update the number of remaining data bytes */
+        hi3c->ControlXferCount = 0U;
+
+        /* Enable control DMA Request */
+        LL_I3C_EnableDMAReq_Control(hi3c->Instance);
+
+        /* Check if Tx counter different from zero */
+        if (hi3c->TxXferCount != 0U)
+        {
+          /* Update the number of remaining data bytes */
+          hi3c->TxXferCount = 0U;
+
+          /* Enable Tx data DMA Request */
+          LL_I3C_EnableDMAReq_TX(hi3c->Instance);
+        }
+
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK)
+        {
+          hi3c->hdmacr->XferCpltCallback = NULL;
+          hi3c->hdmacr->XferErrorCallback = NULL;
+        }
+
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK)
+        {
+          hi3c->hdmatx->XferCpltCallback = NULL;
+          hi3c->hdmatx->XferErrorCallback = NULL;
+        }
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_DMA;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+    }
+  }
+
+  return status;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Controller private read in polling mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Receive(I3C_HandleTypeDef   *hi3c,
+                                       I3C_XferTypeDef     *pXferData,
+                                       uint32_t             timeout)
+{
+  uint32_t tickstart;
+  uint32_t exit_condition;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      hi3c->State         = HAL_I3C_STATE_BUSY_RX;
+      hi3c->pXferData     = pXferData;
+      hi3c->RxXferCount   = hi3c->pXferData->RxBuf.Size;
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+      }
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Check on control FIFO enable/disable state */
+      if (LL_I3C_IsEnabledControlFIFO(hi3c->Instance) == 1U)
+      {
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Decrement remaining control buffer data counter */
+        hi3c->ControlXferCount--;
+
+        /* Initiate a start condition by writing in the CR register */
+        WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer);
+
+        /* Increment Buffer pointer */
+        hi3c->pXferData->CtrlBuf.pBuffer++;
+      }
+
+      /* Do while until FC (Frame Complete) is set or timeout */
+      do
+      {
+        /* Call control data treatment function */
+        I3C_ControlDataTreatment(hi3c);
+
+        /* Call receive treatment function */
+        hi3c->ptrRxFunc(hi3c);
+
+        /* Check for the timeout */
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+
+            break;
+          }
+        }
+
+        if ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET) && (hi3c->ControlXferCount > 0U))
+        {
+          /* Clear frame complete flag */
+          LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+          /* Then Initiate a Start condition */
+          LL_I3C_RequestTransfer(hi3c->Instance);
+        }
+
+        /* Calculate exit_condition value based on Frame complete and error flags */
+        exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+      } while ((exit_condition == 0U) ||
+               ((exit_condition == I3C_EVR_FCF) && (hi3c->ControlXferCount > 0U)));
+
+      /* Clear frame complete flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+      {
+        LL_I3C_ClearFlag_FC(hi3c->Instance);
+      }
+
+      /* Check if all data bytes are received */
+      if ((hi3c->RxXferCount != 0U) && (status == HAL_OK))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+        status = HAL_ERROR;
+      }
+
+      /* Check on error flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        /* Update returned status value */
+        status = HAL_ERROR;
+      }
+
+      /* At the end of Rx process update state to Previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Controller private read in interrupt mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef   *hi3c,
+                                          I3C_XferTypeDef     *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      if (handle_state == HAL_I3C_STATE_LISTEN)
+      {
+        hi3c->XferISR     = I3C_Ctrl_Rx_Listen_Event_ISR;
+      }
+      else
+      {
+        hi3c->XferISR     = I3C_Ctrl_Rx_ISR;
+      }
+      hi3c->pXferData     = pXferData;
+      hi3c->RxXferCount   = hi3c->pXferData->RxBuf.Size;
+      hi3c->State         = HAL_I3C_STATE_BUSY_RX;
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+      }
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Rx process interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_IT);
+
+      /* Initiate a Start condition */
+      LL_I3C_RequestTransfer(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Controller private read in DMA mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
+  *                            (control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef   *hi3c,
+                                           I3C_XferTypeDef     *pXferData)
+{
+  HAL_StatusTypeDef control_dma_status;
+  HAL_StatusTypeDef rx_dma_status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t size_align_word;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on hdmarx and hdmacr handle */
+    else if ((hi3c->hdmarx == NULL) || (hi3c->hdmacr == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      hi3c->XferISR       = I3C_Ctrl_Rx_DMA_ISR;
+      hi3c->pXferData     = pXferData;
+      hi3c->RxXferCount   = hi3c->pXferData->RxBuf.Size;
+      hi3c->State         = HAL_I3C_STATE_BUSY_RX;
+
+      /*------------------------------------ I3C DMA channel for Control Data ----------------------------------------*/
+      /* Set the I3C DMA transfer complete callback */
+      hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi3c->hdmacr->XferErrorCallback = I3C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi3c->hdmacr->XferHalfCpltCallback = NULL;
+      hi3c->hdmacr->XferAbortCallback    = NULL;
+
+      /* assert that DMA source and destination width are configured in word */
+      assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth));
+      assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth));
+
+      /* Enable the control data DMA channel */
+      control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer,
+                                            (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U));
+
+      /*------------------------------------ I3C DMA channel for the Rx Data -----------------------------------------*/
+      /* Check if Rx counter different from zero */
+      if (hi3c->RxXferCount != 0U)
+      {
+        /* Set the I3C DMA transfer complete callback */
+        hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi3c->hdmarx->XferErrorCallback = I3C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi3c->hdmarx->XferHalfCpltCallback = NULL;
+        hi3c->hdmarx->XferAbortCallback    = NULL;
+
+        /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+        if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+        {
+          /* assert that DMA source and destination width are configured in byte */
+          assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+          /* Enable the Rx data DMA channel */
+          rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR,
+                                           (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size);
+        }
+        else
+        {
+          /* assert that DMA source and destination width are configured in word */
+          assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+          /* Check to align data size in words */
+          if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U)
+          {
+            /* Keep the same size */
+            size_align_word = hi3c->pXferData->RxBuf.Size;
+          }
+          else
+          {
+            /* Modify size to be multiple of 4 */
+            size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U));
+          }
+
+          /* Enable the Rx data DMA channel */
+          rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR,
+                                           (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word);
+        }
+      }
+
+      /* Check if DMA process is well started */
+      if ((control_dma_status == HAL_OK) && (rx_dma_status == HAL_OK))
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+        of I3C interrupt handle execution before current process unlock */
+
+        /* Enable Rx process interrupts */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update the number of remaining data bytes */
+        hi3c->ControlXferCount = 0U;
+
+        /* Enable control DMA Request */
+        LL_I3C_EnableDMAReq_Control(hi3c->Instance);
+
+        /* Check if Rx counter different from zero */
+        if (hi3c->RxXferCount != 0U)
+        {
+          /* Update the number of remaining data bytes */
+          hi3c->RxXferCount = 0U;
+
+          /* Enable Rx data DMA Request */
+          LL_I3C_EnableDMAReq_RX(hi3c->Instance);
+        }
+
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK)
+        {
+          hi3c->hdmacr->XferCpltCallback = NULL;
+          hi3c->hdmacr->XferErrorCallback = NULL;
+        }
+
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmarx) == HAL_OK)
+        {
+          hi3c->hdmarx->XferCpltCallback = NULL;
+          hi3c->hdmarx->XferErrorCallback = NULL;
+        }
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_DMA;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+
+    }
+  }
+
+  return status;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Controller multiple Direct CCC Command, I3C private or I2C transfer in interrupt mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @note   This function must be called to transfer read/write I3C or I2C private data or a direct read/write CCC.
+  * @note   The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor.
+  * @note   The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmit and receive
+  *                            buffers (control buffer, data buffers and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef   *hi3c,
+                                                   I3C_XferTypeDef     *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL)                                               ||
+        ((pXferData->RxBuf.pBuffer == NULL) && (hi3c->RxXferCount != 0U)) ||
+        ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      if (handle_state == HAL_I3C_STATE_LISTEN)
+      {
+        hi3c->XferISR     = I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR;
+      }
+      else
+      {
+        hi3c->XferISR     = I3C_Ctrl_Multiple_Xfer_ISR;
+      }
+      hi3c->pXferData     = pXferData;
+      hi3c->TxXferCount   = hi3c->pXferData->TxBuf.Size;
+      hi3c->RxXferCount   = hi3c->pXferData->RxBuf.Size;
+      hi3c->State         = HAL_I3C_STATE_BUSY_TX_RX;
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+      }
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+      }
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Tx and Rx process interrupts */
+      I3C_Enable_IRQ(hi3c, (I3C_XFER_CONTROLLER_TX_IT | I3C_XFER_CONTROLLER_RX_IT));
+
+      /* Initiate a Start condition */
+      LL_I3C_RequestTransfer(hi3c->Instance);
+    }
+  }
+  return status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Controller multiple Direct CCC Command, I3C private or I2C transfer in DMA mode.
+  * @note   The function @ref HAL_I3C_AddDescToFrame() must be called before initiate a transfer.
+  * @note   The Tx FIFO threshold @ref HAL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+  *         multiple transmission frames.
+  * @note   The TxBuf.Size must be equal to the sum of all TxBuf.Size exist in the descriptor.
+  * @note   The RxBuf.Size must be equal to the sum of all RxBuf.Size exist in the descriptor.
+  * @note   This function must be called to transfer read/write private data or a direct read/write CCC command.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmit and receive
+  *                            buffers(control buffer, data buffer and status buffer).
+  *                            This value contain transfer data after called @ref HAL_I3C_AddDescToFrame().
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef   *hi3c, I3C_XferTypeDef     *pXferData)
+{
+  HAL_StatusTypeDef control_dma_status;
+  HAL_StatusTypeDef tx_dma_status = HAL_OK;
+  HAL_StatusTypeDef rx_dma_status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t size_align_word;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL)                                               ||
+        ((pXferData->RxBuf.pBuffer == NULL) && (hi3c->RxXferCount != 0U)) ||
+        ((pXferData->TxBuf.pBuffer == NULL) && (hi3c->TxXferCount != 0U)))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on hdmatx, hdmarx and hdmacr handle */
+    else if ((hi3c->hdmatx == NULL) || (hi3c->hdmacr == NULL) || (hi3c->hdmarx == NULL))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+      hi3c->XferISR       = I3C_Ctrl_Multiple_Xfer_DMA_ISR;
+      hi3c->pXferData     = pXferData;
+      hi3c->RxXferCount   = hi3c->pXferData->RxBuf.Size;
+      hi3c->TxXferCount   = hi3c->pXferData->TxBuf.Size;
+      hi3c->State         = HAL_I3C_STATE_BUSY_TX_RX;
+
+      /*------------------------------------ I3C DMA channel for Control Data -------------------------------------*/
+      /* Set the I3C DMA transfer complete callback */
+      hi3c->hdmacr->XferCpltCallback = I3C_DMAControlTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi3c->hdmacr->XferErrorCallback = I3C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi3c->hdmacr->XferHalfCpltCallback = NULL;
+      hi3c->hdmacr->XferAbortCallback    = NULL;
+
+      /* assert that DMA source and destination width are configured in word */
+      assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmacr->Init.SrcDataWidth));
+      assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmacr->Init.DestDataWidth));
+
+      /* Enable the control data DMA channel */
+      control_dma_status = HAL_DMA_Start_IT(hi3c->hdmacr, (uint32_t)hi3c->pXferData->CtrlBuf.pBuffer,
+                                            (uint32_t)&hi3c->Instance->CR, (hi3c->ControlXferCount * 4U));
+
+      /*------------------------------------ I3C DMA channel for the Rx Data --------------------------------*/
+      /* Check if Rx counter different from zero */
+      if (hi3c->RxXferCount != 0U)
+      {
+        /* Set the I3C DMA transfer complete callback */
+        hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi3c->hdmarx->XferErrorCallback = I3C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi3c->hdmarx->XferHalfCpltCallback = NULL;
+        hi3c->hdmarx->XferAbortCallback    = NULL;
+
+        /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+        if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+        {
+          /* assert that DMA source and destination width are configured in byte */
+          assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+          /* Enable the Rx data DMA channel */
+          rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR,
+                                           (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size);
+        }
+        else
+        {
+          /* assert that DMA source and destination width are configured in word */
+          assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+          /* Check to align data size in words */
+          if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U)
+          {
+            /* Keep the same size */
+            size_align_word = hi3c->pXferData->RxBuf.Size;
+          }
+          else
+          {
+            /* Modify size to be multiple of 4 */
+            size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U));
+          }
+
+          /* Enable the Rx data DMA channel */
+          rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR,
+                                           (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word);
+        }
+      }
+
+      /*------------------------------------ I3C DMA channel for the Tx Data --------------------------------*/
+      /* Check if Tx counter different from zero */
+      if (hi3c->TxXferCount != 0U)
+      {
+        /* Set the I3C DMA transfer complete callback */
+        hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi3c->hdmatx->XferErrorCallback = I3C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi3c->hdmatx->XferHalfCpltCallback = NULL;
+        hi3c->hdmatx->XferAbortCallback    = NULL;
+
+        /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+        if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+        {
+          /* assert that DMA source and destination width are configured in byte */
+          assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size);
+        }
+        else
+        {
+          /* assert that DMA source and destination width are configured in word */
+          assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+          assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+          /* Check to align data size in words */
+          if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U)
+          {
+            /* Keep the same size */
+            size_align_word = hi3c->pXferData->TxBuf.Size;
+          }
+          else
+          {
+            /* Modify size to be multiple of 4 */
+            size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U));
+          }
+
+          /* Enable the Tx data DMA channel */
+          tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                           (uint32_t)&hi3c->Instance->TDWR, size_align_word);
+        }
+      }
+
+      /* Check if DMA process is well started */
+      if ((control_dma_status == HAL_OK) && (tx_dma_status == HAL_OK) && (rx_dma_status == HAL_OK))
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+        of I3C interrupt handle execution before current process unlock */
+
+        /* Enable Tx process interrupts */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update the number of remaining data bytes */
+        hi3c->ControlXferCount = 0U;
+
+        /* Enable control DMA Request */
+        LL_I3C_EnableDMAReq_Control(hi3c->Instance);
+
+        /* Check if Rx counter different from zero */
+        if (hi3c->RxXferCount != 0U)
+        {
+          /* Update the number of remaining data bytes */
+          hi3c->RxXferCount = 0U;
+
+          /* Enable Rx data DMA Request */
+          LL_I3C_EnableDMAReq_RX(hi3c->Instance);
+        }
+
+        /* Check if Tx counter different from zero */
+        if (hi3c->TxXferCount != 0U)
+        {
+          /* Update the number of remaining data bytes */
+          hi3c->TxXferCount = 0U;
+
+          /* Enable Tx data DMA Request */
+          LL_I3C_EnableDMAReq_TX(hi3c->Instance);
+        }
+
+        /* Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+      else
+      {
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmacr) == HAL_OK)
+        {
+          hi3c->hdmacr->XferCpltCallback = NULL;
+          hi3c->hdmacr->XferErrorCallback = NULL;
+        }
+
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmatx) == HAL_OK)
+        {
+          hi3c->hdmatx->XferCpltCallback = NULL;
+          hi3c->hdmatx->XferErrorCallback = NULL;
+        }
+
+        /* Set callback to NULL if DMA started */
+        if (HAL_DMA_Abort(hi3c->hdmarx) == HAL_OK)
+        {
+          hi3c->hdmarx->XferCpltCallback = NULL;
+          hi3c->hdmarx->XferErrorCallback = NULL;
+        }
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_DMA;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+    }
+  }
+  return status;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Controller assign dynamic address (send a broadcast ENTDAA CCC command) in polling mode.
+  * @param  hi3c           : [IN]     Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                   information for the specified I3C.
+  * @param  target_payload : [IN/OUT] Pointer to the returned target payload value.
+  * @param  dynOption      : [IN]     Parameter indicates the Dynamic address assignment option.
+  *                                   It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION.
+  * @param  timeout        : [IN]     Timeout duration in millisecond.
+  * @retval HAL Status     :          Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef  *hi3c,
+                                             uint64_t           *target_payload,
+                                             uint32_t            dynOption,
+                                             uint32_t            timeout)
+{
+  uint32_t tickstart;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on parameters */
+  assert_param(IS_I3C_ENTDAA_OPTION(dynOption));
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    if (target_payload == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Launch a RSTDAA procedure before launch ENTDAA */
+      if ((dynOption == I3C_RSTDAA_THEN_ENTDAA) &&
+          ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN)))
+      {
+        /* Set handle transfer parameters */
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+        hi3c->State     = HAL_I3C_STATE_BUSY_DAA;
+
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+
+        /* Enable arbitration header */
+        LL_I3C_EnableArbitrationHeader(hi3c->Instance);
+
+        /* Write CCC information in the control register */
+        LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_STOP);
+
+        /* Wait Frame completion flag */
+        status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_FCF, RESET, timeout, tickstart);
+
+        /* Clear frame complete flag */
+        if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+        {
+          LL_I3C_ClearFlag_FC(hi3c->Instance);
+        }
+
+        /* Check on error flag */
+        if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+        {
+          /* Clear error flag */
+          LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+          /* Update handle error code parameter */
+          I3C_GetErrorSources(hi3c);
+
+          status = HAL_ERROR;
+        }
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+
+      if (status == HAL_OK)
+      {
+        /* check on the State */
+        if ((handle_state == HAL_I3C_STATE_READY) || (handle_state == HAL_I3C_STATE_LISTEN) ||
+            (handle_state == HAL_I3C_STATE_BUSY_DAA))
+        {
+          /* Check on the state */
+          if (handle_state != HAL_I3C_STATE_BUSY_DAA)
+          {
+            /* Set handle transfer parameters */
+            hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+            hi3c->State     = HAL_I3C_STATE_BUSY_DAA;
+
+            /* Init tickstart for timeout management */
+            tickstart = HAL_GetTick();
+
+            /* Enable arbitration header */
+            LL_I3C_EnableArbitrationHeader(hi3c->Instance);
+
+            /* Write CCC information in the control register */
+            LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP);
+          }
+          else
+          {
+            /* Init tickstart for timeout management */
+            tickstart = HAL_GetTick();
+          }
+
+          /* Wait frame complete flag or TX FIFO not full flag until timeout */
+          status = I3C_WaitOnDAAUntilTimeout(hi3c, timeout, tickstart);
+
+          /* Check TX FIFO not full flag */
+          if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET)
+          {
+            /* Check on the Rx FIFO threshold to know the Rx treatment process : byte or word */
+            if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+            {
+              /* For loop to get target payload */
+              for (uint32_t index = 0U; index < 8U; index++)
+              {
+                /* Retrieve payload byte by byte */
+                *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(hi3c->Instance) << (index * 8U));
+              }
+            }
+            else
+            {
+              /* Retrieve first 32 bits payload */
+              *target_payload = (uint64_t)LL_I3C_ReceiveData32(hi3c->Instance);
+
+              /* Retrieve second 32 bits payload */
+              *target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(hi3c->Instance) << 32U);
+            }
+
+            status = HAL_BUSY;
+          }
+          /* Check on frame complete flag */
+          else
+          {
+            /* Clear frame complete flag */
+            if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+            {
+              /* Clear frame complete flag */
+              LL_I3C_ClearFlag_FC(hi3c->Instance);
+            }
+            /* Update handle state parameter */
+            I3C_StateUpdate(hi3c);
+          }
+        }
+        else
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+          status = HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Controller assign dynamic address (send a broadcast ENTDAA CCC command) in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  dynOption  : [IN]  Parameter indicates the Dynamic address assignment option.
+  *                            It can be one value of @ref I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on parameters */
+  assert_param(IS_I3C_ENTDAA_OPTION(dynOption));
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY_DAA;
+      hi3c->XferISR   = I3C_Ctrl_DAA_ISR;
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Dynamic Address Assignment process interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_DAA_IT);
+
+      /* Enable arbitration header */
+      LL_I3C_EnableArbitrationHeader(hi3c->Instance);
+
+      /* Launch a RSTDAA procedure before launch ENTDAA */
+      if (dynOption == I3C_RSTDAA_THEN_ENTDAA)
+      {
+        /* Write RSTDAA CCC information in the control register */
+        LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_RSTDAA, 0U, LL_I3C_GENERATE_RESTART);
+      }
+      else
+      {
+        /* Write ENTDAA CCC information in the control register */
+        LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP);
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Controller set dynamic address.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  devAddress : [IN]  Value of the dynamic address to be assigned.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAddress)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check if Tx FIFO requests data */
+    if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET)
+    {
+      /* Write device address in the TDR register */
+      LL_I3C_TransmitData8(hi3c->Instance, devAddress);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Check if I3C target device is ready for communication.
+  * @param  hi3c       : [IN] Pointer to a I3C_HandleTypeDef structure that contains
+  *                           the configuration information for the specified I3C.
+  * @param  devAddress : [IN] Value of the device dynamic address.
+  * @param  trials     : [IN] Number of trials
+  * @param  timeout    : [IN] Timeout duration
+  * @retval HAL Status :      Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c,
+                                                 uint8_t            devAddress,
+                                                 uint32_t           trials,
+                                                 uint32_t           timeout)
+{
+  I3C_DeviceTypeDef device;
+  HAL_StatusTypeDef status;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Initiate a device address */
+    device.Address = devAddress;
+
+    /* Initiate a message type */
+    device.MessageType = LL_I3C_CONTROLLER_MTYPE_PRIVATE;
+
+    /* Check if the device is ready*/
+    status = I3C_Ctrl_IsDevice_Ready(hi3c, &device, trials, timeout);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Check if I2C target device is ready for communication.
+  * @param  hi3c       : [IN] Pointer to a I3C_HandleTypeDef structure that contains
+  *                           the configuration information for the specified I3C.
+  * @param  devAddress : [IN] Value of the device dynamic address.
+  * @param  trials     : [IN] Number of trials
+  * @param  timeout    : [IN] Timeout duration
+  * @retval HAL Status :      Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c,
+                                                 uint8_t            devAddress,
+                                                 uint32_t           trials,
+                                                 uint32_t           timeout)
+{
+  I3C_DeviceTypeDef device;
+  HAL_StatusTypeDef status;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Initiate a device address */
+    device.Address = devAddress;
+
+    /* Initiate a message type */
+    device.MessageType = LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C;
+
+    /* Check if the device is ready*/
+    status = I3C_Ctrl_IsDevice_Ready(hi3c, &device, trials, timeout);
+  }
+
+  return status;
+}
+
+/**
+  * @brief Controller generates arbitration (message header {S/Sr + 0x7E addr + W}) in polling mode.
+  * @param  hi3c       : [IN] Pointer to an I3C_HandleTypeDef structure that contains
+  *                           the configuration information for the specified I3C.
+  * @param  timeout    : [IN] Timeout duration
+  * @retval HAL Status :      Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint32_t timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  __IO uint32_t exit_condition;
+  uint32_t tickstart;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      hi3c->State = HAL_I3C_STATE_BUSY;
+
+      /* Disable exit pattern */
+      LL_I3C_DisableExitPattern(hi3c->Instance);
+      /* Disable reset pattern */
+      LL_I3C_DisableResetPattern(hi3c->Instance);
+
+      /* Write message control register */
+      WRITE_REG(hi3c->Instance->CR, LL_I3C_CONTROLLER_MTYPE_HEADER | LL_I3C_GENERATE_STOP);
+
+      /* Calculate exit_condition value based on Frame complete and error flags */
+      exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+
+      tickstart = HAL_GetTick();
+
+      while (exit_condition == 0U)
+      {
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            /* Update I3C error code */
+            hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+
+            break;
+          }
+        }
+        /* Calculate exit_condition value based on Frame complete and error flags */
+        exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Check if the FCF flag has been set */
+        if (__HAL_I3C_GET_FLAG(hi3c, I3C_EVR_FCF) == SET)
+        {
+          /* Clear frame complete flag */
+          LL_I3C_ClearFlag_FC(hi3c->Instance);
+        }
+        else
+        {
+          /* Clear error flag */
+          LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+          /* Update handle error code parameter */
+          I3C_GetErrorSources(hi3c);
+
+          /* Update returned status value */
+          status = HAL_ERROR;
+        }
+      }
+
+      /* At the end of Rx process update state to Previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Exported_Functions_Group6 Target operational functions.
+  * @brief    I3C target operational functions.
+  *
+@verbatim
+ =======================================================================================================================
+                                    ##### Target operational functions #####
+ =======================================================================================================================
+    [..]  This subsection provides a set of functions allowing to manage target I3C operation.
+
+         (+) Call the function HAL_I3C_Tgt_Transmit() to transmit private data in polling mode.
+         (+) Call the function HAL_I3C_Tgt_Transmit_IT() to transmit private data in interrupt mode.
+         (+) Call the function HAL_I3C_Tgt_Transmit_DMA() to transmit private data in DMA mode.
+         (+) Call the function HAL_I3C_Tgt_Receive() to receive private data in polling mode.
+         (+) Call the function HAL_I3C_Tgt_Receive_IT() to receive private data in interrupt mode.
+         (+) Call the function HAL_I3C_Tgt_Receive_DMA() to receive private data in DMA mode.
+         (+) Call the function HAL_I3C_Tgt_ControlRoleReq() to send a control-role request in polling mode.
+         (+) Call the function HAL_I3C_Tgt_ControlRoleReq_IT() to send a control-role request in interrupt mode.
+         (+) Call the function HAL_I3C_Tgt_HotJoinReq() to send a Hot-Join request in polling mode.
+         (+) Call the function HAL_I3C_Tgt_HotJoinReq_IT() to send a Hot-Join request in interrupt mode.
+         (+) Call the function HAL_I3C_Tgt_IBIReq() to send an IBI request in polling mode.
+         (+) Call the function HAL_I3C_Tgt_IBIReq_IT() to send an IBI request in interrupt mode.
+
+         (+) Those functions are called only when mode is Target.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Target transmit private data in polling mode.
+  * @note   Target FIFO preload data is forced within this API for timing purpose.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data
+  *                            to transmit in bytes (TxBuf.Size)).
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  uint32_t it_source;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    it_source = READ_REG(hi3c->Instance->IER);
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->TxBuf.pBuffer == NULL) || (pXferData->TxBuf.Size == 0U))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* check if DEF or GRP CCC notifications are enabled */
+    else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) ||
+             (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->State       = HAL_I3C_STATE_BUSY_TX;
+      hi3c->pXferData   = pXferData;
+      hi3c->TxXferCount = pXferData->TxBuf.Size;
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+      }
+
+      /* Set Preload information */
+      LL_I3C_ConfigTxPreload(hi3c->Instance, (uint16_t)hi3c->pXferData->TxBuf.Size);
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Do while until FC (Frame Complete) is set or timeout */
+      do
+      {
+        /* Call transmit treatment function */
+        hi3c->ptrTxFunc(hi3c);
+
+        /* Check for the Timeout */
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+
+            break;
+          }
+        }
+        /* Exit loop on Frame complete or error flags */
+      } while ((READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)) == 0U);
+
+      /* Clear frame complete flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+      {
+        LL_I3C_ClearFlag_FC(hi3c->Instance);
+      }
+
+      /* Check if all data bytes are transmitted */
+      if ((LL_I3C_GetXferDataCount(hi3c->Instance) != hi3c->pXferData->TxBuf.Size) && (status == HAL_OK))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+        status = HAL_ERROR;
+      }
+
+      /* Check on error flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        /* Update returned status value */
+        status = HAL_ERROR;
+      }
+
+      /* At the end of Tx process update state to Previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Target transmit private data in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data
+  *                            to transmit in bytes (TxBuf.Size)).
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t it_source;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    it_source = READ_REG(hi3c->Instance->IER);
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->TxBuf.pBuffer == NULL) || (pXferData->TxBuf.Size == 0U))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* check if DEF and GRP CCC notifications are enabled */
+    else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) ||
+             (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->State       = HAL_I3C_STATE_BUSY_TX;
+      hi3c->pXferData   = pXferData;
+      hi3c->TxXferCount = pXferData->TxBuf.Size;
+      hi3c->XferISR     = I3C_Tgt_Tx_ISR;
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrTxFunc = &I3C_TransmitWordTreatment;
+      }
+
+      /* Set Preload information */
+      LL_I3C_ConfigTxPreload(hi3c->Instance, (uint16_t)hi3c->pXferData->TxBuf.Size);
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Tx process interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_TX_IT);
+    }
+  }
+
+  return status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Target transmit private data in DMA mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required transmission buffers
+  *                            information (Pointer to the Tx buffer (TxBuf.pBuffer) and size of data
+  *                            to transmit in bytes (TxBuf.Size)).
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
+{
+  HAL_StatusTypeDef tx_dma_status;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t size_align_word;
+  uint32_t it_source;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    it_source = READ_REG(hi3c->Instance->IER);
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->TxBuf.pBuffer == NULL) || (pXferData->TxBuf.Size == 0U))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on hdmatx handle */
+    else if (hi3c->hdmatx == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* check if DEF and GRP CCC notifications are enabled */
+    else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) ||
+             (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->State       = HAL_I3C_STATE_BUSY_TX;
+      hi3c->pXferData   = pXferData;
+      hi3c->TxXferCount = pXferData->TxBuf.Size;
+      hi3c->XferISR     = I3C_Tgt_Tx_DMA_ISR;
+
+      /* Set Preload information */
+      LL_I3C_ConfigTxPreload(hi3c->Instance, (uint16_t)hi3c->pXferData->TxBuf.Size);
+
+      /*------------------------------------ I3C DMA channel for the Tx Data -----------------------------------------*/
+      /* Set the I3C DMA transfer complete callback */
+      hi3c->hdmatx->XferCpltCallback = I3C_DMADataTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi3c->hdmatx->XferErrorCallback = I3C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi3c->hdmatx->XferHalfCpltCallback = NULL;
+      hi3c->hdmatx->XferAbortCallback    = NULL;
+
+      /* Check on the Tx threshold to know the Tx treatment process : byte or word */
+      if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_1_4)
+      {
+        /* assert that DMA source and destination width are configured in byte */
+        assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+        assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+        /* Enable the Tx data DMA channel */
+        tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                         (uint32_t)&hi3c->Instance->TDR, hi3c->pXferData->TxBuf.Size);
+      }
+      else
+      {
+        /* assert that DMA source and destination width are configured in word */
+        assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmatx->Init.SrcDataWidth));
+        assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmatx->Init.DestDataWidth));
+
+        /* Check to align data size in words */
+        if ((hi3c->pXferData->TxBuf.Size % 4U) == 0U)
+        {
+          /* Keep the same size */
+          size_align_word = hi3c->pXferData->TxBuf.Size;
+        }
+        else
+        {
+          /* Modify size to be multiple of 4 */
+          size_align_word = ((hi3c->pXferData->TxBuf.Size + 4U) - (hi3c->pXferData->TxBuf.Size % 4U));
+        }
+
+        /* Enable the Tx data DMA channel */
+        tx_dma_status = HAL_DMA_Start_IT(hi3c->hdmatx, (uint32_t)hi3c->pXferData->TxBuf.pBuffer,
+                                         (uint32_t)&hi3c->Instance->TDWR, size_align_word);
+      }
+
+      /* Check if DMA process is well started */
+      if (tx_dma_status == HAL_OK)
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+        of I3C interrupt handle execution before current process unlock */
+
+        /* Enable Tx process interrupts */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update the number of remaining data bytes */
+        hi3c->TxXferCount = 0U;
+
+        /* Enable Tx data DMA Request */
+        LL_I3C_EnableDMAReq_TX(hi3c->Instance);
+      }
+      else
+      {
+        /* Set callback to NULL if DMA started */
+        hi3c->hdmatx->XferCpltCallback = NULL;
+        hi3c->hdmatx->XferErrorCallback = NULL;
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_DMA;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+    }
+  }
+
+  return status;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Target receive private data in polling mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
+  *                            information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data
+  *                            to be received in bytes (RxBuf.Size)).
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  uint32_t it_source;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    it_source = READ_REG(hi3c->Instance->IER);
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL) || (pXferData->RxBuf.Size == 0U))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* check if DEF and GRP CCC notifications are enabled */
+    else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) ||
+             (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->State       = HAL_I3C_STATE_BUSY_RX;
+      hi3c->pXferData   = pXferData;
+      hi3c->RxXferCount = pXferData->RxBuf.Size;
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+      }
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Do while until FC (Frame Complete) is set or timeout */
+      do
+      {
+        if (hi3c->RxXferCount > 0U)
+        {
+          /* Call receive treatment function */
+          hi3c->ptrRxFunc(hi3c);
+        }
+
+        /* Check for the Timeout */
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+
+            break;
+          }
+        }
+        /* Exit loop on Frame complete or error flags */
+      } while ((READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF)) == 0U);
+
+      /* Clear frame complete flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_FCF) == SET)
+      {
+        LL_I3C_ClearFlag_FC(hi3c->Instance);
+      }
+
+      /* Check if all data bytes are received */
+      if ((LL_I3C_GetXferDataCount(hi3c->Instance) != hi3c->pXferData->RxBuf.Size) && (status == HAL_OK))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+        status = HAL_ERROR;
+      }
+
+      /* Check on error flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        status = HAL_ERROR;
+      }
+
+      /* At the end of Rx process update state to previous state */
+      I3C_StateUpdate(hi3c);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Target receive private data in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
+  *                            information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data
+  *                            to be received in bytes (RxBuf.Size)).
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t it_source;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    it_source = READ_REG(hi3c->Instance->IER);
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL) || (pXferData->RxBuf.Size == 0U))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* check if DEF and GRP CCC notifications are enabled */
+    else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) ||
+             (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->State       = HAL_I3C_STATE_BUSY_RX;
+      hi3c->pXferData   = pXferData;
+      hi3c->RxXferCount = pXferData->RxBuf.Size;
+      hi3c->XferISR     = I3C_Tgt_Rx_ISR;
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* Set byte treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveByteTreatment;
+      }
+      else
+      {
+        /* Set word treatment function pointer */
+        hi3c->ptrRxFunc = &I3C_ReceiveWordTreatment;
+      }
+
+      /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+      of I3C interrupt handle execution before current process unlock */
+
+      /* Enable Rx process interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_RX_IT);
+    }
+  }
+
+  return status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Target receive private data in DMA mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  pXferData  : [IN]  Pointer to an I3C_XferTypeDef structure that contains required reception buffers
+  *                            information (Pointer to the Rx buffer (RxBuf.pBuffer) and size of data
+  *                            to be received in bytes (RxBuf.Size)).
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData)
+{
+  HAL_StatusTypeDef rx_dma_status;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t size_align_word;
+  uint32_t it_source;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    it_source = READ_REG(hi3c->Instance->IER);
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on user parameters */
+    if ((pXferData == NULL) || (pXferData->RxBuf.pBuffer == NULL) || (pXferData->RxBuf.Size == 0U))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on hdmarx handle */
+    else if (hi3c->hdmarx == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DMA_PARAM;
+      status = HAL_ERROR;
+
+      /* Update handle state parameter */
+      I3C_StateUpdate(hi3c);
+    }
+    /* check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* check if DEF and GRP CCC notifications are enabled */
+    else if ((I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_DEFIE) != RESET) ||
+             (I3C_CHECK_IT_SOURCE(it_source, HAL_I3C_IT_GRPIE) != RESET))
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Set handle transfer parameters */
+      hi3c->ErrorCode   = HAL_I3C_ERROR_NONE;
+      hi3c->State       = HAL_I3C_STATE_BUSY_RX;
+      hi3c->pXferData   = pXferData;
+      hi3c->RxXferCount = pXferData->RxBuf.Size;
+      hi3c->XferISR     = I3C_Tgt_Rx_DMA_ISR;
+
+      /*------------------------------------ I3C DMA channel for the Rx Data ---------------------------------------*/
+      /* Set the I3C DMA transfer complete callback */
+      hi3c->hdmarx->XferCpltCallback = I3C_DMADataReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi3c->hdmarx->XferErrorCallback = I3C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi3c->hdmarx->XferHalfCpltCallback = NULL;
+      hi3c->hdmarx->XferAbortCallback    = NULL;
+
+      /* Check on the Rx threshold to know the Rx treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* assert that DMA source and destination width are configured in byte */
+        assert_param(IS_I3C_DMASOURCEBYTE_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+        assert_param(IS_I3C_DMADESTINATIONBYTE_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+        /* Enable the Rx data DMA channel */
+        rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDR,
+                                         (uint32_t)hi3c->pXferData->RxBuf.pBuffer, hi3c->pXferData->RxBuf.Size);
+      }
+      else
+      {
+        /* assert that DMA source and destination width are configured in word */
+        assert_param(IS_I3C_DMASOURCEWORD_VALUE(hi3c->hdmarx->Init.SrcDataWidth));
+        assert_param(IS_I3C_DMADESTINATIONWORD_VALUE(hi3c->hdmarx->Init.DestDataWidth));
+
+        /* Check to align data size in words */
+        if ((hi3c->pXferData->RxBuf.Size % 4U) == 0U)
+        {
+          /* Keep the same size */
+          size_align_word = hi3c->pXferData->RxBuf.Size;
+        }
+        else
+        {
+          /* Modify size to be multiple of 4 */
+          size_align_word = ((hi3c->pXferData->RxBuf.Size + 4U) - (hi3c->pXferData->RxBuf.Size % 4U));
+        }
+
+        /* Enable the Rx data DMA channel */
+        rx_dma_status = HAL_DMA_Start_IT(hi3c->hdmarx, (uint32_t)&hi3c->Instance->RDWR,
+                                         (uint32_t)hi3c->pXferData->RxBuf.pBuffer, size_align_word);
+      }
+
+      if (rx_dma_status == HAL_OK)
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process to avoid the risk
+        of I3C interrupt handle execution before current process unlock */
+
+        /* Enable Rx process interrupts */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update the number of remaining data bytes */
+        hi3c->RxXferCount = 0U;
+
+        /* Enable Rx data DMA Request */
+        LL_I3C_EnableDMAReq_RX(hi3c->Instance);
+      }
+      else
+      {
+        /* Set callback to NULL if DMA started */
+        hi3c->hdmarx->XferCpltCallback = NULL;
+        hi3c->hdmarx->XferErrorCallback = NULL;
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_DMA;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+      }
+    }
+  }
+
+  return status;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Target send control role request in polling mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq(I3C_HandleTypeDef *hi3c, uint32_t timeout)
+{
+  uint32_t tickstart;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Verify if control role request feature is enabled */
+      if (LL_I3C_IsEnabledControllerRoleReq(hi3c->Instance) != 1U)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY;
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Request Controllership */
+      LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ, 0U);
+
+      /* Wait Controllership completion confirmation flag */
+      status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_CRUPDF, RESET, timeout, tickstart);
+
+      /* Clear Control role request flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_CRUPDF) == SET)
+      {
+        LL_I3C_ClearFlag_CRUPD(hi3c->Instance);
+      }
+
+      /* Check on error flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        /* Update handle state parameter to previous state */
+        I3C_StateUpdate(hi3c);
+
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Update handle state parameter to previous state */
+        I3C_StateUpdate(hi3c);
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Target send control role request in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq_IT(I3C_HandleTypeDef *hi3c)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Verify if control role request feature is enabled */
+      if (LL_I3C_IsEnabledControllerRoleReq(hi3c->Instance) != 1U)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Update handle parameters */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY;
+      hi3c->XferISR   = I3C_Tgt_CtrlRole_ISR;
+
+      /* Enable controller-role update and error interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_CTRLROLE);
+
+      /* Request Controllership */
+      LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ, 0U);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Target send hot join request in polling mode.
+  * @param  hi3c       : [IN]     Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                               information for the specified I3C.
+  * @param  pAddress   : [IN/OUT] Pointer to the target own dynamic address assigned by the controller.
+  * @param  timeout    : [IN]     Timeout duration in millisecond.
+  * @retval HAL Status :          Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq(I3C_HandleTypeDef *hi3c, uint8_t *pAddress, uint32_t timeout)
+{
+  uint32_t tickstart;
+  HAL_I3C_StateTypeDef handle_state;
+  uint32_t valid_dynamic_address;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on the pAddress value */
+    if (pAddress == NULL)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check on the Mode */
+    else if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    else
+    {
+      /* Check on the hot join request feature */
+      if (LL_I3C_IsEnabledHotJoin(hi3c->Instance) != 1U)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY;
+
+      /* Init tickstart for timeout management */
+      tickstart = HAL_GetTick();
+
+      /* Request hot join */
+      LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_HOT_JOIN, 0U);
+
+      /* Wait hot join completion confirmation flag */
+      status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_DAUPDF, RESET, timeout, tickstart);
+
+      /* Clear dynamic address update flag */
+      if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_DAUPDF) == SET)
+      {
+        LL_I3C_ClearFlag_DAUPD(hi3c->Instance);
+      }
+
+      /* Get dynamic address validity flag */
+      valid_dynamic_address = LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance);
+
+      /* Check the validity of the own dynamic address */
+      if (valid_dynamic_address == 0U)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_DYNAMIC_ADDR;
+        status = HAL_ERROR;
+
+        /* Update handle state parameter to previous state */
+        I3C_StateUpdate(hi3c);
+      }
+      /* Check on error flag */
+      else if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+      {
+        /* Clear error flag */
+        LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+        /* Update handle error code parameter */
+        I3C_GetErrorSources(hi3c);
+
+        /* Update handle state parameter to previous state */
+        I3C_StateUpdate(hi3c);
+
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Update handle state parameter to previous state */
+        I3C_StateUpdate(hi3c);
+
+        /* Get assigned dynamic address */
+        *pAddress = LL_I3C_GetOwnDynamicAddress(hi3c->Instance);
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Target send hot join request in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                            information for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq_IT(I3C_HandleTypeDef *hi3c)
+{
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* Check on the hot join request feature */
+    else if (LL_I3C_IsEnabledHotJoin(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Update handle parameters */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY;
+      hi3c->XferISR   = I3C_Tgt_HotJoin_ISR;
+
+      /* Enable dynamic address update and error interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_HOTJOIN);
+
+      /* Request hot join */
+      LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_HOT_JOIN, 0U);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Target send IBI request in polling mode.
+  * @param  hi3c        : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                             information for the specified I3C.
+  * @param  pPayload    : [IN]  Pointer to the buffer contains the payload data.
+  * @param  payloadSize : [IN]  Payload buffer size in bytes.
+  * @param  timeout     : [IN]  Timeout duration in millisecond.
+  * @retval HAL Status  :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload,
+                                     uint8_t payloadSize, uint32_t timeout)
+{
+  uint32_t tickstart;
+  uint32_t payload_value = 0U;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Verify if IBI request feature is enabled*/
+      if (LL_I3C_IsEnabledIBI(hi3c->Instance) != 1U)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Update handle parameters */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY;
+
+      /* Check on the IBI additional data */
+      if (LL_I3C_GetDeviceIBIPayload(hi3c->Instance) == LL_I3C_IBI_ADDITIONAL_DATA)
+      {
+        /* Check on the pPayload and payloadSize values */
+        if ((pPayload == NULL) || (payloadSize == 0U))
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Update handle state parameter */
+          I3C_StateUpdate(hi3c);
+        }
+        else
+        {
+          /* For loop to calculate the payload value */
+          for (uint32_t index = 0U; index < payloadSize; index++)
+          {
+            payload_value |= ((uint32_t)pPayload[index] << (index * 8U));
+          }
+
+          /* Load IBI payload data */
+          LL_I3C_SetIBIPayload(hi3c->Instance, payload_value);
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+
+        /* Request IBI */
+        LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_IBI, payloadSize);
+
+        /* Wait IBI completion confirmation flag */
+        status = I3C_WaitOnFlagUntilTimeout(hi3c, HAL_I3C_FLAG_IBIENDF, RESET, timeout, tickstart);
+
+        if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_IBIENDF) == SET)
+        {
+          /* Clear IBI end process flag */
+          LL_I3C_ClearFlag_IBIEND(hi3c->Instance);
+        }
+
+        /* Check on error flag value */
+        if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+        {
+          /* Clear error flag */
+          LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+          /* Update handle error code parameter */
+          I3C_GetErrorSources(hi3c);
+
+          /* Update handle state parameter to previous state */
+          I3C_StateUpdate(hi3c);
+
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Update handle state parameter to previous state */
+          I3C_StateUpdate(hi3c);
+        }
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Target send IBI request in interrupt mode.
+  * @param  hi3c        : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                             information for the specified I3C.
+  * @param  pPayload    : [IN]  Pointer to the buffer contains the payload data.
+  * @param  payloadSize : [IN]  Payload buffer size in bytes.
+  * @retval HAL Status  :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq_IT(I3C_HandleTypeDef *hi3c, const uint8_t *pPayload, uint8_t payloadSize)
+{
+  uint32_t payload_value = 0U;
+  HAL_I3C_StateTypeDef handle_state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the instance and the mode parameters */
+    assert_param(IS_I3C_ALL_INSTANCE(hi3c->Instance));
+    assert_param(IS_I3C_MODE(hi3c->Mode));
+
+    /* Get I3C handle state */
+    handle_state = hi3c->State;
+
+    /* Check on the Mode */
+    if (hi3c->Mode != HAL_I3C_MODE_TARGET)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    /* check on the State */
+    else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+    {
+      status = HAL_BUSY;
+    }
+    /* Verify the dynamic address validity */
+    else if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) != 1U)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Verify if IBI request feature is enabled */
+      if (LL_I3C_IsEnabledIBI(hi3c->Instance) != 1U)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Update handle parameters */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+      hi3c->State     = HAL_I3C_STATE_BUSY;
+      hi3c->XferISR   = I3C_Tgt_IBI_ISR;
+
+      /* Check on the IBI additional data */
+      if (LL_I3C_GetDeviceIBIPayload(hi3c->Instance) == LL_I3C_IBI_ADDITIONAL_DATA)
+      {
+        /* Check on the pPayload and payloadSize values */
+        if ((pPayload == NULL) || (payloadSize == 0U))
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+
+          /* Update handle state parameter */
+          I3C_StateUpdate(hi3c);
+        }
+        else
+        {
+          /* For loop to calculate the payload value */
+          for (uint32_t index = 0U; index < payloadSize; index++)
+          {
+            payload_value |= ((uint32_t)pPayload[index] << (index * 8U));
+          }
+
+          /* Load IBI payload data */
+          LL_I3C_SetIBIPayload(hi3c->Instance, payload_value);
+        }
+      }
+
+      /* Enable IBI end and error interrupts */
+      I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_IBI);
+
+      /* Request IBI */
+      LL_I3C_TargetHandleMessage(hi3c->Instance, LL_I3C_TARGET_MTYPE_IBI, payloadSize);
+    }
+  }
+
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup I3C_Exported_Functions_Group7 Generic and Common functions.
+  * @brief    I3C generic and common functions.
+  *
+@verbatim
+ =======================================================================================================================
+                                        ##### Generic and Common functions #####
+ =======================================================================================================================
+    [..]  This subsection provides a set of functions allowing to Abort transfer or to get in run-time the status
+          of the peripheral.
+
+         (+) Call the function HAL_I3C_Abort_IT() to abort the current transfer either in DMA or IT.
+         (+) Call the function HAL_I3C_GetState() to get the I3C handle state.
+         (+) Call the function HAL_I3C_GetMode() to get the I3C handle mode.
+         (+) Call the function HAL_I3C_GetError() to get the error code.
+         (+) Call the function HAL_I3C_Get_ENTDAA_Payload_Info() to get BCR, DCR and PID information after ENTDAA.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Abort an I3C IT or DMA process communication with Interrupt.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                            information for the specified I3C.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Abort_IT(I3C_HandleTypeDef *hi3c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hi3c->State != HAL_I3C_STATE_ABORT)
+    {
+      /* Set State at HAL_I3C_STATE_ABORT */
+      hi3c->State     = HAL_I3C_STATE_ABORT;
+
+      /* Disable Error Interrupts */
+      __HAL_I3C_DISABLE_IT(hi3c, HAL_I3C_IT_ERRIE);
+
+      hi3c->XferISR   = I3C_Abort_ISR;
+
+      /* Flush the different Fifos to generate an automatic stop mode link to underflow or overflow detection timeout */
+      /* Flush the content of Tx Fifo */
+      LL_I3C_RequestTxFIFOFlush(hi3c->Instance);
+
+      /* Flush the content of Rx Fifo */
+      LL_I3C_RequestRxFIFOFlush(hi3c->Instance);
+
+      /* Check on the I3C mode: Control and status FIFOs available only with controller mode */
+      if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER)
+      {
+        /* Flush the content of Control Fifo */
+        LL_I3C_RequestControlFIFOFlush(hi3c->Instance);
+
+        /* Flush the content of Status Fifo */
+        LL_I3C_RequestStatusFIFOFlush(hi3c->Instance);
+      }
+
+      /* Disable all DMA Requests */
+      LL_I3C_DisableDMAReq_Control(hi3c->Instance);
+      LL_I3C_DisableDMAReq_RX(hi3c->Instance);
+      LL_I3C_DisableDMAReq_TX(hi3c->Instance);
+      LL_I3C_DisableDMAReq_Status(hi3c->Instance);
+
+      if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER)
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process
+        to avoid the risk of I3C interrupt handle execution before current
+        process unlock */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT);
+      }
+      else
+      {
+        /* Note : The I3C interrupts must be enabled after unlocking current process
+        to avoid the risk of I3C interrupt handle execution before current
+        process unlock */
+        I3C_Enable_IRQ(hi3c, I3C_XFER_TARGET_RX_IT);
+      }
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Return the I3C handle state.
+  * @param  hi3c      : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                           information for the specified I3C.
+  * @retval HAL State : [OUT] Value from HAL_I3C_StateTypeDef enumeration.
+  */
+HAL_I3C_StateTypeDef HAL_I3C_GetState(const I3C_HandleTypeDef *hi3c)
+{
+  return hi3c->State;
+}
+
+/**
+  * @brief  Returns the I3C handle mode.
+  * @param  hi3c     : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                          information for the specified I3C.
+  * @retval HAL Mode : [OUT] Value from HAL_I3C_ModeTypeDef enumeration.
+  */
+HAL_I3C_ModeTypeDef HAL_I3C_GetMode(const I3C_HandleTypeDef *hi3c)
+{
+  return hi3c->Mode;
+}
+
+/**
+  * @brief  Return the I3C error code.
+  * @param  hi3c           : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                information for the specified I3C.
+  * @retval I3C Error Code : [OUT] Value from @ref I3C_ERROR_CODE_DEFINITION.
+  */
+uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c)
+{
+  return hi3c->ErrorCode;
+}
+
+/**
+  * @brief  Target/Controller Get Common Command Code Information updated after event.
+  * @param  hi3c     : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                         for the specified I3C.
+  * @param  notifyId : [IN] Parameter indicates which notification is signaled.
+  *                         It can be a combination of value of @ref HAL_I3C_Notification_ID_definition.
+  * @param  pCCCInfo : [IN/OUT] Pointer to an I3C_CCCInfoTypeDef structure that contains the CCC information
+  *                             updated after CCC event.
+  * @retval HAL Status : Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c,
+                                     uint32_t notifyId,
+                                     I3C_CCCInfoTypeDef *pCCCInfo)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check on user parameters */
+    if (pCCCInfo == NULL)
+    {
+      /* Update handle error code parameter */
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    /* Check the I3C state */
+    else if (hi3c->State == HAL_I3C_STATE_RESET)
+    {
+      /* Update handle error code parameter */
+      hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Retrieve Target Dynamic Address value and Validity (target/controller) */
+      if ((notifyId & EVENT_ID_DAU) == EVENT_ID_DAU)
+      {
+        pCCCInfo->DynamicAddrValid = LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance);
+        pCCCInfo->DynamicAddr = LL_I3C_GetOwnDynamicAddress(hi3c->Instance);
+      }
+
+      /* Retrieve Maximum Write Data Length (target) */
+      if ((notifyId & EVENT_ID_SETMWL) == EVENT_ID_SETMWL)
+      {
+        pCCCInfo->MaxWriteLength = LL_I3C_GetMaxWriteLength(hi3c->Instance);
+      }
+
+      /* Retrieve Maximum Read Data Length (target) */
+      if ((notifyId & EVENT_ID_SETMRL) == EVENT_ID_SETMRL)
+      {
+        pCCCInfo->MaxReadLength = LL_I3C_GetMaxReadLength(hi3c->Instance);
+      }
+
+      /* Retrieve Reset Action/Level on received reset pattern (target) */
+      if ((notifyId & EVENT_ID_RSTACT) == EVENT_ID_RSTACT)
+      {
+        pCCCInfo->ResetAction = LL_I3C_GetResetAction(hi3c->Instance);
+      }
+
+      /* Retrieve Activity State (target) */
+      if ((notifyId & EVENT_ID_ENTASx) == EVENT_ID_ENTASx)
+      {
+        pCCCInfo->ActivityState = LL_I3C_GetActivityState(hi3c->Instance);
+      }
+
+      /* Retrieve Interrupt allowed status (target) */
+      if ((notifyId & EVENT_ID_ENEC_DISEC) == EVENT_ID_ENEC_DISEC)
+      {
+        pCCCInfo->HotJoinAllowed = LL_I3C_IsEnabledHotJoin(hi3c->Instance);
+        pCCCInfo->InBandAllowed = LL_I3C_IsEnabledIBI(hi3c->Instance);
+        pCCCInfo->CtrlRoleAllowed = LL_I3C_IsEnabledControllerRoleReq(hi3c->Instance);
+      }
+
+      /* Retrieve In Band Interrupt information (controller) */
+      if ((notifyId & EVENT_ID_IBI) == EVENT_ID_IBI)
+      {
+        pCCCInfo->IBICRTgtAddr = LL_I3C_GetIBITargetAddr(hi3c->Instance);
+        pCCCInfo->IBITgtNbPayload = LL_I3C_GetNbIBIAddData(hi3c->Instance);
+        pCCCInfo->IBITgtPayload = LL_I3C_GetIBIPayload(hi3c->Instance);
+      }
+
+      /* Retrieve Controller role request Interrupt information (controller) */
+      if ((notifyId & EVENT_ID_CR) == EVENT_ID_CR)
+      {
+        pCCCInfo->IBICRTgtAddr = LL_I3C_GetIBITargetAddr(hi3c->Instance);
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Get BCR, DCR and PID information after ENTDAA.
+  * @param  hi3c     : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                         for the specified I3C.
+  * @param  ENTDAA_payload  :[IN] Payload received after ENTDAA
+  * @param  pENTDAA_payload :[OUT] Pointer to an I3C_ENTDAAPayloadTypeDef structure that contains the BCR, DCR and PID
+  *                          information.
+  * @retval HAL Status : Value from HAL_StatusTypeDef enumeration.
+  */
+HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c,
+                                                  uint64_t ENTDAA_payload,
+                                                  I3C_ENTDAAPayloadTypeDef *pENTDAA_payload)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t BCR;
+  uint64_t PID;
+
+  /* check on the handle */
+  if (hi3c == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check on user parameters */
+    if (pENTDAA_payload == NULL)
+    {
+      /* Update handle error code parameter */
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Get Bus Characterics */
+      BCR = __HAL_I3C_GET_BCR(ENTDAA_payload);
+
+      /* Retrieve BCR information */
+      pENTDAA_payload->BCR.IBIPayload = __HAL_I3C_GET_IBI_PAYLOAD(BCR);
+      pENTDAA_payload->BCR.IBIRequestCapable = __HAL_I3C_GET_IBI_CAPABLE(BCR);
+      pENTDAA_payload->BCR.DeviceRole = __HAL_I3C_GET_CR_CAPABLE(BCR);
+      pENTDAA_payload->BCR.AdvancedCapabilities = I3C_GET_ADVANCED_CAPABLE(BCR);
+      pENTDAA_payload->BCR.OfflineCapable = I3C_GET_OFFLINE_CAPABLE(BCR);
+      pENTDAA_payload->BCR.VirtualTargetSupport = I3C_GET_VIRTUAL_TGT(BCR);
+      pENTDAA_payload->BCR.MaxDataSpeedLimitation = I3C_GET_MAX_DATA_SPEED_LIMIT(BCR);
+
+      /* Get Device Characterics */
+      pENTDAA_payload->DCR = I3C_GET_DCR(ENTDAA_payload);
+
+      /* Get Provisioned ID */
+      PID = I3C_GET_PID(ENTDAA_payload);
+
+      /* Change PID from BigEndian to litlleEndian */
+      PID = (uint64_t)((((uint64_t)I3C_BIG_TO_LITTLE_ENDIAN((uint32_t) PID) << 32)   |
+                        ((uint64_t)I3C_BIG_TO_LITTLE_ENDIAN((uint32_t)(PID >> 32)))) >> 16);
+
+      /* Retrieve PID information*/
+      pENTDAA_payload->PID.MIPIMID = I3C_GET_MIPIMID(PID);
+      pENTDAA_payload->PID.IDTSEL = I3C_GET_IDTSEL(PID);
+      pENTDAA_payload->PID.PartID = I3C_GET_PART_ID(PID);
+      pENTDAA_payload->PID.MIPIID = I3C_GET_MIPIID(PID);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_Private_Functions I3C Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handles target received events.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  uint32_t tmpevent = 0U;
+
+  /* I3C Rx FIFO not empty interrupt Check */
+  if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET)
+  {
+    /* Call receive treatment function */
+    hi3c->ptrRxFunc(hi3c);
+  }
+
+  /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management --------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET)
+  {
+    /* Clear controller-role update flag */
+    LL_I3C_ClearFlag_CRUPD(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_GETACCCR */
+    tmpevent |= EVENT_ID_GETACCCR;
+  }
+
+  /* I3C target receive any direct GETxxx CCC event management -------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GETF) != RESET)
+  {
+    /* Clear GETxxx CCC flag */
+    LL_I3C_ClearFlag_GET(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_GETx */
+    tmpevent |= EVENT_ID_GETx;
+  }
+
+  /* I3C target receive get status command (direct GETSTATUS CCC) event management -----------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_STAF) != RESET)
+  {
+    /* Clear GETSTATUS CCC flag */
+    LL_I3C_ClearFlag_STA(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_GETSTATUS */
+    tmpevent |= EVENT_ID_GETSTATUS;
+  }
+
+  /* I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event management -----------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET)
+  {
+    /* Clear dynamic address update flag */
+    LL_I3C_ClearFlag_DAUPD(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_DAU */
+    tmpevent |= EVENT_ID_DAU;
+  }
+
+  /* I3C target receive maximum write length update (direct SETMWL CCC) event management -----------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MWLUPDF) != RESET)
+  {
+    /* Clear SETMWL CCC flag */
+    LL_I3C_ClearFlag_MWLUPD(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_SETMWL */
+    tmpevent |= EVENT_ID_SETMWL;
+  }
+
+  /* I3C target receive maximum read length update(direct SETMRL CCC) event management -------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_MRLUPDF) != RESET)
+  {
+    /* Clear SETMRL CCC flag */
+    LL_I3C_ClearFlag_MRLUPD(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_SETMRL */
+    tmpevent |= EVENT_ID_SETMRL;
+  }
+
+  /* I3C target detect reset pattern (broadcast or direct RSTACT CCC) event management -------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_RSTF) != RESET)
+  {
+    /* Clear reset pattern flag */
+    LL_I3C_ClearFlag_RST(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_RSTACT */
+    tmpevent |= EVENT_ID_RSTACT;
+  }
+
+  /* I3C target receive activity state update (direct or broadcast ENTASx) CCC event management ----------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_ASUPDF) != RESET)
+  {
+    /* Clear ENTASx CCC flag */
+    LL_I3C_ClearFlag_ASUPD(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_ENTASx */
+    tmpevent |= EVENT_ID_ENTASx;
+  }
+
+  /* I3C target receive a direct or broadcast ENEC/DISEC CCC event management ----------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_INTUPDF) != RESET)
+  {
+    /* Clear ENEC/DISEC CCC flag */
+    LL_I3C_ClearFlag_INTUPD(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_ENEC_DISEC */
+    tmpevent |= EVENT_ID_ENEC_DISEC;
+  }
+
+  /* I3C target receive a broadcast DEFTGTS CCC event management -----------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DEFF) != RESET)
+  {
+    /* Clear DEFTGTS CCC flag */
+    LL_I3C_ClearFlag_DEF(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_DEFTGTS */
+    tmpevent |= EVENT_ID_DEFTGTS;
+  }
+
+  /* I3C target receive a group addressing (broadcast DEFGRPA CCC) event management ----------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_GRPF) != RESET)
+  {
+    /* Clear DEFGRPA CCC flag */
+    LL_I3C_ClearFlag_GRP(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_DEFGRPA */
+    tmpevent |= EVENT_ID_DEFGRPA;
+  }
+
+  /* I3C target wakeup event management ----------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET)
+  {
+    /* Clear WKP flag */
+    LL_I3C_ClearFlag_WKP(hi3c->Instance);
+
+    /* Set Identifier EVENT_ID_WKP */
+    tmpevent |= EVENT_ID_WKP;
+  }
+
+  if (tmpevent != 0U)
+  {
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, tmpevent);
+#else
+    /* Asynchronous receive CCC event Callback */
+    HAL_I3C_NotifyCallback(hi3c, tmpevent);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* Update handle state parameter */
+  I3C_StateUpdate(hi3c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles Controller received events.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* I3C controller receive IBI event management ---------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET)
+  {
+    /* Clear IBI request flag */
+    LL_I3C_ClearFlag_IBI(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_IBI);
+#else
+    /* Asynchronous IBI event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller controller-role request event management ---------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET)
+  {
+    /* Clear controller-role request flag */
+    LL_I3C_ClearFlag_CR(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_CR);
+#else
+    /* Asynchronous controller-role event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller hot-join event management ------------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET)
+  {
+    /* Clear hot-join flag */
+    LL_I3C_ClearFlag_HJ(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_HJ);
+#else
+    /* Asynchronous hot-join event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* Update handle state parameter */
+  I3C_StateUpdate(hi3c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles target hot join event.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_HotJoin_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* I3C target receive a dynamic address update event management */
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_DAUPDF) != RESET)
+  {
+    /* Clear dynamic address update flag */
+    LL_I3C_ClearFlag_DAUPD(hi3c->Instance);
+
+    /* Disable dynamic address update and error interrupts */
+    I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_HOTJOIN);
+
+    /* Check the validity of the own dynamic address */
+    if (LL_I3C_IsEnabledOwnDynAddress(hi3c->Instance) == 1U)
+    {
+      /* Update handle state parameter */
+      I3C_StateUpdate(hi3c);
+
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      /* Call registered callback */
+      hi3c->TgtHotJoinCallback(hi3c, (uint8_t)LL_I3C_GetOwnDynamicAddress(hi3c->Instance));
+#else
+      /* Asynchronous receive ENTDAA/RSTDAA/SETNEWDA CCC event Callback */
+      HAL_I3C_TgtHotJoinCallback(hi3c, (uint8_t)LL_I3C_GetOwnDynamicAddress(hi3c->Instance));
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+    }
+    else
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_DYNAMIC_ADDR;
+
+      /* Call error treatment function */
+      I3C_ErrorTreatment(hi3c);
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles target control role event.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_CtrlRole_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* I3C target complete controller-role hand-off procedure (direct GETACCR CCC) event management -------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRUPDF) != RESET)
+  {
+    /* Clear controller-role update flag */
+    LL_I3C_ClearFlag_CRUPD(hi3c->Instance);
+
+    /* Disable controller-role update and error interrupts */
+    I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_CTRLROLE);
+
+    /* Update handle state parameter */
+    I3C_StateUpdate(hi3c);
+
+    hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_GETACCCR);
+#else
+    /* Asynchronous receive GETACCR CCC event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_GETACCCR);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles target IBI event.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_IBI_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* I3C target IBI end process event management ---------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIENDF) != RESET)
+  {
+    /* Clear IBI end flag */
+    LL_I3C_ClearFlag_IBIEND(hi3c->Instance);
+
+    /* Disable IBI end and error interrupts */
+    I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_IBI);
+
+    /* Update handle state parameter */
+    I3C_StateUpdate(hi3c);
+
+    hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_IBIEND);
+#else
+    /* Asynchronous IBI end event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBIEND);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles target transmit data in Interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that a Tx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_TX)
+  {
+    /* I3C Tx FIFO not full interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET)
+    {
+      if (hi3c->TxXferCount > 0U)
+      {
+        /* Call transmit treatment function */
+        hi3c->ptrTxFunc(hi3c);
+      }
+    }
+
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      /* Check if all data bytes are transmitted */
+      if (LL_I3C_GetXferDataCount(hi3c->Instance) == hi3c->pXferData->TxBuf.Size)
+      {
+        /* Disable Tx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_TX_IT);
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the transmit complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->TgtTxCpltCallback(hi3c);
+#else
+        HAL_I3C_TgtTxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+        /* Call error treatment function */
+        I3C_ErrorTreatment(hi3c);
+      }
+    }
+
+    /* I3C target wakeup event management ----------------------------------*/
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET)
+    {
+      /* Clear WKP flag */
+      LL_I3C_ClearFlag_WKP(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      /* Call registered callback */
+      hi3c->NotifyCallback(hi3c, EVENT_ID_WKP);
+#else
+      /* Asynchronous receive CCC event Callback */
+      HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles target receive data in Interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that an Rx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_RX)
+  {
+    /* I3C Rx FIFO not empty interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET)
+    {
+      if (hi3c->RxXferCount > 0U)
+      {
+        /* Call receive treatment function */
+        hi3c->ptrRxFunc(hi3c);
+      }
+    }
+
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      /* Check if all data bytes are received */
+      if (LL_I3C_GetXferDataCount(hi3c->Instance) == hi3c->pXferData->RxBuf.Size)
+      {
+        /* Disable Rx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_TARGET_RX_IT);
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the receive complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->TgtRxCpltCallback(hi3c);
+#else
+        HAL_I3C_TgtRxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+        /* Call error treatment function */
+        I3C_ErrorTreatment(hi3c);
+      }
+    }
+
+    /* I3C target wakeup event management ----------------------------------*/
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET)
+    {
+      /* Clear WKP flag */
+      LL_I3C_ClearFlag_WKP(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      /* Call registered callback */
+      hi3c->NotifyCallback(hi3c, EVENT_ID_WKP);
+#else
+      /* Asynchronous receive CCC event Callback */
+      HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+    }
+  }
+
+  return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Interrupt Sub-Routine which handles target transmit data in DMA mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that a Tx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_TX)
+  {
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      /* Check if all data bytes are transmitted */
+      if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmatx) == 0U)
+      {
+        /* Disable Tx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Update the number of remaining data bytes */
+        hi3c->TxXferCount = 0U;
+
+        /* Call target transmit complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->TgtTxCpltCallback(hi3c);
+#else
+        HAL_I3C_TgtTxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+        /* Call error treatment function */
+        I3C_ErrorTreatment(hi3c);
+      }
+    }
+
+    /* I3C target wakeup event management ----------------------------------*/
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET)
+    {
+      /* Clear WKP flag */
+      LL_I3C_ClearFlag_WKP(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      /* Call registered callback */
+      hi3c->NotifyCallback(hi3c, EVENT_ID_WKP);
+#else
+      /* Asynchronous receive CCC event Callback */
+      HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles target receive data in DMA mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Tgt_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that a Rx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_RX)
+  {
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      /* Check if all data bytes are received */
+      if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmarx) == 0U)
+      {
+        /* Disable Rx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_DMA);
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Update the number of remaining data bytes */
+        hi3c->RxXferCount = 0U;
+
+        /* Call target receive complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->TgtRxCpltCallback(hi3c);
+#else
+        HAL_I3C_TgtRxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+        /* Call error treatment function */
+        I3C_ErrorTreatment(hi3c);
+      }
+    }
+
+    /* I3C target wakeup event management ----------------------------------*/
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_WKPF) != RESET)
+    {
+      /* Clear WKP flag */
+      LL_I3C_ClearFlag_WKP(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      /* Call registered callback */
+      hi3c->NotifyCallback(hi3c, EVENT_ID_WKP);
+#else
+      /* Asynchronous receive CCC event Callback */
+      HAL_I3C_NotifyCallback(hi3c, EVENT_ID_WKP);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+    }
+  }
+
+  return HAL_OK;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller transmission in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Tx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that a Tx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_TX)
+  {
+    /* Check if Control FIFO requests data */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET)
+    {
+      if (hi3c->ControlXferCount > 0U)
+      {
+        /* Call control data treatment function */
+        I3C_ControlDataTreatment(hi3c);
+      }
+    }
+
+    /* I3C Tx FIFO not full interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET)
+    {
+      if (hi3c->TxXferCount > 0U)
+      {
+        /* Call Transmit treatment function */
+        hi3c->ptrTxFunc(hi3c);
+      }
+    }
+
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      if (hi3c->ControlXferCount == 0U)
+      {
+        /* Disable Tx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT);
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the transmit complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->CtrlTxCpltCallback(hi3c);
+#else
+        HAL_I3C_CtrlTxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the transmit complete callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->CtrlTxCpltCallback(hi3c);
+#else
+        HAL_I3C_CtrlTxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+        /* Then Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller reception in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Rx_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that an Rx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_RX)
+  {
+    /* Check if Control FIFO requests data */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET)
+    {
+      if (hi3c->ControlXferCount > 0U)
+      {
+        /* Call control data treatment function */
+        I3C_ControlDataTreatment(hi3c);
+      }
+    }
+
+    /* I3C Rx FIFO not empty interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET)
+    {
+      if (hi3c->RxXferCount > 0U)
+      {
+        /* Call receive treatment function */
+        hi3c->ptrRxFunc(hi3c);
+      }
+    }
+
+    /* I3C Tx FIFO not full interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET)
+    {
+      if (hi3c->TxXferCount > 0U)
+      {
+        /* Call Transmit treatment function */
+        hi3c->ptrTxFunc(hi3c);
+      }
+    }
+
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      if (hi3c->ControlXferCount == 0U)
+      {
+        /* Disable Rx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT);
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the receive complete callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->CtrlRxCpltCallback(hi3c);
+#else
+        HAL_I3C_CtrlRxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the receive complete callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->CtrlRxCpltCallback(hi3c);
+#else
+        HAL_I3C_CtrlRxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+        /* Then Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller multiple transmission/reception in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that a Tx/Rx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX)
+  {
+    /* Check if Control FIFO requests data */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET)
+    {
+      if (hi3c->ControlXferCount > 0U)
+      {
+        /* Call control data treatment function */
+        I3C_ControlDataTreatment(hi3c);
+      }
+    }
+
+    /* I3C Tx FIFO not full interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET)
+    {
+      if (hi3c->TxXferCount > 0U)
+      {
+        /* Call Transmit treatment function */
+        hi3c->ptrTxFunc(hi3c);
+      }
+    }
+
+    /* I3C Rx FIFO not empty interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET)
+    {
+      if (hi3c->RxXferCount > 0U)
+      {
+        /* Call receive treatment function */
+        hi3c->ptrRxFunc(hi3c);
+      }
+    }
+
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      if (hi3c->ControlXferCount == 0U)
+      {
+        /* Disable Tx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_TX_IT);
+
+        /* Disable Rx process interrupts */
+        I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT);
+
+        /* Update handle state parameter */
+        I3C_StateUpdate(hi3c);
+
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the transmit, receive complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->CtrlMultipleXferCpltCallback(hi3c);
+#else
+        HAL_I3C_CtrlMultipleXferCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Then Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller transmission and Controller received events
+  *         in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Tx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* I3C controller receive IBI event management ---------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET)
+  {
+    /* Clear IBI request flag */
+    LL_I3C_ClearFlag_IBI(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_IBI);
+#else
+    /* Asynchronous IBI event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller controller-role request event management ---------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET)
+  {
+    /* Clear controller-role request flag */
+    LL_I3C_ClearFlag_CR(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_CR);
+#else
+    /* Asynchronous controller-role event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller hot-join event management ------------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET)
+  {
+    /* Clear hot-join flag */
+    LL_I3C_ClearFlag_HJ(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_HJ);
+#else
+    /* Asynchronous hot-join event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* ISR controller transmission */
+  return (I3C_Ctrl_Tx_ISR(hi3c, itMasks));
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller reception and Controller received events in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Rx_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* I3C controller receive IBI event management ---------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET)
+  {
+    /* Clear IBI request flag */
+    LL_I3C_ClearFlag_IBI(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_IBI);
+#else
+    /* Asynchronous IBI event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller controller-role request event management ---------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET)
+  {
+    /* Clear controller-role request flag */
+    LL_I3C_ClearFlag_CR(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_CR);
+#else
+    /* Asynchronous controller-role event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller hot-join event management ------------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET)
+  {
+    /* Clear hot-join flag */
+    LL_I3C_ClearFlag_HJ(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_HJ);
+#else
+    /* Asynchronous hot-join event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* ISR controller reception */
+  return (I3C_Ctrl_Rx_ISR(hi3c, itMasks));
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller multiple transmission/reception  and
+  *         Controller received eventsin interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_Listen_Event_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* I3C controller receive IBI event management ---------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_IBIF) != RESET)
+  {
+    /* Clear IBI request flag */
+    LL_I3C_ClearFlag_IBI(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_IBI);
+#else
+    /* Asynchronous IBI event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_IBI);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller controller-role request event management ---------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CRF) != RESET)
+  {
+    /* Clear controller-role request flag */
+    LL_I3C_ClearFlag_CR(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_CR);
+#else
+    /* Asynchronous controller-role event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_CR);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* I3C controller hot-join event management ------------------------------------------------------------------------*/
+  if (I3C_CHECK_FLAG(itMasks, I3C_EVR_HJF) != RESET)
+  {
+    /* Clear hot-join flag */
+    LL_I3C_ClearFlag_HJ(hi3c->Instance);
+
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+    /* Call registered callback */
+    hi3c->NotifyCallback(hi3c, EVENT_ID_HJ);
+#else
+    /* Asynchronous hot-join event Callback */
+    HAL_I3C_NotifyCallback(hi3c, EVENT_ID_HJ);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+  }
+
+  /* ISR controller transmission/reception */
+  return (I3C_Ctrl_Multiple_Xfer_ISR(hi3c, itMasks));
+}
+/**
+  * @brief  Interrupt Sub-Routine which handles controller CCC Dynamic Address Assignment command in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_DAA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  uint64_t target_payload = 0U;
+
+  /* Check that a Dynamic Address Assignment process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_DAA)
+  {
+    /* I3C Control FIFO not full interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_CFNFF) != RESET)
+    {
+      /* Write ENTDAA CCC information in the control register */
+      LL_I3C_ControllerHandleCCC(hi3c->Instance, I3C_BROADCAST_ENTDAA, 0U, LL_I3C_GENERATE_STOP);
+    }
+
+    /* I3C Tx FIFO not full interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_TXFNFF) != RESET)
+    {
+      /* Check on the Rx FIFO threshold to know the Dynamic Address Assignment treatment process : byte or word */
+      if (LL_I3C_GetRxFIFOThreshold(hi3c->Instance) == LL_I3C_RXFIFO_THRESHOLD_1_4)
+      {
+        /* For loop to get target payload */
+        for (uint32_t index = 0U; index < 8U; index++)
+        {
+          /* Retrieve payload byte by byte */
+          target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData8(hi3c->Instance) << (index * 8U));
+        }
+      }
+      else
+      {
+        /* Retrieve first 32 bits payload */
+        target_payload = (uint64_t)LL_I3C_ReceiveData32(hi3c->Instance);
+
+        /* Retrieve second 32 bits payload */
+        target_payload |= (uint64_t)((uint64_t)LL_I3C_ReceiveData32(hi3c->Instance) << 32U);
+      }
+
+      /* Call the corresponding callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      hi3c->TgtReqDynamicAddrCallback(hi3c, target_payload);
+#else
+      HAL_I3C_TgtReqDynamicAddrCallback(hi3c, target_payload);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */
+    }
+
+    /* I3C frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      /* Disable Dynamic Address Assignment process interrupts */
+      I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_DAA_IT);
+
+      /* Update handle state parameter */
+      I3C_StateUpdate(hi3c);
+
+      hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+      /* Call the Dynamic Address Assignment complete callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+      hi3c->CtrlDAACpltCallback(hi3c);
+#else
+      HAL_I3C_CtrlDAACpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+    }
+  }
+  return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Interrupt Sub-Routine which handles controller transmit data in DMA mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Tx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that a Tx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_TX)
+  {
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmacr) == 0U)
+      {
+        /* Check if all data bytes are transmitted */
+        if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmatx) == 0U)
+        {
+          /* Disable Tx process interrupts */
+          I3C_Disable_IRQ(hi3c, I3C_XFER_DMA);
+
+          /* Update handle state parameter */
+          I3C_StateUpdate(hi3c);
+
+          hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+          /* Update the number of remaining data bytes */
+          hi3c->TxXferCount = 0U;
+
+          /* Call controller transmit complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+          hi3c->CtrlTxCpltCallback(hi3c);
+#else
+          HAL_I3C_CtrlTxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+        }
+        else
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+          /* Call error treatment function */
+          I3C_ErrorTreatment(hi3c);
+        }
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the transmit complete callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->CtrlTxCpltCallback(hi3c);
+#else
+        HAL_I3C_CtrlTxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+        /* Then Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller receive data in DMA mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Rx_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that an Rx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_RX)
+  {
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmacr) == 0U)
+      {
+        /* Check if all data bytes are received */
+        if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmarx) == 0U)
+        {
+          /* Disable Rx process interrupts */
+          I3C_Disable_IRQ(hi3c, I3C_XFER_DMA);
+
+          /* Update handle state parameter */
+          I3C_StateUpdate(hi3c);
+
+          hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+          /* Update the number of remaining data bytes */
+          hi3c->RxXferCount = 0U;
+
+          /* Call controller receive complete callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+          hi3c->CtrlRxCpltCallback(hi3c);
+#else
+          HAL_I3C_CtrlRxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+        }
+        else
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+          /* Call error treatment function */
+          I3C_ErrorTreatment(hi3c);
+        }
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Call the receive complete callback */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+        hi3c->CtrlRxCpltCallback(hi3c);
+#else
+        HAL_I3C_CtrlRxCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+
+        /* Then Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handles controller multiple receive and transmit data in DMA mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_Multiple_Xfer_DMA_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that an Rx or Tx process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_BUSY_TX_RX)
+  {
+    /* I3C target frame complete event Check */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmacr) == 0U)
+      {
+        /* Check if all data bytes are received or transmitted */
+        if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmarx) == 0U)
+        {
+          if (I3C_GET_DMA_REMAIN_DATA(hi3c->hdmatx) == 0U)
+          {
+            /* Disable transfer Tx/Rx process interrupts */
+            I3C_Disable_IRQ(hi3c, I3C_XFER_DMA);
+
+            /* Update handle state parameter */
+            I3C_StateUpdate(hi3c);
+
+            hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+            /* Update the number of remaining data bytes */
+            hi3c->RxXferCount = 0U;
+
+            /* Update the number of remaining data bytes */
+            hi3c->TxXferCount = 0U;
+
+            /* Call controller transmit, receive complete callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U)
+            hi3c->CtrlMultipleXferCpltCallback(hi3c);
+#else
+            HAL_I3C_CtrlMultipleXferCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */
+          }
+          else
+          {
+            hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+            /* Call error treatment function */
+            I3C_ErrorTreatment(hi3c);
+          }
+        }
+        else
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_SIZE;
+
+          /* Call error treatment function */
+          I3C_ErrorTreatment(hi3c);
+        }
+      }
+      else
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NONE;
+
+        /* Then Initiate a Start condition */
+        LL_I3C_RequestTransfer(hi3c->Instance);
+      }
+    }
+  }
+  return HAL_OK;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Interrupt Sub-Routine which handles abort process in interrupt mode.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration information
+  *                            for the specified I3C.
+  * @param  itMasks    : [IN]  Flag Interrupt Masks flags to handle.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Abort_ISR(struct __I3C_HandleTypeDef *hi3c, uint32_t itMasks)
+{
+  /* Check that an Abort process is ongoing */
+  if (hi3c->State == HAL_I3C_STATE_ABORT)
+  {
+    /* I3C Rx FIFO not empty interrupt Check */
+    if (I3C_CHECK_FLAG(itMasks, HAL_I3C_FLAG_RXFNEF) != RESET)
+    {
+      if (LL_I3C_IsActiveFlag_DOVR(hi3c->Instance) == 1U)
+      {
+        /* Flush remaining Rx data */
+        LL_I3C_RequestRxFIFOFlush(hi3c->Instance);
+      }
+    }
+
+    /* I3C Abort frame complete event Check */
+    /* Evenif abort is called, the Frame completion can arrive if abort is requested at the end of the processus */
+    /* Evenif completion occurs, treat this end of processus as abort completion process */
+    if (I3C_CHECK_FLAG(itMasks, I3C_EVR_FCF) != RESET)
+    {
+      /* Clear frame complete flag */
+      LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+      /* Call error treatment function */
+      I3C_ErrorTreatment(hi3c);
+    }
+  }
+  return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  DMA I3C control transmit process complete callback.
+  * @param  hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                     for the specified DMA channel.
+  * @retval None
+  */
+static void I3C_DMAControlTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Get the address of the I3C handle : Derogation MISRAC2012-Rule-11.5 */
+  I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable control DMA Request */
+  LL_I3C_DisableDMAReq_Control(hi3c->Instance);
+}
+
+/**
+  * @brief  DMA I3C transmit data process complete callback.
+  * @param  hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                     for the specified DMA channel.
+  * @retval None
+  */
+static void I3C_DMADataTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Get the address of the I3C handle : Derogation MISRAC2012-Rule-11.5 */
+  I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable Tx DMA Request */
+  LL_I3C_DisableDMAReq_TX(hi3c->Instance);
+}
+
+/**
+  * @brief  DMA I3C receive data process complete callback.
+  * @param  hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                     for the specified DMA channel.
+  * @retval None
+  */
+static void I3C_DMADataReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Get the address of the I3C handle : Derogation MISRAC2012-Rule-11.5 */
+  I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Disable Rx DMA Request */
+  LL_I3C_DisableDMAReq_RX(hi3c->Instance);
+}
+
+/**
+  * @brief  DMA I3C communication error callback.
+  * @param  hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                     for the specified DMA channel.
+  * @retval None
+  */
+static void I3C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Just to solve MisraC error then to be removed */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  hi3c->ErrorCode |= HAL_I3C_ERROR_DMA;
+}
+
+/**
+  * @brief DMA I3C communication abort callback to be called at end of DMA Abort procedure.
+  * @param  hdma : [IN] Pointer to a DMA_HandleTypeDef structure that contains the configuration information
+  *                     for the specified DMA channel.
+  * @retval None
+  */
+static void I3C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I3C_HandleTypeDef *hi3c = (I3C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Reset Tx DMA AbortCpltCallback */
+  if (hi3c->hdmatx != NULL)
+  {
+    hi3c->hdmatx->XferAbortCallback = NULL;
+  }
+
+  /* Reset Rx DMA AbortCpltCallback */
+  if (hi3c->hdmarx != NULL)
+  {
+    hi3c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  /* Reset control DMA AbortCpltCallback */
+  if (hi3c->hdmacr != NULL)
+  {
+    hi3c->hdmacr->XferAbortCallback = NULL;
+  }
+
+  I3C_TreatErrorCallback(hi3c);
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  This function handles I3C Communication Timeout.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                            information for the specified I3C.
+  * @param  flag       : [IN]  Specifies the I3C flag to check.
+  * @param  flagstatus : [IN]  The new Flag status (SET or RESET).
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @param  tickstart  : [IN]  Tick start value
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_WaitOnFlagUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t flag, FlagStatus flagstatus,
+                                                    uint32_t timeout, uint32_t tickstart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  while ((__HAL_I3C_GET_FLAG(hi3c, flag) == flagstatus) && (status == HAL_OK))
+  {
+    /* Check for the Timeout */
+    if (timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+      {
+        if (__HAL_I3C_GET_FLAG(hi3c, flag) == flagstatus)
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_TIMEOUT;
+          status = HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Check if an error occurs during Flag waiting */
+    if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+    {
+      /* Clear error flag */
+      LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+      /* Update handle error code parameter */
+      I3C_GetErrorSources(hi3c);
+
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  This function handles I3C Dynamic Address Assignment timeout.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                            information for the specified I3C.
+  * @param  timeout    : [IN]  Timeout duration in millisecond.
+  * @param  tickstart  : [IN]  Tick start value
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_WaitOnDAAUntilTimeout(I3C_HandleTypeDef *hi3c, uint32_t timeout, uint32_t tickstart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t active_flags = READ_REG(hi3c->Instance->EVR);
+
+  while (((active_flags & (HAL_I3C_FLAG_FCF | HAL_I3C_FLAG_TXFNFF)) == 0U) && (status == HAL_OK))
+  {
+    /* Check for the Timeout */
+    if (timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+      {
+        if ((active_flags & (HAL_I3C_FLAG_FCF | HAL_I3C_FLAG_TXFNFF)) == 0U)
+        {
+          hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT;
+          status = HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Check if an error occurs during Flag waiting */
+    if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_ERRF) == SET)
+    {
+      /* Clear error flag */
+      LL_I3C_ClearFlag_ERR(hi3c->Instance);
+
+      /* Update handle error code parameter */
+      I3C_GetErrorSources(hi3c);
+
+      status = HAL_ERROR;
+    }
+
+    /* Read active flags from EVR register */
+    active_flags = READ_REG(hi3c->Instance->EVR);
+  }
+  return status;
+}
+
+/**
+  * @brief  I3C transmit by byte.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_TransmitByteTreatment(I3C_HandleTypeDef *hi3c)
+{
+  /* Check TX FIFO not full flag */
+  while ((__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET) && (hi3c->TxXferCount > 0U))
+  {
+    /* Write Tx buffer data to transmit register */
+    LL_I3C_TransmitData8(hi3c->Instance, *hi3c->pXferData->TxBuf.pBuffer);
+
+    /* Increment Buffer pointer */
+    hi3c->pXferData->TxBuf.pBuffer++;
+
+    /* Decrement remaining bytes counter */
+    hi3c->TxXferCount--;
+  }
+}
+
+/**
+  * @brief  I3C transmit by word.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_TransmitWordTreatment(I3C_HandleTypeDef *hi3c)
+{
+  /* Check TX FIFO not full flag */
+  while (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_TXFNFF) == SET)
+  {
+    /* Write Tx buffer data to transmit register */
+    LL_I3C_TransmitData32(hi3c->Instance, *((uint32_t *)hi3c->pXferData->TxBuf.pBuffer));
+
+    /* Increment Buffer pointer */
+    hi3c->pXferData->TxBuf.pBuffer += sizeof(uint32_t);
+
+    if (hi3c->TxXferCount < sizeof(uint32_t))
+    {
+      hi3c->TxXferCount = 0U;
+    }
+    else
+    {
+      /* Decrement remaining bytes counter */
+      hi3c->TxXferCount -= sizeof(uint32_t);
+    }
+  }
+}
+
+/**
+  * @brief  I3C receive by byte.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_ReceiveByteTreatment(I3C_HandleTypeDef *hi3c)
+{
+  /* Check RX FIFO not empty flag */
+  while (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_RXFNEF) == SET)
+  {
+    /* Store received bytes in the Rx buffer */
+    *hi3c->pXferData->RxBuf.pBuffer = LL_I3C_ReceiveData8(hi3c->Instance);
+
+    /* Increment Buffer pointer */
+    hi3c->pXferData->RxBuf.pBuffer++;
+
+    /* Decrement remaining bytes counter */
+    hi3c->RxXferCount--;
+  }
+}
+
+/**
+  * @brief  I3C receive by word.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_ReceiveWordTreatment(I3C_HandleTypeDef *hi3c)
+{
+  /* Check RX FIFO not empty flag */
+  while (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_RXFNEF) == SET)
+  {
+    /* Store received bytes in the Rx buffer */
+    *((uint32_t *)hi3c->pXferData->RxBuf.pBuffer) = LL_I3C_ReceiveData32(hi3c->Instance);
+
+    /* Increment Buffer pointer */
+    hi3c->pXferData->RxBuf.pBuffer += sizeof(uint32_t);
+
+    if (hi3c->RxXferCount > sizeof(uint32_t))
+    {
+      /* Decrement remaining bytes counter */
+      hi3c->RxXferCount -= sizeof(uint32_t);
+    }
+    else
+    {
+      /* Reset counter as last modulo word Rx data received */
+      hi3c->RxXferCount = 0U;
+    }
+  }
+}
+
+/**
+  * @brief  I3C Control data treatment.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_ControlDataTreatment(I3C_HandleTypeDef *hi3c)
+{
+  /* Check if Control FIFO requests data */
+  if (__HAL_I3C_GET_FLAG(hi3c, HAL_I3C_FLAG_CFNFF) == SET)
+  {
+    /* Decrement remaining control buffer data counter */
+    hi3c->ControlXferCount--;
+
+    /* Write Control buffer data to control register */
+    WRITE_REG(hi3c->Instance->CR, *hi3c->pXferData->CtrlBuf.pBuffer);
+
+    /* Increment Buffer pointer */
+    hi3c->pXferData->CtrlBuf.pBuffer++;
+  }
+}
+
+/**
+  * @brief  I3C state update.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_StateUpdate(I3C_HandleTypeDef *hi3c)
+{
+  /* Check on previous state */
+  if (hi3c->PreviousState == HAL_I3C_STATE_LISTEN)
+  {
+    /* Set state to listen */
+    hi3c->State = HAL_I3C_STATE_LISTEN;
+
+    /* Check the I3C mode */
+    if (hi3c->Mode == HAL_I3C_MODE_TARGET)
+    {
+      /* Store the target event treatment function */
+      hi3c->XferISR = I3C_Tgt_Event_ISR;
+    }
+    else
+    {
+      /* Store the controller event treatment function */
+      hi3c->XferISR = I3C_Ctrl_Event_ISR;
+    }
+  }
+  else
+  {
+    /* Set state to ready */
+    hi3c->State = HAL_I3C_STATE_READY;
+
+    /* Reset XferISR */
+    hi3c->XferISR = NULL;
+  }
+}
+
+/**
+  * @brief  I3C get error source.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_GetErrorSources(I3C_HandleTypeDef *hi3c)
+{
+  /* Check on the I3C mode */
+  switch (hi3c->Mode)
+  {
+    case HAL_I3C_MODE_CONTROLLER:
+    {
+      /* I3C data error during controller-role hand-off procedure */
+      if (LL_I3C_IsActiveFlag_DERR(hi3c->Instance) == 1U)
+      {
+        hi3c->ErrorCode |= HAL_I3C_ERROR_DATA_HAND_OFF;
+      }
+
+      /* I3C data not acknowledged error */
+      if (LL_I3C_IsActiveFlag_DNACK(hi3c->Instance) == 1U)
+      {
+        hi3c->ErrorCode |= HAL_I3C_ERROR_DATA_NACK;
+      }
+
+      /* I3C address not acknowledged error */
+      if (LL_I3C_IsActiveFlag_ANACK(hi3c->Instance) == 1U)
+      {
+        hi3c->ErrorCode |= HAL_I3C_ERROR_ADDRESS_NACK;
+      }
+
+      /* I3C Status FIFO Over-Run or Control FIFO Under-Run error */
+      if (LL_I3C_IsActiveFlag_COVR(hi3c->Instance) == 1U)
+      {
+        hi3c->ErrorCode |= HAL_I3C_ERROR_COVR;
+      }
+
+      break;
+    }
+
+    case HAL_I3C_MODE_TARGET:
+    {
+      /* I3C SCL stall error */
+      if (LL_I3C_IsActiveFlag_STALL(hi3c->Instance) == 1U)
+      {
+        hi3c->ErrorCode |= HAL_I3C_ERROR_STALL;
+      }
+
+      break;
+    }
+
+    default:
+    {
+      break;
+    }
+  }
+
+  /* I3C Rx FIFO Over-Run or Tx FIFO Under-Run error */
+  if (LL_I3C_IsActiveFlag_DOVR(hi3c->Instance) == 1U)
+  {
+    hi3c->ErrorCode |= HAL_I3C_ERROR_DOVR;
+  }
+
+  /* I3C Protocol error */
+  if (LL_I3C_IsActiveFlag_PERR(hi3c->Instance) == 1U)
+  {
+    hi3c->ErrorCode |= (I3C_SER_PERR | LL_I3C_GetMessageErrorCode(hi3c->Instance));
+  }
+}
+
+/**
+  * @brief  I3C transfer prior preparation.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                            information for the specified I3C.
+  * @param  counter    : [IN]  Number of devices or commands to treat.
+  * @param  option     : [IN]  Parameter indicates the transfer option.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Xfer_PriorPreparation(I3C_HandleTypeDef *hi3c, uint8_t counter, uint32_t option)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  uint32_t current_tx_index = 0U;
+  uint32_t global_tx_size   = 0U;
+  uint32_t global_rx_size   = 0U;
+  uint32_t nb_tx_frame      = 0U;
+  uint32_t direction;
+
+  for (uint32_t descr_index = 0U; descr_index < counter; descr_index++)
+  {
+    /* Direct CCC command */
+    if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT)
+    {
+      /* Update direction of frame */
+      direction = hi3c->pCCCDesc[descr_index].Direction;
+
+      /* Direction read with Define byte */
+      if (((option & I3C_DEFINE_BYTE_MASK) != 0U) && (direction == HAL_I3C_DIRECTION_READ))
+      {
+        nb_tx_frame += 1U;
+
+        global_tx_size += 1U;
+
+        global_rx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size - 1U;
+
+        /* Check on the global size and on the Tx buffer pointer */
+        if ((global_tx_size > hi3c->pXferData->TxBuf.Size)    || \
+            (current_tx_index > hi3c->pXferData->TxBuf.Size)  || \
+            (hi3c->pXferData->TxBuf.pBuffer == NULL))
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Fill global Tx buffer with data and update the current index of the Tx buffer */
+          current_tx_index = I3C_FillTxBuffer_CCC(hi3c, descr_index, 1U, current_tx_index);
+        }
+      }
+      else if (direction == HAL_I3C_DIRECTION_WRITE)
+      {
+        nb_tx_frame += 1U;
+
+        global_tx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size;
+
+        /* Check on the global size and on the Tx buffer pointer */
+        if ((global_tx_size > hi3c->pXferData->TxBuf.Size)    || \
+            (current_tx_index > hi3c->pXferData->TxBuf.Size)  || \
+            (hi3c->pXferData->TxBuf.pBuffer == NULL))
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Fill global Tx buffer with data and update the current index of the Tx buffer */
+          current_tx_index = I3C_FillTxBuffer_CCC(hi3c,
+                                                  descr_index,
+                                                  hi3c->pCCCDesc[descr_index].CCCBuf.Size,
+                                                  current_tx_index);
+        }
+      }
+      /* Direction read without Define byte */
+      else
+      {
+        global_rx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size;
+      }
+    }
+    /* Broadcast CCC command */
+    else if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC)
+    {
+      /* Update direction of frame */
+      direction = hi3c->pCCCDesc[descr_index].Direction;
+
+      if (direction == HAL_I3C_DIRECTION_WRITE)
+      {
+        nb_tx_frame += 1U;
+
+        global_tx_size += hi3c->pCCCDesc[descr_index].CCCBuf.Size;
+
+        /* Check on the global size and on the Tx buffer pointer */
+        if ((global_tx_size > hi3c->pXferData->TxBuf.Size)    || \
+            (current_tx_index > hi3c->pXferData->TxBuf.Size)  || \
+            (hi3c->pXferData->TxBuf.pBuffer == NULL))
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Fill global Tx buffer with data and update the current index of the Tx buffer */
+          current_tx_index = I3C_FillTxBuffer_CCC(hi3c,
+                                                  descr_index,
+                                                  hi3c->pCCCDesc[descr_index].CCCBuf.Size,
+                                                  current_tx_index);
+        }
+      }
+      else
+      {
+        status = HAL_ERROR;
+      }
+    }
+    /* Private */
+    else
+    {
+      /* Update direction of frame */
+      direction = hi3c->pPrivateDesc[descr_index].Direction;
+
+      if (direction == HAL_I3C_DIRECTION_WRITE)
+      {
+        nb_tx_frame += 1U;
+
+        global_tx_size += hi3c->pPrivateDesc[descr_index].TxBuf.Size;
+
+        /* Check on the global size and on the Tx buffer pointer */
+        if ((global_tx_size > hi3c->pXferData->TxBuf.Size)    || \
+            (current_tx_index > hi3c->pXferData->TxBuf.Size)  || \
+            (hi3c->pXferData->TxBuf.pBuffer == NULL))
+        {
+          hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Fill global Tx buffer with data and update the current index of the Tx buffer */
+          current_tx_index = I3C_FillTxBuffer_Private(hi3c,
+                                                      descr_index,
+                                                      hi3c->pPrivateDesc[descr_index].TxBuf.Size,
+                                                      current_tx_index);
+        }
+      }
+      else
+      {
+        global_rx_size += hi3c->pPrivateDesc[descr_index].RxBuf.Size;
+      }
+    }
+
+    /* Check if there is an error in the Tx Buffer*/
+    if (status == HAL_ERROR)
+    {
+      break;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check on the Tx threshold and the number of Tx frame */
+    if (LL_I3C_GetTxFIFOThreshold(hi3c->Instance) == LL_I3C_TXFIFO_THRESHOLD_4_4)
+    {
+      /* LL_I3C_TXFIFO_THRESHOLD_4_4 is not allowed when the transfer descriptor contains
+         multiple transmission frames */
+      if (nb_tx_frame > 1U)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check on the size Rx buffer */
+    if (global_rx_size > hi3c->pXferData->RxBuf.Size)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      hi3c->RxXferCount = global_rx_size;
+    }
+
+    /* Set handle transfer parameters */
+    hi3c->TxXferCount = global_tx_size;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  I3C fill Tx Buffer with data from CCC Descriptor.
+  * @param  hi3c           : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                information for the specified I3C.
+  * @param  indexDesc      : [IN]  Index of descriptor.
+  * @param  txSize         : [IN]  Size of Tx data.
+  * @param  txCurrentIndex : [IN]  Current Index of TxBuffer.
+  * @retval index_tx       : [OUT] New current Index of TxBuffer.
+  */
+static uint32_t I3C_FillTxBuffer_CCC(I3C_HandleTypeDef *hi3c,
+                                     uint32_t           indexDesc,
+                                     uint32_t           txSize,
+                                     uint32_t           txCurrentIndex)
+{
+  uint32_t index_tx = txCurrentIndex;
+
+  for (uint32_t index = 0U; index < txSize; index++)
+  {
+    hi3c->pXferData->TxBuf.pBuffer[index_tx] = hi3c->pCCCDesc[indexDesc].CCCBuf.pBuffer[index];
+
+    index_tx++;
+  }
+
+  return index_tx;
+}
+
+/**
+  * @brief  I3C fill Tx Buffer with data from Private Descriptor.
+  * @param  hi3c           : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                information for the specified I3C.
+  * @param  indexDesc      : [IN]  Index of descriptor.
+  * @param  txSize         : [IN]  Size of Tx data.
+  * @param  txCurrentIndex : [IN]  Current Index of TxBuffer.
+  * @retval index_tx       : [OUT] New current Index of TxBuffer.
+  */
+static uint32_t I3C_FillTxBuffer_Private(I3C_HandleTypeDef *hi3c,
+                                         uint32_t           indexDesc,
+                                         uint32_t           txSize,
+                                         uint32_t           txCurrentIndex)
+{
+  uint32_t index_tx = txCurrentIndex;
+
+  for (uint32_t index = 0U; index < txSize; index++)
+  {
+    hi3c->pXferData->TxBuf.pBuffer[index_tx] = hi3c->pPrivateDesc[indexDesc].TxBuf.pBuffer[index];
+
+    index_tx++;
+  }
+
+  return index_tx;
+}
+
+/**
+  * @brief  I3C Control buffer prior preparation.
+  * @param  hi3c       : [IN]  Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                            information for the specified I3C.
+  * @param  counter    : [IN]  Number of devices or commands to treat.
+  * @param  option     : [IN]  Parameter indicates the transfer option.
+  * @retval HAL Status :       Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_ControlBuffer_PriorPreparation(I3C_HandleTypeDef *hi3c,
+                                                            uint8_t            counter,
+                                                            uint32_t           option)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t nb_define_bytes;
+  uint32_t stop_condition;
+  uint32_t nb_data_bytes;
+  uint32_t index;
+
+  /* Check on the control buffer pointer */
+  if (hi3c->pXferData->CtrlBuf.pBuffer == NULL)
+  {
+    hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Extract from option required information */
+    nb_define_bytes = (option & I3C_DEFINE_BYTE_MASK);
+    stop_condition  = (option & I3C_RESTART_STOP_MASK);
+
+    /* Check on the deactivation of the arbitration */
+    if ((option & I3C_ARBITRATION_HEADER_MASK) == I3C_ARBITRATION_HEADER_MASK)
+    {
+      /* Disable arbitration header */
+      LL_I3C_DisableArbitrationHeader(hi3c->Instance);
+    }
+    else
+    {
+      /* Enable arbitration header */
+      LL_I3C_EnableArbitrationHeader(hi3c->Instance);
+    }
+
+    /* Check on the operation type */
+    if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_CCC)
+    {
+      /*------------------------------------------ Broadcast CCC -----------------------------------------------------*/
+      /* Check on the control buffer size */
+      if (hi3c->pXferData->CtrlBuf.Size < (uint32_t)counter)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Set remaining control buffer data counter */
+        hi3c->ControlXferCount = (uint32_t)counter;
+
+        /* For loop on the number of commands */
+        for (index = 0U; index < ((uint32_t)counter - 1U); index++)
+        {
+          /* Update control buffer value */
+          hi3c->pXferData->CtrlBuf.pBuffer[index] = ((uint32_t)hi3c->pCCCDesc[index].CCCBuf.Size              |
+                                                     ((uint32_t)hi3c->pCCCDesc[index].CCC  << I3C_CR_CCC_Pos) |
+                                                     LL_I3C_CONTROLLER_MTYPE_CCC | stop_condition);
+        }
+
+        /* At the last device we should generate a stop condition */
+        hi3c->pXferData->CtrlBuf.pBuffer[index] = ((uint32_t)hi3c->pCCCDesc[index].CCCBuf.Size              |
+                                                   ((uint32_t)hi3c->pCCCDesc[index].CCC  << I3C_CR_CCC_Pos) |
+                                                   LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_GENERATE_STOP);
+      }
+    }
+    else if ((option & I3C_OPERATION_TYPE_MASK) == LL_I3C_CONTROLLER_MTYPE_DIRECT)
+    {
+      /*------------------------------------------ Direct CCC --------------------------------------------------------*/
+      /* Check on the control buffer size */
+      if (hi3c->pXferData->CtrlBuf.Size < ((uint32_t)counter * 2U))
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Set remaining control buffer data counter */
+        hi3c->ControlXferCount = ((uint32_t)counter * 2U);
+
+        /* For loop on the number of (devices or commands) * 2 */
+        for (index = 0U; index < (((uint32_t)counter * 2U) - 2U); index += 2U)
+        {
+          /* Step 1 : update control buffer value for the CCC command */
+          hi3c->pXferData->CtrlBuf.pBuffer[index] = (nb_define_bytes                                               |
+                                                     ((uint32_t)hi3c->pCCCDesc[index / 2U].CCC  << I3C_CR_CCC_Pos) |
+                                                     LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_GENERATE_RESTART);
+
+          /* Step 2 : update control buffer value for target address */
+          hi3c->pXferData->CtrlBuf.pBuffer[index + 1U] =
+            (((uint32_t)hi3c->pCCCDesc[index / 2U].CCCBuf.Size - nb_define_bytes) |
+             hi3c->pCCCDesc[index / 2U].Direction                                            |
+             ((uint32_t)hi3c->pCCCDesc[index / 2U].TargetAddr << I3C_CR_ADD_Pos)  |
+             LL_I3C_CONTROLLER_MTYPE_DIRECT | stop_condition);
+        }
+
+        /* Update control buffer value for the last CCC command */
+        hi3c->pXferData->CtrlBuf.pBuffer[index] = (nb_define_bytes                                               |
+                                                   ((uint32_t)hi3c->pCCCDesc[index / 2U].CCC  << I3C_CR_CCC_Pos) |
+                                                   LL_I3C_CONTROLLER_MTYPE_CCC | LL_I3C_GENERATE_RESTART);
+
+        /* At the last device we should generate a stop condition */
+        hi3c->pXferData->CtrlBuf.pBuffer[index + 1U] =
+          (((uint32_t)hi3c->pCCCDesc[index / 2U].CCCBuf.Size - nb_define_bytes) |
+           hi3c->pCCCDesc[index / 2U].Direction                                            |
+           ((uint32_t)hi3c->pCCCDesc[index / 2U].TargetAddr << I3C_CR_ADD_Pos)  |
+           LL_I3C_CONTROLLER_MTYPE_DIRECT | LL_I3C_GENERATE_STOP);
+      }
+    }
+    else
+    {
+      /*------------------------------------------ Private I3C/I2C ---------------------------------------------------*/
+      /* Check on the control buffer size */
+      if (hi3c->pXferData->CtrlBuf.Size < (uint32_t)counter)
+      {
+        hi3c->ErrorCode = HAL_I3C_ERROR_INVALID_PARAM;
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Set remaining control buffer data counter */
+        hi3c->ControlXferCount = (uint32_t)counter;
+
+        /* For loop on the number of devices */
+        for (index = 0U; index < ((uint32_t)counter - 1U); index++)
+        {
+          /* Check on transfer direction */
+          if (hi3c->pPrivateDesc[index].Direction == HAL_I3C_DIRECTION_READ)
+          {
+            nb_data_bytes = hi3c->pPrivateDesc[index].RxBuf.Size;
+          }
+          else
+          {
+            nb_data_bytes = hi3c->pPrivateDesc[index].TxBuf.Size;
+          }
+
+          /* Update control buffer value */
+          hi3c->pXferData->CtrlBuf.pBuffer[index] =
+            (nb_data_bytes | hi3c->pPrivateDesc[index].Direction                |
+             ((uint32_t)hi3c->pPrivateDesc[index].TargetAddr << I3C_CR_ADD_Pos) |
+             (option & I3C_OPERATION_TYPE_MASK) | stop_condition);
+        }
+
+        /* Check on transfer direction */
+        if (hi3c->pPrivateDesc[index].Direction == HAL_I3C_DIRECTION_READ)
+        {
+          nb_data_bytes = hi3c->pPrivateDesc[index].RxBuf.Size;
+        }
+        else
+        {
+          nb_data_bytes = hi3c->pPrivateDesc[index].TxBuf.Size;
+        }
+
+        /* At the last device we should generate a stop condition */
+        hi3c->pXferData->CtrlBuf.pBuffer[index] =
+          (nb_data_bytes | hi3c->pPrivateDesc[index].Direction                |
+           ((uint32_t)hi3c->pPrivateDesc[index].TargetAddr << I3C_CR_ADD_Pos) |
+           (option & I3C_OPERATION_TYPE_MASK) | LL_I3C_GENERATE_STOP);
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Check if target device is ready for communication.
+  * @param  hi3c    : Pointer to a I3C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I3C.
+  * @param  pDevice : [IN] Structure to define the device address and the device type.
+  * @param  trials  : [IN] Number of trials
+  * @param  timeout : [IN] Timeout duration
+  * @retval HAL Status :   Value from HAL_StatusTypeDef enumeration.
+  */
+static HAL_StatusTypeDef I3C_Ctrl_IsDevice_Ready(I3C_HandleTypeDef *hi3c,
+                                                 const I3C_DeviceTypeDef *pDevice,
+                                                 uint32_t           trials,
+                                                 uint32_t           timeout)
+{
+  __IO uint32_t I3C_Trials = 0UL;
+  __IO uint32_t exit_condition;
+  uint32_t CR_tmp;
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_I3C_StateTypeDef handle_state;
+  uint32_t arbitration_previous_state;
+
+  /* Get I3C handle state */
+  handle_state = hi3c->State;
+
+  /* check on the Mode */
+  if (hi3c->Mode != HAL_I3C_MODE_CONTROLLER)
+  {
+    hi3c->ErrorCode = HAL_I3C_ERROR_NOT_ALLOWED;
+    status = HAL_ERROR;
+  }
+  /* check on the State */
+  else if ((handle_state != HAL_I3C_STATE_READY) && (handle_state != HAL_I3C_STATE_LISTEN))
+  {
+    status = HAL_BUSY;
+  }
+  else
+  {
+    /* Set handle transfer parameters */
+    hi3c->ErrorCode     = HAL_I3C_ERROR_NONE;
+    hi3c->State         = HAL_I3C_STATE_BUSY;
+
+    /* Before modify the arbitration, get the current arbitration state */
+    arbitration_previous_state = LL_I3C_IsEnabledArbitrationHeader(hi3c->Instance);
+
+    /* Disable arbitration header */
+    LL_I3C_DisableArbitrationHeader(hi3c->Instance);
+
+    CR_tmp = (HAL_I3C_DIRECTION_WRITE                                   |
+              ((uint32_t)pDevice->Address << I3C_CR_ADD_Pos)      |
+              pDevice->MessageType | LL_I3C_GENERATE_STOP);
+
+    do
+    {
+      /* Initiate a start condition by writing in the CR register */
+      WRITE_REG(hi3c->Instance->CR, CR_tmp);
+
+      /* Calculate exit_condition value based on Frame complete and error flags */
+      exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+
+      tickstart = HAL_GetTick();
+
+      while (exit_condition == 0U)
+      {
+        if (timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
+          {
+            /* Update I3C error code */
+            hi3c->ErrorCode |= HAL_I3C_ERROR_TIMEOUT;
+            status = HAL_TIMEOUT;
+
+            break;
+          }
+        }
+        /* Calculate exit_condition value based on Frame complete and error flags */
+        exit_condition = (READ_REG(hi3c->Instance->EVR) & (I3C_EVR_FCF | I3C_EVR_ERRF));
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Check if the FCF flag has been set */
+        if (__HAL_I3C_GET_FLAG(hi3c, I3C_EVR_FCF) == SET)
+        {
+          /* Clear frame complete flag */
+          LL_I3C_ClearFlag_FC(hi3c->Instance);
+
+          /* Device is ready */
+          break;
+        }
+        else
+        {
+          /* Clear ERR flag */
+          LL_I3C_ClearFlag_ERR(hi3c->Instance);
+        }
+      }
+
+      /* Increment Trials */
+      I3C_Trials++;
+
+    } while ((I3C_Trials < trials) && (status == HAL_OK));
+
+    /* Device is not ready */
+    if (trials == I3C_Trials)
+    {
+      hi3c->ErrorCode = HAL_I3C_ERROR_ADDRESS_NACK;
+      status = HAL_ERROR;
+    }
+
+    /* update state to Previous state */
+    I3C_StateUpdate(hi3c);
+
+    /* Check if previous arbitration state is enabled */
+    if (arbitration_previous_state == 1U)
+    {
+      LL_I3C_EnableArbitrationHeader(hi3c->Instance);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi3c             : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                 information for the specified I3C.
+  * @param  InterruptRequest : [IN] Value of the interrupt request
+  * @retval None
+  */
+static void I3C_Enable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  /* Check if requested interrupts are related to listening mode */
+  if ((InterruptRequest & I3C_XFER_LISTEN_IT) != 0U)
+  {
+    tmpisr |= ((InterruptRequest & (~I3C_XFER_LISTEN_IT)) | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target transmit in IT mode */
+  if ((InterruptRequest & I3C_XFER_TARGET_TX_IT) != 0U)
+  {
+    /* Enable frame complete, transmit FIFO not full and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target receive in IT mode */
+  if ((InterruptRequest & I3C_XFER_TARGET_RX_IT) != 0U)
+  {
+    /* Enable frame complete, receive FIFO not empty and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE) ;
+  }
+
+  /* Check if requested interrupts are related to transmit/receive in DMA mode */
+  if ((InterruptRequest & I3C_XFER_DMA) != 0U)
+  {
+    /* Enable frame complete and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target hot join */
+  if ((InterruptRequest & I3C_XFER_TARGET_HOTJOIN) != 0U)
+  {
+    /* Enable dynamic address update and error interrupts */
+    tmpisr |= (HAL_I3C_IT_DAUPDIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target control role */
+  if ((InterruptRequest & I3C_XFER_TARGET_CTRLROLE) != 0U)
+  {
+    /* Enable control role update and error interrupts */
+    tmpisr |= (HAL_I3C_IT_CRUPDIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target in band interrupt */
+  if ((InterruptRequest & I3C_XFER_TARGET_IBI) != 0U)
+  {
+    /* Enable IBI end and error interrupts */
+    tmpisr |= (HAL_I3C_IT_IBIENDIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to controller transmit in IT mode */
+  if ((InterruptRequest & I3C_XFER_CONTROLLER_TX_IT) != 0U)
+  {
+    /* Enable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to controller receive in IT mode */
+  if ((InterruptRequest & I3C_XFER_CONTROLLER_RX_IT) != 0U)
+  {
+    /* Enable frame complete, control FIFO not full, receive FIFO not empty and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to controller transmit read or a broadcast CCC in IT mode */
+  if ((InterruptRequest & I3C_XFER_CONTROLLER_RX_CCC_IT) != 0U)
+  {
+    /* Enable frame complete, transmit FIFO not full, control FIFO not full,
+       receive FIFO not empty and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to controller transmit broadcast ENTDAA CCC in IT mode */
+  if ((InterruptRequest & I3C_XFER_CONTROLLER_DAA_IT) != 0U)
+  {
+    /* Enable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Enable requested interrupts */
+  __HAL_I3C_ENABLE_IT(hi3c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi3c             : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                                 information for the specified I3C.
+  * @param  InterruptRequest : [IN] Value of the interrupt request
+  * @retval None
+  */
+static void I3C_Disable_IRQ(I3C_HandleTypeDef *hi3c, uint32_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  /* Check if requested interrupts are related to listening mode */
+  if ((InterruptRequest & I3C_XFER_LISTEN_IT) != 0U)
+  {
+    tmpisr |= ((InterruptRequest & (~I3C_XFER_LISTEN_IT)) | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target transmit mode */
+  if ((InterruptRequest & I3C_XFER_TARGET_TX_IT) != 0U)
+  {
+    /* Disable frame complete, transmit FIFO not full and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target receive mode */
+  if ((InterruptRequest & I3C_XFER_TARGET_RX_IT) != 0U)
+  {
+    /* Disable frame complete, receive FIFO not empty and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to transmit/receive in DMA mode */
+  if ((InterruptRequest & I3C_XFER_DMA) != 0U)
+  {
+    /* Disable frame complete and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target hot join */
+  if ((InterruptRequest & I3C_XFER_TARGET_HOTJOIN) != 0U)
+  {
+    /* Disable dynamic address update and error interrupts */
+    tmpisr |= (HAL_I3C_IT_DAUPDIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target control role */
+  if ((InterruptRequest & I3C_XFER_TARGET_CTRLROLE) != 0U)
+  {
+    /* Disable control role update and error interrupts */
+    tmpisr |= (HAL_I3C_IT_CRUPDIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to target in band interrupt */
+  if ((InterruptRequest & I3C_XFER_TARGET_IBI) != 0U)
+  {
+    /* Disable IBI end and error interrupts */
+    tmpisr |= (HAL_I3C_IT_IBIENDIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to controller transmit in IT mode */
+  if ((InterruptRequest & I3C_XFER_CONTROLLER_TX_IT) != 0U)
+  {
+    /* Disable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to controller transmit read or a broadcast CCC in IT mode */
+  if ((InterruptRequest & I3C_XFER_CONTROLLER_RX_CCC_IT) != 0U)
+  {
+    /* Disable frame complete, transmit FIFO not full, control FIFO not full,
+       receive FIFO not empty and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_RXFNEIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Check if requested interrupts are related to controller transmit broadcast ENTDAA CCC in IT mode */
+  if ((InterruptRequest & I3C_XFER_CONTROLLER_DAA_IT) != 0U)
+  {
+    /* Disable frame complete, control FIFO not full, transmit FIFO not full and error interrupts */
+    tmpisr |= (HAL_I3C_IT_FCIE | HAL_I3C_IT_CFNFIE | HAL_I3C_IT_TXFNFIE | HAL_I3C_IT_ERRIE);
+  }
+
+  /* Disable requested interrupts */
+  __HAL_I3C_DISABLE_IT(hi3c, tmpisr);
+}
+
+/**
+  * @brief  I3C error treatment.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_ErrorTreatment(I3C_HandleTypeDef *hi3c)
+{
+  HAL_I3C_StateTypeDef tmpstate = hi3c->State;
+  uint32_t dmaabortongoing = 0U;
+
+  /* Check on the state */
+  if (tmpstate == HAL_I3C_STATE_BUSY)
+  {
+    /* Update handle state parameter */
+    I3C_StateUpdate(hi3c);
+
+    /* Disable all interrupts related to busy state */
+    I3C_Disable_IRQ(hi3c, (I3C_XFER_TARGET_IBI | I3C_XFER_TARGET_HOTJOIN | I3C_XFER_TARGET_CTRLROLE));
+  }
+  else
+  {
+    /* Disable all interrupts related to busy Tx and Rx state */
+    I3C_Disable_IRQ(hi3c, I3C_XFER_CONTROLLER_RX_CCC_IT);
+
+    /* Reset Tx counter */
+    hi3c->TxXferCount = 0U;
+
+    /* Reset Rx counter */
+    hi3c->RxXferCount = 0U;
+
+    /* Reset Control counter */
+    hi3c->ControlXferCount = 0U;
+
+    /* Reset Tx function pointer */
+    hi3c->ptrTxFunc = NULL;
+
+    /* Reset Rx function pointer */
+    hi3c->ptrRxFunc = NULL;
+
+    /* Reset Context pointer */
+    hi3c->pXferData = NULL;
+    hi3c->pCCCDesc = NULL;
+    hi3c->pPrivateDesc = NULL;
+
+    /* Flush all FIFOs */
+    /* Flush the content of Tx Fifo */
+    LL_I3C_RequestTxFIFOFlush(hi3c->Instance);
+
+    /* Flush the content of Rx Fifo */
+    LL_I3C_RequestRxFIFOFlush(hi3c->Instance);
+
+    /* Check on the I3C mode: Control and status FIFOs available only with controller mode */
+    if (hi3c->Mode == HAL_I3C_MODE_CONTROLLER)
+    {
+      /* Flush the content of Control Fifo */
+      LL_I3C_RequestControlFIFOFlush(hi3c->Instance);
+
+      /* Flush the content of Status Fifo */
+      LL_I3C_RequestStatusFIFOFlush(hi3c->Instance);
+    }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+    /* Abort control DMA transfer if any */
+    if (hi3c->hdmacr != NULL)
+    {
+      /* Disable control DMA Request */
+      LL_I3C_DisableDMAReq_Control(hi3c->Instance);
+
+      /* Check DMA state */
+      if (HAL_DMA_GetState(hi3c->hdmacr) != HAL_DMA_STATE_READY)
+      {
+        /* Set the I3C DMA Abort callback : will lead to call HAL_I3C_AbortCpltCallback()
+           at end of DMA abort procedure */
+
+        /* DMA abort on going */
+        dmaabortongoing = 1U;
+
+        /* Abort control DMA */
+        if (HAL_DMA_Abort_IT(hi3c->hdmacr) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hi3c->hdmacr->XferAbortCallback(hi3c->hdmacr);
+        }
+      }
+    }
+
+    /* Abort RX DMA transfer if any */
+    if (hi3c->hdmarx != NULL)
+    {
+      /* Disable Rx DMA Request */
+      LL_I3C_DisableDMAReq_RX(hi3c->Instance);
+
+      /* Check DMA state */
+      if (HAL_DMA_GetState(hi3c->hdmarx) != HAL_DMA_STATE_READY)
+      {
+        /* Set the I3C DMA Abort callback : will lead to call HAL_I3C_AbortCpltCallback()
+           at end of DMA abort procedure */
+        hi3c->hdmarx->XferAbortCallback = I3C_DMAAbort;
+
+        /* DMA abort on going */
+        dmaabortongoing = 1U;
+
+        /* Abort DMA RX */
+        if (HAL_DMA_Abort_IT(hi3c->hdmarx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hi3c->hdmarx->XferAbortCallback(hi3c->hdmarx);
+        }
+      }
+    }
+
+    /* Abort TX DMA transfer if any */
+    if (hi3c->hdmatx != NULL)
+    {
+      /* Disable Tx DMA Request */
+      LL_I3C_DisableDMAReq_TX(hi3c->Instance);
+
+      /* Check DMA state */
+      if (HAL_DMA_GetState(hi3c->hdmatx) != HAL_DMA_STATE_READY)
+      {
+        /* Set the I3C DMA Abort callback : will lead to call HAL_I3C_AbortCpltCallback()
+           at end of DMA abort procedure */
+        hi3c->hdmatx->XferAbortCallback = I3C_DMAAbort;
+
+        /* DMA abort on going */
+        dmaabortongoing = 1U;
+
+        /* Abort DMA TX */
+        if (HAL_DMA_Abort_IT(hi3c->hdmatx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hi3c->hdmatx->XferAbortCallback(hi3c->hdmatx);
+        }
+      }
+    }
+#endif /* HAL_DMA_MODULE_ENABLED */
+  }
+
+  /* Call Error callback if there is no DMA abort on going */
+  if (dmaabortongoing == 0U)
+  {
+    I3C_TreatErrorCallback(hi3c);
+  }
+}
+
+/**
+  * @brief  I3C Error callback treatment.
+  * @param  hi3c : [IN] Pointer to an I3C_HandleTypeDef structure that contains the configuration
+  *                     information for the specified I3C.
+  * @retval None
+  */
+static void I3C_TreatErrorCallback(I3C_HandleTypeDef *hi3c)
+{
+  if (hi3c->State == HAL_I3C_STATE_ABORT)
+  {
+    /* Update handle state parameter */
+    I3C_StateUpdate(hi3c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1)
+    hi3c->AbortCpltCallback(hi3c);
+#else
+    HAL_I3C_AbortCpltCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Update handle state parameter */
+    I3C_StateUpdate(hi3c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I3C_REGISTER_CALLBACKS == 1)
+    hi3c->ErrorCallback(hi3c);
+#else
+    HAL_I3C_ErrorCallback(hi3c);
+#endif /* USE_HAL_I3C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I3C_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_icache.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_icache.c
new file mode 100644
index 000000000..29bef31fd
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_icache.c
@@ -0,0 +1,512 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_icache.c
+  * @author  MCD Application Team
+  * @brief   ICACHE HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Instruction Cache (ICACHE).
+  *           + Initialization and Configuration
+  *           + Invalidate functions
+  *           + Monitoring management
+  *           + Memory address remap management
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### ICACHE main features #####
+  ==============================================================================
+  [..]
+    The Texture Cache (ICACHE) is introduced on AXI read-only texture port of
+    the GPU2D to improve performance when reading texture data from internal and
+    external memories.
+
+  ===============================================================================
+                        ##### How to use this driver #####
+  ===============================================================================
+  [..]
+     The ICACHE HAL driver can be used as follows:
+
+    (#) Optionally configure the Instruction Cache mode with
+        HAL_ICACHE_ConfigAssociativityMode() if the default configuration
+        does not suit the application requirements.
+
+    (#) Enable and disable the Instruction Cache with respectively
+        HAL_ICACHE_Enable() and HAL_ICACHE_Disable().
+        Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
+        To ensure a deterministic cache behavior after power on, system reset or after
+        a call to @ref HAL_ICACHE_Disable(), the application must call
+        @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset
+        or cache disable, an automatic cache invalidation procedure is launched and the
+        cache is bypassed until the operation completes.
+
+    (#) Initiate the cache maintenance invalidation procedure with either
+        HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT()
+        (interrupt mode). When interrupt mode is used, the callback function
+        HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
+        procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete()
+        may be called to wait for the end of the invalidate procedure automatically
+        initiated when disabling the Instruction Cache with HAL_ICACHE_Disable().
+        The cache operation is bypassed during the invalidation procedure.
+
+    (#) Use the performance monitoring counters for Hit and Miss with the following
+        functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(),
+        HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and
+        HAL_ICACHE_Monitor_GetMissValue()
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ICACHE ICACHE
+  * @brief HAL ICACHE module driver
+  * @{
+  */
+#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants
+  * @{
+  */
+#define ICACHE_INVALIDATE_TIMEOUT_VALUE        1U   /* 1ms */
+#define ICACHE_DISABLE_TIMEOUT_VALUE           1U   /* 1ms */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ICACHE_Private_Macros ICACHE Private Macros
+  * @{
+  */
+
+#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \
+                                                ((__MODE__) == ICACHE_4WAYS))
+
+#define IS_ICACHE_MONITOR_TYPE(__TYPE__)    (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \
+                                             ((__TYPE__) == ICACHE_MONITOR_HIT)      || \
+                                             ((__TYPE__) == ICACHE_MONITOR_MISS))
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions
+  * @{
+  */
+
+/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions
+  * @brief    Initialization and control functions
+  *
+  @verbatim
+  ==============================================================================
+            ##### Initialization and control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize and control the
+    Instruction Cache (mode, invalidate procedure, performance counters).
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the Instruction Cache cache associativity mode selection.
+  * @param  AssociativityMode  Associativity mode selection
+  *         This parameter can be one of the following values:
+  *            @arg ICACHE_1WAY   1-way cache (direct mapped cache)
+  *            @arg ICACHE_4WAYS  4-ways set associative cache (default)
+  * @retval HAL status (HAL_OK/HAL_ERROR)
+  */
+HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode));
+
+  /* Check cache is not enabled */
+  if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the Instruction Cache.
+  * @retval HAL status (HAL_OK)
+  */
+HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
+{
+  /* Reset interrupt enable value */
+  WRITE_REG(ICACHE->IER, 0U);
+
+  /* Clear any pending flags */
+  WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
+
+  /* Disable cache then set default associative mode value */
+  CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
+  WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
+
+  /* Stop monitor and reset monitor values */
+  CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS);
+  SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
+  CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
+
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the Instruction Cache.
+  * @note   This function always returns HAL_OK even if there is any ongoing
+  *         cache operation. The Instruction Cache is bypassed until the
+  *         cache operation completes.
+  * @retval HAL status (HAL_OK)
+  */
+HAL_StatusTypeDef HAL_ICACHE_Enable(void)
+{
+  SET_BIT(ICACHE->CR, ICACHE_CR_EN);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Instruction Cache.
+  * @note   This function waits for the cache being disabled but
+  *         not for the end of the automatic cache invalidation procedure.
+  * @retval HAL status (HAL_OK/HAL_TIMEOUT)
+  */
+HAL_StatusTypeDef HAL_ICACHE_Disable(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* Make sure BSYENDF is reset before to disable the instruction cache */
+  /* as it automatically starts a cache invalidation procedure */
+  WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+  CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for instruction cache being disabled */
+  while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+      {
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Check whether the Instruction Cache is enabled or not.
+  * @retval Status (0: disabled, 1: enabled)
+  */
+uint32_t HAL_ICACHE_IsEnabled(void)
+{
+  return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Invalidate the Instruction Cache.
+  * @note   This function waits for the end of cache invalidation procedure
+  *         and clears the associated BSYENDF flag.
+  * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT)
+  */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check if no ongoing operation */
+  if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U)
+  {
+    /* Launch cache invalidation */
+    SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
+  }
+
+  status = HAL_ICACHE_WaitForInvalidateComplete();
+
+  return status;
+}
+
+/**
+  * @brief  Invalidate the Instruction Cache with interrupt.
+  * @note   This function launches cache invalidation and returns.
+  *         User application shall resort to interrupt generation to check
+  *         the end of the cache invalidation with the BSYENDF flag and the
+  *         HAL_ICACHE_InvalidateCompleteCallback() callback.
+  * @retval HAL status (HAL_OK/HAL_ERROR)
+  */
+HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check no ongoing operation */
+  if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Make sure BSYENDF is reset before to start cache invalidation */
+    WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+    /* Enable end of cache invalidation interrupt */
+    SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+
+    /* Launch cache invalidation */
+    SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
+  }
+
+  return status;
+}
+
+/**
+  * @brief Wait for the end of the Instruction Cache invalidate procedure.
+  * @note This function checks and clears the BSYENDF flag when set.
+  * @retval HAL status (HAL_OK/HAL_TIMEOUT)
+  */
+HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check if ongoing invalidation operation */
+  if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
+  {
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait for end of cache invalidation */
+    while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
+        {
+          status = HAL_TIMEOUT;
+          break;
+        }
+      }
+    }
+  }
+
+  /* Clear BSYENDF */
+  WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+  return status;
+}
+
+
+/**
+  * @brief  Start the Instruction Cache performance monitoring.
+  * @param  MonitorType  Monitoring type
+  *         This parameter can be one of the following values:
+  *            @arg ICACHE_MONITOR_HIT_MISS   Hit & Miss monitoring
+  *            @arg ICACHE_MONITOR_HIT        Hit monitoring
+  *            @arg ICACHE_MONITOR_MISS       Miss monitoring
+  * @retval HAL status (HAL_OK)
+  */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
+{
+  /* Check the parameters */
+  assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+  SET_BIT(ICACHE->CR, MonitorType);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Instruction Cache performance monitoring.
+  * @note   Stopping the monitoring does not reset the values.
+  * @param  MonitorType  Monitoring type
+  *         This parameter can be one of the following values:
+  *            @arg ICACHE_MONITOR_HIT_MISS   Hit & Miss monitoring
+  *            @arg ICACHE_MONITOR_HIT        Hit monitoring
+  *            @arg ICACHE_MONITOR_MISS       Miss monitoring
+  * @retval HAL status (HAL_OK)
+  */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
+{
+  /* Check the parameters */
+  assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+  CLEAR_BIT(ICACHE->CR, MonitorType);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the Instruction Cache performance monitoring values.
+  * @param  MonitorType  Monitoring type
+  *         This parameter can be one of the following values:
+  *            @arg ICACHE_MONITOR_HIT_MISS   Hit & Miss monitoring
+  *            @arg ICACHE_MONITOR_HIT        Hit monitoring
+  *            @arg ICACHE_MONITOR_MISS       Miss monitoring
+  * @retval HAL status (HAL_OK)
+  */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
+{
+  /* Check the parameters */
+  assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+  /* Force/Release reset */
+  SET_BIT(ICACHE->CR, (MonitorType << 2U));
+  CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the Instruction Cache performance Hit monitoring value.
+  * @note   Upon reaching the 32-bit maximum value, monitor does not wrap.
+  * @retval Hit monitoring value
+  */
+uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
+{
+  return (ICACHE->HMONR);
+}
+
+/**
+  * @brief  Get the Instruction Cache performance Miss monitoring value.
+  * @note   Upon reaching the 32-bit maximum value, monitor does not wrap.
+  * @retval Miss monitoring value
+  */
+uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
+{
+  return (ICACHE->MMONR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions
+  * @brief    IRQ and callback functions
+  *
+  @verbatim
+  ==============================================================================
+            ##### IRQ and callback functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to handle ICACHE global interrupt
+    and the associated callback functions.
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief Handle the Instruction Cache interrupt request.
+  * @note This function should be called under the ICACHE_IRQHandler().
+  * @note This function respectively disables the interrupt and clears the
+  *       flag of any pending flag before calling the associated user callback.
+  * @retval None
+  */
+void HAL_ICACHE_IRQHandler(void)
+{
+  /* Get current interrupt flags and interrupt sources value */
+  uint32_t itflags   = READ_REG(ICACHE->SR);
+  uint32_t itsources = READ_REG(ICACHE->IER);
+
+  /* Check Instruction cache Error interrupt flag */
+  if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U)
+  {
+    /* Disable error interrupt */
+    CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+
+    /* Clear ERR pending flag */
+    WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
+
+    /* Instruction cache error interrupt user callback */
+    HAL_ICACHE_ErrorCallback();
+  }
+
+  /* Check Instruction cache BusyEnd interrupt flag */
+  if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U)
+  {
+    /* Disable end of cache invalidation interrupt */
+    CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+
+    /* Clear BSYENDF pending flag */
+    WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+    /* Instruction cache busyend interrupt user callback */
+    HAL_ICACHE_InvalidateCompleteCallback();
+  }
+}
+
+/**
+  * @brief  Cache invalidation complete callback.
+  */
+__weak void HAL_ICACHE_InvalidateCompleteCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  */
+__weak void HAL_ICACHE_ErrorCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_ICACHE_ErrorCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_irda.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_irda.c
new file mode 100644
index 000000000..f17781a8a
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_irda.c
@@ -0,0 +1,2986 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_irda.c
+  * @author  MCD Application Team
+  * @brief   IRDA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the IrDA (Infrared Data Association) Peripheral
+  *          (IRDA)
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The IRDA HAL driver can be used as follows:
+
+    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+        in setting the associated USART or UART in IRDA mode:
+        (++) Enable the USARTx/UARTx interface clock.
+        (++) USARTx/UARTx pins configuration:
+            (+++) Enable the clock for the USARTx/UARTx GPIOs.
+            (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+        (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+             and HAL_IRDA_Receive_IT() APIs):
+            (+++) Configure the USARTx/UARTx interrupt priority.
+            (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+            (+++) The specific IRDA interrupts (Transmission complete interrupt,
+                  RXNE interrupt and Error Interrupts) will be managed using the macros
+                  __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+        (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+             and HAL_IRDA_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer
+                  complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+        the normal or low power mode and the clock prescaler in the hirda handle Init structure.
+
+    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_IRDA_MspInit() API.
+
+         -@@- The specific IRDA interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+    (#) Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+       (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+       (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+       (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+     *** IRDA HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IRDA HAL driver.
+
+       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+     [..]
+       (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_IRDA_RegisterCallback() to register a user callback.
+    Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : IRDA MspInit.
+    (+) MspDeInitCallback         : IRDA MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : IRDA MspInit.
+    (+) MspDeInitCallback         : IRDA MspDeInit.
+
+    [..]
+    By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak functions in the HAL_IRDA_Init()
+    and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
+    or HAL_IRDA_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IRDA IRDA
+  * @brief HAL IRDA module driver
+  * @{
+  */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+  * @{
+  */
+#define IRDA_TEACK_REACK_TIMEOUT            1000U                                   /*!< IRDA TX or RX enable acknowledge time-out value  */
+
+#define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+                                     | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))  /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+
+#define USART_BRR_MIN    0x10U        /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX    0x0000FFFFU  /*!< USART BRR maximum authorized value */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+  * @{
+  */
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__ IRDA clock source.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __PRESCALER__ IRDA clock prescaler value.
+  * @retval Division result
+  */
+#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__)  ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
+                                                                  + ((__BAUD__)/2U)) / (__BAUD__))
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions
+  * @{
+  */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Tickstart, uint32_t Timeout);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+  * @{
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USARTx
+  in asynchronous IRDA mode.
+  (+) For the asynchronous mode only these parameters can be configured:
+      (++) Baud Rate
+      (++) Word Length
+      (++) Parity: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+      (++) Power mode
+      (++) Prescaler setting
+      (++) Receiver/transmitter modes
+
+  [..]
+  The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+  (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible IRDA frame formats are listed in the
+  following table.
+
+    Table 1. IRDA frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             IRDA frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the IRDA mode according to the specified
+  *        parameters in the IRDA_InitTypeDef and initialize the associated handle.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if (hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the IRDA handle */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+  if (hirda->gState == HAL_IRDA_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hirda->Lock = HAL_UNLOCKED;
+
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+    IRDA_InitCallbacksToDefault(hirda);
+
+    if (hirda->MspInitCallback == NULL)
+    {
+      hirda->MspInitCallback = HAL_IRDA_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hirda->MspInitCallback(hirda);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_IRDA_MspInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+  }
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
+  /* Disable the Peripheral to update the configuration registers */
+  __HAL_IRDA_DISABLE(hirda);
+
+  /* Set the IRDA Communication parameters */
+  if (IRDA_SetConfig(hirda) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
+  /* set the UART/USART in IRDA mode */
+  hirda->Instance->CR3 |= USART_CR3_IREN;
+
+  /* Enable the Peripheral */
+  __HAL_IRDA_ENABLE(hirda);
+
+  /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
+  return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+  * @brief DeInitialize the IRDA peripheral.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Check the IRDA handle allocation */
+  if (hirda == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the IRDA handle */
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+  if (hirda->MspDeInitCallback == NULL)
+  {
+    hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hirda->MspDeInitCallback(hirda);
+#else
+  HAL_IRDA_MspDeInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+  /* Disable the Peripheral */
+  __HAL_IRDA_DISABLE(hirda);
+
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+  hirda->gState    = HAL_IRDA_STATE_RESET;
+  hirda->RxState   = HAL_IRDA_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the IRDA MSP.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the IRDA MSP.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User IRDA Callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+  *         to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
+  * @param  hirda irda handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+                                            pIRDA_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+        hirda->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_TX_COMPLETE_CB_ID :
+        hirda->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+        hirda->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_RX_COMPLETE_CB_ID :
+        hirda->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ERROR_CB_ID :
+        hirda->ErrorCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+        hirda->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hirda->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hirda->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = pCallback;
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hirda->gState == HAL_IRDA_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = pCallback;
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an IRDA callback
+  *         IRDA callback is redirected to the weak predefined callback
+  * @note   The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+  *         to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
+  * @param  hirda irda handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_IRDA_STATE_READY == hirda->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+        hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
+        break;
+
+      case HAL_IRDA_TX_COMPLETE_CB_ID :
+        hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
+        break;
+
+      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+        hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
+        break;
+
+      case HAL_IRDA_RX_COMPLETE_CB_ID :
+        hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
+        break;
+
+      case HAL_IRDA_ERROR_CB_ID :
+        hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback          */
+        break;
+
+      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+        hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
+        break;
+
+      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
+                                                                                  AbortTransmitCpltCallback          */
+        break;
+
+      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak
+                                                                                  AbortReceiveCpltCallback           */
+        break;
+
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback        */
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_IRDA_STATE_RESET == hirda->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = HAL_IRDA_MspInit;
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+  *  @brief   IRDA Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                         ##### IO operation functions #####
+ ===============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+  [..]
+    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+    While receiving data, transmission should be avoided as the data to be transmitted
+    could be corrupted.
+
+  [..]
+    (#) There are two modes of transfer:
+        (++) Blocking mode: the communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) Non-Blocking mode: the communication is performed using Interrupts
+             or DMA, these API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+             will be executed respectively at the end of the Transmit or Receive process
+             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+    (#) Blocking mode APIs are :
+        (++) HAL_IRDA_Transmit()
+        (++) HAL_IRDA_Receive()
+
+    (#) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_IRDA_Transmit_IT()
+        (++) HAL_IRDA_Receive_IT()
+        (++) HAL_IRDA_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (++) HAL_IRDA_Transmit_DMA()
+        (++) HAL_IRDA_Receive_DMA()
+        (++) HAL_IRDA_DMAPause()
+        (++) HAL_IRDA_DMAResume()
+        (++) HAL_IRDA_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+        (++) HAL_IRDA_TxHalfCpltCallback()
+        (++) HAL_IRDA_TxCpltCallback()
+        (++) HAL_IRDA_RxHalfCpltCallback()
+        (++) HAL_IRDA_RxCpltCallback()
+        (++) HAL_IRDA_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (++) HAL_IRDA_Abort()
+        (++) HAL_IRDA_AbortTransmit()
+        (++) HAL_IRDA_AbortReceive()
+        (++) HAL_IRDA_Abort_IT()
+        (++) HAL_IRDA_AbortTransmit_IT()
+        (++) HAL_IRDA_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (++) HAL_IRDA_AbortCpltCallback()
+        (++) HAL_IRDA_AbortTransmitCpltCallback()
+        (++) HAL_IRDA_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+             in Interrupt mode reception .
+             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+             to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+             Transfer is kept ongoing on IRDA side.
+             If user wants to abort it, Abort services should be called by user.
+        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+             Error code is set to allow user to identify error type, and
+             HAL_IRDA_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Specify timeout value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    while (hirda->TxXferCount > 0U)
+    {
+      hirda->TxXferCount--;
+
+      if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+    }
+
+    if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Specify timeout value.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+
+    /* Computation of the mask to apply to RDR register
+       of the UART associated to the IRDA */
+    IRDA_MASK_COMPUTATION(hirda);
+    uhMask = hirda->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Check data remaining to be received */
+    while (hirda->RxXferCount > 0U)
+    {
+      hirda->RxXferCount--;
+
+      if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
+        pdata16bits++;
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+        pdata8bits++;
+      }
+    }
+
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    /* Enable the IRDA Transmit Data Register Empty Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;
+    hirda->RxXferCount = Size;
+
+    /* Computation of the mask to apply to the RDR register
+       of the UART associated to the IRDA */
+    IRDA_MASK_COMPUTATION(hirda);
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
+
+    if (hirda->Init.Parity != IRDA_PARITY_NONE)
+    {
+      /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+    else
+    {
+      /* Enable the IRDA Data Register not empty Interrupts */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+
+    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param pData pointer to data buffer (u8 or u16 data elements).
+  * @param Size Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+  uint16_t nbByte = Size;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pTxBuffPtr = pData;
+    hirda->TxXferSize = Size;
+    hirda->TxXferCount = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Set the IRDA DMA transfer complete callback */
+    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+    /* Set the IRDA DMA half transfer complete callback */
+    hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+    /* Set the DMA error callback */
+    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+    /* Set the DMA abort callback */
+    hirda->hdmatx->XferAbortCallback = NULL;
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+       should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+    {
+      nbByte = Size * 2U;
+    }
+
+    /* Check linked list mode */
+    if ((hirda->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hirda->hdmatx->LinkedListQueue != NULL) && (hirda->hdmatx->LinkedListQueue->Head != NULL))
+      {
+        /* Set DMA data size */
+        hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+        /* Set DMA source address */
+        hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+          (uint32_t)hirda->pTxBuffPtr;
+
+        /* Set DMA destination address */
+        hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+          (uint32_t)&hirda->Instance->TDR;
+
+        /* Enable the IRDA transmit DMA channel */
+        status = HAL_DMAEx_List_Start_IT(hirda->hdmatx);
+      }
+      else
+      {
+        /* Update status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable the IRDA transmit DMA channel */
+      status = HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, nbByte);
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Clear the TC flag in the ICR register */
+      __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hirda);
+
+      /* Enable the DMA transfer for transmit request by setting the DMAT bit
+         in the USART CR3 register */
+      SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Set error code to DMA */
+      hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hirda);
+
+      /* Restore hirda->gState to ready */
+      hirda->gState = HAL_IRDA_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @note   When the IRDA parity is enabled (PCE = 1), the received data contains
+  *         the parity bit (MSB position).
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+  uint16_t nbByte = Size;
+
+  /* Check that a Rx process is not already ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hirda);
+
+    hirda->pRxBuffPtr = pData;
+    hirda->RxXferSize = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Set the IRDA DMA transfer complete callback */
+    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+    /* Set the IRDA DMA half transfer complete callback */
+    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+    /* Set the DMA error callback */
+    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+    /* Set the DMA abort callback */
+    hirda->hdmarx->XferAbortCallback = NULL;
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+       should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+    {
+      nbByte = Size * 2U;
+    }
+
+    /* Check linked list mode */
+    if ((hirda->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hirda->hdmarx->LinkedListQueue != NULL) && (hirda->hdmarx->LinkedListQueue->Head != NULL))
+      {
+        /* Set DMA data size */
+        hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+        /* Set DMA source address */
+        hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+          (uint32_t)&hirda->Instance->RDR;
+
+        /* Set DMA destination address */
+        hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hirda->pRxBuffPtr;
+
+        /* Enable the DMA channel */
+        status = HAL_DMAEx_List_Start_IT(hirda->hdmarx);
+      }
+      else
+      {
+        /* Update status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable the DMA channel */
+      status = HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, nbByte);
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hirda);
+
+      if (hirda->Init.Parity != IRDA_PARITY_NONE)
+      {
+        /* Enable the UART Parity Error Interrupt */
+        SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+      }
+
+      /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+         in the USART CR3 register */
+      SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Set error code to DMA */
+      hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hirda);
+
+      /* Restore hirda->RxState to ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+  /* Process Locked */
+  __HAL_LOCK(hirda);
+
+  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+    {
+      /* Disable the IRDA DMA Tx request */
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+    }
+  }
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+      /* Disable the IRDA DMA Rx request */
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+  /* Process Locked */
+  __HAL_LOCK(hirda);
+
+  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    /* Enable the IRDA DMA Tx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+  }
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (hirda->Init.Parity != IRDA_PARITY_NONE)
+    {
+      SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    }
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the IRDA DMA Rx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+     HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+    {
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+      /* Abort the IRDA DMA Tx channel */
+      if (hirda->hdmatx != NULL)
+      {
+        if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+        {
+          if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+          {
+            /* Set error code to DMA */
+            hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+
+      IRDA_EndTxTransfer(hirda);
+    }
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+    {
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+      /* Abort the IRDA DMA Rx channel */
+      if (hirda->hdmarx != NULL)
+      {
+        if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+        {
+          if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+          {
+            /* Set error code to DMA */
+            hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+
+      IRDA_EndRxTransfer(hirda);
+    }
+  }
+
+  return HAL_OK;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+                                   USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Tx and Rx transfer counters */
+  hirda->TxXferCount = 0U;
+  hirda->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Tx transfer counter */
+  hirda->TxXferCount = 0U;
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Rx transfer counter */
+  hirda->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+                                   USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (hirda->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+    {
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (hirda->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+    {
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* IRDA Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        hirda->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* IRDA Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        hirda->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hirda->TxXferCount = 0U;
+    hirda->RxXferCount = 0U;
+
+    /* Reset errorCode */
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+    /* Restore hirda->gState and hirda->RxState to Ready */
+    hirda->gState  = HAL_IRDA_STATE_READY;
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    hirda->AbortCpltCallback(hirda);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+        hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hirda->TxXferCount = 0U;
+
+      /* Restore hirda->gState to Ready */
+      hirda->gState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      hirda->AbortTransmitCpltCallback(hirda);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+    }
+  }
+  else
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    /* Reset Tx transfer counter */
+    hirda->TxXferCount = 0U;
+
+    /* Restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    hirda->AbortTransmitCpltCallback(hirda);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+        hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hirda->RxXferCount = 0U;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+      /* Restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      hirda->AbortReceiveCpltCallback(hirda);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+    }
+  }
+  else
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    /* Reset Rx transfer counter */
+    hirda->RxXferCount = 0U;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+    /* Restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    hirda->AbortReceiveCpltCallback(hirda);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle IRDA interrupt request.
+  * @param hirda  Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t isrflags   = READ_REG(hirda->Instance->ISR);
+  uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+  if (errorflags == 0U)
+  {
+    /* IRDA in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
+    {
+      IRDA_Receive_IT(hirda);
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  cr3its = READ_REG(hirda->Instance->CR3);
+  if ((errorflags != 0U)
+      && (((cr3its & USART_CR3_EIE) != 0U)
+          || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
+  {
+    /* IRDA parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+    }
+
+    /* IRDA frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+    }
+
+    /* IRDA noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+    }
+
+    /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U) &&
+        (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
+    {
+      __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+      hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+    }
+
+    /* Call IRDA Error Call back function if need be --------------------------*/
+    if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+    {
+      /* IRDA in mode Receiver ---------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
+      {
+        IRDA_Receive_IT(hirda);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      errorcode = hirda->ErrorCode;
+      if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
+          ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the IRDA state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        IRDA_EndRxTransfer(hirda);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+        /* Disable the IRDA DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the IRDA DMA Rx channel */
+          if (hirda->hdmarx != NULL)
+          {
+            /* Set the IRDA DMA Abort callback :
+               will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+            hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+            {
+              /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+              hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+            }
+          }
+          else
+          {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+            /* Call registered user error callback */
+            hirda->ErrorCallback(hirda);
+#else
+            /* Call legacy weak user error callback */
+            HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+          }
+        }
+        else
+#endif /* HAL_DMA_MODULE_ENABLED */
+        {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+          /* Call registered user error callback */
+          hirda->ErrorCallback(hirda);
+#else
+          /* Call legacy weak user error callback */
+          HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+        /* Call registered user error callback */
+        hirda->ErrorCallback(hirda);
+#else
+        /* Call legacy weak user error callback */
+        HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* IRDA in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
+  {
+    IRDA_Transmit_IT(hirda);
+    return;
+  }
+
+  /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    IRDA_EndTransmit_IT(hirda);
+    return;
+  }
+
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified USART module.
+  * @retval None
+  */
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA error callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Receive Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   IRDA State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to return the State of IrDA
+    communication process and also return Peripheral Errors occurred during communication process
+     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+         of the IRDA peripheral handle.
+     (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+         communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the IRDA handle state.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval HAL state
+  */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
+{
+  /* Return IRDA handle state */
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = (uint32_t)hirda->gState;
+  temp2 = (uint32_t)hirda->RxState;
+
+  return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief Return the IRDA handle error code.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval IRDA Error Code
+  */
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
+{
+  return hirda->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+  * @{
+  */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  hirda IRDA handle.
+  * @retval none
+  */
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
+{
+  /* Init the IRDA Callback settings */
+  hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+  * @brief Configure the IRDA peripheral.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t tmpreg;
+  uint64_t clocksource;
+  HAL_StatusTypeDef ret = HAL_OK;
+  static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+  uint32_t pclk;
+
+  /* Check the communication parameters */
+  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+  assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+  assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+  assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+  assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+  assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+  assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Configure the IRDA Word Length, Parity and transfer Mode:
+     Set the M bits according to hirda->Init.WordLength value
+     Set PCE and PS bits according to hirda->Init.Parity value
+     Set TE and RE bits according to hirda->Init.Mode value */
+  tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+  MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+  /*--------------------- USART clock PRESC Configuration ----------------*/
+  /* Configure
+  * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
+  MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
+
+  /*-------------------------- USART GTPR Configuration ----------------------*/
+  MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  IRDA_GETCLOCKSOURCE(hirda, clocksource);
+  pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+  tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+
+  /* USARTDIV must be greater than or equal to 0d16 */
+  if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+  {
+    hirda->Instance->BRR = (uint16_t)tmpreg;
+  }
+  else
+  {
+    ret = HAL_ERROR;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief Check the IRDA Idle State.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t tickstart;
+
+  /* Initialize the IRDA ErrorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the IRDA state*/
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hirda);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle IRDA Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @param  Flag Specifies the IRDA flag to check.
+  * @param  Status The actual Flag status (SET or RESET)
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+           interrupts for the interrupt process */
+        CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+        hirda->gState  = HAL_IRDA_STATE_READY;
+        hirda->RxState = HAL_IRDA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hirda);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  DMA IRDA transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    hirda->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the IRDA Transmit Complete Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx complete callback */
+    hirda->TxCpltCallback(hirda);
+#else
+    /* Call legacy weak Tx complete callback */
+    HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+  }
+
+}
+
+/**
+  * @brief  DMA IRDA transmit process half complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx Half complete callback */
+  hirda->TxHalfCpltCallback(hirda);
+#else
+  /* Call legacy weak Tx complete callback */
+  HAL_IRDA_TxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA IRDA receive process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    hirda->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the IRDA CR3 register */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+  }
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Rx complete callback */
+  hirda->RxCpltCallback(hirda);
+#else
+  /* Call legacy weak Rx complete callback */
+  HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA IRDA receive process half complete callback.
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx Half complete callback*/
+  hirda->RxHalfCpltCallback(hirda);
+#else
+  /* Call legacy weak Rx Half complete callback */
+  HAL_IRDA_RxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief DMA IRDA communication error callback.
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+    {
+      hirda->TxXferCount = 0U;
+      IRDA_EndTxTransfer(hirda);
+    }
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+    {
+      hirda->RxXferCount = 0U;
+      IRDA_EndRxTransfer(hirda);
+    }
+  }
+
+  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hirda->ErrorCallback(hirda);
+#else
+  /* Call legacy weak user error callback */
+  HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+  hirda->RxXferCount = 0U;
+  hirda->TxXferCount = 0U;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hirda->ErrorCallback(hirda);
+#else
+  /* Call legacy weak user error callback */
+  HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+  hirda->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hirda->hdmarx != NULL)
+  {
+    if (hirda->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0U;
+  hirda->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hirda->AbortCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+  hirda->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hirda->hdmatx != NULL)
+  {
+    if (hirda->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0U;
+  hirda->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hirda->AbortCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
+  hirda->TxXferCount = 0U;
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  hirda->AbortTransmitCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hirda->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  hirda->AbortReceiveCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_IRDA_Transmit_IT().
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  const uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+  {
+    if (hirda->TxXferCount == 0U)
+    {
+      /* Disable the IRDA Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the IRDA Transmit Complete Interrupt */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+      {
+        tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+        hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+        hirda->pTxBuffPtr += 2U;
+      }
+      else
+      {
+        hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
+        hirda->pTxBuffPtr++;
+      }
+      hirda->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable the IRDA Transmit Complete Interrupt */
+  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx complete callback */
+  hirda->TxCpltCallback(hirda);
+#else
+  /* Call legacy weak Tx complete callback */
+  HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_IRDA_Receive_IT()
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *               the configuration information for the specified IRDA module.
+  * @retval None
+  */
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint16_t *tmp;
+  uint16_t  uhMask = hirda->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
+    if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+    {
+      tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
+      *tmp = (uint16_t)(uhdata & uhMask);
+      hirda->pRxBuffPtr  += 2U;
+    }
+    else
+    {
+      *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+      hirda->pRxBuffPtr++;
+    }
+
+    hirda->RxXferCount--;
+    if (hirda->RxXferCount == 0U)
+    {
+      /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx complete callback */
+      hirda->RxCpltCallback(hirda);
+#else
+      /* Call legacy weak Rx complete callback */
+      HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_iwdg.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_iwdg.c
new file mode 100644
index 000000000..1849eeb38
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_iwdg.c
@@ -0,0 +1,509 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_iwdg.c
+  * @author  MCD Application Team
+  * @brief   IWDG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Independent Watchdog (IWDG) peripheral:
+  *           + Initialization and Start functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### IWDG Generic features #####
+  ==============================================================================
+  [..]
+    (+) The IWDG can be started by either software or hardware (configurable
+        through option byte).
+
+    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+        active even if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+        the IWDG_RLR value is reloaded into the counter and the watchdog reset
+        is prevented.
+
+    (+) The IWDG is implemented in the VDD voltage domain that is still functional
+        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
+
+    (+) Debug mode: When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
+
+    [..] Min-max timeout value @32KHz (LSI): ~125us / ~131.04s
+         The IWDG timeout may vary due to LSI clock frequency dispersion.
+         STM32N6xx devices provide the capability to measure the LSI clock
+         frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+         The measured value can be used to have an IWDG timeout with an
+         acceptable accuracy.
+
+    [..] Default timeout value (necessary for IWDG_SR status register update):
+         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+         This frequency being subject to variations as mentioned above, the
+         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+         below) may become too short or too long.
+         In such cases, this default timeout value can be tuned by redefining
+         the constant LSI_VALUE at user-application level (based, for instance,
+         on the measured LSI clock frequency as explained above).
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Register callback to treat Iwdg interrupt and MspInit using HAL_IWDG_RegisterCallback().
+      (++) Provide exiting handle as first parameter.
+      (++) Provide which callback will be registered using one value from
+           HAL_IWDG_CallbackIDTypeDef.
+      (++) Provide callback function pointer.
+
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+           clock is forced ON and IWDG counter starts counting down.
+      (++) Enable write access to configuration registers:
+          IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR.
+      (++) Configure the IWDG prescaler and counter reload value. This reload
+           value will be loaded in the IWDG counter each time the watchdog is
+           reloaded, then the IWDG will start counting down from this value.
+      (++) Depending on window parameter:
+        (+++) If Window Init parameter is same as Window register value,
+             nothing more is done but reload counter value in order to exit
+             function with exact time base.
+        (+++) Else modify Window register. This will automatically reload
+             watchdog counter.
+      (++) Depending on Early Wakeup Interrupt parameter:
+        (+++) If EWI is set to disable, comparator is set to 0, interrupt is
+             disable & flag is clear.
+        (+++) Else modify EWCR register, setting comparator value, enable
+             interrupt & clear flag.
+      (++) Wait for status flags to be reset.
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
+     *** IWDG HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IWDG HAL driver:
+      (+) __HAL_IWDG_START: Enable the IWDG peripheral
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+  * @brief IWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+  * @{
+  */
+/* Status register needs up to 5 LSI clock periods to be updated. However a
+   synchronisation is added on prescaled LSI clock rising edge, so we only
+   consider a highest prescaler cycle.
+   The timeout value is calculated using the highest prescaler (1024) and
+   the LSI_VALUE constant. The value of this constant can be changed by the user
+   to take into account possible LSI clock period variations.
+   The timeout value is multiplied by 1000 to be converted in milliseconds.
+   LSI startup time is also considered here by adding LSI_STARTUP_TIME
+   converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT        (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+  *  @brief    Initialization and Start functions.
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Start functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the
+          IWDG_InitTypeDef of associated handle.
+      (+) Manage Window option.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+          is reloaded in order to exit function with correct time base.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the IWDG according to the specified parameters in the
+  *         IWDG_InitTypeDef and start watchdog. Before exiting function,
+  *         watchdog is refreshed in order to have correct time base.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+  uint32_t tickstart;
+
+  /* Check the IWDG handle allocation */
+  if (hiwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+  assert_param(IS_IWDG_EWI(hiwdg->Init.EWI));
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+  /* Reset Callback pointers */
+  if (hiwdg->EwiCallback == NULL)
+  {
+    hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback;
+  }
+  if (hiwdg->MspInitCallback == NULL)
+  {
+    hiwdg->MspInitCallback = HAL_IWDG_MspInit;
+  }
+
+  /* Init the low level hardware */
+  hiwdg->MspInitCallback(hiwdg);
+#else
+  /* Init the low level hardware */
+  HAL_IWDG_MspInit(hiwdg);
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+
+  /* Enable IWDG. LSI is turned on automatically */
+  __HAL_IWDG_START(hiwdg);
+
+  /* Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers by writing
+  0x5555 in KR */
+  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+  /* Check Reload update flag, before performing any reload of the counter, else previous value
+  will be taken. */
+  tickstart = HAL_GetTick();
+
+  /* Wait for register to be updated */
+  while ((hiwdg->Instance->SR & IWDG_SR_RVU) != 0x00u)
+  {
+    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
+      if ((hiwdg->Instance->SR & IWDG_SR_RVU) != 0x00u)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register */
+  hiwdg->Instance->ICR = IWDG_ICR_EWIC;
+
+  if (hiwdg->Init.EWI != IWDG_EWI_DISABLE)
+  {
+    /* EWI comparator value different from 0, Enable the early wakeup interrupt
+     * Set Watchdog Early Wakeup Comparator value
+     */
+    hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | hiwdg->Init.EWI;
+  }
+  else
+  {
+    hiwdg->Instance->EWCR = 0x00U;
+  }
+  /* Check pending flag, if previous update not done, return timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait for register to be updated */
+  while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+  {
+    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
+      if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* If window parameter is different than current value, modify window
+  register */
+  if (hiwdg->Instance->WINR != hiwdg->Init.Window)
+  {
+    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+    even if window feature is disabled, Watchdog will be reloaded by writing
+    windows register */
+    hiwdg->Instance->WINR = hiwdg->Init.Window;
+  }
+  else
+  {
+    /* Reload IWDG counter with value defined in the reload register */
+    __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the IWDG MSP.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @note   When rewriting this function in user file, mechanism may be added
+  *         to avoid multiple initialize when HAL_IWDG_Init function is called
+  *         again to change parameters.
+  * @retval None
+  */
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hiwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IWDG_MspInit could be implemented in the user file
+   */
+}
+
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User IWDG Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param  hiwdg IWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID,
+                                            pIWDG_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    switch (CallbackID)
+    {
+      case HAL_IWDG_EWI_CB_ID:
+        hiwdg->EwiCallback = pCallback;
+        break;
+      case HAL_IWDG_MSPINIT_CB_ID:
+        hiwdg->MspInitCallback = pCallback;
+        break;
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Unregister a IWDG Callback
+  *         IWDG Callback is redirected to the weak (surcharged) predefined callback
+  * @param  hiwdg IWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case HAL_IWDG_EWI_CB_ID:
+      hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback;
+      break;
+    case HAL_IWDG_MSPINIT_CB_ID:
+      hiwdg->MspInitCallback = HAL_IWDG_MspInit;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Refresh the IWDG.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Refresh the IWDG.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get back IWDG running status
+  * @note   This API allows to know if IWDG has been started by other master, thread
+  *         or by hardware.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval can be one of following value :
+  *           @arg @ref IWDG_STATUS_DISABLE
+  *           @arg @ref IWDG_STATUS_ENABLE
+  */
+uint32_t HAL_IWDG_GetActiveStatus(const IWDG_HandleTypeDef *hiwdg)
+{
+  uint32_t status;
+
+  /* Get back ONF flag */
+  status = (hiwdg->Instance->SR & IWDG_SR_ONF);
+
+  /* Return status */
+  return status;
+}
+
+
+/**
+  * @brief  Handle IWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+  *         or data logging must be performed before the actual reset is generated.
+  *         The EWI interrupt is enabled by calling HAL_IWDG_Init function with
+  *         EWIMode set to IWDG_EWI_ENABLE.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is
+  *         generated and the corresponding Interrupt Service Routine (ISR) can
+  *         be used to trigger specific actions (such as communications or data
+  *         logging), before resetting the device.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval None
+  */
+void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Check if IWDG Early Wakeup Interrupt occurred */
+  if ((hiwdg->Instance->SR & IWDG_SR_EWIF) != 0x00u)
+  {
+    /* Clear the IWDG Early Wakeup flag */
+    hiwdg->Instance->ICR = IWDG_ICR_EWIC;
+
+#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
+    /* Early Wakeup registered callback */
+    hiwdg->EwiCallback(hiwdg);
+#else
+    /* Early Wakeup callback */
+    HAL_IWDG_EarlyWakeupCallback(hiwdg);
+#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
+  }
+}
+
+
+/**
+  * @brief  IWDG Early Wakeup callback.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval None
+  */
+__weak void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hiwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IWDG_EarlyWakeupCallback could be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_jpeg.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_jpeg.c
new file mode 100644
index 000000000..d4f9d4275
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_jpeg.c
@@ -0,0 +1,4285 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_jpeg.c
+  * @author  MCD Application Team
+  * @brief   JPEG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the JPEG encoder/decoder peripheral:
+  *           + Initialization and de-initialization functions
+  *           + JPEG processing functions encoding and decoding
+  *           + JPEG decoding Getting Info and encoding configuration setting
+  *           + JPEG enable/disable header parsing functions (for decoding)
+  *           + JPEG Input/Output Buffer configuration.
+  *           + JPEG callback functions
+  *           + JPEG Abort/Pause/Resume functions
+  *           + JPEG custom quantization tables setting functions
+  *           + IRQ handler management
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.
+         Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.
+
+     (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set
+         the encoding parameters (mandatory before calling the encoding function).
+         the application can change the encoding parameter ImageQuality from
+         1 to 100 to obtain a more or less quality (visual quality vs the original row image),
+         and inversely more or less jpg file size.
+
+     (#) Note that for decoding operation the JPEG peripheral output data are organized in
+         YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification
+         ISO/IEC 10918-1 standard.
+         It is up to the application to transform these YCbCr blocks to RGB data that can be display.
+
+         Respectively, for Encoding operation the JPEG peripheral input should be organized
+         in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr
+         MCU blocks transformation before feeding the JPEG peripheral with data.
+
+     (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively
+         a JPEG encoding/decoding operation in polling method (blocking).
+
+     (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively
+         a JPEG encoding/decoding operation with Interrupt method (not blocking).
+
+     (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively
+         a JPEG encoding/decoding operation with DMA method (not blocking).
+
+     (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation
+         is a JPEG decoding to provide the application with JPEG image  parameters.
+         This callback is asserted when the JPEG peripheral successfully parse the
+         JPEG header.
+
+     (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding
+         operations to inform the application that the input buffer has been
+         consumed by the peripheral and to ask for a new data chunk if the operation
+         (encoding/decoding) has not been complete yet.
+
+        (++) This CallBack should be implemented in the application side. It should
+             call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
+             or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT
+             to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
+             application to provide a new input data chunk.
+             Once the application succeed getting new data and if the input has been paused,
+             the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
+             input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
+             If the application has ended feeding the HAL JPEG with input data (no more input data), the application
+             Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
+             with the parameter InDataLength set to zero.
+
+         (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
+              to the application to provide the input data (for encoding or decoding) by chunks.
+              If the new input data chunk is not available (because data should be read from an input file
+              for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
+              Once the new input data chunk is available ( read from a file for example), the application
+              can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk
+              then resume the JPEG HAL input by calling function HAL_JPEG_Resume.
+
+         (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume.
+              any time (outside the HAL_JPEG_GetDataCallback)  Once the new input chunk data available.
+              However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
+              (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
+              Transferring the previous chunk buffer to the JPEG peripheral.
+
+     (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver
+         has filled the given output buffer with the given size.
+
+         (++) This CallBack should be implemented in the application side. It should
+              call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
+              with the new output buffer location and size to be used  to store next data chunk.
+              if the application is not ready to provide the output chunk location then it can
+              call the function HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_OUTPUT
+              to inform the JPEG HAL driver that it shall pause output data. Once the application
+              is ready to receive the new data chunk (output buffer location free or available) it should call
+              the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
+              with the new output chunk buffer location and size, then call HAL_JPEG_Resume
+              to inform the HAL that it shall resume outputting data in the given output buffer.
+
+         (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
+              the application to receive data from the JPEG peripheral by chunks. when a chunk
+              is received, the application can pause the HAL JPEG output data to be able to process
+              these received data (YCbCr to RGB conversion in case of decoding or data storage in case
+              of encoding).
+
+         (++) The application can call  functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume.
+              any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use.
+              However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
+              (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
+              Transferring the previous chunk buffer from the JPEG peripheral to the application.
+
+     (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has
+         ended the current JPEG encoding operation, and all output data has been transmitted
+         to the application.
+
+     (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has
+         ended the current JPEG decoding operation. and all output data has been transmitted
+         to the application.
+
+     (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during
+         the current operation. the application can call the function HAL_JPEG_GetError()
+         to retrieve the error codes.
+
+     (#) By default the HAL JPEG driver uses the default quantization tables
+         as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
+         User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables
+         Note that for decoding the quantization tables are automatically extracted from
+         the JPEG header.
+
+      (#) To control JPEG state you can use the following function: HAL_JPEG_GetState()
+
+     *** JPEG HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in JPEG HAL driver.
+
+      (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.
+      (+) __HAL_JPEG_ENABLE             : Enable the JPEG peripheral.
+      (+) __HAL_JPEG_DISABLE            : Disable the JPEG peripheral.
+      (+) __HAL_JPEG_GET_FLAG           : Check the specified JPEG status flag.
+      (+) __HAL_JPEG_CLEAR_FLAG         : Clear the specified JPEG status flag.
+      (+) __HAL_JPEG_ENABLE_IT          : Enable the specified JPEG Interrupt.
+      (+) __HAL_JPEG_DISABLE_IT         : Disable the specified JPEG Interrupt.
+      (+) __HAL_JPEG_GET_IT_SOURCE      : returns the state of the specified JPEG Interrupt (Enabled or disabled).
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_JPEG_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Functions HAL_JPEG_RegisterCallback() or HAL_JPEG_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function HAL_JPEG_RegisterCallback() allows to register following callbacks:
+    (+) EncodeCpltCallback : callback for end of encoding operation.
+    (+) DecodeCpltCallback : callback for end of decoding operation.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : JPEG MspInit.
+    (+) MspDeInitCallback  : JPEG MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
+  register callbacks : respectively HAL_JPEG_RegisterInfoReadyCallback(),
+  HAL_JPEG_RegisterGetDataCallback() and HAL_JPEG_RegisterDataReadyCallback().
+
+  Use function HAL_JPEG_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_JPEG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) EncodeCpltCallback : callback for end of encoding operation.
+    (+) DecodeCpltCallback : callback for end of decoding operation.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : JPEG MspInit.
+    (+) MspDeInitCallback  : JPEG MspDeInit.
+
+  For callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated
+  unregister callbacks : respectively HAL_JPEG_UnRegisterInfoReadyCallback(),
+  HAL_JPEG_UnRegisterGetDataCallback() and HAL_JPEG_UnRegisterDataReadyCallback().
+
+  By default, after the HAL_JPEG_Init() and when the state is HAL_JPEG_STATE_RESET
+  all callbacks are set to the corresponding weak functions :
+  examples HAL_JPEG_DecodeCpltCallback() , HAL_JPEG_GetDataCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_JPEG_Init()/ HAL_JPEG_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_JPEG_Init() / HAL_JPEG_DeInit()
+  keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_JPEG_STATE_READY state only.
+  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+  in HAL_JPEG_STATE_READY or HAL_JPEG_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_JPEG_RegisterCallback() before calling HAL_JPEG_DeInit()
+  or HAL_JPEG_Init() function.
+
+  When The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+
+#if defined (JPEG)
+
+/** @defgroup JPEG JPEG
+  * @brief JPEG HAL module driver.
+  * @{
+  */
+
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup JPEG_Private_Constants
+  * @{
+  */
+#define JPEG_TIMEOUT_VALUE  ((uint32_t)1000)     /* 1s */
+#define JPEG_AC_HUFF_TABLE_SIZE  ((uint32_t)162) /* Huffman AC table size : 162 codes*/
+#define JPEG_DC_HUFF_TABLE_SIZE  ((uint32_t)12)  /* Huffman DC table size : 12 codes*/
+
+#define JPEG_QUANTVAL_MAX ((uint32_t)255)           /* Quantization values are 8-bit numbers*/
+#define JPEG_LOW_QUALITY_REFERENCE ((uint32_t)5000) /*Reference value to generate scaling factor
+                                                      for low quality factors (<50) */
+#define JPEG_HIGH_QUALITY_REFERENCE ((uint32_t)200) /*Reference value to generate scaling factor
+                                                      for high quality factors (>=50)*/
+
+#define JPEG_FIFO_SIZE ((uint32_t)16U)              /* JPEG Input/Output HW FIFO size in words*/
+
+#define JPEG_FIFO_TH_SIZE ((uint32_t)4U)            /* JPEG Input/Output HW FIFO Threshold in words*/
+
+#define JPEG_DMA_MASK     ((uint32_t)0x00001800)     /* JPEG DMA request Mask*/
+#define JPEG_DMA_IDMA     ((uint32_t)JPEG_CR_IDMAEN)  /* DMA request for the input FIFO */
+#define JPEG_DMA_ODMA     ((uint32_t)JPEG_CR_ODMAEN)  /* DMA request for the output FIFO */
+
+#define JPEG_INTERRUPT_MASK  ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
+
+#define JPEG_CONTEXT_ENCODE          ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/
+#define JPEG_CONTEXT_DECODE          ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/
+#define JPEG_CONTEXT_OPERATION_MASK  ((uint32_t)0x00000003) /* JPEG context : operation Mask */
+
+#define JPEG_CONTEXT_POLLING        ((uint32_t)0x00000004)  /* JPEG context : Transfer use Polling */
+#define JPEG_CONTEXT_IT             ((uint32_t)0x00000008)  /* JPEG context : Transfer use Interrupt */
+#define JPEG_CONTEXT_DMA            ((uint32_t)0x0000000C)  /* JPEG context : Transfer use DMA */
+#define JPEG_CONTEXT_METHOD_MASK    ((uint32_t)0x0000000C)  /* JPEG context : Transfer Mask */
+
+
+#define JPEG_CONTEXT_CONF_ENCODING  ((uint32_t)0x00000100)  /* JPEG context : encoding config done */
+
+#define JPEG_CONTEXT_PAUSE_INPUT    ((uint32_t)0x00001000)  /* JPEG context : Pause Input */
+#define JPEG_CONTEXT_PAUSE_OUTPUT   ((uint32_t)0x00002000)  /* JPEG context : Pause Output */
+
+#define JPEG_CONTEXT_CUSTOM_TABLES  ((uint32_t)0x00004000)  /* JPEG context : Use custom quantization tables */
+
+#define JPEG_CONTEXT_ENDING_DMA     ((uint32_t)0x00008000)  /* JPEG context : ending with DMA in progress */
+
+#define JPEG_PROCESS_ONGOING        ((uint32_t)0x00000000)  /* Process is on going */
+#define JPEG_PROCESS_DONE           ((uint32_t)0x00000001)  /* Process is done (ends) */
+#define JPEG_GET_DMA_REMAIN_DATA(__HANDLE__)     (__HAL_DMA_GET_COUNTER(__HANDLE__)\
+                                                  + HAL_DMAEx_GetFifoLevel(__HANDLE__))
+/**
+  * @}
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/** @addtogroup JPEG_Private_Types
+  * @{
+  */
+
+/*
+ JPEG Huffman Table Structure definition :
+ This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard,
+ Annex C Huffman Table specification
+ */
+typedef struct
+{
+  /* These two fields directly represent the contents of a JPEG DHT marker */
+  uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits,
+                             this parameter corresponds to BITS list in the Annex C */
+
+  uint8_t HuffVal[162];    /*!< The symbols, in order of incremented code length,
+                             this parameter corresponds to HUFFVAL list in the Annex C */
+
+
+} JPEG_ACHuffTableTypeDef;
+
+typedef struct
+{
+  /* These two fields directly represent the contents of a JPEG DHT marker */
+  uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits,
+                             this parameter corresponds to BITS list in the Annex C */
+
+  uint8_t HuffVal[12];    /*!< The symbols, in order of incremented code length,
+                            this parameter corresponds to HUFFVAL list in the Annex C */
+
+
+} JPEG_DCHuffTableTypeDef;
+
+typedef struct
+{
+  uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE];      /*!< Code length  */
+
+  uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */
+
+} JPEG_AC_HuffCodeTableTypeDef;
+
+typedef struct
+{
+  uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE];        /*!< Code length  */
+
+  uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */
+
+} JPEG_DC_HuffCodeTableTypeDef;
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup JPEG_Private_Macros
+  * @{
+  */
+#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__)  ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK))
+/*note  : To disable a DMA request we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
+         located in the same DMA request enable register (CR register). */
+#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0UL)
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup JPEG_Private_Variables
+  * @{
+  */
+
+/* The following Huffman tables, are based on the JPEG standard as defined by the ITU-T Recommendation T.81. */
+static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable =
+{
+  { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },   /*Bits*/
+
+  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }           /*HUFFVAL */
+
+};
+
+static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable =
+{
+  { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },  /*Bits*/
+
+  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }          /*HUFFVAL */
+};
+
+static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable =
+{
+  { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d },  /*Bits*/
+
+  {
+    0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,     /*HUFFVAL */
+    0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
+    0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
+    0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
+    0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
+    0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
+    0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+    0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+    0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+    0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+    0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+    0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+    0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
+    0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
+    0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
+    0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
+    0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
+    0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
+    0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
+    0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+    0xf9, 0xfa
+  }
+};
+
+static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable =
+{
+  { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 },   /*Bits*/
+
+  {
+    0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,      /*HUFFVAL */
+    0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
+    0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
+    0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
+    0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
+    0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
+    0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
+    0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
+    0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
+    0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+    0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
+    0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+    0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
+    0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
+    0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
+    0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
+    0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
+    0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
+    0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
+    0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+    0xf9, 0xfa
+  }
+};
+
+static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =
+{
+  0,   1,   8,  16,   9,   2,   3,  10,
+  17,  24,  32,  25,  18,  11,   4,   5,
+  12,  19,  26,  33,  40,  48,  41,  34,
+  27,  20,  13,   6,   7,  14,  21,  28,
+  35,  42,  49,  56,  57,  50,  43,  36,
+  29,  22,  15,  23,  30,  37,  44,  51,
+  58,  59,  52,  45,  38,  31,  39,  46,
+  53,  60,  61,  54,  47,  55,  62,  63
+};
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup JPEG_Private_Functions_Prototypes
+  * @{
+  */
+
+static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(const uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode,
+                                                uint32_t *LastK);
+static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable,
+                                                           JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);
+static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable,
+                                                           JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);
+static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC,
+                                             const __IO uint32_t *DCTableAddress);
+static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC,
+                                             const __IO uint32_t *ACTableAddress);
+static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_Set_Huff_DHTMem(const JPEG_HandleTypeDef *hjpeg);
+static uint32_t  JPEG_Set_Quantization_Mem(const JPEG_HandleTypeDef *hjpeg, const uint8_t *QTable,
+                                           __IO uint32_t *QTableAddress);
+static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg);
+
+static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg);
+static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords);
+static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords);
+static uint32_t JPEG_GetQuality(const JPEG_HandleTypeDef *hjpeg);
+
+static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma);
+static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma);
+static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma);
+static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma)  ;
+
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Exported_Functions JPEG Exported Functions
+  * @{
+  */
+
+/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and de-initialization functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the JPEG peripheral and creates the associated handle
+      (+) DeInitialize the JPEG peripheral
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the JPEG according to the specified
+  *         parameters in the JPEG_InitTypeDef and creates the associated handle.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)
+{
+  /* These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. */
+  static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
+  {
+    16,  11,  10,  16,  24,  40,  51,  61,
+    12,  12,  14,  19,  26,  58,  60,  55,
+    14,  13,  16,  24,  40,  57,  69,  56,
+    14,  17,  22,  29,  51,  87,  80,  62,
+    18,  22,  37,  56,  68, 109, 103,  77,
+    24,  35,  55,  64,  81, 104, 113,  92,
+    49,  64,  78,  87, 103, 121, 120, 101,
+    72,  92,  95,  98, 112, 100, 103,  99
+  };
+  static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] =
+  {
+    17,  18,  24,  47,  99,  99,  99,  99,
+    18,  21,  26,  66,  99,  99,  99,  99,
+    24,  26,  56,  99,  99,  99,  99,  99,
+    47,  66,  99,  99,  99,  99,  99,  99,
+    99,  99,  99,  99,  99,  99,  99,  99,
+    99,  99,  99,  99,  99,  99,  99,  99,
+    99,  99,  99,  99,  99,  99,  99,  99,
+    99,  99,  99,  99,  99,  99,  99,  99
+  };
+
+  /* Check the JPEG handle allocation */
+  if (hjpeg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+  if (hjpeg->State == HAL_JPEG_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hjpeg->Lock = HAL_UNLOCKED;
+
+    hjpeg->InfoReadyCallback  = HAL_JPEG_InfoReadyCallback;  /* Legacy weak InfoReadyCallback  */
+    hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */
+    hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */
+    hjpeg->ErrorCallback      = HAL_JPEG_ErrorCallback;      /* Legacy weak ErrorCallback      */
+    hjpeg->GetDataCallback    = HAL_JPEG_GetDataCallback;    /* Legacy weak GetDataCallback    */
+    hjpeg->DataReadyCallback  = HAL_JPEG_DataReadyCallback;  /* Legacy weak DataReadyCallback  */
+
+    if (hjpeg->MspInitCallback == NULL)
+    {
+      hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hjpeg->MspInitCallback(hjpeg);
+  }
+#else
+  if (hjpeg->State == HAL_JPEG_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hjpeg->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_JPEG_MspInit(hjpeg);
+  }
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+  /* Change the JPEG state */
+  hjpeg->State = HAL_JPEG_STATE_BUSY;
+
+  /* Start the JPEG Core*/
+  __HAL_JPEG_ENABLE(hjpeg);
+
+  /* Stop the JPEG encoding/decoding process*/
+  hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+  /* Disable All Interrupts */
+  __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+
+  /* Disable All DMA requests */
+  JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
+
+  /* Flush input and output FIFOs*/
+  hjpeg->Instance->CR |= JPEG_CR_IFF;
+  hjpeg->Instance->CR |= JPEG_CR_OFF;
+
+  /* Clear all flags */
+  __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
+
+  /* init default quantization tables*/
+  hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable);
+  hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable);
+  hjpeg->QuantTable2 = NULL;
+  hjpeg->QuantTable3 = NULL;
+
+  /* init the default Huffman tables*/
+  if (JPEG_Set_HuffEnc_Mem(hjpeg) != HAL_OK)
+  {
+    hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE;
+
+    return HAL_ERROR;
+  }
+
+  /* Enable header processing*/
+  hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
+
+  /* Reset JpegInCount and JpegOutCount */
+  hjpeg->JpegInCount = 0;
+  hjpeg->JpegOutCount = 0;
+
+  /* Change the JPEG state */
+  hjpeg->State = HAL_JPEG_STATE_READY;
+
+  /* Reset the JPEG ErrorCode */
+  hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
+
+  /* Clear the context fields */
+  hjpeg->Context = 0;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the JPEG peripheral.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Check the JPEG handle allocation */
+  if (hjpeg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+  if (hjpeg->MspDeInitCallback == NULL)
+  {
+    hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hjpeg->MspDeInitCallback(hjpeg);
+
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_JPEG_MspDeInit(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+  /* Change the JPEG state */
+  hjpeg->State = HAL_JPEG_STATE_BUSY;
+
+  /* Reset the JPEG ErrorCode */
+  hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;
+
+  /* Reset JpegInCount and JpegOutCount */
+  hjpeg->JpegInCount = 0;
+  hjpeg->JpegOutCount = 0;
+
+  /* Change the JPEG state */
+  hjpeg->State = HAL_JPEG_STATE_RESET;
+
+  /*Clear the context fields*/
+  hjpeg->Context = 0;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the JPEG MSP.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes JPEG MSP.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User JPEG Callback
+  *         To be used to override the weak predefined callback
+  * @param  hjpeg JPEG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
+  *          @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
+  *          @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,
+                                            pJPEG_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_JPEG_ENCODE_CPLT_CB_ID :
+        hjpeg->EncodeCpltCallback = pCallback;
+        break;
+
+      case HAL_JPEG_DECODE_CPLT_CB_ID :
+        hjpeg->DecodeCpltCallback = pCallback;
+        break;
+
+      case HAL_JPEG_ERROR_CB_ID :
+        hjpeg->ErrorCallback = pCallback;
+        break;
+
+      case HAL_JPEG_MSPINIT_CB_ID :
+        hjpeg->MspInitCallback = pCallback;
+        break;
+
+      case HAL_JPEG_MSPDEINIT_CB_ID :
+        hjpeg->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_JPEG_STATE_RESET == hjpeg->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_JPEG_MSPINIT_CB_ID :
+        hjpeg->MspInitCallback = pCallback;
+        break;
+
+      case HAL_JPEG_MSPDEINIT_CB_ID :
+        hjpeg->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+/**
+  * @brief  Unregister a JPEG Callback
+  *         JPEG callback is redirected to the weak predefined callback
+  * @param  hjpeg JPEG handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID
+  *          @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID
+  *          @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_JPEG_ENCODE_CPLT_CB_ID :
+        hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback  */
+        break;
+
+      case HAL_JPEG_DECODE_CPLT_CB_ID :
+        hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback  */
+        break;
+
+      case HAL_JPEG_ERROR_CB_ID :
+        hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback;           /* Legacy weak ErrorCallback  */
+        break;
+
+      case HAL_JPEG_MSPINIT_CB_ID :
+        hjpeg->MspInitCallback = HAL_JPEG_MspInit;              /* Legacy weak MspInit  */
+        break;
+
+      case HAL_JPEG_MSPDEINIT_CB_ID :
+        hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit;          /* Legacy weak MspDeInit  */
+        break;
+
+      default :
+        /* Update the error code */
+        hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_JPEG_STATE_RESET == hjpeg->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_JPEG_MSPINIT_CB_ID :
+        hjpeg->MspInitCallback = HAL_JPEG_MspInit;           /* Legacy weak MspInit  */
+        break;
+
+      case HAL_JPEG_MSPDEINIT_CB_ID :
+        hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit;       /* Legacy weak MspInit  */
+        break;
+
+      default :
+        /* Update the error code */
+        hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+/**
+  * @brief  Register Info Ready JPEG Callback
+  *         To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback
+  * @param  hjpeg JPEG handle
+  * @param  pCallback pointer to the Info Ready Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,
+                                                     pJPEG_InfoReadyCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    hjpeg->InfoReadyCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Info Ready JPEG Callback
+  *         Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback
+  * @param  hjpeg JPEG handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+/**
+  * @brief  Register Get Data JPEG Callback
+  *         To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback
+  * @param  hjpeg JPEG handle
+  * @param  pCallback pointer to the Get Data Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    hjpeg->GetDataCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Get Data JPEG Callback
+  *         Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback
+  * @param  hjpeg JPEG handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback;  /* Legacy weak GetDataCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+/**
+  * @brief  Register Data Ready JPEG Callback
+  *         To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback
+  * @param  hjpeg JPEG handle
+  * @param  pCallback pointer to the Get Data Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,
+                                                     pJPEG_DataReadyCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    hjpeg->DataReadyCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Data Ready JPEG Callback
+  *         Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback
+  * @param  hjpeg JPEG handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (HAL_JPEG_STATE_READY == hjpeg->State)
+  {
+    hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback;  /* Legacy weak DataReadyCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hjpeg);
+  return status;
+}
+
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions
+  *  @brief    JPEG Configuration functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration
+      (+) HAL_JPEG_GetInfo() :  Extract the image configuration from the JPEG header during the decoding
+      (+) HAL_JPEG_EnableHeaderParsing() :  Enable JPEG Header parsing for decoding
+      (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding
+      (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the JPEG encoding configuration.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pConf pointer to a JPEG_ConfTypeDef structure that contains
+  *         the encoding configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, const JPEG_ConfTypeDef *pConf)
+{
+  uint32_t error;
+  uint32_t numberMCU;
+  uint32_t hfactor;
+  uint32_t vfactor;
+  uint32_t hMCU;
+  uint32_t vMCU;
+
+  /* Check the JPEG handle allocation */
+  if ((hjpeg == NULL) || (pConf == NULL))
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace));
+    assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling));
+    assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality));
+
+    /* Process Locked */
+    __HAL_LOCK(hjpeg);
+
+    if (hjpeg->State == HAL_JPEG_STATE_READY)
+    {
+      hjpeg->State = HAL_JPEG_STATE_BUSY;
+
+      hjpeg->Conf.ColorSpace          =  pConf->ColorSpace;
+      hjpeg->Conf.ChromaSubsampling   =  pConf->ChromaSubsampling;
+      hjpeg->Conf.ImageHeight         =  pConf->ImageHeight;
+      hjpeg->Conf.ImageWidth          =  pConf->ImageWidth;
+      hjpeg->Conf.ImageQuality        =  pConf->ImageQuality;
+
+      /* Reset the Color Space : by default only one quantization table is used*/
+      hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE;
+
+      /* Set Number of color components*/
+      if (hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)
+      {
+        /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/
+        hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING;
+
+        JPEG_SetColorGrayScale(hjpeg);
+        /* Set quantization table 0*/
+        error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
+      }
+      else if (hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE)
+      {
+        /*
+           Set the Color Space for YCbCr : 2 quantization tables are used
+           one for Luminance(Y) and one for both Chrominances (Cb & Cr)
+          */
+        hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0;
+
+        JPEG_SetColorYCBCR(hjpeg);
+
+        /* Set quantization table 0*/
+        error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
+        /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/
+        (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
+
+        if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL)
+        {
+          /*Use user customized quantization tables , 1 table per component*/
+          /* use 3 quantization tables , one for each component*/
+          hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE);
+          hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1;
+
+          (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
+
+          /*Use Quantization 1 table for component 1*/
+          hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT);
+          hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0;
+
+          /*Use Quantization 2 table for component 2*/
+          hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT);
+          hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;
+        }
+      }
+      else /* ColorSpace == JPEG_CMYK_COLORSPACE */
+      {
+        JPEG_SetColorCMYK(hjpeg);
+
+        /* Set quantization table 0*/
+        error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0));
+        /*By default quantization table 0 for All components*/
+
+        if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL)
+        {
+          /*Use user customized quantization tables , 1 table per component*/
+          /* use 4 quantization tables , one for each component*/
+          hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE;
+
+          (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1));
+          (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2));
+          (void) JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3));
+
+          /*Use Quantization 1 table for component 1*/
+          hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0;
+
+          /*Use Quantization 2 table for component 2*/
+          hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;
+
+          /*Use Quantization 3 table for component 3*/
+          hjpeg->Instance->CONFR7 |=  JPEG_CONFR7_QT;
+        }
+      }
+
+      if (error != 0UL)
+      {
+        hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hjpeg);
+
+        /* Set the JPEG State to ready */
+        hjpeg->State = HAL_JPEG_STATE_READY;
+
+        return  HAL_ERROR;
+      }
+      /* Set the image size*/
+      /* set the number of lines*/
+      MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFFUL) << 16));
+      /* set the number of pixels per line*/
+      MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFFUL) << 16));
+
+
+      if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/
+      {
+        hfactor = 16;
+        vfactor = 16;
+      }
+      else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/
+      {
+        hfactor = 16;
+        vfactor = 8;
+      }
+      else /* Default is 8x8 MCU,  4:4:4*/
+      {
+        hfactor = 8;
+        vfactor = 8;
+      }
+
+      hMCU = (hjpeg->Conf.ImageWidth / hfactor);
+      if ((hjpeg->Conf.ImageWidth % hfactor) != 0UL)
+      {
+        hMCU++; /*+1 for horizontal incomplete MCU */
+      }
+
+      vMCU = (hjpeg->Conf.ImageHeight / vfactor);
+      if ((hjpeg->Conf.ImageHeight % vfactor) != 0UL)
+      {
+        vMCU++; /*+1 for vertical incomplete MCU */
+      }
+
+      numberMCU = (hMCU * vMCU) - 1UL; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/
+      /* Set the number of MCU*/
+      hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU);
+
+      hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      /* Set the JPEG State to ready */
+      hjpeg->State = HAL_JPEG_STATE_READY;
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      /* Return function status */
+      return HAL_BUSY;
+    }
+  }
+}
+
+/**
+  * @brief  Extract the image configuration from the JPEG header during the decoding
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pInfo pointer to a JPEG_ConfTypeDef structure that contains
+  *         The JPEG decoded header information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
+{
+  uint32_t yblockNb;
+  uint32_t cBblockNb;
+  uint32_t cRblockNb;
+
+  /* Check the JPEG handle allocation */
+  if ((hjpeg == NULL) || (pInfo == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /*Read the conf parameters */
+  if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)
+  {
+    pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE;
+  }
+  else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0UL)
+  {
+    pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE;
+  }
+  else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)
+  {
+    pInfo->ColorSpace = JPEG_CMYK_COLORSPACE;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000UL) >> 16;
+  pInfo->ImageWidth  = (hjpeg->Instance->CONFR3 & 0xFFFF0000UL) >> 16;
+
+  if ((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))
+  {
+    yblockNb  = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4;
+    cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4;
+    cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4;
+
+    if ((yblockNb == 1UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
+    {
+      pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/
+    }
+    else if ((yblockNb == 0UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
+    {
+      pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
+    }
+    else if ((yblockNb == 3UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL))
+    {
+      pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING;
+    }
+    else /*Default is 4:4:4*/
+    {
+      pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
+    }
+  }
+  else
+  {
+    pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;
+  }
+
+  pInfo->ImageQuality = JPEG_GetQuality(hjpeg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable JPEG Header parsing for decoding
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *               the configuration information for the JPEG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State == HAL_JPEG_STATE_READY)
+  {
+    /* Change the JPEG state */
+    hjpeg->State = HAL_JPEG_STATE_BUSY;
+
+    /* Enable header processing*/
+    hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    /* Change the JPEG state */
+    hjpeg->State = HAL_JPEG_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable JPEG Header parsing for decoding
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *               the configuration information for the JPEG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State == HAL_JPEG_STATE_READY)
+  {
+    /* Change the JPEG state */
+    hjpeg->State = HAL_JPEG_STATE_BUSY;
+
+    /* Disable header processing*/
+    hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    /* Change the JPEG state */
+    hjpeg->State = HAL_JPEG_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Modify the default Quantization tables used for JPEG encoding.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  QTable0  pointer to uint8_t , define the user quantification table for color component 1.
+  *                  If NULL assume no need to update  the table and no error return
+  * @param  QTable1  pointer to uint8_t , define the user quantification table for color component 2.
+  *                  If NULL assume no need to update  the table and no error return.
+  * @param  QTable2  pointer to uint8_t , define the user quantification table for color component 3,
+  *                  If NULL assume no need to update  the table and no error return.
+  * @param  QTable3  pointer to uint8_t , define the user quantification table for color component 4.
+  *                  If NULL assume no need to update  the table and no error return.
+  *
+  * @retval HAL status
+  */
+
+
+HAL_StatusTypeDef  HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,
+                                               uint8_t *QTable2, uint8_t *QTable3)
+{
+  /* Process Locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State == HAL_JPEG_STATE_READY)
+  {
+    /* Change the DMA state */
+    hjpeg->State = HAL_JPEG_STATE_BUSY;
+
+    hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES;
+
+    hjpeg->QuantTable0 = QTable0;
+    hjpeg->QuantTable1 = QTable1;
+    hjpeg->QuantTable2 = QTable2;
+    hjpeg->QuantTable3 = QTable3;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    /* Change the DMA state */
+    hjpeg->State = HAL_JPEG_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions
+  *  @brief   processing functions.
+  *
+@verbatim
+  ==============================================================================
+                      ##### JPEG processing functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_JPEG_Encode()     : JPEG encoding with polling process
+      (+) HAL_JPEG_Decode()     : JPEG decoding with polling process
+      (+) HAL_JPEG_Encode_IT()  : JPEG encoding with interrupt process
+      (+) HAL_JPEG_Decode_IT()  : JPEG decoding with interrupt process
+      (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process
+      (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process
+      (+) HAL_JPEG_Pause()      :   Pause the Input/Output processing
+      (+) HAL_JPEG_Resume()     :  Resume the JPEG Input/Output processing
+      (+) HAL_JPEG_ConfigInputBuffer()  : Config Encoding/Decoding Input Buffer
+      (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer
+      (+) HAL_JPEG_Abort()              : Aborts the JPEG Encoding/Decoding
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts JPEG encoding with polling processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pDataInMCU Pointer to the Input buffer
+  * @param  InDataLength size in bytes Input buffer
+  * @param  pDataOut Pointer to the jpeg output data buffer
+  * @param  OutDataLength size in bytes of the Output buffer
+  * @param  Timeout Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+                                   uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param((InDataLength >= 4UL));
+  assert_param((OutDataLength >= 4UL));
+
+  /* Check In/out buffer allocation and size */
+  if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State != HAL_JPEG_STATE_READY)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+
+  if (hjpeg->State == HAL_JPEG_STATE_READY)
+  {
+    if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
+    {
+      /*Change JPEG state*/
+      hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
+
+      /*Set the Context to Encode with Polling*/
+      hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
+      hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING);
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /*Store In/out buffers pointers and size*/
+      hjpeg->pJpegInBuffPtr = pDataInMCU;
+      hjpeg->pJpegOutBuffPtr = pDataOut;
+      hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /* In Data length must be multiple
+                                                                       of 4 Bytes (1 word)*/
+      hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /* Out Data length must be multiple
+                                                                       of 4 Bytes (1 word)*/
+
+      /*Reset In/out data counter */
+      hjpeg->JpegInCount = 0;
+      hjpeg->JpegOutCount = 0;
+
+      /*Init decoding process*/
+      JPEG_Init_Process(hjpeg);
+
+      /*JPEG data processing : In/Out FIFO transfer*/
+      while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+          {
+
+            /* Update error code */
+            hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hjpeg);
+
+            /*Change JPEG state*/
+            hjpeg->State = HAL_JPEG_STATE_READY;
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      /*Change JPEG state*/
+      hjpeg->State = HAL_JPEG_STATE_READY;
+
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      return HAL_ERROR;
+    }
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts JPEG decoding with polling processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pDataIn Pointer to the input data buffer
+  * @param  InDataLength size in bytes Input buffer
+  * @param  pDataOutMCU Pointer to the Output data buffer
+  * @param  OutDataLength size in bytes of the Output buffer
+  * @param  Timeout Specify Timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+                                   uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param((InDataLength >= 4UL));
+  assert_param((OutDataLength >= 4UL));
+
+  /* Check In/out buffer allocation and size */
+  if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hjpeg);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  if (hjpeg->State == HAL_JPEG_STATE_READY)
+  {
+    /*Change JPEG state*/
+    hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
+
+    /*Set the Context to Decode with Polling*/
+    /*Set the Context to Encode with Polling*/
+    hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
+    hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING);
+
+    /*Store In/out buffers pointers and size*/
+    hjpeg->pJpegInBuffPtr = pDataIn;
+    hjpeg->pJpegOutBuffPtr = pDataOutMCU;
+    hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /*In Data length must be multiple
+                                                                    of 4 Bytes (1 word)*/
+    hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple
+                                                                    of 4 Bytes (1 word)*/
+
+    /*Reset In/out data counter */
+    hjpeg->JpegInCount = 0;
+    hjpeg->JpegOutCount = 0;
+
+    /*Init decoding process*/
+    JPEG_Init_Process(hjpeg);
+
+    /*JPEG data processing : In/Out FIFO transfer*/
+    while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))
+    {
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+        {
+
+          /* Update error code */
+          hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hjpeg);
+
+          /*Change JPEG state*/
+          hjpeg->State = HAL_JPEG_STATE_READY;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    /*Change JPEG state*/
+    hjpeg->State = HAL_JPEG_STATE_READY;
+
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts JPEG encoding with interrupt processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pDataInMCU Pointer to the Input buffer
+  * @param  InDataLength size in bytes Input buffer
+  * @param  pDataOut Pointer to the jpeg output data buffer
+  * @param  OutDataLength size in bytes of the Output buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+                                      uint8_t *pDataOut, uint32_t OutDataLength)
+{
+  /* Check the parameters */
+  assert_param((InDataLength >= 4UL));
+  assert_param((OutDataLength >= 4UL));
+
+  /* Check In/out buffer allocation and size */
+  if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State != HAL_JPEG_STATE_READY)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+  else
+  {
+    if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
+    {
+      /*Change JPEG state*/
+      hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
+
+      /*Set the Context to Encode with IT*/
+      hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
+      hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT);
+
+      /*Store In/out buffers pointers and size*/
+      hjpeg->pJpegInBuffPtr = pDataInMCU;
+      hjpeg->pJpegOutBuffPtr = pDataOut;
+      hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /*In Data length must be multiple
+                                                                      of 4 Bytes (1 word)*/
+      hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple
+                                                                      of 4 Bytes (1 word)*/
+
+      /*Reset In/out data counter */
+      hjpeg->JpegInCount = 0;
+      hjpeg->JpegOutCount = 0;
+
+      /*Init decoding process*/
+      JPEG_Init_Process(hjpeg);
+
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      return HAL_ERROR;
+    }
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts JPEG decoding with interrupt processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pDataIn Pointer to the input data buffer
+  * @param  InDataLength size in bytes Input buffer
+  * @param  pDataOutMCU Pointer to the Output data buffer
+  * @param  OutDataLength size in bytes of the Output buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+                                      uint8_t *pDataOutMCU, uint32_t OutDataLength)
+{
+  /* Check the parameters */
+  assert_param((InDataLength >= 4UL));
+  assert_param((OutDataLength >= 4UL));
+
+  /* Check In/out buffer allocation and size */
+  if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State == HAL_JPEG_STATE_READY)
+  {
+    /*Change JPEG state*/
+    hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
+
+    /*Set the Context to Decode with IT*/
+    hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
+    hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT);
+
+    /*Store In/out buffers pointers and size*/
+    hjpeg->pJpegInBuffPtr = pDataIn;
+    hjpeg->pJpegOutBuffPtr = pDataOutMCU;
+    hjpeg->InDataLength = InDataLength - (InDataLength % 4UL);    /*In Data length must be multiple
+                                                                    of 4 Bytes (1 word)*/
+    hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple
+                                                                    of 4 Bytes (1 word)*/
+
+    /*Reset In/out data counter */
+    hjpeg->JpegInCount = 0;
+    hjpeg->JpegOutCount = 0;
+
+    /*Init decoding process*/
+    JPEG_Init_Process(hjpeg);
+
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts JPEG encoding with DMA processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pDataInMCU Pointer to the Input buffer
+  * @param  InDataLength size in bytes Input buffer
+  * @param  pDataOut Pointer to the jpeg output data buffer
+  * @param  OutDataLength size in bytes of the Output buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,
+                                       uint8_t *pDataOut, uint32_t OutDataLength)
+{
+  /* Check the parameters */
+  assert_param((InDataLength >= 4UL));
+  assert_param((OutDataLength >= 4UL));
+
+  /* Check In/out buffer allocation and size */
+  if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State != HAL_JPEG_STATE_READY)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+  else
+  {
+    if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING)
+    {
+      /*Change JPEG state*/
+      hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;
+
+      /*Set the Context to Encode with DMA*/
+      hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
+      hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA);
+
+      /*Store In/out buffers pointers and size*/
+      hjpeg->pJpegInBuffPtr = pDataInMCU;
+      hjpeg->pJpegOutBuffPtr = pDataOut;
+      hjpeg->InDataLength = InDataLength;
+      hjpeg->OutDataLength = OutDataLength;
+
+      /*Reset In/out data counter */
+      hjpeg->JpegInCount = 0;
+      hjpeg->JpegOutCount = 0;
+
+      /*Init decoding process*/
+      JPEG_Init_Process(hjpeg);
+
+      /* JPEG encoding process using DMA */
+      if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK)
+      {
+        /* Update State */
+        hjpeg->State = HAL_JPEG_STATE_ERROR;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hjpeg);
+
+        return HAL_ERROR;
+      }
+
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      return HAL_ERROR;
+    }
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts JPEG decoding with DMA processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pDataIn Pointer to the input data buffer
+  * @param  InDataLength size in bytes Input buffer
+  * @param  pDataOutMCU Pointer to the Output data buffer
+  * @param  OutDataLength size in bytes of the Output buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,
+                                       uint8_t *pDataOutMCU, uint32_t OutDataLength)
+{
+  /* Check the parameters */
+  assert_param((InDataLength >= 4UL));
+  assert_param((OutDataLength >= 4UL));
+
+  /* Check In/out buffer allocation and size */
+  if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hjpeg);
+
+  if (hjpeg->State == HAL_JPEG_STATE_READY)
+  {
+    /*Change JPEG state*/
+    hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;
+
+    /*Set the Context to Decode with DMA*/
+    hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);
+    hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA);
+
+    /*Store In/out buffers pointers and size*/
+    hjpeg->pJpegInBuffPtr = pDataIn;
+    hjpeg->pJpegOutBuffPtr = pDataOutMCU;
+    hjpeg->InDataLength = InDataLength;
+    hjpeg->OutDataLength = OutDataLength;
+
+    /*Reset In/out data counter */
+    hjpeg->JpegInCount = 0;
+    hjpeg->JpegOutCount = 0;
+
+    /*Init decoding process*/
+    JPEG_Init_Process(hjpeg);
+
+    /* JPEG decoding process using DMA */
+    if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK)
+    {
+      /* Update State */
+      hjpeg->State = HAL_JPEG_STATE_ERROR;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    return HAL_BUSY;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Pause the JPEG Input/Output processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  XferSelection This parameter can be one of the following values :
+  *                           JPEG_PAUSE_RESUME_INPUT : Pause Input processing
+  *                           JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing
+  *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
+{
+  uint32_t mask = 0;
+
+  assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
+
+  if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+  {
+    if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+    {
+      hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
+      mask |= JPEG_DMA_IDMA;
+    }
+    if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+    {
+      hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
+      mask |= JPEG_DMA_ODMA;
+    }
+    JPEG_DISABLE_DMA(hjpeg, mask);
+
+  }
+  else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+  {
+
+    if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+    {
+      hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;
+      mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
+    }
+    if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+    {
+      hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;
+      mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
+    }
+    __HAL_JPEG_DISABLE_IT(hjpeg, mask);
+
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Resume the JPEG Input/Output processing
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  XferSelection This parameter can be one of the following values :
+  *                           JPEG_PAUSE_RESUME_INPUT : Resume Input processing
+  *                           JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing
+  *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)
+{
+  uint32_t mask = 0;
+
+  assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
+
+  if ((hjpeg->Context & (JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)) == 0UL)
+  {
+    /* if nothing paused to resume return error*/
+    return HAL_ERROR;
+  }
+
+  if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+  {
+
+    if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+    {
+      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
+      mask |= JPEG_DMA_IDMA;
+
+      /*JPEG Input DMA transfer data number must be multiple of DMA buffer size
+        as the destination is a 32 bits register */
+      hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
+
+      if (hjpeg->InDataLength > 0UL)
+      {
+        /* Start DMA FIFO In transfer */
+        if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
+                             hjpeg->InDataLength) != HAL_OK)
+        {
+          hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+          hjpeg->State = HAL_JPEG_STATE_ERROR;
+          return HAL_ERROR;
+        }
+      }
+    }
+    if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+    {
+      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
+
+      if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL)
+      {
+        JPEG_DMA_PollResidualData(hjpeg);
+      }
+      else
+      {
+        mask |= JPEG_DMA_ODMA;
+
+        /* Start DMA FIFO Out transfer */
+        if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
+                             hjpeg->OutDataLength) != HAL_OK)
+        {
+          hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+          hjpeg->State = HAL_JPEG_STATE_ERROR;
+          return HAL_ERROR;
+        }
+      }
+
+    }
+    JPEG_ENABLE_DMA(hjpeg, mask);
+
+  }
+  else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+  {
+    if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)
+    {
+      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);
+      mask |= (JPEG_IT_IFT | JPEG_IT_IFNF);
+    }
+    if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
+    {
+      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
+      mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC);
+    }
+    __HAL_JPEG_ENABLE_IT(hjpeg, mask);
+
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Config Encoding/Decoding Input Buffer.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module.
+  * @param  pNewInputBuffer Pointer to the new input data buffer
+  * @param  InDataLength Size in bytes of the new Input data buffer
+  * @retval HAL status
+  */
+void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)
+{
+  hjpeg->pJpegInBuffPtr =  pNewInputBuffer;
+  hjpeg->InDataLength = InDataLength;
+}
+
+/**
+  * @brief  Config Encoding/Decoding Output Buffer.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module.
+  * @param  pNewOutputBuffer Pointer to the new output data buffer
+  * @param  OutDataLength Size in bytes of the new Output data buffer
+  * @retval HAL status
+  */
+void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)
+{
+  hjpeg->pJpegOutBuffPtr = pNewOutputBuffer;
+  hjpeg->OutDataLength = OutDataLength;
+}
+
+/**
+  * @brief  Aborts the JPEG Encoding/Decoding.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t tickstart;
+  uint32_t tmpContext;
+  tmpContext = hjpeg->Context;
+
+  /*Reset the Context operation and method*/
+  hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA);
+
+  if ((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+  {
+    /* Stop the DMA In/out Xfer*/
+    if (HAL_DMA_Abort(hjpeg->hdmaout) != HAL_OK)
+    {
+      if (hjpeg->hdmaout->ErrorCode == HAL_DMA_ERROR_TIMEOUT)
+      {
+        hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+      }
+    }
+    if (HAL_DMA_Abort(hjpeg->hdmain) != HAL_OK)
+    {
+      if (hjpeg->hdmain->ErrorCode == HAL_DMA_ERROR_TIMEOUT)
+      {
+        hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+      }
+    }
+
+  }
+
+  /* Stop the JPEG encoding/decoding process*/
+  hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the JPEG Codec is effectively disabled */
+  while (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != 0UL)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > JPEG_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;
+
+      /* Change the DMA state */
+      hjpeg->State = HAL_JPEG_STATE_ERROR;
+      break;
+    }
+  }
+
+  /* Disable All Interrupts */
+  __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+
+  /* Disable All DMA requests */
+  JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
+
+  /* Flush input and output FIFOs*/
+  hjpeg->Instance->CR |= JPEG_CR_IFF;
+  hjpeg->Instance->CR |= JPEG_CR_OFF;
+
+  /* Clear all flags */
+  __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
+
+  /* Reset JpegInCount and JpegOutCount */
+  hjpeg->JpegInCount = 0;
+  hjpeg->JpegOutCount = 0;
+
+  /*Reset the Context Pause*/
+  hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT);
+
+  /* Change the DMA state*/
+  if (hjpeg->ErrorCode != HAL_JPEG_ERROR_NONE)
+  {
+    hjpeg->State = HAL_JPEG_STATE_ERROR;
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+    /* Return function status */
+    return HAL_ERROR;
+  }
+  else
+  {
+    hjpeg->State = HAL_JPEG_STATE_READY;
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+    /* Return function status */
+    return HAL_OK;
+  }
+
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions
+  *  @brief   JPEG process callback functions.
+  *
+@verbatim
+  ==============================================================================
+              #####  JPEG Decode and Encode callback functions  #####
+  ==============================================================================
+    [..]  This section provides callback functions:
+      (+) HAL_JPEG_InfoReadyCallback()  : Decoding JPEG Info ready callback
+      (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.
+      (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.
+      (+) HAL_JPEG_ErrorCallback()      : JPEG error callback.
+      (+) HAL_JPEG_GetDataCallback()    : Get New Data chunk callback.
+      (+) HAL_JPEG_DataReadyCallback()  : Decoded/Encoded Data ready  callback.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Decoding JPEG Info ready callback.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pInfo pointer to a JPEG_ConfTypeDef structure that contains
+  *         The JPEG decoded header information
+  * @retval None
+  */
+__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+  UNUSED(pInfo);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Encoding complete callback.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Decoding complete callback.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_EncodeCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  JPEG error callback.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+__weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Get New Data chunk callback.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  NbDecodedData Number of consumed data in the previous chunk in bytes
+  * @retval None
+  */
+__weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+  UNUSED(NbDecodedData);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_GetDataCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Decoded/Encoded Data ready  callback.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  pDataOut pointer to the output data buffer
+  * @param  OutDataLength number in bytes of data available in the specified output buffer
+  * @retval None
+  */
+__weak void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hjpeg);
+  UNUSED(pDataOut);
+  UNUSED(OutDataLength);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_JPEG_DataReadyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management
+  *  @brief   JPEG IRQ handler.
+  *
+@verbatim
+  ==============================================================================
+                ##### JPEG IRQ handler management #####
+  ==============================================================================
+    [..]  This section provides JPEG IRQ handler function.
+      (+) HAL_JPEG_IRQHandler()  : handles JPEG interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles JPEG interrupt request.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)
+{
+  switch (hjpeg->State)
+  {
+    case HAL_JPEG_STATE_BUSY_ENCODING:
+    case HAL_JPEG_STATE_BUSY_DECODING:
+      /* continue JPEG data encoding/Decoding*/
+      /* JPEG data processing : In/Out FIFO transfer*/
+      if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+      {
+        (void) JPEG_Process(hjpeg);
+      }
+      else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+      {
+        JPEG_DMA_ContinueProcess(hjpeg);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions
+  *  @brief   Peripheral State functions.
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]  This section provides JPEG State and Errors function.
+      (+) HAL_JPEG_GetState()  : permits to get in run-time the JPEG state.
+      (+) HAL_JPEG_GetError()  : Returns the JPEG error code if any.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the JPEG state.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval JPEG state
+  */
+HAL_JPEG_STATETypeDef HAL_JPEG_GetState(const JPEG_HandleTypeDef *hjpeg)
+{
+  return hjpeg->State;
+}
+
+/**
+  * @brief  Return the JPEG error code
+  * @param  hjpeg  pointer to a JPEG_HandleTypeDef structure that contains
+  *              the configuration information for the specified JPEG.
+  * @retval JPEG Error Code
+  */
+uint32_t HAL_JPEG_GetError(const JPEG_HandleTypeDef *hjpeg)
+{
+  return hjpeg->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup JPEG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Generates Huffman sizes/Codes Table from Bits/vals Table
+  * @param  Bits pointer to bits table
+  * @param  Huffsize pointer to sizes table
+  * @param  Huffcode pointer to codes table
+  * @param  LastK pointer to last Coeff (table dimension)
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(const uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode,
+                                                uint32_t *LastK)
+{
+  uint32_t i;
+  uint32_t j;
+  uint32_t k;
+  uint32_t code;
+  uint32_t si;
+
+  /* Figure C.1: Generation of table of Huffman code sizes */
+  j = 0;
+  for (k = 0; k < 16UL; k++)
+  {
+    i = (uint32_t)Bits[k];
+    if ((j + i) > 256UL)
+    {
+      /* check for table overflow */
+      return HAL_ERROR;
+    }
+    while (i != 0UL)
+    {
+      Huffsize[j] = (uint8_t) k + 1U;
+      j++;
+      i--;
+    }
+  }
+  Huffsize[j] = 0;
+  *LastK = j;
+
+  /* Figure C.2: Generation of table of Huffman codes */
+  code = 0;
+  si = Huffsize[0];
+  j = 0;
+  while (Huffsize[j] != 0U)
+  {
+    while (((uint32_t) Huffsize[j]) == si)
+    {
+      Huffcode[j] = code;
+      j++;
+      code++;
+    }
+    /* code must fit in "size" bits (si), no code is allowed to be all ones*/
+    if (si > 31UL)
+    {
+      return HAL_ERROR;
+    }
+    if (((uint32_t) code) >= (((uint32_t) 1) << si))
+    {
+      return HAL_ERROR;
+    }
+    code <<= 1;
+    si++;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table
+  *         that can programmed to the JPEG encoder registers
+  * @param  AC_BitsValsTable pointer to AC huffman bits/vals table
+  * @param  AC_SizeCodesTable pointer to AC huffman Sizes/Codes table
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable,
+                                                           JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)
+{
+  HAL_StatusTypeDef error;
+  uint8_t huffsize[257];
+  uint32_t huffcode[257];
+  uint32_t k;
+  uint32_t i;
+  uint32_t lsb;
+  uint32_t msb;
+  uint32_t lastK;
+
+  error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
+  if (error != HAL_OK)
+  {
+    return  error;
+  }
+
+  /* Figure C.3: Ordering procedure for encoding procedure code tables */
+  k = 0;
+
+  while (k < lastK)
+  {
+    i = AC_BitsValsTable->HuffVal[k];
+    if (i == 0UL)
+    {
+      i = JPEG_AC_HUFF_TABLE_SIZE - 2UL; /*i = 0x00 EOB code*/
+    }
+    else if (i == 0xF0UL) /* i = 0xF0 ZRL code*/
+    {
+      i = JPEG_AC_HUFF_TABLE_SIZE - 1UL;
+    }
+    else
+    {
+      msb = (i & 0xF0UL) >> 4;
+      lsb = (i & 0x0FUL);
+      i = (msb * 10UL) + lsb - 1UL;
+    }
+    if (i >= JPEG_AC_HUFF_TABLE_SIZE)
+    {
+      return HAL_ERROR; /* Huffman Table overflow error*/
+    }
+    else
+    {
+      AC_SizeCodesTable->HuffmanCode[i] = huffcode[k];
+      AC_SizeCodesTable->CodeLength[i] = huffsize[k] - 1U;
+      k++;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table
+  *         that can programmed to the JPEG encoder registers
+  * @param  DC_BitsValsTable pointer to DC huffman bits/vals table
+  * @param  DC_SizeCodesTable pointer to DC huffman Sizes/Codes table
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable,
+                                                           JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)
+{
+  HAL_StatusTypeDef error;
+
+  uint32_t k;
+  uint32_t i;
+  uint32_t lastK;
+  uint8_t huffsize[257];
+  uint32_t huffcode[257];
+  error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK);
+  if (error != HAL_OK)
+  {
+    return  error;
+  }
+  /* Figure C.3: ordering procedure for encoding procedure code tables */
+  k = 0;
+
+  while (k < lastK)
+  {
+    i = DC_BitsValsTable->HuffVal[k];
+    if (i >= JPEG_DC_HUFF_TABLE_SIZE)
+    {
+      return HAL_ERROR; /* Huffman Table overflow error*/
+    }
+    else
+    {
+      DC_SizeCodesTable->HuffmanCode[i] = huffcode[k];
+      DC_SizeCodesTable->CodeLength[i] = huffsize[k] - 1U;
+      k++;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the JPEG register with an DC huffman table at the given DC table address
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  HuffTableDC pointer to DC huffman table
+  * @param  DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC,
+                                             const __IO uint32_t *DCTableAddress)
+{
+  HAL_StatusTypeDef error;
+  JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
+  uint32_t i;
+  uint32_t lsb;
+  uint32_t msb;
+  __IO uint32_t *address;
+  __IO uint32_t *addressDef;
+
+  if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
+  {
+    address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL));
+  }
+  else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1))
+  {
+    address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  if (HuffTableDC != NULL)
+  {
+    error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable);
+    if (error != HAL_OK)
+    {
+      return  error;
+    }
+    addressDef = address;
+    *addressDef = 0x0FFF0FFF;
+    addressDef++;
+    *addressDef = 0x0FFF0FFF;
+
+    i = JPEG_DC_HUFF_TABLE_SIZE;
+    while (i > 1UL)
+    {
+      i--;
+      address --;
+      msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) |
+            ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFFUL);
+      i--;
+      lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) |
+            ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFFUL);
+
+      *address = lsb | (msb << 16);
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the JPEG register with an AC huffman table at the given AC table address
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  HuffTableAC pointer to AC huffman table
+  * @param  ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(const JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC,
+                                             const __IO uint32_t *ACTableAddress)
+{
+  HAL_StatusTypeDef error;
+  JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable;
+  uint32_t i;
+  uint32_t lsb;
+  uint32_t msb;
+  __IO uint32_t *address;
+  __IO uint32_t *addressDef;
+
+  if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC0))
+  {
+    address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL));
+  }
+  else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1))
+  {
+    address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  if (HuffTableAC != NULL)
+  {
+    error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable);
+    if (error != HAL_OK)
+    {
+      return  error;
+    }
+    /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */
+    /* Locations 162:175 of each AC table contain information used internally by the core */
+
+    addressDef = address;
+    for (i = 0; i < 3UL; i++)
+    {
+      *addressDef = 0x0FFF0FFF;
+      addressDef++;
+    }
+    *addressDef = 0x0FD10FD0;
+    addressDef++;
+    *addressDef = 0x0FD30FD2;
+    addressDef++;
+    *addressDef = 0x0FD50FD4;
+    addressDef++;
+    *addressDef = 0x0FD70FD6;
+    /* end of Locations 162:175  */
+
+
+    i = JPEG_AC_HUFF_TABLE_SIZE;
+    while (i > 1UL)
+    {
+      i--;
+      address--;
+      msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) |
+            ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFFUL);
+      i--;
+      lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) |
+            ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFFUL);
+
+      *address = lsb | (msb << 16);
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the JPEG encoder register huffman tables to used during
+  *         the encdoing operation
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg)
+{
+  HAL_StatusTypeDef error;
+
+  JPEG_Set_Huff_DHTMem(hjpeg);
+  error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable,
+                              (hjpeg->Instance->HUFFENC_AC0));
+  if (error != HAL_OK)
+  {
+    return  error;
+  }
+
+  error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable,
+                              (hjpeg->Instance->HUFFENC_AC1));
+  if (error != HAL_OK)
+  {
+    return  error;
+  }
+
+  error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable,
+                              hjpeg->Instance->HUFFENC_DC0);
+  if (error != HAL_OK)
+  {
+    return  error;
+  }
+
+  error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable,
+                              hjpeg->Instance->HUFFENC_DC1);
+  if (error != HAL_OK)
+  {
+    return  error;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the JPEG register huffman tables to be included in the JPEG
+  *         file header (used for encoding only)
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+static void JPEG_Set_Huff_DHTMem(const JPEG_HandleTypeDef *hjpeg)
+{
+  const JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable;
+  const JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable;
+  const JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable;
+  const JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable;
+  uint32_t value;
+  uint32_t index;
+  __IO uint32_t *address;
+
+  /* DC0 Huffman Table : BITS*/
+  /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/
+  address = (hjpeg->Instance->DHTMEM + 3);
+  index = 16;
+  while (index > 3UL)
+  {
+
+    *address = (((uint32_t)HuffTableDC0->Bits[index - 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableDC0->Bits[index - 2UL] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableDC0->Bits[index - 3UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableDC0->Bits[index - 4UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+
+  }
+  /* DC0 Huffman Table : Val*/
+  /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */
+  address = (hjpeg->Instance->DHTMEM + 6);
+  index = 12;
+  while (index > 3UL)
+  {
+    *address = (((uint32_t)HuffTableDC0->HuffVal[index - 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableDC0->HuffVal[index - 2UL] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableDC0->HuffVal[index - 3UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableDC0->HuffVal[index - 4UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+  }
+
+  /* AC0 Huffman Table : BITS*/
+  /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/
+  address = (hjpeg->Instance->DHTMEM + 10UL);
+  index = 16;
+  while (index > 3UL)
+  {
+
+    *address = (((uint32_t)HuffTableAC0->Bits[index - 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableAC0->Bits[index - 2UL] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableAC0->Bits[index - 3UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableAC0->Bits[index - 4UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+
+  }
+  /* AC0 Huffman Table : Val*/
+  /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */
+  /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */
+  address = (hjpeg->Instance->DHTMEM + 51);
+  value = *address & 0xFFFF0000U;
+  value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFFUL) << 8) |
+          ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFFUL);
+  *address = value;
+
+  /*continue setting 160 AC0 huffman values */
+  address--; /* address = hjpeg->Instance->DHTMEM + 50*/
+  index = JPEG_AC_HUFF_TABLE_SIZE - 2UL;
+  while (index > 3UL)
+  {
+    *address = (((uint32_t)HuffTableAC0->HuffVal[index - 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableAC0->HuffVal[index - 2UL] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableAC0->HuffVal[index - 3UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableAC0->HuffVal[index - 4UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+  }
+
+  /* DC1 Huffman Table : BITS*/
+  /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/
+  /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */
+  address = (hjpeg->Instance->DHTMEM + 51);
+  value = *address & 0x0000FFFFU;
+  value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFFUL) << 24) |
+          (((uint32_t)HuffTableDC1->Bits[0] & 0xFFUL) << 16);
+  *address = value;
+
+  /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */
+  address = (hjpeg->Instance->DHTMEM + 55);
+  value = *address & 0xFFFF0000U;
+  value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFFUL) << 8) |
+          ((uint32_t)HuffTableDC1->Bits[14] & 0xFFUL);
+  *address = value;
+
+  /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/
+  address--;
+  index = 12;
+  while (index > 3UL)
+  {
+
+    *address = (((uint32_t)HuffTableDC1->Bits[index + 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableDC1->Bits[index] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableDC1->Bits[index - 1UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableDC1->Bits[index - 2UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+
+  }
+  /* DC1 Huffman Table : Val*/
+  /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */
+  /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */
+  address = (hjpeg->Instance->DHTMEM + 55);
+  value = *address & 0x0000FFFFUL;
+  value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFFUL) << 24) |
+          (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFFUL) << 16);
+  *address = value;
+
+  /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */
+  address = (hjpeg->Instance->DHTMEM + 58);
+  value = *address & 0xFFFF0000UL;
+  value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFFUL) << 8) |
+          ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFFUL);
+  *address = value;
+
+  /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/
+  address--;
+  index = 8;
+  while (index > 3UL)
+  {
+    *address = (((uint32_t)HuffTableDC1->HuffVal[index + 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableDC1->HuffVal[index - 1UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableDC1->HuffVal[index - 2UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+  }
+
+  /* AC1 Huffman Table : BITS*/
+  /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/
+  /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */
+  address = (hjpeg->Instance->DHTMEM + 58);
+  value = *address & 0x0000FFFFU;
+  value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFFUL) << 24) |
+          (((uint32_t)HuffTableAC1->Bits[0] & 0xFFUL) << 16);
+  *address = value;
+
+  /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */
+  address = (hjpeg->Instance->DHTMEM + 62);
+  value = *address & 0xFFFF0000U;
+  value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFFUL);
+  *address = value;
+
+  /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/
+  address--;
+  index = 12;
+  while (index > 3UL)
+  {
+
+    *address = (((uint32_t)HuffTableAC1->Bits[index + 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableAC1->Bits[index] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableAC1->Bits[index - 1UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableAC1->Bits[index - 2UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+
+  }
+  /* AC1 Huffman Table : Val*/
+  /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */
+  /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */
+  address = (hjpeg->Instance->DHTMEM + 62);
+  value = *address & 0x0000FFFFUL;
+  value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFFUL) << 24) |
+          (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFFUL) << 16);
+  *address = value;
+
+  /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */
+  address = (hjpeg->Instance->DHTMEM + 102);
+  index = JPEG_AC_HUFF_TABLE_SIZE - 2UL;
+  while (index > 3UL)
+  {
+    *address = (((uint32_t)HuffTableAC1->HuffVal[index + 1UL] & 0xFFUL) << 24) |
+               (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFFUL) << 16) |
+               (((uint32_t)HuffTableAC1->HuffVal[index - 1UL] & 0xFFUL) << 8) |
+               ((uint32_t)HuffTableAC1->HuffVal[index - 2UL] & 0xFFUL);
+    address--;
+    index -= 4UL;
+  }
+
+}
+
+/**
+  * @brief  Configure the JPEG registers with a given quantization table
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  QTable pointer to an array of 64 bytes giving the quantization table
+  * @param  QTableAddress destination quantization address in the JPEG peripheral
+  *         it could be QMEM0, QMEM1, QMEM2 or QMEM3
+  * @retval 0 if no error, 1 if error
+  */
+static uint32_t JPEG_Set_Quantization_Mem(const JPEG_HandleTypeDef *hjpeg, const uint8_t *QTable,
+                                          __IO uint32_t *QTableAddress)
+{
+  uint32_t i;
+  uint32_t j;
+  uint32_t quantRow;
+  uint32_t quantVal;
+  uint32_t ScaleFactor;
+  __IO uint32_t *tableAddress;
+
+  tableAddress = QTableAddress;
+
+  if ((hjpeg->Conf.ImageQuality >= 50UL) && (hjpeg->Conf.ImageQuality <= 100UL))
+  {
+    ScaleFactor = JPEG_HIGH_QUALITY_REFERENCE - (hjpeg->Conf.ImageQuality * 2UL);
+  }
+  else if (hjpeg->Conf.ImageQuality > 0UL)
+  {
+    ScaleFactor = JPEG_LOW_QUALITY_REFERENCE / ((uint32_t) hjpeg->Conf.ImageQuality);
+  }
+  else
+  {
+    return 1UL;
+  }
+
+  /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/
+  i = 0;
+  while (i < (JPEG_QUANT_TABLE_SIZE - 3UL))
+  {
+    quantRow = 0;
+    for (j = 0; j < 4UL; j++)
+    {
+      /* Note that the quantization coefficients must be specified in the table in zigzag order */
+      quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i + j]]) * ScaleFactor) + 50UL) / 100UL;
+
+      if (quantVal == 0UL)
+      {
+        quantVal = 1UL;
+      }
+      else if (quantVal > 255UL)
+      {
+        quantVal = JPEG_QUANTVAL_MAX;
+      }
+      else
+      {
+        /* Nothing to do, keep same value of quantVal */
+      }
+
+      quantRow |= ((quantVal & 0xFFUL) << (8UL * j));
+    }
+
+    i += 4UL;
+    *tableAddress = quantRow;
+    tableAddress ++;
+  }
+
+  /* Return function status */
+  return 0UL;
+}
+
+/**
+  * @brief  Configure the JPEG registers for YCbCr color space
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t ySamplingH;
+  uint32_t ySamplingV;
+  uint32_t yblockNb;
+
+  /*Set Number of color components to 3*/
+  hjpeg->Instance->CONFR1 &=  ~JPEG_CONFR1_NF;
+  hjpeg->Instance->CONFR1 |=  JPEG_CONFR1_NF_1;
+
+  /* compute MCU block size and Y, Cb ,Cr sampling factors*/
+  if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
+  {
+    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
+    ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/
+
+    yblockNb  = 0x30; /* 4 blocks of 8x8*/
+  }
+  else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
+  {
+    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
+    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
+
+    yblockNb  = 0x10; /* 2 blocks of 8x8*/
+  }
+  else /*JPEG_444_SUBSAMPLING and default*/
+  {
+    ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/
+    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
+
+    yblockNb  = 0; /* 1 block of 8x8*/
+  }
+
+  hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
+  hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);
+
+  /*Reset CONFR4 register*/
+  hjpeg->Instance->CONFR4 =  0;
+  /*Set Horizental and Vertical  sampling factor , number of blocks,
+   Quantization table and Huffman AC/DC tables for component 0*/
+  hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB));
+
+  /*Reset CONFR5 register*/
+  hjpeg->Instance->CONFR5 =  0;
+  /*Set Horizental and Vertical  sampling factor , number of blocks,
+    Quantization table and Huffman AC/DC tables for component 1*/
+  hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA |
+                              JPEG_CONFR5_HD);
+
+  /*Reset CONFR6 register*/
+  hjpeg->Instance->CONFR6 =  0;
+  /*Set Horizental and Vertical  sampling factor and number of blocks for component 2*/
+  /* In YCBCR , by default, both chrominance components (component 1 and component 2)
+     use the same Quantization table (table 1) */
+  /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */
+  hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA |
+                              JPEG_CONFR6_HD);
+
+}
+
+/**
+  * @brief  Configure the JPEG registers for GrayScale color space
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg)
+{
+  /*Set Number of color components to 1*/
+  hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);
+
+  /*in GrayScale use 1 single Quantization table (Table 0)*/
+  /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/
+
+  /*Reset CONFR4 register*/
+  hjpeg->Instance->CONFR4 =  0;
+  /*Set Horizental and Vertical  sampling factor , number of blocks,
+    Quantization table and Huffman AC/DC tables for component 0*/
+  hjpeg->Instance->CONFR4 |=  JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ;
+}
+
+/**
+  * @brief  Configure the JPEG registers for CMYK color space
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t ySamplingH;
+  uint32_t ySamplingV;
+  uint32_t yblockNb;
+
+  /*Set Number of color components to 4*/
+  hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS);
+
+  /* compute MCU block size and Y, Cb ,Cr sampling factors*/
+  if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)
+  {
+    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
+    ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/
+
+    yblockNb  = 0x30; /* 4 blocks of 8x8*/
+  }
+  else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)
+  {
+    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/
+    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
+
+    yblockNb  = 0x10; /* 2 blocks of 8x8*/
+  }
+  else /*JPEG_444_SUBSAMPLING and default*/
+  {
+    ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/
+    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/
+
+    yblockNb  = 0; /* 1 block of 8x8*/
+  }
+
+  /*Reset CONFR4 register*/
+  hjpeg->Instance->CONFR4 =  0;
+  /*Set Horizental and Vertical  sampling factor , number of blocks,
+    Quantization table and Huffman AC/DC tables for component 0*/
+  hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB));
+
+  /*Reset CONFR5 register*/
+  hjpeg->Instance->CONFR5 =  0;
+  /*Set Horizental and Vertical  sampling factor , number of blocks,
+    Quantization table and Huffman AC/DC tables for component 1*/
+  hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);
+
+  /*Reset CONFR6 register*/
+  hjpeg->Instance->CONFR6 =  0;
+  /*Set Horizental and Vertical  sampling factor , number of blocks,
+    Quantization table and Huffman AC/DC tables for component 2*/
+  hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);
+
+  /*Reset CONFR7 register*/
+  hjpeg->Instance->CONFR7 =  0;
+  /*Set Horizental and Vertical  sampling factor , number of blocks,
+    Quantization table and Huffman AC/DC tables for component 3*/
+  hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);
+}
+
+/**
+  * @brief  Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None
+  */
+static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)
+{
+  /*Reset pause*/
+  hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT));
+
+  if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+  {
+    /*Set JPEG Codec to Decoding mode */
+    hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE;
+  }
+  else /* JPEG_CONTEXT_ENCODE */
+  {
+    /*Set JPEG Codec to Encoding mode */
+    hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE;
+  }
+
+  /*Stop JPEG processing */
+  hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+  /* Disable All Interrupts */
+  __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+
+  /* Disable All DMA requests */
+  JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
+  /* Flush input and output FIFOs*/
+  hjpeg->Instance->CR |= JPEG_CR_IFF;
+  hjpeg->Instance->CR |= JPEG_CR_OFF;
+
+  /* Clear all flags */
+  __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
+
+  /*Start Encoding/Decoding*/
+  hjpeg->Instance->CONFR0 |=  JPEG_CONFR0_START;
+
+  if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+  {
+    /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/
+    __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC | JPEG_IT_HPD);
+  }
+  else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
+  {
+    /*Enable End Of Conversation, and End Of Header parsing interruptions*/
+    __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
+
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  JPEG encoding/decoding process in case of Polling or Interrupt
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING
+  */
+static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t tmpContext;
+  uint32_t itflag = hjpeg->Instance->SR;
+
+  /*End of header processing flag */
+  if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+  {
+    if ((itflag & JPEG_FLAG_HPDF) != 0UL)
+    {
+      /*Call Header parsing complete callback */
+      (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
+      /* Reset the ImageQuality */
+      hjpeg->Conf.ImageQuality = 0;
+      /* Note : the image quality is only available at the end of the decoding operation */
+      /* at the current stage the calculated image quality is not correct so reset it */
+
+      /*Call Info Ready callback */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#else
+      HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+      __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD);
+
+      /* Clear header processing done flag */
+      __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF);
+    }
+  }
+
+  /*Input FIFO status handling*/
+  if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0UL)
+  {
+    if ((itflag & JPEG_FLAG_IFTF) != 0UL)
+    {
+      /*Input FIFO threshold flag */
+      /*JPEG_FIFO_TH_SIZE words can be written in */
+      JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE);
+    }
+    else if ((itflag & JPEG_FLAG_IFNFF) != 0UL)
+    {
+      /*Input FIFO Not Full flag */
+      /*32-bit value can be written in */
+      JPEG_ReadInputData(hjpeg, 1);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /*Output FIFO flag handling*/
+  if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
+  {
+    if ((itflag & JPEG_FLAG_OFTF) != 0UL)
+    {
+      /*Output FIFO threshold flag */
+      /*JPEG_FIFO_TH_SIZE words can be read out */
+      JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE);
+    }
+    else if ((itflag & JPEG_FLAG_OFNEF) != 0UL)
+    {
+      /*Output FIFO Not Empty flag */
+      /*32-bit value can be read out */
+      JPEG_StoreOutputData(hjpeg, 1);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/
+  if ((itflag & (JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF)) == JPEG_FLAG_EOCF)
+  {
+    /*Stop Encoding/Decoding*/
+    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+    if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)
+    {
+      /* Disable All Interrupts */
+      __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+    }
+
+    /* Clear all flags */
+    __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
+
+    /*Call End of conversion callback */
+    if (hjpeg->JpegOutCount > 0UL)
+    {
+      /*Output Buffer is not empty, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+      HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+      hjpeg->JpegOutCount = 0;
+    }
+
+    /*Reset Context Operation*/
+    tmpContext = hjpeg->Context;
+    /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
+    hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    /* Change the JPEG state */
+    hjpeg->State = HAL_JPEG_STATE_READY;
+
+    /*Call End of Encoding/Decoding callback */
+    if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+    {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DecodeCpltCallback(hjpeg);
+#else
+      HAL_JPEG_DecodeCpltCallback(hjpeg);
+#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
+    }
+    else /* JPEG_CONTEXT_ENCODE */
+    {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->EncodeCpltCallback(hjpeg);
+#else
+      HAL_JPEG_EncodeCpltCallback(hjpeg);
+#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
+    }
+
+    return JPEG_PROCESS_DONE;
+  }
+
+  return JPEG_PROCESS_ONGOING;
+}
+
+/**
+  * @brief  Store some output data from the JPEG peripheral to the output buffer.
+  *         This function is used when the JPEG peripheral has new data to output
+  *         in case of Polling or Interrupt process
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  nbOutputWords Number of output words (of 32 bits) ready from the JPEG peripheral
+  * @retval None
+  */
+static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
+{
+  uint32_t index;
+  uint32_t nb_words;
+  uint32_t nb_bytes;
+  uint32_t dataword;
+
+  if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL)))
+  {
+    for (index = 0; index < nbOutputWords; index++)
+    {
+      /*Transfer 32 bits from the JPEG output FIFO*/
+      dataword = hjpeg->Instance->DOR;
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL);
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8);
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16);
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24);
+      hjpeg->JpegOutCount += 4UL;
+    }
+    if (hjpeg->OutDataLength == hjpeg->JpegOutCount)
+    {
+      /*Output Buffer is full, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+      HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
+      hjpeg->JpegOutCount = 0;
+    }
+  }
+  else if (hjpeg->OutDataLength > hjpeg->JpegOutCount)
+  {
+    nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
+    for (index = 0; index < nb_words; index++)
+    {
+      /*Transfer 32 bits from the JPEG output FIFO*/
+      dataword = hjpeg->Instance->DOR;
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL);
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8);
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16);
+      hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24);
+      hjpeg->JpegOutCount += 4UL;
+    }
+    if (hjpeg->OutDataLength == hjpeg->JpegOutCount)
+    {
+      /*Output Buffer is full, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+      HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+      hjpeg->JpegOutCount = 0;
+    }
+    else
+    {
+      nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
+      dataword = hjpeg->Instance->DOR;
+      for (index = 0; index < nb_bytes; index++)
+      {
+        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL);
+        hjpeg->JpegOutCount++;
+      }
+      /*Output Buffer is full, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+      HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+      hjpeg->JpegOutCount = 0;
+
+      nb_bytes = 4UL - nb_bytes;
+      for (index = nb_bytes; index < 4UL; index++)
+      {
+        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL);
+        hjpeg->JpegOutCount++;
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  Read some input Data from the input buffer.
+  *         This function is used when the JPEG peripheral needs new data
+  *         in case of Polling or Interrupt process
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @param  nbRequestWords Number of input words (of 32 bits) that the JPE peripheral request
+  * @retval None
+  */
+static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
+{
+  uint32_t nb_bytes = 0;
+  uint32_t nb_words;
+  uint32_t index;
+  uint32_t dataword;
+  uint32_t input_count;
+
+  if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL))
+  {
+    /* No more Input data : nothing to do*/
+    (void) HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);
+  }
+  else if (hjpeg->InDataLength > hjpeg->JpegInCount)
+  {
+    nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount;
+  }
+  else if (hjpeg->InDataLength == hjpeg->JpegInCount)
+  {
+    /*Call HAL_JPEG_GetDataCallback to get new data */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+    hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount);
+#else
+    HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
+#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/
+
+    if (hjpeg->InDataLength > 4UL)
+    {
+      hjpeg->InDataLength = ((hjpeg->InDataLength + 3UL) / 4UL) * 4UL;
+    }
+    hjpeg->JpegInCount = 0;
+    nb_bytes = hjpeg->InDataLength;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  if (((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL))
+  {
+    nb_words = nb_bytes / 4UL;
+    if (nb_words >= nbRequestWords)
+    {
+      for (index = 0; index < nbRequestWords; index++)
+      {
+        input_count = hjpeg->JpegInCount;
+        hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
+                                (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
+                                (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
+                                (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
+
+        hjpeg->JpegInCount += 4UL;
+      }
+    }
+    else /*nb_words < nbRequestWords*/
+    {
+      if (nb_words > 0UL)
+      {
+        for (index = 0; index < nb_words; index++)
+        {
+          input_count = hjpeg->JpegInCount;
+          hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
+                                  (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
+                                  (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
+                                  (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
+
+          hjpeg->JpegInCount += 4UL;
+        }
+      }
+      else
+      {
+        /* end of file*/
+        dataword = 0;
+        for (index = 0; index < nb_bytes; index++)
+        {
+          dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
+          hjpeg->JpegInCount++;
+        }
+        hjpeg->Instance->DIR = dataword;
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Start the JPEG DMA process (encoding/decoding)
+  * @note   The DMA interrupt must have a higher priority than the JPEG 
+  *         interrupt to prevent the JPEG interrupt from preempting the DMA interrupt
+  *         before the DMA state is updated to ready.
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
+  */
+static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)
+{
+  if ((hjpeg->InDataLength < 4UL) || (hjpeg->OutDataLength < 4UL))
+  {
+    return HAL_ERROR;
+  }
+  /* Reset Ending DMA internal context flag*/
+  hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA;
+
+  /* Disable DMA In/Out Request*/
+  JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA);
+
+  /* Set the JPEG DMA In transfer complete callback */
+  hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback;
+  /* Set the DMA In error callback */
+  hjpeg->hdmain->XferErrorCallback = JPEG_DMAErrorCallback;
+
+  /* Set the JPEG DMA Out transfer complete callback */
+  hjpeg->hdmaout->XferCpltCallback = JPEG_DMAOutCpltCallback;
+  /* Set the DMA Out error callback */
+  hjpeg->hdmaout->XferErrorCallback = JPEG_DMAErrorCallback;
+  /* Set the DMA Out Abort callback */
+  hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback;
+
+  /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/
+  hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
+
+  /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/
+  hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4UL);
+
+  if ((hjpeg->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hjpeg->hdmain->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hjpeg->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hjpeg->InDataLength;
+
+      /* Set DMA source address */
+      hjpeg->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hjpeg->pJpegInBuffPtr;
+
+      /* Set DMA destination address */
+      hjpeg->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hjpeg->Instance->DIR;
+
+      if (HAL_DMAEx_List_Start_IT(hjpeg->hdmain) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the JPEG State to ready */
+      hjpeg->State = HAL_JPEG_STATE_READY;
+
+      /* Update JPEG error code */
+      hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Start DMA FIFO In transfer */
+    if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
+                         hjpeg->InDataLength)  != HAL_OK)
+    {
+      hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+      return HAL_ERROR;
+    }
+  }
+
+  if ((hjpeg->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hjpeg->hdmaout->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hjpeg->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hjpeg->OutDataLength;
+
+      /* Set DMA source address */
+      hjpeg->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hjpeg->Instance->DOR;
+
+      /* Set DMA destination address */
+      hjpeg->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hjpeg->pJpegOutBuffPtr;
+
+      if (HAL_DMAEx_List_Start_IT(hjpeg->hdmaout) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the JPEG State to ready */
+      hjpeg->State = HAL_JPEG_STATE_READY;
+
+      /* Update JPEG error code */
+      hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hjpeg);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Start DMA FIFO Out transfer */
+    if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
+                         hjpeg->OutDataLength)  != HAL_OK)
+    {
+      hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable JPEG In/Out DMA requests*/
+  JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA | JPEG_DMA_ODMA);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Continue the current JPEG DMA process (encoding/decoding)
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING
+  */
+static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t itflag = hjpeg->Instance->SR;
+
+  /*End of header processing flag rises*/
+  if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+  {
+    if ((itflag & JPEG_FLAG_HPDF) != 0UL)
+    {
+      /*Call Header parsing complete callback */
+      (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
+
+      /* Reset the ImageQuality */
+      hjpeg->Conf.ImageQuality = 0;
+      /* Note : the image quality is only available at the end of the decoding operation */
+      /* at the current stage the calculated image quality is not correct so reset it */
+
+      /*Call Info Ready callback */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#else
+      HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+      __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD);
+
+      /* Clear header processing done flag */
+      __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF);
+    }
+  }
+
+  /*End of Conversion handling*/
+  if ((itflag & JPEG_FLAG_EOCF) != 0UL)
+  {
+    /*Disable JPEG In/Out DMA Requests*/
+    JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA);
+
+    hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA;
+
+    /*Stop Encoding/Decoding*/
+    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+    __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+
+    /* Clear all flags */
+    __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL);
+
+    if (hjpeg->hdmain->State == HAL_DMA_STATE_BUSY)
+    {
+      /* Stop the DMA In Xfer*/
+      (void) HAL_DMA_Abort_IT(hjpeg->hdmain);
+    }
+
+    if (hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY)
+    {
+      /* Stop the DMA out Xfer*/
+      (void) HAL_DMA_Abort_IT(hjpeg->hdmaout);
+    }
+    else
+    {
+      JPEG_DMA_EndProcess(hjpeg);
+    }
+  }
+}
+
+/**
+  * @brief  Finalize the current JPEG DMA process (encoding/decoding)
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval JPEG_PROCESS_DONE
+  */
+static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t tmpContext;
+  hjpeg->JpegOutCount = hjpeg->OutDataLength - JPEG_GET_DMA_REMAIN_DATA(hjpeg->hdmaout);
+
+  /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
+  if (hjpeg->JpegOutCount == hjpeg->OutDataLength)
+  {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+    hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+    HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+    hjpeg->JpegOutCount = 0;
+  }
+
+  /*Check if remaining data in the output FIFO*/
+  if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL)
+  {
+    if (hjpeg->JpegOutCount > 0UL)
+    {
+      /*Output Buffer is not empty, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+      HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+      hjpeg->JpegOutCount = 0;
+    }
+
+    /*Stop Encoding/Decoding*/
+    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+    tmpContext = hjpeg->Context;
+    /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
+    hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    /* Change the JPEG state */
+    hjpeg->State = HAL_JPEG_STATE_READY;
+
+    /*Call End of Encoding/Decoding callback */
+    if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+    {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DecodeCpltCallback(hjpeg);
+#else
+      HAL_JPEG_DecodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+    }
+    else /* JPEG_CONTEXT_ENCODE */
+    {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->EncodeCpltCallback(hjpeg);
+#else
+      HAL_JPEG_EncodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+    }
+  }
+  else if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
+  {
+    JPEG_DMA_PollResidualData(hjpeg);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+}
+
+/**
+  * @brief  Poll residual output data when DMA process (encoding/decoding)
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval None.
+  */
+static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t tmpContext;
+  uint32_t count;
+  uint32_t dataOut;
+
+  for (count = JPEG_FIFO_SIZE; count > 0UL; count--)
+  {
+    if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
+    {
+      if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL)
+      {
+        dataOut = hjpeg->Instance->DOR;
+        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataOut & 0x000000FFUL);
+        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataOut & 0x0000FF00UL) >> 8);
+        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataOut & 0x00FF0000UL) >> 16);
+        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataOut & 0xFF000000UL) >> 24);
+        hjpeg->JpegOutCount += 4UL;
+
+        if (hjpeg->JpegOutCount == hjpeg->OutDataLength)
+        {
+          /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+          hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+          HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+          hjpeg->JpegOutCount = 0;
+        }
+
+      }
+    }
+  }
+
+  tmpContext = hjpeg->Context;
+
+  if ((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) || ((tmpContext & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL))
+  {
+    /*Stop Encoding/Decoding*/
+    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+    if (hjpeg->JpegOutCount > 0UL)
+    {
+      /*Output Buffer is not empty, call DecodedDataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+      HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+      hjpeg->JpegOutCount = 0;
+    }
+
+    tmpContext = hjpeg->Context;
+    /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
+    hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hjpeg);
+
+    /* Change the JPEG state */
+    hjpeg->State = HAL_JPEG_STATE_READY;
+
+    /*Call End of Encoding/Decoding callback */
+    if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+    {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DecodeCpltCallback(hjpeg);
+#else
+      HAL_JPEG_DecodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+    }
+    else /* JPEG_CONTEXT_ENCODE */
+    {
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->EncodeCpltCallback(hjpeg);
+#else
+      HAL_JPEG_EncodeCpltCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  DMA input transfer complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure.
+  * @retval None
+  */
+static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
+  __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+
+  if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) ==
+      JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */
+  {
+    JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_IDMA);
+
+    hjpeg->JpegInCount = hjpeg->InDataLength - JPEG_GET_DMA_REMAIN_DATA(hdma);
+
+    /*Call HAL_JPEG_GetDataCallback to get new data */
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+    hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount);
+#else
+    HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+    if (hjpeg->InDataLength >= 4UL)
+    {
+      /*JPEG Input DMA transfer data number must be multiple of 32 bits word
+        as the destination is a 32 bits (4 bytes) register */
+      hjpeg->InDataLength = ((hjpeg->InDataLength + 3UL) / 4UL) * 4UL;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    if (((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (hjpeg->InDataLength > 0UL))
+    {
+      /* Start DMA FIFO In transfer */
+      if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR,
+                           hjpeg->InDataLength) != HAL_OK)
+      {
+        hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+        hjpeg->State = HAL_JPEG_STATE_ERROR;
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+        hjpeg->ErrorCallback(hjpeg);
+#else
+        HAL_JPEG_ErrorCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+        return;
+      }
+      JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA);
+    }
+
+    /* JPEG Conversion still on going : Enable the JPEG IT */
+    __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
+  }
+}
+
+/**
+  * @brief  DMA output transfer complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure.
+  * @retval None
+  */
+static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */
+  __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+
+  if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) ==
+      JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */
+  {
+    if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0UL)
+    {
+      JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA);
+      hjpeg->JpegOutCount = hjpeg->OutDataLength - JPEG_GET_DMA_REMAIN_DATA(hdma);
+
+      /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+      hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#else
+      HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+
+      if ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)
+      {
+        /* Start DMA FIFO Out transfer */
+        if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr,
+                             hjpeg->OutDataLength) != HAL_OK)
+        {
+          hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+          hjpeg->State = HAL_JPEG_STATE_ERROR;
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+          hjpeg->ErrorCallback(hjpeg);
+#else
+          HAL_JPEG_ErrorCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+          return;
+        }
+        JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_ODMA);
+      }
+    }
+
+    /* JPEG Conversion still on going : Enable the JPEG IT */
+    __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD);
+  }
+}
+
+
+/**
+  * @brief  DMA Transfer error callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure.
+  * @retval None
+  */
+static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE)
+  {
+    /*Stop Encoding/Decoding*/
+    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;
+
+    /* Disable All Interrupts */
+    __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK);
+
+    /* Disable All DMA requests */
+    JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK);
+
+    hjpeg->State = HAL_JPEG_STATE_READY;
+    hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA;
+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)
+    hjpeg->ErrorCallback(hjpeg);
+#else
+    HAL_JPEG_ErrorCallback(hjpeg);
+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  DMA output Abort callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure.
+  * @retval None
+  */
+static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL)
+  {
+    JPEG_DMA_EndProcess(hjpeg);
+  }
+}
+
+
+/**
+  * @brief  Calculate the decoded image quality (from 1 to 100)
+  * @param  hjpeg pointer to a JPEG_HandleTypeDef structure that contains
+  *         the configuration information for JPEG module
+  * @retval JPEG image quality from 1 to 100.
+  */
+static uint32_t JPEG_GetQuality(const JPEG_HandleTypeDef *hjpeg)
+{
+  uint32_t quality = 0;
+  uint32_t quantRow;
+  uint32_t quantVal;
+  uint32_t scale;
+  uint32_t i;
+  uint32_t j;
+  const __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0;
+
+  i = 0;
+  while (i < (JPEG_QUANT_TABLE_SIZE - 3UL))
+  {
+    quantRow = *tableAddress;
+    for (j = 0; j < 4UL; j++)
+    {
+      quantVal = (quantRow >> (8UL * j)) & 0xFFUL;
+      if (quantVal == 1UL)
+      {
+        /* if Quantization value = 1 then quality is 100%*/
+        quality += 100UL;
+      }
+      else
+      {
+        /* Note that the quantization coefficients must be specified in the table in zigzag order */
+        scale = (quantVal * 100UL) / ((uint32_t) hjpeg->QuantTable0[JPEG_ZIGZAG_ORDER[i + j]]);
+
+        if (scale <= 100UL)
+        {
+          quality += (200UL - scale) / 2UL;
+        }
+        else
+        {
+          quality += 5000UL / scale;
+        }
+      }
+    }
+
+    i += 4UL;
+    tableAddress ++;
+  }
+
+  return (quality / 64UL);
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* JPEG */
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_lptim.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_lptim.c
new file mode 100644
index 000000000..a16aab72d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_lptim.c
@@ -0,0 +1,3777 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_lptim.c
+  * @author  MCD Application Team
+  * @brief   LPTIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Low Power Timer (LPTIM) peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Start/Stop operation functions in polling mode.
+  *           + Start/Stop operation functions in interrupt mode.
+  *           + Reading operation functions.
+  *           + Peripheral State functions.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The LPTIM HAL driver can be used as follows:
+
+      (#)Initialize the LPTIM low level resources by implementing the
+        HAL_LPTIM_MspInit():
+         (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
+         (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
+             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
+             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
+
+      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
+         configures mainly:
+         (++) The instance: LPTIM1, LPTIM2, LPTIM3, LPTIM4 or LPTIM5.
+         (++) Clock: the counter clock.
+             (+++) Source   : it can be either the ULPTIM input (IN1) or one of
+                              the internal clock; (APB, LSE, LSI or MSI).
+             (+++) Prescaler: select the clock divider.
+         (++)  UltraLowPowerClock : To be used only if the ULPTIM is selected
+               as counter clock source.
+             (+++) Polarity:   polarity of the active edge for the counter unit
+                               if the ULPTIM input is selected.
+             (+++) SampleTime: clock sampling time to configure the clock glitch
+                               filter.
+         (++) Trigger: How the counter start.
+             (+++) Source: trigger can be software or one of the hardware triggers.
+             (+++) ActiveEdge : only for hardware trigger.
+             (+++) SampleTime : trigger sampling time to configure the trigger
+                                glitch filter.
+         (++) OutputPolarity : 2 opposite polarities are possible.
+         (++) UpdateMode: specifies whether the update of the autoreload and
+              the compare values is done immediately or after the end of current
+              period.
+         (++) Input1Source: Source selected for input1 (GPIO or comparator output).
+         (++) Input2Source: Source selected for input2 (GPIO or comparator output).
+              Input2 is used only for encoder feature so is used only for LPTIM1 instance.
+
+      (#)Six modes are available:
+
+         (++) PWM Mode: To generate a PWM signal with specified period and pulse,
+         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
+         mode.
+
+         (++) One Pulse Mode: To generate pulse with specified width in response
+         to a stimulus, call HAL_LPTIM_OnePulse_Start() or
+         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
+
+         (++) Set once Mode: In this mode, the output changes the level (from
+         low level to high level if the output polarity is configured high, else
+         the opposite) when a compare match occurs. To start this mode, call
+         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
+         interruption mode.
+
+         (++) Encoder Mode: To use the encoder interface call
+         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
+         interruption mode. Only available for LPTIM1 instance.
+
+         (++) Time out Mode: an active edge on one selected trigger input rests
+         the counter. The first trigger event will start the timer, any
+         successive trigger event will reset the counter and the timer will
+         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
+         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
+
+         (++) Counter Mode: counter can be used to count external events on
+         the LPTIM Input1 or it can be used to count internal clock cycles.
+         To start this mode, call HAL_LPTIM_Counter_Start() or
+         HAL_LPTIM_Counter_Start_IT() for interruption mode.
+
+
+      (#) User can stop any process by calling the corresponding API:
+          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
+          already started in interruption mode.
+
+      (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
+
+    *** Callback registration ***
+  =============================================
+  [..]
+  The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  [..]
+  Use Function HAL_LPTIM_RegisterCallback() to register a callback.
+  HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+  [..]
+  Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
+  default weak function.
+  HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  [..]
+  These functions allow to register/unregister following callbacks:
+
+    (+) MspInitCallback         : LPTIM Base Msp Init Callback.
+    (+) MspDeInitCallback       : LPTIM Base Msp DeInit Callback.
+    (+) CompareMatchCallback    : Compare match Callback.
+    (+) AutoReloadMatchCallback : Auto-reload match Callback.
+    (+) TriggerCallback         : External trigger event detection Callback.
+    (+) CompareWriteCallback    : Compare register write complete Callback.
+    (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
+    (+) DirectionUpCallback     : Up-counting direction change Callback.
+    (+) DirectionDownCallback   : Down-counting direction change Callback.
+    (+) UpdateEventCallback     : Update event detection Callback.
+    (+) RepCounterWriteCallback : Repetition counter register write complete Callback.
+
+  [..]
+  By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
+  all interrupt callbacks are set to the corresponding weak functions:
+  examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init/DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  [..]
+  Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+  When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup LPTIM LPTIM
+  * @brief LPTIM HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Constants
+  * @{
+  */
+#define TIMEOUT                                     1000UL /* Timeout is 1s */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros
+  * @{
+  */
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \
+  (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() :\
+   ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() :\
+   ((__INSTANCE__) == LPTIM3) ? __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() :\
+   ((__INSTANCE__) == LPTIM4) ? __HAL_LPTIM_LPTIM4_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM5_EXTI_ENABLE_IT())
+
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \
+  (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() :\
+   ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() :\
+   ((__INSTANCE__) == LPTIM3) ? __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() :\
+   ((__INSTANCE__) == LPTIM4) ? __HAL_LPTIM_LPTIM4_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM5_EXTI_DISABLE_IT())
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
+static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
+static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
+static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
+void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
+void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
+void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+                                     uint32_t length);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
+  * @{
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the LPTIM according to the specified parameters in the
+          LPTIM_InitTypeDef and initialize the associated handle.
+      (+) DeInitialize the LPTIM peripheral.
+      (+) Initialize the LPTIM MSP.
+      (+) DeInitialize the LPTIM MSP.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the LPTIM according to the specified parameters in the
+  *         LPTIM_InitTypeDef and initialize the associated handle.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
+{
+  uint32_t tmpcfgr;
+
+  /* Check the LPTIM handle allocation */
+  if (hlptim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
+
+  assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
+  assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+    assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+  }
+  assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
+  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+    assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
+  }
+  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
+  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
+  assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
+
+  if (hlptim->State == HAL_LPTIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hlptim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    LPTIM_ResetCallback(hlptim);
+
+    if (hlptim->MspInitCallback == NULL)
+    {
+      hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    hlptim->MspInitCallback(hlptim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_LPTIM_MspInit(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+  }
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
+
+  /* Set the repetition counter */
+  __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
+
+  /* Wait for the completion of the write operation to the LPTIM_RCR register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+  /* Set LPTIM Period */
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
+
+  /* Wait for the completion of the write operation to the LPTIM_ARR register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+  }
+  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+  }
+
+  /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+                          LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
+
+  /* Set initialization parameters */
+  tmpcfgr |= (hlptim->Init.Clock.Source    |
+              hlptim->Init.Clock.Prescaler |
+              hlptim->Init.UpdateMode      |
+              hlptim->Init.CounterSource);
+
+  /* Glitch filters for internal triggers and  external inputs are configured
+   * only if an internal clock source is provided to the LPTIM
+   */
+  if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+  {
+    tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
+                hlptim->Init.UltraLowPowerClock.SampleTime);
+  }
+
+  /* Configure LPTIM external clock polarity and digital filter */
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+                hlptim->Init.UltraLowPowerClock.SampleTime);
+  }
+
+  /* Configure LPTIM external trigger */
+  if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Enable External trigger and set the trigger source */
+    tmpcfgr |= (hlptim->Init.Trigger.Source     |
+                hlptim->Init.Trigger.ActiveEdge |
+                hlptim->Init.Trigger.SampleTime);
+  }
+
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+
+  /* Configure LPTIM input sources */
+  if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
+  {
+    /* Check LPTIM Input1 and Input2 sources */
+    assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
+    assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
+
+    /* Configure LPTIM Input1 and Input2 sources */
+    hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
+  }
+  else
+  {
+    if (hlptim->Instance == LPTIM3)
+    {
+      /* Check LPTIM3 Input1 source */
+      assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
+
+      /* Configure LPTIM3 Input1 source */
+      hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
+    }
+  }
+
+  /* Initialize the LPTIM channels state */
+  LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the LPTIM peripheral.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the LPTIM handle allocation */
+  if (hlptim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  __HAL_LPTIM_ENABLE(hlptim);
+  if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+  {
+    hlptim->Instance->CCMR1 = 0;
+  }
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+  __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
+  /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
+  {
+    /* Clear flag */
+    __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
+
+    __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
+    /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
+    if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+  __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
+
+  /* Wait for the completion of the write operation to the LPTIM_ARR register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Disable the LPTIM Peripheral Clock */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  hlptim->Instance->CFGR = 0;
+  hlptim->Instance->CFGR2 = 0;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+  if (hlptim->MspDeInitCallback == NULL)
+  {
+    hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  hlptim->MspDeInitCallback(hlptim);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_LPTIM_MspDeInit(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+  /* Change the LPTIM channels state */
+  LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hlptim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the LPTIM MSP.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize LPTIM MSP.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
+  *  @brief   Start-Stop operation functions.
+  *
+@verbatim
+  ==============================================================================
+                ##### LPTIM Start Stop operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start the PWM mode.
+      (+) Stop the PWM mode.
+      (+) Start the One pulse mode.
+      (+) Stop the One pulse mode.
+      (+) Start the Set once mode.
+      (+) Stop the Set once mode.
+      (+) Start the Encoder mode.
+      (+) Stop the Encoder mode.
+      (+) Start the Timeout mode.
+      (+) Stop the Timeout mode.
+      (+) Start the Counter mode.
+      (+) Stop the Counter mode.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the LPTIM PWM generation.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Reset WAVE bit to set PWM mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Enable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM PWM generation.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be disabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable LPTIM signal from the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM PWM generation in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Reset WAVE bit to set PWM mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Enable interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                            LPTIM_IT_UPDATE);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Enable interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                            LPTIM_IT_UPDATE);
+      break;
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Clear flag */
+    __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+
+    /* Wait for the completion of the write operation to the LPTIM_DIER register */
+    if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM PWM generation in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be disabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable LPTIM signal from the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Disable interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                             LPTIM_IT_UPDATE);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Disable interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                             LPTIM_IT_UPDATE);
+      break;
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Clear flag */
+    __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+
+    /* Wait for the completion of the write operation to the LPTIM_DIER register */
+    if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM PWM generation in DMA mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @param  pData The destination Buffer address
+  * @param  Length The length of data to be transferred from LPTIM peripheral to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
+                                          uint32_t Length)
+{
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  if ((pData == NULL) || (Length == 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Reset WAVE bit to set PWM mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Enable update event DMA request */
+  __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Set the DMA update event callbacks */
+      hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
+      hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
+
+      /* Set the DMA error callback */
+      hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
+
+      /* Enable the DMA Channel */
+      hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
+      if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Set the DMA update event callbacks */
+      hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
+      hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
+
+      /* Set the DMA error callback */
+      hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
+
+      /* Enable the DMA Channel */
+      hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
+      if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    default:
+      break;
+  }
+
+  /* Enable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM PWM generation in DMA mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be disabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable update event DMA request */
+  __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Disable update event DMA request */
+      (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Disable update event DMA request */
+      (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
+      break;
+    default:
+      break;
+  }
+
+  /* Disable LPTIM signal from the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM One pulse generation.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Reset WAVE bit to set one pulse mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Enable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Start timer in single (one shot) mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM One pulse generation.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be disabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM One pulse generation in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Reset WAVE bit to set one pulse mode */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Enable  interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                            LPTIM_IT_UPDATE);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Enable interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                            LPTIM_IT_UPDATE);
+      break;
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Clear flag */
+    __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+    /* Wait for the completion of the write operation to the LPTIM_DIER register */
+    if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Enable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Start timer in single (one shot) mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM One pulse generation in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be disabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Disable interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                             LPTIM_IT_UPDATE);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Disable interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
+                             LPTIM_IT_UPDATE);
+      break;
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Clear flag */
+    __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+    /* Wait for the completion of the write operation to the LPTIM_DIER register */
+    if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM in Set once mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Set WAVE bit to enable the set once mode */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Enable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Start timer in single (one shot) mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM Set once mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be disabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the LPTIM Set once mode in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Set WAVE bit to enable the set once mode */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Enable interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Enable interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
+      break;
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Clear flag */
+    __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+    /* Wait for the completion of the write operation to the LPTIM_DIER register */
+    if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Enable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Start timer in single (one shot) mode */
+  __HAL_LPTIM_START_SINGLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the LPTIM Set once mode in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be disabled
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable LPTIM signal on the corresponding output pin */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Disable interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Disable interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
+      break;
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* If external trigger source is used, then enable external trigger interrupt */
+  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+  {
+    /* Clear flag */
+    __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+    /* Enable external trigger interrupt */
+    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
+
+    /* Wait for the completion of the write operation to the LPTIM_DIER register */
+    if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Encoder interface.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
+{
+  uint32_t          tmpcfgr;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+
+  /* Clear CKPOL bits */
+  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+  /* Set Input polarity */
+  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
+
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+
+  /* Set ENC bit to enable the encoder interface */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Encoder interface.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Reset ENC bit to disable the encoder interface */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Encoder interface in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  uint32_t          tmpcfgr;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
+  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
+  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Configure edge sensitivity for encoder mode */
+  /* Get the LPTIMx CFGR value */
+  tmpcfgr = hlptim->Instance->CFGR;
+
+  /* Clear CKPOL bits */
+  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
+
+  /* Set Input polarity */
+  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;
+
+  /* Write to LPTIMx CFGR */
+  hlptim->Instance->CFGR = tmpcfgr;
+
+  /* Set ENC bit to enable the encoder interface */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  /* Enable "switch to up/down direction" interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Encoder interface in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Reset ENC bit to disable the encoder interface */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  /* Disable "switch to down/up direction" interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Timeout function.
+  * @note   The first trigger event will start the timer, any successive
+  *         trigger event will reset the counter and the timer restarts.
+  * @param  hlptim LPTIM handle
+  * @param  Timeout Specifies the TimeOut value to reset the counter.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PULSE(Timeout));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+  /* Load the Timeout value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
+
+  /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Timeout function.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Reset TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Timeout function in interrupt mode.
+  * @note   The first trigger event will start the timer, any successive
+  *         trigger event will reset the counter and the timer restarts.
+  * @param  hlptim LPTIM handle
+  * @param  Timeout Specifies the TimeOut value to reset the counter.
+  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_PULSE(Timeout));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
+
+  /* Set TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  /* Enable Compare match CH1 interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+  /* Load the Timeout value in the compare register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
+
+  /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Timeout function in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+
+  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Reset TIMOUT bit to enable the timeout function */
+  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  /* Disable Compare match CH1 interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Counter mode.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+  if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+      && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    /* Check if clock is prescaled */
+    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+    /* Set clock prescaler to 0 */
+    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+  }
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Counter mode.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the Counter mode in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
+
+  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
+  if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+      && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  {
+    /* Check if clock is prescaled */
+    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
+    /* Set clock prescaler to 0 */
+    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
+  }
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  /* Enable interrupt */
+  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the Counter mode in interrupt mode.
+  * @param  hlptim LPTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+
+  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
+
+  /* Disable interrupt */
+  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM Input Capture measurement.
+  * @param  hlptim LPTIM Input Capture handle
+  * @param  Channel LPTIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Enable capture */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM Input Capture measurement.
+  * @param  hlptim LPTIM Input Capture handle
+  * @param  Channel LPTIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Disable capture */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM Input Capture measurement in interrupt mode.
+  * @param  hlptim LPTIM Input Capture handle
+  * @param  Channel LPTIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Enable Capture/Compare 1 interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Disable Capture/Compare 2 interrupt */
+      __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
+      break;
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Enable capture */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM Input Capture measurement in interrupt mode.
+  * @param  hlptim LPTIM Input Capture handle
+  * @param  Channel LPTIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Disable Capture/Compare 1 interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
+      break;
+    case LPTIM_CHANNEL_2:
+      /* Disable Capture/Compare 2 interrupt */
+      __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
+      break;
+    default:
+      return HAL_ERROR;
+      break;
+  }
+  /* Disable capture */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the LPTIM Input Capture measurement in DMA mode.
+  * @param  hlptim LPTIM Input Capture handle
+  * @param  Channel LPTIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  pData The destination Buffer address
+  * @param  Length The length of data to be transferred from LPTIM peripheral to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
+                                         uint32_t Length)
+{
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  if ((pData == NULL) || (Length == 0U))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check LPTIM channel state */
+  if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Set the DMA capture callbacks */
+      hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
+      hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
+
+      /* Enable the DMA Channel */
+      hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
+      if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable Capture/Compare 1 DMA request */
+      __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
+      break;
+
+    case LPTIM_CHANNEL_2:
+      /* Set the DMA capture callbacks */
+      hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
+      hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
+
+      /* Enable the DMA Channel */
+      hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
+      if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable Capture/Compare 2 DMA request */
+      __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
+      break;
+
+    default:
+      break;
+  }
+
+  /* Wait for the completion of the write operation to the LPTIM_DIER register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Start timer in continuous mode */
+  __HAL_LPTIM_START_CONTINUOUS(hlptim);
+
+  /* Enable capture */
+  __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the LPTIM Input Capture measurement in DMA mode.
+  * @param  hlptim LPTIM Input Capture handle
+  * @param  Channel LPTIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      /* Disable Capture/Compare 1 DMA request */
+      __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
+      break;
+
+    case LPTIM_CHANNEL_2:
+      /* Disable Capture/Compare 2 DMA request */
+      __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
+      break;
+    default:
+      return HAL_ERROR;
+      break;
+  }
+
+  /* Disable capture */
+  __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Set the LPTIM channel state */
+  LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
+
+  /* Set the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
+  *  @brief  Read operation functions.
+  *
+@verbatim
+  ==============================================================================
+                  ##### LPTIM Read operation functions #####
+  ==============================================================================
+[..]  This section provides LPTIM Reading functions.
+      (+) Read the counter value.
+      (+) Read the period (Auto-reload) value.
+      (+) Read the pulse (Compare)value.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the current counter value.
+  * @param  hlptim LPTIM handle
+  * @retval Counter value.
+  */
+uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+  return (hlptim->Instance->CNT);
+}
+
+/**
+  * @brief  Return the current Autoreload (Period) value.
+  * @param  hlptim LPTIM handle
+  * @retval Autoreload value.
+  */
+uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
+
+  return (hlptim->Instance->ARR);
+}
+
+/**
+  * @brief  Return the current Compare (Pulse) value.
+  * @param  hlptim LPTIM handle
+  * @param  Channel LPTIM Channel to be selected
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval Compare value.
+  */
+uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+  uint32_t tmpccr;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+      tmpccr = hlptim->Instance->CCR1;
+      break;
+    case LPTIM_CHANNEL_2:
+      tmpccr = hlptim->Instance->CCR2;
+      break;
+    default:
+      tmpccr = 0;
+      break;
+  }
+  return tmpccr;
+}
+
+/**
+  * @brief  LPTimer Input Capture Get Offset(in counter step unit)
+  * @note   The real capture value corresponding to the input capture trigger can be calculated using
+  *         the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
+  *         The Offset value is depending on the glitch filter value for the channel
+  *         and the value of the prescaler for the kernel clock.
+  *         Please check Errata Sheet V1_8 for more details under "variable latency
+  *         on input capture channel" section.
+  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+  *         the configuration information for LPTIM module.
+  * @param  Channel This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @retval The offset value
+  */
+uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
+{
+
+  uint8_t offset ;
+  uint32_t prescaler;
+  uint32_t filter ;
+
+  /* Get prescaler value */
+  prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance);
+
+  /* Get filter value */
+  filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel);
+
+  /* Get offset value */
+  offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter);
+
+  /* return offset value */
+  return offset;
+}
+
+/**
+  * @}
+  */
+/** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
+  *  @brief  Config channel
+  *
+@verbatim
+  ==============================================================================
+                  ##### LPTIM Config function #####
+  ==============================================================================
+[..]  This section provides LPTIM Config function.
+      (+) Configure channel: Output Compare mode, Period, Polarity.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief
+  * @param  hlptim LPTIM handle
+  * @param  sConfig The output configuration structure
+  * @param  Channel LPTIM Channel to be configured
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @note   Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed
+  *         after a delay that must be greater or equal than the value of
+  *        (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
+  *         division factor (1, 2, 4, ..., 128). Any successive call violating
+  *         this delay, leads to unpredictable results.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
+                                             uint32_t Channel)
+{
+  HAL_StatusTypeDef status;
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+  assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
+
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
+
+      /* Configure the LPTIM Channel 1 in Output Compare */
+      status = LPTIM_OC1_SetConfig(hlptim, sConfig);
+      if (status != HAL_OK)
+      {
+        return status;
+      }
+      break;
+    }
+    case LPTIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
+
+      /* Configure the LPTIM Channel 2 in Output Compare */
+      status = LPTIM_OC2_SetConfig(hlptim, sConfig);
+      if (status != HAL_OK)
+      {
+        return status;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief
+  * @param  hlptim LPTIM handle
+  * @param  sConfig The input configuration structure
+  * @param  Channel LPTIM Channel to be configured
+  *         This parameter can be one of the following values:
+  *            @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
+  *            @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
+  * @note   Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed
+  *         after a delay that must be greater or equal than the value of
+  *        (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
+  *         division factor (1, 2, 4, ..., 128). Any successive call violating
+  *         this delay, leads to unpredictable results.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
+                                             uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
+  assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
+
+  hlptim->State = HAL_LPTIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case LPTIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
+      assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
+
+      /* Configure the LPTIM Channel 1 in Input Capture */
+      LPTIM_IC1_SetConfig(hlptim, sConfig);
+      break;
+    }
+    case LPTIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
+      assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
+
+      /* Configure the LPTIM Channel 2 in Input Capture */
+      LPTIM_IC2_SetConfig(hlptim, sConfig);
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Change the LPTIM state */
+  hlptim->State = HAL_LPTIM_STATE_READY;
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
+  *  @brief  LPTIM  IRQ handler.
+  *
+@verbatim
+  ==============================================================================
+                      ##### LPTIM IRQ handler and callbacks  #####
+  ==============================================================================
+[..]  This section provides LPTIM IRQ handler and callback functions called within
+      the IRQ handler:
+   (+) LPTIM interrupt request handler
+   (+) Compare match Callback
+   (+) Auto-reload match Callback
+   (+) External trigger event detection Callback
+   (+) Compare register write complete Callback
+   (+) Auto-reload register write complete Callback
+   (+) Up-counting direction change Callback
+   (+) Down-counting direction change Callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle LPTIM interrupt request.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Capture Compare 1 interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
+    {
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+
+      /* Input capture event */
+      if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
+      {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+        hlptim->IC_CaptureCallback(hlptim);
+#else
+        HAL_LPTIM_IC_CaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+        hlptim->CompareMatchCallback(hlptim);
+#else
+        HAL_LPTIM_CompareMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+      }
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+
+  /* Capture Compare 2 interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
+    {
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+
+      /* Input capture event */
+      if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
+      {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+        hlptim->IC_CaptureCallback(hlptim);
+#else
+        HAL_LPTIM_IC_CaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+        hlptim->CompareMatchCallback(hlptim);
+#else
+        HAL_LPTIM_CompareMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+      }
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+
+  /* Over Capture 1 interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
+    {
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+
+      /* Over capture event */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->IC_OverCaptureCallback(hlptim);
+#else
+      HAL_LPTIM_IC_OverCaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+
+  /* Over Capture 2 interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
+    {
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+
+      /* Over capture event */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->IC_OverCaptureCallback(hlptim);
+#else
+      HAL_LPTIM_IC_OverCaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+
+  /* Autoreload match interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
+    {
+      /* Clear Autoreload match flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+
+      /* Autoreload match Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->AutoReloadMatchCallback(hlptim);
+#else
+      HAL_LPTIM_AutoReloadMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Trigger detected interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
+    {
+      /* Clear Trigger detected flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+
+      /* Trigger detected callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->TriggerCallback(hlptim);
+#else
+      HAL_LPTIM_TriggerCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Compare write interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
+    {
+      /* Clear Compare write flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+      /* Compare write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->CompareWriteCallback(hlptim);
+#else
+      HAL_LPTIM_CompareWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Compare write interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
+    {
+      /* Clear Compare write flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
+      hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+      /* Compare write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->CompareWriteCallback(hlptim);
+#else
+      HAL_LPTIM_CompareWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Autoreload write interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
+    {
+      /* Clear Autoreload write flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+      /* Autoreload write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->AutoReloadWriteCallback(hlptim);
+#else
+      HAL_LPTIM_AutoReloadWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Direction counter changed from Down to Up interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
+    {
+      /* Clear Direction counter changed from Down to Up flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+
+      /* Direction counter changed from Down to Up Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->DirectionUpCallback(hlptim);
+#else
+      HAL_LPTIM_DirectionUpCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Direction counter changed from Up to Down interrupt */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
+    {
+      /* Clear Direction counter changed from Up to Down flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+
+      /* Direction counter changed from Up to Down Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->DirectionDownCallback(hlptim);
+#else
+      HAL_LPTIM_DirectionDownCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Repetition counter underflowed (or contains zero) and the LPTIM counter
+     overflowed */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
+    {
+      /* Clear update event flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
+
+      /* Update event Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->UpdateEventCallback(hlptim);
+#else
+      HAL_LPTIM_UpdateEventCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Successful APB bus write to repetition counter register */
+  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
+  {
+    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
+    {
+      /* Clear successful APB bus write to repetition counter flag */
+      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
+
+      /* Successful APB bus write to repetition counter Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+      hlptim->RepCounterWriteCallback(hlptim);
+#else
+      HAL_LPTIM_RepCounterWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Compare match callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Autoreload match callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Trigger detected callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Compare write callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Autoreload write callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Successful APB bus write to repetition counter register callback in non-blocking mode.
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Over Capture callback in non-blocking mode
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  hlptim LPTIM IC handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Update event half complete callback in non-blocking mode
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback in non-blocking mode
+  * @param  hlptim LPTIM handle
+  * @retval None
+  */
+__weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hlptim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LPTIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User LPTIM callback to be used instead of the weak predefined callback
+  * @param hlptim LPTIM handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
+  *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
+  *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
+  *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+  *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
+  *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
+  *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+  *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
+  *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
+  *          @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID      Update event detection Callback ID
+  *          @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
+  *          @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
+  *          @arg @ref HAL_LPTIM_ERROR_CB_ID             Error  Callback ID
+  *          @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID        Input Capture Callback ID
+  *          @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID   Input Capture half complete Callback ID
+  *          @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID      Over Capture Callback ID
+  * @param pCallback pointer to the callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
+                                             HAL_LPTIM_CallbackIDTypeDef CallbackID,
+                                             pLPTIM_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hlptim->State == HAL_LPTIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LPTIM_MSPINIT_CB_ID :
+        hlptim->MspInitCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_MSPDEINIT_CB_ID :
+        hlptim->MspDeInitCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+        hlptim->CompareMatchCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+        hlptim->AutoReloadMatchCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_TRIGGER_CB_ID :
+        hlptim->TriggerCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+        hlptim->CompareWriteCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+        hlptim->AutoReloadWriteCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_DIRECTION_UP_CB_ID :
+        hlptim->DirectionUpCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+        hlptim->DirectionDownCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_UPDATE_EVENT_CB_ID :
+        hlptim->UpdateEventCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
+        hlptim->RepCounterWriteCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
+        hlptim->UpdateEventHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_ERROR_CB_ID :
+        hlptim->ErrorCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_IC_CAPTURE_CB_ID :
+        hlptim->IC_CaptureCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
+        hlptim->IC_CaptureHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_OVER_CAPTURE_CB_ID :
+        hlptim->IC_OverCaptureCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hlptim->State == HAL_LPTIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LPTIM_MSPINIT_CB_ID :
+        hlptim->MspInitCallback = pCallback;
+        break;
+
+      case HAL_LPTIM_MSPDEINIT_CB_ID :
+        hlptim->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a LPTIM callback
+  *         LLPTIM callback is redirected to the weak predefined callback
+  * @param hlptim LPTIM handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID          LPTIM Base Msp Init Callback ID
+  *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID        LPTIM Base Msp DeInit Callback ID
+  *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID    Compare match Callback ID
+  *          @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+  *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID          External trigger event detection Callback ID
+  *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID    Compare register write complete Callback ID
+  *          @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+  *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID     Up-counting direction change Callback ID
+  *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID   Down-counting direction change Callback ID
+  *          @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID      Update event detection Callback ID
+  *          @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
+  *          @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
+  *          @arg @ref HAL_LPTIM_ERROR_CB_ID             Error  Callback ID
+  *          @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID        Input Capture Callback ID
+  *          @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID   Input Capture half complete Callback ID
+  *          @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID      Over Capture Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlptim,
+                                               HAL_LPTIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hlptim->State == HAL_LPTIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LPTIM_MSPINIT_CB_ID :
+        /* Legacy weak MspInit Callback */
+        hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+        break;
+
+      case HAL_LPTIM_MSPDEINIT_CB_ID :
+        /* Legacy weak Msp DeInit Callback */
+        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+        break;
+
+      case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+        /* Legacy weak Compare match Callback */
+        hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
+        break;
+
+      case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+        /* Legacy weak Auto-reload match Callback */
+        hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+        break;
+
+      case HAL_LPTIM_TRIGGER_CB_ID :
+        /* Legacy weak External trigger event detection Callback */
+        hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
+        break;
+
+      case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+        /* Legacy weak Compare register write complete Callback */
+        hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
+        break;
+
+      case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+        /* Legacy weak Auto-reload register write complete Callback */
+        hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+        break;
+
+      case HAL_LPTIM_DIRECTION_UP_CB_ID :
+        /* Legacy weak Up-counting direction change Callback */
+        hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
+        break;
+
+      case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+        /* Legacy weak Down-counting direction change Callback */
+        hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
+        break;
+
+      case HAL_LPTIM_UPDATE_EVENT_CB_ID :
+        /* Legacy weak Update event detection Callback */
+        hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
+        break;
+
+      case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
+        /* Legacy weak Repetition counter register write complete Callback */
+        hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
+        break;
+
+      case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
+        /* Legacy weak Update event half complete detection Callback */
+        hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
+        break;
+
+      case HAL_LPTIM_ERROR_CB_ID :
+        /* Legacy weak error Callback */
+        hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
+        break;
+
+      case HAL_LPTIM_IC_CAPTURE_CB_ID :
+        /* Legacy weak IC Capture Callback */
+        hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
+        break;
+
+      case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
+        /* Legacy weak IC Capture half complete Callback */
+        hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
+        break;
+
+      case HAL_LPTIM_OVER_CAPTURE_CB_ID :
+        /* Legacy weak IC over capture Callback */
+        hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hlptim->State == HAL_LPTIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LPTIM_MSPINIT_CB_ID :
+        /* Legacy weak MspInit Callback */
+        hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+        break;
+
+      case HAL_LPTIM_MSPDEINIT_CB_ID :
+        /* Legacy weak Msp DeInit Callback */
+        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Group5 Peripheral State functions
+  *  @brief   Peripheral State functions.
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the LPTIM handle state.
+  * @param  hlptim LPTIM handle
+  * @retval HAL state
+  */
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
+{
+  /* Return LPTIM handle state */
+  return hlptim->State;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+  * @{
+  */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  lptim pointer to a LPTIM_HandleTypeDef structure that contains
+  *                the configuration information for LPTIM module.
+  * @retval None
+  */
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
+{
+  /* Reset the LPTIM callback to the legacy weak callbacks */
+  lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;
+  lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+  lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;
+  lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;
+  lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+  lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;
+  lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;
+  lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
+  lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
+  lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
+  lptim->IC_CaptureCallback      = HAL_LPTIM_IC_CaptureCallback;
+  lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
+  lptim->IC_OverCaptureCallback  = HAL_LPTIM_IC_OverCaptureCallback;
+  lptim->ErrorCallback           = HAL_LPTIM_ErrorCallback;
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  LPTimer Wait for flag set
+  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+  *                the configuration information for LPTIM module.
+  * @param  flag   The lptim flag
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+{
+  HAL_StatusTypeDef result = HAL_OK;
+  uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
+  do
+  {
+    count--;
+    if (count == 0UL)
+    {
+      result = HAL_TIMEOUT;
+    }
+  } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+
+  return result;
+}
+
+/**
+  * @brief  LPTIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+  hlptim->ErrorCallback(hlptim);
+#else
+  HAL_LPTIM_ErrorCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  LPTIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+  hlptim->IC_CaptureCallback(hlptim);
+#else
+  HAL_LPTIM_IC_CaptureCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+  hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  LPTIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+  hlptim->IC_CaptureHalfCpltCallback(hlptim);
+#else
+  HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+  hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  LPTIM DMA Update event complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
+{
+  LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+  hlptim->UpdateEventCallback(hlptim);
+#else
+  HAL_LPTIM_UpdateEventCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+  hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  LPTIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hlptim->State = HAL_LPTIM_STATE_READY;
+
+  if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
+  {
+    hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+  hlptim->UpdateEventHalfCpltCallback(hlptim);
+#else
+  HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+  hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
+}
+/**
+  * @brief  LPTimer Output Compare 1 configuration
+  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+  *                the configuration information for LPTIM module.
+  * @param  sConfig The output configuration structure
+  * @retval None
+  */
+static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpcfgr;
+
+  tmpccmr1 = hlptim->Instance->CCMR1;
+  tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
+
+  if ((hlptim->Instance == LPTIM4) || (hlptim->Instance == LPTIM5))
+  {
+    tmpcfgr = hlptim->Instance->CFGR;
+    tmpcfgr &= ~LPTIM_CFGR_WAVPOL_Msk;
+    tmpcfgr |= sConfig->OCPolarity << LPTIM_CFGR_WAVPOL_Pos;
+
+    /* Write to CFGR register */
+    hlptim->Instance->CFGR = tmpcfgr;
+  }
+  else
+  {
+    tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
+  }
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
+
+  /* Write to CCR1 register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
+
+  /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Write to CCMR1 register */
+  hlptim->Instance->CCMR1 = tmpccmr1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  LPTimer Output Compare 2 configuration
+  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+  *                the configuration information for LPTIM module.
+  * @param  sConfig The output configuration structure
+  * @retval None
+  */
+static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
+{
+  uint32_t tmpccmr1;
+
+  tmpccmr1 = hlptim->Instance->CCMR1;
+  tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
+  tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
+
+  /* Enable the Peripheral */
+  __HAL_LPTIM_ENABLE(hlptim);
+
+  /* Clear flag */
+  __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
+
+  /* Write to CCR2 register */
+  __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
+
+  /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
+  if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Disable the Peripheral */
+  __HAL_LPTIM_DISABLE(hlptim);
+
+  /* Write to CCMR1 register */
+  hlptim->Instance->CCMR1 = tmpccmr1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  LPTimer Input Capture 1 configuration
+  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+  *                the configuration information for LPTIM module.
+  * @param  sConfig The input configuration structure
+  * @retval None
+  */
+static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpcfgr2;
+
+  tmpccmr1 = hlptim->Instance->CCMR1;
+  tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
+  tmpccmr1 |= sConfig->ICPrescaler |
+              sConfig->ICPolarity |
+              sConfig->ICFilter |
+              LPTIM_CCMR1_CC1SEL;
+
+  tmpcfgr2 = hlptim->Instance->CFGR2;
+  tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
+  tmpcfgr2 |= sConfig->ICInputSource;
+
+  /* Write to CCMR1 register */
+  hlptim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to CFGR2 register */
+  hlptim->Instance->CFGR2 = tmpcfgr2;
+}
+
+/**
+  * @brief  LPTimer Input Capture 2 configuration
+  * @param  hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+  *                the configuration information for LPTIM module.
+  * @param  sConfig The input configuration structure
+  * @retval None
+  */
+static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpcfgr2;
+
+  tmpccmr1 = hlptim->Instance->CCMR1;
+  tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
+  tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
+              (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
+              (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
+              LPTIM_CCMR1_CC2SEL;
+
+  tmpcfgr2 = hlptim->Instance->CFGR2;
+  tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
+  tmpcfgr2 |= sConfig->ICInputSource;
+
+  /* Write to CCMR1 register */
+  hlptim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to CFGR2 register */
+  hlptim->Instance->CFGR2 = tmpcfgr2;
+}
+
+/**
+  * @brief  Start the DMA data transfer.
+  * @param  hdma DMA handle
+  * @param  src The source memory Buffer address.
+  * @param  dst The destination memory Buffer address.
+  * @param  length The size of a source block transfer in byte.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+                                     uint32_t length)
+{
+  HAL_StatusTypeDef status;
+
+  /* Enable the DMA channel */
+  if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
+    {
+      /* Enable the DMA channel */
+      hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
+      hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src;
+      hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst;
+
+      status = HAL_DMAEx_List_Start_IT(hdma);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status =  HAL_DMA_Start_IT(hdma, src, dst, length);
+  }
+
+  return status;
+}
+/**
+  * @}
+  */
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
+
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ltdc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ltdc.c
new file mode 100644
index 000000000..0805258ee
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ltdc.c
@@ -0,0 +1,4073 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_ltdc.c
+  * @author  MCD Application Team
+  * @brief   LTDC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the LTDC peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+     [..]
+     The LTDC HAL driver can be used as follows:
+
+     (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef  hltdc;
+
+     (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API:
+         (##) Enable the LTDC interface clock
+         (##) NVIC configuration if you need to use interrupt process
+             (+++) Configure the LTDC interrupt priority
+             (+++) Enable the NVIC LTDC IRQ Channel
+
+     (#) Initialize the required configuration through the following parameters:
+         the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity,
+         Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function
+
+     *** Configuration ***
+     =========================
+     [..]
+     (#) Program the required configuration through the following parameters:
+         the pixel format, the blending factors, input alpha value, the window size
+         and the image size using HAL_LTDC_ConfigLayer() function for foreground
+         or/and background layer.
+
+     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
+         HAL_LTDC_EnableCLUT functions.
+
+     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
+
+     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
+         and HAL_LTDC_EnableColorKeying functions.
+
+     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
+         function
+
+     (#) If needed, reconfigure and change the pixel format value, the alpha value
+         value, the window size, the window position and the layer start address
+         for foreground or/and background layer using respectively the following
+         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
+         HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().
+
+     (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
+         This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
+         then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().
+
+         After calling the _NoReload functions to set different color/format/layer settings,
+         the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
+         Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
+         an immediate reload is required.
+         Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
+         the reload should be done in the next vertical blanking period,
+         this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
+
+
+     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
+
+     *** LTDC HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in LTDC HAL driver.
+
+      (+) __HAL_LTDC_ENABLE: Enable the LTDC.
+      (+) __HAL_LTDC_DISABLE: Disable the LTDC.
+      (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
+      (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
+      (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload  Layer Configuration.
+      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
+      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
+      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
+      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
+      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
+
+     [..]
+       (@) You can refer to the LTDC HAL driver header file for more useful macros
+
+
+     *** Callback registration ***
+     =============================================
+     [..]
+     The compilation define  USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use function HAL_LTDC_RegisterCallback() to register a callback.
+
+    [..]
+    Function HAL_LTDC_RegisterCallback() allows to register following callbacks:
+      (+) LineEventCallback   : LTDC Line Event Callback.
+      (+) ReloadEventCallback : LTDC Reload Event Callback.
+      (+) ErrorCallback       : LTDC Error Callback
+      (+) MspInitCallback     : LTDC MspInit.
+      (+) MspDeInitCallback   : LTDC MspDeInit.
+    [..]
+    This function takes as parameters the HAL peripheral handle, the callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle
+    and the callback ID.
+    [..]
+    This function allows to reset following callbacks:
+      (+) LineEventCallback   : LTDC Line Event Callback
+      (+) ReloadEventCallback : LTDC Reload Event Callback
+      (+) ErrorCallback       : LTDC Error Callback
+      (+) MspInitCallback     : LTDC MspInit
+      (+) MspDeInitCallback   : LTDC MspDeInit.
+
+    [..]
+    By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback().
+    Exception done for MspInit and MspDeInit functions that are
+    reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit()
+    only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
+    thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit()
+    or HAL_LTDC_Init() function.
+
+    [..]
+    When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available and all callbacks
+    are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+
+#if defined (LTDC)
+
+/** @defgroup LTDC LTDC
+  * @brief LTDC HAL module driver
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup LTDC_Private_Define LTDC Private Define
+  * @{
+  */
+#define LTDC_TIMEOUT_VALUE ((uint32_t)100U)  /* 100ms */
+#define LTDC_PIXEL_FORMAT_FLEX_ARGB               0x00CU       /*!< Flexible ARGB format LTDC pixel format*/
+#define LTDC_PIXEL_FORMAT_FLEX_YUV_COPLANAR       0x00DU       /*!< Flexible Co-planar format*/
+#define LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR     0x10DU       /*!< Flexible Semi planar format*/
+#define LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR     0x20DU       /*!< Flexible Full planar format*/
+#define LTDC_FLEXIBLE_PIXEL_FORMAT                0x007U       /*!< Flexible pixel format selection */
+#define LTDC_PITCH_SIGN_MSK                       0x40000000U  /*!< Mask to check Pitch sign  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* YUV to RGB conversion coefficients for BT601/709 Full/Reduced Luminance */
+static const uint32_t V2R[4] = {403, 459, 359, 409};
+static const uint32_t U2G[4] = {48, 55, 88, 100};
+static const uint32_t V2G[4] = {120, 136, 183, 208};
+static const uint32_t U2B[4] = {475, 541, 454, 516};
+
+/* Private function prototypes -----------------------------------------------*/
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc,  uint32_t Aux0Addr, uint32_t Aux1Addr, uint32_t Mirror,
+                           uint32_t LayerIdx);
+static void LTDC_SetCompositionConfig(LTDC_HandleTypeDef *hltdc,  uint32_t LayerIdx);
+static void LTDC_SetPredefFormat(LTDC_HandleTypeDef *hltdc,  uint32_t LayerIdx);
+static void LTDC_RetrieveUserConfig(LTDC_HandleTypeDef *hltdc, uint32_t *Mirror, uint32_t *Aux0Addr,
+                                    uint32_t *Aux1Addr, uint32_t LayerIdx);
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LTDC_Exported_Functions LTDC Exported Functions
+  * @{
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the LTDC
+      (+) De-initialize the LTDC
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
+{
+  uint32_t tmp;
+  uint32_t tmp1;
+
+  /* Check the LTDC peripheral state */
+  if (hltdc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+  assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
+  assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
+  assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
+  assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
+  assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
+  assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
+  assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
+  assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
+  assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
+  assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
+  assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
+  assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+  if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hltdc->Lock = HAL_UNLOCKED;
+
+    /* Reset the LTDC callback to the legacy weak callbacks */
+    hltdc->LineEventCallback   = HAL_LTDC_LineEventCallback;    /* Legacy weak LineEventCallback    */
+    hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback;  /* Legacy weak ReloadEventCallback  */
+    hltdc->ErrorCallback       = HAL_LTDC_ErrorCallback;        /* Legacy weak ErrorCallback        */
+
+    if (hltdc->MspInitCallback == NULL)
+    {
+      hltdc->MspInitCallback = HAL_LTDC_MspInit;
+    }
+    /* Init the low level hardware */
+    hltdc->MspInitCallback(hltdc);
+  }
+#else
+  if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hltdc->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_LTDC_MspInit(hltdc);
+  }
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the HS, VS, DE and PC polarity */
+  hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
+  hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
+                                     hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
+
+  /* Set Synchronization size */
+  tmp = (hltdc->Init.HorizontalSync << 16U);
+  WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync));
+
+  /* Set Accumulated Back porch */
+  tmp = (hltdc->Init.AccumulatedHBP << 16U);
+  WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP));
+
+  /* Set Accumulated Active Width */
+  tmp = (hltdc->Init.AccumulatedActiveW << 16U);
+  WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH));
+
+  /* Set Total Width */
+  tmp = (hltdc->Init.TotalWidth << 16U);
+  WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh));
+
+  /* Set the background color value */
+  tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
+  tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
+  hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
+  hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
+
+  /* Activate Global Reload for Layer 1 and Layer 2 */
+  WRITE_REG(LTDC_LAYER(hltdc, LTDC_LAYER_1)->RCR, LTDC_LxRCR_GRMSK);
+  WRITE_REG(LTDC_LAYER(hltdc, LTDC_LAYER_2)->RCR, LTDC_LxRCR_GRMSK);
+
+  /* Enable the Transfer Error and FIFO underrun interrupts */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
+
+  /* Enable LTDC by setting LTDCEN bit */
+  __HAL_LTDC_ENABLE(hltdc);
+
+  /* Initialize the error code */
+  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
+
+  /* Initialize the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initialize the LTDC peripheral.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
+{
+  uint32_t tickstart;
+
+  /* Check the LTDC peripheral state */
+  if (hltdc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+
+  /* Disable LTDC Layer 1 */
+  __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1);
+
+#if defined(LTDC_Layer2_BASE)
+  /* Disable LTDC Layer 2 */
+  __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2);
+#endif /* LTDC_Layer2_BASE */
+
+  /* Reload during vertical blanking period */
+  __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for VSYNC Interrupt */
+  while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE)
+    {
+      break;
+    }
+  }
+
+  /* Disable LTDC  */
+  __HAL_LTDC_DISABLE(hltdc);
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+  if (hltdc->MspDeInitCallback == NULL)
+  {
+    hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hltdc->MspDeInitCallback(hltdc);
+#else
+  /* DeInit the low level hardware */
+  HAL_LTDC_MspDeInit(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+  /* Initialize the error code */
+  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
+
+  /* Initialize the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the LTDC MSP.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-initialize the LTDC MSP.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User LTDC Callback
+  *         To be used instead of the weak predefined callback
+  * @param hltdc ltdc handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+  *          @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+  *          @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+  *          @ref @ref HAL_LTDC_WARNING_EVENT_CB_ID Warning Event Callback ID
+  *          @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+                                            pLTDC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  if (hltdc->State == HAL_LTDC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_LINE_EVENT_CB_ID :
+        hltdc->LineEventCallback = pCallback;
+        break;
+
+      case HAL_LTDC_RELOAD_EVENT_CB_ID :
+        hltdc->ReloadEventCallback = pCallback;
+        break;
+
+      case HAL_LTDC_ERROR_CB_ID :
+        hltdc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_LTDC_WARNING_EVENT_CB_ID:
+        hltdc->WarningEventCallback = pCallback;
+        break;
+
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hltdc);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an LTDC Callback
+  *         LTDC callback is redirected to the weak predefined callback
+  * @param hltdc ltdc handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+  *          @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+  *          @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_LTDC_WARNING_EVENT_CB_ID Warning Event Callback ID
+  *          @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  if (hltdc->State == HAL_LTDC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_LINE_EVENT_CB_ID :
+        hltdc->LineEventCallback = HAL_LTDC_LineEventCallback;      /* Legacy weak LineEventCallback    */
+        break;
+
+      case HAL_LTDC_RELOAD_EVENT_CB_ID :
+        hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback;  /* Legacy weak ReloadEventCallback  */
+        break;
+
+      case HAL_LTDC_ERROR_CB_ID :
+        hltdc->ErrorCallback       = HAL_LTDC_ErrorCallback;        /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_LTDC_WARNING_EVENT_CB_ID :
+        hltdc->WarningEventCallback = HAL_LTDC_WarningEventCallback;
+        break;
+
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback  */
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;              /* Legcay weak MspDeInit Callback     */
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hltdc->State == HAL_LTDC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_LTDC_MSPINIT_CB_ID :
+        hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback     */
+        break;
+
+      case HAL_LTDC_MSPDEINIT_CB_ID :
+        hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;              /* Legcay weak MspDeInit Callback     */
+        break;
+
+      default :
+        /* Update the error code */
+        hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hltdc);
+
+  return status;
+}
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Configure the LTDC Layer burst length
+  * @param  hltdc        Pointer to a LTDC_HandleTypeDef structure that contains
+  *                       the configuration information for the LTDC.
+  * @param  BurstLength  Burst length.
+  *                       This parameter can be a value between 1-16
+  * @param  LayerIdx     LTDC Layer index.
+  *                       This parameter can be one of the following values:
+  *                       LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigBurstLength(LTDC_HandleTypeDef *hltdc, uint32_t BurstLength, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_BURST_LENGTH(BurstLength));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the layer burst length configuration register */
+  LTDC_LAYER(hltdc, LayerIdx)->BLCR  &= ~(LTDC_LxBLCR_BL);
+  LTDC_LAYER(hltdc, LayerIdx)->BLCR  = BurstLength;
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief               Configure the LTDC Underrun Threshold.
+  * @param  hltdc        Pointer to a LTDC_HandleTypeDef structure that contains
+  *                       the configuration information for the LTDC.
+  * @param  Threshold    Threshold above which
+  *                       a FIFO underrun warning becomes a FIFO underrun error.
+  *                       This parameter can be a value between 0 - 0XFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigUnderrunThreshold(LTDC_HandleTypeDef *hltdc, uint16_t Threshold)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the Fifo Underrun Threshold register */
+  hltdc->Instance->FUTR &= ~(LTDC_FUTR_THRE);
+  hltdc->Instance->FUTR = (uint32_t) Threshold;
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides function allowing to:
+      (+) Handle LTDC interrupt request
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Handle LTDC interrupt request.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL status
+  */
+void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
+{
+#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  uint32_t isrflags = READ_REG(hltdc->Instance->ISR2);
+  uint32_t itsources = READ_REG(hltdc->Instance->IER2);
+#else
+  uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
+  uint32_t itsources = READ_REG(hltdc->Instance->IER);
+#endif /* __ARM_FEATURE_CMSE & __ARM_FEATURE_CMSE == 3U */
+
+
+  /* CRC Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_CRCIF) != 0U) && ((itsources & LTDC_IER_CRCIE) != 0U))
+  {
+    /* Disable the transfer Error interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_CRC);
+
+    /* Clear the crc flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_CRC);
+
+    /* Update error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_CRC;
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_ERROR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hltdc->ErrorCallback(hltdc);
+#else
+    /* Call legacy error callback*/
+    HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* Fifo Underrun Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
+  {
+    /* Disable the transfer Error interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
+
+    /* Clear the UK flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
+
+    /* Update error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_ERROR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hltdc->ErrorCallback(hltdc);
+#else
+    /* Call legacy error callback*/
+    HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* Transfer Error Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
+  {
+    /* Disable the transfer Error interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
+
+    /* Clear the transfer error flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
+
+    /* Update error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_ERROR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hltdc->ErrorCallback(hltdc);
+#else
+    /* Call legacy error callback*/
+    HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* FIFO underrun Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
+  {
+    /* Disable the FIFO underrun interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
+
+    /* Clear the FIFO underrun flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
+
+    /* Update error code */
+    hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_ERROR;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hltdc->ErrorCallback(hltdc);
+#else
+    /* Call legacy error callback*/
+    HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* FIFO underrun Warning Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_FUWIF) != 0U) && ((itsources & LTDC_IER_FUWIE) != 0U))
+  {
+    /* Disable the FIFO underrun interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FUW);
+
+    /* Clear the FIFO underrun flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FUW);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hltdc->WarningEventCallback(hltdc);
+#else
+    /* Call legacy error callback*/
+    HAL_LTDC_WarningEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* Line Interrupt management ************************************************/
+  if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
+  {
+    /* Disable the Line interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+    /* Clear the Line interrupt flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Line interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered Line Event callback */
+    hltdc->LineEventCallback(hltdc);
+#else
+    /*Call Legacy Line Event callback */
+    HAL_LTDC_LineEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+
+  /* Register reload Interrupt management ***************************************/
+  if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
+  {
+    /* Disable the register reload interrupt */
+    __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
+
+    /* Clear the register reload flag */
+    __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
+
+    /* Change LTDC state */
+    hltdc->State = HAL_LTDC_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hltdc);
+
+    /* Reload interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+    /*Call registered reload Event callback */
+    hltdc->ReloadEventCallback(hltdc);
+#else
+    /*Call Legacy Reload Event callback */
+    HAL_LTDC_ReloadEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Error LTDC callback.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Line Event callback.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_LineEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Reload Event callback.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  LTDC FIFO Uderrun Warning callback.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval None
+  */
+__weak void HAL_LTDC_WarningEventCallback(LTDC_HandleTypeDef *hltdc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hltdc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_LTDC_SErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the LTDC foreground or/and background parameters.
+      (+) Set the active layer.
+      (+) Configure the color keying.
+      (+) Configure the C-LUT.
+      (+) Enable / Disable the color keying.
+      (+) Enable / Disable the C-LUT.
+      (+) Update the layer position.
+      (+) Update the layer size.
+      (+) Update pixel format on the fly.
+      (+) Update transparency on the fly.
+      (+) Update address on the fly.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the LTDC Layer according to the specified
+  *         parameters in the LTDC_InitTypeDef and create the associated handle.
+  * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
+  *                    the configuration information for the Layer.
+  * @param  LayerIdx  LTDC Layer index.
+  *                    This parameter can be one of the following values:
+  *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Copy new layer configuration into handle structure */
+  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
+
+  /* Configure Predefined format */
+  LTDC_SetPredefFormat(hltdc, LayerIdx);
+
+  /* Configure composition and blending*/
+  LTDC_SetCompositionConfig(hltdc, LayerIdx);
+
+  /* Disable YUV format */
+  CLEAR_BIT(LTDC_LAYER(hltdc, LayerIdx)->PCR, LTDC_LxPCR_YCEN);
+
+  /* Configure the LTDC Layer */
+  LTDC_SetConfig(hltdc, 0U, 0U, LTDC_MIRROR_NONE, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the color keying.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  RGBValue  the color key value
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the default color values */
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
+  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Load the color lookup table.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  pCLUT     pointer to the color lookup table address.
+  * @param  CLUTSize  the color lookup table size.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize,
+                                      uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t counter;
+  const uint32_t *pcolorlut = pCLUT;
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  for (counter = 0U; (counter < CLUTSize); counter++)
+  {
+    if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
+    {
+      tmp  = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+    }
+    else
+    {
+      tmp  = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+    }
+
+    pcolorlut++;
+
+    /* Specifies the C-LUT address and RGB value */
+    LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;
+  }
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configures the gamma correction for the LTDC peripheral.
+  *
+  * This function sets up the gamma correction feature of the LTDC (Liquid Crystal Display Controller)
+  * peripheral. Gamma correction helps in adjusting the brightness of the output image. This function
+  * allows the configuration of the gamma curve by setting the values for ones, tenths, and the specific
+  * RGB component to be adjusted.
+  *
+  * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param GammaOnes Specifies the value for the ones place in the gamma correction factor.
+  *                  This parameter can be a value between 0 and 2.
+  * @param GammaTenths Specifies the value for the tenths place in the gamma correction factor.
+  *                    This parameter can be a value between 0 and 9 if GammaOnes > 0 else between 4 and 9.
+  * @param RGBComponent Specifies the RGB component to which the gamma correction is applied.
+  *                     This parameter can be one of the following values:
+  *                     @arg LTDC_RGB_COMPONENT_RED  : Gamma correction for the red component.
+  *                     @arg LTDC_RGB_COMPONENT_GREEN: Gamma correction for the green component.
+  *                     @arg LTDC_RGB_COMPONENT_BLUE : Gamma correction for the blue component.
+  *                     @arg LTDC_RGB_COMPONENT_ALL  : Gamma correction for all components.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigGammaCorrection(LTDC_HandleTypeDef *hltdc, uint32_t GammaOnes,
+                                                 uint32_t GammaTenths, uint32_t RGBComponent)
+{
+  const uint32_t gammaindex = (GammaOnes * 70U) + (GammaTenths  * 7U) - 28U;
+  uint8_t gammasegment;
+  const uint8_t GammaAdress[7] = {32, 64, 96, 128, 160, 192, 224};
+  /* Gamma Mapped coefficients for segments 1 to 7 */
+  const uint8_t GammaLUT[182] =
+  {
+    111, 147, 173, 194, 212, 228, 242,  /* Gamma = 0.4 */
+    90, 128, 156, 181, 202, 221, 239,   /* Gamma = 0.5 */
+    73, 111, 142, 169, 193, 215, 236,   /* Gamma = 0.6 */
+    60, 97, 129, 157, 184, 209, 233,    /* Gamma = 0.7 */
+    48, 84, 117, 147, 176, 203, 230,    /* Gamma = 0.8 */
+    39, 73, 106, 137, 168, 198, 227,    /* Gamma = 0.9 */
+    32, 64, 96, 128, 160, 192, 224,     /* Gamma = 1.0 */
+    26, 56, 87, 119, 153, 187, 221,     /* Gamma = 1.1 */
+    21, 49, 79, 112, 146, 181, 218,     /* Gamma = 1.2 */
+    17, 42, 72, 104, 139, 176, 215,     /* Gamma = 1.3 */
+    14, 37, 65, 97, 133, 171, 213,      /* Gamma = 1.4 */
+    11, 32, 59, 91, 127, 167, 210,      /* Gamma = 1.5 */
+    9, 28, 53, 85, 121, 162, 207,       /* Gamma = 1.6 */
+    7, 24, 48, 79, 115, 157, 205,       /* Gamma = 1.7 */
+    6, 21, 44, 74, 110, 153, 202,       /* Gamma = 1.8 */
+    5, 18, 40, 69, 105, 149, 199,       /* Gamma = 1.9 */
+    4, 16, 36, 64, 100, 145, 197,       /* Gamma = 2.0 */
+    3, 14, 33, 60, 96, 141, 194,        /* Gamma = 2.1 */
+    3, 12, 30, 56, 91, 137, 192,        /* Gamma = 2.2 */
+    2, 11, 27, 52, 87, 133, 189,        /* Gamma = 2.3 */
+    2, 9, 24, 49, 83, 129, 187,         /* Gamma = 2.4 */
+    1, 8, 22, 46, 80, 125, 184,         /* Gamma = 2.5 */
+    1, 7, 20, 42, 76, 122, 182,         /* Gamma = 2.6 */
+    1, 6, 18, 40, 72, 119, 180,         /* Gamma = 2.7 */
+    1, 5, 17, 37, 69, 115, 177,         /* Gamma = 2.8 */
+    1, 5, 15, 35, 66, 112, 175,         /* Gamma = 2.9 */
+  };
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_RGB_COMPONENT(RGBComponent));
+  assert_param(IS_LTDC_GAMMA_VALUE(GammaOnes, GammaTenths));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Set Gamma interpolated segments*/
+  hltdc->Instance->GCCR = RGBComponent ;
+  for (gammasegment = 0U; (gammasegment < 7U); gammasegment++)
+  {
+    hltdc->Instance->GCCR = RGBComponent | ((uint32_t) GammaAdress[gammasegment] << LTDC_GCCR_ADDR_Pos) |
+                            ((uint32_t) GammaLUT[gammasegment + gammaindex] << LTDC_GCCR_COMP_Pos);
+  }
+  hltdc->Instance->GCCR = RGBComponent | (0xFFU << LTDC_GCCR_COMP_Pos) | LTDC_GCCR_ADDR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color keying.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CKEN;
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color keying.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CKEN;
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color lookup table.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color lookup table.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable Dither.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable Dither by setting DTEN bit */
+  LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable Dither.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable Dither by setting DTEN bit */
+  LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enables the CRC generator on the LTDC peripheral.
+  *
+  * Activates the Cyclic Redundancy Check (CRC) generator for the LTDC peripheral. The CRC can be used
+  * to verify the integrity of the data processed by the LTDC. Once enabled, the CRC generator computes
+  * a CRC value on the configured frame and can be used for error checking purposes.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_EnableCRC(LTDC_HandleTypeDef *hltdc)
+{
+  uint32_t tickstart;
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable crc by setting CRCEN bit */
+  LTDC->GCR |= (uint32_t)LTDC_GCR_CRCEN;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for CRC computing */
+  while (READ_REG(hltdc->Instance->CCRCR) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE)
+    {
+      break;
+    }
+  }
+
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_CRC);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disables the CRC generator on the LTDC peripheral.
+  *
+  * Deactivates the Cyclic Redundancy Check (CRC) generator for the LTDC peripheral. This function
+  * stops the CRC computation on the data processed by the LTDC, which may be required when CRC
+  * validation is no longer needed.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DisableCRC(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_CRC);
+
+  /* Disable crc by clearing CRCEN bit */
+  LTDC->GCR &= ~(uint32_t)LTDC_GCR_CRCEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enables gamma correction on the LTDC peripheral.
+  *
+  * This function enables the gamma correction feature of the LTDC peripheral, which adjusts the
+  * luminance of the output image to improve visual quality. Gamma correction is applied according to
+  * the previously configured parameters.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_EnableGammaCorrection(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable gamma correction by setting GAMEN bit */
+  LTDC->GCR |= (uint32_t)LTDC_GCR_GAMEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable gamma correction.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval  HAL status
+  */
+
+HAL_StatusTypeDef HAL_LTDC_DisableGammaCorrection(LTDC_HandleTypeDef *hltdc)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable gamma correction by clearing GAMEN bit */
+  LTDC->GCR &= ~(uint32_t)LTDC_GCR_GAMEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Set the LTDC window size.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  XSize     LTDC Pixel per line
+  * @param  YSize     LTDC Line number
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
+{
+  uint32_t mirror = 0U;
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+
+  /* Check the parameters (Layers parameters)*/
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(XSize));
+  assert_param(IS_LTDC_CFBLNBR(YSize));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* update horizontal stop */
+  hltdc->LayerCfg[LayerIdx].WindowX1 = XSize + hltdc->LayerCfg[LayerIdx].WindowX0;
+
+  /* update vertical stop */
+  hltdc->LayerCfg[LayerIdx].WindowY1 = YSize + hltdc->LayerCfg[LayerIdx].WindowY0;
+
+  /* Reconfigures the color frame buffer pitch in byte */
+  hltdc->LayerCfg[LayerIdx].ImageWidth = XSize;
+
+  /* Reconfigures the frame buffer line number */
+  hltdc->LayerCfg[LayerIdx].ImageHeight = YSize;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, aux0Addr, aux1Addr, mirror, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window position.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  X0        LTDC window X offset
+  * @param  Y0        LTDC window Y offset
+  * @param  LayerIdx  LTDC Layer index.
+  *                         This parameter can be one of the following values:
+  *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(X0));
+  assert_param(IS_LTDC_CFBLNBR(Y0));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* update horizontal start/stop */
+  hltdc->LayerCfg[LayerIdx].WindowX0 = X0;
+  hltdc->LayerCfg[LayerIdx].WindowX1 = X0 + hltdc->LayerCfg[LayerIdx].ImageWidth;
+
+  /* update vertical start/stop */
+  hltdc->LayerCfg[LayerIdx].WindowY0 = Y0;
+  hltdc->LayerCfg[LayerIdx].WindowY1 = Y0 + hltdc->LayerCfg[LayerIdx].ImageHeight;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, aux0Addr, aux1Addr, mirror, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the pixel format.
+  * @param  hltdc        pointer to a LTDC_HandleTypeDef structure that contains
+  *                      the configuration information for the LTDC.
+  * @param  Pixelformat  new pixel format value.
+  * @param  LayerIdx     LTDC Layer index.
+  *                      This parameter can be one of the following values:
+  *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Reconfigure the pixel format */
+  hltdc->LayerCfg[LayerIdx].PixelFormat = Pixelformat;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, aux0Addr, aux1Addr, mirror, LayerIdx);
+
+  /* Set LTDC format */
+  LTDC_SetPredefFormat(hltdc, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the layer alpha value.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Alpha     new alpha value.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_ALPHA(Alpha));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Specifies the constant alpha value */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CACR, Alpha);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+/**
+  *
+  * @brief Reconfigure the memory address for a layer buffer in the LTDC peripheral.
+  *
+  * This function configures the memory address for a layer buffer that can contain either ARGB data or
+  * YUV co-planar data.
+  * This allows dynamic updating of the frame buffer address for the specified layer.
+  *
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Address   The memory address where the layer data (ARGB or YUV co-planar) is stored.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Reconfigure the Address */
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = Address;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, 0U, 0U, mirror, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+  *         that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+  *         layer for which we want to read and display on screen only a portion 320x240 taken in the center
+  *         of the buffer.
+  *         The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous
+  *         call to HAL_LTDC_ConfigLayer().
+  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+  *         pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+  * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
+  *                            the configuration information for the LTDC.
+  * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+  * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t pitchUpdate;
+  uint32_t pixelFormat;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* get LayerIdx used pixel format */
+  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+
+  if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    tmp = 4U;
+  }
+  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    tmp = 3U;
+  }
+  else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    tmp = 2U;
+  }
+  else
+  {
+    tmp = 1U;
+  }
+
+  pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
+
+  /* Clear previously set standard pitch */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+
+  /* Set the Reload type as immediate update of LTDC pitch configured above */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Set new line pitch value */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+
+  /* Set the Reload type as immediate update of LTDC pitch configured above */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Sets the expected CRC value for the LTDC peripheral.
+  *
+  * Programs the expected Cyclic Redundancy Check (CRC) value for comparison against the CRC
+  * generated by the LTDC peripheral. This can be used for data integrity verification during
+  * runtime.
+  *
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param ExpectedCRC The expected CRC value to be set for comparison. This is a 16-bit value.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetExpectedCRC(LTDC_HandleTypeDef *hltdc, uint16_t ExpectedCRC)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Set the expected crc value */
+  hltdc->Instance->ECRCR = ExpectedCRC;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Retrieves the computed CRC value from the LTDC peripheral.
+  *
+  * Obtains the CRC value computed by the LTDC peripheral for the current frame. This value can be
+  * used to verify the integrity of the data processed by the LTDC against a known CRC value.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration
+  *              information for the LTDC module.
+  * @param ComputedCRC Pointer to a uint16_t variable where the computed CRC value will be stored.
+  * @note  To get the computed CRC for the current frame (N), this function should be called at the start
+  *        of the first line of the next frame (N+1).
+  *        The CRC value will remain stable until frame (N+1) is fully displayed.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_GetComputedCRC(LTDC_HandleTypeDef *hltdc, uint16_t *pComputedCRC)
+{
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get the computed crc value */
+  *pComputedCRC = (uint16_t) hltdc->Instance->CCRCR;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Define the position of the line interrupt.
+  * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
+  *                 the configuration information for the LTDC.
+  * @param  Line    Line Interrupt Position.
+  * @note   User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LIPOS(Line));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable the Line interrupt */
+  __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
+
+  /* Set the Line Interrupt position */
+  LTDC->LIPCR = (uint32_t)Line;
+
+  /* Enable the Line interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reload LTDC Layers configuration.
+  * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  ReloadType This parameter can be one of the following values :
+  *                      LTDC_RELOAD_IMMEDIATE : Immediate Reload
+  *                      LTDC_RELOAD_VERTICAL_BLANKING  : Reload in the next Vertical Blanking
+  * @note   User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef  HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_RELOAD(ReloadType));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable the Reload interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
+
+  /* Apply Reload type */
+  hltdc->Instance->SRCR = ReloadType;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Reloads configuration for a specific layer of the LTDC peripheral.
+  *
+  * This function triggers a reload of the layer configuration for the LTDC peripheral. The type of
+  * reload operation can be immediate or vertical blanking, as specified by the ReloadType parameter.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration
+  *              information for the LTDC module.
+  * @param ReloadType Specifies the type of reload operation. This parameter can be one of the
+  *                   following values:
+  *                   - LTDC_RELOAD_IMMEDIATE: Perform an immediate reload.
+  *                   - LTDC_RELOAD_VERTICAL_BLANKING: Perform the reload during the vertical blanking
+  *                     period.
+  * @param LayerIdx Specifies the index of the layer to be reloaded. This parameter can be one of the
+  *                 following values:
+  *                 - LTDC_LAYER_1: Reload configuration for layer 1.
+  *                 - LTDC_LAYER_2: Reload configuration for layer 2.
+  * @note   User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ReloadLayer(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_RELOAD(ReloadType));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable the Reload interrupt */
+  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
+
+  /* Apply Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, ReloadType | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Sets the display output format for the LTDC peripheral.
+  *
+  * Configures the LTDC peripheral to output in a specified format. This function allows for the
+  * selection of different color encoding formats, including RGB and YUV/YVU with specific conversion
+  * standards.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration
+  *              information for the LTDC module.
+  * @param Display Specifies the display output format to be selected. This parameter can be one of
+  *                the following values:
+  *                - LTDC_OUT_RGB: Output in RGB format.
+  *                - LTDC_OUT_YUV_HDTV: Output in YUV format using BT.709 conversion (HDTV standard).
+  *                - LTDC_OUT_YUV_SDTV: Output in YUV format using BT.601 conversion (SDTV standard).
+  *                - LTDC_OUT_YVU_HDTV: Output in YVU format using BT.709 conversion (HDTV standard).
+  *                - LTDC_OUT_YVU_SDTV: Output in YVU format using BT.601 conversion (SDTV standard).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetOutputDisplay(LTDC_HandleTypeDef *hltdc, uint32_t Display)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_DISPLAY(Display));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Configure the output format */
+  hltdc->Instance->EDCR = Display;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the LTDC Layer according to the specified without reloading
+  *         parameters in the LTDC_InitTypeDef and create the associated handle.
+  *         Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
+  * @param  hltdc      pointer to a LTDC_HandleTypeDef structure that contains
+  *                    the configuration information for the LTDC.
+  * @param  pLayerCfg  pointer to a LTDC_LayerCfgTypeDef structure that contains
+  *                    the configuration information for the Layer.
+  * @param  LayerIdx   LTDC Layer index.
+  *                    This parameter can be one of the following values:
+  *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+                                                uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
+  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
+  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
+  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
+  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
+  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
+  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
+  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
+  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Copy new layer configuration into handle structure */
+  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
+
+  /* Configure Predefined format */
+  LTDC_SetPredefFormat(hltdc, LayerIdx);
+
+  /* Configure composition and blending*/
+  LTDC_SetCompositionConfig(hltdc, LayerIdx);
+
+  /* Configure the LTDC Layer */
+  LTDC_SetConfig(hltdc, 0U, 0U, LTDC_MIRROR_NONE, LayerIdx);
+
+  /* Initialize the LTDC state*/
+  hltdc->State  = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window size without reloading.
+  *         Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  XSize     LTDC Pixel per line
+  * @param  YSize     LTDC Line number
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+                                                  uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters (Layers parameters)*/
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(XSize));
+  assert_param(IS_LTDC_CFBLNBR(YSize));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* update horizontal stop */
+  hltdc->LayerCfg[LayerIdx].WindowX1 = XSize + hltdc->LayerCfg[LayerIdx].WindowX0;
+
+  /* update vertical stop */
+  hltdc->LayerCfg[LayerIdx].WindowY1 = YSize + hltdc->LayerCfg[LayerIdx].WindowY0;
+
+  /* Reconfigures the color frame buffer pitch in byte */
+  hltdc->LayerCfg[LayerIdx].ImageWidth = XSize;
+
+  /* Reconfigures the frame buffer line number */
+  hltdc->LayerCfg[LayerIdx].ImageHeight = YSize;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, aux0Addr, aux1Addr, mirror, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the LTDC window position without reloading.
+  *         Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  X0        LTDC window X offset
+  * @param  Y0        LTDC window Y offset
+  * @param  LayerIdx  LTDC Layer index.
+  *                         This parameter can be one of the following values:
+  *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+                                                      uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_CFBLL(X0));
+  assert_param(IS_LTDC_CFBLNBR(Y0));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* update horizontal start/stop */
+  hltdc->LayerCfg[LayerIdx].WindowX0 = X0;
+  hltdc->LayerCfg[LayerIdx].WindowX1 = X0 + hltdc->LayerCfg[LayerIdx].ImageWidth;
+
+  /* update vertical start/stop */
+  hltdc->LayerCfg[LayerIdx].WindowY0 = Y0;
+  hltdc->LayerCfg[LayerIdx].WindowY1 = Y0 + hltdc->LayerCfg[LayerIdx].ImageHeight;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, aux0Addr, aux1Addr, mirror, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the pixel format without reloading.
+  *         Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
+  * @param  hltdc        pointer to a LTDC_HandleTypeDfef structure that contains
+  *                      the configuration information for the LTDC.
+  * @param  Pixelformat  new pixel format value.
+  * @param  LayerIdx     LTDC Layer index.
+  *                      This parameter can be one of the following values:
+  *                      LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Reconfigure the pixel format */
+  hltdc->LayerCfg[LayerIdx].PixelFormat = Pixelformat;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, aux0Addr, aux1Addr, mirror, LayerIdx);
+
+  /* Set LTDC format */
+  LTDC_SetPredefFormat(hltdc, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the layer alpha value without reloading.
+  *         Variant of the function HAL_LTDC_SetAlpha without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Alpha     new alpha value.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_ALPHA(Alpha));
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Specifies the constant alpha value */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CACR, Alpha);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reconfigure the frame buffer Address without reloading.
+  *         Variant of the function HAL_LTDC_SetAddress without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  Address   new address value.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Reconfigure the Address */
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = Address;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, 0, 0, mirror, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+  *         that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+  *         layer for which we want to read and display on screen only a portion 320x240 taken in the center
+  *         of the buffer.
+  *         The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by
+  *         previous call to HAL_LTDC_ConfigLayer().
+  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+  *         pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+  *         Variant of the function HAL_LTDC_SetPitch without immediate reload.
+  * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
+  *                            the configuration information for the LTDC.
+  * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+  * @param  LayerIdx           LTDC layer index concerned by the modification of line pitch.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t pitchUpdate;
+  uint32_t pixelFormat;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* get LayerIdx used pixel format */
+  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
+
+  if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+  {
+    tmp = 4U;
+  }
+  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
+  {
+    tmp = 3U;
+  }
+  else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+           (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+  {
+    tmp = 2U;
+  }
+  else
+  {
+    tmp = 1U;
+  }
+
+  pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
+
+  /* Clear previously set standard pitch */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
+
+  /* Set new line pitch value */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color keying without reloading.
+  *         Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CKEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color keying without reloading.
+  *         Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color keying by setting COLKEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CKEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the color lookup table without reloading.
+  *         Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the color lookup table without reloading.
+  *         Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Disable LTDC color lookup table by setting CLUTEN bit */
+  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief    Peripheral State and Errors functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the LTDC handle state.
+      (+) Get the LTDC handle error code.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the LTDC handle state.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *                the configuration information for the LTDC.
+  * @retval HAL state
+  */
+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc)
+{
+  return hltdc->State;
+}
+
+/**
+  * @brief  Return the LTDC handle error code.
+  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains
+  *               the configuration information for the LTDC.
+  * @retval LTDC Error Code
+  */
+uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc)
+{
+  return hltdc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup LTDC_Private_Functions LTDC Private Functions
+  * @{
+  */
+
+
+/**
+  * @brief Reconfigure the full planar memory addresses for a YUV layer in the LTDC peripheral.
+  *
+  * Configures the memory addresses for the Y, U, and V planes of a full planar YUV layer. This function
+  * is used when the Layer is operating in a full planar mode, where the Y, U, and V components are stored in
+  * separate memory areas. It allows for dynamic updating of the frame buffer addresses.
+  *
+  * @note This function is applicable only to LTDC_LAYER_1.
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pYUVFullPlanarAddress Pointer to a LTDC_LayerFlexYUVFullPlanarTypeDef structure that holds
+  *                              the memory addresses for the Y, U, and V planes.
+  * @param  LayerIdx  Specifies the index of the layer being configured. For this function, the only
+  *                 valid value is LTDC_LAYER_1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetFullPlanarAddress(LTDC_HandleTypeDef *hltdc,
+                                                LTDC_LayerFlexYUVFullPlanarTypeDef *pYUVFullPlanarAddress,
+                                                uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PLANAR_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Update LayerCfg structure with required parameters */
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pYUVFullPlanarAddress->YUVFullPlanarAddress.YAddress;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pYUVFullPlanarAddress->YUVFullPlanarAddress.UAddress,
+                 pYUVFullPlanarAddress->YUVFullPlanarAddress.VAddress, mirror, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Reconfigure the semi-planar memory addresses for a YUV layer in the LTDC peripheral.
+  *
+  * Configures the memory addresses for the Y plane and the combined U/V plane of a semi-planar YUV layer.
+  * This function is used when the Layer is operating in a semi-planar mode, where the Y component and the
+  * U/V components are stored in separate memory areas, allowing dynamic updates of the frame buffer addresses.
+  *
+  * @note This function is applicable only to LTDC_LAYER_1.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pYUVSemiPlanarAddress Pointer to an LTDC_LayerFlexYUVSemiPlanarTypeDef structure that holds
+  *                              the memory addresses for the Y plane and the combined U/V plane.
+  * @param LayerIdx Specifies the index of the layer being configured. For this function, the only
+  *                 valid value is LTDC_LAYER_1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetSemiPlanarAddress(LTDC_HandleTypeDef *hltdc,
+                                                LTDC_LayerFlexYUVSemiPlanarTypeDef *pYUVSemiPlanarAddress,
+                                                uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PLANAR_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Update handle */
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pYUVSemiPlanarAddress->YUVSemiPlanarAddress.YAddress;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pYUVSemiPlanarAddress->YUVSemiPlanarAddress.UVAddress, 0, mirror, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Reconfigure the full planar memory addresses for a YUV layer in the LTDC peripheral with no reload.
+  *
+  * Configures the memory addresses for the Y, U, and V planes of a full planar YUV layer. This function
+  * is used when the Layer is operating in a full planar mode, where the Y, U, and V components are stored in
+  * separate memory areas. It allows for dynamic updating of the frame buffer addresses.
+  *
+  * @note This function is applicable only to LTDC_LAYER_1.
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pYUVFullPlanarAddress Pointer to a LTDC_LayerFlexYUVFullPlanarTypeDef structure that holds
+  *                              the memory addresses for the Y, U, and V planes.
+  * @param  LayerIdx  Specifies the index of the layer being configured. For this function, the only
+  *                 valid value is LTDC_LAYER_1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetFullPlanarAddress_NoReload(LTDC_HandleTypeDef *hltdc,
+                                                         LTDC_LayerFlexYUVFullPlanarTypeDef *pYUVFullPlanarAddress,
+                                                         uint32_t LayerIdx)
+{
+  uint32_t mirror = 0U;
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PLANAR_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Update LayerCfg structure with required parameters */
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pYUVFullPlanarAddress->YUVFullPlanarAddress.YAddress;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pYUVFullPlanarAddress->YUVFullPlanarAddress.UAddress,
+                 pYUVFullPlanarAddress->YUVFullPlanarAddress.VAddress, mirror, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Reconfigure the semi-planar memory addresses for a YUV layer in the LTDC peripheral without reload.
+  *
+  * Configures the memory addresses for the Y plane and the combined U/V plane of a semi-planar YUV layer.
+  * This function is used when the Layer is operating in a semi-planar mode, where the Y component and the
+  * U/V components are stored in separate memory areas, allowing dynamic updates of the frame buffer addresses.
+  *
+  * @note This function is applicable only to LTDC_LAYER_1.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pYUVSemiPlanarAddress Pointer to an LTDC_LayerFlexYUVSemiPlanarTypeDef structure that holds
+  *                              the memory addresses for the Y plane and the combined U/V plane.
+  * @param LayerIdx Specifies the index of the layer being configured. For this function, the only
+  *                 valid value is LTDC_LAYER_1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_SetSemiPlanarAddress_NoReload(LTDC_HandleTypeDef *hltdc,
+                                                         LTDC_LayerFlexYUVSemiPlanarTypeDef *pYUVSemiPlanarAddress,
+                                                         uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_PLANAR_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Update handle */
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pYUVSemiPlanarAddress->YUVSemiPlanarAddress.YAddress;
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pYUVSemiPlanarAddress->YUVSemiPlanarAddress.UVAddress, 0, mirror, LayerIdx);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configures the mirroring effect for a specific layer in the LTDC peripheral.
+  *
+  * This function sets the mirroring effect for the specified layer of the LTDC. It can configure the
+  * layer to mirror the image horizontally, vertically, both horizontally and vertically, or not at all.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param Mirror Specifies the mirroring effect to be applied. This parameter can be one of the
+  *               following values:
+  *               - LTDC_MIRROR_HORIZONTAL: Apply horizontal mirroring to the layer.
+  *               - LTDC_MIRROR_VERTICAL: Apply vertical mirroring to the layer.
+  *               - LTDC_MIRROR_HORIZONTAL_VERTICAL: Apply both horizontal and vertical mirroring to
+  *                 the layer.
+  *               - LTDC_MIRROR_NONE: No mirroring is applied to the layer.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigMirror(LTDC_HandleTypeDef *hltdc, uint32_t Mirror, uint32_t LayerIdx)
+{
+  uint32_t aux0Addr = 0U;
+  uint32_t aux1Addr = 0U;
+  uint32_t mirror = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Get previous user configuration */
+  LTDC_RetrieveUserConfig(hltdc, &mirror, &aux0Addr, &aux1Addr, LayerIdx);
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, aux0Addr, aux1Addr, Mirror, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configures the layer parameters for ARGB format in the LTDC peripheral.
+  *
+  * This function sets up the layer-specific parameters for a layer that will handle ARGB pixel data.
+  * It configures various aspects such as pixel format, blending factors, color frame buffer address,
+  * color keying, and more, according to the LTDC_LayerFlexARGBTypeDef structure.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pLayerFlexARGB Pointer to an LTDC_LayerFlexARGBTypeDef structure that specifies the layer
+  *                       configuration parameters for the ARGB format.
+  * @param LayerIdx Specifies the index of the layer being configured. This parameter can be one of the
+  *                 following values:
+  *                 - LTDC_LAYER_1: Configuration for layer 1.
+  *                 - LTDC_LAYER_2: Configuration for layer 2.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexARGB(LTDC_HandleTypeDef *hltdc,
+                                               const LTDC_LayerFlexARGBTypeDef *pLayerFlexARGB, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_ARGB_COMPONENT_WIDTH(pLayerFlexARGB->FlexARGB.RedWidth));
+  assert_param(IS_LTDC_ARGB_COMPONENT_WIDTH(pLayerFlexARGB->FlexARGB.GreenWidth));
+  assert_param(IS_LTDC_ARGB_COMPONENT_WIDTH(pLayerFlexARGB->FlexARGB.BlueWidth));
+  assert_param(IS_LTDC_ARGB_COMPONENT_POSITION(pLayerFlexARGB->FlexARGB.RedPos));
+  assert_param(IS_LTDC_ARGB_COMPONENT_POSITION(pLayerFlexARGB->FlexARGB.GreenPos));
+  assert_param(IS_LTDC_ARGB_COMPONENT_POSITION(pLayerFlexARGB->FlexARGB.BluePos));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* update in the handler */
+  hltdc->LayerCfg[LayerIdx].WindowX0 = pLayerFlexARGB->Layer.WindowX0;
+  hltdc->LayerCfg[LayerIdx].WindowX1 = pLayerFlexARGB->Layer.WindowX1;
+  hltdc->LayerCfg[LayerIdx].WindowY0 = pLayerFlexARGB->Layer.WindowY0;
+  hltdc->LayerCfg[LayerIdx].WindowY1 = pLayerFlexARGB->Layer.WindowY1;
+  hltdc->LayerCfg[LayerIdx].PixelFormat = LTDC_PIXEL_FORMAT_FLEX_ARGB;
+  hltdc->LayerCfg[LayerIdx].Alpha = pLayerFlexARGB->Layer.Alpha;
+  hltdc->LayerCfg[LayerIdx].Alpha0 = pLayerFlexARGB->Layer.Alpha0;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor1 = pLayerFlexARGB->Layer.BlendingFactor1;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor2 = pLayerFlexARGB->Layer.BlendingFactor2;
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pLayerFlexARGB->ARGBAddress;
+  hltdc->LayerCfg[LayerIdx].ImageWidth = pLayerFlexARGB->Layer.ImageWidth;
+  hltdc->LayerCfg[LayerIdx].ImageHeight = pLayerFlexARGB->Layer.ImageHeight;
+
+  /* Configure Flexible ARGB */
+  LTDC_LAYER(hltdc, LayerIdx)->PFCR = 0x7U;
+  LTDC_LAYER(hltdc, LayerIdx)->FPF0R = (pLayerFlexARGB->FlexARGB.RedWidth << LTDC_LxFPF0R_RLEN_Pos) |
+                                       (pLayerFlexARGB->FlexARGB.RedPos << LTDC_LxFPF0R_RPOS_Pos) |
+                                       (pLayerFlexARGB->FlexARGB.AlphaWidth << LTDC_LxFPF0R_ALEN_Pos) |
+                                       pLayerFlexARGB->FlexARGB.AlphaPos;
+  LTDC_LAYER(hltdc, LayerIdx)->FPF1R = (pLayerFlexARGB->FlexARGB.PixelSize << LTDC_LxFPF1R_PSIZE_Pos) |
+                                       (pLayerFlexARGB->FlexARGB.BlueWidth << LTDC_LxFPF1R_BLEN_Pos) |
+                                       (pLayerFlexARGB->FlexARGB.BluePos << LTDC_LxFPF1R_BPOS_Pos) |
+                                       (pLayerFlexARGB->FlexARGB.GreenWidth << LTDC_LxFPF1R_GLEN_Pos) |
+                                       (pLayerFlexARGB->FlexARGB.GreenPos);
+
+  /* Set composition parameters */
+  LTDC_SetCompositionConfig(hltdc, LayerIdx);
+
+
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+  /* Disable YUV mode */
+  MODIFY_REG(LTDC_LAYER(hltdc, LayerIdx)->PCR, LTDC_LxPCR_YCEN, 0U);
+
+  LTDC_SetConfig(hltdc, 0, 0, LTDC_MIRROR_NONE, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configures the layer parameters for YUV co-planar format in the LTDC peripheral.
+  *
+  * This function sets up the layer-specific parameters for a layer that will handle YUV co-planar pixel
+  * data. It allows configuration of the layer to handle pixel data where the Y component is stored
+  * separately from the UV components, which are stored together. The configuration parameters include
+  * pixel format, blending factors, color frame buffer addresses, and more, as defined in the
+  * LTDC_LayerFlexYUVCoPlanarTypeDef structure.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pLayerFlexYUVCoPlanar Pointer to an LTDC_LayerFlexYUVCoPlanarTypeDef structure that
+  *                              specifies the layer configuration parameters for the YUV co-planar format.
+  * @param LayerIdx Specifies the index of the layer being configured. This parameter can be one of the
+  *                 following values:
+  *                 - LTDC_LAYER_1: Configuration for layer 1.
+  *                 - LTDC_LAYER_2: Configuration for layer 2.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexYUVCoPlanar(LTDC_HandleTypeDef *hltdc,
+                                                      const LTDC_LayerFlexYUVCoPlanarTypeDef *pLayerFlexYUVCoPlanar,
+                                                      uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_Y_RANHGE(pLayerFlexYUVCoPlanar->FlexYUV.LuminanceRescale));
+  assert_param(IS_LTDC_Y_ORDER(pLayerFlexYUVCoPlanar->FlexYUV.LuminanceOrder));
+  assert_param(IS_LTDC_YUV_ORDER(pLayerFlexYUVCoPlanar->FlexYUV.YUVOrder));
+  assert_param(IS_LTDC_UV_ORDER(pLayerFlexYUVCoPlanar->FlexYUV.ChrominanceOrder));
+  assert_param(IS_LTDC_YUV2RGBCONVERTOR(pLayerFlexYUVCoPlanar->ColorConverter));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* update the handler */
+  hltdc->LayerCfg[LayerIdx].WindowX0 = pLayerFlexYUVCoPlanar->Layer.WindowX0;
+  hltdc->LayerCfg[LayerIdx].WindowX1 = pLayerFlexYUVCoPlanar->Layer.WindowX1;
+  hltdc->LayerCfg[LayerIdx].WindowY0 = pLayerFlexYUVCoPlanar->Layer.WindowY0;
+  hltdc->LayerCfg[LayerIdx].WindowY1 = pLayerFlexYUVCoPlanar->Layer.WindowY1;
+  hltdc->LayerCfg[LayerIdx].PixelFormat = LTDC_PIXEL_FORMAT_FLEX_YUV_COPLANAR;
+  hltdc->LayerCfg[LayerIdx].Alpha = pLayerFlexYUVCoPlanar->Layer.Alpha;
+  hltdc->LayerCfg[LayerIdx].Alpha0 = pLayerFlexYUVCoPlanar->Layer.Alpha0;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor1 = pLayerFlexYUVCoPlanar->Layer.BlendingFactor1;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor2 = pLayerFlexYUVCoPlanar->Layer.BlendingFactor2;
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pLayerFlexYUVCoPlanar->YUVAddress;
+  hltdc->LayerCfg[LayerIdx].ImageWidth = pLayerFlexYUVCoPlanar->Layer.ImageWidth;
+  hltdc->LayerCfg[LayerIdx].ImageHeight = pLayerFlexYUVCoPlanar->Layer.ImageHeight;
+
+  /* Set composition parameters */
+  LTDC_SetCompositionConfig(hltdc, LayerIdx);
+
+  /* Set flexible YUV format */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->PCR, LTDC_LxPCR_YCEN | (pLayerFlexYUVCoPlanar->FlexYUV.ChrominanceOrder) |
+            (LTDC_PIXEL_FORMAT_FLEX_YUV_COPLANAR >> LTDC_LxPCR_YCM_Pos) |
+            (pLayerFlexYUVCoPlanar->FlexYUV.YUVOrder) |
+            (pLayerFlexYUVCoPlanar->FlexYUV.LuminanceOrder) | pLayerFlexYUVCoPlanar->FlexYUV.LuminanceRescale);
+
+  /* Set YUV to RGB conversion */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CYR0R, \
+            (U2B[pLayerFlexYUVCoPlanar->ColorConverter] << LTDC_LxCYR0R_CB2B_Pos) |
+            V2R[pLayerFlexYUVCoPlanar->ColorConverter]);
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CYR1R, (V2G[pLayerFlexYUVCoPlanar->ColorConverter]) |
+            (U2G[pLayerFlexYUVCoPlanar->ColorConverter] << LTDC_LxCYR1R_CB2G_Pos));
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, 0, 0, LTDC_MIRROR_NONE, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configures the layer parameters for YUV semi-planar format in the LTDC peripheral.
+  *
+  * This function sets up the layer-specific parameters for a layer that will handle YUV semi-planar pixel
+  * data. It configures the layer to process pixel data where the Y component is stored separately from
+  * the UV components, which are stored together in a semi-planar format. The configuration parameters
+  * include pixel format, blending factors, color frame buffer addresses, and more, as defined in the
+  * LTDC_LayerFlexYUVSemiPlanarTypeDef structure.
+  *
+  * @note This function is applicable only to LTDC_LAYER_1.
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pLayerFlexYUVSemiPlanar Pointer to an LTDC_LayerFlexYUVSemiPlanarTypeDef structure that
+  *                                specifies the layer configuration parameters for the YUV semi-planar
+  *                                format.
+  * @param LayerIdx Specifies the index of the layer being configured. For this function, the only
+  *                 valid value is LTDC_LAYER_1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexYUVSemiPlanar(LTDC_HandleTypeDef *hltdc,
+                                                        LTDC_LayerFlexYUVSemiPlanarTypeDef *pLayerFlexYUVSemiPlanar,
+                                                        uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_PLANAR_LAYER(LayerIdx));
+  assert_param(IS_LTDC_Y_RANHGE(pLayerFlexYUVSemiPlanar->FlexYUV.LuminanceRescale));
+  assert_param(IS_LTDC_Y_ORDER(pLayerFlexYUVSemiPlanar->FlexYUV.LuminanceOrder));
+  assert_param(IS_LTDC_YUV_ORDER(pLayerFlexYUVSemiPlanar->FlexYUV.YUVOrder));
+  assert_param(IS_LTDC_UV_ORDER(pLayerFlexYUVSemiPlanar->FlexYUV.ChrominanceOrder));
+  assert_param(IS_LTDC_YUV2RGBCONVERTOR(pLayerFlexYUVSemiPlanar->ColorConverter));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* update the handler */
+  hltdc->LayerCfg[LayerIdx].WindowX0 = pLayerFlexYUVSemiPlanar->Layer.WindowX0;
+  hltdc->LayerCfg[LayerIdx].WindowX1 = pLayerFlexYUVSemiPlanar->Layer.WindowX1;
+  hltdc->LayerCfg[LayerIdx].WindowY0 = pLayerFlexYUVSemiPlanar->Layer.WindowY0;
+  hltdc->LayerCfg[LayerIdx].WindowY1 = pLayerFlexYUVSemiPlanar->Layer.WindowY1;
+  hltdc->LayerCfg[LayerIdx].PixelFormat = LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR;
+  hltdc->LayerCfg[LayerIdx].Alpha = pLayerFlexYUVSemiPlanar->Layer.Alpha;
+  hltdc->LayerCfg[LayerIdx].Alpha0 = pLayerFlexYUVSemiPlanar->Layer.Alpha0;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor1 = pLayerFlexYUVSemiPlanar->Layer.BlendingFactor1;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor2 = pLayerFlexYUVSemiPlanar->Layer.BlendingFactor2;
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pLayerFlexYUVSemiPlanar->YUVSemiPlanarAddress.YAddress;
+  hltdc->LayerCfg[LayerIdx].ImageWidth = pLayerFlexYUVSemiPlanar->Layer.ImageWidth;
+  hltdc->LayerCfg[LayerIdx].ImageHeight = pLayerFlexYUVSemiPlanar->Layer.ImageHeight;
+
+  /* Set composition parameters */
+  LTDC_SetCompositionConfig(hltdc, LayerIdx);
+
+  /* Set flexible YUV format */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->PCR, LTDC_LxPCR_YCEN | pLayerFlexYUVSemiPlanar->FlexYUV.ChrominanceOrder |
+            (LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR >> LTDC_LxPCR_YCM_Pos) |
+            pLayerFlexYUVSemiPlanar->FlexYUV.YUVOrder |
+            pLayerFlexYUVSemiPlanar->FlexYUV.LuminanceOrder | pLayerFlexYUVSemiPlanar->FlexYUV.LuminanceRescale);
+
+  /* Set YUV to RGB conversion */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CYR0R, \
+            (U2B[pLayerFlexYUVSemiPlanar->ColorConverter] << LTDC_LxCYR0R_CB2B_Pos) |
+            V2R[pLayerFlexYUVSemiPlanar->ColorConverter]);
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CYR1R, (V2G[pLayerFlexYUVSemiPlanar->ColorConverter]) |
+            (U2G[pLayerFlexYUVSemiPlanar->ColorConverter] << LTDC_LxCYR1R_CB2G_Pos));
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerFlexYUVSemiPlanar->YUVSemiPlanarAddress.UVAddress, 0, LTDC_MIRROR_NONE, LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configures the layer parameters for YUV full-planar format in the LTDC peripheral.
+  *
+  * This function sets up the layer-specific parameters for a layer that will handle YUV full-planar pixel
+  * data. It configures the layer to process pixel data where the Y component is stored separately from
+  * the UV components, which are stored together in a full-planar format. The configuration parameters
+  * include pixel format, blending factors, color frame buffer addresses, and more, as defined in the
+  * LTDC_LayerFlexYUVfullPlanarTypeDef structure.
+  *
+  *  @note This function is applicable only to LTDC_LAYER_1.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param pLayerFlexYUVfullPlanar Pointer to an LTDC_LayerFlexYUVfullPlanarTypeDef structure that
+  *                                specifies the layer configuration parameters for the YUV full-planar
+  *                                format.
+  * @param LayerIdx Specifies the index of the layer being configured. For this function, the only
+  *                 valid value is LTDC_LAYER_1.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigLayerFlexYUVFullPlanar(LTDC_HandleTypeDef *hltdc,
+                                                        LTDC_LayerFlexYUVFullPlanarTypeDef *pLayerFlexYUVFullPlanar,
+                                                        uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_PLANAR_LAYER(LayerIdx));
+  assert_param(IS_LTDC_Y_RANHGE(pLayerFlexYUVFullPlanar->FlexYUV.LuminanceRescale));
+  assert_param(IS_LTDC_Y_ORDER(pLayerFlexYUVFullPlanar->FlexYUV.LuminanceOrder));
+  assert_param(IS_LTDC_YUV_ORDER(pLayerFlexYUVFullPlanar->FlexYUV.YUVOrder));
+  assert_param(IS_LTDC_UV_ORDER(pLayerFlexYUVFullPlanar->FlexYUV.ChrominanceOrder));
+  assert_param(IS_LTDC_YUV2RGBCONVERTOR(pLayerFlexYUVFullPlanar->ColorConverter));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* update the handler */
+  hltdc->LayerCfg[LayerIdx].WindowX0 = pLayerFlexYUVFullPlanar->Layer.WindowX0;
+  hltdc->LayerCfg[LayerIdx].WindowX1 = pLayerFlexYUVFullPlanar->Layer.WindowX1;
+  hltdc->LayerCfg[LayerIdx].WindowY0 = pLayerFlexYUVFullPlanar->Layer.WindowY0;
+  hltdc->LayerCfg[LayerIdx].WindowY1 = pLayerFlexYUVFullPlanar->Layer.WindowY1;
+  hltdc->LayerCfg[LayerIdx].PixelFormat = LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR;
+  hltdc->LayerCfg[LayerIdx].Alpha = pLayerFlexYUVFullPlanar->Layer.Alpha;
+  hltdc->LayerCfg[LayerIdx].Alpha0 = pLayerFlexYUVFullPlanar->Layer.Alpha0;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor1 = pLayerFlexYUVFullPlanar->Layer.BlendingFactor1;
+  hltdc->LayerCfg[LayerIdx].BlendingFactor2 = pLayerFlexYUVFullPlanar->Layer.BlendingFactor2;
+  hltdc->LayerCfg[LayerIdx].FBStartAdress = pLayerFlexYUVFullPlanar->YUVFullPlanarAddress.YAddress;
+  hltdc->LayerCfg[LayerIdx].ImageWidth = pLayerFlexYUVFullPlanar->Layer.ImageWidth;
+  hltdc->LayerCfg[LayerIdx].ImageHeight = pLayerFlexYUVFullPlanar->Layer.ImageHeight;
+
+  /* Set composition parameters */
+  LTDC_SetCompositionConfig(hltdc, LayerIdx);
+
+  /* Set flexible YUV format */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->PCR, LTDC_LxPCR_YCEN |
+            pLayerFlexYUVFullPlanar->FlexYUV.ChrominanceOrder |
+            (LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR >> LTDC_LxPCR_YCM_Pos) |
+            pLayerFlexYUVFullPlanar->FlexYUV.YUVOrder |
+            pLayerFlexYUVFullPlanar->FlexYUV.LuminanceOrder | pLayerFlexYUVFullPlanar->FlexYUV.LuminanceRescale);
+
+  /* Set YUV to RGB conversion */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CYR0R, \
+            (U2B[pLayerFlexYUVFullPlanar->ColorConverter] << LTDC_LxCYR0R_CB2B_Pos) |
+            V2R[pLayerFlexYUVFullPlanar->ColorConverter]);
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CYR1R, V2G[pLayerFlexYUVFullPlanar->ColorConverter] |
+            (U2G[pLayerFlexYUVFullPlanar->ColorConverter] << LTDC_LxCYR1R_CB2G_Pos));
+
+  /* Set LTDC parameters */
+  LTDC_SetConfig(hltdc, pLayerFlexYUVFullPlanar->YUVFullPlanarAddress.UAddress,
+                 pLayerFlexYUVFullPlanar->YUVFullPlanarAddress.VAddress, LTDC_MIRROR_NONE,
+                 LayerIdx);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the default ARGB8888 color for a specific LTDC layer.
+  *
+  * Each layer within the LTDC module has a default color in the ARGB8888 format, which is
+  * displayed outside the defined layer window or when the layer itself is disabled.
+  * This function enable the display of default color for a given layer.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_EnableDefaultColor(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable Default Color Blending */
+  SET_BIT(LTDC_LAYER(hltdc, LayerIdx)->CR, LTDC_LxCR_DCBEN);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the default ARGB8888 color for a specific LTDC layer.
+  *
+  * Each layer within the LTDC module has a default color in the ARGB8888 format, which is
+  * displayed outside the defined layer window or when the layer itself is disabled.
+  * This function prevents the default color from being displayed when a  layer is disabled.
+  *
+  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values:
+  *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_DisableDefaultColor(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Enable Default Color Blending */
+  CLEAR_BIT(LTDC_LAYER(hltdc, LayerIdx)->CR, LTDC_LxCR_DCBEN);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure the blending order for a given layer.
+  *
+  * This function sets the blending order of the layers managed by the LTDC module.
+  * The blending order determines how the layers are superimposed on each other.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains
+  *              the configuration information for the LTDC module.
+  * @param Order The blending order value. This parameter can be one of the following values:
+  *              @arg LTDC_BLENDING_ORDER_FOREGROUND: Layer set in the foreground.
+  *              @arg LTDC_BLENDING_ORDER_BACKGROUND: Layer set in the background.
+  * @param LayerIdx Index of the layer being configured. This parameter can be one of the following:
+  *                 @arg LTDC_LAYER_1: Layer 1 of the LTDC.
+  *                 @arg LTDC_LAYER_2: Layer 2 of the LTDC.
+  * @retval  HAL status
+  */
+HAL_StatusTypeDef HAL_LTDC_ConfigBlendingOrder(LTDC_HandleTypeDef *hltdc, uint32_t Order, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LTDC_LAYER(LayerIdx));
+  assert_param(IS_LTDC_BLEND_ORDER(Order));
+
+  /* Process locked */
+  __HAL_LOCK(hltdc);
+
+  /* Change LTDC peripheral state */
+  hltdc->State = HAL_LTDC_STATE_BUSY;
+
+  /* Set the blending order */
+  MODIFY_REG(LTDC_LAYER(hltdc, LayerIdx)->BFCR, LTDC_LxBFCR_BOR, Order);
+
+  /* Set the Immediate Reload type */
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->RCR, LTDC_LxRCR_IMR | LTDC_LxRCR_GRMSK);
+
+  /* Change the LTDC state*/
+  hltdc->State = HAL_LTDC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hltdc);
+
+  return HAL_OK;
+}
+/**
+  * @brief Retrieves the user configuration for a specific layer in the LTDC peripheral.
+  *
+  * This static function retrieves the current configuration for the specified layer, including the
+  * mirroring setup and auxiliary buffer addresses.  It extracts the stride based on the pixel format
+  * and calculates the buffer addresses accordingly. The retrieved configuration includes the mirror
+  * orientation and the starting addresses of the color frame buffer and auxiliary buffers.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param Mirror Pointer to a uint32_t variable where the mirror configuration will be stored. The
+  *               value will be one of the following:
+  *               - LTDC_MIRROR_NONE: No mirroring.
+  *               - LTDC_MIRROR_HORIZONTAL: Horizontal mirroring.
+  *               - LTDC_MIRROR_VERTICAL: Vertical mirroring.
+  *               - LTDC_MIRROR_HORIZONTAL_VERTICAL: Horizontal and vertical mirroring.
+  * @param Aux0Addr Pointer to a uint32_t variable where the address of the first auxiliary buffer will
+  *                 be stored, if applicable.
+  * @param Aux1Addr Pointer to a uint32_t variable where the address of the second auxiliary buffer will
+  *                 be stored, if applicable.
+  * @param LayerIdx Specifies the index of the layer being queried. This parameter can be one of the
+  *                 following values:
+  *                 - LTDC_LAYER_1: Retrieve configuration for layer 1.
+  *                 - LTDC_LAYER_2: Retrieve configuration for layer 2.
+  *                 - Other layer indices as defined by the hardware and used within the driver.
+  *
+  * @note This function is intended for internal use within the LTDC driver and does not return a value.
+  */
+static void LTDC_RetrieveUserConfig(LTDC_HandleTypeDef *hltdc, uint32_t *Mirror, uint32_t *Aux0Addr,
+                                    uint32_t *Aux1Addr, uint32_t LayerIdx)
+{
+  uint32_t stride;
+  const uint32_t hmirror = ((LTDC_LAYER(hltdc, LayerIdx)->CR) & LTDC_LxCR_HMEN_Msk);
+  const uint32_t pitchSign = (LTDC_LAYER(hltdc, LayerIdx)->CFBLR & LTDC_LxCFBLR_CFBP) & LTDC_PITCH_SIGN_MSK;
+
+  switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+  {
+    case LTDC_PIXEL_FORMAT_ARGB8888:
+    case LTDC_PIXEL_FORMAT_BGRA8888:
+    case LTDC_PIXEL_FORMAT_ABGR8888:
+    case LTDC_PIXEL_FORMAT_RGBA8888:
+      stride = 4U;
+      break;
+    case LTDC_PIXEL_FORMAT_RGB888:
+      stride = 3U;
+      break;
+    case LTDC_PIXEL_FORMAT_RGB565:
+    case LTDC_PIXEL_FORMAT_BGR565:
+    case LTDC_PIXEL_FORMAT_ARGB1555:
+    case LTDC_PIXEL_FORMAT_ARGB4444:
+    case LTDC_PIXEL_FORMAT_AL88:
+    case LTDC_PIXEL_FORMAT_FLEX_YUV_COPLANAR:
+      stride = 2U;
+      break;
+    case LTDC_PIXEL_FORMAT_FLEX_ARGB:
+      stride = ((LTDC_LAYER(hltdc, LayerIdx)->FPF1R) & LTDC_LxFPF1R_PSIZE_Msk) >> LTDC_LxFPF1R_PSIZE_Pos;
+      break;
+    case LTDC_PIXEL_FORMAT_L8:
+    case LTDC_PIXEL_FORMAT_AL44:
+    case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+    default:
+      stride = 1U;
+      break;
+  }
+
+  if ((pitchSign == 0U) && (hmirror == 0U))
+  {
+    *Mirror = LTDC_MIRROR_NONE;
+    hltdc->LayerCfg[LayerIdx].FBStartAdress = LTDC_LAYER(hltdc, LayerIdx)->CFBAR;
+    *Aux0Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA0R;
+    *Aux1Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA1R;
+  }
+  else if ((pitchSign == 0U) && (hmirror == LTDC_LxCR_HMEN))
+  {
+    *Mirror = LTDC_MIRROR_HORIZONTAL;
+    hltdc->LayerCfg[LayerIdx].FBStartAdress = LTDC_LAYER(hltdc, LayerIdx)->CFBAR - \
+                                              (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                         hltdc->LayerCfg[LayerIdx].WindowX0)) + 1U;
+    switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+    {
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+        *Aux0Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA0R - \
+                    (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                               hltdc->LayerCfg[LayerIdx].WindowX0)) + 1U;
+        break;
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR:
+        *Aux0Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA0R - \
+                    (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U)) + 1U;
+        *Aux1Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA1R - \
+                    (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U)) + 1U;
+        break;
+      default:
+        /* Nothing to do */
+        break;
+    }
+
+  }
+  else if ((pitchSign != 0U) && (hmirror == 0U))
+  {
+    *Mirror = LTDC_MIRROR_VERTICAL;
+    hltdc->LayerCfg[LayerIdx].FBStartAdress = LTDC_LAYER(hltdc, LayerIdx)->CFBAR - \
+                                              (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                         hltdc->LayerCfg[LayerIdx].WindowX0) * \
+                                               ((hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                 hltdc->LayerCfg[LayerIdx].WindowY0) - 1U));
+    switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+    {
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+        *Aux0Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA0R - (stride * \
+                                                           (hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                            hltdc->LayerCfg[LayerIdx].WindowX0) * \
+                                                           (((hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                              hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U) - 1U));
+        break;
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR:
+        *Aux0Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA0R - (stride * \
+                                                           ((hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                             hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) * \
+                                                           (((hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                              hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U) - 1U));
+        *Aux1Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA1R - (stride * \
+                                                           ((hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                             hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) * \
+                                                           (((hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                              hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U) - 1U));
+        break;
+      default:
+        /* Nothing to do */
+        break;
+    }
+  }
+
+  else
+  {
+    *Mirror = LTDC_MIRROR_HORIZONTAL_VERTICAL;
+    hltdc->LayerCfg[LayerIdx].FBStartAdress = LTDC_LAYER(hltdc, LayerIdx)->CFBAR - \
+                                              (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                         hltdc->LayerCfg[LayerIdx].WindowX0) * \
+                                               (hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                hltdc->LayerCfg[LayerIdx].WindowY0)) + 1U;
+    switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+    {
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+        *Aux0Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA0R - (stride * \
+                                                           (hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                            hltdc->LayerCfg[LayerIdx].WindowX0) * \
+                                                           ((hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                             hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U)) + 1U;
+        break;
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR:
+        *Aux0Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA0R - (stride * \
+                                                           ((hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                             hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) * \
+                                                           ((hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                             hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U)) + 1U;
+        *Aux1Addr = LTDC_LAYER(hltdc, LayerIdx)->AFBA1R - (stride * \
+                                                           ((hltdc->LayerCfg[LayerIdx].WindowX1 - \
+                                                             hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) * \
+                                                           ((hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                                             hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U)) + 1U;
+        break;
+      default:
+        /* Nothing to do */
+        break;
+    }
+  }
+}
+
+/**
+  * @brief Set the configuration for a specific layer of the LTDC controller.
+  *
+  * This function configures a layer of the LTDC controller with the specified parameters.
+  * It sets the pixel format stride, window positioning, color frame buffer address, auxiliary
+  * frame buffer addresses, buffer length, and line number based on the layer configuration.
+  * It also handles the mirroring configuration for the layer if specified.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains
+  *              the configuration information for the specified LTDC.
+  * @param Aux0Addr Auxiliary frame buffer address 0 used for certain pixel formats.
+  * @param Aux1Addr Auxiliary frame buffer address 1 used for certain pixel formats.
+  * @param Mirror Specifies the mirroring configuration for the layer. This parameter
+  *               can be one of the following values:
+  *               @arg LTDC_MIRROR_NONE: No mirroring.
+  *               @arg LTDC_MIRROR_HORIZONTAL: Horizontal mirroring.
+  *               @arg LTDC_MIRROR_VERTICAL: Vertical mirroring.
+  *               @arg LTDC_MIRROR_HORIZONTAL_VERTICAL: Horizontal and vertical mirroring.
+  * @param LayerIdx Index of the layer being configured. This parameter can be one of the following:
+  *                 @arg LTDC_LAYER_1: Layer 1 of the LTDC.
+  *                 @arg LTDC_LAYER_2: Layer 2 of the LTDC.
+  *                 Depending on the LTDC hardware, additional layers may be supported.
+  *
+  * @note The stride is calculated based on the pixel format of the layer. The pixel format
+  *       defines the number of bytes per pixel and hence the stride (the increment from one
+  *       pixel to the next in a row of pixels). The function configures the layer window size
+  *       and position, as well as the color and auxiliary frame buffer addresses, which are
+  *       dependent on the mirroring configuration and pixel format. The buffer length and
+  *       frame buffer line number are also set according to the pixel format and layer size.
+  *       Mirroring settings are applied by adjusting the frame buffer start address and
+  *       enabling the corresponding mirroring bits in the control register.
+  *
+  *       This function does not return a value as it is a static function used internally within the
+  *        driver.
+  */
+static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, uint32_t Aux0Addr, uint32_t Aux1Addr, uint32_t Mirror,
+                           uint32_t LayerIdx)
+{
+  uint32_t stride;
+  uint32_t tmp;
+
+  /* Configure the frame buffer line number */
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (hltdc->LayerCfg[LayerIdx].ImageHeight);
+
+  switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+  {
+    case LTDC_PIXEL_FORMAT_ARGB8888:
+    case LTDC_PIXEL_FORMAT_BGRA8888:
+    case LTDC_PIXEL_FORMAT_ABGR8888:
+    case LTDC_PIXEL_FORMAT_RGBA8888:
+      stride = 4U;
+      break;
+    case LTDC_PIXEL_FORMAT_RGB888:
+      stride = 3U;
+      break;
+    case LTDC_PIXEL_FORMAT_RGB565:
+    case LTDC_PIXEL_FORMAT_BGR565:
+    case LTDC_PIXEL_FORMAT_ARGB1555:
+    case LTDC_PIXEL_FORMAT_ARGB4444:
+    case LTDC_PIXEL_FORMAT_AL88:
+    case LTDC_PIXEL_FORMAT_FLEX_YUV_COPLANAR:
+      stride = 2U;
+      break;
+    case LTDC_PIXEL_FORMAT_FLEX_ARGB:
+      stride = (((LTDC_LAYER(hltdc, LayerIdx)->FPF1R) & LTDC_LxFPF1R_PSIZE_Msk) >> LTDC_LxFPF1R_PSIZE_Pos);
+      break;
+    case LTDC_PIXEL_FORMAT_L8:
+    case LTDC_PIXEL_FORMAT_AL44:
+    case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+    default:
+      stride = 1U;
+      break;
+  }
+
+  /* Configure the horizontal start and stop position */
+  tmp = ((hltdc->LayerCfg[LayerIdx].WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
+  LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((hltdc->LayerCfg[LayerIdx].WindowX0 +
+                                         ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
+
+  /* Configure the vertical start and stop position */
+  tmp = ((hltdc->LayerCfg[LayerIdx].WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
+  LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((hltdc->LayerCfg[LayerIdx].WindowY0 +
+                                         (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
+
+  if (Mirror == LTDC_MIRROR_NONE)
+  {
+    LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (hltdc->LayerCfg[LayerIdx].FBStartAdress);
+
+    switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+    {
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr;
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = (hltdc->LayerCfg[LayerIdx].ImageWidth << 16U) |
+                                             (hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                              hltdc->LayerCfg[LayerIdx].WindowX0 + 7U);
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = (hltdc->LayerCfg[LayerIdx].ImageHeight) >> 1U;
+        break;
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr;
+
+        /* Configure the auxiliary frame buffer address 1 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA1R = Aux1Addr;
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = ((hltdc->LayerCfg[LayerIdx].ImageWidth >> 1U) << 16U) |
+                                             (((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) + 7U);
+
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = (hltdc->LayerCfg[LayerIdx].ImageHeight) >> 1U;
+        break;
+      default:
+        /* Nothing to do */
+        break;
+    }
+
+    /* Configure the color frame buffer pitch in byte */
+    LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((hltdc->LayerCfg[LayerIdx].ImageWidth * stride) << 16U) |
+                                          (((hltdc->LayerCfg[LayerIdx].WindowX1 - hltdc->LayerCfg[LayerIdx].WindowX0) *
+                                            stride)  + 7U));
+
+    /* Enable LTDC_Layer by setting LEN bit */
+    MODIFY_REG(LTDC_LAYER(hltdc, LayerIdx)->CR,LTDC_LxCR_HMEN, LTDC_LxCR_LEN);
+  }
+
+  else if (Mirror == LTDC_MIRROR_HORIZONTAL)
+  {
+    /* Configure the color frame buffer start address */
+    LTDC_LAYER(hltdc, LayerIdx)->CFBAR = hltdc->LayerCfg[LayerIdx].FBStartAdress +
+                                         (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                    hltdc->LayerCfg[LayerIdx].WindowX0)) - 1U;
+
+    switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+    {
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr +
+                                              (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                         hltdc->LayerCfg[LayerIdx].WindowX0)) - 1U;
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = (hltdc->LayerCfg[LayerIdx].ImageWidth << 16U) |
+                                             (hltdc->LayerCfg[LayerIdx].WindowX1 - hltdc->LayerCfg[LayerIdx].WindowX0 +
+                                              7U);
+
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = hltdc->LayerCfg[LayerIdx].ImageHeight >> 1U ;
+        break;
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr +
+                                              (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                          hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U)) - 1U;
+
+        /* Configure the auxiliary frame buffer address 1 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA1R = Aux1Addr +
+                                              (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                          hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U)) - 1U;
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = ((hltdc->LayerCfg[LayerIdx].ImageWidth >> 1U) << 16U) |
+                                             (((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) + 7U);
+
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = hltdc->LayerCfg[LayerIdx].ImageHeight >> 1U;
+        break;
+      default:
+        /* Nothing to do */
+        break;
+    }
+
+    /* Configure the color frame buffer pitch in byte */
+    LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((hltdc->LayerCfg[LayerIdx].ImageWidth * stride) << 16U) |
+                                          (((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                             hltdc->LayerCfg[LayerIdx].WindowX0) * stride)  + 7U));
+
+    /* Enable horizontal mirroring bit & LTDC_Layer by setting LEN bit */
+    SET_BIT(LTDC_LAYER(hltdc, LayerIdx)->CR, LTDC_LxCR_HMEN | LTDC_LxCR_LEN);
+  }
+
+  else if (Mirror == LTDC_MIRROR_VERTICAL)
+  {
+    /* Configure the color frame buffer start address */
+    LTDC_LAYER(hltdc, LayerIdx)->CFBAR = hltdc->LayerCfg[LayerIdx].FBStartAdress +
+                                         (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                    hltdc->LayerCfg[LayerIdx].WindowX0) *
+                                          ((hltdc->LayerCfg[LayerIdx].WindowY1 -
+                                            hltdc->LayerCfg[LayerIdx].WindowY0) - 1U));
+
+    switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+    {
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr +
+                                              (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                         hltdc->LayerCfg[LayerIdx].WindowX0) *
+                                               (((hltdc->LayerCfg[LayerIdx].WindowY1 -
+                                                  hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U) - 1U));
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = ((0x8000U - (hltdc->LayerCfg[LayerIdx].ImageWidth * stride)) << 16U) |
+                                             (((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                hltdc->LayerCfg[LayerIdx].WindowX0) * stride)  + 7U);
+
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = hltdc->LayerCfg[LayerIdx].ImageHeight >> 1U;
+        break;
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr +
+                                              (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                          hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) *
+                                               (((hltdc->LayerCfg[LayerIdx].WindowY1 -
+                                                  hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U) - 1U));
+
+        /* Configure the auxiliary frame buffer address 1 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA1R = Aux1Addr +
+                                              (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                          hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) *
+                                               (((hltdc->LayerCfg[LayerIdx].WindowY1 -
+                                                  hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U) - 1U));
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = (((0x8000U - (hltdc->LayerCfg[LayerIdx].ImageWidth >> 1U)) *
+                                               stride) << 16U) |
+                                             ((((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                 hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) * stride) + 7U);
+
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = hltdc->LayerCfg[LayerIdx].ImageHeight >> 1U;
+        break;
+      default:
+        /* Nothing to do */
+        break;
+    }
+
+    /* set the pitch */
+    LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = ((((0x8000U - (hltdc->LayerCfg[LayerIdx].ImageWidth * stride))) << 16U) |
+                                           (((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                              hltdc->LayerCfg[LayerIdx].WindowX0) * stride) + 7U));
+
+    /* Enable LTDC_Layer by setting LEN bit */
+    MODIFY_REG(LTDC_LAYER(hltdc, LayerIdx)->CR, LTDC_LxCR_HMEN, LTDC_LxCR_LEN);
+  }
+
+  else
+    /*  Mirror = LTDC_MIRROR_HORIZONTAL_VERTICAL */
+  {
+    /* Configure the color frame buffer start address */
+    LTDC_LAYER(hltdc, LayerIdx)->CFBAR = hltdc->LayerCfg[LayerIdx].FBStartAdress +
+                                         (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                    hltdc->LayerCfg[LayerIdx].WindowX0) *
+                                          (hltdc->LayerCfg[LayerIdx].WindowY1 - \
+                                           hltdc->LayerCfg[LayerIdx].WindowY0)) - 1U;
+
+    switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+    {
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_SEMIPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr +
+                                              (stride * (hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                         hltdc->LayerCfg[LayerIdx].WindowX0) *
+                                               ((hltdc->LayerCfg[LayerIdx].WindowY1 -
+                                                 hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U)) - 1U;
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = ((0x8000U - (hltdc->LayerCfg[LayerIdx].ImageWidth * stride)) << 16U) |
+                                             (((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                hltdc->LayerCfg[LayerIdx].WindowX0) * stride) + 7U);
+
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = hltdc->LayerCfg[LayerIdx].ImageHeight >> 1U;
+        break;
+      case LTDC_PIXEL_FORMAT_FLEX_YUV_FULLPLANAR:
+        /* Configure the auxiliary frame buffer address 0 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA0R = Aux0Addr +
+                                              (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                          hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) *
+                                               ((hltdc->LayerCfg[LayerIdx].WindowY1 -
+                                                 hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U)) - 1U;
+
+        /* Configure the auxiliary frame buffer address 1 */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBA1R = Aux1Addr +
+                                              (stride * ((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                          hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) *
+                                               ((hltdc->LayerCfg[LayerIdx].WindowY1 -
+                                                 hltdc->LayerCfg[LayerIdx].WindowY0) >> 1U)) - 1U;
+
+        /* Configure the buffer length */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLR = (((0x8000U - (hltdc->LayerCfg[LayerIdx].ImageWidth >> 1U)) * stride)
+                                              << 16U) |
+                                             ((((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                                 hltdc->LayerCfg[LayerIdx].WindowX0) >> 1U) * stride) + 7U);
+
+        /* Configure the frame buffer line number */
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR &= ~(LTDC_L1AFBLNR_AFBLNBR);
+        LTDC_LAYER(hltdc, LayerIdx)->AFBLNR = hltdc->LayerCfg[LayerIdx].ImageHeight >> 1U;
+        break;
+      default:
+        /* Nothing to do */
+        break;
+    }
+
+    LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = ((((0x8000U - (hltdc->LayerCfg[LayerIdx].ImageWidth * stride))) << 16U) |
+                                           (((hltdc->LayerCfg[LayerIdx].WindowX1 -
+                                              hltdc->LayerCfg[LayerIdx].WindowX0) * stride) + 7U));
+
+    /* Enable horizontal mirroring bit & LTDC_Layer by setting LEN bit */
+    SET_BIT(LTDC_LAYER(hltdc, LayerIdx)->CR, LTDC_LxCR_HMEN | LTDC_LxCR_LEN);
+  }
+}
+
+/**
+  * @brief Configures the composition parameters for the specified layer in the LTDC peripheral.
+  *
+  * This static function sets the default color values, constant alpha value, and blending factors for
+  * the specified layer of the LTDC. The configuration is based on the LayerCfg structure within the
+  * LTDC handle, which includes the background color, alpha values, and blending factors.
+  *
+  * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains the configuration information
+  *              for the LTDC module.
+  * @param LayerIdx Specifies the index of the layer being configured. This parameter can be one of the
+  *                 following values:
+  *                 - LTDC_LAYER_1: Configuration for layer 1.
+  *                 - LTDC_LAYER_2: Configuration for layer 2.
+  *                 - Other layer indices as defined by the hardware and used within the driver.
+  *
+  * @note This function is intended for internal use within the LTDC driver and does not return a value.
+ */
+static void LTDC_SetCompositionConfig(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  uint32_t tmp;
+  uint32_t tmp1;
+  uint32_t tmp2;
+
+  /* Configure the default color values */
+  tmp = ((uint32_t)(hltdc->LayerCfg[LayerIdx].Backcolor.Green) << 8U);
+  tmp1 = ((uint32_t)(hltdc->LayerCfg[LayerIdx].Backcolor.Red) << 16U);
+  tmp2 = (hltdc->LayerCfg[LayerIdx].Alpha0 << 24U);
+  WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (hltdc->LayerCfg[LayerIdx].Backcolor.Blue | tmp | tmp1 | tmp2));
+
+  /* Specifies the constant alpha value */
+  LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
+  LTDC_LAYER(hltdc, LayerIdx)->CACR = (hltdc->LayerCfg[LayerIdx].Alpha);
+
+  /* Specifies the blending factors */
+  LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BOR | LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
+  tmp = ((uint32_t)(LTDC_LAYER(hltdc, LayerIdx)->BFCR & LTDC_LxBFCR_BOR_Msk) >> LTDC_LxBFCR_BOR_Pos) << 16U;
+  LTDC_LAYER(hltdc, LayerIdx)->BFCR = (hltdc->LayerCfg[LayerIdx].BlendingFactor1 |
+                                       hltdc->LayerCfg[LayerIdx].BlendingFactor2 | tmp);
+}
+
+/**
+  * @brief Sets a software predefined ARGB pixel format using flexible ARGB parameters for the specified layer.
+  *
+  * This function configures the specified layer of the LTDC to use a software predefined ARGB pixel
+  * format. The desired format is specified by the PixelFormat parameter within the LTDC handle.
+  * @param  hltdc     Pointer to a LTDC_HandleTypeDef structure that contains
+  *                   the configuration information for the LTDC.
+  * @param  LayerIdx  LTDC Layer index.
+  *                   This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
+  * @retval None
+  *
+  *  @note This function does not return a value as it is a static function used internally within the
+  *        driver.
+  */
+static void LTDC_SetPredefFormat(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
+{
+  uint32_t PSIZE = 0U;
+  uint32_t ALEN = 0U;
+  uint32_t APOS = 0U;
+  uint32_t RLEN = 0U;
+  uint32_t RPOS = 0U;
+  uint32_t BLEN = 0U;
+  uint32_t BPOS = 0U;
+  uint32_t GLEN = 0U;
+  uint32_t GPOS = 0U;
+
+  /* Specify Flex ARGB parameters according to pixel format */
+  switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+  {
+    case LTDC_PIXEL_FORMAT_ARGB1555:
+      PSIZE = 2U;
+      ALEN = 1U;
+      APOS = 15U;
+      RLEN = 5U;
+      RPOS = 10U;
+      GLEN = 5U;
+      GPOS = 5U;
+      BLEN = 5U;
+      BPOS = 0U;
+      break;
+    case LTDC_PIXEL_FORMAT_ARGB4444:
+      PSIZE = 2U;
+      ALEN = 4U;
+      APOS = 12U;
+      RLEN = 4U;
+      RPOS = 8U;
+      GLEN = 4U;
+      GPOS = 4U;
+      BLEN = 4U;
+      BPOS = 0U;
+      break;
+    case LTDC_PIXEL_FORMAT_L8:
+      PSIZE = 1U;
+      ALEN = 0U;
+      APOS = 0U;
+      RLEN = 8U;
+      RPOS = 0U;
+      GLEN = 8U;
+      GPOS = 0U;
+      BLEN = 8U;
+      BPOS = 0U;
+      break;
+    case LTDC_PIXEL_FORMAT_AL44:
+      PSIZE = 1U;
+      ALEN = 4U;
+      APOS = 4U;
+      RLEN = 4U;
+      RPOS = 0U;
+      GLEN = 4U;
+      GPOS = 0U;
+      BLEN = 4U;
+      BPOS = 0U;
+      break;
+    case LTDC_PIXEL_FORMAT_AL88:
+      PSIZE = 2U;
+      ALEN = 8U;
+      APOS = 8U;
+      RLEN = 8U;
+      RPOS = 0U;
+      GLEN = 8U;
+      GPOS = 0U;
+      BLEN = 8U;
+      BPOS = 0U;
+      break;
+    default:
+      break;
+  }
+
+  switch (hltdc->LayerCfg[LayerIdx].PixelFormat)
+  {
+    case LTDC_PIXEL_FORMAT_ARGB8888:
+    case LTDC_PIXEL_FORMAT_ABGR8888:
+    case LTDC_PIXEL_FORMAT_RGBA8888:
+    case LTDC_PIXEL_FORMAT_BGRA8888:
+    case LTDC_PIXEL_FORMAT_RGB565:
+    case LTDC_PIXEL_FORMAT_BGR565:
+    case LTDC_PIXEL_FORMAT_RGB888:
+      LTDC_LAYER(hltdc, LayerIdx)->PFCR = (hltdc->LayerCfg[LayerIdx].PixelFormat);
+      LTDC_LAYER(hltdc, LayerIdx)->FPF0R = 0U;
+      LTDC_LAYER(hltdc, LayerIdx)->FPF1R = 0U;
+      break;
+    case LTDC_PIXEL_FORMAT_ARGB1555:
+    case LTDC_PIXEL_FORMAT_ARGB4444:
+    case LTDC_PIXEL_FORMAT_L8:
+    case LTDC_PIXEL_FORMAT_AL44:
+    case LTDC_PIXEL_FORMAT_AL88:
+      LTDC_LAYER(hltdc, LayerIdx)->PFCR = LTDC_LxPFCR_PF;
+      LTDC_LAYER(hltdc, LayerIdx)->FPF0R = (RLEN << LTDC_LxFPF0R_RLEN_Pos) +
+                                           (RPOS << LTDC_LxFPF0R_RPOS_Pos) +
+                                           (ALEN << LTDC_LxFPF0R_ALEN_Pos) +
+                                           APOS;
+      LTDC_LAYER(hltdc, LayerIdx)->FPF1R = (PSIZE << LTDC_LxFPF1R_PSIZE_Pos) +
+                                           (BLEN << LTDC_LxFPF1R_BLEN_Pos)  +
+                                           (BPOS << LTDC_LxFPF1R_BPOS_Pos) +
+                                           (GLEN << LTDC_LxFPF1R_GLEN_Pos) +
+                                           GPOS;
+      break;
+    default:
+      break;
+  }
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* LTDC */
+
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ltdc_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ltdc_ex.c
new file mode 100644
index 000000000..95ff7998d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ltdc_ex.c
@@ -0,0 +1,154 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_ltdc_ex.c
+  * @author  MCD Application Team
+  * @brief   LTDC Extension HAL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
+
+#if defined (LTDC) && defined (DSI)
+
+/** @defgroup LTDCEx LTDCEx
+  * @brief LTDC HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the LTDC
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Retrieve common parameters from DSI Video mode configuration structure
+  * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
+  *                 the configuration information for the LTDC.
+  * @param  VidCfg  pointer to a DSI_VidCfgTypeDef structure that contains
+  *                 the DSI video mode configuration parameters
+  * @note   The implementation of this function is taking into account the LTDC
+  *         polarities inversion as described in the current LTDC specification
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
+{
+  /* Retrieve signal polarities from DSI */
+
+  /* The following polarity is inverted:
+                     LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
+
+#if !defined(POLARITIES_INVERSION_UPDATED)
+  /* Note 1 : Code in line w/ Current LTDC specification */
+  hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
+                            DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+  hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
+  hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
+#else
+  /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+  hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
+  hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
+  hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29;
+#endif /* POLARITIES_INVERSION_UPDATED */
+
+  /* Retrieve vertical timing parameters from DSI */
+  hltdc->Init.VerticalSync       = VidCfg->VerticalSyncActive - 1U;
+  hltdc->Init.AccumulatedVBP     = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
+  hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+                                   VidCfg->VerticalActive - 1U;
+  hltdc->Init.TotalHeigh         = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+                                   VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Retrieve common parameters from DSI Adapted command mode configuration structure
+  * @param  hltdc   pointer to a LTDC_HandleTypeDef structure that contains
+  *                 the configuration information for the LTDC.
+  * @param  CmdCfg  pointer to a DSI_CmdCfgTypeDef structure that contains
+  *                 the DSI command mode configuration parameters
+  * @note   The implementation of this function is taking into account the LTDC
+  *         polarities inversion as described in the current LTDC specification
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
+{
+  /* Retrieve signal polarities from DSI */
+
+  /* The following polarities are inverted:
+                     LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
+                     LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
+                     LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+
+#if !defined(POLARITIES_INVERSION_UPDATED)
+  /* Note 1 : Code in line w/ Current LTDC specification */
+  hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
+                            DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+  hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
+  hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
+#else
+  /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
+  hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
+  hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
+  hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29;
+#endif /* POLARITIES_INVERSION_UPDATED */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LTDC && DSI */
+
+#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mce.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mce.c
new file mode 100644
index 000000000..0d29da8d4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mce.c
@@ -0,0 +1,1048 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mce.c
+  * @author  MCD Application Team
+  * @brief   MCE HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          features of the Memory Cipher Engine (MCE) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Region setting/enable functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+ [..]
+    The MCE HAL driver can be used as follows:
+
+    (#) ToBC (refer to MCE comments)
+
+
+    [..]
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_MCE_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_MCE_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     ToBC (refer to MCE comments)
+
+     When the compilation flag USE_HAL_MCE_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MCE MCE
+  * @brief MCE HAL module driver.
+  * @{
+  */
+
+
+#ifdef HAL_MCE_MODULE_ENABLED
+
+#if defined(MCE1)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define MCE_TIMEOUT_VALUE  255U   /* Internal timeout for keys valid flag */
+#define MCE1_CONTEXT_NB    2U
+/* Private macros ------------------------------------------------------------*/
+
+#define IS_MCE_AES_INSTANCE(INSTANCE) ((INSTANCE) == MCE1)
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MCE_Exported_Functions
+  * @{
+  */
+
+/** @defgroup MCE_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the MCE peripheral and create the associated handle.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_Init(MCE_HandleTypeDef *hmce)
+{
+  /* Check the MCE handle allocation */
+  if (hmce == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+
+  if (hmce->State == HAL_MCE_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    __HAL_UNLOCK(hmce);
+
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+    /* Init the MCE Callback settings */
+    hmce->ErrorCallback = HAL_MCE_ErrorCallback; /* Legacy weak callback */
+
+    if (hmce->MspInitCallback == NULL)
+    {
+      hmce->MspInitCallback = HAL_MCE_MspInit; /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware */
+    hmce->MspInitCallback(hmce);
+#else
+    /* Init the low level hardware */
+    HAL_MCE_MspInit(hmce);
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+  }
+
+  /* Change the MCE state */
+  hmce->State = HAL_MCE_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the MCE peripheral.
+  * @note   Any lock set at peripheral, key or cipher context level requires a MCE peripheral reset
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_DeInit(MCE_HandleTypeDef *hmce)
+{
+  MCE_Region_TypeDef *p_region;
+  MCE_Context_TypeDef *p_context;
+
+  /* Check the MCE handle allocation */
+  if (hmce == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+
+  /* Change the MCE state */
+  hmce->State = HAL_MCE_STATE_BUSY;
+
+  /* Disable interrupts */
+  CLEAR_BIT(hmce->Instance->IAIER, MCE_IAIER_IAEIE);
+
+  /* Disable all regions */
+  for (uint32_t i = MCE_REGION1; i <= MCE_REGION4; i++)
+  {
+    p_region = (MCE_Region_TypeDef *)((uint32_t)(hmce->Instance) + 0x40U + (0x10U * i));
+    CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN);
+    /** we don't have the registry ATTR in this product */
+  }
+
+  /* Disable all cipher contexts if any for the MCE instance */
+  if (hmce->Instance == MCE1)
+  {
+    for (uint32_t i = 0; i < MCE1_CONTEXT_NB; i++)
+    {
+      p_context = (MCE_Context_TypeDef *)((uint32_t)(hmce->Instance) + 0x240U + (0x30U * i));
+      CLEAR_BIT(p_context->CCCFGR, MCE_CCCFGR_CCEN);
+    }
+  }
+
+  /* Clear privileged-only configuration access */
+  /** we don't have the registry PRIVCFGR in this product */
+
+  /* Clear flags */
+  WRITE_REG(hmce->Instance->IACR, MCE_IACR_IAEF);
+
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+  if (hmce->MspDeInitCallback == NULL)
+  {
+    hmce->MspDeInitCallback = HAL_MCE_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hmce->MspDeInitCallback(hmce);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_MCE_MspDeInit(hmce);
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+
+  /* Change the MCE state */
+  hmce->State = HAL_MCE_STATE_RESET;
+
+  /* Reset MCE error status */
+  hmce->ErrorCode = HAL_MCE_ERROR_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmce);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/** *********  main sequence functions : set the configuration of regions, AES context and Noekeon config *********/
+
+/**
+  * @brief  Write instance master or fast master keys
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  pConfig pointer at an MCE_NoekeonConfig structure that contains
+            the configuration on the Noekeon encryption engine
+  * @note   Writes are ignored if MKLOCK or GLOCK bit is set in MCE_CR register and HAL error
+  *         is reported in that case
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_ConfigNoekeon(MCE_HandleTypeDef *hmce, const MCE_NoekeonConfigTypeDef *pConfig)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+
+  /* If Key is null, or
+     if the global lock is set or
+     if the master keys lock is set,
+     return an error */
+  tickstart = HAL_GetTick();
+  if (((hmce->Instance->CR & (MCE_CR_GLOCK | MCE_CR_MKLOCK)) == 0U) && (pConfig->pKey != NULL))
+  {
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    MODIFY_REG(hmce->Instance->CR, MCE_CR_CIPHERSEL, MCE_NOEKEON);
+    /* master keys are used for encryption */
+    if (pConfig->KeyType == MCE_USE_MASTERKEYS)
+    {
+      /* If Master Key valid flag is set, need to write dummy value in MKEYRx to reset it */
+      if ((hmce->Instance->SR & MCE_SR_MKVALID) != 0U)
+      {
+        WRITE_REG(hmce->Instance->MKEYR0, 0U);
+      }
+
+      /* Set Key */
+      WRITE_REG(hmce->Instance->MKEYR0, pConfig->pKey[0]);
+      WRITE_REG(hmce->Instance->MKEYR1, pConfig->pKey[1]);
+      WRITE_REG(hmce->Instance->MKEYR2, pConfig->pKey[2]);
+      WRITE_REG(hmce->Instance->MKEYR3, pConfig->pKey[3]);
+      WRITE_REG(hmce->Instance->MKEYR4, pConfig->pKey[4]);
+      WRITE_REG(hmce->Instance->MKEYR5, pConfig->pKey[5]);
+      WRITE_REG(hmce->Instance->MKEYR6, pConfig->pKey[6]);
+      WRITE_REG(hmce->Instance->MKEYR7, pConfig->pKey[7]);
+      while (HAL_IS_BIT_CLR(hmce->Instance->SR, MCE_SR_MKVALID))
+      {
+        /* Check for the Timeout */
+        if ((HAL_GetTick() - tickstart) > MCE_TIMEOUT_VALUE)
+        {
+
+          hmce->ErrorCode |= HAL_MCE_MASTER_KEY_ERROR;
+          ret = HAL_ERROR;
+          break;
+        }
+      }
+
+    }
+    else if (pConfig->KeyType == MCE_USE_FASTMASTERKEYS)
+    {
+      /* If Fast Master Key valid flag is set, need to write dummy value in FMKEYRx to reset it */
+      if ((hmce->Instance->SR & MCE_SR_FMKVALID) != 0U)
+      {
+        WRITE_REG(hmce->Instance->FMKEYR0, 0U);
+      }
+      /* Set Key */
+      WRITE_REG(hmce->Instance->FMKEYR0, pConfig->pKey[0]);
+      WRITE_REG(hmce->Instance->FMKEYR1, pConfig->pKey[1]);
+      WRITE_REG(hmce->Instance->FMKEYR2, pConfig->pKey[2]);
+      WRITE_REG(hmce->Instance->FMKEYR3, pConfig->pKey[3]);
+      WRITE_REG(hmce->Instance->FMKEYR4, pConfig->pKey[4]);
+      WRITE_REG(hmce->Instance->FMKEYR5, pConfig->pKey[5]);
+      WRITE_REG(hmce->Instance->FMKEYR6, pConfig->pKey[6]);
+      WRITE_REG(hmce->Instance->FMKEYR7, pConfig->pKey[7]);
+      while (HAL_IS_BIT_CLR(hmce->Instance->SR, MCE_SR_FMKVALID))
+      {
+        /* Check for the Timeout */
+        if ((HAL_GetTick() - tickstart) > MCE_TIMEOUT_VALUE)
+        {
+          hmce->ErrorCode |= HAL_MCE_FASTMASTER_KEY_ERROR;
+          ret = HAL_ERROR;
+          break;
+        }
+      }
+    }
+    else
+    {
+      /* nothing to do, the keytype is not valid */
+    }
+    __HAL_UNLOCK(hmce);
+  }
+  return ret;
+}
+
+
+/**
+  * @brief  Set context configuration.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  AESConfig context configuration
+  * @param  ContextIndex index of context that is configured
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_ConfigAESContext(MCE_HandleTypeDef *hmce, const MCE_AESConfigTypeDef  *AESConfig,
+                                           uint32_t ContextIndex)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+  MCE_Context_TypeDef *p_context;
+  uint32_t *p_key;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex));
+
+
+  /* If global lock is set or no configuration provided, context cannot be configured */
+  if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && (AESConfig != NULL) && \
+      ((ContextIndex == MCE_CONTEXT1) || (ContextIndex == MCE_CONTEXT2)))
+  {
+    address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \
+                              (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos)));
+    p_context = (MCE_Context_TypeDef *)address;
+    MODIFY_REG(hmce->Instance->CR, MCE_CR_CIPHERSEL, AESConfig->KeySize);
+    /* Check cipher context is not locked */
+    if ((p_context->CCCFGR & MCE_CCCFGR_CCLOCK) != MCE_CCCFGR_CCLOCK)
+    {
+      if ((p_context->CCCFGR & MCE_CCCFGR_KEYLOCK) != MCE_CCCFGR_KEYLOCK)
+      {
+        /* Take Lock */
+        __HAL_LOCK(hmce);
+
+        /* Write nonce */
+        WRITE_REG(p_context->CCNR0, AESConfig->Nonce[0]);
+        WRITE_REG(p_context->CCNR1, AESConfig->Nonce[1]);
+
+        if (AESConfig->pKey != NULL)
+        {
+          p_key = AESConfig->pKey;
+          WRITE_REG(p_context->CCKEYR0, *p_key);
+          p_key++;
+          WRITE_REG(p_context->CCKEYR1, *p_key);
+          p_key++;
+          WRITE_REG(p_context->CCKEYR2, *p_key);
+          p_key++;
+          WRITE_REG(p_context->CCKEYR3, *p_key);
+        }
+        /* Compute theoretically expected CRC and compare it with that reported by the peripheral */
+
+        /* Write version */
+        MODIFY_REG(p_context->CCCFGR, MCE_CCCFGR_VERSION, ((uint32_t) AESConfig->Version) << MCE_CCCFGR_VERSION_Pos);
+
+        MODIFY_REG(p_context->CCCFGR, MCE_CCCFGR_MODE, (uint32_t) AESConfig->Cipher_Mode);
+        ret = HAL_OK;
+
+        /* Release Lock */
+        __HAL_UNLOCK(hmce);
+      }
+    }
+  }
+  return ret;
+}
+
+
+/**
+  * @brief  Set region configuration.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  RegionIndex index of region that is configured
+  * @param  pConfig region configuration
+  * @note   The region is enabled by default once the configuration is complete
+  * @note   An enabled region is temporary disabled to apply the new configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_ConfigRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex,
+                                       const MCE_RegionConfigTypeDef *pConfig)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+  MCE_Region_TypeDef *p_region;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_REGIONINDEX(RegionIndex));
+  assert_param(IS_MCE_ALGORITHM(hmce->Instance, pConfig->Mode));
+
+  /** we have no AccessMode nor PrivilegedAccess fields in this product */
+
+  /* If global lock is set or no configuration provided, region cannot be configured */
+  if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && (pConfig != NULL))
+  {
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex));
+    p_region = (MCE_Region_TypeDef *)address;
+
+    /* If region is enabled, disable it during the configuration process */
+    if ((p_region->REGCR & MCE_REGCR_BREN) == MCE_REGCR_BREN)
+    {
+      CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN);
+    }
+
+    /* Set privileged access, ciphering algorithm and context ID */
+    MODIFY_REG(p_region->REGCR,  MCE_REGCR_ENC, pConfig->Mode);
+
+    /* Set start and end addresses */
+    WRITE_REG(p_region->SADDR, pConfig->StartAddress);
+    WRITE_REG(p_region->EADDR, pConfig->EndAddress);
+
+    /* Set write attribute for the region */
+    /** we have no ATTR register in this product */
+
+    /* Enable the region by default */
+    SET_BIT(p_region->REGCR, MCE_REGCR_BREN);
+
+    ret = HAL_OK;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hmce);
+  }
+
+  return ret;
+
+}
+
+/**
+  * @brief  Set region AES Context.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  ContextIndex index of context that is configured
+  * @param  RegionIndex index of region that is configured
+  * @note   The Region is enabled by default once the configuration is complete
+  * @note   An enabled region is temporary disabled to apply the new configuration
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_MCE_SetRegionAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex, uint32_t RegionIndex)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+  MCE_Region_TypeDef *p_region;
+  __IO uint32_t address;
+
+  assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex));
+  assert_param(IS_MCE_REGIONINDEX(RegionIndex));
+
+  /* If global lock is set, region cannot be configured */
+  if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK)
+  {
+
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex));
+    p_region = (MCE_Region_TypeDef *)address;
+
+    /* If region is enabled, disable it during the configuration process */
+    if ((p_region->REGCR & MCE_REGCR_BREN) == MCE_REGCR_BREN)
+    {
+      CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN);
+    }
+
+    /* Set context ID */
+    MODIFY_REG(p_region->REGCR, MCE_REGCR_CTXID, ContextIndex);
+
+    /* Enable the region by default */
+    SET_BIT(p_region->REGCR, MCE_REGCR_BREN);
+
+    ret = HAL_OK;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hmce);
+
+  }
+
+  return ret;
+}
+
+
+/** *********  Enabling and disabling functions : enable/disable AES and Noekeon configurations and regions *********/
+
+
+/**
+  * @brief  Cipher context enable
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  ContextIndex index of context that is enabled
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_EnableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex)
+{
+  MCE_Context_TypeDef *p_context;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex));
+
+  if ((ContextIndex != MCE_CONTEXT1) && (ContextIndex != MCE_CONTEXT2))
+  {
+    return HAL_ERROR;
+  }
+
+  address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \
+                            (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos)));
+  p_context = (MCE_Context_TypeDef *)address;
+
+  /* If cipher context is locked or if global lock is set,
+     and if cipher context is not enabled already, return an error */
+
+  if ((p_context->CCCFGR & MCE_CCCFGR_CCEN) != MCE_CCCFGR_CCEN)
+  {
+    if ((p_context->CCCFGR & MCE_CCCFGR_CCLOCK) == MCE_CCCFGR_CCLOCK)
+    {
+      return HAL_ERROR;
+    }
+    if ((hmce->Instance->CR & MCE_CR_GLOCK) == MCE_CR_GLOCK)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  __HAL_LOCK(hmce);
+
+  /* Enable context */
+  SET_BIT(p_context->CCCFGR, MCE_CCCFGR_CCEN);
+
+  __HAL_UNLOCK(hmce);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Cipher context disable
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  ContextIndex index of context that is disabled
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_DisableAESContext(MCE_HandleTypeDef *hmce, uint32_t ContextIndex)
+{
+  MCE_Context_TypeDef *p_context;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex));
+
+  if ((ContextIndex != MCE_CONTEXT1) && (ContextIndex != MCE_CONTEXT2))
+  {
+    return HAL_ERROR;
+  }
+
+  address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \
+                            (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos)));
+  p_context = (MCE_Context_TypeDef *)address;
+
+  /* If cipher context is locked or if global lock is set,
+     and if cipher context is not disabled already, return an error */
+
+  if ((p_context->CCCFGR & MCE_CCCFGR_CCEN) == MCE_CCCFGR_CCEN)
+  {
+    if ((p_context->CCCFGR & MCE_CCCFGR_CCLOCK) == MCE_CCCFGR_CCLOCK)
+    {
+      return HAL_ERROR;
+    }
+    if ((hmce->Instance->CR & MCE_CR_GLOCK) == MCE_CR_GLOCK)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  __HAL_LOCK(hmce);
+
+  /* Disable context */
+  CLEAR_BIT(p_context->CCCFGR, MCE_CCCFGR_CCEN);
+
+  __HAL_UNLOCK(hmce);
+
+  return HAL_OK;
+
+}
+
+
+/**
+  * @brief  Enable region.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  RegionIndex index of region that is enabled
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_EnableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+  MCE_Region_TypeDef *p_region;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_REGIONINDEX(RegionIndex));
+
+  /* If global lock is set, region cannot be configured */
+  if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK)
+  {
+    address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex));
+    p_region = (MCE_Region_TypeDef *)address;
+
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    /* Check region is not enabled, else error */
+    if ((p_region->REGCR & MCE_REGCR_BREN) != MCE_REGCR_BREN)
+    {
+      /* Enable the region */
+      SET_BIT(p_region->REGCR, MCE_REGCR_BREN);
+
+      ret = HAL_OK;
+    }
+
+    /* Release Lock */
+    __HAL_UNLOCK(hmce);
+  }
+
+  return ret;
+
+}
+
+
+/**
+  * @brief  Disable region.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  RegionIndex index of region that is disabled
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_DisableRegion(MCE_HandleTypeDef *hmce, uint32_t RegionIndex)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+  MCE_Region_TypeDef *p_region;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_REGIONINDEX(RegionIndex));
+
+  address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x40U + (0x10U * RegionIndex));
+  p_region = (MCE_Region_TypeDef *)address;
+
+  /* If global lock is set, region cannot be configured */
+  if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK)
+  {
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    /* Check region is enabled, else error */
+    if ((p_region->REGCR & MCE_REGCR_BREN) == MCE_REGCR_BREN)
+    {
+      /* Disable the region */
+      CLEAR_BIT(p_region->REGCR, MCE_REGCR_BREN);
+
+      ret = HAL_OK;
+    }
+
+    /* Release Lock */
+    __HAL_UNLOCK(hmce);
+  }
+
+  return ret;
+
+}
+
+
+/** *************  Lock functions : Lock AES and Noekeon configurations and keys *********/
+
+/**
+  * @brief  Lock MCE instance registers configuration
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @note   Once MCE_CR_GLOCK is set, all writes to MCE registers are ignored,
+  *         with the exception of MCE_IACR and MCE_IAIER registers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_LockGlobalConfig(MCE_HandleTypeDef *hmce)
+{
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+
+  /* Take Lock */
+  __HAL_LOCK(hmce);
+
+  SET_BIT(hmce->Instance->CR, MCE_CR_GLOCK);
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmce);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Lock cipher context
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  ContextIndex index of context that is locked
+  * @note   Once MCE_CCCFGR_CCLOCK is set, writes to MCE_CCxCFGR and MCE_CCxNR registers
+  *         are ignored until next MCE reset.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_LockAESContextConfig(MCE_HandleTypeDef *hmce, uint32_t ContextIndex)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+  MCE_Context_TypeDef *p_context;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex));
+
+  /* If global lock is set or no configuration provided, context cannot be configured */
+  if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && \
+      ((ContextIndex == MCE_CONTEXT1) || (ContextIndex == MCE_CONTEXT2)))
+  {
+    address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \
+                              (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos)));
+    p_context = (MCE_Context_TypeDef *)address;
+
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    SET_BIT(p_context->CCCFGR, MCE_CCCFGR_CCLOCK);
+
+    ret = HAL_OK;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hmce);
+  }
+
+  return ret;
+
+}
+
+/**
+  * @brief  Lock context cipher key
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  ContextIndex index of context the cipher key of which is locked
+  * @note   Once MCE_CCCFGR_KEYLOCK is set, writes to MCE_CCxKEYR registers are ignored
+  *         until next MCE reset. KEYCRC bitfield value does not change.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_LockAESContextKey(MCE_HandleTypeDef *hmce, uint32_t ContextIndex)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+  MCE_Context_TypeDef *p_context;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex));
+
+  /* If global lock is set or no configuration provided, context cannot be configured */
+  if (((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK) && \
+      ((ContextIndex == MCE_CONTEXT1) || (ContextIndex == MCE_CONTEXT2)))
+  {
+    address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \
+                              (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos)));
+    p_context = (MCE_Context_TypeDef *)address;
+
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    SET_BIT(p_context->CCCFGR, MCE_CCCFGR_KEYLOCK);
+
+    ret = HAL_OK;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hmce);
+  }
+
+  return ret;
+
+}
+
+/**
+  * @brief  Lock Noekeon master keys
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @note   Once MCE_CR_MKLOCK is set, writes to MCE_MKEYRx and MCE_FMKEYRx registers are ignored until next MCE reset.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MCE_LockNoekeonMasterKeys(MCE_HandleTypeDef *hmce)
+{
+  HAL_StatusTypeDef ret = HAL_ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+
+  /* If global lock is set, master keys lock cannot be set */
+  if ((hmce->Instance->CR & MCE_CR_GLOCK) != MCE_CR_GLOCK)
+  {
+    /* Take Lock */
+    __HAL_LOCK(hmce);
+
+    SET_BIT(hmce->Instance->CR, MCE_CR_MKLOCK);
+
+    ret = HAL_OK;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hmce);
+  }
+
+  return ret;
+
+}
+
+
+/**
+  * @brief  Initialize the MCE MSP.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval None
+  */
+__weak void HAL_MCE_MspInit(MCE_HandleTypeDef *hmce)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmce);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_MCE_MspInit can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize MCE MSP.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval None
+  */
+__weak void HAL_MCE_MspDeInit(MCE_HandleTypeDef *hmce)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmce);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_MCE_MspDeInit can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  get the CRC key of the specified context.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @param  pCRCKey pointer to the CRC key
+  * @param  ContextIndex index of CONTEXT the CRC key
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_MCE_GetAESContextCRCKey(const MCE_HandleTypeDef *hmce, uint32_t *pCRCKey, uint32_t ContextIndex)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  const MCE_Context_TypeDef *p_context;
+  __IO uint32_t address;
+
+  /* Check the parameters */
+  assert_param(IS_MCE_AES_INSTANCE(hmce->Instance));
+  assert_param(IS_MCE_CONTEXT(hmce->Instance, ContextIndex));
+
+  if (*pCRCKey == 0x00U)
+  {
+    ret = HAL_ERROR;
+  }
+
+  address = (__IO uint32_t)((uint32_t)hmce->Instance + 0x240UL + \
+                            (0x30UL * ((ContextIndex - MCE_CONTEXT1) >> MCE_REGCR_CTXID_Pos)));
+  p_context = (MCE_Context_TypeDef *)address;
+
+  *pCRCKey = READ_REG((p_context->CCCFGR)) & MCE_CCCFGR_KEYCRC;
+
+  *pCRCKey >>= MCE_CCCFGR_KEYCRC_Pos;
+  return ret;
+}
+
+/**
+  * @brief  Compute Key CRC
+  * @param  pKey pointer at set of keys
+  * @retval CRC value
+  */
+uint32_t HAL_MCE_KeyCRCComputation(const uint32_t *pKey)
+{
+  uint8_t crc7_poly = 0x7;
+  const uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
+  uint8_t  i;
+  uint8_t crc = 0;
+  uint32_t  j;
+  uint32_t  keyval;
+  uint32_t k;
+  const uint32_t *temp = pKey;
+
+  for (j = 0U; j < 4U; j++)
+  {
+    keyval = *temp;
+    temp++;
+    if (j == 0U)
+    {
+      keyval ^= key_strobe[0];
+    }
+    else
+    {
+      keyval ^= (key_strobe[j] << 24) | ((uint32_t)crc << 16) | (key_strobe[j] << 8) | crc;
+    }
+
+    crc = 0;
+    for (i = 0; i < (uint8_t)32; i++)
+    {
+      k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31 - i)) & ((uint8_t)0xF)))) & 1U;
+      crc <<= 1;
+      if (k != 0U)
+      {
+        crc ^= crc7_poly;
+      }
+    }
+
+    crc ^= (uint8_t)0x55;
+  }
+
+  return (uint32_t) crc;
+}
+
+/**
+  * @brief  Handle MCE interrupt request.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval None
+  */
+void HAL_MCE_IRQHandler(MCE_HandleTypeDef *hmce)
+{
+  uint32_t isr_reg;
+
+  isr_reg = READ_REG(hmce->Instance->IASR);
+  if ((isr_reg & MCE_IASR_IAEF) == MCE_IASR_IAEF)
+  {
+    /* Set configuration access error */
+    hmce->ErrorCode |= HAL_MCE_CONFIGURATION_ACCESS_ERROR;
+
+    /* Clear configuration access error flag */
+    WRITE_REG(hmce->Instance->IACR, MCE_IACR_IAEF);
+  }
+
+#if (USE_HAL_MCE_REGISTER_CALLBACKS == 1)
+  hmce->ErrorCallback(hmce);
+#else
+  HAL_MCE_ErrorCallback(hmce);
+#endif /* USE_HAL_MCE_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief MCE error callback.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval None
+  */
+__weak void HAL_MCE_ErrorCallback(MCE_HandleTypeDef *hmce)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmce);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_MCE_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Return the MCE state.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval HAL status
+  */
+HAL_MCE_StateTypeDef HAL_MCE_GetState(MCE_HandleTypeDef const *hmce)
+{
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+
+  return hmce->State;
+}
+
+/**
+  * @brief  Return the MCE error code.
+  * @param  hmce pointer to an MCE_HandleTypeDef structure that contains
+  *         the configuration information for MCE module
+  * @retval MCE error code (bitfield on 32 bits)
+  */
+uint32_t HAL_MCE_GetError(MCE_HandleTypeDef const *hmce)
+{
+  /* Check the parameters */
+  assert_param(IS_MCE_ALL_INSTANCE(hmce->Instance));
+
+  return hmce->ErrorCode;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* MCE1 */
+
+#endif /* HAL_MCE_MODULE_ENABLED */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mdf.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mdf.c
new file mode 100644
index 000000000..b935f99cc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mdf.c
@@ -0,0 +1,3582 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mdf.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Multi-function Digital Filter (MDF)
+  *          peripheral:
+  *           + Initialization and de-initialization
+  *           + Acquisition
+  *           + Clock absence detection
+  *           + Short circuit detection
+  *           + Out-off limit detection
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    *** Initialization and de-initialization ***
+    ============================================
+    [..]
+      (#) User has first to initialize MDF or ADF instance.
+      (#) As prerequisite, fill in the HAL_MDF_MspInit() :
+        (++) Enable MDFz or ADFz clock interface with __HAL_RCC_MDFz_CLK_ENABLE()
+             or __HAL_RCC_ADFz_CLK_ENABLE().
+        (++) Enable the clocks for the used GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+        (++) Configure these pins in alternate mode using HAL_GPIO_Init().
+        (++) If interrupt mode is used, enable and configure MDFz_FLTx or ADFz
+             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+        (++) If DMA mode is used, initialize and configure DMA.
+      (#) Configure the common parameters (only for first MDF or ADF instance init),
+          serial interface parameters and filter bitstream selection by calling
+          HAL_MDF_Init() function.
+
+    [..]
+      (#) User can de-initialize MDF or ADF instance with HAL_MDF_DeInit() function.
+
+    *** Acquisition ***
+    ===================
+    [..]
+      (#) Configure filter parameters and start acquisition using HAL_MDF_AcqStart(),
+          HAL_MDF_AcqStart_IT() or HAL_MDF_AcqStart_DMA().
+      (#) In polling mode :
+            (++) Use HAL_MDF_PollForAcq() to detect the end of acquisition.
+                 Use HAL_MDF_GetAcqValue to get acquisition value.
+            (++) Only for MDF instance, use HAL_MDF_PollForSnapshotAcq() to detect
+                 the end of snapshot acquisition.
+                 Use HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value.
+            (++) Only for ADF instance, use HAL_MDF_PollForSndLvl() to detect and get
+                 new sound level value and ambient noise value.
+            (++) Only for ADF instance, use HAL_MDF_PollForSad() to detect sound activity.
+      (#) In interrupt mode :
+            (++) HAL_MDF_AcqCpltCallback() will be called at the end of acquisition.
+                 Use HAL_MDF_GetAcqValue to get acquisition value or use
+                 HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value.
+            (++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new
+                 sound level and ambient noise values are available.
+            (++) Only for ADF instance, HAL_MDF_SadCallback() will be called when
+                 sound activity detection occurs.
+            (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun or
+                 saturation occurs.
+                 Use HAL_MDF_GetErrorCode() to get the corresponding error.
+      (#) In DMA mode :
+            (++) HAL_MDF_AcqHalfCpltCallback() and HAL_MDF_AcqCpltCallback() will be called
+                 respectively at the half acquisition and at the acquisition complete.
+            (++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new
+                 sound level and ambient noise values are available.
+            (++) Only for ADF instance, HAL_MDF_SadCallback() will be called when
+                 sound activity detection occurs.
+            (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun,
+                 saturation or DMA error occurs.
+                 Use HAL_MDF_GetErrorCode() to get the corresponding error.
+      (#) Use HAL_MDF_GenerateTrgo() to generate pulse on TRGO signal.
+      (#) During acquisition, use HAL_MDF_SetDelay() and HAL_MDF_GetDelay() to respectively
+          set and get the delay on data source.
+      (#) During acquisition, use HAL_MDF_SetGain() and HAL_MDF_GetGain() to respectively
+          set and get the filter gain.
+      (#) During acquisition, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset() to respectively
+          set and get the filter offset error compensation.
+      (#) During acquisition, only for MDF instance, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset()
+          to respectively set and get the filter offset error compensation.
+      (#) Stop acquisition using HAL_MDF_AcqStop(), HAL_MDF_AcqStop_IT() or HAL_MDF_AcqStop_DMA().
+
+    *** Clock absence detection ***
+    ===============================
+    [..]
+      (#) Clock absence detection is always enabled so no need to start clock absence detection
+          in polling mode.
+          Use HAL_MDF_CkabStart_IT() to start clock absence detection in interrupt mode.
+      (#) In polling mode, use HAL_MDF_PollForCkab() to detect the clock absence.
+      (#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if clock absence detection
+          occurs.
+          Use HAL_MDF_GetErrorCode() to get the corresponding error.
+      (#) Stop clock absence detection in interrupt mode using HAL_MDF_CkabStop_IT().
+
+    *** Short circuit detection ***
+    ===============================
+    [..]
+      (#) Only for MDF instance, start short circuit detection using HAL_MDF_ScdStart()
+          or HAL_MDF_ScdStart_IT().
+      (#) In polling mode, use HAL_MDF_PollForScd() to detect short circuit.
+      (#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if short circuit detection
+          occurs.
+          Use HAL_MDF_GetErrorCode() to get the corresponding error.
+      (#) Stop short circuit detection using HAL_MDF_ScdStop() or HAL_MDF_ScdStop_IT().
+
+    *** Out-off limit detection ***
+    ===============================
+    [..]
+      (#) Only for MDF instance, start out-off limit detection using HAL_MDF_OldStart()
+          or HAL_MDF_OldStart_IT().
+      (#) In polling mode, use HAL_MDF_PollForOld() to detect out-off limit and to get threshold
+          information.
+      (#) In interrupt mode, HAL_MDF_OldCallback() will be called if out-off limit detection occurs.
+      (#) Stop out-off limit detection using HAL_MDF_OldStop() or HAL_MDF_OldStop_IT().
+
+    *** generic functions ***
+    =========================
+    [..]
+      (#) HAL_MDF_IRQHandler will be called when MDF or ADF interrupt occurs.
+      (#) HAL_MDF_ErrorCallback will be called when MDF or ADF error occurs.
+      (#) Use HAL_MDF_GetState() to get the current MDF or ADF instance state.
+      (#) Use HAL_MDF_GetErrorCode() to get the current MDF or ADF instance error code.
+
+    *** Callback registration ***
+    =============================
+    [..]
+    The compilation define USE_HAL_MDF_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+    Use functions HAL_MDF_RegisterCallback(), HAL_MDF_RegisterOldCallback()
+    or HAL_MDF_RegisterSndLvlCallback() to register a user callback.
+
+    [..]
+    Function HAL_MDF_RegisterCallback() allows to register following callbacks :
+      (+) AcqCpltCallback     : Acquisition complete callback.
+      (+) AcqHalfCpltCallback : Acquisition half complete callback.
+      (+) SadCallback         : Sound activity detection callback (only for ADF instance).
+      (+) ErrorCallback       : Error callback.
+      (+) MspInitCallback     : MSP init callback.
+      (+) MspDeInitCallback   : MSP de-init callback.
+    [..]
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    For MDF instance and for specific out-off limit detection callback use dedicated
+    register callback :
+    HAL_MDF_RegisterOldCallback().
+
+    [..]
+    For ADF instance and for specific sound level callback use dedicated register callback :
+    HAL_MDF_RegisterSndLvlCallback().
+
+    [..]
+    Use function HAL_MDF_UnRegisterCallback() to reset a callback to the default weak function.
+
+    [..]
+    HAL_MDF_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID.
+    [..]
+    This function allows to reset following callbacks :
+      (+) AcqCpltCallback     : Acquisition complete callback.
+      (+) AcqHalfCpltCallback : Acquisition half complete callback.
+      (+) SadCallback         : Sound activity detection callback (only for ADF instance).
+      (+) ErrorCallback       : Error callback.
+      (+) MspInitCallback     : MSP init callback.
+      (+) MspDeInitCallback   : MSP de-init callback.
+
+    [..]
+    For MDF instance and for specific out-off limit detection callback use dedicated
+    unregister callback :
+    HAL_MDF_UnRegisterOldCallback().
+
+    [..]
+    For ADF instance and for specific sound level callback use dedicated unregister callback :
+    HAL_MDF_UnRegisterSndLvlCallback().
+
+    [..]
+    By default, after the call of init function and if the state is RESET
+    all callbacks are reset to the corresponding legacy weak functions :
+    examples HAL_MDF_AcqCpltCallback(), HAL_MDF_ErrorCallback().
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak functions in the init and de-init only when these
+    callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the init and de-init keep and use
+    the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the init/de-init.
+    In that case first register the MspInit/MspDeInit user callbacks using
+    HAL_MDF_RegisterCallback() before calling init or de-init function.
+
+    [..]
+    When the compilation define USE_HAL_MDF_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak callbacks are used.
+
+    @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MDF MDF
+  * @brief MDF HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup MDF_Private_Typedefs  MDF Private Typedefs
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup MDF_Private_Constants  MDF Private Constants
+  * @{
+  */
+#define MDF_INSTANCE_NUMBER 7U /* 6 instances for MDF1 and 1 instance for ADF1 */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDF_Private_Variables  MDF Private Variables
+  * @{
+  */
+static uint32_t           v_mdf1InstanceCounter = 0U;
+static uint32_t           v_adf1InstanceCounter = 0U;
+static MDF_HandleTypeDef *a_mdfHandle[MDF_INSTANCE_NUMBER] = {NULL};
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup MDF_Private_Functions  MDF Private Functions
+  * @{
+  */
+static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance);
+static void     MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig);
+static void     MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma);
+static void     MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma);
+static void     MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup MDF_Exported_Functions  MDF Exported Functions
+  * @{
+  */
+
+/** @defgroup MDF_Exported_Functions_Group1  Initialization and de-initialization functions
+  * @brief    Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Initialize the MDF or ADF instance.
+      (+) De-initialize the MDF or ADF instance.
+      (+) Register and unregister callbacks.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the MDF instance according to the specified parameters
+  *         in the MDF_InitTypeDef structure and initialize the associated handle.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check MDF handle */
+  if (hmdf == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance));
+    assert_param(IS_MDF_FILTER_BITSTREAM(hmdf->Init.FilterBistream));
+    assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.SerialInterface.Activation));
+
+    /* Check that instance has not been already initialized */
+    if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] != NULL)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+      /* Reset callback pointers to the weak predefined callbacks */
+      if (IS_ADF_INSTANCE(hmdf->Instance))
+      {
+        hmdf->OldCallback   = NULL;
+        hmdf->SndLvCallback = HAL_MDF_SndLvlCallback;
+        hmdf->SadCallback   = HAL_MDF_SadCallback;
+      }
+      else /* MDF instance */
+      {
+        hmdf->OldCallback   = HAL_MDF_OldCallback;
+        hmdf->SndLvCallback = NULL;
+        hmdf->SadCallback   = NULL;
+      }
+      hmdf->AcqCpltCallback     = HAL_MDF_AcqCpltCallback;
+      hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback;
+      hmdf->ErrorCallback       = HAL_MDF_ErrorCallback;
+
+      /* Call MDF MSP init function */
+      if (hmdf->MspInitCallback == NULL)
+      {
+        hmdf->MspInitCallback = HAL_MDF_MspInit;
+      }
+      hmdf->MspInitCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+      /* Call MDF MSP init function */
+      HAL_MDF_MspInit(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+      /* Configure common parameters only for first MDF or ADF instance */
+      if (((v_mdf1InstanceCounter == 0U) && IS_MDF_INSTANCE(hmdf->Instance)) ||
+          ((v_adf1InstanceCounter == 0U) && IS_ADF_INSTANCE(hmdf->Instance)))
+      {
+        MDF_TypeDef *mdfBase;
+        /* Get MDF base according instance */
+        mdfBase = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
+
+        /* Check clock generator status */
+        if ((mdfBase->CKGCR & MDF_CKGCR_CCKACTIVE) != 0U)
+        {
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Configure number of interleaved filters for MDF instance */
+          if (IS_MDF_INSTANCE(hmdf->Instance))
+          {
+            assert_param(IS_MDF_INTERLEAVED_FILTERS(hmdf->Init.CommonParam.InterleavedFilters));
+            mdfBase->GCR &= ~(MDF_GCR_ILVNB);
+            mdfBase->GCR |= (hmdf->Init.CommonParam.InterleavedFilters << MDF_GCR_ILVNB_Pos);
+          }
+
+          /* Configure processing clock divider, output clock divider,
+             output clock pins and output clock generation trigger */
+          assert_param(IS_MDF_PROC_CLOCK_DIVIDER(hmdf->Init.CommonParam.ProcClockDivider));
+          assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Activation));
+          mdfBase->CKGCR = 0U;
+          mdfBase->CKGCR |= ((hmdf->Init.CommonParam.ProcClockDivider - 1U) << MDF_CKGCR_PROCDIV_Pos);
+          if (hmdf->Init.CommonParam.OutputClock.Activation == ENABLE)
+          {
+            assert_param(IS_MDF_OUTPUT_CLOCK_PINS(hmdf->Init.CommonParam.OutputClock.Pins));
+            assert_param(IS_MDF_OUTPUT_CLOCK_DIVIDER(hmdf->Init.CommonParam.OutputClock.Divider));
+            assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Trigger.Activation));
+            mdfBase->CKGCR |= (((hmdf->Init.CommonParam.OutputClock.Divider - 1U) << MDF_CKGCR_CCKDIV_Pos) |
+                               hmdf->Init.CommonParam.OutputClock.Pins |
+                               (hmdf->Init.CommonParam.OutputClock.Pins >> 4U));
+            if (hmdf->Init.CommonParam.OutputClock.Trigger.Activation == ENABLE)
+            {
+              if (IS_MDF_INSTANCE(hmdf->Instance))
+              {
+                assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source));
+              }
+              else /* ADF instance */
+              {
+                assert_param(IS_ADF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source));
+              }
+              assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(hmdf->Init.CommonParam.OutputClock.Trigger.Edge));
+              mdfBase->CKGCR |= (hmdf->Init.CommonParam.OutputClock.Trigger.Source |
+                                 hmdf->Init.CommonParam.OutputClock.Trigger.Edge |
+                                 MDF_CKGCR_CKGMOD);
+            }
+          }
+
+          /* Activate clock generator */
+          mdfBase->CKGCR |= MDF_CKGCR_CKDEN;
+        }
+      }
+
+      /* Configure serial interface */
+      if ((status == HAL_OK) && (hmdf->Init.SerialInterface.Activation == ENABLE))
+      {
+        /* Check serial interface status */
+        if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U)
+        {
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Configure mode, clock source and threshold */
+          assert_param(IS_MDF_SITF_MODE(hmdf->Init.SerialInterface.Mode));
+          assert_param(IS_MDF_SITF_CLOCK_SOURCE(hmdf->Init.SerialInterface.ClockSource));
+          assert_param(IS_MDF_SITF_THRESHOLD(hmdf->Init.SerialInterface.Threshold));
+          hmdf->Instance->SITFCR = 0U;
+          hmdf->Instance->SITFCR |= ((hmdf->Init.SerialInterface.Threshold << MDF_SITFCR_STH_Pos) |
+                                     hmdf->Init.SerialInterface.Mode | hmdf->Init.SerialInterface.ClockSource);
+
+          /* Activate serial interface */
+          hmdf->Instance->SITFCR |= MDF_SITFCR_SITFEN;
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Configure filter bitstream */
+        hmdf->Instance->BSMXCR &= ~(MDF_BSMXCR_BSSEL);
+        hmdf->Instance->BSMXCR |= hmdf->Init.FilterBistream;
+
+        /* Update instance counter and table */
+        if (IS_ADF_INSTANCE(hmdf->Instance))
+        {
+          v_adf1InstanceCounter++;
+        }
+        else /* MDF instance */
+        {
+          v_mdf1InstanceCounter++;
+        }
+        a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = hmdf;
+
+        /* Update error code and state */
+        hmdf->ErrorCode = MDF_ERROR_NONE;
+        hmdf->State     = HAL_MDF_STATE_READY;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  De-initialize the MDF instance.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check MDF handle */
+  if (hmdf == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance));
+
+    /* Check that instance has not been already deinitialized */
+    if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] == NULL)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      if (IS_MDF_INSTANCE(hmdf->Instance))
+      {
+        /* Disable short circuit detector if needed */
+        if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != 0U)
+        {
+          hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
+        }
+
+        /* Disable out-off limit detector if needed */
+        if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U)
+        {
+          hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
+        }
+      }
+
+      /* Disable sound activity detector if needed */
+      if (IS_ADF_INSTANCE(hmdf->Instance))
+      {
+        if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+        {
+          hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+        }
+      }
+
+      /* Disable filter if needed */
+      if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+      {
+        hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+      }
+
+      /* Disable serial interface if needed */
+      if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U)
+      {
+        hmdf->Instance->SITFCR &= ~(MDF_SITFCR_SITFEN);
+      }
+
+      /* Disable all interrupts and clear all pending flags */
+      hmdf->Instance->DFLTIER = 0U;
+      hmdf->Instance->DFLTISR = 0xFFFFFFFFU;
+
+      /* Disable clock generator only for last MDF or ADF instance deinitialization */
+      if (((v_mdf1InstanceCounter == 1U) && IS_MDF_INSTANCE(hmdf->Instance)) ||
+          ((v_adf1InstanceCounter == 1U) && IS_ADF_INSTANCE(hmdf->Instance)))
+      {
+        MDF_TypeDef *p_mdf_base;
+        /* Get MDF base according instance */
+        p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
+
+        /* Disable clock generator */
+        p_mdf_base->CKGCR &= ~(MDF_CKGCR_CKDEN);
+      }
+
+      /* Call MDF MSP deinit function */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+      if (hmdf->MspDeInitCallback == NULL)
+      {
+        hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
+      }
+      hmdf->MspDeInitCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+      HAL_MDF_MspDeInit(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+      /* Update instance counter and table */
+      if (IS_ADF_INSTANCE(hmdf->Instance))
+      {
+        v_adf1InstanceCounter--;
+      }
+      else /* MDF instance */
+      {
+        v_mdf1InstanceCounter--;
+      }
+      a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = (MDF_HandleTypeDef *) NULL;
+
+      /* Update state */
+      hmdf->State = HAL_MDF_STATE_RESET;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Initialize the MDF instance MSP.
+  * @param  hmdf MDF handle.
+  * @retval None.
+  */
+__weak void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_MspInit could be implemented in the user file */
+}
+
+/**
+  * @brief  De-initialize the MDF instance MSP.
+  * @param  hmdf MDF handle.
+  * @retval None.
+  */
+__weak void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_MspDeInit could be implemented in the user file */
+}
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a user MDF callback to be used instead of the weak predefined callback.
+  * @param  hmdf MDF handle.
+  * @param  CallbackID ID of the callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID.
+  *           @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID.
+  *           @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance).
+  *           @arg @ref HAL_MDF_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @param  pCallback pointer to the callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef        *hmdf,
+                                           HAL_MDF_CallbackIDTypeDef CallbackID,
+                                           pMDF_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pCallback == NULL)
+  {
+    /* Update error code and status */
+    hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hmdf->State == HAL_MDF_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_MDF_ACQ_COMPLETE_CB_ID :
+          hmdf->AcqCpltCallback = pCallback;
+          break;
+        case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID :
+          hmdf->AcqHalfCpltCallback = pCallback;
+          break;
+        case HAL_MDF_SAD_CB_ID :
+          hmdf->SadCallback = pCallback;
+          break;
+        case HAL_MDF_ERROR_CB_ID :
+          hmdf->ErrorCallback = pCallback;
+          break;
+        case HAL_MDF_MSPINIT_CB_ID :
+          hmdf->MspInitCallback = pCallback;
+          break;
+        case HAL_MDF_MSPDEINIT_CB_ID :
+          hmdf->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* Update error code and status */
+          hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else if (hmdf->State == HAL_MDF_STATE_RESET)
+    {
+      switch (CallbackID)
+      {
+        case HAL_MDF_MSPINIT_CB_ID :
+          hmdf->MspInitCallback = pCallback;
+          break;
+        case HAL_MDF_MSPDEINIT_CB_ID :
+          hmdf->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* Update error code and status */
+          hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* Update error code and status */
+      hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Unregister a user MDF callback.
+  *         MDF callback is redirected to the weak predefined callback.
+  * @param  hmdf MDF handle.
+  * @param  CallbackID ID of the callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID.
+  *           @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID.
+  *           @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance).
+  *           @arg @ref HAL_MDF_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef        *hmdf,
+                                             HAL_MDF_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hmdf->State == HAL_MDF_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_MDF_ACQ_COMPLETE_CB_ID :
+        hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback;
+        break;
+      case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID :
+        hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback;
+        break;
+      case HAL_MDF_SAD_CB_ID :
+        hmdf->SadCallback = HAL_MDF_SadCallback;
+        break;
+      case HAL_MDF_ERROR_CB_ID :
+        hmdf->ErrorCallback = HAL_MDF_ErrorCallback;
+        break;
+      case HAL_MDF_MSPINIT_CB_ID :
+        hmdf->MspInitCallback = HAL_MDF_MspInit;
+        break;
+      case HAL_MDF_MSPDEINIT_CB_ID :
+        hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
+        break;
+      default :
+        /* Update error code and status */
+        hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (hmdf->State == HAL_MDF_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_MDF_MSPINIT_CB_ID :
+        hmdf->MspInitCallback = HAL_MDF_MspInit;
+        break;
+      case HAL_MDF_MSPDEINIT_CB_ID :
+        hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
+        break;
+      default :
+        /* Update error code and status */
+        hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update error code and status */
+    hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Register specific MDF out-off limit detector callback
+  *         to be used instead of the weak predefined callback.
+  * @param  hmdf MDF handle.
+  * @param  pCallback pointer to the out-off limit detector callback function.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_RegisterOldCallback(MDF_HandleTypeDef      *hmdf,
+                                              pMDF_OldCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pCallback == NULL)
+  {
+    /* Update error code and status */
+    hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hmdf->State == HAL_MDF_STATE_READY)
+    {
+      hmdf->OldCallback = pCallback;
+    }
+    else
+    {
+      /* Update error code and status */
+      hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Unregister the specific MDF out-off limit detector callback.
+  *         MDF out-off limit detector callback is redirected to the weak predefined callback.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_UnRegisterOldCallback(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hmdf->State == HAL_MDF_STATE_READY)
+  {
+    hmdf->OldCallback = HAL_MDF_OldCallback;
+  }
+  else
+  {
+    /* Update error code and status */
+    hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Register specific MDF sound level callback
+  *         to be used instead of the weak predefined callback.
+  * @param  hmdf MDF handle.
+  * @param  pCallback pointer to the sound level callback function.
+  * @retval HAL status.
+  * @note   This function must not be used with MDF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef         *hmdf,
+                                                 pMDF_SndLvlCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pCallback == NULL)
+  {
+    /* Update error code and status */
+    hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hmdf->State == HAL_MDF_STATE_READY)
+    {
+      hmdf->SndLvCallback = pCallback;
+    }
+    else
+    {
+      /* Update error code and status */
+      hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Unregister the specific MDF sound level callback.
+  *         MDF sound level callback is redirected to the weak predefined callback.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  * @note   This function must not be used with MDF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hmdf->State == HAL_MDF_STATE_READY)
+  {
+    hmdf->SndLvCallback = HAL_MDF_SndLvlCallback;
+  }
+  else
+  {
+    /* Update error code and status */
+    hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDF_Exported_Functions_Group2  Acquisition functions
+  * @brief    Acquisition functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Acquisition functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Start and stop acquisition in polling, interrupt or DMA mode.
+      (+) Wait and get acquisition values.
+      (+) Generate pulse on TRGO signal.
+      (+) Modify and get some filter parameters during acquisition.
+      (+) Wait and get sound level values for ADF instance.
+      (+) Detect sound activity for ADF instance.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to start acquisition in polling mode.
+  * @param  hmdf MDF handle.
+  * @param  pFilterConfig Filter configuration parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pFilterConfig == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+      assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+    }
+    else
+    {
+      assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+    }
+    if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
+        ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
+         (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
+         (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
+    {
+      status = HAL_ERROR;
+    }
+    /* Check state */
+    else if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+    /* Check filter status */
+    else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* For ADF instance, check SAD status */
+      if (IS_ADF_INSTANCE(hmdf->Instance))
+      {
+        if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+        {
+          status = HAL_ERROR;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* For MDF instance, check OLD status and main filter order */
+      assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
+      if (IS_MDF_INSTANCE(hmdf->Instance))
+      {
+        if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
+        {
+          status = HAL_ERROR;
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Configure filter and start acquisition */
+        hmdf->Instance->DFLTCR = 0U;
+        MDF_AcqStart(hmdf, pFilterConfig);
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for available acquisition value.
+  * @param  hmdf MDF handle.
+  * @param  Timeout Timeout value in milliseconds.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t tickstart = HAL_GetTick();
+
+    /* Wait for available acquisition value */
+    while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_RXNEF) != MDF_DFLTISR_RXNEF) && (status == HAL_OK))
+    {
+      /* Check the timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          status = HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Check if data overflow, saturation or reshape filter occurs */
+    uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF));
+    if (error_flags != 0U)
+    {
+      /* Update error code */
+      if ((error_flags & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF)
+      {
+        hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+      }
+      if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
+      {
+        hmdf->ErrorCode |= MDF_ERROR_SATURATION;
+      }
+      if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
+      {
+        hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
+      }
+
+      /* Clear corresponding flags */
+      hmdf->Instance->DFLTISR |= error_flags;
+
+      /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+      hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+      HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Update state only in asynchronous single shot mode */
+      if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE)
+      {
+        hmdf->State = HAL_MDF_STATE_READY;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for available snapshot acquisition value.
+  * @param  hmdf MDF handle.
+  * @param  Timeout Timeout value in milliseconds.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t tickstart = HAL_GetTick();
+
+    /* Wait for available snapshot acquisition value */
+    while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SSDRF) != MDF_DFLTISR_SSDRF) && (status == HAL_OK))
+    {
+      /* Check the timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          status = HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Check if snapshot overrun, saturation or reshape filter occurs */
+    uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_SSOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF));
+    if (error_flags != 0U)
+    {
+      /* Update error code */
+      if ((error_flags & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF)
+      {
+        hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+      }
+      if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
+      {
+        hmdf->ErrorCode |= MDF_ERROR_SATURATION;
+      }
+      if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
+      {
+        hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
+      }
+
+      /* Clear corresponding flags */
+      hmdf->Instance->DFLTISR |= error_flags;
+
+      /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+      hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+      HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get acquisition value.
+  * @param  hmdf MDF handle.
+  * @param  pValue Acquisition value on 24 MSB.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pValue == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check state */
+    if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+    {
+      if (hmdf->State != HAL_MDF_STATE_READY)
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Get acquisition value */
+    *pValue = (int32_t) hmdf->Instance->DFLTDR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get snapshot acquisition value.
+  * @param  hmdf MDF handle.
+  * @param  pSnapshotParam Snapshot parameters.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pSnapshotParam == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check state */
+  else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t snpsdr_value;
+
+    /* Read value of snapshot data register */
+    snpsdr_value = hmdf->Instance->SNPSDR;
+
+    /* Clear snapshot data ready flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF;
+
+    /* Store value of decimation counter in snapshot parameter structure */
+    pSnapshotParam->DecimationCounter = (snpsdr_value & MDF_SNPSDR_MCICDC);
+
+    /* Check snapshot format */
+    if ((hmdf->Instance->DFLTCR & MDF_SNAPSHOT_16BITS) == MDF_SNAPSHOT_16BITS)
+    {
+      /* Store value of integrator counter in snapshot parameter structure */
+      pSnapshotParam->IntegratorCounter = ((snpsdr_value & MDF_SNPSDR_EXTSDR) >> MDF_SNPSDR_EXTSDR_Pos);
+
+      /* Store snapshot acquisition value (16MSB) in snapshot parameter structure */
+      snpsdr_value &= 0xFFFF0000U;
+      pSnapshotParam->Value = (int32_t) snpsdr_value;
+    }
+    else
+    {
+      /* Store snapshot acquisition value (23MSB) in snapshot parameter structure */
+      snpsdr_value &= 0xFFFFFE00U;
+      pSnapshotParam->Value = (int32_t) snpsdr_value;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop acquisition in polling mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    /* Check if state is ready and filter active */
+    if (hmdf->State == HAL_MDF_STATE_READY)
+    {
+      if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
+      {
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Disable sound activity detector if needed for ADF instance */
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+      {
+        hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable filter */
+    hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+
+    /* Clear all potential pending flags */
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF |
+                                  MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF);
+    }
+    else
+    {
+      hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF |
+                                  MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
+    }
+
+    /* Update state */
+    hmdf->State = HAL_MDF_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start acquisition in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @param  pFilterConfig Filter configuration parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pFilterConfig == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+      assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+    }
+    else
+    {
+      assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+    }
+    if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
+        ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
+         (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
+         (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
+    {
+      status = HAL_ERROR;
+    }
+    /* Check state */
+    else if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+    /* Check filter status */
+    else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* For ADF instance, check SAD status */
+      if (IS_ADF_INSTANCE(hmdf->Instance))
+      {
+        if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+        {
+          status = HAL_ERROR;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* For MDF instance, check OLD status and main filter order */
+      assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
+      if (IS_MDF_INSTANCE(hmdf->Instance))
+      {
+        if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
+        {
+          status = HAL_ERROR;
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT)
+        {
+          /* Enable snapshot overrun and data ready interrupts */
+          hmdf->Instance->DFLTIER |= (MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SSDRIE);
+        }
+        else
+        {
+          if ((IS_MDF_INSTANCE(hmdf->Instance)) || (pFilterConfig->SoundActivity.Activation == DISABLE) ||
+              (pFilterConfig->SoundActivity.DataMemoryTransfer != MDF_SAD_NO_MEMORY_TRANSFER))
+          {
+            /* Enable data overflow and fifo threshold interrupts */
+            hmdf->Instance->DFLTIER |= (MDF_DFLTIER_DOVRIE | MDF_DFLTIER_FTHIE);
+          }
+        }
+
+        if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
+        {
+          /* Enable reshape filter overrun interrupt */
+          hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE;
+        }
+
+        /* Enable saturation interrupt */
+        hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE;
+
+        if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
+        {
+          /* Enable sound level value ready and sound activity detection interrupts */
+          assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt));
+          hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ?
+                                     (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) :
+                                     MDF_DFLTIER_SDDETIE;
+        }
+
+        /* Configure filter and start acquisition */
+        hmdf->Instance->DFLTCR = 0U;
+        MDF_AcqStart(hmdf, pFilterConfig);
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop acquisition in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    /* Check if state is ready and filter active */
+    if (hmdf->State == HAL_MDF_STATE_READY)
+    {
+      if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
+      {
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Disable sound activity detector if needed for ADF instance */
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+      {
+        hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable filter */
+    hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+
+    /* Disable interrupts and clear all potential pending flags */
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SATIE |
+                                   MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE | MDF_DFLTIER_SDLVLIE);
+      hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF |
+                                  MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF);
+    }
+    else
+    {
+      hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SSDRIE |
+                                   MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE);
+      hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF |
+                                  MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
+    }
+
+    /* Update state */
+    hmdf->State = HAL_MDF_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start acquisition in DMA mode.
+  * @param  hmdf MDF handle.
+  * @param  pFilterConfig Filter configuration parameters.
+  * @param  pDmaConfig DMA configuration parameters.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig,
+                                       const MDF_DmaConfigTypeDef *pDmaConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if ((pFilterConfig == NULL) || (pDmaConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    assert_param(IS_FUNCTIONAL_STATE(pDmaConfig->MsbOnly));
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+      assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+    }
+    else
+    {
+      assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
+    }
+    if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
+        ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
+         (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
+         (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
+    {
+      status = HAL_ERROR;
+    }
+    else if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT)
+    {
+      status = HAL_ERROR;
+    }
+    /* Check state */
+    else if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+    /* Check filter status */
+    else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* For ADF instance, check SAD status */
+      if (IS_ADF_INSTANCE(hmdf->Instance))
+      {
+        if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+        {
+          status = HAL_ERROR;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* For MDF instance, check OLD status and main filter order */
+      assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
+      if (IS_MDF_INSTANCE(hmdf->Instance))
+      {
+        if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
+        {
+          status = HAL_ERROR;
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        uint32_t SrcAddress;
+
+        if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
+        {
+          /* Enable reshape filter overrun interrupt */
+          hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE;
+        }
+
+        /* Enable saturation interrupt */
+        hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE;
+
+        if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
+        {
+          /* Enable sound level value ready and sound activity detection interrupts */
+          assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt));
+          hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ?
+                                     (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) :
+                                     MDF_DFLTIER_SDDETIE;
+        }
+
+        /* Enable MDF DMA requests */
+        hmdf->Instance->DFLTCR = MDF_DFLTCR_DMAEN;
+
+        /* Start DMA transfer */
+        hmdf->hdma->XferCpltCallback     = MDF_DmaXferCpltCallback;
+        hmdf->hdma->XferHalfCpltCallback = MDF_DmaXferHalfCpltCallback;
+        hmdf->hdma->XferErrorCallback    = MDF_DmaErrorCallback;
+        SrcAddress = (pDmaConfig->MsbOnly == ENABLE) ? (((uint32_t) &hmdf->Instance->DFLTDR) + 2U) :
+                     (uint32_t) &hmdf->Instance->DFLTDR;
+        if ((hmdf->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hmdf->hdma->LinkedListQueue != NULL)
+          {
+            hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = pDmaConfig->DataLength;
+            hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = SrcAddress;
+            hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pDmaConfig->Address;
+
+            status = HAL_DMAEx_List_Start_IT(hmdf->hdma);
+          }
+          else
+          {
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          status = HAL_DMA_Start_IT(hmdf->hdma, SrcAddress, pDmaConfig->Address, pDmaConfig->DataLength);
+        }
+        if (status != HAL_OK)
+        {
+          /* Update state */
+          hmdf->State = HAL_MDF_STATE_ERROR;
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Configure filter and start acquisition */
+          MDF_AcqStart(hmdf, pFilterConfig);
+        }
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop acquisition in DMA mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check if state is ready and filter active */
+  if (hmdf->State == HAL_MDF_STATE_READY)
+  {
+    if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Check state */
+    if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Stop the DMA transfer */
+      if (HAL_DMA_Abort(hmdf->hdma) != HAL_OK)
+      {
+        /* Update state */
+        hmdf->State = HAL_MDF_STATE_ERROR;
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable sound activity detector if needed for ADF instance */
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
+      {
+        hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
+      }
+    }
+
+    /* Disable filter */
+    hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
+
+    /* Disable interrupts and clear all potential pending flags */
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE |
+                                   MDF_DFLTIER_SDLVLIE);
+      hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | MDF_DFLTISR_SDDETF |
+                                  MDF_DFLTISR_SDLVLF);
+    }
+    else
+    {
+      hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE);
+      hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
+    }
+
+    /* Disable MDF DMA requests */
+    hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DMAEN);
+
+    /* Update state */
+    hmdf->State = HAL_MDF_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to generate pulse on TRGO signal.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_READY)
+  {
+    if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    MDF_TypeDef *p_mdf_base;
+
+    /* Get MDF base according instance */
+    p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
+
+    /* Check if trigger output control is already active */
+    if ((p_mdf_base->GCR & MDF_GCR_TRGO) == MDF_GCR_TRGO)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Generate pulse on trigger output control signal */
+      p_mdf_base->GCR |= MDF_GCR_TRGO;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to set delay to apply on data source in number of samples.
+  * @param  hmdf MDF handle.
+  * @param  Delay Delay to apply on data source in number of samples.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 127.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_DELAY(Delay));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check if bitstream delay is already active */
+    if ((hmdf->Instance->DLYCR & MDF_DLYCR_SKPBF) == MDF_DLYCR_SKPBF)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Configure bitstream delay */
+      hmdf->Instance->DLYCR |= Delay;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get current delay applied on data source in number of samples.
+  * @param  hmdf MDF handle.
+  * @param  pDelay Current delay applied on data source in number of samples.
+  *         This value is between Min_Data = 0 and Max_Data = 127.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pDelay == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check state */
+  else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Get current bitstream delay */
+    *pDelay = (hmdf->Instance->DLYCR & MDF_DLYCR_SKPDLY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to set filter gain.
+  * @param  hmdf MDF handle.
+  * @param  Gain Filter gain in step of around 3db (from -48db to 72dB).
+  *         This parameter must be a number between Min_Data = -16 and Max_Data = 24.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_GAIN(Gain));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t register_gain_value;
+    uint32_t tmp_register;
+
+    if (Gain < 0)
+    {
+      int32_t adjust_gain;
+
+      /* adjust gain value to set on register for negative value (offset of -16) */
+      adjust_gain = Gain - 16;
+      register_gain_value = ((uint32_t) adjust_gain & 0x3FU);
+    }
+    else
+    {
+      /* for positive value, no offset to apply */
+      register_gain_value = (uint32_t) Gain;
+    }
+    /* Set gain */
+    tmp_register = (hmdf->Instance->DFLTCICR & ~(MDF_DFLTCICR_SCALE));
+    hmdf->Instance->DFLTCICR = (tmp_register | (register_gain_value << MDF_DFLTCICR_SCALE_Pos));
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get filter gain.
+  * @param  hmdf MDF handle.
+  * @param  pGain Filter gain in step of around 3db (from -48db to 72dB).
+  *         This parameter is between Min_Data = -16 and Max_Data = 24.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pGain == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check state */
+  else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t register_gain_value;
+
+    /* Get current gain */
+    register_gain_value = ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_SCALE) >> MDF_DFLTCICR_SCALE_Pos);
+    if (register_gain_value > 31U)
+    {
+      /* adjust gain value to set on register for negative value (offset of +16) */
+      register_gain_value |= 0xFFFFFFC0U;
+      *pGain = (int32_t) register_gain_value + 16;
+    }
+    else
+    {
+      /* for positive value, no offset to apply */
+      *pGain = (int32_t) register_gain_value;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to set filter offset error compensation.
+  * @param  hmdf MDF handle.
+  * @param  Offset Filter offset error compensation.
+  *         This parameter must be a number between Min_Data = -33554432 and Max_Data = 33554431.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+  assert_param(IS_MDF_OFFSET(Offset));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Set offset */
+    hmdf->Instance->OECCR = (uint32_t) Offset;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to get filter offset error compensation.
+  * @param  hmdf MDF handle.
+  * @param  pOffset Filter offset error compensation.
+  *         This value is between Min_Data = -33554432 and Max_Data = 33554431.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+  if (pOffset == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check state */
+  else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t register_offset_value;
+
+    /* Get current offset */
+    register_offset_value = hmdf->Instance->OECCR;
+    if (register_offset_value > 33554431U)
+    {
+      /* Negative value */
+      register_offset_value |= 0xFC000000U;
+      *pOffset = (int32_t) register_offset_value;
+    }
+    else
+    {
+      /* Positive value */
+      *pOffset = (int32_t) register_offset_value;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for sound level data.
+  * @param  hmdf MDF handle.
+  * @param  Timeout Timeout value in milliseconds.
+  * @param  pSoundLevel Sound level.
+            This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+  * @param  pAmbientNoise Ambient noise.
+            This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+  * @retval HAL status.
+  * @note   This function must not be used with MDF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel,
+                                        uint32_t *pAmbientNoise)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_ADF_INSTANCE(hmdf->Instance));
+  if ((pSoundLevel == NULL) || (pAmbientNoise == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  /* Check state */
+  else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check SAD status */
+  else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t tickstart = HAL_GetTick();
+
+    /* Wait for available sound level data */
+    while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDLVLF) != MDF_DFLTISR_SDLVLF) && (status == HAL_OK))
+    {
+      /* Check the timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          status = HAL_TIMEOUT;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Get sound level */
+      *pSoundLevel = hmdf->Instance->SADSDLVR;
+
+      /* Get ambient noise */
+      *pAmbientNoise = hmdf->Instance->SADANLVR;
+
+      /* Clear sound level ready flag */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for sound activity detection.
+  * @param  hmdf MDF handle.
+  * @param  Timeout Timeout value in milliseconds.
+  * @retval HAL status.
+  * @note   This function must not be used with MDF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_ADF_INSTANCE(hmdf->Instance));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    status = HAL_ERROR;
+  }
+  /* Check SAD status */
+  else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    uint32_t tickstart = HAL_GetTick();
+
+    /* Wait for sound activity detection */
+    while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDDETF) != MDF_DFLTISR_SDDETF) && (status == HAL_OK))
+    {
+      /* Check the timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          status = HAL_TIMEOUT;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Clear sound activity detection flag */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  MDF acquisition complete callback.
+  * @param  hmdf MDF handle.
+  * @retval None.
+  */
+__weak void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_AcqCpltCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  MDF acquisition half complete callback.
+  * @param  hmdf MDF handle.
+  * @retval None.
+  */
+__weak void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_AcqHalfCpltCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  MDF sound level callback.
+  * @param  hmdf MDF handle.
+  * @param  SoundLevel Sound level value computed by sound activity detector.
+  *         This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+  * @param  AmbientNoise Ambient noise value computed by sound activity detector.
+  *         This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
+  * @retval None.
+  */
+__weak void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+  UNUSED(SoundLevel);
+  UNUSED(AmbientNoise);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_SndLvlCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  MDF sound activity detector callback.
+  * @param  hmdf MDF handle.
+  * @retval None.
+  */
+__weak void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_SadCallback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup MDF_Exported_Functions_Group3  Clock absence detection functions
+  * @brief    Clock absence detection functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### Clock absence detection functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Start and stop clock absence detection in interrupt mode.
+      (+) Detect clock absence.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to poll for the clock absence detection.
+  * @param  hmdf MDF handle.
+  * @param  Timeout Timeout value in milliseconds.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check serial interface status and mode */
+    if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    uint32_t tickstart = HAL_GetTick();
+
+    /* Wait for clock absence detection */
+    while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) != MDF_DFLTISR_CKABF) && (status == HAL_OK))
+    {
+      /* Check the timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          status = HAL_TIMEOUT;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Clear clock absence detection flag */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start clock absence detection in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check serial interface status and mode */
+    if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Clear clock absence detection flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+
+    /* Check clock absence detection flag */
+    if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Enable clock absence detection interrupt */
+      hmdf->Instance->DFLTIER |= MDF_DFLTIER_CKABIE;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop clock absence detection in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check serial interface status and mode */
+    if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable clock absence detection interrupt */
+    hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_CKABIE);
+
+    /* Clear potential pending clock absence detection flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup MDF_Exported_Functions_Group4  Short circuit detection functions
+  * @brief    Short circuit detection functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### Short circuit detection functions #####
+  ==============================================================================
+    [..]  This section provides functions available only for MDF instance
+          allowing to :
+      (+) Start and stop short circuit detection in polling and interrupt mode.
+      (+) Detect short circuit.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to start short-circuit detection in polling mode.
+  * @param  hmdf MDF handle.
+  * @param  pScdConfig Short-circuit detector configuration parameters.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pScdConfig == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+    assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold));
+    assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal));
+
+    /* Check state */
+    if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+    {
+      if (hmdf->State != HAL_MDF_STATE_READY)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Check short-circuit detector status */
+      if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE)
+      {
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Configure threshold and break signal */
+        hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) |
+                                 (pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos));
+
+        /* Enable short-circuit detector */
+        hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the short-circuit detection.
+  * @param  hmdf MDF handle.
+  * @param  Timeout Timeout value in milliseconds.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check short-circuit detector status */
+    if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      uint32_t tickstart = HAL_GetTick();
+
+      /* Wait for short-circuit detection */
+      while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SCDF) != MDF_DFLTISR_SCDF) && (status == HAL_OK))
+      {
+        /* Check the timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            status = HAL_TIMEOUT;
+          }
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Clear short-circuit detection flag */
+        hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop short-circuit detection in polling mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check short-circuit detector status */
+    if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Disable short-circuit detection */
+      hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
+
+      /* Clear potential pending short-circuit detection flag */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start short-circuit detection in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @param  pScdConfig Short-circuit detector configuration parameters.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pScdConfig == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+    assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold));
+    assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal));
+
+    /* Check state */
+    if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+    {
+      if (hmdf->State != HAL_MDF_STATE_READY)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Check short-circuit detector status */
+      if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE)
+      {
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Configure threshold and break signal */
+        hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) |
+                                 (pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos));
+
+        /* Enable short-circuit detector interrupt */
+        hmdf->Instance->DFLTIER |= MDF_DFLTIER_SCDIE;
+
+        /* Enable short-circuit detector */
+        hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop short-circuit detection in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check short-circuit detector status */
+    if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Disable short-circuit detection */
+      hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
+
+      /* Disable short-circuit detection interrupt */
+      hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SCDIE);
+
+      /* Clear potential pending short-circuit detection flag */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup MDF_Exported_Functions_Group5  Out-off limit detection functions
+  * @brief    Out-off limit detection functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### Out-off limit detection functions #####
+  ==============================================================================
+    [..]  This section provides functions available only for MDF instance
+          allowing to :
+      (+) Start and stop out-off limit detection in polling and interrupt mode.
+      (+) Detect short circuit and get threshold information.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function allows to start out-off limit detection in polling mode.
+  * @param  hmdf MDF handle.
+  * @param  pOldConfig Out-off limit detector configuration parameters.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pOldConfig == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+    assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode));
+    assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio));
+    assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold));
+    assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold));
+    assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig));
+    assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal));
+    if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check state */
+      if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+      {
+        if (hmdf->State != HAL_MDF_STATE_READY)
+        {
+          status = HAL_ERROR;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Check out-off limit detector status */
+      if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE)
+      {
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Check filter status */
+        if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE)
+        {
+          /* Check main filter order */
+          if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4)
+          {
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /* Reset main filter order */
+          hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD);
+        }
+
+        if (status == HAL_OK)
+        {
+          /* Configure OLD CIC mode, decimation ratio, event and break signal */
+          hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig |
+                                   ((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) |
+                                   (pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos));
+
+          /* Configure low and high thresholds */
+          hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold;
+          hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold;
+
+          /* Enable out-off limit detector */
+          hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN;
+        }
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to poll for the out-off limit detection.
+  * @param  hmdf MDF handle.
+  * @param  Timeout Timeout value in milliseconds.
+  * @param  pThresholdInfo Threshold information of out-off limit detection.
+  *         This parameter can be a value of @ref MDF_OldThresholdInfo.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+  if (pThresholdInfo == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check state */
+    if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+    {
+      if (hmdf->State != HAL_MDF_STATE_READY)
+      {
+        status = HAL_ERROR;
+      }
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check out-off limit detector status */
+    if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      uint32_t tickstart = HAL_GetTick();
+
+      /* Wait for out-off limit detection */
+      while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_OLDF) != MDF_DFLTISR_OLDF) && (status == HAL_OK))
+      {
+        /* Check the timeout */
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            status = HAL_TIMEOUT;
+          }
+        }
+      }
+
+      if (status == HAL_OK)
+      {
+        /* Get threshold information */
+        if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U)
+        {
+          *pThresholdInfo = MDF_OLD_IN_THRESHOLDS;
+        }
+        else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF)
+        {
+          *pThresholdInfo = MDF_OLD_LOW_THRESHOLD;
+        }
+        else
+        {
+          *pThresholdInfo = MDF_OLD_HIGH_THRESHOLD;
+        }
+
+        /* Clear out-off limit detection flags */
+        hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop out-off limit detection in polling mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check out-off limit detector status */
+    if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Disable out-off limit detection */
+      hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
+
+      /* Clear potential pending out-off limit detection flags */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to start out-off limit detection in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @param  pOldConfig Out-off limit detector configuration parameters.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pOldConfig == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+    assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode));
+    assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio));
+    assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold));
+    assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold));
+    assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig));
+    assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal));
+    if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Check state */
+      if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+      {
+        if (hmdf->State != HAL_MDF_STATE_READY)
+        {
+          status = HAL_ERROR;
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Check out-off limit detector status */
+      if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE)
+      {
+        status = HAL_ERROR;
+      }
+      else
+      {
+        /* Check filter status */
+        if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE)
+        {
+          /* Check main filter order */
+          if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4)
+          {
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /* Reset main filter order */
+          hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD);
+        }
+
+        if (status == HAL_OK)
+        {
+          /* Configure OLD CIC mode, decimation ratio, event and break signal */
+          hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig |
+                                   ((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) |
+                                   (pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos));
+
+          /* Configure low and high thresholds */
+          hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold;
+          hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold;
+
+          /* Enable out-off limit detector interrupt */
+          hmdf->Instance->DFLTIER |= MDF_DFLTIER_OLDIE;
+
+          /* Enable out-off limit detector */
+          hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN;
+        }
+      }
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function allows to stop out-off limit detection in interrupt mode.
+  * @param  hmdf MDF handle.
+  * @retval HAL status.
+  * @note   This function must not be used with ADF instance.
+  */
+HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_MDF_INSTANCE(hmdf->Instance));
+
+  /* Check state */
+  if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
+  {
+    if (hmdf->State != HAL_MDF_STATE_READY)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Check out-off limit detector status */
+    if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
+    {
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Disable out-off limit detection */
+      hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
+
+      /* Disable out-off limit detector interrupt */
+      hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_OLDIE);
+
+      /* Clear potential pending out-off limit detection flags */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  MDF out-off limit detector callback.
+  * @param  hmdf MDF handle.
+  * @param  ThresholdInfo Threshold information of out-off limit detection.
+  *         This parameter can be a value of @ref MDF_OldThresholdInfo.
+  * @retval None.
+  */
+__weak void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+  UNUSED(ThresholdInfo);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_OldCallback could be implemented in the user file */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup MDF_Exported_Functions_Group6  Generic functions
+  * @brief    Generic functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### Generic functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to :
+      (+) Handle MDF interrupt.
+      (+) Inform user that error occurs.
+      (+) Get the current MDF instance state.
+      (+) Get the current MDF instance error code.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles the MDF interrupts.
+  * @param  hmdf MDF handle.
+  * @retval None.
+  */
+void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf)
+{
+  uint32_t tmp_reg1;
+  uint32_t tmp_reg2;
+  uint32_t interrupts;
+
+  /* Read current flags and interrupts and determine which ones occur */
+  tmp_reg1 = hmdf->Instance->DFLTIER;
+  tmp_reg2 = hmdf->Instance->DFLTISR;
+  interrupts = (tmp_reg1 & tmp_reg2);
+
+  /* Check if data overflow occurs */
+  if ((interrupts & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF)
+  {
+    /* Clear data overflow flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_DOVRF;
+
+    /* Update error code */
+    hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+
+    /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if snapshot overrun occurs */
+  else if ((interrupts & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF)
+  {
+    /* Clear snapshot overrun flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSOVRF;
+
+    /* Update error code */
+    hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
+
+    /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if RXFIFO threshold occurs */
+  else if ((interrupts & MDF_DFLTISR_FTHF) == MDF_DFLTISR_FTHF)
+  {
+    /* Call acquisition complete callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->AcqCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_AcqCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+
+    /* Update state only in asynchronous single shot mode */
+    if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE)
+    {
+      hmdf->State = HAL_MDF_STATE_READY;
+    }
+  }
+  /* Check if snapshot data ready occurs */
+  else if ((interrupts & MDF_DFLTISR_SSDRF) == MDF_DFLTISR_SSDRF)
+  {
+    /* Clear snapshot data ready flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF;
+
+    /* Call acquisition complete callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->AcqCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_AcqCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if reshape filter overrun occurs */
+  else if ((interrupts & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
+  {
+    /* Clear reshape filter overrun flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_RFOVRF;
+
+    /* Update error code */
+    hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
+
+    /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if clock absence detection occurs */
+  else if ((interrupts & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF)
+  {
+    /* Clear clock absence detection flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
+
+    /* Update error code */
+    hmdf->ErrorCode |= MDF_ERROR_CLOCK_ABSENCE;
+
+    /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if saturation occurs */
+  else if ((interrupts & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
+  {
+    /* Clear saturation flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_SATF;
+
+    /* Update error code */
+    hmdf->ErrorCode |= MDF_ERROR_SATURATION;
+
+    /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if short-circuit detection occurs */
+  else if ((interrupts & MDF_DFLTISR_SCDF) == MDF_DFLTISR_SCDF)
+  {
+    /* Clear short-circuit detection flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
+
+    /* Update error code */
+    hmdf->ErrorCode |= MDF_ERROR_SHORT_CIRCUIT;
+
+    /* Call error callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if out-off limit detection occurs */
+  else if ((interrupts & MDF_DFLTISR_OLDF) == MDF_DFLTISR_OLDF)
+  {
+    uint32_t threshold_info;
+
+    /* Get threshold information */
+    if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U)
+    {
+      threshold_info = MDF_OLD_IN_THRESHOLDS;
+    }
+    else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF)
+    {
+      threshold_info = MDF_OLD_LOW_THRESHOLD;
+    }
+    else
+    {
+      threshold_info = MDF_OLD_HIGH_THRESHOLD;
+    }
+
+    /* Clear out-off limit detection flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
+
+    /* Update error code */
+    hmdf->ErrorCode |= MDF_ERROR_OUT_OFF_LIMIT;
+
+    /* Call out-off limit detection callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->OldCallback(hmdf, threshold_info);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_OldCallback(hmdf, threshold_info);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  /* Check if sound activity detection occurs */
+  else if ((interrupts & MDF_DFLTISR_SDDETF) == MDF_DFLTISR_SDDETF)
+  {
+    /* Clear sound activity detection flag */
+    hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF;
+
+    /* Call sound activity detection callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+    hmdf->SadCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    HAL_MDF_SadCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Check if sound level ready occurs */
+    if ((interrupts & MDF_DFLTISR_SDLVLF) == MDF_DFLTISR_SDLVLF)
+    {
+      uint32_t sound_level;
+      uint32_t ambient_noise;
+
+      /* Get sound level */
+      sound_level = hmdf->Instance->SADSDLVR;
+
+      /* Get ambient noise */
+      ambient_noise = hmdf->Instance->SADANLVR;
+
+      /* Clear sound level ready flag */
+      hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF;
+
+      /* Call sound level callback */
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+      hmdf->SndLvCallback(hmdf, sound_level, ambient_noise);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+      HAL_MDF_SndLvlCallback(hmdf, sound_level, ambient_noise);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  MDF error callback.
+  * @param  hmdf MDF handle.
+  * @retval None.
+  */
+__weak void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdf);
+
+  /* NOTE : This function should not be modified, when the function is needed,
+            the HAL_MDF_ErrorCallback could be implemented in the user file */
+}
+
+/**
+  * @brief  This function allows to get the current MDF state.
+  * @param  hmdf MDF handle.
+  * @retval MDF state.
+  */
+HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf)
+{
+  /* Return MDF state */
+  return hmdf->State;
+}
+
+/**
+  * @brief  This function allows to get the current MDF error.
+  * @param  hmdf MDF handle.
+  * @retval MDF error code.
+  */
+uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf)
+{
+  /* Return MDF error code */
+  return hmdf->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDF_Private_Functions
+  * @brief      Private functions
+  * @{
+  */
+
+/**
+  * @brief  This function allows to get the handle number from instance.
+  * @param  pInstance MDF instance.
+  * @retval Instance number.
+  */
+static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance)
+{
+  uint32_t handle_number;
+
+  /* Get handle number from instance */
+  if (pInstance == MDF1_Filter0)
+  {
+    handle_number = 0U;
+  }
+  else if (pInstance == MDF1_Filter1)
+  {
+    handle_number = 1U;
+  }
+  else if (pInstance == MDF1_Filter2)
+  {
+    handle_number = 2U;
+  }
+  else if (pInstance == MDF1_Filter3)
+  {
+    handle_number = 3U;
+  }
+  else if (pInstance == MDF1_Filter4)
+  {
+    handle_number = 4U;
+  }
+  else if (pInstance == MDF1_Filter5)
+  {
+    handle_number = 5U;
+  }
+  else /* ADF1_Filter0 */
+  {
+    handle_number = 6U;
+  }
+
+  return handle_number;
+}
+
+/**
+  * @brief  This function allows to configure filter and start acquisition.
+  * @param  hmdf MDF handle.
+  * @param  pFilterConfig Filter configuration parameters.
+  * @retval None.
+  */
+static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig)
+{
+  uint32_t register_gain_value;
+
+  /* Configure acquisition mode, discard samples, trigger and fifo threshold */
+  assert_param(IS_MDF_DISCARD_SAMPLES(pFilterConfig->DiscardSamples));
+  assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold));
+  if ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_CONT) ||
+      (pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE))
+  {
+    /* Trigger parameters are not used */
+    hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold |
+                               (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos));
+  }
+  else
+  {
+    /* Trigger parameters are used */
+    if (IS_ADF_INSTANCE(hmdf->Instance))
+    {
+      assert_param(IS_ADF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source));
+    }
+    else
+    {
+      assert_param(IS_MDF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source));
+    }
+    assert_param(IS_MDF_TRIGGER_EDGE(pFilterConfig->Trigger.Edge));
+    hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold |
+                               pFilterConfig->Trigger.Source | pFilterConfig->Trigger.Edge |
+                               (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos));
+  }
+
+  /* Configure if needed snapshot format only for MDF instance */
+  if (IS_MDF_INSTANCE(hmdf->Instance) && (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT))
+  {
+    assert_param(IS_MDF_SNAPSHOT_FORMAT(pFilterConfig->SnapshotFormat));
+    hmdf->Instance->DFLTCR |= pFilterConfig->SnapshotFormat;
+  }
+
+  /* Configure data source, CIC mode, decimation ratio and gain */
+  if (IS_ADF_INSTANCE(hmdf->Instance))
+  {
+    assert_param(IS_ADF_DATA_SOURCE(pFilterConfig->DataSource));
+    assert_param(IS_ADF_CIC_MODE(pFilterConfig->CicMode));
+  }
+  else
+  {
+    assert_param(IS_MDF_DATA_SOURCE(pFilterConfig->DataSource));
+  }
+  assert_param(IS_MDF_DECIMATION_RATIO(pFilterConfig->DecimationRatio));
+  assert_param(IS_MDF_GAIN(pFilterConfig->Gain));
+  if (pFilterConfig->Gain < 0)
+  {
+    int32_t adjust_gain;
+
+    /* adjust gain value to set on register for negative value (offset of -16) */
+    adjust_gain = pFilterConfig->Gain - 16;
+    register_gain_value = ((uint32_t) adjust_gain & 0x3FU);
+  }
+  else
+  {
+    /* for positive value, no offset to apply */
+    register_gain_value = (uint32_t) pFilterConfig->Gain;
+  }
+  hmdf->Instance->DFLTCICR = (pFilterConfig->DataSource | pFilterConfig->CicMode |
+                              ((pFilterConfig->DecimationRatio - 1U) << MDF_DFLTCICR_MCICD_Pos) |
+                              (register_gain_value << MDF_DFLTCICR_SCALE_Pos));
+
+  /* Configure bitstream delay */
+  assert_param(IS_MDF_DELAY(pFilterConfig->Delay));
+  hmdf->Instance->DLYCR = pFilterConfig->Delay;
+
+  /* Configure offset compensation only for MDF instance */
+  if (IS_MDF_INSTANCE(hmdf->Instance))
+  {
+    assert_param(IS_MDF_OFFSET(pFilterConfig->Offset));
+    hmdf->Instance->OECCR = (uint32_t) pFilterConfig->Offset;
+  }
+
+  /* Configure reshape filter */
+  assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->ReshapeFilter.Activation));
+  hmdf->Instance->DFLTRSFR = 0U;
+  if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
+  {
+    /* Configure reshape filter decimation ratio */
+    assert_param(IS_MDF_RSF_DECIMATION_RATIO(pFilterConfig->ReshapeFilter.DecimationRatio));
+    hmdf->Instance->DFLTRSFR |= pFilterConfig->ReshapeFilter.DecimationRatio;
+  }
+  else
+  {
+    /* Bypass reshape filter */
+    hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_RSFLTBYP;
+  }
+
+  /* Configure high-pass filter */
+  assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->HighPassFilter.Activation));
+  if (pFilterConfig->HighPassFilter.Activation == ENABLE)
+  {
+    /* Configure high-pass filter cut-off frequency */
+    assert_param(IS_MDF_HPF_CUTOFF_FREQ(pFilterConfig->HighPassFilter.CutOffFrequency));
+    hmdf->Instance->DFLTRSFR |= pFilterConfig->HighPassFilter.CutOffFrequency;
+  }
+  else
+  {
+    /* Bypass high-pass filter */
+    hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_HPFBYP;
+  }
+
+  /* Configure integrator only for MDF instance */
+  if (IS_MDF_INSTANCE(hmdf->Instance))
+  {
+    assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->Integrator.Activation));
+    if (pFilterConfig->Integrator.Activation == ENABLE)
+    {
+      /* Configure integrator value and output division */
+      assert_param(IS_MDF_INTEGRATOR_VALUE(pFilterConfig->Integrator.Value));
+      assert_param(IS_MDF_INTEGRATOR_OUTPUT_DIV(pFilterConfig->Integrator.OutputDivision));
+      hmdf->Instance->DFLTINTR = (((pFilterConfig->Integrator.Value - 1U) << MDF_DFLTINTR_INTVAL_Pos) |
+                                  pFilterConfig->Integrator.OutputDivision);
+    }
+    else
+    {
+      /* Bypass integrator */
+      hmdf->Instance->DFLTINTR = 0U;
+    }
+  }
+
+  if (IS_ADF_INSTANCE(hmdf->Instance))
+  {
+    assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
+    if (pFilterConfig->SoundActivity.Activation == ENABLE)
+    {
+      /* Configure SAD mode, frame size, hysteresis, sound trigger event
+         and data memory transfer only for ADF instance */
+      assert_param(IS_MDF_SAD_MODE(pFilterConfig->SoundActivity.Mode));
+      assert_param(IS_MDF_SAD_FRAME_SIZE(pFilterConfig->SoundActivity.FrameSize));
+      if (pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR)
+      {
+        assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Hysteresis));
+      }
+      assert_param(IS_MDF_SAD_SOUND_TRIGGER(pFilterConfig->SoundActivity.SoundTriggerEvent));
+      assert_param(IS_MDF_SAD_DATA_MEMORY_TRANSFER(pFilterConfig->SoundActivity.DataMemoryTransfer));
+      if ((pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR) &&
+          (pFilterConfig->SoundActivity.Hysteresis == ENABLE))
+      {
+        hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize |
+                                 MDF_SADCR_HYSTEN | pFilterConfig->SoundActivity.SoundTriggerEvent |
+                                 pFilterConfig->SoundActivity.DataMemoryTransfer);
+      }
+      else
+      {
+        hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize |
+                                 pFilterConfig->SoundActivity.SoundTriggerEvent |
+                                 pFilterConfig->SoundActivity.DataMemoryTransfer);
+      }
+
+      /* Configure SAD minimum noise level, hangover window, learning frames,
+         ambient noise slope control and signal noise threshold only for ADF instance */
+      assert_param(IS_MDF_SAD_MIN_NOISE_LEVEL(pFilterConfig->SoundActivity.MinNoiseLevel));
+      assert_param(IS_MDF_SAD_HANGOVER_WINDOW(pFilterConfig->SoundActivity.HangoverWindow));
+      assert_param(IS_MDF_SAD_LEARNING_FRAMES(pFilterConfig->SoundActivity.LearningFrames));
+      assert_param(IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(pFilterConfig->SoundActivity.SignalNoiseThreshold));
+      if (pFilterConfig->SoundActivity.Mode != MDF_SAD_SOUND_DETECTOR)
+      {
+        assert_param(IS_MDF_SAD_AMBIENT_NOISE_SLOPE(pFilterConfig->SoundActivity.AmbientNoiseSlope));
+        hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) |
+                                   pFilterConfig->SoundActivity.HangoverWindow |
+                                   pFilterConfig->SoundActivity.LearningFrames |
+                                   (pFilterConfig->SoundActivity.AmbientNoiseSlope << MDF_SADCFGR_ANSLP_Pos) |
+                                   pFilterConfig->SoundActivity.SignalNoiseThreshold);
+      }
+      else
+      {
+        hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) |
+                                   pFilterConfig->SoundActivity.HangoverWindow |
+                                   pFilterConfig->SoundActivity.LearningFrames |
+                                   pFilterConfig->SoundActivity.SignalNoiseThreshold);
+      }
+    }
+    else
+    {
+      /* SAD is not used */
+      hmdf->Instance->SADCR = 0U;
+      hmdf->Instance->SADCFGR = 0U;
+    }
+  }
+
+  /* Update instance state */
+  hmdf->State = HAL_MDF_STATE_ACQUISITION;
+
+  /* Enable sound activity detector if needed only for ADF instance */
+  if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
+  {
+    hmdf->Instance->SADCR |= MDF_SADCR_SADEN;
+  }
+
+  /* Enable filter */
+  hmdf->Instance->DFLTCR |= MDF_DFLTCR_DFLTEN;
+}
+
+/**
+  * @brief  This function handles DMA transfer complete callback.
+  * @param  hdma DMA handle.
+  * @retval None.
+  */
+static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Check if DMA in circular mode */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    hmdf->State = HAL_MDF_STATE_READY;
+  }
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+  hmdf->AcqCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  HAL_MDF_AcqCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  This function handles DMA half transfer complete callback.
+  * @param  hdma DMA handle.
+  * @retval None.
+  */
+static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+  hmdf->AcqHalfCpltCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  HAL_MDF_AcqHalfCpltCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  This function handles DMA error callback.
+  * @param  hdma DMA handle.
+  * @retval None.
+  */
+static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Update error code */
+  hmdf->ErrorCode |= MDF_ERROR_DMA;
+
+#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
+  hmdf->ErrorCallback(hmdf);
+#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
+  HAL_MDF_ErrorCallback(hmdf);
+#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mdios.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mdios.c
new file mode 100644
index 000000000..be42e286e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mdios.c
@@ -0,0 +1,921 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mdios.c
+  * @author  MCD Application Team
+  * @brief   MDIOS HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the MDIOS Peripheral.
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    The MDIOS HAL driver can be used as follow:
+
+    (#) Declare a MDIOS_HandleTypeDef handle structure.
+
+    (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
+        (##) Enable the MDIOS interface clock.
+        (##) MDIOS pins configuration:
+            (+++) Enable clocks for the MDIOS GPIOs.
+            (+++) Configure the MDIOS pins as alternate function.
+        (##) NVIC configuration if you need to use interrupt process:
+            (+++) Configure the MDIOS interrupt priority.
+            (+++) Enable the NVIC MDIOS IRQ handle.
+
+    (#) Program the Port Address and the Preamble Check in the Init structure.
+
+    (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.
+
+    (#) Perform direct slave read/write operations using the following APIs:
+        (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
+        (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
+
+    (#) Get the Master read/write operations flags using the following APIs:
+        (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
+        (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
+
+    (#) Clear the read/write flags using the following APIs:
+        (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
+        (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
+
+    (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
+        the MDIOS will generate an interrupt in the following cases:
+        (##) a DINn register written by the Master
+        (##) a DOUTn register read by the Master
+        (##) an error occur
+
+        (@) A callback is executed for each generated interrupt, so the driver provide the following
+            HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
+        (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
+            and execute the previous callbacks
+
+    (#) Reset the MDIOS peripheral and all related resources by calling the HAL_MDIOS_DeInit() API.
+        (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level resources
+            (GPIO, Clocks, NVIC configuration ...)
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_MDIOS_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_MDIOS_RegisterCallback() to register an interrupt callback.
+
+  Function @ref HAL_MDIOS_RegisterCallback() allows to register following callbacks:
+    (+) WriteCpltCallback  : Write Complete Callback.
+    (+) ReadCpltCallback   : Read Complete Callback.
+    (+) ErrorCallback      : Error Callback.
+    (+) WakeUpCallback     : Wake UP Callback
+    (+) MspInitCallback    : MspInit Callback.
+    (+) MspDeInitCallback  : MspDeInit Callback.
+
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use function @ref HAL_MDIOS_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_MDIOS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) WriteCpltCallback  : Write Complete Callback.
+    (+) ReadCpltCallback   : Read Complete Callback.
+    (+) ErrorCallback      : Error Callback.
+    (+) WakeUpCallback     : Wake UP Callback
+    (+) MspInitCallback    : MspInit Callback.
+    (+) MspDeInitCallback  : MspDeInit Callback.
+
+  By default, after the HAL_MDIOS_Init and when the state is HAL_MDIOS_STATE_RESET
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_MDIOS_WriteCpltCallback(), @ref HAL_MDIOS_ReadCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_MDIOS_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_MDIOS_STATE_READY or HAL_MDIOS_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_MDIOS_RegisterCallback() before calling @ref HAL_MDIOS_DeInit
+  or HAL_MDIOS_Init function.
+
+  When The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined (MDIOS)
+/** @defgroup MDIOS  MDIOS
+  * @brief HAL MDIOS module driver
+  * @{
+  */
+#ifdef HAL_MDIOS_MODULE_ENABLED
+
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define MDIOS_PORT_ADDRESS_SHIFT        ((uint32_t)8)
+#define  MDIOS_ALL_REG_FLAG             ((uint32_t)0xFFFFFFFFU)
+#define  MDIOS_ALL_ERRORS_FLAG          ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
+
+#define MDIOS_DIN_BASE_ADDR             (MDIOS_BASE + 0x100U)
+#define MDIOS_DOUT_BASE_ADDR            (MDIOS_BASE + 0x180U)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios);
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
+  * @{
+  */
+
+/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the MDIOS
+      (+) The following parameters can be configured:
+        (++) Port Address
+        (++) Preamble Check
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the MDIOS according to the specified parameters in
+  *         the MDIOS_InitTypeDef and creates the associated handle .
+  * @param  hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
+  *         the configuration information for MDIOS module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
+{
+  uint32_t tmpcr;
+
+  /* Check the MDIOS handle allocation */
+  if (hmdios == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
+  assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
+  assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+
+  if (hmdios->State == HAL_MDIOS_STATE_RESET)
+  {
+    MDIOS_InitCallbacksToDefault(hmdios);
+
+    if (hmdios->MspInitCallback == NULL)
+    {
+      hmdios->MspInitCallback = HAL_MDIOS_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hmdios->MspInitCallback(hmdios);
+  }
+
+#else
+
+  if (hmdios->State == HAL_MDIOS_STATE_RESET)
+  {
+    /* Init the low level hardware */
+    HAL_MDIOS_MspInit(hmdios);
+  }
+
+#endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */
+
+  /* Change the MDIOS state */
+  hmdios->State = HAL_MDIOS_STATE_BUSY;
+
+  /* Get the MDIOS CR value */
+  tmpcr = hmdios->Instance->CR;
+
+  /* Clear PORT_ADDRESS, DPC and EN bits */
+  tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
+
+  /* Set MDIOS control parameters and enable the peripheral */
+  tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT)    | \
+                      (hmdios->Init.PreambleCheck) | \
+                      (MDIOS_CR_EN));
+
+  /* Write the MDIOS CR */
+  hmdios->Instance->CR = tmpcr;
+
+  hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
+
+  /* Change the MDIOS state */
+  hmdios->State = HAL_MDIOS_STATE_READY;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdios);
+
+  /* Return function status */
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  DeInitializes the MDIOS peripheral.
+  * @param  hmdios: MDIOS handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Check the MDIOS handle allocation */
+  if (hmdios == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
+
+  /* Change the MDIOS state */
+  hmdios->State = HAL_MDIOS_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_MDIOS_DISABLE(hmdios);
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+
+  if (hmdios->MspDeInitCallback == NULL)
+  {
+    hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hmdios->MspDeInitCallback(hmdios);
+#else
+
+  /* DeInit the low level hardware */
+  HAL_MDIOS_MspDeInit(hmdios);
+
+#endif /* (USE_HAL_MDIOS_REGISTER_CALLBACKS) */
+
+  /* Change the MDIOS state */
+  hmdios->State = HAL_MDIOS_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdios);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  MDIOS MSP Init
+  * @param  hmdios: mdios handle
+  * @retval None
+  */
+__weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdios);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MDIOS_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  MDIOS MSP DeInit
+  * @param  hmdios: mdios handle
+  * @retval None
+  */
+__weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdios);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MDIOS_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User MDIOS Callback
+  *         To be used instead of the weak predefined callback
+  * @param hmdios mdios handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
+  *          @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID  Read Complete Callback ID
+  *          @arg @ref HAL_MDIOS_ERROR_CB_ID          Error Callback ID
+  *          @arg @ref HAL_MDIOS_WAKEUP_CB_ID         Wake Up Callback ID
+  *          @arg @ref HAL_MDIOS_MSPINIT_CB_ID        MspInit callback ID
+  *          @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID      MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID,
+                                             pMDIOS_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hmdios);
+
+  if (hmdios->State == HAL_MDIOS_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
+        hmdios->WriteCpltCallback = pCallback;
+        break;
+
+      case HAL_MDIOS_READ_COMPLETE_CB_ID :
+        hmdios->ReadCpltCallback = pCallback;
+        break;
+
+      case HAL_MDIOS_ERROR_CB_ID :
+        hmdios->ErrorCallback = pCallback;
+        break;
+
+      case HAL_MDIOS_WAKEUP_CB_ID :
+        hmdios->WakeUpCallback = pCallback;
+        break;
+
+      case HAL_MDIOS_MSPINIT_CB_ID :
+        hmdios->MspInitCallback = pCallback;
+        break;
+
+      case HAL_MDIOS_MSPDEINIT_CB_ID :
+        hmdios->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hmdios->State == HAL_MDIOS_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_MDIOS_MSPINIT_CB_ID :
+        hmdios->MspInitCallback = pCallback;
+        break;
+
+      case HAL_MDIOS_MSPDEINIT_CB_ID :
+        hmdios->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdios);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an MDIOS Callback
+  *         MDIOS callback is redirected to the weak predefined callback
+  * @param hmdios mdios handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID
+  *          @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID  Read Complete Callback ID
+  *          @arg @ref HAL_MDIOS_ERROR_CB_ID          Error Callback ID
+  *          @arg @ref HAL_MDIOS_WAKEUP_CB_ID         Wake Up Callback ID
+  *          @arg @ref HAL_MDIOS_MSPINIT_CB_ID        MspInit callback ID
+  *          @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID      MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hmdios);
+
+  if (hmdios->State == HAL_MDIOS_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_MDIOS_WRITE_COMPLETE_CB_ID :
+        hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback;
+        break;
+
+      case HAL_MDIOS_READ_COMPLETE_CB_ID :
+        hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback;
+        break;
+
+      case HAL_MDIOS_ERROR_CB_ID :
+        hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback;
+        break;
+
+      case HAL_MDIOS_WAKEUP_CB_ID :
+        hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback;
+        break;
+
+      case HAL_MDIOS_MSPINIT_CB_ID :
+        hmdios->MspInitCallback = HAL_MDIOS_MspInit;
+        break;
+
+      case HAL_MDIOS_MSPDEINIT_CB_ID :
+        hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hmdios->State == HAL_MDIOS_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_MDIOS_MSPINIT_CB_ID :
+        hmdios->MspInitCallback = HAL_MDIOS_MspInit;
+        break;
+
+      case HAL_MDIOS_MSPDEINIT_CB_ID :
+        hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hmdios->ErrorCode |= HAL_MDIOS_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdios);
+
+  return status;
+}
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
+  *  @brief MDIOS Read/Write functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the MDIOS
+    read and write operations.
+
+    (#) APIs that allow to the MDIOS to read/write from/to the
+        values of one of the DINn/DOUTn registers:
+        (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
+        (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
+
+    (#) APIs that provide if there are some Slave registres have been
+        read or written by the Master:
+        (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
+        (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
+
+    (#) APIs that Clear the read/write flags:
+        (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
+        (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()
+
+    (#) A set of Callbacks are provided:
+        (+) HAL_MDIOS_WriteCpltCallback()
+        (+) HAL_MDIOS_ReadCpltCallback()
+        (+) HAL_MDIOS_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes to an MDIOS output register
+  * @param  hmdios: mdios handle
+  * @param  RegNum: MDIOS output register address
+  * @param  Data: Data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_MDIOS_REGISTER(RegNum));
+
+  /* Process Locked */
+  __HAL_LOCK(hmdios);
+
+  /* Get the addr of output register to be written by the MDIOS */
+  tmpreg = MDIOS_DOUT_BASE_ADDR + (4U * RegNum);
+
+  /* Write to DOUTn register */
+  *((uint32_t *)tmpreg) = Data;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hmdios);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads an MDIOS input register
+  * @param  hmdios: mdios handle
+  * @param  RegNum: MDIOS input register address
+  * @param  pData: pointer to Data
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_MDIOS_REGISTER(RegNum));
+
+  /* Process Locked */
+  __HAL_LOCK(hmdios);
+
+  /* Get the addr of input register to be read by the MDIOS */
+  tmpreg = MDIOS_DIN_BASE_ADDR + (4U * RegNum);
+
+  /* Read DINn register */
+  *pData = (uint16_t)(*((uint32_t *)tmpreg));
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hmdios);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets Written registers by MDIO master
+  * @param  hmdios: mdios handle
+  * @retval bit map of written registers addresses
+  */
+uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios)
+{
+  return hmdios->Instance->WRFR;
+}
+
+/**
+  * @brief  Gets Read registers by MDIO master
+  * @param  hmdios: mdios handle
+  * @retval bit map of read registers addresses
+  */
+uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios)
+{
+  return hmdios->Instance->RDFR;
+}
+
+/**
+  * @brief  Clears Write registers flag
+  * @param  hmdios: mdios handle
+  * @param  RegNum: registers addresses to be cleared
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
+{
+  /* Check the parameters */
+  assert_param(IS_MDIOS_REGISTER(RegNum));
+
+  /* Process Locked */
+  __HAL_LOCK(hmdios);
+
+  /* Clear write registers flags */
+  hmdios->Instance->CWRFR |= (RegNum);
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdios);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clears Read register flag
+  * @param  hmdios: mdios handle
+  * @param  RegNum: registers addresses to be cleared
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
+{
+  /* Check the parameters */
+  assert_param(IS_MDIOS_REGISTER(RegNum));
+
+  /* Process Locked */
+  __HAL_LOCK(hmdios);
+
+  /* Clear read registers flags */
+  hmdios->Instance->CRDFR |= (RegNum);
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdios);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables Events for MDIOS peripheral
+  * @param  hmdios: mdios handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Process Locked */
+  __HAL_LOCK(hmdios);
+
+  /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
+  __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hmdios);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles MDIOS interrupt request.
+  * @param hmdios: MDIOS handle
+  * @retval None
+  */
+void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Write Register Interrupt enabled ? */
+  if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != (uint32_t)RESET)
+  {
+    /* Write register flag */
+    if (HAL_MDIOS_GetWrittenRegAddress(hmdios) != (uint32_t)RESET)
+    {
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+      /*Call registered Write complete callback*/
+      hmdios->WriteCpltCallback(hmdios);
+#else
+      /* Write callback function */
+      HAL_MDIOS_WriteCpltCallback(hmdios);
+#endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
+      /* Clear write register flag */
+      hmdios->Instance->CWRFR = MDIOS_ALL_REG_FLAG;
+    }
+  }
+
+  /* Read Register Interrupt enabled ? */
+  if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != (uint32_t)RESET)
+  {
+    /* Read register flag */
+    if (HAL_MDIOS_GetReadRegAddress(hmdios) != (uint32_t)RESET)
+    {
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+      /*Call registered Read complete callback*/
+      hmdios->ReadCpltCallback(hmdios);
+#else
+      /* Read callback function  */
+      HAL_MDIOS_ReadCpltCallback(hmdios);
+#endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
+      /* Clear read register flag */
+      hmdios->Instance->CRDFR = MDIOS_ALL_REG_FLAG;
+    }
+  }
+
+  /* Error Interrupt enabled ? */
+  if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != (uint32_t)RESET)
+  {
+    /* All Errors Flag */
+    if (__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) != (uint32_t)RESET)
+    {
+      hmdios->ErrorCode |= HAL_MDIOS_ERROR_DATA;
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+      /*Call registered Error callback*/
+      hmdios->ErrorCallback(hmdios);
+#else
+      /* Error Callback */
+      HAL_MDIOS_ErrorCallback(hmdios);
+#endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
+      /* Clear errors flag */
+      __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
+    }
+    hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
+  }
+  /* check MDIOS WAKEUP exti flag */
+  if (__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+  {
+    /* Clear MDIOS WAKEUP Exti pending bit */
+    __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+    /*Call registered WakeUp callback*/
+    hmdios->WakeUpCallback(hmdios);
+#else
+    /* MDIOS WAKEUP callback */
+    HAL_MDIOS_WakeUpCallback(hmdios);
+#endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+  }
+
+}
+
+/**
+  * @brief  Write Complete Callback
+  * @param  hmdios: mdios handle
+  * @retval None
+  */
+__weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdios);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Read Complete Callback
+  * @param  hmdios: mdios handle
+  * @retval None
+  */
+__weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdios);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Error Callback
+  * @param hmdios: mdios handle
+  * @retval None
+  */
+__weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdios);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MDIOS_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  MDIOS WAKEUP interrupt callback
+  * @param hmdios: mdios handle
+  * @retval None
+  */
+__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmdios);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MDIOS_WakeUpCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   MDIOS control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the MDIOS.
+     (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
+     (+) HAL_MDIOS_GetError() API, returns the errors code of the HAL state machine.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Gets MDIOS error code
+  * @param  hmdios: mdios handle
+  * @retval mdios error code
+  */
+uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios)
+{
+  /* return the error code */
+  return hmdios->ErrorCode;
+}
+
+/**
+  * @brief  Return the MDIOS HAL state
+  * @param  hmdios: mdios handle
+  * @retval HAL state
+  */
+HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios)
+{
+  /* Return MDIOS state */
+  return hmdios->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios)
+{
+  /* Init the MDIOS Callback settings */
+  hmdios->WriteCpltCallback  = HAL_MDIOS_WriteCpltCallback;   /* Legacy weak WriteCpltCallback   */
+  hmdios->ReadCpltCallback   = HAL_MDIOS_ReadCpltCallback;    /* Legacy weak ReadCpltCallback   */
+  hmdios->ErrorCallback      = HAL_MDIOS_ErrorCallback;       /* Legacy weak ErrorCallback */
+  hmdios->WakeUpCallback     = HAL_MDIOS_WakeUpCallback;      /* Legacy weak WakeUpCallback   */
+}
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+/**
+  * @}
+  */
+#endif /* MDIOS */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mmc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mmc.c
new file mode 100644
index 000000000..6eefd7de4
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mmc.c
@@ -0,0 +1,5918 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mmc.c
+  * @author  MCD Application Team
+  * @brief   MMC card HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (MMC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + MMC card Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to
+    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+    the user in HAL_MMC_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDMMC memories which uses the HAL
+    SDMMC driver functions to interface with MMC and eMMC cards devices.
+    It is used as follows:
+
+    (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
+        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+        (##) SDMMC pins configuration for MMC card
+            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
+             and HAL_MMC_WriteBlocks_IT() APIs).
+            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+                  and __HAL_MMC_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
+                  and __HAL_MMC_CLEAR_IT()
+        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
+
+    (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
+
+  *** MMC Card Initialization and configuration ***
+  ================================================
+  [..]
+    To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
+    SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
+    This function provide the following operations:
+
+    (#) Initialize the SDMMC peripheral interface with default configuration.
+        The initialization process is done at 400KHz. You can change or adapt
+        this frequency by adjusting the "ClockDiv" field.
+        The MMC Card frequency (SDMMC_CK) is computed as follows:
+
+           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+        In initialization mode and according to the MMC Card standard,
+        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+        This phase of initialization is done through SDMMC_Init() and
+        SDMMC_PowerState_ON() SDMMC low level APIs.
+
+    (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
+        This phase allows the card initialization and identification
+        and check the MMC Card type (Standard Capacity or High Capacity)
+        The initialization flow is compatible with MMC standard.
+
+        This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
+        of plug-off plug-in.
+
+    (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
+        frequency by adjusting the "ClockDiv" field.
+        In transfer mode and according to the MMC Card standard, make sure that the
+        SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
+
+    (#) Select the corresponding MMC Card according to the address read with the step 2.
+
+    (#) Configure the MMC Card in wide bus mode: 4-bits data.
+    (#) Select the MMC Card partition using HAL_MMC_SwitchPartition()
+
+  *** MMC Card Read operation ***
+  ==============================
+  [..]
+    (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetCardState() function for MMC card state.
+
+    (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetCardState() function for MMC card state.
+        You could also check the DMA transfer process through the MMC Rx interrupt event.
+
+    (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetCardState() function for MMC card state.
+        You could also check the IT transfer process through the MMC Rx interrupt event.
+
+  *** MMC Card Write operation ***
+  ===============================
+  [..]
+    (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetCardState() function for MMC card state.
+
+    (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 byte).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetCardState() function for MMC card state.
+        You could also check the DMA transfer process through the MMC Tx interrupt event.
+
+    (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
+        This function allows the read of 512 bytes blocks.
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetCardState() function for MMC card state.
+        You could also check the IT transfer process through the MMC Tx interrupt event.
+
+  *** MMC card information ***
+  ===========================
+  [..]
+    (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
+        It returns useful information about the MMC card such as block size, card type,
+        block number ...
+
+  *** MMC card CSD register ***
+  ============================
+  [..]
+    (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** MMC card CID register ***
+  ============================
+  [..]
+    (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
+        Some of the CID parameters are useful for card initialization and identification.
+
+  *** MMC Card Reply Protected Memory Block (RPMB) Key Programming operation ***
+  ==============================
+  [..]
+    (+) You can program the authentication key of RPMB area in polling mode by using function
+        HAL_MMC_RPMB_ProgramAuthenticationKey().
+        This function is only used once during the life of an MMC card.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetRPMBError() function for operation state.
+    (+) You can program the authentication key of RPMB area in Interrupt mode by using function
+        HAL_MMC_RPMB_ProgramAuthenticationKey_IT().
+        This function is only used once during the life of an MMC card.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetRPMBError() function for operation state.
+
+  *** MMC Card Reply Protected Memory Block (RPMB) write counter operation ***
+  ==============================
+  [..]
+    (+) You can get the write counter value of RPMB area in polling mode by using function
+        HAL_MMC_RPMB_GetWriteCounter().
+    (+) You can get the write counter value of RPMB area in Interrupt mode by using function
+        HAL_MMC_RPMB_GetWriteCounter_IT().
+
+  *** MMC Card Reply Protected Memory Block (RPMB) write operation ***
+  ==============================
+  [..]
+    (+) You can write to the RPMB area of MMC card in polling mode by using function
+        HAL_MMC_WriteBlocks().
+        This function supports the one, two, or thirty two blocks write operation
+        (with 512-bytes block length).
+        You can choose the number of blocks at the multiple block read operation by adjusting
+        the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetRPMBError() function for operation state.
+    (+) You can write to the RPMB area of MMC card in Interrupt mode by using function
+        HAL_MMC_WriteBlocks_IT().
+        This function supports the one, two, or thirty two blocks write operation
+        (with 512-bytes block length).
+        You can choose the number of blocks at the multiple block read operation by adjusting
+        the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetRPMBError() function for operation state.
+
+  *** MMC Card Reply Protected Memory Block (RPMB) read operation ***
+  ==============================
+  [..]
+    (+) You can read from the RPMB area of MMC card in polling mode by using function
+        HAL_MMC_RPMB_ReadBlocks().
+        The block size should be chosen as multiple of 512 bytes.
+        You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetRPMBError() function for MMC card state.
+    (+) You can read from the RPMB area of MMC card in Interrupt mode by using function
+        HAL_MMC_RPMB_ReadBlocks_IT().
+        The block size should be chosen as multiple of 512 bytes.
+        You can choose the number of blocks by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_MMC_GetRPMBError() function for MMC card state.
+
+  *** MMC HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in MMC HAL driver.
+
+    (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
+    (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
+    (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
+    (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
+
+  [..]
+    (@) You can refer to the MMC HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_MMC_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) Read_DMALnkLstBufCpltCallback : callback when the DMA reception of linked list node buffer is completed.
+      (+) Write_DMALnkLstBufCpltCallback : callback when the DMA transmission of linked list node buffer is completed.
+      (+) MspInitCallback    : MMC MspInit.
+      (+) MspDeInitCallback  : MMC MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
+      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
+      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
+      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
+      (+) MspInitCallback    : MMC MspInit.
+      (+) MspDeInitCallback  : MMC MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+    By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (overridden) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (overridden) functions in the HAL_MMC_Init
+    and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit
+    or HAL_MMC_Init function.
+
+    When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MMC MMC
+  * @brief MMC HAL module driver
+  * @{
+  */
+
+#if defined (SDMMC1) || defined (SDMMC2)
+#ifdef HAL_MMC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup MMC_Private_Defines
+  * @{
+  */
+#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
+#define MMC_VOLTAGE_RANGE               EMMC_LOW_VOLTAGE_RANGE
+
+#define MMC_EXT_CSD_PWR_CL_26_INDEX     201
+#define MMC_EXT_CSD_PWR_CL_52_INDEX     200
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238
+
+#define MMC_EXT_CSD_PWR_CL_26_POS       8
+#define MMC_EXT_CSD_PWR_CL_52_POS       0
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS   16
+#else
+#define MMC_VOLTAGE_RANGE               EMMC_HIGH_VOLTAGE_RANGE
+
+#define MMC_EXT_CSD_PWR_CL_26_INDEX     203
+#define MMC_EXT_CSD_PWR_CL_52_INDEX     202
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239
+
+#define MMC_EXT_CSD_PWR_CL_26_POS       24
+#define MMC_EXT_CSD_PWR_CL_52_POS       16
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS   24
+#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/
+
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS   0
+#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX             217
+#define MMC_EXT_CSD_S_A_TIMEOUT_POS               8
+
+/* Frequencies used in the driver for clock divider calculation */
+#define MMC_INIT_FREQ                   400000U   /* Initialization phase : 400 kHz max */
+#define MMC_HIGH_SPEED_FREQ             52000000U /* High speed phase : 52 MHz max */
+
+/* The Data elements' postitions in the frame Frame for RPMB area */
+#define MMC_RPMB_KEYMAC_POSITION         196U
+#define MMC_RPMB_DATA_POSITION           228U
+#define MMC_RPMB_NONCE_POSITION          484U
+#define MMC_RPMB_WRITE_COUNTER_POSITION  500U
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+  * @{
+  */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
+static void     MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
+static void     MMC_Write_IT(MMC_HandleTypeDef *hmmc);
+static void     MMC_Read_IT(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
+static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex,
+                                        uint32_t Timeout);
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed);
+
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MMC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup MMC_Exported_Functions_Group1
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize the MMC
+    card device to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the MMC according to the specified parameters in the
+            MMC_HandleTypeDef and create the associated handle.
+  * @param  hmmc: Pointer to the MMC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
+{
+  /* Check the MMC handle allocation */
+  if (hmmc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
+  assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
+
+  if (hmmc->State == HAL_MMC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hmmc->Lock = HAL_UNLOCKED;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_MMC_STATE_RESET only */
+    hmmc->TxCpltCallback    = HAL_MMC_TxCpltCallback;
+    hmmc->RxCpltCallback    = HAL_MMC_RxCpltCallback;
+    hmmc->ErrorCallback     = HAL_MMC_ErrorCallback;
+    hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+    hmmc->Read_DMALnkLstBufCpltCallback  = HAL_MMCEx_Read_DMALnkLstBufCpltCallback;
+    hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback;
+
+    if (hmmc->MspInitCallback == NULL)
+    {
+      hmmc->MspInitCallback = HAL_MMC_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hmmc->MspInitCallback(hmmc);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_MMC_MspInit(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+  }
+
+  hmmc->State = HAL_MMC_STATE_BUSY;
+
+  /* Initialize the Card parameters */
+  if (HAL_MMC_InitCard(hmmc) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Initialize the error code */
+  hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the MMC operation */
+  hmmc->Context = MMC_CONTEXT_NONE;
+
+  /* Initialize the MMC state */
+  hmmc->State = HAL_MMC_STATE_READY;
+
+  /* Configure bus width */
+  if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B)
+  {
+    if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MMC Card.
+  * @param  hmmc: Pointer to MMC handle
+  * @note   This function initializes the MMC card. It could be used when a card
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t errorstate;
+  MMC_InitTypeDef Init;
+  uint32_t sdmmc_clk;
+
+  /* Default SDMMC peripheral configuration for MMC card initialization */
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+
+  /* Init Clock should be less or equal to 400Khz*/
+  if (hmmc->Instance == SDMMC1)
+  {
+    sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+  }
+  else if (hmmc->Instance == SDMMC2)
+  {
+    sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2);
+  }
+  else
+  {
+    sdmmc_clk = 0;
+  }
+  if (sdmmc_clk == 0U)
+  {
+    hmmc->State = HAL_MMC_STATE_READY;
+    hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+    return HAL_ERROR;
+  }
+  Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
+#endif /* USE_SD_TRANSCEIVER */
+
+  /* Initialize SDMMC peripheral interface with default configuration */
+  (void)SDMMC_Init(hmmc->Instance, Init);
+
+  /* Set Power State to ON */
+  (void)SDMMC_PowerState_ON(hmmc->Instance);
+
+  /* wait 74 Cycles: required power up waiting time before starting
+     the MMC initialization sequence */
+  if (Init.ClockDiv != 0U)
+  {
+    sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+  }
+
+  if (sdmmc_clk != 0U)
+  {
+    HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+  }
+
+  /* Identify card operating voltage */
+  errorstate = MMC_PowerON(hmmc);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    hmmc->State = HAL_MMC_STATE_READY;
+    hmmc->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Card initialization */
+  errorstate = MMC_InitCard(hmmc);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    hmmc->State = HAL_MMC_STATE_READY;
+    hmmc->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+    hmmc->ErrorCode |= errorstate;
+    hmmc->State = HAL_MMC_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the MMC card.
+  * @param  hmmc: Pointer to MMC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
+{
+  /* Check the MMC handle allocation */
+  if (hmmc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
+
+  hmmc->State = HAL_MMC_STATE_BUSY;
+
+  /* Set MMC power state to off */
+  MMC_PowerOFF(hmmc);
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+  if (hmmc->MspDeInitCallback == NULL)
+  {
+    hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hmmc->MspDeInitCallback(hmmc);
+#else
+  /* De-Initialize the MSP layer */
+  HAL_MMC_MspDeInit(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+
+  hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+  hmmc->State = HAL_MMC_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MMC MSP.
+  * @param  hmmc: Pointer to MMC handle
+  * @retval None
+  */
+__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MMC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize MMC MSP.
+  * @param  hmmc: Pointer to MMC handle
+  * @retval None
+  */
+__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MMC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MMC_Exported_Functions_Group2
+  *  @brief   Data transfer functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the data
+    transfer from/to MMC card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of MMC blocks to read
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks,
+                                     uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if (NULL == pData)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
+         & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= MMC_BLOCKSIZE;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Read block(s) in polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+    }
+    else
+    {
+      hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+    }
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Poll on SDMMC flags */
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = SDMMC_ReadFIFO(hmmc->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Send stop transmission command in case of multiblock read */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      /* Send stop transmission command */
+      errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+      if (errorstate != HAL_MMC_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in a card. The Data
+  *         transfer is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of MMC blocks to write
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
+                                      uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t add = BlockAdd;
+  const uint8_t *tempbuff = pData;
+
+  if (NULL == pData)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= MMC_BLOCKSIZE;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+    }
+    else
+    {
+      hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
+    }
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = (uint32_t)(*tempbuff);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 8U);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 16U);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 24U);
+          tempbuff++;
+          (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Send stop transmission command in case of multiblock write */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      /* Send stop transmission command */
+      errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+      if (errorstate != HAL_MMC_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @note   You could also check the IT transfer process through the MMC Rx
+  *         interrupt event.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    hmmc->pRxBuffPtr = pData;
+    hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= MMC_BLOCKSIZE;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Read Blocks in IT mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+    }
+    else
+    {
+      hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+    }
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+                               SDMMC_FLAG_RXFIFOHF));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @note   You could also check the IT transfer process through the MMC Tx
+  *         interrupt event.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
+                                         uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    hmmc->pTxBuffPtr = pData;
+    hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= MMC_BLOCKSIZE;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+    }
+    else
+    {
+      hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
+    }
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+                               SDMMC_FLAG_TXFIFOHE));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @note   You could also check the DMA transfer process through the MMC Rx
+  *         interrupt event.
+  * @param  hmmc: Pointer MMC handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    hmmc->pRxBuffPtr = pData;
+    hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= MMC_BLOCKSIZE;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+    hmmc->Instance->IDMABASER = (uint32_t) pData ;
+    hmmc->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+    /* Read Blocks in DMA mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+    }
+    else
+    {
+      hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+    }
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode = errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @note   You could also check the DMA transfer process through the MMC Tx
+  *         interrupt event.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
+                                          uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    hmmc->pTxBuffPtr = pData;
+    hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= MMC_BLOCKSIZE;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    hmmc->Instance->IDMABASER = (uint32_t) pData ;
+    hmmc->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+    }
+    else
+    {
+      hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
+    }
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Erases the specified memory area of the given MMC card.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @param  hmmc: Pointer to MMC handle
+  * @param  BlockStartAdd: Start Block address
+  * @param  BlockEndAdd: End Block address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+  uint32_t errorstate;
+  uint32_t start_add = BlockStartAdd;
+  uint32_t end_add = BlockEndAdd;
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    if (end_add < start_add)
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+      return HAL_ERROR;
+    }
+
+    if (end_add > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
+         & 0x000000FFU) != 0x0U)
+    {
+      if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Check if the card command class supports erase command */
+    if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      start_add *= MMC_BLOCKSIZE;
+      end_add   *= MMC_BLOCKSIZE;
+    }
+
+    /* Send CMD35 MMC_ERASE_GRP_START with argument as addr  */
+    errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Send CMD36 MMC_ERASE_GRP_END with argument as addr  */
+    errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Send CMD38 ERASE */
+    errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles MMC card interrupt request.
+  * @param  hmmc: Pointer to MMC handle
+  * @retval None
+  */
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t errorstate;
+  uint32_t context = hmmc->Context;
+
+  /* Check for SDMMC interrupt flags */
+  if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+  {
+    MMC_Read_IT(hmmc);
+  }
+
+  else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
+  {
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
+
+    __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                         SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE | \
+                         SDMMC_IT_RXFIFOHF);
+
+    __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    if ((context & MMC_CONTEXT_DMA) != 0U)
+    {
+      hmmc->Instance->DLEN = 0;
+      hmmc->Instance->DCTRL = 0;
+      hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
+
+      /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+      if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+          hmmc->ErrorCallback(hmmc);
+#else
+          HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+      hmmc->State = HAL_MMC_STATE_READY;
+      if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+        hmmc->TxCpltCallback(hmmc);
+#else
+        HAL_MMC_TxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+      }
+      if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+        hmmc->RxCpltCallback(hmmc);
+#else
+        HAL_MMC_RxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+      }
+    }
+    else if ((context & MMC_CONTEXT_IT) != 0U)
+    {
+      /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+      if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+          hmmc->ErrorCallback(hmmc);
+#else
+          HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+      hmmc->State = HAL_MMC_STATE_READY;
+      if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+        hmmc->RxCpltCallback(hmmc);
+#else
+        HAL_MMC_RxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+        hmmc->TxCpltCallback(hmmc);
+#else
+        HAL_MMC_TxCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+  {
+    MMC_Write_IT(hmmc);
+  }
+
+  else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL |
+                              SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
+  {
+    /* Set Error code */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+    }
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+    }
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+    }
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+    }
+
+    /* Clear All flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Disable all interrupts */
+    __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                         SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+    hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+    hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP;
+    hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+    hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT);
+
+    if ((context & MMC_CONTEXT_IT) != 0U)
+    {
+      /* Set the MMC state to ready to be able to start again the process */
+      hmmc->State = HAL_MMC_STATE_READY;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+      hmmc->ErrorCallback(hmmc);
+#else
+      HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+    }
+    else if ((context & MMC_CONTEXT_DMA) != 0U)
+    {
+      if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+      {
+        /* Disable Internal DMA */
+        __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
+        hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+        /* Set the MMC state to ready to be able to start again the process */
+        hmmc->State = HAL_MMC_STATE_READY;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+        hmmc->ErrorCallback(hmmc);
+#else
+        HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
+  {
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
+
+    if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+    {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+      hmmc->Write_DMALnkLstBufCpltCallback(hmmc);
+#else
+      HAL_MMCEx_Write_DMALnkLstBufCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+    }
+    else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
+    {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+      hmmc->Read_DMALnkLstBufCpltCallback(hmmc);
+#else
+      HAL_MMCEx_Read_DMALnkLstBufCpltCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+    }
+  }
+
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief return the MMC state
+  * @param hmmc: Pointer to mmc handle
+  * @retval HAL state
+  */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc)
+{
+  return hmmc->State;
+}
+
+/**
+  * @brief  Return the MMC error code
+  * @param  hmmc : Pointer to a MMC_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval MMC Error Code
+  */
+uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc)
+{
+  return hmmc->ErrorCode;
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hmmc: Pointer to MMC handle
+  * @retval None
+  */
+__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MMC_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hmmc: Pointer MMC handle
+  * @retval None
+  */
+__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MMC_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief MMC error callbacks
+  * @param hmmc: Pointer MMC handle
+  * @retval None
+  */
+__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MMC_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief MMC Abort callbacks
+  * @param hmmc: Pointer MMC handle
+  * @retval None
+  */
+__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MMC_AbortCallback can be implemented in the user file
+   */
+}
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User MMC Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @note   The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in
+  *         HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID
+  *         and HAL_MMC_MSP_DEINIT_CB_ID.
+  * @param hmmc : MMC handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_MMC_TX_CPLT_CB_ID                 MMC Tx Complete Callback ID
+  *          @arg @ref HAL_MMC_RX_CPLT_CB_ID                 MMC Rx Complete Callback ID
+  *          @arg @ref HAL_MMC_ERROR_CB_ID                   MMC Error Callback ID
+  *          @arg @ref HAL_MMC_ABORT_CB_ID                   MMC Abort Callback ID
+  *          @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID  MMC DMA Rx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_MMC_MSP_INIT_CB_ID                MMC MspInit Callback ID
+  *          @arg @ref HAL_MMC_MSP_DEINIT_CB_ID              MMC MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+                                           pMMC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+      case HAL_MMC_TX_CPLT_CB_ID :
+        hmmc->TxCpltCallback = pCallback;
+        break;
+      case HAL_MMC_RX_CPLT_CB_ID :
+        hmmc->RxCpltCallback = pCallback;
+        break;
+      case HAL_MMC_ERROR_CB_ID :
+        hmmc->ErrorCallback = pCallback;
+        break;
+      case HAL_MMC_ABORT_CB_ID :
+        hmmc->AbortCpltCallback = pCallback;
+        break;
+      case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hmmc->Read_DMALnkLstBufCpltCallback = pCallback;
+        break;
+      case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hmmc->Write_DMALnkLstBufCpltCallback = pCallback;
+        break;
+      case HAL_MMC_MSP_INIT_CB_ID :
+        hmmc->MspInitCallback = pCallback;
+        break;
+      case HAL_MMC_MSP_DEINIT_CB_ID :
+        hmmc->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hmmc->State == HAL_MMC_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_MMC_MSP_INIT_CB_ID :
+        hmmc->MspInitCallback = pCallback;
+        break;
+      case HAL_MMC_MSP_DEINIT_CB_ID :
+        hmmc->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User MMC Callback
+  *         MMC Callback is redirected to the weak (overridden) predefined callback
+  * @note   The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in
+  *         HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID
+  *         and HAL_MMC_MSP_DEINIT_CB_ID.
+  * @param hmmc : MMC handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_MMC_TX_CPLT_CB_ID                 MMC Tx Complete Callback ID
+  *          @arg @ref HAL_MMC_RX_CPLT_CB_ID                 MMC Rx Complete Callback ID
+  *          @arg @ref HAL_MMC_ERROR_CB_ID                   MMC Error Callback ID
+  *          @arg @ref HAL_MMC_ABORT_CB_ID                   MMC Abort Callback ID
+  *          @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID  MMC DMA Rx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_MMC_MSP_INIT_CB_ID                MMC MspInit Callback ID
+  *          @arg @ref HAL_MMC_MSP_DEINIT_CB_ID              MMC MspDeInit Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+      case HAL_MMC_TX_CPLT_CB_ID :
+        hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+        break;
+      case HAL_MMC_RX_CPLT_CB_ID :
+        hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+        break;
+      case HAL_MMC_ERROR_CB_ID :
+        hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+        break;
+      case HAL_MMC_ABORT_CB_ID :
+        hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+        break;
+      case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hmmc->Read_DMALnkLstBufCpltCallback = HAL_MMCEx_Read_DMALnkLstBufCpltCallback;
+        break;
+      case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback;
+        break;
+      case HAL_MMC_MSP_INIT_CB_ID :
+        hmmc->MspInitCallback = HAL_MMC_MspInit;
+        break;
+      case HAL_MMC_MSP_DEINIT_CB_ID :
+        hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hmmc->State == HAL_MMC_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_MMC_MSP_INIT_CB_ID :
+        hmmc->MspInitCallback = HAL_MMC_MspInit;
+        break;
+      case HAL_MMC_MSP_DEINIT_CB_ID :
+        hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup MMC_Exported_Functions_Group3
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the MMC card
+    operations and get the related information
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CID register.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pCID: Pointer to a HAL_MMC_CIDTypedef structure that
+  *         contains all CID register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
+{
+  pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
+
+  pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
+
+  pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
+
+  pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
+
+  pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
+
+  pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
+
+  pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
+
+  pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
+
+  pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
+
+  pCID->Reserved2 = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CSD register.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
+  *         contains all CSD register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
+{
+  uint32_t block_nbr = 0;
+
+  pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
+
+  pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
+
+  pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
+
+  pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
+
+  pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
+
+  pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
+
+  pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
+
+  pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
+
+  pCSD->PartBlockRead   = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
+
+  pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
+
+  pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
+
+  pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
+
+  pCSD->Reserved2 = 0U; /*!< Reserved */
+
+  if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
+  {
+    return HAL_ERROR;
+  }
+
+  if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
+  {
+    pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
+
+    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
+
+    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
+
+    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
+
+    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
+
+    pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
+
+    hmmc->MmcCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+    hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+    hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+    hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / MMC_BLOCKSIZE);
+    hmmc->MmcCard.LogBlockSize = MMC_BLOCKSIZE;
+  }
+  else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
+  {
+    hmmc->MmcCard.BlockNbr = block_nbr;
+    hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
+    hmmc->MmcCard.BlockSize = MMC_BLOCKSIZE;
+    hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+    hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+    hmmc->State = HAL_MMC_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
+
+  pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
+
+  pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
+
+  pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
+
+  pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
+
+  pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
+
+  pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
+
+  pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
+
+  pCSD->Reserved3 = 0;
+
+  pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
+
+  pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
+
+  pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
+
+  pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
+
+  pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
+
+  pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
+
+  pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
+
+  pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
+
+  pCSD->Reserved4 = 1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the MMC card info.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
+  *         will contain the MMC card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
+{
+  pCardInfo->CardType     = (uint32_t)(hmmc->MmcCard.CardType);
+  pCardInfo->Class        = (uint32_t)(hmmc->MmcCard.Class);
+  pCardInfo->RelCardAdd   = (uint32_t)(hmmc->MmcCard.RelCardAdd);
+  pCardInfo->BlockNbr     = (uint32_t)(hmmc->MmcCard.BlockNbr);
+  pCardInfo->BlockSize    = (uint32_t)(hmmc->MmcCard.BlockSize);
+  pCardInfo->LogBlockNbr  = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
+  pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the Extended CSD register.
+  * @param  hmmc Pointer to MMC handle
+  * @param  pExtCSD Pointer to a memory area (512 bytes) that contains all
+  *         Extended CSD register parameters
+  * @param  Timeout Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t dataremaining;
+  uint32_t *tmp_buf;
+
+  if (NULL == pExtCSD)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0;
+
+    /* Initiaize the destination pointer */
+    tmp_buf = pExtCSD;
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Send ExtCSD Read command to Card */
+    errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Poll on SDMMC flags */
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR |
+                               SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance);
+          tmp_buf++;
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+    hmmc->State = HAL_MMC_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by
+  *         card.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  WideMode: Specifies the MMC card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
+{
+  uint32_t count;
+  SDMMC_InitTypeDef Init;
+  uint32_t errorstate;
+  uint32_t response = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+
+  /* Change State */
+  hmmc->State = HAL_MMC_STATE_BUSY;
+
+  /* Check and update the power class if needed */
+  if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
+  {
+    if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
+    {
+      errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DDR);
+    }
+    else
+    {
+      errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_HIGH);
+    }
+  }
+  else
+  {
+    errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT);
+  }
+
+  if (errorstate == HAL_MMC_ERROR_NONE)
+  {
+    if (WideMode == SDMMC_BUS_WIDE_8B)
+    {
+      errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_4B)
+    {
+      errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_1B)
+    {
+      errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      errorstate = HAL_MMC_ERROR_PARAM;
+    }
+
+    /* Check for switch error and violation of the trial number of sending CMD 13 */
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+      count = SDMMC_MAX_TRIAL;
+      do
+      {
+        errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          break;
+        }
+
+        /* Get command response */
+        response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+        count--;
+      } while (((response & 0x100U) == 0U) && (count != 0U));
+
+      /* Check the status after the switch command execution */
+      if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+      {
+        /* Check the bit SWITCH_ERROR of the device status */
+        if ((response & 0x80U) != 0U)
+        {
+          errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+        }
+        else
+        {
+          /* Configure the SDMMC peripheral */
+          Init = hmmc->Init;
+          Init.BusWide = WideMode;
+          (void)SDMMC_Init(hmmc->Instance, Init);
+        }
+      }
+      else if (count == 0U)
+      {
+        errorstate = SDMMC_ERROR_TIMEOUT;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+
+  /* Change State */
+  hmmc->State = HAL_MMC_STATE_READY;
+
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+    hmmc->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the speed bus mode
+  * @param  hmmc: Pointer to the MMC handle
+  * @param  SpeedMode: Specifies the MMC card speed bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
+  *            @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz)
+  *            @arg SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz)
+  *            @arg SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz)
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t device_type;
+  uint32_t errorstate;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
+
+  /* Change State */
+  hmmc->State = HAL_MMC_STATE_BUSY;
+
+  /* Field DEVICE_TYPE [196 = 49*4] of Extended CSD register */
+  device_type = (hmmc->Ext_CSD[49] & 0x000000FFU);
+
+  switch (SpeedMode)
+  {
+    case SDMMC_SPEED_MODE_AUTO:
+    {
+      if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
+      {
+        /* High Speed DDR mode allowed */
+        errorstate = MMC_HighSpeed(hmmc, ENABLE);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+        }
+        else
+        {
+          if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
+          {
+            /* DDR mode not supported with CLKDIV = 0 */
+            errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+            if (errorstate != HAL_MMC_ERROR_NONE)
+            {
+              hmmc->ErrorCode |= errorstate;
+            }
+          }
+        }
+      }
+      else if ((device_type & 0x02U) != 0U)
+      {
+        /* High Speed mode allowed */
+        errorstate = MMC_HighSpeed(hmmc, ENABLE);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+        }
+      }
+      else
+      {
+        /* Nothing to do : keep current speed */
+      }
+      break;
+    }
+    case SDMMC_SPEED_MODE_DDR:
+    {
+      if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
+      {
+        /* High Speed DDR mode allowed */
+        errorstate = MMC_HighSpeed(hmmc, ENABLE);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+        }
+        else
+        {
+          if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
+          {
+            /* DDR mode not supported with CLKDIV = 0 */
+            errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+            if (errorstate != HAL_MMC_ERROR_NONE)
+            {
+              hmmc->ErrorCode |= errorstate;
+            }
+          }
+        }
+      }
+      else
+      {
+        /* High Speed DDR mode not allowed */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+        status = HAL_ERROR;
+      }
+      break;
+    }
+    case SDMMC_SPEED_MODE_HIGH:
+    {
+      if ((device_type & 0x02U) != 0U)
+      {
+        /* High Speed mode allowed */
+        errorstate = MMC_HighSpeed(hmmc, ENABLE);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+        }
+      }
+      else
+      {
+        /* High Speed mode not allowed */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+        status = HAL_ERROR;
+      }
+      break;
+    }
+    case SDMMC_SPEED_MODE_DEFAULT:
+    {
+      if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
+      {
+        /* High Speed DDR mode activated */
+        errorstate = MMC_DDR_Mode(hmmc, DISABLE);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+        }
+      }
+      if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
+      {
+        /* High Speed mode activated */
+        errorstate = MMC_HighSpeed(hmmc, DISABLE);
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          hmmc->ErrorCode |= errorstate;
+        }
+      }
+      break;
+    }
+    default:
+      hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+      status = HAL_ERROR;
+      break;
+  }
+
+  /* Verify that MMC card is ready to use after Speed mode switch*/
+  tickstart = HAL_GetTick();
+  while ((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER))
+  {
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Change State */
+  hmmc->State = HAL_MMC_STATE_READY;
+  return status;
+}
+
+/**
+  * @brief  Gets the current mmc card data state.
+  * @param  hmmc: pointer to MMC handle
+  * @retval Card state
+  */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t cardstate;
+  uint32_t errorstate;
+  uint32_t resp1 = 0U;
+
+  errorstate = MMC_SendStatus(hmmc, &resp1);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    hmmc->ErrorCode |= errorstate;
+  }
+
+  cardstate = ((resp1 >> 9U) & 0x0FU);
+
+  return (HAL_MMC_CardStateTypeDef)cardstate;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the MMC.
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
+  *                the configuration information for MMC module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t error_code;
+  uint32_t tickstart;
+
+  if (hmmc->State == HAL_MMC_STATE_BUSY)
+  {
+    /* DIsable All interrupts */
+    __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                         SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /*we will send the CMD12 in all cases in order to stop the data transfers*/
+    /*In case the data transfer just finished, the external memory will not respond
+      and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/
+    /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/
+    /*Other scenario will return HAL_ERROR*/
+
+    hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+    error_code = hmmc->ErrorCode;
+    if ((error_code != HAL_MMC_ERROR_NONE) && (error_code != HAL_MMC_ERROR_CMD_RSP_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+
+    tickstart = HAL_GetTick();
+    if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
+    {
+      if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE)
+      {
+        while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
+        {
+          if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+          {
+            hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+            hmmc->State = HAL_MMC_STATE_READY;
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+
+      if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT)
+      {
+        while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND))
+        {
+          if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+          {
+            hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+            hmmc->State = HAL_MMC_STATE_READY;
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
+    {
+      while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
+      {
+        if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+        {
+          hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+          hmmc->State = HAL_MMC_STATE_READY;
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do*/
+    }
+
+    /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear
+      the appropriate flags that will be set depending of the abort/non abort of the memory */
+    /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result
+      in next SDMMC read/write operation to fail */
+
+    /*SDMMC ready for clear data flags*/
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+    /* If IDMA Context, disable Internal DMA */
+    hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Initialize the MMC operation */
+    hmmc->Context = MMC_CONTEXT_NONE;
+  }
+  return HAL_OK;
+}
+/**
+  * @brief  Abort the current transfer and disable the MMC (IT mode).
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
+  *                the configuration information for MMC module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
+{
+  HAL_MMC_CardStateTypeDef CardState;
+
+  /* DIsable All interrupts */
+  __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                       SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+  /* If IDMA Context, disable Internal DMA */
+  hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+  /* Clear All flags */
+  __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+  CardState = HAL_MMC_GetCardState(hmmc);
+  hmmc->State = HAL_MMC_STATE_READY;
+
+  if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+  {
+    hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+  }
+  if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+    hmmc->AbortCpltCallback(hmmc);
+#else
+    HAL_MMC_AbortCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform specific commands sequence for the different type of erase.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @param  hmmc Pointer to MMC handle
+  * @param  EraseType Specifies the type of erase to be performed
+  *          This parameter can be one of the following values:
+  *             @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
+  *             @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
+  *             @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
+  *             @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified
+  *                  by CMD35 & 36
+  *             @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
+  *             @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks
+  *                  previously identified
+  * @param  BlockStartAdd Start Block address
+  * @param  BlockEndAdd End Block address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType,
+                                        uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+  uint32_t errorstate;
+  uint32_t start_add = BlockStartAdd;
+  uint32_t end_add = BlockEndAdd;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the erase type value is correct */
+  assert_param(IS_MMC_ERASE_TYPE(EraseType));
+
+  /* Check the coherence between start and end address */
+  if (end_add < start_add)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  /* Check that the end address is not out of range of device memory */
+  if (end_add > (hmmc->MmcCard.LogBlockNbr))
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+    return HAL_ERROR;
+  }
+
+  /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+  if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+  {
+    if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+    {
+      /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+      return HAL_ERROR;
+    }
+  }
+
+  /* Check if the card command class supports erase command */
+  if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+    return HAL_ERROR;
+  }
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Check that the card is not locked */
+    if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* In case of low capacity card, the address is not block number but bytes */
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      start_add *= MMC_BLOCKSIZE;
+      end_add   *= MMC_BLOCKSIZE;
+    }
+
+    /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */
+    errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* Send CMD36 MMC_ERASE_GRP_END with end address as argument */
+      errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* Send CMD38 ERASE with erase type as argument */
+        errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType);
+        if (errorstate == HAL_MMC_ERROR_NONE)
+        {
+          if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2))
+          {
+            /* Wait that the device is ready by checking the D0 line */
+            while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+            {
+              if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
+              {
+                errorstate = HAL_MMC_ERROR_TIMEOUT;
+              }
+            }
+
+            /* Clear the flag corresponding to end D0 bus line */
+            __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+          }
+        }
+      }
+    }
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+
+      if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Perform sanitize operation on the device.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @param  hmmc Pointer to MMC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t errorstate;
+  uint32_t response = 0U;
+  uint32_t count;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Index : 165 - Value : 0x01 */
+    errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U);
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* Wait that the device is ready by checking the D0 line */
+      while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+      {
+        if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
+        {
+          errorstate = HAL_MMC_ERROR_TIMEOUT;
+        }
+      }
+
+      /* Clear the flag corresponding to end D0 bus line */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+        count = SDMMC_MAX_TRIAL;
+        do
+        {
+          errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+          if (errorstate != HAL_MMC_ERROR_NONE)
+          {
+            break;
+          }
+
+          /* Get command response */
+          response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+          count--;
+        } while (((response & 0x100U) == 0U) && (count != 0U));
+
+        /* Check the status after the switch command execution */
+        if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+        {
+          /* Check the bit SWITCH_ERROR of the device status */
+          if ((response & 0x80U) != 0U)
+          {
+            errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+          }
+        }
+        else if (count == 0U)
+        {
+          errorstate = SDMMC_ERROR_TIMEOUT;
+        }
+        else
+        {
+          /* Nothing to do */
+        }
+      }
+    }
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+
+      if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure the Secure Removal Type (SRT) in the Extended CSD register.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_MMC_GetCardState().
+  * @param  hmmc Pointer to MMC handle
+  * @param  SRTMode Specifies the type of erase to be performed
+  *          This parameter can be one of the following values:
+  *            @arg HAL_MMC_SRT_ERASE Information removed by an erase
+  *            @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character
+  *                 followed by an erase
+  *            @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+  *                 its complement then a random character
+  *            @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode)
+{
+  uint32_t srt;
+  uint32_t errorstate;
+  uint32_t response = 0U;
+  uint32_t count;
+
+  /* Check the erase type value is correct */
+  assert_param(IS_MMC_SRT_TYPE(SRTMode));
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Get the supported values by the device */
+    if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
+    {
+      /* Change State */
+      hmmc->State = HAL_MMC_STATE_BUSY;
+
+      /* Check the value passed as parameter is supported by the device */
+      if ((SRTMode & srt) != 0U)
+      {
+        /* Index : 16 - Value : SRTMode */
+        srt |= ((POSITION_VAL(SRTMode)) << 4U);
+        errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U)));
+        if (errorstate == HAL_MMC_ERROR_NONE)
+        {
+          /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+          count = SDMMC_MAX_TRIAL;
+          do
+          {
+            errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+            if (errorstate != HAL_MMC_ERROR_NONE)
+            {
+              break;
+            }
+
+            /* Get command response */
+            response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+            count--;
+          } while (((response & 0x100U) == 0U) && (count != 0U));
+
+          /* Check the status after the switch command execution */
+          if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+          {
+            /* Check the bit SWITCH_ERROR of the device status */
+            if ((response & 0x80U) != 0U)
+            {
+              errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+            }
+          }
+          else if (count == 0U)
+          {
+            errorstate = SDMMC_ERROR_TIMEOUT;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+      }
+      else
+      {
+        errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+      }
+
+      /* Change State */
+      hmmc->State = HAL_MMC_STATE_READY;
+    }
+    else
+    {
+      errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+    }
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      return HAL_ERROR;
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Gets the supported values of the the Secure Removal Type (SRT).
+  * @param  hmmc pointer to MMC handle
+  * @param  SupportedSRT pointer for supported SRT value
+  *          This parameter is a bit field of the following values:
+  *            @arg HAL_MMC_SRT_ERASE Information removed by an erase
+  *            @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed
+  *                  by an erase
+  *            @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+  *                 its complement then a random character
+  *            @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT)
+{
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Read field SECURE_REMOVAL_TYPE [16 = 4*4] of the Extended CSD register */
+    *SupportedSRT = (hmmc->Ext_CSD[4] & 0x0000000FU); /* Bits [3:0] of field 16 */
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Switch the device from Standby State to Sleep State.
+  * @param  hmmc pointer to MMC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t errorstate,
+           sleep_timeout,
+           timeout,
+           count,
+           response = 0U  ;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+    errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+      count = SDMMC_MAX_TRIAL;
+      do
+      {
+        errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          break;
+        }
+
+        /* Get command response */
+        response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+        count--;
+      } while (((response & 0x100U) == 0U) && (count != 0U));
+
+      /* Check the status after the switch command execution */
+      if (count == 0U)
+      {
+        errorstate = SDMMC_ERROR_TIMEOUT;
+      }
+      else if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* Check the bit SWITCH_ERROR of the device status */
+        if ((response & 0x80U) != 0U)
+        {
+          errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+        }
+        else
+        {
+          /* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */
+          errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U));
+          if (errorstate == HAL_MMC_ERROR_NONE)
+          {
+            /* Field SLEEP_NOTIFICATION_TIME [216] */
+            sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >>
+                              MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU);
+
+            /* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */
+            /* In HAL, the tick interrupt occurs each ms */
+            if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+            {
+              sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+            }
+            timeout = (((1UL << sleep_timeout) / 100U) + 1U);
+
+            /* Wait that the device is ready by checking the D0 line */
+            while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+            {
+              if ((HAL_GetTick() - tickstart) >= timeout)
+              {
+                errorstate = SDMMC_ERROR_TIMEOUT;
+              }
+            }
+
+            /* Clear the flag corresponding to end D0 bus line */
+            __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+            if (errorstate == HAL_MMC_ERROR_NONE)
+            {
+              /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+              count = SDMMC_MAX_TRIAL;
+              do
+              {
+                errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
+                                                 (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+                if (errorstate != HAL_MMC_ERROR_NONE)
+                {
+                  break;
+                }
+
+                /* Get command response */
+                response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+                count--;
+              } while (((response & 0x100U) == 0U) && (count != 0U));
+
+              /* Check the status after the switch command execution */
+              if (count == 0U)
+              {
+                errorstate = SDMMC_ERROR_TIMEOUT;
+              }
+              else if (errorstate == HAL_MMC_ERROR_NONE)
+              {
+                /* Check the bit SWITCH_ERROR of the device status */
+                if ((response & 0x80U) != 0U)
+                {
+                  errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+                }
+                else
+                {
+                  /* Switch the device in stand-by mode */
+                  (void)SDMMC_CmdSelDesel(hmmc->Instance, 0U);
+
+                  /* Field S_A_TIEMOUT [217] */
+                  sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >>
+                                    MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU);
+
+                  /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
+                  /* In HAL, the tick interrupt occurs each ms */
+                  if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+                  {
+                    sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+                  }
+                  timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
+
+                  if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+                  {
+                    /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */
+                    errorstate = SDMMC_CmdSleepMmc(hmmc->Instance,
+                                                   ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U)));
+                    if (errorstate == HAL_MMC_ERROR_NONE)
+                    {
+                      /* Wait that the device is ready by checking the D0 line */
+                      while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+                      {
+                        if ((HAL_GetTick() - tickstart) >= timeout)
+                        {
+                          errorstate = SDMMC_ERROR_TIMEOUT;
+                        }
+                      }
+
+                      /* Clear the flag corresponding to end D0 bus line */
+                      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+                    }
+                  }
+                  else
+                  {
+                    errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+                  }
+                }
+              }
+              else
+              {
+                /* Nothing to do */
+              }
+            }
+          }
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+
+      if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Switch the device from Sleep State to Standby State.
+  * @param  hmmc pointer to MMC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t errorstate;
+  uint32_t sleep_timeout;
+  uint32_t timeout;
+  uint32_t count;
+  uint32_t response = 0U;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Field S_A_TIEMOUT [217] */
+    sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) &
+                     0x000000FFU);
+
+    /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
+    /* In HAL, the tick interrupt occurs each ms */
+    if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+    {
+      sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+    }
+    timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
+
+    /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */
+    errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* Wait that the device is ready by checking the D0 line */
+      while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+      {
+        if ((HAL_GetTick() - tickstart) >= timeout)
+        {
+          errorstate = SDMMC_ERROR_TIMEOUT;
+        }
+      }
+
+      /* Clear the flag corresponding to end D0 bus line */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+        {
+          /* Switch the device in transfer mode */
+          errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
+          if (errorstate == HAL_MMC_ERROR_NONE)
+          {
+            if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER)
+            {
+              /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+              errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+              if (errorstate == HAL_MMC_ERROR_NONE)
+              {
+                /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+                count = SDMMC_MAX_TRIAL;
+                do
+                {
+                  errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
+                                                   (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+                  if (errorstate != HAL_MMC_ERROR_NONE)
+                  {
+                    break;
+                  }
+
+                  /* Get command response */
+                  response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+                  count--;
+                } while (((response & 0x100U) == 0U) && (count != 0U));
+
+                /* Check the status after the switch command execution */
+                if (count == 0U)
+                {
+                  errorstate = SDMMC_ERROR_TIMEOUT;
+                }
+                else if (errorstate == HAL_MMC_ERROR_NONE)
+                {
+                  /* Check the bit SWITCH_ERROR of the device status */
+                  if ((response & 0x80U) != 0U)
+                  {
+                    errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+                  }
+                }
+                else
+                {
+                  /* NOthing to do */
+                }
+              }
+            }
+            else
+            {
+              errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+            }
+          }
+        }
+        else
+        {
+          errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+        }
+      }
+    }
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+
+      if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup MMC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the mmc card.
+  * @param  hmmc: Pointer to MMC handle
+  * @retval MMC Card error state
+  */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+  HAL_MMC_CardCSDTypeDef CSD;
+  uint32_t errorstate;
+  uint16_t mmc_rca = 2U;
+  MMC_InitTypeDef Init;
+
+  /* Check the power State */
+  if (SDMMC_GetPowerState(hmmc->Instance) == 0U)
+  {
+    /* Power off */
+    return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  /* Send CMD2 ALL_SEND_CID */
+  errorstate = SDMMC_CmdSendCID(hmmc->Instance);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    return errorstate;
+  }
+  else
+  {
+    /* Get Card identification number data */
+    hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+    hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
+    hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
+    hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
+  }
+
+  /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */
+  /* MMC Card publishes its RCA. */
+  errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Get the MMC card RCA */
+  hmmc->MmcCard.RelCardAdd = mmc_rca;
+
+  /* Send CMD9 SEND_CSD with argument as card's RCA */
+  errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    return errorstate;
+  }
+  else
+  {
+    /* Get Card Specific Data */
+    hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+    hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
+    hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
+    hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
+  }
+
+  /* Get the Card Class */
+  hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Get CSD parameters */
+  if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
+  {
+    return hmmc->ErrorCode;
+  }
+
+  /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+  errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    hmmc->ErrorCode |= errorstate;
+  }
+
+  /* Get Extended CSD parameters */
+  if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
+  {
+    return hmmc->ErrorCode;
+  }
+
+  /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+  errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    hmmc->ErrorCode |= errorstate;
+  }
+
+  /* Configure the SDMMC peripheral */
+  Init = hmmc->Init;
+  Init.BusWide = SDMMC_BUS_WIDE_1B;
+  (void)SDMMC_Init(hmmc->Instance, Init);
+
+  /* All cards are initialized */
+  return HAL_MMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores MMC information that will be needed in future
+  *         in the MMC handle.
+  * @param  hmmc: Pointer to MMC handle
+  * @retval error state
+  */
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
+{
+  __IO uint32_t count = 0U;
+  uint32_t response = 0U;
+  uint32_t validvoltage = 0U;
+  uint32_t errorstate;
+
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  while (validvoltage == 0U)
+  {
+    if (count++ == SDMMC_MAX_VOLT_TRIAL)
+    {
+      return HAL_MMC_ERROR_INVALID_VOLTRANGE;
+    }
+
+    /* SEND CMD1 APP_CMD with voltage range as argument */
+    errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+    /* Get command response */
+    response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+
+    /* Get operating voltage*/
+    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+  }
+
+  /* When power routine is finished and command returns valid voltage */
+  if (((response & (0xFF000000U)) >> 24) == 0xC0U)
+  {
+    hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
+  }
+  else
+  {
+    hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
+  }
+
+  return HAL_MMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Turns the SDMMC output signals off.
+  * @param  hmmc: Pointer to MMC handle
+  * @retval None
+  */
+static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
+{
+  /* Set Power State to OFF */
+  (void)SDMMC_PowerState_OFF(hmmc->Instance);
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pCardStatus: pointer to the buffer that will contain the MMC card
+  *         status (Card Status register)
+  * @retval error state
+  */
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
+{
+  uint32_t errorstate;
+
+  if (pCardStatus == NULL)
+  {
+    return HAL_MMC_ERROR_PARAM;
+  }
+
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Get MMC card status */
+  *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+
+  return HAL_MMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Reads extended CSD register to get the sectors number of the device
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pFieldData: Pointer to the read buffer
+  * @param  FieldIndex: Index of the field to be read
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
+                                        uint16_t FieldIndex, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t i = 0;
+  uint32_t tmp_data;
+  uint32_t dataremaining;
+
+  hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+  /* Initialize data control register */
+  hmmc->Instance->DCTRL = 0;
+
+  /* Configure the MMC DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = MMC_BLOCKSIZE;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+    hmmc->ErrorCode |= errorstate;
+    hmmc->State = HAL_MMC_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  /* Poll on SDMMC flags */
+  dataremaining = config.DataLength;
+  while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                             SDMMC_FLAG_DATAEND))
+  {
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+    {
+      /* Read data from SDMMC Rx FIFO */
+      for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+      {
+        tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
+        /* eg : SEC_COUNT   : FieldIndex = 212 => i+count = 53 */
+        /*      DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
+        if ((i + count) == ((uint32_t)FieldIndex / 4U))
+        {
+          *pFieldData = tmp_data;
+        }
+      }
+      i += 8U;
+      dataremaining -= SDMMC_FIFO_SIZE;
+    }
+
+    if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get error state */
+  if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+  {
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+    hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+    hmmc->State = HAL_MMC_STATE_READY;
+    return HAL_ERROR;
+  }
+  else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+  {
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+    hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+    hmmc->State = HAL_MMC_STATE_READY;
+    return HAL_ERROR;
+  }
+  else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+  {
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+    hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+    hmmc->State = HAL_MMC_STATE_READY;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+  errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
+  if (errorstate != HAL_MMC_ERROR_NONE)
+  {
+    hmmc->ErrorCode |= errorstate;
+  }
+
+  /* Clear all the static flags */
+  __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+  hmmc->State = HAL_MMC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wrap up reading in non-blocking mode.
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t count;
+  uint32_t data;
+  uint8_t *tmp;
+
+  tmp = hmmc->pRxBuffPtr;
+
+  if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE)
+  {
+    /* Read data from SDMMC Rx FIFO */
+    for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+    {
+      data = SDMMC_ReadFIFO(hmmc->Instance);
+      *tmp = (uint8_t)(data & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+      tmp++;
+    }
+
+    hmmc->pRxBuffPtr = tmp;
+    hmmc->RxXferSize -= SDMMC_FIFO_SIZE;
+  }
+}
+
+/**
+  * @brief  Wrap up writing in non-blocking mode.
+  * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t count;
+  uint32_t data;
+  const uint8_t *tmp;
+
+  tmp = hmmc->pTxBuffPtr;
+
+  if (hmmc->TxXferSize >= SDMMC_FIFO_SIZE)
+  {
+    /* Write data to SDMMC Tx FIFO */
+    for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+    {
+      data = (uint32_t)(*tmp);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 8U);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 16U);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 24U);
+      tmp++;
+      (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+    }
+
+    hmmc->pTxBuffPtr = tmp;
+    hmmc->TxXferSize -= SDMMC_FIFO_SIZE;
+  }
+}
+
+/**
+  * @brief  Switches the MMC card to high speed mode.
+  * @param  hmmc: MMC handle
+  * @param  state: State of high speed mode
+  * @retval MMC Card error state
+  */
+static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
+{
+  uint32_t errorstate = HAL_MMC_ERROR_NONE;
+  uint32_t response = 0U;
+  uint32_t count;
+  uint32_t sdmmc_clk;
+  SDMMC_InitTypeDef Init;
+
+  if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
+  {
+    errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT);
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* Index : 185 - Value : 0 */
+      errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
+    }
+  }
+
+  if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
+  {
+    errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH);
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* Index : 185 - Value : 1 */
+      errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
+    }
+  }
+
+  if (errorstate == HAL_MMC_ERROR_NONE)
+  {
+    /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+    count = SDMMC_MAX_TRIAL;
+    do
+    {
+      errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+      if (errorstate != HAL_MMC_ERROR_NONE)
+      {
+        break;
+      }
+
+      /* Get command response */
+      response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+      count--;
+    } while (((response & 0x100U) == 0U) && (count != 0U));
+
+    /* Check the status after the switch command execution */
+    if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+    {
+      /* Check the bit SWITCH_ERROR of the device status */
+      if ((response & 0x80U) != 0U)
+      {
+        errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+      }
+      else
+      {
+        /* Configure high speed */
+        Init.ClockEdge           = hmmc->Init.ClockEdge;
+        Init.ClockPowerSave      = hmmc->Init.ClockPowerSave;
+        Init.BusWide             = (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS);
+        Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
+
+        if (state == DISABLE)
+        {
+          Init.ClockDiv = hmmc->Init.ClockDiv;
+          (void)SDMMC_Init(hmmc->Instance, Init);
+
+          CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+        }
+        else
+        {
+          /* High Speed Clock should be less or equal to 52MHz*/
+          if (hmmc->Instance == SDMMC1)
+          {
+            sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+          }
+          else if (hmmc->Instance == SDMMC2)
+          {
+            sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2);
+          }
+          else
+          {
+            sdmmc_clk = 0;
+          }
+
+          if (sdmmc_clk == 0U)
+          {
+            errorstate = SDMMC_ERROR_INVALID_PARAMETER;
+          }
+          else
+          {
+            if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ)
+            {
+              Init.ClockDiv = 0;
+            }
+            else
+            {
+              Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ);
+            }
+            (void)SDMMC_Init(hmmc->Instance, Init);
+
+            SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+          }
+        }
+      }
+    }
+    else if (count == 0U)
+    {
+      errorstate = SDMMC_ERROR_TIMEOUT;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  return errorstate;
+}
+
+/**
+  * @brief  Switches the MMC card to Double Data Rate (DDR) mode.
+  * @param  hmmc: MMC handle
+  * @param  state: State of DDR mode
+  * @retval MMC Card error state
+  */
+static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
+{
+  uint32_t errorstate = HAL_MMC_ERROR_NONE;
+  uint32_t response = 0U;
+  uint32_t count;
+
+  if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
+  {
+    if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
+    {
+      errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH);
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* Index : 183 - Value : 1 */
+        errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+      }
+    }
+    else
+    {
+      errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH);
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* Index : 183 - Value : 2 */
+        errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+      }
+    }
+  }
+
+  if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
+  {
+    if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
+    {
+      errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR);
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* Index : 183 - Value : 5 */
+        errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
+      }
+    }
+    else
+    {
+      errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR);
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* Index : 183 - Value : 6 */
+        errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
+      }
+    }
+  }
+
+  if (errorstate == HAL_MMC_ERROR_NONE)
+  {
+    /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+    count = SDMMC_MAX_TRIAL;
+    do
+    {
+      errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+      if (errorstate != HAL_MMC_ERROR_NONE)
+      {
+        break;
+      }
+
+      /* Get command response */
+      response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+      count--;
+    } while (((response & 0x100U) == 0U) && (count != 0U));
+
+    /* Check the status after the switch command execution */
+    if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+    {
+      /* Check the bit SWITCH_ERROR of the device status */
+      if ((response & 0x80U) != 0U)
+      {
+        errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+      }
+      else
+      {
+        /* Configure DDR mode */
+        if (state == DISABLE)
+        {
+          CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
+        }
+        else
+        {
+          SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
+        }
+      }
+    }
+    else if (count == 0U)
+    {
+      errorstate = SDMMC_ERROR_TIMEOUT;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  return errorstate;
+}
+
+/**
+  * @brief  Update the power class of the device.
+  * @param  hmmc MMC handle
+  * @param  Wide Wide of MMC bus
+  * @param  Speed Speed of the MMC bus
+  * @retval MMC Card error state
+  */
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed)
+{
+  uint32_t count;
+  uint32_t response = 0U;
+  uint32_t errorstate = HAL_MMC_ERROR_NONE;
+  uint32_t power_class;
+  uint32_t supported_pwr_class;
+
+  if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
+  {
+    power_class = 0U; /* Default value after power-on or software reset */
+
+    /* Read the PowerClass field of the Extended CSD register */
+    if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
+    {
+      errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+    }
+    else
+    {
+      power_class = ((power_class >> 24U) & 0x000000FFU);
+    }
+
+    /* Get the supported PowerClass field of the Extended CSD register */
+    if (Speed == SDMMC_SPEED_MODE_DDR)
+    {
+      /* Field PWR_CL_DDR_52_xxx [238 or 239] */
+      supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) &
+                             0x000000FFU);
+    }
+    else if (Speed == SDMMC_SPEED_MODE_HIGH)
+    {
+      /* Field PWR_CL_52_xxx [200 or 202] */
+      supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) &
+                             0x000000FFU);
+    }
+    else
+    {
+      /* Field PWR_CL_26_xxx [201 or 203] */
+      supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) &
+                             0x000000FFU);
+    }
+
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      if (Wide == SDMMC_BUS_WIDE_8B)
+      {
+        /* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */
+        supported_pwr_class = (supported_pwr_class >> 4U);
+      }
+
+      if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU))
+      {
+        /* Need to change current power class */
+        errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U)));
+
+        if (errorstate == HAL_MMC_ERROR_NONE)
+        {
+          /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+          count = SDMMC_MAX_TRIAL;
+          do
+          {
+            errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+            if (errorstate != HAL_MMC_ERROR_NONE)
+            {
+              break;
+            }
+
+            /* Get command response */
+            response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+            count--;
+          } while (((response & 0x100U) == 0U) && (count != 0U));
+
+          /* Check the status after the switch command execution */
+          if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+          {
+            /* Check the bit SWITCH_ERROR of the device status */
+            if ((response & 0x80U) != 0U)
+            {
+              errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+            }
+          }
+          else if (count == 0U)
+          {
+            errorstate = SDMMC_ERROR_TIMEOUT;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+      }
+    }
+  }
+
+  return errorstate;
+}
+
+/**
+  * @brief  Used to select the partition.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  Partition: Partition type
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition)
+{
+  uint32_t errorstate;
+  uint32_t response = 0U;
+  uint32_t count;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t arg = Partition | 0x03B30000U;
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Index : 179 - Value : partition */
+    errorstate = SDMMC_CmdSwitch(hmmc->Instance, arg);
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* Wait that the device is ready by checking the D0 line */
+      while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+      {
+        if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
+        {
+          errorstate = HAL_MMC_ERROR_TIMEOUT;
+        }
+      }
+
+      /* Clear the flag corresponding to end D0 bus line */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+        count = SDMMC_MAX_TRIAL;
+        do
+        {
+          errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+          if (errorstate != HAL_MMC_ERROR_NONE)
+          {
+            break;
+          }
+
+          /* Get command response */
+          response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+          count--;
+        } while (((response & 0x100U) == 0U) && (count != 0U));
+
+        /* Check the status after the switch command execution */
+        if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+        {
+          /* Check the bit SWITCH_ERROR of the device status */
+          if ((response & 0x80U) != 0U)
+          {
+            errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+          }
+        }
+        else if (count == 0U)
+        {
+          errorstate = SDMMC_ERROR_TIMEOUT;
+        }
+        else
+        {
+          /* Nothing to do */
+        }
+      }
+    }
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+
+      if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Allows to program the authentication key within the RPMB partition
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pKey: pointer to the authentication key (32 bytes)
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t byte_count = 0;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint8_t tail_pack[12] = {0};
+  uint8_t zero_pack[4] = {0};
+  const uint8_t *rtempbuff;
+  uint8_t  *tempbuff;
+
+  tail_pack[11] = 0x01;
+
+  if (NULL == pKey)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance,  0x80000001U);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    {
+      hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+    }
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    rtempbuff = zero_pack;
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = (uint32_t)(*rtempbuff);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 8U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 16U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 24U);
+          rtempbuff++;
+          byte_count++;
+          (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+          if (byte_count < MMC_RPMB_KEYMAC_POSITION)
+          {
+            rtempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_KEYMAC_POSITION)
+          {
+            rtempbuff = pKey;
+          }
+          else if ((byte_count < MMC_RPMB_WRITE_COUNTER_POSITION) && \
+                   (byte_count >= MMC_RPMB_DATA_POSITION))
+          {
+            rtempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            rtempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Read Response Packet */
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance,  0x00000001);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+    /* Poll on SDMMC flags */
+    tempbuff = zero_pack;
+    byte_count = 0;
+
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = SDMMC_ReadFIFO(hmmc->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Check result of operation */
+    if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x01U))
+    {
+      hmmc->RPMBErrorCode |= tail_pack[9];
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to get the value of write counter within the RPMB partition.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pNonce: pointer to the value of nonce (16 bytes)
+  * @param  Timeout: Specify timeout value
+  * @retval write counter value.
+  */
+uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t byte_count = 0;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint8_t tail_pack[12] = {0};
+  uint8_t zero_pack[4] = {0};
+  uint8_t echo_nonce[16] = {0};
+  uint8_t *tempbuff = zero_pack;
+
+  tail_pack[11] = 0x02;
+
+  if (NULL == pNonce)
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+    return 0;
+  }
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance,  0x00000001U);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+      return 0;
+    }
+
+    /* Send Request Packet */
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+      return 0;
+    }
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = (uint32_t)(*tempbuff);
+          tempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*tempbuff) << 8U);
+          tempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*tempbuff) << 16U);
+          tempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*tempbuff) << 24U);
+          tempbuff++;
+          byte_count++;
+          (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+          if (byte_count < MMC_RPMB_NONCE_POSITION)
+          {
+            tempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_NONCE_POSITION)
+          {
+            tempbuff = (uint8_t *)pNonce;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+        return 0;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Read Response Packt */
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance,  0x00000001U);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+      return 0;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+      return 0;
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+    /* Poll on SDMMC flags */
+    tempbuff = zero_pack;
+
+    byte_count = 0;
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = SDMMC_ReadFIFO(hmmc->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          if (byte_count < MMC_RPMB_NONCE_POSITION)
+          {
+            tempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_NONCE_POSITION)
+          {
+            tempbuff = echo_nonce;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+        hmmc->State = HAL_MMC_STATE_READY;
+        hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+        return 0;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+      return 0;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+      return 0;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+      return 0;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    for (uint8_t i = 0; i < 16U; i++)
+    {
+      if (pNonce[i] != echo_nonce[i])
+      {
+        hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+        return 0;
+      }
+    }
+
+    return ((uint32_t)tail_pack[3] | ((uint32_t)tail_pack[2] << 8) | ((uint32_t)tail_pack[1] << 16) | \
+            ((uint32_t)tail_pack[0] << 24));
+  }
+  else
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+    hmmc->RPMBErrorCode |= HAL_MMC_ERROR_RPMB_COUNTER_FAILURE;
+    return 0;
+  }
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in the RPMB partition. The Data
+  *         transfer is managed by polling mode.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @param  pMAC: Pointer to the authentication MAC buffer
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd,
+                                           uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout)
+{
+
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t byte_count = 0;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint8_t tail_pack[12] = {0};
+  uint8_t zero_pack[4] = {0};
+  uint8_t echo_nonce[16] = {0};
+  const uint8_t local_nonce[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x00, 0x01, 0x02,
+                                   0x03, 0x04, 0x00, 0x01, 0x02, 0x03, 0x04, 0x08
+                                  };
+  const uint8_t *rtempbuff;
+  uint8_t  *tempbuff;
+  uint32_t arg = 0x80000000U;
+  uint32_t offset = 0;
+
+  if ((NumberOfBlocks != 0x1U) && (NumberOfBlocks != 0x2U) && (NumberOfBlocks != 0x20U))
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if ((NULL == pData) || (NULL == pMAC))
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  tail_pack[11] = 0x02;
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance,  0x00000001U);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Send Request Packet */
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    rtempbuff = zero_pack;
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = (uint32_t)(*rtempbuff);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 8U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 16U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 24U);
+          rtempbuff++;
+          byte_count++;
+          (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+          if (byte_count < MMC_RPMB_NONCE_POSITION)
+          {
+            rtempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_NONCE_POSITION)
+          {
+            rtempbuff = local_nonce;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            rtempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Read Response Packt */
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance,  0x00000001);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+    /* Poll on SDMMC flags */
+    tempbuff = zero_pack;
+
+    byte_count = 0;
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = SDMMC_ReadFIFO(hmmc->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          if (byte_count < MMC_RPMB_NONCE_POSITION)
+          {
+            tempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_NONCE_POSITION)
+          {
+            tempbuff = echo_nonce;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    for (uint8_t i = 0; i < 16U; i++)
+    {
+      if (local_nonce[i] != echo_nonce[i])
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  else
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+  tail_pack[11]  = 0x03;
+  tail_pack[10]  = 0x00;
+  tail_pack[7]   = (uint8_t)(NumberOfBlocks) & 0xFFU;
+  tail_pack[6]   = (uint8_t)(NumberOfBlocks >> 8) & 0xFFU;
+  tail_pack[5]   = (uint8_t)(BlockAdd) & 0xFFU;
+  tail_pack[4]   = (uint8_t)(BlockAdd >> 8) & 0xFFU;
+
+  rtempbuff = zero_pack;
+  byte_count = 0;
+  arg |= NumberOfBlocks;
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Send Request Packet */
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+
+    {
+      hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+    }
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = (uint32_t)(*rtempbuff);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 8U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 16U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 24U);
+          rtempbuff++;
+          byte_count++;
+          (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+          if (byte_count == MMC_RPMB_KEYMAC_POSITION)
+          {
+            rtempbuff = pMAC;
+          }
+          if (byte_count == MMC_RPMB_DATA_POSITION)
+          {
+            rtempbuff = &pData[offset];
+          }
+          if ((byte_count >= MMC_RPMB_NONCE_POSITION) && \
+              (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION))
+          {
+            rtempbuff = zero_pack;
+          }
+          if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            rtempbuff = tail_pack;
+          }
+          else if (byte_count == MMC_BLOCKSIZE)
+          {
+            offset += (uint32_t)256U;
+            byte_count = 0;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Response Packet */
+
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+
+    {
+      hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+    }
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+    /* Poll on SDMMC flags */
+    tempbuff = zero_pack;
+    byte_count = 0;
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = SDMMC_ReadFIFO(hmmc->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          if (byte_count < MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Check result of operation */
+    if (((tail_pack[9] & (uint8_t)0xFEU) != 0x00U) || (tail_pack[10] != 0x03U))
+    {
+      hmmc->RPMBErrorCode |= tail_pack[9];
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to read block(s) to a specified address in the RPMB partition. The Data
+  *         transfer is managed by polling mode.
+  * @param  hmmc: Pointer to MMC handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @param  pNonce: Pointer to the buffer that will contain the nonce to transmit
+  * @param  pMAC: Pointer to the authentication MAC buffer
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd,
+                                          uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC,
+                                          uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t byte_count = 0;
+  uint32_t data;
+  uint8_t tail_pack[12] = {0};
+  uint8_t zero_pack[4] = {0};
+  uint8_t echo_nonce[16] = {0};
+  uint32_t dataremaining;
+  const uint8_t *rtempbuff;
+  uint8_t  *tempbuff;
+  uint32_t arg = 0;
+  uint32_t offset = 0;
+
+  arg |= NumberOfBlocks;
+
+  tail_pack[11] = 0x04;
+  tail_pack[10] = 0x00;
+  tail_pack[7]  = 0x00;
+  tail_pack[6]  = 0x00;
+  tail_pack[5]  = (uint8_t)(BlockAdd) & 0xFFU;
+  tail_pack[4]  = (uint8_t)(BlockAdd >> 8) & 0xFFU;
+  tail_pack[3]  = 0x00;
+  tail_pack[2]  = 0x00;
+  tail_pack[1]  = 0x00;
+  tail_pack[0]  = 0x00;
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0U;
+
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance, 1);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Send Request Packet */
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, 0);
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    rtempbuff = zero_pack;
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = (uint32_t)(*rtempbuff);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 8U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 16U);
+          rtempbuff++;
+          byte_count++;
+          data |= ((uint32_t)(*rtempbuff) << 24U);
+          rtempbuff++;
+          byte_count++;
+          (void)SDMMC_WriteFIFO(hmmc->Instance, &data);
+          if (byte_count < MMC_RPMB_NONCE_POSITION)
+          {
+            rtempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_NONCE_POSITION)
+          {
+            rtempbuff = pNonce;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            rtempbuff = tail_pack;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= errorstate;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Read Response Packet */
+    errorstate = SDMMC_CmdBlockCount(hmmc->Instance, arg);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * MMC_BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    /* Write Blocks in Polling mode */
+    hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, 0);
+
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+    /* Poll on SDMMC flags */
+    tempbuff = zero_pack;
+    byte_count = 0;
+
+    dataremaining = config.DataLength;
+    while (!__HAL_MMC_GET_FLAG(hmmc,
+                               SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = SDMMC_ReadFIFO(hmmc->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          byte_count++;
+          if (byte_count < MMC_RPMB_KEYMAC_POSITION)
+          {
+            tempbuff = zero_pack;
+          }
+          else if (byte_count == MMC_RPMB_KEYMAC_POSITION)
+          {
+            tempbuff = (uint8_t *)pMAC;
+          }
+          else if (byte_count == MMC_RPMB_DATA_POSITION)
+          {
+            tempbuff = &pData[offset];
+          }
+          else if (byte_count == MMC_RPMB_NONCE_POSITION)
+          {
+            tempbuff = echo_nonce;
+          }
+          else if (byte_count == MMC_RPMB_WRITE_COUNTER_POSITION)
+          {
+            tempbuff = tail_pack;
+          }
+          else if (byte_count == MMC_BLOCKSIZE)
+          {
+            byte_count = 0;
+            offset += (uint32_t)256U;
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+        hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+        hmmc->State = HAL_MMC_STATE_READY;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /* Get error state */
+    if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+      hmmc->State = HAL_MMC_STATE_READY;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    for (uint8_t i = 0; i < 16U; i++)
+    {
+      if (pNonce[i] != echo_nonce[i])
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check result of operation */
+    if ((tail_pack[9] != 0x00U) || (tail_pack[10] != 0x04U))
+    {
+      hmmc->RPMBErrorCode |= tail_pack[9];
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+
+/**
+  * @brief Read DMA Linked list node Transfer completed callbacks
+  * @param hmmc: MMC handle
+  * @retval None
+  */
+__weak void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MMCEx_Read_DMALnkLstBufCpltCallback can be implemented in the user file
+   */
+}
+/**
+  * @brief Read DMA Linked list node Transfer completed callbacks
+  * @param hmmc: MMC handle
+  * @retval None
+  */
+__weak void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hmmc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MMCEx_Write_DMALnkLstBufCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MMC_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mmc_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mmc_ex.c
new file mode 100644
index 000000000..dcadf21b9
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_mmc_ex.c
@@ -0,0 +1,448 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_mmc_ex.c
+  * @author  MCD Application Team
+  * @brief   MMC card Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (MMC) peripheral:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   The MMC Extension HAL driver can be used as follows:
+   (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
+
+   (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and
+       HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MMCEx MMCEx
+  * @brief MMC Extended HAL module driver
+  * @{
+  */
+
+#if defined (SDMMC1) || defined (SDMMC2)
+#ifdef HAL_MMC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MMCEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup MMCEx_Exported_Functions_Group1
+  *  @brief   Linked List management functions
+  *
+@verbatim
+ ===============================================================================
+                   ##### Linked List management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Build Linked List node.
+  * @param  pNode: Pointer to new node to add.
+  * @param  pNodeConf: Pointer to configuration parameters for new node to add.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode,
+                                                    MMC_DMALinkNodeConfTypeDef *pNodeConf)
+{
+
+  if (SDMMC_DMALinkedList_BuildNode(pNode, pNodeConf) != SDMMC_ERROR_NONE)
+  {
+    return (HAL_ERROR);
+  }
+  else
+  {
+    return (HAL_OK);
+  }
+
+}
+/**
+  * @brief  Insert Linked List node.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @param  pPrevNode: Pointer to previous node.
+  * @param  pNewNode: Pointer to new node to insert.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_InsertNode(MMC_DMALinkedListTypeDef *pLinkedList,
+                                                     MMC_DMALinkNodeTypeDef *pPrevNode,
+                                                     MMC_DMALinkNodeTypeDef *pNewNode)
+{
+
+  if (SDMMC_DMALinkedList_InsertNode(pLinkedList, pPrevNode, pNewNode) != SDMMC_ERROR_NONE)
+  {
+    return (HAL_ERROR);
+  }
+  else
+  {
+    return (HAL_OK);
+  }
+
+}
+/**
+  * @brief  Remove Linked List node.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @param  pNode: Pointer to node to remove.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_RemoveNode(MMC_DMALinkedListTypeDef *pLinkedList,
+                                                     MMC_DMALinkNodeTypeDef *pNode)
+{
+
+  if (SDMMC_DMALinkedList_RemoveNode(pLinkedList, pNode) != SDMMC_ERROR_NONE)
+  {
+    return (HAL_ERROR);
+  }
+  else
+  {
+    return (HAL_OK);
+  }
+}
+
+/**
+  * @brief  Lock Linked List node.
+  * @param  pNode: Pointer to node to remove.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_LockNode(MMC_DMALinkNodeTypeDef *pNode)
+{
+
+  if (SDMMC_DMALinkedList_LockNode(pNode) != SDMMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Unlock Linked List node.
+  * @param  pNode: Pointer to node to remove.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_UnlockNode(MMC_DMALinkNodeTypeDef *pNode)
+{
+
+  if (SDMMC_DMALinkedList_UnlockNode(pNode) != SDMMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Enable Circular mode for DMA Linked List mode.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_EnableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+  if (SDMMC_DMALinkedList_EnableCircularMode(pLinkedList) != SDMMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+/**
+  * @brief  Disable Circular mode for DMA Linked List mode.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+  if (SDMMC_DMALinkedList_DisableCircularMode(pLinkedList) != SDMMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The received Data will be stored in linked list buffers.
+  *         linked list should be prepared before call this function .
+  * @param  hmmc: MMC handle
+  * @param  pLinkedList: pointer to first linked list node
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Total number of blocks to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc,
+                                                     const MMC_DMALinkedListTypeDef *pLinkedList,
+                                                     uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t DmaBase0_reg;
+  uint32_t DmaBase1_reg;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+    hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+    hmmc->Instance->IDMABAR   = (uint32_t) pLinkedList->pHeadNode;
+    hmmc->Instance->IDMALAR   = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+                                sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+    DmaBase0_reg = hmmc->Instance->IDMABASER;
+    DmaBase1_reg = hmmc->Instance->IDMABAR;
+
+    if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+    {
+      hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0;
+
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+    hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+    /* Read Blocks in DMA mode */
+    hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+    /* Read Multi Block command */
+    errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->ErrorCode |= errorstate;
+      return HAL_ERROR;
+    }
+
+    __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+                               SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}
+
+/**
+  * @brief  Write block(s) to a specified address in a card. The transferred Data are stored linked list nodes buffers .
+  *         linked list should be prepared before call this function .
+  * @param  hmmc: MMC handle
+  * @param  pLinkedList: pointer to first linked list node
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Total number of blocks to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc,
+                                                      const MMC_DMALinkedListTypeDef *pLinkedList,
+                                                      uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t DmaBase0_reg;
+  uint32_t DmaBase1_reg;
+  uint32_t add = BlockAdd;
+
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+    {
+      hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    {
+      if ((NumberOfBlocks % 8U) != 0U)
+      {
+        /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+        return HAL_ERROR;
+      }
+
+      if ((BlockAdd % 8U) != 0U)
+      {
+        /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+        hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+        return HAL_ERROR;
+      }
+    }
+
+    hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+    hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+
+    hmmc->Instance->IDMABAR = (uint32_t)  pLinkedList->pHeadNode;
+    hmmc->Instance->IDMALAR = (uint32_t)  SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+                              sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+    DmaBase0_reg = hmmc->Instance->IDMABASER;
+    DmaBase1_reg = hmmc->Instance->IDMABAR;
+
+    if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+    {
+      hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Initialize data control register */
+    hmmc->Instance->DCTRL = 0;
+
+    hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the MMC DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = MMC_BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hmmc->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+    hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+    /* Write Blocks in DMA mode */
+    hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      hmmc->State = HAL_MMC_STATE_READY;
+      hmmc->ErrorCode |= errorstate;
+      return HAL_ERROR;
+    }
+
+    __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+                               SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MMC_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_msp_template.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_msp_template.c
new file mode 100644
index 000000000..87b8ea5ab
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_msp_template.c
@@ -0,0 +1,99 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_msp_template.c
+  * @author  MCD Application Team
+  * @brief   HAL MSP module.
+  *          This file template is located in the HAL folder and should be copied
+  *          to the user folder.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL_MSP HAL MSP module driver
+  * @brief HAL MSP module.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the Global MSP.
+  * @retval None
+  */
+void HAL_MspInit(void)
+{
+
+}
+
+/**
+  * @brief  DeInitializes the Global MSP.
+  * @retval None
+  */
+void HAL_MspDeInit(void)
+{
+
+}
+
+/**
+  * @brief  Initialize the PPP MSP.
+  * @retval None
+  */
+/*
+void HAL_PPP_MspInit(void)
+{
+}
+*/
+
+/**
+  * @brief  DeInitialize the PPP MSP.
+  * @retval None
+  */
+/*
+void HAL_PPP_MspDeInit(void)
+{
+}
+*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_nand.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_nand.c
new file mode 100644
index 000000000..3d65af5e0
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_nand.c
@@ -0,0 +1,2199 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_nand.c
+  * @author  MCD Application Team
+  * @brief   NAND HAL module driver.
+  *          This file provides a generic firmware to drive NAND memories mounted
+  *          as external device.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                         ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a generic layered driver which contains a set of APIs used to
+      control NAND flash memories. It uses the FMC layer functions to interface
+      with NAND devices. This driver is used as follows:
+
+      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
+          with control and timing parameters for both common and attribute spaces.
+
+      (+) Read NAND flash memory maker and device IDs using the function
+          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
+          structure declared by the function caller.
+
+      (+) Access NAND flash memory by read/write operations using the functions
+          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
+          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
+          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
+          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
+          to read/write page(s)/spare area(s). These functions use specific device
+          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
+          structure. The read/write address information is contained by the Nand_Address_Typedef
+          structure passed as parameter.
+
+      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+
+      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+          The erase block address information is contained in the Nand_Address_Typedef
+          structure passed as parameter.
+
+      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+
+      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+          feature or the function HAL_NAND_GetECC() to get the ECC correction code.
+
+      (+) You can monitor the NAND device HAL state by calling the function
+          HAL_NAND_GetState()
+
+    [..]
+      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+          If a NAND flash device contains different operations and/or implementations,
+          it should be implemented separately.
+
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_NAND_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : NAND MspInit.
+        (+) MspDeInitCallback  : NAND MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : NAND MspInit.
+        (+) MspDeInitCallback  : NAND MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (overridden) functions in the HAL_NAND_Init
+      and  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
+      or HAL_NAND_Init function.
+
+      When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+/** @defgroup NAND NAND
+  * @brief NAND HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private Constants ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
+  * @{
+  */
+
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+            ##### NAND Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize
+    the NAND memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform NAND memory Initialization sequence
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  ComSpace_Timing pointer to Common space timing structure
+  * @param  AttSpace_Timing pointer to Attribute space timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+                                 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+  /* Check the NAND handle state */
+  if (hnand == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hnand->State == HAL_NAND_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hnand->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    if (hnand->MspInitCallback == NULL)
+    {
+      hnand->MspInitCallback = HAL_NAND_MspInit;
+    }
+    hnand->ItCallback = HAL_NAND_ITCallback;
+
+    /* Init the low level hardware */
+    hnand->MspInitCallback(hnand);
+#else
+    /* Initialize the low level hardware (MSP) */
+    HAL_NAND_MspInit(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+  }
+
+  /* Initialize NAND control Interface */
+  (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+
+  /* Initialize NAND common space timing Interface */
+  (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+
+  /* Initialize NAND attribute space timing Interface */
+  (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+
+  /* Enable the NAND device */
+  __FMC_NAND_ENABLE(hnand->Instance);
+
+  /* Enable FMC Peripheral */
+  __FMC_ENABLE();
+  /* Update the NAND controller state */
+  hnand->State = HAL_NAND_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform NAND memory De-Initialization sequence
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
+{
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+  if (hnand->MspDeInitCallback == NULL)
+  {
+    hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hnand->MspDeInitCallback(hnand);
+#else
+  /* Initialize the low level hardware (MSP) */
+  HAL_NAND_MspDeInit(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+  /* Configure the NAND registers with their reset values */
+  (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+  /* Reset the NAND controller state */
+  hnand->State = HAL_NAND_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnand);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  NAND MSP Init
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NAND_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  NAND MSP DeInit
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NAND_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  This function handles NAND device interrupt request.
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+  /* Check NAND interrupt Rising edge flag */
+  if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+  {
+    /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
+    HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+    /* Clear NAND interrupt Rising edge pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
+  }
+
+  /* Check NAND interrupt Level flag */
+  if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+  {
+    /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
+    HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+    /* Clear NAND interrupt Level pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
+  }
+
+  /* Check NAND interrupt Falling edge flag */
+  if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+  {
+    /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
+    HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+    /* Clear NAND interrupt Falling edge pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
+  }
+
+  /* Check NAND interrupt FIFO empty flag */
+  if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+  {
+    /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
+    HAL_NAND_ITCallback(hnand);
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
+
+    /* Clear NAND interrupt FIFO empty pending bit */
+    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
+  }
+
+}
+
+/**
+  * @brief  NAND interrupt feature callback
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval None
+  */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NAND_ITCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
+  * @brief    Input Output and memory control functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### NAND Input and Output functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to use and control the NAND
+    memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the NAND memory electronic signature
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pNAND_ID NAND ID structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+  __IO uint32_t data = 0;
+  __IO uint32_t data1 = 0;
+  uint32_t deviceaddress;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* Send Read ID command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+    __DSB();
+
+    /* Read the electronic signature from NAND flash */
+    if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+    {
+      data = *(__IO uint32_t *)deviceaddress;
+
+      /* Return the data read */
+      pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
+      pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
+      pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
+      pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
+    }
+    else
+    {
+      data = *(__IO uint32_t *)deviceaddress;
+      data1 = *((__IO uint32_t *)deviceaddress + 4);
+
+      /* Return the data read */
+      pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
+      pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
+      pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
+      pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  NAND memory reset
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+  uint32_t deviceaddress;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* Send NAND reset command */
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Configure the device: Enter the physical parameters of the device
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pDeviceConfig  pointer to NAND_DeviceConfigTypeDef structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig)
+{
+  hnand->Config.PageSize           = pDeviceConfig->PageSize;
+  hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
+  hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
+  hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
+  hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
+  hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
+  hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read Page(s) from NAND memory block (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to destination read buffer
+  * @param  NumPageToRead  number of pages to read from block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                        uint8_t *pBuffer, uint32_t NumPageToRead)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t nbpages = NumPageToRead;
+  uint8_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* NAND raw address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Page(s) read loop */
+    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Send read page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+        __DSB();
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
+      {
+        *buff = *(uint8_t *)deviceaddress;
+        buff++;
+      }
+
+      /* Decrement pages to read */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read Page(s) from NAND memory block (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to destination read buffer. pBuffer should be 16bits aligned
+  * @param  NumPageToRead  number of pages to read from block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                         uint16_t *pBuffer, uint32_t NumPageToRead)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t nbpages = NumPageToRead;
+  uint16_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* NAND raw address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Page(s) read loop */
+    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Send read page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+        __DSB();
+      }
+
+      /* Calculate PageSize */
+      if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+      {
+        hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+      }
+      else
+      {
+        /* Do nothing */
+        /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
+      {
+        *buff = *(uint16_t *)deviceaddress;
+        buff++;
+      }
+
+      /* Decrement pages to read */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write Page(s) to NAND memory block (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write
+  * @param  NumPageToWrite   number of pages to write to block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                         const uint8_t *pBuffer, uint32_t NumPageToWrite)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t nbpages = NumPageToWrite;
+  const uint8_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* NAND raw address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Page(s) write loop */
+    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Send write page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
+      {
+        *(__IO uint8_t *)deviceaddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+      {
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Decrement pages to write */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write Page(s) to NAND memory block (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned
+  * @param  NumPageToWrite   number of pages to write to block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                          const uint16_t *pBuffer, uint32_t NumPageToWrite)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t nbpages = NumPageToWrite;
+  const uint16_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* NAND raw address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Page(s) write loop */
+    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Send write page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      /* Calculate PageSize */
+      if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+      {
+        hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+      }
+      else
+      {
+        /* Do nothing */
+        /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
+      {
+        *(__IO uint16_t *)deviceaddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+      {
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Decrement pages to write */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer pointer to source buffer to write
+  * @param  NumSpareAreaToRead Number of spare area to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                             uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t columnaddress;
+  uint32_t nbspare = NumSpareAreaToRead;
+  uint8_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* NAND raw address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnaddress = COLUMN_ADDRESS(hnand);
+
+    /* Spare area(s) read loop */
+    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+        __DSB();
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *buff = *(uint8_t *)deviceaddress;
+        buff++;
+      }
+
+      /* Decrement spare areas to read */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+  * @param  NumSpareAreaToRead Number of spare area to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                              uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t columnaddress;
+  uint32_t nbspare = NumSpareAreaToRead;
+  uint16_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* NAND raw address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
+
+    /* Spare area(s) read loop */
+    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+        __DSB();
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *buff = *(uint16_t *)deviceaddress;
+        buff++;
+      }
+
+      /* Decrement spare areas to read */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write
+  * @param  NumSpareAreaTowrite   number of spare areas to write to block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                              const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t columnaddress;
+  uint32_t nbspare = NumSpareAreaTowrite;
+  const uint8_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* Page address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnaddress = COLUMN_ADDRESS(hnand);
+
+    /* Spare area(s) write loop */
+    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *(__IO uint8_t *)deviceaddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+      {
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Decrement spare areas to write */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned.
+  * @param  NumSpareAreaTowrite   number of spare areas to write to block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                               const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceaddress;
+  uint32_t nandaddress;
+  uint32_t columnaddress;
+  uint32_t nbspare = NumSpareAreaTowrite;
+  const uint16_t *buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* NAND raw address calculation */
+    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
+
+    /* Spare area(s) write loop */
+    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+          __DSB();
+        }
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *(__IO uint16_t *)deviceaddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+      {
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Decrement spare areas to write */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandaddress = (uint32_t)(nandaddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  NAND memory Block erase
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
+{
+  uint32_t deviceaddress;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    deviceaddress = NAND_DEVICE;
+
+    /* Send Erase block command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+    __DSB();
+
+    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
+    __DSB();
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Increment the NAND memory address
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param pAddress pointer to NAND address structure
+  * @retval The new status of the increment address operation. It can be:
+  *           - NAND_VALID_ADDRESS: When the new address is valid address
+  *           - NAND_INVALID_ADDRESS: When the new address is invalid address
+  */
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+  uint32_t status = NAND_VALID_ADDRESS;
+
+  /* Increment page address */
+  pAddress->Page++;
+
+  /* Check NAND address is valid */
+  if (pAddress->Page == hnand->Config.BlockSize)
+  {
+    pAddress->Page = 0;
+    pAddress->Block++;
+
+    if (pAddress->Block == hnand->Config.PlaneSize)
+    {
+      pAddress->Block = 0;
+      pAddress->Plane++;
+
+      if (pAddress->Plane == (hnand->Config.PlaneNbr))
+      {
+        status = NAND_INVALID_ADDRESS;
+      }
+    }
+  }
+
+  return (status);
+}
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User NAND Callback
+  *         To be used to override the weak predefined callback
+  * @param hnand : NAND handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
+  *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
+  *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+                                            pNAND_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+      case HAL_NAND_MSP_INIT_CB_ID :
+        hnand->MspInitCallback = pCallback;
+        break;
+      case HAL_NAND_MSP_DEINIT_CB_ID :
+        hnand->MspDeInitCallback = pCallback;
+        break;
+      case HAL_NAND_IT_CB_ID :
+        hnand->ItCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hnand->State == HAL_NAND_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_NAND_MSP_INIT_CB_ID :
+        hnand->MspInitCallback = pCallback;
+        break;
+      case HAL_NAND_MSP_DEINIT_CB_ID :
+        hnand->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User NAND Callback
+  *         NAND Callback is redirected to the weak predefined callback
+  * @param hnand : NAND handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
+  *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
+  *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+      case HAL_NAND_MSP_INIT_CB_ID :
+        hnand->MspInitCallback = HAL_NAND_MspInit;
+        break;
+      case HAL_NAND_MSP_DEINIT_CB_ID :
+        hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+        break;
+      case HAL_NAND_IT_CB_ID :
+        hnand->ItCallback = HAL_NAND_ITCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hnand->State == HAL_NAND_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_NAND_MSP_INIT_CB_ID :
+        hnand->MspInitCallback = HAL_NAND_MspInit;
+        break;
+      case HAL_NAND_MSP_DEINIT_CB_ID :
+        hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### NAND Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the NAND interface.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables dynamically NAND ECC feature.
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Enable ECC feature */
+    (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+{
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Disable ECC feature */
+    (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically NAND ECC feature.
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  ECCval pointer to ECC value
+  * @param  Timeout maximum timeout to wait
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Get NAND ECC value */
+    status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### NAND State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the NAND controller
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  return the NAND state
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval HAL state
+  */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
+{
+  return hnand->State;
+}
+
+/**
+  * @brief  NAND memory read status
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval NAND status
+  */
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
+{
+  uint32_t data;
+  uint32_t deviceaddress;
+  UNUSED(hnand);
+
+  /* Identify the device address */
+  deviceaddress = NAND_DEVICE;
+
+  /* Send Read status operation command */
+  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
+
+  /* Read status register data */
+  data = *(__IO uint8_t *)deviceaddress;
+
+  /* Return the status */
+  if ((data & NAND_ERROR) == NAND_ERROR)
+  {
+    return NAND_ERROR;
+  }
+  else if ((data & NAND_READY) == NAND_READY)
+  {
+    return NAND_READY;
+  }
+  else
+  {
+    return NAND_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_NAND_MODULE_ENABLED  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_nor.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_nor.c
new file mode 100644
index 000000000..fd7675032
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_nor.c
@@ -0,0 +1,1642 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_nor.c
+  * @author  MCD Application Team
+  * @brief   NOR HAL module driver.
+  *          This file provides a generic firmware to drive NOR memories mounted
+  *          as external device.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a generic layered driver which contains a set of APIs used to
+      control NOR flash memories. It uses the FMC layer functions to interface
+      with NOR devices. This driver is used as follows:
+
+      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
+          with control and timing parameters for both normal and extended mode.
+
+      (+) Read NOR flash memory manufacturer code and device IDs using the function
+          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
+          structure declared by the function caller.
+
+      (+) Access NOR flash memory by read/write data unit operations using the functions
+          HAL_NOR_Read(), HAL_NOR_Program().
+
+      (+) Perform NOR flash erase block/chip operations using the functions
+          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+
+      (+) Read the NOR flash CFI (common flash interface) IDs using the function
+          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+          structure declared by the function caller.
+
+      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
+
+      (+) You can monitor the NOR device HAL state by calling the function
+          HAL_NOR_GetState()
+    [..]
+     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+         If a NOR flash device contains different operations and/or implementations,
+         it should be implemented separately.
+
+     *** NOR HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in NOR HAL driver.
+
+      (+) NOR_WRITE : NOR memory write data to specified address
+
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_NOR_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : NOR MspInit.
+        (+) MspDeInitCallback  : NOR MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : NOR MspInit.
+        (+) MspDeInitCallback  : NOR MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (overridden) functions in the HAL_NOR_Init
+      and  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
+      or HAL_NOR_Init function.
+
+      When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+
+/** @defgroup NOR NOR
+  * @brief NOR driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Defines NOR Private Defines
+  * @{
+  */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST_BYTE            (uint16_t)0x0AAA
+#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE        (uint16_t)0x00AA
+#define NOR_CMD_ADDRESS_SECOND_BYTE           (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_THIRD_BYTE            (uint16_t)0x0AAA
+
+#define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
+
+#define NOR_CMD_READ_ARRAY                    (uint16_t)0x00FF
+#define NOR_CMD_WORD_PROGRAM                  (uint16_t)0x0040
+#define NOR_CMD_BUFFERED_PROGRAM              (uint16_t)0x00E8
+#define NOR_CMD_CONFIRM                       (uint16_t)0x00D0
+#define NOR_CMD_BLOCK_ERASE                   (uint16_t)0x0020
+#define NOR_CMD_BLOCK_UNLOCK                  (uint16_t)0x0060
+#define NOR_CMD_READ_STATUS_REG               (uint16_t)0x0070
+#define NOR_CMD_CLEAR_STATUS_REG              (uint16_t)0x0050
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ4                   (uint16_t)0x0010
+#define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
+#define NOR_MASK_STATUS_DQ7                   (uint16_t)0x0080
+
+/* Address of the primary command set */
+#define NOR_ADDRESS_COMMAND_SET               (uint16_t)0x0013
+
+/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
+#define NOR_INTEL_SHARP_EXT_COMMAND_SET       (uint16_t)0x0001 /* Supported in this driver */
+#define NOR_AMD_FUJITSU_COMMAND_SET           (uint16_t)0x0002 /* Supported in this driver */
+#define NOR_INTEL_STANDARD_COMMAND_SET        (uint16_t)0x0003 /* Not Supported in this driver */
+#define NOR_AMD_FUJITSU_EXT_COMMAND_SET       (uint16_t)0x0004 /* Not Supported in this driver */
+#define NOR_WINDBOND_STANDARD_COMMAND_SET     (uint16_t)0x0006 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_STANDARD_COMMAND_SET   (uint16_t)0x0100 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_EXT_COMMAND_SET        (uint16_t)0x0101 /* Not Supported in this driver */
+#define NOR_PAGE_WRITE_COMMAND_SET            (uint16_t)0x0102 /* Not Supported in this driver */
+#define NOR_INTEL_PERFORMANCE_COMMAND_SET     (uint16_t)0x0200 /* Not Supported in this driver */
+#define NOR_INTEL_DATA_COMMAND_SET            (uint16_t)0x0210 /* Not Supported in this driver */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Variables NOR Private Variables
+  * @{
+  */
+
+static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+  * @{
+  */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+           ##### NOR Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize
+    the NOR memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform the NOR memory Initialization sequence
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Timing pointer to NOR control timing structure
+  * @param  ExtTiming pointer to NOR extended mode timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+                               FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+  uint32_t deviceaddress;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR handle parameter */
+  if (hnor == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hnor->State == HAL_NOR_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hnor->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+    if (hnor->MspInitCallback == NULL)
+    {
+      hnor->MspInitCallback = HAL_NOR_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hnor->MspInitCallback(hnor);
+#else
+    /* Initialize the low level hardware (MSP) */
+    HAL_NOR_MspInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+  }
+
+  /* Initialize NOR control Interface */
+  (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+  /* Initialize NOR timing Interface */
+  (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+
+  /* Initialize NOR extended mode timing Interface */
+  (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
+                                         hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+  /* Enable the NORSRAM device */
+  __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+
+  /* Initialize NOR Memory Data Width*/
+  if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_8B;
+  }
+  else
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_16B;
+  }
+
+  /* Enable FMC Peripheral */
+  __FMC_ENABLE();
+
+  /* Initialize the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }
+
+  if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
+  {
+    (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_PROTECTED;
+  }
+  else
+  {
+    /* Get the value of the command set */
+    if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+                NOR_CMD_DATA_CFI);
+    }
+    else
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+    }
+
+    hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+    status = HAL_NOR_ReturnToReadMode(hnor);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Perform NOR memory De-Initialization sequence
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
+{
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+  if (hnor->MspDeInitCallback == NULL)
+  {
+    hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hnor->MspDeInitCallback(hnor);
+#else
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_NOR_MspDeInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+
+  /* Configure the NOR registers with their reset values */
+  (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+
+  /* Reset the NOR controller state */
+  hnor->State = HAL_NOR_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnor);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  NOR MSP Init
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval None
+  */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NOR_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  NOR MSP DeInit
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval None
+  */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NOR_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  NOR MSP Wait for Ready/Busy signal
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Timeout Maximum timeout value
+  * @retval None
+  */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+  UNUSED(Timeout);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_NOR_MspWait could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
+  * @brief    Input Output and memory control functions
+  *
+  @verbatim
+  ==============================================================================
+                ##### NOR Input and Output functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to use and control the NOR memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read NOR flash IDs
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_ID  pointer to NOR ID structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR controller state */
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read ID command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_AUTO_SELECT);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_AUTO_SELECT);
+      }
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    if (status != HAL_ERROR)
+    {
+      /* Read the NOR IDs */
+      pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+      pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+                                                                     DEVICE_CODE1_ADDR);
+      pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+                                                                     DEVICE_CODE2_ADDR);
+      pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+                                                                     DEVICE_CODE3_ADDR);
+    }
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Returns the NOR memory to Read mode.
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR controller state */
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Read data from NOR memory
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress pointer to Device address
+  * @param  pData  pointer to read data
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR controller state */
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read data command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_READ_RESET);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_READ_RESET);
+      }
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    if (status != HAL_ERROR)
+    {
+      /* Read the data */
+      *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+    }
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program data to NOR memory
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress Device address
+  * @param  pData  pointer to the data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+  uint32_t deviceaddress;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send program data command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_PROGRAM);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+      }
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    if (status != HAL_ERROR)
+    {
+      /* Write the data */
+      NOR_WRITE(pAddress, *pData);
+    }
+
+    /* Check the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Reads a half-word buffer from the NOR memory.
+  * @param  hnor pointer to the NOR handle
+  * @param  uwAddress NOR memory internal address to read from.
+  * @param  pData pointer to the buffer that receives the data read from the
+  *         NOR memory.
+  * @param  uwBufferSize  number of Half word to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+                                     uint32_t uwBufferSize)
+{
+  uint32_t deviceaddress;
+  uint32_t size = uwBufferSize;
+  uint32_t address = uwAddress;
+  uint16_t *data = pData;
+  HAL_NOR_StateTypeDef state;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR controller state */
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read data command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_READ_RESET);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_READ_RESET);
+      }
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    if (status != HAL_ERROR)
+    {
+      /* Read buffer */
+      while (size > 0U)
+      {
+        *data = *(__IO uint16_t *)address;
+        data++;
+        address += 2U;
+        size--;
+      }
+    }
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Writes a half-word buffer to the NOR memory. This function must be used
+            only with S29GL128P NOR memory.
+  * @param  hnor pointer to the NOR handle
+  * @param  uwAddress NOR memory internal start write address
+  * @param  pData pointer to source data buffer.
+  * @param  uwBufferSize Size of the buffer to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+                                        uint32_t uwBufferSize)
+{
+  uint16_t *p_currentaddress;
+  const uint16_t *p_endaddress;
+  uint16_t *data = pData;
+  uint32_t deviceaddress;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Initialize variables */
+    p_currentaddress  = (uint16_t *)(deviceaddress + uwAddress);
+    p_endaddress      = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
+
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        /* Issue unlock command sequence */
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+      }
+      else
+      {
+        /* Issue unlock command sequence */
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      }
+      /* Write Buffer Load Command */
+      NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+      NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      /* Write Buffer Load Command */
+      NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
+      NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    if (status != HAL_ERROR)
+    {
+      /* Load Data into NOR Buffer */
+      while (p_currentaddress <= p_endaddress)
+      {
+        NOR_WRITE(p_currentaddress, *data);
+
+        data++;
+        p_currentaddress ++;
+      }
+
+      if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+      {
+        NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+      }
+      else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
+      {
+        NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
+      }
+    }
+
+    /* Check the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+
+}
+
+/**
+  * @brief  Erase the specified block of the NOR memory
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  BlockAddress  Block to erase address
+  * @param  Address Device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+  uint32_t deviceaddress;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send block erase command sequence */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+      }
+      NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    /* Check the NOR memory status and update the controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+
+}
+
+/**
+  * @brief  Erase the entire NOR chip.
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Address  Device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+  uint32_t deviceaddress;
+  HAL_StatusTypeDef status = HAL_OK;
+  UNUSED(Address);
+
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send NOR chip erase command sequence */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
+                  NOR_CMD_DATA_CHIP_ERASE);
+      }
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+
+    /* Check the NOR memory status and update the controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Read NOR flash CFI IDs
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_CFI  pointer to NOR CFI IDs structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+
+  /* Check the NOR controller state */
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read CFI query command */
+    if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+                NOR_CMD_DATA_CFI);
+    }
+    else
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+    }
+    /* read the NOR CFI information */
+    pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+    pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+    pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+    pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User NOR Callback
+  *         To be used to override the weak predefined callback
+  * @param hnor : NOR handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
+  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+                                           pNOR_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_NOR_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  state = hnor->State;
+  if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_NOR_MSP_INIT_CB_ID :
+        hnor->MspInitCallback = pCallback;
+        break;
+      case HAL_NOR_MSP_DEINIT_CB_ID :
+        hnor->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User NOR Callback
+  *         NOR Callback is redirected to the weak predefined callback
+  * @param hnor : NOR handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
+  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_NOR_StateTypeDef state;
+
+  state = hnor->State;
+  if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_NOR_MSP_INIT_CB_ID :
+        hnor->MspInitCallback = HAL_NOR_MspInit;
+        break;
+      case HAL_NOR_MSP_DEINIT_CB_ID :
+        hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+
+/**
+  * @}
+  */
+
+/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### NOR Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the NOR interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically NOR write operation.
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_PROTECTED)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Enable write operation */
+    (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically NOR write operation.
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Disable write operation */
+    (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_PROTECTED;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### NOR State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the NOR controller
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  return the NOR controller state
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @retval NOR controller state
+  */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
+{
+  return hnor->State;
+}
+
+/**
+  * @brief  Returns the NOR operation status.
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Address Device address
+  * @param  Timeout NOR programming Timeout
+  * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+  *         or HAL_NOR_STATUS_TIMEOUT
+  */
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{
+  HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+  uint16_t tmpsr1;
+  uint16_t tmpsr2;
+  uint32_t tickstart;
+
+  /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+  HAL_NOR_MspWait(hnor, Timeout);
+
+  /* Get the NOR memory operation status -------------------------------------*/
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+  {
+    while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          status = HAL_NOR_STATUS_TIMEOUT;
+        }
+      }
+
+      /* Read NOR status register (DQ6 and DQ5) */
+      tmpsr1 = *(__IO uint16_t *)Address;
+      tmpsr2 = *(__IO uint16_t *)Address;
+
+      /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+      {
+        return HAL_NOR_STATUS_SUCCESS ;
+      }
+
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+      {
+        status = HAL_NOR_STATUS_ONGOING;
+      }
+
+      tmpsr1 = *(__IO uint16_t *)Address;
+      tmpsr2 = *(__IO uint16_t *)Address;
+
+      /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+      {
+        return HAL_NOR_STATUS_SUCCESS;
+      }
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+      {
+        return HAL_NOR_STATUS_ERROR;
+      }
+    }
+  }
+  else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+  {
+    do
+    {
+      NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+      tmpsr2 = *(__IO uint16_t *)(Address);
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          return HAL_NOR_STATUS_TIMEOUT;
+        }
+      }
+    } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
+
+    NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+    tmpsr1 = *(__IO uint16_t *)(Address);
+    if ((tmpsr1  & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
+    {
+      /* Clear the Status Register  */
+      NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+      status = HAL_NOR_STATUS_ERROR;
+    }
+    else
+    {
+      status = HAL_NOR_STATUS_SUCCESS;
+    }
+  }
+  else
+  {
+    /* Primary command set not supported by the driver */
+    status = HAL_NOR_STATUS_ERROR;
+  }
+
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pcd.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pcd.c
new file mode 100644
index 000000000..06428306e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pcd.c
@@ -0,0 +1,2306 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pcd.c
+  * @author  MCD Application Team
+  * @brief   PCD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The PCD HAL driver can be used as follows:
+
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:
+         PCD_HandleTypeDef  hpcd;
+
+     (#) Fill parameters of Init structure in HCD handle
+
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+         (##) Enable the PCD/USB Low Level interface clock using
+              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+
+         (##) Initialize the related GPIO clocks
+         (##) Configure PCD pin-out
+         (##) Configure PCD NVIC interrupt
+
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:
+         (##) hpcd.pData = pdev;
+
+     (#)Enable PCD transmission and reception:
+         (##) HAL_PCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCD PCD
+  * @brief PCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+  * @{
+  */
+#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+  * @{
+  */
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PCD according to the specified
+  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+  uint8_t i;
+
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+  if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->SOFCallback = HAL_PCD_SOFCallback;
+    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+    hpcd->ResetCallback = HAL_PCD_ResetCallback;
+    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+    if (hpcd->MspInitCallback == NULL)
+    {
+      hpcd->MspInitCallback = HAL_PCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hpcd->MspInitCallback(hpcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Disable the Interrupts */
+  __HAL_PCD_DISABLE(hpcd);
+
+  /*Init the Core (common init.) */
+  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  /* Force Device Mode */
+  if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  /* Init endpoints structures */
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    /* Init ep structure */
+    hpcd->IN_ep[i].is_in = 1U;
+    hpcd->IN_ep[i].num = i;
+    hpcd->IN_ep[i].tx_fifo_num = i;
+    /* Control until ep is activated */
+    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+    hpcd->IN_ep[i].maxpacket = 0U;
+    hpcd->IN_ep[i].xfer_buff = 0U;
+    hpcd->IN_ep[i].xfer_len = 0U;
+  }
+
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    hpcd->OUT_ep[i].is_in = 0U;
+    hpcd->OUT_ep[i].num = i;
+    /* Control until ep is activated */
+    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+    hpcd->OUT_ep[i].maxpacket = 0U;
+    hpcd->OUT_ep[i].xfer_buff = 0U;
+    hpcd->OUT_ep[i].xfer_len = 0U;
+  }
+
+  /* Init Device */
+  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  hpcd->USB_Address = 0U;
+  hpcd->State = HAL_PCD_STATE_READY;
+
+  /* Activate LPM */
+  if (hpcd->Init.lpm_enable == 1U)
+  {
+    (void)HAL_PCDEx_ActivateLPM(hpcd);
+  }
+
+  (void)USB_DevDisconnect(hpcd->Instance);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the PCD peripheral.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Stop Device */
+  if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  if (hpcd->MspDeInitCallback == NULL)
+  {
+    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hpcd->MspDeInitCallback(hpcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  hpcd->State = HAL_PCD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB PCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+                                           HAL_PCD_CallbackIDTypeDef CallbackID,
+                                           pPCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = pCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = pCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB PCD Callback
+  *         USB PCD callback is redirected to the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = HAL_PCD_SOFCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = HAL_PCD_ResetCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data OUT Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Data OUT Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data IN Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_DataInStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Data IN Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso OUT incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Iso OUT incomplete Callback
+  *         USB PCD Iso OUT incomplete Callback is redirected
+  *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso IN incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD Iso IN incomplete Callback
+  *         USB PCD Iso IN incomplete Callback is redirected
+  *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD BCD Callback
+  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD BCD Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD BCD Callback
+  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD LPM Callback
+  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD LPM Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister the USB PCD LPM Callback
+  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  __HAL_PCD_ENABLE(hpcd);
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  __HAL_PCD_DISABLE(hpcd);
+  (void)USB_DevDisconnect(hpcd->Instance);
+
+  (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/**
+  * @brief  Handles PCD interrupt request.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  USB_OTG_EPTypeDef *ep;
+  uint32_t i;
+  uint32_t ep_intr;
+  uint32_t epint;
+  uint32_t epnum;
+  uint32_t fifoemptymsk;
+  uint32_t RegVal;
+
+  /* ensure that we are in device mode */
+  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+  {
+    /* avoid spurious interrupt */
+    if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+    {
+      return;
+    }
+
+    /* store current frame number */
+    hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+    {
+      /* incorrect mode, acknowledge the interrupt */
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+    }
+
+    /* Handle RxQLevel Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+    {
+      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+      RegVal = USBx->GRXSTSP;
+
+      ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
+
+      if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
+      {
+        if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
+        {
+          (void)USB_ReadPacket(USBx, ep->xfer_buff,
+                               (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
+
+          ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
+          ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
+        }
+      }
+      else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+      {
+        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+        ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
+      }
+      else
+      {
+        /* ... */
+      }
+
+      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+    {
+      epnum = 0U;
+
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+
+      while (ep_intr != 0U)
+      {
+        if ((ep_intr & 0x1U) != 0U)
+        {
+          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+            (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
+          }
+
+          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+            /* Class B setup phase done for previous decoded setup */
+            (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
+          }
+
+          if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+          }
+
+          /* Clear OUT Endpoint disable interrupt */
+          if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
+          {
+            if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
+            {
+              USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
+            }
+
+            ep = &hpcd->OUT_ep[epnum];
+
+            if (ep->is_iso_incomplete == 1U)
+            {
+              ep->is_iso_incomplete = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+              hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+              HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+            }
+
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
+          }
+
+          /* Clear Status Phase Received interrupt */
+          if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+          }
+
+          /* Clear OUT NAK interrupt */
+          if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1U;
+      }
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+    {
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+
+      epnum = 0U;
+
+      while (ep_intr != 0U)
+      {
+        if ((ep_intr & 0x1U) != 0U) /* In ITR */
+        {
+          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+          {
+            fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+
+            if (hpcd->Init.dma_enable == 1U)
+            {
+              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
+
+              /* this is ZLP, so prepare EP0 for next setup */
+              if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
+              {
+                /* prepare to rx more setup packets */
+                (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+              }
+            }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+            hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+          }
+          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+          }
+          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+          }
+          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+          }
+          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+          {
+            (void)USB_FlushTxFifo(USBx, epnum);
+
+            ep = &hpcd->IN_ep[epnum];
+
+            if (ep->is_iso_incomplete == 1U)
+            {
+              ep->is_iso_incomplete = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+              hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+              HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+            }
+
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+          }
+          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+          {
+            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1U;
+      }
+    }
+
+    /* Handle Resume Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+    {
+      /* Clear the Remote Wake-up Signaling */
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+
+      if (hpcd->LPM_State == LPM_L1)
+      {
+        hpcd->LPM_State = LPM_L0;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->ResumeCallback(hpcd);
+#else
+        HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+    }
+
+    /* Handle Suspend Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+    {
+      if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->SuspendCallback(hpcd);
+#else
+        HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+    }
+
+    /* Handle LPM Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+    {
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+
+      if (hpcd->LPM_State == LPM_L0)
+      {
+        hpcd->LPM_State = LPM_L1;
+        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->SuspendCallback(hpcd);
+#else
+        HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+
+    /* Handle Reset Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+    {
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+
+      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+      {
+        USBx_INEP(i)->DIEPINT = 0xFB7FU;
+        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+        USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+      }
+      USBx_DEVICE->DAINTMSK |= 0x10001U;
+
+      if (hpcd->Init.use_dedicated_ep1 != 0U)
+      {
+        USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
+                                   USB_OTG_DOEPMSK_XFRCM |
+                                   USB_OTG_DOEPMSK_EPDM;
+
+        USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
+                                  USB_OTG_DIEPMSK_XFRCM |
+                                  USB_OTG_DIEPMSK_EPDM;
+      }
+      else
+      {
+        USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
+                                USB_OTG_DOEPMSK_XFRCM |
+                                USB_OTG_DOEPMSK_EPDM |
+                                USB_OTG_DOEPMSK_OTEPSPRM |
+                                USB_OTG_DOEPMSK_NAKM;
+
+        USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
+                                USB_OTG_DIEPMSK_XFRCM |
+                                USB_OTG_DIEPMSK_EPDM;
+      }
+
+      /* Set Default Address to 0 */
+      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+
+      /* setup EP0 to receive SETUP packets */
+      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
+                             (uint8_t *)hpcd->Setup);
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+    }
+
+    /* Handle Enumeration done Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+    {
+      (void)USB_ActivateSetup(hpcd->Instance);
+      hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
+
+      /* Set USB Turnaround time */
+      (void)USB_SetTurnaroundTime(hpcd->Instance,
+                                  HAL_RCC_GetHCLKFreq(),
+                                  (uint8_t)hpcd->Init.speed);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ResetCallback(hpcd);
+#else
+      HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+    }
+
+    /* Handle SOF Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->SOFCallback(hpcd);
+#else
+      HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+    }
+
+    /* Handle Global OUT NAK effective Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
+    {
+      USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
+
+      for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+      {
+        if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
+        {
+          /* Abort current transaction and disable the EP */
+          (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
+        }
+      }
+    }
+
+    /* Handle Incomplete ISO IN Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+      for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+      {
+        RegVal = USBx_INEP(epnum)->DIEPCTL;
+
+        if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
+            ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
+        {
+          hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
+
+          /* Abort current transaction and disable the EP */
+          (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
+        }
+      }
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+    }
+
+    /* Handle Incomplete ISO OUT Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+      for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+      {
+        RegVal = USBx_OUTEP(epnum)->DOEPCTL;
+
+        if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
+            ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
+            (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
+        {
+          hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
+
+          USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
+
+          if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
+          {
+            USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
+            break;
+          }
+        }
+      }
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    }
+
+    /* Handle Connection event Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ConnectCallback(hpcd);
+#else
+      HAL_PCD_ConnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+    }
+
+    /* Handle Disconnection event Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+    {
+      RegVal = hpcd->Instance->GOTGINT;
+
+      if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DisconnectCallback(hpcd);
+#else
+        HAL_PCD_DisconnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      hpcd->Instance->GOTGINT |= RegVal;
+    }
+  }
+}
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+
+/**
+  * @brief  Data OUT stage callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Data IN stage callback
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataInStageCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SetupStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Start Of Frame callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SOFCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Reset callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Suspend event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SuspendCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Resume event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResumeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO OUT callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO IN callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Connection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ConnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Disconnection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DisconnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Connect the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disconnect the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the USB Device address.
+  * @param  hpcd PCD handle
+  * @param  address new device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+  __HAL_LOCK(hpcd);
+  hpcd->USB_Address = address;
+  (void)USB_SetDevAddress(hpcd->Instance, address);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Open and configure an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  ep_mps endpoint max packet size
+  * @param  ep_type endpoint type
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+                                  uint16_t ep_mps, uint8_t ep_type)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->num = ep_addr & EP_ADDR_MSK;
+  ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
+  ep->type = ep_type;
+
+  if (ep->is_in != 0U)
+  {
+    /* Assign a Tx FIFO */
+    ep->tx_fifo_num = ep->num;
+  }
+
+  /* Set initial data PID. */
+  if (ep_type == EP_TYPE_BULK)
+  {
+    ep->data_pid_start = 0U;
+  }
+
+  __HAL_LOCK(hpcd);
+  (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return ret;
+}
+
+/**
+  * @brief  Deactivate an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Receive an amount of data.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the reception buffer
+  * @param  len amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    ep->dma_addr = (uint32_t)pBuf;
+  }
+
+  (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Received Data Size
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval Data Size
+  */
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
+{
+  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+}
+/**
+  * @brief  Send an amount of data
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the transmission buffer
+  * @param  len amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    ep->dma_addr = (uint32_t)pBuf;
+  }
+
+  (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set a STALL condition over an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+
+  (void)USB_EPSetStall(hpcd->Instance, ep);
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+  }
+
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear a STALL condition over in an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_EPClearStall(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+   * @brief  Abort an USB EP transaction.
+   * @param  hpcd PCD handle
+   * @param  ep_addr endpoint address
+   * @retval HAL status
+   */
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef ret;
+  PCD_EPTypeDef *ep;
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+  }
+
+  /* Stop Xfer */
+  ret = USB_EPStopXfer(hpcd->Instance, ep);
+
+  return ret;
+}
+
+/**
+  * @brief  Flush an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  __HAL_LOCK(hpcd);
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
+  }
+  else
+  {
+    (void)USB_FlushRxFifo(hpcd->Instance);
+  }
+
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate remote wakeup signalling
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_ActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @brief  De-activate remote wakeup signalling.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PCD handle state.
+  * @param  hpcd PCD handle
+  * @retval HAL state
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
+{
+  return hpcd->State;
+}
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/**
+  * @brief  Set the USB Device high speed test mode.
+  * @param  hpcd PCD handle
+  * @param  testmode USB Device high speed test mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode)
+{
+  const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  switch (testmode)
+  {
+    case TEST_J:
+    case TEST_K:
+    case TEST_SE0_NAK:
+    case TEST_PACKET:
+    case TEST_FORCE_EN:
+      USBx_DEVICE->DCTL |= (uint32_t)testmode << 4;
+      break;
+
+    default:
+      break;
+  }
+
+  return HAL_OK;
+}
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+  * @{
+  */
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/**
+  * @brief  Check FIFO for the next packet to be loaded.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  USB_OTG_EPTypeDef *ep;
+  uint32_t len;
+  uint32_t len32b;
+  uint32_t fifoemptymsk;
+
+  ep = &hpcd->IN_ep[epnum];
+
+  if (ep->xfer_count > ep->xfer_len)
+  {
+    return HAL_ERROR;
+  }
+
+  len = ep->xfer_len - ep->xfer_count;
+
+  if (len > ep->maxpacket)
+  {
+    len = ep->maxpacket;
+  }
+
+  len32b = (len + 3U) / 4U;
+
+  while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
+         (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
+  {
+    /* Write the FIFO */
+    len = ep->xfer_len - ep->xfer_count;
+
+    if (len > ep->maxpacket)
+    {
+      len = ep->maxpacket;
+    }
+    len32b = (len + 3U) / 4U;
+
+    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
+                          (uint8_t)hpcd->Init.dma_enable);
+
+    ep->xfer_buff  += len;
+    ep->xfer_count += len;
+  }
+
+  if (ep->xfer_len <= ep->xfer_count)
+  {
+    fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  process EP OUT transfer complete interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_EPTypeDef *ep;
+  const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+    }
+    else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
+    {
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+    }
+    else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        ep = &hpcd->OUT_ep[epnum];
+
+        /* out data packet received over EP */
+        ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+        if (epnum == 0U)
+        {
+          if (ep->xfer_len == 0U)
+          {
+            /* this is ZLP, so prepare EP0 for next setup */
+            (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+          }
+          else
+          {
+            ep->xfer_buff += ep->xfer_count;
+          }
+        }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+  else
+  {
+    if (gSNPSiD == USB_OTG_CORE_ID_310A)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+        {
+          CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+        }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+      {
+        /* this is ZLP, so prepare EP0 for next setup */
+        (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
+      }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  process EP OUT setup packet received interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+      ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+  {
+    CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+  }
+
+  /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  hpcd->SetupStageCallback(hpcd);
+#else
+  HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
+  {
+    (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+  }
+
+  return HAL_OK;
+}
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pcd_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pcd_ex.c
new file mode 100644
index 000000000..ca1548fd3
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pcd_ex.c
@@ -0,0 +1,323 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @brief   PCD Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCDEx PCDEx
+  * @brief PCD Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    PCDEx control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Update FIFO configuration
+
+@endverbatim
+  * @{
+  */
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/**
+  * @brief  Set Tx FIFO
+  * @param  hpcd PCD handle
+  * @param  fifo The number of Tx fifo
+  * @param  size Fifo size
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+  uint8_t i;
+  uint32_t Tx_Offset;
+
+  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
+      When a TxFIFO is not used, the Configuration should be as follows:
+          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txm can use the space allocated for Txn.
+         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txn should be configured with the minimum space of 16 words
+     The FIFO is used optimally when used TxFIFOs are allocated in the top
+         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+
+  Tx_Offset = hpcd->Instance->GRXFSIZ;
+
+  if (fifo == 0U)
+  {
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
+  }
+  else
+  {
+    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+    for (i = 0U; i < (fifo - 1U); i++)
+    {
+      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
+    }
+
+    /* Multiply Tx_Size by 2 to get higher performance */
+    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Rx FIFO
+  * @param  hpcd PCD handle
+  * @param  size Size of Rx fifo
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+  hpcd->Instance->GRXFSIZ = size;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 1U;
+  hpcd->LPM_State = LPM_L0;
+  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 0U;
+  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Enable DCD : Data Contact Detect */
+  USBx->GCCFG |= USB_OTG_GCCFG_DCDETEN;
+
+  /* Wait for Min DCD Timeout */
+  HAL_Delay(300U);
+
+
+  /* Primary detection: checks if connected to Standard Downstream Port
+  (without charging capability) */
+  USBx->GCCFG &= ~USB_OTG_GCCFG_DCDETEN;
+  HAL_Delay(50U);
+  USBx->GCCFG |= USB_OTG_GCCFG_PDETEN;
+  HAL_Delay(50U);
+
+  if ((USBx->GCCFG & USB_OTG_GCCFG_CHGDET) == 0U)
+  {
+    /* Case of Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* start secondary detection to check connection to Charging Downstream
+    Port or Dedicated Charging Port */
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN);
+    HAL_Delay(50U);
+    USBx->GCCFG |= USB_OTG_GCCFG_SDETEN;
+    HAL_Delay(50U);
+
+    if ((USBx->GCCFG & USB_OTG_GCCFG_FSVPLUS) == USB_OTG_GCCFG_FSVPLUS)
+    {
+      /* case Dedicated Charging Port  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* case Charging Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Battery Charging capability discovery finished */
+  (void)HAL_PCDEx_DeActivateBCD(hpcd);
+
+  /* Check for the Timeout, else start USB Device */
+  if ((HAL_GetTick() - tickstart) > 1000U)
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN);
+
+  hpcd->battery_charging_active = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN);
+
+  hpcd->battery_charging_active = 0U;
+
+  return HAL_OK;
+}
+
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pka.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pka.c
new file mode 100644
index 000000000..79fd679df
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pka.c
@@ -0,0 +1,3042 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pka.c
+  * @author  MCD Application Team
+  * @brief   PKA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of public key accelerator(PKA):
+  *           + Initialization and de-initialization functions
+  *           + Start an operation
+  *           + Retrieve the operation result
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The PKA HAL driver can be used as follows:
+
+    (#) Declare a PKA_HandleTypeDef handle structure, for example: PKA_HandleTypeDef  hpka;
+
+    (#) Initialize the PKA low level resources by implementing the HAL_PKA_MspInit() API:
+        (##) Enable the PKA interface clock
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the PKA interrupt priority
+            (+++) Enable the NVIC PKA IRQ Channel
+
+    (#) Initialize the PKA registers by calling the HAL_PKA_Init() API which trig
+        HAL_PKA_MspInit().
+
+    (#) Fill entirely the input structure corresponding to your operation:
+        For instance: PKA_ModExpInTypeDef for HAL_PKA_ModExp().
+
+    (#) Execute the operation (in polling or interrupt) and check the returned value.
+
+    (#) Retrieve the result of the operation (For instance, HAL_PKA_ModExp_GetResult for
+        HAL_PKA_ModExp operation). The function to gather the result is different for each
+        kind of operation. The correspondence can be found in the following section.
+
+    (#) Call the function HAL_PKA_DeInit() to restore the default configuration which trig
+        HAL_PKA_MspDeInit().
+
+    *** High level operation ***
+    =================================
+    [..]
+      (+) Input structure requires buffers as uint8_t array.
+
+      (+) Output structure requires buffers as uint8_t array.
+
+      (+) Modular exponentiation using:
+      (++) HAL_PKA_ModExp().
+      (++) HAL_PKA_ModExp_IT().
+      (++) HAL_PKA_ModExpFastMode().
+      (++) HAL_PKA_ModExpFastMode_IT().
+      (++) HAL_PKA_ModExpProtectMode().
+      (++) HAL_PKA_ModExpProtectMode_IT().
+      (++) HAL_PKA_ModExp_GetResult() to retrieve the result of the operation.
+
+      (+) RSA Chinese Remainder Theorem (CRT) using:
+      (++) HAL_PKA_RSACRTExp().
+      (++) HAL_PKA_RSACRTExp_IT().
+      (++) HAL_PKA_RSACRTExp_GetResult() to retrieve the result of the operation.
+
+      (+) ECC Point Check using:
+      (++) HAL_PKA_PointCheck().
+      (++) HAL_PKA_PointCheck_IT().
+      (++) HAL_PKA_PointCheck_IsOnCurve() to retrieve the result of the operation.
+
+      (+) ECDSA Sign
+      (++) HAL_PKA_ECDSASign().
+      (++) HAL_PKA_ECDSASign_IT().
+      (++) HAL_PKA_ECDSASign_GetResult() to retrieve the result of the operation.
+
+      (+) ECDSA Verify
+      (++) HAL_PKA_ECDSAVerif().
+      (++) HAL_PKA_ECDSAVerif_IT().
+      (++) HAL_PKA_ECDSAVerif_IsValidSignature() to retrieve the result of the operation.
+
+      (+) ECC Scalar Multiplication using:
+      (++) HAL_PKA_ECCMul().
+      (++) HAL_PKA_ECCMul_IT().
+      (++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation.
+
+      (+) ECC  double base  ladder using:
+      (++) HAL_PKA_ECCDoubleBaseLadder().
+      (++) HAL_PKA_ECCDoubleBaseLadder_IT().
+      (++) HAL_PKA_ECCDoubleBaseLadder_GetResult() to retrieve the result of the operation.
+
+      (+) ECC  projective to affine using:
+      (++) HAL_PKA_ECCProjective2Affine().
+      (++) HAL_PKA_ECCProjective2Affine_IT().
+      (++) HAL_PKA_ECCProjective2Affine_GetResult() to retrieve the result of the operation.
+
+      (+) ECC  complete addition using:
+      (++) HAL_PKA_ECCCompleteAddition().
+      (++) HAL_PKA_ECCCompleteAddition_IT().
+      (++) HAL_PKA_ECCCompleteAddition_GetResult() to retrieve the result of the operation.
+
+    *** Low level operation ***
+    =================================
+    [..]
+      (+) Input structure requires buffers as uint32_t array.
+
+      (+) Output structure requires buffers as uint32_t array.
+
+      (+) Arithmetic addition using:
+      (++) HAL_PKA_Add().
+      (++) HAL_PKA_Add_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+            The resulting size can be the input parameter or the input parameter size + 1 (overflow).
+
+      (+) Arithmetic subtraction using:
+      (++) HAL_PKA_Sub().
+      (++) HAL_PKA_Sub_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+      (+) Arithmetic multiplication using:
+      (++) HAL_PKA_Mul().
+      (++) HAL_PKA_Mul_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+      (+) Comparison using:
+      (++) HAL_PKA_Cmp().
+      (++) HAL_PKA_Cmp_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+      (+) Modular addition using:
+      (++) HAL_PKA_ModAdd().
+      (++) HAL_PKA_ModAdd_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+      (+) Modular subtraction using:
+      (++) HAL_PKA_ModSub().
+      (++) HAL_PKA_ModSub_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+      (+) Modular inversion using:
+      (++) HAL_PKA_ModInv().
+      (++) HAL_PKA_ModInv_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+      (+) Modular reduction using:
+      (++) HAL_PKA_ModRed().
+      (++) HAL_PKA_ModRed_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+      (+) Montgomery multiplication using:
+      (++) HAL_PKA_MontgomeryMul().
+      (++) HAL_PKA_MontgomeryMul_IT().
+      (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
+
+    *** Montgomery parameter ***
+    =================================
+      (+) For some operation, the computation of the Montgomery parameter is a prerequisite.
+      (+) Input structure requires buffers as uint8_t array.
+      (+) Output structure requires buffers as uint32_t array.(Only used inside PKA).
+      (+) You can compute the Montgomery parameter using:
+      (++) HAL_PKA_MontgomeryParam().
+      (++) HAL_PKA_MontgomeryParam_IT().
+      (++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation.
+
+    *** Polling mode operation ***
+    ===================================
+    [..]
+      (+) When an operation is started in polling mode, the function returns when:
+      (++) A timeout is encounter.
+      (++) The operation is completed.
+
+    *** Interrupt mode operation ***
+    ===================================
+    [..]
+      (+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA.
+      (+) Enable the IRQ using HAL_NVIC_EnableIRQ().
+      (+) When an operation is started in interrupt mode, the function returns immediately.
+      (+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called.
+      (+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called.
+      (+) To stop any operation in interrupt mode, use HAL_PKA_Abort().
+
+    *** Utilities ***
+    ===================================
+    [..]
+      (+) To clear the PKA RAM, use HAL_PKA_RAMReset().
+      (+) To get current state, use HAL_PKA_GetState().
+      (+) To get current error, use HAL_PKA_GetError().
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_PKA_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function HAL_PKA_RegisterCallback() allows to register following callbacks:
+       (+) OperationCpltCallback : callback for End of operation.
+       (+) ErrorCallback         : callback for error detection.
+       (+) MspInitCallback       : callback for Msp Init.
+       (+) MspDeInitCallback     : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function HAL_PKA_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) OperationCpltCallback : callback for End of operation.
+       (+) ErrorCallback         : callback for error detection.
+       (+) MspInitCallback       : callback for Msp Init.
+       (+) MspDeInitCallback     : callback for Msp DeInit.
+     [..]
+
+     By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit()
+     or HAL_PKA_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
+
+/** @defgroup PKA PKA
+  * @brief    PKA HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PKA_Private_Define PKA Private Define
+  * @{
+  */
+#define PKA_RAM_SIZE 1334U
+
+/* Private macro -------------------------------------------------------------*/
+#define __PKA_RAM_PARAM_END(TAB,INDEX)                do{                                   \
+                                                                    TAB[INDEX] = 0UL;       \
+                                                                    TAB[INDEX + 1U] = 0UL;  \
+                                                                  } while(0)
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+static uint32_t   primeordersize;
+static uint32_t   opsize;
+static uint32_t   modulussize;
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup PKA_Private_Functions PKA Private Functions
+  * @{
+  */
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka);
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode);
+uint32_t PKA_GetBitSize_u8(uint32_t byteNumber);
+uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
+uint32_t PKA_GetBitSize_u32(uint32_t wordNumber);
+uint32_t PKA_GetArraySize_u8(uint32_t bitSize);
+void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n);
+void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n);
+void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n);
+HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout);
+HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode);
+void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
+void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
+void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in);
+void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in);
+void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
+void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
+void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
+void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
+void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
+void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
+void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
+void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1);
+void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
+                 const uint8_t *pOp3);
+void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in);
+void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in);
+void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in);
+HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status,
+                                             uint32_t Tickstart, uint32_t Timeout);
+uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PKA_Exported_Functions PKA Exported Functions
+  * @{
+  */
+
+/** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the PKAx peripheral:
+
+      (+) User must implement HAL_PKA_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, IT and NVIC ).
+
+      (+) Call the function HAL_PKA_Init() to configure the device.
+
+      (+) Call the function HAL_PKA_DeInit() to restore the default configuration
+          of the selected PKAx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the PKA according to the specified
+  *         parameters in the PKA_InitTypeDef and initialize the associated handle.
+  * @param  hpka PKA handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka)
+{
+  HAL_StatusTypeDef err = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check the PKA handle allocation */
+  if (hpka != NULL)
+  {
+    /* Check the parameters */
+    assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
+
+    if (hpka->State == HAL_PKA_STATE_RESET)
+    {
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+      /* Init the PKA Callback settings */
+      hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
+      hpka->ErrorCallback         = HAL_PKA_ErrorCallback;         /* Legacy weak ErrorCallback         */
+
+      if (hpka->MspInitCallback == NULL)
+      {
+        hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit  */
+      }
+
+      /* Init the low level hardware */
+      hpka->MspInitCallback(hpka);
+#else
+      /* Init the low level hardware */
+      HAL_PKA_MspInit(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+    }
+
+    /* Set the state to busy */
+    hpka->State = HAL_PKA_STATE_BUSY;
+
+    /* Reset the control register and enable the PKA */
+    hpka->Instance->CR = PKA_CR_EN;
+
+    /* Get current tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait the INITOK flag Setting */
+    if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, 5000) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Reset any pending flag */
+    SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+    /* Initialize the error code */
+    hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+    /* Set the state to ready */
+    hpka->State = HAL_PKA_STATE_READY;
+  }
+  else
+  {
+    err = HAL_ERROR;
+  }
+
+  return err;
+}
+
+/**
+  * @brief  DeInitialize the PKA peripheral.
+  * @param  hpka PKA handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka)
+{
+  HAL_StatusTypeDef err = HAL_OK;
+
+  /* Check the PKA handle allocation */
+  if (hpka != NULL)
+  {
+    /* Check the parameters */
+    assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
+
+    /* Set the state to busy */
+    hpka->State = HAL_PKA_STATE_BUSY;
+
+    /* Reset the control register */
+    /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
+    hpka->Instance->CR = 0;
+
+    /* Reset any pending flag */
+    SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+    if (hpka->MspDeInitCallback == NULL)
+    {
+      hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit  */
+    }
+
+    /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+    hpka->MspDeInitCallback(hpka);
+#else
+    /* DeInit the low level hardware: CLOCK, NVIC */
+    HAL_PKA_MspDeInit(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+    /* Reset the error code */
+    hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+    /* Reset the state */
+    hpka->State = HAL_PKA_STATE_RESET;
+  }
+  else
+  {
+    err = HAL_ERROR;
+  }
+
+  return err;
+}
+
+/**
+  * @brief  Initialize the PKA MSP.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+__weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpka);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PKA_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the PKA MSP.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+__weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpka);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PKA_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User PKA Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hpka Pointer to a PKA_HandleTypeDef structure that contains
+  *                the configuration information for the specified PKA.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
+  *          @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID,
+                                           pPKA_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_PKA_STATE_READY == hpka->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PKA_OPERATION_COMPLETE_CB_ID :
+        hpka->OperationCpltCallback = pCallback;
+        break;
+
+      case HAL_PKA_ERROR_CB_ID :
+        hpka->ErrorCallback = pCallback;
+        break;
+
+      case HAL_PKA_MSPINIT_CB_ID :
+        hpka->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PKA_MSPDEINIT_CB_ID :
+        hpka->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_PKA_STATE_RESET == hpka->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PKA_MSPINIT_CB_ID :
+        hpka->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PKA_MSPDEINIT_CB_ID :
+        hpka->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a PKA Callback
+  *         PKA callback is redirected to the weak predefined callback
+  * @param  hpka Pointer to a PKA_HandleTypeDef structure that contains
+  *                the configuration information for the specified PKA.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
+  *          @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_PKA_STATE_READY == hpka->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PKA_OPERATION_COMPLETE_CB_ID :
+        hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
+        break;
+
+      case HAL_PKA_ERROR_CB_ID :
+        hpka->ErrorCallback = HAL_PKA_ErrorCallback;                 /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_PKA_MSPINIT_CB_ID :
+        hpka->MspInitCallback = HAL_PKA_MspInit;                     /* Legacy weak MspInit              */
+        break;
+
+      case HAL_PKA_MSPDEINIT_CB_ID :
+        hpka->MspDeInitCallback = HAL_PKA_MspDeInit;                 /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_PKA_STATE_RESET == hpka->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PKA_MSPINIT_CB_ID :
+        hpka->MspInitCallback = HAL_PKA_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_PKA_MSPDEINIT_CB_ID :
+        hpka->MspDeInitCallback = HAL_PKA_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PKA_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the PKA operations.
+
+    (#) There are two modes of operation:
+
+       (++) Blocking mode : The operation is performed in the polling mode.
+            These functions return when data operation is completed.
+       (++) No-Blocking mode : The operation is performed using Interrupts.
+            These functions return immediately.
+            The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
+            The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
+            To stop any operation in interrupt mode, use HAL_PKA_Abort().
+
+    (#) Blocking mode functions are :
+
+        (++) HAL_PKA_ModExp()
+        (++) HAL_PKA_ModExpFastMode()
+        (++) HAL_PKA_ModExpProtectMode()
+        (++) HAL_PKA_ModExp_GetResult();
+
+        (++) HAL_PKA_ECDSASign()
+        (++) HAL_PKA_ECDSASign_GetResult();
+
+        (++) HAL_PKA_ECDSAVerif()
+        (++) HAL_PKA_ECDSAVerif_IsValidSignature();
+
+        (++) HAL_PKA_RSACRTExp()
+        (++) HAL_PKA_RSACRTExp_GetResult();
+
+        (++) HAL_PKA_PointCheck()
+        (++) HAL_PKA_PointCheck_IsOnCurve();
+
+        (++) HAL_PKA_ECCMul()
+        (++) HAL_PKA_ECCMulFastMode()
+        (++) HAL_PKA_ECCMul_GetResult();
+
+        (++) HAL_PKA_ECCMulEx()
+        (++) HAL_PKA_ECCDoubleBaseLadder()
+        (++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
+        (++) HAL_PKA_ECCProjective2Affine()
+        (++) HAL_PKA_ECCProjective2Affine_GetResult();
+        (++) HAL_PKA_ECCCompleteAddition()
+        (++) HAL_PKA_ECCCompleteAddition_GetResult();
+
+        (++) HAL_PKA_Add()
+        (++) HAL_PKA_Sub()
+        (++) HAL_PKA_Cmp()
+        (++) HAL_PKA_Mul()
+        (++) HAL_PKA_ModAdd()
+        (++) HAL_PKA_ModSub()
+        (++) HAL_PKA_ModInv()
+        (++) HAL_PKA_ModRed()
+        (++) HAL_PKA_MontgomeryMul()
+        (++) HAL_PKA_Arithmetic_GetResult(P);
+
+        (++) HAL_PKA_MontgomeryParam()
+        (++) HAL_PKA_MontgomeryParam_GetResult();
+
+    (#) No-Blocking mode functions with Interrupt are :
+
+        (++) HAL_PKA_ModExp_IT();
+        (++) HAL_PKA_ModExpFastMode_IT();
+        (++) HAL_PKA_ModExpProtectMode_IT()
+        (++) HAL_PKA_ModExp_GetResult();
+
+        (++) HAL_PKA_ECDSASign_IT();
+        (++) HAL_PKA_ECDSASign_GetResult();
+
+        (++) HAL_PKA_ECDSAVerif_IT();
+        (++) HAL_PKA_ECDSAVerif_IsValidSignature();
+
+        (++) HAL_PKA_RSACRTExp_IT();
+        (++) HAL_PKA_RSACRTExp_GetResult();
+
+        (++) HAL_PKA_PointCheck_IT();
+        (++) HAL_PKA_PointCheck_IsOnCurve();
+
+        (++) HAL_PKA_ECCMul_IT();
+        (++) HAL_PKA_ECCMulFastMode_IT();
+        (++) HAL_PKA_ECCMul_GetResult();
+
+        (++) HAL_PKA_ECCMulEx_IT();
+        (++) HAL_PKA_ECCDoubleBaseLadder_IT()
+        (++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
+        (++) HAL_PKA_ECCProjective2Affine_IT()
+        (++) HAL_PKA_ECCProjective2Affine_GetResult();
+        (++) HAL_PKA_ECCCompleteAddition_IT()
+        (++) HAL_PKA_ECCCompleteAddition_GetResult();
+        (++) HAL_PKA_Add_IT();
+        (++) HAL_PKA_Sub_IT();
+        (++) HAL_PKA_Cmp_IT();
+        (++) HAL_PKA_Mul_IT();
+        (++) HAL_PKA_ModAdd_IT();
+        (++) HAL_PKA_ModSub_IT();
+        (++) HAL_PKA_ModInv_IT();
+        (++) HAL_PKA_ModRed_IT();
+        (++) HAL_PKA_MontgomeryMul_IT();
+        (++) HAL_PKA_Arithmetic_GetResult();
+
+        (++) HAL_PKA_MontgomeryParam_IT();
+        (++) HAL_PKA_MontgomeryParam_GetResult();
+
+        (++) HAL_PKA_Abort();
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Modular exponentiation in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModExp_Set(hpka, in);
+
+  opsize = in->OpSize;
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
+}
+
+/**
+  * @brief  Modular exponentiation in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModExp_Set(hpka, in);
+
+  opsize = in->OpSize;
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
+}
+
+/**
+  * @brief  Modular exponentiation in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModExpFastMode_Set(hpka, in);
+
+  opsize = in->OpSize;
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
+}
+
+/**
+  * @brief  Modular exponentiation in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModExpFastMode_Set(hpka, in);
+
+  opsize = in->OpSize;
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
+}
+
+/**
+  * @brief  Modular exponentiation (protected) in blocking mode.
+  *         Useful when a secret information is involved (RSA decryption)
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in,
+                                            uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModExpProtectMode_Set(hpka, in);
+
+  opsize = in->OpSize;
+
+  return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout);
+}
+
+/**
+  * @brief  Modular exponentiation (protected) in non-blocking mode with Interrupt.
+  *         Useful when a secret information is involved (RSA decryption)
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModExpProtectMode_Set(hpka, in);
+
+  opsize = in->OpSize;
+
+  return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT);
+}
+
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  pRes Output buffer
+  * @retval HAL status
+  */
+void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
+{
+  uint32_t size;
+
+  /* Get output result size */
+  size = opsize;
+
+  /* Move the result to appropriate location (indicated in out parameter) */
+  PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size);
+}
+
+/**
+  * @brief  Sign a message using elliptic curves over prime fields in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECDSASign_Set(hpka, in);
+
+  primeordersize = in->primeOrderSize;
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
+}
+
+/**
+  * @brief  Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECDSASign_Set(hpka, in);
+
+  primeordersize = in->primeOrderSize;
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
+}
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  out Output information
+  * @param  outExt Additional Output information (facultative)
+  */
+void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out,
+                                 PKA_ECDSASignOutExtParamTypeDef *outExt)
+{
+  uint32_t size;
+
+  /* Get output result size */
+  size = primeordersize;
+
+
+  if (out != NULL)
+  {
+    PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size);
+    PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size);
+  }
+
+  /* If user requires the additional information */
+  if (outExt != NULL)
+  {
+    /* Move the result to appropriate location (indicated in outExt parameter) */
+    PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size);
+    PKA_Memcpy_u32_to_u8(outExt->ptY, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y], size);
+  }
+}
+
+/**
+  * @brief  Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECDSAVerif_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_ECDSA_VERIFICATION, Timeout);
+}
+
+/**
+  * @brief  Verify the validity of a signature using elliptic curves
+  *         over prime fields in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECDSAVerif_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_ECDSA_VERIFICATION);
+}
+
+/**
+  * @brief  Return the result of the ECDSA verification operation.
+  * @param  hpka PKA handle
+  * @retval 1 if signature is verified, 0 in other case
+  */
+uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka)
+{
+  return (hpka->Instance->RAM[PKA_ECDSA_VERIF_OUT_RESULT] == 0xD60DU) ? 1UL : 0UL;
+}
+
+/**
+  * @brief  RSA CRT exponentiation in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_RSACRTExp_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_RSA_CRT_EXP, Timeout);
+}
+
+/**
+  * @brief  RSA CRT exponentiation in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_RSACRTExp_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_RSA_CRT_EXP);
+}
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  pRes Pointer to memory location to receive the result of the operation
+  * @retval HAL status
+  */
+void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
+{
+  uint32_t size;
+
+  /* Move the result to appropriate location (indicated in out parameter) */
+  size = (hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] + 7UL) / 8UL;
+
+  PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_RSA_CRT_EXP_OUT_RESULT], size);
+}
+
+/**
+  * @brief  Point on elliptic curve check in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_PointCheck_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout);
+}
+
+/**
+  * @brief  Point on elliptic curve check in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_PointCheck_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK);
+}
+
+/**
+  * @brief  Return the result of the point check operation.
+  * @param  hpka PKA handle
+  * @retval 1 if point is on curve, 0 in other case
+  */
+uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka)
+{
+#define PKA_POINT_IS_ON_CURVE 0xD60DUL
+  /* Invert the value of the PKA RAM containing the result of the operation */
+  return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL;
+}
+
+/**
+  * @brief  ECC scalar multiplication in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCMul_Set(hpka, in);
+
+  modulussize = in->modulusSize;
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
+}
+
+/**
+  * @brief  ECC scalar multiplication in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCMul_Set(hpka, in);
+
+  modulussize = in->modulusSize;
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
+}
+/**
+  * @brief  ECC scalar multiplication extended in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCMulEx_Set(hpka, in);
+
+  modulussize = in->modulusSize;
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
+}
+
+/**
+  * @brief  ECC scalar multiplication extended in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCMulEx_Set(hpka, in);
+
+  modulussize = in->modulusSize;
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
+}
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  out Output information
+  * @retval HAL status
+  */
+void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out)
+{
+  uint32_t size;
+
+  /* Get output result size */
+  size = modulussize;
+
+  /* If a destination buffer is provided */
+  if (out != NULL)
+  {
+    /* Move the result to appropriate location (indicated in out parameter) */
+    PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], size);
+    PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], size);
+  }
+}
+
+/**
+  * @brief  Arithmetic addition in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_ARITHMETIC_ADD, Timeout);
+}
+
+/**
+  * @brief  Arithmetic addition in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_ADD);
+}
+
+/**
+  * @brief  Arithmetic subtraction in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_ARITHMETIC_SUB, Timeout);
+}
+
+/**
+  * @brief  Arithmetic subtraction in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_SUB);
+}
+
+/**
+  * @brief  Arithmetic multiplication in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_ARITHMETIC_MUL, Timeout);
+}
+
+/**
+  * @brief  Arithmetic multiplication in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_MUL);
+}
+
+/**
+  * @brief  Comparison in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_COMPARISON, Timeout);
+}
+
+/**
+  * @brief  Comparison in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_COMPARISON);
+}
+
+/**
+  * @brief  Modular addition in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MODULAR_ADD, Timeout);
+}
+
+/**
+  * @brief  Modular addition in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MODULAR_ADD);
+}
+
+/**
+  * @brief  Modular inversion in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModInv_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MODULAR_INV, Timeout);
+}
+
+/**
+  * @brief  Modular inversion in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModInv_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MODULAR_INV);
+}
+
+/**
+  * @brief  Modular subtraction in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MODULAR_SUB, Timeout);
+}
+
+/**
+  * @brief  Modular subtraction in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MODULAR_SUB);
+}
+
+/**
+  * @brief  Modular reduction in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModRed_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MODULAR_RED, Timeout);
+}
+
+/**
+  * @brief  Modular reduction in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ModRed_Set(hpka, in);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MODULAR_RED);
+}
+
+/**
+  * @brief  Montgomery multiplication in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MONTGOMERY_MUL, Timeout);
+}
+
+/**
+  * @brief  Montgomery multiplication in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_MUL);
+}
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  pRes Pointer to memory location to receive the result of the operation
+  */
+void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
+{
+  uint32_t mode = (hpka->Instance->CR & PKA_CR_MODE_Msk) >> PKA_CR_MODE_Pos;
+  uint32_t size = 0;
+
+  /* Move the result to appropriate location (indicated in pRes parameter) */
+  switch (mode)
+  {
+    case PKA_MODE_MONTGOMERY_PARAM:
+    case PKA_MODE_ARITHMETIC_SUB:
+    case PKA_MODE_MODULAR_ADD:
+    case PKA_MODE_MODULAR_RED:
+    case PKA_MODE_MODULAR_INV:
+    case PKA_MODE_MONTGOMERY_MUL:
+      size = hpka->Instance->RAM[2] / 32UL;
+      break;
+    case PKA_MODE_ARITHMETIC_ADD:
+    case PKA_MODE_MODULAR_SUB:
+      size = hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] / 32UL;
+
+      /* Manage the overflow of the addition */
+      if (hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT + size] != 0UL)
+      {
+        size += 1UL;
+      }
+
+      break;
+    case PKA_MODE_COMPARISON:
+      size = 1;
+      break;
+    case PKA_MODE_ARITHMETIC_MUL:
+      size = hpka->Instance->RAM[PKA_ARITHMETIC_MUL_NB_BITS] / 32UL * 2UL;
+      break;
+    default:
+      break;
+  }
+
+  if (pRes != NULL)
+  {
+    switch (mode)
+    {
+      case PKA_MODE_ARITHMETIC_SUB:
+      case PKA_MODE_MODULAR_ADD:
+      case PKA_MODE_MODULAR_RED:
+      case PKA_MODE_MODULAR_INV:
+      case PKA_MODE_MODULAR_SUB:
+      case PKA_MODE_MONTGOMERY_MUL:
+      case PKA_MODE_ARITHMETIC_ADD:
+      case PKA_MODE_COMPARISON:
+      case PKA_MODE_ARITHMETIC_MUL:
+        PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT], size);
+        break;
+      default:
+        break;
+    }
+  }
+}
+
+/**
+  * @brief  Montgomery parameter computation in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
+
+  /* Start the operation */
+  return PKA_Process(hpka, PKA_MODE_MONTGOMERY_PARAM, Timeout);
+}
+
+/**
+  * @brief  Montgomery parameter computation in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
+
+  /* Start the operation */
+  return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM);
+}
+
+/**
+  * @brief  ECC double base ladder in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in,
+                                              uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCDoubleBaseLadder_Set(hpka, in);
+
+  return PKA_Process(hpka, PKA_MODE_DOUBLE_BASE_LADDER, Timeout);
+}
+
+/**
+  * @brief  ECC double base ladder in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCDoubleBaseLadder_Set(hpka, in);
+
+  return PKA_Process_IT(hpka, PKA_MODE_DOUBLE_BASE_LADDER);
+}
+
+/**
+  * @brief  ECC projective to affine in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in,
+                                               uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCProjective2Affine_Set(hpka, in);
+
+  return PKA_Process(hpka, PKA_MODE_ECC_PROJECTIVE_AFF, Timeout);
+}
+
+/**
+  * @brief  ECC projective to affine in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCProjective2Affine_Set(hpka, in);
+
+  return PKA_Process_IT(hpka, PKA_MODE_ECC_PROJECTIVE_AFF);
+}
+
+/**
+  * @brief  ECC complete addition in blocking mode.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in,
+                                              uint32_t Timeout)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCCompleteAddition_Set(hpka, in);
+
+  return PKA_Process(hpka, PKA_MODE_ECC_COMPLETE_ADD, Timeout);
+}
+
+/**
+  * @brief  ECC complete addition in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in)
+{
+  /* Set input parameter in PKA RAM */
+  PKA_ECCCompleteAddition_Set(hpka, in);
+
+  return PKA_Process_IT(hpka, PKA_MODE_ECC_COMPLETE_ADD);
+}
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  pRes pointer to buffer where the result will be copied
+  * @retval HAL status
+  */
+void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
+{
+  uint32_t size;
+
+  /* Retrieve the size of the buffer from the PKA RAM */
+  size = (hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] + 31UL) / 32UL;
+
+  /* Move the result to appropriate location (indicated in out parameter) */
+  PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_OUT_PARAMETER], size);
+}
+
+/**
+  * @brief  Abort any ongoing operation.
+  * @param  hpka PKA handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka)
+{
+  HAL_StatusTypeDef err = HAL_OK;
+
+  /* Clear EN bit */
+  /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
+  CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
+  SET_BIT(hpka->Instance->CR, PKA_CR_EN);
+
+  /* Reset any pending flag */
+  SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+  /* Reset the error code */
+  hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+  /* Reset the state */
+  hpka->State = HAL_PKA_STATE_READY;
+
+  return err;
+}
+
+/**
+  * @brief  Reset the PKA RAM.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka)
+{
+  uint32_t index;
+
+  /* For each element in the PKA RAM */
+  for (index = 0; index < PKA_RAM_SIZE; index++)
+  {
+    /* Clear the content */
+    hpka->Instance->RAM[index] = 0UL;
+  }
+}
+
+/**
+  * @brief  This function handles PKA event interrupt request.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
+{
+  uint32_t mode = PKA_GetMode(hpka);
+  uint32_t itsource = READ_REG(hpka->Instance->CR);
+  uint32_t flag  =   READ_REG(hpka->Instance->SR);
+
+  /* Address error interrupt occurred */
+  if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR))
+  {
+    hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR;
+
+    /* Clear ADDRERR flag */
+    __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_ADDRERR);
+  }
+
+  /* RAM access error interrupt occurred */
+  if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR))
+  {
+    hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR;
+
+    /* Clear RAMERR flag */
+    __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_RAMERR);
+  }
+
+  /* OPERATION access error interrupt occurred */
+  if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR))
+  {
+    hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+
+    /* Clear OPERR flag */
+    __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_OPERR);
+  }
+
+  /* Check the operation success in case of ECDSA signature */
+  switch (mode)
+  {
+    case PKA_MODE_ECDSA_SIGNATURE :
+      /* If error output result is different from no error, operation need to be repeated */
+      if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != PKA_NO_ERROR)
+      {
+        hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+      }
+      break;
+
+    case PKA_MODE_DOUBLE_BASE_LADDER :
+      /* If error output result is different from no error, operation need to be repeated */
+      if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR)
+      {
+        hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+      }
+      break;
+
+    case PKA_MODE_ECC_PROJECTIVE_AFF :
+      /* If error output result is different from no error, operation need to be repeated */
+      if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR)
+      {
+        hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+      }
+      break;
+
+    case PKA_MODE_ECC_MUL :
+      /* If error output result is different from no error, operation need to be repeated */
+      if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR)
+      {
+        hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+      }
+      break;
+
+    case PKA_MODE_MODULAR_EXP_PROTECT :
+      /* If error output result is different from no error, operation need to be repeated */
+      if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR)
+      {
+        hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
+      }
+      break;
+    default :
+      break;
+  }
+  /* Trigger the error callback if an error is present */
+  if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
+  {
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+    hpka->ErrorCallback(hpka);
+#else
+    HAL_PKA_ErrorCallback(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+  }
+
+  /* End Of Operation interrupt occurred */
+  if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND))
+  {
+    /* Clear PROCEND flag */
+    __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND);
+
+    /* Set the state to ready */
+    hpka->State = HAL_PKA_STATE_READY;
+
+#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
+    hpka->OperationCpltCallback(hpka);
+#else
+    HAL_PKA_OperationCpltCallback(hpka);
+#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Process completed callback.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+__weak void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpka);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PKA_OperationCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hpka PKA handle
+  * @retval None
+  */
+__weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpka);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PKA_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions
+  * @brief    Peripheral State and Error functions
+  *
+  @verbatim
+ ===============================================================================
+            ##### Peripheral State and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PKA handle state.
+  * @param  hpka PKA handle
+  * @retval HAL status
+  */
+HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka)
+{
+  /* Return PKA handle state */
+  return hpka->State;
+}
+
+/**
+  * @brief  Return the PKA error code.
+  * @param  hpka PKA handle
+  * @retval PKA error code
+  */
+uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka)
+{
+  /* Return PKA handle error code */
+  return hpka->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup PKA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Get PKA operating mode.
+  * @param  hpka PKA handle
+  * @retval Return the current mode
+  */
+uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka)
+{
+  /* return the shifted PKA_CR_MODE value */
+  return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
+}
+
+/**
+  * @brief  Wait for operation completion or timeout.
+  * @param  hpka PKA handle
+  * @param  Timeout Timeout duration in millisecond.
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Wait for the end of operation or timeout */
+  while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return a hal error code based on PKA error flags.
+  * @param  hpka PKA handle
+  * @param  mode PKA operating mode
+  * @retval error code
+  */
+uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode)
+{
+  uint32_t err = HAL_PKA_ERROR_NONE;
+
+  /* Check RAMERR error */
+  if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR) == SET)
+  {
+    err |= HAL_PKA_ERROR_RAMERR;
+  }
+
+  /* Check ADDRERR error */
+  if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR) == SET)
+  {
+    err |= HAL_PKA_ERROR_ADDRERR;
+  }
+
+  /* Check OPEERR error */
+  if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR) == SET)
+  {
+    err |= HAL_PKA_ERROR_OPERATION;
+  }
+
+  /* Check the operation success in case of ECDSA signature */
+  if (mode == PKA_MODE_ECDSA_SIGNATURE)
+  {
+#define EDCSA_SIGN_NOERROR PKA_NO_ERROR
+    /* If error output result is different from no error, ecsa sign operation need to be repeated */
+    if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != EDCSA_SIGN_NOERROR)
+    {
+      err |= HAL_PKA_ERROR_OPERATION;
+    }
+  }
+
+  /* Check the operation success in case of ECC double base ladder*/
+  if (mode == PKA_MODE_DOUBLE_BASE_LADDER)
+  {
+    /* If error output result is different from no error, PKA operation need to be repeated */
+    if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR)
+    {
+      err |= HAL_PKA_ERROR_OPERATION;
+    }
+  }
+
+  /* Check the operation success in case of ECC projective to affine*/
+  if (mode == PKA_MODE_ECC_PROJECTIVE_AFF)
+  {
+    /* If error output result is different from no error, PKA operation need to be repeated */
+    if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR)
+    {
+      err |= HAL_PKA_ERROR_OPERATION;
+    }
+  }
+
+  /* Check the operation success in case of ECC Fp scalar multiplication*/
+  if (mode == PKA_MODE_ECC_MUL)
+  {
+    /* If error output result is different from no error, PKA operation need to be repeated */
+    if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR)
+    {
+      err |= HAL_PKA_ERROR_OPERATION;
+    }
+  }
+
+  /* Check the operation success in case of protected modular exponentiation*/
+  if (mode == PKA_MODE_MODULAR_EXP_PROTECT)
+  {
+    /* If error output result is different from no error, PKA operation need to be repeated */
+    if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR)
+    {
+      err |= HAL_PKA_ERROR_OPERATION;
+    }
+  }
+
+  return err;
+}
+
+/**
+  * @brief  Get number of bits inside an array of u8.
+  * @param  byteNumber Number of u8 inside the array
+  */
+uint32_t PKA_GetBitSize_u8(uint32_t byteNumber)
+{
+  /* Convert from number of uint8_t in an array to the associated number of bits in this array */
+  return byteNumber * 8UL;
+}
+
+/**
+  * @brief  Get optimal number of bits inside an array of u8.
+  * @param  byteNumber Number of u8 inside the array
+  * @param  msb Most significant uint8_t of the array
+  */
+uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb)
+{
+  uint32_t position;
+
+  position = 32UL - __CLZ(msb);
+
+  return (((byteNumber - 1UL) * 8UL) + position);
+}
+
+/**
+  * @brief  Get number of bits inside an array of u32.
+  * @param  wordNumber Number of u32 inside the array
+  */
+uint32_t PKA_GetBitSize_u32(uint32_t wordNumber)
+{
+  /* Convert from number of uint32_t in an array to the associated number of bits in this array */
+  return wordNumber * 32UL;
+}
+
+/**
+  * @brief  Get number of uint8_t element in an array of bitSize bits.
+  * @param  bitSize Number of bits in an array
+  */
+uint32_t PKA_GetArraySize_u8(uint32_t bitSize)
+{
+  /* Manage the non aligned on uint8_t bitsize: */
+  /*   512 bits requires 64 uint8_t             */
+  /*   521 bits requires 66 uint8_t             */
+  return ((bitSize + 7UL) / 8UL);
+}
+
+/**
+  * @brief  Copy uint32_t array to uint8_t array to fit PKA number representation.
+  * @param  dst Pointer to destination
+  * @param  src Pointer to source
+  * @param  n Number of uint8_t to copy
+  * @retval dst
+  */
+void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n)
+{
+  if (dst != NULL)
+  {
+    if (src != NULL)
+    {
+      uint32_t index_uint32_t = 0UL; /* This index is used outside of the loop */
+
+      for (; index_uint32_t < (n / 4UL); index_uint32_t++)
+      {
+        /* Avoid casting from uint8_t* to uint32_t* by copying 4 uint8_t in a row */
+        /* Apply __REV equivalent */
+        uint32_t index_uint8_t = n - 4UL - (index_uint32_t * 4UL);
+        dst[index_uint8_t + 3UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+        dst[index_uint8_t + 2UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+        dst[index_uint8_t + 1UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
+        dst[index_uint8_t + 0UL] = (uint8_t)((src[index_uint32_t] & 0xFF000000U) >> 24UL);
+      }
+
+      /* Manage the buffers not aligned on uint32_t */
+      if ((n % 4UL) == 1UL)
+      {
+        dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+      }
+      else if ((n % 4UL) == 2UL)
+      {
+        dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+        dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+      }
+      else if ((n % 4UL) == 3UL)
+      {
+        dst[2UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
+        dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
+        dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
+      }
+      else
+      {
+        /* The last element is already handle in the loop */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Copy uint8_t array to uint32_t array to fit PKA number representation.
+  * @param  dst Pointer to destination
+  * @param  src Pointer to source
+  * @param  n Number of uint8_t to copy (must be multiple of 4)
+  * @retval dst
+  */
+void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n)
+{
+  if (dst != NULL)
+  {
+    if (src != NULL)
+    {
+      uint32_t index = 0UL; /* This index is used outside of the loop */
+
+      for (; index < (n / 4UL); index++)
+      {
+        /* Apply the equivalent of __REV from uint8_t to uint32_t */
+        dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
+                     | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
+                     | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL) \
+                     | ((uint32_t)src[(n - (index * 4UL) - 4UL)] << 24UL);
+      }
+
+      /* Manage the buffers not aligned on uint32_t */
+      if ((n % 4UL) == 1UL)
+      {
+        dst[index] = (uint32_t)src[(n - (index * 4UL) - 1UL)];
+      }
+      else if ((n % 4UL) == 2UL)
+      {
+        dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
+                     | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL);
+      }
+      else if ((n % 4UL) == 3UL)
+      {
+        dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
+                     | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
+                     | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL);
+      }
+      else
+      {
+        /* The last element is already handle in the loop */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Copy uint32_t array to uint32_t array.
+  * @param  dst Pointer to destination
+  * @param  src Pointer to source
+  * @param  n Number of u32 to be handled
+  * @retval dst
+  */
+void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n)
+{
+  /* If a destination buffer is provided */
+  if (dst != NULL)
+  {
+    /* If a source buffer is provided */
+    if (src != NULL)
+    {
+      /* For each element in the array */
+      for (uint32_t index = 0UL; index < n; index++)
+      {
+        /* Copy the content */
+        dst[index] = src[index];
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Generic function to start a PKA operation in blocking mode.
+  * @param  hpka PKA handle
+  * @param  mode PKA operation
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout)
+{
+  HAL_StatusTypeDef err = HAL_OK;
+  uint32_t tickstart;
+
+  if (hpka->State == HAL_PKA_STATE_READY)
+  {
+    /* Set the state to busy */
+    hpka->State = HAL_PKA_STATE_BUSY;
+
+    /* Clear any pending error */
+    hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    /* Set the mode and deactivate the interrupts */
+    MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+               mode << PKA_CR_MODE_Pos);
+
+    /* Start the computation */
+    hpka->Instance->CR |= PKA_CR_START;
+
+    /* Wait for the end of operation or timeout */
+    if (PKA_PollEndOfOperation(hpka, Timeout, tickstart) != HAL_OK)
+    {
+      /* Abort any ongoing operation */
+      CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
+
+      hpka->ErrorCode |= HAL_PKA_ERROR_TIMEOUT;
+
+      /* Make ready for the next operation */
+      SET_BIT(hpka->Instance->CR, PKA_CR_EN);
+    }
+
+    /* Check error */
+    hpka->ErrorCode |= PKA_CheckError(hpka, mode);
+
+    /* Clear all flags */
+    hpka->Instance->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
+
+    /* Set the state to ready */
+    hpka->State = HAL_PKA_STATE_READY;
+
+    /* Manage the result based on encountered errors */
+    if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
+    {
+      err = HAL_ERROR;
+    }
+  }
+  else
+  {
+    err = HAL_ERROR;
+  }
+  return err;
+}
+
+/**
+  * @brief  Generic function to start a PKA operation in non-blocking mode with Interrupt.
+  * @param  hpka PKA handle
+  * @param  mode PKA operation
+  * @retval HAL status
+  */
+HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode)
+{
+  HAL_StatusTypeDef err = HAL_OK;
+
+  if (hpka->State == HAL_PKA_STATE_READY)
+  {
+    /* Set the state to busy */
+    hpka->State = HAL_PKA_STATE_BUSY;
+
+    /* Clear any pending error */
+    hpka->ErrorCode = HAL_PKA_ERROR_NONE;
+
+    /* Set the mode and activate interrupts */
+    MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
+               (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE);
+
+    /* Start the computation */
+    hpka->Instance->CR |= PKA_CR_START;
+  }
+  else
+  {
+    err = HAL_ERROR;
+  }
+  return err;
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
+{
+  /* Get the number of bit per operand */
+  hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
+
+  /* Get the number of bit of the exponent */
+  hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
+
+  /* Move the input parameters pOp1 to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL));
+
+  /* Move the exponent to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL));
+
+  /* Move the modulus to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
+{
+  /* Get the number of bit per operand */
+  hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
+
+  /* Get the number of bit of the exponent */
+  hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
+
+  /* Move the input parameters pOp1 to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
+
+  /* Move the exponent to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
+
+  /* Move the modulus to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
+
+  /* Move the Montgomery parameter to PKA RAM */
+  PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
+                        in->OpSize / 4UL);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in)
+{
+  /* Get the number of bit per operand */
+  hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
+
+  /* Get the number of bit of the exponent */
+  hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
+
+  /* Move the input parameters pOp1 to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (in->OpSize / 4UL));
+
+  /* Move the exponent to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], in->pExp, in->expSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (in->expSize / 4UL));
+
+  /* Move the modulus to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], in->pMod, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + (in->OpSize / 4UL));
+
+  /* Move Phi value to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], in->pPhi, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + (in->OpSize / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  * @note   If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash
+  *         for example)the hash value should be written at the end of the buffer with zeros padding at beginning.
+  */
+void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
+{
+  /* Get the prime order n length */
+  hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
+
+  /* Get the modulus p length */
+  hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+  /* Get the coefficient a sign */
+  hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSign;
+
+  /* Move the input parameters coefficient |a| to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters coefficient B to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], in->coefB, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters integer k to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL));
+
+  /* Move the input parameters base point G coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters base point G coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters hash of message z to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
+
+  /* Move the input parameters private key d to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL));
+
+  /* Move the input parameters prime order n to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
+{
+  /* Get the prime order n length */
+  hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
+
+  /* Get the modulus p length */
+  hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+  /* Get the coefficient a sign */
+  hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = in->coefSign;
+
+  /* Move the input parameters coefficient |a| to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters base point G coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters base point G coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX,
+                       in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY,
+                       in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters signature part r to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL));
+
+  /* Move the input parameters signature part s to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL));
+
+  /* Move the input parameters hash of message z to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
+
+  /* Move the input parameters curve prime order n to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
+{
+  /* Get the operand length M */
+  hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->size);
+
+  /* Move the input parameters operand dP to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL));
+
+  /* Move the input parameters operand dQ to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL));
+
+  /* Move the input parameters operand qinv to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL));
+
+  /* Move the input parameters prime p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL));
+
+  /* Move the input parameters prime q to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL));
+
+  /* Move the input parameters operand A to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
+{
+  /* Get the modulus length */
+  hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+  /* Get the coefficient a sign */
+  hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF_SIGN] = in->coefSign;
+
+  /* Move the input parameters coefficient |a| to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters coefficient b to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters Point P coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters Point P coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters montgomery param R2 modulus N to PKA RAM */
+  PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
+                        (in->modulusSize / 4UL));
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
+{
+  /* Get the prime order n length */
+  hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->scalarMulSize, *(in->primeOrder));
+
+  /* Get the modulus length */
+  hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+  /* Get the coefficient a sign */
+  hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign;
+
+  /* Move the input parameters coefficient |a| to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters coefficient b to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters scalar multiplier k to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
+
+  /* Move the input parameters Point P coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters Point P coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters curve prime order N to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL));
+}
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in)
+{
+  /* Get the prime order n length */
+  hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
+
+  /* Get the modulus length */
+  hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
+
+  /* Get the coefficient a sign */
+  hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign;
+
+  /* Move the input parameters coefficient |a| to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters coefficient b to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters scalar multiplier k to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
+
+  /* Move the input parameters Point P coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters Point P coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
+
+  /* Move the input parameters curve prime order N to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
+{
+  /* Get the number of bit per operand */
+  hpka->Instance->RAM[PKA_MODULAR_INV_NB_BITS] = PKA_GetBitSize_u32(in->size);
+
+  /* Move the input parameters operand A to PKA RAM */
+  PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP1 + in->size);
+
+  /* Move the input parameters modulus value n to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP2_MOD + in->size);
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
+{
+  /* Get the number of bit per operand */
+  hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OP_LENGTH] = PKA_GetBitSize_u32(in->OpSize);
+
+  /* Get the number of bit per modulus */
+  hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MOD_LENGTH] = PKA_GetBitSize_u8(in->modSize);
+
+  /* Move the input parameters operand A to PKA RAM */
+  PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize);
+
+  /* Move the input parameters modulus value n to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL));
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  size Size of the operand
+  * @param  pOp1 Generic pointer to input data
+  */
+void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1)
+{
+  uint32_t bytetoskip = 0UL;
+  uint32_t newSize;
+
+  if (pOp1 != NULL)
+  {
+    /* Count the number of zero bytes */
+    while ((bytetoskip < size) && (pOp1[bytetoskip] == 0UL))
+    {
+      bytetoskip++;
+    }
+
+    /* Get new size after skipping zero bytes */
+    newSize = size - bytetoskip;
+
+    /* Get the number of bit per operand */
+    hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(newSize, pOp1[bytetoskip]);
+
+    /* Move the input parameters pOp1 to PKA RAM */
+    PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size);
+    __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL));
+  }
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in)
+{
+  /* Get the prime order n length */
+  hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS] = PKA_GetBitSize_u8(in->primeOrderSize);
+
+  /* Get the modulus p length */
+  hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
+
+  /* Get the coefficient a sign */
+  hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign;
+
+  /* Move the input parameters coefficient |a| to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF], in->coefA, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF + (in->modulusSize / 4UL));
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_P], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_MOD_P + (in->modulusSize / 4UL));
+
+  /* Move the input parameters integer k to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER], in->integerK, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER + (in->modulusSize / 4UL));
+
+  /* Move the input parameters integer m to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER], in->integerM, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER + (in->modulusSize / 4UL));
+
+  /* Move the input parameters first point coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_X], in->basePointX1, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_X + (in->modulusSize / 4UL));
+
+  /* Move the input parameters first point  coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y], in->basePointY1, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y + (in->modulusSize / 4UL));
+
+  /* Move the input parameters first point  coordinate z to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z], in->basePointZ1, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z + (in->modulusSize / 4UL));
+
+  /* Move the input parameters second point coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_X], in->basePointX2, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_X + (in->modulusSize / 4UL));
+
+  /* Move the input parameters second point  coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y], in->basePointY2, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y + (in->modulusSize / 4UL));
+
+  /* Move the input parameters second point  coordinate z to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z], in->basePointZ2, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z + (in->modulusSize / 4UL));
+}
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  out Output information
+  * @retval HAL status
+  */
+void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out)
+{
+  uint32_t size;
+
+  /* Move the result to appropriate location (indicated in out parameter) */
+  size = hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] / 8UL;
+  if (out != NULL)
+  {
+    PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X], size);
+    PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y], size);
+  }
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in)
+{
+  /* Get the modulus p length */
+  hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_P], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MOD_P + (in->modulusSize / 4UL));
+
+  /* Move the input parameters point coordinate x to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_X], in->basePointX, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_X + (in->modulusSize / 4UL));
+
+  /* Move the input parameters point coordinate y to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y], in->basePointY, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y + (in->modulusSize / 4UL));
+
+  /* Move the input parameters point coordinate z to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z], in->basePointZ, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z + (in->modulusSize / 4UL));
+
+  /* Move the input parameters montgomery parameter R2 modulus n to PKA RAM */
+  PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2], in->pMontgomeryParam,
+                        (in->modulusSize / 4UL));
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 + (in->modulusSize / 4UL));
+}
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  out Output information
+  * @retval HAL status
+  */
+void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out)
+{
+  uint32_t size;
+
+  /* Move the result to appropriate location (indicated in out parameter) */
+  size = hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] / 8UL;
+  if (out != NULL)
+  {
+    PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X], size);
+    PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y], size);
+  }
+}
+
+/**
+  * @brief  Set input parameters.
+  * @param  hpka PKA handle
+  * @param  in Input information
+  */
+void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in)
+{
+  /* Get the modulus p length */
+  hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
+
+  /* Get the coefficient a sign */
+  hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign;
+
+  /* Move the input parameters modulus value p to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_P], in->modulus, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_MOD_P + (in->modulusSize / 4UL));
+
+  /* Move the input parameters coefA value to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_A_COEFF], in->coefA, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_A_COEFF + (in->modulusSize / 4UL));
+
+  /* Move the input parameters first point x value  to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_X], in->basePointX1, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_X + (in->modulusSize / 4UL));
+
+  /* Move the input parameters first point y value  to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Y], in->basePointY1, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Y + (in->modulusSize / 4UL));
+
+  /* Move the input parameters first point z value  to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Z], in->basePointZ1, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Z + (in->modulusSize / 4UL));
+
+  /* Move the input parameters second point x value  to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_X], in->basePointX2, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_X + (in->modulusSize / 4UL));
+
+  /* Move the input parameters second point y value  to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Y], in->basePointY2, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Y + (in->modulusSize / 4UL));
+
+  /* Move the input parameters second point z value  to PKA RAM */
+  PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Z], in->basePointZ2, in->modulusSize);
+  __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Z + (in->modulusSize / 4UL));
+}
+
+/**
+  * @brief  Retrieve operation result.
+  * @param  hpka PKA handle
+  * @param  out Output information
+  * @retval HAL status
+  */
+void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out)
+{
+  uint32_t size;
+
+  /* Move the result to appropriate location (indicated in out parameter) */
+  size = (hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] + 7UL) / 8UL;
+  if (out != NULL)
+  {
+    PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_X], size);
+    PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y], size);
+    PKA_Memcpy_u32_to_u8(out->ptZ, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z], size);
+  }
+}
+/**
+  * @brief  Generic function to set input parameters.
+  * @param  hpka PKA handle
+  * @param  size Size of the operand
+  * @param  pOp1 Generic pointer to input data
+  * @param  pOp2 Generic pointer to input data
+  * @param  pOp3 Generic pointer to input data
+  */
+void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
+                 const uint8_t *pOp3)
+{
+  /* Get the number of bit per operand */
+  hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size);
+
+  if (pOp1 != NULL)
+  {
+    /* Move the input parameters pOp1 to PKA RAM */
+    PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size);
+    __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size);
+  }
+
+  if (pOp2 != NULL)
+  {
+    /* Move the input parameters pOp2 to PKA RAM */
+    PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size);
+    __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size);
+  }
+
+  if (pOp3 != NULL)
+  {
+    /* Move the input parameters pOp3 to PKA RAM */
+    PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL);
+    __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size);
+  }
+}
+/**
+  * @brief  Handle PKA init Timeout.
+  * @param  hpka      PKA handle.
+  * @param  Flag      Specifies the PKA flag to check
+  * @param  Status    Flag status (SET or RESET)
+  * @param  Tickstart Tick start value
+  * @param  Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status,
+                                             uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while (__HAL_PKA_GET_FLAG(hpka, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Set the state to ready */
+        hpka->State = HAL_PKA_STATE_READY;
+
+        /* Set the error code to timeout error */
+        hpka->ErrorCode = HAL_PKA_ERROR_TIMEOUT;
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the size of output result.
+  * @param  hpka           PKA handle
+  * @param  Startindex     Specifies the start index of the result in the PKA RAM
+  * @param  Maxsize        Specifies the possible max size of the result in words
+  * @retval size
+  */
+uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize)
+{
+  uint32_t size;
+  uint32_t current_index = Maxsize - 1UL;
+
+  /* Determinate the last index of the result in the PKA RAM */
+  while ((hpka->Instance->RAM[Startindex + current_index] == 0UL) && (current_index != 0UL))
+  {
+    current_index--;
+  }
+  /* Get the size in bytes */
+  size = (current_index + 1UL) * 4UL;
+
+  return size;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pssi.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pssi.c
new file mode 100644
index 000000000..4f1196ed2
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pssi.c
@@ -0,0 +1,1928 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pssi.c
+  * @author  MCD Application Team
+  * @brief   PSSI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The PSSI HAL driver can be used as follows:
+
+    (#) Declare a PSSI_HandleTypeDef handle structure, for example:
+        PSSI_HandleTypeDef  hpssi;
+
+    (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API:
+        (##) Enable the PSSIx interface clock
+        (##) PSSI pins configuration
+            (+++) Enable the clock for the PSSI GPIOs
+            (+++) Configure PSSI pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the PSSIx interrupt priority
+            (+++) Enable the NVIC PSSI IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare  DMA_HandleTypeDef handles structure for the transmit and receive
+            (+++) Enable the DMAx interface clock
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx and Rx
+            (+++) Associate the initialized DMA handle to the hpssi DMA Tx and Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx and Rx
+
+    (#) Configure the Communication Bus Width,  Control Signals, Input Polarity and Output Polarity
+         in the hpssi Init structure.
+
+    (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
+
+    (#) Configure the PSSI clock as internal or external by calling the @ref HAL_PSSI_ClockConfig().
+
+    (#) For PSSI IO operations, two operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit()
+      (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit an amount of data in non-blocking mode (DMA) using
+          @ref HAL_PSSI_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode (DMA) using
+          @ref HAL_PSSI_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback()
+      (+) Abort a  PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT()
+      (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback()
+
+     *** PSSI HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in PSSI HAL driver.
+
+      (+) @ref HAL_PSSI_ENABLE     : Enable the PSSI peripheral
+      (+) @ref HAL_PSSI_DISABLE    : Disable the PSSI peripheral
+      (+) @ref HAL_PSSI_GET_FLAG   : Check whether the specified PSSI flag is set or not
+      (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag
+      (+) @ref HAL_PSSI_ENABLE_IT  : Enable the specified PSSI interrupt
+      (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt
+
+     *** Callback registration ***
+     =============================================
+     Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback()
+     to register an interrupt callback.
+
+     Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks:
+       (+) TxCpltCallback       : callback for transmission end of transfer.
+       (+) RxCpltCallback       : callback for reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+
+
+     Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default
+     weak function.
+     @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) TxCpltCallback       : callback for transmission end of transfer.
+       (+) RxCpltCallback       : callback for reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+
+
+     By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+     Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit()
+     or @ref HAL_PSSI_Init() function.
+
+
+     [..]
+       (@) You can refer to the PSSI HAL driver header file for more useful macros
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PSSI PSSI
+  * @brief PSSI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+#if defined(PSSI)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PSSI_Private_Define PSSI Private Define
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup PSSI_Private_Functions PSSI Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+#if defined(HAL_DMA_MODULE_ENABLED)
+void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+void PSSI_DMAError(DMA_HandleTypeDef *hdma);
+void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+/* Private functions to handle IT transfer */
+static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
+
+
+/* Private functions for PSSI transfer IRQ handler */
+
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
+                                                       uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PSSI_Exported_Functions PSSI Exported Functions
+  * @{
+  */
+
+/** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the PSSIx peripheral:
+
+      (+) User must implement HAL_PSSI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_PSSI_Init() to configure the selected device with
+          the selected configuration:
+        (++) Data Width
+        (++) Control Signals
+        (++) Input Clock polarity
+        (++) Output Clock polarity
+
+      (+) Call the function HAL_PSSI_DeInit() to restore the default configuration
+          of the selected PSSIx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PSSI according to the specified parameters
+  *         in the PSSI_InitTypeDef and initialize the associated handle.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
+{
+  /* Check the PSSI handle allocation */
+  if (hpssi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
+  assert_param(IS_PSSI_CONTROL_SIGNAL(hpssi->Init.ControlSignal));
+  assert_param(IS_PSSI_BUSWIDTH(hpssi->Init.BusWidth));
+  assert_param(IS_PSSI_CLOCK_POLARITY(hpssi->Init.ClockPolarity));
+  assert_param(IS_PSSI_DE_POLARITY(hpssi->Init.DataEnablePolarity));
+  assert_param(IS_PSSI_RDY_POLARITY(hpssi->Init.ReadyPolarity));
+
+  if (hpssi->State == HAL_PSSI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpssi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    /* Init the PSSI Callback settings */
+    hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+    hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+    hpssi->ErrorCallback        = HAL_PSSI_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hpssi->AbortCpltCallback    = HAL_PSSI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+
+    if (hpssi->MspInitCallback == NULL)
+    {
+      hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hpssi->MspInitCallback(hpssi);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_PSSI_MspInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
+  }
+
+  hpssi->State = HAL_PSSI_STATE_BUSY;
+
+  /* Disable the selected PSSI peripheral */
+  HAL_PSSI_DISABLE(hpssi);
+
+  /*---------------------------- PSSIx CR Configuration ----------------------*/
+  /* Configure PSSIx: Control Signal and Bus Width*/
+
+  MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DERDYCFG | PSSI_CR_EDM | PSSI_CR_DEPOL | PSSI_CR_RDYPOL,
+             hpssi->Init.ControlSignal | hpssi->Init.DataEnablePolarity |
+             hpssi->Init.ReadyPolarity | hpssi->Init.BusWidth);
+
+  hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+  hpssi->State = HAL_PSSI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the PSSI peripheral.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
+{
+  /* Check the PSSI handle allocation */
+  if (hpssi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
+
+  hpssi->State = HAL_PSSI_STATE_BUSY;
+
+  /* Disable the PSSI Peripheral Clock */
+  HAL_PSSI_DISABLE(hpssi);
+
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+  if (hpssi->MspDeInitCallback == NULL)
+  {
+    hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hpssi->MspDeInitCallback(hpssi);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_PSSI_MspDeInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
+
+  hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+  hpssi->State = HAL_PSSI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpssi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the PSSI MSP.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval None
+  */
+__weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpssi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PSSI_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief De-Initialize the PSSI MSP.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval None
+  */
+__weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpssi);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_PSSI_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User PSSI Callback
+  *         To be used instead of the weak predefined callback
+  * @note   The HAL_PSSI_RegisterCallback() may be called before HAL_PSSI_Init() in
+  *         HAL_PSSI_STATE_RESET to register callbacks for HAL_PSSI_MSPINIT_CB_ID
+  *         and HAL_PSSI_MSPDEINIT_CB_ID.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID  Tx Transfer completed callback ID
+  *          @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID  Rx Transfer completed callback ID
+  *          @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
+                                            pPSSI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_PSSI_STATE_READY == hpssi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PSSI_TX_COMPLETE_CB_ID :
+        hpssi->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_PSSI_RX_COMPLETE_CB_ID :
+        hpssi->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_PSSI_ERROR_CB_ID :
+        hpssi->ErrorCallback = pCallback;
+        break;
+
+      case HAL_PSSI_ABORT_CB_ID :
+        hpssi->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_PSSI_MSPINIT_CB_ID :
+        hpssi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PSSI_MSPDEINIT_CB_ID :
+        hpssi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_PSSI_STATE_RESET == hpssi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PSSI_MSPINIT_CB_ID :
+        hpssi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PSSI_MSPDEINIT_CB_ID :
+        hpssi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an PSSI Callback
+  *         PSSI callback is redirected to the weak predefined callback
+  * @note   The HAL_PSSI_UnRegisterCallback() may be called before HAL_PSSI_Init() in
+  *         HAL_PSSI_STATE_RESET to un-register callbacks for HAL_PSSI_MSPINIT_CB_ID
+  *         and HAL_PSSI_MSPDEINIT_CB_ID.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID  Tx Transfer completed callback ID
+  *          @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID  Rx Transfer completed callback ID
+  *          @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_PSSI_STATE_READY == hpssi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PSSI_TX_COMPLETE_CB_ID :
+        hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback;             /* Legacy weak TxCpltCallback     */
+        break;
+
+      case HAL_PSSI_RX_COMPLETE_CB_ID :
+        hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback;             /* Legacy weak RxCpltCallback     */
+        break;
+
+      case HAL_PSSI_ERROR_CB_ID :
+        hpssi->ErrorCallback = HAL_PSSI_ErrorCallback;               /* Legacy weak ErrorCallback      */
+        break;
+
+      case HAL_PSSI_ABORT_CB_ID :
+        hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback  */
+        break;
+
+      case HAL_PSSI_MSPINIT_CB_ID :
+        hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit            */
+        break;
+
+      case HAL_PSSI_MSPDEINIT_CB_ID :
+        hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit          */
+        break;
+
+      default :
+        /* Update the error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_PSSI_STATE_RESET == hpssi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PSSI_MSPINIT_CB_ID :
+        hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit            */
+        break;
+
+      case HAL_PSSI_MSPDEINIT_CB_ID :
+        hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit          */
+        break;
+
+      default :
+        /* Update the error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the PSSI data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using DMA.
+            These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated  the DMA IRQ .
+
+    (#) Blocking mode functions are :
+        (++) HAL_PSSI_Transmit()
+        (++) HAL_PSSI_Receive()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_PSSI_Transmit_DMA()
+        (++) HAL_PSSI_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_PSSI_TxCpltCallback()
+        (++) HAL_PSSI_RxCpltCallback()
+        (++) HAL_PSSI_ErrorCallback()
+        (++) HAL_PSSI_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent (in bytes)
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t  transfer_size = Size;
+
+  if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
+      ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
+      ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
+  {
+    hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  if (hpssi->State == HAL_PSSI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hpssi);
+
+    hpssi->State     = HAL_PSSI_STATE_BUSY;
+    hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+
+    /* Disable the selected PSSI peripheral */
+    HAL_PSSI_DISABLE(hpssi);
+
+    /* Configure transfer parameters */
+    MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+               (PSSI_CR_OUTEN_OUTPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+    /* DMA Disable */
+    hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+    /* Enable the selected PSSI peripheral */
+    HAL_PSSI_ENABLE(hpssi);
+
+    if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
+    {
+      uint8_t *pbuffer = pData;
+      while (transfer_size > 0U)
+      {
+        /* Init tickstart for timeout management*/
+        tickstart = HAL_GetTick();
+        /* Wait until Fifo is ready to transfer one byte flag is set */
+        if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+          hpssi->State = HAL_PSSI_STATE_READY;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+          return HAL_ERROR;
+        }
+        /* Write data to DR */
+        *(__IO uint8_t *)(&hpssi->Instance->DR) = *(uint8_t *)pbuffer;
+
+        /* Increment Buffer pointer */
+        pbuffer++;
+
+        transfer_size--;
+      }
+    }
+    else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
+    {
+      uint16_t *pbuffer = (uint16_t *)pData;
+      __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
+
+      while (transfer_size > 0U)
+      {
+        /* Init tickstart for timeout management*/
+        tickstart = HAL_GetTick();
+        /* Wait until Fifo is ready to transfer four bytes flag is set */
+        if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+          hpssi->State = HAL_PSSI_STATE_READY;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+          return HAL_ERROR;
+        }
+        /* Write data to DR */
+        *dr = *pbuffer;
+
+        /* Increment Buffer pointer */
+        pbuffer++;
+        transfer_size -= 2U;
+      }
+    }
+    else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
+    {
+      uint32_t *pbuffer = (uint32_t *)pData;
+      while (transfer_size > 0U)
+      {
+        /* Init tickstart for timeout management*/
+        tickstart = HAL_GetTick();
+        /* Wait until Fifo is ready to transfer four bytes flag is set */
+        if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+          hpssi->State = HAL_PSSI_STATE_READY;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+          return HAL_ERROR;
+        }
+        /* Write data to DR */
+        *(__IO uint32_t *)(&hpssi->Instance->DR) = *pbuffer;
+
+        /* Increment Buffer pointer */
+        pbuffer++;
+        transfer_size -= 4U;
+      }
+    }
+    else
+    {
+      hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+      hpssi->State = HAL_PSSI_STATE_READY;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hpssi);
+      return HAL_ERROR;
+    }
+
+    /* Check Errors Flags */
+    if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
+    {
+      HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
+      HAL_PSSI_DISABLE(hpssi);
+      hpssi->ErrorCode = HAL_PSSI_ERROR_UNDER_RUN;
+      hpssi->State = HAL_PSSI_STATE_READY;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hpssi);
+      return HAL_ERROR;
+    }
+
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in blocking mode.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received (in bytes)
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t  transfer_size = Size;
+
+  if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
+      ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
+      ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
+  {
+    hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+
+  if (hpssi->State == HAL_PSSI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hpssi);
+
+    hpssi->State     = HAL_PSSI_STATE_BUSY;
+    hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
+
+    /* Disable the selected PSSI peripheral */
+    HAL_PSSI_DISABLE(hpssi);
+    /* Configure transfer parameters */
+    MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+               (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL)));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+    /* DMA Disable */
+    hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+    /* Enable the selected PSSI peripheral */
+    HAL_PSSI_ENABLE(hpssi);
+    if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
+    {
+      uint8_t *pbuffer = pData;
+
+      while (transfer_size > 0U)
+      {
+        /* Init tickstart for timeout management*/
+        tickstart = HAL_GetTick();
+        /* Wait until Fifo is ready to receive one byte flag is set */
+        if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+          hpssi->State = HAL_PSSI_STATE_READY;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+          return HAL_ERROR;
+        }
+        /* Read data from DR */
+        *pbuffer = *(__IO uint8_t *)(&hpssi->Instance->DR);
+        pbuffer++;
+        transfer_size--;
+      }
+    }
+    else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
+    {
+      uint16_t *pbuffer = (uint16_t *)pData;
+      __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
+
+      while (transfer_size > 0U)
+      {
+        /* Init tickstart for timeout management*/
+        tickstart = HAL_GetTick();
+        /* Wait until Fifo is ready to receive four bytes flag is set */
+        if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+          hpssi->State = HAL_PSSI_STATE_READY;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+          return HAL_ERROR;
+        }
+
+        /* Read data from DR */
+        *pbuffer = *dr;
+        pbuffer++;
+        transfer_size -= 2U;
+      }
+    }
+    else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
+    {
+      uint32_t *pbuffer = (uint32_t *)pData;
+
+      while (transfer_size > 0U)
+      {
+        /* Init tickstart for timeout management*/
+        tickstart = HAL_GetTick();
+        /* Wait until Fifo is ready to receive four bytes flag is set */
+        if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
+          hpssi->State = HAL_PSSI_STATE_READY;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+          return HAL_ERROR;
+        }
+
+        /* Read data from DR */
+        *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
+        pbuffer++;
+        transfer_size -= 4U;
+      }
+    }
+    else
+    {
+      hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
+      hpssi->State = HAL_PSSI_STATE_READY;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hpssi);
+      return HAL_ERROR;
+    }
+    /* Check Errors Flags */
+
+    if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
+    {
+      HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
+      hpssi->ErrorCode = HAL_PSSI_ERROR_OVER_RUN;
+      __HAL_UNLOCK(hpssi);
+      return HAL_ERROR;
+    }
+
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent (in bytes)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hpssi->State == HAL_PSSI_STATE_READY)
+  {
+
+    /* Process Locked */
+    __HAL_LOCK(hpssi);
+
+    hpssi->State       = HAL_PSSI_STATE_BUSY_TX;
+    hpssi->ErrorCode   = HAL_PSSI_ERROR_NONE;
+
+    /* Disable the selected PSSI peripheral */
+    HAL_PSSI_DISABLE(hpssi);
+
+    /* Prepare transfer parameters */
+    hpssi->pBuffPtr    = pData;
+    hpssi->XferCount   = Size;
+
+    if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
+    {
+      hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hpssi->XferSize = hpssi->XferCount;
+    }
+
+    if (hpssi->XferSize > 0U)
+    {
+      if (hpssi->hdmatx != NULL)
+      {
+
+        /* Configure BusWidth */
+        if (hpssi->hdmatx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)
+        {
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+                     PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
+        }
+        else
+        {
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+                     PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
+        }
+
+        /* Set the PSSI DMA transfer complete callback */
+        hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt;
+
+        /* Set the DMA error callback */
+        hpssi->hdmatx->XferErrorCallback = PSSI_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hpssi->hdmatx->XferHalfCpltCallback = NULL;
+        hpssi->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA  */
+        if ((hpssi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hpssi->hdmatx->LinkedListQueue != NULL)
+          {
+            /* Enable the DMA channel */
+            /* Set DMA data size */
+            hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize;
+            /* Set DMA source address */
+            hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+            /* Set DMA destination address */
+            hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+              (uint32_t)&hpssi->Instance->DR;
+
+            dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmatx);
+          }
+          else
+          {
+            /* Return error status */
+            return HAL_ERROR;
+          }
+        }
+        else
+        {
+          dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR,
+                                           hpssi->XferSize);
+        }
+      }
+      else
+      {
+        /* Update PSSI state */
+        hpssi->State     = HAL_PSSI_STATE_READY;
+
+        /* Update PSSI error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Update XferCount value */
+        hpssi->XferCount -= hpssi->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        /* Note : The PSSI interrupts must be enabled after unlocking current process
+                  to avoid the risk of PSSI interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR interrupt */
+        HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+        /* Enable DMA Request */
+        hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
+        /* Enable the selected PSSI peripheral */
+        HAL_PSSI_ENABLE(hpssi);
+      }
+      else
+      {
+        /* Update PSSI state */
+        hpssi->State     = HAL_PSSI_STATE_READY;
+
+        /* Update PSSI error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hpssi);
+
+      /* Note : The PSSI interrupts must be enabled after unlocking current process
+                to avoid the risk of PSSI interrupt handle execution before current
+                process unlock */
+      /* Enable ERRinterrupt */
+      /* possible to enable all of these */
+
+      HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received (in bytes)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
+{
+
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hpssi->State == HAL_PSSI_STATE_READY)
+  {
+
+    /* Disable the selected PSSI peripheral */
+    HAL_PSSI_DISABLE(hpssi);
+    /* Process Locked */
+    __HAL_LOCK(hpssi);
+
+    hpssi->State       = HAL_PSSI_STATE_BUSY_RX;
+    hpssi->ErrorCode   = HAL_PSSI_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hpssi->pBuffPtr    = pData;
+    hpssi->XferCount   = Size;
+
+    if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
+    {
+      hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hpssi->XferSize = hpssi->XferCount;
+    }
+
+    if (hpssi->XferSize > 0U)
+    {
+      if (hpssi->hdmarx != NULL)
+      {
+        /* Configure BusWidth */
+        if (hpssi->hdmarx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)
+        {
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
+        }
+        else
+        {
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+                     PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
+        }
+
+        /* Set the PSSI DMA transfer complete callback */
+        hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt;
+
+        /* Set the DMA error callback */
+        hpssi->hdmarx->XferErrorCallback = PSSI_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hpssi->hdmarx->XferHalfCpltCallback = NULL;
+        hpssi->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA  */
+        if ((hpssi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hpssi->hdmarx->LinkedListQueue != NULL)
+          {
+            /* Enable the DMA channel */
+            /* Set DMA data size */
+            hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize;
+            /* Set DMA source address */
+            hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+              (uint32_t)&hpssi->Instance->DR;
+            /* Set DMA destination address */
+            hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+            dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmarx);
+          }
+          else
+          {
+            /* Return error status */
+            return HAL_ERROR;
+          }
+        }
+        else
+        {
+          dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData,
+                                           hpssi->XferSize);
+        }
+      }
+      else
+      {
+        /* Update PSSI state */
+        hpssi->State     = HAL_PSSI_STATE_READY;
+
+        /* Update PSSI error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Update XferCount value */
+        hpssi->XferCount -= hpssi->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        /* Note : The PSSI interrupts must be enabled after unlocking current process
+                  to avoid the risk of PSSI interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR  interrupt */
+        HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+        /* Enable DMA Request */
+        hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
+        /* Enable the selected PSSI peripheral */
+        HAL_PSSI_ENABLE(hpssi);
+      }
+      else
+      {
+        /* Update PSSI state */
+        hpssi->State     = HAL_PSSI_STATE_READY;
+
+        /* Update PSSI error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hpssi);
+
+      /* Enable ERR,interrupt */
+      HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a DMA process communication with Interrupt.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
+{
+  /* Process Locked */
+  __HAL_LOCK(hpssi);
+
+  /* Disable Interrupts */
+  HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+  /* Set State at HAL_PSSI_STATE_ABORT */
+  hpssi->State = HAL_PSSI_STATE_ABORT;
+
+  /* Abort DMA TX transfer if any */
+  if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
+  {
+    if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
+    {
+      hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+      if (hpssi->hdmatx != NULL)
+      {
+        /* Set the PSSI DMA Abort callback :
+        will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+        hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
+
+        /* Abort DMA TX */
+        if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
+        }
+      }
+    }
+    /* Abort DMA RX transfer if any */
+    else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
+    {
+      hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+      if (hpssi->hdmarx != NULL)
+      {
+        /* Set the PSSI DMA Abort callback :
+        will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+        hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
+
+        /* Abort DMA RX */
+        if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
+        {
+          /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
+          hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
+        }
+      }
+    }
+    else
+    {
+
+      /* Call the error callback */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+      hpssi->ErrorCallback(hpssi);
+#else
+      HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hpssi);
+
+  /* Note : The PSSI interrupts must be enabled after unlocking current process
+            to avoid the risk of PSSI interrupt handle execution before current
+            process unlock */
+  HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+  return HAL_OK;
+}
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+
+/**
+  * @brief  This function handles PSSI event interrupt request.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval None
+  */
+void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
+{
+  /* Overrun/ Underrun Errors */
+  if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
+  {
+    /* Reset handle parameters */
+    hpssi->XferCount     = 0U;
+
+    /* Disable all interrupts */
+    HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+    /* Abort DMA TX transfer if any */
+    if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
+    {
+      if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
+      {
+        /* Set new error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_UNDER_RUN;
+
+        hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+        if (hpssi->hdmatx != NULL)
+        {
+          /* Set the PSSI DMA Abort callback :
+          will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+          hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
+          }
+        }
+      }
+      /* Abort DMA RX transfer if any */
+      else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
+      {
+        /* Set new error code */
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_OVER_RUN;
+
+        hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+        if (hpssi->hdmarx != NULL)
+        {
+          /* Set the PSSI DMA Abort callback :
+          will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+          hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hpssi);
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
+          {
+            /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
+            hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
+          }
+        }
+      }
+      else
+      {
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+        /* Call the corresponding callback to inform upper layer of the error */
+        hpssi->ErrorCallback(hpssi);
+#else
+        HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+      }
+    }
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+    /* If state is an abort treatment on going, don't change state */
+    if (hpssi->State == HAL_PSSI_STATE_ABORT)
+    {
+      hpssi->State = HAL_PSSI_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hpssi);
+
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      hpssi->AbortCpltCallback(hpssi);
+#else
+      HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Set HAL_PSSI_STATE_READY */
+      hpssi->State         = HAL_PSSI_STATE_READY;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hpssi);
+
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      hpssi->ErrorCallback(hpssi);
+#else
+      HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief   Tx Transfer complete callback.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval None
+  */
+__weak void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpssi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PSSI_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief   Rx Transfer complete callback.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval None
+  */
+__weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpssi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PSSI_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PSSI error callback.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval None
+  */
+__weak void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpssi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PSSI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PSSI abort callback.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval None
+  */
+__weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpssi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PSSI_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions
+  *  @brief   Peripheral State, Mode and Error functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PSSI handle state.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @retval HAL state
+  */
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi)
+{
+  /* Return PSSI handle state */
+  return hpssi->State;
+}
+
+/**
+  * @brief  Return the PSSI error code.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *              the configuration information for the specified PSSI.
+  * @retval PSSI Error Code
+  */
+uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi)
+{
+  return hpssi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_Exported_Functions_Group4 Clock Source Selection function
+  *  @brief   Clock Source Selection function to pick between an internal or
+  *           external clock.
+  *
+@verbatim
+ ===============================================================================
+                  ##### Clock Source Selection function #####
+ ===============================================================================
+    [..] This subsection provides a function allowing to:
+      (+) Configure Clock source
+       (++) The clock source could be external (default) or internal (the clock
+            is generated by the device RCC).
+       (++) The AHB clock frequency must be at least 2.5 times higher than the
+            PSSI_PDCK frequency
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure PSSI Clock Source.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI peripheral.
+  * @param  ClockSource New Clock Configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PSSI_ClockConfig(PSSI_HandleTypeDef *hpssi, uint32_t ClockSource)
+{
+  /* Check the parameter */
+  assert_param(IS_PSSI_CLOCK_SOURCE(ClockSource));
+
+  if (hpssi->State == HAL_PSSI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hpssi);
+
+    HAL_PSSI_DISABLE(hpssi);
+
+    /* Set CKSRC to ClockSource */
+    MODIFY_REG(hpssi->Instance->CR, PSSI_CR_CKSRC, ClockSource);
+
+    HAL_PSSI_ENABLE(hpssi);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  PSSI Errors process.
+  * @param  hpssi PSSI handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
+{
+  /* Reset handle parameters */
+  hpssi->XferCount     = 0U;
+
+  /* Set new error code */
+  hpssi->ErrorCode |= ErrorCode;
+
+  /* Disable all interrupts */
+  HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort DMA TX transfer if any */
+  if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
+  {
+    if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
+    {
+      hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+      if (hpssi->hdmatx != NULL)
+      {
+        /* Set the PSSI DMA Abort callback :
+        will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+        hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        /* Abort DMA TX */
+        if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
+        }
+      }
+    }
+    /* Abort DMA RX transfer if any */
+    else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
+    {
+      hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
+
+      if (hpssi->hdmarx != NULL)
+      {
+        /* Set the PSSI DMA Abort callback :
+        will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
+        hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        /* Abort DMA RX */
+        if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
+        {
+          /* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
+          hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
+        }
+      }
+    }
+    else
+    {
+      /*Nothing to do*/
+    }
+  }
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+  /* If state is an abort treatment on going, don't change state */
+  if (hpssi->State == HAL_PSSI_STATE_ABORT)
+  {
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    hpssi->AbortCpltCallback(hpssi);
+#else
+    HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Set HAL_PSSI_STATE_READY */
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    hpssi->ErrorCallback(hpssi);
+#else
+    HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  DMA PSSI slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  uint32_t tmperror;
+
+  /* Disable Interrupts */
+  HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+  /* Store current volatile hpssi->ErrorCode, misra rule */
+  tmperror = hpssi->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    PSSI_Error(hpssi, hpssi->ErrorCode);
+  }
+  /* hpssi->State == HAL_PSSI_STATE_BUSY_TX */
+  else
+  {
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    hpssi->TxCpltCallback(hpssi);
+#else
+    HAL_PSSI_TxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA PSSI master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  uint32_t tmperror;
+
+  /* Disable Interrupts */
+  HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+  /* Store current volatile hpssi->ErrorCode, misra rule */
+  tmperror = hpssi->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    PSSI_Error(hpssi, hpssi->ErrorCode);
+  }
+  /* hpssi->State == HAL_PSSI_STATE_BUSY_RX */
+  else
+  {
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    hpssi->RxCpltCallback(hpssi);
+#else
+    HAL_PSSI_RxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA PSSI communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  /* Reset AbortCpltCallback */
+  hpssi->hdmatx->XferAbortCallback = NULL;
+  hpssi->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if come from abort from user */
+  if (hpssi->State == HAL_PSSI_STATE_ABORT)
+  {
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    hpssi->AbortCpltCallback(hpssi);
+#else
+    HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    hpssi->ErrorCallback(hpssi);
+#else
+    HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+  }
+}
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+/**
+  * @brief  This function handles PSSI Communication Timeout.
+  * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
+  *                the configuration information for the specified PSSI.
+  * @param  Flag Specifies the PSSI flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
+                                                       uint32_t Timeout, uint32_t Tickstart)
+{
+  while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hpssi->ErrorCode |= HAL_PSSI_ERROR_TIMEOUT;
+        hpssi->State = HAL_PSSI_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hpssi);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+void PSSI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+
+  uint32_t tmperror;
+
+  /* Disable the selected PSSI peripheral */
+  HAL_PSSI_DISABLE(hpssi);
+
+  /* Disable Interrupts */
+  HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
+
+  /* Store current volatile hpssi->ErrorCode, misra rule */
+  tmperror = hpssi->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    PSSI_Error(hpssi, hpssi->ErrorCode);
+  }
+  else
+  {
+    hpssi->State = HAL_PSSI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hpssi);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+    hpssi->ErrorCallback(hpssi);
+#else
+    HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+  }
+}
+#endif /*HAL_DMA_MODULE_ENABLED*/
+
+
+/**
+  * @}
+  */
+#endif /* PSSI */
+#endif /* HAL_PSSI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pwr.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pwr.c
new file mode 100644
index 000000000..73223def2
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pwr.c
@@ -0,0 +1,1035 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization/De-Initialization Functions.
+  *           + Peripheral Control Functions.
+  *           + PWR Attributes Functions.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### PWR peripheral overview #####
+  ==============================================================================
+  [..]
+   (#) The Power control (PWR) provides an overview of the supply architecture
+       for the different power domains and of the supply configuration
+       controller.
+
+   (#) Several low-power modes are available to save power when the CPU does not need to
+       execute code :
+      (+) Sleep   (CPU clock stopped and still in RUN mode)
+      (+) Stop    (System clock stopped)
+      (+) Standby (System powered down)
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+   (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
+       to enable/disable access to the backup domain (RCC Backup domain control
+       register RCC_BDCR, RTC registers, TAMP registers, backup registers and
+       backup SRAM).
+
+   (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
+       mode and voltage threshold) in order to set up the Programmed Voltage
+       Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD()
+       functions to start and stop the PVD detection.
+   (+) PVD level on PVD_IN is compared to the internal VREFINT level.
+       PVDO flag is available in PWR_CR2 to indicate if the voltage level
+       on PVD_IN is higher or lower than the PVD threshold.
+
+   (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
+       with the right parameter to configure the wake up pin polarity (Low or
+       High), the wake up pin selection and to enable and disable it.
+
+   (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
+       functions to manage wake-up flag for the selected pin.
+
+   (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode.
+       Wake-up from Sleep mode could be following to an event or an
+       interrupt according to low power mode intrinsic request called (__WFI()
+       or __WFE()).
+
+   (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop
+       mode. Wake-up from Stop mode could be following to an event or an
+       interrupt according to low power mode intrinsic request called (__WFI()
+       or __WFE()). (Regulator state on STM32N6 devices is managed internally but
+       regulator parameter is kept for product compatibility).
+
+   (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
+       Standby mode. Wake-up from Standby mode can be following only by an
+       interrupt.
+
+   (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
+       enable and disable the Cortex-M55 re-entry in Sleep mode after an
+       interruption handling is over.
+
+   (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
+       to configure the Cortex-M55 to wake-up after any pending event / interrupt
+       even if it's disabled or has insufficient priority to cause exception
+       entry.
+
+   (#) Call HAL_PWR_WAKEUP_PIN_IRQHandler() function to handle all wake-up
+       pins interrupts.
+
+   (#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and
+       privilege attributes and call HAL_PWR_GetConfigAttributes() function to
+       get the attribute configuration for the selected item.
+
+     *** PWR HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in PWR HAL driver.
+
+      (+) __HAL_PWR_GET_FLAG()   : Get the PWR pending flags.
+      (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#if defined (HAL_PWR_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Defines PWR Private Defines
+  * @{
+  */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */
+#define PVD_MODE_IT                    (0x00010000U)                           /*!< Mask for interruption yielded by PVD threshold crossing */
+#define PVD_MODE_EVT                   (0x00020000U)                           /*!< Mask for event yielded by PVD threshold crossing        */
+#define PVD_RISING_EDGE                (0x00000001U)                           /*!< Mask for rising edge set as PVD trigger                 */
+#define PVD_FALLING_EDGE               (0x00000002U)                           /*!< Mask for falling edge set as PVD trigger                */
+#define PVD_RISING_FALLING_EDGE        (0x00000003U)                           /*!< Mask for rising & falling edge set as PVD trigger       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  *  @brief   Initialization and de-Initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and De-Initialization Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to deinitialize power peripheral.
+
+    [..]
+      After system reset, the backup domain (RCC Backup domain control register
+      RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM)
+      is protected against possible unwanted write accesses.
+      The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
+      domain.
+      The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
+      domain.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
+  *         values.
+  * @note   This functionality is not available in this product.
+  *         The prototype is kept just to maintain compatibility with other
+  *         products.
+  * @retval None.
+  */
+void HAL_PWR_DeInit(void)
+{
+}
+
+/**
+  * @brief  Enable access to the backup domain (RCC Backup domain control
+  *         register RCC_BDCR, RTC registers, TAMP registers, backup registers
+  *         and backup SRAM).
+  * @note   After a system reset, the backup domain is protected against
+  *         possible unwanted write accesses.
+  * @retval None.
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  WRITE_REG(PWR->DBPCR, PWR_DBPCR_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain (RCC Backup domain control
+  *         register RCC_BDCR, RTC registers, TAMP registers, backup registers
+  *         and backup SRAM).
+  * @retval None.
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_REG(PWR->DBPCR);
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
+  *  @brief   Power Control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripheral Control Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to control power peripheral.
+
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it
+          to the internal VREFINT.
+
+      (+) A PVDO flag is available to indicate if VDD is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line 66 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+
+      (+) The PVD is stopped in STANDBY mode.
+
+    *** Wake-up pin configuration ***
+    =================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from STANDBY mode.
+          The pin pull is configurable through the WKUPEPR register to be in
+          No-pull, Pull-up and Pull-down.
+          The pin polarity is configurable through the WKUPEPR register to be
+          active on rising or falling edges.
+
+      (+) There are up to four Wake-up pin in the STM32N6 devices family.
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+     The device present 3 principles low-power modes :
+      (+) SLEEP mode   : Cortex-M55 is stopped and all PWR domains are remaining
+                         active (Powered and Clocked).
+
+      (+) STOP mode    : Cortex-M55 is stopped, clocks are stopped and the
+                         regulator is running. The Main regulator or the LP
+                         regulator could be selected.
+
+      (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
+                         supply regulator is powered off.
+
+   *** SLEEP mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
+        SLEEPEntry) function.
+
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
+          (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: enter SLEEP mode with WFE instruction
+                                                and no clear of pending event.
+
+      -@@- The Regulator parameter is not used for the STM32N6 family
+              and is kept as parameter just to maintain compatibility with the
+              lower power families.
+
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt
+        controller (NVIC) can wake up the device from SLEEP mode.
+
+   *** STOP mode ***
+   =================
+    [..]
+      In system STOP mode, the CPU clock is stopped. All CPU subsystem peripheral
+      clocks are stopped too.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption in STOP mode, FLASH can be powered off before
+      entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the STOP mode using
+      the HAL_PWREx_DisableFlashPowerDown() function.
+      (+) Entry:
+         The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
+         STOPEntry) function with:
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
+                This parameter is not used for the STM32N6 family and is kept as parameter
+                just to maintain compatibility with the lower power families.
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
+          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
+          (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: enter STOP mode with WFE instruction
+                                                and no clear of pending event.
+
+      (+) Exit:
+         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** STANDBY mode ***
+   ====================
+    [..]
+    (+)
+      The system STANDBY mode allows to achieve the lowest power consumption.
+      It is based on the Cortex-M55 deep SLEEP mode, with the voltage regulator
+      disabled. The system is consequently powered off. The PLL, the HSI
+      oscillator and the HSE oscillator are also switched off. SRAM and register
+      contents are lost except for the RTC registers, RTC backup registers,
+      backup SRAM and standby circuitry.
+
+    [..]
+      The voltage regulator is OFF.
+
+      (++) Entry:
+        (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
+              function.
+
+      (++) Exit:
+        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
+              RTC wakeup, tamper event, time stamp event, external reset in NRST
+              pin, IWDG reset.
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
+         RTC Wakeup event, a tamper event or a time-stamp event, without
+         depending on an external interrupt (Auto-wakeup mode).
+
+     (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
+
+       (++) To wake up from the STOP mode with an RTC alarm event, it is
+            necessary to configure the RTC to generate the RTC alarm using the
+            HAL_RTC_SetAlarm_IT() function.
+
+       (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
+            it is necessary to configure the RTC to detect the tamper or time
+            stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
+            HAL_RTCEx_SetTamper_IT() functions.
+
+       (++) To wake up from the STOP mode with an RTC WakeUp event, it is
+            necessary to configure the RTC to generate the RTC WakeUp event
+            using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the voltage threshold detected by the Programmed Voltage
+  *         Detector (PVD).
+  * @param  pConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the
+  *                      PVD configuration information (EventMode).
+  * @retval None.
+  */
+void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *pConfigPVD)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_MODE(pConfigPVD->Mode));
+
+  /* Disable PVD Event/Interrupt */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+  /* Configure the PVD in interrupt mode */
+  if ((pConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+
+  /* Configure the PVD in event mode */
+  if ((pConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+
+  /* Rising edge configuration */
+  if ((pConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+
+  /* Falling edge configuration */
+  if ((pConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+}
+
+/**
+  * @brief  Enable the programmable voltage detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_PVDEN);
+}
+
+/**
+  * @brief  Disable the programmable voltage detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDEN);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality.
+  * @param  WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
+  *          This parameter can be one of the following legacy values, which
+  *          sets the default (rising edge):
+  *            @arg PWR_WAKEUP_PIN1,
+  *                 PWR_WAKEUP_PIN2,
+  *                 PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4.
+  *          or one of the following values where the user can explicitly states
+  *          the enabled pin and the chosen polarity:
+  *            @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW.
+  * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+  * @retval None.
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+
+  /*
+     Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge).
+  */
+  SET_BIT(PWR->WKUPEPR, WakeUpPinPolarity);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality.
+  * @param  WakeUpPinx : Specifies the Power Wake-Up pin to disable.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_PIN1,
+  *                 PWR_WAKEUP_PIN2,
+  *                 PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4,
+  *                 PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW.
+  * @retval None.
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  /* Disable the wake up pin selected */
+  CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
+}
+
+/**
+  * @brief Get the Wake-Up Pin pending flags.
+  * @param  WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1    : Get wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2    : Get wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3    : Get wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG4    : Get wakeup event received from PD2.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
+  *                                       wake up pins.
+  * @retval The Wake-Up pin flag.
+  */
+uint32_t HAL_PWR_GetWakeupFlag(uint32_t WakeUpFlag)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));
+
+  /* Return the wake up pin flag */
+  return (PWR->WKUPSR & WakeUpFlag);
+}
+
+/**
+  * @brief Clear the Wake-Up pin pending flag.
+  * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1    : Clear the wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2    : Clear the wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3    : Clear the wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG4    : Clear the wakeup event received from PD2.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from all
+  *                                       wake up pins.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWR_ClearWakeupFlag(uint32_t WakeUpFlag)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag));
+
+  /* Clear the wake up event received from wake up pin x */
+  WRITE_REG(PWR->WKUPCR, WakeUpFlag);
+
+  /* Check if the wake up event is well cleared */
+  if ((PWR->WKUPSR & WakeUpFlag) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enter the current core in SLEEP mode (CSLEEP).
+  * @param  Regulator : NA in this family project
+  *         Specifies the regulator state in SLEEP mode.
+  * @note   This parameter is not used for the STM32N6 family and is kept as
+  *         parameter just to maintain compatibility with the lower power
+  *         families.
+  * @param  SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
+  *                      intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI :             Enter SLEEP mode with WFI instruction.
+  *            @arg PWR_SLEEPENTRY_WFE :             Enter SLEEP mode with WFE instruction.
+  *            @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE and no clear of pending event before.
+  *
+  * @note   Ensure to clear pending events before calling this API through
+  *         HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
+  * @retval None.
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Regulator);
+
+  /* Check the parameters */
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Select Sleep mode entry */
+  if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)
+    {
+      /* Clear all pending event */
+      __SEV();
+      __WFE();
+    }
+
+    /* Request Wait For Event */
+    __WFE();
+  }
+}
+
+/**
+  * @brief  Enter the whole system to Stop mode.
+  * @note   This API will enter the system in STOP mode
+  * @param  Regulator : This parameter is not used for this product family.
+            and is kept as parameter just to maintain compatibility with the
+            lower power families.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI              : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE              : Enter STOP mode with WFE instruction.
+  *            @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP  mode with WFE and no clear of pending event before.
+  * @note   In System STOP mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting System STOP mode by issuing an interrupt or a wakeup
+  *         event, the HSI RC oscillator is selected as default system wakeup
+  *         clock.
+  * @note   In System STOP mode, when the voltage regulator operates in low
+  *         power mode, an additional startup delay is incurred when the system
+  *         is waking up. By keeping the internal regulator ON during STOP mode,
+  *         the consumption is higher although the startup time is reduced.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Regulator);
+
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+  /* Select Stop mode when device enters Deepsleep */
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB();
+  __ISB();
+
+  /* Select Stop mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR)
+    {
+      /* Clear all pending event */
+      __SEV();
+      __WFE();
+    }
+
+    /* Request Wait For Event */
+    __WFE();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-M55 in the System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Enter the whole system to Standby mode.
+  * @note   The Standby mode allows achieving the lowest power consumption.
+  * @note   When the system enters in Standby mode, the voltage regulator is disabled.
+  *         The complete VCORE domain is consequently powered off.
+  *         The PLLs, HSI oscillator, CSI oscillator, HSI48 and the HSE oscillator are
+  *         also switched off.
+  *         SRAM and register contents are lost except for backup domain registers
+  *         (RTC registers, RTC backup register and backup RAM), and Standby circuitry.
+  * @note   When the System exit STANDBY mode by issuing an interrupt or a
+  *         wakeup event, the HSI RC oscillator is selected as system clock.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Select Standby when device enters Deepsleep */
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STANDBY mode */
+  __DSB();
+  __ISB();
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief  Indicate SLEEP-ON-EXIT feature when returning from handler mode to
+  *         thread mode.
+  * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters Sleep mode when an interruption handling is over.
+  *         Setting this bit is useful when the processor is expected to run
+  *         only on interruptions handling.
+  * @retval None.
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex-M55 System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Disable SLEEP-ON-EXIT feature when returning from handler mode to
+  *         thread mode.
+  * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters Sleep mode when an interruption handling is over.
+  * @retval None.
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex-M55 System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enable CORTEX SEV-ON-PEND feature.
+  * @note   Sets SEVONPEND bit of SCR register. When this bit is set, any
+  *         pending event / interrupt even if it's disabled or has insufficient
+  *         priority to cause exception entry wakes up the Cortex-M55.
+  * @retval None.
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex-M55 System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Disable CORTEX SEVONPEND feature.
+  * @note   Resets SEVONPEND bit of SCR register. When this bit is reset, only
+  *         enabled pending causes exception entry wakes up the Cortex-M55.
+  * @retval None.
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex-M55 System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  PWR PVD interrupt Rising callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVD_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_PWR_PVD_Rising_Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief  PWR PVD interrupt Falling callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVD_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_PWR_PVD_Falling_Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief This function handles the PWR WAKEUP PIN interrupt request.
+  * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWR_WAKEUP_PIN_IRQHandler(void)
+{
+  /* Wakeup pin EXTI line interrupt detected */
+  if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF1) != 0U)
+  {
+    /* Clear PWR WKUPF1 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP1);
+
+    /* PWR WKUP1 interrupt user callback */
+    HAL_PWR_WKUP1_Callback();
+  }
+
+  if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF2) != 0U)
+  {
+    /* Clear PWR WKUPF2 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP2);
+
+    /* PWR WKUP2 interrupt user callback */
+    HAL_PWR_WKUP2_Callback();
+  }
+
+  if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF3) != 0U)
+  {
+    /* Clear PWR WKUPF3 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP3);
+
+    /* PWR WKUP3 interrupt user callback */
+    HAL_PWR_WKUP3_Callback();
+  }
+
+  if (READ_BIT(PWR->WKUPSR, PWR_WKUPSR_WKUPF4) != 0U)
+  {
+    /* Clear PWR WKUPF4 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG(PWR_FLAG_WKUP4);
+
+    /* PWR WKUP4 interrupt user callback */
+    HAL_PWR_WKUP4_Callback();
+  }
+}
+
+/**
+  * @brief PWR WKUP1 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_WKUP1_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_WKUP1_Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP2 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_WKUP2_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_WKUP2_Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP3 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_WKUP3_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_WKUP3_Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP4 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_WKUP4_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_WKUP4_Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @}
+  */
+#if defined(PWR_PRIVCFGR_PRIV0)
+/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions
+  *  @brief    Attributes management functions
+  *
+@verbatim
+ ===============================================================================
+                       ##### PWR Attributes Functions #####
+ ===============================================================================
+    [..]
+      The PWR is able to protect register bits from being modified by non-secure
+      and unprivileged accesses.
+      The protection can be activated for the following features through PWR_SECCFGR and
+      PWR_PRIVCFGR:
+
+      (++) System supply configuration.
+      (++) Voltage scaling.
+      (++) Low-power mode.
+      (++) Wake-up (WKUP) pins.
+      (++) Voltage detection and monitoring.
+      (++) VBAT mode.
+
+      A non-secure access to a secure-protected register bit is denied :
+      (++) The secured bits are not written (WI) with a non-secure write access.
+      (++) The secured bits are read as 0 (RAZ) with a non-secure read access.
+
+    [..]
+      After any application reset or system reset, the PWR does not filter any access
+      (default configuration: non-secure, any privileged) until the trusted agent has
+      programmed the security and privileged protection.
+
+    [..] Secure/non-secure access filtering
+      To enable the filtering access based on this attribute, the authorized master
+      agent must set SECx in PWR_SECCFGR related to the PWR feature.
+
+      When a register is configured as secure, read and write operations are only
+      allowed by a secure access.
+      Non-secure read or write accesses are denied (RAZ/WI).
+      An illegal secure access event is generated to the IAC (illegal access controller).
+      There is no bus error generated.
+      When a register is configured as non-secure, read and write operations are
+      allowed by both secure and non-secure accesses.
+
+    [..] Privileged/unprivileged access filtering
+      To enable the filtering access based on this attribute, the authorized master
+      agent has to set PRIVx in PWR_PRIVCFGR related to the PWR feature.
+      When a register is configured as privileged, read and write operations are only
+      allowed by a privileged access.
+      Unprivileged read or write accesses are denied (RAZ/WI).
+      An illegal privileged access event is generated to the IAC.
+      There is no bus error generated.
+      When a register is configured as unprivileged, read and write operations are
+      allowed by both privileged and unprivileged accesses.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the PWR item attributes.
+  * @note   Available attributes are security and privilege protection.
+  * @note   Security attribute can only be set only by secure access.
+  * @note   Privilege attribute for secure items can be managed only by a secure
+  *         privileged access.
+  * @note   Privilege attribute for nsecure items can be managed  by a secure
+  *         privileged access or by a nsecure privileged access.
+  * @param  Item       : Specifies the item(s) to set attributes on.
+  *                      This parameter can be a combination of PWR_ITEMS.
+  * @param  Attributes : Specifies the available attribute(s).
+  *                      This parameter can be one of PWR_ATTRIBUTES.
+  * @retval None.
+  */
+void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
+  assert_param(IS_PWR_ATTRIBUTES(Attributes));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  /* Secure item management (TZEN = 1) */
+  if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK)
+  {
+    /* Privilege item management */
+    if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV)
+    {
+      SET_BIT(PWR_S->SECCFGR, Item);
+      SET_BIT(PWR->PRIVCFGR, Item);
+    }
+    else
+    {
+      SET_BIT(PWR_S->SECCFGR, Item);
+      CLEAR_BIT(PWR->PRIVCFGR, Item);
+    }
+  }
+  /* NSecure item management */
+  else
+  {
+    /* Privilege item management */
+    if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
+    {
+      CLEAR_BIT(PWR_S->SECCFGR, Item);
+      SET_BIT(PWR->PRIVCFGR, Item);
+    }
+    else
+    {
+      CLEAR_BIT(PWR_S->SECCFGR, Item);
+      CLEAR_BIT(PWR->PRIVCFGR, Item);
+    }
+  }
+#else
+  /* NSecure item management (TZEN = 0) */
+  if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK)
+  {
+    /* Privilege item management */
+    if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
+    {
+      SET_BIT(PWR->PRIVCFGR, Item);
+    }
+    else
+    {
+      CLEAR_BIT(PWR->PRIVCFGR, Item);
+    }
+  }
+#endif /* __ARM_FEATURE_CMSE */
+}
+
+
+/**
+  * @brief  Get attribute(s) of a PWR item.
+  * @param  Item        : Specifies the item(s) to get attributes on.
+  *                       This parameter can be one of PWR_ITEMS.
+  * @param  pAttributes : Pointer to return attribute(s).
+  *                       Returned value could be on of PWR_ATTRIBUTES.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
+{
+  uint32_t attributes;
+
+  /* Check attribute pointer */
+  if (pAttributes == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+  /* Check item security */
+  if ((PWR->SECCFGR & Item) == Item)
+  {
+    if ((PWR->PRIVCFGR & Item) == Item)
+    {
+      attributes = PWR_SEC_PRIV;
+    }
+    else
+    {
+      attributes = PWR_SEC_NPRIV;
+    }
+  }
+  else
+  {
+    if ((PWR->PRIVCFGR & Item) == Item)
+    {
+      attributes = PWR_NSEC_PRIV;
+    }
+    else
+    {
+      attributes = PWR_NSEC_NPRIV;
+    }
+  }
+#else
+  if ((PWR->PRIVCFGR & Item) == Item)
+  {
+    attributes = PWR_NSEC_PRIV;
+  }
+  else
+  {
+    attributes = PWR_NSEC_NPRIV;
+  }
+#endif /* __ARM_FEATURE_CMSE */
+
+  /* return value */
+  *pAttributes = attributes;
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+#endif /* #if defined(PWR_PRIVCFGR_PRIV0) */
+
+/**
+  * @}
+  */
+#endif /* defined (HAL_PWR_MODULE_ENABLED) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pwr_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pwr_ex.c
new file mode 100644
index 000000000..296811212
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_pwr_ex.c
@@ -0,0 +1,1798 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller extension peripheral :
+  *           + Power Supply Control Functions
+  *           + Low Power Control Functions
+  *           + Voltage Monitoring Functions
+  *           + Memories Retention Functions
+  *           + I/O Pull-Up Pull-Down Configuration Functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
+       with the following different setups according to hardware:
+       (+) PWR_SMPS_SUPPLY
+       (+) PWR_EXTERNAL_SOURCE_SUPPLY
+
+   (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
+
+   (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
+       internal regulator output voltage. The voltage scaling could be one of
+       the following scales :
+       (+) PWR_REGULATOR_VOLTAGE_SCALE0
+       (+) PWR_REGULATOR_VOLTAGE_SCALE1
+
+   (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
+       voltage applied to the main regulator.
+
+   (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the main
+       internal regulator output voltage in STOP mode. The voltage scaling could be one of
+       the following scales :
+       (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE3
+       (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE5
+
+   (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current output
+       voltage applied to the main regulator in STOP mode.
+
+   (#) Call HAL_PWREx_EnableWakeUpPin() functions to enable the Wake-up pin
+       functionality for the selected pin.
+
+   (#) Call HAL_PWREx_EnableBkupRAMRetention() and HAL_PWREx_DisableBkupRAMRetention()
+       functions to enable and disable BKPSRAM retention in Standby mode.
+
+   (#) Call HAL_PWREx_EnableTCMRetention() and HAL_PWREx_DisableTCMRetention() functions
+       to enable and disable the I-TCM and D-TCM RAMs retention in Standby mode.
+
+   (#) Call HAL_PWREx_EnableTCMFLXRetention() and HAL_PWREx_DisableTCMFLXRetention()
+       functions to enable and disable the I-TCM FLEXMEM retention in Standby mode.
+
+   (#) Call HAL_PWREx_SetPulseLow() function to configure the minimum guaranteed
+       duration of the pwr_on low pulse in Standby mode ( between ~ 0 -> 31 ms).
+
+   (#) Call HAL_PWREx_GetPulseLow() function to get the minimum guaranteed
+       duration of the pwr_on low pulse in Standby mode.
+
+   (#) Call HAL_PWREx_EnableTCMFLXRetention() and HAL_PWREx_DisableTCMFLXRetention()
+       functions to enable and disable the I-TCM FLEXMEM retention in Standby mode.
+
+   (#) Call HAL_PWREx_EnableSMPSPWM() and HAL_PWREx_DisableSMPSPWM() functions to
+       enable and disable the SMPS low-power mode in Stop SVOS range 3.
+
+   (#) Call HAL_PWREx_EnablePullDownOutput() and HAL_PWREx_DisablePullDownOutput()
+       functions to enable and disable the pull down on output voltage during
+       power-down mode.
+
+   (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
+       functions to enable and disable the VBAT and Temperature monitoring.
+       When VBAT and Temperature monitoring feature is enables, use
+       HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
+       respectively the Temperature level and VBAT level.
+
+   (#) Call HAL_PWREx_EnableVDDCOREMonitoring() and HAL_PWREx_EnableVDDCOREMonitoring()
+       functions to enable and disable the VCORE monitoring.
+       When VDDCORE monitoring feature is enables, use HAL_PWREx_GetVDDCORELevel()
+       function to get the current VDDCORE level.
+
+   (#) Call HAL_PWREx_ConfigVDDCORELevel() function to configure the VDDCORE
+       voltage detector low-level selection.
+
+   (#) Call HAL_PWREx_ConfigVddIORange() functions to configure the Vdd IO range:
+       (+) PWR_VDDIO
+       (+) PWR_VDDIO2
+       (+) PWR_VDDIO3
+       (+) PWR_VDDIO4
+       (+) PWR_VDDIO5
+       The voltage range setting could be one of the following values:
+       (+) PWR_VDDIO_RANGE_3V3
+       (+) PWR_VDDIO_RANGE_1V8
+
+   (#) Call HAL_PWREx_GetVddIORange() function to get the current
+       voltage range setting on the selected Vdd IO.
+
+   (#) Call HAL_PWREx_EnableVddIO4RangeSTBY() and HAL_PWREx_DisableVddIO4RangeSTBY()
+       functions to enable and disable the VDD IO4 voltage range Standby mode.
+
+   (#) Call HAL_PWREx_EnableVddIO5RangeSTBY() and HAL_PWREx_DisableVddIO5RangeSTBY()
+       functions to enable and disable the VDD IO5 voltage range Standby mode.
+
+   (#) Call HAL_PWREx_EnableVddUSB() and HAL_PWREx_DisableVddUSB()
+       functions to enable and disable the VDD33USB supply valid.
+
+   (#) Call HAL_PWREx_EnableVddIO2() and HAL_PWREx_DisableVddIO2()
+       functions to enable and disable the VDDIO2 supply valid.
+
+   (#) Call HAL_PWREx_EnableVddIO3() and HAL_PWREx_DisableVddIO3()
+       functions to enable and disable the VDDIO3 supply valid.
+
+   (#) Call HAL_PWREx_EnableVddIO4() and HAL_PWREx_DisableVddIO4()
+       functions to enable and disable the VDDIO4 supply valid.
+
+   (#) Call HAL_PWREx_EnableVddIO5() and HAL_PWREx_DisableVddIO5()
+       functions to enable and disable the VDDIO5 supply valid.
+
+   (#) Call HAL_PWREx_EnableVddA() and HAL_PWREx_DisableVddA()
+       functions to enable and disable the VDDA18ADC supply valid.
+
+   (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured
+       (event mode and PVD type) in order to set up the Peripheral Voltage
+       Monitor, then use HAL_PWREx_EnableVddUSBVMEN(), HAL_PWREx_EnableVddIO2VMEN(),
+       HAL_PWREx_EnableVddIO3VMEN(), HAL_PWREx_EnableVddIO4VMEN(),
+       HAL_PWREx_EnableVddIO5VMEN() and HAL_PWREx_EnableVddAVMEN() functions to
+       start the PVM VDDx monitoring.
+       Use HAL_PWREx_DisableVddUSBVMEN(), HAL_PWREx_DisableVddIO2VMEN(),
+       HAL_PWREx_DisableVddIO3VMEN(), HAL_PWREx_DisableVddIO4VMEN(),
+       HAL_PWREx_DisableVddIO5VMEN() and HAL_PWREx_DisableVddAVMEN() to stop
+       the PVM VDDx monitoring.
+       (+) PVM monitored voltages are :
+             (++) VDDUSB
+             (++) VDDIO2
+             (++) VDDIO3
+             (++) VDDIO4
+             (++) VDDIO5
+             (++) VDDA
+
+   (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and
+       PVM interrupt request.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief    PWR Extended HAL module driver
+  * @{
+  */
+
+#if defined (HAL_PWR_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
+  * @{
+  */
+#define PWR_FLAG_SETTING_DELAY         (1000U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
+  * @{
+  */
+/* Wake-Up Pins EXTI register mask */
+#define PWR_EXTI_WAKEUP_PINS_MASK      (EXTI_IMR2_IM60 | EXTI_IMR2_IM61 |\
+                                        EXTI_IMR2_IM62 | EXTI_IMR2_IM63 )
+
+/* Wake-Up Pins PWR Pin Pull shift offsets */
+#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
+  * @{
+  */
+#define PVM_RISING_EDGE                (1U)                                    /*!< Mask for rising edge set as PVM trigger                 */
+#define PVM_FALLING_EDGE               (2U)                                    /*!< Mask for falling edge set as PVM trigger                */
+#define PVM_MODE_IT                    (4U)                                    /*!< Mask for interruption yielded by PVM threshold crossing */
+#define PVM_MODE_EVT                   (8U)                                    /*!< Mask for event yielded by PVM threshold crossing        */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_VDDCOREVM_Mode_Mask PWR VddCORE VM Mode Mask
+  * @{
+  */
+#define VDDCOREVM_RISING_EDGE          (1U)                                    /*!< Mask for rising edge set as PVM trigger                 */
+#define VDDCOREVM_FALLING_EDGE         (2U)                                    /*!< Mask for falling edge set as PVM trigger                */
+#define VDDCOREVM_MODE_IT              (4U)                                    /*!< Mask for interruption yielded by PVM threshold crossing */
+#define VDDCOREVM_MODE_EVT             (8U)                                    /*!< Mask for event yielded by PVM threshold crossing        */
+/**
+  * @}
+  */
+
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @brief    Power supply control functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Power supply control functions #####
+ ===============================================================================
+    [..]
+       This section provides functions allowing to control power supply.
+
+   (+) The STM32N6 series devices allows two different supply configurations:
+       Direct SMPS supply and external supply.
+
+   (#) After a system reset, the software must configure the used supply configuration
+       in PWR_CR1 using  HAL_PWREx_ConfigSupply() function before changing VOS in PWR_VOSCR,
+       or the RCC sys_ck frequency.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure the system Power Supply.
+  * @param  SupplySource : Specifies the Power Supply source to set after a
+  *                        system startup.
+  *         This parameter can be one of the following values :
+  *            @arg @ref PWR_SMPS_SUPPLY            : VCORE power domains are supplied
+  *                                                   from SMPS step-down converter
+  *                                                   according to VOS.
+  *            @arg @ref PWR_EXTERNAL_SOURCE_SUPPLY : VCORE supplied from external source.
+  *                                                   SMPS step-down converter disabled.
+  * @note: The power supply configuration can be written only one time after POR.
+  * @note: The power supply configuration is not reset by wakeup from Standby mode and
+  *        application reset, but only reset by VDD POR.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_SUPPLY(SupplySource));
+
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR1, PWR_SUPPLY_CONFIG_MASK, SupplySource);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till voltage level flag is set */
+  while ((PWR->VOSCR & PWR_VOSCR_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the power supply configuration.
+  * @retval The supply configuration.
+  */
+uint32_t HAL_PWREx_GetSupplyConfig(void)
+{
+  return (PWR->CR1 & PWR_SUPPLY_CONFIG_MASK);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @param  VoltageScaling : Specifies the regulator output voltage to achieve
+  *                          a tradeoff between performance and power
+  *                          consumption.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage scaling range 0 (highest frequency).
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage scaling range 1 (lowest power).
+  * @note After reset, the system starts from HSI with VOS low.
+  * @note When increasing the performance, the voltage scaling must be changed
+  *       before increasing the system frequency.
+  *       When decreasing performance, the system frequency must first be decreased
+  *       before changing the voltage scaling.
+  * @note When exiting from Stop mode or Standby mode, the Run mode voltage
+  *       scaling is reset to the default VOS low value.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
+
+  /* Set the voltage range */
+  MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till voltage level flag is set */
+  while ((PWR->VOSCR & PWR_VOSCR_VOSRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage. Reflecting the last
+  *        VOS value applied to the PMU.
+  * @retval The current applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+  /* Get the active voltage scaling */
+  return ((PWR->VOSCR & PWR_VOSCR_ACTVOS) >> PWR_VOSCR_ACTVOS_Pos);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage in STOP mode.
+  * @param  VoltageScaling : Specifies the regulator output voltage when the
+  *         system enters Stop mode to achieve a tradeoff between performance
+  *         and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE3 : System Stop mode voltage scaling range 3 (highest frequency).
+  *            @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE5 : System Stop mode voltage scaling range 5 (lowest power).
+  * @retval None.
+  */
+void HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling));
+
+  /* Return the stop mode voltage range */
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling);
+}
+
+/**
+  * @brief Get the main internal regulator output voltage in STOP mode.
+  * @retval The actual applied SVOS selection.
+  */
+uint32_t HAL_PWREx_GetStopModeVoltageRange(void)
+{
+  /* Return the stop voltage scaling */
+  return (PWR->CPUCR & PWR_CPUCR_SVOS);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group2 Wakeup Pins configuration functions
+  * @brief     Wakeup Pins configuration functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Wakeup Pins configuration functions #####
+ ===============================================================================
+    [..]
+
+    *** Wakeup Pins configuration ****
+    ===================================
+    [..]
+      Wakeup pins allow the system to exit from Standby mode. The configuration
+      of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
+      function with:
+       (+) sPinParams: structure to enable and configure a wakeup pin:
+        (++) WakeUpPin: Wakeup pin to be enabled.
+        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
+        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
+    [..]
+      The wakeup pins are internally connected to the EXTI lines [60-63] to
+      generate an interrupt if enabled.
+    [..]
+      When a wakeup pin event is received the HAL_PWR_WAKEUP_PIN_IRQHandler is
+      called and the appropriate flag is set in the PWR_WKUPSR register. Then in
+      the HAL_PWR_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
+      cleared and the appropriate user callback will be called. The user can add
+      his own code by customization of function pointer HAL_PWR_WKUPx_Callback.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief Enable the Wake-up PINx functionality.
+  * @param  sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
+  *                      contains the configuration information for the wake-up
+  *                      Pin.
+  * @retval None.
+  */
+void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams)
+{
+  uint32_t pinConfig;
+  uint32_t regMask;
+  const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin));
+  assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity));
+  assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull));
+
+  pinConfig = sPinParams->WakeUpPin | \
+              (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
+              (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + \
+                                        PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
+
+  regMask   = sPinParams->WakeUpPin | \
+              (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
+              (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
+
+  /* Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge) */
+  MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig);
+
+  /* Configure the Wakeup Pin EXTI Line */
+  MODIFY_REG(EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM60_Pos));
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_Exported_Functions_Group3 Memories Retention Functions
+  * @brief    Memories Retention Functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Memories Retention Functions #####
+ ===============================================================================
+    [..]
+
+    *** Backup RAM (BKPSRAM) retention ****
+    =======================================
+    [..]
+      By default the content of BKPSRAM memories aren't retained in Standby mode.
+      By setting the BKPRBSEN bit in the PWR_BDCR2 register using the
+      HAL_PWREx_EnableBkupRAMRetention() function, the content of these memories
+      are retained even in Standby mode.
+
+    *** TCM RAMs and I-TCM FLEXMEM retention ****
+    =======================================
+    [..]
+      By default the content of TCM RAMs and I-TCM FLEXMEM aren't retained in
+      Standby mode.
+
+      By setting the TCMRBSEN bit in the PWR_CR4 register using the
+      HAL_PWREx_EnableTCMRetention() function, the content of these memories
+      are retained even in Standby mode.
+
+      By setting the TCMFLXRBSEN bit in the PWR_CR4 register using the
+      HAL_PWREx_EnableTCMFLXRetention () function, the content of these memories
+      are retained even in Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Backup RAM retention in Standby and VBAT modes.
+  * @note  After reset, PWR_BDCR2 is write-protected.
+  *        DBP must be set in PWR_DBPCR to disable the write protection.
+  * @retval None.
+  */
+void HAL_PWREx_EnableBkupRAMRetention(void)
+{
+  SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
+}
+
+/**
+  * @brief  Disable the Backup RAM retention in Standby and VBAT modes.
+  * @note  After reset, PWR_BDCR2 is write-protected.
+  *        DBP must be set in PWR_DBPCR to disable the write protection.
+  * @retval None.
+  */
+void HAL_PWREx_DisableBkupRAMRetention(void)
+{
+  CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
+}
+
+/**
+  * @brief Enable the TCM RAMs retention in Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableTCMRetention(void)
+{
+  SET_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
+}
+
+/**
+  * @brief Disable the TCM RAMs retention in Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableTCMRetention(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
+}
+
+/**
+  * @brief Enable the I-TCM FLEXMEM retention in Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableTCMFLXRetention(void)
+{
+  SET_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
+}
+
+/**
+  * @brief Disable the I-TCM FLEXMEM retention in Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableTCMFLXRetention(void)
+{
+  CLEAR_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_Exported_Functions_Group4 Low Power Control Functions
+  * @brief    Low Power Control Functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Low Power Control Functions #####
+ ===============================================================================
+    [..]
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure the pwr_on pulse low configuration.
+  * @param  Pulselowtime : Specifies minimum guaranteed duration of
+                           the pwr_on low pulse in Standby mode.
+  *          This parameter can be a value between 0 and 31:
+  *            0: No guaranteed minimum low time.
+  *            1: 1* 32 LSI cycles= ~ 1 ms guaranteed minimum low time.
+  *            X: X* 32 LSI cycles= ~ X ms guaranteed minimum low time.
+  * @retval None.
+  */
+void HAL_PWREx_SetPulseLow(uint32_t Pulselowtime)
+{
+  assert_param(IS_PWR_PULSE_LOW_TIME(Pulselowtime));
+
+  /* Set the pwr_on pulse low configuration */
+  MODIFY_REG(PWR->CR1, PWR_CR1_POPL_Msk, (Pulselowtime << PWR_CR1_POPL_Pos));
+}
+
+/**
+  * @brief Get the pwr_on pulse low configuration.
+  * @retval The actual applied minimum guaranteed duration of the
+  *         pwr_on low pulse in Standby mode.
+  */
+uint32_t HAL_PWREx_GetPulseLow(void)
+{
+  /* Return the stop voltage scaling */
+  return ((PWR->CR1 & PWR_CR1_POPL_Msk) >> PWR_CR1_POPL_Pos);
+}
+
+/**
+  * @brief  Enable SMPS low-power mode (SVOS range 3 only).
+  * @note   LPDS08V bit is used to keep the SMPS in PWM mode (MR) in Stop SVOS range 3.
+  * @retval None.
+  */
+void HAL_PWREx_EnableSMPSPWM(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_LPDS08V);
+}
+
+/**
+  * @brief  Disable SMPS low-power mode (SVOS range 3 only).
+  * @retval None.
+  */
+void HAL_PWREx_DisableSMPSPWM(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS08V);
+}
+
+/**
+  * @brief  Enable the pull down on output voltage during power-down mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnablePullDownOutput(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
+}
+
+/**
+  * @brief  Disable the pull down on output voltage during power-down mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisablePullDownOutput(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group5 Power Monitoring functions
+  * @brief    Power Monitoring functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Power Monitoring functions #####
+ ===============================================================================
+
+    *** VBAT and Temperature supervision ***
+    ========================================
+    [..]
+      (+) The VBAT battery voltage supply can be monitored by comparing it with
+          two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
+          in the PWR control register 2 (PWR_BDCR1), indicate if VBAT is higher or
+          lower than the threshold.
+      (+) The temperature can be monitored by comparing it with two threshold
+          levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
+          control register 2 (PWR_BDCR1), indicate whether the device temperature
+          is higher or lower than the threshold.
+      (+) The VBAT and the temperature monitoring is enabled by
+          HAL_PWREx_EnableMonitoring() function and disabled by
+          HAL_PWREx_DisableMonitoring() function.
+      (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
+          be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
+          PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
+      (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
+          level which can be :
+          PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
+          PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the VBAT and temperature monitoring.
+  * @note  After reset, PWR_BDCR1 is write-protected.
+  *        DBP must be set in PWR_DBPCR to disable the write protection.
+  * @retval HAL status.
+  */
+void HAL_PWREx_EnableMonitoring(void)
+{
+  /* Enable the VBAT and Temperature monitoring */
+  SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+  * @brief Disable the VBAT and temperature monitoring.
+  * @note  After reset, PWR_BDCR1 is write-protected.
+  *        DBP must be set in PWR_DBPCR to disable the write protection.
+  * @retval HAL status.
+  */
+void HAL_PWREx_DisableMonitoring(void)
+{
+  /* Disable the VBAT and Temperature monitoring */
+  CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
+}
+
+/**
+  * @brief Indicate whether the junction temperature is between, above or below
+  *        the thresholds.
+  * @retval Temperature level.
+  */
+uint32_t HAL_PWREx_GetTemperatureLevel(void)
+{
+  uint32_t tempLevel;
+  uint32_t regValue;
+
+  /* Read the temperature flags */
+  regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_TEMPH | PWR_BDCR1_TEMPL));
+
+  /* Check if the temperature is below the threshold */
+  if (regValue == PWR_BDCR1_TEMPL)
+  {
+    tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the temperature is above the threshold */
+  else if (regValue == PWR_BDCR1_TEMPH)
+  {
+    tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The temperature is between the thresholds */
+  else
+  {
+    tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return tempLevel;
+}
+
+/**
+  * @brief Indicate whether the Battery voltage level is between, above or below
+  *        the thresholds.
+  * @retval VBAT level.
+  */
+uint32_t HAL_PWREx_GetVBATLevel(void)
+{
+  uint32_t vbatLevel;
+  uint32_t regValue;
+
+  /* Read the VBAT flags */
+  regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_VBATH | PWR_BDCR1_VBATL));
+
+  /* Check if the VBAT is below the threshold */
+  if (regValue == PWR_BDCR1_VBATL)
+  {
+    vbatLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the VBAT is above the threshold */
+  else if (regValue == PWR_BDCR1_VBATH)
+  {
+    vbatLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The VBAT is between the thresholds */
+  else
+  {
+    vbatLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return vbatLevel;
+}
+
+/**
+  * @brief Enable the VDDCORE monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_EnableVDDCOREMonitoring(void)
+{
+  /* Enable the VDDCORE monitoring */
+  SET_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
+}
+
+/**
+  * @brief Disable the VDDCORE monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_DisableVDDCOREMonitoring(void)
+{
+  /* Disable the VDDCORE monitoring */
+  CLEAR_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
+}
+
+/**
+  * @brief  Configure the VDDCORE voltage detector low-level selection.
+  * @param  pConfigVddCOREVM : Pointer to a PWR_VddCOREVMTypeDef structure that contains the
+  *                            PVM configuration information (LowVoltageThreshold and Mode).
+  * @retval None.
+  */
+void HAL_PWREx_ConfigVDDCOREVM(const PWR_VddCOREVMTypeDef *pConfigVddCOREVM)
+{
+  assert_param(IS_PWR_VDDCOREVM_LEVEL(pConfigVddCOREVM->LowVoltageThreshold));
+  assert_param(IS_PWR_VDDCOREVM_MODE(pConfigVddCOREVM->Mode));
+
+  /* Disable VDDCORE monitoring Event/Interrupt */
+  __HAL_PWR_VCOREVM_EXTI_DISABLE_EVENT();
+  __HAL_PWR_VCOREVM_EXTI_DISABLE_IT();
+  __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_EDGE();
+  __HAL_PWR_VCOREVM_EXTI_DISABLE_FALLING_EDGE();
+
+  /* Set the VDDCORE voltage detector low-level selection */
+  MODIFY_REG(PWR->CR3, PWR_CR3_VCORELLS_Msk, pConfigVddCOREVM->LowVoltageThreshold);
+
+  /* Configure the VDDCORE monitoring in interrupt mode */
+  if ((pConfigVddCOREVM->Mode & VDDCOREVM_MODE_IT) == VDDCOREVM_MODE_IT)
+  {
+    __HAL_PWR_VCOREVM_EXTI_ENABLE_IT();
+  }
+
+  /* Configure the VDDCORE monitoring in event mode */
+  if ((pConfigVddCOREVM->Mode & VDDCOREVM_MODE_EVT) == VDDCOREVM_MODE_EVT)
+  {
+    __HAL_PWR_VCOREVM_EXTI_ENABLE_EVENT();
+  }
+
+  /* Rising edge configuration */
+  if ((pConfigVddCOREVM->Mode & VDDCOREVM_RISING_EDGE) == VDDCOREVM_RISING_EDGE)
+  {
+    __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_EDGE();
+  }
+
+  /* Falling edge configuration */
+  if ((pConfigVddCOREVM->Mode & VDDCOREVM_FALLING_EDGE) == VDDCOREVM_FALLING_EDGE)
+  {
+    __HAL_PWR_VCOREVM_EXTI_ENABLE_FALLING_EDGE();
+  }
+}
+
+/**
+  * @brief Indicate whether the VDDCORE level is between, above or below
+  *        the thresholds.
+  * @retval VDDCORE level.
+  */
+uint32_t HAL_PWREx_GetVDDCORELevel(void)
+{
+  uint32_t vcoreLevel;
+  uint32_t regValue;
+
+  /* Read the VCORE flags */
+  regValue = READ_BIT(PWR->CR3, (PWR_CR3_VCOREH | PWR_CR3_VCOREL));
+
+  /* Check if the VCORE is below the threshold */
+  if (regValue == PWR_CR3_VCOREL)
+  {
+    vcoreLevel = PWR_VDDCORE_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the VCORE is above the threshold */
+  else if (regValue == PWR_CR3_VCOREH)
+  {
+    vcoreLevel = PWR_VDDCORE_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The VCORE is between the thresholds */
+  else
+  {
+    vcoreLevel = PWR_VDDCORE_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return vcoreLevel;
+}
+
+/**
+  * @brief  Configure the VDD I/O voltage range.
+  * @param  VddIOPort VDD I/O
+  *         This parameter can be one of the following values:
+  *           @arg @ref PWR_VDDIO           Vdd IO
+  *           @arg @ref PWR_VDDIO2          Vdd IO2
+  *           @arg @ref PWR_VDDIO3          Vdd IO3
+  *           @arg @ref PWR_VDDIO4          Vdd IO4
+  *           @arg @ref PWR_VDDIO5          Vdd IO5
+  * @param  VoltageRange Voltage range
+  *         This parameter can be one of the following values:
+  *           @arg @ref PWR_VDDIO_RANGE_3V3   3v3 voltage range
+  *           @arg @ref PWR_VDDIO_RANGE_1V8   1v8 voltage range
+  * @note   HSLV_VDDIOx option bit must be set to allow 1v8 voltage
+  *         range operation.
+  * @note   Setting this configuration while VDDIOx is in 3v3 range
+  *         damages the device.
+  * @retval None.
+  */
+void HAL_PWREx_ConfigVddIORange(uint32_t VddIOPort, uint32_t VoltageRange)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_VDDIO(VddIOPort));
+  assert_param(IS_PWR_VDDIO_RANGE(VoltageRange));
+
+  switch (VddIOPort)
+  {
+    case PWR_VDDIO:
+      MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL, VoltageRange << PWR_SVMCR3_VDDIOVRSEL_Pos);
+      break;
+
+    case PWR_VDDIO2:
+      MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL, VoltageRange << PWR_SVMCR3_VDDIO2VRSEL_Pos);
+      break;
+
+    case PWR_VDDIO3:
+      MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL, VoltageRange << PWR_SVMCR3_VDDIO3VRSEL_Pos);
+      break;
+
+    case PWR_VDDIO4:
+      MODIFY_REG(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL, VoltageRange << PWR_SVMCR1_VDDIO4VRSEL_Pos);
+      break;
+
+    case PWR_VDDIO5:
+      MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos);
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Configure the VDD I/O voltage range.
+  * @param  VddIOPort VDD I/O
+  *         This parameter can be one of the following values:
+  *           @arg @ref PWR_VDDIO           Vdd IO
+  *           @arg @ref PWR_VDDIO2          Vdd IO2
+  *           @arg @ref PWR_VDDIO3          Vdd IO3
+  *           @arg @ref PWR_VDDIO4          Vdd IO4
+  *           @arg @ref PWR_VDDIO5          Vdd IO5
+  * @retval The voltage range:
+  *           @arg @ref PWR_VDDIO_RANGE_3V3   3v3 voltage range
+  *           @arg @ref PWR_VDDIO_RANGE_1V8   1v8 voltage range
+  */
+uint32_t HAL_PWREx_GetVddIORange(uint32_t VddIOPort)
+{
+  uint32_t voltage_range = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_VDDIO(VddIOPort));
+
+  switch (VddIOPort)
+  {
+    case PWR_VDDIO:
+      voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL) >> PWR_SVMCR3_VDDIOVRSEL_Pos);
+      break;
+
+    case PWR_VDDIO2:
+      voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL) >> PWR_SVMCR3_VDDIO2VRSEL_Pos);
+      break;
+
+    case PWR_VDDIO3:
+      voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL) >> PWR_SVMCR3_VDDIO3VRSEL_Pos);
+      break;
+
+    case PWR_VDDIO4:
+      voltage_range = (READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL) >> PWR_SVMCR1_VDDIO4VRSEL_Pos);
+      break;
+
+    case PWR_VDDIO5:
+      voltage_range = (READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos);
+      break;
+
+    default:
+      break;
+  }
+  return voltage_range;
+}
+
+/**
+  * @brief  Enable VDD IO4 voltage range Standby mode.
+  * @note   When this bit is set, the VDDIO4VRSEL configuration
+  *         is retained in Standby mode.
+  * @note   This bit must be set if the VDDIO4 is in 1v8 range
+  *         in Standby mode, and when exiting Standby mode.
+  * @note   It must not be set when VDDIO4 is in 3v3 range in
+  *         Standby mode, or when exiting Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO4RangeSTBY(void)
+{
+  SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
+}
+
+/**
+  * @brief  Disable VDD IO4 voltage range Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO4RangeSTBY(void)
+{
+  CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
+}
+
+/**
+  * @brief  Enable VDD IO5 voltage range Standby mode.
+  * @note   When this bit is set, the VDDIO5VRSEL configuration
+  *         is retained in Standby mode.
+  * @note   This bit must be set if the VDDIO5 is in 1v8 range
+  *         in Standby mode, and when exiting Standby mode.
+  * @note   It must not be set when VDDIO5 is in 3v3 range in
+  *         Standby mode, or when exiting Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO5RangeSTBY(void)
+{
+  SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
+}
+
+/**
+  * @brief  Disable VDD IO5 voltage range Standby mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO5RangeSTBY(void)
+{
+  CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
+}
+
+/**
+  * @brief  Enable VDDUSB supply valid.
+  * @note   Setting this bit is mandatory to use the USB2 HS PHYs.
+  *         is present for consumption saving.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddUSB(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
+}
+
+/**
+  * @brief  Disable VDDUSB supply valid.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddUSB(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
+}
+
+/**
+  * @brief  Enable VDDIO2 supply valid.
+  * @note   Setting this bit is mandatory to use PO[5:0] and PP[15:0] I/Os.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO2(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
+}
+
+/**
+  * @brief  Disable VDDIO2 supply valid.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO2(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
+}
+
+/**
+  * @brief  Enable VDDIO3 supply valid.
+  * @note   Setting this bit is mandatory to use PN[12:0] I/Os.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO3(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
+}
+
+/**
+  * @brief  Disable VDDIO3 supply valid.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO3(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
+}
+
+/**
+  * @brief  Enable VDDIO4 supply valid.
+  * @note   Setting this bit is mandatory to use PB[9,8], PC[12:6], and PD[2] I/Os.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO4(void)
+{
+  SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
+}
+
+/**
+  * @brief  Disable VDDIO4 supply valid.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO4(void)
+{
+  CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
+}
+
+/**
+  * @brief  Enable VDDIO5 supply valid.
+  * @note   Setting this bit is mandatory to use PN[12:0] I/Os.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO5(void)
+{
+  SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
+}
+
+/**
+  * @brief  Disable VDDIO5 supply valid.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO5(void)
+{
+  CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
+}
+
+/**
+  * @brief  Enable VDDA supply valid.
+  * @note   Setting this bit is mandatory to use the analog to digital converters.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddA(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
+}
+
+/**
+  * @brief  Disable VDDA supply valid.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddA(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
+}
+
+/**
+  * @brief  Enable the VDD33USB independent USB 33 voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddUSBVMEN(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
+}
+
+/**
+  * @brief  Disable the VDD33USB independent USB 33 voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddUSBVMEN(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
+}
+
+/**
+  * @brief  Enable the VDDIO2 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO2VMEN(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
+}
+
+/**
+  * @brief  Disable the VDDIO2 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO2VMEN(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
+}
+
+/**
+  * @brief  Enable the VDDIO3 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO3VMEN(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
+}
+
+/**
+  * @brief  Disable the VDDIO3 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO3VMEN(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
+}
+
+/**
+  * @brief  Enable the VDDIO4 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO4VMEN(void)
+{
+  SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
+}
+
+/**
+  * @brief  Disable the VDDIO4 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO4VMEN(void)
+{
+  CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
+}
+
+/**
+  * @brief  Enable the VDDIO5 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddIO5VMEN(void)
+{
+  SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
+}
+
+/**
+  * @brief  Disable the VDDIO5 independent voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddIO5VMEN(void)
+{
+  CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
+}
+
+/**
+  * @brief  Enable the VDDA18ADC independent ADC voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableVddAVMEN(void)
+{
+  SET_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
+}
+
+/**
+  * @brief  Disable the VDDA18ADC independent ADC voltage monitor.
+  * @retval None.
+  */
+void HAL_PWREx_DisableVddAVMEN(void)
+{
+  CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
+}
+
+/**
+  * @brief  Configure the voltage monitor threshold detected by the Peripheral
+  *         voltage monitoring (PVM).
+  * @param  pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the
+  *                      PVM configuration information (PVMType and EventMode).
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *pConfigPVM)
+{
+
+  /* Check the parameters */
+  assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType));
+  assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode));
+
+  /* Check the peripheral voltage monitor type */
+  switch (pConfigPVM->PVMType)
+  {
+    case PWR_VDDUSB_VM: /* Independent USB voltage monitor */
+
+      /* Disable EXTI USBVM event and interrupt */
+      __HAL_PWR_USBVM_EXTI_DISABLE_EVENT();
+      __HAL_PWR_USBVM_EXTI_DISABLE_IT();
+      __HAL_PWR_USBVM_EXTI_DISABLE_RISING_EDGE();
+      __HAL_PWR_USBVM_EXTI_DISABLE_FALLING_EDGE();
+
+      /* Configure the USBVM in interrupt mode */
+      if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_USBVM_EXTI_ENABLE_IT();
+      }
+
+      /* Configure the USBVM in event mode */
+      if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_USBVM_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the USBVM in rising edge */
+      if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      /* Configure the USBVM in falling edge */
+      if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    case PWR_VDDIO2_VM: /* Independent I/Os voltage monitor */
+
+      /* Disable EXTI IO2VM event and interrupt */
+      __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT();
+      __HAL_PWR_IO2VM_EXTI_DISABLE_IT();
+      __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE();
+      __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE();
+
+      /* Configure the IO2VM in interrupt mode */
+      if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_IO2VM_EXTI_ENABLE_IT();
+      }
+
+      /* Configure the IO2VM in event mode */
+      if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the IO2VM in rising edge */
+      if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      /* Configure the IO2VM in falling edge */
+      if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    case PWR_VDDIO3_VM: /* Independent I/Os voltage monitor */
+
+      /* Disable EXTI IO3VM event and interrupt */
+      __HAL_PWR_IO3VM_EXTI_DISABLE_EVENT();
+      __HAL_PWR_IO3VM_EXTI_DISABLE_IT();
+      __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_EDGE();
+      __HAL_PWR_IO3VM_EXTI_DISABLE_FALLING_EDGE();
+
+      /* Configure the IO3VM in interrupt mode */
+      if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_IO3VM_EXTI_ENABLE_IT();
+      }
+
+      /* Configure the IO3VM in event mode */
+      if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_IO3VM_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the IO3VM in rising edge */
+      if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      /* Configure the IO3VM in falling edge */
+      if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_IO3VM_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    case PWR_VDDIO4_VM: /* Independent I/Os voltage monitor */
+
+      /* Disable EXTI IO4VM event and interrupt */
+      __HAL_PWR_IO4VM_EXTI_DISABLE_EVENT();
+      __HAL_PWR_IO4VM_EXTI_DISABLE_IT();
+      __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_EDGE();
+      __HAL_PWR_IO4VM_EXTI_DISABLE_FALLING_EDGE();
+
+      /* Configure the IO4VM in interrupt mode */
+      if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_IO4VM_EXTI_ENABLE_IT();
+      }
+
+      /* Configure the IO4VM in event mode */
+      if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_IO4VM_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the IO4VM in rising edge */
+      if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      /* Configure the IO4VM in falling edge */
+      if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_IO4VM_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    case PWR_VDDIO5_VM: /* Independent I/Os voltage monitor */
+
+      /* Disable EXTI IO5VM event and interrupt */
+      __HAL_PWR_IO5VM_EXTI_DISABLE_EVENT();
+      __HAL_PWR_IO5VM_EXTI_DISABLE_IT();
+      __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_EDGE();
+      __HAL_PWR_IO5VM_EXTI_DISABLE_FALLING_EDGE();
+
+      /* Configure the IO5VM in interrupt mode */
+      if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_IO5VM_EXTI_ENABLE_IT();
+      }
+
+      /* Configure the IO5VM in event mode */
+      if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_IO5VM_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the IO5VM in rising edge */
+      if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      /* Configure the IO5VM in falling edge */
+      if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_IO5VM_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    case PWR_VDDA_VM: /* Independent ADC voltage monitor */
+
+      /* Disable EXTI ADCVM event and interrupt */
+      __HAL_PWR_ADCVM_EXTI_DISABLE_EVENT();
+      __HAL_PWR_ADCVM_EXTI_DISABLE_IT();
+      __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_EDGE();
+      __HAL_PWR_ADCVM_EXTI_DISABLE_FALLING_EDGE();
+
+      /* Configure the ADCVM in interrupt mode */
+      if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
+      {
+        __HAL_PWR_ADCVM_EXTI_ENABLE_IT();
+      }
+
+      /* Configure the ADCVM in event mode */
+      if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
+      {
+        __HAL_PWR_ADCVM_EXTI_ENABLE_EVENT();
+      }
+
+      /* Configure the ADCVM in rising edge */
+      if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
+      {
+        __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_EDGE();
+      }
+
+      /* Configure the ADCVM in falling edge */
+      if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
+      {
+        __HAL_PWR_ADCVM_EXTI_ENABLE_FALLING_EDGE();
+      }
+      break;
+
+    default: /* No valid voltage monitor selected */
+      return HAL_ERROR;
+      break;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles the PWR PVD/PVM interrupt request.
+  * @retval None.
+  */
+void HAL_PWREx_PVD_PVM_IRQHandler(void)
+{
+  uint32_t  rising_flag;
+  uint32_t  falling_flag;
+
+  rising_flag  = READ_REG(EXTI->RPR3);
+  falling_flag = READ_REG(EXTI->FPR3);
+
+  /* Check PWR VDDCORE monitoring exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_VCOREVM) != 0U)
+  {
+    /* Clear VDDCORE monitoring exti pending bit */
+    __HAL_PWR_VCOREVM_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR VDDCORE monitoring interrupt rising user callback */
+    HAL_PWREx_VDDCORE_Rising_Callback();
+  }
+
+  /* Check PWR VDDCORE monitoring exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_VCOREVM) != 0U)
+  {
+    /* Clear VDDCORE monitoring exti pending bit */
+    __HAL_PWR_VCOREVM_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR VDDCORE monitoring interrupt falling user callback */
+    HAL_PWREx_VDDCORE_Falling_Callback();
+  }
+
+  /* Check PWR PVD exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_PVD) != 0U)
+  {
+    /* Clear PVD exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR PVD interrupt rising user callback */
+    HAL_PWR_PVD_Rising_Callback();
+  }
+
+  /* Check PWR PVD exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_PVD) != 0U)
+  {
+    /* Clear PVD exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR PVD interrupt falling user callback */
+    HAL_PWR_PVD_Falling_Callback();
+  }
+
+  /* Check PWR PVM USB exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_PVM_VDDUSB) != 0U)
+  {
+    /* Clear PVM USB exti pending bit */
+    __HAL_PWR_USBVM_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR PVM USB interrupt rising user callback */
+    HAL_PWREx_USBVM_Rising_Callback();
+  }
+
+  /* Check PWR PVM USB exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_PVM_VDDUSB) != 0U)
+  {
+    /* Clear PVM USB exti pending bit */
+    __HAL_PWR_USBVM_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR PVM USB interrupt falling user callback */
+    HAL_PWREx_USBVM_Falling_Callback();
+  }
+
+  /* Check PWR PVM IO2 exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO2) != 0U)
+  {
+    /* Clear PVM IO2 exti pending bit */
+    __HAL_PWR_IO2VM_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR PVM IO2 interrupt rising user callback */
+    HAL_PWREx_IO2VM_Rising_Callback();
+  }
+
+  /* Check PWR PVM IO2 exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO2) != 0U)
+  {
+    /* Clear PVM IO2 exti pending bit */
+    __HAL_PWR_IO2VM_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR PVM IO2 interrupt falling user callback */
+    HAL_PWREx_IO2VM_Falling_Callback();
+  }
+
+  /* Check PWR PVM IO3 exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO3) != 0U)
+  {
+    /* Clear PVM IO3 exti pending bit */
+    __HAL_PWR_IO3VM_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR PVM IO3 interrupt rising user callback */
+    HAL_PWREx_IO3VM_Rising_Callback();
+  }
+
+  /* Check PWR PVM IO3 exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO3) != 0U)
+  {
+    /* Clear PVM IO3 exti pending bit */
+    __HAL_PWR_IO3VM_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR PVM IO3 interrupt falling user callback */
+    HAL_PWREx_IO3VM_Falling_Callback();
+  }
+
+  /* Check PWR PVM IO4 exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO4) != 0U)
+  {
+    /* Clear PVM IO4 exti pending bit */
+    __HAL_PWR_IO4VM_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR PVM IO4 interrupt rising user callback */
+    HAL_PWREx_IO4VM_Rising_Callback();
+  }
+
+  /* Check PWR PVM IO4 exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO4) != 0U)
+  {
+    /* Clear PVM IO4 exti pending bit */
+    __HAL_PWR_IO4VM_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR PVM IO4 interrupt falling user callback */
+    HAL_PWREx_IO4VM_Falling_Callback();
+  }
+
+  /* Check PWR PVM IO5 exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO5) != 0U)
+  {
+    /* Clear PVM IO5 exti pending bit */
+    __HAL_PWR_IO5VM_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR PVM IO5 interrupt rising user callback */
+    HAL_PWREx_IO5VM_Rising_Callback();
+  }
+
+  /* Check PWR PVM IO5 exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO5) != 0U)
+  {
+    /* Clear PVM IO5 exti pending bit */
+    __HAL_PWR_IO5VM_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR PVM IO5 interrupt falling user callback */
+    HAL_PWREx_IO5VM_Falling_Callback();
+
+  }
+
+  /* Check PWR PVM ADC VM exti rising flag */
+  if ((rising_flag & PWR_EXTI_LINE_PVM_VDDA) != 0U)
+  {
+    /* Clear PVM ADC VM exti pending bit */
+    __HAL_PWR_ADCVM_EXTI_CLEAR_RISING_FLAG();
+
+    /* PWR PVM ADC VM interrupt rising user callback */
+    HAL_PWREx_ADCVM_Rising_Callback();
+  }
+
+  /* Check PWR PVM ADC VM exti falling flag */
+  if ((falling_flag & PWR_EXTI_LINE_PVM_VDDA) != 0U)
+  {
+    /* Clear PVM ADC VM exti pending bit */
+    __HAL_PWR_ADCVM_EXTI_CLEAR_FALLING_FLAG();
+
+    /* PWR PVM ADC VM interrupt falling user callback */
+    HAL_PWREx_ADCVM_Falling_Callback();
+  }
+}
+
+/**
+  * @brief  PWR VDDCORE interrupt Rising callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_VDDCORE_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_VDDCORE_Rising_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR VDDCORE interrupt Falling callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_VDDCORE_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_VDDCORE_Falling_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR USBVM interrupt Rising callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_USBVM_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_USBVM_Rising_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR USBVM interrupt Falling callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_USBVM_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_USBVM_Falling_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO2VM interrupt Rising callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO2VM_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO2VM_Rising_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO2VM interrupt Falling callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO2VM_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO2VM_Falling_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO3VM interrupt Rising callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO3VM_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO3VM_Rising_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO3VM interrupt Falling callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO3VM_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO3VM_Falling_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO4VM interrupt Rising callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO4VM_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO4VM_Rising_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO4VM interrupt Falling callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO4VM_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO4VM_Falling_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO5VM interrupt Rising callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO5VM_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO5VM_Rising_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR IO5VM interrupt Falling callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_IO5VM_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_IO5VM_Falling_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR ADCVM interrupt Rising callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_ADCVM_Rising_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_ADCVM_Rising_Callback() API can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWR ADCVM interrupt Falling callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_ADCVM_Falling_Callback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_PWREx_ADCVM_Falling_Callback() API can be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#endif /* defined (HAL_PWR_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ramcfg.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ramcfg.c
new file mode 100644
index 000000000..e6123a304
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_ramcfg.c
@@ -0,0 +1,1072 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_ramcfg.c
+  * @author  GPM Application Team
+  * @brief   RAMCFG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the RAMs configuration controller peripheral:
+  *           + RAMCFG Initialization and De-initialization Functions.
+  *           + RAMCFG ECC Operation Functions.
+  *           + RAMCFG Erase Operation Functions.
+  *           + RAMCFG Handle Interrupt and Callbacks Functions.
+  *           + RAMCFG State and Error Functions.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### RAMCFG Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each SRAM is managed by a RAMCFG instance (AHBSRAM1/2, AXISRAM1 to 6,
+        BKPSRAM, FLEXRAM, and VENCRAM).
+
+    (+) Each SRAM can be erased independently through its RAMCFG instance.
+
+    (+) AXISRAM 1 to 6 are the main SRAMs. AHBSRAM1/2 are preferably for DMA-controlled
+        peripheral-to-memory data flow.
+        AXISRAM 2 to 6 can be shut down when the application is in Run mode.
+
+    (+) FLEXMEM can be either allocated as Cortex-M55 TCM, or as system RAM
+        (FLEXRAM).
+        80 Kbytes of the FLEXMEM are retained in Standby mode, either allocated as
+        extended ITCM (64 +16-Kbyte ECC), or allocated as FLEXRAM.
+
+    (+) The BKPSRAM content is retained in low-power modes, even when VDD is off
+        in VBAT mode. On a tamper event detection, the BKPSRAM content is erased.
+
+    (+) The VENCRAM implements hardware and software erases.
+
+    (+) FLEXRAM and BKPRAM support ECC correction feature:
+             (++) Single error detection and correction with interrupt generation.
+             (++) Double error detection with interrupt generation.
+             (++) Status with failing address
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Call HAL_RAMCFG_Init() to initialize the RAMCFG peripheral before using
+       any feature. Call HAL_RAMCFG_DeInit() to de-initialize the RAMCFG when
+       using this peripheral is no more needed or a hardware issue has occurred.
+          (+) HAL_RAMCFG_Init() and HAL_RAMCFG_DeInit() APIs do not change the
+              activation status of ECC feature. It is managed by
+              HAL_RAMCFG_StartECC(), HAL_RAMCFG_StopECC() or option bytes (When
+              available on the device).
+
+     *** ECC feature ***
+     ===================
+    [..]
+          (+) Call HAL_RAMCFG_StartECC() and HAL_RAMCFG_StopECC() to enable and
+              disable ECC hardware mechanism.
+                    (++) When ECC feature is previously enabled (case of option
+                         byte activation), calling HAL_RAMCFG_StartECC() is
+                         recommended to enable the ECC address latching feature.
+
+          (+) Call HAL_RAMCFG_EnableNotification() and HAL_RAMCFG_DisableNotification()
+              to enable and disable ECC interrupts. Interrupts can be:
+                    (++) Single error interrupt.
+                    (++) Double error interrupt.
+                    (++) Double error interrupt redirected to Non maskable
+                          interrupt (NMI).
+
+          (+) Call HAL_RAMCFG_GetSingleErrorAddress() to get the address of the
+              last fail RAM word detected (only for single error) and
+              call HAL_RAMCFG_GetDoubleErrorAddress() to get the address of the
+              last fail RAM word detected (only for double error).
+
+          (+) Call HAL_RAMCFG_IsECCSingleErrorDetected() to check if an ECC single
+              error was detected.
+              Call HAL_RAMCFG_IsECCDoubleErrorDetected() to check if an ECC double
+              error was detected.
+              These APIs are used in silent mode (No ECC interrupt
+              is enabled).
+
+     *** Erase feature ***
+     =====================
+    [..]
+          (+) Call HAL_RAMCFG_Erase() to launch a hardware erase for the given
+              SRAM.
+
+          (+) The erase value is equal to 0 when launching erase hardware through
+              RAMCFG.
+
+          (+) SRAM2 write protected pages are erased when performing an erase
+              through RAMCFG.
+
+     *** RAMCFG HAL driver macros list ***
+     =====================================
+     [..]
+       Below the list of used macros in RAMCFG HAL driver.
+
+      (+) __HAL_RAMCFG_ENABLE_IT     : Enable the specified RAMCFG interrupts.
+      (+) __HAL_RAMCFG_DISABLE_IT    : Disable the specified RAMCFG interrupts.
+      (+) __HAL_RAMCFG_GET_FLAG      : Get the RAMCFG pending flags.
+      (+) __HAL_RAMCFG_CLEAR_FLAG    : Clear the RAMCFG pending flags.
+      (+) __HAL_RAMCFG_GET_IT_SOURCE : Check whether the specified RAMCFG
+                                       interrupt source is enabled or not.
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RAMCFG RAMCFG
+  * @brief RAMCFG HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup RAMCFG_Private_Constants
+  * @{
+  */
+#define RAMCFG_TIMEOUT_VALUE 50000U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RAMCFG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization Functions  #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to initialize and de-initialize the
+      RAMCFG instance.
+    [..]
+      The HAL_RAMCFG_Init() function follows the RAMCFG instance configuration
+      procedures as described in the reference manual.
+      The HAL_RAMCFG_DeInit() function allows to deinitialize the RAMCFG instance.
+      HAL_RAMCFG_Init() and HAL_RAMCFG_DeInit() APIs do not change the activation
+      status of ECC feature. It is managed by HAL_RAMCFG_StartECC(),
+      HAL_RAMCFG_StopECC() or option bytes (When available on the device).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the RAMCFG by clearing flags and disabling interrupts.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                   the configuration information for the specified RAMCFG
+  *                   instance.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the RAMCFG peripheral handle */
+  if (hramcfg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+  /* Update RAMCFG peripheral state */
+  hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+  /* Check if a valid MSP API was registered */
+  if (hramcfg->MspInitCallback == NULL)
+  {
+    /* Init the low level hardware */
+    hramcfg->MspInitCallback = HAL_RAMCFG_MspInit;
+  }
+
+  /* Init the low level hardware */
+  hramcfg->MspInitCallback(hramcfg);
+#else
+  HAL_RAMCFG_MspInit(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+  /* Disable the ECC Address latch */
+  hramcfg->Instance->CR &= ~(RAMCFG_CR_ALE);
+
+  /* Disable all RAMCFG interrupts */
+  __HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL);
+
+  /* Clear RAMCFG monitor flags */
+  __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL);
+
+  /* Initialize the RAMCFG error code */
+  hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE;
+
+  /* Initialize the RAMCFG state */
+  hramcfg->State = HAL_RAMCFG_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the RAMCFG peripheral.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                   the configuration information for the specified RAMCFG
+  *                   instance.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the RAMCFG peripheral handle */
+  if (hramcfg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+  /* Disable the ECC Address latch */
+  hramcfg->Instance->CR &= ~(RAMCFG_CR_ALE);
+
+  /* Disable all RAMCFG interrupts */
+  __HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL);
+
+  /* Clear RAMCFG monitor flags */
+  __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL);
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+  /* Check if a valid MSP API was registered */
+  if (hramcfg->MspDeInitCallback != NULL)
+  {
+    /* Init the low level hardware */
+    hramcfg->MspDeInitCallback(hramcfg);
+  }
+
+  /* Clean callbacks */
+  hramcfg->DetectSingleErrorCallback = NULL;
+  hramcfg->DetectDoubleErrorCallback = NULL;
+#else
+  HAL_RAMCFG_MspDeInit(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+  /* Reset the RAMCFG error code */
+  hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE;
+
+  /* Reset the RAMCFG state */
+  hramcfg->State = HAL_RAMCFG_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the RAMCFG MSP.
+  * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                  the configuration information for the specified RAMCFG.
+  * @retval None.
+  */
+__weak void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hramcfg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RAMCFG_MspInit can be implemented in the user file      */
+}
+
+/**
+  * @brief DeInitialize the RAMCFG MSP.
+  * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                  the configuration information for the specified RAMCFG.
+  * @retval None.
+  */
+__weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hramcfg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RAMCFG_MspDeInit can be implemented in the user file    */
+}
+/**
+  * @}
+  */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group2
+  *
+@verbatim
+ ===============================================================================
+                      ##### ECC Operations Functions  #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to manage ECC feature provided by
+      the RAMCFG peripheral.
+    [..]
+      The HAL_RAMCFG_StartECC() function allows starting the ECC mechanism and
+      enabling ECC address latching for the selected RAMCFG instance.
+      The HAL_RAMCFG_StopECC() function allows stopping the ECC mechanism and
+      disabling ECC address latching for the selected RAMCFG instance.
+      The HAL_RAMCFG_EnableNotification() function allows enabling interrupts
+      for single ECC error, double ECC error and NMI error.
+      The HAL_RAMCFG_DisableNotification() function allows disabling interrupts
+      for single ECC error, double ECC error. When NMI interrupt is enabled it
+      can only be disabled by a global peripheral reset or by a system reset.
+      The HAL_RAMCFG_IsECCSingleErrorDetected() function allows to check if an
+      single ECC error has occurred.
+      The HAL_RAMCFG_IsECCDoubleErrorDetected() function allows to check if an
+      double ECC error has occurred.
+      The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of
+      the last single ECC error detected.
+      The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of
+      the last double ECC error detected.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start ECC mechanism for the given SRAM.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                   the configuration information for the specified RAMCFG
+  *                   instance.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+  /* Check RAMCFG state */
+  if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+  {
+    /* Update RAMCFG peripheral state */
+    hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+    /* Check if ECC mechanism is non active */
+    if ((hramcfg->Instance->CR & RAMCFG_CR_ECCE) != RAMCFG_CR_ECCE)
+    {
+      /* Start the SRAM ECC mechanism and latching the error address */
+      hramcfg->Instance->CR |= (RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
+    }
+    else
+    {
+      /* Start latching the error address */
+      hramcfg->Instance->CR |= RAMCFG_CR_ALE;
+    }
+
+    /* Update the RAMCFG state */
+    hramcfg->State = HAL_RAMCFG_STATE_READY;
+  }
+  else
+  {
+    /* Update the RAMCFG error code and return error  */
+    hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Stop ECC mechanism for the given SRAM.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                   the configuration information for the specified RAMCFG
+  *                   instance.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+  /* Check RAMCFG state */
+  if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+  {
+    /* Update RAMCFG peripheral state */
+    hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+    /* Check if ECC mechanism is active */
+    if ((hramcfg->Instance->CR & RAMCFG_CR_ECCE) == RAMCFG_CR_ECCE)
+    {
+      /* Unlock the SRAM ECC bit */
+      WRITE_REG(hramcfg->Instance->ECCKEYR, RAMCFG_ECC_KEY1);
+      WRITE_REG(hramcfg->Instance->ECCKEYR, RAMCFG_ECC_KEY2);
+
+      /* Stop the SRAM ECC mechanism and latching the error address */
+      hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
+    }
+    /* Update the RAMCFG state */
+    hramcfg->State = HAL_RAMCFG_STATE_READY;
+  }
+  else
+  {
+    /* Update the RAMCFG error code and return error  */
+    hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable the RAMCFG error interrupts.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @param  Notifications : Select the notification to be enabled.
+  *                         This parameter can be any value of @ref
+  *                         RAMCFG_Interrupt group.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+  assert_param(IS_RAMCFG_INTERRUPT(Notifications));
+
+  /* Check RAMCFG state */
+  if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+  {
+    /* Update RAMCFG peripheral state */
+    hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+    /* Enable RAMCFG interrupts */
+    __HAL_RAMCFG_ENABLE_IT(hramcfg, Notifications);
+
+    /* Update the RAMCFG state */
+    hramcfg->State = HAL_RAMCFG_STATE_READY;
+
+  }
+  else
+  {
+    /* Update the RAMCFG error code and return error */
+    hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Disable the RAMCFG error interrupts.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @param  Notifications : Select the notification to be disabled.
+  *                         This parameter can be :
+  *                         RAMCFG_IT_SINGLEERR : Single Error Interrupt.
+  *                         RAMCFG_IT_DOUBLEERR : Double Error Interrupt.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+  assert_param(IS_RAMCFG_INTERRUPT(Notifications));
+
+  /* Check RAMCFG state */
+  if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+  {
+    /* Update RAMCFG peripheral state */
+    hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+    /* Disable RAMCFG interrupts */
+    __HAL_RAMCFG_DISABLE_IT(hramcfg, Notifications);
+
+    /* Update the RAMCFG state */
+    hramcfg->State = HAL_RAMCFG_STATE_READY;
+  }
+  else
+  {
+    /* Update the RAMCFG error code and return error */
+    hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Check if an ECC single error has occurred.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_RAMCFG_IsECCSingleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+  /* Return the state of SEDC flag */
+  return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_SINGLEERR) == (RAMCFG_FLAG_SINGLEERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if an ECC double error was occurred.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @retval State of bit (1 or 0).
+  */
+uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+  /* Return the state of DED flag */
+  return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_DOUBLEERR) == (RAMCFG_FLAG_DOUBLEERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the RAMCFG single error address.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @retval Single error address offset.
+  */
+uint32_t HAL_RAMCFG_GetSingleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+  return hramcfg->Instance->ESEAR;
+}
+
+/**
+  * @brief  Get the RAMCFG double error address.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @retval Double error address offset.
+  */
+uint32_t HAL_RAMCFG_GetDoubleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
+
+  return hramcfg->Instance->EDEAR;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group5
+  *
+@verbatim
+ ===============================================================================
+                      ##### Erase Operation Functions  #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing a hardware erase for the given SRAM.
+    [..]
+      The HAL_RAMCFG_Erase() function allows a hardware mass erase for the given
+      SRAM. The erase value for all SRAMs is 0.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Launch a Mass Erase for the given SRAM.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+  /* Check RAMCFG state */
+  if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+  {
+    /* Update RAMCFG peripheral state */
+    hramcfg->State = HAL_RAMCFG_STATE_BUSY;
+
+    /* Unlock the RAMCFG erase bit */
+    WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY1);
+    WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY2);
+
+    /* Start the SRAM erase operation */
+    hramcfg->Instance->CR |= RAMCFG_CR_SRAMER;
+
+    /*
+       Wait for the SRAM hardware erase operation to complete by polling on
+       SRAMBUSY flag to be reset.
+    */
+    while (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SRAMBUSY) != 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > RAMCFG_TIMEOUT_VALUE)
+      {
+        /* Update the RAMCFG error code */
+        hramcfg->ErrorCode = HAL_RAMCFG_ERROR_TIMEOUT;
+
+        /* Update the RAMCFG state and return error status */
+        hramcfg->State = HAL_RAMCFG_STATE_ERROR;
+        return HAL_ERROR;
+      }
+    }
+  }
+  else
+  {
+    /* Update the error code and return error status */
+    hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+
+  /* Update the RAMCFG state */
+  hramcfg->State = HAL_RAMCFG_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group6
+  *
+@verbatim
+ ===============================================================================
+               ##### Handle Interrupt and Callbacks Functions  #####
+ ===============================================================================
+    [..]
+      This section provides functions to handle RAMCFG interrupts and
+      Register / UnRegister the different callbacks.
+    [..]
+      The HAL_RAMCFG_IRQHandler() function allows the user to handle the active RAMCFG
+      interrupt request.
+      The HAL_RAMCFG_RegisterCallback() function allows the user to register the selected
+      RAMCFG callbacks.
+      The HAL_RAMCFG_UnRegisterCallback() function allows the user to unregister the
+      selected RAMCFG callbacks.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handles RAMCFG interrupt request.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @retval None.
+  */
+void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Single Error Interrupt Management ****************************************/
+  if (__HAL_RAMCFG_GET_IT_SOURCE(hramcfg, RAMCFG_IT_SINGLEERR) != 0U)
+  {
+    if (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SINGLEERR) != 0U)
+    {
+      /* Clear active flags */
+      __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_SINGLEERR);
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+      /* Check if a valid single error callback is registered */
+      if (hramcfg->DetectSingleErrorCallback != NULL)
+      {
+        /* Single error detection callback */
+        hramcfg->DetectSingleErrorCallback(hramcfg);
+      }
+#else
+      HAL_RAMCFG_DetectSingleErrorCallback(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Double Error Interrupt Management ****************************************/
+  if (__HAL_RAMCFG_GET_IT_SOURCE(hramcfg, RAMCFG_IT_DOUBLEERR) != 0U)
+  {
+    if (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_DOUBLEERR) != 0U)
+    {
+      /* Clear active flags */
+      __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_DOUBLEERR);
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+      /* Check if a valid double error callback is registered */
+      if (hramcfg->DetectDoubleErrorCallback != NULL)
+      {
+        /* Double error detection callback */
+        hramcfg->DetectDoubleErrorCallback(hramcfg);
+      }
+#else
+      HAL_RAMCFG_DetectDoubleErrorCallback(hramcfg);
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  RAMCFG single error detection callback.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                   the configuration information for the specified RAMCFG.
+  * @retval None.
+  */
+__weak void HAL_RAMCFG_DetectSingleErrorCallback(RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hramcfg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RAMCFG_DetectSingleErrorCallback can be implemented in
+            the user file.                                                    */
+}
+
+/**
+  * @brief  RAMCFG double error detection callback.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
+  *                   the configuration information for the specified RAMCFG.
+  * @retval None.
+  */
+__weak void HAL_RAMCFG_DetectDoubleErrorCallback(RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hramcfg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RAMCFG_DetectDoubleErrorCallback can be implemented in
+            the user file.                                                    */
+}
+
+#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register RAMCFG callbacks.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @param  CallbackID    : User Callback identifier a HAL_RAMCFG_CallbackIDTypeDef
+  *                         ENUM as parameter.
+  * @param  pCallback     : Pointer to private callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg,
+                                              HAL_RAMCFG_CallbackIDTypeDef CallbackID,
+                                              void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code and return error */
+    hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Check RAMCFG state */
+  if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case  HAL_RAMCFG_SE_DETECT_CB_ID:
+        /* Register single error callback */
+        hramcfg->DetectSingleErrorCallback = pCallback;
+        break;
+
+      case  HAL_RAMCFG_DE_DETECT_CB_ID:
+        /* Register double error callback */
+        hramcfg->DetectDoubleErrorCallback = pCallback;
+        break;
+
+      case HAL_RAMCFG_MSPINIT_CB_ID :
+        /* Register msp init callback */
+        hramcfg->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RAMCFG_MSPDEINIT_CB_ID :
+        /* Register msp de-init callback */
+        hramcfg->MspDeInitCallback = pCallback;
+        break;
+
+      default:
+        /* Update the error code and return error */
+        hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (hramcfg->State == HAL_RAMCFG_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RAMCFG_MSPINIT_CB_ID :
+        /* Register msp init callback */
+        hramcfg->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RAMCFG_MSPDEINIT_CB_ID :
+        /* Register msp de-init callback */
+        hramcfg->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code and return error */
+        hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code and return error  */
+    hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister RAMCFG callbacks.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @param  CallbackID    : User Callback identifier a HAL_RAMCFG_CallbackIDTypeDef
+  *                         ENUM as parameter.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+  /* Check RAMCFG state */
+  if (hramcfg->State == HAL_RAMCFG_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case  HAL_RAMCFG_SE_DETECT_CB_ID:
+        /* UnRegister single error callback */
+        hramcfg->DetectSingleErrorCallback = NULL;
+        break;
+
+      case  HAL_RAMCFG_DE_DETECT_CB_ID:
+        /* UnRegister double error callback */
+        hramcfg->DetectDoubleErrorCallback = NULL;
+        break;
+
+      case HAL_RAMCFG_MSPINIT_CB_ID :
+        /* UnRegister msp init callback */
+        hramcfg->MspInitCallback = NULL;
+        break;
+
+      case HAL_RAMCFG_MSPDEINIT_CB_ID :
+        /* UnRegister msp de-init callback */
+        hramcfg->MspDeInitCallback = NULL;
+        break;
+
+      case  HAL_RAMCFG_ALL_CB_ID:
+        /* UnRegister all available callbacks */
+        hramcfg->DetectSingleErrorCallback = NULL;
+        hramcfg->DetectDoubleErrorCallback = NULL;
+        hramcfg->MspDeInitCallback         = NULL;
+        hramcfg->MspInitCallback           = NULL;
+        break;
+
+      default:
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (hramcfg->State == HAL_RAMCFG_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RAMCFG_MSPINIT_CB_ID :
+        /* UnRegister msp init callback */
+        hramcfg->MspInitCallback = NULL;
+        break;
+
+      case HAL_RAMCFG_MSPDEINIT_CB_ID :
+        /* UnRegister msp de-init callback */
+        hramcfg->MspDeInitCallback = NULL;
+        break;
+
+      case  HAL_RAMCFG_ALL_CB_ID:
+        /* UnRegister all available callbacks */
+        hramcfg->MspDeInitCallback = NULL;
+        hramcfg->MspInitCallback   = NULL;
+        break;
+
+      default :
+        /* Update the error code */
+        hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+
+        /* Update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code and return error */
+    hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
+
+/** @addtogroup RAMCFG_Exported_Functions_Group7
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Error Functions  #####
+ ===============================================================================
+    [..]
+      This section provides functions to check and get the RAMCFG state
+      and the error code.
+    [..]
+      The HAL_RAMCFG_GetState() function allows the user to get the RAMCFG peripheral
+      state.
+      The HAL_RAMCFG_GetError() function allows the user to get the RAMCFG peripheral error
+      code.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the RAMCFG peripheral state.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @retval RAMCFG state.
+  */
+HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+  /* Return the RAMCFG state */
+  return hramcfg->State;
+}
+
+/**
+  * @brief  Get the RAMCFG peripheral error code.
+  * @param  hramcfg       : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMCFG instance.
+  * @retval RAMCFG error code.
+  */
+uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
+
+  /* Return the RAMCFG error code */
+  return hramcfg->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+
+
+/** @addtogroup RAMCFG_Exported_Functions_Group9
+  *
+@verbatim
+ ===============================================================================
+                      ##### AXISRAM Powerdown Functions  #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to shutdown some AXISRAM memories
+      reduce the consumption.
+    [..]
+      The HAL_RAMCFG_EnableAXISRAM() function allows to power on the selected AXISRAM.
+    [..]
+      The HAL_RAMCFG_DisableAXISRAM() function allows to power off the selected AXISRAM.
+      AXISRAMi memory is in shutdown, and its content is not retained.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable AXISRAM power on.
+  * @note   Only AXISRAM2 to AXISRAM6 are available for this feature.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                   contains the configuration information for the
+  *                   specified RAMCFG instance.
+  * @retval None.
+  */
+void HAL_RAMCFG_EnableAXISRAM(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(hramcfg->Instance));
+
+  /* AXISRAMi power on */
+  CLEAR_BIT(hramcfg->Instance->CR, RAMCFG_AXISRAM_POWERDOWN);
+}
+
+/**
+  * @brief  Disable AXISRAM power on.
+  * @note   Only AXISRAM2 to AXISRAM6 are available for this feature.
+  * @note   AXISRAMi memory is in shutdown, and its content is not retained.
+  * @note   This bit is used to reduce the consumption by powering off the AXISRAMi.
+  * @param  hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
+  *                   contains the configuration information for the
+  *                   specified RAMCFG instance.
+  * @retval None.
+  */
+void HAL_RAMCFG_DisableAXISRAM(const RAMCFG_HandleTypeDef *hramcfg)
+{
+  /* Check the parameters */
+  assert_param(IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(hramcfg->Instance));
+
+  /* AXISRAMi powered off */
+  SET_BIT(hramcfg->Instance->CR, RAMCFG_AXISRAM_POWERDOWN);
+}
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rcc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rcc.c
new file mode 100644
index 000000000..3dc8b5d99
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rcc.c
@@ -0,0 +1,2515 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 64MHz) and all peripherals are off except internal SRAM, BSEC, PWR, IAC,
+      RIFSC, RISAF and JTAG
+      (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
+          all peripherals mapped on these buses are running at HSI speed.
+      (+) All GPIOs are in analog mode , except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance than HSI)
+      (+) Configure the CPU and System bus clock frequencies
+      (+) Configure the AHB and APB buses pre-scalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock kernel source(s) for peripherals which clocks are not
+          derived from the System clock
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+    [..]
+      Incorrect APB prescaler setting:
+      (+) As described in the product errata, after enabling the bus clock to the
+      peripheral and changing the default APB prescaler setting, performing a
+      configuration on the bus peripheral does not update the peripheral registers,
+      resulting in unexpected behavior.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC  RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+#define RCC_MSI_TIMEOUT_VALUE         1U    /* 1 ms */
+#define RCC_HSI_TIMEOUT_VALUE         1U    /* 1 ms */
+#define RCC_HSE_TIMEOUT_VALUE         HSE_STARTUP_TIMEOUT
+#define RCC_LSI_TIMEOUT_VALUE         1U    /* 1 ms */
+#define RCC_CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s  */
+
+#define RCC_PLL1_CONFIG           0U
+#define RCC_PLL2_CONFIG           1U
+#define RCC_PLL3_CONFIG           2U
+#define RCC_PLL4_CONFIG           3U
+
+#define RCC_ITEM_GROUP_IDX_OSC        0x0UL
+#define RCC_ITEM_GROUP_IDX_PLL        0x1UL
+#define RCC_ITEM_GROUP_IDX_IC         0x2UL
+#define RCC_ITEM_GROUP_IDX_SYSCFG     0x3UL
+#define RCC_ITEM_GROUP_IDX_BUS        0x4UL
+#define RCC_ITEM_GROUP_IDX_MEM        0x5UL
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+#define RCC_MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define RCC_MCO1_GPIO_PORT        GPIOA
+#define RCC_MCO1_PIN              GPIO_PIN_8
+
+#define RCC_MCO2_CLK_ENABLE()     __HAL_RCC_GPIOC_CLK_ENABLE()
+#define RCC_MCO2_GPIO_PORT        GPIOC
+#define RCC_MCO2_PIN              GPIO_PIN_9
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit);
+static HAL_StatusTypeDef RCC_PLL_Enable(uint32_t PLLnumber);
+static uint32_t RCC_PLL_IsNewConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit);
+static uint32_t RCC_PLL_Source_IsReady(uint32_t PLLSource);
+static uint32_t RCC_IC_CheckPLLSources(uint32_t PLLSource1, uint32_t PLLSource2);
+static void RCC_ATTR_ConfigItemGroup(uint32_t ItemGroup, uint32_t Item, uint32_t Attributes);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the CPU and System buses clocks (SYSCLK, AHB1,
+       AHB2, AHB3, AHB4, AHB5, APB1, APB2, APB4 and APB5).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+
+         (#) MSI is a low-power RC oscillator which can be used directly as system clock, peripheral
+             clock, or PLL input.But even with frequency calibration, is less accurate than an
+             external crystal oscillator or ceramic resonator.
+
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+         (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or MSI),
+             featuring three different output clocks and able  to work either in integer or Fractional mode.
+           (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
+                and to some peripherals via the ICx mux.
+           (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
+
+         (#) HSE CSS (Clock security system), once enabled and if a HSE clock failure occurs
+            (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled.
+             The interrupt is linked to the Cortex-M NMI (Non-Maskable Interrupt)
+             exception vector.
+
+         (#) LSE CSS (Clock security system), once enabled and if a LSE clock failure occurs
+             the LSE is no more provided to RTC, it allows to wake-up from standby mode and protect the
+             backup registers and BKPSRAM via TAMP. The LSE CSS may be re-armed for further attempt(s) to use LSE.
+
+         (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, LSI, MSI, CPU (SYSA), IC5 mux
+             or IC10 mux clock (through a configurable pre-scaler) on PA8 pin.
+
+         (#) MCO2 (micro controller clock output), used to output HSI, LSE, HSE, LSI, MSI, System Bus (SYSB),
+             IC15 mux or IC20 mux clock (through a configurable pre-scaler) on PC9 pin.
+
+    [..] CPU, System bus, AHB and APB buses clocks configuration
+         (#) Several clock sources can be used to drive independently the CPU (CPUCLK) and System bus clock (SYSCLK):
+             HSI, MSI, HSE or ICx mux.
+             The AHB clock (HCLK) is derived from System core clock through configurable
+             pre-scaler and used to clock the CPU, memory and peripherals mapped
+             on AHB and APB bus through configurable pre-scalers
+             and used to clock the peripherals mapped on these buses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
+
+         -@- All the peripheral clocks are derived from the System bus clock (SYSCLK).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as CPU and system clock source
+  *            - MSI and HSE OFF
+  *            - PLL1, PLL2, PLL3 and PLL4 bypassed
+  *            - AHB, APB Bus prescalers set to 1
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - Memory clocks
+  *            - Misc clocks
+  *            - LSI, LSE and RTC clocks
+  *            - ICx selections and dividers
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+  /* Disable all interrupts except default one */
+  WRITE_REG(RCC->CIER, RCC_CIER_HSECSSIE);
+
+  /* Clear all interrupts flags */
+  WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \
+            RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | RCC_CICR_PLL3RDYC | RCC_CICR_PLL4RDYC | \
+            RCC_CICR_LSECSSC | RCC_CICR_HSECSSC | RCC_CICR_WKUPFC);
+
+  /* Clear reset source flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+  /* Restore default HSI */
+  LL_RCC_HSI_SetDivider(LL_RCC_HSI_DIV_1);
+  LL_RCC_HSI_Enable();
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for HSI READY bit */
+  while (LL_RCC_HSI_IsReady() == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Reset CFGR1 register to select HSI as CPU and system bus clock */
+  CLEAR_REG(RCC->CFGR1);
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR1, (RCC_CFGR1_CPUSWS | RCC_CFGR1_SYSSWS)) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Update the SystemCoreClock variable */
+  SystemCoreClock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if (HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_TIMEOUT;
+  }
+
+  /* Reset PLL1 registers to default value */
+  WRITE_REG(RCC->PLL1CFGR1, 0x08202500U);
+  WRITE_REG(RCC->PLL1CFGR2, 0x00800000U);
+  WRITE_REG(RCC->PLL1CFGR3, 0x4900000DU);
+  /* Reset PLL2 registers to default value */
+  WRITE_REG(RCC->PLL2CFGR1, 0x08000000U);
+  WRITE_REG(RCC->PLL2CFGR2, 0x00000000U);
+  WRITE_REG(RCC->PLL2CFGR3, 0x49000005U);
+  /* Reset PLL3 registers to default value */
+  WRITE_REG(RCC->PLL3CFGR1, 0x08000000U);
+  WRITE_REG(RCC->PLL3CFGR2, 0x00000000U);
+  WRITE_REG(RCC->PLL3CFGR3, 0x49000005U);
+  /* Reset PLL4 registers to default value */
+  WRITE_REG(RCC->PLL4CFGR1, 0x08000000U);
+  WRITE_REG(RCC->PLL4CFGR2, 0x00000000U);
+  WRITE_REG(RCC->PLL4CFGR3, 0x49000005U);
+
+  /* Reset MSION, HSEON, PLL1ON, PLL2ON, PLL3ON and PLL4ON bits */
+  WRITE_REG(RCC->CCR, RCC_CCR_MSIONC | RCC_CCR_HSEONC | \
+            RCC_CCR_PLL1ONC | RCC_CCR_PLL2ONC | RCC_CCR_PLL3ONC | RCC_CCR_PLL4ONC);
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for all PLL ready bits to be reset */
+  while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY | RCC_SR_PLL2RDY | RCC_SR_PLL3RDY | RCC_SR_PLL4RDY)) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Reset prescalers in CFGR2 register to default values*/
+  WRITE_REG(RCC->CFGR2, 0x00100000U);
+
+  /* Reset MSICFGR register */
+  CLEAR_REG(RCC->MSICFGR);
+
+  /* Reset HSIMCR register to default value */
+  WRITE_REG(RCC->HSIMCR, 0x001F07A1U);
+
+  /* Reset HSECFGR register to default value */
+  WRITE_REG(RCC->HSECFGR, 0x00000800U);
+
+  /* Reset STOPCR register to default value */
+  WRITE_REG(RCC->STOPCR, 0x00000002U);
+
+  /* Disable MCO1 and MCO2 */
+  CLEAR_BIT(RCC->MISCENR, RCC_MISCENR_MCO1EN | RCC_MISCENR_MCO2EN);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  pRCC_OscInitStruct  Pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   LSE control requires that the backup domain shall be previously enabled
+  *         with HAL_PWR_EnableBkUpAccess().
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this function. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @note   This function does not protect the MCOxSEL, the PERSEL and the PPPSEL glitch-free muxes
+  *         (Mux selection cannot be changed if selected input clock is inactive).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef  *pRCC_OscInitStruct)
+{
+  uint32_t tickstart;
+  uint32_t sysclksrc;
+  uint32_t cpuclksrc;
+  uint32_t pll1src;
+  uint32_t pll2src;
+  uint32_t pll3src;
+  uint32_t pll4src;
+  uint32_t rccsr;
+
+  /* Check Null pointer */
+  if (pRCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(pRCC_OscInitStruct->OscillatorType));
+
+  cpuclksrc = LL_RCC_GetCpuClkSource();
+  sysclksrc = LL_RCC_GetSysClkSource();
+  pll1src = LL_RCC_PLL1_GetSource();
+  pll2src = LL_RCC_PLL2_GetSource();
+  pll3src = LL_RCC_PLL3_GetSource();
+  pll4src = LL_RCC_PLL4_GetSource();
+  rccsr = RCC->SR;
+
+  /*------------------------------- HSE Configuration ------------------------*/
+  if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(pRCC_OscInitStruct->HSEState));
+
+    /* When the HSE is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled */
+    if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_HSE) || (sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) ||
+        ((pll1src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL1RDY) == RCC_SR_PLL1RDY))) ||
+        ((pll2src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL2RDY) == RCC_SR_PLL2RDY))) ||
+        ((pll3src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL3RDY) == RCC_SR_PLL3RDY))) ||
+        ((pll4src == LL_RCC_PLLSOURCE_HSE) && (((rccsr & RCC_SR_PLL4RDY) == RCC_SR_PLL4RDY))))
+    {
+      if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF)
+      {
+        return HAL_ERROR;
+      }
+      /* HSE ON , nothing to do */
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(pRCC_OscInitStruct->HSEState);
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Check the HSE State */
+      if (pRCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Wait till HSE is ready */
+        while (READ_BIT(RCC->SR, RCC_SR_HSERDY) == 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Wait till HSE is disabled */
+        while (READ_BIT(RCC->SR, RCC_SR_HSERDY) != 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+
+  /*----------------------------- HSI Configuration --------------------------*/
+  if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(pRCC_OscInitStruct->HSIState));
+
+    /* When the HSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled */
+    if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_HSI) || (sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) ||
+        ((pll1src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL1RDY) == RCC_SR_PLL1RDY))) ||
+        ((pll2src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL2RDY) == RCC_SR_PLL2RDY))) ||
+        ((pll3src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL3RDY) == RCC_SR_PLL3RDY))) ||
+        ((pll4src == LL_RCC_PLLSOURCE_HSI) && (((rccsr & RCC_SR_PLL4RDY) == RCC_SR_PLL4RDY))))
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF)
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the divider and calibration is allowed */
+      else
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_HSI_DIV(pRCC_OscInitStruct->HSIDiv));
+        assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue));
+
+        /* Set the HSI Divider */
+        __HAL_RCC_HSI_DIVIDER_CONFIG(pRCC_OscInitStruct->HSIDiv);
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if (pRCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_HSI_DIV(pRCC_OscInitStruct->HSIDiv));
+        assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue));
+
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while (LL_RCC_HSI_IsReady() == 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Set the HSI Divider */
+        __HAL_RCC_HSI_DIVIDER_CONFIG(pRCC_OscInitStruct->HSIDiv);
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is disabled */
+        while (LL_RCC_HSI_IsReady() != 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+
+  /*----------------------------- MSI Configuration --------------------------*/
+  if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_MSI(pRCC_OscInitStruct->MSIState));
+
+    /* When the MSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled */
+    /* but just to update the MSI calibration value */
+    if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_MSI) || (sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) ||
+        ((pll1src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL1RDY) == RCC_SR_PLL1RDY))) ||
+        ((pll2src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL2RDY) == RCC_SR_PLL2RDY))) ||
+        ((pll3src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL3RDY) == RCC_SR_PLL3RDY))) ||
+        ((pll4src == LL_RCC_PLLSOURCE_MSI) && (((rccsr & RCC_SR_PLL4RDY) == RCC_SR_PLL4RDY))))
+    {
+      /* When MSI is used as system clock it will not disabled */
+      if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF)
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_MSI_CALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
+
+        /* Adjusts the Internal High Speed oscillator (MSI) calibration value.*/
+        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->MSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the MSI State */
+      if ((pRCC_OscInitStruct->MSIState) != RCC_MSI_OFF)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_MSI_FREQUENCY(pRCC_OscInitStruct->MSIFrequency));
+        assert_param(IS_RCC_MSI_CALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue));
+
+        /* Set the frequency */
+        __HAL_RCC_MSI_FREQUENCY_CONFIG(pRCC_OscInitStruct->MSIFrequency);
+
+        /* Enable the Internal High Speed oscillator (MSI). */
+        __HAL_RCC_MSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till MSI is ready */
+        while (LL_RCC_MSI_IsReady() == 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_MSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (MSI) calibration value.*/
+        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->MSICalibrationValue);
+      }
+      else
+      {
+        /* Ignore MSI frequency and calibration values in disable case */
+        /* Disable the Internal High Speed oscillator (MSI). */
+        __HAL_RCC_MSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till MSI is disabled */
+        while (LL_RCC_MSI_IsReady() != 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_MSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+
+  /*------------------------------ LSI Configuration -------------------------*/
+  if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(pRCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if ((pRCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while (LL_RCC_LSI_IsReady() == 0U)
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while (LL_RCC_LSI_IsReady() != 0U)
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /*------------------------------ LSE Configuration -------------------------*/
+  if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(pRCC_OscInitStruct->LSEState));
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(pRCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if ((pRCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while (LL_RCC_LSE_IsReady() == 0U)
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is disabled */
+      while (LL_RCC_LSE_IsReady() != 0U)
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /*-------------------------------- PLL1 Configuration ----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL1.PLLState));
+
+  if (pRCC_OscInitStruct->PLL1.PLLState != RCC_PLL_NONE)
+  {
+    uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL1_CONFIG, &(pRCC_OscInitStruct->PLL1));
+    uint32_t pll1_ready = LL_RCC_PLL1_IsReady();
+    if (new_pll_config == 1U)
+    {
+      uint32_t ic1src = LL_RCC_IC1_GetSource();
+      uint32_t ic2src = LL_RCC_IC2_GetSource();
+      uint32_t ic6src = LL_RCC_IC6_GetSource();
+      uint32_t ic11src = LL_RCC_IC11_GetSource();
+      /* PLL1 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */
+      if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL1))
+      {
+        return HAL_ERROR;
+      }
+
+      /* PLL1 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR  */
+      if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL1) ||
+                                                                  (ic6src == LL_RCC_ICCLKSOURCE_PLL1) ||
+                                                                  (ic11src == LL_RCC_ICCLKSOURCE_PLL1)))
+      {
+        return HAL_ERROR;
+      }
+      /* PLL1 is not used, it can be configured */
+      if (RCC_PLL_Config(RCC_PLL1_CONFIG, &(pRCC_OscInitStruct->PLL1)) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else if ((pRCC_OscInitStruct->PLL1.PLLState == RCC_PLL_ON) && (pll1_ready == 0U))
+    {
+      if (RCC_PLL_Enable(RCC_PLL1_CONFIG) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /*-------------------------------- PLL2 Configuration ----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL2.PLLState));
+
+  if (pRCC_OscInitStruct->PLL2.PLLState != RCC_PLL_NONE)
+  {
+    uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL2_CONFIG, &(pRCC_OscInitStruct->PLL2));
+    uint32_t pll2_ready = LL_RCC_PLL2_IsReady();
+    if (new_pll_config == 1U)
+    {
+      uint32_t ic1src = LL_RCC_IC1_GetSource();
+      uint32_t ic2src = LL_RCC_IC2_GetSource();
+      uint32_t ic6src = LL_RCC_IC6_GetSource();
+      uint32_t ic11src = LL_RCC_IC11_GetSource();
+      /* PLL2 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */
+      if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL2))
+      {
+        return HAL_ERROR;
+      }
+
+      /* PLL2 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR  */
+      if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL2) ||
+                                                                  (ic6src == LL_RCC_ICCLKSOURCE_PLL2) ||
+                                                                  (ic11src == LL_RCC_ICCLKSOURCE_PLL2)))
+      {
+        return HAL_ERROR;
+      }
+      /* PLL2 is not used, it can be configured */
+      if (RCC_PLL_Config(RCC_PLL2_CONFIG, &(pRCC_OscInitStruct->PLL2)) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else if ((pRCC_OscInitStruct->PLL2.PLLState == RCC_PLL_ON) && (pll2_ready == 0U))
+    {
+      if (RCC_PLL_Enable(RCC_PLL2_CONFIG) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /*-------------------------------- PLL3 Configuration ----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL3.PLLState));
+
+  if (pRCC_OscInitStruct->PLL3.PLLState != RCC_PLL_NONE)
+  {
+    uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL3_CONFIG, &(pRCC_OscInitStruct->PLL3));
+    uint32_t pll3_ready = LL_RCC_PLL1_IsReady();
+    if (new_pll_config == 1U)
+    {
+      uint32_t ic1src = LL_RCC_IC1_GetSource();
+      uint32_t ic2src = LL_RCC_IC2_GetSource();
+      uint32_t ic6src = LL_RCC_IC6_GetSource();
+      uint32_t ic11src = LL_RCC_IC11_GetSource();
+      /* PLL3 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */
+      if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL3))
+      {
+        return HAL_ERROR;
+      }
+      /* PLL3 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR  */
+      if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL3) ||
+                                                                  (ic6src == LL_RCC_ICCLKSOURCE_PLL3) ||
+                                                                  (ic11src == LL_RCC_ICCLKSOURCE_PLL3)))
+      {
+        return HAL_ERROR;
+      }
+      /* PLL3 is not used, it can be configured */
+      if (RCC_PLL_Config(RCC_PLL3_CONFIG, &(pRCC_OscInitStruct->PLL3)) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else if ((pRCC_OscInitStruct->PLL3.PLLState == RCC_PLL_ON) && (pll3_ready == 0U))
+    {
+      if (RCC_PLL_Enable(RCC_PLL3_CONFIG) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /*-------------------------------- PLL4 Configuration ----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL4.PLLState));
+
+  if (pRCC_OscInitStruct->PLL4.PLLState != RCC_PLL_NONE)
+  {
+    uint32_t new_pll_config = RCC_PLL_IsNewConfig(RCC_PLL4_CONFIG, &(pRCC_OscInitStruct->PLL4));
+    uint32_t pll4_ready = LL_RCC_PLL4_IsReady();
+
+    if (new_pll_config == 1U)
+    {
+      uint32_t ic1src = LL_RCC_IC1_GetSource();
+      uint32_t ic2src = LL_RCC_IC2_GetSource();
+      uint32_t ic6src = LL_RCC_IC6_GetSource();
+      uint32_t ic11src = LL_RCC_IC11_GetSource();
+      /* PLL4 should not be disabled / reconfigured if used for IC1 (cpuclksrc) - return HAL_ERROR */
+      if ((cpuclksrc == RCC_CPUCLKSOURCE_STATUS_IC1) && (ic1src == LL_RCC_ICCLKSOURCE_PLL4))
+      {
+        return HAL_ERROR;
+      }
+      /* PLL4 should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc) - return HAL_ERROR  */
+      if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11) && ((ic2src == LL_RCC_ICCLKSOURCE_PLL4) ||
+                                                                  (ic6src == LL_RCC_ICCLKSOURCE_PLL4) ||
+                                                                  (ic11src == LL_RCC_ICCLKSOURCE_PLL4)))
+      {
+        return HAL_ERROR;
+      }
+      /* PLL4 is not used, it can be configured */
+      if (RCC_PLL_Config(RCC_PLL4_CONFIG, &(pRCC_OscInitStruct->PLL4)) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else if ((pRCC_OscInitStruct->PLL4.PLLState == RCC_PLL_ON) && (pll4_ready == 0U))
+    {
+      if (RCC_PLL_Enable(RCC_PLL4_CONFIG) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, System AXI, AHB, APB buses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  pRCC_ClkInitStruct  Pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
+  *         and updated by HAL_InitTick() function called within this function.
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         start-up from Reset, wake-up from STOP (unless MSI is selected) and STANDBY mode,
+  *         or in case of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after start-up delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef  *pRCC_ClkInitStruct)
+{
+  uint32_t tickstart;
+
+  /* Check Null pointer */
+  if (pRCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(pRCC_ClkInitStruct->ClockType));
+
+  /* Increasing the BUS frequency divider ? */
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK1(pRCC_ClkInitStruct->APB1CLKDivider));
+    if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, (pRCC_ClkInitStruct->APB1CLKDivider));
+    }
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK2(pRCC_ClkInitStruct->APB2CLKDivider));
+    if ((pRCC_ClkInitStruct->APB2CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE2))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, (pRCC_ClkInitStruct->APB2CLKDivider));
+    }
+  }
+
+  /*-------------------------- PCLK4 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4)
+  {
+    assert_param(IS_RCC_PCLK4(pRCC_ClkInitStruct->APB4CLKDivider));
+    if ((pRCC_ClkInitStruct->APB4CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE4))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, (pRCC_ClkInitStruct->APB4CLKDivider));
+    }
+  }
+
+  /*-------------------------- PCLK5 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5)
+  {
+    assert_param(IS_RCC_PCLK5(pRCC_ClkInitStruct->APB5CLKDivider));
+    if ((pRCC_ClkInitStruct->APB5CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE5))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, (pRCC_ClkInitStruct->APB5CLKDivider));
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
+    if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
+    }
+  }
+
+  /*------------------------- CPUCLK Configuration -------------------------*/
+  if ((pRCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_CPUCLK) == RCC_CLOCKTYPE_CPUCLK)
+  {
+    assert_param(IS_RCC_CPUCLKSOURCE(pRCC_ClkInitStruct->CPUCLKSource));
+
+    /* HSE is selected as CPU Clock Source */
+    if (pRCC_ClkInitStruct->CPUCLKSource == RCC_CPUCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if (LL_RCC_HSE_IsReady() == 0U)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* PLL is selected as CPU Clock Source */
+    else if (pRCC_ClkInitStruct->CPUCLKSource == RCC_CPUCLKSOURCE_IC1)
+    {
+      /* Check parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC1Selection.ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC1Selection.ClockDivider));
+
+      /* ICx clock switch requires both origin and destination clock source to be active */
+      /* Check IC1 origin and target clock sources availability */
+      if (RCC_IC_CheckPLLSources(LL_RCC_IC1_GetSource(), pRCC_ClkInitStruct->IC1Selection.ClockSelection) != 1U)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Configure IC1 source and divider */
+      WRITE_REG(RCC->IC1CFGR, pRCC_ClkInitStruct->IC1Selection.ClockSelection | \
+                ((pRCC_ClkInitStruct->IC1Selection.ClockDivider - 1U) << RCC_IC1CFGR_IC1INT_Pos));
+
+      /* Enable IC1 */
+      LL_RCC_IC1_Enable();
+    }
+    /* MSI is selected as CPU Clock Source */
+    else if (pRCC_ClkInitStruct->CPUCLKSource == RCC_CPUCLKSOURCE_MSI)
+    {
+      /* Check the MSI ready flag */
+      if (LL_RCC_MSI_IsReady() == 0U)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* HSI is selected as CPU Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if (LL_RCC_HSI_IsReady() == 0U)
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Switch the CPU clock */
+    MODIFY_REG(RCC->CFGR1, RCC_CFGR1_CPUSW, pRCC_ClkInitStruct->CPUCLKSource);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    while (__HAL_RCC_GET_CPUCLK_SOURCE() != (pRCC_ClkInitStruct->CPUCLKSource << 4U))
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Update the SystemCoreClock global variable with CPU clock */
+    SystemCoreClock = HAL_RCC_GetCpuClockFreq();
+
+  }
+
+  /*------------------------- SYSCLK Configuration -------------------------*/
+  if ((pRCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource));
+
+    /* HSE is selected as System bus clock source */
+    if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if (LL_RCC_HSE_IsReady() == 0U)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* PLL output is selected as System bus clock source */
+    else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)
+    {
+      /* Check parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC2Selection.ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC2Selection.ClockDivider));
+      assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC6Selection.ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC6Selection.ClockDivider));
+      assert_param(IS_RCC_ICCLKSOURCE(pRCC_ClkInitStruct->IC11Selection.ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(pRCC_ClkInitStruct->IC11Selection.ClockDivider));
+
+      /* ICx clock switch requires both origin and destination clock source to be active */
+      /* Check IC2/IC6/IC11 origin and target clock sources availability */
+      if (RCC_IC_CheckPLLSources(LL_RCC_IC2_GetSource(), pRCC_ClkInitStruct->IC2Selection.ClockSelection) != 1U)
+      {
+        return HAL_ERROR;
+      }
+      if (RCC_IC_CheckPLLSources(LL_RCC_IC6_GetSource(), pRCC_ClkInitStruct->IC6Selection.ClockSelection) != 1U)
+      {
+        return HAL_ERROR;
+      }
+      if (RCC_IC_CheckPLLSources(LL_RCC_IC11_GetSource(), pRCC_ClkInitStruct->IC11Selection.ClockSelection) != 1U)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Configure IC2, IC6 and IC11 sources and dividers */
+      WRITE_REG(RCC->IC2CFGR, pRCC_ClkInitStruct->IC2Selection.ClockSelection | \
+                ((pRCC_ClkInitStruct->IC2Selection.ClockDivider - 1U) << RCC_IC2CFGR_IC2INT_Pos));
+      WRITE_REG(RCC->IC6CFGR, pRCC_ClkInitStruct->IC6Selection.ClockSelection | \
+                ((pRCC_ClkInitStruct->IC6Selection.ClockDivider - 1U) << RCC_IC6CFGR_IC6INT_Pos));
+      WRITE_REG(RCC->IC11CFGR, pRCC_ClkInitStruct->IC11Selection.ClockSelection | \
+                ((pRCC_ClkInitStruct->IC11Selection.ClockDivider - 1U) << RCC_IC11CFGR_IC11INT_Pos));
+
+      /* Require to have IC2, IC6 and IC11 outputs enabled */
+      WRITE_REG(RCC->DIVENSR, RCC_DIVENSR_IC2ENS | RCC_DIVENSR_IC6ENS | RCC_DIVENSR_IC11ENS);
+    }
+    /* HSI is selected as System bus clock source */
+    else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
+    {
+      /* Check the HSI ready flag */
+      if (LL_RCC_HSI_IsReady() == 0U)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* MSI is selected as System bus clock source */
+    else
+    {
+      /* Check the MSI ready flag */
+      if (LL_RCC_MSI_IsReady() == 0U)
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Switch the system bus clocks */
+    MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SYSSW, pRCC_ClkInitStruct->SYSCLKSource);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (pRCC_ClkInitStruct->SYSCLKSource << 4U))
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Decreasing the BUS frequency divider ? */
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider));
+    if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider);
+    }
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK1(pRCC_ClkInitStruct->APB1CLKDivider));
+    if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, (pRCC_ClkInitStruct->APB1CLKDivider));
+    }
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK2(pRCC_ClkInitStruct->APB2CLKDivider));
+    if ((pRCC_ClkInitStruct->APB2CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE2))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, (pRCC_ClkInitStruct->APB2CLKDivider));
+    }
+  }
+
+  /*-------------------------- PCLK4 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4)
+  {
+    assert_param(IS_RCC_PCLK4(pRCC_ClkInitStruct->APB4CLKDivider));
+    if ((pRCC_ClkInitStruct->APB4CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE4))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE4, (pRCC_ClkInitStruct->APB4CLKDivider));
+    }
+  }
+
+  /*-------------------------- PCLK5 Configuration ---------------------------*/
+  if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5)
+  {
+    assert_param(IS_RCC_PCLK5(pRCC_ClkInitStruct->APB5CLKDivider));
+    if ((pRCC_ClkInitStruct->APB5CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE5))
+    {
+      MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE5, (pRCC_ClkInitStruct->APB5CLKDivider));
+    }
+  }
+
+  /* Configure the source of time base considering new system clocks settings*/
+  return HAL_InitTick(uwTickPrio);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 Peripheral Control functions
+  *  @brief   RCC clocks control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PWR VDDIO4 Input Independent I/O supply 4 shall be previously set up for PC9
+  *         with HAL_PWREx_EnableVddIO4()
+  * @note   The MCO switch to the new clock source only occurs when the previous clock source is active
+  *         (dynamic switch).
+  * @param  RCC_MCOx specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1 Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2 Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_LSI LSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_MSI MSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_IC5 IC5 clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_IC10 IC10 clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_SYSA CPU clock (SYSA) selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_MSI MSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_IC15 IC15 clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_IC20 IC20 clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_SYSB Bus clock (SYSB) selected as MCO2 source
+  * @param  RCC_MCODiv specifies the MCOx pre-scaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_16  : divider applied to MCOx clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+
+  /* RCC_MCO1 */
+  if (RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    RCC_MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = RCC_MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(RCC_MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Configure MCO1 */
+    LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv);
+
+    /* Enable IC5 if requested as source to MCO1 */
+    if (RCC_MCOSource == RCC_MCO1SOURCE_IC5)
+    {
+      LL_RCC_IC5_Enable();
+    }
+    /* Enable IC10 if requested as source to MCO1 */
+    else if (RCC_MCOSource == RCC_MCO1SOURCE_IC10)
+    {
+      LL_RCC_IC10_Enable();
+    }
+    else
+    {
+      /* Nothing to do as not ICx source */
+    }
+    /* Enable MC01 output */
+    LL_RCC_EnableMCO(LL_RCC_MCO1);
+  }
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    RCC_MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = RCC_MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(RCC_MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Configure MCO2 */
+    LL_RCC_ConfigMCO(RCC_MCOSource, ((RCC_CCIPR5_MCO2PRE << 16U) | ((RCC_MCODiv & RCC_CCIPR5_MCO1PRE) << 8U)));
+
+    /* Enable IC15 if requested as source to MCO2 */
+    if (RCC_MCOSource == RCC_MCO2SOURCE_IC15)
+    {
+      LL_RCC_IC15_Enable();
+    }
+    /* Enable IC20 if requested as source to MCO2 */
+    else if (RCC_MCOSource == RCC_MCO2SOURCE_IC20)
+    {
+      LL_RCC_IC20_Enable();
+    }
+    else
+    {
+      /* Nothing to do as not ICx source */
+    }
+    /* Enable MC02 output */
+    LL_RCC_EnableMCO(LL_RCC_MCO2);
+  }
+}
+
+/**
+  * @brief  Enable the HSE Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
+  * @note   The HSE Clock Security System may be enabled even if the HSE is not enabled
+  *         but will be activated when the HSE is enabled and ready.
+  * @note   It is not possible to disable the HSE Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  LL_RCC_HSE_EnableCSS();
+}
+
+/**
+  * @brief  Returns the CPU clock (sysa_ck) frequency
+  *
+  * @note   The CPU clock frequency computed by this function may be not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If CPUCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note     If CPUCLK source is MSI, function returns values based on MSI_VALUE(*)
+  * @note     If CPUCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note     If CPUCLK source is IC1, function returns values based on HSI_VALUE(*),
+  *           MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value
+  *               64 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baud rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time CPUCLK changes, this function must be called by the user application
+  *         to update the CPUCLK value. Otherwise, any configuration based on this function
+  *         will be incorrect.
+  *
+  * @retval CPUCLK frequency
+  */
+uint32_t HAL_RCC_GetCpuClockFreq(void)
+{
+  uint32_t frequency = 0U;
+  uint32_t ic_divider;
+
+  /* Get CPUCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetCpuClkSource())
+  {
+    /* No check on Ready: Won't be selected by hardware if not */
+    case LL_RCC_CPU_CLKSOURCE_STATUS_HSI:
+      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      break;
+
+    case LL_RCC_CPU_CLKSOURCE_STATUS_MSI:
+      if (LL_RCC_MSI_GetFrequency() == LL_RCC_MSI_FREQ_4MHZ)
+      {
+        frequency = MSI_VALUE;
+      }
+      else
+      {
+        frequency = 16000000UL;
+      }
+      break;
+
+    case LL_RCC_CPU_CLKSOURCE_STATUS_HSE:
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_CPU_CLKSOURCE_STATUS_IC1:
+      ic_divider = LL_RCC_IC1_GetDivider();
+      switch (LL_RCC_IC1_GetSource())
+      {
+        case LL_RCC_ICCLKSOURCE_PLL1:
+          frequency = HAL_RCCEx_GetPLL1CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL2:
+          frequency = HAL_RCCEx_GetPLL2CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL3:
+          frequency = HAL_RCCEx_GetPLL3CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL4:
+          frequency = HAL_RCCEx_GetPLL4CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        default:
+          /* Unexpected case */
+          break;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Returns the SYSCLK bus (sysb_ck) frequency
+  *
+  * @note   The system bus frequency computed by this function may be not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note     If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note     If SYSCLK source is IC2, function returns values based on HSI_VALUE(*),
+  *           MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value
+  *               64 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baud rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called by the user application
+  *         to update the SYSCLK value. Otherwise, any configuration based on this function
+  *         will be incorrect.
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t frequency = 0U;
+  uint32_t ic_divider;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetSysClkSource())
+  {
+    /* No check on Ready: Won't be selected by hardware if not */
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
+      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:
+      if (LL_RCC_MSI_GetFrequency() == LL_RCC_MSI_FREQ_4MHZ)
+      {
+        frequency = MSI_VALUE;
+      }
+      else
+      {
+        frequency = 16000000UL;
+      }
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11:
+      ic_divider = LL_RCC_IC2_GetDivider();
+      switch (LL_RCC_IC2_GetSource())
+      {
+        case LL_RCC_ICCLKSOURCE_PLL1:
+          frequency = HAL_RCCEx_GetPLL1CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL2:
+          frequency = HAL_RCCEx_GetPLL2CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL3:
+          frequency = HAL_RCCEx_GetPLL3CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL4:
+          frequency = HAL_RCCEx_GetPLL4CLKFreq();
+          frequency = frequency / ic_divider;
+          break;
+        default:
+          /* Unexpected case */
+          break;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return the HCLK frequency.
+  * @retval HCLK frequency in Hz
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+  return LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return the PCLK1 frequency.
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+  return LL_RCC_CALC_PCLK1_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()),
+                                LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return the PCLK2 frequency.
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK2 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  return LL_RCC_CALC_PCLK2_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()),
+                                LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return the PCLK4 frequency.
+  * @note   Each time PCLK4 changes, this function must be called to update the
+  *         right PCLK4 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK4 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK4Freq(void)
+{
+  return LL_RCC_CALC_PCLK4_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()),
+                                LL_RCC_GetAPB4Prescaler());
+}
+
+/**
+  * @brief  Return the PCLK5 frequency.
+  * @note   Each time PCLK5 changes, this function must be called to update the
+  *         right PCLK5 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK5 frequency in Hz
+  */
+uint32_t HAL_RCC_GetPCLK5Freq(void)
+{
+  return LL_RCC_CALC_PCLK5_FREQ(LL_RCC_CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()),
+                                LL_RCC_GetAPB5Prescaler());
+}
+
+/**
+  * @brief  Get the oscillators status configuration in RCC_OscInitStruct according to
+  *         the internal RCC configuration registers.
+  * @param  pRCC_OscInitStruct  Pointer to an RCC_OscInitTypeDef structure that
+  *         will return the configuration.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *pRCC_OscInitStruct)
+{
+  uint32_t sr_value;
+  uint32_t cfgr_value;
+
+  /* Get the status register value */
+  sr_value = RCC->SR;
+
+  /* Set all possible values for the Oscillator type parameters --------------*/
+  pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
+                                       RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_HSERDY) != 0UL)
+  {
+    cfgr_value = RCC->HSECFGR;
+    if ((cfgr_value & (RCC_HSECFGR_HSEBYP | RCC_HSECFGR_HSEEXT)) == RCC_HSECFGR_HSEBYP)
+    {
+      pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+    }
+    else if ((cfgr_value & (RCC_HSECFGR_HSEBYP | RCC_HSECFGR_HSEEXT)) == (RCC_HSECFGR_HSEBYP | RCC_HSECFGR_HSEEXT))
+    {
+      pRCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
+    }
+    else
+    {
+      pRCC_OscInitStruct->HSEState = RCC_HSE_ON;
+    }
+  }
+  else
+  {
+    pRCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+  /* Get the MSI configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_MSIRDY) != 0UL)
+  {
+    pRCC_OscInitStruct->MSIState = RCC_MSI_ON;
+  }
+  else
+  {
+    pRCC_OscInitStruct->MSIState = RCC_MSI_OFF;
+  }
+
+  cfgr_value = RCC->MSICFGR;
+  pRCC_OscInitStruct->MSIFrequency = (cfgr_value & RCC_MSICFGR_MSIFREQSEL);
+  pRCC_OscInitStruct->MSICalibrationValue = ((cfgr_value & RCC_MSICFGR_MSITRIM) >> RCC_MSICFGR_MSITRIM_Pos);
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_HSIRDY) != 0UL)
+  {
+    pRCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    pRCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  cfgr_value = RCC->HSICFGR;
+  pRCC_OscInitStruct->HSIDiv = (cfgr_value & RCC_HSICFGR_HSIDIV);
+  pRCC_OscInitStruct->HSICalibrationValue = ((cfgr_value & RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_LSERDY) != 0UL)
+  {
+    cfgr_value = RCC->LSECFGR;
+    if ((cfgr_value & (RCC_LSECFGR_LSEBYP | RCC_LSECFGR_LSEEXT)) == RCC_LSECFGR_LSEBYP)
+    {
+      pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+    }
+    else if ((cfgr_value & (RCC_LSECFGR_LSEBYP | RCC_LSECFGR_LSEEXT)) == (RCC_LSECFGR_LSEBYP | RCC_LSECFGR_LSEEXT))
+    {
+      pRCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
+    }
+    else
+    {
+      pRCC_OscInitStruct->LSEState = RCC_LSE_ON;
+    }
+  }
+  else
+  {
+    pRCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_LSIRDY) != 0UL)
+  {
+    pRCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    pRCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the PLL1 configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_PLL1RDY) != 0UL)
+  {
+    cfgr_value = RCC->PLL1CFGR1;
+    pRCC_OscInitStruct->PLL1.PLLState = RCC_PLL_ON;
+    pRCC_OscInitStruct->PLL1.PLLSource = (cfgr_value & RCC_PLL1CFGR1_PLL1SEL);
+    pRCC_OscInitStruct->PLL1.PLLM = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos);
+    pRCC_OscInitStruct->PLL1.PLLN = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos);
+    pRCC_OscInitStruct->PLL1.PLLFractional = (READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> \
+                                              RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
+    cfgr_value = RCC->PLL1CFGR3;
+    pRCC_OscInitStruct->PLL1.PLLP1 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos);
+    pRCC_OscInitStruct->PLL1.PLLP2 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos);
+  }
+  else
+  {
+    cfgr_value = RCC->PLL1CFGR1;
+    if ((cfgr_value & RCC_PLL1CFGR1_PLL1BYP) != 0UL)
+    {
+      pRCC_OscInitStruct->PLL1.PLLState = RCC_PLL_BYPASS;
+    }
+    else
+    {
+      pRCC_OscInitStruct->PLL1.PLLState = RCC_PLL_OFF;
+    }
+  }
+
+  /* Get the PLL2 configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_PLL2RDY) != 0UL)
+  {
+    cfgr_value = RCC->PLL2CFGR1;
+    pRCC_OscInitStruct->PLL2.PLLState = RCC_PLL_ON;
+    pRCC_OscInitStruct->PLL2.PLLSource = (cfgr_value & RCC_PLL2CFGR1_PLL2SEL);
+    pRCC_OscInitStruct->PLL2.PLLM = ((cfgr_value & RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos);
+    pRCC_OscInitStruct->PLL2.PLLN = ((cfgr_value & RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos);
+    pRCC_OscInitStruct->PLL2.PLLFractional = (READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> \
+                                              RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos);
+    cfgr_value = RCC->PLL2CFGR3;
+    pRCC_OscInitStruct->PLL2.PLLP1 = ((cfgr_value & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos);
+    pRCC_OscInitStruct->PLL2.PLLP2 = ((cfgr_value & RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos);
+  }
+  else
+  {
+    cfgr_value = RCC->PLL2CFGR1;
+    if ((cfgr_value & RCC_PLL2CFGR1_PLL2BYP) != 0UL)
+    {
+      pRCC_OscInitStruct->PLL2.PLLState = RCC_PLL_BYPASS;
+    }
+    else
+    {
+      pRCC_OscInitStruct->PLL2.PLLState = RCC_PLL_OFF;
+    }
+  }
+
+  /* Get the PLL3 configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_PLL3RDY) != 0UL)
+  {
+    cfgr_value = RCC->PLL3CFGR1;
+    pRCC_OscInitStruct->PLL3.PLLState = RCC_PLL_ON;
+    pRCC_OscInitStruct->PLL3.PLLSource = (cfgr_value & RCC_PLL3CFGR1_PLL3SEL);
+    pRCC_OscInitStruct->PLL3.PLLM = ((cfgr_value & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos);
+    pRCC_OscInitStruct->PLL3.PLLN = ((cfgr_value & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos);
+    pRCC_OscInitStruct->PLL3.PLLFractional = (READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> \
+                                              RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos);
+    cfgr_value = RCC->PLL3CFGR3;
+    pRCC_OscInitStruct->PLL3.PLLP1 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos);
+    pRCC_OscInitStruct->PLL3.PLLP2 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos);
+  }
+  else
+  {
+    cfgr_value = RCC->PLL3CFGR1;
+    if ((cfgr_value & RCC_PLL3CFGR1_PLL3BYP) != 0UL)
+    {
+      pRCC_OscInitStruct->PLL3.PLLState = RCC_PLL_BYPASS;
+    }
+    else
+    {
+      pRCC_OscInitStruct->PLL3.PLLState = RCC_PLL_OFF;
+    }
+  }
+
+  /* Get the PLL4 configuration -----------------------------------------------*/
+  if ((sr_value & RCC_SR_PLL4RDY) != 0UL)
+  {
+    cfgr_value = RCC->PLL4CFGR1;
+    pRCC_OscInitStruct->PLL4.PLLState = RCC_PLL_ON;
+    pRCC_OscInitStruct->PLL4.PLLSource = (cfgr_value & RCC_PLL4CFGR1_PLL4SEL);
+    pRCC_OscInitStruct->PLL4.PLLM = ((cfgr_value & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos);
+    pRCC_OscInitStruct->PLL4.PLLN = ((cfgr_value & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos);
+    pRCC_OscInitStruct->PLL4.PLLFractional = (READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> \
+                                              RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos);
+    cfgr_value = RCC->PLL4CFGR3;
+    pRCC_OscInitStruct->PLL4.PLLP1 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos);
+    pRCC_OscInitStruct->PLL4.PLLP2 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos);
+  }
+  else
+  {
+    cfgr_value = RCC->PLL4CFGR1;
+    if ((cfgr_value & RCC_PLL4CFGR1_PLL4BYP) != 0UL)
+    {
+      pRCC_OscInitStruct->PLL4.PLLState = RCC_PLL_BYPASS;
+    }
+    else
+    {
+      pRCC_OscInitStruct->PLL4.PLLState = RCC_PLL_OFF;
+    }
+  }
+}
+
+/**
+  * @brief  Get the clocks status configuration in RCC_ClkInitStruct according to
+  *         the internal RCC configuration registers.
+  * @param  pRCC_ClkInitStruct  Pointer to an RCC_ClkInitTypeDef structure that
+  *         will return the configuration.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *pRCC_ClkInitStruct)
+{
+  uint32_t cfgr_value;
+
+  /* Set all possible values for the Clock type parameter --------------------*/
+  pRCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | \
+                                  RCC_CLOCKTYPE_HCLK   | \
+                                  RCC_CLOCKTYPE_PCLK1  | RCC_CLOCKTYPE_PCLK2 | \
+                                  RCC_CLOCKTYPE_PCLK4  | RCC_CLOCKTYPE_PCLK5;
+
+  /* Get the configuration register 1 value */
+  cfgr_value = RCC->CFGR1;
+
+  /* Get the active CPU source -----------------------------------------------*/
+  pRCC_ClkInitStruct->CPUCLKSource = (cfgr_value & RCC_CFGR1_CPUSWS) >> 4U;
+
+  /* Get the active SYSCLK bus source ----------------------------------------*/
+  pRCC_ClkInitStruct->SYSCLKSource = (cfgr_value & RCC_CFGR1_SYSSWS) >> 4U;
+
+  /* Get the configuration register 2 value */
+  cfgr_value = RCC->CFGR2;
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  pRCC_ClkInitStruct->AHBCLKDivider = (cfgr_value & RCC_CFGR2_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  pRCC_ClkInitStruct->APB1CLKDivider = (cfgr_value & RCC_CFGR2_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  pRCC_ClkInitStruct->APB2CLKDivider = (cfgr_value & RCC_CFGR2_PPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  pRCC_ClkInitStruct->APB4CLKDivider = (cfgr_value & RCC_CFGR2_PPRE4);
+
+  /* Get the APB5 configuration ----------------------------------------------*/
+  pRCC_ClkInitStruct->APB5CLKDivider = (cfgr_value & RCC_CFGR2_PPRE5);
+
+  /* Get the IC1 configuration -----------------------------------------------*/
+  cfgr_value = RCC->IC1CFGR;
+  pRCC_ClkInitStruct->IC1Selection.ClockSelection = cfgr_value & RCC_IC1CFGR_IC1SEL;
+  pRCC_ClkInitStruct->IC1Selection.ClockDivider = ((cfgr_value & RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1U;
+
+  /* Get the IC2 configuration -----------------------------------------------*/
+  cfgr_value = RCC->IC2CFGR;
+  pRCC_ClkInitStruct->IC2Selection.ClockSelection = cfgr_value & RCC_IC2CFGR_IC2SEL;
+  pRCC_ClkInitStruct->IC2Selection.ClockDivider = ((cfgr_value & RCC_IC2CFGR_IC2INT) >> RCC_IC2CFGR_IC2INT_Pos) + 1U;
+
+  /* Get the IC6 configuration -----------------------------------------------*/
+  cfgr_value = RCC->IC6CFGR;
+  pRCC_ClkInitStruct->IC6Selection.ClockSelection = cfgr_value & RCC_IC6CFGR_IC6SEL;
+  pRCC_ClkInitStruct->IC6Selection.ClockDivider = ((cfgr_value & RCC_IC6CFGR_IC6INT) >> RCC_IC6CFGR_IC6INT_Pos) + 1U;
+
+  /* Get the IC11 configuration ----------------------------------------------*/
+  cfgr_value = RCC->IC11CFGR;
+  pRCC_ClkInitStruct->IC11Selection.ClockSelection = cfgr_value & RCC_IC11CFGR_IC11SEL;
+  pRCC_ClkInitStruct->IC11Selection.ClockDivider = ((cfgr_value & RCC_IC11CFGR_IC11INT) >> RCC_IC11CFGR_IC11INT_Pos) + 1U;
+}
+
+/**
+  * @brief This function handles the RCC HSE CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC HCECSSF interrupt flag  */
+  if (LL_RCC_IsActiveFlag_HSECSS() == 1U)
+  {
+    /* Clear RCC HSE Clock Security System pending flag */
+    LL_RCC_ClearFlag_HSECSS();
+
+    /* RCC HSE Clock Security System interrupt user callback */
+    HAL_RCC_CSSCallback();
+  }
+}
+
+/**
+  * @brief  RCC HSE Clock Security System interrupt callback
+  * @retval none
+  */
+__weak void HAL_RCC_CSSCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RCC_CSSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions
+  *  @brief Attributes management functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### RCC attributes functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to:
+
+    (+) Configure the RCC item(s) attribute(s).
+    (+) Get the attribute of an RCC item.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the RCC item(s) attribute(s).
+  * @note   Available attributes are to control the secure, privileged, public and lock access rights of items.
+  *         Default access rights are non-secure, unprivileged, non-public and unlocked.
+  * @note   Secure/non-secure, privileged/unprivileged and public/non-public attributes can be set and reset
+  *         from the secure/privileged state only.
+  * @note   Lock Item attribute can be set from the secure/privileged state only.
+  * @param  Item Item(s) to set attributes on.
+  *         This parameter can be a one value or a combination of @ref RCC_items belonging to the same group of items
+  *         (eg. RCC_ITEM_GROUP_OSC)
+  * @param  Attributes specifies the RCC secure/privilege/public attributes.
+  *         This parameter can be a combination of @ref RCC_attributes
+  * @retval None
+  *
+  */
+void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_ATTRIBUTES(Attributes));
+  assert_param(IS_RCC_ITEM_ATTRIBUTES(Item));
+
+  /* Check then configure items groups */
+  /* Oscillators group */
+  if ((Item & RCC_ITEM_GROUP_OSC) == RCC_ITEM_GROUP_OSC)
+  {
+    RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_OSC, Item & RCC_ITEM_GROUP_OSC_MASK, Attributes);
+  }
+
+  /* PLLs group */
+  if ((Item & RCC_ITEM_GROUP_PLL) == RCC_ITEM_GROUP_PLL)
+  {
+    RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_PLL, Item & RCC_ITEM_GROUP_PLL_MASK, Attributes);
+  }
+
+  /* ICxs group */
+  if ((Item & RCC_ITEM_GROUP_IC) == RCC_ITEM_GROUP_IC)
+  {
+    RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_IC, Item & RCC_ITEM_GROUP_IC_MASK, Attributes);
+  }
+
+  /* System configs group */
+  if ((Item & RCC_ITEM_GROUP_SYSCFG) == RCC_ITEM_GROUP_SYSCFG)
+  {
+    RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_SYSCFG, Item & RCC_ITEM_GROUP_SYSCFG_MASK, Attributes);
+  }
+
+  /* Buses group */
+  if ((Item & RCC_ITEM_GROUP_BUS) == RCC_ITEM_GROUP_BUS)
+  {
+    RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_BUS, Item & RCC_ITEM_GROUP_BUS_MASK, Attributes);
+  }
+
+  /* Memories group */
+  if ((Item & RCC_ITEM_GROUP_MEM) == RCC_ITEM_GROUP_MEM)
+  {
+    RCC_ATTR_ConfigItemGroup(RCC_ITEM_GROUP_IDX_MEM, Item & RCC_ITEM_GROUP_MEM_MASK, Attributes);
+  }
+}
+
+/**
+  * @brief  Get the attributes of an RCC item.
+  * @note   Secured items are available from non-secure state when set as public
+  * @param  Item A single item to get secure/non-secure, public/non-public, privilege/non-privilege and locked
+        attributes from. This parameter can be a value of RCC_items.
+  * @param  pAttributes pointer to return the attributes (this is a combination of @ref RCC_attributes).
+  * @retval HAL Status.
+  *
+  */
+HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
+{
+  uint32_t attributes = 0UL;
+
+  /* Check null pointer */
+  if (pAttributes == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_SINGLE_ITEM_ATTRIBUTES(Item));
+
+  /* Get the item group index and compute the attribute base register address*/
+  uint32_t ItemGroup = (Item & RCC_ITEM_GROUP_MASK) >> RCC_ITEM_GROUP_POS;
+  uint32_t ItemGroupIdx = 0UL;
+  while ((ItemGroup >> ItemGroupIdx) != 1UL)
+  {
+    ItemGroupIdx++;
+  }
+
+  __IO const uint32_t *p_rcc_reg = &(RCC->SECCFGR0) + (0x4UL * ItemGroupIdx);
+
+  if ((Item & RCC_ITEM_GROUP_MASK) != RCC_ITEM_GROUP_MEM)
+  {
+    /* Get secure attribute */
+    attributes |= ((p_rcc_reg[0] & Item) == 0U) ? RCC_ATTR_NSEC : RCC_ATTR_SEC;
+
+    /* Get privilege attribute */
+    attributes |= ((p_rcc_reg[1] & Item) == 0U) ? RCC_ATTR_NPRIV : RCC_ATTR_PRIV;
+
+    /* Get lock attribute */
+    attributes |= ((p_rcc_reg[2] & Item) == 0U) ? RCC_ATTR_NLOCK : RCC_ATTR_LOCK;
+
+    /* Get public attribute */
+    attributes |= ((p_rcc_reg[3] & Item) == 0U) ? RCC_ATTR_NPUB : RCC_ATTR_PUB;
+  }
+  else
+  {
+    /* For memory group, only public attribute is available */
+    attributes |= ((*p_rcc_reg & Item) == 0U) ? RCC_ATTR_NPUB : RCC_ATTR_PUB;
+  }
+
+  /* Return value */
+  *pAttributes = attributes;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Private_functions RCC Private Functions
+  * @{
+  */
+/**
+  * @brief  Configure the requested PLL
+  * @param  PLLnumber PLL number to configure
+  * @param  pPLLInit Pointer to an RCC_PLLInitTypeDef structure that
+  *                  contains the configuration parameters.
+  * @note   PLL is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit)
+{
+  __IO uint32_t *p_rcc_pll_cfgr1_reg;
+  __IO uint32_t *p_rcc_pll_cfgr2_reg;
+  __IO uint32_t *p_rcc_pll_cfgr3_reg;
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t tickstart;
+
+  p_rcc_pll_cfgr1_reg = &(RCC->PLL1CFGR1) + (((uint32_t)0x4) * PLLnumber);
+  p_rcc_pll_cfgr2_reg = &(RCC->PLL1CFGR2) + (((uint32_t)0x4) * PLLnumber);
+  p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber);
+
+  /* !!! WARNING: ONLY INTEGER AND FRACTIONAL MODES MANAGED TODAY !!! */
+  if (pPLLInit->PLLState == RCC_PLL_ON)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource));
+    assert_param(IS_RCC_PLLFRACN_VALUE(pPLLInit->PLLFractional));
+    assert_param(IS_RCC_PLLM_VALUE(pPLLInit->PLLM));
+    assert_param(IS_RCC_PLLN_VALUE(pPLLInit->PLLN));
+    assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP1));
+    assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2));
+
+    /* Ensure PLLx is disabled */
+    WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLx is disabled */
+    while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber))
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Ensure PLLxMODSSDIS='1' */
+    SET_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS);
+
+    /* Clear bypass mode */
+    CLEAR_BIT(*p_rcc_pll_cfgr1_reg, RCC_PLL1CFGR1_PLL1BYP);
+
+    /* Configure the PLLx clock source, multiplication and division factors. */
+    MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \
+               (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \
+                | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos)));
+    MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \
+               ((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos)));
+
+    /* Configure PLLx DIVNFRAC */
+    MODIFY_REG(*p_rcc_pll_cfgr2_reg, RCC_PLL1CFGR2_PLL1DIVNFRAC, \
+               pPLLInit->PLLFractional << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
+
+    /* Clear PLLxMODDSEN (Also clear in Fractional Mode to ensure the latch of updated FRAC value when set again) */
+    CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODDSEN);
+
+    /* Fractional Mode specificities Management */
+    if (pPLLInit->PLLFractional != 0U)
+    {
+      /* Set PLLxMODDSEN and DACEN */
+      SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN));
+    }
+
+    /* Ensure PLLxMODSSRST='1' and Enable PLLx post divider output */
+    SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODSSRST | RCC_PLL1CFGR3_PLL1PDIVEN));
+
+    /* Enable the PLLx */
+    WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS << PLLnumber);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLx is ready */
+    while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else if (pPLLInit->PLLState == RCC_PLL_BYPASS)
+  {
+    assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource));
+
+    /* Check selected source is ready */
+    if (RCC_PLL_Source_IsReady(pPLLInit->PLLSource) == 1U)
+    {
+      /* Ensure PLLx is disabled */
+      WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber);
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till PLLx is disabled */
+      while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber))
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Set bypass mode with selected source */
+      MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1BYP | RCC_PLL1CFGR1_PLL1SEL), \
+                 (RCC_PLL1CFGR1_PLL1BYP | pPLLInit->PLLSource));
+    }
+    else
+    {
+      ret = HAL_ERROR;
+    }
+  }
+  else if (pPLLInit->PLLState == RCC_PLL_OFF)
+  {
+    /* Disable PLLx post divider output */
+    CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1PDIVEN);
+
+    /* Ensure PLLx is disabled */
+    WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLx is disabled */
+    while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber))
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Clear bypass mode */
+    CLEAR_BIT(*p_rcc_pll_cfgr1_reg, RCC_PLL1CFGR1_PLL1BYP);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Enable the requested PLL
+  * @param  PLLnumber PLL number to enable
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCC_PLL_Enable(uint32_t PLLnumber)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t tickstart;
+
+  /* Enable the PLLx */
+  WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS << PLLnumber);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait till PLLx is ready */
+  while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Check for a new PLL configuration
+  * @param  PLLnumber PLL number
+  * @param  pPLLInit Pointer to an RCC_PLLInitTypeDef structure that
+  *                  contains the configuration parameters.  *
+  * @retval 1 if success else 0
+  */
+static uint32_t RCC_PLL_IsNewConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit)
+{
+  __IO const uint32_t *p_rcc_pll_cfgr1_reg, *p_rcc_pll_cfgr2_reg, *p_rcc_pll_cfgr3_reg;
+  uint32_t ret = 0U;
+
+  /* No assert since done in calling function */
+
+  p_rcc_pll_cfgr1_reg = &(RCC->PLL1CFGR1) + (((uint32_t)0x4) * PLLnumber);
+  p_rcc_pll_cfgr2_reg = &(RCC->PLL1CFGR2) + (((uint32_t)0x4) * PLLnumber);
+  p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber);
+
+  /* !!! WARNING: ONLY INTEGER AND FRACTIONAL MODES MANAGED TODAY !!! */
+
+  /* Check for PLLCFGR1, PLLCFGR2 and PLLCFGR3 parameters updates */
+  if ((*p_rcc_pll_cfgr1_reg & (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN)) != \
+      (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \
+       | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos)))
+  {
+    ret = 1U; /* New PLL configuration */
+  }
+  else if ((*p_rcc_pll_cfgr2_reg & RCC_PLL1CFGR2_PLL1DIVNFRAC) != \
+           (pPLLInit->PLLFractional << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos))
+  {
+    ret = 1U; /* New PLL configuration */
+  }
+  else if ((*p_rcc_pll_cfgr3_reg & (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2)) != \
+           ((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos)))
+  {
+    ret = 1U; /* New PLL configuration */
+  }
+  else
+  {
+    /* Mode change detection*/
+    uint32_t pllState;
+
+    /* Get current Mode*/
+    if (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber))
+    {
+      pllState = RCC_PLL_ON;
+    }
+    else
+    {
+      if ((*p_rcc_pll_cfgr1_reg & RCC_PLL1CFGR1_PLL1BYP) != 0UL)
+      {
+        pllState = RCC_PLL_BYPASS;
+      }
+      else
+      {
+        pllState = RCC_PLL_OFF;
+      }
+    }
+
+    /* Compare with new mode */
+    if (pllState != pPLLInit->PLLState)
+    {
+      ret = 1U; /* New PLL configuration */
+    }
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Check whether the PLL source is ready
+  * @param  PLLSource PLL source
+  * @retval 1 if success else 0
+  */
+static uint32_t RCC_PLL_Source_IsReady(uint32_t PLLSource)
+{
+  uint32_t ret = 1U;
+
+  /* No assert since done in calling function */
+
+  switch (PLLSource)
+  {
+    case RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() == 0U)
+      {
+        ret = 0U;
+      }
+      break;
+    case RCC_PLLSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() == 0U)
+      {
+        ret = 0U;
+      }
+      break;
+    case RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() == 0U)
+      {
+        ret = 0U;
+      }
+      break;
+    case RCC_PLLSOURCE_PIN:
+    default:
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Check whether PLL sources are available
+  * @param  PLLSource1 First PLL source
+  * @param  PLLSource2 Second PLL source
+  * @retval 1 if success else 0
+  */
+static uint32_t RCC_IC_CheckPLLSources(uint32_t PLLSource1, uint32_t PLLSource2)
+{
+  uint32_t ret = 1U;
+
+  /* No assert since done in calling function */
+
+  /* Check PLLSource1 clock source */
+  switch (PLLSource1)
+  {
+    case LL_RCC_ICCLKSOURCE_PLL1:
+      if (LL_RCC_PLL1_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL1_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    case LL_RCC_ICCLKSOURCE_PLL2:
+      if (LL_RCC_PLL2_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL2_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    case LL_RCC_ICCLKSOURCE_PLL3:
+      if (LL_RCC_PLL3_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL3_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    case LL_RCC_ICCLKSOURCE_PLL4:
+      if (LL_RCC_PLL4_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL4_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    default:
+      /* Unexpected */
+      ret = 0U;
+      break;
+  }
+
+  /* Check PLLSource2 clock source */
+  switch (PLLSource2)
+  {
+    case LL_RCC_ICCLKSOURCE_PLL1:
+      if (LL_RCC_PLL1_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL1_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    case LL_RCC_ICCLKSOURCE_PLL2:
+      if (LL_RCC_PLL2_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL2_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    case LL_RCC_ICCLKSOURCE_PLL3:
+      if (LL_RCC_PLL3_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL3_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    case LL_RCC_ICCLKSOURCE_PLL4:
+      if (LL_RCC_PLL4_IsReady() == 0U)
+      {
+        if (LL_RCC_PLL4_IsEnabledBypass() == 0U)
+        {
+          ret = 0U;
+        }
+      }
+      break;
+    default:
+      /* Unexpected */
+      ret = 0U;
+      break;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Attribute configuration of a group of Items.
+  * @param  ItemGroupIdx the Item group Index to configure
+  * @param  Item Item(s) to set attributes on.
+  *         This parameter can be a one or a combination of @ref RCC_items, masked with RCC_ITEM_MASK
+  * @param  Attributes specifies the RCC secure/privilege/public/lock attributes.
+  *         This parameter can be a combination of @ref RCC_attributes
+  * @retval None
+  */
+static void RCC_ATTR_ConfigItemGroup(uint32_t ItemGroupIdx, uint32_t Item, uint32_t Attributes)
+{
+  __IO uint32_t *p_rcc_reg = &(RCC->SECCFGR0) + (0x4UL * ItemGroupIdx);
+
+  if (ItemGroupIdx != RCC_ITEM_GROUP_IDX_MEM)
+  {
+#if defined (CPU_IN_SECURE_STATE)
+    /* Check item security attribute management */
+    if ((Attributes & RCC_ATTR_SEC_MASK) == RCC_ATTR_SEC_MASK)
+    {
+      /* Configure item security attribute */
+      if ((Attributes & RCC_ATTR_SEC) == RCC_ATTR_SEC)
+      {
+        SET_BIT(p_rcc_reg[0], Item);
+      }
+      else
+      {
+        CLEAR_BIT(p_rcc_reg[0], Item);
+      }
+    }
+#endif /* CPU_IN_SECURE_STATE */
+
+    /* Check item privilege attribute management */
+    if ((Attributes & RCC_ATTR_PRIV_MASK) == RCC_ATTR_PRIV_MASK)
+    {
+      /* Configure item privilege attribute */
+      if ((Attributes & RCC_ATTR_PRIV) == RCC_ATTR_PRIV)
+      {
+        SET_BIT(p_rcc_reg[1], Item);
+      }
+      else
+      {
+        CLEAR_BIT(p_rcc_reg[1], Item);
+      }
+    }
+
+#if defined (CPU_IN_SECURE_STATE)
+    /* Check item lock attribute management */
+    if ((Attributes & RCC_ATTR_LOCK_MASK) == RCC_ATTR_LOCK_MASK)
+    {
+      /* Configure item lock attribute */
+      if ((Attributes & RCC_ATTR_LOCK) == RCC_ATTR_LOCK)
+      {
+        SET_BIT(p_rcc_reg[2], Item);
+      }
+    }
+
+    /* Check item public attribute management */
+    if ((Attributes & RCC_ATTR_PUB_MASK) == RCC_ATTR_PUB_MASK)
+    {
+      /* Configure item public attribute */
+      if ((Attributes & RCC_ATTR_PUB) == RCC_ATTR_PUB)
+      {
+        SET_BIT(p_rcc_reg[3], Item);
+      }
+      else
+      {
+        CLEAR_BIT(p_rcc_reg[3], Item);
+      }
+    }
+#endif /* CPU_IN_SECURE_STATE */
+  }
+  else
+  {
+    /* For memory group, only public attribute is available */
+#if defined (CPU_IN_SECURE_STATE)
+    /* Check item public attribute management */
+    if ((Attributes & RCC_ATTR_PUB_MASK) == RCC_ATTR_PUB_MASK)
+    {
+      /* Configure item public attribute */
+      if ((Attributes & RCC_ATTR_PUB) == RCC_ATTR_PUB)
+      {
+        SET_BIT(*(p_rcc_reg), Item);
+      }
+      else
+      {
+        CLEAR_BIT(*(p_rcc_reg), Item);
+      }
+    }
+#endif /* CPU_IN_SECURE_STATE */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rcc_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rcc_ex.c
new file mode 100644
index 000000000..525b58c1b
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rcc_ex.c
@@ -0,0 +1,5945 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx  RCCEx
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+  * @{
+  */
+#if defined(USE_FPGA)
+/* ***** FPGA values ******/
+#define RCC_PLL_SOURCE_FREQ   32000000UL  /* PLL source forced to 32MHz */
+#endif /* USE_FPGA */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCCEx_Private_Functions_Prototypes RCCEx Private Functions Prototypes
+  * @{
+  */
+static uint32_t RCCEx_GetHCLKFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCCEx_GetPCLK1Freq(uint32_t HCLK_Frequency);
+static uint32_t RCCEx_GetPCLK2Freq(uint32_t PCLK_Frequency);
+static uint32_t RCCEx_GetPCLK4Freq(uint32_t PCLK_Frequency);
+static uint32_t RCCEx_GetPCLK5Freq(uint32_t PCLK_Frequency);
+static uint32_t RCCEx_GetPLLSourceFreq(uint32_t PLLsource);
+static uint32_t RCCEx_CalcPLLFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N,
+                                  uint32_t FRACN, uint32_t P1, uint32_t P2);
+static uint32_t RCCEx_GetADCCLKFreq(uint32_t ADCxSource);
+static uint32_t RCCEx_GetADFCLKFreq(uint32_t ADFxSource);
+static uint32_t RCCEx_GetCLKPCLKFreq(uint32_t CLKPxSource);
+static uint32_t RCCEx_GetCSICLKFreq(void);
+static uint32_t RCCEx_GetDCMIPPCLKFreq(uint32_t DCMIPPxSource);
+static uint32_t RCCEx_GetETH1CLKFreq(uint32_t ETH1xSource);
+static uint32_t RCCEx_GetETH1PTPCLKFreq(uint32_t ETH1PTPxSource);
+static uint32_t RCCEx_GetFDCANCLKFreq(uint32_t FDCANxSource);
+static uint32_t RCCEx_GetFMCCLKFreq(uint32_t FMCxSource);
+static uint32_t RCCEx_GetI2CCLKFreq(uint32_t I2CxSource);
+static uint32_t RCCEx_GetI3CCLKFreq(uint32_t I3CxSource);
+static uint32_t RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource);
+static uint32_t RCCEx_GetLPUARTCLKFreq(uint32_t LPUARTxSource);
+static uint32_t RCCEx_GetLTDCCLKFreq(uint32_t LPTIMxSource);
+static uint32_t RCCEx_GetMDFCLKFreq(uint32_t MDFxSource);
+static uint32_t RCCEx_GetPSSICLKFreq(uint32_t PSSIxSource);
+static uint32_t RCCEx_GetRTCCLKFreq(void);
+static uint32_t RCCEx_GetSAICLKFreq(uint32_t SAIxSource);
+static uint32_t RCCEx_GetSDMMCCLKFreq(uint32_t SDMMCxSource);
+static uint32_t RCCEx_GetSPDIFRXCLKFreq(uint32_t SPDIFRXxSource);
+static uint32_t RCCEx_GetSPICLKFreq(uint32_t SPIxSource);
+static uint32_t RCCEx_GetUARTCLKFreq(uint32_t UARTxSource);
+static uint32_t RCCEx_GetUSARTCLKFreq(uint32_t USARTxSource);
+static uint32_t RCCEx_GetOTGPHYCLKFreq(uint32_t OTGPHYxSource);
+static uint32_t RCCEx_GetOTGPHYCKREFCLKFreq(uint32_t OTGPHYxCKREFSource);
+static uint32_t RCCEx_GetXSPICLKFreq(uint32_t XSPIxSource);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  *  @brief  Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals clocks
+  *         (ADC, ADF1, CKPER, DCMI, DCMIPP, FDCAN, FMC, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2,
+  *         LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LTDC, LPUART1, MDF1, PSSI, RTC, SAI1, SAI2,
+  *         SDMMC1, SDMMC2, SPDIFRX1, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, TIM,
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, UART9, USART10,
+  *         USBPHY1, USBPHY2, USB OTGHS1, USB OTGHS2, XSPI1, XSPI2, XSPI3).
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) are set to their reset values.
+  * @note   Dynamic switches are used for peripheral input clock selection meaning the switch setting
+  *         can only be changed if both input clocks are present during transition time.
+  * @note   Care must be taken when RCC_PPPCLKSOURCE_ICx is selected. The ICx ClockSelection and ClockDivider fields
+  *         modification indeed impacts all peripherals using this ICx as clock source.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tmpreg;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*---------------------------- RTC configuration -------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* As the RTC clock source selection can be changed only if the Backup Domain is reset */
+    /* reset the Backup domain only if the RTC Clock source selection is modified from default reset value */
+    tmpreg = LL_RCC_GetRTCClockSource();
+
+    if ((tmpreg != RCC_RTCCLKSOURCE_DISABLE) && (tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CCIPR7_RTCSEL)))
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
+
+      /* Read back to check Backup domain enabled */
+      if (READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == 0U)
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+#if 0 /* TO DO */
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        /* excepted the RTC clock source selection that will be changed */
+        tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
+        /* Restore the content of BDCR register */
+        WRITE_REG(RCC->BDCR, tmpreg);
+#endif /* #if 0  TO DO */
+      }
+    }
+
+    if (ret == HAL_OK)
+    {
+      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
+      if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while (LL_RCC_LSE_IsReady() == 0U)
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            ret = HAL_TIMEOUT;
+            break;
+          }
+        }
+      }
+
+      if (ret == HAL_OK)
+      {
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------------ CKPER configuration --------------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection));
+
+    if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC5)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider));
+
+      /* Set IC5 configuration */
+      MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT,
+                 PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos));
+
+      LL_RCC_IC5_Enable();
+    }
+    else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC10)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
+
+      /* Set IC10 configuration */
+      MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
+                 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
+
+      LL_RCC_IC10_Enable();
+    }
+    else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC19)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC19].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC19].ClockDivider));
+
+      /* Set IC19 configuration */
+      MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL | RCC_IC19CFGR_IC19INT,
+                 PeriphClkInit->ICSelection[RCC_IC19].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC19].ClockDivider - 1U) << RCC_IC19CFGR_IC19INT_Pos));
+
+      LL_RCC_IC19_Enable();
+    }
+    else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC20)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC20].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC20].ClockDivider));
+
+      /* Set IC20 configuration */
+      MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL | RCC_IC20CFGR_IC20INT,
+                 PeriphClkInit->ICSelection[RCC_IC20].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC20].ClockDivider - 1U) << RCC_IC20CFGR_IC20INT_Pos));
+
+      LL_RCC_IC20_Enable();
+    }
+    else
+    {
+      /* No ICx selected as source */
+    }
+
+    /* Configure the CKPER clock source */
+    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
+  }
+
+  /*-------------------------- XSPI1 clock source configuration ----------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_XSPI1CLKSOURCE(PeriphClkInit->Xspi1ClockSelection));
+
+    if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_IC3)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
+
+      /* Set IC3 configuration */
+      MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
+                 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
+
+      LL_RCC_IC3_Enable();
+    }
+    else if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_IC4)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
+
+      /* Set IC4 configuration */
+      MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
+                 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
+
+      LL_RCC_IC4_Enable();
+    }
+    else if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Configure the XSPI1 clock source */
+    __HAL_RCC_XSPI1_CONFIG(PeriphClkInit->Xspi1ClockSelection);
+  }
+
+  /*-------------------------- XSPI2 clock source configuration ----------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_XSPI2CLKSOURCE(PeriphClkInit->Xspi2ClockSelection));
+
+    if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_IC3)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
+
+      /* Set IC3 configuration */
+      MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
+                 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
+
+      LL_RCC_IC3_Enable();
+    }
+    else if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_IC4)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
+
+      /* Set IC4 configuration */
+      MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
+                 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
+
+      LL_RCC_IC4_Enable();
+    }
+    else if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Configure the XSPI2 clock source */
+    __HAL_RCC_XSPI2_CONFIG(PeriphClkInit->Xspi2ClockSelection);
+  }
+
+  /*-------------------------- XSPI3 clock source configuration ----------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI3) == RCC_PERIPHCLK_XSPI3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_XSPI3CLKSOURCE(PeriphClkInit->Xspi3ClockSelection));
+
+    if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_IC3)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
+
+      /* Set IC3 configuration */
+      MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
+                 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
+
+      LL_RCC_IC3_Enable();
+    }
+    else if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_IC4)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
+
+      /* Set IC4 configuration */
+      MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
+                 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
+
+      LL_RCC_IC4_Enable();
+    }
+    else if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Configure the XSPI3 clock source */
+    __HAL_RCC_XSPI3_CONFIG(PeriphClkInit->Xspi3ClockSelection);
+  }
+
+  /*---------------------------- FMC configuration -------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection));
+
+    if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_IC3)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
+
+      /* Set IC3 configuration */
+      MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
+                 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
+
+      LL_RCC_IC3_Enable();
+    }
+    else if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_IC4)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
+
+      /* Set IC4 configuration */
+      MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
+                 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
+
+      LL_RCC_IC4_Enable();
+    }
+    else if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of FMC kernel clock*/
+    __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+  }
+
+  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
+
+    if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_IC4)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
+
+      /* Set IC4 configuration */
+      MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
+                 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
+
+      LL_RCC_IC4_Enable();
+    }
+    else if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_IC5)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider));
+
+      /* Set IC5 configuration */
+      MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT,
+                 PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos));
+
+      LL_RCC_IC5_Enable();
+    }
+    else if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SDMMC1 clock*/
+    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
+  }
+
+  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
+
+    if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_IC4)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
+
+      /* Set IC4 configuration */
+      MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
+                 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
+
+      LL_RCC_IC4_Enable();
+    }
+    else if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_IC5)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider));
+
+      /* Set IC5 configuration */
+      MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT,
+                 PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos));
+
+      LL_RCC_IC5_Enable();
+    }
+    else if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SDMMC2 clock*/
+    __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
+  }
+
+  /*---------------------------- ADC configuration -------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
+    assert_param(IS_RCC_ADCDIVIDER(PeriphClkInit->AdcDivider));
+
+    if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_IC7)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
+
+      /* Set IC7 configuration */
+      MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
+                 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
+
+      LL_RCC_IC7_Enable();
+    }
+    else if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Configure the ADC clock source and divider */
+    MODIFY_REG(RCC->CCIPR1, (RCC_CCIPR1_ADCPRE | RCC_CCIPR1_ADC12SEL), \
+               (((PeriphClkInit->AdcDivider - 1U) << RCC_CCIPR1_ADCPRE_Pos) | (PeriphClkInit->AdcClockSelection)));
+  }
+
+  /*---------------------------- ADF1 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ADF1CLKSOURCE(PeriphClkInit->Adf1ClockSelection));
+
+    if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_IC7)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
+
+      /* Set IC7 configuration */
+      MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
+                 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
+
+      LL_RCC_IC7_Enable();
+    }
+    else if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of ADF1 clock*/
+    __HAL_RCC_ADF1_CONFIG(PeriphClkInit->Adf1ClockSelection);
+  }
+
+  /*------------------------------------ CSI configuration --------------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CSI) == RCC_PERIPHCLK_CSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC18].ClockSelection));
+    assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC18].ClockDivider));
+
+    /* Set IC18 configuration */
+    MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL | RCC_IC18CFGR_IC18INT,
+               PeriphClkInit->ICSelection[RCC_IC18].ClockSelection | \
+               ((PeriphClkInit->ICSelection[RCC_IC18].ClockDivider - 1U) << RCC_IC18CFGR_IC18INT_Pos));
+
+    LL_RCC_IC18_Enable();
+  }
+
+  /*---------------------- DCMIPP configuration ------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_DCMIPP) == RCC_PERIPHCLK_DCMIPP)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DCMIPPCLKSOURCE(PeriphClkInit->DcmippClockSelection));
+
+    if (PeriphClkInit->DcmippClockSelection == RCC_DCMIPPCLKSOURCE_IC17)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC17].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC17].ClockDivider));
+
+      /* Set IC17 configuration */
+      MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL | RCC_IC17CFGR_IC17INT,
+                 PeriphClkInit->ICSelection[RCC_IC17].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC17].ClockDivider - 1U) << RCC_IC17CFGR_IC17INT_Pos));
+
+      LL_RCC_IC17_Enable();
+    }
+    else if (PeriphClkInit->DcmippClockSelection == RCC_DCMIPPCLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Configure the CEC clock source */
+    __HAL_RCC_DCMIPP_CONFIG(PeriphClkInit->DcmippClockSelection);
+  }
+
+  /*---------------------- ETH1 configuration --------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1) == RCC_PERIPHCLK_ETH1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ETH1CLKSOURCE(PeriphClkInit->Eth1ClockSelection));
+
+    if (PeriphClkInit->Eth1ClockSelection == RCC_ETH1CLKSOURCE_IC12)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC12].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC12].ClockDivider));
+
+      /* Set IC12 configuration */
+      MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL | RCC_IC12CFGR_IC12INT,
+                 PeriphClkInit->ICSelection[RCC_IC12].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC12].ClockDivider - 1U) << RCC_IC12CFGR_IC12INT_Pos));
+
+      LL_RCC_IC12_Enable();
+    }
+    else if (PeriphClkInit->Eth1ClockSelection == RCC_ETH1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Configure the ETH1 clock source */
+    __HAL_RCC_ETH1_CONFIG(PeriphClkInit->Eth1ClockSelection);
+  }
+
+  /*---------------------- ETH1PHY configuration -----------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ETH1PHYIF(PeriphClkInit->Eth1PhyInterfaceSelection));
+
+    /* Configure the source of ETH1 PHY interface */
+    __HAL_RCC_ETH1PHY_CONFIG(PeriphClkInit->Eth1PhyInterfaceSelection);
+  }
+
+  /*---------------------- ETH1 RX configuration -----------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1RX) == RCC_PERIPHCLK_ETH1RX)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ETH1RXCLKSOURCE(PeriphClkInit->Eth1RxClockSelection));
+
+    /* Configure the ETH1 RX clock source */
+    __HAL_RCC_ETH1RX_CONFIG(PeriphClkInit->Eth1RxClockSelection);
+  }
+
+  /*---------------------- ETH1 TX configuration -----------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1TX) == RCC_PERIPHCLK_ETH1TX)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ETH1TXCLKSOURCE(PeriphClkInit->Eth1TxClockSelection));
+
+    /* Configure the ETH1 TX clock source */
+    __HAL_RCC_ETH1TX_CONFIG(PeriphClkInit->Eth1TxClockSelection);
+  }
+
+  /*---------------------- ETH1 PTP configuration ----------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PTP) == RCC_PERIPHCLK_ETH1PTP)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_ETH1PTPCLKSOURCE(PeriphClkInit->Eth1PtpClockSelection));
+    assert_param(IS_RCC_ETH1PTPDIVIDER(PeriphClkInit->Eth1PtpDivider));
+
+    if (PeriphClkInit->Eth1PtpClockSelection == RCC_ETH1PTPCLKSOURCE_IC13)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC13].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC13].ClockDivider));
+
+      /* Set IC13 configuration */
+      MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL | RCC_IC13CFGR_IC13INT,
+                 PeriphClkInit->ICSelection[RCC_IC13].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC13].ClockDivider - 1U) << RCC_IC13CFGR_IC13INT_Pos));
+
+      LL_RCC_IC13_Enable();
+    }
+    else if (PeriphClkInit->Eth1PtpClockSelection == RCC_ETH1PTPCLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Configure the ETH1 PTP clock source and divider */
+    MODIFY_REG(RCC->CCIPR2, (RCC_CCIPR2_ETH1PTPDIV | RCC_CCIPR2_ETH1PTPSEL), \
+               (((PeriphClkInit->Eth1PtpDivider - 1U) << RCC_CCIPR2_ETH1PTPDIV_Pos) | PeriphClkInit->Eth1PtpClockSelection));
+  }
+
+  /*---------------------- FDCAN configuration -------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
+
+    if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_IC19)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC19].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC19].ClockDivider));
+
+      /* Set IC19 configuration */
+      MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL | RCC_IC19CFGR_IC19INT,
+                 PeriphClkInit->ICSelection[RCC_IC19].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC19].ClockDivider - 1U) << RCC_IC19CFGR_IC19INT_Pos));
+
+      LL_RCC_IC19_Enable();
+    }
+    else if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of FDCAN clock*/
+    __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+  }
+
+  /*------------------------------ I2C1 Configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+    if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_IC10)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
+
+      /* Set IC10 configuration */
+      MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
+                 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
+
+      LL_RCC_IC10_Enable();
+    }
+    else if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of I2C1 clock*/
+    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+  }
+
+  /*------------------------------ I2C2 Configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+    if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_IC10)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
+
+      /* Set IC10 configuration */
+      MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
+                 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
+
+      LL_RCC_IC10_Enable();
+    }
+    else if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of I2C2 clock*/
+    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+  }
+
+  /*------------------------------ I2C3 Configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+    if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_IC10)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
+
+      /* Set IC10 configuration */
+      MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
+                 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
+
+      LL_RCC_IC10_Enable();
+    }
+    else if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of I2C3 clock*/
+    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+  }
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_IC10)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
+
+      /* Set IC10 configuration */
+      MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
+                 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
+
+      LL_RCC_IC10_Enable();
+    }
+    else if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of I2C4 clock*/
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+  }
+
+  /*------------------------------ I3C1 Configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I3C1CLKSOURCE(PeriphClkInit->I3c1ClockSelection));
+
+    if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_IC10)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
+
+      /* Set IC10 configuration */
+      MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
+                 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
+
+      LL_RCC_IC10_Enable();
+    }
+    else if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of I3C1 clock*/
+    __HAL_RCC_I3C1_CONFIG(PeriphClkInit->I3c1ClockSelection);
+  }
+
+  /*------------------------------ I3C2 Configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I3C2CLKSOURCE(PeriphClkInit->I3c2ClockSelection));
+
+    if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_IC10)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
+
+      /* Set IC10 configuration */
+      MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
+                 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
+
+      LL_RCC_IC10_Enable();
+    }
+    else if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of I3C2 clock*/
+    __HAL_RCC_I3C2_CONFIG(PeriphClkInit->I3c2ClockSelection);
+  }
+
+  /*---------------------------- LPTIM1 configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+    if (PeriphClkInit->Lptim1ClockSelection == RCC_LPTIM1CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->Lptim1ClockSelection == RCC_LPTIM1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of LPTIM1 clock*/
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+  }
+
+  /*---------------------------- LPTIM2 configuration ------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
+
+    if (PeriphClkInit->Lptim2ClockSelection == RCC_LPTIM2CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->Lptim2ClockSelection == RCC_LPTIM2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of LPTIM2 clock*/
+    __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+  }
+
+  /*---------------------------- LPTIM3 configuration -----------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection));
+
+    if (PeriphClkInit->Lptim3ClockSelection == RCC_LPTIM3CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->Lptim3ClockSelection == RCC_LPTIM3CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of LPTIM3 clock */
+    __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection);
+  }
+
+  /*---------------------------- LPTIM4 configuration -----------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM4CLKSOURCE(PeriphClkInit->Lptim4ClockSelection));
+
+    if (PeriphClkInit->Lptim4ClockSelection == RCC_LPTIM4CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->Lptim4ClockSelection == RCC_LPTIM4CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of LPTIM4 clock */
+    __HAL_RCC_LPTIM4_CONFIG(PeriphClkInit->Lptim4ClockSelection);
+  }
+
+  /*---------------------------- LPTIM5 configuration -----------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM5CLKSOURCE(PeriphClkInit->Lptim5ClockSelection));
+
+    if (PeriphClkInit->Lptim5ClockSelection == RCC_LPTIM5CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->Lptim5ClockSelection == RCC_LPTIM5CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of LPTIM5 clock */
+    __HAL_RCC_LPTIM5_CONFIG(PeriphClkInit->Lptim5ClockSelection);
+  }
+
+  /*-------------------------- LPUART1 Configuration -------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
+
+    if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of LPUART1 clock */
+    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+  }
+
+  /*-------------------------- LTDC Configuration ----------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection));
+
+    if (PeriphClkInit->LtdcClockSelection == RCC_LTDCCLKSOURCE_IC16)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC16].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC16].ClockDivider));
+
+      /* Set IC16 configuration */
+      MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL | RCC_IC16CFGR_IC16INT,
+                 PeriphClkInit->ICSelection[RCC_IC16].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC16].ClockDivider - 1U) << RCC_IC16CFGR_IC16INT_Pos));
+
+      LL_RCC_IC16_Enable();
+    }
+    else if (PeriphClkInit->LtdcClockSelection == RCC_LTDCCLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of LTDC clock */
+    __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection);
+  }
+
+  /*---------------------------- MDF1 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_MDF1CLKSOURCE(PeriphClkInit->Mdf1ClockSelection));
+
+    if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_IC7)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
+
+      /* Set IC7 configuration */
+      MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
+                 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
+
+      LL_RCC_IC7_Enable();
+    }
+    else if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of MDF1 clock*/
+    __HAL_RCC_MDF1_CONFIG(PeriphClkInit->Mdf1ClockSelection);
+  }
+
+  /*---------------------------- PSSI configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_PSSICLKSOURCE(PeriphClkInit->PssiClockSelection));
+
+    if (PeriphClkInit->PssiClockSelection == RCC_PSSICLKSOURCE_IC20)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC20].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC20].ClockDivider));
+
+      /* Set IC20 configuration */
+      MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL | RCC_IC20CFGR_IC20INT,
+                 PeriphClkInit->ICSelection[RCC_IC20].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC20].ClockDivider - 1U) << RCC_IC20CFGR_IC20INT_Pos));
+
+      LL_RCC_IC20_Enable();
+    }
+    else if (PeriphClkInit->PssiClockSelection == RCC_PSSICLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of PSSI clock*/
+    __HAL_RCC_PSSI_CONFIG(PeriphClkInit->PssiClockSelection);
+  }
+
+  /*---------------------------- SAI1 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+    if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_IC7)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
+
+      /* Set IC7 configuration */
+      MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
+                 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
+
+      LL_RCC_IC7_Enable();
+    }
+    else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SAI1 clock*/
+    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+  }
+
+  /*---------------------------- SAI2 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+    if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_IC7)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
+
+      /* Set IC7 configuration */
+      MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
+                 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
+
+      LL_RCC_IC7_Enable();
+    }
+    else if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SAI2 clock*/
+    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+  }
+
+  /*---------------------------- SPDIFRX1 configuration -------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPDIFRX1) == RCC_PERIPHCLK_SPDIFRX1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPDIFRX1CLKSOURCE(PeriphClkInit->Spdifrx1ClockSelection));
+
+    if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_IC7)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
+
+      /* Set IC7 configuration */
+      MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
+                 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
+
+      LL_RCC_IC7_Enable();
+    }
+    else if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SPDIFRX1 clock */
+    __HAL_RCC_SPDIFRX1_CONFIG(PeriphClkInit->Spdifrx1ClockSelection);
+  }
+
+  /*---------------------------- SPI1 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
+
+    if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SPI1 clock*/
+    __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
+  }
+
+  /*---------------------------- SPI2 configuration ---------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPI2CLKSOURCE(PeriphClkInit->Spi2ClockSelection));
+
+    if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SPI2 clock*/
+    __HAL_RCC_SPI2_CONFIG(PeriphClkInit->Spi2ClockSelection);
+  }
+
+  /*---------------------------- SPI3 configuration ---------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPI3CLKSOURCE(PeriphClkInit->Spi3ClockSelection));
+
+    if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SPI3 clock*/
+    __HAL_RCC_SPI3_CONFIG(PeriphClkInit->Spi3ClockSelection);
+  }
+
+  /*---------------------------- SPI4 configuration -------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPI4CLKSOURCE(PeriphClkInit->Spi4ClockSelection));
+
+    if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SPI4 clock */
+    __HAL_RCC_SPI4_CONFIG(PeriphClkInit->Spi4ClockSelection);
+  }
+
+  /*---------------------------- SPI5 configuration -------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPI5CLKSOURCE(PeriphClkInit->Spi5ClockSelection));
+
+    if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SPI5 clock */
+    __HAL_RCC_SPI5_CONFIG(PeriphClkInit->Spi5ClockSelection);
+  }
+
+  /*---------------------------- SPI6 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection));
+
+    if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_IC8)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
+
+      /* Set IC8 configuration */
+      MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
+                 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
+
+      LL_RCC_IC8_Enable();
+    }
+    else if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of SPI6 clock*/
+    __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+  }
+
+  /*-------------------------- USART1 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+    if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of USART1 clock */
+    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+  }
+
+  /*-------------------------- USART2 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+    if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of USART2 clock */
+    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+  }
+
+  /*-------------------------- USART3 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+    if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of USART3 clock */
+    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+  }
+
+  /*-------------------------- UART4 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+    if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of UART4 clock */
+    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+  }
+
+  /*-------------------------- UART5 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+    if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of UART5 clock */
+    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+  }
+
+  /*-------------------------- USART6 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
+
+    if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of USART6 clock */
+    __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
+  }
+
+  /*-------------------------- UART7 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
+
+    if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of UART7 clock */
+    __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
+  }
+
+  /*-------------------------- UART8 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
+
+    if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of UART8 clock */
+    __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
+  }
+
+  /*-------------------------- UART9 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_UART9CLKSOURCE(PeriphClkInit->Uart9ClockSelection));
+
+    if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of UART9 clock */
+    __HAL_RCC_UART9_CONFIG(PeriphClkInit->Uart9ClockSelection);
+  }
+
+  /*-------------------------- USART10 configuration --------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USART10CLKSOURCE(PeriphClkInit->Usart10ClockSelection));
+
+    if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_IC9)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
+
+      /* Set IC9 configuration */
+      MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
+                 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
+
+      LL_RCC_IC9_Enable();
+    }
+    else if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_IC14)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
+
+      /* Set IC14 configuration */
+      MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
+                 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
+
+      LL_RCC_IC14_Enable();
+    }
+    else if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of USART10 clock */
+    __HAL_RCC_USART10_CONFIG(PeriphClkInit->Usart10ClockSelection);
+  }
+
+  /*------------------------------ USBPHY1 Configuration ---------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHY1) == RCC_PERIPHCLK_USBPHY1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USBPHY1CLKSOURCE(PeriphClkInit->UsbPhy1ClockSelection));
+
+    /* Set the source of USBPHY1 clock*/
+    __HAL_RCC_USBPHY1_CONFIG(PeriphClkInit->UsbPhy1ClockSelection);
+  }
+
+  /*------------------------------ USBPHY2 Configuration ---------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHY2) == RCC_PERIPHCLK_USBPHY2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USBPHY2CLKSOURCE(PeriphClkInit->UsbPhy2ClockSelection));
+
+    /* Set the source of USBPHY2 clock*/
+    __HAL_RCC_USBPHY2_CONFIG(PeriphClkInit->UsbPhy2ClockSelection);
+  }
+
+  /*------------------------------ USBOTGHS1 Configuration -------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGHS1) == RCC_PERIPHCLK_USBOTGHS1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USBOTGHS1CLKSOURCE(PeriphClkInit->UsbOtgHs1ClockSelection));
+
+    if (PeriphClkInit->UsbOtgHs1ClockSelection == RCC_USBOTGHS1CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->UsbOtgHs1ClockSelection == RCC_USBOTGHS1CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of USBOTGHS1 clock */
+    __HAL_RCC_USBOTGHS1_CONFIG(PeriphClkInit->UsbOtgHs1ClockSelection);
+  }
+
+  /*------------------------------ USBOTGHS2 Configuration -------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGHS2) == RCC_PERIPHCLK_USBOTGHS2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_USBOTGHS2CLKSOURCE(PeriphClkInit->UsbOtgHs2ClockSelection));
+
+    if (PeriphClkInit->UsbOtgHs2ClockSelection == RCC_USBOTGHS2CLKSOURCE_IC15)
+    {
+      /* Check the parameters */
+      assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
+      assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
+
+      /* Set IC15 configuration */
+      MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
+                 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
+                 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
+
+      LL_RCC_IC15_Enable();
+    }
+    else if (PeriphClkInit->UsbOtgHs2ClockSelection == RCC_USBOTGHS2CLKSOURCE_CLKP)
+    {
+      LL_RCC_CLKP_Enable();
+    }
+    else
+    {
+      /* No specific enable to do on other sources */
+    }
+
+    /* Set the source of USBOTGHS2 clock */
+    __HAL_RCC_USBOTGHS2_CONFIG(PeriphClkInit->UsbOtgHs2ClockSelection);
+  }
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER_CONFIG(PeriphClkInit->TIMPresSelection);
+  }
+
+  if (status == HAL_OK)
+  {
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals clocks :
+  *         (ADC, ADF1, CKPER, DCMI, DCMIPP, FDCAN, FMC, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2,
+  *         LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LTDC, LPUART1, MDF1, PSSI, RTC, SAI1, SAI2,
+  *         SDMMC1, SDMMC2, SPDIFRX1, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, TIM,
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, UART9, USART10,
+  *         USBPHYC, USB OTGFS, XSPI1, XSPI2, XSPI3).
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  const __IO uint32_t *p_icxcfgr;
+  uint32_t icx_val;
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_ADC      | RCC_PERIPHCLK_ADF1      | RCC_PERIPHCLK_CKPER    | \
+                                        RCC_PERIPHCLK_CSI      | RCC_PERIPHCLK_DCMIPP    | RCC_PERIPHCLK_ETH1     | \
+                                        RCC_PERIPHCLK_ETH1PHY  | RCC_PERIPHCLK_ETH1RX    | RCC_PERIPHCLK_ETH1TX   | \
+                                        RCC_PERIPHCLK_ETH1PTP  | RCC_PERIPHCLK_FDCAN     | RCC_PERIPHCLK_FMC      | \
+                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2      | RCC_PERIPHCLK_I2C3     | \
+                                        RCC_PERIPHCLK_I2C4     | RCC_PERIPHCLK_I3C1      | RCC_PERIPHCLK_I3C2     | \
+                                        RCC_PERIPHCLK_LPTIM1   | RCC_PERIPHCLK_LPTIM2    | RCC_PERIPHCLK_LPTIM3   | \
+                                        RCC_PERIPHCLK_LPTIM4   | RCC_PERIPHCLK_LPTIM5    | RCC_PERIPHCLK_LTDC     | \
+                                        RCC_PERIPHCLK_LPUART1  | RCC_PERIPHCLK_MDF1      | RCC_PERIPHCLK_PSSI     | \
+                                        RCC_PERIPHCLK_RTC      | RCC_PERIPHCLK_SAI1      | RCC_PERIPHCLK_SAI2     | \
+                                        RCC_PERIPHCLK_SDMMC1   | RCC_PERIPHCLK_SDMMC2    | RCC_PERIPHCLK_SPDIFRX1 | \
+                                        RCC_PERIPHCLK_SPI1     | RCC_PERIPHCLK_SPI2      | RCC_PERIPHCLK_SPI3     | \
+                                        RCC_PERIPHCLK_SPI4     | RCC_PERIPHCLK_SPI5      | RCC_PERIPHCLK_SPI6     | \
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_USART1    | RCC_PERIPHCLK_USART2   | \
+                                        RCC_PERIPHCLK_USART3   | RCC_PERIPHCLK_UART4     | RCC_PERIPHCLK_UART5    | \
+                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7     | RCC_PERIPHCLK_UART8    | \
+                                        RCC_PERIPHCLK_UART9    | RCC_PERIPHCLK_USART10   | \
+                                        RCC_PERIPHCLK_XSPI1    | RCC_PERIPHCLK_XSPI2     | RCC_PERIPHCLK_XSPI3    | \
+                                        RCC_PERIPHCLK_USBPHY1  | RCC_PERIPHCLK_USBOTGHS1 | \
+                                        RCC_PERIPHCLK_USBPHY2  | RCC_PERIPHCLK_USBOTGHS2;
+
+  /* Get IC x dividers */
+  p_icxcfgr = &(RCC->IC1CFGR);
+  for (uint32_t i = 0; i < 20U; i++)
+  {
+    icx_val = *p_icxcfgr;
+    PeriphClkInit->ICSelection[i].ClockSelection = (icx_val & RCC_IC1CFGR_IC1SEL) >> RCC_IC1CFGR_IC1SEL_Pos;
+    PeriphClkInit->ICSelection[i].ClockDivider = ((icx_val & RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1U;
+    p_icxcfgr++;
+  }
+
+  /* Get the ADC clock source ------------------------------------------------*/
+  PeriphClkInit->AdcClockSelection          = __HAL_RCC_GET_ADC_SOURCE();
+  /* Get the ADC divider ------------------------------------------------*/
+  PeriphClkInit->AdcDivider                 = __HAL_RCC_GET_ADC_DIVIDER();
+  /* Get the ADF1 clock source -----------------------------------------------*/
+  PeriphClkInit->Adf1ClockSelection         = __HAL_RCC_GET_ADF1_SOURCE();
+  /* Get the CKPER clock source ----------------------------------------------*/
+  PeriphClkInit->CkperClockSelection        = __HAL_RCC_GET_CLKP_SOURCE();
+  /* Get the DCMIPP clock source ---------------------------------------------*/
+  PeriphClkInit->DcmippClockSelection       = __HAL_RCC_GET_DCMIPP_SOURCE();
+  /* Get the ETH1 clock source -----------------------------------------------*/
+  PeriphClkInit->Eth1ClockSelection         = __HAL_RCC_GET_ETH1_SOURCE();
+  /* Get the ETH1 PHY interface ----------------------------------------------*/
+  PeriphClkInit->Eth1PhyInterfaceSelection  = __HAL_RCC_GET_ETH1PHY_INTERFACE();
+  /* Get the ETH1 RX clock source --------------------------------------------*/
+  PeriphClkInit->Eth1RxClockSelection       = __HAL_RCC_GET_ETH1RX_SOURCE();
+  /* Get the ETH1 TX clock source --------------------------------------------*/
+  PeriphClkInit->Eth1TxClockSelection       = __HAL_RCC_GET_ETH1TX_SOURCE();
+  /* Get the ETH1 PTP clock source -------------------------------------------*/
+  PeriphClkInit->Eth1PtpClockSelection      = __HAL_RCC_GET_ETH1PTP_SOURCE();
+  /* Get the ETH1 PTP divider ------------------------------------------------*/
+  PeriphClkInit->Eth1PtpDivider             = __HAL_RCC_GET_ETH1PTP_DIVIDER();
+  /* Get the FDCAN kernel clock source ---------------------------------------*/
+  PeriphClkInit->FdcanClockSelection        = __HAL_RCC_GET_FDCAN_SOURCE();
+  /* Get the FMC kernel clock source -----------------------------------------*/
+  PeriphClkInit->FmcClockSelection          = __HAL_RCC_GET_FMC_SOURCE();
+  /* Get the I2C1 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c1ClockSelection         = __HAL_RCC_GET_I2C1_SOURCE();
+  /* Get the I2C2 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c2ClockSelection         = __HAL_RCC_GET_I2C2_SOURCE();
+  /* Get the I2C3 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c3ClockSelection         = __HAL_RCC_GET_I2C3_SOURCE();
+  /* Get the I2C4 clock source -----------------------------------------------*/
+  PeriphClkInit->I2c4ClockSelection         = __HAL_RCC_GET_I2C4_SOURCE();
+  /* Get the I3C1 clock source -----------------------------------------------*/
+  PeriphClkInit->I3c1ClockSelection         = __HAL_RCC_GET_I3C1_SOURCE();
+  /* Get the I3C2 clock source -----------------------------------------------*/
+  PeriphClkInit->I3c2ClockSelection         = __HAL_RCC_GET_I3C2_SOURCE();
+  /* Get the LPTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection       = __HAL_RCC_GET_LPTIM1_SOURCE();
+  /* Get the LPTIM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim2ClockSelection       = __HAL_RCC_GET_LPTIM2_SOURCE();
+  /* Get the LPTIM3 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim3ClockSelection       = __HAL_RCC_GET_LPTIM3_SOURCE();
+  /* Get the LPTIM4 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim4ClockSelection       = __HAL_RCC_GET_LPTIM4_SOURCE();
+  /* Get the LPTIM5 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim5ClockSelection       = __HAL_RCC_GET_LPTIM5_SOURCE();
+  /* Get the LPUART1 clock source --------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection      = __HAL_RCC_GET_LPUART1_SOURCE();
+  /* Get the LTDC clock source -----------------------------------------------*/
+  PeriphClkInit->LtdcClockSelection         = __HAL_RCC_GET_LTDC_SOURCE();
+  /* Get the MDF1 clock source -----------------------------------------------*/
+  PeriphClkInit->Mdf1ClockSelection         = __HAL_RCC_GET_MDF1_SOURCE();
+  /* Get the PSSI clock source -----------------------------------------------*/
+  PeriphClkInit->PssiClockSelection         = __HAL_RCC_GET_PSSI_SOURCE();
+  /* Get the RTC clock source ------------------------------------------------*/
+  PeriphClkInit->RTCClockSelection          = __HAL_RCC_GET_RTC_SOURCE();
+  /* Get the SAI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection         = __HAL_RCC_GET_SAI1_SOURCE();
+  /* Get the SAI2 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai2ClockSelection         = __HAL_RCC_GET_SAI2_SOURCE();
+  /* Get the SDMMC1 clock source ---------------------------------------------*/
+  PeriphClkInit->Sdmmc1ClockSelection       = __HAL_RCC_GET_SDMMC1_SOURCE();
+  /* Get the SDMMC2 clock source ---------------------------------------------*/
+  PeriphClkInit->Sdmmc2ClockSelection       = __HAL_RCC_GET_SDMMC2_SOURCE();
+  /* Get the SPDIFRX1 clock source -------------------------------------------*/
+  PeriphClkInit->Spdifrx1ClockSelection     = __HAL_RCC_GET_SPDIFRX1_SOURCE();
+  /* Get the SPI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi1ClockSelection         = __HAL_RCC_GET_SPI1_SOURCE();
+  /* Get the SPI2 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi2ClockSelection         = __HAL_RCC_GET_SPI2_SOURCE();
+  /* Get the SPI3 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi3ClockSelection         = __HAL_RCC_GET_SPI3_SOURCE();
+  /* Get the SPI4 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi4ClockSelection         = __HAL_RCC_GET_SPI4_SOURCE();
+  /* Get the SPI5 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi5ClockSelection         = __HAL_RCC_GET_SPI5_SOURCE();
+  /* Get the SPI6 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi6ClockSelection         = __HAL_RCC_GET_SPI6_SOURCE();
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  PeriphClkInit->TIMPresSelection           = __HAL_RCC_GET_TIMCLKPRESCALER();
+  /* Get the USART1 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart1ClockSelection       = __HAL_RCC_GET_USART1_SOURCE();
+  /* Get the USART2 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart2ClockSelection       = __HAL_RCC_GET_USART2_SOURCE();
+  /* Get the USART3 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart3ClockSelection       = __HAL_RCC_GET_USART3_SOURCE();
+  /* Get the UART4 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart4ClockSelection        = __HAL_RCC_GET_UART4_SOURCE();
+  /* Get the UART5 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart5ClockSelection        = __HAL_RCC_GET_UART5_SOURCE();
+  /* Get the USART6 clock source ---------------------------------------------*/
+  PeriphClkInit->Usart6ClockSelection       = __HAL_RCC_GET_USART6_SOURCE();
+  /* Get the UART7 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart7ClockSelection        = __HAL_RCC_GET_UART7_SOURCE();
+  /* Get the UART8 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart8ClockSelection        = __HAL_RCC_GET_UART8_SOURCE();
+  /* Get the UART9 clock source ----------------------------------------------*/
+  PeriphClkInit->Uart9ClockSelection        = __HAL_RCC_GET_UART9_SOURCE();
+  /* Get the USART10 clock source --------------------------------------------*/
+  PeriphClkInit->Usart10ClockSelection      = __HAL_RCC_GET_USART10_SOURCE();
+  /* Get the USBPHY1 clock source --------------------------------------------*/
+  PeriphClkInit->UsbPhy1ClockSelection      = __HAL_RCC_GET_USBPHY1_SOURCE();
+  /* Get the USB OTGHS1 clock source -----------------------------------------*/
+  PeriphClkInit->UsbOtgHs1ClockSelection    = __HAL_RCC_GET_USBOTGHS1_SOURCE();
+  /* Get the USBPHY2 clock source --------------------------------------------*/
+  PeriphClkInit->UsbPhy2ClockSelection      = __HAL_RCC_GET_USBPHY2_SOURCE();
+  /* Get the USB OTGHS2 clock source -----------------------------------------*/
+  PeriphClkInit->UsbOtgHs2ClockSelection    = __HAL_RCC_GET_USBOTGHS2_SOURCE();
+  /* Get the XSPI1 clock source ----------------------------------------------*/
+  PeriphClkInit->Xspi1ClockSelection        = __HAL_RCC_GET_XSPI1_SOURCE();
+  /* Get the XSPI2 clock source ----------------------------------------------*/
+  PeriphClkInit->Xspi2ClockSelection        = __HAL_RCC_GET_XSPI2_SOURCE();
+  /* Get the XSPI3 clock source ----------------------------------------------*/
+  PeriphClkInit->Xspi3ClockSelection        = __HAL_RCC_GET_XSPI3_SOURCE();
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral (SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API or
+  *         if the selected clock source is not enabled (HSI, PLLs clock output..)
+  * @param  PeriphClk: Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_ADC      : ADC peripheral clock
+  *            @arg RCC_PERIPHCLK_ADF1     : ADF1 peripheral clock
+  *            @arg RCC_PERIPHCLK_CSI      : CSI peripheral clock
+  *            @arg RCC_PERIPHCLK_DCMIPP   : DCMIPP peripheral clock
+  *            @arg RCC_PERIPHCLK_I2C1     : I2C1 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2C2     : I2C2 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2C3     : I2C3 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2C4     : I2C4 peripheral clock
+  *            @arg RCC_PERIPHCLK_I3C1     : I3C1 peripheral clock
+  *            @arg RCC_PERIPHCLK_I3C2     : I3C2 peripheral clock
+  *            @arg RCC_PERIPHCLK_FDCAN    : FDCAN peripheral clock
+  *            @arg RCC_PERIPHCLK_FMC      : FMC peripheral clock
+  *            @arg RCC_PERIPHCLK_LPTIM1   : LPTIM1 peripheral clock
+  *            @arg RCC_PERIPHCLK_LPTIM2   : LPTIM2 peripheral clock
+  *            @arg RCC_PERIPHCLK_LPTIM3   : LPTIM3 peripheral clock
+  *            @arg RCC_PERIPHCLK_LPTIM4   : LPTIM4 peripheral clock
+  *            @arg RCC_PERIPHCLK_LPTIM5   : LPTIM5 peripheral clock
+  *            @arg RCC_PERIPHCLK_LPUART1  : LPUART1 peripheral clock
+  *            @arg RCC_PERIPHCLK_LTDC     : LTDC peripheral clock
+  *            @arg RCC_PERIPHCLK_MDF1     : MDF1 peripheral clock
+  *            @arg RCC_PERIPHCLK_PSSI     : PSSI peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI1     : SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI2     : SAI2 peripheral clock
+  *            @arg RCC_PERIPHCLK_SDMMC1   : SDMMC1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SDMMC2   : SDMMC2 peripheral clock
+  *            @arg RCC_PERIPHCLK_SPDIFRX1 : SPDIFRX1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI1     : SPI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI2     : SPI2 peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI3     : SPI3 peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI4     : SPI4 peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI5     : SPI5 peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI6     : SPI6 peripheral clock
+  *            @arg RCC_PERIPHCLK_USART1   : USART1 peripheral clock
+  *            @arg RCC_PERIPHCLK_USART2   : USART2 peripheral clock
+  *            @arg RCC_PERIPHCLK_USART3   : USART3 peripheral clock
+  *            @arg RCC_PERIPHCLK_UART4    : UART4 peripheral clock
+  *            @arg RCC_PERIPHCLK_UART5    : UART5 peripheral clock
+  *            @arg RCC_PERIPHCLK_USART6   : USART6 peripheral clock
+  *            @arg RCC_PERIPHCLK_UART7    : UART7 peripheral clock
+  *            @arg RCC_PERIPHCLK_UART8    : UART8 peripheral clock
+  *            @arg RCC_PERIPHCLK_UART9    : UART9 peripheral clock
+  *            @arg RCC_PERIPHCLK_USART10  : USART10 peripheral clock
+  *            @arg RCC_PERIPHCLK_XSPI1    : XSPI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_XSPI2    : XSPI2 peripheral clock
+  *            @arg RCC_PERIPHCLK_XSPI3    : XSPI3 peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
+{
+  uint32_t frequency = 0;   /* Set to 0 for returned value if no source clock */
+
+  switch (PeriphClk)
+  {
+    case RCC_PERIPHCLK_ADC:
+      frequency = RCCEx_GetADCCLKFreq(LL_RCC_ADC_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_ADF1:
+      frequency = RCCEx_GetADFCLKFreq(LL_RCC_ADF1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_CSI:
+      frequency = RCCEx_GetCSICLKFreq();
+      break;
+
+    case RCC_PERIPHCLK_CKPER:
+      frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_DCMIPP:
+      frequency = RCCEx_GetDCMIPPCLKFreq(LL_RCC_DCMIPP_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_ETH1:
+      frequency = RCCEx_GetETH1CLKFreq(LL_RCC_ETH1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_ETH1PTP:
+      frequency = RCCEx_GetETH1PTPCLKFreq(LL_RCC_ETH1PTP_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_FDCAN:
+      frequency = RCCEx_GetFDCANCLKFreq(LL_RCC_FDCAN_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_FMC:
+      frequency = RCCEx_GetFMCCLKFreq(LL_RCC_FMC_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_I2C1:
+      frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_I2C2:
+      frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_I2C3:
+      frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C3_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_I2C4:
+      frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C4_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_I3C1:
+      frequency = RCCEx_GetI3CCLKFreq(LL_RCC_I3C1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_I3C2:
+      frequency = RCCEx_GetI3CCLKFreq(LL_RCC_I3C2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_LPTIM1:
+      frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_LPTIM2:
+      frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_LPTIM3:
+      frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM3_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_LPTIM4:
+      frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM4_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_LPTIM5:
+      frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM5_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_LPUART1:
+      frequency = RCCEx_GetLPUARTCLKFreq(LL_RCC_LPUART1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_LTDC:
+      frequency = RCCEx_GetLTDCCLKFreq(LL_RCC_LTDC_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_MDF1:
+      frequency = RCCEx_GetMDFCLKFreq(LL_RCC_MDF1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_PSSI:
+      frequency = RCCEx_GetPSSICLKFreq(LL_RCC_PSSI_CLKSOURCE);
+      break;
+
+    case  RCC_PERIPHCLK_RTC:
+      frequency = RCCEx_GetRTCCLKFreq();
+      break;
+
+    case RCC_PERIPHCLK_SAI1:
+      frequency = RCCEx_GetSAICLKFreq(LL_RCC_SAI1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SAI2:
+      frequency = RCCEx_GetSAICLKFreq(LL_RCC_SAI2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SDMMC1:
+      frequency = RCCEx_GetSDMMCCLKFreq(LL_RCC_SDMMC1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SDMMC2:
+      frequency = RCCEx_GetSDMMCCLKFreq(LL_RCC_SDMMC2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SPDIFRX1:
+      frequency = RCCEx_GetSPDIFRXCLKFreq(LL_RCC_SPDIFRX1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SPI1:
+      frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SPI2:
+      frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SPI3:
+      frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI3_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SPI4:
+      frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI4_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SPI5:
+      frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI5_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_SPI6:
+      frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI6_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USART1:
+      frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USART2:
+      frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USART3:
+      frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART3_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_UART4:
+      frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART4_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_UART5:
+      frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART5_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USART6:
+      frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART6_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_UART7:
+      frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART7_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_UART8:
+      frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART8_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_UART9:
+      frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART9_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USART10:
+      frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART10_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USBPHY1:
+      frequency = RCCEx_GetOTGPHYCKREFCLKFreq(LL_RCC_OTGPHY1CKREF_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USBOTGHS1:
+      frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USBPHY2:
+      frequency = RCCEx_GetOTGPHYCKREFCLKFreq(LL_RCC_OTGPHY2CKREF_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_USBOTGHS2:
+      frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_XSPI1:
+      frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI1_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_XSPI2:
+      frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI2_CLKSOURCE);
+      break;
+
+    case RCC_PERIPHCLK_XSPI3:
+      frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI3_CLKSOURCE);
+      break;
+
+    default:
+      /* Unexpected case, frequency is by default set to 0 */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return PLL1 clock frequency
+  * @note   RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL1 output clock frequency
+  */
+uint32_t HAL_RCCEx_GetPLL1CLKFreq(void)
+{
+  uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL1_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL1P_IsEnabled() != 0U)
+    {
+      uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL1_GetSource());
+
+      if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = RCC_PLL_SOURCE_FREQ;
+        /*****************************************/
+#endif /* USE_FPGA */
+        divm = LL_RCC_PLL1_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetFRACN(), \
+                                            LL_RCC_PLL1_GetP1(), LL_RCC_PLL1_GetP2());
+        }
+      }
+    }
+  }
+  else if (LL_RCC_PLL1_IsEnabledBypass() != 0U)
+  {
+    plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL1_GetSource());
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @brief  Return PLL2 clock frequency
+  * @note   RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL2 output clock frequency
+  */
+uint32_t HAL_RCCEx_GetPLL2CLKFreq(void)
+{
+  uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL2_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL2P_IsEnabled() != 0U)
+    {
+      uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL2_GetSource());
+
+      if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = RCC_PLL_SOURCE_FREQ;
+        /*****************************************/
+#endif /* USE_FPGA */
+        divm = LL_RCC_PLL2_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetFRACN(), \
+                                            LL_RCC_PLL2_GetP1(), LL_RCC_PLL2_GetP2());
+        }
+      }
+    }
+  }
+  else if (LL_RCC_PLL2_IsEnabledBypass() != 0U)
+  {
+    plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL2_GetSource());
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @brief  Return PLL3 clock frequency
+  * @note   RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL3 output clock frequency
+  */
+uint32_t HAL_RCCEx_GetPLL3CLKFreq(void)
+{
+  uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL3_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL3P_IsEnabled() != 0U)
+    {
+      uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL3_GetSource());
+
+      if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = RCC_PLL_SOURCE_FREQ;
+        /*****************************************/
+#endif /* USE_FPGA */
+        divm = LL_RCC_PLL3_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetFRACN(), \
+                                            LL_RCC_PLL3_GetP1(), LL_RCC_PLL3_GetP2());
+        }
+      }
+    }
+  }
+  else if (LL_RCC_PLL3_IsEnabledBypass() != 0U)
+  {
+    plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL3_GetSource());
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @brief  Return PLL4 clock frequency
+  * @note   RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL4 output clock frequency
+  */
+uint32_t HAL_RCCEx_GetPLL4CLKFreq(void)
+{
+  uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL4_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL4P_IsEnabled() != 0U)
+    {
+      uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL4_GetSource());
+
+      if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = RCC_PLL_SOURCE_FREQ;
+        /*****************************************/
+#endif /* USE_FPGA */
+        divm = LL_RCC_PLL4_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL4_GetN(), LL_RCC_PLL4_GetFRACN(), \
+                                            LL_RCC_PLL4_GetP1(), LL_RCC_PLL4_GetP2());
+        }
+      }
+    }
+  }
+  else if (LL_RCC_PLL4_IsEnabledBypass() != 0U)
+  {
+    plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL4_GetSource());
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
+  *  @brief  Extended Peripheral Control functions
+  * @{
+  */
+/**
+  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
+  * @param  WakeUpClk Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI oscillator selection
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
+  * @note   This function shall not be called after the Clock Security System on HSE has been
+  *         enabled and the system clock is HSE or a switch on HSE is requested.
+  * @retval None
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System.
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+  *         clock with HAL_RCCEx_PeriphCLKConfig().
+  * @note   Backup domain access should be enabled
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+  LL_RCC_LSE_EnableCSS();
+}
+
+/**
+  * @brief  Disable the LSE Clock Security System.
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+  * @note   Backup domain access should be enabled
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+  /* Disable LSE CSS IT if any */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+
+  LL_RCC_LSE_DisableCSS();
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System Interrupt.
+  * @note   LSE Clock Security System Interrupt is mapped on EXTI line 65 which must be
+  *         enabled at application level to wake up from low power modes
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+  /* Enable LSE CSS IT */
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+  LL_RCC_LSE_EnableCSS();
+}
+
+/**
+  * @brief  Disable the LSE Clock Security System Interrupt.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS_IT(void)
+{
+  /* Disable LSE CSS IT */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+
+  LL_RCC_LSE_DisableCSS();
+}
+
+/**
+  * @brief  Rearm the LSE Clock Security System
+  * @note   Allow to re-arm the LSE Clock Security System after a LSE failure detection
+  * @retval None
+  */
+void HAL_RCCEx_ReArmLSECSS(void)
+{
+  LL_RCC_LSE_ReArmCSS();
+}
+
+/**
+  * @brief Handle the RCC LSE Clock Security System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+  /* Check RCC LSE CSSF flag  */
+  if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  {
+    /* Clear RCC LSE CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+
+    /* RCC LSE Clock Security System interrupt user callback */
+    HAL_RCCEx_LSECSS_Callback();
+  }
+}
+
+/**
+  * @brief  RCCEx LSE Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Configure the requested PLL to SSCG Mode
+  * @param  PLLnumber PLL number to configure.
+  *         This parameter can be one of the following values:
+  *            @ref RCC_PLL_Selection
+  * @param  pPLLInit Pointer to an RCC_PLLInitTypeDef structure that
+  *                  contains the configuration parameters.
+  * @param  pPLLSSCGInit Pointer to an RCC_PLLSSCGInitTypeDef structure that
+  *                  contains the configuration parameters specific to SSCG.
+  * @note   PLL is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PLLSSCGConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit,
+                                          const RCC_PLLSSCGInitTypeDef *pPLLSSCGInit)
+{
+  __IO uint32_t *p_rcc_pll_cfgr1_reg;
+  __IO uint32_t *p_rcc_pll_cfgr2_reg;
+  __IO uint32_t *p_rcc_pll_cfgr3_reg;
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t tickstart;
+
+  p_rcc_pll_cfgr1_reg = &(RCC->PLL1CFGR1) + (((uint32_t)0x4) * PLLnumber);
+  p_rcc_pll_cfgr2_reg = &(RCC->PLL1CFGR2) + (((uint32_t)0x4) * PLLnumber);
+  p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber);
+
+  if (pPLLInit->PLLState == RCC_PLL_ON)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource));
+    assert_param(IS_RCC_PLLFRACN_VALUE(pPLLInit->PLLFractional));
+    assert_param(IS_RCC_PLLM_VALUE(pPLLInit->PLLM));
+    assert_param(IS_RCC_PLLN_VALUE(pPLLInit->PLLN));
+    assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP1));
+    assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2));
+    assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2));
+
+    /* Ensure PLLx is disabled */
+    WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLx is disabled */
+    while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber))
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Ensure PLLxMODSSDIS='1' */
+    SET_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS);
+
+    /* Clear bypass mode */
+    CLEAR_BIT(*p_rcc_pll_cfgr1_reg, RCC_PLL1CFGR1_PLL1BYP);
+
+    /* Configure the PLLx clock source, multiplication and division factors. */
+    MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \
+               (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \
+                | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos)));
+    MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \
+               ((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos)));
+
+    /* Configure PLLx DIVNFRAC */
+    MODIFY_REG(*p_rcc_pll_cfgr2_reg, RCC_PLL1CFGR2_PLL1DIVNFRAC, \
+               pPLLInit->PLLFractional << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
+
+    /* Configure PLLx SSCG Parameters */
+    MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDIV | RCC_PLL1CFGR3_PLL1MODSPR | RCC_PLL1CFGR3_PLL1MODSPR), \
+               ((pPLLSSCGInit->PLLModDiv << RCC_PLL1CFGR3_PLL1MODDIV_Pos) \
+                | (pPLLSSCGInit->PLLModSpreadDepth << RCC_PLL1CFGR3_PLL1MODSPR_Pos)
+                | (pPLLSSCGInit->PLLModSpreadMode << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)));
+
+    /* Clear PLLxMODSSDIS, PLLxMODDSEN and DACEN to 0 */
+    CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS | RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN);
+
+    /* Ensure PLLxMODSSRST='1' and Enable PLLx post divider output */
+    SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODSSRST | RCC_PLL1CFGR3_PLL1PDIVEN));
+
+    /* Set PLLxMODDSEN and DACEN */
+    SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN));
+
+    /* Enable the PLLx */
+    WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS << PLLnumber);
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLLx is ready */
+    while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* When PLL is Ready, deassert the PLLxMODSSRST */
+    CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSRST);
+  }
+  else if (pPLLInit->PLLState == RCC_PLL_BYPASS)
+  {
+    ret = HAL_ERROR;
+  }
+  else
+  {
+    /* other states are not managed this function */
+  }
+
+  return ret;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Return HCLK clock frequency
+  * @param  SYSCLK_Frequency SYSCLK clock frequency
+  * @retval HCLK clock frequency (in Hz)
+  */
+static uint32_t RCCEx_GetHCLKFreq(uint32_t SYSCLK_Frequency)
+{
+  /* HCLK clock frequency */
+  return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return PCLK1 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+static uint32_t RCCEx_GetPCLK1Freq(uint32_t HCLK_Frequency)
+{
+  /* PCLK1 clock frequency */
+  return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return PCLK2 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+static uint32_t RCCEx_GetPCLK2Freq(uint32_t HCLK_Frequency)
+{
+  /* PCLK2 clock frequency */
+  return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return PCLK4 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK4 clock frequency (in Hz)
+  */
+static uint32_t RCCEx_GetPCLK4Freq(uint32_t HCLK_Frequency)
+{
+  /* PCLK4 clock frequency */
+  return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
+}
+
+/**
+  * @brief  Return PCLK5 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK5 clock frequency (in Hz)
+  */
+static uint32_t RCCEx_GetPCLK5Freq(uint32_t HCLK_Frequency)
+{
+  /* PCLK5 clock frequency */
+  return LL_RCC_CALC_PCLK5_FREQ(HCLK_Frequency, LL_RCC_GetAPB5Prescaler());
+}
+
+/**
+  * @brief  Return PLL source clock frequency
+  * @param  PLLsource PLL source clock
+  * @retval PLL source clock frequency (in Hz)
+  */
+static uint32_t RCCEx_GetPLLSourceFreq(uint32_t PLLsource)
+{
+  uint32_t pllinputfreq = RCC_PERIPH_FREQUENCY_NO;
+
+  switch (PLLsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        if (LL_RCC_MSI_GetFrequency() == LL_RCC_MSI_FREQ_4MHZ)
+        {
+          pllinputfreq = MSI_VALUE;
+        }
+        else
+        {
+          pllinputfreq = 16000000UL;
+        }
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        pllinputfreq = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_I2S_CKIN:
+      pllinputfreq = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    default:
+      /* unexpected case */
+      break;
+  }
+
+  return pllinputfreq;
+}
+
+/**
+  * @brief  Calculate the PLL frequency output when used in integer or fractional mode
+  * @param  PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/MSI)
+  * @param  M      Between 1 and 63
+  * @param  N      Between 16 and 640 in integer mode, 20 to 320 in fractional mode
+  * @param  FRACN  0 in integer mode, between 0 and 0xFFFFFF in fractional mode
+  * @param  P1     VCO output divider P1 between 1 and 7
+  * @param  P2     VCO output divider P2 between 1 and 7
+  * @retval PLL clock frequency (in Hz)
+  */
+static uint32_t RCCEx_CalcPLLFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1,
+                                  uint32_t P2)
+{
+  float_t freq;
+
+  freq = ((float_t)PLLInputFreq * ((float_t)N + ((float_t)FRACN / (float_t)0x1000000))) / (float_t)M;
+
+  freq = freq / (float_t)P1;
+  freq = freq / (float_t)P2;
+
+  return (uint32_t)freq;
+}
+
+/**
+  * @brief  Return ADC clock frequency
+  * @param  ADCxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_ADC_Clock_Source
+  * @retval ADC clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetADCCLKFreq(uint32_t ADCxSource)
+{
+  uint32_t adc_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetADCClockSource(ADCxSource))
+  {
+    case LL_RCC_ADC_CLKSOURCE_HCLK:
+      adc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_CLKP:
+      adc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            adc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            adc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            adc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            adc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            adc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            adc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            adc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            adc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            adc_frequency = adc_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        adc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        adc_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_I2S_CKIN:
+      adc_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_TIMG:
+      adc_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return (adc_frequency / __HAL_RCC_GET_ADC_DIVIDER());
+}
+
+/**
+  * @brief  Return ADFx clock frequency
+  * @param  ADFxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_ADF1_Clock_Source
+  * @retval ADF clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetADFCLKFreq(uint32_t ADFxSource)
+{
+  uint32_t adf_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetADFClockSource(ADFxSource))
+  {
+    case LL_RCC_ADF1_CLKSOURCE_HCLK:
+      adf_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_CLKP:
+      adf_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        adf_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_I2S_CKIN:
+      adf_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_TIMG:
+      adf_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return adf_frequency;
+}
+
+/**
+  * @brief  Return CLKP clock frequency
+  * @param  CLKPxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_CLKP_Clock_Source
+  * @retval CLKP clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetCLKPCLKFreq(uint32_t CLKPxSource)
+{
+  uint32_t clkp_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  if (LL_RCC_CLKP_IsEnabled() == 1U)
+  {
+    switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
+    {
+      case LL_RCC_CLKP_CLKSOURCE_HSI:
+        if (LL_RCC_HSI_IsReady() != 0U)
+        {
+          clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+        }
+        break;
+
+      case LL_RCC_CLKP_CLKSOURCE_MSI:
+        if (LL_RCC_MSI_IsReady() != 0U)
+        {
+          clkp_frequency = MSI_VALUE;
+        }
+        break;
+
+      case LL_RCC_CLKP_CLKSOURCE_HSE:
+        if (LL_RCC_HSE_IsReady() != 0U)
+        {
+          clkp_frequency = HSE_VALUE;
+        }
+        break;
+
+      case LL_RCC_CLKP_CLKSOURCE_IC5:
+        if (LL_RCC_IC5_IsEnabled() != 0U)
+        {
+          ic_divider = LL_RCC_IC5_GetDivider();
+          switch (LL_RCC_IC5_GetSource())
+          {
+            case LL_RCC_ICCLKSOURCE_PLL1:
+              clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL2:
+              clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL3:
+              clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL4:
+              clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            default:
+              /* Unexpected case */
+              break;
+          }
+        }
+        break;
+
+      case LL_RCC_CLKP_CLKSOURCE_IC10:
+        if (LL_RCC_IC10_IsEnabled() != 0U)
+        {
+          ic_divider = LL_RCC_IC10_GetDivider();
+          switch (LL_RCC_IC10_GetSource())
+          {
+            case LL_RCC_ICCLKSOURCE_PLL1:
+              clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL2:
+              clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL3:
+              clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL4:
+              clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            default:
+              /* Unexpected case */
+              break;
+          }
+        }
+        break;
+
+      case LL_RCC_CLKP_CLKSOURCE_IC15:
+        if (LL_RCC_IC15_IsEnabled() != 0U)
+        {
+          ic_divider = LL_RCC_IC15_GetDivider();
+          switch (LL_RCC_IC15_GetSource())
+          {
+            case LL_RCC_ICCLKSOURCE_PLL1:
+              clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL2:
+              clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL3:
+              clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL4:
+              clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            default:
+              /* Unexpected case */
+              break;
+          }
+        }
+        break;
+
+      case LL_RCC_CLKP_CLKSOURCE_IC19:
+        if (LL_RCC_IC19_IsEnabled() != 0U)
+        {
+          ic_divider = LL_RCC_IC19_GetDivider();
+          switch (LL_RCC_IC19_GetSource())
+          {
+            case LL_RCC_ICCLKSOURCE_PLL1:
+              clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL2:
+              clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL3:
+              clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL4:
+              clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            default:
+              /* Unexpected case */
+              break;
+          }
+        }
+        break;
+
+      case LL_RCC_CLKP_CLKSOURCE_IC20:
+        if (LL_RCC_IC20_IsEnabled() != 0U)
+        {
+          ic_divider = LL_RCC_IC20_GetDivider();
+          switch (LL_RCC_IC20_GetSource())
+          {
+            case LL_RCC_ICCLKSOURCE_PLL1:
+              clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL2:
+              clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL3:
+              clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            case LL_RCC_ICCLKSOURCE_PLL4:
+              clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+              clkp_frequency = clkp_frequency / ic_divider;
+              break;
+            default:
+              /* Unexpected case */
+              break;
+          }
+        }
+        break;
+
+      default:
+        /* Unexpected case */
+        break;
+    }
+  }
+
+  return clkp_frequency;
+}
+
+/**
+  * @brief  Return CSI clock frequency
+  * @retval CLKP clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetCSICLKFreq(void)
+{
+  uint32_t clkp_frequency = RCC_PERIPH_FREQUENCY_NO;
+
+  if (LL_RCC_IC18_IsEnabled() != 0U)
+  {
+    uint32_t ic_divider = LL_RCC_IC18_GetDivider();
+    switch (LL_RCC_IC18_GetSource())
+    {
+      case LL_RCC_ICCLKSOURCE_PLL1:
+        clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+        clkp_frequency = clkp_frequency / ic_divider;
+        break;
+      case LL_RCC_ICCLKSOURCE_PLL2:
+        clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+        clkp_frequency = clkp_frequency / ic_divider;
+        break;
+      case LL_RCC_ICCLKSOURCE_PLL3:
+        clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+        clkp_frequency = clkp_frequency / ic_divider;
+        break;
+      case LL_RCC_ICCLKSOURCE_PLL4:
+        clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+        clkp_frequency = clkp_frequency / ic_divider;
+        break;
+      default:
+        /* Unexpected case */
+        break;
+    }
+  }
+
+  return clkp_frequency;
+}
+
+/**
+  * @brief  Return DCMIPP clock frequency
+  * @param  DCMIPPxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_DCMIPP_Clock_Source
+  * @retval DCMIPP clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetDCMIPPCLKFreq(uint32_t DCMIPPxSource)
+{
+  uint32_t dcmipp_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetDCMIPPClockSource(DCMIPPxSource))
+  {
+    case LL_RCC_DCMIPP_CLKSOURCE_PCLK5:
+      dcmipp_frequency = RCCEx_GetPCLK5Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_DCMIPP_CLKSOURCE_CLKP:
+      dcmipp_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_DCMIPP_CLKSOURCE_IC17:
+      if (LL_RCC_IC17_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC17_GetDivider();
+        switch (LL_RCC_IC17_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            dcmipp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            dcmipp_frequency = dcmipp_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            dcmipp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            dcmipp_frequency = dcmipp_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            dcmipp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            dcmipp_frequency = dcmipp_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            dcmipp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            dcmipp_frequency = dcmipp_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_DCMIPP_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        dcmipp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return dcmipp_frequency;
+}
+
+/**
+  * @brief  Return ETH1 clock frequency
+  * @param  ETH1xSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_ETH1_Clock_Source
+  * @retval ETH1 clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetETH1CLKFreq(uint32_t ETH1xSource)
+{
+  uint32_t eth1_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetETHClockSource(ETH1xSource))
+  {
+    case LL_RCC_ETH1_CLKSOURCE_HCLK:
+      eth1_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_ETH1_CLKSOURCE_CLKP:
+      eth1_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ETH1_CLKSOURCE_IC12:
+      if (LL_RCC_IC12_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC12_GetDivider();
+        switch (LL_RCC_IC12_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            eth1_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            eth1_frequency = eth1_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            eth1_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            eth1_frequency = eth1_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            eth1_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            eth1_frequency = eth1_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            eth1_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            eth1_frequency = eth1_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ETH1_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        eth1_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return eth1_frequency;
+}
+
+/**
+  * @brief  Return ETH1PTP clock frequency
+  * @param  ETH1PTPxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_ETH1_PTP_Clock_Source
+  * @retval ETH1PTP clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetETH1PTPCLKFreq(uint32_t ETH1PTPxSource)
+{
+  uint32_t eth1ptp_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetETHPTPClockSource(ETH1PTPxSource))
+  {
+    case LL_RCC_ETH1PTP_CLKSOURCE_HCLK:
+      eth1ptp_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_ETH1PTP_CLKSOURCE_CLKP:
+      eth1ptp_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ETH1PTP_CLKSOURCE_IC13:
+      if (LL_RCC_IC13_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC13_GetDivider();
+        switch (LL_RCC_IC13_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            eth1ptp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            eth1ptp_frequency = eth1ptp_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            eth1ptp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            eth1ptp_frequency = eth1ptp_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            eth1ptp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            eth1ptp_frequency = eth1ptp_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            eth1ptp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            eth1ptp_frequency = eth1ptp_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ETH1PTP_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        eth1ptp_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return (eth1ptp_frequency / __HAL_RCC_GET_ETH1PTP_DIVIDER());
+}
+
+/**
+  * @brief  Return FDCAN clock frequency
+  * @param  FDCANxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_FDCAN_Clock_Source
+  * @retval FDCAN clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetFDCANCLKFreq(uint32_t FDCANxSource)
+{
+  uint32_t fdcan_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
+  {
+    case LL_RCC_FDCAN_CLKSOURCE_PCLK1:
+      fdcan_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_CLKP:
+      fdcan_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_IC19:
+      if (LL_RCC_IC19_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC19_GetDivider();
+        switch (LL_RCC_IC19_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            fdcan_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            fdcan_frequency = fdcan_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            fdcan_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            fdcan_frequency = fdcan_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            fdcan_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            fdcan_frequency = fdcan_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            fdcan_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            fdcan_frequency = fdcan_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        fdcan_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return fdcan_frequency;
+}
+
+/**
+  * @brief  Return FMC clock frequency
+  * @param  FMCxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_FMC_Clock_Source
+  * @retval FMC clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetFMCCLKFreq(uint32_t FMCxSource)
+{
+  uint32_t fmc_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetFMCClockSource(FMCxSource))
+  {
+    case LL_RCC_FMC_CLKSOURCE_HCLK:
+      fmc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_CLKP:
+      fmc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_IC3:
+      if (LL_RCC_IC3_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC3_GetDivider();
+        switch (LL_RCC_IC3_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            fmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            fmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            fmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            fmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_IC4:
+      if (LL_RCC_IC4_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC4_GetDivider();
+        switch (LL_RCC_IC4_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            fmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            fmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            fmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            fmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            fmc_frequency = fmc_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return fmc_frequency;
+}
+
+/**
+  * @brief  Return I2Cx clock frequency
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_I2C1_Clock_Source
+  *         @arg @ref RCCEx_I2C2_Clock_Source
+  *         @arg @ref RCCEx_I2C3_Clock_Source
+  *         @arg @ref RCCEx_I2C4_Clock_Source
+  * @retval I2C clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetI2CCLKFreq(uint32_t I2CxSource)
+{
+  uint32_t i2c_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetI2CClockSource(I2CxSource))
+  {
+    case LL_RCC_I2C1_CLKSOURCE_PCLK1:
+    case LL_RCC_I2C2_CLKSOURCE_PCLK1:
+    case LL_RCC_I2C3_CLKSOURCE_PCLK1:
+    case LL_RCC_I2C4_CLKSOURCE_PCLK1:
+      i2c_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_CLKP:
+    case LL_RCC_I2C2_CLKSOURCE_CLKP:
+    case LL_RCC_I2C3_CLKSOURCE_CLKP:
+    case LL_RCC_I2C4_CLKSOURCE_CLKP:
+      i2c_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_IC10:
+    case LL_RCC_I2C2_CLKSOURCE_IC10:
+    case LL_RCC_I2C3_CLKSOURCE_IC10:
+    case LL_RCC_I2C4_CLKSOURCE_IC10:
+      if (LL_RCC_IC10_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC10_GetDivider();
+        switch (LL_RCC_IC10_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            i2c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            i2c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            i2c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            i2c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_IC15:
+    case LL_RCC_I2C2_CLKSOURCE_IC15:
+    case LL_RCC_I2C3_CLKSOURCE_IC15:
+    case LL_RCC_I2C4_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            i2c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            i2c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            i2c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            i2c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            i2c_frequency = i2c_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_HSI:
+    case LL_RCC_I2C2_CLKSOURCE_HSI:
+    case LL_RCC_I2C3_CLKSOURCE_HSI:
+    case LL_RCC_I2C4_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_MSI:
+    case LL_RCC_I2C2_CLKSOURCE_MSI:
+    case LL_RCC_I2C3_CLKSOURCE_MSI:
+    case LL_RCC_I2C4_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        i2c_frequency = MSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return i2c_frequency;
+}
+
+/**
+  * @brief  Return I3Cx clock frequency
+  * @param  I3CxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_I3C1_Clock_Source
+  *         @arg @ref RCCEx_I3C2_Clock_Source
+  * @retval I3C clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetI3CCLKFreq(uint32_t I3CxSource)
+{
+  uint32_t i3c_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetI3CClockSource(I3CxSource))
+  {
+    case LL_RCC_I3C1_CLKSOURCE_PCLK1:
+    case LL_RCC_I3C2_CLKSOURCE_PCLK1:
+      i3c_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_CLKP:
+    case LL_RCC_I3C2_CLKSOURCE_CLKP:
+      i3c_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_IC10:
+    case LL_RCC_I3C2_CLKSOURCE_IC10:
+      if (LL_RCC_IC10_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC10_GetDivider();
+        switch (LL_RCC_IC10_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            i3c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            i3c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            i3c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            i3c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_IC15:
+    case LL_RCC_I3C2_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            i3c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            i3c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            i3c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            i3c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            i3c_frequency = i3c_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_HSI:
+    case LL_RCC_I3C2_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        i3c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_MSI:
+    case LL_RCC_I3C2_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        i3c_frequency = MSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return i3c_frequency;
+}
+
+/**
+  * @brief  Return LPTIMx clock frequency
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_LPTIM1_Clock_Source
+  *         @arg @ref RCCEx_LPTIM2_Clock_Source
+  *         @arg @ref RCCEx_LPTIM3_Clock_Source
+  *         @arg @ref RCCEx_LPTIM4_Clock_Source
+  *         @arg @ref RCCEx_LPTIM5_Clock_Source
+  * @retval LPTIM clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource)
+{
+  uint32_t lptim_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+  {
+    case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
+      lptim_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM3_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM4_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM5_CLKSOURCE_PCLK4:
+      lptim_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM3_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM4_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM5_CLKSOURCE_CLKP:
+      lptim_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM2_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM3_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM4_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM5_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            lptim_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            lptim_frequency = lptim_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            lptim_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            lptim_frequency = lptim_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            lptim_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            lptim_frequency = lptim_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            lptim_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            lptim_frequency = lptim_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM3_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM4_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM5_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        lptim_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM3_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM4_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM5_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        lptim_frequency = LSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM2_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM3_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM4_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM5_CLKSOURCE_TIMG:
+      lptim_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return lptim_frequency;
+}
+
+/**
+  * @brief  Return LPUART clock frequency
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_LPUART1_Clock_Source
+  * @retval LPUART clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetLPUARTCLKFreq(uint32_t LPUARTxSource)
+{
+  uint32_t lpuart_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+  {
+    case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
+      lpuart_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_CLKP:
+      lpuart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            lpuart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            lpuart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            lpuart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            lpuart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            lpuart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            lpuart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            lpuart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            lpuart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            lpuart_frequency = lpuart_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        lpuart_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        lpuart_frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return lpuart_frequency;
+}
+
+/**
+  * @brief  Return LTDC clock frequency
+  * @param  LTDCxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_LTDC_Clock_Source
+  * @retval LTDC clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetLTDCCLKFreq(uint32_t LTDCxSource)
+{
+  uint32_t ltdc_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetLTDCClockSource(LTDCxSource))
+  {
+    case LL_RCC_LTDC_CLKSOURCE_PCLK5:
+      ltdc_frequency = RCCEx_GetPCLK5Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_LTDC_CLKSOURCE_CLKP:
+      ltdc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_LTDC_CLKSOURCE_IC16:
+      if (LL_RCC_IC16_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC16_GetDivider();
+        switch (LL_RCC_IC16_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            ltdc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            ltdc_frequency = ltdc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            ltdc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            ltdc_frequency = ltdc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            ltdc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            ltdc_frequency = ltdc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            ltdc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            ltdc_frequency = ltdc_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LTDC_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        ltdc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return ltdc_frequency;
+}
+
+/**
+  * @brief  Return MDFx clock frequency
+  * @param  MDFxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_MDF1_Clock_Source
+  * @retval MDF clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetMDFCLKFreq(uint32_t MDFxSource)
+{
+  uint32_t adf_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetMDFClockSource(MDFxSource))
+  {
+    case LL_RCC_MDF1_CLKSOURCE_HCLK:
+      adf_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_CLKP:
+      adf_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            adf_frequency = adf_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        adf_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_I2S_CKIN:
+      adf_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_TIMG:
+      adf_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return adf_frequency;
+}
+
+/**
+  * @brief  Return PSSI clock frequency
+  * @param  PSSIxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_PSSI_Clock_Source
+  * @retval PSSI clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetPSSICLKFreq(uint32_t PSSIxSource)
+{
+  uint32_t pssi_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetPSSIClockSource(PSSIxSource))
+  {
+    case LL_RCC_PSSI_CLKSOURCE_HCLK:
+      pssi_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_PSSI_CLKSOURCE_CLKP:
+      pssi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_PSSI_CLKSOURCE_IC20:
+      if (LL_RCC_IC20_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC20_GetDivider();
+        switch (LL_RCC_IC20_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            pssi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            pssi_frequency = pssi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            pssi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            pssi_frequency = pssi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            pssi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            pssi_frequency = pssi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            pssi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            pssi_frequency = pssi_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_PSSI_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pssi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return pssi_frequency;
+}
+
+/**
+  * @brief  Return RTC clock frequency
+  * @retval RTC clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetRTCCLKFreq()
+{
+  uint32_t rtc_frequency = RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetRTCClockSource())
+  {
+    case LL_RCC_RTC_CLKSOURCE_NONE:
+      /* Nothing to do */
+      break;
+
+    case LL_RCC_RTC_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        rtc_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_RTC_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        rtc_frequency = LSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_RTC_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        uint32_t prescaler = (READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE) >> RCC_CCIPR7_RTCPRE_Pos) + 1U;
+        rtc_frequency = HSE_VALUE / prescaler;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return rtc_frequency;
+}
+
+/**
+  * @brief  Return SAIx clock frequency
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_SAI1_Clock_Source
+  *         @arg @ref RCCEx_SAI2_Clock_Source
+  * @retval SAI clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetSAICLKFreq(uint32_t SAIxSource)
+{
+  uint32_t sai_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetSAIClockSource(SAIxSource))
+  {
+    case LL_RCC_SAI1_CLKSOURCE_PCLK2:
+    case LL_RCC_SAI2_CLKSOURCE_PCLK2:
+      sai_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_CLKP:
+    case LL_RCC_SAI2_CLKSOURCE_CLKP:
+      sai_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_IC7:
+    case LL_RCC_SAI2_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            sai_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            sai_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            sai_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            sai_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_IC8:
+    case LL_RCC_SAI2_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            sai_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            sai_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            sai_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            sai_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            sai_frequency = sai_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_HSI:
+    case LL_RCC_SAI2_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        sai_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_MSI:
+    case LL_RCC_SAI2_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        sai_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SAI2_CLKSOURCE_I2S_CKIN:
+      sai_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_SPDIFRX1:
+    case LL_RCC_SAI2_CLKSOURCE_SPDIFRX1:
+      sai_frequency = RCCEx_GetSPDIFRXCLKFreq(LL_RCC_SPDIFRX1_CLKSOURCE);
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return sai_frequency;
+}
+
+/**
+  * @brief  Return SDMMC clock frequency
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_SDMMC1_Clock_Source
+  *         @arg @ref RCCEx_SDMMC2_Clock_Source
+  * @retval SDMMC clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetSDMMCCLKFreq(uint32_t SDMMCxSource)
+{
+  uint32_t sdmmc_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+  {
+    case LL_RCC_SDMMC1_CLKSOURCE_HCLK:
+    case LL_RCC_SDMMC2_CLKSOURCE_HCLK:
+      sdmmc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_CLKP:
+    case LL_RCC_SDMMC2_CLKSOURCE_CLKP:
+      sdmmc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_IC4:
+    case LL_RCC_SDMMC2_CLKSOURCE_IC4:
+      if (LL_RCC_IC4_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC4_GetDivider();
+        switch (LL_RCC_IC4_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            sdmmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            sdmmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            sdmmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            sdmmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_IC5:
+    case LL_RCC_SDMMC2_CLKSOURCE_IC5:
+      if (LL_RCC_IC5_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC5_GetDivider();
+        switch (LL_RCC_IC5_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            sdmmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            sdmmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            sdmmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            sdmmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            sdmmc_frequency = sdmmc_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return sdmmc_frequency;
+}
+
+/**
+  * @brief  Return SPDIFRX clock frequency
+  * @param  SPDIFRXxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_SPDIFRX1_Clock_Source
+  * @retval SPDIF clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetSPDIFRXCLKFreq(uint32_t SPDIFRXxSource)
+{
+  uint32_t spdifrx_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
+  {
+    case LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1:
+      spdifrx_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_CLKP:
+      spdifrx_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            spdifrx_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            spdifrx_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            spdifrx_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            spdifrx_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            spdifrx_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            spdifrx_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            spdifrx_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            spdifrx_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            spdifrx_frequency = spdifrx_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        spdifrx_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        spdifrx_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN:
+      spdifrx_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return spdifrx_frequency;
+}
+
+/**
+  * @brief  Return SPIx clock frequency
+  * @param  SPIxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_SPI1_Clock_Source
+  *         @arg @ref RCCEx_SPI2_Clock_Source
+  *         @arg @ref RCCEx_SPI3_Clock_Source
+  *         @arg @ref RCCEx_SPI4_Clock_Source
+  *         @arg @ref RCCEx_SPI5_Clock_Source
+  *         @arg @ref RCCEx_SPI6_Clock_Source
+  * @retval SPI clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetSPICLKFreq(uint32_t SPIxSource)
+{
+  uint32_t spi_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetSPIClockSource(SPIxSource))
+  {
+    case LL_RCC_SPI2_CLKSOURCE_PCLK1:
+    case LL_RCC_SPI3_CLKSOURCE_PCLK1:
+      spi_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_PCLK2:
+    case LL_RCC_SPI4_CLKSOURCE_PCLK2:
+    case LL_RCC_SPI5_CLKSOURCE_PCLK2:
+      spi_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_SPI6_CLKSOURCE_PCLK4:
+      spi_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_CLKP:
+    case LL_RCC_SPI2_CLKSOURCE_CLKP:
+    case LL_RCC_SPI3_CLKSOURCE_CLKP:
+    case LL_RCC_SPI4_CLKSOURCE_CLKP:
+    case LL_RCC_SPI5_CLKSOURCE_CLKP:
+    case LL_RCC_SPI6_CLKSOURCE_CLKP:
+      spi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_IC8:
+    case LL_RCC_SPI2_CLKSOURCE_IC8:
+    case LL_RCC_SPI3_CLKSOURCE_IC8:
+    case LL_RCC_SPI6_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            spi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            spi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            spi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            spi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_IC9:
+    case LL_RCC_SPI2_CLKSOURCE_IC9:
+    case LL_RCC_SPI3_CLKSOURCE_IC9:
+    case LL_RCC_SPI4_CLKSOURCE_IC9:
+    case LL_RCC_SPI5_CLKSOURCE_IC9:
+    case LL_RCC_SPI6_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            spi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            spi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            spi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            spi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPI4_CLKSOURCE_IC14:
+    case LL_RCC_SPI5_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            spi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            spi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            spi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            spi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            spi_frequency = spi_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_HSI:
+    case LL_RCC_SPI2_CLKSOURCE_HSI:
+    case LL_RCC_SPI3_CLKSOURCE_HSI:
+    case LL_RCC_SPI4_CLKSOURCE_HSI:
+    case LL_RCC_SPI5_CLKSOURCE_HSI:
+    case LL_RCC_SPI6_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_MSI:
+    case LL_RCC_SPI2_CLKSOURCE_MSI:
+    case LL_RCC_SPI3_CLKSOURCE_MSI:
+    case LL_RCC_SPI4_CLKSOURCE_MSI:
+    case LL_RCC_SPI5_CLKSOURCE_MSI:
+    case LL_RCC_SPI6_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        spi_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SPI2_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SPI3_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
+      spi_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SPI4_CLKSOURCE_HSE:
+    case LL_RCC_SPI5_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        spi_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return spi_frequency;
+}
+
+/**
+  * @brief  Return UARTx clock frequency
+  * @param  UARTxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_UART4_Clock_Source
+  *         @arg @ref RCCEx_UART5_Clock_Source
+  *         @arg @ref RCCEx_UART7_Clock_Source
+  *         @arg @ref RCCEx_UART8_Clock_Source
+  *         @arg @ref RCCEx_UART9_Clock_Source
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetUARTCLKFreq(uint32_t UARTxSource)
+{
+  uint32_t uart_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetUARTClockSource(UARTxSource))
+  {
+    case LL_RCC_UART4_CLKSOURCE_PCLK1:
+    case LL_RCC_UART5_CLKSOURCE_PCLK1:
+    case LL_RCC_UART7_CLKSOURCE_PCLK1:
+    case LL_RCC_UART8_CLKSOURCE_PCLK1:
+      uart_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_UART9_CLKSOURCE_PCLK2:
+      uart_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_CLKP:
+    case LL_RCC_UART5_CLKSOURCE_CLKP:
+    case LL_RCC_UART7_CLKSOURCE_CLKP:
+    case LL_RCC_UART8_CLKSOURCE_CLKP:
+    case LL_RCC_UART9_CLKSOURCE_CLKP:
+      uart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_IC9:
+    case LL_RCC_UART5_CLKSOURCE_IC9:
+    case LL_RCC_UART7_CLKSOURCE_IC9:
+    case LL_RCC_UART8_CLKSOURCE_IC9:
+    case LL_RCC_UART9_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            uart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            uart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            uart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            uart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_IC14:
+    case LL_RCC_UART5_CLKSOURCE_IC14:
+    case LL_RCC_UART7_CLKSOURCE_IC14:
+    case LL_RCC_UART8_CLKSOURCE_IC14:
+    case LL_RCC_UART9_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            uart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            uart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            uart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            uart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            uart_frequency = uart_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_HSI:
+    case LL_RCC_UART5_CLKSOURCE_HSI:
+    case LL_RCC_UART7_CLKSOURCE_HSI:
+    case LL_RCC_UART8_CLKSOURCE_HSI:
+    case LL_RCC_UART9_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        uart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_MSI:
+    case LL_RCC_UART5_CLKSOURCE_MSI:
+    case LL_RCC_UART7_CLKSOURCE_MSI:
+    case LL_RCC_UART8_CLKSOURCE_MSI:
+    case LL_RCC_UART9_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        uart_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_LSE:
+    case LL_RCC_UART5_CLKSOURCE_LSE:
+    case LL_RCC_UART7_CLKSOURCE_LSE:
+    case LL_RCC_UART8_CLKSOURCE_LSE:
+    case LL_RCC_UART9_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        uart_frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return uart_frequency;
+}
+
+/**
+  * @brief  Return USARTx clock frequency
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_USART1_Clock_Source
+  *         @arg @ref RCCEx_USART2_Clock_Source
+  *         @arg @ref RCCEx_USART3_Clock_Source
+  *         @arg @ref RCCEx_USART6_Clock_Source
+  *         @arg @ref RCCEx_USART10_Clock_Source
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+static uint32_t RCCEx_GetUSARTCLKFreq(uint32_t USARTxSource)
+{
+  uint32_t usart_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+  {
+    case LL_RCC_USART1_CLKSOURCE_PCLK2:
+    case LL_RCC_USART6_CLKSOURCE_PCLK2:
+    case LL_RCC_USART10_CLKSOURCE_PCLK2:
+      usart_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_USART2_CLKSOURCE_PCLK1:
+    case LL_RCC_USART3_CLKSOURCE_PCLK1:
+      usart_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_CLKP:
+    case LL_RCC_USART2_CLKSOURCE_CLKP:
+    case LL_RCC_USART3_CLKSOURCE_CLKP:
+    case LL_RCC_USART6_CLKSOURCE_CLKP:
+    case LL_RCC_USART10_CLKSOURCE_CLKP:
+      usart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_IC9:
+    case LL_RCC_USART2_CLKSOURCE_IC9:
+    case LL_RCC_USART3_CLKSOURCE_IC9:
+    case LL_RCC_USART6_CLKSOURCE_IC9:
+    case LL_RCC_USART10_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            usart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            usart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            usart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            usart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_IC14:
+    case LL_RCC_USART2_CLKSOURCE_IC14:
+    case LL_RCC_USART3_CLKSOURCE_IC14:
+    case LL_RCC_USART6_CLKSOURCE_IC14:
+    case LL_RCC_USART10_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            usart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            usart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            usart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            usart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            usart_frequency = usart_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_HSI:
+    case LL_RCC_USART2_CLKSOURCE_HSI:
+    case LL_RCC_USART3_CLKSOURCE_HSI:
+    case LL_RCC_USART6_CLKSOURCE_HSI:
+    case LL_RCC_USART10_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_MSI:
+    case LL_RCC_USART2_CLKSOURCE_MSI:
+    case LL_RCC_USART3_CLKSOURCE_MSI:
+    case LL_RCC_USART6_CLKSOURCE_MSI:
+    case LL_RCC_USART10_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        usart_frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_LSE:
+    case LL_RCC_USART2_CLKSOURCE_LSE:
+    case LL_RCC_USART3_CLKSOURCE_LSE:
+    case LL_RCC_USART6_CLKSOURCE_LSE:
+    case LL_RCC_USART10_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        usart_frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return usart_frequency;
+}
+
+/**
+  * @brief  Return OTGPHYx clock frequency
+  * @param  OTGPHYxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_USB_OTGHS1_Clock_Source
+  *         @arg @ref RCCEx_USB_OTGHS2_Clock_Source
+  * @retval OTGPHY clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
+  */
+static uint32_t RCCEx_GetOTGPHYCLKFreq(uint32_t OTGPHYxSource)
+{
+  uint32_t usb_frequency = RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetUSBClockSource(OTGPHYxSource))
+  {
+    case LL_RCC_OTGPHY1_CLKSOURCE_CLKP:
+    case LL_RCC_OTGPHY2_CLKSOURCE_CLKP:
+      usb_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+    case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2:
+    case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        usb_frequency = HSE_VALUE / 2U;
+      }
+      break;
+    case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC:
+    case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
+        {
+          usb_frequency = HSE_VALUE;
+        }
+        else
+        {
+          usb_frequency = HSE_VALUE / 2U;
+        }
+      }
+      break;
+    case LL_RCC_OTGPHY1_CLKSOURCE_IC15:
+    case LL_RCC_OTGPHY2_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        uint32_t ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            usb_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            usb_frequency = usb_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            usb_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            usb_frequency = usb_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            usb_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            usb_frequency = usb_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            usb_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            usb_frequency = usb_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return usb_frequency;
+}
+
+/**
+  * @brief  Return OTGPHYxCKREF clock frequency
+  * @param  OTGPHYxCKREFSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_USBPHY1_Clock_Source
+  *         @arg @ref RCCEx_USBPHY2_Clock_Source
+  * @retval OTGPHYCKREF clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
+  */
+static uint32_t RCCEx_GetOTGPHYCKREFCLKFreq(uint32_t OTGPHYxCKREFSource)
+{
+  uint32_t usb_frequency = RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetUSBClockSource(OTGPHYxCKREFSource))
+  {
+    case LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC:
+    case LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
+        {
+          usb_frequency = HSE_VALUE;
+        }
+        else
+        {
+          usb_frequency = HSE_VALUE / 2U;
+        }
+      }
+      break;
+
+    case LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1:
+      usb_frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY1_CLKSOURCE);
+      break;
+
+    case LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2:
+      usb_frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY2_CLKSOURCE);
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return usb_frequency;
+}
+
+/**
+  * @brief  Return XSPI clock frequency
+  * @param  XSPIxSource This parameter can be one of the following values:
+  *         @arg @ref RCCEx_XSPI1_Clock_Source
+  *         @arg @ref RCCEx_XSPI2_Clock_Source
+  *         @arg @ref RCCEx_XSPI3_Clock_Source
+  * @retval XSPI clock frequency (in Hz)
+  *         - @ref  RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+
+static uint32_t RCCEx_GetXSPICLKFreq(uint32_t XSPIxSource)
+{
+  uint32_t xspi_frequency = RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetXSPIClockSource(XSPIxSource))
+  {
+    case LL_RCC_XSPI1_CLKSOURCE_HCLK:
+    case LL_RCC_XSPI2_CLKSOURCE_HCLK:
+    case LL_RCC_XSPI3_CLKSOURCE_HCLK:
+      xspi_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
+      break;
+
+    case LL_RCC_XSPI1_CLKSOURCE_CLKP:
+    case LL_RCC_XSPI2_CLKSOURCE_CLKP:
+    case LL_RCC_XSPI3_CLKSOURCE_CLKP:
+      xspi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_XSPI1_CLKSOURCE_IC3:
+    case LL_RCC_XSPI2_CLKSOURCE_IC3:
+    case LL_RCC_XSPI3_CLKSOURCE_IC3:
+      if (LL_RCC_IC3_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC3_GetDivider();
+        switch (LL_RCC_IC3_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            xspi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            xspi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            xspi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            xspi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_XSPI1_CLKSOURCE_IC4:
+    case LL_RCC_XSPI2_CLKSOURCE_IC4:
+    case LL_RCC_XSPI3_CLKSOURCE_IC4:
+      if (LL_RCC_IC4_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC4_GetDivider();
+        switch (LL_RCC_IC4_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            xspi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            xspi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            xspi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            xspi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
+            xspi_frequency = xspi_frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return xspi_frequency;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rif.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rif.c
new file mode 100644
index 000000000..32e173f91
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rif.c
@@ -0,0 +1,1135 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rif.c
+  * @author  MCD Application Team
+  * @brief   RIF HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Resource Isolation Framework (RIF) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                ##### RIF main features #####
+  ==============================================================================
+  [..]
+    (+) Resource Isolation framework (RIF) is a comprehensive set of hardware
+    blocks designed to enforce and manage isolation of STM32 hardware resources
+    like memory and peripherals.
+
+    (+) Resource Isolation Framework (RIF) composed of the following sub-blocks:
+      (++) RIMC:  Resource Isolation Master Controller
+                  This sub-block assigns all non RIF-aware bus master to one
+                  security domain by setting secure, privileged and compartment
+                  information on the system bus.
+                  Note that if non-secure software is permitted to configure one of
+                  these peripherals, then this setting is ignored and all accesses
+                  initiated by the peripheral are forced to be non-secure.
+      (++) RISC:  Resource Isolation Slave Controller
+                  This sub-block assigns all non-RIF aware peripherals to zero,
+                  one or any security domains (secure, privilege, compartment).
+      (++) RISAF: Resource Isolation Slave unit for Address space (Full version)
+                  This sub-block assigns memory regions and subregions to one or
+                  more security domains (secure, privilege, compartment).
+      (++) IAC:   Illegal Access Controller
+                  This sub-block centralizes detection of RIF-related accesses,
+                  managed by a secure application. Supported illegal accesses are:
+                  secure, privileged.
+
+  [..]
+    (+) All the setter functions are protected under the CPU_AS_TRUSTED_DOMAIN
+        directive.
+        It ensures that only the trusted domain can manage the critical
+        configurations of the RIF.
+        This directive is defined in the CMSIS file.
+
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    *** Locking RIF components configuration ***
+    ============================================================
+    [..]
+    (#) Lock and get the lock configuration of RIMC registers until next reset
+        with HAL_RIF_RIMC_Lock / HAL_RIF_RIMC_GetLock.
+    (#) Lock and get the lock configuration of RISC registers until next reset
+        with HAL_RIF_RISC_Lock / HAL_RIF_RISC_GetLock.
+    (#) Lock and get the lock configuration of slave resources registers until
+        next reset with HAL_RIF_RISC_SlaveConfigLock / HAL_RIF_RISC_GetSlaveConfigLock.
+    (#) Lock and get the lock configuration of RISAF registers until next reset
+        with HAL_RIF_RISAF_Lock / HAL_RIF_RISAF_GetLock.
+
+    *** Context-related functions ***
+    ============================================================
+    [..]
+    (#) Set or get Debugger Access Port Compartment ID with HAL_RIF_RIMC_SetDebugAccessPortCID /
+        HAL_RIF_RIMC_GetDebugAccessPortCID functions.
+    (#) Check the Debug Domain and Global Debug Domain status with
+        HAL_RIF_RIMC_GetDebugStatus.
+
+#if defined(GENERATOR_RIF_FEATURE_ENCRYPTION_IMPLEMENTED)
+    *** Encryption-related functions ***
+    ============================================================
+    [..]
+    (#) Read of write RISAF encryption keys and related flags.
+
+#endif
+     *** Configuration of master-related attributes ***
+    ============================================================
+    [..]
+    (#) Set or get the secure, privilege and compartment configuration of a
+        bus master thanks to the HAL_RIF_RIMC_ConfigMasterAttributes /
+        HAL_RIF_RIMC_GetConfigMasterAttributes functions.
+    (#) Lock and get lock status the bus master attributes configuration until
+        next system reset using HAL_RIF_RIMC_Lock.
+
+     *** Configuration of slave-related attributes ***
+    ============================================================
+    [..]
+    (#) Set or get the secure and privilege configuration of a bus slave
+        thanks to the HAL_RIF_RISC_SetSlaveSecureAttributes /
+        HAL_RIF_RISC_GetSlaveSecureAttributes functions.
+    (#) Lock and get lock status each bus slave attributes configuration using
+        HAL_RIF_RISC_SlaveConfigLock or lock the whole RISC configuration with
+        HAL_RIF_RISC_Lock until next system reset.
+
+     *** Configuration of RISAF attributes ***
+    ============================================================
+    [..]
+    (#) Set or get a base region configuration with HAL_RIF_RISAF_ConfigBaseRegion /
+        HAL_RIF_RISAF_GetConfigBaseRegion.
+    (#) Set or get a subregion configuration with HAL_RIF_RISAF_ConfigSubRegion /
+        HAL_RIF_RISAF_GetConfigSubRegion.
+    (#) Delegate a subregion configuration to another CID with HAL_RIF_RISAF_ConfigSubRegionDelegation.
+    (#) Get the data from an illegal access to a protected memory region with
+        HAL_RIF_RISAF_GetIllegalAccess.
+
+     *** IAC related functions ***
+    ============================================================
+    [..]
+    (#) Enable or disable peripheral illegal access detection with HAL_RIF_IAC_EnableIT /
+        HAL_RIF_IAC_DisableIT.
+    (#) Retrieve an illegal access flag from a designated peripheral with HAL_RIF_IAC_GetFlag
+        or clear it with HAL_RIF_IAC_ClearFlag.
+    (#) Illegal access interrupt service routines are served by HAL_RIF_IRQHandler()
+        and user can add his own code using HAL_RIF_ILA_Callback().
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RIF RIF
+  * @brief RIF HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_RIF_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @addtogroup RIF_Private_Defines RIF Private Defines
+  * @{
+  */
+#define RIF_PERIPH_IAC_REG_MAX             4U
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RIF_Exported_Functions RIF Exported Functions
+  *  @{
+  */
+
+/** @defgroup RIF_Exported_Functions_Group1  RIMC Configuration functions
+  *  @brief    RIMC Configuration functions
+  *
+@verbatim
+  ==============================================================================
+            ##### RIMC Configuration functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to configure RIMC
+    RIMC is Resource Isolation Master Controller
+@endverbatim
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief  Lock overall configuration of RIMC.
+  * @note   Once set, the overall configuration of RIMC cannot be modified
+  *         upon next system reset.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @note   This API is protected by the TrustZone Enabled compilation directive.
+  * @retval None
+  */
+void HAL_RIF_RIMC_Lock(void)
+{
+  /* Set RIMC Lock bit */
+  RIFSC->RIMC_CR |= RIFSC_RIMC_CR_GLOCK;
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Get RIMC global lock status.
+  * @retval RIF_LOCK_ENABLE if RIMC configuration is locked, else RIF_LOCK_DISABLE
+  */
+uint32_t HAL_RIF_RIMC_GetLock(void)
+{
+  uint32_t lock_status;
+
+  /* Read RIMC lock bit */
+  lock_status = (RIFSC->RIMC_CR & RIF_LOCK_ENABLE);
+
+  return lock_status;
+}
+
+#if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief  Change the Debugger Access Port ID
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @note   This API is protected by the TrustZone Enabled compilation directive.
+  * @param  CID  specifies the Debugger Access Port CID
+  *         This parameter can be a combination of following values:
+  *           @arg @ref RIF_CID_0    Compartment 0 ID selected as Debug access port ID
+  *           @arg @ref RIF_CID_1    Compartment 1 ID selected as Debug access port ID
+  *           @arg @ref RIF_CID_2    Compartment 2 ID selected as Debug access port ID
+  *           @arg @ref RIF_CID_3    Compartment 3 ID selected as Debug access port ID
+  *           @arg @ref RIF_CID_4    Compartment 4 ID selected as Debug access port ID
+  *           @arg @ref RIF_CID_5    Compartment 5 ID selected as Debug access port ID
+  *           @arg @ref RIF_CID_6    Compartment 6 ID selected as Debug access port ID
+  *           @arg @ref RIF_CID_7    Compartment 7 ID selected as Debug access port ID
+  * @retval None
+  */
+void HAL_RIF_RIMC_SetDebugAccessPortCID(uint32_t CID)
+{
+  uint32_t dap_cid;
+  uint32_t rimc_cr_reg;
+
+  /* Check the parameter */
+  assert_param(IS_RIF_SINGLE_CID(CID));
+
+  /* Set Debug Access Port CID bits */
+  dap_cid = POSITION_VAL(CID);
+  rimc_cr_reg = RIFSC->RIMC_CR;
+  rimc_cr_reg &= (~RIFSC_RIMC_CR_DAPCID);
+  rimc_cr_reg |= (dap_cid << RIFSC_RIMC_CR_DAPCID_Pos);
+  RIFSC->RIMC_CR = rimc_cr_reg;
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Get the Debugger Access Port ID
+  * @retval Debugger Access Port ID
+  */
+uint32_t HAL_RIF_RIMC_GetDebugAccessPortCID(void)
+{
+  uint32_t dap_cid;
+
+  /* Read Debug Access Port CID bits */
+  dap_cid = (RIFSC->RIMC_CR & RIFSC_RIMC_CR_DAPCID) >> RIFSC_RIMC_CR_DAPCID_Pos;
+  dap_cid = (1UL << dap_cid);
+  return dap_cid;
+}
+
+#if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief  Configure CID, Secure and Privilege attributes for the designated master.
+  * @note   RIF_CID_7 is not an authorized value for the MasterCID field.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @note   This API is protected by the TrustZone Enabled compilation directive.
+  * @param  MasterId specifies the index of the bus master.
+  *         This parameter can be one of @ref RIF_MASTER_INDEX
+  * @param  pConfig Pointer on Master Isolation configuration structure
+  * @retval None
+  */
+void HAL_RIF_RIMC_ConfigMasterAttributes(uint32_t MasterId, const RIMC_MasterConfig_t *pConfig)
+{
+  uint32_t master_cid;
+  uint32_t rimc_attr_val;
+
+  /* Check the parameter */
+  assert_param(pConfig != (void *)NULL);
+  assert_param(IS_RIF_MASTER_INDEX(MasterId));
+  assert_param(IS_RIF_SINGLE_CID(pConfig->MasterCID));
+  assert_param(IS_RIF_MASTER_CID(pConfig->MasterCID));
+  assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->SecPriv));
+
+  master_cid = POSITION_VAL(pConfig->MasterCID);
+  rimc_attr_val = RIFSC->RIMC_ATTRx[MasterId];
+  rimc_attr_val &= (~(RIFSC_RIMC_ATTRx_MCID | RIFSC_RIMC_ATTRx_MPRIV | RIFSC_RIMC_ATTRx_MSEC));
+  rimc_attr_val |= ((master_cid << RIFSC_RIMC_ATTRx_MCID_Pos) | (pConfig->SecPriv << RIFSC_RIMC_ATTRx_MSEC_Pos));
+  RIFSC->RIMC_ATTRx[MasterId] = rimc_attr_val;
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Get the CID, Secure and Privilege attributes for the designated master.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  MasterId specifies the index of the bus master.
+  *         This parameter can be one of @ref RIF_MASTER_INDEX
+  * @param  pConfig Pointer on Master Isolation configuration structure
+  * @retval None
+  */
+void HAL_RIF_RIMC_GetConfigMasterAttributes(uint32_t MasterId, RIMC_MasterConfig_t *pConfig)
+{
+  uint32_t master_cid;
+  uint32_t rimc_attr_val;
+
+  /* Check the parameter */
+  assert_param(pConfig != (void *)NULL);
+  assert_param(IS_RIF_MASTER_INDEX(MasterId));
+
+  rimc_attr_val = RIFSC->RIMC_ATTRx[MasterId];
+  pConfig->SecPriv = ((rimc_attr_val & (RIFSC_RIMC_ATTRx_MPRIV | RIFSC_RIMC_ATTRx_MSEC))
+                      >> RIFSC_RIMC_ATTRx_MSEC_Pos);
+  master_cid = ((rimc_attr_val & RIFSC_RIMC_ATTRx_MCID) >> RIFSC_RIMC_ATTRx_MCID_Pos);
+  pConfig->MasterCID = (1UL << master_cid);
+}
+/**
+  * @}
+  */
+
+/** @defgroup RIF_Exported_Functions_Group2  RIFSC Configuration functions
+  *  @brief    RIFSC Configuration functions
+  *
+@verbatim
+  ==============================================================================
+            ##### RIFSC Configuration functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to configure RIFSC
+    RIFSC is Resource Isolation Framework Secure Controller
+@endverbatim
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief  Lock overall configuration of RISC.
+  * @note   Once set, the overall configuration of RIFSC cannot be modified
+  *         upon next system reset.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @note   This API is protected by the TrustZone Enabled compilation directive.
+  * @retval None
+  */
+void HAL_RIF_RISC_Lock(void)
+{
+  /* Set RISC Lock bit */
+  RIFSC->RISC_CR |= RIFSC_RISC_CR_GLOCK;
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Get the RIFSC global lock status.
+  * @retval 1 if RISC configuration is locked, else 0
+  */
+uint32_t HAL_RIF_RISC_GetLock(void)
+{
+  uint32_t lock_status;
+
+  /* Read RISC lock bit */
+  lock_status = (RIFSC->RISC_CR & RIF_LOCK_ENABLE);
+
+  return lock_status;
+}
+
+/**
+  * @brief  Configure the Security and Privilege of a designated slave peripheral.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @param  SecPriv specifies the security and privilege attributes of the peripheral.
+  *         This parameter can be one or a combination of @ref RIF_SEC_PRIV
+  * @retval None
+  */
+void HAL_RIF_RISC_SetSlaveSecureAttributes(uint32_t PeriphId, uint32_t SecPriv)
+{
+  __IO uint32_t sec_reg_val;
+
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
+  assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(SecPriv));
+
+  sec_reg_val = RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT];
+  sec_reg_val &= (~(1U << (PeriphId & RIF_PERIPH_BIT_POSITION)));
+  sec_reg_val |= ((SecPriv & RIF_ATTRIBUTE_SEC) << (PeriphId & RIF_PERIPH_BIT_POSITION));
+  RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT] = sec_reg_val;
+
+  sec_reg_val = RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT];
+  sec_reg_val &= (~(1U << (PeriphId & RIF_PERIPH_BIT_POSITION)));
+  sec_reg_val |= (((SecPriv & RIF_ATTRIBUTE_PRIV) >> 1U) << (PeriphId & RIF_PERIPH_BIT_POSITION));
+  RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT] = sec_reg_val;
+}
+
+/**
+  * @brief  Get the Security and Privilege configuration of a designated slave peripheral.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval can be a combination of @ref RIF_SEC_PRIV
+  */
+uint32_t HAL_RIF_RISC_GetSlaveSecureAttributes(uint32_t PeriphId)
+{
+  uint32_t sec_attr;
+  const __IO uint32_t *p_sec_reg;
+
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
+
+  p_sec_reg = &(RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  sec_attr = ((*p_sec_reg & ((uint32_t)RIF_ATTRIBUTE_SEC << (PeriphId & RIF_PERIPH_BIT_POSITION))) >> (PeriphId & RIF_PERIPH_BIT_POSITION));
+
+  p_sec_reg = &(RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  sec_attr |= (((*p_sec_reg & ((uint32_t)RIF_ATTRIBUTE_SEC << (PeriphId & RIF_PERIPH_BIT_POSITION))) >> (PeriphId & RIF_PERIPH_BIT_POSITION)) << 1U);
+
+  return sec_attr;
+}
+
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+/**
+  * @brief  Lock the Isolation and Security configuration of the designated slave peripheral.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval None
+  */
+void HAL_RIF_RISC_SlaveConfigLock(uint32_t PeriphId)
+{
+  __IO uint32_t *p_lock_reg;
+
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
+
+  /* Set RISC Peripheral Lock bit */
+  p_lock_reg = &(RIFSC->RISC_RCFGLOCKRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  *p_lock_reg |= (RIF_LOCK_ENABLE << (PeriphId & RIF_PERIPH_BIT_POSITION));
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
+
+/**
+  * @brief  Get the Isolation and Security configuration lock status.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval 1 if the Isolation and Security configuration is locked, else 0
+  */
+uint32_t HAL_RIF_RISC_GetSlaveConfigLock(uint32_t PeriphId)
+{
+  uint32_t lock_status;
+  const __IO uint32_t *p_lock_reg;
+
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
+
+  p_lock_reg = &(RIFSC->RISC_RCFGLOCKRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  lock_status = ((*p_lock_reg & (RIF_LOCK_ENABLE << (PeriphId & RIF_PERIPH_BIT_POSITION))) >> (PeriphId & RIF_PERIPH_BIT_POSITION));
+
+  return lock_status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RIF_Exported_Functions_Group4  RISAF Configuration functions
+  *  @brief    RISAF Configuration functions
+  *
+@verbatim
+  ==============================================================================
+            ##### RISAF Configuration functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to configure RISAF
+    RISAL is Resource Isolation Slave unit for Address space protection (Full version)
+@endverbatim
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+/**
+  * @brief  Lock overall configuration of RISAF.
+  * @note   Once set, the overall configuration of RISAF cannot be modified
+  *         upon next system reset.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @retval None
+  */
+void HAL_RIF_RISAF_Lock(RISAF_TypeDef *RISAFx)
+{
+  /* Check the parameters */
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+
+  /* Set RISAF Lock bit */
+  RISAFx->CR |= RISAF_CR_GLOCK;
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
+
+/**
+  * @brief  Get RISAF global lock status.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @retval 1 if RISAF configuration is locked, else 0
+  */
+uint32_t HAL_RIF_RISAF_GetLock(const RISAF_TypeDef *RISAFx)
+{
+  uint32_t lock_status;
+
+  /* Read RIMC lock bit */
+  lock_status = (RISAFx->CR & RIF_LOCK_ENABLE);
+
+  return lock_status;
+}
+
+#if defined(GENERATOR_RIF_FEATURE_ENCRYPTION_IMPLEMENTED)
+/**
+  * @brief  Get encryption and key related flags.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @retval A combination of the three encryption related flags
+  */
+uint32_t HAL_RIF_RISAF_GetEncryptionStatus(RISAF_TypeDef *RISAFx)
+{
+  uint32_t tmp = 0;
+
+  return tmp;
+}
+
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+/**
+  * @brief  Write the encryption keys used by the DDRMCE.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  Keys Pointer on the Encryption keys structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_WriteEncryptionKeys(RISAF_TypeDef *RISAFx, RISAF_EncryptionKeys_t *Keys)
+{
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
+
+#endif /* defined(GENERATOR_RIF_FEATURE_ENCRYPTION_IMPLEMENTED) */
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+/**
+  * @brief  Configure a RISAF Base region.
+  * @note   If pConfig->Filtering is equal to RISAF_FILTER_DISABLE, this API only disable the filtering without modifying
+  *         its configuration.
+  * @note   It is not possible to modify the start and end address of the region if the filtering is already enabled.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  Region specifies the RISAF region index
+  *         This parameter can be one one of the following values:
+  *           @arg @ref RISAF_REGION_1
+  *           @arg @ref RISAF_REGION_2
+  *           @arg @ref RISAF_REGION_3
+  *           @arg @ref RISAF_REGION_4
+  *           @arg @ref RISAF_REGION_5
+  *           @arg @ref RISAF_REGION_6
+  *           @arg @ref RISAF_REGION_7
+  *           @arg @ref RISAF_REGION_8
+  *           @arg @ref RISAF_REGION_9
+  *           @arg @ref RISAF_REGION_10
+  *           @arg @ref RISAF_REGION_11
+  *           @arg @ref RISAF_REGION_12
+  *           @arg @ref RISAF_REGION_13
+  *           @arg @ref RISAF_REGION_14
+  *           @arg @ref RISAF_REGION_15
+  * @param  pConfig Pointer on RISAF Base Region configuration structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_ConfigBaseRegion(RISAF_TypeDef *RISAFx, uint32_t Region, const RISAF_BaseRegionConfig_t *pConfig)
+{
+  /* Check the parameters */
+  assert_param(pConfig != (void *)NULL);
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+  assert_param(IS_RISAF_REGION(Region));
+  assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
+
+  /* Only disable the section */
+  if (pConfig->Filtering == RISAF_FILTER_DISABLE)
+  {
+    RISAFx->REG[Region].CFGR &= (~(RISAF_FILTER_ENABLE));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_RISAF_FILTERING(pConfig->Filtering));
+    assert_param(IS_RIF_CID(pConfig->PrivWhitelist));
+    assert_param(IS_RIF_CID(pConfig->ReadWhitelist));
+    assert_param(IS_RIF_CID(pConfig->WriteWhitelist));
+    assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->Secure));
+    assert_param(IS_RISAF_GRANULARITY(RISAFx, pConfig->StartAddress));
+    assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->StartAddress));
+    assert_param(IS_RISAF_GRANULARITY(RISAFx, (pConfig->EndAddress + 1U)));
+    assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->EndAddress));
+    assert_param(pConfig->StartAddress < pConfig->EndAddress);
+
+    /* Update region start and end addresses */
+    RISAFx->REG[Region].STARTR = pConfig->StartAddress;
+    RISAFx->REG[Region].ENDR = pConfig->EndAddress;
+
+    /* Update filtering mode, security and privilege attributes and whitelists */
+    RISAFx->REG[Region].CIDCFGR = (pConfig->ReadWhitelist | (pConfig->WriteWhitelist << RISAF_REGx_CIDCFGR_WRENC0_Pos));
+    RISAFx->REG[Region].CFGR = (pConfig->Filtering | (pConfig->Secure << RISAF_REGx_CFGR_SEC_Pos)
+                                | (pConfig->PrivWhitelist << RISAF_REGx_CFGR_PRIVC0_Pos));
+  }
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
+
+/**
+  * @brief  Get the configuration of a RISAF Base region.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  Region specifies the RISAF region index
+  *         This parameter can be one one of the following values:
+  *           @arg @ref RISAF_REGION_1
+  *           @arg @ref RISAF_REGION_2
+  *           @arg @ref RISAF_REGION_3
+  *           @arg @ref RISAF_REGION_4
+  *           @arg @ref RISAF_REGION_5
+  *           @arg @ref RISAF_REGION_6
+  *           @arg @ref RISAF_REGION_7
+  *           @arg @ref RISAF_REGION_8
+  *           @arg @ref RISAF_REGION_9
+  *           @arg @ref RISAF_REGION_10
+  *           @arg @ref RISAF_REGION_11
+  *           @arg @ref RISAF_REGION_12
+  *           @arg @ref RISAF_REGION_13
+  *           @arg @ref RISAF_REGION_14
+  *           @arg @ref RISAF_REGION_15
+  * @param  pConfig Pointer on RISAF Base Region configuration structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_GetConfigBaseRegion(const RISAF_TypeDef *RISAFx, uint32_t Region, RISAF_BaseRegionConfig_t *pConfig)
+{
+  uint32_t cfgr_reg;
+  uint32_t cidcfgr_reg;
+
+  /* Check the parameters */
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+  assert_param(IS_RISAF_REGION(Region));
+  assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
+  assert_param(pConfig != (void *)NULL);
+
+  cfgr_reg = RISAFx->REG[Region].CFGR;
+  cidcfgr_reg = RISAFx->REG[Region].CIDCFGR;
+
+  pConfig->Filtering = (cfgr_reg & RISAF_REGx_CFGR_BREN);
+  pConfig->Secure = ((cfgr_reg & RISAF_REGx_CFGR_SEC) >> RISAF_REGx_CFGR_SEC_Pos);
+  pConfig->PrivWhitelist = ((cfgr_reg & (RIF_CID_MASK << RISAF_REGx_CFGR_PRIVC0_Pos)) >> RISAF_REGx_CFGR_PRIVC0_Pos);
+  pConfig->ReadWhitelist = (cidcfgr_reg & RIF_CID_MASK);
+  pConfig->WriteWhitelist = ((cidcfgr_reg & (RIF_CID_MASK << RISAF_REGx_CIDCFGR_WRENC0_Pos)) >> RISAF_REGx_CIDCFGR_WRENC0_Pos);
+  pConfig->StartAddress = RISAFx->REG[Region].STARTR;
+  pConfig->EndAddress = RISAFx->REG[Region].ENDR;
+}
+
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+/**
+  * @brief  Delegate a Subregion configuration to another CID.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  Region specifies the RISAF region index
+  *         This parameter can be one one of the following values:
+  *           @arg @ref RISAF_REGION_1
+  *           @arg @ref RISAF_REGION_2
+  *           @arg @ref RISAF_REGION_3
+  *           @arg @ref RISAF_REGION_4
+  *           @arg @ref RISAF_REGION_5
+  *           @arg @ref RISAF_REGION_6
+  *           @arg @ref RISAF_REGION_7
+  *           @arg @ref RISAF_REGION_8
+  *           @arg @ref RISAF_REGION_9
+  *           @arg @ref RISAF_REGION_10
+  *           @arg @ref RISAF_REGION_11
+  *           @arg @ref RISAF_REGION_12
+  *           @arg @ref RISAF_REGION_13
+  *           @arg @ref RISAF_REGION_14
+  *           @arg @ref RISAF_REGION_15
+  * @param  SubRegion specifies the RISAB Subregion index
+  *         This parameter can be one of the following values:
+  *           @arg @ref RISAF_SUBREGION_A
+  *           @arg @ref RISAF_SUBREGION_B
+  * @param  pConfig Pointer on RISAF Subregion configuration structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_ConfigSubRegionDelegation(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                             const RISAF_DelegationConfig_t *pConfig)
+{
+  uint32_t cid;
+  uint32_t nestr_reg;
+
+  /* Check the parameters */
+  assert_param(pConfig != (void *)NULL);
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+  assert_param(IS_RISAF_REGION(Region));
+  assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
+  assert_param(IS_RISAF_SUBREGION(SubRegion));
+  assert_param(IS_RISAF_DELEGATION(pConfig->Delegation));
+  assert_param(IS_RIF_SINGLE_CID(pConfig->DelegatedCID));
+
+  /* Convert mask into bit position */
+  cid = POSITION_VAL(pConfig->DelegatedCID);
+
+  if (SubRegion == RISAF_SUBREGION_A)
+  {
+    nestr_reg = RISAFx->REG[Region].ANESTR;
+    nestr_reg &= (~(RISAF_REGx_zNESTR_DCCID | RISAF_REGx_zNESTR_DCEN));
+    nestr_reg |= ((cid << RISAF_REGx_zNESTR_DCCID_Pos) | pConfig->Delegation);
+    RISAFx->REG[Region].ANESTR = nestr_reg;
+  }
+  else
+  {
+    nestr_reg = RISAFx->REG[Region].BNESTR;
+    nestr_reg &= (~(RISAF_REGx_zNESTR_DCCID | RISAF_REGx_zNESTR_DCEN));
+    nestr_reg |= ((cid << RISAF_REGx_zNESTR_DCCID_Pos) | pConfig->Delegation);
+    RISAFx->REG[Region].BNESTR = nestr_reg;
+  }
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
+
+/**
+  * @brief  Get the delegation configuration of a RISAF Subregion.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  Region specifies the RISAF region index
+  *         This parameter can be one one of the following values:
+  *           @arg @ref RISAF_REGION_1
+  *           @arg @ref RISAF_REGION_2
+  *           @arg @ref RISAF_REGION_3
+  *           @arg @ref RISAF_REGION_4
+  *           @arg @ref RISAF_REGION_5
+  *           @arg @ref RISAF_REGION_6
+  *           @arg @ref RISAF_REGION_7
+  *           @arg @ref RISAF_REGION_8
+  *           @arg @ref RISAF_REGION_9
+  *           @arg @ref RISAF_REGION_10
+  *           @arg @ref RISAF_REGION_11
+  *           @arg @ref RISAF_REGION_12
+  *           @arg @ref RISAF_REGION_13
+  *           @arg @ref RISAF_REGION_14
+  *           @arg @ref RISAF_REGION_15
+  * @param  SubRegion specifies the RISAB Subregion index
+  *         This parameter can be one of the following values:
+  *           @arg @ref RISAF_SUBREGION_A
+  *           @arg @ref RISAF_SUBREGION_B
+  * @param  pConfig Pointer on RISAF Subregion configuration structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_GetConfigSubRegionDelegation(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                                RISAF_DelegationConfig_t *pConfig)
+{
+  uint32_t cid;
+
+  /* Check the parameters */
+  assert_param(pConfig != (void *)NULL);
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+  assert_param(IS_RISAF_REGION(Region));
+  assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
+  assert_param(IS_RISAF_SUBREGION(SubRegion));
+
+  if (SubRegion == RISAF_SUBREGION_A)
+  {
+    pConfig->Delegation = (RISAFx->REG[Region].ANESTR & RISAF_REGx_zNESTR_DCEN);
+    cid = ((RISAFx->REG[Region].ANESTR & RISAF_REGx_zNESTR_DCCID) >> RISAF_REGx_zNESTR_DCCID_Pos);
+  }
+  else
+  {
+    pConfig->Delegation = (RISAFx->REG[Region].BNESTR & RISAF_REGx_zNESTR_DCEN);
+    cid = ((RISAFx->REG[Region].BNESTR & RISAF_REGx_zNESTR_DCCID) >> RISAF_REGx_zNESTR_DCCID_Pos);
+  }
+
+  pConfig->DelegatedCID = (1UL << cid);
+}
+
+/**
+  * @brief  Configure a RISAF subregion.
+  * @note   If pConfig->Filtering is equal to RISAF_FILTER_DISABLE, this API only disable the filtering without modifying
+  *         its configuration. It also can lock the current subregion configuration.
+  * @note   It is not possible to modify the start and end address of a subregion if the filtering is already enabled.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  Region specifies the RISAF region index
+  *         This parameter can be one one of the following values:
+  *           @arg @ref RISAF_REGION_1
+  *           @arg @ref RISAF_REGION_2
+  *           @arg @ref RISAF_REGION_3
+  *           @arg @ref RISAF_REGION_4
+  *           @arg @ref RISAF_REGION_5
+  *           @arg @ref RISAF_REGION_6
+  *           @arg @ref RISAF_REGION_7
+  *           @arg @ref RISAF_REGION_8
+  *           @arg @ref RISAF_REGION_9
+  *           @arg @ref RISAF_REGION_10
+  *           @arg @ref RISAF_REGION_11
+  *           @arg @ref RISAF_REGION_12
+  *           @arg @ref RISAF_REGION_13
+  *           @arg @ref RISAF_REGION_14
+  *           @arg @ref RISAF_REGION_15
+  * @param  SubRegion specifies the RISAB Subregion index
+  *         This parameter can be one of the following values:
+  *           @arg @ref RISAF_SUBREGION_A
+  *           @arg @ref RISAF_SUBREGION_B
+  * @param  pConfig Pointer on RISAF Base Region configuration structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_ConfigSubRegion(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                   const RISAF_SubRegionConfig_t *pConfig)
+{
+  uint32_t cid;
+
+  /* Check the parameters */
+  assert_param(pConfig != (void *)NULL);
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+  assert_param(IS_RISAF_REGION(Region));
+  assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
+  assert_param(IS_RISAF_SUBREGION(SubRegion));
+  assert_param(IS_RISAF_FILTERING(pConfig->Filtering));
+  assert_param(IS_RIF_LOCK_STATE(pConfig->Lock));
+
+  /* Convert mask into bit position */
+  cid = POSITION_VAL(pConfig->CID);
+
+  if (SubRegion == RISAF_SUBREGION_A)
+  {
+    if (pConfig->Filtering == RISAF_FILTER_DISABLE)
+    {
+      RISAFx->REG[Region].ACFGR &= (~(RISAF_FILTER_ENABLE | RISAF_REGx_zCFGR_RLOCK));
+      RISAFx->REG[Region].ACFGR |= (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_RISAF_READ_WRITE(pConfig->ReadWrite));
+      assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->SecPriv));
+      assert_param(IS_RISAF_GRANULARITY(RISAFx, pConfig->StartAddress));
+      assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->StartAddress));
+      assert_param(IS_RISAF_GRANULARITY(RISAFx, (pConfig->EndAddress + 1U)));
+      assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->EndAddress));
+      assert_param(pConfig->StartAddress < pConfig->EndAddress);
+
+      RISAFx->REG[Region].ASTARTR = pConfig->StartAddress;
+      RISAFx->REG[Region].AENDR = pConfig->EndAddress;
+      RISAFx->REG[Region].ACFGR = (pConfig->Filtering  | (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos)
+                                   | (cid << RISAF_REGx_zCFGR_SRCID_Pos) | (pConfig->SecPriv << RISAF_REGx_zCFGR_SEC_Pos)
+                                   | (pConfig->ReadWrite));
+    }
+  }
+  else
+  {
+    if (pConfig->Filtering == RISAF_FILTER_DISABLE)
+    {
+      RISAFx->REG[Region].BCFGR &= (~(RISAF_FILTER_ENABLE | RISAF_REGx_zCFGR_RLOCK));
+      RISAFx->REG[Region].BCFGR |= (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_RISAF_READ_WRITE(pConfig->ReadWrite));
+      assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->SecPriv));
+      assert_param(IS_RISAF_GRANULARITY(RISAFx, pConfig->StartAddress));
+      assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->StartAddress));
+      assert_param(IS_RISAF_GRANULARITY(RISAFx, (pConfig->EndAddress + 1U)));
+      assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->EndAddress));
+      assert_param(pConfig->StartAddress < pConfig->EndAddress);
+
+      RISAFx->REG[Region].BSTARTR = pConfig->StartAddress;
+      RISAFx->REG[Region].BENDR = pConfig->EndAddress;
+      RISAFx->REG[Region].BCFGR = (pConfig->Filtering  | (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos)
+                                   | (cid << RISAF_REGx_zCFGR_SRCID_Pos) | (pConfig->SecPriv << RISAF_REGx_zCFGR_SEC_Pos)
+                                   | (pConfig->ReadWrite));
+    }
+  }
+}
+
+/**
+  * @brief  Get the configuration of a RISAF Subregion.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  Region specifies the RISAF region index
+  *         This parameter can be one one of the following values:
+  *           @arg @ref RISAF_REGION_1
+  *           @arg @ref RISAF_REGION_2
+  *           @arg @ref RISAF_REGION_3
+  *           @arg @ref RISAF_REGION_4
+  *           @arg @ref RISAF_REGION_5
+  *           @arg @ref RISAF_REGION_6
+  *           @arg @ref RISAF_REGION_7
+  *           @arg @ref RISAF_REGION_8
+  *           @arg @ref RISAF_REGION_9
+  *           @arg @ref RISAF_REGION_10
+  *           @arg @ref RISAF_REGION_11
+  *           @arg @ref RISAF_REGION_12
+  *           @arg @ref RISAF_REGION_13
+  *           @arg @ref RISAF_REGION_14
+  *           @arg @ref RISAF_REGION_15
+  * @param  SubRegion specifies the RISAB Subregion index
+  *         This parameter can be one of the following values:
+  *           @arg @ref RISAF_SUBREGION_A
+  *           @arg @ref RISAF_SUBREGION_B
+  * @param  pConfig Pointer on RISAF Base Region configuration structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_GetConfigSubRegion(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
+                                      RISAF_SubRegionConfig_t *pConfig)
+{
+  uint32_t cid;
+  uint32_t cfgr_reg;
+
+  /* Check the parameters */
+  assert_param(pConfig != (void *)NULL);
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+  assert_param(IS_RISAF_REGION(Region));
+  assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
+  assert_param(IS_RISAF_SUBREGION(SubRegion));
+
+  if (SubRegion == RISAF_SUBREGION_A)
+  {
+    cfgr_reg = RISAFx->REG[Region].ACFGR;
+    pConfig->StartAddress = RISAFx->REG[Region].ASTARTR;
+    pConfig->EndAddress = RISAFx->REG[Region].AENDR;
+  }
+  else
+  {
+    cfgr_reg = RISAFx->REG[Region].BCFGR;
+    pConfig->StartAddress = RISAFx->REG[Region].BSTARTR;
+    pConfig->EndAddress = RISAFx->REG[Region].BENDR;
+  }
+
+  pConfig->Filtering = (cfgr_reg & RISAF_REGx_zCFGR_SREN);
+  cid = ((cfgr_reg & RISAF_REGx_zCFGR_SRCID) >> RISAF_REGx_zCFGR_SRCID_Pos);
+  pConfig->CID = (1UL << cid);
+  pConfig->SecPriv = ((cfgr_reg & (RISAF_REGx_zCFGR_PRIV | RISAF_REGx_zCFGR_SEC)) >> RISAF_REGx_zCFGR_SEC_Pos);
+  pConfig->ReadWrite = (cfgr_reg & (RISAF_REGx_zCFGR_WREN | RISAF_REGx_zCFGR_RDEN));
+  pConfig->Lock = ((cfgr_reg & RISAF_REGx_zCFGR_RLOCK) >> RISAF_REGx_zCFGR_RLOCK_Pos);
+}
+
+#if defined(CPU_AS_TRUSTED_DOMAIN)
+/**
+  * @brief  Get the error detected by the RISAF control block,
+  *         the illegal access data and clear related flags.
+  *         Error information can be illegal access or control access type. In case of an illegal access detection, the
+  *         error information is:
+  *           - responsible CID;
+  *           - security access type;
+  *           - privilege access type;
+  *           - read (fetch) or write access type;
+  *           - targeted address.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  RISAFx specifies the RISAF instance.
+  *         This parameter is one of the RISAF instances defined in the CMSIS.
+  * @param  IllegalAccess Pointer on illegal access structure
+  * @retval None
+  */
+void HAL_RIF_RISAF_GetIllegalAccess(RISAF_TypeDef *RISAFx, RISAF_IllegalAccess_t *IllegalAccess)
+{
+  uint32_t cid;
+  uint32_t secpriv;
+
+  /* Check the parameters */
+  assert_param(IllegalAccess != (void *)NULL);
+  assert_param(IS_RISAF_INSTANCE(RISAFx));
+
+  /* Get illegal access type */
+  IllegalAccess->ErrorType = (RISAFx->IASR & (RISAF_IASR_IAEF | RISAF_IASR_CAEF));
+
+  if (IllegalAccess->ErrorType != RISAF_ILLEGAL_ACCESS_NONE)
+  {
+    /* Get illegal access data */
+    cid = (RISAFx->IAR->IAESR & RISAF_IAESR_IACID);
+    IllegalAccess->Data.CID = (1UL << cid);
+    secpriv = ((RISAFx->IAR->IAESR & (RISAF_IAESR_IASEC | RISAF_IAESR_IAPRIV)) >> RISAF_IAESR_IAPRIV_Pos);
+    IllegalAccess->Data.SecPriv = ((secpriv >> 1UL) | (secpriv << 1UL)) & 3UL;
+    IllegalAccess->Data.AccessType = ((RISAFx->IAR->IAESR & RISAF_IAESR_IANRW) >> RISAF_IAESR_IANRW_Pos);
+
+    if ((IllegalAccess->ErrorType & RISAF_ILLEGAL_ACCESS) != 0U)
+    {
+      IllegalAccess->Data.Address = RISAFx->IAR->IADDR;
+    }
+    else
+    {
+      IllegalAccess->Data.Address = 0U;
+    }
+
+    /* Clear flags */
+    RISAFx->IACR = (RISAF_IACR_IAEF | RISAF_IACR_CAEF);
+  }
+}
+#endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
+/**
+  * @}
+  */
+
+/** @defgroup RIF_Exported_Functions_Group6  IAC Configuration functions
+  * @brief    IAC Configuration functions
+  *
+@verbatim
+  ==============================================================================
+            ##### IAC Configuration functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to configure IAC
+    IAC is Illegal Access Controller
+@endverbatim
+  * @{
+  */
+#if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
+/**
+  * @brief  Enable interrupt generation on illegal access detection on peripheral or memory access.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @note   This API is protected by the TrustZone Enabled compilation directive.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval None
+  */
+void HAL_RIF_IAC_EnableIT(uint32_t PeriphId)
+{
+  __IO uint32_t *p_interrupt_reg;
+
+  /* Check parameters */
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
+
+  p_interrupt_reg = &(IAC->IER[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  *p_interrupt_reg |= (1UL << (PeriphId & RIF_PERIPH_BIT_POSITION));
+
+}
+
+/**
+  * @brief  Disable interrupt generation on illegal access detection on peripheral or memory access.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval None
+  */
+void HAL_RIF_IAC_DisableIT(uint32_t PeriphId)
+{
+  __IO uint32_t *p_interrupt_reg;
+
+  /* Check parameters */
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
+
+  p_interrupt_reg = &(IAC->IER[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  *p_interrupt_reg &= (~(1UL << (PeriphId & RIF_PERIPH_BIT_POSITION)));
+}
+
+/**
+  * @brief  Get illegal access detection flag.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval Detection flag value
+  */
+uint32_t HAL_RIF_IAC_GetFlag(uint32_t PeriphId)
+{
+  uint32_t interrupt_flag;
+  const __IO uint32_t *p_interrupt_reg;
+  uint32_t shift_var;
+
+  /* Check parameters */
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
+
+  shift_var = (PeriphId & RIF_PERIPH_BIT_POSITION);
+  p_interrupt_reg = &(IAC->ISR[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  interrupt_flag = ((*p_interrupt_reg & (1UL << shift_var)) >> shift_var);
+
+  return interrupt_flag;
+}
+
+/**
+  * @brief  Clear illegal access detection flag.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval None
+  */
+void HAL_RIF_IAC_ClearFlag(uint32_t PeriphId)
+{
+  __IO uint32_t *p_interrupt_reg;
+
+  /* Check parameters */
+  assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
+
+  p_interrupt_reg = &(IAC->ICR[PeriphId >> RIF_PERIPH_REG_SHIFT]);
+  *p_interrupt_reg = (1UL << (PeriphId & RIF_PERIPH_BIT_POSITION));
+}
+
+/**
+  * @brief  Parse all pending flags and call callback when necessary.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @retval None
+  */
+void HAL_RIF_IRQHandler(void)
+{
+  uint32_t reg_index;
+  uint32_t flag_mask;
+  uint32_t position;
+  uint32_t periph_id;
+
+  for (reg_index = 0 ; reg_index < (RIF_PERIPH_IAC_REG_MAX + 1U) ; reg_index++)
+  {
+    flag_mask = IAC->ISR[reg_index];
+
+    position = 0U;
+    while ((flag_mask >> position) != 0U)
+    {
+      if ((flag_mask & (1UL << position)) != 0U)
+      {
+        periph_id = ((reg_index << RIF_PERIPH_REG_SHIFT) | position);
+        HAL_RIF_IAC_ClearFlag(periph_id);
+        HAL_RIF_ILA_Callback(periph_id);
+      }
+      position++;
+    }
+  }
+}
+
+/**
+  * @brief  RIF illegal access callback.
+  * @note   This API is protected by the Trusted Domain compilation directive.
+  * @note   This API is protected by the TrustZone Enabled compilation directive.
+  * @param  PeriphId specifies the index of the bus slave.
+  *         This parameter can be one of @ref RIF_PERIPHERAL_INDEX
+  * @retval None
+  */
+__weak void HAL_RIF_ILA_Callback(uint32_t PeriphId)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(PeriphId);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+                 the HAL_RIF_ILA_Callback could be implemented in the user file
+  */
+}
+#endif /* CPU_AS_TRUSTED_DOMAIN && CPU_IN_SECURE_STATE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RIF_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rng.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rng.c
new file mode 100644
index 000000000..1d769f4cc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rng.c
@@ -0,0 +1,1025 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rng.c
+  * @author  MCD Application Team
+  * @brief   RNG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Random Number Generator (RNG) peripheral:
+  *           + Initialization and configuration functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The RNG HAL driver can be used as follows:
+
+      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
+          in HAL_RNG_MspInit().
+      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+      (#) Wait until the 32 bit Random Number Generator contains a valid
+          random data using (polling/interrupt) mode.
+      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_RNG_RegisterCallback() to register a user callback.
+    Function HAL_RNG_RegisterCallback() allows to register following callbacks:
+    (+) ErrorCallback             : RNG Error Callback.
+    (+) MspInitCallback           : RNG MspInit.
+    (+) MspDeInitCallback         : RNG MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function.
+    HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) ErrorCallback             : RNG Error Callback.
+    (+) MspInitCallback           : RNG MspInit.
+    (+) MspDeInitCallback         : RNG MspDeInit.
+
+    [..]
+    For specific callback ReadyDataCallback, use dedicated register callbacks:
+    respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
+
+    [..]
+    By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+    all callbacks are set to the corresponding weak (overridden) functions:
+    example HAL_RNG_ErrorCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
+    and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
+    or HAL_RNG_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @addtogroup RNG
+  * @brief RNG HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG Private Constants
+  * @{
+  */
+#define RNG_TIMEOUT_VALUE     4U
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group1
+  *  @brief   Initialization and configuration functions
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the RNG according to the specified parameters
+          in the RNG_InitTypeDef and create the associated handle
+      (+) DeInitialize the RNG peripheral
+      (+) Initialize the RNG MSP
+      (+) DeInitialize RNG MSP
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the RNG peripheral and creates the associated handle.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{
+  uint32_t tickstart;
+  /* Check the RNG handle allocation */
+  if (hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+  assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  if (hrng->State == HAL_RNG_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
+    hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
+    hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
+
+    if (hrng->MspInitCallback == NULL)
+    {
+      hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hrng->MspInitCallback(hrng);
+  }
+#else
+  if (hrng->State == HAL_RNG_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_RNG_MspInit(hrng);
+  }
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+  /* Change RNG peripheral state */
+  hrng->State = HAL_RNG_STATE_BUSY;
+
+  /* Disable RNG */
+  __HAL_RNG_DISABLE(hrng);
+
+  /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
+  MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
+
+  /* Writing bit CONDRST=0 */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for conditioning reset process to be completed */
+  while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+  {
+    if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+      {
+        hrng->State = HAL_RNG_STATE_READY;
+        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Enable the RNG Peripheral */
+  __HAL_RNG_ENABLE(hrng);
+
+  /* verify that no seed error */
+  if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+  {
+    hrng->State = HAL_RNG_STATE_ERROR;
+    return HAL_ERROR;
+  }
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  /* Check if data register contains valid random data */
+  while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET)
+  {
+    if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET)
+      {
+        hrng->State = HAL_RNG_STATE_ERROR;
+        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Initialize the RNG state */
+  hrng->State = HAL_RNG_STATE_READY;
+
+  /* Initialise the error code */
+  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the RNG peripheral.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{
+  uint32_t tickstart;
+
+  /* Check the RNG handle allocation */
+  if (hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Clear Clock Error Detection bit when CONDRT bit is set to 1 */
+  MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST);
+
+  /* Writing bit CONDRST=0 */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for conditioning reset process to be completed */
+  while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+  {
+    if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+      {
+        hrng->State = HAL_RNG_STATE_READY;
+        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrng);
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Disable the RNG Peripheral */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
+
+  /* Clear RNG interrupt status flags */
+  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  if (hrng->MspDeInitCallback == NULL)
+  {
+    hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hrng->MspDeInitCallback(hrng);
+#else
+  /* DeInit the low level hardware */
+  HAL_RNG_MspDeInit(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+  /* Update the RNG state */
+  hrng->State = HAL_RNG_STATE_RESET;
+
+  /* Initialise the error code */
+  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+
+  /* Return the function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RNG MSP.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitializes the RNG MSP.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspDeInit must be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User RNG Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hrng RNG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+                                           pRNG_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_ERROR_CB_ID :
+        hrng->ErrorCallback = pCallback;
+        break;
+
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RNG_STATE_RESET == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an RNG Callback
+  *         RNG callback is redirected to the weak predefined callback
+  * @param  hrng RNG handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_ERROR_CB_ID :
+        hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
+        break;
+
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RNG_STATE_RESET == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Data Ready RNG Callback
+  *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
+  * @param  hrng RNG handle
+  * @param  pCallback pointer to the Data Ready Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    hrng->ReadyDataCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Data Ready RNG Callback
+  *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
+  * @param  hrng RNG handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group2
+  *  @brief   Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Get the 32 bit Random number
+      (+) Get the 32 bit Random number with interrupt enabled
+      (+) Handle RNG interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Generates a 32-bit random number.
+  * @note   This function checks value of RNG_FLAG_DRDY flag to know if valid
+  *         random number is available in the DR register (RNG_FLAG_DRDY flag set
+  *         whenever a random number is available through the RNG_DR register).
+  *         After transitioning from 0 to 1 (random number available),
+  *         RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
+  *         four words from the RNG_DR register, i.e. further function calls
+  *         will immediately return a new u32 random number (additional words are
+  *         available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
+  * @note   When no more random number data is available in DR register, RNG_FLAG_DRDY
+  *         flag is automatically cleared.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @param  random32bit pointer to generated random number variable if successful.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+    /* Check if there is a seed error */
+    if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+    {
+      /* Update the error code */
+      hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+      /* Reset from seed error */
+      status = RNG_RecoverSeedError(hrng);
+      if (status == HAL_ERROR)
+      {
+        return status;
+      }
+    }
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Check if data register contains valid random data */
+    while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+    {
+      if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+        {
+          hrng->State = HAL_RNG_STATE_READY;
+          hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hrng);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get a 32bit Random number */
+    hrng->RandomNumber = hrng->Instance->DR;
+    /* In case of seed error, the value available in the RNG_DR register must not
+       be used as it may not have enough entropy */
+    if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+    {
+      /* Update the error code and status */
+      hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+      status = HAL_ERROR;
+    }
+    else /* No seed error */
+    {
+      *random32bit = hrng->RandomNumber;
+    }
+    hrng->State = HAL_RNG_STATE_READY;
+  }
+  else
+  {
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrng);
+
+  return status;
+}
+
+/**
+  * @brief  Generates a 32-bit random number in interrupt mode.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+    __HAL_RNG_ENABLE_IT(hrng);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles RNG interrupt request.
+  * @note   In the case of a clock error, the RNG is no more able to generate
+  *         random numbers because the PLL48CLK clock is not correct. User has
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
+  *         The clock error has no impact on the previously generated
+  *         random numbers, and the RNG_DR register contents can be used.
+  * @note   In the case of a seed error, the generation of random numbers is
+  *         interrupted as long as the SECS bit is '1'. If a number is
+  *         available in the RNG_DR register, it must not be used because it may
+  *         not have enough entropy. In this case, it is recommended to clear the
+  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
+  *         the RNG peripheral to reinitialize and restart the RNG.
+  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+  *         or CEIS are set.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+
+  */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+  uint32_t rngclockerror = 0U;
+  uint32_t itflag   = hrng->Instance->SR;
+
+  /* RNG clock error interrupt occurred */
+  if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+    rngclockerror = 1U;
+  }
+  else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
+  {
+    /* Check if Seed Error Current Status (SECS) is set */
+    if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS)
+    {
+      /* RNG IP performed the reset automatically (auto-reset) */
+      /* Clear bit SEIS */
+      CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+    }
+    else
+    {
+      /* Seed Error has not been recovered : Update the error code */
+      hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+      rngclockerror = 1U;
+      /* Disable the IT */
+      __HAL_RNG_DISABLE_IT(hrng);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if (rngclockerror == 1U)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback */
+    hrng->ErrorCallback(hrng);
+#else
+    /* Call legacy weak Error callback */
+    HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+    /* Clear the clock error flag */
+    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
+
+    return;
+  }
+
+  /* Check RNG data ready interrupt occurred */
+  if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
+  {
+    /* Generate random number once, so disable the IT */
+    __HAL_RNG_DISABLE_IT(hrng);
+
+    /* Get the 32bit Random number (DRDY flag automatically cleared) */
+    hrng->RandomNumber = hrng->Instance->DR;
+
+    if (hrng->State != HAL_RNG_STATE_ERROR)
+    {
+      /* Change RNG peripheral state */
+      hrng->State = HAL_RNG_STATE_READY;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hrng);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+      /* Call registered Data Ready callback */
+      hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
+#else
+      /* Call legacy weak Data Ready callback */
+      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Read latest generated random number.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval random value
+  */
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng)
+{
+  return (hrng->RandomNumber);
+}
+
+/**
+  * @brief  Data Ready callback in non-blocking mode.
+  * @note   When RNG_FLAG_DRDY flag value is set, first random number has been read
+  *         from DR register in IRQ Handler and is provided as callback parameter.
+  *         Depending on valid data available in the conditioning output buffer,
+  *         additional words can be read by the application from DR register till
+  *         DRDY bit remains high.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @param  random32bit generated random number.
+  * @retval None
+  */
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  UNUSED(random32bit);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  RNG error callbacks.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ErrorCallback must be implemented in the user file.
+   */
+}
+/**
+  * @}
+  */
+
+
+/** @addtogroup RNG_Exported_Functions_Group3
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the RNG state.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL state
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng)
+{
+  return hrng->State;
+}
+
+/**
+  * @brief  Return the RNG handle error code.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval RNG Error Code
+  */
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng)
+{
+  /* Return RNG Error Code */
+  return hrng->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  RNG sequence to recover from a seed error
+  * @param  hrng pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+  __IO uint32_t count = 0U;
+
+  /*Check if seed error current status (SECS)is set */
+  if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+  {
+    /* RNG performed the reset automatically (auto-reset) */
+    /* Clear bit SEIS */
+    CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+  }
+  else  /* Sequence to fully recover from a seed error*/
+  {
+    /* Writing bit CONDRST=1*/
+    SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+    /* Writing bit CONDRST=0*/
+    CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+    /* Wait for conditioning reset process to be completed */
+    count = RNG_TIMEOUT_VALUE;
+    do
+    {
+      count-- ;
+      if (count == 0U)
+      {
+        hrng->State = HAL_RNG_STATE_READY;
+        hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+        /* Call registered Error callback */
+        hrng->ErrorCallback(hrng);
+#else
+        /* Call legacy weak Error callback */
+        HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+        return HAL_ERROR;
+      }
+    } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
+
+    if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+    {
+      /* Clear bit SEIS */
+      CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+    }
+
+    /* Wait for SECS to be cleared */
+    count = RNG_TIMEOUT_VALUE;
+    do
+    {
+      count-- ;
+      if (count == 0U)
+      {
+        hrng->State = HAL_RNG_STATE_READY;
+        hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+        /* Call registered Error callback */
+        hrng->ErrorCallback(hrng);
+#else
+        /* Call legacy weak Error callback */
+        HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+        return HAL_ERROR;
+      }
+    } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
+  }
+  /* Update the error code */
+  hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED;
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rng_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rng_ex.c
new file mode 100644
index 000000000..1d64276eb
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rng_ex.c
@@ -0,0 +1,339 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rng_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended RNG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Random Number Generator (RNG) peripheral:
+  *           + Lock configuration functions
+  *           + Reset the RNG
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#if defined(RNG)
+
+/** @addtogroup RNGEx
+  * @brief RNG Extended HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#if defined(RNG_CR_CONDRST)
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RNGEx_Private_Constants
+  * @{
+  */
+#define RNG_TIMEOUT_VALUE     2U
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions  --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
+  * @{
+  */
+
+/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions
+  *  @brief   Configuration functions
+  *
+@verbatim
+ ===============================================================================
+          ##### Configuration and lock functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef
+      (+) Lock RNG configuration Allows user to lock a configuration until next reset.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the RNG with the specified parameters in the
+  *         RNG_ConfigTypeDef.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *          the configuration information for RNG.
+  * @param  pConf pointer to a RNG_ConfigTypeDef structure that contains
+  *         the configuration information for RNG module
+
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf)
+{
+  uint32_t tickstart;
+  uint32_t cr_value;
+  HAL_StatusTypeDef status ;
+
+  /* Check the RNG handle allocation */
+  if ((hrng == NULL) || (pConf == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+  assert_param(IS_RNG_CLOCK_DIVIDER(pConf->ClockDivider));
+  assert_param(IS_RNG_NIST_COMPLIANCE(pConf->NistCompliance));
+  assert_param(IS_RNG_CONFIG1(pConf->Config1));
+  assert_param(IS_RNG_CONFIG2(pConf->Config2));
+  assert_param(IS_RNG_CONFIG3(pConf->Config3));
+  assert_param(IS_RNG_ARDIS(pConf->AutoReset));
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* Disable RNG */
+    __HAL_RNG_DISABLE(hrng);
+
+    /* RNG CR register configuration. Set value in CR register for :
+        - NIST Compliance setting
+        - Clock divider value
+        - Automatic reset to clear SECS bit
+        - CONFIG 1, CONFIG 2 and CONFIG 3 values */
+    cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance | pConf->AutoReset
+                          | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
+                          | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
+                          | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
+
+    MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
+               | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_ARDIS,
+               (uint32_t)(RNG_CR_CONDRST | cr_value));
+
+    /* RNG health test control in accordance with NIST */
+    WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest);
+
+    /* Writing bit CONDRST=0*/
+    CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait for conditioning reset process to be completed */
+    while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+    {
+      if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of prememption */
+        if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+        {
+          hrng->State = HAL_RNG_STATE_READY;
+          hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Enable RNG */
+    __HAL_RNG_ENABLE(hrng);
+
+    /* Initialize the RNG state */
+    hrng->State = HAL_RNG_STATE_READY;
+
+    /* function status */
+    status = HAL_OK;
+  }
+  else
+  {
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return the function status */
+  return status;
+}
+
+/**
+  * @brief  Get the RNG Configuration and fill parameters in the
+  *         RNG_ConfigTypeDef.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *          the configuration information for RNG.
+  * @param  pConf pointer to a RNG_ConfigTypeDef structure that contains
+  *         the configuration information for RNG module
+
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
+{
+
+  HAL_StatusTypeDef status ;
+
+  /* Check the RNG handle allocation */
+  if ((hrng == NULL) || (pConf == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* Get  RNG parameters  */
+    pConf->Config1        = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ;
+    pConf->Config2        = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
+    pConf->Config3        = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
+    pConf->ClockDivider   = (hrng->Instance->CR & RNG_CR_CLKDIV);
+    pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC);
+    pConf->AutoReset      = (hrng->Instance->CR & RNG_CR_ARDIS);
+    pConf->HealthTest     = (hrng->Instance->HTCR);
+
+    /* Initialize the RNG state */
+    hrng->State = HAL_RNG_STATE_READY;
+
+    /* function status */
+    status = HAL_OK;
+  }
+  else
+  {
+    hrng->ErrorCode |= HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return the function status */
+  return status;
+}
+
+/**
+  * @brief  RNG current configuration lock.
+  * @note   This function allows to lock RNG peripheral configuration.
+  *         Once locked, HW RNG reset has to be performed prior any further
+  *         configuration update.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the RNG handle allocation */
+  if (hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* Perform RNG configuration Lock */
+    MODIFY_REG(hrng->Instance->CR, RNG_CR_CONFIGLOCK, RNG_CR_CONFIGLOCK);
+
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_READY;
+
+    /* function status */
+    status = HAL_OK;
+  }
+  else
+  {
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return the function status */
+  return status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function
+  *  @brief   Recover from seed error function
+  *
+@verbatim
+ ===============================================================================
+          ##### Recover from seed error function #####
+ ===============================================================================
+    [..]  This section provide function allowing to:
+      (+) Recover from a seed error
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  RNG sequence to recover from a seed error
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the RNG handle allocation */
+  if (hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* sequence to fully recover from a seed error */
+    status = RNG_RecoverSeedError(hrng);
+  }
+  else
+  {
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Return the function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* RNG_CR_CONDRST */
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rtc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rtc.c
new file mode 100644
index 000000000..86e845dbf
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rtc.c
@@ -0,0 +1,2284 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rtc.c
+  * @author  GPM Application Team
+  * @brief   RTC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Calendar (Time and Date) configuration
+  *           + Alarms (Alarm A and Alarm B) configuration
+  *           + WakeUp Timer configuration
+  *           + TimeStamp configuration
+  *           + Tampers configuration
+  *           + Backup Data Registers configuration
+  *           + RTC Tamper and TimeStamp Pins Selection
+  *           + Interrupts and flags management
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                          ##### RTC Operating Condition #####
+ ===============================================================================
+  [..] The real-time clock (RTC) and the RTC backup registers can be powered
+       from the VBAT voltage when the main VDD supply is powered off.
+       To retain the content of the RTC backup registers and supply the RTC
+       when VDD is turned off, VBAT pin can be connected to an optional
+       standby voltage supplied by a battery or by another source.
+
+                   ##### Backup Domain Reset #####
+ ===============================================================================
+  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
+       to their reset values.
+       A backup domain reset is generated when one of the following events occurs:
+    (#) Software reset, triggered by setting the BDRST bit in the
+        RCC Backup domain control register (RCC_BDCR).
+    (#) VDD or VBAT power on, if both supplies have previously been powered off.
+    (#) Tamper detection event resets all data backup registers.
+
+                   ##### Backup Domain Access #####
+  ==================================================================
+  [..] After reset, the backup domain (RTC registers and RTC backup data registers)
+       is protected against possible unwanted write accesses.
+  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+    (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for
+        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32)
+    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+
+                  ##### How to use RTC Driver #####
+ ===================================================================
+  [..]
+    (+) Enable the RTC domain access (see description in the section above).
+    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+        format using the HAL_RTC_Init() function.
+
+  *** Time and Date configuration ***
+  ===================================
+  [..]
+    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+        and HAL_RTC_SetDate() functions.
+    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+  *** Alarm configuration ***
+  ===========================
+  [..]
+    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+            You can also configure the RTC Alarm with interrupt mode using the
+            HAL_RTC_SetAlarm_IT() function.
+    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+                  ##### RTC and low power modes #####
+  ==================================================================
+  [..] The MCU can be woken up from a low power mode by an RTC alternate
+       function.
+  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+       These RTC alternate functions can wake up the system from the Stop and
+       Standby low power modes.
+  [..] The system can also wake up from low power modes without depending
+       on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+       or the RTC wakeup events.
+  [..] The RTC provides a programmable time base for waking up from the
+       Stop or Standby mode at regular intervals.
+       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
+       is LSE or LSI.
+
+  *** Callback registration ***
+  =============================================
+  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions. This is the recommended configuration
+  in order to optimize memory/code consumption footprint/performances.
+
+  The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
+
+  Function HAL_RTC_RegisterCallback() allows to register following callbacks:
+    (+) AlarmAEventCallback             : RTC Alarm A Event callback.
+    (+) AlarmBEventCallback             : RTC Alarm B Event callback.
+    (+) TimeStampEventCallback          : RTC TimeStamp Event callback.
+    (+) WakeUpTimerEventCallback        : RTC WakeUpTimer Event callback.
+    (+) SSRUEventCallback               : RTC SSRU Event callback.
+    (+) Tamper1EventCallback            : RTC Tamper 1 Event callback.
+    (+) Tamper2EventCallback            : RTC Tamper 2 Event callback.
+    (+) Tamper3EventCallback            : RTC Tamper 3 Event callback.
+    (+) Tamper4EventCallback            : RTC Tamper 4 Event callback.
+    (+) Tamper5EventCallback            : RTC Tamper 5 Event callback.
+    (+) Tamper6EventCallback            : RTC Tamper 6 Event callback.
+    (+) Tamper7EventCallback            : RTC Tamper 7 Event callback.
+    (+) Tamper8EventCallback            : RTC Tamper 8 Event callback.
+    (+) InternalTamper1EventCallback    : RTC InternalTamper 1 Event callback.
+    (+) InternalTamper2EventCallback    : RTC InternalTamper 2 Event callback.
+    (+) InternalTamper3EventCallback    : RTC InternalTamper 3 Event callback.
+    (+) InternalTamper4EventCallback    : RTC InternalTamper 4 Event callback.
+    (+) InternalTamper5EventCallback    : RTC InternalTamper 5 Event callback.
+    (+) InternalTamper6EventCallback    : RTC InternalTamper 6 Event callback.
+    (+) InternalTamper7EventCallback    : RTC InternalTamper 7 Event callback.
+    (+) InternalTamper8EventCallback    : RTC InternalTamper 8 Event callback.
+    (+) InternalTamper9EventCallback    : RTC InternalTamper 9 Event callback.
+    (+) InternalTamper11EventCallback   : RTC InternalTamper 11 Event callback.
+    (+) MspInitCallback                 : RTC MspInit callback.
+    (+) MspDeInitCallback               : RTC MspDeInit callback.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) AlarmAEventCallback             : RTC Alarm A Event callback.
+    (+) AlarmBEventCallback             : RTC Alarm B Event callback.
+    (+) TimeStampEventCallback          : RTC TimeStamp Event callback.
+    (+) WakeUpTimerEventCallback        : RTC WakeUpTimer Event callback.
+    (+) SSRUEventCallback               : RTC SSRU Event callback.
+    (+) Tamper1EventCallback            : RTC Tamper 1 Event callback.
+    (+) Tamper2EventCallback            : RTC Tamper 2 Event callback.
+    (+) Tamper3EventCallback            : RTC Tamper 3 Event callback.
+    (+) Tamper4EventCallback            : RTC Tamper 4 Event callback.
+    (+) Tamper5EventCallback            : RTC Tamper 5 Event callback.
+    (+) Tamper6EventCallback            : RTC Tamper 6 Event callback.
+    (+) Tamper7EventCallback            : RTC Tamper 7 Event callback.
+    (+) Tamper8EventCallback            : RTC Tamper 8 Event callback.
+    (+) InternalTamper1EventCallback    : RTC InternalTamper 1 Event callback.
+    (+) InternalTamper2EventCallback    : RTC InternalTamper 2 Event callback.
+    (+) InternalTamper3EventCallback    : RTC InternalTamper 3 Event callback.
+    (+) InternalTamper4EventCallback    : RTC InternalTamper 4 Event callback.
+    (+) InternalTamper5EventCallback    : RTC InternalTamper 5 Event callback.
+    (+) InternalTamper6EventCallback    : RTC InternalTamper 6 Event callback.
+    (+) InternalTamper7EventCallback    : RTC InternalTamper 7 Event callback.
+    (+) InternalTamper8EventCallback    : RTC InternalTamper 8 Event callback.
+    (+) InternalTamper9EventCallback    : RTC InternalTamper 9 Event callback.
+    (+) InternalTamper11EventCallback   : RTC InternalTamper 11 Event callback.
+    (+) MspInitCallback                 : RTC MspInit callback.
+    (+) MspDeInitCallback               : RTC MspDeInit callback.
+
+  By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+  all callbacks are set to the corresponding weak functions :
+  examples AlarmAEventCallback(), TimeStampEventCallback().
+  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
+  in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
+  (not registered beforehand).
+  If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
+  or HAL_RTC_Init() function.
+
+  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+
+/** @addtogroup RTC
+  * @brief RTC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RTC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+   [..] This section provides functions allowing to initialize and configure the
+         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+         RTC registers Write protection, enter and exit the RTC initialization mode,
+         RTC registers synchronization check and reference clock detection enable.
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+             It is split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the
+                 asynchronous prescaler to a high value to minimize power consumption.
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WPR.
+         (#) To configure the RTC Calendar, user application should enter
+             initialization mode. In this mode, the calendar counter is stopped
+             and its value can be updated. When the initialization sequence is
+             complete, the calendar restarts counting after 4 RTCCLK cycles.
+         (#) To read the calendar through the shadow registers after Calendar
+             initialization, calendar update or after wakeup from low power modes
+             the software must first clear the RSF flag. The software must then
+             wait until it is set again before reading the calendar, which means
+             that the calendar registers have been correctly copied into the
+             RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function
+             implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the RTC peripheral
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Check the RTC peripheral state */
+  if (hrtc != NULL)
+  {
+    /* Check the parameters */
+    assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+    assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+    assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+    assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+    assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+    assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+    assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+    assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
+    assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
+    assert_param(IS_RTC_BINARY_MODE(hrtc->Init.BinMode));
+    assert_param(IS_RTC_BINARY_MIX_BCDU(hrtc->Init.BinMixBcdU));
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    if (hrtc->State == HAL_RTC_STATE_RESET)
+    {
+      /* Allocate lock resource and initialize it */
+      hrtc->Lock = HAL_UNLOCKED;
+
+      /* Legacy weak AlarmAEventCallback */
+      hrtc->AlarmAEventCallback           = HAL_RTC_AlarmAEventCallback;
+      /* Legacy weak AlarmBEventCallback */
+      hrtc->AlarmBEventCallback           = HAL_RTCEx_AlarmBEventCallback;
+      /* Legacy weak TimeStampEventCallback */
+      hrtc->TimeStampEventCallback        = HAL_RTCEx_TimeStampEventCallback;
+      /* Legacy weak WakeUpTimerEventCallback */
+      hrtc->WakeUpTimerEventCallback      = HAL_RTCEx_WakeUpTimerEventCallback;
+      /* Legacy weak SSRUEventCallback */
+      hrtc->SSRUEventCallback             = HAL_RTCEx_SSRUEventCallback;
+      /* Legacy weak Tamper1EventCallback */
+      hrtc->Tamper1EventCallback          = HAL_RTCEx_Tamper1EventCallback;
+      /* Legacy weak Tamper2EventCallback */
+      hrtc->Tamper2EventCallback          = HAL_RTCEx_Tamper2EventCallback;
+      /* Legacy weak Tamper3EventCallback */
+      hrtc->Tamper3EventCallback          = HAL_RTCEx_Tamper3EventCallback;
+      /* Legacy weak Tamper4EventCallback */
+      hrtc->Tamper4EventCallback          = HAL_RTCEx_Tamper4EventCallback;
+      /* Legacy weak Tamper5EventCallback */
+      hrtc->Tamper5EventCallback          = HAL_RTCEx_Tamper5EventCallback;
+      /* Legacy weak Tamper6EventCallback */
+      hrtc->Tamper6EventCallback          = HAL_RTCEx_Tamper6EventCallback;
+      /* Legacy weak Tamper7EventCallback */
+      hrtc->Tamper7EventCallback          = HAL_RTCEx_Tamper7EventCallback;
+      /* Legacy weak Tamper8EventCallback */
+      hrtc->Tamper8EventCallback          = HAL_RTCEx_Tamper8EventCallback;
+      /* Legacy weak InternalTamper1EventCallback */
+      hrtc->InternalTamper1EventCallback  = HAL_RTCEx_InternalTamper1EventCallback;
+      /* Legacy weak InternalTamper2EventCallback */
+      hrtc->InternalTamper2EventCallback  = HAL_RTCEx_InternalTamper2EventCallback;
+      /* Legacy weak InternalTamper3EventCallback */
+      hrtc->InternalTamper3EventCallback  = HAL_RTCEx_InternalTamper3EventCallback;
+      /* Legacy weak InternalTamper4EventCallback */
+      hrtc->InternalTamper4EventCallback  = HAL_RTCEx_InternalTamper4EventCallback;
+      /* Legacy weak InternalTamper5EventCallback */
+      hrtc->InternalTamper5EventCallback  = HAL_RTCEx_InternalTamper5EventCallback;
+      /* Legacy weak InternalTamper6EventCallback */
+      hrtc->InternalTamper6EventCallback  = HAL_RTCEx_InternalTamper6EventCallback;
+      /* Legacy weak InternalTamper7EventCallback */
+      hrtc->InternalTamper7EventCallback  = HAL_RTCEx_InternalTamper7EventCallback;
+      /* Legacy weak InternalTamper8EventCallback */
+      hrtc->InternalTamper8EventCallback  = HAL_RTCEx_InternalTamper8EventCallback;
+      /* Legacy weak InternalTamper9EventCallback */
+      hrtc->InternalTamper9EventCallback  = HAL_RTCEx_InternalTamper9EventCallback;
+      /* Legacy weak InternalTamper11EventCallback */
+      hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback;
+
+      if (hrtc->MspInitCallback == NULL)
+      {
+        hrtc->MspInitCallback = HAL_RTC_MspInit;
+      }
+      /* Init the low level hardware */
+      hrtc->MspInitCallback(hrtc);
+
+      if (hrtc->MspDeInitCallback == NULL)
+      {
+        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+      }
+    }
+#else
+    if (hrtc->State == HAL_RTC_STATE_RESET)
+    {
+      /* Allocate lock resource and initialize it */
+      hrtc->Lock = HAL_UNLOCKED;
+
+      /* Initialize RTC MSP */
+      HAL_RTC_MspInit(hrtc);
+    }
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_BUSY;
+
+    /* Check if the calendar has been not initialized */
+    if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
+    {
+      /* Disable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+      /* Enter Initialization mode */
+      status = RTC_EnterInitMode(hrtc);
+      if (status == HAL_OK)
+      {
+        /* Clear RTC_CR FMT, OSEL and POL Bits */
+        CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
+
+        /* Set RTC_CR register */
+        SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity));
+
+        /* Configure the RTC PRER */
+        WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
+
+        /* Configure the Binary mode */
+        MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
+
+        /* Exit Initialization mode */
+        status = RTC_ExitInitMode(hrtc);
+
+        if (status == HAL_OK)
+        {
+          MODIFY_REG(RTC->CR, \
+                     RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
+                     hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
+        }
+      }
+
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    }
+    else
+    {
+      /* Calendar is already initialized */
+      /* Set flag to OK */
+      status = HAL_OK;
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Change RTC state */
+      hrtc->State = HAL_RTC_STATE_READY;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the RTC peripheral.
+  * @note   This function does not reset the RTC Backup Data registers.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t          tickstart;
+
+  /* Check RTC handler */
+  if (hrtc != NULL)
+  {
+    /* Check the parameters */
+    assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+
+    /* Set RTC state */
+    hrtc->State = HAL_RTC_STATE_BUSY;
+
+    /* Disable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+    /* Enter Initialization mode */
+    status = RTC_EnterInitMode(hrtc);
+    if (status == HAL_OK)
+    {
+      /* Reset All CR bits except CR[2:0] (which cannot be written before bit
+        WUTE of CR is cleared) */
+      CLEAR_REG(RTC->CR);
+
+      /* Reset TR and DR registers */
+      WRITE_REG(RTC->DR, (uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+      CLEAR_REG(RTC->TR);
+
+      /* Reset other RTC registers */
+      WRITE_REG(RTC->PRER, ((uint32_t)(RTC_PRER_PREDIV_A | 0xFFU)));
+      CLEAR_REG(RTC->ALRMAR);
+      CLEAR_REG(RTC->ALRMBR);
+      CLEAR_REG(RTC->SHIFTR);
+      CLEAR_REG(RTC->CALR);
+      CLEAR_REG(RTC->ALRMASSR);
+      CLEAR_REG(RTC->ALRMBSSR);
+      CLEAR_BIT(RTC->ICSR, (RTC_ICSR_BCDU_Msk | RTC_ICSR_BIN_Msk));
+      WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSOVF | RTC_SCR_CTSF | RTC_SCR_CWUTF | RTC_SCR_CALRBF | \
+                RTC_SCR_CALRAF);
+#if defined (CPU_IN_SECURE_STATE)
+      CLEAR_REG(RTC->SECCFGR);
+#endif /* defined (CPU_IN_SECURE_STATE) */
+      CLEAR_REG(RTC->PRIVCFGR);
+
+      /* Exit initialization mode */
+      status = RTC_ExitInitMode(hrtc);
+
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Wait till WUTWF is set (to be able to reset CR[2:0] and WUTR) and if
+         timeout is reached exit */
+      tickstart = HAL_GetTick();
+
+      while ((((hrtc->Instance->ICSR)  & RTC_ICSR_WUTWF)  == 0U) && (status != HAL_TIMEOUT))
+      {
+        if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+        {
+          /* New check to avoid false timeout detection in case of preemption */
+          if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+          {
+            /* Set RTC state */
+            hrtc->State = HAL_RTC_STATE_TIMEOUT;
+            status = HAL_TIMEOUT;
+          }
+          else
+          {
+            break;
+          }
+        }
+      }
+
+      /* Reset RTC CR register bits [2:0] */
+      CLEAR_REG(RTC->CR);
+
+      /* Reset RTC WUTR register */
+      WRITE_REG(RTC->WUTR, RTC_WUTR_WUT);
+
+      /* Reset TAMP registers */
+      CLEAR_REG(TAMP->CR1);
+      CLEAR_REG(TAMP->CR2);
+      CLEAR_REG(TAMP->CR3);
+      CLEAR_REG(TAMP->FLTCR);
+      WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL_0 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_2);
+      CLEAR_REG(TAMP->ATOR);
+      CLEAR_REG(TAMP->ATCR2);
+#if defined (CPU_IN_SECURE_STATE)
+      CLEAR_REG(TAMP->SECCFGR);
+#endif /* defined (CPU_IN_SECURE_STATE) */
+      CLEAR_REG(TAMP->PRIVCFGR);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+      if (hrtc->MspDeInitCallback == NULL)
+      {
+        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+      }
+
+      /* DeInit the low level hardware: CLOCK, NVIC.*/
+      hrtc->MspDeInitCallback(hrtc);
+
+#else
+      /* De-Initialize RTC MSP */
+      HAL_RTC_MspDeInit(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+      /* Change RTC state */
+      hrtc->State = HAL_RTC_STATE_RESET;
+
+      /* Release Lock */
+      __HAL_UNLOCK(hrtc);
+
+    }
+  }
+
+  return status;
+}
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User RTC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hrtc RTC handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID            Alarm A Event Callback ID
+  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID            Alarm B Event Callback ID
+  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID          TimeStamp Event Callback ID
+  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID        WakeUp Timer Event Callback ID
+  *          @arg @ref HAL_RTC_SSRU_EVENT_CB_ID               SSRU Event Callback ID
+  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID            Tamper 1 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID            Tamper 2 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID            Tamper 3 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID            Tamper 4 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID            Tamper 5 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID            Tamper 6 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID            Tamper 7 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID            Tamper 8 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID   Internal Tamper 1 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID   Internal Tamper 2 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID   Internal Tamper 3 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID   Internal Tamper 4 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID   Internal Tamper 5 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID   Internal Tamper 6 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID   Internal Tamper 7 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID   Internal Tamper 8 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID   Internal Tamper 9 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID  Internal Tamper 11 Callback ID
+  *          @arg @ref HAL_RTC_MSPINIT_CB_ID                  Msp Init callback ID
+  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID                Msp DeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @note  The HAL_RTC_RegisterCallback() may be called before HAL_RTC_Init() in HAL_RTC_STATE_RESET
+  *        to register callbacks for HAL_RTC_MSPINIT_CB_ID and HAL_RTC_MSPDEINIT_CB_ID.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
+                                           pRTC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (HAL_RTC_STATE_READY == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_ALARM_A_EVENT_CB_ID :
+        hrtc->AlarmAEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_ALARM_B_EVENT_CB_ID :
+        hrtc->AlarmBEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+        hrtc->TimeStampEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+        hrtc->WakeUpTimerEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_SSRU_EVENT_CB_ID :
+        hrtc->SSRUEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER1_EVENT_CB_ID :
+        hrtc->Tamper1EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER2_EVENT_CB_ID :
+        hrtc->Tamper2EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER3_EVENT_CB_ID :
+        hrtc->Tamper3EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER4_EVENT_CB_ID :
+        hrtc->Tamper4EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER5_EVENT_CB_ID :
+        hrtc->Tamper5EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER6_EVENT_CB_ID :
+        hrtc->Tamper6EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER7_EVENT_CB_ID :
+        hrtc->Tamper7EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER8_EVENT_CB_ID :
+        hrtc->Tamper8EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
+        hrtc->InternalTamper1EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
+        hrtc->InternalTamper2EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
+        hrtc->InternalTamper3EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
+        hrtc->InternalTamper4EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
+        hrtc->InternalTamper5EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
+        hrtc->InternalTamper6EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID :
+        hrtc->InternalTamper7EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
+        hrtc->InternalTamper8EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID :
+        hrtc->InternalTamper9EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID :
+        hrtc->InternalTamper11EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RTC_STATE_RESET == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an RTC Callback
+  *         RTC callback is redirected to the weak predefined callback
+  * @param  hrtc RTC handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID              Alarm A Event Callback ID
+  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID              Alarm B Event Callback ID
+  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID            TimeStamp Event Callback ID
+  *          @arg @ref HAL_RTC_SSRU_EVENT_CB_ID                 SSRU Callback ID
+  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID          WakeUp Timer Event Callback ID
+  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID              Tamper 1 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID              Tamper 2 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID              Tamper 3 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID              Tamper 4 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID              Tamper 5 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID              Tamper 6 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER7_EVENT_CB_ID              Tamper 7 Callback ID
+  *          @arg @ref HAL_RTC_TAMPER8_EVENT_CB_ID              Tamper 8 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID     Internal Tamper 1 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID     Internal Tamper 2 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID     Internal Tamper 3 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID     Internal Tamper 4 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID     Internal Tamper 5 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID     Internal Tamper 6 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID     Internal Tamper 7 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID     Internal Tamper 8 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID     Internal Tamper 9 Callback ID
+  *          @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID    Internal Tamper 11 Callback ID
+  *          @arg @ref HAL_RTC_MSPINIT_CB_ID                    Msp Init callback ID
+  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID                  Msp DeInit callback ID
+  * @note  The HAL_RTC_UnRegisterCallback() may be called before HAL_RTC_Init() in HAL_RTC_STATE_RESET
+  *        to un-register callbacks for HAL_RTC_MSPINIT_CB_ID and HAL_RTC_MSPDEINIT_CB_ID.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_RTC_STATE_READY == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_ALARM_A_EVENT_CB_ID :
+        /* Legacy weak AlarmAEventCallback */
+        hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;
+        break;
+
+      case HAL_RTC_ALARM_B_EVENT_CB_ID :
+        /* Legacy weak AlarmBEventCallback */
+        hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;
+        break;
+
+      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+        /* Legacy weak TimeStampEventCallback */
+        hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;
+        break;
+
+      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+        /* Legacy weak WakeUpTimerEventCallback */
+        hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback;
+        break;
+
+      case HAL_RTC_SSRU_EVENT_CB_ID :
+        /* Legacy weak SSRUEventCallback */
+        hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback;
+        break;
+
+      case HAL_RTC_TAMPER1_EVENT_CB_ID :
+        /* Legacy weak Tamper1EventCallback */
+        hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;
+        break;
+
+      case HAL_RTC_TAMPER2_EVENT_CB_ID :
+        /* Legacy weak Tamper2EventCallback */
+        hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback;
+        break;
+
+      case HAL_RTC_TAMPER3_EVENT_CB_ID :
+        /* Legacy weak Tamper3EventCallback */
+        hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;
+        break;
+
+      case HAL_RTC_TAMPER4_EVENT_CB_ID :
+        /* Legacy weak Tamper4EventCallback */
+        hrtc->Tamper4EventCallback = HAL_RTCEx_Tamper4EventCallback;
+        break;
+
+      case HAL_RTC_TAMPER5_EVENT_CB_ID :
+        /* Legacy weak Tamper5EventCallback */
+        hrtc->Tamper5EventCallback = HAL_RTCEx_Tamper5EventCallback;
+        break;
+
+      case HAL_RTC_TAMPER6_EVENT_CB_ID :
+        /* Legacy weak Tamper6EventCallback */
+        hrtc->Tamper6EventCallback = HAL_RTCEx_Tamper6EventCallback;
+        break;
+
+      case HAL_RTC_TAMPER7_EVENT_CB_ID :
+        /* Legacy weak Tamper7EventCallback */
+        hrtc->Tamper7EventCallback = HAL_RTCEx_Tamper7EventCallback;
+        break;
+
+      case HAL_RTC_TAMPER8_EVENT_CB_ID :
+        /* Legacy weak Tamper8EventCallback */
+        hrtc->Tamper8EventCallback = HAL_RTCEx_Tamper8EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
+        /* Legacy weak InternalTamper1EventCallback */
+        hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
+        /* Legacy weak InternalTamper2EventCallback */
+        hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
+        /* Legacy weak InternalTamper3EventCallback */
+        hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
+        /* Legacy weak InternalTamper4EventCallback */
+        hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
+        /* Legacy weak InternalTamper5EventCallback */
+        hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
+        /* Legacy weak InternalTamper6EventCallback */
+        hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID :
+        /* Legacy weak InternalTamper7EventCallback */
+        hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
+        /* Legacy weak InternalTamper8EventCallback */
+        hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID :
+        /* Legacy weak InternalTamper9EventCallback */
+        hrtc->InternalTamper9EventCallback = HAL_RTCEx_InternalTamper9EventCallback;
+        break;
+
+      case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID :
+        /* Legacy weak InternalTamper11EventCallback */
+        hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback;
+        break;
+
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = HAL_RTC_MspInit;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RTC_STATE_RESET == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = HAL_RTC_MspInit;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Initialize the RTC MSP.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the RTC MSP.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+  *  @brief   RTC Time and Date functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set RTC current time.
+  * @param  hrtc RTC handle
+  * @param  sTime Pointer to Time structure
+  *          if Binary mode is RTC_BINARY_ONLY, this parameter is not used and RTC_SSR will be automatically
+  *          reset to 0xFFFFFFFF
+  *          else sTime->SubSeconds is not used and RTC_SSR will be automatically reset to the
+  *          A 7-bit async prescaler (RTC_PRER_PREDIV_A)
+  * @param  Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds.
+  *          if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+  *          else this parameter can be one of the following values
+  *             @arg RTC_FORMAT_BIN: Binary format
+  *             @arg RTC_FORMAT_BCD: BCD format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+  uint32_t tmpreg;
+  HAL_StatusTypeDef status;
+
+#ifdef USE_FULL_ASSERT
+  /* Check the parameters depending of the Binary mode with 32-bit free-running counter configuration */
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(Format));
+  }
+#endif /* USE_FULL_ASSERT */
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Enter Initialization mode */
+  status = RTC_EnterInitMode(hrtc);
+  if (status == HAL_OK)
+  {
+    /* Check Binary mode ((32-bit free-running counter) */
+    if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY)
+    {
+      if (Format == RTC_FORMAT_BIN)
+      {
+        if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+        {
+          assert_param(IS_RTC_HOUR12(sTime->Hours));
+          assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+        }
+        else
+        {
+          sTime->TimeFormat = 0x00U;
+          assert_param(IS_RTC_HOUR24(sTime->Hours));
+        }
+        assert_param(IS_RTC_MINUTES(sTime->Minutes));
+        assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+        tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \
+                            ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+                            ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \
+                            (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
+      }
+      else
+      {
+        if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+        {
+          assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
+          assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+        }
+        else
+        {
+          sTime->TimeFormat = 0x00U;
+          assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+        }
+        assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+        assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+        tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \
+                  ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+                  ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \
+                  ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
+      }
+
+      /* Set the RTC_TR register */
+      WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK));
+
+      /* Clear the bits to be configured */
+      CLEAR_BIT(RTC->CR, RTC_CR_BKP);
+    }
+
+    /* Exit Initialization mode */
+    status = RTC_ExitInitMode(hrtc);
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  if (status == HAL_OK)
+  {
+    /* Change RTC state */
+    hrtc->State = HAL_RTC_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return status;
+}
+
+/**
+  * @brief  Get RTC current time.
+  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+  *        value in second fraction ratio with time unit following generic formula:
+  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
+  *        to ensure consistency between the time and date values.
+  * @param  hrtc RTC handle
+  * @param  sTime
+  *          if Binary mode is RTC_BINARY_ONLY, sTime->SubSeconds only is updated
+  *          else
+  *             Pointer to Time structure with Hours, Minutes and Seconds fields returned
+  *               with input format (BIN or BCD), also SubSeconds field returning the
+  *               RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
+  *               factor to be used for second fraction ratio computation.
+  * @param  Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds.
+  *          if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+  *          else this parameter can be one of the following values:
+  *            @arg RTC_FORMAT_BIN: Binary format
+  *            @arg RTC_FORMAT_BCD: BCD format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+  uint32_t tmpreg;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Get subseconds structure field from the corresponding register */
+  sTime->SubSeconds = READ_REG(RTC->SSR);
+
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY)
+  {
+    /* Check the parameters */
+    assert_param(IS_RTC_FORMAT(Format));
+
+    /* Get SecondFraction structure field from the corresponding register field */
+    sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S);
+
+    /* Get the TR register */
+    tmpreg = (uint32_t)(READ_REG(RTC->TR) & RTC_TR_RESERVED_MASK);
+
+    /* Fill the structure fields with the read parameters */
+    sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
+    sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+    sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
+    sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos);
+
+    /* Check the input parameters format */
+    if (Format == RTC_FORMAT_BIN)
+    {
+      /* Convert the time structure parameters to Binary format */
+      sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+      sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+      sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set RTC current date.
+  * @param  hrtc RTC handle
+  * @param  sDate Pointer to date structure
+  * @param  Format Format of sDate->Year, sDate->Month and sDate->Weekday.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FORMAT_BIN: Binary format
+  *            @arg RTC_FORMAT_BCD: BCD format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+  uint32_t datetmpreg;
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
+  {
+    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
+  }
+
+  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+  if (Format == RTC_FORMAT_BIN)
+  {
+    assert_param(IS_RTC_YEAR(sDate->Year));
+    assert_param(IS_RTC_MONTH(sDate->Month));
+    assert_param(IS_RTC_DATE(sDate->Date));
+
+    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \
+                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
+                  ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \
+                  ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+    assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+    assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
+
+    datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \
+                  (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \
+                  (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \
+                  (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
+  }
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Enter Initialization mode */
+  status = RTC_EnterInitMode(hrtc);
+  if (status == HAL_OK)
+  {
+    /* Set the RTC_DR register */
+    WRITE_REG(RTC->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK));
+
+    /* Exit Initialization mode */
+    status = RTC_ExitInitMode(hrtc);
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  if (status == HAL_OK)
+  {
+    /* Change RTC state */
+    hrtc->State = HAL_RTC_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return status;
+}
+
+/**
+  * @brief  Get RTC current date.
+  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
+  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+  * @param  hrtc RTC handle
+  * @param  sDate Pointer to Date structure
+  * @param  Format Format of sDate->Year, sDate->Month and sDate->Weekday.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FORMAT_BIN: Binary format
+  *            @arg RTC_FORMAT_BCD: BCD format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+  uint32_t datetmpreg;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+  /* Get the DR register */
+  datetmpreg = (uint32_t)(READ_REG(RTC->DR) & RTC_DR_RESERVED_MASK);
+
+  /* Fill the structure fields with the read parameters */
+  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
+  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
+  sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos);
+  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos);
+
+  /* Check the input parameters format */
+  if (Format == RTC_FORMAT_BIN)
+  {
+    /* Convert the date structure parameters to Binary format */
+    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Daylight Saving Time, Add one hour to the calendar in one single operation
+  *         without going through the initialization procedure.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set RTC_CR_ADD1H Bit */
+  SET_BIT(RTC->CR, RTC_CR_ADD1H);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+  * @brief  Daylight Saving Time, Subtract one hour from the calendar in one
+  *         single operation without going through the initialization procedure.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Set RTC_CR_SUB1H Bit */
+  SET_BIT(RTC->CR, RTC_CR_SUB1H);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+  * @brief  Daylight Saving Time, Set the store operation bit.
+  * @note   It can be used by the software in order to memorize the DST status.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Set RTC_CR_BKP Bit */
+  SET_BIT(RTC->CR, RTC_CR_BKP);
+}
+
+/**
+  * @brief  Daylight Saving Time, Clear the store operation bit.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Clear RTC_CR_BKP Bit */
+  CLEAR_BIT(RTC->CR, RTC_CR_BKP);
+}
+
+/**
+  * @brief  Daylight Saving Time, Read the store operation bit.
+  * @param  hrtc RTC handle
+  * @retval operation see RTC_StoreOperation_Definitions
+  */
+uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Get RTC_CR_BKP Bit */
+  return READ_BIT(RTC->CR, RTC_CR_BKP);
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+  *  @brief   RTC Alarm functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @param  hrtc RTC handle
+  * @param  sAlarm Pointer to Alarm structure
+  *          if Binary mode is RTC_BINARY_ONLY, 3 fields only are used
+  *             sAlarm->AlarmTime.SubSeconds
+  *             sAlarm->AlarmSubSecondMask
+  *             sAlarm->BinaryAutoClr
+  * @param  Format of the entered parameters.
+  *          if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+  *          else this parameter can be one of the following values
+  *             @arg RTC_FORMAT_BIN: Binary format
+  *             @arg RTC_FORMAT_BCD: BCD format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+  uint32_t tmpreg = 0;
+  uint32_t binary_mode;
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+#ifdef  USE_FULL_ASSERT
+  /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration) */
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE)
+  {
+    assert_param(IS_RTC_FORMAT(Format));
+    assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+    assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+    assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+    assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+    assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+  }
+  else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY)
+  {
+    assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask));
+    assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr));
+  }
+  else /* RTC_BINARY_MIX */
+  {
+    assert_param(IS_RTC_FORMAT(Format));
+    assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+    assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+    assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+    /* In Binary Mix Mode, the RTC can not generate an alarm on a match
+       involving all calendar items + the upper SSR bits */
+    assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <=
+                 (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos)));
+  }
+#endif /* USE_FULL_ASSERT */
+
+  /* Get Binary mode (32-bit free-running counter configuration) */
+  binary_mode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN);
+
+  if (binary_mode != RTC_BINARY_ONLY)
+  {
+    if (Format == RTC_FORMAT_BIN)
+    {
+      if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+      {
+        assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+        assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+      }
+      else
+      {
+        sAlarm->AlarmTime.TimeFormat = 0x00U;
+        assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+      }
+      assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+      assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+      if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+      }
+      else
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+      }
+      tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+                ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+                ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+                ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+                ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+                ((uint32_t)sAlarm->AlarmMask));
+    }
+    else /* format BCD */
+    {
+      if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+      {
+        assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+        assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+      }
+      else
+      {
+        sAlarm->AlarmTime.TimeFormat = 0x00U;
+        assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+      }
+
+      assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+      assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+#ifdef  USE_FULL_ASSERT
+      if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+      }
+      else
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+      }
+
+#endif /* USE_FULL_ASSERT */
+      tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+                ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+                ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+                ((uint32_t)sAlarm->AlarmMask));
+    }
+  }
+
+  /* Configure the Alarm register */
+  if (sAlarm->Alarm == RTC_ALARM_A)
+  {
+    /* Disable the Alarm A interrupt */
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
+    CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
+
+    /* Clear flag alarm A */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+    if (binary_mode == RTC_BINARY_ONLY)
+    {
+      WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr);
+    }
+    else
+    {
+      WRITE_REG(RTC->ALRMAR, tmpreg);
+      WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask);
+    }
+
+    WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds);
+
+    if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+    {
+      /* Configure the  Alarm A output clear */
+      SET_BIT(RTC->CR, RTC_CR_ALRAFCLR);
+    }
+    else
+    {
+      /* Disable the  Alarm A  output clear */
+      CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR);
+    }
+    /* Configure the Alarm state: Enable Alarm */
+    SET_BIT(RTC->CR, RTC_CR_ALRAE);
+  }
+  else
+  {
+    /* Disable the Alarm B interrupt */
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
+    CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
+
+    /* Clear flag alarm B */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+    if (binary_mode == RTC_BINARY_ONLY)
+    {
+      WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr);
+    }
+    else
+    {
+      WRITE_REG(RTC->ALRMBR, tmpreg);
+
+      WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask);
+    }
+
+    WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds);
+
+    if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+    {
+      /* Configure the  Alarm B output clear */
+      SET_BIT(RTC->CR, RTC_CR_ALRBFCLR);
+    }
+    else
+    {
+      /* Disable the  Alarm B output clear */
+      CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR);
+    }
+
+    /* Configure the Alarm state: Enable Alarm */
+    SET_BIT(RTC->CR, RTC_CR_ALRBE);
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the specified RTC Alarm with Interrupt.
+  * @note   The application must ensure that the EXTI RTC interrupt line is enabled.
+  * @param  hrtc RTC handle
+  * @param  sAlarm Pointer to Alarm structure
+  *          if Binary mode is RTC_BINARY_ONLY, 3 fields only are used
+  *             sAlarm->AlarmTime.SubSeconds
+  *             sAlarm->AlarmSubSecondMask
+  *             sAlarm->BinaryAutoClr
+  * @param  Format Specifies the format of the entered parameters.
+  *          if Binary mode is RTC_BINARY_ONLY, this parameter is not used
+  *          else this parameter can be one of the following values
+  *             @arg RTC_FORMAT_BIN: Binary format
+  *             @arg RTC_FORMAT_BCD: BCD format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+  uint32_t tmpreg = 0;
+  uint32_t binary_mode;
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+#ifdef  USE_FULL_ASSERT
+  /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration) */
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE)
+  {
+    assert_param(IS_RTC_FORMAT(Format));
+    assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+    assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+    assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+    assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+    assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+  }
+  else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY)
+  {
+    assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask));
+    assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr));
+  }
+  else /* RTC_BINARY_MIX */
+  {
+    assert_param(IS_RTC_FORMAT(Format));
+    assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+    assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+    assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+    /* In Binary Mix Mode, the RTC can not generate an alarm on a match
+      involving all calendar items + the upper SSR bits */
+    assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <=
+                 (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos)));
+  }
+#endif /* USE_FULL_ASSERT */
+
+  /* Get Binary mode (32-bit free-running counter configuration) */
+  binary_mode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN);
+
+  if (binary_mode != RTC_BINARY_ONLY)
+  {
+    if (Format == RTC_FORMAT_BIN)
+    {
+      if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+      {
+        assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+        assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+      }
+      else
+      {
+        sAlarm->AlarmTime.TimeFormat = 0x00U;
+        assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+      }
+      assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+      assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+      if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+      }
+      else
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+      }
+      tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+                ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+                ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+                ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+                ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+                ((uint32_t)sAlarm->AlarmMask));
+    }
+    else /* Format BCD */
+    {
+      if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
+      {
+        assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+        assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+      }
+      else
+      {
+        sAlarm->AlarmTime.TimeFormat = 0x00U;
+        assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+      }
+
+      assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+      assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+#ifdef  USE_FULL_ASSERT
+      if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+      }
+      else
+      {
+        assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+      }
+
+#endif /* USE_FULL_ASSERT */
+      tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \
+                ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \
+                ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+                ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+                ((uint32_t)sAlarm->AlarmMask));
+
+    }
+  }
+
+  /* Configure the Alarm registers */
+  if (sAlarm->Alarm == RTC_ALARM_A)
+  {
+    /* Disable the Alarm A interrupt */
+    CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
+
+    /* Clear flag alarm A */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+    if (binary_mode == RTC_BINARY_ONLY)
+    {
+      RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr;
+    }
+    else
+    {
+      WRITE_REG(RTC->ALRMAR, tmpreg);
+
+      WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask);
+    }
+
+    WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds);
+
+    if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+    {
+      /* Configure the  Alarm A output clear */
+      SET_BIT(RTC->CR, RTC_CR_ALRAFCLR);
+    }
+    else
+    {
+      /* Disable the Alarm A output clear */
+      CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR);
+    }
+
+    /* Configure the Alarm interrupt */
+    SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
+  }
+  else
+  {
+    /* Disable the Alarm B interrupt */
+    CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
+
+    /* Clear flag alarm B */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+    if (binary_mode == RTC_BINARY_ONLY)
+    {
+      WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr);
+    }
+    else
+    {
+      WRITE_REG(RTC->ALRMBR, tmpreg);
+
+      WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask);
+    }
+
+    WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds);
+
+    if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE)
+    {
+      /* Configure the  Alarm B Output clear */
+      SET_BIT(RTC->CR, RTC_CR_ALRBFCLR);
+    }
+    else
+    {
+      /* Disable the  Alarm B Output clear */
+      CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR);
+    }
+
+    /* Configure the Alarm interrupt */
+    SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate the specified RTC Alarm.
+  * @param  hrtc RTC handle
+  * @param  Alarm Specifies the Alarm.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_ALARM_A:  AlarmA
+  *            @arg RTC_ALARM_B:  AlarmB
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(Alarm));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* In case of interrupt mode is used, the interrupt source must disabled */
+  if (Alarm == RTC_ALARM_A)
+  {
+    CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE);
+
+    /* AlarmA, Clear SSCLR */
+    CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR);
+  }
+  else
+  {
+    CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
+
+    /* AlarmB, Clear SSCLR */
+    CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR);
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  hrtc RTC handle
+  * @param  sAlarm Pointer to Date structure
+  * @param  Alarm Specifies the Alarm.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_ALARM_A: AlarmA
+  *             @arg RTC_ALARM_B: AlarmB
+  * @param  Format Specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_FORMAT_BIN: Binary format
+  *             @arg RTC_FORMAT_BCD: BCD format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm,
+                                   uint32_t Format)
+{
+  uint32_t tmpreg;
+  uint32_t subsecondtmpreg;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+  assert_param(IS_RTC_ALARM(Alarm));
+
+  if (Alarm == RTC_ALARM_A)
+  {
+    /* AlarmA */
+    sAlarm->Alarm = RTC_ALARM_A;
+
+    tmpreg = READ_REG(RTC->ALRMAR);
+    subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+
+    /* Fill the structure with the read parameters */
+    sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos);
+    sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
+    sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos);
+    sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos);
+    sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+    sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos);
+    sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+    sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+  }
+  else
+  {
+    sAlarm->Alarm = RTC_ALARM_B;
+
+    tmpreg = READ_REG(RTC->ALRMBR);
+    subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
+
+    /* Fill the structure with the read parameters */
+    sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos);
+    sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos);
+    sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos);
+    sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos);
+    sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+    sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos);
+    sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL);
+    sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+  }
+
+  if (Format == RTC_FORMAT_BIN)
+  {
+    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+  }
+
+  return HAL_OK;
+}
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Handle Alarm secure interrupt request.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Get interrupt status */
+  uint32_t tmp = READ_REG(RTC->SMISR);
+
+  if ((tmp & RTC_SMISR_ALRAMF) != 0U)
+  {
+    /* Clear the AlarmA interrupt pending bit */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Compare Match registered Callback */
+    hrtc->AlarmAEventCallback(hrtc);
+#else
+    HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  if ((tmp & RTC_SMISR_ALRBMF) != 0U)
+  {
+    /* Clear the AlarmB interrupt pending bit */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Compare Match registered Callback */
+    hrtc->AlarmBEventCallback(hrtc);
+#else
+    HAL_RTCEx_AlarmBEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+
+#else /* defined (CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Handle Alarm non-secure interrupt request.
+  * @note   Alarm non-secure is available in non-secure driver.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Get interrupt status */
+  uint32_t tmp = READ_REG(RTC->MISR);
+
+  if ((tmp & RTC_MISR_ALRAMF) != 0U)
+  {
+    /* Clear the AlarmA interrupt pending bit */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Compare Match registered Callback */
+    hrtc->AlarmAEventCallback(hrtc);
+#else
+    HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  if ((tmp & RTC_MISR_ALRBMF) != 0U)
+  {
+    /* Clear the AlarmB interrupt pending bit */
+    WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Compare Match registered Callback */
+    hrtc->AlarmBEventCallback(hrtc);
+#else
+    HAL_RTCEx_AlarmBEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+#endif /* defined (CPU_IN_SECURE_STATE) */
+
+/**
+  * @brief  Alarm A secure callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the secure callback is needed,
+            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Handle Alarm A Polling request.
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  uint32_t tickstart = HAL_GetTick();
+
+  while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U)
+        {
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  /* Clear the Alarm interrupt pending bit */
+  WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group4
+  *  @brief   Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the
+  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar
+  *         initialization, calendar update or after wakeup from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t tickstart;
+
+  /* Clear RSF flag */
+  CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait the registers to be synchronised */
+  while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U)
+      {
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        return HAL_TIMEOUT;
+      }
+      else
+      {
+        break;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group5
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Get RTC state
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the RTC handle state.
+  * @param  hrtc RTC handle
+  * @retval HAL state
+  */
+HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc)
+{
+  /* Return RTC handle state */
+  return hrtc->State;
+}
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Enter the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check if the Initialization mode is set */
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+  {
+    /* Set the Initialization mode */
+    SET_BIT(RTC->ICSR, RTC_ICSR_INIT);
+
+    tickstart = HAL_GetTick();
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
+    {
+      if ((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+        {
+          status = HAL_TIMEOUT;
+
+          /* Change RTC state */
+          hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Exit the RTC Initialization mode.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Exit Initialization mode */
+  CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+
+  /* If CR_BYPSHAD bit = 0, wait for synchro */
+  if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
+  {
+    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+    {
+      /* Change RTC state */
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+      status = HAL_TIMEOUT;
+    }
+  }
+  else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */
+  {
+    /* Clear BYPSHAD bit */
+    CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
+    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+    {
+      /* Change RTC state */
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+      status = HAL_TIMEOUT;
+    }
+    /* Restore BYPSHAD bit */
+    SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+  }
+  return status;
+}
+
+/**
+  * @brief  Convert a 2 digit decimal to BCD format.
+  * @param  Value Byte to be converted
+  * @retval Converted byte
+  */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint32_t bcd_high = 0U;
+  uint8_t tmp_value = Value;
+
+  while (tmp_value >= 10U)
+  {
+    bcd_high++;
+    tmp_value -= 10U;
+  }
+
+  return ((uint8_t)(bcd_high << 4U) | tmp_value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value BCD value to be converted
+  * @retval Converted word
+  */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint32_t tmp;
+
+  tmp = (((uint32_t)Value & 0xF0U) >> 4) * 10U;
+
+  return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rtc_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rtc_ex.c
new file mode 100644
index 000000000..bd7439fd3
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_rtc_ex.c
@@ -0,0 +1,2999 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_rtc_ex.c
+  * @author  GPM Application Team
+  * @brief   Extended RTC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Real Time Clock (RTC) Extended peripheral:
+  *           + RTC Time Stamp functions
+  *           + RTC Tamper functions
+  *           + RTC Wake-up functions
+  *           + Extended Control functions
+  *           + Extended RTC features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                  ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (+) Enable the RTC domain access.
+    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+        format using the HAL_RTC_Init() function.
+
+  *** RTC Wakeup configuration ***
+  ================================
+  [..]
+    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+        function. You can also configure the RTC Wakeup timer with interrupt mode
+        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+        function.
+
+  *** Outputs configuration ***
+  =============================
+  [..]  The RTC has 2 outputs pins (RTC_OUT1 & RTC_OUT2).
+        To configure the outputs, use the HAL_RTC_Init() function.
+    (+) RTC_OUT1 and RTC_OUT2 which select one of the following two outputs:
+    (+) CALIB: 512Hz or 1Hz clock output (with an LSE frequency of 32.768kHz).
+        To enable the CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function.
+    (+) TAMPALRM: This output is the OR between rtc_tamp_evt and ALARM signals.
+        ALARM is enabled by configuring the OSEL[1:0] bits in the RTC_CR register
+        which select the alarm A, alarm B or wakeup outputs.
+        rtc_tamp_evt is enabled by setting the TAMPOE bit
+        in the RTC_CR register which selects the tamper event outputs.
+
+  *** Smooth digital Calibration configuration ***
+  ================================================
+  [..]
+    (+) Configure the RTC Original Digital Calibration Value and the corresponding
+        calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib()
+        function.
+
+  *** RTC synchronization ***
+  ================================================
+  [..]
+    (+) The RTC can be finely adjusted using HAL_RTCEx_SetSynchroShift() function.
+        Writing to RTC_SHIFTR can shift (either delay or advance) the clock with
+        a resolution of 1 ck_apre period.
+        The shift operation consists in adding the SUBFS[14:0] value to the synchronous
+        prescaler counter SS[15:0]: this delays the clock.
+
+  *** Bypass shadow registers ***
+  ================================================
+  [..]
+    (+) Enable bypass shadow registers using the HAL_RTCEx_EnableBypassShadow().
+        When the Bypass Shadow is enabled the calendar value are taken directly
+        from the Calendar counter.
+        Thus eliminating the need to wait for the RSF bit to be set.
+        This is especially useful after exiting from low-power modes (Stop or Standby),
+        since the shadow registers are not updated during these modes.
+
+  *** RTC ultra-low-power mode ***
+  ================================================
+  [..]
+    (+) Configure the RTC ultra-low-power mode using HAL_RTCEx_SetLowPowerCalib() function.
+        In this case, the calibration mechanism is applied on ck_apre instead of RTCCLK.
+        The resulting accuracy is the same, but the calibration is performed during a
+        calibration cycle of about 220 x PREDIV_A x RTCCLK pulses instead of 220 RTCCLK pulses.
+
+  *** RTC subsecond register underflow interruption ***
+  ================================================
+  [..]
+    (+) Enable the RTC SSRU interruption mode using HAL_RTCEx_SetSSRU_IT() function.
+        In this case, when the SSR rolls under 0, an SSRU interruption is triggered.
+        Disable the RTC SSRU interruption mode using HAL_RTCEx_DeactivateSSRU() function.
+
+  *** TimeStamp configuration ***
+  ===============================
+  [..]
+    (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function.
+        You can also configure the RTC TimeStamp with interrupt mode using the
+        HAL_RTCEx_SetTimeStamp_IT() function.
+    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+        function.
+
+  *** Internal TimeStamp configuration ***
+  ===============================
+  [..]
+    (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function.
+        User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG.
+    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+        function.
+
+   *** Tamper configuration ***
+   ============================
+   [..]
+     (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
+         or Level according to the Tamper filter (if equal to 0 Edge else Level)
+         value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and
+         Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper
+         with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
+     (+) The default configuration of the Tamper erases the backup registers. To avoid
+         erase, enable the TAMPxPOM field on the TAMP_CR2 register.
+     (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to
+         perform TAMP base address offset calculation.
+     (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using
+         setting Interrupt field.
+
+   *** Backup Data Registers and Device Secrets configuration ***
+   ===========================================
+   [..]
+     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+         function.
+     (+) To read the RTC Backup registers, use the HAL_RTCEx_BKUPRead()
+         function.
+     (+) To reset the RTC Backup registers and erase the device secrets,
+         use HAL_RTCEx_BKUPErase() function.
+     (+) Enable the lock of the Boot hardware Key using the HAL_RTCEx_LockBootHardwareKey()
+         function.
+         The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in
+         read nor in write (they are read as 0 and write ignore).
+     (+) Configure the erase of the Device Secrets using HAL_RTCEx_ConfigEraseDeviceSecrets()
+         function.
+     (+) Block the access to the RTC Backup registers and all the device secrets
+         using HAL_RTCEx_BKUPBlock() function.
+
+  *** Monotonic counter ***
+  ================================================
+  [..]
+     (+) To increment the Monotonic counter, use the HAL_RTCEx_MonotonicCounterIncrement()
+         function.
+     (+) To get the current value of the Monotonic counter, use the HAL_RTCEx_MonotonicCounterGet()
+         function.
+
+  *** RTC & TAMP secure protection modes ***
+  ================================================
+  [..]
+     (+) Set the security level of the RTC/TAMP/Backup registers using HAL_RTCEx_SecureModeSet()
+         function.
+      +) Get the security level of the RTC/TAMP/Backup registers using HAL_RTCEx_SecureModeGet()
+         function.
+
+  *** RTC & TAMP privilege protection modes ***
+  ================================================
+  [..]
+     (+) Set the privilege level of the RTC/TAMP/Backup registers using HAL_RTCEx_PrivilegeModeSet()
+         function.
+      +) Get the privilege level of the RTC/TAMP/Backup registers using HAL_RTCEx_PrivilegeModeGet()
+         function.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RTCEx
+  * @brief RTC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TAMP_ALL RTC_TAMPER_ALL
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RTCEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
+  *  @brief   RTC TimeStamp and Tamper functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set TimeStamp.
+  * @note   This API must be called before enabling the TimeStamp feature.
+  * @param  hrtc RTC handle
+  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
+  *         activated.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+  *                                        rising edge of the related pin.
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+  *                                         falling edge of the related pin.
+  * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+  *               The RTC TimeStamp Pin is per default PC13, but for reasons of
+  *               compatibility, this parameter is required.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+  /* Check the parameters */
+  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+  UNUSED(RTC_TimeStampPin);
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set TimeStamp with Interrupt.
+  * @note   This API must be called before enabling the TimeStamp feature.
+  * @note   The application must ensure that the EXTI RTC interrupt line is enabled.
+  * @param  hrtc RTC handle
+  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
+  *         activated.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+  *                                        rising edge of the related pin.
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+  *                                         falling edge of the related pin.
+  * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+  *               The RTC TimeStamp Pin is per default PC13, but for reasons of
+  *               compatibility, this parameter is required.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+  /* Check the parameters */
+  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+  UNUSED(RTC_TimeStampPin);
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
+
+  /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */
+  SET_BIT(RTC->CR, (uint32_t)TimeStampEdge);
+
+  /* Enable timestamp and IT */
+  SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate TimeStamp.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* In case of interrupt mode is used, the interrupt source must disabled */
+  CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Internal TimeStamp.
+  * @note   This API must be called before enabling the internal TimeStamp feature.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Configure the internal Time Stamp Enable bits */
+  SET_BIT(RTC->CR, RTC_CR_ITSE);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate Internal TimeStamp.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Configure the internal Time Stamp Enable bits */
+  CLEAR_BIT(RTC->CR, RTC_CR_ITSE);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RTC TimeStamp value.
+  * @param  hrtc RTC handle
+  * @param  sTimeStamp Pointer to Time structure
+  * @param  sTimeStampDate Pointer to Date structure
+  * @param  Format specifies the format of the entered parameters.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_FORMAT_BIN: Binary data format
+  *             @arg RTC_FORMAT_BCD: BCD data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
+                                         RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
+{
+  uint32_t tmptime;
+  uint32_t tmpdate;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = READ_BIT(RTC->TSTR, RTC_TR_RESERVED_MASK);
+  tmpdate = READ_BIT(RTC->TSDR, RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos);
+  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos);
+  sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos);
+  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos);
+  sTimeStamp->SubSeconds = READ_BIT(RTC->TSSSR, RTC_TSSSR_SS);
+
+  /* Fill the Date structure fields with the read parameters */
+  sTimeStampDate->Year = 0U;
+  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos);
+  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU));
+  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos);
+
+  /* Check the input parameters format */
+  if (Format == RTC_FORMAT_BIN)
+  {
+    /* Convert the TimeStamp structure parameters to Binary format */
+    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+    /* Convert the DateTimeStamp structure parameters to Binary format */
+    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+  }
+
+  /* Check if TIMESTAMP flag is set */
+  if (READ_BIT(RTC->SR, RTC_SR_TSF) != 0U)
+  {
+    /* Clear the TIMESTAMP Flags */
+    WRITE_REG(RTC->SCR, (RTC_SCR_CITSF | RTC_SCR_CTSF));
+
+    /* Check if TIMESTAMP OverRun flag is set */
+    if (READ_BIT(RTC->SR, RTC_SR_TSOVF) != 0U)
+    {
+      /* Clear the TIMESTAMP OverRun Flag */
+      WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF);
+
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle TimeStamp interrupt request.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Get the pending status of the TimeStamp Interrupt */
+#if defined (CPU_IN_SECURE_STATE)
+  if (READ_BIT(RTC->SMISR, RTC_SMISR_TSMF) != 0U)
+#else
+  if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U)
+#endif /* defined (CPU_IN_SECURE_STATE) */
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call TimeStampEvent registered Callback */
+    hrtc->TimeStampEventCallback(hrtc);
+#else
+    HAL_RTCEx_TimeStampEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+    /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when
+       TSF bit is reset.*/
+    WRITE_REG(RTC->SCR, RTC_SCR_CITSF | RTC_SCR_CTSF);
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+  * @brief  TimeStamp callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Handle TimeStamp polling request.
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  uint32_t tickstart = HAL_GetTick();
+
+  while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U)
+        {
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTCEx_Exported_Functions_Group2
+  * @brief    RTC Wake-up functions
+  *
+@verbatim
+ ===============================================================================
+                        ##### RTC Wake-up functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Wake-up feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set wake up timer.
+  * @param  hrtc RTC handle
+  * @param  WakeUpCounter Wake up counter
+  * @param  WakeUpClock Wake up clock
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Clear WUTE in RTC_CR to disable the wakeup timer */
+  CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
+
+  /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
+     counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+     calendar initialization mode. */
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+  {
+    tickstart = HAL_GetTick();
+
+    while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+        {
+          /* Change RTC state */
+          hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hrtc);
+
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  /* Configure the clock source */
+  MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
+
+  /* Configure the Wakeup Timer counter */
+  WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter);
+
+  /* Enable the Wakeup Timer */
+  SET_BIT(RTC->CR, RTC_CR_WUTE);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set wake up timer with interrupt.
+  * @note   The application must ensure that the EXTI RTC interrupt line is enabled.
+  * @param  hrtc RTC handle
+  * @param  WakeUpCounter Wake up counter
+  * @param  WakeUpClock Wake up clock
+  * @param  WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual)
+  *                       - No effect if WakeUpAutoClr is set to zero
+  *                       - This feature is meaningful in case of Low power mode to avoid any RTC software execution
+  *                         after Wake Up.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock,
+                                              uint32_t WakeUpAutoClr)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+  /* (0x0000<=WUTOCLR<=WUT) */
+  assert_param(WakeUpAutoClr <= WakeUpCounter);
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Clear WUTE in RTC_CR to disable the wakeup timer */
+  CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
+
+  /* Clear flag Wake-Up */
+  WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
+
+  /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
+     counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+     calendar initialization mode. */
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+  {
+    tickstart = HAL_GetTick();
+    while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+    {
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
+        {
+          /* Change RTC state */
+          hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hrtc);
+
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  /* Configure the Wakeup Timer counter and auto clear value */
+  WRITE_REG(RTC->WUTR, (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos)));
+
+  /* Configure the clock source */
+  MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
+
+  /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/
+  SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE));
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate wake up timer counter.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the Wakeup Timer */
+  /* In case of interrupt mode is used, the interrupt source must disabled */
+  CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE));
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get wake up timer counter.
+  * @param  hrtc RTC handle
+  * @retval Counter value
+  */
+uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Get the counter value */
+  return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+  * @brief  Handle Wake Up Timer interrupt request.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Get the pending status of the Wake-Up Timer Interrupt */
+#if defined (CPU_IN_SECURE_STATE)
+  if (READ_BIT(RTC->SMISR, RTC_SMISR_WUTMF) != 0U)
+#else
+  if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U)
+#endif /* defined (CPU_IN_SECURE_STATE) */
+  {
+    /* Immediately clear flags */
+    WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call wake up timer registered Callback */
+    hrtc->WakeUpTimerEventCallback(hrtc);
+#else
+    HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+  * @brief  Wake Up Timer callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Handle Wake Up Timer Polling.
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  uint32_t tickstart = HAL_GetTick();
+
+  while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U)
+        {
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  /* Clear the WAKEUPTIMER Flag */
+  WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTCEx_Exported_Functions_Group3
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Extended Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Write a data in a specified RTC Backup data register
+      (+) Read a data in a specified RTC Backup data register
+      (+) Set the Coarse calibration parameters.
+      (+) Deactivate the Coarse calibration parameters
+      (+) Set the Smooth calibration parameters.
+      (+) Set Low Power calibration parameter.
+      (+) Configure the Synchronization Shift Control Settings.
+      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+      (+) Enable the RTC reference clock detection.
+      (+) Disable the RTC reference clock detection.
+      (+) Enable the Bypass Shadow feature.
+      (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the Smooth calibration parameters.
+  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+  *         SmoothCalibMinusPulsesValue must be equal to 0.
+  * @param  hrtc RTC handle
+  * @param  SmoothCalibPeriod  Select the Smooth Calibration Period.
+  *          This parameter can be one of the following values :
+  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+  * @param  SmoothCalibPlusPulses  Select to Set or reset the CALP bit.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+  * @param  SmoothCalibMinusPulsesValue  Select the value of CALM[8:0] bits.
+  *          This parameter can be one any value from 0 to 0x000001FF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
+                                           uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  tickstart = HAL_GetTick();
+
+  /* check if a calibration is pending */
+  while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
+      {
+
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+      else
+      {
+        break;
+      }
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the Smooth calibration settings */
+  MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM),
+             (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue));
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the low power Calibration mode.
+  * @param  hrtc: RTC handle
+  * @param  LowPowerCalib: Low power Calibration mode.
+  *          This parameter can be one of the following values :
+  *             @arg RTC_LPCAL_SET: Low power mode.
+  *             @arg RTC_LPCAL_RESET: High consumption mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_LOW_POWER_CALIB(LowPowerCalib));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Configure the Smooth calibration settings */
+  MODIFY_REG(RTC->CALR, RTC_CALR_LPCAL, LowPowerCalib);
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register.
+  * @param  hrtc RTC handle
+  * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.
+  *          This parameter can be one of the following values:
+  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+  *             @arg RTC_SHIFTADD1S_RESET: No effect.
+  * @param  ShiftSubFS Select the number of Second Fractions to substitute.
+  *          This parameter can be one any value from 0 to 0x7FFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  tickstart = HAL_GetTick();
+
+  /* Wait until the shift is completed */
+  while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U)
+      {
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_TIMEOUT;
+      }
+      else
+      {
+        break;
+      }
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Check if the reference clock detection is disabled */
+  if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U)
+  {
+    /* Configure the Shift settings */
+    MODIFY_REG(RTC->SHIFTR, RTC_SHIFTR_SUBFS, (uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S));
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
+    {
+      if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  else
+  {
+    /* Enable the write protection for RTC registers */
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+    /* Change RTC state */
+    hrtc->State = HAL_RTC_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrtc);
+
+    return HAL_ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  hrtc RTC handle
+  * @param  CalibOutput Select the Calibration output Selection .
+  *          This parameter can be one of the following values:
+  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Configure the RTC_CR register */
+  MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput);
+
+  /* Enable calibration output */
+  SET_BIT(RTC->CR, RTC_CR_COE);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable calibration output */
+  CLEAR_BIT(RTC->CR, RTC_CR_COE);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the RTC reference clock detection.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
+{
+  HAL_StatusTypeDef status;
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Enter Initialization mode */
+  status = RTC_EnterInitMode(hrtc);
+  if (status == HAL_OK)
+  {
+    /* Enable clockref detection */
+    SET_BIT(RTC->CR, RTC_CR_REFCKON);
+
+    /* Exit Initialization mode */
+    status = RTC_ExitInitMode(hrtc);
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  if (status == HAL_OK)
+  {
+    /* Change RTC state */
+    hrtc->State = HAL_RTC_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return status;
+}
+
+/**
+  * @brief  Disable the RTC reference clock detection.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
+{
+  HAL_StatusTypeDef status;
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+  /* Enter Initialization mode */
+  status = RTC_EnterInitMode(hrtc);
+  if (status == HAL_OK)
+  {
+    /* Disable clockref detection */
+    CLEAR_BIT(RTC->CR, RTC_CR_REFCKON);
+
+    /* Exit Initialization mode */
+    status = RTC_ExitInitMode(hrtc);
+  }
+
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  if (status == HAL_OK)
+  {
+    /* Change RTC state */
+    hrtc->State = HAL_RTC_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return status;
+}
+
+/**
+  * @brief  Enable the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken
+  *         directly from the Calendar counter.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Set the BYPSHAD bit */
+  SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken
+  *         directly from the Calendar counter.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Reset the BYPSHAD bit */
+  CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Increment Monotonic counter.
+  * @param  hrtc RTC handle
+  * @param  Instance  Monotonic counter Instance
+  *         This parameter can be one of the following values :
+  *           @arg RTC_MONOTONIC_COUNTER_1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(const RTC_HandleTypeDef *hrtc, uint32_t Instance)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  UNUSED(Instance);
+
+  /* This register is read-only only and is incremented by one when a write access is done to this
+     register. This register cannot roll-over and is frozen when reaching the maximum value. */
+  CLEAR_REG(TAMP->COUNT1R);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Monotonic counter.
+  * @param  hrtc RTC handle
+  * @param  Instance  Monotonic counter Instance
+  *         This parameter can be one of the following values :
+  *           @arg RTC_MONOTONIC_COUNTER_1
+  * @param  pValue Pointer to the counter monotonic counter value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *pValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+  UNUSED(Instance);
+
+  /* This register is read-only only and is incremented by one when a write access is done to this
+     register. This register cannot roll-over and is frozen when reaching the maximum value. */
+  *pValue = READ_REG(TAMP->COUNT1R);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set SSR Underflow detection with Interrupt.
+  * @note   The application must ensure that the EXTI RTC interrupt line is enabled.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* Enable IT SSRU */
+  __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate SSR Underflow.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  /* In case of interrupt mode is used, the interrupt source must disabled */
+  __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU);
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SSR underflow interrupt request.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Get the pending status of the SSR Underflow Interrupt */
+#if defined (CPU_IN_SECURE_STATE)
+  if (READ_BIT(RTC->SMISR, RTC_SMISR_SSRUMF) != 0U)
+#else
+  if (READ_BIT(RTC->MISR, RTC_MISR_SSRUMF) != 0U)
+#endif /* defined (CPU_IN_SECURE_STATE) */
+  {
+    /* Immediately clear SSR underflow flag */
+    WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF);
+
+    /* SSRU callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call SSRUEvent registered Callback */
+    hrtc->SSRUEventCallback(hrtc);
+#else
+    HAL_RTCEx_SSRUEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+  }
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+  * @brief  SSR underflow callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_SSRUEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTCEx_Exported_Functions_Group4
+  * @brief    Extended features functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) RTC Alarm B callback
+      (+) RTC Poll for Alarm B request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Alarm B callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Handle Alarm B Polling request.
+  * @param  hrtc RTC handle
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  uint32_t tickstart = HAL_GetTick();
+
+  while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U)
+        {
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  /* Clear the Alarm Flag */
+  WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTCEx_Exported_Functions_Group5
+  * @brief      Extended RTC Tamper functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### Tamper functions #####
+  ==============================================================================
+  [..]
+   (+) Before calling any tamper or internal tamper function, you have to call first
+       HAL_RTC_Init() function.
+   (+) In that one you can select to output tamper event on RTC pin.
+  [..]
+   (+) Enable the Tamper and configure the Tamper filter count, trigger Edge
+       or Level according to the Tamper filter (if equal to 0 Edge else Level)
+       value, sampling frequency, NoErase, MaskFlag, precharge or discharge and
+       Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function.
+       You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function.
+   (+) The default configuration of the Tamper erases the backup registers. To avoid
+       erase, enable the NoErase field on the TAMP_TAMPCR register.
+  [..]
+   (+) Enable Internal Tamper and configure it with interrupt, timestamp using
+       the HAL_RTCEx_SetInternalTamper() function.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Set Tamper
+  * @param  hrtc RTC handle
+  * @param  sTamper Pointer to Tamper Structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper)
+{
+  uint32_t tmpreg;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
+  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
+  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+  /* Mask flag only supported by TAMPER 1, 2 and 3 */
+  assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_3)));
+  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+  /* Trigger and Filter have exclusive configurations */
+  assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) &&
+                ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) ||
+                 (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) ||
+               ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) &&
+                ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) ||
+                 (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))));
+
+  /* Configuration register 2 */
+  tmpreg = READ_REG(TAMP->CR2);
+  tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) |
+              (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos));
+
+  if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
+  {
+    tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
+  }
+
+  if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
+  {
+    tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos);
+  }
+
+  if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+  {
+    tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos);
+  }
+  WRITE_REG(TAMP->CR2, tmpreg);
+
+  /* Filter control register */
+  WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration |
+            sTamper->TamperPullUp);
+
+  /* Timestamp on tamper */
+  if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
+  {
+    MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
+  }
+
+  /* Control register 1 */
+  SET_BIT(TAMP->CR1, sTamper->Tamper);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Set Tamper in IT mode
+  * @note   The application must ensure that the EXTI TAMP interrupt line is enabled.
+  * @param  hrtc RTC handle
+  * @param  sTamper Pointer to Tamper Structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper)
+{
+  uint32_t tmpreg;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
+  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+  /* The interrupt must not be enabled when TAMPxMSK is set. */
+  assert_param(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_DISABLE);
+  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+  /* Trigger and Filter have exclusive configurations */
+  assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) &&
+                ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) ||
+                 (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) ||
+               ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) &&
+                ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) ||
+                 (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))));
+
+  /* Configuration register 2 */
+  tmpreg = READ_REG(TAMP->CR2);
+  tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) |
+              (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos));
+
+  if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
+  {
+    tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
+  }
+
+  if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+  {
+    tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos);
+  }
+  WRITE_REG(TAMP->CR2, tmpreg);
+
+  /* Filter control register */
+  WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration |
+            sTamper->TamperPullUp);
+
+  /* Timestamp on tamper */
+  if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
+  {
+    MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
+  }
+
+  /* Interrupt enable register */
+  SET_BIT(TAMP->IER, sTamper->Tamper);
+
+  /* Control register 1 */
+  SET_BIT(TAMP->CR1, sTamper->Tamper);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate Tamper.
+  * @param  hrtc RTC handle
+  * @param  Tamper Selected tamper pin.
+  *         This parameter can be a combination of the following values:
+  *         @arg RTC_TAMPER_1
+  *         @arg RTC_TAMPER_2
+  *         @arg RTC_TAMPER_3
+  *         @arg RTC_TAMPER_4
+  *         @arg RTC_TAMPER_5
+  *         @arg RTC_TAMPER_6
+  *         @arg RTC_TAMPER_7
+  *         @arg RTC_TAMPER_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(const RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  assert_param(IS_RTC_TAMPER(Tamper));
+
+  /* Disable the selected Tamper pin */
+  CLEAR_BIT(TAMP->CR1, Tamper);
+
+  /* Clear tamper interrupt and event flags (WO register) */
+  WRITE_REG(TAMP->SCR, Tamper);
+
+  /* Clear tamper mask/noerase/trigger configuration */
+  CLEAR_BIT(TAMP->CR2, (Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | \
+            (Tamper << TAMP_CR2_TAMP1POM_Pos));
+
+  /* Clear tamper interrupt mode configuration */
+  CLEAR_BIT(TAMP->IER, Tamper);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set all active Tampers at the same time.
+  * @note   For interrupt mode, the application must ensure that the EXTI TAMP interrupt line is enabled.
+  * @param  hrtc RTC handle
+  * @param  sAllTamper Pointer to active Tamper Structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper)
+{
+  uint32_t tmp_ier;
+  uint32_t tmp_cr1;
+  uint32_t tmp_cr2;
+  uint32_t tmp_atcr1;
+  uint32_t tmp_atcr2;
+  uint32_t tmp_cr;
+  uint32_t i;
+  uint32_t tickstart;
+
+#ifdef  USE_FULL_ASSERT
+  for (i = 0; i < RTC_TAMP_NB; i++)
+  {
+    assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase));
+    assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag));
+    /* Mask flag only supported by TAMPER 1, 2 and 3 */
+    assert_param(!((sAllTamper->TampInput[i].MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE) &&
+                   (i >= RTC_TAMPER_MASKABLE_NB)));
+  }
+  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection));
+  assert_param(IS_RTC_ATAMPER_FILTER(sAllTamper->ActiveFilter));
+  assert_param(IS_RTC_ATAMPER_OUTPUT_CHANGE_PERIOD(sAllTamper->ActiveOutputChangePeriod));
+  assert_param(IS_RTC_ATAMPER_ASYNCPRES_RTCCLK(sAllTamper->ActiveAsyncPrescaler));
+#endif /* USE_FULL_ASSERT */
+
+  /* Active Tampers must not be already enabled */
+  if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U)
+  {
+    /* Disable all actives tampers with HAL_RTCEx_DeactivateActiveTampers.
+       No need to check return value because it returns always HAL_OK */
+    (void) HAL_RTCEx_DeactivateActiveTampers(hrtc);
+  }
+
+  /* Set TimeStamp on tamper detection */
+  tmp_cr = READ_REG(RTC->CR);
+  if ((tmp_cr & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection))
+  {
+    MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection);
+  }
+
+  tmp_cr1 = READ_REG(TAMP->CR1);
+  tmp_cr2 = READ_REG(TAMP->CR2);
+  tmp_atcr2 = 0U;
+  tmp_ier = READ_REG(TAMP->IER);
+
+  /* Set common parameters */
+  tmp_atcr1 = (sAllTamper->ActiveFilter | (sAllTamper->ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos) |
+               sAllTamper->ActiveAsyncPrescaler);
+
+  /* Set specific parameters for each active tamper inputs if enable */
+  for (i = 0; i < RTC_TAMP_NB; i++)
+  {
+    if (sAllTamper->TampInput[i].Enable != RTC_ATAMP_DISABLE)
+    {
+      tmp_cr1 |= (TAMP_CR1_TAMP1E << i);
+      tmp_atcr1 |= (TAMP_ATCR1_TAMP1AM << i);
+
+      if (sAllTamper->TampInput[i].Interrupt != RTC_ATAMP_INTERRUPT_DISABLE)
+      {
+        /* Interrupt enable register */
+        tmp_ier |= (TAMP_IER_TAMP1IE << i);
+      }
+
+      if (sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
+      {
+        tmp_cr2 |= (TAMP_CR2_TAMP1MSK << i);
+      }
+
+      if (sAllTamper->TampInput[i].NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+      {
+        tmp_cr2 |= (TAMP_CR2_TAMP1POM << i);
+      }
+
+      /* Configure ATOSELx[] in case of output sharing */
+      tmp_atcr2 |= sAllTamper->TampInput[i].Output << ((3U * i) + TAMP_ATCR2_ATOSEL1_Pos);
+
+      if (i != sAllTamper->TampInput[i].Output)
+      {
+        tmp_atcr1 |= TAMP_ATCR1_ATOSHARE;
+      }
+    }
+  }
+
+  WRITE_REG(TAMP->IER, tmp_ier);
+  WRITE_REG(TAMP->ATCR1, tmp_atcr1);
+  WRITE_REG(TAMP->ATCR2, tmp_atcr2);
+  WRITE_REG(TAMP->CR2, tmp_cr2);
+  WRITE_REG(TAMP->CR1, tmp_cr1);
+
+  /* Write seed */
+  for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++)
+  {
+    WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]);
+  }
+
+  /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */
+  tickstart = HAL_GetTick();
+  while (READ_BIT(TAMP->ATOR,  TAMP_ATOR_SEEDF) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U)
+      {
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        return HAL_TIMEOUT;
+      }
+      else
+      {
+        break;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write a new seed. Active tamper must be enabled.
+  * @param  hrtc RTC handle
+  * @param  pSeed Pointer to active tamper seed values.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed)
+{
+  uint32_t i;
+  uint32_t tickstart;
+
+  /* Active Tampers must be enabled */
+  if (READ_BIT(TAMP->ATOR,  TAMP_ATOR_INITS) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++)
+  {
+    WRITE_REG(TAMP->ATSEEDR, pSeed[i]);
+  }
+
+  /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */
+  tickstart = HAL_GetTick();
+  while (READ_BIT(TAMP->ATOR,  TAMP_ATOR_SEEDF) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+    {
+      /* New check to avoid false timeout detection in case of preemption */
+      if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U)
+      {
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        return HAL_TIMEOUT;
+      }
+      else
+      {
+        break;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+#if defined(TAMP_SECCFGR_BHKLOCK)
+/**
+  * @brief  Lock the Boot hardware Key
+  * @param  hrtc RTC handle
+  * @note   The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in
+  *         read nor in write (they are read as 0 and write ignore).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_LockBootHardwareKey(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK);
+
+  return HAL_OK;
+}
+#endif /* TAMP_SECCFGR_BHKLOCK */
+
+/**
+  * @brief  Deactivate all Active Tampers at the same time.
+  * @param  hrtc RTC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Get Active tampers */
+  uint32_t atamp_mask = READ_BIT(TAMP->ATCR1, TAMP_ALL);
+
+  /* Disable all actives tampers but not passives tampers */
+  CLEAR_BIT(TAMP->CR1, atamp_mask);
+
+  /* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */
+  WRITE_REG(TAMP->SCR, atamp_mask);
+
+  /* Disable no erase and mask */
+  CLEAR_BIT(TAMP->CR2, (atamp_mask | ((atamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) <<
+                                      TAMP_CR2_TAMP1MSK_Pos)));
+
+  /* Clear all active tampers interrupt mode configuration but not passives tampers */
+  CLEAR_BIT(TAMP->IER, atamp_mask);
+
+  /* Set reset value for active tamper control register 1 */
+  WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL_0 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_2);
+
+  /* Set reset value for active tamper control register 2 */
+  CLEAR_REG(TAMP->ATCR2);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Tamper event polling.
+  * @param  hrtc RTC handle
+  * @param  Tamper Selected tamper pin.
+  *         This parameter can be a combination of the following values:
+  *         @arg RTC_TAMPER_1
+  *         @arg RTC_TAMPER_2
+  *         @arg RTC_TAMPER_3
+  *         @arg RTC_TAMPER_4
+  *         @arg RTC_TAMPER_5
+  *         @arg RTC_TAMPER_6
+  *         @arg RTC_TAMPER_7
+  *         @arg RTC_TAMPER_8
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  assert_param(IS_RTC_TAMPER(Tamper));
+
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Get the status of the Interrupt */
+  while (READ_BIT(TAMP->SR, Tamper) != Tamper)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(TAMP->SR, Tamper) != Tamper)
+        {
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  /* Clear the Tamper Flag */
+  WRITE_REG(TAMP->SCR, Tamper);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Set Internal Tamper
+  * @param  hrtc RTC handle
+  * @param  sIntTamper Pointer to Internal Tamper Structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc,
+                                              const RTC_InternalTamperTypeDef *sIntTamper)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
+  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
+  assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase));
+
+  /* Timestamp enable on internal tamper */
+  if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
+  {
+    MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
+  }
+
+  /* No Erase Backup register enable for Internal Tamper */
+  if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+  {
+    SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos)));
+  }
+  else
+  {
+    CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos)));
+  }
+
+  /* Enable Vcore monitoring for internal tamper 7 */
+  if ((sIntTamper->IntTamper & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
+  {
+    SET_BIT(TAMP->OR, TAMP_OR_VCOREMEN);
+  }
+
+  /* Enable Internal Tamper */
+  SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Set Internal Tamper in interrupt mode
+  * @note   The application must ensure that the EXTI TAMP interrupt line is enabled.
+  * @param  hrtc RTC handle
+  * @param  sIntTamper Pointer to Internal Tamper Structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc,
+                                                 const RTC_InternalTamperTypeDef *sIntTamper)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper));
+  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection));
+  assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase));
+
+  /* Timestamp enable on internal tamper */
+  if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
+  {
+    MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
+  }
+
+  /* Interrupt enable register */
+  SET_BIT(TAMP->IER, sIntTamper->IntTamper);
+
+  /* No Erase Backup register enable for Internal Tamper */
+  if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
+  {
+    SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos)));
+  }
+  else
+  {
+    CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP1E_Pos - TAMP_CR3_ITAMP1POM_Pos)));
+  }
+
+  /* Enable Vcore monitoring for internal tamper 7 */
+  if ((sIntTamper->IntTamper & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
+  {
+    SET_BIT(TAMP->OR, TAMP_OR_VCOREMEN);
+  }
+
+  /* Enable Internal Tamper */
+  SET_BIT(TAMP->CR1, sIntTamper->IntTamper);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate Internal Tamper.
+  * @param  hrtc RTC handle
+  * @param  IntTamper Selected internal tamper event.
+  *          This parameter can be any combination of existing internal tampers.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
+
+  /* Disable the selected Tamper pin */
+  CLEAR_BIT(TAMP->CR1, IntTamper);
+
+  /* Clear internal tamper interrupt mode configuration */
+  CLEAR_BIT(TAMP->IER, IntTamper);
+
+  /* Clear internal tamper interrupt */
+  WRITE_REG(TAMP->SCR, IntTamper);
+
+  /* Disable Vcore monitoring for internal tamper 7 */
+  if ((IntTamper & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
+  {
+    CLEAR_BIT(TAMP->OR, TAMP_OR_VCOREMEN);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Internal Tamper event polling.
+  * @param  hrtc RTC handle
+  * @param  IntTamper selected tamper.
+  *          This parameter can be any combination of existing internal tampers.
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper,
+                                                       uint32_t Timeout)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper));
+
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Get the status of the Interrupt */
+  while (READ_BIT(TAMP->SR, IntTamper) != IntTamper)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (READ_BIT(TAMP->SR, IntTamper) != IntTamper)
+        {
+          return HAL_TIMEOUT;
+        }
+        else
+        {
+          break;
+        }
+      }
+    }
+  }
+
+  /* Clear the Tamper Flag */
+  WRITE_REG(TAMP->SCR, IntTamper);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle Tamper interrupt request.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Get the pending status of the Tampers Interrupt */
+#if defined (CPU_IN_SECURE_STATE)
+  uint32_t tmp = READ_REG(TAMP->SMISR);
+#else
+  uint32_t tmp = READ_REG(TAMP->MISR);
+#endif /* defined (CPU_IN_SECURE_STATE) */
+
+  /* Check Tamper1 status */
+  if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Tamper 1 Event registered secure Callback */
+    hrtc->Tamper1EventCallback(hrtc);
+#else
+    /* Tamper1 secure callback */
+    HAL_RTCEx_Tamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Tamper2 status */
+  if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Tamper 2 Event registered secure Callback */
+    hrtc->Tamper2EventCallback(hrtc);
+#else
+    /* Tamper2 secure callback */
+    HAL_RTCEx_Tamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Tamper3 status */
+  if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Tamper 3 Event registered secure Callback */
+    hrtc->Tamper3EventCallback(hrtc);
+#else
+    /* Tamper3 secure callback */
+    HAL_RTCEx_Tamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Tamper4 status */
+  if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Tamper 4 Event registered secure Callback */
+    hrtc->Tamper4EventCallback(hrtc);
+#else
+    /* Tamper4 secure callback */
+    HAL_RTCEx_Tamper4EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Tamper5 status */
+  if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Tamper 5 Event registered secure Callback */
+    hrtc->Tamper5EventCallback(hrtc);
+#else
+    /* Tamper5 secure callback */
+    HAL_RTCEx_Tamper5EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Tamper6 status */
+  if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Tamper 6 Event registered secure Callback */
+    hrtc->Tamper6EventCallback(hrtc);
+#else
+    /* Tamper6 secure callback */
+    HAL_RTCEx_Tamper6EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Tamper7 status */
+  if ((tmp & RTC_TAMPER_7) == RTC_TAMPER_7)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Tamper 7 Event registered secure Callback */
+    hrtc->Tamper7EventCallback(hrtc);
+#else
+    /* Tamper7 secure callback */
+    HAL_RTCEx_Tamper7EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper1 status */
+  if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 1 Event registered secure Callback */
+    hrtc->InternalTamper1EventCallback(hrtc);
+#else
+    /* Internal Tamper1 secure callback */
+    HAL_RTCEx_InternalTamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper2 status */
+  if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 2 Event registered secure Callback */
+    hrtc->InternalTamper2EventCallback(hrtc);
+#else
+    /* Internal Tamper2 secure callback */
+    HAL_RTCEx_InternalTamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper3 status */
+  if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 3 Event registered secure Callback */
+    hrtc->InternalTamper3EventCallback(hrtc);
+#else
+    /* Internal Tamper3 secure callback */
+    HAL_RTCEx_InternalTamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper4 status */
+  if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 4 Event registered secure Callback */
+    hrtc->InternalTamper4EventCallback(hrtc);
+#else
+    /* Internal Tamper4 secure callback */
+    HAL_RTCEx_InternalTamper4EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper5 status */
+  if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 5 Event registered secure Callback */
+    hrtc->InternalTamper5EventCallback(hrtc);
+#else
+    /* Internal Tamper5 secure callback */
+    HAL_RTCEx_InternalTamper5EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper6 status */
+  if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 6 Event registered secure Callback */
+    hrtc->InternalTamper6EventCallback(hrtc);
+#else
+    /* Internal Tamper6 secure callback */
+    HAL_RTCEx_InternalTamper6EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper7 status */
+  if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 7 Event registered secure Callback */
+    hrtc->InternalTamper7EventCallback(hrtc);
+#else
+    /* Internal Tamper7 secure callback */
+    HAL_RTCEx_InternalTamper7EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper8 status */
+  if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 8 Event registered secure Callback */
+    hrtc->InternalTamper8EventCallback(hrtc);
+#else
+    /* Internal Tamper8 secure callback */
+    HAL_RTCEx_InternalTamper8EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper9 status */
+  if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 9 Event registered secure Callback */
+    hrtc->InternalTamper9EventCallback(hrtc);
+#else
+    /* Internal Tamper9 secure callback */
+    HAL_RTCEx_InternalTamper9EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Check Internal Tamper11 status */
+  if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11)
+  {
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+    /* Call Internal Tamper 11 Event registered secure Callback */
+    hrtc->InternalTamper11EventCallback(hrtc);
+#else
+    /* Internal Tamper11 secure callback */
+    HAL_RTCEx_InternalTamper11EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+  }
+
+  /* Clear flags after treatment to allow the potential tamper feature */
+  WRITE_REG(TAMP->SCR, tmp);
+}
+
+/**
+  * @brief  Tamper 1 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 2 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 3 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 4 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper4EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 5 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper5EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 6 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper6EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 7 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper7EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper7EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tamper 8 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_Tamper8EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_Tamper8EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 1 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper1EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 2 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper2EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 3 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 4 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper4EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 5 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 6 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 7 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper7EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 8 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 9 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper9EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Internal Tamper 11 callback.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+__weak void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RTCEx_InternalTamper11EventCallback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group6
+  * @brief      Extended RTC Backup register functions
+  *
+@verbatim
+  ===============================================================================
+             ##### Extended RTC Backup register functions #####
+  ===============================================================================
+  [..]
+   (+) Before calling any tamper or internal tamper function, you have to call first
+       HAL_RTC_Init() function.
+   (+) In that one you can select to output tamper event on RTC pin.
+  [..]
+   This subsection provides functions allowing to
+   (+) Write a data in a specified RTC Backup data register
+   (+) Read a data in a specified RTC Backup data register
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Write a data in a specified RTC Backup data register.
+  * @param  hrtc RTC handle
+  * @param  BackupRegister RTC Backup data Register number.
+  *          This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB
+  * @param  Data Data to be written in the specified Backup data register.
+  * @retval None
+  */
+void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+  uint32_t tmp;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(BackupRegister));
+
+  /* Determine address of the specified Backup register */
+  tmp = (uint32_t)(&(TAMP->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Write data in the specified register Backup register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @param  hrtc RTC handle
+  * @param  BackupRegister RTC Backup data Register number.
+  *          This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB
+  * @retval Read value
+  */
+uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+  uint32_t tmp;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(BackupRegister));
+
+  /* Determine address of the specified Backup register */
+  tmp = (uint32_t)(&(TAMP->BKP0R));
+  tmp += (BackupRegister * 4U);
+
+  /* Read the data from the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @brief  Reset the RTC Backup data Registers and the device secrets.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void  HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  SET_BIT(TAMP->CR2, TAMP_CR2_BKERASE);
+}
+
+/**
+  * @brief  Block the access to the RTC Backup data Register and all the device secrets.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void  HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  WRITE_REG(TAMP->CR2, TAMP_CR2_BKBLOCK);
+}
+
+/**
+  * @brief  Disable the Block to the access to the RTC Backup data Register and the device secrets.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+void  HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  CLEAR_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK);
+}
+
+/**
+  * @brief  Enable and Disable the erase of the configurable Device Secrets
+  * @note   This API must be called before enabling the Tamper.
+  * @param  hrtc RTC handle
+  * @param  DeviceSecretConf Specifies the configuration of the Device Secrets
+  *         This parameter can be a combination of the following values:
+  *         @arg TAMP_DEVICESECRETS_ERASE_NONE
+  *         @arg TAMP_DEVICESECRETS_ERASE_BKPSRAM
+  *
+  * @retval None
+  */
+void  HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  MODIFY_REG(TAMP->RPCFGR, TAMP_RPCFGR_RPCFG0, DeviceSecretConf);
+}
+/**
+  * @}
+  */
+
+/** @addtogroup RTCEx_Exported_Functions_Group7
+  * @brief      Extended RTC security functions
+  *
+@verbatim
+  ===============================================================================
+             ##### Extended RTC security functions #####
+  ===============================================================================
+  [..]
+   (+) Before calling security function, you have to call first
+       HAL_RTC_Init() function.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the security level of the RTC/TAMP/Backup registers.
+  *         To set the secure level please call HAL_RTCEx_SecureModeSet.
+  * @param  hrtc RTC handle
+  * @param  secureState  Secure state
+  * @retval HAL_StatusTypeDef
+  */
+HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(const RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef  *secureState)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Read registers */
+  uint32_t rtc_seccfgr = READ_REG(RTC->SECCFGR);
+  uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR);
+
+  /* RTC */
+  secureState->rtcSecureFull = READ_BIT(rtc_seccfgr, RTC_SECCFGR_SEC);
+
+  /* Warning, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */
+  secureState->rtcNonSecureFeatures = ~(READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_ALL)) & RTC_NONSECURE_FEATURE_ALL;
+
+  /* TAMP */
+  secureState->tampSecureFull = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_TAMPSEC);
+
+  /* Monotonic Counter */
+  secureState->MonotonicCounterSecure = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_CNT1SEC);
+
+  /* Backup register start zones
+     Warning : Backup register start zones are shared with privilege configuration */
+  secureState->backupRegisterStartZone2 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPRWSEC) >> TAMP_SECCFGR_BKPRWSEC_Pos;
+  secureState->backupRegisterStartZone3 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPWSEC) >> TAMP_SECCFGR_BKPWSEC_Pos;
+
+  return HAL_OK;
+}
+
+
+#if defined (CPU_IN_SECURE_STATE)
+/**
+  * @brief  Set the security level of the RTC/TAMP/Backup registers.
+  *         To get the current security level call HAL_RTCEx_SecureModeGet.
+  * @param  hrtc RTC handle
+  * @param  secureState  Secure state
+  * @retval HAL_StatusTypeDef
+  */
+HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(const RTC_HandleTypeDef *hrtc, const RTC_SecureStateTypeDef  *secureState)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull));
+  assert_param(IS_RTC_NONSECURE_FEATURES(secureState->rtcNonSecureFeatures));
+  assert_param(IS_TAMP_SECURE_FULL(secureState->tampSecureFull));
+  assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone2));
+  assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone3));
+  assert_param(IS_TAMP_MONOTONIC_CNT_SECURE(secureState->MonotonicCounterSecure));
+
+  /* RTC, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */
+  WRITE_REG(RTC->SECCFGR, secureState->rtcSecureFull | (~(secureState->rtcNonSecureFeatures) &
+                                                        RTC_NONSECURE_FEATURE_ALL));
+
+  /* Tamper + Backup register + Monotonic counter
+     Warning : Backup register start zone are Shared with privilege configuration */
+  WRITE_REG(TAMP->SECCFGR,
+            secureState->tampSecureFull | secureState->MonotonicCounterSecure |
+            (TAMP_SECCFGR_BKPRWSEC & (secureState->backupRegisterStartZone2 << TAMP_SECCFGR_BKPRWSEC_Pos)) |
+            (TAMP_SECCFGR_BKPWSEC & (secureState->backupRegisterStartZone3 << TAMP_SECCFGR_BKPWSEC_Pos)));
+
+  return HAL_OK;
+}
+
+
+#endif /* defined (CPU_IN_SECURE_STATE) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTCEx_Exported_Functions_Group8
+  * @brief      Extended RTC privilege functions
+  *
+@verbatim
+  ===============================================================================
+             ##### Extended RTC privilege functions #####
+  ===============================================================================
+  [..]
+   (+) Before calling privilege function, you have to call first
+       HAL_RTC_Init() function.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the privilege level of the RTC/TAMP/Backup registers.
+  *         To get the current privilege level call HAL_RTCEx_PrivilegeModeGet.
+  * @param  hrtc RTC handle
+  * @param  privilegeState  Privilege state
+  * @retval HAL_StatusTypeDef
+  */
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(const RTC_HandleTypeDef *hrtc,
+                                             const RTC_PrivilegeStateTypeDef *privilegeState)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull));
+  assert_param(IS_RTC_PRIVILEGE_FEATURES(privilegeState->rtcPrivilegeFeatures));
+  assert_param(IS_TAMP_PRIVILEGE_FULL(privilegeState->tampPrivilegeFull));
+  assert_param(IS_TAMP_MONOTONIC_CNT_PRIVILEGE(privilegeState->MonotonicCounterPrivilege));
+  assert_param(IS_RTC_PRIVILEGE_BKUP_ZONE(privilegeState->backupRegisterPrivZone));
+  assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone2));
+  assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone3));
+
+  /* RTC privilege configuration */
+  WRITE_REG(RTC->PRIVCFGR, privilegeState->rtcPrivilegeFull | privilegeState->rtcPrivilegeFeatures);
+
+  /* TAMP, Monotonic counter and Backup registers privilege configuration
+     Warning : privilegeState->backupRegisterPrivZone is only writable in secure mode or if trustzone is disabled.
+               In non secure mode, a notification is generated through a flag/interrupt in the TZIC
+               (TrustZone interrupt controller). The bits are not written. */
+  WRITE_REG(TAMP->PRIVCFGR, privilegeState->tampPrivilegeFull | privilegeState->backupRegisterPrivZone | \
+            privilegeState->MonotonicCounterPrivilege);
+
+  /* Backup register start zone
+     Warning : This parameter is only writable in secure mode or if trustzone is disabled.
+               In non secure mode, a notification is generated through a flag/interrupt in the TZIC
+               (TrustZone interrupt controller). The bits are not written.
+     Warning : Backup register start zones are shared with secure configuration */
+  MODIFY_REG(TAMP->SECCFGR,
+             (TAMP_SECCFGR_BKPRWSEC | TAMP_SECCFGR_BKPWSEC),
+             ((privilegeState->backupRegisterStartZone2 << TAMP_SECCFGR_BKPRWSEC_Pos) | \
+              (privilegeState->backupRegisterStartZone3 << TAMP_SECCFGR_BKPWSEC_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the privilege level of the RTC/TAMP/Backup registers.
+  *         To set the privilege level please call HAL_RTCEx_PrivilegeModeSet.
+  * @param  hrtc RTC handle
+  * @param  privilegeState  Privilege state
+  * @retval HAL_StatusTypeDef
+  */
+HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  /* Read registers */
+  uint32_t rtc_privcfgr = READ_REG(RTC->PRIVCFGR);
+  uint32_t tamp_privcfgr = READ_REG(TAMP->PRIVCFGR);
+  uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR);
+
+  /* RTC privilege configuration */
+  privilegeState->rtcPrivilegeFull = READ_BIT(rtc_privcfgr, RTC_PRIVCFGR_PRIV);
+
+  /* Warning, rtcPrivilegeFeatures is only relevant if privilegeState->rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO */
+  privilegeState->rtcPrivilegeFeatures = READ_BIT(rtc_privcfgr, RTC_PRIVILEGE_FEATURE_ALL);
+
+  /* TAMP and Backup registers privilege configuration */
+  privilegeState->tampPrivilegeFull = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_TAMPPRIV);
+
+  /* Monotonic registers privilege configuration */
+  privilegeState->MonotonicCounterPrivilege = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_CNT1PRIV);
+
+  /* Backup registers Zones */
+  privilegeState->backupRegisterPrivZone = READ_BIT(tamp_privcfgr, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV));
+
+  /* Backup register start zones
+     Warning : Shared with secure configuration */
+  privilegeState->backupRegisterStartZone2 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPRWSEC) >>
+                                             TAMP_SECCFGR_BKPRWSEC_Pos;
+
+  privilegeState->backupRegisterStartZone3 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPWSEC) >>
+                                             TAMP_SECCFGR_BKPWSEC_Pos;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sai.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sai.c
new file mode 100644
index 000000000..747d953ce
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sai.c
@@ -0,0 +1,2898 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sai.c
+  * @author  MCD Application Team
+  * @brief   SAI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Serial Audio Interface (SAI) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                  ##### How to use this driver #####
+  ==============================================================================
+
+  [..]
+    The SAI HAL driver can be used as follows:
+
+    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).
+    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
+        (##) Enable the SAI interface clock.
+        (##) SAI pins configuration:
+            (+++) Enable the clock for the SAI GPIOs.
+            (+++) Configure these SAI pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()
+             and HAL_SAI_Receive_IT() APIs):
+            (+++) Configure the SAI interrupt priority.
+            (+++) Enable the NVIC SAI IRQ handle.
+
+        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()
+             and HAL_SAI_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+                DMA Tx/Rx Stream.
+
+    (#) The initialization can be done by two ways
+        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().
+        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().
+
+  [..]
+    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)
+        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()
+        inside the transmit and receive process.
+  [..]
+    (@) Make sure that either:
+        (+@) PLLSAI1CLK output is configured or
+        (+@) PLLSAI2CLK output is configured or
+        (+@) PLLSAI3CLK output is configured or
+        (+@) External clock source is configured after setting correctly
+             the define constant EXTERNAL_SAI1_CLOCK_VALUE or EXTERNAL_SAI2_CLOCK_VALUE
+             in the stm32n6xx_hal_conf.h file.
+
+  [..]
+    (@) In master Tx mode: enabling the audio block immediately generates the bit clock
+        for the external slaves even if there is no data in the FIFO, However FS signal
+        generation is conditioned by the presence of data in the FIFO.
+
+  [..]
+    (@) In master Rx mode: enabling the audio block immediately generates the bit clock
+        and FS signal for the external slaves.
+
+  [..]
+    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:
+        (+@) First bit Offset <= (SLOT size - Data size)
+        (+@) Data size <= SLOT size
+        (+@) Number of SLOT x SLOT size = Frame length
+        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
+
+  [..]
+    (@) PDM interface can be activated through HAL_SAI_Init function.
+        Please note that PDM interface is only available for SAI1 sub-block A.
+        PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function.
+
+  [..]
+    Three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()
+      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    =============================
+    [..]
+      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()
+      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()
+      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()
+      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can
+          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()
+      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can
+          add his own code by customization of function pointer HAL_SAI_ErrorCallback()
+      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()
+      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()
+      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()
+
+    *** SAI HAL driver additional function list ***
+    ===============================================
+    [..]
+      Below the list the others API available SAI HAL driver :
+
+      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode
+      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode
+      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode
+      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode
+      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.
+      (+) HAL_SAI_Abort(): Abort the current transfer
+
+    *** SAI HAL driver macros list ***
+    ==================================
+    [..]
+      Below the list of most used macros in SAI HAL driver :
+
+      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral
+      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral
+      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts
+      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts
+      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is
+          enabled or disabled
+      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
+
+    *** Callback registration ***
+    =============================
+    [..]
+    The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+    Use functions HAL_SAI_RegisterCallback() to register a user callback.
+
+    [..]
+    Function HAL_SAI_RegisterCallback() allows to register following callbacks:
+      (+) RxCpltCallback     : SAI receive complete.
+      (+) RxHalfCpltCallback : SAI receive half complete.
+      (+) TxCpltCallback     : SAI transmit complete.
+      (+) TxHalfCpltCallback : SAI transmit half complete.
+      (+) ErrorCallback      : SAI error.
+      (+) MspInitCallback    : SAI MspInit.
+      (+) MspDeInitCallback  : SAI MspDeInit.
+    [..]
+    This function takes as parameters the HAL peripheral handle, the callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the callback ID.
+    [..]
+    This function allows to reset following callbacks:
+      (+) RxCpltCallback     : SAI receive complete.
+      (+) RxHalfCpltCallback : SAI receive half complete.
+      (+) TxCpltCallback     : SAI transmit complete.
+      (+) TxHalfCpltCallback : SAI transmit half complete.
+      (+) ErrorCallback      : SAI error.
+      (+) MspInitCallback    : SAI MspInit.
+      (+) MspDeInitCallback  : SAI MspDeInit.
+
+    [..]
+    By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak functions:
+    examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak functions in the HAL_SAI_Init
+    and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
+    or HAL_SAI_Init function.
+
+    [..]
+    When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak callbacks are used.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SAI SAI
+  * @brief SAI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup SAI_Private_Typedefs  SAI Private Typedefs
+  * @{
+  */
+typedef enum
+{
+  SAI_MODE_DMA,
+  SAI_MODE_IT
+} SAI_ModeTypedef;
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SAI_Private_Constants  SAI Private Constants
+  * @{
+  */
+#define SAI_DEFAULT_TIMEOUT      4U
+#define SAI_LONG_TIMEOUT         1000U
+#define SAI_SPDIF_FRAME_LENGTH   64U
+#define SAI_AC97_FRAME_LENGTH    256U
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SAI_Private_Functions  SAI Private Functions
+  * @{
+  */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai);
+static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode);
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
+
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);
+
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void SAI_DMAError(DMA_HandleTypeDef *hdma);
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup SAI_Exported_Functions SAI Exported Functions
+  * @{
+  */
+
+/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]  This subsection provides a set of functions allowing to initialize and
+        de-initialize the SAIx peripheral:
+
+      (+) User must implement HAL_SAI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SAI_Init() to configure the selected device with
+          the selected configuration:
+        (++) Mode (Master/slave TX/RX)
+        (++) Protocol
+        (++) Data Size
+        (++) MCLK Output
+        (++) Audio frequency
+        (++) FIFO Threshold
+        (++) Frame Config
+        (++) Slot Config
+        (++) PDM Config
+
+      (+) Call the function HAL_SAI_DeInit() to restore the default configuration
+          of the selected SAI peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the structure FrameInit, SlotInit and the low part of
+  *         Init according to the specified parameters and call the function
+  *         HAL_SAI_Init to initialize the SAI block.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  protocol one of the supported protocol @ref SAI_Protocol
+  * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
+  *                   the configuration information for SAI module.
+  * @param  nbslot Number of slot.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));
+  assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));
+
+  switch (protocol)
+  {
+    case SAI_I2S_STANDARD :
+    case SAI_I2S_MSBJUSTIFIED :
+    case SAI_I2S_LSBJUSTIFIED :
+      status = SAI_InitI2S(hsai, protocol, datasize, nbslot);
+      break;
+    case SAI_PCM_LONG :
+    case SAI_PCM_SHORT :
+      status = SAI_InitPCM(hsai, protocol, datasize, nbslot);
+      break;
+    default :
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    status = HAL_SAI_Init(hsai);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the SAI according to the specified parameters.
+  *         in the SAI_InitTypeDef structure and initialize the associated handle.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
+{
+  uint32_t tmpregisterGCR;
+  uint32_t ckstr_bits;
+  uint32_t syncen_bits;
+
+  /* Check the SAI handle allocation */
+  if (hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* check the instance */
+  assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));
+
+  /* Check the SAI Block parameters */
+  assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));
+  assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));
+  assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));
+  assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));
+  assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
+  assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
+  assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
+  assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput));
+  assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
+  assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
+  assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
+  assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));
+  assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));
+  assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));
+  assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));
+  assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling));
+
+  /* Check the SAI Block Frame parameters */
+  assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));
+  assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));
+  assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));
+  assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));
+  assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));
+
+  /* Check the SAI Block Slot parameters */
+  assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));
+  assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));
+  assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));
+  assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));
+
+  /* Check the SAI PDM parameters */
+  assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation));
+  if (hsai->Init.PdmInit.Activation == ENABLE)
+  {
+    assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr));
+    assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable));
+    /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */
+    if ((hsai->Instance != SAI1_Block_A) ||
+        (hsai->Init.AudioMode != SAI_MODEMASTER_RX) ||
+        (hsai->Init.Protocol != SAI_FREE_PROTOCOL))
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  if (hsai->State == HAL_SAI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsai->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    /* Reset callback pointers to the weak predefined callbacks */
+    hsai->RxCpltCallback     = HAL_SAI_RxCpltCallback;
+    hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+    hsai->TxCpltCallback     = HAL_SAI_TxCpltCallback;
+    hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+    hsai->ErrorCallback      = HAL_SAI_ErrorCallback;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    if (hsai->MspInitCallback == NULL)
+    {
+      hsai->MspInitCallback = HAL_SAI_MspInit;
+    }
+    hsai->MspInitCallback(hsai);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_SAI_MspInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+
+  /* Disable the selected SAI peripheral */
+  if (SAI_Disable(hsai) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  hsai->State = HAL_SAI_STATE_BUSY;
+
+  /* SAI Block Synchro Configuration -----------------------------------------*/
+  /* This setting must be done with both audio block (A & B) disabled         */
+  switch (hsai->Init.SynchroExt)
+  {
+    case SAI_SYNCEXT_DISABLE :
+      tmpregisterGCR = 0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+      break;
+    case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
+      tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+      break;
+    default :
+      tmpregisterGCR = 0;
+      break;
+  }
+
+  switch (hsai->Init.Synchro)
+  {
+    case SAI_ASYNCHRONOUS :
+      syncen_bits = 0;
+      break;
+    case SAI_SYNCHRONOUS :
+      syncen_bits = SAI_xCR1_SYNCEN_0;
+      break;
+    case SAI_SYNCHRONOUS_EXT_SAI1 :
+      syncen_bits = SAI_xCR1_SYNCEN_1;
+      break;
+    case SAI_SYNCHRONOUS_EXT_SAI2 :
+      syncen_bits = SAI_xCR1_SYNCEN_1;
+      tmpregisterGCR |= SAI_GCR_SYNCIN_0;
+      break;
+    default :
+      syncen_bits = 0;
+      break;
+  }
+
+  if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+  {
+    SAI1->GCR = tmpregisterGCR;
+  }
+  else
+  {
+    SAI2->GCR = tmpregisterGCR;
+  }
+
+  if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
+  {
+    uint32_t freq = 0;
+    uint32_t tmpval;
+
+    /* In this case, the MCKDIV value is calculated to get AudioFrequency */
+    if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))
+    {
+      freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);
+    }
+    if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B))
+    {
+      freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);
+    }
+
+    /* Configure Master Clock Divider using the following formula :
+       - If NODIV = 1 :
+         MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
+       - If NODIV = 0 :
+         MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
+    if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
+    {
+      /* NODIV = 1 */
+      uint32_t tmpframelength;
+
+      if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+      {
+        /* For SPDIF protocol, frame length is set by hardware to 64 */
+        tmpframelength = SAI_SPDIF_FRAME_LENGTH;
+      }
+      else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
+      {
+        /* For AC97 protocol, frame length is set by hardware to 256 */
+        tmpframelength = SAI_AC97_FRAME_LENGTH;
+      }
+      else
+      {
+        /* For free protocol, frame length is set by user */
+        tmpframelength = hsai->FrameInit.FrameLength;
+      }
+
+      /* (freq x 10) to keep Significant digits */
+      tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength);
+    }
+    else
+    {
+      /* NODIV = 0 */
+      uint32_t tmposr;
+      tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U;
+      /* (freq x 10) to keep Significant digits */
+      tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U);
+    }
+    hsai->Init.Mckdiv = tmpval / 10U;
+
+    /* Round result to the nearest integer */
+    if ((tmpval % 10U) > 8U)
+    {
+      hsai->Init.Mckdiv += 1U;
+    }
+
+    /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
+    if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
+    {
+      hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
+    }
+  }
+
+  /* Check the SAI Block master clock divider parameter */
+  assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
+
+  /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */
+  if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    /* Transmit */
+    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR;
+  }
+  else
+  {
+    /* Receive */
+    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U;
+  }
+
+  /* SAI Block Configuration -------------------------------------------------*/
+  /* SAI CR1 Configuration */
+  hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \
+                           SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
+                           SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \
+                           SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR |     \
+                           SAI_xCR1_MCKEN);
+
+  hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol |           \
+                          hsai->Init.DataSize | hsai->Init.FirstBit  |           \
+                          ckstr_bits | syncen_bits |                             \
+                          hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \
+                          hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) |     \
+                          hsai->Init.MckOverSampling | hsai->Init.MckOutput);
+
+  /* SAI CR2 Configuration */
+  hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
+  hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);
+
+  /* SAI Frame Configuration -----------------------------------------*/
+  hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \
+                             SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));
+  hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) |
+                           hsai->FrameInit.FSOffset |
+                           hsai->FrameInit.FSDefinition |
+                           hsai->FrameInit.FSPolarity   |
+                           ((hsai->FrameInit.ActiveFrameLength - 1U) << 8));
+
+  /* SAI Block_x SLOT Configuration ------------------------------------------*/
+  /* This register has no meaning in AC 97 and SPDIF audio protocol */
+  hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |  \
+                              SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN));
+
+  hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \
+                           (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) <<  8);
+
+  /* SAI PDM Configuration ---------------------------------------------------*/
+  if (hsai->Instance == SAI1_Block_A)
+  {
+    /* Disable PDM interface */
+    SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
+    if (hsai->Init.PdmInit.Activation == ENABLE)
+    {
+      /* Configure and enable PDM interface */
+      SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable |
+                     ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos));
+      SAI1->PDMCR |= SAI_PDMCR_PDMEN;
+    }
+  }
+
+  /* Initialize the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+  /* Initialize the SAI state */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the SAI peripheral.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
+{
+  /* Check the SAI handle allocation */
+  if (hsai == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hsai->State = HAL_SAI_STATE_BUSY;
+
+  /* Disabled All interrupt and clear all the flag */
+  hsai->Instance->IMR = 0;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+  /* Disable the SAI */
+  if (SAI_Disable(hsai) != HAL_OK)
+  {
+    /* Reset SAI state to ready */
+    hsai->State = HAL_SAI_STATE_READY;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_ERROR;
+  }
+
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+  /* Disable SAI PDM interface */
+  if (hsai->Instance == SAI1_Block_A)
+  {
+    /* Reset PDM delays */
+    SAI1->PDMDLY = 0U;
+
+    /* Disable PDM interface */
+    SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN);
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  if (hsai->MspDeInitCallback == NULL)
+  {
+    hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+  }
+  hsai->MspDeInitCallback(hsai);
+#else
+  HAL_SAI_MspDeInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+  /* Initialize the error code */
+  hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+  /* Initialize the SAI state */
+  hsai->State = HAL_SAI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the SAI MSP.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the SAI MSP.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a user SAI callback
+  *         to be used instead of the weak predefined callback.
+  * @param  hsai SAI handle.
+  * @param  CallbackID ID of the callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+  *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+  *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+  *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+  *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @param  pCallback pointer to the callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,
+                                           HAL_SAI_CallbackIDTypeDef CallbackID,
+                                           pSAI_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* update the error code */
+    hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (HAL_SAI_STATE_READY == hsai->State)
+    {
+      switch (CallbackID)
+      {
+        case HAL_SAI_RX_COMPLETE_CB_ID :
+          hsai->RxCpltCallback = pCallback;
+          break;
+        case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+          hsai->RxHalfCpltCallback = pCallback;
+          break;
+        case HAL_SAI_TX_COMPLETE_CB_ID :
+          hsai->TxCpltCallback = pCallback;
+          break;
+        case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+          hsai->TxHalfCpltCallback = pCallback;
+          break;
+        case HAL_SAI_ERROR_CB_ID :
+          hsai->ErrorCallback = pCallback;
+          break;
+        case HAL_SAI_MSPINIT_CB_ID :
+          hsai->MspInitCallback = pCallback;
+          break;
+        case HAL_SAI_MSPDEINIT_CB_ID :
+          hsai->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else if (HAL_SAI_STATE_RESET == hsai->State)
+    {
+      switch (CallbackID)
+      {
+        case HAL_SAI_MSPINIT_CB_ID :
+          hsai->MspInitCallback = pCallback;
+          break;
+        case HAL_SAI_MSPDEINIT_CB_ID :
+          hsai->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* update the error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Unregister a user SAI callback.
+  *         SAI callback is redirected to the weak predefined callback.
+  * @param  hsai SAI handle.
+  * @param  CallbackID ID of the callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+  *           @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+  *           @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+  *           @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+  *           @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+  *           @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,
+                                             HAL_SAI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_SAI_STATE_READY == hsai->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SAI_RX_COMPLETE_CB_ID :
+        hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+        break;
+      case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+        hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+        break;
+      case HAL_SAI_TX_COMPLETE_CB_ID :
+        hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+        break;
+      case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+        hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+        break;
+      case HAL_SAI_ERROR_CB_ID :
+        hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+        break;
+      case HAL_SAI_MSPINIT_CB_ID :
+        hsai->MspInitCallback = HAL_SAI_MspInit;
+        break;
+      case HAL_SAI_MSPDEINIT_CB_ID :
+        hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SAI_STATE_RESET == hsai->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SAI_MSPINIT_CB_ID :
+        hsai->MspInitCallback = HAL_SAI_MspInit;
+        break;
+      case HAL_SAI_MSPDEINIT_CB_ID :
+        hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update the error code */
+    hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
+  * @brief    Data transfers functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the SAI data
+    transfers.
+
+    (+) There are two modes of transfer:
+      (++) Blocking mode : The communication is performed in the polling mode.
+           The status of all data processing is returned by the same function
+           after finishing transfer.
+      (++) No-Blocking mode : The communication is performed using Interrupts
+           or DMA. These functions return the status of the transfer startup.
+           The end of the data processing will be indicated through the
+           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+
+    (+) Blocking mode functions are :
+      (++) HAL_SAI_Transmit()
+      (++) HAL_SAI_Receive()
+
+    (+) Non Blocking mode functions with Interrupt are :
+      (++) HAL_SAI_Transmit_IT()
+      (++) HAL_SAI_Receive_IT()
+
+    (+) Non Blocking mode functions with DMA are :
+      (++) HAL_SAI_Transmit_DMA()
+      (++) HAL_SAI_Receive_DMA()
+
+    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+      (++) HAL_SAI_TxCpltCallback()
+      (++) HAL_SAI_RxCpltCallback()
+      (++) HAL_SAI_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t temp;
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->pBuffPtr = pData;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+    {
+      /* fill the fifo with data before to enabled the SAI */
+      SAI_FillFifo(hsai);
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    while (hsai->XferCount > 0U)
+    {
+      /* Write data if the FIFO is not full */
+      if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)
+      {
+        if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+        {
+          hsai->Instance->DR = *hsai->pBuffPtr;
+          hsai->pBuffPtr++;
+        }
+        else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+        {
+          temp = (uint32_t)(*hsai->pBuffPtr);
+          hsai->pBuffPtr++;
+          temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+          hsai->pBuffPtr++;
+          hsai->Instance->DR = temp;
+        }
+        else
+        {
+          temp = (uint32_t)(*hsai->pBuffPtr);
+          hsai->pBuffPtr++;
+          temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+          hsai->pBuffPtr++;
+          temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+          hsai->pBuffPtr++;
+          temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+          hsai->pBuffPtr++;
+          hsai->Instance->DR = temp;
+        }
+        hsai->XferCount--;
+      }
+      else
+      {
+        /* Check for the Timeout */
+        if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
+        {
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+          /* Disable SAI peripheral */
+          /* No need to check return value because state update, unlock and error return will be performed later */
+          (void) SAI_Disable(hsai);
+
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    hsai->State = HAL_SAI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t temp;
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Receive data */
+    while (hsai->XferCount > 0U)
+    {
+      if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)
+      {
+        if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+        {
+          *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
+          hsai->pBuffPtr++;
+        }
+        else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+        {
+          temp = hsai->Instance->DR;
+          *hsai->pBuffPtr = (uint8_t)temp;
+          hsai->pBuffPtr++;
+          *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+          hsai->pBuffPtr++;
+        }
+        else
+        {
+          temp = hsai->Instance->DR;
+          *hsai->pBuffPtr = (uint8_t)temp;
+          hsai->pBuffPtr++;
+          *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+          hsai->pBuffPtr++;
+          *hsai->pBuffPtr = (uint8_t)(temp >> 16);
+          hsai->pBuffPtr++;
+          *hsai->pBuffPtr = (uint8_t)(temp >> 24);
+          hsai->pBuffPtr++;
+        }
+        hsai->XferCount--;
+      }
+      else
+      {
+        /* Check for the Timeout */
+        if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY))
+        {
+          /* Update error code */
+          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+          /* Clear all the flags */
+          hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+          /* Disable SAI peripheral */
+          /* No need to check return value because state update, unlock and error return will be performed later */
+          (void) SAI_Disable(hsai);
+
+          /* Flush the fifo */
+          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+          /* Change the SAI state */
+          hsai->State = HAL_SAI_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsai);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    hsai->State = HAL_SAI_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;
+    }
+    else
+    {
+      hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;
+    }
+
+    /* Fill the fifo before starting the communication */
+    SAI_FillFifo(hsai);
+
+    /* Enable FRQ and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;
+    }
+    else
+    {
+      hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;
+    }
+
+    /* Enable TXE and OVRUDR interrupts */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the audio stream playing from the Media.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Pause the audio file playing by disabling the SAI DMA requests */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the audio stream playing from the Media.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
+{
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Enable the SAI DMA requests */
+  hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+  /* If the SAI peripheral is still not enabled, enable it */
+  if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+  {
+    /* Enable SAI peripheral */
+    __HAL_SAI_ENABLE(hsai);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the audio stream playing from the Media.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Disable SAI peripheral */
+  if (SAI_Disable(hsai) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Disable the SAI DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Abort the SAI Tx DMA Stream */
+  if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
+  {
+    if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+    {
+      /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+      if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+      {
+        status = HAL_ERROR;
+        hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+      }
+    }
+  }
+
+  /* Abort the SAI Rx DMA Stream */
+  if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
+  {
+    if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+    {
+      /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+      if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+      {
+        status = HAL_ERROR;
+        hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+      }
+    }
+  }
+
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+  /* Set hsai state to ready */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return status;
+}
+
+/**
+  * @brief Abort the current transfer and disable the SAI.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hsai);
+
+  /* Disable SAI peripheral */
+  if (SAI_Disable(hsai) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Check SAI DMA is enabled or not */
+  if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+  {
+    /* Disable the SAI DMA request */
+    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+    /* Abort the SAI Tx DMA Stream */
+    if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
+    {
+      if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
+      {
+        /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+        if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+        {
+          status = HAL_ERROR;
+          hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+        }
+      }
+    }
+
+    /* Abort the SAI Rx DMA Stream */
+    if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
+    {
+      if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
+      {
+        /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+        if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+        {
+          status = HAL_ERROR;
+          hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+        }
+      }
+    }
+  }
+
+  /* Disabled All interrupt and clear all the flag */
+  hsai->Instance->IMR = 0;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+  /* Flush the fifo */
+  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+  /* Set hsai state to ready */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsai);
+
+  return status;
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    uint32_t dmaSrcSize;
+
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_TX;
+
+    /* Set the SAI Tx DMA Half transfer complete callback */
+    hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;
+
+    /* Set the SAI TxDMA transfer complete callback */
+    hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;
+
+    /* Set the DMA error callback */
+    hsai->hdmatx->XferErrorCallback = SAI_DMAError;
+
+    /* Set the DMA Tx abort callback */
+    hsai->hdmatx->XferAbortCallback = NULL;
+
+    /* For transmission, the DMA source is data buffer.
+       We have to compute DMA size of a source block transfer in bytes according SAI data size. */
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      dmaSrcSize = (uint32_t) Size;
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      dmaSrcSize = 2U * (uint32_t) Size;
+    }
+    else
+    {
+      dmaSrcSize = 4U * (uint32_t) Size;
+    }
+
+    /* Enable the Tx DMA Stream */
+    if ((hsai->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if (hsai->hdmatx->LinkedListQueue != NULL)
+      {
+        /* Set DMA data size */
+        hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize;
+
+        /* Set DMA source address */
+        hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr;
+
+        /* Set DMA destination address */
+        hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR;
+
+        status = HAL_DMAEx_List_Start_IT(hsai->hdmatx);
+      }
+      else
+      {
+        __HAL_UNLOCK(hsai);
+        return  HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, dmaSrcSize);
+    }
+
+    if (status != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
+
+    /* Enable the interrupts for error handling */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    /* Enable SAI Tx DMA Request */
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+    /* Wait until FIFO is not empty */
+    while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT)
+      {
+        /* Update error code */
+        hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsai);
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hsai->State == HAL_SAI_STATE_READY)
+  {
+    uint32_t dmaSrcSize;
+
+    /* Process Locked */
+    __HAL_LOCK(hsai);
+
+    hsai->pBuffPtr = pData;
+    hsai->XferSize = Size;
+    hsai->XferCount = Size;
+    hsai->ErrorCode = HAL_SAI_ERROR_NONE;
+    hsai->State = HAL_SAI_STATE_BUSY_RX;
+
+    /* Set the SAI Rx DMA Half transfer complete callback */
+    hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;
+
+    /* Set the SAI Rx DMA transfer complete callback */
+    hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;
+
+    /* Set the DMA error callback */
+    hsai->hdmarx->XferErrorCallback = SAI_DMAError;
+
+    /* Set the DMA Rx abort callback */
+    hsai->hdmarx->XferAbortCallback = NULL;
+
+    /* For reception, the DMA source is SAI DR register.
+       We have to compute DMA size of a source block transfer in bytes according SAI data size. */
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      dmaSrcSize = (uint32_t) Size;
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      dmaSrcSize = 2U * (uint32_t) Size;
+    }
+    else
+    {
+      dmaSrcSize = 4U * (uint32_t) Size;
+    }
+
+    /* Enable the Rx DMA Stream */
+    if ((hsai->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if (hsai->hdmarx->LinkedListQueue != NULL)
+      {
+        /* Set DMA data size */
+        hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize;
+
+        /* Set DMA source address */
+        hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR;
+
+        /* Set DMA destination address */
+        hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr;
+
+        status = HAL_DMAEx_List_Start_IT(hsai->hdmarx);
+      }
+      else
+      {
+        __HAL_UNLOCK(hsai);
+        return  HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, dmaSrcSize);
+    }
+
+    if (status != HAL_OK)
+    {
+      __HAL_UNLOCK(hsai);
+      return  HAL_ERROR;
+    }
+
+    /* Enable the interrupts for error handling */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    /* Enable SAI Rx DMA Request */
+    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
+    /* Check if the SAI is already enabled */
+    if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
+    {
+      /* Enable SAI peripheral */
+      __HAL_SAI_ENABLE(hsai);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsai);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the Tx mute mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  val  value sent during the mute @ref SAI_Block_Mute_Value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
+{
+  assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));
+
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+    SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable the Tx mute mode.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Enable the Rx mute detection.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  callback function called when the mute is detected.
+  * @param  counter number a data before mute detection max 63.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
+{
+  assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));
+
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    /* set the mute counter */
+    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
+    SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
+    hsai->mutecallback = callback;
+    /* enable the IT interrupt */
+    __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable the Rx mute detection.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    /* set the mutecallback to NULL */
+    hsai->mutecallback = NULL;
+    /* enable the IT interrupt */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Handle SAI interrupt request.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->State != HAL_SAI_STATE_RESET)
+  {
+    uint32_t itflags = hsai->Instance->SR;
+    uint32_t itsources = hsai->Instance->IMR;
+    uint32_t cr1config = hsai->Instance->CR1;
+    uint32_t tmperror;
+
+    /* SAI Fifo request interrupt occurred -----------------------------------*/
+    if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
+    {
+      hsai->InterruptServiceRoutine(hsai);
+    }
+    /* SAI Overrun error interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))
+    {
+      /* Clear the SAI Overrun flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+      /* Get the SAI error code */
+      tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);
+      /* Change the SAI error code */
+      hsai->ErrorCode |= tmperror;
+      /* the transfer is not stopped, we will forward the information to the user and we let
+      the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+      hsai->ErrorCallback(hsai);
+#else
+      HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+    }
+    /* SAI mutedet interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
+    {
+      /* Clear the SAI mutedet flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);
+      /* call the call back function */
+      if (hsai->mutecallback != NULL)
+      {
+        /* inform the user that an RX mute event has been detected */
+        hsai->mutecallback();
+      }
+    }
+    /* SAI AFSDET interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
+    {
+      /* Clear the SAI AFSDET flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
+
+      /* Check SAI DMA is enabled or not */
+      if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if (hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+          {
+            /* Update SAI error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+            /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+            hsai->ErrorCallback(hsai);
+#else
+            HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+          }
+        }
+        if (hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+          {
+            /* Update SAI error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+            /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+            hsai->ErrorCallback(hsai);
+#else
+            HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+          }
+        }
+      }
+      else
+      {
+        /* Abort SAI */
+        /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
+        (void) HAL_SAI_Abort(hsai);
+
+        /* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+        hsai->ErrorCallback(hsai);
+#else
+        HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+      }
+    }
+    /* SAI LFSDET interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
+    {
+      /* Clear the SAI LFSDET flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
+
+      /* Check SAI DMA is enabled or not */
+      if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if (hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+          {
+            /* Update SAI error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+            /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+            hsai->ErrorCallback(hsai);
+#else
+            HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+          }
+        }
+        if (hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+          {
+            /* Update SAI error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+            /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+            hsai->ErrorCallback(hsai);
+#else
+            HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+          }
+        }
+      }
+      else
+      {
+        /* Abort SAI */
+        /* No need to check return value because HAL_SAI_ErrorCallback will be called later */
+        (void) HAL_SAI_Abort(hsai);
+
+        /* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+        hsai->ErrorCallback(hsai);
+#else
+        HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+      }
+    }
+    /* SAI WCKCFG interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
+    {
+      /* Clear the SAI WCKCFG flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
+
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
+
+      /* Check SAI DMA is enabled or not */
+      if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
+      {
+        /* Abort the SAI DMA Streams */
+        if (hsai->hdmatx != NULL)
+        {
+          /* Set the DMA Tx abort callback */
+          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK)
+          {
+            /* Update SAI error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+            /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+            hsai->ErrorCallback(hsai);
+#else
+            HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+          }
+        }
+        if (hsai->hdmarx != NULL)
+        {
+          /* Set the DMA Rx abort callback */
+          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;
+
+          /* Abort DMA in IT mode */
+          if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK)
+          {
+            /* Update SAI error code */
+            hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+            /* Call SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+            hsai->ErrorCallback(hsai);
+#else
+            HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+          }
+        }
+      }
+      else
+      {
+        /* If WCKCFG occurs, SAI audio block is automatically disabled */
+        /* Disable all interrupts and clear all flags */
+        hsai->Instance->IMR = 0U;
+        hsai->Instance->CLRFR = 0xFFFFFFFFU;
+        /* Set the SAI state to ready to be able to start again the process */
+        hsai->State = HAL_SAI_STATE_READY;
+
+        /* Initialize XferCount */
+        hsai->XferCount = 0U;
+
+        /* SAI error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+        hsai->ErrorCallback(hsai);
+#else
+        HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+      }
+    }
+    /* SAI CNRDY interrupt occurred ----------------------------------*/
+    else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))
+    {
+      /* Clear the SAI CNRDY flag */
+      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);
+      /* Change the SAI error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
+      /* the transfer is not stopped, we will forward the information to the user and we let
+      the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+      hsai->ErrorCallback(hsai);
+#else
+      HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx Transfer Half completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer half completed callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief SAI error callback.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsai);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SAI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions
+  *
+@verbatim
+  ===============================================================================
+                ##### Peripheral State and Errors functions #####
+  ===============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SAI handle state.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval HAL state
+  */
+HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai)
+{
+  return hsai->State;
+}
+
+/**
+  * @brief  Return the SAI error code.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for the specified SAI Block.
+  * @retval SAI Error Code
+  */
+uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai)
+{
+  return hsai->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SAI_Private_Functions
+  * @brief      Private functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SAI I2S protocol according to the specified parameters
+  *         in the SAI_InitTypeDef and create the associated handle.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  protocol one of the supported protocol.
+  * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize.
+  * @param  nbslot number of slot minimum value is 2 and max is 16.
+  *         the value must be a multiple of 2.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
+  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
+  /* Compute ClockStrobing according AudioMode */
+  if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    /* Transmit */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
+  }
+  else
+  {
+    /* Receive */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
+  }
+  hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;
+  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
+  hsai->SlotInit.FirstBitOffset  = 0;
+  hsai->SlotInit.SlotNumber      = nbslot;
+
+  /* in IS2 the number of slot must be even */
+  if ((nbslot & 0x1U) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  if (protocol == SAI_I2S_STANDARD)
+  {
+    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
+    hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;
+  }
+  else
+  {
+    /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
+    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
+    hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;
+  }
+
+  /* Frame definition */
+  switch (datasize)
+  {
+    case SAI_PROTOCOL_DATASIZE_16BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 32U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_24BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_24;
+      hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_32BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_32;
+      hsai->FrameInit.FrameLength = 64U * (nbslot / 2U);
+      hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U);
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    default :
+      status = HAL_ERROR;
+      break;
+  }
+  if (protocol == SAI_I2S_LSBJUSTIFIED)
+  {
+    if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)
+    {
+      hsai->SlotInit.FirstBitOffset = 16;
+    }
+    if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)
+    {
+      hsai->SlotInit.FirstBitOffset = 8;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Initialize the SAI PCM protocol according to the specified parameters
+  *         in the SAI_InitTypeDef and create the associated handle.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  protocol one of the supported protocol
+  * @param  datasize one of the supported datasize @ref SAI_Protocol_DataSize
+  * @param  nbslot number of slot minimum value is 1 and the max is 16.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;
+  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;
+  /* Compute ClockStrobing according AudioMode */
+  if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    /* Transmit */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;
+  }
+  else
+  {
+    /* Receive */
+    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;
+  }
+  hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;
+  hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;
+  hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;
+  hsai->SlotInit.FirstBitOffset  = 0;
+  hsai->SlotInit.SlotNumber      = nbslot;
+  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;
+
+  if (protocol == SAI_PCM_SHORT)
+  {
+    hsai->FrameInit.ActiveFrameLength = 1;
+  }
+  else
+  {
+    /* SAI_PCM_LONG */
+    hsai->FrameInit.ActiveFrameLength = 13;
+  }
+
+  switch (datasize)
+  {
+    case SAI_PROTOCOL_DATASIZE_16BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 16U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :
+      hsai->Init.DataSize = SAI_DATASIZE_16;
+      hsai->FrameInit.FrameLength = 32U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_24BIT :
+      hsai->Init.DataSize = SAI_DATASIZE_24;
+      hsai->FrameInit.FrameLength = 32U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    case SAI_PROTOCOL_DATASIZE_32BIT:
+      hsai->Init.DataSize = SAI_DATASIZE_32;
+      hsai->FrameInit.FrameLength = 32U * nbslot;
+      hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;
+      break;
+    default :
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Fill the fifo.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_FillFifo(SAI_HandleTypeDef *hsai)
+{
+  uint32_t temp;
+
+  /* fill the fifo with data before to enabled the SAI */
+  while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U))
+  {
+    if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))
+    {
+      hsai->Instance->DR = *hsai->pBuffPtr;
+      hsai->pBuffPtr++;
+    }
+    else if (hsai->Init.DataSize <= SAI_DATASIZE_16)
+    {
+      temp = (uint32_t)(*hsai->pBuffPtr);
+      hsai->pBuffPtr++;
+      temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+      hsai->pBuffPtr++;
+      hsai->Instance->DR = temp;
+    }
+    else
+    {
+      temp = (uint32_t)(*hsai->pBuffPtr);
+      hsai->pBuffPtr++;
+      temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+      hsai->pBuffPtr++;
+      temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+      hsai->pBuffPtr++;
+      temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+      hsai->pBuffPtr++;
+      hsai->Instance->DR = temp;
+    }
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Return the interrupt flag to set according the SAI setup.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @param  mode SAI_MODE_DMA or SAI_MODE_IT
+  * @retval the list of the IT flag to enable
+  */
+static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode)
+{
+  uint32_t tmpIT = SAI_IT_OVRUDR;
+
+  if (mode == SAI_MODE_IT)
+  {
+    tmpIT |= SAI_IT_FREQ;
+  }
+
+  if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&
+      ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))
+  {
+    tmpIT |= SAI_IT_CNRDY;
+  }
+
+  if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
+  {
+    tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET;
+  }
+  else
+  {
+    /* hsai has been configured in master mode */
+    tmpIT |= SAI_IT_WCKCFG;
+  }
+  return tmpIT;
+}
+
+/**
+  * @brief  Disable the SAI and wait for the disabling.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
+{
+  uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Disable the SAI instance */
+  __HAL_SAI_DISABLE(hsai);
+
+  do
+  {
+    /* Check for the Timeout */
+    if (count == 0U)
+    {
+      /* Update error code */
+      hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;
+      status = HAL_TIMEOUT;
+      break;
+    }
+    count--;
+  } while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U);
+
+  return status;
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->XferCount == 0U)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->TxCpltCallback(hsai);
+#else
+    HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Write data on DR register */
+    hsai->Instance->DR = *hsai->pBuffPtr;
+    hsai->pBuffPtr++;
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->XferCount == 0U)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->TxCpltCallback(hsai);
+#else
+    HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Write data on DR register */
+    uint32_t temp;
+    temp = (uint32_t)(*hsai->pBuffPtr);
+    hsai->pBuffPtr++;
+    temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+    hsai->pBuffPtr++;
+    hsai->Instance->DR = temp;
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+  if (hsai->XferCount == 0U)
+  {
+    /* Handle the end of the transmission */
+    /* Disable FREQ and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->TxCpltCallback(hsai);
+#else
+    HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Write data on DR register */
+    uint32_t temp;
+    temp = (uint32_t)(*hsai->pBuffPtr);
+    hsai->pBuffPtr++;
+    temp |= ((uint32_t)(*hsai->pBuffPtr) << 8);
+    hsai->pBuffPtr++;
+    temp |= ((uint32_t)(*hsai->pBuffPtr) << 16);
+    hsai->pBuffPtr++;
+    temp |= ((uint32_t)(*hsai->pBuffPtr) << 24);
+    hsai->pBuffPtr++;
+    hsai->Instance->DR = temp;
+    hsai->XferCount--;
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
+{
+  /* Receive data */
+  *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR;
+  hsai->pBuffPtr++;
+  hsai->XferCount--;
+
+  /* Check end of the transfer */
+  if (hsai->XferCount == 0U)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->RxCpltCallback(hsai);
+#else
+    HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
+{
+  uint32_t temp;
+
+  /* Receive data */
+  temp = hsai->Instance->DR;
+  *hsai->pBuffPtr = (uint8_t)temp;
+  hsai->pBuffPtr++;
+  *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+  hsai->pBuffPtr++;
+  hsai->XferCount--;
+
+  /* Check end of the transfer */
+  if (hsai->XferCount == 0U)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->RxCpltCallback(hsai);
+#else
+    HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
+  * @param  hsai pointer to a SAI_HandleTypeDef structure that contains
+  *              the configuration information for SAI module.
+  * @retval None
+  */
+static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
+{
+  uint32_t temp;
+
+  /* Receive data */
+  temp = hsai->Instance->DR;
+  *hsai->pBuffPtr = (uint8_t)temp;
+  hsai->pBuffPtr++;
+  *hsai->pBuffPtr = (uint8_t)(temp >> 8);
+  hsai->pBuffPtr++;
+  *hsai->pBuffPtr = (uint8_t)(temp >> 16);
+  hsai->pBuffPtr++;
+  *hsai->pBuffPtr = (uint8_t)(temp >> 24);
+  hsai->pBuffPtr++;
+  hsai->XferCount--;
+
+  /* Check end of the transfer */
+  if (hsai->XferCount == 0U)
+  {
+    /* Disable TXE and OVRUDR interrupts */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
+
+    /* Clear the SAI Overrun flag */
+    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
+
+    hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+    hsai->RxCpltCallback(hsai);
+#else
+    HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  DMA SAI transmit process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Check if DMA in circular mode */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    hsai->XferCount = 0;
+
+    /* Disable SAI Tx DMA Request */
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+
+    /* Stop the interrupts error handling */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    hsai->State = HAL_SAI_STATE_READY;
+  }
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->TxCpltCallback(hsai);
+#else
+  HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SAI transmit process half complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->TxHalfCpltCallback(hsai);
+#else
+  HAL_SAI_TxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SAI receive process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Check if DMA in circular mode*/
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    /* Disable Rx DMA Request */
+    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
+    hsai->XferCount = 0;
+
+    /* Stop the interrupts error handling */
+    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+    hsai->State = HAL_SAI_STATE_READY;
+  }
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->RxCpltCallback(hsai);
+#else
+  HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SAI receive process half complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->RxHalfCpltCallback(hsai);
+#else
+  HAL_SAI_RxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SAI communication error callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set SAI error code */
+  hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+
+  /* Disable the SAI DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Disable SAI peripheral */
+  /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
+  (void) SAI_Disable(hsai);
+
+  /* Set the SAI state ready to be able to start again the process */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Initialize XferCount */
+  hsai->XferCount = 0U;
+
+  /* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->ErrorCallback(hsai);
+#else
+  HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SAI Abort callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable DMA request */
+  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
+
+  /* Disable all interrupts and clear all flags */
+  hsai->Instance->IMR = 0U;
+  hsai->Instance->CLRFR = 0xFFFFFFFFU;
+
+  if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
+  {
+    /* Disable SAI peripheral */
+    /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
+    (void) SAI_Disable(hsai);
+
+    /* Flush the fifo */
+    SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+  }
+  /* Set the SAI state to ready to be able to start again the process */
+  hsai->State = HAL_SAI_STATE_READY;
+
+  /* Initialize XferCount */
+  hsai->XferCount = 0U;
+
+  /* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+  hsai->ErrorCallback(hsai);
+#else
+  HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sai_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sai_ex.c
new file mode 100644
index 000000000..3bdb9e372
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sai_ex.c
@@ -0,0 +1,129 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sai_ex.c
+  * @author  MCD Application Team
+  * @brief   SAI Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionality of the SAI Peripheral Controller:
+  *           + Modify PDM microphone delays.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_SAI_MODULE_ENABLED
+
+/** @defgroup SAIEx SAIEx
+  * @brief SAI Extended HAL module driver
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines
+  * @{
+  */
+#define SAI_PDM_DELAY_MASK          0x77U
+#define SAI_PDM_DELAY_OFFSET        8U
+#define SAI_PDM_RIGHT_DELAY_OFFSET  4U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    SAIEx control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Modify PDM microphone delays
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure PDM microphone delays.
+  * @param  hsai SAI handle.
+  * @param  pdmMicDelay Microphone delays configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai,
+                                              const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t offset;
+
+  /* Check that SAI sub-block is SAI1 sub-block A */
+  if (hsai->Instance != SAI1_Block_A)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check microphone delay parameters */
+    assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
+    assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
+    assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
+
+    /* Compute offset on PDMDLY register according mic pair number */
+    offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
+
+    /* Check SAI state and offset */
+    if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
+    {
+      /* Reset current delays for specified microphone */
+      SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
+
+      /* Apply new microphone delays */
+      SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SAI_MODULE_ENABLED */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sd.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sd.c
new file mode 100644
index 000000000..1ea168ae5
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sd.c
@@ -0,0 +1,4082 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sd.c
+  * @author  MCD Application Team
+  * @brief   SD card HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to
+    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+    the user in HAL_SD_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDMMC memories which uses the HAL
+    SDMMC driver functions to interface with SD and uSD cards devices.
+    It is used as follows:
+
+    (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API:
+        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+        (##) SDMMC pins configuration for SD card
+            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+             and HAL_SD_WriteBlocks_IT() APIs).
+            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
+
+    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
+  *** SD Card Initialization and configuration ***
+  ================================================
+  [..]
+    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+    SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+    This function provide the following operations:
+
+    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+        type (Standard Capacity or High Capacity). You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        The SD Card frequency (SDMMC_CK) is computed as follows:
+
+           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+        In initialization mode and according to the SD Card standard,
+        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+        This phase of initialization is done through SDMMC_Init() and
+        SDMMC_PowerState_ON() SDMMC low level APIs.
+
+    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+        This phase allows the card initialization and identification
+        and check the SD Card type (Standard Capacity or High Capacity)
+        The initialization flow is compatible with SD standard.
+
+        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+        of plug-off plug-in.
+
+    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        In transfer mode and according to the SD Card standard, make sure that the
+        SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
+
+    (#) Select the corresponding SD Card according to the address read with the step 2.
+
+    (#) Configure the SD Card in wide bus mode: 4-bits data.
+
+  *** SD Card Read operation ***
+  ==============================
+  [..]
+    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Rx interrupt event.
+
+    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Rx interrupt event.
+
+  *** SD Card Write operation ***
+  ===============================
+  [..]
+    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+
+    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Tx interrupt event.
+
+    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Tx interrupt event.
+
+  *** SD card status ***
+  ======================
+  [..]
+    (+) The SD Status contains status bits that are related to the SD Memory
+        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+  *** SD card information ***
+  ===========================
+  [..]
+    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+        It returns useful information about the SD card such as block size, card type,
+        block number ...
+
+  *** SD card CSD register ***
+  ============================
+    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD card CID register ***
+  ============================
+    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SD HAL driver.
+
+    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+
+    (@) You can refer to the SD HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_SD_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
+      (+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
+      (+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
+      (+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+    For specific callbacks TransceiverCallback use dedicated register callbacks:
+    respectively HAL_SD_RegisterTransceiverCallback().
+
+    Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) Read_DMALnkLstBufCpltCallback : callback when the DMA reception of linked list node buffer is completed.
+      (+) Write_DMALnkLstBufCpltCallback : callback when the DMA transmission of linked list node buffer is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+    For specific callbacks TransceiverCallback use dedicated unregister callbacks:
+    respectively HAL_SD_UnRegisterTransceiverCallback().
+
+    By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (overridden) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (overridden) functions in the HAL_SD_Init
+    and HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+    or HAL_SD_Init function.
+
+    When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SD
+  * @{
+  */
+
+#if defined (SDMMC1) || defined (SDMMC2)
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SD_Private_Defines
+  * @{
+  */
+/* Frequencies used in the driver for clock divider calculation */
+#define SD_INIT_FREQ                   400000U   /* Initialization phase : 400 kHz max */
+#define SD_NORMAL_SPEED_FREQ           25000000U /* Normal speed phase : 25 MHz max */
+#define SD_HIGH_SPEED_FREQ             50000000U /* High speed phase : 50 MHz max */
+/* Private macro -------------------------------------------------------------*/
+#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)?  \
+                                              DLYB_SDMMC1 : DLYB_SDMMC2 )
+#elif defined (DLYB_SDMMC1)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
+#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void     SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void     SD_Write_IT(SD_HandleTypeDef *hsd);
+static void     SD_Read_IT(SD_HandleTypeDef *hsd);
+static uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode);
+#if (USE_SD_TRANSCEIVER != 0U)
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode);
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
+#endif /* USE_SD_TRANSCEIVER */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SD_Exported_Functions_Group1
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize the SD
+    card device to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SD according to the specified parameters in the
+            SD_HandleTypeDef and create the associated handle.
+  * @param  hsd: Pointer to the SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStatusTypeDef CardStatus;
+  uint32_t speedgrade;
+  uint32_t unitsize;
+  uint32_t tickstart;
+
+  /* Check the SD handle allocation */
+  if (hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+  assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
+
+  if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsd->Lock = HAL_UNLOCKED;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+    /* Force  SDMMC_TRANSCEIVER_PRESENT for Legacy usage */
+    if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_UNKNOWN)
+    {
+      hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT;
+    }
+#endif /*USE_SD_TRANSCEIVER */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+    hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
+    hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
+    hsd->ErrorCallback     = HAL_SD_ErrorCallback;
+    hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+    hsd->Read_DMALnkLstBufCpltCallback  = HAL_SDEx_Read_DMALnkLstBufCpltCallback;
+    hsd->Write_DMALnkLstBufCpltCallback = HAL_SDEx_Write_DMALnkLstBufCpltCallback;
+#if (USE_SD_TRANSCEIVER != 0U)
+    if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+    {
+      hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+    }
+#endif /* USE_SD_TRANSCEIVER */
+
+    if (hsd->MspInitCallback == NULL)
+    {
+      hsd->MspInitCallback = HAL_SD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hsd->MspInitCallback(hsd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SD_MspInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  hsd->State = HAL_SD_STATE_PROGRAMMING;
+
+  /* Initialize the Card parameters */
+  if (HAL_SD_InitCard(hsd) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Get Initial Card Speed from Card Status*/
+  speedgrade = CardStatus.UhsSpeedGrade;
+  unitsize = CardStatus.UhsAllocationUnitSize;
+  if ((hsd->SdCard.CardType == CARD_SDHC_SDXC) && ((speedgrade != 0U) || (unitsize != 0U)))
+  {
+    hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
+  }
+  else
+  {
+    if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+    {
+      hsd->SdCard.CardSpeed  = CARD_HIGH_SPEED;
+    }
+    else
+    {
+      hsd->SdCard.CardSpeed  = CARD_NORMAL_SPEED;
+    }
+
+  }
+  /* Configure the bus wide */
+  if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Verify that SD card is ready to use after Initialization */
+  tickstart = HAL_GetTick();
+  while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+  {
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the error code */
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  /* Initialize the SD state */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SD Card.
+  * @param  hsd: Pointer to SD handle
+  * @note   This function initializes the SD card. It could be used when a card
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  SD_InitTypeDef Init;
+  uint32_t sdmmc_clk;
+
+  /* Default SDMMC peripheral configuration for SD card initialization */
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+
+  /* Init Clock should be less or equal to 400Khz*/
+  if (hsd->Instance == SDMMC1)
+  {
+    sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+  }
+  else if (hsd->Instance == SDMMC2)
+  {
+    sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2);
+  }
+  else
+  {
+    sdmmc_clk = 0;
+  }
+  if (sdmmc_clk == 0U)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+    return HAL_ERROR;
+  }
+  Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+
+  if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+  {
+    /* Set Transceiver polarity */
+    hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+  }
+#elif defined (USE_SD_DIRPOL)
+  /* Set Transceiver polarity */
+  hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+#endif /* USE_SD_TRANSCEIVER  */
+
+  /* Initialize SDMMC peripheral interface with default configuration */
+  (void)SDMMC_Init(hsd->Instance, Init);
+
+  /* Set Power State to ON */
+  (void)SDMMC_PowerState_ON(hsd->Instance);
+
+  /* wait 74 Cycles: required power up waiting time before starting
+     the SD initialization sequence */
+  if (Init.ClockDiv != 0U)
+  {
+    sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+  }
+
+  if (sdmmc_clk != 0U)
+  {
+    HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+  }
+
+  /* Identify card operating voltage */
+  errorstate = SD_PowerON(hsd);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Card initialization */
+  errorstate = SD_InitCard(hsd);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the SD card.
+  * @param  hsd: Pointer to SD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if (hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  /* Deactivate the 1.8V Mode */
+  if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+  {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    if (hsd->DriveTransceiver_1_8V_Callback == NULL)
+    {
+      hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+    }
+    hsd->DriveTransceiver_1_8V_Callback(RESET);
+#else
+    HAL_SD_DriveTransceiver_1_8V_Callback(RESET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+#endif /* USE_SD_TRANSCEIVER   */
+
+  /* Set SD power state to off */
+  SD_PowerOFF(hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  if (hsd->MspDeInitCallback == NULL)
+  {
+    hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsd->MspDeInitCallback(hsd);
+#else
+  /* De-Initialize the MSP layer */
+  HAL_SD_MspDeInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+  hsd->State = HAL_SD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SD MSP.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group2
+  *  @brief   Data transfer functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the data
+    transfer from/to SD card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+                                    uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= BLOCKSIZE;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Read block(s) in polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Poll on SDMMC flags */
+    dataremaining = config.DataLength;
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = SDMMC_ReadFIFO(hsd->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    /* Send stop transmission command in case of multiblock read */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if (hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Allows to write block(s) to a specified address in a card. The Data
+  *         transfer is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t add = BlockAdd;
+  const uint8_t *tempbuff = pData;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= BLOCKSIZE;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE))
+      {
+        /* Write data to SDMMC Tx FIFO */
+        for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+        {
+          data = (uint32_t)(*tempbuff);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 8U);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 16U);
+          tempbuff++;
+          data |= ((uint32_t)(*tempbuff) << 24U);
+          tempbuff++;
+          (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+        }
+        dataremaining -= SDMMC_FIFO_SIZE;
+      }
+
+      if (((HAL_GetTick() - tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    /* Send stop transmission command in case of multiblock write */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+    {
+      if (hsd->SdCard.CardType != CARD_SECURED)
+      {
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get error state */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                       uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pRxBuffPtr = pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= BLOCKSIZE;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Read Blocks in IT mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+                             SDMMC_FLAG_RXFIFOHF));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pTxBuffPtr = pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= BLOCKSIZE;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+                             SDMMC_FLAG_TXFIFOHE));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pRxBuffPtr = pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= BLOCKSIZE;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+    hsd->Instance->IDMABASER = (uint32_t) pData ;
+    hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+    /* Read Blocks in DMA mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if (NULL == pData)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pTxBuffPtr = pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= BLOCKSIZE;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    hsd->Instance->IDMABASER = (uint32_t) pData ;
+    hsd->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+
+    /* Write Blocks in Polling mode */
+    if (NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Erases the specified memory area of the given SD card.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  BlockStartAdd: Start Block address
+  * @param  BlockEndAdd: End Block address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+  uint32_t errorstate;
+  uint32_t start_add = BlockStartAdd;
+  uint32_t end_add = BlockEndAdd;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if (end_add < start_add)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      return HAL_ERROR;
+    }
+
+    if (end_add > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Check if the card command class supports erase command */
+    if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Get start and end block for high capacity cards */
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      start_add *= BLOCKSIZE;
+      end_add   *= BLOCKSIZE;
+    }
+
+    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+    if (hsd->SdCard.CardType != CARD_SECURED)
+    {
+      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
+      if (errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+
+      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
+      if (errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Send CMD38 ERASE */
+    errorstate = SDMMC_CmdErase(hsd->Instance, 0UL);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  uint32_t context = hsd->Context;
+
+  /* Check for SDMMC interrupt flags */
+  if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Read_IT(hsd);
+  }
+
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
+
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                        SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE | \
+                        SDMMC_IT_RXFIFOHF);
+
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    if ((context & SD_CONTEXT_IT) != 0U)
+    {
+      if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else if ((context & SD_CONTEXT_DMA) != 0U)
+    {
+      hsd->Instance->DLEN = 0;
+      hsd->Instance->DCTRL = 0;
+      hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+      /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+      if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Write_IT(hsd);
+  }
+
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR |
+                             SDMMC_FLAG_TXUNDERR) != RESET)
+  {
+    /* Set Error code */
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+    }
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+    }
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+    }
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+    }
+
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Disable all interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                        SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+    hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+    hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+    hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
+
+    if ((context & SD_CONTEXT_IT) != 0U)
+    {
+      /* Set the SD state to ready to be able to start again the process */
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+    else if ((context & SD_CONTEXT_DMA) != 0U)
+    {
+      if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+      {
+        /* Disable Internal DMA */
+        __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
+        hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+        /* Set the SD state to ready to be able to start again the process */
+        hsd->State = HAL_SD_STATE_READY;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->ErrorCallback(hsd);
+#else
+        HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
+
+    if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->Write_DMALnkLstBufCpltCallback(hsd);
+#else
+      HAL_SDEx_Write_DMALnkLstBufCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+    else /* SD_CONTEXT_READ_MULTIPLE_BLOCK */
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->Read_DMALnkLstBufCpltCallback(hsd);
+#else
+      HAL_SDEx_Read_DMALnkLstBufCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief return the SD state
+  * @param hsd: Pointer to sd handle
+  * @retval HAL state
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd)
+{
+  return hsd->State;
+}
+
+/**
+  * @brief  Return the SD error code
+  * @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval SD Error Code
+  */
+uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd)
+{
+  return hsd->ErrorCode;
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: Pointer to SD handle
+  * @retval None
+  */
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD error callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_AbortCallback can be implemented in the user file
+   */
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+  * @brief  Enable/Disable the SD Transceiver 1.8V Mode Callback.
+  * @param  status: Voltage Switch State
+  * @retval None
+  */
+__weak  void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(status);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_EnableTransceiver could be implemented in the user file
+   */
+}
+#endif /* USE_SD_TRANSCEIVER  */
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SD Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @note   The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in
+  *         HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID
+  *         and HAL_SD_MSP_DEINIT_CB_ID.
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID                 SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID                 SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID                   SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID                   SD Abort Callback ID
+  *          @arg @ref HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID  SD DMA Rx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Tx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID                SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID              SD MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+                                          pSD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_TX_CPLT_CB_ID :
+        hsd->TxCpltCallback = pCallback;
+        break;
+      case HAL_SD_RX_CPLT_CB_ID :
+        hsd->RxCpltCallback = pCallback;
+        break;
+      case HAL_SD_ERROR_CB_ID :
+        hsd->ErrorCallback = pCallback;
+        break;
+      case HAL_SD_ABORT_CB_ID :
+        hsd->AbortCpltCallback = pCallback;
+        break;
+      case HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hsd->Read_DMALnkLstBufCpltCallback = pCallback;
+        break;
+      case HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hsd->Write_DMALnkLstBufCpltCallback = pCallback;
+        break;
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = pCallback;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = pCallback;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SD Callback
+  *         SD Callback is redirected to the weak (overridden) predefined callback
+  * @note   The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in
+  *         HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID
+  *         and HAL_SD_MSP_DEINIT_CB_ID.
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID                 SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID                 SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID                   SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID                   SD Abort Callback ID
+  *          @arg @ref HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID  SD DMA Rx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID SD DMA Tx Linked List Node buffer Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID                SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID              SD MspDeInit Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_TX_CPLT_CB_ID :
+        hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+        break;
+      case HAL_SD_RX_CPLT_CB_ID :
+        hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+        break;
+      case HAL_SD_ERROR_CB_ID :
+        hsd->ErrorCallback = HAL_SD_ErrorCallback;
+        break;
+      case HAL_SD_ABORT_CB_ID :
+        hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+        break;
+      case HAL_SD_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hsd->Read_DMALnkLstBufCpltCallback = HAL_SDEx_Read_DMALnkLstBufCpltCallback;
+        break;
+      case HAL_SD_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
+        hsd->Write_DMALnkLstBufCpltCallback = HAL_SDEx_Write_DMALnkLstBufCpltCallback;
+        break;
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = HAL_SD_MspInit;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsd->State == HAL_SD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SD_MSP_INIT_CB_ID :
+        hsd->MspInitCallback = HAL_SD_MspInit;
+        break;
+      case HAL_SD_MSP_DEINIT_CB_ID :
+        hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+  * @brief  Register a User SD Transceiver Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @param hsd : SD handle
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->DriveTransceiver_1_8V_Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SD Transceiver Callback
+  *         SD Callback is redirected to the weak (overridden) predefined callback
+  * @param hsd : SD handle
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+#endif /* USE_SD_TRANSCEIVER */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group3
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the SD card
+    operations and get the related information
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CID register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
+  *         contains all CID register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+{
+  pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+  pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+  pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+  pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+  pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+  pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+  pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+  pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+  pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
+  pCID->Reserved2 = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CSD register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+  *         contains all CSD register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+
+  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+  pCSD->Reserved2 = 0U; /*!< Reserved */
+
+  if (hsd->SdCard.CardType == CARD_SDSC)
+  {
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
+
+    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+    hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / BLOCKSIZE);
+    hsd->SdCard.LogBlockSize = BLOCKSIZE;
+  }
+  else if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
+  {
+    /* Byte 7 */
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+    hsd->SdCard.BlockSize = BLOCKSIZE;
+    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+
+  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+  pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+  pCSD->Reserved3 = 0;
+
+  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+  pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
+  pCSD->Reserved4 = 1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Gets the SD status info.( shall be called if there is no SD transaction ongoing )
+  * @param  hsd: Pointer to SD handle
+  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+  uint32_t sd_status[16];
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hsd->State == HAL_SD_STATE_BUSY)
+  {
+    return HAL_ERROR;
+  }
+
+  errorstate = SD_SendSDStatus(hsd, sd_status);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
+
+    pStatus->UhsSpeedGrade = (uint8_t)((sd_status[3] & 0x00F0U) >> 4U);
+    pStatus->UhsAllocationUnitSize = (uint8_t)(sd_status[3] & 0x000FU) ;
+    pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode = errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Gets the SD card info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by
+  *         card.
+  * @param  hsd: Pointer to SD handle
+  * @param  WideMode: Specifies the SD card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
+{
+  SDMMC_InitTypeDef Init;
+  uint32_t errorstate;
+  uint32_t sdmmc_clk;
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_BUS_WIDE(WideMode));
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    if (WideMode == SDMMC_BUS_WIDE_8B)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_4B)
+    {
+      errorstate = SD_WideBus_Enable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else if (WideMode == SDMMC_BUS_WIDE_1B)
+    {
+      errorstate = SD_WideBus_Disable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    }
+  }
+  else
+  {
+    /* SD Card does not support this feature */
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hsd->Instance == SDMMC1)
+    {
+      sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+    }
+    else
+    {
+      sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2);
+    }
+    if (sdmmc_clk != 0U)
+    {
+      /* Configure the SDMMC peripheral */
+      Init.ClockEdge           = hsd->Init.ClockEdge;
+      Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+      Init.BusWide             = WideMode;
+      Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+
+      /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
+      if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
+      {
+        Init.ClockDiv = hsd->Init.ClockDiv;
+      }
+      else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+      {
+        /* UltraHigh speed SD card,user Clock div */
+        Init.ClockDiv = hsd->Init.ClockDiv;
+      }
+      else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+      {
+        /* High speed SD card, Max Frequency = 50Mhz */
+        if (hsd->Init.ClockDiv == 0U)
+        {
+          if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+        else
+        {
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+      }
+      else
+      {
+        /* No High speed SD card, Max Frequency = 25Mhz */
+        if (hsd->Init.ClockDiv == 0U)
+        {
+          if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+        else
+        {
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+          {
+            Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+          }
+          else
+          {
+            Init.ClockDiv = hsd->Init.ClockDiv;
+          }
+        }
+      }
+
+#if (USE_SD_TRANSCEIVER != 0U)
+      Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+#endif /* USE_SD_TRANSCEIVER */
+
+      (void)SDMMC_Init(hsd->Instance, Init);
+    }
+    else
+    {
+      hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER;
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    status = HAL_ERROR;
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return status;
+}
+
+/**
+  * @brief  Configure the speed bus mode
+  * @param  hsd: Pointer to the SD handle
+  * @param  SpeedMode: Specifies the SD card speed bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
+  *            @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed/SDR12 mode
+  *            @arg SDMMC_SPEED_MODE_HIGH: High Speed/SDR25 mode
+  *            @arg SDMMC_SPEED_MODE_ULTRA: Ultra high speed mode
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode)
+{
+  uint32_t tickstart;
+  uint32_t errorstate;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+
+#if (USE_SD_TRANSCEIVER != 0U)
+  if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+  {
+    switch (SpeedMode)
+    {
+      case SDMMC_SPEED_MODE_AUTO:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+          /* Enable Ultra High Speed */
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+            {
+              hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+              status = HAL_ERROR;
+            }
+          }
+        }
+        else if (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED)
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /*Nothing to do, Use defaultSpeed */
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_ULTRA_SDR104:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable UltraHigh Speed */
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+          hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_ULTRA_SDR50:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable UltraHigh Speed */
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR50_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+          hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_DDR:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable DDR Mode*/
+          if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+          hsd->Instance->CLKCR |=  SDMMC_CLKCR_BUSSPEED | SDMMC_CLKCR_DDR;
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_HIGH:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_DEFAULT:
+      {
+        /* Switch to default Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+
+        break;
+      }
+      default:
+        hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    switch (SpeedMode)
+    {
+      case SDMMC_SPEED_MODE_AUTO:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          /*Nothing to do, Use defaultSpeed */
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_HIGH:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable High Speed */
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_DEFAULT:
+      {
+        /* Switch to default Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+
+        break;
+      }
+      case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+      default:
+        hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+        status = HAL_ERROR;
+        break;
+    }
+  }
+#else
+  switch (SpeedMode)
+  {
+    case SDMMC_SPEED_MODE_AUTO:
+    {
+      if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+          (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+          (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+      {
+        /* Enable High Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /*Nothing to do, Use defaultSpeed */
+      }
+      break;
+    }
+    case SDMMC_SPEED_MODE_HIGH:
+    {
+      if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+          (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED) ||
+          (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+      {
+        /* Enable High Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+        status = HAL_ERROR;
+      }
+      break;
+    }
+    case SDMMC_SPEED_MODE_DEFAULT:
+    {
+      /* Switch to default Speed */
+      if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+        status = HAL_ERROR;
+      }
+
+      break;
+    }
+    case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+    default:
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      status = HAL_ERROR;
+      break;
+  }
+#endif /* USE_SD_TRANSCEIVER */
+
+  /* Verify that SD card is ready to use after Speed mode switch*/
+  tickstart = HAL_GetTick();
+  while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+  {
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set Block Size for Card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    status = HAL_ERROR;
+  }
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+  return status;
+}
+
+/**
+  * @brief  Gets the current sd card data state.
+  * @param  hsd: pointer to SD handle
+  * @retval Card state
+  */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+  uint32_t cardstate;
+  uint32_t errorstate;
+  uint32_t resp1 = 0;
+
+  errorstate = SD_SendStatus(hsd, &resp1);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= errorstate;
+  }
+
+  cardstate = ((resp1 >> 9U) & 0x0FU);
+
+  return (HAL_SD_CardStateTypeDef)cardstate;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
+{
+  uint32_t error_code;
+  uint32_t tickstart;
+
+  if (hsd->State == HAL_SD_STATE_BUSY)
+  {
+    /* DIsable All interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                        SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    /*we will send the CMD12 in all cases in order to stop the data transfers*/
+    /*In case the data transfer just finished , the external memory will not respond
+      and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/
+    /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/
+    /*Other scenario will return HAL_ERROR*/
+
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+    error_code = hsd->ErrorCode;
+    if ((error_code != HAL_SD_ERROR_NONE) && (error_code != HAL_SD_ERROR_CMD_RSP_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+
+    tickstart = HAL_GetTick();
+    if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
+    {
+      if (hsd->ErrorCode == HAL_SD_ERROR_NONE)
+      {
+        while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
+        {
+          if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+          {
+            hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+            hsd->State = HAL_SD_STATE_READY;
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+
+      if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT)
+      {
+        while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND))
+        {
+          if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+          {
+            hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+            hsd->State = HAL_SD_STATE_READY;
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
+    {
+      while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
+      {
+        if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+        {
+          hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+          hsd->State = HAL_SD_STATE_READY;
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do*/
+    }
+
+    /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear
+      the appropriate flags that will be set depending of the abort/non abort of the memory */
+    /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared
+      and will result in next SDMMC read/write operation to fail */
+
+    /*SDMMC ready for clear data flags*/
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END);
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+    /* If IDMA Context, disable Internal DMA */
+    hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    /* Initialize the SD operation */
+    hsd->Context = SD_CONTEXT_NONE;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the current transfer and disable the SD (IT mode).
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Disable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                      SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+
+  /* If IDMA Context, disable Internal DMA */
+  hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+
+  if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+
+  if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the sd card.
+  * @param  hsd: Pointer to SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardCSDTypeDef CSD;
+  uint32_t errorstate;
+  uint16_t sd_rca = 0U;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the power State */
+  if (SDMMC_GetPowerState(hsd->Instance) == 0U)
+  {
+    /* Power off */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD2 ALL_SEND_CID */
+    errorstate = SDMMC_CmdSendCID(hsd->Instance);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card identification number data */
+      hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    while (sd_rca == 0U)
+    {
+      errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+      if (errorstate != HAL_SD_ERROR_NONE)
+      {
+        return errorstate;
+      }
+      if ((HAL_GetTick() - tickstart) >=  SDMMC_CMDTIMEOUT)
+      {
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+  }
+  if (hsd->SdCard.CardType != CARD_SECURED)
+  {
+    /* Get the SD card RCA */
+    hsd->SdCard.RelCardAdd = sd_rca;
+
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card Specific Data */
+      hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+      hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);
+      hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);
+      hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);
+    }
+  }
+
+  /* Get the Card Class */
+  hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U);
+
+  /* Get CSD parameters */
+  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+  {
+    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+  }
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* All cards are initialized */
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores SD information that will be needed in future
+  *         in the SD handle.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+  __IO uint32_t count = 0U;
+  uint32_t response = 0U;
+  uint32_t validvoltage = 0U;
+  uint32_t errorstate;
+#if (USE_SD_TRANSCEIVER != 0U)
+  uint32_t tickstart = HAL_GetTick();
+#endif /* USE_SD_TRANSCEIVER  */
+
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+  errorstate = SDMMC_CmdOperCond(hsd->Instance);
+  if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */
+  {
+    hsd->SdCard.CardVersion = CARD_V1_X;
+    /* CMD0: GO_IDLE_STATE */
+    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+  }
+  else
+  {
+    hsd->SdCard.CardVersion = CARD_V2_X;
+  }
+
+  if (hsd->SdCard.CardVersion == CARD_V2_X)
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+  }
+  /* SD CARD */
+  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+  while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+  {
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send CMD41 */
+    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY |
+                                         SD_SWITCH_1_8V_CAPACITY);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+    /* Get command response */
+    response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+    /* Get operating voltage*/
+    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+    count++;
+  }
+
+  if (count >= SDMMC_MAX_VOLT_TRIAL)
+  {
+    return HAL_SD_ERROR_INVALID_VOLTRANGE;
+  }
+
+  /* Set default card type */
+  hsd->SdCard.CardType = CARD_SDSC;
+
+  if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY)
+  {
+    hsd->SdCard.CardType = CARD_SDHC_SDXC;
+#if (USE_SD_TRANSCEIVER != 0U)
+    if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+    {
+      if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
+      {
+        hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
+
+        /* Start switching procedue */
+        hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
+
+        /* Send CMD11 to switch 1.8V mode */
+        errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
+        if (errorstate != HAL_SD_ERROR_NONE)
+        {
+          return errorstate;
+        }
+
+        /* Check to CKSTOP */
+        while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
+        {
+          if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+          {
+            return HAL_SD_ERROR_TIMEOUT;
+          }
+        }
+
+        /* Clear CKSTOP Flag */
+        hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
+
+        /* Check to BusyD0 */
+        if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
+        {
+          /* Error when activate Voltage Switch in SDMMC Peripheral */
+          return SDMMC_ERROR_UNSUPPORTED_FEATURE;
+        }
+        else
+        {
+          /* Enable Transceiver Switch PIN */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+          HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+          /* Switch ready */
+          hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
+
+          /* Check VSWEND Flag */
+          while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
+          {
+            if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+            {
+              return HAL_SD_ERROR_TIMEOUT;
+            }
+          }
+
+          /* Clear VSWEND Flag */
+          hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
+
+          /* Check BusyD0 status */
+          if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
+          {
+            /* Error when enabling 1.8V mode */
+            return HAL_SD_ERROR_INVALID_VOLTRANGE;
+          }
+          /* Switch to 1.8V OK */
+
+          /* Disable VSWITCH FLAG from SDMMC Peripheral */
+          hsd->Instance->POWER = 0x13U;
+
+          /* Clean Status flags */
+          hsd->Instance->ICR = 0xFFFFFFFFU;
+        }
+      }
+    }
+#endif /* USE_SD_TRANSCEIVER  */
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Turns the SDMMC output signals off.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
+  */
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
+{
+  /* Set Power State to OFF */
+  (void)SDMMC_PowerState_OFF(hsd->Instance);
+}
+
+/**
+  * @brief  Send Status info command.
+  * @param  hsd: pointer to SD handle
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
+  *         SD Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count = 0;
+  uint32_t *pData = pSDstatus;
+
+  /* Check SD response */
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Set block size for card if it is not equal to current block size for card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Send CMD55 */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Configure the SD DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 64U;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+    return errorstate;
+  }
+
+  /* Get status data */
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+  {
+    if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (count < 16U))
+    {
+      *pData = SDMMC_ReadFIFO(hsd->Instance);
+      pData++;
+      count++;
+    }
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DPSMACT)))
+  {
+    *pData = SDMMC_ReadFIFO(hsd->Instance);
+    pData++;
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  /* Clear all the static status flags*/
+  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card
+  *         status (Card Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+  uint32_t errorstate;
+
+  if (pCardStatus == NULL)
+  {
+    return HAL_SD_ERROR_PARAM;
+  }
+
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Get SD card status */
+  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enables the SDMMC wide bus mode.
+  * @param  hsd: pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0UL, 0UL};
+  uint32_t errorstate;
+
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports wide bus operation */
+  if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA.*/
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+/**
+  * @brief  Disables the SDMMC wide bus mode.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+{
+  uint32_t scr[2U] = {0UL, 0UL};
+  uint32_t errorstate;
+
+  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+  {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+  }
+
+  /* Get SCR Register */
+  errorstate = SD_FindSCR(hsd, scr);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* If requested card supports 1 bit mode operation */
+  if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+  {
+    /* Send CMD55 APP_CMD with argument as card's RCA */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    return HAL_SD_ERROR_NONE;
+  }
+  else
+  {
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+}
+
+/**
+  * @brief  Finds the SD card SCR register value.
+  * @param  hsd: Pointer to SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value
+  * @retval error state
+  */
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t index = 0U;
+  uint32_t tempscr[2U] = {0UL, 0UL};
+  uint32_t *scr = pSCR;
+
+  /* Set Block Size To 8 Bytes */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  /* Send CMD55 APP_CMD with argument as card's RCA */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 8U;
+  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDMMC_DPSM_ENABLE;
+  (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+  if (errorstate != HAL_SD_ERROR_NONE)
+  {
+    return errorstate;
+  }
+
+  while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                            SDMMC_FLAG_DATAEND))
+  {
+    if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
+    {
+      tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
+      tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
+      index++;
+    }
+
+    if ((HAL_GetTick() - tickstart) >=  SDMMC_SWDATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+    return HAL_SD_ERROR_DATA_TIMEOUT;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
+  }
+  else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+  {
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+    return HAL_SD_ERROR_RX_OVERRUN;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24U)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8U) | \
+            ((tempscr[1] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24U));
+    scr++;
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24U)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8U) | \
+            ((tempscr[0] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24U));
+
+  }
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Wrap up reading in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count;
+  uint32_t data;
+  uint8_t *tmp;
+
+  tmp = hsd->pRxBuffPtr;
+
+  if (hsd->RxXferSize >= SDMMC_FIFO_SIZE)
+  {
+    /* Read data from SDMMC Rx FIFO */
+    for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+    {
+      data = SDMMC_ReadFIFO(hsd->Instance);
+      *tmp = (uint8_t)(data & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+      tmp++;
+      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+      tmp++;
+    }
+
+    hsd->pRxBuffPtr = tmp;
+    hsd->RxXferSize -= SDMMC_FIFO_SIZE;
+  }
+}
+
+/**
+  * @brief  Wrap up writing in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count;
+  uint32_t data;
+  const uint8_t *tmp;
+
+  tmp = hsd->pTxBuffPtr;
+
+  if (hsd->TxXferSize >= SDMMC_FIFO_SIZE)
+  {
+    /* Write data to SDMMC Tx FIFO */
+    for (count = 0U; count < (SDMMC_FIFO_SIZE / 4U); count++)
+    {
+      data = (uint32_t)(*tmp);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 8U);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 16U);
+      tmp++;
+      data |= ((uint32_t)(*tmp) << 24U);
+      tmp++;
+      (void)SDMMC_WriteFIFO(hsd->Instance, &data);
+    }
+
+    hsd->pTxBuffPtr = tmp;
+    hsd->TxXferSize -= SDMMC_FIFO_SIZE;
+  }
+}
+
+/**
+  * @brief  Switches the SD card to High Speed mode.
+  *         This API must be used after "Transfer State"
+  * @note   This operation should be followed by the configuration
+  *         of PLL to have SDMMCCK clock between 25 and 50 MHz
+  * @param  hsd: SD handle
+  * @param  SwitchSpeedMode: SD speed mode( SDMMC_SDR12_SWITCH_PATTERN, SDMMC_SDR25_SWITCH_PATTERN)
+  * @retval SD Card error state
+  */
+uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+  uint32_t SD_hs[16]  = {0};
+  uint32_t count = 0;
+  uint32_t Timeout = HAL_GetTick();
+
+  if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+  {
+    /* Standard Speed Card <= 12.5Mhz  */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardSpeed >= CARD_HIGH_SPEED)
+  {
+    /* Initialize the Data control register */
+    hsd->Instance->DCTRL = 0;
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
+    sdmmc_datainitstructure.DataLength    = 64U;
+    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
+
+    (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
+
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (count < 16U))
+      {
+        SD_hs[count]  = SDMMC_ReadFIFO(hsd->Instance);
+        count++;
+      }
+      if ((HAL_GetTick() - Timeout) >=  SDMMC_SWDATATIMEOUT)
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+      errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+      errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+      return errorstate;
+    }
+    else
+    {
+      /* No error flag set */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Test if the switch mode HS is ok */
+    if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+    {
+      errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+  }
+
+  return errorstate;
+}
+
+#if (USE_SD_TRANSCEIVER != 0U)
+/**
+  * @brief  Switches the SD card to Ultra High Speed mode.
+  *         This API must be used after "Transfer State"
+  * @note   This operation should be followed by the configuration
+  *         of PLL to have SDMMCCK clock between 50 and 120 MHz
+  * @param  hsd: SD handle
+  * @param  UltraHighSpeedMode: SD speed mode( SDMMC_SDR50_SWITCH_PATTERN, SDMMC_SDR104_SWITCH_PATTERN)
+  * @retval SD Card error state
+  */
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+  uint32_t SD_hs[16]  = {0};
+  uint32_t count;
+  uint32_t loop = 0 ;
+  uint32_t Timeout = HAL_GetTick();
+
+  if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+  {
+    /* Standard Speed Card <= 12.5Mhz  */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+  {
+    /* Initialize the Data control register */
+    hsd->Instance->DCTRL = 0;
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
+    sdmmc_datainitstructure.DataLength    = 64U;
+    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
+
+    if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+    {
+      return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+    }
+
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, UltraHighSpeedMode);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+      {
+        for (count = 0U; count < 8U; count++)
+        {
+          SD_hs[(8U * loop) + count]  = SDMMC_ReadFIFO(hsd->Instance);
+        }
+        loop ++;
+      }
+
+      if ((HAL_GetTick() - Timeout) >=  SDMMC_SWDATATIMEOUT)
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+      errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+      errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+      return errorstate;
+    }
+    else
+    {
+      /* No error flag set */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Test if the switch mode HS is ok */
+    if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+    {
+      errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+      HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
+      /* Enable DelayBlock Peripheral */
+      /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
+      MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1);
+      LL_DLYB_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance));
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+    }
+  }
+
+  return errorstate;
+}
+
+/**
+  * @brief  Switches the SD card to Double Data Rate (DDR) mode.
+  *         This API must be used after "Transfer State"
+  * @note   This operation should be followed by the configuration
+  *         of PLL to have SDMMCCK clock less than 50MHz
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate = HAL_SD_ERROR_NONE;
+  SDMMC_DataInitTypeDef sdmmc_datainitstructure;
+  uint32_t SD_hs[16]  = {0};
+  uint32_t count;
+  uint32_t loop = 0 ;
+  uint32_t Timeout = HAL_GetTick();
+
+  if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+  {
+    /* Standard Speed Card <= 12.5Mhz  */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+  }
+
+  if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+  {
+    /* Initialize the Data control register */
+    hsd->Instance->DCTRL = 0;
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    sdmmc_datainitstructure.DataTimeOut   = SDMMC_DATATIMEOUT;
+    sdmmc_datainitstructure.DataLength    = 64U;
+    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
+    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;
+
+    if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+    {
+      return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
+    }
+
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+                              SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+      {
+        for (count = 0U; count < 8U; count++)
+        {
+          SD_hs[(8U * loop) + count]  = SDMMC_ReadFIFO(hsd->Instance);
+        }
+        loop ++;
+      }
+
+      if ((HAL_GetTick() - Timeout) >=  SDMMC_SWDATATIMEOUT)
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_SD_ERROR_TIMEOUT;
+      }
+    }
+
+    if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
+
+      errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
+
+      return errorstate;
+    }
+    else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+    {
+      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
+
+      errorstate = SDMMC_ERROR_RX_OVERRUN;
+
+      return errorstate;
+    }
+    else
+    {
+      /* No error flag set */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    /* Test if the switch mode  is ok */
+    if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
+    {
+      errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->DriveTransceiver_1_8V_Callback(SET);
+#else
+      HAL_SD_DriveTransceiver_1_8V_Callback(SET);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
+      /* Enable DelayBlock Peripheral */
+      /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */
+      MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0);
+      LL_DLYB_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance));
+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
+    }
+  }
+
+  return errorstate;
+}
+
+#endif /* USE_SD_TRANSCEIVER */
+
+/**
+  * @brief Read DMA Linked list node Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Read_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Read_DMALnkLstBufCpltCallback can be implemented in the user file
+   */
+}
+/**
+  * @brief Read DMA Linked list node Transfer completed callbacks
+  * @param hsd: SD handle
+  * @retval None
+  */
+__weak void HAL_SDEx_Write_DMALnkLstBufCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDEx_Write_DMALnkLstBufCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sd_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sd_ex.c
new file mode 100644
index 000000000..205a3042b
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sd_ex.c
@@ -0,0 +1,395 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sd_ex.c
+  * @author  MCD Application Team
+  * @brief   SD card Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital (SD) peripheral:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   The SD Extension HAL driver can be used as follows:
+   (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
+   (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer()
+       and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDEx SDEx
+  * @brief SD Extended HAL module driver
+  * @{
+  */
+
+#if defined (SDMMC1) || defined (SDMMC2)
+#ifdef HAL_SD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup SDEx_Exported_Functions_Group1
+  *  @brief   Linked List management functions
+  *
+@verbatim
+ ===============================================================================
+                   ##### Linked List management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Build Linked List node.
+  * @param  pNode: Pointer to new node to add.
+  * @param  pNodeConf: Pointer to configuration parameters for new node to add.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf)
+{
+
+  (void)SDMMC_DMALinkedList_BuildNode(pNode, pNodeConf);
+
+  return (HAL_OK);
+
+}
+
+/**
+  * @brief  Insert new Linked List node.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @param  pPrevNode: Pointer to previous node.
+  * @param  pNewNode: Pointer to new node to insert.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_InsertNode(SD_DMALinkedListTypeDef *pLinkedList,
+                                                    SD_DMALinkNodeTypeDef *pPrevNode, SD_DMALinkNodeTypeDef *pNewNode)
+{
+
+  (void)SDMMC_DMALinkedList_InsertNode(pLinkedList, pPrevNode, pNewNode);
+
+  return (HAL_OK);
+
+}
+/**
+  * @brief  Remove Linked List node.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @param  pNode: Pointer to node to remove.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_RemoveNode(SD_DMALinkedListTypeDef *pLinkedList, SD_DMALinkNodeTypeDef *pNode)
+{
+
+  if (SDMMC_DMALinkedList_RemoveNode(pLinkedList, pNode) != SDMMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Lock Linked List node.
+  * @param  pNode: Pointer to node to remove.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_LockNode(SD_DMALinkNodeTypeDef *pNode)
+{
+
+  if (SDMMC_DMALinkedList_LockNode(pNode) != SDMMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Unlock Linked List node.
+  * @param  pNode: Pointer to node to remove.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_UnlockNode(SD_DMALinkNodeTypeDef *pNode)
+{
+
+  if (SDMMC_DMALinkedList_UnlockNode(pNode) != SDMMC_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Enable Circular mode for DMA Linked List.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_EnableCircularMode(SD_DMALinkedListTypeDef *pLinkedList)
+{
+
+  (void)SDMMC_DMALinkedList_EnableCircularMode(pLinkedList);
+
+  return HAL_OK;
+
+}
+/**
+  * @brief  Disable Circular mode for DMA Linked List.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTypeDef *pLinkedList)
+{
+
+  (void)SDMMC_DMALinkedList_DisableCircularMode(pLinkedList);
+
+  return HAL_OK;
+
+}
+
+
+/**
+  * @brief  Reads block(s) from a specified address in a card. The received Data will be stored in linked list buffers.
+  *         linked list should be prepared before call this function .
+  * @param  hsd: SD handle
+  * @param  pLinkedList: pointer to first linked list node
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Total number of blocks to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd,
+                                                    const SDMMC_DMALinkedListTypeDef *pLinkedList,
+                                                    uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t DmaBase0_reg;
+  uint32_t DmaBase1_reg;
+  uint32_t add = BlockAdd;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+    hsd->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+
+    hsd->Instance->IDMABAR   = (uint32_t) pLinkedList->pHeadNode;
+    hsd->Instance->IDMALAR   = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+                               sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+    DmaBase0_reg = hsd->Instance->IDMABASER;
+    DmaBase1_reg = hsd->Instance->IDMABAR;
+
+    if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0;
+    /* Clear old Flags*/
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+    /* Read Blocks in DMA mode */
+    hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+    /* Read Multi Block command */
+    errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->ErrorCode |= errorstate;
+      return HAL_ERROR;
+    }
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+                             SDMMC_IT_IDMABTC));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}
+
+/**
+  * @brief  Write block(s) to a specified address in a card. The transferred Data are stored linked list nodes buffers .
+  *         linked list should be prepared before call this function .
+  * @param  hsd: SD handle
+  * @param  pLinkedList: pointer to first linked list node
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Total number of blocks to read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd,
+                                                     const SDMMC_DMALinkedListTypeDef *pLinkedList,
+                                                     uint32_t BlockAdd, uint32_t NumberOfBlocks)
+
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t DmaBase0_reg;
+  uint32_t DmaBase1_reg;
+  uint32_t add = BlockAdd;
+
+  if (hsd->State == HAL_SD_STATE_READY)
+  {
+    if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
+    hsd->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
+
+    hsd->Instance->IDMABAR = (uint32_t)  pLinkedList->pHeadNode;
+    hsd->Instance->IDMALAR = (uint32_t)  SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
+                             sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
+
+    DmaBase0_reg = hsd->Instance->IDMABASER;
+    DmaBase1_reg = hsd->Instance->IDMABAR;
+
+    if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
+    {
+      hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0;
+
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsd->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
+
+    hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+    /* Write Blocks in DMA mode */
+    hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+    /* Write Multi Block command */
+    errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    if (errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->ErrorCode |= errorstate;
+      return HAL_ERROR;
+    }
+
+    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+                             SDMMC_IT_IDMABTC));
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sdio.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sdio.c
new file mode 100644
index 000000000..6b2fa3c8a
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sdio.c
@@ -0,0 +1,2877 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sdio.c
+  * @author  MCD Application Team
+  * @brief   SDIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Secure Digital Input Output (SDIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver implements a high level communication layer for read and write from/to
+    this SDIO card. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+    the user in HAL_SDIO_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
+    examples.
+    You can easily tailor this configuration according to hardware resources.
+
+  [..]
+    This driver is a generic layered driver for SDMMC memories which uses the HAL
+    SDMMC driver functions to interface with SDIO cards devices.
+    It is used as follows:
+
+    (#)Initialize the SDMMC low level resources by implementing the HAL_SDIO_MspInit() API:
+        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+        (##) SDMMC pins configuration for SDIO card
+            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+                  and according to your pin assignment;
+        (##) NVIC configuration if you need to use interrupt process (HAL_SDIO_ReadExtended_DMA()
+             and HAL_SDIO_WriteExtended_DMA() APIs).
+            (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDMMC interrupts are managed using the macros __HAL_SDIO_ENABLE_IT()
+                  and __HAL_SDIO_DISABLE_IT() inside the communication process.
+            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SDIO_GET_IT().
+        (##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
+
+    (#) At this stage, you can perform SDIO read/write/erase operations after SDIO card initialization.
+
+  *** SDIO Card Initialization and configuration ***
+  ================================================
+  [..]
+    To initialize the SDIO Card, use the HAL_SDIO_Init() function. It Initializes
+    SDMMC Peripheral(STM32 side) and the SDIO Card, and put it into StandBy State (Ready for data transfer).
+    This function provide the following operations:
+
+    (#) Apply the SDIO Card initialization process at 400KHz. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        The SDIO Card frequency (SDMMC_CK) is computed as follows:
+
+           SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
+
+        In initialization mode and according to the SDIO Card standard,
+        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+        This phase of initialization is done through SDMMC_Init() and
+        SDMMC_PowerState_ON() SDMMC low level APIs.
+
+    (#) Initialize the SDIO card. The API used is HAL_SDIO_Init().
+        This phase allows the card initialization and identification.
+
+    (#) Configure the SDIO Card Data transfer frequency. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field by the API HAL_SDIO_ConfigFrequency().
+
+    (#) Configure the SDIO Card in wide bus mode: 4-bits data by the API HAL_SDIO_SetDataBusWidth().
+
+    (#) Configure the SDIO Card data block size by the API : HAL_SDIO_SetBlockSize().
+
+    (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode().
+
+    (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback
+        function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function.
+
+  *** SDIO Card Read operation ***
+  ==============================
+  [..]
+    (+) You can read from SDIO card in polling mode by using function HAL_SDIO_ReadExtended().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+
+    (+) You can read from SDIO card in DMA mode by using function HAL_SDIO_ReadExtended_DMA().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+        After this, you have to ensure that the transfer is done correctly.
+        You could also check the DMA transfer process through the SDIO Rx interrupt event.
+
+  *** SDIO Card Write operation ***
+  ===============================
+  [..]
+    (+) You can write to SDIO card in polling mode by using function HAL_SDIO_WriteExtended().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+
+    (+) You can write to SDIO card in DMA mode by using function HAL_SDIO_WriteExtended_DMA().
+        This function support only 2048-bytes block length (the block size should be
+        chosen by using the API HAL_SDIO_SetBlockSize).
+        You could also check the DMA transfer process through the SDIO Tx interrupt event.
+
+
+  *** SDIO card common control register (CCCR) ***
+  ======================
+  [..]
+    (+) The SDIO CCCR allow for quick host checking and control of an IO card's enable and interrupts on a per card and
+        per function basis.
+        To get the Card common control registers field, you can use the API HAL_SDIO_GetCardCommonControlRegister().
+
+  *** SDIO card Function basic register (FBR) ***
+  ===========================
+  [..]
+    (+) The SDIO card function basic register are used to allow the host to quickly determine the abilities and
+        requirements of each function.
+    (+) To get the SDIO function basic register information, you can use the API HAL_SDIO_GetCardFBRRegister().
+
+  *** SDIO HAL driver macros list ***
+  ==================================
+  [..]
+    Below the list of most used macros in SDIO HAL driver.
+
+    (+) __HAL_SDIO_ENABLE_IT: Enable the SDIO device interrupt
+    (+) __HAL_SDIO_DISABLE_IT: Disable the SDIO device interrupt
+    (+) __HAL_SDIO_GET_FLAG: Check whether the specified SDIO flag is set or not
+    (+) __HAL_SDIO_CLEAR_FLAG: Clear the SDIO's pending flags
+    (+) __HAL_SDIO_GET_IT: Check whether the specified SDIO interrupt has occurred or not
+    (+) __HAL_SDIO_GET_IT_SOURCE: Checks whether the specified SDIO interrupt is enabled or not
+
+    (@) You can refer to the SDIO HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_SDIO_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) MspInitCallback    : SDIO MspInit.
+      (+) MspDeInitCallback  : SDIO MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+    For specific callbacks TransceiverCallback use dedicated register callbacks:
+    respectively HAL_SDIO_RegisterTransceiverCallback().
+
+    Use function HAL_SDIO_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) MspInitCallback    : SDIO MspInit.
+      (+) MspDeInitCallback  : SDIO MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+    For specific callbacks TransceiverCallback use dedicated unregister callbacks:
+    respectively HAL_SDIO_UnRegisterTransceiverCallback().
+
+    By default, after the HAL_SDIO_Init and if the state is HAL_SDIO_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (overridden) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (overridden) functions in the HAL_SDIO_Init
+    and HAL_SDIO_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SDIO_Init and HAL_SDIO_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SDIO_RegisterCallback before calling HAL_SDIO_DeInit
+    or HAL_SDIO_Init function.
+
+    When The compilation define USE_HAL_SDIO_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (overridden) callbacks are used.
+
+  *** SDIO peripheral IO interrupt ***
+  =============================================
+  [..]
+  (+) Below the list of most used SDIO function to check and control the IO card's enable and interrupts on a per
+      functions basis.
+
+    (+) HAL_SDIO_EnableIOFunctionInterrupt: Enable SDIO IO interrupt.
+    (+) HAL_SDIO_DisableIOFunctionInterrupt: Disable SDIO IO interrupt.
+    (+) HAL_SDIO_EnableIOFunction: Enable Function number(0-7)
+    (+) HAL_SDIO_DisableIOFunction: Disable Function number(0-7)
+    (+) HAL_SDIO_SelectIOFunction: Select a function number(0-7)
+    (+) HAL_SDIO_AbortIOFunction: Abort an IO read or write operation and free the SDIO bus.
+    (+) HAL_SDIO_EnableIOAsynInterrupt: Enable Bit of asynchronous interrupt
+    (+) HAL_SDIO_DisableIOAsynInterrupt: Disable Bit of asynchronous interrupt
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+#if defined (SDMMC1) || defined (SDMMC2)
+#ifdef HAL_SDIO_MODULE_ENABLED
+
+/* Private define ----------------------------------------------------------------------------------------------------*/
+/** @addtogroup SDIO_Private_Defines
+  * @{
+  */
+#define SDIO_INIT_FREQ         400000U /*!< Initialization phase : 400 kHz max */
+#define SDIO_TIMEOUT           1000U   /*!< SDIO timeout millisecond           */
+
+#define SDIO_FUNCTION_0        0x00U   /*!< SDIO_Functions 0                   */
+#define SDIO_FUNCTION_1        0x01U   /*!< SDIO_Functions 1                   */
+
+#define SDIO_READ              0x0U    /*!< Read flag for cmd52 and cmd53      */
+#define SDIO_WRITE             0x1U    /*!< Write flag for cmd52 and cmd53     */
+
+#define SDIO_BUS_SPEED_SDR12   0x00U   /*!< SDIO bus speed mode SDR12          */
+#define SDIO_BUS_SPEED_SDR25   0x02U   /*!< SDIO bus speed mode SDR25          */
+#define SDIO_BUS_SPEED_SDR50   0x04U   /*!< SDIO bus speed mode SDR50          */
+#define SDIO_BUS_SPEED_DDR50   0x08U   /*!< SDIO bus speed mode DDR50          */
+
+#define SDIO_CCCR_REG_NUMBER   0x16U   /*!< SDIO card cccr register number     */
+
+#define SDIO_OCR_VDD_32_33     (1U << 20U)
+#define SDIO_OCR_SDIO_S18R     (1U << 24U)
+/**
+  * @}
+  */
+
+/* Private macro -----------------------------------------------------------------------------------------------------*/
+#define IS_SDIO_RAW_FLAG(ReadAfterWrite)   (((ReadAfterWrite) == HAL_SDIO_WRITE_ONLY) || \
+                                            ((ReadAfterWrite) == HAL_SDIO_READ_AFTER_WRITE))
+
+#define IS_SDIO_FUNCTION(FN)        (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7))
+
+#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE)    || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE)   || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE)   || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE)   || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE)  || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE)  || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE)  || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \
+                                                 ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE))
+
+/* Private functions -------------------------------------------------------------------------------------------------*/
+/** @defgroup SDIO_Private_Functions SDIO Private Functions
+  * @{
+  */
+static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio);
+static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr,
+                                         uint8_t *pData);
+static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr,
+                                          uint8_t *pData);
+static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg,
+                                            uint8_t *pData, uint16_t Size_byte);
+static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size);
+static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDIO_Exported_Functions
+  * @{
+  */
+/** @addtogroup SDIO_Exported_Functions_Group1
+  *  @brief   Initialization and de-initialization functions
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize the SDIO
+    device to be ready for use.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the SDIO according to the specified parameters in the
+            SDIO_HandleTypeDef and create the associated handle.
+  * @param  hsdio: Pointer to the SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio)
+{
+  SDIO_InitTypeDef Init;
+  uint32_t sdmmc_clk;
+  uint8_t data;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance));
+  assert_param(IS_SDMMC_CLOCK_EDGE(hsdio->Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsdio->Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(hsdio->Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsdio->Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(hsdio->Init.ClockDiv));
+
+  /* Check the SDIO handle allocation */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_RESET)
+  {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_SDIO_STATE_RESET only */
+    hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback;
+    hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback;
+    hsdio->ErrorCallback  = HAL_SDIO_ErrorCallback;
+#if (USE_SDIO_TRANSCEIVER != 0U)
+    if (hsdio->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
+    {
+      hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback;
+    }
+#endif /* USE_SDIO_TRANSCEIVER */
+
+    if (hsdio->MspInitCallback == NULL)
+    {
+      hsdio->MspInitCallback = HAL_SDIO_MspInit;
+    }
+    /* Init the low level hardware */
+    hsdio->MspInitCallback(hsdio);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SDIO_MspInit(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+  }
+
+  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;
+  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDMMC_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+
+  sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+  if (sdmmc_clk == 0U)
+  {
+    hsdio->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+    return HAL_ERROR;
+  }
+  Init.ClockDiv = sdmmc_clk / (2U * SDIO_INIT_FREQ);
+  /* Initialize SDMMC peripheral interface with default configuration */
+  (void)SDMMC_Init(hsdio->Instance, Init);
+
+  /* Set Power State to ON */
+  (void)SDMMC_PowerState_ON(hsdio->Instance);
+
+  /* wait 74 Cycles: required power up waiting time before starting the SDIO initialization sequence */
+  sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+  HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+
+  if (hsdio->SDIO_IdentifyCard == NULL)
+  {
+    hsdio->SDIO_IdentifyCard = SDIO_InitCard;
+  }
+  /* SDIO enumeration sequence */
+  if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK)
+  {
+    hsdio->State = HAL_SDIO_STATE_RESET;
+    return HAL_ERROR;
+  }
+
+  /* Configure the SDMMC user parameters */
+  Init.ClockEdge           = hsdio->Init.ClockEdge;
+  Init.ClockPowerSave      = hsdio->Init.ClockPowerSave;
+  Init.BusWide             = hsdio->Init.BusWide;
+  Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl;
+  Init.ClockDiv            = hsdio->Init.ClockDiv;
+  (void)SDMMC_Init(hsdio->Instance, Init);
+
+  data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U;
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->Context = SDIO_CONTEXT_NONE;
+  hsdio->State = HAL_SDIO_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initializes the SDIO device.
+  * @param  hsdio: Pointer to the SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(hsdio->Instance));
+
+  /* Check the SDIO handle allocation */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set Power State to OFF */
+  (void)SDMMC_PowerState_OFF(hsdio->Instance);
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+  if (hsdio->MspDeInitCallback == NULL)
+  {
+    hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsdio->MspDeInitCallback(hsdio);
+#else
+  /* De-Initialize the MSP layer */
+  HAL_SDIO_MspDeInit(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+  hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+  hsdio->State = HAL_SDIO_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SDIO MSP.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize SDIO MSP.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_MspDeInit could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group2
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and de-initialization functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to re-configure the SDIO peripheral.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enables wide bus operation for the requested card if supported by card.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  BusWide: Specifies the SDIO card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide)
+{
+  uint8_t data;
+  HAL_StatusTypeDef error_state = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    data = (BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U;
+    MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_WIDBUS,
+               (BusWide == HAL_SDIO_4_WIRES_MODE) ? SDMMC_BUS_WIDE_4B : SDMMC_BUS_WIDE_1B);
+
+    if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK)
+    {
+      error_state =  HAL_ERROR;
+    }
+  }
+  else
+  {
+    error_state =  HAL_ERROR;
+  }
+
+  return error_state;
+}
+
+/**
+  * @brief  Update the SDIO Clock.
+  * @param  hsdio: Pointer to SDIO handle.
+  * @param  ClockSpeed: SDIO Clock speed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed)
+{
+  uint32_t ClockDiv;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)) / (2U * ClockSpeed);
+    MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_CLKDIV, ClockDiv);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the SDIO block size.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  function_nbr: Specifies the SDIO function number.
+  * @param  BlockSize: Specifies the SDIO Block size to set.
+  *         This parameter can be one of the following values @ref SDIO_Exported_Constansts_Group7.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize)
+{
+  HAL_SDIO_ExtendedCmd_TypeDef cmd53;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(function_nbr));
+  assert_param(IS_SDIO_SUPPORTED_BLOCK_SIZE(BlockSize));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set SDIO F1 block size */
+  cmd53.IOFunctionNbr = SDIO_FUNCTION_0;
+  cmd53.OpCode = HAL_SDIO_OP_CODE_AUTO_INC;
+  cmd53.Block_Mode = HAL_SDIO_MODE_BYTE;
+  cmd53.Reg_Addr = (function_nbr * 0x100UL) + 0x10UL;
+  if (SDIO_WriteExtended(hsdio, &cmd53, (uint8_t *)(&BlockSize), 2U) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->block_size = BlockSize;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the data rate.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  DataRate: Specifies the SDIO data rate to set.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate)
+{
+  HAL_StatusTypeDef errorstate = HAL_OK;
+  uint8_t data;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  switch (DataRate)
+  {
+    case HAL_SDIOS_DATA_RATE_SDR25:
+      data = SDIO_BUS_SPEED_SDR25;
+      errorstate = SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR16_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data);
+      break;
+
+    case HAL_SDIOS_DATA_RATE_SDR50:
+      data = SDIO_BUS_SPEED_SDR50;
+      errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2U) | (SDIO_FUNCTION_0 << 1U) | (SDIO_FUNCTION_0 << 14U)
+                                            | SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data);
+      MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED, SDMMC_CLKCR_BUSSPEED);
+      break;
+
+    case HAL_SDIOS_DATA_RATE_DDR50:
+      data = SDIO_BUS_SPEED_DDR50;
+      errorstate = SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) |
+                                            SDMMC_SDIO_CCCR16_SD_BYTE3), HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data);
+      MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED,
+                 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED);
+      break;
+    default: /* SDR12 */
+      break;
+  }
+
+  return (errorstate != HAL_OK) ? HAL_ERROR : HAL_OK;
+}
+
+/**
+  * @brief  Reset SDIO Card
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t data = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /**  To reset the SDIO module by CMD52 with writing to RES in CCCR or send CMD0 the card shall change the speed mode
+    *  default speed mode.
+    *  The reset cmd (cmd0) is only used for memory. In order to reset an I/O card or the I/O portion of a combo card,
+    *  Use CMD52 to write 1 to the RES bit in the CCC(bit3 of register 6).
+    */
+  if (SDIO_WriteDirect(hsdio, ((SDIO_FUNCTION_0 << 2) | (SDIO_FUNCTION_0 << 1) | (SDIO_FUNCTION_0 << 14) |
+                               SDMMC_SDIO_CCCR4_SD_BYTE2),
+                       HAL_SDIO_WRITE_ONLY,
+                       0U,
+                       &data) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->State = HAL_SDIO_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Card Common Control register (CCCR).
+  * @param  hsdio: Pointer to SDIO handle.
+  * @param  pCccr: Pointer to Cccr register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr)
+{
+  uint8_t tempBuffer[256] = {0U};
+  uint32_t count;
+
+  assert_param(hsdio != NULL);
+  assert_param(pCccr != NULL);
+
+  if ((hsdio == NULL) || (pCccr == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++)
+  {
+    if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0 + count, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) !=
+        HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  pCccr->cccr_revision = tempBuffer[0] & 0x0FU;
+  pCccr->sdio_revision = (tempBuffer[0] & 0xF0U) >> 4U;
+  pCccr->sd_spec_revision = tempBuffer[0x01U] & 0x0FU;
+  pCccr->bus_width_8Bit = ((tempBuffer[0x07U] & 0x04U) != 0U) ? HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED
+                          : HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED;
+  pCccr->card_capability = (tempBuffer[0x08U] & 0xDFUL);
+  /* common CIS pointer */
+  pCccr->commonCISPointer = tempBuffer[0x09U] | ((uint32_t)tempBuffer[(uint32_t)0x09U + 1U] << 8U) |
+                            ((uint32_t)tempBuffer[(uint32_t)0x09U + 2U] << 16U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Card Function Basic register(FBR).
+  * @param  hsdio: Pointer to SDIO handle.
+  * @param  pFbr: Pointer to Fbr register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr)
+{
+  uint8_t tempBuffer[256] = {0U};
+  uint32_t count;
+  uint8_t func_idx;
+
+  assert_param(hsdio != NULL);
+  assert_param(pFbr != NULL);
+
+  if ((hsdio == NULL) || (pFbr == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  for (func_idx = 2U; func_idx <= SDIO_MAX_IO_NUMBER; func_idx++)
+  {
+    for (count = 0U; count <= SDIO_CCCR_REG_NUMBER; count++)
+    {
+      if (SDIO_ReadDirect(hsdio, (((uint32_t)SDMMC_SDIO_F1BR0 * (uint32_t)func_idx) + count),
+                          HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &tempBuffer[count]) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+    }
+    pFbr[(uint32_t)func_idx - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU;
+    pFbr[(uint32_t)func_idx - 1U].ioExtFunctionCode = tempBuffer[1U];
+    pFbr[(uint32_t)func_idx - 1U].ioPointerToCIS = tempBuffer[9U] | ((uint32_t)tempBuffer[10U] << 8U) |
+                                                   ((uint32_t)tempBuffer[11U] << 16U);
+    pFbr[(uint32_t)func_idx - 1U].ioPointerToCSA = tempBuffer[12U] | ((uint32_t)tempBuffer[13U] << 8U) |
+                                                   ((uint32_t)tempBuffer[14U] << 16U);
+    if ((tempBuffer[2U] & 0x01U) != 0U)
+    {
+      pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_POWER_SELECTION;
+    }
+    if ((tempBuffer[0U] & 0x40U) != 0U)
+    {
+      pFbr[(uint32_t)func_idx - 1U].flags |= (uint8_t)HAL_SDIO_FBR_SUPPORT_CSA;
+    }
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group3
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Data management functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the data transfer from/to SDIO card.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Read data from a specified address using the direct mode through cmd52.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Specifies the SDIO Argument.
+  * @param  pData: pointer to the buffer that will contain the received data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData)
+{
+  uint32_t cmd;
+  uint32_t errorstate;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+  assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite));
+
+  if ((hsdio == NULL) || (Argument == NULL) || (NULL == pData))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    cmd = SDIO_READ << 31U;
+    cmd |= (((uint32_t)Argument->IOFunctionNbr) << 28U);
+    cmd |= (((uint32_t)Argument->ReadAfterWrite) << 27U);
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= 0U;
+    errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData);
+
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Read data from a specified address using the direct mode through cmd52.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Specifies the SDIO Argument.
+  * @param  Data: pointer to the buffer that will contain the received data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data)
+{
+  uint32_t cmd;
+  uint32_t errorstate;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(IS_SDIO_RAW_FLAG(Argument->ReadAfterWrite));
+
+  if ((hsdio == NULL) || (Argument == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    cmd = SDIO_WRITE << 31U;
+    cmd |= ((uint32_t)Argument->IOFunctionNbr) << 28U;
+    cmd |= ((uint32_t)Argument->ReadAfterWrite) << 27U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= Data;
+    errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &Data);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read data from a specified address using extended mode through cmd53.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:   size to read.
+  * @param  Timeout_Ms:  Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                        uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms)
+{
+  uint32_t cmd;
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t regCount;
+  uint8_t byteCount;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint8_t *tempbuff = pData;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Compute how many blocks are to be send for pData of length data_size to be send */
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    /* Configure the SDIO DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      /* (Argument & 0x1FFU) is to get the 9 bits of Block/Byte counts */
+      config.DataLength    = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC ;
+    /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */
+    config.TransferMode = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                          SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM         = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Correspond to the write or read bit of the CMD argument */
+    /* Read */
+    hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK :
+                     SDIO_CONTEXT_READ_SINGLE_BLOCK;
+    cmd = SDIO_READ << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= (Size_byte & 0x1FFU);
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */
+    /* Poll on SDMMC flags */
+    dataremaining = config.DataLength;
+
+    while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL |
+                                SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+    {
+      if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (regCount = 0U; regCount < 8U; regCount++)
+        {
+          data = SDMMC_ReadFIFO(hsdio->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+        }
+        dataremaining -= 32U;
+      }
+      else if (dataremaining < 32U)
+      {
+        while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE)))
+        {
+          data = SDMMC_ReadFIFO(hsdio->Instance);
+          for (byteCount = 0U; byteCount < 4U; byteCount++)
+          {
+            if (dataremaining > 0U)
+            {
+              *tempbuff = (uint8_t)((data >> (byteCount * 8U)) & 0xFFU);
+              tempbuff++;
+              dataremaining--;
+            }
+          }
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+      if ((HAL_GetTick() - tickstart) >=  Timeout_Ms)
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT;
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+    /* Get error state */
+    if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_RX_OVERRUN;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER)
+    {
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write data from a specified address using extended mode through cmd53.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:  Block size to write.
+  * @param  Timeout_Ms:  Specify timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                         uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms)
+{
+  uint32_t cmd;
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t regCount;
+  uint8_t byteCount;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint8_t *u32tempbuff = pData;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Compute how many blocks are to be send for pData of length data_size to be send */
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    /* Configure the SDIO DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      config.DataLength    = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    /* (HAL_SDIO_MODE_BLOCK << 27) corresponds to the block mode bit of the CMD argument */
+    config.TransferMode  = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                           SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Correspond to the write or read bit of the CMD argument */
+    hsdio->Context = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK :
+                     SDIO_CONTEXT_WRITE_SINGLE_BLOCK;
+    cmd = SDIO_WRITE << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= (Size_byte & 0x1FFU);
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                                SDMMC_FLAG_DATAEND))
+    {
+
+      if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+      {
+        /* Read data from SDMMC Rx FIFO */
+        for (regCount = 0U; regCount < 8U; regCount++)
+        {
+          hsdio->Instance->FIFO = *u32tempbuff;
+          u32tempbuff++;
+        }
+        dataremaining -= 32U;
+      }
+      else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)))
+      {
+        uint8_t *u8buff = (uint8_t *)u32tempbuff;
+        while (dataremaining > 0U)
+        {
+          data = 0U;
+          for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++)
+          {
+            data |= ((uint32_t)(*u8buff) << (byteCount << 3U));
+            u8buff++;
+            dataremaining--;
+          }
+          hsdio->Instance->FIFO = data;
+        }
+      }
+      if (((HAL_GetTick() - tickstart) >=  Timeout_Ms))
+      {
+        /* Clear all the static flags */
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT;
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+    /* Get error state */
+    if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      /* (SDIO_WRITE << 31) correspond to the write or read bit of the CMD argument */
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER)
+    {
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read data from a specified address using extended mode through cmd53 in DMA mode.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:  Block size to write.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                            uint8_t *pData, uint32_t Size_byte)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint8_t *p_dma_buffer;
+  uint32_t cmd;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    p_dma_buffer = (uint8_t *)pData;
+    hsdio->pRxBuffPtr = (uint8_t *)pData;
+    hsdio->RxXferSize = Size_byte;
+    hsdio->next_data_addr = (uint32_t)pData;
+
+    /* Compute how many blocks are to be send for pData of length data_size to be send */
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    if (nbr_of_block != 0U)
+    {
+      hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block));
+      hsdio->next_reg_addr = (Argument->Reg_Addr) | ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U)
+                             | ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U);
+      hsdio->next_data_addr += (nbr_of_block * hsdio->block_size);
+    }
+    else
+    {
+      hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte :
+                               HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      if (hsdio->remaining_data != 0U)
+      {
+        hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                                (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) :
+                                (Size_byte - hsdio->remaining_data);
+        hsdio->next_reg_addr += (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \
+                                (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE + 1U) : (Size_byte + 1U);
+      }
+    }
+
+    /* DMA configuration (use single buffer) */
+    hsdio->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+    hsdio->Instance->IDMABASER = (uint32_t)p_dma_buffer;
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      config.DataLength    = (Size_byte > 0U) ? Size_byte : HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC ;
+    config.TransferMode  = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                           SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Read */
+    hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_READ_MULTIPLE_BLOCK :
+                                SDIO_CONTEXT_READ_SINGLE_BLOCK) | SDIO_CONTEXT_DMA;
+
+    cmd = SDIO_READ << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= ((nbr_of_block == 0U) ? Size_byte :  nbr_of_block) & 0x1FFU;
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* Enable interrupt */
+    __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write data from a specified address using extended mode through cmd53 in DMA mode.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  Argument: Pointer to SDIO argument
+  * @param  pData:  pointer to the buffer that will contain the data to transmit
+  * @param  Size_byte:  Block size to write.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument,
+                                             uint8_t *pData, uint32_t Size_byte)
+{
+  uint32_t cmd;
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint8_t *p_dma_buffer;
+  uint32_t nbr_of_block;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(Argument != NULL);
+  assert_param(pData != NULL);
+
+  if ((hsdio == NULL) || (Argument == NULL) || (pData == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+    hsdio->State = HAL_SDIO_STATE_BUSY;
+
+    /* Initialize data control register */
+    if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+    {
+      hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+    }
+    else
+    {
+      hsdio->Instance->DCTRL = 0U;
+    }
+
+    p_dma_buffer = (uint8_t *)pData;
+    hsdio->pTxBuffPtr = (uint8_t *)pData;
+    hsdio->TxXferSize = Size_byte;
+    hsdio->next_data_addr = (uint32_t)pData;
+
+    nbr_of_block = (Size_byte & ~(hsdio->block_size & 1U)) >> __CLZ(__RBIT(hsdio->block_size));
+
+    if (nbr_of_block != 0U)
+    {
+      hsdio->remaining_data = (Size_byte - (hsdio->block_size * nbr_of_block));
+      if (hsdio->block_size <= 128U)
+      {
+        hsdio->next_reg_addr = (Argument->Reg_Addr) |
+                               ((((nbr_of_block * hsdio->block_size) >> 1U) & 0x3FFFU) << 1U) |
+                               ((hsdio->remaining_data <= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? 1U : 0U);
+      }
+      else
+      {
+        hsdio->next_reg_addr = (nbr_of_block * hsdio->block_size) >> 1U;
+      }
+      hsdio->next_data_addr += (nbr_of_block * hsdio->block_size);
+    }
+    else
+    {
+      hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                              (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) :
+                              (Size_byte - hsdio->remaining_data);
+      if (hsdio->remaining_data != 0U)
+      {
+        hsdio->remaining_data = (Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                                (Size_byte - HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) :
+                                (Size_byte - hsdio->remaining_data);
+        hsdio->next_reg_addr += ((Size_byte >= HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? \
+                                 (HAL_SDIO_DATA_BLOCK_SIZE_512BYTE >> 1U) : (Size_byte >> 1U)) |
+                                (((hsdio->remaining_data > 0U) ? 0U : 1U));
+      }
+      hsdio->next_data_addr += (Size_byte < HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? Size_byte :
+                               HAL_SDIO_DATA_BLOCK_SIZE_512BYTE;
+    }
+
+    /* DMA configuration (use single buffer) */
+    hsdio->Instance->IDMACTRL  = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
+    hsdio->Instance->IDMABASER = (uint32_t)p_dma_buffer;
+
+    /* Configure the SDIO DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    if (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK)
+    {
+      config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+      config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+    }
+    else
+    {
+      config.DataLength = (Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ? HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte;
+      config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+    }
+
+    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = (Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK
+                           : SDMMC_TRANSFER_MODE_SDIO;
+    config.DPSM          = SDMMC_DPSM_DISABLE;
+    (void)SDMMC_ConfigData(hsdio->Instance, &config);
+
+    __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+    /* Write */
+    hsdio->Context = (uint32_t)((Argument->Block_Mode == HAL_SDIO_MODE_BLOCK) ?
+                                SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK :
+                                SDIO_CONTEXT_WRITE_SINGLE_BLOCK) | SDIO_CONTEXT_DMA;
+    cmd = SDIO_WRITE << 31U;
+    cmd |= Argument->IOFunctionNbr << 28U;
+    cmd |= Argument->Block_Mode << 27U;
+    cmd |= Argument->OpCode << 26U;
+    cmd |= (Argument->Reg_Addr & 0x1FFFFU) << 9U;
+    cmd |= ((nbr_of_block == 0U) ? ((Size_byte > HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) ?
+                                    HAL_SDIO_DATA_BLOCK_SIZE_512BYTE : Size_byte) : nbr_of_block) & 0x1FFU;
+    errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+    if (errorstate != HAL_SDIO_ERROR_NONE)
+    {
+      hsdio->ErrorCode |= errorstate;
+      if (errorstate != (SDMMC_ERROR_ADDR_OUT_OF_RANGE | SDMMC_ERROR_ILLEGAL_CMD | SDMMC_ERROR_COM_CRC_FAILED |
+                         SDMMC_ERROR_GENERAL_UNKNOWN_ERR))
+      {
+        MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+        __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+        hsdio->State = HAL_SDIO_STATE_READY;
+        hsdio->Context = SDIO_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+    /* Enable interrupt */
+    __HAL_SDIO_ENABLE_IT(hsdio, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group4
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set callback functions allowing to manage the data transfer from/to SDIO card.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles SDIO device interrupt request.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio)
+{
+  HAL_SDIO_ExtendedCmd_TypeDef CMD53_desc;
+  HAL_StatusTypeDef errorstate;
+  uint32_t ctx = hsdio->Context;
+  uint32_t flags;
+
+  flags   = READ_REG(((SDMMC_TypeDef *)((uint32_t)(hsdio)->Instance))->STA);
+
+  if (READ_BIT(flags, SDMMC_FLAG_SDIOIT) != 0U)
+  {
+    (void)SDIO_IOFunction_IRQHandler(hsdio);
+  }
+
+  if (READ_BIT(flags, SDMMC_FLAG_DATAEND) != 0U)
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_FLAG_DATAEND);
+
+    hsdio->State = HAL_SDIO_STATE_READY;
+
+    __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_DATAEND  | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR |
+                          SDMMC_IT_RXOVERR  | SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF);
+
+    __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_IDMABTC);
+    __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+    if ((ctx & SDIO_CONTEXT_DMA) != 0U)
+    {
+      hsdio->Instance->DLEN = 0;
+      hsdio->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+      if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+      {
+        hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+      }
+      else
+      {
+        hsdio->Instance->DCTRL = 0U;
+      }
+
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      hsdio->State = HAL_SDIO_STATE_READY;
+    }
+
+    if (hsdio->remaining_data != 0U)
+    {
+      CMD53_desc.Block_Mode = HAL_SDIO_MODE_BYTE;
+      CMD53_desc.Reg_Addr = hsdio->next_reg_addr;
+      CMD53_desc.IOFunctionNbr = 1;
+      CMD53_desc.OpCode = 1;
+      if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+        hsdio->pRxBuffPtr = (uint8_t *)hsdio->next_data_addr;
+        errorstate =  HAL_SDIO_ReadExtended_DMA(hsdio, &CMD53_desc, hsdio->pRxBuffPtr, hsdio->remaining_data);
+      }
+      else
+      {
+        hsdio->pTxBuffPtr = (uint8_t *)hsdio->next_data_addr;
+        errorstate =  HAL_SDIO_WriteExtended_DMA(hsdio, &CMD53_desc, hsdio->pTxBuffPtr, hsdio->remaining_data);
+      }
+      if (errorstate != HAL_OK)
+      {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1)
+        hsdio->ErrorCallback(hsdio);
+#else
+        HAL_SDIO_ErrorCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+      }
+    }
+    else if (((ctx & SDIO_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((ctx & SDIO_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+    {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+      hsdio->RxCpltCallback(hsdio);
+#else
+      HAL_SDIO_RxCpltCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+    }
+    else
+    {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+      hsdio->TxCpltCallback(hsdio);
+#else
+      HAL_SDIO_TxCpltCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+    }
+  }
+
+  if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR))
+  {
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1)
+    hsdio->ErrorCallback(hsdio);
+#else
+    HAL_SDIO_ErrorCallback(hsdio);
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsdio: Pointer to SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callbacks
+  * @param hsdio: Pointer SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SDIO error callbacks
+  * @param hsdio: Pointer SDIO handle
+  * @retval None
+  */
+__weak void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SDIO IO Function complete callback
+  * @param hsdio: Pointer SDIO handle
+  * @param func: SDIO IO Function
+  * @retval None
+  */
+__weak void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+  UNUSED(func);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_ErrorCallback can be implemented in the user file
+   */
+}
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+/**
+  * @brief  Enable/Disable the SDIO Transceiver 1.8V Mode Callback.
+  * @param  hsdio: Pointer SDIO handle
+  * @param  status: Voltage Switch State
+  * @retval None
+  */
+__weak  void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdio);
+  UNUSED(status);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SDIO_EnableTransceiver could be implemented in the user file
+   */
+}
+#endif /* USE_SDIO_TRANSCEIVER  */
+
+#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SDIO Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @param hsdio : SDIO handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDIO_TX_CPLT_CB_ID                 SDIO Tx Complete Callback ID
+  *          @arg @ref HAL_SDIO_RX_CPLT_CB_ID                 SDIO Rx Complete Callback ID
+  *          @arg @ref HAL_SDIO_ERROR_CB_ID                   SDIO Error Callback ID
+  *          @arg @ref HAL_SDIO_MSP_INIT_CB_ID                SDIO MspInit Callback ID
+  *          @arg @ref HAL_SDIO_MSP_DEINIT_CB_ID              SDIO MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID,
+                                            pSDIO_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(pCallback != NULL);
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_TX_CPLT_CB_ID :
+        hsdio->TxCpltCallback = pCallback;
+        break;
+      case HAL_SDIO_RX_CPLT_CB_ID :
+        hsdio->RxCpltCallback = pCallback;
+        break;
+      case HAL_SDIO_ERROR_CB_ID :
+        hsdio->ErrorCallback = pCallback;
+        break;
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = pCallback;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdio->State == HAL_SDIO_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = pCallback;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SDIO Callback
+  *         SDIO Callback is redirected to the weak (overridden) predefined callback.
+  * @note   The HAL_SDIO_UnRegisterCallback() may be called before HAL_SDIO_Init() in
+  *         HAL_SDIO_STATE_RESET to register callbacks for HAL_SDIO_MSP_INIT_CB_ID
+  *         and HAL_SDIO_MSP_DEINIT_CB_ID.
+  * @param hsdio : SDIO handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values @ref SDIO_Exported_Types_Group3.
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_TX_CPLT_CB_ID :
+        hsdio->TxCpltCallback = HAL_SDIO_TxCpltCallback;
+        break;
+      case HAL_SDIO_RX_CPLT_CB_ID :
+        hsdio->RxCpltCallback = HAL_SDIO_RxCpltCallback;
+        break;
+      case HAL_SDIO_ERROR_CB_ID :
+        hsdio->ErrorCallback = HAL_SDIO_ErrorCallback;
+        break;
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = HAL_SDIO_MspInit;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit;
+        break;
+      default :
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdio->State == HAL_SDIO_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SDIO_MSP_INIT_CB_ID :
+        hsdio->MspInitCallback = HAL_SDIO_MspInit;
+        break;
+      case HAL_SDIO_MSP_DEINIT_CB_ID :
+        hsdio->MspDeInitCallback = HAL_SDIO_MspDeInit;
+        break;
+      default :
+        hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */
+
+#if (USE_SDIO_TRANSCEIVER != 0U)
+/**
+  * @brief  Register a User SDIO Transceiver Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @param hsdio : SDIO handle
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio,
+                                                       pSDIO_TransceiverCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->DriveTransceiver_1_8V_Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SDIO Transceiver Callback
+  *         SDIO Callback is redirected to the weak (overridden) predefined callback
+  * @param hsdio : SDIO handle
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hsdio->State == HAL_SDIO_STATE_READY)
+  {
+    hsdio->DriveTransceiver_1_8V_Callback = HAL_SDIO_DriveTransceiver_1_8V_Callback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_SDIO_TRANSCEIVER */
+
+/**
+  * @brief Register a User SDIO Identification Callback
+  * @param hsdio: Pointer to SDIO handle
+  * @param pCallback: pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio,
+                                                        pSDIO_IdentifyCardCallbackTypeDef pCallback)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(pCallback != NULL);
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  hsdio->SDIO_IdentifyCard = pCallback;
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group5
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Peripheral State and Errors functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the SDIO card operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief return the SDIO state
+  * @param hsdio: Pointer to SDIO handle
+  * @retval HAL state
+  */
+HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio)
+{
+  return hsdio->State;
+}
+
+/**
+  * @brief  Return the SDIO error code
+  * @param  hsdio : Pointer to a SDIO_HandleTypeDef structure that contains the configuration information.
+  * @retval SDIO Error Code
+  */
+uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio)
+{
+  return hsdio->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDIO_Exported_Functions_Group6
+  *  @brief
+  *
+@verbatim
+  ==============================================================================
+          ##### Peripheral IO interrupt #####
+  ==============================================================================
+  [..]
+    This subsection provides a set functions allowing to enable/disable IO functions interrupt features
+    on the SDIO card.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enable SDIO IO interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t intEn  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need enable again */
+  if ((((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U) && ((intEn & 0x01U) != 0U))
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    intEn |= (1U << (uint32_t)IOFunction) | 0x01U;
+    hsdio->IOInterruptNbr++;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0,
+                       &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  __HAL_SDIO_ENABLE_IT(hsdio, SDMMC_IT_SDIOIT);
+
+  /* Enable host SDIO interrupt operations */
+  __SDMMC_OPERATION_ENABLE(hsdio->Instance);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable SDIO IO interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t intEn  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already disable , do not need enable again */
+  if (((intEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    /* disable the interrupt, don't disable the interrupt master here */
+    intEn &= ~(1U << (uint32_t)IOFunction);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       &intEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdio->IOInterruptNbr > 1U)
+  {
+    hsdio->IOInterruptNbr--;
+  }
+  else
+  {
+    hsdio->IOInterruptNbr = 0U;
+    __HAL_SDIO_DISABLE_IT(hsdio, SDMMC_IT_SDIOIT);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable SDIO IO Enable.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t ioEn  = 0U;
+  uint8_t ioReady = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need to enable again */
+  if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x01U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    ioEn |= (1U << (uint32_t)IOFunction);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioReady) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* check if IO ready */
+  if ((ioReady & (1U << (uint32_t)IOFunction)) != 0U)
+  {
+    return HAL_OK;
+  }
+
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Disable SDIO IO Enable.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  uint8_t ioEn  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need enable again */
+  if (((ioEn >> (uint32_t)IOFunction) & 0x01U) == 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    ioEn &= ~(1U << (uint32_t)IOFunction);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR0_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0, &ioEn) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select SDIO IO Enable.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  IOFunction: Specifies the SDIO IO function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR12_SD_BYTE1, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       (uint8_t *)&IOFunction) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort IO transfer.
+  * @param  hsdio:  Pointer to SDIO handle
+  * @param IOFunction IO number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       (uint8_t *)&IOFunction) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable Assynchrone interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t enable_asyn_it  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it)
+      != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already enable , do not need enable again */
+  if ((enable_asyn_it & 0x02U) == 0x02U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    enable_asyn_it |= 0x02U;
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       &enable_asyn_it) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable Assynchrone interrupt.
+  * @param  hsdio: Pointer to SDIO handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t enable_asyn_it  = 0U;
+
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &enable_asyn_it)
+      != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* if already disable , do not need disable again */
+  if ((enable_asyn_it & 0x02U) == 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    enable_asyn_it &= (uint8_t) ~(0x02U);
+  }
+
+  if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR20_SD_BYTE2, HAL_SDIO_READ_AFTER_WRITE, SDIO_FUNCTION_0,
+                       &enable_asyn_it) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief sdio set io IRQ handler.
+  * @param hsdio  Pointer to SDIO handle
+  * @param IOFunction IO function io number.
+  * @param Callback io IRQ handler.
+  */
+HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction,
+                                                      HAL_SDIO_IOFunction_CallbackTypeDef pCallback)
+{
+  /* Check the parameters */
+  assert_param(hsdio != NULL);
+  assert_param(IS_SDIO_FUNCTION(IOFunction));
+
+  /* Check the SDIO peripheral handle parameter */
+  if (hsdio == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback;
+  hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction);
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function --------------------------------------------------------------------------------------------------*/
+/** @addtogroup SDIO_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Initializes the SDIO device.
+  * @param  hsdio: Pointer to the SDIO handle
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio)
+{
+  uint32_t errorstate;
+  uint32_t timeout = 0U;
+  uint16_t sdio_rca = 1U;
+  uint32_t Resp4;
+  uint32_t nbr_of_func;
+
+  /* Identify card operating voltage */
+  errorstate = SDMMC_CmdGoIdleState(hsdio->Instance);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the power State */
+  if (SDMMC_GetPowerState(hsdio->Instance) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Send CMD5 */
+  errorstate = SDMMC_CmdSendOperationcondition(hsdio->Instance, 0U, &Resp4);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+  nbr_of_func = ((Resp4 & 0x70000000U) >> 28U);
+  /* Check if Nbr of function > 0 and OCR valid */
+  if (nbr_of_func > 0U)
+  {
+    /* Send CMD5 with arg= S18R, WV*/
+    if (SDMMC_CmdSendOperationcondition(hsdio->Instance, (SDIO_OCR_VDD_32_33 | SDIO_OCR_SDIO_S18R), &Resp4)
+        != HAL_SDIO_ERROR_NONE)
+    {
+      return HAL_ERROR;
+    }
+    /* Check if IORDY = 1 and S18A = 1 */
+    if ((((Resp4 & 0x80000000U) >> 31U) != 0U) && (((Resp4 & 0x1000000U) >> 24U) != 0U))
+    {
+      /* Send CMD11 to switch 1.8V mode */
+      errorstate = SDMMC_CmdVoltageSwitch(hsdio->Instance);
+      if (errorstate != HAL_SDIO_ERROR_NONE)
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* S18A is not supported */
+    }
+  }
+
+  /** Cmd3 is sent while response is SDMMC_ERROR_ILLEGAL_CMD, due to the partial init test done before
+    * (sending cmd0 after the sequence cmd0/cmd3 is sent is considered illegal).
+    */
+  do
+  {
+    errorstate = SDMMC_CmdSetRelAdd(hsdio->Instance, &sdio_rca);
+    timeout++;
+    HAL_Delay(1);
+  } while ((errorstate == SDMMC_ERROR_ILLEGAL_CMD) && (timeout != SDIO_TIMEOUT));
+
+  if ((timeout == SDIO_TIMEOUT) || (errorstate != HAL_SDIO_ERROR_NONE))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Select the Card ( Sending CMD7)*/
+  errorstate = SDMMC_CmdSelDesel(hsdio->Instance, (uint32_t)(((uint32_t)sdio_rca) << 16U));
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read 1 byte data.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  cmd_arg: formatted CMD52 structure
+  * @param  pData: pointer to write or read data
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw,
+                                         uint32_t function_nbr, uint8_t *pData)
+{
+  uint32_t errorstate;
+  uint32_t cmd;
+
+  cmd = SDIO_READ << 31U;
+  cmd |= function_nbr << 28U;
+  cmd |= raw << 27U;
+  cmd |= (addr & 0x1FFFFU) << 9U;
+  errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, pData);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    hsdio->ErrorCode |= errorstate;
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+  /* Clear all the static flags */
+  __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write 1 byte data.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  cmd_arg: formatted CMD52 structure
+  * @param  pData: pointer to write or read data
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw,
+                                          uint32_t function_nbr, uint8_t *pData)
+{
+  uint32_t errorstate;
+  uint32_t cmd;
+  uint8_t response;
+
+  cmd = SDIO_WRITE << 31U;
+  cmd |= function_nbr << 28U;
+  cmd |= raw << 27U;
+  cmd |= (addr & 0x1FFFFU) << 9U;
+  cmd |= ((uint32_t) * pData & 0x000000FFU);
+  errorstate = SDMMC_SDIO_CmdReadWriteDirect(hsdio->Instance, cmd, &response);
+
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    hsdio->ErrorCode |= errorstate;
+    /* Clear all the static flags */
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+
+  /* Clear all the static flags */
+  __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write multiple data with a single command.
+  * @param  hsdio: Pointer to SDIO handle
+  * @param  cmd_arg: formatted cmd53 structure
+  * @param  Size_byte: block size if CMD53 defined in HAL_SDIO_MODE_BLOCK
+  * @param  pData: pointer to write or read data
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg,
+                                            uint8_t *pData, uint16_t Size_byte)
+{
+  SDMMC_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t regCount;
+  uint8_t byteCount;
+  uint32_t data;
+  uint32_t dataremaining;
+  uint32_t *u32tempbuff = (uint32_t *)(uint32_t)pData;
+  SDMMC_TypeDef *SDMMCx;
+  uint32_t cmd;
+  uint32_t nbr_of_block;
+
+  hsdio->ErrorCode = HAL_SDIO_ERROR_NONE;
+
+  /* Compute how many blocks are to be send for pData of length data_size to be send */
+  nbr_of_block = (((uint32_t)Size_byte & ~((uint32_t)hsdio->block_size & 1U))) >> __CLZ(__RBIT(hsdio->block_size));
+
+  /* Initialize data control register */
+  if ((hsdio->Instance->DCTRL & SDMMC_DCTRL_SDIOEN) != 0U)
+  {
+    hsdio->Instance->DCTRL = SDMMC_DCTRL_SDIOEN;
+  }
+  else
+  {
+    hsdio->Instance->DCTRL = 0U;
+  }
+
+  /* Configure the SDIO DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  if (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK)
+  {
+    config.DataLength    = (uint32_t)(nbr_of_block * hsdio->block_size);
+    config.DataBlockSize = SDIO_Convert_Block_Size(hsdio, hsdio->block_size);
+  }
+  else
+  {
+    config.DataLength    = Size_byte;
+    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
+  }
+
+  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;
+  config.TransferMode  = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDMMC_TRANSFER_MODE_BLOCK :
+                         SDMMC_TRANSFER_MODE_SDIO;
+  config.DPSM          = SDMMC_DPSM_DISABLE;
+  (void)SDMMC_ConfigData(hsdio->Instance, &config);
+  __SDMMC_CMDTRANS_ENABLE(hsdio->Instance);
+
+  hsdio->Context = (cmd_arg->Block_Mode == HAL_SDIO_MODE_BLOCK) ? SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK :
+                   SDIO_CONTEXT_WRITE_SINGLE_BLOCK;
+  cmd = SDIO_WRITE << 31U;
+  cmd |= cmd_arg->IOFunctionNbr << 28U;
+  cmd |= cmd_arg->Block_Mode << 27U;
+  cmd |= cmd_arg->OpCode << 26U;
+  cmd |= (cmd_arg->Reg_Addr & 0x1FFFFU) << 9U;
+  cmd |= (((uint32_t)Size_byte) & 0x1FFU);
+  errorstate = SDMMC_SDIO_CmdReadWriteExtended(hsdio->Instance, cmd);
+  if (errorstate != HAL_SDIO_ERROR_NONE)
+  {
+    MODIFY_REG(hsdio->Instance->DCTRL, SDMMC_DCTRL_FIFORST, SDMMC_DCTRL_FIFORST);
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+    hsdio->ErrorCode |= errorstate;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+
+  SDMMCx = hsdio->Instance;
+  dataremaining = config.DataLength;
+  while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                              SDMMC_FLAG_DATAEND))
+  {
+    if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+    {
+      for (regCount = 8U; regCount > 0U; regCount--)
+      {
+        SDMMCx->FIFO = *u32tempbuff;
+        u32tempbuff++;
+      }
+      dataremaining -= 32U;
+    }
+    else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)))
+    {
+      uint8_t *u8buff = (uint8_t *)u32tempbuff;
+      while (dataremaining > 0U)
+      {
+        data = 0U;
+        for (byteCount = 0U; (byteCount < 4U) && (dataremaining > 0U); byteCount++)
+        {
+          data |= ((uint32_t)(*u8buff) << (byteCount << 3U));
+          u8buff++;
+          dataremaining--;
+        }
+        SDMMCx->FIFO = data;
+      }
+    }
+    if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+    {
+      __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+      hsdio->ErrorCode |= HAL_SDIO_ERROR_TIMEOUT;
+      hsdio->State = HAL_SDIO_STATE_READY;
+      hsdio->Context = SDIO_CONTEXT_NONE;
+      return HAL_TIMEOUT;
+    }
+  }
+
+  __SDMMC_CMDTRANS_DISABLE(hsdio->Instance);
+  if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DTIMEOUT))
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_TIMEOUT;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_DCRCFAIL))
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_DATA_CRC_FAIL;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR))
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_FLAGS);
+    hsdio->ErrorCode |= HAL_SDIO_ERROR_TX_UNDERRUN;
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else if (hsdio->ErrorCode == SDMMC_ERROR_INVALID_PARAMETER)
+  {
+    __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+    hsdio->State = HAL_SDIO_STATE_READY;
+    hsdio->Context = SDIO_CONTEXT_NONE;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  __HAL_SDIO_CLEAR_FLAG(hsdio, SDMMC_STATIC_DATA_FLAGS);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Allows to convert a block size in the according SDMMC value for configuring the SDMMC when doing a CMD53
+  * @param  hsdio: Pointer to the SDIO handle.
+  * @param  block_size: block size in bytes
+  * @retval block size as DBLOCKSIZE[3:0] bits format
+  */
+static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size)
+{
+  UNUSED(hsdio);
+
+  uint8_t most_bit = (uint8_t)__CLZ(__RBIT(block_size));
+  /*(1 << most_bit) - 1) is the mask used for blocksize*/
+  if (((uint8_t)block_size & ((1U << most_bit) - 1U)) != 0U)
+  {
+    return (uint8_t)SDMMC_DATABLOCK_SIZE_4B;
+  }
+  return most_bit << SDMMC_DCTRL_DBLOCKSIZE_Pos;
+}
+
+/*!
+ * @brief SDIO card io pending interrupt handle function.
+ * @note  This function is used to handle the pending io interrupt.
+ *        To register a IO IRQ handler, Use HAL_SDIO_EnableIOInterrupt and HAL_SDIO_SetIOIRQHandler
+ * @param  hsdio: Pointer to SDIO handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio)
+{
+  uint8_t count;
+  uint8_t pendingInt;
+
+  if (hsdio->IOInterruptNbr == 1U)
+  {
+    if ((hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U]) != NULL)
+    {
+      (hsdio->SDIO_IOFunction_Callback[hsdio->IOFunctionMask - 1U])(hsdio, hsdio->IOFunctionMask - 1U);
+    }
+  }
+  else if ((hsdio->IOInterruptNbr > 1U) && (hsdio->IOFunctionMask != 0U))
+  {
+    /* Get pending int firstly */
+    if (SDIO_ReadDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE1, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &pendingInt) !=
+        HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    if ((pendingInt != 0U) && (hsdio->IOFunctionMask != 0U))
+    {
+      for (count = 1; count <= SDIO_MAX_IO_NUMBER; count++)
+      {
+        if (((pendingInt & (1U << count)) != 0U) && (((1U << count)  & hsdio->IOFunctionMask) != 0U))
+        {
+          if ((hsdio->SDIO_IOFunction_Callback[count - 1U]) != NULL)
+          {
+            (hsdio->SDIO_IOFunction_Callback[count - 1U])(hsdio, count);
+          }
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+#endif /* HAL_SDIO_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sdram.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sdram.c
new file mode 100644
index 000000000..e6029a208
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sdram.c
@@ -0,0 +1,1432 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sdram.c
+  * @author  MCD Application Team
+  * @brief   SDRAM HAL module driver.
+  *          This file provides a generic firmware to drive SDRAM memories mounted
+  *          as external device.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver is a generic layered driver which contains a set of APIs used to
+    control SDRAM memories. It uses the FMC layer functions to interface
+    with SDRAM devices.
+    The following sequence should be followed to configure the FMC to interface
+    with SDRAM memories:
+
+   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
+          SDRAM_HandleTypeDef  hsdram
+
+       (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
+            values of the structure member.
+
+       (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
+            base register instance for NOR or SDRAM device
+
+   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
+          FMC_SDRAM_TimingTypeDef  Timing;
+      and fill its fields with the allowed values of the structure member.
+
+   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
+       performs the following sequence:
+
+       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
+       (##) Control register configuration using the FMC SDRAM interface function
+            FMC_SDRAM_Init()
+       (##) Timing register configuration using the FMC SDRAM interface function
+            FMC_SDRAM_Timing_Init()
+       (##) Program the SDRAM external device by applying its initialization sequence
+            according to the device plugged in your hardware. This step is mandatory
+            for accessing the SDRAM device.
+
+   (#) At this stage you can perform read/write accesses from/to the memory connected
+       to the SDRAM Bank. You can perform either polling or DMA transfer using the
+       following APIs:
+       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
+       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
+
+   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
+       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
+       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
+       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
+       structure.
+
+   (#) You can continuously monitor the SDRAM device HAL state by calling the function
+       HAL_SDRAM_GetState()
+
+   *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : SDRAM MspInit.
+        (+) MspDeInitCallback  : SDRAM MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : SDRAM MspInit.
+        (+) MspDeInitCallback  : SDRAM MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
+      and  HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
+      or HAL_SDRAM_Init function.
+
+      When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+
+/** @defgroup SDRAM SDRAM
+  * @brief SDRAM driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
+  * @{
+  */
+static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
+static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
+static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
+  * @{
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+           ##### SDRAM Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to initialize/de-initialize
+    the SDRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Performs the SDRAM device initialization sequence.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  Timing Pointer to SDRAM control timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
+{
+  /* Check the SDRAM handle parameter */
+  if (hsdram == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsdram->State == HAL_SDRAM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsdram->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+    if (hsdram->MspInitCallback == NULL)
+    {
+      hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+    }
+    hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+    hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+    hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+
+    /* Init the low level hardware */
+    hsdram->MspInitCallback(hsdram);
+#else
+    /* Initialize the low level hardware (MSP) */
+    HAL_SDRAM_MspInit(hsdram);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+  }
+
+  /* Initialize the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+  /* Initialize SDRAM control Interface */
+  (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
+
+  /* Initialize SDRAM timing Interface */
+  (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
+
+  /* Enable FMC Peripheral */
+  __FMC_ENABLE();
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Perform the SDRAM device initialization sequence.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
+{
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  if (hsdram->MspDeInitCallback == NULL)
+  {
+    hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsdram->MspDeInitCallback(hsdram);
+#else
+  /* Initialize the low level hardware (MSP) */
+  HAL_SDRAM_MspDeInit(hsdram);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+  /* Configure the SDRAM registers with their reset values */
+  (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
+
+  /* Reset the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsdram);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SDRAM MSP Init.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SDRAM MSP DeInit.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  This function handles SDRAM refresh error interrupt request.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Check SDRAM interrupt Rising edge flag */
+  if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
+  {
+    /* SDRAM refresh error interrupt callback */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+    hsdram->RefreshErrorCallback(hsdram);
+#else
+    HAL_SDRAM_RefreshErrorCallback(hsdram);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+    /* Clear SDRAM refresh error interrupt pending bit */
+    __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
+  }
+}
+
+/**
+  * @brief  SDRAM Refresh error callback.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsdram);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete error callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
+  * @brief    Input Output and memory control functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### SDRAM Input and Output functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to use and control the SDRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads 8-bit data buffer from the SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+  uint8_t *pdestbuff = pDstBuffer;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Read data from source */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *(__IO uint8_t *)pSdramAddress;
+      pdestbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = state;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 8-bit data buffer to SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
+  uint8_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *(__IO uint8_t *)pSdramAddress = *psrcbuff;
+      psrcbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 16-bit data buffer from the SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *pSdramAddress = pAddress;
+  uint16_t *pdestbuff = pDstBuffer;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size >= 2U ; size -= 2U)
+    {
+      *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
+      pdestbuff++;
+      *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
+      pdestbuff++;
+      pSdramAddress++;
+    }
+
+    /* Read last 16-bits if size is not 32-bits multiple */
+    if ((BufferSize % 2U) != 0U)
+    {
+      *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = state;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 16-bit data buffer to SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                      uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psdramaddress = pAddress;
+  uint16_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size >= 2U ; size -= 2U)
+    {
+      *psdramaddress = (uint32_t)(*psrcbuff);
+      psrcbuff++;
+      *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
+      psrcbuff++;
+      psdramaddress++;
+    }
+
+    /* Write last 16-bits if size is not 32-bits multiple */
+    if ((BufferSize % 2U) != 0U)
+    {
+      *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 32-bit data buffer from the SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
+  uint32_t *pdestbuff = pDstBuffer;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Read data from source */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *(__IO uint32_t *)pSdramAddress;
+      pdestbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = state;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 32-bit data buffer to SDRAM memory.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *pSdramAddress = pAddress;
+  uint32_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pSdramAddress = *psrcbuff;
+      psrcbuff++;
+      pSdramAddress++;
+    }
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    return  HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads a Words data from the SDRAM memory using DMA transfer.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                     uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+  uint32_t size;
+  uint32_t data_width;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    status = HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    if (state == HAL_SDRAM_STATE_READY)
+    {
+      hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
+    }
+    else
+    {
+      hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
+    }
+    hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
+
+    if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U))
+      {
+        /* Check destination data width and set the size to be transferred */
+        data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+
+        if (data_width == DMA_DEST_DATAWIDTH_WORD)
+        {
+          size = (BufferSize * 4U);
+        }
+        else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+        {
+          size = (BufferSize * 2U);
+        }
+        else
+        {
+          size = (BufferSize);
+        }
+        /* Set Source , destination , buffer size */
+        /* Set DMA data size */
+        hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
+        /* Set DMA source address */
+        hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
+        /* Set DMA destination address */
+        hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer;
+
+        /* Enable the DMA Stream */
+        status = HAL_DMAEx_List_Start_IT(hsdram->hdma);
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsdram);
+
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Check destination data width and set the size to be transferred */
+      data_width = hsdram->hdma->Init.DestDataWidth;
+
+      if (data_width == DMA_DEST_DATAWIDTH_WORD)
+      {
+        size = (BufferSize * 4U);
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+      {
+        size = (BufferSize * 2U);
+      }
+      else
+      {
+        size = (BufferSize);
+      }
+
+      /* Enable the DMA Stream */
+      status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                      uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+  uint32_t size;
+  uint32_t data_width;
+
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    status = HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsdram);
+
+    /* Update the SDRAM controller state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
+    hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
+
+    if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U))
+      {
+        /* Check destination data width and set the size to be transferred */
+        data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+
+        if (data_width == DMA_DEST_DATAWIDTH_WORD)
+        {
+          size = (BufferSize * 4U);
+        }
+        else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+        {
+          size = (BufferSize * 2U);
+        }
+        else
+        {
+          size = (BufferSize);
+        }
+        /* Set Source , destination , buffer size */
+        /* Set DMA data size */
+        hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
+        /* Set DMA source address */
+        hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer;
+        /* Set DMA destination address */
+        hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
+
+        /* Enable the DMA Stream */
+        status = HAL_DMAEx_List_Start_IT(hsdram->hdma);
+      }
+      else
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsdram);
+
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Check destination data width and set the size to be transferred */
+      data_width = hsdram->hdma->Init.DestDataWidth;
+
+      if (data_width == DMA_DEST_DATAWIDTH_WORD)
+      {
+        size = (BufferSize * 4U);
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+      {
+        size = (BufferSize * 2U);
+      }
+      else
+      {
+        size = (BufferSize);
+      }
+
+      /* Enable the DMA Stream */
+      status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsdram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SDRAM Callback
+  *         To be used to override the weak predefined callback
+  * @param hsdram : SDRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
+  *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
+  *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                             pSDRAM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SDRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  state = hsdram->State;
+  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = pCallback;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = pCallback;
+        break;
+      case HAL_SDRAM_REFRESH_ERR_CB_ID :
+        hsdram->RefreshErrorCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = pCallback;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SDRAM Callback
+  *         SDRAM Callback is redirected to the weak predefined callback
+  * @param hsdram : SDRAM handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDRAM_MSP_INIT_CB_ID       SDRAM MspInit callback ID
+  *          @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID     SDRAM MspDeInit callback ID
+  *          @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID    SDRAM Refresh Error callback ID
+  *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SDRAM_StateTypeDef state;
+
+  state = hsdram->State;
+  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+        break;
+      case HAL_SDRAM_REFRESH_ERR_CB_ID :
+        hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+        break;
+      case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+        hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+        break;
+      case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+        hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_MSP_INIT_CB_ID :
+        hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+        break;
+      case HAL_SDRAM_MSP_DEINIT_CB_ID :
+        hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User SDRAM Callback for DMA transfers
+  *         To be used to override the weak predefined callback
+  * @param hsdram : SDRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID  SDRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID   SDRAM DMA Xfer Error callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+                                                pSDRAM_DmaCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SDRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsdram);
+
+  state = hsdram->State;
+  if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+        hsdram->DmaXferCpltCallback = pCallback;
+        break;
+      case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+        hsdram->DmaXferErrorCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsdram);
+  return status;
+}
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### SDRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the SDRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically SDRAM write protection.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Enable write protection */
+    (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically SDRAM write protection.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
+{
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Disable write protection */
+    (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sends Command to the SDRAM bank.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  Command SDRAM command structure
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
+                                        uint32_t Timeout)
+{
+  HAL_SDRAM_StateTypeDef state = hsdram->State;
+
+  /* Check the SDRAM controller state */
+  if (state == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Send SDRAM command */
+    (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
+
+    /* Update the SDRAM controller state state */
+    if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
+    {
+      hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
+    }
+    else
+    {
+      hsdram->State = HAL_SDRAM_STATE_READY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Programs the SDRAM Memory Refresh rate.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  RefreshRate The SDRAM refresh rate value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
+{
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Program the refresh rate */
+    (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @param  AutoRefreshNumber The SDRAM auto Refresh number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
+{
+  /* Check the SDRAM controller state */
+  if (hsdram->State == HAL_SDRAM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hsdram->State == HAL_SDRAM_STATE_READY)
+  {
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_BUSY;
+
+    /* Set the Auto-Refresh number */
+    (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
+
+    /* Update the SDRAM state */
+    hsdram->State = HAL_SDRAM_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the SDRAM memory current mode.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval The SDRAM memory mode.
+  */
+uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
+{
+  /* Return the SDRAM memory current mode */
+  return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDRAM_Exported_Functions_Group4 State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### SDRAM State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the SDRAM controller
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the SDRAM state.
+  * @param  hsdram pointer to a SDRAM_HandleTypeDef structure that contains
+  *                the configuration information for SDRAM module.
+  * @retval HAL state
+  */
+HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram)
+{
+  return hsdram->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
+  * @{
+  */
+/**
+  * @brief  DMA SDRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_READY;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  hsdram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SDRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  hsdram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SDRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SDRAM error callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SDRAM controller state */
+  hsdram->State = HAL_SDRAM_STATE_ERROR;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+  hsdram->DmaXferErrorCallback(hdma);
+#else
+  HAL_SDRAM_DMA_XferErrorCallback(hdma);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smartcard.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smartcard.c
new file mode 100644
index 000000000..c7152440d
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smartcard.c
@@ -0,0 +1,3242 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smartcard.c
+  * @author  MCD Application Team
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the SMARTCARD peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The SMARTCARD HAL driver can be used as follows:
+
+    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+    (#) Associate a USART to the SMARTCARD handle hsmartcard.
+    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) USART pins configuration:
+             (+++) Enable the clock for the USART GPIOs.
+             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+             and HAL_SMARTCARD_Receive_IT() APIs):
+             (+++) Configure the USARTx interrupt priority.
+             (+++) Enable the NVIC USART IRQ handle.
+        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+             and HAL_SMARTCARD_Receive_DMA() APIs):
+             (+++) Declare a DMA handle structure for the Tx/Rx channel.
+             (+++) Enable the DMAx interface clock.
+             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+             (+++) Configure the DMA Tx/Rx channel.
+             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+             (+++) Configure the priority and enable the NVIC for the transfer complete
+                   interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+        error enabling or disabling in the hsmartcard handle Init structure.
+
+    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+        in the hsmartcard handle AdvancedInit structure.
+
+    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_SMARTCARD_MspInit() API.
+        [..]
+        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+    [..]
+    [..] Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** SMARTCARD HAL driver macros list ***
+     ========================================
+     [..]
+       Below the list of most used macros in SMARTCARD HAL driver.
+
+       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+     [..]
+       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
+    Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : SMARTCARD MspInit.
+    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : SMARTCARD MspInit.
+    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
+
+    [..]
+    By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak functions in the HAL_SMARTCARD_Init()
+    and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
+    or HAL_SMARTCARD_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARD SMARTCARD
+  * @brief HAL SMARTCARD module driver
+  * @{
+  */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+  * @{
+  */
+#define SMARTCARD_TEACK_REACK_TIMEOUT  1000U       /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+                                      USART_CR1_RE | USART_CR1_OVER8| \
+                                      USART_CR1_FIFOEN))  /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+                                          USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+
+#define USART_CR2_FIELDS  ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
+                                      USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_BRR_MIN  0x10U        /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX  0x0000FFFFU  /*!< USART BRR maximum authorized value */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+  * @{
+  */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+                                                          FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USARTx
+  associated to the SmartCard.
+  (+) These parameters can be configured:
+      (++) Baud Rate
+      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+      (++) Receiver/transmitter modes
+      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+      (++) Prescaler value
+      (++) Guard bit time
+      (++) NACK enabling or disabling on transmission error
+
+  (+) The following advanced features can be configured as well:
+      (++) TX and/or RX pin level inversion
+      (++) data logical level inversion
+      (++) RX and TX pins swap
+      (++) RX overrun detection disabling
+      (++) DMA disabling on RX error
+      (++) MSB first on communication line
+      (++) Time out enabling (and if activated, timeout value)
+      (++) Block length
+      (++) Auto-retry counter
+  [..]
+  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+  (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  The USART frame format is given in the following table:
+
+    Table 1. USART frame format.
+    +---------------------------------------------------------------+
+    | M1M0 bits |  PCE bit  |            USART frame                |
+    |-----------------------|---------------------------------------|
+    |     01    |    1      |    | SB | 8 bit data | PB | STB |     |
+    +---------------------------------------------------------------+
+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SMARTCARD mode according to the specified
+  *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if (hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsmartcard->Lock = HAL_UNLOCKED;
+
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+    SMARTCARD_InitCallbacksToDefault(hsmartcard);
+
+    if (hsmartcard->MspInitCallback == NULL)
+    {
+      hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hsmartcard->MspInitCallback(hsmartcard);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_SMARTCARD_MspInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+  }
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral to set smartcard mode */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* In SmartCard mode, the following bits must be kept cleared:
+  - LINEN in the USART_CR2 register,
+  - HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* set the USART in SMARTCARD mode */
+  SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+  /* Set the SMARTCARD Communication parameters */
+  if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the SMARTCARD transmission completion indication */
+  SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
+
+  if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+  {
+    SMARTCARD_AdvFeatureConfig(hsmartcard);
+  }
+
+  /* Enable the Peripheral */
+  SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+  return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD peripheral.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if (hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
+  WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
+  WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
+  WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
+  WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
+
+  /* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+  if (hsmartcard->MspDeInitCallback == NULL)
+  {
+    hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hsmartcard->MspDeInitCallback(hsmartcard);
+#else
+  HAL_SMARTCARD_MspDeInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+  hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
+  hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SMARTCARD Callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
+  *         in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+  *         and HAL_SMARTCARD_MSPDEINIT_CB_ID
+  * @param  hsmartcard smartcard handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+                                                 HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+                                                 pSMARTCARD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+
+      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+        hsmartcard->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+        hsmartcard->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ERROR_CB_ID :
+        hsmartcard->ErrorCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+        hsmartcard->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hsmartcard->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hsmartcard->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+        hsmartcard->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+        hsmartcard->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsmartcard->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsmartcard->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsmartcard->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsmartcard->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an SMARTCARD callback
+  *         SMARTCARD callback is redirected to the weak predefined callback
+  * @note   The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
+  *         in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+  *         and HAL_SMARTCARD_MSPDEINIT_CB_ID
+  * @param  hsmartcard smartcard handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+                                                   HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+        hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                 /* Legacy weak TxCpltCallback */
+        break;
+
+      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+        hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                 /* Legacy weak RxCpltCallback */
+        break;
+
+      case HAL_SMARTCARD_ERROR_CB_ID :
+        hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                   /* Legacy weak ErrorCallback  */
+        break;
+
+      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+        hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;           /* Legacy weak AbortCpltCallback */
+        break;
+
+      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+                                                                                            AbortTransmitCpltCallback*/
+        break;
+
+      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
+                                                                                           AbortReceiveCpltCallback */
+        break;
+
+      case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
+        hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback */
+        break;
+
+      case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
+        hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback;    /* Legacy weak TxFifoEmptyCallback */
+        break;
+
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;                       /* Legacy weak MspInitCallback  */
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                   /* Legacy weak MspDeInitCallback */
+        break;
+
+      default :
+        /* Update the error code */
+        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+  * @brief    SMARTCARD Transmit and Receive functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+  [..]
+    Smartcard is a single wire half duplex communication protocol.
+    The Smartcard interface is designed to support asynchronous protocol Smartcards as
+    defined in the ISO 7816-3 standard. The USART should be configured as:
+    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+  [..]
+    (#) There are two modes of transfer:
+        (##) Blocking mode: The communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (##) Non-Blocking mode: The communication is performed using Interrupts
+             or DMA, the relevant API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+        (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+             will be executed respectively at the end of the Transmit or Receive process
+             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+             error is detected.
+
+    (#) Blocking mode APIs are :
+        (##) HAL_SMARTCARD_Transmit()
+        (##) HAL_SMARTCARD_Receive()
+
+    (#) Non Blocking mode APIs with Interrupt are :
+        (##) HAL_SMARTCARD_Transmit_IT()
+        (##) HAL_SMARTCARD_Receive_IT()
+        (##) HAL_SMARTCARD_IRQHandler()
+
+    (#) Non Blocking mode functions with DMA are :
+        (##) HAL_SMARTCARD_Transmit_DMA()
+        (##) HAL_SMARTCARD_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (##) HAL_SMARTCARD_TxCpltCallback()
+        (##) HAL_SMARTCARD_RxCpltCallback()
+        (##) HAL_SMARTCARD_ErrorCallback()
+
+  [..]
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (##) HAL_SMARTCARD_Abort()
+        (##) HAL_SMARTCARD_AbortTransmit()
+        (##) HAL_SMARTCARD_AbortReceive()
+        (##) HAL_SMARTCARD_Abort_IT()
+        (##) HAL_SMARTCARD_AbortTransmit_IT()
+        (##) HAL_SMARTCARD_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+        a set of Abort Complete Callbacks are provided:
+        (##) HAL_SMARTCARD_AbortCpltCallback()
+        (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+        (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error,
+           Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer,
+           Error code is set to allow user to identify error type,
+           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+           If user wants to abort it, Abort services should be called by user.
+       (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+           mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type,
+           and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send an amount of data in blocking mode.
+  * @note   When FIFO mode is enabled, writing a data in the TDR register adds one
+  *         data to the TXFIFO. Write operations to the TDR register are performed
+  *         when TXFNF flag is set. From hardware perspective, TXFNF flag and
+  *         TXE are mapped on the same bit-field.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @param  Timeout  Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout)
+{
+  uint32_t tickstart;
+  const uint8_t  *ptmpdata = pData;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if ((ptmpdata == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+       the bidirectional line to detect a NACK signal in case of parity error.
+       Therefore, the receiver block must be enabled as well (RE bit must be set). */
+    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+    {
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    }
+    /* Enable Tx */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Perform a TX/RX FIFO Flush */
+    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    while (hsmartcard->TxXferCount > 0U)
+    {
+      hsmartcard->TxXferCount--;
+      if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
+      ptmpdata++;
+    }
+    if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+                                         tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Disable the Peripheral first to update mode */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+    {
+      /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+         for Transmit phase. Disable this receiver block. */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    }
+    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+        || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+    {
+      /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+      __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+    }
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* At end of Tx process, restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @note   When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *         is not empty. Read operations from the RDR register are performed when
+  *         RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *         RXNE are mapped on the same bit-field.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint8_t  *ptmpdata = pData;
+
+  /* Check that a Rx process is not already ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if ((ptmpdata == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Check the remain data to be received */
+    while (hsmartcard->RxXferCount > 0U)
+    {
+      hsmartcard->RxXferCount--;
+
+      if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+      ptmpdata++;
+    }
+
+    /* At end of Rx process, restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @note   When FIFO mode is disabled, USART interrupt is generated whenever
+  *         USART_TDR register is empty, i.e one interrupt per data to transmit.
+  * @note   When FIFO mode is enabled, USART interrupt is generated whenever
+  *         TXFIFO threshold reached. In that case the interrupt rate depends on
+  *         TXFIFO threshold configuration.
+  * @note   This function sets the hsmartcard->TxIsr function pointer according to
+  *         the FIFO mode (data transmission processing depends on FIFO mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->pTxBuffPtr  = pData;
+    hsmartcard->TxXferSize  = Size;
+    hsmartcard->TxXferCount = Size;
+    hsmartcard->TxISR       = NULL;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+       the bidirectional line to detect a NACK signal in case of parity error.
+       Therefore, the receiver block must be enabled as well (RE bit must be set). */
+    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+    {
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    }
+    /* Enable Tx */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Perform a TX/RX FIFO Flush */
+    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+    /* Configure Tx interrupt processing */
+    if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer */
+      hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+      /* Enable the TX FIFO threshold interrupt */
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer */
+      hsmartcard->TxISR = SMARTCARD_TxISR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+      /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @note   When FIFO mode is disabled, USART interrupt is generated whenever
+  *         USART_RDR register can be read, i.e one interrupt per data to receive.
+  * @note   When FIFO mode is enabled, USART interrupt is generated whenever
+  *         RXFIFO threshold reached. In that case the interrupt rate depends on
+  *         RXFIFO threshold configuration.
+  * @note   This function sets the hsmartcard->RxIsr function pointer according to
+  *         the FIFO mode (data reception processing depends on FIFO mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Configure Rx interrupt processing */
+    if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess))
+    {
+      /* Set the Rx ISR function pointer */
+      hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+    }
+    else
+    {
+      /* Set the Rx ISR function pointer */
+      hsmartcard->RxISR = SMARTCARD_RxISR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->pTxBuffPtr = pData;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+       the bidirectional line to detect a NACK signal in case of parity error.
+       Therefore, the receiver block must be enabled as well (RE bit must be set). */
+    if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+        && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+    {
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    }
+    /* Enable Tx */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Perform a TX/RX FIFO Flush */
+    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+    /* Set the SMARTCARD error callback */
+    hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+    /* Check linked list mode */
+    if ((hsmartcard->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hsmartcard->hdmatx->LinkedListQueue != NULL) && (hsmartcard->hdmatx->LinkedListQueue->Head != NULL))
+      {
+        /* Set DMA data size */
+        hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size;
+
+        /* Set DMA source address */
+        hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+          (uint32_t)hsmartcard->pTxBuffPtr;
+
+        /* Set DMA destination address */
+        hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+          (uint32_t)&hsmartcard->Instance->TDR;
+
+        /* Enable the SMARTCARD transmit DMA channel */
+        status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmatx);
+      }
+      else
+      {
+        /* Update status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable the SMARTCARD transmit DMA channel */
+      status = HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr,
+                                (uint32_t)&hsmartcard->Instance->TDR, Size);
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Clear the TC flag in the ICR register */
+      CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Enable the UART Error Interrupt: (Frame error) */
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+      /* Enable the DMA transfer for transmit request by setting the DMAT bit
+         in the SMARTCARD associated USART CR3 register */
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Set error code to DMA */
+      hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Restore hsmartcard->State to ready */
+      hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
+  *         the received data contain the parity bit (MSB position).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+    /* Set the SMARTCARD DMA error callback */
+    hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+    /* Check linked list mode  */
+    if ((hsmartcard->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hsmartcard->hdmarx->LinkedListQueue != NULL) && (hsmartcard->hdmarx->LinkedListQueue->Head != NULL))
+      {
+        /* Set DMA data size */
+        hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size;
+
+        /* Set DMA source address */
+        hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+          (uint32_t)&hsmartcard->Instance->RDR;
+
+        /* Set DMA destination address */
+        hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+          (uint32_t)hsmartcard->pRxBuffPtr;
+
+        /* Enable the SMARTCARD receive DMA channel */
+        status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmarx);
+      }
+      else
+      {
+        /* Update status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable the DMA channel */
+      status = HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR,
+                                (uint32_t)hsmartcard->pRxBuffPtr, Size);
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Enable the SMARTCARD Parity Error Interrupt */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+      /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+         in the SMARTCARD associated USART CR3 register */
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Set error code to DMA */
+      hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmartcard);
+
+      /* Restore hsmartcard->State to ready */
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+     ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1,
+            (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+             USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Tx and Rx transfer counters */
+  hsmartcard->TxXferCount = 0U;
+  hsmartcard->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Tx transfer counter */
+  hsmartcard->TxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and  ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+                                        USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Rx transfer counter */
+  hsmartcard->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+     ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1,
+            (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
+             USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+     DMA Abort complete callbacks should be initialised before any call
+     to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (hsmartcard->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+    {
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (hsmartcard->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+    {
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (hsmartcard->hdmatx != NULL)
+    {
+      /* SMARTCARD Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        hsmartcard->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (hsmartcard->hdmarx != NULL)
+    {
+      /* SMARTCARD Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        hsmartcard->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hsmartcard->TxXferCount = 0U;
+    hsmartcard->RxXferCount = 0U;
+
+    /* Clear ISR function pointers */
+    hsmartcard->RxISR = NULL;
+    hsmartcard->TxISR = NULL;
+
+    /* Reset errorCode */
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                               SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+                               SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+    hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+        hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hsmartcard->TxXferCount = 0U;
+
+      /* Clear TxISR function pointers */
+      hsmartcard->TxISR = NULL;
+
+      /* Restore hsmartcard->gState to Ready */
+      hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    }
+  }
+  else
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    /* Reset Tx transfer counter */
+    hsmartcard->TxXferCount = 0U;
+
+    /* Clear TxISR function pointers */
+    hsmartcard->TxISR = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+    /* Restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and  ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+                                        USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+        hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hsmartcard->RxXferCount = 0U;
+
+      /* Clear RxISR function pointer */
+      hsmartcard->RxISR = NULL;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                                 SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+                                 SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+      /* Restore hsmartcard->RxState to Ready */
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    }
+  }
+  else
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    /* Reset Rx transfer counter */
+    hsmartcard->RxXferCount = 0U;
+
+    /* Clear RxISR function pointer */
+    hsmartcard->RxISR = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                               SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+                               SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SMARTCARD interrupt requests.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
+  uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
+  uint32_t cr3its     = READ_REG(hsmartcard->Instance->CR3);
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == 0U)
+  {
+    /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (hsmartcard->RxISR != NULL)
+      {
+        hsmartcard->RxISR(hsmartcard);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))))
+  {
+    /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+    }
+
+    /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+    }
+
+    /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+    }
+
+    /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)
+            || ((cr3its & USART_CR3_EIE) != 0U)))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+    }
+
+    /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+    }
+
+    /* Call SMARTCARD Error Call back function if need be --------------------------*/
+    if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+    {
+      /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (hsmartcard->RxISR != NULL)
+        {
+          hsmartcard->RxISR(hsmartcard);
+        }
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = hsmartcard->ErrorCode;
+      if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+          || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        SMARTCARD_EndRxTransfer(hsmartcard);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+        /* Disable the SMARTCARD DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the SMARTCARD DMA Rx channel */
+          if (hsmartcard->hdmarx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback :
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+              hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+            }
+          }
+          else
+          {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+            /* Call registered user error callback */
+            hsmartcard->ErrorCallback(hsmartcard);
+#else
+            /* Call legacy weak user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+          }
+        }
+        else
+#endif /* HAL_DMA_MODULE_ENABLED */
+        {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+          /* Call registered user error callback */
+          hsmartcard->ErrorCallback(hsmartcard);
+#else
+          /* Call legacy weak user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+        }
+      }
+      /* other error type to be considered as blocking :
+          - Frame error in Transmission
+      */
+      else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+               && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+        SMARTCARD_EndTxTransfer(hsmartcard);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+        /* Disable the SMARTCARD DMA Tx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+          /* Abort the SMARTCARD DMA Tx channel */
+          if (hsmartcard->hdmatx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback :
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA TX */
+            if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+              hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+            }
+          }
+          else
+          {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+            /* Call registered user error callback */
+            hsmartcard->ErrorCallback(hsmartcard);
+#else
+            /* Call legacy weak user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+          }
+        }
+        else
+#endif /* HAL_DMA_MODULE_ENABLED */
+        {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+          /* Call registered user error callback */
+          hsmartcard->ErrorCallback(hsmartcard);
+#else
+          /* Call legacy weak user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+        /* Call registered user error callback */
+        hsmartcard->ErrorCallback(hsmartcard);
+#else
+        /* Call legacy weak user error callback */
+        HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+        hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+  if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
+  {
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+    __HAL_UNLOCK(hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx complete callback */
+    hsmartcard->RxCpltCallback(hsmartcard);
+#else
+    /* Call legacy weak Rx complete callback */
+    HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+       to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+    __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (hsmartcard->TxISR != NULL)
+    {
+      hsmartcard->TxISR(hsmartcard);
+    }
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+  if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+  {
+    if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+    {
+      SMARTCARD_EndTransmit_IT(hsmartcard);
+      return;
+    }
+  }
+
+  /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    hsmartcard->TxFifoEmptyCallback(hsmartcard);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    return;
+  }
+
+  /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    hsmartcard->RxFifoFullCallback(hsmartcard);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    return;
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD error callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Receive Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+  * @brief    SMARTCARD State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### Peripheral State and Errors functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to return the State of SmartCard
+    handle and also return Peripheral Errors occurred during communication process
+     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+         of the SMARTCARD peripheral.
+     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+         communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SMARTCARD handle state.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle state
+  */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Return SMARTCARD handle state */
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = (uint32_t)hsmartcard->gState;
+  temp2 = (uint32_t)hsmartcard->RxState;
+
+  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the SMARTCARD handle error code.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle Error Code
+  */
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  return hsmartcard->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+  * @{
+  */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  hsmartcard SMARTCARD handle.
+  * @retval none
+  */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Init the SMARTCARD Callback settings */
+  hsmartcard->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback    */
+  hsmartcard->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback    */
+  hsmartcard->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback     */
+  hsmartcard->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback */
+  hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+                                                                                      AbortTransmitCpltCallback     */
+  hsmartcard->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak
+                                                                                      AbortReceiveCpltCallback      */
+  hsmartcard->RxFifoFullCallback        = HAL_SMARTCARDEx_RxFifoFullCallback;      /* Legacy weak
+                                                                                      RxFifoFullCallback            */
+  hsmartcard->TxFifoEmptyCallback       = HAL_SMARTCARDEx_TxFifoEmptyCallback;     /* Legacy weak
+                                                                                      TxFifoEmptyCallback           */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Configure the SMARTCARD associated USART peripheral.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpreg;
+  uint64_t clocksource;
+  HAL_StatusTypeDef ret = HAL_OK;
+  static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+  assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+  assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+  assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+  assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+  assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+  assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+  assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+  assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+  assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+  assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+  assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+  assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+   * Oversampling is forced to 16 (OVER8 = 0).
+   * Configure the Parity and Mode:
+   *  set PS bit according to hsmartcard->Init.Parity value
+   *  set TE and RE bits according to hsmartcard->Init.Mode value */
+  tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
+            ((uint32_t)hsmartcard->Init.WordLength));
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = hsmartcard->Init.StopBits;
+  /* Synchronous mode is activated by default */
+  tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+  tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+  tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+  MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+   * - one-bit sampling method versus three samples' majority rule
+   *   according to hsmartcard->Init.OneBitSampling
+   * - NACK transmission in case of parity error according
+   *   to hsmartcard->Init.NACKEnable
+   * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+
+  tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+  tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
+  MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+  /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/
+  /* Configure
+  * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */
+  MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler);
+
+  /*-------------------------- USART GTPR Configuration ----------------------*/
+  tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
+  MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
+
+  /*-------------------------- USART RTOR Configuration ----------------------*/
+  tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
+  if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+  {
+    assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+    tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+  }
+  WRITE_REG(hsmartcard->Instance->RTOR, tmpreg);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+  pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+  tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+                       (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+
+  /* USARTDIV must be greater than or equal to 0d16 */
+  if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+  {
+    hsmartcard->Instance->BRR = (uint16_t)tmpreg;
+  }
+  else
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  hsmartcard->NbTxDataToProcess = 1U;
+  hsmartcard->NbRxDataToProcess = 1U;
+
+  /* Clear ISR function pointers */
+  hsmartcard->RxISR   = NULL;
+  hsmartcard->TxISR   = NULL;
+
+  return ret;
+}
+
+
+/**
+  * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                   the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+  }
+
+}
+
+/**
+  * @brief Check the SMARTCARD Idle State.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                   the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tickstart;
+
+  /* Initialize the SMARTCARD ErrorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
+                                         SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
+                                         SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the SMARTCARD states */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SMARTCARD Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                   the configuration information for the specified SMARTCARD module.
+  * @param  Flag Specifies the SMARTCARD flag to check.
+  * @param  Status The actual Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+                                                          FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+           interrupts for the interrupt process */
+        CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+        hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+        hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmartcard);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Tx process, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  DMA SMARTCARD transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+  hsmartcard->TxXferCount = 0U;
+
+  /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+  in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+  /* Enable the SMARTCARD Transmit Complete Interrupt */
+  __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+}
+
+/**
+  * @brief  DMA SMARTCARD receive process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+  hsmartcard->RxXferCount = 0U;
+
+  /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+     in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Rx complete callback */
+  hsmartcard->RxCpltCallback(hsmartcard);
+#else
+  /* Call legacy weak Rx complete callback */
+  HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA SMARTCARD communication error callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+  /* Stop SMARTCARD DMA Tx request if ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+  {
+    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+    {
+      hsmartcard->TxXferCount = 0U;
+      SMARTCARD_EndTxTransfer(hsmartcard);
+    }
+  }
+
+  /* Stop SMARTCARD DMA Rx request if ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+  {
+    if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+    {
+      hsmartcard->RxXferCount = 0U;
+      SMARTCARD_EndRxTransfer(hsmartcard);
+    }
+  }
+
+  hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hsmartcard->ErrorCallback(hsmartcard);
+#else
+  /* Call legacy weak user error callback */
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+  hsmartcard->RxXferCount = 0U;
+  hsmartcard->TxXferCount = 0U;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hsmartcard->ErrorCallback(hsmartcard);
+#else
+  /* Call legacy weak user error callback */
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+  hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hsmartcard->hdmarx != NULL)
+  {
+    if (hsmartcard->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0U;
+  hsmartcard->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+  hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hsmartcard->hdmatx != NULL)
+  {
+    if (hsmartcard->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0U;
+  hsmartcard->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+  hsmartcard->TxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
+  hsmartcard->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+                             SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+                             SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+  *         and when the FIFO mode is disabled.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Tx process is ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+  {
+    if (hsmartcard->TxXferCount == 0U)
+    {
+      /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the SMARTCARD Transmit Complete Interrupt */
+      __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+    }
+    else
+    {
+      hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+      hsmartcard->pTxBuffPtr++;
+      hsmartcard->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+  *         and when the FIFO mode is enabled.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint16_t   nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (hsmartcard->TxXferCount == 0U)
+      {
+        /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+        CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+        /* Enable the SMARTCARD Transmit Complete Interrupt */
+        __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+      }
+      else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+        hsmartcard->pTxBuffPtr++;
+        hsmartcard->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable the SMARTCARD Transmit Complete Interrupt */
+  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the Peripheral first to update mode */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+  if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+      && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+  {
+    /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+       for Transmit phase. Disable this receiver block. */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+  }
+  if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+      || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+  {
+    /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+    __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+  }
+  SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* Tx process is ended, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Clear TxISR function pointer */
+  hsmartcard->TxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx complete callback */
+  hsmartcard->TxCpltCallback(hsmartcard);
+#else
+  /* Call legacy weak Tx complete callback */
+  HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+  *         and when the FIFO mode is disabled.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Rx process is ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+  {
+    *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+    hsmartcard->pRxBuffPtr++;
+
+    hsmartcard->RxXferCount--;
+    if (hsmartcard->RxXferCount == 0U)
+    {
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+      /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+      if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+      {
+        /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+      }
+
+      /* Disable the SMARTCARD Parity Error Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx complete callback */
+      hsmartcard->RxCpltCallback(hsmartcard);
+#else
+      /* Call legacy weak Rx complete callback */
+      HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+  *         and when the FIFO mode is enabled.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint16_t   nb_rx_data;
+  uint16_t rxdatacount;
+
+  /* Check that a Rx process is ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+  {
+    for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+    {
+      *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+      hsmartcard->pRxBuffPtr++;
+
+      hsmartcard->RxXferCount--;
+      if (hsmartcard->RxXferCount == 0U)
+      {
+        CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+        /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+        if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+        {
+          /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+        }
+
+        /* Disable the SMARTCARD Parity Error Interrupt */
+        CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+        hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+        /* Call registered Rx complete callback */
+        hsmartcard->RxCpltCallback(hsmartcard);
+#else
+        /* Call legacy weak Rx complete callback */
+        HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = hsmartcard->RxXferCount;
+    if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      hsmartcard->RxISR = SMARTCARD_RxISR;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smartcard_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smartcard_ex.c
new file mode 100644
index 000000000..4e9fd6a7c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smartcard_ex.c
@@ -0,0 +1,495 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smartcard_ex.c
+  * @author  MCD Application Team
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides extended firmware functions to manage the following
+  *          functionalities of the SmartCard.
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  =============================================================================
+               ##### SMARTCARD peripheral extended features  #####
+  =============================================================================
+  [..]
+  The Extended SMARTCARD HAL driver can be used as follows:
+
+    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+  * @brief SMARTCARD Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 16U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 16U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  * @brief    Extended control functions
+  *
+@verbatim
+  ===============================================================================
+                      ##### Peripheral Control functions #####
+  ===============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the SMARTCARD.
+     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+  * @{
+  */
+
+/** @brief Update on the fly the SMARTCARD block length in RTOR register.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param BlockLength SMARTCARD block length (8-bit long at most)
+  * @retval None
+  */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
+}
+
+/** @brief Update on the fly the receiver timeout value in RTOR register.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+  assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/** @brief Enable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Set the USART RTOEN bit */
+    SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/** @brief Disable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Clear the USART RTOEN bit */
+    CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
+  * @brief   SMARTCARD Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of FIFO mode related callback functions.
+
+    (#) TX/RX Fifos Callbacks:
+        (++) HAL_SMARTCARDEx_RxFifoFullCallback()
+        (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  SMARTCARD RX Fifo full callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                   the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD TX Fifo empty callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                   the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
+  *  @brief   SMARTCARD control functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral FIFO Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SMARTCARD
+    FIFO feature.
+     (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param hsmartcard SMARTCARD handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
+
+  /* Restore SMARTCARD configuration */
+  WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param hsmartcard SMARTCARD handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
+
+  /* Restore SMARTCARD configuration */
+  WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param hsmartcard      SMARTCARD handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+  /* Restore SMARTCARD configuration */
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param hsmartcard      SMARTCARD handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+  /* Restore SMARTCARD configuration */
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Private_Functions  SMARTCARD Extended Private Functions
+  * @{
+  */
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the USART configuration registers.
+  * @param hsmartcard SMARTCARD handle.
+  * @retval None
+  */
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+  static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
+  {
+    hsmartcard->NbTxDataToProcess = 1U;
+    hsmartcard->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+                                    (uint16_t)denominator[tx_fifo_threshold];
+    hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+                                    (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smbus.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smbus.c
new file mode 100644
index 000000000..d5a65ba4c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smbus.c
@@ -0,0 +1,2776 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smbus.c
+  * @author  MCD Application Team
+  * @brief   SMBUS HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the System Management Bus (SMBus) peripheral,
+  *          based on I2C principles of operation :
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The SMBUS HAL driver can be used as follows:
+
+    (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+        SMBUS_HandleTypeDef  hsmbus;
+
+    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+        (##) Enable the SMBUSx interface clock
+        (##) SMBUS pins configuration
+            (+++) Enable the clock for the SMBUS GPIOs
+            (+++) Configure SMBUS pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the SMBUSx interrupt priority
+            (+++) Enable the NVIC SMBUS IRQ Channel
+
+    (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+        Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+        Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+        (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+
+    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+
+    (#) For SMBUS IO operations, only one mode of operations is available within this driver
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Master_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Master_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+      (++) The associated previous transfer callback is called at the end of abort process
+      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+      (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
+           add their own code to check the Address Match Code and the transmission direction
+           request by master/host (Write/Read).
+      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Slave_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Slave_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+      (+) Enable/Disable the SMBUS alert mode using
+          HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
+      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Alert Error Code using function HAL_SMBUS_GetError()
+      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Error Code using function HAL_SMBUS_GetError()
+
+     *** SMBUS HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in SMBUS HAL driver.
+
+      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
+      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
+      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
+      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
+      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
+      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) ErrorCallback        : callback for error detection.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
+    [..]
+     Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+     weak function.
+     HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) ErrorCallback        : callback for error detection.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
+    [..]
+     By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
+     or HAL_SMBUS_Init() function.
+    [..]
+     When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMBUS SMBUS
+  * @brief SMBUS HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFUL)     /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR    (10000U)           /*!< 10 s  */
+#define HAL_TIMEOUT_BUSY    (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_DIR     (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE    (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF   (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TC      (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TCR     (25U)              /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS    (25U)              /*!< 25 ms */
+#define MAX_NBYTE_SIZE      255U
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+  * @{
+  */
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+                                                      FlagStatus Status, uint32_t Timeout);
+
+/* Private functions for SMBUS transfer IRQ handler */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+
+/* Private function to flush TXDR register */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private function to handle start, restart or stop a transfer */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
+                                 uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+  * @{
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the SMBUSx peripheral:
+
+      (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+      (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Bus Timeout
+        (++) Analog Filer mode
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+        (++) Packet Error Check mode
+        (++) Peripheral mode
+
+
+      (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+          of the selected SMBUSx peripheral.
+
+      (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+          HAL_SMBUS_ConfigDigitalFilter().
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SMBUS according to the specified parameters
+  *         in the SMBUS_InitTypeDef and initialize the associated handle.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the SMBUS handle allocation */
+  if (hsmbus == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+  assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+  assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+  assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+  assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+  assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+  assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+  assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+  assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+  assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsmbus->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+    hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hsmbus->SlaveTxCpltCallback  = HAL_SMBUS_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hsmbus->SlaveRxCpltCallback  = HAL_SMBUS_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hsmbus->ListenCpltCallback   = HAL_SMBUS_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hsmbus->ErrorCallback        = HAL_SMBUS_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hsmbus->AddrCallback         = HAL_SMBUS_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hsmbus->MspInitCallback == NULL)
+    {
+      hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hsmbus->MspInitCallback(hsmbus);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_SMBUS_MspInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+  }
+
+  hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+  /* Disable the selected SMBUS peripheral */
+  __HAL_SMBUS_DISABLE(hsmbus);
+
+  /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+  /* Configure SMBUSx: Frequency range */
+  hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+  /* Configure SMBUSx: Bus Timeout  */
+  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+  hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+  hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+  /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+  /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+  hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  if (hsmbus->Init.OwnAddress1 != 0UL)
+  {
+    if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+    {
+      hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+    }
+  }
+
+  /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+  /* AUTOEND and NACK bit will be manage during Transfer process */
+  hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+  /* Configure SMBUSx: Dual mode and Own Address2 */
+  hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
+                            (hsmbus->Init.OwnAddress2Masks << 8U));
+
+  /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+  /* Configure SMBUSx: Generalcall and NoStretch mode */
+  hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
+                           hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
+                           hsmbus->Init.AnalogFilter);
+
+  /* Enable Slave Byte Control only in case of Packet Error Check is enabled
+     and SMBUS Peripheral is set in Slave mode */
+  if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
+      ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+       (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+  {
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+  }
+
+  /* Enable the selected SMBUS peripheral */
+  __HAL_SMBUS_ENABLE(hsmbus);
+
+  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+  hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+  hsmbus->State = HAL_SMBUS_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the SMBUS peripheral.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the SMBUS handle allocation */
+  if (hsmbus == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+
+  hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+  /* Disable the SMBUS Peripheral Clock */
+  __HAL_SMBUS_DISABLE(hsmbus);
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+  if (hsmbus->MspDeInitCallback == NULL)
+  {
+    hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hsmbus->MspDeInitCallback(hsmbus);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_SMBUS_MspDeInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+  hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+  hsmbus->PreviousState =  HAL_SMBUS_STATE_RESET;
+  hsmbus->State = HAL_SMBUS_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsmbus);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the SMBUS MSP.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the SMBUS MSP.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Configure Analog noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  AnalogFilter This parameter can be one of the following values:
+  *         @arg @ref SMBUS_ANALOGFILTER_ENABLE
+  *         @arg @ref SMBUS_ANALOGFILTER_DISABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Reset ANOFF bit */
+    hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hsmbus->Instance->CR1 |= AnalogFilter;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure Digital noise filter.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Get the old register value */
+    tmpreg = hsmbus->Instance->CR1;
+
+    /* Reset I2C DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+    /* Store the new register value */
+    hsmbus->Instance->CR1 = tmpreg;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SMBUS Callback
+  *         To be used instead of the weak predefined callback
+  * @note   The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
+  *         HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+  *         HAL_SMBUS_MSPDEINIT_CB_ID.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                             HAL_SMBUS_CallbackIDTypeDef CallbackID,
+                                             pSMBUS_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_SMBUS_STATE_READY == hsmbus->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+        hsmbus->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+        hsmbus->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+        hsmbus->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+        hsmbus->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+        hsmbus->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_ERROR_CB_ID :
+        hsmbus->ErrorCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_MSPINIT_CB_ID :
+        hsmbus->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_MSPDEINIT_CB_ID :
+        hsmbus->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMBUS_MSPINIT_CB_ID :
+        hsmbus->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SMBUS_MSPDEINIT_CB_ID :
+        hsmbus->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an SMBUS Callback
+  *         SMBUS callback is redirected to the weak predefined callback
+  * @note   The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
+  *         HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+  *         HAL_SMBUS_MSPDEINIT_CB_ID
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                               HAL_SMBUS_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_SMBUS_STATE_READY == hsmbus->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+        hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+        hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+        hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+        hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+        hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_SMBUS_ERROR_CB_ID :
+        hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_SMBUS_MSPINIT_CB_ID :
+        hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_SMBUS_MSPDEINIT_CB_ID :
+        hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMBUS_MSPINIT_CB_ID :
+        hsmbus->MspInitCallback = HAL_SMBUS_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_SMBUS_MSPDEINIT_CB_ID :
+        hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match SMBUS Callback
+  *         To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+                                                 pSMBUS_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_SMBUS_STATE_READY == hsmbus->State)
+  {
+    hsmbus->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match SMBUS Callback
+  *         Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_SMBUS_STATE_READY == hsmbus->State)
+  {
+    hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the SMBUS data
+    transfers.
+
+    (#) Blocking mode function to check if device is ready for usage is :
+        (++) HAL_SMBUS_IsDeviceReady()
+
+    (#) There is only one mode of transfer:
+       (++) Non-Blocking mode : The communication is performed using Interrupts.
+            These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated SMBUS IRQ when using Interrupt mode.
+
+    (#) Non-Blocking mode functions with Interrupt are :
+        (++) HAL_SMBUS_Master_Transmit_IT()
+        (++) HAL_SMBUS_Master_Receive_IT()
+        (++) HAL_SMBUS_Slave_Transmit_IT()
+        (++) HAL_SMBUS_Slave_Receive_IT()
+        (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
+        (++) HAL_SMBUS_DisableListen_IT()
+        (++) HAL_SMBUS_EnableAlert_IT()
+        (++) HAL_SMBUS_DisableAlert_IT()
+
+    (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+        (++) HAL_SMBUS_MasterTxCpltCallback()
+        (++) HAL_SMBUS_MasterRxCpltCallback()
+        (++) HAL_SMBUS_SlaveTxCpltCallback()
+        (++) HAL_SMBUS_SlaveRxCpltCallback()
+        (++) HAL_SMBUS_AddrCallback()
+        (++) HAL_SMBUS_ListenCpltCallback()
+        (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* In case of Quick command, remove autoend mode */
+    /* Manage the stop generation by software */
+    if (hsmbus->pBuffPtr == NULL)
+    {
+      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+    }
+
+    if (Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+    {
+      SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                           SMBUS_GENERATE_START_WRITE);
+    }
+    else
+    {
+      /* If transfer direction not change, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+
+      /* Store current volatile XferOptions, misra rule */
+      tmp = hsmbus->XferOptions;
+
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
+          (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+      {
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                             SMBUS_NO_STARTSTOP);
+      }
+      /* Else transfer direction change, so generate Restart with new transfer direction */
+      else
+      {
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+                             hsmbus->XferOptions,
+                             SMBUS_GENERATE_START_WRITE);
+      }
+
+      /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+      if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+      {
+        if (hsmbus->XferSize > 0U)
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+        else
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+                                              uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* In case of Quick command, remove autoend mode */
+    /* Manage the stop generation by software */
+    if (hsmbus->pBuffPtr == NULL)
+    {
+      hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+    }
+
+    if (Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+    {
+      SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+                           SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                           SMBUS_GENERATE_START_READ);
+    }
+    else
+    {
+      /* If transfer direction not change, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+
+      /* Store current volatile XferOptions, Misra rule */
+      tmp = hsmbus->XferOptions;
+
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
+          (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+      {
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                             SMBUS_NO_STARTSTOP);
+      }
+      /* Else transfer direction change, so generate Restart with new transfer direction */
+      else
+      {
+        /* Convert OTHER_xxx XferOptions if any */
+        SMBUS_ConvertOtherXferOptions(hsmbus);
+
+        /* Handle Transfer */
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+                             hsmbus->XferOptions,
+                             SMBUS_GENERATE_START_READ);
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master/host SMBUS process communication with Interrupt.
+  * @note   This abort can be called only if state is ready
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    /* Keep the same state as previous */
+    /* to perform as well the call of the corresponding end of transfer callback */
+    if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+    }
+    else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Wrong usage of abort function */
+      /* This function should be used only in case of abort monitored by master device */
+      return HAL_ERROR;
+    }
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+    }
+    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+                                              uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0UL))
+    {
+      hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+      return HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Set SBC bit to manage Acknowledge at each bit */
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+    /* Enable Address Acknowledge */
+    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
+    if (Size > MAX_NBYTE_SIZE)
+    {
+      hsmbus->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hsmbus->XferSize = Size;
+    }
+
+    /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+    if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+    {
+      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
+                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                           SMBUS_NO_STARTSTOP);
+    }
+    else
+    {
+      /* Set NBYTE to transmit */
+      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                           SMBUS_NO_STARTSTOP);
+
+      /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+      /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+      if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+      {
+        hsmbus->XferSize--;
+        hsmbus->XferCount--;
+      }
+    }
+
+    /* Clear ADDR flag after prepare the transfer parameters */
+    /* This action will generate an acknowledge to the HOST */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    /* REnable ADDR interrupt */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+                                             uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0UL))
+    {
+      hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+      return HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    /* Set SBC bit to manage Acknowledge at each bit */
+    hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+    /* Enable Address Acknowledge */
+    hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hsmbus->pBuffPtr = pData;
+    hsmbus->XferSize = Size;
+    hsmbus->XferCount = Size;
+    hsmbus->XferOptions = XferOptions;
+
+    /* Convert OTHER_xxx XferOptions if any */
+    SMBUS_ConvertOtherXferOptions(hsmbus);
+
+    /* Set NBYTE to receive */
+    /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+    /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+    /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+    /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+    if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
+    {
+      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                           SMBUS_NO_STARTSTOP);
+    }
+    else
+    {
+      SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+    }
+
+    /* Clear ADDR flag after prepare the transfer parameters */
+    /* This action will generate an acknowledge to the HOST */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Note : The SMBUS interrupts must be enabled after unlocking current process
+              to avoid the risk of SMBUS interrupt handle execution before current
+              process unlock */
+    /* REnable ADDR interrupt */
+    SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+  /* Enable the Address Match interrupt */
+  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+  {
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Disable the Address Match interrupt */
+    SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the SMBUS alert mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Enable SMBus alert */
+  hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+
+  /* Clear ALERT flag */
+  __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+  /* Enable Alert Interrupt */
+  SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Disable the SMBUS alert mode with Interrupt.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Enable SMBus alert */
+  hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
+  /* Disable Alert Interrupt */
+  SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if target device is ready for communication.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+                                          uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t SMBUS_Trials = 0UL;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+    hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+          {
+            /* Device is ready */
+            hsmbus->State = HAL_SMBUS_STATE_READY;
+
+            /* Update SMBUS error code */
+            hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hsmbus);
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+        tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+        /* Device is ready */
+        hsmbus->State = HAL_SMBUS_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmbus);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (SMBUS_Trials == Trials)
+      {
+        /* Generate Stop */
+        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */
+        if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+      }
+
+      /* Increment Trials */
+      SMBUS_Trials++;
+    } while (SMBUS_Trials < Trials);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Update SMBUS error code */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+
+/**
+  * @brief  Handle SMBUS event interrupt request.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Use a local variable to store the current ISR flags */
+  /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+  uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
+  uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
+
+  /* SMBUS in mode Transmitter ---------------------------------------------------*/
+  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+                                           SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
+      ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+  {
+    /* Slave mode selected */
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+    {
+      (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+    }
+    /* Master mode selected */
+    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /* SMBUS in mode Receiver ----------------------------------------------------*/
+  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+                                           SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
+      ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+  {
+    /* Slave mode selected */
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+    {
+      (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+    }
+    /* Master mode selected */
+    else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /* SMBUS in mode Listener Only --------------------------------------------------*/
+  if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
+       (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
+       (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
+      ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+       (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+  {
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+    {
+      (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
+    }
+  }
+}
+
+/**
+  * @brief  Handle SMBUS error interrupt request.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  SMBUS_ITErrorHandler(hsmbus);
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read)
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+                                   uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SMBUS error callback.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval None
+  */
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmbus);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMBUS_ErrorCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   Peripheral State and Errors functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SMBUS handle state.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @retval HAL state
+  */
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Return SMBUS handle state */
+  return hsmbus->State;
+}
+
+/**
+  * @brief  Return the SMBUS error code.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *              the configuration information for the specified SMBUS.
+  * @retval SMBUS Error Code
+  */
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus)
+{
+  return hsmbus->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+  *  @brief   Data transfers Private functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  StatusFlags Value of Interrupt Flags.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+{
+  uint16_t DevAddress;
+
+  /* Process Locked */
+  __HAL_LOCK(hsmbus);
+
+  if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+    /* Flush TX register */
+    SMBUS_Flush_TXDR(hsmbus);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+    hsmbus->ErrorCallback(hsmbus);
+#else
+    HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+  }
+  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
+  {
+    /* Check and treat errors if errors occurs during STOP process */
+    SMBUS_ITErrorHandler(hsmbus);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+    {
+      /* Disable Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+
+      /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+      /* Disable the selected SMBUS peripheral */
+      __HAL_SMBUS_DISABLE(hsmbus);
+
+      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Re-enable the selected SMBUS peripheral */
+      __HAL_SMBUS_ENABLE(hsmbus);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+      hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+      HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+    }
+    else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+    {
+      /* Store Last receive data if any */
+      if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
+      {
+        /* Read data from RXDR */
+        *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+        /* Increment Buffer pointer */
+        hsmbus->pBuffPtr++;
+
+        if (hsmbus->XferSize > 0U)
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+
+      /* Disable Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+
+      hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+      hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+      HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+    /* Increment Buffer pointer */
+    hsmbus->pBuffPtr++;
+
+    /* Increment Size counter */
+    hsmbus->XferSize--;
+    hsmbus->XferCount--;
+  }
+  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
+  {
+    /* Write data to TXDR */
+    hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hsmbus->pBuffPtr++;
+
+    /* Increment Size counter */
+    hsmbus->XferSize--;
+    hsmbus->XferCount--;
+  }
+  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
+  {
+    if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
+    {
+      DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+      {
+        SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
+                             (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+                             SMBUS_NO_STARTSTOP);
+        hsmbus->XferSize = MAX_NBYTE_SIZE;
+      }
+      else
+      {
+        hsmbus->XferSize = hsmbus->XferCount;
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                             SMBUS_NO_STARTSTOP);
+        /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+        /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+        if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+    }
+    else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        {
+          /* Disable Interrupt */
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+          hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+        }
+        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        {
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+          hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+        }
+        else
+        {
+          /* Nothing to do */
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
+  {
+    if (hsmbus->XferCount == 0U)
+    {
+      /* Specific use case for Quick command */
+      if (hsmbus->pBuffPtr == NULL)
+      {
+        /* Generate a Stop command */
+        hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+      }
+      /* Call TxCpltCallback() if no stop mode is set */
+      else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+      {
+        /* No Generate Stop, to permit restart mode */
+        /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+        {
+          /* Disable Interrupt */
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+          hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+          HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+        }
+        else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+        {
+          SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+          hsmbus->PreviousState = hsmbus->State;
+          hsmbus->State = HAL_SMBUS_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hsmbus);
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+          hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+          HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+        }
+        else
+        {
+          /* Nothing to do */
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmbus);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  StatusFlags Value of Interrupt Flags.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+{
+  uint8_t TransferDirection;
+  uint16_t SlaveAddrCode;
+
+  /* Process Locked */
+  __HAL_LOCK(hsmbus);
+
+  if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
+  {
+    /* Check that SMBUS transfer finished */
+    /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hsmbus->XferCount == 0U)
+    {
+      /* Clear NACK Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      /* Flush TX register */
+      SMBUS_Flush_TXDR(hsmbus);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+    }
+    else
+    {
+      /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+      /* Clear NACK Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+      /* Set HAL State to "Idle" State, mean to LISTEN state */
+      /* So reset Slave Busy state */
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+      /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+      /* Flush TX register */
+      SMBUS_Flush_TXDR(hsmbus);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+      hsmbus->ErrorCallback(hsmbus);
+#else
+      HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+    }
+  }
+  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
+  {
+    TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
+    SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
+
+    /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+    /* Other ADDRInterrupt will be treat in next Listen usecase */
+    __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    /* Call Slave Addr callback */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+    hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#else
+    HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+  }
+  else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
+           (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
+  {
+    if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+    {
+      /* Read data from RXDR */
+      *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+      /* Increment Buffer pointer */
+      hsmbus->pBuffPtr++;
+
+      hsmbus->XferSize--;
+      hsmbus->XferCount--;
+
+      if (hsmbus->XferCount == 1U)
+      {
+        /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+        /* or only the last Byte of Transfer */
+        /* So reset the RELOAD bit mode */
+        hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+        SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      }
+      else if (hsmbus->XferCount == 0U)
+      {
+        /* Last Byte is received, disable Interrupt */
+        SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+        /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+        hsmbus->PreviousState = hsmbus->State;
+        hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmbus);
+
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+        hsmbus->SlaveRxCpltCallback(hsmbus);
+#else
+        HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        /* Set Reload for next Bytes */
+        SMBUS_TransferConfig(hsmbus, 0, 1,
+                             SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                             SMBUS_NO_STARTSTOP);
+
+        /* Ack last Byte Read */
+        hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+      }
+    }
+    else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+    {
+      if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
+      {
+        if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+        {
+          SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
+                               (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+                               SMBUS_NO_STARTSTOP);
+          hsmbus->XferSize = MAX_NBYTE_SIZE;
+        }
+        else
+        {
+          hsmbus->XferSize = hsmbus->XferCount;
+          SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                               SMBUS_NO_STARTSTOP);
+          /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+          /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+          if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
+          {
+            hsmbus->XferSize--;
+            hsmbus->XferCount--;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Data have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hsmbus->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hsmbus->pBuffPtr++;
+
+      hsmbus->XferCount--;
+      hsmbus->XferSize--;
+    }
+
+    if (hsmbus->XferCount == 0U)
+    {
+      /* Last Byte is Transmitted */
+      /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+      hsmbus->SlaveTxCpltCallback(hsmbus);
+#else
+      HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Check if STOPF is set */
+  if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
+  {
+    if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Store Last receive data if any */
+      if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+      {
+        /* Read data from RXDR */
+        *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+        /* Increment Buffer pointer */
+        hsmbus->pBuffPtr++;
+
+        if (hsmbus->XferSize > 0U)
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+      }
+
+      /* Disable RX and TX Interrupts */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+      /* Disable ADDR Interrupt */
+      SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+      /* Disable Address Acknowledge */
+      hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+      /* Clear Configuration Register 2 */
+      SMBUS_RESET_CR2(hsmbus);
+
+      /* Clear STOP Flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+      /* Clear ADDR flag */
+      __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+
+      hsmbus->XferOptions = 0;
+      hsmbus->PreviousState = hsmbus->State;
+      hsmbus->State = HAL_SMBUS_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hsmbus);
+
+      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+      hsmbus->ListenCpltCallback(hsmbus);
+#else
+      HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmbus);
+
+  return HAL_OK;
+}
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+{
+  uint32_t tmpisr = 0UL;
+
+  if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+  {
+    /* Enable ERR interrupt */
+    tmpisr |= SMBUS_IT_ERRI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+  {
+    /* Enable ADDR, STOP interrupt */
+    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+  {
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+  {
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of SMBUS interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+}
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+  * @retval HAL status
+  */
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+{
+  uint32_t tmpisr = 0UL;
+  uint32_t tmpstate = hsmbus->State;
+
+  if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
+  {
+    /* Disable ERR interrupt */
+    tmpisr |= SMBUS_IT_ERRI;
+  }
+
+  if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+  {
+    /* Disable TC, STOP, NACK and TXI interrupt */
+    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+
+    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+        && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+
+    if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Disable STOP and NACK interrupt */
+      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+    }
+  }
+
+  if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+  {
+    /* Disable TC, STOP, NACK and RXI interrupt */
+    tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+
+    if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+        && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+
+    if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+    {
+      /* Disable STOP and NACK interrupt */
+      tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+    }
+  }
+
+  if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+  {
+    /* Disable ADDR, STOP and NACK interrupt */
+    tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+    if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+    {
+      /* Disable ERR interrupt */
+      tmpisr |= SMBUS_IT_ERRI;
+    }
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+}
+
+/**
+  * @brief  SMBUS interrupts error handler.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+  uint32_t itflags   = READ_REG(hsmbus->Instance->ISR);
+  uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+  uint32_t tmpstate;
+  uint32_t tmperror;
+
+  /* SMBUS Bus error interrupt occurred ------------------------------------*/
+  if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+  }
+
+  /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+  }
+
+  /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+  if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+  }
+
+  /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+  if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+    /* Clear TIMEOUT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+  }
+
+  /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+  if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+    /* Clear ALERT flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+  }
+
+  /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+  if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  {
+    hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+    /* Clear PEC error flag */
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+  }
+
+  if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+  {
+    /* Flush TX register */
+    SMBUS_Flush_TXDR(hsmbus);
+  }
+
+  /* Store current volatile hsmbus->ErrorCode, misra rule */
+  tmperror = hsmbus->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
+  {
+    /* Do not Reset the HAL state in case of ALERT error */
+    if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+    {
+      /* Store current volatile hsmbus->State, misra rule */
+      tmpstate = hsmbus->State;
+
+      if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+          || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+      {
+        /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+        /* keep HAL_SMBUS_STATE_LISTEN if set */
+        hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+        hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+      }
+    }
+
+    /* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+    hsmbus->ErrorCallback(hsmbus);
+#else
+    HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Handle SMBUS Communication Timeout.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUS.
+  * @param  Flag Specifies the SMBUS flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+                                                      FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait until flag is set */
+  while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        hsmbus->PreviousState = hsmbus->State;
+        hsmbus->State = HAL_SMBUS_STATE_READY;
+
+        /* Update SMBUS error code */
+        hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmbus);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SMBUS Tx data register flush process.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  {
+    hsmbus->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET)
+  {
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hsmbus SMBUS handle.
+  * @param  DevAddress specifies the slave address to be programmed.
+  * @param  Size specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the SMBUS START condition generation.
+  *   This parameter can be one or a combination  of the following values:
+  *     @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
+  *     @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+  *     @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+  * @param  Request New state of the SMBUS START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
+                                 uint32_t Mode, uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+  assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+
+  /* update CR2 register */
+  MODIFY_REG(hsmbus->Instance->CR2,
+             ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
+               I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+                        (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                        (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+  * @brief  Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC   */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to SMBUS_FIRST_FRAME                  */
+  if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition      */
+  /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE  */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+  /* it request implicitly to generate a restart condition             */
+  /* then generate a stop condition at the end of transfer             */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC              */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+  }
+  /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+  /* it request implicitly to generate a restart condition               */
+  /* then generate a stop condition at the end of transfer               */
+  /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC              */
+  else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+  {
+    hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smbus_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smbus_ex.c
new file mode 100644
index 000000000..eddb3cefd
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_smbus_ex.c
@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_smbus_ex.c
+  * @author  MCD Application Team
+  * @brief   SMBUS Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of SMBUS Extended peripheral:
+  *           + Extended features functions
+  *           + WakeUp Mode Functions
+  *           + FastModePlus Functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### SMBUS peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the SMBUS interface for STM32N6xx
+       devices contains the following additional features
+
+       (+) Disable or enable wakeup from Stop mode(s)
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
+          (++) HAL_SMBUSEx_EnableWakeUp()
+          (++) HAL_SMBUSEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_SMBUSEx_ConfigFastModePlus()
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMBUSEx SMBUSEx
+  * @brief SMBUS Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @brief    WakeUp Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### WakeUp Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Wake Up Feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable SMBUS wakeup from Stop mode(s).
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Enable wakeup from stop mode */
+    hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable SMBUS wakeup from Stop mode(s).
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Disable wakeup from stop mode */
+    hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @brief    Fast Mode Plus Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Fast Mode Plus Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure SMBUS Fast Mode Plus.
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @param  FastModePlus New state of the Fast Mode Plus.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus)
+{
+  /* Check the parameters */
+  assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+  assert_param(IS_SMBUS_FASTMODEPLUS(FastModePlus));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    if (FastModePlus == SMBUS_FASTMODEPLUS_ENABLE)
+    {
+      /* Set SMBUSx FMP bit */
+      hsmbus->Instance->CR1 |= (I2C_CR1_FMP);
+    }
+    else
+    {
+      /* Reset SMBUSx FMP bit */
+      hsmbus->Instance->CR1 &= ~(I2C_CR1_FMP);
+    }
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spdifrx.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spdifrx.c
new file mode 100644
index 000000000..1e5a341ee
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spdifrx.c
@@ -0,0 +1,1741 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_spdifrx.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the SPDIFRX audio interface:
+  *           + Initialization and Configuration
+  *           + Data transfers functions
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                  ##### How to use this driver #####
+ ===============================================================================
+ [..]
+    The SPDIFRX HAL driver can be used as follow:
+
+    (#) Declare SPDIFRX_HandleTypeDef handle structure.
+    (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:
+        (##) Enable the SPDIFRX interface clock.
+        (##) SPDIFRX pins configuration:
+            (+++) Enable the clock for the SPDIFRX GPIOs.
+            (+++) Configure these SPDIFRX pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and
+             HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
+            (+++) Configure the SPDIFRX interrupt priority.
+            (+++) Enable the NVIC SPDIFRX IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and
+             HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's).
+            (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
+            (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.
+            (+++) Configure the DMA Channel.
+            (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+                DMA CtrlRx/DataRx channel.
+
+   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format,
+       stereo mode and masking of user bits using HAL_SPDIFRX_Init() function.
+
+   -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
+       __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
+   -@- Make sure that ck_spdif clock is configured.
+
+   (#) Three operation modes are available within this driver :
+
+   *** Polling mode for reception operation (for debug purpose) ***
+   ================================================================
+   [..]
+     (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
+     (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow()
+
+   *** Interrupt mode for reception operation ***
+   =========================================
+   [..]
+     (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT()
+     (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveCtrlFlow_IT()
+     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+
+   *** DMA mode for reception operation ***
+   ========================================
+   [..]
+     (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA()
+     (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveCtrlFlow_DMA()
+     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback
+     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback
+     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can
+         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback
+     (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()
+
+   *** SPDIFRX HAL driver macros list ***
+   =============================================
+   [..]
+     Below the list of most used macros in SPDIFRX HAL driver.
+      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDLE State)
+      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
+      (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
+      (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
+      (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts
+      (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.
+
+   [..]
+      (@) You can refer to the SPDIFRX HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use HAL_SPDIFRX_RegisterCallback() function to register an interrupt callback.
+
+  The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks:
+    (+) RxHalfCpltCallback  : SPDIFRX Data flow half completed callback.
+    (+) RxCpltCallback      : SPDIFRX Data flow completed callback.
+    (+) CxHalfCpltCallback  : SPDIFRX Control flow half completed callback.
+    (+) CxCpltCallback      : SPDIFRX Control flow completed callback.
+    (+) ErrorCallback       : SPDIFRX error callback.
+    (+) MspInitCallback     : SPDIFRX MspInit.
+    (+) MspDeInitCallback   : SPDIFRX MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use HAL_SPDIFRX_UnRegisterCallback() function to reset a callback to the default
+  weak function.
+  The HAL_SPDIFRX_UnRegisterCallback() function takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset the following callbacks:
+    (+) RxHalfCpltCallback  : SPDIFRX Data flow half completed callback.
+    (+) RxCpltCallback      : SPDIFRX Data flow completed callback.
+    (+) CxHalfCpltCallback  : SPDIFRX Control flow half completed callback.
+    (+) CxCpltCallback      : SPDIFRX Control flow completed callback.
+    (+) ErrorCallback       : SPDIFRX error callback.
+    (+) MspInitCallback     : SPDIFRX MspInit.
+    (+) MspDeInitCallback   : SPDIFRX MspDeInit.
+
+  By default, after the HAL_SPDIFRX_Init() and when the state is HAL_SPDIFRX_STATE_RESET
+  all callbacks are set to the corresponding weak functions :
+  HAL_SPDIFRX_RxHalfCpltCallback() , HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(),
+  HAL_SPDIFRX_CxCpltCallback() and HAL_SPDIFRX_ErrorCallback()
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_SPDIFRX_Init()/ HAL_SPDIFRX_DeInit() only when
+  these callbacks pointers are NULL (not registered beforehand).
+  If not, MspInit or MspDeInit callbacks pointers are not null, the HAL_SPDIFRX_Init() / HAL_SPDIFRX_DeInit()
+  keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_SPDIFRX_STATE_READY state only.
+  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+  in HAL_SPDIFRX_STATE_READY or HAL_SPDIFRX_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_SPDIFRX_RegisterCallback() before calling HAL_SPDIFRX_DeInit()
+  or HAL_SPDIFRX_Init() function.
+
+  When The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPDIFRX SPDIFRX
+  * @brief SPDIFRX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+#if defined (SPDIFRX)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SPDIFRX_Private_Defines SPDIFRX Private Defines
+  * @{
+  */
+#define SPDIFRX_TIMEOUT_VALUE  10U
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SPDIFRX_Private_Functions
+  * @{
+  */
+static void  SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void  SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void  SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);
+static void  SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
+static void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
+static void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
+static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag,
+                                                         FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
+/**
+  * @}
+  */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions
+  * @{
+  */
+
+/** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ===============================================================================
+  ##### Initialization and de-initialization functions #####
+  ===============================================================================
+  [..]  This subsection provides a set of functions allowing to initialize and
+        de-initialize the SPDIFRX peripheral:
+
+  (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
+      all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+  (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
+      the selected configuration:
+  (++) Input Selection (IN0, IN1,...)
+  (++) Maximum allowed re-tries during synchronization phase
+  (++) Wait for activity on SPDIF selected input
+  (++) Channel status selection (from channel A or B)
+  (++) Data format (LSB, MSB, ...)
+  (++) Stereo mode
+  (++) User bits masking (PT,C,U,V,...)
+
+  (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
+      of the selected SPDIFRXx peripheral.
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initializes the SPDIFRX according to the specified parameters
+  *        in the SPDIFRX_InitTypeDef and create the associated handle.
+  * @param hspdif SPDIFRX handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
+{
+  uint32_t tmpreg;
+
+  /* Check the SPDIFRX handle allocation */
+  if (hspdif == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the SPDIFRX parameters */
+  assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
+  assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
+  assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
+  assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
+  assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
+  assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
+  assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
+  assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
+  assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
+  assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
+  assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.SymbolClockGen));
+  assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.BackupSymbolClockGen));
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  if (hspdif->State == HAL_SPDIFRX_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hspdif->Lock = HAL_UNLOCKED;
+
+    hspdif->RxHalfCpltCallback  = HAL_SPDIFRX_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+    hspdif->RxCpltCallback      = HAL_SPDIFRX_RxCpltCallback;     /* Legacy weak RxCpltCallback     */
+    hspdif->CxHalfCpltCallback  = HAL_SPDIFRX_CxHalfCpltCallback; /* Legacy weak CxHalfCpltCallback */
+    hspdif->CxCpltCallback      = HAL_SPDIFRX_CxCpltCallback;     /* Legacy weak CxCpltCallback     */
+    hspdif->ErrorCallback       = HAL_SPDIFRX_ErrorCallback;      /* Legacy weak ErrorCallback      */
+
+    if (hspdif->MspInitCallback == NULL)
+    {
+      hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hspdif->MspInitCallback(hspdif);
+  }
+#else
+  if (hspdif->State == HAL_SPDIFRX_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hspdif->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SPDIFRX_MspInit(hspdif);
+  }
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+  /* SPDIFRX peripheral state is BUSY */
+  hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+  /* Disable SPDIFRX interface (IDLE State) */
+  __HAL_SPDIFRX_IDLE(hspdif);
+
+  /* Reset the old SPDIFRX CR configuration */
+  tmpreg = hspdif->Instance->CR;
+
+  tmpreg &= ~(SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
+              SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK  |
+              SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
+              SPDIFRX_CR_CKSEN | SPDIFRX_CR_CKSBKPEN |
+              SPDIFRX_CR_INSEL);
+
+  /* Sets the new configuration of the SPDIFRX peripheral */
+  tmpreg |= (hspdif->Init.StereoMode |
+             hspdif->Init.InputSelection |
+             hspdif->Init.Retries |
+             hspdif->Init.WaitForActivity |
+             hspdif->Init.ChannelSelection |
+             hspdif->Init.DataFormat |
+             hspdif->Init.PreambleTypeMask |
+             hspdif->Init.ChannelStatusMask |
+             hspdif->Init.ValidityBitMask |
+             hspdif->Init.ParityErrorMask
+            );
+
+  if (hspdif->Init.SymbolClockGen == ENABLE)
+  {
+    tmpreg |= SPDIFRX_CR_CKSEN;
+  }
+
+  if (hspdif->Init.BackupSymbolClockGen == ENABLE)
+  {
+    tmpreg |= SPDIFRX_CR_CKSBKPEN;
+  }
+
+  hspdif->Instance->CR = tmpreg;
+
+  hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+  /* SPDIFRX peripheral state is READY*/
+  hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief DeInitializes the SPDIFRX peripheral
+  * @param hspdif SPDIFRX handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Check the SPDIFRX handle allocation */
+  if (hspdif == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));
+
+  hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+  /* Disable SPDIFRX interface (IDLE state) */
+  __HAL_SPDIFRX_IDLE(hspdif);
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  if (hspdif->MspDeInitCallback == NULL)
+  {
+    hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hspdif->MspDeInitCallback(hspdif);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_SPDIFRX_MspDeInit(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+  hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+  /* SPDIFRX peripheral state is RESET*/
+  hspdif->State = HAL_SPDIFRX_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspdif);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief SPDIFRX MSP Init
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_SPDIFRX_MspInit could be implemented in the user file
+  */
+}
+
+/**
+  * @brief SPDIFRX MSP DeInit
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_SPDIFRX_MspDeInit could be implemented in the user file
+  */
+}
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SPDIFRX Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hspdif SPDIFRX handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID    SPDIFRX Data flow half completed callback ID
+  *          @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID    SPDIFRX Data flow completed callback ID
+  *          @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID    SPDIFRX Control flow half completed callback ID
+  *          @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID    SPDIFRX Control flow completed callback ID
+  *          @arg @ref HAL_SPDIFRX_ERROR_CB_ID      SPDIFRX error callback ID
+  *          @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID    MspInit callback ID
+  *          @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID  MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
+                                               pSPDIFRX_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hspdif);
+
+  if (HAL_SPDIFRX_STATE_READY == hspdif->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPDIFRX_RX_HALF_CB_ID :
+        hspdif->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPDIFRX_RX_CPLT_CB_ID :
+        hspdif->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPDIFRX_CX_HALF_CB_ID :
+        hspdif->CxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPDIFRX_CX_CPLT_CB_ID :
+        hspdif->CxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPDIFRX_ERROR_CB_ID :
+        hspdif->ErrorCallback = pCallback;
+        break;
+
+      case HAL_SPDIFRX_MSPINIT_CB_ID :
+        hspdif->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+        hspdif->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SPDIFRX_STATE_RESET == hspdif->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPDIFRX_MSPINIT_CB_ID :
+        hspdif->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+        hspdif->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspdif);
+  return status;
+}
+
+/**
+  * @brief  Unregister a SPDIFRX Callback
+  *         SPDIFRX callback is redirected to the weak predefined callback
+  * @param  hspdif SPDIFRX handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID    SPDIFRX Data flow half completed callback ID
+  *          @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID    SPDIFRX Data flow completed callback ID
+  *          @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID    SPDIFRX Control flow half completed callback ID
+  *          @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID    SPDIFRX Control flow completed callback ID
+  *          @arg @ref HAL_SPDIFRX_ERROR_CB_ID      SPDIFRX error callback ID
+  *          @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID    MspInit callback ID
+  *          @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID  MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
+                                                 HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hspdif);
+
+  if (HAL_SPDIFRX_STATE_READY == hspdif->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPDIFRX_RX_HALF_CB_ID :
+        hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback;
+        break;
+
+      case HAL_SPDIFRX_RX_CPLT_CB_ID :
+        hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback;
+        break;
+
+      case HAL_SPDIFRX_CX_HALF_CB_ID :
+        hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback;
+        break;
+
+      case HAL_SPDIFRX_CX_CPLT_CB_ID :
+        hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback;
+        break;
+
+      case HAL_SPDIFRX_ERROR_CB_ID :
+        hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SPDIFRX_STATE_RESET == hspdif->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPDIFRX_MSPINIT_CB_ID :
+        hspdif->MspInitCallback = HAL_SPDIFRX_MspInit;  /* Legacy weak MspInit  */
+        break;
+
+      case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+        hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit;  /* Legacy weak MspInit  */
+        break;
+
+      default :
+        /* Update the error code */
+        hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspdif);
+  return status;
+}
+
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+/**
+  * @brief Set the SPDIFRX  data format according to the specified parameters in the SPDIFRX_InitTypeDef.
+  * @param hspdif SPDIFRX handle
+  * @param sDataFormat SPDIFRX data format
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
+{
+  uint32_t tmpreg;
+
+  /* Check the SPDIFRX handle allocation */
+  if (hspdif == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the SPDIFRX parameters */
+  assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
+  assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
+  assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
+  assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
+  assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
+  assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
+
+  /* Reset the old SPDIFRX CR configuration */
+  tmpreg = hspdif->Instance->CR;
+
+  if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
+      (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
+       ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
+  {
+    return HAL_ERROR;
+  }
+
+  tmpreg &= ~(SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |
+              SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
+
+  /* Configure the new data format */
+  tmpreg |= (sDataFormat.StereoMode |
+             sDataFormat.DataFormat |
+             sDataFormat.PreambleTypeMask |
+             sDataFormat.ChannelStatusMask |
+             sDataFormat.ValidityBitMask |
+             sDataFormat.ParityErrorMask);
+
+  hspdif->Instance->CR = tmpreg;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions
+  *  @brief Data transfers functions
+  *
+@verbatim
+===============================================================================
+                     ##### IO operation functions #####
+===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the SPDIFRX data
+    transfers.
+
+    (#) There is two mode of transfer:
+        (++) Blocking mode : The communication is performed in the polling mode.
+             The status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) No-Blocking mode : The communication is performed using Interrupts
+             or DMA. These functions return the status of the transfer start-up.
+             The end of the data processing will be indicated through the
+             dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_SPDIFRX_ReceiveDataFlow()
+        (++) HAL_SPDIFRX_ReceiveCtrlFlow()
+                (+@) Do not use blocking mode to receive both control and data flow at the same time.
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_SPDIFRX_ReceiveCtrlFlow_IT()
+        (++) HAL_SPDIFRX_ReceiveDataFlow_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_SPDIFRX_ReceiveCtrlFlow_DMA()
+        (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+        (++) HAL_SPDIFRX_RxCpltCallback()
+        (++) HAL_SPDIFRX_CxCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Receives an amount of data (Data Flow) in blocking mode.
+  * @param  hspdif pointer to SPDIFRX_HandleTypeDef structure that contains
+  *                 the configuration information for SPDIFRX module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint16_t sizeCounter = Size;
+  uint32_t *pTmpBuf = pData;
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hspdif->State == HAL_SPDIFRX_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hspdif);
+
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+    /* Start synchronisation */
+    __HAL_SPDIFRX_SYNC(hspdif);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until SYNCD flag is set */
+    if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Start reception */
+    __HAL_SPDIFRX_RCV(hspdif);
+
+    /* Receive data flow */
+    while (sizeCounter > 0U)
+    {
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Wait until RXNE flag is set */
+      if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      (*pTmpBuf) = hspdif->Instance->DR;
+      pTmpBuf++;
+      sizeCounter--;
+    }
+
+    /* SPDIFRX ready */
+    hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data (Control Flow) in blocking mode.
+  * @param  hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains
+  *                 the configuration information for SPDIFRX module.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be received
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint16_t sizeCounter = Size;
+  uint32_t *pTmpBuf = pData;
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if (hspdif->State == HAL_SPDIFRX_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hspdif);
+
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+
+    /* Start synchronization */
+    __HAL_SPDIFRX_SYNC(hspdif);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until SYNCD flag is set */
+    if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Start reception */
+    __HAL_SPDIFRX_RCV(hspdif);
+
+    /* Receive control flow */
+    while (sizeCounter > 0U)
+    {
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Wait until CSRNE flag is set */
+      if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      (*pTmpBuf) = hspdif->Instance->CSR;
+      pTmpBuf++;
+      sizeCounter--;
+    }
+
+    /* SPDIFRX ready */
+    hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
+  * @param hspdif SPDIFRX handle
+  * @param pData a 32-bit pointer to the Receive data buffer.
+  * @param Size number of data sample to be received .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+  uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
+
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hspdif);
+
+    hspdif->pRxBuffPtr = pData;
+    hspdif->RxXferSize = Size;
+    hspdif->RxXferCount = Size;
+
+    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+    /* Check if a receive process is ongoing or not */
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+    /* Enable the SPDIFRX  PE Error Interrupt */
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+    /* Enable the SPDIFRX  OVR Error Interrupt */
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+    /* Enable the SPDIFRX RXNE interrupt */
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count == 0U)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
+        }
+        count--;
+      } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data (Control Flow) with Interrupt
+  * @param hspdif SPDIFRX handle
+  * @param pData a 32-bit pointer to the Receive data buffer.
+  * @param Size number of data sample (Control Flow) to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+  uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
+
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hspdif);
+
+    hspdif->pCsBuffPtr = pData;
+    hspdif->CsXferSize = Size;
+    hspdif->CsXferCount = Size;
+
+    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+
+    /* Check if a receive process is ongoing or not */
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+    /* Enable the SPDIFRX PE Error Interrupt */
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+    /* Enable the SPDIFRX OVR Error Interrupt */
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+    /* Enable the SPDIFRX CSRNE interrupt */
+    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count == 0U)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
+        }
+        count--;
+      } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data (Data Flow) mode with DMA
+  * @param hspdif SPDIFRX handle
+  * @param pData a 32-bit pointer to the Receive data buffer.
+  * @param Size number of data sample to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+  uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hspdif);
+
+    hspdif->pRxBuffPtr = pData;
+    hspdif->RxXferSize = Size;
+    hspdif->RxXferCount = Size;
+
+    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
+
+    /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+    hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;
+
+    /* Set the SPDIFRX Rx DMA transfer complete callback */
+    hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;
+
+    /* Set the DMA error callback */
+    hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
+
+    /* Enable the DMA request */
+    if ((hspdif->hdmaDrRx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if (hspdif->hdmaDrRx->LinkedListQueue != NULL)
+      {
+        hspdif->hdmaDrRx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t) Size * 4U;
+        hspdif->hdmaDrRx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+          (uint32_t) &hspdif->Instance->DR;
+        hspdif->hdmaDrRx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+          (uint32_t) hspdif->pRxBuffPtr;
+
+        if (HAL_DMAEx_List_Start_IT(hspdif->hdmaDrRx) != HAL_OK)
+        {
+          /* Set SPDIFRX error */
+          hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+          /* Set SPDIFRX state */
+          hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Set SPDIFRX error */
+        hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+        /* Set SPDIFRX state */
+        hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspdif);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr,
+                           (uint32_t) Size * 4U) != HAL_OK)
+      {
+        /* Set SPDIFRX error */
+        hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+        /* Set SPDIFRX state */
+        hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspdif);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
+    hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count == 0U)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
+        }
+        count--;
+      } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data (Control Flow) with DMA
+  * @param hspdif SPDIFRX handle
+  * @param pData a 32-bit pointer to the Receive data buffer.
+  * @param Size number of data (Control Flow) sample to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
+{
+  uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+  const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
+
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
+
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
+  {
+    hspdif->pCsBuffPtr = pData;
+    hspdif->CsXferSize = Size;
+    hspdif->CsXferCount = Size;
+
+    /* Process Locked */
+    __HAL_LOCK(hspdif);
+
+    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
+    hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
+
+    /* Set the SPDIFRX Rx DMA Half transfer complete callback */
+    hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
+
+    /* Set the SPDIFRX Rx DMA transfer complete callback */
+    hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
+
+    /* Set the DMA error callback */
+    hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
+
+    /* Enable the DMA request */
+    if ((hspdif->hdmaCsRx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if (hspdif->hdmaCsRx->LinkedListQueue != NULL)
+      {
+        hspdif->hdmaCsRx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t) Size * 4U;
+        hspdif->hdmaCsRx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+          (uint32_t) &hspdif->Instance->CSR;
+        hspdif->hdmaCsRx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+          (uint32_t) hspdif->pCsBuffPtr;
+
+        if (HAL_DMAEx_List_Start_IT(hspdif->hdmaCsRx) != HAL_OK)
+        {
+          /* Set SPDIFRX error */
+          hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+          /* Set SPDIFRX state */
+          hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Set SPDIFRX error */
+        hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+        /* Set SPDIFRX state */
+        hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspdif);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr,
+                           (uint32_t) Size * 4U) != HAL_OK)
+      {
+        /* Set SPDIFRX error */
+        hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+        /* Set SPDIFRX state */
+        hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspdif);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
+    hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
+
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFRXEN) != SPDIFRX_STATE_RCV)
+    {
+      /* Start synchronization */
+      __HAL_SPDIFRX_SYNC(hspdif);
+
+      /* Wait until SYNCD flag is set */
+      do
+      {
+        if (count == 0U)
+        {
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hspdif);
+
+          return HAL_TIMEOUT;
+        }
+        count--;
+      } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+
+      /* Start reception */
+      __HAL_SPDIFRX_RCV(hspdif);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief stop the audio stream receive from the Media.
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Process Locked */
+  __HAL_LOCK(hspdif);
+
+  /* Disable the SPDIFRX DMA requests */
+  hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+  hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+
+  /* Disable the SPDIFRX DMA channel */
+  if (hspdif->hdmaDrRx != NULL)
+  {
+    __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
+  }
+  if (hspdif->hdmaCsRx != NULL)
+  {
+    __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+  }
+
+  /* Disable SPDIFRX peripheral */
+  __HAL_SPDIFRX_IDLE(hspdif);
+
+  hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspdif);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles SPDIFRX interrupt request.
+  * @param  hspdif SPDIFRX handle
+  * @retval HAL status
+  */
+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
+{
+  uint32_t itFlag   = hspdif->Instance->SR;
+  uint32_t itSource = hspdif->Instance->IMR;
+
+  /* SPDIFRX in mode Data Flow Reception */
+  if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource &  SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
+  {
+    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
+    SPDIFRX_ReceiveDataFlow_IT(hspdif);
+  }
+
+  /* SPDIFRX in mode Control Flow Reception */
+  if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource &  SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
+  {
+    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
+    SPDIFRX_ReceiveControlFlow_IT(hspdif);
+  }
+
+  /* SPDIFRX Overrun error interrupt occurred */
+  if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource &  SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
+  {
+    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE);
+
+    /* Change the SPDIFRX error code */
+    hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
+
+    /* the transfer is not stopped */
+    HAL_SPDIFRX_ErrorCallback(hspdif);
+  }
+
+  /* SPDIFRX Parity error interrupt occurred */
+  if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource &  SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
+  {
+    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE);
+
+    /* Change the SPDIFRX error code */
+    hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
+
+    /* the transfer is not stopped */
+    HAL_SPDIFRX_ErrorCallback(hspdif);
+  }
+}
+
+/**
+  * @brief Rx Transfer (Data flow) half completed callbacks
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief Rx Transfer (Data flow) completed callbacks
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief Rx (Control flow) Transfer half completed callbacks
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief Rx Transfer (Control flow) completed callbacks
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief SPDIFRX error callbacks
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspdif);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+===============================================================================
+##### Peripheral State and Errors functions #####
+===============================================================================
+[..]
+This subsection permit to get in run-time the status of the peripheral
+and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SPDIFRX state
+  * @param  hspdif SPDIFRX handle
+  * @retval HAL state
+  */
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif)
+{
+  return hspdif->State;
+}
+
+/**
+  * @brief  Return the SPDIFRX error code
+  * @param  hspdif SPDIFRX handle
+  * @retval SPDIFRX Error Code
+  */
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif)
+{
+  return hspdif->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief DMA SPDIFRX receive process (Data flow) complete callback
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable Rx DMA Request */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+    hspdif->RxXferCount = 0;
+    hspdif->State = HAL_SPDIFRX_STATE_READY;
+  }
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  hspdif->RxCpltCallback(hspdif);
+#else
+  HAL_SPDIFRX_RxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA SPDIFRX receive process (Data flow) half complete callback
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  hspdif->RxHalfCpltCallback(hspdif);
+#else
+  HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief DMA SPDIFRX receive process (Control flow) complete callback
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
+{
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable Cb DMA Request */
+  hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
+  hspdif->CsXferCount = 0;
+
+  hspdif->State = HAL_SPDIFRX_STATE_READY;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  hspdif->CxCpltCallback(hspdif);
+#else
+  HAL_SPDIFRX_CxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA SPDIFRX receive process (Control flow) half complete callback
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  hspdif->CxHalfCpltCallback(hspdif);
+#else
+  HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA SPDIFRX communication error callback
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Disable Rx and Cb DMA Request */
+  hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
+  hspdif->RxXferCount = 0;
+
+  hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+  /* Set the error code and execute error callback*/
+  hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+  /* The transfer is not stopped */
+  hspdif->ErrorCallback(hspdif);
+#else
+  /* The transfer is not stopped */
+  HAL_SPDIFRX_ErrorCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief Receive an amount of data (Data Flow) with Interrupt
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Receive data */
+  (*hspdif->pRxBuffPtr) = hspdif->Instance->DR;
+  hspdif->pRxBuffPtr++;
+  hspdif->RxXferCount--;
+
+  if (hspdif->RxXferCount == 0U)
+  {
+    /* Disable RXNE/PE and OVR interrupts */
+    __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
+
+    hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+    hspdif->RxCpltCallback(hspdif);
+#else
+    HAL_SPDIFRX_RxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief Receive an amount of data (Control Flow) with Interrupt
+  * @param hspdif SPDIFRX handle
+  * @retval None
+  */
+static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
+{
+  /* Receive data */
+  (*hspdif->pCsBuffPtr) = hspdif->Instance->CSR;
+  hspdif->pCsBuffPtr++;
+  hspdif->CsXferCount--;
+
+  if (hspdif->CsXferCount == 0U)
+  {
+    /* Disable CSRNE interrupt */
+    __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+
+    hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspdif);
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+    hspdif->CxCpltCallback(hspdif);
+#else
+    HAL_SPDIFRX_CxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief This function handles SPDIFRX Communication Timeout.
+  * @param hspdif SPDIFRX handle
+  * @param Flag Flag checked
+  * @param Status Value of the flag expected
+  * @param Timeout Duration of the timeout
+  * @param tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag,
+                                                        FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
+{
+  /* Wait until flag is set */
+  while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+           process */
+        __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+        __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+        __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+        __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+        __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+        __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+        __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+
+        hspdif->State = HAL_SPDIFRX_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspdif);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+#endif /* SPDIFRX */
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spi.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spi.c
new file mode 100644
index 000000000..28033bbc9
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spi.c
@@ -0,0 +1,3919 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_spi.c
+  * @author  MCD Application Team
+  * @brief   SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The SPI HAL driver can be used as follows:
+
+      (#) Declare a SPI_HandleTypeDef handle structure, for example:
+          SPI_HandleTypeDef  hspi;
+
+      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+          (##) Enable the SPIx interface clock
+          (##) SPI pins configuration
+              (+++) Enable the clock for the SPI GPIOs
+              (+++) Configure these SPI pins as alternate function push-pull
+          (##) NVIC configuration if you need to use interrupt process or DMA process
+              (+++) Configure the SPIx interrupt priority
+              (+++) Enable the NVIC SPI IRQ handle
+          (##) DMA Configuration if you need to use DMA process
+              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
+              (+++) Enable the DMAx clock
+              (+++) Configure the DMA handle parameters
+              (+++) Configure the DMA Tx or Rx Stream/Channel
+              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+                    or Rx Stream/Channel
+
+      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+              by calling the customized HAL_SPI_MspInit() API.
+     [..]
+       Callback registration:
+
+      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL
+          allows the user to configure dynamically the driver callbacks.
+          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+            (+) TxCpltCallback        : SPI Tx Completed callback
+            (+) RxCpltCallback        : SPI Rx Completed callback
+            (+) TxRxCpltCallback      : SPI TxRx Completed callback
+            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback
+            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback
+            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
+            (+) ErrorCallback         : SPI Error callback
+            (+) AbortCpltCallback     : SPI Abort callback
+            (+) SuspendCallback       : SPI Suspend callback
+            (+) MspInitCallback       : SPI Msp Init callback
+            (+) MspDeInitCallback     : SPI Msp DeInit callback
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+
+      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+          weak function.
+          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (+) TxCpltCallback        : SPI Tx Completed callback
+            (+) RxCpltCallback        : SPI Rx Completed callback
+            (+) TxRxCpltCallback      : SPI TxRx Completed callback
+            (+) TxHalfCpltCallback    : SPI Tx Half Completed callback
+            (+) RxHalfCpltCallback    : SPI Rx Half Completed callback
+            (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
+            (+) ErrorCallback         : SPI Error callback
+            (+) AbortCpltCallback     : SPI Abort callback
+            (+) SuspendCallback       : SPI Suspend callback
+            (+) MspInitCallback       : SPI Msp Init callback
+            (+) MspDeInitCallback     : SPI Msp DeInit callback
+
+       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+       all callbacks are set to the corresponding weak functions:
+       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+       Exception done for MspInit and MspDeInit functions that are
+       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+       these callbacks are null (not registered beforehand).
+       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+       Exception done MspInit/MspDeInit functions that can be registered/unregistered
+       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+       Then, the user first registers the MspInit/MspDeInit user callbacks
+       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+       or HAL_SPI_Init() function.
+
+       When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined,
+       the callback registering feature is not available and weak callbacks are used.
+
+       SuspendCallback restriction:
+           SuspendCallback is called only when MasterReceiverAutoSusp is enabled and
+       EOT interrupt is activated. SuspendCallback is used in relation with functions
+       HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT.
+
+    [..]
+      Circular mode restriction:
+      (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
+          (++) Master 2Lines RxOnly
+          (++) Master 1Line Rx
+      (+) The CRC feature is not managed when the DMA circular mode is enabled
+      (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
+          HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
+          Those functions are maintained for backward compatibility reasons.
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPI SPI
+  * @brief SPI HAL module driver
+  * @{
+  */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+  * @{
+  */
+#define SPI_DEFAULT_TIMEOUT 100UL
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+  * @{
+  */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag,
+                                                    FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
+static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi);
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+  * @{
+  */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          de-initialize the SPIx peripheral:
+
+      (+) User must implement HAL_SPI_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_SPI_Init() to configure the selected device with
+          the selected configuration:
+        (++) Mode
+        (++) Direction
+        (++) Data Size
+        (++) Clock Polarity and Phase
+        (++) NSS Management
+        (++) BaudRate Prescaler
+        (++) FirstBit
+        (++) TIMode
+        (++) CRC Calculation
+        (++) CRC Polynomial if CRC enabled
+        (++) CRC Length, used only with Data8 and Data16
+        (++) FIFO reception threshold
+        (++) FIFO transmission threshold
+
+      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+          of the selected SPIx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SPI according to the specified parameters
+  *         in the SPI_InitTypeDef and initialize the associated handle.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+  uint32_t crc_length;
+  uint32_t packet_length;
+#if (USE_SPI_CRC != 0UL)
+  uint32_t crc_poly_msb_mask;
+#endif /* USE_SPI_CRC */
+
+  /* Check the SPI handle allocation */
+  if (hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+  assert_param(IS_SPI_MODE(hspi->Init.Mode));
+  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+  if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
+  {
+    assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize));
+    assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
+  }
+  else
+  {
+    assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+    assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
+  }
+  assert_param(IS_SPI_NSS(hspi->Init.NSS));
+  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+  {
+    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+  }
+#if (USE_SPI_CRC != 0UL)
+  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
+    {
+      assert_param(IS_SPI_LIMITED_CRC_LENGTH(hspi->Init.CRCLength));
+    }
+    else
+    {
+      assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+    }
+    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+    assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
+    assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
+  }
+#else
+  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+  assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement));
+  assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity));
+  assert_param(IS_SPI_MASTER_RX_AUTOSUSP(hspi->Init.MasterReceiverAutoSusp));
+
+  /* Verify that the SPI instance supports Data Size higher than 16bits */
+  if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Verify that the SPI instance supports requested data packing */
+  packet_length = SPI_GetPacketSize(hspi);
+  if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) ||
+      ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)))
+  {
+    return HAL_ERROR;
+  }
+#if (USE_SPI_CRC != 0UL)
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* Verify that the SPI instance supports CRC Length higher than 16bits */
+    if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Align the CRC Length on the data size */
+    if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+    {
+      crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos;
+    }
+    else
+    {
+      crc_length = hspi->Init.CRCLength;
+    }
+
+    /* Verify the correctness of polynom size */
+    assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length));
+
+    /* Verify that the CRC Length is higher than DataSize */
+    if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos;
+  }
+#endif /* USE_SPI_CRC */
+
+  if (hspi->State == HAL_SPI_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+    /* Init the SPI Callback settings */
+    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
+    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
+    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
+    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
+    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
+    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hspi->SuspendCallback      = HAL_SPI_SuspendCallback;      /* Legacy weak SuspendCallback      */
+
+    if (hspi->MspInitCallback == NULL)
+    {
+      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    hspi->MspInitCallback(hspi);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  }
+
+  hspi->State = HAL_SPI_STATE_BUSY;
+
+  /* Disable the selected SPI peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+#if (USE_SPI_CRC == 0)
+  /* Keep the default value of CRCSIZE in case of CRC is not used */
+  crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE;
+#endif /* USE_SPI_CRC */
+
+  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+  Communication speed, First bit, CRC calculation state, CRC Length */
+
+  /* SPIx NSS Software Management Configuration */
+  if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) &&  \
+                                            (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
+                                           ((hspi->Init.Mode == SPI_MODE_SLAVE) && \
+                                            (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
+  }
+
+  /* SPIx Master Rx Auto Suspend Configuration */
+  if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT))
+  {
+    MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp);
+  }
+  else
+  {
+    CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX);
+  }
+
+  /* SPIx CFG1 Configuration */
+  WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
+                                   hspi->Init.FifoThreshold     | hspi->Init.DataSize));
+
+  /* SPIx CFG2 Configuration */
+  WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode                | hspi->Init.TIMode    |
+                                   hspi->Init.NSSPolarity             | hspi->Init.NSS       |
+                                   hspi->Init.CLKPolarity             | hspi->Init.CLKPhase  |
+                                   hspi->Init.FirstBit                | hspi->Init.Mode      |
+                                   hspi->Init.MasterInterDataIdleness | hspi->Init.Direction |
+                                   hspi->Init.MasterSSIdleness        | hspi->Init.IOSwap    |
+                                   hspi->Init.ReadyMasterManagement   | hspi->Init.ReadyPolarity));
+
+#if (USE_SPI_CRC != 0UL)
+  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+  /* Configure : CRC Polynomial */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* Initialize TXCRC Pattern Initial Value */
+    if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
+    {
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
+    }
+    else
+    {
+      CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
+    }
+
+    /* Initialize RXCRC Pattern Initial Value */
+    if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
+    {
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
+    }
+    else
+    {
+      CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
+    }
+
+    /* Enable 33/17 bits CRC computation */
+    if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
+        ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT)))
+    {
+      /* Set SPI_CR1_CRC33_17 bit */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+      /* Write CRC polynomial in SPI Register */
+      WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
+    }
+    else
+    {
+      /* Clear SPI_CR1_CRC33_17 bit */
+      CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+
+      /* Write CRC polynomial and set MSB bit at 1 in SPI Register */
+      /* Set MSB is mandatory for a correct CRC computation        */
+      crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U));
+      WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask);
+    }
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Insure that Underrun configuration is managed only by Salve */
+  if (hspi->Init.Mode == SPI_MODE_SLAVE)
+  {
+#if (USE_SPI_CRC != 0UL)
+    MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG);
+#endif /* USE_SPI_CRC */
+  }
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
+  /* Insure that AFCNTR is managed only by Master */
+  if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
+  {
+    /* Alternate function GPIOs control */
+    MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
+  }
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State     = HAL_SPI_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-Initialize the SPI peripheral.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+  /* Check the SPI handle allocation */
+  if (hspi == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check SPI Instance parameter */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+  hspi->State = HAL_SPI_STATE_BUSY;
+
+  /* Disable the SPI Peripheral Clock */
+  __HAL_SPI_DISABLE(hspi);
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  if (hspi->MspDeInitCallback == NULL)
+  {
+    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  hspi->MspDeInitCallback(hspi);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  hspi->State = HAL_SPI_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SPI MSP.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspInit should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize the SPI MSP.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspDeInit should be implemented in the user file
+   */
+}
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+/**
+  * @brief  Register a User SPI Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for the specified SPI.
+  * @param  CallbackID ID of the callback to be registered
+  * @param  pCallback pointer to the Callback function
+  * @note   The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
+  *         to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+                                           pSPI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_SPI_STATE_READY == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_TX_COMPLETE_CB_ID :
+        hspi->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_RX_COMPLETE_CB_ID :
+        hspi->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+        hspi->TxRxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+        hspi->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+        hspi->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+        hspi->TxRxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_ERROR_CB_ID :
+        hspi->ErrorCallback = pCallback;
+        break;
+
+      case HAL_SPI_ABORT_CB_ID :
+        hspi->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_SUSPEND_CB_ID :
+        hspi->SuspendCallback = pCallback;
+        break;
+
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SPI_STATE_RESET == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an SPI Callback
+  *         SPI callback is redirected to the weak predefined callback
+  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for the specified SPI.
+  * @param  CallbackID ID of the callback to be unregistered
+  * @note   The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
+  *         to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_SPI_STATE_READY == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_TX_COMPLETE_CB_ID :
+        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
+        break;
+
+      case HAL_SPI_RX_COMPLETE_CB_ID :
+        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
+        break;
+
+      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
+        break;
+
+      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
+        break;
+
+      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
+        break;
+
+      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+        break;
+
+      case HAL_SPI_ERROR_CB_ID :
+        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_SPI_ABORT_CB_ID :
+        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_SPI_SUSPEND_CB_ID :
+        hspi->SuspendCallback = HAL_SPI_SuspendCallback;           /* Legacy weak SuspendCallback      */
+        break;
+
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SPI_STATE_RESET == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of functions allowing to manage the SPI
+    data transfers.
+
+    [..] The SPI supports master and slave mode :
+
+    (#) There are two modes of transfer:
+       (##) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (##) No-Blocking mode: The communication is performed using Interrupts
+            or DMA, These APIs return the HAL status.
+            The end of the data processing will be indicated through the
+            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+            will be executed respectively at the end of the transmit or Receive process
+            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+        exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
+  *                  the configuration information for SPI module.
+  * @param  pData  : pointer to data buffer
+  * @param  Size   : amount of data to be sent
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+#if defined (__GNUC__)
+  __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+#endif /* __GNUC__ */
+
+  uint32_t tickstart;
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (const uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = NULL;
+  hspi->RxXferSize  = (uint16_t) 0UL;
+  hspi->RxXferCount = (uint16_t) 0UL;
+  hspi->TxISR       = NULL;
+  hspi->RxISR       = NULL;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+  else
+  {
+    SPI_2LINES_TX(hspi);
+  }
+
+  /* Set the number of data at current transfer */
+  MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  /* Transmit data in 32 Bit mode */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+  {
+    /* Transmit data in 32 Bit mode */
+    while (hspi->TxXferCount > 0UL)
+    {
+      /* Wait until TXP flag is set to send data */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+      {
+        *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint32_t);
+        hspi->TxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          /* Call standard close procedure with error check */
+          SPI_CloseTransfer(hspi);
+
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+          hspi->State = HAL_SPI_STATE_READY;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Transmit data in 16 Bit mode */
+  else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* Transmit data in 16 Bit mode */
+    while (hspi->TxXferCount > 0UL)
+    {
+      /* Wait until TXP flag is set to send data */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+      {
+        if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+        {
+          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
+          hspi->pTxBuffPtr += sizeof(uint32_t);
+          hspi->TxXferCount -= (uint16_t)2UL;
+        }
+        else
+        {
+#if defined (__GNUC__)
+          *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
+#else
+          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+          hspi->pTxBuffPtr += sizeof(uint16_t);
+          hspi->TxXferCount--;
+        }
+      }
+      else
+      {
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          /* Call standard close procedure with error check */
+          SPI_CloseTransfer(hspi);
+
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+          hspi->State = HAL_SPI_STATE_READY;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Transmit data in 8 Bit mode */
+  else
+  {
+    while (hspi->TxXferCount > 0UL)
+    {
+      /* Wait until TXP flag is set to send data */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+      {
+        if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
+        {
+          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
+          hspi->pTxBuffPtr += sizeof(uint32_t);
+          hspi->TxXferCount -= (uint16_t)4UL;
+        }
+        else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+        {
+#if defined (__GNUC__)
+          *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
+#else
+          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+          hspi->pTxBuffPtr += sizeof(uint16_t);
+          hspi->TxXferCount -= (uint16_t)2UL;
+        }
+        else
+        {
+          *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
+          hspi->pTxBuffPtr += sizeof(uint8_t);
+          hspi->TxXferCount--;
+        }
+      }
+      else
+      {
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          /* Call standard close procedure with error check */
+          SPI_CloseTransfer(hspi);
+
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+          hspi->State = HAL_SPI_STATE_READY;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Wait for Tx (and CRC) data to be sent */
+  if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+  }
+
+  /* Call standard close procedure with error check */
+  SPI_CloseTransfer(hspi);
+
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
+  *                  the configuration information for SPI module.
+  * @param  pData  : pointer to data buffer
+  * @param  Size   : amount of data to be received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t temp_sr_reg;
+  uint16_t init_max_data_in_fifo;
+  init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
+#if defined (__GNUC__)
+  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+#endif /* __GNUC__ */
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->pTxBuffPtr  = NULL;
+  hspi->TxXferSize  = (uint16_t) 0UL;
+  hspi->TxXferCount = (uint16_t) 0UL;
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+  /* Configure communication direction: 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+  else
+  {
+    SPI_2LINES_RX(hspi);
+  }
+
+  /* Set the number of data at current transfer */
+  MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  /* Receive data in 32 Bit mode */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+  {
+    /* Transfer loop */
+    while (hspi->RxXferCount > 0UL)
+    {
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      /* Check the RXP flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+      {
+        *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint32_t);
+        hspi->RxXferCount--;
+      }
+      /* Check RXWNE flag if RXP cannot be reached */
+      else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+      {
+        *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint32_t);
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          /* Call standard close procedure with error check */
+          SPI_CloseTransfer(hspi);
+
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+          hspi->State = HAL_SPI_STATE_READY;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Receive data in 16 Bit mode */
+  else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* Transfer loop */
+    while (hspi->RxXferCount > 0UL)
+    {
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      /* Check the RXP flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+      {
+#if defined (__GNUC__)
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount--;
+      }
+      /* Check RXWNE flag if RXP cannot be reached */
+      else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+      {
+#if defined (__GNUC__)
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+#if defined (__GNUC__)
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount -= (uint16_t)2UL;
+      }
+      /* Check RXPLVL flags when RXWNE cannot be reached */
+      else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
+      {
+#if defined (__GNUC__)
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          /* Call standard close procedure with error check */
+          SPI_CloseTransfer(hspi);
+
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+          hspi->State = HAL_SPI_STATE_READY;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /* Receive data in 8 Bit mode */
+  else
+  {
+    /* Transfer loop */
+    while (hspi->RxXferCount > 0UL)
+    {
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      /* Check the RXP flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+      {
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        hspi->RxXferCount--;
+      }
+      /* Check RXWNE flag if RXP cannot be reached */
+      else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+      {
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        hspi->RxXferCount -= (uint16_t)4UL;
+      }
+      /* Check RXPLVL flags when RXWNE cannot be reached */
+      else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
+      {
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        hspi->RxXferCount--;
+      }
+      else
+      {
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          /* Call standard close procedure with error check */
+          SPI_CloseTransfer(hspi);
+
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+          hspi->State = HAL_SPI_STATE_READY;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+#if (USE_SPI_CRC != 0UL)
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* Wait for crc data to be received */
+    if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    }
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Call standard close procedure with error check */
+  SPI_CloseTransfer(hspi);
+
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in blocking mode.
+  * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
+  *                  the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @param  Size   : amount of data to be sent and received
+  * @param  Timeout: Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                          uint16_t Size, uint32_t Timeout)
+{
+#if defined (__GNUC__)
+  __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+#endif /* __GNUC__ */
+
+  uint32_t   tickstart;
+  uint32_t   fifo_length;
+  uint32_t   temp_sr_reg;
+  uint16_t   initial_TxXferCount;
+  uint16_t   initial_RxXferCount;
+  uint16_t   init_max_data_in_fifo;
+  init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  initial_TxXferCount = Size;
+  initial_RxXferCount = Size;
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferCount = Size;
+  hspi->RxXferSize  = Size;
+  hspi->pTxBuffPtr  = (const uint8_t *)pTxData;
+  hspi->TxXferCount = Size;
+  hspi->TxXferSize  = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+  /* Set Full-Duplex mode */
+  SPI_2LINES(hspi);
+
+  /* Initialize FIFO length */
+  if (IS_SPI_FULL_INSTANCE(hspi->Instance))
+  {
+    fifo_length = SPI_HIGHEND_FIFO_SIZE;
+  }
+  else
+  {
+    fifo_length = SPI_LOWEND_FIFO_SIZE;
+  }
+
+  /* Set the number of data at current transfer */
+  MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+  __HAL_SPI_ENABLE(hspi);
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  /* Transmit and Receive data in 32 Bit mode */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+  {
+    /* Adapt fifo length to 32bits data width */
+    fifo_length = (fifo_length / 4UL);
+
+    while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+    {
+      /* Check TXP flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+          (initial_RxXferCount  < (initial_TxXferCount + fifo_length)))
+      {
+        *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint32_t);
+        hspi->TxXferCount --;
+        initial_TxXferCount = hspi->TxXferCount;
+      }
+
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      if (initial_RxXferCount > 0UL)
+      {
+        /* Check the RXP flag */
+        if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+        {
+          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint32_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXWNE flag if RXP cannot be reached */
+        else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+        {
+          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint32_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        else
+        {
+          /* Timeout management */
+          if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+          {
+            /* Call standard close procedure with error check */
+            SPI_CloseTransfer(hspi);
+
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+            hspi->State = HAL_SPI_STATE_READY;
+
+            /* Unlock the process */
+            __HAL_UNLOCK(hspi);
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /* Transmit and Receive data in 16 Bit mode */
+  else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    /* Adapt fifo length to 16bits data width */
+    fifo_length = (fifo_length / 2UL);
+
+    while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+    {
+      /* Check the TXP flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+          (initial_RxXferCount  < (initial_TxXferCount + fifo_length)))
+      {
+#if defined (__GNUC__)
+        *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
+#else
+        *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+        hspi->pTxBuffPtr += sizeof(uint16_t);
+        hspi->TxXferCount--;
+        initial_TxXferCount = hspi->TxXferCount;
+      }
+
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      if (initial_RxXferCount > 0UL)
+      {
+        /* Check the RXP flag */
+        if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+        {
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXWNE flag if RXP cannot be reached */
+        else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+        {
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+          hspi->RxXferCount -= (uint16_t)2UL;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXPLVL flags when RXWNE cannot be reached */
+        else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
+        {
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        else
+        {
+          /* Timeout management */
+          if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+          {
+            /* Call standard close procedure with error check */
+            SPI_CloseTransfer(hspi);
+
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+            hspi->State = HAL_SPI_STATE_READY;
+
+            /* Unlock the process */
+            __HAL_UNLOCK(hspi);
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /* Transmit and Receive data in 8 Bit mode */
+  else
+  {
+    while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+    {
+      /* Check the TXP flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+          (initial_RxXferCount  < (initial_TxXferCount + fifo_length)))
+      {
+        *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint8_t);
+        hspi->TxXferCount--;
+        initial_TxXferCount = hspi->TxXferCount;
+      }
+
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      if (initial_RxXferCount > 0UL)
+      {
+        /* Check the RXP flag */
+        if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+        {
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXWNE flag if RXP cannot be reached */
+        else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+        {
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          hspi->RxXferCount -= (uint16_t)4UL;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXPLVL flags when RXWNE cannot be reached */
+        else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
+        {
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        else
+        {
+          /* Timeout management */
+          if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+          {
+            /* Call standard close procedure with error check */
+            SPI_CloseTransfer(hspi);
+
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+            hspi->State = HAL_SPI_STATE_READY;
+
+            /* Unlock the process */
+            __HAL_UNLOCK(hspi);
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+
+  /* Wait for Tx/Rx (and CRC) data to be sent/received */
+  if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+  }
+
+  /* Call standard close procedure with error check */
+  SPI_CloseTransfer(hspi);
+
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size : amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
+{
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (const uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = NULL;
+  hspi->RxXferSize  = (uint16_t) 0UL;
+  hspi->RxXferCount = (uint16_t) 0UL;
+  hspi->RxISR       = NULL;
+
+  /* Set the function for IT treatment */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+  {
+    hspi->TxISR = SPI_TxISR_32BIT;
+  }
+  else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->TxISR = SPI_TxISR_16BIT;
+  }
+  else
+  {
+    hspi->TxISR = SPI_TxISR_8BIT;
+  }
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+  else
+  {
+    SPI_2LINES_TX(hspi);
+  }
+
+  /* Set the number of data at current transfer */
+  MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  /* Enable EOT, TXP, FRE, MODF and UDR interrupts */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size : amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pTxBuffPtr  = NULL;
+  hspi->TxXferSize  = (uint16_t) 0UL;
+  hspi->TxXferCount = (uint16_t) 0UL;
+  hspi->TxISR       = NULL;
+
+  /* Set the function for IT treatment */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+  {
+    hspi->RxISR = SPI_RxISR_32BIT;
+  }
+  else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->RxISR = SPI_RxISR_16BIT;
+  }
+  else
+  {
+    hspi->RxISR = SPI_RxISR_8BIT;
+  }
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+  else
+  {
+    SPI_2LINES_RX(hspi);
+  }
+
+  /* Note : The SPI must be enabled after unlocking current process
+            to avoid the risk of SPI interrupt handle execution before current
+            process unlock */
+
+  /* Set the number of data at current transfer */
+  MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  /* Enable EOT, RXP, OVR, FRE and MODF interrupts */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
+  *                  the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @param  Size   : amount of data to be sent and received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                             uint16_t Size)
+{
+  uint32_t tmp_TxXferCount;
+#if defined (__GNUC__)
+  __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+#endif /* __GNUC__ */
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (const uint8_t *)pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+  tmp_TxXferCount   = hspi->TxXferCount;
+
+  /* Set the function for IT treatment */
+  if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
+  {
+    hspi->TxISR     = SPI_TxISR_32BIT;
+    hspi->RxISR     = SPI_RxISR_32BIT;
+  }
+  else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->RxISR     = SPI_RxISR_16BIT;
+    hspi->TxISR     = SPI_TxISR_16BIT;
+  }
+  else
+  {
+    hspi->RxISR     = SPI_RxISR_8BIT;
+    hspi->TxISR     = SPI_TxISR_8BIT;
+  }
+
+  /* Set Full-Duplex mode */
+  SPI_2LINES(hspi);
+
+  /* Set the number of data at current transfer */
+  MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  /* Fill in the TxFIFO */
+  while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL))
+  {
+    /* Transmit data in 32 Bit mode */
+    if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+    {
+      *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint32_t);
+      hspi->TxXferCount--;
+      tmp_TxXferCount = hspi->TxXferCount;
+    }
+    /* Transmit data in 16 Bit mode */
+    else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+    {
+#if defined (__GNUC__)
+      *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
+#else
+      *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+      hspi->pTxBuffPtr += sizeof(uint16_t);
+      hspi->TxXferCount--;
+      tmp_TxXferCount = hspi->TxXferCount;
+    }
+    /* Transmit data in 8 Bit mode */
+    else
+    {
+      *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint8_t);
+      hspi->TxXferCount--;
+      tmp_TxXferCount = hspi->TxXferCount;
+    }
+  }
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Start Master transfer */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  return HAL_OK;
+}
+
+
+
+
+/**
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
+  * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size : amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (const uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = NULL;
+  hspi->TxISR       = NULL;
+  hspi->RxISR       = NULL;
+  hspi->RxXferSize  = (uint16_t)0UL;
+  hspi->RxXferCount = (uint16_t)0UL;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
+  else
+  {
+    SPI_2LINES_TX(hspi);
+  }
+
+  /* Packing mode management is enabled by the DMA settings */
+  if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth !=  DMA_SRC_DATAWIDTH_WORD) && \
+       (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
+      ((hspi->Init.DataSize > SPI_DATASIZE_8BIT)  && (hspi->hdmatx->Init.SrcDataWidth ==  DMA_SRC_DATAWIDTH_BYTE)))
+  {
+    /* Restriction the DMA data received is not allowed in this mode */
+    __HAL_UNLOCK(hspi);
+    return HAL_ERROR;
+  }
+
+  /* Adjust XferCount according to DMA alignment / Data size */
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+    {
+      hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+    if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+    {
+      hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
+    }
+  }
+  else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+  {
+    if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+    {
+      hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+  }
+  else
+  {
+    /* Adjustment done */
+  }
+
+  /* Set the SPI TxDMA Half transfer complete callback */
+  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+  /* Set the SPI TxDMA transfer complete callback */
+  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+  /* Set the DMA error callback */
+  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmatx->XferAbortCallback = NULL;
+
+  /* Clear TXDMAEN bit*/
+  CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    hspi->TxXferCount = Size;
+  }
+  else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+  {
+    hspi->TxXferCount = Size * 2U;
+  }
+  else
+  {
+    hspi->TxXferCount = Size * 4U;
+  }
+
+  /* Enable the Tx DMA Stream/Channel */
+  if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hspi->hdmatx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount;
+
+      /* Set DMA source address */
+      hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr;
+
+      /* Set DMA destination address */
+      hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR;
+
+      status = HAL_DMAEx_List_Start_IT(hspi->hdmatx);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+                              hspi->TxXferCount);
+  }
+
+  /* Check status */
+  if (status != HAL_OK)
+  {
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
+  }
+
+  /* Set the number of data at current transfer */
+  if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)
+  {
+    MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+  }
+  else
+  {
+    MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+  }
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hspi : pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for SPI module.
+  * @param  pData: pointer to data buffer
+  * @param  Size : amount of data to be sent
+  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    __HAL_UNLOCK(hspi);
+    return HAL_BUSY;
+  }
+
+  if ((pData == NULL) || (Size == 0UL))
+  {
+    __HAL_UNLOCK(hspi);
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+  hspi->TxXferSize  = (uint16_t) 0UL;
+  hspi->TxXferCount = (uint16_t) 0UL;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+  else
+  {
+    SPI_2LINES_RX(hspi);
+  }
+
+  /* Packing mode management is enabled by the DMA settings */
+  if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) &&  \
+       (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
+      ((hspi->Init.DataSize > SPI_DATASIZE_8BIT)  && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)))
+  {
+    /* Restriction the DMA data received is not allowed in this mode */
+    __HAL_UNLOCK(hspi);
+    return HAL_ERROR;
+  }
+
+  /* Clear RXDMAEN bit */
+  CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+  /* Adjust XferCount according to DMA alignment / Data size */
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD)
+    {
+      hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+    if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+    {
+      hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
+    }
+  }
+  else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+  {
+    if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+    {
+      hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+  }
+  else
+  {
+    /* Adjustment done */
+  }
+
+  /* Set the SPI RxDMA Half transfer complete callback */
+  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+  /* Set the SPI Rx DMA transfer complete callback */
+  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    hspi->RxXferCount = Size;
+  }
+  else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+  {
+    hspi->RxXferCount = Size * 2U;
+  }
+  else
+  {
+    hspi->RxXferCount = Size * 4U;
+  }
+
+  /* Enable the Rx DMA Stream/Channel  */
+  if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hspi->hdmarx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount;
+
+      /* Set DMA source address */
+      hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR;
+
+      /* Set DMA destination address */
+      hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr;
+
+      status = HAL_DMAEx_List_Start_IT(hspi->hdmarx);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+                              hspi->RxXferCount);
+  }
+
+  /* Check status */
+  if (status != HAL_OK)
+  {
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
+  }
+
+  /* Set the number of data at current transfer */
+  if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR)
+  {
+    MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+  }
+  else
+  {
+    MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+  }
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
+  * @param  hspi   : pointer to a SPI_HandleTypeDef structure that contains
+  *                  the configuration information for SPI module.
+  * @param  pTxData: pointer to transmission data buffer
+  * @param  pRxData: pointer to reception data buffer
+  * @param  Size   : amount of data to be sent
+  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (const uint8_t *)pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+  /* Set Full-Duplex mode */
+  SPI_2LINES(hspi);
+
+  /* Reset the Tx/Rx DMA bits */
+  CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+  /* Packing mode management is enabled by the DMA settings */
+  if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \
+       (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
+      ((hspi->Init.DataSize > SPI_DATASIZE_8BIT)  && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)))
+  {
+    /* Restriction the DMA data received is not allowed in this mode */
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+    return HAL_ERROR;
+  }
+
+  /* Adjust XferCount according to DMA alignment / Data size */
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
+    {
+      hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+    if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+    {
+      hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
+    }
+    if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD)
+    {
+      hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+    if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+    {
+      hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
+    }
+  }
+  else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+  {
+    if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
+    {
+      hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+    if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
+    {
+      hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+    }
+  }
+  else
+  {
+    /* Adjustment done */
+  }
+
+  /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+  hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
+
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+  /* Set the DMA AbortCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    hspi->RxXferCount = Size;
+  }
+  else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+  {
+    hspi->RxXferCount = Size * 2U;
+  }
+  else
+  {
+    hspi->RxXferCount = Size * 4U;
+  }
+  /* Enable the Rx DMA Stream/Channel  */
+  if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hspi->hdmarx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount;
+
+      /* Set DMA source address */
+      hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR;
+
+      /* Set DMA destination address */
+      hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr;
+
+      status = HAL_DMAEx_List_Start_IT(hspi->hdmarx);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+                              hspi->RxXferCount);
+  }
+
+  /* Check status */
+  if (status != HAL_OK)
+  {
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
+  }
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+  is performed in DMA reception complete callback  */
+  hspi->hdmatx->XferHalfCpltCallback = NULL;
+  hspi->hdmatx->XferCpltCallback     = NULL;
+  hspi->hdmatx->XferAbortCallback    = NULL;
+
+  /* Set the DMA error callback */
+  hspi->hdmatx->XferErrorCallback    = SPI_DMAError;
+
+  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+  {
+    hspi->TxXferCount = Size;
+  }
+  else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+  {
+    hspi->TxXferCount = Size * 2U;
+  }
+  else
+  {
+    hspi->TxXferCount = Size * 4U;
+  }
+
+  /* Enable the Tx DMA Stream/Channel  */
+  if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if (hspi->hdmatx->LinkedListQueue != NULL)
+    {
+      /* Set DMA data size */
+      hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount;
+
+      /* Set DMA source address */
+      hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr;
+
+      /* Set DMA destination address */
+      hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR;
+
+      status = HAL_DMAEx_List_Start_IT(hspi->hdmatx);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+                              hspi->TxXferCount);
+  }
+
+  /* Check status */
+  if (status != HAL_OK)
+  {
+    /* Abort Rx DMA Channel already started */
+    (void)HAL_DMA_Abort(hspi->hdmarx);
+
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
+  }
+
+  if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR))
+  {
+    MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+  }
+  else
+  {
+    MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+  }
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+  /* Enable SPI peripheral */
+  __HAL_SPI_ENABLE(hspi);
+
+  if (hspi->Init.Mode == SPI_MODE_MASTER)
+  {
+    /* Master transfer start */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+  }
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfer (blocking mode).
+  * @param  hspi SPI handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+  *         started in Interrupt or DMA mode.
+  * @note   This procedure performs following operations :
+  *          + Disable SPI Interrupts (depending of transfer direction)
+  *          + Disable the DMA transfer in the peripheral register (if enabled)
+  *          + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *          + Set handle State to READY.
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+  HAL_StatusTypeDef errorcode;
+
+  __IO uint32_t count;
+
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
+  /* Set hspi->state to aborting to avoid any interaction */
+  hspi->State = HAL_SPI_STATE_ABORT;
+
+  /* Initialized local variable  */
+  errorcode = HAL_OK;
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
+
+  /* If master communication on going, make sure current frame is done before closing the connection */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
+  {
+    /* Disable EOT interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
+
+    /* Request a Suspend transfer */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+
+    /* Clear SUSP flag */
+    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
+  }
+
+  /* Disable the SPI DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
+  {
+    if (hspi->hdmatx != NULL)
+    {
+      /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+      hspi->hdmatx->XferAbortCallback = NULL;
+
+      /* Abort DMA Tx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+        }
+      }
+    }
+  }
+
+  /* Disable the SPI DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
+  {
+    if (hspi->hdmarx != NULL)
+    {
+      /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+      hspi->hdmarx->XferAbortCallback = NULL;
+
+      /* Abort DMA Rx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+        }
+      }
+    }
+  }
+
+  /* Proceed with abort procedure */
+  SPI_AbortTransfer(hspi);
+
+  /* Check error during Abort procedure */
+  if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT))
+  {
+    /* return HAL_Error in case of error during Abort procedure */
+    errorcode = HAL_ERROR;
+  }
+  else
+  {
+    /* Reset errorCode */
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  }
+
+  /* Restore hspi->state to ready */
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
+  return errorcode;
+}
+
+/**
+  * @brief  Abort ongoing transfer (Interrupt mode).
+  * @param  hspi SPI handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+  *         started in Interrupt or DMA mode.
+  * @note   This procedure performs following operations :
+  *          + Disable SPI Interrupts (depending of transfer direction)
+  *          + Disable the DMA transfer in the peripheral register (if enabled)
+  *          + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *          + Set handle State to READY
+  *          + At abort completion, call user abort complete callback.
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+  HAL_StatusTypeDef errorcode;
+  __IO uint32_t count;
+  uint32_t dma_tx_abort_done = 1UL;
+  uint32_t dma_rx_abort_done = 1UL;
+
+  /* Set hspi->state to aborting to avoid any interaction */
+  hspi->State = HAL_SPI_STATE_ABORT;
+
+  /* Initialized local variable  */
+  errorcode = HAL_OK;
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
+
+  /* If master communication on going, make sure current frame is done before closing the connection */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
+  {
+    /* Disable EOT interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
+
+    /* Request a Suspend transfer */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+
+    /* Clear SUSP flag */
+    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
+  }
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
+     before any call to DMA Abort functions */
+
+  if (hspi->hdmatx != NULL)
+  {
+    if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
+    {
+      /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */
+      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+
+      dma_tx_abort_done = 0UL;
+
+      /* Abort DMA Tx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
+        {
+          dma_tx_abort_done = 1UL;
+          hspi->hdmatx->XferAbortCallback = NULL;
+        }
+      }
+    }
+    else
+    {
+      hspi->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+
+  if (hspi->hdmarx != NULL)
+  {
+    if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
+    {
+      /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */
+      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+
+      dma_rx_abort_done = 0UL;
+
+      /* Abort DMA Rx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
+        {
+          dma_rx_abort_done = 1UL;
+          hspi->hdmarx->XferAbortCallback = NULL;
+        }
+      }
+    }
+    else
+    {
+      hspi->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* If no running DMA transfer, finish cleanup and call callbacks */
+  if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
+  {
+    /* Proceed with abort procedure */
+    SPI_AbortTransfer(hspi);
+
+    /* Check error during Abort procedure */
+    if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT))
+    {
+      /* return HAL_Error in case of error during Abort procedure */
+      errorcode = HAL_ERROR;
+    }
+    else
+    {
+      /* Reset errorCode */
+      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+    }
+
+    /* Restore hspi->state to ready */
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+    hspi->AbortCpltCallback(hspi);
+#else
+    HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  }
+
+  return errorcode;
+}
+
+/**
+  * @brief  Pause the DMA Transfer.
+  *         This API is not supported, it is maintained for backward compatibility.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL_ERROR
+  */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+  /* Set error code to not supported */
+  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Resume the DMA Transfer.
+  *         This API is not supported, it is maintained for backward compatibility.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL_ERROR
+  */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+  /* Set error code to not supported */
+  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Stop the DMA Transfer.
+  *         This API is not supported, it is maintained for backward compatibility.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL_ERROR
+  */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+  /* Set error code to not supported */
+  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Handle SPI interrupt request.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval None
+  */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+  uint32_t itsource = hspi->Instance->IER;
+  uint32_t itflag   = hspi->Instance->SR;
+  uint32_t trigger  = itsource & itflag;
+  uint32_t cfg1     = hspi->Instance->CFG1;
+  uint32_t handled  = 0UL;
+
+  HAL_SPI_StateTypeDef State = hspi->State;
+#if defined (__GNUC__)
+  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+#endif /* __GNUC__ */
+
+  /* SPI in SUSPEND mode  ----------------------------------------------------*/
+  if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
+  {
+    /* Clear the Suspend flag */
+    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+    /* Suspend on going, Call the Suspend callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+    hspi->SuspendCallback(hspi);
+#else
+    HAL_SPI_SuspendCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* SPI in mode Transmitter and Receiver ------------------------------------*/
+  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
+      HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
+  {
+    hspi->TxISR(hspi);
+    hspi->RxISR(hspi);
+    handled = 1UL;
+  }
+
+  /* SPI in mode Receiver ----------------------------------------------------*/
+  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \
+      HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+  {
+    hspi->RxISR(hspi);
+    handled = 1UL;
+  }
+
+  /* SPI in mode Transmitter -------------------------------------------------*/
+  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \
+      HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+  {
+    hspi->TxISR(hspi);
+    handled = 1UL;
+  }
+
+  if (handled != 0UL)
+  {
+    return;
+  }
+
+  /* SPI End Of Transfer: DMA or IT based transfer */
+  if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
+  {
+    /* Clear EOT/TXTF/SUSP flag */
+    __HAL_SPI_CLEAR_EOTFLAG(hspi);
+    __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+    /* Disable EOT interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
+
+    /* For the IT based receive extra polling maybe required for last packet */
+    if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+    {
+      /* Pooling remaining data */
+      while (hspi->RxXferCount != 0UL)
+      {
+        /* Receive data in 32 Bit mode */
+        if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+        {
+          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint32_t);
+        }
+        /* Receive data in 16 Bit mode */
+        else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+        {
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+        }
+        /* Receive data in 8 Bit mode */
+        else
+        {
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+        }
+
+        hspi->RxXferCount--;
+      }
+    }
+
+    /* Call SPI Standard close procedure */
+    SPI_CloseTransfer(hspi);
+
+    hspi->State = HAL_SPI_STATE_READY;
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+      hspi->ErrorCallback(hspi);
+#else
+      HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      return;
+    }
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+    /* Call appropriate user callback */
+    if (State == HAL_SPI_STATE_BUSY_TX_RX)
+    {
+      hspi->TxRxCpltCallback(hspi);
+    }
+    else if (State == HAL_SPI_STATE_BUSY_RX)
+    {
+      hspi->RxCpltCallback(hspi);
+    }
+    else if (State == HAL_SPI_STATE_BUSY_TX)
+    {
+      hspi->TxCpltCallback(hspi);
+    }
+#else
+    /* Call appropriate user callback */
+    if (State == HAL_SPI_STATE_BUSY_TX_RX)
+    {
+      HAL_SPI_TxRxCpltCallback(hspi);
+    }
+    else if (State == HAL_SPI_STATE_BUSY_RX)
+    {
+      HAL_SPI_RxCpltCallback(hspi);
+    }
+    else if (State == HAL_SPI_STATE_BUSY_TX)
+    {
+      HAL_SPI_TxCpltCallback(hspi);
+    }
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    else
+    {
+      /* End of the appropriate call */
+    }
+
+    return;
+  }
+
+  /* SPI in Error Treatment --------------------------------------------------*/
+  if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL)
+  {
+    /* SPI Overrun error interrupt occurred ----------------------------------*/
+    if ((trigger & SPI_FLAG_OVR) != 0UL)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    }
+
+    /* SPI Mode Fault error interrupt occurred -------------------------------*/
+    if ((trigger & SPI_FLAG_MODF) != 0UL)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+      __HAL_SPI_CLEAR_MODFFLAG(hspi);
+    }
+
+    /* SPI Frame error interrupt occurred ------------------------------------*/
+    if ((trigger & SPI_FLAG_FRE) != 0UL)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+      __HAL_SPI_CLEAR_FREFLAG(hspi);
+    }
+
+    /* SPI Underrun error interrupt occurred ------------------------------------*/
+    if ((trigger & SPI_FLAG_UDR) != 0UL)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
+      __HAL_SPI_CLEAR_UDRFLAG(hspi);
+    }
+
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      /* Disable SPI peripheral */
+      __HAL_SPI_DISABLE(hspi);
+
+      /* Disable all interrupts */
+      __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF |
+                                  SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR));
+
+      /* Disable the SPI DMA requests if enabled */
+      if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+      {
+        /* Disable the SPI DMA requests */
+        CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+        /* Abort the SPI DMA Rx channel */
+        if (hspi->hdmarx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+          {
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+          }
+        }
+        /* Abort the SPI DMA Tx channel */
+        if (hspi->hdmatx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+          {
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+          }
+        }
+      }
+      else
+      {
+        /* Restore hspi->State to Ready */
+        hspi->State = HAL_SPI_STATE_READY;
+
+        /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+        hspi->ErrorCallback(hspi);
+#else
+        HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      }
+    }
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx Half Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Half Transfer completed callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Half Transfer callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief SPI error callback.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_ErrorCallback should be implemented in the user file
+   */
+  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+            and user can use HAL_SPI_GetError() API to check the latest error occurred
+   */
+}
+
+/**
+  * @brief  SPI Abort Complete callback.
+  * @param  hspi SPI handle.
+  * @retval None
+  */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SPI Suspend callback.
+  * @param  hspi SPI handle.
+  * @retval None
+  */
+__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_SuspendCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+  * @brief   SPI control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SPI.
+     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SPI handle state.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI state
+  */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
+{
+  /* Return SPI handle state */
+  return hspi->State;
+}
+
+/**
+  * @brief  Return the SPI error code.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI error code in bitmap format
+  */
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
+{
+  /* Return SPI ErrorCode */
+  return hspi->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Private_Functions
+  * @brief   Private functions
+  * @{
+  */
+
+/**
+  * @brief DMA SPI transmit process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hspi->State != HAL_SPI_STATE_ABORT)
+  {
+    if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)
+    {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+      hspi->TxCpltCallback(hspi);
+#else
+      HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Enable EOT interrupt */
+      __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+    }
+  }
+}
+
+/**
+  * @brief DMA SPI receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hspi->State != HAL_SPI_STATE_ABORT)
+  {
+    if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR)
+    {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+      hspi->RxCpltCallback(hspi);
+#else
+      HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Enable EOT interrupt */
+      __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA SPI transmit receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hspi->State != HAL_SPI_STATE_ABORT)
+  {
+    if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) &&
+        (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR))
+    {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+      hspi->TxRxCpltCallback(hspi);
+#else
+      HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Enable EOT interrupt */
+      __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA SPI half transmit process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+                            ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  hspi->TxHalfCpltCallback(hspi);
+#else
+  HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI half receive process complete callback
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+                            ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  hspi->RxHalfCpltCallback(hspi);
+#else
+  HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI half transmit receive process complete callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+                            ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  hspi->TxRxHalfCpltCallback(hspi);
+#else
+  HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI communication error callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* if DMA error is FIFO error ignore it */
+  if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE)
+  {
+    /* Call SPI standard close procedure */
+    SPI_CloseTransfer(hspi);
+
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    hspi->State = HAL_SPI_STATE_READY;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+    hspi->ErrorCallback(hspi);
+#else
+    HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  hspi->RxXferCount = (uint16_t) 0UL;
+  hspi->TxXferCount = (uint16_t) 0UL;
+
+  /* Restore hspi->State to Ready */
+  hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  hspi->ErrorCallback(hspi);
+#else
+  HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hspi->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hspi->hdmarx != NULL)
+  {
+    if (hspi->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* Call the Abort procedure */
+  SPI_AbortTransfer(hspi);
+
+  /* Restore hspi->State to Ready */
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  hspi->AbortCpltCallback(hspi);
+#else
+  HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hspi->hdmatx != NULL)
+  {
+    if (hspi->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* Call the Abort procedure */
+  SPI_AbortTransfer(hspi);
+
+  /* Restore hspi->State to Ready */
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+  hspi->AbortCpltCallback(hspi);
+#else
+  HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Manage the receive 8-bit in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 8 Bit mode */
+  *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR);
+  hspi->pRxBuffPtr += sizeof(uint8_t);
+  hspi->RxXferCount--;
+
+  /* Disable IT if no more data excepted */
+  if (hspi->RxXferCount == 0UL)
+  {
+    /* Disable RXP interrupts */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+  }
+}
+
+
+/**
+  * @brief  Manage the 16-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 16 Bit mode */
+#if defined (__GNUC__)
+  __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
+
+  *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+  *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+  hspi->pRxBuffPtr += sizeof(uint16_t);
+  hspi->RxXferCount--;
+
+  /* Disable IT if no more data excepted */
+  if (hspi->RxXferCount == 0UL)
+  {
+    /* Disable RXP interrupts */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+  }
+}
+
+
+/**
+  * @brief  Manage the 32-bit receive in Interrupt context.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
+{
+  /* Receive data in 32 Bit mode */
+  *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR);
+  hspi->pRxBuffPtr += sizeof(uint32_t);
+  hspi->RxXferCount--;
+
+  /* Disable IT if no more data excepted */
+  if (hspi->RxXferCount == 0UL)
+  {
+    /* Disable RXP interrupts */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+  }
+}
+
+
+/**
+  * @brief  Handle the data 8-bit transmit in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 8 Bit mode */
+  *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint8_t);
+  hspi->TxXferCount--;
+
+  /* Disable IT if no more data excepted */
+  if (hspi->TxXferCount == 0UL)
+  {
+    /* Disable TXP interrupts */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+  }
+}
+
+/**
+  * @brief  Handle the data 16-bit transmit in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 16 Bit mode */
+#if defined (__GNUC__)
+  __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+
+  *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
+#else
+  *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+  hspi->pTxBuffPtr += sizeof(uint16_t);
+  hspi->TxXferCount--;
+
+  /* Disable IT if no more data excepted */
+  if (hspi->TxXferCount == 0UL)
+  {
+    /* Disable TXP interrupts */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+  }
+}
+
+/**
+  * @brief  Handle the data 32-bit transmit in Interrupt mode.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 32 Bit mode */
+  *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint32_t);
+  hspi->TxXferCount--;
+
+  /* Disable IT if no more data excepted */
+  if (hspi->TxXferCount == 0UL)
+  {
+    /* Disable TXP interrupts */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+  }
+}
+
+/**
+  * @brief  Abort Transfer and clear flags.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
+{
+  /* Disable SPI peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* Disable ITs */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+                              SPI_IT_FRE | SPI_IT_MODF));
+
+  /* Clear the Status flags in the SR register */
+  __HAL_SPI_CLEAR_EOTFLAG(hspi);
+  __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+
+  /* Disable Tx DMA Request */
+  CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+  /* Clear the Error flags in the SR register */
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  __HAL_SPI_CLEAR_UDRFLAG(hspi);
+  __HAL_SPI_CLEAR_FREFLAG(hspi);
+  __HAL_SPI_CLEAR_MODFFLAG(hspi);
+  __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+#if (USE_SPI_CRC != 0U)
+  __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+#endif /* USE_SPI_CRC */
+
+  hspi->TxXferCount = (uint16_t)0UL;
+  hspi->RxXferCount = (uint16_t)0UL;
+}
+
+
+/**
+  * @brief  Close Transfer and clear flags.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval HAL_ERROR: if any error detected
+  *         HAL_OK: if nothing detected
+  */
+static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
+{
+  uint32_t itflag = hspi->Instance->SR;
+
+  __HAL_SPI_CLEAR_EOTFLAG(hspi);
+  __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+
+  /* Disable SPI peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* Disable ITs */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+                              SPI_IT_FRE | SPI_IT_MODF));
+
+  /* Disable Tx DMA Request */
+  CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+  /* Report UnderRun error for non RX Only communication */
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    if ((itflag & SPI_FLAG_UDR) != 0UL)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
+      __HAL_SPI_CLEAR_UDRFLAG(hspi);
+    }
+  }
+
+  /* Report OverRun error for non TX Only communication */
+  if (hspi->State != HAL_SPI_STATE_BUSY_TX)
+  {
+    if ((itflag & SPI_FLAG_OVR) != 0UL)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+      __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    }
+
+#if (USE_SPI_CRC != 0UL)
+    /* Check if CRC error occurred */
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      if ((itflag & SPI_FLAG_CRCERR) != 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+        __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+      }
+    }
+#endif /* USE_SPI_CRC */
+  }
+
+  /* SPI Mode Fault error interrupt occurred -------------------------------*/
+  if ((itflag & SPI_FLAG_MODF) != 0UL)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+    __HAL_SPI_CLEAR_MODFFLAG(hspi);
+  }
+
+  /* SPI Frame error interrupt occurred ------------------------------------*/
+  if ((itflag & SPI_FLAG_FRE) != 0UL)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+    __HAL_SPI_CLEAR_FREFLAG(hspi);
+  }
+
+  hspi->TxXferCount = (uint16_t)0UL;
+  hspi->RxXferCount = (uint16_t)0UL;
+}
+
+/**
+  * @brief Handle SPI Communication Timeout.
+  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *              the configuration information for SPI module.
+  * @param Flag: SPI flag to check
+  * @param Status: flag state to check
+  * @param Timeout: Timeout duration
+  * @param Tickstart: Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Wait until flag is set */
+  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if ((((HAL_GetTick() - Tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Compute configured packet size from fifo perspective.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval Packet size occupied in the fifo
+  */
+static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi)
+{
+  uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
+  uint32_t data_size       = (hspi->Init.DataSize      >> SPI_CFG1_DSIZE_Pos) + 1UL;
+
+  /* Convert data size to Byte */
+  data_size = (data_size + 7UL) / 8UL;
+
+  return data_size * fifo_threashold;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spi_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spi_ex.c
new file mode 100644
index 000000000..f705814ab
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_spi_ex.c
@@ -0,0 +1,227 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_spi_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          SPI peripheral extended functionalities :
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPIEx SPIEx
+  * @brief SPI Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+  * @{
+  */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of extended functions to manage the SPI
+    data transfers.
+
+    (#) SPIEx function:
+        (++) HAL_SPIEx_FlushRxFifo()
+        (++) HAL_SPIEx_EnableLockConfiguration()
+        (++) HAL_SPIEx_ConfigureUnderrun()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Flush the RX fifo.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
+{
+  uint8_t  count  = 0;
+  uint32_t itflag = hspi->Instance->SR;
+  __IO uint32_t tmpreg;
+
+  while (((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) !=  0UL))
+  {
+    count += (uint8_t)4UL;
+    tmpreg = hspi->Instance->RXDR;
+    UNUSED(tmpreg); /* To avoid GCC warning */
+
+    if (IS_SPI_FULL_INSTANCE(hspi->Instance))
+    {
+      if (count > SPI_HIGHEND_FIFO_SIZE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      if (count > SPI_LOWEND_FIFO_SIZE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Enable the Lock for the AF configuration of associated IOs
+  *         and write protect the Content of Configuration register 2
+  *         when SPI is enabled
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
+{
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    hspi->State = HAL_SPI_STATE_READY;
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+    return errorcode;
+  }
+
+  /* Check if the SPI is disabled to edit IOLOCK bit */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
+  }
+  else
+  {
+    /* Disable SPI peripheral */
+    __HAL_SPI_DISABLE(hspi);
+
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
+
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  hspi->State = HAL_SPI_STATE_READY;
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Configure the UNDERRUN condition and behavior of slave transmitter.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  UnderrunDetection : Detection of underrun condition at slave transmitter
+  *                             This parameter is not supported in this SPI version.
+  *                             It is kept in order to not break the compatibility.
+  * @param  UnderrunBehaviour : Behavior of slave transmitter at underrun condition
+  *                             This parameter can be a value of @ref SPI_Underrun_Behaviour.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+                                              uint32_t UnderrunBehaviour)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(UnderrunDetection);
+
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Check State and Insure that Underrun configuration is managed only by Salve */
+  if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
+  {
+    errorcode = HAL_BUSY;
+    hspi->State = HAL_SPI_STATE_READY;
+    /* Process Unlocked */
+    __HAL_UNLOCK(hspi);
+    return errorcode;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
+
+  /* Check if the SPI is disabled to edit CFG1 register */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Configure Underrun fields */
+    MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
+  }
+  else
+  {
+    /* Disable SPI peripheral */
+    __HAL_SPI_DISABLE(hspi);
+
+    /* Configure Underrun fields */
+    MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
+
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+
+  hspi->State = HAL_SPI_STATE_READY;
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sram.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sram.c
new file mode 100644
index 000000000..5e48c0f03
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_sram.c
@@ -0,0 +1,1239 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_sram.c
+  * @author  MCD Application Team
+  * @brief   SRAM HAL module driver.
+  *          This file provides a generic firmware to drive SRAM memories
+  *          mounted as external device.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                          ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver is a generic layered driver which contains a set of APIs used to
+    control SRAM memories. It uses the FMC layer functions to interface
+    with SRAM devices.
+    The following sequence should be followed to configure the FMC to interface
+    with SRAM/PSRAM memories:
+
+   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+          SRAM_HandleTypeDef  hsram; and:
+
+       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
+            values of the structure member.
+
+       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+            base register instance for NOR or SRAM device
+
+       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+            base register instance for NOR or SRAM extended mode
+
+   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+       mode timings; for example:
+          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
+      and fill its fields with the allowed values of the structure member.
+
+   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+       performs the following sequence:
+
+       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+       (##) Control register configuration using the FMC NORSRAM interface function
+            FMC_NORSRAM_Init()
+       (##) Timing register configuration using the FMC NORSRAM interface function
+            FMC_NORSRAM_Timing_Init()
+       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
+            FMC_NORSRAM_Extended_Timing_Init()
+       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
+
+   (#) At this stage you can perform read/write accesses from/to the memory connected
+       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+       following APIs:
+       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+
+   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
+   (#) You can continuously monitor the SRAM device HAL state by calling the function
+       HAL_SRAM_GetState()
+
+       *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : SRAM MspInit.
+        (+) MspDeInitCallback  : SRAM MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : SRAM MspInit.
+        (+) MspDeInitCallback  : SRAM MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
+      and  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
+      or HAL_SRAM_Init function.
+
+      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+/** @defgroup SRAM SRAM
+  * @brief SRAM driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SRAM_Private_Functions SRAM Private Functions
+  * @{
+  */
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions.
+  *
+  @verbatim
+  ==============================================================================
+           ##### SRAM Initialization and de_initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to initialize/de-initialize
+          the SRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Performs the SRAM device initialization sequence
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  Timing Pointer to SRAM control timing structure
+  * @param  ExtTiming Pointer to SRAM extended mode timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+                                FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+  /* Check the SRAM handle parameter */
+  if (hsram == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsram->State == HAL_SRAM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsram->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+    if (hsram->MspInitCallback == NULL)
+    {
+      hsram->MspInitCallback = HAL_SRAM_MspInit;
+    }
+    hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+    hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+    /* Init the low level hardware */
+    hsram->MspInitCallback(hsram);
+#else
+    /* Initialize the low level hardware (MSP) */
+    HAL_SRAM_MspInit(hsram);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+  }
+
+  /* Initialize SRAM control Interface */
+  (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+  /* Initialize SRAM timing Interface */
+  (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+
+  /* Initialize SRAM extended mode timing Interface */
+  (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
+                                         hsram->Init.ExtendedMode);
+
+  /* Enable the NORSRAM device */
+  __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+  /* Enable FMC Peripheral */
+  __FMC_ENABLE();
+
+  /* Initialize the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Performs the SRAM device De-initialization sequence.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  if (hsram->MspDeInitCallback == NULL)
+  {
+    hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsram->MspDeInitCallback(hsram);
+#else
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_SRAM_MspDeInit(hsram);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+  /* Configure the SRAM registers with their reset values */
+  (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+  /* Reset the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SRAM MSP Init.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SRAM MSP DeInit.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete error callback.
+  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+  * @brief    Input Output and memory control functions
+  *
+  @verbatim
+  ==============================================================================
+                  ##### SRAM Input and Output functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to use and control the SRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads 8-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                   uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+  uint8_t *pdestbuff = pDstBuffer;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *psramaddress;
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 8-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+  uint8_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *psramaddress = *psrcbuff;
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 16-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint16_t *pdestbuff = pDstBuffer;
+  uint8_t limit;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Check if the size is a 32-bits multiple */
+    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+    /* Read data from memory */
+    for (size = BufferSize; size != limit; size -= 2U)
+    {
+      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+      pdestbuff++;
+      *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Read last 16-bits if size is not 32-bits multiple */
+    if (limit != 0U)
+    {
+      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 16-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint16_t *psrcbuff = pSrcBuffer;
+  uint8_t limit;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Check if the size is a 32-bits multiple */
+    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+    /* Write data to memory */
+    for (size = BufferSize; size != limit; size -= 2U)
+    {
+      *psramaddress = (uint32_t)(*psrcbuff);
+      psrcbuff++;
+      *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Write last 16-bits if size is not 32-bits multiple */
+    if (limit != 0U)
+    {
+      *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 32-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint32_t *pdestbuff = pDstBuffer;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *psramaddress;
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 32-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint32_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *psramaddress = *psrcbuff;
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads a Words data from the SRAM memory using DMA transfer.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+  uint32_t size;
+  uint32_t data_width;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    if (state == HAL_SRAM_STATE_READY)
+    {
+      hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+    }
+    else
+    {
+      hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
+    }
+    hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+    if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U))
+      {
+        /* Check destination data width and set the size to be transferred */
+        data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+
+        if (data_width == DMA_DEST_DATAWIDTH_WORD)
+        {
+          size = (BufferSize * 4U);
+        }
+        else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+        {
+          size = (BufferSize * 2U);
+        }
+        else
+        {
+          size = (BufferSize);
+        }
+        /* Set Source , destination , buffer size */
+        /* Set DMA data size */
+        hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
+        /* Set DMA source address */
+        hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
+        /* Set DMA destination address */
+        hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer;
+
+        /* Enable the DMA Stream */
+        status = HAL_DMAEx_List_Start_IT(hsram->hdma);
+      }
+      else
+      {
+        /* Change SRAM state */
+        hsram->State = HAL_SRAM_STATE_READY;
+
+        __HAL_UNLOCK(hsram);
+
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Check destination data width and set the size to be transferred */
+      data_width = hsram->hdma->Init.DestDataWidth;
+
+      if (data_width == DMA_DEST_DATAWIDTH_WORD)
+      {
+        size = (BufferSize * 4U);
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+      {
+        size = (BufferSize * 2U);
+      }
+      else
+      {
+        size = (BufferSize);
+      }
+
+      /* Enable the DMA Stream */
+      status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size);
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+  uint32_t size;
+  uint32_t data_width;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+    hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+    if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U))
+      {
+        /* Check destination data width and set the size to be transferred */
+        data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+
+        if (data_width == DMA_DEST_DATAWIDTH_WORD)
+        {
+          size = (BufferSize * 4U);
+        }
+        else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+        {
+          size = (BufferSize * 2U);
+        }
+        else
+        {
+          size = (BufferSize);
+        }
+        /* Set Source , destination , buffer size */
+        /* Set DMA data size */
+        hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
+        /* Set DMA source address */
+        hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer;
+        /* Set DMA destination address */
+        hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
+        /* Enable the DMA Stream */
+        status = HAL_DMAEx_List_Start_IT(hsram->hdma);
+      }
+      else
+      {
+        /* Change SRAM state */
+        hsram->State = HAL_SRAM_STATE_READY;
+
+        __HAL_UNLOCK(hsram);
+
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Check destination data width and set the size to be transferred */
+      data_width = hsram->hdma->Init.DestDataWidth;
+
+      if (data_width == DMA_DEST_DATAWIDTH_WORD)
+      {
+        size = (BufferSize * 4U);
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+      {
+        size = (BufferSize * 2U);
+      }
+      else
+      {
+        size = (BufferSize);
+      }
+
+      /* Enable the DMA Stream */
+      status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size);
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SRAM Callback
+  *         To be used to override the weak predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
+  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                            pSRAM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  state = hsram->State;
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_MSP_INIT_CB_ID :
+        hsram->MspInitCallback = pCallback;
+        break;
+      case HAL_SRAM_MSP_DEINIT_CB_ID :
+        hsram->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SRAM Callback
+  *         SRAM Callback is redirected to the weak predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
+  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  state = hsram->State;
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_MSP_INIT_CB_ID :
+        hsram->MspInitCallback = HAL_SRAM_MspInit;
+        break;
+      case HAL_SRAM_MSP_DEINIT_CB_ID :
+        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+        break;
+      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+        hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+        break;
+      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+        hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (state == HAL_SRAM_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_MSP_INIT_CB_ID :
+        hsram->MspInitCallback = HAL_SRAM_MspInit;
+        break;
+      case HAL_SRAM_MSP_DEINIT_CB_ID :
+        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User SRAM Callback for DMA transfers
+  *         To be used to override the weak predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                               pSRAM_DmaCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsram);
+
+  state = hsram->State;
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+        hsram->DmaXferCpltCallback = pCallback;
+        break;
+      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+        hsram->DmaXferErrorCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+  return status;
+}
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+  *  @brief   Control functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### SRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the SRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically SRAM write operation.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Enable write operation */
+    (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically SRAM write operation.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Disable write operation */
+    (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### SRAM State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the SRAM controller
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the SRAM controller state
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL state
+  */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
+{
+  return hsram->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Private_Functions SRAM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SRAM error callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Derogation MISRAC2012-Rule-11.5 */
+  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_ERROR;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferErrorCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferErrorCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_tim.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_tim.c
new file mode 100644
index 000000000..8c477842b
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_tim.c
@@ -0,0 +1,8231 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
+            to use the Timer to generate an Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function HAL_TIM_RegisterCallback() to register a callback.
+  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+    (+) Break2Callback                    : TIM Break2 Callback.
+    (+) EncoderIndexCallback              : TIM Encoder Index Callback.
+    (+) DirectionChangeCallback           : TIM Direction Change Callback
+    (+) IndexErrorCallback                : TIM Index Error Callback.
+    (+) TransitionErrorCallback           : TIM Transition Error Callback
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel */
+  if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+                       Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @note   When the timer instance is initialized in One Pulse mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @note   When the timer instance is initialized in Encoder mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData1 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((pData2 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    default:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  uint32_t itsource = htim->Instance->DIER;
+  uint32_t itflag   = htim->Instance->SR;
+
+  /* Capture compare 1 event */
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+  {
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+    {
+      {
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+  {
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+  {
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+  {
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+  {
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
+  {
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
+  {
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+  {
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
+  {
+    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Encoder index event */
+  if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
+  {
+    if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->EncoderIndexCallback(htim);
+#else
+      HAL_TIMEx_EncoderIndexCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Direction change event */
+  if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
+  {
+    if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->DirectionChangeCallback(htim);
+#else
+      HAL_TIMEx_DirectionChangeCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Index error event */
+  if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
+  {
+    if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->IndexErrorCallback(htim);
+#else
+      HAL_TIMEx_IndexErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Transition error event */
+  if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
+  {
+    if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TransitionErrorCallback(htim);
+#else
+      HAL_TIMEx_TransitionErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 5 in Output Compare */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 6 in Output Compare */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_4)
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      switch (InputChannel)
+      {
+        case TIM_CHANNEL_1:
+        {
+          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC1PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        case TIM_CHANNEL_2:
+        {
+          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC2PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        default:
+          status = HAL_ERROR;
+          break;
+      }
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return status;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                              uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t BlockDataLength = 0;
+  uint32_t data_width;
+  const DMA_HandleTypeDef *hdma = NULL;
+
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_UPDATE];
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC1];
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC2];
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC3];
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC4];
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (hdma != NULL)
+  {
+
+    if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
+        && (hdma->LinkedListQueue->Head != 0U))
+    {
+      data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
+    }
+    else
+    {
+      data_width = hdma->Init.SrcDataWidth;
+    }
+
+    switch (data_width)
+    {
+      case DMA_SRC_DATAWIDTH_BYTE:
+      {
+        BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL;
+        break;
+      }
+      case DMA_SRC_DATAWIDTH_HALFWORD:
+      {
+        BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
+        break;
+      }
+      case DMA_SRC_DATAWIDTH_WORD:
+      {
+        BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
+        break;
+      }
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                                BlockDataLength);
+    }
+  }
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpDBSS = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = TIM_DCR_DBSS_0;
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = TIM_DCR_DBSS_1;
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = TIM_DCR_DBSS_2;
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t BlockDataLength = 0;
+  uint32_t data_width;
+  const DMA_HandleTypeDef *hdma = NULL;
+
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_UPDATE];
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC1];
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC2];
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC3];
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_CC4];
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (hdma != NULL)
+  {
+
+    if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
+        && (hdma->LinkedListQueue->Head != 0U))
+    {
+      data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
+    }
+    else
+    {
+      data_width = hdma->Init.SrcDataWidth;
+    }
+
+    switch (data_width)
+
+    {
+      case DMA_SRC_DATAWIDTH_BYTE:
+      {
+        BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL;
+        break;
+      }
+      case DMA_SRC_DATAWIDTH_HALFWORD:
+      {
+        BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
+        break;
+      }
+      case DMA_SRC_DATAWIDTH_WORD:
+      {
+        BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
+        break;
+      }
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                               BlockDataLength);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_DTR2
+  *            @arg TIM_DMABASE_ECR
+  *            @arg TIM_DMABASE_TISEL
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpDBSS = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = TIM_DCR_DBSS_0;
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS =  TIM_DCR_DBSS_1;
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = TIM_DCR_DBSS_2;
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Configure the DMA Burst Source Selection */
+      tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
+
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+  *         only for timer instances supporting break input(s).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    switch (Channel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_3:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_4:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_5:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 5 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 5 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_6:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 6 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 6 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        break;
+      }
+      default:
+        break;
+    }
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    case TIM_CLOCKSOURCE_ITR4:
+    case TIM_CLOCKSOURCE_ITR5:
+    case TIM_CLOCKSOURCE_ITR6:
+    case TIM_CLOCKSOURCE_ITR7:
+    case TIM_CLOCKSOURCE_ITR8:
+    case TIM_CLOCKSOURCE_ITR9:
+    case TIM_CLOCKSOURCE_ITR10:
+    case TIM_CLOCKSOURCE_ITR11:
+    case TIM_CLOCKSOURCE_ITR12:
+    case TIM_CLOCKSOURCE_ITR13:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @brief  Start the DMA data transfer.
+  * @param  hdma DMA handle
+  * @param  src      : The source memory Buffer address.
+  * @param  dst      : The destination memory Buffer address.
+  * @param  length   : The size of a source block transfer in byte.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
+                                   uint32_t length)
+{
+  HAL_StatusTypeDef status ;
+
+  /* Enable the DMA channel */
+  if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+  {
+    if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
+    {
+      /* Enable the DMA channel */
+      hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
+      hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src;
+      hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst;
+
+      status = HAL_DMAEx_List_Start_IT(hdma);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_DMA_Start_IT(hdma, src, dst, length);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+   (+) TIM Index callback
+   (+) TIM Direction change callback
+   (+) TIM Index error callback
+   (+) TIM Transition error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+  *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+  *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+  *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                       = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_INDEX_CB_ID :
+        htim->EncoderIndexCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+        htim->DirectionChangeCallback              = pCallback;
+        break;
+
+      case HAL_TIM_INDEX_ERROR_CB_ID :
+        htim->IndexErrorCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_TRANSITION_ERROR_CB_ID :
+        htim->TransitionErrorCallback              = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
+  *          @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
+  *          @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
+  *          @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        /* Legacy weak Period Elapsed Callback */
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        /* Legacy weak Period Elapsed half complete Callback */
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        /* Legacy weak Trigger Callback */
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        /* Legacy weak Trigger half complete Callback */
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        /* Legacy weak IC Capture Callback */
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        /* Legacy weak IC Capture half complete Callback */
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        /* Legacy weak OC Delay Elapsed Callback */
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        /* Legacy weak PWM Pulse Finished Callback */
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        /* Legacy weak PWM Pulse Finished half complete Callback */
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        /* Legacy weak Error Callback */
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        /* Legacy weak Commutation Callback */
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        /* Legacy weak Commutation half complete Callback */
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        /* Legacy weak Break Callback */
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        /* Legacy weak Break2 Callback */
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+        break;
+
+      case HAL_TIM_ENCODER_INDEX_CB_ID :
+        /* Legacy weak Encoder Index Callback */
+        htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
+        break;
+
+      case HAL_TIM_DIRECTION_CHANGE_CB_ID :
+        /* Legacy weak Direction Change Callback */
+        htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
+        break;
+
+      case HAL_TIM_INDEX_ERROR_CB_ID :
+        /* Legacy weak Index Error Callback */
+        htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
+        break;
+
+      case HAL_TIM_TRANSITION_ERROR_CB_ID :
+        /* Legacy weak Transition Error Callback */
+        htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM handle
+  * @retval Active channel
+  */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
+{
+  return htim->Channel;
+}
+
+/**
+  * @brief  Return actual state of the TIM channel.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval TIM Channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  return channel_state;
+}
+
+/**
+  * @brief  Return actual state of a DMA burst operation.
+  * @param  htim TIM handle
+  * @retval DMA burst state
+  */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+  return htim->DMABurstState;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+
+  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+  {
+    /* Clear the update flag */
+    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+  }
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC4NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 12U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC4NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+    /* Reset the Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4N;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
+          (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    case TIM_TS_ITR4:
+    case TIM_TS_ITR5:
+    case TIM_TS_ITR6:
+    case TIM_TS_ITR7:
+    case TIM_TS_ITR8:
+    case TIM_TS_ITR9:
+    case TIM_TS_ITR10:
+    case TIM_TS_ITR11:
+    case TIM_TS_ITR12:
+    case TIM_TS_ITR13:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
+  htim->EncoderIndexCallback              = HAL_TIMEx_EncoderIndexCallback;
+  htim->DirectionChangeCallback           = HAL_TIMEx_DirectionChangeCallback;
+  htim->IndexErrorCallback                = HAL_TIMEx_IndexErrorCallback;
+  htim->TransitionErrorCallback           = HAL_TIMEx_TransitionErrorCallback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_tim_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_tim_ex.c
new file mode 100644
index 000000000..1700c7450
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_tim_ex.c
@@ -0,0 +1,3427 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Timer remapping capabilities configuration
+  *           + Timer encoder index configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+    (#) In case of Pulse on compare, configure pulse length and delay
+    (#) Encoder index configuration
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+     (#) In case of Pulse On Compare:
+           (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
+
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+                HAL_TIMEx_OCN_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+                HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+                HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+  * @{
+  */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT    5UL /* 5 milliseconds */
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @note   When the timer instance is initialized in Hall Sensor Interface mode,
+  *         timer channels 1 and channel 2 are reserved and cannot be used for
+  *         other purpose.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+  {
+    return HAL_BUSY;
+  }
+  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel for Capture 1*/
+  if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM complementary channel state */
+  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM complementary channel state */
+  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
+
+      /* Enable the DMA channel */
+      if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to enable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel pulse output channel to disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output channel and the Input Capture channel */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM  channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Select timer input source.
+      (+) Enable or disable channel grouping.
+      (+) Configure Pulse on compare.
+      (+) Configure Encoder index.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR4: Internal trigger 4 selected
+  *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+  *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+  *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+  *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+  *            @arg TIM_TS_ITR9: Internal trigger 9 selected
+  *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+  *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if (CommutationSource == TIM_COMMUTATION_TRGI)
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR4: Internal trigger 4 selected
+  *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+  *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+  *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+  *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+  *            @arg TIM_TS_ITR9: Internal trigger 9 selected
+  *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+  *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if (CommutationSource == TIM_COMMUTATION_TRGI)
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR4: Internal trigger 4 selected
+  *            @arg TIM_TS_ITR5: Internal trigger 5 selected
+  *            @arg TIM_TS_ITR6: Internal trigger 6 selected
+  *            @arg TIM_TS_ITR7: Internal trigger 7 selected
+  *            @arg TIM_TS_ITR8: Internal trigger 8 selected
+  *            @arg TIM_TS_ITR9: Internal trigger 9 selected
+  *            @arg TIM_TS_ITR10: Internal trigger 10 selected
+  *            @arg TIM_TS_ITR11: Internal trigger 11 selected
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if (CommutationSource == TIM_COMMUTATION_TRGI)
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+  assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+    assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+  }
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmporx;
+  uint32_t bkin_enable_mask;
+  uint32_t bkin_polarity_mask;
+  uint32_t bkin_enable_bitpos;
+  uint32_t bkin_polarity_bitpos;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_MDF1)
+  {
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+  }
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  switch (sBreakInputConfig->Source)
+  {
+    case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM_AF1_BKINE;
+      bkin_enable_bitpos = TIM_AF1_BKINE_Pos;
+      bkin_polarity_mask = TIM_AF1_BKINP;
+      bkin_polarity_bitpos = TIM_AF1_BKINP_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_MDF1:
+    {
+      bkin_enable_mask = TIM_AF1_BKCMP8E;
+      bkin_enable_bitpos = TIM_AF1_BKCMP8E_Pos;
+      /* No polarity bit for MDF. Variable bkin_polarity_mask keeps its default value 0 */
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+
+    default:
+    {
+      bkin_enable_mask = 0U;
+      bkin_polarity_mask = 0U;
+      bkin_enable_bitpos = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+  }
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Get the TIMx_AF1 register value */
+      tmporx = htim->Instance->AF1;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      tmporx &= ~bkin_polarity_mask;
+      tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+      /* Set TIMx_AF1 */
+      htim->Instance->AF1 = tmporx;
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Get the TIMx_AF2 register value */
+      tmporx = htim->Instance->AF2;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      tmporx &= ~bkin_polarity_mask;
+      tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+
+      /* Set TIMx_AF2 */
+      htim->Instance->AF2 = tmporx;
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM1, the parameter can take one of the following values:
+  *            @arg TIM_TIM1_ETR_GPIO           TIM1 ETR is connected to GPIO
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1      TIM1 ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2      TIM1 ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3      TIM1 ETR is connected to ADC1 AWD3
+  *            @arg TIM_TIM1_ETR_ADC2_AWD1      TIM1 ETR is connected to ADC4 AWD1
+  *            @arg TIM_TIM1_ETR_ADC2_AWD2      TIM1 ETR is connected to ADC4 AWD2
+  *            @arg TIM_TIM1_ETR_ADC2_AWD3      TIM1 ETR is connected to ADC4 AWD3
+  *
+  *         For TIM2, the parameter can take one of the following values:
+  *            @arg TIM_TIM2_ETR_GPIO           TIM2 ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_DCMIPP_HSYNC   TIM2_ETR is connected to DCMIPP HSYNC
+  *            @arg TIM_TIM2_ETR_LCD_HSYNC      TIM2_ETR is connected to LCD HSYNC
+  *            @arg TIM_TIM2_ETR_SAI1_FSA       TIM2_ETR is connected to SAI1 FS_A
+  *            @arg TIM_TIM2_ETR_SAI1_FSB       TIM2_ETR is connected to SAI1 FS_B
+  *            @arg TIM_TIM2_ETR_GFXTIM_TE      TIM2_ETR is connected to GFXTIM TE
+  *            @arg TIM_TIM2_ETR_DCMIPP_VSYNC   TIM2_ETR is connected to DCMIPP VSYNC
+  *            @arg TIM_TIM2_ETR_LCD_VSYNC      TIM2_ETR is connected to LCD VSYNC
+  *            @arg TIM_TIM2_ETR_TIM3_ETR       TIM2_ETR is connected to TIM3_ETR
+  *            @arg TIM_TIM2_ETR_TIM4_ETR       TIM2_ETR is connected to TIM4_ETR
+  *            @arg TIM_TIM2_ETR_TIM5_ETR       TIM2_ETR is connected to TIM5_ETR
+  *            @arg TIM_TIM2_ETR_USB1_SOF       TIM2_ETR is connected to USB1 OTG SOF
+  *            @arg TIM_TIM2_ETR_USB2_SOF       TIM2_ETR is connected to USB2 OTG SOF
+  *
+  *         For TIM3, the parameter can take one of the following values:
+  *            @arg TIM_TIM3_ETR_GPIO           TIM3 ETR is connected to GPIO
+  *            @arg TIM_TIM3_ETR_DCMIPP_HSYNC   TIM3 ETR is connected to DCMIPP HSYNC
+  *            @arg TIM_TIM3_ETR_LCD_HSYNC      TIM3 ETR is connected to LCD HSYNC
+  *            @arg TIM_TIM3_ETR_GFXTIM_TE      TIM3 ETR is connected to GFXTIM TE
+  *            @arg TIM_TIM3_ETR_DCMIPP_VSYNC   TIM3 ETR is connected to DCMIPP VSYNC
+  *            @arg TIM_TIM3_ETR_LCD_VSYNC      TIM3 ETR is connected to LCD VSYNC
+  *            @arg TIM_TIM3_ETR_TIM2_ETR       TIM3 ETR is connected to TIM2 ETR
+  *            @arg TIM_TIM3_ETR_TIM4_ETR       TIM3 ETR is connected to TIM4_ETR
+  *            @arg TIM_TIM3_ETR_TIM5_ETR       TIM3 ETR is connected to TIM5_ETR
+  *
+  *         For TIM4, the parameter can take one of the following values:
+  *            @arg TIM_TIM4_ETR_GPIO           TIM4 ETR is connected to GPIO
+  *            @arg TIM_TIM4_ETR_DCMIPP_HSYNC   TIM4 ETR is connected to DCMIPP HSYNC
+  *            @arg TIM_TIM4_ETR_LCD_HSYNC      TIM4 ETR is connected to LCD HSYNC
+  *            @arg TIM_TIM4_ETR_GFXTIM_TE      TIM4 ETR is connected to GFXTIM TE
+  *            @arg TIM_TIM4_ETR_DCMIPP_VSYNC   TIM4 ETR is connected to DCMIPP VSYNC
+  *            @arg TIM_TIM4_ETR_LCD_VSYNC      TIM4 ETR is connected to LCD VSYNC
+  *            @arg TIM_TIM4_ETR_TIM2_ETR       TIM4 ETR is connected to TIM2 ETR
+  *            @arg TIM_TIM4_ETR_TIM3_ETR       TIM4 ETR is connected to TIM3_ETR
+  *            @arg TIM_TIM4_ETR_TIM5_ETR       TIM4 ETR is connected to TIM5_ETR
+  *
+  *         For TIM5, the parameter can take one of the following values:
+  *            @arg TIM_TIM5_ETR_GPIO           TIM5 ETR is connected to GPIO
+  *            @arg TIM_TIM5_ETR_SAI2_FSA       TIM5_ETR is connected to SAI2 FS_A
+  *            @arg TIM_TIM5_ETR_SAI2_FSB       TIM5_ETR is connected to SAI2 FS_B
+  *            @arg TIM_TIM5_ETR_DCMIPP_HSYNC   TIM5 ETR is connected to DCMIPP HSYNC
+  *            @arg TIM_TIM5_ETR_LCD_HSYNC      TIM5 ETR is connected to LCD HSYNC
+  *            @arg TIM_TIM5_ETR_GFXTIM_TE      TIM5 ETR is connected to GFXTIM TE
+  *            @arg TIM_TIM5_ETR_DCMIPP_VSYNC   TIM5 ETR is connected to DCMIPP VSYNC
+  *            @arg TIM_TIM5_ETR_LCD_VSYNC      TIM5 ETR is connected to LCD VSYNC
+  *            @arg TIM_TIM5_ETR_TIM2_ETR       TIM5 ETR is connected to TIM2_ETR
+  *            @arg TIM_TIM5_ETR_TIM3_ETR       TIM5 ETR is connected to TIM3_ETR
+  *            @arg TIM_TIM5_ETR_TIM4_ETR       TIM5 ETR is connected to TIM4_ETR
+  *            @arg TIM_TIM5_ETR_USB1_SOF       TIM5_ETR is connected to USB1 OTG SOF
+  *            @arg TIM_TIM5_ETR_USB2_SOF       TIM5_ETR is connected to USB2 OTG SOF
+  *
+  *         For TIM8, the parameter can take one of the following values:
+  *            @arg TIM_TIM8_ETR_GPIO           TIM8 ETR is connected to GPIO
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1      TIM8 ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2      TIM8 ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3      TIM8 ETR is connected to ADC2 AWD3
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP(htim->Instance, Remap));
+
+  __HAL_LOCK(htim);
+
+  MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the timer input source
+  * @param  htim TIM handle.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TI1 input channel
+  *            @arg TIM_CHANNEL_2: TI2 input channel
+  * @param  TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_TI1_GPIO:                TIM2 TI1 is connected to GPIO
+  *            @arg TIM_TIM2_TI1_ETH1_PPS:            TIM2 TI1 is connected to ETH1 PPS
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg TIM_TIM3_TI1_ETH1_PPS:            TIM3 TI1 is connected to ETH1 PPS
+  *            @arg TIM_TIM3_TI1_FDCAN_RTP            TIM3_TI1 is connected to FDCAN RTP
+  *            @arg TIM_TIM3_TI1_FDCAN_TMP            TIM3_TI1 is connected to FDCAN TMP
+  *            @arg TIM_TIM3_TI1_FDCAN_SOC            TIM3_TI1 is connected to FDCAN SOC
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg TIM_TIM5_TI1_FDCAN_RTP            TIM5_TI1 is connected to FDCAN RTP
+  *            @arg TIM_TIM5_TI1_FDCAN_TMP            TIM5_TI1 is connected to FDCAN TMP
+  *
+  *         For TIM9, the parameter is one of the following values:
+  *            @arg TIM_TIM9_TI1_GPIO:                TIM9 TI1 is connected to GPIO
+  *            @arg TIM_TIM9_TI1_MCO1:                TIM9 TI1 is connected to MCO1
+  *            @arg TIM_TIM9_TI1_MCO2:                TIM9 TI1 is connected to MCO2
+  *
+  *         For TIM10, the parameter is one of the following values:
+  *            @arg TIM_TIM10_TI1_GPIO                TIM10_TI1 is connected to GPIO
+  *            @arg TIM_TIM10_TI1_I3C1_IBIACK         TIM10_TI1 is connected to I3C1 IBI ACK
+  *
+  *         For TIM11, the parameter is one of the following values:
+  *            @arg TIM_TIM11_TI1_GPIO                TIM11_TI1 is connected to GPIO
+  *            @arg TIM_TIM11_TI1_I3C2_IBIACK         TIM11_TI1 is connected to I3C2 IBI ACK
+  *
+  *         For TIM12, the parameter is one of the following values:
+  *            @arg TIM_TIM12_TI1_GPIO:                TIM12 TI1 is connected to GPIO
+  *            @arg TIM_TIM12_TI1_SPDIF_FS:            TIM12 TI1 is connected to SPDIF FS
+  *            @arg TIM_TIM12_TI1_HSI_1024:            TIM12 TI1 is connected to HSI/1024
+  *            @arg TIM_TIM12_TI1_MSI_128:             TIM12_TI1 is connected to MSI/128
+  *            @arg TIM_TIM12_TI1_MCO1:                TIM12 TI1 is connected to MCO1
+  *            @arg TIM_TIM12_TI1_MCO2:                TIM12 TI1 is connected to MCO2
+  *
+  *         For TIM13, the parameter is one of the following values:
+  *            @arg TIM_TIM13_TI1_GPIO                TIM13_TI1 is connected to GPIO
+  *            @arg TIM_TIM13_TI1_I3C1_IBIACK         TIM13_TI1 is connected to I3C1 IBI ACK
+  *
+  *         For TIM14, the parameter is one of the following values:
+  *            @arg TIM_TIM14_TI1_GPIO                TIM14_TI1 is connected to GPIO
+  *            @arg TIM_TIM14_TI1_I3C2_IBIACK         TIM14_TI1 is connected to I3C2 IBI ACK
+  *
+  *         For TIM15, the parameter is one of the following values:
+  *            @arg TIM_TIM15_TI1_GPIO:                TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_TIM2_CH1:            TIM15 TI1 is connected to TIM2 CH1
+  *            @arg TIM_TIM15_TI1_TIM3_CH1:            TIM15 TI1 is connected to TIM3 CH1
+  *            @arg TIM_TIM15_TI1_TIM4_CH1:            TIM15 TI1 is connected to TIM4 CH1
+  *            @arg TIM_TIM15_TI1_MCO1:                TIM15 TI1 is connected to MCO1
+  *            @arg TIM_TIM15_TI1_MCO2:                TIM15 TI1 is connected to MCO2
+  *            @arg TIM_TIM15_TI2_GPIO:                TIM15 TI2 is connected to GPIO
+  *            @arg TIM_TIM15_TI2_TIM2_CH2:            TIM15 TI2 is connected to TIM2 CH2
+  *            @arg TIM_TIM15_TI2_TIM3_CH2:            TIM15 TI2 is connected to TIM3 CH2
+  *            @arg TIM_TIM15_TI2_TIM4_CH2:            TIM15 TI2 is connected to TIM4 CH2
+  *
+  *         For TIM16, the parameter is one of the following values:
+  *            @arg TIM_TIM16_TI1_GPIO:                TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_LSI                  TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_LSE                  TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_RTC_WKUP:            TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  *         For TIM17, the parameter is one of the following values:
+  *            @arg TIM_TIM17_TI1_GPIO:                TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_SPDIF_FS:            TIM17 TI1 is connected to SPDIF FS
+  *            @arg TIM_TIM17_TI1_HSE_1024:            TIM17 TI1 is connected to HSE/1024
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_TISEL(TISelection));
+
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+      break;
+    case TIM_CHANNEL_2:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim TIM handle.
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disarm the designated break input (when it operates in bidirectional mode).
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to disarm
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpbdtr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Check initial conditions */
+      tmpbdtr = READ_REG(htim->Instance->BDTR);
+      if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+          (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+      {
+        /* Break input BRK is disarmed */
+        SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+      }
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Check initial conditions */
+      tmpbdtr = READ_REG(htim->Instance->BDTR);
+      if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+          (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+      {
+        /* Break input BRK is disarmed */
+        SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Arm the designated break input (when it operates in bidirectional mode).
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to arm
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @note  Arming is possible at anytime, even if fault is present.
+  * @note  Break input is automatically armed as soon as MOE bit is set.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Check initial conditions */
+      if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+      {
+        /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+        while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+        {
+          if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+          {
+            /* New check to avoid false timeout detection in case of preemption */
+            if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+            {
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+      }
+      break;
+    }
+
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Check initial conditions */
+      if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+      {
+        /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+        while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+        {
+          if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+          {
+            /* New check to avoid false timeout detection in case of preemption */
+            if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+            {
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable dithering
+  * @param  htim TIM handle
+  * @note   Main usage is PWM mode
+  * @note   This function must be called when timer is stopped or disabled (CEN =0)
+  * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+  *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
+  *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
+  *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
+  *           - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
+  *             (corresponds to 4094 for the integer part and 15 for the dithered part).
+  * @note   Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER()  __HAL_TIM_CALC_PULSE_DITHER()
+  *         can be used to calculate period (ARR) and delay (CCRx) value.
+  * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+  * @note   Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+  *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+  *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable dithering
+  * @param  htim TIM handle
+  * @note   This function must be called when timer is stopped or disabled (CEN =0)
+  * @note   If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
+  *           - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
+  *           - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
+  *           - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
+  *           - ARR and CCRx values are limited to 0xFFEF in dithering mode
+  *             (corresponds to 4094 for the integer part and 15 for the dithered part).
+  * @note   Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
+  *         So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
+  *         __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the pulse on compare pulse width and pulse prescaler
+  * @param  htim TIM Output Compare handle
+  * @param  PulseWidthPrescaler  Pulse width prescaler
+  *         This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
+  * @param  PulseWidth  Pulse width
+  *         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
+                                                    uint32_t PulseWidthPrescaler,
+                                                    uint32_t PulseWidth)
+{
+  uint32_t tmpecr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
+  assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx ECR register value */
+  tmpecr = htim->Instance->ECR;
+  /* Reset the Pulse width prescaler and the Pulse width */
+  tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
+  /* Set the Pulse width prescaler and Pulse width*/
+  tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
+  tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
+  /* Write to TIMx ECR */
+  htim->Instance->ECR = tmpecr;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
+  * @param  htim TIM handle
+  * @param  Source Source of slave mode selection preload
+  *         This parameter can be one of the following values:
+  *            @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
+  *            @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
+
+  MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable deadtime preload
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable deadtime preload
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure deadtime
+  * @param  htim TIM handle
+  * @param  Deadtime Deadtime value
+  * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DEADTIME(Deadtime));
+
+  MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure asymmetrical deadtime
+  * @param  htim TIM handle
+  * @param  FallingDeadtime Falling edge deadtime value
+  * @note   This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DEADTIME(FallingDeadtime));
+
+  MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable asymmetrical deadtime
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable asymmetrical deadtime
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the encoder index.
+  * @note   warning in case of encoder mode clock plus direction
+  *                    @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+  *         Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
+  * @param  htim TIM handle.
+  * @param  sEncoderIndexConfig Encoder index configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
+                                               TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
+  assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
+  assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
+  assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking));
+  assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
+  assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
+  assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Configures the TIMx External Trigger (ETR) which is used as Index input */
+  TIM_ETR_SetConfig(htim->Instance,
+                    sEncoderIndexConfig->Prescaler,
+                    sEncoderIndexConfig->Polarity,
+                    sEncoderIndexConfig->Filter);
+
+  /* Configures the encoder index */
+  MODIFY_REG(htim->Instance->ECR,
+             TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
+             (sEncoderIndexConfig->Direction |
+              (sEncoderIndexConfig->Blanking) |
+              ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
+              sEncoderIndexConfig->Position |
+              TIM_ECR_IE));
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable encoder index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable encoder index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable encoder first index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable encoder first index
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC synchronization
+  * @param  htim TIM handle
+  * @note This mode can be enabled only when the counter period or the compare
+  *       value - as per configured ADC trigger - is a multiple of the ADC clock
+  *       period.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_EnableADCSynchronization(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+
+  SET_BIT(htim->Instance->CR2, TIM_CR2_ADSYNC);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable ADC synchronization
+  * @param  htim TIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisableADCSynchronization(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+
+  CLEAR_BIT(htim->Instance->CR2, TIM_CR2_ADSYNC);
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Commutation callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Commutation half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Encoder index callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Direction change callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Index error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transition error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return actual state of the TIM complementary channel.
+  * @param  htim TIM handle
+  * @param  ChannelN TIM Complementary channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @retval TIM Complementary channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+  return channel_state;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA error callback (complementary channel)
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_timebase_rtc_wakeup_template.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_timebase_rtc_wakeup_template.c
new file mode 100644
index 000000000..6ad741555
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_timebase_rtc_wakeup_template.c
@@ -0,0 +1,269 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_timebase_rtc_wakeup_template.c
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware RTC_WAKEUP Template.
+  *
+  *          This file overrides the native HAL time base functions (defined as weak)
+  *          to use the RTC WAKEUP for the time base generation:
+  *           + Initializes the RTC peripheral and configures the wakeup timer to be
+  *             incremented each 1ms
+  *           + The wakeup feature is configured to assert an interrupt each 1ms
+  *           + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
+  *           + HSE (default), LSE or LSI can be selected as RTC clock source
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32n6xx_hal_timebase_rtc_wakeup.c'
+    (#) Add this file and the RTC HAL drivers to your project and uncomment
+       HAL_RTC_MODULE_ENABLED define in stm32n6xx_hal_conf.h
+
+    [..]
+    (@) HAL RTC alarm and HAL RTC wakeup drivers can not be used with low power modes:
+        The wake up capability of the RTC may be intrusive in case of prior low power mode
+        configuration requiring different wake up sources.
+        Application/Example behavior is no more guaranteed
+    (@) The stm32n6xx_hal_timebase_tim use is recommended for the Applications/Examples
+          requiring low power modes
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL_TimeBase_RTC_Alarm_Template  HAL TimeBase RTC Alarm Template
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+  + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+  + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+                          precision.
+  + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+                          precision.
+  */
+/* #define RTC_CLOCK_SOURCE_HSE */
+/* #define RTC_CLOCK_SOURCE_LSE */
+#define RTC_CLOCK_SOURCE_LSI
+
+/* The time base should be 1ms
+   Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+*/
+#if defined (RTC_CLOCK_SOURCE_HSE)
+#define RTC_ASYNCH_PREDIV      99U
+#define RTC_SYNCH_PREDIV        4U
+#elif defined (RTC_CLOCK_SOURCE_LSE)
+#define RTC_ASYNCH_PREDIV       0U
+#define RTC_SYNCH_PREDIV       32U
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+#define RTC_ASYNCH_PREDIV       0U
+#define RTC_SYNCH_PREDIV       31U
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static RTC_HandleTypeDef        hRTC_Handle;
+
+/* Private function prototypes -----------------------------------------------*/
+void RTC_IRQHandler(void);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) */
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the RTC_ALARMA as a time base source.
+  *         The time source is configured to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+  * @param  TickPriority Tick interrupt priority.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  HAL_StatusTypeDef  Status;
+
+  RCC_OscInitTypeDef        RCC_OscInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = {0};
+
+  /* Disable bkup domain protection */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  HAL_PWR_EnableBkUpAccess();
+
+  /* Force and Release the Backup domain reset */
+  __HAL_RCC_BACKUPRESET_FORCE();
+  __HAL_RCC_BACKUPRESET_RELEASE();
+
+  /* Enable RTC Clock */
+  __HAL_RCC_RTC_ENABLE();
+  __HAL_RCC_RTCAPB_CLK_ENABLE();
+
+#if defined (RTC_CLOCK_SOURCE_LSE)
+  /* Configure LSE as RTC clock source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.PLL1.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL2.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL3.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL4.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSEState            = RCC_LSE_RTC_ONLY;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+  /* Configure LSI as RTC clock source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_LSI;
+  RCC_OscInitStruct.PLL1.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL2.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL3.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL4.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.LSIState            = RCC_LSI_ON;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+  /* Configure HSE as RTC clock source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.PLL1.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL2.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL3.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL4.PLLState       = RCC_PLL_NONE;
+  RCC_OscInitStruct.HSEState            = RCC_HSE_ON;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+  Status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  if (Status == HAL_OK)
+  {
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+    Status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+  }
+
+  if (Status == HAL_OK)
+  {
+    hRTC_Handle.Instance = RTC;
+    hRTC_Handle.Init.HourFormat     = RTC_HOURFORMAT_24;
+    hRTC_Handle.Init.AsynchPrediv   = RTC_ASYNCH_PREDIV;
+    hRTC_Handle.Init.SynchPrediv    = RTC_SYNCH_PREDIV;
+    hRTC_Handle.Init.OutPut         = RTC_OUTPUT_DISABLE;
+    hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+    hRTC_Handle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
+    hRTC_Handle.Init.BinMode        = RTC_BINARY_NONE;
+
+    Status = HAL_RTC_Init(&hRTC_Handle);
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+    HAL_RTC_RegisterCallback(&hRTC_Handle, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, TimeBase_RTCEx_WakeUpTimerEventCallback);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) */
+  }
+
+  if (Status == HAL_OK)
+  {
+    Status = HAL_RTCEx_SetWakeUpTimer_IT(&hRTC_Handle, 0, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, 0);
+  }
+
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    /* Enable the RTC global Interrupt */
+    HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    Status = HAL_ERROR;
+  }
+
+  HAL_NVIC_EnableIRQ(RTC_IRQn);
+
+  return Status;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling RTC_WKUP interrupt.
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+  /* Disable WAKE UP TIMER Interrupt */
+  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling RTC_WKUP interrupt.
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Disable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+  /* Enable  WAKE UP TIMER  interrupt */
+  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+  /* Enable the write protection for RTC registers */
+  __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+}
+
+/**
+  * @brief  Wake Up Timer Event Callback in non blocking mode
+  * @note   This function is called  when RTC_WKUP interrupt took place, inside
+  * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  hrtc RTC handle
+  * @retval None
+  */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U)
+void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+#else
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
+
+  HAL_IncTick();
+}
+
+/**
+  * @brief  This function handles  WAKE UP TIMER  interrupt request.
+  * @retval None
+  */
+void RTC_IRQHandler(void)
+{
+  HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_timebase_tim_template.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_timebase_tim_template.c
new file mode 100644
index 000000000..898293291
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_timebase_tim_template.c
@@ -0,0 +1,203 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbaxx_hal_timebase_tim_template.c
+  * @author  MCD Application Team
+  * @brief   HAL time base based on the hardware TIM.
+  *
+  *          This file overrides the native HAL time base functions (defined as weak)
+  *          the TIM time base:
+  *           + Initializes the TIM peripheral to generate a Period elapsed Event each 1ms
+  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    This file must be copied to the application folder and modified as follows:
+    (#) Rename it to 'stm32n6xx_hal_timebase_tim.c'
+    (#) Add this file and the TIM HAL drivers to your project and uncomment
+       HAL_TIM_MODULE_ENABLED define in stm32n6xx_hal_conf.h
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL_TimeBase
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TIM_CNT_FREQ 1000000U /* Timer frequency counter : 1 MHz */
+#define TIM_FREQ     1000U    /* Timer frequency : 1 kHz => to have 1 ms interrupt */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static TIM_HandleTypeDef        TimHandle;
+
+/* Private function prototypes -----------------------------------------------*/
+void TIM2_IRQHandler(void);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U)
+void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+#endif /* (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) */
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function configures the TIM2 as a time base source.
+  *         The time source is configured  to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
+  * @note   This function is called  automatically at the beginning of program after
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+  * @param  TickPriority Tick interrupt priority.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  RCC_ClkInitTypeDef    clkconfig;
+  uint32_t              uwTimclock;
+  uint32_t              uwAPB1Prescaler;
+  uint32_t              uwPrescalerValue;
+  HAL_StatusTypeDef     Status;
+
+  /* Enable TIM2 clock */
+  __HAL_RCC_TIM2_CLK_ENABLE();
+
+  /* Get clock configuration */
+  HAL_RCC_GetClockConfig(&clkconfig);
+
+  /* Get APB1 prescaler */
+  uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+
+  /* Compute TIM2 clock */
+  if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+  {
+    uwTimclock = HAL_RCC_GetPCLK1Freq();
+  }
+  else
+  {
+    uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
+  }
+
+  /* Compute the prescaler value to have TIM2 counter clock equal to TIM_CNT_FREQ */
+  uwPrescalerValue = (uint32_t)((uwTimclock / TIM_CNT_FREQ) - 1U);
+
+  /* Initialize TIM2 */
+  TimHandle.Instance = TIM2;
+
+  /* Initialize TIMx peripheral as follow:
+  + Period = [(TIM_CNT_FREQ/TIM_FREQ) - 1]. to have a (1/TIM_FREQ) s time base.
+  + Prescaler = (uwTimclock/TIM_CNT_FREQ - 1) to have a TIM_CNT_FREQ counter clock.
+  + ClockDivision = 0
+  + Counter direction = Up
+  */
+  TimHandle.Init.Period = (TIM_CNT_FREQ / TIM_FREQ) - 1U;
+  TimHandle.Init.Prescaler = uwPrescalerValue;
+  TimHandle.Init.ClockDivision = 0;
+  TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+  Status = HAL_TIM_Base_Init(&TimHandle);
+  if (Status == HAL_OK)
+  {
+    /* Start the TIM time Base generation in interrupt mode */
+    Status = HAL_TIM_Base_Start_IT(&TimHandle);
+    if (Status == HAL_OK)
+    {
+      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+      {
+        /* Enable the TIM2 global Interrupt */
+        HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority, 0);
+        uwTickPrio = TickPriority;
+      }
+      else
+      {
+        Status = HAL_ERROR;
+      }
+    }
+  }
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U)
+  HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback);
+#endif /* (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) */
+
+  HAL_NVIC_EnableIRQ(TIM2_IRQn);
+
+  /* Return function Status */
+  return Status;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   Disable the tick increment by disabling TIM2 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_SuspendTick(void)
+{
+  /* Disable TIM2 update Interrupt */
+  __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   Enable the tick increment by Enabling TIM2 update interrupt.
+  * @param  None
+  * @retval None
+  */
+void HAL_ResumeTick(void)
+{
+  /* Enable TIM2 Update interrupt */
+  __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+  * @brief  Period elapsed callback in non blocking mode
+  * @note   This function is called  when TIM2 interrupt took place, inside
+  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+  * a global variable "uwTick" used as application time base.
+  * @param  htim TIM handle
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U)
+void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+#else
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+#endif /* (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  HAL_IncTick();
+}
+
+/**
+  * @brief  This function handles TIM interrupt request.
+  * @param  None
+  * @retval None
+  */
+void TIM2_IRQHandler(void)
+{
+  HAL_TIM_IRQHandler(&TimHandle);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_uart.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_uart.c
new file mode 100644
index 000000000..afe1ae99f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_uart.c
@@ -0,0 +1,4791 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) UART interrupts handling:
+              -@@-  The specific UART interrupts (Transmission complete interrupt,
+                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+                inside the transmit and receive processes.
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+        in the huart handle AdvancedInit structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+        by calling the HAL_LIN_Init() API.
+
+    (#) For the UART Multiprocessor mode, initialize the UART registers
+        by calling the HAL_MultiProcessor_Init() API.
+
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    [..]
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+        calling the customized HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_UART_RegisterCallback() to register a user callback.
+    Function HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    For specific callback RxEventCallback, use dedicated registration/reset functions:
+    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+
+    [..]
+    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak functions in the HAL_UART_Init()
+    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+    or HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+                                      USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+                                      USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
+#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+  * @{
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+  * @{
+  */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+  * @}
+  */
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+    and UART multiprocessor mode configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+  Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Initialize the half-duplex mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check UART instance */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the LIN mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart             UART handle.
+  * @param BreakDetectLength Specifies the LIN break detection length.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  /* LIN mode limited to 16-bit oversampling only */
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    return HAL_ERROR;
+  }
+  /* LIN mode limited to 8-bit data length */
+  if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In LIN mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the multiprocessor mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart        UART handle.
+  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod Specifies the UART wakeup method.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+  * @note  If the user resorts to idle line detection wake up, the Address parameter
+  *        is useless and ignored by the initialization function.
+  * @note  If the user resorts to address mark wake up, the address length detection
+  *        is configured by default to 4 bits only. For the UART to be able to
+  *        manage 6-, 7- or 8-bit long addresses detection, the API
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+  *        HAL_MultiProcessor_Init().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the wake up method parameter */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In multiprocessor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+  {
+    /* If address mark wake up method is chosen, set the USART address node */
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+  }
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief DeInitialize the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  huart->Instance->CR1 = 0x0U;
+  huart->Instance->CR2 = 0x0U;
+  huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @note   The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback          */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+                                                                                  AbortTransmitCpltCallback          */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
+                                                                                  AbortReceiveCpltCallback           */
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback         */
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback     */
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback    */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback        */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User UART Rx Event Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart     Uart handle
+  * @param  pCallback Pointer to the Rx Event Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = pCallback;
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the UART Rx Event Callback
+  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+  * @param  huart     Uart handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  * @brief UART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+        reception services:
+        (+) HAL_UARTEx_RxEventCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+           in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+           to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+           Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+           user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+  *       data to the TXFIFO. Write operations to the TDR register are performed
+  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
+  *       TXE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (const uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      huart->gState = HAL_UART_STATE_READY;
+
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        huart->RxState = HAL_UART_STATE_READY;
+
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+        pdata16bits++;
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+    huart->TxISR       = NULL;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Configure Tx interrupt processing */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+      }
+
+      /* Enable the TX FIFO threshold interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT;
+      }
+
+      /* Enable the Transmit Data Register Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_IT(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+  uint16_t nbByte = Size;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+         should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        nbByte = Size * 2U;
+      }
+
+      /* Check linked list mode */
+      if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL))
+        {
+          /* Set DMA data size */
+          huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+          /* Set DMA source address */
+          huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr;
+
+          /* Set DMA destination address */
+          huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+            (uint32_t)&huart->Instance->TDR;
+
+          /* Enable the UART transmit DMA channel */
+          status = HAL_DMAEx_List_Start_IT(huart->hdmatx);
+        }
+        else
+        {
+          /* Update status */
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Enable the UART transmit DMA channel */
+        status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte);
+      }
+
+      if (status != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the UART CR3 register */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_DMA(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Suspend callback to Null.
+         No call back execution at end of DMA Suspend procedure */
+      huart->hdmatx->XferSuspendCallback = NULL;
+
+      if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Set the UART DMA Suspend callback to Null.
+         No call back execution at end of DMA Suspend procedure */
+      huart->hdmarx->XferSuspendCallback = NULL;
+
+      if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Resume the UART DMA Tx channel */
+    if (huart->hdmatx != NULL)
+    {
+      if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Resume the UART DMA Rx channel */
+    if (huart->hdmarx != NULL)
+    {
+      if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if (huart->hdmatx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if (huart->hdmarx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+                                          USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+                                          USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0U;
+    huart->RxXferCount = 0U;
+
+    /* Clear ISR function pointers */
+    huart->RxISR = NULL;
+    huart->TxISR = NULL;
+
+    /* Reset errorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Discard the received data */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0U;
+
+      /* Clear TxISR function pointers */
+      huart->TxISR = NULL;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0U;
+
+    /* Clear TxISR function pointers */
+    huart->TxISR = NULL;
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0U;
+
+      /* Clear RxISR function pointer */
+      huart->pRxBuffPtr = NULL;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+      /* Discard the received data */
+      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+#endif /* HAL_DMA_MODULE_ENABLED */
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0U;
+
+    /* Clear RxISR function pointer */
+    huart->pRxBuffPtr = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == 0U)
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (huart->RxISR != NULL)
+      {
+        huart->RxISR(huart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (huart->RxISR != NULL)
+        {
+          huart->RxISR(huart);
+        }
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+        /* Abort the UART DMA Rx channel if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          /* Disable the UART DMA Rx request if enabled */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+          }
+        }
+        else
+#endif /* HAL_DMA_MODULE_ENABLED */
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      && ((isrflags & USART_ISR_IDLE) != 0U)
+      && ((cr1its & USART_ISR_IDLE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+      if ((nb_remaining_rx_data > 0U)
+          && (nb_remaining_rx_data < huart->RxXferSize))
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR)
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+        }
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* If DMA is in Circular mode, Idle event is to be reported to user
+           even if occurring after a Transfer Complete event from DMA */
+        if (nb_remaining_rx_data == huart->RxXferSize)
+        {
+          if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR)
+          {
+            /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+               In this case, Rx Event type is Idle Event */
+            huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered Rx Event callback*/
+            huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+            /*Call legacy weak Rx Event callback*/
+            HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+          }
+        }
+      }
+      return;
+    }
+    else
+    {
+#endif /* HAL_DMA_MODULE_ENABLED */
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+      if ((huart->RxXferCount > 0U)
+          && (nb_rx_data > 0U))
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+#if defined(HAL_DMA_MODULE_ENABLED)
+    }
+#endif /* HAL_DMA_MODULE_ENABLED */
+  }
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+    /* UART Rx state is not reset as a reception process might be ongoing.
+       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (huart->TxISR != NULL)
+    {
+      huart->TxISR(huart);
+    }
+    return;
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    huart->TxFifoEmptyCallback(huart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    huart->RxFifoFullCallback(huart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
+  * @param  huart UART handle
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the UART.
+     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+     (+) UART_SetConfig() API configures the UART peripheral
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+     (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Update on the fly the receiver timeout value in RTOR register.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+    MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+  }
+}
+
+/**
+  * @brief  Enable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Set the USART RTOEN bit */
+      SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Clear the USART RTOEN bit */
+      CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
+  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+  *         as it may not have been in mute mode at this very moment).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Enter UART mute mode (means UART actually enters mute mode).
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+  * @brief  Enable the UART transmitter and disable the UART receiver.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the UART receiver and disable the UART transmitter.
+  * @param  huart UART handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Transmit break characters.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   UART Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the UART handle state.
+      (+) Return the UART handle error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the UART handle state.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
+{
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART handle error code.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
+  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
+  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
+  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  uint64_t clocksource;
+  uint32_t usartdiv;
+  HAL_StatusTypeDef ret               = HAL_OK;
+  uint32_t lpuart_ker_ck_pres;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+  }
+  else
+  {
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+  }
+
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    /* Retrieve frequency clock */
+    pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+    /* If proper clock source reported */
+    if (pclk != 0U)
+    {
+      /* Compute clock after Prescaler */
+      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+        /* Check computed UsartDiv value is in allocated range
+           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+        {
+          huart->Instance->BRR = usartdiv;
+        }
+        else
+        {
+          ret = HAL_ERROR;
+        }
+      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (pclk != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if (pclk != 0U)
+    {
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+        huart->Instance->BRR = brrtemp;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+  else
+  {
+    pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+    if (pclk != 0U)
+    {
+      /* USARTDIV must be greater than or equal to 0d16 */
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        huart->Instance->BRR = (uint16_t)usartdiv;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+  huart->NbRxDataToProcess = 1;
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+  huart->TxISR = NULL;
+
+  return ret;
+}
+
+/**
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+  }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+  }
+}
+
+/**
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Disable TXE interrupt for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+      interrupts for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      huart->RxState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles UART Communication Timeout. It waits
+  *                  until a flag is no longer in the specified status.
+  * @param huart     UART handle.
+  * @param Flag      Specifies the UART flag to check
+  * @param Status    The actual Flag status (SET or RESET)
+  * @param Tickstart Tick start value
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+
+        return HAL_TIMEOUT;
+      }
+
+      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+        {
+          /* Clear Overrun Error flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+
+          huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_ERROR;
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in interrupt mode.
+  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr  = pData;
+  huart->RxXferSize  = Size;
+  huart->RxXferCount = Size;
+  huart->RxISR       = NULL;
+
+  /* Computation of UART mask to apply to RDR register */
+  UART_MASK_COMPUTATION(huart);
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Configure Rx interrupt processing */
+  if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+    }
+
+    /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+  }
+  else
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT;
+    }
+
+    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+    else
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief  Start Receive operation in DMA mode.
+  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+  uint16_t nbByte = Size;
+
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  if (huart->hdmarx != NULL)
+  {
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmarx->XferAbortCallback = NULL;
+
+    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+       should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      nbByte = Size * 2U;
+    }
+
+    /* Check linked list mode */
+    if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+    {
+      if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL))
+      {
+        /* Set DMA data size */
+        huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+        /* Set DMA source address */
+        huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+          (uint32_t)&huart->Instance->RDR;
+
+        /* Set DMA destination address */
+        huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr;
+
+        /* Enable the UART receive DMA channel */
+        status = HAL_DMAEx_List_Start_IT(huart->hdmarx);
+      }
+      else
+      {
+        /* Update status */
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable the UART receive DMA channel */
+      status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte);
+    }
+
+    if (status != HAL_OK)
+    {
+      /* Set error code to DMA */
+      huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+      /* Restore huart->RxState to ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable the UART Parity Error Interrupt */
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+  in the UART CR3 register */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, TXFT interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+}
+
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* Check if DMA in circular mode */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    huart->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx Half complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx Half complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* Check if DMA in circular mode */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+  }
+
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Transfer Complete */
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx complete callback*/
+    huart->RxCpltCallback(huart);
+#else
+    /*Call legacy weak Rx complete callback*/
+    HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART receive process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Half Transfer */
+  huart->RxEventType = HAL_UART_RXEVENT_HT;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Half complete callback*/
+    huart->RxHalfCpltCallback(huart);
+#else
+    /*Call legacy weak Rx Half complete callback*/
+    HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    huart->TxXferCount = 0U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    huart->RxXferCount = 0U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+  huart->RxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+      huart->pTxBuffPtr++;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      tmp = (const uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+      huart->pTxBuffPtr += 2U;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+        huart->pTxBuffPtr++;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        tmp = (const uint16_t *) huart->pTxBuffPtr;
+        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+        huart->pTxBuffPtr += 2U;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8 bits data word length .
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+    huart->pRxBuffPtr++;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    tmp = (uint16_t *) huart->pRxBuffPtr ;
+    *tmp = (uint16_t)(uhdata & uhMask);
+    huart->pRxBuffPtr += 2U;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+      huart->pRxBuffPtr++;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+        break;
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_8BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      tmp = (uint16_t *) huart->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      huart->pRxBuffPtr += 2U;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+        break;
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_16BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_uart_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_uart_ex.c
new file mode 100644
index 000000000..f6b608eb8
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_uart_ex.c
@@ -0,0 +1,1044 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 16U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 16U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart            UART handle.
+  * @param Polarity         Select the driver enable polarity.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime    Driver Enable assertion time:
+  *       5-bit value defining the time between the activation of the DE (Driver Enable)
+  *       signal and the beginning of the start bit. It is expressed in sample time
+  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime  Driver Enable deassertion time:
+  *       5-bit value defining the time between the end of the last stop bit, in a
+  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *       oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime)
+{
+  uint32_t temp;
+
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+  *  @brief Extended functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+    (#) Wakeup from Stop mode Callback:
+        (+) HAL_UARTEx_WakeupCallback()
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_UARTEx_RxFifoFullCallback()
+        (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART RX Fifo full callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART TX Fifo empty callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+    [..] This subsection also provides a set of additional functions providing enhanced reception
+    services to user. (For example, these functions allow application to handle use cases
+    where number of data to be received is unknown).
+
+    (#) Compared to standard reception services which only consider number of received
+        data elements as reception completion criteria, these functions also consider additional events
+        as triggers for updating reception status to caller :
+       (+) Detection of inactivity period (RX line has not been active for a given period).
+          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+               for 1 frame time, after last received byte.
+          (++) RX inactivity detected by RTO, i.e. line has been in idle state
+               for a programmable time, after last received byte.
+       (+) Detection that a specific character has been received.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+           or till IDLE event occurs. Reception is handled only during function execution.
+           When function exits, no data reception could occur. HAL status and number of actually received data elements,
+           are returned by function after finishing transfer.
+       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+           These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+    (#) Blocking mode API:
+        (+) HAL_UARTEx_ReceiveToIdle()
+
+    (#) Non-Blocking mode API with Interrupt:
+        (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+    (#) Non-Blocking mode API with DMA:
+        (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart         UART handle.
+  * @param AddressLength This parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @note It is the application responsibility to enable the interrupt used as
+  *       usart_wkup interrupt source before entering low-power mode.
+  * @param huart           UART handle.
+  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUP_ON_ADDRESS
+  *          @arg @ref UART_WAKEUP_ON_STARTBIT
+  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Wait until REACK flag is set */
+  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->gState = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Set UESM bit */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Clear UESM bit */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Disable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
+  *        or if reception is stopped after IDLE event (less than the expected number of data has been received)
+  *        In this case, RxLen output parameter indicates number of data available in reception buffer.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
+  * @param RxLen   Number of data elements finally received
+  *                (could be lower than Size, in case reception ends on IDLE event)
+  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Initialize output number of received elements */
+    *RxLen = 0U;
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      /* Check if IDLE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+      {
+        /* Clear IDLE flag in ISR */
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+        /* If Set, but no data ever received, clear flag without exiting loop */
+        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+        if (*RxLen > 0U)
+        {
+          huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_OK;
+        }
+      }
+
+      /* Check if RXNE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+      {
+        if (pdata8bits == NULL)
+        {
+          *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+          pdata16bits++;
+        }
+        else
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+          pdata8bits++;
+        }
+        /* Increment number of received elements */
+        *RxLen += 1U;
+        huart->RxXferCount--;
+      }
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set number of received elements in output parameter : RxLen */
+    *RxLen = huart->RxXferSize - huart->RxXferCount;
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+  *        number of received data elements.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    (void)UART_Start_Receive_IT(huart, pData, Size);
+
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+    else
+    {
+      /* In case of errors already pending when reception is started,
+         Interrupts may have already been raised and lead to reception abortion.
+         (Overrun error for instance).
+         In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+      status = HAL_ERROR;
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief Receive an amount of data in DMA mode till either the expected number
+  *        of data is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to DMA services, transferring automatically received data elements in user reception buffer and
+  *        calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+  *        reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+  * @note  When the UART parity is enabled (PCE = 1), the received data contain
+  *        the parity bit (MSB position).
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+  * @note  When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+  *        of reception process is provided to application through calls of Rx Event callback (either default one
+  *        HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+  *        Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+  *        to Rx Event callback execution.
+  * @note  This function is expected to be called within the user implementation of Rx Event Callback,
+  *        in order to provide the accurate value :
+  *        In Interrupt Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one)
+  *        In DMA Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one).
+  *        In DMA mode, RxEvent callback could be called several times;
+  *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
+  *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+  * @param  huart UART handle.
+  * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+  */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
+{
+  /* Return Rx Event type value, as stored in UART handle */
+  return (huart->RxEventType);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart           UART handle.
+  * @param WakeUpSelection UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+  {
+    huart->NbTxDataToProcess = 1U;
+    huart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                               (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                               (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_usart.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_usart.c
new file mode 100644
index 000000000..30f1bb9dc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_usart.c
@@ -0,0 +1,3922 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_usart.c
+  * @author  MCD Application Team
+  * @brief   USART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
+  *          Peripheral (USART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+    [..]
+      The USART HAL driver can be used as follows:
+
+      (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+      (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+          (++) Enable the USARTx interface clock.
+          (++) USART pins configuration:
+            (+++) Enable the clock for the USART GPIOs.
+            (+++) Configure these USART pins as alternate function pull-up.
+          (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+            (++) USART interrupts handling:
+              -@@-   The specific USART interrupts (Transmission complete interrupt,
+                  RXNE interrupt and Error Interrupts) will be managed using the macros
+                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+          (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+               HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer
+                  complete interrupt on the DMA Tx/Rx channel.
+
+      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
+          (Receiver/Transmitter) in the husart handle Init structure.
+
+      (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+               by calling the customized HAL_USART_MspInit(&husart) API.
+
+    [..]
+     (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+        HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
+        HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_USART_RegisterCallback() to register a user callback.
+    Function HAL_USART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : USART MspInit.
+    (+) MspDeInitCallback         : USART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : USART MspInit.
+    (+) MspDeInitCallback         : USART MspDeInit.
+
+    [..]
+    By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak functions in the HAL_USART_Init()
+    and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
+    or HAL_USART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup USART USART
+  * @brief HAL USART Synchronous SPI module driver
+  * @{
+  */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+  * @{
+  */
+#define USART_DUMMY_DATA          ((uint16_t) 0xFFFF)           /*!< USART transmitted dummy data                     */
+#define USART_TEACK_REACK_TIMEOUT             1000U             /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_CR1_FIELDS          ((uint32_t)(USART_CR1_M |  USART_CR1_PCE | USART_CR1_PS    | \
+                                              USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8 | \
+                                              USART_CR1_FIFOEN ))                                  /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+
+#define USART_CR2_FIELDS          ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \
+                                              USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \
+                                              USART_CR2_DIS_NSS))                                  /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+
+#define USART_CR3_FIELDS          ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))             /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */
+
+#define USART_BRR_MIN    0x10U        /* USART BRR minimum authorized value */
+#define USART_BRR_MAX    0xFFFFU      /* USART BRR maximum authorized value */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions
+  * @{
+  */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+#endif /* HAL_DMA_MODULE_ENABLED */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+                                                      uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart);
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USART
+    in synchronous SPI master/slave mode.
+      (+) For the synchronous SPI mode only these parameters can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) USART polarity
+        (++) USART phase
+        (++) USART LastBit
+        (++) Receiver/transmitter modes
+
+    [..]
+    The HAL_USART_Init() function follows the USART synchronous SPI configuration
+    procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible USART formats are listed in the
+  following table.
+
+    Table 1. USART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |            USART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the USART mode according to the specified
+  *         parameters in the USART_InitTypeDef and initialize the associated handle.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+  /* Check the USART handle allocation */
+  if (husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  if (husart->State == HAL_USART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    husart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    USART_InitCallbacksToDefault(husart);
+
+    if (husart->MspInitCallback == NULL)
+    {
+      husart->MspInitCallback = HAL_USART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    husart->MspInitCallback(husart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_USART_MspInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+  }
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_USART_DISABLE(husart);
+
+  /* Set the Usart Communication parameters */
+  if (USART_SetConfig(husart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In Synchronous SPI mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register
+  - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+  */
+  husart->Instance->CR2 &= ~USART_CR2_LINEN;
+  husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+  /* Enable the Peripheral */
+  __HAL_USART_ENABLE(husart);
+
+  /* TEACK and/or REACK to check before moving husart->State to Ready */
+  return (USART_CheckIdleState(husart));
+}
+
+/**
+  * @brief DeInitialize the USART peripheral.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+  /* Check the USART handle allocation */
+  if (husart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_USART_INSTANCE(husart->Instance));
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  husart->Instance->CR1 = 0x0U;
+  husart->Instance->CR2 = 0x0U;
+  husart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  if (husart->MspDeInitCallback == NULL)
+  {
+    husart->MspDeInitCallback = HAL_USART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  husart->MspDeInitCallback(husart);
+#else
+  /* DeInit the low level hardware */
+  HAL_USART_MspDeInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+  husart->State = HAL_USART_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the USART MSP.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the USART MSP.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User USART Callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+  *         to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
+  * @param  husart usart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
++  */
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+                                             pUSART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+        husart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_TX_COMPLETE_CB_ID :
+        husart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+        husart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_RX_COMPLETE_CB_ID :
+        husart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_TX_RX_COMPLETE_CB_ID :
+        husart->TxRxCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_ERROR_CB_ID :
+        husart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_USART_ABORT_COMPLETE_CB_ID :
+        husart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_RX_FIFO_FULL_CB_ID :
+        husart->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_USART_TX_FIFO_EMPTY_CB_ID :
+        husart->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (husart->State == HAL_USART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an USART Callback
+  *         USART callaback is redirected to the weak predefined callback
+  * @note   The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+  *         to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
+  * @param  husart usart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_USART_STATE_READY == husart->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+        husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback  */
+        break;
+
+      case HAL_USART_TX_COMPLETE_CB_ID :
+        husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback       */
+        break;
+
+      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+        husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback   */
+        break;
+
+      case HAL_USART_RX_COMPLETE_CB_ID :
+        husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback       */
+        break;
+
+      case HAL_USART_TX_RX_COMPLETE_CB_ID :
+        husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback     */
+        break;
+
+      case HAL_USART_ERROR_CB_ID :
+        husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_USART_ABORT_COMPLETE_CB_ID :
+        husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_USART_RX_FIFO_FULL_CB_ID :
+        husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback   */
+        break;
+
+      case HAL_USART_TX_FIFO_EMPTY_CB_ID :
+        husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback  */
+        break;
+
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback      */
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback    */
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_USART_STATE_RESET == husart->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = HAL_USART_MspInit;
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = HAL_USART_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+  * @brief   USART Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI
+    data transfers.
+
+    [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input).
+
+    [..]
+
+    (#) There are two modes of transfer:
+        (++) Blocking mode: The communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) No-Blocking mode: The communication is performed using Interrupts
+             or DMA, These API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+             will be executed respectively at the end of the transmit or Receive process
+             The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (++) HAL_USART_Transmit() in simplex mode
+        (++) HAL_USART_Receive() in full duplex receive only
+        (++) HAL_USART_TransmitReceive() in full duplex mode
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (++) HAL_USART_Transmit_IT() in simplex mode
+        (++) HAL_USART_Receive_IT() in full duplex receive only
+        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
+        (++) HAL_USART_IRQHandler()
+
+    (#) No-Blocking mode API's  with DMA are :
+        (++) HAL_USART_Transmit_DMA() in simplex mode
+        (++) HAL_USART_Receive_DMA() in full duplex receive only
+        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+        (++) HAL_USART_DMAPause()
+        (++) HAL_USART_DMAResume()
+        (++) HAL_USART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (++) HAL_USART_TxCpltCallback()
+        (++) HAL_USART_RxCpltCallback()
+        (++) HAL_USART_TxHalfCpltCallback()
+        (++) HAL_USART_RxHalfCpltCallback()
+        (++) HAL_USART_ErrorCallback()
+        (++) HAL_USART_TxRxCpltCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (++) HAL_USART_Abort()
+        (++) HAL_USART_Abort_IT()
+
+    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+        (++) HAL_USART_AbortCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+             to be evaluated by user : this concerns Frame Error,
+             Parity Error or Noise Error in Interrupt mode reception .
+             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
+             error type, and HAL_USART_ErrorCallback() user callback is executed.
+             Transfer is kept ongoing on USART side.
+             If user wants to abort it, Abort services should be called by user.
+        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+             Error code is set to allow user to identify error type,
+             and HAL_USART_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Simplex send an amount of data in blocking mode.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pTxData.
+  * @param  husart USART handle.
+  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size Amount of data elements (u8 or u16) to be sent.
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+                                     uint32_t Timeout)
+{
+  const uint8_t  *ptxdata8bits;
+  const uint16_t *ptxdata16bits;
+  uint32_t tickstart;
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pTxData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      ptxdata8bits  = NULL;
+      ptxdata16bits = (const uint16_t *) pTxData;
+    }
+    else
+    {
+      ptxdata8bits  = pTxData;
+      ptxdata16bits = NULL;
+    }
+
+    /* Check the remaining data to be sent */
+    while (husart->TxXferCount > 0U)
+    {
+      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (ptxdata8bits == NULL)
+      {
+        husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
+        ptxdata16bits++;
+      }
+      else
+      {
+        husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
+        ptxdata8bits++;
+      }
+
+      husart->TxXferCount--;
+    }
+
+    if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Clear Transmission Complete Flag */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+    /* Clear overrun flag and discard the received data */
+    __HAL_USART_CLEAR_OREFLAG(husart);
+    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+    __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+
+    /* At end of Tx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pRxData.
+  * @param husart USART handle.
+  * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *prxdata8bits;
+  uint16_t *prxdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pRxData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+    uhMask = husart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      prxdata8bits  = NULL;
+      prxdata16bits = (uint16_t *) pRxData;
+    }
+    else
+    {
+      prxdata8bits  = pRxData;
+      prxdata16bits = NULL;
+    }
+
+    /* as long as data have to be received */
+    while (husart->RxXferCount > 0U)
+    {
+      if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
+      {
+        /* Wait until TXE flag is set to send dummy byte in order to generate the
+        * clock for the slave to send data.
+        * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+        * can be written for all the cases. */
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
+      }
+
+      /* Wait for RXNE Flag */
+      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+
+      if (prxdata8bits == NULL)
+      {
+        *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+        prxdata16bits++;
+      }
+      else
+      {
+        *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+        prxdata8bits++;
+      }
+
+      husart->RxXferCount--;
+
+    }
+
+    /* Clear SPI slave underrun flag and discard transmit data */
+    if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+    {
+      __HAL_USART_CLEAR_UDRFLAG(husart);
+      __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* At end of Rx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+  *         of u16 available through pTxData and through pRxData.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
+  * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
+  * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+                                            uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *prxdata8bits;
+  uint16_t *prxdata16bits;
+  const uint8_t  *ptxdata8bits;
+  const uint16_t *ptxdata16bits;
+  uint16_t uhMask;
+  uint16_t rxdatacount;
+  uint32_t tickstart;
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    husart->RxXferSize = Size;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+    husart->RxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+    uhMask = husart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+    {
+      prxdata8bits  = NULL;
+      ptxdata8bits  = NULL;
+      ptxdata16bits = (const uint16_t *) pTxData;
+      prxdata16bits = (uint16_t *) pRxData;
+    }
+    else
+    {
+      prxdata8bits  = pRxData;
+      ptxdata8bits  = pTxData;
+      ptxdata16bits = NULL;
+      prxdata16bits = NULL;
+    }
+
+    if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE))
+    {
+      /* Wait until TXE flag is set to send data */
+      if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (ptxdata8bits == NULL)
+      {
+        husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+        ptxdata16bits++;
+      }
+      else
+      {
+        husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+        ptxdata8bits++;
+      }
+
+      husart->TxXferCount--;
+    }
+
+    /* Check the remain data to be sent */
+    /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+    rxdatacount = husart->RxXferCount;
+    while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
+    {
+      if (husart->TxXferCount > 0U)
+      {
+        /* Wait until TXE flag is set to send data */
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+        if (ptxdata8bits == NULL)
+        {
+          husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+          ptxdata16bits++;
+        }
+        else
+        {
+          husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+          ptxdata8bits++;
+        }
+
+        husart->TxXferCount--;
+      }
+
+      if (husart->RxXferCount > 0U)
+      {
+        /* Wait for RXNE Flag */
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+        {
+          return HAL_TIMEOUT;
+        }
+
+        if (prxdata8bits == NULL)
+        {
+          *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+          prxdata16bits++;
+        }
+        else
+        {
+          *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+          prxdata8bits++;
+        }
+
+        husart->RxXferCount--;
+      }
+      rxdatacount = husart->RxXferCount;
+    }
+
+    /* At end of TxRx process, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pTxData.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to data buffer (u8 or u16 data elements).
+  * @param  Size amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
+{
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pTxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pTxBuffPtr  = pTxData;
+    husart->TxXferSize  = Size;
+    husart->TxXferCount = Size;
+    husart->TxISR       = NULL;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State     = HAL_USART_STATE_BUSY_TX;
+
+    /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+    are not managed by the USART Transmit Process to avoid the overrun interrupt
+    when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+    to benefit for the frame error and noise interrupts the usart mode should be
+    configured only for transmit "USART_MODE_TX" */
+
+    /* Configure Tx interrupt processing */
+    if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        husart->TxISR = USART_TxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        husart->TxISR = USART_TxISR_8BIT_FIFOEN;
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Enable the TX FIFO threshold interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        husart->TxISR = USART_TxISR_16BIT;
+      }
+      else
+      {
+        husart->TxISR = USART_TxISR_8BIT;
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Enable the USART Transmit Data Register Empty Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pRxData.
+  * @param  husart USART handle.
+  * @param  pRxData pointer to data buffer (u8 or u16 data elements).
+  * @param  Size amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  uint16_t nb_dummy_data;
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pRxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr  = pRxData;
+    husart->RxXferSize  = Size;
+    husart->RxXferCount = Size;
+    husart->RxISR       = NULL;
+
+    USART_MASK_COMPUTATION(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Configure Rx interrupt processing */
+    if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+    {
+      /* Set the Rx ISR function pointer according to the data word length */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        husart->RxISR = USART_RxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        husart->RxISR = USART_RxISR_8BIT_FIFOEN;
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
+      SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+    }
+    else
+    {
+      /* Set the Rx ISR function pointer according to the data word length */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        husart->RxISR = USART_RxISR_16BIT;
+      }
+      else
+      {
+        husart->RxISR = USART_RxISR_8BIT;
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Enable the USART Parity Error and Data Register not empty Interrupts */
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+      }
+      else
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+      }
+    }
+
+    if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
+    {
+      /* Send dummy data in order to generate the clock for the Slave to send the next data.
+         When FIFO mode is disabled only one data must be transferred.
+         When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold.
+      */
+      if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+      {
+        for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--)
+        {
+          husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+        }
+      }
+      else
+      {
+        husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+      }
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+  *         of u16 available through pTxData and through pRxData.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
+  * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
+  * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+                                               uint16_t Size)
+{
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->RxXferCount = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    /* Computation of USART mask to apply to RDR register */
+    USART_MASK_COMPUTATION(husart);
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    /* Configure TxRx interrupt processing */
+    if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess))
+    {
+      /* Set the Rx ISR function pointer according to the data word length */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        husart->TxISR = USART_TxISR_16BIT_FIFOEN;
+        husart->RxISR = USART_RxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        husart->TxISR = USART_TxISR_8BIT_FIFOEN;
+        husart->RxISR = USART_RxISR_8BIT_FIFOEN;
+      }
+
+      /* Process Locked */
+      __HAL_UNLOCK(husart);
+
+      /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        /* Enable the USART Parity Error interrupt  */
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
+
+      /* Enable the TX and  RX FIFO Threshold interrupts */
+      SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
+    }
+    else
+    {
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        husart->TxISR = USART_TxISR_16BIT;
+        husart->RxISR = USART_RxISR_16BIT;
+      }
+      else
+      {
+        husart->TxISR = USART_TxISR_8BIT;
+        husart->RxISR = USART_RxISR_8BIT;
+      }
+
+      /* Process Locked */
+      __HAL_UNLOCK(husart);
+
+      /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+      }
+      else
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+      }
+
+      /* Enable the USART Transmit Data Register Empty Interrupt */
+      SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pTxData.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to data buffer (u8 or u16 data elements).
+  * @param  Size amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  const uint32_t *tmp;
+  uint16_t nbByte = Size;
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pTxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+    husart->TxXferCount = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX;
+
+    if (husart->hdmatx != NULL)
+    {
+      /* Set the USART DMA transfer complete callback */
+      husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+      /* Set the USART DMA Half transfer complete callback */
+      husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+      /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+         should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        nbByte = Size * 2U;
+      }
+
+      tmp = (const uint32_t *)&pTxData;
+
+      /* Check linked list mode */
+      if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL))
+        {
+          /* Set DMA data size */
+          husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+          /* Set DMA source address */
+          husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp;
+
+          /* Set DMA destination address */
+          husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+            (uint32_t)&husart->Instance->TDR;
+
+          /* Enable the USART transmit DMA channel */
+          status = HAL_DMAEx_List_Start_IT(husart->hdmatx);
+        }
+        else
+        {
+          /* Update status */
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Enable the USART transmit DMA channel */
+        status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte);
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Clear the TC flag in the ICR register */
+      __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Enable the DMA transfer for transmit request by setting the DMAT bit
+         in the USART CR3 register */
+      SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Set error code to DMA */
+      husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Restore husart->State to ready */
+      husart->State = HAL_USART_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note   When the USART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pRxData.
+  * @param  husart USART handle.
+  * @param  pRxData pointer to data buffer (u8 or u16 data elements).
+  * @param  Size amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t *tmp = (uint32_t *)&pRxData;
+  uint16_t nbByte = Size;
+
+  /* Check that a Rx process is not already ongoing */
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pRxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pRxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_RX;
+
+    if (husart->hdmarx != NULL)
+    {
+      /* Set the USART DMA Rx transfer complete callback */
+      husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+      /* Set the USART DMA Half transfer complete callback */
+      husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+      /* Set the USART DMA Rx transfer error callback */
+      husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+      /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+         should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        nbByte = Size * 2U;
+      }
+
+      /* Check linked list mode */
+      if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL))
+        {
+          /* Set DMA data size */
+          husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+          /* Set DMA source address */
+          husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+            (uint32_t)&husart->Instance->RDR;
+
+          /* Set DMA destination address */
+          husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp;
+
+          /* Enable the USART receive DMA channel */
+          status = HAL_DMAEx_List_Start_IT(husart->hdmarx);
+        }
+        else
+        {
+          /* Update status */
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Enable the USART receive DMA channel */
+        status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte);
+      }
+    }
+
+    if ((status == HAL_OK) &&
+        (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+    {
+      /* Enable the USART transmit DMA channel: the transmit channel is used in order
+         to generate in the non-blocking mode the clock to the slave device,
+         this mode isn't a simplex receive mode but a full-duplex receive mode */
+
+      /* Set the USART DMA Tx Complete and Error callback to Null */
+      if (husart->hdmatx != NULL)
+      {
+        husart->hdmatx->XferErrorCallback = NULL;
+        husart->hdmatx->XferHalfCpltCallback = NULL;
+        husart->hdmatx->XferCpltCallback = NULL;
+
+        /* Check linked list mode */
+        if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL))
+          {
+            /* Set DMA data size */
+            husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+            /* Set DMA source address */
+            husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp;
+
+            /* Set DMA destination address */
+            husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+              (uint32_t)&husart->Instance->TDR;
+
+            /* Enable the USART transmit DMA channel */
+            status = HAL_DMAEx_List_Start_IT(husart->hdmatx);
+          }
+          else
+          {
+            /* Update status */
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte);
+        }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        /* Enable the USART Parity Error Interrupt */
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
+
+      /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+         in the USART CR3 register */
+      SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+      /* Enable the DMA transfer for transmit request by setting the DMAT bit
+         in the USART CR3 register */
+      SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+      return HAL_OK;
+    }
+    else
+    {
+      if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST))
+      {
+        status = HAL_DMA_Abort(husart->hdmarx);
+      }
+
+      /* No need to check on error code */
+      UNUSED(status);
+
+      /* Set error code to DMA */
+      husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Restore husart->State to ready */
+      husart->State = HAL_USART_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @note   When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+  *         of u16 available through pTxData and through pRxData.
+  * @param  husart USART handle.
+  * @param  pTxData pointer to TX data buffer (u8 or u16 data elements).
+  * @param  pRxData pointer to RX data buffer (u8 or u16 data elements).
+  * @param  Size amount of data elements (u8 or u16) to be received/sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
+                                                uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+  const uint32_t *tmp;
+  uint16_t nbByte = Size;
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(husart);
+
+    husart->pRxBuffPtr = pRxData;
+    husart->RxXferSize = Size;
+    husart->pTxBuffPtr = pTxData;
+    husart->TxXferSize = Size;
+
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+    husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+    if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
+    {
+      /* Set the USART DMA Rx transfer complete callback */
+      husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+      /* Set the USART DMA Half transfer complete callback */
+      husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+      /* Set the USART DMA Tx transfer complete callback */
+      husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+      /* Set the USART DMA Half transfer complete callback */
+      husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+      /* Set the USART DMA Tx transfer error callback */
+      husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+      /* Set the USART DMA Rx transfer error callback */
+      husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+      /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+         should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
+      if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+      {
+        nbByte = Size * 2U;
+      }
+
+      /* Check linked list mode */
+      tmp = (uint32_t *)&pRxData;
+      if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL))
+        {
+          /* Set DMA data size */
+          husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+          /* Set DMA source address */
+          husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
+            (uint32_t)&husart->Instance->RDR;
+
+          /* Set DMA destination address */
+          husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp;
+
+          /* Enable the USART receive DMA channel */
+          status = HAL_DMAEx_List_Start_IT(husart->hdmarx);
+        }
+        else
+        {
+          /* Update status */
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        /* Enable the USART receive DMA channel */
+        status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, nbByte);
+      }
+
+      /* Enable the USART transmit DMA channel */
+      if (status == HAL_OK)
+      {
+        tmp = (const uint32_t *)&pTxData;
+
+        /* Check linked list mode */
+        if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL))
+          {
+            /* Set DMA data size */
+            husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
+
+            /* Set DMA source address */
+            husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp;
+
+            /* Set DMA destination address */
+            husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
+              (uint32_t)&husart->Instance->TDR;
+
+            /* Enable the USART transmit DMA channel */
+            status = HAL_DMAEx_List_Start_IT(husart->hdmatx);
+          }
+          else
+          {
+            /* Update status */
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte);
+        }
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        /* Enable the USART Parity Error Interrupt */
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
+
+      /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Clear the TC flag in the ICR register */
+      __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+      /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+         in the USART CR3 register */
+      SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+      /* Enable the DMA transfer for transmit request by setting the DMAT bit
+         in the USART CR3 register */
+      SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+      return HAL_OK;
+    }
+    else
+    {
+      if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST))
+      {
+        status = HAL_DMA_Abort(husart->hdmarx);
+      }
+
+      /* No need to check on error code */
+      UNUSED(status);
+
+      /* Set error code to DMA */
+      husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(husart);
+
+      /* Restore husart->State to ready */
+      husart->State = HAL_USART_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
+      (state == HAL_USART_STATE_BUSY_TX))
+  {
+    /* Suspend the USART DMA Tx channel : use blocking DMA Suspend API (no callback) */
+    if (husart->hdmatx != NULL)
+    {
+      /* Set the USART DMA Suspend callback to Null.
+         No call back execution at end of DMA Suspend procedure */
+      husart->hdmatx->XferSuspendCallback = NULL;
+
+      if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else if ((state == HAL_USART_STATE_BUSY_RX) ||
+           (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Set the USART DMA Suspend callback to Null.
+    No call back execution at end of DMA Suspend procedure */
+    husart->hdmarx->XferSuspendCallback = NULL;
+
+    if (HAL_DMAEx_Suspend(husart->hdmarx) != HAL_OK)
+    {
+      if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+      {
+        /* Set error code to DMA */
+        husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+        return HAL_TIMEOUT;
+      }
+    }
+
+    if (state == HAL_USART_STATE_BUSY_TX_RX)
+    {
+      /* Set the USART DMA Suspend callback to Null.
+      No call back execution at end of DMA Suspend procedure */
+      husart->hdmatx->XferSuspendCallback = NULL;
+
+      if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  if (state == HAL_USART_STATE_BUSY_TX)
+  {
+    /* Resume the USART DMA Tx channel */
+    if (husart->hdmatx != NULL)
+    {
+      if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  else if ((state == HAL_USART_STATE_BUSY_RX) ||
+           (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (husart->Init.Parity != USART_PARITY_NONE)
+    {
+      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    }
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Resume the USART DMA Rx channel */
+    if (husart->hdmarx != NULL)
+    {
+      if (HAL_DMAEx_Resume(husart->hdmarx) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+        return HAL_ERROR;
+      }
+    }
+
+    if (state == HAL_USART_STATE_BUSY_TX_RX)
+    {
+      /* Resume the USART DMA Tx channel */
+      if (husart->hdmatx != NULL)
+      {
+        if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK)
+        {
+          /* Set error code to DMA */
+          husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param  husart USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+     HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  /* Disable the USART Tx/Rx DMA requests */
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+  /* Abort the USART DMA tx channel */
+  if (husart->hdmatx != NULL)
+  {
+    if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+    {
+      if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+      {
+        /* Set error code to DMA */
+        husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /* Abort the USART DMA rx channel */
+  if (husart->hdmarx != NULL)
+  {
+    if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+    {
+      if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+      {
+        /* Set error code to DMA */
+        husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  USART_EndTransfer(husart);
+  husart->State = HAL_USART_STATE_READY;
+
+  return HAL_OK;
+}
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable USART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+                                    USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* Abort the USART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the USART DMA Tx request if enabled */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (husart->hdmatx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      husart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Abort the USART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the USART DMA Rx request if enabled */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (husart->hdmarx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      husart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* Reset Tx and Rx transfer counters */
+  husart->TxXferCount = 0U;
+  husart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+  {
+    __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Discard the received data */
+  __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable USART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+                                    USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+  /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (husart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+    {
+      husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+    }
+    else
+    {
+      husart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (husart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+    {
+      husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+    }
+    else
+    {
+      husart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Abort the USART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at USART level */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (husart->hdmatx != NULL)
+    {
+      /* USART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+      {
+        husart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Abort the USART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the USART DMA Rx request if enabled */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (husart->hdmarx != NULL)
+    {
+      /* USART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+      {
+        husart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    husart->TxXferCount = 0U;
+    husart->RxXferCount = 0U;
+
+    /* Reset errorCode */
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (husart->FifoMode == USART_FIFOMODE_ENABLE)
+    {
+      __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Discard the received data */
+    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+    /* Restore husart->State to Ready */
+    husart->State  = HAL_USART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Complete Callback */
+    husart->AbortCpltCallback(husart);
+#else
+    /* Call legacy weak Abort Complete Callback */
+    HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle USART interrupt request.
+  * @param  husart USART handle.
+  * @retval None
+  */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+  uint32_t isrflags   = READ_REG(husart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(husart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(husart->Instance->CR3);
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+                                      USART_ISR_UDR));
+  if (errorflags == 0U)
+  {
+    /* USART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (husart->RxISR != NULL)
+      {
+        husart->RxISR(husart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+          || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
+  {
+    /* USART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_PE;
+    }
+
+    /* USART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_FE;
+    }
+
+    /* USART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_NE;
+    }
+
+    /* USART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_ORE;
+    }
+
+    /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
+
+      husart->ErrorCode |= HAL_USART_ERROR_RTO;
+    }
+
+    /* USART SPI slave underrun error interrupt occurred -------------------------*/
+    if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      /* Ignore SPI slave underrun errors when reception is going on */
+      if (husart->State == HAL_USART_STATE_BUSY_RX)
+      {
+        __HAL_USART_CLEAR_UDRFLAG(husart);
+        return;
+      }
+      else
+      {
+        __HAL_USART_CLEAR_UDRFLAG(husart);
+        husart->ErrorCode |= HAL_USART_ERROR_UDR;
+      }
+    }
+
+    /* Call USART Error Call back function if need be --------------------------*/
+    if (husart->ErrorCode != HAL_USART_ERROR_NONE)
+    {
+      /* USART in mode Receiver ---------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (husart->RxISR != NULL)
+        {
+          husart->RxISR(husart);
+        }
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
+      if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
+          (errorcode != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the USART state ready to be able to start again the process,
+           Disable Interrupts, and disable DMA requests, if ongoing */
+        USART_EndTransfer(husart);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+        /* Abort the USART DMA Rx channel if enabled */
+        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+        {
+          /* Disable the USART DMA Rx request if enabled */
+          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+          /* Abort the USART DMA Tx channel */
+          if (husart->hdmatx != NULL)
+          {
+            /* Set the USART Tx DMA Abort callback to NULL : no callback
+               executed at end of DMA abort procedure */
+            husart->hdmatx->XferAbortCallback = NULL;
+
+            /* Abort DMA TX */
+            (void)HAL_DMA_Abort_IT(husart->hdmatx);
+          }
+
+          /* Abort the USART DMA Rx channel */
+          if (husart->hdmarx != NULL)
+          {
+            /* Set the USART Rx DMA Abort callback :
+               will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
+              husart->hdmarx->XferAbortCallback(husart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+            /* Call registered Error Callback */
+            husart->ErrorCallback(husart);
+#else
+            /* Call legacy weak Error Callback */
+            HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+          }
+        }
+        else
+#endif /* HAL_DMA_MODULE_ENABLED */
+        {
+          /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+          /* Call registered Error Callback */
+          husart->ErrorCallback(husart);
+#else
+          /* Call legacy weak Error Callback */
+          HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+        /* Call registered Error Callback */
+        husart->ErrorCallback(husart);
+#else
+        /* Call legacy weak Error Callback */
+        HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+        husart->ErrorCode = HAL_USART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+
+  /* USART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (husart->TxISR != NULL)
+    {
+      husart->TxISR(husart);
+    }
+    return;
+  }
+
+  /* USART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    USART_EndTransmit_IT(husart);
+    return;
+  }
+
+  /* USART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    husart->TxFifoEmptyCallback(husart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_USARTEx_TxFifoEmptyCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* USART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    husart->RxFifoFullCallback(husart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_USARTEx_RxFifoFullCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief Rx Half Transfer completed callback.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_TxRxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief USART error callback.
+  * @param husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  USART Abort Complete callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   USART Peripheral State and Error functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the USART handle state
+      (+) Return the USART handle error code
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief Return the USART handle state.
+  * @param husart pointer to a USART_HandleTypeDef structure that contains
+  *              the configuration information for the specified USART.
+  * @retval USART handle state
+  */
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart)
+{
+  return husart->State;
+}
+
+/**
+  * @brief Return the USART error code.
+  * @param husart pointer to a USART_HandleTypeDef structure that contains
+  *              the configuration information for the specified USART.
+  * @retval USART handle Error Code
+  */
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
+{
+  return husart->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  husart USART handle.
+  * @retval none
+  */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
+{
+  /* Init the USART Callback settings */
+  husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
+  husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  husart->RxFifoFullCallback        = HAL_USARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
+  husart->TxFifoEmptyCallback       = HAL_USARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/**
+  * @brief  End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+                                    USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* At end of process, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+  * @brief DMA USART transmit process complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+  /* Check if DMA in circular mode */
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    husart->TxXferCount = 0U;
+
+    if (husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+      /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+         in the USART CR3 register */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+    }
+  }
+  /* DMA Circular mode */
+  else
+  {
+    if (husart->State == HAL_USART_STATE_BUSY_TX)
+    {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Tx Complete Callback */
+      husart->TxCpltCallback(husart);
+#else
+      /* Call legacy weak Tx Complete Callback */
+      HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief DMA USART transmit process half complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx Half Complete Callback */
+  husart->TxHalfCpltCallback(husart);
+#else
+  /* Call legacy weak Tx Half Complete Callback */
+  HAL_USART_TxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA USART receive process complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+  /* Check if DMA in circular mode*/
+  if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
+  {
+    husart->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+       in USART CR3 register */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+    /* similarly, disable the DMA TX transfer that was started to provide the
+       clock to the slave device */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    if (husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx Complete Callback */
+      husart->RxCpltCallback(husart);
+#else
+      /* Call legacy weak Rx Complete Callback */
+      HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+    }
+    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+    else
+    {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Tx Rx Complete Callback */
+      husart->TxRxCpltCallback(husart);
+#else
+      /* Call legacy weak Tx Rx Complete Callback */
+      HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+    }
+    husart->State = HAL_USART_STATE_READY;
+  }
+  /* DMA circular mode */
+  else
+  {
+    if (husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx Complete Callback */
+      husart->RxCpltCallback(husart);
+#else
+      /* Call legacy weak Rx Complete Callback */
+      HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+    }
+    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+    else
+    {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Tx Rx Complete Callback */
+      husart->TxRxCpltCallback(husart);
+#else
+      /* Call legacy weak Tx Rx Complete Callback */
+      HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief DMA USART receive process half complete callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Rx Half Complete Callback */
+  husart->RxHalfCpltCallback(husart);
+#else
+  /* Call legacy weak Rx Half Complete Callback */
+  HAL_USART_RxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA USART communication error callback.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+  husart->RxXferCount = 0U;
+  husart->TxXferCount = 0U;
+  USART_EndTransfer(husart);
+
+  husart->ErrorCode |= HAL_USART_ERROR_DMA;
+  husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Error Callback */
+  husart->ErrorCallback(husart);
+#else
+  /* Call legacy weak Error Callback */
+  HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+  husart->RxXferCount = 0U;
+  husart->TxXferCount = 0U;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Error Callback */
+  husart->ErrorCallback(husart);
+#else
+  /* Call legacy weak Error Callback */
+  HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA USART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+  husart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (husart->hdmarx != NULL)
+  {
+    if (husart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0U;
+  husart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Complete Callback */
+  husart->AbortCpltCallback(husart);
+#else
+  /* Call legacy weak Abort Complete Callback */
+  HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+}
+
+
+/**
+  * @brief  DMA USART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
+  husart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (husart->hdmatx != NULL)
+  {
+    if (husart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0U;
+  husart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Complete Callback */
+  husart->AbortCpltCallback(husart);
+#else
+  /* Call legacy weak Abort Complete Callback */
+  HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+  * @brief  Handle USART Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
+  * @param  husart USART handle.
+  * @param  Flag Specifies the USART flag to check.
+  * @param  Status the actual Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+                                                      uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        husart->State = HAL_USART_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(husart);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Configure the USART peripheral.
+  * @param husart USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpreg;
+  uint64_t clocksource;
+  HAL_StatusTypeDef ret                = HAL_OK;
+  uint16_t brrtemp;
+  uint32_t usartdiv;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+  assert_param(IS_USART_PARITY(husart->Init.Parity));
+  assert_param(IS_USART_MODE(husart->Init.Mode));
+  assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE and RE bits and configure
+  *  the USART Word Length, Parity and Mode:
+  *  set the M bits according to husart->Init.WordLength value
+  *  set PCE and PS bits according to husart->Init.Parity value
+  *  set TE and RE bits according to husart->Init.Mode value
+  *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+  tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+  MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*---------------------------- USART CR2 Configuration ---------------------*/
+  /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
+   * set CPOL bit according to husart->Init.CLKPolarity value
+   * set CPHA bit according to husart->Init.CLKPhase value
+   * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only)
+   * set STOP[13:12] bits according to husart->Init.StopBits value */
+  tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+  tmpreg |= (uint32_t)husart->Init.CLKLastBit;
+  tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+  tmpreg |= (uint32_t)husart->Init.StopBits;
+  MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+   * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */
+  MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */
+  USART_GETCLOCKSOURCE(husart, clocksource);
+
+  pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource);
+
+  usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+
+  /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
+  if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
+  {
+    brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    husart->Instance->BRR = brrtemp;
+  }
+  else
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  husart->NbTxDataToProcess = 1U;
+  husart->NbRxDataToProcess = 1U;
+
+  /* Clear ISR function pointers */
+  husart->RxISR   = NULL;
+  husart->TxISR   = NULL;
+
+  return ret;
+}
+
+/**
+  * @brief Check the USART Idle State.
+  * @param husart USART handle.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+  uint32_t tickstart;
+
+  /* Initialize the USART ErrorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the USART state*/
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Simplex send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Transmit_IT().
+  * @note   The USART errors are not managed to avoid the overrun error.
+  * @note   ISR function executed when FIFO mode is disabled and when the
+  *         data word length is less than 9 bits long.
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+
+  /* Check that a Tx process is ongoing */
+  if ((state == HAL_USART_STATE_BUSY_TX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    if (husart->TxXferCount == 0U)
+    {
+      /* Disable the USART Transmit data register empty interrupt */
+      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+    }
+    else
+    {
+      husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+      husart->pTxBuffPtr++;
+      husart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief  Simplex send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Transmit_IT().
+  * @note   The USART errors are not managed to avoid the overrun error.
+  * @note   ISR function executed when FIFO mode is disabled and when the
+  *         data word length is 9 bits long.
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+  const uint16_t *tmp;
+
+  if ((state == HAL_USART_STATE_BUSY_TX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    if (husart->TxXferCount == 0U)
+    {
+      /* Disable the USART Transmit data register empty interrupt */
+      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+    }
+    else
+    {
+      tmp = (const uint16_t *) husart->pTxBuffPtr;
+      husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+      husart->pTxBuffPtr += 2U;
+      husart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief  Simplex send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Transmit_IT().
+  * @note   The USART errors are not managed to avoid the overrun error.
+  * @note   ISR function executed when FIFO mode is enabled and when the
+  *         data word length is less than 9 bits long.
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if ((state == HAL_USART_STATE_BUSY_TX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (husart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
+
+        /* Enable the USART Transmit Complete Interrupt */
+        __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+        break; /* force exit loop */
+      }
+      else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
+      {
+        husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+        husart->pTxBuffPtr++;
+        husart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Simplex send an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Transmit_IT().
+  * @note   The USART errors are not managed to avoid the overrun error.
+  * @note   ISR function executed when FIFO mode is enabled and when the
+  *         data word length is 9 bits long.
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+  const uint16_t *tmp;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if ((state == HAL_USART_STATE_BUSY_TX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (husart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT);
+
+        /* Enable the USART Transmit Complete Interrupt */
+        __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+        break; /* force exit loop */
+      }
+      else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
+      {
+        tmp = (const uint16_t *) husart->pTxBuffPtr;
+        husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+        husart->pTxBuffPtr += 2U;
+        husart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wraps up transmission in non-blocking mode.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+  /* Disable the USART Transmit Complete Interrupt */
+  __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+  __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+  /* Clear TxISR function pointer */
+  husart->TxISR = NULL;
+
+  if (husart->State == HAL_USART_STATE_BUSY_TX)
+  {
+    /* Clear overrun flag and discard the received data */
+    __HAL_USART_CLEAR_OREFLAG(husart);
+    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
+    /* Tx process is completed, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Complete Callback */
+    husart->TxCpltCallback(husart);
+#else
+    /* Call legacy weak Tx Complete Callback */
+    HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+  }
+  else if (husart->RxXferCount == 0U)
+  {
+    /* TxRx process is completed, restore husart->State to Ready */
+    husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Rx Complete Callback */
+    husart->TxRxCpltCallback(husart);
+#else
+    /* Call legacy weak Tx Rx Complete Callback */
+    HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+
+/**
+  * @brief  Simplex receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Receive_IT().
+  * @note   ISR function executed when FIFO mode is disabled and when the
+  *         data word length is less than 9 bits long.
+  * @param  husart USART handle
+  * @retval None
+  */
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+  uint16_t txdatacount;
+  uint16_t uhMask = husart->Mask;
+  uint32_t txftie;
+
+  if ((state == HAL_USART_STATE_BUSY_RX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+    husart->pRxBuffPtr++;
+    husart->RxXferCount--;
+
+    if (husart->RxXferCount == 0U)
+    {
+      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Clear RxISR function pointer */
+      husart->RxISR = NULL;
+
+      /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+      txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+      txdatacount = husart->TxXferCount;
+
+      if (state == HAL_USART_STATE_BUSY_RX)
+      {
+        /* Clear SPI slave underrun flag and discard transmit data */
+        if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+        {
+          __HAL_USART_CLEAR_UDRFLAG(husart);
+          __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+        }
+
+        /* Rx process is completed, restore husart->State to Ready */
+        husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+        /* Call registered Rx Complete Callback */
+        husart->RxCpltCallback(husart);
+#else
+        /* Call legacy weak Rx Complete Callback */
+        HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+      }
+      else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+               (txftie != USART_CR3_TXFTIE) &&
+               (txdatacount == 0U))
+      {
+        /* TxRx process is completed, restore husart->State to Ready */
+        husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+        /* Call registered Tx Rx Complete Callback */
+        husart->TxRxCpltCallback(husart);
+#else
+        /* Call legacy weak Tx Rx Complete Callback */
+        HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+    else if ((state == HAL_USART_STATE_BUSY_RX) &&
+             (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+    {
+      /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+}
+
+/**
+  * @brief  Simplex receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Receive_IT().
+  * @note   ISR function executed when FIFO mode is disabled and when the
+  *         data word length is 9 bits long.
+  * @param  husart USART handle
+  * @retval None
+  */
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
+{
+  const HAL_USART_StateTypeDef state = husart->State;
+  uint16_t txdatacount;
+  uint16_t *tmp;
+  uint16_t uhMask = husart->Mask;
+  uint32_t txftie;
+
+  if ((state == HAL_USART_STATE_BUSY_RX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    tmp = (uint16_t *) husart->pRxBuffPtr;
+    *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+    husart->pRxBuffPtr += 2U;
+    husart->RxXferCount--;
+
+    if (husart->RxXferCount == 0U)
+    {
+      /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+      /* Clear RxISR function pointer */
+      husart->RxISR = NULL;
+
+      /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+      txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+      txdatacount = husart->TxXferCount;
+
+      if (state == HAL_USART_STATE_BUSY_RX)
+      {
+        /* Clear SPI slave underrun flag and discard transmit data */
+        if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+        {
+          __HAL_USART_CLEAR_UDRFLAG(husart);
+          __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+        }
+
+        /* Rx process is completed, restore husart->State to Ready */
+        husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+        /* Call registered Rx Complete Callback */
+        husart->RxCpltCallback(husart);
+#else
+        /* Call legacy weak Rx Complete Callback */
+        HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+      }
+      else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+               (txftie != USART_CR3_TXFTIE) &&
+               (txdatacount == 0U))
+      {
+        /* TxRx process is completed, restore husart->State to Ready */
+        husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+        /* Call registered Tx Rx Complete Callback */
+        husart->TxRxCpltCallback(husart);
+#else
+        /* Call legacy weak Tx Rx Complete Callback */
+        HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+    else if ((state == HAL_USART_STATE_BUSY_RX) &&
+             (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+    {
+      /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+      husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+}
+
+/**
+  * @brief  Simplex receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Receive_IT().
+  * @note   ISR function executed when FIFO mode is enabled and when the
+  *         data word length is less than 9 bits long.
+  * @param  husart USART handle
+  * @retval None
+  */
+static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+  HAL_USART_StateTypeDef state = husart->State;
+  uint16_t txdatacount;
+  uint16_t rxdatacount;
+  uint16_t uhMask = husart->Mask;
+  uint16_t nb_rx_data;
+  uint32_t txftie;
+
+  /* Check that a Rx process is ongoing */
+  if ((state == HAL_USART_STATE_BUSY_RX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+    {
+      if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
+      {
+        *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+        husart->pRxBuffPtr++;
+        husart->RxXferCount--;
+
+        if (husart->RxXferCount == 0U)
+        {
+          /* Disable the USART Parity Error Interrupt */
+          CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+          /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+             and RX FIFO Threshold interrupt */
+          CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+          /* Clear RxISR function pointer */
+          husart->RxISR = NULL;
+
+          /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+          txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+          txdatacount = husart->TxXferCount;
+
+          if (state == HAL_USART_STATE_BUSY_RX)
+          {
+            /* Clear SPI slave underrun flag and discard transmit data */
+            if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+            {
+              __HAL_USART_CLEAR_UDRFLAG(husart);
+              __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+            }
+
+            /* Rx process is completed, restore husart->State to Ready */
+            husart->State = HAL_USART_STATE_READY;
+            state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+            /* Call registered Rx Complete Callback */
+            husart->RxCpltCallback(husart);
+#else
+            /* Call legacy weak Rx Complete Callback */
+            HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+          }
+          else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+                   (txftie != USART_CR3_TXFTIE) &&
+                   (txdatacount == 0U))
+          {
+            /* TxRx process is completed, restore husart->State to Ready */
+            husart->State = HAL_USART_STATE_READY;
+            state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+            /* Call registered Tx Rx Complete Callback */
+            husart->TxRxCpltCallback(husart);
+#else
+            /* Call legacy weak Tx Rx Complete Callback */
+            HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        else if ((state == HAL_USART_STATE_BUSY_RX) &&
+                 (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+        {
+          /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+          husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+        }
+        else
+        {
+          /* Nothing to do */
+        }
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = husart->RxXferCount;
+    if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
+    {
+      /* Disable the USART RXFT interrupt*/
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      husart->RxISR = USART_RxISR_8BIT;
+
+      /* Enable the USART Data Register Not Empty interrupt */
+      SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+      if ((husart->TxXferCount == 0U) &&
+          (state == HAL_USART_STATE_BUSY_TX_RX) &&
+          (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+      {
+        /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+        husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief  Simplex receive an amount of data in non-blocking mode.
+  * @note   Function called under interruption only, once
+  *         interruptions have been enabled by HAL_USART_Receive_IT().
+  * @note   ISR function executed when FIFO mode is enabled and when the
+  *         data word length is 9 bits long.
+  * @param  husart USART handle
+  * @retval None
+  */
+static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
+{
+  HAL_USART_StateTypeDef state = husart->State;
+  uint16_t txdatacount;
+  uint16_t rxdatacount;
+  uint16_t *tmp;
+  uint16_t uhMask = husart->Mask;
+  uint16_t nb_rx_data;
+  uint32_t txftie;
+
+  /* Check that a Tx process is ongoing */
+  if ((state == HAL_USART_STATE_BUSY_RX) ||
+      (state == HAL_USART_STATE_BUSY_TX_RX))
+  {
+    for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+    {
+      if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET)
+      {
+        tmp = (uint16_t *) husart->pRxBuffPtr;
+        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+        husart->pRxBuffPtr += 2U;
+        husart->RxXferCount--;
+
+        if (husart->RxXferCount == 0U)
+        {
+          /* Disable the USART Parity Error Interrupt */
+          CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+          /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+             and RX FIFO Threshold interrupt */
+          CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+          /* Clear RxISR function pointer */
+          husart->RxISR = NULL;
+
+          /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */
+          txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE);
+          txdatacount = husart->TxXferCount;
+
+          if (state == HAL_USART_STATE_BUSY_RX)
+          {
+            /* Clear SPI slave underrun flag and discard transmit data */
+            if (husart->SlaveMode == USART_SLAVEMODE_ENABLE)
+            {
+              __HAL_USART_CLEAR_UDRFLAG(husart);
+              __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+            }
+
+            /* Rx process is completed, restore husart->State to Ready */
+            husart->State = HAL_USART_STATE_READY;
+            state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+            /* Call registered Rx Complete Callback */
+            husart->RxCpltCallback(husart);
+#else
+            /* Call legacy weak Rx Complete Callback */
+            HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+          }
+          else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+                   (txftie != USART_CR3_TXFTIE) &&
+                   (txdatacount == 0U))
+          {
+            /* TxRx process is completed, restore husart->State to Ready */
+            husart->State = HAL_USART_STATE_READY;
+            state = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+            /* Call registered Tx Rx Complete Callback */
+            husart->TxRxCpltCallback(husart);
+#else
+            /* Call legacy weak Tx Rx Complete Callback */
+            HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+          }
+          else
+          {
+            /* Nothing to do */
+          }
+        }
+        else if ((state == HAL_USART_STATE_BUSY_RX) &&
+                 (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+        {
+          /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+          husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+        }
+        else
+        {
+          /* Nothing to do */
+        }
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = husart->RxXferCount;
+    if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess))
+    {
+      /* Disable the USART RXFT interrupt*/
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      husart->RxISR = USART_RxISR_16BIT;
+
+      /* Enable the USART Data Register Not Empty interrupt */
+      SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+
+      if ((husart->TxXferCount == 0U) &&
+          (state == HAL_USART_STATE_BUSY_TX_RX) &&
+          (husart->SlaveMode == USART_SLAVEMODE_DISABLE))
+      {
+        /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+        husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_usart_ex.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_usart_ex.c
new file mode 100644
index 000000000..41f58b365
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_usart_ex.c
@@ -0,0 +1,541 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_usart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended USART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### USART peripheral extended features  #####
+  ==============================================================================
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+    (#) Slave mode enabling/disabling and NSS pin configuration.
+
+        -@- When USART operates in Slave mode, Slave mode must be enabled prior
+            starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup USARTEx USARTEx
+  * @brief USART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
+  * @{
+  */
+/* USART RX FIFO depth */
+#define RX_FIFO_DEPTH 16U
+
+/* USART TX FIFO depth */
+#define TX_FIFO_DEPTH 16U
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup USARTEx_Private_Functions USARTEx Private Functions
+  * @{
+  */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USARTEx_Exported_Functions  USARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
+  * @brief Extended USART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of FIFO mode related callback functions.
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_USARTEx_RxFifoFullCallback()
+        (+) HAL_USARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  USART RX Fifo full callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  USART TX Fifo empty callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
+     (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
+     (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
+     (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the SPI slave mode.
+  * @note When the USART operates in SPI slave mode, it handles data flow using
+  *       the serial interface clock derived from the external SCLK signal
+  *       provided by the external master SPI device.
+  * @note In SPI slave mode, the USART must be enabled before starting the master
+  *       communications (or between frames while the clock is stable). Otherwise,
+  *       if the USART slave is enabled while the master is in the middle of a
+  *       frame, it will become desynchronized with the master.
+  * @note The data register of the slave needs to be ready before the first edge
+  *       of the communication clock or before the end of the ongoing communication,
+  *       otherwise the SPI slave will transmit zeros.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* In SPI slave mode mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bit in the USART_CR2 register
+  - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* Enable SPI slave mode */
+  SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Enable USART */
+  __HAL_USART_ENABLE(husart);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the SPI slave mode.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Disable SPI slave mode */
+  CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->SlaveMode = USART_SLAVEMODE_DISABLE;
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Slave Select input pin (NSS).
+  * @note Software NSS management: SPI slave will always be selected and NSS
+  *       input pin will be ignored.
+  * @note Hardware NSS management: the SPI slave selection depends on NSS
+  *       input pin. The slave is selected when NSS is low and deselected when
+  *       NSS is high.
+  * @param husart      USART handle.
+  * @param NSSConfig   NSS configuration.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_NSS_HARD
+  *            @arg @ref USART_NSS_SOFT
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+  assert_param(IS_USART_NSS(NSSConfig));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Program DIS_NSS bit in the USART_CR2 register */
+  MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  husart->FifoMode = USART_FIFOMODE_ENABLE;
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  USARTEx_SetNbDataToProcess(husart);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Disable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  husart->FifoMode = USART_FIFOMODE_DISABLE;
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param husart      USART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref USART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref USART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref USART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref USART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref USART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+  assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  USARTEx_SetNbDataToProcess(husart);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param husart      USART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref USART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref USART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref USART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref USART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref USART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+  assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  USARTEx_SetNbDataToProcess(husart);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup USARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the USART configuration registers.
+  * @param husart USART handle.
+  * @retval None
+  */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+  static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (husart->FifoMode == USART_FIFOMODE_DISABLE)
+  {
+    husart->NbTxDataToProcess = 1U;
+    husart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+                                            USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+    tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+                                            USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+    husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                                (uint16_t)denominator[tx_fifo_threshold];
+    husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                                (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_wwdg.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_wwdg.c
new file mode 100644
index 000000000..db0482d6f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_wwdg.c
@@ -0,0 +1,420 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_wwdg.c
+  * @author  MCD Application Team
+  * @brief   WWDG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Window Watchdog (WWDG) peripheral:
+  *           + Initialization and Configuration functions
+  *           + IO operation functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### WWDG Specific features #####
+  ==============================================================================
+  [..]
+    Once enabled the WWDG generates a system reset on expiry of a programmed
+    time period, unless the program refreshes the counter (T[6;0] downcounter)
+    before reaching 0x3F value (i.e. a reset is generated when the counter
+    value rolls down from 0x40 to 0x3F).
+
+    (+) An MCU reset is also generated if the counter value is refreshed
+        before the counter has reached the refresh window value. This
+        implies that the counter must be refreshed in a limited window.
+    (+) Once enabled the WWDG cannot be disabled except by a system reset.
+    (+) If required by application, an Early Wakeup Interrupt can be triggered
+        in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+        (EWI) can be used if specific safety operations or data logging must
+        be performed before the actual reset is generated. When the downcounter
+        reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+        line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+        disabled except by a system reset.
+    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
+        reset occurs.
+    (+) The WWDG counter input clock is derived from the APB clock divided
+        by a programmable prescaler.
+    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+        where T[5;0] are the lowest 6 bits of Counter.
+    (+) WWDG Counter refresh is allowed between the following limits :
+        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+    (+) Typical values:
+        (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
+             max timeout before reset: approximately 64us
+        (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler
+             dividing by 128:
+             max timeout before reset: approximately 524.28ms
+
+                     ##### How to use this driver #####
+  ==============================================================================
+
+    *** Common driver usage ***
+    ===========================
+
+  [..]
+    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+    (+) Configure the WWDG prescaler, refresh window value, counter value and early
+        interrupt status using HAL_WWDG_Init() function. This will automatically
+        enable WWDG and start its downcounter. Time reference can be taken from
+        function exit. Care must be taken to provide a counter value
+        greater than 0x40 to prevent generation of immediate reset.
+    (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+        generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+        triggered by the interrupt service routine, flag will be automatically
+        cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+        can add his own code by customization of callback HAL_WWDG_WakeupCallback.
+    (+) Then the application program must refresh the WWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_WWDG_Refresh() function. This operation must occur only when
+        the counter is lower than the refresh window value already programmed.
+
+    *** Callback registration ***
+    =============================
+
+  [..]
+    The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+    the user to configure dynamically the driver callbacks. Use Functions
+    HAL_WWDG_RegisterCallback() to register a user callback.
+
+    (+) Function HAL_WWDG_RegisterCallback() allows to register following
+        callbacks:
+        (++) EwiCallback : callback for Early WakeUp Interrupt.
+        (++) MspInitCallback : WWDG MspInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
+    the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
+    takes as parameters the HAL peripheral handle and the Callback ID.
+    This function allows to reset following callbacks:
+        (++) EwiCallback : callback for  Early WakeUp Interrupt.
+        (++) MspInitCallback : WWDG MspInit.
+
+    [..]
+    When calling HAL_WWDG_Init function, callbacks are reset to the
+    corresponding legacy weak (surcharged) functions:
+    HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+    not been registered before.
+
+    [..]
+    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
+    *** WWDG HAL driver macros list ***
+    ===================================
+    [..]
+      Below the list of available macros in WWDG HAL driver.
+      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+  * @brief WWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Initialize and start the WWDG according to the specified parameters
+          in the WWDG_InitTypeDef of associated handle.
+      (+) Initialize the WWDG MSP.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the WWDG according to the specified.
+  *         parameters in the WWDG_InitTypeDef of  associated handle.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check the WWDG handle allocation */
+  if (hwwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+  /* Reset Callback pointers */
+  if (hwwdg->EwiCallback == NULL)
+  {
+    hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+  }
+
+  if (hwwdg->MspInitCallback == NULL)
+  {
+    hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+  }
+
+  /* Init the low level hardware */
+  hwwdg->MspInitCallback(hwwdg);
+#else
+  /* Init the low level hardware */
+  HAL_WWDG_MspInit(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+  /* Set WWDG Counter */
+  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+  /* Set WWDG Prescaler and Window */
+  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the WWDG MSP.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @note   When rewriting this function in user file, mechanism may be added
+  *         to avoid multiple initialize when HAL_WWDG_Init function is called
+  *         again to change parameters.
+  * @retval None
+  */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_MspInit could be implemented in the user file
+   */
+}
+
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User WWDG Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param  hwwdg WWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+                                            pWWDG_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    switch (CallbackID)
+    {
+      case HAL_WWDG_EWI_CB_ID:
+        hwwdg->EwiCallback = pCallback;
+        break;
+
+      case HAL_WWDG_MSPINIT_CB_ID:
+        hwwdg->MspInitCallback = pCallback;
+        break;
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Unregister a WWDG Callback
+  *         WWDG Callback is redirected to the weak (surcharged) predefined callback
+  * @param  hwwdg WWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case HAL_WWDG_EWI_CB_ID:
+      hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+      break;
+
+    case HAL_WWDG_MSPINIT_CB_ID:
+      hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+  *  @brief    IO operation functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Refresh the WWDG.
+    (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Refresh the WWDG.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Write to WWDG CR the WWDG Counter value to refresh with */
+  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle WWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+  *         or data logging must be performed before the actual reset is generated.
+  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+  *         EWIMode set to WWDG_EWI_ENABLE.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is
+  *         generated and the corresponding Interrupt Service Routine (ISR) can
+  *         be used to trigger specific actions (such as communications or data
+  *         logging), before resetting the device.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check if Early Wakeup Interrupt is enable */
+  if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+  {
+    /* Check if WWDG Early Wakeup Interrupt occurred */
+    if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+    {
+      /* Clear the WWDG Early Wakeup flag */
+      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+      /* Early Wakeup registered callback */
+      hwwdg->EwiCallback(hwwdg);
+#else
+      /* Early Wakeup callback */
+      HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+
+/**
+  * @brief  WWDG Early Wakeup callback.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_xspi.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_xspi.c
new file mode 100644
index 000000000..a7fad61da
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_hal_xspi.c
@@ -0,0 +1,3493 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_hal_xspi.c
+  * @author  MCD Application Team
+  * @brief   XSPI HAL module driver.
+             This file provides firmware functions to manage the following
+             functionalities of the XSPI interface (XSPI).
+              + Initialization and de-initialization functions
+              + Hyperbus configuration
+              + Indirect functional mode management
+              + Memory-mapped functional mode management
+              + Auto-polling functional mode management
+              + Interrupts and flags management
+              + DMA channel configuration for indirect functional mode
+              + Errors management and abort functionality
+              + IO manager configuration
+              + HIGH-SPEED INTERFACE configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    *** Initialization ***
+    ======================
+    [..]
+     As prerequisite, fill in the HAL_XSPI_MspInit() :
+     (+) Enable XSPI clocks interface with __HAL_RCC_XSPI_CLK_ENABLE().
+     (+) Reset XSPI Peripheral with __HAL_RCC_XSPI_FORCE_RESET() and __HAL_RCC_XSPI_RELEASE_RESET().
+     (+) Enable the clocks for the XSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+     (+) Configure these XSPI pins in alternate mode using HAL_GPIO_Init().
+     (+) If interrupt or DMA mode is used, enable and configure XSPI global
+         interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+     (+) If DMA mode is used, enable the clocks for the XSPI DMA channel
+         with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+         link it with XSPI handle using __HAL_LINKDMA(), enable and configure
+         DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+    [..]
+     Configure the fifo threshold, the memory mode, the memory type, the
+     device size, the CS high time, the free running clock, the clock mode,
+     the wrap size, the clock prescaler, the sample shifting, the hold delay
+     and the CS boundary using the HAL_XSPI_Init() function.
+    [..]
+     When using Hyperbus, configure the RW recovery time, the access time,
+     the write latency and the latency mode using the HAL_XSPI_HyperbusCfg()
+     function.
+
+    *** Indirect functional mode ***
+    ================================
+    [..]
+     In regular mode, configure the command sequence using the HAL_XSPI_Command()
+     or HAL_XSPI_Command_IT() functions :
+     (+) Instruction phase : the mode used and if present the size, the instruction
+         opcode and the DTR mode.
+     (+) Address phase : the mode used and if present the size, the address
+         value and the DTR mode.
+     (+) Alternate-bytes phase : the mode used and if present the size, the
+         alternate bytes values and the DTR mode.
+     (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+     (+) Data phase : the mode used and if present the number of bytes and the DTR mode.
+     (+) Data strobe (DQS) mode : the activation (or not) of this mode
+     (+) IO selection : to access external memory.
+     (+) Operation type : always common configuration.
+    [..]
+     In Hyperbus mode, configure the command sequence using the HAL_XSPI_HyperbusCmd()
+     function :
+     (+) Address space : indicate if the access will be done in register or memory
+     (+) Address size
+     (+) Number of data
+     (+) Data strobe (DQS) mode : the activation (or not) of this mode
+    [..]
+     If no data is required for the command (only for regular mode, not for
+     Hyperbus mode), it is sent directly to the memory :
+     (+) In polling mode, the output of the function is done when the transfer is complete.
+     (+) In interrupt mode, HAL_XSPI_CmdCpltCallback() will be called when the transfer is complete.
+    [..]
+     For the indirect write mode, use HAL_XSPI_Transmit(), HAL_XSPI_Transmit_DMA() or
+     HAL_XSPI_Transmit_IT() after the command configuration :
+     (+) In polling mode, the output of the function is done when the transfer is complete.
+     (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold
+         is reached and HAL_XSPI_TxCpltCallback() will be called when the transfer is complete.
+     (+) In DMA mode, HAL_XSPI_TxHalfCpltCallback() will be called at the half transfer and
+         HAL_XSPI_TxCpltCallback() will be called when the transfer is complete.
+    [..]
+     For the indirect read mode, use HAL_XSPI_Receive(), HAL_XSPI_Receive_DMA() or
+     HAL_XSPI_Receive_IT() after the command configuration :
+     (+) In polling mode, the output of the function is done when the transfer is complete.
+     (+) In interrupt mode, HAL_XSPI_FifoThresholdCallback() will be called when the fifo threshold
+         is reached and HAL_XSPI_RxCpltCallback() will be called when the transfer is complete.
+     (+) In DMA mode, HAL_XSPI_RxHalfCpltCallback() will be called at the half transfer and
+         HAL_XSPI_RxCpltCallback() will be called when the transfer is complete.
+
+    *** Auto-polling functional mode ***
+    ====================================
+    [..]
+     Configure the command sequence by the same way than the indirect mode
+    [..]
+     Configure the auto-polling functional mode using the HAL_XSPI_AutoPolling()
+     or HAL_XSPI_AutoPolling_IT() functions :
+     (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+         the polling interval and the automatic stop activation.
+    [..]
+     After the configuration :
+     (+) In polling mode, the output of the function is done when the status match is reached. The
+         automatic stop is activated to avoid an infinite loop.
+     (+) In interrupt mode, HAL_XSPI_StatusMatchCallback() will be called each time the status match is reached.
+
+    *** Memory-mapped functional mode ***
+    =====================================
+    [..]
+     Configure the command sequence by the same way than the indirect mode except
+     for the operation type in regular mode :
+     (+) Operation type equals to read configuration : the command configuration
+         applies to read access in memory-mapped mode
+     (+) Operation type equals to write configuration : the command configuration
+         applies to write access in memory-mapped mode
+     (+) Both read and write configuration should be performed before activating
+         memory-mapped mode
+    [..]
+     Configure the memory-mapped functional mode using the HAL_XSPI_MemoryMapped()
+     functions :
+     (+) The timeout activation and the timeout period.
+    [..]
+     After the configuration, the XSPI will be used as soon as an access on the AHB is done on
+     the address range. HAL_XSPI_TimeOutCallback() will be called when the timeout expires.
+
+    *** Errors management and abort functionality ***
+    =================================================
+    [..]
+     HAL_XSPI_GetError() function gives the error raised during the last operation.
+    [..]
+     HAL_XSPI_Abort() and HAL_XSPI_AbortIT() functions aborts any on-going operation and
+     flushes the fifo :
+     (+) In polling mode, the output of the function is done when the transfer
+         complete bit is set and the busy bit cleared.
+     (+) In interrupt mode, HAL_XSPI_AbortCpltCallback() will be called when
+         the transfer complete bit is set.
+
+    *** Control functions ***
+    =========================
+    [..]
+     HAL_XSPI_GetState() function gives the current state of the HAL XSPI driver.
+    [..]
+     HAL_XSPI_SetTimeout() function configures the timeout value used in the driver.
+    [..]
+     HAL_XSPI_SetFifoThreshold() function configures the threshold on the Fifo of the XSPI Peripheral.
+    [..]
+     HAL_XSPI_SetMemoryType() function configures the type of the external memory.
+    [..]
+     HAL_XSPI_SetDeviceSize() function configures the size of the external memory.
+    [..]
+     HAL_XSPI_SetClockPrescaler() function configures the clock prescaler of the XSPI Peripheral.
+    [..]
+     HAL_XSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+
+    *** IO manager configuration functions ***
+    ==========================================
+    [..]
+     HAL_XSPIM_Config() function configures the IO manager for the XSPI instance.
+
+    *** High-speed interface and calibration functions ***
+    ==========================================
+    [..]
+     The  purpose of High-speed interface is primary to shift data or data strobe by one quarter of octal
+     bus clock period, with a correct timing accuracy. DLL must be calibrated versus this clock period.
+     The calibration process is automatically enabled when one of the three conditions below is met:
+     (+) The XSPI exits Reset state.
+     (+) The Prescaler is set.
+     (+) The configuration of communication is set.
+    [..]
+     HAL_XSPI_GetDelayValue() function Get the delay values of the high-speed interface DLLs..
+    [..]
+     HAL_XSPI_SetDelayValue() function Set the delay values of the high-speed interface DLLs..
+
+    *** Callback registration ***
+    =============================================
+    [..]
+     The compilation define  USE_HAL_XSPI_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+
+    [..]
+     Use function HAL_XSPI_RegisterCallback() to register a user callback,
+     it allows to register following callbacks:
+     (+) ErrorCallback : callback when error occurs.
+     (+) AbortCpltCallback : callback when abort is completed.
+     (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+     (+) CmdCpltCallback : callback when a command without data is completed.
+     (+) RxCpltCallback : callback when a reception transfer is completed.
+     (+) TxCpltCallback : callback when a transmission transfer is completed.
+     (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+     (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+     (+) StatusMatchCallback : callback when a status match occurs.
+     (+) TimeOutCallback : callback when the timeout perioed expires.
+     (+) MspInitCallback    : XSPI MspInit.
+     (+) MspDeInitCallback  : XSPI MspDeInit.
+    [..]
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+
+    [..]
+     Use function HAL_XSPI_UnRegisterCallback() to reset a callback to the default
+     weak (overridden) function. It allows to reset following callbacks:
+     (+) ErrorCallback : callback when error occurs.
+     (+) AbortCpltCallback : callback when abort is completed.
+     (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+     (+) CmdCpltCallback : callback when a command without data is completed.
+     (+) RxCpltCallback : callback when a reception transfer is completed.
+     (+) TxCpltCallback : callback when a transmission transfer is completed.
+     (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+     (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+     (+) StatusMatchCallback : callback when a status match occurs.
+     (+) TimeOutCallback : callback when the timeout perioed expires.
+     (+) MspInitCallback    : XSPI MspInit.
+     (+) MspDeInitCallback  : XSPI MspDeInit.
+    [..]
+     This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+    [..]
+     By default, after the HAL_XSPI_Init() and if the state is HAL_XSPI_STATE_RESET
+     all callbacks are reset to the corresponding legacy weak (overridden) functions.
+     Exception done for MspInit and MspDeInit callbacks that are respectively
+     reset to the legacy weak (overridden) functions in the HAL_XSPI_Init()
+     and HAL_XSPI_DeInit() only when these callbacks are null (not registered beforehand).
+     If not, MspInit or MspDeInit are not null, the HAL_XSPI_Init() and HAL_XSPI_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    [..]
+     Callbacks can be registered/unregistered in READY state only.
+     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+     during the Init/DeInit.
+     In that case first register the MspInit/MspDeInit user callbacks
+     using HAL_XSPI_RegisterCallback() before calling HAL_XSPI_DeInit()
+     or HAL_XSPI_Init() function.
+
+    [..]
+     When The compilation define USE_HAL_XSPI_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registering feature is not available
+     and weak (overridden) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+#include "stm32n6xx_hal_rcc.h"
+
+#if defined(XSPI) || defined(XSPI1) || defined(XSPI2) || defined(XSPI3)
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup XSPI XSPI
+  * @brief XSPI HAL module driver
+  * @{
+  */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+
+/**
+  @cond 0
+  */
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+#define XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000)         /*!< Indirect write mode    */
+#define XSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)XSPI_CR_FMODE_0)    /*!< Indirect read mode     */
+#define XSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)XSPI_CR_FMODE_1)    /*!< Automatic polling mode */
+#define XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)XSPI_CR_FMODE)      /*!< Memory-mapped mode     */
+
+#define XSPI_CFG_STATE_MASK  0x00000004U
+#define XSPI_BUSY_STATE_MASK 0x00000008U
+
+#define XSPI_NB_INSTANCE   3U
+#define XSPI_IOM_NB_PORTS  2U
+#define XSPI_IOM_PORT_MASK 0x1U
+
+/* Private macro -------------------------------------------------------------*/
+#define IS_XSPI_FUNCTIONAL_MODE(MODE) (((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
+                                       ((MODE) == XSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
+                                       ((MODE) == XSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
+                                       ((MODE) == XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+static void              XSPI_DMACplt(DMA_HandleTypeDef *hdma);
+static void              XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma);
+static void              XSPI_DMAError(DMA_HandleTypeDef *hdma);
+static void              XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, FlagStatus State,
+                                                        uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd);
+static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg);
+/**
+  @endcond
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup XSPI_Exported_Functions XSPI Exported Functions
+  * @{
+  */
+
+/** @defgroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Initialize the XSPI.
+      (+) De-initialize the XSPI.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the XSPI mode according to the specified parameters
+  *         in the XSPI_InitTypeDef and initialize the associated handle.
+  * @param  hxspi : XSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the XSPI handle allocation */
+  if (hxspi == NULL)
+  {
+    status = HAL_ERROR;
+    /* No error code can be set set as the handler is null */
+  }
+  else
+  {
+    /* Check the parameters of the initialization structure */
+    assert_param(IS_XSPI_MEMORY_MODE(hxspi->Init.MemoryMode));
+    assert_param(IS_XSPI_MEMORY_TYPE(hxspi->Init.MemoryType));
+    assert_param(IS_XSPI_MEMORY_SIZE(hxspi->Init.MemorySize));
+    assert_param(IS_XSPI_CS_HIGH_TIME_CYCLE(hxspi->Init.ChipSelectHighTimeCycle));
+    assert_param(IS_XSPI_FREE_RUN_CLK(hxspi->Init.FreeRunningClock));
+    assert_param(IS_XSPI_CLOCK_MODE(hxspi->Init.ClockMode));
+    assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize));
+    assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler));
+    assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting));
+    assert_param(IS_XSPI_DHQC(hxspi->Init.DelayHoldQuarterCycle));
+    assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary));
+    assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte));
+    assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran));
+    assert_param(IS_XSPI_CSSEL(hxspi->Init.MemorySelect));
+    assert_param(IS_XSPI_EXTENDMEM(hxspi->Init.MemoryExtended));
+    /* Initialize error code */
+    hxspi->ErrorCode = HAL_XSPI_ERROR_NONE;
+
+    /* Check if the state is the reset state */
+    if (hxspi->State == HAL_XSPI_STATE_RESET)
+    {
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+      /* Reset Callback pointers in HAL_XSPI_STATE_RESET only */
+      hxspi->ErrorCallback         = HAL_XSPI_ErrorCallback;
+      hxspi->AbortCpltCallback     = HAL_XSPI_AbortCpltCallback;
+      hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback;
+      hxspi->CmdCpltCallback       = HAL_XSPI_CmdCpltCallback;
+      hxspi->RxCpltCallback        = HAL_XSPI_RxCpltCallback;
+      hxspi->TxCpltCallback        = HAL_XSPI_TxCpltCallback;
+      hxspi->RxHalfCpltCallback    = HAL_XSPI_RxHalfCpltCallback;
+      hxspi->TxHalfCpltCallback    = HAL_XSPI_TxHalfCpltCallback;
+      hxspi->StatusMatchCallback   = HAL_XSPI_StatusMatchCallback;
+      hxspi->TimeOutCallback       = HAL_XSPI_TimeOutCallback;
+
+      if (hxspi->MspInitCallback == NULL)
+      {
+        hxspi->MspInitCallback = HAL_XSPI_MspInit;
+      }
+
+      /* Init the low level hardware */
+      hxspi->MspInitCallback(hxspi);
+#else
+      /* Initialization of the low level hardware */
+      HAL_XSPI_MspInit(hxspi);
+#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+
+      /* Configure the default timeout for the XSPI memory access */
+      (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
+
+      /* Configure memory type, device size, chip select high time, free running clock, clock mode */
+      MODIFY_REG(hxspi->Instance->DCR1,
+                 (XSPI_DCR1_MTYP | XSPI_DCR1_DEVSIZE | XSPI_DCR1_CSHT | XSPI_DCR1_FRCK | XSPI_DCR1_CKMODE),
+                 (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) |
+                  ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode));
+
+      /* Configure wrap size */
+      MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize);
+
+      /* Configure chip select boundary */
+      MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_CSBOUND_Pos));
+
+      /* Configure maximum transfer */
+      MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_MAXTRAN, \
+                 (hxspi->Init.MaxTran << XSPI_DCR3_MAXTRAN_Pos));
+
+      /* Configure refresh */
+      hxspi->Instance->DCR4 = hxspi->Init.Refresh;
+
+      /* Configure FIFO threshold */
+      MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos));
+
+      /* Wait till busy flag is reset */
+      status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout);
+
+      if (status == HAL_OK)
+      {
+        /* Configure clock prescaler */
+        MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER,
+                   ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos));
+
+        if (IS_XSPI_ALL_INSTANCE(hxspi->Instance))
+        {
+          /* The configuration of clock prescaler trigger automatically a calibration process.
+          So it is necessary to wait the calibration is complete */
+          status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout);
+          if (status != HAL_OK)
+          {
+            return status;
+          }
+        }
+        /* Configure Dual Memory mode and CS Selection */
+        MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_DMM | XSPI_CR_CSSEL),
+                   (hxspi->Init.MemoryMode | hxspi->Init.MemorySelect));
+
+        /* Configure sample shifting and delay hold quarter cycle */
+        MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC),
+                   (hxspi->Init.SampleShifting | hxspi->Init.DelayHoldQuarterCycle));
+
+        /* Enable XSPI */
+        HAL_XSPI_ENABLE(hxspi);
+
+        /* Enable free running clock if needed : must be done after XSPI enable */
+        if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE)
+        {
+          SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK);
+        }
+
+        if (hxspi->Init.MemoryExtended == HAL_XSPI_CSSEL_HW)
+        {
+          SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_EXTENDMEM);
+        }
+
+        /* Initialize the XSPI state */
+        if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)
+        {
+          hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT;
+        }
+        else
+        {
+          hxspi->State = HAL_XSPI_STATE_READY;
+        }
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Initialize the XSPI MSP.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_XSPI_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  De-Initialize the XSPI peripheral.
+  * @param  hxspi : XSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the XSPI handle allocation */
+  if (hxspi == NULL)
+  {
+    status = HAL_ERROR;
+    /* No error code can be set as the handler is null */
+  }
+  else
+  {
+    /* Disable XSPI */
+    HAL_XSPI_DISABLE(hxspi);
+
+    /* Disable free running clock if needed : must be done after XSPI disable */
+    CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK);
+
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    if (hxspi->MspDeInitCallback == NULL)
+    {
+      hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit;
+    }
+
+    /* De-initialize the low level hardware */
+    hxspi->MspDeInitCallback(hxspi);
+#else
+    /* De-initialize the low-level hardware */
+    HAL_XSPI_MspDeInit(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+
+    /* Reset the driver state */
+    hxspi->State = HAL_XSPI_STATE_RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the XSPI MSP.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_XSPI_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief XSPI Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Handle the interrupts.
+      (+) Handle the command sequence (regular and Hyperbus).
+      (+) Handle the Hyperbus configuration.
+      (+) Transmit data in blocking, interrupt or DMA mode.
+      (+) Receive data in blocking, interrupt or DMA mode.
+      (+) Manage the auto-polling functional mode.
+      (+) Manage the memory-mapped functional mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle XSPI interrupt request.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi)
+{
+  __IO uint32_t *data_reg = &hxspi->Instance->DR;
+  uint32_t flag           = hxspi->Instance->SR;
+  uint32_t itsource       = hxspi->Instance->CR;
+  uint32_t currentstate   = hxspi->State;
+
+  /* XSPI fifo threshold interrupt occurred -------------------------------*/
+  if (((flag & HAL_XSPI_FLAG_FT) != 0U) && ((itsource & HAL_XSPI_IT_FT) != 0U))
+  {
+    if (currentstate == HAL_XSPI_STATE_BUSY_TX)
+    {
+      /* Write a data in the fifo */
+      *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr;
+      hxspi->pBuffPtr++;
+      hxspi->XferCount--;
+    }
+    else if (currentstate == HAL_XSPI_STATE_BUSY_RX)
+    {
+      /* Read a data from the fifo */
+      *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg);
+      hxspi->pBuffPtr++;
+      hxspi->XferCount--;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    if (hxspi->XferCount == 0U)
+    {
+      /* All data have been received or transmitted for the transfer */
+      /* Disable fifo threshold interrupt */
+      HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_FT);
+    }
+
+    /* Fifo threshold callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    hxspi->FifoThresholdCallback(hxspi);
+#else
+    HAL_XSPI_FifoThresholdCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+  }
+  /* XSPI transfer complete interrupt occurred ----------------------------*/
+  else if (((flag & HAL_XSPI_FLAG_TC) != 0U) && ((itsource & HAL_XSPI_IT_TC) != 0U))
+  {
+    if (currentstate == HAL_XSPI_STATE_BUSY_RX)
+    {
+      if ((hxspi->XferCount > 0U) && ((flag & XSPI_SR_FLEVEL) != 0U))
+      {
+        /* Read the last data received in the fifo */
+        *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg);
+        hxspi->pBuffPtr++;
+        hxspi->XferCount--;
+      }
+      else if (hxspi->XferCount == 0U)
+      {
+        /* Clear flag */
+        hxspi->Instance->FCR = HAL_XSPI_FLAG_TC;
+
+        /* Disable the interrupts */
+        HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE);
+
+        hxspi->State = HAL_XSPI_STATE_READY;
+
+        /* RX complete callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->RxCpltCallback(hxspi);
+#else
+        HAL_XSPI_RxCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+    else
+    {
+      /* Clear flag */
+      hxspi->Instance->FCR = HAL_XSPI_FLAG_TC;
+
+      /* Disable the interrupts */
+      HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE);
+
+      hxspi->State = HAL_XSPI_STATE_READY;
+
+      if (currentstate == HAL_XSPI_STATE_BUSY_TX)
+      {
+        /* TX complete callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->TxCpltCallback(hxspi);
+#else
+        HAL_XSPI_TxCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+      else if (currentstate == HAL_XSPI_STATE_BUSY_CMD)
+      {
+        /* Command complete callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->CmdCpltCallback(hxspi);
+#else
+        HAL_XSPI_CmdCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+      else if (currentstate == HAL_XSPI_STATE_ABORT)
+      {
+        if (hxspi->ErrorCode == HAL_XSPI_ERROR_NONE)
+        {
+          /* Abort called by the user */
+          /* Abort complete callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+          hxspi->AbortCpltCallback(hxspi);
+#else
+          HAL_XSPI_AbortCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+        }
+        else
+        {
+          /* Abort due to an error (eg : DMA error) */
+          /* Error callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+          hxspi->ErrorCallback(hxspi);
+#else
+          HAL_XSPI_ErrorCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+  /* XSPI status match interrupt occurred ---------------------------------*/
+  else if (((flag & HAL_XSPI_FLAG_SM) != 0U) && ((itsource & HAL_XSPI_IT_SM) != 0U))
+  {
+    /* Clear flag */
+    hxspi->Instance->FCR = HAL_XSPI_FLAG_SM;
+
+    /* Check if automatic poll mode stop is activated */
+    if ((hxspi->Instance->CR & XSPI_CR_APMS) != 0U)
+    {
+      /* Disable the interrupts */
+      HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE);
+
+      hxspi->State = HAL_XSPI_STATE_READY;
+    }
+
+    /* Status match callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    hxspi->StatusMatchCallback(hxspi);
+#else
+    HAL_XSPI_StatusMatchCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+  }
+  /* XSPI transfer error interrupt occurred -------------------------------*/
+  else if (((flag & HAL_XSPI_FLAG_TE) != 0U) && ((itsource & HAL_XSPI_IT_TE) != 0U))
+  {
+    /* Clear flag */
+    hxspi->Instance->FCR = HAL_XSPI_FLAG_TE;
+
+    /* Disable all interrupts */
+    HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE));
+
+    /* Set error code */
+    hxspi->ErrorCode = HAL_XSPI_ERROR_TRANSFER;
+
+    /* Check if the DMA is enabled */
+    if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer on the XSPI side */
+      CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN);
+
+      /* Disable the DMA transmit on the DMA side */
+      hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK)
+      {
+        hxspi->State = HAL_XSPI_STATE_READY;
+
+        /* Error callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->ErrorCallback(hxspi);
+#else
+        HAL_XSPI_ErrorCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+
+      /* Disable the DMA receive on the DMA side */
+      hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK)
+      {
+        hxspi->State = HAL_XSPI_STATE_READY;
+
+        /* Error callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->ErrorCallback(hxspi);
+#else
+        HAL_XSPI_ErrorCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+    }
+    else
+    {
+      hxspi->State = HAL_XSPI_STATE_READY;
+
+      /* Error callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+      hxspi->ErrorCallback(hxspi);
+#else
+      HAL_XSPI_ErrorCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+    }
+  }
+  /* XSPI timeout interrupt occurred --------------------------------------*/
+  else if (((flag & HAL_XSPI_FLAG_TO) != 0U) && ((itsource & HAL_XSPI_IT_TO) != 0U))
+  {
+    /* Clear flag */
+    hxspi->Instance->FCR = HAL_XSPI_FLAG_TO;
+
+    /* Timeout callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    hxspi->TimeOutCallback(hxspi);
+#else
+    HAL_XSPI_TimeOutCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  Set the command configuration.
+  * @param  hxspi   : XSPI handle
+  * @param  pCmd     : structure that contains the command configuration information
+  * @param  Timeout : Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t state;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters of the command structure */
+  assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType));
+  if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM)
+  {
+    assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect));
+  }
+
+  assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode));
+  if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth));
+    assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode));
+  }
+
+  assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode));
+  if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth));
+    assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode));
+  }
+
+  assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode));
+  if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE)
+  {
+    assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth));
+    assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode));
+  }
+
+  assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode));
+
+  if (pCmd->DataMode != HAL_XSPI_DATA_NONE)
+  {
+    if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG)
+    {
+      assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength));
+    }
+    assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode));
+    assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles));
+  }
+
+  assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode));
+
+  /* Check the state of the driver */
+  state = hxspi->State;
+  if (((state == HAL_XSPI_STATE_READY)         && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) ||
+      ((state == HAL_XSPI_STATE_READ_CMD_CFG)  && ((pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) ||
+                                                   (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG))) ||
+      ((state == HAL_XSPI_STATE_WRITE_CMD_CFG) &&
+       ((pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG)  ||
+        (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG))))
+  {
+    /* Wait till busy flag is reset */
+    status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Initialize error code */
+      hxspi->ErrorCode = HAL_XSPI_ERROR_NONE;
+
+      /* Configure the registers */
+      status = XSPI_ConfigCmd(hxspi, pCmd);
+
+      if (status == HAL_OK)
+      {
+        if (pCmd->DataMode == HAL_XSPI_DATA_NONE)
+        {
+          /* When there is no data phase, the transfer start as soon as the configuration is done
+             so wait until TC flag is set to go back in idle state */
+          status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout);
+
+          HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC);
+        }
+        else
+        {
+          /* Update the state */
+          if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG)
+          {
+            hxspi->State = HAL_XSPI_STATE_CMD_CFG;
+          }
+          else if (pCmd->OperationType == HAL_XSPI_OPTYPE_READ_CFG)
+          {
+            if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG)
+            {
+              hxspi->State = HAL_XSPI_STATE_CMD_CFG;
+            }
+            else
+            {
+              hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG;
+            }
+          }
+          else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG)
+          {
+            if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG)
+            {
+              hxspi->State = HAL_XSPI_STATE_CMD_CFG;
+            }
+            else
+            {
+              hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG;
+            }
+          }
+          else
+          {
+            /* Wrap configuration, no state change */
+          }
+        }
+      }
+    }
+    else
+    {
+      status = HAL_BUSY;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the command configuration in interrupt mode.
+  * @param  hxspi : XSPI handle
+  * @param  pCmd   : structure that contains the command configuration information
+  * @note   This function is used only in Indirect Read or Write Modes
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters of the command structure */
+  assert_param(IS_XSPI_OPERATION_TYPE(pCmd->OperationType));
+
+  if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM)
+  {
+    assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect));
+  }
+
+  assert_param(IS_XSPI_INSTRUCTION_MODE(pCmd->InstructionMode));
+  if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE)
+  {
+    assert_param(IS_XSPI_INSTRUCTION_WIDTH(pCmd->InstructionWidth));
+    assert_param(IS_XSPI_INSTRUCTION_DTR_MODE(pCmd->InstructionDTRMode));
+  }
+
+  assert_param(IS_XSPI_ADDRESS_MODE(pCmd->AddressMode));
+  if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE)
+  {
+    assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth));
+    assert_param(IS_XSPI_ADDRESS_DTR_MODE(pCmd->AddressDTRMode));
+  }
+
+  assert_param(IS_XSPI_ALT_BYTES_MODE(pCmd->AlternateBytesMode));
+  if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE)
+  {
+    assert_param(IS_XSPI_ALT_BYTES_WIDTH(pCmd->AlternateBytesWidth));
+    assert_param(IS_XSPI_ALT_BYTES_DTR_MODE(pCmd->AlternateBytesDTRMode));
+  }
+
+  assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode));
+
+  if (pCmd->DataMode != HAL_XSPI_DATA_NONE)
+  {
+    assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength));
+    assert_param(IS_XSPI_DATA_DTR_MODE(pCmd->DataDTRMode));
+    assert_param(IS_XSPI_DUMMY_CYCLES(pCmd->DummyCycles));
+  }
+
+  assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode));
+
+  /* Check the state of the driver */
+  if ((hxspi->State  == HAL_XSPI_STATE_READY) && (pCmd->OperationType     == HAL_XSPI_OPTYPE_COMMON_CFG) &&
+      (pCmd->DataMode == HAL_XSPI_DATA_NONE)   && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS))
+  {
+    /* Wait till busy flag is reset */
+    status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Initialize error code */
+      hxspi->ErrorCode = HAL_XSPI_ERROR_NONE;
+
+      /* Clear flags related to interrupt */
+      HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC);
+
+      /* Configure the registers */
+      status = XSPI_ConfigCmd(hxspi, pCmd);
+
+      if (status == HAL_OK)
+      {
+        /* Update the state */
+        hxspi->State = HAL_XSPI_STATE_BUSY_CMD;
+
+        /* Enable the transfer complete and transfer error interrupts */
+        HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_TE);
+      }
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Hyperbus parameters.
+  * @param  hxspi   : XSPI handle
+  * @param  pCfg     : Pointer to Structure containing the Hyperbus configuration
+  * @param  Timeout : Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg,
+                                       uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t state;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters of the hyperbus configuration structure */
+  assert_param(IS_XSPI_RW_RECOVERY_TIME_CYCLE(pCfg->RWRecoveryTimeCycle));
+  assert_param(IS_XSPI_ACCESS_TIME_CYCLE(pCfg->AccessTimeCycle));
+  assert_param(IS_XSPI_WRITE_ZERO_LATENCY(pCfg->WriteZeroLatency));
+  assert_param(IS_XSPI_LATENCY_MODE(pCfg->LatencyMode));
+
+  /* Check the state of the driver */
+  state = hxspi->State;
+  if ((state == HAL_XSPI_STATE_HYPERBUS_INIT) || (state == HAL_XSPI_STATE_READY))
+  {
+    /* Wait till busy flag is reset */
+    status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Configure Hyperbus configuration Latency register */
+      WRITE_REG(hxspi->Instance->HLCR, ((pCfg->RWRecoveryTimeCycle << XSPI_HLCR_TRWR_Pos) |
+                                        (pCfg->AccessTimeCycle << XSPI_HLCR_TACC_Pos)     |
+                                        pCfg->WriteZeroLatency | pCfg->LatencyMode));
+
+      /* Update the state */
+      hxspi->State = HAL_XSPI_STATE_READY;
+    }
+    else
+    {
+      status = HAL_BUSY;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the Hyperbus command configuration.
+  * @param  hxspi   : XSPI handle
+  * @param  pCmd     : Structure containing the Hyperbus command
+  * @param  Timeout : Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd,
+                                       uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters of the hyperbus command structure */
+  assert_param(IS_XSPI_ADDRESS_SPACE(pCmd->AddressSpace));
+  assert_param(IS_XSPI_ADDRESS_WIDTH(pCmd->AddressWidth));
+  assert_param(IS_XSPI_DATA_LENGTH(pCmd->DataLength));
+  assert_param(IS_XSPI_DQS_MODE(pCmd->DQSMode));
+  assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode));
+
+  /* Check the state of the driver */
+  if ((hxspi->State == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS))
+  {
+    /* Wait till busy flag is reset */
+    status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Re-initialize the value of the functional mode */
+      MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U);
+
+      /* Configure the address space in the DCR1 register */
+      MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP_0, pCmd->AddressSpace);
+
+      /* Configure the CCR and WCCR registers with the address size and the following configuration :
+         - DQS signal enabled (used as RWDS)
+         - DTR mode enabled on address and data */
+      /* - address and data on 8 or 16 lines */
+      WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | pCmd->DataMode |
+                                       pCmd->AddressWidth | XSPI_CCR_ADDTR | XSPI_CCR_ADMODE_2));
+      WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | pCmd->DataMode |
+                                        pCmd->AddressWidth | XSPI_WCCR_ADDTR | XSPI_WCCR_ADMODE_2));
+
+      /* Configure the DLR register with the number of data */
+      WRITE_REG(hxspi->Instance->DLR, (pCmd->DataLength - 1U));
+
+      /* Configure the AR register with the address value */
+      WRITE_REG(hxspi->Instance->AR, pCmd->Address);
+
+      /* Update the state */
+      hxspi->State = HAL_XSPI_STATE_CMD_CFG;
+    }
+    else
+    {
+      status = HAL_BUSY;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hxspi   : XSPI handle
+  * @param  pData   : pointer to data buffer
+  * @param  Timeout : Timeout duration
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+  __IO uint32_t *data_reg = &hxspi->Instance->DR;
+
+  /* Check the data pointer allocation */
+  if (pData == NULL)
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+  else
+  {
+    /* Check the state */
+    if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+    {
+      /* Configure counters and size */
+      hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U;
+      hxspi->XferSize  = hxspi->XferCount;
+      hxspi->pBuffPtr  = (uint8_t *)pData;
+
+      /* Configure CR register with functional mode as indirect write */
+      MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      do
+      {
+        /* Wait till fifo threshold flag is set to send data */
+        status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout);
+
+        if (status != HAL_OK)
+        {
+          break;
+        }
+
+        *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr;
+        hxspi->pBuffPtr++;
+        hxspi->XferCount--;
+      } while (hxspi->XferCount > 0U);
+
+      if (status == HAL_OK)
+      {
+        /* Wait till transfer complete flag is set to go back in idle state */
+        status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          /* Clear transfer complete flag */
+          HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC);
+
+          hxspi->State = HAL_XSPI_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hxspi   : XSPI handle
+  * @param  pData   : pointer to data buffer
+  * @param  Timeout : Timeout duration
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+  __IO uint32_t *data_reg = &hxspi->Instance->DR;
+  uint32_t addr_reg = hxspi->Instance->AR;
+  uint32_t ir_reg = hxspi->Instance->IR;
+
+  /* Check the data pointer allocation */
+  if (pData == NULL)
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+  else
+  {
+    /* Check the state */
+    if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+    {
+      /* Configure counters and size */
+      hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U;
+      hxspi->XferSize  = hxspi->XferCount;
+      hxspi->pBuffPtr  = pData;
+
+      /* Configure CR register with functional mode as indirect read */
+      MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Trig the transfer by re-writing address or instruction register */
+      if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)
+      {
+        WRITE_REG(hxspi->Instance->AR, addr_reg);
+      }
+      else
+      {
+        if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE)
+        {
+          WRITE_REG(hxspi->Instance->AR, addr_reg);
+        }
+        else
+        {
+          WRITE_REG(hxspi->Instance->IR, ir_reg);
+        }
+      }
+
+      do
+      {
+        /* Wait till fifo threshold or transfer complete flags are set to read received data */
+        status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, tickstart, Timeout);
+
+        if (status != HAL_OK)
+        {
+          break;
+        }
+
+        *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg);
+        hxspi->pBuffPtr++;
+        hxspi->XferCount--;
+      } while (hxspi->XferCount > 0U);
+
+      if (status == HAL_OK)
+      {
+        /* Wait till transfer complete flag is set to go back in idle state */
+        status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout);
+
+        if (status == HAL_OK)
+        {
+          /* Clear transfer complete flag */
+          HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC);
+
+          hxspi->State = HAL_XSPI_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with interrupt.
+  * @param  hxspi : XSPI handle
+  * @param  pData : pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the data pointer allocation */
+  if (pData == NULL)
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+  else
+  {
+    /* Check the state */
+    if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+    {
+      /* Configure counters and size */
+      hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U;
+      hxspi->XferSize  = hxspi->XferCount;
+      hxspi->pBuffPtr  = (uint8_t *)pData;
+
+      /* Configure CR register with functional mode as indirect write */
+      MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+      /* Clear flags related to interrupt */
+      HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC);
+
+      /* Update the state */
+      hxspi->State = HAL_XSPI_STATE_BUSY_TX;
+
+      /* Enable the transfer complete, fifo threshold and transfer error interrupts */
+      HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE);
+    }
+    else
+    {
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with interrupt.
+  * @param  hxspi : XSPI handle
+  * @param  pData : pointer to data buffer
+  * @note   This function is used only in Indirect Read Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t addr_reg = hxspi->Instance->AR;
+  uint32_t ir_reg = hxspi->Instance->IR;
+
+  /* Check the data pointer allocation */
+  if (pData == NULL)
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+  else
+  {
+    /* Check the state */
+    if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+    {
+      /* Configure counters and size */
+      hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U;
+      hxspi->XferSize  = hxspi->XferCount;
+      hxspi->pBuffPtr  = pData;
+
+      /* Configure CR register with functional mode as indirect read */
+      MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+      /* Clear flags related to interrupt */
+      HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC);
+
+      /* Update the state */
+      hxspi->State = HAL_XSPI_STATE_BUSY_RX;
+
+      /* Enable the transfer complete, fifo threshold and transfer error interrupts */
+      HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE);
+
+      /* Trig the transfer by re-writing address or instruction register */
+      if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)
+      {
+        WRITE_REG(hxspi->Instance->AR, addr_reg);
+      }
+      else
+      {
+        if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE)
+        {
+          WRITE_REG(hxspi->Instance->AR, addr_reg);
+        }
+        else
+        {
+          WRITE_REG(hxspi->Instance->IR, ir_reg);
+        }
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Send an amount of data in non-blocking mode with DMA.
+  * @param  hxspi : XSPI handle
+  * @param  pData : pointer to data buffer
+  * @note   This function is used only in Indirect Write Mode
+  * @note   If DMA peripheral access is configured as halfword, the number
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t data_size = hxspi->Instance->DLR + 1U;
+  DMA_QListTypeDef *p_queue = {NULL};
+  uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE;
+
+  /* Check the data pointer allocation */
+  if (pData == NULL)
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+  else
+  {
+    /* Check the state */
+    if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+    {
+      if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        p_queue = hxspi->hdmatx->LinkedListQueue;
+        if ((p_queue != NULL) && (p_queue->Head != NULL))
+        {
+          data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+        }
+        else
+        {
+          /* Set Error Code function status  */
+          hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+
+          /* Return function status */
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        data_width = hxspi->hdmatx->Init.DestDataWidth;
+      }
+      /* Configure counters and size */
+      if (data_width == DMA_DEST_DATAWIDTH_BYTE)
+      {
+        hxspi->XferCount = data_size;
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+      {
+        if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword
+          => no transfer possible with DMA peripheral access configured as halfword */
+          hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+        }
+        else
+        {
+          hxspi->XferCount = data_size;
+        }
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_WORD)
+      {
+        if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on word
+          => no transfer possible with DMA peripheral access configured as word */
+          hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+        }
+        else
+        {
+          hxspi->XferCount = data_size;
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if (status == HAL_OK)
+      {
+        hxspi->XferSize = hxspi->XferCount;
+        hxspi->pBuffPtr = (uint8_t *)pData;
+
+        /* Configure CR register with functional mode as indirect write */
+        MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+
+        /* Clear flags related to interrupt */
+        HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC);
+
+        /* Update the state */
+        hxspi->State = HAL_XSPI_STATE_BUSY_TX;
+
+        /* Set the DMA transfer complete callback */
+        hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt;
+
+        /* Set the DMA Half transfer complete callback */
+        hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt;
+
+        /* Set the DMA error callback */
+        hxspi->hdmatx->XferErrorCallback = XSPI_DMAError;
+
+        /* Clear the DMA abort callback */
+        hxspi->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the transmit DMA Channel */
+        if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hxspi->hdmatx->LinkedListQueue != NULL)
+          {
+            /* Enable the DMA channel */
+            MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \
+                       (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED));
+            MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \
+                       DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH);
+            /* Set DMA data size*/
+            p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize;
+            /* Set DMA source address */
+            p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
+            /* Set DMA destination address */
+            p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR;
+
+            status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx);
+          }
+          else
+          {
+            /* Set Error Code */
+            hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+
+            hxspi->State = HAL_XSPI_STATE_READY;
+
+            /* Return function status */
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) &&
+              (hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_FIXED))
+          {
+            status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->XferSize);
+          }
+          else
+          {
+            /* no transmit possible with DMA peripheral, invalid configuration */
+            hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+            status = HAL_ERROR;
+          }
+        }
+        if (status == HAL_OK)
+        {
+          /* Enable the transfer error interrupt */
+          HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE);
+
+          /* Enable the DMA transfer by setting the DMAEN bit  */
+          SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+          hxspi->State = HAL_XSPI_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @param  hxspi : XSPI handle
+  * @param  pData : pointer to data buffer.
+  * @note   This function is used only in Indirect Read Mode
+  * @note   If DMA peripheral access is configured as halfword, the number
+  *         of data and the fifo threshold should be aligned on halfword
+  * @note   If DMA peripheral access is configured as word, the number
+  *         of data and the fifo threshold should be aligned on word
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t data_size = hxspi->Instance->DLR + 1U;
+  uint32_t addr_reg = hxspi->Instance->AR;
+  uint32_t ir_reg = hxspi->Instance->IR;
+  DMA_QListTypeDef *p_queue = {NULL};
+  uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE;
+
+  /* Check the data pointer allocation */
+  if (pData == NULL)
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+  else
+  {
+    /* Check the state */
+    if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+    {
+      if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+      {
+        p_queue = hxspi->hdmarx->LinkedListQueue;
+        if ((p_queue != NULL) && (p_queue->Head != NULL))
+        {
+          data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
+        }
+        else
+        {
+          /* Set Error Code */
+          hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+
+          /* Return function status */
+          status = HAL_ERROR;
+        }
+      }
+      else
+      {
+        data_width = hxspi->hdmarx->Init.DestDataWidth;
+      }
+
+      /* Configure counters and size */
+      if (data_width == DMA_DEST_DATAWIDTH_BYTE)
+      {
+        hxspi->XferCount = data_size;
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
+      {
+        if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on halfword
+          => no transfer possible with DMA peripheral access configured as halfword */
+          hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+        }
+        else
+        {
+          hxspi->XferCount = data_size;
+        }
+      }
+      else if (data_width == DMA_DEST_DATAWIDTH_WORD)
+      {
+        if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U))
+        {
+          /* The number of data or the fifo threshold is not aligned on word
+          => no transfer possible with DMA peripheral access configured as word */
+          hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+          status = HAL_ERROR;
+        }
+        else
+        {
+          hxspi->XferCount = data_size;
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if (status == HAL_OK)
+      {
+        hxspi->XferSize  = hxspi->XferCount;
+        hxspi->pBuffPtr  = pData;
+
+        /* Configure CR register with functional mode as indirect read */
+        MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ);
+
+        /* Clear flags related to interrupt */
+        HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC);
+
+        /* Update the state */
+        hxspi->State = HAL_XSPI_STATE_BUSY_RX;
+
+        /* Set the DMA transfer complete callback */
+        hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt;
+
+        /* Set the DMA Half transfer complete callback */
+        hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt;
+
+        /* Set the DMA error callback */
+        hxspi->hdmarx->XferErrorCallback = XSPI_DMAError;
+
+        /* Clear the DMA abort callback */
+        hxspi->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the receive DMA Channel */
+        if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
+        {
+          if (hxspi->hdmarx->LinkedListQueue != NULL)
+          {
+            /* Enable the DMA channel */
+            MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \
+                       (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED));
+            MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \
+                       DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY);
+            /* Set DMA data size */
+            p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize;
+            /* Set DMA source address */
+            p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR;
+            /* Set DMA destination address */
+            p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
+
+            status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx);
+          }
+          else
+          {
+            /* Set Error Code */
+            hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+
+            hxspi->State = HAL_XSPI_STATE_READY;
+
+            /* Return function status */
+            status = HAL_ERROR;
+          }
+        }
+        else
+        {
+          if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_SINC_FIXED)
+              && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED))
+          {
+            status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->XferSize);
+          }
+          else
+          {
+            /* no receive possible with DMA peripheral, invalid configuration */
+            hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+            status = HAL_ERROR;
+          }
+        }
+        if (status == HAL_OK)
+        {
+          /* Enable the transfer error interrupt */
+          HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE);
+
+          /* Trig the transfer by re-writing address or instruction register */
+          if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)
+          {
+            WRITE_REG(hxspi->Instance->AR, addr_reg);
+          }
+          else
+          {
+            if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE)
+            {
+              WRITE_REG(hxspi->Instance->AR, addr_reg);
+            }
+            else
+            {
+              WRITE_REG(hxspi->Instance->IR, ir_reg);
+            }
+          }
+
+          /* Enable the DMA transfer by setting the DMAEN bit  */
+          SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+          hxspi->State = HAL_XSPI_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the XSPI Automatic Polling Mode in blocking mode.
+  * @param  hxspi   : XSPI handle
+  * @param  pCfg     : Pointer to structure that contains the polling configuration information.
+  * @param  Timeout : Timeout duration
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg,
+                                       uint32_t Timeout)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t addr_reg = hxspi->Instance->AR;
+  uint32_t ir_reg = hxspi->Instance->IR;
+#ifdef USE_FULL_ASSERT
+  uint32_t dlr_reg = hxspi->Instance->DLR;
+#endif /* USE_FULL_ASSERT */
+
+  /* Check the parameters of the autopolling configuration structure */
+  assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode));
+  assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop));
+  assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime));
+  assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
+
+  /* Check the state */
+  if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_ENABLE))
+  {
+    /* Wait till busy flag is reset */
+    status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Configure registers */
+      WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue);
+      WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask);
+      WRITE_REG(hxspi->Instance->PIR,   pCfg->IntervalTime);
+      MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE),
+                 (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING));
+
+      /* Trig the transfer by re-writing address or instruction register */
+      if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)
+      {
+        WRITE_REG(hxspi->Instance->AR, addr_reg);
+      }
+      else
+      {
+        if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE)
+        {
+          WRITE_REG(hxspi->Instance->AR, addr_reg);
+        }
+        else
+        {
+          WRITE_REG(hxspi->Instance->IR, ir_reg);
+        }
+      }
+
+      /* Wait till status match flag is set to go back in idle state */
+      status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout);
+
+      if (status == HAL_OK)
+      {
+        /* Clear status match flag */
+        HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM);
+
+        hxspi->State = HAL_XSPI_STATE_READY;
+      }
+    }
+    else
+    {
+      status = HAL_BUSY;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the XSPI Automatic Polling Mode in non-blocking mode.
+  * @param  hxspi : XSPI handle
+  * @param  pCfg   : Pointer to structure that contains the polling configuration information.
+  * @note   This function is used only in Automatic Polling Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t addr_reg = hxspi->Instance->AR;
+  uint32_t ir_reg = hxspi->Instance->IR;
+#ifdef USE_FULL_ASSERT
+  uint32_t dlr_reg = hxspi->Instance->DLR;
+#endif /* USE_FULL_ASSERT */
+
+  /* Check the parameters of the autopolling configuration structure */
+  assert_param(IS_XSPI_MATCH_MODE(pCfg->MatchMode));
+  assert_param(IS_XSPI_AUTOMATIC_STOP(pCfg->AutomaticStop));
+  assert_param(IS_XSPI_INTERVAL(pCfg->IntervalTime));
+  assert_param(IS_XSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
+
+  /* Check the state */
+  if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+  {
+    /* Wait till busy flag is reset */
+    status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout);
+
+    if (status == HAL_OK)
+    {
+      /* Configure registers */
+      WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue);
+      WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask);
+      WRITE_REG(hxspi->Instance->PIR,   pCfg->IntervalTime);
+      MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE),
+                 (pCfg->MatchMode | pCfg->AutomaticStop | XSPI_FUNCTIONAL_MODE_AUTO_POLLING));
+
+      /* Clear flags related to interrupt */
+      HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_SM);
+
+      hxspi->State = HAL_XSPI_STATE_BUSY_AUTO_POLLING;
+
+      /* Enable the status match and transfer error interrupts */
+      HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE);
+
+      /* Trig the transfer by re-writing address or instruction register */
+      if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS)
+      {
+        WRITE_REG(hxspi->Instance->AR, addr_reg);
+      }
+      else
+      {
+        if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE)
+        {
+          WRITE_REG(hxspi->Instance->AR, addr_reg);
+        }
+        else
+        {
+          WRITE_REG(hxspi->Instance->IR, ir_reg);
+        }
+      }
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Memory Mapped mode.
+  * @param  hxspi : XSPI handle
+  * @param  pCfg   : Pointer to structure that contains the memory mapped configuration information.
+  * @note   This function is used only in Memory mapped Mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the parameters of the memory-mapped configuration structure */
+  assert_param(IS_XSPI_TIMEOUT_ACTIVATION(pCfg->TimeOutActivation));
+  assert_param(IS_XSPI_NO_PREFETCH_DATA(pCfg->NoPrefetchData));
+
+  /* Check the state */
+  if (hxspi->State == HAL_XSPI_STATE_CMD_CFG)
+  {
+    /* Wait till busy flag is reset */
+    status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout);
+
+    if (status == HAL_OK)
+    {
+      hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED;
+
+      if (pCfg->NoPrefetchData == HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE)
+      {
+        /* Configure register */
+        MODIFY_REG(hxspi->Instance->CR, XSPI_CR_NOPREF, pCfg->NoPrefetchData);
+      }
+
+      else
+      {
+        assert_param(IS_XSPI_NO_PREFETCH_AXI(pCfg->NoPrefetchAXI));
+
+        /* Configure register */
+        MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_NOPREF | XSPI_CR_NOPREF_AXI),
+                   (pCfg->NoPrefetchData | pCfg->NoPrefetchAXI));
+      }
+      if (pCfg->TimeOutActivation == HAL_XSPI_TIMEOUT_COUNTER_ENABLE)
+      {
+        assert_param(IS_XSPI_TIMEOUT_PERIOD(pCfg->TimeoutPeriodClock));
+
+        /* Configure register */
+        WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock);
+
+        /* Clear flags related to interrupt */
+        HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO);
+
+        /* Enable the timeout interrupt */
+        HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO);
+      }
+
+      /* Configure CR register with functional mode as memory-mapped */
+      MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE),
+                 (pCfg->TimeOutActivation | XSPI_FUNCTIONAL_MODE_MEMORY_MAPPED));
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Transfer Error callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_XSPI_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Abort completed callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_XSPI_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FIFO Threshold callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_XSPI_FIFOThresholdCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Command completed callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_XSPI_CmdCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_XSPI_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_XSPI_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_XSPI_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_XSPI_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Status Match callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_XSPI_StatusMatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout callback.
+  * @param  hxspi : XSPI handle
+  * @retval None
+  */
+__weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hxspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_XSPI_TimeOutCallback could be implemented in the user file
+   */
+}
+
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User XSPI Callback
+  *         To be used to override the weak predefined callback
+  * @param hxspi : XSPI handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_XSPI_ERROR_CB_ID          XSPI Error Callback ID
+  *          @arg @ref HAL_XSPI_ABORT_CB_ID          XSPI Abort Callback ID
+  *          @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID
+  *          @arg @ref HAL_XSPI_CMD_CPLT_CB_ID       XSPI Command Complete Callback ID
+  *          @arg @ref HAL_XSPI_RX_CPLT_CB_ID        XSPI Rx Complete Callback ID
+  *          @arg @ref HAL_XSPI_TX_CPLT_CB_ID        XSPI Tx Complete Callback ID
+  *          @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID   XSPI Rx Half Complete Callback ID
+  *          @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID   XSPI Tx Half Complete Callback ID
+  *          @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID   XSPI Status Match Callback ID
+  *          @arg @ref HAL_XSPI_TIMEOUT_CB_ID        XSPI Timeout Callback ID
+  *          @arg @ref HAL_XSPI_MSP_INIT_CB_ID       XSPI MspInit callback ID
+  *          @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID     XSPI MspDeInit callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID,
+                                            pXSPI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hxspi->State == HAL_XSPI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case  HAL_XSPI_ERROR_CB_ID :
+        hxspi->ErrorCallback = pCallback;
+        break;
+      case HAL_XSPI_ABORT_CB_ID :
+        hxspi->AbortCpltCallback = pCallback;
+        break;
+      case HAL_XSPI_FIFO_THRESHOLD_CB_ID :
+        hxspi->FifoThresholdCallback = pCallback;
+        break;
+      case HAL_XSPI_CMD_CPLT_CB_ID :
+        hxspi->CmdCpltCallback = pCallback;
+        break;
+      case HAL_XSPI_RX_CPLT_CB_ID :
+        hxspi->RxCpltCallback = pCallback;
+        break;
+      case HAL_XSPI_TX_CPLT_CB_ID :
+        hxspi->TxCpltCallback = pCallback;
+        break;
+      case HAL_XSPI_RX_HALF_CPLT_CB_ID :
+        hxspi->RxHalfCpltCallback = pCallback;
+        break;
+      case HAL_XSPI_TX_HALF_CPLT_CB_ID :
+        hxspi->TxHalfCpltCallback = pCallback;
+        break;
+      case HAL_XSPI_STATUS_MATCH_CB_ID :
+        hxspi->StatusMatchCallback = pCallback;
+        break;
+      case HAL_XSPI_TIMEOUT_CB_ID :
+        hxspi->TimeOutCallback = pCallback;
+        break;
+      case HAL_XSPI_MSP_INIT_CB_ID :
+        hxspi->MspInitCallback = pCallback;
+        break;
+      case HAL_XSPI_MSP_DEINIT_CB_ID :
+        hxspi->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hxspi->State == HAL_XSPI_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_XSPI_MSP_INIT_CB_ID :
+        hxspi->MspInitCallback = pCallback;
+        break;
+      case HAL_XSPI_MSP_DEINIT_CB_ID :
+        hxspi->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User XSPI Callback
+  *         XSPI Callback is redirected to the weak predefined callback
+  * @param hxspi : XSPI handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_XSPI_ERROR_CB_ID          XSPI Error Callback ID
+  *          @arg @ref HAL_XSPI_ABORT_CB_ID          XSPI Abort Callback ID
+  *          @arg @ref HAL_XSPI_FIFO_THRESHOLD_CB_ID XSPI FIFO Threshold Callback ID
+  *          @arg @ref HAL_XSPI_CMD_CPLT_CB_ID       XSPI Command Complete Callback ID
+  *          @arg @ref HAL_XSPI_RX_CPLT_CB_ID        XSPI Rx Complete Callback ID
+  *          @arg @ref HAL_XSPI_TX_CPLT_CB_ID        XSPI Tx Complete Callback ID
+  *          @arg @ref HAL_XSPI_RX_HALF_CPLT_CB_ID   XSPI Rx Half Complete Callback ID
+  *          @arg @ref HAL_XSPI_TX_HALF_CPLT_CB_ID   XSPI Tx Half Complete Callback ID
+  *          @arg @ref HAL_XSPI_STATUS_MATCH_CB_ID   XSPI Status Match Callback ID
+  *          @arg @ref HAL_XSPI_TIMEOUT_CB_ID        XSPI Timeout Callback ID
+  *          @arg @ref HAL_XSPI_MSP_INIT_CB_ID       XSPI MspInit callback ID
+  *          @arg @ref HAL_XSPI_MSP_DEINIT_CB_ID     XSPI MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hxspi->State == HAL_XSPI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case  HAL_XSPI_ERROR_CB_ID :
+        hxspi->ErrorCallback = HAL_XSPI_ErrorCallback;
+        break;
+      case HAL_XSPI_ABORT_CB_ID :
+        hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback;
+        break;
+      case HAL_XSPI_FIFO_THRESHOLD_CB_ID :
+        hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback;
+        break;
+      case HAL_XSPI_CMD_CPLT_CB_ID :
+        hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback;
+        break;
+      case HAL_XSPI_RX_CPLT_CB_ID :
+        hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback;
+        break;
+      case HAL_XSPI_TX_CPLT_CB_ID :
+        hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback;
+        break;
+      case HAL_XSPI_RX_HALF_CPLT_CB_ID :
+        hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback;
+        break;
+      case HAL_XSPI_TX_HALF_CPLT_CB_ID :
+        hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback;
+        break;
+      case HAL_XSPI_STATUS_MATCH_CB_ID :
+        hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback;
+        break;
+      case HAL_XSPI_TIMEOUT_CB_ID :
+        hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback;
+        break;
+      case HAL_XSPI_MSP_INIT_CB_ID :
+        hxspi->MspInitCallback = HAL_XSPI_MspInit;
+        break;
+      case HAL_XSPI_MSP_DEINIT_CB_ID :
+        hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hxspi->State == HAL_XSPI_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_XSPI_MSP_INIT_CB_ID :
+        hxspi->MspInitCallback = HAL_XSPI_MspInit;
+        break;
+      case HAL_XSPI_MSP_DEINIT_CB_ID :
+        hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions
+  *  @brief   XSPI control and State functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral Control and State functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Check in run-time the state of the driver.
+      (+) Check the error code set during last operation.
+      (+) Abort any operation.
+      (+) Manage the Fifo threshold.
+      (+) Configure the timeout duration used in the driver.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Abort the current operation, return to the indirect mode.
+  * @param  hxspi : XSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check if the state is not in reset state */
+  if (hxspi->State != HAL_XSPI_STATE_RESET)
+  {
+    /* Check if the DMA is enabled */
+    if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer on the XSPI side */
+      CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN);
+
+      /* Disable the DMA transmit on the DMA side */
+      status = HAL_DMA_Abort(hxspi->hdmatx);
+      if (status != HAL_OK)
+      {
+        hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+      }
+
+      /* Disable the DMA receive on the DMA side */
+      status = HAL_DMA_Abort(hxspi->hdmarx);
+      if (status != HAL_OK)
+      {
+        hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+      }
+    }
+
+    if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET)
+    {
+      /* Perform an abort of the XSPI */
+      SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT);
+
+      /* Wait until the transfer complete flag is set to go back in idle state */
+      status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout);
+
+      if (status == HAL_OK)
+      {
+        /* Clear transfer complete flag */
+        HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC);
+
+        /* Wait until the busy flag is reset to go back in idle state */
+        status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeout);
+
+        if (status == HAL_OK)
+        {
+          /* Return to indirect mode */
+          CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE);
+
+          hxspi->State = HAL_XSPI_STATE_READY;
+        }
+      }
+    }
+    else
+    {
+      /* Return to indirect mode */
+      CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE);
+
+      hxspi->State = HAL_XSPI_STATE_READY;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Abort the current operation, return to the indirect mode. (non-blocking function)
+  * @param  hxspi : XSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check if the state is not in reset state */
+  if (hxspi->State != HAL_XSPI_STATE_RESET)
+  {
+    /* Disable all interrupts */
+    HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE));
+
+    hxspi->State = HAL_XSPI_STATE_ABORT;
+
+    /* Check if the DMA is enabled */
+    if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U)
+    {
+      /* Disable the DMA transfer on the XSPI side */
+      CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN);
+
+      /* Disable the DMA transmit on the DMA side */
+      hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK)
+      {
+        hxspi->State = HAL_XSPI_STATE_READY;
+
+        /* Abort callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->AbortCpltCallback(hxspi);
+#else
+        HAL_XSPI_AbortCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+
+      /* Disable the DMA receive on the DMA side */
+      hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt;
+      if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK)
+      {
+        hxspi->State = HAL_XSPI_STATE_READY;
+
+        /* Abort callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->AbortCpltCallback(hxspi);
+#else
+        HAL_XSPI_AbortCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+    }
+    else
+    {
+      if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET)
+      {
+        /* Clear transfer complete flag */
+        HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC);
+
+        /* Enable the transfer complete interrupts */
+        HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC);
+
+        /* Perform an abort of the XSPI */
+        SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT);
+
+        /* Return to indirect mode */
+        CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE);
+      }
+      else
+      {
+        /* Return to indirect mode */
+        CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE);
+
+        hxspi->State = HAL_XSPI_STATE_READY;
+
+        /* Abort callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+        hxspi->AbortCpltCallback(hxspi);
+#else
+        HAL_XSPI_AbortCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+      }
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/** @brief  Set XSPI Fifo threshold.
+  * @param  hxspi     : XSPI handle.
+  * @param  Threshold : Threshold of the Fifo.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(Threshold));
+
+  /* Check the state */
+  if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U)
+  {
+    /* Synchronize initialization structure with the new fifo threshold value */
+    hxspi->Init.FifoThresholdByte = Threshold;
+
+    /* Configure new fifo threshold */
+    MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_FTHRES_Pos));
+
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/** @brief  Get XSPI Fifo threshold.
+  * @param  hxspi : XSPI handle.
+  * @retval Fifo threshold
+  */
+uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi)
+{
+  return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U);
+}
+
+/** @brief  Set XSPI Memory Type.
+  * @param  hxspi     : XSPI handle.
+  * @param  Type : Memory Type.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_XSPI_MEMORY_TYPE(Type));
+
+  /* Check the state */
+  if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U)
+  {
+    /* Synchronize initialization structure with the new memory type value */
+    hxspi->Init.MemoryType = Type;
+
+    /* Configure new memory type */
+    MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP, hxspi->Init.MemoryType);
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/** @brief  Set XSPI Device Size.
+  * @param  hxspi     : XSPI handle.
+  * @param  Size : Device Size.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_XSPI_MEMORY_SIZE(Size));
+
+  /* Check the state */
+  if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U)
+  {
+    /* Synchronize initialization structure with the new device size value */
+    hxspi->Init.MemorySize = Size;
+
+    /* Configure new device size */
+    MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE,
+               (hxspi->Init.MemorySize << XSPI_DCR1_DEVSIZE_Pos));
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/** @brief  Set XSPI Clock prescaler.
+  * @param  hxspi     : XSPI handle.
+  * @param  Prescaler : Clock prescaler.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_XSPI_CLK_PRESCALER(Prescaler));
+
+  /* Check the state */
+  if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U)
+  {
+    /* Synchronize initialization structure with the new clock prescaler value */
+    hxspi->Init.ClockPrescaler = Prescaler;
+
+    /* Configure clock prescaler */
+    MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER,
+               ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos));
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+  }
+
+  return status;
+}
+
+/** @brief Set XSPI timeout.
+  * @param  hxspi   : XSPI handle.
+  * @param  Timeout : Timeout for the memory access.
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout)
+{
+  hxspi->Timeout = Timeout;
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return the XSPI error code.
+  * @param  hxspi : XSPI handle
+  * @retval XSPI Error Code
+  */
+uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi)
+{
+  return hxspi->ErrorCode;
+}
+
+/**
+  * @brief  Return the XSPI handle state.
+  * @param  hxspi : XSPI handle
+  * @retval HAL state
+  */
+uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi)
+{
+  /* Return XSPI handle state */
+  return hxspi->State;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_Exported_Functions_Group4 IO Manager configuration function
+  *  @brief   XSPI IO Manager configuration function
+  *
+@verbatim
+ ===============================================================================
+                  ##### IO Manager configuration function #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Configure the IO manager.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the XSPI IO manager.
+  * @param  hxspi   : XSPI handle
+  * @param  pCfg     : Pointer to Configuration of the IO Manager for the instance
+  * @param  Timeout : Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint8_t index;
+  uint8_t xspi_enabled = 0U;
+
+  XSPIM_CfgTypeDef IOM_cfg[XSPI_NB_INSTANCE] = {0};
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Timeout);
+
+  /* Check the parameters of the XSPI IO Manager configuration structure */
+  assert_param(IS_XSPIM_NCS_OVR(pCfg->nCSOverride));
+  assert_param(IS_XSPIM_IO_PORT(pCfg->IOPort));
+  assert_param(IS_XSPIM_REQ2ACKTIME(pCfg->Req2AckTime));
+
+  /**************** Get current configuration of the instances ****************/
+  for (index = 0U; index < XSPI_NB_INSTANCE; index++)
+  {
+    XSPIM_GetConfig(index + 1U, &(IOM_cfg[index]));
+  }
+
+  /********** Disable all XSPI to configure XSPI IO Manager **********/
+  if (__HAL_RCC_XSPI1_IS_CLK_ENABLED() != 0U)
+  {
+    if ((XSPI1->CR & XSPI_CR_EN) != 0U)
+    {
+      CLEAR_BIT(XSPI1->CR, XSPI_CR_EN);
+      xspi_enabled |= 0x1U;
+    }
+  }
+  if (__HAL_RCC_XSPI2_IS_CLK_ENABLED() != 0U)
+  {
+    if ((XSPI2->CR & XSPI_CR_EN) != 0U)
+    {
+      CLEAR_BIT(XSPI2->CR, XSPI_CR_EN);
+      xspi_enabled |= 0x2U;
+    }
+  }
+  if (__HAL_RCC_XSPI3_IS_CLK_ENABLED() != 0U)
+  {
+    if ((XSPI3->CR & XSPI_CR_EN) != 0U)
+    {
+      CLEAR_BIT(XSPI2->CR, XSPI_CR_EN);
+      xspi_enabled |= 0x4U;
+    }
+  }
+
+  /***************** Deactivation of previous configuration *****************/
+  CLEAR_REG(XSPIM->CR);
+
+  /******************** Activation of new configuration *********************/
+  MODIFY_REG(XSPIM->CR, XSPIM_CR_REQ2ACK_TIME, ((pCfg->Req2AckTime - 1U) << XSPIM_CR_REQ2ACK_TIME_Pos));
+
+  if (hxspi->Instance == XSPI1)
+  {
+    IOM_cfg[0].IOPort = pCfg->IOPort ;
+    if (pCfg->nCSOverride != HAL_XSPI_CSSEL_OVR_DISABLED)
+    {
+      MODIFY_REG(XSPIM->CR, (XSPIM_CR_CSSEL_OVR_O1 | XSPIM_CR_CSSEL_OVR_EN), (pCfg->nCSOverride));
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else if (hxspi->Instance == XSPI2)
+  {
+    IOM_cfg[1].IOPort = pCfg->IOPort ;
+    if (pCfg->nCSOverride != HAL_XSPI_CSSEL_OVR_DISABLED)
+    {
+      MODIFY_REG(XSPIM->CR, (XSPIM_CR_CSSEL_OVR_O2 | XSPIM_CR_CSSEL_OVR_EN), (pCfg->nCSOverride));
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else if (hxspi->Instance == XSPI3)
+  {
+    if (pCfg->IOPort == HAL_XSPIM_IOPORT_1)
+    {
+      IOM_cfg[0].IOPort = HAL_XSPIM_IOPORT_2 ;
+      IOM_cfg[1].IOPort = HAL_XSPIM_IOPORT_2 ;
+    }
+    else if (pCfg->IOPort == HAL_XSPIM_IOPORT_2)
+    {
+      IOM_cfg[0].IOPort = HAL_XSPIM_IOPORT_1 ;
+      IOM_cfg[1].IOPort = HAL_XSPIM_IOPORT_1 ;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+  else
+  {
+    hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM;
+    return HAL_ERROR;
+  }
+
+  for (index = 0U; index < (XSPI_NB_INSTANCE - 2U); index++)
+  {
+    if (IOM_cfg[index].IOPort == IOM_cfg[index + 1U].IOPort)
+    {
+      /*Mux*/
+      SET_BIT(XSPIM->CR, XSPIM_CR_MUXEN);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+    if (IOM_cfg[0].IOPort == HAL_XSPIM_IOPORT_2)
+    {
+      /*Mode*/
+      SET_BIT(XSPIM->CR, XSPIM_CR_MODE);
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+  }
+
+  /******* Re-enable both XSPI after configure XSPI IO Manager ********/
+  if ((xspi_enabled & 0x1U) != 0U)
+  {
+    SET_BIT(XSPI1->CR, XSPI_CR_EN);
+  }
+  if ((xspi_enabled & 0x2U) != 0U)
+  {
+    SET_BIT(XSPI2->CR, XSPI_CR_EN);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions
+  *  @brief   XSPI high-speed interface and calibration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### High-speed interface and calibration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to :
+      (+) Get the delay values of the high-speed interface DLLs.
+    (+) Set a delay value for the high-speed interface DLLs.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the delay values of the high-speed interface DLLs.
+  * @param  hxspi : XSPI handle
+  * @param  pCfg   : Current delay values corresponding to the DelayValueType field.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t reg = 0;
+
+  if (IS_XSPI_ALL_INSTANCE(hxspi->Instance))
+  {
+    /* Check the parameter specified in the structure */
+    assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType));
+
+    switch (pCfg->DelayValueType)
+    {
+      case HAL_XSPI_CAL_FULL_CYCLE_DELAY:
+        reg = hxspi->Instance->CALFCR;
+        pCfg->MaxCalibration = (reg & XSPI_CALFCR_CALMAX);
+        break;
+      case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY:
+        reg = hxspi->Instance->CALMR;
+        break;
+      case HAL_XSPI_CAL_DATA_OUTPUT_DELAY:
+        reg = hxspi->Instance->CALSOR;
+        break;
+      case HAL_XSPI_CAL_DQS_INPUT_DELAY:
+        reg = hxspi->Instance->CALSIR;
+        break;
+      default:
+        status = HAL_ERROR;
+        hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      pCfg->FineCalibrationUnit = (reg & XSPI_CALFCR_FINE);
+      pCfg->CoarseCalibrationUnit = ((reg & XSPI_CALFCR_COARSE) >> XSPI_CALFCR_COARSE_Pos);
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set a delay value for the high-speed interface DLLs.
+  * @param  hxspi : XSPI handle
+  * @param  pCfg   : Configuration of delay value specified in DelayValueType field.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (IS_XSPI_ALL_INSTANCE(hxspi->Instance))
+  {
+    /* Check the parameter specified in the structure */
+    assert_param(IS_XSPI_DELAY_TYPE(pCfg->DelayValueType));
+    assert_param(IS_XSPI_FINECAL_VALUE(pCfg->FineCalibrationUnit));
+    assert_param(IS_XSPI_COARSECAL_VALUE(pCfg->CoarseCalibrationUnit));
+
+    /* Check if the state isn't in one of the busy states */
+    if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U)
+    {
+      switch (pCfg->DelayValueType)
+      {
+        case HAL_XSPI_CAL_FEEDBACK_CLK_DELAY:
+          MODIFY_REG(hxspi->Instance->CALMR, (XSPI_CALMR_COARSE |  XSPI_CALMR_FINE),
+                     (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALMR_COARSE_Pos)));
+          break;
+        case HAL_XSPI_CAL_DATA_OUTPUT_DELAY:
+          MODIFY_REG(hxspi->Instance->CALSOR, (XSPI_CALSOR_COARSE | XSPI_CALSOR_FINE),
+                     (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALSOR_COARSE_Pos)));
+          break;
+        case HAL_XSPI_CAL_DQS_INPUT_DELAY:
+          MODIFY_REG(hxspi->Instance->CALSIR, (XSPI_CALSIR_COARSE | XSPI_CALSIR_FINE),
+                     (pCfg->FineCalibrationUnit | (pCfg->CoarseCalibrationUnit << XSPI_CALSIR_COARSE_Pos)));
+          break;
+        default:
+          status = HAL_ERROR;
+          hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+          break;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+    hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  @cond 0
+  */
+/**
+  * @brief  DMA XSPI process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void XSPI_DMACplt(DMA_HandleTypeDef *hdma)
+{
+  XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent);
+  hxspi->XferCount = 0;
+
+  /* Disable the DMA transfer on the XSPI side */
+  CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN);
+
+  /* Enable the XSPI transfer complete Interrupt */
+  HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC);
+}
+
+/**
+  * @brief  DMA XSPI process half complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void XSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent);
+  hxspi->XferCount = (hxspi->XferCount >> 1);
+
+  if (hxspi->State == HAL_XSPI_STATE_BUSY_RX)
+  {
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    hxspi->RxHalfCpltCallback(hxspi);
+#else
+    HAL_XSPI_RxHalfCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+  }
+  else
+  {
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    hxspi->TxHalfCpltCallback(hxspi);
+#else
+    HAL_XSPI_TxHalfCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+  }
+}
+
+/**
+  * @brief  DMA XSPI communication error callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void XSPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent);
+  hxspi->XferCount = 0;
+  hxspi->ErrorCode = HAL_XSPI_ERROR_DMA;
+
+  /* Disable the DMA transfer on the XSPI side */
+  CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN);
+
+  /* Abort the XSPI */
+  if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK)
+  {
+    /* Disable the interrupts */
+    HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE);
+
+    hxspi->State = HAL_XSPI_STATE_READY;
+
+    /* Error callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    hxspi->ErrorCallback(hxspi);
+#else
+    HAL_XSPI_ErrorCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+  }
+}
+
+/**
+  * @brief  DMA XSPI abort complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
+{
+  XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent);
+  hxspi->XferCount = 0;
+
+  /* Check the state */
+  if (hxspi->State == HAL_XSPI_STATE_ABORT)
+  {
+    /* DMA abort called by XSPI abort */
+    if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET)
+    {
+      /* Clear transfer complete flag */
+      HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC);
+
+      /* Enable the transfer complete interrupts */
+      HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC);
+
+      /* Perform an abort of the XSPI */
+      SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT);
+    }
+    else
+    {
+      hxspi->State = HAL_XSPI_STATE_READY;
+
+      /* Abort callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+      hxspi->AbortCpltCallback(hxspi);
+#else
+      HAL_XSPI_AbortCpltCallback(hxspi);
+#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+    }
+  }
+  else
+  {
+    /* DMA abort called due to a transfer error interrupt */
+    hxspi->State = HAL_XSPI_STATE_READY;
+
+    /* Error callback */
+#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
+    hxspi->ErrorCallback(hxspi);
+#else
+    HAL_XSPI_ErrorCallback(hxspi);
+#endif /* defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
+  }
+}
+
+/**
+  * @brief  Wait for a flag state until timeout.
+  * @param  hxspi     : XSPI handle
+  * @param  Flag      : Flag checked
+  * @param  State     : Value of the flag expected
+  * @param  Timeout   : Duration of the timeout
+  * @param  Tickstart : Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag,
+                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is in expected state */
+  while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hxspi->State     = HAL_XSPI_STATE_READY;
+        hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT;
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the registers for the regular command mode.
+  * @param  hxspi : XSPI handle
+  * @param  pCmd   : structure that contains the command configuration information
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ccr_reg;
+  __IO uint32_t *tcr_reg;
+  __IO uint32_t *ir_reg;
+  __IO uint32_t *abr_reg;
+
+  /* Re-initialize the value of the functional mode */
+  MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U);
+
+  if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM)
+  {
+    assert_param(IS_XSPI_IO_SELECT(pCmd->IOSelect));
+    MODIFY_REG(hxspi->Instance->CR, XSPI_CR_MSEL, pCmd->IOSelect);
+  }
+
+  if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG)
+  {
+    ccr_reg = &(hxspi->Instance->WCCR);
+    tcr_reg = &(hxspi->Instance->WTCR);
+    ir_reg  = &(hxspi->Instance->WIR);
+    abr_reg = &(hxspi->Instance->WABR);
+  }
+  else if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRAP_CFG)
+  {
+    ccr_reg = &(hxspi->Instance->WPCCR);
+    tcr_reg = &(hxspi->Instance->WPTCR);
+    ir_reg  = &(hxspi->Instance->WPIR);
+    abr_reg = &(hxspi->Instance->WPABR);
+  }
+  else
+  {
+    ccr_reg = &(hxspi->Instance->CCR);
+    tcr_reg = &(hxspi->Instance->TCR);
+    ir_reg  = &(hxspi->Instance->IR);
+    abr_reg = &(hxspi->Instance->ABR);
+  }
+
+  /* Configure the CCR register with DQS and SIOO modes */
+  *ccr_reg = pCmd->DQSMode;
+
+  if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE)
+  {
+    /* Configure the ABR register with alternate bytes value */
+    *abr_reg = pCmd->AlternateBytes;
+
+    /* Configure the CCR register with alternate bytes communication parameters */
+    MODIFY_REG((*ccr_reg), (XSPI_CCR_ABMODE | XSPI_CCR_ABDTR | XSPI_CCR_ABSIZE),
+               (pCmd->AlternateBytesMode | pCmd->AlternateBytesDTRMode | pCmd->AlternateBytesWidth));
+  }
+
+  /* Configure the TCR register with the number of dummy cycles */
+  MODIFY_REG((*tcr_reg), XSPI_TCR_DCYC, pCmd->DummyCycles);
+
+  if (pCmd->DataMode != HAL_XSPI_DATA_NONE)
+  {
+    if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG)
+    {
+      /* Configure the DLR register with the number of data */
+      hxspi->Instance->DLR = (pCmd->DataLength - 1U);
+    }
+  }
+
+  /* Configure SSHIFT register to handle SDR/DTR data transfer */
+  if (pCmd->DataMode != HAL_XSPI_DATA_NONE)
+  {
+    if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)
+    {
+      /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */
+      CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT);
+    }
+    else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE)
+    {
+      /* Configure sample shifting */
+      SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT);
+    }
+    else
+    {
+      /* Do nothing */
+    }
+  }
+
+  if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE)
+  {
+    if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE)
+    {
+      if (pCmd->DataMode != HAL_XSPI_DATA_NONE)
+      {
+        /* ---- Command with instruction, address and data ---- */
+
+        /* Configure the CCR register with all communication parameters */
+        MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE  | XSPI_CCR_IDTR  | XSPI_CCR_ISIZE  |
+                                XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE |
+                                XSPI_CCR_DMODE  | XSPI_CCR_DDTR),
+                   (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth |
+                    pCmd->AddressMode     | pCmd->AddressDTRMode     | pCmd->AddressWidth     |
+                    pCmd->DataMode        | pCmd->DataDTRMode));
+      }
+      else
+      {
+        /* ---- Command with instruction and address ---- */
+
+        /* Configure the CCR register with all communication parameters */
+        MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE  | XSPI_CCR_IDTR  | XSPI_CCR_ISIZE  |
+                                XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE),
+                   (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth |
+                    pCmd->AddressMode     | pCmd->AddressDTRMode     | pCmd->AddressWidth));
+
+        /* The DHQC bit is linked with DDTR bit which should be activated */
+        if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) &&
+            (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
+        {
+          MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE);
+        }
+      }
+      /* Configure the IR register with the instruction value */
+      *ir_reg = pCmd->Instruction;
+
+      /* Configure the AR register with the address value */
+      hxspi->Instance->AR = pCmd->Address;
+    }
+    else
+    {
+      if (pCmd->DataMode != HAL_XSPI_DATA_NONE)
+      {
+        /* ---- Command with instruction and data ---- */
+
+        /* Configure the CCR register with all communication parameters */
+        MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE |
+                                XSPI_CCR_DMODE | XSPI_CCR_DDTR),
+                   (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth |
+                    pCmd->DataMode        | pCmd->DataDTRMode));
+      }
+      else
+      {
+        /* ---- Command with only instruction ---- */
+
+        /* Configure the CCR register with all communication parameters */
+        MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE),
+                   (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth));
+
+        /* The DHQC bit is linked with DDTR bit which should be activated */
+        if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) &&
+            (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
+        {
+          MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE);
+        }
+      }
+
+      /* Configure the IR register with the instruction value */
+      *ir_reg = pCmd->Instruction;
+
+    }
+  }
+  else
+  {
+    if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE)
+    {
+      if (pCmd->DataMode != HAL_XSPI_DATA_NONE)
+      {
+        /* ---- Command with address and data ---- */
+
+        /* Configure the CCR register with all communication parameters */
+        MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE |
+                                XSPI_CCR_DMODE  | XSPI_CCR_DDTR),
+                   (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth     |
+                    pCmd->DataMode    | pCmd->DataDTRMode));
+      }
+      else
+      {
+        /* ---- Command with only address ---- */
+
+        /* Configure the CCR register with all communication parameters */
+        MODIFY_REG((*ccr_reg), (XSPI_CCR_ADMODE | XSPI_CCR_ADDTR | XSPI_CCR_ADSIZE),
+                   (pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth));
+      }
+
+      /* Configure the AR register with the instruction value */
+      hxspi->Instance->AR = pCmd->Address;
+    }
+    else
+    {
+      /* ---- Invalid command configuration (no instruction, no address) ---- */
+      status = HAL_ERROR;
+      hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Get the current IOM configuration for an XSPI instance.
+  * @param  instance_nb : number of the instance
+  * @param  pCfg         : configuration of the IO Manager for the instance
+  * @retval HAL status
+  */
+static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg)
+{
+  uint32_t mux;
+  uint32_t mode;
+
+  if (instance_nb == 1U)
+  {
+    if ((XSPIM->CR & XSPIM_CR_MODE) == 0U)
+    {
+      pCfg->IOPort = HAL_XSPIM_IOPORT_1;
+    }
+    else
+    {
+      pCfg->IOPort = HAL_XSPIM_IOPORT_2;
+    }
+
+    if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN)
+    {
+      pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED;
+    }
+    else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O1) == XSPIM_CR_CSSEL_OVR_O1)
+    {
+      pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2;
+    }
+    else
+    {
+      pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1;
+    }
+  }
+  else
+  {
+    mux = (XSPIM->CR & XSPIM_CR_MUXEN);
+    mode = ((XSPIM->CR & XSPIM_CR_MODE) >> XSPIM_CR_MODE_Pos);
+    if (mux != mode)
+    {
+      pCfg->IOPort = HAL_XSPIM_IOPORT_1;
+    }
+    else
+    {
+      pCfg->IOPort = HAL_XSPIM_IOPORT_2;
+    }
+    if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_EN) != XSPIM_CR_CSSEL_OVR_EN)
+    {
+      pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_DISABLED;
+    }
+    else if ((XSPIM->CR & XSPIM_CR_CSSEL_OVR_O2) == XSPIM_CR_CSSEL_OVR_O2)
+    {
+      pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS2;
+    }
+    else
+    {
+      pCfg->nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1;
+    }
+  }
+}
+/**
+  @endcond
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* XSPI || XSPI1 || XSPI2 || XSPI3 */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_adc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_adc.c
new file mode 100644
index 000000000..d50e0ef33
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_adc.c
@@ -0,0 +1,1053 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_adc.c
+  * @author  MCD Application Team
+  * @brief   ADC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_adc.h"
+#include "stm32n6xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2)
+
+/** @addtogroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+  * @{
+  */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent  */
+/*       of device clock setting.                                             */
+/*       In user application, ADC timeout values should be defined with       */
+/*       temporal values, in function of device clock settings.               */
+/*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          APB prescaler 16, ADC prescaler 4.                                */
+/*        - ADC clock from asynchronous clock (PLL) with prescaler 1,         */
+/*          with highest ratio CPU clock frequency vs HSI clock frequency     */
+/* Unit: CPU cycles.                                                          */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (512UL * 16UL * 4UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* common to several ADC instances.                                           */
+/* (None) */
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC instance.                                                              */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
+  (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
+  )
+
+#define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__)                           \
+  (   ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9)                     \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10)                    \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11)                    \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12)                    \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13)                    \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14)                    \
+      || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15)                    \
+  )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
+  (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
+      || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                               \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group regular                                                          */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH1)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM12_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM18_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH1)                \
+  )
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
+  (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
+   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
+  )
+
+#define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__)           \
+  (((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER)                    \
+   || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)        \
+   || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)      \
+   || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_MDF_TRANSFER)                \
+  )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
+  (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
+   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
+  (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
+  (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)          \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)         \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)         \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)         \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)         \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)         \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)         \
+      || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)         \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group injected                                                         */
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH2)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM12_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM18_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_CH2)                \
+  )
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
+  (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                     \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
+  )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
+  (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                        \
+   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
+  (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)                  \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
+  (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)              \
+   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
+  )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* multimode.                                                                 */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
+  (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                              \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
+  )
+
+#define IS_LL_ADC_MULTI_DATA_FORMAT(__MULTI_DATA_FORMAT__)                     \
+  (((__MULTI_DATA_FORMAT__) == LL_ADC_MULTI_REG_DATA_EACH_ADC)                 \
+   || ((__MULTI_DATA_FORMAT__) == LL_ADC_MULTI_REG_DATA_COMMON_32B)            \
+   || ((__MULTI_DATA_FORMAT__) == LL_ADC_MULTI_REG_DATA_COMMON_16B)            \
+  )
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \
+  (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)              \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES)         \
+  )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
+  (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                           \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
+  )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of all ADC instances belonging to
+  *         the same ADC common instance to their default reset values.
+  * @note   This function is performing a hard reset, using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 series, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         To de-initialize only 1 ADC instance, use
+  *         function @ref LL_ADC_DeInit().
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+  /* Force reset of ADC clock (bus clock) */
+  LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
+
+  /* Release reset of ADC clock (bus clock) */
+  LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of ADC common parameters
+  *         (all ADC instances belonging to the same ADC common instance)
+  *         and multimode (for devices with several ADC instances available).
+  * @note   The setting of ADC common parameters is conditioned to
+  *         ADC instances state:
+  *         All ADC instances belonging to the same ADC common instance
+  *         must be disabled.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are initialized
+  *          - ERROR: ADC common registers are not initialized
+  */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+#if defined(ADC_MULTIMODE_SUPPORT)
+  assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
+  if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+  {
+    assert_param(IS_LL_ADC_MULTI_DATA_FORMAT(pADC_CommonInitStruct->MultiDataFormat));
+    assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
+  }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Note: Hardware constraint (refer to description of functions             */
+  /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
+  /*       On this STM32 series, setting of these features is conditioned to  */
+  /*       ADC state:                                                         */
+  /*       All ADC instances of the ADC common group must be disabled.        */
+  if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - common to several ADC                                               */
+    /*    (all ADC instances belonging to the same ADC common instance)       */
+    /*  - multimode (if several ADC instances available on the                */
+    /*    selected device)                                                    */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                 ADC_CCR_DUAL
+                 | ADC_CCR_DAMDF
+                 | ADC_CCR_DELAY
+                 ,
+                 pADC_CommonInitStruct->Multimode
+                 | pADC_CommonInitStruct->MultiDataFormat
+                 | pADC_CommonInitStruct->MultiTwoSamplingDelay
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                 ADC_CCR_DUAL
+                 | ADC_CCR_DAMDF
+                 | ADC_CCR_DELAY
+                 ,
+                 LL_ADC_MULTI_INDEPENDENT
+                );
+    }
+#else
+    /* No configuration to perform */
+#endif /* ADC_MULTIMODE_SUPPORT */
+  }
+  else
+  {
+    /* Initialization error: One or several ADC instances belonging to        */
+    /* the same ADC common instance are not disabled.                         */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+  * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
+{
+  /* Set ADC_CommonInitStruct fields to default values */
+  /* Set fields of ADC common */
+  /* (all ADC instances belonging to the same ADC common instance) */
+#if defined(ADC_MULTIMODE_SUPPORT)
+  /* Set fields of ADC multimode */
+  pADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
+  pADC_CommonInitStruct->MultiDataFormat       = LL_ADC_MULTI_REG_DATA_EACH_ADC;
+  pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+  * @brief  De-initialize registers of the selected ADC instance
+  *         to their default reset values.
+  * @note   To reset all ADC instances quickly (perform a hard reset),
+  *         use function @ref LL_ADC_CommonDeInit().
+  * @note   If this functions returns error status, it means that ADC instance
+  *         is in an unknown state.
+  *         In this case, perform a hard reset using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 series, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         Refer to function @ref LL_ADC_CommonDeInit().
+  * @param  ADCx ADC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are de-initialized
+  *          - ERROR: ADC registers are not de-initialized
+  */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  __IO uint32_t timeout_cpu_cycles = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  /* Disable ADC instance if not already disabled.                            */
+  if (LL_ADC_IsEnabled(ADCx) == 1UL)
+  {
+    /* Stop potential ADC conversion on going on ADC group regular.           */
+    if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
+    {
+      if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
+      {
+        LL_ADC_REG_StopConversion(ADCx);
+      }
+    }
+
+    /* Stop potential ADC conversion on going on ADC group injected.          */
+    if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
+    {
+      if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
+      {
+        LL_ADC_INJ_StopConversion(ADCx);
+      }
+    }
+
+    /* Wait for ADC conversions are effectively stopped                       */
+    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+    while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
+            | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+
+    /* Disable the ADC instance */
+    LL_ADC_Disable(ADCx);
+
+    /* Wait for ADC instance is effectively disabled */
+    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+    while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+  }
+
+  /* Check whether ADC state is compliant with expected state */
+  if (READ_BIT(ADCx->CR,
+               (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+                | ADC_CR_ADDIS | ADC_CR_ADEN)
+              )
+      == 0UL)
+  {
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    CLEAR_BIT(ADCx->IER,
+              (LL_ADC_IT_ADRDY
+               | LL_ADC_IT_EOC
+               | LL_ADC_IT_EOS
+               | LL_ADC_IT_OVR
+               | LL_ADC_IT_EOSMP
+               | LL_ADC_IT_JEOC
+               | LL_ADC_IT_JEOS
+               | LL_ADC_IT_AWD1
+               | LL_ADC_IT_AWD2
+               | LL_ADC_IT_AWD3
+              )
+             );
+
+    /* Reset register ISR */
+    SET_BIT(ADCx->ISR,
+            (LL_ADC_FLAG_ADRDY
+             | LL_ADC_FLAG_EOC
+             | LL_ADC_FLAG_EOS
+             | LL_ADC_FLAG_OVR
+             | LL_ADC_FLAG_EOSMP
+             | LL_ADC_FLAG_JEOC
+             | LL_ADC_FLAG_JEOS
+             | LL_ADC_FLAG_AWD1
+             | LL_ADC_FLAG_AWD2
+             | LL_ADC_FLAG_AWD3
+            )
+           );
+
+    /* Reset register CR */
+    /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
+    /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
+    /*    access mode "read-set": no direct reset applicable.                 */
+    /*  - Reset Calibration mode to default setting (single ended).           */
+    /*  - Enable ADC deep power down.                                         */
+    /*    Note: ADC internal voltage regulator disable and ADC deep power     */
+    /*          down enable are conditioned to ADC state disabled:            */
+    /*          already done above.                                           */
+    CLEAR_BIT(ADCx->CR, ADC_CR_ADCALDIF);
+    SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+
+    /* Reset register CFGR */
+    CLEAR_BIT(ADCx->CFGR1,
+              ADC_CFGR1_AWD1CH  | ADC_CFGR1_JAUTO   | ADC_CFGR1_JAWD1EN |
+              ADC_CFGR1_AWD1EN  | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
+              ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN  | ADC_CFGR1_AUTDLY  |
+              ADC_CFGR1_CONT    | ADC_CFGR1_OVRMOD  |
+              ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL  |
+              ADC_CFGR1_RES     | ADC_CFGR1_DMNGT);
+
+
+    /* Reset register CFGR2 */
+    CLEAR_BIT(ADCx->CFGR2,
+              (ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS
+               | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
+               | ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
+             );
+
+    /* Reset register SMPR1 */
+    CLEAR_BIT(ADCx->SMPR1,
+              (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+               | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+               | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+             );
+
+    /* Reset register SMPR2 */
+    CLEAR_BIT(ADCx->SMPR2,
+              (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
+               | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
+               | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
+             );
+
+    /* Reset registers of AWD1 thresholds */
+    CLEAR_BIT(ADCx->AWD1LTR, ADC_AWD1LTR_LTR);
+    SET_BIT(ADCx->AWD1HTR, ADC_AWD1HTR_HTR & (~ADC_AWD1HTR_HTR_22));
+
+    /* Reset registers of AWD2 thresholds */
+    CLEAR_BIT(ADCx->AWD2LTR, ADC_AWD2LTR_LTR);
+    SET_BIT(ADCx->AWD2HTR, ADC_AWD2HTR_HTR & (~ADC_AWD2HTR_HTR_22));
+
+    /* Reset registers of AWD3 thresholds */
+    CLEAR_BIT(ADCx->AWD3LTR, ADC_AWD3LTR_LTR);
+    SET_BIT(ADCx->AWD3HTR, ADC_AWD3HTR_HTR & (~ADC_AWD3HTR_HTR_22));
+
+    /* Reset register SQR1 */
+    CLEAR_BIT(ADCx->SQR1,
+              (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
+               | ADC_SQR1_SQ1 | ADC_SQR1_L)
+             );
+
+    /* Reset register SQR2 */
+    CLEAR_BIT(ADCx->SQR2,
+              (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
+               | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
+             );
+
+    /* Reset register SQR3 */
+    CLEAR_BIT(ADCx->SQR3,
+              (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
+               | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
+             );
+
+    /* Reset register SQR4 */
+    CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+    /* Reset register JSQR */
+    CLEAR_BIT(ADCx->JSQR,
+              (ADC_JSQR_JL
+               | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
+               | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1)
+             );
+
+    /* Reset register DR */
+    /* Note: bits in access mode read only, no direct reset applicable */
+
+    /* Reset register OFR1 */
+    CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET);
+    /* Reset register OFCFGR1 */
+    CLEAR_BIT(ADCx->OFCFGR1, ADC_OFCFGR1_SSAT | ADC_OFCFGR1_USAT | ADC_OFCFGR1_POSOFF | ADC_OFCFGR1_OFFSET_CH);
+    /* Reset register OFR2 */
+    CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET);
+    /* Reset register OFCFGR2 */
+    CLEAR_BIT(ADCx->OFCFGR2, ADC_OFCFGR2_SSAT | ADC_OFCFGR2_USAT | ADC_OFCFGR2_POSOFF | ADC_OFCFGR2_OFFSET_CH);
+    /* Reset register OFR3 */
+    CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET);
+    /* Reset register OFCFGR3 */
+    CLEAR_BIT(ADCx->OFCFGR3, ADC_OFCFGR3_SSAT | ADC_OFCFGR3_USAT | ADC_OFCFGR3_POSOFF | ADC_OFCFGR3_OFFSET_CH);
+    /* Reset register OFR4 */
+    CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET);
+    /* Reset register OFCFGR4 */
+    CLEAR_BIT(ADCx->OFCFGR4, ADC_OFCFGR4_SSAT | ADC_OFCFGR4_USAT | ADC_OFCFGR4_POSOFF | ADC_OFCFGR4_OFFSET_CH);
+
+    /* Reset register GCOMP */
+    /* Note: Bitfield ADC_GCOMP_GCOMPCOEFF reset value is 0x1000 */
+    MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF, 0x1000UL);
+
+    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+    /* Note: bits in access mode read only, no direct reset applicable */
+
+    /* Reset register AWD2CR */
+    CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+    /* Reset register AWD3CR */
+    CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+    /* Reset register DIFSEL */
+    CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+    /* Reset register PCSEL */
+    CLEAR_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL);
+
+    /* Reset register CALFACT */
+    CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+  }
+  else
+  {
+    /* ADC instance is in an unknown state */
+    /* Need to performing a hard reset of ADC instance, using high level      */
+    /* clock source RCC ADC reset.                                            */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 families).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, some other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
+  assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
+  assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(pADC_InitStruct->LeftBitShift));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC instance                                                        */
+    /*    - Set ADC data resolution                                           */
+    /*    - Set ADC conversion data alignment                                 */
+    /*    - Set ADC low power mode                                            */
+    MODIFY_REG(ADCx->CFGR1,
+               ADC_CFGR1_RES
+               | ADC_CFGR1_AUTDLY
+               ,
+               pADC_InitStruct->Resolution
+               | pADC_InitStruct->LowPowerMode
+              );
+
+    MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, pADC_InitStruct->LeftBitShift);
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
+  * @param  pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+  /* Set ADC_InitStruct fields to default values */
+  /* Set fields of ADC instance */
+  pADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
+  pADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
+  pADC_InitStruct->LeftBitShift  = LL_ADC_LEFT_BIT_SHIFT_NONE;
+}
+
+/**
+  * @brief  Initialize some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, pADC_RegInitStruct ->TriggerSource));
+  assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct ->SequencerLength));
+  assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_RegInitStruct ->DataTransferMode));
+
+  if (pADC_RegInitStruct ->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct ->SequencerDiscont));
+
+    /* ADC group regular continuous mode and discontinuous mode                 */
+    /* can not be enabled simultaneously                                       */
+    assert_param((pADC_RegInitStruct ->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+                 || (pADC_RegInitStruct ->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+  }
+  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct ->ContinuousMode));
+  assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct ->Overrun));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group regular                                                   */
+    /*    - Set ADC group regular trigger source                              */
+    /*    - Set ADC group regular sequencer length                            */
+    /*    - Set ADC group regular sequencer discontinuous mode                */
+    /*    - Set ADC group regular continuous mode                             */
+    /*    - Set ADC group regular conversion data transfer: no transfer or    */
+    /*      transfer by DMA, and DMA requests mode                            */
+    /*    - Set ADC group regular overrun behavior                            */
+    /* Note: On this STM32 series, ADC trigger edge is set when starting      */
+    /*       ADC conversion.                                                  */
+    /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().      */
+    if (pADC_RegInitStruct ->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_EXTSEL
+                 | ADC_CFGR1_EXTEN
+                 | ADC_CFGR1_DISCEN
+                 | ADC_CFGR1_DISCNUM
+                 | ADC_CFGR1_CONT
+                 | ADC_CFGR1_DMNGT
+                 | ADC_CFGR1_OVRMOD
+                 ,
+                 pADC_RegInitStruct ->TriggerSource
+                 | pADC_RegInitStruct ->SequencerDiscont
+                 | pADC_RegInitStruct ->ContinuousMode
+                 | pADC_RegInitStruct ->DataTransferMode
+                 | pADC_RegInitStruct ->Overrun
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_EXTSEL
+                 | ADC_CFGR1_EXTEN
+                 | ADC_CFGR1_DISCEN
+                 | ADC_CFGR1_DISCNUM
+                 | ADC_CFGR1_CONT
+                 | ADC_CFGR1_DMNGT
+                 | ADC_CFGR1_OVRMOD
+                 ,
+                 pADC_RegInitStruct ->TriggerSource
+                 | LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | pADC_RegInitStruct ->ContinuousMode
+                 | pADC_RegInitStruct ->DataTransferMode
+                 | pADC_RegInitStruct ->Overrun
+                );
+    }
+
+    /* Set ADC group regular sequencer length and scan direction */
+    LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct ->SequencerLength);
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+  * @param  pADC_RegInitStruct  Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+  /* Set ADC_REG_InitStruct fields to default values */
+  /* Set fields of ADC group regular */
+  /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by      */
+  /*       setting of trigger source to SW start.                             */
+  pADC_RegInitStruct ->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
+  pADC_RegInitStruct ->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  pADC_RegInitStruct ->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  pADC_RegInitStruct ->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
+  pADC_RegInitStruct ->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
+  pADC_RegInitStruct ->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+  * @brief  Initialize some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, pADC_InjInitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
+  if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
+  }
+  assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group injected                                                  */
+    /*    - Set ADC group injected trigger source                             */
+    /*    - Set ADC group injected sequencer length                           */
+    /*    - Set ADC group injected sequencer discontinuous mode               */
+    /*    - Set ADC group injected conversion trigger: independent or         */
+    /*      from ADC group regular                                            */
+    /* Note: On this STM32 series, ADC trigger edge is set when starting       */
+    /*       ADC conversion.                                                  */
+    /*       Refer to function @ref LL_ADC_INJ_StartConversionExtTrig().      */
+    if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_JDISCEN
+                 | ADC_CFGR1_JAUTO
+                 ,
+                 pADC_InjInitStruct->SequencerDiscont
+                 | pADC_InjInitStruct->TrigAuto
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_JDISCEN
+                 | ADC_CFGR1_JAUTO
+                 ,
+                 LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | pADC_InjInitStruct->TrigAuto
+                );
+    }
+
+    MODIFY_REG(ADCx->JSQR,
+               ADC_JSQR_JEXTSEL
+               | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JL
+               ,
+               pADC_InjInitStruct->TriggerSource
+               | pADC_InjInitStruct->SequencerLength
+              );
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+  * @param  pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
+{
+  /* Set ADC_INJ_InitStruct fields to default values */
+  /* Set fields of ADC group injected */
+  pADC_InjInitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
+  pADC_InjInitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+  pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+  pADC_InjInitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_crc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_crc.c
new file mode 100644
index 000000000..83d2c8b6e
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_crc.c
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_crc.c
+  * @author  MCD Application Team
+  * @brief   CRC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_crc.h"
+#include "stm32n6xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize CRC registers (Registers restored to their default values).
+  * @param  CRCx CRC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: CRC registers are de-initialized
+  *          - ERROR: CRC registers are not de-initialized
+  */
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+  if (CRCx == CRC)
+  {
+    /* Force CRC reset */
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_CRC);
+
+    /* Release CRC reset */
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_CRC);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (CRC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dlyb.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dlyb.c
new file mode 100644
index 000000000..7ae14b935
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dlyb.c
@@ -0,0 +1,243 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_dlyb.c
+  * @author  MCD Application Team
+  * @brief   DelayBlock Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DelayBlock peripheral:
+  *           + input clock frequency
+  *           + up to 12 oversampling phases
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### DelayBlock peripheral features #####
+  ==============================================================================
+    [..] The DelayBlock is used to generate an Output clock which is de-phased from the Input
+          clock. The phase of the Output clock is programmed by FW. The Output clock is then used
+          to clock the receive data in i.e. a SDMMC, OSPI or QSPI interface.
+         The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
+          and recenter the Output clock phase to the receive data.
+
+    [..] The DelayBlock features include the following:
+         (+) Input clock frequency.
+         (+) Up to 12 oversampling phases.
+
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers
+      that interfaces with the DELAY peripheral.
+      The LL_DLYB_SetDelay() function, configure the Delay value configured on SEL and UNIT.
+      The LL_DLYB_GetDelay() function, return the Delay value configured on SEL and UNIT.
+      The LL_DLYB_GetClockPeriod()function, get the clock period.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup DLYB_LL DLYB
+  * @brief DLYB LL module driver.
+  * @{
+  */
+
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED)
+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2)
+
+/**
+  @cond 0
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DLYB_TIMEOUT 0xFFU
+#define DLYB_LNG_10_0_MASK   0x07FF0000U
+#define DLYB_LNG_11_10_MASK  0x0C000000U
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/**
+  @endcond
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DLYB_LL_Exported_Functions
+  *  @brief    Configuration and control functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to
+      (+) Control the DLYB.
+@endverbatim
+  * @{
+  */
+
+/** @addtogroup DLYB_Control_Functions DLYB Control functions
+  * @{
+  */
+
+/**
+  * @brief  Set the Delay value configured on SEL and UNIT.
+  * @param  DLYBx: Pointer to DLYB instance.
+  * @param  pdlyb_cfg: Pointer to DLYB configuration structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: the Delay value is set.
+  *          - ERROR: the Delay value is not set.
+  */
+void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, const LL_DLYB_CfgTypeDef  *pdlyb_cfg)
+{
+  /* Check the DelayBlock instance */
+  assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
+
+  /* Enable the length sampling */
+  SET_BIT(DLYBx->CR, DLYB_CR_SEN);
+
+  /* Update the UNIT and SEL field */
+  DLYBx->CFGR = (pdlyb_cfg->PhaseSel) | ((pdlyb_cfg->Units) << DLYB_CFGR_UNIT_Pos);
+
+  /* Disable the length sampling */
+  CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN);
+}
+
+/**
+  * @brief  Get the Delay value configured on SEL and UNIT.
+  * @param  DLYBx: Pointer to DLYB instance.
+  * @param  pdlyb_cfg: Pointer to DLYB configuration structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: the Delay value is received.
+  *          - ERROR: the Delay value is not received.
+  */
+void LL_DLYB_GetDelay(const DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+  /* Check the DelayBlock instance */
+  assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
+
+  /* Fill the DelayBlock configuration structure with SEL and UNIT value */
+  pdlyb_cfg->Units = ((DLYBx->CFGR & DLYB_CFGR_UNIT) >> DLYB_CFGR_UNIT_Pos);
+  pdlyb_cfg->PhaseSel = (DLYBx->CFGR & DLYB_CFGR_SEL);
+}
+
+/**
+  * @brief  Get the clock period.
+  * @param  DLYBx: Pointer to DLYB instance.
+  * @param  pdlyb_cfg: Pointer to DLYB configuration structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: there is a valid period detected and stored in pdlyb_cfg.
+  *          - ERROR: there is no valid period detected.
+  */
+uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg)
+{
+  uint32_t i = 0U;
+  uint32_t nb ;
+  uint32_t lng ;
+  uint32_t tickstart;
+
+  /* Check the DelayBlock instance */
+  assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
+
+  /* Enable the length sampling */
+  SET_BIT(DLYBx->CR, DLYB_CR_SEN);
+
+  /* Delay line length detection */
+  while (i < DLYB_MAX_UNIT)
+  {
+    /* Set the Delay of the UNIT(s)*/
+    DLYBx->CFGR = DLYB_MAX_SELECT | (i << DLYB_CFGR_UNIT_Pos);
+
+    /* Waiting for a LNG valid value */
+    tickstart =  HAL_GetTick();
+    while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
+    {
+      if ((HAL_GetTick() - tickstart) >=  DLYB_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U)
+        {
+          return (uint32_t) HAL_TIMEOUT;
+        }
+      }
+    }
+
+    if ((DLYBx->CFGR & DLYB_LNG_10_0_MASK) != 0U)
+    {
+      if ((DLYBx->CFGR & (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)) != DLYB_LNG_11_10_MASK)
+      {
+        /* Delay line length is configured to one input clock period*/
+        break;
+      }
+    }
+    i++;
+  }
+
+  if (DLYB_MAX_UNIT != i)
+  {
+    /* Determine how many unit delays (nb) span one input clock period */
+    lng = (DLYBx->CFGR & DLYB_CFGR_LNG) >> 16U;
+    nb = 10U;
+    while ((nb > 0U) && ((lng >> nb) == 0U))
+    {
+      nb--;
+    }
+    if (nb != 0U)
+    {
+      pdlyb_cfg->PhaseSel = nb ;
+      pdlyb_cfg->Units = i ;
+
+      /* Disable the length sampling */
+      CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN);
+
+      return (uint32_t)SUCCESS;
+    }
+  }
+
+  /* Disable the length sampling */
+  CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN);
+
+  return (uint32_t)ERROR;
+
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */
+#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dma.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dma.c
new file mode 100644
index 000000000..149c6a501
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dma.c
@@ -0,0 +1,1264 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+ @verbatim
+  ==============================================================================
+                        ##### LL DMA driver acronyms #####
+  ==============================================================================
+  [..]  Acronyms table :
+                   =========================================
+                   || Acronym ||                          ||
+                   =========================================
+                   || SRC     ||  Source                  ||
+                   || DEST    ||  Destination             ||
+                   || ADDR    ||  Address                 ||
+                   || ADDRS   ||  Addresses               ||
+                   || INC     ||  Increment / Incremented ||
+                   || DEC     ||  Decrement / Decremented ||
+                   || BLK     ||  Block                   ||
+                   || RPT     ||  Repeat / Repeated       ||
+                   || TRIG    ||  Trigger                 ||
+                   =========================================
+ @endverbatim
+  ******************************************************************************
+  */
+
+#if defined (USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_dma.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if (defined (GPDMA1) || defined (HPDMA1))
+
+/** @addtogroup DMA_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DMA_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1)                && \
+                                                            (((Channel)  == LL_DMA_CHANNEL_0)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_1)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_2)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_3)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_4)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_5)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_6)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_7)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_8)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_9)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_10)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_11)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_12)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_13)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_14)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_15)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_ALL))) || \
+                                                           (((INSTANCE) == GPDMA1)                && \
+                                                            (((Channel)  == LL_DMA_CHANNEL_0)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_1)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_2)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_3)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_4)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_5)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_6)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_7)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_8)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_9)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_10)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_11)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_12)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_13)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_14)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_15)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_ALL))))
+
+#define IS_LL_HPDMA_CHANNEL_INSTANCE(INSTANCE, Channel)   (((INSTANCE) == HPDMA1)                && \
+                                                           (((Channel)  == LL_DMA_CHANNEL_0)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_1)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_2)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_3)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_4)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_5)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_6)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_7)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_8)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_9)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_10)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_11)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_12)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_13)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_14)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_15)))
+
+#define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel)   (((INSTANCE) == GPDMA1)                && \
+                                                           (((Channel)  == LL_DMA_CHANNEL_0)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_1)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_2)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_3)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_4)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_5)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_6)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_7)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_8)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_9)     || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_10)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_11)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_12)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_13)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_14)    || \
+                                                            ((Channel)  == LL_DMA_CHANNEL_15)))
+
+#define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel)  ((((INSTANCE) == HPDMA1)                && \
+                                                            (((Channel)  == LL_DMA_CHANNEL_12)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_13)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_14)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_15)))  || \
+                                                           (((INSTANCE) == GPDMA1)                && \
+                                                            (((Channel)  == LL_DMA_CHANNEL_12)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_13)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_14)    || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_15))))
+
+#define IS_LL_DMA_MODE(__VALUE__)                         (((__VALUE__) == LL_DMA_NORMAL) || \
+                                                           ((__VALUE__) == LL_DMA_PFCTRL))
+
+#define IS_LL_DMA_PFREQ_INSTANCE(INSTANCE, Channel)       ((((INSTANCE) == HPDMA1)                && \
+                                                            (((Channel)  == LL_DMA_CHANNEL_0)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_1)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_15)))  || \
+                                                           (((INSTANCE) == GPDMA1)                && \
+                                                            (((Channel)  == LL_DMA_CHANNEL_0)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_1)     || \
+                                                             ((Channel)  == LL_DMA_CHANNEL_15))))
+
+#define IS_LL_DMA_DIRECTION(__VALUE__)                    (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
+                                                           ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                           ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
+
+#define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__)               (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD)    || \
+                                                           ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
+                                                           ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
+
+#define IS_LL_DMA_BURST_LENGTH(__VALUE__)                 (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
+
+#define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__)               (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE)        || \
+                                                           ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD)    || \
+                                                           ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD)        || \
+                                                           ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_DOUBLEWORD))
+
+#define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__)              (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE)        || \
+                                                           ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD)    || \
+                                                           ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD)        || \
+                                                           ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_DOUBLEWORD))
+
+#define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__)           (((__VALUE__) == LL_DMA_SRC_FIXED) || \
+                                                           ((__VALUE__) == LL_DMA_SRC_INCREMENT))
+
+#define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__)          (((__VALUE__) == LL_DMA_DEST_FIXED) || \
+                                                           ((__VALUE__) == LL_DMA_DEST_INCREMENT))
+
+#define IS_LL_DMA_PRIORITY(__VALUE__)                     (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT)  || \
+                                                           ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT)  || \
+                                                           ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
+                                                           ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
+
+#define IS_LL_DMA_BLK_DATALENGTH(__VALUE__)                ((__VALUE__) <= 0xFFFFU)
+
+#define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__)               ((__VALUE__) <= 0x0EFFU)
+
+#define IS_LL_DMA_TRIGGER_MODE(__VALUE__)                 (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER)      || \
+                                                           ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER)  || \
+                                                           ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
+                                                           ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
+
+#define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__)             (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
+                                                           ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
+                                                           ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
+
+#define IS_LL_DMA_BLKHW_REQUEST(__VALUE__)                (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
+                                                           ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
+
+#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__)             ((__VALUE__) <= LL_HPDMA1_TRIGGER_EXTIT15_SYNC)
+
+#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__)             ((__VALUE__) <= LL_HPDMA1_REQUEST_I3C2_RS)
+
+#define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__)          (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER)         || \
+                                                           ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER)     || \
+                                                           ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
+                                                           ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
+
+#define IS_LL_DMA_DEST_WORD_EXCHANGE(__VALUE__)           (((__VALUE__) == LL_DMA_DEST_WORD_PRESERVE) || \
+                                                           ((__VALUE__) == LL_DMA_DEST_WORD_EXCHANGE))
+
+#define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__)       (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
+                                                           ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
+
+#define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__)           (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
+                                                           ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
+
+#define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__)            (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
+                                                           ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
+
+#define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__)          (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
+                                                           ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
+
+#define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__)           (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
+                                                           ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
+
+#define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__)          (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
+                                                           ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
+
+#define IS_LL_DMA_LINK_STEP_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
+                                                           ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
+
+#define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__)        (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
+                                                           ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__)       (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
+                                                           ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__)       ((__VALUE__) <= 0x1FFFU)
+
+#define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__)       (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
+                                                           ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__)      (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
+                                                           ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
+
+#define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__)      ((__VALUE__) <= 0xFFFFU)
+
+#define IS_LL_DMA_LINK_BASEADDR(__VALUE__)                (((__VALUE__) & 0xFFFFU) == 0U)
+
+#define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__)             (((__VALUE__) & 0x03U) == 0U)
+
+#define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__)       ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
+
+#define IS_LL_DMA_LINK_NODETYPE(__VALUE__)                (((__VALUE__) == LL_DMA_HPDMA_2D_NODE)     || \
+                                                           ((__VALUE__) == LL_DMA_HPDMA_LINEAR_NODE) || \
+                                                           ((__VALUE__) == LL_DMA_GPDMA_2D_NODE)     || \
+                                                           ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE))
+
+#if defined (CPU_IN_SECURE_STATE)
+#define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__)              (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
+                                                           ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
+
+#define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__)             (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
+                                                           ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
+
+#endif /* CPU_IN_SECURE_STATE */
+#define IS_LL_DMA_LIMIT_CHANNEL_INSTANCE(INSTANCE, Channel)   (((INSTANCE) == HPDMA1)               && \
+                                                               (((Channel)  == LL_DMA_CHANNEL_12)    || \
+                                                                ((Channel)  == LL_DMA_CHANNEL_13)    || \
+                                                                ((Channel)  == LL_DMA_CHANNEL_14)    || \
+                                                                ((Channel)  == LL_DMA_CHANNEL_15)))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief De-initialize the DMA registers to their default reset values.
+  * @note  This API is used for all available DMA channels.
+  * @note  To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+  *        helper macros :
+  *        @arg @ref LL_DMA_GET_INSTANCE
+  *        @arg @ref LL_DMA_GET_CHANNEL
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS : DMA registers are de-initialized.
+  *          - ERROR   : DMA registers are not de-initialized.
+  */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  DMA_Channel_TypeDef *tmp;
+  ErrorStatus status = SUCCESS;
+
+  /* Check the DMA Instance DMAx and Channel parameters */
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+  if (Channel == LL_DMA_CHANNEL_ALL)
+  {
+    if (DMAx == GPDMA1)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
+    }
+    else
+    {
+      /* Force reset of DMA clock */
+      LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_HPDMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_HPDMA1);
+    }
+  }
+  else
+  {
+    /* Get the DMA Channel Instance */
+    tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+    /* Suspend DMA channel */
+    LL_DMA_SuspendChannel(DMAx, Channel);
+
+    /* Disable the selected Channel */
+    LL_DMA_ResetChannel(DMAx, Channel);
+
+    /* Reset DMAx_Channely control register */
+    LL_DMA_WriteReg(tmp, CLBAR, 0U);
+
+    /* Reset DMAx_Channely control register */
+    LL_DMA_WriteReg(tmp, CCR, 0U);
+
+    /* Reset DMAx_Channely Configuration register */
+    LL_DMA_WriteReg(tmp, CTR1, 0U);
+
+    /* Reset DMAx_Channely transfer register 2 */
+    LL_DMA_WriteReg(tmp, CTR2, 0U);
+
+    /* Reset DMAx_Channely block number of data register */
+    LL_DMA_WriteReg(tmp, CBR1, 0U);
+
+    /* Reset DMAx_Channely source address register */
+    LL_DMA_WriteReg(tmp, CSAR, 0U);
+
+    /* Reset DMAx_Channely destination address register */
+    LL_DMA_WriteReg(tmp, CDAR, 0U);
+
+    /* Check DMA channel */
+    if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+    {
+      /* Reset DMAx_Channely transfer register 3 */
+      LL_DMA_WriteReg(tmp, CTR3, 0U);
+
+      /* Reset DMAx_Channely Block register 2 */
+      LL_DMA_WriteReg(tmp, CBR2, 0U);
+    }
+
+    /* Reset DMAx_Channely Linked list address register */
+    LL_DMA_WriteReg(tmp, CLLR, 0U);
+
+    /* Reset DMAx_Channely pending flags */
+    LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
+
+    /* Reset DMAx_Channely attribute */
+    LL_DMA_DisableChannelPrivilege(DMAx, Channel);
+
+#if defined (CPU_IN_SECURE_STATE)
+    LL_DMA_DisableChannelSecure(DMAx, Channel);
+#endif /* CPU_IN_SECURE_STATE */
+  }
+
+  return (uint32_t)status;
+}
+
+/**
+  * @brief Initialize the DMA registers according to the specified parameters
+  *        in DMA_InitStruct.
+  * @note  This API is used for all available DMA channels.
+  * @note  A software request transfer can be done once programming the direction
+  *        field in memory to memory value.
+  * @note  To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+  *        helper macros :
+  *        @arg @ref LL_DMA_GET_INSTANCE
+  *        @arg @ref LL_DMA_GET_CHANNEL
+  * @note   Warning if AXI port is selected with HPDMA, the maximum source (and destination) length should be less
+  *         than 17. Otherwise, an error will be returned and no initialization performed.
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS : DMA registers are initialized.
+  *          - ERROR   : Not applicable.
+  */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+  /* Check the DMA parameters from DMA_InitStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+
+  /* Check direction */
+  if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+  {
+    assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
+  }
+
+  assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
+  assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
+  assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
+  assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
+  assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+  assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
+  assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
+  assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
+  assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
+  assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
+  assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
+  assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
+  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+  if (DMA_InitStruct->Mode == LL_DMA_PFCTRL)
+  {
+    assert_param(IS_LL_DMA_PFREQ_INSTANCE(DMAx, Channel));
+  }
+
+  /* Check DMA instance */
+  if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
+  {
+    assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
+    assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
+    assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitStruct->DestWordExchange));
+    assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
+    assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
+    assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
+    assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
+    assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
+    assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
+  }
+
+  /* Check trigger polarity */
+  if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+  {
+    assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
+    assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
+  }
+
+  /* Check DMA channel */
+  if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+  {
+    assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount));
+    assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode));
+    assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode));
+    assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset));
+    assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset));
+    assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode));
+    assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode));
+    assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset));
+    assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset));
+  }
+
+  if (DMAx == HPDMA1)
+  {
+    if ((DMA_InitStruct->SrcAllocatedPort == LL_DMA_SRC_ALLOCATED_PORT0) &&
+        (DMA_InitStruct->SrcBurstLength > 16U))
+    {
+      return (uint32_t)ERROR;
+    }
+    if ((DMA_InitStruct->DestAllocatedPort == LL_DMA_DEST_ALLOCATED_PORT0) &&
+        (DMA_InitStruct->DestBurstLength > 16U))
+    {
+      return (uint32_t)ERROR;
+    }
+  }
+
+  /*-------------------------- DMAx CLBAR Configuration ------------------------
+   * Configure the Transfer linked list address with parameter :
+   * - LinkedListBaseAdd:                              DMA_CLBAR_LBA[31:16] bits
+   */
+  LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
+
+  /*-------------------------- DMAx CCR Configuration --------------------------
+   * Configure the control parameter :
+   * - LinkAllocatedPort:                              DMA_CCR_LAP bit
+   * - LinkStepMode:                                   DMA_CCR_LSM bit
+   * - Priority:                                       DMA_CCR_PRIO [23:22] bits
+   */
+  LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
+                       DMA_InitStruct->LinkAllocatedPort       | \
+                       DMA_InitStruct->LinkStepMode);
+
+  /*-------------------------- DMAx CTR1 Configuration -------------------------
+   * Configure the Data transfer  parameter :
+   * - DestAllocatedPort:                         DMA_CTR1_DAP bit
+   * - DestWordExchange:                          DMA_CTR1_DWX bit
+   * - DestHWordExchange:                         DMA_CTR1_DHX bit
+   * - DestByteExchange:                          DMA_CTR1_DBX bit
+   * - DestIncMode:                               DMA_CTR1_DINC bit
+   * - DestDataWidth:                             DMA_CTR1_DDW_LOG2 [17:16] bits
+   * - SrcAllocatedPort:                          DMA_CTR1_SAP bit
+   * - SrcByteExchange:                           DMA_CTR1_SBX bit
+   * - DataAlignment:                             DMA_CTR1_PAM [12:11] bits
+   * - SrcIncMode:                                DMA_CTR1_SINC bit
+   * - SrcDataWidth:                              DMA_CTR1_SDW_LOG2 [1:0] bits
+   * - SrcBurstLength:                            DMA_CTR1_SBL_1 [9:4] bits
+   * - DestBurstLength:                           DMA_CTR1_DBL_1 [25:20] bits
+   */
+  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
+                        DMA_InitStruct->DestWordExchange                 | \
+                        DMA_InitStruct->DestHWordExchange                | \
+                        DMA_InitStruct->DestByteExchange                 | \
+                        DMA_InitStruct->DestIncMode                      | \
+                        DMA_InitStruct->DestDataWidth                    | \
+                        DMA_InitStruct->SrcAllocatedPort                 | \
+                        DMA_InitStruct->SrcByteExchange                  | \
+                        DMA_InitStruct->DataAlignment                    | \
+                        DMA_InitStruct->SrcIncMode                       | \
+                        DMA_InitStruct->SrcDataWidth);
+  /* Check DMA instance */
+  if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
+  {
+    LL_DMA_ConfigBurstLength(DMAx, Channel,  DMA_InitStruct->SrcBurstLength,
+                             DMA_InitStruct->DestBurstLength);
+  }
+
+  /*-------------------------- DMAx CTR2 Configuration -------------------------
+   * Configure the channel transfer parameter :
+   * - TransferEventMode:                          DMA_CTR2_TCEM [31:30] bits
+   * - TriggerPolarity:                            DMA_CTR2_TRIGPOL [25:24] bits
+   * - TriggerMode:                                DMA_CTR2_TRIGM  [15:14] bits
+   * - BlkHWRequest:                               DMA_CTR2_BREQ bit
+   * - Mode:                                       DMA_CTR2_PFREQ bit
+   * - Direction:                                  DMA_CTR2_DREQ bit
+   * - Direction:                                  DMA_CTR2_SWREQ bit
+   * - TriggerSelection:                           DMA_CTR2_TRIGSEL [21:16] bits
+   * - Request:                                    DMA_CTR2_REQSEL [6:0] bits
+   */
+  LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
+                               DMA_InitStruct->TriggerPolarity                  | \
+                               DMA_InitStruct->BlkHWRequest                     | \
+                               DMA_InitStruct->Mode                             | \
+                               DMA_InitStruct->Direction);
+
+  /* Check direction */
+  if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+  {
+    LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
+  }
+
+  /* Check trigger polarity */
+  if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+  {
+    LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
+    LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
+  }
+
+  /*-------------------------- DMAx CBR1 Configuration -------------------------
+   * Configure the Transfer Block counters and update mode with parameter :
+   * - BlkDataLength:                                   DMA_CBR1_BNDT[15:0] bits
+   * - BlkRptCount:                                     DMA_CBR1_BRC[26:16] bits
+   *   BlkRptCount field is supported only by 2D addressing channels.
+   * - BlkRptSrcAddrUpdateMode:                                DMA_CBR1_BRSDEC bit
+   *   BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
+   * - BlkRptDestAddrUpdateMode:                               DMA_CBR1_BRDDEC bit
+   *   BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
+   * - SrcAddrUpdateMode:                                      DMA_CBR1_SDEC bit
+   *   SrcAddrUpdateMode field is supported only by 2D addressing channels.
+   * - DestAddrUpdateMode:                                     DMA_CBR1_DDEC bit
+   *   DestAddrUpdateMode field is supported only by 2D addressing channels.
+   */
+  LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
+
+  /* Check DMA channel */
+  if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+  {
+    LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount);
+    LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode  | \
+                                  DMA_InitStruct->BlkRptDestAddrUpdateMode                | \
+                                  DMA_InitStruct->SrcAddrUpdateMode                       | \
+                                  DMA_InitStruct->DestAddrUpdateMode);
+  }
+
+  /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
+   * Configure the Transfer source address with parameter :
+   * - SrcAddress:                                        DMA_CSAR_SA[31:0] bits
+   * - DestAddress:                                       DMA_CDAR_DA[31:0] bits
+   */
+  LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
+
+  /* Check DMA channel */
+  if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
+  {
+    /*------------------------ DMAx CTR3 Configuration -------------------------
+     * Configure the Transfer Block counters and update mode with parameter :
+     * - SrcAddrOffset:                                 DMA_CTR3_SAO[28:16] bits
+     *   SrcAddrOffset field is supported only by 2D addressing channels.
+     * - DestAddrOffset:                                DMA_CTR3_DAO[12:0] bits
+     *   DestAddrOffset field is supported only by 2D addressing channels.
+     */
+    LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset);
+
+    /*------------------------ DMAx CBR2 Configuration -----------------------
+     * Configure the Transfer Block counters and update mode with parameter :
+     * - BlkRptSrcAddrOffset:                         DMA_CBR2_BRSAO[15:0] bits
+     *   BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
+     * - BlkRptDestAddrOffset:                        DMA_CBR2_BRDAO[31:16] bits
+     *   BlkRptDestAddrOffset field is supported only by 2D addressing channels.
+     */
+    LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset,
+                                       DMA_InitStruct->BlkRptDestAddrOffset);
+  }
+
+  /*-------------------------- DMAx CLLR Configuration -------------------------
+   * Configure the Transfer linked list address with parameter :
+   * - DestAddrOffset:                                    DMA_CLLR_LA[15:2] bits
+   */
+  LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
+
+  return (uint32_t)SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval None.
+  */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Set DMA_InitStruct fields to default values */
+  DMA_InitStruct->SrcAddress               = 0x00000000U;
+  DMA_InitStruct->DestAddress              = 0x00000000U;
+  DMA_InitStruct->Direction                = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
+  DMA_InitStruct->BlkHWRequest             = LL_DMA_HWREQUEST_SINGLEBURST;
+  DMA_InitStruct->DataAlignment            = LL_DMA_DATA_ALIGN_ZEROPADD;
+  DMA_InitStruct->SrcBurstLength           = 1U;
+  DMA_InitStruct->DestBurstLength          = 1U;
+  DMA_InitStruct->SrcDataWidth             = LL_DMA_SRC_DATAWIDTH_BYTE;
+  DMA_InitStruct->DestDataWidth            = LL_DMA_DEST_DATAWIDTH_BYTE;
+  DMA_InitStruct->SrcIncMode               = LL_DMA_SRC_FIXED;
+  DMA_InitStruct->DestIncMode              = LL_DMA_DEST_FIXED;
+  DMA_InitStruct->Priority                 = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
+  DMA_InitStruct->BlkDataLength            = 0x00000000U;
+  DMA_InitStruct->Mode                     = LL_DMA_NORMAL;
+  DMA_InitStruct->BlkRptCount              = 0x00000000U;
+  DMA_InitStruct->TriggerMode              = LL_DMA_TRIGM_BLK_TRANSFER;
+  DMA_InitStruct->TriggerPolarity          = LL_DMA_TRIG_POLARITY_MASKED;
+  DMA_InitStruct->TriggerSelection         = 0x00000000U;
+  DMA_InitStruct->Request                  = 0x00000000U;
+  DMA_InitStruct->TransferEventMode        = LL_DMA_TCEM_BLK_TRANSFER;
+  DMA_InitStruct->DestWordExchange         = LL_DMA_DEST_WORD_PRESERVE;
+  DMA_InitStruct->DestHWordExchange        = LL_DMA_DEST_HALFWORD_PRESERVE;
+  DMA_InitStruct->DestByteExchange         = LL_DMA_DEST_BYTE_PRESERVE;
+  DMA_InitStruct->SrcByteExchange          = LL_DMA_SRC_BYTE_PRESERVE;
+  DMA_InitStruct->SrcAllocatedPort         = LL_DMA_SRC_ALLOCATED_PORT0;
+  DMA_InitStruct->DestAllocatedPort        = LL_DMA_DEST_ALLOCATED_PORT0;
+  DMA_InitStruct->LinkAllocatedPort        = LL_DMA_LINK_ALLOCATED_PORT0;
+  DMA_InitStruct->LinkStepMode             = LL_DMA_LSM_FULL_EXECUTION;
+  DMA_InitStruct->SrcAddrUpdateMode        = LL_DMA_BURST_SRC_ADDR_INCREMENT;
+  DMA_InitStruct->DestAddrUpdateMode       = LL_DMA_BURST_DEST_ADDR_INCREMENT;
+  DMA_InitStruct->SrcAddrOffset            = 0x00000000U;
+  DMA_InitStruct->DestAddrOffset           = 0x00000000U;
+  DMA_InitStruct->BlkRptSrcAddrUpdateMode  = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
+  DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
+  DMA_InitStruct->BlkRptSrcAddrOffset      = 0x00000000U;
+  DMA_InitStruct->BlkRptDestAddrOffset     = 0x00000000U;
+  DMA_InitStruct->LinkedListBaseAddr       = 0x00000000U;
+  DMA_InitStruct->LinkedListAddrOffset     = 0x00000000U;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
+  * @param  DMA_InitLinkedListStruct Pointer to
+  *         a @ref LL_DMA_InitLinkedListTypeDef structure.
+  * @retval None.
+  */
+void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
+{
+  /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
+  DMA_InitLinkedListStruct->Priority          = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
+  DMA_InitLinkedListStruct->LinkStepMode      = LL_DMA_LSM_FULL_EXECUTION;
+  DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
+  DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
+}
+
+/**
+  * @brief De-initialize the DMA linked list.
+  * @note  This API is used for all available DMA channels.
+  * @note  To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+  *        helper macros :
+  *        @arg @ref LL_DMA_GET_INSTANCE
+  *        @arg @ref LL_DMA_GET_CHANNEL
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS : DMA registers are de-initialized.
+  *          - ERROR   : DMA registers are not de-initialized.
+  */
+uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  return LL_DMA_DeInit(DMAx, Channel);
+}
+
+/**
+  * @brief Initialize the DMA linked list according to the specified parameters
+  *        in LL_DMA_InitLinkedListTypeDef.
+  * @note  This API is used for all available DMA channels.
+  * @note  To convert DMAx_Channely Instance to DMAx Instance and Channely, use
+  *        helper macros :
+  *        @arg @ref LL_DMA_GET_INSTANCE
+  *        @arg @ref LL_DMA_GET_CHANNEL
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_8
+  *         @arg @ref LL_DMA_CHANNEL_9
+  *         @arg @ref LL_DMA_CHANNEL_10
+  *         @arg @ref LL_DMA_CHANNEL_11
+  *         @arg @ref LL_DMA_CHANNEL_12
+  *         @arg @ref LL_DMA_CHANNEL_13
+  *         @arg @ref LL_DMA_CHANNEL_14
+  *         @arg @ref LL_DMA_CHANNEL_15
+  * @param  DMA_InitLinkedListStruct pointer to
+  *         a @ref LL_DMA_InitLinkedListTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS : DMA registers are initialized.
+  *          - ERROR   : Not applicable.
+  */
+uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
+{
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+  /* Check the DMA parameters from DMA_InitLinkedListStruct */
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
+  assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
+  assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
+  /* Check DMA instance */
+  if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
+  {
+    assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
+  }
+
+  /*-------------------------- DMAx CCR Configuration --------------------------
+   * Configure the control parameter :
+   * - LinkAllocatedPort:                              DMA_CCR_LAP bit
+   *   LinkAllocatedPort field is supported only by GPDMA channels.
+   * - LinkStepMode:                                   DMA_CCR_LSM bit
+   * - Priority:                                       DMA_CCR_PRIO [23:22] bits
+   */
+  LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
+                       DMA_InitLinkedListStruct->LinkAllocatedPort       | \
+                       DMA_InitLinkedListStruct->LinkStepMode);
+
+  /*-------------------------- DMAx CTR2 Configuration -------------------------
+   * Configure the channel transfer parameter :
+   * - TransferEventMode:                          DMA_CTR2_TCEM [31:30] bits
+   */
+  LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
+
+  return (uint32_t)SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitNodeTypeDef field to default value.
+  * @param  DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
+  *         structure.
+  * @retval None.
+  */
+void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
+{
+  /* Set DMA_InitNodeStruct fields to default values */
+#if defined (CPU_IN_SECURE_STATE)
+  DMA_InitNodeStruct->DestSecure               = LL_DMA_CHANNEL_DEST_NSEC;
+#endif /* CPU_IN_SECURE_STATE */
+  DMA_InitNodeStruct->DestAllocatedPort        = LL_DMA_DEST_ALLOCATED_PORT0;
+  DMA_InitNodeStruct->DestWordExchange         = LL_DMA_DEST_WORD_PRESERVE;
+  DMA_InitNodeStruct->DestHWordExchange        = LL_DMA_DEST_HALFWORD_PRESERVE;
+  DMA_InitNodeStruct->DestByteExchange         = LL_DMA_DEST_BYTE_PRESERVE;
+  DMA_InitNodeStruct->DestBurstLength          = 1U;
+  DMA_InitNodeStruct->DestIncMode              = LL_DMA_DEST_FIXED;
+  DMA_InitNodeStruct->DestDataWidth            = LL_DMA_DEST_DATAWIDTH_BYTE;
+#if defined (CPU_IN_SECURE_STATE)
+  DMA_InitNodeStruct->SrcSecure                = LL_DMA_CHANNEL_SRC_NSEC;
+#endif /* CPU_IN_SECURE_STATE */
+  DMA_InitNodeStruct->SrcAllocatedPort         = LL_DMA_SRC_ALLOCATED_PORT0;
+  DMA_InitNodeStruct->SrcByteExchange          = LL_DMA_SRC_BYTE_PRESERVE;
+  DMA_InitNodeStruct->DataAlignment            = LL_DMA_DATA_ALIGN_ZEROPADD;
+  DMA_InitNodeStruct->SrcBurstLength           = 1U;
+  DMA_InitNodeStruct->SrcIncMode               = LL_DMA_SRC_FIXED;
+  DMA_InitNodeStruct->SrcDataWidth             = LL_DMA_SRC_DATAWIDTH_BYTE;
+  DMA_InitNodeStruct->TransferEventMode        = LL_DMA_TCEM_BLK_TRANSFER;
+  DMA_InitNodeStruct->TriggerPolarity          = LL_DMA_TRIG_POLARITY_MASKED;
+  DMA_InitNodeStruct->TriggerSelection         = 0x00000000U;
+  DMA_InitNodeStruct->TriggerMode              = LL_DMA_TRIGM_BLK_TRANSFER;
+  DMA_InitNodeStruct->BlkHWRequest             = LL_DMA_HWREQUEST_SINGLEBURST;
+  DMA_InitNodeStruct->Direction                = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
+  DMA_InitNodeStruct->Request                  = 0x00000000U;
+  DMA_InitNodeStruct->Mode                     = LL_DMA_NORMAL;
+  DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
+  DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode  = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
+  DMA_InitNodeStruct->DestAddrUpdateMode       = LL_DMA_BURST_DEST_ADDR_INCREMENT;
+  DMA_InitNodeStruct->SrcAddrUpdateMode        = LL_DMA_BURST_SRC_ADDR_INCREMENT;
+  DMA_InitNodeStruct->BlkRptCount              = 0x00000000U;
+  DMA_InitNodeStruct->BlkDataLength            = 0x00000000U;
+  DMA_InitNodeStruct->SrcAddress               = 0x00000000U;
+  DMA_InitNodeStruct->DestAddress              = 0x00000000U;
+  DMA_InitNodeStruct->DestAddrOffset           = 0x00000000U;
+  DMA_InitNodeStruct->SrcAddrOffset            = 0x00000000U;
+  DMA_InitNodeStruct->BlkRptDestAddrOffset     = 0x00000000U;
+  DMA_InitNodeStruct->BlkRptSrcAddrOffset      = 0x00000000U;
+  DMA_InitNodeStruct->UpdateRegisters          = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
+                                                  LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
+                                                  LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \
+                                                  LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR);
+  DMA_InitNodeStruct->NodeType                 = LL_DMA_GPDMA_LINEAR_NODE;
+}
+
+/**
+  * @brief  Initializes DMA linked list node according to the specified
+  *         parameters in the DMA_InitNodeStruct.
+  * @note   Warning: the maximum allowed AXI burst length shall not exceed 16.
+  *         Otherwise, an error will be returned and no initialization performed.
+  * @param  DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
+  *         that contains linked list node
+  *         registers configurations.
+  * @param  pNode Pointer to linked list node to fill according to
+  *         LL_DMA_LinkNodeTypeDef parameters.
+  * @retval None
+  */
+uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
+{
+  uint32_t reg_counter = 0U;
+
+  /* Check the DMA Node type */
+  assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
+
+  /* Check the DMA parameters from DMA_InitNodeStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
+
+  /* Check direction */
+  if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+  {
+    assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
+  }
+
+  assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
+  assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
+  assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
+  assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
+  assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
+  assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
+  assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
+  assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
+  assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
+  assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
+  assert_param(IS_LL_DMA_MODE(DMA_InitNodeStruct->Mode));
+
+#if defined (CPU_IN_SECURE_STATE)
+  assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
+  assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
+#endif /* CPU_IN_SECURE_STATE */
+
+  /* Check trigger polarity */
+  if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+  {
+    assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
+    assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
+  }
+
+  {
+    assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
+    assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));
+    assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitNodeStruct->DestWordExchange));
+    assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
+    assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
+    assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
+    assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
+    assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
+  }
+
+  /* Check DMA channel */
+  if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
+      (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
+  {
+    assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount));
+    assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode));
+    assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode));
+    assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset));
+    assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset));
+    assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode));
+    assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode));
+    assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset));
+    assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset));
+  }
+
+  if ((DMA_InitNodeStruct->NodeType & (LL_DMA_HPDMA_2D_NODE | LL_DMA_HPDMA_LINEAR_NODE)) != 0U)
+  {
+    if (((DMA_InitNodeStruct->SrcAllocatedPort & DMA_CTR1_SAP) == LL_DMA_SRC_ALLOCATED_PORT0) &&
+        (DMA_InitNodeStruct->SrcBurstLength > 16U))
+    {
+      return (uint32_t)ERROR;
+    }
+    if (((DMA_InitNodeStruct->DestAllocatedPort & DMA_CTR1_DAP) == LL_DMA_DEST_ALLOCATED_PORT0) &&
+        (DMA_InitNodeStruct->DestBurstLength > 16U))
+    {
+      return (uint32_t)ERROR;
+    }
+  }
+
+  /* Check if CTR1 register update is enabled */
+  if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
+  {
+    /*-------------------------- DMAx CTR1 Configuration -----------------------
+    * Configure the Data transfer  parameter :
+    * - DestAllocatedPort:                        DMA_CTR1_DAP bit
+    * - DestWordExchange:                         DMA_CTR1_DWX bit
+    * - DestHWordExchange:                        DMA_CTR1_DHX bit
+    * - DestByteExchange:                         DMA_CTR1_DBX bit
+    * - DestIncMode:                              DMA_CTR1_DINC bit
+    * - DestDataWidth:                            DMA_CTR1_DDW_LOG2 [17:16] bits
+    * - SrcAllocatedPort:                         DMA_CTR1_SAP bit
+    * - SrcByteExchange:                          DMA_CTR1_SBX bit
+    * - DataAlignment:                            DMA_CTR1_PAM [12:11] bits
+    * - SrcIncMode:                               DMA_CTR1_SINC bit
+    * - SrcDataWidth:                             DMA_CTR1_SDW_LOG2 [1:0] bits
+    * - SrcBurstLength:                           DMA_CTR1_SBL_1 [9:4] bits
+    * - DestBurstLength:                          DMA_CTR1_DBL_1 [25:20] bits
+    */
+
+    pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode   | \
+                                         DMA_InitNodeStruct->DestDataWidth | \
+                                         DMA_InitNodeStruct->DataAlignment | \
+                                         DMA_InitNodeStruct->SrcIncMode    | \
+                                         DMA_InitNodeStruct->SrcDataWidth);
+
+#if defined (CPU_IN_SECURE_STATE)
+    pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
+                                          DMA_InitNodeStruct->SrcSecure);
+#endif /* CPU_IN_SECURE_STATE */
+
+    /* Update CTR1 register fields */
+    pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort                              | \
+                                          DMA_InitNodeStruct->DestWordExchange                               | \
+                                          DMA_InitNodeStruct->DestHWordExchange                              | \
+                                          DMA_InitNodeStruct->DestByteExchange                               | \
+                                          ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
+                                          DMA_InitNodeStruct->SrcAllocatedPort                               | \
+                                          DMA_InitNodeStruct->SrcByteExchange                                | \
+                                          ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
+
+    /* Increment counter for the next register */
+    reg_counter++;
+  }
+
+
+  /* Check if CTR2 register update is enabled */
+  if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
+  {
+    /*-------------------------- DMAx CTR2 Configuration -----------------------
+     * Configure the channel transfer parameter :
+     * - TransferEventMode:                        DMA_CTR2_TCEM [31:30] bits
+     * - TriggerPolarity:                          DMA_CTR2_TRIGPOL [25:24] bits
+     * - TriggerMode:                              DMA_CTR2_TRIGM  [15:14] bits
+     * - Mode:                                     DMA_CTR2_PFREQ bit
+     * - BlkHWRequest:                             DMA_CTR2_BREQ bit
+     * - Direction:                                DMA_CTR2_DREQ bit
+     * - Direction:                                DMA_CTR2_SWREQ bit
+     * - TriggerSelection:                         DMA_CTR2_TRIGSEL [21:16] bits
+     * - Request:                                  DMA_CTR2_REQSEL [6:0] bits
+     */
+    pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
+                                         DMA_InitNodeStruct->TriggerPolarity   | \
+                                         DMA_InitNodeStruct->BlkHWRequest      | \
+                                         DMA_InitNodeStruct->Mode              | \
+                                         DMA_InitNodeStruct->Direction);
+
+    /* Check direction */
+    if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
+    {
+      pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
+    }
+
+    /* Check trigger polarity */
+    if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
+    {
+      pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
+                                             DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
+    }
+
+
+    /* Increment counter for the next register */
+    reg_counter++;
+  }
+
+  /* Check if CBR1 register update is enabled */
+  if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
+  {
+    /*-------------------------- DMAx CBR1 Configuration -----------------------
+     * Configure the Transfer Block counters and update mode with parameter :
+     * - BlkDataLength:                                 DMA_CBR1_BNDT[15:0] bits
+     * - BlkRptCount:                                   DMA_CBR1_BRC[26:16] bits
+     *   BlkRptCount field is supported only by 2D addressing channels.
+     * - BlkRptSrcAddrUpdateMode:                              DMA_CBR1_BRSDEC bit
+     *   BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
+     * - BlkRptDestAddrUpdateMode:                             DMA_CBR1_BRDDEC bit
+     *   BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
+     * - SrcAddrUpdateMode:                                    DMA_CBR1_SDEC bit
+     *   SrcAddrUpdateMode field is supported only by 2D addressing channels.
+     * - DestAddrUpdateMode:                                   DMA_CBR1_DDEC bit
+     *   DestAddrUpdateMode field is supported only by 2D addressing channels.
+     */
+    pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
+
+    /* Update CBR1 register fields for 2D addressing channels */
+    if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
+        (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
+    {
+      pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \
+                                            DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode  | \
+                                            DMA_InitNodeStruct->DestAddrUpdateMode       | \
+                                            DMA_InitNodeStruct->SrcAddrUpdateMode        | \
+                                            ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC));
+    }
+
+    /* Increment counter for the next register */
+    reg_counter++;
+  }
+
+  /* Check if CSAR register update is enabled */
+  if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
+  {
+    /*-------------------------- DMAx CSAR Configuration -----------------------
+     * Configure the Transfer Block counters and update mode with parameter :
+     * - SrcAddress:                                         DMA_CSAR_SA[31:0] bits
+     */
+    pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
+
+    /* Increment counter for the next register */
+    reg_counter++;
+  }
+
+
+  /* Check if CDAR register update is enabled */
+  if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
+  {
+    /*-------------------------- DMAx CDAR Configuration -----------------------
+     * Configure the Transfer Block counters and update mode with parameter :
+     * - DestAddress:                                        DMA_CDAR_DA[31:0] bits
+     */
+    pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
+
+    /* Increment counter for the next register */
+    reg_counter++;
+  }
+
+  /* Update CTR3 register fields for 2D addressing channels */
+  if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
+  {
+    /* Check if CTR3 register update is enabled */
+    if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3)
+    {
+      /*-------------------------- DMAx CTR3 Configuration ---------------------
+      * Configure the Block counters and update mode with parameter :
+      * - DestAddressOffset:                             DMA_CTR3_DAO[12:0] bits
+      *   DestAddressOffset field is supported only by 2D addressing channels.
+      * - SrcAddressOffset:                              DMA_CTR3_SAO[12:0] bits
+      *   SrcAddressOffset field is supported only by 2D addressing channels.
+      */
+      pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \
+                                           ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
+
+      /* Increment counter for the next register */
+      reg_counter++;
+    }
+  }
+
+
+  /* Update CBR2 register fields for 2D addressing channels */
+  if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
+  {
+    /* Check if CBR2 register update is enabled */
+    if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2)
+    {
+      /*-------------------------- DMAx CBR2 Configuration ---------------------
+      * Configure the Block counters and update mode with parameter :
+      * - BlkRptDestAddrOffset:                       DMA_CBR2_BRDAO[31:16] bits
+      *   BlkRptDestAddrOffset field is supported only by 2D addressing channels.
+      * - BlkRptSrcAddrOffset:                        DMA_CBR2_BRSAO[15:0] bits
+      *   BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
+      */
+      pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \
+                                           ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \
+                                            DMA_CBR2_BRDAO));
+
+      /* Increment counter for the next register */
+      reg_counter++;
+    }
+  }
+
+  /* Check if CLLR register update is enabled */
+  if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
+  {
+    /*-------------------------- DMAx CLLR Configuration -----------------------
+    * Configure the Transfer Block counters and update mode with parameter :
+    * - UpdateRegisters                                         DMA_CLLR_UT1 bit
+    * - UpdateRegisters                                         DMA_CLLR_UT2 bit
+    * - UpdateRegisters                                         DMA_CLLR_UB1 bit
+    * - UpdateRegisters                                         DMA_CLLR_USA bit
+    * - UpdateRegisters                                         DMA_CLLR_UDA bit
+    * - UpdateRegisters                                         DMA_CLLR_UT3 bit
+    *   DMA_CLLR_UT3 bit is discarded for linear addressing channels.
+    * - UpdateRegisters                                         DMA_CLLR_UB2 bit
+    *   DMA_CLLR_UB2 bit is discarded for linear addressing channels.
+    * - UpdateRegisters                                         DMA_CLLR_ULL bit
+    */
+    pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
+                                                                                 DMA_CLLR_UB1 | DMA_CLLR_USA | \
+                                                                                 DMA_CLLR_UDA | DMA_CLLR_ULL)));
+
+    /* Update CLLR register fields for 2D addressing channels */
+    if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
+        (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
+    {
+      pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2));
+    }
+  }
+  else
+  {
+    /* Reset of the CLLR of the node being created */
+    pNode->LinkRegisters[reg_counter] = 0U;
+  }
+
+  return (uint32_t)SUCCESS;
+}
+
+/**
+  * @brief  Connect Linked list Nodes.
+  * @param  pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
+  * @param  PrevNodeCLLRIdx Offset of Previous Node CLLR register.
+  *         This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
+  * @param  pNewLinkNode Pointer to new Linked list.
+  * @param  NewNodeCLLRIdx Offset of New Node CLLR register.
+  *         This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
+  * @retval None
+  */
+void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
+                            LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
+{
+  pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA)                        | \
+                                                   (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1  | \
+                                                       DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
+                                                       DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)));
+}
+
+/**
+  * @brief  Disconnect the next linked list node.
+  * @param  pLinkNode Pointer to linked list node to be disconnected from the next one.
+  * @param  LinkNodeCLLRIdx Offset of Link Node CLLR register.
+  * @retval None.
+  */
+void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
+{
+  pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* GPDMA1 || HPDMA1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dma2d.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dma2d.c
new file mode 100644
index 000000000..34f88138c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_dma2d.c
@@ -0,0 +1,633 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_dma2d.c
+  * @author  MCD Application Team
+  * @brief   DMA2D LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_dma2d.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif  /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA2D)
+
+/** @addtogroup DMA2D_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants
+  * @{
+  */
+#define LL_DMA2D_COLOR            0xFFU                                      /*!< Maximum output color setting                   */
+#define LL_DMA2D_NUMBEROFLINES    DMA2D_NLR_NL                               /*!< Maximum number of lines                        */
+#define LL_DMA2D_NUMBEROFPIXELS   (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos)         /*!< Maximum number of pixels per lines             */
+#define LL_DMA2D_OFFSET_MAX       0x3FFFU                                    /*!< Maximum output line offset expressed in pixels */
+#define LL_DMA2D_CLUTSIZE_MAX     0xFFU                                      /*!< Maximum CLUT size                              */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA2D_MODE(MODE)          (((MODE) == LL_DMA2D_MODE_M2M)                      || \
+                                         ((MODE) == LL_DMA2D_MODE_M2M_PFC)                  || \
+                                         ((MODE) == LL_DMA2D_MODE_M2M_BLEND)                || \
+                                         ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG) || \
+                                         ((MODE) == LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG) || \
+                                         ((MODE) == LL_DMA2D_MODE_R2M))
+
+#define IS_LL_DMA2D_OCMODE(MODE_ARGB)   (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \
+                                         ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444))
+
+#define IS_LL_DMA2D_GREEN(GREEN)        ((GREEN) <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_RED(RED)            ((RED)   <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_BLUE(BLUE)          ((BLUE)  <= LL_DMA2D_COLOR)
+#define IS_LL_DMA2D_ALPHA(ALPHA)        ((ALPHA) <= LL_DMA2D_COLOR)
+
+#define IS_LL_DMA2D_OFFSET_MODE(MODE)   (((MODE) == LL_DMA2D_LINE_OFFSET_PIXELS) || \
+                                         ((MODE) == LL_DMA2D_LINE_OFFSET_BYTES))
+
+#define IS_LL_DMA2D_OFFSET(OFFSET)      ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
+
+#define IS_LL_DMA2D_LINE(LINES)         ((LINES)  <= LL_DMA2D_NUMBEROFLINES)
+#define IS_LL_DMA2D_PIXEL(PIXELS)       ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
+
+#define IS_LL_DMA2D_SWAP_MODE(MODE)     (((MODE) == LL_DMA2D_SWAP_MODE_REGULAR) || \
+                                         ((MODE) == LL_DMA2D_SWAP_MODE_TWO_BY_TWO))
+
+#define IS_LL_DMA2D_ALPHAINV(ALPHA)     (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \
+                                         ((ALPHA) == LL_DMA2D_ALPHA_INVERTED))
+
+#define IS_LL_DMA2D_RBSWAP(RBSWAP)      (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \
+                                         ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP))
+
+#define IS_LL_DMA2D_LCMODE(MODE_ARGB)   (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565)   || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8)       || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44)     || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88)     || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4)       || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8)       || \
+                                         ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4))
+
+#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \
+                                          ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888))
+
+#define IS_LL_DMA2D_CLUTSIZE(SIZE)      ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
+
+#define IS_LL_DMA2D_ALPHAMODE(MODE)     (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
+                                         ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE)  || \
+                                         ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
+
+#define IS_LL_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == LL_DMA2D_CSS_444) || \
+                                              ((CSS) == LL_DMA2D_CSS_422) || \
+                                              ((CSS) == LL_DMA2D_CSS_420))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA2D_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
+  * @{
+  */
+
+/**
+  * @brief  De-initialize DMA2D registers (registers restored to their default values).
+  * @param  DMA2Dx DMA2D Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA2D registers are de-initialized
+  *          - ERROR: DMA2D registers are not de-initialized
+  */
+ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+
+  if (DMA2Dx == DMA2D)
+  {
+    /* Force reset of DMA2D clock */
+    LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_DMA2D);
+
+    /* Release reset of DMA2D clock */
+    LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_DMA2D);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
+  * @note   DMA2D transfers must be disabled to set initialization bits in configuration registers,
+  *         otherwise ERROR result is returned.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DMA2D_InitStruct  pointer to a LL_DMA2D_InitTypeDef structure
+  *         that contains the configuration information for the specified DMA2D peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
+  *          - ERROR: Issue occurred during DMA2D registers initialization
+  */
+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  LL_DMA2D_ColorTypeDef dma2d_colorstruct;
+  uint32_t tmp;
+  uint32_t tmp1;
+  uint32_t tmp2;
+  uint32_t regMask;
+  uint32_t regValue;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode));
+  assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode));
+  assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
+  assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
+  assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen));
+  assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed));
+  assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue));
+  assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha));
+  assert_param(IS_LL_DMA2D_SWAP_MODE(DMA2D_InitStruct->OutputSwapMode));
+  assert_param(IS_LL_DMA2D_OFFSET_MODE(DMA2D_InitStruct->LineOffsetMode));
+  assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset));
+  assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode));
+  assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode));
+
+  /* DMA2D transfers must be disabled to configure bits in initialization registers */
+  tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx);
+  tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx);
+  tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx);
+  if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U))
+  {
+    /* DMA2D CR register configuration -------------------------------------------*/
+    MODIFY_REG(DMA2Dx->CR, (DMA2D_CR_MODE | DMA2D_CR_LOM), \
+               (DMA2D_InitStruct->Mode | DMA2D_InitStruct->LineOffsetMode));
+
+    /* DMA2D OPFCCR register configuration ---------------------------------------*/
+    regMask = DMA2D_OPFCCR_CM;
+    regValue = DMA2D_InitStruct->ColorMode;
+
+    regMask |= DMA2D_OPFCCR_SB;
+    regValue |= DMA2D_InitStruct->OutputSwapMode;
+
+    regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI);
+    regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode);
+
+
+    MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue);
+
+    /* DMA2D OOR register configuration ------------------------------------------*/
+    LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
+
+    /* DMA2D NLR register configuration ------------------------------------------*/
+    LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines);
+
+    /* DMA2D OMAR register configuration ------------------------------------------*/
+    LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
+
+    /* DMA2D OCOLR register configuration ------------------------------------------*/
+    dma2d_colorstruct.ColorMode   = DMA2D_InitStruct->ColorMode;
+    dma2d_colorstruct.OutputBlue  = DMA2D_InitStruct->OutputBlue;
+    dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
+    dma2d_colorstruct.OutputRed   = DMA2D_InitStruct->OutputRed;
+    dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
+    LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct);
+
+    status = SUCCESS;
+  }
+  /* If DMA2D transfers are not disabled, return ERROR */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
+  * @param DMA2D_InitStruct  pointer to a @ref LL_DMA2D_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
+{
+  /* Set DMA2D_InitStruct fields to default values */
+  DMA2D_InitStruct->Mode                = LL_DMA2D_MODE_M2M;
+  DMA2D_InitStruct->ColorMode           = LL_DMA2D_OUTPUT_MODE_ARGB8888;
+  DMA2D_InitStruct->NbrOfLines          = 0x0U;
+  DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
+  DMA2D_InitStruct->LineOffsetMode      = LL_DMA2D_LINE_OFFSET_PIXELS;
+  DMA2D_InitStruct->LineOffset          = 0x0U;
+  DMA2D_InitStruct->OutputBlue          = 0x0U;
+  DMA2D_InitStruct->OutputGreen         = 0x0U;
+  DMA2D_InitStruct->OutputRed           = 0x0U;
+  DMA2D_InitStruct->OutputAlpha         = 0x0U;
+  DMA2D_InitStruct->OutputMemoryAddress = 0x0U;
+  DMA2D_InitStruct->OutputSwapMode      = LL_DMA2D_SWAP_MODE_REGULAR;
+  DMA2D_InitStruct->AlphaInversionMode  = LL_DMA2D_ALPHA_REGULAR;
+  DMA2D_InitStruct->RBSwapMode          = LL_DMA2D_RB_MODE_REGULAR;
+}
+
+/**
+  * @brief  Configure the foreground or background according to the specified parameters
+  *         in the LL_DMA2D_LayerCfgTypeDef structure.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DMA2D_LayerCfg  pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
+  *         the configuration information for the specified layer.
+  * @param  LayerIdx  DMA2D Layer index.
+  *                   This parameter can be one of the following values:
+  *                   0(background) / 1(foreground)
+  * @retval None
+  */
+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset));
+  assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode));
+  assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode));
+  assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize));
+  assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode));
+  assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green));
+  assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red));
+  assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue));
+  assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha));
+  assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode));
+  assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode));
+  assert_param(IS_LL_DMA2D_CHROMA_SUB_SAMPLING(DMA2D_LayerCfg->ChromaSubSampling));
+
+
+  if (LayerIdx == 0U)
+  {
+    /* Configure the background memory address */
+    LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+    /* Configure the background line offset */
+    LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+    /* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion
+       CLUT size, CLUT Color mode and Color mode */
+    MODIFY_REG(DMA2Dx->BGPFCCR, \
+               (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \
+                DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \
+               ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
+                DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
+                (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
+                DMA2D_LayerCfg->ColorMode));
+
+    /* Configure the background color */
+    LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+    /* Configure the background CLUT memory address */
+    LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+  }
+  else
+  {
+    /* Configure the foreground memory address */
+    LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
+
+    /* Configure the foreground line offset */
+    LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
+
+    /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion
+       CLUT size, CLUT Color mode and Color mode */
+    MODIFY_REG(DMA2Dx->FGPFCCR, \
+               (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_CSS | DMA2D_FGPFCCR_AM | \
+                DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
+               ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
+                DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \
+                DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \
+                DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode));
+
+    /* Configure the foreground color */
+    LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
+
+    /* Configure the foreground CLUT memory address */
+    LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
+  }
+}
+
+/**
+  * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
+  * @param DMA2D_LayerCfg  pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
+{
+  /* Set DMA2D_LayerCfg fields to default values */
+  DMA2D_LayerCfg->MemoryAddress      = 0x0U;
+  DMA2D_LayerCfg->ColorMode          = LL_DMA2D_INPUT_MODE_ARGB8888;
+  DMA2D_LayerCfg->LineOffset         = 0x0U;
+  DMA2D_LayerCfg->CLUTColorMode      = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888;
+  DMA2D_LayerCfg->CLUTSize           = 0x0U;
+  DMA2D_LayerCfg->AlphaMode          = LL_DMA2D_ALPHA_MODE_NO_MODIF;
+  DMA2D_LayerCfg->Alpha              = 0x0U;
+  DMA2D_LayerCfg->Blue               = 0x0U;
+  DMA2D_LayerCfg->Green              = 0x0U;
+  DMA2D_LayerCfg->Red                = 0x0U;
+  DMA2D_LayerCfg->CLUTMemoryAddress  = 0x0U;
+  DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
+  DMA2D_LayerCfg->RBSwapMode         = LL_DMA2D_RB_MODE_REGULAR;
+  DMA2D_LayerCfg->ChromaSubSampling  = LL_DMA2D_CSS_444;
+}
+
+/**
+  * @brief  Initialize DMA2D output color register according to the specified parameters
+  *         in DMA2D_ColorStruct.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  DMA2D_ColorStruct  pointer to a LL_DMA2D_ColorTypeDef structure that contains
+  *         the color configuration information for the specified DMA2D peripheral.
+  * @retval None
+  */
+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
+{
+  uint32_t outgreen;
+  uint32_t outred;
+  uint32_t outalpha;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode));
+  assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen));
+  assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed));
+  assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue));
+  assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha));
+
+  /* DMA2D OCOLR register configuration ------------------------------------------*/
+  if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+    outred = DMA2D_ColorStruct->OutputRed << 16U;
+    outalpha = DMA2D_ColorStruct->OutputAlpha << 24U;
+  }
+  else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
+    outred = DMA2D_ColorStruct->OutputRed << 16U;
+    outalpha = 0x00000000U;
+  }
+  else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+    outred = DMA2D_ColorStruct->OutputRed << 11U;
+    outalpha = 0x00000000U;
+  }
+  else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
+    outred = DMA2D_ColorStruct->OutputRed << 10U;
+    outalpha = DMA2D_ColorStruct->OutputAlpha << 15U;
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    outgreen = DMA2D_ColorStruct->OutputGreen << 4U;
+    outred = DMA2D_ColorStruct->OutputRed << 8U;
+    outalpha = DMA2D_ColorStruct->OutputAlpha << 12U;
+  }
+  LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha));
+}
+
+/**
+  * @brief  Return DMA2D output Blue color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU));
+  }
+
+  return color;
+}
+
+/**
+  * @brief  Return DMA2D output Green color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U);
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U);
+  }
+
+  return color;
+}
+
+/**
+  * @brief  Return DMA2D output Red color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U);
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U);
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U);
+  }
+
+  return color;
+}
+
+/**
+  * @brief  Return DMA2D output Alpha color.
+  * @param  DMA2Dx DMA2D Instance.
+  * @param  ColorMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
+  * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF
+  */
+uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
+{
+  uint32_t color;
+
+  /* Check the parameters */
+  assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
+  assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
+
+  /* DMA2D OCOLR register reading ------------------------------------------*/
+  if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U);
+  }
+  else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565))
+  {
+    color = 0x0U;
+  }
+  else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U);
+  }
+  else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
+  {
+    color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U);
+  }
+
+  return color;
+}
+
+/**
+  * @brief  Configure DMA2D transfer size.
+  * @param  DMA2Dx DMA2D Instance
+  * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
+  * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
+  * @retval None
+  */
+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
+{
+  MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \
+             ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (DMA2D) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_exti.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_exti.c
new file mode 100644
index 000000000..bf7d97003
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_exti.c
@@ -0,0 +1,377 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_exti.c
+  * @author  GPM Application Team
+  * @brief   EXTI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_exti.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+
+#define IS_LL_EXTI_LINE_64_95(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+                                                      || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+                                                      || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+                                                      || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+                                                      || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+                                                      || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the EXTI registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - 0x00: EXTI registers are de-initialized
+  */
+uint32_t LL_EXTI_DeInit(void)
+{
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR1,   0x00000000U);
+  /* Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR1,   0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR1,  0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR1,  0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+  /* Pending register set to default reset values */
+  LL_EXTI_WriteReg(RPR1,   0xFFFFFFFFU);
+  LL_EXTI_WriteReg(FPR1,   0xFFFFFFFFU);
+  /* Privilege register set to default reset values */
+  LL_EXTI_WriteReg(PRIVCFGR1,  0x00000000U);
+#if defined CPU_IN_SECURE_STATE
+  /* Secure register set to default reset values */
+  LL_EXTI_WriteReg(SECCFGR1,  0x00000000U);
+#endif /* CPU_IN_SECURE_STATE */
+
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR2,   0x00000000U);
+  /* Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR2,   0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR2,  0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR2,  0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+  /* Pending register set to default reset values */
+  LL_EXTI_WriteReg(RPR2,   0xFFFFFFFFU);
+  LL_EXTI_WriteReg(FPR2,   0xFFFFFFFFU);
+  /* Privilege register set to default reset values */
+  LL_EXTI_WriteReg(PRIVCFGR2,  0x00000000U);
+#if defined CPU_IN_SECURE_STATE
+  /* Secure register set to default reset values */
+  LL_EXTI_WriteReg(SECCFGR2,  0x00000000U);
+#endif /* CPU_IN_SECURE_STATE */
+
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR3,   0x00000000U);
+  /* Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR3,   0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR3,  0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR3,  0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER3, 0x00000000U);
+  /* Pending register set to default reset values */
+  LL_EXTI_WriteReg(RPR3,   0xFFFFFFFFU);
+  LL_EXTI_WriteReg(FPR3,   0xFFFFFFFFU);
+  /* Privilege register set to default reset values */
+  LL_EXTI_WriteReg(PRIVCFGR3,  0x00000000U);
+#if defined CPU_IN_SECURE_STATE
+  /* Secure register set to default reset values */
+  LL_EXTI_WriteReg(SECCFGR3,  0x00000000U);
+#endif /* CPU_IN_SECURE_STATE */
+
+  return 0x00u;
+}
+
+/**
+  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - 0x00: EXTI registers are initialized
+  *          - any other value : wrong configuration
+  */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  uint32_t status = 0x00u;
+
+  /* Check the parameters */
+  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+  assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+  assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+  /* ENABLE LineCommand */
+  if (EXTI_InitStruct->LineCommand != DISABLE)
+  {
+    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+    /* Configure EXTI Lines in range from 0 to 31 */
+    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        default:
+          status = 0x01u;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Rising Trigger on provided Lines */
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          default:
+            status |= 0x02u;
+            break;
+        }
+      }
+    }
+    /* Configure EXTI Lines in range from 32 to 63 */
+    if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        default:
+          status |= 0x04u;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable IT on provided Lines */
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          default:
+            status |= 0x08u;
+            break;
+        }
+      }
+    }
+    /* Configure EXTI Lines in range from 64 to 95 */
+    if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
+          LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
+          break;
+        default:
+          status |= 0x10u;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            /* Then Enable IT on provided Lines */
+            LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          default:
+            status |= 0x20u;
+            break;
+        }
+      }
+    }
+  }
+  /* DISABLE LineCommand */
+  else
+  {
+    /* De-configure EXTI Lines in range from 0 to 31 */
+    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+    /* De-configure EXTI Lines in range from 32 to 63 */
+    LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+    LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+    /* De-configure EXTI Lines in range from 64 to 95 */
+    LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+    LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval None
+  */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->Line_64_95     = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->LineCommand    = DISABLE;
+  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (EXTI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_fmc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_fmc.c
new file mode 100644
index 000000000..c1e803536
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_fmc.c
@@ -0,0 +1,1066 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_fmc.c
+  * @author  MCD Application Team
+  * @brief   FMC Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### FMC peripheral features #####
+  ==============================================================================
+  [..] The Flexible memory controller (FMC) includes following memory controllers:
+       (+) The NOR/PSRAM memory controller
+     (+) The NAND memory controller
+       (+) The Synchronous DRAM (SDRAM) controller
+
+  [..] The FMC functional block makes the interface with synchronous and asynchronous static
+       memories and SDRAM memories. Its main purposes are:
+       (+) to translate AHB transactions into the appropriate external device protocol
+       (+) to meet the access time requirements of the external memory devices
+
+  [..] All external memories share the addresses, data and control signals with the controller.
+       Each external device is accessed by means of a unique Chip Select. The FMC performs
+       only one access at a time to an external device.
+       The main features of the FMC controller are the following:
+        (+) Interface with static-memory mapped devices including:
+           (++) Static random access memory (SRAM)
+           (++) Read-only memory (ROM)
+           (++) NOR Flash memory/OneNAND Flash memory
+           (++) PSRAM (4 memory banks)
+           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+                data
+        (+) Interface with synchronous DRAM (SDRAM) memories
+        (+) Independent Chip Select control for each memory bank
+        (+) Independent configuration for each memory bank
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
+    || defined(HAL_SRAM_MODULE_ENABLED)
+
+/** @defgroup FMC_LL  FMC Low Layer
+  * @brief FMC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
+  * @{
+  */
+
+/* ----------------------- FMC registers bit mask --------------------------- */
+
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK    ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD  |\
+                                      FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
+                                      FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT  |\
+                                      FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#define BWTR_CLEAR_MASK   ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD  |\
+                                      FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
+                                      FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
+
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN  | \
+                                      FMC_PCR_PWID    | FMC_PCR_ECCEN  | \
+                                      FMC_PCR_TCLR    | FMC_PCR_TAR    | \
+                                      FMC_PCR_ECCSS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEM_MEMSET  | FMC_PMEM_MEMWAIT |\
+                                      FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATT_ATTSET  | FMC_PATT_ATTWAIT |\
+                                      FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
+
+
+/* --- SDCR Register ---*/
+/* SDCR register clear mask */
+#define SDCR_CLEAR_MASK   ((uint32_t)(FMC_SDCRx_NC    | FMC_SDCRx_NR     | \
+                                      FMC_SDCRx_MWID  | FMC_SDCRx_NB     | \
+                                      FMC_SDCRx_CAS   | FMC_SDCRx_WP     | \
+                                      FMC_SDCRx_SDCLK | FMC_SDCRx_RPIPE))
+
+/* --- SDTR Register ---*/
+/* SDTR register clear mask */
+#define SDTR_CLEAR_MASK   ((uint32_t)(FMC_SDTRx_TMRD  | FMC_SDTRx_TXSR   | \
+                                      FMC_SDTRx_TRAS  | FMC_SDTRx_TRC    | \
+                                      FMC_SDTRx_TWR   | FMC_SDTRx_TRP    | \
+                                      FMC_SDTRx_TRCD))
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+  * @{
+  */
+
+
+/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
+  * @brief  NORSRAM Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                   ##### How to use NORSRAM device driver #####
+  ==============================================================================
+
+  [..]
+    This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+    to run the NORSRAM external devices.
+
+    (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+    (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+    (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+    (+) FMC NORSRAM bank extended timing configuration using the function
+        FMC_NORSRAM_Extended_Timing_Init()
+    (+) FMC NORSRAM bank enable/disable write operation using the functions
+        FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NORSRAM interface
+    (+) De-initialize the FMC NORSRAM interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the FMC_NORSRAM device according to the specified
+  *         control parameters in the FMC_NORSRAM_InitTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Init Pointer to NORSRAM Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+                                    const FMC_NORSRAM_InitTypeDef *Init)
+{
+  uint32_t flashaccess;
+  uint32_t btcr_reg;
+  uint32_t mask;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+  assert_param(IS_FMC_MUX(Init->DataAddressMux));
+  assert_param(IS_FMC_MEMORY(Init->MemoryType));
+  assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+  assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+  assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+  assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+  assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+  assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+  assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+  assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+  assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+  assert_param(IS_FMC_PAGESIZE(Init->PageSize));
+  assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
+
+  /* Disable NORSRAM Device */
+  __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
+  /* Set NORSRAM device control parameters */
+  if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+  {
+    flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
+  }
+  else
+  {
+    flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
+  }
+
+  btcr_reg = (flashaccess                   | \
+              Init->DataAddressMux          | \
+              Init->MemoryType              | \
+              Init->MemoryDataWidth         | \
+              Init->BurstAccessMode         | \
+              Init->WaitSignalPolarity      | \
+              Init->WaitSignalActive        | \
+              Init->WriteOperation          | \
+              Init->WaitSignal              | \
+              Init->ExtendedMode            | \
+              Init->AsynchronousWait        | \
+              Init->WriteBurst);
+
+  btcr_reg |= Init->ContinuousClock;
+  btcr_reg |= Init->NBLSetupTime;
+  btcr_reg |= Init->PageSize;
+
+  mask = (FMC_BCRx_MBKEN                |
+          FMC_BCRx_MUXEN                |
+          FMC_BCRx_MTYP                 |
+          FMC_BCRx_MWID                 |
+          FMC_BCRx_FACCEN               |
+          FMC_BCRx_BURSTEN              |
+          FMC_BCRx_WAITPOL              |
+          FMC_BCRx_WAITCFG              |
+          FMC_BCRx_WREN                 |
+          FMC_BCRx_WAITEN               |
+          FMC_BCRx_EXTMOD               |
+          FMC_BCRx_ASYNCWAIT            |
+          FMC_BCRx_CBURSTRW);
+
+  mask |= FMC_CFGR_CCLKEN;
+  mask |= FMC_BCRx_NBLSET;
+  mask |= FMC_BCRx_CPSIZE;
+
+  MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
+
+  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+  if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+  {
+    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN, Init->ContinuousClock);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the FMC_NORSRAM peripheral
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  ExDevice Pointer to NORSRAM extended mode device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+                                     FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Disable the FMC_NORSRAM device */
+  __FMC_NORSRAM_DISABLE(Device, Bank);
+
+  /* De-initialize the FMC_NORSRAM device */
+  /* FMC_NORSRAM_BANK1 */
+  if (Bank == FMC_NORSRAM_BANK1)
+  {
+    Device->BTCR[Bank] = 0x000030DBU;
+  }
+  /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+  else
+  {
+    Device->BTCR[Bank] = 0x000030D2U;
+  }
+
+  Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+                                          const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+  uint32_t tmpr;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+  assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+  assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
+  assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+  assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+  assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+  assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+  assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Set FMC_NORSRAM device timing parameters */
+  Device->BTCR[Bank + 1U] =
+    (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
+    (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
+    (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
+    (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) |
+    (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
+    ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
+    ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
+    Timing->AccessMode;
+
+  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+  if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN))
+  {
+    tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
+    tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
+    MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+  *         parameters in the FMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @param  ExtendedMode FMC Extended Mode
+  *          This parameter can be one of the following values:
+  *            @arg FMC_EXTENDED_MODE_DISABLE
+  *            @arg FMC_EXTENDED_MODE_ENABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+                                                   const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+                                                   uint32_t ExtendedMode)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+
+  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+  if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+  {
+    /* Check the parameters */
+    assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+    assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+    assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+    assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+    assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
+    assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+    assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+    assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
+                                                     ((Timing->AddressHoldTime)        << FMC_BWTRx_ADDHLD_Pos)  |
+                                                     ((Timing->DataSetupTime)          << FMC_BWTRx_DATAST_Pos)  |
+                                                     ((Timing->DataHoldTime)           << FMC_BWTRx_DATAHLD_Pos) |
+                                                     Timing->AccessMode                                          |
+                                                     ((Timing->BusTurnAroundDuration)  << FMC_BWTRx_BUSTURN_Pos)));
+  }
+  else
+  {
+    Device->BWTR[Bank] = 0x0FFFFFFFU;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### FMC_NORSRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NORSRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically FMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Enable write operation */
+  SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+  /* Disable write operation */
+  CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
+  * @brief    NAND Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use NAND device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC NAND banks in order
+    to run the NAND external devices.
+
+    (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+    (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+    (+) FMC NAND bank common space timing configuration using the function
+        FMC_NAND_CommonSpace_Timing_Init()
+    (+) FMC NAND bank attribute space timing configuration using the function
+        FMC_NAND_AttributeSpace_Timing_Init()
+    (+) FMC NAND bank enable/disable ECC correction feature using the functions
+        FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+    (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC NAND interface
+    (+) De-initialize the FMC NAND interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FMC_NAND device according to the specified
+  *         control parameters in the FMC_NAND_HandleTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Init Pointer to NAND Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+  assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+  /* NAND bank 3 registers configuration */
+  MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |
+                                           FMC_PCR_MEMORY_TYPE_NAND                     |
+                                           Init->MemoryDataWidth                        |
+                                           Init->EccComputation                         |
+                                           Init->ECCPageSize                            |
+                                           ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos)  |
+                                           ((Init->TARSetupTime)  << FMC_PCR_TAR_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Common space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                   const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* NAND bank 3 registers configuration */
+  Device->PMEM = (Timing->SetupTime |
+                  ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
+                  ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
+                  ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
+  *         parameters in the FMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+                                                      const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* NAND bank 3 registers configuration */
+  Device->PATT = (Timing->SetupTime |
+                  ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
+                  ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
+                  ((Timing->HiZSetupTime)  << FMC_PATT_ATTHIZ_Pos));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FMC_NAND device
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Disable the NAND Bank */
+  __FMC_NAND_DISABLE(Device, Bank);
+
+  /* De-initialize the NAND Bank */
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* Set the FMC_NAND_BANK3 registers to their reset values */
+  WRITE_REG(Device->PCR,  0x0007FE08U);
+  WRITE_REG(Device->SR,   0x00015753U);
+  WRITE_REG(Device->PMEM, 0x0A0A0A0AU);
+  WRITE_REG(Device->PATT, 0x0A0A0A0AU);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                       ##### FMC_NAND Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC NAND interface.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Enable ECC feature */
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  SET_BIT(Device->PCR, FMC_PCR_ECCEN);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Disable ECC feature */
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  ECCval Pointer to ECC value
+  * @param  Bank NAND bank number
+  * @param  Timeout Timeout wait value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+                                  uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_NAND_DEVICE(Device));
+  assert_param(IS_FMC_NAND_BANK(Bank));
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FIFO is empty */
+  while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  UNUSED(Bank);
+
+  /* Get the ECCR register value */
+  *ECCval = (uint32_t)Device->HECCR;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_LL_SDRAM
+  * @brief    SDRAM Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use SDRAM device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FMC SDRAM banks in order
+    to run the SDRAM external devices.
+
+    (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
+    (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
+    (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
+    (+) FMC SDRAM bank enable/disable write operation using the functions
+        FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
+    (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
+
+@endverbatim
+  * @{
+  */
+
+/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FMC SDRAM interface
+    (+) De-initialize the FMC SDRAM interface
+    (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FMC_SDRAM device according to the specified
+  *         control parameters in the FMC_SDRAM_InitTypeDef
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Init Pointer to SDRAM Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
+  assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
+  assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
+  assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
+  assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
+  assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
+  assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
+  assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
+
+  /* Set SDRAM bank configuration parameters */
+  if (Init->SDBank == FMC_SDRAM_BANK1)
+  {
+    MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
+               SDCR_CLEAR_MASK,
+               (Init->ColumnBitsNumber   |
+                Init->RowBitsNumber      |
+                Init->MemoryDataWidth    |
+                Init->InternalBankNumber |
+                Init->CASLatency         |
+                Init->WriteProtection    |
+                Init->SDClockPeriod      |
+                Init->ReadPipeDelay));
+  }
+  else /* FMC_Bank2_SDRAM */
+  {
+    MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
+               FMC_SDCRx_SDCLK           |
+               FMC_SDCRx_RPIPE,
+               (Init->SDClockPeriod      |
+                Init->ReadPipeDelay));
+
+    MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
+               SDCR_CLEAR_MASK,
+               (Init->ColumnBitsNumber   |
+                Init->RowBitsNumber      |
+                Init->MemoryDataWidth    |
+                Init->InternalBankNumber |
+                Init->CASLatency         |
+                Init->WriteProtection));
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initializes the FMC_SDRAM device timing according to the specified
+  *         parameters in the FMC_SDRAM_TimingTypeDef
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Timing Pointer to SDRAM Timing structure
+  * @param  Bank SDRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
+                                        const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
+  assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
+  assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
+  assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
+  assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
+  assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
+  assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Set SDRAM device timing parameters */
+  MODIFY_REG(Device->SDTR,
+             SDTR_CLEAR_MASK,
+             (((Timing->LoadToActiveDelay) - 1U)                                      |
+              (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
+              (((Timing->SelfRefreshTime) - 1U)      << FMC_SDTRx_TRAS_Pos) |
+              (((Timing->RowCycleDelay) - 1U)        << FMC_SDTRx_TRC_Pos)  |
+              (((Timing->WriteRecoveryTime) - 1U)    << FMC_SDTRx_TWR_Pos)  |
+              (((Timing->RPDelay) - 1U)              << FMC_SDTRx_TRP_Pos)  |
+              (((Timing->RCDDelay) - 1U)             << FMC_SDTRx_TRCD_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FMC_SDRAM peripheral
+  * @param  Device Pointer to SDRAM device instance
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* De-initialize the SDRAM device */
+  Device->SDCR[Bank] = 0x000002D0U;
+  Device->SDTR       = 0x0FFFFFFFU;
+  Device->SDCMR      = 0x00000000U;
+  Device->SDRTR      = 0x00000000U;
+  Device->SDSR       = 0x00000000U;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### FMC_SDRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FMC SDRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically FMC_SDRAM write protection.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Bank SDRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Enable write protection */
+  SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FMC_SDRAM write protection.
+  * @param  hsdram FMC_SDRAM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Disable write protection */
+  CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Send Command to the FMC SDRAM bank
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Command Pointer to SDRAM command structure
+  * @param  Timing Pointer to SDRAM Timing structure
+  * @param  Timeout Timeout wait value
+  * @retval HAL state
+  */
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
+                                        const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
+  assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
+  assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
+  assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
+
+  /* Set command register */
+  MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_DS2 | FMC_SDCMR_DS1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
+             ((Command->CommandMode) | (Command->CommandTarget) |
+              (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
+              ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Timeout);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Program the SDRAM Memory Refresh rate.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  RefreshRate The SDRAM refresh rate value.
+  * @retval HAL state
+  */
+HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
+
+  /* Set the refresh rate in command register */
+  MODIFY_REG(Device->SDRTR, FMC_SDRTR_RFSCNT, (RefreshRate << FMC_SDRTR_RFSCNT_Pos));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  AutoRefreshNumber Specifies the auto Refresh number.
+  * @retval None
+  */
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
+                                                 uint32_t AutoRefreshNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
+
+  /* Set the Auto-refresh number in command register */
+  MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Returns the indicated FMC SDRAM bank mode status.
+  * @param  Device Pointer to SDRAM device instance
+  * @param  Bank Defines the FMC SDRAM bank. This parameter can be
+  *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
+  * @retval The FMC SDRAM bank mode status, could be on of the following values:
+  *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
+  *         FMC_SDRAM_POWER_DOWN_MODE.
+  */
+uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_FMC_SDRAM_DEVICE(Device));
+  assert_param(IS_FMC_SDRAM_BANK(Bank));
+
+  /* Get the corresponding bank mode */
+  if (Bank == FMC_SDRAM_BANK1)
+  {
+    tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
+  }
+  else
+  {
+    tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
+  }
+
+  /* Return the mode status */
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_NOR_MODULE_ENABLED */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_gpio.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_gpio.c
new file mode 100644
index 000000000..effd98d64
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_gpio.c
@@ -0,0 +1,294 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_gpio.c
+  * @author  GPM Application Team
+  * @brief   GPIO LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_gpio.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPION) || defined (GPIOO) || defined (GPIOP) || defined (GPIOQ)
+/** @addtogroup GPIO_LL
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+  * range of the shift operator in following API :
+  * LL_GPIO_Init
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  * @param  GPIOx GPIO Port
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are de-initialized
+  *          - ERROR:   Wrong GPIO Port
+  */
+ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Force and Release reset on clock of GPIOx Port */
+  if (GPIOx == GPIOA)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD);
+  }
+  else if (GPIOx == GPIOE)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE);
+  }
+  else if (GPIOx == GPIOF)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF);
+  }
+  else if (GPIOx == GPIOG)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG);
+  }
+  else if (GPIOx == GPIOH)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH);
+  }
+  else if (GPIOx == GPION)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPION);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPION);
+  }
+  else if (GPIOx == GPIOO)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOO);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOO);
+  }
+  else if (GPIOx == GPIOP)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOP);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOP);
+  }
+  else if (GPIOx == GPIOQ)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOQ);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOQ);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+  * @param  GPIOx GPIO Port
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *         that contains the configuration information for the specified GPIO peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, const LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  uint32_t pinpos;
+  uint32_t currentpin;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /* Initialize  pinpos on first pin set */
+  pinpos = 0;
+
+  /* Configure the port pins */
+  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
+  {
+    /* Get current io position */
+    currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
+
+    if (currentpin != 0x00u)
+    {
+      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+        /* Speed mode configuration */
+        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+        /* Check Output mode parameters */
+        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+        /* Output mode configuration*/
+        LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+      {
+        /* Check Alternate parameter */
+        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+        /* Speed mode configuration */
+        if (currentpin < LL_GPIO_PIN_8)
+        {
+          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+        else
+        {
+          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+      }
+
+      /* Pin Mode configuration */
+      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+    }
+    pinpos++;
+  }
+
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPION) || defined (GPIOO) || defined (GPIOP) || defined (GPIOQ) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_i2c.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_i2c.c
new file mode 100644
index 000000000..751699c17
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_i2c.c
@@ -0,0 +1,240 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_i2c.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
+                                                 ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the I2C registers to their default reset values.
+  * @param  I2Cx I2C Instance.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are de-initialized
+  *          - ERROR: I2C registers are not de-initialized
+  */
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+  }
+  else if (I2Cx == I2C2)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+  }
+  else if (I2Cx == I2C3)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
+  }
+  else if (I2Cx == I2C4)
+  {
+    /* Force reset of I2C clock */
+    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_I2C4);
+
+    /* Release reset of I2C clock */
+    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_I2C4);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+  * @param  I2Cx I2C Instance.
+  * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are initialized
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  /* Check the I2C parameters from I2C_InitStruct */
+  assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+  assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+  assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+  assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+  assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+  assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+  /* Disable the selected I2Cx Peripheral */
+  LL_I2C_Disable(I2Cx);
+
+  /*---------------------------- I2Cx CR1 Configuration ------------------------
+   * Configure the analog and digital noise filters with parameters :
+   * - AnalogFilter: I2C_CR1_ANFOFF bit
+   * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+   */
+  LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+  /*---------------------------- I2Cx TIMINGR Configuration --------------------
+   * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+   * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+   *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+   */
+  LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+  /* Enable the selected I2Cx Peripheral */
+  LL_I2C_Enable(I2Cx);
+
+  /*---------------------------- I2Cx OAR1 Configuration -----------------------
+   * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+   * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
+   * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
+   */
+  LL_I2C_DisableOwnAddress1(I2Cx);
+  LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+  /* OwnAdress1 == 0 is reserved for General Call address */
+  if (I2C_InitStruct->OwnAddress1 != 0U)
+  {
+    LL_I2C_EnableOwnAddress1(I2Cx);
+  }
+
+  /*---------------------------- I2Cx MODE Configuration -----------------------
+  * Configure I2Cx peripheral mode with parameter :
+   * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+   */
+  LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+  /*---------------------------- I2Cx CR2 Configuration ------------------------
+   * Configure the ACKnowledge or Non ACKnowledge condition
+   * after the address receive match code or next received byte with parameter :
+   * - TypeAcknowledge: I2C_CR2_NACK bit
+   */
+  LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
+  * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval None
+  */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Set I2C_InitStruct fields to default values */
+  I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
+  I2C_InitStruct->Timing          = 0U;
+  I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
+  I2C_InitStruct->DigitalFilter   = 0U;
+  I2C_InitStruct->OwnAddress1     = 0U;
+  I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+  I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_i3c.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_i3c.c
new file mode 100644
index 000000000..b6f48dcdb
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_i3c.c
@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_i3c.c
+  * @author  MCD Application Team
+  * @brief   I3C LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_bus.h"
+#include "stm32n6xx_ll_i3c.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (I3C1) || defined (I3C2)
+
+/** @defgroup I3C_LL I3C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I3C_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_I3C_SDAHOLDTIME_VALUE(VALUE) (((VALUE) == LL_I3C_SDA_HOLD_TIME_0_5) || \
+                                            ((VALUE) == LL_I3C_SDA_HOLD_TIME_1_5))
+
+#define IS_LL_I3C_WAITTIME_VALUE(VALUE) (((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_0) || \
+                                         ((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_1) || \
+                                         ((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_2) || \
+                                         ((VALUE) == LL_I3C_OWN_ACTIVITY_STATE_3))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I3C_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I3C_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the I3C registers to their default reset values.
+  * @param  I3Cx I3C Instance.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I3C registers are de-initialized
+  *          - ERROR: I3C registers are not de-initialized
+  */
+ErrorStatus LL_I3C_DeInit(const I3C_TypeDef *I3Cx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the I3C Instance I3Cx */
+  assert_param(IS_I3C_ALL_INSTANCE(I3Cx));
+
+  if (I3Cx == I3C1)
+  {
+    /* Force reset of I3C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C1);
+
+    /* Release reset of I3C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C1);
+  }
+  else if (I3Cx == I3C2)
+  {
+    /* Force reset of I3C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C2);
+
+    /* Release reset of I3C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C2);
+
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the I3C registers according to the specified parameters in I3C_InitStruct.
+  * @param  I3Cx I3C Instance.
+  * @param  I3C_InitStruct pointer to a @ref LL_I3C_InitTypeDef structure.
+  * @param  Mode I3C peripheral mode.
+  *              This parameter can be a value of @ref I3C_LL_EC_MODE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I3C registers are initialized
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_I3C_Init(I3C_TypeDef *I3Cx, LL_I3C_InitTypeDef *I3C_InitStruct, uint32_t Mode)
+{
+  uint32_t waveform_value;
+  uint32_t timing_value;
+
+  /* Check the I3C Instance I3Cx */
+  assert_param(IS_I3C_ALL_INSTANCE(I3Cx));
+
+  /* Disable the selected I3C peripheral */
+  LL_I3C_Disable(I3Cx);
+
+  /* Check on the I3C mode: initialization depends on the mode */
+  if (Mode == LL_I3C_MODE_CONTROLLER)
+  {
+    /* Check the parameters */
+    assert_param(IS_LL_I3C_SDAHOLDTIME_VALUE(I3C_InitStruct->CtrlBusCharacteristic.SDAHoldTime));
+    assert_param(IS_LL_I3C_WAITTIME_VALUE(I3C_InitStruct->CtrlBusCharacteristic.WaitTime));
+
+    /* Set Controller mode */
+    LL_I3C_SetMode(I3Cx, LL_I3C_MODE_CONTROLLER);
+
+    /*------------------ SCL signal waveform configuration : I3C timing register 0 (I3C_TIMINGR0) ------------------- */
+    /* Set the controller SCL waveform */
+    waveform_value =
+      ((uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.SCLPPLowDuration)                                |
+       ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.SCLI3CHighDuration << I3C_TIMINGR0_SCLH_I3C_Pos) |
+       ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.SCLODLowDuration << I3C_TIMINGR0_SCLL_OD_Pos)    |
+       ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.SCLI2CHighDuration << I3C_TIMINGR0_SCLH_I2C_Pos));
+
+    LL_I3C_ConfigClockWaveForm(I3Cx, waveform_value);
+
+    /*------------------- Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------- */
+    /* Set SDA hold time, activity state, bus free duration and bus available duration */
+    timing_value = ((uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.SDAHoldTime)                               |
+                    (uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.WaitTime)                                  |
+                    ((uint32_t)I3C_InitStruct->CtrlBusCharacteristic.BusFreeDuration <<  I3C_TIMINGR1_FREE_Pos) |
+                    (uint32_t)(I3C_InitStruct->CtrlBusCharacteristic.BusIdleDuration));
+
+    LL_I3C_SetCtrlBusCharacteristic(I3Cx, timing_value);
+  }
+  else
+  {
+    /* Set target mode */
+    LL_I3C_SetMode(I3Cx, LL_I3C_MODE_TARGET);
+
+    /*------------------- Timing configuration : I3C timing register 1 (I3C_TIMINGR1) ------------------------------- */
+    /* Set the number of kernel clocks cycles for the bus available condition time */
+    LL_I3C_SetTgtBusCharacteristic(I3Cx, I3C_InitStruct->TgtBusCharacteristic.BusAvailableDuration);
+  }
+
+  /* Enable the selected I3C peripheral */
+  LL_I3C_Enable(I3Cx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_I3C_InitTypeDef field to default value.
+  * @param  I3C_InitStruct Pointer to a @ref LL_I3C_InitTypeDef structure.
+  * @retval None
+  */
+void LL_I3C_StructInit(LL_I3C_InitTypeDef *I3C_InitStruct)
+{
+  /* Set I3C_InitStruct fields to default values */
+  I3C_InitStruct->CtrlBusCharacteristic.SDAHoldTime         = LL_I3C_SDA_HOLD_TIME_0_5;
+  I3C_InitStruct->CtrlBusCharacteristic.WaitTime            = LL_I3C_OWN_ACTIVITY_STATE_0;
+  I3C_InitStruct->CtrlBusCharacteristic.SCLPPLowDuration    = 0U;
+  I3C_InitStruct->CtrlBusCharacteristic.SCLI3CHighDuration  = 0U;
+  I3C_InitStruct->CtrlBusCharacteristic.SCLODLowDuration    = 0U;
+  I3C_InitStruct->CtrlBusCharacteristic.SCLI2CHighDuration  = 0U;
+  I3C_InitStruct->CtrlBusCharacteristic.BusFreeDuration     = 0U;
+  I3C_InitStruct->CtrlBusCharacteristic.BusIdleDuration     = 0U;
+  I3C_InitStruct->TgtBusCharacteristic.BusAvailableDuration = 0U;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I3C1 || I3C2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_lptim.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_lptim.c
new file mode 100644
index 000000000..508a81b35
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_lptim.c
@@ -0,0 +1,206 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_lptim.c
+  * @author  MCD Application Team
+  * @brief   LPTIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_lptim.h"
+#include "stm32n6xx_ll_bus.h"
+#include "stm32n6xx_ll_rcc.h"
+
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
+
+/** @addtogroup LPTIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+                                             || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+
+#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+                                         || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPTIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set LPTIMx registers to their reset values.
+  * @param  LPTIMx LP Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx registers are de-initialized
+  *          - ERROR: invalid LPTIMx instance
+  */
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
+  if (LPTIMx == LPTIM1)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+  }
+  else if (LPTIMx == LPTIM2)
+  {
+    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2);
+    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2);
+  }
+  else if (LPTIMx == LPTIM3)
+  {
+    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3);
+    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3);
+  }
+  else if (LPTIMx == LPTIM4)
+  {
+    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4);
+    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4);
+  }
+  else if (LPTIMx == LPTIM5)
+  {
+    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5);
+    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5);
+  }
+  else
+  {
+    result = ERROR;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set each fields of the LPTIM_InitStruct structure to its default
+  *         value.
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval None
+  */
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+{
+  /* Set the default configuration */
+  LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
+  LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
+  LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
+}
+
+/**
+  * @brief  Configure the LPTIMx peripheral according to the specified parameters.
+  * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
+  * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
+  * @param  LPTIMx LP Timer Instance
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx instance has been initialized
+  *          - ERROR: LPTIMx instance hasn't been initialized
+  */
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+{
+  ErrorStatus result = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+  assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+  assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+  assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+
+  /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
+     (ENABLE bit is reset to 0).
+  */
+  if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
+  {
+    result = ERROR;
+  }
+  else
+  {
+    /* Set CKSEL bitfield according to ClockSource value */
+    /* Set PRESC bitfield according to Prescaler value */
+    /* Set WAVE bitfield according to Waveform value */
+    MODIFY_REG(LPTIMx->CFGR,
+               (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE),
+               LPTIM_InitStruct->ClockSource | \
+               LPTIM_InitStruct->Prescaler | \
+               LPTIM_InitStruct->Waveform);
+  }
+
+  return result;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_lpuart.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_lpuart.c
new file mode 100644
index 000000000..681a2af3f
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_lpuart.c
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_lpuart.c
+  * @author  MCD Application Team
+  * @brief   LPUART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_lpuart.h"
+#include "stm32n6xx_ll_rcc.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @addtogroup LPUART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Constants
+  * @{
+  */
+
+/* Definition of default baudrate value used for LPUART initialisation */
+#define LPUART_DEFAULT_BAUDRATE          (9600U)
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of LPUART registers                  */
+
+#define IS_LL_LPUART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
+/*              value :                                                       */
+/*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
+/*                - LPUART_BRR register value should be >= 0x300              */
+/*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
+/*              Baudrate specified by the user should belong to [8, 33000000].*/
+#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U))
+
+/* __VALUE__ BRR content must be greater than or equal to 0x300. */
+#define IS_LL_LPUART_BRR_MIN(__VALUE__)   ((__VALUE__) >= 0x300U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
+#define IS_LL_LPUART_BRR_MAX(__VALUE__)   ((__VALUE__) <= 0x000FFFFFU)
+
+#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
+                                           || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
+                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
+                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
+
+#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
+                                        || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
+                                        || ((__VALUE__) == LL_LPUART_PARITY_ODD))
+
+#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
+                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
+                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
+
+#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
+                                          || ((__VALUE__) == LL_LPUART_STOPBITS_2))
+
+#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
+                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
+                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
+                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPUART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize LPUART registers (Registers restored to their default values).
+  * @param  LPUARTx LPUART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+
+  if (LPUARTx == LPUART1)
+  {
+    /* Force reset of LPUART peripheral */
+    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPUART1);
+
+    /* Release reset of LPUART peripheral */
+    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPUART1);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize LPUART registers according to the specified
+  *         parameters in LPUART_InitStruct.
+  * @note   As some bits in LPUART configuration registers can only be written when
+  *         the LPUART is disabled (USART_CR1_UE bit =0),
+  *         LPUART Peripheral should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  LPUARTx LPUART Instance
+  * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *         that contains the configuration information for the specified LPUART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
+  *          - ERROR: Problem occurred during LPUART Registers initialization
+  */
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk;
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+  assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));
+  assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+  assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
+  assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
+  assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
+  assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
+  assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+  /* LPUART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
+  if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
+  {
+    /*---------------------------- LPUART CR1 Configuration -----------------------
+     * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
+     */
+    MODIFY_REG(LPUARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
+               (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
+
+    /*---------------------------- LPUART CR2 Configuration -----------------------
+     * Configure LPUARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
+     */
+    LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
+
+    /*---------------------------- LPUART CR3 Configuration -----------------------
+     * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
+     *   to LPUART_InitStruct->HardwareFlowControl value.
+     */
+    LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- LPUART BRR Configuration -----------------------
+     * Retrieve Clock frequency used for LPUART Peripheral
+     */
+    periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+
+    /* Configure the LPUART Baud Rate :
+       - prescaler value is required
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (LPUART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_LPUART_SetBaudRate(LPUARTx,
+                            periphclk,
+                            LPUART_InitStruct->PrescalerValue,
+                            LPUART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 0x300 */
+      assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
+
+      /* Check BRR is lower than or equal to 0xFFFFF */
+      assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
+    }
+
+    /*---------------------------- LPUART PRESC Configuration -----------------------
+     * Configure LPUARTx PRESC (Prescaler) with parameters:
+     * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.
+     */
+    LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
+  * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  /* Set LPUART_InitStruct fields to default values */
+  LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;
+  LPUART_InitStruct->BaudRate            = LPUART_DEFAULT_BAUDRATE;
+  LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
+  LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
+  LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
+  LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
+  LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_pka.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_pka.c
new file mode 100644
index 000000000..25f633258
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_pka.c
@@ -0,0 +1,163 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_pka.c
+  * @author  MCD Application Team
+  * @brief   PKA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_pka.h"
+#include "stm32n6xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(PKA)
+
+/** @addtogroup PKA_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PKA_LL_Private_Macros PKA Private Constants
+  * @{
+  */
+#define IS_LL_PKA_MODE(__VALUE__)     (((__VALUE__)==  LL_PKA_MODE_MODULAR_EXP)          ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MONTGOMERY_PARAM)     ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MODULAR_EXP_FAST)     ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MODULAR_EXP_PROTECT)  ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ECC_MUL)              ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ECC_COMPLETE_ADD)     ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ECDSA_SIGNATURE)      ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ECDSA_VERIFICATION)   ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_POINT_CHECK)          ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_RSA_CRT_EXP)          ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MODULAR_INV)          ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ARITHMETIC_ADD)       ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ARITHMETIC_SUB)       ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ARITHMETIC_MUL)       ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_COMPARISON)           ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MODULAR_REDUC)        ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MODULAR_ADD)          ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MODULAR_SUB)          ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_MONTGOMERY_MUL)       ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_DOUBLE_BASE_LADDER)   ||\
+                                       ((__VALUE__) ==  LL_PKA_MODE_ECC_PROJECTIVE_AFF))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PKA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PKA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize PKA registers (Registers restored to their default values).
+  * @param  PKAx PKA Instance.
+  * @retval ErrorStatus
+  *          - SUCCESS: PKA registers are de-initialized
+  *          - ERROR: PKA registers are not de-initialized
+  */
+ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_PKA_ALL_INSTANCE(PKAx));
+
+  if (PKAx == PKA)
+  {
+    /* Force PKA reset */
+    LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA);
+
+    /* Release PKA reset */
+    LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize PKA registers according to the specified parameters in PKA_InitStruct.
+  * @param  PKAx PKA Instance.
+  * @param  PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure
+  *         that contains the configuration information for the specified PKA peripheral.
+  * @retval ErrorStatus
+  *          - SUCCESS: PKA registers are initialized according to PKA_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct)
+{
+  assert_param(IS_PKA_ALL_INSTANCE(PKAx));
+  assert_param(IS_LL_PKA_MODE(PKA_InitStruct->Mode));
+
+  LL_PKA_Config(PKAx, PKA_InitStruct->Mode);
+
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_PKA_InitTypeDef field to default value.
+  * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure
+  *                       whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct)
+{
+  /* Reset PKA init structure parameters values */
+  PKA_InitStruct->Mode       = LL_PKA_MODE_MODULAR_EXP;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (PKA) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_pwr.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_pwr.c
new file mode 100644
index 000000000..ed46f9462
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_pwr.c
@@ -0,0 +1,108 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+#if defined (USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_pwr.h"
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PWR_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the PWR registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS : PWR registers are de-initialized.
+  *          - ERROR   : not applicable.
+  */
+ErrorStatus LL_PWR_DeInit(void)
+{
+  WRITE_REG(PWR->CR1, 0x00000024U);
+  WRITE_REG(PWR->CR2, 0x00000000U);
+  WRITE_REG(PWR->CR3, 0x00000000U);
+  WRITE_REG(PWR->CR4, 0x00000000U);
+  WRITE_REG(PWR->VOSCR, 0x00020002U);
+  WRITE_REG(PWR->BDCR1, 0x00000000U);
+  WRITE_REG(PWR->BDCR2, 0x00000000U);
+  WRITE_REG(PWR->DBPCR, 0x00000000U);
+  WRITE_REG(PWR->CPUCR, 0x00010000U);
+  WRITE_REG(PWR->SVMCR1, 0x00000000U);
+  WRITE_REG(PWR->SVMCR2, 0x00000000U);
+  WRITE_REG(PWR->SVMCR3, 0x00000000U);
+  WRITE_REG(PWR->WKUPCR, 0x00000000U);
+  WRITE_REG(PWR->WKUPSR, 0x00000000U);
+  WRITE_REG(PWR->WKUPEPR, 0x00000000U);
+
+  /* Clear PWR low power flags */
+  LL_PWR_ClearFlag_STOP_SB();
+
+  /* Clear PWR wake up flags */
+  LL_PWR_ClearFlag_WU();
+
+  /* Reset privilege attribute */
+  LL_PWR_ConfigPrivilege(0);
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+  /* Reset secure attribute */
+  LL_PWR_ConfigSecure(0);
+#endif /* defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U) */
+
+  return SUCCESS;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PWR) */
+/**
+  * @}
+  */
+
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rcc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rcc.c
new file mode 100644
index 000000000..44850dd9b
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rcc.c
@@ -0,0 +1,3406 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_rcc.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Constants
+  * @{
+  */
+#if defined(USE_FPGA)
+/* ***** FPGA values ******/
+#define FREF_FREQ         32000000UL  /* FREF forced to 32MHz */
+#define PLL_SOURCE_FREQ   32000000UL  /* PLL source forced to 32MHz */
+#endif /* USE_FPGA */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_ADC_CLKSOURCE)
+
+#define IS_LL_RCC_ADF_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_ADF1_CLKSOURCE)
+
+#define IS_LL_RCC_DCMIPP_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_DCMIPP_CLKSOURCE)
+
+#define IS_LL_RCC_ETH_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_ETH1_CLKSOURCE)
+
+#define IS_LL_RCC_ETHPTP_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ETH1PTP_CLKSOURCE)
+
+#define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__)  ((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)
+
+#define IS_LL_RCC_FMC_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_FMC_CLKSOURCE)
+
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+
+#define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I3C1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_I3C2_CLKSOURCE))
+
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)  \
+                                               || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)  \
+                                               || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE)  \
+                                               || ((__VALUE__) == LL_RCC_LPTIM4_CLKSOURCE)  \
+                                               || ((__VALUE__) == LL_RCC_LPTIM5_CLKSOURCE))
+
+#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__)   ((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)
+
+#define IS_LL_RCC_MDF_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_MDF1_CLKSOURCE)
+
+#define IS_LL_RCC_OTGPHY_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OTGPHY1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_OTGPHY2_CLKSOURCE))
+
+#define IS_LL_RCC_OTGPHYCKREF_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OTGPHY1CKREF_CLKSOURCE) \
+                                                    || ((__VALUE__) == LL_RCC_OTGPHY2CKREF_CLKSOURCE))
+
+#define IS_LL_RCC_PSSI_CLKSOURCE(__VALUE__)   ((__VALUE__) == LL_RCC_PSSI_CLKSOURCE)
+
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+
+#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
+
+#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE)
+
+#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_SPI4_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_SPI5_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
+
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)   (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_UART9_CLKSOURCE))
+
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_USART10_CLKSOURCE))
+
+#define IS_LL_RCC_XSPI_CLKSOURCE(__VALUE__)   (((__VALUE__) == LL_RCC_XSPI1_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_XSPI2_CLKSOURCE) \
+                                               || ((__VALUE__) == LL_RCC_XSPI3_CLKSOURCE))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+  * @{
+  */
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency);
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL1, PLL2 and PLL3 OFF
+  *            - AHB, APB Bus pre-scaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval None
+  */
+void LL_RCC_DeInit(void)
+{
+  /* Disable all interrupts except default one */
+  WRITE_REG(RCC->CIER, RCC_CIER_HSECSSIE);
+
+  /* Clear all interrupts flags */
+  WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \
+            RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | RCC_CICR_PLL3RDYC | RCC_CICR_PLL4RDYC | \
+            RCC_CICR_LSECSSC | RCC_CICR_HSECSSC | RCC_CICR_WKUPFC);
+
+  /* Clear reset source flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+  /* Restore default HSI */
+  LL_RCC_HSI_SetDivider(LL_RCC_HSI_DIV_1);
+  LL_RCC_HSI_Enable();
+
+  /* Wait for HSI READY bit */
+  while (LL_RCC_HSI_IsReady() == 0U)
+  {}
+
+  /* Reset CFGR1 register to select HSI as system clock */
+  CLEAR_REG(RCC->CFGR1);
+
+  /* Reset MSION, HSEON, PLL1ON, PLL2ON, PLL3ON and PLL4ON bits */
+  WRITE_REG(RCC->CCR, RCC_CCR_MSIONC | RCC_CCR_HSEONC | \
+            RCC_CCR_PLL1ONC | RCC_CCR_PLL2ONC | RCC_CCR_PLL3ONC | RCC_CCR_PLL4ONC);
+
+  /* Wait for PLL1 READY bit to be reset */
+  while (LL_RCC_PLL1_IsReady() != 0U)
+  {}
+
+  /* Wait for PLL2 READY bit to be reset */
+  while (LL_RCC_PLL2_IsReady() != 0U)
+  {}
+
+  /* Wait for PLL3 READY bit to be reset */
+  while (LL_RCC_PLL3_IsReady() != 0U)
+  {}
+
+  /* Wait for PLL4 READY bit to be reset */
+  while (LL_RCC_PLL4_IsReady() != 0U)
+  {}
+
+  /* Reset prescalers in CFGR2 register */
+  CLEAR_REG(RCC->CFGR2);
+
+  /* Reset LSECFGR register */
+  CLEAR_REG(RCC->LSECFGR);
+
+  /* Reset MSICFGR register */
+  CLEAR_REG(RCC->MSICFGR);
+
+  /* Reset HSIMCR register to default value */
+  WRITE_REG(RCC->HSIMCR, 0x001F07A1U);
+
+  /* Reset HSECFGR register to default value */
+  WRITE_REG(RCC->HSECFGR, 0x00000800U);
+
+  /* Reset STOPCR register to default value */
+  WRITE_REG(RCC->STOPCR, 0x00000008U);
+
+  /* Reset PLL1 registers to default value */
+  WRITE_REG(RCC->PLL1CFGR1, 0x08202500U);
+  WRITE_REG(RCC->PLL1CFGR2, 0x00800000U);
+  WRITE_REG(RCC->PLL1CFGR3, 0x4900000DU);
+  /* Reset PLL2 registers to default value */
+  WRITE_REG(RCC->PLL2CFGR1, 0x08000000U);
+  WRITE_REG(RCC->PLL2CFGR2, 0x00000000U);
+  WRITE_REG(RCC->PLL2CFGR3, 0x49000005U);
+  /* Reset PLL3 registers to default value */
+  WRITE_REG(RCC->PLL3CFGR1, 0x08000000U);
+  WRITE_REG(RCC->PLL3CFGR2, 0x00000000U);
+  WRITE_REG(RCC->PLL3CFGR3, 0x49000005U);
+  /* Reset PLL4 registers to default value */
+  WRITE_REG(RCC->PLL4CFGR1, 0x08000000U);
+  WRITE_REG(RCC->PLL4CFGR2, 0x00000000U);
+  WRITE_REG(RCC->PLL4CFGR3, 0x49000005U);
+
+  /* Disable DIVENR register to set ICx state to default value */
+  WRITE_REG(RCC->DIVENCR, 0x00FFFFFFU);
+
+  /* ICxCFGR reset value */
+  WRITE_REG(RCC->IC1CFGR, 0x00020000U);
+  WRITE_REG(RCC->IC2CFGR, 0x00030000U);
+  WRITE_REG(RCC->IC3CFGR, 0x00000000U);
+  WRITE_REG(RCC->IC4CFGR, 0x00000000U);
+  WRITE_REG(RCC->IC5CFGR, 0x00000000U);
+  WRITE_REG(RCC->IC6CFGR, 0x00030000U);
+  WRITE_REG(RCC->IC7CFGR, 0x10000000U);
+  WRITE_REG(RCC->IC8CFGR, 0x10000000U);
+  WRITE_REG(RCC->IC9CFGR, 0x10000000U);
+  WRITE_REG(RCC->IC10CFGR, 0x10000000U);
+  WRITE_REG(RCC->IC11CFGR, 0x00030000U);
+  WRITE_REG(RCC->IC12CFGR, 0x20000000U);
+  WRITE_REG(RCC->IC13CFGR, 0x20000000U);
+  WRITE_REG(RCC->IC14CFGR, 0x20000000U);
+  WRITE_REG(RCC->IC15CFGR, 0x20000000U);
+  WRITE_REG(RCC->IC16CFGR, 0x30000000U);
+  WRITE_REG(RCC->IC17CFGR, 0x30000000U);
+  WRITE_REG(RCC->IC18CFGR, 0x30000000U);
+  WRITE_REG(RCC->IC19CFGR, 0x30000000U);
+  WRITE_REG(RCC->IC20CFGR, 0x30000000U);
+
+  /* CCIPRx reset value except RTCSEL/RTCPRE preserved */
+  WRITE_REG(RCC->CCIPR1, 0x00000000U);
+  WRITE_REG(RCC->CCIPR2, 0x00000000U);
+  WRITE_REG(RCC->CCIPR3, 0x00000001U);
+  WRITE_REG(RCC->CCIPR4, 0x00000000U);
+  WRITE_REG(RCC->CCIPR5, 0x0000F0F0U);
+  WRITE_REG(RCC->CCIPR6, 0x00000000U);
+  MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PERSEL | RCC_CCIPR7_PSSISEL | \
+             RCC_CCIPR7_SAI1SEL | RCC_CCIPR7_SAI2SEL, 0x00000000U);
+  WRITE_REG(RCC->CCIPR8, 0x00000000U);
+  WRITE_REG(RCC->CCIPR9, 0x00000000U);
+  WRITE_REG(RCC->CCIPR12, 0x00000000U);
+  WRITE_REG(RCC->CCIPR13, 0x00000000U);
+  WRITE_REG(RCC->CCIPR14, 0x00000000U);
+
+  /* Reset MEMENR register to default value */
+  WRITE_REG(RCC->MEMENR, 0x000013FFU);
+
+  /* Reset MISCENR register */
+  CLEAR_REG(RCC->MISCENR);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
+  *         and different peripheral clocks available on the device.
+  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note   If SYSCLK source is MSI, function returns values based on MSI_VALUE(***)
+  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+  *         or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note   (*) HSI_VALUE is a constant defined in header file (default value
+  *             64 MHz) divider by HSIDIV, but the real value may vary depending on
+  *             on the variations in voltage and temperature.
+  * @note   (**) HSE_VALUE is a constant defined in header file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  * @note   (***) MSI_VALUE is a constant defined in header file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note   The result of this function could be incorrect when using fractional
+  *         value for HSE crystal.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  * @{
+  */
+
+/**
+  * @brief  Return the frequencies of different on chip clocks;  CPU, System bus, AHB, APB1, APB2, APB4
+  *         and APB5 buses clocks.
+  * @note   Each time CPUCLK, SYSCLK, HCLK, PCLK1, PCLK2, PCLK4 and/or PCLK5 clock changes, this function
+  *         must be called to update application structure fields. Otherwise, any configuration based on this
+  *         function will be incorrect.
+  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+  * @retval None
+  */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+  /* Get CPU frequency */
+  RCC_Clocks->CPUCLK_Frequency = LL_RCC_GetCpuClockFreq();
+
+  /* Get SYSCLK frequency */
+  RCC_Clocks->SYSCLK_Frequency = LL_RCC_GetSystemClockFreq();
+
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK4 clock frequency */
+  RCC_Clocks->PCLK4_Frequency  = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK5 clock frequency */
+  RCC_Clocks->PCLK5_Frequency  = RCC_GetPCLK5ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+  * @brief  Return CPU clock frequency
+  * @retval CPU clock frequency (in Hz)
+  */
+uint32_t LL_RCC_GetCpuClockFreq(void)
+{
+  uint32_t frequency = 0U;
+  uint32_t ic_divider;
+
+  /* Get CPU clock source ----------------------------------------------------*/
+  switch (LL_RCC_GetCpuClkSource())
+  {
+    /* No check on Ready: Won't be selected by hardware if not */
+    case LL_RCC_CPU_CLKSOURCE_STATUS_HSI:
+      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      break;
+
+    case LL_RCC_CPU_CLKSOURCE_STATUS_MSI:
+      frequency = MSI_VALUE;
+      break;
+
+    case LL_RCC_CPU_CLKSOURCE_STATUS_HSE:
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_CPU_CLKSOURCE_STATUS_IC1:
+      ic_divider = LL_RCC_IC1_GetDivider();
+      switch (LL_RCC_IC1_GetSource())
+      {
+        case LL_RCC_ICCLKSOURCE_PLL1:
+          frequency = LL_RCC_GetPLL1ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL2:
+          frequency = LL_RCC_GetPLL2ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL3:
+          frequency = LL_RCC_GetPLL3ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL4:
+          frequency = LL_RCC_GetPLL4ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        default:
+          /* Unexpected case */
+          break;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return SYSTEM bus clock frequency
+  * @retval SYSTEM bus clock frequency (in Hz)
+  */
+uint32_t LL_RCC_GetSystemClockFreq(void)
+{
+  uint32_t frequency = 0U;
+  uint32_t ic_divider;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetSysClkSource())
+  {
+    /* No check on Ready: Won't be selected by hardware if not */
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
+      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:
+      frequency = MSI_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11:
+      ic_divider = LL_RCC_IC2_GetDivider();
+      switch (LL_RCC_IC2_GetSource())
+      {
+        case LL_RCC_ICCLKSOURCE_PLL1:
+          frequency = LL_RCC_GetPLL1ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL2:
+          frequency = LL_RCC_GetPLL2ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL3:
+          frequency = LL_RCC_GetPLL3ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        case LL_RCC_ICCLKSOURCE_PLL4:
+          frequency = LL_RCC_GetPLL4ClockFreq();
+          frequency = frequency / ic_divider;
+          break;
+        default:
+          /* Unexpected case */
+          break;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return PLL1 clock frequency
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL1 output clock frequency
+  */
+uint32_t LL_RCC_GetPLL1ClockFreq(void)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t pllsource;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL1_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL1P_IsEnabled() != 0U)
+    {
+      pllsource = LL_RCC_PLL1_GetSource();
+
+      switch (pllsource)
+      {
+        case LL_RCC_PLLSOURCE_HSI:
+          if (LL_RCC_HSI_IsReady() != 0U)
+          {
+            pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_MSI:
+          if (LL_RCC_MSI_IsReady() != 0U)
+          {
+            pllinputfreq = MSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_HSE:
+          if (LL_RCC_HSE_IsReady() != 0U)
+          {
+            pllinputfreq = HSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_I2S_CKIN:
+          pllinputfreq = EXTERNAL_CLOCK_VALUE;
+          break;
+
+        default:
+          /* unexpected case */
+          break;
+      }
+
+      if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = PLL_SOURCE_FREQ;
+#endif /* USE_FPGA */
+        /* INTEGER mode only  - others TO DO */
+        divm = LL_RCC_PLL1_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetFRACN(), \
+                                                  LL_RCC_PLL1_GetP1(), LL_RCC_PLL1_GetP2());
+        }
+      }
+    }
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @brief  Return PLL2 clock frequency
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL2 output clock frequency
+  */
+uint32_t LL_RCC_GetPLL2ClockFreq(void)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t pllsource;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL2_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL2P_IsEnabled() != 0U)
+    {
+      pllsource = LL_RCC_PLL2_GetSource();
+
+      switch (pllsource)
+      {
+        case LL_RCC_PLLSOURCE_HSI:
+          if (LL_RCC_HSI_IsReady() != 0U)
+          {
+            pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_MSI:
+          if (LL_RCC_MSI_IsReady() != 0U)
+          {
+            pllinputfreq = MSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_HSE:
+          if (LL_RCC_HSE_IsReady() != 0U)
+          {
+            pllinputfreq = HSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_I2S_CKIN:
+          pllinputfreq = EXTERNAL_CLOCK_VALUE;
+          break;
+
+        default:
+          /* unexpected case */
+          break;
+      }
+
+      if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = PLL_SOURCE_FREQ;
+#endif /* USE_FPGA */
+        /* INTEGER mode only  - others TO DO */
+        divm = LL_RCC_PLL2_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetFRACN(), \
+                                                  LL_RCC_PLL2_GetP1(), LL_RCC_PLL2_GetP2());
+        }
+      }
+    }
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @brief  Return PLL3 clock frequency
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL3 output clock frequency
+  */
+uint32_t LL_RCC_GetPLL3ClockFreq(void)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t pllsource;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL3_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL3P_IsEnabled() != 0U)
+    {
+      pllsource = LL_RCC_PLL3_GetSource();
+
+      switch (pllsource)
+      {
+        case LL_RCC_PLLSOURCE_HSI:
+          if (LL_RCC_HSI_IsReady() != 0U)
+          {
+            pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_MSI:
+          if (LL_RCC_MSI_IsReady() != 0U)
+          {
+            pllinputfreq = MSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_HSE:
+          if (LL_RCC_HSE_IsReady() != 0U)
+          {
+            pllinputfreq = HSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_I2S_CKIN:
+          pllinputfreq = EXTERNAL_CLOCK_VALUE;
+          break;
+
+        default:
+          /* unexpected case */
+          break;
+      }
+
+      if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = PLL_SOURCE_FREQ;
+#endif /* USE_FPGA */
+        /* INTEGER mode only  - others TO DO */
+        divm = LL_RCC_PLL3_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetFRACN(), \
+                                                  LL_RCC_PLL3_GetP1(), LL_RCC_PLL3_GetP2());
+        }
+      }
+    }
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @brief  Return PLL4 clock frequency
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval PLL4 output clock frequency
+  */
+uint32_t LL_RCC_GetPLL4ClockFreq(void)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t pllsource;
+  uint32_t divm;
+
+  /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP1 / PLLP2
+  */
+  if (LL_RCC_PLL4_IsReady() != 0U)
+  {
+    if (LL_RCC_PLL4P_IsEnabled() != 0U)
+    {
+      pllsource = LL_RCC_PLL4_GetSource();
+
+      switch (pllsource)
+      {
+        case LL_RCC_PLLSOURCE_HSI:
+          if (LL_RCC_HSI_IsReady() != 0U)
+          {
+            pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_MSI:
+          if (LL_RCC_MSI_IsReady() != 0U)
+          {
+            pllinputfreq = MSI_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_HSE:
+          if (LL_RCC_HSE_IsReady() != 0U)
+          {
+            pllinputfreq = HSE_VALUE;
+          }
+          break;
+
+        case LL_RCC_PLLSOURCE_I2S_CKIN:
+          pllinputfreq = EXTERNAL_CLOCK_VALUE;
+          break;
+
+        default:
+          /* unexpected case */
+          break;
+      }
+
+      if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
+      {
+#if defined(USE_FPGA)
+        /**** FPGA PLL input forced to 32MHz *****/
+        pllinputfreq = PLL_SOURCE_FREQ;
+#endif /* USE_FPGA */
+        /* INTEGER mode only  - others TO DO */
+        divm = LL_RCC_PLL4_GetM();
+
+        if (divm != 0U)
+        {
+          plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL4_GetN(), LL_RCC_PLL4_GetFRACN(), \
+                                                  LL_RCC_PLL4_GetP1(), LL_RCC_PLL4_GetP2());
+        }
+      }
+    }
+  }
+
+  return plloutputfreq;
+}
+
+/**
+  * @brief  Helper function to calculate the PLL frequency output when used in integer or fractional mode
+  * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (), @ref LL_RCC_PLL1_GetN (),
+  *           @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP1 (), @ref LL_RCC_PLL1_GetP2 ());
+  * @param  PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/MSI)
+  * @param  M      Between 1 and 63
+  * @param  N      Between 16 and 640 in integer mode, 20 to 320 in fractional mode
+  * @param  FRACN  0 in integer mode, between 0 and 0xFFFFFF in fractional mode
+  * @param  P1     VCO output divider P1 between 1 and 7
+  * @param  P2     VCO output divider P2 between 1 and 7
+  * @retval PLL clock frequency (in Hz)
+  */
+uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1,
+                                 uint32_t P2)
+{
+  float_t freq;
+
+  freq = ((float_t)PLLInputFreq * ((float_t)N + ((float_t)FRACN / (float_t)0x1000000))) / (float_t)M;
+
+  freq = freq / (float_t)P1;
+  freq = freq / (float_t)P2;
+
+  return (uint32_t)freq;
+}
+
+/**
+  * @brief  Return ADC clock frequency
+  * @param  ADCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval ADC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+  switch (LL_RCC_GetADCClockSource(ADCxSource))
+  {
+    case LL_RCC_ADC_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_I2S_CKIN:
+      frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_TIMG:
+      frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return ADFx clock frequency
+  * @param  ADFxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADF1_CLKSOURCE
+  * @retval ADF clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_ADF_CLKSOURCE(ADFxSource));
+
+  switch (LL_RCC_GetADFClockSource(ADFxSource))
+  {
+    case LL_RCC_ADF1_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_I2S_CKIN:
+      frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_ADF1_CLKSOURCE_TIMG:
+      frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return CLKP clock frequency
+  * @param  CLKPxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
+  * @retval CLKP clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
+  {
+    case LL_RCC_CLKP_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        frequency = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_IC5:
+      if (LL_RCC_IC5_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC5_GetDivider();
+        switch (LL_RCC_IC5_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_IC10:
+      if (LL_RCC_IC10_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC10_GetDivider();
+        switch (LL_RCC_IC10_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_IC19:
+      if (LL_RCC_IC19_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC19_GetDivider();
+        switch (LL_RCC_IC19_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_IC20:
+      if (LL_RCC_IC20_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC20_GetDivider();
+        switch (LL_RCC_IC20_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return DCMIPP clock frequency
+  * @param  DCMIPPxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DCMIPP_CLKSOURCE
+  * @retval DCMIPP clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetDCMIPPClockFreq(uint32_t DCMIPPxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_DCMIPP_CLKSOURCE(DCMIPPxSource));
+
+  switch (LL_RCC_GetDCMIPPClockSource(DCMIPPxSource))
+  {
+    case LL_RCC_DCMIPP_CLKSOURCE_PCLK5:
+      frequency = RCC_GetPCLK5ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_DCMIPP_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_DCMIPP_CLKSOURCE_IC17:
+      if (LL_RCC_IC17_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC17_GetDivider();
+        switch (LL_RCC_IC17_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_DCMIPP_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return ETH clock frequency
+  * @param  ETHxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1_CLKSOURCE
+  * @retval ETH1 clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetETHClockFreq(uint32_t ETHxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_ETH_CLKSOURCE(ETHxSource));
+
+  switch (LL_RCC_GetETHClockSource(ETHxSource))
+  {
+    case LL_RCC_ETH1_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_ETH1_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ETH1_CLKSOURCE_IC12:
+      if (LL_RCC_IC12_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC12_GetDivider();
+        switch (LL_RCC_IC12_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ETH1_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return ETH PTP clock frequency
+  * @param  ETHxPTPSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ETH1PTP_CLKSOURCE
+  * @retval ETH1 PTP clock frequency with divider (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetETHPTPClockFreq(uint32_t ETHxPTPSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_ETHPTP_CLKSOURCE(ETHxPTPSource));
+
+  switch (LL_RCC_GetETHPTPClockSource(ETHxPTPSource))
+  {
+    case LL_RCC_ETH1PTP_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_ETH1PTP_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_ETH1PTP_CLKSOURCE_IC13:
+      if (LL_RCC_IC13_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC13_GetDivider();
+        switch (LL_RCC_IC13_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_ETH1PTP_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  /* Apply divider */
+  if (frequency != LL_RCC_PERIPH_FREQUENCY_NO)
+  {
+    frequency = frequency / ((LL_RCC_GetETH1PTPDivider() >> RCC_CCIPR2_ETH1PTPDIV_Pos) + 1U);
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return FDCAN clock frequency
+  * @param  FDCANxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval FDCAN clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
+  {
+    case LL_RCC_FDCAN_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_IC19:
+      if (LL_RCC_IC19_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC19_GetDivider();
+        switch (LL_RCC_IC19_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return FMC clock frequency
+  * @param  FMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE
+  * @retval FMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetFMCClockSource(FMCxSource))
+  {
+    case LL_RCC_FMC_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_IC3:
+      if (LL_RCC_IC3_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC3_GetDivider();
+        switch (LL_RCC_IC3_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_IC4:
+      if (LL_RCC_IC4_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC4_GetDivider();
+        switch (LL_RCC_IC4_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return I2Cx clock frequency
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C2_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C3_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  * @retval I2C clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+  switch (LL_RCC_GetI2CClockSource(I2CxSource))
+  {
+    case LL_RCC_I2C1_CLKSOURCE_PCLK1:
+    case LL_RCC_I2C2_CLKSOURCE_PCLK1:
+    case LL_RCC_I2C3_CLKSOURCE_PCLK1:
+    case LL_RCC_I2C4_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_CLKP:
+    case LL_RCC_I2C2_CLKSOURCE_CLKP:
+    case LL_RCC_I2C3_CLKSOURCE_CLKP:
+    case LL_RCC_I2C4_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_IC10:
+    case LL_RCC_I2C2_CLKSOURCE_IC10:
+    case LL_RCC_I2C3_CLKSOURCE_IC10:
+    case LL_RCC_I2C4_CLKSOURCE_IC10:
+      if (LL_RCC_IC10_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC10_GetDivider();
+        switch (LL_RCC_IC10_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_IC15:
+    case LL_RCC_I2C2_CLKSOURCE_IC15:
+    case LL_RCC_I2C3_CLKSOURCE_IC15:
+    case LL_RCC_I2C4_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_HSI:
+    case LL_RCC_I2C2_CLKSOURCE_HSI:
+    case LL_RCC_I2C3_CLKSOURCE_HSI:
+    case LL_RCC_I2C4_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_I2C1_CLKSOURCE_MSI:
+    case LL_RCC_I2C2_CLKSOURCE_MSI:
+    case LL_RCC_I2C3_CLKSOURCE_MSI:
+    case LL_RCC_I2C4_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return I3Cx clock frequency
+  * @param  I3CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I3C1_CLKSOURCE
+  *         @arg @ref LL_RCC_I3C2_CLKSOURCE
+  * @retval I3C clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I3C_CLKSOURCE(I3CxSource));
+
+  switch (LL_RCC_GetI3CClockSource(I3CxSource))
+  {
+    case LL_RCC_I3C1_CLKSOURCE_PCLK1:
+    case LL_RCC_I3C2_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_CLKP:
+    case LL_RCC_I3C2_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_IC10:
+    case LL_RCC_I3C2_CLKSOURCE_IC10:
+      if (LL_RCC_IC10_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC10_GetDivider();
+        switch (LL_RCC_IC10_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_IC15:
+    case LL_RCC_I3C2_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_HSI:
+    case LL_RCC_I3C2_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_I3C1_CLKSOURCE_MSI:
+    case LL_RCC_I3C2_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return LPTIMx clock frequency
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM3_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM4_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM5_CLKSOURCE
+  * @retval LPTIM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+  switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+  {
+    case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM3_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM4_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM5_CLKSOURCE_PCLK4:
+      frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM3_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM4_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM5_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM2_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM3_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM4_CLKSOURCE_IC15:
+    case LL_RCC_LPTIM5_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM3_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM4_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM5_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM3_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM4_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM5_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        frequency = LSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM2_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM3_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM4_CLKSOURCE_TIMG:
+    case LL_RCC_LPTIM5_CLKSOURCE_TIMG:
+      frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return LPUART clock frequency
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval LPUART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+  {
+    case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
+      frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return LTDC clock frequency
+  * @param  LTDCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LTDC_CLKSOURCE
+  * @retval LTDC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
+
+  switch (LL_RCC_GetLTDCClockSource(LTDCxSource))
+  {
+    case LL_RCC_LTDC_CLKSOURCE_PCLK5:
+      frequency = RCC_GetPCLK5ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_LTDC_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_LTDC_CLKSOURCE_IC16:
+      if (LL_RCC_IC16_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC16_GetDivider();
+        switch (LL_RCC_IC16_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_LTDC_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return MDFx clock frequency
+  * @param  MDFxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MDF1_CLKSOURCE
+  * @retval MDF clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetMDFClockFreq(uint32_t MDFxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_MDF_CLKSOURCE(MDFxSource));
+
+  switch (LL_RCC_GetMDFClockSource(MDFxSource))
+  {
+    case LL_RCC_MDF1_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_I2S_CKIN:
+      frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_MDF1_CLKSOURCE_TIMG:
+      frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return OTGPHYx clock frequency
+  * @param  OTGPHYxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
+  * @retval OTGPHY clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetOTGPHYClockFreq(uint32_t OTGPHYxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_OTGPHY_CLKSOURCE(OTGPHYxSource));
+
+  switch (LL_RCC_GetOTGPHYClockSource(OTGPHYxSource))
+  {
+    case LL_RCC_OTGPHY1_CLKSOURCE_CLKP:
+    case LL_RCC_OTGPHY2_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_OTGPHY1_CLKSOURCE_IC15:
+    case LL_RCC_OTGPHY2_CLKSOURCE_IC15:
+      if (LL_RCC_IC15_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC15_GetDivider();
+        switch (LL_RCC_IC15_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2:
+    case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        frequency = HSE_VALUE >> 1U;
+      }
+      break;
+
+    case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC:
+    case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
+        {
+          frequency = HSE_VALUE;
+        }
+        else
+        {
+          frequency = HSE_VALUE >> 1U;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return OTGPHYxCKREF clock frequency
+  * @param  OTGPHYxCKREFSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
+  *         @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
+  * @retval OTGPHYCKREF clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetOTGPHYCKREFClockFreq(uint32_t OTGPHYxCKREFSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_OTGPHYCKREF_CLKSOURCE(OTGPHYxCKREFSource));
+
+  switch (LL_RCC_GetOTGPHYCKREFClockSource(OTGPHYxCKREFSource))
+  {
+    case LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1:
+      frequency = LL_RCC_GetOTGPHYClockFreq(LL_RCC_OTGPHY1_CLKSOURCE);
+      break;
+
+    case LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2:
+      frequency = LL_RCC_GetOTGPHYClockFreq(LL_RCC_OTGPHY2_CLKSOURCE);
+      break;
+
+    case LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC:
+    case LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
+        {
+          frequency = HSE_VALUE;
+        }
+        else
+        {
+          frequency = HSE_VALUE >> 1U;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return PSSI clock frequency
+  * @param  PSSIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PSSI_CLKSOURCE
+  * @retval PSSI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_PSSI_CLKSOURCE(PSSIxSource));
+
+  switch (LL_RCC_GetPSSIClockSource(PSSIxSource))
+  {
+    case LL_RCC_PSSI_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_PSSI_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_PSSI_CLKSOURCE_IC20:
+      if (LL_RCC_IC20_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC20_GetDivider();
+        switch (LL_RCC_IC20_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_PSSI_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return SAIx clock frequency
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE
+  * @retval SAI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+  switch (LL_RCC_GetSAIClockSource(SAIxSource))
+  {
+    case LL_RCC_SAI1_CLKSOURCE_PCLK2:
+    case LL_RCC_SAI2_CLKSOURCE_PCLK2:
+      frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_CLKP:
+    case LL_RCC_SAI2_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_IC7:
+    case LL_RCC_SAI2_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_IC8:
+    case LL_RCC_SAI2_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_HSI:
+    case LL_RCC_SAI2_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_MSI:
+    case LL_RCC_SAI2_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SAI2_CLKSOURCE_I2S_CKIN:
+      frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_SPDIFRX1:
+    case LL_RCC_SAI2_CLKSOURCE_SPDIFRX1:
+      frequency = LL_RCC_GetSPDIFRXClockFreq(LL_RCC_SPDIFRX1_CLKSOURCE);
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return SDMMC clock frequency
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
+  *         @arg @ref LL_RCC_SDMMC2_CLKSOURCE
+  * @retval SDMMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
+
+  switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+  {
+    case LL_RCC_SDMMC1_CLKSOURCE_HCLK:
+    case LL_RCC_SDMMC2_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_CLKP:
+    case LL_RCC_SDMMC2_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_IC4:
+    case LL_RCC_SDMMC2_CLKSOURCE_IC4:
+      if (LL_RCC_IC4_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC4_GetDivider();
+        switch (LL_RCC_IC4_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SDMMC1_CLKSOURCE_IC5:
+    case LL_RCC_SDMMC2_CLKSOURCE_IC5:
+      if (LL_RCC_IC5_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC5_GetDivider();
+        switch (LL_RCC_IC5_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return SPDIFRX clock frequency
+  * @param  SPDIFRXxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+  * @retval SPDIF clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
+
+  switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
+  {
+    case LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_IC7:
+      if (LL_RCC_IC7_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC7_GetDivider();
+        switch (LL_RCC_IC7_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN:
+      frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return SPIx clock frequency
+  * @param  SPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI2_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI3_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI4_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI5_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  * @retval SPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
+
+  switch (LL_RCC_GetSPIClockSource(SPIxSource))
+  {
+    case LL_RCC_SPI2_CLKSOURCE_PCLK1:
+    case LL_RCC_SPI3_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_PCLK2:
+    case LL_RCC_SPI4_CLKSOURCE_PCLK2:
+    case LL_RCC_SPI5_CLKSOURCE_PCLK2:
+      frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_SPI6_CLKSOURCE_PCLK4:
+      frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_CLKP:
+    case LL_RCC_SPI2_CLKSOURCE_CLKP:
+    case LL_RCC_SPI3_CLKSOURCE_CLKP:
+    case LL_RCC_SPI4_CLKSOURCE_CLKP:
+    case LL_RCC_SPI5_CLKSOURCE_CLKP:
+    case LL_RCC_SPI6_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_IC8:
+    case LL_RCC_SPI2_CLKSOURCE_IC8:
+    case LL_RCC_SPI3_CLKSOURCE_IC8:
+    case LL_RCC_SPI6_CLKSOURCE_IC8:
+      if (LL_RCC_IC8_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC8_GetDivider();
+        switch (LL_RCC_IC8_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_IC9:
+    case LL_RCC_SPI2_CLKSOURCE_IC9:
+    case LL_RCC_SPI3_CLKSOURCE_IC9:
+    case LL_RCC_SPI4_CLKSOURCE_IC9:
+    case LL_RCC_SPI5_CLKSOURCE_IC9:
+    case LL_RCC_SPI6_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPI4_CLKSOURCE_IC14:
+    case LL_RCC_SPI5_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_HSI:
+    case LL_RCC_SPI2_CLKSOURCE_HSI:
+    case LL_RCC_SPI3_CLKSOURCE_HSI:
+    case LL_RCC_SPI4_CLKSOURCE_HSI:
+    case LL_RCC_SPI5_CLKSOURCE_HSI:
+    case LL_RCC_SPI6_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_MSI:
+    case LL_RCC_SPI2_CLKSOURCE_MSI:
+    case LL_RCC_SPI3_CLKSOURCE_MSI:
+    case LL_RCC_SPI4_CLKSOURCE_MSI:
+    case LL_RCC_SPI5_CLKSOURCE_MSI:
+    case LL_RCC_SPI6_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SPI1_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SPI2_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SPI3_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
+      frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SPI4_CLKSOURCE_HSE:
+    case LL_RCC_SPI5_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return UARTx clock frequency
+  * @param  UARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_UART4_CLKSOURCE
+  *         @arg @ref LL_RCC_UART5_CLKSOURCE
+  *         @arg @ref LL_RCC_UART7_CLKSOURCE
+  *         @arg @ref LL_RCC_UART8_CLKSOURCE
+  *         @arg @ref LL_RCC_UART9_CLKSOURCE
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+
+  switch (LL_RCC_GetUARTClockSource(UARTxSource))
+  {
+    case LL_RCC_UART4_CLKSOURCE_PCLK1:
+    case LL_RCC_UART5_CLKSOURCE_PCLK1:
+    case LL_RCC_UART7_CLKSOURCE_PCLK1:
+    case LL_RCC_UART8_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_UART9_CLKSOURCE_PCLK2:
+      frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_CLKP:
+    case LL_RCC_UART5_CLKSOURCE_CLKP:
+    case LL_RCC_UART7_CLKSOURCE_CLKP:
+    case LL_RCC_UART8_CLKSOURCE_CLKP:
+    case LL_RCC_UART9_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_IC9:
+    case LL_RCC_UART5_CLKSOURCE_IC9:
+    case LL_RCC_UART7_CLKSOURCE_IC9:
+    case LL_RCC_UART8_CLKSOURCE_IC9:
+    case LL_RCC_UART9_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_IC14:
+    case LL_RCC_UART5_CLKSOURCE_IC14:
+    case LL_RCC_UART7_CLKSOURCE_IC14:
+    case LL_RCC_UART8_CLKSOURCE_IC14:
+    case LL_RCC_UART9_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_HSI:
+    case LL_RCC_UART5_CLKSOURCE_HSI:
+    case LL_RCC_UART7_CLKSOURCE_HSI:
+    case LL_RCC_UART8_CLKSOURCE_HSI:
+    case LL_RCC_UART9_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_MSI:
+    case LL_RCC_UART5_CLKSOURCE_MSI:
+    case LL_RCC_UART7_CLKSOURCE_MSI:
+    case LL_RCC_UART8_CLKSOURCE_MSI:
+    case LL_RCC_UART9_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_UART4_CLKSOURCE_LSE:
+    case LL_RCC_UART5_CLKSOURCE_LSE:
+    case LL_RCC_UART7_CLKSOURCE_LSE:
+    case LL_RCC_UART8_CLKSOURCE_LSE:
+    case LL_RCC_UART9_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return USARTx clock frequency
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART1_CLKSOURCE
+  *         @arg @ref LL_RCC_USART2_CLKSOURCE
+  *         @arg @ref LL_RCC_USART3_CLKSOURCE
+  *         @arg @ref LL_RCC_USART6_CLKSOURCE
+  *         @arg @ref LL_RCC_USART10_CLKSOURCE
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+  switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+  {
+    case LL_RCC_USART1_CLKSOURCE_PCLK2:
+    case LL_RCC_USART6_CLKSOURCE_PCLK2:
+    case LL_RCC_USART10_CLKSOURCE_PCLK2:
+      frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_USART2_CLKSOURCE_PCLK1:
+    case LL_RCC_USART3_CLKSOURCE_PCLK1:
+      frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_CLKP:
+    case LL_RCC_USART2_CLKSOURCE_CLKP:
+    case LL_RCC_USART3_CLKSOURCE_CLKP:
+    case LL_RCC_USART6_CLKSOURCE_CLKP:
+    case LL_RCC_USART10_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_IC9:
+    case LL_RCC_USART2_CLKSOURCE_IC9:
+    case LL_RCC_USART3_CLKSOURCE_IC9:
+    case LL_RCC_USART6_CLKSOURCE_IC9:
+    case LL_RCC_USART10_CLKSOURCE_IC9:
+      if (LL_RCC_IC9_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC9_GetDivider();
+        switch (LL_RCC_IC9_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_IC14:
+    case LL_RCC_USART2_CLKSOURCE_IC14:
+    case LL_RCC_USART3_CLKSOURCE_IC14:
+    case LL_RCC_USART6_CLKSOURCE_IC14:
+    case LL_RCC_USART10_CLKSOURCE_IC14:
+      if (LL_RCC_IC14_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC14_GetDivider();
+        switch (LL_RCC_IC14_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_HSI:
+    case LL_RCC_USART2_CLKSOURCE_HSI:
+    case LL_RCC_USART3_CLKSOURCE_HSI:
+    case LL_RCC_USART6_CLKSOURCE_HSI:
+    case LL_RCC_USART10_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_MSI:
+    case LL_RCC_USART2_CLKSOURCE_MSI:
+    case LL_RCC_USART3_CLKSOURCE_MSI:
+    case LL_RCC_USART6_CLKSOURCE_MSI:
+    case LL_RCC_USART10_CLKSOURCE_MSI:
+      if (LL_RCC_MSI_IsReady() != 0U)
+      {
+        frequency = MSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_USART1_CLKSOURCE_LSE:
+    case LL_RCC_USART2_CLKSOURCE_LSE:
+    case LL_RCC_USART3_CLKSOURCE_LSE:
+    case LL_RCC_USART6_CLKSOURCE_LSE:
+    case LL_RCC_USART10_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Unexpected case */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return XSPI clock frequency
+  * @param  XSPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_XSPI1_CLKSOURCE
+  *         @arg @ref LL_RCC_XSPI2_CLKSOURCE
+  *         @arg @ref LL_RCC_XSPI3_CLKSOURCE
+  * @retval XSPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+
+uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource)
+{
+  uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  uint32_t ic_divider;
+
+  switch (LL_RCC_GetXSPIClockSource(XSPIxSource))
+  {
+    case LL_RCC_XSPI1_CLKSOURCE_HCLK:
+    case LL_RCC_XSPI2_CLKSOURCE_HCLK:
+    case LL_RCC_XSPI3_CLKSOURCE_HCLK:
+      frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
+      break;
+
+    case LL_RCC_XSPI1_CLKSOURCE_CLKP:
+    case LL_RCC_XSPI2_CLKSOURCE_CLKP:
+    case LL_RCC_XSPI3_CLKSOURCE_CLKP:
+      frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_XSPI1_CLKSOURCE_IC3:
+    case LL_RCC_XSPI2_CLKSOURCE_IC3:
+    case LL_RCC_XSPI3_CLKSOURCE_IC3:
+      if (LL_RCC_IC3_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC3_GetDivider();
+        switch (LL_RCC_IC3_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    case LL_RCC_XSPI1_CLKSOURCE_IC4:
+    case LL_RCC_XSPI2_CLKSOURCE_IC4:
+    case LL_RCC_XSPI3_CLKSOURCE_IC4:
+      if (LL_RCC_IC4_IsEnabled() != 0U)
+      {
+        ic_divider = LL_RCC_IC4_GetDivider();
+        switch (LL_RCC_IC4_GetSource())
+        {
+          case LL_RCC_ICCLKSOURCE_PLL1:
+            frequency = LL_RCC_GetPLL1ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL2:
+            frequency = LL_RCC_GetPLL2ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL3:
+            frequency = LL_RCC_GetPLL3ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          case LL_RCC_ICCLKSOURCE_PLL4:
+            frequency = LL_RCC_GetPLL4ClockFreq();
+            frequency = frequency / ic_divider;
+            break;
+          default:
+            /* Unexpected case */
+            break;
+        }
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Return HCLK clock frequency
+  * @param  SYSCLK_Frequency SYSCLK clock frequency
+  * @retval HCLK clock frequency (in Hz)
+  */
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+  /* HCLK clock frequency */
+  return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return PCLK1 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK1 clock frequency */
+  return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return PCLK2 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK2 clock frequency */
+  return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return PCLK4 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK4 clock frequency (in Hz)
+  */
+static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK4 clock frequency */
+  return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
+}
+
+/**
+  * @brief  Return PCLK5 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK5 clock frequency (in Hz)
+  */
+static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK5 clock frequency */
+  return LL_RCC_CALC_PCLK5_FREQ(HCLK_Frequency, LL_RCC_GetAPB5Prescaler());
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rng.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rng.c
new file mode 100644
index 000000000..e17affc98
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rng.c
@@ -0,0 +1,158 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_rng.c
+  * @author  MCD Application Team
+  * @brief   RNG LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_rng.h"
+#include "stm32n6xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @addtogroup RNG_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Private_Macros RNG Private Macros
+  * @{
+  */
+#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
+                                 ((__MODE__) == LL_RNG_CED_DISABLE))
+
+#define IS_LL_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) ((__CLOCK_DIV__) <=0x0Fu)
+
+
+#define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \
+                                                        ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))
+
+#define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
+
+#define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
+
+#define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RNG_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize RNG registers (Registers restored to their default values).
+  * @param  RNGx RNG Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RNG registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+  if (RNGx == RNG)
+  {
+    /* Enable RNG reset state */
+    LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG);
+
+    /* Release RNG from reset state */
+    LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize RNG registers according to the specified parameters in RNG_InitStruct.
+  * @param  RNGx RNG Instance
+  * @param  RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
+  *         that contains the configuration information for the specified RNG peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+  assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
+
+  /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
+  MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_InitStruct->ClockErrorDetection | RNG_CR_CONDRST);
+  /* Writing bits CONDRST=0*/
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
+  * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
+  *                       whose fields will be set to default values.
+  * @retval None
+  */
+void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
+{
+  /* Set RNG_InitStruct fields to default values */
+  RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
+
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rtc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rtc.c
new file mode 100644
index 000000000..95eb09cef
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_rtc.c
@@ -0,0 +1,855 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_rtc.c
+  * @author  GPM Application Team
+  * @brief   RTC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_rtc.h"
+#include "stm32n6xx_ll_cortex.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+  * @{
+  */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT     ((uint32_t) 0x0000007FU)
+#define RTC_SYNCH_PRESC_DEFAULT      ((uint32_t) 0x000000FFU)
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT         ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT          ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+                                         || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+                                     || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+                                          || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+                                      || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+                                      || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+                                      || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+                                      || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+                                      || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+                                      || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
+
+#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+                                        || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+                                        || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RTC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-Initializes the RTC registers to their default reset values.
+  * @note   This function does not reset the RTC Clock source and RTC Backup Data
+  *         registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are de-initialized
+  *          - ERROR: RTC registers are not de-initialized
+  */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    WRITE_REG(RTCx->TR,       0U);
+    WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+    WRITE_REG(RTCx->CR,       0U);
+    WRITE_REG(RTCx->WUTR,     RTC_WUTR_WUT);
+    WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+    WRITE_REG(RTCx->ALRMAR,   0U);
+    WRITE_REG(RTCx->ALRMBR,   0U);
+    WRITE_REG(RTCx->SHIFTR,   0U);
+    WRITE_REG(RTCx->CALR,     0U);
+    WRITE_REG(RTCx->ALRMASSR, 0U);
+    WRITE_REG(RTCx->ALRMBSSR, 0U);
+    WRITE_REG(RTCx->PRIVCFGR, 0U);
+#if defined (CPU_IN_SECURE_STATE)
+    WRITE_REG(RTCx->SECCFGR,  0U);
+#endif /* defined (CPU_IN_SECURE_STATE) */
+
+    /* Clear some bits of RTC_ICSR and exit Initialization mode */
+    CLEAR_BIT(RTCx->ICSR, RTC_ICSR_BCDU_Msk | RTC_ICSR_BIN_Msk | RTC_ICSR_INIT);
+
+    /* Wait till the RTC RSF flag is set */
+    status = LL_RTC_WaitForSynchro(RTCx);
+  }
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  /* DeInitialization of the TAMP registers */
+  WRITE_REG(TAMP->CR1,        0U);
+  WRITE_REG(TAMP->CR2,        0U);
+  WRITE_REG(TAMP->CR3,        0U);
+#if defined (CPU_IN_SECURE_STATE)
+  WRITE_REG(TAMP->SECCFGR,    0U);
+#endif /* defined (CPU_IN_SECURE_STATE) */
+  WRITE_REG(TAMP->PRIVCFGR,   0U);
+  WRITE_REG(TAMP->FLTCR,      0U);
+  WRITE_REG(TAMP->ATCR1,      0x00070000U);
+  WRITE_REG(TAMP->ATCR2,      0U);
+  WRITE_REG(TAMP->IER,        0U);
+  WRITE_REG(TAMP->SCR,        0xFFFFFFFFU);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters
+  *         in RTC_InitStruct.
+  * @param  RTCx RTC Instance
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in
+  *         initialization mode only.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized
+  */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+  assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+  assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Set Hour Format */
+    LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+    /* Configure Synchronous and Asynchronous prescaler factor */
+    LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+    LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    status = SUCCESS;
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  /* Set RTC_InitStruct fields to default values */
+  RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
+  RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+  RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+    }
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+                         RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+    }
+    else
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+  RTC_TimeStruct->Hours      = 0U;
+  RTC_TimeStruct->Minutes    = 0U;
+  RTC_TimeStruct->Seconds    = 0U;
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Day register is configured
+  *          - ERROR: RTC Day register is not configured
+  */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+  {
+    RTC_DateStruct->Month = (uint8_t)((uint32_t) RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+  }
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+    assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+    assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+  }
+  else
+  {
+    assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+    assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+    assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+  }
+  assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month,
+                         RTC_DateStruct->Year);
+    }
+    else
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+  * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+  RTC_DateStruct->Day     = 1U;
+  RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
+  RTC_DateStruct->Year    = 0U;
+}
+
+/**
+  * @brief  Set the RTC Alarm A.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMA registers are configured
+  *          - ERROR: ALARMA registers are not configured
+  */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMA_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMA_EnableWeekday(RTCx);
+    LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the RTC Alarm B.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (@ref LL_RTC_ALMB_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMB registers are configured
+  *          - ERROR: ALARMB registers are not configured
+  */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMB_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMB_EnableWeekday(RTCx);
+    LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode
+  */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+  ErrorStatus status = SUCCESS;
+  uint32_t tmp;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Check if the Initialization mode is set */
+  if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+  {
+    /* Set the Initialization mode */
+    LL_RTC_EnableInitMode(RTCx);
+
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+    while ((timeout != 0U) && (tmp != 1U))
+    {
+      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+      {
+        timeout --;
+      }
+      tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+      if (timeout == 0U)
+      {
+        status = ERROR;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Exit the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts
+  *         counting after 4 RTCCLK cycles.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC exited from in Init mode
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable initialization mode */
+  LL_RTC_DisableInitMode(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar
+  *         initialization, calendar update or after wakeup from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+  uint32_t      tmp;
+  ErrorStatus   status  = SUCCESS;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Clear RSF flag */
+  LL_RTC_ClearFlag_RS(RTCx);
+
+  /* Wait the registers to be synchronised */
+  tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+  while ((timeout != 0U) && (tmp != 1U))
+  {
+    if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+    {
+      timeout--;
+    }
+    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+  }
+
+  if (timeout == 0U)
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RTC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_sdmmc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_sdmmc.c
new file mode 100644
index 000000000..9d7225b17
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_sdmmc.c
@@ -0,0 +1,2111 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_sdmmc.c
+  * @author  MCD Application Team
+  * @brief   SDMMC Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the SDMMC peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                       ##### SDMMC peripheral features #####
+  ==============================================================================
+    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+         devices.
+
+    [..] The SDMMC features include the following:
+         (+) Full compliance with MultiMediaCard System Specification Version 4.51. Card support
+             for three different databus modes: 1-bit (default), 4-bit and 8-bit.
+         (+) Full compatibility with previous versions of MultiMediaCards (backward compatibility).
+         (+) Full compliance with SD memory card specifications version 4.1.
+             (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
+              UHS-II mode not supported).
+         (+) Full compliance with SDIO card specification version 4.0. Card support
+             for two different databus modes: 1-bit (default) and 4-bit.
+             (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and
+              UHS-II mode not supported).
+         (+) Data transfer up to 208 Mbyte/s for the 8 bit mode. (depending maximum allowed IO speed).
+         (+) Data and command output enable signals to control external bidirectional drivers
+
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers
+      that interfaces with the SDMMC peripheral.
+      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
+      is used in the device's driver to perform SDMMC operations and functionalities.
+
+      This driver is almost transparent for the final user, it is only used to implement other
+      functionalities of the external device.
+
+    [..]
+      (+) The SDMMC clock is coming from output of PLL1_Q or PLL2_R.
+       Before start working with SDMMC peripheral make sure that the PLL is well configured.
+          The SDMMC peripheral uses two clock signals:
+          (++) PLL1_Q bus clock (default after reset)
+          (++) PLL2_R bus clock
+
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+          peripheral.
+
+      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
+          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
+
+      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
+          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
+
+      (+) When using the DMA mode
+          (++) Configure the IDMA mode (Single buffer or double)
+          (++) Configure the buffer address
+          (++) Configure Data Path State Machine
+
+      (+) To control the CPSM (Command Path State Machine) and send
+          commands to the card use the SDMMC_SendCommand(SDMMCx),
+          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
+          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
+          to the selected command to be sent.
+          The parameters that should be filled are:
+           (++) Command Argument
+           (++) Command Index
+           (++) Command Response type
+           (++) Command Wait
+           (++) CPSM Status (Enable or Disable).
+
+          -@@- To check if the command is well received, read the SDMMC_CMDRESP
+              register using the SDMMC_GetCommandResponse().
+              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
+              SDMMC_GetResponse() function.
+
+      (+) To control the DPSM (Data Path State Machine) and send/receive
+           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
+          SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
+
+    *** Read Operations ***
+    =======================
+    [..]
+      (#) First, user has to fill the data structure (pointer to
+          SDMMC_DataInitTypeDef) according to the selected data type to be received.
+          The parameters that should be filled are:
+           (++) Data TimeOut
+           (++) Data Length
+           (++) Data Block size
+           (++) Data Transfer direction: should be from card (To SDMMC)
+           (++) Data Transfer mode
+           (++) DPSM Status (Enable or Disable)
+
+      (#) Configure the SDMMC resources to receive the data from the card
+          according to selected transfer mode (Refer to Step 8, 9 and 10).
+
+      (#) Send the selected Read command (refer to step 11).
+
+      (#) Use the SDMMC flags/interrupts to check the transfer status.
+
+    *** Write Operations ***
+    ========================
+    [..]
+     (#) First, user has to fill the data structure (pointer to
+         SDMMC_DataInitTypeDef) according to the selected data type to be received.
+         The parameters that should be filled are:
+          (++) Data TimeOut
+          (++) Data Length
+          (++) Data Block size
+          (++) Data Transfer direction:  should be to card (To CARD)
+          (++) Data Transfer mode
+          (++) DPSM Status (Enable or Disable)
+
+     (#) Configure the SDMMC resources to send the data to the card according to
+         selected transfer mode.
+
+     (#) Send the selected Write command.
+
+     (#) Use the SDMMC flags/interrupts to check the transfer status.
+
+    *** Command management operations ***
+    =====================================
+    [..]
+     (#) The commands used for Read/Write/Erase operations are managed in
+         separate functions.
+         Each function allows to send the needed command with the related argument,
+         then check the response.
+         By the same approach, you could implement a command and check the response.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+  * @brief Low layer module for SD
+  * @{
+  */
+
+#if defined (SDMMC1) || defined (SDMMC2)
+#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED)  || defined (HAL_SDIO_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDMMC according to the specified
+  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
+  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+
+  /* Set SDMMC configuration parameters */
+  tmpreg |= (Init.ClockEdge           | \
+             Init.ClockPowerSave      | \
+             Init.BusWide             | \
+             Init.HardwareFlowControl | \
+             Init.ClockDiv
+            );
+
+  /* Write to SDMMC CLKCR */
+  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### I/O operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the SDMMC data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling)
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx)
+{
+  /* Read data from Rx FIFO */
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Write data (word) to Tx FIFO in blocking mode (polling)
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+{
+  /* Write data to FIFO */
+  SDMMCx->FIFO = *pWriteData;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SDMMC data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set SDMMC Power state to ON.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to ON */
+  SDMMCx->POWER |= SDMMC_POWER_PWRCTRL;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set SDMMC Power state to Power-Cycle.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to Power Cycle*/
+  SDMMCx->POWER |= SDMMC_POWER_PWRCTRL_1;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set SDMMC Power state to OFF.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to OFF */
+  SDMMCx->POWER &= ~(SDMMC_POWER_PWRCTRL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get SDMMC Power state.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Power status of the controller. The returned value can be one of the
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON
+  */
+uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+}
+
+/**
+  * @brief  Configure the SDMMC command path according to the specified parameters in
+  *         SDMMC_CmdInitTypeDef structure and send the command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
+  *         the configuration information for the SDMMC command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
+  assert_param(IS_SDMMC_RESPONSE(Command->Response));
+  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDMMC_CPSM(Command->CPSM));
+
+  /* Set the SDMMC Argument value */
+  SDMMCx->ARG = Command->Argument;
+
+  /* Set SDMMC command parameters */
+  tmpreg |= (uint32_t)(Command->CmdIndex         | \
+                       Command->Response         | \
+                       Command->WaitForInterrupt | \
+                       Command->CPSM);
+
+  /* Write to SDMMC CMD register */
+  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return the command index of last command for which response received
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx)
+{
+  return (uint8_t)(SDMMCx->RESPCMD);
+}
+
+
+/**
+  * @brief  Return the response received from the card for the last command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Response: Specifies the SDMMC response register.
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_RESP1: Response Register 1
+  *            @arg SDMMC_RESP2: Response Register 2
+  *            @arg SDMMC_RESP3: Response Register 3
+  *            @arg SDMMC_RESP4: Response Register 4
+  * @retval The Corresponding response register value
+  */
+uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_RESP(Response));
+
+  /* Get the response */
+  tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response;
+
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @brief  Configure the SDMMC data path according to the specified
+  *         parameters in the SDMMC_DataInitTypeDef.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure
+  *         that contains the configuration information for the SDMMC data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
+  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDMMC_DPSM(Data->DPSM));
+
+  /* Set the SDMMC Data TimeOut value */
+  SDMMCx->DTIMER = Data->DataTimeOut;
+
+  /* Set the SDMMC DataLength value */
+  SDMMCx->DLEN = Data->DataLength;
+
+  /* Set the SDMMC data configuration parameters */
+  tmpreg |= (uint32_t)(Data->DataBlockSize | \
+                       Data->TransferDir   | \
+                       Data->TransferMode  | \
+                       Data->DPSM);
+
+  /* Write to SDMMC DCTRL */
+  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->DCOUNT);
+}
+
+/**
+  * @brief  Get the FIFO data
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Data received
+  */
+uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+  * @retval None
+  */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
+
+  /* Set SDMMC read wait mode */
+  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+ ===============================================================================
+                   ##### Commands management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send the Data Block Length command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Data Block number command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockCount;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCK_COUNT;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCK_COUNT, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Single Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Multi Block command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command for SD and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command and check the response
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Erase command and check the response
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  EraseType Type of erase to be performed
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Set Block Size for Card */
+  sdmmc_cmdinit.Argument         = EraseType;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Stop Transfer command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD12 STOP_TRANSMISSION  */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+
+  __SDMMC_CMDSTOP_ENABLE(SDMMCx);
+  __SDMMC_CMDTRANS_DISABLE(SDMMCx);
+
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT);
+
+  __SDMMC_CMDSTOP_DISABLE(SDMMCx);
+
+  /* Ignore Address Out Of Range Error, Not relevant at end of memory */
+  if (errorstate == SDMMC_ERROR_ADDR_OUT_OF_RANGE)
+  {
+    errorstate = SDMMC_ERROR_NONE;
+  }
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Select Deselect command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  addr: Address of the card to be selected
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Go Idle State command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdError(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Operating Condition command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp7(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Application command to verify that that the next command
+  *         is an application specific com-mand rather than a standard command
+  *         and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  /* If there is a HAL_ERROR, it is a MMC card, else
+  it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating
+  *         condition register (OCR)
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Bus Width command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  BusWidth: BusWidth
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send SCR command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD51 SD_APP_SEND_SCR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CID command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD2 ALL_SEND_CID */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pRCA: Card RCA
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Set Relative Address command to MMC card (not SD card).
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  RCA Card RCA
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = ((uint32_t)RCA << 16U);
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Sleep command to MMC card (not SD card).
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  Argument Argument of the command (RCA and Sleep/Awake)
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_MMC_SLEEP_AWAKE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status register command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Sends host capacity support information and activates the card's
+  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDMMCx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+  /* CMD Response: R1 */
+  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN*/
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating
+  *         condition register (OCR)
+  * @param  None
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = 0x00000000;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_VOLTAGE_SWITCH;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_VOLTAGE_SWITCH, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send EXT_CSD command and check the response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Execute a cmd52 to write single byte data and read single byte data if needed
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument:  SDMMC command argument which is sent to a card as part of a command message
+  * @param  pData: pointer to read response if needed
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SDMMC_RW_DIRECT;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_DIRECT, pResponse);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Execute a cmd53 to write or read multiple data with a single command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: SDMMC command argument which is sent to a card as part of a command message
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SDMMC_RW_EXTENDED;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_EXTENDED, NULL);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Execute a cmd5 to write or read multiple data with a single command
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Argument: SDMMC command argument which is sent to a card as part of a command message
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp)
+{
+  SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+  uint32_t             errorstate;
+
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SDMMC_SEN_OP_COND;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp4(SDMMCx, pResp);
+
+  return errorstate;
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+  *  @brief   Responses functions
+  *
+@verbatim
+ ===============================================================================
+                   ##### Responses management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed responses.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The Timeout is expressed in ms */
+  uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT |
+                        SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+
+  /* We have received response, retrieve it for analysis  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    return SDMMC_ERROR_NONE;
+  }
+  else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+  {
+    return SDMMC_ERROR_ADDR_MISALIGNED;
+  }
+  else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+  {
+    return SDMMC_ERROR_BLOCK_LEN_ERR;
+  }
+  else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+  {
+    return SDMMC_ERROR_ERASE_SEQ_ERR;
+  }
+  else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+  {
+    return SDMMC_ERROR_BAD_ERASE_PARAM;
+  }
+  else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+  {
+    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+  }
+  else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+  {
+    return SDMMC_ERROR_CARD_ECC_FAILED;
+  }
+  else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+  {
+    return SDMMC_ERROR_CC_ERR;
+  }
+  else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+  {
+    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+  }
+  else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+  }
+  else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+  {
+    return SDMMC_ERROR_CID_CSD_OVERWRITE;
+  }
+  else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+  {
+    return SDMMC_ERROR_WP_ERASE_SKIP;
+  }
+  else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+  {
+    return SDMMC_ERROR_CARD_ECC_DISABLED;
+  }
+  else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+  {
+    return SDMMC_ERROR_ERASE_RESET;
+  }
+  else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+  {
+    return SDMMC_ERROR_AKE_SEQ_ERR;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R4 response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pResp: pointer to response
+  * @retval error state
+  */
+uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp)
+{
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+  {
+    /* Clear all the static flags */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* We have received response, retrieve it.  */
+  *pResp = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R5 (cmd52/cmd53) response.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  SDIO_CMD: The sent command index
+  * @param  pData: pointer to the read/write buffer needed for cmd52
+  * @retval SDIO Card error state
+  */
+uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData)
+{
+  uint32_t response_r5;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SDIO_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* We have received response, retrieve it.  */
+  response_r5 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  if ((response_r5 & SDMMC_SDIO_R5_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    /* we only want 8 bit read or write data and the 8 bit response flags are masked in the data pointer */
+    if (pData != NULL)
+    {
+      *pData = (uint8_t)(response_r5 & 0xFFU);
+    }
+
+    return SDMMC_ERROR_NONE;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_OUT_OF_RANGE) == SDMMC_SDIO_R5_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) == SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER)
+  {
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_ILLEGAL_CMD) == SDMMC_SDIO_R5_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if ((response_r5 & SDMMC_SDIO_R5_COM_CRC_FAILED) == SDMMC_SDIO_R5_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative
+  *         address RCA
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Check response received is of desired command */
+  if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  /* We have received response, retrieve it.  */
+  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
+
+  if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
+                      SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+  {
+    *pRCA = (uint16_t)(response_r1 >> 16);
+
+    return SDMMC_ERROR_NONE;
+  }
+  else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDMMCx->STA;
+  } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+           ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+  {
+    /* Card is not SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
+
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+
+  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+  {
+    /* Card is not SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
+
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
+  }
+
+  return SDMMC_ERROR_NONE;
+
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SDMMC_LL_Group6 Linked List functions
+  *  @brief   Linked List management functions
+  *
+@verbatim
+ ===============================================================================
+                   ##### Linked List management functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the needed functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Build new Linked List node.
+  * @param  pNode: Pointer to new node to add.
+  * @param  pNodeConf: Pointer to configuration parameters for new node to add.
+  * @retval Error status
+  */
+uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf)
+{
+
+  if ((pNode == NULL) || (pNodeConf == NULL))
+  {
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+  /* Configure the Link Node registers*/
+  pNode->IDMABASER = pNodeConf->BufferAddress;
+  pNode->IDMABSIZE = pNodeConf->BufferSize;
+  pNode->IDMALAR   = SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ABR;
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Insert new Linked List node.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @param  pPrevNode: Pointer to previous node .
+  * @param  pNewNode: Pointer to new node to add.
+  * @retval Error status
+  */
+uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode,
+                                        SDMMC_DMALinkNodeTypeDef *pNode)
+{
+  uint32_t link_list_offset;
+  uint32_t node_address = (uint32_t) pNode;
+
+  /* First Node */
+  if (pLinkedList->NodesCounter == 0U)
+  {
+
+    pLinkedList->pHeadNode = pNode;
+    pLinkedList->pTailNode = pNode;
+    pLinkedList->NodesCounter = 1U;
+
+  }
+  else if (pPrevNode == pLinkedList->pTailNode)
+  {
+    if (pNode <= pLinkedList->pHeadNode)
+    {
+      /* Node Address should greater than Head Node Address*/
+      return SDMMC_ERROR_INVALID_PARAMETER;
+    }
+
+    /*Last Node, no next node */
+    MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, 0U);
+
+    /*link Prev node with new one */
+    MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, SDMMC_IDMALAR_ULA);
+    MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, (node_address - (uint32_t)pLinkedList->pHeadNode));
+
+    pLinkedList->NodesCounter ++;
+    pLinkedList->pTailNode = pNode;
+
+  }
+  else
+  {
+
+    if (pNode <= pLinkedList->pHeadNode)
+    {
+      /* Node Address should greater than Head Node Address*/
+      return SDMMC_ERROR_INVALID_PARAMETER;
+    }
+
+    /*link New node with Next one */
+    link_list_offset = pNode->IDMALAR;
+    MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, link_list_offset);
+
+    /*link Prev node with new one */
+    MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_ULA, SDMMC_IDMALAR_ULA);
+    MODIFY_REG(pPrevNode->IDMALAR, SDMMC_IDMALAR_IDMALA, (node_address - (uint32_t)pLinkedList->pHeadNode));
+
+    pLinkedList->NodesCounter ++;
+
+  }
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Remove  node from the Linked List.
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @param  pNode: Pointer to new node to add.
+  * @retval Error status
+   */
+uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode)
+{
+  uint32_t count = 0U;
+  uint32_t linked_list_offset;
+  SDMMC_DMALinkNodeTypeDef *prev_node = NULL;
+  SDMMC_DMALinkNodeTypeDef *curr_node ;
+
+  /* First Node */
+  if (pLinkedList->NodesCounter == 0U)
+  {
+
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+  else
+  {
+    curr_node = pLinkedList->pHeadNode;
+    while ((curr_node != pNode) && (count <= pLinkedList->NodesCounter))
+    {
+      prev_node = curr_node;
+      curr_node = (SDMMC_DMALinkNodeTypeDef *)((prev_node->IDMALAR & SDMMC_IDMALAR_IDMALA) +
+                                               (uint32_t)pLinkedList->pHeadNode);
+      count++;
+    }
+
+    if ((count == 0U) || (count > pLinkedList->NodesCounter))
+    {
+      /* Node not found in the linked list */
+      return SDMMC_ERROR_INVALID_PARAMETER;
+    }
+
+    pLinkedList->NodesCounter--;
+
+    if (pLinkedList->NodesCounter == 0U)
+    {
+      pLinkedList->pHeadNode = 0U;
+      pLinkedList->pTailNode = 0U;
+    }
+    else
+    {
+      /*link prev node with next one */
+      linked_list_offset = curr_node->IDMALAR;
+      MODIFY_REG(prev_node->IDMALAR, SDMMC_IDMALAR_IDMALA, linked_list_offset);
+      /* Configure the new Link Node registers*/
+      pNode->IDMALAR    |= linked_list_offset;
+
+      pLinkedList->pTailNode = prev_node;
+    }
+  }
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Lock Linked List Node
+  * @param  pNode: Pointer to node to lock.
+  * @retval Error status
+
+  */
+uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode)
+{
+
+  if (pNode == NULL)
+  {
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+
+  MODIFY_REG(pNode->IDMALAR, SDMMC_IDMALAR_ABR, 0U);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Unlock Linked List Node
+  * @param  pNode: Pointer to node to unlock.
+  * @retval Error status
+
+  */
+uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode)
+{
+
+  if (pNode == NULL)
+  {
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+
+  MODIFY_REG(pNode->IDMALAR, SDMMC_IDMALAR_ABR, SDMMC_IDMALAR_ABR);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Enable Linked List circular mode
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @retval Error status
+
+  */
+uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+  if (pLinkedList == NULL)
+  {
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+
+  MODIFY_REG(pLinkedList->pTailNode->IDMALAR, SDMMC_IDMALAR_ULA | SDMMC_IDMALAR_IDMALA, SDMMC_IDMALAR_ULA);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Disable DMA Linked List Circular mode
+  * @param  pLinkedList: Pointer to the linkedlist that contains transfer nodes
+  * @retval Error status
+   */
+uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList)
+{
+
+  if (pLinkedList == NULL)
+  {
+    return SDMMC_ERROR_INVALID_PARAMETER;
+  }
+
+  MODIFY_REG(pLinkedList->pTailNode->IDMALAR, SDMMC_IDMALAR_ULA, 0U);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @}
+  */
+
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDMMC_CMDTIMEOUT is expressed in ms */
+  uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+
+  } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+
+  /* Clear all the static flags */
+  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
+#endif /* SDMMC1 || SDMMC2 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_spi.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_spi.c
new file mode 100644
index 000000000..843b81879
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_spi.c
@@ -0,0 +1,758 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_spi.c
+  * @author  MCD Application Team
+  * @brief   SPI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_spi.h"
+#include "stm32n6xx_ll_bus.h"
+#include "stm32n6xx_ll_rcc.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
+
+/** @addtogroup SPI_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup SPI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_SPI_MODE(__VALUE__)                   (((__VALUE__) == LL_SPI_MODE_MASTER)         || \
+                                                     ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_SS_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
+
+#define IS_LL_SPI_ID_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
+
+#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
+                                                     ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
+
+#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
+                                                     ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
+
+#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__)    (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
+                                                     ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED)    || \
+                                                     ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
+
+#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__)  (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
+                                                     ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME)   || \
+                                                     ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
+
+#define IS_LL_SPI_PROTOCOL(__VALUE__)               (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA)           || \
+                                                     ((__VALUE__) == LL_SPI_PROTOCOL_TI))
+
+#define IS_LL_SPI_PHASE(__VALUE__)                  (((__VALUE__) == LL_SPI_PHASE_1EDGE)                 || \
+                                                     ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_POLARITY(__VALUE__)               (((__VALUE__) == LL_SPI_POLARITY_LOW)                || \
+                                                     ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__)      (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_BYPASS)    || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)      || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)      || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)     || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)     || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)     || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128)    || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__)               (((__VALUE__) == LL_SPI_LSB_FIRST)                   || \
+                                                     ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)     (((__VALUE__) == LL_SPI_FULL_DUPLEX)                 || \
+                                                     ((__VALUE__) == LL_SPI_SIMPLEX_TX)                  || \
+                                                     ((__VALUE__) == LL_SPI_SIMPLEX_RX)                  || \
+                                                     ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX)              || \
+                                                     ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__)              (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
+
+#define IS_LL_SPI_FIFO_TH(__VALUE__)                (((__VALUE__) == LL_SPI_FIFO_TH_01DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_02DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_03DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_04DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_05DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_06DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_07DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_08DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_09DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_10DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_11DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_12DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_13DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_14DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_15DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
+
+#define IS_LL_SPI_CRC(__VALUE__)                    (((__VALUE__) == LL_SPI_CRC_4BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_5BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_6BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_7BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_8BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_9BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_10BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_11BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_12BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_13BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_14BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_15BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_16BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_17BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_18BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_19BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_20BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_21BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_22BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_23BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_24BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_25BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_26BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_27BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_28BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_29BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_30BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_31BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_32BIT))
+
+#define IS_LL_SPI_NSS(__VALUE__)                    (((__VALUE__) == LL_SPI_NSS_SOFT)                    || \
+                                                     ((__VALUE__) == LL_SPI_NSS_HARD_INPUT)              || \
+                                                     ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_RX_FIFO(__VALUE__)                (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET)             || \
+                                                     ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET)             || \
+                                                     ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET)             || \
+                                                     ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__)         (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE)       || \
+                                                     ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__)          ((__VALUE__) >= 0x1UL)
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+  if (SPIx == SPI1)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    /* Update the return status */
+    status = SUCCESS;
+  }
+#endif /* SPI1 */
+#if defined(SPI2)
+  if (SPIx == SPI2)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    /* Update the return status */
+    status = SUCCESS;
+  }
+#endif /* SPI2 */
+#if defined(SPI3)
+  if (SPIx == SPI3)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    /* Update the return status */
+    status = SUCCESS;
+  }
+#endif /* SPI3 */
+#if defined(SPI4)
+  if (SPIx == SPI4)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+    /* Update the return status */
+    status = SUCCESS;
+  }
+#endif /* SPI4 */
+#if defined(SPI5)
+  if (SPIx == SPI5)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
+
+    /* Update the return status */
+    status = SUCCESS;
+  }
+#endif /* SPI5 */
+#if defined(SPI6)
+  if (SPIx == SPI6)
+  {
+    /* Force reset of SPI clock */
+    LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6);
+
+    /* Release reset of SPI clock */
+    LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
+
+    /* Update the return status */
+    status = SUCCESS;
+  }
+#endif /* SPI6 */
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled
+  *         (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+  */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t tmp_nss;
+  uint32_t tmp_mode;
+  uint32_t tmp_nss_polarity;
+
+  /* Check the SPI Instance SPIx*/
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+  /* Check the SPI parameters from SPI_InitStruct*/
+  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+  assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
+  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+  /* Check the SPI instance is not enabled */
+  if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
+  {
+    /*---------------------------- SPIx CFG1 Configuration ------------------------
+       * Configure SPIx CFG1 with parameters:
+       * - Master Baud Rate       : SPI_CFG1_MBR[2:0] bits & SPI_CFG1_BPASS bit
+       * - CRC Computation Enable : SPI_CFG1_CRCEN bit
+       * - Length of data frame   : SPI_CFG1_DSIZE[4:0] bits
+       */
+    MODIFY_REG(SPIx->CFG1, SPI_CFG1_BPASS | SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
+               SPI_InitStruct->BaudRate  | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
+
+    tmp_nss  = SPI_InitStruct->NSS;
+    tmp_mode = SPI_InitStruct->Mode;
+    tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
+
+    /* Checks to setup Internal SS signal level and avoid a MODF Error */
+    if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW)  && \
+                                          (tmp_mode == LL_SPI_MODE_MASTER))              || \
+                                         ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
+                                          (tmp_mode == LL_SPI_MODE_SLAVE))))
+    {
+      LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
+    }
+
+    /*---------------------------- SPIx CFG2 Configuration ------------------------
+       * Configure SPIx CFG2 with parameters:
+       * - NSS management         : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
+       * - ClockPolarity          : SPI_CFG2_CPOL bit
+       * - ClockPhase             : SPI_CFG2_CPHA bit
+       * - BitOrder               : SPI_CFG2_LSBFRST bit
+       * - Master/Slave Mode      : SPI_CFG2_MASTER bit
+       * - SPI Mode               : SPI_CFG2_COMM[1:0] bits
+       */
+    MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM   | SPI_CFG2_SSOE    |
+               SPI_CFG2_CPOL              | SPI_CFG2_CPHA    |
+               SPI_CFG2_LSBFRST           | SPI_CFG2_MASTER  | SPI_CFG2_COMM,
+               SPI_InitStruct->NSS        | SPI_InitStruct->ClockPolarity                    |
+               SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder                         |
+               SPI_InitStruct->Mode       | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
+
+    /*---------------------------- SPIx CR1 Configuration ------------------------
+       * Configure SPIx CR1 with parameter:
+       * - Half Duplex Direction  : SPI_CR1_HDDIR bit
+       */
+    MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
+
+    /*---------------------------- SPIx CRCPOLY Configuration ----------------------
+       * Configure SPIx CRCPOLY with parameter:
+       * - CRCPoly                : CRCPOLY[31:0] bits
+       */
+    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+    {
+      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+    }
+
+    /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+    CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+
+    status = SUCCESS;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * whose fields will be set to default values.
+  * @retval None
+  */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  /* Set SPI_InitStruct fields to default values */
+  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
+  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
+  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
+  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
+  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
+  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
+  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
+  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct->CRCPoly           = 7UL;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/** @addtogroup I2S_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+  * @{
+  */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK                       (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
+                                                      SPI_I2SCFGR_DATFMT  | SPI_I2SCFGR_CKPOL  | \
+                                                      SPI_I2SCFGR_I2SSTD  | SPI_I2SCFGR_MCKOE  | \
+                                                      SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+  * @{
+  */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__)            (((__VALUE__) == LL_I2S_DATAFORMAT_16B)              || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED)     || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_24B)              || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__)  (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH)    || \
+                                                    ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
+
+#define IS_LL_I2S_CKPOL(__VALUE__)                  (((__VALUE__) == LL_I2S_POLARITY_LOW)               || \
+                                                     ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__)              (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)            || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_MSB)                || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_LSB)                || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT)          || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__)                  (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)               || \
+                                                    ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)               || \
+                                                    ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX)      || \
+                                                    ((__VALUE__) == LL_I2S_MODE_MASTER_TX)              || \
+                                                    ((__VALUE__) == LL_I2S_MODE_MASTER_RX)              || \
+                                                    ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__)           (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE)          || \
+                                                    ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__)           ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)                && \
+                                                    ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K))             || \
+                                                   ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)       ((__VALUE__) <= 0xFFUL)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__)      (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN)       || \
+                                                    ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+
+#define IS_LL_I2S_FIFO_TH (__VALUE__)              (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
+
+#define IS_LL_I2S_BIT_ORDER(__VALUE__)             (((__VALUE__) == LL_I2S_LSB_FIRST)                   || \
+                                                    ((__VALUE__) == LL_I2S_MSB_FIRST))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2S_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI/I2S registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
+{
+  return LL_SPI_DeInit(SPIx);
+}
+
+/**
+  * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+  * @note   As some bits in I2S configuration registers can only be written when the SPI is disabled
+  *         (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
+  * @note   I2S (SPI) source clock must be ready before calling this function. Otherwise will results
+  *         in wrong programming.
+  * @param  SPIx SPI Instance
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are Initialized
+  *          - ERROR: SPI registers are not Initialized
+  */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  uint32_t i2sdiv = 0UL;
+  uint32_t i2sodd = 0UL;
+  uint32_t packetlength = 1UL;
+  uint32_t ispcm = 0UL;
+  uint32_t tmp;
+  uint32_t sourceclock = 0UL;
+
+  ErrorStatus status = ERROR;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(sourceclock);
+
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+  assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+  assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+  assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+  assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+  assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
+
+  /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
+   * In this case, it is useless to check if the I2SMOD bit is set to 0 because
+   * this bit I2SMOD only serves to select the desired mode.
+   */
+  if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
+  {
+    /*---------------------------- SPIx I2SCFGR Configuration --------------------
+     * Configure SPIx I2SCFGR with parameters:
+     * - Mode           : SPI_I2SCFGR_I2SCFG[2:0] bits
+     * - Standard       : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+     * - DataFormat     : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
+     * - ClockPolarity  : SPI_I2SCFGR_CKPOL bit
+     * - MCLKOutput     : SPI_I2SPR_MCKOE bit
+     * - I2S mode       : SPI_I2SCFGR_I2SMOD bit
+     */
+
+    /* Write to SPIx I2SCFGR */
+    MODIFY_REG(SPIx->I2SCFGR,
+               I2S_I2SCFGR_CLEAR_MASK,
+               I2S_InitStruct->Mode       | I2S_InitStruct->Standard      |
+               I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+               I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
+
+    /*---------------------------- SPIx I2SCFGR Configuration ----------------------
+     * Configure SPIx I2SCFGR with parameters:
+     * - AudioFreq      : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
+     */
+
+    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+     * else, default values are used:  i2sodd = 0U, i2sdiv = 0U.
+     */
+    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+    {
+      /* Check the frame length (For the Prescaler computing)
+       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+       */
+      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+      {
+        /* Packet length is 32 bits */
+        packetlength = 2UL;
+      }
+
+      /* Check if PCM standard is used */
+      if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
+          (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
+      {
+        ispcm = 1UL;
+      }
+
+      /* Get the I2S (SPI) source clock value */
+      if (SPIx == SPI1)
+      {
+        sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI1_CLKSOURCE);
+      }
+      else if (SPIx == SPI2)
+      {
+        sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI2_CLKSOURCE);
+      }
+      else if (SPIx == SPI3)
+      {
+        sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI3_CLKSOURCE);
+      }
+      else /* SPI6 */
+      {
+        sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE);
+      }
+
+      /* Compute the Real divider depending on the MCLK output state with a fixed point */
+      if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+      {
+        /* MCLK output is enabled */
+        tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
+      }
+      else
+      {
+        /* MCLK output is disabled */
+        tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
+      }
+
+      /* Remove the fixed point */
+      tmp = tmp / 16UL;
+
+      /* Check the parity of the divider */
+      i2sodd = tmp & 0x1UL;
+
+      /* Compute the i2sdiv prescaler */
+      i2sdiv = tmp / 2UL;
+    }
+
+    /* Test if the obtain values are forbidden or out of range */
+    if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
+    {
+      /* Set the default values */
+      i2sdiv = 0UL;
+      i2sodd = 0UL;
+    }
+
+    /* Write to SPIx I2SCFGR register the computed value */
+    MODIFY_REG(SPIx->I2SCFGR,
+               SPI_I2SCFGR_ODD                 | SPI_I2SCFGR_I2SDIV,
+               (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
+
+    status = SUCCESS;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  *         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  /*--------------- Reset I2S init structure parameters values -----------------*/
+  I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
+  I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
+  I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
+  I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
+  I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
+  I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
+}
+
+/**
+  * @brief  Set linear and parity prescaler.
+  * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+  *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+  * @param  SPIx SPI Instance
+  * @param  PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
+  * @note   PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
+  * @param  PrescalerParity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+  assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+  /* Write to SPIx I2SPR */
+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
+             (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_tim.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_tim.c
new file mode 100644
index 000000000..535dc451c
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_tim.c
@@ -0,0 +1,1425 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_tim.h"
+#include "stm32n6xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1)  \
+ || defined (TIM2)  \
+ || defined (TIM3)  \
+ || defined (TIM4)  \
+ || defined (TIM5)  \
+ || defined (TIM6)  \
+ || defined (TIM7)  \
+ || defined (TIM8)  \
+ || defined (TIM9)  \
+ || defined (TIM10) \
+ || defined (TIM11) \
+ || defined (TIM12) \
+ || defined (TIM13) \
+ || defined (TIM14) \
+ || defined (TIM15) \
+ || defined (TIM16) \
+ || defined (TIM17) \
+ || defined (TIM18)
+
+/** @addtogroup TIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
+                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
+                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
+                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
+                                           || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+                                           || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+                                              || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+  * @{
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup TIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set TIMx registers to their reset values.
+  * @param  TIMx Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: invalid TIMx instance
+  */
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+
+  if (TIMx == TIM1)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+  }
+  else if (TIMx == TIM2)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+  }
+  else if (TIMx == TIM3)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+  }
+  else if (TIMx == TIM4)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+  }
+  else if (TIMx == TIM5)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+  }
+  else if (TIMx == TIM6)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+  }
+  else if (TIMx == TIM7)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+  }
+  else if (TIMx == TIM8)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+  }
+  else if (TIMx == TIM9)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
+  }
+  else if (TIMx == TIM10)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM10);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM10);
+  }
+  else if (TIMx == TIM11)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM11);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM11);
+  }
+  else if (TIMx == TIM12)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+  }
+  else if (TIMx == TIM13)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+  }
+  else if (TIMx == TIM14)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+  }
+  else if (TIMx == TIM15)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
+  }
+  else if (TIMx == TIM16)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+  }
+  else if (TIMx == TIM17)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+  }
+  else if (TIMx == TIM18)
+  {
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM18);
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM18);
+  }
+  else
+  {
+    result = ERROR;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the time base unit configuration data structure
+  *         to their default values.
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+  * @retval None
+  */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
+  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
+  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
+  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
+  TIM_InitStruct->RepetitionCounter = 0x00000000U;
+}
+
+/**
+  * @brief  Configure the TIMx time base unit.
+  * @param  TIMx Timer Instance
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+  *         (TIMx time base unit configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+  }
+
+  /* Write to TIMx CR1 */
+  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+  /* Set the Autoreload value */
+  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+  /* Set the Prescaler value */
+  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter value (if applicable) immediately */
+  LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the TIMx output channel configuration data
+  *         structure to their default values.
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+  *         (the output channel configuration data structure)
+  * @retval None
+  */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  /* Set the default configuration */
+  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
+  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
+  TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
+  TIM_OC_InitStruct->CompareValue = 0x00000000U;
+  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
+  TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
+  TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
+  TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+  * @brief  Configure the TIMx output channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+  *         data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = OC1Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = OC2Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = OC3Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = OC4Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH5:
+      result = OC5Config(TIMx, TIM_OC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH6:
+      result = OC6Config(TIMx, TIM_OC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set the fields of the TIMx input channel configuration data
+  *         structure to their default values.
+  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+  *         data structure)
+  * @retval None
+  */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the TIMx input channel.
+  * @param  TIMx Timer Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+  *         structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx output channel is initialized
+  *          - ERROR: TIMx output channel is not initialized
+  */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+  ErrorStatus result = ERROR;
+
+  switch (Channel)
+  {
+    case LL_TIM_CHANNEL_CH1:
+      result = IC1Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH2:
+      result = IC2Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH3:
+      result = IC3Config(TIMx, TIM_IC_InitStruct);
+      break;
+    case LL_TIM_CHANNEL_CH4:
+      result = IC4Config(TIMx, TIM_IC_InitStruct);
+      break;
+    default:
+      break;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Fills each TIM_EncoderInitStruct field with its default value
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+  *         configuration data structure)
+  * @retval None
+  */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  /* Set the default configuration */
+  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
+  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
+  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
+  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
+  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+  * @brief  Configure the encoder interface of the timer instance.
+  * @param  TIMx Timer Instance
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+  *         configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Configure TI1 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+  /* Configure TI2 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Set encoder mode */
+  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the TIMx Hall sensor interface configuration data
+  *         structure to their default values.
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+  *         configuration data structure)
+  * @retval None
+  */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+  /* Set the default configuration */
+  TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
+  TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
+  TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
+  TIM_HallSensorInitStruct->CommutationDelay  = 0U;
+}
+
+/**
+  * @brief  Configure the Hall sensor interface of the timer instance.
+  * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+  *       to the TI1 input channel
+  * @note TIMx slave mode controller is configured in reset mode.
+          Selected internal trigger is TI1F_ED.
+  * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+  * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+  *       between 2 changes on the inputs. It gives information about motor speed.
+  * @note Channel 2 is configured in output PWM 2 mode.
+  * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+  * @note OC2REF is selected as trigger output on TRGO.
+  * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+  *       when TIMx operates in Hall sensor interface mode.
+  * @param  TIMx Timer Instance
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+  *         interface configuration data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+  assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+  /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+  tmpcr2 |= TIM_CR2_TI1S;
+
+  /* OC2REF signal is used as trigger output (TRGO) */
+  tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+  /* Configure the slave mode controller */
+  tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+  tmpsmcr |= LL_TIM_TS_TI1F_ED;
+  tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+  /* Configure input channel 1 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
+  tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+  /* Configure input channel 2 */
+  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
+  tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx SMCR */
+  LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  /* Write to TIMx CCR2 */
+  LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the fields of the Break and Dead Time configuration data structure
+  *         to their default values.
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+  *         data structure)
+  * @retval None
+  */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
+  TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
+  TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
+  TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
+  TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
+  TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
+  TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
+  TIM_BDTRInitStruct->BreakAFMode     = LL_TIM_BREAK_AFMODE_INPUT;
+  TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
+  TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
+  TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
+  TIM_BDTRInitStruct->Break2AFMode    = LL_TIM_BREAK2_AFMODE_INPUT;
+  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+  * @brief  Configure the Break and Dead Time feature of the timer instance.
+  * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+  *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+  *  can be necessary to configure all of them during the first write access to
+  *  the TIMx_BDTR register.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @param  TIMx Timer Instance
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+  *         data structure)
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Break and Dead Time is initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+  uint32_t tmpbdtr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+  assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+  assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+  the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
+
+  if (IS_TIM_BKIN2_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+    assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+    assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+    assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
+
+    /* Set the BREAK2 input related BDTR bit-fields */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
+  }
+
+  /* Set TIMx_BDTR */
+  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+  return SUCCESS;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+  *  @brief   Private functions
+  * @{
+  */
+/**
+  * @brief  Configure the TIMx output channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+  /* Set the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR1 */
+  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+  /* Reset Capture/Compare selection Bits */
+  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+
+    /* Set the complementary output Polarity */
+    MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
+
+    /* Set the complementary output State */
+    MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
+
+    /* Set the Output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+
+    /* Set the complementary output Idle state */
+    MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
+  }
+
+  /* Write to TIMx CR2 */
+  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+  /* Write to TIMx CCMR2 */
+  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 5.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr3;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+  /* Disable the Channel 5: Reset the CC5E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CCMR3 register value */
+  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+  }
+
+  /* Write to TIMx CCMR3 */
+  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx output channel 6.
+  * @param  TIMx Timer Instance
+  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+  uint32_t tmpccmr3;
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+  /* Disable the Channel 5: Reset the CC6E Bit */
+  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+  /* Get the TIMx CCER register value */
+  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+  /* Get the TIMx CCMR3 register value */
+  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+  /* Select the Output Compare Mode */
+  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+  /* Set the Output Compare Polarity */
+  MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+  /* Set the Output State */
+  MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+    /* Set the Output Idle state */
+    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CCMR3 */
+  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+  /* Set the Capture Compare Register value */
+  LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+  /* Write to TIMx CCER */
+  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 1.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 2.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR1,
+             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 3.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+  /* Select the Polarity and set the CC3E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Configure the TIMx input channel 4.
+  * @param  TIMx Timer Instance
+  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: TIMx registers are de-initialized
+  *          - ERROR: not applicable
+  */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+  /* Select the Input and set the filter and the prescaler value */
+  MODIFY_REG(TIMx->CCMR2,
+             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+  /* Select the Polarity and set the CC4E Bit */
+  MODIFY_REG(TIMx->CCER,
+             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+  return SUCCESS;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_ucpd.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_ucpd.c
new file mode 100644
index 000000000..ef91e60f7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_ucpd.c
@@ -0,0 +1,169 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_ucpd.c
+  * @author  MCD Application Team
+  * @brief   UCPD LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_ucpd.h"
+#include "stm32n6xx_ll_bus.h"
+#include "stm32n6xx_ll_rcc.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+#if defined (UCPD1)
+/** @addtogroup UCPD_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UCPD_LL_Private_Constants UCPD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UCPD_LL_Private_Macros UCPD Private Macros
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UCPD_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UCPD_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the UCPD registers to their default reset values.
+  * @param  UCPDx ucpd Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ucpd registers are de-initialized
+  *          - ERROR: ucpd registers are not de-initialized
+  */
+ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
+
+  LL_UCPD_Disable(UCPDx);
+
+  if (UCPD1 == UCPDx)
+  {
+    /* Force reset of ucpd clock */
+    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1);
+
+    /* Release reset of ucpd clock */
+    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1);
+
+    /* Disable ucpd clock */
+    LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1);
+
+    status = SUCCESS;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
+  * @note   As some bits in ucpd configuration registers can only be written when the ucpd is disabled
+  *         (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
+  * @param  UCPDx UCPD Instance
+  * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
+  *         the configuration information for the UCPD peripheral.
+  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+  */
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct)
+{
+  /* Check the ucpd Instance UCPDx*/
+  assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
+
+  if (UCPD1 == UCPDx)
+  {
+    LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1);
+  }
+
+
+  LL_UCPD_Disable(UCPDx);
+
+  /*---------------------------- UCPDx CFG1 Configuration ------------------------*/
+  MODIFY_REG(UCPDx->CFG1,
+             UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
+             UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin  << UCPD_CFG1_TRANSWIN_Pos) |
+             (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_UCPD_InitTypeDef field to default value.
+  * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure
+  *         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
+{
+  /* Set UCPD_InitStruct fields to default values */
+  UCPD_InitStruct->psc_ucpdclk  = LL_UCPD_PSC_DIV2;
+  UCPD_InitStruct->transwin     = 0x7;   /* Divide by 8                     */
+  UCPD_InitStruct->IfrGap       = 0x10;  /* Divide by 17                    */
+  UCPD_InitStruct->HbitClockDiv = 0x0D;  /* Divide by 14 to produce HBITCLK */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (UCPD1) */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_usart.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_usart.c
new file mode 100644
index 000000000..986ea3dd7
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_usart.c
@@ -0,0 +1,487 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_usart.c
+  * @author  MCD Application Team
+  * @brief   USART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_usart.h"
+#include "stm32n6xx_ll_rcc.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \
+ || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10)
+
+/** @addtogroup USART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+  * @{
+  */
+
+/* Definition of default baudrate value used for USART initialisation */
+#define USART_DEFAULT_BAUDRATE          (9600U)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+                                       || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize USART registers (Registers restored to their default values).
+  * @param  USARTx USART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are de-initialized
+  *          - ERROR: USART registers are not de-initialized
+  */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+
+  if (USARTx == USART1)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+  }
+  else if (USARTx == USART2)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+  }
+  else if (USARTx == USART3)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+  }
+  else if (USARTx == UART4)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+  }
+  else if (USARTx == UART5)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+  }
+  else if (USARTx == USART6)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
+  }
+  else if (USARTx == UART7)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
+  }
+  else if (USARTx == UART8)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
+  }
+  else if (USARTx == UART9)
+  {
+    /* Force reset of UART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
+
+    /* Release reset of UART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
+  }
+  else if (USARTx == USART10)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize USART registers according to the specified
+  *         parameters in USART_InitStruct.
+  * @note   As some bits in USART configuration registers can only be written when
+  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+  *         this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  USARTx USART Instance
+  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
+  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR1 Configuration ---------------------
+     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+     */
+    MODIFY_REG(USARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+    /*---------------------------- USART CR2 Configuration ---------------------
+     * Configure USARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+     */
+    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+    /*---------------------------- USART CR3 Configuration ---------------------
+     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+     *   USART_InitStruct->HardwareFlowControl value.
+     */
+    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- USART BRR Configuration ---------------------
+     * Retrieve Clock frequency used for USART Peripheral
+     */
+    if (USARTx == USART1)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+    }
+    else if (USARTx == USART2)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+    }
+    else if (USARTx == USART3)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+    }
+    else if (USARTx == UART4)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+    }
+    else if (USARTx == UART5)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+    }
+    else if (USARTx == USART6)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE);
+    }
+    else if (USARTx == UART7)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE);
+    }
+    else if (USARTx == UART8)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE);
+    }
+    else if (USARTx == UART9)
+    {
+      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART9_CLKSOURCE);
+    }
+    else if (USARTx == USART10)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART10_CLKSOURCE);
+    }
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+
+    /* Configure the USART Baud Rate :
+       - prescaler value is required
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (USART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_USART_SetBaudRate(USARTx,
+                           periphclk,
+                           USART_InitStruct->PrescalerValue,
+                           USART_InitStruct->OverSampling,
+                           USART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+    }
+
+    /*---------------------------- USART PRESC Configuration -----------------------
+     * Configure USARTx PRESC (Prescaler) with parameters:
+     * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
+     */
+    LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
+  }
+  /* Endif (=> USART not in Disabled state => return ERROR) */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+  /* Set USART_InitStruct fields to default values */
+  USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
+  USART_InitStruct->BaudRate            = USART_DEFAULT_BAUDRATE;
+  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+  * @brief  Initialize USART Clock related settings according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @note   As some bits in USART configuration registers can only be written when
+  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+  *         this function. Otherwise, ERROR result will be returned.
+  * @param  USARTx USART Instance
+  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *         that contains the Clock configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers related to Clock settings are initialized according
+  *                     to USART_ClockInitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check USART Instance and Clock signal output parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /* Ensure USART instance is USART capable */
+    assert_param(IS_USART_INSTANCE(USARTx));
+
+    /* Check clock related parameters */
+    assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+    assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+    assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+    /*---------------------------- USART CR2 Configuration -----------------------
+     * Configure USARTx CR2 (Clock signal related bits) with parameters:
+     * - Clock Output:                USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+     * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+     * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+     * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+     */
+    MODIFY_REG(USARTx->CR2,
+               USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+               USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+               USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+  }
+  /* Else (USART not in Disabled state => return ERROR */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  /* Set LL_USART_ClockInitStruct fields with default values */
+  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_usb.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_usb.c
new file mode 100644
index 000000000..b03daa3cc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_usb.c
@@ -0,0 +1,2237 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_usb.c
+  * @author  MCD Application Team
+  * @brief   USB Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
+
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+  @endverbatim
+
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_hal.h"
+
+/** @addtogroup STM32N6xx_LL_USB_DRIVER
+  * @{
+  */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined (USB1_OTG_HS) || defined (USB2_OTG_HS)
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Initialization/de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx USB Instance
+  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret;
+
+  if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
+  {
+    /* Select Data line pulsing using utmi_txvalid */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS);
+
+
+    /* Reset after a PHY select */
+    ret = USB_CoreReset(USBx);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  if (cfg.dma_enable == 1U)
+  {
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  Set the USB turnaround time
+  * @param  USBx USB Instance
+  * @param  hclk: AHB clock frequency
+  * @retval USB turnaround time In PHY Clocks number
+  */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+                                        uint32_t hclk, uint8_t speed)
+{
+  uint32_t UsbTrd;
+
+  /* The USBTRD is configured according to the tables below, depending on AHB frequency
+  used by application. In the low AHB frequency range it is used to stretch enough the USB response
+  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+  latency to the Data FIFO */
+  if (speed == USBD_FS_SPEED)
+  {
+    if ((hclk >= 14200000U) && (hclk < 15000000U))
+    {
+      /* hclk Clock Range between 14.2-15 MHz */
+      UsbTrd = 0xFU;
+    }
+    else if ((hclk >= 15000000U) && (hclk < 16000000U))
+    {
+      /* hclk Clock Range between 15-16 MHz */
+      UsbTrd = 0xEU;
+    }
+    else if ((hclk >= 16000000U) && (hclk < 17200000U))
+    {
+      /* hclk Clock Range between 16-17.2 MHz */
+      UsbTrd = 0xDU;
+    }
+    else if ((hclk >= 17200000U) && (hclk < 18500000U))
+    {
+      /* hclk Clock Range between 17.2-18.5 MHz */
+      UsbTrd = 0xCU;
+    }
+    else if ((hclk >= 18500000U) && (hclk < 20000000U))
+    {
+      /* hclk Clock Range between 18.5-20 MHz */
+      UsbTrd = 0xBU;
+    }
+    else if ((hclk >= 20000000U) && (hclk < 21800000U))
+    {
+      /* hclk Clock Range between 20-21.8 MHz */
+      UsbTrd = 0xAU;
+    }
+    else if ((hclk >= 21800000U) && (hclk < 24000000U))
+    {
+      /* hclk Clock Range between 21.8-24 MHz */
+      UsbTrd = 0x9U;
+    }
+    else if ((hclk >= 24000000U) && (hclk < 27700000U))
+    {
+      /* hclk Clock Range between 24-27.7 MHz */
+      UsbTrd = 0x8U;
+    }
+    else if ((hclk >= 27700000U) && (hclk < 32000000U))
+    {
+      /* hclk Clock Range between 27.7-32 MHz */
+      UsbTrd = 0x7U;
+    }
+    else /* if(hclk >= 32000000) */
+    {
+      /* hclk Clock Range between 32-200 MHz */
+      UsbTrd = 0x6U;
+    }
+  }
+  else if (speed == USBD_HS_SPEED)
+  {
+    UsbTrd = USBD_HS_TRDT_VALUE;
+  }
+  else
+  {
+    UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+  }
+
+  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetCurrentMode Set functional mode
+  * @param  USBx  Selected device
+  * @param  mode  current core mode
+  *          This parameter can be one of these values:
+  *            @arg USB_DEVICE_MODE Peripheral mode
+  *            @arg USB_HOST_MODE Host mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
+{
+  uint32_t ms = 0U;
+
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
+  if (mode == USB_HOST_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+
+    do
+    {
+      HAL_Delay(10U);
+      ms += 10U;
+    } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
+  }
+  else if (mode == USB_DEVICE_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+    do
+    {
+      HAL_Delay(10U);
+      ms += 10U;
+    } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit Initializes the USB_OTG controller registers
+  *         for device mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx->DIEPTXF[i] = 0U;
+  }
+
+  /* Disable USB PHY pulldown resistors */
+  USBx->GCCFG &= ~USB_OTG_GCCFG_PULLDOWNEN;
+
+  /* VBUS Sensing setup */
+  if (cfg.vbus_sensing_enable == 0U)
+  {
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+    /* B-peripheral session valid override enable */
+    USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+    USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+  }
+  else
+  {
+    /* B-peripheral session valid override disable */
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN;
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL;
+  }
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+
+  if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
+  {
+    if (cfg.speed == USBD_HS_SPEED)
+    {
+      /* Set Core speed to High speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
+    }
+    else
+    {
+      /* Set Core speed to Full speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
+    }
+  }
+  else
+
+  {
+    /* Set Core speed to Full speed mode */
+    (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
+  }
+
+  /* Flush the FIFOs */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Clear all pending Device Interrupts */
+  USBx_DEVICE->DIEPMSK = 0U;
+  USBx_DEVICE->DOEPMSK = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_INEP(i)->DIEPCTL = 0U;
+    }
+
+    USBx_INEP(i)->DIEPTSIZ = 0U;
+    USBx_INEP(i)->DIEPINT  = 0xFB7FU;
+  }
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_OUTEP(i)->DOEPCTL = 0U;
+    }
+
+    USBx_OUTEP(i)->DOEPTSIZ = 0U;
+    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;
+  }
+
+  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xBFFFFFFFU;
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Device mode ONLY */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
+                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
+                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |
+                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
+
+  if (cfg.Sof_enable != 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+  }
+
+  if (cfg.vbus_sensing_enable == 1U)
+  {
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_FlushTxFifo Flush a Tx FIFO
+  * @param  USBx  Selected device
+  * @param  num  FIFO number
+  *         This parameter can be a value from 1 to 15
+            15 means Flush all Tx FIFOs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
+{
+  __IO uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Flush TX Fifo */
+  count = 0U;
+  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
+
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_FlushRxFifo  Flush Rx FIFO
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Flush RX Fifo */
+  count = 0U;
+  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register
+  *         depending the PHY type and the enumeration speed of the device.
+  * @param  USBx  Selected device
+  * @param  speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  * @retval  Hal status
+  */
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG |= speed;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_GetDevSpeed  Return the Dev Speed
+  * @param  USBx  Selected device
+  * @retval speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg USBD_HS_SPEED: High speed mode
+  *            @arg USBD_FS_SPEED: Full speed mode
+  */
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t speed;
+  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
+
+  if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+  {
+    speed = USBD_HS_SPEED;
+  }
+  else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
+           (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
+  {
+    speed = USBD_FS_SPEED;
+  }
+  else
+  {
+    speed = 0xFU;
+  }
+
+  return speed;
+}
+
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+  }
+  else
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) |
+                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate and configure a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
+    }
+
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
+                                   USB_OTG_DIEPCTL_MPSIZ |
+                                   USB_OTG_DIEPCTL_TXFNUM |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_EPTYP);
+  }
+  else
+  {
+    if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
+    }
+
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
+                                    USB_OTG_DOEPCTL_MPSIZ |
+                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_EPTYP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(epnum)->DIEPCTL  |= USB_OTG_DIEPCTL_SNAK;
+      USBx_INEP(epnum)->DIEPCTL  |= USB_OTG_DIEPCTL_EPDIS;
+    }
+
+    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+  }
+  else
+  {
+    if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL  |= USB_OTG_DOEPCTL_SNAK;
+      USBx_OUTEP(epnum)->DOEPCTL  |= USB_OTG_DOEPCTL_EPDIS;
+    }
+
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+  uint16_t pktcnt;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0U)
+    {
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
+      if (epnum == 0U)
+      {
+        if (ep->xfer_len > ep->maxpacket)
+        {
+          ep->xfer_len = ep->maxpacket;
+        }
+
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      }
+      else
+      {
+        pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19));
+
+        if (ep->type == EP_TYPE_ISOC)
+        {
+          USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+          USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29));
+        }
+      }
+
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    }
+    else
+    {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Enable the Tx FIFO Empty Interrupt for this EP */
+        if (ep->xfer_len > 0U)
+        {
+          USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+        }
+      }
+      else
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+
+        (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
+      }
+    }
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (epnum == 0U)
+    {
+      if (ep->xfer_len > 0U)
+      {
+        ep->xfer_len = ep->maxpacket;
+      }
+
+      /* Store transfer size, for EP0 this is equal to endpoint max packet size */
+      ep->xfer_size = ep->maxpacket;
+
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    }
+    else
+    {
+      if (ep->xfer_len == 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+        USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+      }
+      else
+      {
+        pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+        ep->xfer_size = ep->maxpacket * pktcnt;
+
+        USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+        USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
+      }
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
+    }
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+      }
+    }
+    /* EP enable */
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+   * @brief  USB_EPStoptXfer  Stop transfer on an EP
+   * @param  USBx  usb device instance
+   * @param  ep pointer to endpoint structure
+   * @retval HAL status
+   */
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* EP enable, IN data in FIFO */
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
+      USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
+
+      do
+      {
+        count++;
+
+        if (count > 10000U)
+        {
+          ret = HAL_ERROR;
+          break;
+        }
+      } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) ==  USB_OTG_DIEPCTL_EPENA);
+    }
+  }
+  else /* OUT endpoint */
+  {
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
+      USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
+
+      do
+      {
+        count++;
+
+        if (count > 10000U)
+        {
+          ret = HAL_ERROR;
+          break;
+        }
+      } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) ==  USB_OTG_DOEPCTL_EPENA);
+    }
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated
+  *         with the EP/channel
+  * @param  USBx  Selected device
+  * @param  src   pointer to source buffer
+  * @param  ch_ep_num  endpoint or host channel number
+  * @param  len  Number of bytes to write
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+                                  uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t *pSrc = src;
+  uint32_t count32b;
+  uint32_t i;
+
+  if (dma == 0U)
+  {
+    count32b = ((uint32_t)len + 3U) / 4U;
+    for (i = 0U; i < count32b; i++)
+    {
+      USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
+      pSrc++;
+      pSrc++;
+      pSrc++;
+      pSrc++;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadPacket : read a packet from the RX FIFO
+  * @param  USBx  Selected device
+  * @param  dest  source pointer
+  * @param  len  Number of bytes to read
+  * @retval pointer to destination buffer
+  */
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t *pDest = dest;
+  uint32_t pData;
+  uint32_t i;
+  uint32_t count32b = (uint32_t)len >> 2U;
+  uint16_t remaining_bytes = len % 4U;
+
+  for (i = 0U; i < count32b; i++)
+  {
+    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
+    pDest++;
+    pDest++;
+    pDest++;
+    pDest++;
+  }
+
+  /* When Number of data is not word aligned, read the remaining byte */
+  if (remaining_bytes != 0U)
+  {
+    i = 0U;
+    __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
+
+    do
+    {
+      *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
+      i++;
+      pDest++;
+      remaining_bytes--;
+    } while (remaining_bytes != 0U);
+  }
+
+  return ((void *)pDest);
+}
+
+/**
+  * @brief  USB_EPSetStall : set a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+    }
+    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+    }
+    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  else
+  {
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_StopDevice : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+  HAL_StatusTypeDef ret;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Clear Pending interrupt */
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx_INEP(i)->DIEPINT = 0xFB7FU;
+    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+  }
+
+  /* Clear interrupt masks */
+  USBx_DEVICE->DIEPMSK  = 0U;
+  USBx_DEVICE->DOEPMSK  = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  /* Flush the FIFO */
+  ret = USB_FlushRxFifo(USBx);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  ret = USB_FlushTxFifo(USBx,  0x10U);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_SetDevAddress : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @param  address  new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
+  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevConnect : Connect the USB device by enabling Rpu
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling Rpu
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status
+  * @param  USBx  Selected device
+  * @retval USB Global Interrupt status
+  */
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
+{
+  uint32_t tmpreg;
+
+  tmpreg = USBx->GINTSTS;
+  tmpreg &= USBx->GINTMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ReadChInterrupts: return USB channel interrupt status
+  * @param  USBx  Selected device
+  * @param  chnum Channel number
+  * @retval USB Channel Interrupt status
+  */
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg = USBx_HC(chnum)->HCINT;
+  tmpreg &= USBx_HC(chnum)->HCINTMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval USB Device OUT EP interrupt status
+  */
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xffff0000U) >> 16);
+}
+
+/**
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval USB Device IN EP interrupt status
+  */
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xFFFFU));
+}
+
+/**
+  * @brief  Returns Device OUT EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device OUT EP Interrupt register
+  */
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
+  tmpreg &= USBx_DEVICE->DOEPMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  Returns Device IN EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device IN EP Interrupt register
+  */
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+  uint32_t msk;
+  uint32_t emp;
+
+  msk = USBx_DEVICE->DIEPMSK;
+  emp = USBx_DEVICE->DIEPEMPMSK;
+  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
+  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ClearInterrupts: clear a USB interrupt
+  * @param  USBx  Selected device
+  * @param  interrupt  flag
+  * @retval None
+  */
+void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+  USBx->GINTSTS &= interrupt;
+}
+
+/**
+  * @brief  Returns USB core mode
+  * @param  USBx  Selected device
+  * @retval return core mode : Host or Device
+  *          This parameter can be one of these values:
+  *           0 : Host
+  *           1 : Device
+  */
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx->GINTSTS) & 0x1U);
+}
+
+/**
+  * @brief  Activate EP0 for Setup transactions
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* Set the MPS of the IN EP0 to 64 bytes */
+  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Prepare the EP0 to start the first control setup
+  * @param  USBx  Selected device
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @param  psetup  pointer to setup packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
+
+  if (gSNPSiD > USB_OTG_CORE_ID_300A)
+  {
+    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      return HAL_OK;
+    }
+  }
+
+  USBx_OUTEP(0U)->DOEPTSIZ = 0U;
+  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
+  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;
+
+  if (dma == 1U)
+  {
+    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
+    /* EP enable */
+    USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the USB Core (needed after USB clock settings change)
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+  __IO uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Core Soft Reset */
+  count = 0U;
+  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers
+  *         for Host mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Enable USB PHY pulldown resistors */
+  USBx->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN;
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+  /* Disable VBUS override */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBVALOVAL | USB_OTG_GCCFG_VBVALEXTOEN);
+
+  /* Disable Battery chargin detector */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDETEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDETEN);
+
+  if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U)
+  {
+    if (cfg.speed == USBH_FSLS_SPEED)
+    {
+      /* Force Device Enumeration to FS/LS mode only */
+      USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+    }
+    else
+    {
+      /* Set default Max speed support */
+      USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+    }
+  }
+  else
+  {
+    /* Set default Max speed support */
+    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+  }
+
+  /* Make sure the FIFOs are flushed. */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Clear all pending HC Interrupts */
+  for (i = 0U; i < cfg.Host_channels; i++)
+  {
+    USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK;
+    USBx_HC(i)->HCINTMSK = 0U;
+  }
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
+  /* set Rx FIFO size */
+  USBx->GRXFSIZ  = 0x200U;
+  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+  USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Host mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \
+                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
+
+  return ret;
+}
+
+/**
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
+  *         HCFG register on the PHY type and set the right frame interval
+  * @param  USBx  Selected device
+  * @param  freq  clock frequency
+  *          This parameter can be one of these values:
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
+
+  if (freq == HCFG_48_MHZ)
+  {
+    USBx_HOST->HFIR = HFIR_48_MHZ;
+  }
+  else if (freq == HCFG_6_MHZ)
+  {
+    USBx_HOST->HFIR = HFIR_6_MHZ;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_OTG_ResetPort : Reset Host Port
+  * @param  USBx  Selected device
+  * @retval HAL status
+  * @note (1)The application must wait at least 10 ms
+  *   before clearing the reset bit.
+  */
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+  HAL_Delay(100U);                                 /* See Note #1 */
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+  HAL_Delay(10U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DriveVbus : activate or de-activate vbus
+  * @param  state  VBUS state
+  *          This parameter can be one of these values:
+  *           0 : Deactivate VBUS
+  *           1 : Activate VBUS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
+  {
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
+  }
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
+  {
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return Host Core speed
+  * @param  USBx  Selected device
+  * @retval speed : Host speed
+  *          This parameter can be one of these values:
+  *            @arg HCD_SPEED_HIGH: High speed mode
+  *            @arg HCD_SPEED_FULL: Full speed mode
+  *            @arg HCD_SPEED_LOW: Low speed mode
+  */
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
+}
+
+/**
+  * @brief  Return Host Current Frame number
+  * @param  USBx  Selected device
+  * @retval current frame number
+  */
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+  * @brief  Initialize a host channel
+  * @param  USBx  Selected device
+  * @param  ch_num  Channel number
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum  Endpoint number
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address  Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed  Current device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @param  ep_type  Endpoint Type
+  *          This parameter can be one of these values:
+  *            @arg EP_TYPE_CTRL: Control type
+  *            @arg EP_TYPE_ISOC: Isochronous type
+  *            @arg EP_TYPE_BULK: Bulk type
+  *            @arg EP_TYPE_INTR: Interrupt type
+  * @param  mps  Max Packet Size
+  *          This parameter can be a value from 0 to 32K
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+                              uint8_t epnum, uint8_t dev_address, uint8_t speed,
+                              uint8_t ep_type, uint16_t mps)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t HCcharEpDir;
+  uint32_t HCcharLowSpeed;
+  uint32_t HostCoreSpeed;
+
+  /* Clear old interrupt conditions for this host channel. */
+  USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK;
+
+  /* Enable channel interrupts required for this transfer. */
+  switch (ep_type)
+  {
+    case EP_TYPE_CTRL:
+    case EP_TYPE_BULK:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_NAKM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+      else
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
+                                               USB_OTG_HCINTMSK_ACKM;
+      }
+      break;
+
+    case EP_TYPE_INTR:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_NAKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+
+      break;
+
+    case EP_TYPE_ISOC:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_ACKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+      }
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  /* Clear Hub Start Split transaction */
+  USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
+
+  /* Enable host channel Halt interrupt */
+  USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
+
+  /* Enable the top level host channel interrupt. */
+  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
+
+  /* Make sure host channel interrupts are enabled. */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+
+  /* Program the HCCHAR register */
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    HCcharEpDir = 0U;
+  }
+
+  HostCoreSpeed = USB_GetHostSpeed(USBx);
+
+  /* LS device plugged to HUB */
+  if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
+  {
+    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+  }
+  else
+  {
+    HCcharLowSpeed = 0U;
+  }
+
+  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
+                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) |
+                                      USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed;
+
+  if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC))
+  {
+    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Start a transfer over a host channel
+  * @param  USBx  Selected device
+  * @param  hc  pointer to host channel structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)hc->ch_num;
+  __IO uint32_t tmpreg;
+  uint8_t  is_oddframe;
+  uint16_t len_words;
+  uint16_t num_packets;
+  uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT;
+
+  /* in DMA mode host Core automatically issues ping in case of NYET/NAK */
+  if (dma == 1U)
+  {
+    if ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))
+    {
+
+      USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
+                                               USB_OTG_HCINTMSK_ACKM |
+                                               USB_OTG_HCINTMSK_NAKM);
+    }
+  }
+  else
+  {
+    if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U))
+    {
+      (void)USB_DoPing(USBx, hc->ch_num);
+      return HAL_OK;
+    }
+  }
+
+  if (hc->do_ssplit == 1U)
+  {
+    /* Set number of packet to 1 for Split transaction */
+    num_packets = 1U;
+
+    if (hc->ep_is_in != 0U)
+    {
+      hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+    }
+    else
+    {
+      if (hc->ep_type == EP_TYPE_ISOC)
+      {
+        if (hc->xfer_len > ISO_SPLT_MPS)
+        {
+          /* Isochrone Max Packet Size for Split mode */
+          hc->XferSize = hc->max_packet;
+          hc->xfer_len = hc->XferSize;
+
+          if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE))
+          {
+            hc->iso_splt_xactPos = HCSPLT_MIDDLE;
+          }
+          else
+          {
+            hc->iso_splt_xactPos = HCSPLT_BEGIN;
+          }
+        }
+        else
+        {
+          hc->XferSize = hc->xfer_len;
+
+          if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE))
+          {
+            hc->iso_splt_xactPos = HCSPLT_FULL;
+          }
+          else
+          {
+            hc->iso_splt_xactPos = HCSPLT_END;
+          }
+        }
+      }
+      else
+      {
+        if ((dma == 1U) && (hc->xfer_len > hc->max_packet))
+        {
+          hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+        }
+        else
+        {
+          hc->XferSize = hc->xfer_len;
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Compute the expected number of packets associated to the transfer */
+    if (hc->xfer_len > 0U)
+    {
+      num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+
+      if (num_packets > max_hc_pkt_count)
+      {
+        num_packets = max_hc_pkt_count;
+        hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+      }
+    }
+    else
+    {
+      num_packets = 1U;
+    }
+
+    /*
+    * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
+    * max_packet size.
+    */
+    if (hc->ep_is_in != 0U)
+    {
+      hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+    }
+    else
+    {
+      hc->XferSize = hc->xfer_len;
+    }
+  }
+
+  /* Initialize the HCTSIZn register */
+  USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
+                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
+
+  if (dma != 0U)
+  {
+    /* xfer_buff MUST be 32-bits aligned */
+    USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+  }
+
+  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
+  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
+
+  if (hc->do_ssplit == 1U)
+  {
+    /* Set Hub start Split transaction */
+    USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) |
+                                        (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN;
+
+    /* unmask ack & nyet for IN/OUT transactions */
+    USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM |
+                                            USB_OTG_HCINTMSK_NYET);
+
+    if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U))
+    {
+      USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+      USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
+    }
+
+    if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) &&
+        (hc->do_csplit == 1U) && (hc->ep_is_in == 1U))
+    {
+      USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+    }
+
+    /* Position management for iso out transaction on split mode */
+    if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U))
+    {
+      /* Set data payload position */
+      switch (hc->iso_splt_xactPos)
+      {
+        case HCSPLT_BEGIN:
+          /* First data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1;
+          break;
+
+        case HCSPLT_MIDDLE:
+          /* Middle data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos;
+          break;
+
+        case HCSPLT_END:
+          /* End data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0;
+          break;
+
+        case HCSPLT_FULL:
+          /* Entire data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+  else
+  {
+    /* Clear Hub Start Split transaction */
+    USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
+  }
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(ch_num)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+  /* make sure to set the correct ep direction */
+  if (hc->ep_is_in != 0U)
+  {
+    tmpreg |= USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+  }
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(ch_num)->HCCHAR = tmpreg;
+
+  if (dma != 0U) /* dma mode */
+  {
+    return HAL_OK;
+  }
+
+  if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U))
+  {
+    switch (hc->ep_type)
+    {
+      /* Non periodic transfer */
+      case EP_TYPE_CTRL:
+      case EP_TYPE_BULK:
+
+        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+
+        /* check if there is enough space in FIFO space */
+        if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+        {
+          /* need to process data in nptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+        }
+        break;
+
+      /* Periodic transfer */
+      case EP_TYPE_INTR:
+      case EP_TYPE_ISOC:
+        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+        /* check if there is enough space in FIFO space */
+        if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+        {
+          /* need to process data in ptxfempty interrupt */
+          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+        }
+        break;
+
+      default:
+        break;
+    }
+
+    /* Write packet into the Tx FIFO. */
+    (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Read all host channel interrupts status
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return ((USBx_HOST->HAINT) & 0xFFFFU);
+}
+
+/**
+  * @brief  Halt a host channel
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t hcnum = (uint32_t)hc_num;
+  __IO uint32_t count = 0U;
+  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+  uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
+  uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31;
+
+  /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels.
+     At the end of the next uframe/frame (in the worst case), the core generates a channel halted
+     and disables the channel automatically. */
+
+  if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) &&
+      ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR)))))
+  {
+    return HAL_OK;
+  }
+
+  /* Check for space in the request queue to issue the halt. */
+  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
+    {
+      if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+      {
+        USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+        USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+        do
+        {
+          count++;
+
+          if (count > 1000U)
+          {
+            break;
+          }
+        } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+      }
+      else
+      {
+        USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      }
+    }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
+  }
+  else
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
+    {
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      do
+      {
+        count++;
+
+        if (count > 1000U)
+        {
+          break;
+        }
+      } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+    }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initiate Do Ping protocol
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t chnum = (uint32_t)ch_num;
+  uint32_t num_packets = 1U;
+  uint32_t tmpreg;
+
+  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                           USB_OTG_HCTSIZ_DOPING;
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(chnum)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(chnum)->HCCHAR = tmpreg;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop Host Core
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t count = 0U;
+  uint32_t value;
+  uint32_t i;
+
+  (void)USB_DisableGlobalInt(USBx);
+
+  /* Flush USB FIFO */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Flush out any leftover queued requests. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |=  USB_OTG_HCCHAR_CHDIS;
+    value &= ~USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+  }
+
+  /* Halt all channels to put them into a known state. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |= USB_OTG_HCCHAR_CHDIS;
+    value |= USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+
+    do
+    {
+      count++;
+
+      if (count > 1000U)
+      {
+        break;
+      }
+    } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+  }
+
+  /* Clear any pending Host interrupts */
+  USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK;
+  USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
+
+  (void)USB_EnableGlobalInt(USBx);
+
+  return ret;
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+  {
+    /* active Remote wakeup signalling */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* active Remote wakeup signalling */
+  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+
+  return HAL_OK;
+}
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_utils.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_utils.c
new file mode 100644
index 000000000..4cc0a6bf9
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_utils.c
@@ -0,0 +1,631 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_utils.c
+  * @author  MCD Application Team
+  * @brief   UTILS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_utils.h"
+#include "stm32n6xx_ll_pwr.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILS_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+  * @{
+  */
+#define UTILS_MAX_FREQUENCY_SCALE0  800000000U      /*!< Maximum frequency for system clock at power scale 0, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE1  600000000U      /*!< Maximum frequency for system clock at power scale 1, in Hz */
+
+#define UTILS_PLLVCO_INPUT_MAX       50000000U      /*!< Frequency max for the PLLVCO input, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_MAX    3200000000U      /*!< Frequency max for the PLLVCO output, in Hz */
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN         16000000U   /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX         48000000U   /*!< Frequency max for HSE frequency, in Hz   */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_UTILS_AHB_DIV(__VALUE__)    (((__VALUE__) == LL_RCC_AHB_DIV_1) \
+                                           || ((__VALUE__) == LL_RCC_AHB_DIV_2) \
+                                           || ((__VALUE__) == LL_RCC_AHB_DIV_4) \
+                                           || ((__VALUE__) == LL_RCC_AHB_DIV_8) \
+                                           || ((__VALUE__) == LL_RCC_AHB_DIV_16) \
+                                           || ((__VALUE__) == LL_RCC_AHB_DIV_64) \
+                                           || ((__VALUE__) == LL_RCC_AHB_DIV_128))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+                                         || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+                                         || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+                                         || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+                                         || ((__VALUE__) == LL_RCC_APB1_DIV_16) \
+                                         || ((__VALUE__) == LL_RCC_APB1_DIV_32) \
+                                         || ((__VALUE__) == LL_RCC_APB1_DIV_64) \
+                                         || ((__VALUE__) == LL_RCC_APB1_DIV_128))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+                                         || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+                                         || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+                                         || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+                                         || ((__VALUE__) == LL_RCC_APB2_DIV_16) \
+                                         || ((__VALUE__) == LL_RCC_APB2_DIV_32) \
+                                         || ((__VALUE__) == LL_RCC_APB2_DIV_64) \
+                                         || ((__VALUE__) == LL_RCC_APB2_DIV_128))
+
+#define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
+                                         || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
+                                         || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
+                                         || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
+                                         || ((__VALUE__) == LL_RCC_APB4_DIV_16) \
+                                         || ((__VALUE__) == LL_RCC_APB4_DIV_32) \
+                                         || ((__VALUE__) == LL_RCC_APB4_DIV_64) \
+                                         || ((__VALUE__) == LL_RCC_APB4_DIV_128))
+
+#define IS_LL_UTILS_APB5_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB5_DIV_1) \
+                                         || ((__VALUE__) == LL_RCC_APB5_DIV_2) \
+                                         || ((__VALUE__) == LL_RCC_APB5_DIV_4) \
+                                         || ((__VALUE__) == LL_RCC_APB5_DIV_8) \
+                                         || ((__VALUE__) == LL_RCC_APB5_DIV_16) \
+                                         || ((__VALUE__) == LL_RCC_APB5_DIV_32) \
+                                         || ((__VALUE__) == LL_RCC_APB5_DIV_64) \
+                                         || ((__VALUE__) == LL_RCC_APB5_DIV_128))
+
+/* Values expected to use PLL in Integer mode */
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
+
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((16U <= (__VALUE__)) && ((__VALUE__) <= 640U))
+
+#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 7U))
+
+#define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) == 0U)
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) \
+  (((__STATE__) == LL_UTILS_HSEBYPASS_ON) || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) \
+  (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+  * @{
+  */
+static void        UTILS_ConfigurePLL1InIntegerMode(const LL_UTILS_PLLInitTypeDef *pUTILS_ClkInitStruct);
+static void        UTILS_ConfigureIC(const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct);
+static ErrorStatus UTILS_EnablePLL1AndSwitchSystem(uint32_t CPU_Frequency,
+                                                   const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+  * @{
+  */
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+void LL_Init1msTick(uint32_t CPU_Frequency)
+{
+  /* Use frequency provided in argument */
+  LL_InitTick(CPU_Frequency, 1000U);
+}
+
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on SysTick counter flag
+  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+  *         and use rather osDelay service.
+  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+  *         will configure Systick to 1ms
+  * @param  Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void LL_mDelay(uint32_t Delay)
+{
+  uint32_t count = Delay;
+  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+  /* Add this code to indicate that local variable is not used */
+  ((void)tmp);
+
+  /* Add a period to guaranty minimum wait */
+  if (count < LL_MAX_DELAY)
+  {
+    count++;
+  }
+
+  while (count != 0U)
+  {
+    if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+    {
+      count--;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_EF_SYSTEM
+  *  @brief    System Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### System Configuration functions #####
+ ===============================================================================
+    [..]
+         System, AXI, AHB and APB buses clocks configuration
+
+         (+) The maximum frequency of the CPU is 800 MHz and AXI is 400 MHz.
+         (+) The maximum frequency of the HCLK, PCLK1, PCLK2, PCLK4 and PCLK5 is 200 MHz.
+  @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
+{
+  /* CPU clock frequency */
+  SystemCoreClock = CPU_Frequency;
+}
+
+/**
+  * @brief  This function configures the CPU system clock with HSI as clock source of the PLL1
+  *         used in integer mode.
+  * @note   The application needs to ensure that PLL1 is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP1 / PLLP2)
+  *         - PLLM: ensure that the VCO input frequency ranges from 1 to 50 MHz (PLLVCO_input = HSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is maximum 3200 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP1, PLLP2: ensure that max frequency at 800 MHz is reached (PLLVCO_output / PLLP1 / PLLP2)
+  * @param  pUTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  pUTILS_ICInitStruct pointer to a @ref LL_UTILS_ICInitTypeDef structure that contains
+  *                             the configuration information for the IC.
+  * @param  pUTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  *
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
+                                         const LL_UTILS_ICInitTypeDef  *pUTILS_ICInitStruct,
+                                         const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+  uint32_t pllfreq;
+  uint32_t hsi_clk;
+
+  /* Check the PLL parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(pUTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(pUTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP1));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP2));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(pUTILS_PLLInitStruct->FRACN));
+
+  hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos));
+
+  /* Check VCO Input frequency */
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(hsi_clk / pUTILS_PLLInitStruct->PLLM));
+
+  /* Check that PLL1 is not enabled and thus ready for configuration */
+  if (LL_RCC_PLL1_IsReady() != 1U)
+  {
+    /* Integer mode only */
+    if (pUTILS_PLLInitStruct->FRACN == 0U)
+    {
+      /* Calculate the new PLL output frequency */
+      pllfreq = LL_RCC_CalcPLLClockFreq(hsi_clk, pUTILS_PLLInitStruct->PLLM,
+                                        pUTILS_PLLInitStruct->PLLN, pUTILS_PLLInitStruct->FRACN,
+                                        pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2);
+      /* Check VCO Output frequency */
+      assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruct->PLLP2));
+
+      /* Enable HSI if not enabled */
+      if (LL_RCC_HSI_IsReady() != 1U)
+      {
+        LL_RCC_HSI_Enable();
+        while (LL_RCC_HSI_IsReady() != 1U)
+        {
+          /* Wait for HSI ready */
+        }
+      }
+
+      /* Configure PLL1 */
+      LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_HSI);
+
+      UTILS_ConfigurePLL1InIntegerMode(pUTILS_PLLInitStruct);
+
+      UTILS_ConfigureIC(pUTILS_ICInitStruct);
+
+      /* Enable PLL and switch CPU/system clock to PLL */
+      status = UTILS_EnablePLL1AndSwitchSystem(pllfreq, pUTILS_ClkInitStruct);
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures the CPU system clock with MSI as clock source of the PLL1
+  *         used in integer mode.
+  * @note   The application needs to ensure that PLL1 is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLP1 / PLLP2)
+  *         - PLLM: ensure that the VCO input frequency ranges from 1 to 50 MHz (PLLVCO_input = MSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is maximum 3200 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP1, PLLP2: ensure that max frequency at 800 MHz is reached (PLLVCO_output / PLLP1 / PLLP2)
+  * @param  pUTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  pUTILS_ICInitStruct pointer to a @ref LL_UTILS_ICInitTypeDef structure that contains
+  *                             the configuration information for the IC.
+  * @param  pUTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  *
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_MSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
+                                         const LL_UTILS_ICInitTypeDef  *pUTILS_ICInitStruct,
+                                         const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+  uint32_t pllfreq;
+
+  /* Check the PLL parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(pUTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(pUTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP1));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP2));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(pUTILS_PLLInitStruct->FRACN));
+
+  /* Check VCO Input frequency */
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(MSI_VALUE / pUTILS_PLLInitStruct->PLLM));
+
+  /* Check that PLL1 is not enabled and thus ready for configuration */
+  if (LL_RCC_PLL1_IsReady() != 1U)
+  {
+    /* Integer mode only */
+    if (pUTILS_PLLInitStruct->FRACN == 0U)
+    {
+      /* Calculate the new PLL output frequency */
+      pllfreq = LL_RCC_CalcPLLClockFreq(MSI_VALUE, pUTILS_PLLInitStruct->PLLM,
+                                        pUTILS_PLLInitStruct->PLLN, pUTILS_PLLInitStruct->FRACN,
+                                        pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2);
+
+      /* Check VCO Output frequency */
+      assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruct->PLLP2));
+
+      /* Enable MSI if not enabled */
+      if (LL_RCC_MSI_IsReady() != 1U)
+      {
+        LL_RCC_MSI_Enable();
+        while (LL_RCC_MSI_IsReady() != 1U)
+        {
+          /* Wait for MSI ready */
+        }
+      }
+
+      /* Configure PLL1 */
+      LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_MSI);
+
+      UTILS_ConfigurePLL1InIntegerMode(pUTILS_PLLInitStruct);
+
+      UTILS_ConfigureIC(pUTILS_ICInitStruct);
+
+      /* Enable PLL and switch system clock to PLL */
+      status = UTILS_EnablePLL1AndSwitchSystem(pllfreq, pUTILS_ClkInitStruct);
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures the CPU system clock with HSE as clock source of the PLL1
+  *         used in integer mode.
+  * @note   The application needs to ensure that PLL1 is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP1 / PLLP2)
+  *         - PLLM: ensure that the VCO input frequency ranges from 1 to 50 MHz (PLLVCO_input = HSE frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is maximum 3200 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP1, PLLP2: ensure that max frequency at 800 MHz is reached (PLLVCO_output / PLLP1 / PLLP2)
+  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 50000000
+  * @param  HSEBypass This parameter can be one of the following values:
+  *         @arg @ref LL_UTILS_HSEBYPASS_ON
+  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+  * @param  pUTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  pUTILS_ICInitStruct pointer to a @ref LL_UTILS_ICInitTypeDef structure that contains
+  *                             the configuration information for the IC.
+  * @param  pUTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  *
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
+                                         const LL_UTILS_ICInitTypeDef  *pUTILS_ICInitStruct,
+                                         const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+  uint32_t pllfreq;
+
+  /* Check the HSE parameters */
+  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+  /* Check the PLL parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(pUTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(pUTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP1));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP2));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(pUTILS_PLLInitStruct->FRACN));
+
+  /* Check VCO Input frequency */
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(HSEFrequency / pUTILS_PLLInitStruct->PLLM));
+
+  /* Check that PLL1 is not enabled and thus ready for configuration */
+  if (LL_RCC_PLL1_IsReady() != 1U)
+  {
+    /* Integer mode only */
+    if (pUTILS_PLLInitStruct->FRACN == 0U)
+    {
+      /* Calculate the new PLL output frequency */
+      pllfreq = LL_RCC_CalcPLLClockFreq(HSEFrequency, pUTILS_PLLInitStruct->PLLM,
+                                        pUTILS_PLLInitStruct->PLLN, pUTILS_PLLInitStruct->FRACN,
+                                        pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2);
+
+      /* Check VCO Output frequency */
+      assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruct->PLLP2));
+
+      /* Enable HSE if not enabled */
+      if (LL_RCC_HSE_IsReady() != 1U)
+      {
+        /* Check if need to enable HSE bypass feature or not */
+        if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+        {
+          LL_RCC_HSE_EnableBypass();
+        }
+        else
+        {
+          LL_RCC_HSE_DisableBypass();
+        }
+
+        /* Enable HSE */
+        LL_RCC_HSE_Enable();
+        while (LL_RCC_HSE_IsReady() != 1U)
+        {
+          /* Wait for HSE ready */
+        }
+      }
+
+      /* Configure PLL1 */
+      LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_HSE);
+
+      UTILS_ConfigurePLL1InIntegerMode(pUTILS_PLLInitStruct);
+
+      UTILS_ConfigureIC(pUTILS_ICInitStruct);
+
+      /* Enable PLL and switch system clock to PLL */
+      status = UTILS_EnablePLL1AndSwitchSystem(pllfreq, pUTILS_ClkInitStruct);
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_LL_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Function to configure PLL1 in Integer mode
+  * @param  pUTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @retval None
+  */
+static void UTILS_ConfigurePLL1InIntegerMode(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct)
+{
+  LL_RCC_PLL1_DisableModulationSpreadSpectrum();
+  LL_RCC_PLL1_SetM(pUTILS_PLLInitStruct->PLLM);
+  LL_RCC_PLL1_SetN(pUTILS_PLLInitStruct->PLLN);
+  LL_RCC_PLL1_SetFRACN(pUTILS_PLLInitStruct->FRACN);
+  LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum();
+  LL_RCC_PLL1_AssertModulationSpreadSpectrumReset();
+  LL_RCC_PLL1_SetP1(pUTILS_PLLInitStruct->PLLP1);
+  LL_RCC_PLL1_SetP2(pUTILS_PLLInitStruct->PLLP2);
+}
+
+/**
+  * @brief  Function to configure IC for CPU/System buses clocks
+  * @param  pUTILS_ICInitStruct pointer to a @ref LL_UTILS_ICInitTypeDef structure that contains
+  *                             the configuration information for the IC (IC1, IC2, IC6 and IC11).
+  * @retval None
+  */
+static void UTILS_ConfigureIC(const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct)
+{
+  /* Configure and enable each IC used for CPU/System buses clocks */
+  LL_RCC_IC1_SetSource(pUTILS_ICInitStruct->IC1Source);
+  LL_RCC_IC1_SetDivider(pUTILS_ICInitStruct->IC1Divider);
+  LL_RCC_IC1_Enable();
+  LL_RCC_IC2_SetSource(pUTILS_ICInitStruct->IC2Source);
+  LL_RCC_IC2_SetDivider(pUTILS_ICInitStruct->IC2Divider);
+  LL_RCC_IC2_Enable();
+  LL_RCC_IC6_SetSource(pUTILS_ICInitStruct->IC6Source);
+  LL_RCC_IC6_SetDivider(pUTILS_ICInitStruct->IC6Divider);
+  LL_RCC_IC6_Enable();
+  LL_RCC_IC11_SetSource(pUTILS_ICInitStruct->IC11Source);
+  LL_RCC_IC11_SetDivider(pUTILS_ICInitStruct->IC11Divider);
+  LL_RCC_IC11_Enable();
+}
+
+/**
+  * @brief  Function to enable PLL1 and switch CPU/system clock to PLL
+  * @param  CPU_Frequency CPU frequency
+  * @param  pUTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: No problem to switch system to PLL
+  *          - ERROR: Problem to switch system to PLL
+  */
+static ErrorStatus UTILS_EnablePLL1AndSwitchSystem(uint32_t CPU_Frequency,
+                                                   const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  assert_param(IS_LL_UTILS_AHB_DIV(pUTILS_ClkInitStruct->AHBCLKDivider));
+  assert_param(IS_LL_UTILS_APB1_DIV(pUTILS_ClkInitStruct->APB1CLKDivider));
+  assert_param(IS_LL_UTILS_APB2_DIV(pUTILS_ClkInitStruct->APB2CLKDivider));
+  assert_param(IS_LL_UTILS_APB4_DIV(pUTILS_ClkInitStruct->APB4CLKDivider));
+  assert_param(IS_LL_UTILS_APB5_DIV(pUTILS_ClkInitStruct->APB5CLKDivider));
+
+  /* Update system clock configuration */
+  /* Enable PLL1 */
+  LL_RCC_PLL1_Enable();
+  while (LL_RCC_PLL1_IsReady() != 1U)
+  {
+    /* Wait for PLL1 ready */
+  }
+
+  LL_RCC_PLL1P_Enable();
+
+  /* Set APBx prescalers to the highest divider */
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_128);
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_128);
+  LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_128);
+  LL_RCC_SetAPB5Prescaler(LL_RCC_APB5_DIV_128);
+
+  /* Set AHB prescaler*/
+  LL_RCC_SetAHBPrescaler(pUTILS_ClkInitStruct->AHBCLKDivider);
+
+  /* CPU clock switch on the IC1 */
+  LL_RCC_SetCpuClkSource(LL_RCC_CPU_CLKSOURCE_IC1);
+  while (LL_RCC_GetCpuClkSource() != LL_RCC_CPU_CLKSOURCE_STATUS_IC1)
+  {
+    /* Wait for CPU clock switch to IC1 */
+  }
+
+  /* System buses clock switch on the IC2, IC6 and IC11 */
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11);
+  while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11)
+  {
+    /* Wait for System buses clock switch to IC2, IC6 and IC11 */
+  }
+
+  LL_SetSystemCoreClock(CPU_Frequency);
+
+  /* Set APBx prescalers */
+  LL_RCC_SetAPB1Prescaler(pUTILS_ClkInitStruct->APB1CLKDivider);
+  LL_RCC_SetAPB2Prescaler(pUTILS_ClkInitStruct->APB2CLKDivider);
+  LL_RCC_SetAPB4Prescaler(pUTILS_ClkInitStruct->APB4CLKDivider);
+  LL_RCC_SetAPB5Prescaler(pUTILS_ClkInitStruct->APB5CLKDivider);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_venc.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_venc.c
new file mode 100644
index 000000000..82cdba4bd
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_ll_venc.c
@@ -0,0 +1,148 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx_ll_venc.c
+  * @author  GPM Application Team
+  * @brief   VENC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32n6xx_ll_venc.h"
+#include "stm32n6xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+
+/** @addtogroup STM32N6xx_LL_Driver
+  * @{
+  */
+#if defined(VENC)
+
+/** @addtogroup VENC_LL
+  * @{
+  */
+
+
+/* Global variables ----------------------------------------------------------*/
+/** @addtogroup VENC_Global_Variables
+  * @{
+  */
+
+
+
+/**
+  * @}
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup VENC_Private_Types VENC Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup VENC_Private_Constants VENC Private Constants
+  * @{
+
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup VENC_Private_Macros VENC Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup VENC_Private_Variables VENC Private Variables
+  * @{
+
+ */
+
+
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+
+/* Functions Definition ------------------------------------------------------*/
+/** @addtogroup VENC_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the VENC hardware
+  * @note   to check that the initialization is correct, ASIC ID should be checked
+  * @retval None
+  */
+void LL_VENC_Init(void)
+{
+  /* make sure VENCRAM is allocated to VENC and not the system*/
+  assert_param(!LL_VENC_IS_VENCRAM_SYSTEM_ACCESSIBLE());
+
+  /* enable APB5 bus clock*/
+  /* cf. errata : SHOULD ADD REFERENCE TO THE ERRATA */
+  /* using CMSIS access because ll_bus does not contain APB5 enable macros*/
+  WRITE_REG(RCC->BUSENSR, RCC_BUSENSR_APB5ENS);
+
+  /* enable VENCRAM */
+  LL_MEM_EnableClock(LL_MEM_VENCRAM);
+
+  /* enable VENC clock */
+  LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_VENC);
+}
+
+/**
+  * @brief  De-Initialize the VENC hardware
+  * @retval None
+  */
+void LL_VENC_DeInit(void)
+{
+  /* don't turn off APB5 in DeInit because other peripherals may be using it */
+
+  /* disable VENCRAM */
+  LL_MEM_DisableClock(LL_MEM_VENCRAM);
+
+  /* disable VENC clock */
+  LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_VENC);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USE_VENC_MODULE */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/drivers/src/stm32n6xx_util_i3c.c b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_util_i3c.c
new file mode 100644
index 000000000..e2cf074fc
--- /dev/null
+++ b/stm32cube/stm32n6xx/drivers/src/stm32n6xx_util_i3c.c
@@ -0,0 +1,425 @@
+/**
+  **********************************************************************************************************************
+  * @file    stm32n6xx_util_i3c.c
+  * @author  MCD Application Team
+  * @brief   This utility help to calculate the different I3C Timing.
+  **********************************************************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  **********************************************************************************************************************
+  */
+
+/* Includes ----------------------------------------------------------------------------------------------------------*/
+#include "stm32n6xx_util_i3c.h"
+
+/** @addtogroup STM32N6xx_UTIL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILITY_I3C
+  * @{
+  */
+
+#if (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER)
+
+/* Private typedef ---------------------------------------------------------------------------------------------------*/
+/* Private define ----------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_UTIL_Private_Define I3C Utility Private Define
+  * @{
+  */
+#define SEC210PSEC              (uint64_t)100000000000 /*!< 10ps, to take two decimal float of ns calculation */
+#define TI3CH_MIN               3200U       /*!< Open drain & push pull SCL high min, 32ns */
+#define TI3CH_OD_MAX            4100U       /*!< Open drain SCL high max, 41 ns */
+#define TI3CL_OD_MIN            20000U      /*!< Open drain SCL low min, 200 ns */
+#define TFMPL_OD_MIN            50000U      /*!< Fast Mode Plus Open drain SCL low min, 500 ns */
+#define TFML_OD_MIN             130000U     /*!< Fast Mode Open drain SCL low min, 1300 ns */
+#define TFM_MIN                 250000U     /*!< Fast Mode, period min for ti3cclk, 2.5us */
+#define TSM_MIN                 1000000U    /*!< Standard Mode, period min for ti3cclk, 10us */
+#define TI3C_CAS_MIN            3840U       /*!< Time SCL after START min, 38.4 ns */
+#define TCAPA                   35000U      /*!< Capacitor effect Value measure on Nucleo around 350ns */
+#define I3C_FREQUENCY_MAX       257000000U  /*!< Maximum I3C frequency */
+/**
+  * @}
+  */
+
+/* Private macro -----------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_UTIL_Private_Macro I3C Utility Private Macro
+  * @{
+  */
+#define DIV_ROUND_CLOSEST(x, d) (((x) + ((d) / 2U)) / (d))
+/**
+  * @}
+  */
+
+/* Private function prototypes ---------------------------------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------------------------------------------------*/
+/** @defgroup I3C_UTIL_Exported_Functions I3C Utility Exported Functions
+  * @{
+  */
+
+/** @defgroup I3C_UTIL_EF_Computation Computation
+  * @{
+  */
+/**
+  * @brief  Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock.
+  * @param  pInputTiming    : [IN]  Pointer to an I3C_CtrlTimingTypeDef structure that contains
+  *                                 the required parameter for I3C timing computation.
+  * @param  pOutputConfig   : [OUT]  Pointer to an LL_I3C_CtrlBusConfTypeDef structure that contains
+  *                                  the configuration information for the specified I3C.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Timing calculation successfully
+  *          - ERROR: Parameters or timing calculation error
+  */
+ErrorStatus I3C_CtrlTimingComputation(const I3C_CtrlTimingTypeDef *pInputTiming,
+                                      LL_I3C_CtrlBusConfTypeDef *pOutputConfig)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* MIPI Standard constants */
+  /* I3C: Open drain & push pull SCL high min, tDIG_H & tDIG_H_MIXED: 32 ns */
+  uint32_t ti3ch_min       = TI3CH_MIN;
+
+  /* I3C: Open drain SCL high max, t_HIGH: 41 ns */
+  uint32_t ti3ch_od_max   = TI3CH_OD_MAX;
+
+  /* I3C: Open drain SCL high max, tHIGH: 41 ns (Ti3ch_od_max= 410)
+      I3C (pure bus): Open drain SCL low min, tLOW_OD: 200 ns */
+  uint32_t ti3cl_od_min    = TI3CL_OD_MIN;
+
+  /* I3C (mixed bus): Open drain SCL low min,
+     tLOW: 500 ns (FM+ I2C on the bus)
+     tLOW: 1300 ns (FM I2C on the bus) */
+  uint32_t tfmpl_od_min    = TFMPL_OD_MIN;
+  uint32_t tfml_od_min     = TFML_OD_MIN;
+
+  /* I2C: min ti3cclk
+          fSCL: 1 MHz (FM+)
+          fSCL: 100 kHz (SM) */
+  uint32_t tfm_min         = TFM_MIN;
+  uint32_t tsm_min         = TSM_MIN;
+
+  /* I3C: time SCL after START min, Tcas: 38,4 ns */
+  uint32_t ti3c_cas_min    = TI3C_CAS_MIN;
+
+  /* Period Clock source */
+  uint32_t ti3cclk = 0U;
+
+  /* I3C: Push pull period */
+  uint32_t ti3c_pp_min = 0U;
+
+  /* I2C: Open drain period */
+  uint32_t ti2c_od_min = 0U;
+
+  /* Time for SDA rise to 70% VDD from GND, capacitor effect */
+  /* Value measure on Nucleo around 350ns */
+  uint32_t tcapa = TCAPA;
+
+  /* Compute variable */
+  uint32_t sclhi3c;
+  uint32_t scllpp;
+  uint32_t scllod;
+  uint32_t sclhi2c;
+  uint32_t oneus;
+  uint32_t free;
+  uint32_t sdahold;
+
+  /* Verify Parameters */
+  if (pInputTiming->clockSrcFreq > I3C_FREQUENCY_MAX)
+  {
+    /* Above this frequency, some timing register parameters are over than field value */
+    status = ERROR;
+  }
+
+  if ((pInputTiming->busType != I3C_PURE_I3C_BUS) && (pInputTiming->busType != I3C_MIXED_BUS))
+  {
+    status = ERROR;
+  }
+
+  if (((pInputTiming->clockSrcFreq == 0U) || (pInputTiming->i3cPPFreq == 0U)) &&
+      (pInputTiming->busType == I3C_PURE_I3C_BUS))
+  {
+    status = ERROR;
+  }
+
+  if (((pInputTiming->clockSrcFreq == 0U) || (pInputTiming->i3cPPFreq == 0U) || (pInputTiming->i2cODFreq == 0U)) &&
+      (pInputTiming->busType == I3C_MIXED_BUS))
+  {
+    status = ERROR;
+  }
+
+  if (status == SUCCESS)
+  {
+    /* Period Clock source */
+    ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->clockSrcFreq / (uint64_t)2)) /
+                         (uint64_t)pInputTiming->clockSrcFreq);
+
+    if ((pInputTiming->dutyCycle > 50U) || (ti3cclk == 0U))
+    {
+      status = ERROR;
+    }
+  }
+
+  if ((status == SUCCESS) && (ti3cclk != 0U))
+  {
+    /* I3C: Push pull period */
+    ti3c_pp_min = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->i3cPPFreq / (uint64_t)2)) /
+                             (uint64_t)pInputTiming->i3cPPFreq);
+
+    /* I2C: Open drain period */
+    ti2c_od_min = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->i2cODFreq / (uint64_t)2)) /
+                             (uint64_t)pInputTiming->i2cODFreq);
+
+    if ((pInputTiming->busType != I3C_PURE_I3C_BUS) && (ti2c_od_min > tsm_min))
+    {
+      status = ERROR;
+    }
+  }
+
+  /* SCL Computation */
+  if ((status == SUCCESS) && (ti3cclk != 0U))
+  {
+    /* I3C SCL high level (push-pull & open drain) */
+    if (pInputTiming->busType == I3C_PURE_I3C_BUS)
+    {
+      sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * pInputTiming->dutyCycle, ti3cclk), 100U) - 1U;
+
+      /* Check if sclhi3c < ti3ch_min, in that case calculate sclhi3c based on ti3ch_min */
+      if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
+      {
+        sclhi3c = DIV_ROUND_CLOSEST(ti3ch_min, ti3cclk) - 1U;
+
+        /* Check if sclhi3c < ti3ch_min */
+        if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
+        {
+          sclhi3c += 1U;
+        }
+
+        scllpp = DIV_ROUND_CLOSEST(ti3c_pp_min, ti3cclk) - (sclhi3c + 1U) - 1U;
+      }
+      else
+      {
+        sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * pInputTiming->dutyCycle, ti3cclk), 100U) - 1U;
+
+        /* Check if sclhi3c < ti3ch_min */
+        if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
+        {
+          sclhi3c += 1U;
+        }
+
+        scllpp  = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk) + (ti3cclk / 2U)), ti3cclk) - 1U;
+      }
+
+    }
+    else
+    {
+      /* Warning: (sclhi3c + 1) * ti3cclk > Ti3ch_od_max expected */
+      sclhi3c = DIV_ROUND_CLOSEST(ti3ch_od_max, ti3cclk) - 1U;
+
+      if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
+      {
+        sclhi3c += 1U;
+      }
+      else if (((sclhi3c + 1U) * ti3cclk) > ti3ch_od_max)
+      {
+        sclhi3c = (ti3ch_od_max / ti3cclk);
+      }
+      else
+      {
+        /* Do nothing, keep sclhi3c as previously calculated */
+      }
+
+      /* I3C SCL low level (push-pull) */
+      /* tscllpp = (scllpp + 1) x ti3cclk */
+      scllpp  = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk)), ti3cclk) - 1U;
+    }
+
+    /* Check if scllpp is superior at (ti3c_pp_min + 1/2 clock source cycle) */
+    /* Goal is to choice the scllpp approach lowest, to have a value frequency highest approach as possible */
+    uint32_t ideal_scllpp = (ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk));
+    if (((scllpp + 1U) * ti3cclk) >= (ideal_scllpp + (ti3cclk / 2U) + 1U))
+    {
+      scllpp -= 1U;
+    }
+
+    /* Check if scllpp + sclhi3c is inferior at (ti3c_pp_min + 1/2 clock source cycle) */
+    /* Goal is to increase the scllpp, to have a value frequency not out of the clock request */
+    if (((scllpp + sclhi3c + 1U + 1U) * ti3cclk) < (ideal_scllpp + (ti3cclk / 2U) + 1U))
+    {
+      scllpp += 1U;
+    }
+
+    /* I3C SCL low level (pure I3C bus) */
+    if (pInputTiming->busType == I3C_PURE_I3C_BUS)
+    {
+      if (ti3c_pp_min < ti3cl_od_min)
+      {
+        scllod  = DIV_ROUND_CLOSEST(ti3cl_od_min, ti3cclk) - 1U;
+
+        if (((scllod + 1U) * ti3cclk) < ti3cl_od_min)
+        {
+          scllod += 1U;
+        }
+      }
+      else
+      {
+        scllod = scllpp;
+      }
+
+      /* Verify that SCL Open drain Low duration is superior as SDA rise time 70% */
+      if (((scllod + 1U) * ti3cclk) < tcapa)
+      {
+        scllod = DIV_ROUND_CLOSEST(tcapa, ti3cclk) + 1U;
+      }
+
+      sclhi2c = 0U; /* I2C SCL not used in pure I3C bus */
+    }
+    /* SCL low level on mixed bus (open-drain) */
+    /* I2C SCL high level (mixed bus with I2C) */
+    else
+    {
+      scllod  = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti2c_od_min * (100U - pInputTiming->dutyCycle),
+                                                    ti3cclk), 100U) - 1U;
+
+      /* Mix Bus Fast Mode plus */
+      if (ti2c_od_min < tfm_min)
+      {
+        if (((scllod + 1U) * ti3cclk) < tfmpl_od_min)
+        {
+          scllod  = DIV_ROUND_CLOSEST(tfmpl_od_min, ti3cclk) - 1U;
+        }
+      }
+      /* Mix Bus Fast Mode */
+      else
+      {
+        if (((scllod + 1U) * ti3cclk) < tfml_od_min)
+        {
+          scllod  = DIV_ROUND_CLOSEST(tfml_od_min, ti3cclk) - 1U;
+        }
+      }
+
+      sclhi2c = DIV_ROUND_CLOSEST((ti2c_od_min - ((scllod + 1U) * ti3cclk)), ti3cclk) - 1U;
+    }
+
+    /* Clock After Start computation */
+
+    /* I3C pure bus: (Tcas + tcapa)/2 */
+    if (pInputTiming->busType == I3C_PURE_I3C_BUS)
+    {
+      free = DIV_ROUND_CLOSEST((ti3c_cas_min + tcapa), (2U * ti3cclk)) + 1U;
+    }
+    /* I3C, I2C mixed: (scllod + tcapa)/2 */
+    else
+    {
+      free = DIV_ROUND_CLOSEST((((scllod + 1U) * ti3cclk) + tcapa), (2U * ti3cclk));
+    }
+
+    /* One cycle hold time addition */
+    /* By default 1/2 cycle: must be > 3 ns */
+    if (ti3cclk > 600U)
+    {
+      sdahold = 0U;
+    }
+    else
+    {
+      sdahold = 1U;
+    }
+
+    /* 1 microsecond reference */
+    oneus = DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U;
+
+    if ((scllpp > 0xFFU) || (sclhi3c > 0xFFU) || (scllod > 0xFFU) || (sclhi2c > 0xFFU) ||
+        (free > 0xFFU) || (oneus > 0xFFU))
+    {
+      /* Case of value is over 8bits, issue may be due to clocksource have a rate too high for bus clock request */
+      /* Update the return status */
+      status = ERROR;
+    }
+    else
+    {
+      /* SCL configuration */
+      pOutputConfig->SCLPPLowDuration = (uint8_t)scllpp;
+      pOutputConfig->SCLI3CHighDuration = (uint8_t)sclhi3c;
+      pOutputConfig->SCLODLowDuration = (uint8_t)scllod;
+      pOutputConfig->SCLI2CHighDuration = (uint8_t)sclhi2c;
+
+      /* Free, Idle and SDA hold time configuration */
+      pOutputConfig->BusFreeDuration = (uint8_t)free;
+      pOutputConfig->BusIdleDuration = (uint8_t)oneus;
+      pOutputConfig->SDAHoldTime = (uint32_t)(sdahold << I3C_TIMINGR1_SDA_HD_Pos);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock.
+  * @param  pInputTiming    : [IN]  Pointer to an I3C_TgtTimingTypeDef structure that contains
+  *                                 the required parameter for I3C timing computation.
+  * @param  pOutputConfig   : [OUT]  Pointer to an LL_I3C_TgtBusConfTypeDef structure that contains
+  *                                      the configuration information for the specified I3C.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Timing calculation successfully
+  *          - ERROR: Parameters or timing calculation error
+  */
+ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming,
+                                     LL_I3C_TgtBusConfTypeDef *pOutputConfig)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t oneus;
+  uint32_t ti3cclk = 0U;
+
+  /* Verify Parameters */
+  if (pInputTiming->clockSrcFreq == 0U)
+  {
+    status = ERROR;
+  }
+
+  if (status == SUCCESS)
+  {
+    /* Period Clock source */
+    ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->clockSrcFreq / (uint64_t)2)) /
+                         (uint64_t)pInputTiming->clockSrcFreq);
+
+    /* Verify Parameters */
+    if (ti3cclk == 0U)
+    {
+      status = ERROR;
+    }
+  }
+
+  if ((status == SUCCESS) && (ti3cclk != 0U))
+  {
+    /* 1 microsecond reference */
+    oneus =  DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U;
+
+    /* Bus available time configuration */
+    pOutputConfig->BusAvailableDuration = (uint8_t)oneus;
+  }
+
+  return status;
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+#endif /* (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/soc/Templates/partition_stm32n645xx.h b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n645xx.h
new file mode 100644
index 000000000..6a5a6796e
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n645xx.h
@@ -0,0 +1,792 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32n645xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N645xx Device Initial Setup for Secure / Non-Secure Zones
+  *          for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32N645XX_H
+#define PARTITION_STM32N645XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          0
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x00000000      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00000000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x00000000      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x00000000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x00000000      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x00000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x00000000      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  PVD_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  DTS_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RCC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  LOCKUP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  CACHE_ECC_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TCM_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.7>  BKP_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FPU_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> RTC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TAMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> RIFSC_TAMPER_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.13> IAC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> RCC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.16> RTC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> IWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.19> WWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI0_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI6_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.27> EXTI7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> EXTI8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> EXTI9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> EXTI10_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.31> EXTI11_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  EXTI12_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  EXTI13_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  EXTI14_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  EXTI15_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.6>  PKA_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HASH_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.8>  RNG_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.11> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.12> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.13> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.14> ADC1_2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> CSI_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> DCMIPP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.19> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.20> PAHB_ERR_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.21> NPU0_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> NPU1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> NPU2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> NPU3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> CACHEAXI_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.26> LTDC_LO_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.27> LTDC_LO_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.28> DMA2D_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> JPEG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.31> GFXMMU_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  GFXTIM_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPU2D_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPU2D_ER_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.4>  HPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  HPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  HPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  HPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  HPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.10> HPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.11> HPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.12> HPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.13> HPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.20> GPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.21> GPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.22> GPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.23> GPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.24> GPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.25> GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.3>  GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.9>  I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.10> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.14> I3C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> I3C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.19> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.22> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.27> TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.29> TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> TIM9_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.31> TIM10_IRQn            <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS3_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..159
+//   <o.0>  TIM11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM12_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM13_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM14_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM15_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TIM16_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TIM17_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM18_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  LPTIM1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPTIM2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> LPTIM3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.11> LPTIM4_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> LPTIM5_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.13> ADF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.14> MDF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.15> MDF1_FLT1_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.16> MDF1_FLT2_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.17> MDF1_FLT3_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.18> MDF1_FLT4_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.19> MDF1_FLT5_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.20> SAI1_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.21> SAI1_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.22> SAI2_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.23> SAI2_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPDIFRX1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> SPI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> SPI3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> SPI4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> SPI5_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> SPI6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> USART1_IRQn         <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    1
+
+/*
+// Interrupts 160..191
+//   <o.0>  USART2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  USART3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  USART6_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  UART8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  UART9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  USART10_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPUART1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.10> XSPI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> XSPI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> XSPI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> SDMMC1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.16> UCPD1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> USB1_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.18> USB2_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.19> ETH1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> FDCAN1_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.21> FDCAN1_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.22> FDCAN2_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.23> FDCAN2_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.24> FDCAN3_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.25> FDCAN3_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.26> FDCAN_CU_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.27> MDIOS_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> DCMI_PSSI_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.29> WAKEUP_PIN_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.30> CTI_INT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.31> CTI_INT1_IRQn       <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    1
+
+/*
+// Interrupts 192..223
+//   <o.0>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LTDC_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LTDC_UP_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif    
+
+}
+
+#endif  /* PARTITION_STM32N645XX_H */
diff --git a/stm32cube/stm32n6xx/soc/Templates/partition_stm32n647xx.h b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n647xx.h
new file mode 100644
index 000000000..8283b5c64
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n647xx.h
@@ -0,0 +1,792 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32n647xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N647xx Device Initial Setup for Secure / Non-Secure Zones
+  *          for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32N647XX_H
+#define PARTITION_STM32N647XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          0
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x00000000      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00000000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x00000000      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x00000000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x00000000      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x00000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x00000000      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  PVD_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  DTS_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RCC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  LOCKUP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  CACHE_ECC_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TCM_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.7>  BKP_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FPU_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> RTC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TAMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> RIFSC_TAMPER_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.13> IAC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> RCC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.16> RTC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> IWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.19> WWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI0_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI6_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.27> EXTI7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> EXTI8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> EXTI9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> EXTI10_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.31> EXTI11_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  EXTI12_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  EXTI13_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  EXTI14_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  EXTI15_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.6>  PKA_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HASH_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.8>  RNG_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.11> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.12> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.13> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.14> ADC1_2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> CSI_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> DCMIPP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.19> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.20> PAHB_ERR_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.21> NPU0_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> NPU1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> NPU2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> NPU3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> CACHEAXI_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.26> LTDC_LO_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.27> LTDC_LO_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.28> DMA2D_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> JPEG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> VENC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> GFXMMU_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  GFXTIM_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPU2D_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPU2D_ER_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.4>  HPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  HPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  HPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  HPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  HPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.10> HPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.11> HPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.12> HPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.13> HPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.20> GPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.21> GPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.22> GPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.23> GPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.24> GPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.25> GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.3>  GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.9>  I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.10> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.14> I3C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> I3C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.19> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.22> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.27> TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.29> TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> TIM9_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.31> TIM10_IRQn            <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS3_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..159
+//   <o.0>  TIM11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM12_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM13_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM14_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM15_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TIM16_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TIM17_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM18_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  LPTIM1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPTIM2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> LPTIM3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.11> LPTIM4_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> LPTIM5_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.13> ADF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.14> MDF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.15> MDF1_FLT1_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.16> MDF1_FLT2_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.17> MDF1_FLT3_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.18> MDF1_FLT4_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.19> MDF1_FLT5_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.20> SAI1_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.21> SAI1_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.22> SAI2_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.23> SAI2_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPDIFRX1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> SPI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> SPI3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> SPI4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> SPI5_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> SPI6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> USART1_IRQn         <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    1
+
+/*
+// Interrupts 160..191
+//   <o.0>  USART2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  USART3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  USART6_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  UART8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  UART9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  USART10_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPUART1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.10> XSPI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> XSPI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> XSPI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> SDMMC1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.16> UCPD1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> USB1_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.18> USB2_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.19> ETH1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> FDCAN1_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.21> FDCAN1_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.22> FDCAN2_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.23> FDCAN2_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.24> FDCAN3_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.25> FDCAN3_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.26> FDCAN_CU_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.27> MDIOS_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> DCMI_PSSI_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.29> WAKEUP_PIN_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.30> CTI_INT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.31> CTI_INT1_IRQn       <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    1
+
+/*
+// Interrupts 192..223
+//   <o.0>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LTDC_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LTDC_UP_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif    
+
+}
+
+#endif  /* PARTITION_STM32N647XX_H */
diff --git a/stm32cube/stm32n6xx/soc/Templates/partition_stm32n655xx.h b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n655xx.h
new file mode 100644
index 000000000..055603e91
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n655xx.h
@@ -0,0 +1,792 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32n655xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N655xx Device Initial Setup for Secure / Non-Secure Zones
+  *          for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32N655XX_H
+#define PARTITION_STM32N655XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          0
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x00000000      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00000000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x00000000      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x00000000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x00000000      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x00000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x00000000      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  PVD_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  DTS_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RCC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  LOCKUP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  CACHE_ECC_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TCM_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.7>  BKP_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FPU_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> RTC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TAMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> RIFSC_TAMPER_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.13> IAC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> RCC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.16> RTC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> IWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.19> WWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI0_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI6_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.27> EXTI7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> EXTI8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> EXTI9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> EXTI10_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.31> EXTI11_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  EXTI12_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  EXTI13_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  EXTI14_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  EXTI15_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.5>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.6>  PKA_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HASH_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.8>  RNG_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.11> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.12> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.13> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.14> ADC1_2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> CSI_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> DCMIPP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.19> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.20> PAHB_ERR_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.21> NPU0_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> NPU1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> NPU2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> NPU3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> CACHEAXI_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.26> LTDC_LO_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.27> LTDC_LO_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.28> DMA2D_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> JPEG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.31> GFXMMU_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  GFXTIM_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPU2D_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPU2D_ER_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.4>  HPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  HPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  HPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  HPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  HPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.10> HPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.11> HPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.12> HPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.13> HPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.20> GPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.21> GPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.22> GPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.23> GPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.24> GPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.25> GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.3>  GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.9>  I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.10> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.14> I3C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> I3C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.19> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.22> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.27> TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.29> TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> TIM9_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.31> TIM10_IRQn            <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS3_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..159
+//   <o.0>  TIM11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM12_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM13_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM14_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM15_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TIM16_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TIM17_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM18_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  LPTIM1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPTIM2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> LPTIM3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.11> LPTIM4_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> LPTIM5_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.13> ADF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.14> MDF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.15> MDF1_FLT1_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.16> MDF1_FLT2_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.17> MDF1_FLT3_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.18> MDF1_FLT4_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.19> MDF1_FLT5_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.20> SAI1_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.21> SAI1_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.22> SAI2_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.23> SAI2_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPDIFRX1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> SPI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> SPI3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> SPI4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> SPI5_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> SPI6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> USART1_IRQn         <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    1
+
+/*
+// Interrupts 160..191
+//   <o.0>  USART2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  USART3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  USART6_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  UART8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  UART9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  USART10_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPUART1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.10> XSPI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> XSPI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> XSPI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> SDMMC1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.16> UCPD1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> USB1_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.18> USB2_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.19> ETH1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> FDCAN1_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.21> FDCAN1_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.22> FDCAN2_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.23> FDCAN2_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.24> FDCAN3_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.25> FDCAN3_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.26> FDCAN_CU_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.27> MDIOS_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> DCMI_PSSI_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.29> WAKEUP_PIN_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.30> CTI_INT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.31> CTI_INT1_IRQn       <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    1
+
+/*
+// Interrupts 192..223
+//   <o.0>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LTDC_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LTDC_UP_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif    
+
+}
+
+#endif  /* PARTITION_STM32N655XX_H */
diff --git a/stm32cube/stm32n6xx/soc/Templates/partition_stm32n657xx.h b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n657xx.h
new file mode 100644
index 000000000..713068609
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/Templates/partition_stm32n657xx.h
@@ -0,0 +1,792 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32n657xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones
+  *          for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32N657XX_H
+#define PARTITION_STM32N657XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          0
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   0
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x00000000      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x00000000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x00000000      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x00000000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x00000000      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x00000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x00000000      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00000000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00000000      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  PVD_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  DTS_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RCC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.4>  LOCKUP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  CACHE_ECC_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TCM_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.7>  BKP_ECC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FPU_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> RTC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> TAMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> RIFSC_TAMPER_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.13> IAC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> RCC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.16> RTC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> IWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.19> WWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI0_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI6_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.27> EXTI7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> EXTI8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> EXTI9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> EXTI10_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.31> EXTI11_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  EXTI12_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  EXTI13_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  EXTI14_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  EXTI15_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  SAES_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.5>  CRYP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.6>  PKA_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HASH_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.8>  RNG_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.9>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.10> MCE1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.11> MCE2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.12> MCE3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.13> MCE4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.14> ADC1_2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> CSI_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.16> DCMIPP_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.18> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.19> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.20> PAHB_ERR_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.21> NPU0_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.22> NPU1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.23> NPU2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.24> NPU3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.25> CACHEAXI_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.26> LTDC_LO_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.27> LTDC_LO_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.28> DMA2D_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.29> JPEG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> VENC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> GFXMMU_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  GFXTIM_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPU2D_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPU2D_ER_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  ICACHE_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.4>  HPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  HPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.6>  HPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.7>  HPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.8>  HPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.9>  HPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.10> HPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.11> HPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.12> HPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.13> HPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.20> GPDMA1_Channel0_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.21> GPDMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.22> GPDMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.23> GPDMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.24> GPDMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.25> GPDMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.26> GPDMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.27> GPDMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.28> GPDMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.29> GPDMA1_Channel9_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..127
+//   <o.0>  GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.1>  GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.2>  GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.3>  GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I2C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  I2C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  I2C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  I2C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  I2C3_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.9>  I2C3_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.10> I2C4_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> I2C4_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> I3C1_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> I3C1_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.14> I3C2_EV_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> I3C2_ER_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM1_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM1_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM1_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.19> TIM1_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> TIM2_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.21> TIM3_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.22> TIM4_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.23> TIM5_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.24> TIM6_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.25> TIM7_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.26> TIM8_BRK_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.27> TIM8_UP_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> TIM8_TRG_COM_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.29> TIM8_CC_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.30> TIM9_IRQn             <0=> Secure state <1=> Non-Secure state
+//   <o.31> TIM10_IRQn            <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS3_VAL     0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4    1
+
+/*
+// Interrupts 128..159
+//   <o.0>  TIM11_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  TIM12_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  TIM13_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  TIM14_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TIM15_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TIM16_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TIM17_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM18_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  LPTIM1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPTIM2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> LPTIM3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.11> LPTIM4_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> LPTIM5_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.13> ADF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.14> MDF1_FLT0_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.15> MDF1_FLT1_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.16> MDF1_FLT2_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.17> MDF1_FLT3_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.18> MDF1_FLT4_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.19> MDF1_FLT5_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.20> SAI1_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.21> SAI1_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.22> SAI2_A_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.23> SAI2_B_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.24> SPDIFRX1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.25> SPI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.26> SPI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> SPI3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> SPI4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> SPI5_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.30> SPI6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.31> USART1_IRQn         <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS4_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5    1
+
+/*
+// Interrupts 160..191
+//   <o.0>  USART2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.1>  USART3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.2>  UART4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.3>  UART5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  USART6_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  UART7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  UART8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  UART9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  USART10_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.9>  LPUART1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.10> XSPI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> XSPI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> XSPI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> FMC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.14> SDMMC1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> SDMMC2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.16> UCPD1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> USB1_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.18> USB2_OTG_HS_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.19> ETH1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.20> FDCAN1_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.21> FDCAN1_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.22> FDCAN2_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.23> FDCAN2_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.24> FDCAN3_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.25> FDCAN3_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.26> FDCAN_CU_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.27> MDIOS_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.28> DCMI_PSSI_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.29> WAKEUP_PIN_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.30> CTI_INT0_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.31> CTI_INT1_IRQn       <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS5_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6    1
+
+/*
+// Interrupts 192..223
+//   <o.0>  Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.1>  LTDC_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LTDC_UP_ERR_IRQn    <0=> Secure state <1=> Non-Secure state
+
+*/
+#define NVIC_INIT_ITNS6_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+  #endif    
+
+}
+
+#endif  /* PARTITION_STM32N657XX_H */
diff --git a/stm32cube/stm32n6xx/soc/partition_stm32n6xx.h b/stm32cube/stm32n6xx/soc/partition_stm32n6xx.h
new file mode 100644
index 000000000..6f3c56525
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/partition_stm32n6xx.h
@@ -0,0 +1,71 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32n6xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N6xx Device Header File for Initial Setup for
+  *          Secure / Non-Secure Zones based on CMSIS CORE V5.3.1
+  *
+  *          The file is included in system_stm32L5xx_s.c in secure application.
+  *          It includes the configuration section that allows to select the
+  *          STM32N6xx device partitioning file for system core secure attributes
+  *          and interrupt secure and non-secure assignment.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32N6xx
+  * @{
+  */
+
+#ifndef PARTITION_STM32N6XX_H
+#define PARTITION_STM32N6XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Secure_configuration_section
+  * @{
+  */
+
+#if defined(STM32N657xx)
+  #include "partition_stm32n657xx.h"
+#elif defined(STM32N655xx)
+  #include "partition_stm32n655xx.h"
+#elif defined(STM32N647xx)
+  #include "partition_stm32n647xx.h"
+#elif defined(STM32N645xx)
+  #include "partition_stm32n645xx.h"
+#else
+  #error "Please select first the target STM32N6xx device used in your application (in stm32n6xx.h file)"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* PARTITION_STM32N6XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/soc/stm32n645xx.h b/stm32cube/stm32n6xx/soc/stm32n645xx.h
new file mode 100644
index 000000000..cda58c8ed
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/stm32n645xx.h
@@ -0,0 +1,41437 @@
+/**
+  ******************************************************************************
+  * @file    stm32n645xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N645xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+#ifndef STM32N645xx_H
+#define STM32N645xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup ST
+  * @{
+  */
+
+/** @addtogroup STM32N645xx
+  * @{
+  */
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+typedef enum
+{
+/* ======================================  ARM Cortex-M55 Specific Interrupt Numbers  ======================================== */
+  NonMaskableInt_IRQn        = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted                         */
+  HardFault_IRQn             = -13,    /*!< -13 Hard Fault, all classes of Fault                                               */
+  MemoryManagement_IRQn      = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match       */
+  BusFault_IRQn              = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn            = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition                  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  SecureFault_IRQn           = -9,     /*!< -9  Secure Fault                                                                   */
+#endif
+  SVCall_IRQn                = -5,     /*!< -5  System Service Call via SVC instruction                                        */
+  DebugMonitor_IRQn          = -4,     /*!< -4  Debug Monitor                                                                  */
+  PendSV_IRQn                = -2,     /*!< -2  Pendable request for system service                                            */
+  SysTick_IRQn               = -1,     /*!< -1  System Tick Timer                                                              */
+
+/* ======================================  STM32N6xx Specific Interrupt Numbers  ============================================= */
+  PVD_PVM_IRQn               = 0,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection                                */
+  DTS_IRQn                   = 2,      /*!< Thermal Sensor interruption                                                        */
+  RCC_IRQn                   = 3,      /*!< RCC non-secure global interrupts through EXTI Line detection                       */
+  LOCKUP_IRQn                = 4,      /*!< LOCKUP / (no Overstack in CM55)                                                    */
+  CACHE_ECC_IRQn             = 5,      /*!< Error ECC cache interrupt                                                          */
+  TCM_ECC_IRQn               = 6,      /*!< TCM ECC interrupts                                                                 */
+  BKP_ECC_IRQn               = 7,      /*!< Backup RAM Interrupts                                                              */
+  FPU_IRQn                   = 8,      /*!< FPU interrupt                                                                      */
+  RTC_S_IRQn                 = 10,     /*!< RTC secure interrupts through EXTI Line detection                                  */
+  TAMP_IRQn                  = 11,     /*!< Tamper secure and non-secure interrupts through EXTI Line detection                */
+  RIFSC_TAMPER_IRQn          = 12,     /*!< RIF Tamper interrupts                                                              */
+  IAC_IRQn                   = 13,     /*!< IAC interrupt                                                                      */
+  RCC_S_IRQn                 = 14,     /*!< RCC secure global interrupts through EXTI Line detection                           */
+  RTC_IRQn                   = 16,     /*!< RTC non-secure interrupts through EXTI Line detection                              */
+  IWDG_IRQn                  = 18,     /*!< Internal Watchdog interrupt                                                        */
+  WWDG_IRQn                  = 19,     /*!< Window Watchdog interrupt                                                          */
+  EXTI0_IRQn                 = 20,     /*!< EXTI Line0 interrupt                                                               */
+  EXTI1_IRQn                 = 21,     /*!< EXTI Line1 interrupt                                                               */
+  EXTI2_IRQn                 = 22,     /*!< EXTI Line2 interrupt                                                               */
+  EXTI3_IRQn                 = 23,     /*!< EXTI Line3 interrupt                                                               */
+  EXTI4_IRQn                 = 24,     /*!< EXTI Line4 interrupt                                                               */
+  EXTI5_IRQn                 = 25,     /*!< EXTI Line5 interrupt                                                               */
+  EXTI6_IRQn                 = 26,     /*!< EXTI Line6 interrupt                                                               */
+  EXTI7_IRQn                 = 27,     /*!< EXTI Line7 interrupt                                                               */
+  EXTI8_IRQn                 = 28,     /*!< EXTI Line8 interrupt                                                               */
+  EXTI9_IRQn                 = 29,     /*!< EXTI Line9 interrupt                                                               */
+  EXTI10_IRQn                = 30,     /*!< EXTI Line10 interrupt                                                              */
+  EXTI11_IRQn                = 31,     /*!< EXTI Line11 interrupt                                                              */
+  EXTI12_IRQn                = 32,     /*!< EXTI Line12 interrupt                                                              */
+  EXTI13_IRQn                = 33,     /*!< EXTI Line13 interrupt                                                              */
+  EXTI14_IRQn                = 34,     /*!< EXTI Line14 interrupt                                                              */
+  EXTI15_IRQn                = 35,     /*!< EXTI Line15 interrupt                                                              */
+  PKA_IRQn                   = 38,     /*!< PKA interrupt                                                                      */
+  HASH_IRQn                  = 39,     /*!< HASH interrupt                                                                     */
+  RNG_IRQn                   = 40,     /*!< RNG global interrupt                                                               */
+  ADC1_2_IRQn                = 46,     /*!< ADC1 & ADC2 interrupt                                                              */
+  CSI_IRQn                   = 47,     /*!< CSI global interrupt                                                               */
+  DCMIPP_IRQn                = 48,     /*!< DCMIPP global interrupt                                                            */
+  PAHB_ERR_IRQn              = 52,     /*!< PAHB error interrupt                                                               */
+  LTDC_LO_IRQn               = 58,     /*!< LTDC low-layer global interrupt                                                    */
+  LTDC_LO_ERR_IRQn           = 59,     /*!< LTDC low-layer error interrupt                                                     */
+  DMA2D_IRQn                 = 60,     /*!< DMA2D global interrupt                                                             */
+  JPEG_IRQn                  = 61,     /*!< JPEG global interrupt                                                              */
+  VENC_IRQn                  = 62,     /*!< VENC global interrupt                                                              */
+  GFXMMU_IRQn                = 63,     /*!< GFXMMU global interrupt                                                            */
+  GFXTIM_IRQn                = 64,     /*!< GFXTIM global interrupt                                                            */
+  GPU2D_IRQn                 = 65,     /*!< GPU2D interrupt                                                                    */
+  GPU2D_ER_IRQn              = 66,     /*!< GPU2D error interrupt                                                              */
+  ICACHE_IRQn                = 67,     /*!< GPU2D cache interrupt                                                              */
+  HPDMA1_Channel0_IRQn       = 68,     /*!< HPDMA1 Channel 0 global interrupt                                                  */
+  HPDMA1_Channel1_IRQn       = 69,     /*!< HPDMA1 Channel 1 global interrupt                                                  */
+  HPDMA1_Channel2_IRQn       = 70,     /*!< HPDMA1 Channel 2 global interrupt                                                  */
+  HPDMA1_Channel3_IRQn       = 71,     /*!< HPDMA1 Channel 3 global interrupt                                                  */
+  HPDMA1_Channel4_IRQn       = 72,     /*!< HPDMA1 Channel 4 global interrupt                                                  */
+  HPDMA1_Channel5_IRQn       = 73,     /*!< HPDMA1 Channel 5 global interrupt                                                  */
+  HPDMA1_Channel6_IRQn       = 74,     /*!< HPDMA1 Channel 6 global interrupt                                                  */
+  HPDMA1_Channel7_IRQn       = 75,     /*!< HPDMA1 Channel 7 global interrupt                                                  */
+  HPDMA1_Channel8_IRQn       = 76,     /*!< HPDMA1 Channel 8 global interrupt                                                  */
+  HPDMA1_Channel9_IRQn       = 77,     /*!< HPDMA1 Channel 9 global interrupt                                                  */
+  HPDMA1_Channel10_IRQn      = 78,     /*!< HPDMA1 Channel 10 global interrupt                                                 */
+  HPDMA1_Channel11_IRQn      = 79,     /*!< HPDMA1 Channel 11 global interrupt                                                 */
+  HPDMA1_Channel12_IRQn      = 80,     /*!< HPDMA1 Channel 12 global interrupt                                                 */
+  HPDMA1_Channel13_IRQn      = 81,     /*!< HPDMA1 Channel 13 global interrupt                                                 */
+  HPDMA1_Channel14_IRQn      = 82,     /*!< HPDMA1 Channel 14 global interrupt                                                 */
+  HPDMA1_Channel15_IRQn      = 83,     /*!< HPDMA1 Channel 15 global interrupt                                                 */
+  GPDMA1_Channel0_IRQn       = 84,     /*!< GPDMA1 Channel 0 interrupt                                                         */
+  GPDMA1_Channel1_IRQn       = 85,     /*!< GPDMA1 Channel 1 interrupt                                                         */
+  GPDMA1_Channel2_IRQn       = 86,     /*!< GPDMA1 Channel 2 interrupt                                                         */
+  GPDMA1_Channel3_IRQn       = 87,     /*!< GPDMA1 Channel 3 interrupt                                                         */
+  GPDMA1_Channel4_IRQn       = 88,     /*!< GPDMA1 Channel 4 interrupt                                                         */
+  GPDMA1_Channel5_IRQn       = 89,     /*!< GPDMA1 Channel 5 interrupt                                                         */
+  GPDMA1_Channel6_IRQn       = 90,     /*!< GPDMA1 Channel 6 interrupt                                                         */
+  GPDMA1_Channel7_IRQn       = 91,     /*!< GPDMA1 Channel 7 interrupt                                                         */
+  GPDMA1_Channel8_IRQn       = 92,     /*!< GPDMA1 Channel 8 interrupt                                                         */
+  GPDMA1_Channel9_IRQn       = 93,     /*!< GPDMA1 Channel 9 interrupt                                                         */
+  GPDMA1_Channel10_IRQn      = 94,     /*!< GPDMA1 Channel 10 interrupt                                                        */
+  GPDMA1_Channel11_IRQn      = 95,     /*!< GPDMA1 Channel 11 interrupt                                                        */
+  GPDMA1_Channel12_IRQn      = 96,     /*!< GPDMA1 Channel 12 interrupt                                                        */
+  GPDMA1_Channel13_IRQn      = 97,     /*!< GPDMA1 Channel 13 interrupt                                                        */
+  GPDMA1_Channel14_IRQn      = 98,     /*!< GPDMA1 Channel 14 interrupt                                                        */
+  GPDMA1_Channel15_IRQn      = 99,     /*!< GPDMA1 Channel 15 interrupt                                                        */
+  I2C1_EV_IRQn               = 100,    /*!< I2C1 event interrupt                                                               */
+  I2C1_ER_IRQn               = 101,    /*!< I2C1 error interrupt                                                               */
+  I2C2_EV_IRQn               = 102,    /*!< I2C2 event interrupt                                                               */
+  I2C2_ER_IRQn               = 103,    /*!< I2C2 error interrupt                                                               */
+  I2C3_EV_IRQn               = 104,    /*!< I2C3 event interrupt                                                               */
+  I2C3_ER_IRQn               = 105,    /*!< I2C3 error interrupt                                                               */
+  I2C4_EV_IRQn               = 106,    /*!< I2C4 event interrupt                                                               */
+  I2C4_ER_IRQn               = 107,    /*!< I2C4 error interrupt                                                               */
+  I3C1_EV_IRQn               = 108,    /*!< I3C1 event interrupt                                                               */
+  I3C1_ER_IRQn               = 109,    /*!< I3C1 error interrupt                                                               */
+  I3C2_EV_IRQn               = 110,    /*!< I3C2 event interrupt                                                               */
+  I3C2_ER_IRQn               = 111,    /*!< I3C2 error interrupt                                                               */
+  TIM1_BRK_IRQn              = 112,    /*!< TIM1 Break interrupt                                                               */
+  TIM1_UP_IRQn               = 113,    /*!< TIM1 Update interrupt                                                              */
+  TIM1_TRG_COM_IRQn          = 114,    /*!< TIM1 Trigger and Commutation interrupt                                             */
+  TIM1_CC_IRQn               = 115,    /*!< TIM1 Capture Compare interrupt                                                     */
+  TIM2_IRQn                  = 116,    /*!< TIM2 global interrupt                                                              */
+  TIM3_IRQn                  = 117,    /*!< TIM3 global interrupt                                                              */
+  TIM4_IRQn                  = 118,    /*!< TIM4 global interrupt                                                              */
+  TIM5_IRQn                  = 119,    /*!< TIM5 global interrupt                                                              */
+  TIM6_IRQn                  = 120,    /*!< TIM6 global interrupt                                                              */
+  TIM7_IRQn                  = 121,    /*!< TIM7 global interrupt                                                              */
+  TIM8_BRK_IRQn              = 122,    /*!< TIM8 Break interrupt                                                               */
+  TIM8_UP_IRQn               = 123,    /*!< TIM8 Update interrupt                                                              */
+  TIM8_TRG_COM_IRQn          = 124,    /*!< TIM8 Trigger and Commutation interrupt                                             */
+  TIM8_CC_IRQn               = 125,    /*!< TIM8 Capture Compare interrupt                                                     */
+  TIM9_IRQn                  = 126,    /*!< TIM9 global interrupt                                                              */
+  TIM10_IRQn                 = 127,    /*!< TIM10 global interrupt                                                             */
+  TIM11_IRQn                 = 128,    /*!< TIM11 global interrupt                                                             */
+  TIM12_IRQn                 = 129,    /*!< TIM12 global interrupt                                                             */
+  TIM13_IRQn                 = 130,    /*!< TIM13 global interrupt                                                             */
+  TIM14_IRQn                 = 131,    /*!< TIM14 global interrupt                                                             */
+  TIM15_IRQn                 = 132,    /*!< TIM15 global interrupt                                                             */
+  TIM16_IRQn                 = 133,    /*!< TIM16 global interrupt                                                             */
+  TIM17_IRQn                 = 134,    /*!< TIM17 global interrupt                                                             */
+  TIM18_IRQn                 = 135,    /*!< TIM18 global interrupt                                                             */
+  LPTIM1_IRQn                = 136,    /*!< LPTIM1 global interrupt                                                            */
+  LPTIM2_IRQn                = 137,    /*!< LPTIM2 global interrupt                                                            */
+  LPTIM3_IRQn                = 138,    /*!< LPTIM3 global interrupt                                                            */
+  LPTIM4_IRQn                = 139,    /*!< LPTIM4 global interrupt                                                            */
+  LPTIM5_IRQn                = 140,    /*!< LPTIM5 global interrupt                                                            */
+  ADF1_FLT0_IRQn             = 141,    /*!< ADF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT0_IRQn             = 142,    /*!< MDF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT1_IRQn             = 143,    /*!< MDF1 Filter 1 global interrupt                                                     */
+  MDF1_FLT2_IRQn             = 144,    /*!< MDF1 Filter 2 global interrupt                                                     */
+  MDF1_FLT3_IRQn             = 145,    /*!< MDF1 Filter 3 global interrupt                                                     */
+  MDF1_FLT4_IRQn             = 146,    /*!< MDF1 Filter 4 global interrupt                                                     */
+  MDF1_FLT5_IRQn             = 147,    /*!< MDF1 Filter 5 global interrupt                                                     */
+  SAI1_A_IRQn                = 148,    /*!< Serial Audio Interface 1 block A interrupt                                         */
+  SAI1_B_IRQn                = 149,    /*!< Serial Audio Interface 1 block B interrupt                                         */
+  SAI2_A_IRQn                = 150,    /*!< Serial Audio Interface 2 block A interrupt                                         */
+  SAI2_B_IRQn                = 151,    /*!< Serial Audio Interface 2 block B interrupt                                         */
+  SPDIFRX1_IRQn              = 152,    /*!< SPDIFRX1 interrupt                                                                 */
+  SPI1_IRQn                  = 153,    /*!< SPI1 global interrupt                                                              */
+  SPI2_IRQn                  = 154,    /*!< SPI2 global interrupt                                                              */
+  SPI3_IRQn                  = 155,    /*!< SPI3 global interrupt                                                              */
+  SPI4_IRQn                  = 156,    /*!< SPI4 global interrupt                                                              */
+  SPI5_IRQn                  = 157,    /*!< SPI5 global interrupt                                                              */
+  SPI6_IRQn                  = 158,    /*!< SPI6 global interrupt                                                              */
+  USART1_IRQn                = 159,    /*!< USART1 global interrupt                                                            */
+  USART2_IRQn                = 160,    /*!< USART2 global interrupt                                                            */
+  USART3_IRQn                = 161,    /*!< USART3 global interrupt                                                            */
+  UART4_IRQn                 = 162,    /*!< UART4 global interrupt                                                             */
+  UART5_IRQn                 = 163,    /*!< UART5 global interrupt                                                             */
+  USART6_IRQn                = 164,    /*!< USART3 global interrupt                                                            */
+  UART7_IRQn                 = 165,    /*!< UART7 global interrupt                                                             */
+  UART8_IRQn                 = 166,    /*!< UART8 global interrupt                                                             */
+  UART9_IRQn                 = 167,    /*!< UART9 global interrupt                                                             */
+  USART10_IRQn               = 168,    /*!< USART10 global interrupt                                                           */
+  LPUART1_IRQn               = 169,    /*!< LPUART1 global interrupt                                                           */
+  XSPI1_IRQn                 = 170,    /*!< XSPI1 global interrupt                                                             */
+  XSPI2_IRQn                 = 171,    /*!< XSPI2 global interrupt                                                             */
+  XSPI3_IRQn                 = 172,    /*!< XSPI3 global interrupt                                                             */
+  FMC_IRQn                   = 173,    /*!< FMC global interrupt                                                               */
+  SDMMC1_IRQn                = 174,    /*!< SDMMC1 global interrupt                                                            */
+  SDMMC2_IRQn                = 175,    /*!< SDMMC2 global interrupt                                                            */
+  UCPD1_IRQn                 = 176,    /*!< UCPD1 global interrupt                                                             */
+  USB1_OTG_HS_IRQn           = 177,    /*!< USB1 OTG HS interrupt                                                              */
+  USB2_OTG_HS_IRQn           = 178,    /*!< USB2 OTG HS interrupt                                                              */
+  ETH1_IRQn                  = 179,    /*!< ETH1 global interrupt                                                              */
+  FDCAN1_IT0_IRQn            = 180,    /*!< FDCAN1 interrupt 0                                                                 */
+  FDCAN1_IT1_IRQn            = 181,    /*!< FDCAN1 interrupt 1                                                                 */
+  FDCAN2_IT0_IRQn            = 182,    /*!< FDCAN2 interrupt 0                                                                 */
+  FDCAN2_IT1_IRQn            = 183,    /*!< FDCAN2 interrupt 1                                                                 */
+  FDCAN3_IT0_IRQn            = 184,    /*!< FDCAN3 interrupt 0                                                                 */
+  FDCAN3_IT1_IRQn            = 185,    /*!< FDCAN3 interrupt 1                                                                 */
+  FDCAN_CU_IRQn              = 186,    /*!< FDCAN Clock Unit interrupt                                                         */
+  MDIOS_IRQn                 = 187,    /*!< MDIOS global interrupt                                                             */
+  DCMI_PSSI_IRQn             = 188,    /*!< DCMI/PSSI global interrupt                                                         */
+  WAKEUP_PIN_IRQn            = 189,    /*!< Wake-up pins interrupt                                                             */
+  CTI_INT0_IRQn              = 190,    /*!< CTI INT0 interrupt                                                                 */
+  CTI_INT1_IRQn              = 191,    /*!< CTI INT1 interrupt                                                                 */
+  LTDC_UP_IRQn               = 193,    /*!< LTDC up-layer global interrupt                                                     */
+  LTDC_UP_ERR_IRQn           = 194,    /*!< LTDC up-layer error interrupt                                                      */
+} IRQn_Type;
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/**
+  * @brief Configuration of the Cortex-M55 Processor and Core Peripherals
+   */
+#define __CM55_REV                0x0101U /*!< Cortex-M55 revision r1p1                      */
+#define __FPU_PRESENT             1U      /*!< CM55 Floating Point Unit present              */
+#define __DSP_PRESENT             1U      /*!< CM55 Digital Signal Processing Unit present   */
+#define __MPU_PRESENT             1U      /*!< CM55 Memory Programming Unit present          */
+#define __ICACHE_PRESENT          1U      /*!< CM55 Instruction cache present                */
+#define __DCACHE_PRESENT          1U      /*!< CM55 Data cache present                       */
+#define __VTOR_PRESENT            1U      /*!< CM55 Vector table offset register present     */
+#define __PMU_PRESENT             1U      /*!< CM55 Performance Monitoring Unit present      */
+#define __PMU_NUM_EVENTCNT        8U      /*!< CM55 can monitor up to 8 PMU events           */
+#define __NVIC_PRIO_BITS          4U      /*!< CM55 uses 4 bits for the Priority Levels      */
+#define __Vendor_SysTickConfig    0U      /*!< Set to 1 if different SysTick Config is used  */
+#define __SAUREGION_PRESENT       1U      /*!< SAU regions present                           */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define CPU_IN_SECURE_STATE
+#endif
+
+#define CPU_AS_TRUSTED_DOMAIN
+
+#include "core_cm55.h"                    /*!< ARM Cortex-M55 processor and core peripherals */
+#include "system_stm32n6xx.h"             /*!< STM32N6xx System */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup STM32N6xx_peripherals
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter (ADC)
+  */
+typedef struct
+{
+  __IO uint32_t ISR;           /*!< ADC interrupt and status register,                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< ADC interrupt enable register,                         Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< ADC control register,                                  Address offset: 0x08 */
+  __IO uint32_t CFGR1;         /*!< ADC configuration register 1,                          Address offset: 0x0C */
+  __IO uint32_t CFGR2;         /*!< ADC configuration register 2,                          Address offset: 0x10 */
+  __IO uint32_t SMPR1;         /*!< ADC sample time register 1,                            Address offset: 0x14 */
+  __IO uint32_t SMPR2;         /*!< ADC sample time register 2,                            Address offset: 0x18 */
+  __IO uint32_t PCSEL;         /*!< ADC channel preselection register,                     Address offset: 0x1C */
+  uint32_t      RESERVED1[4];  /*!< Reserved,                                              Address offset: 0x020-0x02C */
+  __IO uint32_t SQR1;          /*!< ADC regular sequence register 1,                       Address offset: 0x30 */
+  __IO uint32_t SQR2;          /*!< ADC regular sequence register 2,                       Address offset: 0x34 */
+  __IO uint32_t SQR3;          /*!< ADC regular sequence register 3,                       Address offset: 0x38 */
+  __IO uint32_t SQR4;          /*!< ADC regular sequence register 4,                       Address offset: 0x3C */
+  __IO uint32_t DR;            /*!< ADC regular data register,                             Address offset: 0x40 */
+  uint32_t      RESERVED2[2];  /*!< Reserved,                                              Address offset: 0x044-0x048 */
+  __IO uint32_t JSQR;          /*!< ADC injected sequence register,                        Address offset: 0x4C */
+  __IO uint32_t OFCFGR1;       /*!< ADC offset configuration register 1,                   Address offset: 0x50 */
+  __IO uint32_t OFCFGR2;       /*!< ADC offset configuration register 2,                   Address offset: 0x54 */
+  __IO uint32_t OFCFGR3;       /*!< ADC offset configuration register 3,                   Address offset: 0x58 */
+  __IO uint32_t OFCFGR4;       /*!< ADC offset configuration register 4,                   Address offset: 0x5C */
+  __IO uint32_t OFR1;          /*!< ADC offset register 1,                                 Address offset: 0x60 */
+  __IO uint32_t OFR2;          /*!< ADC offset register 2,                                 Address offset: 0x64 */
+  __IO uint32_t OFR3;          /*!< ADC offset register 3,                                 Address offset: 0x68 */
+  __IO uint32_t OFR4;          /*!< ADC offset register 4,                                 Address offset: 0x6C */
+  __IO uint32_t GCOMP;         /*!< ADC gain compensation register,                        Address offset: 0x70 */
+  uint32_t      RESERVED3[3];  /*!< Reserved,                                              Address offset: 0x074-0x07C */
+  __IO uint32_t JDR1;          /*!< ADC injected data register 1,                          Address offset: 0x80 */
+  __IO uint32_t JDR2;          /*!< ADC injected data register 2,                          Address offset: 0x84 */
+  __IO uint32_t JDR3;          /*!< ADC injected data register 3,                          Address offset: 0x88 */
+  __IO uint32_t JDR4;          /*!< ADC injected data register 4,                          Address offset: 0x8C */
+  uint32_t      RESERVED4[4];  /*!< Reserved,                                              Address offset: 0x090-0x09C */
+  __IO uint32_t AWD2CR;        /*!< ADC analog watchdog 2 configuration register,          Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;        /*!< ADC analog watchdog 3 configuration register,          Address offset: 0xA4 */
+  __IO uint32_t AWD1LTR;       /*!< ADC analog watchdog 1 low threshold register,          Address offset: 0xA8 */
+  __IO uint32_t AWD1HTR;       /*!< ADC analog watchdog 1 high threshold register,         Address offset: 0xAC */
+  __IO uint32_t AWD2LTR;       /*!< ADC analog watchdog 2 low threshold register,          Address offset: 0xB0 */
+  __IO uint32_t AWD2HTR;       /*!< ADC analog watchdog 2 high threshold register,         Address offset: 0xB4 */
+  __IO uint32_t AWD3LTR;       /*!< ADC analog watchdog 3 low threshold register,          Address offset: 0xB8 */
+  __IO uint32_t AWD3HTR;       /*!< ADC analog watchdog 3 high threshold register,         Address offset: 0xBC */
+  __IO uint32_t DIFSEL;        /*!< ADC differential mode selection register,              Address offset: 0xC0 */
+  __IO uint32_t CALFACT;       /*!< ADC calibration factors,                               Address offset: 0xC4 */
+  uint32_t      RESERVED5[2];  /*!< Reserved,                                              Address offset: 0x0C8-0x0CC */
+  __IO uint32_t OR;            /*!< ADC option register,                                   Address offset: 0xD0 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;           /*!< ADC common status register,                            Address offset: 0x300 */
+  uint32_t RESERVED;           /*!< Reserved,                                              Address offset: 0x304 */
+  __IO uint32_t CCR;           /*!< ADC common control register,                           Address offset: 0x308 */
+  __IO uint32_t CDR;           /*!< ADC common regular data register for dual mode,        Address offset: 0x30C */
+  __IO uint32_t CDR2;          /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Boot and Security
+  */
+
+typedef struct
+{
+  __IO uint32_t FVRw[384];       /*!< BSEC fuse word (0-383) value register,       Address offset: 0x000-0x5FC */
+       uint32_t RESERVED0[128];  /*!< Reserved,                                    Address offset: 0x600-0x7FC */
+  __IO uint32_t SPLOCKx[12];     /*!< BSEC sticky program lock register (0-11),    Address offset: 0x800-0x82C */
+       uint32_t RESERVED1[4];    /*!< Reserved,                                    Address offset: 0x830-0x83C */
+  __IO uint32_t SWLOCKx[12];     /*!< BSEC sticky write lock register (0-11),      Address offset: 0x840-0x86C */
+       uint32_t RESERVED2[4];    /*!< Reserved,                                    Address offset: 0x870-0x87C */
+  __IO uint32_t SRLOCKx[12];     /*!< BSEC sticky reload lock register (0-11),     Address offset: 0x880-0x8AC */
+       uint32_t RESERVED3[4];    /*!< Reserved,                                    Address offset: 0x8B0-0x8BC */
+  __IO uint32_t OTPVLDRx[12];    /*!< BSEC OTP valid register (0-11),              Address offset: 0x8C0-0x8EC */
+       uint32_t RESERVED4[20];   /*!< Reserved,                                    Address offset: 0x8F0-0x93C */
+  __IO uint32_t SFSRx[12];       /*!< BSEC shadowed fuses status register (0-11),  Address offset: 0x940-0x96C */
+       uint32_t RESERVED5[165];  /*!< Reserved,                                    Address offset: 0x970-0xC00 */
+  __IO uint32_t OTPCR;           /*!< BSEC OTP control register,                   Address offset: 0xC04 */
+  __IO uint32_t WDR;             /*!< BSEC write data register,                    Address offset: 0xC08 */
+       uint32_t RESERVED6[125];  /*!< Reserved,                                    Address offset: 0xC0C-0xDFC */
+  __IO uint32_t SCRATCHRx[4];    /*!< BSEC scratch register (0-3),                 Address offset: 0xE00-0xE0C */
+  __IO uint32_t LOCKR;           /*!< BSEC lock register,                          Address offset: 0xE10 */
+  __IO uint32_t JTAGINR;         /*!< BSEC JTAG input register,                    Address offset: 0xE14 */
+  __IO uint32_t JTAGOUTR;        /*!< BSEC JTAG output register,                   Address offset: 0xE18 */
+       uint32_t RESERVED7[2];    /*!< Reserved,                                    Address offset: 0xE1C-0xE20 */
+  __IO uint32_t UNMAPR;          /*!< BSEC unmap register,                         Address offset: 0xE24 */
+       uint32_t RESERVED8[6];    /*!< Reserved,                                    Address offset: 0xE28-0xE3C */
+  __IO uint32_t SR;              /*!< BSEC status register,                        Address offset: 0xE40 */
+  __IO uint32_t OTPSR;           /*!< BSEC OTP status register,                    Address offset: 0xE44 */
+       uint32_t RESERVED9[14];   /*!< Reserved,                                    Address offset: 0xE48-0xE7C */
+  __IO uint32_t EPOCHRx[2];      /*!< BSEC epoch register (0-1),                   Address offset: 0xE80-0xE84 */
+  __IO uint32_t EPOCHSELR;       /*!< BSEC epoch select register,                  Address offset: 0xE88 */
+  __IO uint32_t DBGCR;           /*!< BSEC debug control register,                 Address offset: 0xE8C */
+  __IO uint32_t AP_UNLOCK;       /*!< BSEC AP unlock,                              Address offset: 0xE90 */
+  __IO uint32_t HDPLSR;          /*!< BSEC hide protection level status register,  Address offset: 0xE94 */
+  __IO uint32_t HDPLCR;          /*!< BSEC hide protection level control register, Address offset: 0xE98 */
+  __IO uint32_t NEXTLR;          /*!< BSEC next hide protection level register,    Address offset: 0xE9C */
+       uint32_t RESERVED10[40];  /*!< Reserved,                                    Address offset: 0xEA0-0xF3C */
+  __IO uint32_t WOSCRx[8];       /*!< BSEC write once scratch register (0-7),      Address offset: 0xF40-0xF5C */
+       uint32_t RESERVED11[34];  /*!< Reserved,                                    Address offset: 0xF60-0xFE4 */
+  __IO uint32_t HRCR;            /*!< BSEC hot reset count register,               Address offset: 0xFE8 */
+  __IO uint32_t WRCR;            /*!< BSEC warm reset count register,              Address offset: 0xFEC */
+} BSEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+typedef struct
+{
+  __IO uint32_t DR;            /*!< CRC Data register,                              Address offset: 0x00 */
+  __IO uint32_t IDR;           /*!< CRC Independent data register,                  Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< CRC Control register,                           Address offset: 0x08 */
+       uint32_t RESERVED1;     /*!< Reserved,                                                       0x0C */
+  __IO uint32_t INIT;          /*!< Initial CRC value register,                     Address offset: 0x10 */
+  __IO uint32_t POL;           /*!< CRC polynomial register,                        Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/*
+ * @brief  (CSI)
+ */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< CSI-2 Host control register                           Address offset: 0x0000 */
+  __IO uint32_t PCR;              /*!< CSI-2 Host DPHY_RX control register                   Address offset: 0x0004 */
+       uint32_t RESERVED0[2];     /*!< Reserved                                              Address offset: 0x0008-0x000C */
+  __IO uint32_t VC0CFGR1;         /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */
+  __IO uint32_t VC0CFGR2;         /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */
+  __IO uint32_t VC0CFGR3;         /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */
+  __IO uint32_t VC0CFGR4;         /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */
+  __IO uint32_t VC1CFGR1;         /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */
+  __IO uint32_t VC1CFGR2;         /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */
+  __IO uint32_t VC1CFGR3;         /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */
+  __IO uint32_t VC1CFGR4;         /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */
+  __IO uint32_t VC2CFGR1;         /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */
+  __IO uint32_t VC2CFGR2;         /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */
+  __IO uint32_t VC2CFGR3;         /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */
+  __IO uint32_t VC2CFGR4;         /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */
+  __IO uint32_t VC3CFGR1;         /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */
+  __IO uint32_t VC3CFGR2;         /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */
+  __IO uint32_t VC3CFGR3;         /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */
+  __IO uint32_t VC3CFGR4;         /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */
+  __IO uint32_t LB0CFGR;          /*!< CSI-2 Host line byte 0 configuration register         Address offset: 0x0050 */
+  __IO uint32_t LB1CFGR;          /*!< CSI-2 Host line byte 1 configuration register         Address offset: 0x0054 */
+  __IO uint32_t LB2CFGR;          /*!< CSI-2 Host line byte 2 configuration register         Address offset: 0x0058 */
+  __IO uint32_t LB3CFGR;          /*!< CSI-2 Host line byte 3 configuration register         Address offset: 0x005C */
+  __IO uint32_t TIM0CFGR;         /*!< CSI-2 Host timer 0 configuration register             Address offset: 0x0060 */
+  __IO uint32_t TIM1CFGR;         /*!< CSI-2 Host timer 1 configuration register             Address offset: 0x0064 */
+  __IO uint32_t TIM2CFGR;         /*!< CSI-2 Host timer 2 configuration register             Address offset: 0x0068 */
+  __IO uint32_t TIM3CFGR;         /*!< CSI-2 Host timer 3 configuration register             Address offset: 0x006C */
+  __IO uint32_t LMCFGR;           /*!< CSI-2 Host lane merger configuration register         Address offset: 0x0070 */
+  __IO uint32_t PRGITR;           /*!< CSI-2 Host program interrupt register                 Address offset: 0x0074 */
+  __IO uint32_t WDR;              /*!< CSI-2 Host watchdog register                          Address offset: 0x0078 */
+       uint32_t RESERVED1;        /*!< Reserved                                              Address offset: 0x007C */
+  __IO uint32_t IER0;             /*!< CSI-2 Host Interrupt enable register 0                Address offset: 0x0080 */
+  __IO uint32_t IER1;             /*!< CSI-2 Host Interrupt enable register 1                Address offset: 0x0084 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                              Address offset: 0x0088-0x008C */
+  __IO uint32_t SR0;              /*!< CSI-2 Host status register 0                          Address offset: 0x0090 */
+  __IO uint32_t SR1;              /*!< CSI-2 Host status register 1                          Address offset: 0x0094 */
+       uint32_t RESERVED3[26];    /*!< Reserved                                              Address offset: 0x0098-0x00FC */
+  __IO uint32_t FCR0;             /*!< CSI-2 Host Flag clear register 0                      Address offset: 0x0100 */
+  __IO uint32_t FCR1;             /*!< CSI-2 Host Flag clear register 1                      Address offset: 0x0104 */
+       uint32_t RESERVED4[2];     /*!< Reserved                                              Address offset: 0x0108-0x010C */
+  __IO uint32_t SPDFR;            /*!< CSI-2 Host short packet data field register           Address offset: 0x0110 */
+  __IO uint32_t ERR1;             /*!< CSI-2 Host error register 1                           Address offset: 0x0114 */
+  __IO uint32_t ERR2;             /*!< CSI-2 Host error register 2                           Address offset: 0x0118 */
+       uint32_t RESERVED5[953];   /*!< Reserved                                              Address offset: 0x011C-0x0FFC */
+  __IO uint32_t PRCR;             /*!< CSI PHY reset control register                        Address offset: 0x1000 */
+  __IO uint32_t PMCR;             /*!< CSI PHY mode control register                         Address offset: 0x1004 */
+  __IO uint32_t PFCR;             /*!< CSI PHY frequency control register                    Address offset: 0x1008 */
+       uint32_t RESERVED6;        /*!< Reserved                                              Address offset: 0x100C */
+  __IO uint32_t PTCR0;            /*!< CSI PHY test control register 0                       Address offset: 0x1010 */
+  __IO uint32_t PTCR1;            /*!< CSI PHY test control register 1                       Address offset: 0x1014 */
+  __IO uint32_t PTSR;             /*!< CSI PHY test status register                          Address offset: 0x1018 */
+       uint32_t RESERVED7[1017];  /*!< Reserved                                              Address offset: 0x101C-0x1FFC */
+} CSI_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                            Address offset: 0x00  */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,              Address offset: 0x04  */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t APB1LFZ1;      /*!< Debug MCU APB1LFZ1 freeze register,            Address offset: 0x10  */
+  __IO uint32_t APB1HFZ1;      /*!< Debug MCU APB1HFZ1 freeze register,            Address offset: 0x14  */
+  __IO uint32_t APB2FZ1;       /*!< Debug MCU APB2FZ1 freeze register,             Address offset: 0x18  */
+  __IO uint32_t APB4FZ1;       /*!< Debug MCU APB4FZ1 freeze register,             Address offset: 0x1C  */
+  __IO uint32_t APB5FZ1;       /*!< Debug MCU APB5FZ1 freeze register,             Address offset: 0x20  */
+  __IO uint32_t AHB1FZ1;       /*!< Debug MCU AHB1FZ1 freeze register,             Address offset: 0x24  */
+  __IO uint32_t AHB5FZ1;       /*!< Debug MCU AHB5FZ1 freeze register,             Address offset: 0x28  */
+  uint32_t RESERVED2[52];      /*!< Reserved,                                  Address offset: 0x2C-0xF8 */
+  __IO uint32_t SR;            /*!< Debug MCU status register,                     Address offset: 0xFC  */
+  __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register,        Address offset: 0x100 */
+  __IO uint32_t DBG_AUTH_DEV;  /*!< Debug MCU authentication device register,      Address offset: 0x104 */
+  __IO uint32_t DBG_AUTH_ACK;  /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */
+} DBGMCU_TypeDef;
+
+/**
+  * @brief DCMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+#define DCMIPP_NUM_OF_PIPES 0x03U
+
+typedef struct
+{
+  uint32_t PxRIxCR1;      /*! DCMIPP Pipex ROIx configuration register 1  Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2)  */
+  uint32_t PxRIxCR2;      /*! DCMIPP Pipex ROIx configuration register 2  Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2)  */
+} DCMIPP_Region_TypeDef;
+
+/*
+ * @brief Digital camera interface pixel pipeline DCMIPP
+ */
+typedef struct
+{
+  __IO uint32_t IPGR1;           /*!< DCMIPP IPPLUG global register 1                                    Address offset: 0x000 */
+  __IO uint32_t IPGR2;           /*!< DCMIPP IPPLUG global register 2                                    Address offset: 0x004 */
+  __IO uint32_t IPGR3;           /*!< DCMIPP IPPLUG global register 3                                    Address offset: 0x008 */
+       uint32_t RESERVED0[4];    /*!< Reserved                                                           Address offset: 0x00C-0x018 */
+  __IO uint32_t IPGR8;           /*!< DCMIPP IPPLUG identification register                              Address offset: 0x01C */
+  __IO uint32_t IPC1R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */
+       uint32_t RESERVED1;       /*!< Reserved                                                           Address offset: 0x02C */
+  __IO uint32_t IPC2R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x030 */
+  __IO uint32_t IPC2R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x034 */
+  __IO uint32_t IPC2R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x038 */
+       uint32_t RESERVED2;       /*!< Reserved                                                           Address offset: 0x03C */
+  __IO uint32_t IPC3R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x040 */
+  __IO uint32_t IPC3R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x044 */
+  __IO uint32_t IPC3R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x048 */
+       uint32_t RESERVED3;       /*!< Reserved                                                           Address offset: 0x04C */
+  __IO uint32_t IPC4R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x050 */
+  __IO uint32_t IPC4R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x054 */
+  __IO uint32_t IPC4R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x058 */
+       uint32_t RESERVED4;       /*!< Reserved                                                           Address offset: 0x05C */
+  __IO uint32_t IPC5R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x060 */
+  __IO uint32_t IPC5R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x064 */
+  __IO uint32_t IPC5R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x068 */
+       uint32_t RESERVED5[38];   /*!< Reserved                                                           Address offset: 0x06C-0x100 */
+  __IO uint32_t PRCR;            /*!< DCMIPP parallel interface control register                         Address offset: 0x104 */
+  __IO uint32_t PRESCR;          /*!< DCMIPP parallel interface embedded synchronization code register   Address offset: 0x108 */
+  __IO uint32_t PRESUR;          /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */
+       uint32_t RESERVED6[57];   /*!< Reserved                                                           Address offset: 0x110-0x1F0 */
+  __IO uint32_t PRIER;           /*!< DCMIPP parallel interface interrupt enable register                Address offset: 0x1F4 */
+  __IO uint32_t PRSR;            /*!< DCMIPP parallel interface status register                          Address offset: 0x1F8 */
+  __IO uint32_t PRFCR;           /*!< DCMIPP parallel interface interrupt clear register                 Address offset: 0x1FC */
+       uint32_t RESERVED7;       /*!< Reserved                                                           Address offset: 0x200 */
+  __IO uint32_t CMCR;            /*!< DCMIPP common configuration register                               Address offset: 0x204 */
+  __IO uint32_t CMFRCR;          /*!< DCMIPP common frame counter register                               Address offset: 0x208 */
+       uint32_t RESERVED8[121];  /*!< Reserved                                                           Address offset: 0x20C-0x3EC */
+  __IO uint32_t CMIER;           /*!< DCMIPP common interrupt enable register                            Address offset: 0x3F0 */
+  __IO uint32_t CMSR1;           /*!< DCMIPP common status register 1                                    Address offset: 0x3F4 */
+  __IO uint32_t CMSR2;           /*!< DCMIPP common status register 2                                    Address offset: 0x3F8 */
+  __IO uint32_t CMFCR;           /*!< DCMIPP common interrupt clear register                             Address offset: 0x3FC */
+       uint32_t RESERVED9;            /*!< Reserved                                                      Address offset: 0x400 */
+  __IO uint32_t P0FSCR;          /*!< DCMIPP Pipe0 flow selection configuration register                 Address offset: 0x404 */
+       uint32_t RESERVED10[62];  /*!< Reserved                                                           Address offset: 0x408-0x4FC */
+  __IO uint32_t P0FCTCR;         /*!< DCMIPP Pipe0 flow control configuration register                   Address offset: 0x500 */
+  __IO uint32_t P0SCSTR;         /*!< DCMIPP Pipe0 stat/crop start register                              Address offset: 0x504 */
+  __IO uint32_t P0SCSZR;         /*!< DCMIPP Pipe0 stat/crop size register                               Address offset: 0x508 */
+       uint32_t RESERVED11[41];  /*!< Reserved                                                           Address offset: 0x50C-0x5AC */
+  __IO uint32_t P0DCCNTR;        /*!< DCMIPP Pipe0 dump counter register                                 Address offset: 0x5B0 */
+  __IO uint32_t P0DCLMTR;        /*!< DCMIPP Pipe0 dump limit register                                   Address offset: 0x5B4 */
+       uint32_t RESERVED12[2];   /*!< Reserved                                                           Address offset: 0x5B8-0x5BC */
+  __IO uint32_t P0PPCR;          /*!< DCMIPP Pipe0 pixel packer configuration register                   Address offset: 0x5C0 */
+  __IO uint32_t P0PPM0AR1;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1               Address offset: 0x5C4 */
+  __IO uint32_t P0PPM0AR2;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2               Address offset: 0x5C8 */
+       uint32_t RESERVED13;      /*!< Reserved                                                           Address offset: 0x5C8-0x5CC */
+  __IO uint32_t P0STM0AR;        /*!< DCMIPP Pipe0 status Memory0 address register                       Address offset: 0x5D0 */
+       uint32_t RESERVED14[8];   /*!< Reserved                                                           Address offset: 0x5D4-0x5F0 */
+  __IO uint32_t P0IER;           /*!< DCMIPP Pipe0 interrupt enable register                             Address offset: 0x5F4 */
+  __IO uint32_t P0SR;            /*!< DCMIPP Pipe0 status register                                       Address offset: 0x5F8 */
+  __IO uint32_t P0FCR;           /*!< DCMIPP Pipe0 interrupt clear register                              Address offset: 0x5FC */
+       uint32_t RESERVED15;      /*!< Reserved                                                           Address offset: 0x600 */
+  __IO uint32_t P0CFSCR;         /*!< DCMIPP Pipe0 current flow selection configuration register         Address offset: 0x604 */
+       uint32_t RESERVED17[62];  /*!< Reserved                                                           Address offset: 0x608-0x6FC */
+  __IO uint32_t P0CFCTCR;        /*!< DCMIPP Pipe0 current flow control configuration register           Address offset: 0x700 */
+  __IO uint32_t P0CSCSTR;        /*!< DCMIPP Pipe0 current stat/crop start register                      Address offset: 0x704 */
+  __IO uint32_t P0CSCSZR;        /*!< DCMIPP Pipe0 current stat/crop size register                       Address offset: 0x708 */
+       uint32_t RESERVED18[45];  /*!< Reserved                                                           Address offset: 0x70C-0x7BC */
+  __IO uint32_t P0CPPCR;         /*!< DCMIPP Pipe0 current pixel packer configuration register           Address offset: 0x7C0 */
+  __IO uint32_t P0CPPM0AR1;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1       Address offset: 0x7C4 */
+  __IO uint32_t P0CPPM0AR2;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2       Address offset: */
+       uint32_t RESERVED19[14];  /*!< Reserved                                                           Address offset: 0x7C8-0x7FC */
+  __IO uint32_t P1FSCR;          /*!< DCMIPP Pipe1 flow selection configuration register                 Address offset: 0x804 */
+       uint32_t RESERVED20[6];   /*!< Reserved                                                           Address offset: 0x808-0x81C */
+  __IO uint32_t P1SRCR;          /*!< DCMIPP Pipe1 stat removal configuration register                   Address offset: 0x820 */
+  __IO uint32_t P1BPRCR;         /*!< DCMIPP Pipe1 bad pixel removal control register                    Address offset: 0x824 */
+  __IO uint32_t P1BPRSR;         /*!< DCMIPP Pipe1 bad pixel removal status register                     Address offset: 0x828 */
+       uint32_t RESERVED21;      /*!< Reserved                                                           Address offset: 0x82C */
+  __IO uint32_t P1DECR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x830 */
+       uint32_t RESERVED22[3];   /*!< Reserved                                                           Address offset: 0x834-0x83C */
+  __IO uint32_t P1BLCCR;         /*!< DCMIPP Pipe1 black level calibration control register              Address offset: 0x840 */
+  __IO uint32_t P1EXCR1;         /*!< DCMIPP Pipe1 exposure control register 1                           Address offset: 0x844 */
+  __IO uint32_t P1EXCR2;         /*!< DCMIPP Pipe1 exposure control register 2                           Address offset: 0x848 */
+       uint32_t RESERVED23;      /*!< Reserved                                                           Address offset: 0x84C */
+  __IO uint32_t P1ST1CR;         /*!< DCMIPP Pipe1 statistics 1 control register                         Address offset: 0x850 */
+  __IO uint32_t P1ST2CR;         /*!< DCMIPP Pipe1 statistics 2 control register                         Address offset: 0x854 */
+  __IO uint32_t P1ST3CR;         /*!< DCMIPP Pipe1 statistics 3 control register                         Address offset: 0x858 */
+  __IO uint32_t P1STSTR;         /*!< DCMIPP Pipe1 statistics window start register                      Address offset: 0x85C */
+  __IO uint32_t P1STSZR;         /*!< DCMIPP Pipe1 statistics window size register                       Address offset: 0x860 */
+  __IO uint32_t P1ST1SR;         /*!< DCMIPP Pipe1 statistics 1 status register                          Address offset: 0x864 */
+  __IO uint32_t P1ST2SR;         /*!< DCMIPP Pipe1 statistics 2 status register                          Address offset: 0x868 */
+  __IO uint32_t P1ST3SR;         /*!< DCMIPP Pipe1 statistics 3 status register                          Address offset: 0x86C */
+  __IO uint32_t P1DMCR;          /*!< DCMIPP Pipe1 demosaicing configuration register                    Address offset: 0x870 */
+       uint32_t RESERVED24[3];   /*!< Reserved                                                           Address offset: 0x874-0x87C */
+  __IO uint32_t P1CCCR;          /*!< DCMIPP Pipe1 ColorConv configuration register                      Address offset: 0x880 */
+  __IO uint32_t P1CCRR1;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 1                  Address offset: 0x884 */
+  __IO uint32_t P1CCRR2;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 2                  Address offset: 0x888 */
+  __IO uint32_t P1CCGR1;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 1                Address offset: 0x88C */
+  __IO uint32_t P1CCGR2;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 2                Address offset: 0x890 */
+  __IO uint32_t P1CCBR1;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1                 Address offset: 0x894 */
+  __IO uint32_t P1CCBR2;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2                 Address offset: 0x898 */
+       uint32_t RESERVED25;      /*!< Reserved                                                           Address offset: 0x89C */
+  __IO uint32_t P1CTCR1;         /*!< DCMIPP Pipe1 contrast control register 1                           Address offset: 0x8A0 */
+  __IO uint32_t P1CTCR2;         /*!< DCMIPP Pipe1 contrast control register 2                           Address offset: 0x8A4 */
+  __IO uint32_t P1CTCR3;         /*!< DCMIPP Pipe1 contrast control register 3                           Address offset: 0x8A8 */
+       uint32_t RESERVED26[21];  /*!< Reserved                                                           Address offset: 0x8AC-0x8FC */
+  __IO uint32_t P1FCTCR;         /*!< DCMIPP Pipe1 flow control configuration register                   Address offset: 0x900 */
+  __IO uint32_t P1CRSTR;         /*!< DCMIPP Pipe1 crop window start register                            Address offset: 0x904 */
+  __IO uint32_t P1CRSZR;         /*!< DCMIPP Pipe1 crop window size register                             Address offset: 0x908 */
+  __IO uint32_t P1DCCR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x90C */
+  __IO uint32_t P1DSCR;          /*!< DCMIPP Pipe1 downsize configuration register                       Address offset: 0x910 */
+  __IO uint32_t P1DSRTIOR;       /*!< DCMIPP Pipe1 downsize ratio register                               Address offset: 0x914 */
+  __IO uint32_t P1DSSZR;         /*!< DCMIPP Pipe1 downsize destination size register                    Address offset: 0x918 */
+       uint32_t RESERVED28;      /*!< Reserved                                                           Address offset:  */
+  __IO uint32_t P1CMRICR;        /*!< DCMIPP Pipe1 common ROI configuration register                     Address offset: 0x920 */
+  __IO uint32_t P1RIxCR1;        /*!< DCMIPP Pipe1 ROIx configuration register 1                         Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P1RIxCR2;        /*!< DCMIPP Pipe1 ROIx configuration register 2                         Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED29[17];      /*!< Reserved                                                       Address offset:  */
+  __IO uint32_t P1GMCR;          /*!< DCMIPP Pipe1 gamma configuration register                          Address offset: 0x970 */
+       uint32_t RESERVED30[3];   /*!< Reserved                                                           Address offset: 0x974-0x97C */
+  __IO uint32_t P1YUVCR;         /*!< DCMIPP Pipe1 YUVConv configuration register                        Address offset: 0x980 */
+  __IO uint32_t P1YUVRR1;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 1                    Address offset: 0x984 */
+  __IO uint32_t P1YUVRR2;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 2                    Address offset: 0x988 */
+  __IO uint32_t P1YUVGR1;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 1                  Address offset: 0x98C */
+  __IO uint32_t P1YUVGR2;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 2                  Address offset: 0x990 */
+  __IO uint32_t P1YUVBR1;        /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1                   Address offset: 0x994 */
+  __IO uint32_t P1YUVBR2;        /*!< DCMIPP Pipe1 YUV blue coefficient register 2                       Address offset: 0x998 */
+       uint32_t RESERVED31[9];   /*!< Reserved                                                           Address offset: 0x99C-0x9BC */
+  __IO uint32_t P1PPCR;          /*!< DCMIPP Pipe1 pixel packer configuration register                   Address offset: 0x9C0 */
+  __IO uint32_t P1PPM0AR1;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1               Address offset: 0x9C4 */
+  __IO uint32_t P1PPM0AR2;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2               Address offset: 0x9C8 */
+  __IO uint32_t P1PPM0PR;        /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register                   Address offset: 0x9CC */
+  __IO uint32_t P1STM0AR;        /*!< DCMIPP Pipe1 status Memory0 address register                       Address offset: 0x9D0 */
+  __IO uint32_t P1PPM1AR1;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1               Address offset: 0x9D4 */
+  __IO uint32_t P1PPM1AR2;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2               Address offset: 0x9D8 */
+  __IO uint32_t P1PPM1PR;        /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register                   Address offset: 0x9DC */
+  __IO uint32_t P1STM1AR;        /*!< DCMIPP Pipe1 status Memory1 address register                       Address offset: 0x9E0 */
+  __IO uint32_t P1PPM2AR1;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 1               Address offset: 0x9E4 */
+  __IO uint32_t P1PPM2AR2;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 2               Address offset: 0x9E8 */
+  __IO uint32_t RESERVED34;      /*!< Reserved                                                           Address offset: 0x9EC */
+  __IO uint32_t P1STM2AR;        /*!< DCMIPP Pipe1 status Memory2 address register                       Address offset: 0x9F0 */
+  __IO uint32_t P1IER;           /*!< DCMIPP Pipe1 interrupt enable register                             Address offset: 0x9F4 */
+  __IO uint32_t P1SR;            /*!< DCMIPP Pipe1 status register                                       Address offset: 0x9F8 */
+  __IO uint32_t P1FCR;           /*!< DCMIPP Pipe1 interrupt clear register                              Address offset: 0x9FC */
+       uint32_t RESERVED35;      /*!< Reserved                                                           Address offset: 0xA00 */
+  __IO uint32_t P1CFSCR;         /*!< DCMIPP Pipe1 current flow selection configuration register         Address offset: 0xA04 */
+       uint32_t RESERVED36[7];   /*!< Reserved                                                           Address offset: 0xA08-0xA20 */
+  __IO uint32_t P1CBPRCR;        /*!< DCMIPP Pipe1 current bad pixel removal register                    Address offset: 0xA24 */
+       uint32_t RESERVED37[6];   /*!< Reserved                                                           Address offset: 0xA28-0xA3C */
+  __IO uint32_t P1CBLCCR;        /*!< DCMIPP Pipe1 current black level calibration control register      Address offset: 0xA40 */
+  __IO uint32_t P1CEXCR1;        /*!< DCMIPP Pipe1 current exposure control register 1                   Address offset: 0xA44 */
+  __IO uint32_t P1CEXCR2;        /*!< DCMIPP Pipe1 current exposure control register 2                   Address offset: 0xA48 */
+       uint32_t RESERVED38;      /*!< Reserved                                                           Address offset: 0xA4C */
+  __IO uint32_t P1CST1CR;        /*!< DCMIPP Pipe1 current statistics 1 control register                 Address offset: 0xA50 */
+  __IO uint32_t P1CST2CR;        /*!< DCMIPP Pipe1 current statistics 2 control register                 Address offset: 0xA54 */
+  __IO uint32_t P1CST3CR;        /*!< DCMIPP Pipe1 current statistics 3 control register                 Address offset: 0xA58 */
+  __IO uint32_t P1CSTSTR;        /*!< DCMIPP Pipe1 current statistics window start register              Address offset: 0xA5C */
+  __IO uint32_t P1CSTSZR;        /*!< DCMIPP Pipe1 current statistics window size register               Address offset: 0xA60 */
+       uint32_t RESERVED39[7];   /*!< Reserved                                                           Address offset: 0xA64-0xA7C */
+  __IO uint32_t P1CCCCR;         /*!< DCMIPP Pipe1 current ColorConv configuration register              Address offset: 0xA80 */
+  __IO uint32_t P1CCCRR1;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1          Address offset: 0xA84 */
+  __IO uint32_t P1CCCRR2;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2          Address offset: 0xA88 */
+  __IO uint32_t P1CCCGR1;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1        Address offset: 0xA8C */
+  __IO uint32_t P1CCCGR2;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2        Address offset: 0xA90 */
+  __IO uint32_t P1CCCBR1;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1         Address offset: 0xA94 */
+  __IO uint32_t P1CCCBR2;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2         Address offset: 0xA98 */
+       uint32_t RESERVED40;      /*!< Reserved                                                           Address offset: 0xA9C */
+  __IO uint32_t P1CCTCR1;        /*!< DCMIPP Pipe1 current contrast control register 1                   Address offset: 0xAA0 */
+  __IO uint32_t P1CCTCR2;        /*!< DCMIPP Pipe1 current contrast control register 2                   Address offset: 0xAA4 */
+  __IO uint32_t P1CCTCR3;        /*!< DCMIPP Pipe1 current contrast control register 3                   Address offset: 0xAA8 */
+       uint32_t RESERVED41[21];  /*!< Reserved                                                           Address offset: 0xAAC-0xAFC */
+  __IO uint32_t P1CFCTCR;        /*!< DCMIPP Pipe1 current flow control configuration register           Address offset: 0xB00 */
+  __IO uint32_t P1CCRSTR;        /*!< DCMIPP Pipe1 current crop window start register                    Address offset: 0xB04 */
+  __IO uint32_t P1CCRSZR;        /*!< DCMIPP Pipe1 current crop window size register                     Address offset: 0xB08 */
+  __IO uint32_t P1CDCCR;         /*!< DCMIPP Pipe1 current decimation register                           Address offset: 0xB0C */
+  __IO uint32_t P1CDSCR;         /*!< DCMIPP Pipe1 current downsize configuration register               Address offset: 0xB10 */
+  __IO uint32_t P1CDSRTIOR;      /*!< DCMIPP Pipe1 current downsize ratio register                       Address offset: 0xB14 */
+  __IO uint32_t P1CDSSZR;        /*!< DCMIPP Pipe1 current downsize destination size register            Address offset: 0xB18 */
+       uint32_t RESERVED43;      /*!< Reserved                                                           Address offset: 0xB1C */
+       uint32_t P1CCMRICR;       /*!< DCMIPP Pipe1 current common ROI configuration register             Address offset: 0xB20 */
+  __IO uint32_t P1CRIxCR1;       /*!< DCMIPP Pipe1 current ROIx configuration register 1                 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */
+  __IO uint32_t P1CRIxCR2;       /*!< DCMIPP Pipe1 current ROIx configuration register 2                 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */
+  uint32_t RESERVED44[37];       /*!< Reserved                                                           Address offset: 0xB64-0xBBC */
+  __IO uint32_t P1CPPCR;         /*!< DCMIPP Pipe1 current pixel packer configuration register           Address offset: 0xBC0 */
+  __IO uint32_t P1CPPM0AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC4 */
+  __IO uint32_t P1CPPM0AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC8 */
+  __IO uint32_t P1CPPM0PR;       /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register           Address offset: 0xBCC */
+       uint32_t RESERVED45;      /*!< Reserved                                                           Address offset: 0xBD0 */
+  __IO uint32_t P1CPPM1AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1       Address offset: 0xBD4 */
+  __IO uint32_t P1CPPM1AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2       Address offset: 0xBD8 */
+  __IO uint32_t P1CPPM1PR;       /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register           Address offset: 0xBDC */
+       uint32_t RESERVED47;      /*!< Reserved                                                           Address offset: 0xBE0 */
+  __IO uint32_t P1CPPM2AR1;      /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1       Address offset: 0xBE4 */
+  __IO uint32_t P1CPPM2AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2       Address offset: 0xBE8 */
+       uint32_t RESERVED48[6];   /*!< Reserved                                                           Address offset: 0xBE8-0xBFC */
+  __IO uint32_t P2FSCR;          /*!< DCMIPP Pipe2 flow selection configuration register                 Address offset: 0xC04 */
+       uint32_t RESERVED49[62];  /*!< Reserved                                                           Address offset: 0xC08-0xCFC */
+  __IO uint32_t P2FCTCR;         /*!< DCMIPP Pipe2 flow control configuration register                   Address offset: 0xD00 */
+  __IO uint32_t P2CRSTR;         /*!< DCMIPP Pipe2 crop window start register                            Address offset: 0xD04 */
+  __IO uint32_t P2CRSZR;         /*!< DCMIPP Pipe2 crop window size register                             Address offset: 0xD08 */
+  __IO uint32_t P2DCCR;          /*!< DCMIPP Pipe2 decimation register                                   Address offset: 0xD0C */
+  __IO uint32_t P2DSCR;          /*!< DCMIPP Pipe2 downsize configuration register                       Address offset: 0xD10 */
+  __IO uint32_t P2DSRTIOR;       /*!< DCMIPP Pipe2 downsize ratio register                               Address offset: 0xD14 */
+  __IO uint32_t P2DSSZR;         /*!< DCMIPP Pipe2 downsize destination size register                    Address offset: 0xD18 */
+       uint32_t RESERVED51;      /*!< Reserved                                                           Address offset:  0xD1C */
+  __IO uint32_t P2CMRICR;        /*!< DCMIPP Pipe2 common ROI configuration register                     Address offset:  0xD20 */
+  __IO uint32_t P2RIxCR1;        /*!< DCMIPP Pipe2 ROIx configuration register 1                         Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P2RIxCR2;        /*!< DCMIPP Pipe2 ROIx configuration register 2                         Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED53[17];  /*!< Reserved                                                           Address offset: */
+  __IO uint32_t P2GMCR;          /*!< DCMIPP Pipe2 gamma configuration register                          Address offset: 0xD70 */
+       uint32_t RESERVED54[19];  /*!< Reserved                                                           Address offset: 0xD74-0xDBC */
+  __IO uint32_t P2PPCR;          /*!< DCMIPP Pipe2 pixel packer configuration register                   Address offset: 0xDC0 */
+  __IO uint32_t P2PPM0AR1;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1               Address offset: 0xDC4 */
+  __IO uint32_t P2PPM0AR2;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2               Address offset: 0xDC8 */
+  __IO uint32_t P2PPM0PR;        /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register                   Address offset: 0xDCC */
+  __IO uint32_t P2STM0AR;        /*!< DCMIPP Pipe2 status Memory0 address register                       Address offset: 0xDD0 */
+       uint32_t RESERVED55[8];   /*!< Reserved                                                           Address offset: 0xDD4-0xDF0 */
+  __IO uint32_t P2IER;           /*!< DCMIPP Pipe2 interrupt enable register                             Address offset: 0xDF4 */
+  __IO uint32_t P2SR;            /*!< DCMIPP Pipe2 status register                                       Address offset: 0xDF8 */
+  __IO uint32_t P2FCR;           /*!< DCMIPP Pipe2 interrupt clear register                              Address offset: 0xDFC */
+       uint32_t RESERVED56;      /*!< Reserved                                                           Address offset: 0xE00 */
+  __IO uint32_t P2CFSCR;         /*!< DCMIPP Pipe2 current flow selection configuration register         Address offset: 0xE04 */
+       uint32_t RESERVED57[62];  /*!< Reserved                                                           Address offset: 0xE08-0xEFC */
+  __IO uint32_t P2CFCTCR;        /*!< DCMIPP Pipe2 current flow control configuration register           Address offset: 0xF00 */
+  __IO uint32_t P2CCRSTR;        /*!< DCMIPP Pipe2 current crop window start register                    Address offset: 0xF04 */
+  __IO uint32_t P2CCRSZR;        /*!< DCMIPP Pipe2 current crop window size register                     Address offset: 0xF08 */
+  __IO uint32_t P2CDCCR;         /*!< DCMIPP Pipe2 current decimation register                           Address offset: 0xF0C */
+  __IO uint32_t P2CDSCR;         /*!< DCMIPP Pipe2 current downsize configuration register               Address offset: 0xF10 */
+  __IO uint32_t P2CDSRTIOR;      /*!< DCMIPP Pipe2 current downsize ratio register                       Address offset: 0xF14 */
+  __IO uint32_t P2CDSSZR;        /*!< DCMIPP Pipe2 current downsize destination size register            Address offset: 0xF18 */
+  __IO uint32_t RESERVED59[2];   /*!< Reserved                                                           Address offset: 0xF1C-0xF20 */
+  __IO uint32_t P2CRIxCR1;       /*!< Pipe2 current ROIx configuration register 1                        Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/
+  __IO uint32_t P2CRIxCR2;       /*!< Pipe2 current ROIx configuration register 2                        Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/
+       uint32_t RESERVED60[37];  /*!< Reserved                                                           Address offset: 0xF64-0xFBC */
+  __IO uint32_t P2CPPCR;         /*!< DCMIPP Pipe2 current pixel packer configuration register           Address offset: 0xFC0 */
+  __IO uint32_t P2CPPM0AR1;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1       Address offset: 0xFC4 */
+  __IO uint32_t P2CPPM0AR2;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2       Address offset: 0xFC8 */
+  __IO uint32_t P2CPPM0PR;       /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register           Address offset: 0xFCC */
+       uint32_t RESERVED61[7];   /*!< Reserved                                                           Address offset: 0xFD0-0xFE8 */
+  __IO uint32_t HWCFGR2;         /*!< DCMIPP hardware configuration register 2                           Address offset: 0xFEC */
+  __IO uint32_t HWCFGR1;         /*!< DCMIPP hardware configuration register 1                           Address offset: 0xFF0 */
+  __IO uint32_t VERR;            /*!< DCMIPP version register                                            Address offset: 0xFF4 */
+  __IO uint32_t IPIDR;           /*!< DCMIPP identification register                                     Address offset: 0xFF8 */
+  __IO uint32_t SIDR;            /*!< DCMIPP size identification register                                Address offset: 0xFFC */
+} DCMIPP_TypeDef;
+
+/**
+  * @ brief Delay Block
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< Delay Block Control Register,       Address offset: 0x00 */
+  __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t SECCFGR;      /*!< DMA secure configuration register,               Address offset: 0x00  */
+  __IO uint32_t PRIVCFGR;     /*!< DMA privileged configuration register,           Address offset: 0x04 */
+  __IO uint32_t RCFGLOCKR;    /*!< DMA configuration lock register,                 Address offset: 0x08 */
+  __IO uint32_t MISR;         /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
+  __IO uint32_t SMISR;        /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CLBAR;         /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
+  __IO uint32_t CCIDCFGR;      /*!< DMA channel x CID register,                      Address offset: 0x54 + (x * 0x80) */
+       uint32_t RESERVED1[1];  /*!< Reserved 1,                                      Address offset: 0x58 + (x * 0x80) */
+  __IO uint32_t CFCR;          /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
+  __IO uint32_t CSR;           /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
+  __IO uint32_t CCR;           /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
+       uint32_t RESERVED2[10]; /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C + (x * 0x80) */
+  __IO uint32_t CTR1;          /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
+  __IO uint32_t CTR2;          /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
+  __IO uint32_t CBR1;          /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
+  __IO uint32_t CSAR;          /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
+  __IO uint32_t CDAR;          /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
+  __IO uint32_t CTR3;          /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
+  __IO uint32_t CBR2;          /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
+       uint32_t RESERVED3[8];  /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8 + (x * 0x80) */
+  __IO uint32_t CLLR;          /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
+} DMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
+} DMA2D_TypeDef;
+
+/**
+  * @brief DTS Controller
+  */
+typedef struct
+{
+  uint32_t      RESERVED1[4];    /*!< Reserved,                                 Address offset: 0x00-0x0F */
+  __IO uint32_t PVTREG_LOCKR;    /*!< DTS PVT Register Lock Register,           Address offset: 0x10 */
+  __IO uint32_t PVTLOCK_SR;      /*!< DTS PVT Lock Status Register,             Address offset: 0x14 */
+  uint32_t      RESERVED2[2];    /*!< Reserved,                                 Address offset: 0x18-0x1F */
+  __IO uint32_t PVTTMR_CR;       /*!< DTS PVT Timer Control Register,           Address offset: 0x20 */
+  __IO uint32_t PVTTMR_SR;       /*!< DTS PVT Timer Status Register,            Address offset: 0x24 */
+  uint32_t      RESERVED3[6];    /*!< Reserved,                                 Address offset: 0x28-0x3F */
+  __IO uint32_t PVT_IER;         /*!< DTS PVT IRQ Enable Register,              Address offset: 0x40 */
+  uint32_t      RESERVED4[3];    /*!< Reserved,                                 Address offset: 0x44-0x4F */
+  __IO uint32_t PVTIRQTRMASKR;   /*!< DTS PVT IRQ Timer Mask Register,          Address offset: 0x50 */
+  __IO uint32_t TS_MR;           /*!< DTS PVT IRQ TS Mask Register,             Address offset: 0x54 */
+  uint32_t      RESERVED5[2];    /*!< Reserved,                                 Address offset: 0x58-0x5F */
+  __IO uint32_t PVTTR_SR;        /*!< DTS PVT IRQ Timer Status Register,        Address offset: 0x60 */
+  __IO uint32_t TS_ISR;          /*!< DTS PVT IRQ TS Status Register,           Address offset: 0x64 */
+  uint32_t      RESERVED6[2];    /*!< Reserved,                                 Address offset: 0x68-0x6F */
+  __IO uint32_t PVTTMRRAW_ISR;   /*!< DTS PVT IRQ Timer Raw Status Register,    Address offset: 0x70 */
+  __IO uint32_t TSRAW_ISR;       /*!< DTS PVT IRQ TS Raw Status Register,       Address offset: 0x74 */
+  uint32_t      RESERVED7[2];    /*!< Reserved,                                 Address offset: 0x78-0x7F */
+  __IO uint32_t TSCCLKSYNTHR;    /*!< DTS TSC Clock Synthesizer Register,       Address offset: 0x80 */
+  __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register,  Address offset: 0x84 */
+  __IO uint32_t TSCSDIF_SR;      /*!< DTS TSC SDIF Status Register,             Address offset: 0x88 */
+  __IO uint32_t TSCSDIF_CR;      /*!< DTS TSC SDIF Register,                    Address offset: 0x8C */
+  __IO uint32_t TSCSDIFHALTR;    /*!< DTS TSC SDIF Halt Register,               Address offset: 0x90 */
+  __IO uint32_t TSCSDIF_CFGR;    /*!< DTS TSC SDIF Control Register,            Address offset: 0x94 */
+  uint32_t      RESERVED8[2];    /*!< Reserved,                                 Address offset: 0x98-0x9F */
+  __IO uint32_t TSCSMPL_CR;      /*!< DTS TSC Sample Control Register,          Address offset: 0xA0 */
+  __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register,            Address offset: 0xA4 */
+  __IO uint32_t TSCSMPLCNTR;     /*!< DTS TSC Sample Count Register,            Address offset: 0xA8 */
+} DTS_TypeDef;
+
+/**
+  * @brief DTS Sensor Controller
+  */
+typedef struct
+{
+  __IO uint32_t TS_IER;          /*!< DTS TSx IRQ Enable Register,              Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ISR;          /*!< DTS TSx IRQ Status Register,              Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ICR;          /*!< DTS TSx IRQ Clear Register,               Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSIRQTESTR;      /*!< DTS TSx IRQ Test Register,                Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFRDATAR;    /*!< DTS TSx SDIF RDATA Register,              Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDONER;     /*!< DTS TSx SDIF Done Register,               Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDATAR;     /*!< DTS TSx SDIF Data Register,               Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */
+  uint32_t      RESERVED1[1];    /*!< Reserved,                                 Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMA_CFGR;   /*!< DTS TSx Alarm A Configuration Register,   Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMB_CFGR;   /*!< DTS TSx Alarm B Configuration Register,   Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHLSAMPLER;     /*!< DTS TSx High/Low Sample Register,         Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHILORESETR;    /*!< DTS TSx High/Low Reset Register,          Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */
+} DTS_SensorTypeDef;
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;               /*!< Operating mode configuration register,                        Address offset: 0x00 */
+  __IO uint32_t MACECR;              /*!< Extended operating mode configuration register,               Address offset: 0x04 */
+  __IO uint32_t MACPFR;              /*!< Packet filtering control register             ,               Address offset: 0x08 */
+  __IO uint32_t MACWTR;              /*!< Watchdog timeout register,                                    Address offset: 0x0C */
+  __IO uint32_t MACHT0R;             /*!< Hash Table 0 register,                                        Address offset: 0x10 */
+  __IO uint32_t MACHT1R;             /*!< Hash Table 1 register,                                        Address offset: 0x14 */
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTCR;             /*!< VLAN tag Control register,                                    Address offset: 0x50 */
+  __IO uint32_t MACVTDR;             /*!< VLAN tag data register,                                       Address offset: 0x54 */
+  __IO uint32_t MACVHTR;             /*!< VLAN Hash table register,                                     Address offset: 0x58 */
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVIR;              /*!< VLAN inclusion register,                                      Address offset: 0x60 */
+  __IO uint32_t MACIVIR;             /*!< Inner VLAN inclusion register,                                Address offset: 0x64 */
+  uint32_t      RESERVED3[2];
+  __IO uint32_t MACQ0TXFCR;          /*!< Tx Queue 0 flow control register,                             Address offset: 0x70 */
+  uint32_t      RESERVED4[7];
+  __IO uint32_t MACRXFCR;            /*!< Rx flow control register,                                     Address offset: 0x90 */
+  __IO uint32_t MACRXQCR;            /*!< Rx Queue control register,                                    Address offset: 0x94 */
+  uint32_t      RESERVED5[2];
+  __IO uint32_t MACRXQC0R;           /*!< Rx queue control 0 register,                                  Address offset: 0xA0 */
+  __IO uint32_t MACRXQC1R;           /*!< Rx queue control 1 register,                                  Address offset: 0xA4 */
+  __IO uint32_t MACRXQC2R;           /*!< Rx queue control 2 register,                                  Address offset: 0xA8 */
+  uint32_t      RESERVED6;
+  __IO uint32_t MACISR;              /*!< Interrupt status register,                                    Address offset: 0xB0 */
+  __IO uint32_t MACIER;              /*!< Interrupt enable register,                                    Address offset: 0xB4 */
+  __IO uint32_t MACRXTXSR;           /*!< Rx Tx status register,                                        Address offset: 0xB8 */
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;             /*!< PMT control status register,                                  Address offset: 0xC0 */
+  __IO uint32_t MACRWKPFR;           /*!< Remote wakeup packet filter register,                         Address offset: 0xC4 */
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;             /*!< LPI control and status register,                              Address offset: 0xD0 */
+  __IO uint32_t MACLTCR;             /*!< LPI timers control register,                                  Address offset: 0xD4 */
+  __IO uint32_t MACLETR;             /*!< LPI entry timer register,                                     Address offset: 0xD8 */
+  __IO uint32_t MAC1USTCR;           /*!< One-microsecond-tick counter register,                        Address offset: 0xDC */
+  uint32_t      RESERVED9[6];
+  __IO uint32_t MACPHYCSR;           /*!< PHYIF control status register,                                Address offset: 0xF8 */
+  uint32_t      RESERVED10[5];
+  __IO uint32_t MACVR;               /*!< Version register,                                             Address offset: 0x110 */
+  __IO uint32_t MACDR;               /*!< Debug register,                                               Address offset: 0x114 */
+  uint32_t      RESERVED11;
+  __IO uint32_t MACHWF0R;            /*!< HW feature 0 register,                                        Address offset: 0x11C */
+  __IO uint32_t MACHWF1R;            /*!< HW feature 1 register,                                        Address offset: 0x120 */
+  __IO uint32_t MACHWF2R;            /*!< HW feature 2 register,                                        Address offset: 0x124 */
+  __IO uint32_t MACHWF3R;            /*!< HW feature 3 register,                                        Address offset: 0x128 */
+  uint32_t      RESERVED12[53];
+  __IO uint32_t MACMDIOAR;           /*!< MDIO address register,                                        Address offset: 0x200 */
+  __IO uint32_t MACMDIODR;           /*!< MDIO data register,                                           Address offset: 0x204 */
+  uint32_t      RESERVED13[2];
+  __IO uint32_t MACARPAR;            /*!< ARP address register,                                         Address offset: 0x210 */
+  uint32_t      RESERVED14[7];
+  __IO uint32_t MACCSRSWCR;          /*!< CSR software control register,                                Address offset: 0x230 */
+  __IO uint32_t MACFPECSR;           /*!< FPE control and status register,                              Address offset: 0x234 */
+   uint32_t     RESERVED15[2];
+  __IO uint32_t MACPRSTIMR;          /*!< MAC presentation time register,                               Address offset: 0x0240 */
+  __IO uint32_t MACPRSTIMUR;         /*!< MAC presentation time update register,                        Address offset: 0x0244 */
+   uint32_t     RESERVED16[46];
+  __IO uint32_t MACA0HR;             /*!< MAC Address 0 high register,                                  Address offset: 0x0300 */
+  __IO uint32_t MACA0LR;             /*!< MAC Address 0 low register,                                   Address offset: 0x0304 */
+  __IO uint32_t MACA1HR;             /*!< MAC Address 1 high register,                                  Address offset: 0x0308 */
+  __IO uint32_t MACA1LR;             /*!< MAC Address 1 low register,                                   Address offset: 0x030C */
+  __IO uint32_t MACA2HR;             /*!< MAC Address 2 high register,                                  Address offset: 0x0310 */
+  __IO uint32_t MACA2LR;             /*!< MAC Address 2 low register,                                   Address offset: 0x0314 */
+  __IO uint32_t MACA3HR;             /*!< MAC Address 3 high register,                                  Address offset: 0x0318 */
+  __IO uint32_t MACA3LR;             /*!< MAC Address 3 low register,                                   Address offset: 0x031C */
+  uint32_t      RESERVED17[248];
+  __IO uint32_t MMCCR;               /*!< MMC control register,                                         Address offset: 0x0700 */
+  __IO uint32_t MMCRIR;              /*!< MMC Rx interrupt register,                                    Address offset: 0x0704 */
+  __IO uint32_t MMCTIR;              /*!< MMC Tx interrupt register,                                    Address offset: 0x0708 */
+  __IO uint32_t MMCRIMR;             /*!< MMC Rx interrupt mask register,                               Address offset: 0x070C */
+  __IO uint32_t MMCTIMR;             /*!< MMC Tx interrupt mask register,                               Address offset: 0x0710 */
+  uint32_t      RESERVED18[14];
+  __IO uint32_t MMCTSCGPR;           /*!< Tx single collision good packets register,                    Address offset: 0x074C */
+  __IO uint32_t MMCTMCGPR;           /*!< Tx multiple collision good packets register,                  Address offset: 0x0750 */
+  uint32_t      RESERVED19[5];
+  __IO uint32_t MMCTPCGR;            /*!< Tx packet count good register,                                Address offset: 0x0768 */
+  uint32_t      RESERVED20[10];
+  __IO uint32_t MMCRCRCEPR;          /*!< Rx CRC error packets register,                                Address offset: 0x0794 */
+  __IO uint32_t MMCRAEPR;            /*!< Rx alignment error packets register,                          Address offset: 0x0798 */
+  uint32_t      RESERVED21[10];
+  __IO uint32_t MMCRUPGR;            /*!< Rx unicast packets good register,                             Address offset: 0x07C4 */
+  uint32_t      RESERVED22[9];
+  __IO uint32_t MMCTLPIMSTR;         /*!< Tx LPI microsecond timer register,                            Address offset: 0x07EC */
+  __IO uint32_t MMCTLPITCR;          /*!< Tx LPI transition counter register,                           Address offset: 0x07F0 */
+  __IO uint32_t MMCRLPIMSTR;         /*!< Rx LPI microsecond counter register,                          Address offset: 0x07F4 */
+  __IO uint32_t MMCRLPITCR;          /*!< Rx LPI transition counter register,                           Address offset: 0x07F8 */
+  uint32_t      RESERVED23[41];
+  __IO uint32_t MMCFPETISR;          /*!< MMC FPE Tx interrupt status register,                         Address offset: 0x08A0 */
+  __IO uint32_t MMCFPETIMR;          /*!< MMC FPE Tx interrupt mask register,                           Address offset: 0x08A4 */
+  __IO uint32_t MMCFPETFCR;          /*!< MMC FPE Tx fragment counter register,       -                 Address offset: 0x08A8 */
+  __IO uint32_t MMCTHRCR;            /*!< MMC Tx hold request counter register,                         Address offset: 0x08AC */
+  uint32_t      RESERVED24[4];
+  __IO uint32_t MMCFPERISR;          /*!< MMC FPE Rx interrupt status register,                         Address offset: 0x08C0 */
+  __IO uint32_t MMCFPERIMR;          /*!< MMC FPE Rx interrupt mask register,                           Address offset: 0x08C4 */
+  __IO uint32_t MMCRPAER;            /*!< MMC Rx packet assembly error register,                        Address offset: 0x08C8 */
+  __IO uint32_t MMCRPSMDER;          /*!< MMC Rx packet SMD error register,                             Address offset: 0x08CC */
+  __IO uint32_t MMCRPAOKR;           /*!< MMC Rx packet assembly OK register,                           Address offset: 0x08D0 */
+  __IO uint32_t MMCFPERFCR;          /*!< MMC Rx FPE fragments counter register,                        Address offset: 0x08D4 */
+  uint32_t      RESERVED25[10];
+  __IO uint32_t MACL3L4C0R;          /*!< L3 and L4 control 0 register,                                 Address offset: 0x0900 */
+  __IO uint32_t MACL4A0R;            /*!< Layer4 Address filter 0 register,                             Address offset: 0x0904 */
+  uint32_t      RESERVED26[2];
+  __IO uint32_t MACL3A0R0R;           /*!< Layer3 Address 0 filter 0 register,                           Address offset: 0x0910 */
+  __IO uint32_t MACL3A1R0R;           /*!< Layer3 Address 1 filter 0 register,                           Address offset: 0x0914 */
+  __IO uint32_t MACL3A2R0R;           /*!< Layer3 Address 2 filter 0 register,                           Address offset: 0x0918 */
+  __IO uint32_t MACL3A3R0R;           /*!< Layer3 Address 3 filter 0 register,                           Address offset: 0x091C */
+  uint32_t      RESERVED27[4];
+  __IO uint32_t MACL3L4C1R;          /*!< L3 and L4 control 1 register,                                 Address offset: 0x0930 */
+  __IO uint32_t MACL4A1R;            /*!< Layer 4 address filter 1 register,                            Address offset: 0x0934 */
+  uint32_t      RESERVED28[2];
+  __IO uint32_t MACL3A01R;           /*!< Layer3 address 0 filter 1 Register,                           Address offset: 0x0940 */
+  __IO uint32_t MACL3A11R;           /*!< Layer3 address 1 filter 1 register,                           Address offset: 0x0944 */
+  __IO uint32_t MACL3A21R;           /*!< Layer3 address 2 filter 1 Register,                           Address offset: 0x0948 */
+  __IO uint32_t MACL3A31R;           /*!< Layer3 address 3 filter 1 register,                           Address offset: 0x094C */
+  uint32_t      RESERVED29[72];
+  __IO uint32_t MACIACR;             /*!< MAC Indirect Access Control register,                         Address offset: 0x0A70 */
+  __IO uint32_t MACTMRQR;            /*!< MAC type-based Rx Queue mapping register,                     Address offset: 0x0A74 */
+  uint32_t      RESERVED30[34];
+  __IO uint32_t MACTSCR;             /*!< Timestamp control Register,                                   Address offset: 0x0B00 */
+  __IO uint32_t MACSSIR;             /*!< Subsecond increment register,                                 Address offset: 0x0B04 */
+  __IO uint32_t MACSTSR;             /*!< System time seconds register,                                 Address offset: 0x0B08 */
+  __IO uint32_t MACSTNR;             /*!< System time nanoseconds register,                             Address offset: 0x0B0C */
+  __IO uint32_t MACSTSUR;            /*!< System time seconds update register,                          Address offset: 0x0B10 */
+  __IO uint32_t MACSTNUR;            /*!< System time nanoseconds update register,                      Address offset: 0x0B14 */
+  __IO uint32_t MACTSAR;             /*!< Timestamp addend register,                                    Address offset: 0x0B18 */
+  uint32_t      RESERVED31;
+  __IO uint32_t MACTSSR;             /*!< Timestamp status register,                                    Address offset: 0x0B20 */
+  uint32_t      RESERVED32[3];
+  __IO uint32_t MACTXTSSNR;          /*!< Tx timestamp status nanoseconds register,                     Address offset: 0x0B30 */
+  __IO uint32_t MACTXTSSSR;          /*!< Tx timestamp status seconds register,                         Address offset: 0x0B34 */
+  uint32_t      RESERVED33[2];
+  __IO uint32_t MACACR;              /*!< Auxiliary control register,                                   Address offset: 0x0B40 */
+  uint32_t      RESERVED34;
+  __IO uint32_t MACATSNR;            /*!< Auxiliary timestamp nanoseconds register,                     Address offset: 0x0B48 */
+  __IO uint32_t MACATSSR;            /*!< Auxiliary timestamp seconds register,                         Address offset: 0x0B4C */
+  __IO uint32_t MACTSIACR;           /*!< Timestamp Ingress asymmetric correction register,             Address offset: 0x0B50 */
+  __IO uint32_t MACTSEACR;           /*!< Timestamp Egress asymmetric correction register,              Address offset: 0x0B54 */
+  __IO uint32_t MACTSICNR;           /*!< Timestamp Ingress correction nanosecond register,             Address offset: 0x0B58 */
+  __IO uint32_t MACTSECNR;           /*!< Timestamp Egress correction nanosecond register,              Address offset: 0x0B5C */
+  uint32_t      RESERVED35[2];
+  __IO uint32_t MACTSILR;            /*!< Timestamp Ingress Latency register,                           Address offset: 0x0B68 */
+  __IO uint32_t MACTSELR;            /*!< Timestamp Egress Latency register,                            Address offset: 0x0B6C */
+  __IO uint32_t MACPPSCR;            /*!< PPS control register,                                         Address offset: 0x0B70 */
+  uint32_t      RESERVED36[3];
+  __IO uint32_t MACPPSTTS0R;         /*!< PPS 0 target time seconds register,                           Address offset: 0x0B80 */
+  __IO uint32_t MACPPSTTN0R;         /*!< PPS 0 target time nanoseconds register,                       Address offset: 0x0B84 */
+  __IO uint32_t MACPPSI0R;           /*!< PPS 0 interval register,                                      Address offset: 0x0B88 */
+  __IO uint32_t MACPPSW0R;           /*!< PPS 0 width register,                                         Address offset: 0x0B8C */
+  __IO uint32_t MACPPSTTS1R;         /*!< PPS 1 target time seconds register,                           Address offset: 0x0B90 */
+  __IO uint32_t MACPPSTTN1R;         /*!< PPS 1 target time nanoseconds register,                       Address offset: 0x0B94 */
+  __IO uint32_t MACPPSI1R;           /*!< PPS 1 interval register,                                      Address offset: 0x0B98 */
+  __IO uint32_t MACPPSW1R;           /*!< PPS 1 width register,                                         Address offset: 0x0B9C */
+  uint32_t      RESERVED37[8];
+  __IO uint32_t MACPOCR;             /*!< PTP Offload control register,                                 Address offset: 0x0BC0 */
+  __IO uint32_t MACSPI0R;            /*!< PTP Source Port Identity 0 Register,                          Address offset: 0x0BC4 */
+  __IO uint32_t MACSPI1R;            /*!< PTP Source port identity 1 register,                          Address offset: 0x0BC8 */
+  __IO uint32_t MACSPI2R;            /*!< PTP Source port identity 2 register,                          Address offset: 0x0BCC */
+  __IO uint32_t MACLMIR;             /*!< Log message interval register,                                Address offset: 0x0BD0 */
+  uint32_t      RESERVED38[11];
+  __IO uint32_t MTLOMR;              /*!< Operating mode Register,                                      Address offset: 0x0C00 */
+  uint32_t      RESERVED39[7];
+  __IO uint32_t MTLISR;              /*!< Interrupt status Register,                                    Address offset: 0x0C20 */
+  uint32_t      RESERVED40[3];
+  __IO uint32_t MTLRXQDMAMR;         /*!< Rx Queue and DMA Channel Mapping Register,                    Address offset: 0x0C30 */
+  uint32_t      RESERVED41[3];
+  __IO uint32_t MTLTBSCR;            /*!< TBS control register,                                         Address offset: 0x0C40 */
+  uint32_t      RESERVED42[3];
+  __IO uint32_t MTLESTCR;            /*!< EST Control Register,                                         Address offset: 0x0C50 */
+  __IO uint32_t MTLESTECR;           /*!< EST Extended Control Register,                                Address offset: 0x0C54 */
+  __IO uint32_t MTLESTSR;            /*!< EST Status Register,                                          Address offset: 0x0C58 */
+  uint32_t      RESERVED43;
+  __IO uint32_t MTLESTSCHER;         /*!< EST Schedule Error Register,                                  Address offset: 0x0C60 */
+  __IO uint32_t MTLESTFSER;          /*!< EST Frame size Error Register,                                Address offset: 0x0C64 */
+  __IO uint32_t MTLESTFSCR;          /*!< EST Frame size Capture Register,                              Address offset: 0x0C68 */
+  uint32_t      RESERVED44;
+  __IO uint32_t MTLESTIER;           /*!< EST Interrupt Enable Register,                                Address offset: 0x0C70 */
+  uint32_t      RESERVED45[3];
+  __IO uint32_t MTLESTGCLCR;         /*!< EST Gate Control List Register,                               Address offset: 0x0C80 */
+  __IO uint32_t MTLESTGCLDR;         /*!< EST Gate Control List Data Register,                          Address offset: 0x0C84 */
+  uint32_t      RESERVED46[2];
+  __IO uint32_t MTLFPECSR;           /*!< FPE Frame Preemption Control Status Register,                 Address offset: 0x0C90 */
+  __IO uint32_t MTLFPEAR;            /*!< FPE Frame Preemption Advance Register,                        Address offset: 0x0C94 */
+  uint32_t      RESERVED47[26];
+  struct {
+  __IO uint32_t MTLTXQOMR;           /*!< Tx queue x operating mode Register,                           Address offset: 0x0D00 */
+  __IO uint32_t MTLTXQUR;            /*!< Tx queue x underflow register,                                Address offset: 0x0D04 */
+  __IO uint32_t MTLTXQDR;            /*!< Tx queue x debug register,                                    Address offset: 0x0D08 */
+  uint32_t      RESERVED48[1];
+  __IO uint32_t MTLTXQ1ECR;           /*!< Tx queue 1 ETS control Register,                              Address offset: 0x0D50 */
+  __IO uint32_t MTLTXQESR;           /*!< Tx queue x ETS status Register,                               Address offset: 0x0D14 */
+  __IO uint32_t MTLTXQQWR;           /*!< Tx queue x quantum weight register,                           Address offset: 0x0D18 */
+  __IO uint32_t MTLTXQ1SSCR;          /*!< Tx queue 1 send slope credit Register,                        Address offset: 0x0D5C */
+  __IO uint32_t MTLTXQ1HCR;           /*!< Tx Queue 1 hiCredit register,                                 Address offset: 0x0D60 */
+  __IO uint32_t MTLTXQ1LCR;           /*!< Tx queue 1 loCredit register,                                 Address offset: 0x0D64 */
+  uint32_t      RESERVED49[1];
+  __IO uint32_t MTLQICSR;           /*!< Queue 0 interrupt control status Register,                    Address offset: 0x0D2C */
+  __IO uint32_t MTLRXQOMR;          /*!< Rx queue x operating mode register,                           Address offset: 0x0D30 */
+  __IO uint32_t MTLRXQMPOCR;        /*!< Rx queue x missed packet and overflow counter register,       Address offset: 0x0D34 */
+  __IO uint32_t MTLRXQDR;           /*!< Rx queue x debug register,                                    Address offset: 0x0D38 */
+  __IO uint32_t MTLRXQCR;           /*!< Rx queue x control register,                                  Address offset: 0x0D3C */
+  } MTL_QUEUE[2];
+  uint32_t      RESERVED52[160];
+  __IO uint32_t DMAMR;               /*!< DMA mode register,                                            Address offset: 0x1000 */
+  __IO uint32_t DMASBMR;             /*!< System bus mode register,                                     Address offset: 0x1004 */
+  __IO uint32_t DMAISR;              /*!< Interrupt status register,                                    Address offset: 0x1008 */
+  __IO uint32_t DMADSR;              /*!< Debug status register,                                        Address offset: 0x100C */
+  uint32_t      RESERVED53[4];
+  __IO uint32_t DMAA4TXACR;          /*!< AXI4 transmit channel ACE control register,                   Address offset: 0x1020 */
+  __IO uint32_t DMAA4RXACR;          /*!< AXI4 receive channel ACE control register,                    Address offset: 0x1024 */
+  __IO uint32_t DMAA4DACR;           /*!< AXI4 descriptor ACE control register,                         Address offset: 0x1028 */
+  uint32_t      RESERVED54[5];
+  __IO uint32_t DMALPIEI;            /*!< AXI4 LPI Entry Interval register,                             Address offset: 0x1040 */
+  uint32_t      RESERVED55[3];
+  __IO uint32_t DMATBSCTRL0R;        /*!< DMA TBS control register 0,                                   Address offset: 0x1050 */
+  uint32_t      RESERVED56[37];
+  struct {
+  uint32_t      RESERVED57[6];
+  __IO uint32_t DMACCR;             /*!< Channel x control register,                                   Address offset: 0x1100 */
+  __IO uint32_t DMACTXCR;           /*!< Channel x transmit control register,                          Address offset: 0x1104 */
+  __IO uint32_t DMACRXCR;           /*!< Channel x receive control register,                           Address offset: 0x1108 */
+  uint32_t      RESERVED58[2];
+  __IO uint32_t DMACTXDLAR;         /*!< Channel x Tx descriptor list address register,                Address offset: 0x1114 */
+  uint32_t      RESERVED59;
+  __IO uint32_t DMACRXDLAR;         /*!< Channel x Rx descriptor list address register,                Address offset: 0x111C */
+  __IO uint32_t DMACTXDTPR;         /*!< Channel x Tx descriptor tail pointer register,                Address offset: 0x1120 */
+  uint32_t      RESERVED60;
+  __IO uint32_t DMACRXDTPR;         /*!< Channel x Rx descriptor tail pointer register,                Address offset: 0x1128 */
+  __IO uint32_t DMACTXRLR;          /*!< Channel x Tx descriptor ring length register,                 Address offset: 0x112C */
+  __IO uint32_t DMACRXRLR;          /*!< Channel x Rx descriptor ring length register,                 Address offset: 0x1130 */
+  __IO uint32_t DMACIER;            /*!< Channel x interrupt enable register,                          Address offset: 0x1134 */
+  __IO uint32_t DMACRXIWTR;         /*!< Channel x Rx interrupt watchdog timer register,               Address offset: 0x1138 */
+  __IO uint32_t DMACSFCSR;          /*!< Channel x slot function control status register,              Address offset: 0x113C */
+  uint32_t      RESERVED61;
+  __IO uint32_t DMACCATXDR;         /*!< Channel x current application transmit descriptor register,   Address offset: 0x1144 */
+  uint32_t      RESERVED62;
+  __IO uint32_t DMACCARXDR;         /*!< Channel x current application receive descriptor register,    Address offset: 0x114C */
+  uint32_t      RESERVED63;
+  __IO uint32_t DMACCATXBR;         /*!< Channel x current application transmit buffer register,       Address offset: 0x1154 */
+  uint32_t      RESERVED64;
+  __IO uint32_t DMACCARXBR;         /*!< Channel x current application receive buffer register,        Address offset: 0x115C */
+  __IO uint32_t DMACSR;             /*!< Channel x status register,                                    Address offset: 0x1160 */
+  __IO uint32_t DMACMFCR;            /*!< Channel x missed frame count register,                        Address offset: 0x1164 */
+  } DMA_CH[2];
+}ETH_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+typedef struct
+{
+  __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
+  __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
+  __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
+  __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
+  __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
+  __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
+  __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
+       uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x1C */
+  __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
+  __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
+  __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
+  __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
+  __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
+  __IO uint32_t SECCFGR2;       /*!< EXTI Security Configuration Register 2,          Address offset:   0x34 */
+  __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
+       uint32_t RESERVED2;      /*!< Reserved 2,                                      Address offset:   0x3C */
+  __IO uint32_t RTSR3;          /*!< EXTI Rising Trigger Selection Register 3,        Address offset:   0x40 */
+  __IO uint32_t FTSR3;          /*!< EXTI Falling Trigger Selection Register 3,       Address offset:   0x44 */
+  __IO uint32_t SWIER3;         /*!< EXTI Software Interrupt event Register 3,        Address offset:   0x48 */
+  __IO uint32_t RPR3;           /*!< EXTI Rising Pending Register 3,                  Address offset:   0x4C */
+  __IO uint32_t FPR3;           /*!< EXTI Falling Pending Register 3,                 Address offset:   0x50 */
+  __IO uint32_t SECCFGR3;       /*!< EXTI Security Configuration Register 3,          Address offset:   0x54 */
+  __IO uint32_t PRIVCFGR3;      /*!< EXTI Privilege Configuration Register 3,         Address offset:   0x58 */
+       uint32_t RESERVED3;      /*!< Reserved 3,                                      Address offset:   0x5C */
+  __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
+  __IO uint32_t LOCKR;          /*!< EXTI Lock Register,                              Address offset:   0x70 */
+       uint32_t RESERVED4[3];   /*!< Reserved 4,                                                0x74 -- 0x7C */
+  __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
+  __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
+       uint32_t RESERVED5[2];   /*!< Reserved 5,                                                0x88 -- 0x8C */
+  __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
+  __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
+       uint32_t RESERVED6[2];   /*!< Reserved 6,                                                0x98 -- 0x9C */
+  __IO uint32_t IMR3;           /*!< EXTI Interrupt Mask Register 3,                  Address offset:   0xA0 */
+  __IO uint32_t EMR3;           /*!< EXTI Event Mask Register 3,                      Address offset:   0xA4 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t CREL;           /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+ __IO uint32_t ENDN;           /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+ __IO uint32_t RESERVED1;      /*!< Reserved,                                                                        0x008 */
+ __IO uint32_t DBTP;           /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+ __IO uint32_t TEST;           /*!< FDCAN Test register,                                             Address offset: 0x010 */
+ __IO uint32_t RWD;            /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+ __IO uint32_t CCCR;           /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+ __IO uint32_t NBTP;           /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+ __IO uint32_t TSCC;           /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+ __IO uint32_t TSCV;           /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+ __IO uint32_t TOCC;           /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+ __IO uint32_t TOCV;           /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+ __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                                0x030 - 0x03C */
+ __IO uint32_t ECR;            /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+ __IO uint32_t PSR;            /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+ __IO uint32_t TDCR;           /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+ __IO uint32_t RESERVED3;      /*!< Reserved,                                                                        0x04C */
+ __IO uint32_t IR;             /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+ __IO uint32_t IE;             /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+ __IO uint32_t ILS;            /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+ __IO uint32_t ILE;            /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+ __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                                0x060 - 0x07C */
+ __IO uint32_t GFC;            /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+ __IO uint32_t SIDFC;          /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+ __IO uint32_t XIDFC;          /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+ __IO uint32_t RESERVED5;      /*!< Reserved,                                                                        0x08C */
+ __IO uint32_t XIDAM;          /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+ __IO uint32_t HPMS;           /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+ __IO uint32_t NDAT1;          /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+ __IO uint32_t NDAT2;          /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+ __IO uint32_t RXF0C;          /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+ __IO uint32_t RXF0S;          /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+ __IO uint32_t RXF0A;          /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+ __IO uint32_t RXBC;           /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+ __IO uint32_t RXF1C;          /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+ __IO uint32_t RXF1S;          /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+ __IO uint32_t RXF1A;          /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+ __IO uint32_t RXESC;          /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+ __IO uint32_t TXBC;           /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+ __IO uint32_t TXFQS;          /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+ __IO uint32_t TXESC;          /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+ __IO uint32_t TXBRP;          /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+ __IO uint32_t TXBAR;          /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+ __IO uint32_t TXBCR;          /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+ __IO uint32_t TXBTO;          /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+ __IO uint32_t TXBCF;          /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+ __IO uint32_t TXBTIE;         /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+ __IO uint32_t TXBCIE;         /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+ __IO uint32_t RESERVED6[2];   /*!< Reserved,                                                                0x0E8 - 0x0EC */
+ __IO uint32_t TXEFC;          /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+ __IO uint32_t TXEFS;          /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+ __IO uint32_t TXEFA;          /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+ __IO uint32_t RESERVED7;      /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;         /*!< TT Trigger Memory Configuration register,        Address offset: 0x100 */
+  __IO uint32_t TTRMC;         /*!< TT Reference Message Configuration register,     Address offset: 0x104 */
+  __IO uint32_t TTOCF;         /*!< TT Operation Configuration register,             Address offset: 0x108 */
+  __IO uint32_t TTMLM;         /*!< TT Matrix Limits register,                       Address offset: 0x10C */
+  __IO uint32_t TURCF;         /*!< TUR Configuration register,                      Address offset: 0x110 */
+  __IO uint32_t TTOCN;         /*!< TT Operation Control register,                   Address offset: 0x114 */
+  __IO uint32_t TTGTP;         /*!< TT Global Time Preset register,                  Address offset: 0x118 */
+  __IO uint32_t TTTMK;         /*!< TT Time Mark register,                          Address offset: 0x11C */
+  __IO uint32_t TTIR;          /*!< TT Interrupt register,                           Address offset: 0x120 */
+  __IO uint32_t TTIE;          /*!< TT Interrupt Enable register,                    Address offset: 0x124 */
+  __IO uint32_t TTILS;         /*!< TT Interrupt Line Select register,               Address offset: 0x128 */
+  __IO uint32_t TTOST;         /*!< TT Operation Status register,                    Address offset: 0x12C */
+  __IO uint32_t TURNA;         /*!< TT TUR Numerator Actual register,                Address offset: 0x130 */
+  __IO uint32_t TTLGT;         /*!< TT Local and Global Time register,               Address offset: 0x134 */
+  __IO uint32_t TTCTC;         /*!< TT Cycle Time and Count register,                Address offset: 0x138 */
+  __IO uint32_t TTCPT;         /*!< TT Capture Time register,                        Address offset: 0x13C */
+  __IO uint32_t TTCSM;         /*!< TT Cycle Sync Mark register,                     Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111];/*!< Reserved,                                                0x144 - 0x2FC */
+  __IO uint32_t TTTS;          /*!< TT Trigger Select register,                      Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;          /*!< Clock Calibration Unit Core Release register,    Address offset: 0x00 */
+  __IO uint32_t CCFG;          /*!< Calibration Configuration register,              Address offset: 0x04 */
+  __IO uint32_t CSTAT;         /*!< Calibration Status register,                     Address offset: 0x08 */
+  __IO uint32_t CWD;           /*!< Calibration Watchdog register,                   Address offset: 0x0C */
+  __IO uint32_t IR;            /*!< CCU Interrupt register,                          Address offset: 0x10 */
+  __IO uint32_t IE;            /*!< CCU Interrupt Enable register,                   Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+/**
+ * @brief FD Controller Area Network Configuration
+ */
+typedef struct
+{
+ __IO uint32_t CKDIV;          /*!< FDCAN clock divider register,            Address offset: 0x100 + 0x000 */
+      uint32_t RESERVED1[128]; /*!< Reserved,                                0x100 + 0x004 - 0x100 + 0x200 */
+ __IO uint32_t OPTR;           /*!< FDCAN option register,                   Address offset: 0x100 + 0x204 */
+      uint32_t RESERVED2[58];  /*!< Reserved,                                0x100 + 0x208 - 0x100 + 0x2EC */
+ __IO uint32_t HWCFG;          /*!< FDCAN hardware configuration register,   Address offset: 0x100 + 0x2F0 */
+ __IO uint32_t VERR;           /*!< FDCAN IP version register,               Address offset: 0x100 + 0x2F4 */
+ __IO uint32_t IPIDR;          /*!< FDCAN IP ID register,                    Address offset: 0x100 + 0x2F8 */
+ __IO uint32_t SIDR;           /*!< FDCAN size ID register,                  Address offset: 0x100 + 0x2FC */
+} FDCAN_Config_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1
+  */
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+typedef struct
+{
+  __IO uint32_t SDCR[2];         /*!< SDRAM device 1/2 control register                      Address offset: 0x140-0x144 */
+  __IO uint32_t SDTR;            /*!< SDRAM timing register                                  Address offset: 0x148 */
+       uint32_t RESERVED0;       /*!< Reserved                                               Address offset: 0x14C */
+  __IO uint32_t SDCMR;           /*!< SDRAM command mode register                            Address offset: 0x150 */
+  __IO uint32_t SDRTR;           /*!< SDRAM refresh timer register                           Address offset: 0x154 */
+  __IO uint32_t SDSR;            /*!< SDRAM status register                                  Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+typedef struct
+{
+  __IO uint32_t PCR;             /*!< NAND Flash Programmable control register               Address offset: 0x080 */
+  __IO uint32_t SR;              /*!< FMC status register                                    Address offset: 0x084 */
+  __IO uint32_t PMEM;            /*!< Common memory space timing register                    Address offset: 0x088 */
+  __IO uint32_t PATT;            /*!< Attribute memory space timing registers                Address offset: 0x08C */
+  __IO uint32_t HPR;             /*!< FMC Hamming parity result registers                    Address offset: 0x090 */
+  __IO uint32_t HECCR;           /*!< FMC Hamming code ECC result register                   Address offset: 0x094 */
+       uint32_t RESERVED0[58];   /*!< Reserved                                               Address offset: 0x098-0x17C */
+  __IO uint32_t IER;             /*!< FMC NAND Interrupt Enable Register                     Address offset: 0x180 */
+  __IO uint32_t ISR;             /*!< FMC Controller Interrupt Status Register               Address offset: 0x184 */
+  __IO uint32_t ICR;             /*!< FMC NAND Controller Interrupt Clear Register           Address offset: 0x188 */
+       uint32_t RESERVED1[29];   /*!< Reserved                                               Address offset: 0x18C-0x1FC */
+  __IO uint32_t CSQCR;           /*!< FMC NAND Command Sequencer Control Register            Address offset: 0x200 */
+  __IO uint32_t CSQCFGR1;        /*!< FMC NAND Command Sequencer Configuration Register 1    Address offset: 0x204 */
+  __IO uint32_t CSQCFGR2;        /*!< FMC NAND Command Sequencer Configuration Register 2    Address offset: 0x208 */
+  __IO uint32_t CSQCFGR3;        /*!< FMC NAND sequencer configuration register 3            Address offset: 0x20C */
+  __IO uint32_t CSQAR1;          /*!< FMC NAND Command Sequencer Address Register 1          Address offset: 0x210 */
+  __IO uint32_t CSQAR2;          /*!< FMC NAND Command Sequencer Address Register 2          Address offset: 0x214 */
+       uint32_t RESERVED2[2];    /*!< Reserved                                               Address offset: 0x218-0x21C */
+  __IO uint32_t CSQIER;          /*!< FMC NAND Command Sequencer Interrupt Enable Register   Address offset: 0x220 */
+  __IO uint32_t CSQISR;          /*!< FMC NAND Command Sequencer Interrupt Status Register   Address offset: 0x224 */
+  __IO uint32_t CSQICR;          /*!< FMC NAND Command Sequencer Interrupt Clear Register    Address offset: 0x228 */
+       uint32_t RESERVED3;       /*!< Reserved                                               Address offset: 0x22C */
+  __IO uint32_t CSQEMSR;         /*!< FMC Command Sequencer Error Mapping Status register    Address offset: 0x230 */
+       uint32_t RESERVED4[7];    /*!< Reserved                                               Address offset: 0x234-0x24C */
+  __IO uint32_t BCHIER;          /*!< FMC BCH Interrupt enable register                      Address offset: 0x250 */
+  __IO uint32_t BCHISR;          /*!< FMC BCH Interrupt and Status Register                  Address offset: 0x254 */
+  __IO uint32_t BCHICR;          /*!< FMC BCH Interrupt Clear Register                       Address offset: 0x258 */
+       uint32_t RESERVED5;       /*!< Reserved                                               Address offset: 0x25C */
+  __IO uint32_t BCHPBR1;         /*!< FMC BCH Parity Bits Register 1                         Address offset: 0x260 */
+  __IO uint32_t BCHPBR2;         /*!< FMC BCH Parity Bits Register 2                         Address offset: 0x264 */
+  __IO uint32_t BCHPBR3;         /*!< FMC BCH Parity Bits Register 3                         Address offset: 0x268 */
+  __IO uint32_t BCHPBR4;         /*!< FMC BCH Parity Bits Register 4                         Address offset: 0x26C */
+       uint32_t RESERVED6[3];    /*!< Reserved                                               Address offset: 0x270-0x278 */
+  __IO uint32_t BCHDSR0;         /*!< FMC BCH Decoder Status register 0                      Address offset: 0x27C */
+  __IO uint32_t BCHDSR1;         /*!< FMC BCH Decoder Status register for bank 1             Address offset: 0x280 */
+  __IO uint32_t BCHDSR2;         /*!< FMC BCH Decoder Status register for bank 2             Address offset: 0x284 */
+  __IO uint32_t BCHDSR3;         /*!< FMC BCH Decoder Status register for bank 3             Address offset: 0x288 */
+  __IO uint32_t BCHDSR4;         /*!< FMC BCH Decoder Status register for bank 4             Address offset: 0x28C */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Common
+  */
+typedef struct{
+  __IO uint32_t CFGR;            /*!< FMC common configuration register                      Address offset: 0x020 */
+} FMC_Common_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+typedef struct
+{
+  __IO uint32_t MODER;         /*!< GPIO port mode register,                     Address offset: 0x00      */
+  __IO uint32_t OTYPER;        /*!< GPIO port output type register,              Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;       /*!< GPIO port output speed register,             Address offset: 0x08      */
+  __IO uint32_t PUPDR;         /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
+  __IO uint32_t IDR;           /*!< GPIO port input data register,               Address offset: 0x10      */
+  __IO uint32_t ODR;           /*!< GPIO port output data register,              Address offset: 0x14      */
+  __IO uint32_t BSRR;          /*!< GPIO port bit set/reset  register,           Address offset: 0x18      */
+  __IO uint32_t LCKR;          /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
+  __IO uint32_t AFR[2];        /*!< GPIO alternate function registers,           Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;           /*!< GPIO bit reset register,                     Address offset: 0x28      */
+       uint32_t RESERVED0;     /*!< Reserved,                                    Address offset: 0x2C      */
+  __IO uint32_t SECCFGR;       /*!< GPIO port secure configuration register,     Address offset: 0x30      */
+  __IO uint32_t PRIVCFGR;      /*!< GPIO port privileged configuration register, Address offset: 0x34      */
+  __IO uint32_t RCFGLOCKR;     /*!< GPIO port resource configuration register,   Address offset: 0x38      */
+       uint32_t RESERVED1;     /*!< Reserved,                                    Address offset: 0x3C      */
+  __IO uint32_t DELAYR[2];     /*!< GPIO port delay register,                    Address offset: 0x40-0x44 */
+  __IO uint32_t ADVCFGR[2];    /*!< GPIO port advanced configuration register,   Address offset: 0x48-0x4C */
+} GPIO_TypeDef;
+
+/**
+  * @brief GFXMMU
+  */
+typedef struct
+{
+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
+       uint32_t RESERVED0;       /*!< Reserved0,                                         Address offset: 0x0C */
+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
+  __IO uint32_t DAR;             /*!< GFXMMU default alpha register,                     Address offset: 0x14 */
+       uint32_t RESERVED1[2];    /*!< Reserved1,                                 Address offset: 0x18 to 0x1C */
+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                 Address offset: 0x30 to 0xFFC */
+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                      Address offset: 0x1000 to 0x2FFC
+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
+} GFXMMU_TypeDef;
+
+/**
+  * @brief GFXTIM
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< GFXTIM configuration register,                    Address offset: 0x00 */
+  __IO uint32_t CGCR;          /*!< GFXTIM clock generator configuration register,    Address offset: 0x04 */
+  __IO uint32_t TCR;           /*!< GFXTIM timers configuration register,             Address offset: 0x08 */
+  __IO uint32_t TDR;           /*!< GFXTIM timers disable register,                   Address offset: 0x0C */
+  __IO uint32_t EVCR;          /*!< GFXTIM events control register,                   Address offset: 0x10 */
+  __IO uint32_t EVSR;          /*!< GFXTIM events selection register,                 Address offset: 0x14 */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                         Address offset: 0x18-0x1C */
+  __IO uint32_t WDGTCR;        /*!< GFXTIM watchdog timer configuration register,     Address offset: 0x20 */
+  uint32_t RESERVED2[3];       /*!< Reserved,                                         Address offset: 0x24-0x2C */
+  __IO uint32_t ISR;           /*!< GFXTIM interrupt status register,                 Address offset: 0x30 */
+  __IO uint32_t ICR;           /*!< GFXTIM interrupt clear register,                  Address offset: 0x34 */
+  __IO uint32_t IER;           /*!< GFXTIM interrupt enable register,                 Address offset: 0x38 */
+  __IO uint32_t TSR;           /*!< GFXTIM timers status register,                    Address offset: 0x3C */
+  __IO uint32_t LCCRR;         /*!< GFXTIM line clock counter reload register,        Address offset: 0x40 */
+  __IO uint32_t FCCRR;         /*!< GFXTIM frame clock counter reload register,       Address offset: 0x44 */
+  uint32_t RESERVED3[2];       /*!< Reserved,                                         Address offset: 0x48-0x4C */
+  __IO uint32_t ATR;           /*!< GFXTIM absolute time register,                    Address offset: 0x50 */
+  __IO uint32_t AFCR;          /*!< GFXTIM absolute frame counter register,           Address offset: 0x54 */
+  __IO uint32_t ALCR;          /*!< GFXTIM absolute line counter register,            Address offset: 0x58 */
+  uint32_t RESERVED4[1];       /*!< Reserved,                                         Address offset: 0x5C */
+  __IO uint32_t AFCC1R;        /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
+  uint32_t RESERVED5[3];       /*!< Reserved,                                         Address offset: 0x64-0X6C */
+  __IO uint32_t ALCC1R;        /*!< GFXTIM absolute line counter compare 1 register,  Address offset: 0x70 */
+  __IO uint32_t ALCC2R;        /*!< GFXTIM absolute line counter compare 2 register,  Address offset: 0x74 */
+  uint32_t RESERVED6[2];       /*!< Reserved,                                         Address offset: 0x78-0X7C */
+  __IO uint32_t RFC1R;         /*!< GFXTIM relative frame counter 1 register,         Address offset: 0x80 */
+  __IO uint32_t RFC1RR;        /*!< GFXTIM relative frame counter 1 reload register,  Address offset: 0x84 */
+  __IO uint32_t RFC2R;         /*!< GFXTIM relative frame counter 2 register,         Address offset: 0x88 */
+  __IO uint32_t RFC2RR;        /*!< GFXTIM relative frame counter 2 reload register,  Address offset: 0x8C */
+  uint32_t RESERVED7[4];       /*!< Reserved,                                         Address offset: 0x90-0X9C */
+  __IO uint32_t WDGCR;         /*!< GFXTIM watchdog counter register,                 Address offset: 0xA0 */
+  __IO uint32_t WDGRR;         /*!< GFXTIM watchdog reload register,                  Address offset: 0xA4 */
+  __IO uint32_t WDGPAR;        /*!< GFXTIM watchdog pre-alarm register,               Address offset: 0xA8 */
+  uint32_t RESERVED8[209];     /*!< Reserved,                                         Address offset: 0xAC-0X3EC */
+  __IO uint32_t HWCFGR;        /*!< GFXTIM HW configuration register,                 Address offset: 0x3F0 */
+  __IO uint32_t VERR;          /*!< GFXTIM version register,                          Address offset: 0x3F4 */
+  __IO uint32_t IPIDR;         /*!< GFXTIM identification register,                   Address offset: 0x3F8 */
+  __IO uint32_t SIDR;          /*!< GFXTIM size identification register,              Address offset: 0x3FC */
+} GFXTIM_TypeDef;
+
+/**
+  * @brief HASH
+  */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
+} HASH_TypeDef;
+
+/**
+  * @brief HASH_DIGEST
+  */
+typedef struct
+{
+  __IO uint32_t HR[16];           /*!< HASH digest registers,          Address offset: 0x310-0x34C */
+} HASH_DIGEST_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Improved Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
+  uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
+  __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
+  __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
+  __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
+  __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
+  __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
+  __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
+  __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
+  uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
+  __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
+  uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
+  __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
+  __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
+  __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
+  uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
+  __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
+  __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
+  uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
+  __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
+  __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
+  uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
+  __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
+  __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
+  __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
+  uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
+  __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
+  __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
+  __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
+  __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
+  __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
+  __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
+} I3C_TypeDef;
+
+/**
+  * @brief Illegal Access Controller
+  */
+typedef struct
+{
+  __IO uint32_t IER[5];         /*!< Interrupt Enable register,                 Address offset: 0x000       */
+  uint32_t      RESERVED1[27];  /*!< Reserved,                                  Address offset: 0x014-0x07C */
+  __IO uint32_t ISR[5];         /*!< Interrupt Status register,                 Address offset: 0x080       */
+  uint32_t      RESERVED2[27];  /*!< Reserved,                                  Address offset: 0x094-0x0FC */
+  __IO uint32_t ICR[5];         /*!< Interrupt Clear register,                  Address offset: 0x100       */
+} IAC_TypeDef;
+
+/**
+  * @brief Instruction Cache
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
+  __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
+  __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
+  __IO uint32_t FCR;            /*!< ICACHE flag clear register,             Address offset: 0x0C */
+  __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
+  __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
+} ICACHE_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t KR;              /*!< IWDG key register                    Address offset: 0x000 */
+  __IO uint32_t PR;              /*!< IWDG prescaler register              Address offset: 0x004 */
+  __IO uint32_t RLR;             /*!< IWDG reload register                 Address offset: 0x008 */
+  __IO uint32_t SR;              /*!< IWDG status register                 Address offset: 0x00C */
+  __IO uint32_t WINR;            /*!< IWDG window register                 Address offset: 0x010 */
+  __IO uint32_t EWCR;            /*!< IWDG early wakeup interrupt register Address offset: 0x014 */
+  __IO uint32_t ICR;             /*!< IWDG interrupt clear register        Address offset: 0x018 */
+} IWDG_TypeDef;
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+
+/**
+  * @brief LCD-TFT Display Controller (LTDC)
+  */
+typedef struct
+{
+       uint32_t RESERVED0[2];   /*!< Reserved Address offset: 0x00-0x04 */
+  __IO uint32_t SSCR;           /*!< LTDC synchronization size configuration register Address offset: 0x8 */
+  __IO uint32_t BPCR;           /*!< LTDC back porch configuration register Address offset: 0xc */
+  __IO uint32_t AWCR;           /*!< LTDC active width configuration register Address offset: 0x10 */
+  __IO uint32_t TWCR;           /*!< LTDC total width configuration register Address offset: 0x14 */
+  __IO uint32_t GCR;            /*!< LTDC global control register Address offset: 0x18 */
+       uint32_t RESERVED1[2];   /*!< Reserved Address offset: */
+  __IO uint32_t SRCR;           /*!< LTDC shadow reload configuration register Address offset: 0x24 */
+  __IO uint32_t GCCR;           /*!< LTDC gamma correction configuration register Address offset: 0x28 */
+  __IO uint32_t BCCR;           /*!< LTDC background color configuration register Address offset: 0x2c */
+       uint32_t RESERVED2;      /*!< Reserved Address offset: 0x30 */
+  __IO uint32_t IER;            /*!< LTDC interrupt enable register Address offset: 0x34 */
+  __IO uint32_t ISR;            /*!< LTDC interrupt status register Address offset: 0x38 */
+  __IO uint32_t ICR;            /*!< LTDC Interrupt Clear Register Address offset: 0x3c */
+  __IO uint32_t LIPCR;          /*!< LTDC line interrupt position configuration register Address offset: 0x40 */
+  __IO uint32_t CPSR;           /*!< LTDC current position status register Address offset: 0x44 */
+  __IO uint32_t CDSR;           /*!< LTDC current display status register Address offset: 0x48 */
+       uint32_t RESERVED3[5];   /*!< Reserved Address offset: 0x4c */
+  __IO uint32_t EDCR;           /*!< LTDC external display control register Address offset: 0x60 */
+  __IO uint32_t IER2;           /*!< LTDC interrupt enable register 2 Address offset: 0x64 */
+  __IO uint32_t ISR2;           /*!< LTDC interrupt status register 2 Address offset: 0x68 */
+  __IO uint32_t ICR2;           /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */
+  __IO uint32_t LIPCR2;         /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */
+       uint32_t RESERVED4;      /*!< Reserved Address offset: 0x74 */
+  __IO uint32_t ECRCR;          /*!< LTDC expected CRC register Address offset: 0x78 */
+  __IO uint32_t CCRCR;          /*!< LTDC computed CRC register Address offset: 0x7c */
+  __IO uint32_t RB0AR;          /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */
+  __IO uint32_t RB1AR;          /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */
+  __IO uint32_t RBPR;           /*!< LTDC rotation buffer pitch register Address offset: 0x88 */
+  __IO uint32_t RIFCR;          /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */
+  __IO uint32_t FUTR;           /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller (LTDC)
+  */
+typedef struct
+{
+  __IO uint32_t C0R;          /*!< LTDC layer x configuration 0 register Address offset: 0x100 */
+  __IO uint32_t C1R;          /*!< LTDC layer x configuration 1 register Address offset: 0x104 */
+  __IO uint32_t RCR;          /*!< LTDC layer x reload control register Address offset: 0x108 */
+  __IO uint32_t CR;           /*!< LTDC layer x control register Address offset: 0x10c */
+  __IO uint32_t WHPCR;        /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */
+  __IO uint32_t WVPCR;        /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */
+  __IO uint32_t CKCR;         /*!< LTDC layer x color keying configuration register Address offset: 0x118 */
+  __IO uint32_t PFCR;         /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */
+  __IO uint32_t CACR;         /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */
+  __IO uint32_t DCCR;         /*!< LTDC layer x default color configuration register Address offset: 0x124 */
+  __IO uint32_t BFCR;         /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */
+  __IO uint32_t BLCR;         /*!< LTDC layer x burst length configuration register Address offset: 0x12c */
+  __IO uint32_t PCR;          /*!< LTDC layer x planar configuration register Address offset: 0x130 */
+  __IO uint32_t CFBAR;        /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */
+  __IO uint32_t CFBLR;        /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */
+  __IO uint32_t CFBLNR;       /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */
+  __IO uint32_t AFBA0R;       /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */
+  __IO uint32_t AFBA1R;       /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */
+  __IO uint32_t AFBLR;        /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */
+  __IO uint32_t AFBLNR;       /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */
+  __IO uint32_t CLUTWR;       /*!< LTDC layer x CLUT write register Address offset: 0x150 */
+  __IO uint32_t SISR;         /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */
+  __IO uint32_t SOSR;         /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */
+  __IO uint32_t SVSFR;        /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */
+  __IO uint32_t SVSPR;        /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */
+  __IO uint32_t SHSFR;        /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */
+  __IO uint32_t SHSPR;        /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */
+  __IO uint32_t CYR0R;        /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */
+  __IO uint32_t CYR1R;        /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */
+  __IO uint32_t FPF0R;        /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */
+  __IO uint32_t FPF1R;        /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */
+} LTDC_Layer_TypeDef;
+
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
+  __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
+  __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
+  __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
+  __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
+  __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
+  __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
+  __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
+  __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x20 */
+  __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
+  __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
+  __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
+  __IO uint32_t RESERVED2;      /*!< Reserved,                               Address offset: 0x30 */
+  __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
+} LPTIM_TypeDef;
+
+
+
+/**
+  * @brief ADF
+  */
+typedef struct
+{
+  __IO uint32_t GCR;            /*!< MDF Global Control register,             Address offset: 0x00  */
+  __IO uint32_t CKGCR;          /*!< MDF Clock Generator Control Register,    Address offset: 0x04  */
+  uint32_t      RESERVED1[6];   /*!< Reserved, 0x08-0x1C                                            */
+  __IO uint32_t OR;             /*!< MDF  Option Register,                    Address offset: 0x20  */
+} MDF_TypeDef;
+
+/**
+  * @brief ADF filter
+  */
+typedef struct
+{
+ __IO uint32_t SITFCR;         /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
+ __IO uint32_t BSMXCR;         /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
+ __IO uint32_t DFLTCR;         /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
+ __IO uint32_t DFLTCICR;       /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
+ __IO uint32_t DFLTRSFR;       /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
+ __IO uint32_t DFLTINTR;       /*!< MDF Integrator Configuration Register,          Address offset: 0x94 */
+ __IO uint32_t OLDCR;          /*!< MDF Out-Of Limit Detector Control Register,     Address offset: 0x98 */
+ __IO uint32_t OLDTHLR;        /*!< MDF OLD Threshold Low Register,                 Address offset: 0x9C */
+ __IO uint32_t OLDTHHR;        /*!< MDF OLD Threshold High Register,                Address offset: 0xA0 */
+ __IO uint32_t DLYCR;          /*!< MDF Delay control Register,                     Address offset: 0xA4 */
+ __IO uint32_t SCDCR;          /*!< MDF short circuit detector control Register,    Address offset: 0xA8 */
+ __IO uint32_t DFLTIER;        /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
+ __IO uint32_t DFLTISR;        /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
+ __IO uint32_t OECCR;          /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
+ __IO uint32_t SADCR;          /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
+ __IO uint32_t SADCFGR;        /*!< MDF SAD configuration register,                 Address offset: 0xBC */
+ __IO uint32_t SADSDLVR;       /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
+ __IO uint32_t SADANLVR;       /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
+ uint32_t     RESERVED1[9];    /*!< Reserved, 0xC8-0xE8                                                  */
+ __IO uint32_t SNPSDR;         /*!< MDF Snapshot Data Register,                     Address offset: 0xEC */
+ __IO uint32_t DFLTDR;         /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
+} MDF_Filter_TypeDef;
+
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+/**
+  * @brief PSSI
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< PSSI control register,                 Address offset: 0x000 */
+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
+} PSSI_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+typedef struct
+{
+  __IO uint32_t CR1;             /*!< PWR Control register 1                           Address offset: 0x000 */
+  __IO uint32_t CR2;             /*!< PWR Control Register 2                           Address offset: 0x004 */
+  __IO uint32_t CR3;             /*!< PWR Control Register 3                           Address offset: 0x008 */
+  __IO uint32_t CR4;             /*!< PWR Control Register 4                           Address offset: 0x00C */
+       uint32_t RESERVED0[4];    /*!< Reserved                                         Address offset: 0x010-0x01C */
+  __IO uint32_t VOSCR;           /*!< PWR Voltage scaling control register             Address offset: 0x020 */
+  __IO uint32_t BDCR1;           /*!< PWR Backup domain control register 1             Address offset: 0x024 */
+  __IO uint32_t BDCR2;           /*!< PWR Backup domain control register 2             Address offset: 0x028 */
+  __IO uint32_t DBPCR;           /*!< PWR Disable backup protection control register   Address offset: 0x02C */
+  __IO uint32_t CPUCR;           /*!< PWR CPU control register                         Address offset: 0x030 */
+  __IO uint32_t SVMCR1;          /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */
+  __IO uint32_t SVMCR2;          /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */
+  __IO uint32_t SVMCR3;          /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */
+       uint32_t RESERVED1[4];    /*!< Reserved                                         Address offset: 0x040-0x04C */
+  __IO uint32_t WKUPCR;          /*!< PWR Wakeup control register 1                    Address offset: 0x050 */
+  __IO uint32_t WKUPSR;          /*!< PWR Wakeup control register 2                    Address offset: 0x054 */
+  __IO uint32_t WKUPEPR;         /*!< PWR Wakeup control register 3                    Address offset: 0x058 */
+       uint32_t RESERVED2[5];    /*!< Reserved                                         Address offset: 0x05C-0x06C */
+  __IO uint32_t SECCFGR;         /*!< PWR Security configuration register              Address offset: 0x070 */
+  __IO uint32_t PRIVCFGR;        /*!< PWR Privilege configuration register             Address offset: 0x074 */
+} PWR_TypeDef;
+
+/**
+  * @brief PKA
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< PKA control register,             Address offset: 0x00 */
+  __IO uint32_t SR;            /*!< PKA status register,              Address offset: 0x04 */
+  __IO uint32_t CLRFR;         /*!< PKA clear flag register,          Address offset: 0x08 */
+  uint32_t Reserved[253];      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
+  __IO uint32_t RAM[1334];     /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
+} PKA_TypeDef;
+
+/**
+  * @brief RAMs configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control Register,                    Address offset: 0x00 */
+  __IO uint32_t IER;         /*!< Interrupt Enable Register,           Address offset: 0x04 */
+  __IO uint32_t ISR;         /*!< Interrupt Status Register,           Address offset: 0x08 */
+  __IO uint32_t ESEAR;       /*!< ECC Single Error Address Register,   Address offset: 0x0C */
+  __IO uint32_t EDEAR;       /*!< ECC Double Error Address Register,   Address offset: 0x10 */
+  __IO uint32_t ICR;         /*!< Interrupt Clear Register,            Address offset: 0x14 */
+  uint32_t      RESERVED[3]; /*!< Reserved,                       Address offset: 0x18-0x20 */
+  __IO uint32_t ECCKEYR;     /*!< RAM ECC Key Register,                Address offset: 0x24 */
+  __IO uint32_t ERKEYR;      /*!< RAM Erase Key Register,              Address offset: 0x28 */
+}RAMCFG_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< RCC control register                                           Address offset: 0x0000 */
+  __IO uint32_t SR;               /*!< RCC status register                                            Address offset: 0x0004 */
+  __IO uint32_t STOPCR;           /*!< RCC Stop mode control register                                 Address offset: 0x0008 */
+       uint32_t RESERVED0[5];     /*!< Reserved                                                       Address offset: 0x000C-0x001C */
+  __IO uint32_t CFGR1;            /*!< RCC configuration register 1                                   Address offset: 0x0020 */
+  __IO uint32_t CFGR2;            /*!< RCC configuration register 2                                   Address offset: 0x0024 */
+       uint32_t RESERVED1;        /*!< Reserved                                                       Address offset: 0x0028 */
+  __IO uint32_t BDCR;             /*!< RCC backup domain protection register                          Address offset: 0x002C */
+  __IO uint32_t HWRSR;            /*!< RCC reset status register for hardware                         Address offset: 0x0030 */
+  __IO uint32_t RSR;              /*!< RCC reset register                                             Address offset: 0x0034 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                                       Address offset: 0x0038-0x003C */
+  __IO uint32_t LSECFGR;          /*!< RCC LSE configuration register                                 Address offset: 0x0040 */
+  __IO uint32_t MSICFGR;          /*!< RCC MSI configuration register                                 Address offset: 0x0044 */
+  __IO uint32_t HSICFGR;          /*!< RCC HSI configuration register                                 Address offset: 0x0048 */
+  __IO uint32_t HSIMCR;           /*!< RCC HSI Monitor control register                               Address offset: 0x004C */
+  __IO uint32_t HSIMSR;           /*!< RCC HSI Monitor status register                                Address offset: 0x0050 */
+  __IO uint32_t HSECFGR;          /*!< RCC HSE configuration register                                 Address offset: 0x0054 */
+       uint32_t RESERVED3[10];    /*!< Reserved                                                       Address offset: 0x0058-0x007C */
+  __IO uint32_t PLL1CFGR1;        /*!< RCC PLL1 configuration register 1                              Address offset: 0x0080 */
+  __IO uint32_t PLL1CFGR2;        /*!< RCC PLL1 configuration register 2                              Address offset: 0x0084 */
+  __IO uint32_t PLL1CFGR3;        /*!< RCC PLL1 configuration register 3                              Address offset: 0x0088 */
+       uint32_t RESERVED4;        /*!< Reserved                                                       Address offset: 0x008C */
+  __IO uint32_t PLL2CFGR1;        /*!< RCC PLL2 configuration register 1                              Address offset: 0x0090 */
+  __IO uint32_t PLL2CFGR2;        /*!< RCC PLL2 configuration register 2                              Address offset: 0x0094 */
+  __IO uint32_t PLL2CFGR3;        /*!< RCC PLL2 configuration register 3                              Address offset: 0x0098 */
+       uint32_t RESERVED5;        /*!< Reserved                                                       Address offset: 0x009C */
+  __IO uint32_t PLL3CFGR1;        /*!< RCC PLL3 configuration register 1                              Address offset: 0x00A0 */
+  __IO uint32_t PLL3CFGR2;        /*!< RCC PLL3 configuration register 2                              Address offset: 0x00A4 */
+  __IO uint32_t PLL3CFGR3;        /*!< RCC PLL3 configuration register 3                              Address offset: 0x00A8 */
+       uint32_t RESERVED6;        /*!< Reserved                                                       Address offset: 0x00AC */
+  __IO uint32_t PLL4CFGR1;        /*!< RCC PLL4 configuration register 1                              Address offset: 0x00B0 */
+  __IO uint32_t PLL4CFGR2;        /*!< RCC PLL4 configuration register 2                              Address offset: 0x00B4 */
+  __IO uint32_t PLL4CFGR3;        /*!< RCC PLL4 configuration register 3                              Address offset: 0x00B8 */
+       uint32_t RESERVED7[2];     /*!< Reserved                                                       Address offset: 0x00BC-0x00C0 */
+  __IO uint32_t IC1CFGR;          /*!< RCC IC1 configuration register                                 Address offset: 0x00C4 */
+  __IO uint32_t IC2CFGR;          /*!< RCC IC2 configuration register                                 Address offset: 0x00C8 */
+  __IO uint32_t IC3CFGR;          /*!< RCC IC3 configuration register                                 Address offset: 0x00CC */
+  __IO uint32_t IC4CFGR;          /*!< RCC IC4 configuration register                                 Address offset: 0x00D0 */
+  __IO uint32_t IC5CFGR;          /*!< RCC IC5 configuration register                                 Address offset: 0x00D4 */
+  __IO uint32_t IC6CFGR;          /*!< RCC IC6 configuration register                                 Address offset: 0x00D8 */
+  __IO uint32_t IC7CFGR;          /*!< RCC IC7 configuration register                                 Address offset: 0x00DC */
+  __IO uint32_t IC8CFGR;          /*!< RCC IC8 configuration register                                 Address offset: 0x00E0 */
+  __IO uint32_t IC9CFGR;          /*!< RCC IC9 configuration register                                 Address offset: 0x00E4 */
+  __IO uint32_t IC10CFGR;         /*!< RCC IC10 configuration register                                Address offset: 0x00E8 */
+  __IO uint32_t IC11CFGR;         /*!< RCC IC11 configuration register                                Address offset: 0x00EC */
+  __IO uint32_t IC12CFGR;         /*!< RCC IC12 configuration register                                Address offset: 0x00F0 */
+  __IO uint32_t IC13CFGR;         /*!< RCC IC13 configuration register                                Address offset: 0x00F4 */
+  __IO uint32_t IC14CFGR;         /*!< RCC IC14 configuration register                                Address offset: 0x00F8 */
+  __IO uint32_t IC15CFGR;         /*!< RCC IC15 configuration register                                Address offset: 0x00FC */
+  __IO uint32_t IC16CFGR;         /*!< RCC IC16 configuration register                                Address offset: 0x0100 */
+  __IO uint32_t IC17CFGR;         /*!< RCC IC17 configuration register                                Address offset: 0x0104 */
+  __IO uint32_t IC18CFGR;         /*!< RCC IC18 configuration register                                Address offset: 0x0108 */
+  __IO uint32_t IC19CFGR;         /*!< RCC IC19 configuration register                                Address offset: 0x010C */
+  __IO uint32_t IC20CFGR;         /*!< RCC IC20 configuration register                                Address offset: 0x0110 */
+       uint32_t RESERVED8[4];     /*!< Reserved                                                       Address offset: 0x0114-0x0120 */
+  __IO uint32_t CIER;             /*!< RCC clock-source interrupt enable register                     Address offset: 0x0124 */
+  __IO uint32_t CIFR;             /*!< RCC clock-source interrupt flag register                       Address offset: 0x0128 */
+  __IO uint32_t CICR;             /*!< RCC clock-source interrupt clear register                      Address offset: 0x012C */
+       uint32_t RESERVED9[5];     /*!< Reserved                                                       Address offset: 0x0130-0x0140 */
+  __IO uint32_t CCIPR1;           /*!< RCC clock configuration for independent peripheral register 1  Address offset: 0x0144 */
+  __IO uint32_t CCIPR2;           /*!< RCC clock configuration for independent peripheral register 2  Address offset: 0x0148 */
+  __IO uint32_t CCIPR3;           /*!< RCC clock configuration for independent peripheral register 3  Address offset: 0x014C */
+  __IO uint32_t CCIPR4;           /*!< RCC clock configuration for independent peripheral register 4  Address offset: 0x0150 */
+  __IO uint32_t CCIPR5;           /*!< RCC clock configuration for independent peripheral register 5  Address offset: 0x0154 */
+  __IO uint32_t CCIPR6;           /*!< RCC clock configuration for independent peripheral register 6  Address offset: 0x0158 */
+  __IO uint32_t CCIPR7;           /*!< RCC clock configuration for independent peripheral register 7  Address offset: 0x015C */
+  __IO uint32_t CCIPR8;           /*!< RCC clock configuration for independent peripheral register 8  Address offset: 0x0160 */
+  __IO uint32_t CCIPR9;           /*!< RCC clock configuration for independent peripheral register 9  Address offset: 0x0164 */
+       uint32_t RESERVED10[2];    /*!< Reserved                                                       Address offset: 0x0168-0x016C */
+  __IO uint32_t CCIPR12;          /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */
+  __IO uint32_t CCIPR13;          /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */
+  __IO uint32_t CCIPR14;          /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */
+       uint32_t RESERVED11[35];   /*!< Reserved                                                       Address offset: 0x017C-0x0204 */
+  __IO uint32_t MISCRSTR;         /*!< RCC miscellaneous configurations reset register                Address offset: 0x0208 */
+  __IO uint32_t MEMRSTR;          /*!< RCC embedded memories reset register                           Address offset: 0x020C */
+  __IO uint32_t AHB1RSTR;         /*!< RCC AHB1 reset register                                        Address offset: 0x0210 */
+  __IO uint32_t AHB2RSTR;         /*!< RCC AHB2 reset register                                        Address offset: 0x0214 */
+  __IO uint32_t AHB3RSTR;         /*!< RCC AHB3 reset register                                        Address offset: 0x0218 */
+  __IO uint32_t AHB4RSTR;         /*!< RCC AHB4 reset register                                        Address offset: 0x021C */
+  __IO uint32_t AHB5RSTR;         /*!< RCC AHB5 reset register                                        Address offset: 0x0220 */
+  __IO uint32_t APB1RSTR1;        /*!< RCC APB1 reset register 1                                      Address offset: 0x0224 */
+  __IO uint32_t APB1RSTR2;        /*!< RCC APB1 reset register 2                                      Address offset: 0x0228 */
+  __IO uint32_t APB2RSTR;         /*!< RCC APB2 reset register                                        Address offset: 0x022C */
+       uint32_t RESERVED12;       /*!< Reserved                                                       Address offset: 0x0230 */
+  __IO uint32_t APB4RSTR1;        /*!< RCC APB4 reset register 1                                      Address offset: 0x0234 */
+  __IO uint32_t APB4RSTR2;        /*!< RCC APB4 reset register 2                                      Address offset: 0x0238 */
+  __IO uint32_t APB5RSTR;         /*!< RCC APB5 reset register                                        Address offset: 0x023C */
+  __IO uint32_t DIVENR;           /*!< RCC IC dividers enable register                                Address offset: 0x0240 */
+  __IO uint32_t BUSENR;           /*!< RCC embedded buses enable register                             Address offset: 0x0244 */
+  __IO uint32_t MISCENR;          /*!< RCC miscellaneous configurations enable register               Address offset: 0x0248 */
+  __IO uint32_t MEMENR;           /*!< RCC embedded memories enable register                          Address offset: 0x024C */
+  __IO uint32_t AHB1ENR;          /*!< RCC AHB1 enable register                                       Address offset: 0x0250 */
+  __IO uint32_t AHB2ENR;          /*!< RCC AHB2 enable register                                       Address offset: 0x0254 */
+  __IO uint32_t AHB3ENR;          /*!< RCC AHB3 enable register                                       Address offset: 0x0258 */
+  __IO uint32_t AHB4ENR;          /*!< RCC AHB4 enable register                                       Address offset: 0x025C */
+  __IO uint32_t AHB5ENR;          /*!< RCC AHB5 enable register                                       Address offset: 0x0260 */
+  __IO uint32_t APB1ENR1;         /*!< RCC APB1 enable register 1                                     Address offset: 0x0264 */
+  __IO uint32_t APB1ENR2;         /*!< RCC APB1 enable register 2                                     Address offset: 0x0268 */
+  __IO uint32_t APB2ENR;          /*!< RCC APB2 enable register                                       Address offset: 0x026C */
+  __IO uint32_t APB3ENR;          /*!< RCC APB3 enable register                                       Address offset: 0x0270 */
+  __IO uint32_t APB4ENR1;         /*!< RCC APB4 enable register 1                                     Address offset: 0x0274 */
+  __IO uint32_t APB4ENR2;         /*!< RCC APB4 enable register 2                                     Address offset: 0x0278 */
+  __IO uint32_t APB5ENR;          /*!< RCC APB5 enable register                                       Address offset: 0x027C */
+       uint32_t RESERVED13;       /*!< Reserved                                                       Address offset: 0x0280 */
+  __IO uint32_t BUSLPENR;         /*!< RCC embedded buses sleep enable register                       Address offset: 0x0284 */
+  __IO uint32_t MISCLPENR;        /*!< RCC miscellaneous configurations sleep enable register         Address offset: 0x0288 */
+  __IO uint32_t MEMLPENR;         /*!< RCC embedded memories sleep enable register                    Address offset: 0x028C */
+  __IO uint32_t AHB1LPENR;        /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0290 */
+  __IO uint32_t AHB2LPENR;        /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0294 */
+  __IO uint32_t AHB3LPENR;        /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0298 */
+  __IO uint32_t AHB4LPENR;        /*!< RCC AHB4 sleep enable register                                 Address offset: 0x029C */
+  __IO uint32_t AHB5LPENR;        /*!< RCC AHB5 sleep enable register                                 Address offset: 0x02A0 */
+  __IO uint32_t APB1LPENR1;       /*!< RCC APB1 sleep enable register 1                               Address offset: 0x02A4 */
+  __IO uint32_t APB1LPENR2;       /*!< RCC APB1 sleep enable register 2                               Address offset: 0x02A8 */
+  __IO uint32_t APB2LPENR;        /*!< RCC APB2 sleep enable register                                 Address offset: 0x02AC */
+  __IO uint32_t APB3LPENR;        /*!< RCC APB3 sleep enable register                                 Address offset: 0x02B0 */
+  __IO uint32_t APB4LPENR1;       /*!< RCC APB4 sleep enable register 1                               Address offset: 0x02B4 */
+  __IO uint32_t APB4LPENR2;       /*!< RCC APB4 sleep enable register 2                               Address offset: 0x02B8 */
+  __IO uint32_t APB5LPENR;        /*!< RCC APB5 sleep enable register                                 Address offset: 0x02BC */
+       uint32_t RESERVED14[99];   /*!< Reserved                                                       Address offset: 0x02C0-0x0448 */
+  __IO uint32_t RDCR;             /*!< RCC reset duration control register                            Address offset: 0x044C */
+       uint32_t RESERVED15[204];  /*!< Reserved                                                       Address offset: 0x0450-0x077C */
+  __IO uint32_t SECCFGR0;         /*!< RCC oscillator secure configuration register 0                 Address offset: 0x0780 */
+  __IO uint32_t PRIVCFGR0;        /*!< RCC oscillator privilege configuration register 0              Address offset: 0x0784 */
+  __IO uint32_t LOCKCFGR0;        /*!< RCC oscillator lock configuration register 0                   Address offset: 0x0788 */
+  __IO uint32_t PUBCFGR0;         /*!< RCC oscillator public configuration register 0                 Address offset: 0x078C */
+  __IO uint32_t SECCFGR1;         /*!< RCC PLL secure configuration register 1                        Address offset: 0x0790 */
+  __IO uint32_t PRIVCFGR1;        /*!< RCC PLL privilege configuration register 1                     Address offset: 0x0794 */
+  __IO uint32_t LOCKCFGR1;        /*!< RCC PLL lock configuration register 1                          Address offset: 0x0798 */
+  __IO uint32_t PUBCFGR1;         /*!< RCC PLL public configuration register 1                        Address offset: 0x079C */
+  __IO uint32_t SECCFGR2;         /*!< RCC divider secure configuration register 2                    Address offset: 0x07A0 */
+  __IO uint32_t PRIVCFGR2;        /*!< RCC divider privilege configuration register 2                 Address offset: 0x07A4 */
+  __IO uint32_t LOCKCFGR2;        /*!< RCC divider lock configuration register 2                      Address offset: 0x07A8 */
+  __IO uint32_t PUBCFGR2;         /*!< RCC divider public configuration register 2                    Address offset: 0x07AC */
+  __IO uint32_t SECCFGR3;         /*!< RCC system secure configuration register 3                     Address offset: 0x07B0 */
+  __IO uint32_t PRIVCFGR3;        /*!< RCC system privilege configuration register 3                  Address offset: 0x07B4 */
+  __IO uint32_t LOCKCFGR3;        /*!< RCC system lock configuration register 3                       Address offset: 0x07B8 */
+  __IO uint32_t PUBCFGR3;         /*!< RCC system public configuration register 3                     Address offset: 0x07BC */
+  __IO uint32_t SECCFGR4;         /*!< RCC bus secure configuration register 4                        Address offset: 0x07C0 */
+  __IO uint32_t PRIVCFGR4;        /*!< RCC bus privilege configuration register 4                     Address offset: 0x07C4 */
+  __IO uint32_t LOCKCFGR4;        /*!< RCC bus lock configuration register 4                          Address offset: 0x07C8 */
+  __IO uint32_t PUBCFGR4;         /*!< RCC bus public configuration register 4                        Address offset: 0x07CC */
+  __IO uint32_t PUBCFGR5;         /*!< RCC bus public configuration register 4                        Address offset: 0x07D0 */
+       uint32_t RESERVED16[11];   /*!< Reserved                                                       Address offset: 0x07D4-0x07FC */
+  __IO uint32_t CSR;              /*!< RCC control Set register                                       Address offset: 0x0800 */
+       uint32_t RESERVED17;       /*!< Reserved                                                       Address offset: 0x0804 */
+  __IO uint32_t STOPCSR;          /*!< RCC STOPCSR configuration register                             Address offset: 0x0808 */
+       uint32_t RESERVED18[127];  /*!< Reserved                                                       Address offset: 0x080C-0x0A00 */
+  __IO uint32_t MISCRSTSR;        /*!< RCC miscellaneous reset register                               Address offset: 0x0A08 */
+  __IO uint32_t MEMRSTSR;         /*!< RCC memory reset register                                      Address offset: 0x0A0C */
+  __IO uint32_t AHB1RSTSR;        /*!< RCC AHB1 reset register                                        Address offset: 0x0A10 */
+  __IO uint32_t AHB2RSTSR;        /*!< RCC AHB2 reset register                                        Address offset: 0x0A14 */
+  __IO uint32_t AHB3RSTSR;        /*!< RCC AHB3 reset register                                        Address offset: 0x0A18 */
+  __IO uint32_t AHB4RSTSR;        /*!< RCC AHB4 reset register                                        Address offset: 0x0A1C */
+  __IO uint32_t AHB5RSTSR;        /*!< RCC AHB5 reset register                                        Address offset: 0x0A20 */
+  __IO uint32_t APB1RSTSR1;       /*!< RCC APB1 reset register 1                                      Address offset: 0x0A24 */
+  __IO uint32_t APB1RSTSR2;       /*!< RCC APB1 reset register 2                                      Address offset: 0x0A28 */
+  __IO uint32_t APB2RSTSR;        /*!< RCC APB2 reset register                                        Address offset: 0x0A2C */
+       uint32_t RESERVED19;       /*!< Reserved                                                       Address offset: 0x0A30 */
+  __IO uint32_t APB4RSTSR1;       /*!< RCC APB4 reset register 1                                      Address offset: 0x0A34 */
+  __IO uint32_t APB4RSTSR2;       /*!< RCC APB4 reset register 2                                      Address offset: 0x0A38 */
+  __IO uint32_t APB5RSTSR;        /*!< RCC APB5 reset register                                        Address offset: 0x0A3C */
+  __IO uint32_t DIVENSR;          /*!< RCC divider enable register                                    Address offset: 0x0A40 */
+  __IO uint32_t BUSENSR;          /*!< RCC bus enable register                                        Address offset: 0x0A44 */
+  __IO uint32_t MISCENSR;         /*!< RCC miscellaneous enable register                              Address offset: 0x0A48 */
+  __IO uint32_t MEMENSR;          /*!< RCC memory enable register                                     Address offset: 0x0A4C */
+  __IO uint32_t AHB1ENSR;         /*!< RCC AHB1 enable register                                       Address offset: 0x0A50 */
+  __IO uint32_t AHB2ENSR;         /*!< RCC AHB2 enable register                                       Address offset: 0x0A54 */
+  __IO uint32_t AHB3ENSR;         /*!< RCC AHB3 enable register                                       Address offset: 0x0A58 */
+  __IO uint32_t AHB4ENSR;         /*!< RCC AHB4 enable register                                       Address offset: 0x0A5C */
+  __IO uint32_t AHB5ENSR;         /*!< RCC AHB5 enable register                                       Address offset: 0x0A60 */
+  __IO uint32_t APB1ENSR1;        /*!< RCC APB1 enable register 1                                     Address offset: 0x0A64 */
+  __IO uint32_t APB1ENSR2;        /*!< RCC APB1 enable register 2                                     Address offset: 0x0A68 */
+  __IO uint32_t APB2ENSR;         /*!< RCC APB2 enable register                                       Address offset: 0x0A6C */
+  __IO uint32_t APB3ENSR;         /*!< RCC APB3 enable register                                       Address offset: 0x0A70 */
+  __IO uint32_t APB4ENSR1;        /*!< RCC APB4 enable register 1                                     Address offset: 0x0A74 */
+  __IO uint32_t APB4ENSR2;        /*!< RCC APB4 enable register 2                                     Address offset: 0x0A78 */
+  __IO uint32_t APB5ENSR;         /*!< RCC APB5 enable register                                       Address offset: 0x0A7C */
+       uint32_t RESERVED20;       /*!< Reserved                                                       Address offset: 0x0A80 */
+  __IO uint32_t BUSLPENSR;        /*!< RCC bus sleep enable register                                  Address offset: 0x0A84 */
+  __IO uint32_t MISCLPENSR;       /*!< RCC miscellaneous sleep enable register                        Address offset: 0x0A88 */
+  __IO uint32_t MEMLPENSR;        /*!< RCC memory sleep enable register                               Address offset: 0x0A8C */
+  __IO uint32_t AHB1LPENSR;       /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0A90 */
+  __IO uint32_t AHB2LPENSR;       /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0A94 */
+  __IO uint32_t AHB3LPENSR;       /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0A98 */
+  __IO uint32_t AHB4LPENSR;       /*!< RCC AHB4 sleep enable register                                 Address offset: 0x0A9C */
+  __IO uint32_t AHB5LPENSR;       /*!< RCC AHB5 sleep enable register                                 Address offset: 0x0AA0 */
+  __IO uint32_t APB1LPENSR1;      /*!< RCC APB1 sleep enable register 1                               Address offset: 0x0AA4 */
+  __IO uint32_t APB1LPENSR2;      /*!< RCC APB1 sleep enable register 2                               Address offset: 0x0AA8 */
+  __IO uint32_t APB2LPENSR;       /*!< RCC APB2 sleep enable register                                 Address offset: 0x0AAC */
+  __IO uint32_t APB3LPENSR;       /*!< RCC APB3 sleep enable register                                 Address offset: 0x0AB0 */
+  __IO uint32_t APB4LPENSR1;      /*!< RCC APB4 sleep enable register 1                               Address offset: 0x0AB4 */
+  __IO uint32_t APB4LPENSR2;      /*!< RCC APB4 sleep enable register 2                               Address offset: 0x0AB8 */
+  __IO uint32_t APB5LPENSR;       /*!< RCC APB5 sleep enable register                                 Address offset: 0x0ABC */
+       uint32_t RESERVED21[305];  /*!< Reserved                                                       Address offset: 0x0AC0-0x0F80 */
+  __IO uint32_t PRIVCFGSR0;       /*!< RCC oscillator privilege configuration set register 0          Address offset: 0x0F84 */
+       uint32_t RESERVED22;       /*!< Reserved                                                       Address offset: 0x0F88 */
+  __IO uint32_t PUBCFGSR0;        /*!< RCC oscillator public configuration set register 0             Address offset: 0x0F8C */
+       uint32_t RESERVED23;       /*!< Reserved                                                       Address offset: 0x0F90 */
+  __IO uint32_t PRIVCFGSR1;       /*!< RCC PLL privilege configuration set register 1                 Address offset: 0x0F94 */
+       uint32_t RESERVED24;       /*!< Reserved                                                       Address offset: 0x0F98 */
+  __IO uint32_t PUBCFGSR1;        /*!< RCC PLL public configuration set register 1                    Address offset: 0x0F9C */
+       uint32_t RESERVED25;       /*!< Reserved                                                       Address offset: 0x0FA0 */
+  __IO uint32_t PRIVCFGSR2;       /*!< RCC divider privilege configuration set register 2             Address offset: 0x0FA4 */
+       uint32_t RESERVED26;       /*!< Reserved                                                       Address offset: 0x0FA8 */
+  __IO uint32_t PUBCFGSR2;        /*!< RCC divider public configuration set register 2                Address offset: 0x0FAC */
+       uint32_t RESERVED27;       /*!< Reserved                                                       Address offset: 0x0FB0 */
+  __IO uint32_t PRIVCFGSR3;       /*!< RCC system privilege configuration set register 3              Address offset: 0x0FB4 */
+       uint32_t RESERVED28;       /*!< Reserved                                                       Address offset: 0x0FB8 */
+  __IO uint32_t PUBCFGSR3;        /*!< RCC system public configuration set register 3                 Address offset: 0x0FBC */
+       uint32_t RESERVED29;       /*!< Reserved                                                       Address offset: 0x0FC0 */
+  __IO uint32_t PRIVCFGSR4;       /*!< RCC privilege configuration set register 4                     Address offset: 0x0FC4 */
+       uint32_t RESERVED30;       /*!< Reserved                                                       Address offset: 0x0FC8 */
+  __IO uint32_t PUBCFGSR4;        /*!< RCC public configuration set register 4                            Address offset: 0x0FCC */
+  __IO uint32_t PUBCFGSR5;        /*!< RCC public configuration set register 5                            Address offset: 0x0FD0 */
+       uint32_t RESERVED31[11];   /*!< Reserved                                                       Address offset: 0x0FD4-0x0FFC */
+  __IO uint32_t CCR;              /*!< RCC control clear register                                     Address offset: 0x1000 */
+       uint32_t RESERVED32;       /*!< Reserved                                                       Address offset: 0x1004 */
+  __IO uint32_t STOPCCR;          /*!< RCC Stop mode configuration clear register                     Address offset: 0x1008 */
+       uint32_t RESERVED33[127];  /*!< Reserved                                                       Address offset: 0x100C-0x1200 */
+  __IO uint32_t MISCRSTCR;        /*!< RCC miscellaneous reset clear register                         Address offset: 0x1208 */
+  __IO uint32_t MEMRSTCR;         /*!< RCC memory reset clear register                                Address offset: 0x120C */
+  __IO uint32_t AHB1RSTCR;        /*!< RCC AHB1 reset clear register                                  Address offset: 0x1210 */
+  __IO uint32_t AHB2RSTCR;        /*!< RCC AHB2 reset clear register                                  Address offset: 0x1214 */
+  __IO uint32_t AHB3RSTCR;        /*!< RCC AHB3 reset r clear register                                Address offset: 0x1218 */
+  __IO uint32_t AHB4RSTCR;        /*!< RCC AHB4 reset clear register                                  Address offset: 0x121C */
+  __IO uint32_t AHB5RSTCR;        /*!< RCC AHB5 reset clear register                                  Address offset: 0x1220 */
+  __IO uint32_t APB1RSTCR1;       /*!< RCC APB1 reset clear register 1                                Address offset: 0x1224 */
+  __IO uint32_t APB1RSTCR2;       /*!< RCC APB1 reset clear register 2                                Address offset: 0x1228 */
+  __IO uint32_t APB2RSTCR;        /*!< RCC APB2 reset clear register                                  Address offset: 0x122C */
+       uint32_t RESERVED34;       /*!< Reserved                                                       Address offset: 0x1230 */
+  __IO uint32_t APB4RSTCR1;       /*!< RCC APB4 reset clear register 1                                Address offset: 0x1234 */
+  __IO uint32_t APB4RSTCR2;       /*!< RCC APB4 reset clear register 2                                Address offset: 0x1238 */
+  __IO uint32_t APB5RSTCR;        /*!< RCC APB5 reset clear register                                  Address offset: 0x123C */
+  __IO uint32_t DIVENCR;          /*!< RCC divider enable clear register                              Address offset: 0x1240 */
+  __IO uint32_t BUSENCR;          /*!< RCC bus enable clear register                                  Address offset: 0x1244 */
+  __IO uint32_t MISCENCR;         /*!< RCC miscellaneous enable clear register                        Address offset: 0x1248 */
+  __IO uint32_t MEMENCR;          /*!< RCC memory enable clear register                               Address offset: 0x124C */
+  __IO uint32_t AHB1ENCR;         /*!< RCC AHB1 enable clear register                                 Address offset: 0x1250 */
+  __IO uint32_t AHB2ENCR;         /*!< RCC AHB2 enable clear register                                 Address offset: 0x1254 */
+  __IO uint32_t AHB3ENCR;         /*!< RCC AHB3 enable clear register                                 Address offset: 0x1258 */
+  __IO uint32_t AHB4ENCR;         /*!< RCC AHB4 enable clear register                                 Address offset: 0x125C */
+  __IO uint32_t AHB5ENCR;         /*!< RCC AHB5 enable clear register                                 Address offset: 0x1260 */
+  __IO uint32_t APB1ENCR1;        /*!< RCC APB1 enable clear register 1                               Address offset: 0x1264 */
+  __IO uint32_t APB1ENCR2;        /*!< RCC APB1 enable clear register 2                               Address offset: 0x1268 */
+  __IO uint32_t APB2ENCR;         /*!< RCC APB2 enable clear register                                 Address offset: 0x126C */
+  __IO uint32_t APB3ENCR;         /*!< RCC APB3 enable clear register                                 Address offset: 0x1270 */
+  __IO uint32_t APB4ENCR1;        /*!< RCC APB4 enable clear register 1                               Address offset: 0x1274 */
+  __IO uint32_t APB4ENCR2;        /*!< RCC APB4 enable clear register 2                               Address offset: 0x1278 */
+  __IO uint32_t APB5ENCR;         /*!< RCC APB5 enable clear register                                 Address offset: 0x127C */
+       uint32_t RESERVED35;       /*!< Reserved                                                       Address offset: 0x1280 */
+  __IO uint32_t BUSLPENCR;        /*!< RCC bus sleep enable clear register                            Address offset: 0x1284 */
+  __IO uint32_t MISCLPENCR;       /*!< RCC miscellaneous sleep enable clear register                  Address offset: 0x1288 */
+  __IO uint32_t MEMLPENCR;        /*!< RCC memory sleep enable clear register                         Address offset: 0x128C */
+  __IO uint32_t AHB1LPENCR;       /*!< RCC AHB1 sleep enable clear register                           Address offset: 0x1290 */
+  __IO uint32_t AHB2LPENCR;       /*!< RCC AHB2 sleep enable clear register                           Address offset: 0x1294 */
+  __IO uint32_t AHB3LPENCR;       /*!< RCC AHB3 sleep enable clear register                           Address offset: 0x1298 */
+  __IO uint32_t AHB4LPENCR;       /*!< RCC AHB4 sleep enable clear register                           Address offset: 0x129C */
+  __IO uint32_t AHB5LPENCR;       /*!< RCC AHB5 sleep enable clear register                           Address offset: 0x12A0 */
+  __IO uint32_t APB1LPENCR1;      /*!< RCC APB1 sleep enable clear register 1                         Address offset: 0x12A4 */
+  __IO uint32_t APB1LPENCR2;      /*!< RCC APB1 sleep enable clear register 2                         Address offset: 0x12A8 */
+  __IO uint32_t APB2LPENCR;       /*!< RCC APB2 sleep enable clear register                           Address offset: 0x12AC */
+  __IO uint32_t APB3LPENCR;       /*!< RCC APB3 sleep enable clear register                           Address offset: 0x12B0 */
+  __IO uint32_t APB4LPENCR1;      /*!< RCC APB4 sleep enable clear register 1                         Address offset: 0x12B4 */
+  __IO uint32_t APB4LPENCR2;      /*!< RCC APB4 sleep enable clear register 2                         Address offset: 0x12B8 */
+  __IO uint32_t APB5LPENCR;       /*!< RCC APB5 sleep enable clear register                           Address offset: 0x12BC */
+       uint32_t RESERVED36[305];  /*!< Reserved                                                       Address offset: 0x12C0-0x1780 */
+  __IO uint32_t PRIVCFGCR0;       /*!< RCC oscillator privilege configuration clear register 0        Address offset: 0x1784 */
+       uint32_t RESERVED37;       /*!< Reserved                                                       Address offset: 0x1788 */
+  __IO uint32_t PUBCFGCR0;        /*!< RCC oscillator public configuration clear register 0           Address offset: 0x178C */
+       uint32_t RESERVED38;       /*!< Reserved                                                       Address offset: 0x1790 */
+  __IO uint32_t PRIVCFGCR1;       /*!< RCC PLL privilege configuration clear register 1               Address offset: 0x1794 */
+       uint32_t RESERVED39;       /*!< Reserved                                                       Address offset: 0x1798 */
+  __IO uint32_t PUBCFGCR1;        /*!< RCC PLL public configuration clear register 1                  Address offset: 0x179C */
+       uint32_t RESERVED40;       /*!< Reserved                                                       Address offset: 0x17A0 */
+  __IO uint32_t PRIVCFGCR2;       /*!< RCC divider privilege configuration clear register 2           Address offset: 0x17A4 */
+       uint32_t RESERVED41;       /*!< Reserved                                                       Address offset: 0x17A8 */
+  __IO uint32_t PUBCFGCR2;        /*!< RCC divider public configuration clear register 2              Address offset: 0x17AC */
+       uint32_t RESERVED42;       /*!< Reserved                                                       Address offset: 0x17B0 */
+  __IO uint32_t PRIVCFGCR3;       /*!< RCC system privilege configuration clear register 3            Address offset: 0x17B4 */
+       uint32_t RESERVED43;       /*!< Reserved                                                       Address offset: 0x17B8 */
+  __IO uint32_t PUBCFGCR3;        /*!< RCC system public configuration clear register 3               Address offset: 0x17BC */
+       uint32_t RESERVED44;       /*!< Reserved                                                       Address offset: 0x17C0 */
+  __IO uint32_t PRIVCFGCR4;       /*!< RCC privilege configuration clear register 4                   Address offset: 0x17C4 */
+       uint32_t RESERVED45;       /*!< Reserved                                                       Address offset: 0x17C8 */
+  __IO uint32_t PUBCFGCR4;        /*!< RCC public configuration clear register 4                      Address offset: 0x17CC */
+  __IO uint32_t PUBCFGCR5;        /*!< RCC public configuration clear register 5                      Address offset: 0x17D0 */
+} RCC_TypeDef;
+
+/*
+ * @brief  RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1)
+ */
+typedef struct
+{
+  __IO uint32_t RISC_CR;            /*!< RIFSC RISC slave configuration register x               Address offset: 0x000 */
+       uint32_t RESERVED0[3];       /*!< Reserved                                                Address offset: 0x004-0x00C */
+  __IO uint32_t RISC_SECCFGRx[6];   /*!< RIFSC RISC slave security configuration register x      Address offset: 0x010-0x24 */
+       uint32_t RESERVED1[2];       /*!< Reserved                                                Address offset: 0x028-0x02C */
+  __IO uint32_t RISC_PRIVCFGRx[6];  /*!< RIFSC RISFC slave privileged register x                 Address offset: 0x030-0x44 */
+       uint32_t RESERVED2[2];       /*!< Reserved                                                Address offset: 0x048-0x04C */
+  __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */
+       uint32_t RESERVED3[742];     /*!< Reserved                                                Address offset: 0x068-0xBFC */
+  __IO uint32_t RIMC_CR;            /*!< RIFSC RIMC master configuration register                Address offset: 0xC00 */
+       uint32_t RESERVED4[3];       /*!< Reserved                                                Address offset: 0xC04-0xC0C */
+  __IO uint32_t RIMC_ATTRx[13];     /*!< RIFSC RIMC master attribute register x                  Address offset: 0xC10-0xC40 */
+       uint32_t RESERVED5[219];     /*!< Reserved                                                Address offset: 0xC40-0xFAC */
+  __IO uint32_t PPSRx[6];           /*!< RIFSC peripheral protection status register x           Address offset: 0xFB0-0xFC4 */
+       uint32_t RESERVED6[8];       /*!< Reserved                                                Address offset: 0xFC8-0xFE4 */
+} RIFSC_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version)
+  */
+typedef struct
+{
+  __IO uint32_t CFGR;          /*!< RISAF Region X configuration register             */
+  __IO uint32_t STARTR;        /*!< RISAF Region X start address register             */
+  __IO uint32_t ENDR;          /*!< RISAF Region X end address register               */
+  __IO uint32_t CIDCFGR;       /*!< RISAF Region X CID configuration register         */
+  __IO uint32_t ACFGR;         /*!< RISAF Region X subregion A configuration register */
+  __IO uint32_t ASTARTR;       /*!< RISAF Region X subregion A start address register */
+  __IO uint32_t AENDR;         /*!< RISAF Region X subregion A end address register   */
+  __IO uint32_t ANESTR;        /*!< RISAF Region X subregion A nested mode register   */
+  __IO uint32_t BCFGR;         /*!< RISAF Region X subregion B configuration register */
+  __IO uint32_t BSTARTR;       /*!< RISAF Region X subregion B start address register */
+  __IO uint32_t BENDR;         /*!< RISAF Region X subregion B end address register   */
+  __IO uint32_t BNESTR;        /*!< RISAF Region X subregion B nested mode register   */
+       uint32_t RESERVED0[4];  /*!< Reserved                                          */
+} RISAF_Region_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t IAESR;         /*!< RISAF Illegal access error status register */
+  __IO uint32_t IADDR;         /*!< RISAF Illegal address register,            */
+} RISAF_Illegal_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t              CR;            /*!< RISAF Configuration register,                            Address offset: 0x000 */
+  __IO uint32_t              RESERVED0;     /*!< Reserved,                                                Address offset: 0x004 */
+  __IO uint32_t              IASR;          /*!< RISAF Illegal access status register,                    Address offset: 0x008 */
+  __IO uint32_t              IACR;          /*!< RISAF Illegal access clear register,                     Address offset: 0x00C */
+       uint32_t              RESERVED1[4];  /*!< Reserved,                                                          0x010-0x01C */
+       RISAF_Illegal_TypeDef IAR[1];        /*!< RISAF Illegal access error status and address register,            0x020-0x024 */
+       uint32_t              RESERVED2[6];  /*!< Reserved,                                                          0x028-0x03C */
+       RISAF_Region_TypeDef  REG[15];       /*!< RISAF Region X configuration register,                             0x040-0x3FC */
+} RISAF_TypeDef;
+
+/**
+  * @brief RNG
+  */
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+  uint32_t RESERVED;
+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
+} RNG_TypeDef;
+
+/*
+* @brief RTC Specific device feature definitions
+*/
+#define RTC_BKP_NB         32U
+#define RTC_TAMP_NB        7U
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
+ __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
+ __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
+ __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
+ __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
+ __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
+ __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
+__IO uint32_t SECCFGR;      /*!< RTC secure mode control register,               Address offset: 0x20 */
+ __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
+ __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
+ __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
+ __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
+ __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
+ __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
+      uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
+ __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
+ __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
+ __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
+ __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
+ __IO uint32_t SMISR;       /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
+ __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
+      uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
+ __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
+ __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+typedef struct
+{
+  __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
+  uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
+  __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
+  __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,              Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,              Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                   Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                    Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,           Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                 Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                 Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                 Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                 Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                 Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,                Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,               Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,               Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,                     Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,            Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                       Address offset: 0x3C */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,      Address offset: 0x40 */
+  __IO uint32_t FIFOTHR;        /*!< SDMMC data FIFO threshold register,        Address offset: 0x44 */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x48 - 0x4C                                           */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,                Address offset: 0x50 */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,            Address offset: 0x54 */
+  __IO uint32_t IDMABASER;      /*!< SDMMC DMA buffer base address register,    Address offset: 0x58 */
+  uint32_t      RESERVED1[2];   /*!< Reserved, 0x5C - 0x60                                           */
+  __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,    Address offset: 0x64 */
+  __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
+  uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                  Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/**
+  * @brief SPI
+  */
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief UCPD
+  */
+typedef struct
+{
+  __IO uint32_t CFG1;        /*!< UCPD configuration register 1,            Address offset: 0x00 */
+  __IO uint32_t CFG2;        /*!< UCPD configuration register 2,            Address offset: 0x04 */
+  __IO uint32_t RESERVED0;   /*!< UCPD reserved register,                   Address offset: 0x08 */
+  __IO uint32_t CR;          /*!< UCPD control register,                    Address offset: 0x0C */
+  __IO uint32_t IMR;         /*!< UCPD interrupt mask register,             Address offset: 0x10 */
+  __IO uint32_t SR;          /*!< UCPD status register,                     Address offset: 0x14 */
+  __IO uint32_t ICR;         /*!< UCPD interrupt flag clear register        Address offset: 0x18 */
+  __IO uint32_t TX_ORDSET;   /*!< UCPD Tx ordered set type register,        Address offset: 0x1C */
+  __IO uint32_t TX_PAYSZ;    /*!< UCPD Tx payload size register,            Address offset: 0x20 */
+  __IO uint32_t TXDR;        /*!< UCPD Tx data register,                    Address offset: 0x24 */
+  __IO uint32_t RX_ORDSET;   /*!< UCPD Rx ordered set type register,        Address offset: 0x28 */
+  __IO uint32_t RX_PAYSZ;    /*!< UCPD Rx payload size register,            Address offset: 0x2C */
+  __IO uint32_t RXDR;        /*!< UCPD Rx data register,                    Address offset: 0x30 */
+  __IO uint32_t RX_ORDEXT1;  /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
+  __IO uint32_t RX_ORDEXT2;  /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
+} UCPD_TypeDef;
+
+/**
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;             /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t GOTGINT;             /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t GAHBCFG;             /*!< Core AHB Configuration Register,           Address offset: 008h */
+  __IO uint32_t GUSBCFG;             /*!< Core USB Configuration Register,           Address offset: 00Ch */
+  __IO uint32_t GRSTCTL;             /*!< Core Reset Register,                       Address offset: 010h */
+  __IO uint32_t GINTSTS;             /*!< Core Interrupt Register,                   Address offset: 014h */
+  __IO uint32_t GINTMSK;             /*!< Core Interrupt Mask Register,              Address offset: 018h */
+  __IO uint32_t GRXSTSR;             /*!< Receive Sts Q Read Register,               Address offset: 01Ch */
+  __IO uint32_t GRXSTSP;             /*!< Receive Sts Q Read & POP Register,         Address offset: 020h */
+  __IO uint32_t GRXFSIZ;             /*!< Receive FIFO Size Register,                Address offset: 024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;  /*!< EP0 / Non Periodic Tx FIFO Size Register,  Address offset: 028h */
+  __IO uint32_t HNPTXSTS;            /*!< Non Periodic Tx FIFO/Queue Sts reg,        Address offset: 02Ch */
+  __IO uint32_t Reserved30[2];       /*!< Reserved,                                  Address offset: 030h */
+  __IO uint32_t GCCFG;               /*!< General Purpose IO Register,               Address offset: 038h */
+  __IO uint32_t CID;                 /*!< User ID Register,                          Address offset: 03Ch */
+  __IO uint32_t GSNPSID;             /*!< USB_OTG core ID,                           Address offset: 040h */
+  __IO uint32_t GHWCFG1;             /*!< User HW config1,                           Address offset: 044h */
+  __IO uint32_t GHWCFG2;             /*!< User HW config2,                           Address offset: 048h */
+  __IO uint32_t GHWCFG3;             /*!< User HW config3,                           Address offset: 04Ch */
+  __IO uint32_t Reserved6;           /*!< Reserved,                                  Address offset: 050h */
+  __IO uint32_t GLPMCFG;             /*!< LPM Register,                              Address offset: 054h */
+  __IO uint32_t GPWRDN;              /*!< Power Down Register,                       Address offset: 058h */
+  __IO uint32_t GDFIFOCFG;           /*!< DFIFO Software Config Register,            Address offset: 05Ch */
+  __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register,    Address offset: 60Ch */
+  __IO uint32_t Reserved43[39];      /*!< Reserved,                                  Address offset: 058h */
+  __IO uint32_t HPTXFSIZ;            /*!< Host Periodic Tx FIFO Size Reg,            Address offset: 100h */
+  __IO uint32_t DIEPTXF[0x0F];       /*!< dev Periodic Transmit FIFO                 Address offset: 104h */
+} USB_OTG_GlobalTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;          /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;     /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;     /*!< Core AHB Configuration Register,           Address offset: 008h */
+} USB_PHY_GlobalTypeDef;
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;                /*!< dev Configuration Register,   Address offset: 800h */
+  __IO uint32_t DCTL;                /*!< dev Control Register,         Address offset: 804h */
+  __IO uint32_t DSTS;                /*!< dev Status Register (RO),     Address offset: 808h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                     Address offset: 80Ch */
+  __IO uint32_t DIEPMSK;             /*!< dev IN Endpoint Mask,         Address offset: 810h */
+  __IO uint32_t DOEPMSK;             /*!< dev OUT Endpoint Mask,        Address offset: 814h */
+  __IO uint32_t DAINT;               /*!< dev All Endpoints Itr Reg,    Address offset: 818h */
+  __IO uint32_t DAINTMSK;            /*!< dev All Endpoints Itr Mask,   Address offset: 81Ch */
+  __IO uint32_t Reserved20;          /*!< Reserved,                     Address offset: 820h */
+  __IO uint32_t Reserved9;           /*!< Reserved,                     Address offset: 824h */
+  __IO uint32_t DVBUSDIS;            /*!< dev VBUS discharge Register,  Address offset: 828h */
+  __IO uint32_t DVBUSPULSE;          /*!< dev VBUS Pulse Register,      Address offset: 82Ch */
+  __IO uint32_t DTHRCTL;             /*!< dev threshold,                Address offset: 830h */
+  __IO uint32_t DIEPEMPMSK;          /*!< dev empty msk,                Address offset: 834h */
+  __IO uint32_t DEACHINT;            /*!< dedicated EP interrupt,       Address offset: 838h */
+  __IO uint32_t DEACHMSK;            /*!< dedicated EP msk,             Address offset: 83Ch */
+  __IO uint32_t Reserved40;          /*!< dedicated EP mask,            Address offset: 840h */
+  __IO uint32_t DINEP1MSK;           /*!< dedicated EP mask,            Address offset: 844h */
+  __IO uint32_t Reserved44[15];      /*!< Reserved,                     Address offset: 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;          /*!< dedicated EP msk,             Address offset: 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;             /*!< dev IN Endpoint Control Register,          Address offset: 900h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;             /*!< dev IN Endpoint Itr Register,              Address offset: 900h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;            /*!< IN Endpoint Txfer Size Register,           Address offset: 900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;             /*!< IN Endpoint DMA Address Register,          Address offset: 900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;             /*!< IN Endpoint Tx FIFO Status Register,       Address offset: 900h + (ep_num * 20h) + 18h */
+  __IO uint32_t Reserved18;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;             /*!< dev OUT Endpoint Control Register,         Address offset: B00h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;             /*!< dev OUT Endpoint Itr Register,             Address offset: B00h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;            /*!< dev OUT Endpoint Txfer Size Register,      Address offset: B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;             /*!< dev OUT Endpoint DMA Address Register,     Address offset: B00h + (ep_num * 20h) + 14h */
+  __IO uint32_t Reserved18[2];       /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 18h */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;                 /*!< Host Configuration Register,              Address offset: 400h */
+  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register,             Address offset: 404h */
+  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining,           Address offset: 408h */
+  __IO uint32_t Reserved40C;          /*!< Reserved,                                 Address offset: 40Ch */
+  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status,      Address offset: 410h */
+  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register,     Address offset: 414h */
+  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask,         Address offset: 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;               /*!< Host Channel Characteristics Register,    Address offset: 500h */
+  __IO uint32_t HCSPLT;               /*!< Host Channel Split Control Register,      Address offset: 504h */
+  __IO uint32_t HCINT;                /*!< Host Channel Interrupt Register,          Address offset: 508h */
+  __IO uint32_t HCINTMSK;             /*!< Host Channel Interrupt Mask Register,     Address offset: 50Ch */
+  __IO uint32_t HCTSIZ;               /*!< Host Channel Transfer Size Register,      Address offset: 510h */
+  __IO uint32_t HCDMA;                /*!< Host Channel DMA Address Register,        Address offset: 514h */
+  uint32_t Reserved[2];               /*!< Reserved,                                 Address offset: 518h */
+} USB_OTG_HostChannelTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;           /*!< USB HS PHY Control Register,              Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;      /*!< USB HS PHY Trimming_1 Register,           Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;      /*!< USB HS PHY Trimming_2 Register,           Address offset: 008h */
+} USB_HS_PHYC_GlobalTypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t IMR;         /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t IFCR;        /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t DR;          /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t CSR;         /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t DIR;         /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t BOOTCR;         /*!< SYSCFG boot pin control register,                                            Address offset: 0x00 */
+  __IO uint32_t CM55CR;         /*!< SYSCFG Cortex-M55 control register,                                          Address offset: 0x04 */
+  __IO uint32_t CM55TCMCR;      /*!< SYSCFG Cortex-M55 TCM control register,                                      Address offset: 0x08 */
+  __IO uint32_t CM55RWMCR;      /*!< SYSCFG Cortex-M55 memory RW margin register,                                 Address offset: 0x0C */
+  __IO uint32_t INITSVTORCR;    /*!< SYSCFG Cortex-M55 SVTOR control register,                                    Address offset: 0x10 */
+  __IO uint32_t INITNSVTORCR;   /*!< Cortex-M55 NSVTOR control register,                                          Address offset: 0x14 */
+  __IO uint32_t CM55RSTCR;      /*!< SYSCFG Cortex-M55 reset type control register,                               Address offset: 0x18 */
+  __IO uint32_t CM55PAHBWPR;    /*!< SYSCFG Cortex-M55 P-AHB write posting control register,                      Address offset: 0x1C */
+  __IO uint32_t VENCRAMCR;      /*!< SYSCFG VENCRAM control register,                                             Address offset: 0x20 */
+  __IO uint32_t POTTAMPRSTCR;   /*!< SYSCFG potential tamper reset register,                                      Address offset: 0x24 */
+  uint32_t      RESERVED1[3];   /*!< Reserved,                                                                    Address offset: 0x28-0x30 */
+  __IO uint32_t ICNEWRCR;       /*!< SYSCFG AHB-AXI bridge early write response,                                  Address offset: 0x34 */
+  __IO uint32_t ICNCGCR;        /*!< SYSCFG ICN clock gating control register,                                    Address offset: 0x38 */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                                                    Address offset: 0x3C-0x40 */
+  __IO uint32_t VDDIO2CCCR;     /*!< SYSCFG VDDIO2 compensation cell control register,                            Address offset: 0x44 */
+  __IO uint32_t VDDIO2CCSR;     /*!< SYSCFG VDDIO2 compensation cell status register,                             Address offset: 0x48 */
+  __IO uint32_t VDDIO3CCCR;     /*!< SYSCFG VDDIO3 compensation cell control register,                            Address offset: 0x4C */
+  __IO uint32_t VDDIO3CCSR;     /*!< SYSCFG VDDIO3 compensation cell status register,                             Address offset: 0x50 */
+  __IO uint32_t VDDIO4CCCR;     /*!< SYSCFG VDDIO4 compensation cell control register,                            Address offset: 0x54 */
+  __IO uint32_t VDDIO4CCSR;     /*!< SYSCFG VDDIO4 compensation cell status register,                             Address offset: 0x58 */
+  __IO uint32_t VDDIO5CCCR;     /*!< SYSCFG VDDIO5 compensation cell control register,                            Address offset: 0x5C */
+  __IO uint32_t VDDIO5CCSR;     /*!< SYSCFG VDDIO5 compensation cell status register,                             Address offset: 0x60 */
+  __IO uint32_t VDDCCCR;        /*!< SYSCFG VDD compensation cell control register,                               Address offset: 0x64 */
+  __IO uint32_t VDDCCSR;        /*!< SYSCFG VDD compensation cell status register,                                Address offset: 0x68 */
+  __IO uint32_t CBR;            /*!< SYSCFG control timer break register,                                         Address offset: 0x6C */
+  __IO uint32_t SEC_AIDCR;      /*!< SYSCFG DMA CID secure control register,                                      Address offset: 0x70 */
+  __IO uint32_t FMC_RETIMECR;   /*!< SYSCFG FMC retiming logic control register,                                  Address offset: 0x74 */
+  uint32_t      RESERVED3[34];  /*!< Reserved,                                                                    Address offset: 0x78-0xFC */
+  __IO uint32_t BOOTSR;         /*!< SYSCFG boot pin status register,                                             Address offset: 0x100 */
+  __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register,                             Address offset: 0x104 */
+  uint32_t      RESERVED4[446]; /*!< Reserved,                                                                    Address offset: 0x108-0x3FC */
+  __IO uint32_t SECPRIV_AIDCR;  /*!< SYSCFG DMA CID non-secure control register,                                  Address offset: 0x800 */
+  uint32_t      RESERVED5[507]; /*!< Reserved,                                                                    Address offset: 0x804-0xFEC */
+  __IO uint32_t DEVICEID;       /*!< SYSCFG Device ID,                                                            Address offset: 0xFF0 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Tamper and backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1;           /*!< TAMP configuration register 1,                    Address offset: 0x00 */
+ __IO uint32_t CR2;           /*!< TAMP configuration register 2,                    Address offset: 0x04 */
+ __IO uint32_t CR3;           /*!< TAMP configuration register 3,                    Address offset: 0x08 */
+ __IO uint32_t FLTCR;         /*!< TAMP filter control register,                     Address offset: 0x0C */
+ __IO uint32_t ATCR1;         /*!< TAMP filter control register 1                    Address offset: 0x10 */
+ __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,                 Address offset: 0x14 */
+ __IO uint32_t ATOR;          /*!< TAMP active tamper output register,               Address offset: 0x18 */
+ __IO uint32_t ATCR2;         /*!< TAMP filter control register 2,                   Address offset: 0x1C */
+ __IO uint32_t SECCFGR;       /*!< TAMP secure mode control register,                Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR;      /*!< TAMP privilege mode control register,             Address offset: 0x24 */
+      uint32_t RESERVED2;     /*!< Reserved,                                         Address offset: 0x28 */
+ __IO uint32_t IER;           /*!< TAMP interrupt enable register,                   Address offset: 0x2C */
+ __IO uint32_t SR;            /*!< TAMP status register,                             Address offset: 0x30 */
+ __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,            Address offset: 0x34 */
+ __IO uint32_t SMISR;         /*!< TAMP secure masked interrupt status register,     Address offset: 0x38 */
+ __IO uint32_t SCR;           /*!< TAMP status clear register,                       Address offset: 0x3C */
+ __IO uint32_t COUNT1R;       /*!< TAMP monotonic counter register,                  Address offset: 0x40 */
+      uint32_t RESERVED4[3];  /*!< Reserved,                                         Address offset: 0x43 -- 0x4C */
+ __IO uint32_t OR;            /*!< TAMP option register,                             Address offset: 0x50 */
+ __IO uint32_t RPCFGR;        /*!< TAMP resources protection configuration register, Address offset: 0x54 */
+      uint32_t RESERVED5[42]; /*!< Reserved,                                         Address offset: 0x58 -- 0xFC */
+ __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                           Address offset: 0x100 */
+ __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                           Address offset: 0x104 */
+ __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                           Address offset: 0x108 */
+ __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                           Address offset: 0x10C */
+ __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                           Address offset: 0x110 */
+ __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                           Address offset: 0x114 */
+ __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                           Address offset: 0x118 */
+ __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                           Address offset: 0x11C */
+ __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                           Address offset: 0x120 */
+ __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                           Address offset: 0x124 */
+ __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                          Address offset: 0x128 */
+ __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                          Address offset: 0x12C */
+ __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                          Address offset: 0x130 */
+ __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                          Address offset: 0x134 */
+ __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                          Address offset: 0x138 */
+ __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                          Address offset: 0x13C */
+ __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                          Address offset: 0x140 */
+ __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                          Address offset: 0x144 */
+ __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                          Address offset: 0x148 */
+ __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                          Address offset: 0x14C */
+ __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                          Address offset: 0x150 */
+ __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                          Address offset: 0x154 */
+ __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                          Address offset: 0x158 */
+ __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                          Address offset: 0x15C */
+ __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                          Address offset: 0x160 */
+ __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                          Address offset: 0x164 */
+ __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                          Address offset: 0x168 */
+ __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                          Address offset: 0x16C */
+ __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                          Address offset: 0x170 */
+ __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                          Address offset: 0x174 */
+ __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                          Address offset: 0x178 */
+ __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                          Address offset: 0x17C */
+} TAMP_TypeDef;
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint32_t CR1;            /*!< TIM control register 1,                   Address offset:  0x00 */
+  __IO uint32_t CR2;            /*!< TIM control register 2,                   Address offset:  0x04 */
+  __IO uint32_t SMCR;           /*!< TIM slave mode control register,          Address offset:  0x08 */
+  __IO uint32_t DIER;           /*!< TIM DMA/interrupt enable register,        Address offset:  0x0C */
+  __IO uint32_t SR;             /*!< TIM status register,                      Address offset:  0x10 */
+  __IO uint32_t EGR;            /*!< TIM event generation register,            Address offset:  0x14 */
+  __IO uint32_t CCMR1;          /*!< TIM capture/compare mode register 1,      Address offset:  0x18 */
+  __IO uint32_t CCMR2;          /*!< TIM capture/compare mode register 2,      Address offset:  0x1C */
+  __IO uint32_t CCER;           /*!< TIM capture/compare enable register,      Address offset:  0x20 */
+  __IO uint32_t CNT;            /*!< TIM counter register,                     Address offset:  0x24 */
+  __IO uint32_t PSC;            /*!< TIM prescaler,                            Address offset:  0x28 */
+  __IO uint32_t ARR;            /*!< TIM auto-reload register,                 Address offset:  0x2C */
+  __IO uint32_t RCR;            /*!< TIM repetition counter register,          Address offset:  0x30 */
+  __IO uint32_t CCR1;           /*!< TIM capture/compare register 1,           Address offset:  0x34 */
+  __IO uint32_t CCR2;           /*!< TIM capture/compare register 2,           Address offset:  0x38 */
+  __IO uint32_t CCR3;           /*!< TIM capture/compare register 3,           Address offset:  0x3C */
+  __IO uint32_t CCR4;           /*!< TIM capture/compare register 4,           Address offset:  0x40 */
+  __IO uint32_t BDTR;           /*!< TIM break and dead-time register,         Address offset:  0x44 */
+  __IO uint32_t CCR5;           /*!< TIM capture/compare register 5,           Address offset:  0x48 */
+  __IO uint32_t CCR6;           /*!< TIM capture/compare register 6,           Address offset:  0x4C */
+  __IO uint32_t CCMR3;          /*!< TIM capture/compare mode register 3,      Address offset:  0x50 */
+  __IO uint32_t DTR2;           /*!< TIM deadtime register 2,                  Address offset:  0x54 */
+  __IO uint32_t ECR;            /*!< TIM encoder control register,             Address offset:  0x58 */
+  __IO uint32_t TISEL;          /*!< TIM Input Selection register,             Address offset:  0x5C */
+  __IO uint32_t AF1;            /*!< TIM alternate function option register 1, Address offset:  0x60 */
+  __IO uint32_t AF2;            /*!< TIM alternate function option register 2, Address offset:  0x64 */
+       uint32_t RESERVED1[221]; /*!< Reserved,                                            0x6C-0x3D8 */
+  __IO uint32_t DCR;            /*!< TIM DMA control register,                 Address offset: 0x3DC */
+  __IO uint32_t DMAR;           /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C */
+} USART_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief Window Watchdog
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,              Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,               Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief Extended-SPI Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI Control Register,                                Address offset: 0x000         */
+       uint32_t RESERVED1;      /*!< Reserved,                                             Address offset: 0x004         */
+  __IO uint32_t DCR1;           /*!< XSPI Device Configuration Register 1,                 Address offset: 0x008         */
+  __IO uint32_t DCR2;           /*!< XSPI Device Configuration Register 2,                 Address offset: 0x00C         */
+  __IO uint32_t DCR3;           /*!< XSPI Device Configuration Register 3,                 Address offset: 0x010         */
+  __IO uint32_t DCR4;           /*!< XSPI Device Configuration Register 4,                 Address offset: 0x014         */
+       uint32_t RESERVED2[2];   /*!< Reserved,                                             Address offset: 0x018 - 0x01C */
+  __IO uint32_t SR;             /*!< XSPI Status Register,                                 Address offset: 0x020         */
+  __IO uint32_t FCR;            /*!< XSPI Flag Clear Register,                             Address offset: 0x024         */
+       uint32_t RESERVED3[6];   /*!< Reserved,                                             Address offset: 0x028 - 0x03C */
+  __IO uint32_t DLR;            /*!< XSPI Data Length Register,                            Address offset: 0x040         */
+       uint32_t RESERVED4;      /*!< Reserved,                                             Address offset: 0x044         */
+  __IO uint32_t AR;             /*!< XSPI Address Register,                                Address offset: 0x048         */
+       uint32_t RESERVED5;      /*!< Reserved,                                             Address offset: 0x04C         */
+  __IO uint32_t DR;             /*!< XSPI Data Register,                                   Address offset: 0x050         */
+       uint32_t RESERVED6[11];  /*!< Reserved,                                             Address offset: 0x054 - 0x07C */
+  __IO uint32_t PSMKR;          /*!< XSPI Polling Status Mask Register,                    Address offset: 0x080         */
+       uint32_t RESERVED7;      /*!< Reserved,                                             Address offset: 0x084         */
+  __IO uint32_t PSMAR;          /*!< XSPI Polling Status Match Register,                   Address offset: 0x088         */
+       uint32_t RESERVED8;      /*!< Reserved,                                             Address offset: 0x08C         */
+  __IO uint32_t PIR;            /*!< XSPI Polling Interval Register,                       Address offset: 0x090         */
+       uint32_t RESERVED9[27];  /*!< Reserved,                                             Address offset: 0x094 - 0x0FC */
+  __IO uint32_t CCR;            /*!< XSPI Communication Configuration Register,            Address offset: 0x100         */
+       uint32_t RESERVED10;     /*!< Reserved,                                             Address offset: 0x104         */
+  __IO uint32_t TCR;            /*!< XSPI Timing Configuration Register,                   Address offset: 0x108         */
+       uint32_t RESERVED11;     /*!< Reserved,                                             Address offset: 0x10C         */
+  __IO uint32_t IR;             /*!< XSPI Instruction Register,                            Address offset: 0x110         */
+       uint32_t RESERVED12[3];  /*!< Reserved,                                             Address offset: 0x114 - 0x11C */
+  __IO uint32_t ABR;            /*!< XSPI Alternate Bytes Register,                        Address offset: 0x120         */
+       uint32_t RESERVED13[3];  /*!< Reserved,                                             Address offset: 0x124 - 0x12C */
+  __IO uint32_t LPTR;           /*!< XSPI Low-Power Timeout Register,                      Address offset: 0x130         */
+       uint32_t RESERVED14[3];  /*!< Reserved,                                             Address offset: 0x134 - 0x13C */
+  __IO uint32_t WPCCR;          /*!< XSPI Wrap Communication Configuration Register,       Address offset: 0x140         */
+       uint32_t RESERVED15;     /*!< Reserved,                                             Address offset: 0x144         */
+  __IO uint32_t WPTCR;          /*!< XSPI Wrap Timing Configuration Register,              Address offset: 0x148         */
+       uint32_t RESERVED16;     /*!< Reserved,                                             Address offset: 0x14C         */
+  __IO uint32_t WPIR;           /*!< XSPI Wrap Instruction Register,                       Address offset: 0x150         */
+       uint32_t RESERVED17[3];  /*!< Reserved,                                             Address offset: 0x154 - 0x15C */
+  __IO uint32_t WPABR;          /*!< XSPI Wrap Alternate Bytes Register,                   Address offset: 0x160         */
+       uint32_t RESERVED18[7];  /*!< Reserved,                                             Address offset: 0x164 - 0x17C */
+  __IO uint32_t WCCR;           /*!< XSPI Write Communication Configuration Register,      Address offset: 0x180         */
+       uint32_t RESERVED19;     /*!< Reserved,                                             Address offset: 0x184         */
+  __IO uint32_t WTCR;           /*!< XSPI Write Timing Configuration Register,             Address offset: 0x188         */
+       uint32_t RESERVED20;     /*!< Reserved,                                             Address offset: 0x18C         */
+  __IO uint32_t WIR;            /*!< XSPI Write Instruction Register,                      Address offset: 0x190         */
+       uint32_t RESERVED21[3];  /*!< Reserved,                                             Address offset: 0x194 - 0x19C */
+  __IO uint32_t WABR;           /*!< XSPI Write Alternate Bytes Register,                  Address offset: 0x1A0         */
+       uint32_t RESERVED22[23]; /*!< Reserved,                                             Address offset: 0x1A4 - 0x1FC */
+  __IO uint32_t HLCR;           /*!< XSPI HyperBus Latency Configuration Register,         Address offset: 0x200         */
+       uint32_t RESERVED23[3];  /*!< Reserved,                                             Address offset: 0x204 - 0x20C */
+  __IO uint32_t CALFCR;         /*!< XSPI Full-Cycle Calibration Configuration Register,   Address offset: 0x210         */
+       uint32_t RESERVED24;     /*!< Reserved,                                             Address offset: 0x214         */
+  __IO uint32_t CALMR;          /*!< XSPI DLL Master Calibration Configuration Register,   Address offset: 0x218         */
+       uint32_t RESERVED25;     /*!< Reserved,                                             Address offset: 0x21C         */
+  __IO uint32_t CALSOR;         /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220         */
+       uint32_t RESERVED26;     /*!< Reserved,                                             Address offset: 0x224         */
+  __IO uint32_t CALSIR;         /*!< XSPI Slave Input Calibration Configuration Register,  Address offset: 0x228         */
+} XSPI_TypeDef;
+
+/**
+  * @brief XSPI IO Manager
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI IO Manager Control Register,                     Address offset: 0x00        */
+} XSPIM_TypeDef;
+
+/** @} */ /* End of group STM32N6xx_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_peripheralAddr
+  * @{
+  */
+
+/* Internal RAMs sizes */
+#define SRAM1_AXI_SIZE                  0x100000UL   /*!< SRAM1_AXI = 1024 Kbytes */
+#define SRAM2_AXI_SIZE                  0x100000UL   /*!< SRAM2_AXI = 1024 Kbytes */
+#define FLEXRAM_SIZE                     0x64000UL   /*!< FLEXRAM <= 400 Kbytes   */
+#define SRAM3_AXI_SIZE                   0x70000UL   /*!< SRAM3_AXI = 448 Kbytes  */
+#define SRAM4_AXI_SIZE                   0x70000UL   /*!< SRAM4_AXI = 448 Kbytes  */
+#define SRAM5_AXI_SIZE                   0x70000UL   /*!< SRAM5_AXI = 448 Kbytes  */
+#define SRAM6_AXI_SIZE                   0x70000UL   /*!< SRAM6_AXI = 448 Kbytes  */
+#define SRAM1_AHB_SIZE                    0x4000UL   /*!< SRAM1_AHB = 16 Kbytes   */
+#define SRAM2_AHB_SIZE                    0x4000UL   /*!< SRAM2_AHB = 16 Kbytes   */
+#define VENC_RAM_SIZE                    0x20000UL   /*!< VENC RAM  = 128 Kbytes  */
+#define SRAM7_AXI_SIZE                   0x40000UL   /*!< SRAM7_AXI = 256 Kbytes  */
+#define BKPSRAM_SIZE                      0x2000UL   /*!< BKPSRAM  = 8 Kbytes     */
+
+
+#define FMC_BASE                        0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */
+#define FMC_BANK1                       FMC_BASE
+#define FMC_BANK1_1                     FMC_BANK1
+#define FMC_BANK1_2                     (FMC_BANK1 + 0x04000000UL)
+#define FMC_BANK1_3                     (FMC_BANK1 + 0x08000000UL)
+#define FMC_BANK1_4                     (FMC_BANK1 + 0x0C000000UL)
+#define FMC_BANK5                       0xC0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK5_1                     FMC_BANK5
+#define FMC_BANK5_2                     (FMC_BANK5 + 0x04000000UL)
+#define FMC_BANK5_3                     (FMC_BANK5 + 0x08000000UL)
+#define FMC_BANK5_4                     (FMC_BANK5 + 0x0C000000UL)
+#define FMC_BANK6                       0xD0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK6_1                     FMC_BANK6
+#define FMC_BANK6_2                     (FMC_BANK6 + 0x04000000UL)
+#define FMC_BANK6_3                     (FMC_BANK6 + 0x08000000UL)
+#define FMC_BANK6_4                     (FMC_BANK6 + 0x0C000000UL)
+#define XSPI1_BASE                      0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI    */
+#define XSPI2_BASE                      0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI    */
+#define XSPI3_BASE                      0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI    */
+
+/**************************************************************************/
+/*                                                                        */
+/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */
+/*                                                                        */
+/**************************************************************************/
+
+#define ITCM_BASE_NS                    0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_NS                 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_NS                    0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_NS               0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_NS               0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_NS               0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_NS               0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_NS               0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_NS               0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_NS                SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define SRAM7_AXI_BASE_NS               0x243C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */
+#define VENC_RAM_BASE_NS                0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS  0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS  0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS  0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS  0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_NS         0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_NS               0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_NS               0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_NS                SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */
+#define BKPSRAM_BASE_NS                 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge      */
+#define PERIPH_BASE_NS                  0x40000000UL /*!< Base address of : AHB/APB Peripherals                      */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_NS              PERIPH_BASE_NS
+#define AHB1PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00020000UL)
+#define APB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02000000UL)
+#define AHB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02020000UL)
+#define APB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04000000UL)
+#define AHB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04020000UL)
+#define APB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06000000UL)
+#define AHB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06020000UL)
+#define APB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08000000UL)
+#define AHB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0000UL)
+#define TIM3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0400UL)
+#define TIM4_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0800UL)
+#define TIM5_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0C00UL)
+#define TIM6_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1000UL)
+#define TIM7_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1400UL)
+#define TIM12_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1800UL)
+#define TIM13_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1C00UL)
+#define TIM14_BASE_NS                   (APB1PERIPH_BASE_NS + 0x2000UL)
+#define LPTIM1_BASE_NS                  (APB1PERIPH_BASE_NS + 0x2400UL)
+#define WWDG_BASE_NS                    (APB1PERIPH_BASE_NS + 0x2C00UL)
+#define TIM10_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3000UL)
+#define TIM11_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3400UL)
+#define SPI2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3800UL)
+#define SPI3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3C00UL)
+#define SPDIFRX_BASE_NS                 (APB1PERIPH_BASE_NS + 0x4000UL)
+#define USART2_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4400UL)
+#define USART3_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4800UL)
+#define UART4_BASE_NS                   (APB1PERIPH_BASE_NS + 0x4C00UL)
+#define UART5_BASE_NS                   (APB1PERIPH_BASE_NS + 0x5000UL)
+#define I2C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5400UL)
+#define I2C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5800UL)
+#define I2C3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5C00UL)
+#define I3C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6000UL)
+#define I3C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6400UL)
+#define UART7_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7800UL)
+#define UART8_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7C00UL)
+#define MDIOS_BASE_NS                   (APB1PERIPH_BASE_NS + 0x9400UL)
+#define FDCAN1_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA000UL)
+#define FDCAN_CONFIG_BASE_NS            (APB1PERIPH_BASE_NS + 0xA100UL)
+#define FDCAN2_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA400UL)
+#define FDCAN_CCU_BASE_NS               (APB1PERIPH_BASE_NS + 0xA800UL)
+#define SRAMCAN_BASE_NS                 (APB1PERIPH_BASE_NS + 0xC000UL)
+#define FDCAN3_BASE_NS                  (APB1PERIPH_BASE_NS + 0xE800UL)
+#define UCPD1_BASE_NS                   (APB1PERIPH_BASE_NS + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_NS                  (AHB1PERIPH_BASE_NS + 0x1000UL)
+#define GPDMA1_Channel0_BASE_NS         (GPDMA1_BASE_NS + 0x0050UL)
+#define GPDMA1_Channel1_BASE_NS         (GPDMA1_BASE_NS + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_NS         (GPDMA1_BASE_NS + 0x0150UL)
+#define GPDMA1_Channel3_BASE_NS         (GPDMA1_BASE_NS + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_NS         (GPDMA1_BASE_NS + 0x0250UL)
+#define GPDMA1_Channel5_BASE_NS         (GPDMA1_BASE_NS + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_NS         (GPDMA1_BASE_NS + 0x0350UL)
+#define GPDMA1_Channel7_BASE_NS         (GPDMA1_BASE_NS + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_NS         (GPDMA1_BASE_NS + 0x0450UL)
+#define GPDMA1_Channel9_BASE_NS         (GPDMA1_BASE_NS + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_NS        (GPDMA1_BASE_NS + 0x0550UL)
+#define GPDMA1_Channel11_BASE_NS        (GPDMA1_BASE_NS + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_NS        (GPDMA1_BASE_NS + 0x0650UL)
+#define GPDMA1_Channel13_BASE_NS        (GPDMA1_BASE_NS + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_NS        (GPDMA1_BASE_NS + 0x0750UL)
+#define GPDMA1_Channel15_BASE_NS        (GPDMA1_BASE_NS + 0x07D0UL)
+#define ADC1_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2000UL)
+#define ADC2_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2100UL)
+#define ADC12_COMMON_BASE_NS            (AHB1PERIPH_BASE_NS + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0000UL)
+#define TIM8_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0400UL)
+#define USART1_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1000UL)
+#define USART6_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1400UL)
+#define UART9_BASE_NS                   (APB2PERIPH_BASE_NS + 0x1800UL)
+#define USART10_BASE_NS                 (APB2PERIPH_BASE_NS + 0x1C00UL)
+#define SPI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3000UL)
+#define SPI4_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3400UL)
+#define TIM18_BASE_NS                   (APB2PERIPH_BASE_NS + 0x3C00UL)
+#define TIM15_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4000UL)
+#define TIM16_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4400UL)
+#define TIM17_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4800UL)
+#define TIM9_BASE_NS                    (APB2PERIPH_BASE_NS + 0x4C00UL)
+#define SPI5_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5000UL)
+#define SAI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5800UL)
+#define SAI1_Block_A_BASE_NS            (SAI1_BASE_NS + 0x0004UL)
+#define SAI1_Block_B_BASE_NS            (SAI1_BASE_NS + 0x0024UL)
+#define SAI2_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5C00UL)
+#define SAI2_Block_A_BASE_NS            (SAI2_BASE_NS + 0x0004UL)
+#define SAI2_Block_B_BASE_NS            (SAI2_BASE_NS + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_NS                  (AHB2PERIPH_BASE_NS + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_NS        (RAMCFG_BASE_NS)
+#define RAMCFG_SRAM2_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_NS         (RAMCFG_BASE_NS + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0500UL)
+#define MDF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x5000UL)
+#define MDF1_Filter0_BASE_NS            (MDF1_BASE_NS + 0x0080UL)
+#define MDF1_Filter1_BASE_NS            (MDF1_BASE_NS + 0x0100UL)
+#define MDF1_Filter2_BASE_NS            (MDF1_BASE_NS + 0x0180UL)
+#define MDF1_Filter3_BASE_NS            (MDF1_BASE_NS + 0x0200UL)
+#define MDF1_Filter4_BASE_NS            (MDF1_BASE_NS + 0x0280UL)
+#define MDF1_Filter5_BASE_NS            (MDF1_BASE_NS + 0x0300UL)
+#define ADF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x6000UL)
+#define ADF1_Filter0_BASE_NS            (ADF1_BASE_NS + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_NS                 (APB3PERIPH_BASE_NS + 0x0000UL)
+#define DBGMCU_BASE_NS                  (APB3PERIPH_BASE_NS + 0x1000UL)
+#define DFT_APB_BASE_NS                 (APB3PERIPH_BASE_NS + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x0000UL)
+#define HASH_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0400UL)
+#define HASH_DIGEST_BASE_NS             (AHB3PERIPH_BASE_NS + 0x0710UL)
+#define PKA_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x2000UL)
+#define RIFSC_BASE_NS                   (AHB3PERIPH_BASE_NS + 0x4000UL)
+#define RISAF1_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x6000UL)
+#define RISAF2_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x7000UL)
+#define RISAF3_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x8000UL)
+#define RISAF6_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xB000UL)
+#define RISAF7_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xC000UL)
+#define RISAF8_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xD000UL)
+#define RISAF9_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xE000UL)
+#define RISAF11_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x010000UL)
+#define RISAF12_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x011000UL)
+#define RISAF13_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x012000UL)
+#define RISAF14_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x013000UL)
+#define RISAF21_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x015000UL)
+#define RISAF22_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x016000UL)
+#define RISAF23_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_NS                     (APB4PERIPH_BASE_NS + 0x0800UL)
+#define LPUART1_BASE_NS                 (APB4PERIPH_BASE_NS + 0x0C00UL)
+#define SPI6_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1400UL)
+#define I2C4_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1C00UL)
+#define LPTIM2_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2400UL)
+#define LPTIM3_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2800UL)
+#define LPTIM4_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2C00UL)
+#define LPTIM5_BASE_NS                  (APB4PERIPH_BASE_NS + 0x3000UL)
+#define VREFBUF_BASE_NS                 (APB4PERIPH_BASE_NS + 0x3C00UL)
+#define RTC_BASE_NS                     (APB4PERIPH_BASE_NS + 0x4000UL)
+#define TAMP_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4400UL)
+#define IWDG_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4800UL)
+#define SERC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x7C00UL)
+#define SYSCFG_BASE_NS                  (APB4PERIPH_BASE_NS + 0x8000UL)
+#define BSEC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x9000UL)
+#define DTS_BASE_NS                     (APB4PERIPH_BASE_NS + 0xA000UL)
+#define DTS_Sensor0_BASE_NS             (DTS_BASE_NS + 0x0C0UL)
+#define DTS_Sensor1_BASE_NS             (DTS_BASE_NS + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0000UL)
+#define GPIOB_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0400UL)
+#define GPIOC_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0800UL)
+#define GPIOD_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0C00UL)
+#define GPIOE_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1000UL)
+#define GPIOF_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1400UL)
+#define GPIOG_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1800UL)
+#define GPIOH_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1C00UL)
+#define GPION_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3400UL)
+#define GPIOO_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3800UL)
+#define GPIOP_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3C00UL)
+#define GPIOQ_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x4000UL)
+#define PWR_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4800UL)
+#define CRC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4C00UL)
+#define EXTI_BASE_NS                    (AHB4PERIPH_BASE_NS + 0x5000UL)
+#define RCC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x1000UL)
+#define LTDC_Layer1_BASE_NS             (LTDC_BASE_NS + 0x0100UL)
+#define LTDC_Layer2_BASE_NS             (LTDC_BASE_NS + 0x0200UL)
+#define DCMIPP_BASE_NS                  (APB5PERIPH_BASE_NS + 0x2000UL)
+#define GFXTIM_BASE_NS                  (APB5PERIPH_BASE_NS + 0x4000UL)
+#define VENC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x5000UL)
+#define CSI_BASE_NS                     (APB5PERIPH_BASE_NS + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x0000UL)
+#define HPDMA1_Channel0_BASE_NS         (HPDMA1_BASE_NS + 0x0050UL)
+#define HPDMA1_Channel1_BASE_NS         (HPDMA1_BASE_NS + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_NS         (HPDMA1_BASE_NS + 0x0150UL)
+#define HPDMA1_Channel3_BASE_NS         (HPDMA1_BASE_NS + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_NS         (HPDMA1_BASE_NS + 0x0250UL)
+#define HPDMA1_Channel5_BASE_NS         (HPDMA1_BASE_NS + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_NS         (HPDMA1_BASE_NS + 0x0350UL)
+#define HPDMA1_Channel7_BASE_NS         (HPDMA1_BASE_NS + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_NS         (HPDMA1_BASE_NS + 0x0450UL)
+#define HPDMA1_Channel9_BASE_NS         (HPDMA1_BASE_NS + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_NS        (HPDMA1_BASE_NS + 0x0550UL)
+#define HPDMA1_Channel11_BASE_NS        (HPDMA1_BASE_NS + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_NS        (HPDMA1_BASE_NS + 0x0650UL)
+#define HPDMA1_Channel13_BASE_NS        (HPDMA1_BASE_NS + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_NS        (HPDMA1_BASE_NS + 0x0750UL)
+#define HPDMA1_Channel15_BASE_NS        (HPDMA1_BASE_NS + 0x07D0UL)
+#define DMA2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x1000UL)
+#define JPEG_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x3000UL)
+#define FMC_R_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x4000UL)
+#define FMC_Bank1_R_BASE_NS             (FMC_R_BASE_NS + 0x0000UL)
+#define FMC_Bank1E_R_BASE_NS            (FMC_R_BASE_NS + 0x0104UL)
+#define FMC_Bank3_R_BASE_NS             (FMC_R_BASE_NS + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_NS           (FMC_R_BASE_NS + 0x0140UL)
+#define FMC_Common_R_BASE_NS            (FMC_R_BASE_NS + 0x0020UL)
+#define XSPI1_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x5000UL)
+#define PSSI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x6400UL)
+#define SDMMC2_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x6800UL)
+#define DLYB_SDMMC2_BASE_NS             (AHB5PERIPH_BASE_NS + 0x6C00UL)
+#define SDMMC1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x7000UL)
+#define DLYB_SDMMC1_BASE_NS             (AHB5PERIPH_BASE_NS + 0x8000UL)
+#define DCMI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x8400UL)
+#define XSPI2_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xA000UL)
+#define XSPIM_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xB400UL)
+#define XSPI3_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xD000UL)
+#define GFXMMU_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x010000UL)
+#define GPU2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x014000UL)
+#define GPUCACHE_BASE_NS                (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ICACHE_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ETH1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x016000UL)
+#define ETH1_MAC_BASE_NS                (ETH1_BASE_NS)
+#define USB1_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x020000UL)
+#define USB2_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x060000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_NS                     (0x46009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_NS                   (BOOTROM_BASE_NS + 0x0047ECUL)
+
+
+#if defined (CPU_IN_SECURE_STATE)
+/*********************************************************************/
+/*                                                                   */
+/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */
+/*                                                                   */
+/*********************************************************************/
+#define ITCM_BASE_S                     0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_S                  0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_S                     0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_S                0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_S                0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_S                0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_S                0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_S                0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_S                0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_S                 SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define SRAM7_AXI_BASE_S                0x343C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */
+#define VENC_RAM_BASE_S                 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_S   0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_S   0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_S   0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_S   0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_S          0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_S                0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_S                0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_S                 SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge  */
+#define BKPSRAM_BASE_S                  0x3C000000UL   /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge    */
+#define PERIPH_BASE_S                   0x50000000UL   /*!< Base address of : AHB/APB Peripherals                    */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_S               PERIPH_BASE_S
+#define AHB1PERIPH_BASE_S               (PERIPH_BASE_S + 0x00020000UL)
+#define APB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02000000UL)
+#define AHB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02020000UL)
+#define APB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04000000UL)
+#define AHB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04020000UL)
+#define APB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06000000UL)
+#define AHB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06020000UL)
+#define APB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08000000UL)
+#define AHB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_S                     (APB1PERIPH_BASE_S + 0x0000UL)
+#define TIM3_BASE_S                     (APB1PERIPH_BASE_S + 0x0400UL)
+#define TIM4_BASE_S                     (APB1PERIPH_BASE_S + 0x0800UL)
+#define TIM5_BASE_S                     (APB1PERIPH_BASE_S + 0x0C00UL)
+#define TIM6_BASE_S                     (APB1PERIPH_BASE_S + 0x1000UL)
+#define TIM7_BASE_S                     (APB1PERIPH_BASE_S + 0x1400UL)
+#define TIM12_BASE_S                    (APB1PERIPH_BASE_S + 0x1800UL)
+#define TIM13_BASE_S                    (APB1PERIPH_BASE_S + 0x1C00UL)
+#define TIM14_BASE_S                    (APB1PERIPH_BASE_S + 0x2000UL)
+#define LPTIM1_BASE_S                   (APB1PERIPH_BASE_S + 0x2400UL)
+#define WWDG_BASE_S                     (APB1PERIPH_BASE_S + 0x2C00UL)
+#define TIM10_BASE_S                    (APB1PERIPH_BASE_S + 0x3000UL)
+#define TIM11_BASE_S                    (APB1PERIPH_BASE_S + 0x3400UL)
+#define SPI2_BASE_S                     (APB1PERIPH_BASE_S + 0x3800UL)
+#define SPI3_BASE_S                     (APB1PERIPH_BASE_S + 0x3C00UL)
+#define SPDIFRX_BASE_S                  (APB1PERIPH_BASE_S + 0x4000UL)
+#define USART2_BASE_S                   (APB1PERIPH_BASE_S + 0x4400UL)
+#define USART3_BASE_S                   (APB1PERIPH_BASE_S + 0x4800UL)
+#define UART4_BASE_S                    (APB1PERIPH_BASE_S + 0x4C00UL)
+#define UART5_BASE_S                    (APB1PERIPH_BASE_S + 0x5000UL)
+#define I2C1_BASE_S                     (APB1PERIPH_BASE_S + 0x5400UL)
+#define I2C2_BASE_S                     (APB1PERIPH_BASE_S + 0x5800UL)
+#define I2C3_BASE_S                     (APB1PERIPH_BASE_S + 0x5C00UL)
+#define I3C1_BASE_S                     (APB1PERIPH_BASE_S + 0x6000UL)
+#define I3C2_BASE_S                     (APB1PERIPH_BASE_S + 0x6400UL)
+#define UART7_BASE_S                    (APB1PERIPH_BASE_S + 0x7800UL)
+#define UART8_BASE_S                    (APB1PERIPH_BASE_S + 0x7C00UL)
+#define MDIOS_BASE_S                    (APB1PERIPH_BASE_S + 0x9400UL)
+#define FDCAN1_BASE_S                   (APB1PERIPH_BASE_S + 0xA000UL)
+#define FDCAN_CONFIG_BASE_S             (APB1PERIPH_BASE_S + 0xA100UL)
+#define FDCAN2_BASE_S                   (APB1PERIPH_BASE_S + 0xA400UL)
+#define FDCAN_CCU_BASE_S                (APB1PERIPH_BASE_S + 0xA800UL)
+#define SRAMCAN_BASE_S                  (APB1PERIPH_BASE_S + 0xC000UL)
+#define FDCAN3_BASE_S                   (APB1PERIPH_BASE_S + 0xE800UL)
+#define UCPD1_BASE_S                    (APB1PERIPH_BASE_S + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_S                   (AHB1PERIPH_BASE_S + 0x1000UL)
+#define GPDMA1_Channel0_BASE_S          (GPDMA1_BASE_S + 0x0050UL)
+#define GPDMA1_Channel1_BASE_S          (GPDMA1_BASE_S + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_S          (GPDMA1_BASE_S + 0x0150UL)
+#define GPDMA1_Channel3_BASE_S          (GPDMA1_BASE_S + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_S          (GPDMA1_BASE_S + 0x0250UL)
+#define GPDMA1_Channel5_BASE_S          (GPDMA1_BASE_S + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_S          (GPDMA1_BASE_S + 0x0350UL)
+#define GPDMA1_Channel7_BASE_S          (GPDMA1_BASE_S + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_S          (GPDMA1_BASE_S + 0x0450UL)
+#define GPDMA1_Channel9_BASE_S          (GPDMA1_BASE_S + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_S         (GPDMA1_BASE_S + 0x0550UL)
+#define GPDMA1_Channel11_BASE_S         (GPDMA1_BASE_S + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_S         (GPDMA1_BASE_S + 0x0650UL)
+#define GPDMA1_Channel13_BASE_S         (GPDMA1_BASE_S + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_S         (GPDMA1_BASE_S + 0x0750UL)
+#define GPDMA1_Channel15_BASE_S         (GPDMA1_BASE_S + 0x07D0UL)
+#define ADC1_BASE_S                     (AHB1PERIPH_BASE_S + 0x2000UL)
+#define ADC2_BASE_S                     (AHB1PERIPH_BASE_S + 0x2100UL)
+#define ADC12_COMMON_BASE_S             (AHB1PERIPH_BASE_S + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_S                     (APB2PERIPH_BASE_S + 0x0000UL)
+#define TIM8_BASE_S                     (APB2PERIPH_BASE_S + 0x0400UL)
+#define USART1_BASE_S                   (APB2PERIPH_BASE_S + 0x1000UL)
+#define USART6_BASE_S                   (APB2PERIPH_BASE_S + 0x1400UL)
+#define UART9_BASE_S                    (APB2PERIPH_BASE_S + 0x1800UL)
+#define USART10_BASE_S                  (APB2PERIPH_BASE_S + 0x1C00UL)
+#define SPI1_BASE_S                     (APB2PERIPH_BASE_S + 0x3000UL)
+#define SPI4_BASE_S                     (APB2PERIPH_BASE_S + 0x3400UL)
+#define TIM18_BASE_S                    (APB2PERIPH_BASE_S + 0x3C00UL)
+#define TIM15_BASE_S                    (APB2PERIPH_BASE_S + 0x4000UL)
+#define TIM16_BASE_S                    (APB2PERIPH_BASE_S + 0x4400UL)
+#define TIM17_BASE_S                    (APB2PERIPH_BASE_S + 0x4800UL)
+#define TIM9_BASE_S                     (APB2PERIPH_BASE_S + 0x4C00UL)
+#define SPI5_BASE_S                     (APB2PERIPH_BASE_S + 0x5000UL)
+#define SAI1_BASE_S                     (APB2PERIPH_BASE_S + 0x5800UL)
+#define SAI1_Block_A_BASE_S             (SAI1_BASE_S + 0x0004UL)
+#define SAI1_Block_B_BASE_S             (SAI1_BASE_S + 0x0024UL)
+#define SAI2_BASE_S                     (APB2PERIPH_BASE_S + 0x5C00UL)
+#define SAI2_Block_A_BASE_S             (SAI2_BASE_S + 0x0004UL)
+#define SAI2_Block_B_BASE_S             (SAI2_BASE_S + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_S                   (AHB2PERIPH_BASE_S + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_S         (RAMCFG_BASE_S)
+#define RAMCFG_SRAM2_AXI_BASE_S         (RAMCFG_BASE_S + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_S         (RAMCFG_BASE_S + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_S         (RAMCFG_BASE_S + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_S         (RAMCFG_BASE_S + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_S         (RAMCFG_BASE_S + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_S         (RAMCFG_BASE_S + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_S         (RAMCFG_BASE_S + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_S          (RAMCFG_BASE_S + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_S           (RAMCFG_BASE_S + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_S           (RAMCFG_BASE_S + 0x0500UL)
+#define MDF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x5000UL)
+#define MDF1_Filter0_BASE_S             (MDF1_BASE_S + 0x0080UL)
+#define MDF1_Filter1_BASE_S             (MDF1_BASE_S + 0x0100UL)
+#define MDF1_Filter2_BASE_S             (MDF1_BASE_S + 0x0180UL)
+#define MDF1_Filter3_BASE_S             (MDF1_BASE_S + 0x0200UL)
+#define MDF1_Filter4_BASE_S             (MDF1_BASE_S + 0x0280UL)
+#define MDF1_Filter5_BASE_S             (MDF1_BASE_S + 0x0300UL)
+#define ADF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x6000UL)
+#define ADF1_Filter0_BASE_S             (ADF1_BASE_S + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_S                  (APB3PERIPH_BASE_S + 0x0000UL)
+#define DBGMCU_BASE_S                   (APB3PERIPH_BASE_S + 0x1000UL)
+#define DFT_APB_BASE_S                  (APB3PERIPH_BASE_S + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_S                      (AHB3PERIPH_BASE_S + 0x0000UL)
+#define HASH_BASE_S                     (AHB3PERIPH_BASE_S + 0x0400UL)
+#define HASH_DIGEST_BASE_S              (AHB3PERIPH_BASE_S + 0x0710UL)
+#define PKA_BASE_S                      (AHB3PERIPH_BASE_S + 0x2000UL)
+#define RIFSC_BASE_S                    (AHB3PERIPH_BASE_S + 0x4000UL)
+#define IAC_BASE_S                      (AHB3PERIPH_BASE_S + 0x5000UL)
+#define RISAF1_BASE_S                   (AHB3PERIPH_BASE_S + 0x6000UL)
+#define RISAF2_BASE_S                   (AHB3PERIPH_BASE_S + 0x7000UL)
+#define RISAF3_BASE_S                   (AHB3PERIPH_BASE_S + 0x8000UL)
+#define RISAF6_BASE_S                   (AHB3PERIPH_BASE_S + 0xB000UL)
+#define RISAF7_BASE_S                   (AHB3PERIPH_BASE_S + 0xC000UL)
+#define RISAF8_BASE_S                   (AHB3PERIPH_BASE_S + 0xD000UL)
+#define RISAF9_BASE_S                   (AHB3PERIPH_BASE_S + 0xE000UL)
+#define RISAF11_BASE_S                  (AHB3PERIPH_BASE_S + 0x010000UL)
+#define RISAF12_BASE_S                  (AHB3PERIPH_BASE_S + 0x011000UL)
+#define RISAF13_BASE_S                  (AHB3PERIPH_BASE_S + 0x012000UL)
+#define RISAF14_BASE_S                  (AHB3PERIPH_BASE_S + 0x013000UL)
+#define RISAF21_BASE_S                  (AHB3PERIPH_BASE_S + 0x015000UL)
+#define RISAF22_BASE_S                  (AHB3PERIPH_BASE_S + 0x016000UL)
+#define RISAF23_BASE_S                  (AHB3PERIPH_BASE_S + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_S                      (APB4PERIPH_BASE_S + 0x0800UL)
+#define LPUART1_BASE_S                  (APB4PERIPH_BASE_S + 0x0C00UL)
+#define SPI6_BASE_S                     (APB4PERIPH_BASE_S + 0x1400UL)
+#define I2C4_BASE_S                     (APB4PERIPH_BASE_S + 0x1C00UL)
+#define LPTIM2_BASE_S                   (APB4PERIPH_BASE_S + 0x2400UL)
+#define LPTIM3_BASE_S                   (APB4PERIPH_BASE_S + 0x2800UL)
+#define LPTIM4_BASE_S                   (APB4PERIPH_BASE_S + 0x2C00UL)
+#define LPTIM5_BASE_S                   (APB4PERIPH_BASE_S + 0x3000UL)
+#define VREFBUF_BASE_S                  (APB4PERIPH_BASE_S + 0x3C00UL)
+#define RTC_BASE_S                      (APB4PERIPH_BASE_S + 0x4000UL)
+#define TAMP_BASE_S                     (APB4PERIPH_BASE_S + 0x4400UL)
+#define IWDG_BASE_S                     (APB4PERIPH_BASE_S + 0x4800UL)
+
+#define SERC_BASE_S                     (APB4PERIPH_BASE_S + 0x7C00UL)
+#define SYSCFG_BASE_S                   (APB4PERIPH_BASE_S + 0x8000UL)
+#define BSEC_BASE_S                     (APB4PERIPH_BASE_S + 0x9000UL)
+#define DTS_BASE_S                      (APB4PERIPH_BASE_S + 0xA000UL)
+#define DTS_Sensor0_BASE_S              (DTS_BASE_S + 0x0C0UL)
+#define DTS_Sensor1_BASE_S              (DTS_BASE_S + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_S                    (AHB4PERIPH_BASE_S + 0x0000UL)
+#define GPIOB_BASE_S                    (AHB4PERIPH_BASE_S + 0x0400UL)
+#define GPIOC_BASE_S                    (AHB4PERIPH_BASE_S + 0x0800UL)
+#define GPIOD_BASE_S                    (AHB4PERIPH_BASE_S + 0x0C00UL)
+#define GPIOE_BASE_S                    (AHB4PERIPH_BASE_S + 0x1000UL)
+#define GPIOF_BASE_S                    (AHB4PERIPH_BASE_S + 0x1400UL)
+#define GPIOG_BASE_S                    (AHB4PERIPH_BASE_S + 0x1800UL)
+#define GPIOH_BASE_S                    (AHB4PERIPH_BASE_S + 0x1C00UL)
+#define GPION_BASE_S                    (AHB4PERIPH_BASE_S + 0x3400UL)
+#define GPIOO_BASE_S                    (AHB4PERIPH_BASE_S + 0x3800UL)
+#define GPIOP_BASE_S                    (AHB4PERIPH_BASE_S + 0x3C00UL)
+#define GPIOQ_BASE_S                    (AHB4PERIPH_BASE_S + 0x4000UL)
+#define PWR_BASE_S                      (AHB4PERIPH_BASE_S + 0x4800UL)
+#define CRC_BASE_S                      (AHB4PERIPH_BASE_S + 0x4C00UL)
+#define EXTI_BASE_S                     (AHB4PERIPH_BASE_S + 0x5000UL)
+#define RCC_BASE_S                      (AHB4PERIPH_BASE_S + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_S                     (APB5PERIPH_BASE_S + 0x1000UL)
+#define LTDC_Layer1_BASE_S              (LTDC_BASE_S + 0x0100UL)
+#define LTDC_Layer2_BASE_S              (LTDC_BASE_S + 0x0200UL)
+#define DCMIPP_BASE_S                   (APB5PERIPH_BASE_S + 0x2000UL)
+#define GFXTIM_BASE_S                   (APB5PERIPH_BASE_S + 0x4000UL)
+#define VENC_BASE_S                     (APB5PERIPH_BASE_S + 0x5000UL)
+#define CSI_BASE_S                      (APB5PERIPH_BASE_S + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_S                   (AHB5PERIPH_BASE_S + 0x0000UL)
+#define HPDMA1_Channel0_BASE_S          (HPDMA1_BASE_S + 0x0050UL)
+#define HPDMA1_Channel1_BASE_S          (HPDMA1_BASE_S + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_S          (HPDMA1_BASE_S + 0x0150UL)
+#define HPDMA1_Channel3_BASE_S          (HPDMA1_BASE_S + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_S          (HPDMA1_BASE_S + 0x0250UL)
+#define HPDMA1_Channel5_BASE_S          (HPDMA1_BASE_S + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_S          (HPDMA1_BASE_S + 0x0350UL)
+#define HPDMA1_Channel7_BASE_S          (HPDMA1_BASE_S + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_S          (HPDMA1_BASE_S + 0x0450UL)
+#define HPDMA1_Channel9_BASE_S          (HPDMA1_BASE_S + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_S         (HPDMA1_BASE_S + 0x0550UL)
+#define HPDMA1_Channel11_BASE_S         (HPDMA1_BASE_S + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_S         (HPDMA1_BASE_S + 0x0650UL)
+#define HPDMA1_Channel13_BASE_S         (HPDMA1_BASE_S + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_S         (HPDMA1_BASE_S + 0x0750UL)
+#define HPDMA1_Channel15_BASE_S         (HPDMA1_BASE_S + 0x07D0UL)
+#define DMA2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x1000UL)
+#define JPEG_BASE_S                     (AHB5PERIPH_BASE_S + 0x3000UL)
+#define FMC_R_BASE_S                    (AHB5PERIPH_BASE_S + 0x4000UL)
+#define FMC_Bank1_R_BASE_S              (FMC_R_BASE_S + 0x0000UL)
+#define FMC_Bank1E_R_BASE_S             (FMC_R_BASE_S + 0x0104UL)
+#define FMC_Bank3_R_BASE_S              (FMC_R_BASE_S + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_S            (FMC_R_BASE_S + 0x0140UL)
+#define FMC_Common_R_BASE_S             (FMC_R_BASE_S + 0x0020UL)
+#define XSPI1_BASE_S                    (AHB5PERIPH_BASE_S + 0x5000UL)
+#define PSSI_BASE_S                     (AHB5PERIPH_BASE_S + 0x6400UL)
+#define SDMMC2_BASE_S                   (AHB5PERIPH_BASE_S + 0x6800UL)
+#define DLYB_SDMMC2_BASE_S              (AHB5PERIPH_BASE_S + 0x6C00UL)
+#define SDMMC1_BASE_S                   (AHB5PERIPH_BASE_S + 0x7000UL)
+#define DLYB_SDMMC1_BASE_S              (AHB5PERIPH_BASE_S + 0x8000UL)
+#define DCMI_BASE_S                     (AHB5PERIPH_BASE_S + 0x8400UL)
+#define XSPI2_BASE_S                    (AHB5PERIPH_BASE_S + 0xA000UL)
+#define XSPIM_BASE_S                    (AHB5PERIPH_BASE_S + 0xB400UL)
+#define XSPI3_BASE_S                    (AHB5PERIPH_BASE_S + 0xD000UL)
+#define GFXMMU_BASE_S                   (AHB5PERIPH_BASE_S + 0x010000UL)
+#define GPU2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x014000UL)
+#define GPUCACHE_BASE_S                 (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ICACHE_BASE_S                   (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ETH1_BASE_S                     (AHB5PERIPH_BASE_S + 0x016000UL)
+#define ETH1_MAC_BASE_S                 (ETH1_BASE_S)
+#define USB1_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x020000UL)
+#define USB2_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x060000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_S                      (0x56009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_S                    (BOOTROM_BASE_S + 0x0047ECUL)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_declaration
+  * @{
+  */
+#define ADC12_COMMON_NS           ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
+#define ADC1_NS                   ((ADC_TypeDef *) ADC1_BASE_NS)
+#define ADC2_NS                   ((ADC_TypeDef *) ADC2_BASE_NS)
+#define ADF1_NS                   ((MDF_TypeDef *) ADF1_BASE_NS)
+#define ADF1_Filter0_NS           ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS)
+#define BSEC_NS                   ((BSEC_TypeDef *) BSEC_BASE_NS)
+#define CRC_NS                    ((CRC_TypeDef *) CRC_BASE_NS)
+#define CSI_NS                    ((CSI_TypeDef *) CSI_BASE_NS)
+#define DBGMCU_NS                 ((DBGMCU_TypeDef *) DBGMCU_BASE_NS)
+#define DCMI_NS                   ((DCMI_TypeDef *) DCMI_BASE_NS)
+#define DCMIPP_NS                 ((DCMIPP_TypeDef *) DCMIPP_BASE_NS)
+#define DLYB_SDMMC1_NS            ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
+#define DLYB_SDMMC2_NS            ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
+#define DMA2D_NS                  ((DMA2D_TypeDef *) DMA2D_BASE_NS)
+#define DTS_NS                    ((DTS_TypeDef *) DTS_BASE_NS)
+#define DTS_Sensor0_NS            ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS)
+#define DTS_Sensor1_NS            ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS)
+#define ETH1_NS                   ((ETH_TypeDef *) ETH1_BASE_NS)
+#define EXTI_NS                   ((EXTI_TypeDef *) EXTI_BASE_NS)
+#define FDCAN1_NS                 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
+#define FDCAN2_NS                 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS)
+#define FDCAN3_NS                 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS)
+#define FDCAN_CCU_NS              ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS)
+#define FDCAN_CONFIG_NS           ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
+#define FMC_Bank1E_R_NS           ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
+#define FMC_Bank1_R_NS            ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
+#define FMC_Bank3_R_NS            ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
+#define FMC_Bank5_6_R_NS          ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS)
+#define FMC_Common_R_NS           ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS)
+#define GFXMMU_NS                 ((GFXMMU_TypeDef *) GFXMMU_BASE_NS)
+#define GFXTIM_NS                 ((GFXTIM_TypeDef *) GFXTIM_BASE_NS)
+#define GPDMA1_NS                 ((DMA_TypeDef *) GPDMA1_BASE_NS)
+#define GPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
+#define GPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
+#define GPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
+#define GPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
+#define GPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
+#define GPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
+#define GPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
+#define GPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
+#define GPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
+#define GPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
+#define GPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
+#define GPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
+#define GPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
+#define GPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
+#define GPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
+#define GPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
+#define GPIOA_NS                  ((GPIO_TypeDef *) GPIOA_BASE_NS)
+#define GPIOB_NS                  ((GPIO_TypeDef *) GPIOB_BASE_NS)
+#define GPIOC_NS                  ((GPIO_TypeDef *) GPIOC_BASE_NS)
+#define GPIOD_NS                  ((GPIO_TypeDef *) GPIOD_BASE_NS)
+#define GPIOE_NS                  ((GPIO_TypeDef *) GPIOE_BASE_NS)
+#define GPIOF_NS                  ((GPIO_TypeDef *) GPIOF_BASE_NS)
+#define GPIOG_NS                  ((GPIO_TypeDef *) GPIOG_BASE_NS)
+#define GPIOH_NS                  ((GPIO_TypeDef *) GPIOH_BASE_NS)
+#define GPION_NS                  ((GPIO_TypeDef *) GPION_BASE_NS)
+#define GPIOO_NS                  ((GPIO_TypeDef *) GPIOO_BASE_NS)
+#define GPIOP_NS                  ((GPIO_TypeDef *) GPIOP_BASE_NS)
+#define GPIOQ_NS                  ((GPIO_TypeDef *) GPIOQ_BASE_NS)
+#define HASH_NS                   ((HASH_TypeDef *) HASH_BASE_NS)
+#define HASH_DIGEST_NS            ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
+#define HPDMA1_NS                 ((DMA_TypeDef *) HPDMA1_BASE_NS)
+#define HPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS)
+#define HPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS)
+#define HPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS)
+#define HPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS)
+#define HPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS)
+#define HPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS)
+#define HPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS)
+#define HPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS)
+#define HPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS)
+#define HPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS)
+#define HPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS)
+#define HPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS)
+#define HPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS)
+#define HPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS)
+#define HPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS)
+#define HPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS)
+#define I2C1_NS                   ((I2C_TypeDef *) I2C1_BASE_NS)
+#define I2C2_NS                   ((I2C_TypeDef *) I2C2_BASE_NS)
+#define I2C3_NS                   ((I2C_TypeDef *) I2C3_BASE_NS)
+#define I2C4_NS                   ((I2C_TypeDef *) I2C4_BASE_NS)
+#define I3C1_NS                   ((I3C_TypeDef *) I3C1_BASE_NS)
+#define I3C2_NS                   ((I3C_TypeDef *) I3C2_BASE_NS)
+#define ICACHE_NS                 ((ICACHE_TypeDef *) ICACHE_BASE_NS)
+#define IWDG_NS                   ((IWDG_TypeDef *) IWDG_BASE_NS)
+#define JPEG_NS                   ((JPEG_TypeDef *) JPEG_BASE_NS)
+#define LPTIM1_NS                 ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
+#define LPTIM2_NS                 ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
+#define LPTIM3_NS                 ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
+#define LPTIM4_NS                 ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
+#define LPTIM5_NS                 ((LPTIM_TypeDef *) LPTIM5_BASE_NS)
+#define LPUART1_NS                ((USART_TypeDef *) LPUART1_BASE_NS)
+#define LTDC_NS                   ((LTDC_TypeDef *)LTDC_BASE_NS)
+#define LTDC_Layer1_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS)
+#define LTDC_Layer2_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS)
+#define MDF1_NS                   ((MDF_TypeDef *) MDF1_BASE_NS)
+#define MDF1_Filter0_NS           ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS)
+#define MDF1_Filter1_NS           ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS)
+#define MDF1_Filter2_NS           ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS)
+#define MDF1_Filter3_NS           ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS)
+#define MDF1_Filter4_NS           ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS)
+#define MDF1_Filter5_NS           ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS)
+#define MDIOS_NS                  ((MDIOS_TypeDef *) MDIOS_BASE_NS)
+#define PKA_NS                    ((PKA_TypeDef *) PKA_BASE_NS)
+#define PSSI_NS                   ((PSSI_TypeDef *) PSSI_BASE_NS)
+#define PWR_NS                    ((PWR_TypeDef *) PWR_BASE_NS)
+#define RAMCFG_NS                 ((RAMCFG_TypeDef *) RAMCFG_BASE_NS)
+#define RAMCFG_SRAM1_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS)
+#define RAMCFG_SRAM2_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS)
+#define RAMCFG_SRAM3_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS)
+#define RAMCFG_SRAM4_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS)
+#define RAMCFG_SRAM5_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS)
+#define RAMCFG_SRAM6_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS)
+#define RAMCFG_SRAM1_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS)
+#define RAMCFG_SRAM2_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS)
+#define RAMCFG_VENC_RAM_NS        ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS)
+#define RAMCFG_FLEXRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS)
+#define RCC_NS                    ((RCC_TypeDef *) RCC_BASE_NS)
+#define RIFSC_NS                  ((RIFSC_TypeDef *) RIFSC_BASE_NS)
+#define RISAF1_NS                 ((RISAF_TypeDef *) RISAF1_BASE_NS)
+#define RISAF2_NS                 ((RISAF_TypeDef *) RISAF2_BASE_NS)
+#define RISAF3_NS                 ((RISAF_TypeDef *) RISAF3_BASE_NS)
+#define RISAF6_NS                 ((RISAF_TypeDef *) RISAF6_BASE_NS)
+#define RISAF7_NS                 ((RISAF_TypeDef *) RISAF7_BASE_NS)
+#define RISAF8_NS                 ((RISAF_TypeDef *) RISAF8_BASE_NS)
+#define RISAF9_NS                 ((RISAF_TypeDef *) RISAF9_BASE_NS)
+#define RISAF11_NS                ((RISAF_TypeDef *) RISAF11_BASE_NS)
+#define RISAF12_NS                ((RISAF_TypeDef *) RISAF12_BASE_NS)
+#define RISAF13_NS                ((RISAF_TypeDef *) RISAF13_BASE_NS)
+#define RISAF14_NS                ((RISAF_TypeDef *) RISAF14_BASE_NS)
+#define RISAF21_NS                ((RISAF_TypeDef *) RISAF21_BASE_NS)
+#define RISAF22_NS                ((RISAF_TypeDef *) RISAF22_BASE_NS)
+#define RISAF23_NS                ((RISAF_TypeDef *) RISAF23_BASE_NS)
+#define RNG_NS                    ((RNG_TypeDef *) RNG_BASE_NS)
+#define RTC_NS                    ((RTC_TypeDef *) RTC_BASE_NS)
+#define SAI1_NS                   ((SAI_TypeDef *) SAI1_BASE_NS)
+#define SAI1_Block_A_NS           ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS)
+#define SAI1_Block_B_NS           ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS)
+#define SAI2_NS                   ((SAI_TypeDef *) SAI2_BASE_NS)
+#define SAI2_Block_A_NS           ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS)
+#define SAI2_Block_B_NS           ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS)
+#define SDMMC1_NS                 ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
+#define SDMMC2_NS                 ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
+#define SPDIFRX_NS                ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS)
+#define SPI1_NS                   ((SPI_TypeDef *) SPI1_BASE_NS)
+#define SPI2_NS                   ((SPI_TypeDef *) SPI2_BASE_NS)
+#define SPI3_NS                   ((SPI_TypeDef *) SPI3_BASE_NS)
+#define SPI4_NS                   ((SPI_TypeDef *) SPI4_BASE_NS)
+#define SPI5_NS                   ((SPI_TypeDef *) SPI5_BASE_NS)
+#define SPI6_NS                   ((SPI_TypeDef *) SPI6_BASE_NS)
+#define SYSCFG_NS                 ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
+#define TAMP_NS                   ((TAMP_TypeDef *) TAMP_BASE_NS)
+#define TIM1_NS                   ((TIM_TypeDef *) TIM1_BASE_NS)
+#define TIM2_NS                   ((TIM_TypeDef *) TIM2_BASE_NS)
+#define TIM3_NS                   ((TIM_TypeDef *) TIM3_BASE_NS)
+#define TIM4_NS                   ((TIM_TypeDef *) TIM4_BASE_NS)
+#define TIM5_NS                   ((TIM_TypeDef *) TIM5_BASE_NS)
+#define TIM6_NS                   ((TIM_TypeDef *) TIM6_BASE_NS)
+#define TIM7_NS                   ((TIM_TypeDef *) TIM7_BASE_NS)
+#define TIM8_NS                   ((TIM_TypeDef *) TIM8_BASE_NS)
+#define TIM9_NS                   ((TIM_TypeDef *) TIM9_BASE_NS)
+#define TIM10_NS                  ((TIM_TypeDef *) TIM10_BASE_NS)
+#define TIM11_NS                  ((TIM_TypeDef *) TIM11_BASE_NS)
+#define TIM12_NS                  ((TIM_TypeDef *) TIM12_BASE_NS)
+#define TIM13_NS                  ((TIM_TypeDef *) TIM13_BASE_NS)
+#define TIM14_NS                  ((TIM_TypeDef *) TIM14_BASE_NS)
+#define TIM15_NS                  ((TIM_TypeDef *) TIM15_BASE_NS)
+#define TIM16_NS                  ((TIM_TypeDef *) TIM16_BASE_NS)
+#define TIM17_NS                  ((TIM_TypeDef *) TIM17_BASE_NS)
+#define TIM18_NS                  ((TIM_TypeDef *) TIM18_BASE_NS)
+#define UART4_NS                  ((USART_TypeDef *) UART4_BASE_NS)
+#define UART5_NS                  ((USART_TypeDef *) UART5_BASE_NS)
+#define UART7_NS                  ((USART_TypeDef *) UART7_BASE_NS)
+#define UART8_NS                  ((USART_TypeDef *) UART8_BASE_NS)
+#define UART9_NS                  ((USART_TypeDef *) UART9_BASE_NS)
+#define UCPD1_NS                  ((UCPD_TypeDef *) UCPD1_BASE_NS)
+#define USART1_NS                 ((USART_TypeDef *) USART1_BASE_NS)
+#define USART2_NS                 ((USART_TypeDef *) USART2_BASE_NS)
+#define USART3_NS                 ((USART_TypeDef *) USART3_BASE_NS)
+#define USART6_NS                 ((USART_TypeDef *) USART6_BASE_NS)
+#define USART10_NS                ((USART_TypeDef *) USART10_BASE_NS)
+#define USB1_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS)
+#define USB2_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS)
+#define USB1_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS)
+#define USB2_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS)
+#define VENC_NS                   ((VENC_TypeDef *) VENC_BASE_NS)
+#define VREFBUF_NS                ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
+#define WWDG_NS                   ((WWDG_TypeDef *) WWDG_BASE_NS)
+#define XSPI1_NS                  ((XSPI_TypeDef *) XSPI1_BASE_NS)
+#define XSPI2_NS                  ((XSPI_TypeDef *) XSPI2_BASE_NS)
+#define XSPI3_NS                  ((XSPI_TypeDef *) XSPI3_BASE_NS)
+#define XSPIM_NS                  ((XSPIM_TypeDef *) XSPIM_BASE_NS)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON_S            ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
+#define ADC1_S                    ((ADC_TypeDef *) ADC1_BASE_S)
+#define ADC2_S                    ((ADC_TypeDef *) ADC2_BASE_S)
+#define ADF1_S                    ((MDF_TypeDef *) ADF1_BASE_S)
+#define ADF1_Filter0_S            ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S)
+#define BSEC_S                    ((BSEC_TypeDef *) BSEC_BASE_S)
+#define CRC_S                     ((CRC_TypeDef *) CRC_BASE_S)
+#define CSI_S                     ((CSI_TypeDef *) CSI_BASE_S)
+#define DBGMCU_S                  ((DBGMCU_TypeDef *) DBGMCU_BASE_S)
+#define DCMI_S                    ((DCMI_TypeDef *) DCMI_BASE_S)
+#define DCMIPP_S                  ((DCMIPP_TypeDef *) DCMIPP_BASE_S)
+#define DLYB_SDMMC1_S             ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
+#define DLYB_SDMMC2_S             ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
+#define DMA2D_S                   ((DMA2D_TypeDef *) DMA2D_BASE_S)
+#define DTS_S                     ((DTS_TypeDef *) DTS_BASE_S)
+#define DTS_Sensor0_S             ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S)
+#define DTS_Sensor1_S             ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S)
+#define ETH1_S                    ((ETH_TypeDef *) ETH1_BASE_S)
+#define EXTI_S                    ((EXTI_TypeDef *) EXTI_BASE_S)
+#define FDCAN1_S                  ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
+#define FDCAN2_S                  ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S)
+#define FDCAN3_S                  ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S)
+#define FDCAN_CCU_S               ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S)
+#define FDCAN_CONFIG_S            ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
+#define FMC_Bank1E_R_S            ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
+#define FMC_Bank1_R_S             ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
+#define FMC_Bank3_R_S             ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
+#define FMC_Bank5_6_R_S           ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S)
+#define FMC_Common_R_S            ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S)
+#define GFXMMU_S                  ((GFXMMU_TypeDef *) GFXMMU_BASE_S)
+#define GFXTIM_S                  ((GFXTIM_TypeDef *) GFXTIM_BASE_S)
+#define GPDMA1_S                  ((DMA_TypeDef *) GPDMA1_BASE_S)
+#define GPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
+#define GPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
+#define GPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
+#define GPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
+#define GPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
+#define GPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
+#define GPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
+#define GPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
+#define GPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
+#define GPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
+#define GPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
+#define GPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
+#define GPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
+#define GPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
+#define GPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
+#define GPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
+#define GPIOA_S                   ((GPIO_TypeDef *) GPIOA_BASE_S)
+#define GPIOB_S                   ((GPIO_TypeDef *) GPIOB_BASE_S)
+#define GPIOC_S                   ((GPIO_TypeDef *) GPIOC_BASE_S)
+#define GPIOD_S                   ((GPIO_TypeDef *) GPIOD_BASE_S)
+#define GPIOE_S                   ((GPIO_TypeDef *) GPIOE_BASE_S)
+#define GPIOF_S                   ((GPIO_TypeDef *) GPIOF_BASE_S)
+#define GPIOG_S                   ((GPIO_TypeDef *) GPIOG_BASE_S)
+#define GPIOH_S                   ((GPIO_TypeDef *) GPIOH_BASE_S)
+#define GPION_S                   ((GPIO_TypeDef *) GPION_BASE_S)
+#define GPIOO_S                   ((GPIO_TypeDef *) GPIOO_BASE_S)
+#define GPIOP_S                   ((GPIO_TypeDef *) GPIOP_BASE_S)
+#define GPIOQ_S                   ((GPIO_TypeDef *) GPIOQ_BASE_S)
+#define HASH_S                    ((HASH_TypeDef *) HASH_BASE_S)
+#define HASH_DIGEST_S             ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
+#define HPDMA1_S                  ((DMA_TypeDef *) HPDMA1_BASE_S)
+#define HPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S)
+#define HPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S)
+#define HPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S)
+#define HPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S)
+#define HPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S)
+#define HPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S)
+#define HPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S)
+#define HPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S)
+#define HPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S)
+#define HPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S)
+#define HPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S)
+#define HPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S)
+#define HPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S)
+#define HPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S)
+#define HPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S)
+#define HPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S)
+#define I2C1_S                    ((I2C_TypeDef *) I2C1_BASE_S)
+#define I2C2_S                    ((I2C_TypeDef *) I2C2_BASE_S)
+#define I2C3_S                    ((I2C_TypeDef *) I2C3_BASE_S)
+#define I2C4_S                    ((I2C_TypeDef *) I2C4_BASE_S)
+#define I3C1_S                    ((I3C_TypeDef *) I3C1_BASE_S)
+#define I3C2_S                    ((I3C_TypeDef *) I3C2_BASE_S)
+#define IAC_S                     ((IAC_TypeDef *) IAC_BASE_S)
+#define ICACHE_S                  ((ICACHE_TypeDef *) ICACHE_BASE_S)
+#define IWDG_S                    ((IWDG_TypeDef *) IWDG_BASE_S)
+#define JPEG_S                    ((JPEG_TypeDef *) JPEG_BASE_S)
+#define LPTIM1_S                  ((LPTIM_TypeDef *) LPTIM1_BASE_S)
+#define LPTIM2_S                  ((LPTIM_TypeDef *) LPTIM2_BASE_S)
+#define LPTIM3_S                  ((LPTIM_TypeDef *) LPTIM3_BASE_S)
+#define LPTIM4_S                  ((LPTIM_TypeDef *) LPTIM4_BASE_S)
+#define LPTIM5_S                  ((LPTIM_TypeDef *) LPTIM5_BASE_S)
+#define LPUART1_S                 ((USART_TypeDef *) LPUART1_BASE_S)
+#define LTDC_S                    ((LTDC_TypeDef *)LTDC_BASE_S)
+#define LTDC_Layer1_S             ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S)
+#define LTDC_Layer2_S             ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S)
+#define MDF1_S                    ((MDF_TypeDef *) MDF1_BASE_S)
+#define MDF1_Filter0_S            ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S)
+#define MDF1_Filter1_S            ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S)
+#define MDF1_Filter2_S            ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S)
+#define MDF1_Filter3_S            ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S)
+#define MDF1_Filter4_S            ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S)
+#define MDF1_Filter5_S            ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S)
+#define MDIOS_S                   ((MDIOS_TypeDef *) MDIOS_BASE_S)
+#define PKA_S                     ((PKA_TypeDef *) PKA_BASE_S)
+#define PSSI_S                    ((PSSI_TypeDef *) PSSI_BASE_S)
+#define PWR_S                     ((PWR_TypeDef *) PWR_BASE_S)
+#define RAMCFG_S                  ((RAMCFG_TypeDef *) RAMCFG_BASE_S)
+#define RAMCFG_SRAM1_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S)
+#define RAMCFG_SRAM2_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S)
+#define RAMCFG_SRAM3_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S)
+#define RAMCFG_SRAM4_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S)
+#define RAMCFG_SRAM5_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S)
+#define RAMCFG_SRAM6_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S)
+#define RAMCFG_SRAM1_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S)
+#define RAMCFG_SRAM2_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S)
+#define RAMCFG_VENC_RAM_S         ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_S          ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S)
+#define RAMCFG_FLEXRAM_S          ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S)
+#define RCC_S                     ((RCC_TypeDef *) RCC_BASE_S)
+#define RIFSC_S                   ((RIFSC_TypeDef *) RIFSC_BASE_S)
+#define RISAF1_S                  ((RISAF_TypeDef *) RISAF1_BASE_S)
+#define RISAF2_S                  ((RISAF_TypeDef *) RISAF2_BASE_S)
+#define RISAF3_S                  ((RISAF_TypeDef *) RISAF3_BASE_S)
+#define RISAF6_S                  ((RISAF_TypeDef *) RISAF6_BASE_S)
+#define RISAF7_S                  ((RISAF_TypeDef *) RISAF7_BASE_S)
+#define RISAF8_S                  ((RISAF_TypeDef *) RISAF8_BASE_S)
+#define RISAF9_S                  ((RISAF_TypeDef *) RISAF9_BASE_S)
+#define RISAF11_S                 ((RISAF_TypeDef *) RISAF11_BASE_S)
+#define RISAF12_S                 ((RISAF_TypeDef *) RISAF12_BASE_S)
+#define RISAF13_S                 ((RISAF_TypeDef *) RISAF13_BASE_S)
+#define RISAF14_S                 ((RISAF_TypeDef *) RISAF14_BASE_S)
+#define RISAF21_S                 ((RISAF_TypeDef *) RISAF21_BASE_S)
+#define RISAF22_S                 ((RISAF_TypeDef *) RISAF22_BASE_S)
+#define RISAF23_S                 ((RISAF_TypeDef *) RISAF23_BASE_S)
+#define RNG_S                     ((RNG_TypeDef *) RNG_BASE_S)
+#define RTC_S                     ((RTC_TypeDef *) RTC_BASE_S)
+#define SAI1_S                    ((SAI_TypeDef *) SAI1_BASE_S)
+#define SAI1_Block_A_S            ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S)
+#define SAI1_Block_B_S            ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S)
+#define SAI2_S                    ((SAI_TypeDef *) SAI2_BASE_S)
+#define SAI2_Block_A_S            ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S)
+#define SAI2_Block_B_S            ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S)
+#define SDMMC1_S                  ((SDMMC_TypeDef *) SDMMC1_BASE_S)
+#define SDMMC2_S                  ((SDMMC_TypeDef *) SDMMC2_BASE_S)
+#define SPDIFRX_S                 ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S)
+#define SPI1_S                    ((SPI_TypeDef *) SPI1_BASE_S)
+#define SPI2_S                    ((SPI_TypeDef *) SPI2_BASE_S)
+#define SPI3_S                    ((SPI_TypeDef *) SPI3_BASE_S)
+#define SPI4_S                    ((SPI_TypeDef *) SPI4_BASE_S)
+#define SPI5_S                    ((SPI_TypeDef *) SPI5_BASE_S)
+#define SPI6_S                    ((SPI_TypeDef *) SPI6_BASE_S)
+#define SYSCFG_S                  ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
+#define TAMP_S                    ((TAMP_TypeDef *) TAMP_BASE_S)
+#define TIM1_S                    ((TIM_TypeDef *) TIM1_BASE_S)
+#define TIM2_S                    ((TIM_TypeDef *) TIM2_BASE_S)
+#define TIM3_S                    ((TIM_TypeDef *) TIM3_BASE_S)
+#define TIM4_S                    ((TIM_TypeDef *) TIM4_BASE_S)
+#define TIM5_S                    ((TIM_TypeDef *) TIM5_BASE_S)
+#define TIM6_S                    ((TIM_TypeDef *) TIM6_BASE_S)
+#define TIM7_S                    ((TIM_TypeDef *) TIM7_BASE_S)
+#define TIM8_S                    ((TIM_TypeDef *) TIM8_BASE_S)
+#define TIM9_S                    ((TIM_TypeDef *) TIM9_BASE_S)
+#define TIM10_S                   ((TIM_TypeDef *) TIM10_BASE_S)
+#define TIM11_S                   ((TIM_TypeDef *) TIM11_BASE_S)
+#define TIM12_S                   ((TIM_TypeDef *) TIM12_BASE_S)
+#define TIM13_S                   ((TIM_TypeDef *) TIM13_BASE_S)
+#define TIM14_S                   ((TIM_TypeDef *) TIM14_BASE_S)
+#define TIM15_S                   ((TIM_TypeDef *) TIM15_BASE_S)
+#define TIM16_S                   ((TIM_TypeDef *) TIM16_BASE_S)
+#define TIM17_S                   ((TIM_TypeDef *) TIM17_BASE_S)
+#define TIM18_S                   ((TIM_TypeDef *) TIM18_BASE_S)
+#define UART4_S                   ((USART_TypeDef *) UART4_BASE_S)
+#define UART5_S                   ((USART_TypeDef *) UART5_BASE_S)
+#define UART7_S                   ((USART_TypeDef *) UART7_BASE_S)
+#define UART8_S                   ((USART_TypeDef *) UART8_BASE_S)
+#define UART9_S                   ((USART_TypeDef *) UART9_BASE_S)
+#define UCPD1_S                   ((UCPD_TypeDef *) UCPD1_BASE_S)
+#define USART1_S                  ((USART_TypeDef *) USART1_BASE_S)
+#define USART2_S                  ((USART_TypeDef *) USART2_BASE_S)
+#define USART3_S                  ((USART_TypeDef *) USART3_BASE_S)
+#define USART6_S                  ((USART_TypeDef *) USART6_BASE_S)
+#define USART10_S                 ((USART_TypeDef *) USART10_BASE_S)
+#define USB1_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S)
+#define USB2_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S)
+#define USB1_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S)
+#define USB2_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S)
+#define VENC_S                    ((VENC_TypeDef *) VENC_BASE_S)
+#define VREFBUF_S                 ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
+#define WWDG_S                    ((WWDG_TypeDef *) WWDG_BASE_S)
+#define XSPI1_S                   ((XSPI_TypeDef *) XSPI1_BASE_S)
+#define XSPI2_S                   ((XSPI_TypeDef *) XSPI2_BASE_S)
+#define XSPI3_S                   ((XSPI_TypeDef *) XSPI3_BASE_S)
+#define XSPIM_S                   ((XSPIM_TypeDef *) XSPIM_BASE_S)
+#endif
+
+/*!< Peripheral Instance aliases for Non-Secure/Secure execution  */
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON              ADC12_COMMON_S
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_S
+
+#define ADC1                      ADC1_S
+#define ADC1_BASE                 ADC1_BASE_S
+
+#define ADC2                      ADC2_S
+#define ADC2_BASE                 ADC2_BASE_S
+
+#define ADF1                      ADF1_S
+#define ADF1_BASE                 ADF1_BASE_S
+
+#define ADF1_Filter0              ADF1_Filter0_S
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_S
+
+#define BSEC                      BSEC_S
+#define BSEC_BASE                 BSEC_BASE_S
+
+#define CRC                       CRC_S
+#define CRC_BASE                  CRC_BASE_S
+
+
+#define CSI                       CSI_S
+#define CSI_BASE                  CSI_BASE_S
+
+#define DBGMCU                    DBGMCU_S
+#define DBGMCU_BASE               DBGMCU_BASE_S
+
+#define DCMI                      DCMI_S
+#define DCMI_BASE                 DCMI_BASE_S
+
+#define DCMIPP                    DCMIPP_S
+#define DCMIPP_BASE               DCMIPP_BASE_S
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_S
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_S
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_S
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_S
+
+#define DMA2D                     DMA2D_S
+#define DMA2D_BASE                DMA2D_BASE_S
+
+#define DTS                       DTS_S
+#define DTS_BASE                  DTS_BASE_S
+
+#define DTS_Sensor0               DTS_Sensor0_S
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_S
+
+#define DTS_Sensor1               DTS_Sensor1_S
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_S
+
+#define ETH1                      ETH1_S
+#define ETH1_BASE                 ETH1_BASE_S
+
+#define EXTI                      EXTI_S
+#define EXTI_BASE                 EXTI_BASE_S
+
+#define FDCAN1                    FDCAN1_S
+#define FDCAN1_BASE               FDCAN1_BASE_S
+
+#define FDCAN2                    FDCAN2_S
+#define FDCAN2_BASE               FDCAN2_BASE_S
+
+#define FDCAN3                    FDCAN3_S
+#define FDCAN3_BASE               FDCAN3_BASE_S
+
+#define FDCAN_CCU                 FDCAN_CCU_S
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_S
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_S
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_S
+
+#define FMC_R_BASE                FMC_R_BASE_S
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_S
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_S
+
+#define FMC_Bank1_R               FMC_Bank1_R_S
+#define FMC_Bank1_R_BASE          FMC_Bank1_R_BASE_S
+
+#define FMC_Bank3_R               FMC_Bank3_R_S
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_S
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_S
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_S
+
+#define FMC_Common_R              FMC_Common_R_S
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_S
+
+#define GFXMMU                       GFXMMU_S
+#define GFXMMU_BASE                  GFXMMU_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_S
+
+#define GFXTIM                    GFXTIM_S
+#define GFXTIM_BASE               GFXTIM_BASE_S
+
+#define GPDMA1                    GPDMA1_S
+#define GPDMA1_BASE               GPDMA1_BASE_S
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_S
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_S
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_S
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_S
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_S
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_S
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_S
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_S
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_S
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_S
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_S
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_S
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_S
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_S
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_S
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_S
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_S
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_S
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_S
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_S
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_S
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_S
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_S
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_S
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_S
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_S
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_S
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_S
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_S
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_S
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_S
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_S
+
+#define GPIOA                     GPIOA_S
+#define GPIOA_BASE                GPIOA_BASE_S
+
+#define GPIOB                     GPIOB_S
+#define GPIOB_BASE                GPIOB_BASE_S
+
+#define GPIOC                     GPIOC_S
+#define GPIOC_BASE                GPIOC_BASE_S
+
+#define GPIOD                     GPIOD_S
+#define GPIOD_BASE                GPIOD_BASE_S
+
+#define GPIOE                     GPIOE_S
+#define GPIOE_BASE                GPIOE_BASE_S
+
+#define GPIOF                     GPIOF_S
+#define GPIOF_BASE                GPIOF_BASE_S
+
+#define GPIOG                     GPIOG_S
+#define GPIOG_BASE                GPIOG_BASE_S
+
+#define GPIOH                     GPIOH_S
+#define GPIOH_BASE                GPIOH_BASE_S
+
+#define GPION                     GPION_S
+#define GPION_BASE                GPION_BASE_S
+
+#define GPIOO                     GPIOO_S
+#define GPIOO_BASE                GPIOO_BASE_S
+
+#define GPIOP                     GPIOP_S
+#define GPIOP_BASE                GPIOP_BASE_S
+
+#define GPIOQ                     GPIOQ_S
+#define GPIOQ_BASE                GPIOQ_BASE_S
+
+#define GPU2D                     GPU2D_BASE_S
+#define GPU2D_BASE                GPU2D_BASE_S
+
+#define HASH                      HASH_S
+#define HASH_BASE                 HASH_BASE_S
+
+#define HASH_DIGEST               HASH_DIGEST_S
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_S
+
+#define HPDMA1                    HPDMA1_S
+#define HPDMA1_BASE               HPDMA1_BASE_S
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_S
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_S
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_S
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_S
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_S
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_S
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_S
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_S
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_S
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_S
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_S
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_S
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_S
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_S
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_S
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_S
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_S
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_S
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_S
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_S
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_S
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_S
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_S
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_S
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_S
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_S
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_S
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_S
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_S
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_S
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_S
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_S
+
+#define I2C1                      I2C1_S
+#define I2C1_BASE                 I2C1_BASE_S
+
+#define I2C2                      I2C2_S
+#define I2C2_BASE                 I2C2_BASE_S
+
+#define I2C3                      I2C3_S
+#define I2C3_BASE                 I2C3_BASE_S
+
+#define I2C4                      I2C4_S
+#define I2C4_BASE                 I2C4_BASE_S
+
+#define I3C1                      I3C1_S
+#define I3C1_BASE                 I3C1_BASE_S
+
+#define I3C2                      I3C2_S
+#define I3C2_BASE                 I3C2_BASE_S
+
+#define IAC                       IAC_S
+#define IAC_BASE                  IAC_BASE_S
+
+#define ICACHE                    ICACHE_S
+#define ICACHE_BASE               ICACHE_BASE_S
+
+#define IWDG                      IWDG_S
+#define IWDG_BASE                 IWDG_BASE_S
+
+#define JPEG                      JPEG_S
+#define JPEG_BASE                 JPEG_BASE_S
+
+#define LPTIM1                    LPTIM1_S
+#define LPTIM1_BASE               LPTIM1_BASE_S
+
+#define LPTIM2                    LPTIM2_S
+#define LPTIM2_BASE               LPTIM2_BASE_S
+
+#define LPTIM3                    LPTIM3_S
+#define LPTIM3_BASE               LPTIM3_BASE_S
+
+#define LPTIM4                    LPTIM4_S
+#define LPTIM4_BASE               LPTIM4_BASE_S
+
+#define LPTIM5                    LPTIM5_S
+#define LPTIM5_BASE               LPTIM5_BASE_S
+
+#define LPUART1                   LPUART1_S
+#define LPUART1_BASE              LPUART1_BASE_S
+
+#define LTDC                      LTDC_S
+#define LTDC_BASE                 LTDC_BASE_S
+
+#define LTDC_Layer1               LTDC_Layer1_S
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_S
+
+#define LTDC_Layer2               LTDC_Layer2_S
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_S
+
+
+#define MDF1                      MDF1_S
+#define MDF1_BASE                 MDF1_BASE_S
+
+#define MDF1_Filter0              MDF1_Filter0_S
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_S
+
+#define MDF1_Filter1              MDF1_Filter1_S
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_S
+
+#define MDF1_Filter2              MDF1_Filter2_S
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_S
+
+#define MDF1_Filter3              MDF1_Filter3_S
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_S
+
+#define MDF1_Filter4              MDF1_Filter4_S
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_S
+
+#define MDF1_Filter5              MDF1_Filter5_S
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_S
+
+#define MDIOS                     MDIOS_S
+#define MDIOS_BASE                MDIOS_BASE_S
+
+#define PKA                       PKA_S
+#define PKA_BASE                  PKA_BASE_S
+
+#define PSSI                      PSSI_S
+#define PSSI_BASE                 PSSI_BASE_S
+
+#define PWR                       PWR_S
+#define PWR_BASE                  PWR_BASE_S
+
+#define RAMCFG                    RAMCFG_S
+#define RAMCFG_BASE               RAMCFG_BASE_S
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_S
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_S
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_S
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_S
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_S
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_S
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_S
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_S
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_S
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_S
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_S
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_S
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_S
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_S
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_S
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_S
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_S
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_S
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_S
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_S
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_S
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_S
+
+#define RCC                       RCC_S
+#define RCC_BASE                  RCC_BASE_S
+
+#define RIFSC                     RIFSC_S
+#define RIFSC_BASE                RIFSC_BASE_S
+
+#define RISAF1                    RISAF1_S
+#define RISAF1_BASE               RISAF1_BASE_S
+
+#define RISAF2                    RISAF2_S
+#define RISAF2_BASE               RISAF2_BASE_S
+
+#define RISAF3                    RISAF3_S
+#define RISAF3_BASE               RISAF3_BASE_S
+
+#define RISAF6                    RISAF6_S
+#define RISAF6_BASE               RISAF6_BASE_S
+
+#define RISAF7                    RISAF7_S
+#define RISAF7_BASE               RISAF7_BASE_S
+
+#define RISAF8                    RISAF8_S
+#define RISAF8_BASE               RISAF8_BASE_S
+
+#define RISAF9                    RISAF9_S
+#define RISAF9_BASE               RISAF9_BASE_S
+
+#define RISAF11                   RISAF11_S
+#define RISAF11_BASE              RISAF11_BASE_S
+
+#define RISAF12                   RISAF12_S
+#define RISAF12_BASE              RISAF12_BASE_S
+
+#define RISAF13                   RISAF13_S
+#define RISAF13_BASE              RISAF13_BASE_S
+
+#define RISAF14                   RISAF14_S
+#define RISAF14_BASE              RISAF14_BASE_S
+
+#define RISAF21                   RISAF21_S
+#define RISAF21_BASE              RISAF21_BASE_S
+
+#define RISAF22                   RISAF22_S
+#define RISAF22_BASE              RISAF22_BASE_S
+
+#define RISAF23                   RISAF23_S
+#define RISAF23_BASE              RISAF23_BASE_S
+
+#define RNG                       RNG_S
+#define RNG_BASE                  RNG_BASE_S
+
+#define RTC                       RTC_S
+#define RTC_BASE                  RTC_BASE_S
+
+
+#define SAI1                      SAI1_S
+#define SAI1_BASE                 SAI1_BASE_S
+
+#define SAI1_Block_A              SAI1_Block_A_S
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_S
+
+#define SAI1_Block_B              SAI1_Block_B_S
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_S
+
+#define SAI2                      SAI2_S
+#define SAI2_BASE                 SAI2_BASE_S
+
+#define SAI2_Block_A              SAI2_Block_A_S
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_S
+
+#define SAI2_Block_B              SAI2_Block_B_S
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_S
+
+#define SDMMC1                    SDMMC1_S
+#define SDMMC1_BASE               SDMMC1_BASE_S
+
+#define SDMMC2                    SDMMC2_S
+#define SDMMC2_BASE               SDMMC2_BASE_S
+
+#define SPDIFRX                   SPDIFRX_S
+#define SPDIFRX_BASE              SPDIFRX_BASE_S
+
+#define SPI1                      SPI1_S
+#define SPI1_BASE                 SPI1_BASE_S
+
+#define SPI2                      SPI2_S
+#define SPI2_BASE                 SPI2_BASE_S
+
+#define SPI3                      SPI3_S
+#define SPI3_BASE                 SPI3_BASE_S
+
+#define SPI4                      SPI4_S
+#define SPI4_BASE                 SPI4_BASE_S
+
+#define SPI5                      SPI5_S
+#define SPI5_BASE                 SPI5_BASE_S
+
+#define SPI6                      SPI6_S
+#define SPI6_BASE                 SPI6_BASE_S
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_S
+
+#define SYSCFG                    SYSCFG_S
+#define SYSCFG_BASE               SYSCFG_BASE_S
+
+#define TAMP                      TAMP_S
+#define TAMP_BASE                 TAMP_BASE_S
+
+#define TIM1                      TIM1_S
+#define TIM1_BASE                 TIM1_BASE_S
+
+#define TIM2                      TIM2_S
+#define TIM2_BASE                 TIM2_BASE_S
+
+#define TIM3                      TIM3_S
+#define TIM3_BASE                 TIM3_BASE_S
+
+#define TIM4                      TIM4_S
+#define TIM4_BASE                 TIM4_BASE_S
+
+#define TIM5                      TIM5_S
+#define TIM5_BASE                 TIM5_BASE_S
+
+#define TIM6                      TIM6_S
+#define TIM6_BASE                 TIM6_BASE_S
+
+#define TIM7                      TIM7_S
+#define TIM7_BASE                 TIM7_BASE_S
+
+#define TIM8                      TIM8_S
+#define TIM8_BASE                 TIM8_BASE_S
+
+#define TIM9                      TIM9_S
+#define TIM9_BASE                 TIM9_BASE_S
+
+#define TIM10                     TIM10_S
+#define TIM10_BASE                TIM10_BASE_S
+
+#define TIM11                     TIM11_S
+#define TIM11_BASE                TIM11_BASE_S
+
+#define TIM12                     TIM12_S
+#define TIM12_BASE                TIM12_BASE_S
+
+#define TIM13                     TIM13_S
+#define TIM13_BASE                TIM13_BASE_S
+
+#define TIM14                     TIM14_S
+#define TIM14_BASE                TIM14_BASE_S
+
+#define TIM15                     TIM15_S
+#define TIM15_BASE                TIM15_BASE_S
+
+#define TIM16                     TIM16_S
+#define TIM16_BASE                TIM16_BASE_S
+
+#define TIM17                     TIM17_S
+#define TIM17_BASE                TIM17_BASE_S
+
+#define TIM18                     TIM18_S
+#define TIM18_BASE                TIM18_BASE_S
+
+#define UART4                     UART4_S
+#define UART4_BASE                UART4_BASE_S
+
+#define UART5                     UART5_S
+#define UART5_BASE                UART5_BASE_S
+
+#define UART7                     UART7_S
+#define UART7_BASE                UART7_BASE_S
+
+#define UART8                     UART8_S
+#define UART8_BASE                UART8_BASE_S
+
+#define UART9                     UART9_S
+#define UART9_BASE                UART9_BASE_S
+
+#define UCPD1                     UCPD1_S
+#define UCPD1_BASE                UCPD1_BASE_S
+
+#define USART1                    USART1_S
+#define USART1_BASE               USART1_BASE_S
+
+#define USART2                    USART2_S
+#define USART2_BASE               USART2_BASE_S
+
+#define USART3                    USART3_S
+#define USART3_BASE               USART3_BASE_S
+
+#define USART6                    USART6_S
+#define USART6_BASE               USART6_BASE_S
+
+#define USART10                   USART10_S
+#define USART10_BASE              USART10_BASE_S
+
+#define USB1_OTG_HS               USB1_OTG_HS_S
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_S
+
+#define USB2_OTG_HS               USB2_OTG_HS_S
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_S
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_S
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_S
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_S
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_S
+
+#define VENC                      VENC_S
+#define VENC_BASE                 VENC_BASE_S
+
+#define VREFBUF                   VREFBUF_S
+#define VREFBUF_BASE              VREFBUF_BASE_S
+
+#define WWDG                      WWDG_S
+#define WWDG_BASE                 WWDG_BASE_S
+
+#define XSPI1                     XSPI1_S
+
+#define XSPI2                     XSPI2_S
+
+#define XSPI3                     XSPI3_S
+
+#define XSPIM                     XSPIM_S
+#define XSPIM_BASE                XSPIM_BASE_S
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_S
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_S
+
+#else
+
+#define ADC12_COMMON              ADC12_COMMON_NS
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_NS
+
+#define ADC1                      ADC1_NS
+#define ADC1_BASE                 ADC1_BASE_NS
+
+#define ADC2                      ADC2_NS
+#define ADC2_BASE                 ADC2_BASE_NS
+
+#define ADF1                      ADF1_NS
+#define ADF1_BASE                 ADF1_BASE_NS
+
+#define ADF1_Filter0              ADF1_Filter0_NS
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_NS
+
+#define BSEC                      BSEC_NS
+#define BSEC_BASE                 BSEC_BASE_NS
+
+#define CRC                       CRC_NS
+#define CRC_BASE                  CRC_BASE_NS
+
+
+#define CSI                       CSI_NS
+#define CSI_BASE                  CSI_BASE_NS
+
+#define DBGMCU                    DBGMCU_NS
+#define DBGMCU_BASE               DBGMCU_BASE_NS
+
+#define DCMI                      DCMI_NS
+#define DCMI_BASE                 DCMI_BASE_NS
+
+#define DCMIPP                    DCMIPP_NS
+#define DCMIPP_BASE               DCMIPP_BASE_NS
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_NS
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_NS
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_NS
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_NS
+
+#define DMA2D                     DMA2D_NS
+#define DMA2D_BASE                DMA2D_BASE_NS
+
+#define DTS                       DTS_NS
+#define DTS_BASE                  DTS_BASE_NS
+
+#define DTS_Sensor0               DTS_Sensor0_NS
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_NS
+
+#define DTS_Sensor1               DTS_Sensor1_NS
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_NS
+
+#define ETH1                      ETH1_NS
+#define ETH1_BASE                 ETH1_BASE_NS
+
+#define EXTI                      EXTI_NS
+#define EXTI_BASE                 EXTI_BASE_NS
+
+#define FDCAN1                    FDCAN1_NS
+#define FDCAN1_BASE               FDCAN1_BASE_NS
+
+#define FDCAN2                    FDCAN2_NS
+#define FDCAN2_BASE               FDCAN2_BASE_NS
+
+#define FDCAN3                    FDCAN3_NS
+#define FDCAN3_BASE               FDCAN3_BASE_NS
+
+#define FDCAN_CCU                 FDCAN_CCU_NS
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_NS
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_NS
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_NS
+
+#define FMC_R_BASE                FMC_R_BASE_NS
+#define FMC_R_BASE_BASE           FMC_R_BASE_BASE_NS
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_NS
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_NS
+
+#define FMC_Bank1_R               FMC_Bank1_R_NS
+#define FMC_Bank1_Rv              FMC_Bank1_R_BASE_NS
+
+#define FMC_Bank3_R               FMC_Bank3_R_NS
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_NS
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_NS
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_NS
+
+#define FMC_Common_R              FMC_Common_R_NS
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_NS
+
+#define GFXMMU                       GFXMMU_NS
+#define GFXMMU_BASE                  GFXMMU_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_NS
+
+#define GFXTIM                    GFXTIM_NS
+#define GFXTIM_BASE               GFXTIM_BASE_NS
+
+#define GPDMA1                    GPDMA1_NS
+#define GPDMA1_BASE               GPDMA1_BASE_NS
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_NS
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_NS
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_NS
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_NS
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_NS
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_NS
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_NS
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_NS
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_NS
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_NS
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_NS
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_NS
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_NS
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_NS
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_NS
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_NS
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_NS
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_NS
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_NS
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_NS
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_NS
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_NS
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_NS
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_NS
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_NS
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_NS
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_NS
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_NS
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_NS
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_NS
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_NS
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_NS
+
+#define GPIOA                     GPIOA_NS
+#define GPIOA_BASE                GPIOA_BASE_NS
+
+#define GPIOB                     GPIOB_NS
+#define GPIOB_BASE                GPIOB_BASE_NS
+
+#define GPIOC                     GPIOC_NS
+#define GPIOC_BASE                GPIOC_BASE_NS
+
+#define GPIOD                     GPIOD_NS
+#define GPIOD_BASE                GPIOD_BASE_NS
+
+#define GPIOE                     GPIOE_NS
+#define GPIOE_BASE                GPIOE_BASE_NS
+
+#define GPIOF                     GPIOF_NS
+#define GPIOF_BASE                GPIOF_BASE_NS
+
+#define GPIOG                     GPIOG_NS
+#define GPIOG_BASE                GPIOG_BASE_NS
+
+#define GPIOH                     GPIOH_NS
+#define GPIOH_BASE                GPIOH_BASE_NS
+
+#define GPION                     GPION_NS
+#define GPION_BASE                GPION_BASE_NS
+
+#define GPIOO                     GPIOO_NS
+#define GPIOO_BASE                GPIOO_BASE_NS
+
+#define GPIOP                     GPIOP_NS
+#define GPIOP_BASE                GPIOP_BASE_NS
+
+#define GPIOQ                     GPIOQ_NS
+#define GPIOQ_BASE                GPIOQ_BASE_NS
+
+#define GPU2D                     GPU2D_BASE_NS
+#define GPU2D_BASE                GPU2D_BASE_NS
+
+#define HASH                      HASH_NS
+#define HASH_BASE                 HASH_BASE_NS
+
+#define HASH_DIGEST               HASH_DIGEST_NS
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_NS
+
+#define HPDMA1                    HPDMA1_NS
+#define HPDMA1_BASE               HPDMA1_BASE_NS
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_NS
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_NS
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_NS
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_NS
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_NS
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_NS
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_NS
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_NS
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_NS
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_NS
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_NS
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_NS
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_NS
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_NS
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_NS
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_NS
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_NS
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_NS
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_NS
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_NS
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_NS
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_NS
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_NS
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_NS
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_NS
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_NS
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_NS
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_NS
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_NS
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_NS
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_NS
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_NS
+
+#define I2C1                      I2C1_NS
+#define I2C1_BASE                 I2C1_BASE_NS
+
+#define I2C2                      I2C2_NS
+#define I2C2_BASE                 I2C2_BASE_NS
+
+#define I2C3                      I2C3_NS
+#define I2C3_BASE                 I2C3_BASE_NS
+
+#define I2C4                      I2C4_NS
+#define I2C4_BASE                 I2C4_BASE_NS
+
+#define I3C1                      I3C1_NS
+#define I3C1_BASE                 I3C1_BASE_NS
+
+#define I3C2                      I3C2_NS
+#define I3C2_BASE                 I3C2_BASE_NS
+
+#define ICACHE                    ICACHE_NS
+#define ICACHE_BASE               ICACHE_BASE_NS
+
+#define IWDG                      IWDG_NS
+#define IWDG_BASE                 IWDG_BASE_NS
+
+#define JPEG                      JPEG_NS
+#define JPEG_BASE                 JPEG_BASE_NS
+
+#define LPTIM1                    LPTIM1_NS
+#define LPTIM1_BASE               LPTIM1_BASE_NS
+
+#define LPTIM2                    LPTIM2_NS
+#define LPTIM2_BASE               LPTIM2_BASE_NS
+
+#define LPTIM3                    LPTIM3_NS
+#define LPTIM3_BASE               LPTIM3_BASE_NS
+
+#define LPTIM4                    LPTIM4_NS
+#define LPTIM4_BASE               LPTIM4_BASE_NS
+
+#define LPTIM5                    LPTIM5_NS
+#define LPTIM5_BASE               LPTIM5_BASE_NS
+
+#define LPUART1                   LPUART1_NS
+#define LPUART1_BASE              LPUART1_BASE_NS
+
+#define LTDC                      LTDC_NS
+#define LTDC_BASE                 LTDC_BASE_NS
+
+#define LTDC_Layer1               LTDC_Layer1_NS
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_NS
+
+#define LTDC_Layer2               LTDC_Layer2_NS
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_NS
+
+
+#define MDF1                      MDF1_NS
+#define MDF1_BASE                 MDF1_BASE_NS
+
+#define MDF1_Filter0              MDF1_Filter0_NS
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_NS
+
+#define MDF1_Filter1              MDF1_Filter1_NS
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_NS
+
+#define MDF1_Filter2              MDF1_Filter2_NS
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_NS
+
+#define MDF1_Filter3              MDF1_Filter3_NS
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_NS
+
+#define MDF1_Filter4              MDF1_Filter4_NS
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_NS
+
+#define MDF1_Filter5              MDF1_Filter5_NS
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_NS
+
+#define MDIOS                     MDIOS_NS
+#define MDIOS_BASE                MDIOS_BASE_NS
+
+#define PKA                       PKA_NS
+#define PKA_BASE                  PKA_BASE_NS
+
+#define PSSI                      PSSI_NS
+#define PSSI_BASE                 PSSI_BASE_NS
+
+#define PWR                       PWR_NS
+#define PWR_BASE                  PWR_BASE_NS
+
+#define RAMCFG                    RAMCFG_NS
+#define RAMCFG_BASE               RAMCFG_BASE_NS
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_NS
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_NS
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_NS
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_NS
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_NS
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_NS
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_NS
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_NS
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_NS
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_NS
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_NS
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_NS
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_NS
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_NS
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_NS
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_NS
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_NS
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_NS
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_NS
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_NS
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_NS
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_NS
+
+#define RCC                       RCC_NS
+#define RCC_BASE                  RCC_BASE_NS
+
+#define RIFSC                     RIFSC_NS
+#define RIFSC_BASE                RIFSC_BASE_NS
+
+#define RISAF1                    RISAF1_NS
+#define RISAF1_BASE               RISAF1_BASE_NS
+
+#define RISAF2                    RISAF2_NS
+#define RISAF2_BASE               RISAF2_BASE_NS
+
+#define RISAF3                    RISAF3_NS
+#define RISAF3_BASE               RISAF3_BASE_NS
+
+#define RISAF6                    RISAF6_NS
+#define RISAF6_BASE               RISAF6_BASE_NS
+
+#define RISAF7                    RISAF7_NS
+#define RISAF7_BASE               RISAF7_BASE_NS
+
+#define RISAF8                    RISAF8_NS
+#define RISAF8_BASE               RISAF8_BASE_NS
+
+#define RISAF9                    RISAF9_NS
+#define RISAF9_BASE               RISAF9_BASE_NS
+
+#define RISAF11                   RISAF11_NS
+#define RISAF11_BASE              RISAF11_BASE_NS
+
+#define RISAF12                   RISAF12_NS
+#define RISAF12_BASE              RISAF12_BASE_NS
+
+#define RISAF13                   RISAF13_NS
+#define RISAF13_BASE              RISAF13_BASE_NS
+
+#define RISAF14                   RISAF14_NS
+#define RISAF14_BASE              RISAF14_BASE_NS
+
+#define RISAF21                   RISAF21_NS
+#define RISAF21_BASE              RISAF21_BASE_NS
+
+#define RISAF22                   RISAF22_NS
+#define RISAF22_BASE              RISAF22_BASE_NS
+
+#define RISAF23                   RISAF23_NS
+#define RISAF23_BASE              RISAF23_BASE_NS
+
+#define RNG                       RNG_NS
+#define RNG_BASE                  RNG_BASE_NS
+
+#define RTC                       RTC_NS
+#define RTC_BASE                  RTC_BASE_NS
+
+
+#define SAI1                      SAI1_NS
+#define SAI1_BASE                 SAI1_BASE_NS
+
+#define SAI1_Block_A              SAI1_Block_A_NS
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_NS
+
+#define SAI1_Block_B              SAI1_Block_B_NS
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_NS
+
+#define SAI2                      SAI2_NS
+#define SAI2_BASE                 SAI2_BASE_NS
+
+#define SAI2_Block_A              SAI2_Block_A_NS
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_NS
+
+#define SAI2_Block_B              SAI2_Block_B_NS
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_NS
+
+#define SDMMC1                    SDMMC1_NS
+#define SDMMC1_BASE               SDMMC1_BASE_NS
+
+#define SDMMC2                    SDMMC2_NS
+#define SDMMC2_BASE               SDMMC2_BASE_NS
+
+#define SPDIFRX                   SPDIFRX_NS
+#define SPDIFRX_BASE              SPDIFRX_BASE_NS
+
+#define SPI1                      SPI1_NS
+#define SPI1_BASE                 SPI1_BASE_NS
+
+#define SPI2                      SPI2_NS
+#define SPI2_BASE                 SPI2_BASE_NS
+
+#define SPI3                      SPI3_NS
+#define SPI3_BASE                 SPI3_BASE_NS
+
+#define SPI4                      SPI4_NS
+#define SPI4_BASE                 SPI4_BASE_NS
+
+#define SPI5                      SPI5_NS
+#define SPI5_BASE                 SPI5_BASE_NS
+
+#define SPI6                      SPI6_NS
+#define SPI6_BASE                 SPI6_BASE_NS
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_NS
+
+#define SYSCFG                    SYSCFG_NS
+#define SYSCFG_BASE               SYSCFG_BASE_NS
+
+#define TAMP                      TAMP_NS
+#define TAMP_BASE                 TAMP_BASE_NS
+
+#define TIM1                      TIM1_NS
+#define TIM1_BASE                 TIM1_BASE_NS
+
+#define TIM2                      TIM2_NS
+#define TIM2_BASE                 TIM2_BASE_NS
+
+#define TIM3                      TIM3_NS
+#define TIM3_BASE                 TIM3_BASE_NS
+
+#define TIM4                      TIM4_NS
+#define TIM4_BASE                 TIM4_BASE_NS
+
+#define TIM5                      TIM5_NS
+#define TIM5_BASE                 TIM5_BASE_NS
+
+#define TIM6                      TIM6_NS
+#define TIM6_BASE                 TIM6_BASE_NS
+
+#define TIM7                      TIM7_NS
+#define TIM7_BASE                 TIM7_BASE_NS
+
+#define TIM8                      TIM8_NS
+#define TIM8_BASE                 TIM8_BASE_NS
+
+#define TIM9                      TIM9_NS
+#define TIM9_BASE                 TIM9_BASE_NS
+
+#define TIM10                     TIM10_NS
+#define TIM10_BASE                TIM10_BASE_NS
+
+#define TIM11                     TIM11_NS
+#define TIM11_BASE                TIM11_BASE_NS
+
+#define TIM12                     TIM12_NS
+#define TIM12_BASE                TIM12_BASE_NS
+
+#define TIM13                     TIM13_NS
+#define TIM13_BASE                TIM13_BASE_NS
+
+#define TIM14                     TIM14_NS
+#define TIM14_BASE                TIM14_BASE_NS
+
+#define TIM15                     TIM15_NS
+#define TIM15_BASE                TIM15_BASE_NS
+
+#define TIM16                     TIM16_NS
+#define TIM16_BASE                TIM16_BASE_NS
+
+#define TIM17                     TIM17_NS
+#define TIM17_BASE                TIM17_BASE_NS
+
+#define TIM18                     TIM18_NS
+#define TIM18_BASE                TIM18_BASE_NS
+
+#define UART4                     UART4_NS
+#define UART4_BASE                UART4_BASE_NS
+
+#define UART5                     UART5_NS
+#define UART5_BASE                UART5_BASE_NS
+
+#define UART7                     UART7_NS
+#define UART7_BASE                UART7_BASE_NS
+
+#define UART8                     UART8_NS
+#define UART8_BASE                UART8_BASE_NS
+
+#define UART9                     UART9_NS
+#define UART9_BASE                UART9_BASE_NS
+
+#define UCPD1                     UCPD1_NS
+#define UCPD1_BASE                UCPD1_BASE_NS
+
+#define USART1                    USART1_NS
+#define USART1_BASE               USART1_BASE_NS
+
+#define USART2                    USART2_NS
+#define USART2_BASE               USART2_BASE_NS
+
+#define USART3                    USART3_NS
+#define USART3_BASE               USART3_BASE_NS
+
+#define USART6                    USART6_NS
+#define USART6_BASE               USART6_BASE_NS
+
+#define USART10                   USART10_NS
+#define USART10_BASE              USART10_BASE_NS
+
+#define USB1_OTG_HS               USB1_OTG_HS_NS
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_NS
+
+#define USB2_OTG_HS               USB2_OTG_HS_NS
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_NS
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_NS
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_NS
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_NS
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_NS
+
+#define VENC                      VENC_NS
+#define VENC_BASE                 VENC_BASE_NS
+
+#define VREFBUF                   VREFBUF_NS
+#define VREFBUF_BASE              VREFBUF_BASE_NS
+
+#define WWDG                      WWDG_NS
+#define WWDG_BASE                 WWDG_BASE_NS
+
+#define XSPI1                     XSPI1_NS
+
+#define XSPI2                     XSPI2_NS
+
+#define XSPI3                     XSPI3_NS
+
+#define XSPIM                     XSPIM_NS
+#define XSPIM_BASE                XSPIM_BASE_NS
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_NS
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_NS
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Timing_Definition
+  * @{
+  */
+
+#define LSI_STARTUP_TIME                16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter (ADC)                   */
+/*                                                                            */
+/******************************************************************************/
+
+/* Specific device feature definitions */
+#define ADC_MULTIMODE_SUPPORT         /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)
+#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)
+#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)
+#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)
+#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)
+#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)
+#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)
+#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)
+#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)
+#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)
+#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)
+#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)
+#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)
+#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)
+#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)
+#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)
+#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)
+#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)
+#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)
+#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)
+#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)
+#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)
+#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)
+#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)
+#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)
+#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)
+#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_DEEPPWD_Pos             (29U)
+#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)
+#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)
+#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR1 register  ******************/
+#define ADC_CFGR1_DMNGT_Pos            (0U)
+#define ADC_CFGR1_DMNGT_Msk            (0x3UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000003 */
+#define ADC_CFGR1_DMNGT                ADC_CFGR1_DMNGT_Msk                     /*!< ADC data management configuration */
+#define ADC_CFGR1_DMNGT_0              (0x1UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR1_DMNGT_1              (0x2UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000002 */
+
+#define ADC_CFGR1_RES_Pos              (2U)
+#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x0000000C */
+#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
+#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
+
+#define ADC_CFGR1_EXTSEL_Pos           (5U)
+#define ADC_CFGR1_EXTSEL_Msk           (0x1FUL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x000003E0 */
+#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
+#define ADC_CFGR1_EXTSEL_0             (0x01UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_CFGR1_EXTSEL_1             (0x02UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_2             (0x04UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_3             (0x08UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000100 */
+#define ADC_CFGR1_EXTSEL_4             (0x10UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000200 */
+
+#define ADC_CFGR1_EXTEN_Pos            (10U)
+#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
+
+#define ADC_CFGR1_OVRMOD_Pos           (12U)
+#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
+#define ADC_CFGR1_CONT_Pos             (13U)
+#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
+#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR1_AUTDLY_Pos           (14U)
+#define ADC_CFGR1_AUTDLY_Msk           (0x1UL << ADC_CFGR1_AUTDLY_Pos)         /*!< 0x00004000 */
+#define ADC_CFGR1_AUTDLY               ADC_CFGR1_AUTDLY_Msk                    /*!< ADC low power auto wait */
+
+#define ADC_CFGR1_DISCEN_Pos           (16U)
+#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR1_DISCNUM_Pos          (17U)
+#define ADC_CFGR1_DISCNUM_Msk          (0x7UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x000E0000 */
+#define ADC_CFGR1_DISCNUM              ADC_CFGR1_DISCNUM_Msk                   /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR1_DISCNUM_0            (0x1UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00020000 */
+#define ADC_CFGR1_DISCNUM_1            (0x2UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00040000 */
+#define ADC_CFGR1_DISCNUM_2            (0x4UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00080000 */
+
+#define ADC_CFGR1_JDISCEN_Pos          (20U)
+#define ADC_CFGR1_JDISCEN_Msk          (0x1UL << ADC_CFGR1_JDISCEN_Pos)        /*!< 0x00100000 */
+#define ADC_CFGR1_JDISCEN              ADC_CFGR1_JDISCEN_Msk                   /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CFGR1_AWD1SGL_Pos          (22U)
+#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
+#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR1_AWD1EN_Pos           (23U)
+#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
+#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR1_JAWD1EN_Pos          (24U)
+#define ADC_CFGR1_JAWD1EN_Msk          (0x1UL << ADC_CFGR1_JAWD1EN_Pos)        /*!< 0x01000000 */
+#define ADC_CFGR1_JAWD1EN              ADC_CFGR1_JAWD1EN_Msk                   /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR1_JAUTO_Pos            (25U)
+#define ADC_CFGR1_JAUTO_Msk            (0x1UL << ADC_CFGR1_JAUTO_Pos)          /*!< 0x02000000 */
+#define ADC_CFGR1_JAUTO                ADC_CFGR1_JAUTO_Msk                     /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR1_AWD1CH_Pos           (26U)
+#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
+#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
+#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
+#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
+#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
+#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)
+#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)
+#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)
+#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)
+#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)
+#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+#define ADC_CFGR2_BULB_Pos             (13U)
+#define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)            /*!< 0x00002000 */
+#define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                       /*!< ADC bulb sampling mode */
+
+#define ADC_CFGR2_SWTRIG_Pos           (14U)
+#define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)          /*!< 0x00004000 */
+#define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                     /*!< ADC software trigger bit for sampling time control trigger mode */
+
+#define ADC_CFGR2_SMPTRIG_Pos          (15U)
+#define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)         /*!< 0x00008000 */
+#define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                    /*!< ADC sampling time control trigger mode */
+
+#define ADC_CFGR2_OVSR_Pos             (16U)
+#define ADC_CFGR2_OVSR_Msk             (0x3FFUL << ADC_CFGR2_OVSR_Pos)          /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                       /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x001UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1               (0x002UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2               (0x004UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3               (0x008UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4               (0x010UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5               (0x020UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6               (0x040UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7               (0x080UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8               (0x100UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9               (0x200UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos           (28U)
+#define ADC_CFGR2_LSHIFT_Msk           (0xFUL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT               ADC_CFGR2_LSHIFT_Msk                     /*!< ADC left shift factor */
+#define ADC_CFGR2_LSHIFT_0             (0x1UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1             (0x2UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2             (0x4UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3             (0x8UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)
+#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)
+#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)
+#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)
+#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)
+#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)
+#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)
+#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)
+#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)
+#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)
+#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)
+#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)
+#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)
+#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)
+#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)
+#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)
+#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)
+#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)
+#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)
+#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos            (27U)
+#define ADC_SMPR2_SMP19_Msk            (0x7UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                ADC_SMPR2_SMP19_Msk                     /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0              (0x1UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1              (0x2UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2              (0x4UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  *****************/
+#define ADC_PCSEL_PCSEL_Pos            (0U)
+#define ADC_PCSEL_PCSEL_Msk            (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                ADC_PCSEL_PCSEL_Msk                   /*!< ADC channel preselection */
+#define ADC_PCSEL_PCSEL_0              (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1              (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2              (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3              (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4              (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5              (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6              (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7              (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8              (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9              (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10             (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11             (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12             (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13             (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14             (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15             (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16             (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17             (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18             (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19             (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)
+#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)
+#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)
+#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)
+#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)
+#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)
+#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)
+#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)
+#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)
+#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)
+#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)
+#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)
+#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)
+#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)
+#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)
+#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)
+#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)
+#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)
+#define ADC_DR_RDATA_Msk               (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)      /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x00000001UL << ADC_DR_RDATA_Pos)      /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x00000002UL << ADC_DR_RDATA_Pos)      /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x00000004UL << ADC_DR_RDATA_Pos)      /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x00000008UL << ADC_DR_RDATA_Pos)      /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x00000010UL << ADC_DR_RDATA_Pos)      /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x00000020UL << ADC_DR_RDATA_Pos)      /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x00000040UL << ADC_DR_RDATA_Pos)      /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x00000080UL << ADC_DR_RDATA_Pos)      /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x00000100UL << ADC_DR_RDATA_Pos)      /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x00000200UL << ADC_DR_RDATA_Pos)      /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x00000400UL << ADC_DR_RDATA_Pos)      /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x00000800UL << ADC_DR_RDATA_Pos)      /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x00001000UL << ADC_DR_RDATA_Pos)      /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x00002000UL << ADC_DR_RDATA_Pos)      /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x00004000UL << ADC_DR_RDATA_Pos)      /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x00008000UL << ADC_DR_RDATA_Pos)      /*!< 0x00008000 */
+#define ADC_DR_RDATA_16                (0x00010000UL << ADC_DR_RDATA_Pos)      /*!< 0x00010000 */
+#define ADC_DR_RDATA_17                (0x00020000UL << ADC_DR_RDATA_Pos)      /*!< 0x00020000 */
+#define ADC_DR_RDATA_18                (0x00040000UL << ADC_DR_RDATA_Pos)      /*!< 0x00040000 */
+#define ADC_DR_RDATA_19                (0x00080000UL << ADC_DR_RDATA_Pos)      /*!< 0x00080000 */
+#define ADC_DR_RDATA_20                (0x00100000UL << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
+#define ADC_DR_RDATA_21                (0x00200000UL << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
+#define ADC_DR_RDATA_22                (0x00400000UL << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
+#define ADC_DR_RDATA_23                (0x00800000UL << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
+#define ADC_DR_RDATA_24                (0x01000000UL << ADC_DR_RDATA_Pos)      /*!< 0x01000000 */
+#define ADC_DR_RDATA_25                (0x02000000UL << ADC_DR_RDATA_Pos)      /*!< 0x02000000 */
+#define ADC_DR_RDATA_26                (0x04000000UL << ADC_DR_RDATA_Pos)      /*!< 0x04000000 */
+#define ADC_DR_RDATA_27                (0x08000000UL << ADC_DR_RDATA_Pos)      /*!< 0x08000000 */
+#define ADC_DR_RDATA_28                (0x10000000UL << ADC_DR_RDATA_Pos)      /*!< 0x10000000 */
+#define ADC_DR_RDATA_29                (0x20000000UL << ADC_DR_RDATA_Pos)      /*!< 0x20000000 */
+#define ADC_DR_RDATA_30                (0x40000000UL << ADC_DR_RDATA_Pos)      /*!< 0x40000000 */
+#define ADC_DR_RDATA_31                (0x80000000UL << ADC_DR_RDATA_Pos)      /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)
+#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)
+#define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x01UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x02UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x04UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x08UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos            (7U)
+#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos              (9U)
+#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos              (15U)
+#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos              (21U)
+#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (27U)
+#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR1 register  ***************/
+#define ADC_OFCFGR1_POSOFF_Pos         (24U)
+#define ADC_OFCFGR1_POSOFF_Msk         (0x01UL << ADC_OFCFGR1_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR1_POSOFF             ADC_OFCFGR1_POSOFF_Msk                  /*!< ADC offset instance 1 positive offset enable */
+
+#define ADC_OFCFGR1_USAT_Pos           (25U)
+#define ADC_OFCFGR1_USAT_Msk           (0x01UL << ADC_OFCFGR1_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR1_USAT               ADC_OFCFGR1_USAT_Msk                    /*!< ADC offset instance 1  unsigned saturation value */
+
+#define ADC_OFCFGR1_SSAT_Pos           (26U)
+#define ADC_OFCFGR1_SSAT_Msk           (0x01UL << ADC_OFCFGR1_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR1_SSAT               ADC_OFCFGR1_SSAT_Msk                    /*!< ADC offset instance 1 signed satuaration enable */
+
+#define ADC_OFCFGR1_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR1_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR1_OFFSET_CH          ADC_OFCFGR1_OFFSET_CH_Msk               /*!< ADC offset instance 1 channel selection */
+#define ADC_OFCFGR1_OFFSET_CH_0        (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR1_OFFSET_CH_1        (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR1_OFFSET_CH_2        (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR1_OFFSET_CH_3        (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR1_OFFSET_CH_4        (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR2 register  ***************/
+#define ADC_OFCFGR2_POSOFF_Pos         (24U)
+#define ADC_OFCFGR2_POSOFF_Msk         (0x01UL << ADC_OFCFGR2_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR2_POSOFF             ADC_OFCFGR2_POSOFF_Msk                  /*!< ADC offset instance 2 positive offset enable */
+
+#define ADC_OFCFGR2_USAT_Pos           (25U)
+#define ADC_OFCFGR2_USAT_Msk           (0x01UL << ADC_OFCFGR2_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR2_USAT               ADC_OFCFGR2_USAT_Msk                    /*!< ADC offset instance 2 unsigned saturation value */
+
+#define ADC_OFCFGR2_SSAT_Pos           (26U)
+#define ADC_OFCFGR2_SSAT_Msk           (0x01UL << ADC_OFCFGR2_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR2_SSAT               ADC_OFCFGR2_SSAT_Msk                    /*!< ADC offset instance 2 signed satuaration enable */
+
+#define ADC_OFCFGR2_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR2_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR2_OFFSET_CH          ADC_OFCFGR2_OFFSET_CH_Msk               /*!< ADC offset instance 2 channel selection */
+#define ADC_OFCFGR2_OFFSET_CH_0        (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR2_OFFSET_CH_1        (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR2_OFFSET_CH_2        (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR2_OFFSET_CH_3        (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR2_OFFSET_CH_4        (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR3 register  ***************/
+#define ADC_OFCFGR3_POSOFF_Pos         (24U)
+#define ADC_OFCFGR3_POSOFF_Msk         (0x01UL << ADC_OFCFGR3_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR3_POSOFF             ADC_OFCFGR3_POSOFF_Msk                  /*!< ADC offset instance 3 positive offset enable */
+
+#define ADC_OFCFGR3_USAT_Pos           (25U)
+#define ADC_OFCFGR3_USAT_Msk           (0x01UL << ADC_OFCFGR3_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR3_USAT               ADC_OFCFGR3_USAT_Msk                    /*!< ADC offset instance 3 unsigned saturation value */
+
+#define ADC_OFCFGR3_SSAT_Pos           (26U)
+#define ADC_OFCFGR3_SSAT_Msk           (0x01UL << ADC_OFCFGR3_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR3_SSAT               ADC_OFCFGR3_SSAT_Msk                    /*!< ADC offset instance 3 signed satuaration enable */
+
+#define ADC_OFCFGR3_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR3_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR3_OFFSET_CH          ADC_OFCFGR3_OFFSET_CH_Msk               /*!< ADC offset instance 3 channel selection for the data offset */
+#define ADC_OFCFGR3_OFFSET_CH_0        (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR3_OFFSET_CH_1        (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR3_OFFSET_CH_2        (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR3_OFFSET_CH_3        (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR3_OFFSET_CH_4        (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR4 register  ***************/
+#define ADC_OFCFGR4_POSOFF_Pos         (24U)
+#define ADC_OFCFGR4_POSOFF_Msk         (0x01UL << ADC_OFCFGR4_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR4_POSOFF             ADC_OFCFGR4_POSOFF_Msk                  /*!< ADC offset instance 4 positive offset enable */
+
+#define ADC_OFCFGR4_USAT_Pos           (25U)
+#define ADC_OFCFGR4_USAT_Msk           (0x01UL << ADC_OFCFGR4_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR4_USAT               ADC_OFCFGR4_USAT_Msk                    /*!< ADC offset instance 4 unsigned saturation value */
+
+#define ADC_OFCFGR4_SSAT_Pos           (26U)
+#define ADC_OFCFGR4_SSAT_Msk           (0x01UL << ADC_OFCFGR4_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR4_SSAT               ADC_OFCFGR4_SSAT_Msk                    /*!< ADC offset instance 4 signed satuaration enable */
+
+#define ADC_OFCFGR4_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR4_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR4_OFFSET_CH          ADC_OFCFGR4_OFFSET_CH_Msk               /*!< ADC offset instance 4 channel selection for the data offset */
+#define ADC_OFCFGR4_OFFSET_CH_0        (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR4_OFFSET_CH_1        (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR4_OFFSET_CH_2        (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR4_OFFSET_CH_3        (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR4_OFFSET_CH_4        (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET_Pos            (0U)
+#define ADC_OFR1_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR1_OFFSET                ADC_OFR1_OFFSET_Msk                     /*!< ADC offset instance 1 offset level */
+#define ADC_OFR1_OFFSET_0              (0x0000001UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET_1              (0x0000002UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET_2              (0x0000004UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET_3              (0x0000008UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET_4              (0x0000010UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET_5              (0x0000020UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET_6              (0x0000040UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET_7              (0x0000080UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET_8              (0x0000100UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET_9              (0x0000200UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET_10             (0x0000400UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET_11             (0x0000800UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET_12             (0x0001000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET_13             (0x0002000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET_14             (0x0004000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET_15             (0x0008000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET_16             (0x0010000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET_17             (0x0020000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET_18             (0x0040000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET_19             (0x0080000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET_20             (0x0100000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET_21             (0x0200000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET_Pos            (0U)
+#define ADC_OFR2_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR2_OFFSET                ADC_OFR2_OFFSET_Msk                     /*!< ADC offset instance 2 offset level */
+#define ADC_OFR2_OFFSET_0              (0x0000001UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET_1              (0x0000002UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET_2              (0x0000004UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET_3              (0x0000008UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET_4              (0x0000010UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET_5              (0x0000020UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET_6              (0x0000040UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET_7              (0x0000080UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET_8              (0x0000100UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET_9              (0x0000200UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET_10             (0x0000400UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET_11             (0x0000800UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET_12             (0x0001000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET_13             (0x0002000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET_14             (0x0004000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET_15             (0x0008000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET_16             (0x0010000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET_17             (0x0020000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET_18             (0x0040000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET_19             (0x0080000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET_20             (0x0100000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET_21             (0x0200000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET_Pos            (0U)
+#define ADC_OFR3_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR3_OFFSET                ADC_OFR3_OFFSET_Msk                     /*!< ADC offset instance 3 offset level */
+#define ADC_OFR3_OFFSET_0              (0x0000001UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET_1              (0x0000002UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET_2              (0x0000004UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET_3              (0x0000008UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET_4              (0x0000010UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET_5              (0x0000020UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET_6              (0x0000040UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET_7              (0x0000080UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET_8              (0x0000100UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET_9              (0x0000200UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET_10             (0x0000400UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET_11             (0x0000800UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET_12             (0x0001000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET_13             (0x0002000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET_14             (0x0004000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET_15             (0x0008000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET_16             (0x0010000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET_17             (0x0020000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET_18             (0x0040000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET_19             (0x0080000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET_20             (0x0100000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET_21             (0x0200000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET_Pos            (0U)
+#define ADC_OFR4_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR4_OFFSET                ADC_OFR4_OFFSET_Msk                     /*!< ADC offset instance 4 offset level */
+#define ADC_OFR4_OFFSET_0              (0x0000001UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET_1              (0x0000002UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET_2              (0x0000004UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET_3              (0x0000008UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET_4              (0x0000010UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET_5              (0x0000020UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET_6              (0x0000040UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET_7              (0x0000080UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET_8              (0x0000100UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET_9              (0x0000200UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET_10             (0x0000400UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET_11             (0x0000800UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET_12             (0x0001000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET_13             (0x0002000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET_14             (0x0004000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET_15             (0x0008000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET_16             (0x0010000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET_17             (0x0020000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET_18             (0x0040000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET_19             (0x0080000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET_20             (0x0100000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET_21             (0x0200000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_GCOMP register  *****************/
+#define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
+#define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< Gain compensation coefficient */
+#define ADC_GCOMP_GCOMP_Pos            (31U)
+#define ADC_GCOMP_GCOMP_Msk            (0x1UL << ADC_GCOMP_GCOMP_Pos)          /*!< 0x80000000 */
+#define ADC_GCOMP_GCOMP                ADC_GCOMP_GCOMP_Msk                     /*!< Gain compensation mode */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)
+#define ADC_JDR1_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x00000001UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x00000002UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x00000004UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x00000008UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x00000010UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x00000020UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x00000040UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x00000080UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x00000100UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x00000200UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x00000400UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x00000800UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x00001000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x00002000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x00004000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x00008000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16              (0x00010000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17              (0x00020000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18              (0x00040000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19              (0x00080000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20              (0x00100000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21              (0x00200000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22              (0x00400000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23              (0x00800000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24              (0x01000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25              (0x02000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26              (0x04000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27              (0x08000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28              (0x10000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29              (0x20000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30              (0x40000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31              (0x80000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos             (0U)
+#define ADC_JDR2_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x00000001UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x00000002UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x00000004UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x00000008UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x00000010UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x00000020UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x00000040UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x00000080UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x00000100UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x00000200UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x00000400UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x00000800UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x00001000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x00002000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x00004000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x00008000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16              (0x00010000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17              (0x00020000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18              (0x00040000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19              (0x00080000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20              (0x00100000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21              (0x00200000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22              (0x00400000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23              (0x00800000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24              (0x01000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25              (0x02000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26              (0x04000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27              (0x08000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28              (0x10000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29              (0x20000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30              (0x40000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31              (0x80000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos             (0U)
+#define ADC_JDR3_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x00000001UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x00000002UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x00000004UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x00000008UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x00000010UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x00000020UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x00000040UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x00000080UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x00000100UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x00000200UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x00000400UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x00000800UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x00001000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x00002000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x00004000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x00008000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16              (0x00010000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17              (0x00020000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18              (0x00040000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19              (0x00080000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20              (0x00100000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21              (0x00200000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22              (0x00400000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23              (0x00800000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24              (0x01000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25              (0x02000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26              (0x04000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27              (0x08000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28              (0x10000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29              (0x20000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30              (0x40000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31              (0x80000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos             (0U)
+#define ADC_JDR4_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x00000001UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x00000002UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x00000004UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x00000008UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x00000010UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x00000020UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x00000040UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x00000080UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x00000100UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x00000200UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x00000400UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x00000800UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x00001000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x00002000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x00004000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x00008000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16              (0x00010000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17              (0x00020000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18              (0x00040000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19              (0x00080000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20              (0x00100000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21              (0x00200000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22              (0x00400000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23              (0x00800000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24              (0x01000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25              (0x02000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26              (0x04000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27              (0x08000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28              (0x10000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29              (0x20000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30              (0x40000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31              (0x80000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)
+#define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)
+#define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19           (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD1TR_LT register  *************/
+#define ADC_AWD1LTR_LTR_Pos            (0U)
+#define ADC_AWD1LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1LTR_LTR                ADC_AWD1LTR_LTR_Msk                    /*!< ADC analog watchdog 1 threshold low */
+#define ADC_AWD1LTR_LTR_0              (0x000001UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1LTR_LTR_1              (0x000002UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1LTR_LTR_2              (0x000004UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1LTR_LTR_3              (0x000008UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1LTR_LTR_4              (0x000010UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1LTR_LTR_5              (0x000020UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1LTR_LTR_6              (0x000040UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1LTR_LTR_7              (0x000080UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1LTR_LTR_8              (0x000100UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1LTR_LTR_9              (0x000200UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1LTR_LTR_10             (0x000400UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1LTR_LTR_11             (0x000800UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1LTR_LTR_12             (0x001000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1LTR_LTR_13             (0x002000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1LTR_LTR_14             (0x004000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1LTR_LTR_15             (0x008000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1LTR_LTR_16             (0x010000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1LTR_LTR_17             (0x020000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1LTR_LTR_18             (0x040000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1LTR_LTR_19             (0x080000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1LTR_LTR_20             (0x100000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1LTR_LTR_21             (0x200000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1LTR_LTR_22             (0x400000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD1TR_HT register  *******************/
+#define ADC_AWD1HTR_HTR_Pos            (0U)
+#define ADC_AWD1HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1HTR_HTR                ADC_AWD1HTR_HTR_Msk                    /*!< ADC analog watchdog 1 threshold high */
+#define ADC_AWD1HTR_HTR_0              (0x000001UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1HTR_HTR_1              (0x000002UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1HTR_HTR_2              (0x000004UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1HTR_HTR_3              (0x000008UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1HTR_HTR_4              (0x000010UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1HTR_HTR_5              (0x000020UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1HTR_HTR_6              (0x000040UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1HTR_HTR_7              (0x000080UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1HTR_HTR_8              (0x000100UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1HTR_HTR_9              (0x000200UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1HTR_HTR_10             (0x000400UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1HTR_HTR_11             (0x000800UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1HTR_HTR_12             (0x001000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1HTR_HTR_13             (0x002000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1HTR_HTR_14             (0x004000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1HTR_HTR_15             (0x008000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1HTR_HTR_16             (0x010000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1HTR_HTR_17             (0x020000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1HTR_HTR_18             (0x040000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1HTR_HTR_19             (0x080000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1HTR_HTR_20             (0x100000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1HTR_HTR_21             (0x200000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1HTR_HTR_22             (0x400000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00400000 */
+
+#define ADC_AWD1HTR_AWDFILT_Pos         (29U)
+#define ADC_AWD1HTR_AWDFILT_Msk         (0x7UL << ADC_AWD1HTR_AWDFILT_Pos)      /*!< 0x00000007 */
+#define ADC_AWD1HTR_AWDFILT             ADC_AWD1HTR_AWDFILT_Msk                 /*!< ADC analog watchdog 1 filtering */
+#define ADC_AWD1HTR_AWDFILT_0           (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */
+#define ADC_AWD1HTR_AWDFILT_1           (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */
+#define ADC_AWD1HTR_AWDFILT_2           (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */
+
+/********************  Bit definition for ADC_AWD2TR_LT register  *******************/
+#define ADC_AWD2LTR_LTR_Pos            (0U)
+#define ADC_AWD2LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2LTR_LTR                ADC_AWD2LTR_LTR_Msk                    /*!< ADC analog watchdog 2 threshold low */
+#define ADC_AWD2LTR_LTR_0              (0x000001UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2LTR_LTR_1              (0x000002UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2LTR_LTR_2              (0x000004UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2LTR_LTR_3              (0x000008UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2LTR_LTR_4              (0x000010UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2LTR_LTR_5              (0x000020UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2LTR_LTR_6              (0x000040UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2LTR_LTR_7              (0x000080UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2LTR_LTR_8              (0x000100UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2LTR_LTR_9              (0x000200UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2LTR_LTR_10             (0x000400UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2LTR_LTR_11             (0x000800UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2LTR_LTR_12             (0x001000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2LTR_LTR_13             (0x002000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2LTR_LTR_14             (0x004000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2LTR_LTR_15             (0x008000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2LTR_LTR_16             (0x010000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2LTR_LTR_17             (0x020000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2LTR_LTR_18             (0x040000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2LTR_LTR_19             (0x080000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2LTR_LTR_20             (0x100000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2LTR_LTR_21             (0x200000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2LTR_LTR_22             (0x400000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD2TR_HT register  *******************/
+#define ADC_AWD2HTR_HTR_Pos            (0U)
+#define ADC_AWD2HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2HTR_HTR                ADC_AWD2HTR_HTR_Msk                    /*!< ADC analog watchdog 2 threshold high */
+#define ADC_AWD2HTR_HTR_0              (0x000001UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2HTR_HTR_1              (0x000002UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2HTR_HTR_2              (0x000004UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2HTR_HTR_3              (0x000008UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2HTR_HTR_4              (0x000010UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2HTR_HTR_5              (0x000020UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2HTR_HTR_6              (0x000040UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2HTR_HTR_7              (0x000080UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2HTR_HTR_8              (0x000100UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2HTR_HTR_9              (0x000200UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2HTR_HTR_10             (0x000400UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2HTR_HTR_11             (0x000800UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2HTR_HTR_12             (0x001000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2HTR_HTR_13             (0x002000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2HTR_HTR_14             (0x004000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2HTR_HTR_15             (0x008000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2HTR_HTR_16             (0x010000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2HTR_HTR_17             (0x020000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2HTR_HTR_18             (0x040000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2HTR_HTR_19             (0x080000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2HTR_HTR_20             (0x100000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2HTR_HTR_21             (0x200000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2HTR_HTR_22             (0x400000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_LT register  *******************/
+#define ADC_AWD3LTR_LTR_Pos            (0U)
+#define ADC_AWD3LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3LTR_LTR                ADC_AWD3LTR_LTR_Msk                    /*!< ADC analog watchdog 3 threshold low */
+#define ADC_AWD3LTR_LTR_0              (0x000001UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3LTR_LTR_1              (0x000002UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3LTR_LTR_2              (0x000004UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3LTR_LTR_3              (0x000008UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3LTR_LTR_4              (0x000010UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3LTR_LTR_5              (0x000020UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3LTR_LTR_6              (0x000040UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3LTR_LTR_7              (0x000080UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3LTR_LTR_8              (0x000100UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3LTR_LTR_9              (0x000200UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3LTR_LTR_10             (0x000400UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3LTR_LTR_11             (0x000800UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3LTR_LTR_12             (0x001000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3LTR_LTR_13             (0x002000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3LTR_LTR_14             (0x004000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3LTR_LTR_15             (0x008000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3LTR_LTR_16             (0x010000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3LTR_LTR_17             (0x020000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3LTR_LTR_18             (0x040000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3LTR_LTR_19             (0x080000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3LTR_LTR_20             (0x100000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3LTR_LTR_21             (0x200000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3LTR_LTR_22             (0x400000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_HT register  *******************/
+#define ADC_AWD3HTR_HTR_Pos            (0U)
+#define ADC_AWD3HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3HTR_HTR                ADC_AWD3HTR_HTR_Msk                    /*!< ADC analog watchdog 3 threshold high */
+#define ADC_AWD3HTR_HTR_0              (0x000001UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3HTR_HTR_1              (0x000002UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3HTR_HTR_2              (0x000004UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3HTR_HTR_3              (0x000008UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3HTR_HTR_4              (0x000010UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3HTR_HTR_5              (0x000020UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3HTR_HTR_6              (0x000040UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3HTR_HTR_7              (0x000080UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3HTR_HTR_8              (0x000100UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3HTR_HTR_9              (0x000200UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3HTR_HTR_10             (0x000400UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3HTR_HTR_11             (0x000800UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3HTR_HTR_12             (0x001000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3HTR_HTR_13             (0x002000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3HTR_HTR_14             (0x004000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3HTR_HTR_15             (0x008000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3HTR_HTR_16             (0x010000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3HTR_HTR_17             (0x020000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3HTR_HTR_18             (0x040000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3HTR_HTR_19             (0x080000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3HTR_HTR_20             (0x100000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3HTR_HTR_21             (0x200000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3HTR_HTR_22             (0x400000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)
+#define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode selection */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)
+#define ADC_CALFACT_CALFACT_S_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos)  /*!< 0x000003FF */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7        (0x80UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8        (0x100UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9        (0x200UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000200 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)
+#define ADC_CALFACT_CALFACT_D_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos)  /*!< 0x03FF0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7        (0x80UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8        (0x100UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9        (0x200UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x02000000 */
+
+#define ADC_CALFACT_CALADDOS_Pos       (31U)
+#define ADC_CALFACT_CALADDOS_Msk       (0x01UL << ADC_CALFACT_CALADDOS_Pos)    /*!< 0x80000000 */
+#define ADC_CALFACT_CALADDOS           ADC_CALFACT_CALADDOS_Msk                /*!< ADC calibration additional offset mode */
+
+/********************  Bit definition for ADC_OR option register  ***************/
+#define ADC_OR_OP0_Pos                 (0U)
+#define ADC_OR_OP0_Msk                 (0x1UL << ADC_OR_OP0_Pos)               /*!< 0x00000001 */
+#define ADC_OR_OP0                     ADC_OR_OP0_Msk                          /*!< ADC internal reference voltage buffer */
+
+#define ADC_OR_OP1_Pos                 (1U)
+#define ADC_OR_OP1_Msk                 (0x1UL << ADC_OR_OP1_Pos)               /*!< 0x00000002 */
+#define ADC_OR_OP1                     ADC_OR_OP1_Msk                          /*!< ADC internal bandgap */
+
+#define ADC_OR_OP2_Pos                 (2U)
+#define ADC_OR_OP2_Msk                 (0x1UL << ADC_OR_OP2_Pos)               /*!< 0x00000004 */
+#define ADC_OR_OP2                     ADC_OR_OP2_Msk                          /*!< ADC internal path to VDDCORE */
+
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)
+#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)
+#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)
+#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)
+#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)
+#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)
+#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)
+#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)
+#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)
+#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)
+#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)
+#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)
+#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)
+#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)
+#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)
+#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)
+#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)
+#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)
+#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)
+#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)
+#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
+
+#define ADC_CCR_DAMDF_Pos              (14U)
+#define ADC_CCR_DAMDF_Msk              (0x3UL << ADC_CCR_DAMDF_Pos)            /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                  ADC_CCR_DAMDF_Msk                       /*!< ADC multimode data format */
+#define ADC_CCR_DAMDF_0                (0x1UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                (0x2UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00008000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)
+#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+
+#define ADC_CCR_VBATEN_Pos             (24U)
+#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos         (0U)
+#define ADC_CDR2_RDATA_ALT_Msk         (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT             ADC_CDR2_RDATA_ALT_Msk                   /*!< ADC multimode master or slave (alternated) group regular conversion data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       BSEC unit (Boot and Security)                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for BSEC_FVRw register  *******************/
+#define BSEC_FVRw_FV_Pos               (0U)
+#define BSEC_FVRw_FV_Msk               (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos)           /*!< 0xFFFFFFFF */
+#define BSEC_FVRw_FV                   BSEC_FVRw_FV_Msk                            /*!< Fuse value */
+
+/*****************  Bit definition for BSEC_SPLOCKx register  *****************/
+#define BSEC_SPLOCKx_SPLOCK0_Pos       (0U)
+#define BSEC_SPLOCKx_SPLOCK0_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SPLOCKx_SPLOCK0           BSEC_SPLOCKx_SPLOCK0_Msk                    /*!< Sticky programming lock for word (32*x) */
+#define BSEC_SPLOCKx_SPLOCK1_Pos       (1U)
+#define BSEC_SPLOCKx_SPLOCK1_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SPLOCKx_SPLOCK1           BSEC_SPLOCKx_SPLOCK1_Msk                    /*!< Sticky programming lock for word (1+32*x) */
+#define BSEC_SPLOCKx_SPLOCK2_Pos       (2U)
+#define BSEC_SPLOCKx_SPLOCK2_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SPLOCKx_SPLOCK2           BSEC_SPLOCKx_SPLOCK2_Msk                    /*!< Sticky programming lock for word (2+32*x) */
+#define BSEC_SPLOCKx_SPLOCK3_Pos       (3U)
+#define BSEC_SPLOCKx_SPLOCK3_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SPLOCKx_SPLOCK3           BSEC_SPLOCKx_SPLOCK3_Msk                    /*!< Sticky programming lock for word (3+32*x) */
+#define BSEC_SPLOCKx_SPLOCK4_Pos       (4U)
+#define BSEC_SPLOCKx_SPLOCK4_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SPLOCKx_SPLOCK4           BSEC_SPLOCKx_SPLOCK4_Msk                    /*!< Sticky programming lock for word (4+32*x) */
+#define BSEC_SPLOCKx_SPLOCK5_Pos       (5U)
+#define BSEC_SPLOCKx_SPLOCK5_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SPLOCKx_SPLOCK5           BSEC_SPLOCKx_SPLOCK5_Msk                    /*!< Sticky programming lock for word (5+32*x) */
+#define BSEC_SPLOCKx_SPLOCK6_Pos       (6U)
+#define BSEC_SPLOCKx_SPLOCK6_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SPLOCKx_SPLOCK6           BSEC_SPLOCKx_SPLOCK6_Msk                    /*!< Sticky programming lock for word (6+32*x) */
+#define BSEC_SPLOCKx_SPLOCK7_Pos       (7U)
+#define BSEC_SPLOCKx_SPLOCK7_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SPLOCKx_SPLOCK7           BSEC_SPLOCKx_SPLOCK7_Msk                    /*!< Sticky programming lock for word (7+32*x) */
+#define BSEC_SPLOCKx_SPLOCK8_Pos       (8U)
+#define BSEC_SPLOCKx_SPLOCK8_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SPLOCKx_SPLOCK8           BSEC_SPLOCKx_SPLOCK8_Msk                    /*!< Sticky programming lock for word (8+32*x) */
+#define BSEC_SPLOCKx_SPLOCK9_Pos       (9U)
+#define BSEC_SPLOCKx_SPLOCK9_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SPLOCKx_SPLOCK9           BSEC_SPLOCKx_SPLOCK9_Msk                    /*!< Sticky programming lock for word (9+32*x) */
+#define BSEC_SPLOCKx_SPLOCK10_Pos      (10U)
+#define BSEC_SPLOCKx_SPLOCK10_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SPLOCKx_SPLOCK10          BSEC_SPLOCKx_SPLOCK10_Msk                   /*!< Sticky programming lock for word (10+32*x) */
+#define BSEC_SPLOCKx_SPLOCK11_Pos      (11U)
+#define BSEC_SPLOCKx_SPLOCK11_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SPLOCKx_SPLOCK11          BSEC_SPLOCKx_SPLOCK11_Msk                   /*!< Sticky programming lock for word (11+32*x) */
+#define BSEC_SPLOCKx_SPLOCK12_Pos      (12U)
+#define BSEC_SPLOCKx_SPLOCK12_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SPLOCKx_SPLOCK12          BSEC_SPLOCKx_SPLOCK12_Msk                   /*!< Sticky programming lock for word (12+32*x) */
+#define BSEC_SPLOCKx_SPLOCK13_Pos      (13U)
+#define BSEC_SPLOCKx_SPLOCK13_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SPLOCKx_SPLOCK13          BSEC_SPLOCKx_SPLOCK13_Msk                   /*!< Sticky programming lock for word (13+32*x) */
+#define BSEC_SPLOCKx_SPLOCK14_Pos      (14U)
+#define BSEC_SPLOCKx_SPLOCK14_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SPLOCKx_SPLOCK14          BSEC_SPLOCKx_SPLOCK14_Msk                   /*!< Sticky programming lock for word (14+32*x) */
+#define BSEC_SPLOCKx_SPLOCK15_Pos      (15U)
+#define BSEC_SPLOCKx_SPLOCK15_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SPLOCKx_SPLOCK15          BSEC_SPLOCKx_SPLOCK15_Msk                   /*!< Sticky programming lock for word (15+32*x) */
+#define BSEC_SPLOCKx_SPLOCK16_Pos      (16U)
+#define BSEC_SPLOCKx_SPLOCK16_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SPLOCKx_SPLOCK16          BSEC_SPLOCKx_SPLOCK16_Msk                   /*!< Sticky programming lock for word (16+32*x) */
+#define BSEC_SPLOCKx_SPLOCK17_Pos      (17U)
+#define BSEC_SPLOCKx_SPLOCK17_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SPLOCKx_SPLOCK17          BSEC_SPLOCKx_SPLOCK17_Msk                   /*!< Sticky programming lock for word (17+32*x) */
+#define BSEC_SPLOCKx_SPLOCK18_Pos      (18U)
+#define BSEC_SPLOCKx_SPLOCK18_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SPLOCKx_SPLOCK18          BSEC_SPLOCKx_SPLOCK18_Msk                   /*!< Sticky programming lock for word (18+32*x) */
+#define BSEC_SPLOCKx_SPLOCK19_Pos      (19U)
+#define BSEC_SPLOCKx_SPLOCK19_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SPLOCKx_SPLOCK19          BSEC_SPLOCKx_SPLOCK19_Msk                   /*!< Sticky programming lock for word (19+32*x) */
+#define BSEC_SPLOCKx_SPLOCK20_Pos      (20U)
+#define BSEC_SPLOCKx_SPLOCK20_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SPLOCKx_SPLOCK20          BSEC_SPLOCKx_SPLOCK20_Msk                   /*!< Sticky programming lock for word (20+32*x) */
+#define BSEC_SPLOCKx_SPLOCK21_Pos      (21U)
+#define BSEC_SPLOCKx_SPLOCK21_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SPLOCKx_SPLOCK21          BSEC_SPLOCKx_SPLOCK21_Msk                   /*!< Sticky programming lock for word (21+32*x) */
+#define BSEC_SPLOCKx_SPLOCK22_Pos      (22U)
+#define BSEC_SPLOCKx_SPLOCK22_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SPLOCKx_SPLOCK22          BSEC_SPLOCKx_SPLOCK22_Msk                   /*!< Sticky programming lock for word (22+32*x) */
+#define BSEC_SPLOCKx_SPLOCK23_Pos      (23U)
+#define BSEC_SPLOCKx_SPLOCK23_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SPLOCKx_SPLOCK23          BSEC_SPLOCKx_SPLOCK23_Msk                   /*!< Sticky programming lock for word (23+32*x) */
+#define BSEC_SPLOCKx_SPLOCK24_Pos      (24U)
+#define BSEC_SPLOCKx_SPLOCK24_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SPLOCKx_SPLOCK24          BSEC_SPLOCKx_SPLOCK24_Msk                   /*!< Sticky programming lock for word (24+32*x) */
+#define BSEC_SPLOCKx_SPLOCK25_Pos      (25U)
+#define BSEC_SPLOCKx_SPLOCK25_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SPLOCKx_SPLOCK25          BSEC_SPLOCKx_SPLOCK25_Msk                   /*!< Sticky programming lock for word (25+32*x) */
+#define BSEC_SPLOCKx_SPLOCK26_Pos      (26U)
+#define BSEC_SPLOCKx_SPLOCK26_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SPLOCKx_SPLOCK26          BSEC_SPLOCKx_SPLOCK26_Msk                   /*!< Sticky programming lock for word (26+32*x) */
+#define BSEC_SPLOCKx_SPLOCK27_Pos      (27U)
+#define BSEC_SPLOCKx_SPLOCK27_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SPLOCKx_SPLOCK27          BSEC_SPLOCKx_SPLOCK27_Msk                   /*!< Sticky programming lock for word (27+32*x) */
+#define BSEC_SPLOCKx_SPLOCK28_Pos      (28U)
+#define BSEC_SPLOCKx_SPLOCK28_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SPLOCKx_SPLOCK28          BSEC_SPLOCKx_SPLOCK28_Msk                   /*!< Sticky programming lock for word (28+32*x) */
+#define BSEC_SPLOCKx_SPLOCK29_Pos      (29U)
+#define BSEC_SPLOCKx_SPLOCK29_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SPLOCKx_SPLOCK29          BSEC_SPLOCKx_SPLOCK29_Msk                   /*!< Sticky programming lock for word (29+32*x) */
+#define BSEC_SPLOCKx_SPLOCK30_Pos      (30U)
+#define BSEC_SPLOCKx_SPLOCK30_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SPLOCKx_SPLOCK30          BSEC_SPLOCKx_SPLOCK30_Msk                   /*!< Sticky programming lock for word (30+32*x) */
+#define BSEC_SPLOCKx_SPLOCK31_Pos      (31U)
+#define BSEC_SPLOCKx_SPLOCK31_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SPLOCKx_SPLOCK31          BSEC_SPLOCKx_SPLOCK31_Msk                   /*!< Sticky programming lock for word (31+32*x) */
+
+/*****************  Bit definition for BSEC_SWLOCKx register  *****************/
+#define BSEC_SWLOCKx_SWLOCK0_Pos       (0U)
+#define BSEC_SWLOCKx_SWLOCK0_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SWLOCKx_SWLOCK0           BSEC_SWLOCKx_SWLOCK0_Msk                    /*!< Sticky write lock for shadow register (32*x) */
+#define BSEC_SWLOCKx_SWLOCK1_Pos       (1U)
+#define BSEC_SWLOCKx_SWLOCK1_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SWLOCKx_SWLOCK1           BSEC_SWLOCKx_SWLOCK1_Msk                    /*!< Sticky write lock for shadow register (1+32*x) */
+#define BSEC_SWLOCKx_SWLOCK2_Pos       (2U)
+#define BSEC_SWLOCKx_SWLOCK2_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SWLOCKx_SWLOCK2           BSEC_SWLOCKx_SWLOCK2_Msk                    /*!< Sticky write lock for shadow register (2+32*x) */
+#define BSEC_SWLOCKx_SWLOCK3_Pos       (3U)
+#define BSEC_SWLOCKx_SWLOCK3_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SWLOCKx_SWLOCK3           BSEC_SWLOCKx_SWLOCK3_Msk                    /*!< Sticky write lock for shadow register (3+32*x) */
+#define BSEC_SWLOCKx_SWLOCK4_Pos       (4U)
+#define BSEC_SWLOCKx_SWLOCK4_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SWLOCKx_SWLOCK4           BSEC_SWLOCKx_SWLOCK4_Msk                    /*!< Sticky write lock for shadow register (4+32*x) */
+#define BSEC_SWLOCKx_SWLOCK5_Pos       (5U)
+#define BSEC_SWLOCKx_SWLOCK5_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SWLOCKx_SWLOCK5           BSEC_SWLOCKx_SWLOCK5_Msk                    /*!< Sticky write lock for shadow register (5+32*x) */
+#define BSEC_SWLOCKx_SWLOCK6_Pos       (6U)
+#define BSEC_SWLOCKx_SWLOCK6_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SWLOCKx_SWLOCK6           BSEC_SWLOCKx_SWLOCK6_Msk                    /*!< Sticky write lock for shadow register (6+32*x) */
+#define BSEC_SWLOCKx_SWLOCK7_Pos       (7U)
+#define BSEC_SWLOCKx_SWLOCK7_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SWLOCKx_SWLOCK7           BSEC_SWLOCKx_SWLOCK7_Msk                    /*!< Sticky write lock for shadow register (7+32*x) */
+#define BSEC_SWLOCKx_SWLOCK8_Pos       (8U)
+#define BSEC_SWLOCKx_SWLOCK8_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SWLOCKx_SWLOCK8           BSEC_SWLOCKx_SWLOCK8_Msk                    /*!< Sticky write lock for shadow register (8+32*x) */
+#define BSEC_SWLOCKx_SWLOCK9_Pos       (9U)
+#define BSEC_SWLOCKx_SWLOCK9_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SWLOCKx_SWLOCK9           BSEC_SWLOCKx_SWLOCK9_Msk                    /*!< Sticky write lock for shadow register (9+32*x) */
+#define BSEC_SWLOCKx_SWLOCK10_Pos      (10U)
+#define BSEC_SWLOCKx_SWLOCK10_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SWLOCKx_SWLOCK10          BSEC_SWLOCKx_SWLOCK10_Msk                   /*!< Sticky write lock for shadow register (10+32*x) */
+#define BSEC_SWLOCKx_SWLOCK11_Pos      (11U)
+#define BSEC_SWLOCKx_SWLOCK11_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SWLOCKx_SWLOCK11          BSEC_SWLOCKx_SWLOCK11_Msk                   /*!< Sticky write lock for shadow register (11+32*x) */
+#define BSEC_SWLOCKx_SWLOCK12_Pos      (12U)
+#define BSEC_SWLOCKx_SWLOCK12_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SWLOCKx_SWLOCK12          BSEC_SWLOCKx_SWLOCK12_Msk                   /*!< Sticky write lock for shadow register (12+32*x) */
+#define BSEC_SWLOCKx_SWLOCK13_Pos      (13U)
+#define BSEC_SWLOCKx_SWLOCK13_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SWLOCKx_SWLOCK13          BSEC_SWLOCKx_SWLOCK13_Msk                   /*!< Sticky write lock for shadow register (13+32*x) */
+#define BSEC_SWLOCKx_SWLOCK14_Pos      (14U)
+#define BSEC_SWLOCKx_SWLOCK14_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SWLOCKx_SWLOCK14          BSEC_SWLOCKx_SWLOCK14_Msk                   /*!< Sticky write lock for shadow register (14+32*x) */
+#define BSEC_SWLOCKx_SWLOCK15_Pos      (15U)
+#define BSEC_SWLOCKx_SWLOCK15_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SWLOCKx_SWLOCK15          BSEC_SWLOCKx_SWLOCK15_Msk                   /*!< Sticky write lock for shadow register (15+32*x) */
+#define BSEC_SWLOCKx_SWLOCK16_Pos      (16U)
+#define BSEC_SWLOCKx_SWLOCK16_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SWLOCKx_SWLOCK16          BSEC_SWLOCKx_SWLOCK16_Msk                   /*!< Sticky write lock for shadow register (16+32*x) */
+#define BSEC_SWLOCKx_SWLOCK17_Pos      (17U)
+#define BSEC_SWLOCKx_SWLOCK17_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SWLOCKx_SWLOCK17          BSEC_SWLOCKx_SWLOCK17_Msk                   /*!< Sticky write lock for shadow register (17+32*x) */
+#define BSEC_SWLOCKx_SWLOCK18_Pos      (18U)
+#define BSEC_SWLOCKx_SWLOCK18_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SWLOCKx_SWLOCK18          BSEC_SWLOCKx_SWLOCK18_Msk                   /*!< Sticky write lock for shadow register (18+32*x) */
+#define BSEC_SWLOCKx_SWLOCK19_Pos      (19U)
+#define BSEC_SWLOCKx_SWLOCK19_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SWLOCKx_SWLOCK19          BSEC_SWLOCKx_SWLOCK19_Msk                   /*!< Sticky write lock for shadow register (19+32*x) */
+#define BSEC_SWLOCKx_SWLOCK20_Pos      (20U)
+#define BSEC_SWLOCKx_SWLOCK20_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SWLOCKx_SWLOCK20          BSEC_SWLOCKx_SWLOCK20_Msk                   /*!< Sticky write lock for shadow register (20+32*x) */
+#define BSEC_SWLOCKx_SWLOCK21_Pos      (21U)
+#define BSEC_SWLOCKx_SWLOCK21_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SWLOCKx_SWLOCK21          BSEC_SWLOCKx_SWLOCK21_Msk                   /*!< Sticky write lock for shadow register (21+32*x) */
+#define BSEC_SWLOCKx_SWLOCK22_Pos      (22U)
+#define BSEC_SWLOCKx_SWLOCK22_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SWLOCKx_SWLOCK22          BSEC_SWLOCKx_SWLOCK22_Msk                   /*!< Sticky write lock for shadow register (22+32*x) */
+#define BSEC_SWLOCKx_SWLOCK23_Pos      (23U)
+#define BSEC_SWLOCKx_SWLOCK23_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SWLOCKx_SWLOCK23          BSEC_SWLOCKx_SWLOCK23_Msk                   /*!< Sticky write lock for shadow register (23+32*x) */
+#define BSEC_SWLOCKx_SWLOCK24_Pos      (24U)
+#define BSEC_SWLOCKx_SWLOCK24_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SWLOCKx_SWLOCK24          BSEC_SWLOCKx_SWLOCK24_Msk                   /*!< Sticky write lock for shadow register (24+32*x) */
+#define BSEC_SWLOCKx_SWLOCK25_Pos      (25U)
+#define BSEC_SWLOCKx_SWLOCK25_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SWLOCKx_SWLOCK25          BSEC_SWLOCKx_SWLOCK25_Msk                   /*!< Sticky write lock for shadow register (25+32*x) */
+#define BSEC_SWLOCKx_SWLOCK26_Pos      (26U)
+#define BSEC_SWLOCKx_SWLOCK26_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SWLOCKx_SWLOCK26          BSEC_SWLOCKx_SWLOCK26_Msk                   /*!< Sticky write lock for shadow register (26+32*x) */
+#define BSEC_SWLOCKx_SWLOCK27_Pos      (27U)
+#define BSEC_SWLOCKx_SWLOCK27_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SWLOCKx_SWLOCK27          BSEC_SWLOCKx_SWLOCK27_Msk                   /*!< Sticky write lock for shadow register (27+32*x) */
+#define BSEC_SWLOCKx_SWLOCK28_Pos      (28U)
+#define BSEC_SWLOCKx_SWLOCK28_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SWLOCKx_SWLOCK28          BSEC_SWLOCKx_SWLOCK28_Msk                   /*!< Sticky write lock for shadow register (28+32*x) */
+#define BSEC_SWLOCKx_SWLOCK29_Pos      (29U)
+#define BSEC_SWLOCKx_SWLOCK29_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SWLOCKx_SWLOCK29          BSEC_SWLOCKx_SWLOCK29_Msk                   /*!< Sticky write lock for shadow register (29+32*x) */
+#define BSEC_SWLOCKx_SWLOCK30_Pos      (30U)
+#define BSEC_SWLOCKx_SWLOCK30_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SWLOCKx_SWLOCK30          BSEC_SWLOCKx_SWLOCK30_Msk                   /*!< Sticky write lock for shadow register (30+32*x) */
+#define BSEC_SWLOCKx_SWLOCK31_Pos      (31U)
+#define BSEC_SWLOCKx_SWLOCK31_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SWLOCKx_SWLOCK31          BSEC_SWLOCKx_SWLOCK31_Msk                   /*!< Sticky write lock for shadow register (31+32*x) */
+
+/*****************  Bit definition for BSEC_SRLOCKx register  *****************/
+#define BSEC_SRLOCKx_SRLOCK0_Pos       (0U)
+#define BSEC_SRLOCKx_SRLOCK0_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SRLOCKx_SRLOCK0           BSEC_SRLOCKx_SRLOCK0_Msk                    /*!< Sticky reload lock for fuse word (32*x) */
+#define BSEC_SRLOCKx_SRLOCK1_Pos       (1U)
+#define BSEC_SRLOCKx_SRLOCK1_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SRLOCKx_SRLOCK1           BSEC_SRLOCKx_SRLOCK1_Msk                    /*!< Sticky reload lock for fuse word (1+32*x) */
+#define BSEC_SRLOCKx_SRLOCK2_Pos       (2U)
+#define BSEC_SRLOCKx_SRLOCK2_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SRLOCKx_SRLOCK2           BSEC_SRLOCKx_SRLOCK2_Msk                    /*!< Sticky reload lock for fuse word (2+32*x) */
+#define BSEC_SRLOCKx_SRLOCK3_Pos       (3U)
+#define BSEC_SRLOCKx_SRLOCK3_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SRLOCKx_SRLOCK3           BSEC_SRLOCKx_SRLOCK3_Msk                    /*!< Sticky reload lock for fuse word (3+32*x) */
+#define BSEC_SRLOCKx_SRLOCK4_Pos       (4U)
+#define BSEC_SRLOCKx_SRLOCK4_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SRLOCKx_SRLOCK4           BSEC_SRLOCKx_SRLOCK4_Msk                    /*!< Sticky reload lock for fuse word (4+32*x) */
+#define BSEC_SRLOCKx_SRLOCK5_Pos       (5U)
+#define BSEC_SRLOCKx_SRLOCK5_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SRLOCKx_SRLOCK5           BSEC_SRLOCKx_SRLOCK5_Msk                    /*!< Sticky reload lock for fuse word (5+32*x) */
+#define BSEC_SRLOCKx_SRLOCK6_Pos       (6U)
+#define BSEC_SRLOCKx_SRLOCK6_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SRLOCKx_SRLOCK6           BSEC_SRLOCKx_SRLOCK6_Msk                    /*!< Sticky reload lock for fuse word (6+32*x) */
+#define BSEC_SRLOCKx_SRLOCK7_Pos       (7U)
+#define BSEC_SRLOCKx_SRLOCK7_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SRLOCKx_SRLOCK7           BSEC_SRLOCKx_SRLOCK7_Msk                    /*!< Sticky reload lock for fuse word (7+32*x) */
+#define BSEC_SRLOCKx_SRLOCK8_Pos       (8U)
+#define BSEC_SRLOCKx_SRLOCK8_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SRLOCKx_SRLOCK8           BSEC_SRLOCKx_SRLOCK8_Msk                    /*!< Sticky reload lock for fuse word (8+32*x) */
+#define BSEC_SRLOCKx_SRLOCK9_Pos       (9U)
+#define BSEC_SRLOCKx_SRLOCK9_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SRLOCKx_SRLOCK9           BSEC_SRLOCKx_SRLOCK9_Msk                    /*!< Sticky reload lock for fuse word (9+32*x) */
+#define BSEC_SRLOCKx_SRLOCK10_Pos      (10U)
+#define BSEC_SRLOCKx_SRLOCK10_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SRLOCKx_SRLOCK10          BSEC_SRLOCKx_SRLOCK10_Msk                   /*!< Sticky reload lock for fuse word (10+2*x) */
+#define BSEC_SRLOCKx_SRLOCK11_Pos      (11U)
+#define BSEC_SRLOCKx_SRLOCK11_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SRLOCKx_SRLOCK11          BSEC_SRLOCKx_SRLOCK11_Msk                   /*!< Sticky reload lock for fuse word (11+32*x) */
+#define BSEC_SRLOCKx_SRLOCK12_Pos      (12U)
+#define BSEC_SRLOCKx_SRLOCK12_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SRLOCKx_SRLOCK12          BSEC_SRLOCKx_SRLOCK12_Msk                   /*!< Sticky reload lock for fuse word (12+32*x) */
+#define BSEC_SRLOCKx_SRLOCK13_Pos      (13U)
+#define BSEC_SRLOCKx_SRLOCK13_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SRLOCKx_SRLOCK13          BSEC_SRLOCKx_SRLOCK13_Msk                   /*!< Sticky reload lock for fuse word (13+32*x) */
+#define BSEC_SRLOCKx_SRLOCK14_Pos      (14U)
+#define BSEC_SRLOCKx_SRLOCK14_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SRLOCKx_SRLOCK14          BSEC_SRLOCKx_SRLOCK14_Msk                   /*!< Sticky reload lock for fuse word (14+32*x) */
+#define BSEC_SRLOCKx_SRLOCK15_Pos      (15U)
+#define BSEC_SRLOCKx_SRLOCK15_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SRLOCKx_SRLOCK15          BSEC_SRLOCKx_SRLOCK15_Msk                   /*!< Sticky reload lock for fuse word (15+32*x) */
+#define BSEC_SRLOCKx_SRLOCK16_Pos      (16U)
+#define BSEC_SRLOCKx_SRLOCK16_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SRLOCKx_SRLOCK16          BSEC_SRLOCKx_SRLOCK16_Msk                   /*!< Sticky reload lock for fuse word (16+32*x) */
+#define BSEC_SRLOCKx_SRLOCK17_Pos      (17U)
+#define BSEC_SRLOCKx_SRLOCK17_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SRLOCKx_SRLOCK17          BSEC_SRLOCKx_SRLOCK17_Msk                   /*!< Sticky reload lock for fuse word (17+32*x) */
+#define BSEC_SRLOCKx_SRLOCK18_Pos      (18U)
+#define BSEC_SRLOCKx_SRLOCK18_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SRLOCKx_SRLOCK18          BSEC_SRLOCKx_SRLOCK18_Msk                   /*!< Sticky reload lock for fuse word (18+32*x) */
+#define BSEC_SRLOCKx_SRLOCK19_Pos      (19U)
+#define BSEC_SRLOCKx_SRLOCK19_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SRLOCKx_SRLOCK19          BSEC_SRLOCKx_SRLOCK19_Msk                   /*!< Sticky reload lock for fuse word (19+32*x) */
+#define BSEC_SRLOCKx_SRLOCK20_Pos      (20U)
+#define BSEC_SRLOCKx_SRLOCK20_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SRLOCKx_SRLOCK20          BSEC_SRLOCKx_SRLOCK20_Msk                   /*!< Sticky reload lock for fuse word (20+32*x) */
+#define BSEC_SRLOCKx_SRLOCK21_Pos      (21U)
+#define BSEC_SRLOCKx_SRLOCK21_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SRLOCKx_SRLOCK21          BSEC_SRLOCKx_SRLOCK21_Msk                   /*!< Sticky reload lock for fuse word (21+32*x) */
+#define BSEC_SRLOCKx_SRLOCK22_Pos      (22U)
+#define BSEC_SRLOCKx_SRLOCK22_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SRLOCKx_SRLOCK22          BSEC_SRLOCKx_SRLOCK22_Msk                   /*!< Sticky reload lock for fuse word (22+32*x) */
+#define BSEC_SRLOCKx_SRLOCK23_Pos      (23U)
+#define BSEC_SRLOCKx_SRLOCK23_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SRLOCKx_SRLOCK23          BSEC_SRLOCKx_SRLOCK23_Msk                   /*!< Sticky reload lock for fuse word (23+32*x) */
+#define BSEC_SRLOCKx_SRLOCK24_Pos      (24U)
+#define BSEC_SRLOCKx_SRLOCK24_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SRLOCKx_SRLOCK24          BSEC_SRLOCKx_SRLOCK24_Msk                   /*!< Sticky reload lock for fuse word (24+32*x) */
+#define BSEC_SRLOCKx_SRLOCK25_Pos      (25U)
+#define BSEC_SRLOCKx_SRLOCK25_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SRLOCKx_SRLOCK25          BSEC_SRLOCKx_SRLOCK25_Msk                   /*!< Sticky reload lock for fuse word (25+32*x) */
+#define BSEC_SRLOCKx_SRLOCK26_Pos      (26U)
+#define BSEC_SRLOCKx_SRLOCK26_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SRLOCKx_SRLOCK26          BSEC_SRLOCKx_SRLOCK26_Msk                   /*!< Sticky reload lock for fuse word (26+32*x) */
+#define BSEC_SRLOCKx_SRLOCK27_Pos      (27U)
+#define BSEC_SRLOCKx_SRLOCK27_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SRLOCKx_SRLOCK27          BSEC_SRLOCKx_SRLOCK27_Msk                   /*!< Sticky reload lock for fuse word (27+32*x) */
+#define BSEC_SRLOCKx_SRLOCK28_Pos      (28U)
+#define BSEC_SRLOCKx_SRLOCK28_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SRLOCKx_SRLOCK28          BSEC_SRLOCKx_SRLOCK28_Msk                   /*!< Sticky reload lock for fuse word (28+32*x) */
+#define BSEC_SRLOCKx_SRLOCK29_Pos      (29U)
+#define BSEC_SRLOCKx_SRLOCK29_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SRLOCKx_SRLOCK29          BSEC_SRLOCKx_SRLOCK29_Msk                   /*!< Sticky reload lock for fuse word (29+32*x) */
+#define BSEC_SRLOCKx_SRLOCK30_Pos      (30U)
+#define BSEC_SRLOCKx_SRLOCK30_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SRLOCKx_SRLOCK30          BSEC_SRLOCKx_SRLOCK30_Msk                   /*!< Sticky reload lock for fuse word (30+32*x) */
+#define BSEC_SRLOCKx_SRLOCK31_Pos      (31U)
+#define BSEC_SRLOCKx_SRLOCK31_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SRLOCKx_SRLOCK31          BSEC_SRLOCKx_SRLOCK31_Msk                   /*!< Sticky reload lock for fuse word (31+32*x) */
+
+/****************  Bit definition for BSEC_OTPVLDRx register  *****************/
+#define BSEC_OTPVLDRx_VLDF0_Pos        (0U)
+#define BSEC_OTPVLDRx_VLDF0_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos)           /*!< 0x00000001 */
+#define BSEC_OTPVLDRx_VLDF0            BSEC_OTPVLDRx_VLDF0_Msk                     /*!< Valid flag for shadow register (32*x) */
+#define BSEC_OTPVLDRx_VLDF1_Pos        (1U)
+#define BSEC_OTPVLDRx_VLDF1_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos)           /*!< 0x00000002 */
+#define BSEC_OTPVLDRx_VLDF1            BSEC_OTPVLDRx_VLDF1_Msk                     /*!< Valid flag for shadow register (1+32*x) */
+#define BSEC_OTPVLDRx_VLDF2_Pos        (2U)
+#define BSEC_OTPVLDRx_VLDF2_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos)           /*!< 0x00000004 */
+#define BSEC_OTPVLDRx_VLDF2            BSEC_OTPVLDRx_VLDF2_Msk                     /*!< Valid flag for shadow register (2+32*x) */
+#define BSEC_OTPVLDRx_VLDF3_Pos        (3U)
+#define BSEC_OTPVLDRx_VLDF3_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos)           /*!< 0x00000008 */
+#define BSEC_OTPVLDRx_VLDF3            BSEC_OTPVLDRx_VLDF3_Msk                     /*!< Valid flag for shadow register (3+32*x) */
+#define BSEC_OTPVLDRx_VLDF4_Pos        (4U)
+#define BSEC_OTPVLDRx_VLDF4_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos)           /*!< 0x00000010 */
+#define BSEC_OTPVLDRx_VLDF4            BSEC_OTPVLDRx_VLDF4_Msk                     /*!< Valid flag for shadow register (4+32*x) */
+#define BSEC_OTPVLDRx_VLDF5_Pos        (5U)
+#define BSEC_OTPVLDRx_VLDF5_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos)           /*!< 0x00000020 */
+#define BSEC_OTPVLDRx_VLDF5            BSEC_OTPVLDRx_VLDF5_Msk                     /*!< Valid flag for shadow register (5+32*x) */
+#define BSEC_OTPVLDRx_VLDF6_Pos        (6U)
+#define BSEC_OTPVLDRx_VLDF6_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos)           /*!< 0x00000040 */
+#define BSEC_OTPVLDRx_VLDF6            BSEC_OTPVLDRx_VLDF6_Msk                     /*!< Valid flag for shadow register (6+32*x) */
+#define BSEC_OTPVLDRx_VLDF7_Pos        (7U)
+#define BSEC_OTPVLDRx_VLDF7_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos)           /*!< 0x00000080 */
+#define BSEC_OTPVLDRx_VLDF7            BSEC_OTPVLDRx_VLDF7_Msk                     /*!< Valid flag for shadow register (7+32*x) */
+#define BSEC_OTPVLDRx_VLDF8_Pos        (8U)
+#define BSEC_OTPVLDRx_VLDF8_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos)           /*!< 0x00000100 */
+#define BSEC_OTPVLDRx_VLDF8            BSEC_OTPVLDRx_VLDF8_Msk                     /*!< Valid flag for shadow register (8+32*x) */
+#define BSEC_OTPVLDRx_VLDF9_Pos        (9U)
+#define BSEC_OTPVLDRx_VLDF9_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos)           /*!< 0x00000200 */
+#define BSEC_OTPVLDRx_VLDF9            BSEC_OTPVLDRx_VLDF9_Msk                     /*!< Valid flag for shadow register (9+32*x) */
+#define BSEC_OTPVLDRx_VLDF10_Pos       (10U)
+#define BSEC_OTPVLDRx_VLDF10_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos)          /*!< 0x00000400 */
+#define BSEC_OTPVLDRx_VLDF10           BSEC_OTPVLDRx_VLDF10_Msk                    /*!< Valid flag for shadow register (10+32*x) */
+#define BSEC_OTPVLDRx_VLDF11_Pos       (11U)
+#define BSEC_OTPVLDRx_VLDF11_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos)          /*!< 0x00000800 */
+#define BSEC_OTPVLDRx_VLDF11           BSEC_OTPVLDRx_VLDF11_Msk                    /*!< Valid flag for shadow register (11+32*x) */
+#define BSEC_OTPVLDRx_VLDF12_Pos       (12U)
+#define BSEC_OTPVLDRx_VLDF12_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos)          /*!< 0x00001000 */
+#define BSEC_OTPVLDRx_VLDF12           BSEC_OTPVLDRx_VLDF12_Msk                    /*!< Valid flag for shadow register (12+32*x) */
+#define BSEC_OTPVLDRx_VLDF13_Pos       (13U)
+#define BSEC_OTPVLDRx_VLDF13_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos)          /*!< 0x00002000 */
+#define BSEC_OTPVLDRx_VLDF13           BSEC_OTPVLDRx_VLDF13_Msk                    /*!< Valid flag for shadow register (13+32*x) */
+#define BSEC_OTPVLDRx_VLDF14_Pos       (14U)
+#define BSEC_OTPVLDRx_VLDF14_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos)          /*!< 0x00004000 */
+#define BSEC_OTPVLDRx_VLDF14           BSEC_OTPVLDRx_VLDF14_Msk                    /*!< Valid flag for shadow register (14+32*x) */
+#define BSEC_OTPVLDRx_VLDF15_Pos       (15U)
+#define BSEC_OTPVLDRx_VLDF15_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos)          /*!< 0x00008000 */
+#define BSEC_OTPVLDRx_VLDF15           BSEC_OTPVLDRx_VLDF15_Msk                    /*!< Valid flag for shadow register (15+32*x) */
+#define BSEC_OTPVLDRx_VLDF16_Pos       (16U)
+#define BSEC_OTPVLDRx_VLDF16_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos)          /*!< 0x00010000 */
+#define BSEC_OTPVLDRx_VLDF16           BSEC_OTPVLDRx_VLDF16_Msk                    /*!< Valid flag for shadow register (16+32*x) */
+#define BSEC_OTPVLDRx_VLDF17_Pos       (17U)
+#define BSEC_OTPVLDRx_VLDF17_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos)          /*!< 0x00020000 */
+#define BSEC_OTPVLDRx_VLDF17           BSEC_OTPVLDRx_VLDF17_Msk                    /*!< Valid flag for shadow register (17+32*x) */
+#define BSEC_OTPVLDRx_VLDF18_Pos       (18U)
+#define BSEC_OTPVLDRx_VLDF18_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos)          /*!< 0x00040000 */
+#define BSEC_OTPVLDRx_VLDF18           BSEC_OTPVLDRx_VLDF18_Msk                    /*!< Valid flag for shadow register (18+32*x) */
+#define BSEC_OTPVLDRx_VLDF19_Pos       (19U)
+#define BSEC_OTPVLDRx_VLDF19_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos)          /*!< 0x00080000 */
+#define BSEC_OTPVLDRx_VLDF19           BSEC_OTPVLDRx_VLDF19_Msk                    /*!< Valid flag for shadow register (19+32*x) */
+#define BSEC_OTPVLDRx_VLDF20_Pos       (20U)
+#define BSEC_OTPVLDRx_VLDF20_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos)          /*!< 0x00100000 */
+#define BSEC_OTPVLDRx_VLDF20           BSEC_OTPVLDRx_VLDF20_Msk                    /*!< Valid flag for shadow register (20+32*x) */
+#define BSEC_OTPVLDRx_VLDF21_Pos       (21U)
+#define BSEC_OTPVLDRx_VLDF21_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos)          /*!< 0x00200000 */
+#define BSEC_OTPVLDRx_VLDF21           BSEC_OTPVLDRx_VLDF21_Msk                    /*!< Valid flag for shadow register (21+32*x) */
+#define BSEC_OTPVLDRx_VLDF22_Pos       (22U)
+#define BSEC_OTPVLDRx_VLDF22_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos)          /*!< 0x00400000 */
+#define BSEC_OTPVLDRx_VLDF22           BSEC_OTPVLDRx_VLDF22_Msk                    /*!< Valid flag for shadow register (22+32*x) */
+#define BSEC_OTPVLDRx_VLDF23_Pos       (23U)
+#define BSEC_OTPVLDRx_VLDF23_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos)          /*!< 0x00800000 */
+#define BSEC_OTPVLDRx_VLDF23           BSEC_OTPVLDRx_VLDF23_Msk                    /*!< Valid flag for shadow register (23+32*x) */
+#define BSEC_OTPVLDRx_VLDF24_Pos       (24U)
+#define BSEC_OTPVLDRx_VLDF24_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos)          /*!< 0x01000000 */
+#define BSEC_OTPVLDRx_VLDF24           BSEC_OTPVLDRx_VLDF24_Msk                    /*!< Valid flag for shadow register (24+32*x) */
+#define BSEC_OTPVLDRx_VLDF25_Pos       (25U)
+#define BSEC_OTPVLDRx_VLDF25_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos)          /*!< 0x02000000 */
+#define BSEC_OTPVLDRx_VLDF25           BSEC_OTPVLDRx_VLDF25_Msk                    /*!< Valid flag for shadow register (25+32*x) */
+#define BSEC_OTPVLDRx_VLDF26_Pos       (26U)
+#define BSEC_OTPVLDRx_VLDF26_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos)          /*!< 0x04000000 */
+#define BSEC_OTPVLDRx_VLDF26           BSEC_OTPVLDRx_VLDF26_Msk                    /*!< Valid flag for shadow register (26+32*x) */
+#define BSEC_OTPVLDRx_VLDF27_Pos       (27U)
+#define BSEC_OTPVLDRx_VLDF27_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos)          /*!< 0x08000000 */
+#define BSEC_OTPVLDRx_VLDF27           BSEC_OTPVLDRx_VLDF27_Msk                    /*!< Valid flag for shadow register (27+32*x) */
+#define BSEC_OTPVLDRx_VLDF28_Pos       (28U)
+#define BSEC_OTPVLDRx_VLDF28_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos)          /*!< 0x10000000 */
+#define BSEC_OTPVLDRx_VLDF28           BSEC_OTPVLDRx_VLDF28_Msk                    /*!< Valid flag for shadow register (28+32*x) */
+#define BSEC_OTPVLDRx_VLDF29_Pos       (29U)
+#define BSEC_OTPVLDRx_VLDF29_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos)          /*!< 0x20000000 */
+#define BSEC_OTPVLDRx_VLDF29           BSEC_OTPVLDRx_VLDF29_Msk                    /*!< Valid flag for shadow register (29+32*x) */
+#define BSEC_OTPVLDRx_VLDF30_Pos       (30U)
+#define BSEC_OTPVLDRx_VLDF30_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos)          /*!< 0x40000000 */
+#define BSEC_OTPVLDRx_VLDF30           BSEC_OTPVLDRx_VLDF30_Msk                    /*!< Valid flag for shadow register (30+32*x) */
+#define BSEC_OTPVLDRx_VLDF31_Pos       (31U)
+#define BSEC_OTPVLDRx_VLDF31_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos)          /*!< 0x80000000 */
+#define BSEC_OTPVLDRx_VLDF31           BSEC_OTPVLDRx_VLDF31_Msk                    /*!< Valid flag for shadow register (31+32*x) */
+
+/******************  Bit definition for BSEC_SFSRx register  ******************/
+#define BSEC_SFSRx_SFW0_Pos            (0U)
+#define BSEC_SFSRx_SFW0_Msk            (0x1UL << BSEC_SFSRx_SFW0_Pos)               /*!< 0x00000001 */
+#define BSEC_SFSRx_SFW0                BSEC_SFSRx_SFW0_Msk                         /*!< Shadowed fuse word (32*x) */
+#define BSEC_SFSRx_SFW1_Pos            (1U)
+#define BSEC_SFSRx_SFW1_Msk            (0x1UL << BSEC_SFSRx_SFW1_Pos)               /*!< 0x00000002 */
+#define BSEC_SFSRx_SFW1                BSEC_SFSRx_SFW1_Msk                         /*!< Shadowed fuse word (1+32*x) */
+#define BSEC_SFSRx_SFW2_Pos            (2U)
+#define BSEC_SFSRx_SFW2_Msk            (0x1UL << BSEC_SFSRx_SFW2_Pos)               /*!< 0x00000004 */
+#define BSEC_SFSRx_SFW2                BSEC_SFSRx_SFW2_Msk                         /*!< Shadowed fuse word (2+32*x) */
+#define BSEC_SFSRx_SFW3_Pos            (3U)
+#define BSEC_SFSRx_SFW3_Msk            (0x1UL << BSEC_SFSRx_SFW3_Pos)               /*!< 0x00000008 */
+#define BSEC_SFSRx_SFW3                BSEC_SFSRx_SFW3_Msk                         /*!< Shadowed fuse word (3+32*x) */
+#define BSEC_SFSRx_SFW4_Pos            (4U)
+#define BSEC_SFSRx_SFW4_Msk            (0x1UL << BSEC_SFSRx_SFW4_Pos)               /*!< 0x00000010 */
+#define BSEC_SFSRx_SFW4                BSEC_SFSRx_SFW4_Msk                         /*!< Shadowed fuse word (4+32*x) */
+#define BSEC_SFSRx_SFW5_Pos            (5U)
+#define BSEC_SFSRx_SFW5_Msk            (0x1UL << BSEC_SFSRx_SFW5_Pos)               /*!< 0x00000020 */
+#define BSEC_SFSRx_SFW5                BSEC_SFSRx_SFW5_Msk                         /*!< Shadowed fuse word (5+32*x) */
+#define BSEC_SFSRx_SFW6_Pos            (6U)
+#define BSEC_SFSRx_SFW6_Msk            (0x1UL << BSEC_SFSRx_SFW6_Pos)               /*!< 0x00000040 */
+#define BSEC_SFSRx_SFW6                BSEC_SFSRx_SFW6_Msk                         /*!< Shadowed fuse word (6+32*x) */
+#define BSEC_SFSRx_SFW7_Pos            (7U)
+#define BSEC_SFSRx_SFW7_Msk            (0x1UL << BSEC_SFSRx_SFW7_Pos)               /*!< 0x00000080 */
+#define BSEC_SFSRx_SFW7                BSEC_SFSRx_SFW7_Msk                         /*!< Shadowed fuse word (7+32*x) */
+#define BSEC_SFSRx_SFW8_Pos            (8U)
+#define BSEC_SFSRx_SFW8_Msk            (0x1UL << BSEC_SFSRx_SFW8_Pos)               /*!< 0x00000100 */
+#define BSEC_SFSRx_SFW8                BSEC_SFSRx_SFW8_Msk                         /*!< Shadowed fuse word (8+32*x) */
+#define BSEC_SFSRx_SFW9_Pos            (9U)
+#define BSEC_SFSRx_SFW9_Msk            (0x1UL << BSEC_SFSRx_SFW9_Pos)               /*!< 0x00000200 */
+#define BSEC_SFSRx_SFW9                BSEC_SFSRx_SFW9_Msk                         /*!< Shadowed fuse word (9+32*x) */
+#define BSEC_SFSRx_SFW10_Pos           (10U)
+#define BSEC_SFSRx_SFW10_Msk           (0x1UL << BSEC_SFSRx_SFW10_Pos)              /*!< 0x00000400 */
+#define BSEC_SFSRx_SFW10               BSEC_SFSRx_SFW10_Msk                        /*!< Shadowed fuse word (10+32*x) */
+#define BSEC_SFSRx_SFW11_Pos           (11U)
+#define BSEC_SFSRx_SFW11_Msk           (0x1UL << BSEC_SFSRx_SFW11_Pos)              /*!< 0x00000800 */
+#define BSEC_SFSRx_SFW11               BSEC_SFSRx_SFW11_Msk                        /*!< Shadowed fuse word (11+32*x) */
+#define BSEC_SFSRx_SFW12_Pos           (12U)
+#define BSEC_SFSRx_SFW12_Msk           (0x1UL << BSEC_SFSRx_SFW12_Pos)              /*!< 0x00001000 */
+#define BSEC_SFSRx_SFW12               BSEC_SFSRx_SFW12_Msk                        /*!< Shadowed fuse word (12+32*x) */
+#define BSEC_SFSRx_SFW13_Pos           (13U)
+#define BSEC_SFSRx_SFW13_Msk           (0x1UL << BSEC_SFSRx_SFW13_Pos)              /*!< 0x00002000 */
+#define BSEC_SFSRx_SFW13               BSEC_SFSRx_SFW13_Msk                        /*!< Shadowed fuse word (13+32*x) */
+#define BSEC_SFSRx_SFW14_Pos           (14U)
+#define BSEC_SFSRx_SFW14_Msk           (0x1UL << BSEC_SFSRx_SFW14_Pos)              /*!< 0x00004000 */
+#define BSEC_SFSRx_SFW14               BSEC_SFSRx_SFW14_Msk                        /*!< Shadowed fuse word (14+32*x) */
+#define BSEC_SFSRx_SFW15_Pos           (15U)
+#define BSEC_SFSRx_SFW15_Msk           (0x1UL << BSEC_SFSRx_SFW15_Pos)              /*!< 0x00008000 */
+#define BSEC_SFSRx_SFW15               BSEC_SFSRx_SFW15_Msk                        /*!< Shadowed fuse word (15+32*x) */
+#define BSEC_SFSRx_SFW16_Pos           (16U)
+#define BSEC_SFSRx_SFW16_Msk           (0x1UL << BSEC_SFSRx_SFW16_Pos)              /*!< 0x00010000 */
+#define BSEC_SFSRx_SFW16               BSEC_SFSRx_SFW16_Msk                        /*!< Shadowed fuse word (16+32*x) */
+#define BSEC_SFSRx_SFW17_Pos           (17U)
+#define BSEC_SFSRx_SFW17_Msk           (0x1UL << BSEC_SFSRx_SFW17_Pos)              /*!< 0x00020000 */
+#define BSEC_SFSRx_SFW17               BSEC_SFSRx_SFW17_Msk                        /*!< Shadowed fuse word (17+32*x) */
+#define BSEC_SFSRx_SFW18_Pos           (18U)
+#define BSEC_SFSRx_SFW18_Msk           (0x1UL << BSEC_SFSRx_SFW18_Pos)              /*!< 0x00040000 */
+#define BSEC_SFSRx_SFW18               BSEC_SFSRx_SFW18_Msk                        /*!< Shadowed fuse word (18+32*x) */
+#define BSEC_SFSRx_SFW19_Pos           (19U)
+#define BSEC_SFSRx_SFW19_Msk           (0x1UL << BSEC_SFSRx_SFW19_Pos)              /*!< 0x00080000 */
+#define BSEC_SFSRx_SFW19               BSEC_SFSRx_SFW19_Msk                        /*!< Shadowed fuse word (19+32*x) */
+#define BSEC_SFSRx_SFW20_Pos           (20U)
+#define BSEC_SFSRx_SFW20_Msk           (0x1UL << BSEC_SFSRx_SFW20_Pos)              /*!< 0x00100000 */
+#define BSEC_SFSRx_SFW20               BSEC_SFSRx_SFW20_Msk                        /*!< Shadowed fuse word (20+32*x) */
+#define BSEC_SFSRx_SFW21_Pos           (21U)
+#define BSEC_SFSRx_SFW21_Msk           (0x1UL << BSEC_SFSRx_SFW21_Pos)              /*!< 0x00200000 */
+#define BSEC_SFSRx_SFW21               BSEC_SFSRx_SFW21_Msk                        /*!< Shadowed fuse word (21+32*x) */
+#define BSEC_SFSRx_SFW22_Pos           (22U)
+#define BSEC_SFSRx_SFW22_Msk           (0x1UL << BSEC_SFSRx_SFW22_Pos)              /*!< 0x00400000 */
+#define BSEC_SFSRx_SFW22               BSEC_SFSRx_SFW22_Msk                        /*!< Shadowed fuse word (22+32*x) */
+#define BSEC_SFSRx_SFW23_Pos           (23U)
+#define BSEC_SFSRx_SFW23_Msk           (0x1UL << BSEC_SFSRx_SFW23_Pos)              /*!< 0x00800000 */
+#define BSEC_SFSRx_SFW23               BSEC_SFSRx_SFW23_Msk                        /*!< Shadowed fuse word (23+32*x) */
+#define BSEC_SFSRx_SFW24_Pos           (24U)
+#define BSEC_SFSRx_SFW24_Msk           (0x1UL << BSEC_SFSRx_SFW24_Pos)              /*!< 0x01000000 */
+#define BSEC_SFSRx_SFW24               BSEC_SFSRx_SFW24_Msk                        /*!< Shadowed fuse word (24+32*x) */
+#define BSEC_SFSRx_SFW25_Pos           (25U)
+#define BSEC_SFSRx_SFW25_Msk           (0x1UL << BSEC_SFSRx_SFW25_Pos)              /*!< 0x02000000 */
+#define BSEC_SFSRx_SFW25               BSEC_SFSRx_SFW25_Msk                        /*!< Shadowed fuse word (25+32*x) */
+#define BSEC_SFSRx_SFW26_Pos           (26U)
+#define BSEC_SFSRx_SFW26_Msk           (0x1UL << BSEC_SFSRx_SFW26_Pos)              /*!< 0x04000000 */
+#define BSEC_SFSRx_SFW26               BSEC_SFSRx_SFW26_Msk                        /*!< Shadowed fuse word (26+32*x) */
+#define BSEC_SFSRx_SFW27_Pos           (27U)
+#define BSEC_SFSRx_SFW27_Msk           (0x1UL << BSEC_SFSRx_SFW27_Pos)              /*!< 0x08000000 */
+#define BSEC_SFSRx_SFW27               BSEC_SFSRx_SFW27_Msk                        /*!< Shadowed fuse word (27+32*x) */
+#define BSEC_SFSRx_SFW28_Pos           (28U)
+#define BSEC_SFSRx_SFW28_Msk           (0x1UL << BSEC_SFSRx_SFW28_Pos)              /*!< 0x10000000 */
+#define BSEC_SFSRx_SFW28               BSEC_SFSRx_SFW28_Msk                        /*!< Shadowed fuse word (28+32*x) */
+#define BSEC_SFSRx_SFW29_Pos           (29U)
+#define BSEC_SFSRx_SFW29_Msk           (0x1UL << BSEC_SFSRx_SFW29_Pos)              /*!< 0x20000000 */
+#define BSEC_SFSRx_SFW29               BSEC_SFSRx_SFW29_Msk                        /*!< Shadowed fuse word (29+32*x) */
+#define BSEC_SFSRx_SFW30_Pos           (30U)
+#define BSEC_SFSRx_SFW30_Msk           (0x1UL << BSEC_SFSRx_SFW30_Pos)              /*!< 0x40000000 */
+#define BSEC_SFSRx_SFW30               BSEC_SFSRx_SFW30_Msk                        /*!< Shadowed fuse word (30+32*x) */
+#define BSEC_SFSRx_SFW31_Pos           (31U)
+#define BSEC_SFSRx_SFW31_Msk           (0x1UL << BSEC_SFSRx_SFW31_Pos)              /*!< 0x80000000 */
+#define BSEC_SFSRx_SFW31               BSEC_SFSRx_SFW31_Msk                        /*!< Shadowed fuse word (31+32*x) */
+
+/******************  Bit definition for BSEC_OTPCR register  ******************/
+#define BSEC_OTPCR_ADDR_Pos            (0U)
+#define BSEC_OTPCR_ADDR_Msk            (0x1FFUL << BSEC_OTPCR_ADDR_Pos)             /*!< 0x000001FF */
+#define BSEC_OTPCR_ADDR                BSEC_OTPCR_ADDR_Msk                         /*!< Fuse word address */
+#define BSEC_OTPCR_PROG_Pos            (13U)
+#define BSEC_OTPCR_PROG_Msk            (0x1UL << BSEC_OTPCR_PROG_Pos)               /*!< 0x00002000 */
+#define BSEC_OTPCR_PROG                BSEC_OTPCR_PROG_Msk                         /*!< Fuse word programming */
+#define BSEC_OTPCR_PPLOCK_Pos          (14U)
+#define BSEC_OTPCR_PPLOCK_Msk          (0x1UL << BSEC_OTPCR_PPLOCK_Pos)             /*!< 0x00004000 */
+#define BSEC_OTPCR_PPLOCK              BSEC_OTPCR_PPLOCK_Msk                       /*!< Permanent programming lock */
+#define BSEC_OTPCR_LASTCID_Pos         (19U)
+#define BSEC_OTPCR_LASTCID_Msk         (0x7UL << BSEC_OTPCR_LASTCID_Pos)            /*!< 0x00380000 */
+#define BSEC_OTPCR_LASTCID             BSEC_OTPCR_LASTCID_Msk                      /*!< Last CID */
+
+/*******************  Bit definition for BSEC_WDR register  *******************/
+#define BSEC_WDR_WRDATA_Pos            (0U)
+#define BSEC_WDR_WRDATA_Msk            (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos)        /*!< 0xFFFFFFFF */
+#define BSEC_WDR_WRDATA                BSEC_WDR_WRDATA_Msk                         /*!< OTP write data */
+
+/****************  Bit definition for BSEC_SCRATCHRx register  ****************/
+#define BSEC_SCRATCHRx_SDATA_Pos       (0U)
+#define BSEC_SCRATCHRx_SDATA_Msk       (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_SCRATCHRx_SDATA           BSEC_SCRATCHRx_SDATA_Msk                    /*!< Scratch data */
+
+/******************  Bit definition for BSEC_LOCKR register  ******************/
+#define BSEC_LOCKR_GWLOCK_Pos          (0U)
+#define BSEC_LOCKR_GWLOCK_Msk          (0x1UL << BSEC_LOCKR_GWLOCK_Pos)             /*!< 0x00000001 */
+#define BSEC_LOCKR_GWLOCK              BSEC_LOCKR_GWLOCK_Msk                       /*!< Global write lock */
+#define BSEC_LOCKR_HKLOCK_Pos          (2U)
+#define BSEC_LOCKR_HKLOCK_Msk          (0x1UL << BSEC_LOCKR_HKLOCK_Pos)             /*!< 0x00000004 */
+#define BSEC_LOCKR_HKLOCK              BSEC_LOCKR_HKLOCK_Msk                       /*!< Hardware key lock */
+
+/*****************  Bit definition for BSEC_JTAGINR register  *****************/
+#define BSEC_JTAGINR_JDATAIN_Pos       (0U)
+#define BSEC_JTAGINR_JDATAIN_Msk       (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_JTAGINR_JDATAIN           BSEC_JTAGINR_JDATAIN_Msk                    /*!< JTAG input data */
+
+/****************  Bit definition for BSEC_JTAGOUTR register  *****************/
+#define BSEC_JTAGOUTR_JDATAOUT_Pos     (0U)
+#define BSEC_JTAGOUTR_JDATAOUT_Msk     (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define BSEC_JTAGOUTR_JDATAOUT         BSEC_JTAGOUTR_JDATAOUT_Msk                  /*!< JTAG output data */
+
+/*****************  Bit definition for BSEC_UNMAPR register  ******************/
+#define BSEC_UNMAPR_UNMAP_Pos          (0U)
+#define BSEC_UNMAPR_UNMAP_Msk          (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos)      /*!< 0xFFFFFFFF */
+#define BSEC_UNMAPR_UNMAP              BSEC_UNMAPR_UNMAP_Msk                       /*!< Unmap key */
+
+/*******************  Bit definition for BSEC_SR register  ********************/
+#define BSEC_SR_HVALID_Pos             (1U)
+#define BSEC_SR_HVALID_Msk             (0x1UL << BSEC_SR_HVALID_Pos)                /*!< 0x00000002 */
+#define BSEC_SR_HVALID                 BSEC_SR_HVALID_Msk                          /*!< Hardware key valid */
+#define BSEC_SR_DBGREQ_Pos             (16U)
+#define BSEC_SR_DBGREQ_Msk             (0x1UL << BSEC_SR_DBGREQ_Pos)                /*!< 0x00010000 */
+#define BSEC_SR_DBGREQ                 BSEC_SR_DBGREQ_Msk                          /*!< Debug request */
+#define BSEC_SR_NVSTATE_Pos            (26U)
+#define BSEC_SR_NVSTATE_Msk            (0x3FUL << BSEC_SR_NVSTATE_Pos)              /*!< 0xFC000000 */
+#define BSEC_SR_NVSTATE                BSEC_SR_NVSTATE_Msk                         /*!< Non-volatile state */
+
+/******************  Bit definition for BSEC_OTPSR register  ******************/
+#define BSEC_OTPSR_BUSY_Pos            (0U)
+#define BSEC_OTPSR_BUSY_Msk            (0x1UL << BSEC_OTPSR_BUSY_Pos)               /*!< 0x00000001 */
+#define BSEC_OTPSR_BUSY                BSEC_OTPSR_BUSY_Msk                         /*!< Busy flag */
+#define BSEC_OTPSR_INIT_DONE_Pos       (1U)
+#define BSEC_OTPSR_INIT_DONE_Msk       (0x1UL << BSEC_OTPSR_INIT_DONE_Pos)          /*!< 0x00000002 */
+#define BSEC_OTPSR_INIT_DONE           BSEC_OTPSR_INIT_DONE_Msk                    /*!< Initialization done */
+#define BSEC_OTPSR_HIDEUP_Pos          (2U)
+#define BSEC_OTPSR_HIDEUP_Msk          (0x1UL << BSEC_OTPSR_HIDEUP_Pos)             /*!< 0x00000004 */
+#define BSEC_OTPSR_HIDEUP              BSEC_OTPSR_HIDEUP_Msk                       /*!< Hide upper fuse words */
+#define BSEC_OTPSR_OTPNVIR_Pos         (4U)
+#define BSEC_OTPSR_OTPNVIR_Msk         (0x1UL << BSEC_OTPSR_OTPNVIR_Pos)            /*!< 0x00000010 */
+#define BSEC_OTPSR_OTPNVIR             BSEC_OTPSR_OTPNVIR_Msk                      /*!< OTP not virgin */
+#define BSEC_OTPSR_OTPERR_Pos          (5U)
+#define BSEC_OTPSR_OTPERR_Msk          (0x1UL << BSEC_OTPSR_OTPERR_Pos)             /*!< 0x00000020 */
+#define BSEC_OTPSR_OTPERR              BSEC_OTPSR_OTPERR_Msk                       /*!< OTP with error */
+#define BSEC_OTPSR_OTPSEC_Pos          (6U)
+#define BSEC_OTPSR_OTPSEC_Msk          (0x1UL << BSEC_OTPSR_OTPSEC_Pos)             /*!< 0x00000040 */
+#define BSEC_OTPSR_OTPSEC              BSEC_OTPSR_OTPSEC_Msk                       /*!< OTP with single error correction */
+#define BSEC_OTPSR_PROGFAIL_Pos        (16U)
+#define BSEC_OTPSR_PROGFAIL_Msk        (0x1UL << BSEC_OTPSR_PROGFAIL_Pos)           /*!< 0x00010000 */
+#define BSEC_OTPSR_PROGFAIL            BSEC_OTPSR_PROGFAIL_Msk                     /*!< Programming failed */
+#define BSEC_OTPSR_DISTURBF_Pos        (17U)
+#define BSEC_OTPSR_DISTURBF_Msk        (0x1UL << BSEC_OTPSR_DISTURBF_Pos)           /*!< 0x00020000 */
+#define BSEC_OTPSR_DISTURBF            BSEC_OTPSR_DISTURBF_Msk                     /*!< Disturb flag */
+#define BSEC_OTPSR_DEDF_Pos            (18U)
+#define BSEC_OTPSR_DEDF_Msk            (0x1UL << BSEC_OTPSR_DEDF_Pos)               /*!< 0x00040000 */
+#define BSEC_OTPSR_DEDF                BSEC_OTPSR_DEDF_Msk                         /*!< Double error detection flag */
+#define BSEC_OTPSR_SECF_Pos            (19U)
+#define BSEC_OTPSR_SECF_Msk            (0x1UL << BSEC_OTPSR_SECF_Pos)               /*!< 0x00080000 */
+#define BSEC_OTPSR_SECF                BSEC_OTPSR_SECF_Msk                         /*!< Single error correction flag */
+#define BSEC_OTPSR_PPLF_Pos            (20U)
+#define BSEC_OTPSR_PPLF_Msk            (0x1UL << BSEC_OTPSR_PPLF_Pos)               /*!< 0x00100000 */
+#define BSEC_OTPSR_PPLF                BSEC_OTPSR_PPLF_Msk                         /*!< Permanent programming lock flag */
+#define BSEC_OTPSR_PPLMF_Pos           (21U)
+#define BSEC_OTPSR_PPLMF_Msk           (0x1UL << BSEC_OTPSR_PPLMF_Pos)              /*!< 0x00200000 */
+#define BSEC_OTPSR_PPLMF               BSEC_OTPSR_PPLMF_Msk                        /*!< Permanent programming lock mismatch flag */
+#define BSEC_OTPSR_AMEF_Pos            (22U)
+#define BSEC_OTPSR_AMEF_Msk            (0x1UL << BSEC_OTPSR_AMEF_Pos)               /*!< 0x00400000 */
+#define BSEC_OTPSR_AMEF                BSEC_OTPSR_AMEF_Msk                         /*!< Addresses mismatch error flag */
+
+/*****************  Bit definition for BSEC_EPOCHRx register  *****************/
+#define BSEC_EPOCHRx_EPOCH_Pos         (0U)
+#define BSEC_EPOCHRx_EPOCH_Msk         (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos)     /*!< 0xFFFFFFFF */
+#define BSEC_EPOCHRx_EPOCH             BSEC_EPOCHRx_EPOCH_Msk                      /*!< Epoch */
+
+/****************  Bit definition for BSEC_EPOCHSELR register  ****************/
+#define BSEC_EPOCHSELR_EPSEL_Pos       (0U)
+#define BSEC_EPOCHSELR_EPSEL_Msk       (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos)          /*!< 0x00000001 */
+#define BSEC_EPOCHSELR_EPSEL           BSEC_EPOCHSELR_EPSEL_Msk                    /*!< Epoch selection */
+
+/******************  Bit definition for BSEC_DBGCR register  ******************/
+#define BSEC_DBGCR_UNLOCK_Pos          (8U)
+#define BSEC_DBGCR_UNLOCK_Msk          (0xFFUL << BSEC_DBGCR_UNLOCK_Pos)            /*!< 0x0000FF00 */
+#define BSEC_DBGCR_UNLOCK              BSEC_DBGCR_UNLOCK_Msk                       /*!< Non-secure debug authorization */
+#define BSEC_DBGCR_AUTH_HDPL_Pos       (16U)
+#define BSEC_DBGCR_AUTH_HDPL_Msk       (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos)         /*!< 0x00FF0000 */
+#define BSEC_DBGCR_AUTH_HDPL           BSEC_DBGCR_AUTH_HDPL_Msk                    /*!< Level at which debug may be opened */
+#define BSEC_DBGCR_AUTH_SEC_Pos        (24U)
+#define BSEC_DBGCR_AUTH_SEC_Msk        (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos)          /*!< 0xFF000000 */
+#define BSEC_DBGCR_AUTH_SEC            BSEC_DBGCR_AUTH_SEC_Msk                     /*!< Secure debug authorization */
+
+/***************  Bit definition for BSEC_AP_UNLOCK register  *****************/
+#define BSEC_AP_UNLOCK_UNLOCK_Pos      (0U)
+#define BSEC_AP_UNLOCK_UNLOCK_Msk      (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos)        /*!< 0x000000FF */
+#define BSEC_AP_UNLOCK_UNLOCK          BSEC_AP_UNLOCK_UNLOCK_Msk                   /*!< Unlock DBG_MCU AP interface */
+
+/*****************  Bit definition for BSEC_HDPLSR register  ******************/
+#define BSEC_HDPLSR_HDPL_Pos           (0U)
+#define BSEC_HDPLSR_HDPL_Msk           (0xFFUL << BSEC_HDPLSR_HDPL_Pos)             /*!< 0x000000FF */
+#define BSEC_HDPLSR_HDPL               BSEC_HDPLSR_HDPL_Msk                        /*!< Current HDPL */
+
+/*****************  Bit definition for BSEC_HDPLCR register  ******************/
+#define BSEC_HDPLCR_INCR_HDPL_Pos      (0U)
+#define BSEC_HDPLCR_INCR_HDPL_Msk      (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos)  /*!< 0xFFFFFFFF */
+#define BSEC_HDPLCR_INCR_HDPL          BSEC_HDPLCR_INCR_HDPL_Msk                   /*!< Increment HDPL */
+
+/*****************  Bit definition for BSEC_NEXTLR register  ******************/
+#define BSEC_NEXTLR_INCR_Pos           (0U)
+#define BSEC_NEXTLR_INCR_Msk           (0x3UL << BSEC_NEXTLR_INCR_Pos)              /*!< 0x00000003 */
+#define BSEC_NEXTLR_INCR               BSEC_NEXTLR_INCR_Msk                        /*!< Increment */
+
+/*****************  Bit definition for BSEC_WOSCRx register  ******************/
+#define BSEC_WOSCRx_WOSDATA_Pos        (0U)
+#define BSEC_WOSCRx_WOSDATA_Msk        (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos)    /*!< 0xFFFFFFFF */
+#define BSEC_WOSCRx_WOSDATA            BSEC_WOSCRx_WOSDATA_Msk                     /*!< Write once scratch data */
+
+/******************  Bit definition for BSEC_HRCR register  *******************/
+#define BSEC_HRCR_HRC_Pos              (0U)
+#define BSEC_HRCR_HRC_Msk              (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_HRCR_HRC                  BSEC_HRCR_HRC_Msk                           /*!< Hot reset counter */
+
+/******************  Bit definition for BSEC_WRCR register  *******************/
+#define BSEC_WRCR_WRC_Pos              (0U)
+#define BSEC_WRCR_WRC_Msk              (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_WRCR_WRC                  BSEC_WRCR_WRC_Msk                           /*!< Warm reset counter */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos              (0U)
+#define CRC_DR_DR_Msk              (0xFFFFFFFFUL << CRC_DR_DR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                  CRC_DR_DR_Msk                               /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos            (0U)
+#define CRC_IDR_IDR_Msk            (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR                CRC_IDR_IDR_Msk                             /*!< General-purpose 32-bits data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos           (0U)
+#define CRC_CR_RESET_Msk           (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
+#define CRC_CR_RESET               CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos        (3U)
+#define CRC_CR_POLYSIZE_Msk        (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE            CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0          (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1          (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos          (5U)
+#define CRC_CR_REV_IN_Msk          (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
+#define CRC_CR_REV_IN              CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0            (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1            (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos         (7U)
+#define CRC_CR_REV_OUT_Msk         (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
+#define CRC_CR_REV_OUT             CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
+#define CRC_CR_REV_OUT_0           (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
+#define CRC_CR_REV_OUT_1           (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
+#define CRC_CR_RTYPE_IN_Pos        (9U)
+#define CRC_CR_RTYPE_IN_Msk        (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
+#define CRC_CR_RTYPE_IN            CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
+#define CRC_CR_RTYPE_OUT_Pos       (10U)
+#define CRC_CR_RTYPE_OUT_Msk       (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
+#define CRC_CR_RTYPE_OUT           CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos          (0U)
+#define CRC_INIT_INIT_Msk          (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)         /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT              CRC_INIT_INIT_Msk                           /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos            (0U)
+#define CRC_POL_POL_Msk            (0xFFFFFFFFUL << CRC_POL_POL_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_POL_POL                CRC_POL_POL_Msk                             /*!< Coefficients of the polynomial */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (CSI)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CSI_CR register  ********************/
+#define CSI_CR_CSIEN_Pos                (0U)
+#define CSI_CR_CSIEN_Msk                (0x1UL << CSI_CR_CSIEN_Pos)               /*!< 0x00000001 */
+#define CSI_CR_CSIEN                    CSI_CR_CSIEN_Msk                         /*!< CSI-2 enable */
+#define CSI_CR_VC0START_Pos             (2U)
+#define CSI_CR_VC0START_Msk             (0x1UL << CSI_CR_VC0START_Pos)            /*!< 0x00000004 */
+#define CSI_CR_VC0START                 CSI_CR_VC0START_Msk                      /*!< Virtual channel 0 start */
+#define CSI_CR_VC0STOP_Pos              (3U)
+#define CSI_CR_VC0STOP_Msk              (0x1UL << CSI_CR_VC0STOP_Pos)             /*!< 0x00000008 */
+#define CSI_CR_VC0STOP                  CSI_CR_VC0STOP_Msk                       /*!< Virtual channel 0 stop */
+#define CSI_CR_VC1START_Pos             (6U)
+#define CSI_CR_VC1START_Msk             (0x1UL << CSI_CR_VC1START_Pos)            /*!< 0x00000040 */
+#define CSI_CR_VC1START                 CSI_CR_VC1START_Msk                      /*!< Virtual channel 1 start */
+#define CSI_CR_VC1STOP_Pos              (7U)
+#define CSI_CR_VC1STOP_Msk              (0x1UL << CSI_CR_VC1STOP_Pos)             /*!< 0x00000080 */
+#define CSI_CR_VC1STOP                  CSI_CR_VC1STOP_Msk                       /*!< Virtual channel 1 stop */
+#define CSI_CR_VC2START_Pos             (10U)
+#define CSI_CR_VC2START_Msk             (0x1UL << CSI_CR_VC2START_Pos)            /*!< 0x00000400 */
+#define CSI_CR_VC2START                 CSI_CR_VC2START_Msk                      /*!< Virtual channel 2 start */
+#define CSI_CR_VC2STOP_Pos              (11U)
+#define CSI_CR_VC2STOP_Msk              (0x1UL << CSI_CR_VC2STOP_Pos)             /*!< 0x00000800 */
+#define CSI_CR_VC2STOP                  CSI_CR_VC2STOP_Msk                       /*!< Virtual channel 2 stop */
+#define CSI_CR_VC3START_Pos             (14U)
+#define CSI_CR_VC3START_Msk             (0x1UL << CSI_CR_VC3START_Pos)            /*!< 0x00004000 */
+#define CSI_CR_VC3START                 CSI_CR_VC3START_Msk                      /*!< Virtual channel 3 start */
+#define CSI_CR_VC3STOP_Pos              (15U)
+#define CSI_CR_VC3STOP_Msk              (0x1UL << CSI_CR_VC3STOP_Pos)             /*!< 0x00008000 */
+#define CSI_CR_VC3STOP                  CSI_CR_VC3STOP_Msk                       /*!< Virtual channel 3 stop */
+
+/*******************  Bit definition for CSI_PCR register  ********************/
+#define CSI_PCR_PWRDOWN_Pos             (0U)
+#define CSI_PCR_PWRDOWN_Msk             (0x1UL << CSI_PCR_PWRDOWN_Pos)            /*!< 0x00000001 */
+#define CSI_PCR_PWRDOWN                 CSI_PCR_PWRDOWN_Msk                      /*!< Virtual channel 3 start */
+#define CSI_PCR_CLEN_Pos                (1U)
+#define CSI_PCR_CLEN_Msk                (0x1UL << CSI_PCR_CLEN_Pos)               /*!< 0x00000002 */
+#define CSI_PCR_CLEN                    CSI_PCR_CLEN_Msk                         /*!< Clock lane enable */
+#define CSI_PCR_DL0EN_Pos               (2U)
+#define CSI_PCR_DL0EN_Msk               (0x1UL << CSI_PCR_DL0EN_Pos)              /*!< 0x00000004 */
+#define CSI_PCR_DL0EN                   CSI_PCR_DL0EN_Msk                        /*!< D-PHY_RX data lane 0 enable */
+#define CSI_PCR_DL1EN_Pos               (3U)
+#define CSI_PCR_DL1EN_Msk               (0x1UL << CSI_PCR_DL1EN_Pos)              /*!< 0x00000008 */
+#define CSI_PCR_DL1EN                   CSI_PCR_DL1EN_Msk                        /*!< D-PHY_RX data lane 1 enable */
+
+/*****************  Bit definition for CSI_VC0CFGR1 register  *****************/
+#define CSI_VC0CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC0CFGR1_ALLDT_Msk          (0x1UL << CSI_VC0CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC0CFGR1_ALLDT              CSI_VC0CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC0CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC0CFGR1_DT0EN_Msk          (0x1UL << CSI_VC0CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC0CFGR1_DT0EN              CSI_VC0CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC0CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC0CFGR1_DT1EN_Msk          (0x1UL << CSI_VC0CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC0CFGR1_DT1EN              CSI_VC0CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC0CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC0CFGR1_DT2EN_Msk          (0x1UL << CSI_VC0CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC0CFGR1_DT2EN              CSI_VC0CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC0CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC0CFGR1_DT3EN_Msk          (0x1UL << CSI_VC0CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC0CFGR1_DT3EN              CSI_VC0CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC0CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC0CFGR1_DT4EN_Msk          (0x1UL << CSI_VC0CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC0CFGR1_DT4EN              CSI_VC0CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC0CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC0CFGR1_DT5EN_Msk          (0x1UL << CSI_VC0CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC0CFGR1_DT5EN              CSI_VC0CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC0CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC0CFGR1_DT6EN_Msk          (0x1UL << CSI_VC0CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC0CFGR1_DT6EN              CSI_VC0CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC0CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC0CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR1_CDTFT              CSI_VC0CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC0CFGR1_DT0_Pos            (16U)
+#define CSI_VC0CFGR1_DT0_Msk            (0x3FUL << CSI_VC0CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR1_DT0                CSI_VC0CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC0CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC0CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR1_DT0FT              CSI_VC0CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC0CFGR2 register  *****************/
+#define CSI_VC0CFGR2_DT1_Pos            (0U)
+#define CSI_VC0CFGR2_DT1_Msk            (0x3FUL << CSI_VC0CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR2_DT1                CSI_VC0CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC0CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR2_DT1FT              CSI_VC0CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC0CFGR2_DT2_Pos            (16U)
+#define CSI_VC0CFGR2_DT2_Msk            (0x3FUL << CSI_VC0CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR2_DT2                CSI_VC0CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC0CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR2_DT2FT              CSI_VC0CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC0CFGR3 register  *****************/
+#define CSI_VC0CFGR3_DT3_Pos            (0U)
+#define CSI_VC0CFGR3_DT3_Msk            (0x3FUL << CSI_VC0CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR3_DT3                CSI_VC0CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC0CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR3_DT3FT              CSI_VC0CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC0CFGR3_DT4_Pos            (16U)
+#define CSI_VC0CFGR3_DT4_Msk            (0x3FUL << CSI_VC0CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR3_DT4                CSI_VC0CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC0CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR3_DT4FT              CSI_VC0CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC0CFGR4 register  *****************/
+#define CSI_VC0CFGR4_DT5_Pos            (0U)
+#define CSI_VC0CFGR4_DT5_Msk            (0x3FUL << CSI_VC0CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR4_DT5                CSI_VC0CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC0CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR4_DT5FT              CSI_VC0CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC0CFGR4_DT6_Pos            (16U)
+#define CSI_VC0CFGR4_DT6_Msk            (0x3FUL << CSI_VC0CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR4_DT6                CSI_VC0CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC0CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR4_DT6FT              CSI_VC0CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC1CFGR1 register  *****************/
+#define CSI_VC1CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC1CFGR1_ALLDT_Msk          (0x1UL << CSI_VC1CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC1CFGR1_ALLDT              CSI_VC1CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC1CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC1CFGR1_DT0EN_Msk          (0x1UL << CSI_VC1CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC1CFGR1_DT0EN              CSI_VC1CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC1CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC1CFGR1_DT1EN_Msk          (0x1UL << CSI_VC1CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC1CFGR1_DT1EN              CSI_VC1CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC1CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC1CFGR1_DT2EN_Msk          (0x1UL << CSI_VC1CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC1CFGR1_DT2EN              CSI_VC1CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC1CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC1CFGR1_DT3EN_Msk          (0x1UL << CSI_VC1CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC1CFGR1_DT3EN              CSI_VC1CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC1CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC1CFGR1_DT4EN_Msk          (0x1UL << CSI_VC1CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC1CFGR1_DT4EN              CSI_VC1CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC1CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC1CFGR1_DT5EN_Msk          (0x1UL << CSI_VC1CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC1CFGR1_DT5EN              CSI_VC1CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC1CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC1CFGR1_DT6EN_Msk          (0x1UL << CSI_VC1CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC1CFGR1_DT6EN              CSI_VC1CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC1CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC1CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR1_CDTFT              CSI_VC1CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC1CFGR1_DT0_Pos            (16U)
+#define CSI_VC1CFGR1_DT0_Msk            (0x3FUL << CSI_VC1CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR1_DT0                CSI_VC1CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC1CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC1CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR1_DT0FT              CSI_VC1CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC1CFGR2 register  *****************/
+#define CSI_VC1CFGR2_DT1_Pos            (0U)
+#define CSI_VC1CFGR2_DT1_Msk            (0x3FUL << CSI_VC1CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR2_DT1                CSI_VC1CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC1CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR2_DT1FT              CSI_VC1CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC1CFGR2_DT2_Pos            (16U)
+#define CSI_VC1CFGR2_DT2_Msk            (0x3FUL << CSI_VC1CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR2_DT2                CSI_VC1CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC1CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR2_DT2FT              CSI_VC1CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC1CFGR3 register  *****************/
+#define CSI_VC1CFGR3_DT3_Pos            (0U)
+#define CSI_VC1CFGR3_DT3_Msk            (0x3FUL << CSI_VC1CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR3_DT3                CSI_VC1CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC1CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR3_DT3FT              CSI_VC1CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC1CFGR3_DT4_Pos            (16U)
+#define CSI_VC1CFGR3_DT4_Msk            (0x3FUL << CSI_VC1CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR3_DT4                CSI_VC1CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC1CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR3_DT4FT              CSI_VC1CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC1CFGR4 register  *****************/
+#define CSI_VC1CFGR4_DT5_Pos            (0U)
+#define CSI_VC1CFGR4_DT5_Msk            (0x3FUL << CSI_VC1CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR4_DT5                CSI_VC1CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC1CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR4_DT5FT              CSI_VC1CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC1CFGR4_DT6_Pos            (16U)
+#define CSI_VC1CFGR4_DT6_Msk            (0x3FUL << CSI_VC1CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR4_DT6                CSI_VC1CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC1CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR4_DT6FT              CSI_VC1CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC2CFGR1 register  *****************/
+#define CSI_VC2CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC2CFGR1_ALLDT_Msk          (0x1UL << CSI_VC2CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC2CFGR1_ALLDT              CSI_VC2CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC2CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC2CFGR1_DT0EN_Msk          (0x1UL << CSI_VC2CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC2CFGR1_DT0EN              CSI_VC2CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC2CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC2CFGR1_DT1EN_Msk          (0x1UL << CSI_VC2CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC2CFGR1_DT1EN              CSI_VC2CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC2CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC2CFGR1_DT2EN_Msk          (0x1UL << CSI_VC2CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC2CFGR1_DT2EN              CSI_VC2CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC2CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC2CFGR1_DT3EN_Msk          (0x1UL << CSI_VC2CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC2CFGR1_DT3EN              CSI_VC2CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC2CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC2CFGR1_DT4EN_Msk          (0x1UL << CSI_VC2CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC2CFGR1_DT4EN              CSI_VC2CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC2CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC2CFGR1_DT5EN_Msk          (0x1UL << CSI_VC2CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC2CFGR1_DT5EN              CSI_VC2CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC2CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC2CFGR1_DT6EN_Msk          (0x1UL << CSI_VC2CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC2CFGR1_DT6EN              CSI_VC2CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC2CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC2CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR1_CDTFT              CSI_VC2CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC2CFGR1_DT0_Pos            (16U)
+#define CSI_VC2CFGR1_DT0_Msk            (0x3FUL << CSI_VC2CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR1_DT0                CSI_VC2CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC2CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC2CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR1_DT0FT              CSI_VC2CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC2CFGR2 register  *****************/
+#define CSI_VC2CFGR2_DT1_Pos            (0U)
+#define CSI_VC2CFGR2_DT1_Msk            (0x3FUL << CSI_VC2CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR2_DT1                CSI_VC2CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC2CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR2_DT1FT              CSI_VC2CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC2CFGR2_DT2_Pos            (16U)
+#define CSI_VC2CFGR2_DT2_Msk            (0x3FUL << CSI_VC2CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR2_DT2                CSI_VC2CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC2CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR2_DT2FT              CSI_VC2CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC2CFGR3 register  *****************/
+#define CSI_VC2CFGR3_DT3_Pos            (0U)
+#define CSI_VC2CFGR3_DT3_Msk            (0x3FUL << CSI_VC2CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR3_DT3                CSI_VC2CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC2CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR3_DT3FT              CSI_VC2CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC2CFGR3_DT4_Pos            (16U)
+#define CSI_VC2CFGR3_DT4_Msk            (0x3FUL << CSI_VC2CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR3_DT4                CSI_VC2CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC2CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR3_DT4FT              CSI_VC2CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC2CFGR4 register  *****************/
+#define CSI_VC2CFGR4_DT5_Pos            (0U)
+#define CSI_VC2CFGR4_DT5_Msk            (0x3FUL << CSI_VC2CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR4_DT5                CSI_VC2CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC2CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR4_DT5FT              CSI_VC2CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC2CFGR4_DT6_Pos            (16U)
+#define CSI_VC2CFGR4_DT6_Msk            (0x3FUL << CSI_VC2CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR4_DT6                CSI_VC2CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC2CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR4_DT6FT              CSI_VC2CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC3CFGR1 register  *****************/
+#define CSI_VC3CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC3CFGR1_ALLDT_Msk          (0x1UL << CSI_VC3CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC3CFGR1_ALLDT              CSI_VC3CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC3CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC3CFGR1_DT0EN_Msk          (0x1UL << CSI_VC3CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC3CFGR1_DT0EN              CSI_VC3CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC3CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC3CFGR1_DT1EN_Msk          (0x1UL << CSI_VC3CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC3CFGR1_DT1EN              CSI_VC3CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC3CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC3CFGR1_DT2EN_Msk          (0x1UL << CSI_VC3CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC3CFGR1_DT2EN              CSI_VC3CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC3CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC3CFGR1_DT3EN_Msk          (0x1UL << CSI_VC3CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC3CFGR1_DT3EN              CSI_VC3CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC3CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC3CFGR1_DT4EN_Msk          (0x1UL << CSI_VC3CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC3CFGR1_DT4EN              CSI_VC3CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC3CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC3CFGR1_DT5EN_Msk          (0x1UL << CSI_VC3CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC3CFGR1_DT5EN              CSI_VC3CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC3CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC3CFGR1_DT6EN_Msk          (0x1UL << CSI_VC3CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC3CFGR1_DT6EN              CSI_VC3CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC3CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC3CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR1_CDTFT              CSI_VC3CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC3CFGR1_DT0_Pos            (16U)
+#define CSI_VC3CFGR1_DT0_Msk            (0x3FUL << CSI_VC3CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR1_DT0                CSI_VC3CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC3CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC3CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR1_DT0FT              CSI_VC3CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC3CFGR2 register  *****************/
+#define CSI_VC3CFGR2_DT1_Pos            (0U)
+#define CSI_VC3CFGR2_DT1_Msk            (0x3FUL << CSI_VC3CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR2_DT1                CSI_VC3CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC3CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR2_DT1FT              CSI_VC3CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC3CFGR2_DT2_Pos            (16U)
+#define CSI_VC3CFGR2_DT2_Msk            (0x3FUL << CSI_VC3CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR2_DT2                CSI_VC3CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC3CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR2_DT2FT              CSI_VC3CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC3CFGR3 register  *****************/
+#define CSI_VC3CFGR3_DT3_Pos            (0U)
+#define CSI_VC3CFGR3_DT3_Msk            (0x3FUL << CSI_VC3CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR3_DT3                CSI_VC3CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC3CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR3_DT3FT              CSI_VC3CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC3CFGR3_DT4_Pos            (16U)
+#define CSI_VC3CFGR3_DT4_Msk            (0x3FUL << CSI_VC3CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR3_DT4                CSI_VC3CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC3CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR3_DT4FT              CSI_VC3CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC3CFGR4 register  *****************/
+#define CSI_VC3CFGR4_DT5_Pos            (0U)
+#define CSI_VC3CFGR4_DT5_Msk            (0x3FUL << CSI_VC3CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR4_DT5                CSI_VC3CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC3CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR4_DT5FT              CSI_VC3CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC3CFGR4_DT6_Pos            (16U)
+#define CSI_VC3CFGR4_DT6_Msk            (0x3FUL << CSI_VC3CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR4_DT6                CSI_VC3CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC3CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR4_DT6FT              CSI_VC3CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_LB0CFGR register  ******************/
+#define CSI_LB0CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB0CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB0CFGR_BYTECNT             CSI_LB0CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB0CFGR_LINECNT_Pos         (16U)
+#define CSI_LB0CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB0CFGR_LINECNT             CSI_LB0CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB1CFGR register  ******************/
+#define CSI_LB1CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB1CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB1CFGR_BYTECNT             CSI_LB1CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB1CFGR_LINECNT_Pos         (16U)
+#define CSI_LB1CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB1CFGR_LINECNT             CSI_LB1CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB2CFGR register  ******************/
+#define CSI_LB2CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB2CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB2CFGR_BYTECNT             CSI_LB2CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB2CFGR_LINECNT_Pos         (16U)
+#define CSI_LB2CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB2CFGR_LINECNT             CSI_LB2CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB3CFGR register  ******************/
+#define CSI_LB3CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB3CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB3CFGR_BYTECNT             CSI_LB3CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB3CFGR_LINECNT_Pos         (16U)
+#define CSI_LB3CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB3CFGR_LINECNT             CSI_LB3CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_TIM0CFGR register  *****************/
+#define CSI_TIM0CFGR_COUNT_Pos          (0U)
+#define CSI_TIM0CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM0CFGR_COUNT              CSI_TIM0CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM1CFGR register  *****************/
+#define CSI_TIM1CFGR_COUNT_Pos          (0U)
+#define CSI_TIM1CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM1CFGR_COUNT              CSI_TIM1CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM2CFGR register  *****************/
+#define CSI_TIM2CFGR_COUNT_Pos          (0U)
+#define CSI_TIM2CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM2CFGR_COUNT              CSI_TIM2CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM3CFGR register  *****************/
+#define CSI_TIM3CFGR_COUNT_Pos          (0U)
+#define CSI_TIM3CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM3CFGR_COUNT              CSI_TIM3CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/******************  Bit definition for CSI_LMCFGR register  ******************/
+#define CSI_LMCFGR_LANENB_Pos           (8U)
+#define CSI_LMCFGR_LANENB_Msk           (0x7UL << CSI_LMCFGR_LANENB_Pos)          /*!< 0x00000700 */
+#define CSI_LMCFGR_LANENB               CSI_LMCFGR_LANENB_Msk                    /*!< Number of lanes */
+#define CSI_LMCFGR_DL0MAP_Pos           (16U)
+#define CSI_LMCFGR_DL0MAP_Msk           (0x7UL << CSI_LMCFGR_DL0MAP_Pos)          /*!< 0x00070000 */
+#define CSI_LMCFGR_DL0MAP               CSI_LMCFGR_DL0MAP_Msk                    /*!< Physical mapping of logical data lane 0 */
+#define CSI_LMCFGR_DL1MAP_Pos           (20U)
+#define CSI_LMCFGR_DL1MAP_Msk           (0x7UL << CSI_LMCFGR_DL1MAP_Pos)          /*!< 0x00700000 */
+#define CSI_LMCFGR_DL1MAP               CSI_LMCFGR_DL1MAP_Msk                    /*!< Physical mapping of logical data lane 1 */
+
+/******************  Bit definition for CSI_PRGITR register  ******************/
+#define CSI_PRGITR_LB0VC_Pos            (0U)
+#define CSI_PRGITR_LB0VC_Msk            (0x3UL << CSI_PRGITR_LB0VC_Pos)           /*!< 0x00000003 */
+#define CSI_PRGITR_LB0VC                CSI_PRGITR_LB0VC_Msk                     /*!< Line/Byte counter 0 linked to a virtual channel */
+#define CSI_PRGITR_LB0EN_Pos            (3U)
+#define CSI_PRGITR_LB0EN_Msk            (0x1UL << CSI_PRGITR_LB0EN_Pos)           /*!< 0x00000008 */
+#define CSI_PRGITR_LB0EN                CSI_PRGITR_LB0EN_Msk                     /*!< Line/Byte 0counter enable */
+#define CSI_PRGITR_LB1VC_Pos            (4U)
+#define CSI_PRGITR_LB1VC_Msk            (0x3UL << CSI_PRGITR_LB1VC_Pos)           /*!< 0x00000030 */
+#define CSI_PRGITR_LB1VC                CSI_PRGITR_LB1VC_Msk                     /*!< Line/Byte counter 1 linked to a virtual channel */
+#define CSI_PRGITR_LB1EN_Pos            (7U)
+#define CSI_PRGITR_LB1EN_Msk            (0x1UL << CSI_PRGITR_LB1EN_Pos)           /*!< 0x00000080 */
+#define CSI_PRGITR_LB1EN                CSI_PRGITR_LB1EN_Msk                     /*!< Line/Byte 1 counter enable */
+#define CSI_PRGITR_LB2VC_Pos            (8U)
+#define CSI_PRGITR_LB2VC_Msk            (0x3UL << CSI_PRGITR_LB2VC_Pos)           /*!< 0x00000300 */
+#define CSI_PRGITR_LB2VC                CSI_PRGITR_LB2VC_Msk                     /*!< Line/Byte counter 2 linked to a virtual channel */
+#define CSI_PRGITR_LB2EN_Pos            (11U)
+#define CSI_PRGITR_LB2EN_Msk            (0x1UL << CSI_PRGITR_LB2EN_Pos)           /*!< 0x00000800 */
+#define CSI_PRGITR_LB2EN                CSI_PRGITR_LB2EN_Msk                     /*!< Line/Byte 2 counter enable */
+#define CSI_PRGITR_LB3VC_Pos            (12U)
+#define CSI_PRGITR_LB3VC_Msk            (0x3UL << CSI_PRGITR_LB3VC_Pos)           /*!< 0x00003000 */
+#define CSI_PRGITR_LB3VC                CSI_PRGITR_LB3VC_Msk                     /*!< Line/Byte counter 3 linked to a virtual channel */
+#define CSI_PRGITR_LB3EN_Pos            (15U)
+#define CSI_PRGITR_LB3EN_Msk            (0x1UL << CSI_PRGITR_LB3EN_Pos)           /*!< 0x00008000 */
+#define CSI_PRGITR_LB3EN                CSI_PRGITR_LB3EN_Msk                     /*!< Line/Byte 3 counter enable */
+#define CSI_PRGITR_TIM0VC_Pos           (16U)
+#define CSI_PRGITR_TIM0VC_Msk           (0x3UL << CSI_PRGITR_TIM0VC_Pos)          /*!< 0x00030000 */
+#define CSI_PRGITR_TIM0VC               CSI_PRGITR_TIM0VC_Msk                    /*!< TIM0 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM0EOF_Pos          (18U)
+#define CSI_PRGITR_TIM0EOF_Msk          (0x1UL << CSI_PRGITR_TIM0EOF_Pos)         /*!< 0x00040000 */
+#define CSI_PRGITR_TIM0EOF              CSI_PRGITR_TIM0EOF_Msk                   /*!< TIM0 base time starting from the end of frame */
+#define CSI_PRGITR_TIM0EN_Pos           (19U)
+#define CSI_PRGITR_TIM0EN_Msk           (0x1UL << CSI_PRGITR_TIM0EN_Pos)          /*!< 0x00080000 */
+#define CSI_PRGITR_TIM0EN               CSI_PRGITR_TIM0EN_Msk                    /*!< TIM0 base time enable */
+#define CSI_PRGITR_TIM1VC_Pos           (20U)
+#define CSI_PRGITR_TIM1VC_Msk           (0x3UL << CSI_PRGITR_TIM1VC_Pos)          /*!< 0x00300000 */
+#define CSI_PRGITR_TIM1VC               CSI_PRGITR_TIM1VC_Msk                    /*!< TIM1 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM1EOF_Pos          (22U)
+#define CSI_PRGITR_TIM1EOF_Msk          (0x1UL << CSI_PRGITR_TIM1EOF_Pos)         /*!< 0x00400000 */
+#define CSI_PRGITR_TIM1EOF              CSI_PRGITR_TIM1EOF_Msk                   /*!< TIM1 base time starting from the end of frame */
+#define CSI_PRGITR_TIM1EN_Pos           (23U)
+#define CSI_PRGITR_TIM1EN_Msk           (0x1UL << CSI_PRGITR_TIM1EN_Pos)          /*!< 0x00800000 */
+#define CSI_PRGITR_TIM1EN               CSI_PRGITR_TIM1EN_Msk                    /*!< TIM1 base time enable */
+#define CSI_PRGITR_TIM2VC_Pos           (24U)
+#define CSI_PRGITR_TIM2VC_Msk           (0x3UL << CSI_PRGITR_TIM2VC_Pos)          /*!< 0x03000000 */
+#define CSI_PRGITR_TIM2VC               CSI_PRGITR_TIM2VC_Msk                    /*!< TIM2 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM2EOF_Pos          (26U)
+#define CSI_PRGITR_TIM2EOF_Msk          (0x1UL << CSI_PRGITR_TIM2EOF_Pos)         /*!< 0x04000000 */
+#define CSI_PRGITR_TIM2EOF              CSI_PRGITR_TIM2EOF_Msk                   /*!< TIM2 base time starting from the end of frame */
+#define CSI_PRGITR_TIM2EN_Pos           (27U)
+#define CSI_PRGITR_TIM2EN_Msk           (0x1UL << CSI_PRGITR_TIM2EN_Pos)          /*!< 0x08000000 */
+#define CSI_PRGITR_TIM2EN               CSI_PRGITR_TIM2EN_Msk                    /*!< TIM2 base time enable */
+#define CSI_PRGITR_TIM3VC_Pos           (28U)
+#define CSI_PRGITR_TIM3VC_Msk           (0x3UL << CSI_PRGITR_TIM3VC_Pos)          /*!< 0x30000000 */
+#define CSI_PRGITR_TIM3VC               CSI_PRGITR_TIM3VC_Msk                    /*!< TIM3 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM3EOF_Pos          (30U)
+#define CSI_PRGITR_TIM3EOF_Msk          (0x1UL << CSI_PRGITR_TIM3EOF_Pos)         /*!< 0x40000000 */
+#define CSI_PRGITR_TIM3EOF              CSI_PRGITR_TIM3EOF_Msk                   /*!< TIM3 base time starting from the end of frame */
+#define CSI_PRGITR_TIM3EN_Pos           (31U)
+#define CSI_PRGITR_TIM3EN_Msk           (0x1UL << CSI_PRGITR_TIM3EN_Pos)          /*!< 0x80000000 */
+#define CSI_PRGITR_TIM3EN               CSI_PRGITR_TIM3EN_Msk                    /*!< TIM3 base time enable */
+
+/*******************  Bit definition for CSI_WDR register  ********************/
+#define CSI_WDR_CNT_Pos                 (0U)
+#define CSI_WDR_CNT_Msk                 (0xFFFFFFFFUL << CSI_WDR_CNT_Pos)         /*!< 0xFFFFFFFF */
+#define CSI_WDR_CNT                     CSI_WDR_CNT_Msk                          /*!< Watchdog counter */
+
+/*******************  Bit definition for CSI_IER0 register  *******************/
+#define CSI_IER0_LB0IE_Pos              (0U)
+#define CSI_IER0_LB0IE_Msk              (0x1UL << CSI_IER0_LB0IE_Pos)             /*!< 0x00000001 */
+#define CSI_IER0_LB0IE                  CSI_IER0_LB0IE_Msk                       /*!< Line byte counter 0 interrupt enable */
+#define CSI_IER0_LB1IE_Pos              (1U)
+#define CSI_IER0_LB1IE_Msk              (0x1UL << CSI_IER0_LB1IE_Pos)             /*!< 0x00000002 */
+#define CSI_IER0_LB1IE                  CSI_IER0_LB1IE_Msk                       /*!< Line byte counter 1 interrupt enable */
+#define CSI_IER0_LB2IE_Pos              (2U)
+#define CSI_IER0_LB2IE_Msk              (0x1UL << CSI_IER0_LB2IE_Pos)             /*!< 0x00000004 */
+#define CSI_IER0_LB2IE                  CSI_IER0_LB2IE_Msk                       /*!< Line byte counter 2 interrupt enable */
+#define CSI_IER0_LB3IE_Pos              (3U)
+#define CSI_IER0_LB3IE_Msk              (0x1UL << CSI_IER0_LB3IE_Pos)             /*!< 0x00000008 */
+#define CSI_IER0_LB3IE                  CSI_IER0_LB3IE_Msk                       /*!< Line byte counter 3 interrupt enable */
+#define CSI_IER0_TIM0IE_Pos             (4U)
+#define CSI_IER0_TIM0IE_Msk             (0x1UL << CSI_IER0_TIM0IE_Pos)            /*!< 0x00000010 */
+#define CSI_IER0_TIM0IE                 CSI_IER0_TIM0IE_Msk                      /*!< Timer 0 interrupt enable */
+#define CSI_IER0_TIM1IE_Pos             (5U)
+#define CSI_IER0_TIM1IE_Msk             (0x1UL << CSI_IER0_TIM1IE_Pos)            /*!< 0x00000020 */
+#define CSI_IER0_TIM1IE                 CSI_IER0_TIM1IE_Msk                      /*!< Timer 1 interrupt enable */
+#define CSI_IER0_TIM2IE_Pos             (6U)
+#define CSI_IER0_TIM2IE_Msk             (0x1UL << CSI_IER0_TIM2IE_Pos)            /*!< 0x00000040 */
+#define CSI_IER0_TIM2IE                 CSI_IER0_TIM2IE_Msk                      /*!< Timer 2 interrupt enable */
+#define CSI_IER0_TIM3IE_Pos             (7U)
+#define CSI_IER0_TIM3IE_Msk             (0x1UL << CSI_IER0_TIM3IE_Pos)            /*!< 0x00000080 */
+#define CSI_IER0_TIM3IE                 CSI_IER0_TIM3IE_Msk                      /*!< Timer 3 interrupt enable */
+#define CSI_IER0_SOF0IE_Pos             (8U)
+#define CSI_IER0_SOF0IE_Msk             (0x1UL << CSI_IER0_SOF0IE_Pos)            /*!< 0x00000100 */
+#define CSI_IER0_SOF0IE                 CSI_IER0_SOF0IE_Msk                      /*!< Start of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_SOF1IE_Pos             (9U)
+#define CSI_IER0_SOF1IE_Msk             (0x1UL << CSI_IER0_SOF1IE_Pos)            /*!< 0x00000200 */
+#define CSI_IER0_SOF1IE                 CSI_IER0_SOF1IE_Msk                      /*!< Start of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_SOF2IE_Pos             (10U)
+#define CSI_IER0_SOF2IE_Msk             (0x1UL << CSI_IER0_SOF2IE_Pos)            /*!< 0x00000400 */
+#define CSI_IER0_SOF2IE                 CSI_IER0_SOF2IE_Msk                      /*!< Start of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_SOF3IE_Pos             (11U)
+#define CSI_IER0_SOF3IE_Msk             (0x1UL << CSI_IER0_SOF3IE_Pos)            /*!< 0x00000800 */
+#define CSI_IER0_SOF3IE                 CSI_IER0_SOF3IE_Msk                      /*!< Start of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_EOF0IE_Pos             (12U)
+#define CSI_IER0_EOF0IE_Msk             (0x1UL << CSI_IER0_EOF0IE_Pos)            /*!< 0x00001000 */
+#define CSI_IER0_EOF0IE                 CSI_IER0_EOF0IE_Msk                      /*!< End of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_EOF1IE_Pos             (13U)
+#define CSI_IER0_EOF1IE_Msk             (0x1UL << CSI_IER0_EOF1IE_Pos)            /*!< 0x00002000 */
+#define CSI_IER0_EOF1IE                 CSI_IER0_EOF1IE_Msk                      /*!< End of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_EOF2IE_Pos             (14U)
+#define CSI_IER0_EOF2IE_Msk             (0x1UL << CSI_IER0_EOF2IE_Pos)            /*!< 0x00004000 */
+#define CSI_IER0_EOF2IE                 CSI_IER0_EOF2IE_Msk                      /*!< End of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_EOF3IE_Pos             (15U)
+#define CSI_IER0_EOF3IE_Msk             (0x1UL << CSI_IER0_EOF3IE_Pos)            /*!< 0x00008000 */
+#define CSI_IER0_EOF3IE                 CSI_IER0_EOF3IE_Msk                      /*!< End of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_SPKTIE_Pos             (16U)
+#define CSI_IER0_SPKTIE_Msk             (0x1UL << CSI_IER0_SPKTIE_Pos)            /*!< 0x00010000 */
+#define CSI_IER0_SPKTIE                 CSI_IER0_SPKTIE_Msk                      /*!< Short packet interrupt enable */
+#define CSI_IER0_CCFIFOFIE_Pos          (21U)
+#define CSI_IER0_CCFIFOFIE_Msk          (0x1UL << CSI_IER0_CCFIFOFIE_Pos)         /*!< 0x00200000 */
+#define CSI_IER0_CCFIFOFIE              CSI_IER0_CCFIFOFIE_Msk                   /*!< Clock changer FIFO full interrupt enable */
+#define CSI_IER0_CRCERRIE_Pos           (24U)
+#define CSI_IER0_CRCERRIE_Msk           (0x1UL << CSI_IER0_CRCERRIE_Pos)          /*!< 0x01000000 */
+#define CSI_IER0_CRCERRIE               CSI_IER0_CRCERRIE_Msk                    /*!< CRC error interrupt enable */
+#define CSI_IER0_ECCERRIE_Pos           (25U)
+#define CSI_IER0_ECCERRIE_Msk           (0x1UL << CSI_IER0_ECCERRIE_Pos)          /*!< 0x02000000 */
+#define CSI_IER0_ECCERRIE               CSI_IER0_ECCERRIE_Msk                    /*!< ECC error interrupt enable */
+#define CSI_IER0_CECCERRIE_Pos          (26U)
+#define CSI_IER0_CECCERRIE_Msk          (0x1UL << CSI_IER0_CECCERRIE_Pos)         /*!< 0x04000000 */
+#define CSI_IER0_CECCERRIE              CSI_IER0_CECCERRIE_Msk                   /*!< Corrected ECC error interrupt enable */
+#define CSI_IER0_IDERRIE_Pos            (27U)
+#define CSI_IER0_IDERRIE_Msk            (0x1UL << CSI_IER0_IDERRIE_Pos)           /*!< 0x08000000 */
+#define CSI_IER0_IDERRIE                CSI_IER0_IDERRIE_Msk                     /*!< Data type ID error interrupt enable */
+#define CSI_IER0_SPKTERRIE_Pos          (28U)
+#define CSI_IER0_SPKTERRIE_Msk          (0x1UL << CSI_IER0_SPKTERRIE_Pos)         /*!< 0x10000000 */
+#define CSI_IER0_SPKTERRIE              CSI_IER0_SPKTERRIE_Msk                   /*!< Short packet error interrupt enable */
+#define CSI_IER0_WDERRIE_Pos            (29U)
+#define CSI_IER0_WDERRIE_Msk            (0x1UL << CSI_IER0_WDERRIE_Pos)           /*!< 0x20000000 */
+#define CSI_IER0_WDERRIE                CSI_IER0_WDERRIE_Msk                     /*!< Watchdog error interrupt enable */
+#define CSI_IER0_SYNCERRIE_Pos          (30U)
+#define CSI_IER0_SYNCERRIE_Msk          (0x1UL << CSI_IER0_SYNCERRIE_Pos)         /*!< 0x40000000 */
+#define CSI_IER0_SYNCERRIE              CSI_IER0_SYNCERRIE_Msk                   /*!< Invalid synchronization error interrupt enable */
+
+/*******************  Bit definition for CSI_IER1 register  *******************/
+#define CSI_IER1_ESOTDL0IE_Pos          (0U)
+#define CSI_IER1_ESOTDL0IE_Msk          (0x1UL << CSI_IER1_ESOTDL0IE_Pos)         /*!< 0x00000001 */
+#define CSI_IER1_ESOTDL0IE              CSI_IER1_ESOTDL0IE_Msk                   /*!< Start of transmission error interrupt enable on lane 0 */
+#define CSI_IER1_ESOTSYNCDL0IE_Pos      (1U)
+#define CSI_IER1_ESOTSYNCDL0IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos)     /*!< 0x00000002 */
+#define CSI_IER1_ESOTSYNCDL0IE          CSI_IER1_ESOTSYNCDL0IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 0 */
+#define CSI_IER1_EESCDL0IE_Pos          (2U)
+#define CSI_IER1_EESCDL0IE_Msk          (0x1UL << CSI_IER1_EESCDL0IE_Pos)         /*!< 0x00000004 */
+#define CSI_IER1_EESCDL0IE              CSI_IER1_EESCDL0IE_Msk                   /*!< D-PHY_RX lane 0 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL0IE_Pos      (3U)
+#define CSI_IER1_ESYNCESCDL0IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos)     /*!< 0x00000008 */
+#define CSI_IER1_ESYNCESCDL0IE          CSI_IER1_ESYNCESCDL0IE_Msk               /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL0IE_Pos         (4U)
+#define CSI_IER1_ECTRLDL0IE_Msk         (0x1UL << CSI_IER1_ECTRLDL0IE_Pos)        /*!< 0x00000010 */
+#define CSI_IER1_ECTRLDL0IE             CSI_IER1_ECTRLDL0IE_Msk                  /*!< D-PHY_RX lane 0 control error interrupt enable */
+#define CSI_IER1_ESOTDL1IE_Pos          (8U)
+#define CSI_IER1_ESOTDL1IE_Msk          (0x1UL << CSI_IER1_ESOTDL1IE_Pos)         /*!< 0x00000100 */
+#define CSI_IER1_ESOTDL1IE              CSI_IER1_ESOTDL1IE_Msk                   /*!< Start of transmission error interrupt enable on lane 1 */
+#define CSI_IER1_ESOTSYNCDL1IE_Pos      (9U)
+#define CSI_IER1_ESOTSYNCDL1IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos)     /*!< 0x00000200 */
+#define CSI_IER1_ESOTSYNCDL1IE          CSI_IER1_ESOTSYNCDL1IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 1 */
+#define CSI_IER1_EESCDL1IE_Pos          (10U)
+#define CSI_IER1_EESCDL1IE_Msk          (0x1UL << CSI_IER1_EESCDL1IE_Pos)         /*!< 0x00000400 */
+#define CSI_IER1_EESCDL1IE              CSI_IER1_EESCDL1IE_Msk                   /*!< D-PHY_RX lane 1 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL1IE_Pos      (11U)
+#define CSI_IER1_ESYNCESCDL1IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos)     /*!< 0x00000800 */
+#define CSI_IER1_ESYNCESCDL1IE          CSI_IER1_ESYNCESCDL1IE_Msk               /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL1IE_Pos         (12U)
+#define CSI_IER1_ECTRLDL1IE_Msk         (0x1UL << CSI_IER1_ECTRLDL1IE_Pos)        /*!< 0x00001000 */
+#define CSI_IER1_ECTRLDL1IE             CSI_IER1_ECTRLDL1IE_Msk                  /*!< D-PHY_RX lane 1 control error interrupt enable */
+
+/*******************  Bit definition for CSI_SR0 register  ********************/
+#define CSI_SR0_LB0F_Pos                (0U)
+#define CSI_SR0_LB0F_Msk                (0x1UL << CSI_SR0_LB0F_Pos)               /*!< 0x00000001 */
+#define CSI_SR0_LB0F                    CSI_SR0_LB0F_Msk                         /*!< Line byte counter 0 flag */
+#define CSI_SR0_LB1F_Pos                (1U)
+#define CSI_SR0_LB1F_Msk                (0x1UL << CSI_SR0_LB1F_Pos)               /*!< 0x00000002 */
+#define CSI_SR0_LB1F                    CSI_SR0_LB1F_Msk                         /*!< Line byte counter 1 flag */
+#define CSI_SR0_LB2F_Pos                (2U)
+#define CSI_SR0_LB2F_Msk                (0x1UL << CSI_SR0_LB2F_Pos)               /*!< 0x00000004 */
+#define CSI_SR0_LB2F                    CSI_SR0_LB2F_Msk                         /*!< Line byte counter 2 flag */
+#define CSI_SR0_LB3F_Pos                (3U)
+#define CSI_SR0_LB3F_Msk                (0x1UL << CSI_SR0_LB3F_Pos)               /*!< 0x00000008 */
+#define CSI_SR0_LB3F                    CSI_SR0_LB3F_Msk                         /*!< Line byte counter 3 flag */
+#define CSI_SR0_TIM0F_Pos               (4U)
+#define CSI_SR0_TIM0F_Msk               (0x1UL << CSI_SR0_TIM0F_Pos)              /*!< 0x00000010 */
+#define CSI_SR0_TIM0F                   CSI_SR0_TIM0F_Msk                        /*!< Timer 0 flag */
+#define CSI_SR0_TIM1F_Pos               (5U)
+#define CSI_SR0_TIM1F_Msk               (0x1UL << CSI_SR0_TIM1F_Pos)              /*!< 0x00000020 */
+#define CSI_SR0_TIM1F                   CSI_SR0_TIM1F_Msk                        /*!< Timer 1 flag */
+#define CSI_SR0_TIM2F_Pos               (6U)
+#define CSI_SR0_TIM2F_Msk               (0x1UL << CSI_SR0_TIM2F_Pos)              /*!< 0x00000040 */
+#define CSI_SR0_TIM2F                   CSI_SR0_TIM2F_Msk                        /*!< Timer 2 flag */
+#define CSI_SR0_TIM3F_Pos               (7U)
+#define CSI_SR0_TIM3F_Msk               (0x1UL << CSI_SR0_TIM3F_Pos)              /*!< 0x00000080 */
+#define CSI_SR0_TIM3F                   CSI_SR0_TIM3F_Msk                        /*!< Timer 3 flag */
+#define CSI_SR0_SOF0F_Pos               (8U)
+#define CSI_SR0_SOF0F_Msk               (0x1UL << CSI_SR0_SOF0F_Pos)              /*!< 0x00000100 */
+#define CSI_SR0_SOF0F                   CSI_SR0_SOF0F_Msk                        /*!< Start of frame flag for virtual channel 0 */
+#define CSI_SR0_SOF1F_Pos               (9U)
+#define CSI_SR0_SOF1F_Msk               (0x1UL << CSI_SR0_SOF1F_Pos)              /*!< 0x00000200 */
+#define CSI_SR0_SOF1F                   CSI_SR0_SOF1F_Msk                        /*!< Start of frame flag for virtual channel 1 */
+#define CSI_SR0_SOF2F_Pos               (10U)
+#define CSI_SR0_SOF2F_Msk               (0x1UL << CSI_SR0_SOF2F_Pos)              /*!< 0x00000400 */
+#define CSI_SR0_SOF2F                   CSI_SR0_SOF2F_Msk                        /*!< Start of frame flag for virtual channel 2 */
+#define CSI_SR0_SOF3F_Pos               (11U)
+#define CSI_SR0_SOF3F_Msk               (0x1UL << CSI_SR0_SOF3F_Pos)              /*!< 0x00000800 */
+#define CSI_SR0_SOF3F                   CSI_SR0_SOF3F_Msk                        /*!< Start of frame flag for virtual channel 3 */
+#define CSI_SR0_EOF0F_Pos               (12U)
+#define CSI_SR0_EOF0F_Msk               (0x1UL << CSI_SR0_EOF0F_Pos)              /*!< 0x00001000 */
+#define CSI_SR0_EOF0F                   CSI_SR0_EOF0F_Msk                        /*!< End of frame flag for virtual channel 0 */
+#define CSI_SR0_EOF1F_Pos               (13U)
+#define CSI_SR0_EOF1F_Msk               (0x1UL << CSI_SR0_EOF1F_Pos)              /*!< 0x00002000 */
+#define CSI_SR0_EOF1F                   CSI_SR0_EOF1F_Msk                        /*!< End of frame flag for virtual channel 1 */
+#define CSI_SR0_EOF2F_Pos               (14U)
+#define CSI_SR0_EOF2F_Msk               (0x1UL << CSI_SR0_EOF2F_Pos)              /*!< 0x00004000 */
+#define CSI_SR0_EOF2F                   CSI_SR0_EOF2F_Msk                        /*!< End of frame flag for virtual channel 2 */
+#define CSI_SR0_EOF3F_Pos               (15U)
+#define CSI_SR0_EOF3F_Msk               (0x1UL << CSI_SR0_EOF3F_Pos)              /*!< 0x00008000 */
+#define CSI_SR0_EOF3F                   CSI_SR0_EOF3F_Msk                        /*!< End of frame flag for virtual channel 3 */
+#define CSI_SR0_SPKTF_Pos               (16U)
+#define CSI_SR0_SPKTF_Msk               (0x1UL << CSI_SR0_SPKTF_Pos)              /*!< 0x00010000 */
+#define CSI_SR0_SPKTF                   CSI_SR0_SPKTF_Msk                        /*!< Short packet flag */
+#define CSI_SR0_VC0STATEF_Pos           (17U)
+#define CSI_SR0_VC0STATEF_Msk           (0x1UL << CSI_SR0_VC0STATEF_Pos)          /*!< 0x00020000 */
+#define CSI_SR0_VC0STATEF               CSI_SR0_VC0STATEF_Msk                    /*!< Virtual channel 0 state flag */
+#define CSI_SR0_VC1STATEF_Pos           (18U)
+#define CSI_SR0_VC1STATEF_Msk           (0x1UL << CSI_SR0_VC1STATEF_Pos)          /*!< 0x00040000 */
+#define CSI_SR0_VC1STATEF               CSI_SR0_VC1STATEF_Msk                    /*!< Virtual channel 1 state flag */
+#define CSI_SR0_VC2STATEF_Pos           (19U)
+#define CSI_SR0_VC2STATEF_Msk           (0x1UL << CSI_SR0_VC2STATEF_Pos)          /*!< 0x00080000 */
+#define CSI_SR0_VC2STATEF               CSI_SR0_VC2STATEF_Msk                    /*!< Virtual channel 2 state flag */
+#define CSI_SR0_VC3STATEF_Pos           (20U)
+#define CSI_SR0_VC3STATEF_Msk           (0x1UL << CSI_SR0_VC3STATEF_Pos)          /*!< 0x00100000 */
+#define CSI_SR0_VC3STATEF               CSI_SR0_VC3STATEF_Msk                    /*!< Virtual channel 3 state flag */
+#define CSI_SR0_CCFIFOFF_Pos            (21U)
+#define CSI_SR0_CCFIFOFF_Msk            (0x1UL << CSI_SR0_CCFIFOFF_Pos)           /*!< 0x00200000 */
+#define CSI_SR0_CCFIFOFF                CSI_SR0_CCFIFOFF_Msk                     /*!< Clock changer FIFO full flag */
+#define CSI_SR0_CRCERRF_Pos             (24U)
+#define CSI_SR0_CRCERRF_Msk             (0x1UL << CSI_SR0_CRCERRF_Pos)            /*!< 0x01000000 */
+#define CSI_SR0_CRCERRF                 CSI_SR0_CRCERRF_Msk                      /*!< CRC error flag */
+#define CSI_SR0_ECCERRF_Pos             (25U)
+#define CSI_SR0_ECCERRF_Msk             (0x1UL << CSI_SR0_ECCERRF_Pos)            /*!< 0x02000000 */
+#define CSI_SR0_ECCERRF                 CSI_SR0_ECCERRF_Msk                      /*!< ECC error flag */
+#define CSI_SR0_CECCERRF_Pos            (26U)
+#define CSI_SR0_CECCERRF_Msk            (0x1UL << CSI_SR0_CECCERRF_Pos)           /*!< 0x04000000 */
+#define CSI_SR0_CECCERRF                CSI_SR0_CECCERRF_Msk                     /*!< Corrected ECC error flag */
+#define CSI_SR0_IDERRF_Pos              (27U)
+#define CSI_SR0_IDERRF_Msk              (0x1UL << CSI_SR0_IDERRF_Pos)             /*!< 0x08000000 */
+#define CSI_SR0_IDERRF                  CSI_SR0_IDERRF_Msk                       /*!< Data type ID error flag */
+#define CSI_SR0_SPKTERRF_Pos            (28U)
+#define CSI_SR0_SPKTERRF_Msk            (0x1UL << CSI_SR0_SPKTERRF_Pos)           /*!< 0x10000000 */
+#define CSI_SR0_SPKTERRF                CSI_SR0_SPKTERRF_Msk                     /*!< Short packet error flag */
+#define CSI_SR0_WDERRF_Pos              (29U)
+#define CSI_SR0_WDERRF_Msk              (0x1UL << CSI_SR0_WDERRF_Pos)             /*!< 0x20000000 */
+#define CSI_SR0_WDERRF                  CSI_SR0_WDERRF_Msk                       /*!< Watchdog error flag */
+#define CSI_SR0_SYNCERRF_Pos            (30U)
+#define CSI_SR0_SYNCERRF_Msk            (0x1UL << CSI_SR0_SYNCERRF_Pos)           /*!< 0x40000000 */
+#define CSI_SR0_SYNCERRF                CSI_SR0_SYNCERRF_Msk                     /*!< Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_SR1 register  ********************/
+#define CSI_SR1_ESOTDL0F_Pos            (0U)
+#define CSI_SR1_ESOTDL0F_Msk            (0x1UL << CSI_SR1_ESOTDL0F_Pos)           /*!< 0x00000001 */
+#define CSI_SR1_ESOTDL0F                CSI_SR1_ESOTDL0F_Msk                     /*!< Start of transmission error flag on lane 0 */
+#define CSI_SR1_ESOTSYNCDL0F_Pos        (1U)
+#define CSI_SR1_ESOTSYNCDL0F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos)       /*!< 0x00000002 */
+#define CSI_SR1_ESOTSYNCDL0F            CSI_SR1_ESOTSYNCDL0F_Msk                 /*!< Start of transmission synchronization error flag on lane 0 */
+#define CSI_SR1_EESCDL0F_Pos            (2U)
+#define CSI_SR1_EESCDL0F_Msk            (0x1UL << CSI_SR1_EESCDL0F_Pos)           /*!< 0x00000004 */
+#define CSI_SR1_EESCDL0F                CSI_SR1_EESCDL0F_Msk                     /*!< D-PHY_RX lane 0 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL0F_Pos        (3U)
+#define CSI_SR1_ESYNCESCDL0F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos)       /*!< 0x00000008 */
+#define CSI_SR1_ESYNCESCDL0F            CSI_SR1_ESYNCESCDL0F_Msk                 /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL0F_Pos           (4U)
+#define CSI_SR1_ECTRLDL0F_Msk           (0x1UL << CSI_SR1_ECTRLDL0F_Pos)          /*!< 0x00000010 */
+#define CSI_SR1_ECTRLDL0F               CSI_SR1_ECTRLDL0F_Msk                    /*!< D-PHY_RX lane 0 control error flag */
+#define CSI_SR1_ESOTDL1F_Pos            (8U)
+#define CSI_SR1_ESOTDL1F_Msk            (0x1UL << CSI_SR1_ESOTDL1F_Pos)           /*!< 0x00000100 */
+#define CSI_SR1_ESOTDL1F                CSI_SR1_ESOTDL1F_Msk                     /*!< Start of transmission error flag on lane 1 */
+#define CSI_SR1_ESOTSYNCDL1F_Pos        (9U)
+#define CSI_SR1_ESOTSYNCDL1F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos)       /*!< 0x00000200 */
+#define CSI_SR1_ESOTSYNCDL1F            CSI_SR1_ESOTSYNCDL1F_Msk                 /*!< Start of transmission synchronization error flag on lane 1 */
+#define CSI_SR1_EESCDL1F_Pos            (10U)
+#define CSI_SR1_EESCDL1F_Msk            (0x1UL << CSI_SR1_EESCDL1F_Pos)           /*!< 0x00000400 */
+#define CSI_SR1_EESCDL1F                CSI_SR1_EESCDL1F_Msk                     /*!< D-PHY_RX lane 1 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL1F_Pos        (11U)
+#define CSI_SR1_ESYNCESCDL1F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos)       /*!< 0x00000800 */
+#define CSI_SR1_ESYNCESCDL1F            CSI_SR1_ESYNCESCDL1F_Msk                 /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL1F_Pos           (12U)
+#define CSI_SR1_ECTRLDL1F_Msk           (0x1UL << CSI_SR1_ECTRLDL1F_Pos)          /*!< 0x00001000 */
+#define CSI_SR1_ECTRLDL1F               CSI_SR1_ECTRLDL1F_Msk                    /*!< D-PHY_RX lane 1 control error flag */
+#define CSI_SR1_ACTDL0F_Pos             (16U)
+#define CSI_SR1_ACTDL0F_Msk             (0x1UL << CSI_SR1_ACTDL0F_Pos)            /*!< 0x00010000 */
+#define CSI_SR1_ACTDL0F                 CSI_SR1_ACTDL0F_Msk                      /*!< D-PHY_RX lane 0 High speed reception active */
+#define CSI_SR1_SYNCDL0F_Pos            (17U)
+#define CSI_SR1_SYNCDL0F_Msk            (0x1UL << CSI_SR1_SYNCDL0F_Pos)           /*!< 0x00020000 */
+#define CSI_SR1_SYNCDL0F                CSI_SR1_SYNCDL0F_Msk                     /*!< D-PHY_RX lane 0 receiver synchronization observed */
+#define CSI_SR1_SKCALDL0F_Pos           (18U)
+#define CSI_SR1_SKCALDL0F_Msk           (0x1UL << CSI_SR1_SKCALDL0F_Pos)          /*!< 0x00040000 */
+#define CSI_SR1_SKCALDL0F               CSI_SR1_SKCALDL0F_Msk                    /*!< D-PHY_RX lane 0 High speed skew calibration */
+#define CSI_SR1_STOPDL0F_Pos            (19U)
+#define CSI_SR1_STOPDL0F_Msk            (0x1UL << CSI_SR1_STOPDL0F_Pos)           /*!< 0x00080000 */
+#define CSI_SR1_STOPDL0F                CSI_SR1_STOPDL0F_Msk                     /*!< D-PHY_RX receiver data lane 0 in stop state */
+#define CSI_SR1_ULPNDL0F_Pos            (20U)
+#define CSI_SR1_ULPNDL0F_Msk            (0x1UL << CSI_SR1_ULPNDL0F_Pos)           /*!< 0x00100000 */
+#define CSI_SR1_ULPNDL0F                CSI_SR1_ULPNDL0F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */
+#define CSI_SR1_ACTDL1F_Pos             (22U)
+#define CSI_SR1_ACTDL1F_Msk             (0x1UL << CSI_SR1_ACTDL1F_Pos)            /*!< 0x00400000 */
+#define CSI_SR1_ACTDL1F                 CSI_SR1_ACTDL1F_Msk                      /*!< D-PHY_RX lane 1 High speed reception active */
+#define CSI_SR1_SYNCDL1F_Pos            (23U)
+#define CSI_SR1_SYNCDL1F_Msk            (0x1UL << CSI_SR1_SYNCDL1F_Pos)           /*!< 0x00800000 */
+#define CSI_SR1_SYNCDL1F                CSI_SR1_SYNCDL1F_Msk                     /*!< D-PHY_RX lane 1 receiver synchronization observed */
+#define CSI_SR1_SKCALDL1F_Pos           (24U)
+#define CSI_SR1_SKCALDL1F_Msk           (0x1UL << CSI_SR1_SKCALDL1F_Pos)          /*!< 0x01000000 */
+#define CSI_SR1_SKCALDL1F               CSI_SR1_SKCALDL1F_Msk                    /*!< D-PHY_RX lane 1 High speed skew calibration */
+#define CSI_SR1_STOPDL1F_Pos            (25U)
+#define CSI_SR1_STOPDL1F_Msk            (0x1UL << CSI_SR1_STOPDL1F_Pos)           /*!< 0x02000000 */
+#define CSI_SR1_STOPDL1F                CSI_SR1_STOPDL1F_Msk                     /*!< D-PHY_RX receiver data lane 1 in stop state */
+#define CSI_SR1_ULPNDL1F_Pos            (26U)
+#define CSI_SR1_ULPNDL1F_Msk            (0x1UL << CSI_SR1_ULPNDL1F_Pos)           /*!< 0x04000000 */
+#define CSI_SR1_ULPNDL1F                CSI_SR1_ULPNDL1F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */
+#define CSI_SR1_STOPCLF_Pos             (28U)
+#define CSI_SR1_STOPCLF_Msk             (0x1UL << CSI_SR1_STOPCLF_Pos)            /*!< 0x10000000 */
+#define CSI_SR1_STOPCLF                 CSI_SR1_STOPCLF_Msk                      /*!< D-PHY_RX receiver in stop state for the clock lane */
+#define CSI_SR1_ULPNACTF_Pos            (29U)
+#define CSI_SR1_ULPNACTF_Msk            (0x1UL << CSI_SR1_ULPNACTF_Pos)           /*!< 0x20000000 */
+#define CSI_SR1_ULPNACTF                CSI_SR1_ULPNACTF_Msk                     /*!< D-PHY_RX receiver ULP state (not) active */
+#define CSI_SR1_ULPNCLF_Pos             (30U)
+#define CSI_SR1_ULPNCLF_Msk             (0x1UL << CSI_SR1_ULPNCLF_Pos)            /*!< 0x40000000 */
+#define CSI_SR1_ULPNCLF                 CSI_SR1_ULPNCLF_Msk                      /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */
+#define CSI_SR1_ACTCLF_Pos              (31U)
+#define CSI_SR1_ACTCLF_Msk              (0x1UL << CSI_SR1_ACTCLF_Pos)             /*!< 0x80000000 */
+#define CSI_SR1_ACTCLF                  CSI_SR1_ACTCLF_Msk                       /*!< D-PHY_RX receiver clock active flag */
+
+/*******************  Bit definition for CSI_FCR0 register  *******************/
+#define CSI_FCR0_CLB0F_Pos              (0U)
+#define CSI_FCR0_CLB0F_Msk              (0x1UL << CSI_FCR0_CLB0F_Pos)             /*!< 0x00000001 */
+#define CSI_FCR0_CLB0F                  CSI_FCR0_CLB0F_Msk                       /*!< Clear Line byte counter 0 flag */
+#define CSI_FCR0_CLB1F_Pos              (1U)
+#define CSI_FCR0_CLB1F_Msk              (0x1UL << CSI_FCR0_CLB1F_Pos)             /*!< 0x00000002 */
+#define CSI_FCR0_CLB1F                  CSI_FCR0_CLB1F_Msk                       /*!< Clear Line byte counter 1 flag */
+#define CSI_FCR0_CLB2F_Pos              (2U)
+#define CSI_FCR0_CLB2F_Msk              (0x1UL << CSI_FCR0_CLB2F_Pos)             /*!< 0x00000004 */
+#define CSI_FCR0_CLB2F                  CSI_FCR0_CLB2F_Msk                       /*!< Clear Line byte counter 2 flag */
+#define CSI_FCR0_CLB3F_Pos              (3U)
+#define CSI_FCR0_CLB3F_Msk              (0x1UL << CSI_FCR0_CLB3F_Pos)             /*!< 0x00000008 */
+#define CSI_FCR0_CLB3F                  CSI_FCR0_CLB3F_Msk                       /*!< Clear Line byte counter 3 flag */
+#define CSI_FCR0_CTIM0F_Pos             (4U)
+#define CSI_FCR0_CTIM0F_Msk             (0x1UL << CSI_FCR0_CTIM0F_Pos)            /*!< 0x00000010 */
+#define CSI_FCR0_CTIM0F                 CSI_FCR0_CTIM0F_Msk                      /*!< Clear Timer 0 flag */
+#define CSI_FCR0_CTIM1F_Pos             (5U)
+#define CSI_FCR0_CTIM1F_Msk             (0x1UL << CSI_FCR0_CTIM1F_Pos)            /*!< 0x00000020 */
+#define CSI_FCR0_CTIM1F                 CSI_FCR0_CTIM1F_Msk                      /*!< Clear Timer 1 flag */
+#define CSI_FCR0_CTIM2F_Pos             (6U)
+#define CSI_FCR0_CTIM2F_Msk             (0x1UL << CSI_FCR0_CTIM2F_Pos)            /*!< 0x00000040 */
+#define CSI_FCR0_CTIM2F                 CSI_FCR0_CTIM2F_Msk                      /*!< Clear Timer 2 flag */
+#define CSI_FCR0_CTIM3F_Pos             (7U)
+#define CSI_FCR0_CTIM3F_Msk             (0x1UL << CSI_FCR0_CTIM3F_Pos)            /*!< 0x00000080 */
+#define CSI_FCR0_CTIM3F                 CSI_FCR0_CTIM3F_Msk                      /*!< Clear Timer 3 flag */
+#define CSI_FCR0_CSOF0F_Pos             (8U)
+#define CSI_FCR0_CSOF0F_Msk             (0x1UL << CSI_FCR0_CSOF0F_Pos)            /*!< 0x00000100 */
+#define CSI_FCR0_CSOF0F                 CSI_FCR0_CSOF0F_Msk                      /*!< Clear Start of frame flag for virtual channel 0 */
+#define CSI_FCR0_CSOF1F_Pos             (9U)
+#define CSI_FCR0_CSOF1F_Msk             (0x1UL << CSI_FCR0_CSOF1F_Pos)            /*!< 0x00000200 */
+#define CSI_FCR0_CSOF1F                 CSI_FCR0_CSOF1F_Msk                      /*!< Clear Start of frame flag for virtual channel 1 */
+#define CSI_FCR0_CSOF2F_Pos             (10U)
+#define CSI_FCR0_CSOF2F_Msk             (0x1UL << CSI_FCR0_CSOF2F_Pos)            /*!< 0x00000400 */
+#define CSI_FCR0_CSOF2F                 CSI_FCR0_CSOF2F_Msk                      /*!< Clear Start of frame flag for virtual channel 2 */
+#define CSI_FCR0_CSOF3F_Pos             (11U)
+#define CSI_FCR0_CSOF3F_Msk             (0x1UL << CSI_FCR0_CSOF3F_Pos)            /*!< 0x00000800 */
+#define CSI_FCR0_CSOF3F                 CSI_FCR0_CSOF3F_Msk                      /*!< Clear Start of frame flag for virtual channel 3 */
+#define CSI_FCR0_CEOF0F_Pos             (12U)
+#define CSI_FCR0_CEOF0F_Msk             (0x1UL << CSI_FCR0_CEOF0F_Pos)            /*!< 0x00001000 */
+#define CSI_FCR0_CEOF0F                 CSI_FCR0_CEOF0F_Msk                      /*!< Clear End of frame flag for virtual channel 0 */
+#define CSI_FCR0_CEOF1F_Pos             (13U)
+#define CSI_FCR0_CEOF1F_Msk             (0x1UL << CSI_FCR0_CEOF1F_Pos)            /*!< 0x00002000 */
+#define CSI_FCR0_CEOF1F                 CSI_FCR0_CEOF1F_Msk                      /*!< Clear End of frame flag for virtual channel 1 */
+#define CSI_FCR0_CEOF2F_Pos             (14U)
+#define CSI_FCR0_CEOF2F_Msk             (0x1UL << CSI_FCR0_CEOF2F_Pos)            /*!< 0x00004000 */
+#define CSI_FCR0_CEOF2F                 CSI_FCR0_CEOF2F_Msk                      /*!< Clear End of frame flag for virtual channel 2 */
+#define CSI_FCR0_CEOF3F_Pos             (15U)
+#define CSI_FCR0_CEOF3F_Msk             (0x1UL << CSI_FCR0_CEOF3F_Pos)            /*!< 0x00008000 */
+#define CSI_FCR0_CEOF3F                 CSI_FCR0_CEOF3F_Msk                      /*!< Clear End of frame flag for virtual channel 3 */
+#define CSI_FCR0_CSPKTF_Pos             (16U)
+#define CSI_FCR0_CSPKTF_Msk             (0x1UL << CSI_FCR0_CSPKTF_Pos)            /*!< 0x00010000 */
+#define CSI_FCR0_CSPKTF                 CSI_FCR0_CSPKTF_Msk                      /*!< Clear Short packet flag */
+#define CSI_FCR0_CCCFIFOFF_Pos          (21U)
+#define CSI_FCR0_CCCFIFOFF_Msk          (0x1UL << CSI_FCR0_CCCFIFOFF_Pos)         /*!< 0x00200000 */
+#define CSI_FCR0_CCCFIFOFF              CSI_FCR0_CCCFIFOFF_Msk                   /*!< Clear Clock changer FIFO full flag */
+#define CSI_FCR0_CCRCERRF_Pos           (24U)
+#define CSI_FCR0_CCRCERRF_Msk           (0x1UL << CSI_FCR0_CCRCERRF_Pos)          /*!< 0x01000000 */
+#define CSI_FCR0_CCRCERRF               CSI_FCR0_CCRCERRF_Msk                    /*!< Clear CRC error flag */
+#define CSI_FCR0_CECCERRF_Pos           (25U)
+#define CSI_FCR0_CECCERRF_Msk           (0x1UL << CSI_FCR0_CECCERRF_Pos)          /*!< 0x02000000 */
+#define CSI_FCR0_CECCERRF               CSI_FCR0_CECCERRF_Msk                    /*!< Clear ECC error flag */
+#define CSI_FCR0_CCECCERRF_Pos          (26U)
+#define CSI_FCR0_CCECCERRF_Msk          (0x1UL << CSI_FCR0_CCECCERRF_Pos)         /*!< 0x04000000 */
+#define CSI_FCR0_CCECCERRF              CSI_FCR0_CCECCERRF_Msk                   /*!< Clear Corrected ECC error flag */
+#define CSI_FCR0_CIDERRF_Pos            (27U)
+#define CSI_FCR0_CIDERRF_Msk            (0x1UL << CSI_FCR0_CIDERRF_Pos)           /*!< 0x08000000 */
+#define CSI_FCR0_CIDERRF                CSI_FCR0_CIDERRF_Msk                     /*!< Clear Data type ID error flag */
+#define CSI_FCR0_CSPKTERRF_Pos          (28U)
+#define CSI_FCR0_CSPKTERRF_Msk          (0x1UL << CSI_FCR0_CSPKTERRF_Pos)         /*!< 0x10000000 */
+#define CSI_FCR0_CSPKTERRF              CSI_FCR0_CSPKTERRF_Msk                   /*!< Clear Short packet error flag */
+#define CSI_FCR0_CWDERRF_Pos            (29U)
+#define CSI_FCR0_CWDERRF_Msk            (0x1UL << CSI_FCR0_CWDERRF_Pos)           /*!< 0x20000000 */
+#define CSI_FCR0_CWDERRF                CSI_FCR0_CWDERRF_Msk                     /*!< Clear Watchdog error flag */
+#define CSI_FCR0_CSYNCERRF_Pos          (30U)
+#define CSI_FCR0_CSYNCERRF_Msk          (0x1UL << CSI_FCR0_CSYNCERRF_Pos)         /*!< 0x40000000 */
+#define CSI_FCR0_CSYNCERRF              CSI_FCR0_CSYNCERRF_Msk                   /*!< Clear Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_FCR1 register  *******************/
+#define CSI_FCR1_CESOTDL0F_Pos          (0U)
+#define CSI_FCR1_CESOTDL0F_Msk          (0x1UL << CSI_FCR1_CESOTDL0F_Pos)         /*!< 0x00000001 */
+#define CSI_FCR1_CESOTDL0F              CSI_FCR1_CESOTDL0F_Msk                   /*!< Clear Start of transmission error flag on lane 0 */
+#define CSI_FCR1_CESOTSYNCDL0F_Pos      (1U)
+#define CSI_FCR1_CESOTSYNCDL0F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos)     /*!< 0x00000002 */
+#define CSI_FCR1_CESOTSYNCDL0F          CSI_FCR1_CESOTSYNCDL0F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 0 */
+#define CSI_FCR1_CEESCDL0F_Pos          (2U)
+#define CSI_FCR1_CEESCDL0F_Msk          (0x1UL << CSI_FCR1_CEESCDL0F_Pos)         /*!< 0x00000004 */
+#define CSI_FCR1_CEESCDL0F              CSI_FCR1_CEESCDL0F_Msk                   /*!< Clear D-PHY_RX lane 0 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL0F_Pos      (3U)
+#define CSI_FCR1_CESYNCESCDL0F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos)     /*!< 0x00000008 */
+#define CSI_FCR1_CESYNCESCDL0F          CSI_FCR1_CESYNCESCDL0F_Msk               /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL0F_Pos         (4U)
+#define CSI_FCR1_CECTRLDL0F_Msk         (0x1UL << CSI_FCR1_CECTRLDL0F_Pos)        /*!< 0x00000010 */
+#define CSI_FCR1_CECTRLDL0F             CSI_FCR1_CECTRLDL0F_Msk                  /*!< Clear D-PHY_RX lane 0 control error flag */
+#define CSI_FCR1_CESOTDL1F_Pos          (8U)
+#define CSI_FCR1_CESOTDL1F_Msk          (0x1UL << CSI_FCR1_CESOTDL1F_Pos)         /*!< 0x00000100 */
+#define CSI_FCR1_CESOTDL1F              CSI_FCR1_CESOTDL1F_Msk                   /*!< Clear Start of transmission error flag on lane 1 */
+#define CSI_FCR1_CESOTSYNCDL1F_Pos      (9U)
+#define CSI_FCR1_CESOTSYNCDL1F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos)     /*!< 0x00000200 */
+#define CSI_FCR1_CESOTSYNCDL1F          CSI_FCR1_CESOTSYNCDL1F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 1 */
+#define CSI_FCR1_CEESCDL1F_Pos          (10U)
+#define CSI_FCR1_CEESCDL1F_Msk          (0x1UL << CSI_FCR1_CEESCDL1F_Pos)         /*!< 0x00000400 */
+#define CSI_FCR1_CEESCDL1F              CSI_FCR1_CEESCDL1F_Msk                   /*!< Clear D-PHY_RX lane 1 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL1F_Pos      (11U)
+#define CSI_FCR1_CESYNCESCDL1F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos)     /*!< 0x00000800 */
+#define CSI_FCR1_CESYNCESCDL1F          CSI_FCR1_CESYNCESCDL1F_Msk               /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL1F_Pos         (12U)
+#define CSI_FCR1_CECTRLDL1F_Msk         (0x1UL << CSI_FCR1_CECTRLDL1F_Pos)        /*!< 0x00001000 */
+#define CSI_FCR1_CECTRLDL1F             CSI_FCR1_CECTRLDL1F_Msk                  /*!< Clear D-PHY_RX lane 1 control error flag */
+
+/******************  Bit definition for CSI_SPDFR register  *******************/
+#define CSI_SPDFR_DATAFIELD_Pos         (0U)
+#define CSI_SPDFR_DATAFIELD_Msk         (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos)     /*!< 0x0000FFFF */
+#define CSI_SPDFR_DATAFIELD             CSI_SPDFR_DATAFIELD_Msk                  /*!< Data field */
+#define CSI_SPDFR_DATATYPE_Pos          (16U)
+#define CSI_SPDFR_DATATYPE_Msk          (0x3FUL << CSI_SPDFR_DATATYPE_Pos)        /*!< 0x003F0000 */
+#define CSI_SPDFR_DATATYPE              CSI_SPDFR_DATATYPE_Msk                   /*!< Data type class */
+#define CSI_SPDFR_VCHANNEL_Pos          (22U)
+#define CSI_SPDFR_VCHANNEL_Msk          (0x3UL << CSI_SPDFR_VCHANNEL_Pos)         /*!< 0x00C00000 */
+#define CSI_SPDFR_VCHANNEL              CSI_SPDFR_VCHANNEL_Msk                   /*!< Virtual channel */
+
+/*******************  Bit definition for CSI_ERR1 register  *******************/
+#define CSI_ERR1_CRCDTERR_Pos           (0U)
+#define CSI_ERR1_CRCDTERR_Msk           (0x3FUL << CSI_ERR1_CRCDTERR_Pos)         /*!< 0x0000003F */
+#define CSI_ERR1_CRCDTERR               CSI_ERR1_CRCDTERR_Msk                    /*!< Data type having a CRC error */
+#define CSI_ERR1_CRCVCERR_Pos           (6U)
+#define CSI_ERR1_CRCVCERR_Msk           (0x3UL << CSI_ERR1_CRCVCERR_Pos)          /*!< 0x000000C0 */
+#define CSI_ERR1_CRCVCERR               CSI_ERR1_CRCVCERR_Msk                    /*!< Virtual channel having a CRC error */
+#define CSI_ERR1_CECCDTERR_Pos          (8U)
+#define CSI_ERR1_CECCDTERR_Msk          (0x3FUL << CSI_ERR1_CECCDTERR_Pos)        /*!< 0x00003F00 */
+#define CSI_ERR1_CECCDTERR              CSI_ERR1_CECCDTERR_Msk                   /*!< Data type having a corrected ECC error */
+#define CSI_ERR1_CECCVCERR_Pos          (14U)
+#define CSI_ERR1_CECCVCERR_Msk          (0x3UL << CSI_ERR1_CECCVCERR_Pos)         /*!< 0x0000C000 */
+#define CSI_ERR1_CECCVCERR              CSI_ERR1_CECCVCERR_Msk                   /*!< Virtual channel having a corrected ECC error */
+#define CSI_ERR1_IDDTERR_Pos            (16U)
+#define CSI_ERR1_IDDTERR_Msk            (0x3FUL << CSI_ERR1_IDDTERR_Pos)          /*!< 0x003F0000 */
+#define CSI_ERR1_IDDTERR                CSI_ERR1_IDDTERR_Msk                     /*!< Data type in error */
+#define CSI_ERR1_IDVCERR_Pos            (22U)
+#define CSI_ERR1_IDVCERR_Msk            (0x3UL << CSI_ERR1_IDVCERR_Pos)           /*!< 0x00C00000 */
+#define CSI_ERR1_IDVCERR                CSI_ERR1_IDVCERR_Msk                     /*!< Virtual channel having ID error */
+
+/*******************  Bit definition for CSI_ERR2 register  *******************/
+#define CSI_ERR2_SPKTDTERR_Pos          (0U)
+#define CSI_ERR2_SPKTDTERR_Msk          (0x3FUL << CSI_ERR2_SPKTDTERR_Pos)        /*!< 0x0000003F */
+#define CSI_ERR2_SPKTDTERR              CSI_ERR2_SPKTDTERR_Msk                   /*!< Data type having a short packet error */
+#define CSI_ERR2_SPKTVCERR_Pos          (6U)
+#define CSI_ERR2_SPKTVCERR_Msk          (0x3UL << CSI_ERR2_SPKTVCERR_Pos)         /*!< 0x000000C0 */
+#define CSI_ERR2_SPKTVCERR              CSI_ERR2_SPKTVCERR_Msk                   /*!< Virtual channel having a short packet error */
+#define CSI_ERR2_WDVCERR_Pos            (16U)
+#define CSI_ERR2_WDVCERR_Msk            (0x3UL << CSI_ERR2_WDVCERR_Pos)           /*!< 0x00030000 */
+#define CSI_ERR2_WDVCERR                CSI_ERR2_WDVCERR_Msk                     /*!< Virtual channel having a watchdog error */
+#define CSI_ERR2_SYNCVCERR_Pos          (18U)
+#define CSI_ERR2_SYNCVCERR_Msk          (0x3UL << CSI_ERR2_SYNCVCERR_Pos)         /*!< 0x000C0000 */
+#define CSI_ERR2_SYNCVCERR              CSI_ERR2_SYNCVCERR_Msk                   /*!< Virtual channel having synchronization error */
+
+/*******************  Bit definition for CSI_PRCR register  *******************/
+#define CSI_PRCR_PEN_Pos                (1U)
+#define CSI_PRCR_PEN_Msk                (0x1UL << CSI_PRCR_PEN_Pos)               /*!< 0x00000002 */
+#define CSI_PRCR_PEN                    CSI_PRCR_PEN_Msk                         /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */
+
+/*******************  Bit definition for CSI_PMCR register  *******************/
+#define CSI_PMCR_FRXMDL0_Pos            (0U)
+#define CSI_PMCR_FRXMDL0_Msk            (0x1UL << CSI_PMCR_FRXMDL0_Pos)           /*!< 0x00000001 */
+#define CSI_PMCR_FRXMDL0                CSI_PMCR_FRXMDL0_Msk                     /*!< Force to Rx Mode the Data Lane 0 */
+#define CSI_PMCR_FRXMDL1_Pos            (1U)
+#define CSI_PMCR_FRXMDL1_Msk            (0x1UL << CSI_PMCR_FRXMDL1_Pos)           /*!< 0x00000002 */
+#define CSI_PMCR_FRXMDL1                CSI_PMCR_FRXMDL1_Msk                     /*!< Force to Rx Mode the Data Lane 1 */
+#define CSI_PMCR_FTXSMDL0_Pos           (2U)
+#define CSI_PMCR_FTXSMDL0_Msk           (0x1UL << CSI_PMCR_FTXSMDL0_Pos)          /*!< 0x00000004 */
+#define CSI_PMCR_FTXSMDL0               CSI_PMCR_FTXSMDL0_Msk                    /*!< Force to Tx Stop Mode the Data Lane 0 */
+#define CSI_PMCR_DTDL_Pos               (4U)
+#define CSI_PMCR_DTDL_Msk               (0x1UL << CSI_PMCR_DTDL_Pos)              /*!< 0x00000010 */
+#define CSI_PMCR_DTDL                   CSI_PMCR_DTDL_Msk                        /*!< Disable Turn-around Data Lane 0 */
+#define CSI_PMCR_RTDL0_Pos              (8U)
+#define CSI_PMCR_RTDL0_Msk              (0x1UL << CSI_PMCR_RTDL0_Pos)             /*!< 0x00000100 */
+#define CSI_PMCR_RTDL0                  CSI_PMCR_RTDL0_Msk                       /*!< Turn-around Request Data Lane 0 */
+#define CSI_PMCR_TUESDL0_Pos            (12U)
+#define CSI_PMCR_TUESDL0_Msk            (0x1UL << CSI_PMCR_TUESDL0_Pos)           /*!< 0x00001000 */
+#define CSI_PMCR_TUESDL0                CSI_PMCR_TUESDL0_Msk                     /*!< Tx ULP Escape-mode Data Lane 0 */
+#define CSI_PMCR_TUEXDL0_Pos            (16U)
+#define CSI_PMCR_TUEXDL0_Msk            (0x1UL << CSI_PMCR_TUEXDL0_Pos)           /*!< 0x00010000 */
+#define CSI_PMCR_TUEXDL0                CSI_PMCR_TUEXDL0_Msk                     /*!< Tx ULP Exit-sequence Data Lane 0 */
+
+/*******************  Bit definition for CSI_PFCR register  *******************/
+#define CSI_PFCR_CCFR_Pos               (0U)
+#define CSI_PFCR_CCFR_Msk               (0x3FUL << CSI_PFCR_CCFR_Pos)             /*!< 0x0000003F */
+#define CSI_PFCR_CCFR                   CSI_PFCR_CCFR_Msk                        /*!< Configuration Clock Frequency Range selection */
+#define CSI_PFCR_HSFR_Pos               (8U)
+#define CSI_PFCR_HSFR_Msk               (0x7FUL << CSI_PFCR_HSFR_Pos)             /*!< 0x00007F00 */
+#define CSI_PFCR_HSFR                   CSI_PFCR_HSFR_Msk                        /*!< PHY-high-speed Frequency Range selection */
+#define CSI_PFCR_DLD_Pos                (16U)
+#define CSI_PFCR_DLD_Msk                (0x1UL << CSI_PFCR_DLD_Pos)               /*!< 0x00010000 */
+#define CSI_PFCR_DLD                    CSI_PFCR_DLD_Msk                         /*!< Data Lane Direction of lane0 */
+
+/******************  Bit definition for CSI_PTCR0 register  *******************/
+#define CSI_PTCR0_TCKEN_Pos             (0U)
+#define CSI_PTCR0_TCKEN_Msk             (0x1UL << CSI_PTCR0_TCKEN_Pos)            /*!< 0x00000001 */
+#define CSI_PTCR0_TCKEN                 CSI_PTCR0_TCKEN_Msk                      /*!< Test-interface Clock Enable for the TDI bus into the PHY */
+#define CSI_PTCR0_TRSEN_Pos             (1U)
+#define CSI_PTCR0_TRSEN_Msk             (0x1UL << CSI_PTCR0_TRSEN_Pos)            /*!< 0x00000002 */
+#define CSI_PTCR0_TRSEN                 CSI_PTCR0_TRSEN_Msk                      /*!< Test-interface Reset Enable for the TDI bus into the PHY */
+
+/******************  Bit definition for CSI_PTCR1 register  *******************/
+#define CSI_PTCR1_TDI_Pos               (0U)
+#define CSI_PTCR1_TDI_Msk               (0xFFUL << CSI_PTCR1_TDI_Pos)             /*!< 0x000000FF */
+#define CSI_PTCR1_TDI                   CSI_PTCR1_TDI_Msk                        /*!< Test-interface Data In */
+#define CSI_PTCR1_TWM_Pos               (16U)
+#define CSI_PTCR1_TWM_Msk               (0x1UL << CSI_PTCR1_TWM_Pos)              /*!< 0x00010000 */
+#define CSI_PTCR1_TWM                   CSI_PTCR1_TWM_Msk                        /*!< Test-interface Write Mode selector */
+
+/*******************  Bit definition for CSI_PTSR register  *******************/
+#define CSI_PTSR_TDO_Pos                (0U)
+#define CSI_PTSR_TDO_Msk                (0xFFUL << CSI_PTSR_TDO_Pos)              /*!< 0x000000FF */
+#define CSI_PTSR_TDO                    CSI_PTSR_TDO_Msk                         /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                DBGMCU                                         */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  ****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos             (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk             (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)          /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                 DBGMCU_IDCODE_DEV_ID_Msk                       /*!< Device ID */
+#define DBGMCU_IDCODE_REV_ID_Pos             (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk             (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)         /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                 DBGMCU_IDCODE_REV_ID_Msk                       /*!< Revision ID */
+
+/********************  Bit definition for DBGMCU_CR register  ********************/
+#define DBGMCU_CR_DBG_SLEEP_Pos              (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk              (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)             /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                  DBGMCU_CR_DBG_SLEEP_Msk                        /*!< Allow debug in Sleep mode */
+#define DBGMCU_CR_DBG_STOP_Pos               (1U)
+#define DBGMCU_CR_DBG_STOP_Msk               (0x1UL << DBGMCU_CR_DBG_STOP_Pos)              /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                   DBGMCU_CR_DBG_STOP_Msk                         /*!< Allow debug in Stop mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos            (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk            (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)           /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                DBGMCU_CR_DBG_STANDBY_Msk                      /*!< Allow debug in Standby mode */
+#define DBGMCU_CR_DBGCLKEN_Pos               (20U)
+#define DBGMCU_CR_DBGCLKEN_Msk               (0x1UL << DBGMCU_CR_DBGCLKEN_Pos)              /*!< 0x00100000 */
+#define DBGMCU_CR_DBGCLKEN                   DBGMCU_CR_DBGCLKEN_Msk                         /*!< Debug clock enable through software */
+#define DBGMCU_CR_TRACECLKEN_Pos             (21U)
+#define DBGMCU_CR_TRACECLKEN_Msk             (0x1UL << DBGMCU_CR_TRACECLKEN_Pos)            /*!< 0x00200000 */
+#define DBGMCU_CR_TRACECLKEN                 DBGMCU_CR_TRACECLKEN_Msk                       /*!< TPIU export clock enable through software */
+#define DBGMCU_CR_DBTRGOEN_Pos               (28U)
+#define DBGMCU_CR_DBTRGOEN_Msk               (0x1UL << DBGMCU_CR_DBTRGOEN_Pos)              /*!< 0x10000000 */
+#define DBGMCU_CR_DBTRGOEN                   DBGMCU_CR_DBTRGOEN_Msk                         /*!< DBTRGIO connection control */
+#define DBGMCU_CR_HLT_TSGEN_EN_Pos           (31U)
+#define DBGMCU_CR_HLT_TSGEN_EN_Msk           (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos)          /*!< 0x80000000 */
+#define DBGMCU_CR_HLT_TSGEN_EN               DBGMCU_CR_HLT_TSGEN_EN_Msk                     /*!< TSGEN halt enable */
+
+/********************  Bit definition for DBGMCU_APB1LFZ1 register  ***************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos    (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP        DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk              /*!< TIM2 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos    (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP        DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk              /*!< TIM3 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos    (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP        DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk              /*!< TIM4 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos    (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP        DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk              /*!< TIM5 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos    (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP        DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk              /*!< TIM6 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos    (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos)  /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP        DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk             /*!< TIM7 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos   (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos)  /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP       DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk             /*!< TIM12 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos   (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos)  /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP       DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk             /*!< TIM13 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos   (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP       DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk             /*!< TIM14 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos  (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP      DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk            /*!< LPTIM1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos   (11U)
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP       DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk             /*!< WWDG1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos   (12U)
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP       DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk             /*!< TIM10 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos   (13U)
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP       DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk             /*!< TIM11 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos    (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos)   /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP        DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk              /*!< I2C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos    (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos)   /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP        DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk              /*!< I2C2 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos    (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos)   /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP        DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk              /*!< I2C3 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos    (24U)
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos)   /*!< 0x01000000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP        DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk              /*!< I3C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos    (25U)
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP        DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk              /*!< I3C2 SMBUS timeout stop in debug */
+
+/********************  Bit definition for DBGMCU_APB1HFZ1 register  ***************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos   (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk   (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP       DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk             /*!< FDCAN stop in debug */
+
+/********************  Bit definition for DBGMCU_APB2FZ1 register  ***************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos     (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos)    /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP         DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk               /*!< TIM1 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos     (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos)    /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP         DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk               /*!< TIM8 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos    (15U)
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP        DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk              /*!< TIM18 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos    (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos)   /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP        DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk              /*!< TIM15 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos    (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos)   /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP        DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk              /*!< TIM16 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos    (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos)   /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP        DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk              /*!< TIM17 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos     (19U)
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos)    /*!< 0x00080000 */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP         DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk               /*!< TIM9 stop in debug */
+
+/********************  Bit definition for DBGMCU_APB4FZ1 register  ***************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos     (8U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos)    /*!< 0x00000100 */
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP         DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk               /*!< I2C4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos   (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos)  /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP       DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk             /*!< LPTIM2 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos   (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP       DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk             /*!< LPTIM3 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos   (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP       DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk             /*!< LPTIM4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos   (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP       DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk             /*!< LPTIM5 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos      (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos)     /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP          DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk                /*!< RTC stop in debug */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos     (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos)    /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP         DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk               /*!< IWDG stop in debug */
+
+/********************  Bit definition for DBGMCU_APB5FZ1 register  ***************/
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos   (4U)
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk   (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos)  /*!< 0x00000010 */
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP       DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk             /*!< GFXTIM stop in debug */
+
+/********************  Bit definition for DBGMCU_AHB1FZ1 register  ***************/
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk              /*!< GPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk              /*!< GPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk              /*!< GPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk              /*!< GPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk              /*!< GPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk              /*!< GPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk              /*!< GPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk              /*!< GPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk              /*!< GPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk              /*!< GPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk             /*!< GPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk             /*!< GPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk             /*!< GPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk             /*!< GPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk             /*!< GPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk             /*!< GPDMA1_CH15 suspend in debug */
+
+/********************  Bit definition for DBGMCU_AHB5FZ1 register  ***************/
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk              /*!< HPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk              /*!< HPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk              /*!< HPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk              /*!< HPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk              /*!< HPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk              /*!< HPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk              /*!< HPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk              /*!< HPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk              /*!< HPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk              /*!< HPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk             /*!< HPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk             /*!< HPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk             /*!< HPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk             /*!< HPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk             /*!< HPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk             /*!< HPDMA1_CH15 suspend in debug */
+
+/********************  Bit definition for DBGMCU_SR register  ***************/
+#define DBGMCU_SR_AP0_PRESENT_Pos            (0U)
+#define DBGMCU_SR_AP0_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos)           /*!< 0x00000001 */
+#define DBGMCU_SR_AP0_PRESENT                DBGMCU_SR_AP0_PRESENT_Msk                      /*!< Access point 0 presence */
+#define DBGMCU_SR_AP1_PRESENT_Pos            (1U)
+#define DBGMCU_SR_AP1_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos)           /*!< 0x00000002 */
+#define DBGMCU_SR_AP1_PRESENT                DBGMCU_SR_AP1_PRESENT_Msk                      /*!< Access point 1 presence */
+#define DBGMCU_SR_AP0_ENABLE_Pos             (16U)
+#define DBGMCU_SR_AP0_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos)            /*!< 0x00010000 */
+#define DBGMCU_SR_AP0_ENABLE                 DBGMCU_SR_AP0_ENABLE_Msk                       /*!< Access point 0 enable */
+#define DBGMCU_SR_AP1_ENABLE_Pos             (17U)
+#define DBGMCU_SR_AP1_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos)            /*!< 0x00020000 */
+#define DBGMCU_SR_AP1_ENABLE                 DBGMCU_SR_AP1_ENABLE_Msk                       /*!< Access point 1 enable */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_HOST register  **********************/
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos     (0U)
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk     (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE         DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk                   /*!< Message[31:0] */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos      (0U)
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk      (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE          DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk                    /*!< Message[31:0] */
+
+/********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***************/
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos     (0U)
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk     (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos)    /*!< 0x00000001 */
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK         DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk               /*!< Access status to DBG_AUTH_HOST register */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos   (1U)
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk   (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos)  /*!< 0x00000002 */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK       DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk             /*!< Access status to DBG_AUTH_DEV register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos                 (0U)
+#define DCMI_CR_CAPTURE_Msk                 (0x1UL << DCMI_CR_CAPTURE_Pos)          /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE                     DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos                      (1U)
+#define DCMI_CR_CM_Msk                      (0x1UL << DCMI_CR_CM_Pos)               /*!< 0x00000002 */
+#define DCMI_CR_CM                          DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos                    (2U)
+#define DCMI_CR_CROP_Msk                    (0x1UL << DCMI_CR_CROP_Pos)             /*!< 0x00000004 */
+#define DCMI_CR_CROP                        DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos                    (3U)
+#define DCMI_CR_JPEG_Msk                    (0x1UL << DCMI_CR_JPEG_Pos)             /*!< 0x00000008 */
+#define DCMI_CR_JPEG                        DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos                     (4U)
+#define DCMI_CR_ESS_Msk                     (0x1UL << DCMI_CR_ESS_Pos)              /*!< 0x00000010 */
+#define DCMI_CR_ESS                         DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos                  (5U)
+#define DCMI_CR_PCKPOL_Msk                  (0x1UL << DCMI_CR_PCKPOL_Pos)           /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL                      DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos                   (6U)
+#define DCMI_CR_HSPOL_Msk                   (0x1UL << DCMI_CR_HSPOL_Pos)            /*!< 0x00000040 */
+#define DCMI_CR_HSPOL                       DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos                   (7U)
+#define DCMI_CR_VSPOL_Msk                   (0x1UL << DCMI_CR_VSPOL_Pos)            /*!< 0x00000080 */
+#define DCMI_CR_VSPOL                       DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_Pos                    (8U)
+#define DCMI_CR_FCRC_Msk                    (0x3UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000300 */
+#define DCMI_CR_FCRC                        DCMI_CR_FCRC_Msk                        /*!< DCMI Frame capture rate control FCRC[1:0] */
+#define DCMI_CR_FCRC_0                      (0x1UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000100 */
+#define DCMI_CR_FCRC_1                      (0x2UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000200 */
+#define DCMI_CR_EDM_Pos                     (10U)
+#define DCMI_CR_EDM_Msk                     (0x3UL << DCMI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define DCMI_CR_EDM                         DCMI_CR_EDM_Msk                         /*!< DCMI Extended data mode EDM[1:0] */
+#define DCMI_CR_EDM_0                       (0x1UL << DCMI_CR_EDM_Pos)              /*!< 0x00000400 */
+#define DCMI_CR_EDM_1                       (0x2UL << DCMI_CR_EDM_Pos)              /*!< 0x00000800 */
+#define DCMI_CR_ENABLE_Pos                  (14U)
+#define DCMI_CR_ENABLE_Msk                  (0x1UL << DCMI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define DCMI_CR_ENABLE                      DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos                     (16U)
+#define DCMI_CR_BSM_Msk                     (0x3UL << DCMI_CR_BSM_Pos)              /*!< 0x00030000 */
+#define DCMI_CR_BSM                         DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0                       (0x1UL << DCMI_CR_BSM_Pos)              /*!< 0x00010000 */
+#define DCMI_CR_BSM_1                       (0x2UL << DCMI_CR_BSM_Pos)              /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos                    (18U)
+#define DCMI_CR_OEBS_Msk                    (0x1UL << DCMI_CR_OEBS_Pos)             /*!< 0x00040000 */
+#define DCMI_CR_OEBS                        DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos                     (19U)
+#define DCMI_CR_LSM_Msk                     (0x1UL << DCMI_CR_LSM_Pos)              /*!< 0x00080000 */
+#define DCMI_CR_LSM                         DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos                    (20U)
+#define DCMI_CR_OELS_Msk                    (0x1UL << DCMI_CR_OELS_Pos)             /*!< 0x00100000 */
+#define DCMI_CR_OELS                        DCMI_CR_OELS_Msk
+#define DCMI_CR_PSDM_Pos                    (31U)
+#define DCMI_CR_PSDM_Msk                    (0x0UL << DCMI_CR_PSDM_Pos)             /*!< 0x00000000 */
+#define DCMI_CR_PSDM                        DCMI_CR_PSDM_Msk                        /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos                   (0U)
+#define DCMI_SR_HSYNC_Msk                   (0x1UL << DCMI_SR_HSYNC_Pos)            /*!< 0x00000001 */
+#define DCMI_SR_HSYNC                       DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos                   (1U)
+#define DCMI_SR_VSYNC_Msk                   (0x1UL << DCMI_SR_VSYNC_Pos)            /*!< 0x00000002 */
+#define DCMI_SR_VSYNC                       DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos                     (2U)
+#define DCMI_SR_FNE_Msk                     (0x1UL << DCMI_SR_FNE_Pos)              /*!< 0x00000004 */
+#define DCMI_SR_FNE                         DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos              (0U)
+#define DCMI_RIS_FRAME_RIS_Msk              (0x1UL << DCMI_RIS_FRAME_RIS_Pos)       /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS                  DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos                (1U)
+#define DCMI_RIS_OVR_RIS_Msk                (0x1UL << DCMI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS                    DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos                (2U)
+#define DCMI_RIS_ERR_RIS_Msk                (0x1UL << DCMI_RIS_ERR_RIS_Pos)         /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS                    DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos              (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk              (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)       /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos               (4U)
+#define DCMI_RIS_LINE_RIS_Msk               (0x1UL << DCMI_RIS_LINE_RIS_Pos)        /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS                   DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos               (0U)
+#define DCMI_IER_FRAME_IE_Msk               (0x1UL << DCMI_IER_FRAME_IE_Pos)        /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE                   DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos                 (1U)
+#define DCMI_IER_OVR_IE_Msk                 (0x1UL << DCMI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE                     DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos                 (2U)
+#define DCMI_IER_ERR_IE_Msk                 (0x1UL << DCMI_IER_ERR_IE_Pos)          /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE                     DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos               (3U)
+#define DCMI_IER_VSYNC_IE_Msk               (0x1UL << DCMI_IER_VSYNC_IE_Pos)        /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE                   DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos                (4U)
+#define DCMI_IER_LINE_IE_Msk                (0x1UL << DCMI_IER_LINE_IE_Pos)         /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE                    DCMI_IER_LINE_IE_Msk
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos              (0U)
+#define DCMI_MIS_FRAME_MIS_Msk              (0x1UL << DCMI_MIS_FRAME_MIS_Pos)       /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS                  DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos                (1U)
+#define DCMI_MIS_OVR_MIS_Msk                (0x1UL << DCMI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS                    DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos                (2U)
+#define DCMI_MIS_ERR_MIS_Msk                (0x1UL << DCMI_MIS_ERR_MIS_Pos)         /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS                    DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos              (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk              (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)       /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos               (4U)
+#define DCMI_MIS_LINE_MIS_Msk               (0x1UL << DCMI_MIS_LINE_MIS_Pos)        /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS                   DCMI_MIS_LINE_MIS_Msk
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos              (0U)
+#define DCMI_ICR_FRAME_ISC_Msk              (0x1UL << DCMI_ICR_FRAME_ISC_Pos)       /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC                  DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos                (1U)
+#define DCMI_ICR_OVR_ISC_Msk                (0x1UL << DCMI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC                    DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos                (2U)
+#define DCMI_ICR_ERR_ISC_Msk                (0x1UL << DCMI_ICR_ERR_ISC_Pos)         /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC                    DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos              (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk              (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)       /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC                  DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos               (4U)
+#define DCMI_ICR_LINE_ISC_Msk               (0x1UL << DCMI_ICR_LINE_ISC_Pos)        /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC                   DCMI_ICR_LINE_ISC_Msk
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos                   (0U)
+#define DCMI_ESCR_FSC_Msk                   (0xFFUL << DCMI_ESCR_FSC_Pos)           /*!< 0x000000FF */
+#define DCMI_ESCR_FSC                       DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos                   (8U)
+#define DCMI_ESCR_LSC_Msk                   (0xFFUL << DCMI_ESCR_LSC_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC                       DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos                   (16U)
+#define DCMI_ESCR_LEC_Msk                   (0xFFUL << DCMI_ESCR_LEC_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC                       DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos                   (24U)
+#define DCMI_ESCR_FEC_Msk                   (0xFFUL << DCMI_ESCR_FEC_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC                       DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos                   (0U)
+#define DCMI_ESUR_FSU_Msk                   (0xFFUL << DCMI_ESUR_FSU_Pos)           /*!< 0x000000FF */
+#define DCMI_ESUR_FSU                       DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos                   (8U)
+#define DCMI_ESUR_LSU_Msk                   (0xFFUL << DCMI_ESUR_LSU_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU                       DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos                   (16U)
+#define DCMI_ESUR_LEU_Msk                   (0xFFUL << DCMI_ESUR_LEU_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU                       DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos                   (24U)
+#define DCMI_ESUR_FEU_Msk                   (0xFFUL << DCMI_ESUR_FEU_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU                       DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos             (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk             (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)   /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT                 DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos                 (16U)
+#define DCMI_CWSTRT_VST_Msk                 (0x1FFFUL << DCMI_CWSTRT_VST_Pos)       /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST                     DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos              (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk              (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)    /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT                  DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos               (16U)
+#define DCMI_CWSIZE_VLINE_Msk               (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)     /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE                   DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos                   (0U)
+#define DCMI_DR_BYTE0_Msk                   (0xFFUL << DCMI_DR_BYTE0_Pos)           /*!< 0x000000FF */
+#define DCMI_DR_BYTE0                       DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos                   (8U)
+#define DCMI_DR_BYTE1_Msk                   (0xFFUL << DCMI_DR_BYTE1_Pos)           /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1                       DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos                   (16U)
+#define DCMI_DR_BYTE2_Msk                   (0xFFUL << DCMI_DR_BYTE2_Pos)           /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2                       DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos                   (24U)
+#define DCMI_DR_BYTE3_Msk                   (0xFFUL << DCMI_DR_BYTE3_Pos)           /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3                       DCMI_DR_BYTE3_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   DCMIPP                                   */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for DCMIPP_IPGR1 register  *****************/
+#define DCMIPP_IPGR1_MEMORYPAGE_Pos         (0U)
+#define DCMIPP_IPGR1_MEMORYPAGE_Msk         (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos)           /*!< 0x00000007 */
+#define DCMIPP_IPGR1_MEMORYPAGE             DCMIPP_IPGR1_MEMORYPAGE_Msk                     /*!< Memory page size, as power of 2 of 64-byte units: */
+#define DCMIPP_IPGR1_QOS_MODE_Pos           (24U)
+#define DCMIPP_IPGR1_QOS_MODE_Msk           (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_IPGR1_QOS_MODE               DCMIPP_IPGR1_QOS_MODE_Msk                       /*!< Quality of service */
+
+/*****************  Bit definition for DCMIPP_IPGR2 register  *****************/
+#define DCMIPP_IPGR2_PSTART_Pos             (0U)
+#define DCMIPP_IPGR2_PSTART_Msk             (0x1UL << DCMIPP_IPGR2_PSTART_Pos)               /*!< 0x00000001 */
+#define DCMIPP_IPGR2_PSTART                 DCMIPP_IPGR2_PSTART_Msk                         /*!< Request to lock the IP-Plug, to allow reconfiguration */
+
+/*****************  Bit definition for DCMIPP_IPGR3 register  *****************/
+#define DCMIPP_IPGR3_IDLE_Pos               (0U)
+#define DCMIPP_IPGR3_IDLE_Msk               (0x1UL << DCMIPP_IPGR3_IDLE_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_IPGR3_IDLE                   DCMIPP_IPGR3_IDLE_Msk                           /*!< Status of IP-Plug */
+
+/*****************  Bit definition for DCMIPP_IPGR8 register  *****************/
+#define DCMIPP_IPGR8_DID_Pos                (0U)
+#define DCMIPP_IPGR8_DID_Msk                (0x3FUL << DCMIPP_IPGR8_DID_Pos)                 /*!< 0x0000003F */
+#define DCMIPP_IPGR8_DID                    DCMIPP_IPGR8_DID_Msk                            /*!< Division identifier (0x14) */
+#define DCMIPP_IPGR8_REVID_Pos              (8U)
+#define DCMIPP_IPGR8_REVID_Msk              (0x1FUL << DCMIPP_IPGR8_REVID_Pos)               /*!< 0x00001F00 */
+#define DCMIPP_IPGR8_REVID                  DCMIPP_IPGR8_REVID_Msk                          /*!< Revision identifier (0x03) */
+#define DCMIPP_IPGR8_ARCHIID_Pos            (16U)
+#define DCMIPP_IPGR8_ARCHIID_Msk            (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos)             /*!< 0x001F0000 */
+#define DCMIPP_IPGR8_ARCHIID                DCMIPP_IPGR8_ARCHIID_Msk                        /*!< Architecture identifier (0x04) */
+#define DCMIPP_IPGR8_IPPID_Pos              (24U)
+#define DCMIPP_IPGR8_IPPID_Msk              (0xFFUL << DCMIPP_IPGR8_IPPID_Pos)               /*!< 0xFF000000 */
+#define DCMIPP_IPGR8_IPPID                  DCMIPP_IPGR8_IPPID_Msk                          /*!< IP identifier (0xAA) */
+
+/****************  Bit definition for DCMIPP_IPC1R1 register  *****************/
+#define DCMIPP_IPC1R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC1R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC1R1_TRAFFIC               DCMIPP_IPC1R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC1R1_OTR_Pos               (8U)
+#define DCMIPP_IPC1R1_OTR_Msk               (0xFUL << DCMIPP_IPC1R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC1R1_OTR                   DCMIPP_IPC1R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC1R2 register  *****************/
+#define DCMIPP_IPC1R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC1R2_WLRU_Msk              (0xFUL << DCMIPP_IPC1R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC1R2_WLRU                  DCMIPP_IPC1R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC1R3 register  *****************/
+#define DCMIPP_IPC1R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC1R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC1R3_DPREGSTART            DCMIPP_IPC1R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC1R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC1R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC1R3_DPREGEND              DCMIPP_IPC1R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC2R1 register  *****************/
+#define DCMIPP_IPC2R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC2R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC2R1_TRAFFIC               DCMIPP_IPC2R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC2R1_OTR_Pos               (8U)
+#define DCMIPP_IPC2R1_OTR_Msk               (0xFUL << DCMIPP_IPC2R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC2R1_OTR                   DCMIPP_IPC2R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC2R2 register  *****************/
+#define DCMIPP_IPC2R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC2R2_WLRU_Msk              (0xFUL << DCMIPP_IPC2R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC2R2_WLRU                  DCMIPP_IPC2R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC2R3 register  *****************/
+#define DCMIPP_IPC2R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC2R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC2R3_DPREGSTART            DCMIPP_IPC2R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC2R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC2R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC2R3_DPREGEND              DCMIPP_IPC2R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC3R1 register  *****************/
+#define DCMIPP_IPC3R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC3R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC3R1_TRAFFIC               DCMIPP_IPC3R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC3R1_OTR_Pos               (8U)
+#define DCMIPP_IPC3R1_OTR_Msk               (0xFUL << DCMIPP_IPC3R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC3R1_OTR                   DCMIPP_IPC3R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC3R2 register  *****************/
+#define DCMIPP_IPC3R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC3R2_WLRU_Msk              (0xFUL << DCMIPP_IPC3R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC3R2_WLRU                  DCMIPP_IPC3R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC3R3 register  *****************/
+#define DCMIPP_IPC3R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC3R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC3R3_DPREGSTART            DCMIPP_IPC3R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC3R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC3R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC3R3_DPREGEND              DCMIPP_IPC3R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC4R1 register  *****************/
+#define DCMIPP_IPC4R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC4R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC4R1_TRAFFIC               DCMIPP_IPC4R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC4R1_OTR_Pos               (8U)
+#define DCMIPP_IPC4R1_OTR_Msk               (0xFUL << DCMIPP_IPC4R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC4R1_OTR                   DCMIPP_IPC4R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC4R2 register  *****************/
+#define DCMIPP_IPC4R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC4R2_WLRU_Msk              (0xFUL << DCMIPP_IPC4R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC4R2_WLRU                  DCMIPP_IPC4R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC4R3 register  *****************/
+#define DCMIPP_IPC4R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC4R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC4R3_DPREGSTART            DCMIPP_IPC4R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC4R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC4R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC4R3_DPREGEND              DCMIPP_IPC4R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC5R1 register  *****************/
+#define DCMIPP_IPC5R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC5R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC5R1_TRAFFIC               DCMIPP_IPC5R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC5R1_OTR_Pos               (8U)
+#define DCMIPP_IPC5R1_OTR_Msk               (0xFUL << DCMIPP_IPC5R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC5R1_OTR                   DCMIPP_IPC5R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC5R2 register  *****************/
+#define DCMIPP_IPC5R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC5R2_WLRU_Msk              (0xFUL << DCMIPP_IPC5R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC5R2_WLRU                  DCMIPP_IPC5R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC5R3 register  *****************/
+#define DCMIPP_IPC5R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC5R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC5R3_DPREGSTART            DCMIPP_IPC5R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC5R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC5R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC5R3_DPREGEND              DCMIPP_IPC5R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/***************  Bit definition for DCMIPP_PRHWCFGR register  ****************/
+
+/*****************  Bit definition for DCMIPP_PRCR register  ******************/
+#define DCMIPP_PRCR_ESS_Pos                 (4U)
+#define DCMIPP_PRCR_ESS_Msk                 (0x1UL << DCMIPP_PRCR_ESS_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_PRCR_ESS                     DCMIPP_PRCR_ESS_Msk                             /*!< Embedded synchronization select */
+#define DCMIPP_PRCR_PCKPOL_Pos              (5U)
+#define DCMIPP_PRCR_PCKPOL_Msk              (0x1UL << DCMIPP_PRCR_PCKPOL_Pos)                /*!< 0x00000020 */
+#define DCMIPP_PRCR_PCKPOL                  DCMIPP_PRCR_PCKPOL_Msk                          /*!< Pixel clock polarity */
+#define DCMIPP_PRCR_HSPOL_Pos               (6U)
+#define DCMIPP_PRCR_HSPOL_Msk               (0x1UL << DCMIPP_PRCR_HSPOL_Pos)                 /*!< 0x00000040 */
+#define DCMIPP_PRCR_HSPOL                   DCMIPP_PRCR_HSPOL_Msk                           /*!< Horizontal synchronization polarity */
+#define DCMIPP_PRCR_VSPOL_Pos               (7U)
+#define DCMIPP_PRCR_VSPOL_Msk               (0x1UL << DCMIPP_PRCR_VSPOL_Pos)                 /*!< 0x00000080 */
+#define DCMIPP_PRCR_VSPOL                   DCMIPP_PRCR_VSPOL_Msk                           /*!< Vertical synchronization polarity */
+#define DCMIPP_PRCR_EDM_Pos                 (10U)
+#define DCMIPP_PRCR_EDM_Msk                 (0x7UL << DCMIPP_PRCR_EDM_Pos)                   /*!< 0x00001C00 */
+#define DCMIPP_PRCR_EDM                     DCMIPP_PRCR_EDM_Msk                             /*!< Extended data mode */
+#define DCMIPP_PRCR_ENABLE_Pos              (14U)
+#define DCMIPP_PRCR_ENABLE_Msk              (0x1UL << DCMIPP_PRCR_ENABLE_Pos)                /*!< 0x00004000 */
+#define DCMIPP_PRCR_ENABLE                  DCMIPP_PRCR_ENABLE_Msk                          /*!< Parallel interface enable */
+#define DCMIPP_PRCR_FORMAT_Pos              (16U)
+#define DCMIPP_PRCR_FORMAT_Msk              (0xFFUL << DCMIPP_PRCR_FORMAT_Pos)               /*!< 0x00FF0000 */
+#define DCMIPP_PRCR_FORMAT                  DCMIPP_PRCR_FORMAT_Msk                          /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */
+#define DCMIPP_PRCR_SWAPCYCLES_Pos          (25U)
+#define DCMIPP_PRCR_SWAPCYCLES_Msk          (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos)            /*!< 0x02000000 */
+#define DCMIPP_PRCR_SWAPCYCLES              DCMIPP_PRCR_SWAPCYCLES_Msk                      /*!< Swap data from cycle 0 vs */
+#define DCMIPP_PRCR_SWAPBITS_Pos            (26U)
+#define DCMIPP_PRCR_SWAPBITS_Msk            (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos)              /*!< 0x04000000 */
+#define DCMIPP_PRCR_SWAPBITS                DCMIPP_PRCR_SWAPBITS_Msk                        /*!< Swap LSB vs */
+
+/****************  Bit definition for DCMIPP_PRESCR register  *****************/
+#define DCMIPP_PRESCR_FSC_Pos               (0U)
+#define DCMIPP_PRESCR_FSC_Msk               (0xFFUL << DCMIPP_PRESCR_FSC_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESCR_FSC                   DCMIPP_PRESCR_FSC_Msk                           /*!< Frame start delimiter code */
+#define DCMIPP_PRESCR_LSC_Pos               (8U)
+#define DCMIPP_PRESCR_LSC_Msk               (0xFFUL << DCMIPP_PRESCR_LSC_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESCR_LSC                   DCMIPP_PRESCR_LSC_Msk                           /*!< Line start delimiter code */
+#define DCMIPP_PRESCR_LEC_Pos               (16U)
+#define DCMIPP_PRESCR_LEC_Msk               (0xFFUL << DCMIPP_PRESCR_LEC_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESCR_LEC                   DCMIPP_PRESCR_LEC_Msk                           /*!< Line end delimiter code */
+#define DCMIPP_PRESCR_FEC_Pos               (24U)
+#define DCMIPP_PRESCR_FEC_Msk               (0xFFUL << DCMIPP_PRESCR_FEC_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESCR_FEC                   DCMIPP_PRESCR_FEC_Msk                           /*!< Frame end delimiter code */
+
+/****************  Bit definition for DCMIPP_PRESUR register  *****************/
+#define DCMIPP_PRESUR_FSU_Pos               (0U)
+#define DCMIPP_PRESUR_FSU_Msk               (0xFFUL << DCMIPP_PRESUR_FSU_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESUR_FSU                   DCMIPP_PRESUR_FSU_Msk                           /*!< Frame start delimiter unmask */
+#define DCMIPP_PRESUR_LSU_Pos               (8U)
+#define DCMIPP_PRESUR_LSU_Msk               (0xFFUL << DCMIPP_PRESUR_LSU_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESUR_LSU                   DCMIPP_PRESUR_LSU_Msk                           /*!< Line start delimiter unmask */
+#define DCMIPP_PRESUR_LEU_Pos               (16U)
+#define DCMIPP_PRESUR_LEU_Msk               (0xFFUL << DCMIPP_PRESUR_LEU_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESUR_LEU                   DCMIPP_PRESUR_LEU_Msk                           /*!< Line end delimiter unmask */
+#define DCMIPP_PRESUR_FEU_Pos               (24U)
+#define DCMIPP_PRESUR_FEU_Msk               (0xFFUL << DCMIPP_PRESUR_FEU_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESUR_FEU                   DCMIPP_PRESUR_FEU_Msk                           /*!< Frame end delimiter unmask */
+
+/*****************  Bit definition for DCMIPP_PRIER register  *****************/
+#define DCMIPP_PRIER_ERRIE_Pos              (6U)
+#define DCMIPP_PRIER_ERRIE_Msk              (0x1UL << DCMIPP_PRIER_ERRIE_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRIER_ERRIE                  DCMIPP_PRIER_ERRIE_Msk                          /*!< Synchronization error interrupt enable */
+
+/*****************  Bit definition for DCMIPP_PRSR register  ******************/
+#define DCMIPP_PRSR_ERRF_Pos                (6U)
+#define DCMIPP_PRSR_ERRF_Msk                (0x1UL << DCMIPP_PRSR_ERRF_Pos)                  /*!< 0x00000040 */
+#define DCMIPP_PRSR_ERRF                    DCMIPP_PRSR_ERRF_Msk                            /*!< Synchronization error raw interrupt status */
+#define DCMIPP_PRSR_HSYNC_Pos               (16U)
+#define DCMIPP_PRSR_HSYNC_Msk               (0x1UL << DCMIPP_PRSR_HSYNC_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_PRSR_HSYNC                   DCMIPP_PRSR_HSYNC_Msk                           /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */
+#define DCMIPP_PRSR_VSYNC_Pos               (17U)
+#define DCMIPP_PRSR_VSYNC_Msk               (0x1UL << DCMIPP_PRSR_VSYNC_Pos)                 /*!< 0x00020000 */
+#define DCMIPP_PRSR_VSYNC                   DCMIPP_PRSR_VSYNC_Msk                           /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */
+
+/*****************  Bit definition for DCMIPP_PRFCR register  *****************/
+#define DCMIPP_PRFCR_CERRF_Pos              (6U)
+#define DCMIPP_PRFCR_CERRF_Msk              (0x1UL << DCMIPP_PRFCR_CERRF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRFCR_CERRF                  DCMIPP_PRFCR_CERRF_Msk                          /*!< Synchronization error interrupt status clear */
+
+/*****************  Bit definition for DCMIPP_CMCR register  ******************/
+#define DCMIPP_CMCR_INSEL_Pos               (0U)
+#define DCMIPP_CMCR_INSEL_Msk               (0x1UL << DCMIPP_CMCR_INSEL_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_CMCR_INSEL                   DCMIPP_CMCR_INSEL_Msk                           /*!< input selection */
+#define DCMIPP_CMCR_PSFC_Pos                (1U)
+#define DCMIPP_CMCR_PSFC_Msk                (0x3UL << DCMIPP_CMCR_PSFC_Pos)                  /*!< 0x00000006 */
+#define DCMIPP_CMCR_PSFC                    DCMIPP_CMCR_PSFC_Msk                            /*!< Pipe selection for the frame counter */
+#define DCMIPP_CMCR_CFC_Pos                 (4U)
+#define DCMIPP_CMCR_CFC_Msk                 (0x1UL << DCMIPP_CMCR_CFC_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_CMCR_CFC                     DCMIPP_CMCR_CFC_Msk                             /*!< Clear frame counter */
+#define DCMIPP_CMCR_SWAPRB_Pos              (7U)
+#define DCMIPP_CMCR_SWAPRB_Msk              (0x1UL << DCMIPP_CMCR_SWAPRB_Pos)                /*!< 0x00000080 */
+#define DCMIPP_CMCR_SWAPRB                  DCMIPP_CMCR_SWAPRB_Msk                          /*!< Swap R/U and B/V */
+
+/****************  Bit definition for DCMIPP_CMFRCR register  *****************/
+#define DCMIPP_CMFRCR_FRMCNT_Pos            (0U)
+#define DCMIPP_CMFRCR_FRMCNT_Msk            (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_CMFRCR_FRMCNT                DCMIPP_CMFRCR_FRMCNT_Msk                        /*!< Frame counter, read-only, loops around */
+
+/*****************  Bit definition for DCMIPP_CMIER register  *****************/
+#define DCMIPP_CMIER_ATXERRIE_Pos           (5U)
+#define DCMIPP_CMIER_ATXERRIE_Msk           (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMIER_ATXERRIE               DCMIPP_CMIER_ATXERRIE_Msk                       /*!< AXI Transfer error interrupt enable for IPPLUG */
+#define DCMIPP_CMIER_PRERRIE_Pos            (6U)
+#define DCMIPP_CMIER_PRERRIE_Msk            (0x1UL << DCMIPP_CMIER_PRERRIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMIER_PRERRIE                DCMIPP_CMIER_PRERRIE_Msk                        /*!< limit interrupt enable for the Parallel Interface */
+#define DCMIPP_CMIER_P0LINEIE_Pos           (8U)
+#define DCMIPP_CMIER_P0LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMIER_P0LINEIE               DCMIPP_CMIER_P0LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0FRAMEIE_Pos          (9U)
+#define DCMIPP_CMIER_P0FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMIER_P0FRAMEIE              DCMIPP_CMIER_P0FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0VSYNCIE_Pos          (10U)
+#define DCMIPP_CMIER_P0VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMIER_P0VSYNCIE              DCMIPP_CMIER_P0VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0LIMITIE_Pos          (14U)
+#define DCMIPP_CMIER_P0LIMITIE_Msk          (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMIER_P0LIMITIE              DCMIPP_CMIER_P0LIMITIE_Msk                      /*!< limit interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0OVRIE_Pos            (15U)
+#define DCMIPP_CMIER_P0OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMIER_P0OVRIE                DCMIPP_CMIER_P0OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P1LINEIE_Pos           (16U)
+#define DCMIPP_CMIER_P1LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMIER_P1LINEIE               DCMIPP_CMIER_P1LINEIE_Msk                       /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */
+#define DCMIPP_CMIER_P1FRAMEIE_Pos          (17U)
+#define DCMIPP_CMIER_P1FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMIER_P1FRAMEIE              DCMIPP_CMIER_P1FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1VSYNCIE_Pos          (18U)
+#define DCMIPP_CMIER_P1VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMIER_P1VSYNCIE              DCMIPP_CMIER_P1VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1OVRIE_Pos            (23U)
+#define DCMIPP_CMIER_P1OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMIER_P1OVRIE                DCMIPP_CMIER_P1OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P2LINEIE_Pos           (24U)
+#define DCMIPP_CMIER_P2LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMIER_P2LINEIE               DCMIPP_CMIER_P2LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2FRAMEIE_Pos          (25U)
+#define DCMIPP_CMIER_P2FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMIER_P2FRAMEIE              DCMIPP_CMIER_P2FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2VSYNCIE_Pos          (26U)
+#define DCMIPP_CMIER_P2VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMIER_P2VSYNCIE              DCMIPP_CMIER_P2VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2OVRIE_Pos            (31U)
+#define DCMIPP_CMIER_P2OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMIER_P2OVRIE                DCMIPP_CMIER_P2OVRIE_Msk                        /*!< Overrun interrupt status enable for the Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR1 register  *****************/
+#define DCMIPP_CMSR1_PRHSYNC_Pos            (0U)
+#define DCMIPP_CMSR1_PRHSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos)              /*!< 0x00000001 */
+#define DCMIPP_CMSR1_PRHSYNC                DCMIPP_CMSR1_PRHSYNC_Msk                        /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_PRVSYNC_Pos            (1U)
+#define DCMIPP_CMSR1_PRVSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos)              /*!< 0x00000002 */
+#define DCMIPP_CMSR1_PRVSYNC                DCMIPP_CMSR1_PRVSYNC_Msk                        /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_P0LSTLINE_Pos          (8U)
+#define DCMIPP_CMSR1_P0LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos)            /*!< 0x00000100 */
+#define DCMIPP_CMSR1_P0LSTLINE              DCMIPP_CMSR1_P0LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0LSTFRM_Pos           (9U)
+#define DCMIPP_CMSR1_P0LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR1_P0LSTFRM               DCMIPP_CMSR1_P0LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0CPTACT_Pos           (15U)
+#define DCMIPP_CMSR1_P0CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos)             /*!< 0x00008000 */
+#define DCMIPP_CMSR1_P0CPTACT               DCMIPP_CMSR1_P0CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */
+#define DCMIPP_CMSR1_P1LSTLINE_Pos          (16U)
+#define DCMIPP_CMSR1_P1LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos)            /*!< 0x00010000 */
+#define DCMIPP_CMSR1_P1LSTLINE              DCMIPP_CMSR1_P1LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1LSTFRM_Pos           (17U)
+#define DCMIPP_CMSR1_P1LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR1_P1LSTFRM               DCMIPP_CMSR1_P1LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1CPTACT_Pos           (23U)
+#define DCMIPP_CMSR1_P1CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos)             /*!< 0x00800000 */
+#define DCMIPP_CMSR1_P1CPTACT               DCMIPP_CMSR1_P1CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */
+#define DCMIPP_CMSR1_P2LSTLINE_Pos          (24U)
+#define DCMIPP_CMSR1_P2LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos)            /*!< 0x01000000 */
+#define DCMIPP_CMSR1_P2LSTLINE              DCMIPP_CMSR1_P2LSTLINE_Msk                      /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2LSTFRM_Pos           (25U)
+#define DCMIPP_CMSR1_P2LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR1_P2LSTFRM               DCMIPP_CMSR1_P2LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2CPTACT_Pos           (31U)
+#define DCMIPP_CMSR1_P2CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos)             /*!< 0x80000000 */
+#define DCMIPP_CMSR1_P2CPTACT               DCMIPP_CMSR1_P2CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR2 register  *****************/
+#define DCMIPP_CMSR2_ATXERRF_Pos            (5U)
+#define DCMIPP_CMSR2_ATXERRF_Msk            (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos)              /*!< 0x00000020 */
+#define DCMIPP_CMSR2_ATXERRF                DCMIPP_CMSR2_ATXERRF_Msk                        /*!< AXI transfer error interrupt status flag for the IPPLUG */
+#define DCMIPP_CMSR2_PRERRF_Pos             (6U)
+#define DCMIPP_CMSR2_PRERRF_Msk             (0x1UL << DCMIPP_CMSR2_PRERRF_Pos)               /*!< 0x00000040 */
+#define DCMIPP_CMSR2_PRERRF                 DCMIPP_CMSR2_PRERRF_Msk                         /*!< Synchronization error raw interrupt status for the parallel interface */
+#define DCMIPP_CMSR2_P0LINEF_Pos            (8U)
+#define DCMIPP_CMSR2_P0LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos)              /*!< 0x00000100 */
+#define DCMIPP_CMSR2_P0LINEF                DCMIPP_CMSR2_P0LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0FRAMEF_Pos           (9U)
+#define DCMIPP_CMSR2_P0FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR2_P0FRAMEF               DCMIPP_CMSR2_P0FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0VSYNCF_Pos           (10U)
+#define DCMIPP_CMSR2_P0VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos)             /*!< 0x00000400 */
+#define DCMIPP_CMSR2_P0VSYNCF               DCMIPP_CMSR2_P0VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0LIMITF_Pos           (14U)
+#define DCMIPP_CMSR2_P0LIMITF_Msk           (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos)             /*!< 0x00004000 */
+#define DCMIPP_CMSR2_P0LIMITF               DCMIPP_CMSR2_P0LIMITF_Msk                       /*!< Limit raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0OVRF_Pos             (15U)
+#define DCMIPP_CMSR2_P0OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos)               /*!< 0x00008000 */
+#define DCMIPP_CMSR2_P0OVRF                 DCMIPP_CMSR2_P0OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P1LINEF_Pos            (16U)
+#define DCMIPP_CMSR2_P1LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos)              /*!< 0x00010000 */
+#define DCMIPP_CMSR2_P1LINEF                DCMIPP_CMSR2_P1LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1FRAMEF_Pos           (17U)
+#define DCMIPP_CMSR2_P1FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR2_P1FRAMEF               DCMIPP_CMSR2_P1FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1VSYNCF_Pos           (18U)
+#define DCMIPP_CMSR2_P1VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos)             /*!< 0x00040000 */
+#define DCMIPP_CMSR2_P1VSYNCF               DCMIPP_CMSR2_P1VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1OVRF_Pos             (23U)
+#define DCMIPP_CMSR2_P1OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos)               /*!< 0x00800000 */
+#define DCMIPP_CMSR2_P1OVRF                 DCMIPP_CMSR2_P1OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P2LINEF_Pos            (24U)
+#define DCMIPP_CMSR2_P2LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos)              /*!< 0x01000000 */
+#define DCMIPP_CMSR2_P2LINEF                DCMIPP_CMSR2_P2LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2FRAMEF_Pos           (25U)
+#define DCMIPP_CMSR2_P2FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR2_P2FRAMEF               DCMIPP_CMSR2_P2FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2VSYNCF_Pos           (26U)
+#define DCMIPP_CMSR2_P2VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos)             /*!< 0x04000000 */
+#define DCMIPP_CMSR2_P2VSYNCF               DCMIPP_CMSR2_P2VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2OVRF_Pos             (31U)
+#define DCMIPP_CMSR2_P2OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos)               /*!< 0x80000000 */
+#define DCMIPP_CMSR2_P2OVRF                 DCMIPP_CMSR2_P2OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMFCR register  *****************/
+#define DCMIPP_CMFCR_CATXERRF_Pos           (5U)
+#define DCMIPP_CMFCR_CATXERRF_Msk           (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMFCR_CATXERRF               DCMIPP_CMFCR_CATXERRF_Msk                       /*!< AXI Transfer error interrupt status clear */
+#define DCMIPP_CMFCR_CPRERRF_Pos            (6U)
+#define DCMIPP_CMFCR_CPRERRF_Msk            (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMFCR_CPRERRF                DCMIPP_CMFCR_CPRERRF_Msk                        /*!< Synchronization error interrupt status clear */
+#define DCMIPP_CMFCR_CP0LINEF_Pos           (8U)
+#define DCMIPP_CMFCR_CP0LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMFCR_CP0LINEF               DCMIPP_CMFCR_CP0LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0FRAMEF_Pos          (9U)
+#define DCMIPP_CMFCR_CP0FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMFCR_CP0FRAMEF              DCMIPP_CMFCR_CP0FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0VSYNCF_Pos          (10U)
+#define DCMIPP_CMFCR_CP0VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMFCR_CP0VSYNCF              DCMIPP_CMFCR_CP0VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP0LIMITF_Pos          (14U)
+#define DCMIPP_CMFCR_CP0LIMITF_Msk          (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMFCR_CP0LIMITF              DCMIPP_CMFCR_CP0LIMITF_Msk                      /*!< limit interrupt status clear */
+#define DCMIPP_CMFCR_CP0OVRF_Pos            (15U)
+#define DCMIPP_CMFCR_CP0OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMFCR_CP0OVRF                DCMIPP_CMFCR_CP0OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP1LINEF_Pos           (16U)
+#define DCMIPP_CMFCR_CP1LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMFCR_CP1LINEF               DCMIPP_CMFCR_CP1LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1FRAMEF_Pos          (17U)
+#define DCMIPP_CMFCR_CP1FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMFCR_CP1FRAMEF              DCMIPP_CMFCR_CP1FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1VSYNCF_Pos          (18U)
+#define DCMIPP_CMFCR_CP1VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMFCR_CP1VSYNCF              DCMIPP_CMFCR_CP1VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP1OVRF_Pos            (23U)
+#define DCMIPP_CMFCR_CP1OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMFCR_CP1OVRF                DCMIPP_CMFCR_CP1OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP2LINEF_Pos           (24U)
+#define DCMIPP_CMFCR_CP2LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMFCR_CP2LINEF               DCMIPP_CMFCR_CP2LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2FRAMEF_Pos          (25U)
+#define DCMIPP_CMFCR_CP2FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMFCR_CP2FRAMEF              DCMIPP_CMFCR_CP2FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2VSYNCF_Pos          (26U)
+#define DCMIPP_CMFCR_CP2VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMFCR_CP2VSYNCF              DCMIPP_CMFCR_CP2VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP2OVRF_Pos            (31U)
+#define DCMIPP_CMFCR_CP2OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMFCR_CP2OVRF                DCMIPP_CMFCR_CP2OVRF_Msk                        /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0FSCR register  *****************/
+#define DCMIPP_P0FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P0FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P0FSCR_DTIDA                 DCMIPP_P0FSCR_DTIDA_Msk                         /*!< Data type selection ID A */
+#define DCMIPP_P0FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P0FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P0FSCR_DTIDB                 DCMIPP_P0FSCR_DTIDB_Msk                         /*!< Data type selection ID B */
+#define DCMIPP_P0FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P0FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P0FSCR_DTMODE                DCMIPP_P0FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_VC_Pos                (19U)
+#define DCMIPP_P0FSCR_VC_Msk                (0x3UL << DCMIPP_P0FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P0FSCR_VC                    DCMIPP_P0FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P0FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P0FSCR_PIPEN                 DCMIPP_P0FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P0FCTCR register  ****************/
+#define DCMIPP_P0FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P0FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P0FCTCR_FRATE                DCMIPP_P0FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P0FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P0FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P0FCTCR_CPTMODE              DCMIPP_P0FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P0FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P0FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P0FCTCR_CPTREQ               DCMIPP_P0FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P0SCSTR register  ****************/
+#define DCMIPP_P0SCSTR_HSTART_Pos           (0U)
+#define DCMIPP_P0SCSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0SCSTR_HSTART               DCMIPP_P0SCSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0SCSTR_VSTART_Pos           (16U)
+#define DCMIPP_P0SCSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSTR_VSTART               DCMIPP_P0SCSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P0SCSZR register  ****************/
+#define DCMIPP_P0SCSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P0SCSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P0SCSZR_HSIZE                DCMIPP_P0SCSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0SCSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P0SCSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSZR_VSIZE                DCMIPP_P0SCSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0SCSZR_POSNEG_Pos           (30U)
+#define DCMIPP_P0SCSZR_POSNEG_Msk           (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P0SCSZR_POSNEG               DCMIPP_P0SCSZR_POSNEG_Msk                       /*!< This bit is set and cleared by software */
+#define DCMIPP_P0SCSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P0SCSZR_ENABLE_Msk           (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P0SCSZR_ENABLE               DCMIPP_P0SCSZR_ENABLE_Msk                       /*!< This bit is set and cleared by software */
+
+/***************  Bit definition for DCMIPP_P0DCCNTR register  ****************/
+#define DCMIPP_P0DCCNTR_CNT_Pos             (0U)
+#define DCMIPP_P0DCCNTR_CNT_Msk             (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos)         /*!< 0x03FFFFFF */
+#define DCMIPP_P0DCCNTR_CNT                 DCMIPP_P0DCCNTR_CNT_Msk                         /*!< Number of data dumped during the frame */
+
+/***************  Bit definition for DCMIPP_P0DCLMTR register  ****************/
+#define DCMIPP_P0DCLMTR_LIMIT_Pos           (0U)
+#define DCMIPP_P0DCLMTR_LIMIT_Msk           (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos)        /*!< 0x00FFFFFF */
+#define DCMIPP_P0DCLMTR_LIMIT               DCMIPP_P0DCLMTR_LIMIT_Msk                       /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */
+#define DCMIPP_P0DCLMTR_ENABLE_Pos          (31U)
+#define DCMIPP_P0DCLMTR_ENABLE_Msk          (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0DCLMTR_ENABLE              DCMIPP_P0DCLMTR_ENABLE_Msk                      /*!<  */
+
+/****************  Bit definition for DCMIPP_P0PPCR register  *****************/
+#define DCMIPP_P0PPCR_SWAPYUV_Pos           (0U)
+#define DCMIPP_P0PPCR_SWAPYUV_Msk           (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P0PPCR_SWAPYUV               DCMIPP_P0PPCR_SWAPYUV_Msk                       /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0PPCR_PAD_Pos               (5U)
+#define DCMIPP_P0PPCR_PAD_Msk               (0x1UL << DCMIPP_P0PPCR_PAD_Pos)                 /*!< 0x00000020 */
+#define DCMIPP_P0PPCR_PAD                   DCMIPP_P0PPCR_PAD_Msk                           /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0PPCR_HEADEREN_Pos          (6U)
+#define DCMIPP_P0PPCR_HEADEREN_Msk          (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos)            /*!< 0x00000040 */
+#define DCMIPP_P0PPCR_HEADEREN              DCMIPP_P0PPCR_HEADEREN_Msk                      /*!< CSI header dump enable */
+#define DCMIPP_P0PPCR_BSM_Pos               (7U)
+#define DCMIPP_P0PPCR_BSM_Msk               (0x3UL << DCMIPP_P0PPCR_BSM_Pos)                 /*!< 0x00000180 */
+#define DCMIPP_P0PPCR_BSM                   DCMIPP_P0PPCR_BSM_Msk                           /*!< Byte select mode */
+#define DCMIPP_P0PPCR_OEBS_Pos              (9U)
+#define DCMIPP_P0PPCR_OEBS_Msk              (0x1UL << DCMIPP_P0PPCR_OEBS_Pos)                /*!< 0x00000200 */
+#define DCMIPP_P0PPCR_OEBS                  DCMIPP_P0PPCR_OEBS_Msk                          /*!< Odd/even byte select (byte select start) */
+#define DCMIPP_P0PPCR_LSM_Pos               (10U)
+#define DCMIPP_P0PPCR_LSM_Msk               (0x1UL << DCMIPP_P0PPCR_LSM_Pos)                 /*!< 0x00000400 */
+#define DCMIPP_P0PPCR_LSM                   DCMIPP_P0PPCR_LSM_Msk                           /*!< Line select mode */
+#define DCMIPP_P0PPCR_OELS_Pos              (11U)
+#define DCMIPP_P0PPCR_OELS_Msk              (0x1UL << DCMIPP_P0PPCR_OELS_Pos)                /*!< 0x00000800 */
+#define DCMIPP_P0PPCR_OELS                  DCMIPP_P0PPCR_OELS_Msk                          /*!< Odd/even line select (line select start) */
+#define DCMIPP_P0PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P0PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P0PPCR_LINEMULT              DCMIPP_P0PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0PPCR_DBM_Pos               (16U)
+#define DCMIPP_P0PPCR_DBM_Msk               (0x1UL << DCMIPP_P0PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P0PPCR_DBM                   DCMIPP_P0PPCR_DBM_Msk                           /*!< Double buffer mode */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR1 register  ***************/
+#define DCMIPP_P0PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR1_M0A                DCMIPP_P0PPM0AR1_M0A_Msk                        /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR2 register  ***************/
+#define DCMIPP_P0PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR2_M0A                DCMIPP_P0PPM0AR2_M0A_Msk                        /*!< Memory0 address */
+
+/*****************  Bit definition for DCMIPP_P0IER register  *****************/
+#define DCMIPP_P0IER_LINEIE_Pos             (0U)
+#define DCMIPP_P0IER_LINEIE_Msk             (0x1UL << DCMIPP_P0IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0IER_LINEIE                 DCMIPP_P0IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P0IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P0IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0IER_FRAMEIE                DCMIPP_P0IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P0IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P0IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0IER_VSYNCIE                DCMIPP_P0IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P0IER_LIMITIE_Pos            (6U)
+#define DCMIPP_P0IER_LIMITIE_Msk            (0x1UL << DCMIPP_P0IER_LIMITIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0IER_LIMITIE                DCMIPP_P0IER_LIMITIE_Msk                        /*!< Limit interrupt enable */
+#define DCMIPP_P0IER_OVRIE_Pos              (7U)
+#define DCMIPP_P0IER_OVRIE_Msk              (0x1UL << DCMIPP_P0IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0IER_OVRIE                  DCMIPP_P0IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P0SR register  ******************/
+#define DCMIPP_P0SR_LINEF_Pos               (0U)
+#define DCMIPP_P0SR_LINEF_Msk               (0x1UL << DCMIPP_P0SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P0SR_LINEF                   DCMIPP_P0SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P0SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P0SR_FRAMEF_Msk              (0x1UL << DCMIPP_P0SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P0SR_FRAMEF                  DCMIPP_P0SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P0SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P0SR_VSYNCF_Msk              (0x1UL << DCMIPP_P0SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P0SR_VSYNCF                  DCMIPP_P0SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P0SR_LIMITF_Pos              (6U)
+#define DCMIPP_P0SR_LIMITF_Msk              (0x1UL << DCMIPP_P0SR_LIMITF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_P0SR_LIMITF                  DCMIPP_P0SR_LIMITF_Msk                          /*!< Limit raw interrupt status */
+#define DCMIPP_P0SR_OVRF_Pos                (7U)
+#define DCMIPP_P0SR_OVRF_Msk                (0x1UL << DCMIPP_P0SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P0SR_OVRF                    DCMIPP_P0SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P0SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P0SR_LSTLINE_Msk             (0x1UL << DCMIPP_P0SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P0SR_LSTLINE                 DCMIPP_P0SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P0SR_LSTFRM_Msk              (0x1UL << DCMIPP_P0SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P0SR_LSTFRM                  DCMIPP_P0SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_CPTACT_Pos              (23U)
+#define DCMIPP_P0SR_CPTACT_Msk              (0x1UL << DCMIPP_P0SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P0SR_CPTACT                  DCMIPP_P0SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P0FCR register  *****************/
+#define DCMIPP_P0FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P0FCR_CLINEF_Msk             (0x1UL << DCMIPP_P0FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0FCR_CLINEF                 DCMIPP_P0FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P0FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0FCR_CFRAMEF                DCMIPP_P0FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P0FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0FCR_CVSYNCF                DCMIPP_P0FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P0FCR_CLIMITF_Pos            (6U)
+#define DCMIPP_P0FCR_CLIMITF_Msk            (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0FCR_CLIMITF                DCMIPP_P0FCR_CLIMITF_Msk                        /*!< limit interrupt status clear */
+#define DCMIPP_P0FCR_COVRF_Pos              (7U)
+#define DCMIPP_P0FCR_COVRF_Msk              (0x1UL << DCMIPP_P0FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0FCR_COVRF                  DCMIPP_P0FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0CFSCR register  ****************/
+#define DCMIPP_P0CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P0CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P0CFSCR_DTIDA                DCMIPP_P0CFSCR_DTIDA_Msk                        /*!< Current Data type selection ID A */
+#define DCMIPP_P0CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P0CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P0CFSCR_DTIDB                DCMIPP_P0CFSCR_DTIDB_Msk                        /*!< Current Data type selection ID B */
+#define DCMIPP_P0CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P0CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P0CFSCR_DTMODE               DCMIPP_P0CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P0CFSCR_VC_Pos               (19U)
+#define DCMIPP_P0CFSCR_VC_Msk               (0x3UL << DCMIPP_P0CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P0CFSCR_VC                   DCMIPP_P0CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P0CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P0CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P0CFSCR_PIPEN                DCMIPP_P0CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P0CFCTCR register  ****************/
+#define DCMIPP_P0CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P0CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P0CFCTCR_FRATE               DCMIPP_P0CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P0CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P0CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P0CFCTCR_CPTMODE             DCMIPP_P0CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P0CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P0CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P0CFCTCR_CPTREQ              DCMIPP_P0CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P0CSCSTR register  ****************/
+#define DCMIPP_P0CSCSTR_HSTART_Pos          (0U)
+#define DCMIPP_P0CSCSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSTR_HSTART              DCMIPP_P0CSCSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0CSCSTR_VSTART_Pos          (16U)
+#define DCMIPP_P0CSCSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSTR_VSTART              DCMIPP_P0CSCSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P0CSCSZR register  ****************/
+#define DCMIPP_P0CSCSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P0CSCSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSZR_HSIZE               DCMIPP_P0CSCSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0CSCSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P0CSCSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSZR_VSIZE               DCMIPP_P0CSCSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0CSCSZR_POSNEG_Pos          (30U)
+#define DCMIPP_P0CSCSZR_POSNEG_Msk          (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos)            /*!< 0x40000000 */
+#define DCMIPP_P0CSCSZR_POSNEG              DCMIPP_P0CSCSZR_POSNEG_Msk                      /*!< Current value of the POSNEG bit */
+#define DCMIPP_P0CSCSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P0CSCSZR_ENABLE_Msk          (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0CSCSZR_ENABLE              DCMIPP_P0CSCSZR_ENABLE_Msk                      /*!< Current value of the ENABLE bit */
+
+/****************  Bit definition for DCMIPP_P0CPPCR register  ****************/
+#define DCMIPP_P0CPPCR_SWAPYUV_Pos          (0U)
+#define DCMIPP_P0CPPCR_SWAPYUV_Msk          (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P0CPPCR_SWAPYUV              DCMIPP_P0CPPCR_SWAPYUV_Msk                      /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0CPPCR_PAD_Pos              (5U)
+#define DCMIPP_P0CPPCR_PAD_Msk              (0x1UL << DCMIPP_P0CPPCR_PAD_Pos)                /*!< 0x00000020 */
+#define DCMIPP_P0CPPCR_PAD                  DCMIPP_P0CPPCR_PAD_Msk                          /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0CPPCR_HEADEREN_Pos         (6U)
+#define DCMIPP_P0CPPCR_HEADEREN_Msk         (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos)           /*!< 0x00000040 */
+#define DCMIPP_P0CPPCR_HEADEREN             DCMIPP_P0CPPCR_HEADEREN_Msk                     /*!< Current CSI header dump enable */
+#define DCMIPP_P0CPPCR_BSM_Pos              (7U)
+#define DCMIPP_P0CPPCR_BSM_Msk              (0x3UL << DCMIPP_P0CPPCR_BSM_Pos)                /*!< 0x00000180 */
+#define DCMIPP_P0CPPCR_BSM                  DCMIPP_P0CPPCR_BSM_Msk                          /*!< Current Byte select mode */
+#define DCMIPP_P0CPPCR_OEBS_Pos             (9U)
+#define DCMIPP_P0CPPCR_OEBS_Msk             (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos)               /*!< 0x00000200 */
+#define DCMIPP_P0CPPCR_OEBS                 DCMIPP_P0CPPCR_OEBS_Msk                         /*!< Current odd/even byte select (Byte select start) */
+#define DCMIPP_P0CPPCR_LSM_Pos              (10U)
+#define DCMIPP_P0CPPCR_LSM_Msk              (0x1UL << DCMIPP_P0CPPCR_LSM_Pos)                /*!< 0x00000400 */
+#define DCMIPP_P0CPPCR_LSM                  DCMIPP_P0CPPCR_LSM_Msk                          /*!< Current Line select mode */
+#define DCMIPP_P0CPPCR_OELS_Pos             (11U)
+#define DCMIPP_P0CPPCR_OELS_Msk             (0x1UL << DCMIPP_P0CPPCR_OELS_Pos)               /*!< 0x00000800 */
+#define DCMIPP_P0CPPCR_OELS                 DCMIPP_P0CPPCR_OELS_Msk                         /*!< Current odd/even line select (Line select start) */
+#define DCMIPP_P0CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P0CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P0CPPCR_LINEMULT             DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Current amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P0CPPCR_DBM_Msk              (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P0CPPCR_DBM                  DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Double buffer mode */
+
+/**************  Bit definition for DCMIPP_P0CPPM0AR1 register  ***************/
+#define DCMIPP_P0CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P0CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P0CPPM0AR1_M0A               DCMIPP_P0CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/****************  Bit definition for DCMIPP_P1FSCR register  *****************/
+#define DCMIPP_P1FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P1FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P1FSCR_DTIDA                 DCMIPP_P1FSCR_DTIDA_Msk                         /*!< Data type ID A */
+#define DCMIPP_P1FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P1FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P1FSCR_DTIDB                 DCMIPP_P1FSCR_DTIDB_Msk                         /*!< Data type ID B */
+#define DCMIPP_P1FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P1FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P1FSCR_DTMODE                DCMIPP_P1FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_PIPEDIFF_Pos          (18U)
+#define DCMIPP_P1FSCR_PIPEDIFF_Msk          (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_P1FSCR_PIPEDIFF              DCMIPP_P1FSCR_PIPEDIFF_Msk                      /*!< Differentiates Pipe2 vs */
+#define DCMIPP_P1FSCR_VC_Pos                (19U)
+#define DCMIPP_P1FSCR_VC_Msk                (0x3UL << DCMIPP_P1FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P1FSCR_VC                    DCMIPP_P1FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P1FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P1FSCR_FDTF                  DCMIPP_P1FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P1FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P1FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P1FSCR_FDTFEN                DCMIPP_P1FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P1FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P1FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P1FSCR_PIPEN                 DCMIPP_P1FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P1SRCR register  *****************/
+#define DCMIPP_P1SRCR_LASTLINE_Pos          (0U)
+#define DCMIPP_P1SRCR_LASTLINE_Msk          (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1SRCR_LASTLINE              DCMIPP_P1SRCR_LASTLINE_Msk                      /*!< Number of the last line to be kept when CROPEN = 1 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos      (12U)
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk      (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos)        /*!< 0x00007000 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL          DCMIPP_P1SRCR_FIRSTLINEDEL_Msk                  /*!< Number of lines to be deleted when CROPEN = 1 */
+#define DCMIPP_P1SRCR_CROPEN_Pos            (15U)
+#define DCMIPP_P1SRCR_CROPEN_Msk            (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos)              /*!< 0x00008000 */
+#define DCMIPP_P1SRCR_CROPEN                DCMIPP_P1SRCR_CROPEN_Msk                        /*!< Crop line enable */
+
+/****************  Bit definition for DCMIPP_P1BPRCR register  ****************/
+#define DCMIPP_P1BPRCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BPRCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BPRCR_ENABLE               DCMIPP_P1BPRCR_ENABLE_Msk                       /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */
+#define DCMIPP_P1BPRCR_STRENGTH_Pos         (1U)
+#define DCMIPP_P1BPRCR_STRENGTH_Msk         (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos)           /*!< 0x0000000E */
+#define DCMIPP_P1BPRCR_STRENGTH             DCMIPP_P1BPRCR_STRENGTH_Msk                     /*!< Strength (aggressivity) of the bad pixel detection: */
+
+/****************  Bit definition for DCMIPP_P1BPRSR register  ****************/
+#define DCMIPP_P1BPRSR_BADCNT_Pos           (0U)
+#define DCMIPP_P1BPRSR_BADCNT_Msk           (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1BPRSR_BADCNT               DCMIPP_P1BPRSR_BADCNT_Msk                       /*!< Amount of detected bad pixels */
+
+/****************  Bit definition for DCMIPP_P1DECR register  *****************/
+#define DCMIPP_P1DECR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DECR_ENABLE_Msk            (0x1UL << DCMIPP_P1DECR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DECR_ENABLE                DCMIPP_P1DECR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DECR_HDEC_Pos              (1U)
+#define DCMIPP_P1DECR_HDEC_Msk              (0x3UL << DCMIPP_P1DECR_HDEC_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DECR_HDEC                  DCMIPP_P1DECR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DECR_VDEC_Pos              (3U)
+#define DCMIPP_P1DECR_VDEC_Msk              (0x3UL << DCMIPP_P1DECR_VDEC_Pos)                /*!< 0x00000018 */
+#define DCMIPP_P1DECR_VDEC                  DCMIPP_P1DECR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1BLCCR register  ****************/
+#define DCMIPP_P1BLCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BLCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BLCCR_ENABLE               DCMIPP_P1BLCCR_ENABLE_Msk                       /*!< Black level calibration */
+#define DCMIPP_P1BLCCR_BLCB_Pos             (8U)
+#define DCMIPP_P1BLCCR_BLCB_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos)              /*!< 0x0000FF00 */
+#define DCMIPP_P1BLCCR_BLCB                 DCMIPP_P1BLCCR_BLCB_Msk                         /*!< Black level calibration - Blue */
+#define DCMIPP_P1BLCCR_BLCG_Pos             (16U)
+#define DCMIPP_P1BLCCR_BLCG_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos)              /*!< 0x00FF0000 */
+#define DCMIPP_P1BLCCR_BLCG                 DCMIPP_P1BLCCR_BLCG_Msk                         /*!< Black level calibration - Green */
+#define DCMIPP_P1BLCCR_BLCR_Pos             (24U)
+#define DCMIPP_P1BLCCR_BLCR_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos)              /*!< 0xFF000000 */
+#define DCMIPP_P1BLCCR_BLCR                 DCMIPP_P1BLCCR_BLCR_Msk                         /*!< Black level calibration - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR1 register  ****************/
+#define DCMIPP_P1EXCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1EXCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1EXCR1_ENABLE               DCMIPP_P1EXCR1_ENABLE_Msk                       /*!< Exposure control (multiplication and shift) of all red, green and blue */
+#define DCMIPP_P1EXCR1_MULTR_Pos            (20U)
+#define DCMIPP_P1EXCR1_MULTR_Msk            (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR1_MULTR                DCMIPP_P1EXCR1_MULTR_Msk                        /*!< Exposure multiplier - Red */
+#define DCMIPP_P1EXCR1_SHFR_Pos             (28U)
+#define DCMIPP_P1EXCR1_SHFR_Msk             (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR1_SHFR                 DCMIPP_P1EXCR1_SHFR_Msk                         /*!< Exposure shift - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR2 register  ****************/
+#define DCMIPP_P1EXCR2_MULTB_Pos            (4U)
+#define DCMIPP_P1EXCR2_MULTB_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos)             /*!< 0x00000FF0 */
+#define DCMIPP_P1EXCR2_MULTB                DCMIPP_P1EXCR2_MULTB_Msk                        /*!< Exposure multiplier - Blue */
+#define DCMIPP_P1EXCR2_SHFB_Pos             (12U)
+#define DCMIPP_P1EXCR2_SHFB_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos)               /*!< 0x00007000 */
+#define DCMIPP_P1EXCR2_SHFB                 DCMIPP_P1EXCR2_SHFB_Msk                         /*!< Exposure shift - Blue */
+#define DCMIPP_P1EXCR2_MULTG_Pos            (20U)
+#define DCMIPP_P1EXCR2_MULTG_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR2_MULTG                DCMIPP_P1EXCR2_MULTG_Msk                        /*!< Exposure multiplier - Green */
+#define DCMIPP_P1EXCR2_SHFG_Pos             (28U)
+#define DCMIPP_P1EXCR2_SHFG_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR2_SHFG                 DCMIPP_P1EXCR2_SHFG_Msk                         /*!< Exposure shift - Green */
+
+/****************  Bit definition for DCMIPP_P1ST1CR register  ****************/
+#define DCMIPP_P1ST1CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST1CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST1CR_ENABLE               DCMIPP_P1ST1CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST1CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST1CR_BINS_Msk             (0x3UL << DCMIPP_P1ST1CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST1CR_BINS                 DCMIPP_P1ST1CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST1CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST1CR_SRC_Msk              (0x7UL << DCMIPP_P1ST1CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST1CR_SRC                  DCMIPP_P1ST1CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST1CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST1CR_MODE_Msk             (0x1UL << DCMIPP_P1ST1CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST1CR_MODE                 DCMIPP_P1ST1CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST2CR register  ****************/
+#define DCMIPP_P1ST2CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST2CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST2CR_ENABLE               DCMIPP_P1ST2CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST2CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST2CR_BINS_Msk             (0x3UL << DCMIPP_P1ST2CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST2CR_BINS                 DCMIPP_P1ST2CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST2CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST2CR_SRC_Msk              (0x7UL << DCMIPP_P1ST2CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST2CR_SRC                  DCMIPP_P1ST2CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST2CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST2CR_MODE_Msk             (0x1UL << DCMIPP_P1ST2CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST2CR_MODE                 DCMIPP_P1ST2CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST3CR register  ****************/
+#define DCMIPP_P1ST3CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST3CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST3CR_ENABLE               DCMIPP_P1ST3CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST3CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST3CR_BINS_Msk             (0x3UL << DCMIPP_P1ST3CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST3CR_BINS                 DCMIPP_P1ST3CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST3CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST3CR_SRC_Msk              (0x7UL << DCMIPP_P1ST3CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST3CR_SRC                  DCMIPP_P1ST3CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST3CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST3CR_MODE_Msk             (0x1UL << DCMIPP_P1ST3CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST3CR_MODE                 DCMIPP_P1ST3CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1STSTR register  ****************/
+#define DCMIPP_P1STSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1STSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1STSTR_HSTART               DCMIPP_P1STSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1STSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSTR_VSTART               DCMIPP_P1STSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1STSZR register  ****************/
+#define DCMIPP_P1STSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1STSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1STSZR_HSIZE                DCMIPP_P1STSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1STSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSZR_VSIZE                DCMIPP_P1STSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1STSZR_CROPEN_Pos           (31U)
+#define DCMIPP_P1STSZR_CROPEN_Msk           (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1STSZR_CROPEN               DCMIPP_P1STSZR_CROPEN_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1ST1SR register  ****************/
+#define DCMIPP_P1ST1SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST1SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST1SR_ACCU                 DCMIPP_P1ST1SR_ACCU_Msk                         /*!< Accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST2SR register  ****************/
+#define DCMIPP_P1ST2SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST2SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST2SR_ACCU                 DCMIPP_P1ST2SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST3SR register  ****************/
+#define DCMIPP_P1ST3SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST3SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST3SR_ACCU                 DCMIPP_P1ST3SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1DMCR register  *****************/
+#define DCMIPP_P1DMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DMCR_ENABLE                DCMIPP_P1DMCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DMCR_TYPE_Pos              (1U)
+#define DCMIPP_P1DMCR_TYPE_Msk              (0x3UL << DCMIPP_P1DMCR_TYPE_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DMCR_TYPE                  DCMIPP_P1DMCR_TYPE_Msk                          /*!< Raw Bayer type */
+#define DCMIPP_P1DMCR_PEAK_Pos              (16U)
+#define DCMIPP_P1DMCR_PEAK_Msk              (0x7UL << DCMIPP_P1DMCR_PEAK_Pos)                /*!< 0x00070000 */
+#define DCMIPP_P1DMCR_PEAK                  DCMIPP_P1DMCR_PEAK_Msk                          /*!< Strength of the peak detection */
+#define DCMIPP_P1DMCR_LINEV_Pos             (20U)
+#define DCMIPP_P1DMCR_LINEV_Msk             (0x7UL << DCMIPP_P1DMCR_LINEV_Pos)               /*!< 0x00700000 */
+#define DCMIPP_P1DMCR_LINEV                 DCMIPP_P1DMCR_LINEV_Msk                         /*!< Strength of the vertical line detection */
+#define DCMIPP_P1DMCR_LINEH_Pos             (24U)
+#define DCMIPP_P1DMCR_LINEH_Msk             (0x7UL << DCMIPP_P1DMCR_LINEH_Pos)               /*!< 0x07000000 */
+#define DCMIPP_P1DMCR_LINEH                 DCMIPP_P1DMCR_LINEH_Msk                         /*!< Strength of the horizontal line detection */
+#define DCMIPP_P1DMCR_EDGE_Pos              (28U)
+#define DCMIPP_P1DMCR_EDGE_Msk              (0x7UL << DCMIPP_P1DMCR_EDGE_Pos)                /*!< 0x70000000 */
+#define DCMIPP_P1DMCR_EDGE                  DCMIPP_P1DMCR_EDGE_Msk                          /*!< Strength of the edge detection */
+
+/****************  Bit definition for DCMIPP_P1CCCR register  *****************/
+#define DCMIPP_P1CCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1CCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1CCCR_ENABLE                DCMIPP_P1CCCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1CCCR_TYPE_Pos              (1U)
+#define DCMIPP_P1CCCR_TYPE_Msk              (0x1UL << DCMIPP_P1CCCR_TYPE_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1CCCR_TYPE                  DCMIPP_P1CCCR_TYPE_Msk                          /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCR_CLAMP_Pos             (2U)
+#define DCMIPP_P1CCCR_CLAMP_Msk             (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos)               /*!< 0x00000004 */
+#define DCMIPP_P1CCCR_CLAMP                 DCMIPP_P1CCCR_CLAMP_Msk                         /*!< Clamp the output samples */
+
+/****************  Bit definition for DCMIPP_P1CCRR1 register  ****************/
+#define DCMIPP_P1CCRR1_RR_Pos               (0U)
+#define DCMIPP_P1CCRR1_RR_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR1_RR                   DCMIPP_P1CCRR1_RR_Msk                           /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCRR1_RG_Pos               (16U)
+#define DCMIPP_P1CCRR1_RG_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCRR1_RG                   DCMIPP_P1CCRR1_RG_Msk                           /*!< Coefficient row 1 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCRR2 register  ****************/
+#define DCMIPP_P1CCRR2_RB_Pos               (0U)
+#define DCMIPP_P1CCRR2_RB_Msk               (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR2_RB                   DCMIPP_P1CCRR2_RB_Msk                           /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCRR2_RA_Pos               (16U)
+#define DCMIPP_P1CCRR2_RA_Msk               (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCRR2_RA                   DCMIPP_P1CCRR2_RA_Msk                           /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCGR1 register  ****************/
+#define DCMIPP_P1CCGR1_GR_Pos               (0U)
+#define DCMIPP_P1CCGR1_GR_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR1_GR                   DCMIPP_P1CCGR1_GR_Msk                           /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCGR1_GG_Pos               (16U)
+#define DCMIPP_P1CCGR1_GG_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCGR1_GG                   DCMIPP_P1CCGR1_GG_Msk                           /*!< Coefficient row 2 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCGR2 register  ****************/
+#define DCMIPP_P1CCGR2_GB_Pos               (0U)
+#define DCMIPP_P1CCGR2_GB_Msk               (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR2_GB                   DCMIPP_P1CCGR2_GB_Msk                           /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCGR2_GA_Pos               (16U)
+#define DCMIPP_P1CCGR2_GA_Msk               (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCGR2_GA                   DCMIPP_P1CCGR2_GA_Msk                           /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCBR1 register  ****************/
+#define DCMIPP_P1CCBR1_BR_Pos               (0U)
+#define DCMIPP_P1CCBR1_BR_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR1_BR                   DCMIPP_P1CCBR1_BR_Msk                           /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCBR1_BG_Pos               (16U)
+#define DCMIPP_P1CCBR1_BG_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCBR1_BG                   DCMIPP_P1CCBR1_BG_Msk                           /*!< Coefficient row 3 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCBR2 register  ****************/
+#define DCMIPP_P1CCBR2_BB_Pos               (0U)
+#define DCMIPP_P1CCBR2_BB_Msk               (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR2_BB                   DCMIPP_P1CCBR2_BB_Msk                           /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCBR2_BA_Pos               (16U)
+#define DCMIPP_P1CCBR2_BA_Msk               (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCBR2_BA                   DCMIPP_P1CCBR2_BA_Msk                           /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CTCR1 register  ****************/
+#define DCMIPP_P1CTCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1CTCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CTCR1_ENABLE               DCMIPP_P1CTCR1_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1CTCR1_LUM0_Pos             (9U)
+#define DCMIPP_P1CTCR1_LUM0_Msk             (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR1_LUM0                 DCMIPP_P1CTCR1_LUM0_Msk                         /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR2 register  ****************/
+#define DCMIPP_P1CTCR2_LUM4_Pos             (1U)
+#define DCMIPP_P1CTCR2_LUM4_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR2_LUM4                 DCMIPP_P1CTCR2_LUM4_Msk                         /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM3_Pos             (9U)
+#define DCMIPP_P1CTCR2_LUM3_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR2_LUM3                 DCMIPP_P1CTCR2_LUM3_Msk                         /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM2_Pos             (17U)
+#define DCMIPP_P1CTCR2_LUM2_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR2_LUM2                 DCMIPP_P1CTCR2_LUM2_Msk                         /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM1_Pos             (25U)
+#define DCMIPP_P1CTCR2_LUM1_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR2_LUM1                 DCMIPP_P1CTCR2_LUM1_Msk                         /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR3 register  ****************/
+#define DCMIPP_P1CTCR3_LUM8_Pos             (1U)
+#define DCMIPP_P1CTCR3_LUM8_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR3_LUM8                 DCMIPP_P1CTCR3_LUM8_Msk                         /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM7_Pos             (9U)
+#define DCMIPP_P1CTCR3_LUM7_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR3_LUM7                 DCMIPP_P1CTCR3_LUM7_Msk                         /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM6_Pos             (17U)
+#define DCMIPP_P1CTCR3_LUM6_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR3_LUM6                 DCMIPP_P1CTCR3_LUM6_Msk                         /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM5_Pos             (25U)
+#define DCMIPP_P1CTCR3_LUM5_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR3_LUM5                 DCMIPP_P1CTCR3_LUM5_Msk                         /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1FCTCR register  ****************/
+#define DCMIPP_P1FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P1FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P1FCTCR_FRATE                DCMIPP_P1FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P1FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P1FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P1FCTCR_CPTMODE              DCMIPP_P1FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P1FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P1FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P1FCTCR_CPTREQ               DCMIPP_P1FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P1CRSTR register  ****************/
+#define DCMIPP_P1CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CRSTR_HSTART               DCMIPP_P1CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSTR_VSTART               DCMIPP_P1CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CRSZR register  ****************/
+#define DCMIPP_P1CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1CRSZR_HSIZE                DCMIPP_P1CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSZR_VSIZE                DCMIPP_P1CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CRSZR_ENABLE               DCMIPP_P1CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1DCCR register  *****************/
+#define DCMIPP_P1DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1DCCR_ENABLE                DCMIPP_P1DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P1DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P1DCCR_HDEC_Msk              (0x3UL << DCMIPP_P1DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1DCCR_HDEC                  DCMIPP_P1DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P1DCCR_VDEC_Msk              (0x3UL << DCMIPP_P1DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1DCCR_VDEC                  DCMIPP_P1DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1DSCR register  *****************/
+#define DCMIPP_P1DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P1DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P1DSCR_HDIV                  DCMIPP_P1DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P1DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1DSCR_VDIV                  DCMIPP_P1DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P1DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1DSCR_ENABLE                DCMIPP_P1DSCR_ENABLE_Msk                        /*!<  Downscaler Enable */
+
+/***************  Bit definition for DCMIPP_P1DSRTIOR register  ***************/
+#define DCMIPP_P1DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P1DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P1DSRTIOR_HRATIO             DCMIPP_P1DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P1DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P1DSRTIOR_VRATIO             DCMIPP_P1DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P1DSSZR register  ****************/
+#define DCMIPP_P1DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1DSSZR_HSIZE                DCMIPP_P1DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1DSSZR_VSIZE                DCMIPP_P1DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CMRICR register  ***************/
+#define DCMIPP_P1CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P1CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P1CMRICR_ROILSZ              DCMIPP_P1CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P1CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P1CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P1CMRICR_ROI1EN              DCMIPP_P1CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P1CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P1CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P1CMRICR_ROI2EN              DCMIPP_P1CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P1CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P1CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CMRICR_ROI3EN              DCMIPP_P1CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P1CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P1CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P1CMRICR_ROI4EN              DCMIPP_P1CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P1CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P1CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P1CMRICR_ROI5EN              DCMIPP_P1CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P1CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P1CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P1CMRICR_ROI6EN              DCMIPP_P1CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P1CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P1CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P1CMRICR_ROI7EN              DCMIPP_P1CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P1CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P1CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P1CMRICR_ROI8EN              DCMIPP_P1CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P1RIxCR1 register  ***************/
+#define DCMIPP_P1RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P1RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P1RIxCR1_HSTART              DCMIPP_P1RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P1RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P1RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P1RIxCR1_CLB                 DCMIPP_P1RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P1RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P1RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P1RIxCR1_CLG                 DCMIPP_P1RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P1RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P1RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P1RIxCR1_VSTART              DCMIPP_P1RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P1RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P1RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P1RIxCR1_CLR                 DCMIPP_P1RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P1RIxCR2 register  ***************/
+#define DCMIPP_P1RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P1RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P1RIxCR2_VSIZE               DCMIPP_P1RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P1RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P1RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P1RIxCR2_HSIZE               DCMIPP_P1RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P1GMCR register  *****************/
+#define DCMIPP_P1GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos)              /*!< 0x00000001   */
+#define DCMIPP_P1GMCR_ENABLE                DCMIPP_P1GMCR_ENABLE_Msk                        /*!<  Gamma  enable*/
+
+/****************  Bit definition for DCMIPP_P1YUVCR register  ****************/
+#define DCMIPP_P1YUVCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1YUVCR_ENABLE_Msk           (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1YUVCR_ENABLE               DCMIPP_P1YUVCR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1YUVCR_TYPE_Pos             (1U)
+#define DCMIPP_P1YUVCR_TYPE_Msk             (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1YUVCR_TYPE                 DCMIPP_P1YUVCR_TYPE_Msk                         /*!< Output samples type used while CLAMP is activated */
+#define DCMIPP_P1YUVCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1YUVCR_CLAMP_Msk            (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1YUVCR_CLAMP                DCMIPP_P1YUVCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1YUVRR1 register  ****************/
+#define DCMIPP_P1YUVRR1_RR_Pos              (0U)
+#define DCMIPP_P1YUVRR1_RR_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR1_RR                  DCMIPP_P1YUVRR1_RR_Msk                          /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1YUVRR1_RG_Pos              (16U)
+#define DCMIPP_P1YUVRR1_RG_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVRR1_RG                  DCMIPP_P1YUVRR1_RG_Msk                          /*!< Coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVRR2 register  ****************/
+#define DCMIPP_P1YUVRR2_RB_Pos              (0U)
+#define DCMIPP_P1YUVRR2_RB_Msk              (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR2_RB                  DCMIPP_P1YUVRR2_RB_Msk                          /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1YUVRR2_RA_Pos              (16U)
+#define DCMIPP_P1YUVRR2_RA_Msk              (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVRR2_RA                  DCMIPP_P1YUVRR2_RA_Msk                          /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVGR1 register  ****************/
+#define DCMIPP_P1YUVGR1_GR_Pos              (0U)
+#define DCMIPP_P1YUVGR1_GR_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR1_GR                  DCMIPP_P1YUVGR1_GR_Msk                          /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1YUVGR1_GG_Pos              (16U)
+#define DCMIPP_P1YUVGR1_GG_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVGR1_GG                  DCMIPP_P1YUVGR1_GG_Msk                          /*!< Coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVGR2 register  ****************/
+#define DCMIPP_P1YUVGR2_GB_Pos              (0U)
+#define DCMIPP_P1YUVGR2_GB_Msk              (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR2_GB                  DCMIPP_P1YUVGR2_GB_Msk                          /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1YUVGR2_GA_Pos              (16U)
+#define DCMIPP_P1YUVGR2_GA_Msk              (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVGR2_GA                  DCMIPP_P1YUVGR2_GA_Msk                          /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVBR1 register  ****************/
+#define DCMIPP_P1YUVBR1_BR_Pos              (0U)
+#define DCMIPP_P1YUVBR1_BR_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR1_BR                  DCMIPP_P1YUVBR1_BR_Msk                          /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1YUVBR1_BG_Pos              (16U)
+#define DCMIPP_P1YUVBR1_BG_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVBR1_BG                  DCMIPP_P1YUVBR1_BG_Msk                          /*!< Coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVBR2 register  ****************/
+#define DCMIPP_P1YUVBR2_BB_Pos              (0U)
+#define DCMIPP_P1YUVBR2_BB_Msk              (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR2_BB                  DCMIPP_P1YUVBR2_BB_Msk                          /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1YUVBR2_BA_Pos              (16U)
+#define DCMIPP_P1YUVBR2_BA_Msk              (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVBR2_BA                  DCMIPP_P1YUVBR2_BA_Msk                          /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1PPCR register  *****************/
+#define DCMIPP_P1PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P1PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P1PPCR_FORMAT                DCMIPP_P1PPCR_FORMAT_Msk                        /*!< Memory format */
+#define DCMIPP_P1PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P1PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P1PPCR_SWAPRB                DCMIPP_P1PPCR_SWAPRB_Msk                        /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P1PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P1PPCR_LINEMULT              DCMIPP_P1PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P1PPCR_DBM_Pos               (16U)
+#define DCMIPP_P1PPCR_DBM_Msk               (0x1UL << DCMIPP_P1PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P1PPCR_DBM                   DCMIPP_P1PPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P1PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P1PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos)                /*!< 0x000E0000 */
+#define DCMIPP_P1PPCR_LMAWM                 DCMIPP_P1PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P1PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P1PPCR_LMAWE_Msk             (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos)                /*!< 0x00100000 */
+#define DCMIPP_P1PPCR_LMAWE                 DCMIPP_P1PPCR_LMAWE_Msk                           /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P1PPM0AR1 register  ***************/
+#define DCMIPP_P1PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR1_M0A                DCMIPP_P1PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM0AR2 register  ***************/
+#define DCMIPP_P1PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR2_M0A                DCMIPP_P1PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1PPM0PR register  ****************/
+#define DCMIPP_P1PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM0PR_PITCH               DCMIPP_P1PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR1 register  ***************/
+#define DCMIPP_P1PPM1AR1_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR1_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR1_M1A                DCMIPP_P1PPM1AR1_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR2 register  ***************/
+#define DCMIPP_P1PPM1AR2_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR2_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR2_M1A                DCMIPP_P1PPM1AR2_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1PR register  ****************/
+#define DCMIPP_P1PPM1PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM1PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM1PR_PITCH               DCMIPP_P1PPM1PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1STM1AR register  ****************/
+#define DCMIPP_P1STM1AR_M1A_Pos             (0U)
+#define DCMIPP_P1STM1AR_M1A_Msk             (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM1AR_M1A                 DCMIPP_P1STM1AR_M1A_Msk                         /*!< status Memory1 address register */
+
+/***************  Bit definition for DCMIPP_P1PPM2AR1 register  ***************/
+#define DCMIPP_P1PPM2AR1_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR1_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR1_M2A                DCMIPP_P1PPM2AR1_M2A_Msk                        /*!< Memory2 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM2AR2 register  ***************/
+#define DCMIPP_P1PPM2AR2_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR2_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR2_M2A                DCMIPP_P1PPM2AR2_M2A_Msk                        /*!< Memory2 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1STM2AR register  ****************/
+#define DCMIPP_P1STM2AR_M2A_Pos             (0U)
+#define DCMIPP_P1STM2AR_M2A_Msk             (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM2AR_M2A                 DCMIPP_P1STM2AR_M2A_Msk                         /*!< status Memory2 address register */
+
+/*****************  Bit definition for DCMIPP_P1IER register  *****************/
+#define DCMIPP_P1IER_LINEIE_Pos             (0U)
+#define DCMIPP_P1IER_LINEIE_Msk             (0x1UL << DCMIPP_P1IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1IER_LINEIE                 DCMIPP_P1IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P1IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P1IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1IER_FRAMEIE                DCMIPP_P1IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P1IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P1IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1IER_VSYNCIE                DCMIPP_P1IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P1IER_OVRIE_Pos              (7U)
+#define DCMIPP_P1IER_OVRIE_Msk              (0x1UL << DCMIPP_P1IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1IER_OVRIE                  DCMIPP_P1IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P1SR register  ******************/
+#define DCMIPP_P1SR_LINEF_Pos               (0U)
+#define DCMIPP_P1SR_LINEF_Msk               (0x1UL << DCMIPP_P1SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P1SR_LINEF                   DCMIPP_P1SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P1SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P1SR_FRAMEF_Msk              (0x1UL << DCMIPP_P1SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1SR_FRAMEF                  DCMIPP_P1SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P1SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P1SR_VSYNCF_Msk              (0x1UL << DCMIPP_P1SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P1SR_VSYNCF                  DCMIPP_P1SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P1SR_OVRF_Pos                (7U)
+#define DCMIPP_P1SR_OVRF_Msk                (0x1UL << DCMIPP_P1SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P1SR_OVRF                    DCMIPP_P1SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P1SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P1SR_LSTLINE_Msk             (0x1UL << DCMIPP_P1SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P1SR_LSTLINE                 DCMIPP_P1SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P1SR_LSTFRM_Msk              (0x1UL << DCMIPP_P1SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P1SR_LSTFRM                  DCMIPP_P1SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_CPTACT_Pos              (23U)
+#define DCMIPP_P1SR_CPTACT_Msk              (0x1UL << DCMIPP_P1SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P1SR_CPTACT                  DCMIPP_P1SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P1FCR register  *****************/
+#define DCMIPP_P1FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P1FCR_CLINEF_Msk             (0x1UL << DCMIPP_P1FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1FCR_CLINEF                 DCMIPP_P1FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P1FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1FCR_CFRAMEF                DCMIPP_P1FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P1FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1FCR_CVSYNCF                DCMIPP_P1FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P1FCR_COVRF_Pos              (7U)
+#define DCMIPP_P1FCR_COVRF_Msk              (0x1UL << DCMIPP_P1FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1FCR_COVRF                  DCMIPP_P1FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P1CFSCR register  ****************/
+#define DCMIPP_P1CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P1CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P1CFSCR_DTIDA                DCMIPP_P1CFSCR_DTIDA_Msk                        /*!< Current Data type ID A */
+#define DCMIPP_P1CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P1CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P1CFSCR_DTIDB                DCMIPP_P1CFSCR_DTIDB_Msk                        /*!< Current Data type ID B */
+#define DCMIPP_P1CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P1CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P1CFSCR_DTMODE               DCMIPP_P1CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P1CFSCR_PIPEDIFF_Pos         (18U)
+#define DCMIPP_P1CFSCR_PIPEDIFF_Msk         (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CFSCR_PIPEDIFF             DCMIPP_P1CFSCR_PIPEDIFF_Msk                     /*!< Current differentiates Pipe2 vs */
+#define DCMIPP_P1CFSCR_VC_Pos               (19U)
+#define DCMIPP_P1CFSCR_VC_Msk               (0x3UL << DCMIPP_P1CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P1CFSCR_VC                   DCMIPP_P1CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P1CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P1CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P1CFSCR_FDTF                 DCMIPP_P1CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P1CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P1CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P1CFSCR_FDTFEN               DCMIPP_P1CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P1CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P1CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1CFSCR_PIPEN                DCMIPP_P1CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P1CBPRCR register  ****************/
+#define DCMIPP_P1CBPRCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBPRCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBPRCR_ENABLE              DCMIPP_P1CBPRCR_ENABLE_Msk                      /*!< Current status of enable bit */
+#define DCMIPP_P1CBPRCR_STRENGTH_Pos        (1U)
+#define DCMIPP_P1CBPRCR_STRENGTH_Msk        (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos)          /*!< 0x0000000E */
+#define DCMIPP_P1CBPRCR_STRENGTH            DCMIPP_P1CBPRCR_STRENGTH_Msk                    /*!< Current strength (aggressivity) of the bad pixel detection: */
+
+/***************  Bit definition for DCMIPP_P1CBLCCR register  ****************/
+#define DCMIPP_P1CBLCCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBLCCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBLCCR_ENABLE              DCMIPP_P1CBLCCR_ENABLE_Msk                      /*!< For current black level calibration */
+#define DCMIPP_P1CBLCCR_BLCB_Pos            (8U)
+#define DCMIPP_P1CBLCCR_BLCB_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos)             /*!< 0x0000FF00 */
+#define DCMIPP_P1CBLCCR_BLCB                DCMIPP_P1CBLCCR_BLCB_Msk                        /*!< Current black level calibration - Blue */
+#define DCMIPP_P1CBLCCR_BLCG_Pos            (16U)
+#define DCMIPP_P1CBLCCR_BLCG_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos)             /*!< 0x00FF0000 */
+#define DCMIPP_P1CBLCCR_BLCG                DCMIPP_P1CBLCCR_BLCG_Msk                        /*!< Current black level calibration - Green */
+#define DCMIPP_P1CBLCCR_BLCR_Pos            (24U)
+#define DCMIPP_P1CBLCCR_BLCR_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos)             /*!< 0xFF000000 */
+#define DCMIPP_P1CBLCCR_BLCR                DCMIPP_P1CBLCCR_BLCR_Msk                        /*!< Current black level calibration - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR1 register  ****************/
+#define DCMIPP_P1CEXCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CEXCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CEXCR1_ENABLE              DCMIPP_P1CEXCR1_ENABLE_Msk                      /*!< for exposure control (multiplication and shift) */
+#define DCMIPP_P1CEXCR1_MULTR_Pos           (20U)
+#define DCMIPP_P1CEXCR1_MULTR_Msk           (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR1_MULTR               DCMIPP_P1CEXCR1_MULTR_Msk                       /*!< Current exposure multiplier - Red */
+#define DCMIPP_P1CEXCR1_SHFR_Pos            (28U)
+#define DCMIPP_P1CEXCR1_SHFR_Msk            (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR1_SHFR                DCMIPP_P1CEXCR1_SHFR_Msk                        /*!< Current exposure shift - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR2 register  ****************/
+#define DCMIPP_P1CEXCR2_MULTB_Pos           (4U)
+#define DCMIPP_P1CEXCR2_MULTB_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos)            /*!< 0x00000FF0 */
+#define DCMIPP_P1CEXCR2_MULTB               DCMIPP_P1CEXCR2_MULTB_Msk                       /*!< Current exposure multiplier - Blue */
+#define DCMIPP_P1CEXCR2_SHFB_Pos            (12U)
+#define DCMIPP_P1CEXCR2_SHFB_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos)              /*!< 0x00007000 */
+#define DCMIPP_P1CEXCR2_SHFB                DCMIPP_P1CEXCR2_SHFB_Msk                        /*!< Current exposure shift - Blue */
+#define DCMIPP_P1CEXCR2_MULTG_Pos           (20U)
+#define DCMIPP_P1CEXCR2_MULTG_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR2_MULTG               DCMIPP_P1CEXCR2_MULTG_Msk                       /*!< Current exposure multiplier - Green */
+#define DCMIPP_P1CEXCR2_SHFG_Pos            (28U)
+#define DCMIPP_P1CEXCR2_SHFG_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR2_SHFG                DCMIPP_P1CEXCR2_SHFG_Msk                        /*!< Current exposure shift - Green */
+
+/***************  Bit definition for DCMIPP_P1CST1CR register  ****************/
+#define DCMIPP_P1CST1CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST1CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST1CR_ENABLE              DCMIPP_P1CST1CR_ENABLE_Msk                      /*!< Current enable bit value */
+#define DCMIPP_P1CST1CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST1CR_BINS_Msk            (0x3UL << DCMIPP_P1CST1CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST1CR_BINS                DCMIPP_P1CST1CR_BINS_Msk                        /*!< Current bin definition */
+#define DCMIPP_P1CST1CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST1CR_SRC_Msk             (0x7UL << DCMIPP_P1CST1CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST1CR_SRC                 DCMIPP_P1CST1CR_SRC_Msk                         /*!< Current source of statistics */
+#define DCMIPP_P1CST1CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST1CR_MODE_Msk            (0x1UL << DCMIPP_P1CST1CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST1CR_MODE                DCMIPP_P1CST1CR_MODE_Msk                        /*!< Current statistics mode */
+#define DCMIPP_P1CST1CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST1CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST1CR_ACCU                DCMIPP_P1CST1CR_ACCU_Msk                        /*!< Current accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST2CR register  ****************/
+#define DCMIPP_P1CST2CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST2CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST2CR_ENABLE              DCMIPP_P1CST2CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST2CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST2CR_BINS_Msk            (0x3UL << DCMIPP_P1CST2CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST2CR_BINS                DCMIPP_P1CST2CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST2CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST2CR_SRC_Msk             (0x7UL << DCMIPP_P1CST2CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST2CR_SRC                 DCMIPP_P1CST2CR_SRC_Msk                         /*!< source of stat */
+#define DCMIPP_P1CST2CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST2CR_MODE_Msk            (0x1UL << DCMIPP_P1CST2CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST2CR_MODE                DCMIPP_P1CST2CR_MODE_Msk                        /*!< statistics mode */
+#define DCMIPP_P1CST2CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST2CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST2CR_ACCU                DCMIPP_P1CST2CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST3CR register  ****************/
+#define DCMIPP_P1CST3CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST3CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST3CR_ENABLE              DCMIPP_P1CST3CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST3CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST3CR_BINS_Msk            (0x3UL << DCMIPP_P1CST3CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST3CR_BINS                DCMIPP_P1CST3CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST3CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST3CR_SRC_Msk             (0x7UL << DCMIPP_P1CST3CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST3CR_SRC                 DCMIPP_P1CST3CR_SRC_Msk                         /*!< Statistics source */
+#define DCMIPP_P1CST3CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST3CR_MODE_Msk            (0x1UL << DCMIPP_P1CST3CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST3CR_MODE                DCMIPP_P1CST3CR_MODE_Msk                        /*!< Statistics mode */
+#define DCMIPP_P1CST3CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST3CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST3CR_ACCU                DCMIPP_P1CST3CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CSTSTR register  ****************/
+#define DCMIPP_P1CSTSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CSTSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSTR_HSTART              DCMIPP_P1CSTSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CSTSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSTR_VSTART              DCMIPP_P1CSTSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CSTSZR register  ****************/
+#define DCMIPP_P1CSTSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CSTSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSZR_HSIZE               DCMIPP_P1CSTSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CSTSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSZR_VSIZE               DCMIPP_P1CSTSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CSTSZR_CROPEN_Pos          (31U)
+#define DCMIPP_P1CSTSZR_CROPEN_Msk          (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CSTSZR_CROPEN              DCMIPP_P1CSTSZR_CROPEN_Msk                      /*!< Current CROPEN bit value */
+
+/****************  Bit definition for DCMIPP_P1CCCCR register  ****************/
+#define DCMIPP_P1CCCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CCCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CCCCR_ENABLE               DCMIPP_P1CCCCR_ENABLE_Msk                       /*!< This bit indicates the current value applied */
+#define DCMIPP_P1CCCCR_TYPE_Pos             (1U)
+#define DCMIPP_P1CCCCR_TYPE_Msk             (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1CCCCR_TYPE                 DCMIPP_P1CCCCR_TYPE_Msk                         /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1CCCCR_CLAMP_Msk            (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1CCCCR_CLAMP                DCMIPP_P1CCCCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1CCCRR1 register  ****************/
+#define DCMIPP_P1CCCRR1_RR_Pos              (0U)
+#define DCMIPP_P1CCCRR1_RR_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR1_RR                  DCMIPP_P1CCCRR1_RR_Msk                          /*!< Current coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCCRR1_RG_Pos              (16U)
+#define DCMIPP_P1CCCRR1_RG_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCRR1_RG                  DCMIPP_P1CCCRR1_RG_Msk                          /*!< Current coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCRR2 register  ****************/
+#define DCMIPP_P1CCCRR2_RB_Pos              (0U)
+#define DCMIPP_P1CCCRR2_RB_Msk              (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR2_RB                  DCMIPP_P1CCCRR2_RB_Msk                          /*!< Current coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCCRR2_RA_Pos              (16U)
+#define DCMIPP_P1CCCRR2_RA_Msk              (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCRR2_RA                  DCMIPP_P1CCCRR2_RA_Msk                          /*!< Current coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCGR1 register  ****************/
+#define DCMIPP_P1CCCGR1_GR_Pos              (0U)
+#define DCMIPP_P1CCCGR1_GR_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR1_GR                  DCMIPP_P1CCCGR1_GR_Msk                          /*!< Current coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCCGR1_GG_Pos              (16U)
+#define DCMIPP_P1CCCGR1_GG_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCGR1_GG                  DCMIPP_P1CCCGR1_GG_Msk                          /*!< Current coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCGR2 register  ****************/
+#define DCMIPP_P1CCCGR2_GB_Pos              (0U)
+#define DCMIPP_P1CCCGR2_GB_Msk              (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR2_GB                  DCMIPP_P1CCCGR2_GB_Msk                          /*!< Current coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCCGR2_GA_Pos              (16U)
+#define DCMIPP_P1CCCGR2_GA_Msk              (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCGR2_GA                  DCMIPP_P1CCCGR2_GA_Msk                          /*!< Current coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCBR1 register  ****************/
+#define DCMIPP_P1CCCBR1_BR_Pos              (0U)
+#define DCMIPP_P1CCCBR1_BR_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR1_BR                  DCMIPP_P1CCCBR1_BR_Msk                          /*!< Current coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCCBR1_BG_Pos              (16U)
+#define DCMIPP_P1CCCBR1_BG_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCBR1_BG                  DCMIPP_P1CCCBR1_BG_Msk                          /*!< Current coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCBR2 register  ****************/
+#define DCMIPP_P1CCCBR2_BB_Pos              (0U)
+#define DCMIPP_P1CCCBR2_BB_Msk              (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR2_BB                  DCMIPP_P1CCCBR2_BB_Msk                          /*!< Current coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCCBR2_BA_Pos              (16U)
+#define DCMIPP_P1CCCBR2_BA_Msk              (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCBR2_BA                  DCMIPP_P1CCCBR2_BA_Msk                          /*!< Current coefficient row 3 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR1 register  ****************/
+#define DCMIPP_P1CCTCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CCTCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CCTCR1_ENABLE              DCMIPP_P1CCTCR1_ENABLE_Msk                      /*!< Current ENABLE bit value */
+#define DCMIPP_P1CCTCR1_LUM0_Pos            (9U)
+#define DCMIPP_P1CCTCR1_LUM0_Msk            (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR1_LUM0                DCMIPP_P1CCTCR1_LUM0_Msk                        /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR2 register  ****************/
+#define DCMIPP_P1CCTCR2_LUM4_Pos            (1U)
+#define DCMIPP_P1CCTCR2_LUM4_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR2_LUM4                DCMIPP_P1CCTCR2_LUM4_Msk                        /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM3_Pos            (9U)
+#define DCMIPP_P1CCTCR2_LUM3_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR2_LUM3                DCMIPP_P1CCTCR2_LUM3_Msk                        /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM2_Pos            (17U)
+#define DCMIPP_P1CCTCR2_LUM2_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR2_LUM2                DCMIPP_P1CCTCR2_LUM2_Msk                        /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM1_Pos            (25U)
+#define DCMIPP_P1CCTCR2_LUM1_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR2_LUM1                DCMIPP_P1CCTCR2_LUM1_Msk                        /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR3 register  ****************/
+#define DCMIPP_P1CCTCR3_LUM8_Pos            (1U)
+#define DCMIPP_P1CCTCR3_LUM8_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR3_LUM8                DCMIPP_P1CCTCR3_LUM8_Msk                        /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM7_Pos            (9U)
+#define DCMIPP_P1CCTCR3_LUM7_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR3_LUM7                DCMIPP_P1CCTCR3_LUM7_Msk                        /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM6_Pos            (17U)
+#define DCMIPP_P1CCTCR3_LUM6_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR3_LUM6                DCMIPP_P1CCTCR3_LUM6_Msk                        /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM5_Pos            (25U)
+#define DCMIPP_P1CCTCR3_LUM5_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR3_LUM5                DCMIPP_P1CCTCR3_LUM5_Msk                        /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CFCTCR register  ****************/
+#define DCMIPP_P1CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P1CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P1CFCTCR_FRATE               DCMIPP_P1CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P1CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P1CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P1CFCTCR_CPTMODE             DCMIPP_P1CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P1CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P1CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P1CFCTCR_CPTREQ              DCMIPP_P1CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P1CCRSTR register  ****************/
+#define DCMIPP_P1CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSTR_HSTART              DCMIPP_P1CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSTR_VSTART              DCMIPP_P1CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CCRSZR register  ****************/
+#define DCMIPP_P1CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSZR_HSIZE               DCMIPP_P1CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSZR_VSIZE               DCMIPP_P1CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P1CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CCRSZR_ENABLE              DCMIPP_P1CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P1CDCCR register  *****************/
+#define DCMIPP_P1CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CDCCR_ENABLE               DCMIPP_P1CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P1CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P1CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1CDCCR_HDEC                 DCMIPP_P1CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P1CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P1CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1CDCCR_VDEC                 DCMIPP_P1CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1CDSCR register  ****************/
+#define DCMIPP_P1CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P1CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P1CDSCR_HDIV                 DCMIPP_P1CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P1CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P1CDSCR_VDIV                 DCMIPP_P1CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CDSCR_ENABLE               DCMIPP_P1CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P1CDSRTIOR register  ***************/
+#define DCMIPP_P1CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P1CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P1CDSRTIOR_HRATIO            DCMIPP_P1CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P1CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P1CDSRTIOR_VRATIO            DCMIPP_P1CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P1CDSSZR register  ****************/
+#define DCMIPP_P1CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CDSSZR_HSIZE               DCMIPP_P1CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CDSSZR_VSIZE               DCMIPP_P1CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CPPCR register  ****************/
+#define DCMIPP_P1CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P1CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P1CPPCR_FORMAT               DCMIPP_P1CPPCR_FORMAT_Msk                       /*!< Memory format */
+#define DCMIPP_P1CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P1CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P1CPPCR_SWAPRB               DCMIPP_P1CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P1CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P1CPPCR_LINEMULT             DCMIPP_P1CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+
+/**************  Bit definition for DCMIPP_P1CPPM0AR1 register  ***************/
+#define DCMIPP_P1CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P1CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM0AR1_M0A               DCMIPP_P1CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM0PR register  ***************/
+#define DCMIPP_P1CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM0PR_PITCH              DCMIPP_P1CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM1AR1 register  ***************/
+#define DCMIPP_P1CPPM1AR1_M1A_Pos           (0U)
+#define DCMIPP_P1CPPM1AR1_M1A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM1AR1_M1A               DCMIPP_P1CPPM1AR1_M1A_Msk                       /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM1PR register  ***************/
+#define DCMIPP_P1CPPM1PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM1PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM1PR_PITCH              DCMIPP_P1CPPM1PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM2AR1 register  ***************/
+#define DCMIPP_P1CPPM2AR1_M2A_Pos           (0U)
+#define DCMIPP_P1CPPM2AR1_M2A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM2AR1_M2A               DCMIPP_P1CPPM2AR1_M2A_Msk                       /*!< Memory 2 address */
+
+/****************  Bit definition for DCMIPP_P2FSCR register  *****************/
+#define DCMIPP_P2FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P2FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2FSCR_DTIDA                 DCMIPP_P2FSCR_DTIDA_Msk                         /*!< Data type ID */
+#define DCMIPP_P2FSCR_VC_Pos                (19U)
+#define DCMIPP_P2FSCR_VC_Msk                (0x3UL << DCMIPP_P2FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P2FSCR_VC                    DCMIPP_P2FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P2FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P2FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P2FSCR_FDTF                  DCMIPP_P2FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P2FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P2FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P2FSCR_FDTFEN                DCMIPP_P2FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P2FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P2FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P2FSCR_PIPEN                 DCMIPP_P2FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P2FCTCR register  ****************/
+#define DCMIPP_P2FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P2FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P2FCTCR_FRATE                DCMIPP_P2FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P2FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P2FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P2FCTCR_CPTMODE              DCMIPP_P2FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P2FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P2FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P2FCTCR_CPTREQ               DCMIPP_P2FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P2CRSTR register  ****************/
+#define DCMIPP_P2CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P2CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CRSTR_HSTART               DCMIPP_P2CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P2CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSTR_VSTART               DCMIPP_P2CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CRSZR register  ****************/
+#define DCMIPP_P2CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2CRSZR_HSIZE                DCMIPP_P2CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSZR_VSIZE                DCMIPP_P2CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CRSZR_ENABLE               DCMIPP_P2CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P2DCCR register  *****************/
+#define DCMIPP_P2DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P2DCCR_ENABLE                DCMIPP_P2DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P2DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P2DCCR_HDEC_Msk              (0x3UL << DCMIPP_P2DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P2DCCR_HDEC                  DCMIPP_P2DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P2DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P2DCCR_VDEC_Msk              (0x3UL << DCMIPP_P2DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P2DCCR_VDEC                  DCMIPP_P2DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2DSCR register  *****************/
+#define DCMIPP_P2DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P2DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P2DSCR_HDIV                  DCMIPP_P2DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P2DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P2DSCR_VDIV                  DCMIPP_P2DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P2DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2DSCR_ENABLE                DCMIPP_P2DSCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2DSRTIOR register  ***************/
+#define DCMIPP_P2DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P2DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P2DSRTIOR_HRATIO             DCMIPP_P2DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P2DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P2DSRTIOR_VRATIO             DCMIPP_P2DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P2DSSZR register  ****************/
+#define DCMIPP_P2DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2DSSZR_HSIZE                DCMIPP_P2DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2DSSZR_VSIZE                DCMIPP_P2DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2GMCR register  *****************/
+#define DCMIPP_P2GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P2GMCR_ENABLE                DCMIPP_P2GMCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2CMRICR register  ***************/
+#define DCMIPP_P2CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P2CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P2CMRICR_ROILSZ              DCMIPP_P2CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P2CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P2CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P2CMRICR_ROI1EN              DCMIPP_P2CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P2CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P2CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P2CMRICR_ROI2EN              DCMIPP_P2CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P2CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P2CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P2CMRICR_ROI3EN              DCMIPP_P2CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P2CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P2CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P2CMRICR_ROI4EN              DCMIPP_P2CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P2CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P2CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P2CMRICR_ROI5EN              DCMIPP_P2CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P2CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P2CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P2CMRICR_ROI6EN              DCMIPP_P2CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P2CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P2CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P2CMRICR_ROI7EN              DCMIPP_P2CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P2CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P2CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P2CMRICR_ROI8EN              DCMIPP_P2CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P2RIxCR1 register  ***************/
+#define DCMIPP_P2RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P2RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P2RIxCR1_HSTART              DCMIPP_P2RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P2RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P2RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P2RIxCR1_CLB                 DCMIPP_P2RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P2RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P2RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P2RIxCR1_CLG                 DCMIPP_P2RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P2RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P2RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P2RIxCR1_VSTART              DCMIPP_P2RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P2RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P2RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P2RIxCR1_CLR                 DCMIPP_P2RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P2RIxCR2 register  ***************/
+#define DCMIPP_P2RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P2RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P2RIxCR2_VSIZE               DCMIPP_P2RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P2RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P2RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P2RIxCR2_HSIZE               DCMIPP_P2RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P2PPCR register  *****************/
+#define DCMIPP_P2PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P2PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P2PPCR_FORMAT                DCMIPP_P2PPCR_FORMAT_Msk                         /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P2PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P2PPCR_SWAPRB                DCMIPP_P2PPCR_SWAPRB_Msk                         /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P2PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P2PPCR_LINEMULT              DCMIPP_P2PPCR_LINEMULT_Msk                       /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2PPCR_DBM_Pos               (16U)
+#define DCMIPP_P2PPCR_DBM_Msk               (0x1UL << DCMIPP_P2PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P2PPCR_DBM                   DCMIPP_P2PPCR_DBM_Msk                            /*!< Double buffer mode */
+#define DCMIPP_P2PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P2PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos)               /*!< 0x000E0000 */
+#define DCMIPP_P2PPCR_LMAWM                 DCMIPP_P2PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P2PPCR_LMAWE_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos)               /*!< 0x00100000 */
+#define DCMIPP_P2PPCR_LMAWE                 DCMIPP_P2PPCR_LMAWE_Msk                          /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR1 register  ***************/
+#define DCMIPP_P2PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR1_M0A                DCMIPP_P2PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1 */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR2 register  ***************/
+#define DCMIPP_P2PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR2_M0A                DCMIPP_P2PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2*/
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P2PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P2PPM0PR_PITCH               DCMIPP_P2PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2STM0AR_Pos                 (0U)
+#define DCMIPP_P2STM0AR_Msk                 (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P2STM0AR                     DCMIPP_P2STM0AR_Msk                             /*!< Pipe2 status Memory0 address register */
+
+/*****************  Bit definition for DCMIPP_P2IER register  *****************/
+#define DCMIPP_P2IER_LINEIE_Pos             (0U)
+#define DCMIPP_P2IER_LINEIE_Msk             (0x1UL << DCMIPP_P2IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2IER_LINEIE                 DCMIPP_P2IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P2IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P2IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2IER_FRAMEIE                DCMIPP_P2IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P2IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P2IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2IER_VSYNCIE                DCMIPP_P2IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P2IER_OVRIE_Pos              (7U)
+#define DCMIPP_P2IER_OVRIE_Msk              (0x1UL << DCMIPP_P2IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2IER_OVRIE                  DCMIPP_P2IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P2SR register  ******************/
+#define DCMIPP_P2SR_LINEF_Pos               (0U)
+#define DCMIPP_P2SR_LINEF_Msk               (0x1UL << DCMIPP_P2SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P2SR_LINEF                   DCMIPP_P2SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P2SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P2SR_FRAMEF_Msk              (0x1UL << DCMIPP_P2SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P2SR_FRAMEF                  DCMIPP_P2SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P2SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P2SR_VSYNCF_Msk              (0x1UL << DCMIPP_P2SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P2SR_VSYNCF                  DCMIPP_P2SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P2SR_OVRF_Pos                (7U)
+#define DCMIPP_P2SR_OVRF_Msk                (0x1UL << DCMIPP_P2SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P2SR_OVRF                    DCMIPP_P2SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P2SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P2SR_LSTLINE_Msk             (0x1UL << DCMIPP_P2SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P2SR_LSTLINE                 DCMIPP_P2SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P2SR_LSTFRM_Msk              (0x1UL << DCMIPP_P2SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P2SR_LSTFRM                  DCMIPP_P2SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_CPTACT_Pos              (23U)
+#define DCMIPP_P2SR_CPTACT_Msk              (0x1UL << DCMIPP_P2SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P2SR_CPTACT                  DCMIPP_P2SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P2FCR register  *****************/
+#define DCMIPP_P2FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P2FCR_CLINEF_Msk             (0x1UL << DCMIPP_P2FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2FCR_CLINEF                 DCMIPP_P2FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P2FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2FCR_CFRAMEF                DCMIPP_P2FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P2FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2FCR_CVSYNCF                DCMIPP_P2FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P2FCR_COVRF_Pos              (7U)
+#define DCMIPP_P2FCR_COVRF_Msk              (0x1UL << DCMIPP_P2FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2FCR_COVRF                  DCMIPP_P2FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P2CFSCR register  ****************/
+#define DCMIPP_P2CFSCR_DTID_Pos             (0U)
+#define DCMIPP_P2CFSCR_DTID_Msk             (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2CFSCR_DTID                 DCMIPP_P2CFSCR_DTID_Msk                         /*!< Current Data type ID */
+#define DCMIPP_P2CFSCR_VC_Pos               (19U)
+#define DCMIPP_P2CFSCR_VC_Msk               (0x3UL << DCMIPP_P2CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P2CFSCR_VC                   DCMIPP_P2CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P2CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P2CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P2CFSCR_FDTF                 DCMIPP_P2CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P2CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P2CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P2CFSCR_FDTFEN               DCMIPP_P2CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P2CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P2CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2CFSCR_PIPEN                DCMIPP_P2CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P2CFCTCR register  ****************/
+#define DCMIPP_P2CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P2CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P2CFCTCR_FRATE               DCMIPP_P2CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P2CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P2CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P2CFCTCR_CPTMODE             DCMIPP_P2CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P2CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P2CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P2CFCTCR_CPTREQ              DCMIPP_P2CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P2CCRSTR register  ****************/
+#define DCMIPP_P2CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P2CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSTR_HSTART              DCMIPP_P2CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P2CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSTR_VSTART              DCMIPP_P2CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P2CCRSZR register  ****************/
+#define DCMIPP_P2CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSZR_HSIZE               DCMIPP_P2CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSZR_VSIZE               DCMIPP_P2CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P2CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P2CCRSZR_ENABLE              DCMIPP_P2CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P2CDCCR register  *****************/
+#define DCMIPP_P2CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P2CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P2CDCCR_ENABLE               DCMIPP_P2CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P2CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P2CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos)              /*!< 0x00000006 */
+#define DCMIPP_P2CDCCR_HDEC                 DCMIPP_P2CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P2CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P2CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos)              /*!< 0x00000018 */
+#define DCMIPP_P2CDCCR_VDEC                 DCMIPP_P2CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2CDSCR register  ****************/
+#define DCMIPP_P2CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P2CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P2CDSCR_HDIV                 DCMIPP_P2CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P2CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P2CDSCR_VDIV                 DCMIPP_P2CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CDSCR_ENABLE               DCMIPP_P2CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P2CDSRTIOR register  ***************/
+#define DCMIPP_P2CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P2CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P2CDSRTIOR_HRATIO            DCMIPP_P2CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P2CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P2CDSRTIOR_VRATIO            DCMIPP_P2CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P2CDSSZR register  ****************/
+#define DCMIPP_P2CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CDSSZR_HSIZE               DCMIPP_P2CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CDSSZR_VSIZE               DCMIPP_P2CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CPPCR register  ****************/
+#define DCMIPP_P2CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P2CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P2CPPCR_FORMAT               DCMIPP_P2CPPCR_FORMAT_Msk                       /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P2CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P2CPPCR_SWAPRB               DCMIPP_P2CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P2CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P2CPPCR_LINEMULT             DCMIPP_P2CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P2CPPCR_DBM_Msk              (0x1UL << DCMIPP_P2CPPCR_DBM_Pos)                /*!< 0x00010000 */
+#define DCMIPP_P2CPPCR_DBM                  DCMIPP_P2CPPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P2CPPCR_LMAWM_Pos            (17U)
+#define DCMIPP_P2CPPCR_LMAWM_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos)              /*!< 0x000E0000 */
+#define DCMIPP_P2CPPCR_LMAWM                DCMIPP_P2CPPCR_LMAWM_Msk                         /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2CPPCR_LMAWE_Pos            (20U)
+#define DCMIPP_P2CPPCR_LMAWE_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos)              /*!< 0x00100000 */
+#define DCMIPP_P2CPPCR_LMAWE                DCMIPP_P2CPPCR_LMAWE_Msk                         /*!< Line multi address wrapping enable */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR1 register  ***************/
+#define DCMIPP_P2CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR1_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR2 register  ***************/
+#define DCMIPP_P2CPPM0AR2_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR2_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR2_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address Register 2 */
+
+/***************  Bit definition for DCMIPP_P2CPPM0PR register  ***************/
+#define DCMIPP_P2CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P2CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P2CPPM0PR_PITCH              DCMIPP_P2CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/****************  Bit definition for DCMIPP_HWCFGR2 register  ****************/
+#define DCMIPP_HWCFGR2_VPFT_Pos             (0U)
+#define DCMIPP_HWCFGR2_VPFT_Msk             (0x7U << DCMIPP_HWCFGR2_VPFT_Pos)               /*!< 0x00000007 */
+#define DCMIPP_HWCFGR2_VPFT                 DCMIPP_HWCFGR2_VPFT_Msk                         /*!< Virtual pipe function */
+#define DCMIPP_HWCFGR2_DBMFT_Pos            (4U)
+#define DCMIPP_HWCFGR2_DBMFT_Msk            (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos)              /*!< 0x00000010 */
+#define DCMIPP_HWCFGR2_DBMFT                DCMIPP_HWCFGR2_DBMFT_Msk                        /*!< Double buffer mode featured */
+#define DCMIPP_HWCFGR2_PROCCLK_Pos          (8U)
+#define DCMIPP_HWCFGR2_PROCCLK_Msk          (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos)            /*!< 0x00000100 */
+#define DCMIPP_HWCFGR2_PROCCLK              DCMIPP_HWCFGR2_PROCCLK_Msk                      /*!< Processing clock linked to AXI clock featured */
+#define DCMIPP_HWCFGR2_ADDMOD_Pos           (12U)
+#define DCMIPP_HWCFGR2_ADDMOD_Msk           (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR2_ADDMOD               DCMIPP_HWCFGR2_ADDMOD_Msk                       /*!< Address modulo computation to access a small buffer in streaming featured */
+#define DCMIPP_HWCFGR2_DEC1_Pos             (16U)
+#define DCMIPP_HWCFGR2_DEC1_Msk             (0x1U << DCMIPP_HWCFGR2_DEC1_Pos)               /*!< 0x00010000 */
+#define DCMIPP_HWCFGR2_DEC1                 DCMIPP_HWCFGR2_DEC1_Msk                         /*!< Decimation on Pipe1 before downsize */
+#define DCMIPP_HWCFGR2_DEC2_Pos             (17U)
+#define DCMIPP_HWCFGR2_DEC2_Msk             (0x1U << DCMIPP_HWCFGR2_DEC2_Pos)               /*!< 0x00020000 */
+#define DCMIPP_HWCFGR2_DEC2                 DCMIPP_HWCFGR2_DEC2_Msk                         /*!< Decimation on Pipe2 before downsize */
+#define DCMIPP_HWCFGR2_MCU_Pos              (20U)
+#define DCMIPP_HWCFGR2_MCU_Msk              (0x1U << DCMIPP_HWCFGR2_MCU_Pos)                /*!< 0x00100000 */
+#define DCMIPP_HWCFGR2_MCU                  DCMIPP_HWCFGR2_MCU_Msk                          /*!< Macroblock unit as pixel format  */
+#define DCMIPP_HWCFGR2_TPG_Pos              (24U)
+#define DCMIPP_HWCFGR2_TPG_Msk              (0x1U << DCMIPP_HWCFGR2_TPG_Pos)                /*!< 0x01000000 */
+#define DCMIPP_HWCFGR2_TPG                  DCMIPP_HWCFGR2_TPG_Msk                          /*!< Test Pattern Generator */
+#define DCMIPP_HWCFGR2_STV_Pos              (28U)
+#define DCMIPP_HWCFGR2_STV_Msk              (0x1U << DCMIPP_HWCFGR2_STV_Pos)                /*!< 0x10000000 */
+#define DCMIPP_HWCFGR2_STV                  DCMIPP_HWCFGR2_STV_Msk                          /*!< Statistic Version */
+
+/****************  Bit definition for DCMIPP_HWCFGR1 register  ****************/
+#define DCMIPP_HWCFGR1_CSIFT_Pos            (0U)
+#define DCMIPP_HWCFGR1_CSIFT_Msk            (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos)              /*!< 0x00000001 */
+#define DCMIPP_HWCFGR1_CSIFT                DCMIPP_HWCFGR1_CSIFT_Msk                        /*!< CSI2 host protocol compliant */
+#define DCMIPP_HWCFGR1_PIPENB_Pos           (4U)
+#define DCMIPP_HWCFGR1_PIPENB_Msk           (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos)             /*!< 0x00000030 */
+#define DCMIPP_HWCFGR1_PIPENB               DCMIPP_HWCFGR1_PIPENB_Msk                       /*!< Number of pipes */
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos        (8U)
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk        (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos)          /*!< 0x00000100 */
+#define DCMIPP_HWCFGR1_IPPLUGCFG            DCMIPP_HWCFGR1_IPPLUGCFG_Msk                    /*!< IP-Plug configuration */
+#define DCMIPP_HWCFGR1_DSP1FT_Pos           (12U)
+#define DCMIPP_HWCFGR1_DSP1FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR1_DSP1FT               DCMIPP_HWCFGR1_DSP1FT_Msk                       /*!< Down-sampling feature for the pixel Pipe1 */
+#define DCMIPP_HWCFGR1_DSP2FT_Pos           (13U)
+#define DCMIPP_HWCFGR1_DSP2FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos)             /*!< 0x00002000 */
+#define DCMIPP_HWCFGR1_DSP2FT               DCMIPP_HWCFGR1_DSP2FT_Msk                       /*!< Down-sampling feature for the pixel Pipe2 */
+#define DCMIPP_HWCFGR1_RB2RGB_Pos           (16U)
+#define DCMIPP_HWCFGR1_RB2RGB_Msk           (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos)             /*!< 0x00010000 */
+#define DCMIPP_HWCFGR1_RB2RGB               DCMIPP_HWCFGR1_RB2RGB_Msk                       /*!< Raw Bayer to RGB feature (demosaicer) */
+#define DCMIPP_HWCFGR1_PLANARFT_Pos         (20U)
+#define DCMIPP_HWCFGR1_PLANARFT_Msk         (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos)           /*!< 0x00300000 */
+#define DCMIPP_HWCFGR1_PLANARFT             DCMIPP_HWCFGR1_PLANARFT_Msk                     /*!< Buffer features for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI1NB_Pos           (24U)
+#define DCMIPP_HWCFGR1_ROI1NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos)             /*!< 0x0F000000 */
+#define DCMIPP_HWCFGR1_ROI1NB               DCMIPP_HWCFGR1_ROI1NB_Msk                       /*!< Number of ROIs for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI2NB_Pos           (28U)
+#define DCMIPP_HWCFGR1_ROI2NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos)             /*!< 0xF0000000 */
+#define DCMIPP_HWCFGR1_ROI2NB               DCMIPP_HWCFGR1_ROI2NB_Msk                       /*!< Number of ROIs for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_VERR register  ******************/
+#define DCMIPP_VERR_MINREV_Pos              (0U)
+#define DCMIPP_VERR_MINREV_Msk              (0xFU << DCMIPP_VERR_MINREV_Pos)                /*!< 0x0000000F */
+#define DCMIPP_VERR_MINREV                  DCMIPP_VERR_MINREV_Msk                          /*!< DCMIPP minor revision */
+#define DCMIPP_VERR_MAJREV_Pos              (4U)
+#define DCMIPP_VERR_MAJREV_Msk              (0xFU << DCMIPP_VERR_MAJREV_Pos)                /*!< 0x000000F0 */
+#define DCMIPP_VERR_MAJREV                  DCMIPP_VERR_MAJREV_Msk                          /*!< DCMIPP major revision */
+
+/*****************  Bit definition for DCMIPP_IPIDR register  *****************/
+#define DCMIPP_IPIDR_IDR_Pos                (0U)
+#define DCMIPP_IPIDR_IDR_Msk                (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_IPIDR_IDR                    DCMIPP_IPIDR_IDR_Msk                            /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */
+
+/*****************  Bit definition for DCMIPP_SIDR register  ******************/
+#define DCMIPP_SIDR_SID_Pos                 (0U)
+#define DCMIPP_SIDR_SID_Msk                 (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos)            /*!< 0xFFFFFFFF */
+#define DCMIPP_SIDR_SID                     DCMIPP_SIDR_SID_Msk                             /*!< 4-Kbyte decoding space */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos                     (0U)
+#define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
+#define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos                     (1U)
+#define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
+#define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos                   (0U)
+#define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
+#define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos                  (8U)
+#define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos                   (16U)
+#define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos                  (31U)
+#define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_SECCFGR register  ****************/
+#define DMA_SECCFGR_SEC0_Pos     (0U)
+#define DMA_SECCFGR_SEC0_Msk     (0x1UL << DMA_SECCFGR_SEC0_Pos)                /*!< 0x00000001 */
+#define DMA_SECCFGR_SEC0         DMA_SECCFGR_SEC0_Msk                          /*!< Secure State of Channel 0 */
+#define DMA_SECCFGR_SEC1_Pos     (1U)
+#define DMA_SECCFGR_SEC1_Msk     (0x1UL << DMA_SECCFGR_SEC1_Pos)                /*!< 0x00000002 */
+#define DMA_SECCFGR_SEC1         DMA_SECCFGR_SEC1_Msk                          /*!< Secure State of Channel 1 */
+#define DMA_SECCFGR_SEC2_Pos     (2U)
+#define DMA_SECCFGR_SEC2_Msk     (0x1UL << DMA_SECCFGR_SEC2_Pos)                /*!< 0x00000004 */
+#define DMA_SECCFGR_SEC2         DMA_SECCFGR_SEC2_Msk                          /*!< Secure State of Channel 2 */
+#define DMA_SECCFGR_SEC3_Pos     (3U)
+#define DMA_SECCFGR_SEC3_Msk     (0x1UL << DMA_SECCFGR_SEC3_Pos)                /*!< 0x00000008 */
+#define DMA_SECCFGR_SEC3         DMA_SECCFGR_SEC3_Msk                          /*!< Secure State of Channel 3 */
+#define DMA_SECCFGR_SEC4_Pos     (4U)
+#define DMA_SECCFGR_SEC4_Msk     (0x1UL << DMA_SECCFGR_SEC4_Pos)                /*!< 0x00000010 */
+#define DMA_SECCFGR_SEC4         DMA_SECCFGR_SEC4_Msk                          /*!< Secure State of Channel 4 */
+#define DMA_SECCFGR_SEC5_Pos     (5U)
+#define DMA_SECCFGR_SEC5_Msk     (0x1UL << DMA_SECCFGR_SEC5_Pos)                /*!< 0x00000020 */
+#define DMA_SECCFGR_SEC5         DMA_SECCFGR_SEC5_Msk                          /*!< Secure State of Channel 5 */
+#define DMA_SECCFGR_SEC6_Pos     (6U)
+#define DMA_SECCFGR_SEC6_Msk     (0x1UL << DMA_SECCFGR_SEC6_Pos)                /*!< 0x00000040 */
+#define DMA_SECCFGR_SEC6         DMA_SECCFGR_SEC6_Msk                          /*!< Secure State of Channel 6 */
+#define DMA_SECCFGR_SEC7_Pos     (7U)
+#define DMA_SECCFGR_SEC7_Msk     (0x1UL << DMA_SECCFGR_SEC7_Pos)                /*!< 0x00000080 */
+#define DMA_SECCFGR_SEC7         DMA_SECCFGR_SEC7_Msk                          /*!< Secure State of Channel 7 */
+#define DMA_SECCFGR_SEC8_Pos     (8U)
+#define DMA_SECCFGR_SEC8_Msk     (0x1UL << DMA_SECCFGR_SEC8_Pos)                /*!< 0x00000100 */
+#define DMA_SECCFGR_SEC8         DMA_SECCFGR_SEC8_Msk                          /*!< Secure State of Channel 8 */
+#define DMA_SECCFGR_SEC9_Pos     (9U)
+#define DMA_SECCFGR_SEC9_Msk     (0x1UL << DMA_SECCFGR_SEC9_Pos)                /*!< 0x00000200 */
+#define DMA_SECCFGR_SEC9         DMA_SECCFGR_SEC9_Msk                          /*!< Secure State of Channel 9 */
+#define DMA_SECCFGR_SEC10_Pos    (10U)
+#define DMA_SECCFGR_SEC10_Msk    (0x1UL << DMA_SECCFGR_SEC10_Pos)               /*!< 0x00000400 */
+#define DMA_SECCFGR_SEC10        DMA_SECCFGR_SEC10_Msk                         /*!< Secure State of Channel 10 */
+#define DMA_SECCFGR_SEC11_Pos    (11U)
+#define DMA_SECCFGR_SEC11_Msk    (0x1UL << DMA_SECCFGR_SEC11_Pos)               /*!< 0x00000800 */
+#define DMA_SECCFGR_SEC11        DMA_SECCFGR_SEC11_Msk                         /*!< Secure State of Channel 11 */
+#define DMA_SECCFGR_SEC12_Pos    (12U)
+#define DMA_SECCFGR_SEC12_Msk    (0x1UL << DMA_SECCFGR_SEC12_Pos)               /*!< 0x00001000 */
+#define DMA_SECCFGR_SEC12        DMA_SECCFGR_SEC12_Msk                         /*!< Secure State of Channel 12 */
+#define DMA_SECCFGR_SEC13_Pos    (13U)
+#define DMA_SECCFGR_SEC13_Msk    (0x1UL << DMA_SECCFGR_SEC13_Pos)               /*!< 0x00002000 */
+#define DMA_SECCFGR_SEC13        DMA_SECCFGR_SEC13_Msk                         /*!< Secure State of Channel 13 */
+#define DMA_SECCFGR_SEC14_Pos    (14U)
+#define DMA_SECCFGR_SEC14_Msk    (0x1UL << DMA_SECCFGR_SEC14_Pos)               /*!< 0x00004000 */
+#define DMA_SECCFGR_SEC14        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 14 */
+#define DMA_SECCFGR_SEC15_Pos    (15U)
+#define DMA_SECCFGR_SEC15_Msk    (0x1UL << DMA_SECCFGR_SEC15_Pos)               /*!< 0x00008000 */
+#define DMA_SECCFGR_SEC15        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 15 */
+
+/*******************  Bit definition for DMA_PRIVCFGR register  ****************/
+#define DMA_PRIVCFGR_PRIV0_Pos              (0U)
+#define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0 */
+#define DMA_PRIVCFGR_PRIV1_Pos              (1U)
+#define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1 */
+#define DMA_PRIVCFGR_PRIV2_Pos              (2U)
+#define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2 */
+#define DMA_PRIVCFGR_PRIV3_Pos              (3U)
+#define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3 */
+#define DMA_PRIVCFGR_PRIV4_Pos              (4U)
+#define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4 */
+#define DMA_PRIVCFGR_PRIV5_Pos              (5U)
+#define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5 */
+#define DMA_PRIVCFGR_PRIV6_Pos              (6U)
+#define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6 */
+#define DMA_PRIVCFGR_PRIV7_Pos              (7U)
+#define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7 */
+#define DMA_PRIVCFGR_PRIV8_Pos              (8U)
+#define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
+#define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8 */
+#define DMA_PRIVCFGR_PRIV9_Pos              (9U)
+#define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
+#define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9 */
+#define DMA_PRIVCFGR_PRIV10_Pos             (10U)
+#define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
+#define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
+#define DMA_PRIVCFGR_PRIV11_Pos             (11U)
+#define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
+#define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */
+#define DMA_PRIVCFGR_PRIV12_Pos             (12U)
+#define DMA_PRIVCFGR_PRIV12_Msk             (0x1UL << DMA_PRIVCFGR_PRIV12_Pos)      /*!< 0x00001000 */
+#define DMA_PRIVCFGR_PRIV12                 DMA_PRIVCFGR_PRIV12_Msk                 /*!< Privileged State of Channel 12 */
+#define DMA_PRIVCFGR_PRIV13_Pos             (13U)
+#define DMA_PRIVCFGR_PRIV13_Msk             (0x1UL << DMA_PRIVCFGR_PRIV13_Pos)      /*!< 0x00002000 */
+#define DMA_PRIVCFGR_PRIV13                 DMA_PRIVCFGR_PRIV13_Msk                 /*!< Privileged State of Channel 13 */
+#define DMA_PRIVCFGR_PRIV14_Pos             (14U)
+#define DMA_PRIVCFGR_PRIV14_Msk             (0x1UL << DMA_PRIVCFGR_PRIV14_Pos)      /*!< 0x00004000 */
+#define DMA_PRIVCFGR_PRIV14                 DMA_PRIVCFGR_PRIV14_Msk                 /*!< Privileged State of Channel 14 */
+#define DMA_PRIVCFGR_PRIV15_Pos             (15U)
+#define DMA_PRIVCFGR_PRIV15_Msk             (0x1UL << DMA_PRIVCFGR_PRIV15_Pos)      /*!< 0x00008000 */
+#define DMA_PRIVCFGR_PRIV15                 DMA_PRIVCFGR_PRIV15_Msk                 /*!< Privileged State of Channel 15 */
+
+/*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
+#define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
+#define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
+#define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
+#define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
+#define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
+#define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
+#define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
+#define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
+#define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
+#define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
+#define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
+#define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
+#define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
+#define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
+#define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
+#define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
+#define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
+#define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
+#define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
+#define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
+#define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
+#define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
+#define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
+#define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
+#define DMA_RCFGLOCKR_LOCK8_Pos              (8U)
+#define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
+#define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
+#define DMA_RCFGLOCKR_LOCK9_Pos              (9U)
+#define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
+#define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
+#define DMA_RCFGLOCKR_LOCK10_Pos             (10U)
+#define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
+#define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
+#define DMA_RCFGLOCKR_LOCK11_Pos             (11U)
+#define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
+#define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */
+#define DMA_RCFGLOCKR_LOCK12_Pos             (12U)
+#define DMA_RCFGLOCKR_LOCK12_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos)      /*!< 0x00001000 */
+#define DMA_RCFGLOCKR_LOCK12                 DMA_RCFGLOCKR_LOCK12_Msk                 /*!< Lock the configuration of Channel 12 */
+#define DMA_RCFGLOCKR_LOCK13_Pos             (13U)
+#define DMA_RCFGLOCKR_LOCK13_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos)      /*!< 0x00002000 */
+#define DMA_RCFGLOCKR_LOCK13                 DMA_RCFGLOCKR_LOCK13_Msk                 /*!< Lock the configuration of Channel 13 */
+#define DMA_RCFGLOCKR_LOCK14_Pos             (14U)
+#define DMA_RCFGLOCKR_LOCK14_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos)      /*!< 0x00004000 */
+#define DMA_RCFGLOCKR_LOCK14                 DMA_RCFGLOCKR_LOCK14_Msk                 /*!< Lock the configuration of Channel 14 */
+#define DMA_RCFGLOCKR_LOCK15_Pos             (15U)
+#define DMA_RCFGLOCKR_LOCK15_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos)      /*!< 0x00008000 */
+#define DMA_RCFGLOCKR_LOCK15                 DMA_RCFGLOCKR_LOCK15_Msk                 /*!< Lock the configuration of Channel 15 */
+
+/*******************  Bit definition for DMA_MISR register  ****************/
+#define DMA_MISR_MIS0_Pos                   (0U)
+#define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
+#define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0 */
+#define DMA_MISR_MIS1_Pos                   (1U)
+#define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
+#define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1 */
+#define DMA_MISR_MIS2_Pos                   (2U)
+#define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
+#define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2 */
+#define DMA_MISR_MIS3_Pos                   (3U)
+#define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
+#define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3 */
+#define DMA_MISR_MIS4_Pos                   (4U)
+#define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
+#define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4 */
+#define DMA_MISR_MIS5_Pos                   (5U)
+#define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
+#define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5 */
+#define DMA_MISR_MIS6_Pos                   (6U)
+#define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
+#define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6 */
+#define DMA_MISR_MIS7_Pos                   (7U)
+#define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
+#define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7 */
+#define DMA_MISR_MIS8_Pos                   (8U)
+#define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
+#define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 8 */
+#define DMA_MISR_MIS9_Pos                   (9U)
+#define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
+#define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 9 */
+#define DMA_MISR_MIS10_Pos                  (10U)
+#define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
+#define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 10 */
+#define DMA_MISR_MIS11_Pos                  (11U)
+#define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
+#define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 11 */
+#define DMA_MISR_MIS12_Pos                  (12U)
+#define DMA_MISR_MIS12_Msk                  (0x1UL << DMA_MISR_MIS12_Pos)           /*!< 0x00001000 */
+#define DMA_MISR_MIS12                      DMA_MISR_MIS12_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 12 */
+#define DMA_MISR_MIS13_Pos                  (13U)
+#define DMA_MISR_MIS13_Msk                  (0x1UL << DMA_MISR_MIS13_Pos)           /*!< 0x00002000 */
+#define DMA_MISR_MIS13                      DMA_MISR_MIS13_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 13 */
+#define DMA_MISR_MIS14_Pos                  (14U)
+#define DMA_MISR_MIS14_Msk                  (0x1UL << DMA_MISR_MIS14_Pos)           /*!< 0x00004000 */
+#define DMA_MISR_MIS14                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 14 */
+#define DMA_MISR_MIS15_Pos                  (15U)
+#define DMA_MISR_MIS15_Msk                  (0x1UL << DMA_MISR_MIS15_Pos)           /*!< 0x00008000 */
+#define DMA_MISR_MIS15                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 15 */
+
+/*******************  Bit definition for DMA_SMISR register  ****************/
+#define DMA_SMISR_MIS0_Pos       (0U)
+#define DMA_SMISR_MIS0_Msk       (0x1UL << DMA_SMISR_MIS0_Pos)                  /*!< 0x00000001 */
+#define DMA_SMISR_MIS0           DMA_SMISR_MIS0_Msk                            /*!< Masked Interrupt State of Secure Channel 0 */
+#define DMA_SMISR_MIS1_Pos       (1U)
+#define DMA_SMISR_MIS1_Msk       (0x1UL << DMA_SMISR_MIS1_Pos)                  /*!< 0x00000002 */
+#define DMA_SMISR_MIS1           DMA_SMISR_MIS1_Msk                            /*!< Masked Interrupt State of Secure Channel 1 */
+#define DMA_SMISR_MIS2_Pos       (2U)
+#define DMA_SMISR_MIS2_Msk       (0x1UL << DMA_SMISR_MIS2_Pos)                  /*!< 0x00000004 */
+#define DMA_SMISR_MIS2           DMA_SMISR_MIS2_Msk                            /*!< Masked Interrupt State of Secure Channel 2 */
+#define DMA_SMISR_MIS3_Pos       (3U)
+#define DMA_SMISR_MIS3_Msk       (0x1UL << DMA_SMISR_MIS3_Pos)                  /*!< 0x00000008 */
+#define DMA_SMISR_MIS3           DMA_SMISR_MIS3_Msk                            /*!< Masked Interrupt State of Secure Channel 3 */
+#define DMA_SMISR_MIS4_Pos       (4U)
+#define DMA_SMISR_MIS4_Msk       (0x1UL << DMA_SMISR_MIS4_Pos)                  /*!< 0x00000010 */
+#define DMA_SMISR_MIS4           DMA_SMISR_MIS4_Msk                            /*!< Masked Interrupt State of Secure Channel 4 */
+#define DMA_SMISR_MIS5_Pos       (5U)
+#define DMA_SMISR_MIS5_Msk       (0x1UL << DMA_SMISR_MIS5_Pos)                  /*!< 0x00000020 */
+#define DMA_SMISR_MIS5           DMA_SMISR_MIS5_Msk                            /*!< Masked Interrupt State of Secure Channel 5 */
+#define DMA_SMISR_MIS6_Pos       (6U)
+#define DMA_SMISR_MIS6_Msk       (0x1UL << DMA_SMISR_MIS6_Pos)                  /*!< 0x00000040 */
+#define DMA_SMISR_MIS6           DMA_SMISR_MIS6_Msk                            /*!< Masked Interrupt State of Secure Channel 6 */
+#define DMA_SMISR_MIS7_Pos       (7U)
+#define DMA_SMISR_MIS7_Msk       (0x1UL << DMA_SMISR_MIS7_Pos)                  /*!< 0x00000080 */
+#define DMA_SMISR_MIS7           DMA_SMISR_MIS7_Msk                            /*!< Masked Interrupt State of Secure Channel 7 */
+#define DMA_SMISR_MIS8_Pos       (8U)
+#define DMA_SMISR_MIS8_Msk       (0x1UL << DMA_SMISR_MIS8_Pos)                  /*!< 0x00000100 */
+#define DMA_SMISR_MIS8           DMA_SMISR_MIS8_Msk                            /*!< Masked Interrupt State of Secure Channel 8 */
+#define DMA_SMISR_MIS9_Pos       (9U)
+#define DMA_SMISR_MIS9_Msk       (0x1UL << DMA_SMISR_MIS9_Pos)                  /*!< 0x00000200 */
+#define DMA_SMISR_MIS9           DMA_SMISR_MIS9_Msk                            /*!< Masked Interrupt State of Secure Channel 9 */
+#define DMA_SMISR_MIS10_Pos      (10U)
+#define DMA_SMISR_MIS10_Msk      (0x1UL << DMA_SMISR_MIS10_Pos)                 /*!< 0x00000400 */
+#define DMA_SMISR_MIS10          DMA_SMISR_MIS10_Msk                           /*!< Masked Interrupt State of Secure Channel 10 */
+#define DMA_SMISR_MIS11_Pos      (11U)
+#define DMA_SMISR_MIS11_Msk      (0x1UL << DMA_SMISR_MIS11_Pos)                 /*!< 0x00000800 */
+#define DMA_SMISR_MIS11          DMA_SMISR_MIS11_Msk                           /*!< Masked Interrupt State of Secure Channel 11 */
+#define DMA_SMISR_MIS12_Pos      (12U)
+#define DMA_SMISR_MIS12_Msk      (0x1UL << DMA_SMISR_MIS12_Pos)                 /*!< 0x00001000 */
+#define DMA_SMISR_MIS12          DMA_SMISR_MIS12_Msk                           /*!< Masked Interrupt State of Secure Channel 12 */
+#define DMA_SMISR_MIS13_Pos      (13U)
+#define DMA_SMISR_MIS13_Msk      (0x1UL << DMA_SMISR_MIS13_Pos)                 /*!< 0x00002000 */
+#define DMA_SMISR_MIS13          DMA_SMISR_MIS13_Msk                           /*!< Masked Interrupt State of Secure Channel 13 */
+#define DMA_SMISR_MIS14_Pos      (14U)
+#define DMA_SMISR_MIS14_Msk      (0x1UL << DMA_SMISR_MIS14_Pos)                 /*!< 0x00004000 */
+#define DMA_SMISR_MIS14          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 14 */
+#define DMA_SMISR_MIS15_Pos      (15U)
+#define DMA_SMISR_MIS15_Msk      (0x1UL << DMA_SMISR_MIS15_Pos)                 /*!< 0x00008000 */
+#define DMA_SMISR_MIS15          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 15 */
+
+/*******************  Bit definition for DMA_CLBAR register  ****************/
+#define DMA_CLBAR_LBA_Pos                   (16U)
+#define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
+#define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
+
+/*******************  Bit definition for DMA_CCIDCFGR register  *******************/
+#define DMA_CCIDCFGR_CFEN_Pos           (0U)
+#define DMA_CCIDCFGR_CFEN_Msk           (0x1UL << DMA_CCIDCFGR_CFEN_Pos)         /*!< 0x00000001 */
+#define DMA_CCIDCFGR_CFEN               DMA_CCIDCFGR_CFEN_Msk                   /*!< CID filtering enable of the channel x */
+#define DMA_CCIDCFGR_SCID_Pos           (4U)
+#define DMA_CCIDCFGR_SCID_Msk           (0x7UL << DMA_CCIDCFGR_SCID_Pos)         /*!< 0x00000070 */
+#define DMA_CCIDCFGR_SCID               DMA_CCIDCFGR_SCID_Msk                   /*!< select a static CID to the channel x */
+
+/*******************  Bit definition for DMA_CFCR register  *******************/
+#define DMA_CFCR_TCF_Pos                    (8U)
+#define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
+#define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear */
+#define DMA_CFCR_HTF_Pos                    (9U)
+#define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
+#define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear */
+#define DMA_CFCR_DTEF_Pos                   (10U)
+#define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
+#define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear */
+#define DMA_CFCR_ULEF_Pos                   (11U)
+#define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
+#define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
+#define DMA_CFCR_USEF_Pos                   (12U)
+#define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
+#define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear */
+#define DMA_CFCR_SUSPF_Pos                  (13U)
+#define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
+#define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear */
+#define DMA_CFCR_TOF_Pos                    (14U)
+#define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
+#define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun clear flag */
+
+/*******************  Bit definition for DMA_CSR register  *******************/
+#define DMA_CSR_IDLEF_Pos                   (0U)
+#define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
+#define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag */
+#define DMA_CSR_TCF_Pos                     (8U)
+#define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
+#define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag */
+#define DMA_CSR_HTF_Pos                     (9U)
+#define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
+#define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag */
+#define DMA_CSR_DTEF_Pos                    (10U)
+#define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
+#define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag */
+#define DMA_CSR_ULEF_Pos                    (11U)
+#define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
+#define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
+#define DMA_CSR_USEF_Pos                    (12U)
+#define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
+#define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag */
+#define DMA_CSR_SUSPF_Pos                   (13U)
+#define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
+#define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag */
+#define DMA_CSR_TOF_Pos                     (14U)
+#define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
+#define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag */
+#define DMA_CSR_FIFOL_Pos                   (16U)
+#define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
+#define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos                      (0U)
+#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable */
+#define DMA_CCR_RESET_Pos                   (1U)
+#define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
+#define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset */
+#define DMA_CCR_SUSP_Pos                    (2U)
+#define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
+#define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend */
+#define DMA_CCR_TCIE_Pos                    (8U)
+#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
+#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos                    (9U)
+#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
+#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable */
+#define DMA_CCR_DTEIE_Pos                   (10U)
+#define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
+#define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable */
+#define DMA_CCR_ULEIE_Pos                   (11U)
+#define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
+#define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
+#define DMA_CCR_USEIE_Pos                   (12U)
+#define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
+#define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable */
+#define DMA_CCR_SUSPIE_Pos                  (13U)
+#define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
+#define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable */
+#define DMA_CCR_TOIE_Pos                    (14U)
+#define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
+#define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable */
+#define DMA_CCR_LSM_Pos                     (16U)
+#define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
+#define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode */
+#define DMA_CCR_LAP_Pos                     (17U)
+#define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
+#define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port */
+#define DMA_CCR_PRIO_Pos                    (22U)
+#define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
+#define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level */
+#define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
+#define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
+
+/*******************  Bit definition for DMA_CTR1 register  *******************/
+#define DMA_CTR1_SDW_LOG2_Pos               (0U)
+#define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
+#define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst */
+#define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_SINC_Pos                   (3U)
+#define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
+#define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst */
+#define DMA_CTR1_SBL_1_Pos                  (4U)
+#define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
+#define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1 */
+#define DMA_CTR1_PAM_Pos                    (11U)
+#define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
+#define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode */
+#define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
+#define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
+#define DMA_CTR1_SBX_Pos                    (13U)
+#define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
+#define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
+#define DMA_CTR1_SAP_Pos                    (14U)
+#define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
+#define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port */
+#define DMA_CTR1_SSEC_Pos                   (15U)
+#define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
+#define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source */
+#define DMA_CTR1_DDW_LOG2_Pos               (16U)
+#define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
+#define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst */
+#define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_DINC_Pos                   (19U)
+#define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
+#define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst */
+#define DMA_CTR1_DBL_1_Pos                  (20U)
+#define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
+#define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1 */
+#define DMA_CTR1_DBX_Pos                    (26U)
+#define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
+#define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange */
+#define DMA_CTR1_DHX_Pos                    (27U)
+#define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
+#define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange */
+#define DMA_CTR1_DWX_Pos                    (28U)
+#define DMA_CTR1_DWX_Msk                    (0x1UL << DMA_CTR1_DWX_Pos)             /*!< 0x10000000 */
+#define DMA_CTR1_DWX                        DMA_CTR1_DWX_Msk                        /*!< Destination word-word exchange */
+#define DMA_CTR1_DAP_Pos                    (30U)
+#define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
+#define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port */
+#define DMA_CTR1_DSEC_Pos                   (31U)
+#define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
+#define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination */
+
+/******************  Bit definition for DMA_CTR2 register  *******************/
+#define DMA_CTR2_REQSEL_Pos                 (0U)
+#define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
+#define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
+#define DMA_CTR2_SWREQ_Pos                  (9U)
+#define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
+#define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request */
+#define DMA_CTR2_DREQ_Pos                   (10U)
+#define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
+#define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request */
+#define DMA_CTR2_BREQ_Pos                   (11U)
+#define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
+#define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request */
+#define DMA_CTR2_PFREQ_Pos                  (12U)
+#define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)           /*!< 0x00001000 */
+#define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Hardware request in peripheral flow control mode */
+#define DMA_CTR2_TRIGM_Pos                  (14U)
+#define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
+#define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode */
+#define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
+#define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
+#define DMA_CTR2_TRIGSEL_Pos                (16U)
+#define DMA_CTR2_TRIGSEL_Msk                (0x7FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x007F0000 */
+#define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection */
+#define DMA_CTR2_TRIGPOL_Pos                (24U)
+#define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
+#define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity */
+#define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
+#define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
+#define DMA_CTR2_TCEM_Pos                   (30U)
+#define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
+#define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode */
+#define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
+#define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
+
+/******************  Bit definition for DMA_CBR1 register  *******************/
+#define DMA_CBR1_BNDT_Pos                   (0U)
+#define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
+#define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
+#define DMA_CBR1_BRC_Pos                    (16U)
+#define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
+#define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter */
+#define DMA_CBR1_SDEC_Pos                   (28U)
+#define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
+#define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement */
+#define DMA_CBR1_DDEC_Pos                   (29U)
+#define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
+#define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement */
+#define DMA_CBR1_BRSDEC_Pos                 (30U)
+#define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
+#define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement */
+#define DMA_CBR1_BRDDEC_Pos                 (31U)
+#define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
+#define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement */
+
+/******************  Bit definition for DMA_CSAR register  ********************/
+#define DMA_CSAR_SA_Pos                     (0U)
+#define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
+
+/******************  Bit definition for DMA_CDAR register  *******************/
+#define DMA_CDAR_DA_Pos                     (0U)
+#define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
+
+/******************  Bit definition for DMA_CTR3 register  *******************/
+#define DMA_CTR3_SAO_Pos                    (0U)
+#define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
+#define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment */
+#define DMA_CTR3_DAO_Pos                    (16U)
+#define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
+#define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
+
+/******************  Bit definition for DMA_CBR2 register  *******************/
+#define DMA_CBR2_BRSAO_Pos                  (0U)
+#define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
+#define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset */
+#define DMA_CBR2_BRDAO_Pos                  (16U)
+#define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
+#define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
+
+/******************  Bit definition for DMA_CLLR register  *******************/
+#define DMA_CLLR_LA_Pos                     (2U)
+#define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
+#define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
+#define DMA_CLLR_ULL_Pos                    (16U)
+#define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
+#define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory */
+#define DMA_CLLR_UB2_Pos                    (25U)
+#define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
+#define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory */
+#define DMA_CLLR_UT3_Pos                    (26U)
+#define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
+#define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM */
+#define DMA_CLLR_UDA_Pos                    (27U)
+#define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
+#define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM */
+#define DMA_CLLR_USA_Pos                    (28U)
+#define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
+#define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM */
+#define DMA_CLLR_UB1_Pos                    (29U)
+#define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
+#define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM */
+#define DMA_CLLR_UT2_Pos                    (30U)
+#define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
+#define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM */
+#define DMA_CLLR_UT1_Pos                    (31U)
+#define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
+#define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          DMA2D Controller (DMA2D)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DMA2D_CR register  ******************/
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0] */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /*!< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+/*!<Mode_ARGB8888/RGB888 */
+#define DMA2D_OCOLR_BLUE_1         (0x000000FFUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_1        (0x0000FF00UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_1          (0x00FF0000UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1        (0xFF000000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_2        (0x000007E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_2          (0x0000F800UL)                              /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_3        (0x000003E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_3          (0x00007C00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3        (0x00008000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4         (0x0000000FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_4        (0x000000F0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_4          (0x00000F00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4        (0x0000F000UL)                              /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital Temperature Sensor                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DTS_PVTREG_LOCKR register  *****************/
+#define DTS_PVTREG_LOCKR_LOCK_Pos                 (0U)
+#define DTS_PVTREG_LOCKR_LOCK_Msk                 (0xFFFFFFFFUL << DTS_PVTREG_LOCKR_LOCK_Pos)         /*!< 0xFFFFFFFF */
+#define DTS_PVTREG_LOCKR_LOCK                     DTS_PVTREG_LOCKR_LOCK_Msk                           /*!< PVT software lock */
+
+/*******************  Bit definition for DTS_PVTLOCK_SR register  *****************/
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos         (0U)
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos)        /*!< 0x00000001 */
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS             DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk                   /*!< Software lock status */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos         (1U)
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos)        /*!< 0x00000002 */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS             DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk                   /*!< Hardware lock status */
+
+/*******************  Bit definition for DTS_PVTTMR_CR register  *****************/
+#define DTS_PVTTMR_CR_TMR_DELAY_Pos               (0U)
+#define DTS_PVTTMR_CR_TMR_DELAY_Msk               (0xFFFFUL << DTS_PVTTMR_CR_TMR_DELAY_Pos)           /*!< 0x0000FFFF */
+#define DTS_PVTTMR_CR_TMR_DELAY                   DTS_PVTTMR_CR_TMR_DELAY_Msk                         /*!< Timer delay */
+#define DTS_PVTTMR_CR_TMR_RUN_Pos                 (16U)
+#define DTS_PVTTMR_CR_TMR_RUN_Msk                 (0x1UL << DTS_PVTTMR_CR_TMR_RUN_Pos)                /*!< 0x00010000 */
+#define DTS_PVTTMR_CR_TMR_RUN                     DTS_PVTTMR_CR_TMR_RUN_Msk                           /*!< Enable */
+
+/*******************  Bit definition for DTS_PVTTMR_SR register  *****************/
+#define DTS_PVTTMR_SR_TMR_BUSY_Pos                (0U)
+#define DTS_PVTTMR_SR_TMR_BUSY_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_BUSY_Pos)               /*!< 0x00000001 */
+#define DTS_PVTTMR_SR_TMR_BUSY                    DTS_PVTTMR_SR_TMR_BUSY_Msk                          /*!< Counter busy flag */
+#define DTS_PVTTMR_SR_TMR_DONE_Pos                (1U)
+#define DTS_PVTTMR_SR_TMR_DONE_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_PVTTMR_SR_TMR_DONE                    DTS_PVTTMR_SR_TMR_DONE_Msk                          /*!< Cnt delay timeout */
+
+/*******************  Bit definition for DTS_PVT_IER register  *****************/
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Pos            (0U)
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Msk            (0x1UL << DTS_PVT_IER_TMR_IRQ_ENABLE_Pos)           /*!< 0x00000001 */
+#define DTS_PVT_IER_TMR_IRQ_ENABLE                DTS_PVT_IER_TMR_IRQ_ENABLE_Msk                      /*!< Timer IRQ enable */
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Pos             (1U)
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Msk             (0x1UL << DTS_PVT_IER_TS_IRQ_ENABLE_Pos)            /*!< 0x00000002 */
+#define DTS_PVT_IER_TS_IRQ_ENABLE                 DTS_PVT_IER_TS_IRQ_ENABLE_Msk                       /*!< TS IRQ enable */
+
+/*******************  Bit definition for DTS_PVTIRQTRMASKR register  *****************/
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos        (0U)
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk        (0x1UL << DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos)       /*!< 0x00000001 */
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK            DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk                  /*!< Timer IRQ mask */
+
+/*******************  Bit definition for DTS_TS_MR register  *****************/
+#define DTS_TS_MR_TS0_IRQ_MASK_Pos                (0U)
+#define DTS_TS_MR_TS0_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS0_IRQ_MASK_Pos)               /*!< 0x00000001 */
+#define DTS_TS_MR_TS0_IRQ_MASK                    DTS_TS_MR_TS0_IRQ_MASK_Msk                          /*!< TS0 IRQ mask */
+#define DTS_TS_MR_TS1_IRQ_MASK_Pos                (1U)
+#define DTS_TS_MR_TS1_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS1_IRQ_MASK_Pos)               /*!< 0x00000002 */
+#define DTS_TS_MR_TS1_IRQ_MASK                    DTS_TS_MR_TS1_IRQ_MASK_Msk                          /*!< TS1 IRQ mask */
+
+/*******************  Bit definition for DTS_PVTTR_SR register  *****************/
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos           (0U)
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk           (0x1UL << DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos)          /*!< 0x00000001 */
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS               DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk                     /*!< Timer IRQ status after masking */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Pos             (0U)
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS0_IRQ_STATUS_Pos)            /*!< 0x00000001 */
+#define DTS_TS_ISR_TS0_IRQ_STATUS                 DTS_TS_ISR_TS0_IRQ_STATUS_Msk                       /*!< TS0 IRQ status after masking */
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Pos             (1U)
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS1_IRQ_STATUS_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ISR_TS1_IRQ_STATUS                 DTS_TS_ISR_TS1_IRQ_STATUS_Msk                       /*!< TS1 IRQ status after masking */
+
+/*******************  Bit definition for DTS_PVTTMRRAW_ISR register  *****************/
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos  (0U)
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk  (0x1UL << DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos) /*!< 0x00000001 */
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS      DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk            /*!< Timer IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSRAW_ISR register  *****************/
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos      (0U)
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos)     /*!< 0x00000001 */
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS0_RAW_IRQ_STATUS_Msk                /*!< TS0 IRQ status before masking */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos      (1U)
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos)     /*!< 0x00000002 */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk                /*!< TS1 IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSCCLKSYNTHR register  *****************/
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos         (0U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos)       /*!< 0x000000FF */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO             DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk                   /*!< Synthesized clk_ts low period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos         (8U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos)       /*!< 0x0000FF00 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI             DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk                   /*!< Synthesized clk_ts ghigh period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos       (16U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk       (0xFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos)      /*!< 0x000F0000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD           DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk                 /*!< Hold input or output delay */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos         (24U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk         (0x1UL << DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos)        /*!< 0x01000000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN             DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk                   /*!< Synthesized enable */
+
+/*******************  Bit definition for DTS_TSCSDIFDISABLER register  *****************/
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos  (0U)
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk            /*!< TS0 SDIF disable */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos  (1U)
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos) /*!< 0x00000002 */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk            /*!< TS1 SDIF disable */
+
+/*******************  Bit definition for DTS_TSCSDIF_SR register  *****************/
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Pos              (0U)
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_BUSY_Pos)             /*!< 0x00000001 */
+#define DTS_TSCSDIF_SR_SDIF_BUSY                  DTS_TSCSDIF_SR_SDIF_BUSY_Msk                        /*!< SDIF busy flag */
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Pos              (1U)
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_LOCK_Pos)             /*!< 0x00000002 */
+#define DTS_TSCSDIF_SR_SDIF_LOCK                  DTS_TSCSDIF_SR_SDIF_LOCK_Msk                        /*!< SDIF locked flag */
+
+/*******************  Bit definition for DTS_TSCSDIF_CR register  *****************/
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Pos             (0U)
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Msk             (0xFFFFFFUL << DTS_TSCSDIF_CR_SDIF_WDATA_Pos)       /*!< 0x00FFFFFF */
+#define DTS_TSCSDIF_CR_SDIF_WDATA                 DTS_TSCSDIF_CR_SDIF_WDATA_Msk                       /*!< SDIF write data */
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Pos              (24U)
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Msk              (0x7UL << DTS_TSCSDIF_CR_SDIF_ADDR_Pos)             /*!< 0x07000000 */
+#define DTS_TSCSDIF_CR_SDIF_ADDR                  DTS_TSCSDIF_CR_SDIF_ADDR_Msk                        /*!< SDIF register address */
+#define DTS_TSCSDIF_CR_SDIF_WRN_Pos               (27U)
+#define DTS_TSCSDIF_CR_SDIF_WRN_Msk               (0x1UL << DTS_TSCSDIF_CR_SDIF_WRN_Pos)              /*!< 0x08000000 */
+#define DTS_TSCSDIF_CR_SDIF_WRN                   DTS_TSCSDIF_CR_SDIF_WRN_Msk                         /*!< SDIF write no read control */
+#define DTS_TSCSDIF_CR_SDIF_PROG_Pos              (31U)
+#define DTS_TSCSDIF_CR_SDIF_PROG_Msk              (0x1UL << DTS_TSCSDIF_CR_SDIF_PROG_Pos)             /*!< 0x80000000 */
+#define DTS_TSCSDIF_CR_SDIF_PROG                  DTS_TSCSDIF_CR_SDIF_PROG_Msk                        /*!< SDIF program request */
+
+/*******************  Bit definition for DTS_TSCSDIFHALTR register  *****************/
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Pos            (0U)
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Msk            (0x1UL << DTS_TSCSDIFHALTR_SDIF_STOP_Pos)           /*!< 0x00000001 */
+#define DTS_TSCSDIFHALTR_SDIF_STOP                DTS_TSCSDIFHALTR_SDIF_STOP_Msk                      /*!< SDIF stop */
+
+/*******************  Bit definition for DTS_TSCSDIF_CFGR register  *****************/
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos         (0U)
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk         (0x3UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000003 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT             DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk                   /*!< SDIF programming inhibit */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_0           (0x1UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000001 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_1           (0x2UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000002 */
+
+/*******************  Bit definition for DTS_TSCSMPL_CR register  *****************/
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos       (0U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk       (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos)      /*!< 0x00000001 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE           DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk                 /*!< Sample counter disable */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos          (1U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk          (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos)         /*!< 0x00000002 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD              DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk                    /*!< Sample counter hold */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Pos           (2U)
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Msk           (0x1UL << DTS_TSCSMPL_CR_SMPL_DISCARD_Pos)          /*!< 0x00000004 */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD               DTS_TSCSMPL_CR_SMPL_DISCARD_Msk                     /*!< Sample discard */
+
+/*******************  Bit definition for DTS_TSCSDIFSMPLCLRR register  *****************/
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos  (0U)
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk  (0x1UL << DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR      DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk            /*!< Sample counter clear */
+
+/*******************  Bit definition for DTS_TSCSMPLCNTR register  *****************/
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Pos            (0U)
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Msk            (0xFFFFUL << DTS_TSCSMPLCNTR_SMPL_COUNT_Pos)        /*!< 0x0000FFFF */
+#define DTS_TSCSMPLCNTR_SMPL_COUNT                DTS_TSCSMPLCNTR_SMPL_COUNT_Msk                      /*!< Sample counter  */
+
+/*******************  Bit definition for DTS_TS_IER register  *****************/
+#define DTS_TS_IER_IRQ_EN_FAULT_Pos               (0U)
+#define DTS_TS_IER_IRQ_EN_FAULT_Msk               (0x1UL << DTS_TS_IER_IRQ_EN_FAULT_Pos)              /*!< 0x00000001 */
+#define DTS_TS_IER_IRQ_EN_FAULT                   DTS_TS_IER_IRQ_EN_FAULT_Msk                         /*!< TS Fault IRQ enable */
+#define DTS_TS_IER_IRQ_EN_DONE_Pos                (1U)
+#define DTS_TS_IER_IRQ_EN_DONE_Msk                (0x1UL << DTS_TS_IER_IRQ_EN_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_TS_IER_IRQ_EN_DONE                    DTS_TS_IER_IRQ_EN_DONE_Msk                          /*!< TS Sample done IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMA_Pos              (3U)
+#define DTS_TS_IER_IRQ_EN_ALARMA_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMA_Pos)             /*!< 0x00000008 */
+#define DTS_TS_IER_IRQ_EN_ALARMA                  DTS_TS_IER_IRQ_EN_ALARMA_Msk                        /*!< TS Alarm A IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMB_Pos              (4U)
+#define DTS_TS_IER_IRQ_EN_ALARMB_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMB_Pos)             /*!< 0x00000010 */
+#define DTS_TS_IER_IRQ_EN_ALARMB                  DTS_TS_IER_IRQ_EN_ALARMB_Msk                        /*!< TS Alarm B IRQ enable */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Pos           (0U)
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Msk           (0x1UL << DTS_TS_ISR_IRQ_STATUS_FAULT_Pos)          /*!< 0x00000001 */
+#define DTS_TS_ISR_IRQ_STATUS_FAULT               DTS_TS_ISR_IRQ_STATUS_FAULT_Msk                     /*!< TS Fault IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Pos            (1U)
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Msk            (0x1UL << DTS_TS_ISR_IRQ_STATUS_DONE_Pos)           /*!< 0x00000002 */
+#define DTS_TS_ISR_IRQ_STATUS_DONE                DTS_TS_ISR_IRQ_STATUS_DONE_Msk                      /*!< TS Sample done IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos          (3U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos)         /*!< 0x00000008 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA              DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk                    /*!< TS Alarm A IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos          (4U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos)         /*!< 0x00000010 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB              DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk                    /*!< TS Alarm B IRQ status */
+
+/*******************  Bit definition for DTS_TS_ICR register  *****************/
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos            (0U)
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk            (0x1UL << DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos)           /*!< 0x00000001 */
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT                DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk                      /*!< TS Fault IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Pos             (1U)
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Msk             (0x1UL << DTS_TS_ICR_IRQ_CLEAR_DONE_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE                 DTS_TS_ICR_IRQ_CLEAR_DONE_Msk                       /*!< TS Sample done IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos           (3U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos)          /*!< 0x00000008 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA               DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk                     /*!< TS Alarm A IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos           (4U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos)          /*!< 0x00000010 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB               DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk                     /*!< TS Alarm B IRQ clear */
+
+/*******************  Bit definition for DTS_TSIRQTESTR register  *****************/
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos         (0U)
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk         (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos)        /*!< 0x00000001 */
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT             DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk                   /*!< TS Fault IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos          (1U)
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk          (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos)         /*!< 0x00000002 */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE              DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk                    /*!< TS Sample done IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos        (3U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos)       /*!< 0x00000008 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA            DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk                  /*!< TS Alarm A IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos        (4U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos)       /*!< 0x00000010 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB            DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk                  /*!< TS Alarm B IRQ test */
+
+/*******************  Bit definition for DTS_TSSDIFRDATAR register  *****************/
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Pos           (0U)
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Msk           (0xFFFFFFUL << DTS_TSSDIFRDATAR_SDIF_RDATA_Pos)     /*!< 0x00FFFFFF */
+#define DTS_TSSDIFRDATAR_SDIF_RDATA               DTS_TSSDIFRDATAR_SDIF_RDATA_Msk                     /*!< TS SDIF read data */
+
+/*******************  Bit definition for DTS_TSSDIFDONER register  *****************/
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos        (0U)
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk        (0x1UL << DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos)       /*!< 0x00000001 */
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE            DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk                  /*!< TS Sample done flag */
+
+/*******************  Bit definition for DTS_TSSDIFDATAR register  *****************/
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Pos           (0U)
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Msk           (0xFFFFUL << DTS_TSSDIFDATAR_SAMPLE_DATA_Pos)       /*!< 0x0000FFFF */
+#define DTS_TSSDIFDATAR_SAMPLE_DATA               DTS_TSSDIFDATAR_SAMPLE_DATA_Msk                     /*!< TS Sample data */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos           (16U)
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk           (0x1UL << DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos)          /*!< 0x00010000 */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE               DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk                     /*!< TS Sample type */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos          (17U)
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk          (0x1UL << DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos)         /*!< 0x00020000 */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT              DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk                    /*!< TS Sample fault */
+
+/*******************  Bit definition for DTS_TSALARMA_CFGR register  *****************/
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos        (0U)
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk        (0xFFFFUL << DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH            DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk                  /*!< TS Alarm A hysteresis threshold */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos       (16U)
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk       (0xFFFFUL << DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH           DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk                 /*!< TS Alarm A threshold */
+
+/*******************  Bit definition for DTS_TSALARMB_CFGR register  *****************/
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos        (0U)
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk        (0xFFFFUL << DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH            DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk                  /*!< TS Alarm B hysteresis threshold */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos       (16U)
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk       (0xFFFFUL << DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH           DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk                 /*!< TS Alarm B threshold */
+
+/*******************  Bit definition for DTS_TSHLSAMPLER register  *****************/
+#define DTS_TSHLSAMPLER_SMPL_LO_Pos               (0U)
+#define DTS_TSHLSAMPLER_SMPL_LO_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_LO_Pos)           /*!< 0x0000FFFF */
+#define DTS_TSHLSAMPLER_SMPL_LO                   DTS_TSHLSAMPLER_SMPL_LO_Msk                         /*!< TS Lowest valid data sample value received */
+#define DTS_TSHLSAMPLER_SMPL_HI_Pos               (16U)
+#define DTS_TSHLSAMPLER_SMPL_HI_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_HI_Pos)           /*!< 0xFFFF0000 */
+#define DTS_TSHLSAMPLER_SMPL_HI                   DTS_TSHLSAMPLER_SMPL_HI_Msk                         /*!< TS Highest valid data sample value received */
+
+/*******************  Bit definition for DTS_TSHILORESETR register  *****************/
+#define DTS_TSHILORESETR_SMPL_LO_SET_Pos          (0U)
+#define DTS_TSHILORESETR_SMPL_LO_SET_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_LO_SET_Pos)         /*!< 0x00000001 */
+#define DTS_TSHILORESETR_SMPL_LO_SET              DTS_TSHILORESETR_SMPL_LO_SET_Msk                    /*!< TS Sample Low Set */
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Pos          (1U)
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_HI_CLR_Pos)         /*!< 0x00000002 */
+#define DTS_TSHILORESETR_SMPL_HI_CLR              DTS_TSHILORESETR_SMPL_HI_CLR_Msk                    /*!< TS Sample high clear 0 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              Ethernet MAC                                  */
+/*                                                                            */
+/******************************************************************************/
+/******  Bit definition for Ethernet MAC Configuration Register  **************/
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_PB_Pos                              (18U)
+#define ETH_MACCR_PB_Msk                              (0x1UL << ETH_MACCR_PB_Pos) /*!< 0x00040000 */
+#define ETH_MACCR_PB                                  ETH_MACCR_PB_Msk         /* Packet Burst Enable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_PS_Pos                              (15U)
+#define ETH_MACCR_PS_Msk                              (0x1UL << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
+#define ETH_MACCR_PS                                  ETH_MACCR_PS_Msk         /* Port Select */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* MAC speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/******  Bit definition for Ethernet MAC Extended Configuration Register  ***********/
+#define ETH_MACECR_APDIM_Pos                          (30U)
+#define ETH_MACECR_APDIM_Msk                          (0x1FUL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */
+#define ETH_MACECR_APDIM                              ETH_MACECR_APDIM_Msk      /* ARP Packet Drop if IP Address Mismatch */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/************  Bit definition for Ethernet MAC Packet Filter Register  ***************/
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/************  Bit definition for Ethernet MAC Watchdog Timeout Register  ***************/
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/************  Bit definition for Ethernet MAC Hash Table 0 register  ***************/
+#define ETH_MACHT0R_HTH_Pos                           (0U)
+#define ETH_MACHT0R_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT0R_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/************  Bit definition for Ethernet MAC Hash Table 1 register  ***************/
+#define ETH_MACHT1R_HTL_Pos                           (0U)
+#define ETH_MACHT1R_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT1R_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/************  Bit definition for Ethernet MAC VLAN tag Control register  ***************/
+#define ETH_MACVTCR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTCR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTCR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTCR_EIVLRXS                            ETH_MACVTCR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTCR_EIVLS_Pos                          (28U)
+#define ETH_MACVTCR_EIVLS_Msk                          (0x3UL << ETH_MACVTCR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS                              ETH_MACVTCR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS                  ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS                 ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP                  ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTCR_ERIVLT_Msk                         (0x1UL << ETH_MACVTCR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTCR_ERIVLT                             ETH_MACVTCR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTCR_EDVLP_Pos                          (26U)
+#define ETH_MACVTCR_EDVLP_Msk                          (0x1UL << ETH_MACVTCR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTCR_EDVLP                              ETH_MACVTCR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTCR_VTHM_Pos                           (25U)
+#define ETH_MACVTCR_VTHM_Msk                           (0x1UL << ETH_MACVTCR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTCR_VTHM                               ETH_MACVTCR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTCR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTCR_EVLRXS_Msk                         (0x1UL << ETH_MACVTCR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTCR_EVLRXS                             ETH_MACVTCR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTCR_EVLS_Pos                           (21U)
+#define ETH_MACVTCR_EVLS_Msk                           (0x3UL << ETH_MACVTCR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS                               ETH_MACVTCR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTCR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS                   ETH_MACVTCR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS                  ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP                   ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTCR_DOVLTC_Msk                         (0x1UL << ETH_MACVTCR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTCR_DOVLTC                             ETH_MACVTCR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTCR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTCR_ERSVLM_Msk                         (0x1UL << ETH_MACVTCR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTCR_ERSVLM                             ETH_MACVTCR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTCR_ESVL_Pos                           (18U)
+#define ETH_MACVTCR_ESVL_Msk                           (0x1UL << ETH_MACVTCR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTCR_ESVL                               ETH_MACVTCR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTCR_VTIM_Pos                           (17U)
+#define ETH_MACVTCR_VTIM_Msk                           (0x1UL << ETH_MACVTCR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTCR_VTIM                               ETH_MACVTCR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTCR_ETV_Pos                            (16U)
+#define ETH_MACVTCR_ETV_Msk                            (0x1UL << ETH_MACVTCR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTCR_ETV                                ETH_MACVTCR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTCR_OFS_Pos                            (2U)
+#define ETH_MACVTCR_OFS_Msk                            (0x3UL << ETH_MACVTCR_OFS_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS                                ETH_MACVTCR_EVLS_Msk      /* Offset */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER0             ((uint32_t)0x00000000)   /* holds MAC VLAN Tag Filter0 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos) /*!< 0x00000004 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk /* holds MAC VLAN Tag Filter1 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos         (3U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos) /*!< 0x00000008 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk /* holds MAC VLAN Tag Filter2 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk         (0x3UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk /* holds MAC VLAN Tag Filter3 content */
+#define ETH_MACVTCR_CT_Pos                             (1U)
+#define ETH_MACVTCR_CT_Msk                             (0x1UL << ETH_MACVTCR_CT_Pos) /*!< 0x00000002 */
+#define ETH_MACVTCR_CT                                 ETH_MACVTCR_CT_Msk       /* Command Type */
+#define ETH_MACVTCR_OB_Pos                             (0U)
+#define ETH_MACVTCR_OB_Msk                             (0x1UL << ETH_MACVTCR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACVTCR_OB                                 ETH_MACVTCR_OB_Msk       /* Operation Busy */
+
+/************  Bit definition for Ethernet MAC VLAN tag data register  ***************/
+#define ETH_MACVTDR_DMACHN_Pos                        (25U)
+#define ETH_MACVTDR_DMACHN_Msk                        (0x1UL << ETH_MACVTDR_DMACHN_Pos) /*!< 0x02000000 */
+#define ETH_MACVTDR_DMACHN                            ETH_MACVTDR_DMACHN_Msk   /* DMA Channel Number */
+#define ETH_MACVTDR_DMACHEN_Pos                       (24U)
+#define ETH_MACVTDR_DMACHEN_Msk                       (0x1UL << ETH_MACVTDR_DMACHEN_Pos) /*!< 0x01000000 */
+#define ETH_MACVTDR_DMACHEN                           ETH_MACVTDR_DMACHEN_Msk   /* DMA Channel Number Enable */
+#define ETH_MACVTDR_ERIVLT_Pos                        (20U)
+#define ETH_MACVTDR_ERIVLT_Msk                        (0x1UL << ETH_MACVTDR_ERIVLT_Pos) /*!< 0x00100000 */
+#define ETH_MACVTDR_ERIVLT                            ETH_MACVTDR_ERIVLT_Msk   /* Enable Inner VLAN Tag Comparison */
+#define ETH_MACVTDR_ERSVLM_Pos                        (19U)
+#define ETH_MACVTDR_ERSVLM_Msk                        (0x1UL << ETH_MACVTDR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_ERSVLM                            ETH_MACVTDR_ERSVLM_Msk   /* Enable S-VLAN Match for received Frames */
+#define ETH_MACVTDR_DOVLTC_Pos                        (18U)
+#define ETH_MACVTDR_DOVLTC_Msk                        (0x1UL << ETH_MACVTDR_DOVLTC_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_DOVLTC                            ETH_MACVTDR_DOVLTC_Msk   /* Disable VLAN Type Comparison */
+#define ETH_MACVTDR_ETV_Pos                           (17U)
+#define ETH_MACVTDR_ETV_Msk                           (0x1UL << ETH_MACVTDR_ETV_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV                               ETH_MACVTDR_ETV_Msk   /* 12-bit or 16-bit VLAN comparison */
+#define ETH_MACVTDR_ETV_VLAN16B                       ((uint32_t)0x00000000)   /* 16-bit VLAN */
+#define ETH_MACVTDR_ETV_VLAN12B_Pos                   (17U)
+#define ETH_MACVTDR_ETV_VLAN12B_Msk                   (0x1UL << ETH_MACVTDR_ETV_VLAN12B_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV_VLAN12B                       ETH_MACVTDR_ETV_VLAN12B_Msk   /* 12-bit VLAN */
+#define ETH_MACVTDR_VEN_Pos                           (16U)
+#define ETH_MACVTDR_VEN_Msk                           (0x1UL << ETH_MACVTDR_VEN_Pos) /*!< 0x00010000 */
+#define ETH_MACVTDR_VEN                               ETH_MACVTDR_VEN_Msk   /* VLAN Tag Enable */
+#define ETH_MACVTDR_VID_Pos                           (0U)
+#define ETH_MACVTDR_VID_Msk                           (0xFFFFUL << ETH_MACVTDR_VID_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID                               ETH_MACVTDR_VID_Msk        /* VLAN Tag ID */
+#define ETH_MACVTDR_VID_12BIT_Msk                     (0xFFFU << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000FFF */
+#define ETH_MACVTDR_VID_12BIT                         ETH_MACVTDR_VID_12BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 12bit */
+#define ETH_MACVTDR_VID_16BIT_Msk                     (0xFFFFU << ETH_MACVTDR_VID_Pos)                    /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID_16BIT                         ETH_MACVTDR_VID_16BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 16bit */
+#define ETH_MACVTDR_VID_0                             (0x1U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000001 */
+#define ETH_MACVTDR_VID_1                             (0x2U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000002 */
+#define ETH_MACVTDR_VID_2                             (0x4U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000004 */
+#define ETH_MACVTDR_VID_3                             (0x8U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000008 */
+#define ETH_MACVTDR_VID_4                             (0x10U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000010 */
+#define ETH_MACVTDR_VID_5                             (0x20U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000020 */
+#define ETH_MACVTDR_VID_6                             (0x40U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000040 */
+#define ETH_MACVTDR_VID_7                             (0x80U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000080 */
+#define ETH_MACVTDR_VID_8                             (0x100U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000100 */
+#define ETH_MACVTDR_VID_9                             (0x200U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000200 */
+#define ETH_MACVTDR_VID_10                            (0x400U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000400 */
+#define ETH_MACVTDR_VID_11                            (0x800U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000800 */
+#define ETH_MACVTDR_VID_12                            (0x1000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00001000 */
+#define ETH_MACVTDR_VID_13                            (0x2000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00002000 */
+#define ETH_MACVTDR_VID_14                            (0x4000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00004000 */
+#define ETH_MACVTDR_VID_15                            (0x8000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00008000 */
+
+/************  Bit definition for Ethernet MAC VLAN Hash Table Register  ***************/
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/************  Bit definition for Ethernet MAC VLAN inclusion Register  ***************/
+#define ETH_MACVIR_BUSY_Pos                           (31U)
+#define ETH_MACVIR_BUSY_Msk                           (0x1UL << ETH_MACVIR_BUSY_Pos) /*!< 0x80000000 */
+#define ETH_MACVIR_BUSY                               ETH_MACVIR_BUSY_Msk      /* Busy */
+#define ETH_MACVIR_RDWR_Pos                           (30U)
+#define ETH_MACVIR_RDWR_Msk                           (0x1UL << ETH_MACVIR_RDWR_Pos) /*!< 0x40000000 */
+#define ETH_MACVIR_RDWR                               ETH_MACVIR_RDWR_Msk      /* Read write control */
+#define ETH_MACVIR_ADDR_Pos                           (24U)
+#define ETH_MACVIR_ADDR_Msk                           (0x1UL << ETH_MACVIR_ADDR_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR                               ETH_MACVIR_ADDR_Msk      /* Address */
+#define ETH_MACVIR_ADDR_VLANINSTXQ0                   ((uint32_t)0x00000000)   /* VLAN tag for insertion in the Transmit packets from Tx Queue 0 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Pos               (24U)
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Msk               (0x1UL << ETH_MACVIR_ADDR_VLANINSTXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1                   ETH_MACVIR_ADDR_VLANINSTXQ1_Msk   /* VLAN tag for insertion in the Transmit packets from Tx Queue 1 */
+#define ETH_MACVIR_CBTI_Pos                           (21U)
+#define ETH_MACVIR_CBTI_Msk                           (0x1UL << ETH_MACVIR_CBTI_Pos) /*!< 0x00200000 */
+#define ETH_MACVIR_CBTI                               ETH_MACVIR_CBTI_Msk      /* Channel based tag insertion */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Inner_VLAN Incl Register   ***************/
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Tx Queue 0 flow control Register   ***************/
+#define ETH_MACQ0TXFCR_PT_Pos                         (16U)
+#define ETH_MACQ0TXFCR_PT_Msk                         (0xFFFFUL << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACQ0TXFCR_PT                             ETH_MACQ0TXFCR_PT_Msk       /* Pause Time */
+#define ETH_MACQ0TXFCR_DZPQ_Pos                       (7U)
+#define ETH_MACQ0TXFCR_DZPQ_Msk                       (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACQ0TXFCR_DZPQ                           ETH_MACQ0TXFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACQ0TXFCR_PLT_Pos                        (4U)
+#define ETH_MACQ0TXFCR_PLT_Msk                        (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACQ0TXFCR_PLT                            ETH_MACQ0TXFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACQ0TXFCR_PLT_MINUS4                     ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Pos                (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACQ0TXFCR_PLT_MINUS28                    ETH_MACQ0TXFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Pos                (5U)
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACQ0TXFCR_PLT_MINUS36                    ETH_MACQ0TXFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Msk               (0x3UL << ETH_MACQ0TXFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACQ0TXFCR_PLT_MINUS144                   ETH_MACQ0TXFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Pos               (6U)
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Msk               (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACQ0TXFCR_PLT_MINUS256                   ETH_MACQ0TXFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Msk               (0x5UL << ETH_MACQ0TXFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACQ0TXFCR_PLT_MINUS512                   ETH_MACQ0TXFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACQ0TXFCR_TFE_Pos                        (1U)
+#define ETH_MACQ0TXFCR_TFE_Msk                        (0x1UL << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACQ0TXFCR_TFE                            ETH_MACQ0TXFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACQ0TXFCR_FCB_Pos                        (0U)
+#define ETH_MACQ0TXFCR_FCB_Msk                        (0x1UL << ETH_MACQ0TXFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACQ0TXFCR_FCB                            ETH_MACQ0TXFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/************ Bit definition for Ethernet MAC Rx flow control Register   ***************/
+#define ETH_MACRXFCR_UP_Pos                            (1U)
+#define ETH_MACRXFCR_UP_Msk                            (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRXFCR_UP                                ETH_MACRXFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRXFCR_RFE_Pos                           (0U)
+#define ETH_MACRXFCR_RFE_Msk                           (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXFCR_RFE                               ETH_MACRXFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/************ Bit definition for Ethernet MAC Rx Queue control Register  ***************/
+#define ETH_MACRXQCR_VFFQ_Pos                         (17U)
+#define ETH_MACRXQCR_VFFQ_Msk                         (0x1UL << ETH_MACRXQCR_VFFQ_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ                             ETH_MACRXQCR_VFFQ_Msk       /* VLAN Tag Filter Fail Packets Queue */
+#define ETH_MACRXQCR_VFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_VFFQ_Q1_Pos                      (17U)
+#define ETH_MACRXQCR_VFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_VFFQ_Q1_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ_Q1                          ETH_MACRXQCR_VFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_VFFQE_Pos                        (16U)
+#define ETH_MACRXQCR_VFFQE_Msk                        (0x1UL << ETH_MACRXQCR_VFFQE_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQCR_VFFQE                            ETH_MACRXQCR_VFFQE_Msk       /* VLAN Tag Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_MFFQ_Pos                         (9U)
+#define ETH_MACRXQCR_MFFQ_Msk                         (0x1UL << ETH_MACRXQCR_MFFQ_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ                             ETH_MACRXQCR_MFFQ_Msk       /* Multicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_MFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_MFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_MFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_MFFQ_Q1_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ_Q1                          ETH_MACRXQCR_MFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_MFFQE_Pos                        (8U)
+#define ETH_MACRXQCR_MFFQE_Msk                        (0x1UL << ETH_MACRXQCR_MFFQE_Pos) /*!< 0x00000100 */
+#define ETH_MACRXQCR_MFFQE                            ETH_MACRXQCR_MFFQE_Msk       /* Multicast Address Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_UFFQ_Pos                         (1U)
+#define ETH_MACRXQCR_UFFQ_Msk                         (0x1UL << ETH_MACRXQCR_UFFQ_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ                             ETH_MACRXQCR_UFFQ_Msk       /* Unicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_UFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_UFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_UFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_UFFQ_Q1_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ_Q1                          ETH_MACRXQCR_UFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_UFFQE_Pos                        (0U)
+#define ETH_MACRXQCR_UFFQE_Msk                        (0x1UL << ETH_MACRXQCR_UFFQE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQCR_UFFQE                            ETH_MACRXQCR_UFFQE_Msk       /* Unicast Address Filter Fail Packets Queuing Enable */
+
+/************ Bit definition for Ethernet MAC Rx queue control 0 Register   ***************/
+#define ETH_MACRXQC0R_RXQ1EN_Pos                      (2U)
+#define ETH_MACRXQC0R_RXQ1EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
+#define ETH_MACRXQC0R_RXQ1EN                          ETH_MACRXQC0R_RXQ1EN_Msk       /* Receive Queue 1 Enable */
+#define ETH_MACRXQC0R_RXQ1EN_NOT                      ((uint32_t)0x00000000)        /* Queue 1 Not enabled */
+#define ETH_MACRXQC0R_RXQ1EN_AV_Pos                   (2U)
+#define ETH_MACRXQC0R_RXQ1EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_AV_Pos) /*!< 0x00000004 */
+#define ETH_MACRXQC0R_RXQ1EN_AV                       ETH_MACRXQC0R_RXQ1EN_AV_Msk   /* Queue 1 enabled for AV */
+#define ETH_MACRXQC0R_RXQ1EN_GT_Pos                   (3U)
+#define ETH_MACRXQC0R_RXQ1EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_GT_Pos) /*!< 0x00000008 */
+#define ETH_MACRXQC0R_RXQ1EN_GT                       ETH_MACRXQC0R_RXQ1EN_GT_Msk   /* Queue 1 enabled for Generic traffic */
+#define ETH_MACRXQC0R_RXQ0EN_Pos                      (0U)
+#define ETH_MACRXQC0R_RXQ0EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
+#define ETH_MACRXQC0R_RXQ0EN                          ETH_MACRXQC0R_RXQ0EN_Msk       /* Receive Queue 0 Enable */
+#define ETH_MACRXQC0R_RXQ0EN_NOT                      ((uint32_t)0x00000000)        /* Queue 0 Not enabled */
+#define ETH_MACRXQC0R_RXQ0EN_AV_Pos                   (0U)
+#define ETH_MACRXQC0R_RXQ0EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_AV_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC0R_RXQ0EN_AV                       ETH_MACRXQC0R_RXQ0EN_AV_Msk   /* Queue 0 enabled for AV */
+#define ETH_MACRXQC0R_RXQ0EN_GT_Pos                   (1U)
+#define ETH_MACRXQC0R_RXQ0EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_GT_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQC0R_RXQ0EN_GT                       ETH_MACRXQC0R_RXQ0EN_GT_Msk   /* Queue 0 enabled for Generic traffic */
+
+/************ Bit definition for Ethernet MAC Rx queue control 1 Register   ***************/
+#define ETH_MACRXQC1R_TBRQE_Pos                       (29U)
+#define ETH_MACRXQC1R_TBRQE_Msk                       (0x1UL << ETH_MACRXQC1R_TBRQE_Pos) /*!< 0x20000000 */
+#define ETH_MACRXQC1R_TBRQE                           ETH_MACRXQC1R_TBRQE_Msk       /* Type Field Based Rx Queuing Enable */
+#define ETH_MACRXQC1R_OMCBCQ_Pos                      (28U)
+#define ETH_MACRXQC1R_OMCBCQ_Msk                      (0x1UL << ETH_MACRXQC1R_OMCBCQ_Pos) /*!< 0x10000000 */
+#define ETH_MACRXQC1R_OMCBCQ                          ETH_MACRXQC1R_OMCBCQ_Msk       /* Overriding MC-BC queue priority select */
+#define ETH_MACRXQC1R_FPRQ_Pos                        (24U)
+#define ETH_MACRXQC1R_FPRQ_Msk                        (0x7UL << ETH_MACRXQC1R_FPRQ_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_FPRQ                            ETH_MACRXQC1R_FPRQ_Msk       /* Frame Preemption Residue Queue */
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Pos                   (24U)
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_FPRQ_RXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACRXQC1R_FPRQ_RXQ1                       ETH_MACRXQC1R_FPRQ_RXQ1_Msk       /* Rx queue 1 */
+#define ETH_MACRXQC1R_TPQC_Pos                        (22U)
+#define ETH_MACRXQC1R_TPQC_Msk                        (0x3UL << ETH_MACRXQC1R_TPQC_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_TPQC                            ETH_MACRXQC1R_TPQC_Msk   /* Tagged PTP over Ethernet Packets Queuing Control */
+#define ETH_MACRXQC1R_TPQC_PTPGENVLANTAG              ((uint32_t)0x00000000)   /* VLAN tagged PTPoE packets are routed as generic VLAN tagged packet */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos             (22U)
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk             (0x1UL << ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos) /*!< 0x000400000 */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ                 ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk /* VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos           (23U)
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk           (0x1UL << ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos) /*!< 0x00080000 */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ               ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk /* VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ */
+#define ETH_MACRXQC1R_TACPQE_Pos                      (21U)
+#define ETH_MACRXQC1R_TACPQE_Msk                      (0x1UL << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
+#define ETH_MACRXQC1R_TACPQE                          ETH_MACRXQC1R_TACPQE_Msk       /* Tagged AV Control Packets Queuing Enable */
+#define ETH_MACRXQC1R_MCBCQEN_Pos                     (20U)
+#define ETH_MACRXQC1R_MCBCQEN_Msk                     (0x1UL << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
+#define ETH_MACRXQC1R_MCBCQEN                         ETH_MACRXQC1R_MCBCQEN_Msk     /* Multicast and Broadcast Queue Enable */
+#define ETH_MACRXQC1R_MCBCQ_Pos                       (16U)
+#define ETH_MACRXQC1R_MCBCQ_Msk                       (0x7UL << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
+#define ETH_MACRXQC1R_MCBCQ                           ETH_MACRXQC1R_MCBCQ_Msk       /* Multicast and Broadcast Queue */
+#define ETH_MACRXQC1R_MCBCQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Pos                  (16U)
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_MCBCQ_RXQ1_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1                      ETH_MACRXQC1R_MCBCQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_UPQ_Pos                         (12U)
+#define ETH_MACRXQC1R_UPQ_Msk                         (0x7UL << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
+#define ETH_MACRXQC1R_UPQ                             ETH_MACRXQC1R_UPQ_Msk       /* Untagged Packet Queue */
+#define ETH_MACRXQC1R_UPQ_RXQ0                        ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_UPQ_RXQ1_Pos                    (12U)
+#define ETH_MACRXQC1R_UPQ_RXQ1_Msk                    (0x1UL << ETH_MACRXQC1R_UPQ_RXQ1_Pos) /*!< 0x00001000 */
+#define ETH_MACRXQC1R_UPQ_RXQ1                        ETH_MACRXQC1R_UPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_PTPQ_Pos                        (4U)
+#define ETH_MACRXQC1R_PTPQ_Msk                        (0x7UL << ETH_MACRXQC1R_PTPQ_Pos) /*!< 0x00000070 */
+#define ETH_MACRXQC1R_PTPQ                            ETH_MACRXQC1R_PTPQ_Msk       /* PTP Packets Queue */
+#define ETH_MACRXQC1R_PTPQ_RXQ0                       ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Pos                   (4U)
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_PTPQ_RXQ1_Pos) /*!< 0x00000010 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1                       ETH_MACRXQC1R_PTPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_AVCPQ_Pos                       (0U)
+#define ETH_MACRXQC1R_AVCPQ_Msk                       (0x7UL << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
+#define ETH_MACRXQC1R_AVCPQ                           ETH_MACRXQC1R_AVCPQ_Msk       /* AV Untagged Control Packets Queue */
+#define ETH_MACRXQC1R_AVCPQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Pos                  (0U)
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_AVCPQ_RXQ1_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1                      ETH_MACRXQC1R_AVCPQ_RXQ1_Msk  /* Rx queue 1 */
+
+/************ Bit definition for Ethernet MAC Rx queue control 2 Register   ***************/
+#define ETH_MACRXQC2R_PSRQ1_Pos                       (8U)
+#define ETH_MACRXQC2R_PSRQ1_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
+#define ETH_MACRXQC2R_PSRQ1                           ETH_MACRXQC2R_PSRQ1_Msk       /* Priorities Selected in the Receive Queue 1 */
+#define ETH_MACRXQC2R_PSRQ0_Pos                       (0U)
+#define ETH_MACRXQC2R_PSRQ0_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
+#define ETH_MACRXQC2R_PSRQ0                           ETH_MACRXQC2R_PSRQ0_Msk       /* Priorities Selected in the Receive Queue 0 */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MFRIS_Pos                          (20U)
+#define ETH_MACISR_MFRIS_Msk                          (0x1UL << ETH_MACISR_MFRIS_Pos) /*!< 0x00100000 */
+#define ETH_MACISR_MFRIS                              ETH_MACISR_MFRIS_Msk   /* MMC FPE Receive Interrupt Status */
+#define ETH_MACISR_MFTIS_Pos                          (19U)
+#define ETH_MACISR_MFTIS_Msk                          (0x1UL << ETH_MACISR_MFTIS_Pos) /*!< 0x00080000 */
+#define ETH_MACISR_MFTIS                              ETH_MACISR_MFTIS_Msk   /* MMC FPE Transmit Interrupt Status */
+#define ETH_MACISR_MDIOIS_Pos                         (18U)
+#define ETH_MACISR_MDIOIS_Msk                         (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIS                             ETH_MACISR_MDIOIS_Msk   /* MDIO Interrupt Status*/
+#define ETH_MACISR_FPEIS_Pos                          (17U)
+#define ETH_MACISR_FPEIS_Msk                          (0x1UL << ETH_MACISR_FPEIS_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIS                              ETH_MACISR_FPEIS_Msk   /* Frame Preemption Interrupt Status */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+#define ETH_MACISR_RGSMIIIS_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIS_Msk                       (0x1UL << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIS                           ETH_MACISR_RGSMIIIS_Msk     /* RGMII Interrupt Status */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MDIOIE_Pos                         (18U)
+#define ETH_MACISR_MDIOIE_Msk                         (0x1UL << ETH_MACISR_MDIOIE_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIE                             ETH_MACISR_MDIOIE_Msk   /* Receive Interrupt Enable*/
+#define ETH_MACISR_FPEIE_Pos                          (17U)
+#define ETH_MACISR_FPEIE_Msk                          (0x1UL << ETH_MACISR_FPEIE_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIE                              ETH_MACISR_FPEIE_Msk   /* Frame Preemption Interrupt Enable */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+#define ETH_MACISR_RGSMIIIE_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIE_Msk                       (0x1UL << ETH_MACISR_RGSMIIIE_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIE                           ETH_MACISR_RGSMIIIE_Msk     /* RGMII Interrupt Enable */
+
+/************ Bit definition for Ethernet MAC Rx Tx Status Register   ***************/
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/************ Bit definition for Ethernet MAC PMT Control Status Register   ***************/
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/************ Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register   ***************/
+#define ETH_MACRWKPFR_MACRWKPFR_Pos                   (0U)
+#define ETH_MACRWKPFR_MACRWKPFR_Msk                   (0xFFFFFFFFUL << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWKPFR_MACRWKPFR                       ETH_MACRWKPFR_MACRWKPFR_Msk  /* Wake-up Packet filter register data */
+
+/************ Bit definition for Ethernet MAC LPI Control Status Register   ***************/
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLSEN_Pos                         (18U)
+#define ETH_MACLCSR_PLSEN_Msk                         (0x1UL << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
+#define ETH_MACLCSR_PLSEN                             ETH_MACLCSR_PLSEN_Msk      /* PHY Link Status Enable */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/************ Bit definition for Ethernet MAC LPI Timers Control Register   ***************/
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/************ Bit definition for Ethernet MAC LPI Entry Timer Register   ***************/
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/************ Bit definition for Ethernet MAC 1US Tic Counter Register   ***************/
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/************ Bit definition for Ethernet MAC PHYIF control status Register   ***************/
+#define ETH_MACPHYCSR_LNKSTS_Pos                      (19U)
+#define ETH_MACPHYCSR_LNKSTS_Msk                      (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS                          ETH_MACPHYCSR_LNKSTS_Msk  /* Link Status */
+#define ETH_MACPHYCSR_LNKSTS_LD                       ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LNKSTS_LU_Pos                   (19U)
+#define ETH_MACPHYCSR_LNKSTS_LU_Msk                   (0x1UL << ETH_MACPHYCSR_LNKSTS_LU_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS_LU                       ETH_MACPHYCSR_LNKSTS_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_LNKSPEED_Pos                    (17U)
+#define ETH_MACPHYCSR_LNKSPEED_Msk                    (0x3UL << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
+#define ETH_MACPHYCSR_LNKSPEED                        ETH_MACPHYCSR_LNKSPEED_Msk  /* Link Speed */
+#define ETH_MACPHYCSR_LNKSPEED_2_5MHZ                 ((uint32_t)0x00000000)    /* 2.5 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos              (17U)
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk              (0x1UL << ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos) /*!< 0x00020000 */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ                  ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk   /* 25 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos             (18U)
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk             (0x1UL << ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos) /*!< 0x00040000 */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ                 ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk  /* 125 MHz */
+#define ETH_MACPHYCSR_LNKMOD_Pos                      (16U)
+#define ETH_MACPHYCSR_LNKMOD_Msk                      (0x1UL << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKMOD                          ETH_MACPHYCSR_LNKMOD_Msk  /* Link Mode */
+#define ETH_MACPHYCSR_LNKMOD_HD                       ((uint32_t)0x00000000)    /* Half-duplex mode */
+#define ETH_MACPHYCSR_LNKMOD_FD_Pos                   (16U)
+#define ETH_MACPHYCSR_LNKMOD_FD_Msk                   (0x1UL << ETH_MACPHYCSR_LNKMOD_FD_Pos) /*!< 0x00010000 */
+#define ETH_MACPHYCSR_LNKMOD_FD                       ETH_MACPHYCSR_LNKMOD_FD_Msk  /* Full-duplex mode */
+#define ETH_MACPHYCSR_LUD_Pos                         (1U)
+#define ETH_MACPHYCSR_LUD_Msk                         (0x1UL << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD                             ETH_MACPHYCSR_LUD_Msk  /* Link Up or Down */
+#define ETH_MACPHYCSR_LUD_LD                          ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LUD_LU_Pos                      (1U)
+#define ETH_MACPHYCSR_LUD_LU_Msk                      (0x1UL << ETH_MACPHYCSR_LUD_LU_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD_LU                          ETH_MACPHYCSR_LUD_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_TC_Pos                          (0U)
+#define ETH_MACPHYCSR_TC_Msk                          (0x1UL << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
+#define ETH_MACPHYCSR_TC                              ETH_MACPHYCSR_TC_Msk  /* Transmit Configuration in RGMII */
+
+/************ Bit definition for Ethernet MAC Version Register   ***************/
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/************ Bit definition for Ethernet MAC Debug Register   ***************/
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/************ Bit definition for Ethernet MAC HW Feature 0 Register   ***************/
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos              (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII                  ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk /* RGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos              (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII                  ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Pos                (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Msk                (0x3UL << ETH_MACHWF0R_ACTPHYSEL_TBI_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI                    ETH_MACHWF0R_ACTPHYSEL_TBI_Msk /* TBI */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos               (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk               (0x5UL << ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos) /*!< 0x50000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI                   ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk /* RTBI */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Pos               (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Msk               (0x3UL << ETH_MACHWF0R_ACTPHYSEL_SMII_Pos) /*!< 0x60000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII                   ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/************ Bit definition for Ethernet MAC HW Feature 1 Register   ***************/
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_HASHTBLSZ_NOHASH                 ((uint32_t)0x00000000)   /* No Hash table */
+#define ETH_MACHWF1R_HASHTBLSZ_64_Pos                 (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_64_Msk                 (0x1UL << ETH_MACHWF1R_HASHTBLSZ_64_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_64                     ETH_MACHWF1R_HASHTBLSZ_64_Msk /* 64 */
+#define ETH_MACHWF1R_HASHTBLSZ_128_Pos                (25U)
+#define ETH_MACHWF1R_HASHTBLSZ_128_Msk                (0x1UL << ETH_MACHWF1R_HASHTBLSZ_128_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_128                    ETH_MACHWF1R_HASHTBLSZ_128_Msk /* 128 */
+#define ETH_MACHWF1R_HASHTBLSZ_256_Pos                (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_256_Msk                (0x3UL << ETH_MACHWF1R_HASHTBLSZ_256_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_256                    ETH_MACHWF1R_HASHTBLSZ_256_Msk /* 256 */
+#define ETH_MACHWF1R_POUOST_Pos                       (23U)
+#define ETH_MACHWF1R_POUOST_Msk                       (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_POUOST                           ETH_MACHWF1R_POUOST_Msk   /* One Step for PTP over UDP/IP Feature Enable */
+#define ETH_MACHWF1R_RAVSEL_Pos                       (21U)
+#define ETH_MACHWF1R_RAVSEL_Msk                       (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_RAVSEL                           ETH_MACHWF1R_RAVSEL_Msk   /* Rx Side Only AV Feature Enable */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_SPRAM_Pos                        (5U)
+#define ETH_MACHWF1R_SPRAM_Msk                        (0x1FUL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF1R_SPRAM                            ETH_MACHWF1R_SPRAM_Msk /* MTL Receive FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/************ Bit definition for Ethernet MAC HW Feature 2 Register   ***************/
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TDCSZ_Pos                        (22U)
+#define ETH_MACHWF2R_TDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_TDCSZ                            ETH_MACHWF2R_TDCSZ_Msk /* Tx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_TXCHCNT_1DMATXCH                 ((uint32_t)0x00000000) /* 1 DMA Tx Channel */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos             (18U)
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk             (0x1UL << ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH                 ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk  /* 2 DMA Tx Channels */
+#define ETH_MACHWF2R_RDCSZ_Pos                        (16U)
+#define ETH_MACHWF2R_RDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_RDCSZ                            ETH_MACHWF2R_RDCSZ_Msk /* Rx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (12U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_RXCHCNT_1DMARXCH                 ((uint32_t)0x00000000) /* 1 DMA Rx Channel */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos             (12U)
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk             (0x1UL << ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH                 ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk  /* 2 DMA Rx Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_TXQCNT_1MTLTXQ                   ((uint32_t)0x00000000) /* 1 MTL Tx queue */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos               (6U)
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk               (0x1UL << ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ                   ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk  /* 2 MTL Tx queue */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+#define ETH_MACHWF2R_RXQCNT_1MTLRXQ                   ((uint32_t)0x00000000) /* 1 MTL Rx queue */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos               (0U)
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk               (0x1UL << ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ                   ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk  /* 2 MTL Rx queue */
+
+/************ Bit definition for Ethernet MAC HW Feature 3 Register    ***************/
+#define ETH_MACHWF3R_ASP_Pos                          (28U)
+#define ETH_MACHWF3R_ASP_Msk                          (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP                              ETH_MACHWF3R_ASP_Msk /* Automotive Safety Package */
+#define ETH_MACHWF3R_ASP_NONE                         ((uint32_t)0x00000000) /* None */
+#define ETH_MACHWF3R_ASP_ECC_Pos                      (28U)
+#define ETH_MACHWF3R_ASP_ECC_Msk                      (0x1UL << ETH_MACHWF3R_ASP_ECC_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF3R_ASP_ECC                          ETH_MACHWF3R_ASP_ECC_Msk  /* ECC only */
+#define ETH_MACHWF3R_ASP_ASNPPE_Pos                   (29U)
+#define ETH_MACHWF3R_ASP_ASNPPE_Msk                   (0x1UL << ETH_MACHWF3R_ASP_ASNPPE_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF3R_ASP_ASNPPE                       ETH_MACHWF3R_ASP_ASNPPE_Msk  /* AS_NPPE */
+#define ETH_MACHWF3R_ASP_ASPPE_Pos                    (28U)
+#define ETH_MACHWF3R_ASP_ASPPE_Msk                    (0x3UL << ETH_MACHWF3R_ASP_ASPPE_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP_ASPPE                        ETH_MACHWF3R_ASP_ASPPE_Msk  /* AS_PPE */
+#define ETH_MACHWF3R_TBSSEL_Pos                       (27U)
+#define ETH_MACHWF3R_TBSSEL_Msk                       (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF3R_TBSSEL                           ETH_MACHWF3R_TBSSEL_Msk /* Time-based scheduling Enable */
+#define ETH_MACHWF3R_FPESEL_Pos                       (26U)
+#define ETH_MACHWF3R_FPESEL_Msk                       (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF3R_FPESEL                           ETH_MACHWF3R_FPESEL_Msk /* Frame Preemption Enable */
+#define ETH_MACHWF3R_ESTWID_Pos                       (20U)
+#define ETH_MACHWF3R_ESTWID_Msk                       (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID                           ETH_MACHWF3R_ESTWID_Msk /* Width of the Time Interval field in the Gate Control List */
+#define ETH_MACHWF3R_ESTWID_NOWIDTH                   ((uint32_t)0x00000000) /* No Width */
+#define ETH_MACHWF3R_ESTWID_16_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_16_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_16_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF3R_ESTWID_16                        ETH_MACHWF3R_ESTWID_16_Msk  /* 16 Width */
+#define ETH_MACHWF3R_ESTWID_20_Pos                    (21U)
+#define ETH_MACHWF3R_ESTWID_20_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_20_Pos) /*!< 0x00200000 */
+#define ETH_MACHWF3R_ESTWID_20                        ETH_MACHWF3R_ESTWID_20_Msk  /* 20 Width */
+#define ETH_MACHWF3R_ESTWID_24_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_24_Msk                    (0x3UL << ETH_MACHWF3R_ESTWID_24_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID_24                        ETH_MACHWF3R_ESTWID_24_Msk  /* 24 Width */
+#define ETH_MACHWF3R_ESTDEP_Pos                       (17U)
+#define ETH_MACHWF3R_ESTDEP_Msk                       (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */
+#define ETH_MACHWF3R_ESTDEP                           ETH_MACHWF3R_ESTDEP_Msk /* Depth of the Gate Control List */
+#define ETH_MACHWF3R_ESTDEP_NODEPTH                   ((uint32_t)0x00000000) /* No depth */
+#define ETH_MACHWF3R_ESTDEP_64_Pos                    (17U)
+#define ETH_MACHWF3R_ESTDEP_64_Msk                    (0x1UL << ETH_MACHWF3R_ESTDEP_64_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF3R_ESTDEP_64                        ETH_MACHWF3R_ESTDEP_64_Msk  /* 64 depth */
+#define ETH_MACHWF3R_ESTDEP_128_Pos                   (18U)
+#define ETH_MACHWF3R_ESTDEP_128_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_128_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF3R_ESTDEP_128                       ETH_MACHWF3R_ESTDEP_128_Msk  /* 128 depth */
+#define ETH_MACHWF3R_ESTDEP_256_Pos                   (17U)
+#define ETH_MACHWF3R_ESTDEP_256_Msk                   (0x3UL << ETH_MACHWF3R_ESTDEP_256_Pos) /*!< 0x00060000 */
+#define ETH_MACHWF3R_ESTDEP_256                       ETH_MACHWF3R_ESTDEP_256_Msk  /* 256 depth */
+#define ETH_MACHWF3R_ESTDEP_512_Pos                   (19U)
+#define ETH_MACHWF3R_ESTDEP_512_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_512_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF3R_ESTDEP_512                       ETH_MACHWF3R_ESTDEP_512_Msk  /* 512 depth */
+#define ETH_MACHWF3R_ESTDEP_1024_Pos                  (17U)
+#define ETH_MACHWF3R_ESTDEP_1024_Msk                  (0x5UL << ETH_MACHWF3R_ESTDEP_1024_Pos) /*!< 0x000A0000 */
+#define ETH_MACHWF3R_ESTDEP_1024                      ETH_MACHWF3R_ESTDEP_1024_Msk  /* 1024 depth */
+#define ETH_MACHWF3R_ESTSEL_Pos                       (16U)
+#define ETH_MACHWF3R_ESTSEL_Msk                       (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF3R_ESTSEL                           ETH_MACHWF3R_ESTSEL_Msk  /* Enhancements to Scheduled Traffic Enable */
+#define ETH_MACHWF3R_FRPES_Pos                        (13U)
+#define ETH_MACHWF3R_FRPES_Msk                        (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */
+#define ETH_MACHWF3R_FRPES                            ETH_MACHWF3R_FRPES_Msk  /* Flexible Receive Parser Table Entries size */
+#define ETH_MACHWF3R_FRPES_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPES_128_Pos                    (13U)
+#define ETH_MACHWF3R_FRPES_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_128_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF3R_FRPES_128                        ETH_MACHWF3R_FRPES_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPES_256_Pos                    (14U)
+#define ETH_MACHWF3R_FRPES_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_256_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF3R_FRPES_256                        ETH_MACHWF3R_FRPES_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPBS_Pos                        (11U)
+#define ETH_MACHWF3R_FRPBS_Msk                        (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */
+#define ETH_MACHWF3R_FRPBS                            ETH_MACHWF3R_FRPBS_Msk  /* Flexible Receive Parser Buffer size */
+#define ETH_MACHWF3R_FRPBS_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPBS_128_Pos                    (11U)
+#define ETH_MACHWF3R_FRPBS_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_128_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF3R_FRPBS_128                        ETH_MACHWF3R_FRPBS_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPBS_256_Pos                    (12U)
+#define ETH_MACHWF3R_FRPBS_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_256_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF3R_FRPBS_256                        ETH_MACHWF3R_FRPBS_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPSEL_Pos                       (10U)
+#define ETH_MACHWF3R_FRPSEL_Msk                       (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */
+#define ETH_MACHWF3R_FRPSEL                           ETH_MACHWF3R_FRPSEL_Msk  /* Flexible Receive Parser Selected */
+#define ETH_MACHWF3R_PDUPSEL_Pos                      (9U)
+#define ETH_MACHWF3R_PDUPSEL_Msk                      (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF3R_PDUPSEL                          ETH_MACHWF3R_PDUPSEL_Msk  /* Broadcast/Multicast Packet Duplication */
+#define ETH_MACHWF3R_DVLAN_Pos                        (5U)
+#define ETH_MACHWF3R_DVLAN_Msk                        (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF3R_DVLAN                            ETH_MACHWF3R_DVLAN_Msk  /* Double VLAN processing enable */
+#define ETH_MACHWF3R_CBTISEL_Pos                      (4U)
+#define ETH_MACHWF3R_CBTISEL_Msk                      (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF3R_CBTISEL                          ETH_MACHWF3R_CBTISEL_Msk  /* Queue/Channel based VLAN tag insertion on Tx enable */
+#define ETH_MACHWF3R_NRVF_Pos                         (0U)
+#define ETH_MACHWF3R_NRVF_Msk                         (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */
+#define ETH_MACHWF3R_NRVF                             ETH_MACHWF3R_NRVF_Msk  /* Number of Extended VLAN Tag Filters Enabled */
+#define ETH_MACHWF3R_NRVF_NOEXRXVLANFLTR              ((uint32_t)0x00000000) /* No Extended Rx VLAN Filters */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos           (0U)
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR               ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos           (1U)
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR               ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk          (0x3UL << ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos) /*!< 0x00000003 */
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR              ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos          (2U)
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk          (0x1UL << ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR              ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk          (0x5UL << ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos) /*!< 0x00000005 */
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR              ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk
+
+/************ Bit definition for Ethernet MAC MDIO Address Register   ***************/
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV204_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV204_Msk                   (0x3UL << ETH_MACMDIOAR_CR_DIV204_Pos) /*!< 0x00000600 */
+#define ETH_MACMDIOAR_CR_DIV204                       ETH_MACMDIOAR_CR_DIV204_Msk /* CSR clock/204 */
+#define ETH_MACMDIOAR_CR_DIV324_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV324_Msk                   (0x7UL << ETH_MACMDIOAR_CR_DIV324_Pos) /*!< 0x00000700 */
+#define ETH_MACMDIOAR_CR_DIV324                       ETH_MACMDIOAR_CR_DIV324_Msk /* CSR clock/304 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_GOC_Pos                         (2U)
+#define ETH_MACMDIOAR_GOC_Msk                         (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_GOC_0                           (0x1U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000004 */
+#define ETH_MACMDIOAR_GOC_1                           (0x2U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000008 */
+#define ETH_MACMDIOAR_GOC                             ETH_MACMDIOAR_GOC_Msk    /* GMII Operation Command */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_GB_Pos                          (0U)
+#define ETH_MACMDIOAR_GB_Msk                          (0x1UL << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_GB                              ETH_MACMDIOAR_GB_Msk     /* GMII Busy */
+
+/************ Bit definition for Ethernet MAC MDIO Data Register   ***************/
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_GD_Pos                          (0U)
+#define ETH_MACMDIODR_GD_Msk                          (0xFFFFUL << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_GD                              ETH_MACMDIODR_GD_Msk     /* GMII Data */
+
+/************ Bit definition for Ethernet ARP Address Register    ***************/
+#define ETH_MACARPAR_ARPPA_Pos                        (0U)
+#define ETH_MACARPAR_ARPPA_Msk                        (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                            ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/************ Bit definition for Ethernet MAC CSR software control Register   ***************/
+#define ETH_MACCSRSWCR_SEEN_Pos                       (8U)
+#define ETH_MACCSRSWCR_SEEN_Msk                       (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */
+#define ETH_MACCSRSWCR_SEEN                           ETH_MACCSRSWCR_SEEN_Msk /* Slave Error Response Enable */
+#define ETH_MACCSRSWCR_RCWE_Pos                       (0U)
+#define ETH_MACCSRSWCR_RCWE_Msk                       (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */
+#define ETH_MACCSRSWCR_RCWE                           ETH_MACCSRSWCR_RCWE_Msk /* Register Clear on Write 1 Enable */
+
+/************ Bit definition for Ethernet MAC FPE control and status Register   ***************/
+#define ETH_MACFPECSR_TRSP_Pos                        (19U)
+#define ETH_MACFPECSR_TRSP_Msk                        (0x1UL << ETH_MACFPECSR_TRSP_Pos) /*!< 0x00080000 */
+#define ETH_MACFPECSR_TRSP                            ETH_MACFPECSR_TRSP_Msk /* Transmitted Respond Frame */
+#define ETH_MACFPECSR_TVER_Pos                        (18U)
+#define ETH_MACFPECSR_TVER_Msk                        (0x1UL << ETH_MACFPECSR_TVER_Pos) /*!< 0x00040000 */
+#define ETH_MACFPECSR_TVER                            ETH_MACFPECSR_TVER_Msk /* Transmitted Verify Frame */
+#define ETH_MACFPECSR_RRSP_Pos                        (17U)
+#define ETH_MACFPECSR_RRSP_Msk                        (0x1UL << ETH_MACFPECSR_RRSP_Pos) /*!< 0x00020000 */
+#define ETH_MACFPECSR_RRSP                            ETH_MACFPECSR_RRSP_Msk /* Received Respond Frame */
+#define ETH_MACFPECSR_RVER_Pos                        (16U)
+#define ETH_MACFPECSR_RVER_Msk                        (0x1UL << ETH_MACFPECSR_RVER_Pos) /*!< 0x00010000 */
+#define ETH_MACFPECSR_RVER                            ETH_MACFPECSR_RVER_Msk /* Received Verify Frame */
+#define ETH_MACFPECSR_SRSP_Pos                        (2U)
+#define ETH_MACFPECSR_SRSP_Msk                        (0x1UL << ETH_MACFPECSR_SRSP_Pos) /*!< 0x00000004 */
+#define ETH_MACFPECSR_SRSP                            ETH_MACFPECSR_SRSP_Msk /* Send Respond mPacket */
+#define ETH_MACFPECSR_SVER_Pos                        (1U)
+#define ETH_MACFPECSR_SVER_Msk                        (0x1UL << ETH_MACFPECSR_SVER_Pos) /*!< 0x00000002 */
+#define ETH_MACFPECSR_SVER                            ETH_MACFPECSR_SVER_Msk /* Send Verify mPacket */
+#define ETH_MACFPECSR_EFPE_Pos                        (0U)
+#define ETH_MACFPECSR_EFPE_Msk                        (0x1UL << ETH_MACFPECSR_EFPE_Pos) /*!< 0x00000001 */
+#define ETH_MACFPECSR_EFPE                            ETH_MACFPECSR_EFPE_Msk /* Enable Tx Frame Preemption */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMR_MPTN_Pos                        (0U)
+#define ETH_MACPRSTIMR_MPTN_Msk                        (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMR_MPTN                            ETH_MACPRSTIMR_MPTN_Msk /* MAC 1722 Presentation Time in ns */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMUR_MPTU_Pos                       (0U)
+#define ETH_MACPRSTIMUR_MPTU_Msk                       (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMUR_MPTU                           ETH_MACPRSTIMUR_MPTU_Msk /* MAC 1722 Presentation Time Update */
+
+/************ Bit definition for Ethernet MAC Address 0 High Register   ***************/
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_DCS_Pos                           (16U)
+#define ETH_MACA0HR_DCS_Msk                           (0x1UL << ETH_MACA0HR_DCS_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_DCS                               ETH_MACA0HR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/************ Bit definition for Ethernet MAC Address x Low Register   ***************/
+#define ETH_MACAxLR_ADDRLO_Pos                        (0U)
+#define ETH_MACAxLR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACAxLR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACAxLR_ADDRLO                            ETH_MACAxLR_ADDRLO_Msk   /* MAC Address x*/
+
+/************ Bit definition for Ethernet MAC Address x High Register  ***************/
+#define ETH_MACAxHR_AE_Pos                            (31U)
+#define ETH_MACAxHR_AE_Msk                            (0x1UL << ETH_MACAxHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAxHR_AE                                ETH_MACAxHR_AE_Msk /* Address Enable*/
+#define ETH_MACAxHR_SA_Pos                            (30U)
+#define ETH_MACAxHR_SA_Msk                            (0x1UL << ETH_MACAxHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAxHR_SA                                ETH_MACAxHR_SA_Msk /* Source Address */
+#define ETH_MACAxHR_MBC_Pos                           (24U)
+#define ETH_MACAxHR_MBC_Msk                           (0x3FUL << ETH_MACAxHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAxHR_MBC                               ETH_MACAxHR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACAxHR_DCS_Pos                           (16U)
+#define ETH_MACAxHR_DCS_Msk                           (0x1UL << ETH_MACAxHR_DCS_Pos) /*!< 0x00010000 */
+#define ETH_MACAxHR_DCS                               ETH_MACAxHR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACAxHR_ADDRHI_Pos                        (0U)
+#define ETH_MACAxHR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACAxHR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAxHR_ADDRHI                            ETH_MACAxHR_ADDRHI_Msk   /* MAC Address 1*/
+
+/************ Bit definition for Ethernet MMC Control Register   ***************/
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/************ Bit definition for Ethernet MMC Rx Interrupt Register  ***************/
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Register   ***************/
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Rx interrupt Mask Register   ***************/
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Mask Register   ***************/
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Single Collision Good Packets Register   ***************/
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register   ***************/
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Packet Count Good Register  ***************/
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/************ Bit definition for Ethernet MMC Rx CRC Error Packets Register  ***************/
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx alignment error packets Register   ***************/
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx Unicast Packets Good Register   ***************/
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/************ Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register   ***************/
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Tx LPI Transition Counter Register   ***************/
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register   ***************/
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Transition Counter Register   ***************/
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt status Register   ***************/
+#define ETH_MMCFPETISR_HRCIS_Pos                      (1U)
+#define ETH_MMCFPETISR_HRCIS_msk                      (0x1UL <<  ETH_MMCFPETISR_HRCIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETISR_HRCIS                          ETH_MMCFPETISR_HRCIS_msk /* MMC Tx Hold Request Counter Interrupt Status */
+#define ETH_MMCFPETISR_FCIS_Pos                       (0U)
+#define ETH_MMCFPETISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPETISR_FCIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETISR_FCIS                           ETH_MMCFPETISR_FCIS_msk /* MMC Tx FPE Fragment Counter Interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt mask Register   ***************/
+#define ETH_MMCFPETIMR_HRCIM_Pos                      (1U)
+#define ETH_MMCFPETIMR_HRCIM_msk                      (0x1UL <<  ETH_MMCFPETIMR_HRCIM_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETIMR_HRCIM                          ETH_MMCFPETIMR_HRCIM_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+#define ETH_MMCFPETIMR_FCIM_Pos                       (0U)
+#define ETH_MMCFPETIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPETIMR_FCIM_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETIMR_FCIM                           ETH_MMCFPETIMR_FCIM_msk /* MMC Transmit Fragment Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC FPE Tx fragment counter Register   ***************/
+#define ETH_MMCFPETFCR_TXFFC_Pos                      (0U)
+#define ETH_MMCFPETFCR_TXFFC_msk                      (0xFFFFFFFFUL <<  ETH_MMCFPETFCR_TXFFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPETFCR_TXFFC                          ETH_MMCFPETFCR_TXFFC_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx hold request counter Register   ***************/
+#define ETH_MMCTHRCR_TXHRC_Pos                        (0U)
+#define ETH_MMCTHRCR_TXHRC_msk                        (0xFFFFFFFFUL <<  ETH_MMCTHRCR_TXHRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTHRCR_TXHRC                            ETH_MMCTHRCR_TXHRC_msk /* Tx hold request counter */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt status Register   ***************/
+#define ETH_MMCFPERISR_FCIS_Pos                       (3U)
+#define ETH_MMCFPERISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPERISR_FCIS_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERISR_FCIS                           ETH_MMCFPERISR_FCIS_msk /* MMC Rx FPE Fragment Counter Interrupt Status */
+#define ETH_MMCFPERISR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERISR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERISR_PAOCIS                         ETH_MMCFPERISR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt status */
+#define ETH_MMCFPERISR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERISR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERISR_PSECIS                         ETH_MMCFPERISR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt status */
+#define ETH_MMCFPERISR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERISR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERISR_PAECIS                         ETH_MMCFPERISR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt mask Register   ***************/
+#define ETH_MMCFPERIMR_FCIM_Pos                       (3U)
+#define ETH_MMCFPERIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPERIMR_FCIM_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERIMR_FCIM                           ETH_MMCFPERIMR_FCIM_msk /* MMC Rx FPE Fragment Counter Interrupt Mask */
+#define ETH_MMCFPERIMR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERIMR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERIMR_PAOCIS                         ETH_MMCFPERIMR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt Mask */
+#define ETH_MMCFPERIMR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERIMR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERIMR_PSECIS                         ETH_MMCFPERIMR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt Mask */
+#define ETH_MMCFPERIMR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERIMR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERIMR_PAECIS                         ETH_MMCFPERIMR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly error Register   ***************/
+#define ETH_MMCRPAER_PAEC_Pos                         (0U)
+#define ETH_MMCRPAER_PAEC_msk                         (0xFFFFFFFFUL <<  ETH_MMCRPAER_PAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAER_PAEC                             ETH_MMCRPAER_PAEC_msk /* Rx Packet Assembly Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet SMD error Register   ***************/
+#define ETH_MMCRPSMDER_PSEC_Pos                       (0U)
+#define ETH_MMCRPSMDER_PSEC_msk                       (0xFFFFFFFFUL <<  ETH_MMCRPSMDER_PSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPSMDER_PSEC                           ETH_MMCRPSMDER_PSEC_msk /* Rx Packet SMD Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly OK Register   ***************/
+#define ETH_MMCRPAOKR_PAOC_Pos                        (0U)
+#define ETH_MMCRPAOKR_PAOC_msk                        (0xFFFFFFFFUL <<  ETH_MMCRPAOKR_PAOC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAOKR_PAOC                            ETH_MMCRPAOKR_PAOC_msk /* Rx Packet Assembly OK Counter */
+
+/************ Bit definition for Ethernet MMC Rx FPE fragments counter Register   ***************/
+#define ETH_MMCFPERFCR_FFC_Pos                        (0U)
+#define ETH_MMCFPERFCR_FFC_msk                        (0xFFFFFFFFUL <<  ETH_MMCFPERFCR_FFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPERFCR_FFC                            ETH_MMCFPERFCR_FFC_msk /* Rx FPE Fragment Counter */
+
+/************ Bit definition for Ethernet MAC L3 and L4 control 0 Register   ***************/
+#define ETH_MACL3L4C0R_DMCHEN0_Pos                     (28U)
+#define ETH_MACL3L4C0R_DMCHEN0_Msk                     (0x1UL << ETH_MACL3L4C0R_DMCHEN0_Pos) /*!< 0x10000000 */
+#define ETH_MACL3L4C0R_DMCHEN0                         ETH_MACL3L4C0R_DMCHEN0_Msk /* DMA Channel Select Enable */
+#define ETH_MACL3L4C0R_DMCHN0_Pos                      (24U)
+#define ETH_MACL3L4C0R_DMCHN0_Msk                      (0x1UL << ETH_MACL3L4C0R_DMCHN0_Pos) /*!< 0x01000000 */
+#define ETH_MACL3L4C0R_DMCHN0                          ETH_MACL3L4C0R_DMCHN0_Msk /* DMA Channel Number */
+#define ETH_MACL3L4C0R_L4DPIM0_Pos                     (21U)
+#define ETH_MACL3L4C0R_L4DPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4C0R_L4DPIM0                         ETH_MACL3L4C0R_L4DPIM0_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4DPM0_Pos                      (20U)
+#define ETH_MACL3L4C0R_L4DPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4C0R_L4DPM0                          ETH_MACL3L4C0R_L4DPM0_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4C0R_L4SPIM0_Pos                     (19U)
+#define ETH_MACL3L4C0R_L4SPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4C0R_L4SPIM0                         ETH_MACL3L4C0R_L4SPIM0_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4SPM0_Pos                      (18U)
+#define ETH_MACL3L4C0R_L4SPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4C0R_L4SPM0                          ETH_MACL3L4C0R_L4SPM0_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4C0R_L4PEN0_Pos                      (16U)
+#define ETH_MACL3L4C0R_L4PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4C0R_L4PEN0                          ETH_MACL3L4C0R_L4PEN0_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4C0R_L3HDBM0_Pos                     (11U)
+#define ETH_MACL3L4C0R_L3HDBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4C0R_L3HDBM0                         ETH_MACL3L4C0R_L3HDBM0_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3HSBM0_Pos                     (6U)
+#define ETH_MACL3L4C0R_L3HSBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4C0R_L3HSBM0                         ETH_MACL3L4C0R_L3HSBM0_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3DAIM0_Pos                     (5U)
+#define ETH_MACL3L4C0R_L3DAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4C0R_L3DAIM0                         ETH_MACL3L4C0R_L3DAIM0_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3DAM0_Pos                      (4U)
+#define ETH_MACL3L4C0R_L3DAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4C0R_L3DAM0                          ETH_MACL3L4C0R_L3DAM0_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4C0R_L3SAIM0_Pos                     (3U)
+#define ETH_MACL3L4C0R_L3SAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4C0R_L3SAIM0                         ETH_MACL3L4C0R_L3SAIM0_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3SAM0_Pos                      (2U)
+#define ETH_MACL3L4C0R_L3SAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4C0R_L3SAM0                          ETH_MACL3L4C0R_L3SAM0_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4C0R_L3PEN0_Pos                      (0U)
+#define ETH_MACL3L4C0R_L3PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4C0R_L3PEN0                          ETH_MACL3L4C0R_L3PEN0_Msk  /* Layer 3 Protocol Enable */
+
+/************ Bit definition for Ethernet MAC Layer4 Address filter Register   ***************/
+#define ETH_MACL4A0R_L4DP0_Pos                        (16U)
+#define ETH_MACL4A0R_L4DP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4A0R_L4DP0                            ETH_MACL4A0R_L4DP0_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4A0R_L4SP0_Pos                        (0U)
+#define ETH_MACL4A0R_L4SP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4A0R_L4SP0                            ETH_MACL4A0R_L4SP0_Msk     /* Layer 4 Source Port Number Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 0 Register   ***************/
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 1 Register   ***************/
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 2 Register   ***************/
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 3 Register   ***************/
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/************ Bit definition for Ethernet MAC Indirect Access Control Register   ***************/
+#define ETH_MACIACR_MSEL_Pos                           (16U)
+#define ETH_MACIACR_MSEL_Msk                           (0xFUL << ETH_MACIACR_MSEL_Pos) /*!< 0x000F0000 */
+#define ETH_MACIACR_MSEL                               ETH_MACIACR_MSEL_Msk    /* Mode Select */
+#define ETH_MACIACR_MSEL_RXQ                           ((uint32_t)0x00000000)   /* Type-based RXQ mapping */
+#define ETH_MACIACR_AOFF_Pos                           (8U)
+#define ETH_MACIACR_AOFF_Msk                           (0xFFUL << ETH_MACIACR_AOFF_Pos) /*!< 0x0000FF00 */
+#define ETH_MACIACR_AOFF                               ETH_MACIACR_AOFF_Msk    /* Address Offset */
+#define ETH_MACIACR_AOFF_IndReg0                       ((uint32_t)0x00000000)   /* Indirect register 0 */
+#define ETH_MACIACR_AOFF_IndReg1_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg1_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg1_Pos) /*!< 0x00000100 */
+#define ETH_MACIACR_AOFF_IndReg1                       ETH_MACIACR_AOFF_IndReg1_Msk  /* Indirect register 1 */
+#define ETH_MACIACR_AOFF_IndReg2_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg2_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg2_Pos) /*!< 0x00000200 */
+#define ETH_MACIACR_AOFF_IndReg2                       ETH_MACIACR_AOFF_IndReg2_Msk  /* Indirect register 2 */
+#define ETH_MACIACR_AOFF_IndReg3_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg3_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg3_Pos) /*!< 0x00000300 */
+#define ETH_MACIACR_AOFF_IndReg3                       ETH_MACIACR_AOFF_IndReg3_Msk  /* Indirect register 3 */
+#define ETH_MACIACR_AOFF_IndReg4_Pos                   (10U)
+#define ETH_MACIACR_AOFF_IndReg4_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg4_Pos) /*!< 0x00000400 */
+#define ETH_MACIACR_AOFF_IndReg4                       ETH_MACIACR_AOFF_IndReg4_Msk  /* Indirect register 4 */
+#define ETH_MACIACR_AOFF_IndReg5_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg5_Msk                   (0x5UL << ETH_MACIACR_AOFF_IndReg5_Pos) /*!< 0x00000500 */
+#define ETH_MACIACR_AOFF_IndReg5                       ETH_MACIACR_AOFF_IndReg5_Msk  /* Indirect register 5 */
+#define ETH_MACIACR_AOFF_IndReg6_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg6_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg6_Pos) /*!< 0x00000600 */
+#define ETH_MACIACR_AOFF_IndReg6                       ETH_MACIACR_AOFF_IndReg6_Msk  /* Indirect register 6 */
+#define ETH_MACIACR_AOFF_IndReg7_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg7_Msk                   (0x7UL << ETH_MACIACR_AOFF_IndReg7_Pos) /*!< 0x00000700 */
+#define ETH_MACIACR_AOFF_IndReg7                       ETH_MACIACR_AOFF_IndReg7_Msk  /* Indirect register 7 */
+#define ETH_MACIACR_AUTO_Pos                           (5U)
+#define ETH_MACIACR_AUTO_Msk                           (0x1UL << ETH_MACIACR_AUTO_Pos) /*!< 0x00000020 */
+#define ETH_MACIACR_AUTO                               ETH_MACIACR_AUTO_Msk    /* Auto-increment */
+#define ETH_MACIACR_COM_Pos                            (1U)
+#define ETH_MACIACR_COM_Msk                            (0x1UL << ETH_MACIACR_COM_Pos) /*!< 0x00000002 */
+#define ETH_MACIACR_COM                                ETH_MACIACR_COM_Msk    /* Command type: 1: read operation / 0: write operation */
+#define ETH_MACIACR_OB_Pos                             (0U)
+#define ETH_MACIACR_OB_Msk                             (0x1UL << ETH_MACIACR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACIACR_OB                                 ETH_MACIACR_OB_Msk    /* Operation Busy */
+
+/************ Bit definition for Ethernet MAC type-based Rx Queue mapping Register   ***************/
+#define ETH_MACTMRQR_PFEX_Pos                          (20U)
+#define ETH_MACTMRQR_PFEX_Msk                          (0x1UL << ETH_MACTMRQR_PFEX_Pos) /*!< 0x00100000 */
+#define ETH_MACTMRQR_PFEX                              ETH_MACTMRQR_PFEX_Msk    /* Preemption or Express Packet */
+#define ETH_MACTMRQR_TMRQ_Pos                          (16U)
+#define ETH_MACTMRQR_TMRQ_Msk                          (0x7UL << ETH_MACTMRQR_TMRQ_Pos) /*!< 0x00070000 */
+#define ETH_MACTMRQR_TMRQ                              ETH_MACTMRQR_TMRQ_Msk    /* Type Match Rx Queue Number */
+#define ETH_MACTMRQR_TYP_Pos                           (0U)
+#define ETH_MACTMRQR_TYP_Msk                           (0xFFFFUL << ETH_MACTMRQR_TYP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACTMRQR_TYP                               ETH_MACTMRQR_TYP_Msk    /* Type field Value */
+
+/************ Bit definition for Ethernet MAC Timestamp Control Register   ***************/
+#define ETH_MACTSCR_AV8021ASMEN_Pos                   (28U)
+#define ETH_MACTSCR_AV8021ASMEN_Msk                   (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
+#define ETH_MACTSCR_AV8021ASMEN                       ETH_MACTSCR_AV8021ASMEN_Msk  /* AV 802.1AS Mode Enable */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_ESTI_Pos                          (20U)
+#define ETH_MACTSCR_ESTI_Msk                          (0x1UL << ETH_MACTSCR_ESTI_Pos) /*!< 0x00100000 */
+#define ETH_MACTSCR_ESTI                              ETH_MACTSCR_ESTI_Msk  /* External System Time Input */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_PTGE_Pos                          (6U)
+#define ETH_MACTSCR_PTGE_Msk                          (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */
+#define ETH_MACTSCR_PTGE                              ETH_MACTSCR_PTGE_Msk  /* Presentation Time Generation Enable */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/************ Bit definition for Ethernet MAC Sub-second Increment Register   ***************/
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Register   ***************/
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Register   ***************/
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Update Register   ***************/
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Update Register   ***************/
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Addend Register   ***************/
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/************ Bit definition for Ethernet MAC Timestamp Status Register   ***************/
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR1_Pos                    (5U)
+#define ETH_MACTSSR_TSTRGTERR1_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR1_Pos) /*!< 0x00000020 */
+#define ETH_MACTSSR_TSTRGTERR1                        ETH_MACTSSR_TSTRGTERR1_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_TSTARGT1_Pos                      (4U)
+#define ETH_MACTSSR_TSTARGT1_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT1_Pos) /*!< 0x00000010 */
+#define ETH_MACTSSR_TSTARGT1                          ETH_MACTSSR_TSTARGT1_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register   ***************/
+#define ETH_MACTXTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTXTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTXTSSNR_TXTSSMIS                        ETH_MACTXTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTXTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTXTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTXTSSNR_TXTSSLO                         ETH_MACTXTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register   ***************/
+#define ETH_MACTXTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTXTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTXTSSSR_TXTSSHI                         ETH_MACTXTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/************ Bit definition for Ethernet MAC Auxiliary Control Register   ***************/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register   ***************/
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register   ***************/
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register   ***************/
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction  ***************/
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond   ***************/
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond   ***************/
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Latency   ***************/
+#define ETH_MACTSILR_ITLNS_Pos                        (16U)
+#define ETH_MACTSILR_ITLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSILR_ITLNS                            ETH_MACTSILR_ITLNS_Msk  /* Ingress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSILR_ITLSNS_Pos                       (8U)
+#define ETH_MACTSILR_ITLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSILR_ITLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Ingress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Latency Register   ***************/
+#define ETH_MACTSELR_ETLNS_Pos                        (16U)
+#define ETH_MACTSELR_ETLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSELR_ETLNS                            ETH_MACTSILR_ITLNS_Msk  /* Egress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSELR_ETLSNS_Pos                       (8U)
+#define ETH_MACTSELR_ETLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSELR_ETLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Egress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC PPS Control Register   ***************/
+#define ETH_MACPPSCR_TIMESEL_Pos                      (28U)
+#define ETH_MACPPSCR_TIMESEL_Msk                      (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSCR_TIMESEL                          ETH_MACPPSCR_TIMESEL_Msk  /* Time Select */
+#define ETH_MACPPSCR_MCGREN0_Pos                      (7U)
+#define ETH_MACPPSCR_MCGREN0_Msk                      (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0                          ETH_MACPPSCR_MCGREN0_Msk  /* MCGR Mode Enable for PPS0 Output */
+#define ETH_MACPPSCR_MCGREN0_PPS                      ((uint32_t)0x00000000)   /* PPS mode */
+#define ETH_MACPPSCR_MCGREN0_MCGR_Pos                 (7U)
+#define ETH_MACPPSCR_MCGREN0_MCGR_Msk                 (0x1UL << ETH_MACPPSCR_MCGREN0_MCGR_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0_MCGR                     ETH_MACPPSCR_MCGREN0_MCGR_Msk  /* MCGR mode */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/************ Bit definition for Ethernet MAC PPS x target time seconds Register   ***************/
+#define ETH_MACPPSTTSxR_TSTRH0_Pos                    (0U)
+#define ETH_MACPPSTTSxR_TSTRH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSTTSxR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSxR_TSTRH0                        ETH_MACPPSTTSxR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/************ Bit definition for Ethernet MAC PPS x target time nanoseconds Register   ***************/
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Pos                 (31U)
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Msk                 (0x1UL << ETH_MACPPSTTNxR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNxR_TRGTBUSY0                     ETH_MACPPSTTNxR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNxR_TTSL0_Pos                     (0U)
+#define ETH_MACPPSTTNxR_TTSL0_Msk                     (0x7FFFFFFFUL << ETH_MACPPSTTNxR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNxR_TTSL0                         ETH_MACPPSTTNxR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/************ Bit definition for Ethernet MAC PPS x Interval Register   ***************/
+#define ETH_MACPPSIxR_PPSINT0_Pos                     (0U)
+#define ETH_MACPPSIxR_PPSINT0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSIxR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIxR_PPSINT0                         ETH_MACPPSIxR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/************ Bit definition for Ethernet MAC PPS x Width Register   ***************/
+#define ETH_MACPPSWxR_PPSWIDTH0_Pos                   (0U)
+#define ETH_MACPPSWxR_PPSWIDTH0_Msk                   (0xFFFFFFFFUL << ETH_MACPPSWxR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWxR_PPSWIDTH0                       ETH_MACPPSWxR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/************ Bit definition for Ethernet MAC PTP Offload Control Register   ***************/
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_PDRDIS_Pos                        (7U)
+#define ETH_MACPOCR_PDRDIS_Msk                        (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */
+#define ETH_MACPOCR_PDRDIS                            ETH_MACPOCR_PDRDIS_Msk  /* Disable Peer Delay Response response generation */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 0 Register   ***************/
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 1 Register   ***************/
+#define ETH_MACSPI1R_SPI1_Pos                        (0U)
+#define ETH_MACSPI1R_SPI1_Msk                        (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                            ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 2 Register   ***************/
+#define ETH_MACSPI2R_SPI2_Pos                        (0U)
+#define ETH_MACSPI2R_SPI2_Msk                        (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                            ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/************ Bit definition for Ethernet MAC Log Message Interval Register   ***************/
+#define ETH_MACLMIR_LMPDRI_Pos                       (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                       (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                            ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                      (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                      (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                          ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                          (0U)
+#define ETH_MACLMIR_LSI_Msk                          (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                              ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/************ Bit definition for Ethernet MTL Operation Mode Register   ***************/
+#define ETH_MTLOMR_CNTCLR_Pos                        (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                        (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                            ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                       (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                       (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                           ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_SCHALG_Pos                        (5U)
+#define ETH_MTLOMR_SCHALG_Msk                        (0x3UL << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG                            ETH_MTLOMR_SCHALG_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_SCHALG_WRR                        ((uint32_t)0x00000000)   /* Weighted round robin (WRR) algorithm */
+#define ETH_MTLOMR_SCHALG_SP_Pos                     (5U)
+#define ETH_MTLOMR_SCHALG_SP_Msk                     (0x3UL << ETH_MTLOMR_SCHALG_SP_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG_SP                         ETH_MTLOMR_SCHALG_SP_Msk  /* Strict priority (SP) algorithm */
+#define ETH_MTLOMR_RAA_Pos                           (2U)
+#define ETH_MTLOMR_RAA_Msk                           (0x1UL << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA                               ETH_MTLOMR_RAA_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_RAA_SP                            ((uint32_t)0x00000000)   /* Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest */
+#define ETH_MTLOMR_RAA_WSP_Pos                       (2U)
+#define ETH_MTLOMR_RAA_WSP_Msk                       (0x1UL << ETH_MTLOMR_RAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA_WSP                           ETH_MTLOMR_RAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_MTLOMR_DTXSTS_Pos                        (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                        (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                            ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/************ Bit definition for Ethernet MTL Interrupt Status Register   ***************/
+#define ETH_MTLISR_ESTIS_Pos                          (18U)
+#define ETH_MTLISR_ESTIS_Msk                          (0x1UL << ETH_MTLISR_ESTIS_Pos) /*!< 0x00040000 */
+#define ETH_MTLISR_ESTIS                              ETH_MTLISR_ESTIS_Msk     /* EST (TAS- 802.1Qbv) Interrupt Status */
+#define ETH_MTLISR_Q1IS_Pos                           (1U)
+#define ETH_MTLISR_Q1IS_Msk                           (0x1UL << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
+#define ETH_MTLISR_Q1IS                               ETH_MTLISR_Q1IS_Msk       /* Queue 1 Interrupt status */
+#define ETH_MTLISR_Q0IS_Pos                           (0U)
+#define ETH_MTLISR_Q0IS_Msk                           (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_Q0IS                               ETH_MTLISR_Q0IS_Msk       /* Queue 0 Interrupt status */
+
+/************ Bit definition for Ethernet MTL Rx Queue and DMA Channel Mapping   ***************/
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Pos                 (12U)
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1DDMACH_Pos) /*!< 0x00001000 */
+#define ETH_MTLRXQDMAMR_Q1DDMACH                     ETH_MTLRXQDMAMR_Q1DDMACH_Msk /* Queue 1 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Pos                 (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH                     ETH_MTLRXQDMAMR_Q1MDMACH_Msk /* Queue 1 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos          (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk /* DMA Channel 1 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Pos                 (4U)
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0DDMACH_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH                     ETH_MTLRXQDMAMR_Q0DDMACH_Msk /* Queue 0 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Pos                 (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH                     ETH_MTLRXQDMAMR_Q0MDMACH_Msk /* Queue 0 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos          (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk /* DMA Channel 1 */
+
+/************ Bit definition for Ethernet MTL TBS control Register   ***************/
+#define ETH_MTLTBSCR_LEOS_Pos                       (8U)
+#define ETH_MTLTBSCR_LEOS_Msk                       (0xFFFFFFUL << ETH_MTLTBSCR_LEOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEOS                           ETH_MTLTBSCR_LEOS_Msk /* Launch Expiry Offset */
+#define ETH_MTLTBSCR_LEGOS_Pos                      (4U)
+#define ETH_MTLTBSCR_LEGOS_Msk                      (0x7UL << ETH_MTLTBSCR_LEGOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEGOS                          ETH_MTLTBSCR_LEGOS_Msk /* Launch Expiry GSN Offset */
+#define ETH_MTLTBSCR_LEOV_Pos                       (1U)
+#define ETH_MTLTBSCR_LEOV_Msk                       (0x1UL << ETH_MTLTBSCR_LEOV_Pos) /*!< 0x00000002 */
+#define ETH_MTLTBSCR_LEOV                           ETH_MTLTBSCR_LEOV_Msk /* Launch expiry offset valid */
+#define ETH_MTLTBSCR_ESTM_Pos                       (0U)
+#define ETH_MTLTBSCR_ESTM_Msk                       (0x1UL << ETH_MTLTBSCR_ESTM_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM                           ETH_MTLTBSCR_ESTM_Msk /* EST offset mode */
+#define ETH_MTLTBSCR_ESTM_ESTOFFDIS                 ((uint32_t)0x00000000)   /* EST offset mode disabled */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos              (0U)
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk              (0x1UL << ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN                   ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk  /* EST offset mode enabled */
+
+/************ Bit definition for Ethernet MTL EST Control Register   ***************/
+#define ETH_MTLESTCR_PTOV_Pos                       (24U)
+#define ETH_MTLESTCR_PTOV_Msk                       (0xFFFFFFUL << ETH_MTLESTCR_PTOV_Pos) /*!< 0xFF000000 */
+#define ETH_MTLESTCR_PTOV                           ETH_MTLESTCR_PTOV_Msk /* PTP Time Offset Value */
+#define ETH_MTLESTCR_CTOV_Pos                       (12U)
+#define ETH_MTLESTCR_CTOV_Msk                       (0xFFFUL << ETH_MTLESTCR_CTOV_Pos) /*!< 0x00FFF000 */
+#define ETH_MTLESTCR_CTOV                           ETH_MTLESTCR_CTOV_Msk /* Current Time Offset Value */
+#define ETH_MTLESTCR_TILS_Pos                       (8U)
+#define ETH_MTLESTCR_TILS_Msk                       (0x7UL << ETH_MTLESTCR_TILS_Pos) /*!< 0x00000700 */
+#define ETH_MTLESTCR_TILS                           ETH_MTLESTCR_TILS_Msk /* Time Interval Left Shift Amount */
+#define ETH_MTLESTCR_LCSE_Pos                       (6U)
+#define ETH_MTLESTCR_LCSE_Msk                       (0x3UL << ETH_MTLESTCR_LCSE_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE                           ETH_MTLESTCR_LCSE_Msk /* Loop Count to report Scheduling Error */
+#define ETH_MTLESTCR_LCSE_4IT                       ((uint32_t)0x00000000)   /* 4 iterations */
+#define ETH_MTLESTCR_LCSE_8IT_Pos                   (6U)
+#define ETH_MTLESTCR_LCSE_8IT_Msk                   (0x1UL << ETH_MTLESTCR_LCSE_8IT_Pos) /*!< 0x00000040 */
+#define ETH_MTLESTCR_LCSE_8IT                       ETH_MTLESTCR_LCSE_8IT_Msk   /* 8 iterations */
+#define ETH_MTLESTCR_LCSE_16IT_Pos                  (7U)
+#define ETH_MTLESTCR_LCSE_16IT_Msk                  (0x1UL << ETH_MTLESTCR_LCSE_16IT_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTCR_LCSE_16IT                      ETH_MTLESTCR_LCSE_16IT_Msk  /* 16 iterations */
+#define ETH_MTLESTCR_LCSE_32IT_Pos                  (6U)
+#define ETH_MTLESTCR_LCSE_32IT_Msk                  (0x3UL << ETH_MTLESTCR_LCSE_32IT_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE_32IT                      ETH_MTLESTCR_LCSE_32IT_Msk  /* 32 iterations */
+#define ETH_MTLESTCR_DFBS_Pos                       (5U)
+#define ETH_MTLESTCR_DFBS_Msk                       (0x1UL << ETH_MTLESTCR_DFBS_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTCR_DFBS                           ETH_MTLESTCR_DFBS_Msk /* Drop Frames causing Scheduling Error */
+#define ETH_MTLESTCR_DDBF_Pos                       (4U)
+#define ETH_MTLESTCR_DDBF_Msk                       (0x1UL << ETH_MTLESTCR_DDBF_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTCR_DDBF                           ETH_MTLESTCR_DDBF_Msk /* Do not Drop frames during Frame Size Error */
+#define ETH_MTLESTCR_SSWL_Pos                       (1U)
+#define ETH_MTLESTCR_SSWL_Msk                       (0x1UL << ETH_MTLESTCR_SSWL_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTCR_SSWL                           ETH_MTLESTCR_SSWL_Msk /* Switch to S/W owned list */
+#define ETH_MTLESTCR_EEST_Pos                       (0U)
+#define ETH_MTLESTCR_EEST_Msk                       (0x1UL << ETH_MTLESTCR_EEST_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTCR_EEST                           ETH_MTLESTCR_EEST_Msk /* Enable EST */
+
+/************ Bit definition for Ethernet MTL EST Extended Control Register   ***************/
+/* Bit definition for Ethernet MTL EST Extended Control Register */
+#define ETH_MTLESTECR_OVHD_Pos                       (0U)
+#define ETH_MTLESTECR_OVHD_Msk                       (0x3FUL << ETH_MTLESTECR_OVHD_Pos) /*!< 0x0000003F */
+#define ETH_MTLESTECR_OVHD                           ETH_MTLESTECR_OVHD_Msk /* Overhead Bytes Value */
+
+/************ Bit definition for Ethernet MTL EST Status Register   ***************/
+#define ETH_MTLESTSR_CGSN_Pos                       (16U)
+#define ETH_MTLESTSR_CGSN_Msk                       (0xFUL << ETH_MTLESTSR_CGSN_Pos) /*!< 0x000F0000 */
+#define ETH_MTLESTSR_CGSN                           ETH_MTLESTSR_CGSN_Msk /* Current GCL slot number */
+#define ETH_MTLESTSR_BTRL_Pos                       (8U)
+#define ETH_MTLESTSR_BTRL_Msk                       (0xFFUL << ETH_MTLESTSR_BTRL_Pos) /*!< 0x00000F00 */
+#define ETH_MTLESTSR_BTRL                           ETH_MTLESTSR_CGSN_Msk /* BTR Error Loop Count */
+#define ETH_MTLESTSR_SWOL_Pos                       (7U)
+#define ETH_MTLESTSR_SWOL_Msk                       (0x1UL << ETH_MTLESTSR_SWOL_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTSR_SWOL                           ETH_MTLESTSR_SWOL_Msk /* S/W owned list */
+#define ETH_MTLESTSR_CGCE_Pos                       (4U)
+#define ETH_MTLESTSR_CGCE_Msk                       (0x1UL << ETH_MTLESTSR_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTSR_CGCE                           ETH_MTLESTSR_CGCE_Msk /* Constant Gate Control Error */
+#define ETH_MTLESTSR_HLBS_Pos                       (3U)
+#define ETH_MTLESTSR_HLBS_Msk                       (0x1UL << ETH_MTLESTSR_HLBS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTSR_HLBS                           ETH_MTLESTSR_HLBS_Msk /* Head-Of-Line Blocking due to Scheduling */
+#define ETH_MTLESTSR_HLBF_Pos                       (2U)
+#define ETH_MTLESTSR_HLBF_Msk                       (0x1UL << ETH_MTLESTSR_HLBF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTSR_HLBF                           ETH_MTLESTSR_HLBF_Msk /* Head-Of-Line Blocking due to Frame Size */
+#define ETH_MTLESTSR_BTRE_Pos                       (1U)
+#define ETH_MTLESTSR_BTRE_Msk                       (0x1UL << ETH_MTLESTSR_BTRE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTSR_BTRE                           ETH_MTLESTSR_BTRE_Msk /* BTR Error */
+#define ETH_MTLESTSR_SWLC_Pos                       (0U)
+#define ETH_MTLESTSR_SWLC_Msk                       (0x1UL << ETH_MTLESTSR_SWLC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTSR_SWLC                           ETH_MTLESTSR_SWLC_Msk /* Switch to S/W owned list Complete */
+
+/************ Bit definition for Ethernet MTL EST Schedule Error Register   ***************/
+/* Bit definition for Ethernet MTL EST Schedule Error Register */
+#define ETH_MTLESTSCHER_SEQN_Pos                       (0U)
+#define ETH_MTLESTSCHER_SEQN_Msk                       (0x3UL << ETH_MTLESTSCHER_SEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTSCHER_SEQN                           ETH_MTLESTSCHER_SEQN_Msk /* Schedule Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Error Register   ***************/
+#define ETH_MTLESTFSER_FEQN_Pos                       (0U)
+#define ETH_MTLESTFSER_FEQN_Msk                       (0x3UL << ETH_MTLESTFSER_FEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTFSER_FEQN                           ETH_MTLESTFSER_FEQN_Msk /* Frame Size Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Capture Register   ***************/
+#define ETH_MTLESTFSCR_HBFQ_Pos                       (16U)
+#define ETH_MTLESTFSCR_HBFQ_Msk                       (0x1UL << ETH_MTLESTFSCR_HBFQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLESTFSCR_HBFQ                           ETH_MTLESTFSCR_HBFQ_Msk /* Queue Number of HLBF */
+#define ETH_MTLESTFSCR_HBFS_Pos                       (0U)
+#define ETH_MTLESTFSCR_HBFS_Msk                       (0x7FFFUL << ETH_MTLESTFSCR_HBFS_Pos) /*!< 0x00007FFF */
+#define ETH_MTLESTFSCR_HBFS                           ETH_MTLESTFSCR_HBFS_Msk /* Frame Size of HLBF */
+
+/************ Bit definition for Ethernet MTL EST Interrupt Enable Register   ***************/
+/* Bit definition for Ethernet MTL EST Interrupt Enable Register */
+#define ETH_MTLESTIER_CGCE_Pos                       (4U)
+#define ETH_MTLESTIER_CGCE_Msk                       (0x1UL << ETH_MTLESTIER_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTIER_CGCE                           ETH_MTLESTIER_CGCE_Msk /* Interrupt Enable for CGCE */
+#define ETH_MTLESTIER_IEHS_Pos                       (3U)
+#define ETH_MTLESTIER_IEHS_Msk                       (0x1UL << ETH_MTLESTIER_IEHS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTIER_IEHS                           ETH_MTLESTIER_IEHS_Msk /* Interrupt Enable for HLBS */
+#define ETH_MTLESTIER_IEHF_Pos                       (2U)
+#define ETH_MTLESTIER_IEHF_Msk                       (0x1UL << ETH_MTLESTIER_IEHF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTIER_IEHF                           ETH_MTLESTIER_IEHF_Msk /* Interrupt Enable for HLBF */
+#define ETH_MTLESTIER_IEBE_Pos                       (1U)
+#define ETH_MTLESTIER_IEBE_Msk                       (0x1UL << ETH_MTLESTIER_IEBE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTIER_IEBE                           ETH_MTLESTIER_IEBE_Msk /* Interrupt Enable for BTR Error */
+#define ETH_MTLESTIER_IECC_Pos                       (0U)
+#define ETH_MTLESTIER_IECC_Msk                       (0x1UL << ETH_MTLESTIER_IECC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTIER_IECC                           ETH_MTLESTIER_IECC_Msk /* Interrupt Enable for Switch List */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Register   ***************/
+#define ETH_MTLESTGCLCR_ADDR_Pos                       (8U)
+#define ETH_MTLESTGCLCR_ADDR_Msk                       (0x3FUL << ETH_MTLESTGCLCR_ADDR_Pos) /*!< 0x00003F00 */
+#define ETH_MTLESTGCLCR_ADDR                           ETH_MTLESTGCLCR_ADDR_Msk /* Gate Control List Address */
+#define ETH_MTLESTGCLCR_ADDR_BTRLOW                    ((uint32_t)0x00000000)   /* BTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk               (0x1UL << ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos) /*!< 0x00000100 */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH                   ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk /* BTR High (63:31) */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos                (9U)
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk                (0x1UL << ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos) /*!< 0x00000200 */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW                    ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk /* CTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk               (0x3UL << ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos) /*!< 0x00000300 */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH                   ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk /* CTR High (39:32) */
+#define ETH_MTLESTGCLCR_ADDR_TER_Pos                   (10U)
+#define ETH_MTLESTGCLCR_ADDR_TER_Msk                   (0x1UL << ETH_MTLESTGCLCR_ADDR_TER_Pos) /*!< 0x00000400 */
+#define ETH_MTLESTGCLCR_ADDR_TER                       ETH_MTLESTGCLCR_ADDR_TER_Msk /* TER (30:0) */
+#define ETH_MTLESTGCLCR_ADDR_LLR_Pos                   (8U)
+#define ETH_MTLESTGCLCR_ADDR_LLR_Msk                   (0x5UL << ETH_MTLESTGCLCR_ADDR_LLR_Pos) /*!< 0x00000500 */
+#define ETH_MTLESTGCLCR_ADDR_LLR                       ETH_MTLESTGCLCR_ADDR_LLR_Msk /* LLR (6:0) */
+#define ETH_MTLESTGCLCR_DBGB_Pos                       (5U)
+#define ETH_MTLESTGCLCR_DBGB_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGB_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTGCLCR_DBGB                           ETH_MTLESTGCLCR_DBGB_Msk /* Debug Mode Bank Select */
+#define ETH_MTLESTGCLCR_DBGM_Pos                       (4U)
+#define ETH_MTLESTGCLCR_DBGM_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGM_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTGCLCR_DBGM                           ETH_MTLESTGCLCR_DBGM_Msk /* Debug Mode */
+#define ETH_MTLESTGCLCR_GCRR_Pos                       (2U)
+#define ETH_MTLESTGCLCR_GCRR_Msk                       (0x1UL << ETH_MTLESTGCLCR_GCRR_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTGCLCR_GCRR                           ETH_MTLESTGCLCR_GCRR_Msk /* Gate Control Related Registers */
+#define ETH_MTLESTGCLCR_R1W0_Pos                       (1U)
+#define ETH_MTLESTGCLCR_R1W0_Msk                       (0x1UL << ETH_MTLESTGCLCR_R1W0_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTGCLCR_R1W0                           ETH_MTLESTGCLCR_R1W0_Msk /* Read 1, Write 0 */
+#define ETH_MTLESTGCLCR_SRWO_Pos                       (0U)
+#define ETH_MTLESTGCLCR_SRWO_Msk                       (0x1UL << ETH_MTLESTGCLCR_SRWO_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTGCLCR_SRWO                           ETH_MTLESTGCLCR_SRWO_Msk /* Start Read/Write Operation */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Data Register   ***************/
+#define ETH_MTLESTGCLDR_GCD_Pos                        (0U)
+#define ETH_MTLESTGCLDR_GCD_Msk                        (0xFFFFFFFFUL << ETH_MTLESTGCLDR_GCD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MTLESTGCLDR_GCD                            ETH_MTLESTGCLDR_GCD_Msk /* Gate Control Data */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Control Status Register   ***************/
+#define ETH_MTLFPECSR_HRS_Pos                          (28U)
+#define ETH_MTLFPECSR_HRS_Msk                          (0x1UL << ETH_MTLFPECSR_HRS_Pos) /*!< 0x10000000 */
+#define ETH_MTLFPECSR_HRS                              ETH_MTLFPECSR_HRS_Msk /* Hold/Release Status */
+#define ETH_MTLFPECSR_PEC_Pos                          (8U)
+#define ETH_MTLFPECSR_PEC_Msk                          (0x3UL << ETH_MTLFPECSR_PEC_Pos) /*!< 0x00000300 */
+#define ETH_MTLFPECSR_PEC                              ETH_MTLFPECSR_PEC_Msk /* Preemption Classification */
+#define ETH_MTLFPECSR_AFSZ_Pos                         (0U)
+#define ETH_MTLFPECSR_AFSZ_Msk                         (0x3UL << ETH_MTLFPECSR_AFSZ_Pos) /*!< 0x00000003 */
+#define ETH_MTLFPECSR_AFSZ                             ETH_MTLFPECSR_AFSZ_Msk /* Additional Fragment Size */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Advance Register   ***************/
+#define ETH_MTLFPEAR_RADV_Pos                          (16U)
+#define ETH_MTLFPEAR_RADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_RADV_Pos) /*!< 0xFFFF0000 */
+#define ETH_MTLFPEAR_RADV                              ETH_MTLFPEAR_RADV_Msk /* Release Advance */
+#define ETH_MTLFPEAR_HADV_Pos                          (0U)
+#define ETH_MTLFPEAR_HADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_HADV_Pos) /*!< 0x0000FFFF */
+#define ETH_MTLFPEAR_HADV                              ETH_MTLFPEAR_HADV_Msk /* Hold Advance */
+
+/************ Bit definition for Ethernet MTL Tx queue x operating mode Register   ***************/
+#define ETH_MTLTXQxOMR_TQS_Pos                          (16U)
+#define ETH_MTLTXQxOMR_TQS_Msk                          (0xFUL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x000F0000 */
+#define ETH_MTLTXQxOMR_TQS                              ETH_MTLTXQxOMR_TQS_Msk     /* Transmit queue size */
+#define ETH_MTLTXQxOMR_TQS_0                            (0x1UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00010000 */
+#define ETH_MTLTXQxOMR_TQS_1                            (0x2UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00020000 */
+#define ETH_MTLTXQxOMR_TQS_2                            (0x4UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00040000 */
+#define ETH_MTLTXQxOMR_TQS_3                            (0x8UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00080000 */
+#define ETH_MTLTXQxOMR_TTC_Pos                          (4U)
+#define ETH_MTLTXQxOMR_TTC_Msk                          (0x7UL << ETH_MTLTXQxOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQxOMR_TTC                              ETH_MTLTXQxOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTXQxOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTXQxOMR_TXQEN_Pos                        (2U)
+#define ETH_MTLTXQxOMR_TXQEN_Msk                        (0x3UL << ETH_MTLTXQxOMR_TXQEN_Pos) /*!< 0x0000000C */
+#define ETH_MTLTXQxOMR_TXQEN                            ETH_MTLTXQxOMR_TXQEN_Msk     /* Transmit Queue Enable */
+#define ETH_MTLTXQxOMR_TXQEN_NOT                        ((uint32_t)0x00000000)   /* Not enabled */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos                 (2U)
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk                 (0x1UL << ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE                     ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk     /* Enable in AV mode */
+#define ETH_MTLTXQxOMR_TXQEN_EN_Pos                     (3U)
+#define ETH_MTLTXQxOMR_TXQEN_EN_Msk                     (0x1UL << ETH_MTLTXQxOMR_TXQEN_EN_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxOMR_TXQEN_EN                         ETH_MTLTXQxOMR_TXQEN_EN_Msk     /* Enabled */
+#define ETH_MTLTXQxOMR_TSF_Pos                          (1U)
+#define ETH_MTLTXQxOMR_TSF_Msk                          (0x1UL << ETH_MTLTXQxOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQxOMR_TSF                              ETH_MTLTXQxOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTXQxOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTXQxOMR_FTQ_Msk                          (0x1UL << ETH_MTLTXQxOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxOMR_FTQ                              ETH_MTLTXQxOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Underflow Register   ***************/
+#define ETH_MTLTXQxUR_UFCNTOVF_Pos                     (11U)
+#define ETH_MTLTXQxUR_UFCNTOVF_Msk                     (0x1UL << ETH_MTLTXQxUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQxUR_UFCNTOVF                         ETH_MTLTXQxUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTXQxUR_UFPKTCNT_Pos                     (0U)
+#define ETH_MTLTXQxUR_UFPKTCNT_Msk                     (0x7FFUL << ETH_MTLTXQxUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTXQxUR_UFPKTCNT                         ETH_MTLTXQxUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Debug Register   ***************/
+#define ETH_MTLTXQxDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTXQxDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTXQxDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTXQxDR_STXSTSF                           ETH_MTLTXQxDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTXQxDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTXQxDR_PTXQ_Msk                          (0x7UL << ETH_MTLTXQxDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTXQxDR_PTXQ                              ETH_MTLTXQxDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTXQxDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTXQxDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTXQxDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQxDR_TXSTSFSTS                         ETH_MTLTXQxDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTXQxDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTXQxDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQxDR_TXQSTS                            ETH_MTLTXQxDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTXQxDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTXQxDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxDR_TWCSTS                            ETH_MTLTXQxDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTXQxDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTXQxDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTXQxDR_TRCSTS                            ETH_MTLTXQ0DR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTXQxDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTXQxDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTXQxDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTXQxDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTXQxDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTXQxDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxDR_TXQPAUSED                         ETH_MTLTXQxDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/************ Bit definition for Ethernet MTL Tx queue x ETS status Register   ***************/
+#define ETH_MTLTXQxESR_ABS_Pos                       (0U)
+#define ETH_MTLTXQxESR_ABS_Msk                       (0xFFFFFFUL << ETH_MTLTXQxESR_ABS_Pos) /*!< 0x00FFFFFF */
+#define ETH_MTLTXQxESR_ABS                           ETH_MTLTXQxESR_ABS_Msk  /* Average Bits per Slot */
+
+/************ Bit definition for Ethernet MTL Tx queue 0 quantum weight Register   ***************/
+#define ETH_MTLTXQ0QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ0QWR_ISCQW_Msk                       (0x7FUL << ETH_MTLTXQ0QWR_ISCQW_Pos) /*!< 0x0000007F */
+#define ETH_MTLTXQ0QWR_ISCQW                           ETH_MTLTXQ0QWR_ISCQW_Msk  /* Weights */
+
+/************ Bit definition for Ethernet MTL Queue x Interrupt Control Status Register   ***************/
+#define ETH_MTLQxICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQxICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQxICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQxICSR_RXOIE                            ETH_MTLQxICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQxICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQxICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQxICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQxICSR_RXOVFIS                          ETH_MTLQxICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQxICSR_ABPSIE_Pos                       (9U)
+#define ETH_MTLQxICSR_ABPSIE_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIE_Pos) /*!< 0x00000200 */
+#define ETH_MTLQxICSR_ABPSIE                           ETH_MTLQxICSR_ABPSIE_Msk   /* Average Bits Per Slot Interrupt Enable */
+#define ETH_MTLQxICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQxICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQxICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQxICSR_TXUIE                            ETH_MTLQxICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQxICSR_ABPSIS_Pos                       (1U)
+#define ETH_MTLQxICSR_ABPSIS_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIS_Pos) /*!< 0x00000002 */
+#define ETH_MTLQxICSR_ABPSIS                           ETH_MTLQxICSR_ABPSIS_Msk /* Average Bits Per Slot Interrupt Status */
+#define ETH_MTLQxICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQxICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQxICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQxICSR_TXUNFIS                          ETH_MTLQxICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Operation Mode Register   ***************/
+#define ETH_MTLRXQxOMR_RQS_Pos                          (20U)
+#define ETH_MTLRXQxOMR_RQS_Msk                          (0xFUL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00F00000 */
+#define ETH_MTLRXQxOMR_RQS                              ETH_MTLRXQxOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRXQxOMR_RQS_0                            (0x1UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00100000 */
+#define ETH_MTLRXQxOMR_RQS_1                            (0x2UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00200000 */
+#define ETH_MTLRXQxOMR_RQS_2                            (0x4UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00400000 */
+#define ETH_MTLRXQxOMR_RQS_3                            (0x8UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00800000 */
+#define ETH_MTLRXQxOMR_RFD_Pos                          (14U)
+#define ETH_MTLRXQxOMR_RFD_Msk                          (0x7UL << ETH_MTLRXQxOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRXQxOMR_RFD                              ETH_MTLRXQxOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRXQxOMR_RFA_Pos                          (8U)
+#define ETH_MTLRXQxOMR_RFA_Msk                          (0x7UL << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRXQxOMR_RFA                              ETH_MTLRXQxOMR_RFA_Pos /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRXQxOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRXQxOMR_EHFC_Msk                         (0x1UL << ETH_MTLRXQxOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQxOMR_EHFC                             ETH_MTLRXQxOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRXQxOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRXQxOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRXQxOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQxOMR_DISTCPEF                         ETH_MTLRXQxOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRXQxOMR_RSF_Pos                          (5U)
+#define ETH_MTLRXQxOMR_RSF_Msk                          (0x1UL << ETH_MTLRXQxOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxOMR_RSF                              ETH_MTLRXQxOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRXQxOMR_FEP_Pos                          (4U)
+#define ETH_MTLRXQxOMR_FEP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxOMR_FEP                              ETH_MTLRXQxOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRXQxOMR_FUP_Pos                          (3U)
+#define ETH_MTLRXQxOMR_FUP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxOMR_FUP                              ETH_MTLRXQxOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRXQxOMR_RTC_Pos                          (0U)
+#define ETH_MTLRXQxOMR_RTC_Msk                          (0x3UL << ETH_MTLRXQxOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRXQxOMR_RTC                              ETH_MTLRXQxOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRXQxOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Missed Packet Overflow Cnt Register   ***************/
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQxMPOCR_MISCNTOVF                      ETH_MTLRXQxMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT                      ETH_MTLRXQxMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF                      ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT                      ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Debug Register   ***************/
+#define ETH_MTLRXQxDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRXQxDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRXQxDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRXQxDR_PRXQ                              ETH_MTLRXQxDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRXQxDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRXQxDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS                            ETH_MTLRXQxDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRXQxDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRXQxDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS_FULL                       ETH_MTLRXQxDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRXQxDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRXQxDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS                            ETH_MTLRXQxDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRXQxDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS              ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING                   ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRXQxDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRXQxDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRXQxDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQxDR_RWCSTS                            ETH_MTLRXQxDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Control Register   ***************/
+#define ETH_MTLRXQxCR_RQPA_Pos                          (3U)
+#define ETH_MTLRXQxCR_RQPA_Msk                          (0x1UL << ETH_MTLRXQxCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxCR_RQPA                              ETH_MTLRXQxCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRXQxCR_RQW_Pos                           (0U)
+#define ETH_MTLRXQxCR_RQW_Msk                           (0x7UL << ETH_MTLRXQxCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRXQxCR_RQW                               ETH_MTLRXQxCR_RQW_Msk      /* Receive Queue Weight */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 ETS control Register   ***************/
+#define ETH_MTLTXQ1ECR_SLC_Pos                         (4U)
+#define ETH_MTLTXQ1ECR_SLC_Msk                         (0x7UL << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQ1ECR_SLC                             ETH_MTLTXQ1ECR_SLC_Msk     /* Slot Count */
+#define ETH_MTLTXQ1ECR_SLC_1SLOT                       ((uint32_t)0x00000000)   /* 1 Slot */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_2SLOT_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT                       ETH_MTLTXQ1ECR_SLC_2SLOT_Msk     /* 2 Slots */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Pos                   (5U)
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_4SLOT_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT                       ETH_MTLTXQ1ECR_SLC_4SLOT_Msk     /* 4 Slots */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Msk                   (0x3UL << ETH_MTLTXQ1ECR_SLC_8SLOT_Pos) /*!< 0x00000030 */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT                       ETH_MTLTXQ1ECR_SLC_8SLOT_Msk     /* 8 Slots */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Pos                  (6U)
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Msk                  (0x1UL << ETH_MTLTXQ1ECR_SLC_16SLOT_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT                      ETH_MTLTXQ1ECR_SLC_16SLOT_Msk     /* 16 Slots */
+#define ETH_MTLTXQ1ECR_CC_Pos                          (3U)
+#define ETH_MTLTXQ1ECR_CC_Msk                          (0x1UL << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1ECR_CC                              ETH_MTLTXQ1ECR_CC_Msk     /* Credit Control */
+#define ETH_MTLTXQ1ECR_AVALG_Pos                       (2U)
+#define ETH_MTLTXQ1ECR_AVALG_Msk                       (0x1UL << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1ECR_AVALG                           ETH_MTLTXQ1ECR_AVALG_Msk     /* Credit Control */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 quantum weight Register   ***************/
+#define ETH_MTLTXQ1QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ1QWR_ISCQW_Msk                       (0x3FFFUL << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1QWR_ISCQW                           ETH_MTLTXQ1QWR_ISCQW_Msk     /* IdleSlopeCredit or Weights */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 send slope credit Register   ***************/
+#define ETH_MTLTXQ1SSCR_SSC_Pos                        (0U)
+#define ETH_MTLTXQ1SSCR_SSC_Msk                        (0x3FFFUL << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1SSCR_SSC                            ETH_MTLTXQ1SSCR_SSC_Msk     /* sendSlopeCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx Queue 1 hiCredit Register   ***************/
+#define ETH_MTLTXQ1HCR_HC_Pos                          (0U)
+#define ETH_MTLTXQ1HCR_HC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1HCR_HC                              ETH_MTLTXQ1HCR_HC_Msk     /* hiCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 loCredit Register   ***************/
+#define ETH_MTLTXQ1LCR_LC_Pos                          (0U)
+#define ETH_MTLTXQ1LCR_LC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1LCR_LC                              ETH_MTLTXQ1LCR_LC_Msk     /* loCredit Value */
+
+/************ Bit definition for Ethernet DMA Mode Register   ***************/
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk         /* Transmit priority */
+#define ETH_DMAMR_DSPW_Pos                            (8U)
+#define ETH_DMAMR_DSPW_Msk                            (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */
+#define ETH_DMAMR_DSPW                                ETH_DMAMR_DSPW_Msk         /* Descriptor Posted Write */
+#define ETH_DMAMR_TAA_Pos                             (2U)
+#define ETH_DMAMR_TAA_Msk                             (0x7UL << ETH_DMAMR_TAA_Pos) /*!< 0x000001C0 */
+#define ETH_DMAMR_TAA                                 ETH_DMAMR_TAA_Msk         /* Transmit Arbitration Algorithm */
+#define ETH_DMAMR_TAA_FP                              ((uint32_t)0x00000000)    /* Fixed priority */
+#define ETH_DMAMR_TAA_WSP_Pos                         (2U)
+#define ETH_DMAMR_TAA_WSP_Msk                         (0x1UL << ETH_DMAMR_TAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_DMAMR_TAA_WSP                             ETH_DMAMR_TAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_DMAMR_TAA_WRR_Pos                         (3U)
+#define ETH_DMAMR_TAA_WRR_Msk                         (0x1UL << ETH_DMAMR_TAA_WRR_Pos) /*!< 0x00000008 */
+#define ETH_DMAMR_TAA_WRR                             ETH_DMAMR_TAA_WRR_Msk  /* Weighted Round-Robin (WRR) */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk  /* Software Reset */
+
+/************ Bit definition for Ethernet DMA System bus mode Register   ***************/
+#define ETH_DMASBMR_ENLPI_Pos                         (31U)
+#define ETH_DMASBMR_ENLPI_Msk                         (0x1UL << ETH_DMASBMR_ENLPI_Pos) /*!< 0x80000000 */
+#define ETH_DMASBMR_ENLPI                             ETH_DMASBMR_ENLPI_Msk       /* Enable Low Power Interface (LPI) */
+#define ETH_DMASBMR_LPIXPKT_Pos                       (30U)
+#define ETH_DMASBMR_LPIXPKT_Msk                       (0x1UL << ETH_DMASBMR_LPIXPKT_Pos) /*!< 0x40000000 */
+#define ETH_DMASBMR_LPIXPKT                           ETH_DMASBMR_LPIXPKT_Msk       /* Unlock on Magic Packet or Remote wakeup Packet */
+#define ETH_DMASBMR_WR_OSR_LMT_Pos                    (24U)
+#define ETH_DMASBMR_WR_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
+#define ETH_DMASBMR_WR_OSR_LMT                        ETH_DMASBMR_WR_OSR_LMT_Msk            /*!< AXI Maximum Write Outstanding Request Limit */
+#define ETH_DMASBMR_WR_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
+#define ETH_DMASBMR_WR_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
+#define ETH_DMASBMR_RD_OSR_LMT_Pos                    (16U)
+#define ETH_DMASBMR_RD_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
+#define ETH_DMASBMR_RD_OSR_LMT                        ETH_DMASBMR_RD_OSR_LMT_Msk            /*!< AXI Maximum Read Outstanding Request Limit */
+#define ETH_DMASBMR_RD_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
+#define ETH_DMASBMR_RD_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
+#define ETH_DMASBMR_ONEKBBE_Pos                       (13U)
+#define ETH_DMASBMR_ONEKBBE_Msk                       (0x1UL << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
+#define ETH_DMASBMR_ONEKBBE                           ETH_DMASBMR_ONEKBBE_Msk       /* 1 Kbyte Boundary Crossing Enable for the AXI Master */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_AALE_Pos                          (10U)
+#define ETH_DMASBMR_AALE_Msk                          (0x1UL << ETH_DMASBMR_AALE_Pos) /*!< 0x00000400 */
+#define ETH_DMASBMR_AALE                              ETH_DMASBMR_AALE_Msk       /* Automatic AXI LPI enable */
+#define ETH_DMASBMR_BLEN256_Pos                       (7U)
+#define ETH_DMASBMR_BLEN256_Msk                       (0x1UL << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
+#define ETH_DMASBMR_BLEN256                           ETH_DMASBMR_BLEN256_Msk       /* AXI Burst Length 256 */
+#define ETH_DMASBMR_BLEN128_Pos                       (6U)
+#define ETH_DMASBMR_BLEN128_Msk                       (0x1UL << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
+#define ETH_DMASBMR_BLEN128                           ETH_DMASBMR_BLEN128_Msk       /* AXI Burst Length 128 */
+#define ETH_DMASBMR_BLEN64_Pos                        (5U)
+#define ETH_DMASBMR_BLEN64_Msk                        (0x1UL << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
+#define ETH_DMASBMR_BLEN64                            ETH_DMASBMR_BLEN64_Msk       /* AXI Burst Length 64 */
+#define ETH_DMASBMR_BLEN32_Pos                        (4U)
+#define ETH_DMASBMR_BLEN32_Msk                        (0x1UL << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
+#define ETH_DMASBMR_BLEN32                            ETH_DMASBMR_BLEN32_Msk       /* AXI Burst Length 32 */
+#define ETH_DMASBMR_BLEN16_Pos                        (3U)
+#define ETH_DMASBMR_BLEN16_Msk                        (0x1UL << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
+#define ETH_DMASBMR_BLEN16                            ETH_DMASBMR_BLEN16_Msk       /* AXI Burst Length 16 */
+#define ETH_DMASBMR_BLEN8_Pos                         (2U)
+#define ETH_DMASBMR_BLEN8_Msk                         (0x1UL << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
+#define ETH_DMASBMR_BLEN8                             ETH_DMASBMR_BLEN8_Msk       /* AXI Burst Length 8 */
+#define ETH_DMASBMR_BLEN4_Pos                         (1U)
+#define ETH_DMASBMR_BLEN4_Msk                         (0x1UL << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
+#define ETH_DMASBMR_BLEN4                             ETH_DMASBMR_BLEN4_Msk       /* AXI Burst Length 4 */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/************ Bit definition for Ethernet DMA Interrupt Status Register   ***************/
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMAC1IS_Pos                        (1U)
+#define ETH_DMAISR_DMAC1IS_Msk                        (0x1UL << ETH_DMAISR_DMAC1IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC1IS                            ETH_DMAISR_DMAC1IS_Msk    /* DMA Channel 1 Interrupt Status */
+#define ETH_DMAISR_DMAC0IS_Pos                        (0U)
+#define ETH_DMAISR_DMAC0IS_Msk                        (0x1UL << ETH_DMAISR_DMAC0IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC0IS                            ETH_DMAISR_DMAC0IS_Msk    /* DMA Channel 0 Interrupt Status */
+
+/************ Bit definition for Ethernet DMA Debug Status Register   ***************/
+#define ETH_DMADSR_TPS1_Pos                            (20U)
+#define ETH_DMADSR_TPS1_Msk                            (0xFUL << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
+#define ETH_DMADSR_TPS1                                ETH_DMADSR_TPS1_Msk       /* DMA Channel 1 Transmit Process State */
+#define ETH_DMADSR_TPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS1_FETCHING_Pos                   (20U)
+#define ETH_DMADSR_TPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS1_FETCHING_Pos) /*!< 0x00100000 */
+#define ETH_DMADSR_TPS1_FETCHING                       ETH_DMADSR_TPS1_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS1_WAITING_Pos                    (21U)
+#define ETH_DMADSR_TPS1_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS1_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_DMADSR_TPS1_WAITING                        ETH_DMADSR_TPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS1_READING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_READING_Msk                    (0x3UL << ETH_DMADSR_TPS1_READING_Pos) /*!< 0x00300000 */
+#define ETH_DMADSR_TPS1_READING                        ETH_DMADSR_TPS1_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos               (22U)
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos) /*!< 0x00400000 */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR                   ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS1_SUSPENDED_Pos                  (21U)
+#define ETH_DMADSR_TPS1_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS1_SUSPENDED_Pos) /*!< 0x00600000 */
+#define ETH_DMADSR_TPS1_SUSPENDED                      ETH_DMADSR_TPS1_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS1_CLOSING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS1_CLOSING_Pos) /*!< 0x00700000 */
+#define ETH_DMADSR_TPS1_CLOSING                        ETH_DMADSR_TPS1_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS1_Pos                            (16U)
+#define ETH_DMADSR_RPS1_Msk                            (0xFUL << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
+#define ETH_DMADSR_RPS1                                ETH_DMADSR_RPS1_Msk       /* DMA Channel 1 Receive Process State */
+#define ETH_DMADSR_RPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS1_FETCHING_Pos                   (16U)
+#define ETH_DMADSR_RPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS1_FETCHING_Pos) /*!< 0x00010000 */
+#define ETH_DMADSR_RPS1_FETCHING                       ETH_DMADSR_RPS1_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS1_WAITING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS1_WAITING_Pos) /*!< 0x00030000 */
+#define ETH_DMADSR_RPS1_WAITING                        ETH_DMADSR_RPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS1_SUSPENDED_Pos                  (18U)
+#define ETH_DMADSR_RPS1_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS1_SUSPENDED_Pos) /*!< 0x00040000 */
+#define ETH_DMADSR_RPS1_SUSPENDED                      ETH_DMADSR_RPS1_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS1_CLOSING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS1_CLOSING_Pos) /*!< 0x00050000 */
+#define ETH_DMADSR_RPS1_CLOSING                        ETH_DMADSR_RPS1_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos               (17U)
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos) /*!< 0x00060000 */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR                   ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS1_TRANSFERRING_Pos               (16U)
+#define ETH_DMADSR_RPS1_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS1_TRANSFERRING_Pos) /*!< 0x00070000 */
+#define ETH_DMADSR_RPS1_TRANSFERRING                   ETH_DMADSR_RPS1_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_TPS0_Pos                            (12U)
+#define ETH_DMADSR_TPS0_Msk                            (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS0                                ETH_DMADSR_TPS0_Msk       /* DMA Channel 0 Transmit Process State */
+#define ETH_DMADSR_TPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS0_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS0_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS0_FETCHING                       ETH_DMADSR_TPS0_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS0_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS0_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS0_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS0_WAITING                        ETH_DMADSR_TPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS0_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_READING_Msk                    (0x3UL << ETH_DMADSR_TPS0_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS0_READING                        ETH_DMADSR_TPS0_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR                   ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS0_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS0_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS0_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS0_SUSPENDED                      ETH_DMADSR_TPS0_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS0_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS0_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS0_CLOSING                        ETH_DMADSR_TPS0_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS0_Pos                            (8U)
+#define ETH_DMADSR_RPS0_Msk                            (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS0                                ETH_DMADSR_RPS0_Msk       /* DMA Channel 0 Receive Process State */
+#define ETH_DMADSR_RPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS0_FETCHING_Pos                   (8U)
+#define ETH_DMADSR_RPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS0_FETCHING_Pos) /*!< 0x00000100 */
+#define ETH_DMADSR_RPS0_FETCHING                       ETH_DMADSR_RPS0_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS0_WAITING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS0_WAITING_Pos) /*!< 0x00000300 */
+#define ETH_DMADSR_RPS0_WAITING                        ETH_DMADSR_RPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS0_SUSPENDED_Pos                  (10U)
+#define ETH_DMADSR_RPS0_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS0_SUSPENDED_Pos) /*!< 0x00000400 */
+#define ETH_DMADSR_RPS0_SUSPENDED                      ETH_DMADSR_RPS0_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS0_CLOSING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS0_CLOSING_Pos) /*!< 0x00000500 */
+#define ETH_DMADSR_RPS0_CLOSING                        ETH_DMADSR_RPS0_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos               (9U)
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos) /*!< 0x00000600 */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR                   ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS0_TRANSFERRING_Pos               (8U)
+#define ETH_DMADSR_RPS0_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS0_TRANSFERRING_Pos) /*!< 0x00000700 */
+#define ETH_DMADSR_RPS0_TRANSFERRING                   ETH_DMADSR_RPS0_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_AXRHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXRHSTS_Msk                         (0x1UL << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
+#define ETH_DMADSR_AXRHSTS                             ETH_DMADSR_AXRHSTS_Msk /* AXI Master Read Channel Status */
+#define ETH_DMADSR_AXWHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXWHSTS_Msk                         (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
+#define ETH_DMADSR_AXWHSTS                             ETH_DMADSR_AXWHSTS_Msk /* AXI Master Write Channel */
+
+/************ Bit definition for Ethernet DMA AXI4 transmit channel ACE control Register   ***************/
+#define ETH_DMAA4TXACR_THC_Pos                         (16U)
+#define ETH_DMAA4TXACR_THC_Msk                         (0xFUL << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4TXACR_THC                             ETH_DMAA4TXACR_THC_Msk       /* Transmit DMA First Packet Buffer or TSO Header Cache Control */
+#define ETH_DMAA4TXACR_TEC_Pos                         (8U)
+#define ETH_DMAA4TXACR_TEC_Msk                         (0xFUL << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4TXACR_TEC                             ETH_DMAA4TXACR_TEC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+#define ETH_DMAA4TXACR_TDRC_Pos                        (0U)
+#define ETH_DMAA4TXACR_TDRC_Msk                        (0xFUL << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4TXACR_TDRC                            ETH_DMAA4TXACR_TDRC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 receive channel ACE control Register   ***************/
+#define ETH_DMAA4RXACR_RDC_Pos                         (24U)
+#define ETH_DMAA4RXACR_RDC_Msk                         (0xFUL << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
+#define ETH_DMAA4RXACR_RDC                             ETH_DMAA4RXACR_RDC_Msk       /* Receive DMA Buffer Cache Control */
+#define ETH_DMAA4RXACR_RHC_Pos                         (16U)
+#define ETH_DMAA4RXACR_RHC_Msk                         (0xFUL << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4RXACR_RHC                             ETH_DMAA4RXACR_RHC_Msk       /* Receive DMA Header Cache Control */
+#define ETH_DMAA4RXACR_RPC_Pos                         (8U)
+#define ETH_DMAA4RXACR_RPC_Msk                         (0xFUL << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4RXACR_RPC                             ETH_DMAA4RXACR_RPC_Msk       /* Receive DMA Payload Cache Control */
+#define ETH_DMAA4RXACR_RDWC_Pos                        (0U)
+#define ETH_DMAA4RXACR_RDWC_Msk                        (0xFUL << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4RXACR_RDWC                            ETH_DMAA4RXACR_RDWC_Msk   /* Receive DMA Write Descriptor Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 descriptor ACE control Register   ***************/
+#define ETH_DMAA4DACR_RDRC_Pos                         (8U)
+#define ETH_DMAA4DACR_RDRC_Msk                         (0xFUL << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4DACR_RDRC                             ETH_DMAA4DACR_RDRC_Msk       /* Receive DMA Read Descriptor Cache control */
+#define ETH_DMAA4DACR_TDWD_Pos                         (4U)
+#define ETH_DMAA4DACR_TDWD_Msk                         (0xFUL << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
+#define ETH_DMAA4DACR_TDWD                             ETH_DMAA4DACR_TDWD_Msk       /* Transmit DMA Write Descriptor Domain control */
+#define ETH_DMAA4DACR_TDWC_Pos                         (0U)
+#define ETH_DMAA4DACR_TDWC_Msk                         (0xFUL << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4DACR_TDWC                             ETH_DMAA4DACR_TDWC_Msk       /* Transmit DMA Write Descriptor Cache control */
+
+/************ Bit definition for Ethernet DMA AXI4 LPI Entry Interval Register   ***************/
+/* Bit definition for Ethernet DMA AXI4 LPI Entry Interval register */
+#define ETH_DMALPIEI_LPIEI_Pos                         (0U)
+#define ETH_DMALPIEI_LPIEI_Msk                         (0xFUL << ETH_DMALPIEI_LPIEI_Pos) /*!< 0x0000000F */
+#define ETH_DMALPIEI_LPIEI                             ETH_DMALPIEI_LPIEI_Msk   /* LPI Entry Interval */
+
+/************ Bit definition for Ethernet DMA TBS control Register   ***************/
+#define ETH_DMATBSCTRL0R_FTOS_Pos                      (8U)
+#define ETH_DMATBSCTRL0R_FTOS_Msk                      (0xFFFFFFUL << ETH_DMATBSCTRL0R_FTOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_DMATBSCTRL0R_FTOS                          ETH_DMATBSCTRL0R_FTOS_Msk   /* Fetch time offset */
+#define ETH_DMATBSCTRL0R_FGOS_Pos                      (4U)
+#define ETH_DMATBSCTRL0R_FGOS_Msk                      (0x7UL << ETH_DMATBSCTRL0R_FGOS_Pos) /*!< 0x00000070 */
+#define ETH_DMATBSCTRL0R_FGOS                          ETH_DMATBSCTRL0R_FGOS_Msk   /* Fetch GSN offset */
+#define ETH_DMATBSCTRL0R_FTOV_Pos                      (0U)
+#define ETH_DMATBSCTRL0R_FTOV_Msk                      (0x1UL << ETH_DMATBSCTRL0R_FTOV_Pos) /*!< 0x00000001 */
+#define ETH_DMATBSCTRL0R_FTOV                          ETH_DMATBSCTRL0R_FTOV_Msk   /* Fetch time offset valid */
+
+/************ Bit definition for Ethernet DMA Channel x Control Register   ***************/
+#define ETH_DMACxCR_DSL_Pos                            (18U)
+#define ETH_DMACxCR_DSL_Msk                            (0x7UL << ETH_DMACxCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACxCR_DSL                                ETH_DMACxCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACxCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACxCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACxCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACxCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACxCR_PBLX8_Pos                          (16U)
+#define ETH_DMACxCR_PBLX8_Msk                          (0x1UL << ETH_DMACxCR_PBLX8_Pos) /*!< 0x00010000 */
+#define ETH_DMACxCR_PBLX8                              ETH_DMACxCR_PBLX8_Msk  /* 8xPBL mode */
+#define ETH_DMACxCR_MSS_Pos                            (0U)
+#define ETH_DMACxCR_MSS_Msk                            (0x3FFFUL << ETH_DMACxCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACxCR_MSS                                ETH_DMACxCR_MSS_Msk       /* Maximum Segment Size */
+
+/************ Bit definition for Ethernet DMA Channel x transmit control Register   ***************/
+#define ETH_DMACxTXCR_EDSE_Pos                         (28U)
+#define ETH_DMACxTXCR_EDSE_Msk                         (0x1UL << ETH_DMACxTXCR_EDSE_Pos) /*!< 0x10000000 */
+#define ETH_DMACxTXCR_EDSE                             ETH_DMACxTXCR_EDSE_Msk       /* Enhanced Descriptor Enable */
+#define ETH_DMACxTXCR_TQOS_Pos                         (24U)
+#define ETH_DMACxTXCR_TQOS_Msk                         (0xFUL << ETH_DMACxTXCR_TQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxTXCR_TQOS                             ETH_DMACxTXCR_TQOS_Msk       /* Transmit QOS */
+#define ETH_DMACxTXCR_TXPBL_Pos                        (16U)
+#define ETH_DMACxTXCR_TXPBL_Msk                        (0x3FUL << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxTXCR_TXPBL                            ETH_DMACxTXCR_TXPBL_Msk       /* Transmit Programmable Burst Length */
+#define ETH_DMACxTXCR_TXPBL_1PBL                       (0x1U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00010000 */
+#define ETH_DMACxTXCR_TXPBL_2PBL                       (0x2U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00020000 */
+#define ETH_DMACxTXCR_TXPBL_4PBL                       (0x4U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00040000 */
+#define ETH_DMACxTXCR_TXPBL_8PBL                       (0x8U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00080000 */
+#define ETH_DMACxTXCR_TXPBL_16PBL                      (0x10U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00100000 */
+#define ETH_DMACxTXCR_TXPBL_32PBL                      (0x20U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00200000 */
+#define ETH_DMACxTXCR_IPBL_Pos                         (15U)
+#define ETH_DMACxTXCR_IPBL_Msk                         (0x1UL << ETH_DMACxTXCR_IPBL_Pos) /*!< 0x00008000 */
+#define ETH_DMACxTXCR_IPBL                             ETH_DMACxTXCR_IPBL_Msk       /* Ignore PBL Requirement */
+#define ETH_DMACxTXCR_TSE_Pos                          (12U)
+#define ETH_DMACxTXCR_TSE_Msk                          (0x1UL << ETH_DMACxTXCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxTXCR_TSE                              ETH_DMACxTXCR_TSE_Msk       /* TCP Segmentation Enabled */
+#define ETH_DMACxTXCR_OSF_Pos                          (4U)
+#define ETH_DMACxTXCR_OSF_Msk                          (0x1UL << ETH_DMACxTXCR_OSF_Pos) /*!< 0x00000010 */
+#define ETH_DMACxTXCR_OSF                              ETH_DMACxTXCR_OSF_Msk       /* Operate on Second Packet */
+#define ETH_DMACxTXCR_TCW_Pos                          (1U)
+#define ETH_DMACxTXCR_TCW_Msk                          (0x7UL << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000E */
+#define ETH_DMACxTXCR_TCW                              ETH_DMACxTXCR_TCW_Msk       /* Transmit Channel Weight */
+#define ETH_DMACxTXCR_TCW_1                            (0x1U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000002 */
+#define ETH_DMACxTXCR_TCW_2                            (0x2U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000004 */
+#define ETH_DMACxTXCR_TCW_3                            (0x3U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000006 */
+#define ETH_DMACxTXCR_TCW_4                            (0x4U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000008 */
+#define ETH_DMACxTXCR_TCW_5                            (0x5U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000A */
+#define ETH_DMACxTXCR_TCW_6                            (0x6U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000C */
+#define ETH_DMACxTXCR_TCW_7                            (0x7U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000E */
+#define ETH_DMACxTXCR_ST_Pos                           (0U)
+#define ETH_DMACxTXCR_ST_Msk                           (0x1UL << ETH_DMACxTXCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACxTXCR_ST                               ETH_DMACxTXCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/************ Bit definition for Ethernet DMA Channel x receive control Register   ***************/
+#define ETH_DMACxRXCR_RPF_Pos                         (31U)
+#define ETH_DMACxRXCR_RPF_Msk                         (0x1UL << ETH_DMACxRXCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACxRXCR_RPF                             ETH_DMACxRXCR_RPF_Msk       /* DMA Rx Channel Packet Flush */
+#define ETH_DMACxRXCR_RQOS_Pos                        (24U)
+#define ETH_DMACxRXCR_RQOS_Msk                        (0xFUL << ETH_DMACxRXCR_RQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxRXCR_RQOS                            ETH_DMACxRXCR_RQOS_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_Pos                       (16U)
+#define ETH_DMACxRXCR_RXPBL_Msk                       (0x3FUL << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxRXCR_RXPBL                           ETH_DMACxRXCR_RXPBL_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_1PBL                      (0x1U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00010000 */
+#define ETH_DMACxRXCR_RXPBL_2PBL                      (0x2U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00020000 */
+#define ETH_DMACxRXCR_RXPBL_4PBL                      (0x4U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00040000 */
+#define ETH_DMACxRXCR_RXPBL_8PBL                      (0x8U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00080000 */
+#define ETH_DMACxRXCR_RXPBL_16PBL                     (0x10U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00100000 */
+#define ETH_DMACxRXCR_RXPBL_32PBL                     (0x20U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00200000 */
+#define ETH_DMACxRXCR_RBSZ_Pos                        (1U)
+#define ETH_DMACxRXCR_RBSZ_Msk                        (0x1FFFUL << ETH_DMACxRXCR_RBSZ_Pos) /*!< 0x00003FFE */
+#define ETH_DMACxRXCR_RBSZ                            ETH_DMACxRXCR_RBSZ_Msk       /* Receive Buffer size */
+#define ETH_DMACxRXCR_SR_Pos                          (0U)
+#define ETH_DMACxRXCR_SR_Msk                          (0x1UL << ETH_DMACxRXCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACxRXCR_SR                              ETH_DMACxRXCR_SR_Msk       /* Start or Stop Receive */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor list address Register   ***************/
+#define ETH_DMACxTXDLAR_TDESLA_Pos                    (0U)
+#define ETH_DMACxTXDLAR_TDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDLAR_TDESLA                        ETH_DMACxTXDLAR_TDESLA_Msk   /* Start of Transmit List */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor list address Register   ***************/
+#define ETH_DMACxRXDLAR_RDESLA_Pos                    (0U)
+#define ETH_DMACxRXDLAR_RDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDLAR_RDESLA                        ETH_DMACxRXDLAR_RDESLA_Msk   /* Start of Receive List */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor tail pointer Register   ***************/
+#define ETH_DMACxTXDTPR_TDT_Pos                       (0U)
+#define ETH_DMACxTXDTPR_TDT_Msk                       (0xFFFFFFFFUL << ETH_DMACxTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDTPR_TDT                           ETH_DMACxTXDTPR_TDT_Msk   /* Transmit Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor tail pointer Register   ***************/
+#define ETH_DMACxRXDTPR_TDT_Pos                      (0U)
+#define ETH_DMACxRXDTPR_TDT_Msk                      (0xFFFFFFFFUL << ETH_DMACxRXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDTPR_TDT                          ETH_DMACxRXDTPR_TDT_Msk   /* Receive Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor ring length Register   ***************/
+#define ETH_DMACxTXRLR_TDRL_Pos                       (0U)
+#define ETH_DMACxTXRLR_TDRL_Msk                       (0x3FFUL << ETH_DMACxTXRLR_TDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxTXRLR_TDRL                           ETH_DMACxTXRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor ring length Register   ***************/
+#define ETH_DMACxRXRLR_ARBS_Pos                       (17U)
+#define ETH_DMACxRXRLR_ARBS_Msk                       (0x7FUL << ETH_DMACxRXRLR_ARBS_Pos) /*!< 0x000FE0000 */
+#define ETH_DMACxRXRLR_ARBS                           ETH_DMACxRXRLR_ARBS_Msk   /* Alternate Receive Buffer Size */
+#define ETH_DMACxRXRLR_RDRL_Pos                       (0U)
+#define ETH_DMACxRXRLR_RDRL_Msk                       (0x3FFUL << ETH_DMACxRXRLR_RDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxRXRLR_RDRL                           ETH_DMACxRXRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Interrupt Enable Register   ***************/
+#define ETH_DMACxIER_NIE_Pos                           (15U)
+#define ETH_DMACxIER_NIE_Msk                           (0x1UL << ETH_DMACxIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACxIER_NIE                               ETH_DMACxIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACxIER_AIE_Pos                           (14U)
+#define ETH_DMACxIER_AIE_Msk                           (0x1UL << ETH_DMACxIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACxIER_AIE                               ETH_DMACxIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACxIER_CDEE_Pos                          (13U)
+#define ETH_DMACxIER_CDEE_Msk                          (0x1UL << ETH_DMACxIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxIER_CDEE                              ETH_DMACxIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACxIER_FBEE_Pos                          (12U)
+#define ETH_DMACxIER_FBEE_Msk                          (0x1UL << ETH_DMACxIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxIER_FBEE                              ETH_DMACxIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACxIER_ERIE_Pos                          (11U)
+#define ETH_DMACxIER_ERIE_Msk                          (0x1UL << ETH_DMACxIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACxIER_ERIE                              ETH_DMACxIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACxIER_ETIE_Pos                          (10U)
+#define ETH_DMACxIER_ETIE_Msk                          (0x1UL << ETH_DMACxIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACxIER_ETIE                              ETH_DMACxIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACxIER_RWTE_Pos                          (9U)
+#define ETH_DMACxIER_RWTE_Msk                          (0x1UL << ETH_DMACxIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACxIER_RWTE                              ETH_DMACxIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACxIER_RSE_Pos                           (8U)
+#define ETH_DMACxIER_RSE_Msk                           (0x1UL << ETH_DMACxIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACxIER_RSE                               ETH_DMACxIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACxIER_RBUE_Pos                          (7U)
+#define ETH_DMACxIER_RBUE_Msk                          (0x1UL << ETH_DMACxIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACxIER_RBUE                              ETH_DMACxIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACxIER_RIE_Pos                           (6U)
+#define ETH_DMACxIER_RIE_Msk                           (0x1UL << ETH_DMACxIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACxIER_RIE                               ETH_DMACxIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACxIER_TBUE_Pos                          (2U)
+#define ETH_DMACxIER_TBUE_Msk                          (0x1UL << ETH_DMACxIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACxIER_TBUE                              ETH_DMACxIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACxIER_TXSE_Pos                          (1U)
+#define ETH_DMACxIER_TXSE_Msk                          (0x1UL << ETH_DMACxIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACxIER_TXSE                              ETH_DMACxIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACxIER_TIE_Pos                           (0U)
+#define ETH_DMACxIER_TIE_Msk                           (0x1UL << ETH_DMACxIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACxIER_TIE                               ETH_DMACxIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/************ Bit definition for Ethernet DMA Channel x Rx Interrupt Watchdog Timer Register   ***************/
+#define ETH_DMACxRXIWTR_RWTU_Pos                        (16U)
+#define ETH_DMACxRXIWTR_RWTU_Msk                        (0x3UL << ETH_DMACxRXIWTR_RWTU_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU                            ETH_DMACxRXIWTR_RWTU_Msk    /* Receive Interrupt Watchdog Timer Count Units */
+#define ETH_DMACxRXIWTR_RWTU_256                        ((uint32_t)0x00000000)   /* 256 */
+#define ETH_DMACxRXIWTR_RWTU_512_Pos                    (16U)
+#define ETH_DMACxRXIWTR_RWTU_512_Msk                    (0x1UL << ETH_DMACxRXIWTR_RWTU_512_Pos) /*!< 0x00010000 */
+#define ETH_DMACxRXIWTR_RWTU_512                        ETH_DMACxRXIWTR_RWTU_512_Msk    /* 512 */
+#define ETH_DMACxRXIWTR_RWTU_1024_Pos                   (17U)
+#define ETH_DMACxRXIWTR_RWTU_1024_Msk                   (0x1UL << ETH_DMACxRXIWTR_RWTU_1024_Pos) /*!< 0x00020000 */
+#define ETH_DMACxRXIWTR_RWTU_1024                       ETH_DMACxRXIWTR_RWTU_1024_Msk    /* 1024 */
+#define ETH_DMACxRXIWTR_RWTU_2048_Pos                   (16U)
+#define ETH_DMACxRXIWTR_RWTU_2048_Msk                   (0x3UL << ETH_DMACxRXIWTR_RWTU_2048_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU_2048                       ETH_DMACxRXIWTR_RWTU_2048_Msk    /* 2048 */
+#define ETH_DMACxRXIWTR_RWT_Pos                         (0U)
+#define ETH_DMACxRXIWTR_RWT_Msk                         (0xFFUL << ETH_DMACxRXIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACxRXIWTR_RWT                             ETH_DMACxRXIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/************ Bit definition for Ethernet DMA Channel x slot function control status Register   ***************/
+#define ETH_DMACxSFCSR_RSN_Pos                        (16U)
+#define ETH_DMACxSFCSR_RSN_Msk                        (0xFUL << ETH_DMACxSFCSR_RSN_Pos) /*!< 0x000F0000 */
+#define ETH_DMACxSFCSR_RSN                            ETH_DMACxSFCSR_RSN_Msk    /* Reference Slot Number */
+#define ETH_DMACxSFCSR_SIV_Pos                        (4U)
+#define ETH_DMACxSFCSR_SIV_Msk                        (0xFFFUL << ETH_DMACxSFCSR_SIV_Pos) /*!< 0x0000FFF0 */
+#define ETH_DMACxSFCSR_SIV                            ETH_DMACxSFCSR_SIV_Msk    /* Slot Interval Value */
+#define ETH_DMACxSFCSR_ASC_Pos                        (1U)
+#define ETH_DMACxSFCSR_ASC_Msk                        (0x1UL << ETH_DMACxSFCSR_ASC_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSFCSR_ASC                            ETH_DMACxSFCSR_ASC_Msk    /* Advance Slot Check */
+#define ETH_DMACxSFCSR_ESC_Pos                        (0U)
+#define ETH_DMACxSFCSR_ESC_Msk                        (0x1UL << ETH_DMACxSFCSR_ESC_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSFCSR_ESC                            ETH_DMACxSFCSR_ESC_Msk    /* Enable Slot Comparison */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Desc Register   ***************/
+#define ETH_DMACxCATXDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACxCATXDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXDR_CURTDESAPTR                     ETH_DMACxCATXDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Desc Register   ***************/
+#define ETH_DMACxCARXDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACxCARXDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXDR_CURRDESAPTR                     ETH_DMACxCARXDR_CURRDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Buffer Register   ***************/
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXBR_CURTBUFAPTR                     ETH_DMACxCATXBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Buffer Register   ***************/
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXBR_CURRBUFAPTR                     ETH_DMACxCARXBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Status Register   ***************/
+#define ETH_DMACxSR_REB_Pos                            (19U)
+#define ETH_DMACxSR_REB_Msk                            (0x7UL << ETH_DMACxSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACxSR_REB                                ETH_DMACxSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACxSR_TEB_Pos                            (16U)
+#define ETH_DMACxSR_TEB_Msk                            (0x7UL << ETH_DMACxSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACxSR_TEB                                ETH_DMACxSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACxSR_NIS_Pos                            (15U)
+#define ETH_DMACxSR_NIS_Msk                            (0x1UL << ETH_DMACxSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACxSR_NIS                                ETH_DMACxSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACxSR_AIS_Pos                            (14U)
+#define ETH_DMACxSR_AIS_Msk                            (0x1UL << ETH_DMACxSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACxSR_AIS                                ETH_DMACxSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACxSR_CDE_Pos                            (13U)
+#define ETH_DMACxSR_CDE_Msk                            (0x1UL << ETH_DMACxSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxSR_CDE                                ETH_DMACxSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACxSR_FBE_Pos                            (12U)
+#define ETH_DMACxSR_FBE_Msk                            (0x1UL << ETH_DMACxSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxSR_FBE                                ETH_DMACxSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACxSR_ERI_Pos                            (11U)
+#define ETH_DMACxSR_ERI_Msk                            (0x1UL << ETH_DMACxSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACxSR_ERI                                ETH_DMACxSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACxSR_ETI_Pos                            (10U)
+#define ETH_DMACxSR_ETI_Msk                            (0x1UL << ETH_DMACxSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACxSR_ETI                                ETH_DMACxSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACxSR_RWT_Pos                            (9U)
+#define ETH_DMACxSR_RWT_Msk                            (0x1UL << ETH_DMACxSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACxSR_RWT                                ETH_DMACxSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACxSR_RPS_Pos                            (8U)
+#define ETH_DMACxSR_RPS_Msk                            (0x1UL << ETH_DMACxSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACxSR_RPS                                ETH_DMACxSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACxSR_RBU_Pos                            (7U)
+#define ETH_DMACxSR_RBU_Msk                            (0x1UL << ETH_DMACxSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACxSR_RBU                                ETH_DMACxSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACxSR_RI_Pos                             (6U)
+#define ETH_DMACxSR_RI_Msk                             (0x1UL << ETH_DMACxSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACxSR_RI                                 ETH_DMACxSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACxSR_TBU_Pos                            (2U)
+#define ETH_DMACxSR_TBU_Msk                            (0x1UL << ETH_DMACxSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACxSR_TBU                                ETH_DMACxSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACxSR_TPS_Pos                            (1U)
+#define ETH_DMACxSR_TPS_Msk                            (0x1UL << ETH_DMACxSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSR_TPS                                ETH_DMACxSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACxSR_TI_Pos                             (0U)
+#define ETH_DMACxSR_TI_Msk                             (0x1UL << ETH_DMACxSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSR_TI                                 ETH_DMACxSR_TI_Msk        /* Transmit Interrupt */
+
+/************ Bit definition for Ethernet DMA Channel x missed frame count Register   ***************/
+#define ETH_DMACxMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACxMFCR_MFCO_Msk                         (0x1UL << ETH_DMACxMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACxMFCR_MFCO                             ETH_DMACxMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACxMFCR_MFC_Pos                          (0U)
+#define ETH_DMACxMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACxMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACxMFCR_MFC                              ETH_DMACxMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_RTSR1 register  *****************/
+#define EXTI_RTSR1_RT0_Pos           (0U)
+#define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
+#define EXTI_RTSR1_RT1_Pos           (1U)
+#define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
+#define EXTI_RTSR1_RT2_Pos           (2U)
+#define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
+#define EXTI_RTSR1_RT3_Pos           (3U)
+#define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
+#define EXTI_RTSR1_RT4_Pos           (4U)
+#define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
+#define EXTI_RTSR1_RT5_Pos           (5U)
+#define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
+#define EXTI_RTSR1_RT6_Pos           (6U)
+#define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
+#define EXTI_RTSR1_RT7_Pos           (7U)
+#define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
+#define EXTI_RTSR1_RT8_Pos           (8U)
+#define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
+#define EXTI_RTSR1_RT9_Pos           (9U)
+#define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
+#define EXTI_RTSR1_RT10_Pos          (10U)
+#define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
+#define EXTI_RTSR1_RT11_Pos          (11U)
+#define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
+#define EXTI_RTSR1_RT12_Pos          (12U)
+#define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
+#define EXTI_RTSR1_RT13_Pos          (13U)
+#define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
+#define EXTI_RTSR1_RT14_Pos          (14U)
+#define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
+#define EXTI_RTSR1_RT15_Pos          (15U)
+#define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
+#define EXTI_RTSR1_RT20_Pos          (20U)
+#define EXTI_RTSR1_RT20_Msk          (0x1UL << EXTI_RTSR1_RT20_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20              EXTI_RTSR1_RT20_Msk                       /*!< Rising trigger configuration for input line 20 */
+#define EXTI_RTSR1_RT21_Pos          (21U)
+#define EXTI_RTSR1_RT21_Msk          (0x1UL << EXTI_RTSR1_RT21_Pos)            /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21              EXTI_RTSR1_RT21_Msk                       /*!< Rising trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_FTSR1 register  *****************/
+#define EXTI_FTSR1_FT0_Pos           (0U)
+#define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
+#define EXTI_FTSR1_FT1_Pos           (1U)
+#define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
+#define EXTI_FTSR1_FT2_Pos           (2U)
+#define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
+#define EXTI_FTSR1_FT3_Pos           (3U)
+#define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
+#define EXTI_FTSR1_FT4_Pos           (4U)
+#define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
+#define EXTI_FTSR1_FT5_Pos           (5U)
+#define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
+#define EXTI_FTSR1_FT6_Pos           (6U)
+#define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
+#define EXTI_FTSR1_FT7_Pos           (7U)
+#define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
+#define EXTI_FTSR1_FT8_Pos           (8U)
+#define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
+#define EXTI_FTSR1_FT9_Pos           (9U)
+#define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
+#define EXTI_FTSR1_FT10_Pos          (10U)
+#define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
+#define EXTI_FTSR1_FT11_Pos          (11U)
+#define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
+#define EXTI_FTSR1_FT12_Pos          (12U)
+#define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
+#define EXTI_FTSR1_FT13_Pos          (13U)
+#define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
+#define EXTI_FTSR1_FT14_Pos          (14U)
+#define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
+#define EXTI_FTSR1_FT15_Pos          (15U)
+#define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
+#define EXTI_FTSR1_FT20_Pos          (20U)
+#define EXTI_FTSR1_FT20_Msk          (0x1UL << EXTI_FTSR1_FT20_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20              EXTI_FTSR1_FT20_Msk                       /*!< Falling trigger configuration for input line 20 */
+#define EXTI_FTSR1_FT21_Pos          (21U)
+#define EXTI_FTSR1_FT21_Msk          (0x1UL << EXTI_FTSR1_FT21_Pos)            /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21              EXTI_FTSR1_FT21_Msk                       /*!< Falling trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_SWIER1 register  ****************/
+#define EXTI_SWIER1_SWI0_Pos         (0U)
+#define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos         (1U)
+#define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos         (2U)
+#define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos         (3U)
+#define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos         (4U)
+#define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos         (5U)
+#define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos         (6U)
+#define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos         (7U)
+#define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos         (8U)
+#define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos         (9U)
+#define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos        (10U)
+#define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos        (11U)
+#define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos        (12U)
+#define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos        (13U)
+#define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos        (14U)
+#define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos        (15U)
+#define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI20_Pos        (20U)
+#define EXTI_SWIER1_SWI20_Msk        (0x1UL << EXTI_SWIER1_SWI20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20            EXTI_SWIER1_SWI20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos        (21U)
+#define EXTI_SWIER1_SWI21_Msk        (0x1UL << EXTI_SWIER1_SWI21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21            EXTI_SWIER1_SWI21_Msk                     /*!< Software Interrupt on line 21 */
+
+/*******************  Bit definition for EXTI_RPR1 register  ******************/
+#define EXTI_RPR1_RPIF0_Pos          (0U)
+#define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
+#define EXTI_RPR1_RPIF1_Pos          (1U)
+#define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
+#define EXTI_RPR1_RPIF2_Pos          (2U)
+#define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
+#define EXTI_RPR1_RPIF3_Pos          (3U)
+#define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
+#define EXTI_RPR1_RPIF4_Pos          (4U)
+#define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
+#define EXTI_RPR1_RPIF5_Pos          (5U)
+#define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
+#define EXTI_RPR1_RPIF6_Pos          (6U)
+#define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
+#define EXTI_RPR1_RPIF7_Pos          (7U)
+#define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
+#define EXTI_RPR1_RPIF8_Pos          (8U)
+#define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
+#define EXTI_RPR1_RPIF9_Pos          (9U)
+#define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
+#define EXTI_RPR1_RPIF10_Pos         (10U)
+#define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
+#define EXTI_RPR1_RPIF11_Pos         (11U)
+#define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
+#define EXTI_RPR1_RPIF12_Pos         (12U)
+#define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
+#define EXTI_RPR1_RPIF13_Pos         (13U)
+#define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
+#define EXTI_RPR1_RPIF14_Pos         (14U)
+#define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
+#define EXTI_RPR1_RPIF15_Pos         (15U)
+#define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
+#define EXTI_RPR1_RPIF20_Pos         (20U)
+#define EXTI_RPR1_RPIF20_Msk         (0x1UL << EXTI_RPR1_RPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_RPR1_RPIF20             EXTI_RPR1_RPIF20_Msk                      /*!< Rising Pending Interrupt Flag on line 20 */
+#define EXTI_RPR1_RPIF21_Pos         (21U)
+#define EXTI_RPR1_RPIF21_Msk         (0x1UL << EXTI_RPR1_RPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_RPR1_RPIF21             EXTI_RPR1_RPIF21_Msk                      /*!< Rising Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_FPR1 register  ******************/
+#define EXTI_FPR1_FPIF0_Pos          (0U)
+#define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
+#define EXTI_FPR1_FPIF1_Pos          (1U)
+#define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
+#define EXTI_FPR1_FPIF2_Pos          (2U)
+#define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
+#define EXTI_FPR1_FPIF3_Pos          (3U)
+#define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
+#define EXTI_FPR1_FPIF4_Pos          (4U)
+#define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
+#define EXTI_FPR1_FPIF5_Pos          (5U)
+#define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
+#define EXTI_FPR1_FPIF6_Pos          (6U)
+#define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
+#define EXTI_FPR1_FPIF7_Pos          (7U)
+#define EXTI_FPR1_FPIF7_Msk           (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
+#define EXTI_FPR1_FPIF8_Pos          (8U)
+#define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
+#define EXTI_FPR1_FPIF9_Pos          (9U)
+#define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
+#define EXTI_FPR1_FPIF10_Pos         (10U)
+#define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
+#define EXTI_FPR1_FPIF11_Pos         (11U)
+#define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
+#define EXTI_FPR1_FPIF12_Pos         (12U)
+#define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
+#define EXTI_FPR1_FPIF13_Pos         (13U)
+#define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
+#define EXTI_FPR1_FPIF14_Pos         (14U)
+#define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
+#define EXTI_FPR1_FPIF15_Pos         (15U)
+#define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
+#define EXTI_FPR1_FPIF20_Pos         (20U)
+#define EXTI_FPR1_FPIF20_Msk         (0x1UL << EXTI_FPR1_FPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_FPR1_FPIF20             EXTI_FPR1_FPIF20_Msk                      /*!< Falling Pending Interrupt Flag on line 20 */
+#define EXTI_FPR1_FPIF21_Pos         (21U)
+#define EXTI_FPR1_FPIF21_Msk         (0x1UL << EXTI_FPR1_FPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_FPR1_FPIF21             EXTI_FPR1_FPIF21_Msk                      /*!< Falling Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_SECCFGR1 register  ******************/
+#define EXTI_SECCFGR1_SEC0_Pos       (0U)
+#define EXTI_SECCFGR1_SEC0_Msk       (0x1UL << EXTI_SECCFGR1_SEC0_Pos)         /*!< 0x00000001 */
+#define EXTI_SECCFGR1_SEC0           EXTI_SECCFGR1_SEC0_Msk                    /*!< Security enable on line 0 */
+#define EXTI_SECCFGR1_SEC1_Pos       (1U)
+#define EXTI_SECCFGR1_SEC1_Msk       (0x1UL << EXTI_SECCFGR1_SEC1_Pos)         /*!< 0x00000002 */
+#define EXTI_SECCFGR1_SEC1           EXTI_SECCFGR1_SEC1_Msk                    /*!< Security enable on line 1 */
+#define EXTI_SECCFGR1_SEC2_Pos       (2U)
+#define EXTI_SECCFGR1_SEC2_Msk       (0x1UL << EXTI_SECCFGR1_SEC2_Pos)         /*!< 0x00000004 */
+#define EXTI_SECCFGR1_SEC2           EXTI_SECCFGR1_SEC2_Msk                    /*!< Security enable on line 2 */
+#define EXTI_SECCFGR1_SEC3_Pos       (3U)
+#define EXTI_SECCFGR1_SEC3_Msk       (0x1UL << EXTI_SECCFGR1_SEC3_Pos)         /*!< 0x00000008 */
+#define EXTI_SECCFGR1_SEC3           EXTI_SECCFGR1_SEC3_Msk                    /*!< Security enable on line 3 */
+#define EXTI_SECCFGR1_SEC4_Pos       (4U)
+#define EXTI_SECCFGR1_SEC4_Msk       (0x1UL << EXTI_SECCFGR1_SEC4_Pos)         /*!< 0x00000010 */
+#define EXTI_SECCFGR1_SEC4           EXTI_SECCFGR1_SEC4_Msk                    /*!< Security enable on line 4 */
+#define EXTI_SECCFGR1_SEC5_Pos       (5U)
+#define EXTI_SECCFGR1_SEC5_Msk       (0x1UL << EXTI_SECCFGR1_SEC5_Pos)         /*!< 0x00000020 */
+#define EXTI_SECCFGR1_SEC5           EXTI_SECCFGR1_SEC5_Msk                    /*!< Security enable on line 5 */
+#define EXTI_SECCFGR1_SEC6_Pos       (6U)
+#define EXTI_SECCFGR1_SEC6_Msk       (0x1UL << EXTI_SECCFGR1_SEC6_Pos)         /*!< 0x00000040 */
+#define EXTI_SECCFGR1_SEC6           EXTI_SECCFGR1_SEC6_Msk                    /*!< Security enable on line 6 */
+#define EXTI_SECCFGR1_SEC7_Pos       (7U)
+#define EXTI_SECCFGR1_SEC7_Msk       (0x1UL << EXTI_SECCFGR1_SEC7_Pos)         /*!< 0x00000080 */
+#define EXTI_SECCFGR1_SEC7           EXTI_SECCFGR1_SEC7_Msk                    /*!< Security enable on line 7 */
+#define EXTI_SECCFGR1_SEC8_Pos       (8U)
+#define EXTI_SECCFGR1_SEC8_Msk       (0x1UL << EXTI_SECCFGR1_SEC8_Pos)         /*!< 0x00000100 */
+#define EXTI_SECCFGR1_SEC8           EXTI_SECCFGR1_SEC8_Msk                    /*!< Security enable on line 8 */
+#define EXTI_SECCFGR1_SEC9_Pos       (9U)
+#define EXTI_SECCFGR1_SEC9_Msk       (0x1UL << EXTI_SECCFGR1_SEC9_Pos)         /*!< 0x00000200 */
+#define EXTI_SECCFGR1_SEC9           EXTI_SECCFGR1_SEC9_Msk                    /*!< Security enable on line 9 */
+#define EXTI_SECCFGR1_SEC10_Pos      (10U)
+#define EXTI_SECCFGR1_SEC10_Msk      (0x1UL << EXTI_SECCFGR1_SEC10_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR1_SEC10          EXTI_SECCFGR1_SEC10_Msk                   /*!< Security enable on line 10 */
+#define EXTI_SECCFGR1_SEC11_Pos      (11U)
+#define EXTI_SECCFGR1_SEC11_Msk      (0x1UL << EXTI_SECCFGR1_SEC11_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR1_SEC11          EXTI_SECCFGR1_SEC11_Msk                   /*!< Security enable on line 11 */
+#define EXTI_SECCFGR1_SEC12_Pos      (12U)
+#define EXTI_SECCFGR1_SEC12_Msk      (0x1UL << EXTI_SECCFGR1_SEC12_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR1_SEC12          EXTI_SECCFGR1_SEC12_Msk                   /*!< Security enable on line 12 */
+#define EXTI_SECCFGR1_SEC13_Pos      (13U)
+#define EXTI_SECCFGR1_SEC13_Msk      (0x1UL << EXTI_SECCFGR1_SEC13_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR1_SEC13          EXTI_SECCFGR1_SEC13_Msk                   /*!< Security enable on line 13 */
+#define EXTI_SECCFGR1_SEC14_Pos      (14U)
+#define EXTI_SECCFGR1_SEC14_Msk      (0x1UL << EXTI_SECCFGR1_SEC14_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR1_SEC14          EXTI_SECCFGR1_SEC14_Msk                   /*!< Security enable on line 14 */
+#define EXTI_SECCFGR1_SEC15_Pos      (15U)
+#define EXTI_SECCFGR1_SEC15_Msk      (0x1UL << EXTI_SECCFGR1_SEC15_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR1_SEC15          EXTI_SECCFGR1_SEC15_Msk                   /*!< Security enable on line 15 */
+#define EXTI_SECCFGR1_SEC17_Pos      (17U)
+#define EXTI_SECCFGR1_SEC17_Msk      (0x1UL << EXTI_SECCFGR1_SEC17_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR1_SEC17          EXTI_SECCFGR1_SEC17_Msk                   /*!< Security enable on line 17 */
+#define EXTI_SECCFGR1_SEC18_Pos      (18U)
+#define EXTI_SECCFGR1_SEC18_Msk      (0x1UL << EXTI_SECCFGR1_SEC18_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR1_SEC18          EXTI_SECCFGR1_SEC18_Msk                   /*!< Security enable on line 18 */
+#define EXTI_SECCFGR1_SEC19_Pos      (19U)
+#define EXTI_SECCFGR1_SEC19_Msk      (0x1UL << EXTI_SECCFGR1_SEC19_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR1_SEC19          EXTI_SECCFGR1_SEC19_Msk                   /*!< Security enable on line 19 */
+#define EXTI_SECCFGR1_SEC20_Pos      (20U)
+#define EXTI_SECCFGR1_SEC20_Msk      (0x1UL << EXTI_SECCFGR1_SEC20_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR1_SEC20          EXTI_SECCFGR1_SEC20_Msk                   /*!< Security enable on line 20 */
+#define EXTI_SECCFGR1_SEC21_Pos      (21U)
+#define EXTI_SECCFGR1_SEC21_Msk      (0x1UL << EXTI_SECCFGR1_SEC21_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR1_SEC21          EXTI_SECCFGR1_SEC21_Msk                   /*!< Security enable on line 21 */
+#define EXTI_SECCFGR1_SEC22_Pos      (22U)
+#define EXTI_SECCFGR1_SEC22_Msk      (0x1UL << EXTI_SECCFGR1_SEC22_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR1_SEC22          EXTI_SECCFGR1_SEC22_Msk                   /*!< Security enable on line 22 */
+#define EXTI_SECCFGR1_SEC23_Pos      (23U)
+#define EXTI_SECCFGR1_SEC23_Msk      (0x1UL << EXTI_SECCFGR1_SEC23_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR1_SEC23          EXTI_SECCFGR1_SEC23_Msk                   /*!< Security enable on line 23 */
+#define EXTI_SECCFGR1_SEC24_Pos      (24U)
+#define EXTI_SECCFGR1_SEC24_Msk      (0x1UL << EXTI_SECCFGR1_SEC24_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR1_SEC24          EXTI_SECCFGR1_SEC24_Msk                   /*!< Security enable on line 24 */
+#define EXTI_SECCFGR1_SEC25_Pos      (25U)
+#define EXTI_SECCFGR1_SEC25_Msk      (0x1UL << EXTI_SECCFGR1_SEC25_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR1_SEC25          EXTI_SECCFGR1_SEC25_Msk                   /*!< Security enable on line 25 */
+#define EXTI_SECCFGR1_SEC26_Pos      (26U)
+#define EXTI_SECCFGR1_SEC26_Msk      (0x1UL << EXTI_SECCFGR1_SEC26_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR1_SEC26          EXTI_SECCFGR1_SEC26_Msk                   /*!< Security enable on line 26 */
+#define EXTI_SECCFGR1_SEC27_Pos      (27U)
+#define EXTI_SECCFGR1_SEC27_Msk      (0x1UL << EXTI_SECCFGR1_SEC27_Pos)        /*!< 0x08000000 */
+#define EXTI_SECCFGR1_SEC27          EXTI_SECCFGR1_SEC27_Msk                   /*!< Security enable on line 27 */
+#define EXTI_SECCFGR1_SEC28_Pos      (28U)
+#define EXTI_SECCFGR1_SEC28_Msk      (0x1UL << EXTI_SECCFGR1_SEC28_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR1_SEC28          EXTI_SECCFGR1_SEC28_Msk                   /*!< Security enable on line 28 */
+#define EXTI_SECCFGR1_SEC29_Pos      (29U)
+#define EXTI_SECCFGR1_SEC29_Msk      (0x1UL << EXTI_SECCFGR1_SEC29_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR1_SEC29          EXTI_SECCFGR1_SEC29_Msk                   /*!< Security enable on line 29 */
+#define EXTI_SECCFGR1_SEC30_Pos      (30U)
+#define EXTI_SECCFGR1_SEC30_Msk      (0x1UL << EXTI_SECCFGR1_SEC30_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR1_SEC30          EXTI_SECCFGR1_SEC30_Msk                   /*!< Security enable on line 30 */
+#define EXTI_SECCFGR1_SEC31_Pos      (31U)
+#define EXTI_SECCFGR1_SEC31_Msk      (0x1UL << EXTI_SECCFGR1_SEC31_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR1_SEC31          EXTI_SECCFGR1_SEC31_Msk                   /*!< Security enable on line 31 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR1 register  ******************/
+#define EXTI_PRIVCFGR1_PRIV0_Pos     (0U)
+#define EXTI_PRIVCFGR1_PRIV0_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos)       /*!< 0x00000001 */
+#define EXTI_PRIVCFGR1_PRIV0         EXTI_PRIVCFGR1_PRIV0_Msk                  /*!< Privilege enable on line 0 */
+#define EXTI_PRIVCFGR1_PRIV1_Pos     (1U)
+#define EXTI_PRIVCFGR1_PRIV1_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos)       /*!< 0x00000002 */
+#define EXTI_PRIVCFGR1_PRIV1         EXTI_PRIVCFGR1_PRIV1_Msk                  /*!< Privilege enable on line 1 */
+#define EXTI_PRIVCFGR1_PRIV2_Pos     (2U)
+#define EXTI_PRIVCFGR1_PRIV2_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos)       /*!< 0x00000004 */
+#define EXTI_PRIVCFGR1_PRIV2         EXTI_PRIVCFGR1_PRIV2_Msk                  /*!< Privilege enable on line 2 */
+#define EXTI_PRIVCFGR1_PRIV3_Pos     (3U)
+#define EXTI_PRIVCFGR1_PRIV3_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos)       /*!< 0x00000008 */
+#define EXTI_PRIVCFGR1_PRIV3         EXTI_PRIVCFGR1_PRIV3_Msk                  /*!< Privilege enable on line 3 */
+#define EXTI_PRIVCFGR1_PRIV4_Pos     (4U)
+#define EXTI_PRIVCFGR1_PRIV4_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos)       /*!< 0x00000010 */
+#define EXTI_PRIVCFGR1_PRIV4         EXTI_PRIVCFGR1_PRIV4_Msk                  /*!< Privilege enable on line 4 */
+#define EXTI_PRIVCFGR1_PRIV5_Pos     (5U)
+#define EXTI_PRIVCFGR1_PRIV5_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos)       /*!< 0x00000020 */
+#define EXTI_PRIVCFGR1_PRIV5         EXTI_PRIVCFGR1_PRIV5_Msk                  /*!< Privilege enable on line 5 */
+#define EXTI_PRIVCFGR1_PRIV6_Pos     (6U)
+#define EXTI_PRIVCFGR1_PRIV6_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos)       /*!< 0x00000040 */
+#define EXTI_PRIVCFGR1_PRIV6         EXTI_PRIVCFGR1_PRIV6_Msk                  /*!< Privilege enable on line 6 */
+#define EXTI_PRIVCFGR1_PRIV7_Pos     (7U)
+#define EXTI_PRIVCFGR1_PRIV7_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos)       /*!< 0x00000080 */
+#define EXTI_PRIVCFGR1_PRIV7         EXTI_PRIVCFGR1_PRIV7_Msk                  /*!< Privilege enable on line 7 */
+#define EXTI_PRIVCFGR1_PRIV8_Pos     (8U)
+#define EXTI_PRIVCFGR1_PRIV8_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos)       /*!< 0x00000100 */
+#define EXTI_PRIVCFGR1_PRIV8         EXTI_PRIVCFGR1_PRIV8_Msk                  /*!< Privilege enable on line 8 */
+#define EXTI_PRIVCFGR1_PRIV9_Pos     (9U)
+#define EXTI_PRIVCFGR1_PRIV9_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos)       /*!< 0x00000200 */
+#define EXTI_PRIVCFGR1_PRIV9         EXTI_PRIVCFGR1_PRIV9_Msk                  /*!< Privilege enable on line 9 */
+#define EXTI_PRIVCFGR1_PRIV10_Pos    (10U)
+#define EXTI_PRIVCFGR1_PRIV10_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR1_PRIV10        EXTI_PRIVCFGR1_PRIV10_Msk                 /*!< Privilege enable on line 10 */
+#define EXTI_PRIVCFGR1_PRIV11_Pos    (11U)
+#define EXTI_PRIVCFGR1_PRIV11_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR1_PRIV11        EXTI_PRIVCFGR1_PRIV11_Msk                 /*!< Privilege enable on line 11 */
+#define EXTI_PRIVCFGR1_PRIV12_Pos    (12U)
+#define EXTI_PRIVCFGR1_PRIV12_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR1_PRIV12        EXTI_PRIVCFGR1_PRIV12_Msk                 /*!< Privilege enable on line 12 */
+#define EXTI_PRIVCFGR1_PRIV13_Pos    (13U)
+#define EXTI_PRIVCFGR1_PRIV13_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR1_PRIV13        EXTI_PRIVCFGR1_PRIV13_Msk                 /*!< Privilege enable on line 13 */
+#define EXTI_PRIVCFGR1_PRIV14_Pos    (14U)
+#define EXTI_PRIVCFGR1_PRIV14_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR1_PRIV14        EXTI_PRIVCFGR1_PRIV14_Msk                 /*!< Privilege enable on line 14 */
+#define EXTI_PRIVCFGR1_PRIV15_Pos    (15U)
+#define EXTI_PRIVCFGR1_PRIV15_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR1_PRIV15        EXTI_PRIVCFGR1_PRIV15_Msk                 /*!< Privilege enable on line 15 */
+#define EXTI_PRIVCFGR1_PRIV17_Pos    (17U)
+#define EXTI_PRIVCFGR1_PRIV17_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR1_PRIV17        EXTI_PRIVCFGR1_PRIV17_Msk                 /*!< Privilege enable on line 17 */
+#define EXTI_PRIVCFGR1_PRIV18_Pos    (18U)
+#define EXTI_PRIVCFGR1_PRIV18_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR1_PRIV18        EXTI_PRIVCFGR1_PRIV18_Msk                 /*!< Privilege enable on line 18 */
+#define EXTI_PRIVCFGR1_PRIV19_Pos    (19U)
+#define EXTI_PRIVCFGR1_PRIV19_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR1_PRIV19        EXTI_PRIVCFGR1_PRIV19_Msk                 /*!< Privilege enable on line 19 */
+#define EXTI_PRIVCFGR1_PRIV20_Pos    (20U)
+#define EXTI_PRIVCFGR1_PRIV20_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR1_PRIV20        EXTI_PRIVCFGR1_PRIV20_Msk                 /*!< Privilege enable on line 20 */
+#define EXTI_PRIVCFGR1_PRIV21_Pos    (21U)
+#define EXTI_PRIVCFGR1_PRIV21_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR1_PRIV21        EXTI_PRIVCFGR1_PRIV21_Msk                 /*!< Privilege enable on line 21 */
+#define EXTI_PRIVCFGR1_PRIV22_Pos    (22U)
+#define EXTI_PRIVCFGR1_PRIV22_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR1_PRIV22        EXTI_PRIVCFGR1_PRIV22_Msk                 /*!< Privilege enable on line 22 */
+#define EXTI_PRIVCFGR1_PRIV23_Pos    (23U)
+#define EXTI_PRIVCFGR1_PRIV23_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR1_PRIV23        EXTI_PRIVCFGR1_PRIV23_Msk                 /*!< Privilege enable on line 23 */
+#define EXTI_PRIVCFGR1_PRIV24_Pos    (24U)
+#define EXTI_PRIVCFGR1_PRIV24_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR1_PRIV24        EXTI_PRIVCFGR1_PRIV24_Msk                 /*!< Privilege enable on line 24 */
+#define EXTI_PRIVCFGR1_PRIV25_Pos    (25U)
+#define EXTI_PRIVCFGR1_PRIV25_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR1_PRIV25        EXTI_PRIVCFGR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
+#define EXTI_PRIVCFGR1_PRIV26_Pos    (26U)
+#define EXTI_PRIVCFGR1_PRIV26_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR1_PRIV26        EXTI_PRIVCFGR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
+#define EXTI_PRIVCFGR1_PRIV27_Pos    (27U)
+#define EXTI_PRIVCFGR1_PRIV27_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos)      /*!< 0x08000000 */
+#define EXTI_PRIVCFGR1_PRIV27        EXTI_PRIVCFGR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
+#define EXTI_PRIVCFGR1_PRIV28_Pos    (28U)
+#define EXTI_PRIVCFGR1_PRIV28_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR1_PRIV28        EXTI_PRIVCFGR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
+#define EXTI_PRIVCFGR1_PRIV29_Pos    (29U)
+#define EXTI_PRIVCFGR1_PRIV29_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR1_PRIV29        EXTI_PRIVCFGR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
+#define EXTI_PRIVCFGR1_PRIV30_Pos    (30U)
+#define EXTI_PRIVCFGR1_PRIV30_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR1_PRIV30        EXTI_PRIVCFGR1_PRIV30_Msk                 /*!< Privilege enable on line 30 */
+#define EXTI_PRIVCFGR1_PRIV31_Pos    (31U)
+#define EXTI_PRIVCFGR1_PRIV31_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR1_PRIV31        EXTI_PRIVCFGR1_PRIV31_Msk                 /*!< Privilege enable on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR2 register  *****************/
+#define EXTI_RTSR2_RT39_Pos          (7U)
+#define EXTI_RTSR2_RT39_Msk          (0x1UL << EXTI_RTSR2_RT39_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR2_RT39              EXTI_RTSR2_RT39_Msk                       /*!< Rising trigger configuration for input line 39 */
+#define EXTI_RTSR2_RT40_Pos          (8U)
+#define EXTI_RTSR2_RT40_Msk          (0x1UL << EXTI_RTSR2_RT40_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR2_RT40              EXTI_RTSR2_RT40_Msk                       /*!< Rising trigger configuration for input line 40 */
+#define EXTI_RTSR2_RT51_Pos          (19U)
+#define EXTI_RTSR2_RT51_Msk          (0x1UL << EXTI_RTSR2_RT51_Pos)            /*!< 0x00080000 */
+#define EXTI_RTSR2_RT51              EXTI_RTSR2_RT51_Msk                       /*!< Rising trigger configuration for input line 51 */
+#define EXTI_RTSR2_RT54_Pos          (22U)
+#define EXTI_RTSR2_RT54_Msk          (0x1UL << EXTI_RTSR2_RT54_Pos)            /*!< 0x00400000 */
+#define EXTI_RTSR2_RT54              EXTI_RTSR2_RT54_Msk                       /*!< Rising trigger configuration for input line 54 */
+#define EXTI_RTSR2_RT56_Pos          (24U)
+#define EXTI_RTSR2_RT56_Msk          (0x1UL << EXTI_RTSR2_RT56_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR2_RT56              EXTI_RTSR2_RT56_Msk                       /*!< Rising trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_FTSR2 register  *****************/
+#define EXTI_FTSR2_FT39_Pos          (7U)
+#define EXTI_FTSR2_FT39_Msk          (0x1UL << EXTI_FTSR2_FT39_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR2_FT39              EXTI_FTSR2_FT39_Msk                       /*!< Falling trigger configuration for input line 39 */
+#define EXTI_FTSR2_FT40_Pos          (8U)
+#define EXTI_FTSR2_FT40_Msk          (0x1UL << EXTI_FTSR2_FT40_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR2_FT40              EXTI_FTSR2_FT40_Msk                       /*!< Falling trigger configuration for input line 40 */
+#define EXTI_FTSR2_FT51_Pos          (19U)
+#define EXTI_FTSR2_FT51_Msk          (0x1UL << EXTI_FTSR2_FT51_Pos)            /*!< 0x00080000 */
+#define EXTI_FTSR2_FT51              EXTI_FTSR2_FT51_Msk                       /*!< Falling trigger configuration for input line 51 */
+#define EXTI_FTSR2_FT54_Pos          (22U)
+#define EXTI_FTSR2_FT54_Msk          (0x1UL << EXTI_FTSR2_FT54_Pos)            /*!< 0x00400000 */
+#define EXTI_FTSR2_FT54              EXTI_FTSR2_FT54_Msk                       /*!< Falling trigger configuration for input line 54 */
+#define EXTI_FTSR2_FT56_Pos          (24U)
+#define EXTI_FTSR2_FT56_Msk          (0x1UL << EXTI_FTSR2_FT56_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR2_FT56              EXTI_FTSR2_FT56_Msk                       /*!< Falling trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_SWIER2 register  ****************/
+#define EXTI_SWIER2_SWI39_Pos        (7U)
+#define EXTI_SWIER2_SWI39_Msk        (0x1UL << EXTI_SWIER2_SWI39_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER2_SWI39            EXTI_SWIER2_SWI39_Msk                     /*!< Software Interrupt on line 39 */
+#define EXTI_SWIER2_SWI40_Pos        (8U)
+#define EXTI_SWIER2_SWI40_Msk        (0x1UL << EXTI_SWIER2_SWI40_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER2_SWI40            EXTI_SWIER2_SWI40_Msk                     /*!< Software Interrupt on line 40 */
+#define EXTI_SWIER2_SWI51_Pos        (19U)
+#define EXTI_SWIER2_SWI51_Msk        (0x1UL << EXTI_SWIER2_SWI51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWI51            EXTI_SWIER2_SWI51_Msk                     /*!< Software Interrupt on line 51 */
+#define EXTI_SWIER2_SWI54_Pos        (22U)
+#define EXTI_SWIER2_SWI54_Msk        (0x1UL << EXTI_SWIER2_SWI54_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER2_SWI54            EXTI_SWIER2_SWI54_Msk                     /*!< Software Interrupt on line 54 */
+#define EXTI_SWIER2_SWI56_Pos        (24U)
+#define EXTI_SWIER2_SWI56_Msk        (0x1UL << EXTI_SWIER2_SWI56_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER2_SWI56            EXTI_SWIER2_SWI56_Msk                     /*!< Software Interrupt on line 56 */
+
+/*******************  Bit definition for EXTI_RPR2 register  ******************/
+#define EXTI_RPR2_RPIF39_Pos         (7U)
+#define EXTI_RPR2_RPIF39_Msk         (0x1UL << EXTI_RPR2_RPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR2_RPIF39             EXTI_RPR2_RPIF39_Msk                      /*!< Rising Pending Interrupt Flag on line 39 */
+#define EXTI_RPR2_RPIF40_Pos         (8U)
+#define EXTI_RPR2_RPIF40_Msk         (0x1UL << EXTI_RPR2_RPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR2_RPIF40             EXTI_RPR2_RPIF40_Msk                      /*!< Rising Pending Interrupt Flag on line 40 */
+#define EXTI_RPR2_RPIF51_Pos         (19U)
+#define EXTI_RPR2_RPIF51_Msk         (0x1UL << EXTI_RPR2_RPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_RPR2_RPIF51             EXTI_RPR2_RPIF51_Msk                      /*!< Rising Pending Interrupt Flag on line 51 */
+#define EXTI_RPR2_RPIF54_Pos         (22U)
+#define EXTI_RPR2_RPIF54_Msk         (0x1UL << EXTI_RPR2_RPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_RPR2_RPIF54             EXTI_RPR2_RPIF54_Msk                      /*!< Rising Pending Interrupt Flag on line 54 */
+#define EXTI_RPR2_RPIF56_Pos         (24U)
+#define EXTI_RPR2_RPIF56_Msk         (0x1UL << EXTI_RPR2_RPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_RPR2_RPIF56             EXTI_RPR2_RPIF56_Msk                      /*!< Rising Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_FPR2 register  ******************/
+#define EXTI_FPR2_FPIF39_Pos         (7U)
+#define EXTI_FPR2_FPIF39_Msk         (0x1UL << EXTI_FPR2_FPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR2_FPIF39             EXTI_FPR2_FPIF39_Msk                      /*!< Falling Pending Interrupt Flag on line 39 */
+#define EXTI_FPR2_FPIF40_Pos         (8U)
+#define EXTI_FPR2_FPIF40_Msk         (0x1UL << EXTI_FPR2_FPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR2_FPIF40             EXTI_FPR2_FPIF40_Msk                      /*!< Falling Pending Interrupt Flag on line 40 */
+#define EXTI_FPR2_FPIF51_Pos         (19U)
+#define EXTI_FPR2_FPIF51_Msk         (0x1UL << EXTI_FPR2_FPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_FPR2_FPIF51             EXTI_FPR2_FPIF51_Msk                      /*!< Falling Pending Interrupt Flag on line 51 */
+#define EXTI_FPR2_FPIF54_Pos         (22U)
+#define EXTI_FPR2_FPIF54_Msk         (0x1UL << EXTI_FPR2_FPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_FPR2_FPIF54             EXTI_FPR2_FPIF54_Msk                      /*!< Falling Pending Interrupt Flag on line 54 */
+#define EXTI_FPR2_FPIF56_Pos         (24U)
+#define EXTI_FPR2_FPIF56_Msk         (0x1UL << EXTI_FPR2_FPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_FPR2_FPIF56             EXTI_FPR2_FPIF56_Msk                      /*!< Falling Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_SECCFGR2 register  ******************/
+#define EXTI_SECCFGR2_SEC32_Pos      (0U)
+#define EXTI_SECCFGR2_SEC32_Msk      (0x1UL << EXTI_SECCFGR2_SEC32_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR2_SEC32          EXTI_SECCFGR2_SEC32_Msk                   /*!< Security enable on line 32 */
+#define EXTI_SECCFGR2_SEC33_Pos      (1U)
+#define EXTI_SECCFGR2_SEC33_Msk      (0x1UL << EXTI_SECCFGR2_SEC33_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR2_SEC33          EXTI_SECCFGR2_SEC33_Msk                   /*!< Security enable on line 33 */
+#define EXTI_SECCFGR2_SEC34_Pos      (2U)
+#define EXTI_SECCFGR2_SEC34_Msk      (0x1UL << EXTI_SECCFGR2_SEC34_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR2_SEC34          EXTI_SECCFGR2_SEC34_Msk                   /*!< Security enable on line 34 */
+#define EXTI_SECCFGR2_SEC35_Pos      (3U)
+#define EXTI_SECCFGR2_SEC35_Msk      (0x1UL << EXTI_SECCFGR2_SEC35_Pos)        /*!< 0x00000008 */
+#define EXTI_SECCFGR2_SEC35          EXTI_SECCFGR2_SEC35_Msk                   /*!< Security enable on line 35 */
+#define EXTI_SECCFGR2_SEC36_Pos      (4U)
+#define EXTI_SECCFGR2_SEC36_Msk      (0x1UL << EXTI_SECCFGR2_SEC36_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR2_SEC36          EXTI_SECCFGR2_SEC36_Msk                   /*!< Security enable on line 36 */
+#define EXTI_SECCFGR2_SEC37_Pos      (5U)
+#define EXTI_SECCFGR2_SEC37_Msk      (0x1UL << EXTI_SECCFGR2_SEC37_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR2_SEC37          EXTI_SECCFGR2_SEC37_Msk                   /*!< Security enable on line 37 */
+#define EXTI_SECCFGR2_SEC38_Pos      (6U)
+#define EXTI_SECCFGR2_SEC38_Msk      (0x1UL << EXTI_SECCFGR2_SEC38_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR2_SEC38          EXTI_SECCFGR2_SEC38_Msk                   /*!< Security enable on line 38 */
+#define EXTI_SECCFGR2_SEC39_Pos      (7U)
+#define EXTI_SECCFGR2_SEC39_Msk      (0x1UL << EXTI_SECCFGR2_SEC39_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR2_SEC39          EXTI_SECCFGR2_SEC39_Msk                   /*!< Security enable on line 39 */
+#define EXTI_SECCFGR2_SEC40_Pos      (8U)
+#define EXTI_SECCFGR2_SEC40_Msk      (0x1UL << EXTI_SECCFGR2_SEC40_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR2_SEC40          EXTI_SECCFGR2_SEC40_Msk                   /*!< Security enable on line 40 */
+#define EXTI_SECCFGR2_SEC41_Pos      (9U)
+#define EXTI_SECCFGR2_SEC41_Msk      (0x1UL << EXTI_SECCFGR2_SEC41_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR2_SEC41          EXTI_SECCFGR2_SEC41_Msk                   /*!< Security enable on line 41 */
+#define EXTI_SECCFGR2_SEC42_Pos      (10U)
+#define EXTI_SECCFGR2_SEC42_Msk      (0x1UL << EXTI_SECCFGR2_SEC42_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR2_SEC42          EXTI_SECCFGR2_SEC42_Msk                   /*!< Security enable on line 42 */
+#define EXTI_SECCFGR2_SEC43_Pos      (11U)
+#define EXTI_SECCFGR2_SEC43_Msk      (0x1UL << EXTI_SECCFGR2_SEC43_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR2_SEC43          EXTI_SECCFGR2_SEC43_Msk                   /*!< Security enable on line 43 */
+#define EXTI_SECCFGR2_SEC44_Pos      (12U)
+#define EXTI_SECCFGR2_SEC44_Msk      (0x1UL << EXTI_SECCFGR2_SEC44_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR2_SEC44          EXTI_SECCFGR2_SEC44_Msk                   /*!< Security enable on line 44 */
+#define EXTI_SECCFGR2_SEC45_Pos      (13U)
+#define EXTI_SECCFGR2_SEC45_Msk      (0x1UL << EXTI_SECCFGR2_SEC45_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR2_SEC45          EXTI_SECCFGR2_SEC45                       /*!< Security enable on line 45 */
+#define EXTI_SECCFGR2_SEC46_Pos      (14U)
+#define EXTI_SECCFGR2_SEC46_Msk      (0x1UL << EXTI_SECCFGR2_SEC46_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR2_SEC46          EXTI_SECCFGR2_SEC46_Msk                   /*!< Security enable on line 46 */
+#define EXTI_SECCFGR2_SEC47_Pos      (15U)
+#define EXTI_SECCFGR2_SEC47_Msk      (0x1UL << EXTI_SECCFGR2_SEC47_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR2_SEC47          EXTI_SECCFGR2_SEC47_Msk                   /*!< Security enable on line 47 */
+#define EXTI_SECCFGR2_SEC48_Pos      (16U)
+#define EXTI_SECCFGR2_SEC48_Msk      (0x1UL << EXTI_SECCFGR2_SEC48_Pos)        /*!< 0x00010000 */
+#define EXTI_SECCFGR2_SEC48          EXTI_SECCFGR2_SEC48_Msk                   /*!< Security enable on line 48 */
+#define EXTI_SECCFGR2_SEC49_Pos      (17U)
+#define EXTI_SECCFGR2_SEC49_Msk      (0x1UL << EXTI_SECCFGR2_SEC49_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR2_SEC49          EXTI_SECCFGR2_SEC49_Msk                   /*!< Security enable on line 49 */
+#define EXTI_SECCFGR2_SEC50_Pos      (18U)
+#define EXTI_SECCFGR2_SEC50_Msk      (0x1UL << EXTI_SECCFGR2_SEC50_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR2_SEC50          EXTI_SECCFGR2_SEC50_Msk                   /*!< Security enable on line 50 */
+#define EXTI_SECCFGR2_SEC51_Pos      (19U)
+#define EXTI_SECCFGR2_SEC51_Msk      (0x1UL << EXTI_SECCFGR2_SEC51_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR2_SEC51          EXTI_SECCFGR2_SEC51_Msk                   /*!< Security enable on line 51 */
+#define EXTI_SECCFGR2_SEC52_Pos      (20U)
+#define EXTI_SECCFGR2_SEC52_Msk      (0x1UL << EXTI_SECCFGR2_SEC52_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR2_SEC52          EXTI_SECCFGR2_SEC52_Msk                   /*!< Security enable on line 52 */
+#define EXTI_SECCFGR2_SEC53_Pos      (21U)
+#define EXTI_SECCFGR2_SEC53_Msk      (0x1UL << EXTI_SECCFGR2_SEC53_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR2_SEC53          EXTI_SECCFGR2_SEC53_Msk                   /*!< Security enable on line 53 */
+#define EXTI_SECCFGR2_SEC54_Pos      (22U)
+#define EXTI_SECCFGR2_SEC54_Msk      (0x1UL << EXTI_SECCFGR2_SEC54_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR2_SEC54          EXTI_SECCFGR2_SEC54_Msk                   /*!< Security enable on line 54 */
+#define EXTI_SECCFGR2_SEC55_Pos      (23U)
+#define EXTI_SECCFGR2_SEC55_Msk      (0x1UL << EXTI_SECCFGR2_SEC55_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR2_SEC55          EXTI_SECCFGR2_SEC55_Msk                   /*!< Security enable on line 55 */
+#define EXTI_SECCFGR2_SEC56_Pos      (24U)
+#define EXTI_SECCFGR2_SEC56_Msk      (0x1UL << EXTI_SECCFGR2_SEC56_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR2_SEC56          EXTI_SECCFGR2_SEC56_Msk                   /*!< Security enable on line 56 */
+#define EXTI_SECCFGR2_SEC57_Pos      (25U)
+#define EXTI_SECCFGR2_SEC57_Msk      (0x1UL << EXTI_SECCFGR2_SEC57_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR2_SEC57          EXTI_SECCFGR2_SEC57_Msk                   /*!< Security enable on line 57 */
+#define EXTI_SECCFGR2_SEC58_Pos      (26U)
+#define EXTI_SECCFGR2_SEC58_Msk      (0x1UL << EXTI_SECCFGR2_SEC58_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR2_SEC58          EXTI_SECCFGR2_SEC58_Msk                   /*!< Security enable on line 58 */
+#define EXTI_SECCFGR2_SEC60_Pos      (28U)
+#define EXTI_SECCFGR2_SEC60_Msk      (0x1UL << EXTI_SECCFGR2_SEC60_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR2_SEC60          EXTI_SECCFGR2_SEC60_Msk                   /*!< Security enable on line 60 */
+#define EXTI_SECCFGR2_SEC61_Pos      (29U)
+#define EXTI_SECCFGR2_SEC61_Msk      (0x1UL << EXTI_SECCFGR2_SEC61_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR2_SEC61          EXTI_SECCFGR2_SEC61_Msk                   /*!< Security enable on line 61 */
+#define EXTI_SECCFGR2_SEC62_Pos      (30U)
+#define EXTI_SECCFGR2_SEC62_Msk      (0x1UL << EXTI_SECCFGR2_SEC62_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR2_SEC62          EXTI_SECCFGR2_SEC62_Msk                   /*!< Security enable on line 62 */
+#define EXTI_SECCFGR2_SEC63_Pos      (31U)
+#define EXTI_SECCFGR2_SEC63_Msk      (0x1UL << EXTI_SECCFGR2_SEC63_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR2_SEC63          EXTI_SECCFGR2_SEC63_Msk                   /*!< Security enable on line 63 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR2 register  ******************/
+#define EXTI_PRIVCFGR2_PRIV32_Pos    (0U)
+#define EXTI_PRIVCFGR2_PRIV32_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR2_PRIV32        EXTI_PRIVCFGR2_PRIV32_Msk                 /*!< Privilege enable on line 32 */
+#define EXTI_PRIVCFGR2_PRIV33_Pos    (1U)
+#define EXTI_PRIVCFGR2_PRIV33_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR2_PRIV33        EXTI_PRIVCFGR2_PRIV33_Msk                 /*!< Privilege enable on line 33 */
+#define EXTI_PRIVCFGR2_PRIV34_Pos    (2U)
+#define EXTI_PRIVCFGR2_PRIV34_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR2_PRIV34        EXTI_PRIVCFGR2_PRIV34_Msk                 /*!< Privilege enable on line 34 */
+#define EXTI_PRIVCFGR2_PRIV35_Pos    (3U)
+#define EXTI_PRIVCFGR2_PRIV35_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos)      /*!< 0x00000008 */
+#define EXTI_PRIVCFGR2_PRIV35        EXTI_PRIVCFGR2_PRIV35_Msk                 /*!< Privilege enable on line 35 */
+#define EXTI_PRIVCFGR2_PRIV36_Pos    (4U)
+#define EXTI_PRIVCFGR2_PRIV36_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR2_PRIV36        EXTI_PRIVCFGR2_PRIV36_Msk                 /*!< Privilege enable on line 36 */
+#define EXTI_PRIVCFGR2_PRIV37_Pos    (5U)
+#define EXTI_PRIVCFGR2_PRIV37_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR2_PRIV37        EXTI_PRIVCFGR2_PRIV37_Msk                 /*!< Privilege enable on line 37 */
+#define EXTI_PRIVCFGR2_PRIV38_Pos    (6U)
+#define EXTI_PRIVCFGR2_PRIV38_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR2_PRIV38        EXTI_PRIVCFGR2_PRIV38_Msk                 /*!< Privilege enable on line 38 */
+#define EXTI_PRIVCFGR2_PRIV39_Pos    (7U)
+#define EXTI_PRIVCFGR2_PRIV39_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR2_PRIV39        EXTI_PRIVCFGR2_PRIV39_Msk                 /*!< Privilege enable on line 39 */
+#define EXTI_PRIVCFGR2_PRIV40_Pos    (8U)
+#define EXTI_PRIVCFGR2_PRIV40_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV40_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR2_PRIV40        EXTI_PRIVCFGR2_PRIV40_Msk                 /*!< Privilege enable on line 40 */
+#define EXTI_PRIVCFGR2_PRIV41_Pos    (9U)
+#define EXTI_PRIVCFGR2_PRIV41_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV41_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR2_PRIV41        EXTI_PRIVCFGR2_PRIV41_Msk                 /*!< Privilege enable on line 41 */
+#define EXTI_PRIVCFGR2_PRIV42_Pos    (10U)
+#define EXTI_PRIVCFGR2_PRIV42_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV42_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR2_PRIV42        EXTI_PRIVCFGR2_PRIV42_Msk                 /*!< Privilege enable on line 42 */
+#define EXTI_PRIVCFGR2_PRIV43_Pos    (11U)
+#define EXTI_PRIVCFGR2_PRIV43_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV43_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR2_PRIV43        EXTI_PRIVCFGR2_PRIV43_Msk                 /*!< Privilege enable on line 43 */
+#define EXTI_PRIVCFGR2_PRIV44_Pos    (12U)
+#define EXTI_PRIVCFGR2_PRIV44_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV44_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR2_PRIV44        EXTI_PRIVCFGR2_PRIV44_Msk                 /*!< Privilege enable on line 44 */
+#define EXTI_PRIVCFGR2_PRIV45_Pos    (13U)
+#define EXTI_PRIVCFGR2_PRIV45_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV45_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR2_PRIV45        EXTI_PRIVCFGR2_PRIV45                     /*!< Privilege enable on line 45 */
+#define EXTI_PRIVCFGR2_PRIV46_Pos    (14U)
+#define EXTI_PRIVCFGR2_PRIV46_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV46_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR2_PRIV46        EXTI_PRIVCFGR2_PRIV46_Msk                 /*!< Privilege enable on line 46 */
+#define EXTI_PRIVCFGR2_PRIV47_Pos    (15U)
+#define EXTI_PRIVCFGR2_PRIV47_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV47_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR2_PRIV47        EXTI_PRIVCFGR2_PRIV47_Msk                 /*!< Privilege enable on line 47 */
+#define EXTI_PRIVCFGR2_PRIV48_Pos    (16U)
+#define EXTI_PRIVCFGR2_PRIV48_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV48_Pos)      /*!< 0x00010000 */
+#define EXTI_PRIVCFGR2_PRIV48        EXTI_PRIVCFGR2_PRIV48_Msk                 /*!< Privilege enable on line 48 */
+#define EXTI_PRIVCFGR2_PRIV49_Pos    (17U)
+#define EXTI_PRIVCFGR2_PRIV49_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV49_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR2_PRIV49        EXTI_PRIVCFGR2_PRIV49_Msk                 /*!< Privilege enable on line 49 */
+#define EXTI_PRIVCFGR2_PRIV50_Pos    (18U)
+#define EXTI_PRIVCFGR2_PRIV50_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV50_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR2_PRIV50        EXTI_PRIVCFGR2_PRIV50_Msk                 /*!< Privilege enable on line 50 */
+#define EXTI_PRIVCFGR2_PRIV51_Pos    (19U)
+#define EXTI_PRIVCFGR2_PRIV51_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV51_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR2_PRIV51        EXTI_PRIVCFGR2_PRIV51_Msk                 /*!< Privilege enable on line 51 */
+#define EXTI_PRIVCFGR2_PRIV52_Pos    (20U)
+#define EXTI_PRIVCFGR2_PRIV52_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV52_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR2_PRIV52        EXTI_PRIVCFGR2_PRIV52_Msk                 /*!< Privilege enable on line 52 */
+#define EXTI_PRIVCFGR2_PRIV53_Pos    (21U)
+#define EXTI_PRIVCFGR2_PRIV53_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV53_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR2_PRIV53        EXTI_PRIVCFGR2_PRIV53_Msk                 /*!< Privilege enable on line 53 */
+#define EXTI_PRIVCFGR2_PRIV54_Pos    (22U)
+#define EXTI_PRIVCFGR2_PRIV54_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV54_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR2_PRIV54        EXTI_PRIVCFGR2_PRIV54_Msk                 /*!< Privilege enable on line 54 */
+#define EXTI_PRIVCFGR2_PRIV55_Pos    (23U)
+#define EXTI_PRIVCFGR2_PRIV55_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV55_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR2_PRIV55        EXTI_PRIVCFGR2_PRIV55_Msk                 /*!< Privilege enable on line 55 */
+#define EXTI_PRIVCFGR2_PRIV56_Pos    (24U)
+#define EXTI_PRIVCFGR2_PRIV56_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV56_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR2_PRIV56        EXTI_PRIVCFGR2_PRIV56_Msk                 /*!< Privilege enable on line 56 */
+#define EXTI_PRIVCFGR2_PRIV57_Pos    (25U)
+#define EXTI_PRIVCFGR2_PRIV57_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV57_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR2_PRIV57        EXTI_PRIVCFGR2_PRIV57_Msk                 /*!< Privilege enable on line 57 */
+#define EXTI_PRIVCFGR2_PRIV58_Pos    (26U)
+#define EXTI_PRIVCFGR2_PRIV58_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV58_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR2_PRIV58        EXTI_PRIVCFGR2_PRIV58_Msk                 /*!< Privilege enable on line 58 */
+#define EXTI_PRIVCFGR2_PRIV60_Pos    (28U)
+#define EXTI_PRIVCFGR2_PRIV60_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV60_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR2_PRIV60        EXTI_PRIVCFGR2_PRIV60_Msk                 /*!< Privilege enable on line 60 */
+#define EXTI_PRIVCFGR2_PRIV61_Pos    (29U)
+#define EXTI_PRIVCFGR2_PRIV61_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV61_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR2_PRIV61        EXTI_PRIVCFGR2_PRIV61_Msk                 /*!< Privilege enable on line 61 */
+#define EXTI_PRIVCFGR2_PRIV62_Pos    (30U)
+#define EXTI_PRIVCFGR2_PRIV62_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV62_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR2_PRIV62        EXTI_PRIVCFGR2_PRIV62_Msk                 /*!< Privilege enable on line 62 */
+#define EXTI_PRIVCFGR2_PRIV63_Pos    (31U)
+#define EXTI_PRIVCFGR2_PRIV63_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV63_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR2_PRIV63        EXTI_PRIVCFGR2_PRIV63_Msk                 /*!< Privilege enable on line 63 */
+
+/*******************  Bit definition for EXTI_RTSR3 register  *****************/
+#define EXTI_RTSR3_RT66_Pos          (2U)
+#define EXTI_RTSR3_RT66_Msk          (0x1UL << EXTI_RTSR3_RT66_Pos)            /*!< 0x00000004 */
+#define EXTI_RTSR3_RT66              EXTI_RTSR3_RT66_Msk                       /*!< Rising trigger configuration for input line 66 */
+#define EXTI_RTSR3_RT68_Pos          (4U)
+#define EXTI_RTSR3_RT68_Msk          (0x1UL << EXTI_RTSR3_RT68_Pos)            /*!< 0x00000010 */
+#define EXTI_RTSR3_RT68              EXTI_RTSR3_RT68_Msk                       /*!< Rising trigger configuration for input line 68 */
+#define EXTI_RTSR3_RT69_Pos          (5U)
+#define EXTI_RTSR3_RT69_Msk          (0x1UL << EXTI_RTSR3_RT69_Pos)            /*!< 0x00000020 */
+#define EXTI_RTSR3_RT69              EXTI_RTSR3_RT69_Msk                       /*!< Rising trigger configuration for input line 69 */
+#define EXTI_RTSR3_RT70_Pos          (6U)
+#define EXTI_RTSR3_RT70_Msk          (0x1UL << EXTI_RTSR3_RT70_Pos)            /*!< 0x00000040 */
+#define EXTI_RTSR3_RT70              EXTI_RTSR3_RT70_Msk                       /*!< Rising trigger configuration for input line 70 */
+#define EXTI_RTSR3_RT71_Pos          (7U)
+#define EXTI_RTSR3_RT71_Msk          (0x1UL << EXTI_RTSR3_RT71_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR3_RT71              EXTI_RTSR3_RT71_Msk                       /*!< Rising trigger configuration for input line 71 */
+#define EXTI_RTSR3_RT72_Pos          (8U)
+#define EXTI_RTSR3_RT72_Msk          (0x1UL << EXTI_RTSR3_RT72_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR3_RT72              EXTI_RTSR3_RT72_Msk                       /*!< Rising trigger configuration for input line 72 */
+#define EXTI_RTSR3_RT73_Pos          (9U)
+#define EXTI_RTSR3_RT73_Msk          (0x1UL << EXTI_RTSR3_RT73_Pos)            /*!< 0x00000200 */
+#define EXTI_RTSR3_RT73              EXTI_RTSR3_RT73_Msk                       /*!< Rising trigger configuration for input line 73 */
+#define EXTI_RTSR3_RT74_Pos          (10U)
+#define EXTI_RTSR3_RT74_Msk          (0x1UL << EXTI_RTSR3_RT74_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR3_RT74              EXTI_RTSR3_RT74_Msk                       /*!< Rising trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_FTSR3 register  *****************/
+#define EXTI_FTSR3_FT66_Pos          (2U)
+#define EXTI_FTSR3_FT66_Msk          (0x1UL << EXTI_FTSR3_FT66_Pos)            /*!< 0x00000004 */
+#define EXTI_FTSR3_FT66              EXTI_FTSR3_FT66_Msk                       /*!< Falling trigger configuration for input line 66 */
+#define EXTI_FTSR3_FT68_Pos          (4U)
+#define EXTI_FTSR3_FT68_Msk          (0x1UL << EXTI_FTSR3_FT68_Pos)            /*!< 0x00000010 */
+#define EXTI_FTSR3_FT68              EXTI_FTSR3_FT68_Msk                       /*!< Falling trigger configuration for input line 68 */
+#define EXTI_FTSR3_FT69_Pos          (5U)
+#define EXTI_FTSR3_FT69_Msk          (0x1UL << EXTI_FTSR3_FT69_Pos)            /*!< 0x00000020 */
+#define EXTI_FTSR3_FT69              EXTI_FTSR3_FT69_Msk                       /*!< Falling trigger configuration for input line 69 */
+#define EXTI_FTSR3_FT70_Pos          (6U)
+#define EXTI_FTSR3_FT70_Msk          (0x1UL << EXTI_FTSR3_FT70_Pos)            /*!< 0x00000040 */
+#define EXTI_FTSR3_FT70              EXTI_FTSR3_FT70_Msk                       /*!< Falling trigger configuration for input line 70 */
+#define EXTI_FTSR3_FT71_Pos          (7U)
+#define EXTI_FTSR3_FT71_Msk          (0x1UL << EXTI_FTSR3_FT71_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR3_FT71              EXTI_FTSR3_FT71_Msk                       /*!< Falling trigger configuration for input line 71 */
+#define EXTI_FTSR3_FT72_Pos          (8U)
+#define EXTI_FTSR3_FT72_Msk          (0x1UL << EXTI_FTSR3_FT72_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR3_FT72              EXTI_FTSR3_FT72_Msk                       /*!< Falling trigger configuration for input line 72 */
+#define EXTI_FTSR3_FT73_Pos          (9U)
+#define EXTI_FTSR3_FT73_Msk          (0x1UL << EXTI_FTSR3_FT73_Pos)            /*!< 0x00000200 */
+#define EXTI_FTSR3_FT73              EXTI_FTSR3_FT73_Msk                       /*!< Falling trigger configuration for input line 73 */
+#define EXTI_FTSR3_FT74_Pos          (10U)
+#define EXTI_FTSR3_FT74_Msk          (0x1UL << EXTI_FTSR3_FT74_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR3_FT74              EXTI_FTSR3_FT74_Msk                       /*!< Falling trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_SWIER3 register  ****************/
+#define EXTI_SWIER3_SWI66_Pos        (2U)
+#define EXTI_SWIER3_SWI66_Msk        (0x1UL << EXTI_SWIER3_SWI66_Pos)          /*!< 0x00000004 */
+#define EXTI_SWIER3_SWI66            EXTI_SWIER3_SWI66_Msk                     /*!< Software Interrupt on line 66 */
+#define EXTI_SWIER3_SWI68_Pos        (4U)
+#define EXTI_SWIER3_SWI68_Msk        (0x1UL << EXTI_SWIER3_SWI68_Pos)          /*!< 0x00000010 */
+#define EXTI_SWIER3_SWI68            EXTI_SWIER3_SWI68_Msk                     /*!< Software Interrupt on line 68 */
+#define EXTI_SWIER3_SWI69_Pos        (5U)
+#define EXTI_SWIER3_SWI69_Msk        (0x1UL << EXTI_SWIER3_SWI69_Pos)          /*!< 0x00000020 */
+#define EXTI_SWIER3_SWI69            EXTI_SWIER3_SWI69_Msk                     /*!< Software Interrupt on line 69 */
+#define EXTI_SWIER3_SWI70_Pos        (6U)
+#define EXTI_SWIER3_SWI70_Msk        (0x1UL << EXTI_SWIER3_SWI70_Pos)          /*!< 0x00000040 */
+#define EXTI_SWIER3_SWI70            EXTI_SWIER3_SWI70_Msk                     /*!< Software Interrupt on line 70 */
+#define EXTI_SWIER3_SWI71_Pos        (7U)
+#define EXTI_SWIER3_SWI71_Msk        (0x1UL << EXTI_SWIER3_SWI71_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER3_SWI71            EXTI_SWIER3_SWI71_Msk                     /*!< Software Interrupt on line 71 */
+#define EXTI_SWIER3_SWI72_Pos        (8U)
+#define EXTI_SWIER3_SWI72_Msk        (0x1UL << EXTI_SWIER3_SWI72_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER3_SWI72            EXTI_SWIER3_SWI72_Msk                     /*!< Software Interrupt on line 72 */
+#define EXTI_SWIER3_SWI73_Pos        (9U)
+#define EXTI_SWIER3_SWI73_Msk        (0x1UL << EXTI_SWIER3_SWI73_Pos)          /*!< 0x00000200 */
+#define EXTI_SWIER3_SWI73            EXTI_SWIER3_SWI73_Msk                     /*!< Software Interrupt on line 73 */
+#define EXTI_SWIER3_SWI74_Pos        (10U)
+#define EXTI_SWIER3_SWI74_Msk        (0x1UL << EXTI_SWIER3_SWI74_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER3_SWI74            EXTI_SWIER3_SWI74_Msk                     /*!< Software Interrupt on line 74 */
+
+/*******************  Bit definition for EXTI_RPR3 register  ******************/
+#define EXTI_RPR3_RPIF66_Pos         (2U)
+#define EXTI_RPR3_RPIF66_Msk         (0x1UL << EXTI_RPR3_RPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_RPR3_RPIF66             EXTI_RPR3_RPIF66_Msk                      /*!< Rising Pending Interrupt Flag on line 66 */
+#define EXTI_RPR3_RPIF68_Pos         (4U)
+#define EXTI_RPR3_RPIF68_Msk         (0x1UL << EXTI_RPR3_RPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_RPR3_RPIF68             EXTI_RPR3_RPIF68_Msk                      /*!< Rising Pending Interrupt Flag on line 68 */
+#define EXTI_RPR3_RPIF69_Pos         (5U)
+#define EXTI_RPR3_RPIF69_Msk         (0x1UL << EXTI_RPR3_RPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_RPR3_RPIF69             EXTI_RPR3_RPIF69_Msk                      /*!< Rising Pending Interrupt Flag on line 69 */
+#define EXTI_RPR3_RPIF70_Pos         (6U)
+#define EXTI_RPR3_RPIF70_Msk         (0x1UL << EXTI_RPR3_RPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_RPR3_RPIF70             EXTI_RPR3_RPIF70_Msk                      /*!< Rising Pending Interrupt Flag on line 70 */
+#define EXTI_RPR3_RPIF71_Pos         (7U)
+#define EXTI_RPR3_RPIF71_Msk         (0x1UL << EXTI_RPR3_RPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR3_RPIF71             EXTI_RPR3_RPIF71_Msk                      /*!< Rising Pending Interrupt Flag on line 71 */
+#define EXTI_RPR3_RPIF72_Pos         (8U)
+#define EXTI_RPR3_RPIF72_Msk         (0x1UL << EXTI_RPR3_RPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR3_RPIF72             EXTI_RPR3_RPIF72_Msk                      /*!< Rising Pending Interrupt Flag on line 72 */
+#define EXTI_RPR3_RPIF73_Pos         (9U)
+#define EXTI_RPR3_RPIF73_Msk         (0x1UL << EXTI_RPR3_RPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_RPR3_RPIF73             EXTI_RPR3_RPIF73_Msk                      /*!< Rising Pending Interrupt Flag on line 73 */
+#define EXTI_RPR3_RPIF74_Pos         (10U)
+#define EXTI_RPR3_RPIF74_Msk         (0x1UL << EXTI_RPR3_RPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR3_RPIF74             EXTI_RPR3_RPIF74_Msk                      /*!< Rising Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_FPR3 register  ******************/
+#define EXTI_FPR3_FPIF66_Pos         (2U)
+#define EXTI_FPR3_FPIF66_Msk         (0x1UL << EXTI_FPR3_FPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_FPR3_FPIF66             EXTI_FPR3_FPIF66_Msk                      /*!< Falling Pending Interrupt Flag on line 66 */
+#define EXTI_FPR3_FPIF68_Pos         (4U)
+#define EXTI_FPR3_FPIF68_Msk         (0x1UL << EXTI_FPR3_FPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_FPR3_FPIF68             EXTI_FPR3_FPIF68_Msk                      /*!< Falling Pending Interrupt Flag on line 68 */
+#define EXTI_FPR3_FPIF69_Pos         (5U)
+#define EXTI_FPR3_FPIF69_Msk         (0x1UL << EXTI_FPR3_FPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_FPR3_FPIF69             EXTI_FPR3_FPIF69_Msk                      /*!< Falling Pending Interrupt Flag online  69 */
+#define EXTI_FPR3_FPIF70_Pos         (6U)
+#define EXTI_FPR3_FPIF70_Msk         (0x1UL << EXTI_FPR3_FPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_FPR3_FPIF70             EXTI_FPR3_FPIF70_Msk                      /*!< Falling Pending Interrupt Flag on line 70 */
+#define EXTI_FPR3_FPIF71_Pos         (7U)
+#define EXTI_FPR3_FPIF71_Msk         (0x1UL << EXTI_FPR3_FPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR3_FPIF71             EXTI_FPR3_FPIF71_Msk                      /*!< Falling Pending Interrupt Flag on line 71 */
+#define EXTI_FPR3_FPIF72_Pos         (8U)
+#define EXTI_FPR3_FPIF72_Msk         (0x1UL << EXTI_FPR3_FPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR3_FPIF72             EXTI_FPR3_FPIF72_Msk                      /*!< Falling Pending Interrupt Flag on line 72 */
+#define EXTI_FPR3_FPIF73_Pos         (9U)
+#define EXTI_FPR3_FPIF73_Msk         (0x1UL << EXTI_FPR3_FPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_FPR3_FPIF73             EXTI_FPR3_FPIF73_Msk                      /*!< Falling Pending Interrupt Flag on line 73 */
+#define EXTI_FPR3_FPIF74_Pos         (10U)
+#define EXTI_FPR3_FPIF74_Msk         (0x1UL << EXTI_FPR3_FPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR3_FPIF74             EXTI_FPR3_FPIF74_Msk                      /*!< Falling Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_SECCFGR3 register  ******************/
+#define EXTI_SECCFGR3_SEC64_Pos      (0U)
+#define EXTI_SECCFGR3_SEC64_Msk      (0x1UL << EXTI_SECCFGR3_SEC64_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR3_SEC64          EXTI_SECCFGR3_SEC64_Msk                   /*!< Security enable on line 64 */
+#define EXTI_SECCFGR3_SEC65_Pos      (1U)
+#define EXTI_SECCFGR3_SEC65_Msk      (0x1UL << EXTI_SECCFGR3_SEC65_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR3_SEC65          EXTI_SECCFGR3_SEC65_Msk                   /*!< Security enable on line 65 */
+#define EXTI_SECCFGR3_SEC66_Pos      (2U)
+#define EXTI_SECCFGR3_SEC66_Msk      (0x1UL << EXTI_SECCFGR3_SEC66_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR3_SEC66          EXTI_SECCFGR3_SEC66_Msk                   /*!< Security enable on line 66  */
+#define EXTI_SECCFGR3_SEC68_Pos      (4U)
+#define EXTI_SECCFGR3_SEC68_Msk      (0x1UL << EXTI_SECCFGR3_SEC68_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR3_SEC68          EXTI_SECCFGR3_SEC68_Msk                   /*!< Security enable on line 68 */
+#define EXTI_SECCFGR3_SEC69_Pos      (5U)
+#define EXTI_SECCFGR3_SEC69_Msk      (0x1UL << EXTI_SECCFGR3_SEC69_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR3_SEC69          EXTI_SECCFGR3_SEC69_Msk                   /*!< Security enable on line 69 */
+#define EXTI_SECCFGR3_SEC70_Pos      (6U)
+#define EXTI_SECCFGR3_SEC70_Msk      (0x1UL << EXTI_SECCFGR3_SEC70_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR3_SEC70          EXTI_SECCFGR3_SEC70_Msk                   /*!< Security enable on line 70 */
+#define EXTI_SECCFGR3_SEC71_Pos      (7U)
+#define EXTI_SECCFGR3_SEC71_Msk      (0x1UL << EXTI_SECCFGR3_SEC71_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR3_SEC71          EXTI_SECCFGR3_SEC71_Msk                   /*!< Security enable on line 71 */
+#define EXTI_SECCFGR3_SEC72_Pos      (8U)
+#define EXTI_SECCFGR3_SEC72_Msk      (0x1UL << EXTI_SECCFGR3_SEC72_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR3_SEC72          EXTI_SECCFGR3_SEC72_Msk                   /*!< Security enable on line 72 */
+#define EXTI_SECCFGR3_SEC73_Pos      (9U)
+#define EXTI_SECCFGR3_SEC73_Msk      (0x1UL << EXTI_SECCFGR3_SEC73_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR3_SEC73          EXTI_SECCFGR3_SEC73_Msk                   /*!< Security enable on line 73 */
+#define EXTI_SECCFGR3_SEC74_Pos      (10U)
+#define EXTI_SECCFGR3_SEC74_Msk      (0x1UL << EXTI_SECCFGR3_SEC74_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR3_SEC74          EXTI_SECCFGR3_SEC74_Msk                   /*!< Security enable on line 74 */
+#define EXTI_SECCFGR3_SEC77_Pos      (13U)
+#define EXTI_SECCFGR3_SEC77_Msk      (0x1UL << EXTI_SECCFGR3_SEC77_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR3_SEC77          EXTI_SECCFGR3_SEC77_Msk                   /*!< Security enable on line 77 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR3 register  ******************/
+#define EXTI_PRIVCFGR3_PRIV64_Pos    (0U)
+#define EXTI_PRIVCFGR3_PRIV64_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV64_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR3_PRIV64        EXTI_PRIVCFGR3_PRIV64_Msk                 /*!< Privilege enable on line 64 */
+#define EXTI_PRIVCFGR3_PRIV65_Pos    (1U)
+#define EXTI_PRIVCFGR3_PRIV65_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV65_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR3_PRIV65        EXTI_PRIVCFGR3_PRIV65_Msk                 /*!< Privilege enable on line 65 */
+#define EXTI_PRIVCFGR3_PRIV66_Pos    (2U)
+#define EXTI_PRIVCFGR3_PRIV66_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV66_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR3_PRIV66        EXTI_PRIVCFGR3_PRIV66_Msk                 /*!< Privilege enable on line 66  */
+#define EXTI_PRIVCFGR3_PRIV68_Pos    (4U)
+#define EXTI_PRIVCFGR3_PRIV68_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV68_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR3_PRIV68        EXTI_PRIVCFGR3_PRIV68_Msk                 /*!< Privilege enable on line 68 */
+#define EXTI_PRIVCFGR3_PRIV69_Pos    (5U)
+#define EXTI_PRIVCFGR3_PRIV69_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV69_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR3_PRIV69        EXTI_PRIVCFGR3_PRIV69_Msk                 /*!< Privilege enable on line 69 */
+#define EXTI_PRIVCFGR3_PRIV70_Pos    (6U)
+#define EXTI_PRIVCFGR3_PRIV70_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV70_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR3_PRIV70        EXTI_PRIVCFGR3_PRIV70_Msk                 /*!< Privilege enable on line 70 */
+#define EXTI_PRIVCFGR3_PRIV71_Pos    (7U)
+#define EXTI_PRIVCFGR3_PRIV71_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV71_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR3_PRIV71        EXTI_PRIVCFGR3_PRIV71_Msk                 /*!< Privilege enable on line 71 */
+#define EXTI_PRIVCFGR3_PRIV72_Pos    (8U)
+#define EXTI_PRIVCFGR3_PRIV72_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV72_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR3_PRIV72        EXTI_PRIVCFGR3_PRIV72_Msk                 /*!< Privilege enable on line 72 */
+#define EXTI_PRIVCFGR3_PRIV73_Pos    (9U)
+#define EXTI_PRIVCFGR3_PRIV73_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV73_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR3_PRIV73        EXTI_PRIVCFGR3_PRIV73_Msk                 /*!< Privilege enable on line 73 */
+#define EXTI_PRIVCFGR3_PRIV74_Pos    (10U)
+#define EXTI_PRIVCFGR3_PRIV74_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV74_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR3_PRIV74        EXTI_PRIVCFGR3_PRIV74_Msk                 /*!< Privilege enable on line 74 */
+#define EXTI_PRIVCFGR3_PRIV77_Pos    (13U)
+#define EXTI_PRIVCFGR3_PRIV77_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV77_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR3_PRIV77        EXTI_PRIVCFGR3_PRIV77_Msk                 /*!< Privilege enable on line 77 */
+
+/*****************  Bit definition for EXTI_EXTICR1 register  **************/
+#define EXTI_EXTICR1_EXTI0_Pos       (0U)
+#define EXTI_EXTICR1_EXTI0_Msk       (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
+#define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR1_EXTI0_3         (0x8UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR1_EXTI0_4         (0x10UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR1_EXTI0_5         (0x20UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR1_EXTI0_6         (0x40UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR1_EXTI0_7         (0x80UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR1_EXTI1_Pos       (8U)
+#define EXTI_EXTICR1_EXTI1_Msk       (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
+#define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR1_EXTI1_3         (0x8UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR1_EXTI1_4         (0x10UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR1_EXTI1_5         (0x20UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR1_EXTI1_6         (0x40UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR1_EXTI1_7         (0x80UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR1_EXTI2_Pos       (16U)
+#define EXTI_EXTICR1_EXTI2_Msk       (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
+#define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR1_EXTI2_3         (0x8UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR1_EXTI2_4         (0x10UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR1_EXTI2_5         (0x20UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR1_EXTI2_6         (0x40UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR1_EXTI2_7         (0x80UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR1_EXTI3_Pos       (24U)
+#define EXTI_EXTICR1_EXTI3_Msk       (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
+#define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR1_EXTI3_3         (0x8UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR1_EXTI3_4         (0x10UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR1_EXTI3_5         (0x20UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR1_EXTI3_6         (0x40UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR1_EXTI3_7         (0x80UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR2 register  **************/
+#define EXTI_EXTICR2_EXTI4_Pos       (0U)
+#define EXTI_EXTICR2_EXTI4_Msk       (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
+#define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR2_EXTI4_3         (0x8UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR2_EXTI4_4         (0x10UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR2_EXTI4_5         (0x20UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR2_EXTI4_6         (0x40UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR2_EXTI4_7         (0x80UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR2_EXTI5_Pos       (8U)
+#define EXTI_EXTICR2_EXTI5_Msk       (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
+#define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR2_EXTI5_3         (0x8UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR2_EXTI5_4         (0x10UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR2_EXTI5_5         (0x20UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR2_EXTI5_6         (0x40UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR2_EXTI5_7         (0x80UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR2_EXTI6_Pos       (16U)
+#define EXTI_EXTICR2_EXTI6_Msk       (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
+#define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR2_EXTI6_3         (0x8UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR2_EXTI6_4         (0x10UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR2_EXTI6_5         (0x20UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR2_EXTI6_6         (0x40UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR2_EXTI6_7         (0x80UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR2_EXTI7_Pos       (24U)
+#define EXTI_EXTICR2_EXTI7_Msk       (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
+#define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR2_EXTI7_3         (0x8UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR2_EXTI7_4         (0x10UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR2_EXTI7_5         (0x20UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR2_EXTI7_6         (0x40UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR2_EXTI7_7         (0x80UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR3 register  **************/
+#define EXTI_EXTICR3_EXTI8_Pos       (0U)
+#define EXTI_EXTICR3_EXTI8_Msk       (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
+#define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR3_EXTI8_3         (0x8UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR3_EXTI8_4         (0x10UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR3_EXTI8_5         (0x20UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR3_EXTI8_6         (0x40UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR3_EXTI8_7         (0x80UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR3_EXTI9_Pos       (8U)
+#define EXTI_EXTICR3_EXTI9_Msk       (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
+#define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR3_EXTI9_3         (0x8UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR3_EXTI9_4         (0x10UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR3_EXTI9_5         (0x20UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR3_EXTI9_6         (0x40UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR3_EXTI9_7         (0x80UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR3_EXTI10_Pos      (16U)
+#define EXTI_EXTICR3_EXTI10_Msk      (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
+#define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR3_EXTI10_3        (0x8UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR3_EXTI10_4        (0x10UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR3_EXTI10_5        (0x20UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR3_EXTI10_6        (0x40UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR3_EXTI10_7        (0x80UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR3_EXTI11_Pos      (24U)
+#define EXTI_EXTICR3_EXTI11_Msk      (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
+#define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR3_EXTI11_3        (0x8UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR3_EXTI11_4        (0x10UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR3_EXTI11_5        (0x20UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR3_EXTI11_6        (0x40UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR3_EXTI11_7        (0x80UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR4 register  **************/
+#define EXTI_EXTICR4_EXTI12_Pos      (0U)
+#define EXTI_EXTICR4_EXTI12_Msk      (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x000000FF */
+#define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
+#define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
+#define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
+#define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
+#define EXTI_EXTICR4_EXTI12_3        (0x8UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000008 */
+#define EXTI_EXTICR4_EXTI12_4        (0x10UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000010 */
+#define EXTI_EXTICR4_EXTI12_5        (0x20UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000020 */
+#define EXTI_EXTICR4_EXTI12_6        (0x40UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000040 */
+#define EXTI_EXTICR4_EXTI12_7        (0x80UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000080 */
+#define EXTI_EXTICR4_EXTI13_Pos      (8U)
+#define EXTI_EXTICR4_EXTI13_Msk      (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x0000FF00 */
+#define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
+#define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
+#define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000200 */
+#define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000400 */
+#define EXTI_EXTICR4_EXTI13_3        (0x8UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000800 */
+#define EXTI_EXTICR4_EXTI13_4        (0x10UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00001000 */
+#define EXTI_EXTICR4_EXTI13_5        (0x20UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00002000 */
+#define EXTI_EXTICR4_EXTI13_6        (0x40UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00004000 */
+#define EXTI_EXTICR4_EXTI13_7        (0x80UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00008000 */
+#define EXTI_EXTICR4_EXTI14_Pos      (16U)
+#define EXTI_EXTICR4_EXTI14_Msk      (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
+#define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR4_EXTI14_3        (0x8UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR4_EXTI14_4        (0x10UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR4_EXTI14_5        (0x20UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR4_EXTI14_6        (0x40UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR4_EXTI14_7        (0x80UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR4_EXTI15_Pos      (24U)
+#define EXTI_EXTICR4_EXTI15_Msk      (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
+#define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR4_EXTI15_3        (0x8UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR4_EXTI15_4        (0x10UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR4_EXTI15_5        (0x20UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR4_EXTI15_6        (0x40UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR4_EXTI15_7        (0x80UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x80000000 */
+
+/*******************  Bit definition I_LOCKR register  ******************/
+#define EXTI_LOCKR_LOCK_Pos          (0U)
+#define EXTI_LOCKR_LOCK_Msk          (0x1UL << EXTI_LOCKR_LOCK_Pos)            /*!< 0x00000001 */
+#define EXTI_LOCKR_LOCK              EXTI_LOCKR_LOCK_Msk                       /*!< Security and privilege configuration lock */
+
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos            (0U)
+#define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
+#define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos            (1U)
+#define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
+#define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos            (2U)
+#define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
+#define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos            (3U)
+#define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
+#define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos            (4U)
+#define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
+#define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos            (5U)
+#define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
+#define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos            (6U)
+#define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
+#define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos            (7U)
+#define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
+#define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos            (8U)
+#define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
+#define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos            (9U)
+#define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
+#define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos           (10U)
+#define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos           (11U)
+#define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos           (12U)
+#define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos           (13U)
+#define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos           (14U)
+#define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos           (15U)
+#define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM17_Pos           (17U)
+#define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos           (18U)
+#define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos           (19U)
+#define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos           (20U)
+#define EXTI_IMR1_IM20_Msk           (0x1UL << EXTI_IMR1_IM20_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR1_IM20               EXTI_IMR1_IM20_Msk                        /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos           (21U)
+#define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos           (22U)
+#define EXTI_IMR1_IM22_Msk           (0x1UL << EXTI_IMR1_IM22_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR1_IM22               EXTI_IMR1_IM22_Msk                        /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos           (23U)
+#define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos           (24U)
+#define EXTI_IMR1_IM24_Msk           (0x1UL << EXTI_IMR1_IM24_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR1_IM24               EXTI_IMR1_IM24_Msk                        /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos           (25U)
+#define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos           (26U)
+#define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos           (27U)
+#define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */
+#define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos           (28U)
+#define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos           (29U)
+#define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos           (30U)
+#define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos           (31U)
+#define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos             (0U)
+#define EXTI_IMR1_IM_Msk             (0xFFFEFFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos            (0U)
+#define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
+#define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos            (1U)
+#define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
+#define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos            (2U)
+#define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
+#define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos            (3U)
+#define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
+#define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos            (4U)
+#define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
+#define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos            (5U)
+#define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
+#define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos            (6U)
+#define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
+#define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos            (7U)
+#define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
+#define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos            (8U)
+#define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
+#define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos            (9U)
+#define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
+#define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos           (10U)
+#define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos           (11U)
+#define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos           (12U)
+#define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos           (13U)
+#define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos           (14U)
+#define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos           (15U)
+#define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM17_Pos           (17U)
+#define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos           (18U)
+#define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos           (19U)
+#define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos           (20U)
+#define EXTI_EMR1_EM20_Msk           (0x1UL << EXTI_EMR1_EM20_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR1_EM20               EXTI_EMR1_EM20_Msk                        /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos           (21U)
+#define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos           (22U)
+#define EXTI_EMR1_EM22_Msk           (0x1UL << EXTI_EMR1_EM22_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR1_EM22               EXTI_EMR1_EM22_Msk                        /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos           (23U)
+#define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos           (24U)
+#define EXTI_EMR1_EM24_Msk           (0x1UL << EXTI_EMR1_EM24_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR1_EM24               EXTI_EMR1_EM24_Msk                        /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos           (25U)
+#define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos           (26U)
+#define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos           (27U)
+#define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */
+#define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos           (28U)
+#define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos           (29U)
+#define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos           (30U)
+#define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos           (31U)
+#define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */
+#define EXTI_EMR1_EM_Pos             (0U)
+#define EXTI_EMR1_EM_Msk             (0xFFFEFFFFUL << EXTI_EMR1_EM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_EMR1_EM                 EXTI_EMR1_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos           (0U)
+#define EXTI_IMR2_IM32_Msk           (0x1UL << EXTI_IMR2_IM32_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR2_IM32               EXTI_IMR2_IM32_Msk                        /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos           (1U)
+#define EXTI_IMR2_IM33_Msk           (0x1UL << EXTI_IMR2_IM33_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR2_IM33               EXTI_IMR2_IM33_Msk                        /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos           (2U)
+#define EXTI_IMR2_IM34_Msk           (0x1UL << EXTI_IMR2_IM34_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR2_IM34               EXTI_IMR2_IM34_Msk                        /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos           (3U)
+#define EXTI_IMR2_IM35_Msk           (0x1UL << EXTI_IMR2_IM35_Pos)             /*!< 0x00000008 */
+#define EXTI_IMR2_IM35               EXTI_IMR2_IM35_Msk                        /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos           (4U)
+#define EXTI_IMR2_IM36_Msk           (0x1UL << EXTI_IMR2_IM36_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR2_IM36               EXTI_IMR2_IM36_Msk                        /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos           (5U)
+#define EXTI_IMR2_IM37_Msk           (0x1UL << EXTI_IMR2_IM37_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR2_IM37               EXTI_IMR2_IM37_Msk                        /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos           (6U)
+#define EXTI_IMR2_IM38_Msk           (0x1UL << EXTI_IMR2_IM38_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR2_IM38               EXTI_IMR2_IM38_Msk                        /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos           (7U)
+#define EXTI_IMR2_IM39_Msk           (0x1UL << EXTI_IMR2_IM39_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR2_IM39               EXTI_IMR2_IM39_Msk                        /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos           (8U)
+#define EXTI_IMR2_IM40_Msk           (0x1UL << EXTI_IMR2_IM40_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR2_IM40               EXTI_IMR2_IM40_Msk                        /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos           (9U)
+#define EXTI_IMR2_IM41_Msk           (0x1UL << EXTI_IMR2_IM41_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR2_IM41               EXTI_IMR2_IM41_Msk                        /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos           (10U)
+#define EXTI_IMR2_IM42_Msk           (0x1UL << EXTI_IMR2_IM42_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR2_IM42               EXTI_IMR2_IM42_Msk                        /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos           (11U)
+#define EXTI_IMR2_IM43_Msk           (0x1UL << EXTI_IMR2_IM43_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR2_IM43               EXTI_IMR2_IM43_Msk                        /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos           (12U)
+#define EXTI_IMR2_IM44_Msk           (0x1UL << EXTI_IMR2_IM44_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR2_IM44               EXTI_IMR2_IM44_Msk                        /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM45_Pos           (13U)
+#define EXTI_IMR2_IM45_Msk           (0x1UL << EXTI_IMR2_IM45_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR2_IM45               EXTI_IMR2_IM45_Msk                        /*!< Interrupt Mask on line 45 */
+#define EXTI_IMR2_IM46_Pos           (14U)
+#define EXTI_IMR2_IM46_Msk           (0x1UL << EXTI_IMR2_IM46_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR2_IM46               EXTI_IMR2_IM46_Msk                        /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos           (15U)
+#define EXTI_IMR2_IM47_Msk           (0x1UL << EXTI_IMR2_IM47_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR2_IM47               EXTI_IMR2_IM47_Msk                        /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos           (16U)
+#define EXTI_IMR2_IM48_Msk           (0x1UL << EXTI_IMR2_IM48_Pos)             /*!< 0x00010000 */
+#define EXTI_IMR2_IM48               EXTI_IMR2_IM48_Msk                        /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos           (17U)
+#define EXTI_IMR2_IM49_Msk           (0x1UL << EXTI_IMR2_IM49_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR2_IM49               EXTI_IMR2_IM49_Msk                        /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos           (18U)
+#define EXTI_IMR2_IM50_Msk           (0x1UL << EXTI_IMR2_IM50_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR2_IM50               EXTI_IMR2_IM50_Msk                        /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos           (19U)
+#define EXTI_IMR2_IM51_Msk           (0x1UL << EXTI_IMR2_IM51_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR2_IM51               EXTI_IMR2_IM51_Msk                        /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos           (20U)
+#define EXTI_IMR2_IM52_Msk           (0x1UL << EXTI_IMR2_IM52_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR2_IM52               EXTI_IMR2_IM52_Msk                        /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos           (21U)
+#define EXTI_IMR2_IM53_Msk           (0x1UL << EXTI_IMR2_IM53_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR2_IM53               EXTI_IMR2_IM53_Msk                        /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos           (22U)
+#define EXTI_IMR2_IM54_Msk           (0x1UL << EXTI_IMR2_IM54_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR2_IM54               EXTI_IMR2_IM54_Msk                        /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos           (23U)
+#define EXTI_IMR2_IM55_Msk           (0x1UL << EXTI_IMR2_IM55_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR2_IM55               EXTI_IMR2_IM55_Msk                        /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos           (24U)
+#define EXTI_IMR2_IM56_Msk           (0x1UL << EXTI_IMR2_IM56_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR2_IM56               EXTI_IMR2_IM56_Msk                        /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos           (25U)
+#define EXTI_IMR2_IM57_Msk           (0x1UL << EXTI_IMR2_IM57_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR2_IM57               EXTI_IMR2_IM57_Msk                        /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos           (26U)
+#define EXTI_IMR2_IM58_Msk           (0x1UL << EXTI_IMR2_IM58_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR2_IM58               EXTI_IMR2_IM58_Msk                        /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM60_Pos           (28U)
+#define EXTI_IMR2_IM60_Msk           (0x1UL << EXTI_IMR2_IM60_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR2_IM60               EXTI_IMR2_IM60_Msk                        /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos           (29U)
+#define EXTI_IMR2_IM61_Msk           (0x1UL << EXTI_IMR2_IM61_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR2_IM61               EXTI_IMR2_IM61_Msk                        /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos           (30U)
+#define EXTI_IMR2_IM62_Msk           (0x1UL << EXTI_IMR2_IM62_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR2_IM62               EXTI_IMR2_IM62_Msk                        /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos           (31U)
+#define EXTI_IMR2_IM63_Msk           (0x1UL << EXTI_IMR2_IM63_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR2_IM63               EXTI_IMR2_IM63_Msk                        /*!< Interrupt Mask on line 63 */
+#define EXTI_IMR2_IM_Pos             (0U)
+#define EXTI_IMR2_IM_Msk             (0xF7FFFFFFUL << EXTI_IMR2_IM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_IMR2_IM                 EXTI_IMR2_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos           (0U)
+#define EXTI_EMR2_EM32_Msk           (0x1UL << EXTI_EMR2_EM32_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR2_EM32               EXTI_EMR2_EM32_Msk                        /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos           (1U)
+#define EXTI_EMR2_EM33_Msk           (0x1UL << EXTI_EMR2_EM33_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR2_EM33               EXTI_EMR2_EM33_Msk                        /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos           (2U)
+#define EXTI_EMR2_EM34_Msk           (0x1UL << EXTI_EMR2_EM34_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR2_EM34               EXTI_EMR2_EM34_Msk                        /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos           (3U)
+#define EXTI_EMR2_EM35_Msk           (0x1UL << EXTI_EMR2_EM35_Pos)             /*!< 0x00000008 */
+#define EXTI_EMR2_EM35               EXTI_EMR2_EM35_Msk                        /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos           (4U)
+#define EXTI_EMR2_EM36_Msk           (0x1UL << EXTI_EMR2_EM36_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR2_EM36               EXTI_EMR2_EM36_Msk                        /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos           (5U)
+#define EXTI_EMR2_EM37_Msk           (0x1UL << EXTI_EMR2_EM37_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR2_EM37               EXTI_EMR2_EM37_Msk                        /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos           (6U)
+#define EXTI_EMR2_EM38_Msk           (0x1UL << EXTI_EMR2_EM38_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR2_EM38               EXTI_EMR2_EM38_Msk                        /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos           (7U)
+#define EXTI_EMR2_EM39_Msk           (0x1UL << EXTI_EMR2_EM39_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR2_EM39               EXTI_EMR2_EM39_Msk                        /*!< Event Mask on line 39 */
+#define EXTI_EMR2_EM40_Pos           (8U)
+#define EXTI_EMR2_EM40_Msk           (0x1UL << EXTI_EMR2_EM40_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR2_EM40               EXTI_EMR2_EM40_Msk                        /*!< Event Mask on line 40 */
+#define EXTI_EMR2_EM41_Pos           (9U)
+#define EXTI_EMR2_EM41_Msk           (0x1UL << EXTI_EMR2_EM41_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR2_EM41               EXTI_EMR2_EM41_Msk                        /*!< Event Mask on line 41 */
+#define EXTI_EMR2_EM42_Pos           (10U)
+#define EXTI_EMR2_EM42_Msk           (0x1UL << EXTI_EMR2_EM42_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR2_EM42               EXTI_EMR2_EM42_Msk                        /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos           (11U)
+#define EXTI_EMR2_EM43_Msk           (0x1UL << EXTI_EMR2_EM43_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR2_EM43               EXTI_EMR2_EM43_Msk                        /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos           (12U)
+#define EXTI_EMR2_EM44_Msk           (0x1UL << EXTI_EMR2_EM44_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR2_EM44               EXTI_EMR2_EM44_Msk                        /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM45_Pos           (13U)
+#define EXTI_EMR2_EM45_Msk           (0x1UL << EXTI_EMR2_EM45_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR2_EM45               EXTI_EMR2_EM45_Msk                        /*!< Event Mask on line 45 */
+#define EXTI_EMR2_EM46_Pos           (14U)
+#define EXTI_EMR2_EM46_Msk           (0x1UL << EXTI_EMR2_EM46_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR2_EM46               EXTI_EMR2_EM46_Msk                        /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos           (15U)
+#define EXTI_EMR2_EM47_Msk           (0x1UL << EXTI_EMR2_EM47_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR2_EM47               EXTI_EMR2_EM47_Msk                        /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos           (16U)
+#define EXTI_EMR2_EM48_Msk           (0x1UL << EXTI_EMR2_EM48_Pos)             /*!< 0x00010000 */
+#define EXTI_EMR2_EM48               EXTI_EMR2_EM48_Msk                        /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos           (17U)
+#define EXTI_EMR2_EM49_Msk           (0x1UL << EXTI_EMR2_EM49_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR2_EM49               EXTI_EMR2_EM49_Msk                        /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos           (18U)
+#define EXTI_EMR2_EM50_Msk           (0x1UL << EXTI_EMR2_EM50_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR2_EM50               EXTI_EMR2_EM50_Msk                        /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos           (19U)
+#define EXTI_EMR2_EM51_Msk           (0x1UL << EXTI_EMR2_EM51_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR2_EM51               EXTI_EMR2_EM51_Msk                        /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos           (20U)
+#define EXTI_EMR2_EM52_Msk           (0x1UL << EXTI_EMR2_EM52_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR2_EM52               EXTI_EMR2_EM52_Msk                        /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos           (21U)
+#define EXTI_EMR2_EM53_Msk           (0x1UL << EXTI_EMR2_EM53_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR2_EM53               EXTI_EMR2_EM53_Msk                        /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos           (22U)
+#define EXTI_EMR2_EM54_Msk           (0x1UL << EXTI_EMR2_EM54_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR2_EM54               EXTI_EMR2_EM54_Msk                        /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos           (23U)
+#define EXTI_EMR2_EM55_Msk           (0x1UL << EXTI_EMR2_EM55_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR2_EM55               EXTI_EMR2_EM55_Msk                        /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos           (24U)
+#define EXTI_EMR2_EM56_Msk           (0x1UL << EXTI_EMR2_EM56_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR2_EM56               EXTI_EMR2_EM56_Msk                        /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos           (25U)
+#define EXTI_EMR2_EM57_Msk           (0x1UL << EXTI_EMR2_EM57_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR2_EM57               EXTI_EMR2_EM57_Msk                        /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos           (26U)
+#define EXTI_EMR2_EM58_Msk           (0x1UL << EXTI_EMR2_EM58_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR2_EM58               EXTI_EMR2_EM58_Msk                        /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM60_Pos           (28U)
+#define EXTI_EMR2_EM60_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR2_EM60               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos           (29U)
+#define EXTI_EMR2_EM61_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR2_EM61               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos           (30U)
+#define EXTI_EMR2_EM62_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR2_EM62               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos           (31U)
+#define EXTI_EMR2_EM63_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR2_EM63               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 63 */
+#define EXTI_EMR2_EM_Pos             (0U)
+#define EXTI_EMR2_EM_Msk             (0xF7FFFFFFUL << EXTI_EMR2_EM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_EMR2_EM                 EXTI_EMR2_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR3 register  ******************/
+#define EXTI_IMR3_IM64_Pos           (0U)
+#define EXTI_IMR3_IM64_Msk           (0x1UL << EXTI_IMR3_IM64_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR3_IM64               EXTI_IMR3_IM64_Msk                        /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos           (1U)
+#define EXTI_IMR3_IM65_Msk           (0x1UL << EXTI_IMR3_IM65_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR3_IM65               EXTI_IMR3_IM65_Msk                        /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos           (2U)
+#define EXTI_IMR3_IM66_Msk           (0x1UL << EXTI_IMR3_IM66_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR3_IM66               EXTI_IMR3_IM66_Msk                        /*!< Interrupt Mask on line 66  */
+#define EXTI_IMR3_IM68_Pos           (4U)
+#define EXTI_IMR3_IM68_Msk           (0x1UL << EXTI_IMR3_IM68_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR3_IM68               EXTI_IMR3_IM68_Msk                        /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos           (5U)
+#define EXTI_IMR3_IM69_Msk           (0x1UL << EXTI_IMR3_IM69_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR3_IM69               EXTI_IMR3_IM69_Msk                        /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos           (6U)
+#define EXTI_IMR3_IM70_Msk           (0x1UL << EXTI_IMR3_IM70_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR3_IM70               EXTI_IMR3_IM70_Msk                        /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos           (7U)
+#define EXTI_IMR3_IM71_Msk           (0x1UL << EXTI_IMR3_IM71_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR3_IM71               EXTI_IMR3_IM71_Msk                        /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos           (8U)
+#define EXTI_IMR3_IM72_Msk           (0x1UL << EXTI_IMR3_IM72_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR3_IM72               EXTI_IMR3_IM72_Msk                        /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos           (9U)
+#define EXTI_IMR3_IM73_Msk           (0x1UL << EXTI_IMR3_IM73_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR3_IM73               EXTI_IMR3_IM73_Msk                        /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos           (10U)
+#define EXTI_IMR3_IM74_Msk           (0x1UL << EXTI_IMR3_IM74_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR3_IM74               EXTI_IMR3_IM74_Msk                        /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM77_Pos           (13U)
+#define EXTI_IMR3_IM77_Msk           (0x1UL << EXTI_IMR3_IM77_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR3_IM77               EXTI_IMR3_IM77_Msk                        /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM_Pos             (0U)
+#define EXTI_IMR3_IM_Msk             (0x27F7UL << EXTI_IMR3_IM_Pos)             /*!< 0x000027F7 */
+#define EXTI_IMR3_IM                 EXTI_IMR3_IM_Msk                           /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR3 register  ******************/
+#define EXTI_EMR3_EM64_Pos           (0U)
+#define EXTI_EMR3_EM64_Msk           (0x1UL << EXTI_EMR3_EM64_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR3_EM64               EXTI_EMR3_EM64_Msk                        /*!< Event Mask on line 64 */
+#define EXTI_EMR3_EM65_Pos           (1U)
+#define EXTI_EMR3_EM65_Msk           (0x1UL << EXTI_EMR3_EM65_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR3_EM65               EXTI_EMR3_EM65_Msk                        /*!< Event Mask on line 65 */
+#define EXTI_EMR3_EM66_Pos           (2U)
+#define EXTI_EMR3_EM66_Msk           (0x1UL << EXTI_EMR3_EM66_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR3_EM66               EXTI_EMR3_EM66_Msk                        /*!< Event Mask on line 66  */
+#define EXTI_EMR3_EM68_Pos           (4U)
+#define EXTI_EMR3_EM68_Msk           (0x1UL << EXTI_EMR3_EM68_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR3_EM68               EXTI_EMR3_EM68_Msk                        /*!< Event Mask on line 68 */
+#define EXTI_EMR3_EM69_Pos           (5U)
+#define EXTI_EMR3_EM69_Msk           (0x1UL << EXTI_EMR3_EM69_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR3_EM69               EXTI_EMR3_EM69_Msk                        /*!< Event Mask on line 69 */
+#define EXTI_EMR3_EM70_Pos           (6U)
+#define EXTI_EMR3_EM70_Msk           (0x1UL << EXTI_EMR3_EM70_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR3_EM70               EXTI_EMR3_EM70_Msk                        /*!< Event Mask on line 70 */
+#define EXTI_EMR3_EM71_Pos           (7U)
+#define EXTI_EMR3_EM71_Msk           (0x1UL << EXTI_EMR3_EM71_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR3_EM71               EXTI_EMR3_EM71_Msk                        /*!< Event Mask on line 71 */
+#define EXTI_EMR3_EM72_Pos           (8U)
+#define EXTI_EMR3_EM72_Msk           (0x1UL << EXTI_EMR3_EM72_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR3_EM72               EXTI_EMR3_EM72_Msk                        /*!< Event Mask on line 72 */
+#define EXTI_EMR3_EM73_Pos           (9U)
+#define EXTI_EMR3_EM73_Msk           (0x1UL << EXTI_EMR3_EM73_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR3_EM73               EXTI_EMR3_EM73_Msk                        /*!< Event Mask on line 73 */
+#define EXTI_EMR3_EM74_Pos           (10U)
+#define EXTI_EMR3_EM74_Msk           (0x1UL << EXTI_EMR3_EM74_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR3_EM74               EXTI_EMR3_EM74_Msk                        /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM77_Pos           (13U)
+#define EXTI_EMR3_EM77_Msk           (0x1UL << EXTI_EMR3_EM77_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR3_EM77               EXTI_EMR3_EM77_Msk                        /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM_Pos             (0U)
+#define EXTI_EMR3_EM_Msk             (0x27F7UL << EXTI_EMR3_EM_Pos)             /*!< 0x000027F7 */
+#define EXTI_EMR3_EM                 EXTI_EMR3_EM_Msk                           /*!< Event Mask All */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos           (0U)
+#define FDCAN_CREL_DAY_Msk           (0xFFUL << FDCAN_CREL_DAY_Pos)            /*!< 0x000000FF */
+#define FDCAN_CREL_DAY               FDCAN_CREL_DAY_Msk                        /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos           (8U)
+#define FDCAN_CREL_MON_Msk           (0xFFUL << FDCAN_CREL_MON_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON               FDCAN_CREL_MON_Msk                        /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos          (16U)
+#define FDCAN_CREL_YEAR_Msk          (0xFUL << FDCAN_CREL_YEAR_Pos)            /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR              FDCAN_CREL_YEAR_Msk                       /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos       (20U)
+#define FDCAN_CREL_SUBSTEP_Msk       (0xFUL << FDCAN_CREL_SUBSTEP_Pos)         /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP           FDCAN_CREL_SUBSTEP_Msk                    /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos          (24U)
+#define FDCAN_CREL_STEP_Msk          (0xFUL << FDCAN_CREL_STEP_Pos)            /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP              FDCAN_CREL_STEP_Msk                       /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos           (28U)
+#define FDCAN_CREL_REL_Msk           (0xFUL << FDCAN_CREL_REL_Pos)             /*!< 0xF0000000 */
+#define FDCAN_CREL_REL               FDCAN_CREL_REL_Msk                        /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos           (0U)
+#define FDCAN_ENDN_ETV_Msk           (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV               FDCAN_ENDN_ETV_Msk                        /*!<Endianness Test Value                   */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos          (0U)
+#define FDCAN_DBTP_DSJW_Msk          (0xFUL << FDCAN_DBTP_DSJW_Pos)            /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW              FDCAN_DBTP_DSJW_Msk                       /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos        (4U)
+#define FDCAN_DBTP_DTSEG2_Msk        (0xFUL << FDCAN_DBTP_DTSEG2_Pos)          /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2            FDCAN_DBTP_DTSEG2_Msk                     /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos        (8U)
+#define FDCAN_DBTP_DTSEG1_Msk        (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)         /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1            FDCAN_DBTP_DTSEG1_Msk                     /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos          (16U)
+#define FDCAN_DBTP_DBRP_Msk          (0x1FUL << FDCAN_DBTP_DBRP_Pos)           /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP              FDCAN_DBTP_DBRP_Msk                       /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos           (23U)
+#define FDCAN_DBTP_TDC_Msk           (0x1UL << FDCAN_DBTP_TDC_Pos)             /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC               FDCAN_DBTP_TDC_Msk                        /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos          (4U)
+#define FDCAN_TEST_LBCK_Msk          (0x1UL << FDCAN_TEST_LBCK_Pos)            /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK              FDCAN_TEST_LBCK_Msk                       /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos            (5U)
+#define FDCAN_TEST_TX_Msk            (0x3UL << FDCAN_TEST_TX_Pos)              /*!< 0x00000060 */
+#define FDCAN_TEST_TX                FDCAN_TEST_TX_Msk                         /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos            (7U)
+#define FDCAN_TEST_RX_Msk            (0x1UL << FDCAN_TEST_RX_Pos)              /*!< 0x00000080 */
+#define FDCAN_TEST_RX                FDCAN_TEST_RX_Msk                         /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos            (0U)
+#define FDCAN_RWD_WDC_Msk            (0xFFUL << FDCAN_RWD_WDC_Pos)             /*!< 0x000000FF */
+#define FDCAN_RWD_WDC                FDCAN_RWD_WDC_Msk                         /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos            (8U)
+#define FDCAN_RWD_WDV_Msk            (0xFFUL << FDCAN_RWD_WDV_Pos)             /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV                FDCAN_RWD_WDV_Msk                         /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  *******************/
+#define FDCAN_CCCR_INIT_Pos          (0U)
+#define FDCAN_CCCR_INIT_Msk          (0x1UL << FDCAN_CCCR_INIT_Pos)            /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT              FDCAN_CCCR_INIT_Msk                       /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos           (1U)
+#define FDCAN_CCCR_CCE_Msk           (0x1UL << FDCAN_CCCR_CCE_Pos)             /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE               FDCAN_CCCR_CCE_Msk                        /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos           (2U)
+#define FDCAN_CCCR_ASM_Msk           (0x1UL << FDCAN_CCCR_ASM_Pos)             /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM               FDCAN_CCCR_ASM_Msk                        /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos           (3U)
+#define FDCAN_CCCR_CSA_Msk           (0x1UL << FDCAN_CCCR_CSA_Pos)             /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA               FDCAN_CCCR_CSA_Msk                        /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos           (4U)
+#define FDCAN_CCCR_CSR_Msk           (0x1UL << FDCAN_CCCR_CSR_Pos)             /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR               FDCAN_CCCR_CSR_Msk                        /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos           (5U)
+#define FDCAN_CCCR_MON_Msk           (0x1UL << FDCAN_CCCR_MON_Pos)             /*!< 0x00000020 */
+#define FDCAN_CCCR_MON               FDCAN_CCCR_MON_Msk                        /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos           (6U)
+#define FDCAN_CCCR_DAR_Msk           (0x1UL << FDCAN_CCCR_DAR_Pos)             /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR               FDCAN_CCCR_DAR_Msk                        /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos          (7U)
+#define FDCAN_CCCR_TEST_Msk          (0x1UL << FDCAN_CCCR_TEST_Pos)            /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST              FDCAN_CCCR_TEST_Msk                       /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos          (8U)
+#define FDCAN_CCCR_FDOE_Msk          (0x1UL << FDCAN_CCCR_FDOE_Pos)            /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE              FDCAN_CCCR_FDOE_Msk                       /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos          (9U)
+#define FDCAN_CCCR_BRSE_Msk          (0x1UL << FDCAN_CCCR_BRSE_Pos)            /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE              FDCAN_CCCR_BRSE_Msk                       /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos          (12U)
+#define FDCAN_CCCR_PXHD_Msk          (0x1UL << FDCAN_CCCR_PXHD_Pos)            /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD              FDCAN_CCCR_PXHD_Msk                       /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos          (13U)
+#define FDCAN_CCCR_EFBI_Msk          (0x1UL << FDCAN_CCCR_EFBI_Pos)            /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI              FDCAN_CCCR_EFBI_Msk                       /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos           (14U)
+#define FDCAN_CCCR_TXP_Msk           (0x1UL << FDCAN_CCCR_TXP_Pos)             /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP               FDCAN_CCCR_TXP_Msk                        /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos          (15U)
+#define FDCAN_CCCR_NISO_Msk          (0x1UL << FDCAN_CCCR_NISO_Pos)            /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO              FDCAN_CCCR_NISO_Msk                       /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  *******************/
+#define FDCAN_NBTP_NTSEG2_Pos        (0U)
+#define FDCAN_NBTP_NTSEG2_Msk        (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)         /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2            FDCAN_NBTP_NTSEG2_Msk                     /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos        (8U)
+#define FDCAN_NBTP_NTSEG1_Msk        (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)         /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1            FDCAN_NBTP_NTSEG1_Msk                     /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos          (16U)
+#define FDCAN_NBTP_NBRP_Msk          (0x1FFUL << FDCAN_NBTP_NBRP_Pos)          /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP              FDCAN_NBTP_NBRP_Msk                       /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos          (25U)
+#define FDCAN_NBTP_NSJW_Msk          (0x7FUL << FDCAN_NBTP_NSJW_Pos)           /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW              FDCAN_NBTP_NSJW_Msk                       /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  *******************/
+#define FDCAN_TSCC_TSS_Pos           (0U)
+#define FDCAN_TSCC_TSS_Msk           (0x3UL << FDCAN_TSCC_TSS_Pos)             /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS               FDCAN_TSCC_TSS_Msk                        /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos           (16U)
+#define FDCAN_TSCC_TCP_Msk           (0xFUL << FDCAN_TSCC_TCP_Pos)             /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP               FDCAN_TSCC_TCP_Msk                        /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  *******************/
+#define FDCAN_TSCV_TSC_Pos           (0U)
+#define FDCAN_TSCV_TSC_Msk           (0xFFFFUL << FDCAN_TSCV_TSC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC               FDCAN_TSCV_TSC_Msk                        /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  *******************/
+#define FDCAN_TOCC_ETOC_Pos          (0U)
+#define FDCAN_TOCC_ETOC_Msk          (0x1UL << FDCAN_TOCC_ETOC_Pos)            /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC              FDCAN_TOCC_ETOC_Msk                       /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos           (1U)
+#define FDCAN_TOCC_TOS_Msk           (0x3UL << FDCAN_TOCC_TOS_Pos)             /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS               FDCAN_TOCC_TOS_Msk                        /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos           (16U)
+#define FDCAN_TOCC_TOP_Msk           (0xFFFFUL << FDCAN_TOCC_TOP_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP               FDCAN_TOCC_TOP_Msk                        /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  *******************/
+#define FDCAN_TOCV_TOC_Pos           (0U)
+#define FDCAN_TOCV_TOC_Msk           (0xFFFFUL << FDCAN_TOCV_TOC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC               FDCAN_TOCV_TOC_Msk                        /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  ********************/
+#define FDCAN_ECR_TEC_Pos            (0U)
+#define FDCAN_ECR_TEC_Msk            (0xFFUL << FDCAN_ECR_TEC_Pos)             /*!< 0x000000FF */
+#define FDCAN_ECR_TEC                FDCAN_ECR_TEC_Msk                         /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos            (8U)
+#define FDCAN_ECR_REC_Msk            (0x7FUL << FDCAN_ECR_REC_Pos)             /*!< 0x00007F00 */
+#define FDCAN_ECR_REC                FDCAN_ECR_REC_Msk                         /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos             (15U)
+#define FDCAN_ECR_RP_Msk             (0x1UL << FDCAN_ECR_RP_Pos)               /*!< 0x00008000 */
+#define FDCAN_ECR_RP                 FDCAN_ECR_RP_Msk                          /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos            (16U)
+#define FDCAN_ECR_CEL_Msk            (0xFFUL << FDCAN_ECR_CEL_Pos)             /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL                FDCAN_ECR_CEL_Msk                         /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  ********************/
+#define FDCAN_PSR_LEC_Pos            (0U)
+#define FDCAN_PSR_LEC_Msk            (0x7UL << FDCAN_PSR_LEC_Pos)              /*!< 0x00000007 */
+#define FDCAN_PSR_LEC                FDCAN_PSR_LEC_Msk                         /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos            (3U)
+#define FDCAN_PSR_ACT_Msk            (0x3UL << FDCAN_PSR_ACT_Pos)              /*!< 0x00000018 */
+#define FDCAN_PSR_ACT                FDCAN_PSR_ACT_Msk                         /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos             (5U)
+#define FDCAN_PSR_EP_Msk             (0x1UL << FDCAN_PSR_EP_Pos)               /*!< 0x00000020 */
+#define FDCAN_PSR_EP                 FDCAN_PSR_EP_Msk                          /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos             (6U)
+#define FDCAN_PSR_EW_Msk             (0x1UL << FDCAN_PSR_EW_Pos)               /*!< 0x00000040 */
+#define FDCAN_PSR_EW                 FDCAN_PSR_EW_Msk                          /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos             (7U)
+#define FDCAN_PSR_BO_Msk             (0x1UL << FDCAN_PSR_BO_Pos)               /*!< 0x00000080 */
+#define FDCAN_PSR_BO                 FDCAN_PSR_BO_Msk                          /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos           (8U)
+#define FDCAN_PSR_DLEC_Msk           (0x7UL << FDCAN_PSR_DLEC_Pos)             /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC               FDCAN_PSR_DLEC_Msk                        /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos           (11U)
+#define FDCAN_PSR_RESI_Msk           (0x1UL << FDCAN_PSR_RESI_Pos)             /*!< 0x00000800 */
+#define FDCAN_PSR_RESI               FDCAN_PSR_RESI_Msk                        /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos           (12U)
+#define FDCAN_PSR_RBRS_Msk           (0x1UL << FDCAN_PSR_RBRS_Pos)             /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS               FDCAN_PSR_RBRS_Msk                        /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos           (13U)
+#define FDCAN_PSR_REDL_Msk           (0x1UL << FDCAN_PSR_REDL_Pos)             /*!< 0x00002000 */
+#define FDCAN_PSR_REDL               FDCAN_PSR_REDL_Msk                        /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos            (14U)
+#define FDCAN_PSR_PXE_Msk            (0x1UL << FDCAN_PSR_PXE_Pos)              /*!< 0x00004000 */
+#define FDCAN_PSR_PXE                FDCAN_PSR_PXE_Msk                         /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos           (16U)
+#define FDCAN_PSR_TDCV_Msk           (0x7FUL << FDCAN_PSR_TDCV_Pos)            /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV               FDCAN_PSR_TDCV_Msk                        /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  *******************/
+#define FDCAN_TDCR_TDCF_Pos          (0U)
+#define FDCAN_TDCR_TDCF_Msk          (0x7FUL << FDCAN_TDCR_TDCF_Pos)           /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF              FDCAN_TDCR_TDCF_Msk                       /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos          (8U)
+#define FDCAN_TDCR_TDCO_Msk          (0x7FUL << FDCAN_TDCR_TDCO_Pos)           /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO              FDCAN_TDCR_TDCO_Msk                       /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  *********************/
+#define FDCAN_IR_RF0N_Pos            (0U)
+#define FDCAN_IR_RF0N_Msk            (0x1UL << FDCAN_IR_RF0N_Pos)              /*!< 0x00000001 */
+#define FDCAN_IR_RF0N                FDCAN_IR_RF0N_Msk                         /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos            (1U)
+#define FDCAN_IR_RF0W_Msk            (0x1UL << FDCAN_IR_RF0W_Pos)              /*!< 0x00000002 */
+#define FDCAN_IR_RF0W                FDCAN_IR_RF0W_Msk                         /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos            (2U)
+#define FDCAN_IR_RF0F_Msk            (0x1UL << FDCAN_IR_RF0F_Pos)              /*!< 0x00000004 */
+#define FDCAN_IR_RF0F                FDCAN_IR_RF0F_Msk                         /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos            (3U)
+#define FDCAN_IR_RF0L_Msk            (0x1UL << FDCAN_IR_RF0L_Pos)              /*!< 0x00000008 */
+#define FDCAN_IR_RF0L                FDCAN_IR_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos            (4U)
+#define FDCAN_IR_RF1N_Msk            (0x1UL << FDCAN_IR_RF1N_Pos)              /*!< 0x00000010 */
+#define FDCAN_IR_RF1N                FDCAN_IR_RF1N_Msk                         /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos            (5U)
+#define FDCAN_IR_RF1W_Msk            (0x1UL << FDCAN_IR_RF1W_Pos)              /*!< 0x00000020 */
+#define FDCAN_IR_RF1W                FDCAN_IR_RF1W_Msk                         /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos            (6U)
+#define FDCAN_IR_RF1F_Msk            (0x1UL << FDCAN_IR_RF1F_Pos)              /*!< 0x00000040 */
+#define FDCAN_IR_RF1F                FDCAN_IR_RF1F_Msk                         /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos            (7U)
+#define FDCAN_IR_RF1L_Msk            (0x1UL << FDCAN_IR_RF1L_Pos)              /*!< 0x00000080 */
+#define FDCAN_IR_RF1L                FDCAN_IR_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos             (8U)
+#define FDCAN_IR_HPM_Msk             (0x1UL << FDCAN_IR_HPM_Pos)               /*!< 0x00000100 */
+#define FDCAN_IR_HPM                 FDCAN_IR_HPM_Msk                          /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos              (9U)
+#define FDCAN_IR_TC_Msk              (0x1UL << FDCAN_IR_TC_Pos)                /*!< 0x00000200 */
+#define FDCAN_IR_TC                  FDCAN_IR_TC_Msk                           /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos             (10U)
+#define FDCAN_IR_TCF_Msk             (0x1UL << FDCAN_IR_TCF_Pos)               /*!< 0x00000400 */
+#define FDCAN_IR_TCF                 FDCAN_IR_TCF_Msk                          /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos             (11U)
+#define FDCAN_IR_TFE_Msk             (0x1UL << FDCAN_IR_TFE_Pos)               /*!< 0x00000800 */
+#define FDCAN_IR_TFE                 FDCAN_IR_TFE_Msk                          /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos            (12U)
+#define FDCAN_IR_TEFN_Msk            (0x1UL << FDCAN_IR_TEFN_Pos)              /*!< 0x00001000 */
+#define FDCAN_IR_TEFN                FDCAN_IR_TEFN_Msk                         /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos            (13U)
+#define FDCAN_IR_TEFW_Msk            (0x1UL << FDCAN_IR_TEFW_Pos)              /*!< 0x00002000 */
+#define FDCAN_IR_TEFW                FDCAN_IR_TEFW_Msk                         /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos            (14U)
+#define FDCAN_IR_TEFF_Msk            (0x1UL << FDCAN_IR_TEFF_Pos)              /*!< 0x00004000 */
+#define FDCAN_IR_TEFF                FDCAN_IR_TEFF_Msk                         /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos            (15U)
+#define FDCAN_IR_TEFL_Msk            (0x1UL << FDCAN_IR_TEFL_Pos)              /*!< 0x00008000 */
+#define FDCAN_IR_TEFL                FDCAN_IR_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos             (16U)
+#define FDCAN_IR_TSW_Msk             (0x1UL << FDCAN_IR_TSW_Pos)               /*!< 0x00010000 */
+#define FDCAN_IR_TSW                 FDCAN_IR_TSW_Msk                          /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos            (17U)
+#define FDCAN_IR_MRAF_Msk            (0x1UL << FDCAN_IR_MRAF_Pos)              /*!< 0x00020000 */
+#define FDCAN_IR_MRAF                FDCAN_IR_MRAF_Msk                         /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos             (18U)
+#define FDCAN_IR_TOO_Msk             (0x1UL << FDCAN_IR_TOO_Pos)               /*!< 0x00040000 */
+#define FDCAN_IR_TOO                 FDCAN_IR_TOO_Msk                          /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos             (19U)
+#define FDCAN_IR_DRX_Msk             (0x1UL << FDCAN_IR_DRX_Pos)               /*!< 0x00080000 */
+#define FDCAN_IR_DRX                 FDCAN_IR_DRX_Msk                          /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos             (22U)
+#define FDCAN_IR_ELO_Msk             (0x1UL << FDCAN_IR_ELO_Pos)               /*!< 0x00400000 */
+#define FDCAN_IR_ELO                 FDCAN_IR_ELO_Msk                          /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos              (23U)
+#define FDCAN_IR_EP_Msk              (0x1UL << FDCAN_IR_EP_Pos)                /*!< 0x00800000 */
+#define FDCAN_IR_EP                  FDCAN_IR_EP_Msk                           /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos              (24U)
+#define FDCAN_IR_EW_Msk              (0x1UL << FDCAN_IR_EW_Pos)                /*!< 0x01000000 */
+#define FDCAN_IR_EW                  FDCAN_IR_EW_Msk                           /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos              (25U)
+#define FDCAN_IR_BO_Msk              (0x1UL << FDCAN_IR_BO_Pos)                /*!< 0x02000000 */
+#define FDCAN_IR_BO                  FDCAN_IR_BO_Msk                           /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos             (26U)
+#define FDCAN_IR_WDI_Msk             (0x1UL << FDCAN_IR_WDI_Pos)               /*!< 0x04000000 */
+#define FDCAN_IR_WDI                 FDCAN_IR_WDI_Msk                          /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos             (27U)
+#define FDCAN_IR_PEA_Msk             (0x1UL << FDCAN_IR_PEA_Pos)               /*!< 0x08000000 */
+#define FDCAN_IR_PEA                 FDCAN_IR_PEA_Msk                          /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos             (28U)
+#define FDCAN_IR_PED_Msk             (0x1UL << FDCAN_IR_PED_Pos)               /*!< 0x10000000 */
+#define FDCAN_IR_PED                 FDCAN_IR_PED_Msk                          /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos             (29U)
+#define FDCAN_IR_ARA_Msk             (0x1UL << FDCAN_IR_ARA_Pos)               /*!< 0x20000000 */
+#define FDCAN_IR_ARA                 FDCAN_IR_ARA_Msk                          /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  *********************/
+#define FDCAN_IE_RF0NE_Pos           (0U)
+#define FDCAN_IE_RF0NE_Msk           (0x1UL << FDCAN_IE_RF0NE_Pos)             /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE               FDCAN_IE_RF0NE_Msk                        /*!<Rx FIFO 0 New Message Enable             */
+#define FDCAN_IE_RF0WE_Pos           (1U)
+#define FDCAN_IE_RF0WE_Msk           (0x1UL << FDCAN_IE_RF0WE_Pos)             /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE               FDCAN_IE_RF0WE_Msk                        /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos           (2U)
+#define FDCAN_IE_RF0FE_Msk           (0x1UL << FDCAN_IE_RF0FE_Pos)             /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE               FDCAN_IE_RF0FE_Msk                        /*!<Rx FIFO 0 Full Enable                    */
+#define FDCAN_IE_RF0LE_Pos           (3U)
+#define FDCAN_IE_RF0LE_Msk           (0x1UL << FDCAN_IE_RF0LE_Pos)             /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE               FDCAN_IE_RF0LE_Msk                        /*!<Rx FIFO 0 Message Lost Enable            */
+#define FDCAN_IE_RF1NE_Pos           (4U)
+#define FDCAN_IE_RF1NE_Msk           (0x1UL << FDCAN_IE_RF1NE_Pos)             /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE               FDCAN_IE_RF1NE_Msk                        /*!<Rx FIFO 1 New Message Enable             */
+#define FDCAN_IE_RF1WE_Pos           (5U)
+#define FDCAN_IE_RF1WE_Msk           (0x1UL << FDCAN_IE_RF1WE_Pos)             /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE               FDCAN_IE_RF1WE_Msk                        /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos           (6U)
+#define FDCAN_IE_RF1FE_Msk           (0x1UL << FDCAN_IE_RF1FE_Pos)             /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE               FDCAN_IE_RF1FE_Msk                        /*!<Rx FIFO 1 Full Enable                    */
+#define FDCAN_IE_RF1LE_Pos           (7U)
+#define FDCAN_IE_RF1LE_Msk           (0x1UL << FDCAN_IE_RF1LE_Pos)             /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE               FDCAN_IE_RF1LE_Msk                        /*!<Rx FIFO 1 Message Lost Enable            */
+#define FDCAN_IE_HPME_Pos            (8U)
+#define FDCAN_IE_HPME_Msk            (0x1UL << FDCAN_IE_HPME_Pos)              /*!< 0x00000100 */
+#define FDCAN_IE_HPME                FDCAN_IE_HPME_Msk                         /*!<High Priority Message Enable             */
+#define FDCAN_IE_TCE_Pos             (9U)
+#define FDCAN_IE_TCE_Msk             (0x1UL << FDCAN_IE_TCE_Pos)               /*!< 0x00000200 */
+#define FDCAN_IE_TCE                 FDCAN_IE_TCE_Msk                          /*!<Transmission Completed Enable            */
+#define FDCAN_IE_TCFE_Pos            (10U)
+#define FDCAN_IE_TCFE_Msk            (0x1UL << FDCAN_IE_TCFE_Pos)              /*!< 0x00000400 */
+#define FDCAN_IE_TCFE                FDCAN_IE_TCFE_Msk                         /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos            (11U)
+#define FDCAN_IE_TFEE_Msk            (0x1UL << FDCAN_IE_TFEE_Pos)              /*!< 0x00000800 */
+#define FDCAN_IE_TFEE                FDCAN_IE_TFEE_Msk                         /*!<Tx FIFO Empty Enable                     */
+#define FDCAN_IE_TEFNE_Pos           (12U)
+#define FDCAN_IE_TEFNE_Msk           (0x1UL << FDCAN_IE_TEFNE_Pos)             /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE               FDCAN_IE_TEFNE_Msk                        /*!<Tx Event FIFO New Entry Enable           */
+#define FDCAN_IE_TEFWE_Pos           (13U)
+#define FDCAN_IE_TEFWE_Msk           (0x1UL << FDCAN_IE_TEFWE_Pos)             /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE               FDCAN_IE_TEFWE_Msk                        /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos           (14U)
+#define FDCAN_IE_TEFFE_Msk           (0x1UL << FDCAN_IE_TEFFE_Pos)             /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE               FDCAN_IE_TEFFE_Msk                        /*!<Tx Event FIFO Full Enable                */
+#define FDCAN_IE_TEFLE_Pos           (15U)
+#define FDCAN_IE_TEFLE_Msk           (0x1UL << FDCAN_IE_TEFLE_Pos)             /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE               FDCAN_IE_TEFLE_Msk                        /*!<Tx Event FIFO Element Lost Enable        */
+#define FDCAN_IE_TSWE_Pos            (16U)
+#define FDCAN_IE_TSWE_Msk            (0x1UL << FDCAN_IE_TSWE_Pos)              /*!< 0x00010000 */
+#define FDCAN_IE_TSWE                FDCAN_IE_TSWE_Msk                         /*!<Timestamp Wraparound Enable              */
+#define FDCAN_IE_MRAFE_Pos           (17U)
+#define FDCAN_IE_MRAFE_Msk           (0x1UL << FDCAN_IE_MRAFE_Pos)             /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE               FDCAN_IE_MRAFE_Msk                        /*!<Message RAM Access Failure Enable        */
+#define FDCAN_IE_TOOE_Pos            (18U)
+#define FDCAN_IE_TOOE_Msk            (0x1UL << FDCAN_IE_TOOE_Pos)              /*!< 0x00040000 */
+#define FDCAN_IE_TOOE                FDCAN_IE_TOOE_Msk                         /*!<Timeout Occurred Enable                  */
+#define FDCAN_IE_DRXE_Pos            (19U)
+#define FDCAN_IE_DRXE_Msk            (0x1UL << FDCAN_IE_DRXE_Pos)              /*!< 0x00080000 */
+#define FDCAN_IE_DRXE                FDCAN_IE_DRXE_Msk                         /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos            (20U)
+#define FDCAN_IE_BECE_Msk            (0x1UL << FDCAN_IE_BECE_Pos)              /*!< 0x00100000 */
+#define FDCAN_IE_BECE                FDCAN_IE_BECE_Msk                         /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos            (21U)
+#define FDCAN_IE_BEUE_Msk            (0x1UL << FDCAN_IE_BEUE_Pos)              /*!< 0x00200000 */
+#define FDCAN_IE_BEUE                FDCAN_IE_BEUE_Msk                         /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos            (22U)
+#define FDCAN_IE_ELOE_Msk            (0x1UL << FDCAN_IE_ELOE_Pos)              /*!< 0x00400000 */
+#define FDCAN_IE_ELOE                FDCAN_IE_ELOE_Msk                         /*!<Error Logging Overflow Enable            */
+#define FDCAN_IE_EPE_Pos             (23U)
+#define FDCAN_IE_EPE_Msk             (0x1UL << FDCAN_IE_EPE_Pos)               /*!< 0x00800000 */
+#define FDCAN_IE_EPE                 FDCAN_IE_EPE_Msk                          /*!<Error Passive Enable                     */
+#define FDCAN_IE_EWE_Pos             (24U)
+#define FDCAN_IE_EWE_Msk             (0x1UL << FDCAN_IE_EWE_Pos)               /*!< 0x01000000 */
+#define FDCAN_IE_EWE                 FDCAN_IE_EWE_Msk                          /*!<Warning Status Enable                    */
+#define FDCAN_IE_BOE_Pos             (25U)
+#define FDCAN_IE_BOE_Msk             (0x1UL << FDCAN_IE_BOE_Pos)               /*!< 0x02000000 */
+#define FDCAN_IE_BOE                 FDCAN_IE_BOE_Msk                          /*!<Bus_Off Status Enable                    */
+#define FDCAN_IE_WDIE_Pos            (26U)
+#define FDCAN_IE_WDIE_Msk            (0x1UL << FDCAN_IE_WDIE_Pos)              /*!< 0x04000000 */
+#define FDCAN_IE_WDIE                FDCAN_IE_WDIE_Msk                         /*!<Watchdog Interrupt Enable                */
+#define FDCAN_IE_PEAE_Pos            (27U)
+#define FDCAN_IE_PEAE_Msk            (0x1UL << FDCAN_IE_PEAE_Pos)              /*!< 0x08000000 */
+#define FDCAN_IE_PEAE                FDCAN_IE_PEAE_Msk                         /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos            (28U)
+#define FDCAN_IE_PEDE_Msk            (0x1UL << FDCAN_IE_PEDE_Pos)              /*!< 0x10000000 */
+#define FDCAN_IE_PEDE                FDCAN_IE_PEDE_Msk                         /*!<Protocol Error in Data Phase Enable      */
+#define FDCAN_IE_ARAE_Pos            (29U)
+#define FDCAN_IE_ARAE_Msk            (0x1UL << FDCAN_IE_ARAE_Pos)              /*!< 0x20000000 */
+#define FDCAN_IE_ARAE                FDCAN_IE_ARAE_Msk                         /*!<Access to Reserved Address Enable        */
+
+/*****************  Bit definition for FDCAN_ILS register  ********************/
+#define FDCAN_ILS_RF0NL_Pos          (0U)
+#define FDCAN_ILS_RF0NL_Msk          (0x1UL << FDCAN_ILS_RF0NL_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL              FDCAN_ILS_RF0NL_Msk                       /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos          (1U)
+#define FDCAN_ILS_RF0WL_Msk          (0x1UL << FDCAN_ILS_RF0WL_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL              FDCAN_ILS_RF0WL_Msk                       /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos          (2U)
+#define FDCAN_ILS_RF0FL_Msk          (0x1UL << FDCAN_ILS_RF0FL_Pos)            /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL              FDCAN_ILS_RF0FL_Msk                       /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos          (3U)
+#define FDCAN_ILS_RF0LL_Msk          (0x1UL << FDCAN_ILS_RF0LL_Pos)            /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL              FDCAN_ILS_RF0LL_Msk                       /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos          (4U)
+#define FDCAN_ILS_RF1NL_Msk          (0x1UL << FDCAN_ILS_RF1NL_Pos)            /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL              FDCAN_ILS_RF1NL_Msk                       /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos          (5U)
+#define FDCAN_ILS_RF1WL_Msk          (0x1UL << FDCAN_ILS_RF1WL_Pos)            /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL              FDCAN_ILS_RF1WL_Msk                       /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos          (6U)
+#define FDCAN_ILS_RF1FL_Msk          (0x1UL << FDCAN_ILS_RF1FL_Pos)            /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL              FDCAN_ILS_RF1FL_Msk                       /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos          (7U)
+#define FDCAN_ILS_RF1LL_Msk          (0x1UL << FDCAN_ILS_RF1LL_Pos)            /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL              FDCAN_ILS_RF1LL_Msk                       /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos           (8U)
+#define FDCAN_ILS_HPML_Msk           (0x1UL << FDCAN_ILS_HPML_Pos)             /*!< 0x00000100 */
+#define FDCAN_ILS_HPML               FDCAN_ILS_HPML_Msk                        /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos            (9U)
+#define FDCAN_ILS_TCL_Msk            (0x1UL << FDCAN_ILS_TCL_Pos)              /*!< 0x00000200 */
+#define FDCAN_ILS_TCL                FDCAN_ILS_TCL_Msk                         /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos           (10U)
+#define FDCAN_ILS_TCFL_Msk           (0x1UL << FDCAN_ILS_TCFL_Pos)             /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL               FDCAN_ILS_TCFL_Msk                        /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos           (11U)
+#define FDCAN_ILS_TFEL_Msk           (0x1UL << FDCAN_ILS_TFEL_Pos)             /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL               FDCAN_ILS_TFEL_Msk                        /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos          (12U)
+#define FDCAN_ILS_TEFNL_Msk          (0x1UL << FDCAN_ILS_TEFNL_Pos)            /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL              FDCAN_ILS_TEFNL_Msk                       /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos          (13U)
+#define FDCAN_ILS_TEFWL_Msk          (0x1UL << FDCAN_ILS_TEFWL_Pos)            /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL              FDCAN_ILS_TEFWL_Msk                       /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos          (14U)
+#define FDCAN_ILS_TEFFL_Msk          (0x1UL << FDCAN_ILS_TEFFL_Pos)            /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL              FDCAN_ILS_TEFFL_Msk                       /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos          (15U)
+#define FDCAN_ILS_TEFLL_Msk          (0x1UL << FDCAN_ILS_TEFLL_Pos)            /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL              FDCAN_ILS_TEFLL_Msk                       /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos           (16U)
+#define FDCAN_ILS_TSWL_Msk           (0x1UL << FDCAN_ILS_TSWL_Pos)             /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL               FDCAN_ILS_TSWL_Msk                        /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFL_Pos          (17U)
+#define FDCAN_ILS_MRAFL_Msk          (0x1UL << FDCAN_ILS_MRAFL_Pos)            /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFL              FDCAN_ILS_MRAFL_Msk                       /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOL_Pos           (18U)
+#define FDCAN_ILS_TOOL_Msk           (0x1UL << FDCAN_ILS_TOOL_Pos)             /*!< 0x00040000 */
+#define FDCAN_ILS_TOOL               FDCAN_ILS_TOOL_Msk                        /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXL_Pos           (19U)
+#define FDCAN_ILS_DRXL_Msk           (0x1UL << FDCAN_ILS_DRXL_Pos)             /*!< 0x00080000 */
+#define FDCAN_ILS_DRXL               FDCAN_ILS_DRXL_Msk                        /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_ELOL_Pos           (22U)
+#define FDCAN_ILS_ELOL_Msk           (0x1UL << FDCAN_ILS_ELOL_Pos)             /*!< 0x00400000 */
+#define FDCAN_ILS_ELOL               FDCAN_ILS_ELOL_Msk                        /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPL_Pos            (23U)
+#define FDCAN_ILS_EPL_Msk            (0x1UL << FDCAN_ILS_EPL_Pos)              /*!< 0x00800000 */
+#define FDCAN_ILS_EPL                FDCAN_ILS_EPL_Msk                         /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWL_Pos            (24U)
+#define FDCAN_ILS_EWL_Msk            (0x1UL << FDCAN_ILS_EWL_Pos)              /*!< 0x01000000 */
+#define FDCAN_ILS_EWL                FDCAN_ILS_EWL_Msk                         /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOL_Pos            (25U)
+#define FDCAN_ILS_BOL_Msk            (0x1UL << FDCAN_ILS_BOL_Pos)              /*!< 0x02000000 */
+#define FDCAN_ILS_BOL                FDCAN_ILS_BOL_Msk                         /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIL_Pos           (26U)
+#define FDCAN_ILS_WDIL_Msk           (0x1UL << FDCAN_ILS_WDIL_Pos)             /*!< 0x04000000 */
+#define FDCAN_ILS_WDIL               FDCAN_ILS_WDIL_Msk                        /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAL_Pos           (27U)
+#define FDCAN_ILS_PEAL_Msk           (0x1UL << FDCAN_ILS_PEAL_Pos)             /*!< 0x08000000 */
+#define FDCAN_ILS_PEAL               FDCAN_ILS_PEAL_Msk                        /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDL_Pos           (28U)
+#define FDCAN_ILS_PEDL_Msk           (0x1UL << FDCAN_ILS_PEDL_Pos)             /*!< 0x10000000 */
+#define FDCAN_ILS_PEDL               FDCAN_ILS_PEDL_Msk                        /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAL_Pos           (29U)
+#define FDCAN_ILS_ARAL_Msk           (0x1UL << FDCAN_ILS_ARAL_Pos)             /*!< 0x20000000 */
+#define FDCAN_ILS_ARAL               FDCAN_ILS_ARAL_Msk                        /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  ********************/
+#define FDCAN_ILE_EINT0_Pos          (0U)
+#define FDCAN_ILE_EINT0_Msk          (0x1UL << FDCAN_ILE_EINT0_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0              FDCAN_ILE_EINT0_Msk                       /*!<Enable Interrupt Line 0                  */
+#define FDCAN_ILE_EINT1_Pos          (1U)
+#define FDCAN_ILE_EINT1_Msk          (0x1UL << FDCAN_ILE_EINT1_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1              FDCAN_ILE_EINT1_Msk                       /*!<Enable Interrupt Line 1                  */
+
+/*****************  Bit definition for FDCAN_GFC register  ******************/
+#define FDCAN_GFC_RRFE_Pos           (0U)
+#define FDCAN_GFC_RRFE_Msk           (0x1UL << FDCAN_GFC_RRFE_Pos)             /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE               FDCAN_GFC_RRFE_Msk                        /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos           (1U)
+#define FDCAN_GFC_RRFS_Msk           (0x1UL << FDCAN_GFC_RRFS_Pos)             /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS               FDCAN_GFC_RRFS_Msk                        /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos           (2U)
+#define FDCAN_GFC_ANFE_Msk           (0x3UL << FDCAN_GFC_ANFE_Pos)             /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE               FDCAN_GFC_ANFE_Msk                        /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos           (4U)
+#define FDCAN_GFC_ANFS_Msk           (0x3UL << FDCAN_GFC_ANFS_Pos)             /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS               FDCAN_GFC_ANFS_Msk                        /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos        (2U)
+#define FDCAN_SIDFC_FLSSA_Msk        (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA            FDCAN_SIDFC_FLSSA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos          (16U)
+#define FDCAN_SIDFC_LSS_Msk          (0xFFUL << FDCAN_SIDFC_LSS_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS              FDCAN_SIDFC_LSS_Msk                       /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos        (2U)
+#define FDCAN_XIDFC_FLESA_Msk        (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA            FDCAN_XIDFC_FLESA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos          (16U)
+#define FDCAN_XIDFC_LSE_Msk          (0x7FUL << FDCAN_XIDFC_LSE_Pos)           /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE              FDCAN_XIDFC_LSE_Msk                       /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ******************/
+#define FDCAN_XIDAM_EIDM_Pos         (0U)
+#define FDCAN_XIDAM_EIDM_Msk         (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)    /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM             FDCAN_XIDAM_EIDM_Msk                      /*!<Extended ID Mask                         */
+
+/*****************  Bit definition for FDCAN_HPMS register  *******************/
+#define FDCAN_HPMS_BIDX_Pos          (0U)
+#define FDCAN_HPMS_BIDX_Msk          (0x3FUL << FDCAN_HPMS_BIDX_Pos)           /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX              FDCAN_HPMS_BIDX_Msk                       /*!<Buffer Index                             */
+#define FDCAN_HPMS_MSI_Pos           (6U)
+#define FDCAN_HPMS_MSI_Msk           (0x3UL << FDCAN_HPMS_MSI_Pos)             /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI               FDCAN_HPMS_MSI_Msk                        /*!<Message Storage Indicator                */
+#define FDCAN_HPMS_FIDX_Pos          (8U)
+#define FDCAN_HPMS_FIDX_Msk          (0x7FUL << FDCAN_HPMS_FIDX_Pos)           /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX              FDCAN_HPMS_FIDX_Msk                       /*!<Filter Index                             */
+#define FDCAN_HPMS_FLST_Pos          (15U)
+#define FDCAN_HPMS_FLST_Msk          (0x1UL << FDCAN_HPMS_FLST_Pos)            /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST              FDCAN_HPMS_FLST_Msk                       /*!<Filter List                              */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos          (0U)
+#define FDCAN_NDAT1_ND0_Msk          (0x1UL << FDCAN_NDAT1_ND0_Pos)            /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0              FDCAN_NDAT1_ND0_Msk                       /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos          (1U)
+#define FDCAN_NDAT1_ND1_Msk          (0x1UL << FDCAN_NDAT1_ND1_Pos)            /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1              FDCAN_NDAT1_ND1_Msk                       /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos          (2U)
+#define FDCAN_NDAT1_ND2_Msk          (0x1UL << FDCAN_NDAT1_ND2_Pos)            /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2              FDCAN_NDAT1_ND2_Msk                       /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos          (3U)
+#define FDCAN_NDAT1_ND3_Msk          (0x1UL << FDCAN_NDAT1_ND3_Pos)            /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3              FDCAN_NDAT1_ND3_Msk                       /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos          (4U)
+#define FDCAN_NDAT1_ND4_Msk          (0x1UL << FDCAN_NDAT1_ND4_Pos)            /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4              FDCAN_NDAT1_ND4_Msk                       /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos          (5U)
+#define FDCAN_NDAT1_ND5_Msk          (0x1UL << FDCAN_NDAT1_ND5_Pos)            /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5              FDCAN_NDAT1_ND5_Msk                       /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos          (6U)
+#define FDCAN_NDAT1_ND6_Msk          (0x1UL << FDCAN_NDAT1_ND6_Pos)            /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6              FDCAN_NDAT1_ND6_Msk                       /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos          (7U)
+#define FDCAN_NDAT1_ND7_Msk          (0x1UL << FDCAN_NDAT1_ND7_Pos)            /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7              FDCAN_NDAT1_ND7_Msk                       /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos          (8U)
+#define FDCAN_NDAT1_ND8_Msk          (0x1UL << FDCAN_NDAT1_ND8_Pos)            /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8              FDCAN_NDAT1_ND8_Msk                       /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos              (9U)
+#define FDCAN_NDAT1_ND9_Msk          (0x1UL << FDCAN_NDAT1_ND9_Pos)            /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9              FDCAN_NDAT1_ND9_Msk                       /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos            (10U)
+#define FDCAN_NDAT1_ND10_Msk         (0x1UL << FDCAN_NDAT1_ND10_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10             FDCAN_NDAT1_ND10_Msk                      /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos         (11U)
+#define FDCAN_NDAT1_ND11_Msk         (0x1UL << FDCAN_NDAT1_ND11_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11             FDCAN_NDAT1_ND11_Msk                      /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos         (12U)
+#define FDCAN_NDAT1_ND12_Msk         (0x1UL << FDCAN_NDAT1_ND12_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12             FDCAN_NDAT1_ND12_Msk                      /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos         (13U)
+#define FDCAN_NDAT1_ND13_Msk         (0x1UL << FDCAN_NDAT1_ND13_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13             FDCAN_NDAT1_ND13_Msk                      /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos         (14U)
+#define FDCAN_NDAT1_ND14_Msk         (0x1UL << FDCAN_NDAT1_ND14_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14             FDCAN_NDAT1_ND14_Msk                      /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos         (15U)
+#define FDCAN_NDAT1_ND15_Msk         (0x1UL << FDCAN_NDAT1_ND15_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15             FDCAN_NDAT1_ND15_Msk                      /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos         (16U)
+#define FDCAN_NDAT1_ND16_Msk         (0x1UL << FDCAN_NDAT1_ND16_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16             FDCAN_NDAT1_ND16_Msk                      /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos         (17U)
+#define FDCAN_NDAT1_ND17_Msk         (0x1UL << FDCAN_NDAT1_ND17_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17             FDCAN_NDAT1_ND17_Msk                      /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos         (18U)
+#define FDCAN_NDAT1_ND18_Msk         (0x1UL << FDCAN_NDAT1_ND18_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18             FDCAN_NDAT1_ND18_Msk                      /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos         (19U)
+#define FDCAN_NDAT1_ND19_Msk         (0x1UL << FDCAN_NDAT1_ND19_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19             FDCAN_NDAT1_ND19_Msk                      /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos         (20U)
+#define FDCAN_NDAT1_ND20_Msk         (0x1UL << FDCAN_NDAT1_ND20_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20             FDCAN_NDAT1_ND20_Msk                      /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos         (21U)
+#define FDCAN_NDAT1_ND21_Msk         (0x1UL << FDCAN_NDAT1_ND21_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21             FDCAN_NDAT1_ND21_Msk                      /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos         (22U)
+#define FDCAN_NDAT1_ND22_Msk         (0x1UL << FDCAN_NDAT1_ND22_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22             FDCAN_NDAT1_ND22_Msk                      /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos         (23U)
+#define FDCAN_NDAT1_ND23_Msk         (0x1UL << FDCAN_NDAT1_ND23_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23             FDCAN_NDAT1_ND23_Msk                      /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos         (24U)
+#define FDCAN_NDAT1_ND24_Msk         (0x1UL << FDCAN_NDAT1_ND24_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24             FDCAN_NDAT1_ND24_Msk                      /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos         (25U)
+#define FDCAN_NDAT1_ND25_Msk         (0x1UL << FDCAN_NDAT1_ND25_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25             FDCAN_NDAT1_ND25_Msk                      /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos         (26U)
+#define FDCAN_NDAT1_ND26_Msk         (0x1UL << FDCAN_NDAT1_ND26_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26             FDCAN_NDAT1_ND26_Msk                      /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos         (27U)
+#define FDCAN_NDAT1_ND27_Msk         (0x1UL << FDCAN_NDAT1_ND27_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27             FDCAN_NDAT1_ND27_Msk                      /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos         (28U)
+#define FDCAN_NDAT1_ND28_Msk         (0x1UL << FDCAN_NDAT1_ND28_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28             FDCAN_NDAT1_ND28_Msk                      /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos         (29U)
+#define FDCAN_NDAT1_ND29_Msk         (0x1UL << FDCAN_NDAT1_ND29_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29             FDCAN_NDAT1_ND29_Msk                      /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos         (30U)
+#define FDCAN_NDAT1_ND30_Msk         (0x1UL << FDCAN_NDAT1_ND30_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30             FDCAN_NDAT1_ND30_Msk                      /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos         (31U)
+#define FDCAN_NDAT1_ND31_Msk         (0x1UL << FDCAN_NDAT1_ND31_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31             FDCAN_NDAT1_ND31_Msk                      /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos         (0U)
+#define FDCAN_NDAT2_ND32_Msk         (0x1UL << FDCAN_NDAT2_ND32_Pos)           /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32             FDCAN_NDAT2_ND32_Msk                      /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos         (1U)
+#define FDCAN_NDAT2_ND33_Msk         (0x1UL << FDCAN_NDAT2_ND33_Pos)           /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33             FDCAN_NDAT2_ND33_Msk                      /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos         (2U)
+#define FDCAN_NDAT2_ND34_Msk         (0x1UL << FDCAN_NDAT2_ND34_Pos)           /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34             FDCAN_NDAT2_ND34_Msk                      /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos         (3U)
+#define FDCAN_NDAT2_ND35_Msk         (0x1UL << FDCAN_NDAT2_ND35_Pos)           /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35             FDCAN_NDAT2_ND35_Msk                      /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos         (4U)
+#define FDCAN_NDAT2_ND36_Msk         (0x1UL << FDCAN_NDAT2_ND36_Pos)           /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36             FDCAN_NDAT2_ND36_Msk                      /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos         (5U)
+#define FDCAN_NDAT2_ND37_Msk         (0x1UL << FDCAN_NDAT2_ND37_Pos)           /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37             FDCAN_NDAT2_ND37_Msk                      /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos         (6U)
+#define FDCAN_NDAT2_ND38_Msk         (0x1UL << FDCAN_NDAT2_ND38_Pos)           /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38             FDCAN_NDAT2_ND38_Msk                      /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos         (7U)
+#define FDCAN_NDAT2_ND39_Msk         (0x1UL << FDCAN_NDAT2_ND39_Pos)           /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39             FDCAN_NDAT2_ND39_Msk                      /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos         (8U)
+#define FDCAN_NDAT2_ND40_Msk         (0x1UL << FDCAN_NDAT2_ND40_Pos)           /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40             FDCAN_NDAT2_ND40_Msk                      /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos         (9U)
+#define FDCAN_NDAT2_ND41_Msk         (0x1UL << FDCAN_NDAT2_ND41_Pos)           /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41             FDCAN_NDAT2_ND41_Msk                      /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos         (10U)
+#define FDCAN_NDAT2_ND42_Msk         (0x1UL << FDCAN_NDAT2_ND42_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42             FDCAN_NDAT2_ND42_Msk                      /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos         (11U)
+#define FDCAN_NDAT2_ND43_Msk         (0x1UL << FDCAN_NDAT2_ND43_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43             FDCAN_NDAT2_ND43_Msk                      /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos         (12U)
+#define FDCAN_NDAT2_ND44_Msk         (0x1UL << FDCAN_NDAT2_ND44_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44             FDCAN_NDAT2_ND44_Msk                      /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos         (13U)
+#define FDCAN_NDAT2_ND45_Msk         (0x1UL << FDCAN_NDAT2_ND45_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45             FDCAN_NDAT2_ND45_Msk                      /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos         (14U)
+#define FDCAN_NDAT2_ND46_Msk         (0x1UL << FDCAN_NDAT2_ND46_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46             FDCAN_NDAT2_ND46_Msk                      /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos         (15U)
+#define FDCAN_NDAT2_ND47_Msk         (0x1UL << FDCAN_NDAT2_ND47_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47             FDCAN_NDAT2_ND47_Msk                      /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos         (16U)
+#define FDCAN_NDAT2_ND48_Msk         (0x1UL << FDCAN_NDAT2_ND48_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48             FDCAN_NDAT2_ND48_Msk                      /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos         (17U)
+#define FDCAN_NDAT2_ND49_Msk         (0x1UL << FDCAN_NDAT2_ND49_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49             FDCAN_NDAT2_ND49_Msk                      /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos         (18U)
+#define FDCAN_NDAT2_ND50_Msk         (0x1UL << FDCAN_NDAT2_ND50_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50             FDCAN_NDAT2_ND50_Msk                      /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos         (19U)
+#define FDCAN_NDAT2_ND51_Msk         (0x1UL << FDCAN_NDAT2_ND51_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51             FDCAN_NDAT2_ND51_Msk                      /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos         (20U)
+#define FDCAN_NDAT2_ND52_Msk         (0x1UL << FDCAN_NDAT2_ND52_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52             FDCAN_NDAT2_ND52_Msk                      /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos         (21U)
+#define FDCAN_NDAT2_ND53_Msk         (0x1UL << FDCAN_NDAT2_ND53_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53             FDCAN_NDAT2_ND53_Msk                      /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos         (22U)
+#define FDCAN_NDAT2_ND54_Msk         (0x1UL << FDCAN_NDAT2_ND54_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54             FDCAN_NDAT2_ND54_Msk                      /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos         (23U)
+#define FDCAN_NDAT2_ND55_Msk         (0x1UL << FDCAN_NDAT2_ND55_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55             FDCAN_NDAT2_ND55_Msk                      /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos         (24U)
+#define FDCAN_NDAT2_ND56_Msk         (0x1UL << FDCAN_NDAT2_ND56_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56             FDCAN_NDAT2_ND56_Msk                      /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos         (25U)
+#define FDCAN_NDAT2_ND57_Msk         (0x1UL << FDCAN_NDAT2_ND57_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57             FDCAN_NDAT2_ND57_Msk                      /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos         (26U)
+#define FDCAN_NDAT2_ND58_Msk         (0x1UL << FDCAN_NDAT2_ND58_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58             FDCAN_NDAT2_ND58_Msk                      /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos         (27U)
+#define FDCAN_NDAT2_ND59_Msk         (0x1UL << FDCAN_NDAT2_ND59_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59             FDCAN_NDAT2_ND59_Msk                      /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos         (28U)
+#define FDCAN_NDAT2_ND60_Msk         (0x1UL << FDCAN_NDAT2_ND60_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60             FDCAN_NDAT2_ND60_Msk                      /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos         (29U)
+#define FDCAN_NDAT2_ND61_Msk         (0x1UL << FDCAN_NDAT2_ND61_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61             FDCAN_NDAT2_ND61_Msk                      /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos         (30U)
+#define FDCAN_NDAT2_ND62_Msk         (0x1UL << FDCAN_NDAT2_ND62_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62             FDCAN_NDAT2_ND62_Msk                      /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos         (31U)
+#define FDCAN_NDAT2_ND63_Msk         (0x1UL << FDCAN_NDAT2_ND63_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63             FDCAN_NDAT2_ND63_Msk                      /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos         (2U)
+#define FDCAN_RXF0C_F0SA_Msk         (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA             FDCAN_RXF0C_F0SA_Msk                      /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos          (16U)
+#define FDCAN_RXF0C_F0S_Msk          (0x7FUL << FDCAN_RXF0C_F0S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S              FDCAN_RXF0C_F0S_Msk                       /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos         (24U)
+#define FDCAN_RXF0C_F0WM_Msk         (0x7FUL << FDCAN_RXF0C_F0WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM             FDCAN_RXF0C_F0WM_Msk                      /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos         (31U)
+#define FDCAN_RXF0C_F0OM_Msk         (0x1UL << FDCAN_RXF0C_F0OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM             FDCAN_RXF0C_F0OM_Msk                      /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ******************/
+#define FDCAN_RXF0S_F0FL_Pos         (0U)
+#define FDCAN_RXF0S_F0FL_Msk         (0x7FUL << FDCAN_RXF0S_F0FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL             FDCAN_RXF0S_F0FL_Msk                      /*!<Rx FIFO 0 Fill Level                     */
+#define FDCAN_RXF0S_F0GI_Pos         (8U)
+#define FDCAN_RXF0S_F0GI_Msk         (0x3FUL << FDCAN_RXF0S_F0GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI             FDCAN_RXF0S_F0GI_Msk                      /*!<Rx FIFO 0 Get Index                      */
+#define FDCAN_RXF0S_F0PI_Pos         (16U)
+#define FDCAN_RXF0S_F0PI_Msk         (0x3FUL << FDCAN_RXF0S_F0PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI             FDCAN_RXF0S_F0PI_Msk                      /*!<Rx FIFO 0 Put Index                      */
+#define FDCAN_RXF0S_F0F_Pos          (24U)
+#define FDCAN_RXF0S_F0F_Msk          (0x1UL << FDCAN_RXF0S_F0F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F              FDCAN_RXF0S_F0F_Msk                       /*!<Rx FIFO 0 Full                           */
+#define FDCAN_RXF0S_RF0L_Pos         (25U)
+#define FDCAN_RXF0S_RF0L_Msk         (0x1UL << FDCAN_RXF0S_RF0L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L             FDCAN_RXF0S_RF0L_Msk                      /*!<Rx FIFO 0 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ******************/
+#define FDCAN_RXF0A_F0AI_Pos         (0U)
+#define FDCAN_RXF0A_F0AI_Msk         (0x3FUL << FDCAN_RXF0A_F0AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI             FDCAN_RXF0A_F0AI_Msk                      /*!<Rx FIFO 0 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos          (2U)
+#define FDCAN_RXBC_RBSA_Msk          (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA              FDCAN_RXBC_RBSA_Msk                       /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ******************/
+#define FDCAN_RXF1C_F1SA_Pos         (2U)
+#define FDCAN_RXF1C_F1SA_Msk         (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA             FDCAN_RXF1C_F1SA_Msk                      /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos          (16U)
+#define FDCAN_RXF1C_F1S_Msk          (0x7FUL << FDCAN_RXF1C_F1S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S              FDCAN_RXF1C_F1S_Msk                       /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos         (24U)
+#define FDCAN_RXF1C_F1WM_Msk         (0x7FUL << FDCAN_RXF1C_F1WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM             FDCAN_RXF1C_F1WM_Msk                      /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos         (31U)
+#define FDCAN_RXF1C_F1OM_Msk         (0x1UL << FDCAN_RXF1C_F1OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM             FDCAN_RXF1C_F1OM_Msk                      /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ******************/
+#define FDCAN_RXF1S_F1FL_Pos         (0U)
+#define FDCAN_RXF1S_F1FL_Msk         (0x7FUL << FDCAN_RXF1S_F1FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL             FDCAN_RXF1S_F1FL_Msk                      /*!<Rx FIFO 1 Fill Level                     */
+#define FDCAN_RXF1S_F1GI_Pos         (8U)
+#define FDCAN_RXF1S_F1GI_Msk         (0x3FUL << FDCAN_RXF1S_F1GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI             FDCAN_RXF1S_F1GI_Msk                      /*!<Rx FIFO 1 Get Index                      */
+#define FDCAN_RXF1S_F1PI_Pos         (16U)
+#define FDCAN_RXF1S_F1PI_Msk         (0x3FUL << FDCAN_RXF1S_F1PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI             FDCAN_RXF1S_F1PI_Msk                      /*!<Rx FIFO 1 Put Index                      */
+#define FDCAN_RXF1S_F1F_Pos          (24U)
+#define FDCAN_RXF1S_F1F_Msk          (0x1UL << FDCAN_RXF1S_F1F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F              FDCAN_RXF1S_F1F_Msk                       /*!<Rx FIFO 1 Full                           */
+#define FDCAN_RXF1S_RF1L_Pos         (25U)
+#define FDCAN_RXF1S_RF1L_Msk         (0x1UL << FDCAN_RXF1S_RF1L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L             FDCAN_RXF1S_RF1L_Msk                      /*!<Rx FIFO 1 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ******************/
+#define FDCAN_RXF1A_F1AI_Pos         (0U)
+#define FDCAN_RXF1A_F1AI_Msk         (0x3FUL << FDCAN_RXF1A_F1AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI             FDCAN_RXF1A_F1AI_Msk                      /*!<Rx FIFO 1 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXESC register  ******************/
+#define FDCAN_RXESC_F0DS_Pos         (0U)
+#define FDCAN_RXESC_F0DS_Msk         (0x7UL << FDCAN_RXESC_F0DS_Pos)           /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS             FDCAN_RXESC_F0DS_Msk                      /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos         (4U)
+#define FDCAN_RXESC_F1DS_Msk         (0x7UL << FDCAN_RXESC_F1DS_Pos)           /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS             FDCAN_RXESC_F1DS_Msk                      /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos         (8U)
+#define FDCAN_RXESC_RBDS_Msk         (0x7UL << FDCAN_RXESC_RBDS_Pos)           /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS             FDCAN_RXESC_RBDS_Msk                      /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *******************/
+#define FDCAN_TXBC_TBSA_Pos          (2U)
+#define FDCAN_TXBC_TBSA_Msk          (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA              FDCAN_TXBC_TBSA_Msk                       /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos          (16U)
+#define FDCAN_TXBC_NDTB_Msk          (0x3FUL << FDCAN_TXBC_NDTB_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB              FDCAN_TXBC_NDTB_Msk                       /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos          (24U)
+#define FDCAN_TXBC_TFQS_Msk          (0x3FUL << FDCAN_TXBC_TFQS_Pos)           /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS              FDCAN_TXBC_TFQS_Msk                       /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos          (30U)
+#define FDCAN_TXBC_TFQM_Msk          (0x1UL << FDCAN_TXBC_TFQM_Pos)            /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM              FDCAN_TXBC_TFQM_Msk                       /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  ******************/
+#define FDCAN_TXFQS_TFFL_Pos         (0U)
+#define FDCAN_TXFQS_TFFL_Msk         (0x3FUL << FDCAN_TXFQS_TFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL             FDCAN_TXFQS_TFFL_Msk                      /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos         (8U)
+#define FDCAN_TXFQS_TFGI_Msk         (0x1FUL << FDCAN_TXFQS_TFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI             FDCAN_TXFQS_TFGI_Msk                      /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos        (16U)
+#define FDCAN_TXFQS_TFQPI_Msk        (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)         /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI            FDCAN_TXFQS_TFQPI_Msk                     /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos         (21U)
+#define FDCAN_TXFQS_TFQF_Msk         (0x1UL << FDCAN_TXFQS_TFQF_Pos)           /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF             FDCAN_TXFQS_TFQF_Msk                      /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  ******************/
+#define FDCAN_TXESC_TBDS_Pos         (0U)
+#define FDCAN_TXESC_TBDS_Msk         (0x7UL << FDCAN_TXESC_TBDS_Pos)           /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS             FDCAN_TXESC_TBDS_Msk                      /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  ******************/
+#define FDCAN_TXBRP_TRP_Pos          (0U)
+#define FDCAN_TXBRP_TRP_Msk          (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)     /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP              FDCAN_TXBRP_TRP_Msk                       /*!<Transmission Request Pending             */
+
+/*****************  Bit definition for FDCAN_TXBAR register  ******************/
+#define FDCAN_TXBAR_AR_Pos           (0U)
+#define FDCAN_TXBAR_AR_Msk           (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR               FDCAN_TXBAR_AR_Msk                        /*!<Add Request                              */
+
+/*****************  Bit definition for FDCAN_TXBCR register  ******************/
+#define FDCAN_TXBCR_CR_Pos           (0U)
+#define FDCAN_TXBCR_CR_Msk           (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR               FDCAN_TXBCR_CR_Msk                        /*!<Cancellation Request                     */
+
+/*****************  Bit definition for FDCAN_TXBTO register  ******************/
+#define FDCAN_TXBTO_TO_Pos           (0U)
+#define FDCAN_TXBTO_TO_Msk           (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO               FDCAN_TXBTO_TO_Msk                        /*!<Transmission Occurred                    */
+
+/*****************  Bit definition for FDCAN_TXBCF register  ******************/
+#define FDCAN_TXBCF_CF_Pos           (0U)
+#define FDCAN_TXBCF_CF_Msk           (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF               FDCAN_TXBCF_CF_Msk                        /*!<Cancellation Finished                    */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  *****************/
+#define FDCAN_TXBTIE_TIE_Pos         (0U)
+#define FDCAN_TXBTIE_TIE_Msk         (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)    /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE             FDCAN_TXBTIE_TIE_Msk                      /*!<Transmission Interrupt Enable            */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  ****************/
+#define FDCAN_TXBCIE_CFIE_Pos        (0U)
+#define FDCAN_TXBCIE_CFIE_Msk        (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)   /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE            FDCAN_TXBCIE_CFIE_Msk                     /*!<Cancellation Finished Interrupt Enable   */
+
+/*****************  Bit definition for FDCAN_TXEFC register  ******************/
+#define FDCAN_TXEFC_EFSA_Pos         (2U)
+#define FDCAN_TXEFC_EFSA_Msk         (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA             FDCAN_TXEFC_EFSA_Msk                      /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos          (16U)
+#define FDCAN_TXEFC_EFS_Msk          (0x3FUL << FDCAN_TXEFC_EFS_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS              FDCAN_TXEFC_EFS_Msk                       /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos         (24U)
+#define FDCAN_TXEFC_EFWM_Msk         (0x3FUL << FDCAN_TXEFC_EFWM_Pos)          /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM             FDCAN_TXEFC_EFWM_Msk                      /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  ******************/
+#define FDCAN_TXEFS_EFFL_Pos         (0U)
+#define FDCAN_TXEFS_EFFL_Msk         (0x3FUL << FDCAN_TXEFS_EFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL             FDCAN_TXEFS_EFFL_Msk                      /*!<Event FIFO Fill Level                    */
+#define FDCAN_TXEFS_EFGI_Pos         (8U)
+#define FDCAN_TXEFS_EFGI_Msk         (0x1FUL << FDCAN_TXEFS_EFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI             FDCAN_TXEFS_EFGI_Msk                      /*!<Event FIFO Get Index                     */
+#define FDCAN_TXEFS_EFPI_Pos         (16U)
+#define FDCAN_TXEFS_EFPI_Msk         (0x1FUL << FDCAN_TXEFS_EFPI_Pos)          /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI             FDCAN_TXEFS_EFPI_Msk                      /*!<Event FIFO Put Index                     */
+#define FDCAN_TXEFS_EFF_Pos          (24U)
+#define FDCAN_TXEFS_EFF_Msk          (0x1UL << FDCAN_TXEFS_EFF_Pos)            /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF              FDCAN_TXEFS_EFF_Msk                       /*!<Event FIFO Full                          */
+#define FDCAN_TXEFS_TEFL_Pos         (25U)
+#define FDCAN_TXEFS_TEFL_Msk         (0x1UL << FDCAN_TXEFS_TEFL_Pos)           /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL             FDCAN_TXEFS_TEFL_Msk                      /*!<Tx Event FIFO Element Lost               */
+
+/*****************  Bit definition for FDCAN_TXEFA register  ******************/
+#define FDCAN_TXEFA_EFAI_Pos         (0U)
+#define FDCAN_TXEFA_EFAI_Msk         (0x1FUL << FDCAN_TXEFA_EFAI_Pos)          /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI             FDCAN_TXEFA_EFAI_Msk                      /*!<Event FIFO Acknowledge Index             */
+
+/*****************  Bit definition for FDCAN_TTTMC register  ******************/
+#define FDCAN_TTTMC_TMSA_Pos         (2U)
+#define FDCAN_TTTMC_TMSA_Msk         (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA             FDCAN_TTTMC_TMSA_Msk                      /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos          (16U)
+#define FDCAN_TTTMC_TME_Msk          (0x7FUL << FDCAN_TTTMC_TME_Pos)           /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME              FDCAN_TTTMC_TME_Msk                       /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  ******************/
+#define FDCAN_TTRMC_RID_Pos          (0U)
+#define FDCAN_TTRMC_RID_Msk          (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)     /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID              FDCAN_TTRMC_RID_Msk                       /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos          (30U)
+#define FDCAN_TTRMC_XTD_Msk          (0x1UL << FDCAN_TTRMC_XTD_Pos)            /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD              FDCAN_TTRMC_XTD_Msk                       /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos         (31U)
+#define FDCAN_TTRMC_RMPS_Msk         (0x1UL << FDCAN_TTRMC_RMPS_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS             FDCAN_TTRMC_RMPS_Msk                      /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  ******************/
+#define FDCAN_TTOCF_OM_Pos           (0U)
+#define FDCAN_TTOCF_OM_Msk           (0x3UL << FDCAN_TTOCF_OM_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM               FDCAN_TTOCF_OM_Msk                        /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos          (3U)
+#define FDCAN_TTOCF_GEN_Msk          (0x1UL << FDCAN_TTOCF_GEN_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN              FDCAN_TTOCF_GEN_Msk                       /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos           (4U)
+#define FDCAN_TTOCF_TM_Msk           (0x1UL << FDCAN_TTOCF_TM_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM               FDCAN_TTOCF_TM_Msk                        /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos        (5U)
+#define FDCAN_TTOCF_LDSDL_Msk        (0x7UL << FDCAN_TTOCF_LDSDL_Pos)          /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL            FDCAN_TTOCF_LDSDL_Msk                     /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos         (8U)
+#define FDCAN_TTOCF_IRTO_Msk         (0x7FUL << FDCAN_TTOCF_IRTO_Pos)          /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO             FDCAN_TTOCF_IRTO_Msk                      /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos         (15U)
+#define FDCAN_TTOCF_EECS_Msk         (0x1UL << FDCAN_TTOCF_EECS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS             FDCAN_TTOCF_EECS_Msk                      /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos          (16U)
+#define FDCAN_TTOCF_AWL_Msk          (0xFFUL << FDCAN_TTOCF_AWL_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL              FDCAN_TTOCF_AWL_Msk                       /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos         (24U)
+#define FDCAN_TTOCF_EGTF_Msk         (0x1UL << FDCAN_TTOCF_EGTF_Pos)           /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF             FDCAN_TTOCF_EGTF_Msk                      /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos          (25U)
+#define FDCAN_TTOCF_ECC_Msk          (0x1UL << FDCAN_TTOCF_ECC_Pos)            /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC              FDCAN_TTOCF_ECC_Msk                       /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos         (26U)
+#define FDCAN_TTOCF_EVTP_Msk         (0x1UL << FDCAN_TTOCF_EVTP_Pos)           /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP             FDCAN_TTOCF_EVTP_Msk                      /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  ******************/
+#define FDCAN_TTMLM_CCM_Pos          (0U)
+#define FDCAN_TTMLM_CCM_Msk          (0x3FUL << FDCAN_TTMLM_CCM_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM              FDCAN_TTMLM_CCM_Msk                       /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos          (6U)
+#define FDCAN_TTMLM_CSS_Msk          (0x3UL << FDCAN_TTMLM_CSS_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS              FDCAN_TTMLM_CSS_Msk                       /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos         (8U)
+#define FDCAN_TTMLM_TXEW_Msk         (0xFUL << FDCAN_TTMLM_TXEW_Pos)           /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW             FDCAN_TTMLM_TXEW_Msk                      /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos         (16U)
+#define FDCAN_TTMLM_ENTT_Msk         (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)         /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT             FDCAN_TTMLM_ENTT_Msk                      /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  ******************/
+#define FDCAN_TURCF_NCL_Pos          (0U)
+#define FDCAN_TURCF_NCL_Msk          (0xFFFFUL << FDCAN_TURCF_NCL_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL              FDCAN_TURCF_NCL_Msk                       /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos           (16U)
+#define FDCAN_TURCF_DC_Msk           (0x3FFFUL << FDCAN_TURCF_DC_Pos)          /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC               FDCAN_TURCF_DC_Msk                        /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos          (31U)
+#define FDCAN_TURCF_ELT_Msk          (0x1UL << FDCAN_TURCF_ELT_Pos)            /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT              FDCAN_TURCF_ELT_Msk                       /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ******************/
+#define FDCAN_TTOCN_SGT_Pos          (0U)
+#define FDCAN_TTOCN_SGT_Msk          (0x1UL << FDCAN_TTOCN_SGT_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT              FDCAN_TTOCN_SGT_Msk                       /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos          (1U)
+#define FDCAN_TTOCN_ECS_Msk          (0x1UL << FDCAN_TTOCN_ECS_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS              FDCAN_TTOCN_ECS_Msk                       /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos          (2U)
+#define FDCAN_TTOCN_SWP_Msk          (0x1UL << FDCAN_TTOCN_SWP_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP              FDCAN_TTOCN_SWP_Msk                       /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos          (3U)
+#define FDCAN_TTOCN_SWS_Msk          (0x3UL << FDCAN_TTOCN_SWS_Pos)            /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS              FDCAN_TTOCN_SWS_Msk                       /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos         (5U)
+#define FDCAN_TTOCN_RTIE_Msk         (0x1UL << FDCAN_TTOCN_RTIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE             FDCAN_TTOCN_RTIE_Msk                      /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos          (6U)
+#define FDCAN_TTOCN_TMC_Msk          (0x3UL << FDCAN_TTOCN_TMC_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC              FDCAN_TTOCN_TMC_Msk                       /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos         (8U)
+#define FDCAN_TTOCN_TTIE_Msk         (0x1UL << FDCAN_TTOCN_TTIE_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE             FDCAN_TTOCN_TTIE_Msk                      /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos          (9U)
+#define FDCAN_TTOCN_GCS_Msk          (0x1UL << FDCAN_TTOCN_GCS_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS              FDCAN_TTOCN_GCS_Msk                       /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos          (10U)
+#define FDCAN_TTOCN_FGP_Msk          (0x1UL << FDCAN_TTOCN_FGP_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP              FDCAN_TTOCN_FGP_Msk                       /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos          (11U)
+#define FDCAN_TTOCN_TMG_Msk          (0x1UL << FDCAN_TTOCN_TMG_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG              FDCAN_TTOCN_TMG_Msk                       /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos          (12U)
+#define FDCAN_TTOCN_NIG_Msk          (0x1UL << FDCAN_TTOCN_NIG_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG              FDCAN_TTOCN_NIG_Msk                       /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos         (13U)
+#define FDCAN_TTOCN_ESCN_Msk         (0x1UL << FDCAN_TTOCN_ESCN_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN             FDCAN_TTOCN_ESCN_Msk                      /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos         (15U)
+#define FDCAN_TTOCN_LCKC_Msk         (0x1UL << FDCAN_TTOCN_LCKC_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC             FDCAN_TTOCN_LCKC_Msk                      /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ******************/
+#define FDCAN_TTGTP_TP_Pos           (0U)
+#define FDCAN_TTGTP_TP_Msk           (0xFFFFUL << FDCAN_TTGTP_TP_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP               FDCAN_TTGTP_TP_Msk                        /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos          (16U)
+#define FDCAN_TTGTP_CTP_Msk          (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP              FDCAN_TTGTP_CTP_Msk                       /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ******************/
+#define FDCAN_TTTMK_TM_Pos           (0U)
+#define FDCAN_TTTMK_TM_Msk           (0xFFFFUL << FDCAN_TTTMK_TM_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM               FDCAN_TTTMK_TM_Msk                        /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos         (16U)
+#define FDCAN_TTTMK_TICC_Msk         (0x7FUL << FDCAN_TTTMK_TICC_Pos)          /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC             FDCAN_TTTMK_TICC_Msk                      /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos         (31U)
+#define FDCAN_TTTMK_LCKM_Msk         (0x1UL << FDCAN_TTTMK_LCKM_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM             FDCAN_TTTMK_LCKM_Msk                      /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  *******************/
+#define FDCAN_TTIR_SBC_Pos           (0U)
+#define FDCAN_TTIR_SBC_Msk           (0x1UL << FDCAN_TTIR_SBC_Pos)             /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC               FDCAN_TTIR_SBC_Msk                        /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos           (1U)
+#define FDCAN_TTIR_SMC_Msk           (0x1UL << FDCAN_TTIR_SMC_Pos)             /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC               FDCAN_TTIR_SMC_Msk                        /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos           (2U)
+#define FDCAN_TTIR_CSM_Msk           (0x1UL << FDCAN_TTIR_CSM_Pos)             /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM               FDCAN_TTIR_CSM_Msk                        /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos           (3U)
+#define FDCAN_TTIR_SOG_Msk           (0x1UL << FDCAN_TTIR_SOG_Pos)             /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG               FDCAN_TTIR_SOG_Msk                        /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos          (4U)
+#define FDCAN_TTIR_RTMI_Msk          (0x1UL << FDCAN_TTIR_RTMI_Pos)            /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI              FDCAN_TTIR_RTMI_Msk                       /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos          (5U)
+#define FDCAN_TTIR_TTMI_Msk          (0x1UL << FDCAN_TTIR_TTMI_Pos)            /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI              FDCAN_TTIR_TTMI_Msk                       /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos           (6U)
+#define FDCAN_TTIR_SWE_Msk           (0x1UL << FDCAN_TTIR_SWE_Pos)             /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE               FDCAN_TTIR_SWE_Msk                        /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos           (7U)
+#define FDCAN_TTIR_GTW_Msk           (0x1UL << FDCAN_TTIR_GTW_Pos)             /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW               FDCAN_TTIR_GTW_Msk                        /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos           (8U)
+#define FDCAN_TTIR_GTD_Msk           (0x1UL << FDCAN_TTIR_GTD_Pos)             /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD               FDCAN_TTIR_GTD_Msk                        /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos           (9U)
+#define FDCAN_TTIR_GTE_Msk           (0x1UL << FDCAN_TTIR_GTE_Pos)             /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE               FDCAN_TTIR_GTE_Msk                        /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos           (10U)
+#define FDCAN_TTIR_TXU_Msk           (0x1UL << FDCAN_TTIR_TXU_Pos)             /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU               FDCAN_TTIR_TXU_Msk                        /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos           (11U)
+#define FDCAN_TTIR_TXO_Msk           (0x1UL << FDCAN_TTIR_TXO_Pos)             /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO               FDCAN_TTIR_TXO_Msk                        /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos           (12U)
+#define FDCAN_TTIR_SE1_Msk           (0x1UL << FDCAN_TTIR_SE1_Pos)             /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1               FDCAN_TTIR_SE1_Msk                        /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos           (13U)
+#define FDCAN_TTIR_SE2_Msk           (0x1UL << FDCAN_TTIR_SE2_Pos)             /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2               FDCAN_TTIR_SE2_Msk                        /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos           (14U)
+#define FDCAN_TTIR_ELC_Msk           (0x1UL << FDCAN_TTIR_ELC_Pos)             /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC               FDCAN_TTIR_ELC_Msk                        /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos           (15U)
+#define FDCAN_TTIR_IWT_Msk           (0x1UL << FDCAN_TTIR_IWT_Pos)             /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT               FDCAN_TTIR_IWT_Msk                        /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos            (16U)
+#define FDCAN_TTIR_WT_Msk            (0x1UL << FDCAN_TTIR_WT_Pos)              /*!< 0x00010000 */
+#define FDCAN_TTIR_WT                FDCAN_TTIR_WT_Msk                         /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos            (17U)
+#define FDCAN_TTIR_AW_Msk            (0x1UL << FDCAN_TTIR_AW_Pos)              /*!< 0x00020000 */
+#define FDCAN_TTIR_AW                FDCAN_TTIR_AW_Msk                         /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos           (18U)
+#define FDCAN_TTIR_CER_Msk           (0x1UL << FDCAN_TTIR_CER_Pos)             /*!< 0x00040000 */
+#define FDCAN_TTIR_CER               FDCAN_TTIR_CER_Msk                        /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  *******************/
+#define FDCAN_TTIE_SBCE_Pos          (0U)
+#define FDCAN_TTIE_SBCE_Msk          (0x1UL << FDCAN_TTIE_SBCE_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE              FDCAN_TTIE_SBCE_Msk                       /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos          (1U)
+#define FDCAN_TTIE_SMCE_Msk          (0x1UL << FDCAN_TTIE_SMCE_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE              FDCAN_TTIE_SMCE_Msk                       /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos          (2U)
+#define FDCAN_TTIE_CSME_Msk          (0x1UL << FDCAN_TTIE_CSME_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME              FDCAN_TTIE_CSME_Msk                       /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos          (3U)
+#define FDCAN_TTIE_SOGE_Msk          (0x1UL << FDCAN_TTIE_SOGE_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE              FDCAN_TTIE_SOGE_Msk                       /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos         (4U)
+#define FDCAN_TTIE_RTMIE_Msk         (0x1UL << FDCAN_TTIE_RTMIE_Pos)           /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE             FDCAN_TTIE_RTMIE_Msk                      /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos         (5U)
+#define FDCAN_TTIE_TTMIE_Msk         (0x1UL << FDCAN_TTIE_TTMIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE             FDCAN_TTIE_TTMIE_Msk                      /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos          (6U)
+#define FDCAN_TTIE_SWEE_Msk          (0x1UL << FDCAN_TTIE_SWEE_Pos)            /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE              FDCAN_TTIE_SWEE_Msk                       /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos          (7U)
+#define FDCAN_TTIE_GTWE_Msk          (0x1UL << FDCAN_TTIE_GTWE_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE              FDCAN_TTIE_GTWE_Msk                       /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos          (8U)
+#define FDCAN_TTIE_GTDE_Msk          (0x1UL << FDCAN_TTIE_GTDE_Pos)            /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE              FDCAN_TTIE_GTDE_Msk                       /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos          (9U)
+#define FDCAN_TTIE_GTEE_Msk          (0x1UL << FDCAN_TTIE_GTEE_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE              FDCAN_TTIE_GTEE_Msk                       /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos          (10U)
+#define FDCAN_TTIE_TXUE_Msk          (0x1UL << FDCAN_TTIE_TXUE_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE              FDCAN_TTIE_TXUE_Msk                       /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos          (11U)
+#define FDCAN_TTIE_TXOE_Msk          (0x1UL << FDCAN_TTIE_TXOE_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE              FDCAN_TTIE_TXOE_Msk                       /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos          (12U)
+#define FDCAN_TTIE_SE1E_Msk          (0x1UL << FDCAN_TTIE_SE1E_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E              FDCAN_TTIE_SE1E_Msk                       /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos          (13U)
+#define FDCAN_TTIE_SE2E_Msk          (0x1UL << FDCAN_TTIE_SE2E_Pos)            /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E              FDCAN_TTIE_SE2E_Msk                       /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos          (14U)
+#define FDCAN_TTIE_ELCE_Msk          (0x1UL << FDCAN_TTIE_ELCE_Pos)            /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE              FDCAN_TTIE_ELCE_Msk                       /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos          (15U)
+#define FDCAN_TTIE_IWTE_Msk          (0x1UL << FDCAN_TTIE_IWTE_Pos)            /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE              FDCAN_TTIE_IWTE_Msk                       /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos           (16U)
+#define FDCAN_TTIE_WTE_Msk           (0x1UL << FDCAN_TTIE_WTE_Pos)             /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE               FDCAN_TTIE_WTE_Msk                        /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos           (17U)
+#define FDCAN_TTIE_AWE_Msk           (0x1UL << FDCAN_TTIE_AWE_Pos)             /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE               FDCAN_TTIE_AWE_Msk                        /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos          (18U)
+#define FDCAN_TTIE_CERE_Msk          (0x1UL << FDCAN_TTIE_CERE_Pos)            /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE              FDCAN_TTIE_CERE_Msk                       /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ******************/
+#define FDCAN_TTILS_SBCS_Pos         (0U)
+#define FDCAN_TTILS_SBCS_Msk         (0x1UL << FDCAN_TTILS_SBCS_Pos)           /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS             FDCAN_TTILS_SBCS_Msk                      /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos         (1U)
+#define FDCAN_TTILS_SMCS_Msk         (0x1UL << FDCAN_TTILS_SMCS_Pos)           /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS             FDCAN_TTILS_SMCS_Msk                      /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos         (2U)
+#define FDCAN_TTILS_CSMS_Msk         (0x1UL << FDCAN_TTILS_CSMS_Pos)           /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS             FDCAN_TTILS_CSMS_Msk                      /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos         (3U)
+#define FDCAN_TTILS_SOGS_Msk         (0x1UL << FDCAN_TTILS_SOGS_Pos)           /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS             FDCAN_TTILS_SOGS_Msk                      /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos        (4U)
+#define FDCAN_TTILS_RTMIS_Msk        (0x1UL << FDCAN_TTILS_RTMIS_Pos)          /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS            FDCAN_TTILS_RTMIS_Msk                     /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos        (5U)
+#define FDCAN_TTILS_TTMIS_Msk        (0x1UL << FDCAN_TTILS_TTMIS_Pos)          /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS            FDCAN_TTILS_TTMIS_Msk                     /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos         (6U)
+#define FDCAN_TTILS_SWES_Msk         (0x1UL << FDCAN_TTILS_SWES_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES             FDCAN_TTILS_SWES_Msk                      /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos         (7U)
+#define FDCAN_TTILS_GTWS_Msk         (0x1UL << FDCAN_TTILS_GTWS_Pos)           /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS             FDCAN_TTILS_GTWS_Msk                      /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos         (8U)
+#define FDCAN_TTILS_GTDS_Msk         (0x1UL << FDCAN_TTILS_GTDS_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS             FDCAN_TTILS_GTDS_Msk                      /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos         (9U)
+#define FDCAN_TTILS_GTES_Msk         (0x1UL << FDCAN_TTILS_GTES_Pos)           /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES             FDCAN_TTILS_GTES_Msk                      /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos         (10U)
+#define FDCAN_TTILS_TXUS_Msk         (0x1UL << FDCAN_TTILS_TXUS_Pos)           /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS             FDCAN_TTILS_TXUS_Msk                      /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos         (11U)
+#define FDCAN_TTILS_TXOS_Msk         (0x1UL << FDCAN_TTILS_TXOS_Pos)           /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS             FDCAN_TTILS_TXOS_Msk                      /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos         (12U)
+#define FDCAN_TTILS_SE1S_Msk         (0x1UL << FDCAN_TTILS_SE1S_Pos)           /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S             FDCAN_TTILS_SE1S_Msk                      /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos         (13U)
+#define FDCAN_TTILS_SE2S_Msk         (0x1UL << FDCAN_TTILS_SE2S_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S             FDCAN_TTILS_SE2S_Msk                      /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos         (14U)
+#define FDCAN_TTILS_ELCS_Msk         (0x1UL << FDCAN_TTILS_ELCS_Pos)           /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS             FDCAN_TTILS_ELCS_Msk                      /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos         (15U)
+#define FDCAN_TTILS_IWTS_Msk         (0x1UL << FDCAN_TTILS_IWTS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS             FDCAN_TTILS_IWTS_Msk                      /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos          (16U)
+#define FDCAN_TTILS_WTS_Msk          (0x1UL << FDCAN_TTILS_WTS_Pos)            /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS              FDCAN_TTILS_WTS_Msk                       /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos          (17U)
+#define FDCAN_TTILS_AWS_Msk          (0x1UL << FDCAN_TTILS_AWS_Pos)            /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS              FDCAN_TTILS_AWS_Msk                       /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos         (18U)
+#define FDCAN_TTILS_CERS_Msk         (0x1UL << FDCAN_TTILS_CERS_Pos)           /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS             FDCAN_TTILS_CERS_Msk                      /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ******************/
+#define FDCAN_TTOST_EL_Pos           (0U)
+#define FDCAN_TTOST_EL_Msk           (0x3UL << FDCAN_TTOST_EL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOST_EL               FDCAN_TTOST_EL_Msk                        /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos           (2U)
+#define FDCAN_TTOST_MS_Msk           (0x3UL << FDCAN_TTOST_MS_Pos)             /*!< 0x0000000C */
+#define FDCAN_TTOST_MS               FDCAN_TTOST_MS_Msk                        /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos          (4U)
+#define FDCAN_TTOST_SYS_Msk          (0x3UL << FDCAN_TTOST_SYS_Pos)            /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS              FDCAN_TTOST_SYS_Msk                       /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos         (6U)
+#define FDCAN_TTOST_QGTP_Msk         (0x1UL << FDCAN_TTOST_QGTP_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP             FDCAN_TTOST_QGTP_Msk                      /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos          (7U)
+#define FDCAN_TTOST_QCS_Msk          (0x1UL << FDCAN_TTOST_QCS_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS              FDCAN_TTOST_QCS_Msk                       /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos          (8U)
+#define FDCAN_TTOST_RTO_Msk          (0xFFUL << FDCAN_TTOST_RTO_Pos)           /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO              FDCAN_TTOST_RTO_Msk                       /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos         (22U)
+#define FDCAN_TTOST_WGTD_Msk         (0x1UL << FDCAN_TTOST_WGTD_Pos)           /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD             FDCAN_TTOST_WGTD_Msk                      /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos          (23U)
+#define FDCAN_TTOST_GFI_Msk          (0x1UL << FDCAN_TTOST_GFI_Pos)            /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI              FDCAN_TTOST_GFI_Msk                       /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos          (24U)
+#define FDCAN_TTOST_TMP_Msk          (0x7UL << FDCAN_TTOST_TMP_Pos)            /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP              FDCAN_TTOST_TMP_Msk                       /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos          (27U)
+#define FDCAN_TTOST_GSI_Msk          (0x1UL << FDCAN_TTOST_GSI_Pos)            /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI              FDCAN_TTOST_GSI_Msk                       /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos          (28U)
+#define FDCAN_TTOST_WFE_Msk          (0x1UL << FDCAN_TTOST_WFE_Pos)            /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE              FDCAN_TTOST_WFE_Msk                       /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos          (29U)
+#define FDCAN_TTOST_AWE_Msk          (0x1UL << FDCAN_TTOST_AWE_Pos)            /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE              FDCAN_TTOST_AWE_Msk                       /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos         (30U)
+#define FDCAN_TTOST_WECS_Msk         (0x1UL << FDCAN_TTOST_WECS_Pos)           /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS             FDCAN_TTOST_WECS_Msk                      /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos          (31U)
+#define FDCAN_TTOST_SPL_Msk          (0x1UL << FDCAN_TTOST_SPL_Pos)            /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL              FDCAN_TTOST_SPL_Msk                       /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ******************/
+#define FDCAN_TURNA_NAV_Pos          (0U)
+#define FDCAN_TURNA_NAV_Msk          (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)        /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV              FDCAN_TURNA_NAV_Msk                       /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ******************/
+#define FDCAN_TTLGT_LT_Pos           (0U)
+#define FDCAN_TTLGT_LT_Msk           (0xFFFFUL << FDCAN_TTLGT_LT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT               FDCAN_TTLGT_LT_Msk                        /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos           (16U)
+#define FDCAN_TTLGT_GT_Msk           (0xFFFFUL << FDCAN_TTLGT_GT_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT               FDCAN_TTLGT_GT_Msk                        /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ******************/
+#define FDCAN_TTCTC_CT_Pos           (0U)
+#define FDCAN_TTCTC_CT_Msk           (0xFFFFUL << FDCAN_TTCTC_CT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT               FDCAN_TTCTC_CT_Msk                        /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos           (16U)
+#define FDCAN_TTCTC_CC_Msk           (0x3FUL << FDCAN_TTCTC_CC_Pos)            /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC               FDCAN_TTCTC_CC_Msk                        /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ******************/
+#define FDCAN_TTCPT_CCV_Pos          (0U)
+#define FDCAN_TTCPT_CCV_Msk          (0x3FUL << FDCAN_TTCPT_CCV_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV              FDCAN_TTCPT_CCV_Msk                       /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos          (16U)
+#define FDCAN_TTCPT_SWV_Msk          (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV              FDCAN_TTCPT_SWV_Msk                       /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ******************/
+#define FDCAN_TTCSM_CSM_Pos          (0U)
+#define FDCAN_TTCSM_CSM_Msk          (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM              FDCAN_TTCSM_CSM_Msk                       /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *******************/
+#define FDCAN_TTTS_SWTSEL_Pos        (0U)
+#define FDCAN_TTTS_SWTSEL_Msk        (0x3UL << FDCAN_TTTS_SWTSEL_Pos)          /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL            FDCAN_TTTS_SWTSEL_Msk                     /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos        (4U)
+#define FDCAN_TTTS_EVTSEL_Msk        (0x3UL << FDCAN_TTTS_EVTSEL_Pos)          /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL            FDCAN_TTTS_EVTSEL_Msk                     /*!<Event trigger input selection            */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FDCANCCU (Clock Calibration unit)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ****************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ****************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  ***************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ****************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *****************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *****************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  **********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!< Memory bank enable bit */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!< Address/data multiplexing enable bit */
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!< Memory type */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!< Memory data bus width */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!< Flash access enable */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!< Burst enable bit */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!< Wait signal polarity bit */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!< Wait timing configuration */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!< Write enable bit */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!< Wait enable bit */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!< Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!< Wait signal during asynchronous transfers */
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!< CRAM page size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!< Write burst enable */
+#define FMC_BCRx_CSCOUNT_Pos       (20U)
+#define FMC_BCRx_CSCOUNT_Msk       (0x3UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00300000 */
+#define FMC_BCRx_CSCOUNT           FMC_BCRx_CSCOUNT_Msk                        /*!< Chip Select (CS) counter */
+#define FMC_BCRx_CSCOUNT_0         (0x1UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00100000 */
+#define FMC_BCRx_CSCOUNT_1         (0x2UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00200000 */
+#define FMC_BCRx_NBLSET_Pos        (22U)
+#define FMC_BCRx_NBLSET_Msk        (0x3UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00C00000 */
+#define FMC_BCRx_NBLSET            FMC_BCRx_NBLSET_Msk                         /*!< Byte lane (NBL) setup */
+#define FMC_BCRx_NBLSET_0          (0x1UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00400000 */
+#define FMC_BCRx_NBLSET_1          (0x2UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00800000 */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  **********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!< Address setup phase duration */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!< Address-hold phase duration */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!< Data-phase duration */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!< Bus turnaround phase duration */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!< Clock divide ratio */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!< Data latency for synchronous memory */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!< Access mode */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+#define FMC_BTRx_DATAHLD_Pos       (30U)
+#define FMC_BTRx_DATAHLD_Msk       (0x3UL << FMC_BTRx_DATAHLD_Pos)              /*!< 0xC0000000 */
+#define FMC_BTRx_DATAHLD           FMC_BTRx_DATAHLD_Msk                        /*!< Data Hold phase duration */
+#define FMC_BTRx_DATAHLD_0         (0x1UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x40000000 */
+#define FMC_BTRx_DATAHLD_1         (0x2UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_CFGR register  *****************/
+#define FMC_CFGR_CLKDIV_Pos        (16U)
+#define FMC_CFGR_CLKDIV_Msk        (0xFUL << FMC_CFGR_CLKDIV_Pos)               /*!< 0x000F0000 */
+#define FMC_CFGR_CLKDIV            FMC_CFGR_CLKDIV_Msk                         /*!< Clock divide ratio (for FMC_CLK signal) */
+#define FMC_CFGR_CLKDIV_0          (0x1UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00010000 */
+#define FMC_CFGR_CLKDIV_1          (0x2UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00020000 */
+#define FMC_CFGR_CLKDIV_2          (0x4UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00040000 */
+#define FMC_CFGR_CLKDIV_3          (0x8UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00080000 */
+#define FMC_CFGR_CCLKEN_Pos        (20U)
+#define FMC_CFGR_CCLKEN_Msk        (0x1UL << FMC_CFGR_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_CFGR_CCLKEN            FMC_CFGR_CCLKEN_Msk                         /*!< Continuous clock enable */
+#define FMC_CFGR_BMAP_Pos          (24U)
+#define FMC_CFGR_BMAP_Msk          (0x3UL << FMC_CFGR_BMAP_Pos)                 /*!< 0x03000000 */
+#define FMC_CFGR_BMAP              FMC_CFGR_BMAP_Msk                           /*!< FMC memory region mapping */
+#define FMC_CFGR_BMAP_0            (0x1UL << FMC_CFGR_BMAP_Pos)                /*!< 0x01000000 */
+#define FMC_CFGR_BMAP_1            (0x2UL << FMC_CFGR_BMAP_Pos)                /*!< 0x02000000 */
+#define FMC_CFGR_FMCEN_Pos         (31U)
+#define FMC_CFGR_FMCEN_Msk         (0x1UL << FMC_CFGR_FMCEN_Pos)                /*!< 0x80000000 */
+#define FMC_CFGR_FMCEN             FMC_CFGR_FMCEN_Msk                          /*!< FMC controller enable */
+
+/******************  Bit definition for FMC_PCR register  *********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!< Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!< NAND Flash memory bank enable bit */
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!< Data bus width */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!< ECC computation logic enable bit */
+#define FMC_PCR_ECCALG_Pos         (8U)
+#define FMC_PCR_ECCALG_Msk         (0x1UL << FMC_PCR_ECCALG_Pos)               /*!< 0x00000100 */
+#define FMC_PCR_ECCALG             FMC_PCR_ECCALG_Msk                          /*!< ECC algorithm */
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!< CLE to RE delay */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!< ALE to RE delay */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
+#define FMC_PCR_ECCSS_Pos          (17U)
+#define FMC_PCR_ECCSS_Msk          (0x7UL << FMC_PCR_ECCSS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCSS              FMC_PCR_ECCSS_Msk                           /*!< ECC page size */
+#define FMC_PCR_ECCSS_0            (0x1UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00020000 */
+#define FMC_PCR_ECCSS_1            (0x2UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00040000 */
+#define FMC_PCR_ECCSS_2            (0x4UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00080000 */
+#define FMC_PCR_BCHECC_Pos         (24U)
+#define FMC_PCR_BCHECC_Msk         (0x1UL << FMC_PCR_BCHECC_Pos)                /*!< 0x01000000 */
+#define FMC_PCR_BCHECC             FMC_PCR_BCHECC_Msk                          /*!< BCH error correction capability */
+#define FMC_PCR_WEN_Pos            (25U)
+#define FMC_PCR_WEN_Msk            (0x1UL << FMC_PCR_WEN_Pos)                   /*!< 0x02000000 */
+#define FMC_PCR_WEN                FMC_PCR_WEN_Msk                             /*!< Write enable */
+
+/******************  Bit definition for FMC_SR register  ******************/
+#define FMC_SR_ISOST_Pos           (0U)
+#define FMC_SR_ISOST_Msk           (0x3UL << FMC_SR_ISOST_Pos)                  /*!< 0x00000003 */
+#define FMC_SR_ISOST               FMC_SR_ISOST_Msk                            /*!< FMC isolation state with respect to the AXI interface */
+#define FMC_SR_PEF_Pos             (4U)
+#define FMC_SR_PEF_Msk             (0x1UL << FMC_SR_PEF_Pos)                    /*!< 0x00000010 */
+#define FMC_SR_PEF                 FMC_SR_PEF_Msk                              /*!< Pipe Empty Flag */
+#define FMC_SR_NWRF_Pos            (6U)
+#define FMC_SR_NWRF_Msk            (0x1UL << FMC_SR_NWRF_Pos)                   /*!< 0x00000040 */
+#define FMC_SR_NWRF                FMC_SR_NWRF_Msk                             /*!< NAND write request flag */
+
+/******************  Bit definition for FMC_PMEM register  ********************/
+#define FMC_PMEM_MEMSET_Pos        (0U)
+#define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!< Common memory setup time */
+#define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+#define FMC_PMEM_MEMWAIT_Pos       (8U)
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!< Common memory wait time */
+#define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PMEM_MEMHOLD_Pos       (16U)
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!< Common memory hold time */
+#define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PMEM_MEMHIZ_Pos        (24U)
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!< Common memory databus Hi-Z time */
+#define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ********************/
+#define FMC_PATT_ATTSET_Pos        (0U)
+#define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!< Attribute memory setup time */
+#define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+#define FMC_PATT_ATTWAIT_Pos       (8U)
+#define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!< Attribute memory wait time */
+#define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PATT_ATTHOLD_Pos       (16U)
+#define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!< Attribute memory hold time */
+#define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PATT_ATTHIZ_Pos        (24U)
+#define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!< Attribute memory data bus Hi-Z time */
+#define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_HPR register  ******************/
+#define FMC_HPR_HPR_Pos            (0U)
+#define FMC_HPR_HPR_Msk            (0xFFFFFFFFUL << FMC_HPR_HPR_Pos)            /*!< 0xFFFFFFFF */
+#define FMC_HPR_HPR                FMC_HPR_HPR_Msk                             /*!< Hamming parity result */
+
+/****************  Bit definition for FMC_HECCR register  *****************/
+#define FMC_HECCR_HECC_Pos         (0U)
+#define FMC_HECCR_HECC_Msk         (0xFFFFFFFFUL << FMC_HECCR_HECC_Pos)         /*!< 0xFFFFFFFF */
+#define FMC_HECCR_HECC             FMC_HECCR_HECC_Msk                          /*!< ECC result */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!< Address setup phase duration */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!< Address-hold phase duration */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!< Data-phase duration */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!< Bus turnaround phase duration */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!< Access mode */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
+#define FMC_BWTRx_DATAHLD_Pos      (30U)
+#define FMC_BWTRx_DATAHLD_Msk      (0x3UL << FMC_BWTRx_DATAHLD_Pos)             /*!< 0xC0000000 */
+#define FMC_BWTRx_DATAHLD          FMC_BWTRx_DATAHLD_Msk                       /*!< Data Hold phase duration */
+#define FMC_BWTRx_DATAHLD_0        (0x1UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x40000000 */
+#define FMC_BWTRx_DATAHLD_1        (0x2UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!< Number of column address bits */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000002 */
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!< Number of row address bits */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000008 */
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!< Memory data bus width */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000020 */
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!< Number of internal banks */
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!< CAS latency */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!< Write protection */
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!< SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000800 */
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!< Read pipe */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00004000 */
+#define FMC_SDCRx_SDEN_Pos         (16U)
+#define FMC_SDCRx_SDEN_Msk         (0x1UL << FMC_SDCRx_SDEN_Pos)               /*!< 0x00010000 */
+#define FMC_SDCRx_SDEN             FMC_SDCRx_SDEN_Msk                          /*!< SDRAM device enable */
+#define FMC_SDCRx_SDINIT_Pos       (17U)
+#define FMC_SDCRx_SDINIT_Msk       (0x1UL << FMC_SDCRx_SDINIT_Pos)             /*!< 0x00020000 */
+#define FMC_SDCRx_SDINIT           FMC_SDCRx_SDINIT_Msk                        /*!< SDRAM device initialization */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  **************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!< Load mode register to active */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000008 */
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<Exit self-refresh delay */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000080 */
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!< Self refresh time */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000800 */
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!< Row cycle delay */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00004000 */
+#define FMC_SDTRx_TRC_3            (0x8UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00008000 */
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!< Recovery delay */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00040000 */
+#define FMC_SDTRx_TWR_3            (0x8UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00080000 */
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!< Row precharge delay */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00400000 */
+#define FMC_SDTRx_TRP_3            (0x8UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00800000 */
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!< Row to column delay */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x04000000 */
+#define FMC_SDTRx_TRCD_3           (0x8UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x08000000 */
+
+/******************  Bit definition for FMC_SDCMR register  *******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!< Command mode */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
+#define FMC_SDCMR_DS2_Pos          (3U)
+#define FMC_SDCMR_DS2_Msk          (0x1UL << FMC_SDCMR_DS2_Pos)                /*!< 0x00000008 */
+#define FMC_SDCMR_DS2              FMC_SDCMR_DS2_Msk                           /*!< Command targeting SDRAM device 2 */
+#define FMC_SDCMR_DS1_Pos          (4U)
+#define FMC_SDCMR_DS1_Msk          (0x1UL << FMC_SDCMR_DS1_Pos)                /*!< 0x00000010 */
+#define FMC_SDCMR_DS1              FMC_SDCMR_DS1_Msk                           /*!< Command targeting SDRAM device 1 */
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!< Number of auto-refresh */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x3FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x007FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!< Mode register definition */
+
+/******************  Bit definition for FMC_SDRTR register  *******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!< Clear refresh error flag */
+#define FMC_SDRTR_RFSCNT_Pos       (1U)
+#define FMC_SDRTR_RFSCNT_Msk       (0x1FFFUL << FMC_SDRTR_RFSCNT_Pos)          /*!< 0x00003FFE */
+#define FMC_SDRTR_RFSCNT           FMC_SDRTR_RFSCNT_Msk                        /*!< Refresh timer count */
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!< RES interrupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ********************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!< Refresh error flag */
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!< Status mode for bank 1 */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!< Status mode for bank 2 */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
+#define FMC_SDSR_CMDOK_Pos         (15U)
+#define FMC_SDSR_CMDOK_Msk         (0x1UL << FMC_SDSR_CMDOK_Pos)               /*!< 0x00004000 */
+#define FMC_SDSR_CMDOK             FMC_SDSR_CMDOK_Msk                          /*!< Previous command status */
+
+/*******************  Bit definition for FMC_IER register  ********************/
+#define FMC_IER_IREE_Pos              (0U)
+#define FMC_IER_IREE_Msk              (0x1UL << FMC_IER_IREE_Pos)               /*!< 0x00000001 */
+#define FMC_IER_IREE                  FMC_IER_IREE_Msk                         /*!< Interrupt rising edge detection enable bit */
+#define FMC_IER_IHLE_Pos              (1U)
+#define FMC_IER_IHLE_Msk              (0x1UL << FMC_IER_IHLE_Pos)               /*!< 0x00000002 */
+#define FMC_IER_IHLE                  FMC_IER_IHLE_Msk                         /*!< Interrupt high-level detection enable bit */
+#define FMC_IER_IFEE_Pos              (2U)
+#define FMC_IER_IFEE_Msk              (0x1UL << FMC_IER_IFEE_Pos)               /*!< 0x00000004 */
+#define FMC_IER_IFEE                  FMC_IER_IFEE_Msk                         /*!< Interrupt falling edge detection enable bit */
+
+/*******************  Bit definition for FMC_ISR register  ********************/
+#define FMC_ISR_IREF_Pos              (0U)
+#define FMC_ISR_IREF_Msk              (0x1UL << FMC_ISR_IREF_Pos)               /*!< 0x00000001 */
+#define FMC_ISR_IREF                  FMC_ISR_IREF_Msk                         /*!< Interrupt rising edge flag */
+#define FMC_ISR_IHLF_Pos              (1U)
+#define FMC_ISR_IHLF_Msk              (0x1UL << FMC_ISR_IHLF_Pos)               /*!< 0x00000002 */
+#define FMC_ISR_IHLF                  FMC_ISR_IHLF_Msk                         /*!< Interrupt high-level flag */
+#define FMC_ISR_IFEF_Pos              (2U)
+#define FMC_ISR_IFEF_Msk              (0x1UL << FMC_ISR_IFEF_Pos)               /*!< 0x00000004 */
+#define FMC_ISR_IFEF                  FMC_ISR_IFEF_Msk                         /*!< Interrupt falling edge flag */
+
+/*******************  Bit definition for FMC_ICR register  ********************/
+#define FMC_ICR_CIREF_Pos             (0U)
+#define FMC_ICR_CIREF_Msk             (0x1UL << FMC_ICR_CIREF_Pos)              /*!< 0x00000001 */
+#define FMC_ICR_CIREF                 FMC_ICR_CIREF_Msk                        /*!< Clear Interrupt rising edge flag */
+#define FMC_ICR_CIHLF_Pos             (1U)
+#define FMC_ICR_CIHLF_Msk             (0x1UL << FMC_ICR_CIHLF_Pos)              /*!< 0x00000002 */
+#define FMC_ICR_CIHLF                 FMC_ICR_CIHLF_Msk                        /*!< Clear Interrupt high-level flag */
+#define FMC_ICR_CIFEF_Pos             (2U)
+#define FMC_ICR_CIFEF_Msk             (0x1UL << FMC_ICR_CIFEF_Pos)              /*!< 0x00000004 */
+#define FMC_ICR_CIFEF                 FMC_ICR_CIFEF_Msk                        /*!< Clear Interrupt falling edge flag */
+
+/****************  Bit definition for FMC_CSQCR register  *****************/
+#define FMC_CSQCR_CSQSTART_Pos        (0U)
+#define FMC_CSQCR_CSQSTART_Msk        (0x1UL << FMC_CSQCR_CSQSTART_Pos)         /*!< 0x00000001 */
+#define FMC_CSQCR_CSQSTART            FMC_CSQCR_CSQSTART_Msk                   /*!< Command Sequencer Enable */
+
+/***************  Bit definition for FMC_CSQCFGR1 register  ***************/
+#define FMC_CSQCFGR1_CMD2EN_Pos       (1U)
+#define FMC_CSQCFGR1_CMD2EN_Msk       (0x1UL << FMC_CSQCFGR1_CMD2EN_Pos)        /*!< 0x00000002 */
+#define FMC_CSQCFGR1_CMD2EN           FMC_CSQCFGR1_CMD2EN_Msk                  /*!< Command cycle 2 Enable */
+#define FMC_CSQCFGR1_DMADEN_Pos       (2U)
+#define FMC_CSQCFGR1_DMADEN_Msk       (0x1UL << FMC_CSQCFGR1_DMADEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR1_DMADEN           FMC_CSQCFGR1_DMADEN_Msk                  /*!< Command sequencer DMA request data enable */
+#define FMC_CSQCFGR1_ACYNBR_Pos       (4U)
+#define FMC_CSQCFGR1_ACYNBR_Msk       (0x7UL << FMC_CSQCFGR1_ACYNBR_Pos)        /*!< 0x00000070 */
+#define FMC_CSQCFGR1_ACYNBR           FMC_CSQCFGR1_ACYNBR_Msk                  /*!< Address Cycle number */
+#define FMC_CSQCFGR1_CMD1_Pos         (8U)
+#define FMC_CSQCFGR1_CMD1_Msk         (0xFFUL << FMC_CSQCFGR1_CMD1_Pos)         /*!< 0x0000FF00 */
+#define FMC_CSQCFGR1_CMD1             FMC_CSQCFGR1_CMD1_Msk                    /*!< Command 1 sequencer */
+#define FMC_CSQCFGR1_CMD2_Pos         (16U)
+#define FMC_CSQCFGR1_CMD2_Msk         (0xFFUL << FMC_CSQCFGR1_CMD2_Pos)         /*!< 0x00FF0000 */
+#define FMC_CSQCFGR1_CMD2             FMC_CSQCFGR1_CMD2_Msk                    /*!< Command 2 sequencer */
+#define FMC_CSQCFGR1_CMD1T_Pos        (24U)
+#define FMC_CSQCFGR1_CMD1T_Msk        (0x1UL << FMC_CSQCFGR1_CMD1T_Pos)         /*!< 0x01000000 */
+#define FMC_CSQCFGR1_CMD1T            FMC_CSQCFGR1_CMD1T_Msk                   /*!< Command 1 Sequencer timings */
+#define FMC_CSQCFGR1_CMD2T_Pos        (25U)
+#define FMC_CSQCFGR1_CMD2T_Msk        (0x1UL << FMC_CSQCFGR1_CMD2T_Pos)         /*!< 0x02000000 */
+#define FMC_CSQCFGR1_CMD2T            FMC_CSQCFGR1_CMD2T_Msk                   /*!< Command 2 Sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR2 register  ***************/
+#define FMC_CSQCFGR2_SQSDTEN_Pos      (0U)
+#define FMC_CSQCFGR2_SQSDTEN_Msk      (0x1UL << FMC_CSQCFGR2_SQSDTEN_Pos)       /*!< 0x00000001 */
+#define FMC_CSQCFGR2_SQSDTEN          FMC_CSQCFGR2_SQSDTEN_Msk                 /*!< Sequencer spare data transfer enable */
+#define FMC_CSQCFGR2_RCMD2EN_Pos      (1U)
+#define FMC_CSQCFGR2_RCMD2EN_Msk      (0x1UL << FMC_CSQCFGR2_RCMD2EN_Pos)       /*!< 0x00000002 */
+#define FMC_CSQCFGR2_RCMD2EN          FMC_CSQCFGR2_RCMD2EN_Msk                 /*!< Random Command 2 sequencer enable */
+#define FMC_CSQCFGR2_DMASEN_Pos       (2U)
+#define FMC_CSQCFGR2_DMASEN_Msk       (0x1UL << FMC_CSQCFGR2_DMASEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR2_DMASEN           FMC_CSQCFGR2_DMASEN_Msk                  /*!< Command sequencer DMA request decoding status enable */
+#define FMC_CSQCFGR2_RCMD1_Pos        (8U)
+#define FMC_CSQCFGR2_RCMD1_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD1_Pos)        /*!< 0x0000FF00 */
+#define FMC_CSQCFGR2_RCMD1            FMC_CSQCFGR2_RCMD1_Msk                   /*!< Random Command 1 sequencer */
+#define FMC_CSQCFGR2_RCMD2_Pos        (16U)
+#define FMC_CSQCFGR2_RCMD2_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD2_Pos)        /*!< 0x00FF0000 */
+#define FMC_CSQCFGR2_RCMD2            FMC_CSQCFGR2_RCMD2_Msk                   /*!< Random Command 2 sequencer */
+#define FMC_CSQCFGR2_RCMD1T_Pos       (24U)
+#define FMC_CSQCFGR2_RCMD1T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD1T_Pos)        /*!< 0x01000000 */
+#define FMC_CSQCFGR2_RCMD1T           FMC_CSQCFGR2_RCMD1T_Msk                  /*!< Command 1 sequencer timings */
+#define FMC_CSQCFGR2_RCMD2T_Pos       (25U)
+#define FMC_CSQCFGR2_RCMD2T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD2T_Pos)        /*!< 0x02000000 */
+#define FMC_CSQCFGR2_RCMD2T           FMC_CSQCFGR2_RCMD2T_Msk                  /*!< Command 1 sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR3 register  ***************/
+#define FMC_CSQCFGR3_SNBR_Pos         (8U)
+#define FMC_CSQCFGR3_SNBR_Msk         (0x3FUL << FMC_CSQCFGR3_SNBR_Pos)         /*!< 0x00003F00 */
+#define FMC_CSQCFGR3_SNBR             FMC_CSQCFGR3_SNBR_Msk                    /*!< Number of sectors to be read/written */
+#define FMC_CSQCFGR3_AC1T_Pos         (16U)
+#define FMC_CSQCFGR3_AC1T_Msk         (0x1UL << FMC_CSQCFGR3_AC1T_Pos)          /*!< 0x00010000 */
+#define FMC_CSQCFGR3_AC1T             FMC_CSQCFGR3_AC1T_Msk                    /*!< Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_AC2T_Pos         (17U)
+#define FMC_CSQCFGR3_AC2T_Msk         (0x1UL << FMC_CSQCFGR3_AC2T_Pos)          /*!< 0x00020000 */
+#define FMC_CSQCFGR3_AC2T             FMC_CSQCFGR3_AC2T_Msk                    /*!< Address cycle 2 sequencer timings */
+#define FMC_CSQCFGR3_AC3T_Pos         (18U)
+#define FMC_CSQCFGR3_AC3T_Msk         (0x1UL << FMC_CSQCFGR3_AC3T_Pos)          /*!< 0x00040000 */
+#define FMC_CSQCFGR3_AC3T             FMC_CSQCFGR3_AC3T_Msk                    /*!< Address cycle 3 sequencer timings */
+#define FMC_CSQCFGR3_AC4T_Pos         (19U)
+#define FMC_CSQCFGR3_AC4T_Msk         (0x1UL << FMC_CSQCFGR3_AC4T_Pos)          /*!< 0x00080000 */
+#define FMC_CSQCFGR3_AC4T             FMC_CSQCFGR3_AC4T_Msk                    /*!< Address cycle 4sequencer timings */
+#define FMC_CSQCFGR3_AC5T_Pos         (20U)
+#define FMC_CSQCFGR3_AC5T_Msk         (0x1UL << FMC_CSQCFGR3_AC5T_Pos)          /*!< 0x00100000 */
+#define FMC_CSQCFGR3_AC5T             FMC_CSQCFGR3_AC5T_Msk                    /*!< Address cycle 5 sequencer timings */
+#define FMC_CSQCFGR3_SDT_Pos          (21U)
+#define FMC_CSQCFGR3_SDT_Msk          (0x1UL << FMC_CSQCFGR3_SDT_Pos)           /*!< 0x00200000 */
+#define FMC_CSQCFGR3_SDT              FMC_CSQCFGR3_SDT_Msk                     /*!< Spare data transfer sequencer timings */
+#define FMC_CSQCFGR3_RAC1T_Pos        (22U)
+#define FMC_CSQCFGR3_RAC1T_Msk        (0x1UL << FMC_CSQCFGR3_RAC1T_Pos)         /*!< 0x00400000 */
+#define FMC_CSQCFGR3_RAC1T            FMC_CSQCFGR3_RAC1T_Msk                   /*!< Random Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_RAC2T_Pos        (23U)
+#define FMC_CSQCFGR3_RAC2T_Msk        (0x1UL << FMC_CSQCFGR3_RAC2T_Pos)         /*!< 0x00800000 */
+#define FMC_CSQCFGR3_RAC2T            FMC_CSQCFGR3_RAC2T_Msk                   /*!< Random Address cycle 2 sequencer timings */
+
+/****************  Bit definition for FMC_CSQAR1 register  ****************/
+#define FMC_CSQAR1_ADDC1_Pos          (0U)
+#define FMC_CSQAR1_ADDC1_Msk          (0xFFUL << FMC_CSQAR1_ADDC1_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR1_ADDC1              FMC_CSQAR1_ADDC1_Msk                     /*!< Address Cycle 1 */
+#define FMC_CSQAR1_ADDC2_Pos          (8U)
+#define FMC_CSQAR1_ADDC2_Msk          (0xFFUL << FMC_CSQAR1_ADDC2_Pos)          /*!< 0x0000FF00 */
+#define FMC_CSQAR1_ADDC2              FMC_CSQAR1_ADDC2_Msk                     /*!< Address Cycle 2 */
+#define FMC_CSQAR1_ADDC3_Pos          (16U)
+#define FMC_CSQAR1_ADDC3_Msk          (0xFFUL << FMC_CSQAR1_ADDC3_Pos)          /*!< 0x00FF0000 */
+#define FMC_CSQAR1_ADDC3              FMC_CSQAR1_ADDC3_Msk                     /*!< Address Cycle 3 */
+#define FMC_CSQAR1_ADDC4_Pos          (24U)
+#define FMC_CSQAR1_ADDC4_Msk          (0xFFUL << FMC_CSQAR1_ADDC4_Pos)          /*!< 0xFF000000 */
+#define FMC_CSQAR1_ADDC4              FMC_CSQAR1_ADDC4_Msk                     /*!< Address Cycle 4 */
+
+/****************  Bit definition for FMC_CSQAR2 register  ****************/
+#define FMC_CSQAR2_ADDC5_Pos          (0U)
+#define FMC_CSQAR2_ADDC5_Msk          (0xFFUL << FMC_CSQAR2_ADDC5_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR2_ADDC5              FMC_CSQAR2_ADDC5_Msk                     /*!< Address Cycle 5 */
+#define FMC_CSQAR2_SAO_Pos            (16U)
+#define FMC_CSQAR2_SAO_Msk            (0xFFFFUL << FMC_CSQAR2_SAO_Pos)          /*!< 0xFFFF0000 */
+#define FMC_CSQAR2_SAO                FMC_CSQAR2_SAO_Msk                       /*!< Spare Area Address Offset. */
+
+/****************  Bit definition for FMC_CSQIER register  ****************/
+#define FMC_CSQIER_TCIE_Pos           (0U)
+#define FMC_CSQIER_TCIE_Msk           (0x1UL << FMC_CSQIER_TCIE_Pos)            /*!< 0x00000001 */
+#define FMC_CSQIER_TCIE               FMC_CSQIER_TCIE_Msk                      /*!< Transfer Complete Interrupt enable */
+#define FMC_CSQIER_SCIE_Pos           (1U)
+#define FMC_CSQIER_SCIE_Msk           (0x1UL << FMC_CSQIER_SCIE_Pos)            /*!< 0x00000002 */
+#define FMC_CSQIER_SCIE               FMC_CSQIER_SCIE_Msk                      /*!< Sector Complete interrupt enable */
+#define FMC_CSQIER_SEIE_Pos           (2U)
+#define FMC_CSQIER_SEIE_Msk           (0x1UL << FMC_CSQIER_SEIE_Pos)            /*!< 0x00000004 */
+#define FMC_CSQIER_SEIE               FMC_CSQIER_SEIE_Msk                      /*!< Sector Error interrupt enable */
+#define FMC_CSQIER_SUEIE_Pos          (3U)
+#define FMC_CSQIER_SUEIE_Msk          (0x1UL << FMC_CSQIER_SUEIE_Pos)           /*!< 0x00000008 */
+#define FMC_CSQIER_SUEIE              FMC_CSQIER_SUEIE_Msk                     /*!< Sector Uncorrectable Error interrupt enable */
+#define FMC_CSQIER_CMDTCIE_Pos        (4U)
+#define FMC_CSQIER_CMDTCIE_Msk        (0x1UL << FMC_CSQIER_CMDTCIE_Pos)         /*!< 0x00000010 */
+#define FMC_CSQIER_CMDTCIE            FMC_CSQIER_CMDTCIE_Msk                   /*!< Command Transfer Complete interrupt enable */
+
+/****************  Bit definition for FMC_CSQISR register  ****************/
+#define FMC_CSQISR_TCF_Pos            (0U)
+#define FMC_CSQISR_TCF_Msk            (0x1UL << FMC_CSQISR_TCF_Pos)             /*!< 0x00000001 */
+#define FMC_CSQISR_TCF                FMC_CSQISR_TCF_Msk                       /*!< Transfer Complete flag */
+#define FMC_CSQISR_SCF_Pos            (1U)
+#define FMC_CSQISR_SCF_Msk            (0x1UL << FMC_CSQISR_SCF_Pos)             /*!< 0x00000002 */
+#define FMC_CSQISR_SCF                FMC_CSQISR_SCF_Msk                       /*!< Sector Complete flag */
+#define FMC_CSQISR_SEF_Pos            (2U)
+#define FMC_CSQISR_SEF_Msk            (0x1UL << FMC_CSQISR_SEF_Pos)             /*!< 0x00000004 */
+#define FMC_CSQISR_SEF                FMC_CSQISR_SEF_Msk                       /*!< Sector Error flag */
+#define FMC_CSQISR_SUEF_Pos           (3U)
+#define FMC_CSQISR_SUEF_Msk           (0x1UL << FMC_CSQISR_SUEF_Pos)            /*!< 0x00000008 */
+#define FMC_CSQISR_SUEF               FMC_CSQISR_SUEF_Msk                      /*!< Sector Uncorrectable Error flag */
+#define FMC_CSQISR_CMDTCF_Pos         (4U)
+#define FMC_CSQISR_CMDTCF_Msk         (0x1UL << FMC_CSQISR_CMDTCF_Pos)          /*!< 0x00000010 */
+#define FMC_CSQISR_CMDTCF             FMC_CSQISR_CMDTCF_Msk                    /*!< Command Transfer Complete flag */
+
+/****************  Bit definition for FMC_CSQICR register  ****************/
+#define FMC_CSQICR_CTCF_Pos           (0U)
+#define FMC_CSQICR_CTCF_Msk           (0x1UL << FMC_CSQICR_CTCF_Pos)            /*!< 0x00000001 */
+#define FMC_CSQICR_CTCF               FMC_CSQICR_CTCF_Msk                      /*!< Clear Transfer Complete flag */
+#define FMC_CSQICR_CSCF_Pos           (1U)
+#define FMC_CSQICR_CSCF_Msk           (0x1UL << FMC_CSQICR_CSCF_Pos)            /*!< 0x00000002 */
+#define FMC_CSQICR_CSCF               FMC_CSQICR_CSCF_Msk                      /*!< Clear Sector Complete flag */
+#define FMC_CSQICR_CSEF_Pos           (2U)
+#define FMC_CSQICR_CSEF_Msk           (0x1UL << FMC_CSQICR_CSEF_Pos)            /*!< 0x00000004 */
+#define FMC_CSQICR_CSEF               FMC_CSQICR_CSEF_Msk                      /*!< Clear Sector Error flag */
+#define FMC_CSQICR_CSUEF_Pos          (3U)
+#define FMC_CSQICR_CSUEF_Msk          (0x1UL << FMC_CSQICR_CSUEF_Pos)           /*!< 0x00000008 */
+#define FMC_CSQICR_CSUEF              FMC_CSQICR_CSUEF_Msk                     /*!< Clear Sector uncorrectable Error flag */
+#define FMC_CSQICR_CCMDTCF_Pos        (4U)
+#define FMC_CSQICR_CCMDTCF_Msk        (0x1UL << FMC_CSQICR_CCMDTCF_Pos)         /*!< 0x00000010 */
+#define FMC_CSQICR_CCMDTCF            FMC_CSQICR_CCMDTCF_Msk                   /*!< Clear Command Transfer Complete flag */
+
+/***************  Bit definition for FMC_CSQEMSR register  ****************/
+#define FMC_CSQEMSR_SEM_Pos           (0U)
+#define FMC_CSQEMSR_SEM_Msk           (0xFFFFUL << FMC_CSQEMSR_SEM_Pos)         /*!< 0x0000FFFF */
+#define FMC_CSQEMSR_SEM               FMC_CSQEMSR_SEM_Msk                      /*!< Sector Error mapping */
+
+/****************  Bit definition for FMC_BCHIER register  ****************/
+#define FMC_BCHIER_DUEIE_Pos          (0U)
+#define FMC_BCHIER_DUEIE_Msk          (0x1UL << FMC_BCHIER_DUEIE_Pos)           /*!< 0x00000001 */
+#define FMC_BCHIER_DUEIE              FMC_BCHIER_DUEIE_Msk                     /*!< Decoder Uncorrectable Errors Interrupt enable */
+#define FMC_BCHIER_DERIE_Pos          (1U)
+#define FMC_BCHIER_DERIE_Msk          (0x1UL << FMC_BCHIER_DERIE_Pos)           /*!< 0x00000002 */
+#define FMC_BCHIER_DERIE              FMC_BCHIER_DERIE_Msk                     /*!< Decoder Error Ready Interrupt enable */
+#define FMC_BCHIER_DEFIE_Pos          (2U)
+#define FMC_BCHIER_DEFIE_Msk          (0x1UL << FMC_BCHIER_DEFIE_Pos)           /*!< 0x00000004 */
+#define FMC_BCHIER_DEFIE              FMC_BCHIER_DEFIE_Msk                     /*!< Decoder Error Found Interrupt enable */
+#define FMC_BCHIER_DSRIE_Pos          (3U)
+#define FMC_BCHIER_DSRIE_Msk          (0x1UL << FMC_BCHIER_DSRIE_Pos)           /*!< 0x00000008 */
+#define FMC_BCHIER_DSRIE              FMC_BCHIER_DSRIE_Msk                     /*!< Decoder Syndrome Ready Interrupt enable */
+#define FMC_BCHIER_EPBRIE_Pos         (4U)
+#define FMC_BCHIER_EPBRIE_Msk         (0x1UL << FMC_BCHIER_EPBRIE_Pos)          /*!< 0x00000010 */
+#define FMC_BCHIER_EPBRIE             FMC_BCHIER_EPBRIE_Msk                    /*!< Decoder Parity Bits Ready Interrupt enable */
+
+/****************  Bit definition for FMC_BCHISR register  ****************/
+#define FMC_BCHISR_DUEF_Pos           (0U)
+#define FMC_BCHISR_DUEF_Msk           (0x1UL << FMC_BCHISR_DUEF_Pos)            /*!< 0x00000001 */
+#define FMC_BCHISR_DUEF               FMC_BCHISR_DUEF_Msk                      /*!< Decoder Uncorrectable Errors flag */
+#define FMC_BCHISR_DERF_Pos           (1U)
+#define FMC_BCHISR_DERF_Msk           (0x1UL << FMC_BCHISR_DERF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHISR_DERF               FMC_BCHISR_DERF_Msk                      /*!< Decoder Error Ready flag */
+#define FMC_BCHISR_DEFF_Pos           (2U)
+#define FMC_BCHISR_DEFF_Msk           (0x1UL << FMC_BCHISR_DEFF_Pos)            /*!< 0x00000004 */
+#define FMC_BCHISR_DEFF               FMC_BCHISR_DEFF_Msk                      /*!< Decoder Error Found flag */
+#define FMC_BCHISR_DSRF_Pos           (3U)
+#define FMC_BCHISR_DSRF_Msk           (0x1UL << FMC_BCHISR_DSRF_Pos)            /*!< 0x00000008 */
+#define FMC_BCHISR_DSRF               FMC_BCHISR_DSRF_Msk                      /*!< Decoder Syndrome Ready flag */
+#define FMC_BCHISR_EPBRF_Pos          (4U)
+#define FMC_BCHISR_EPBRF_Msk          (0x1UL << FMC_BCHISR_EPBRF_Pos)           /*!< 0x00000010 */
+#define FMC_BCHISR_EPBRF              FMC_BCHISR_EPBRF_Msk                     /*!< Encoder Parity Bits Ready flag */
+
+/****************  Bit definition for FMC_BCHICR register  ****************/
+#define FMC_BCHICR_CDUEF_Pos          (0U)
+#define FMC_BCHICR_CDUEF_Msk          (0x1UL << FMC_BCHICR_CDUEF_Pos)           /*!< 0x00000001 */
+#define FMC_BCHICR_CDUEF              FMC_BCHICR_CDUEF_Msk                     /*!< Clear Decoder Uncorrectable Error flag */
+#define FMC_BCHICR_CDERF_Pos          (1U)
+#define FMC_BCHICR_CDERF_Msk          (0x1UL << FMC_BCHICR_CDERF_Pos)           /*!< 0x00000002 */
+#define FMC_BCHICR_CDERF              FMC_BCHICR_CDERF_Msk                     /*!< Clear Decoder Error ready flag */
+#define FMC_BCHICR_CDEFF_Pos          (2U)
+#define FMC_BCHICR_CDEFF_Msk          (0x1UL << FMC_BCHICR_CDEFF_Pos)           /*!< 0x00000004 */
+#define FMC_BCHICR_CDEFF              FMC_BCHICR_CDEFF_Msk                     /*!< Clear Decoder Error Found flag */
+#define FMC_BCHICR_CDSRF_Pos          (3U)
+#define FMC_BCHICR_CDSRF_Msk          (0x1UL << FMC_BCHICR_CDSRF_Pos)           /*!< 0x00000008 */
+#define FMC_BCHICR_CDSRF              FMC_BCHICR_CDSRF_Msk                     /*!< Clear Decoder Syndrome Ready flag */
+#define FMC_BCHICR_CEPBRF_Pos         (4U)
+#define FMC_BCHICR_CEPBRF_Msk         (0x1UL << FMC_BCHICR_CEPBRF_Pos)          /*!< 0x00000010 */
+#define FMC_BCHICR_CEPBRF             FMC_BCHICR_CEPBRF_Msk                    /*!< Clear Encoder Parity Bits Ready flag */
+
+/***************  Bit definition for FMC_BCHPBR1 register  ****************/
+#define FMC_BCHPBR1_BCHPB_Pos         (0U)
+#define FMC_BCHPBR1_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR1_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR1_BCHPB             FMC_BCHPBR1_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR2 register  ****************/
+#define FMC_BCHPBR2_BCHPB_Pos         (0U)
+#define FMC_BCHPBR2_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR2_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR2_BCHPB             FMC_BCHPBR2_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR3 register  ****************/
+#define FMC_BCHPBR3_BCHPB_Pos         (0U)
+#define FMC_BCHPBR3_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR3_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR3_BCHPB             FMC_BCHPBR3_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR4 register  ****************/
+#define FMC_BCHPBR4_BCHPB_Pos         (0U)
+#define FMC_BCHPBR4_BCHPB_Msk         (0xFFUL << FMC_BCHPBR4_BCHPB_Pos)         /*!< 0x000000FF */
+#define FMC_BCHPBR4_BCHPB             FMC_BCHPBR4_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHDSR0 register  ****************/
+#define FMC_BCHDSR0_DUE_Pos           (0U)
+#define FMC_BCHDSR0_DUE_Msk           (0x1UL << FMC_BCHDSR0_DUE_Pos)            /*!< 0x00000001 */
+#define FMC_BCHDSR0_DUE               FMC_BCHDSR0_DUE_Msk                      /*!< Decoder uncorrectable error */
+#define FMC_BCHDSR0_DEF_Pos           (1U)
+#define FMC_BCHDSR0_DEF_Msk           (0x1UL << FMC_BCHDSR0_DEF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHDSR0_DEF               FMC_BCHDSR0_DEF_Msk                      /*!< Decoder error found */
+#define FMC_BCHDSR0_DEN_Pos           (4U)
+#define FMC_BCHDSR0_DEN_Msk           (0xFUL << FMC_BCHDSR0_DEN_Pos)            /*!< 0x000000F0 */
+#define FMC_BCHDSR0_DEN               FMC_BCHDSR0_DEN_Msk                      /*!< Decoder error number */
+
+/***************  Bit definition for FMC_BCHDSR1 register  ****************/
+#define FMC_BCHDSR1_EBP1_Pos          (0U)
+#define FMC_BCHDSR1_EBP1_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP1_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR1_EBP1              FMC_BCHDSR1_EBP1_Msk                     /*!< Error bit position for error number 1 */
+#define FMC_BCHDSR1_EBP2_Pos          (16U)
+#define FMC_BCHDSR1_EBP2_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP2_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR1_EBP2              FMC_BCHDSR1_EBP2_Msk                     /*!< Error bit position for error number 2 */
+
+/***************  Bit definition for FMC_BCHDSR2 register  ****************/
+#define FMC_BCHDSR2_EBP3_Pos          (0U)
+#define FMC_BCHDSR2_EBP3_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP3_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR2_EBP3              FMC_BCHDSR2_EBP3_Msk                     /*!< Error bit position for error number 3 */
+#define FMC_BCHDSR2_EBP4_Pos          (16U)
+#define FMC_BCHDSR2_EBP4_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP4_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR2_EBP4              FMC_BCHDSR2_EBP4_Msk                     /*!< Error bit position for error number 4 */
+
+/***************  Bit definition for FMC_BCHDSR3 register  ****************/
+#define FMC_BCHDSR3_EBP5_Pos          (0U)
+#define FMC_BCHDSR3_EBP5_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP5_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR3_EBP5              FMC_BCHDSR3_EBP5_Msk                     /*!< Error bit position for error number 5 */
+#define FMC_BCHDSR3_EBP6_Pos          (16U)
+#define FMC_BCHDSR3_EBP6_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP6_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR3_EBP6              FMC_BCHDSR3_EBP6_Msk                     /*!< Error bit position for error number 6 */
+
+/***************  Bit definition for FMC_BCHDSR4 register  ****************/
+#define FMC_BCHDSR4_EBP7_Pos          (0U)
+#define FMC_BCHDSR4_EBP7_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP7_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR4_EBP7              FMC_BCHDSR4_EBP7_Msk                     /*!< Error bit position for error number 7 */
+#define FMC_BCHDSR4_EBP8_Pos          (16U)
+#define FMC_BCHDSR4_EBP8_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP8_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR4_EBP8              FMC_BCHDSR4_EBP8_Msk                     /*!< Error bit position for error number 8 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic MMU (GFXMMU)                                 */
+/*                                                                            */
+/******************************************************************************/
+/****************** Bits definition for GFXMMU_CR register ********************/
+#define GFXMMU_CR_B0OIE_Pos                (0U)
+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)      /*!< 0x00000001 */
+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */
+#define GFXMMU_CR_B1OIE_Pos                (1U)
+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)      /*!< 0x00000002 */
+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */
+#define GFXMMU_CR_B2OIE_Pos                (2U)
+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)      /*!< 0x00000004 */
+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */
+#define GFXMMU_CR_B3OIE_Pos                (3U)
+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)      /*!< 0x00000008 */
+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */
+#define GFXMMU_CR_AMEIE_Pos                (4U)
+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)      /*!< 0x00000010 */
+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */
+#define GFXMMU_CR_BS_Pos                   (6U)
+#define GFXMMU_CR_BS_Msk                   (0x1UL << GFXMMU_CR_BS_Pos)         /*!< 0x00000040 */
+#define GFXMMU_CR_BS                       GFXMMU_CR_BS_Msk                    /*!< Block size */
+#define GFXMMU_CR_ATE_Pos                  (15U)
+#define GFXMMU_CR_ATE_Msk                  (0x1UL << GFXMMU_CR_ATE_Pos)        /*!< 0x00008000 */
+#define GFXMMU_CR_ATE                      GFXMMU_CR_ATE_Msk                   /*!< Address translation enable */
+#define GFXMMU_CR_B0PE_Pos                 (24U)
+#define GFXMMU_CR_B0PE_Msk                 (0x1UL << GFXMMU_CR_B0PE_Pos)       /*!< 0x01000000 */
+#define GFXMMU_CR_B0PE                     GFXMMU_CR_B0PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B0PM_Pos                 (25U)
+#define GFXMMU_CR_B0PM_Msk                 (0x1UL << GFXMMU_CR_B0PM_Pos)       /*!< 0x02000000 */
+#define GFXMMU_CR_B0PM                     GFXMMU_CR_B0PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B1PE_Pos                 (26U)
+#define GFXMMU_CR_B1PE_Msk                 (0x1UL << GFXMMU_CR_B1PE_Pos)       /*!< 0x04000000 */
+#define GFXMMU_CR_B1PE                     GFXMMU_CR_B1PE_Msk                  /*!< Buffer 1 packing enable */
+#define GFXMMU_CR_B1PM_Pos                 (27U)
+#define GFXMMU_CR_B1PM_Msk                 (0x1UL << GFXMMU_CR_B1PM_Pos)       /*!< 0x08000000 */
+#define GFXMMU_CR_B1PM                     GFXMMU_CR_B1PM_Msk                  /*!< Buffer 1 packing mode */
+#define GFXMMU_CR_B2PE_Pos                 (28U)
+#define GFXMMU_CR_B2PE_Msk                 (0x1UL << GFXMMU_CR_B2PE_Pos)       /*!< 0x10000000 */
+#define GFXMMU_CR_B2PE                     GFXMMU_CR_B2PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B2PM_Pos                 (29U)
+#define GFXMMU_CR_B2PM_Msk                 (0x1UL << GFXMMU_CR_B2PM_Pos)       /*!< 0x20000000 */
+#define GFXMMU_CR_B2PM                     GFXMMU_CR_B2PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B3PE_Pos                 (30U)
+#define GFXMMU_CR_B3PE_Msk                 (0x1UL << GFXMMU_CR_B3PE_Pos)       /*!< 0x40000000 */
+#define GFXMMU_CR_B3PE                     GFXMMU_CR_B3PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B3PM_Pos                 (31U)
+#define GFXMMU_CR_B3PM_Msk                 (0x1UL << GFXMMU_CR_B3PM_Pos)       /*!< 0x80000000 */
+#define GFXMMU_CR_B3PM                     GFXMMU_CR_B3PM_Msk                  /*!< Buffer 0 packing mode */
+
+/****************** Bits definition for GFXMMU_SR register ********************/
+#define GFXMMU_SR_B0OF_Pos                 (0U)
+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)       /*!< 0x00000001 */
+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */
+#define GFXMMU_SR_B1OF_Pos                 (1U)
+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)       /*!< 0x00000002 */
+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */
+#define GFXMMU_SR_B2OF_Pos                 (2U)
+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)       /*!< 0x00000004 */
+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */
+#define GFXMMU_SR_B3OF_Pos                 (3U)
+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)       /*!< 0x00000008 */
+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */
+#define GFXMMU_SR_AMEF_Pos                 (4U)
+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)       /*!< 0x00000010 */
+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AXI master error flag */
+
+/****************** Bits definition for GFXMMU_FCR register *******************/
+#define GFXMMU_FCR_CB0OF_Pos               (0U)
+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)     /*!< 0x00000001 */
+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */
+#define GFXMMU_FCR_CB1OF_Pos               (1U)
+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)     /*!< 0x00000002 */
+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */
+#define GFXMMU_FCR_CB2OF_Pos               (2U)
+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)     /*!< 0x00000004 */
+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */
+#define GFXMMU_FCR_CB3OF_Pos               (3U)
+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)     /*!< 0x00000008 */
+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */
+#define GFXMMU_FCR_CAMEF_Pos               (4U)
+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)     /*!< 0x00000010 */
+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */
+
+/****************** Bits definition for GFXMMU_DVR register *******************/
+#define GFXMMU_DVR_DV_Pos                  (0U)
+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */
+
+/****************** Bits definition for GFXMMU_DAR register *******************/
+#define GFXMMU_DAR_DA_Pos                  (0U)
+#define GFXMMU_DAR_DA_Msk                  (0xFFUL << GFXMMU_DVR_DA_Pos)       /*!< 0x000000FF */
+#define GFXMMU_DAR_DA                      GFXMMU_DVR_DA_Msk                   /*!< DA[7:0] bits (Default alpha) */
+
+/****************** Bits definition for GFXMMU_B0CR register ******************/
+#define GFXMMU_B0CR_PBO_Pos                (4U)
+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B0CR_PBBA_Pos               (23U)
+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B1CR register ******************/
+#define GFXMMU_B1CR_PBO_Pos                (4U)
+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B1CR_PBBA_Pos               (23U)
+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B2CR register ******************/
+#define GFXMMU_B2CR_PBO_Pos                (4U)
+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B2CR_PBBA_Pos               (23U)
+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B3CR register ******************/
+#define GFXMMU_B3CR_PBO_Pos                (4U)
+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B3CR_PBBA_Pos               (23U)
+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_LUTxL register *****************/
+#define GFXMMU_LUTxL_EN_Pos                (0U)
+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)      /*!< 0x00000001 */
+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */
+#define GFXMMU_LUTxL_FVB_Pos               (8U)
+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)    /*!< 0x0000FF00 */
+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */
+#define GFXMMU_LUTxL_LVB_Pos               (16U)
+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)    /*!< 0x00FF0000 */
+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */
+
+/****************** Bits definition for GFXMMU_LUTxH register *****************/
+#define GFXMMU_LUTxH_LO_Pos                (0U)
+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)  /*!< 0x0003FFFF */
+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[17:0] bits (Line offset) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic Timer (GFXTIM)                               */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CR_TES_Pos              (0U)
+#define GFXTIM_CR_TES_Msk              (0x3UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000003 */
+#define GFXTIM_CR_TES                  GFXTIM_CR_TES_Msk
+#define GFXTIM_CR_TES_0                (0x1UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000001 */
+#define GFXTIM_CR_TES_1                (0x2UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000002 */
+
+#define GFXTIM_CR_TEPOL_Pos            (4U)
+#define GFXTIM_CR_TEPOL_Msk            (0x1UL << GFXTIM_CR_TEPOL_Pos)          /*!< 0x00000010 */
+#define GFXTIM_CR_TEPOL                GFXTIM_CR_TEPOL_Msk
+
+#define GFXTIM_CR_SYNCS_Pos            (8U)
+#define GFXTIM_CR_SYNCS_Msk            (0x3UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000300 */
+#define GFXTIM_CR_SYNCS                GFXTIM_CR_SYNCS_Msk
+#define GFXTIM_CR_SYNCS_0              (0x1UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000100 */
+#define GFXTIM_CR_SYNCS_1              (0x2UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000200 */
+
+#define GFXTIM_CR_FCCOE_Pos            (16U)
+#define GFXTIM_CR_FCCOE_Msk            (0x1UL << GFXTIM_CR_FCCOE_Pos)          /*!< 0x00010000 */
+#define GFXTIM_CR_FCCOE                GFXTIM_CR_FCCOE_Msk
+
+#define GFXTIM_CR_LCCOE_Pos            (17U)
+#define GFXTIM_CR_LCCOE_Msk            (0x1UL << GFXTIM_CR_LCCOE_Pos)          /*!< 0x00020000 */
+#define GFXTIM_CR_LCCOE                GFXTIM_CR_LCCOE_Msk
+
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CGCR_LCS_Pos           (0U)
+#define GFXTIM_CGCR_LCS_Msk           (0x7UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_LCS               GFXTIM_CGCR_LCS_Msk
+#define GFXTIM_CGCR_LCS_0             (0x1UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000001 */
+#define GFXTIM_CGCR_LCS_1             (0x2UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000002 */
+#define GFXTIM_CGCR_LCS_2             (0x4UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000004 */
+
+#define GFXTIM_CGCR_LCCCS_Pos         (4U)
+#define GFXTIM_CGCR_LCCCS_Msk         (0x1UL << GFXTIM_CGCR_LCCCS_Pos)         /*!< 0x00000010 */
+#define GFXTIM_CGCR_LCCCS             GFXTIM_CGCR_LCCCS_Msk
+
+#define GFXTIM_CGCR_LCCFR_Pos         (8U)
+#define GFXTIM_CGCR_LCCFR_Msk         (0x1UL << GFXTIM_CGCR_LCCFR_Pos)         /*!< 0x00000100 */
+#define GFXTIM_CGCR_LCCFR             GFXTIM_CGCR_LCCFR_Msk
+
+#define GFXTIM_CGCR_LCCHRS_Pos        (12U)
+#define GFXTIM_CGCR_LCCHRS_Msk        (0x7UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00007000 */
+#define GFXTIM_CGCR_LCCHRS            GFXTIM_CGCR_LCCHRS_Msk
+#define GFXTIM_CGCR_LCCHRS_0          (0x1UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00001000 */
+#define GFXTIM_CGCR_LCCHRS_1          (0x2UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00002000 */
+#define GFXTIM_CGCR_LCCHRS_2          (0x4UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCS_Pos           (16U)
+#define GFXTIM_CGCR_FCS_Msk           (0x7UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_FCS               GFXTIM_CGCR_FCS_Msk
+#define GFXTIM_CGCR_FCS_0             (0x1UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00001000 */
+#define GFXTIM_CGCR_FCS_1             (0x2UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00002000 */
+#define GFXTIM_CGCR_FCS_2             (0x4UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCCCS_Pos         (20U)
+#define GFXTIM_CGCR_FCCCS_Msk         (0x7UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00070000 */
+#define GFXTIM_CGCR_FCCCS             GFXTIM_CGCR_FCCCS_Msk
+#define GFXTIM_CGCR_FCCCS_0           (0x1UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00010000 */
+#define GFXTIM_CGCR_FCCCS_1           (0x2UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00020000 */
+#define GFXTIM_CGCR_FCCCS_2           (0x4UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_CGCR_FCCFR_Pos         (24U)
+#define GFXTIM_CGCR_FCCFR_Msk         (0x1UL << GFXTIM_CGCR_FCCFR_Pos)         /*!< 0x00100000 */
+#define GFXTIM_CGCR_FCCFR             GFXTIM_CGCR_FCCFR_Msk
+
+#define GFXTIM_CGCR_FCCHRS_Pos        (28U)
+#define GFXTIM_CGCR_FCCHRS_Msk        (0x7UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x70000000 */
+#define GFXTIM_CGCR_FCCHRS            GFXTIM_CGCR_FCCHRS_Msk
+#define GFXTIM_CGCR_FCCHRS_0          (0x1UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x10000000 */
+#define GFXTIM_CGCR_FCCHRS_1          (0x2UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x20000000 */
+#define GFXTIM_CGCR_FCCHRS_2          (0x4UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_TCR register  *****************/
+#define GFXTIM_TCR_AFCEN_Pos           (0U)
+#define GFXTIM_TCR_AFCEN_Msk           (0x1UL << GFXTIM_TCR_AFCEN_Pos)         /*!< 0x00000001 */
+#define GFXTIM_TCR_AFCEN               GFXTIM_TCR_AFCEN_Msk
+
+#define GFXTIM_TCR_FAFCR_Pos           (1U)
+#define GFXTIM_TCR_FAFCR_Msk           (0x1UL << GFXTIM_TCR_FAFCR_Pos)         /*!< 0x00000002 */
+#define GFXTIM_TCR_FAFCR               GFXTIM_TCR_FAFCR_Msk
+
+#define GFXTIM_TCR_ALCEN_Pos           (4U)
+#define GFXTIM_TCR_ALCEN_Msk           (0x1UL << GFXTIM_TCR_ALCEN_Pos)         /*!< 0x00000010 */
+#define GFXTIM_TCR_ALCEN               GFXTIM_TCR_ALCEN_Msk
+
+#define GFXTIM_TCR_FALCR_Pos           (5U)
+#define GFXTIM_TCR_FALCR_Msk           (0x1UL << GFXTIM_TCR_FALCR_Pos)         /*!< 0x00000020 */
+#define GFXTIM_TCR_FALCR               GFXTIM_TCR_FALCR_Msk
+
+#define GFXTIM_TCR_RFC1EN_Pos          (16U)
+#define GFXTIM_TCR_RFC1EN_Msk          (0x1UL << GFXTIM_TCR_RFC1EN_Pos)        /*!< 0x00010000 */
+#define GFXTIM_TCR_RFC1EN              GFXTIM_TCR_RFC1EN_Msk
+
+#define GFXTIM_TCR_RFC1CM_Pos          (17U)
+#define GFXTIM_TCR_RFC1CM_Msk          (0x1UL << GFXTIM_TCR_RFC1CM_Pos)        /*!< 0x00020000 */
+#define GFXTIM_TCR_RFC1CM              GFXTIM_TCR_RFC1CM_Msk
+
+#define GFXTIM_TCR_FRFC1R_Pos          (18U)
+#define GFXTIM_TCR_FRFC1R_Msk          (0x1UL << GFXTIM_TCR_FRFC1R_Pos)        /*!< 0x00040000 */
+#define GFXTIM_TCR_FRFC1R              GFXTIM_TCR_FRFC1R_Msk
+
+#define GFXTIM_TCR_RFC2EN_Pos          (20U)
+#define GFXTIM_TCR_RFC2EN_Msk          (0x1UL << GFXTIM_TCR_RFC2EN_Pos)        /*!< 0x00100000 */
+#define GFXTIM_TCR_RFC2EN              GFXTIM_TCR_RFC2EN_Msk
+
+#define GFXTIM_TCR_RFC2CM_Pos          (21U)
+#define GFXTIM_TCR_RFC2CM_Msk          (0x1UL << GFXTIM_TCR_RFC2CM_Pos)        /*!< 0x00200000 */
+#define GFXTIM_TCR_RFC2CM              GFXTIM_TCR_RFC2CM_Msk
+
+#define GFXTIM_TCR_FRFC2R_Pos          (22U)
+#define GFXTIM_TCR_FRFC2R_Msk          (0x1UL << GFXTIM_TCR_FRFC2R_Pos)        /*!< 0x00400000 */
+#define GFXTIM_TCR_FRFC2R              GFXTIM_TCR_FRFC2R_Msk
+
+/******************  Bits definition for GFXTIM_TDR register  *****************/
+#define GFXTIM_TDR_AFCDIS_Pos          (0U)
+#define GFXTIM_TDR_AFCDIS_Msk          (0x1UL << GFXTIM_TDR_AFCDIS_Pos)        /*!< 0x00000001 */
+#define GFXTIM_TDR_AFCDIS              GFXTIM_TDR_AFCDIS_Msk
+
+#define GFXTIM_TDR_ALCDIS_Pos          (4U)
+#define GFXTIM_TDR_ALCDIS_Msk          (0x1UL << GFXTIM_TDR_ALCDIS_Pos)        /*!< 0x00000010 */
+#define GFXTIM_TDR_ALCDIS              GFXTIM_TDR_ALCDIS_Msk
+
+#define GFXTIM_TDR_RFC1DIS_Pos         (16U)
+#define GFXTIM_TDR_RFC1DIS_Msk         (0x1UL << GFXTIM_TDR_RFC1DIS_Pos)       /*!< 0x00010000 */
+#define GFXTIM_TDR_RFC1DIS             GFXTIM_TDR_RFC1DIS_Msk
+
+#define GFXTIM_TDR_RFC2DIS_Pos         (20U)
+#define GFXTIM_TDR_RFC2DIS_Msk         (0x1UL << GFXTIM_TDR_RFC2DIS_Pos)       /*!< 0x00100000 */
+#define GFXTIM_TDR_RFC2DIS             GFXTIM_TDR_RFC2DIS_Msk
+
+/******************  Bits definition for GFXTIM_EVCR register  ****************/
+#define GFXTIM_EVCR_EV1EN_Pos          (0U)
+#define GFXTIM_EVCR_EV1EN_Msk          (0x1UL << GFXTIM_EVCR_EV1EN_Pos)        /*!< 0x00000001 */
+#define GFXTIM_EVCR_EV1EN              GFXTIM_EVCR_EV1EN_Msk
+
+#define GFXTIM_EVCR_EV2EN_Pos          (1U)
+#define GFXTIM_EVCR_EV2EN_Msk          (0x1UL << GFXTIM_EVCR_EV2EN_Pos)        /*!< 0x00000002 */
+#define GFXTIM_EVCR_EV2EN              GFXTIM_EVCR_EV2EN_Msk
+
+#define GFXTIM_EVCR_EV3EN_Pos          (2U)
+#define GFXTIM_EVCR_EV3EN_Msk          (0x1UL << GFXTIM_EVCR_EV3EN_Pos)        /*!< 0x00000004 */
+#define GFXTIM_EVCR_EV3EN              GFXTIM_EVCR_EV3EN_Msk
+
+#define GFXTIM_EVCR_EV4EN_Pos          (3U)
+#define GFXTIM_EVCR_EV4EN_Msk          (0x1UL << GFXTIM_EVCR_EV4EN_Pos)        /*!< 0x00000008 */
+#define GFXTIM_EVCR_EV4EN              GFXTIM_EVCR_EV4EN_Msk
+
+/******************  Bits definition for GFXTIM_EVSR register  ****************/
+#define GFXTIM_EVSR_LES1_Pos           (0U)
+#define GFXTIM_EVSR_LES1_Msk           (0x7UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000007 */
+#define GFXTIM_EVSR_LES1               GFXTIM_EVSR_LES1_Msk
+#define GFXTIM_EVSR_LES1_0             (0x1UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000001 */
+#define GFXTIM_EVSR_LES1_1             (0x2UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000002 */
+#define GFXTIM_EVSR_LES1_2             (0x4UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000004 */
+
+#define GFXTIM_EVSR_FES1_Pos           (4U)
+#define GFXTIM_EVSR_FES1_Msk           (0x7UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000070 */
+#define GFXTIM_EVSR_FES1               GFXTIM_EVSR_FES1_Msk
+#define GFXTIM_EVSR_FES1_0             (0x1UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000010 */
+#define GFXTIM_EVSR_FES1_1             (0x2UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000020 */
+#define GFXTIM_EVSR_FES1_2             (0x4UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000040 */
+
+#define GFXTIM_EVSR_LES2_Pos           (8U)
+#define GFXTIM_EVSR_LES2_Msk           (0x7UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000700 */
+#define GFXTIM_EVSR_LES2               GFXTIM_EVSR_LES2_Msk
+#define GFXTIM_EVSR_LES2_0             (0x1UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000100 */
+#define GFXTIM_EVSR_LES2_1             (0x2UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000200 */
+#define GFXTIM_EVSR_LES2_2             (0x4UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000400 */
+
+#define GFXTIM_EVSR_FES2_Pos           (12U)
+#define GFXTIM_EVSR_FES2_Msk           (0x7UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00007000 */
+#define GFXTIM_EVSR_FES2               GFXTIM_EVSR_FES2_Msk
+#define GFXTIM_EVSR_FES2_0             (0x1UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00001000 */
+#define GFXTIM_EVSR_FES2_1             (0x2UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00002000 */
+#define GFXTIM_EVSR_FES2_2             (0x4UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00004000 */
+
+#define GFXTIM_EVSR_LES3_Pos           (16U)
+#define GFXTIM_EVSR_LES3_Msk           (0x7UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00070000 */
+#define GFXTIM_EVSR_LES3               GFXTIM_EVSR_LES3_Msk
+#define GFXTIM_EVSR_LES3_0             (0x1UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00010000 */
+#define GFXTIM_EVSR_LES3_1             (0x2UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00020000 */
+#define GFXTIM_EVSR_LES3_2             (0x4UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_EVSR_FES3_Pos           (20U)
+#define GFXTIM_EVSR_FES3_Msk           (0x7UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00700000 */
+#define GFXTIM_EVSR_FES3               GFXTIM_EVSR_FES3_Msk
+#define GFXTIM_EVSR_FES3_0             (0x1UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00100000 */
+#define GFXTIM_EVSR_FES3_1             (0x2UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00200000 */
+#define GFXTIM_EVSR_FES3_2             (0x4UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00400000 */
+
+#define GFXTIM_EVSR_LES4_Pos           (24U)
+#define GFXTIM_EVSR_LES4_Msk           (0x7UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x07000000 */
+#define GFXTIM_EVSR_LES4               GFXTIM_EVSR_LES4_Msk
+#define GFXTIM_EVSR_LES4_0             (0x1UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x01000000 */
+#define GFXTIM_EVSR_LES4_1             (0x2UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x02000000 */
+#define GFXTIM_EVSR_LES4_2             (0x4UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x04000000 */
+
+#define GFXTIM_EVSR_FES4_Pos           (28U)
+#define GFXTIM_EVSR_FES4_Msk           (0x7UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x70000000 */
+#define GFXTIM_EVSR_FES4               GFXTIM_EVSR_FES4_Msk
+#define GFXTIM_EVSR_FES4_0             (0x1UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x10000000 */
+#define GFXTIM_EVSR_FES4_1             (0x2UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x20000000 */
+#define GFXTIM_EVSR_FES4_2             (0x4UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_WDGTCR register  **************/
+#define GFXTIM_WDGTCR_WDGEN_Pos        (0U)
+#define GFXTIM_WDGTCR_WDGEN_Msk        (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos)      /*!< 0x00000001 */
+#define GFXTIM_WDGTCR_WDGEN            GFXTIM_WDGTCR_WDGEN_Msk
+
+#define GFXTIM_WDGTCR_WDGDIS_Pos       (1U)
+#define GFXTIM_WDGTCR_WDGDIS_Msk       (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos)     /*!< 0x00000002 */
+#define GFXTIM_WDGTCR_WDGDIS           GFXTIM_WDGTCR_WDGDIS_Msk
+
+#define GFXTIM_WDGTCR_WDGS_Pos         (2U)
+#define GFXTIM_WDGTCR_WDGS_Msk         (0x1UL << GFXTIM_WDGTCR_WDGS_Pos)       /*!< 0x00000004 */
+#define GFXTIM_WDGTCR_WDGS             GFXTIM_WDGTCR_WDGS_Msk
+
+#define GFXTIM_WDGTCR_WDGHRC_Pos       (4U)
+#define GFXTIM_WDGTCR_WDGHRC_Msk       (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000030 */
+#define GFXTIM_WDGTCR_WDGHRC           GFXTIM_WDGTCR_WDGHRC_Msk
+#define GFXTIM_WDGTCR_WDGHRC_0         (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000010 */
+#define GFXTIM_WDGTCR_WDGHRC_1         (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000020 */
+
+#define GFXTIM_WDGTCR_WDGCS_Pos        (8U)
+#define GFXTIM_WDGTCR_WDGCS_Msk        (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000700 */
+#define GFXTIM_WDGTCR_WDGCS            GFXTIM_WDGTCR_WDGCS_Msk
+#define GFXTIM_WDGTCR_WDGCS_0          (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000100 */
+#define GFXTIM_WDGTCR_WDGCS_1          (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000200 */
+#define GFXTIM_WDGTCR_WDGCS_2          (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000400 */
+#define GFXTIM_WDGTCR_WDGCS_3          (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000800 */
+
+#define GFXTIM_WDGTCR_FWDGR_Pos        (16U)
+#define GFXTIM_WDGTCR_FWDGR_Msk        (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos)      /*!< 0x00010000 */
+#define GFXTIM_WDGTCR_FWDGR            GFXTIM_WDGTCR_FWDGR_Msk
+
+/******************  Bits definition for GFXTIM_ISR register  *****************/
+#define GFXTIM_ISR_AFCOF_Pos           (0U)
+#define GFXTIM_ISR_AFCOF_Msk           (0x1UL << GFXTIM_ISR_AFCOF_Pos)         /*!< 0x00000001 */
+#define GFXTIM_ISR_AFCOF               GFXTIM_ISR_AFCOF_Msk
+
+#define GFXTIM_ISR_ALCOF_Pos           (1U)
+#define GFXTIM_ISR_ALCOF_Msk           (0x1UL << GFXTIM_ISR_ALCOF_Pos)         /*!< 0x00000002 */
+#define GFXTIM_ISR_ALCOF               GFXTIM_ISR_ALCOF_Msk
+
+#define GFXTIM_ISR_TEF_Pos             (2U)
+#define GFXTIM_ISR_TEF_Msk             (0x1UL << GFXTIM_ISR_TEF_Pos)           /*!< 0x00000004 */
+#define GFXTIM_ISR_TEF                 GFXTIM_ISR_TEF_Msk
+
+#define GFXTIM_ISR_AFCC1F_Pos          (4U)
+#define GFXTIM_ISR_AFCC1F_Msk          (0x1UL << GFXTIM_ISR_AFCC1F_Pos)        /*!< 0x00000010 */
+#define GFXTIM_ISR_AFCC1F              GFXTIM_ISR_AFCC1F_Msk
+
+#define GFXTIM_ISR_ALCC1F_Pos          (8U)
+#define GFXTIM_ISR_ALCC1F_Msk          (0x1UL << GFXTIM_ISR_ALCC1F_Pos)        /*!< 0x00000100 */
+#define GFXTIM_ISR_ALCC1F              GFXTIM_ISR_ALCC1F_Msk
+
+#define GFXTIM_ISR_ALCC2F_Pos          (9U)
+#define GFXTIM_ISR_ALCC2F_Msk          (0x1UL << GFXTIM_ISR_ALCC2F_Pos)        /*!< 0x00000200 */
+#define GFXTIM_ISR_ALCC2F              GFXTIM_ISR_ALCC2F_Msk
+
+#define GFXTIM_ISR_RFC1RF_Pos          (12U)
+#define GFXTIM_ISR_RFC1RF_Msk          (0x1UL << GFXTIM_ISR_RFC1RF_Pos)        /*!< 0x00001000 */
+#define GFXTIM_ISR_RFC1RF              GFXTIM_ISR_RFC1RF_Msk
+
+#define GFXTIM_ISR_RFC2RF_Pos          (13U)
+#define GFXTIM_ISR_RFC2RF_Msk          (0x1UL << GFXTIM_ISR_RFC2RF_Pos)        /*!< 0x00002000 */
+#define GFXTIM_ISR_RFC2RF              GFXTIM_ISR_RFC2RF_Msk
+
+#define GFXTIM_ISR_EV1F_Pos            (16U)
+#define GFXTIM_ISR_EV1F_Msk            (0x1UL << GFXTIM_ISR_EV1F_Pos)          /*!< 0x00010000 */
+#define GFXTIM_ISR_EV1F                GFXTIM_ISR_EV1F_Msk
+
+#define GFXTIM_ISR_EV2F_Pos            (17U)
+#define GFXTIM_ISR_EV2F_Msk            (0x1UL << GFXTIM_ISR_EV2F_Pos)          /*!< 0x00020000 */
+#define GFXTIM_ISR_EV2F                GFXTIM_ISR_EV2F_Msk
+
+#define GFXTIM_ISR_EV3F_Pos            (18U)
+#define GFXTIM_ISR_EV3F_Msk            (0x1UL << GFXTIM_ISR_EV3F_Pos)          /*!< 0x00040000 */
+#define GFXTIM_ISR_EV3F                GFXTIM_ISR_EV3F_Msk
+
+#define GFXTIM_ISR_EV4F_Pos            (19U)
+#define GFXTIM_ISR_EV4F_Msk            (0x1UL << GFXTIM_ISR_EV4F_Pos)          /*!< 0x00080000 */
+#define GFXTIM_ISR_EV4F                GFXTIM_ISR_EV4F_Msk
+
+#define GFXTIM_ISR_WDGAF_Pos           (24U)
+#define GFXTIM_ISR_WDGAF_Msk           (0x1UL << GFXTIM_ISR_WDGAF_Pos)         /*!< 0x01000000 */
+#define GFXTIM_ISR_WDGAF               GFXTIM_ISR_WDGAF_Msk
+
+#define GFXTIM_ISR_WDGPF_Pos           (25U)
+#define GFXTIM_ISR_WDGPF_Msk           (0x1UL << GFXTIM_ISR_WDGPF_Pos)         /*!< 0x02000000 */
+#define GFXTIM_ISR_WDGPF               GFXTIM_ISR_WDGPF_Msk
+
+/******************  Bits definition for GFXTIM_ICR register  *****************/
+#define GFXTIM_ICR_CAFCOF_Pos          (0U)
+#define GFXTIM_ICR_CAFCOF_Msk          (0x1UL << GFXTIM_ICR_CAFCOF_Pos)        /*!< 0x00000001 */
+#define GFXTIM_ICR_CAFCOF              GFXTIM_ICR_CAFCOF_Msk
+
+#define GFXTIM_ICR_CALCOF_Pos          (1U)
+#define GFXTIM_ICR_CALCOF_Msk          (0x1UL << GFXTIM_ICR_CALCOF_Pos)        /*!< 0x00000002 */
+#define GFXTIM_ICR_CALCOF              GFXTIM_ICR_CALCOF_Msk
+
+#define GFXTIM_ICR_CTEF_Pos            (2U)
+#define GFXTIM_ICR_CTEF_Msk            (0x1UL << GFXTIM_ICR_CTEF_Pos)          /*!< 0x00000004 */
+#define GFXTIM_ICR_CTEF                GFXTIM_ICR_CTEF_Msk
+
+#define GFXTIM_ICR_CAFCC1F_Pos         (4U)
+#define GFXTIM_ICR_CAFCC1F_Msk         (0x1UL << GFXTIM_ICR_CAFCC1F_Pos)       /*!< 0x00000010 */
+#define GFXTIM_ICR_CAFCC1F             GFXTIM_ICR_CAFCC1F_Msk
+
+#define GFXTIM_ICR_CALCC1F_Pos         (8U)
+#define GFXTIM_ICR_CALCC1F_Msk         (0x1UL << GFXTIM_ICR_CALCC1F_Pos)       /*!< 0x00000100 */
+#define GFXTIM_ICR_CALCC1F             GFXTIM_ICR_CALCC1F_Msk
+
+#define GFXTIM_ICR_CALCC2F_Pos         (9U)
+#define GFXTIM_ICR_CALCC2F_Msk         (0x1UL << GFXTIM_ICR_CALCC2F_Pos)       /*!< 0x00000200 */
+#define GFXTIM_ICR_CALCC2F             GFXTIM_ICR_CALCC2F_Msk
+
+#define GFXTIM_ICR_CRFC1RF_Pos         (12U)
+#define GFXTIM_ICR_CRFC1RF_Msk         (0x1UL << GFXTIM_ICR_CRFC1RF_Pos)       /*!< 0x00001000 */
+#define GFXTIM_ICR_CRFC1RF             GFXTIM_ICR_CRFC1RF_Msk
+
+#define GFXTIM_ICR_CRFC2RF_Pos         (13U)
+#define GFXTIM_ICR_CRFC2RF_Msk         (0x1UL << GFXTIM_ICR_CRFC2RF_Pos)       /*!< 0x00002000 */
+#define GFXTIM_ICR_CRFC2RF             GFXTIM_ICR_CRFC2RF_Msk
+
+#define GFXTIM_ICR_CEV1F_Pos           (16U)
+#define GFXTIM_ICR_CEV1F_Msk           (0x1UL << GFXTIM_ICR_CEV1F_Pos)         /*!< 0x00010000 */
+#define GFXTIM_ICR_CEV1F               GFXTIM_ICR_CEV1F_Msk
+
+#define GFXTIM_ICR_CEV2F_Pos           (17U)
+#define GFXTIM_ICR_CEV2F_Msk           (0x1UL << GFXTIM_ICR_CEV2F_Pos)         /*!< 0x00020000 */
+#define GFXTIM_ICR_CEV2F               GFXTIM_ICR_CEV2F_Msk
+
+#define GFXTIM_ICR_CEV3F_Pos           (18U)
+#define GFXTIM_ICR_CEV3F_Msk           (0x1UL << GFXTIM_ICR_CEV3F_Pos)         /*!< 0x00040000 */
+#define GFXTIM_ICR_CEV3F               GFXTIM_ICR_CEV3F_Msk
+
+#define GFXTIM_ICR_CEV4F_Pos           (19U)
+#define GFXTIM_ICR_CEV4F_Msk           (0x1UL << GFXTIM_ICR_CEV4F_Pos)         /*!< 0x00080000 */
+#define GFXTIM_ICR_CEV4F               GFXTIM_ICR_CEV4F_Msk
+
+#define GFXTIM_ICR_CWDGAF_Pos          (24U)
+#define GFXTIM_ICR_CWDGAF_Msk          (0x1UL << GFXTIM_ICR_CWDGAF_Pos)        /*!< 0x01000000 */
+#define GFXTIM_ICR_CWDGAF              GFXTIM_ICR_CWDGAF_Msk
+
+#define GFXTIM_ICR_CWDGPF_Pos          (25U)
+#define GFXTIM_ICR_CWDGPF_Msk          (0x1UL << GFXTIM_ICR_CWDGPF_Pos)        /*!< 0x02000000 */
+#define GFXTIM_ICR_CWDGPF              GFXTIM_ICR_CWDGPF_Msk
+
+/******************  Bits definition for GFXTIM_IER register  *****************/
+#define GFXTIM_IER_AFCOIE_Pos          (0U)
+#define GFXTIM_IER_AFCOIE_Msk          (0x1UL << GFXTIM_IER_AFCOIE_Pos)        /*!< 0x00000001 */
+#define GFXTIM_IER_AFCOIE              GFXTIM_IER_AFCOIE_Msk
+
+#define GFXTIM_IER_ALCOIE_Pos          (1U)
+#define GFXTIM_IER_ALCOIE_Msk          (0x1UL << GFXTIM_IER_ALCOIE_Pos)        /*!< 0x00000002 */
+#define GFXTIM_IER_ALCOIE              GFXTIM_IER_ALCOIE_Msk
+
+#define GFXTIM_IER_TEIE_Pos            (2U)
+#define GFXTIM_IER_TEIE_Msk            (0x1UL << GFXTIM_IER_TEIE_Pos)          /*!< 0x00000004 */
+#define GFXTIM_IER_TEIE                GFXTIM_IER_TEIE_Msk
+
+#define GFXTIM_IER_AFCC1IE_Pos         (4U)
+#define GFXTIM_IER_AFCC1IE_Msk         (0x1UL << GFXTIM_IER_AFCC1IE_Pos)       /*!< 0x00000010 */
+#define GFXTIM_IER_AFCC1IE             GFXTIM_IER_AFCC1IE_Msk
+
+#define GFXTIM_IER_ALCC1IE_Pos         (8U)
+#define GFXTIM_IER_ALCC1IE_Msk         (0x1UL << GFXTIM_IER_ALCC1IE_Pos)       /*!< 0x00000100 */
+#define GFXTIM_IER_ALCC1IE             GFXTIM_IER_ALCC1IE_Msk
+
+#define GFXTIM_IER_ALCC2IE_Pos         (9U)
+#define GFXTIM_IER_ALCC2IE_Msk         (0x1UL << GFXTIM_IER_ALCC2IE_Pos)       /*!< 0x00000200 */
+#define GFXTIM_IER_ALCC2IE             GFXTIM_IER_ALCC2IE_Msk
+
+#define GFXTIM_IER_RFC1RIE_Pos         (12U)
+#define GFXTIM_IER_RFC1RIE_Msk         (0x1UL << GFXTIM_IER_RFC1RIE_Pos)       /*!< 0x00001000 */
+#define GFXTIM_IER_RFC1RIE             GFXTIM_IER_RFC1RIE_Msk
+
+#define GFXTIM_IER_RFC2RIE_Pos         (13U)
+#define GFXTIM_IER_RFC2RIE_Msk         (0x1UL << GFXTIM_IER_RFC2RIE_Pos)       /*!< 0x00002000 */
+#define GFXTIM_IER_RFC2RIE             GFXTIM_IER_RFC2RIE_Msk
+
+#define GFXTIM_IER_EV1IE_Pos           (16U)
+#define GFXTIM_IER_EV1IE_Msk           (0x1UL << GFXTIM_IER_EV1IE_Pos)         /*!< 0x00010000 */
+#define GFXTIM_IER_EV1IE               GFXTIM_IER_EV1IE_Msk
+
+#define GFXTIM_IER_EV2IE_Pos           (17U)
+#define GFXTIM_IER_EV2IE_Msk           (0x1UL << GFXTIM_IER_EV2IE_Pos)         /*!< 0x00020000 */
+#define GFXTIM_IER_EV2IE               GFXTIM_IER_EV2IE_Msk
+
+#define GFXTIM_IER_EV3IE_Pos           (18U)
+#define GFXTIM_IER_EV3IE_Msk           (0x1UL << GFXTIM_IER_EV3IE_Pos)         /*!< 0x00040000 */
+#define GFXTIM_IER_EV3IE               GFXTIM_IER_EV3IE_Msk
+
+#define GFXTIM_IER_EV4IE_Pos           (19U)
+#define GFXTIM_IER_EV4IE_Msk           (0x1UL << GFXTIM_IER_EV4IE_Pos)         /*!< 0x00080000 */
+#define GFXTIM_IER_EV4IE               GFXTIM_IER_EV4IE_Msk
+
+#define GFXTIM_IER_WDGAIE_Pos          (24U)
+#define GFXTIM_IER_WDGAIE_Msk          (0x1UL << GFXTIM_IER_WDGAIE_Pos)        /*!< 0x01000000 */
+#define GFXTIM_IER_WDGAIE              GFXTIM_IER_WDGAIE_Msk
+
+#define GFXTIM_IER_WDGPIE_Pos          (25U)
+#define GFXTIM_IER_WDGPIE_Msk          (0x1UL << GFXTIM_IER_WDGPIE_Pos)        /*!< 0x02000000 */
+#define GFXTIM_IER_WDGPIE              GFXTIM_IER_WDGPIE_Msk
+
+/******************  Bits definition for GFXTIM_TSR register  *****************/
+#define GFXTIM_TSR_AFCS_Pos            (0U)
+#define GFXTIM_TSR_AFCS_Msk            (0x1UL << GFXTIM_TSR_AFCS_Pos)          /*!< 0x00000001 */
+#define GFXTIM_TSR_AFCS                GFXTIM_TSR_AFCS_Msk
+
+#define GFXTIM_TSR_ALCS_Pos            (4U)
+#define GFXTIM_TSR_ALCS_Msk            (0x1UL << GFXTIM_TSR_ALCS_Pos)          /*!< 0x00000010 */
+#define GFXTIM_TSR_ALCS                GFXTIM_TSR_ALCS_Msk
+
+#define GFXTIM_TSR_RFC1S_Pos           (16U)
+#define GFXTIM_TSR_RFC1S_Msk           (0x1UL << GFXTIM_TSR_RFC1S_Pos)         /*!< 0x00010000 */
+#define GFXTIM_TSR_RFC1S               GFXTIM_TSR_RFC1S_Msk
+
+#define GFXTIM_TSR_RFC2S_Pos           (20U)
+#define GFXTIM_TSR_RFC2S_Msk           (0x1UL << GFXTIM_TSR_RFC2S_Pos)         /*!< 0x00100000 */
+#define GFXTIM_TSR_RFC2S               GFXTIM_TSR_RFC2S_Msk
+
+/******************  Bits definition for GFXTIM_LCCRR register  ***************/
+#define GFXTIM_LCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_LCCRR_RELOAD_Msk        (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
+#define GFXTIM_LCCRR_RELOAD            GFXTIM_LCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_FCCRR register  ***************/
+#define GFXTIM_FCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_FCCRR_RELOAD_Msk        (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_FCCRR_RELOAD            GFXTIM_FCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_ATR register  *****************/
+#define GFXTIM_ATR_LINE_Pos            (0U)
+#define GFXTIM_ATR_LINE_Msk            (0xFFFUL << GFXTIM_ATR_LINE_Pos)        /*!< 0x00000FFF */
+#define GFXTIM_ATR_LINE                GFXTIM_ATR_LINE_Msk
+
+#define GFXTIM_ATR_FRAME_Pos           (12U)
+#define GFXTIM_ATR_FRAME_Msk           (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos)     /*!< 0xFFFFF000 */
+#define GFXTIM_ATR_FRAME               GFXTIM_ATR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_AFCR register  ****************/
+#define GFXTIM_AFCR_FRAME_Pos          (0U)
+#define GFXTIM_AFCR_FRAME_Msk          (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos)    /*!< 0x000FFFFF */
+#define GFXTIM_AFCR_FRAME              GFXTIM_AFCR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCR register  ****************/
+#define GFXTIM_ALCR_LINE_Pos           (0U)
+#define GFXTIM_ALCR_LINE_Msk           (0xFFFUL << GFXTIM_ALCR_LINE_Pos)       /*!< 0x00000FFF */
+#define GFXTIM_ALCR_LINE               GFXTIM_ALCR_LINE_Msk
+
+/******************  Bits definition for GFXTIM_AFCC1R register  **************/
+#define GFXTIM_AFCC1R_FRAME_Pos        (0U)
+#define GFXTIM_AFCC1R_FRAME_Msk        (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos)  /*!< 0x000FFFFF */
+#define GFXTIM_AFCC1R_FRAME            GFXTIM_AFCC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCC1R register  **************/
+#define GFXTIM_ALCC1R_LINE_Pos         (0U)
+#define GFXTIM_ALCC1R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC1R_LINE             GFXTIM_ALCC1R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_ALCC2R register  **************/
+#define GFXTIM_ALCC2R_LINE_Pos         (0U)
+#define GFXTIM_ALCC2R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC2R_LINE             GFXTIM_ALCC2R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_RFC1R register  ***************/
+#define GFXTIM_RFC1R_FRAME_Pos         (0U)
+#define GFXTIM_RFC1R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC1R_FRAME             GFXTIM_RFC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC1RR register  **************/
+#define GFXTIM_RFC1RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC1RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC1RR_FRAME            GFXTIM_RFC1RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2R register  ***************/
+#define GFXTIM_RFC2R_FRAME_Pos         (0U)
+#define GFXTIM_RFC2R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC2R_FRAME             GFXTIM_RFC2R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2RR register  **************/
+#define GFXTIM_RFC2RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC2RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC2RR_FRAME            GFXTIM_RFC2RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_WDGCR register  ***************/
+#define GFXTIM_WDGCR_VALUE_Pos         (0U)
+#define GFXTIM_WDGCR_VALUE_Msk         (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos)    /*!< 0x0000FFFF */
+#define GFXTIM_WDGCR_VALUE             GFXTIM_WDGCR_VALUE_Msk
+
+/******************  Bits definition for GFXTIM_WDGRR register  ***************/
+#define GFXTIM_WDGRR_RELOAD_Pos        (0U)
+#define GFXTIM_WDGRR_RELOAD_Msk        (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos)   /*!< 0x0000FFFF */
+#define GFXTIM_WDGRR_RELOAD            GFXTIM_WDGRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_WDGPAR register  **************/
+#define GFXTIM_WDGPAR_PREALARM_Pos      (0U)
+#define GFXTIM_WDGPAR_PREALARM_Msk     (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
+#define GFXTIM_WDGPAR_PREALARM          GFXTIM_WDGPAR_PREALARM_Msk
+
+/******************  Bits definition for GFXTIM_HWCFGR register  **************/
+
+/******************  Bits definition for GFXTIM_VERR register  ****************/
+#define GFXTIM_VERR_MINREV_Pos         (0U)
+#define GFXTIM_VERR_MINREV_Msk         (0xFUL << GFXTIM_VERR_MINREV_Pos)       /*!< 0x0000000F */
+#define GFXTIM_VERR_MINREV             GFXTIM_VERR_MINREV_Msk
+
+#define GFXTIM_VERR_MAJREV_Pos         (4U)
+#define GFXTIM_VERR_MAJREV_Msk         (0xFUL << GFXTIM_VERR_MAJREV_Pos)       /*!< 0x000000F0 */
+#define GFXTIM_VERR_MAJREV             GFXTIM_VERR_MAJREV_Msk
+
+/******************  Bits definition for GFXTIM_IPIDR register  ***************/
+#define GFXTIM_IPIDR_ID_Pos            (0U)
+#define GFXTIM_IPIDR_ID_Msk            (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_IPIDR_ID                GFXTIM_IPIDR_ID_Msk
+
+/******************  Bits definition for GFXTIM_SIDR register  ****************/
+#define GFXTIM_SIDR_SID_Pos            (0U)
+#define GFXTIM_SIDR_SID_Msk            (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_SIDR_SID                GFXTIM_SIDR_SID_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)
+#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos               (1U)
+#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos               (2U)
+#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos               (3U)
+#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos               (4U)
+#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos               (5U)
+#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos               (6U)
+#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos               (7U)
+#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos               (8U)
+#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos               (9U)
+#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos              (10U)
+#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos              (11U)
+#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos              (12U)
+#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos              (13U)
+#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos              (14U)
+#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos              (15U)
+#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
+
+/******************  Bits definition for GPIO_SECCFGR register  ******************/
+#define GPIO_SECCFGR_SEC0_Pos          (0U)
+#define GPIO_SECCFGR_SEC0_Msk          (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
+#define GPIO_SECCFGR_SEC0              GPIO_SECCFGR_SEC0_Msk
+#define GPIO_SECCFGR_SEC1_Pos          (1U)
+#define GPIO_SECCFGR_SEC1_Msk          (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
+#define GPIO_SECCFGR_SEC1              GPIO_SECCFGR_SEC1_Msk
+#define GPIO_SECCFGR_SEC2_Pos          (2U)
+#define GPIO_SECCFGR_SEC2_Msk          (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
+#define GPIO_SECCFGR_SEC2              GPIO_SECCFGR_SEC2_Msk
+#define GPIO_SECCFGR_SEC3_Pos          (3U)
+#define GPIO_SECCFGR_SEC3_Msk          (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
+#define GPIO_SECCFGR_SEC3              GPIO_SECCFGR_SEC3_Msk
+#define GPIO_SECCFGR_SEC4_Pos          (4U)
+#define GPIO_SECCFGR_SEC4_Msk          (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
+#define GPIO_SECCFGR_SEC4              GPIO_SECCFGR_SEC4_Msk
+#define GPIO_SECCFGR_SEC5_Pos          (5U)
+#define GPIO_SECCFGR_SEC5_Msk          (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
+#define GPIO_SECCFGR_SEC5              GPIO_SECCFGR_SEC5_Msk
+#define GPIO_SECCFGR_SEC6_Pos          (6U)
+#define GPIO_SECCFGR_SEC6_Msk          (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
+#define GPIO_SECCFGR_SEC6              GPIO_SECCFGR_SEC6_Msk
+#define GPIO_SECCFGR_SEC7_Pos          (7U)
+#define GPIO_SECCFGR_SEC7_Msk          (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
+#define GPIO_SECCFGR_SEC7              GPIO_SECCFGR_SEC7_Msk
+#define GPIO_SECCFGR_SEC8_Pos          (8U)
+#define GPIO_SECCFGR_SEC8_Msk          (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
+#define GPIO_SECCFGR_SEC8              GPIO_SECCFGR_SEC8_Msk
+#define GPIO_SECCFGR_SEC9_Pos          (9U)
+#define GPIO_SECCFGR_SEC9_Msk          (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
+#define GPIO_SECCFGR_SEC9              GPIO_SECCFGR_SEC9_Msk
+#define GPIO_SECCFGR_SEC10_Pos         (10U)
+#define GPIO_SECCFGR_SEC10_Msk         (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
+#define GPIO_SECCFGR_SEC10             GPIO_SECCFGR_SEC10_Msk
+#define GPIO_SECCFGR_SEC11_Pos         (11U)
+#define GPIO_SECCFGR_SEC11_Msk         (0x1UL << GPIO_SECCFGR_SEC11_Pos)       /*!< 0x00000800 */
+#define GPIO_SECCFGR_SEC11             GPIO_SECCFGR_SEC11_Msk
+#define GPIO_SECCFGR_SEC12_Pos         (12U)
+#define GPIO_SECCFGR_SEC12_Msk         (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
+#define GPIO_SECCFGR_SEC12             GPIO_SECCFGR_SEC12_Msk
+#define GPIO_SECCFGR_SEC13_Pos         (13U)
+#define GPIO_SECCFGR_SEC13_Msk         (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
+#define GPIO_SECCFGR_SEC13             GPIO_SECCFGR_SEC13_Msk
+#define GPIO_SECCFGR_SEC14_Pos         (14U)
+#define GPIO_SECCFGR_SEC14_Msk         (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
+#define GPIO_SECCFGR_SEC14             GPIO_SECCFGR_SEC14_Msk
+#define GPIO_SECCFGR_SEC15_Pos         (15U)
+#define GPIO_SECCFGR_SEC15_Msk         (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
+#define GPIO_SECCFGR_SEC15             GPIO_SECCFGR_SEC15_Msk
+
+/******************  Bits definition for GPIO_PRIVCFGR register  ******************/
+#define GPIO_PRIVCFGR_PRIV0_Pos        (0U)
+#define GPIO_PRIVCFGR_PRIV0_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV0_Pos)      /*!< 0x00000001 */
+#define GPIO_PRIVCFGR_PRIV0            GPIO_PRIVCFGR_PRIV0_Msk
+#define GPIO_PRIVCFGR_PRIV1_Pos        (1U)
+#define GPIO_PRIVCFGR_PRIV1_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV1_Pos)      /*!< 0x00000002 */
+#define GPIO_PRIVCFGR_PRIV1            GPIO_PRIVCFGR_PRIV1_Msk
+#define GPIO_PRIVCFGR_PRIV2_Pos        (2U)
+#define GPIO_PRIVCFGR_PRIV2_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV2_Pos)      /*!< 0x00000004 */
+#define GPIO_PRIVCFGR_PRIV2            GPIO_PRIVCFGR_PRIV2_Msk
+#define GPIO_PRIVCFGR_PRIV3_Pos        (3U)
+#define GPIO_PRIVCFGR_PRIV3_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV3_Pos)      /*!< 0x00000008 */
+#define GPIO_PRIVCFGR_PRIV3            GPIO_PRIVCFGR_PRIV3_Msk
+#define GPIO_PRIVCFGR_PRIV4_Pos        (4U)
+#define GPIO_PRIVCFGR_PRIV4_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV4_Pos)      /*!< 0x00000010 */
+#define GPIO_PRIVCFGR_PRIV4            GPIO_PRIVCFGR_PRIV4_Msk
+#define GPIO_PRIVCFGR_PRIV5_Pos        (5U)
+#define GPIO_PRIVCFGR_PRIV5_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV5_Pos)      /*!< 0x00000020 */
+#define GPIO_PRIVCFGR_PRIV5            GPIO_PRIVCFGR_PRIV5_Msk
+#define GPIO_PRIVCFGR_PRIV6_Pos        (6U)
+#define GPIO_PRIVCFGR_PRIV6_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV6_Pos)      /*!< 0x00000040 */
+#define GPIO_PRIVCFGR_PRIV6            GPIO_PRIVCFGR_PRIV6_Msk
+#define GPIO_PRIVCFGR_PRIV7_Pos        (7U)
+#define GPIO_PRIVCFGR_PRIV7_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV7_Pos)      /*!< 0x00000080 */
+#define GPIO_PRIVCFGR_PRIV7            GPIO_PRIVCFGR_PRIV7_Msk
+#define GPIO_PRIVCFGR_PRIV8_Pos        (8U)
+#define GPIO_PRIVCFGR_PRIV8_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV8_Pos)      /*!< 0x00000100 */
+#define GPIO_PRIVCFGR_PRIV8            GPIO_PRIVCFGR_PRIV8_Msk
+#define GPIO_PRIVCFGR_PRIV9_Pos        (9U)
+#define GPIO_PRIVCFGR_PRIV9_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV9_Pos)      /*!< 0x00000200 */
+#define GPIO_PRIVCFGR_PRIV9            GPIO_PRIVCFGR_PRIV9_Msk
+#define GPIO_PRIVCFGR_PRIV10_Pos       (10U)
+#define GPIO_PRIVCFGR_PRIV10_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV10_Pos)     /*!< 0x00000400 */
+#define GPIO_PRIVCFGR_PRIV10           GPIO_PRIVCFGR_PRIV10_Msk
+#define GPIO_PRIVCFGR_PRIV11_Pos       (11U)
+#define GPIO_PRIVCFGR_PRIV11_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV11_Pos)     /*!< 0x00000800 */
+#define GPIO_PRIVCFGR_PRIV11           GPIO_PRIVCFGR_PRIV11_Msk
+#define GPIO_PRIVCFGR_PRIV12_Pos       (12U)
+#define GPIO_PRIVCFGR_PRIV12_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV12_Pos)     /*!< 0x00001000 */
+#define GPIO_PRIVCFGR_PRIV12           GPIO_PRIVCFGR_PRIV12_Msk
+#define GPIO_PRIVCFGR_PRIV13_Pos       (13U)
+#define GPIO_PRIVCFGR_PRIV13_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV13_Pos)     /*!< 0x00002000 */
+#define GPIO_PRIVCFGR_PRIV13           GPIO_PRIVCFGR_PRIV13_Msk
+#define GPIO_PRIVCFGR_PRIV14_Pos       (14U)
+#define GPIO_PRIVCFGR_PRIV14_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV14_Pos)     /*!< 0x00004000 */
+#define GPIO_PRIVCFGR_PRIV14           GPIO_PRIVCFGR_PRIV14_Msk
+#define GPIO_PRIVCFGR_PRIV15_Pos       (15U)
+#define GPIO_PRIVCFGR_PRIV15_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV15_Pos)     /*!< 0x00008000 */
+#define GPIO_PRIVCFGR_PRIV15           GPIO_PRIVCFGR_PRIV15_Msk
+
+/******************  Bits definition for GPIO_RCFGLOCKR register  ******************/
+#define GPIO_RCFGLOCKR_RLOCK0_Pos      (0U)
+#define GPIO_RCFGLOCKR_RLOCK0_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK0_Pos)    /*!< 0x00000001 */
+#define GPIO_RCFGLOCKR_RLOCK0          GPIO_RCFGLOCKR_RLOCK0_Msk
+#define GPIO_RCFGLOCKR_RLOCK1_Pos      (1U)
+#define GPIO_RCFGLOCKR_RLOCK1_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK1_Pos)    /*!< 0x00000002 */
+#define GPIO_RCFGLOCKR_RLOCK1          GPIO_RCFGLOCKR_RLOCK1_Msk
+#define GPIO_RCFGLOCKR_RLOCK2_Pos      (2U)
+#define GPIO_RCFGLOCKR_RLOCK2_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK2_Pos)    /*!< 0x00000004 */
+#define GPIO_RCFGLOCKR_RLOCK2          GPIO_RCFGLOCKR_RLOCK2_Msk
+#define GPIO_RCFGLOCKR_RLOCK3_Pos      (3U)
+#define GPIO_RCFGLOCKR_RLOCK3_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK3_Pos)    /*!< 0x00000008 */
+#define GPIO_RCFGLOCKR_RLOCK3          GPIO_RCFGLOCKR_RLOCK3_Msk
+#define GPIO_RCFGLOCKR_RLOCK4_Pos      (4U)
+#define GPIO_RCFGLOCKR_RLOCK4_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK4_Pos)    /*!< 0x00000010 */
+#define GPIO_RCFGLOCKR_RLOCK4          GPIO_RCFGLOCKR_RLOCK4_Msk
+#define GPIO_RCFGLOCKR_RLOCK5_Pos      (5U)
+#define GPIO_RCFGLOCKR_RLOCK5_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK5_Pos)    /*!< 0x00000020 */
+#define GPIO_RCFGLOCKR_RLOCK5          GPIO_RCFGLOCKR_RLOCK5_Msk
+#define GPIO_RCFGLOCKR_RLOCK6_Pos      (6U)
+#define GPIO_RCFGLOCKR_RLOCK6_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK6_Pos)    /*!< 0x00000040 */
+#define GPIO_RCFGLOCKR_RLOCK6          GPIO_RCFGLOCKR_RLOCK6_Msk
+#define GPIO_RCFGLOCKR_RLOCK7_Pos      (7U)
+#define GPIO_RCFGLOCKR_RLOCK7_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK7_Pos)    /*!< 0x00000080 */
+#define GPIO_RCFGLOCKR_RLOCK7          GPIO_RCFGLOCKR_RLOCK7_Msk
+#define GPIO_RCFGLOCKR_RLOCK8_Pos      (8U)
+#define GPIO_RCFGLOCKR_RLOCK8_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK8_Pos)    /*!< 0x00000100 */
+#define GPIO_RCFGLOCKR_RLOCK8          GPIO_RCFGLOCKR_RLOCK8_Msk
+#define GPIO_RCFGLOCKR_RLOCK9_Pos      (9U)
+#define GPIO_RCFGLOCKR_RLOCK9_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK9_Pos)    /*!< 0x00000200 */
+#define GPIO_RCFGLOCKR_RLOCK9          GPIO_RCFGLOCKR_RLOCK9_Msk
+#define GPIO_RCFGLOCKR_RLOCK10_Pos     (10U)
+#define GPIO_RCFGLOCKR_RLOCK10_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK10_Pos)   /*!< 0x00000400 */
+#define GPIO_RCFGLOCKR_RLOCK10         GPIO_RCFGLOCKR_RLOCK10_Msk
+#define GPIO_RCFGLOCKR_RLOCK11_Pos     (11U)
+#define GPIO_RCFGLOCKR_RLOCK11_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK11_Pos)   /*!< 0x00000800 */
+#define GPIO_RCFGLOCKR_RLOCK11         GPIO_RCFGLOCKR_RLOCK11_Msk
+#define GPIO_RCFGLOCKR_RLOCK12_Pos     (12U)
+#define GPIO_RCFGLOCKR_RLOCK12_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK12_Pos)   /*!< 0x00001000 */
+#define GPIO_RCFGLOCKR_RLOCK12         GPIO_RCFGLOCKR_RLOCK12_Msk
+#define GPIO_RCFGLOCKR_RLOCK13_Pos     (13U)
+#define GPIO_RCFGLOCKR_RLOCK13_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK13_Pos)   /*!< 0x00002000 */
+#define GPIO_RCFGLOCKR_RLOCK13         GPIO_RCFGLOCKR_RLOCK13_Msk
+#define GPIO_RCFGLOCKR_RLOCK14_Pos     (14U)
+#define GPIO_RCFGLOCKR_RLOCK14_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK14_Pos)   /*!< 0x00004000 */
+#define GPIO_RCFGLOCKR_RLOCK14         GPIO_RCFGLOCKR_RLOCK14_Msk
+#define GPIO_RCFGLOCKR_RLOCK15_Pos     (15U)
+#define GPIO_RCFGLOCKR_RLOCK15_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK15_Pos)   /*!< 0x00008000 */
+#define GPIO_RCFGLOCKR_RLOCK15         GPIO_RCFGLOCKR_RLOCK15_Msk
+
+/****************** Bit definition for GPIO_DELAYRL register *********************/
+#define GPIO_DELAYRL_DLY0_Pos        (0U)
+#define GPIO_DELAYRL_DLY0_Msk        (0xFUL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRL_DLY0            GPIO_DELAYRL_DLY0_Msk
+#define GPIO_DELAYRL_DLY0_0          (0x1UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRL_DLY0_1          (0x2UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRL_DLY0_2          (0x4UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRL_DLY0_3          (0x8UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRL_DLY1_Pos        (4U)
+#define GPIO_DELAYRL_DLY1_Msk        (0xFUL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRL_DLY1            GPIO_DELAYRL_DLY1_Msk
+#define GPIO_DELAYRL_DLY1_0          (0x1UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRL_DLY1_1          (0x2UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRL_DLY1_2          (0x4UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRL_DLY1_3          (0x8UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRL_DLY2_Pos        (8U)
+#define GPIO_DELAYRL_DLY2_Msk        (0xFUL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000F00 */
+#define GPIO_DELAYRL_DLY2            GPIO_DELAYRL_DLY2_Msk
+#define GPIO_DELAYRL_DLY2_0          (0x1UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000100 */
+#define GPIO_DELAYRL_DLY2_1          (0x2UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000200 */
+#define GPIO_DELAYRL_DLY2_2          (0x4UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000400 */
+#define GPIO_DELAYRL_DLY2_3          (0x8UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000800 */
+#define GPIO_DELAYRL_DLY3_Pos        (12U)
+#define GPIO_DELAYRL_DLY3_Msk        (0xFUL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x0000F000 */
+#define GPIO_DELAYRL_DLY3            GPIO_DELAYRL_DLY3_Msk
+#define GPIO_DELAYRL_DLY3_0          (0x1UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00001000 */
+#define GPIO_DELAYRL_DLY3_1          (0x2UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00002000 */
+#define GPIO_DELAYRL_DLY3_2          (0x4UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00004000 */
+#define GPIO_DELAYRL_DLY3_3          (0x8UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00008000 */
+#define GPIO_DELAYRL_DLY4_Pos        (16U)
+#define GPIO_DELAYRL_DLY4_Msk        (0xFUL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x000F0000 */
+#define GPIO_DELAYRL_DLY4            GPIO_DELAYRL_DLY4_Msk
+#define GPIO_DELAYRL_DLY4_0          (0x1UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00010000 */
+#define GPIO_DELAYRL_DLY4_1          (0x2UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00020000 */
+#define GPIO_DELAYRL_DLY4_2          (0x4UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00040000 */
+#define GPIO_DELAYRL_DLY4_3          (0x8UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00080000 */
+#define GPIO_DELAYRL_DLY5_Pos        (20U)
+#define GPIO_DELAYRL_DLY5_Msk        (0xFUL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00F00000 */
+#define GPIO_DELAYRL_DLY5            GPIO_DELAYRL_DLY5_Msk
+#define GPIO_DELAYRL_DLY5_0          (0x1UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00100000 */
+#define GPIO_DELAYRL_DLY5_1          (0x2UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00200000 */
+#define GPIO_DELAYRL_DLY5_2          (0x4UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00400000 */
+#define GPIO_DELAYRL_DLY5_3          (0x8UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00800000 */
+#define GPIO_DELAYRL_DLY6_Pos        (24U)
+#define GPIO_DELAYRL_DLY6_Msk        (0xFUL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x0F000000 */
+#define GPIO_DELAYRL_DLY6            GPIO_DELAYRL_DLY6_Msk
+#define GPIO_DELAYRL_DLY6_0          (0x1UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x01000000 */
+#define GPIO_DELAYRL_DLY6_1          (0x2UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x02000000 */
+#define GPIO_DELAYRL_DLY6_2          (0x4UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x04000000 */
+#define GPIO_DELAYRL_DLY6_3          (0x8UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x08000000 */
+#define GPIO_DELAYRL_DLY7_Pos        (28U)
+#define GPIO_DELAYRL_DLY7_Msk        (0xFUL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0xF0000000 */
+#define GPIO_DELAYRL_DLY7            GPIO_DELAYRL_DLY7_Msk
+#define GPIO_DELAYRL_DLY7_0          (0x1UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x10000000 */
+#define GPIO_DELAYRL_DLY7_1          (0x2UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x20000000 */
+#define GPIO_DELAYRL_DLY7_2          (0x4UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x40000000 */
+#define GPIO_DELAYRL_DLY7_3          (0x8UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_DELAYRH register *********************/
+#define GPIO_DELAYRH_DLY8_Pos        (0U)
+#define GPIO_DELAYRH_DLY8_Msk        (0xFUL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRH_DLY8            GPIO_DELAYRH_DLY8_Msk
+#define GPIO_DELAYRH_DLY8_0          (0x1UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRH_DLY8_1          (0x2UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRH_DLY8_2          (0x4UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRH_DLY8_3          (0x8UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRH_DLY9_Pos        (4U)
+#define GPIO_DELAYRH_DLY9_Msk        (0xFUL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRH_DLY9            GPIO_DELAYRH_DLY9_Msk
+#define GPIO_DELAYRH_DLY9_0          (0x1UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRH_DLY9_1          (0x2UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRH_DLY9_2          (0x4UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRH_DLY9_3          (0x8UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRH_DLY10_Pos       (8U)
+#define GPIO_DELAYRH_DLY10_Msk       (0xFUL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000F00 */
+#define GPIO_DELAYRH_DLY10           GPIO_DELAYRH_DLY10_Msk
+#define GPIO_DELAYRH_DLY10_0         (0x1UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000100 */
+#define GPIO_DELAYRH_DLY10_1         (0x2UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000200 */
+#define GPIO_DELAYRH_DLY10_2         (0x4UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000400 */
+#define GPIO_DELAYRH_DLY10_3         (0x8UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000800 */
+#define GPIO_DELAYRH_DLY11_Pos       (12U)
+#define GPIO_DELAYRH_DLY11_Msk       (0xFUL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x0000F000 */
+#define GPIO_DELAYRH_DLY11           GPIO_DELAYRH_DLY11_Msk
+#define GPIO_DELAYRH_DLY11_0         (0x1UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00001000 */
+#define GPIO_DELAYRH_DLY11_1         (0x2UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00002000 */
+#define GPIO_DELAYRH_DLY11_2         (0x4UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00004000 */
+#define GPIO_DELAYRH_DLY11_3         (0x8UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00008000 */
+#define GPIO_DELAYRH_DLY12_Pos       (16U)
+#define GPIO_DELAYRH_DLY12_Msk       (0xFUL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x000F0000 */
+#define GPIO_DELAYRH_DLY12           GPIO_DELAYRH_DLY12_Msk
+#define GPIO_DELAYRH_DLY12_0         (0x1UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00010000 */
+#define GPIO_DELAYRH_DLY12_1         (0x2UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00020000 */
+#define GPIO_DELAYRH_DLY12_2         (0x4UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00040000 */
+#define GPIO_DELAYRH_DLY12_3         (0x8UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00080000 */
+#define GPIO_DELAYRH_DLY13_Pos       (20U)
+#define GPIO_DELAYRH_DLY13_Msk       (0xFUL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00F00000 */
+#define GPIO_DELAYRH_DLY13           GPIO_DELAYRH_DLY13_Msk
+#define GPIO_DELAYRH_DLY13_0         (0x1UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00100000 */
+#define GPIO_DELAYRH_DLY13_1         (0x2UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00200000 */
+#define GPIO_DELAYRH_DLY13_2         (0x4UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00400000 */
+#define GPIO_DELAYRH_DLY13_3         (0x8UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00800000 */
+#define GPIO_DELAYRH_DLY14_Pos       (24U)
+#define GPIO_DELAYRH_DLY14_Msk       (0xFUL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x0F000000 */
+#define GPIO_DELAYRH_DLY14           GPIO_DELAYRH_DLY14_Msk
+#define GPIO_DELAYRH_DLY14_0         (0x1UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x01000000 */
+#define GPIO_DELAYRH_DLY14_1         (0x2UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x02000000 */
+#define GPIO_DELAYRH_DLY14_2         (0x4UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x04000000 */
+#define GPIO_DELAYRH_DLY14_3         (0x8UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x08000000 */
+#define GPIO_DELAYRH_DLY15_Pos       (28U)
+#define GPIO_DELAYRH_DLY15_Msk       (0xFUL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0xF0000000 */
+#define GPIO_DELAYRH_DLY15           GPIO_DELAYRH_DLY15_Msk
+#define GPIO_DELAYRH_DLY15_0         (0x1UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x10000000 */
+#define GPIO_DELAYRH_DLY15_1         (0x2UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x20000000 */
+#define GPIO_DELAYRH_DLY15_2         (0x4UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x40000000 */
+#define GPIO_DELAYRH_DLY15_3         (0x8UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRL register *********************/
+#define GPIO_ADVCFGRL_0_Pos            (0U)
+#define GPIO_ADVCFGRL_0_Msk            (0xFUL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRL_0                GPIO_ADVCFGRL_0_Msk
+#define GPIO_ADVCFGRL_DLYPATH0         (0x1UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRL_DE0              (0x2UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRL_INVCLK0          (0x4UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRL_RET0             (0x8UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRL_1_Pos            (4U)
+#define GPIO_ADVCFGRL_1_Msk            (0xFUL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRL_1                GPIO_ADVCFGRL_1_Msk
+#define GPIO_ADVCFGRL_DLYPATH1         (0x1UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRL_DE1              (0x2UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRL_INVCLK1          (0x4UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRL_RET1             (0x8UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRL_2_Pos            (8U)
+#define GPIO_ADVCFGRL_2_Msk            (0xFUL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000F00 */
+#define GPIO_ADVCFGRL_2                GPIO_ADVCFGRL_2_Msk
+#define GPIO_ADVCFGRL_DLYPATH2         (0x1UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000100 */
+#define GPIO_ADVCFGRL_DE2              (0x2UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000200 */
+#define GPIO_ADVCFGRL_INVCLK2          (0x4UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000400 */
+#define GPIO_ADVCFGRL_RET2             (0x8UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000800 */
+#define GPIO_ADVCFGRL_3_Pos            (12U)
+#define GPIO_ADVCFGRL_3_Msk            (0xFUL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x0000F000 */
+#define GPIO_ADVCFGRL_3                GPIO_ADVCFGRL_3_Msk
+#define GPIO_ADVCFGRL_DLYPATH3         (0x1UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00001000 */
+#define GPIO_ADVCFGRL_DE3              (0x2UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00002000 */
+#define GPIO_ADVCFGRL_INVCLK3          (0x4UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00004000 */
+#define GPIO_ADVCFGRL_RET3             (0x8UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00008000 */
+#define GPIO_ADVCFGRL_4_Pos            (16U)
+#define GPIO_ADVCFGRL_4_Msk            (0xFUL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x000F0000 */
+#define GPIO_ADVCFGRL_4                GPIO_ADVCFGRL_4_Msk
+#define GPIO_ADVCFGRL_DLYPATH4         (0x1UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00010000 */
+#define GPIO_ADVCFGRL_DE4              (0x2UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00020000 */
+#define GPIO_ADVCFGRL_INVCLK4          (0x4UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00040000 */
+#define GPIO_ADVCFGRL_RET4             (0x8UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00080000 */
+#define GPIO_ADVCFGRL_5_Pos            (20U)
+#define GPIO_ADVCFGRL_5_Msk            (0xFUL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00F00000 */
+#define GPIO_ADVCFGRL_5                GPIO_ADVCFGRL_5_Msk
+#define GPIO_ADVCFGRL_DLYPATH5         (0x1UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00100000 */
+#define GPIO_ADVCFGRL_DE5              (0x2UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00200000 */
+#define GPIO_ADVCFGRL_INVCLK5          (0x4UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00400000 */
+#define GPIO_ADVCFGRL_RET5             (0x8UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00800000 */
+#define GPIO_ADVCFGRL_6_Pos            (24U)
+#define GPIO_ADVCFGRL_6_Msk            (0xFUL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x0F000000 */
+#define GPIO_ADVCFGRL_6                GPIO_ADVCFGRL_6_Msk
+#define GPIO_ADVCFGRL_DLYPATH6         (0x1UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x01000000 */
+#define GPIO_ADVCFGRL_DE6              (0x2UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x02000000 */
+#define GPIO_ADVCFGRL_INVCLK6          (0x4UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x04000000 */
+#define GPIO_ADVCFGRL_RET6             (0x8UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x08000000 */
+#define GPIO_ADVCFGRL_7_Pos            (28U)
+#define GPIO_ADVCFGRL_7_Msk            (0xFUL << GPIO_ADVCFGRL_7_Pos)          /*!< 0xF0000000 */
+#define GPIO_ADVCFGRL_7                GPIO_ADVCFGRL_7_Msk
+#define GPIO_ADVCFGRL_DLYPATH7         (0x1UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x10000000 */
+#define GPIO_ADVCFGRL_DE7              (0x2UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x20000000 */
+#define GPIO_ADVCFGRL_INVCLK7          (0x4UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x40000000 */
+#define GPIO_ADVCFGRL_RET7             (0x8UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRH register *********************/
+#define GPIO_ADVCFGRH_8_Pos            (0U)
+#define GPIO_ADVCFGRH_8_Msk            (0xFUL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRH_8                GPIO_ADVCFGRH_8_Msk
+#define GPIO_ADVCFGRH_DLYPATH8         (0x1UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRH_DE8              (0x2UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRH_INVCLK8          (0x4UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRH_RET8             (0x8UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRH_9_Pos            (4U)
+#define GPIO_ADVCFGRH_9_Msk            (0xFUL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRH_9                GPIO_ADVCFGRH_9_Msk
+#define GPIO_ADVCFGRH_DLYPATH9         (0x1UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRH_DE9              (0x2UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRH_INVCLK9          (0x4UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRH_RET9             (0x8UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRH_10_Pos           (8U)
+#define GPIO_ADVCFGRH_10_Msk           (0xFUL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000F00 */
+#define GPIO_ADVCFGRH_10               GPIO_ADVCFGRH_10_Msk
+#define GPIO_ADVCFGRH_DLYPATH10        (0x1UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000100 */
+#define GPIO_ADVCFGRH_DE10             (0x2UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000200 */
+#define GPIO_ADVCFGRH_INVCLK10         (0x4UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000400 */
+#define GPIO_ADVCFGRH_RET10            (0x8UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000800 */
+#define GPIO_ADVCFGRH_11_Pos           (12U)
+#define GPIO_ADVCFGRH_11_Msk           (0xFUL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x0000F000 */
+#define GPIO_ADVCFGRH_11               GPIO_ADVCFGRH_11_Msk
+#define GPIO_ADVCFGRH_DLYPATH11        (0x1UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00001000 */
+#define GPIO_ADVCFGRH_DE11             (0x2UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00002000 */
+#define GPIO_ADVCFGRH_INVCLK11         (0x4UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00004000 */
+#define GPIO_ADVCFGRH_RET11            (0x8UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00008000 */
+#define GPIO_ADVCFGRH_12_Pos           (16U)
+#define GPIO_ADVCFGRH_12_Msk           (0xFUL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x000F0000 */
+#define GPIO_ADVCFGRH_12               GPIO_ADVCFGRH_12_Msk
+#define GPIO_ADVCFGRH_DLYPATH12        (0x1UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00010000 */
+#define GPIO_ADVCFGRH_DE12             (0x2UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00020000 */
+#define GPIO_ADVCFGRH_INVCLK12         (0x4UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00040000 */
+#define GPIO_ADVCFGRH_RET12            (0x8UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00080000 */
+#define GPIO_ADVCFGRH_13_Pos           (20U)
+#define GPIO_ADVCFGRH_13_Msk           (0xFUL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00F00000 */
+#define GPIO_ADVCFGRH_13               GPIO_ADVCFGRH_13_Msk
+#define GPIO_ADVCFGRH_DLYPATH13        (0x1UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00100000 */
+#define GPIO_ADVCFGRH_DE13             (0x2UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00200000 */
+#define GPIO_ADVCFGRH_INVCLK13         (0x4UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00400000 */
+#define GPIO_ADVCFGRH_RET13            (0x8UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00800000 */
+#define GPIO_ADVCFGRH_14_Pos           (24U)
+#define GPIO_ADVCFGRH_14_Msk           (0xFUL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x0F000000 */
+#define GPIO_ADVCFGRH_14               GPIO_ADVCFGRH_14_Msk
+#define GPIO_ADVCFGRH_DLYPATH14        (0x1UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x01000000 */
+#define GPIO_ADVCFGRH_DE14             (0x2UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x02000000 */
+#define GPIO_ADVCFGRH_INVCLK14         (0x4UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x04000000 */
+#define GPIO_ADVCFGRH_RET14            (0x8UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x08000000 */
+#define GPIO_ADVCFGRH_15_Pos           (28U)
+#define GPIO_ADVCFGRH_15_Msk           (0xFUL << GPIO_ADVCFGRH_15_Pos)         /*!< 0xF0000000 */
+#define GPIO_ADVCFGRH_15               GPIO_ADVCFGRH_15_Msk
+#define GPIO_ADVCFGRH_DLYPATH15        (0x1UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x10000000 */
+#define GPIO_ADVCFGRH_DE15             (0x2UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x20000000 */
+#define GPIO_ADVCFGRH_INVCLK15         (0x4UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x40000000 */
+#define GPIO_ADVCFGRH_RET15            (0x8UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x80000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT_Pos                    (2U)
+#define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
+#define HASH_CR_INIT                        HASH_CR_INIT_Msk
+#define HASH_CR_DMAE_Pos                    (3U)
+#define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
+#define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
+#define HASH_CR_DATATYPE_Pos                (4U)
+#define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
+#define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
+#define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos                    (6U)
+#define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
+#define HASH_CR_MODE                        HASH_CR_MODE_Msk
+#define HASH_CR_NBW_Pos                     (8U)
+#define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
+#define HASH_CR_NBW                         HASH_CR_NBW_Msk
+#define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
+#define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
+#define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
+#define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos                   (12U)
+#define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
+#define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
+#define HASH_CR_MDMAT_Pos                   (13U)
+#define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
+#define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
+#define HASH_CR_LKEY_Pos                    (16U)
+#define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
+#define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
+#define HASH_CR_ALGO_Pos                    (17U)
+#define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
+#define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
+#define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
+#define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
+#define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
+#define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBLW_Pos                   (0U)
+#define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
+#define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
+#define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
+#define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
+#define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
+#define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
+#define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos                   (8U)
+#define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
+#define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIE_Pos                  (0U)
+#define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
+#define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
+#define HASH_IMR_DCIE_Pos                   (1U)
+#define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
+#define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS_Pos                   (0U)
+#define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
+#define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
+#define HASH_SR_DCIS_Pos                    (1U)
+#define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
+#define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
+#define HASH_SR_DMAS_Pos                    (2U)
+#define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
+#define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
+#define HASH_SR_BUSY_Pos                    (3U)
+#define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
+#define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
+#define HASH_SR_NBWE_Pos                    (16U)
+#define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
+#define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
+#define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
+#define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
+#define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
+#define HASH_SR_DINNE_Pos                   (15U)
+#define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
+#define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
+#define HASH_SR_NBWP_Pos                    (9U)
+#define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
+#define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
+#define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
+#define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
+#define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos                      (0U)
+#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
+#define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos                    (1U)
+#define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
+#define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos                    (2U)
+#define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
+#define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos                  (3U)
+#define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos                  (4U)
+#define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
+#define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos                  (5U)
+#define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
+#define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos                    (6U)
+#define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos                   (7U)
+#define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos                     (8U)
+#define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
+#define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos                  (12U)
+#define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos                   (13U)
+#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
+#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos                 (14U)
+#define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos                 (15U)
+#define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos                     (16U)
+#define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
+#define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos               (17U)
+#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos                   (18U)
+#define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos                    (19U)
+#define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
+#define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos                  (20U)
+#define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos                  (21U)
+#define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos                 (22U)
+#define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos                   (23U)
+#define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
+#define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
+#define I2C_CR1_FMP_Pos                     (24U)
+#define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
+#define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
+#define I2C_CR1_ADDRACLR_Pos                (30U)
+#define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
+#define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
+#define I2C_CR1_STOPFACLR_Pos               (31U)
+#define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
+#define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos                    (0U)
+#define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
+#define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos                  (10U)
+#define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos                   (11U)
+#define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
+#define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos                 (12U)
+#define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos                   (13U)
+#define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
+#define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
+#define I2C_CR2_STOP_Pos                    (14U)
+#define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
+#define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos                    (15U)
+#define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
+#define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos                  (16U)
+#define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos                  (24U)
+#define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
+#define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos                 (25U)
+#define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos                 (26U)
+#define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos                    (0U)
+#define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
+#define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos                (10U)
+#define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos                  (15U)
+#define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos                    (1U)
+#define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
+#define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos                 (8U)
+#define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos              (8U)
+#define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos              (9U)
+#define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos              (8U)
+#define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos              (10U)
+#define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos              (8U)
+#define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos              (9U)
+#define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos              (8U)
+#define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos                  (15U)
+#define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos                (0U)
+#define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos                (8U)
+#define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos              (16U)
+#define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos              (20U)
+#define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos               (28U)
+#define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos              (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos                     (0U)
+#define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
+#define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos                    (1U)
+#define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
+#define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos                    (2U)
+#define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
+#define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos                    (3U)
+#define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
+#define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos                   (4U)
+#define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
+#define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos                   (5U)
+#define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
+#define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos                      (6U)
+#define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
+#define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos                     (7U)
+#define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
+#define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos                    (8U)
+#define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
+#define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
+#define I2C_ISR_ARLO_Pos                    (9U)
+#define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
+#define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos                     (10U)
+#define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
+#define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos                  (11U)
+#define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
+#define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos                 (12U)
+#define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos                   (13U)
+#define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
+#define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos                    (15U)
+#define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
+#define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
+#define I2C_ISR_DIR_Pos                     (16U)
+#define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
+#define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos                 (17U)
+#define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos                  (3U)
+#define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos                  (4U)
+#define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
+#define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos                  (5U)
+#define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
+#define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos                  (8U)
+#define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
+#define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos                  (9U)
+#define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos                   (10U)
+#define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos                   (11U)
+#define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
+#define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos                (12U)
+#define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos                 (13U)
+#define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos                    (0U)
+#define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
+#define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos                 (0U)
+#define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos                 (0U)
+#define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Improved Inter-integrated Circuit Interface (I3C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I3C_CR register  *********************/
+#define I3C_CR_DCNT_Pos                     (0U)
+#define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
+#define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
+#define I3C_CR_RNW_Pos                      (16U)
+#define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
+#define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
+#define I3C_CR_CCC_Pos                      (16U)
+#define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
+#define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
+#define I3C_CR_ADD_Pos                      (17U)
+#define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
+#define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
+#define I3C_CR_MTYPE_Pos                    (27U)
+#define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
+#define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
+#define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
+#define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
+#define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
+#define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
+#define I3C_CR_MEND_Pos                     (31U)
+#define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
+#define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
+
+/*******************  Bit definition for I3C_CFGR register  *******************/
+#define I3C_CFGR_EN_Pos                     (0U)
+#define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
+#define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
+#define I3C_CFGR_CRINIT_Pos                 (1U)
+#define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
+#define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
+#define I3C_CFGR_NOARBH_Pos                 (2U)
+#define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
+#define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
+#define I3C_CFGR_RSTPTRN_Pos                (3U)
+#define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
+#define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
+#define I3C_CFGR_EXITPTRN_Pos               (4U)
+#define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
+#define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
+#define I3C_CFGR_HKSDAEN_Pos                (5U)
+#define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
+#define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
+#define I3C_CFGR_HJACK_Pos                  (7U)
+#define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
+#define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
+#define I3C_CFGR_RXDMAEN_Pos                (8U)
+#define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
+#define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
+#define I3C_CFGR_RXFLUSH_Pos                (9U)
+#define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
+#define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
+#define I3C_CFGR_RXTHRES_Pos                (10U)
+#define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
+#define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
+#define I3C_CFGR_TXDMAEN_Pos                (12U)
+#define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
+#define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
+#define I3C_CFGR_TXFLUSH_Pos                (13U)
+#define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
+#define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
+#define I3C_CFGR_TXTHRES_Pos                (14U)
+#define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
+#define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
+#define I3C_CFGR_SDMAEN_Pos                 (16U)
+#define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
+#define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
+#define I3C_CFGR_SFLUSH_Pos                 (17U)
+#define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
+#define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
+#define I3C_CFGR_SMODE_Pos                  (18U)
+#define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
+#define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
+#define I3C_CFGR_TMODE_Pos                  (19U)
+#define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
+#define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
+#define I3C_CFGR_CDMAEN_Pos                 (20U)
+#define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
+#define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
+#define I3C_CFGR_CFLUSH_Pos                 (21U)
+#define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
+#define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
+#define I3C_CFGR_TSFSET_Pos                 (30U)
+#define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
+#define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
+
+/*******************  Bit definition for I3C_RDR register  ********************/
+#define I3C_RDR_RDB0_Pos                    (0U)
+#define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
+#define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
+
+/******************  Bit definition for I3C_RDWR register  ********************/
+#define I3C_RDWR_RDBx_Pos                   (0U)
+#define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
+#define I3C_RDWR_RDB0_Pos                   (0U)
+#define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
+#define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
+#define I3C_RDWR_RDB1_Pos                   (8U)
+#define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
+#define I3C_RDWR_RDB2_Pos                   (16U)
+#define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
+#define I3C_RDWR_RDB3_Pos                   (24U)
+#define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
+
+/*******************  Bit definition for I3C_TDR register  ********************/
+#define I3C_TDR_TDB0_Pos                    (0U)
+#define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
+#define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
+
+/******************  Bit definition for I3C_TDWR register  ********************/
+#define I3C_TDWR_TDBx_Pos                   (0U)
+#define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
+#define I3C_TDWR_TDB0_Pos                   (0U)
+#define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
+#define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
+#define I3C_TDWR_TDB1_Pos                   (8U)
+#define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
+#define I3C_TDWR_TDB2_Pos                   (16U)
+#define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
+#define I3C_TDWR_TDB3_Pos                   (24U)
+#define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
+
+/*******************  Bit definition for I3C_IBIDR register  ******************/
+#define I3C_IBIDR_IBIDBx_Pos                (0U)
+#define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
+#define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
+#define I3C_IBIDR_IBIDB0_Pos                (0U)
+#define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
+#define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
+#define I3C_IBIDR_IBIDB1_Pos                (8U)
+#define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
+#define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
+#define I3C_IBIDR_IBIDB2_Pos                (16U)
+#define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
+#define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
+#define I3C_IBIDR_IBIDB3_Pos                (24U)
+#define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
+#define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
+
+/******************  Bit definition for I3C_TGTTDR register  ******************/
+#define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
+#define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
+#define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
+#define I3C_TGTTDR_PRELOAD_Pos              (16U)
+#define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
+#define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
+
+/*******************  Bit definition for I3C_SR register  *********************/
+#define I3C_SR_XDCNT_Pos                    (0U)
+#define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
+#define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
+#define I3C_SR_ABT_Pos                      (17U)
+#define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
+#define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
+#define I3C_SR_DIR_Pos                      (18U)
+#define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
+#define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
+#define I3C_SR_MID_Pos                      (24U)
+#define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
+#define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
+
+/*******************  Bit definition for I3C_SER register  ********************/
+#define I3C_SER_CODERR_Pos                  (0U)
+#define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
+#define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
+#define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
+#define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
+#define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
+#define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
+#define I3C_SER_PERR_Pos                    (4U)
+#define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
+#define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
+#define I3C_SER_STALL_Pos                   (5U)
+#define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
+#define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
+#define I3C_SER_DOVR_Pos                    (6U)
+#define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
+#define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
+#define I3C_SER_COVR_Pos                    (7U)
+#define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
+#define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
+#define I3C_SER_ANACK_Pos                   (8U)
+#define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
+#define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
+#define I3C_SER_DNACK_Pos                   (9U)
+#define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
+#define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
+#define I3C_SER_DERR_Pos                    (10U)
+#define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
+#define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
+
+/*******************  Bit definition for I3C_RMR register  ********************/
+#define I3C_RMR_IBIRDCNT_Pos                (0U)
+#define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
+#define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
+#define I3C_RMR_RCODE_Pos                   (8U)
+#define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
+#define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
+#define I3C_RMR_RADD_Pos                    (17U)
+#define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
+#define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
+
+/*******************  Bit definition for I3C_EVR register  ********************/
+#define I3C_EVR_CFEF_Pos                    (0U)
+#define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
+#define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
+#define I3C_EVR_TXFEF_Pos                   (1U)
+#define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
+#define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
+#define I3C_EVR_CFNFF_Pos                   (2U)
+#define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
+#define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
+#define I3C_EVR_SFNEF_Pos                   (3U)
+#define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
+#define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
+#define I3C_EVR_TXFNFF_Pos                  (4U)
+#define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
+#define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
+#define I3C_EVR_RXFNEF_Pos                  (5U)
+#define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
+#define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
+#define I3C_EVR_TXLASTF_Pos                 (6U)
+#define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
+#define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
+#define I3C_EVR_RXLASTF_Pos                 (7U)
+#define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
+#define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
+#define I3C_EVR_FCF_Pos                     (9U)
+#define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
+#define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
+#define I3C_EVR_RXTGTENDF_Pos               (10U)
+#define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
+#define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
+#define I3C_EVR_ERRF_Pos                    (11U)
+#define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
+#define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
+#define I3C_EVR_IBIF_Pos                    (15U)
+#define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
+#define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
+#define I3C_EVR_IBIENDF_Pos                 (16U)
+#define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
+#define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
+#define I3C_EVR_CRF_Pos                     (17U)
+#define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
+#define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
+#define I3C_EVR_CRUPDF_Pos                  (18U)
+#define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
+#define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
+#define I3C_EVR_HJF_Pos                     (19U)
+#define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
+#define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
+#define I3C_EVR_WKPF_Pos                    (21U)
+#define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
+#define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
+#define I3C_EVR_GETF_Pos                    (22U)
+#define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
+#define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
+#define I3C_EVR_STAF_Pos                    (23U)
+#define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
+#define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
+#define I3C_EVR_DAUPDF_Pos                  (24U)
+#define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
+#define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
+#define I3C_EVR_MWLUPDF_Pos                 (25U)
+#define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
+#define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
+#define I3C_EVR_MRLUPDF_Pos                 (26U)
+#define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
+#define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
+#define I3C_EVR_RSTF_Pos                    (27U)
+#define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
+#define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
+#define I3C_EVR_ASUPDF_Pos                  (28U)
+#define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
+#define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
+#define I3C_EVR_INTUPDF_Pos                 (29U)
+#define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
+#define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
+#define I3C_EVR_DEFF_Pos                    (30U)
+#define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
+#define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
+#define I3C_EVR_GRPF_Pos                    (31U)
+#define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
+#define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
+
+/*******************  Bit definition for I3C_IER register  ********************/
+#define I3C_IER_CFNFIE_Pos                  (2U)
+#define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
+#define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
+#define I3C_IER_SFNEIE_Pos                  (3U)
+#define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
+#define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
+#define I3C_IER_TXFNFIE_Pos                 (4U)
+#define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
+#define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
+#define I3C_IER_RXFNEIE_Pos                 (5U)
+#define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
+#define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
+#define I3C_IER_FCIE_Pos                    (9U)
+#define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
+#define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
+#define I3C_IER_RXTGTENDIE_Pos              (10U)
+#define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
+#define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
+#define I3C_IER_ERRIE_Pos                   (11U)
+#define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
+#define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
+#define I3C_IER_IBIIE_Pos                   (15U)
+#define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
+#define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
+#define I3C_IER_IBIENDIE_Pos                (16U)
+#define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
+#define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
+#define I3C_IER_CRIE_Pos                    (17U)
+#define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
+#define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
+#define I3C_IER_CRUPDIE_Pos                 (18U)
+#define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
+#define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
+#define I3C_IER_HJIE_Pos                    (19U)
+#define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
+#define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
+#define I3C_IER_WKPIE_Pos                   (21U)
+#define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
+#define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
+#define I3C_IER_GETIE_Pos                   (22U)
+#define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
+#define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
+#define I3C_IER_STAIE_Pos                   (23U)
+#define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
+#define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
+#define I3C_IER_DAUPDIE_Pos                 (24U)
+#define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
+#define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
+#define I3C_IER_MWLUPDIE_Pos                (25U)
+#define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
+#define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
+#define I3C_IER_MRLUPDIE_Pos                (26U)
+#define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
+#define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
+#define I3C_IER_RSTIE_Pos                   (27U)
+#define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
+#define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
+#define I3C_IER_ASUPDIE_Pos                 (28U)
+#define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
+#define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
+#define I3C_IER_INTUPDIE_Pos                (29U)
+#define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
+#define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
+#define I3C_IER_DEFIE_Pos                   (30U)
+#define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
+#define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
+#define I3C_IER_GRPIE_Pos                   (31U)
+#define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
+#define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
+
+/*******************  Bit definition for I3C_CEVR register  *******************/
+#define I3C_CEVR_CFCF_Pos                   (9U)
+#define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
+#define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
+#define I3C_CEVR_CRXTGTENDF_Pos             (10U)
+#define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
+#define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
+#define I3C_CEVR_CERRF_Pos                  (11U)
+#define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
+#define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
+#define I3C_CEVR_CIBIF_Pos                  (15U)
+#define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
+#define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
+#define I3C_CEVR_CIBIENDF_Pos               (16U)
+#define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
+#define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
+#define I3C_CEVR_CCRF_Pos                   (17U)
+#define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
+#define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
+#define I3C_CEVR_CCRUPDF_Pos                (18U)
+#define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
+#define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
+#define I3C_CEVR_CHJF_Pos                   (19U)
+#define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
+#define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
+#define I3C_CEVR_CWKPF_Pos                  (21U)
+#define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
+#define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
+#define I3C_CEVR_CGETF_Pos                  (22U)
+#define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
+#define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
+#define I3C_CEVR_CSTAF_Pos                  (23U)
+#define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
+#define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
+#define I3C_CEVR_CDAUPDF_Pos                (24U)
+#define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
+#define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
+#define I3C_CEVR_CMWLUPDF_Pos               (25U)
+#define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
+#define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
+#define I3C_CEVR_CMRLUPDF_Pos               (26U)
+#define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
+#define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
+#define I3C_CEVR_CRSTF_Pos                  (27U)
+#define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
+#define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
+#define I3C_CEVR_CASUPDF_Pos                (28U)
+#define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
+#define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
+#define I3C_CEVR_CINTUPDF_Pos               (29U)
+#define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
+#define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
+#define I3C_CEVR_CDEFF_Pos                  (30U)
+#define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
+#define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
+#define I3C_CEVR_CGRPF_Pos                  (31U)
+#define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
+#define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
+
+/******************  Bit definition for I3C_DEVR0 register  *******************/
+#define I3C_DEVR0_DAVAL_Pos                 (0U)
+#define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
+#define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
+#define I3C_DEVR0_DA_Pos                    (1U)
+#define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
+#define I3C_DEVR0_IBIEN_Pos                 (16U)
+#define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
+#define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
+#define I3C_DEVR0_CREN_Pos                  (17U)
+#define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
+#define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
+#define I3C_DEVR0_HJEN_Pos                  (19U)
+#define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
+#define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
+#define I3C_DEVR0_AS_Pos                    (20U)
+#define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
+#define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
+#define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
+#define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
+#define I3C_DEVR0_RSTACT_Pos                (22U)
+#define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
+#define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
+#define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
+#define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
+#define I3C_DEVR0_RSTVAL_Pos                (24U)
+#define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
+#define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
+
+/******************  Bit definition for I3C_DEVRX register  *******************/
+#define I3C_DEVRX_DA_Pos                    (1U)
+#define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
+#define I3C_DEVRX_IBIACK_Pos                (16U)
+#define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
+#define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
+#define I3C_DEVRX_CRACK_Pos                 (17U)
+#define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
+#define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
+#define I3C_DEVRX_IBIDEN_Pos                (18U)
+#define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
+#define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
+#define I3C_DEVRX_SUSP_Pos                  (19U)
+#define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
+#define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
+#define I3C_DEVRX_DIS_Pos                   (31U)
+#define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
+#define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
+
+/******************  Bit definition for I3C_MAXRLR register  ******************/
+#define I3C_MAXRLR_MRL_Pos                  (0U)
+#define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
+#define I3C_MAXRLR_IBIP_Pos                 (16U)
+#define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
+#define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
+#define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
+#define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
+#define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
+
+/******************  Bit definition for I3C_MAXWLR register  ******************/
+#define I3C_MAXWLR_MWL_Pos                  (0U)
+#define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
+
+/****************  Bit definition for I3C_TIMINGR0 register  ******************/
+#define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
+#define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
+#define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
+#define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
+#define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
+#define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
+#define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
+#define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
+#define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
+#define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
+#define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
+#define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
+
+/****************  Bit definition for I3C_TIMINGR1 register  ******************/
+#define I3C_TIMINGR1_AVAL_Pos               (0U)
+#define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
+#define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
+#define I3C_TIMINGR1_ASNCR_Pos              (8U)
+#define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
+#define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
+#define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
+#define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
+#define I3C_TIMINGR1_FREE_Pos               (16U)
+#define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
+#define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
+#define I3C_TIMINGR1_SDA_HD_Pos             (28U)
+#define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
+#define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
+
+/****************  Bit definition for I3C_TIMINGR2 register  ******************/
+#define I3C_TIMINGR2_STALLT_Pos             (0U)
+#define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x0000001 */
+#define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
+#define I3C_TIMINGR2_STALLD_Pos             (1U)
+#define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x0000002 */
+#define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
+#define I3C_TIMINGR2_STALLC_Pos             (2U)
+#define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x0000004 */
+#define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
+#define I3C_TIMINGR2_STALLA_Pos             (3U)
+#define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x0000008 */
+#define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
+#define I3C_TIMINGR2_STALL_Pos              (8U)
+#define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x000FF00 */
+#define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
+
+/*******************  Bit definition for I3C_BCR register  ********************/
+#define I3C_BCR_BCR_Pos                     (0U)
+#define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
+#define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
+#define I3C_BCR_BCR0_Pos                    (0U)
+#define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
+#define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
+#define I3C_BCR_BCR1_Pos                    (1U)
+#define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
+#define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
+#define I3C_BCR_BCR2_Pos                    (2U)
+#define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
+#define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
+#define I3C_BCR_BCR3_Pos                    (3U)
+#define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
+#define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
+#define I3C_BCR_BCR4_Pos                    (4U)
+#define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
+#define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
+#define I3C_BCR_BCR5_Pos                    (5U)
+#define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
+#define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
+#define I3C_BCR_BCR6_Pos                    (6U)
+#define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
+#define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
+
+/*******************  Bit definition for I3C_DCR register  ********************/
+#define I3C_DCR_DCR_Pos                     (0U)
+#define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x00000FF */
+#define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
+
+/*****************  Bit definition for I3C_GETCAPR register  ******************/
+#define I3C_GETCAPR_CAPPEND_Pos             (14U)
+#define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
+#define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
+
+/*****************  Bit definition for I3C_CRCAPR register  *******************/
+#define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
+#define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
+#define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
+#define I3C_CRCAPR_CAPGRP_Pos               (9U)
+#define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
+#define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
+
+/****************  Bit definition for I3C_GETMXDSR register  ******************/
+#define I3C_GETMXDSR_HOFFAS_Pos             (0U)
+#define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
+#define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
+#define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
+#define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
+#define I3C_GETMXDSR_FMT_Pos                (8U)
+#define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
+#define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
+#define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
+#define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
+#define I3C_GETMXDSR_RDTURN_Pos             (16U)
+#define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
+#define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
+#define I3C_GETMXDSR_TSCO_Pos               (24U)
+#define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
+#define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
+
+/******************  Bit definition for I3C_EPIDR register  *******************/
+#define I3C_EPIDR_MIPIID_Pos                (12U)
+#define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
+#define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
+#define I3C_EPIDR_IDTSEL_Pos                (16U)
+#define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
+#define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
+#define I3C_EPIDR_MIPIMID_Pos               (17U)
+#define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
+#define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Illegal Access Controller (IAC)                                */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for IAC_IER0 register *******************/
+#define IAC_IER0_IAIE0_Pos            (0U)
+#define IAC_IER0_IAIE0_Msk            (0x1UL << IAC_IER0_IAIE0_Pos)              /*!< 0x00000001 */
+#define IAC_IER0_IAIE0                IAC_IER0_IAIE0_Msk
+#define IAC_IER0_IAIE1_Pos            (1U)
+#define IAC_IER0_IAIE1_Msk            (0x1UL << IAC_IER0_IAIE1_Pos)              /*!< 0x00000002 */
+#define IAC_IER0_IAIE1                IAC_IER0_IAIE1_Msk
+#define IAC_IER0_IAIE2_Pos            (2U)
+#define IAC_IER0_IAIE2_Msk            (0x1UL << IAC_IER0_IAIE2_Pos)              /*!< 0x00000004 */
+#define IAC_IER0_IAIE2                IAC_IER0_IAIE2_Msk
+#define IAC_IER0_IAIE3_Pos            (3U)
+#define IAC_IER0_IAIE3_Msk            (0x1UL << IAC_IER0_IAIE3_Pos)              /*!< 0x00000008 */
+#define IAC_IER0_IAIE3                IAC_IER0_IAIE3_Msk
+#define IAC_IER0_IAIE4_Pos            (4U)
+#define IAC_IER0_IAIE4_Msk            (0x1UL << IAC_IER0_IAIE4_Pos)              /*!< 0x00000010 */
+#define IAC_IER0_IAIE4                IAC_IER0_IAIE4_Msk
+#define IAC_IER0_IAIE5_Pos            (5U)
+#define IAC_IER0_IAIE5_Msk            (0x1UL << IAC_IER0_IAIE5_Pos)              /*!< 0x00000020 */
+#define IAC_IER0_IAIE5                IAC_IER0_IAIE5_Msk
+#define IAC_IER0_IAIE6_Pos            (6U)
+#define IAC_IER0_IAIE6_Msk            (0x1UL << IAC_IER0_IAIE6_Pos)              /*!< 0x00000040 */
+#define IAC_IER0_IAIE6                IAC_IER0_IAIE6_Msk
+#define IAC_IER0_IAIE8_Pos            (8U)
+#define IAC_IER0_IAIE8_Msk            (0x1UL << IAC_IER0_IAIE8_Pos)              /*!< 0x00000100 */
+#define IAC_IER0_IAIE8                IAC_IER0_IAIE8_Msk
+#define IAC_IER0_IAIE9_Pos            (9U)
+#define IAC_IER0_IAIE9_Msk            (0x1UL << IAC_IER0_IAIE9_Pos)              /*!< 0x00000200 */
+#define IAC_IER0_IAIE9                IAC_IER0_IAIE9_Msk
+#define IAC_IER0_IAIE10_Pos           (10U)
+#define IAC_IER0_IAIE10_Msk           (0x1UL << IAC_IER0_IAIE10_Pos)             /*!< 0x00000400 */
+#define IAC_IER0_IAIE10               IAC_IER0_IAIE10_Msk
+#define IAC_IER0_IAIE11_Pos           (11U)
+#define IAC_IER0_IAIE11_Msk           (0x1UL << IAC_IER0_IAIE11_Pos)             /*!< 0x00000800 */
+#define IAC_IER0_IAIE11               IAC_IER0_IAIE11_Msk
+#define IAC_IER0_IAIE12_Pos           (12U)
+#define IAC_IER0_IAIE12_Msk           (0x1UL << IAC_IER0_IAIE12_Pos)             /*!< 0x00001000 */
+#define IAC_IER0_IAIE12               IAC_IER0_IAIE12_Msk
+#define IAC_IER0_IAIE13_Pos           (13U)
+#define IAC_IER0_IAIE13_Msk           (0x1UL << IAC_IER0_IAIE13_Pos)             /*!< 0x00002000 */
+#define IAC_IER0_IAIE13               IAC_IER0_IAIE13_Msk
+#define IAC_IER0_IAIE14_Pos           (14U)
+#define IAC_IER0_IAIE14_Msk           (0x1UL << IAC_IER0_IAIE14_Pos)             /*!< 0x00004000 */
+#define IAC_IER0_IAIE14               IAC_IER0_IAIE14_Msk
+#define IAC_IER0_IAIE15_Pos           (15U)
+#define IAC_IER0_IAIE15_Msk           (0x1UL << IAC_IER0_IAIE15_Pos)             /*!< 0x00008000 */
+#define IAC_IER0_IAIE15               IAC_IER0_IAIE15_Msk
+#define IAC_IER0_IAIE16_Pos           (16U)
+#define IAC_IER0_IAIE16_Msk           (0x1UL << IAC_IER0_IAIE16_Pos)             /*!< 0x00010000 */
+#define IAC_IER0_IAIE16               IAC_IER0_IAIE16_Msk
+#define IAC_IER0_IAIE17_Pos           (17U)
+#define IAC_IER0_IAIE17_Msk           (0x1UL << IAC_IER0_IAIE17_Pos)             /*!< 0x00020000 */
+#define IAC_IER0_IAIE17               IAC_IER0_IAIE17_Msk
+#define IAC_IER0_IAIE18_Pos           (18U)
+#define IAC_IER0_IAIE18_Msk           (0x1UL << IAC_IER0_IAIE18_Pos)             /*!< 0x00040000 */
+#define IAC_IER0_IAIE18               IAC_IER0_IAIE18_Msk
+#define IAC_IER0_IAIE19_Pos           (19U)
+#define IAC_IER0_IAIE19_Msk           (0x1UL << IAC_IER0_IAIE19_Pos)             /*!< 0x00080000 */
+#define IAC_IER0_IAIE19               IAC_IER0_IAIE19_Msk
+#define IAC_IER0_IAIE20_Pos           (20U)
+#define IAC_IER0_IAIE20_Msk           (0x1UL << IAC_IER0_IAIE20_Pos)             /*!< 0x00100000 */
+#define IAC_IER0_IAIE20               IAC_IER0_IAIE20_Msk
+#define IAC_IER0_IAIE21_Pos           (21U)
+#define IAC_IER0_IAIE21_Msk           (0x1UL << IAC_IER0_IAIE21_Pos)             /*!< 0x00200000 */
+#define IAC_IER0_IAIE21               IAC_IER0_IAIE21_Msk
+#define IAC_IER0_IAIE22_Pos           (22U)
+#define IAC_IER0_IAIE22_Msk           (0x1UL << IAC_IER0_IAIE22_Pos)             /*!< 0x00400000 */
+#define IAC_IER0_IAIE22               IAC_IER0_IAIE22_Msk
+#define IAC_IER0_IAIE23_Pos           (23U)
+#define IAC_IER0_IAIE23_Msk           (0x1UL << IAC_IER0_IAIE23_Pos)             /*!< 0x00800000 */
+#define IAC_IER0_IAIE23               IAC_IER0_IAIE23_Msk
+#define IAC_IER0_IAIE24_Pos           (24U)
+#define IAC_IER0_IAIE24_Msk           (0x1UL << IAC_IER0_IAIE24_Pos)             /*!< 0x01000000 */
+#define IAC_IER0_IAIE24               IAC_IER0_IAIE24_Msk
+#define IAC_IER0_IAIE25_Pos           (25U)
+#define IAC_IER0_IAIE25_Msk           (0x1UL << IAC_IER0_IAIE25_Pos)             /*!< 0x02000000 */
+#define IAC_IER0_IAIE25               IAC_IER0_IAIE25_Msk
+#define IAC_IER0_IAIE26_Pos           (26U)
+#define IAC_IER0_IAIE26_Msk           (0x1UL << IAC_IER0_IAIE26_Pos)             /*!< 0x04000000 */
+#define IAC_IER0_IAIE26               IAC_IER0_IAIE26_Msk
+#define IAC_IER0_IAIE27_Pos           (27U)
+#define IAC_IER0_IAIE27_Msk           (0x1UL << IAC_IER0_IAIE27_Pos)             /*!< 0x08000000 */
+#define IAC_IER0_IAIE27               IAC_IER0_IAIE27_Msk
+#define IAC_IER0_IAIE28_Pos           (28U)
+#define IAC_IER0_IAIE28_Msk           (0x1UL << IAC_IER0_IAIE28_Pos)             /*!< 0x10000000 */
+#define IAC_IER0_IAIE28               IAC_IER0_IAIE28_Msk
+#define IAC_IER0_IAIE29_Pos           (29U)
+#define IAC_IER0_IAIE29_Msk           (0x1UL << IAC_IER0_IAIE29_Pos)             /*!< 0x20000000 */
+#define IAC_IER0_IAIE29               IAC_IER0_IAIE29_Msk
+#define IAC_IER0_IAIE30_Pos           (30U)
+#define IAC_IER0_IAIE30_Msk           (0x1UL << IAC_IER0_IAIE30_Pos)             /*!< 0x40000000 */
+#define IAC_IER0_IAIE30               IAC_IER0_IAIE30_Msk
+#define IAC_IER0_IAIE31_Pos           (31U)
+#define IAC_IER0_IAIE31_Msk           (0x1UL << IAC_IER0_IAIE31_Pos)             /*!< 0x80000000 */
+#define IAC_IER0_IAIE31               IAC_IER0_IAIE31_Msk
+
+/*******************  Bits definition for IAC_IER1 register *******************/
+#define IAC_IER1_IAIE32_Pos           (0U)
+#define IAC_IER1_IAIE32_Msk           (0x1UL << IAC_IER1_IAIE32_Pos)             /*!< 0x00000001 */
+#define IAC_IER1_IAIE32               IAC_IER1_IAIE32_Msk
+#define IAC_IER1_IAIE33_Pos           (1U)
+#define IAC_IER1_IAIE33_Msk           (0x1UL << IAC_IER1_IAIE33_Pos)             /*!< 0x00000002 */
+#define IAC_IER1_IAIE33               IAC_IER1_IAIE33_Msk
+#define IAC_IER1_IAIE34_Pos           (2U)
+#define IAC_IER1_IAIE34_Msk           (0x1UL << IAC_IER1_IAIE34_Pos)             /*!< 0x00000004 */
+#define IAC_IER1_IAIE34               IAC_IER1_IAIE34_Msk
+#define IAC_IER1_IAIE35_Pos           (3U)
+#define IAC_IER1_IAIE35_Msk           (0x1UL << IAC_IER1_IAIE35_Pos)             /*!< 0x00000008 */
+#define IAC_IER1_IAIE35               IAC_IER1_IAIE35_Msk
+#define IAC_IER1_IAIE36_Pos           (4U)
+#define IAC_IER1_IAIE36_Msk           (0x1UL << IAC_IER1_IAIE36_Pos)             /*!< 0x00000010 */
+#define IAC_IER1_IAIE36               IAC_IER1_IAIE36_Msk
+#define IAC_IER1_IAIE37_Pos           (5U)
+#define IAC_IER1_IAIE37_Msk           (0x1UL << IAC_IER1_IAIE37_Pos)             /*!< 0x00000020 */
+#define IAC_IER1_IAIE37               IAC_IER1_IAIE37_Msk
+#define IAC_IER1_IAIE38_Pos           (6U)
+#define IAC_IER1_IAIE38_Msk           (0x1UL << IAC_IER1_IAIE38_Pos)             /*!< 0x00000040 */
+#define IAC_IER1_IAIE38               IAC_IER1_IAIE38_Msk
+#define IAC_IER1_IAIE39_Pos           (7U)
+#define IAC_IER1_IAIE39_Msk           (0x1UL << IAC_IER1_IAIE39_Pos)             /*!< 0x00000080 */
+#define IAC_IER1_IAIE39               IAC_IER1_IAIE39_Msk
+#define IAC_IER1_IAIE40_Pos           (8U)
+#define IAC_IER1_IAIE40_Msk           (0x1UL << IAC_IER1_IAIE40_Pos)             /*!< 0x00000100 */
+#define IAC_IER1_IAIE40               IAC_IER1_IAIE40_Msk
+#define IAC_IER1_IAIE41_Pos           (9U)
+#define IAC_IER1_IAIE41_Msk           (0x1UL << IAC_IER1_IAIE41_Pos)             /*!< 0x00000200 */
+#define IAC_IER1_IAIE41               IAC_IER1_IAIE41_Msk
+#define IAC_IER1_IAIE42_Pos           (10U)
+#define IAC_IER1_IAIE42_Msk           (0x1UL << IAC_IER1_IAIE42_Pos)             /*!< 0x00000400 */
+#define IAC_IER1_IAIE42               IAC_IER1_IAIE42_Msk
+#define IAC_IER1_IAIE43_Pos           (11U)
+#define IAC_IER1_IAIE43_Msk           (0x1UL << IAC_IER1_IAIE43_Pos)             /*!< 0x00000800 */
+#define IAC_IER1_IAIE43               IAC_IER1_IAIE43_Msk
+#define IAC_IER1_IAIE44_Pos           (12U)
+#define IAC_IER1_IAIE44_Msk           (0x1UL << IAC_IER1_IAIE44_Pos)             /*!< 0x00001000 */
+#define IAC_IER1_IAIE44               IAC_IER1_IAIE44_Msk
+#define IAC_IER1_IAIE45_Pos           (13U)
+#define IAC_IER1_IAIE45_Msk           (0x1UL << IAC_IER1_IAIE45_Pos)             /*!< 0x00002000 */
+#define IAC_IER1_IAIE45               IAC_IER1_IAIE45_Msk
+#define IAC_IER1_IAIE46_Pos           (14U)
+#define IAC_IER1_IAIE46_Msk           (0x1UL << IAC_IER1_IAIE46_Pos)             /*!< 0x00004000 */
+#define IAC_IER1_IAIE46               IAC_IER1_IAIE46_Msk
+#define IAC_IER1_IAIE47_Pos           (15U)
+#define IAC_IER1_IAIE47_Msk           (0x1UL << IAC_IER1_IAIE47_Pos)             /*!< 0x00008000 */
+#define IAC_IER1_IAIE47               IAC_IER1_IAIE47_Msk
+#define IAC_IER1_IAIE48_Pos           (16U)
+#define IAC_IER1_IAIE48_Msk           (0x1UL << IAC_IER1_IAIE48_Pos)             /*!< 0x00010000 */
+#define IAC_IER1_IAIE48               IAC_IER1_IAIE48_Msk
+#define IAC_IER1_IAIE49_Pos           (17U)
+#define IAC_IER1_IAIE49_Msk           (0x1UL << IAC_IER1_IAIE49_Pos)             /*!< 0x00020000 */
+#define IAC_IER1_IAIE49               IAC_IER1_IAIE49_Msk
+#define IAC_IER1_IAIE50_Pos           (18U)
+#define IAC_IER1_IAIE50_Msk           (0x1UL << IAC_IER1_IAIE50_Pos)             /*!< 0x00040000 */
+#define IAC_IER1_IAIE50               IAC_IER1_IAIE50_Msk
+#define IAC_IER1_IAIE51_Pos           (19U)
+#define IAC_IER1_IAIE51_Msk           (0x1UL << IAC_IER1_IAIE51_Pos)             /*!< 0x00080000 */
+#define IAC_IER1_IAIE51               IAC_IER1_IAIE51_Msk
+#define IAC_IER1_IAIE52_Pos           (20U)
+#define IAC_IER1_IAIE52_Msk           (0x1UL << IAC_IER1_IAIE52_Pos)             /*!< 0x00100000 */
+#define IAC_IER1_IAIE52               IAC_IER1_IAIE52_Msk
+#define IAC_IER1_IAIE53_Pos           (21U)
+#define IAC_IER1_IAIE53_Msk           (0x1UL << IAC_IER1_IAIE53_Pos)             /*!< 0x00200000 */
+#define IAC_IER1_IAIE53               IAC_IER1_IAIE53_Msk
+#define IAC_IER1_IAIE54_Pos           (22U)
+#define IAC_IER1_IAIE54_Msk           (0x1UL << IAC_IER1_IAIE54_Pos)             /*!< 0x00400000 */
+#define IAC_IER1_IAIE54               IAC_IER1_IAIE54_Msk
+#define IAC_IER1_IAIE55_Pos           (23U)
+#define IAC_IER1_IAIE55_Msk           (0x1UL << IAC_IER1_IAIE55_Pos)             /*!< 0x00800000 */
+#define IAC_IER1_IAIE55               IAC_IER1_IAIE55_Msk
+#define IAC_IER1_IAIE56_Pos           (24U)
+#define IAC_IER1_IAIE56_Msk           (0x1UL << IAC_IER1_IAIE56_Pos)             /*!< 0x01000000 */
+#define IAC_IER1_IAIE56               IAC_IER1_IAIE56_Msk
+#define IAC_IER1_IAIE57_Pos           (25U)
+#define IAC_IER1_IAIE57_Msk           (0x1UL << IAC_IER1_IAIE57_Pos)             /*!< 0x02000000 */
+#define IAC_IER1_IAIE57               IAC_IER1_IAIE57_Msk
+#define IAC_IER1_IAIE58_Pos           (26U)
+#define IAC_IER1_IAIE58_Msk           (0x1UL << IAC_IER1_IAIE58_Pos)             /*!< 0x04000000 */
+#define IAC_IER1_IAIE58               IAC_IER1_IAIE58_Msk
+#define IAC_IER1_IAIE60_Pos           (28U)
+#define IAC_IER1_IAIE60_Msk           (0x1UL << IAC_IER1_IAIE60_Pos)             /*!< 0x10000000 */
+#define IAC_IER1_IAIE60               IAC_IER1_IAIE60_Msk
+#define IAC_IER1_IAIE61_Pos           (29U)
+#define IAC_IER1_IAIE61_Msk           (0x1UL << IAC_IER1_IAIE61_Pos)             /*!< 0x20000000 */
+#define IAC_IER1_IAIE61               IAC_IER1_IAIE61_Msk
+#define IAC_IER1_IAIE62_Pos           (30U)
+#define IAC_IER1_IAIE62_Msk           (0x1UL << IAC_IER1_IAIE62_Pos)             /*!< 0x40000000 */
+#define IAC_IER1_IAIE62               IAC_IER1_IAIE62_Msk
+
+/*******************  Bits definition for IAC_IER2 register *******************/
+#define IAC_IER2_IAIE64_Pos           (0U)
+#define IAC_IER2_IAIE64_Msk           (0x1UL << IAC_IER2_IAIE64_Pos)             /*!< 0x00000001 */
+#define IAC_IER2_IAIE64               IAC_IER2_IAIE64_Msk
+#define IAC_IER2_IAIE65_Pos           (1U)
+#define IAC_IER2_IAIE65_Msk           (0x1UL << IAC_IER2_IAIE65_Pos)             /*!< 0x00000002 */
+#define IAC_IER2_IAIE65               IAC_IER2_IAIE65_Msk
+#define IAC_IER2_IAIE67_Pos           (3U)
+#define IAC_IER2_IAIE67_Msk           (0x1UL << IAC_IER2_IAIE67_Pos)             /*!< 0x00000008 */
+#define IAC_IER2_IAIE67               IAC_IER2_IAIE67_Msk
+#define IAC_IER2_IAIE68_Pos           (4U)
+#define IAC_IER2_IAIE68_Msk           (0x1UL << IAC_IER2_IAIE68_Pos)             /*!< 0x00000010 */
+#define IAC_IER2_IAIE68               IAC_IER2_IAIE68_Msk
+#define IAC_IER2_IAIE69_Pos           (5U)
+#define IAC_IER2_IAIE69_Msk           (0x1UL << IAC_IER2_IAIE69_Pos)             /*!< 0x00000020 */
+#define IAC_IER2_IAIE69               IAC_IER2_IAIE69_Msk
+#define IAC_IER2_IAIE76_Pos           (12U)
+#define IAC_IER2_IAIE76_Msk           (0x1UL << IAC_IER2_IAIE76_Pos)             /*!< 0x00001000 */
+#define IAC_IER2_IAIE76               IAC_IER2_IAIE76_Msk
+#define IAC_IER2_IAIE77_Pos           (13U)
+#define IAC_IER2_IAIE77_Msk           (0x1UL << IAC_IER2_IAIE77_Pos)             /*!< 0x00002000 */
+#define IAC_IER2_IAIE77               IAC_IER2_IAIE77_Msk
+#define IAC_IER2_IAIE78_Pos           (14U)
+#define IAC_IER2_IAIE78_Msk           (0x1UL << IAC_IER2_IAIE78_Pos)             /*!< 0x00004000 */
+#define IAC_IER2_IAIE78               IAC_IER2_IAIE78_Msk
+#define IAC_IER2_IAIE79_Pos           (15U)
+#define IAC_IER2_IAIE79_Msk           (0x1UL << IAC_IER2_IAIE79_Pos)             /*!< 0x00008000 */
+#define IAC_IER2_IAIE79               IAC_IER2_IAIE79_Msk
+#define IAC_IER2_IAIE80_Pos           (16U)
+#define IAC_IER2_IAIE80_Msk           (0x1UL << IAC_IER2_IAIE80_Pos)             /*!< 0x00010000 */
+#define IAC_IER2_IAIE80               IAC_IER2_IAIE80_Msk
+#define IAC_IER2_IAIE81_Pos           (17U)
+#define IAC_IER2_IAIE81_Msk           (0x1UL << IAC_IER2_IAIE81_Pos)             /*!< 0x00020000 */
+#define IAC_IER2_IAIE81               IAC_IER2_IAIE81_Msk
+#define IAC_IER2_IAIE82_Pos           (18U)
+#define IAC_IER2_IAIE82_Msk           (0x1UL << IAC_IER2_IAIE82_Pos)             /*!< 0x00040000 */
+#define IAC_IER2_IAIE82               IAC_IER2_IAIE82_Msk
+#define IAC_IER2_IAIE83_Pos           (19U)
+#define IAC_IER2_IAIE83_Msk           (0x1UL << IAC_IER2_IAIE83_Pos)             /*!< 0x00080000 */
+#define IAC_IER2_IAIE83               IAC_IER2_IAIE83_Msk
+#define IAC_IER2_IAIE84_Pos           (20U)
+#define IAC_IER2_IAIE84_Msk           (0x1UL << IAC_IER2_IAIE84_Pos)             /*!< 0x00100000 */
+#define IAC_IER2_IAIE84               IAC_IER2_IAIE84_Msk
+#define IAC_IER2_IAIE86_Pos           (22U)
+#define IAC_IER2_IAIE86_Msk           (0x1UL << IAC_IER2_IAIE86_Pos)             /*!< 0x00400000 */
+#define IAC_IER2_IAIE86               IAC_IER2_IAIE86_Msk
+#define IAC_IER2_IAIE87_Pos           (23U)
+#define IAC_IER2_IAIE87_Msk           (0x1UL << IAC_IER2_IAIE87_Pos)             /*!< 0x00800000 */
+#define IAC_IER2_IAIE87               IAC_IER2_IAIE87_Msk
+#define IAC_IER2_IAIE88_Pos           (24U)
+#define IAC_IER2_IAIE88_Msk           (0x1UL << IAC_IER2_IAIE88_Pos)             /*!< 0x01000000 */
+#define IAC_IER2_IAIE88               IAC_IER2_IAIE88_Msk
+#define IAC_IER2_IAIE89_Pos           (25U)
+#define IAC_IER2_IAIE89_Msk           (0x1UL << IAC_IER2_IAIE89_Pos)             /*!< 0x02000000 */
+#define IAC_IER2_IAIE89               IAC_IER2_IAIE89_Msk
+#define IAC_IER2_IAIE90_Pos           (26U)
+#define IAC_IER2_IAIE90_Msk           (0x1UL << IAC_IER2_IAIE90_Pos)             /*!< 0x04000000 */
+#define IAC_IER2_IAIE90               IAC_IER2_IAIE90_Msk
+#define IAC_IER2_IAIE92_Pos           (28U)
+#define IAC_IER2_IAIE92_Msk           (0x1UL << IAC_IER2_IAIE92_Pos)             /*!< 0x10000000 */
+#define IAC_IER2_IAIE92               IAC_IER2_IAIE92_Msk
+#define IAC_IER2_IAIE93_Pos           (29U)
+#define IAC_IER2_IAIE93_Msk           (0x1UL << IAC_IER2_IAIE93_Pos)             /*!< 0x20000000 */
+#define IAC_IER2_IAIE93               IAC_IER2_IAIE93_Msk
+#define IAC_IER2_IAIE94_Pos           (30U)
+#define IAC_IER2_IAIE94_Msk           (0x1UL << IAC_IER2_IAIE94_Pos)             /*!< 0x40000000 */
+#define IAC_IER2_IAIE94               IAC_IER2_IAIE94_Msk
+#define IAC_IER2_IAIE95_Pos           (31U)
+#define IAC_IER2_IAIE95_Msk           (0x1UL << IAC_IER2_IAIE95_Pos)             /*!< 0x80000000 */
+#define IAC_IER2_IAIE95               IAC_IER2_IAIE95_Msk
+
+/*******************  Bits definition for IAC_IER3 register *******************/
+#define IAC_IER3_IAIE96_Pos           (0U)
+#define IAC_IER3_IAIE96_Msk           (0x1UL << IAC_IER3_IAIE96_Pos)             /*!< 0x00000001 */
+#define IAC_IER3_IAIE96               IAC_IER3_IAIE96_Msk
+#define IAC_IER3_IAIE97_Pos           (1U)
+#define IAC_IER3_IAIE97_Msk           (0x1UL << IAC_IER3_IAIE97_Pos)             /*!< 0x00000002 */
+#define IAC_IER3_IAIE97               IAC_IER3_IAIE97_Msk
+#define IAC_IER3_IAIE98_Pos           (2U)
+#define IAC_IER3_IAIE98_Msk           (0x1UL << IAC_IER3_IAIE98_Pos)             /*!< 0x00000004 */
+#define IAC_IER3_IAIE98               IAC_IER3_IAIE98_Msk
+#define IAC_IER3_IAIE99_Pos           (3U)
+#define IAC_IER3_IAIE99_Msk           (0x1UL << IAC_IER3_IAIE99_Pos)             /*!< 0x00000008 */
+#define IAC_IER3_IAIE99               IAC_IER3_IAIE99_Msk
+#define IAC_IER3_IAIE100_Pos          (4U)
+#define IAC_IER3_IAIE100_Msk          (0x1UL << IAC_IER3_IAIE100_Pos)            /*!< 0x00000010 */
+#define IAC_IER3_IAIE100              IAC_IER3_IAIE100_Msk
+#define IAC_IER3_IAIE101_Pos          (5U)
+#define IAC_IER3_IAIE101_Msk          (0x1UL << IAC_IER3_IAIE101_Pos)            /*!< 0x00000020 */
+#define IAC_IER3_IAIE101              IAC_IER3_IAIE101_Msk
+#define IAC_IER3_IAIE102_Pos          (6U)
+#define IAC_IER3_IAIE102_Msk          (0x1UL << IAC_IER3_IAIE102_Pos)            /*!< 0x00000040 */
+#define IAC_IER3_IAIE102              IAC_IER3_IAIE102_Msk
+#define IAC_IER3_IAIE103_Pos          (7U)
+#define IAC_IER3_IAIE103_Msk          (0x1UL << IAC_IER3_IAIE103_Pos)            /*!< 0x00000080 */
+#define IAC_IER3_IAIE103              IAC_IER3_IAIE103_Msk
+#define IAC_IER3_IAIE104_Pos          (8U)
+#define IAC_IER3_IAIE104_Msk          (0x1UL << IAC_IER3_IAIE104_Pos)            /*!< 0x00000100 */
+#define IAC_IER3_IAIE104              IAC_IER3_IAIE104_Msk
+#define IAC_IER3_IAIE106_Pos          (10U)
+#define IAC_IER3_IAIE106_Msk          (0x1UL << IAC_IER3_IAIE106_Pos)            /*!< 0x00000400 */
+#define IAC_IER3_IAIE106              IAC_IER3_IAIE106_Msk
+
+/*******************  Bits definition for IAC_IER4 register *******************/
+#define IAC_IER4_IAIE128_Pos          (0U)
+#define IAC_IER4_IAIE128_Msk          (0x1UL << IAC_IER4_IAIE128_Pos)            /*!< 0x00000001 */
+#define IAC_IER4_IAIE128              IAC_IER4_IAIE128_Msk
+#define IAC_IER4_IAIE129_Pos          (1U)
+#define IAC_IER4_IAIE129_Msk          (0x1UL << IAC_IER4_IAIE129_Pos)            /*!< 0x00000002 */
+#define IAC_IER4_IAIE129              IAC_IER4_IAIE129_Msk
+#define IAC_IER4_IAIE130_Pos          (2U)
+#define IAC_IER4_IAIE130_Msk          (0x1UL << IAC_IER4_IAIE130_Pos)            /*!< 0x00000004 */
+#define IAC_IER4_IAIE130              IAC_IER4_IAIE130_Msk
+#define IAC_IER4_IAIE131_Pos          (3U)
+#define IAC_IER4_IAIE131_Msk          (0x1UL << IAC_IER4_IAIE131_Pos)            /*!< 0x00000008 */
+#define IAC_IER4_IAIE131              IAC_IER4_IAIE131_Msk
+#define IAC_IER4_IAIE133_Pos          (5U)
+#define IAC_IER4_IAIE133_Msk          (0x1UL << IAC_IER4_IAIE133_Pos)            /*!< 0x00000020 */
+#define IAC_IER4_IAIE133              IAC_IER4_IAIE133_Msk
+#define IAC_IER4_IAIE134_Pos          (6U)
+#define IAC_IER4_IAIE134_Msk          (0x1UL << IAC_IER4_IAIE134_Pos)            /*!< 0x00000040 */
+#define IAC_IER4_IAIE134              IAC_IER4_IAIE134_Msk
+#define IAC_IER4_IAIE135_Pos          (7U)
+#define IAC_IER4_IAIE135_Msk          (0x1UL << IAC_IER4_IAIE135_Pos)            /*!< 0x00000080 */
+#define IAC_IER4_IAIE135              IAC_IER4_IAIE135_Msk
+#define IAC_IER4_IAIE136_Pos          (8U)
+#define IAC_IER4_IAIE136_Msk          (0x1UL << IAC_IER4_IAIE136_Pos)            /*!< 0x00000100 */
+#define IAC_IER4_IAIE136              IAC_IER4_IAIE136_Msk
+#define IAC_IER4_IAIE137_Pos          (9U)
+#define IAC_IER4_IAIE137_Msk          (0x1UL << IAC_IER4_IAIE137_Pos)            /*!< 0x00000200 */
+#define IAC_IER4_IAIE137              IAC_IER4_IAIE137_Msk
+#define IAC_IER4_IAIE138_Pos          (10U)
+#define IAC_IER4_IAIE138_Msk          (0x1UL << IAC_IER4_IAIE138_Pos)            /*!< 0x00000400 */
+#define IAC_IER4_IAIE138              IAC_IER4_IAIE138_Msk
+#define IAC_IER4_IAIE139_Pos          (11U)
+#define IAC_IER4_IAIE139_Msk          (0x1UL << IAC_IER4_IAIE139_Pos)            /*!< 0x00000800 */
+#define IAC_IER4_IAIE139              IAC_IER4_IAIE139_Msk
+#define IAC_IER4_IAIE140_Pos          (12U)
+#define IAC_IER4_IAIE140_Msk          (0x1UL << IAC_IER4_IAIE140_Pos)            /*!< 0x00001000 */
+#define IAC_IER4_IAIE140              IAC_IER4_IAIE140_Msk
+#define IAC_IER4_IAIE141_Pos          (13U)
+#define IAC_IER4_IAIE141_Msk          (0x1UL << IAC_IER4_IAIE141_Pos)            /*!< 0x00002000 */
+#define IAC_IER4_IAIE141              IAC_IER4_IAIE141_Msk
+#define IAC_IER4_IAIE142_Pos          (14U)
+#define IAC_IER4_IAIE142_Msk          (0x1UL << IAC_IER4_IAIE142_Pos)            /*!< 0x00004000 */
+#define IAC_IER4_IAIE142              IAC_IER4_IAIE142_Msk
+#define IAC_IER4_IAIE143_Pos          (15U)
+#define IAC_IER4_IAIE143_Msk          (0x1UL << IAC_IER4_IAIE143_Pos)            /*!< 0x00008000 */
+#define IAC_IER4_IAIE143              IAC_IER4_IAIE143_Msk
+#define IAC_IER4_IAIE144_Pos          (16U)
+#define IAC_IER4_IAIE144_Msk          (0x1UL << IAC_IER4_IAIE144_Pos)            /*!< 0x00010000 */
+#define IAC_IER4_IAIE144              IAC_IER4_IAIE144_Msk
+#define IAC_IER4_IAIE145_Pos          (17U)
+#define IAC_IER4_IAIE145_Msk          (0x1UL << IAC_IER4_IAIE145_Pos)            /*!< 0x00020000 */
+#define IAC_IER4_IAIE145              IAC_IER4_IAIE145_Msk
+#define IAC_IER4_IAIE146_Pos          (18U)
+#define IAC_IER4_IAIE146_Msk          (0x1UL << IAC_IER4_IAIE146_Pos)            /*!< 0x00040000 */
+#define IAC_IER4_IAIE146              IAC_IER4_IAIE146_Msk
+#define IAC_IER4_IAIE147_Pos          (19U)
+#define IAC_IER4_IAIE147_Msk          (0x1UL << IAC_IER4_IAIE147_Pos)            /*!< 0x00080000 */
+#define IAC_IER4_IAIE147              IAC_IER4_IAIE147_Msk
+#define IAC_IER4_IAIE149_Pos          (21U)
+#define IAC_IER4_IAIE149_Msk          (0x1UL << IAC_IER4_IAIE149_Pos)            /*!< 0x00200000 */
+#define IAC_IER4_IAIE149              IAC_IER4_IAIE149_Msk
+#define IAC_IER4_IAIE150_Pos          (22U)
+#define IAC_IER4_IAIE150_Msk          (0x1UL << IAC_IER4_IAIE150_Pos)            /*!< 0x00400000 */
+#define IAC_IER4_IAIE150              IAC_IER4_IAIE150_Msk
+#define IAC_IER4_IAIE151_Pos          (23U)
+#define IAC_IER4_IAIE151_Msk          (0x1UL << IAC_IER4_IAIE151_Pos)            /*!< 0x00800000 */
+#define IAC_IER4_IAIE151              IAC_IER4_IAIE151_Msk
+#define IAC_IER4_IAIE152_Pos          (24U)
+#define IAC_IER4_IAIE152_Msk          (0x1UL << IAC_IER4_IAIE152_Pos)            /*!< 0x01000000 */
+#define IAC_IER4_IAIE152              IAC_IER4_IAIE152_Msk
+#define IAC_IER4_IAIE153_Pos          (25U)
+#define IAC_IER4_IAIE153_Msk          (0x1UL << IAC_IER4_IAIE153_Pos)            /*!< 0x02000000 */
+#define IAC_IER4_IAIE153              IAC_IER4_IAIE153_Msk
+#define IAC_IER4_IAIE155_Pos          (27U)
+#define IAC_IER4_IAIE155_Msk          (0x1UL << IAC_IER4_IAIE155_Pos)            /*!< 0x08000000 */
+#define IAC_IER4_IAIE155              IAC_IER4_IAIE155_Msk
+#define IAC_IER4_IAIE156_Pos          (28U)
+#define IAC_IER4_IAIE156_Msk          (0x1UL << IAC_IER4_IAIE156_Pos)            /*!< 0x10000000 */
+#define IAC_IER4_IAIE156              IAC_IER4_IAIE156_Msk
+#define IAC_IER4_IAIE157_Pos          (29U)
+#define IAC_IER4_IAIE157_Msk          (0x1UL << IAC_IER4_IAIE157_Pos)            /*!< 0x20000000 */
+#define IAC_IER4_IAIE157              IAC_IER4_IAIE157_Msk
+
+/*******************  Bits definition for IAC_ISR0 register *******************/
+#define IAC_ISR0_IAF0_Pos             (0U)
+#define IAC_ISR0_IAF0_Msk             (0x1UL << IAC_ISR0_IAF0_Pos)               /*!< 0x00000001 */
+#define IAC_ISR0_IAF0                 IAC_ISR0_IAF0_Msk
+#define IAC_ISR0_IAF1_Pos             (1U)
+#define IAC_ISR0_IAF1_Msk             (0x1UL << IAC_ISR0_IAF1_Pos)               /*!< 0x00000002 */
+#define IAC_ISR0_IAF1                 IAC_ISR0_IAF1_Msk
+#define IAC_ISR0_IAF2_Pos             (2U)
+#define IAC_ISR0_IAF2_Msk             (0x1UL << IAC_ISR0_IAF2_Pos)               /*!< 0x00000004 */
+#define IAC_ISR0_IAF2                 IAC_ISR0_IAF2_Msk
+#define IAC_ISR0_IAF3_Pos             (3U)
+#define IAC_ISR0_IAF3_Msk             (0x1UL << IAC_ISR0_IAF3_Pos)               /*!< 0x00000008 */
+#define IAC_ISR0_IAF3                 IAC_ISR0_IAF3_Msk
+#define IAC_ISR0_IAF4_Pos             (4U)
+#define IAC_ISR0_IAF4_Msk             (0x1UL << IAC_ISR0_IAF4_Pos)               /*!< 0x00000010 */
+#define IAC_ISR0_IAF4                 IAC_ISR0_IAF4_Msk
+#define IAC_ISR0_IAF5_Pos             (5U)
+#define IAC_ISR0_IAF5_Msk             (0x1UL << IAC_ISR0_IAF5_Pos)               /*!< 0x00000020 */
+#define IAC_ISR0_IAF5                 IAC_ISR0_IAF5_Msk
+#define IAC_ISR0_IAF6_Pos             (6U)
+#define IAC_ISR0_IAF6_Msk             (0x1UL << IAC_ISR0_IAF6_Pos)               /*!< 0x00000040 */
+#define IAC_ISR0_IAF6                 IAC_ISR0_IAF6_Msk
+#define IAC_ISR0_IAF8_Pos             (8U)
+#define IAC_ISR0_IAF8_Msk             (0x1UL << IAC_ISR0_IAF8_Pos)               /*!< 0x00000100 */
+#define IAC_ISR0_IAF8                 IAC_ISR0_IAF8_Msk
+#define IAC_ISR0_IAF9_Pos             (9U)
+#define IAC_ISR0_IAF9_Msk             (0x1UL << IAC_ISR0_IAF9_Pos)               /*!< 0x00000200 */
+#define IAC_ISR0_IAF9                 IAC_ISR0_IAF9_Msk
+#define IAC_ISR0_IAF10_Pos            (10U)
+#define IAC_ISR0_IAF10_Msk            (0x1UL << IAC_ISR0_IAF10_Pos)              /*!< 0x00000400 */
+#define IAC_ISR0_IAF10                IAC_ISR0_IAF10_Msk
+#define IAC_ISR0_IAF11_Pos            (11U)
+#define IAC_ISR0_IAF11_Msk            (0x1UL << IAC_ISR0_IAF11_Pos)              /*!< 0x00000800 */
+#define IAC_ISR0_IAF11                IAC_ISR0_IAF11_Msk
+#define IAC_ISR0_IAF12_Pos            (12U)
+#define IAC_ISR0_IAF12_Msk            (0x1UL << IAC_ISR0_IAF12_Pos)              /*!< 0x00001000 */
+#define IAC_ISR0_IAF12                IAC_ISR0_IAF12_Msk
+#define IAC_ISR0_IAF13_Pos            (13U)
+#define IAC_ISR0_IAF13_Msk            (0x1UL << IAC_ISR0_IAF13_Pos)              /*!< 0x00002000 */
+#define IAC_ISR0_IAF13                IAC_ISR0_IAF13_Msk
+#define IAC_ISR0_IAF14_Pos            (14U)
+#define IAC_ISR0_IAF14_Msk            (0x1UL << IAC_ISR0_IAF14_Pos)              /*!< 0x00004000 */
+#define IAC_ISR0_IAF14                IAC_ISR0_IAF14_Msk
+#define IAC_ISR0_IAF15_Pos            (15U)
+#define IAC_ISR0_IAF15_Msk            (0x1UL << IAC_ISR0_IAF15_Pos)              /*!< 0x00008000 */
+#define IAC_ISR0_IAF15                IAC_ISR0_IAF15_Msk
+#define IAC_ISR0_IAF16_Pos            (16U)
+#define IAC_ISR0_IAF16_Msk            (0x1UL << IAC_ISR0_IAF16_Pos)              /*!< 0x00010000 */
+#define IAC_ISR0_IAF16                IAC_ISR0_IAF16_Msk
+#define IAC_ISR0_IAF17_Pos            (17U)
+#define IAC_ISR0_IAF17_Msk            (0x1UL << IAC_ISR0_IAF17_Pos)              /*!< 0x00020000 */
+#define IAC_ISR0_IAF17                IAC_ISR0_IAF17_Msk
+#define IAC_ISR0_IAF18_Pos            (18U)
+#define IAC_ISR0_IAF18_Msk            (0x1UL << IAC_ISR0_IAF18_Pos)              /*!< 0x00040000 */
+#define IAC_ISR0_IAF18                IAC_ISR0_IAF18_Msk
+#define IAC_ISR0_IAF19_Pos            (19U)
+#define IAC_ISR0_IAF19_Msk            (0x1UL << IAC_ISR0_IAF19_Pos)              /*!< 0x00080000 */
+#define IAC_ISR0_IAF19                IAC_ISR0_IAF19_Msk
+#define IAC_ISR0_IAF20_Pos            (20U)
+#define IAC_ISR0_IAF20_Msk            (0x1UL << IAC_ISR0_IAF20_Pos)              /*!< 0x00100000 */
+#define IAC_ISR0_IAF20                IAC_ISR0_IAF20_Msk
+#define IAC_ISR0_IAF21_Pos            (21U)
+#define IAC_ISR0_IAF21_Msk            (0x1UL << IAC_ISR0_IAF21_Pos)              /*!< 0x00200000 */
+#define IAC_ISR0_IAF21                IAC_ISR0_IAF21_Msk
+#define IAC_ISR0_IAF22_Pos            (22U)
+#define IAC_ISR0_IAF22_Msk            (0x1UL << IAC_ISR0_IAF22_Pos)              /*!< 0x00400000 */
+#define IAC_ISR0_IAF22                IAC_ISR0_IAF22_Msk
+#define IAC_ISR0_IAF23_Pos            (23U)
+#define IAC_ISR0_IAF23_Msk            (0x1UL << IAC_ISR0_IAF23_Pos)              /*!< 0x00800000 */
+#define IAC_ISR0_IAF23                IAC_ISR0_IAF23_Msk
+#define IAC_ISR0_IAF24_Pos            (24U)
+#define IAC_ISR0_IAF24_Msk            (0x1UL << IAC_ISR0_IAF24_Pos)              /*!< 0x01000000 */
+#define IAC_ISR0_IAF24                IAC_ISR0_IAF24_Msk
+#define IAC_ISR0_IAF25_Pos            (25U)
+#define IAC_ISR0_IAF25_Msk            (0x1UL << IAC_ISR0_IAF25_Pos)              /*!< 0x02000000 */
+#define IAC_ISR0_IAF25                IAC_ISR0_IAF25_Msk
+#define IAC_ISR0_IAF26_Pos            (26U)
+#define IAC_ISR0_IAF26_Msk            (0x1UL << IAC_ISR0_IAF26_Pos)              /*!< 0x04000000 */
+#define IAC_ISR0_IAF26                IAC_ISR0_IAF26_Msk
+#define IAC_ISR0_IAF27_Pos            (27U)
+#define IAC_ISR0_IAF27_Msk            (0x1UL << IAC_ISR0_IAF27_Pos)              /*!< 0x08000000 */
+#define IAC_ISR0_IAF27                IAC_ISR0_IAF27_Msk
+#define IAC_ISR0_IAF28_Pos            (28U)
+#define IAC_ISR0_IAF28_Msk            (0x1UL << IAC_ISR0_IAF28_Pos)              /*!< 0x10000000 */
+#define IAC_ISR0_IAF28                IAC_ISR0_IAF28_Msk
+#define IAC_ISR0_IAF29_Pos            (29U)
+#define IAC_ISR0_IAF29_Msk            (0x1UL << IAC_ISR0_IAF29_Pos)              /*!< 0x20000000 */
+#define IAC_ISR0_IAF29                IAC_ISR0_IAF29_Msk
+#define IAC_ISR0_IAF30_Pos            (30U)
+#define IAC_ISR0_IAF30_Msk            (0x1UL << IAC_ISR0_IAF30_Pos)              /*!< 0x40000000 */
+#define IAC_ISR0_IAF30                IAC_ISR0_IAF30_Msk
+#define IAC_ISR0_IAF31_Pos            (31U)
+#define IAC_ISR0_IAF31_Msk            (0x1UL << IAC_ISR0_IAF31_Pos)              /*!< 0x80000000 */
+#define IAC_ISR0_IAF31                IAC_ISR0_IAF31_Msk
+
+/*******************  Bits definition for IAC_ISR1 register *******************/
+#define IAC_ISR1_IAF32_Pos            (0U)
+#define IAC_ISR1_IAF32_Msk            (0x1UL << IAC_ISR1_IAF32_Pos)              /*!< 0x00000001 */
+#define IAC_ISR1_IAF32                IAC_ISR1_IAF32_Msk
+#define IAC_ISR1_IAF33_Pos            (1U)
+#define IAC_ISR1_IAF33_Msk            (0x1UL << IAC_ISR1_IAF33_Pos)              /*!< 0x00000002 */
+#define IAC_ISR1_IAF33                IAC_ISR1_IAF33_Msk
+#define IAC_ISR1_IAF34_Pos            (2U)
+#define IAC_ISR1_IAF34_Msk            (0x1UL << IAC_ISR1_IAF34_Pos)              /*!< 0x00000004 */
+#define IAC_ISR1_IAF34                IAC_ISR1_IAF34_Msk
+#define IAC_ISR1_IAF35_Pos            (3U)
+#define IAC_ISR1_IAF35_Msk            (0x1UL << IAC_ISR1_IAF35_Pos)              /*!< 0x00000008 */
+#define IAC_ISR1_IAF35                IAC_ISR1_IAF35_Msk
+#define IAC_ISR1_IAF36_Pos            (4U)
+#define IAC_ISR1_IAF36_Msk            (0x1UL << IAC_ISR1_IAF36_Pos)              /*!< 0x00000010 */
+#define IAC_ISR1_IAF36                IAC_ISR1_IAF36_Msk
+#define IAC_ISR1_IAF37_Pos            (5U)
+#define IAC_ISR1_IAF37_Msk            (0x1UL << IAC_ISR1_IAF37_Pos)              /*!< 0x00000020 */
+#define IAC_ISR1_IAF37                IAC_ISR1_IAF37_Msk
+#define IAC_ISR1_IAF38_Pos            (6U)
+#define IAC_ISR1_IAF38_Msk            (0x1UL << IAC_ISR1_IAF38_Pos)              /*!< 0x00000040 */
+#define IAC_ISR1_IAF38                IAC_ISR1_IAF38_Msk
+#define IAC_ISR1_IAF39_Pos            (7U)
+#define IAC_ISR1_IAF39_Msk            (0x1UL << IAC_ISR1_IAF39_Pos)              /*!< 0x00000080 */
+#define IAC_ISR1_IAF39                IAC_ISR1_IAF39_Msk
+#define IAC_ISR1_IAF40_Pos            (8U)
+#define IAC_ISR1_IAF40_Msk            (0x1UL << IAC_ISR1_IAF40_Pos)              /*!< 0x00000100 */
+#define IAC_ISR1_IAF40                IAC_ISR1_IAF40_Msk
+#define IAC_ISR1_IAF41_Pos            (9U)
+#define IAC_ISR1_IAF41_Msk            (0x1UL << IAC_ISR1_IAF41_Pos)              /*!< 0x00000200 */
+#define IAC_ISR1_IAF41                IAC_ISR1_IAF41_Msk
+#define IAC_ISR1_IAF42_Pos            (10U)
+#define IAC_ISR1_IAF42_Msk            (0x1UL << IAC_ISR1_IAF42_Pos)              /*!< 0x00000400 */
+#define IAC_ISR1_IAF42                IAC_ISR1_IAF42_Msk
+#define IAC_ISR1_IAF43_Pos            (11U)
+#define IAC_ISR1_IAF43_Msk            (0x1UL << IAC_ISR1_IAF43_Pos)              /*!< 0x00000800 */
+#define IAC_ISR1_IAF43                IAC_ISR1_IAF43_Msk
+#define IAC_ISR1_IAF44_Pos            (12U)
+#define IAC_ISR1_IAF44_Msk            (0x1UL << IAC_ISR1_IAF44_Pos)              /*!< 0x00001000 */
+#define IAC_ISR1_IAF44                IAC_ISR1_IAF44_Msk
+#define IAC_ISR1_IAF45_Pos            (13U)
+#define IAC_ISR1_IAF45_Msk            (0x1UL << IAC_ISR1_IAF45_Pos)              /*!< 0x00002000 */
+#define IAC_ISR1_IAF45                IAC_ISR1_IAF45_Msk
+#define IAC_ISR1_IAF46_Pos            (14U)
+#define IAC_ISR1_IAF46_Msk            (0x1UL << IAC_ISR1_IAF46_Pos)              /*!< 0x00004000 */
+#define IAC_ISR1_IAF46                IAC_ISR1_IAF46_Msk
+#define IAC_ISR1_IAF47_Pos            (15U)
+#define IAC_ISR1_IAF47_Msk            (0x1UL << IAC_ISR1_IAF47_Pos)              /*!< 0x00008000 */
+#define IAC_ISR1_IAF47                IAC_ISR1_IAF47_Msk
+#define IAC_ISR1_IAF48_Pos            (16U)
+#define IAC_ISR1_IAF48_Msk            (0x1UL << IAC_ISR1_IAF48_Pos)              /*!< 0x00010000 */
+#define IAC_ISR1_IAF48                IAC_ISR1_IAF48_Msk
+#define IAC_ISR1_IAF49_Pos            (17U)
+#define IAC_ISR1_IAF49_Msk            (0x1UL << IAC_ISR1_IAF49_Pos)              /*!< 0x00020000 */
+#define IAC_ISR1_IAF49                IAC_ISR1_IAF49_Msk
+#define IAC_ISR1_IAF50_Pos            (18U)
+#define IAC_ISR1_IAF50_Msk            (0x1UL << IAC_ISR1_IAF50_Pos)              /*!< 0x00040000 */
+#define IAC_ISR1_IAF50                IAC_ISR1_IAF50_Msk
+#define IAC_ISR1_IAF51_Pos            (19U)
+#define IAC_ISR1_IAF51_Msk            (0x1UL << IAC_ISR1_IAF51_Pos)              /*!< 0x00080000 */
+#define IAC_ISR1_IAF51                IAC_ISR1_IAF51_Msk
+#define IAC_ISR1_IAF52_Pos            (20U)
+#define IAC_ISR1_IAF52_Msk            (0x1UL << IAC_ISR1_IAF52_Pos)              /*!< 0x00100000 */
+#define IAC_ISR1_IAF52                IAC_ISR1_IAF52_Msk
+#define IAC_ISR1_IAF53_Pos            (21U)
+#define IAC_ISR1_IAF53_Msk            (0x1UL << IAC_ISR1_IAF53_Pos)              /*!< 0x00200000 */
+#define IAC_ISR1_IAF53                IAC_ISR1_IAF53_Msk
+#define IAC_ISR1_IAF54_Pos            (22U)
+#define IAC_ISR1_IAF54_Msk            (0x1UL << IAC_ISR1_IAF54_Pos)              /*!< 0x00400000 */
+#define IAC_ISR1_IAF54                IAC_ISR1_IAF54_Msk
+#define IAC_ISR1_IAF55_Pos            (23U)
+#define IAC_ISR1_IAF55_Msk            (0x1UL << IAC_ISR1_IAF55_Pos)              /*!< 0x00800000 */
+#define IAC_ISR1_IAF55                IAC_ISR1_IAF55_Msk
+#define IAC_ISR1_IAF56_Pos            (24U)
+#define IAC_ISR1_IAF56_Msk            (0x1UL << IAC_ISR1_IAF56_Pos)              /*!< 0x01000000 */
+#define IAC_ISR1_IAF56                IAC_ISR1_IAF56_Msk
+#define IAC_ISR1_IAF57_Pos            (25U)
+#define IAC_ISR1_IAF57_Msk            (0x1UL << IAC_ISR1_IAF57_Pos)              /*!< 0x02000000 */
+#define IAC_ISR1_IAF57                IAC_ISR1_IAF57_Msk
+#define IAC_ISR1_IAF58_Pos            (26U)
+#define IAC_ISR1_IAF58_Msk            (0x1UL << IAC_ISR1_IAF58_Pos)              /*!< 0x04000000 */
+#define IAC_ISR1_IAF58                IAC_ISR1_IAF58_Msk
+#define IAC_ISR1_IAF60_Pos            (28U)
+#define IAC_ISR1_IAF60_Msk            (0x1UL << IAC_ISR1_IAF60_Pos)              /*!< 0x10000000 */
+#define IAC_ISR1_IAF60                IAC_ISR1_IAF60_Msk
+#define IAC_ISR1_IAF61_Pos            (29U)
+#define IAC_ISR1_IAF61_Msk            (0x1UL << IAC_ISR1_IAF61_Pos)              /*!< 0x20000000 */
+#define IAC_ISR1_IAF61                IAC_ISR1_IAF61_Msk
+#define IAC_ISR1_IAF62_Pos            (30U)
+#define IAC_ISR1_IAF62_Msk            (0x1UL << IAC_ISR1_IAF62_Pos)              /*!< 0x40000000 */
+#define IAC_ISR1_IAF62                IAC_ISR1_IAF62_Msk
+
+/*******************  Bits definition for IAC_ISR2 register *******************/
+#define IAC_ISR2_IAF64_Pos            (0U)
+#define IAC_ISR2_IAF64_Msk            (0x1UL << IAC_ISR2_IAF64_Pos)              /*!< 0x00000001 */
+#define IAC_ISR2_IAF64                IAC_ISR2_IAF64_Msk
+#define IAC_ISR2_IAF65_Pos            (1U)
+#define IAC_ISR2_IAF65_Msk            (0x1UL << IAC_ISR2_IAF65_Pos)              /*!< 0x00000002 */
+#define IAC_ISR2_IAF65                IAC_ISR2_IAF65_Msk
+#define IAC_ISR2_IAF67_Pos            (3U)
+#define IAC_ISR2_IAF67_Msk            (0x1UL << IAC_ISR2_IAF67_Pos)              /*!< 0x00000008 */
+#define IAC_ISR2_IAF67                IAC_ISR2_IAF67_Msk
+#define IAC_ISR2_IAF68_Pos            (4U)
+#define IAC_ISR2_IAF68_Msk            (0x1UL << IAC_ISR2_IAF68_Pos)              /*!< 0x00000010 */
+#define IAC_ISR2_IAF68                IAC_ISR2_IAF68_Msk
+#define IAC_ISR2_IAF69_Pos            (5U)
+#define IAC_ISR2_IAF69_Msk            (0x1UL << IAC_ISR2_IAF69_Pos)              /*!< 0x00000020 */
+#define IAC_ISR2_IAF69                IAC_ISR2_IAF69_Msk
+#define IAC_ISR2_IAF76_Pos            (12U)
+#define IAC_ISR2_IAF76_Msk            (0x1UL << IAC_ISR2_IAF76_Pos)              /*!< 0x00001000 */
+#define IAC_ISR2_IAF76                IAC_ISR2_IAF76_Msk
+#define IAC_ISR2_IAF77_Pos            (13U)
+#define IAC_ISR2_IAF77_Msk            (0x1UL << IAC_ISR2_IAF77_Pos)              /*!< 0x00002000 */
+#define IAC_ISR2_IAF77                IAC_ISR2_IAF77_Msk
+#define IAC_ISR2_IAF78_Pos            (14U)
+#define IAC_ISR2_IAF78_Msk            (0x1UL << IAC_ISR2_IAF78_Pos)              /*!< 0x00004000 */
+#define IAC_ISR2_IAF78                IAC_ISR2_IAF78_Msk
+#define IAC_ISR2_IAF79_Pos            (15U)
+#define IAC_ISR2_IAF79_Msk            (0x1UL << IAC_ISR2_IAF79_Pos)              /*!< 0x00008000 */
+#define IAC_ISR2_IAF79                IAC_ISR2_IAF79_Msk
+#define IAC_ISR2_IAF80_Pos            (16U)
+#define IAC_ISR2_IAF80_Msk            (0x1UL << IAC_ISR2_IAF80_Pos)              /*!< 0x00010000 */
+#define IAC_ISR2_IAF80                IAC_ISR2_IAF80_Msk
+#define IAC_ISR2_IAF81_Pos            (17U)
+#define IAC_ISR2_IAF81_Msk            (0x1UL << IAC_ISR2_IAF81_Pos)              /*!< 0x00020000 */
+#define IAC_ISR2_IAF81                IAC_ISR2_IAF81_Msk
+#define IAC_ISR2_IAF82_Pos            (18U)
+#define IAC_ISR2_IAF82_Msk            (0x1UL << IAC_ISR2_IAF82_Pos)              /*!< 0x00040000 */
+#define IAC_ISR2_IAF82                IAC_ISR2_IAF82_Msk
+#define IAC_ISR2_IAF83_Pos            (19U)
+#define IAC_ISR2_IAF83_Msk            (0x1UL << IAC_ISR2_IAF83_Pos)              /*!< 0x00080000 */
+#define IAC_ISR2_IAF83                IAC_ISR2_IAF83_Msk
+#define IAC_ISR2_IAF84_Pos            (20U)
+#define IAC_ISR2_IAF84_Msk            (0x1UL << IAC_ISR2_IAF84_Pos)              /*!< 0x00100000 */
+#define IAC_ISR2_IAF84                IAC_ISR2_IAF84_Msk
+#define IAC_ISR2_IAF86_Pos            (22U)
+#define IAC_ISR2_IAF86_Msk            (0x1UL << IAC_ISR2_IAF86_Pos)              /*!< 0x00400000 */
+#define IAC_ISR2_IAF86                IAC_ISR2_IAF86_Msk
+#define IAC_ISR2_IAF87_Pos            (23U)
+#define IAC_ISR2_IAF87_Msk            (0x1UL << IAC_ISR2_IAF87_Pos)              /*!< 0x00800000 */
+#define IAC_ISR2_IAF87                IAC_ISR2_IAF87_Msk
+#define IAC_ISR2_IAF88_Pos            (24U)
+#define IAC_ISR2_IAF88_Msk            (0x1UL << IAC_ISR2_IAF88_Pos)              /*!< 0x01000000 */
+#define IAC_ISR2_IAF88                IAC_ISR2_IAF88_Msk
+#define IAC_ISR2_IAF89_Pos            (25U)
+#define IAC_ISR2_IAF89_Msk            (0x1UL << IAC_ISR2_IAF89_Pos)              /*!< 0x02000000 */
+#define IAC_ISR2_IAF89                IAC_ISR2_IAF89_Msk
+#define IAC_ISR2_IAF90_Pos            (26U)
+#define IAC_ISR2_IAF90_Msk            (0x1UL << IAC_ISR2_IAF90_Pos)              /*!< 0x04000000 */
+#define IAC_ISR2_IAF90                IAC_ISR2_IAF90_Msk
+#define IAC_ISR2_IAF92_Pos            (28U)
+#define IAC_ISR2_IAF92_Msk            (0x1UL << IAC_ISR2_IAF92_Pos)              /*!< 0x10000000 */
+#define IAC_ISR2_IAF92                IAC_ISR2_IAF92_Msk
+#define IAC_ISR2_IAF93_Pos            (29U)
+#define IAC_ISR2_IAF93_Msk            (0x1UL << IAC_ISR2_IAF93_Pos)              /*!< 0x20000000 */
+#define IAC_ISR2_IAF93                IAC_ISR2_IAF93_Msk
+#define IAC_ISR2_IAF94_Pos            (30U)
+#define IAC_ISR2_IAF94_Msk            (0x1UL << IAC_ISR2_IAF94_Pos)              /*!< 0x40000000 */
+#define IAC_ISR2_IAF94                IAC_ISR2_IAF94_Msk
+#define IAC_ISR2_IAF95_Pos            (31U)
+#define IAC_ISR2_IAF95_Msk            (0x1UL << IAC_ISR2_IAF95_Pos)              /*!< 0x80000000 */
+#define IAC_ISR2_IAF95                IAC_ISR2_IAF95_Msk
+
+/*******************  Bits definition for IAC_ISR3 register *******************/
+#define IAC_ISR3_IAF96_Pos            (0U)
+#define IAC_ISR3_IAF96_Msk            (0x1UL << IAC_ISR3_IAF96_Pos)              /*!< 0x00000001 */
+#define IAC_ISR3_IAF96                IAC_ISR3_IAF96_Msk
+#define IAC_ISR3_IAF97_Pos            (1U)
+#define IAC_ISR3_IAF97_Msk            (0x1UL << IAC_ISR3_IAF97_Pos)              /*!< 0x00000002 */
+#define IAC_ISR3_IAF97                IAC_ISR3_IAF97_Msk
+#define IAC_ISR3_IAF98_Pos            (2U)
+#define IAC_ISR3_IAF98_Msk            (0x1UL << IAC_ISR3_IAF98_Pos)              /*!< 0x00000004 */
+#define IAC_ISR3_IAF98                IAC_ISR3_IAF98_Msk
+#define IAC_ISR3_IAF99_Pos            (3U)
+#define IAC_ISR3_IAF99_Msk            (0x1UL << IAC_ISR3_IAF99_Pos)              /*!< 0x00000008 */
+#define IAC_ISR3_IAF99                IAC_ISR3_IAF99_Msk
+#define IAC_ISR3_IAF100_Pos           (4U)
+#define IAC_ISR3_IAF100_Msk           (0x1UL << IAC_ISR3_IAF100_Pos)             /*!< 0x00000010 */
+#define IAC_ISR3_IAF100               IAC_ISR3_IAF100_Msk
+#define IAC_ISR3_IAF101_Pos           (5U)
+#define IAC_ISR3_IAF101_Msk           (0x1UL << IAC_ISR3_IAF101_Pos)             /*!< 0x00000020 */
+#define IAC_ISR3_IAF101               IAC_ISR3_IAF101_Msk
+#define IAC_ISR3_IAF102_Pos           (6U)
+#define IAC_ISR3_IAF102_Msk           (0x1UL << IAC_ISR3_IAF102_Pos)             /*!< 0x00000040 */
+#define IAC_ISR3_IAF102               IAC_ISR3_IAF102_Msk
+#define IAC_ISR3_IAF103_Pos           (7U)
+#define IAC_ISR3_IAF103_Msk           (0x1UL << IAC_ISR3_IAF103_Pos)             /*!< 0x00000080 */
+#define IAC_ISR3_IAF103               IAC_ISR3_IAF103_Msk
+#define IAC_ISR3_IAF104_Pos           (8U)
+#define IAC_ISR3_IAF104_Msk           (0x1UL << IAC_ISR3_IAF104_Pos)             /*!< 0x00000100 */
+#define IAC_ISR3_IAF104               IAC_ISR3_IAF104_Msk
+#define IAC_ISR3_IAF106_Pos           (10U)
+#define IAC_ISR3_IAF106_Msk           (0x1UL << IAC_ISR3_IAF106_Pos)             /*!< 0x00000400 */
+#define IAC_ISR3_IAF106               IAC_ISR3_IAF106_Msk
+
+/*******************  Bits definition for IAC_ISR4 register *******************/
+#define IAC_ISR4_IAF128_Pos           (0U)
+#define IAC_ISR4_IAF128_Msk           (0x1UL << IAC_ISR4_IAF128_Pos)             /*!< 0x00000001 */
+#define IAC_ISR4_IAF128               IAC_ISR4_IAF128_Msk
+#define IAC_ISR4_IAF129_Pos           (1U)
+#define IAC_ISR4_IAF129_Msk           (0x1UL << IAC_ISR4_IAF129_Pos)             /*!< 0x00000002 */
+#define IAC_ISR4_IAF129               IAC_ISR4_IAF129_Msk
+#define IAC_ISR4_IAF130_Pos           (2U)
+#define IAC_ISR4_IAF130_Msk           (0x1UL << IAC_ISR4_IAF130_Pos)             /*!< 0x00000004 */
+#define IAC_ISR4_IAF130               IAC_ISR4_IAF130_Msk
+#define IAC_ISR4_IAF131_Pos           (3U)
+#define IAC_ISR4_IAF131_Msk           (0x1UL << IAC_ISR4_IAF131_Pos)             /*!< 0x00000008 */
+#define IAC_ISR4_IAF131               IAC_ISR4_IAF131_Msk
+#define IAC_ISR4_IAF133_Pos           (5U)
+#define IAC_ISR4_IAF133_Msk           (0x1UL << IAC_ISR4_IAF133_Pos)             /*!< 0x00000020 */
+#define IAC_ISR4_IAF133               IAC_ISR4_IAF133_Msk
+#define IAC_ISR4_IAF134_Pos           (6U)
+#define IAC_ISR4_IAF134_Msk           (0x1UL << IAC_ISR4_IAF134_Pos)             /*!< 0x00000040 */
+#define IAC_ISR4_IAF134               IAC_ISR4_IAF134_Msk
+#define IAC_ISR4_IAF135_Pos           (7U)
+#define IAC_ISR4_IAF135_Msk           (0x1UL << IAC_ISR4_IAF135_Pos)             /*!< 0x00000080 */
+#define IAC_ISR4_IAF135               IAC_ISR4_IAF135_Msk
+#define IAC_ISR4_IAF136_Pos           (8U)
+#define IAC_ISR4_IAF136_Msk           (0x1UL << IAC_ISR4_IAF136_Pos)             /*!< 0x00000100 */
+#define IAC_ISR4_IAF136               IAC_ISR4_IAF136_Msk
+#define IAC_ISR4_IAF137_Pos           (9U)
+#define IAC_ISR4_IAF137_Msk           (0x1UL << IAC_ISR4_IAF137_Pos)             /*!< 0x00000200 */
+#define IAC_ISR4_IAF137               IAC_ISR4_IAF137_Msk
+#define IAC_ISR4_IAF138_Pos           (10U)
+#define IAC_ISR4_IAF138_Msk           (0x1UL << IAC_ISR4_IAF138_Pos)             /*!< 0x00000400 */
+#define IAC_ISR4_IAF138               IAC_ISR4_IAF138_Msk
+#define IAC_ISR4_IAF139_Pos           (11U)
+#define IAC_ISR4_IAF139_Msk           (0x1UL << IAC_ISR4_IAF139_Pos)             /*!< 0x00000800 */
+#define IAC_ISR4_IAF139               IAC_ISR4_IAF139_Msk
+#define IAC_ISR4_IAF140_Pos           (12U)
+#define IAC_ISR4_IAF140_Msk           (0x1UL << IAC_ISR4_IAF140_Pos)             /*!< 0x00001000 */
+#define IAC_ISR4_IAF140               IAC_ISR4_IAF140_Msk
+#define IAC_ISR4_IAF141_Pos           (13U)
+#define IAC_ISR4_IAF141_Msk           (0x1UL << IAC_ISR4_IAF141_Pos)             /*!< 0x00002000 */
+#define IAC_ISR4_IAF141               IAC_ISR4_IAF141_Msk
+#define IAC_ISR4_IAF142_Pos           (14U)
+#define IAC_ISR4_IAF142_Msk           (0x1UL << IAC_ISR4_IAF142_Pos)             /*!< 0x00004000 */
+#define IAC_ISR4_IAF142               IAC_ISR4_IAF142_Msk
+#define IAC_ISR4_IAF143_Pos           (15U)
+#define IAC_ISR4_IAF143_Msk           (0x1UL << IAC_ISR4_IAF143_Pos)             /*!< 0x00008000 */
+#define IAC_ISR4_IAF143               IAC_ISR4_IAF143_Msk
+#define IAC_ISR4_IAF144_Pos           (16U)
+#define IAC_ISR4_IAF144_Msk           (0x1UL << IAC_ISR4_IAF144_Pos)             /*!< 0x00010000 */
+#define IAC_ISR4_IAF144               IAC_ISR4_IAF144_Msk
+#define IAC_ISR4_IAF145_Pos           (17U)
+#define IAC_ISR4_IAF145_Msk           (0x1UL << IAC_ISR4_IAF145_Pos)             /*!< 0x00020000 */
+#define IAC_ISR4_IAF145               IAC_ISR4_IAF145_Msk
+#define IAC_ISR4_IAF146_Pos           (18U)
+#define IAC_ISR4_IAF146_Msk           (0x1UL << IAC_ISR4_IAF146_Pos)             /*!< 0x00040000 */
+#define IAC_ISR4_IAF146               IAC_ISR4_IAF146_Msk
+#define IAC_ISR4_IAF147_Pos           (19U)
+#define IAC_ISR4_IAF147_Msk           (0x1UL << IAC_ISR4_IAF147_Pos)             /*!< 0x00080000 */
+#define IAC_ISR4_IAF147               IAC_ISR4_IAF147_Msk
+#define IAC_ISR4_IAF149_Pos           (21U)
+#define IAC_ISR4_IAF149_Msk           (0x1UL << IAC_ISR4_IAF149_Pos)             /*!< 0x00200000 */
+#define IAC_ISR4_IAF149               IAC_ISR4_IAF149_Msk
+#define IAC_ISR4_IAF150_Pos           (22U)
+#define IAC_ISR4_IAF150_Msk           (0x1UL << IAC_ISR4_IAF150_Pos)             /*!< 0x00400000 */
+#define IAC_ISR4_IAF150               IAC_ISR4_IAF150_Msk
+#define IAC_ISR4_IAF151_Pos           (23U)
+#define IAC_ISR4_IAF151_Msk           (0x1UL << IAC_ISR4_IAF151_Pos)             /*!< 0x00800000 */
+#define IAC_ISR4_IAF151               IAC_ISR4_IAF151_Msk
+#define IAC_ISR4_IAF152_Pos           (24U)
+#define IAC_ISR4_IAF152_Msk           (0x1UL << IAC_ISR4_IAF152_Pos)             /*!< 0x01000000 */
+#define IAC_ISR4_IAF152               IAC_ISR4_IAF152_Msk
+#define IAC_ISR4_IAF153_Pos           (25U)
+#define IAC_ISR4_IAF153_Msk           (0x1UL << IAC_ISR4_IAF153_Pos)             /*!< 0x02000000 */
+#define IAC_ISR4_IAF153               IAC_ISR4_IAF153_Msk
+#define IAC_ISR4_IAF155_Pos           (27U)
+#define IAC_ISR4_IAF155_Msk           (0x1UL << IAC_ISR4_IAF155_Pos)             /*!< 0x08000000 */
+#define IAC_ISR4_IAF155               IAC_ISR4_IAF155_Msk
+#define IAC_ISR4_IAF156_Pos           (28U)
+#define IAC_ISR4_IAF156_Msk           (0x1UL << IAC_ISR4_IAF156_Pos)             /*!< 0x10000000 */
+#define IAC_ISR4_IAF156               IAC_ISR4_IAF156_Msk
+#define IAC_ISR4_IAF157_Pos           (29U)
+#define IAC_ISR4_IAF157_Msk           (0x1UL << IAC_ISR4_IAF157_Pos)             /*!< 0x20000000 */
+#define IAC_ISR4_IAF157               IAC_ISR4_IAF157_Msk
+
+/*******************  Bits definition for IAC_ICR0 register *******************/
+#define IAC_ICR0_IACF0_Pos            (0U)
+#define IAC_ICR0_IACF0_Msk            (0x1UL << IAC_ICR0_IACF0_Pos)               /*!< 0x00000001 */
+#define IAC_ICR0_IACF0                IAC_ICR0_IACF0_Msk
+#define IAC_ICR0_IACF1_Pos            (1U)
+#define IAC_ICR0_IACF1_Msk            (0x1UL << IAC_ICR0_IACF1_Pos)               /*!< 0x00000002 */
+#define IAC_ICR0_IACF1                IAC_ICR0_IACF1_Msk
+#define IAC_ICR0_IACF2_Pos            (2U)
+#define IAC_ICR0_IACF2_Msk            (0x1UL << IAC_ICR0_IACF2_Pos)               /*!< 0x00000004 */
+#define IAC_ICR0_IACF2                IAC_ICR0_IACF2_Msk
+#define IAC_ICR0_IACF3_Pos            (3U)
+#define IAC_ICR0_IACF3_Msk            (0x1UL << IAC_ICR0_IACF3_Pos)               /*!< 0x00000008 */
+#define IAC_ICR0_IACF3                IAC_ICR0_IACF3_Msk
+#define IAC_ICR0_IACF4_Pos            (4U)
+#define IAC_ICR0_IACF4_Msk            (0x1UL << IAC_ICR0_IACF4_Pos)               /*!< 0x00000010 */
+#define IAC_ICR0_IACF4                IAC_ICR0_IACF4_Msk
+#define IAC_ICR0_IACF5_Pos            (5U)
+#define IAC_ICR0_IACF5_Msk            (0x1UL << IAC_ICR0_IACF5_Pos)               /*!< 0x00000020 */
+#define IAC_ICR0_IACF5                IAC_ICR0_IACF5_Msk
+#define IAC_ICR0_IACF6_Pos            (6U)
+#define IAC_ICR0_IACF6_Msk            (0x1UL << IAC_ICR0_IACF6_Pos)               /*!< 0x00000040 */
+#define IAC_ICR0_IACF6                IAC_ICR0_IACF6_Msk
+#define IAC_ICR0_IACF8_Pos            (8U)
+#define IAC_ICR0_IACF8_Msk            (0x1UL << IAC_ICR0_IACF8_Pos)               /*!< 0x00000100 */
+#define IAC_ICR0_IACF8                IAC_ICR0_IACF8_Msk
+#define IAC_ICR0_IACF9_Pos            (9U)
+#define IAC_ICR0_IACF9_Msk            (0x1UL << IAC_ICR0_IACF9_Pos)               /*!< 0x00000200 */
+#define IAC_ICR0_IACF9                IAC_ICR0_IACF9_Msk
+#define IAC_ICR0_IACF10_Pos           (10U)
+#define IAC_ICR0_IACF10_Msk           (0x1UL << IAC_ICR0_IACF10_Pos)              /*!< 0x00000400 */
+#define IAC_ICR0_IACF10               IAC_ICR0_IACF10_Msk
+#define IAC_ICR0_IACF11_Pos           (11U)
+#define IAC_ICR0_IACF11_Msk           (0x1UL << IAC_ICR0_IACF11_Pos)              /*!< 0x00000800 */
+#define IAC_ICR0_IACF11               IAC_ICR0_IACF11_Msk
+#define IAC_ICR0_IACF12_Pos           (12U)
+#define IAC_ICR0_IACF12_Msk           (0x1UL << IAC_ICR0_IACF12_Pos)              /*!< 0x00001000 */
+#define IAC_ICR0_IACF12               IAC_ICR0_IACF12_Msk
+#define IAC_ICR0_IACF13_Pos           (13U)
+#define IAC_ICR0_IACF13_Msk           (0x1UL << IAC_ICR0_IACF13_Pos)              /*!< 0x00002000 */
+#define IAC_ICR0_IACF13               IAC_ICR0_IACF13_Msk
+#define IAC_ICR0_IACF14_Pos           (14U)
+#define IAC_ICR0_IACF14_Msk           (0x1UL << IAC_ICR0_IACF14_Pos)              /*!< 0x00004000 */
+#define IAC_ICR0_IACF14               IAC_ICR0_IACF14_Msk
+#define IAC_ICR0_IACF15_Pos           (15U)
+#define IAC_ICR0_IACF15_Msk           (0x1UL << IAC_ICR0_IACF15_Pos)              /*!< 0x00008000 */
+#define IAC_ICR0_IACF15               IAC_ICR0_IACF15_Msk
+#define IAC_ICR0_IACF16_Pos           (16U)
+#define IAC_ICR0_IACF16_Msk           (0x1UL << IAC_ICR0_IACF16_Pos)              /*!< 0x00010000 */
+#define IAC_ICR0_IACF16               IAC_ICR0_IACF16_Msk
+#define IAC_ICR0_IACF17_Pos           (17U)
+#define IAC_ICR0_IACF17_Msk           (0x1UL << IAC_ICR0_IACF17_Pos)              /*!< 0x00020000 */
+#define IAC_ICR0_IACF17               IAC_ICR0_IACF17_Msk
+#define IAC_ICR0_IACF18_Pos           (18U)
+#define IAC_ICR0_IACF18_Msk           (0x1UL << IAC_ICR0_IACF18_Pos)              /*!< 0x00040000 */
+#define IAC_ICR0_IACF18               IAC_ICR0_IACF18_Msk
+#define IAC_ICR0_IACF19_Pos           (19U)
+#define IAC_ICR0_IACF19_Msk           (0x1UL << IAC_ICR0_IACF19_Pos)              /*!< 0x00080000 */
+#define IAC_ICR0_IACF19               IAC_ICR0_IACF19_Msk
+#define IAC_ICR0_IACF20_Pos           (20U)
+#define IAC_ICR0_IACF20_Msk           (0x1UL << IAC_ICR0_IACF20_Pos)              /*!< 0x00100000 */
+#define IAC_ICR0_IACF20               IAC_ICR0_IACF20_Msk
+#define IAC_ICR0_IACF21_Pos           (21U)
+#define IAC_ICR0_IACF21_Msk           (0x1UL << IAC_ICR0_IACF21_Pos)              /*!< 0x00200000 */
+#define IAC_ICR0_IACF21               IAC_ICR0_IACF21_Msk
+#define IAC_ICR0_IACF22_Pos           (22U)
+#define IAC_ICR0_IACF22_Msk           (0x1UL << IAC_ICR0_IACF22_Pos)              /*!< 0x00400000 */
+#define IAC_ICR0_IACF22               IAC_ICR0_IACF22_Msk
+#define IAC_ICR0_IACF23_Pos           (23U)
+#define IAC_ICR0_IACF23_Msk           (0x1UL << IAC_ICR0_IACF23_Pos)              /*!< 0x00800000 */
+#define IAC_ICR0_IACF23               IAC_ICR0_IACF23_Msk
+#define IAC_ICR0_IACF24_Pos           (24U)
+#define IAC_ICR0_IACF24_Msk           (0x1UL << IAC_ICR0_IACF24_Pos)              /*!< 0x01000000 */
+#define IAC_ICR0_IACF24               IAC_ICR0_IACF24_Msk
+#define IAC_ICR0_IACF25_Pos           (25U)
+#define IAC_ICR0_IACF25_Msk           (0x1UL << IAC_ICR0_IACF25_Pos)              /*!< 0x02000000 */
+#define IAC_ICR0_IACF25               IAC_ICR0_IACF25_Msk
+#define IAC_ICR0_IACF26_Pos           (26U)
+#define IAC_ICR0_IACF26_Msk           (0x1UL << IAC_ICR0_IACF26_Pos)              /*!< 0x04000000 */
+#define IAC_ICR0_IACF26               IAC_ICR0_IACF26_Msk
+#define IAC_ICR0_IACF27_Pos           (27U)
+#define IAC_ICR0_IACF27_Msk           (0x1UL << IAC_ICR0_IACF27_Pos)              /*!< 0x08000000 */
+#define IAC_ICR0_IACF27               IAC_ICR0_IACF27_Msk
+#define IAC_ICR0_IACF28_Pos           (28U)
+#define IAC_ICR0_IACF28_Msk           (0x1UL << IAC_ICR0_IACF28_Pos)              /*!< 0x10000000 */
+#define IAC_ICR0_IACF28               IAC_ICR0_IACF28_Msk
+#define IAC_ICR0_IACF29_Pos           (29U)
+#define IAC_ICR0_IACF29_Msk           (0x1UL << IAC_ICR0_IACF29_Pos)              /*!< 0x20000000 */
+#define IAC_ICR0_IACF29               IAC_ICR0_IACF29_Msk
+#define IAC_ICR0_IACF30_Pos           (30U)
+#define IAC_ICR0_IACF30_Msk           (0x1UL << IAC_ICR0_IACF30_Pos)              /*!< 0x40000000 */
+#define IAC_ICR0_IACF30               IAC_ICR0_IACF30_Msk
+#define IAC_ICR0_IACF31_Pos           (31U)
+#define IAC_ICR0_IACF31_Msk           (0x1UL << IAC_ICR0_IACF31_Pos)              /*!< 0x80000000 */
+#define IAC_ICR0_IACF31               IAC_ICR0_IACF31_Msk
+
+/*******************  Bits definition for IAC_ICR1 register *******************/
+#define IAC_ICR1_IACF32_Pos           (0U)
+#define IAC_ICR1_IACF32_Msk           (0x1UL << IAC_ICR1_IACF32_Pos)              /*!< 0x00000001 */
+#define IAC_ICR1_IACF32               IAC_ICR1_IACF32_Msk
+#define IAC_ICR1_IACF33_Pos           (1U)
+#define IAC_ICR1_IACF33_Msk           (0x1UL << IAC_ICR1_IACF33_Pos)              /*!< 0x00000002 */
+#define IAC_ICR1_IACF33               IAC_ICR1_IACF33_Msk
+#define IAC_ICR1_IACF34_Pos           (2U)
+#define IAC_ICR1_IACF34_Msk           (0x1UL << IAC_ICR1_IACF34_Pos)              /*!< 0x00000004 */
+#define IAC_ICR1_IACF34               IAC_ICR1_IACF34_Msk
+#define IAC_ICR1_IACF35_Pos           (3U)
+#define IAC_ICR1_IACF35_Msk           (0x1UL << IAC_ICR1_IACF35_Pos)              /*!< 0x00000008 */
+#define IAC_ICR1_IACF35               IAC_ICR1_IACF35_Msk
+#define IAC_ICR1_IACF36_Pos           (4U)
+#define IAC_ICR1_IACF36_Msk           (0x1UL << IAC_ICR1_IACF36_Pos)              /*!< 0x00000010 */
+#define IAC_ICR1_IACF36               IAC_ICR1_IACF36_Msk
+#define IAC_ICR1_IACF37_Pos           (5U)
+#define IAC_ICR1_IACF37_Msk           (0x1UL << IAC_ICR1_IACF37_Pos)              /*!< 0x00000020 */
+#define IAC_ICR1_IACF37               IAC_ICR1_IACF37_Msk
+#define IAC_ICR1_IACF38_Pos           (6U)
+#define IAC_ICR1_IACF38_Msk           (0x1UL << IAC_ICR1_IACF38_Pos)              /*!< 0x00000040 */
+#define IAC_ICR1_IACF38               IAC_ICR1_IACF38_Msk
+#define IAC_ICR1_IACF39_Pos           (7U)
+#define IAC_ICR1_IACF39_Msk           (0x1UL << IAC_ICR1_IACF39_Pos)              /*!< 0x00000080 */
+#define IAC_ICR1_IACF39               IAC_ICR1_IACF39_Msk
+#define IAC_ICR1_IACF40_Pos           (8U)
+#define IAC_ICR1_IACF40_Msk           (0x1UL << IAC_ICR1_IACF40_Pos)              /*!< 0x00000100 */
+#define IAC_ICR1_IACF40               IAC_ICR1_IACF40_Msk
+#define IAC_ICR1_IACF41_Pos           (9U)
+#define IAC_ICR1_IACF41_Msk           (0x1UL << IAC_ICR1_IACF41_Pos)              /*!< 0x00000200 */
+#define IAC_ICR1_IACF41               IAC_ICR1_IACF41_Msk
+#define IAC_ICR1_IACF42_Pos           (10U)
+#define IAC_ICR1_IACF42_Msk           (0x1UL << IAC_ICR1_IACF42_Pos)              /*!< 0x00000400 */
+#define IAC_ICR1_IACF42               IAC_ICR1_IACF42_Msk
+#define IAC_ICR1_IACF43_Pos           (11U)
+#define IAC_ICR1_IACF43_Msk           (0x1UL << IAC_ICR1_IACF43_Pos)              /*!< 0x00000800 */
+#define IAC_ICR1_IACF43               IAC_ICR1_IACF43_Msk
+#define IAC_ICR1_IACF44_Pos           (12U)
+#define IAC_ICR1_IACF44_Msk           (0x1UL << IAC_ICR1_IACF44_Pos)              /*!< 0x00001000 */
+#define IAC_ICR1_IACF44               IAC_ICR1_IACF44_Msk
+#define IAC_ICR1_IACF45_Pos           (13U)
+#define IAC_ICR1_IACF45_Msk           (0x1UL << IAC_ICR1_IACF45_Pos)              /*!< 0x00002000 */
+#define IAC_ICR1_IACF45               IAC_ICR1_IACF45_Msk
+#define IAC_ICR1_IACF46_Pos           (14U)
+#define IAC_ICR1_IACF46_Msk           (0x1UL << IAC_ICR1_IACF46_Pos)              /*!< 0x00004000 */
+#define IAC_ICR1_IACF46               IAC_ICR1_IACF46_Msk
+#define IAC_ICR1_IACF47_Pos           (15U)
+#define IAC_ICR1_IACF47_Msk           (0x1UL << IAC_ICR1_IACF47_Pos)              /*!< 0x00008000 */
+#define IAC_ICR1_IACF47               IAC_ICR1_IACF47_Msk
+#define IAC_ICR1_IACF48_Pos           (16U)
+#define IAC_ICR1_IACF48_Msk           (0x1UL << IAC_ICR1_IACF48_Pos)              /*!< 0x00010000 */
+#define IAC_ICR1_IACF48               IAC_ICR1_IACF48_Msk
+#define IAC_ICR1_IACF49_Pos           (17U)
+#define IAC_ICR1_IACF49_Msk           (0x1UL << IAC_ICR1_IACF49_Pos)              /*!< 0x00020000 */
+#define IAC_ICR1_IACF49               IAC_ICR1_IACF49_Msk
+#define IAC_ICR1_IACF50_Pos           (18U)
+#define IAC_ICR1_IACF50_Msk           (0x1UL << IAC_ICR1_IACF50_Pos)              /*!< 0x00040000 */
+#define IAC_ICR1_IACF50               IAC_ICR1_IACF50_Msk
+#define IAC_ICR1_IACF51_Pos           (19U)
+#define IAC_ICR1_IACF51_Msk           (0x1UL << IAC_ICR1_IACF51_Pos)              /*!< 0x00080000 */
+#define IAC_ICR1_IACF51               IAC_ICR1_IACF51_Msk
+#define IAC_ICR1_IACF52_Pos           (20U)
+#define IAC_ICR1_IACF52_Msk           (0x1UL << IAC_ICR1_IACF52_Pos)              /*!< 0x00100000 */
+#define IAC_ICR1_IACF52               IAC_ICR1_IACF52_Msk
+#define IAC_ICR1_IACF53_Pos           (21U)
+#define IAC_ICR1_IACF53_Msk           (0x1UL << IAC_ICR1_IACF53_Pos)              /*!< 0x00200000 */
+#define IAC_ICR1_IACF53               IAC_ICR1_IACF53_Msk
+#define IAC_ICR1_IACF54_Pos           (22U)
+#define IAC_ICR1_IACF54_Msk           (0x1UL << IAC_ICR1_IACF54_Pos)              /*!< 0x00400000 */
+#define IAC_ICR1_IACF54               IAC_ICR1_IACF54_Msk
+#define IAC_ICR1_IACF55_Pos           (23U)
+#define IAC_ICR1_IACF55_Msk           (0x1UL << IAC_ICR1_IACF55_Pos)              /*!< 0x00800000 */
+#define IAC_ICR1_IACF55               IAC_ICR1_IACF55_Msk
+#define IAC_ICR1_IACF56_Pos           (24U)
+#define IAC_ICR1_IACF56_Msk           (0x1UL << IAC_ICR1_IACF56_Pos)              /*!< 0x01000000 */
+#define IAC_ICR1_IACF56               IAC_ICR1_IACF56_Msk
+#define IAC_ICR1_IACF57_Pos           (25U)
+#define IAC_ICR1_IACF57_Msk           (0x1UL << IAC_ICR1_IACF57_Pos)              /*!< 0x02000000 */
+#define IAC_ICR1_IACF57               IAC_ICR1_IACF57_Msk
+#define IAC_ICR1_IACF58_Pos           (26U)
+#define IAC_ICR1_IACF58_Msk           (0x1UL << IAC_ICR1_IACF58_Pos)              /*!< 0x04000000 */
+#define IAC_ICR1_IACF58               IAC_ICR1_IACF58_Msk
+#define IAC_ICR1_IACF60_Pos           (28U)
+#define IAC_ICR1_IACF60_Msk           (0x1UL << IAC_ICR1_IACF60_Pos)              /*!< 0x10000000 */
+#define IAC_ICR1_IACF60               IAC_ICR1_IACF60_Msk
+#define IAC_ICR1_IACF61_Pos           (29U)
+#define IAC_ICR1_IACF61_Msk           (0x1UL << IAC_ICR1_IACF61_Pos)              /*!< 0x20000000 */
+#define IAC_ICR1_IACF61               IAC_ICR1_IACF61_Msk
+#define IAC_ICR1_IACF62_Pos           (30U)
+#define IAC_ICR1_IACF62_Msk           (0x1UL << IAC_ICR1_IACF62_Pos)              /*!< 0x40000000 */
+#define IAC_ICR1_IACF62               IAC_ICR1_IACF62_Msk
+
+/*******************  Bits definition for IAC_ICR2 register *******************/
+#define IAC_ICR2_IACF64_Pos           (0U)
+#define IAC_ICR2_IACF64_Msk           (0x1UL << IAC_ICR2_IACF64_Pos)              /*!< 0x00000001 */
+#define IAC_ICR2_IACF64               IAC_ICR2_IACF64_Msk
+#define IAC_ICR2_IACF65_Pos           (1U)
+#define IAC_ICR2_IACF65_Msk           (0x1UL << IAC_ICR2_IACF65_Pos)              /*!< 0x00000002 */
+#define IAC_ICR2_IACF65               IAC_ICR2_IACF65_Msk
+#define IAC_ICR2_IACF67_Pos           (3U)
+#define IAC_ICR2_IACF67_Msk           (0x1UL << IAC_ICR2_IACF67_Pos)              /*!< 0x00000008 */
+#define IAC_ICR2_IACF67               IAC_ICR2_IACF67_Msk
+#define IAC_ICR2_IACF68_Pos           (4U)
+#define IAC_ICR2_IACF68_Msk           (0x1UL << IAC_ICR2_IACF68_Pos)              /*!< 0x00000010 */
+#define IAC_ICR2_IACF68               IAC_ICR2_IACF68_Msk
+#define IAC_ICR2_IACF69_Pos           (5U)
+#define IAC_ICR2_IACF69_Msk           (0x1UL << IAC_ICR2_IACF69_Pos)              /*!< 0x00000020 */
+#define IAC_ICR2_IACF69               IAC_ICR2_IACF69_Msk
+#define IAC_ICR2_IACF76_Pos           (12U)
+#define IAC_ICR2_IACF76_Msk           (0x1UL << IAC_ICR2_IACF76_Pos)              /*!< 0x00001000 */
+#define IAC_ICR2_IACF76               IAC_ICR2_IACF76_Msk
+#define IAC_ICR2_IACF77_Pos           (13U)
+#define IAC_ICR2_IACF77_Msk           (0x1UL << IAC_ICR2_IACF77_Pos)              /*!< 0x00002000 */
+#define IAC_ICR2_IACF77               IAC_ICR2_IACF77_Msk
+#define IAC_ICR2_IACF78_Pos           (14U)
+#define IAC_ICR2_IACF78_Msk           (0x1UL << IAC_ICR2_IACF78_Pos)              /*!< 0x00004000 */
+#define IAC_ICR2_IACF78               IAC_ICR2_IACF78_Msk
+#define IAC_ICR2_IACF79_Pos           (15U)
+#define IAC_ICR2_IACF79_Msk           (0x1UL << IAC_ICR2_IACF79_Pos)              /*!< 0x00008000 */
+#define IAC_ICR2_IACF79               IAC_ICR2_IACF79_Msk
+#define IAC_ICR2_IACF80_Pos           (16U)
+#define IAC_ICR2_IACF80_Msk           (0x1UL << IAC_ICR2_IACF80_Pos)              /*!< 0x00010000 */
+#define IAC_ICR2_IACF80               IAC_ICR2_IACF80_Msk
+#define IAC_ICR2_IACF81_Pos           (17U)
+#define IAC_ICR2_IACF81_Msk           (0x1UL << IAC_ICR2_IACF81_Pos)              /*!< 0x00020000 */
+#define IAC_ICR2_IACF81               IAC_ICR2_IACF81_Msk
+#define IAC_ICR2_IACF82_Pos           (18U)
+#define IAC_ICR2_IACF82_Msk           (0x1UL << IAC_ICR2_IACF82_Pos)              /*!< 0x00040000 */
+#define IAC_ICR2_IACF82               IAC_ICR2_IACF82_Msk
+#define IAC_ICR2_IACF83_Pos           (19U)
+#define IAC_ICR2_IACF83_Msk           (0x1UL << IAC_ICR2_IACF83_Pos)              /*!< 0x00080000 */
+#define IAC_ICR2_IACF83               IAC_ICR2_IACF83_Msk
+#define IAC_ICR2_IACF84_Pos           (20U)
+#define IAC_ICR2_IACF84_Msk           (0x1UL << IAC_ICR2_IACF84_Pos)              /*!< 0x00100000 */
+#define IAC_ICR2_IACF84               IAC_ICR2_IACF84_Msk
+#define IAC_ICR2_IACF86_Pos           (22U)
+#define IAC_ICR2_IACF86_Msk           (0x1UL << IAC_ICR2_IACF86_Pos)              /*!< 0x00400000 */
+#define IAC_ICR2_IACF86               IAC_ICR2_IACF86_Msk
+#define IAC_ICR2_IACF87_Pos           (23U)
+#define IAC_ICR2_IACF87_Msk           (0x1UL << IAC_ICR2_IACF87_Pos)              /*!< 0x00800000 */
+#define IAC_ICR2_IACF87               IAC_ICR2_IACF87_Msk
+#define IAC_ICR2_IACF88_Pos           (24U)
+#define IAC_ICR2_IACF88_Msk           (0x1UL << IAC_ICR2_IACF88_Pos)              /*!< 0x01000000 */
+#define IAC_ICR2_IACF88               IAC_ICR2_IACF88_Msk
+#define IAC_ICR2_IACF89_Pos           (25U)
+#define IAC_ICR2_IACF89_Msk           (0x1UL << IAC_ICR2_IACF89_Pos)              /*!< 0x02000000 */
+#define IAC_ICR2_IACF89               IAC_ICR2_IACF89_Msk
+#define IAC_ICR2_IACF90_Pos           (26U)
+#define IAC_ICR2_IACF90_Msk           (0x1UL << IAC_ICR2_IACF90_Pos)              /*!< 0x04000000 */
+#define IAC_ICR2_IACF90               IAC_ICR2_IACF90_Msk
+#define IAC_ICR2_IACF92_Pos           (28U)
+#define IAC_ICR2_IACF92_Msk           (0x1UL << IAC_ICR2_IACF92_Pos)              /*!< 0x10000000 */
+#define IAC_ICR2_IACF92               IAC_ICR2_IACF92_Msk
+#define IAC_ICR2_IACF93_Pos           (29U)
+#define IAC_ICR2_IACF93_Msk           (0x1UL << IAC_ICR2_IACF93_Pos)              /*!< 0x20000000 */
+#define IAC_ICR2_IACF93               IAC_ICR2_IACF93_Msk
+#define IAC_ICR2_IACF94_Pos           (30U)
+#define IAC_ICR2_IACF94_Msk           (0x1UL << IAC_ICR2_IACF94_Pos)              /*!< 0x40000000 */
+#define IAC_ICR2_IACF94               IAC_ICR2_IACF94_Msk
+#define IAC_ICR2_IACF95_Pos           (31U)
+#define IAC_ICR2_IACF95_Msk           (0x1UL << IAC_ICR2_IACF95_Pos)              /*!< 0x80000000 */
+#define IAC_ICR2_IACF95               IAC_ICR2_IACF95_Msk
+
+/*******************  Bits definition for IAC_ICR3 register *******************/
+#define IAC_ICR3_IACF96_Pos           (0U)
+#define IAC_ICR3_IACF96_Msk           (0x1UL << IAC_ICR3_IACF96_Pos)              /*!< 0x00000001 */
+#define IAC_ICR3_IACF96               IAC_ICR3_IACF96_Msk
+#define IAC_ICR3_IACF97_Pos           (1U)
+#define IAC_ICR3_IACF97_Msk           (0x1UL << IAC_ICR3_IACF97_Pos)              /*!< 0x00000002 */
+#define IAC_ICR3_IACF97               IAC_ICR3_IACF97_Msk
+#define IAC_ICR3_IACF98_Pos           (2U)
+#define IAC_ICR3_IACF98_Msk           (0x1UL << IAC_ICR3_IACF98_Pos)              /*!< 0x00000004 */
+#define IAC_ICR3_IACF98               IAC_ICR3_IACF98_Msk
+#define IAC_ICR3_IACF99_Pos           (3U)
+#define IAC_ICR3_IACF99_Msk           (0x1UL << IAC_ICR3_IACF99_Pos)              /*!< 0x00000008 */
+#define IAC_ICR3_IACF99               IAC_ICR3_IACF99_Msk
+#define IAC_ICR3_IACF100_Pos          (4U)
+#define IAC_ICR3_IACF100_Msk          (0x1UL << IAC_ICR3_IACF100_Pos)             /*!< 0x00000010 */
+#define IAC_ICR3_IACF100              IAC_ICR3_IACF100_Msk
+#define IAC_ICR3_IACF101_Pos          (5U)
+#define IAC_ICR3_IACF101_Msk          (0x1UL << IAC_ICR3_IACF101_Pos)             /*!< 0x00000020 */
+#define IAC_ICR3_IACF101              IAC_ICR3_IACF101_Msk
+#define IAC_ICR3_IACF102_Pos          (6U)
+#define IAC_ICR3_IACF102_Msk          (0x1UL << IAC_ICR3_IACF102_Pos)             /*!< 0x00000040 */
+#define IAC_ICR3_IACF102              IAC_ICR3_IACF102_Msk
+#define IAC_ICR3_IACF103_Pos          (7U)
+#define IAC_ICR3_IACF103_Msk          (0x1UL << IAC_ICR3_IACF103_Pos)             /*!< 0x00000080 */
+#define IAC_ICR3_IACF103              IAC_ICR3_IACF103_Msk
+#define IAC_ICR3_IACF104_Pos          (8U)
+#define IAC_ICR3_IACF104_Msk          (0x1UL << IAC_ICR3_IACF104_Pos)             /*!< 0x00000100 */
+#define IAC_ICR3_IACF104              IAC_ICR3_IACF104_Msk
+#define IAC_ICR3_IACF106_Pos          (10U)
+#define IAC_ICR3_IACF106_Msk          (0x1UL << IAC_ICR3_IACF106_Pos)             /*!< 0x00000400 */
+#define IAC_ICR3_IACF106              IAC_ICR3_IACF106_Msk
+
+/*******************  Bits definition for IAC_ICR4 register *******************/
+#define IAC_ICR4_IACF128_Pos          (0U)
+#define IAC_ICR4_IACF128_Msk          (0x1UL << IAC_ICR4_IACF128_Pos)             /*!< 0x00000001 */
+#define IAC_ICR4_IACF128              IAC_ICR4_IACF128_Msk
+#define IAC_ICR4_IACF129_Pos          (1U)
+#define IAC_ICR4_IACF129_Msk          (0x1UL << IAC_ICR4_IACF129_Pos)             /*!< 0x00000002 */
+#define IAC_ICR4_IACF129              IAC_ICR4_IACF129_Msk
+#define IAC_ICR4_IACF130_Pos          (2U)
+#define IAC_ICR4_IACF130_Msk          (0x1UL << IAC_ICR4_IACF130_Pos)             /*!< 0x00000004 */
+#define IAC_ICR4_IACF130              IAC_ICR4_IACF130_Msk
+#define IAC_ICR4_IACF131_Pos          (3U)
+#define IAC_ICR4_IACF131_Msk          (0x1UL << IAC_ICR4_IACF131_Pos)             /*!< 0x00000008 */
+#define IAC_ICR4_IACF131              IAC_ICR4_IACF131_Msk
+#define IAC_ICR4_IACF133_Pos          (5U)
+#define IAC_ICR4_IACF133_Msk          (0x1UL << IAC_ICR4_IACF133_Pos)             /*!< 0x00000020 */
+#define IAC_ICR4_IACF133              IAC_ICR4_IACF133_Msk
+#define IAC_ICR4_IACF134_Pos          (6U)
+#define IAC_ICR4_IACF134_Msk          (0x1UL << IAC_ICR4_IACF134_Pos)             /*!< 0x00000040 */
+#define IAC_ICR4_IACF134              IAC_ICR4_IACF134_Msk
+#define IAC_ICR4_IACF135_Pos          (7U)
+#define IAC_ICR4_IACF135_Msk          (0x1UL << IAC_ICR4_IACF135_Pos)             /*!< 0x00000080 */
+#define IAC_ICR4_IACF135              IAC_ICR4_IACF135_Msk
+#define IAC_ICR4_IACF136_Pos          (8U)
+#define IAC_ICR4_IACF136_Msk          (0x1UL << IAC_ICR4_IACF136_Pos)             /*!< 0x00000100 */
+#define IAC_ICR4_IACF136              IAC_ICR4_IACF136_Msk
+#define IAC_ICR4_IACF137_Pos          (9U)
+#define IAC_ICR4_IACF137_Msk          (0x1UL << IAC_ICR4_IACF137_Pos)             /*!< 0x00000200 */
+#define IAC_ICR4_IACF137              IAC_ICR4_IACF137_Msk
+#define IAC_ICR4_IACF138_Pos          (10U)
+#define IAC_ICR4_IACF138_Msk          (0x1UL << IAC_ICR4_IACF138_Pos)             /*!< 0x00000400 */
+#define IAC_ICR4_IACF138              IAC_ICR4_IACF138_Msk
+#define IAC_ICR4_IACF139_Pos          (11U)
+#define IAC_ICR4_IACF139_Msk          (0x1UL << IAC_ICR4_IACF139_Pos)             /*!< 0x00000800 */
+#define IAC_ICR4_IACF139              IAC_ICR4_IACF139_Msk
+#define IAC_ICR4_IACF140_Pos          (12U)
+#define IAC_ICR4_IACF140_Msk          (0x1UL << IAC_ICR4_IACF140_Pos)             /*!< 0x00001000 */
+#define IAC_ICR4_IACF140              IAC_ICR4_IACF140_Msk
+#define IAC_ICR4_IACF141_Pos          (13U)
+#define IAC_ICR4_IACF141_Msk          (0x1UL << IAC_ICR4_IACF141_Pos)             /*!< 0x00002000 */
+#define IAC_ICR4_IACF141              IAC_ICR4_IACF141_Msk
+#define IAC_ICR4_IACF142_Pos          (14U)
+#define IAC_ICR4_IACF142_Msk          (0x1UL << IAC_ICR4_IACF142_Pos)             /*!< 0x00004000 */
+#define IAC_ICR4_IACF142              IAC_ICR4_IACF142_Msk
+#define IAC_ICR4_IACF143_Pos          (15U)
+#define IAC_ICR4_IACF143_Msk          (0x1UL << IAC_ICR4_IACF143_Pos)             /*!< 0x00008000 */
+#define IAC_ICR4_IACF143              IAC_ICR4_IACF143_Msk
+#define IAC_ICR4_IACF144_Pos          (16U)
+#define IAC_ICR4_IACF144_Msk          (0x1UL << IAC_ICR4_IACF144_Pos)             /*!< 0x00010000 */
+#define IAC_ICR4_IACF144              IAC_ICR4_IACF144_Msk
+#define IAC_ICR4_IACF145_Pos          (17U)
+#define IAC_ICR4_IACF145_Msk          (0x1UL << IAC_ICR4_IACF145_Pos)             /*!< 0x00020000 */
+#define IAC_ICR4_IACF145              IAC_ICR4_IACF145_Msk
+#define IAC_ICR4_IACF146_Pos          (18U)
+#define IAC_ICR4_IACF146_Msk          (0x1UL << IAC_ICR4_IACF146_Pos)             /*!< 0x00040000 */
+#define IAC_ICR4_IACF146              IAC_ICR4_IACF146_Msk
+#define IAC_ICR4_IACF147_Pos          (19U)
+#define IAC_ICR4_IACF147_Msk          (0x1UL << IAC_ICR4_IACF147_Pos)             /*!< 0x00080000 */
+#define IAC_ICR4_IACF147              IAC_ICR4_IACF147_Msk
+#define IAC_ICR4_IACF149_Pos          (21U)
+#define IAC_ICR4_IACF149_Msk          (0x1UL << IAC_ICR4_IACF149_Pos)             /*!< 0x00200000 */
+#define IAC_ICR4_IACF149              IAC_ICR4_IACF149_Msk
+#define IAC_ICR4_IACF150_Pos          (22U)
+#define IAC_ICR4_IACF150_Msk          (0x1UL << IAC_ICR4_IACF150_Pos)             /*!< 0x00400000 */
+#define IAC_ICR4_IACF150              IAC_ICR4_IACF150_Msk
+#define IAC_ICR4_IACF151_Pos          (23U)
+#define IAC_ICR4_IACF151_Msk          (0x1UL << IAC_ICR4_IACF151_Pos)             /*!< 0x00800000 */
+#define IAC_ICR4_IACF151              IAC_ICR4_IACF151_Msk
+#define IAC_ICR4_IACF152_Pos          (24U)
+#define IAC_ICR4_IACF152_Msk          (0x1UL << IAC_ICR4_IACF152_Pos)             /*!< 0x01000000 */
+#define IAC_ICR4_IACF152              IAC_ICR4_IACF152_Msk
+#define IAC_ICR4_IACF153_Pos          (25U)
+#define IAC_ICR4_IACF153_Msk          (0x1UL << IAC_ICR4_IACF153_Pos)             /*!< 0x02000000 */
+#define IAC_ICR4_IACF153              IAC_ICR4_IACF153_Msk
+#define IAC_ICR4_IACF155_Pos          (27U)
+#define IAC_ICR4_IACF155_Msk          (0x1UL << IAC_ICR4_IACF155_Pos)             /*!< 0x08000000 */
+#define IAC_ICR4_IACF155              IAC_ICR4_IACF155_Msk
+#define IAC_ICR4_IACF156_Pos          (28U)
+#define IAC_ICR4_IACF156_Msk          (0x1UL << IAC_ICR4_IACF156_Pos)             /*!< 0x10000000 */
+#define IAC_ICR4_IACF156              IAC_ICR4_IACF156_Msk
+#define IAC_ICR4_IACF157_Pos          (29U)
+#define IAC_ICR4_IACF157_Msk          (0x1UL << IAC_ICR4_IACF157_Pos)             /*!< 0x20000000 */
+#define IAC_ICR4_IACF157              IAC_ICR4_IACF157_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 ICACHE                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for ICACHE_CR register  *******************/
+#define ICACHE_CR_EN_Pos               (0U)
+#define ICACHE_CR_EN_Msk               (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
+#define ICACHE_CR_EN                   ICACHE_CR_EN_Msk                        /*!< Enable */
+#define ICACHE_CR_CACHEINV_Pos         (1U)
+#define ICACHE_CR_CACHEINV_Msk         (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
+#define ICACHE_CR_CACHEINV             ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
+#define ICACHE_CR_WAYSEL_Pos           (2U)
+#define ICACHE_CR_WAYSEL_Msk           (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
+#define ICACHE_CR_WAYSEL               ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
+#define ICACHE_CR_HITMEN_Pos           (16U)
+#define ICACHE_CR_HITMEN_Msk           (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
+#define ICACHE_CR_HITMEN               ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
+#define ICACHE_CR_MISSMEN_Pos          (17U)
+#define ICACHE_CR_MISSMEN_Msk          (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
+#define ICACHE_CR_MISSMEN              ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
+#define ICACHE_CR_HITMRST_Pos          (18U)
+#define ICACHE_CR_HITMRST_Msk          (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
+#define ICACHE_CR_HITMRST              ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
+#define ICACHE_CR_MISSMRST_Pos         (19U)
+#define ICACHE_CR_MISSMRST_Msk         (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
+#define ICACHE_CR_MISSMRST             ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
+
+/******************  Bit definition for ICACHE_SR register  *******************/
+#define ICACHE_SR_BUSYF_Pos            (0U)
+#define ICACHE_SR_BUSYF_Msk            (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
+#define ICACHE_SR_BUSYF                ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
+#define ICACHE_SR_BSYENDF_Pos          (1U)
+#define ICACHE_SR_BSYENDF_Msk          (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
+#define ICACHE_SR_BSYENDF              ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
+#define ICACHE_SR_ERRF_Pos             (2U)
+#define ICACHE_SR_ERRF_Msk             (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
+#define ICACHE_SR_ERRF                 ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
+
+/******************  Bit definition for ICACHE_IER register  ******************/
+#define ICACHE_IER_BSYENDIE_Pos        (1U)
+#define ICACHE_IER_BSYENDIE_Msk        (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
+#define ICACHE_IER_BSYENDIE            ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
+#define ICACHE_IER_ERRIE_Pos           (2U)
+#define ICACHE_IER_ERRIE_Msk           (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
+#define ICACHE_IER_ERRIE               ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
+
+/******************  Bit definition for ICACHE_FCR register  ******************/
+#define ICACHE_FCR_CBSYENDF_Pos        (1U)
+#define ICACHE_FCR_CBSYENDF_Msk        (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
+#define ICACHE_FCR_CBSYENDF            ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
+#define ICACHE_FCR_CERRF_Pos           (2U)
+#define ICACHE_FCR_CERRF_Msk           (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
+#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
+
+/******************  Bit definition for ICACHE_HMONR register  ****************/
+#define ICACHE_HMONR_HITMON_Pos         (0U)
+#define ICACHE_HMONR_HITMON_Msk         (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)/*!< 0xFFFFFFFF */
+#define ICACHE_HMONR_HITMON             ICACHE_HMONR_HITMON_Msk                /*!< Cache hit monitor register */
+
+/******************  Bit definition for ICACHE_MMONR register  ****************/
+#define ICACHE_MMONR_MISSMON_Pos        (0U)
+#define ICACHE_MMONR_MISSMON_Msk        (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
+#define ICACHE_MMONR_MISSMON            ICACHE_MMONR_MISSMON_Msk               /*!< Cache miss monitor register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent Watchdog (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos             (0U)
+#define IWDG_KR_KEY_Msk             (0xFFFFUL << IWDG_KR_KEY_Pos)          /*!< 0x0000FFFF */
+#define IWDG_KR_KEY                 IWDG_KR_KEY_Msk                       /*!< Key value (write only, read 0x0000) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos              (0U)
+#define IWDG_PR_PR_Msk              (0xFUL << IWDG_PR_PR_Pos)              /*!< 0x0000000F */
+#define IWDG_PR_PR                  IWDG_PR_PR_Msk                        /*!< Prescaler divider */
+#define IWDG_PR_PR_0                (0x1UL << IWDG_PR_PR_Pos)              /*!< 0x00000001 */
+#define IWDG_PR_PR_1                (0x2UL << IWDG_PR_PR_Pos)              /*!< 0x00000002 */
+#define IWDG_PR_PR_2                (0x4UL << IWDG_PR_PR_Pos)              /*!< 0x00000004 */
+#define IWDG_PR_PR_3                (0x8UL << IWDG_PR_PR_Pos)              /*!< 0x00000008 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos             (0U)
+#define IWDG_RLR_RL_Msk             (0xFFFUL << IWDG_RLR_RL_Pos)           /*!< 0x00000FFF */
+#define IWDG_RLR_RL                 IWDG_RLR_RL_Msk                       /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos             (0U)
+#define IWDG_SR_PVU_Msk             (0x1UL << IWDG_SR_PVU_Pos)             /*!< 0x00000001 */
+#define IWDG_SR_PVU                 IWDG_SR_PVU_Msk                       /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos             (1U)
+#define IWDG_SR_RVU_Msk             (0x1UL << IWDG_SR_RVU_Pos)             /*!< 0x00000002 */
+#define IWDG_SR_RVU                 IWDG_SR_RVU_Msk                       /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos             (2U)
+#define IWDG_SR_WVU_Msk             (0x1UL << IWDG_SR_WVU_Pos)             /*!< 0x00000004 */
+#define IWDG_SR_WVU                 IWDG_SR_WVU_Msk                       /*!< Watchdog counter window value update */
+#define IWDG_SR_EWU_Pos             (3U)
+#define IWDG_SR_EWU_Msk             (0x1UL << IWDG_SR_EWU_Pos)             /*!< 0x00000008 */
+#define IWDG_SR_EWU                 IWDG_SR_EWU_Msk                       /*!< Watchdog interrupt comparator value update */
+#define IWDG_SR_ONF_Pos             (8U)
+#define IWDG_SR_ONF_Msk             (0x1UL << IWDG_SR_ONF_Pos)             /*!< 0x00000100 */
+#define IWDG_SR_ONF                 IWDG_SR_ONF_Msk                       /*!< Watchdog Enable status bit */
+#define IWDG_SR_EWIF_Pos            (15U)
+#define IWDG_SR_EWIF_Msk            (0x1UL << IWDG_SR_EWIF_Pos)            /*!< 0x00008000 */
+#define IWDG_SR_EWIF                IWDG_SR_EWIF_Msk                      /*!< Watchdog Early Interrupt flag */
+
+/******************  Bit definition for IWDG_WINR register  *******************/
+#define IWDG_WINR_WIN_Pos           (0U)
+#define IWDG_WINR_WIN_Msk           (0xFFFUL << IWDG_WINR_WIN_Pos)         /*!< 0x00000FFF */
+#define IWDG_WINR_WIN               IWDG_WINR_WIN_Msk                     /*!< Watchdog counter window value */
+
+/******************  Bit definition for IWDG_EWCR register  *******************/
+#define IWDG_EWCR_EWIT_Pos          (0U)
+#define IWDG_EWCR_EWIT_Msk          (0xFFFUL << IWDG_EWCR_EWIT_Pos)        /*!< 0x00000FFF */
+#define IWDG_EWCR_EWIT              IWDG_EWCR_EWIT_Msk                    /*!< Watchdog counter window value */
+#define IWDG_EWCR_EWIE_Pos          (15U)
+#define IWDG_EWCR_EWIE_Msk          (0x1UL << IWDG_EWCR_EWIE_Pos)          /*!< 0x00008000 */
+#define IWDG_EWCR_EWIE              IWDG_EWCR_EWIE_Msk                    /*!< Watchdog early interrupt enable */
+
+/*******************  Bit definition for IWDG_ICR register  *******************/
+#define IWDG_ICR_EWIC_Pos           (15U)
+#define IWDG_ICR_EWIC_Msk           (0x1UL << IWDG_ICR_EWIC_Pos)           /*!< 0x00008000 */
+#define IWDG_ICR_EWIC               IWDG_ICR_EWIC_Msk                     /*!< Watchdog early interrupt acknowledge */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)         /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                    /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                       /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                       /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk               /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)            /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                       /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                      /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                    /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)    /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                     /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                    /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                      /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                      /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)              /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                         /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)             /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                        /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)            /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                       /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)             /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                        /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)            /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                       /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)             /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                        /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)             /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                        /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IDMAEN_Pos              (11U)
+#define JPEG_CR_IDMAEN_Msk              (0x1UL << JPEG_CR_IDMAEN_Pos)            /*!< 0x00000800 */
+#define JPEG_CR_IDMAEN                  JPEG_CR_IDMAEN_Msk                       /*!<Input DMA enable */
+#define JPEG_CR_ODMAEN_Pos              (12U)
+#define JPEG_CR_ODMAEN_Msk              (0x1UL << JPEG_CR_ODMAEN_Pos)            /*!< 0x00001000 */
+#define JPEG_CR_ODMAEN                  JPEG_CR_ODMAEN_Msk                       /*!<Output DMA enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)               /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                          /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)               /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                          /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)              /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                         /*!<Input FIFO is not full and is below its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)             /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                        /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)              /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                         /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)             /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                        /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)              /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                         /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)              /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                         /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)               /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                          /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (5U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                       /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (6U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                       /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)    /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                      /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)   /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                     /*!<Data Output FIFO */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                            */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CC1IF_Pos         (0U)
+#define LPTIM_ISR_CC1IF_Msk         (0x1UL << LPTIM_ISR_CC1IF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ISR_CC1IF             LPTIM_ISR_CC1IF_Msk                        /*!< Capture/Compare 1 interrupt flag */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMP1OK_Pos        (3U)
+#define LPTIM_ISR_CMP1OK_Msk        (0x1UL << LPTIM_ISR_CMP1OK_Pos)            /*!< 0x00000008 */
+#define LPTIM_ISR_CMP1OK            LPTIM_ISR_CMP1OK_Msk                       /*!< Compare register 1 update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+#define LPTIM_ISR_UE_Pos            (7U)
+#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
+#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
+#define LPTIM_ISR_REPOK_Pos         (8U)
+#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
+#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
+#define LPTIM_ISR_CC2IF_Pos         (9U)
+#define LPTIM_ISR_CC2IF_Msk         (0x1UL << LPTIM_ISR_CC2IF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ISR_CC2IF             LPTIM_ISR_CC2IF_Msk                        /*!< Capture/Compare 2 interrupt flag */
+#define LPTIM_ISR_CC1OF_Pos         (12U)
+#define LPTIM_ISR_CC1OF_Msk         (0x1UL << LPTIM_ISR_CC1OF_Pos)             /*!< 0x00001000 */
+#define LPTIM_ISR_CC1OF             LPTIM_ISR_CC1OF_Msk                        /*!< Capture/Compare 1 over-capture flag */
+#define LPTIM_ISR_CC2OF_Pos         (13U)
+#define LPTIM_ISR_CC2OF_Msk         (0x1UL << LPTIM_ISR_CC2OF_Pos)             /*!< 0x00002000 */
+#define LPTIM_ISR_CC2OF             LPTIM_ISR_CC2OF_Msk                        /*!< Capture/Compare 2 over-capture flag */
+#define LPTIM_ISR_CMP2OK_Pos        (19U)
+#define LPTIM_ISR_CMP2OK_Msk        (0x1UL << LPTIM_ISR_CMP2OK_Pos)            /*!< 0x00080000 */
+#define LPTIM_ISR_CMP2OK            LPTIM_ISR_CMP2OK_Msk                       /*!< Compare register 2 update OK */
+#define LPTIM_ISR_DIEROK_Pos        (24U)
+#define LPTIM_ISR_DIEROK_Msk        (0x1UL << LPTIM_ISR_DIEROK_Pos)            /*!< 0x01000000 */
+#define LPTIM_ISR_DIEROK            LPTIM_ISR_DIEROK_Msk                       /*!< Interrupt enable register update OK */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CC1CF_Pos         (0U)
+#define LPTIM_ICR_CC1CF_Msk         (0x1UL << LPTIM_ICR_CC1CF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CC1CF              LPTIM_ICR_CC1CF_Msk                       /*!< Capture/Compare 1 clear flag  */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMP1OKCF_Pos      (3U)
+#define LPTIM_ICR_CMP1OKCF_Msk      (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)          /*!< 0x00000008 */
+#define LPTIM_ICR_CMP1OKCF          LPTIM_ICR_CMP1OKCF_Msk                     /*!< Compare register 1 update OK clear flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+#define LPTIM_ICR_UECF_Pos          (7U)
+#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
+#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
+#define LPTIM_ICR_REPOKCF_Pos       (8U)
+#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
+#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
+#define LPTIM_ICR_CC2CF_Pos         (9U)
+#define LPTIM_ICR_CC2CF_Msk         (0x1UL << LPTIM_ICR_CC2CF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ICR_CC2CF             LPTIM_ICR_CC2CF_Msk                        /*!< Capture/Compare 2 clear flag  */
+#define LPTIM_ICR_CC1OCF_Pos        (12U)
+#define LPTIM_ICR_CC1OCF_Msk        (0x1UL << LPTIM_ICR_CC1OCF_Pos)            /*!< 0x00001000 */
+#define LPTIM_ICR_CC1OCF            LPTIM_ICR_CC1OCF_Msk                       /*!< Capture/Compare 1 over-capture clear flag */
+#define LPTIM_ICR_CC2OCF_Pos        (13U)
+#define LPTIM_ICR_CC2OCF_Msk        (0x1UL << LPTIM_ICR_CC2OCF_Pos)            /*!< 0x00002000 */
+#define LPTIM_ICR_CC2OCF            LPTIM_ICR_CC2OCF_Msk                       /*!< Capture/Compare 2 over-capture clear flag */
+#define LPTIM_ICR_CMP2OKCF_Pos      (19U)
+#define LPTIM_ICR_CMP2OKCF_Msk      (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)          /*!< 0x00080000 */
+#define LPTIM_ICR_CMP2OKCF          LPTIM_ICR_CMP2OKCF_Msk                     /*!< Compare register 2 update OK clear flag */
+#define LPTIM_ICR_DIEROKCF_Pos      (24U)
+#define LPTIM_ICR_DIEROKCF_Msk      (0x1UL << LPTIM_ICR_DIEROKCF_Pos)          /*!< 0x01000000 */
+#define LPTIM_ICR_DIEROKCF          LPTIM_ICR_DIEROKCF_Msk                     /*!< Interrupt enable register update OK clear flag */
+
+/******************  Bit definition for LPTIM_DIER register *******************/
+#define LPTIM_DIER_CC1IE_Pos        (0U)
+#define LPTIM_DIER_CC1IE_Msk        (0x1UL << LPTIM_DIER_CC1IE_Pos)            /*!< 0x00000001 */
+#define LPTIM_DIER_CC1IE            LPTIM_DIER_CC1IE_Msk                       /*!< Compare/Compare interrupt enable */
+#define LPTIM_DIER_ARRMIE_Pos        (1U)
+#define LPTIM_DIER_ARRMIE_Msk       (0x1UL << LPTIM_DIER_ARRMIE_Pos)           /*!< 0x00000002 */
+#define LPTIM_DIER_ARRMIE           LPTIM_DIER_ARRMIE_Msk                      /*!< Autoreload match Interrupt Enable */
+#define LPTIM_DIER_EXTTRIGIE_Pos    (2U)
+#define LPTIM_DIER_EXTTRIGIE_Msk    (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)        /*!< 0x00000004 */
+#define LPTIM_DIER_EXTTRIGIE        LPTIM_DIER_EXTTRIGIE_Msk                   /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_DIER_CMP1OKIE_Pos     (3U)
+#define LPTIM_DIER_CMP1OKIE_Msk     (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)         /*!< 0x00000008 */
+#define LPTIM_DIER_CMP1OKIE         LPTIM_DIER_CMP1OKIE_Msk                    /*!< Compare register 1 update OK interrupt enable */
+#define LPTIM_DIER_ARROKIE_Pos      (4U)
+#define LPTIM_DIER_ARROKIE_Msk      (0x1UL << LPTIM_DIER_ARROKIE_Pos)          /*!< 0x00000010 */
+#define LPTIM_DIER_ARROKIE          LPTIM_DIER_ARROKIE_Msk                     /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_DIER_UPIE_Pos         (5U)
+#define LPTIM_DIER_UPIE_Msk         (0x1UL << LPTIM_DIER_UPIE_Pos)             /*!< 0x00000020 */
+#define LPTIM_DIER_UPIE             LPTIM_DIER_UPIE_Msk                        /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_DIER_DOWNIE_Pos       (6U)
+#define LPTIM_DIER_DOWNIE_Msk       (0x1UL << LPTIM_DIER_DOWNIE_Pos)           /*!< 0x00000040 */
+#define LPTIM_DIER_DOWNIE           LPTIM_DIER_DOWNIE_Msk                      /*!< Counter direction change up to down Interrupt Enable */
+#define LPTIM_DIER_UEIE_Pos         (7U)
+#define LPTIM_DIER_UEIE_Msk         (0x1UL << LPTIM_DIER_UEIE_Pos)             /*!< 0x00000080 */
+#define LPTIM_DIER_UEIE             LPTIM_DIER_UEIE_Msk                        /*!< Update event Interrupt Enable */
+#define LPTIM_DIER_REPOKIE_Pos      (8U)
+#define LPTIM_DIER_REPOKIE_Msk      (0x1UL << LPTIM_DIER_REPOKIE_Pos)          /*!< 0x00000100 */
+#define LPTIM_DIER_REPOKIE          LPTIM_DIER_REPOKIE_Msk                     /*!< Repetition register update OK Interrupt Enable */
+#define LPTIM_DIER_CC2IE_Pos        (9U)
+#define LPTIM_DIER_CC2IE_Msk        (0x1UL << LPTIM_DIER_CC2IE_Pos)            /*!< 0x00000200 */
+#define LPTIM_DIER_CC2IE            LPTIM_DIER_CC2IE_Msk                       /*!< Capture/Compare 2 interrupt interrupt enable */
+#define LPTIM_DIER_CC1OIE_Pos       (12U)
+#define LPTIM_DIER_CC1OIE_Msk       (0x1UL << LPTIM_DIER_CC1OIE_Pos)           /*!< 0x00001000 */
+#define LPTIM_DIER_CC1OIE           LPTIM_DIER_CC1OIE_Msk                      /*!< Capture/Compare 1 over-capture interrupt enable */
+#define LPTIM_DIER_CC2OIE_Pos       (13U)
+#define LPTIM_DIER_CC2OIE_Msk       (0x1UL << LPTIM_DIER_CC2OIE_Pos)           /*!< 0x00002000 */
+#define LPTIM_DIER_CC2OIE           LPTIM_DIER_CC2OIE_Msk                      /*!< Capture/Compare 2 over-capture interrupt enable */
+#define LPTIM_DIER_CC1DE_Pos        (16U)
+#define LPTIM_DIER_CC1DE_Msk        (0x1UL << LPTIM_DIER_CC1DE_Pos)            /*!< 0x00010000 */
+#define LPTIM_DIER_CC1DE            LPTIM_DIER_CC1DE_Msk                       /*!< Capture/Compare 1 DMA request enable */
+#define LPTIM_DIER_CMP2OKIE_Pos     (19U)
+#define LPTIM_DIER_CMP2OKIE_Msk     (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)         /*!< 0x00080000 */
+#define LPTIM_DIER_CMP2OKIE         LPTIM_DIER_CMP2OKIE_Msk                    /*!< Compare register 2 update OK interrupt enable */
+#define LPTIM_DIER_UEDE_Pos         (23U)
+#define LPTIM_DIER_UEDE_Msk         (0x1UL << LPTIM_DIER_UEDE_Pos)             /*!< 0x00800000 */
+#define LPTIM_DIER_UEDE             LPTIM_DIER_UEDE_Msk                        /*!< Update event DMA request enable */
+#define LPTIM_DIER_CC2DE_Pos        (25U)
+#define LPTIM_DIER_CC2DE_Msk        (0x1UL << LPTIM_DIER_CC2DE_Pos)            /*!< 0x02000000 */
+#define LPTIM_DIER_CC2DE            LPTIM_DIER_CC2DE_Msk                       /*!< Capture/Compare 2 DMA request enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CCR1_CCR1_Pos           (0U)
+#define LPTIM_CCR1_CCR1_Msk           (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)        /*!< 0x0000FFFF */
+#define LPTIM_CCR1_CCR1               LPTIM_CCR1_CCR1_Msk                      /*!< Compare register 1 */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000020 */
+#define LPTIM_CFGR2_IC1SEL_Pos      (16U)
+#define LPTIM_CFGR2_IC1SEL_Msk      (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IC1SEL          LPTIM_CFGR2_IC1SEL_Msk                     /*!< IC1SEL[17:16] bits */
+#define LPTIM_CFGR2_IC1SEL_0        (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CFGR2_IC1SEL_1        (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00020000 */
+#define LPTIM_CFGR2_IC2SEL_Pos      (20U)
+#define LPTIM_CFGR2_IC2SEL_Msk      (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IC2SEL          LPTIM_CFGR2_IC2SEL_Msk                     /*!< IC2SEL[21:20] bits */
+#define LPTIM_CFGR2_IC2SEL_0        (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00100000 */
+#define LPTIM_CFGR2_IC2SEL_1        (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00200000 */
+
+/******************  Bit definition for LPTIM_RCR register  *******************/
+#define LPTIM_RCR_REP_Pos           (0U)
+#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
+#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!< Repetition Counter Value */
+
+/*****************  Bit definition for LPTIM_CCMR1 register  ******************/
+#define LPTIM_CCMR1_CC1SEL_Pos      (0U)
+#define LPTIM_CCMR1_CC1SEL_Msk      (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CCMR1_CC1SEL          LPTIM_CCMR1_CC1SEL_Msk                     /*!< Capture/Compare 1 selection */
+#define LPTIM_CCMR1_CC1E_Pos        (1U)
+#define LPTIM_CCMR1_CC1E_Msk        (0x1UL << LPTIM_CCMR1_CC1E_Pos)            /*!< 0x00000002 */
+#define LPTIM_CCMR1_CC1E            LPTIM_CCMR1_CC1E_Msk                       /*!< Capture/Compare 1 output enable */
+#define LPTIM_CCMR1_CC1P_Pos        (2U)
+#define LPTIM_CCMR1_CC1P_Msk        (0x3UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x0000000C */
+#define LPTIM_CCMR1_CC1P            LPTIM_CCMR1_CC1P_Msk                       /*!< Capture/Compare 1 output polarity */
+#define LPTIM_CCMR1_CC1P_0          (0x1UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000004 */
+#define LPTIM_CCMR1_CC1P_1          (0x2UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000008 */
+#define LPTIM_CCMR1_IC1PSC_Pos      (8U)
+#define LPTIM_CCMR1_IC1PSC_Msk      (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000300 */
+#define LPTIM_CCMR1_IC1PSC          LPTIM_CCMR1_IC1PSC_Msk                     /*!< Input capture 1 prescaler */
+#define LPTIM_CCMR1_IC1PSC_0        (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000100 */
+#define LPTIM_CCMR1_IC1PSC_1        (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000200 */
+#define LPTIM_CCMR1_IC1F_Pos        (12U)
+#define LPTIM_CCMR1_IC1F_Msk        (0x3UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00003000 */
+#define LPTIM_CCMR1_IC1F            LPTIM_CCMR1_IC1F_Msk                       /*!< Input capture 1 filter */
+#define LPTIM_CCMR1_IC1F_0          (0x1UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00001000 */
+#define LPTIM_CCMR1_IC1F_1          (0x2UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00002000 */
+#define LPTIM_CCMR1_CC2SEL_Pos      (16U)
+#define LPTIM_CCMR1_CC2SEL_Msk      (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CCMR1_CC2SEL          LPTIM_CCMR1_CC2SEL_Msk                     /*!< Capture/Compare 2 selection */
+#define LPTIM_CCMR1_CC2E_Pos        (17U)
+#define LPTIM_CCMR1_CC2E_Msk        (0x1UL << LPTIM_CCMR1_CC2E_Pos)            /*!< 0x00020000 */
+#define LPTIM_CCMR1_CC2E            LPTIM_CCMR1_CC2E_Msk                       /*!< Capture/Compare 2 output enable */
+#define LPTIM_CCMR1_CC2P_Pos        (18U)
+#define LPTIM_CCMR1_CC2P_Msk        (0x3UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x000C0000 */
+#define LPTIM_CCMR1_CC2P            LPTIM_CCMR1_CC2P_Msk                       /*!< Capture/Compare 2 output polarity */
+#define LPTIM_CCMR1_CC2P_0          (0x1UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00040000 */
+#define LPTIM_CCMR1_CC2P_1          (0x2UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00080000 */
+#define LPTIM_CCMR1_IC2PSC_Pos      (24U)
+#define LPTIM_CCMR1_IC2PSC_Msk      (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x03000000 */
+#define LPTIM_CCMR1_IC2PSC          LPTIM_CCMR1_IC2PSC_Msk                     /*!< Input capture 2 prescaler */
+#define LPTIM_CCMR1_IC2PSC_0        (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x01000000 */
+#define LPTIM_CCMR1_IC2PSC_1        (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x02000000 */
+#define LPTIM_CCMR1_IC2F_Pos        (28U)
+#define LPTIM_CCMR1_IC2F_Msk        (0x3UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x30000000 */
+#define LPTIM_CCMR1_IC2F            LPTIM_CCMR1_IC2F_Msk                       /*!< Input capture 2 filter */
+#define LPTIM_CCMR1_IC2F_0          (0x1UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x10000000 */
+#define LPTIM_CCMR1_IC2F_1          (0x2UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x20000000 */
+
+/******************  Bit definition for LPTIM_CCR2 register  ******************/
+#define LPTIM_CCR2_CCR2_Pos         (0U)
+#define LPTIM_CCR2_CCR2_Msk         (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)           /*!< 0x0000FFFF */
+#define LPTIM_CCR2_CCR2             LPTIM_CCR2_CCR2_Msk                         /*!< Compare register 2 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/* Bit fields for LTDC_SSCR register */
+#define LTDC_SSCR_VSH_Pos                (0U)
+#define LTDC_SSCR_VSH_Msk                (0xfffUL << LTDC_SSCR_VSH_Pos)
+#define LTDC_SSCR_VSH                    LTDC_SSCR_VSH_Msk  /*!< vertical synchronization height (in units of horizontal scan line)These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. */
+#define LTDC_SSCR_HSW_Pos                (16U)
+#define LTDC_SSCR_HSW_Msk                (0xfffUL << LTDC_SSCR_HSW_Pos)
+#define LTDC_SSCR_HSW                    LTDC_SSCR_HSW_Msk  /*!< horizontal synchronization width (in units of pixel clock period)These bits define the number of Horizontal Synchronization pixel minus 1. */
+
+/* Bit fields for LTDC_BPCR register */
+#define LTDC_BPCR_AVBP_Pos               (0U)
+#define LTDC_BPCR_AVBP_Msk               (0xfffUL << LTDC_BPCR_AVBP_Pos)
+#define LTDC_BPCR_AVBP                   LTDC_BPCR_AVBP_Msk  /*!< accumulated Vertical back porch (in units of horizontal scan line)These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1.The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. */
+#define LTDC_BPCR_AHBP_Pos               (16U)
+#define LTDC_BPCR_AHBP_Msk               (0xfffUL << LTDC_BPCR_AHBP_Pos)
+#define LTDC_BPCR_AHBP                   LTDC_BPCR_AHBP_Msk  /*!< accumulated horizontal back porch (in units of pixel clock period)These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1.The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. */
+
+/* Bit fields for LTDC_AWCR register */
+#define LTDC_AWCR_AAH_Pos                (0U)
+#define LTDC_AWCR_AAH_Msk                (0xfffUL << LTDC_AWCR_AAH_Pos)
+#define LTDC_AWCR_AAH                    LTDC_AWCR_AAH_Msk  /*!< accumulated active height (in units of horizontal scan line)These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel.Refer to device datasheet for maximum active height supported following maximum pixel clock. */
+#define LTDC_AWCR_AAW_Pos                (16U)
+#define LTDC_AWCR_AAW_Msk                (0xfffUL << LTDC_AWCR_AAW_Pos)
+#define LTDC_AWCR_AAW                    LTDC_AWCR_AAW_Msk  /*!< accumulated active width (in units of pixel clock period)These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1.The active width is the number of pixels in active display area of the panel scan line.Refer to device datasheet for maximum active width supported following maximum pixel clock. */
+
+/* Bit fields for LTDC_TWCR register */
+#define LTDC_TWCR_TOTALH_Pos             (0U)
+#define LTDC_TWCR_TOTALH_Msk             (0xfffUL << LTDC_TWCR_TOTALH_Pos)
+#define LTDC_TWCR_TOTALH                 LTDC_TWCR_TOTALH_Msk  /*!< total height (in units of horizontal scan line)These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. */
+#define LTDC_TWCR_TOTALW_Pos             (16U)
+#define LTDC_TWCR_TOTALW_Msk             (0xfffUL << LTDC_TWCR_TOTALW_Pos)
+#define LTDC_TWCR_TOTALW                 LTDC_TWCR_TOTALW_Msk  /*!< total width (in units of pixel clock period)These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. */
+
+/* Bit fields for LTDC_GCR register */
+#define LTDC_GCR_LTDCEN_Pos              (0U)
+#define LTDC_GCR_LTDCEN_Msk              (0x1UL << LTDC_GCR_LTDCEN_Pos)
+#define LTDC_GCR_LTDCEN                  LTDC_GCR_LTDCEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: LTDC disable- 1: LTDC enable */
+#define LTDC_GCR_GAMEN_Pos               (1U)
+#define LTDC_GCR_GAMEN_Msk               (0x1UL << LTDC_GCR_GAMEN_Pos)
+#define LTDC_GCR_GAMEN                   LTDC_GCR_GAMEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: GammaCorrection disable (pixels bypass the gamma operator)- 1: Gamma Correction enable */
+#define LTDC_GCR_ROTEN_Pos               (2U)
+#define LTDC_GCR_ROTEN_Msk               (0x1UL << LTDC_GCR_ROTEN_Pos)
+#define LTDC_GCR_ROTEN                   LTDC_GCR_ROTEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: Rotation disable- 1: Rotation enable (for a pure visual rotation, the mirroring has to be activated) */
+#define LTDC_GCR_DBW_Pos                 (4U)
+#define LTDC_GCR_DBW_Msk                 (0x7UL << LTDC_GCR_DBW_Pos)
+#define LTDC_GCR_DBW                     LTDC_GCR_DBW_Msk  /*!< dither blue widthThese bits return the dither blue bits. */
+#define LTDC_GCR_DGW_Pos                 (8U)
+#define LTDC_GCR_DGW_Msk                 (0x7UL << LTDC_GCR_DGW_Pos)
+#define LTDC_GCR_DGW                     LTDC_GCR_DGW_Msk  /*!< dither green widthThese bits return the dither green bits. */
+#define LTDC_GCR_DRW_Pos                 (12U)
+#define LTDC_GCR_DRW_Msk                 (0x7UL << LTDC_GCR_DRW_Pos)
+#define LTDC_GCR_DRW                     LTDC_GCR_DRW_Msk  /*!< dither red widthThese bits return the Dither Red Bits. */
+#define LTDC_GCR_DEN_Pos                 (16U)
+#define LTDC_GCR_DEN_Msk                 (0x1UL << LTDC_GCR_DEN_Pos)
+#define LTDC_GCR_DEN                     LTDC_GCR_DEN_Msk  /*!< dither enableThis bit is set and cleared by software.- 0: dither disable- 1: dither enable */
+#define LTDC_GCR_BCKEN_Pos               (17U)
+#define LTDC_GCR_BCKEN_Msk               (0x1UL << LTDC_GCR_BCKEN_Pos)
+#define LTDC_GCR_BCKEN                   LTDC_GCR_BCKEN_Msk  /*!< backgroundlayer enableThis bit is set and cleared by software.- 0: backgrounddisable- 1: background enable */
+#define LTDC_GCR_CRCEN_Pos               (19U)
+#define LTDC_GCR_CRCEN_Msk               (0x1UL << LTDC_GCR_CRCEN_Pos)
+#define LTDC_GCR_CRCEN                   LTDC_GCR_CRCEN_Msk  /*!< CRC enableThis bit is set and cleared by software.- 0: CRC disable- 1: CRC enable */
+#define LTDC_GCR_SFEN_Pos                (24U)
+#define LTDC_GCR_SFEN_Msk                (0x1UL << LTDC_GCR_SFEN_Pos)
+#define LTDC_GCR_SFEN                    LTDC_GCR_SFEN_Msk  /*!< single-frame mode: mode enableThis bit is set and cleared by software.- 0: single-frame disable:a trigger (on SFSW or External) will generate a continuous flow.- 1: single-frame enable: a trigger (on SFSW or External) will generate a single frame. */
+#define LTDC_GCR_SFSWTR_Pos              (25U)
+#define LTDC_GCR_SFSWTR_Msk              (0x1UL << LTDC_GCR_SFSWTR_Pos)
+#define LTDC_GCR_SFSWTR                  LTDC_GCR_SFSWTR_Msk  /*!< single-frame mode: software triggerThis bit is set by software and cleared by hardware.- 0: no action- 1: triggers one frame */
+#define LTDC_GCR_SFEXEN_Pos              (26U)
+#define LTDC_GCR_SFEXEN_Msk              (0x1UL << LTDC_GCR_SFEXEN_Pos)
+#define LTDC_GCR_SFEXEN                  LTDC_GCR_SFEXEN_Msk  /*!< single-frame mode: external trigger enableThis bit is set and cleared by software.- 0: external trigger disable- 1: external trigger enable: a trigger on the external trigger will generate one single frame. */
+#define LTDC_GCR_PCPOL_Pos               (28U)
+#define LTDC_GCR_PCPOL_Msk               (0x1UL << LTDC_GCR_PCPOL_Pos)
+#define LTDC_GCR_PCPOL                   LTDC_GCR_PCPOL_Msk  /*!< pixel clock polarityThis bit is set and cleared by software.- 0: pixel clock polarity is active low.- 1: pixel clock is active high. */
+#define LTDC_GCR_DEPOL_Pos               (29U)
+#define LTDC_GCR_DEPOL_Msk               (0x1UL << LTDC_GCR_DEPOL_Pos)
+#define LTDC_GCR_DEPOL                   LTDC_GCR_DEPOL_Msk  /*!< blanking (=no data/pixel) polarityThis bit is set and cleared by software.- 0: blanking (no data/pixel) polarity is active low.- 1: blanking (no data/pixel) polarity is active high. */
+#define LTDC_GCR_VSPOL_Pos               (30U)
+#define LTDC_GCR_VSPOL_Msk               (0x1UL << LTDC_GCR_VSPOL_Pos)
+#define LTDC_GCR_VSPOL                   LTDC_GCR_VSPOL_Msk  /*!< vertical synchronization polarityThis bit is set and cleared by software.- 0: vertical synchronization is active low.- 1: vertical synchronization is active high. */
+#define LTDC_GCR_HSPOL_Pos               (31U)
+#define LTDC_GCR_HSPOL_Msk               (0x1UL << LTDC_GCR_HSPOL_Pos)
+#define LTDC_GCR_HSPOL                   LTDC_GCR_HSPOL_Msk  /*!< horizontal synchronization polarityThis bit is set and cleared by software.- 0: horizontal synchronization polarity is active low.- 1: horizontal synchronization polarity is active high. */
+
+/* Bit fields for LTDC_SRCR register */
+#define LTDC_SRCR_IMR_Pos                (0U)
+#define LTDC_SRCR_IMR_Msk                (0x1UL << LTDC_SRCR_IMR_Pos)
+#define LTDC_SRCR_IMR                    LTDC_SRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_SRCR_VBR_Pos                (1U)
+#define LTDC_SRCR_VBR_Msk                (0x1UL << LTDC_SRCR_VBR_Pos)
+#define LTDC_SRCR_VBR                    LTDC_SRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+
+/* Bit fields for LTDC_GCCR register */
+#define LTDC_GCCR_ADDR_Pos               (0U)
+#define LTDC_GCCR_ADDR_Msk               (0xffUL << LTDC_GCCR_ADDR_Pos)
+#define LTDC_GCCR_ADDR                   LTDC_GCCR_ADDR_Msk  /*!< address of the R,G,B table where the COMP component is written.When LTDC_GC1R.GCT=2, the gamma is implemented with 8 interpolated segment. In that case, the valid ADDR addresses are: 0, 32, 64, 96, 128, 160, 192, 224, 255.Note that for ADDR=255, the gamma interpolation hardware considers that the address is 256. */
+#define LTDC_GCCR_COMP_Pos               (8U)
+#define LTDC_GCCR_COMP_Msk               (0xffUL << LTDC_GCCR_COMP_Pos)
+#define LTDC_GCCR_COMP                   LTDC_GCCR_COMP_Msk  /*!< color component to be written, in either (or all) the R,G,B tables.. */
+#define LTDC_GCCR_BEN_Pos                (16U)
+#define LTDC_GCCR_BEN_Msk                (0x1UL << LTDC_GCCR_BEN_Pos)
+#define LTDC_GCCR_BEN                    LTDC_GCCR_BEN_Msk  /*!< write trigger to the blue table- 0: no action done- 1: COMP is written at ADDR in the Blue table. */
+#define LTDC_GCCR_GEN_Pos                (17U)
+#define LTDC_GCCR_GEN_Msk                (0x1UL << LTDC_GCCR_GEN_Pos)
+#define LTDC_GCCR_GEN                    LTDC_GCCR_GEN_Msk  /*!< write trigger to the green table- 0: no action done- 1: COMP is written at ADDR in the Green table. */
+#define LTDC_GCCR_REN_Pos                (18U)
+#define LTDC_GCCR_REN_Msk                (0x1UL << LTDC_GCCR_REN_Pos)
+#define LTDC_GCCR_REN                    LTDC_GCCR_REN_Msk  /*!< write trigger to the red table- 0: no action done- 1: COMP is written at ADDR in the Red table. */
+
+/* Bit fields for LTDC_BCCR register */
+#define LTDC_BCCR_BCBLUE_Pos             (0U)
+#define LTDC_BCCR_BCBLUE_Msk             (0xffUL << LTDC_BCCR_BCBLUE_Pos)
+#define LTDC_BCCR_BCBLUE                 LTDC_BCCR_BCBLUE_Msk  /*!< background color blue valueThese bits configure the background blue value. */
+#define LTDC_BCCR_BCGREEN_Pos            (8U)
+#define LTDC_BCCR_BCGREEN_Msk            (0xffUL << LTDC_BCCR_BCGREEN_Pos)
+#define LTDC_BCCR_BCGREEN                LTDC_BCCR_BCGREEN_Msk  /*!< background color green valueThese bits configure the background green value. */
+#define LTDC_BCCR_BCRED_Pos              (16U)
+#define LTDC_BCCR_BCRED_Msk              (0xffUL << LTDC_BCCR_BCRED_Pos)
+#define LTDC_BCCR_BCRED                  LTDC_BCCR_BCRED_Msk  /*!< background color red valueThese bits configure the background red value. */
+
+/* Bit fields for LTDC_IER register */
+#define LTDC_IER_LIE_Pos                 (0U)
+#define LTDC_IER_LIE_Msk                 (0x1UL << LTDC_IER_LIE_Pos)
+#define LTDC_IER_LIE                     LTDC_IER_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER_FUWIE_Pos               (1U)
+#define LTDC_IER_FUWIE_Msk               (0x1UL << LTDC_IER_FUWIE_Pos)
+#define LTDC_IER_FUWIE                   LTDC_IER_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER_TERRIE_Pos              (2U)
+#define LTDC_IER_TERRIE_Msk              (0x1UL << LTDC_IER_TERRIE_Pos)
+#define LTDC_IER_TERRIE                  LTDC_IER_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER_RRIE_Pos                (3U)
+#define LTDC_IER_RRIE_Msk                (0x1UL << LTDC_IER_RRIE_Pos)
+#define LTDC_IER_RRIE                    LTDC_IER_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER_FUIE_Pos                (6U)
+#define LTDC_IER_FUIE_Msk                (0x1UL << LTDC_IER_FUIE_Pos)
+#define LTDC_IER_FUIE                    LTDC_IER_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER_CRCIE_Pos               (7U)
+#define LTDC_IER_CRCIE_Msk               (0x1UL << LTDC_IER_CRCIE_Pos)
+#define LTDC_IER_CRCIE                   LTDC_IER_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+#define LTDC_IER_FURIE_Pos               (8U)
+#define LTDC_IER_FURIE_Msk               (0x1UL << LTDC_IER_FURIE_Pos)
+#define LTDC_IER_FURIE                   LTDC_IER_FURIE_Msk  /*!< FIFOunderrun at rotation interrupt enableThis bit is set and cleared by software.- 0: FIFOunderrun at rotation interrupt disable- 1: FIFO underrunat rotation interrupt enable */
+
+/* Bit fields for LTDC_ISR register */
+#define LTDC_ISR_LIF_Pos                 (0U)
+#define LTDC_ISR_LIF_Msk                 (0x1UL << LTDC_ISR_LIF_Pos)
+#define LTDC_ISR_LIF                     LTDC_ISR_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR_FUWIF_Pos               (1U)
+#define LTDC_ISR_FUWIF_Msk               (0x1UL << LTDC_ISR_FUWIF_Pos)
+#define LTDC_ISR_FUWIF                   LTDC_ISR_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR_TERRIF_Pos              (2U)
+#define LTDC_ISR_TERRIF_Msk              (0x1UL << LTDC_ISR_TERRIF_Pos)
+#define LTDC_ISR_TERRIF                  LTDC_ISR_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR_RRIF_Pos                (3U)
+#define LTDC_ISR_RRIF_Msk                (0x1UL << LTDC_ISR_RRIF_Pos)
+#define LTDC_ISR_RRIF                    LTDC_ISR_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR_FUIF_Pos                (6U)
+#define LTDC_ISR_FUIF_Msk                (0x1UL << LTDC_ISR_FUIF_Pos)
+#define LTDC_ISR_FUIF                    LTDC_ISR_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data is read from the FIFO */
+#define LTDC_ISR_CRCIF_Pos               (7U)
+#define LTDC_ISR_CRCIF_Msk               (0x1UL << LTDC_ISR_CRCIF_Pos)
+#define LTDC_ISR_CRCIF                   LTDC_ISR_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when the computed CRC is different from the expected CRC. */
+#define LTDC_ISR_FURIF_Pos               (8U)
+#define LTDC_ISR_FURIF_Msk               (0x1UL << LTDC_ISR_FURIF_Pos)
+#define LTDC_ISR_FURIF                   LTDC_ISR_FURIF_Msk  /*!< FIFO underrun at rotation interrupt flag- 0: no FIFO underrun at rotation interrupt generated- 1: FIFO underrun at rotation interrupt generated */
+
+/* Bit fields for LTDC_ICR register */
+#define LTDC_ICR_CLIF_Pos                (0U)
+#define LTDC_ICR_CLIF_Msk                (0x1UL << LTDC_ICR_CLIF_Pos)
+#define LTDC_ICR_CLIF                    LTDC_ICR_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFUWIF_Pos              (1U)
+#define LTDC_ICR_CFUWIF_Msk              (0x1UL << LTDC_ICR_CFUWIF_Pos)
+#define LTDC_ICR_CFUWIF                  LTDC_ICR_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CTERRIF_Pos             (2U)
+#define LTDC_ICR_CTERRIF_Msk             (0x1UL << LTDC_ICR_CTERRIF_Pos)
+#define LTDC_ICR_CTERRIF                 LTDC_ICR_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CRRIF_Pos               (3U)
+#define LTDC_ICR_CRRIF_Msk               (0x1UL << LTDC_ICR_CRRIF_Pos)
+#define LTDC_ICR_CRRIF                   LTDC_ICR_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR_CFUIF_Pos               (6U)
+#define LTDC_ICR_CFUIF_Msk               (0x1UL << LTDC_ICR_CFUIF_Pos)
+#define LTDC_ICR_CFUIF                   LTDC_ICR_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CCRCIF_Pos              (7U)
+#define LTDC_ICR_CCRCIF_Msk              (0x1UL << LTDC_ICR_CCRCIF_Pos)
+#define LTDC_ICR_CCRCIF                  LTDC_ICR_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFURIF_Pos              (8U)
+#define LTDC_ICR_CFURIF_Msk              (0x1UL << LTDC_ICR_CFURIF_Pos)
+#define LTDC_ICR_CFURIF                  LTDC_ICR_CFURIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the FURIF flag in the LTDC_ISR register */
+
+/* Bit fields for LTDC_LIPCR register */
+#define LTDC_LIPCR_LIPOS_Pos             (0U)
+#define LTDC_LIPCR_LIPOS_Msk             (0xfffUL << LTDC_LIPCR_LIPOS_Pos)
+#define LTDC_LIPCR_LIPOS                 LTDC_LIPCR_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR register */
+#define LTDC_CPSR_CYPOS_Pos              (0U)
+#define LTDC_CPSR_CYPOS_Msk              (0xfffUL << LTDC_CPSR_CYPOS_Pos)
+#define LTDC_CPSR_CYPOS                  LTDC_CPSR_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR_CXPOS_Pos              (16U)
+#define LTDC_CPSR_CXPOS_Msk              (0xfffUL << LTDC_CPSR_CXPOS_Pos)
+#define LTDC_CPSR_CXPOS                  LTDC_CPSR_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_CDSR register */
+#define LTDC_CDSR_VDES_Pos               (0U)
+#define LTDC_CDSR_VDES_Msk               (0x1UL << LTDC_CDSR_VDES_Pos)
+#define LTDC_CDSR_VDES                   LTDC_CDSR_VDES_Msk  /*!< vertical data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HDES_Pos               (1U)
+#define LTDC_CDSR_HDES_Msk               (0x1UL << LTDC_CDSR_HDES_Pos)
+#define LTDC_CDSR_HDES                   LTDC_CDSR_HDES_Msk  /*!< horizontal data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_VSYNCS_Pos             (2U)
+#define LTDC_CDSR_VSYNCS_Msk             (0x1UL << LTDC_CDSR_VSYNCS_Pos)
+#define LTDC_CDSR_VSYNCS                 LTDC_CDSR_VSYNCS_Msk  /*!< vertical synchronization display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HSYNCS_Pos             (3U)
+#define LTDC_CDSR_HSYNCS_Msk             (0x1UL << LTDC_CDSR_HSYNCS_Pos)
+#define LTDC_CDSR_HSYNCS                 LTDC_CDSR_HSYNCS_Msk  /*!< horizontal synchronization display status- 0: active low- 1: active high */
+
+/* Bit fields for LTDC_EDCR register */
+#define LTDC_EDCR_OCYEN_Pos              (25U)
+#define LTDC_EDCR_OCYEN_Msk              (0x1UL << LTDC_EDCR_OCYEN_Pos)
+#define LTDC_EDCR_OCYEN                  LTDC_EDCR_OCYEN_Msk  /*!< output conversion to YCbCr 422: Enable- 0: conversion is disabled- 1: conversion is enabled */
+#define LTDC_EDCR_OCYSEL_Pos             (26U)
+#define LTDC_EDCR_OCYSEL_Msk             (0x1UL << LTDC_EDCR_OCYSEL_Pos)
+#define LTDC_EDCR_OCYSEL                 LTDC_EDCR_OCYSEL_Msk  /*!< output conversion to YCbCr 422: selection of the CCIR hard-wired coefficients:- 0: use CCIR-BT601 set (for typically SDTV analog-like displays)- 1: use CCIR-BT709 set (for typically HDTV digital-like displays) */
+#define LTDC_EDCR_OCYCO_Pos              (27U)
+#define LTDC_EDCR_OCYCO_Msk              (0x1UL << LTDC_EDCR_OCYCO_Pos)
+#define LTDC_EDCR_OCYCO                  LTDC_EDCR_OCYCO_Msk  /*!< output conversion to YCbCr 422: chrominance order.- 0: Cb is output first (so: Y0Cb, then Y1Cr, Y2Cb, etc .. ).- 1: Cr is output first (so: Y0Cr, then Y1Cb, Y2Cr, etc ..). */
+
+/* Bit fields for LTDC_IER2 register */
+#define LTDC_IER2_LIE_Pos                (0U)
+#define LTDC_IER2_LIE_Msk                (0x1UL << LTDC_IER2_LIE_Pos)
+#define LTDC_IER2_LIE                    LTDC_IER2_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER2_FUWIE_Pos              (1U)
+#define LTDC_IER2_FUWIE_Msk              (0x1UL << LTDC_IER2_FUWIE_Pos)
+#define LTDC_IER2_FUWIE                  LTDC_IER2_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER2_TERRIE_Pos             (2U)
+#define LTDC_IER2_TERRIE_Msk             (0x1UL << LTDC_IER2_TERRIE_Pos)
+#define LTDC_IER2_TERRIE                 LTDC_IER2_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER2_RRIE_Pos               (3U)
+#define LTDC_IER2_RRIE_Msk               (0x1UL << LTDC_IER2_RRIE_Pos)
+#define LTDC_IER2_RRIE                   LTDC_IER2_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER2_FUIE_Pos               (6U)
+#define LTDC_IER2_FUIE_Msk               (0x1UL << LTDC_IER2_FUIE_Pos)
+#define LTDC_IER2_FUIE                   LTDC_IER2_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER2_CRCIE_Pos              (7U)
+#define LTDC_IER2_CRCIE_Msk              (0x1UL << LTDC_IER2_CRCIE_Pos)
+#define LTDC_IER2_CRCIE                  LTDC_IER2_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+
+/* Bit fields for LTDC_ISR2 register */
+#define LTDC_ISR2_LIF_Pos                (0U)
+#define LTDC_ISR2_LIF_Msk                (0x1UL << LTDC_ISR2_LIF_Pos)
+#define LTDC_ISR2_LIF                    LTDC_ISR2_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR2_FUWIF_Pos              (1U)
+#define LTDC_ISR2_FUWIF_Msk              (0x1UL << LTDC_ISR2_FUWIF_Pos)
+#define LTDC_ISR2_FUWIF                  LTDC_ISR2_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR2_TERRIF_Pos             (2U)
+#define LTDC_ISR2_TERRIF_Msk             (0x1UL << LTDC_ISR2_TERRIF_Pos)
+#define LTDC_ISR2_TERRIF                 LTDC_ISR2_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR2_RRIF_Pos               (3U)
+#define LTDC_ISR2_RRIF_Msk               (0x1UL << LTDC_ISR2_RRIF_Pos)
+#define LTDC_ISR2_RRIF                   LTDC_ISR2_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR2_FUIF_Pos               (6U)
+#define LTDC_ISR2_FUIF_Msk               (0x1UL << LTDC_ISR2_FUIF_Pos)
+#define LTDC_ISR2_FUIF                   LTDC_ISR2_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO */
+#define LTDC_ISR2_CRCIF_Pos              (7U)
+#define LTDC_ISR2_CRCIF_Msk              (0x1UL << LTDC_ISR2_CRCIF_Pos)
+#define LTDC_ISR2_CRCIF                  LTDC_ISR2_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when a bus error occurs */
+
+/* Bit fields for LTDC_ICR2 register */
+#define LTDC_ICR2_CLIF_Pos               (0U)
+#define LTDC_ICR2_CLIF_Msk               (0x1UL << LTDC_ICR2_CLIF_Pos)
+#define LTDC_ICR2_CLIF                   LTDC_ICR2_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CFUWIF_Pos             (1U)
+#define LTDC_ICR2_CFUWIF_Msk             (0x1UL << LTDC_ICR2_CFUWIF_Pos)
+#define LTDC_ICR2_CFUWIF                 LTDC_ICR2_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CTERRIF_Pos            (2U)
+#define LTDC_ICR2_CTERRIF_Msk            (0x1UL << LTDC_ICR2_CTERRIF_Pos)
+#define LTDC_ICR2_CTERRIF                LTDC_ICR2_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CRRIF_Pos              (3U)
+#define LTDC_ICR2_CRRIF_Msk              (0x1UL << LTDC_ICR2_CRRIF_Pos)
+#define LTDC_ICR2_CRRIF                  LTDC_ICR2_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR2_CFUIF_Pos              (6U)
+#define LTDC_ICR2_CFUIF_Msk              (0x1UL << LTDC_ICR2_CFUIF_Pos)
+#define LTDC_ICR2_CFUIF                  LTDC_ICR2_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CCRCIF_Pos             (7U)
+#define LTDC_ICR2_CCRCIF_Msk             (0x1UL << LTDC_ICR2_CCRCIF_Pos)
+#define LTDC_ICR2_CCRCIF                 LTDC_ICR2_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+
+/* Bit fields for LTDC_LIPCR2 register */
+#define LTDC_LIPCR2_LIPOS_Pos             (0U)
+#define LTDC_LIPCR2_LIPOS_Msk             (0xffffUL << LTDC_LIPCR2_LIPOS_Pos)
+#define LTDC_LIPCR2_LIPOS                 LTDC_LIPCR2_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR2 register */
+#define LTDC_CPSR2_CYPOS_Pos             (0U)
+#define LTDC_CPSR2_CYPOS_Msk             (0xffffUL << LTDC_CPSR2_CYPOS_Pos)
+#define LTDC_CPSR2_CYPOS                 LTDC_CPSR2_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR2_CXPOS_Pos             (16U)
+#define LTDC_CPSR2_CXPOS_Msk             (0xffffUL << LTDC_CPSR2_CXPOS_Pos)
+#define LTDC_CPSR2_CXPOS                 LTDC_CPSR2_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_ECRCR register */
+#define LTDC_ECRCR_ECRC_Pos              (0U)
+#define LTDC_ECRCR_ECRC_Msk              (0xffffUL << LTDC_ECRCR_ECRC_Pos)
+#define LTDC_ECRCR_ECRC                  LTDC_ECRCR_ECRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_CCRCR register */
+#define LTDC_CCRCR_CCRC_Pos              (0U)
+#define LTDC_CCRCR_CCRC_Msk              (0xffffUL << LTDC_CCRCR_CCRC_Pos)
+#define LTDC_CCRCR_CCRC                  LTDC_CCRCR_CCRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_FUTR register */
+#define LTDC_FUTR_THRE_Pos               (0U)
+#define LTDC_FUTR_THRE_Msk               (0xffffUL << LTDC_FUTR_THRE_Pos)
+#define LTDC_FUTR_THRE                   LTDC_FUTR_THRE_Msk  /*!< threshold to trigger a FIFO underrun killing interrupt (unit is per fifo word, 64bit) */
+
+/* Bit fields for LTDC_LxC0R register */
+#define LTDC_LxC0R_CKTA_Pos              (0U)
+#define LTDC_LxC0R_CKTA_Msk              (0x1UL << LTDC_LxC0R_CKTA_Pos)
+#define LTDC_LxC0R_CKTA                  LTDC_LxC0R_CKTA_Msk  /*!< color key transparency Ability */
+#define LTDC_LxC0R_CFBDA_Pos             (1U)
+#define LTDC_LxC0R_CFBDA_Msk             (0x1UL << LTDC_LxC0R_CFBDA_Pos)
+#define LTDC_LxC0R_CFBDA                 LTDC_LxC0R_CFBDA_Msk  /*!< color frame buffer duplication ability */
+#define LTDC_LxC0R_CFBPA_Pos             (2U)
+#define LTDC_LxC0R_CFBPA_Msk             (0x1UL << LTDC_LxC0R_CFBPA_Pos)
+#define LTDC_LxC0R_CFBPA                 LTDC_LxC0R_CFBPA_Msk  /*!< color frame buffer pitch ability */
+#define LTDC_LxC0R_APA_Pos               (3U)
+#define LTDC_LxC0R_APA_Msk               (0x1UL << LTDC_LxC0R_APA_Pos)
+#define LTDC_LxC0R_APA                   LTDC_LxC0R_APA_Msk  /*!< alpha plane ability */
+#define LTDC_LxC0R_DCP_Pos               (4U)
+#define LTDC_LxC0R_DCP_Msk               (0x1UL << LTDC_LxC0R_DCP_Pos)
+#define LTDC_LxC0R_DCP                   LTDC_LxC0R_DCP_Msk  /*!< default color programmability */
+#define LTDC_LxC0R_WINA_Pos              (5U)
+#define LTDC_LxC0R_WINA_Msk              (0x1UL << LTDC_LxC0R_WINA_Pos)
+#define LTDC_LxC0R_WINA                  LTDC_LxC0R_WINA_Msk  /*!< windowing ability */
+#define LTDC_LxC0R_CLUTA_Pos             (6U)
+#define LTDC_LxC0R_CLUTA_Msk             (0x1UL << LTDC_LxC0R_CLUTA_Pos)
+#define LTDC_LxC0R_CLUTA                 LTDC_LxC0R_CLUTA_Msk  /*!< CLUT ability */
+#define LTDC_LxC0R_CKRA_Pos              (7U)
+#define LTDC_LxC0R_CKRA_Msk              (0x1UL << LTDC_LxC0R_CKRA_Pos)
+#define LTDC_LxC0R_CKRA                  LTDC_LxC0R_CKRA_Msk  /*!< color key replace ability */
+#define LTDC_LxC0R_F21_Pos               (8U)
+#define LTDC_LxC0R_F21_Msk               (0x1UL << LTDC_LxC0R_F21_Pos)
+#define LTDC_LxC0R_F21                   LTDC_LxC0R_F21_Msk  /*!< blending factor 2, ability for: 1.0 */
+#define LTDC_LxC0R_F20_Pos               (9U)
+#define LTDC_LxC0R_F20_Msk               (0x1UL << LTDC_LxC0R_F20_Pos)
+#define LTDC_LxC0R_F20                   LTDC_LxC0R_F20_Msk  /*!< blending factor 2, ability for: 0.0 */
+#define LTDC_LxC0R_F2P_Pos               (10U)
+#define LTDC_LxC0R_F2P_Msk               (0x1UL << LTDC_LxC0R_F2P_Pos)
+#define LTDC_LxC0R_F2P                   LTDC_LxC0R_F2P_Msk  /*!< blending factor 2, ability for: pixel_alpha */
+#define LTDC_LxC0R_F21P_Pos              (11U)
+#define LTDC_LxC0R_F21P_Msk              (0x1UL << LTDC_LxC0R_F21P_Pos)
+#define LTDC_LxC0R_F21P                  LTDC_LxC0R_F21P_Msk  /*!< blending factor 2, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F2C_Pos               (12U)
+#define LTDC_LxC0R_F2C_Msk               (0x1UL << LTDC_LxC0R_F2C_Pos)
+#define LTDC_LxC0R_F2C                   LTDC_LxC0R_F2C_Msk  /*!< blending factor 2, ability for: constant_alpha */
+#define LTDC_LxC0R_F21C_Pos              (13U)
+#define LTDC_LxC0R_F21C_Msk              (0x1UL << LTDC_LxC0R_F21C_Pos)
+#define LTDC_LxC0R_F21C                  LTDC_LxC0R_F21C_Msk  /*!< blending factor 2, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F2PC_Pos              (14U)
+#define LTDC_LxC0R_F2PC_Msk              (0x1UL << LTDC_LxC0R_F2PC_Pos)
+#define LTDC_LxC0R_F2PC                  LTDC_LxC0R_F2PC_Msk  /*!< blending factor 2, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F21PC_Pos             (15U)
+#define LTDC_LxC0R_F21PC_Msk             (0x1UL << LTDC_LxC0R_F21PC_Pos)
+#define LTDC_LxC0R_F21PC                 LTDC_LxC0R_F21PC_Msk  /*!< blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_F11_Pos               (16U)
+#define LTDC_LxC0R_F11_Msk               (0x1UL << LTDC_LxC0R_F11_Pos)
+#define LTDC_LxC0R_F11                   LTDC_LxC0R_F11_Msk  /*!< blending factor 1, ability for: 1.0 */
+#define LTDC_LxC0R_F10_Pos               (17U)
+#define LTDC_LxC0R_F10_Msk               (0x1UL << LTDC_LxC0R_F10_Pos)
+#define LTDC_LxC0R_F10                   LTDC_LxC0R_F10_Msk  /*!< blending factor 1,ability for: 0.0 */
+#define LTDC_LxC0R_F1P_Pos               (18U)
+#define LTDC_LxC0R_F1P_Msk               (0x1UL << LTDC_LxC0R_F1P_Pos)
+#define LTDC_LxC0R_F1P                   LTDC_LxC0R_F1P_Msk  /*!< blending factor 1, ability for: pixel_alpha */
+#define LTDC_LxC0R_F11P_Pos              (19U)
+#define LTDC_LxC0R_F11P_Msk              (0x1UL << LTDC_LxC0R_F11P_Pos)
+#define LTDC_LxC0R_F11P                  LTDC_LxC0R_F11P_Msk  /*!< blending factor 1, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F1C_Pos               (20U)
+#define LTDC_LxC0R_F1C_Msk               (0x1UL << LTDC_LxC0R_F1C_Pos)
+#define LTDC_LxC0R_F1C                   LTDC_LxC0R_F1C_Msk  /*!< blending factor 1, ability for: constant_alpha */
+#define LTDC_LxC0R_F11C_Pos              (21U)
+#define LTDC_LxC0R_F11C_Msk              (0x1UL << LTDC_LxC0R_F11C_Pos)
+#define LTDC_LxC0R_F11C                  LTDC_LxC0R_F11C_Msk  /*!< blending factor 1, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F1PC_Pos              (22U)
+#define LTDC_LxC0R_F1PC_Msk              (0x1UL << LTDC_LxC0R_F1PC_Pos)
+#define LTDC_LxC0R_F1PC                  LTDC_LxC0R_F1PC_Msk  /*!< blending factor 1, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F11PC_Pos             (23U)
+#define LTDC_LxC0R_F11PC_Msk             (0x1UL << LTDC_LxC0R_F11PC_Pos)
+#define LTDC_LxC0R_F11PC                 LTDC_LxC0R_F11PC_Msk  /*!< blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_P88_Pos               (24U)
+#define LTDC_LxC0R_P88_Msk               (0x1UL << LTDC_LxC0R_P88_Pos)
+#define LTDC_LxC0R_P88                   LTDC_LxC0R_P88_Msk  /*!< pixel format, ability for: AL88. */
+#define LTDC_LxC0R_P44_Pos               (25U)
+#define LTDC_LxC0R_P44_Msk               (0x1UL << LTDC_LxC0R_P44_Pos)
+#define LTDC_LxC0R_P44                   LTDC_LxC0R_P44_Msk  /*!< pixel format, ability for: AL44. */
+#define LTDC_LxC0R_P8_Pos                (26U)
+#define LTDC_LxC0R_P8_Msk                (0x1UL << LTDC_LxC0R_P8_Pos)
+#define LTDC_LxC0R_P8                    LTDC_LxC0R_P8_Msk  /*!< pixel format, ability for: L8. */
+#define LTDC_LxC0R_P4444_Pos             (27U)
+#define LTDC_LxC0R_P4444_Msk             (0x1UL << LTDC_LxC0R_P4444_Pos)
+#define LTDC_LxC0R_P4444                 LTDC_LxC0R_P4444_Msk  /*!< pixel format, ability for: ARGB4444. */
+#define LTDC_LxC0R_P1555_Pos             (28U)
+#define LTDC_LxC0R_P1555_Msk             (0x1UL << LTDC_LxC0R_P1555_Pos)
+#define LTDC_LxC0R_P1555                 LTDC_LxC0R_P1555_Msk  /*!< pixel format, ability for: ARGB1555. */
+#define LTDC_LxC0R_P565_Pos              (29U)
+#define LTDC_LxC0R_P565_Msk              (0x1UL << LTDC_LxC0R_P565_Pos)
+#define LTDC_LxC0R_P565                  LTDC_LxC0R_P565_Msk  /*!< pixel format, ability for: RGB565. */
+#define LTDC_LxC0R_P888_Pos              (30U)
+#define LTDC_LxC0R_P888_Msk              (0x1UL << LTDC_LxC0R_P888_Pos)
+#define LTDC_LxC0R_P888                  LTDC_LxC0R_P888_Msk  /*!< pixel format, ability for: RGB888. */
+#define LTDC_LxC0R_P8888_Pos             (31U)
+#define LTDC_LxC0R_P8888_Msk             (0x1UL << LTDC_LxC0R_P8888_Pos)
+#define LTDC_LxC0R_P8888                 LTDC_LxC0R_P8888_Msk  /*!< pixel format, ability for: ARGB8888. */
+
+/* Bit fields for LTDC_LxC1R register */
+#define LTDC_LxC1R_YIA_Pos               (0U)
+#define LTDC_LxC1R_YIA_Msk               (0x1UL << LTDC_LxC1R_YIA_Pos)
+#define LTDC_LxC1R_YIA                   LTDC_LxC1R_YIA_Msk  /*!< YCbCr 422 interleaved ability for that layer.- 0: interleaved not available- 1: interleaved available */
+#define LTDC_LxC1R_YSPA_Pos              (1U)
+#define LTDC_LxC1R_YSPA_Msk              (0x1UL << LTDC_LxC1R_YSPA_Pos)
+#define LTDC_LxC1R_YSPA                  LTDC_LxC1R_YSPA_Msk  /*!< YCbCr 420 semi-planar ability for that layer.- 0: semiplanar not available- 1: semi-planar available */
+#define LTDC_LxC1R_YFPA_Pos              (2U)
+#define LTDC_LxC1R_YFPA_Msk              (0x1UL << LTDC_LxC1R_YFPA_Pos)
+#define LTDC_LxC1R_YFPA                  LTDC_LxC1R_YFPA_Msk  /*!< YCbCr 420 full-planar ability for that layer.- 0: full planar not available- 1: full planar available */
+#define LTDC_LxC1R_SCA_Pos               (31U)
+#define LTDC_LxC1R_SCA_Msk               (0x1UL << LTDC_LxC1R_SCA_Pos)
+#define LTDC_LxC1R_SCA                   LTDC_LxC1R_SCA_Msk  /*!< scaling ability for that layer.- 0: scaling not available- 1: scaling available */
+
+/* Bit fields for LTDC_LxRCR register */
+#define LTDC_LxRCR_IMR_Pos               (0U)
+#define LTDC_LxRCR_IMR_Msk               (0x1UL << LTDC_LxRCR_IMR_Pos)
+#define LTDC_LxRCR_IMR                   LTDC_LxRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_LxRCR_VBR_Pos               (1U)
+#define LTDC_LxRCR_VBR_Msk               (0x1UL << LTDC_LxRCR_VBR_Pos)
+#define LTDC_LxRCR_VBR                   LTDC_LxRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+#define LTDC_LxRCR_GRMSK_Pos             (2U)
+#define LTDC_LxRCR_GRMSK_Msk             (0x1UL << LTDC_LxRCR_GRMSK_Pos)
+#define LTDC_LxRCR_GRMSK                 LTDC_LxRCR_GRMSK_Msk  /*!< shadow reload control: global (centralized) reload maskedThis bit is set and cleared by software.- 0: global reload active (the control from the LTDC_SRCR are enabled)- 1: global reload is masked (the control from the LTDC_SRCR are disabled) */
+
+/* Bit fields for LTDC_LxCR register */
+#define LTDC_LxCR_LEN_Pos                (0U)
+#define LTDC_LxCR_LEN_Msk                (0x1UL << LTDC_LxCR_LEN_Pos)
+#define LTDC_LxCR_LEN                    LTDC_LxCR_LEN_Msk  /*!< layer enable: the bit is used to enable/disable the presence of this whole layer.This bit is set and cleared by software.- 0: layer disabled- 1: layer enabled */
+#define LTDC_LxCR_CKEN_Pos               (1U)
+#define LTDC_LxCR_CKEN_Msk               (0x1UL << LTDC_LxCR_CKEN_Pos)
+#define LTDC_LxCR_CKEN                   LTDC_LxCR_CKEN_Msk  /*!< color keying enableThis bit is set and cleared by software.- 0: color keying disabled- 1: color keying enabled: if RGB matches, then the ARGB are set to 0. */
+#define LTDC_LxCR_VPDEN_Pos              (2U)
+#define LTDC_LxCR_VPDEN_Msk              (0x1UL << LTDC_LxCR_VPDEN_Pos)
+#define LTDC_LxCR_VPDEN                  LTDC_LxCR_VPDEN_Msk  /*!< vertical pixel duplication enableThis bit is set and cleared by software.- 0: duplication disabled- 1: duplication enabled */
+#define LTDC_LxCR_CLUTEN_Pos             (4U)
+#define LTDC_LxCR_CLUTEN_Msk             (0x1UL << LTDC_LxCR_CLUTEN_Pos)
+#define LTDC_LxCR_CLUTEN                 LTDC_LxCR_CLUTEN_Msk  /*!< color look-up table enableThis bit is set and cleared by software.- 0: color look-up table disabled- 1: color look-up table enabledThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up table (CLUT) */
+#define LTDC_LxCR_HMEN_Pos               (8U)
+#define LTDC_LxCR_HMEN_Msk               (0x1UL << LTDC_LxCR_HMEN_Pos)
+#define LTDC_LxCR_HMEN                   LTDC_LxCR_HMEN_Msk  /*!< horizontal mirroring enableThis bit is set and cleared by software.- 0: mirror disabled- 1: mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instannce: if line is 100 pixels, 24bpp, then address is set to 299) */
+#define LTDC_LxCR_DCBEN_Pos              (9U)
+#define LTDC_LxCR_DCBEN_Msk              (0x1UL << LTDC_LxCR_DCBEN_Pos)
+#define LTDC_LxCR_DCBEN                  LTDC_LxCR_DCBEN_Msk  /*!< default color blending enableThis bit is set and cleared by software.- 0: blending disabled- 1: blending enabled */
+
+/* Bit fields for LTDC_LxWHPCR register */
+#define LTDC_LxWHPCR_WHSTPOS_Pos         (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSTPOS_Pos)
+#define LTDC_LxWHPCR_WHSTPOS             LTDC_LxWHPCR_WHSTPOS_Msk  /*!< window horizontal start positionThese bits configure the first visible pixel of a line of the layer window.WHSTPOS[15:0] must be >= AAW[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWHPCR_WHSPPOS_Pos         (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos)
+#define LTDC_LxWHPCR_WHSPPOS             LTDC_LxWHPCR_WHSPPOS_Msk  /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxWVPCR register */
+#define LTDC_LxWVPCR_WVSTPOS_Pos         (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos)
+#define LTDC_LxWVPCR_WVSTPOS             LTDC_LxWVPCR_WVSTPOS_Msk  /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWVPCR_WVSPPOS_Pos         (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos)
+#define LTDC_LxWVPCR_WVSPPOS             LTDC_LxWVPCR_WVSPPOS_Msk  /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxCKCR register */
+#define LTDC_LxCKCR_CKBLUE_Pos           (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk           (0xffUL << LTDC_LxCKCR_CKBLUE_Pos)
+#define LTDC_LxCKCR_CKBLUE               LTDC_LxCKCR_CKBLUE_Msk  /*!< color key blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos          (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk          (0xffUL << LTDC_LxCKCR_CKGREEN_Pos)
+#define LTDC_LxCKCR_CKGREEN              LTDC_LxCKCR_CKGREEN_Msk  /*!< color key green value */
+#define LTDC_LxCKCR_CKRED_Pos            (16U)
+#define LTDC_LxCKCR_CKRED_Msk            (0xffUL << LTDC_LxCKCR_CKRED_Pos)
+#define LTDC_LxCKCR_CKRED                LTDC_LxCKCR_CKRED_Msk  /*!< color key red value */
+
+/* Bit fields for LTDC_LxPFCR register */
+#define LTDC_LxPFCR_PF_Pos               (0U)
+#define LTDC_LxPFCR_PF_Msk               (0x7UL << LTDC_LxPFCR_PF_Pos)
+#define LTDC_LxPFCR_PF                   LTDC_LxPFCR_PF_Msk  /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */
+
+/* Bit fields for LTDC_LxCACR register */
+#define LTDC_LxCACR_CONSTA_Pos           (0U)
+#define LTDC_LxCACR_CONSTA_Msk           (0xffUL << LTDC_LxCACR_CONSTA_Pos)
+#define LTDC_LxCACR_CONSTA               LTDC_LxCACR_CONSTA_Msk  /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */
+
+/* Bit fields for LTDC_LxDCCR register */
+#define LTDC_LxDCCR_DCBLUE_Pos           (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk           (0xffUL << LTDC_LxDCCR_DCBLUE_Pos)
+#define LTDC_LxDCCR_DCBLUE               LTDC_LxDCCR_DCBLUE_Msk  /*!< default color blueThese bits configure the default blue value. */
+#define LTDC_LxDCCR_DCGREEN_Pos          (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk          (0xffUL << LTDC_LxDCCR_DCGREEN_Pos)
+#define LTDC_LxDCCR_DCGREEN              LTDC_LxDCCR_DCGREEN_Msk  /*!< default color greenThese bits configure the default green value. */
+#define LTDC_LxDCCR_DCRED_Pos            (16U)
+#define LTDC_LxDCCR_DCRED_Msk            (0xffUL << LTDC_LxDCCR_DCRED_Pos)
+#define LTDC_LxDCCR_DCRED                LTDC_LxDCCR_DCRED_Msk  /*!< default color redThese bits configure the default red value. */
+#define LTDC_LxDCCR_DCALPHA_Pos          (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk          (0xffUL << LTDC_LxDCCR_DCALPHA_Pos)
+#define LTDC_LxDCCR_DCALPHA              LTDC_LxDCCR_DCALPHA_Msk  /*!< default color alphaThese bits configure the default alpha value. */
+
+/* Bit fields for LTDC_LxBFCR register */
+#define LTDC_LxBFCR_BF2_Pos              (0U)
+#define LTDC_LxBFCR_BF2_Msk              (0x7UL << LTDC_LxBFCR_BF2_Pos)
+#define LTDC_LxBFCR_BF2                  LTDC_LxBFCR_BF2_Msk  /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */
+#define LTDC_LxBFCR_BF1_Pos              (8U)
+#define LTDC_LxBFCR_BF1_Msk              (0x7UL << LTDC_LxBFCR_BF1_Pos)
+#define LTDC_LxBFCR_BF1                  LTDC_LxBFCR_BF1_Msk  /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */
+#define LTDC_LxBFCR_BOR_Pos              (16U)
+#define LTDC_LxBFCR_BOR_Msk              (0x1UL << LTDC_LxBFCR_BOR_Pos)
+#define LTDC_LxBFCR_BOR                  LTDC_LxBFCR_BOR_Msk  /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */
+
+/* Bit fields for LTDC_LxBLCR register */
+#define LTDC_LxBLCR_BL_Pos               (0U)
+#define LTDC_LxBLCR_BL_Msk               (0x1fUL << LTDC_LxBLCR_BL_Pos)
+#define LTDC_LxBLCR_BL                   LTDC_LxBLCR_BL_Msk  /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */
+
+/* Bit fields for LTDC_LxPCR register */
+#define LTDC_LxPCR_YCEN_Pos              (3U)
+#define LTDC_LxPCR_YCEN_Msk              (0x1UL << LTDC_LxPCR_YCEN_Pos)
+#define LTDC_LxPCR_YCEN                  LTDC_LxPCR_YCEN_Msk  /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */
+#define LTDC_LxPCR_YCM_Pos               (4U)
+#define LTDC_LxPCR_YCM_Msk               (0x3UL << LTDC_LxPCR_YCM_Pos)
+#define LTDC_LxPCR_YCM                   LTDC_LxPCR_YCM_Msk  /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */
+#define LTDC_LxPCR_YF_Pos                (6U)
+#define LTDC_LxPCR_YF_Msk                (0x1UL << LTDC_LxPCR_YF_Pos)
+#define LTDC_LxPCR_YF                    LTDC_LxPCR_YF_Msk  /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */
+#define LTDC_LxPCR_CBF_Pos               (7U)
+#define LTDC_LxPCR_CBF_Msk               (0x1UL << LTDC_LxPCR_CBF_Pos)
+#define LTDC_LxPCR_CBF                   LTDC_LxPCR_CBF_Msk  /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */
+#define LTDC_LxPCR_OF_Pos                (8U)
+#define LTDC_LxPCR_OF_Msk                (0x1UL << LTDC_LxPCR_OF_Pos)
+#define LTDC_LxPCR_OF                    LTDC_LxPCR_OF_Msk  /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */
+#define LTDC_LxPCR_YREN_Pos              (9U)
+#define LTDC_LxPCR_YREN_Msk              (0x1UL << LTDC_LxPCR_YREN_Pos)
+#define LTDC_LxPCR_YREN                  LTDC_LxPCR_YREN_Msk  /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */
+
+/* Bit fields for LTDC_LxCFBAR register */
+#define LTDC_LxCFBAR_CFBADD_Pos          (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk          (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos)
+#define LTDC_LxCFBAR_CFBADD              LTDC_LxCFBAR_CFBADD_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxCFBLR register */
+#define LTDC_LxCFBLR_CFBLL_Pos           (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk           (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos)
+#define LTDC_LxCFBLR_CFBLL               LTDC_LxCFBLR_CFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_LxCFBLR_CFBP_Pos            (16U)
+#define LTDC_LxCFBLR_CFBP_Msk            (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos)
+#define LTDC_LxCFBLR_CFBP                LTDC_LxCFBLR_CFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxCFBLNR register */
+#define LTDC_LxCFBLNR_CFBLNBR_Pos        (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk        (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
+#define LTDC_LxCFBLNR_CFBLNBR            LTDC_LxCFBLNR_CFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_L1AFBA0R register */
+#define LTDC_L1AFBA0R_AFBADD0_Pos        (0U)
+#define LTDC_L1AFBA0R_AFBADD0_Msk        (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos)
+#define LTDC_L1AFBA0R_AFBADD0            LTDC_L1AFBA0R_AFBADD0_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBA1R register */
+#define LTDC_L1AFBA1R_AFBADD1_Pos        (0U)
+#define LTDC_L1AFBA1R_AFBADD1_Msk        (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos)
+#define LTDC_L1AFBA1R_AFBADD1            LTDC_L1AFBA1R_AFBADD1_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBLR register */
+#define LTDC_L1AFBLR_AFBLL_Pos           (0U)
+#define LTDC_L1AFBLR_AFBLL_Msk           (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos)
+#define LTDC_L1AFBLR_AFBLL               LTDC_L1AFBLR_AFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_L1AFBLR_AFBP_Pos            (16U)
+#define LTDC_L1AFBLR_AFBP_Msk            (0xffffUL << LTDC_L1AFBLR_AFBP_Pos)
+#define LTDC_L1AFBLR_AFBP                LTDC_L1AFBLR_AFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxAFBLNR register */
+#define LTDC_L1AFBLNR_AFBLNBR_Pos        (0U)
+#define LTDC_L1AFBLNR_AFBLNBR_Msk        (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos)
+#define LTDC_L1AFBLNR_AFBLNBR            LTDC_L1AFBLNR_AFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_LxCLUTWR register */
+#define LTDC_LxCLUTWR_BLUE_Pos           (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk           (0xffUL << LTDC_LxCLUTWR_BLUE_Pos)
+#define LTDC_LxCLUTWR_BLUE               LTDC_LxCLUTWR_BLUE_Msk  /*!< blue valueThese bits configure the blue value. */
+#define LTDC_LxCLUTWR_GREEN_Pos          (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk          (0xffUL << LTDC_LxCLUTWR_GREEN_Pos)
+#define LTDC_LxCLUTWR_GREEN              LTDC_LxCLUTWR_GREEN_Msk  /*!< green valueThese bits configure the green value. */
+#define LTDC_LxCLUTWR_RED_Pos            (16U)
+#define LTDC_LxCLUTWR_RED_Msk            (0xffUL << LTDC_LxCLUTWR_RED_Pos)
+#define LTDC_LxCLUTWR_RED                LTDC_LxCLUTWR_RED_Msk  /*!< red valueThese bits configure the red value. */
+#define LTDC_LxCLUTWR_CLUTADD_Pos        (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk        (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos)
+#define LTDC_LxCLUTWR_CLUTADD            LTDC_LxCLUTWR_CLUTADD_Msk  /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */
+
+/* Bit fields for LTDC_LxCYR0R register */
+#define LTDC_LxCYR0R_CR2R_Pos            (0U)
+#define LTDC_LxCYR0R_CR2R_Msk            (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos)
+#define LTDC_LxCYR0R_CR2R                LTDC_LxCYR0R_CR2R_Msk  /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR0R_CB2B_Pos            (16U)
+#define LTDC_LxCYR0R_CB2B_Msk            (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos)
+#define LTDC_LxCYR0R_CB2B                LTDC_LxCYR0R_CB2B_Msk  /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxCYR1R register */
+#define LTDC_LxCYR1R_CR2G_Pos            (0U)
+#define LTDC_LxCYR1R_CR2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos)
+#define LTDC_LxCYR1R_CR2G                LTDC_LxCYR1R_CR2G_Msk  /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR1R_CB2G_Pos            (16U)
+#define LTDC_LxCYR1R_CB2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos)
+#define LTDC_LxCYR1R_CB2G                LTDC_LxCYR1R_CB2G_Msk  /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxFPF0R register */
+#define LTDC_LxFPF0R_APOS_Pos            (0U)
+#define LTDC_LxFPF0R_APOS_Msk            (0x1fUL << LTDC_LxFPF0R_APOS_Pos)
+#define LTDC_LxFPF0R_APOS                LTDC_LxFPF0R_APOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_ALEN_Pos            (5U)
+#define LTDC_LxFPF0R_ALEN_Msk            (0xfUL << LTDC_LxFPF0R_ALEN_Pos)
+#define LTDC_LxFPF0R_ALEN                LTDC_LxFPF0R_ALEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF0R_RPOS_Pos            (9U)
+#define LTDC_LxFPF0R_RPOS_Msk            (0x1fUL << LTDC_LxFPF0R_RPOS_Pos)
+#define LTDC_LxFPF0R_RPOS                LTDC_LxFPF0R_RPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_RLEN_Pos            (14U)
+#define LTDC_LxFPF0R_RLEN_Msk            (0xfUL << LTDC_LxFPF0R_RLEN_Pos)
+#define LTDC_LxFPF0R_RLEN                LTDC_LxFPF0R_RLEN_Msk  /*!< Width of the red component (in bits). */
+
+/* Bit fields for LTDC_LxFPF1R register */
+#define LTDC_LxFPF1R_GPOS_Pos            (0U)
+#define LTDC_LxFPF1R_GPOS_Msk            (0x1fUL << LTDC_LxFPF1R_GPOS_Pos)
+#define LTDC_LxFPF1R_GPOS                LTDC_LxFPF1R_GPOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_GLEN_Pos            (5U)
+#define LTDC_LxFPF1R_GLEN_Msk            (0xfUL << LTDC_LxFPF1R_GLEN_Pos)
+#define LTDC_LxFPF1R_GLEN                LTDC_LxFPF1R_GLEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF1R_BPOS_Pos            (9U)
+#define LTDC_LxFPF1R_BPOS_Msk            (0x1fUL << LTDC_LxFPF1R_BPOS_Pos)
+#define LTDC_LxFPF1R_BPOS                LTDC_LxFPF1R_BPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_BLEN_Pos            (14U)
+#define LTDC_LxFPF1R_BLEN_Msk            (0xfUL << LTDC_LxFPF1R_BLEN_Pos)
+#define LTDC_LxFPF1R_BLEN                LTDC_LxFPF1R_BLEN_Msk  /*!< Width of the red component (in bits). */
+
+#define LTDC_LxFPF1R_PSIZE_Pos            (18U)
+#define LTDC_LxFPF1R_PSIZE_Msk            (0x7UL << LTDC_LxFPF1R_PSIZE_Pos)
+#define LTDC_LxFPF1R_PSIZE                LTDC_LxFPF1R_PSIZE_Msk  /*!< Width of the red component (in bits). */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDF/ADF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for MDF/ADF_GCR register  ****************/
+#define MDF_GCR_TRGO_Pos                    (0U)
+#define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
+#define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!< Trigger output control */
+#define MDF_GCR_ILVNB_Pos                   (4U)
+#define MDF_GCR_ILVNB_Msk                   (0xFUL << MDF_GCR_ILVNB_Pos)            /*!< 0x000000F0 */
+#define MDF_GCR_ILVNB                       MDF_GCR_ILVNB_Msk                       /*!< Interleaved Number */
+
+/*******************  Bit definition for MDF/ADF_CKGCR register  ********************/
+#define MDF_CKGCR_CKDEN_Pos                 (0U)
+#define MDF_CKGCR_CKDEN_Msk                 (0x1UL << MDF_CKGCR_CKDEN_Pos)          /*!< 0x00000001 */
+#define MDF_CKGCR_CKDEN                     MDF_CKGCR_CKDEN_Msk                     /*!<CKGEN diveders enable */
+#define MDF_CKGCR_CCK0EN_Pos                (1U)
+#define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
+#define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!<CCK0 clock enable */
+#define MDF_CKGCR_CCK1EN_Pos                (2U)
+#define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
+#define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!<CCK1 clock enable */
+#define MDF_CKGCR_CKGMOD_Pos                (4U)
+#define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
+#define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!<Clock genartor mode */
+#define MDF_CKGCR_CCK0DIR_Pos               (5U)
+#define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
+#define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!<CCK0 clock direction */
+#define MDF_CKGCR_CCK1DIR_Pos               (6U)
+#define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
+#define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!<CCK1 clock direction */
+#define MDF_CKGCR_TRGSENS_Pos               (8U)
+#define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
+#define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!<CKGEN trigger sensitivity selection */
+#define MDF_CKGCR_TRGSRC_Pos                (12U)
+#define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
+#define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!<Digital Filter trigger signal selection */
+#define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
+#define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
+#define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
+#define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
+#define MDF_CKGCR_CCKDIV_Pos                (16U)
+#define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
+#define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!<Divider to control the MDF_CCK clock */
+#define MDF_CKGCR_PROCDIV_Pos               (24U)
+#define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
+#define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!<Divider to control the serial interface clock */
+#define MDF_CKGCR_CCKACTIVE_Pos             (31U)
+#define MDF_CKGCR_CCKACTIVE_Msk             (0x1UL << MDF_CKGCR_CCKACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_CKGCR_CCKACTIVE                 MDF_CKGCR_CCKACTIVE_Msk                 /*!<Clock generator active flag */
+
+/*******************  Bit definition for MDF/ADF_OR register  ********************/
+#define MDF_OR_OPTION_Pos                   (0U)
+#define MDF_OR_OPTION_Msk                   (0xFFFFFFFFUL << MDF_OR_OPTION_Pos)     /*!< 0xFFFFFFFF */
+#define MDF_OR_OPTION                       MDF_OR_OPTION_Msk                       /*!<Option Control Bits */
+
+/*******************  Bit definition for MDF/ADF_SITFxCR register  ********************/
+#define MDF_SITFCR_SITFEN_Pos               (0U)
+#define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
+#define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!<Serial interface enable */
+#define MDF_SITFCR_SCKSRC_Pos               (1U)
+#define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
+#define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!<Serial clock source */
+#define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SITFMOD_Pos              (4U)
+#define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
+#define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!<Serial interface type */
+#define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
+#define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
+#define MDF_SITFCR_STH_Pos                  (8U)
+#define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
+#define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!<Manchester Symbol threshold / SPI threshold */
+#define MDF_SITFCR_SITFACTIVE_Pos           (31U)
+#define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
+#define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!<Serial interface active flag */
+
+/*******************  Bit definition for MDF/ADF_BSMXxCR register  ********************/
+#define MDF_BSMXCR_BSSEL_Pos                (0U)
+#define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
+#define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!<Bit Streal selection */
+#define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
+#define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
+#define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
+#define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
+#define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
+#define MDF_BSMXCR_BSMXACTIVATE_Pos         (31U)
+#define MDF_BSMXCR_BSMXACTIVATE_Msk         (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos)  /*!< 0x80000000 */
+#define MDF_BSMXCR_BSMXACTIVATE             MDF_BSMXCR_BSMXACTIVATE_Msk             /*!<Bit Streal activation flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCR register  ********************/
+#define MDF_DFLTCR_DFLTEN_Pos               (0U)
+#define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!<Digital filter enable */
+#define MDF_DFLTCR_DMAEN_Pos                (1U)
+#define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
+#define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!<DMA request enable */
+#define MDF_DFLTCR_FTH_Pos                  (2U)
+#define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
+#define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!<RXFIFO Threshold selection */
+#define MDF_DFLTCR_ACQMOD_Pos               (4U)
+#define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!<Digital filter trigger mode */
+#define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
+#define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
+#define MDF_DFLTCR_TRGSENS_Pos              (8U)
+#define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!<Digital filter trigger sensitivity selection */
+#define MDF_DFLTCR_TRGSRC_Pos               (12U)
+#define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!<Digital filter trigger signal selection */
+#define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
+#define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
+#define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
+#define MDF_DFLTCR_SNPSFMT_Pos              (16U)
+#define MDF_DFLTCR_SNPSFMT_Msk              (0x1UL << MDF_DFLTCR_SNPSFMT_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_SNPSFMT                  MDF_DFLTCR_SNPSFMT_Msk                  /*!<SnapShot Data format */
+#define MDF_DFLTCR_NBDIS_Pos                (20U)
+#define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!<Number of samples to be discard */
+#define MDF_DFLTCR_DFLTRUN_Pos              (30U)
+#define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!<Digital filter run status flag */
+#define MDF_DFLTCR_DFLTACTIVE_Pos           (31U)
+#define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!<Digital filter active flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCICR register  ********************/
+#define MDF_DFLTCICR_DATSRC_Pos             (0U)
+#define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!<Source Data for the digital filter */
+#define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTCICR_CICMOD_Pos             (4U)
+#define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
+#define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!<Select the CIC Mode*/
+#define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
+#define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
+#define MDF_DFLTCICR_MCICD_Pos              (8U)
+#define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
+#define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!<CIC decimation ratio selection*/
+#define MDF_DFLTCICR_SCALE_Pos              (20U)
+#define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
+#define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!<Scaling factor selection*/
+
+/*******************  Bit definition for MDF/ADF_DFLTxRSFR register  ********************/
+#define MDF_DFLTRSFR_RSFLTBYP_Pos           (0U)
+#define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
+#define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!<Reshape filter bypass*/
+#define MDF_DFLTRSFR_RSFLTD_Pos             (4U)
+#define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!<Reshape filter decimation ratio*/
+#define MDF_DFLTRSFR_HPFBYP_Pos             (7U)
+#define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!<High-pass filter bypass*/
+#define MDF_DFLTRSFR_HPFC_Pos               (8U)
+#define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!<High-pass filter cut-off frequency*/
+#define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
+#define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)
+
+/*******************  Bit definition for MDF/ADF_DFLTxINTR register  ********************/
+#define MDF_DFLTINTR_INTDIV_Pos             (0U)
+#define MDF_DFLTINTR_INTDIV_Msk             (0x3UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTINTR_INTDIV                 MDF_DFLTINTR_INTDIV_Msk                 /*!<Integrator output dividion*/
+#define MDF_DFLTINTR_INTDIV_0               (0x1UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTINTR_INTDIV_1               (0x2UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTINTR_INTVAL_Pos             (4U)
+#define MDF_DFLTINTR_INTVAL_Msk             (0x7FUL << MDF_DFLTINTR_INTVAL_Pos)     /*!< 0x000007F0 */
+#define MDF_DFLTINTR_INTVAL                 MDF_DFLTINTR_INTVAL_Msk                 /*!<Integrator value selection*/
+
+/*******************  Bit definition for MDF/ADF_OLDxCR register  ********************/
+#define MDF_OLDCR_OLDEN_Pos                 (0U)
+#define MDF_OLDCR_OLDEN_Msk                 (0x1UL << MDF_OLDCR_OLDEN_Pos)          /*!< 0x00000001 */
+#define MDF_OLDCR_OLDEN                     MDF_OLDCR_OLDEN_Msk                     /*!<OLD enable*/
+#define MDF_OLDCR_THINB_Pos                 (1U)
+#define MDF_OLDCR_THINB_Msk                 (0x1UL << MDF_OLDCR_THINB_Pos)          /*!< 0x00000002 */
+#define MDF_OLDCR_THINB                     MDF_OLDCR_THINB_Msk                     /*!<OLD threshold in band*/
+#define MDF_OLDCR_BKOLD_Pos                 (4U)
+#define MDF_OLDCR_BKOLD_Msk                 (0xFUL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x000000F0 */
+#define MDF_OLDCR_BKOLD                     MDF_OLDCR_BKOLD_Msk                     /*!<Bteak signal assignment for OLD*/
+#define MDF_OLDCR_BKOLD_0                   (0x1UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000010 */
+#define MDF_OLDCR_BKOLD_1                   (0x2UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000020 */
+#define MDF_OLDCR_BKOLD_2                   (0x4UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000040 */
+#define MDF_OLDCR_BKOLD_3                   (0x8UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000080 */
+#define MDF_OLDCR_ACICN_Pos                 (12U)
+#define MDF_OLDCR_ACICN_Msk                 (0x3UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00003000 */
+#define MDF_OLDCR_ACICN                     MDF_OLDCR_ACICN_Msk                     /*!<OLD CIC order selection*/
+#define MDF_OLDCR_ACICN_0                   (0x1UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00001000 */
+#define MDF_OLDCR_ACICN_1                   (0x2UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00002000 */
+#define MDF_OLDCR_ACICD_Pos                 (17U)
+#define MDF_OLDCR_ACICD_Msk                 (0x1FUL << MDF_OLDCR_ACICD_Pos)         /*!< 0x003E0000 */
+#define MDF_OLDCR_ACICD                     MDF_OLDCR_ACICD_Msk                     /*!<OLD CIC decimation ratio selection*/
+#define MDF_OLDCR_OLDACTIVE_Pos             (31U)
+#define MDF_OLDCR_OLDACTIVE_Msk             (0x1UL << MDF_OLDCR_OLDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_OLDCR_OLDACTIVE                 MDF_OLDCR_OLDACTIVE_Msk                 /*!<OLD active flag*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHLR register  ********************/
+#define MDF_OLDTHLR_OLDTHL_Pos              (0U)
+#define MDF_OLDTHLR_OLDTHL_Msk              (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHLR_OLDTHL                  MDF_OLDTHLR_OLDTHL_Msk                  /*!<OLD Low threshold value*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHHR register  ********************/
+#define MDF_OLDTHHR_OLDTHH_Pos              (0U)
+#define MDF_OLDTHHR_OLDTHH_Msk              (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHHR_OLDTHH                  MDF_OLDTHHR_OLDTHH_Msk                  /*!<OLD High threshold value*/
+
+/*******************  Bit definition for MDF/ADF_DLYxCR register  ********************/
+#define MDF_DLYCR_SKPDLY_Pos                (0U)
+#define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
+#define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!<Delay to apply to a bitstream*/
+#define MDF_DLYCR_SKPBF_Pos                 (31U)
+#define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
+#define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!<DSkip Busy Flag*/
+
+/*******************  Bit definition for MDF/ADF_SCDxCR register  ********************/
+#define MDF_SCDCR_SCDEN_Pos                 (0U)
+#define MDF_SCDCR_SCDEN_Msk                 (0x1UL << MDF_SCDCR_SCDEN_Pos)          /*!< 0x00000001 */
+#define MDF_SCDCR_SCDEN                     MDF_SCDCR_SCDEN_Msk                     /*!<Short circuit detector enable*/
+#define MDF_SCDCR_BKSCD_Pos                 (4U)
+#define MDF_SCDCR_BKSCD_Msk                 (0xFUL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x000000F0 */
+#define MDF_SCDCR_BKSCD                     MDF_SCDCR_BKSCD_Msk                     /*!<Break signal assignment to short circuit detector */
+#define MDF_SCDCR_BKSCD_0                   (0x1UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000010 */
+#define MDF_SCDCR_BKSCD_1                   (0x2UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000020 */
+#define MDF_SCDCR_BKSCD_2                   (0x4UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000040 */
+#define MDF_SCDCR_BKSCD_3                   (0x8UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000080 */
+#define MDF_SCDCR_SCDT_Pos                  (12U)
+#define MDF_SCDCR_SCDT_Msk                  (0xFFUL << MDF_SCDCR_SCDT_Pos)          /*!< 0x00000FF00 */
+#define MDF_SCDCR_SCDT                      MDF_SCDCR_SCDT_Msk                      /*!<Short circuit detector threshold*/
+#define MDF_SCDCR_SCDACTIVE_Pos             (31U)
+#define MDF_SCDCR_SCDACTIVE_Msk             (0x1UL << MDF_SCDCR_SCDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SCDCR_SCDACTIVE                 MDF_SCDCR_SCDACTIVE_Msk                 /*!<Short circuit detector active flag*/
+
+/*******************  Bit definition for MDF/ADF_DFLTIER register  ********************/
+#define MDF_DFLTIER_FTHIE_Pos               (0U)
+#define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!<RXFIFO threshold interrupt enable*/
+#define MDF_DFLTIER_DOVRIE_Pos              (1U)
+#define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
+#define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!<Data overflow interrupt enable*/
+#define MDF_DFLTIER_SSDRIE_Pos              (2U)
+#define MDF_DFLTIER_SSDRIE_Msk              (0x1UL << MDF_DFLTIER_SSDRIE_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTIER_SSDRIE                  MDF_DFLTIER_SSDRIE_Msk                  /*!<Snapshot data ready interrupt enable*/
+#define MDF_DFLTIER_OLDIE_Pos               (4U)
+#define MDF_DFLTIER_OLDIE_Msk               (0x1UL << MDF_DFLTIER_OLDIE_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTIER_OLDIE                   MDF_DFLTIER_OLDIE_Msk                   /*!<OLD interrupt enable*/
+#define MDF_DFLTIER_SSOVRIE_Pos             (7U)
+#define MDF_DFLTIER_SSOVRIE_Msk             (0x1UL << MDF_DFLTIER_SSOVRIE_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTIER_SSOVRIE                 MDF_DFLTIER_SSOVRIE_Msk                 /*!<Snapshot overrun interrupt enable*/
+#define MDF_DFLTIER_SCDIE_Pos               (8U)
+#define MDF_DFLTIER_SCDIE_Msk               (0x1UL << MDF_DFLTIER_SCDIE_Pos)        /*!< 0x00000100 */
+#define MDF_DFLTIER_SCDIE                   MDF_DFLTIER_SCDIE_Msk                   /*!<Short circuit dtector interrupt enable*/
+#define MDF_DFLTIER_SATIE_Pos               (9U)
+#define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
+#define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!<Saturation detection interrupt enable*/
+#define MDF_DFLTIER_CKABIE_Pos              (10U)
+#define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
+#define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!<Clock absence detection interrupt enable*/
+#define MDF_DFLTIER_RFOVRIE_Pos             (11U)
+#define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
+#define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!<reshape filter overrun interrupt enable*/
+#define MDF_DFLTIER_SDDETIE_Pos             (12U)
+#define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
+#define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!<SAD interrupt enable*/
+#define MDF_DFLTIER_SDLVLIE_Pos             (13U)
+#define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
+#define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!<Sound level value ready interrupt enable*/
+
+/*******************  Bit definition for MDF/ADF_DFLTISR register  ********************/
+#define MDF_DFLTISR_FTHF_Pos                (0U)
+#define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
+#define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!<RXFIFO threshold interrupt flag*/
+#define MDF_DFLTISR_DOVRF_Pos               (1U)
+#define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
+#define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!<Data overflow interrupt flag*/
+#define MDF_DFLTISR_SSDRF_Pos               (2U)
+#define MDF_DFLTISR_SSDRF_Msk               (0x1UL << MDF_DFLTISR_SSDRF_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTISR_SSDRF                   MDF_DFLTISR_SSDRF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_RXNEF_Pos               (3U)
+#define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
+#define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_OLDF_Pos                (4U)
+#define MDF_DFLTISR_OLDF_Msk                (0x1UL << MDF_DFLTISR_OLDF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_OLDF                    MDF_DFLTISR_OLDF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THLF_Pos                (5U)
+#define MDF_DFLTISR_THLF_Msk                (0x1UL << MDF_DFLTISR_THLF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THLF                    MDF_DFLTISR_THLF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THHF_Pos                (6U)
+#define MDF_DFLTISR_THHF_Msk                (0x1UL << MDF_DFLTISR_THHF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THHF                    MDF_DFLTISR_THHF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_SSOVRF_Pos              (7U)
+#define MDF_DFLTISR_SSOVRF_Msk              (0x1UL << MDF_DFLTISR_SSOVRF_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTISR_SSOVRF                  MDF_DFLTISR_SSOVRF_Msk                  /*!<Snapshot overrun interrupt flag*/
+#define MDF_DFLTISR_SCDF_Pos                (8U)
+#define MDF_DFLTISR_SCDF_Msk                (0x1UL << MDF_DFLTISR_SCDF_Pos)         /*!< 0x00000100 */
+#define MDF_DFLTISR_SCDF                    MDF_DFLTISR_SCDF_Msk                    /*!<Short circuit dtector interrupt flag*/
+#define MDF_DFLTISR_SATF_Pos                (9U)
+#define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
+#define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!<Saturation detection interrupt flag*/
+#define MDF_DFLTISR_CKABF_Pos               (10U)
+#define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
+#define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!<Clock absence detection interrupt flag*/
+#define MDF_DFLTISR_RFOVRF_Pos              (11U)
+#define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
+#define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!<reshape filter overrun interrupt flag*/
+#define MDF_DFLTISR_SDDETF_Pos              (12U)
+#define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!<SAD interrupt flag*/
+#define MDF_DFLTISR_SDLVLF_Pos              (13U)
+#define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
+#define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!<Sound level value ready interrupt flag*/
+
+/*******************  Bit definition for MDF/ADF_OECCR register  ********************/
+#define MDF_OECCR_OFFSET_Pos                (0U)
+#define MDF_OECCR_OFFSET_Msk                (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos)   /*!< 0x03FFFFFF */
+#define MDF_OECCR_OFFSET                    MDF_OECCR_OFFSET_Msk                    /*!<Short circuit detector enable*/
+
+/*******************  Bit definition for MDF/ADF_SADCR register  ********************/
+#define MDF_SADCR_SADEN_Pos                 (0U)
+#define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
+#define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!<SAD enable*/
+#define MDF_SADCR_DATCAP_Pos                (1U)
+#define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
+#define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!<SAD data capture mode*/
+#define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
+#define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
+#define MDF_SADCR_DETCFG_Pos                (3U)
+#define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
+#define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!<SAD trigger event configuration*/
+#define MDF_SADCR_SADST_Pos                 (4U)
+#define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
+#define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!<SAD state*/
+#define MDF_SADCR_HYSTEN_Pos                (7U)
+#define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
+#define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!<Hysteresis enable*/
+#define MDF_SADCR_FRSIZE_Pos                (8U)
+#define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
+#define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!<Frame size*/
+#define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
+#define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
+#define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
+#define MDF_SADCR_SADMOD_Pos                (12U)
+#define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
+#define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!<SAD working mode*/
+#define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
+#define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
+#define MDF_SADCR_SADACTIVE_Pos             (31U)
+#define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!<SAD active flag*/
+
+/*******************  Bit definition for MDF/ADF_SADCFGR register  ********************/
+#define MDF_SADCFGR_SNTHR_Pos               (0U)
+#define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
+#define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!<Signal to noise threshold*/
+#define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
+#define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
+#define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
+#define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
+#define MDF_SADCFGR_ANSLP_Pos               (4U)
+#define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
+#define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!<Ambiant noise slope control*/
+#define MDF_SADCFGR_LFRNB_Pos               (8U)
+#define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
+#define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!<Number of learning frames*/
+#define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
+#define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
+#define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
+#define MDF_SADCFGR_HGOVR_Pos               (12U)
+#define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
+#define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!<Hangover time window*/
+#define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
+#define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
+#define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
+#define MDF_SADCFGR_ANMIN_Pos               (16U)
+#define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
+#define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!<Hangover time window*/
+
+/*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
+#define MDF_SADSDLVR_SDLVL_Pos              (0U)
+#define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!<Short term sound level*/
+
+/*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
+#define MDF_SADANLVR_ANLVL_Pos              (0U)
+#define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!<Ambiant noise level estimation*/
+
+/*******************  Bit definition for MDF/ADF_SNPSDR register  ********************/
+#define MDF_SNPSDR_MCICDC_Pos               (0U)
+#define MDF_SNPSDR_MCICDC_Msk               (0x1FFUL << MDF_SNPSDR_MCICDC_Pos)      /*!< 0x000001FF */
+#define MDF_SNPSDR_MCICDC                   MDF_SNPSDR_MCICDC_Msk                   /*!<MCIC decimation counter*/
+#define MDF_SNPSDR_EXTSDR_Pos               (9U)
+#define MDF_SNPSDR_EXTSDR_Msk               (0x7FUL << MDF_SNPSDR_EXTSDR_Pos)       /*!< 0x0000FE00 */
+#define MDF_SNPSDR_EXTSDR                   MDF_SNPSDR_EXTSDR_Msk                   /*!<Extended data size*/
+#define MDF_SNPSDR_SDR_Pos                  (16U)
+#define MDF_SNPSDR_SDR_Msk                  (0xFFFFUL << MDF_SNPSDR_SDR_Pos)        /*!< 0xFFFF0000 */
+#define MDF_SNPSDR_SDR                      MDF_SNPSDR_SDR_Msk                      /*!<Extended data size*/
+
+/*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
+#define MDF_DFLTDR_DR_Pos                   (8U)
+#define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
+#define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!<MCIC decimation counter*/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDIOS                                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Public Key Accelerator (PKA)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PKA_CR register  *********************/
+#define PKA_CR_EN_Pos                       (0U)
+#define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
+#define PKA_CR_EN                           PKA_CR_EN_Msk                           /*!< PKA enable */
+#define PKA_CR_START_Pos                    (1U)
+#define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
+#define PKA_CR_START                        PKA_CR_START_Msk                        /*!< Start operation */
+#define PKA_CR_MODE_Pos                     (8U)
+#define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
+#define PKA_CR_MODE                         PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
+#define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
+#define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
+#define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
+#define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
+#define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
+#define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
+#define PKA_CR_PROCENDIE_Pos                (17U)
+#define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
+#define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
+#define PKA_CR_RAMERRIE_Pos                 (19U)
+#define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
+#define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
+#define PKA_CR_ADDRERRIE_Pos                (20U)
+#define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
+#define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                    /*!< Address error interrupt enable */
+#define PKA_CR_OPERRIE_Pos                  (21U)
+#define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)           /*!< 0x00200000 */
+#define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                      /*!< Operation Error interrupt enable */
+
+/*******************  Bit definition for PKA_SR register  *********************/
+#define PKA_SR_INITOK_Pos                   (0U)
+#define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)            /*!< 0x00000001 */
+#define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                       /*!< PKA initialisation flag */
+#define PKA_SR_BUSY_Pos                     (16U)
+#define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
+#define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
+#define PKA_SR_PROCENDF_Pos                 (17U)
+#define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
+#define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
+#define PKA_SR_RAMERRF_Pos                  (19U)
+#define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
+#define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
+#define PKA_SR_ADDRERRF_Pos                 (20U)
+#define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
+#define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
+#define PKA_SR_OPERRF_Pos                   (21U)
+#define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)            /*!< 0x00200000 */
+#define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                       /*!< PKA operation Error flag*/
+
+/*******************  Bit definition for PKA_CLRFR register  ******************/
+#define PKA_CLRFR_PROCENDFC_Pos             (17U)
+#define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
+#define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
+#define PKA_CLRFR_RAMERRFC_Pos              (19U)
+#define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
+#define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
+#define PKA_CLRFR_ADDRERRFC_Pos             (20U)
+#define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
+#define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
+#define PKA_CLRFR_OPERRFC_Pos               (21U)
+#define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)        /*!< 0x00200000 */
+#define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                   /*!< Clear PKA operation Error flag*/
+
+/*******************  Bits definition for PKA RAM  *************************/
+#define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */
+
+/* Compute Montgomery parameter input data */
+#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Compute Montgomery parameter output data */
+#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */
+
+/* Compute modular exponentiation input data */
+#define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
+#define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+#define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
+#define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
+#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */
+
+/* Compute modular exponentiation output data */
+#define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */
+
+/* Compute ECC scalar multiplication input data */
+#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */
+
+/* Compute ECC scalar multiplication output data */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
+
+/* Point check input data */
+#define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+
+/* Point check output data */
+#define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+
+/* ECDSA signature input data */
+#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
+#define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA signature output data */
+#define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */
+
+
+/* ECDSA verification input data */
+#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
+#define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA verification output data */
+#define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* RSA CRT exponentiation input data */
+#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
+#define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
+#define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
+#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+
+/* RSA CRT exponentiation output data */
+#define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular reduction input data */
+#define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
+#define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
+#define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
+#define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Modular reduction output data */
+#define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic addition input data */
+#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic addition output data */
+#define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic subtraction input data */
+#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic subtraction output data */
+#define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic multiplication input data */
+#define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic multiplication output data */
+#define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Comparison input data */
+#define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Comparison output data */
+#define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular addition input data */
+#define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
+
+/* Modular addition output data */
+#define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular inversion input data */
+#define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
+
+/* Modular inversion output data */
+#define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular subtraction input data */
+#define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
+
+/* Modular subtraction output data */
+#define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Montgomery multiplication input data */
+#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
+
+/* Montgomery multiplication output data */
+#define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Generic Arithmetic input data */
+#define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
+
+/* Generic Arithmetic output data */
+#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)   /*!< Output result for arithmetic operations */
+
+/* Compute ECC complete addition input data */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)   /*!< Input Modulus number of bits */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Z coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC complete addition output data */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Z coordinate */
+
+/* Compute ECC double base ladder input data */
+#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS  ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN         ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF              ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER            ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X             ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y             ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z             ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X             ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y             ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z             ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC double base ladder output data */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)      /*!< Output result X coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y          ((0x05D0UL - PKA_RAM_OFFSET)>>2)      /*!< Output result Y coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR             ((0x0520UL - PKA_RAM_OFFSET)>>2)      /*!< Output result error */
+
+/* Compute ECC projective to affine conversion input data */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)  /*!< Input Modulus number of bits */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)  /*!< Input modulus GF(p) */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X               ((0x0D60UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P X coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y               ((0x0DB8UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Y coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z               ((0x0E10UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Z coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2   ((0x04C8UL - PKA_RAM_OFFSET)>>2)  /*!< Input storage area for Montgomery parameter */
+
+/* Compute ECC projective to affine conversion output data */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X      ((0x0578UL - PKA_RAM_OFFSET)>>2)         /*!< Output result x affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y      ((0x05D0UL - PKA_RAM_OFFSET)>>2)         /*!< Output result y affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR         ((0x0680UL - PKA_RAM_OFFSET)>>2)         /*!< Output result error */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                Parallel Synchronous Slave Interface (PSSI )                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PSSI_CR register  *******************/
+#define PSSI_CR_CKPOL_Pos                   (5U)
+#define PSSI_CR_CKPOL_Msk                   (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
+#define PSSI_CR_CKPOL                       PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
+#define PSSI_CR_DEPOL_Pos                   (6U)
+#define PSSI_CR_DEPOL_Msk                   (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
+#define PSSI_CR_DEPOL                       PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
+#define PSSI_CR_RDYPOL_Pos                  (8U)
+#define PSSI_CR_RDYPOL_Msk                  (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
+#define PSSI_CR_RDYPOL                      PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
+#define PSSI_CR_EDM_Pos                     (10U)
+#define PSSI_CR_EDM_Msk                     (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define PSSI_CR_EDM                         PSSI_CR_EDM_Msk                         /*!< Extended data mode */
+#define PSSI_CR_ENABLE_Pos                  (14U)
+#define PSSI_CR_ENABLE_Msk                  (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define PSSI_CR_ENABLE                      PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
+#define PSSI_CR_DERDYCFG_Pos                (18U)
+#define PSSI_CR_DERDYCFG_Msk                (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
+#define PSSI_CR_DERDYCFG                    PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
+#define PSSI_CR_CKSRC_Pos                   (29U)
+#define PSSI_CR_CKSRC_Msk                   (0x1UL << PSSI_CR_CKSRC_Pos)            /*!< 0x20000000 */
+#define PSSI_CR_CKSRC                       PSSI_CR_CKSRC_Msk                       /*!< Clock source */
+#define PSSI_CR_DMAEN_Pos                   (30U)
+#define PSSI_CR_DMAEN_Msk                   (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
+#define PSSI_CR_DMAEN                       PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
+#define PSSI_CR_OUTEN_Pos                   (31U)
+#define PSSI_CR_OUTEN_Msk                   (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
+#define PSSI_CR_OUTEN                       PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */
+
+/********************  Bit definition for PSSI_SR register  *******************/
+#define PSSI_SR_RTT4B_Pos                   (2U)
+#define PSSI_SR_RTT4B_Msk                   (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
+#define PSSI_SR_RTT4B                       PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
+#define PSSI_SR_RTT1B_Pos                   (3U)
+#define PSSI_SR_RTT1B_Msk                   (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
+#define PSSI_SR_RTT1B                       PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */
+
+/********************  Bit definition for PSSI_RIS register  *******************/
+#define PSSI_RIS_OVR_RIS_Pos                (1U)
+#define PSSI_RIS_OVR_RIS_Msk                (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define PSSI_RIS_OVR_RIS                    PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */
+
+/********************  Bit definition for PSSI_IER register  *******************/
+#define PSSI_IER_OVR_IE_Pos                 (1U)
+#define PSSI_IER_OVR_IE_Msk                 (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define PSSI_IER_OVR_IE                     PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */
+
+/********************  Bit definition for PSSI_MIS register  *******************/
+#define PSSI_MIS_OVR_MIS_Pos                (1U)
+#define PSSI_MIS_OVR_MIS_Msk                (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define PSSI_MIS_OVR_MIS                    PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */
+
+/********************  Bit definition for PSSI_ICR register  *******************/
+#define PSSI_ICR_OVR_ISC_Pos                (1U)
+#define PSSI_ICR_OVR_ISC_Msk                (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define PSSI_ICR_OVR_ISC                    PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */
+
+/********************  Bit definition for PSSI_DR register  *******************/
+#define PSSI_DR_DR_Pos                      (0U)
+#define PSSI_DR_DR_Msk                      (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
+#define PSSI_DR_DR                          PSSI_DR_DR_Msk                          /*!< Data register  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PWR_CR1 register  ********************/
+#define PWR_CR1_SDEN_Pos                (2U)
+#define PWR_CR1_SDEN_Msk                (0x1UL << PWR_CR1_SDEN_Pos)             /*!< 0x00000004 */
+#define PWR_CR1_SDEN                    PWR_CR1_SDEN_Msk                        /*!< SMPS step-down converter enable */
+#define PWR_CR1_MODE_PDN_Pos            (4U)
+#define PWR_CR1_MODE_PDN_Msk            (0x1UL << PWR_CR1_MODE_PDN_Pos)         /*!< 0x00000010 */
+#define PWR_CR1_MODE_PDN                PWR_CR1_MODE_PDN_Msk                    /*!< Pull down on output voltage during power down mode */
+#define PWR_CR1_LPDS08V_Pos             (5U)
+#define PWR_CR1_LPDS08V_Msk             (0x1UL << PWR_CR1_LPDS08V_Pos)          /*!< 0x00000020 */
+#define PWR_CR1_LPDS08V                 PWR_CR1_LPDS08V_Msk                     /*!< SMPS Low power mode enable (SVOS high only) */
+#define PWR_CR1_VDD18SMPSVMEN_Pos       (8U)
+#define PWR_CR1_VDD18SMPSVMEN_Msk       (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos)    /*!< 0x00000100 */
+#define PWR_CR1_VDD18SMPSVMEN           PWR_CR1_VDD18SMPSVMEN_Msk               /*!< VDD18SMPS voltage monitor enable */
+#define PWR_CR1_VDD18SMPSRDY_Pos        (15U)
+#define PWR_CR1_VDD18SMPSRDY_Msk        (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos)     /*!< 0x00008000 */
+#define PWR_CR1_VDD18SMPSRDY            PWR_CR1_VDD18SMPSRDY_Msk                /*!< VDD18SMPS ready */
+#define PWR_CR1_POPL_Pos                (16U)
+#define PWR_CR1_POPL_Msk                (0x1FUL << PWR_CR1_POPL_Pos)            /*!< 0x001F0000 */
+#define PWR_CR1_POPL                    PWR_CR1_POPL_Msk                        /*!< pwr_on pulse low configuration */
+#define PWR_CR1_POPL_0                  (0x1UL << PWR_CR1_POPL_Pos)             /*!< 0x00010000 */
+#define PWR_CR1_POPL_1                  (0x2UL << PWR_CR1_POPL_Pos)             /*!< 0x00020000 */
+#define PWR_CR1_POPL_2                  (0x4UL << PWR_CR1_POPL_Pos)             /*!< 0x00040000 */
+#define PWR_CR1_POPL_3                  (0x8UL << PWR_CR1_POPL_Pos)             /*!< 0x00080000 */
+#define PWR_CR1_POPL_4                  (0x10UL << PWR_CR1_POPL_Pos)            /*!< 0x00100000 */
+
+/*******************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_PVDEN_Pos               (0U)
+#define PWR_CR2_PVDEN_Msk               (0x1UL << PWR_CR2_PVDEN_Pos)            /*!< 0x00000001 */
+#define PWR_CR2_PVDEN                   PWR_CR2_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR2_PVDO_Pos                (8U)
+#define PWR_CR2_PVDO_Msk                (0x1UL << PWR_CR2_PVDO_Pos)             /*!< 0x00000100 */
+#define PWR_CR2_PVDO                    PWR_CR2_PVDO_Msk                        /*!< Programmable Voltage Detect Output */
+
+/*******************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_VCOREMONEN_Pos          (0U)
+#define PWR_CR3_VCOREMONEN_Msk          (0x1UL << PWR_CR3_VCOREMONEN_Pos)       /*!< 0x00000001 */
+#define PWR_CR3_VCOREMONEN              PWR_CR3_VCOREMONEN_Msk                  /*!< VDDCORE monitoring enable */
+#define PWR_CR3_VCORELLS_Pos            (4U)
+#define PWR_CR3_VCORELLS_Msk            (0x1UL << PWR_CR3_VCORELLS_Pos)         /*!< 0x00000010 */
+#define PWR_CR3_VCORELLS                PWR_CR3_VCORELLS_Msk                    /*!< VDDCORE Voltage Detector low level selection */
+#define PWR_CR3_VCOREL_Pos              (8U)
+#define PWR_CR3_VCOREL_Msk              (0x1UL << PWR_CR3_VCOREL_Pos)           /*!< 0x00000100 */
+#define PWR_CR3_VCOREL                  PWR_CR3_VCOREL_Msk                      /*!< Monitored VDDCORE level above low threshold */
+#define PWR_CR3_VCOREH_Pos              (9U)
+#define PWR_CR3_VCOREH_Msk              (0x1UL << PWR_CR3_VCOREH_Pos)           /*!< 0x00000200 */
+#define PWR_CR3_VCOREH                  PWR_CR3_VCOREH_Msk                      /*!< Monitored VDDCORE level above high threshold */
+
+/*******************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_TCMRBSEN_Pos            (0U)
+#define PWR_CR4_TCMRBSEN_Msk            (0x1UL << PWR_CR4_TCMRBSEN_Pos)         /*!< 0x00000001 */
+#define PWR_CR4_TCMRBSEN                PWR_CR4_TCMRBSEN_Msk                    /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */
+#define PWR_CR4_TCMFLXRBSEN_Pos         (4U)
+#define PWR_CR4_TCMFLXRBSEN_Msk         (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos)      /*!< 0x00000010 */
+#define PWR_CR4_TCMFLXRBSEN             PWR_CR4_TCMFLXRBSEN_Msk                 /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */
+
+/******************  Bit definition for PWR_VOSCR register  *******************/
+#define PWR_VOSCR_VOS_Pos               (0U)
+#define PWR_VOSCR_VOS_Msk               (0x1UL << PWR_VOSCR_VOS_Pos)            /*!< 0x00000001 */
+#define PWR_VOSCR_VOS                   PWR_VOSCR_VOS_Msk                       /*!< Voltage scaling selection according to performance */
+#define PWR_VOSCR_VOSRDY_Pos            (1U)
+#define PWR_VOSCR_VOSRDY_Msk            (0x1UL << PWR_VOSCR_VOSRDY_Pos)         /*!< 0x00000002 */
+#define PWR_VOSCR_VOSRDY                PWR_VOSCR_VOSRDY_Msk                    /*!< VOS Ready bit for VCORE voltage scaling output selection */
+#define PWR_VOSCR_ACTVOS_Pos            (16U)
+#define PWR_VOSCR_ACTVOS_Msk            (0x1UL << PWR_VOSCR_ACTVOS_Pos)         /*!< 0x00010000 */
+#define PWR_VOSCR_ACTVOS                PWR_VOSCR_ACTVOS_Msk                    /*!< VOS currently applied for VCORE voltage scaling selection */
+#define PWR_VOSCR_ACTVOSRDY_Pos         (17U)
+#define PWR_VOSCR_ACTVOSRDY_Msk         (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos)      /*!< 0x00020000 */
+#define PWR_VOSCR_ACTVOSRDY             PWR_VOSCR_ACTVOSRDY_Msk                 /*!< Voltage levels ready bit for currently used ACTVOS */
+
+/******************  Bit definition for PWR_BDCR1 register  *******************/
+#define PWR_BDCR1_MONEN_Pos             (0U)
+#define PWR_BDCR1_MONEN_Msk             (0x1UL << PWR_BDCR1_MONEN_Pos)          /*!< 0x00000001 */
+#define PWR_BDCR1_MONEN                 PWR_BDCR1_MONEN_Msk                     /*!< VBAT and temperature monitoring enable */
+#define PWR_BDCR1_VBATL_Pos             (16U)
+#define PWR_BDCR1_VBATL_Msk             (0x1UL << PWR_BDCR1_VBATL_Pos)          /*!< 0x00010000 */
+#define PWR_BDCR1_VBATL                 PWR_BDCR1_VBATL_Msk                     /*!< VBAT level monitoring versus low threshold */
+#define PWR_BDCR1_VBATH_Pos             (17U)
+#define PWR_BDCR1_VBATH_Msk             (0x1UL << PWR_BDCR1_VBATH_Pos)          /*!< 0x00020000 */
+#define PWR_BDCR1_VBATH                 PWR_BDCR1_VBATH_Msk                     /*!< VBAT level monitoring versus high threshold */
+#define PWR_BDCR1_TEMPL_Pos             (18U)
+#define PWR_BDCR1_TEMPL_Msk             (0x1UL << PWR_BDCR1_TEMPL_Pos)          /*!< 0x00040000 */
+#define PWR_BDCR1_TEMPL                 PWR_BDCR1_TEMPL_Msk                     /*!< Temperature level monitoring versus low threshold */
+#define PWR_BDCR1_TEMPH_Pos             (19U)
+#define PWR_BDCR1_TEMPH_Msk             (0x1UL << PWR_BDCR1_TEMPH_Pos)          /*!< 0x00080000 */
+#define PWR_BDCR1_TEMPH                 PWR_BDCR1_TEMPH_Msk                     /*!< Temperature level monitoring versus high threshold */
+
+/******************  Bit definition for PWR_BDCR2 register  *******************/
+#define PWR_BDCR2_BKPRBSEN_Pos          (0U)
+#define PWR_BDCR2_BKPRBSEN_Msk          (0x1UL << PWR_BDCR2_BKPRBSEN_Pos)       /*!< 0x00000001 */
+#define PWR_BDCR2_BKPRBSEN              PWR_BDCR2_BKPRBSEN_Msk                  /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */
+
+/******************  Bit definition for PWR_DBPCR register  *******************/
+#define PWR_DBPCR_DBP_Pos               (0U)
+#define PWR_DBPCR_DBP_Msk               (0x1UL << PWR_DBPCR_DBP_Pos)            /*!< 0x00000001 */
+#define PWR_DBPCR_DBP                   PWR_DBPCR_DBP_Msk                       /*!< Disable backup domain write protection */
+
+/******************  Bit definition for PWR_CPUCR register  *******************/
+#define PWR_CPUCR_PDDS_Pos              (0U)
+#define PWR_CPUCR_PDDS_Msk              (0x1UL << PWR_CPUCR_PDDS_Pos)           /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS                  PWR_CPUCR_PDDS_Msk                      /*!< Power Down Deepsleep selection */
+#define PWR_CPUCR_CSSF_Pos              (1U)
+#define PWR_CPUCR_CSSF_Msk              (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000002 */
+#define PWR_CPUCR_CSSF                  PWR_CPUCR_CSSF_Msk                      /*!< Clear Standby and Stop flags (always read as 0) */
+#define PWR_CPUCR_STOPF_Pos             (8U)
+#define PWR_CPUCR_STOPF_Msk             (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000100 */
+#define PWR_CPUCR_STOPF                 PWR_CPUCR_STOPF_Msk                     /*!< STOP flag */
+#define PWR_CPUCR_SBF_Pos               (9U)
+#define PWR_CPUCR_SBF_Msk               (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000200 */
+#define PWR_CPUCR_SBF                   PWR_CPUCR_SBF_Msk                       /*!< System Standby flag */
+#define PWR_CPUCR_SVOS_Pos              (16U)
+#define PWR_CPUCR_SVOS_Msk              (0x1UL << PWR_CPUCR_SVOS_Pos)           /*!< 0x00010000 */
+#define PWR_CPUCR_SVOS                  PWR_CPUCR_SVOS_Msk                      /*!< System Stop mode voltage scaling selection */
+
+/******************  Bit definition for PWR_SVMCR1 register  ******************/
+#define PWR_SVMCR1_VDDIO4VMEN_Pos       (0U)
+#define PWR_SVMCR1_VDDIO4VMEN_Msk       (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR1_VDDIO4VMEN           PWR_SVMCR1_VDDIO4VMEN_Msk               /*!< VDDOI4 Independent I/Os voltage monitor enable */
+#define PWR_SVMCR1_VDDIO4SV_Pos         (8U)
+#define PWR_SVMCR1_VDDIO4SV_Msk         (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR1_VDDIO4SV             PWR_SVMCR1_VDDIO4SV_Msk                 /*!< VDDIO4 Independent I/Os supply valid */
+#define PWR_SVMCR1_VDDIO4RDY_Pos        (16U)
+#define PWR_SVMCR1_VDDIO4RDY_Msk        (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR1_VDDIO4RDY            PWR_SVMCR1_VDDIO4RDY_Msk                /*!< VDDIO4 ready */
+#define PWR_SVMCR1_VDDIO4VRSEL_Pos      (24U)
+#define PWR_SVMCR1_VDDIO4VRSEL_Msk      (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR1_VDDIO4VRSEL          PWR_SVMCR1_VDDIO4VRSEL_Msk              /*!< VDDIO4 IO voltage range selection */
+#define PWR_SVMCR1_VDDIO4VRSTBY_Pos     (25U)
+#define PWR_SVMCR1_VDDIO4VRSTBY_Msk     (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos)  /*!< 0x04000000 */
+#define PWR_SVMCR1_VDDIO4VRSTBY         PWR_SVMCR1_VDDIO4VRSTBY_Msk             /*!< VDDIO4 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR2 register  ******************/
+#define PWR_SVMCR2_VDDIO5VMEN_Pos       (0U)
+#define PWR_SVMCR2_VDDIO5VMEN_Msk       (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR2_VDDIO5VMEN           PWR_SVMCR2_VDDIO5VMEN_Msk               /*!< VDDIO5 Independent voltage monitor enable */
+#define PWR_SVMCR2_VDDIO5SV_Pos         (8U)
+#define PWR_SVMCR2_VDDIO5SV_Msk         (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR2_VDDIO5SV             PWR_SVMCR2_VDDIO5SV_Msk                 /*!< VDDIO5 Independent supply valid */
+#define PWR_SVMCR2_VDDIO5RDY_Pos        (16U)
+#define PWR_SVMCR2_VDDIO5RDY_Msk        (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR2_VDDIO5RDY            PWR_SVMCR2_VDDIO5RDY_Msk                /*!< VDDIO5 ready */
+#define PWR_SVMCR2_VDDIO5VRSEL_Pos      (24U)
+#define PWR_SVMCR2_VDDIO5VRSEL_Msk      (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR2_VDDIO5VRSEL          PWR_SVMCR2_VDDIO5VRSEL_Msk              /*!< VDDIO5 IO voltage range selection */
+#define PWR_SVMCR2_VDDIO5VRSTBY_Pos     (25U)
+#define PWR_SVMCR2_VDDIO5VRSTBY_Msk     (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos)  /*!< 0x02000000 */
+#define PWR_SVMCR2_VDDIO5VRSTBY         PWR_SVMCR2_VDDIO5VRSTBY_Msk             /*!< VDDIO5 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR3 register  ******************/
+#define PWR_SVMCR3_VDDIO2VMEN_Pos       (0U)
+#define PWR_SVMCR3_VDDIO2VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR3_VDDIO2VMEN           PWR_SVMCR3_VDDIO2VMEN_Msk               /*!< VDDIO2 Independent voltage monitor enable */
+#define PWR_SVMCR3_VDDIO3VMEN_Pos       (1U)
+#define PWR_SVMCR3_VDDIO3VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos)    /*!< 0x00000002 */
+#define PWR_SVMCR3_VDDIO3VMEN           PWR_SVMCR3_VDDIO3VMEN_Msk               /*!< VDDIO3 Independent voltage monitor enable */
+#define PWR_SVMCR3_USB33VMEN_Pos        (2U)
+#define PWR_SVMCR3_USB33VMEN_Msk        (0x1UL << PWR_SVMCR3_USB33VMEN_Pos)     /*!< 0x00000004 */
+#define PWR_SVMCR3_USB33VMEN            PWR_SVMCR3_USB33VMEN_Msk                /*!< VDD33USB Independent USB 33 voltage monitor enable */
+#define PWR_SVMCR3_AVMEN_Pos            (4U)
+#define PWR_SVMCR3_AVMEN_Msk            (0x1UL << PWR_SVMCR3_AVMEN_Pos)         /*!< 0x00000010 */
+#define PWR_SVMCR3_AVMEN                PWR_SVMCR3_AVMEN_Msk                    /*!< VDDA18ADC Independent ADC voltage monitor enable */
+#define PWR_SVMCR3_VDDIO2SV_Pos         (8U)
+#define PWR_SVMCR3_VDDIO2SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR3_VDDIO2SV             PWR_SVMCR3_VDDIO2SV_Msk                 /*!< VDDIO2 Independent supply valid */
+#define PWR_SVMCR3_VDDIO3SV_Pos         (9U)
+#define PWR_SVMCR3_VDDIO3SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos)      /*!< 0x00000200 */
+#define PWR_SVMCR3_VDDIO3SV             PWR_SVMCR3_VDDIO3SV_Msk                 /*!< VDDIO3 Independent supply valid */
+#define PWR_SVMCR3_USB33SV_Pos          (10U)
+#define PWR_SVMCR3_USB33SV_Msk          (0x1UL << PWR_SVMCR3_USB33SV_Pos)       /*!< 0x00000400 */
+#define PWR_SVMCR3_USB33SV              PWR_SVMCR3_USB33SV_Msk                  /*!< VDD33USB Independent supply valid */
+#define PWR_SVMCR3_ASV_Pos              (12U)
+#define PWR_SVMCR3_ASV_Msk              (0x1UL << PWR_SVMCR3_ASV_Pos)           /*!< 0x00001000 */
+#define PWR_SVMCR3_ASV                  PWR_SVMCR3_ASV_Msk                      /*!< VDDA18ADC Independent supply valid */
+#define PWR_SVMCR3_VDDIO2RDY_Pos        (16U)
+#define PWR_SVMCR3_VDDIO2RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR3_VDDIO2RDY            PWR_SVMCR3_VDDIO2RDY_Msk                /*!< VDDIO2 ready */
+#define PWR_SVMCR3_VDDIO3RDY_Pos        (17U)
+#define PWR_SVMCR3_VDDIO3RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos)     /*!< 0x00020000 */
+#define PWR_SVMCR3_VDDIO3RDY            PWR_SVMCR3_VDDIO3RDY_Msk                /*!< VDDIO3 ready */
+#define PWR_SVMCR3_USB33RDY_Pos         (18U)
+#define PWR_SVMCR3_USB33RDY_Msk         (0x1UL << PWR_SVMCR3_USB33RDY_Pos)      /*!< 0x00040000 */
+#define PWR_SVMCR3_USB33RDY             PWR_SVMCR3_USB33RDY_Msk                 /*!< VDD33USB ready */
+#define PWR_SVMCR3_ARDY_Pos             (20U)
+#define PWR_SVMCR3_ARDY_Msk             (0x1UL << PWR_SVMCR3_ARDY_Pos)          /*!< 0x00100000 */
+#define PWR_SVMCR3_ARDY                 PWR_SVMCR3_ARDY_Msk                     /*!< VDDA18ADC ready */
+#define PWR_SVMCR3_VDDIOVRSEL_Pos       (24U)
+#define PWR_SVMCR3_VDDIOVRSEL_Msk       (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos)    /*!< 0x01000000 */
+#define PWR_SVMCR3_VDDIOVRSEL           PWR_SVMCR3_VDDIOVRSEL_Msk               /*!< VDD IO voltage range selection */
+#define PWR_SVMCR3_VDDIO2VRSEL_Pos      (25U)
+#define PWR_SVMCR3_VDDIO2VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos)   /*!< 0x02000000 */
+#define PWR_SVMCR3_VDDIO2VRSEL          PWR_SVMCR3_VDDIO2VRSEL_Msk              /*!< VDDIO2 IO voltage range selection */
+#define PWR_SVMCR3_VDDIO3VRSEL_Pos      (26U)
+#define PWR_SVMCR3_VDDIO3VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos)   /*!< 0x04000000 */
+#define PWR_SVMCR3_VDDIO3VRSEL          PWR_SVMCR3_VDDIO3VRSEL_Msk              /*!< VDDIO3 IO voltage range selection */
+
+/*****************  Bit definition for PWR_WKUPCR register  *******************/
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                    /*!< Clear Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                    /*!< Clear Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                    /*!< Clear Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                    /*!< Clear Wakeup Flag for WKUP4 pin */
+#define PWR_WKUPCR_WKUPC_Pos           (0U)
+#define PWR_WKUPCR_WKUPC_Msk           (0xFUL << PWR_WKUPCR_WKUPC_Pos)         /*!< 0x0000000F */
+#define PWR_WKUPCR_WKUPC               PWR_WKUPCR_WKUPC_Msk                    /*!< Clear Wakeup Flag 1 to 4 */
+
+/*****************  Bit definition for PWR_WKUPSR register  *******************/
+#define PWR_WKUPSR_WKUPF1_Pos          (0U)
+#define PWR_WKUPSR_WKUPF1_Msk          (0x1UL << PWR_WKUPSR_WKUPF1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPSR_WKUPF1              PWR_WKUPSR_WKUPF1_Msk                    /*!< Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPSR_WKUPF2_Pos          (1U)
+#define PWR_WKUPSR_WKUPF2_Msk          (0x1UL << PWR_WKUPSR_WKUPF2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPSR_WKUPF2              PWR_WKUPSR_WKUPF2_Msk                    /*!< Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPSR_WKUPF3_Pos          (2U)
+#define PWR_WKUPSR_WKUPF3_Msk          (0x1UL << PWR_WKUPSR_WKUPF3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPSR_WKUPF3              PWR_WKUPSR_WKUPF3_Msk                    /*!< Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPSR_WKUPF4_Pos          (3U)
+#define PWR_WKUPSR_WKUPF4_Msk          (0x1UL << PWR_WKUPSR_WKUPF4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPSR_WKUPF4              PWR_WKUPSR_WKUPF4_Msk                    /*!< Wakeup Flag for WKUP4 pin */
+
+/*****************  Bit definition for PWR_WKUPEPR register  *******************/
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)       /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                  /*!< Enable Wakeup pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)       /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                  /*!< Enable Wakeup pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)       /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                  /*!< Enable Wakeup pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)       /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                  /*!< Enable Wakeup pin WKUP4 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)        /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                   /*!< Wakeup Polarity bit for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)        /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                   /*!< Wakeup Polarity bit for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)        /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                   /*!< Wakeup Polarity bit for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)        /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                   /*!< Wakeup Polarity bit for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPP_Pos          (8U)
+#define PWR_WKUPEPR_WKUPP_Msk          (0x0FUL << PWR_WKUPEPR_WKUPP_Pos)        /*!< 0x0000300F */
+#define PWR_WKUPEPR_WKUPP              PWR_WKUPEPR_WKUPP_Msk                    /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk                /*!< Wakeup pull configuration for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk                /*!< Wakeup pull configuration for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk                /*!< Wakeup pull configuration for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk                /*!< Wakeup pull configuration for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos)       /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                   /*!< Enable all Wakeup Pin */
+
+/*****************  Bit definition for PWR_SECCFGR register  ******************/
+#define PWR_SECCFGR_SEC0_Pos            (0U)
+#define PWR_SECCFGR_SEC0_Msk            (0x1UL << PWR_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
+#define PWR_SECCFGR_SEC0                PWR_SECCFGR_SEC0_Msk                    /*!< System supply configuration secure protection */
+#define PWR_SECCFGR_SEC1_Pos            (1U)
+#define PWR_SECCFGR_SEC1_Msk            (0x1UL << PWR_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
+#define PWR_SECCFGR_SEC1                PWR_SECCFGR_SEC1_Msk                    /*!< Programmable voltage detector secure protection */
+#define PWR_SECCFGR_SEC2_Pos            (2U)
+#define PWR_SECCFGR_SEC2_Msk            (0x1UL << PWR_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
+#define PWR_SECCFGR_SEC2                PWR_SECCFGR_SEC2_Msk                    /*!< VDDCORE monitor secure protection */
+#define PWR_SECCFGR_SEC3_Pos            (3U)
+#define PWR_SECCFGR_SEC3_Msk            (0x1UL << PWR_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
+#define PWR_SECCFGR_SEC3                PWR_SECCFGR_SEC3_Msk                    /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */
+#define PWR_SECCFGR_SEC4_Pos            (4U)
+#define PWR_SECCFGR_SEC4_Msk            (0x1UL << PWR_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
+#define PWR_SECCFGR_SEC4                PWR_SECCFGR_SEC4_Msk                    /*!< Voltage scaling selection secure protection */
+#define PWR_SECCFGR_SEC5_Pos            (5U)
+#define PWR_SECCFGR_SEC5_Msk            (0x1UL << PWR_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
+#define PWR_SECCFGR_SEC5                PWR_SECCFGR_SEC5_Msk                    /*!< Backup domain secure protection */
+#define PWR_SECCFGR_SEC6_Pos            (6U)
+#define PWR_SECCFGR_SEC6_Msk            (0x1UL << PWR_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
+#define PWR_SECCFGR_SEC6                PWR_SECCFGR_SEC6_Msk                    /*!< CPU power control secure protection */
+#define PWR_SECCFGR_SEC7_Pos            (7U)
+#define PWR_SECCFGR_SEC7_Msk            (0x1UL << PWR_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
+#define PWR_SECCFGR_SEC7                PWR_SECCFGR_SEC7_Msk                    /*!< Peripheral voltage monitor secure protection */
+#define PWR_SECCFGR_WKUPSEC1_Pos        (16U)
+#define PWR_SECCFGR_WKUPSEC1_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos)     /*!< 0x00010000 */
+#define PWR_SECCFGR_WKUPSEC1            PWR_SECCFGR_WKUPSEC1_Msk                /*!< WKUP1 secure protection */
+#define PWR_SECCFGR_WKUPSEC2_Pos        (17U)
+#define PWR_SECCFGR_WKUPSEC2_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos)     /*!< 0x00020000 */
+#define PWR_SECCFGR_WKUPSEC2            PWR_SECCFGR_WKUPSEC2_Msk                /*!< WKUP2 secure protection */
+#define PWR_SECCFGR_WKUPSEC3_Pos        (18U)
+#define PWR_SECCFGR_WKUPSEC3_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos)     /*!< 0x00040000 */
+#define PWR_SECCFGR_WKUPSEC3            PWR_SECCFGR_WKUPSEC3_Msk                /*!< WKUP3 secure protection */
+#define PWR_SECCFGR_WKUPSEC4_Pos        (19U)
+#define PWR_SECCFGR_WKUPSEC4_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos)     /*!< 0x00080000 */
+#define PWR_SECCFGR_WKUPSEC4            PWR_SECCFGR_WKUPSEC4_Msk                /*!< WKUP4 secure protection */
+
+/*****************  Bit definition for PWR_PRIVCFGR register  *****************/
+#define PWR_PRIVCFGR_PRIV0_Pos          (0U)
+#define PWR_PRIVCFGR_PRIV0_Msk          (0x1UL << PWR_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define PWR_PRIVCFGR_PRIV0              PWR_PRIVCFGR_PRIV0_Msk                  /*!< System supply configuration privileged protection */
+#define PWR_PRIVCFGR_PRIV1_Pos          (1U)
+#define PWR_PRIVCFGR_PRIV1_Msk          (0x1UL << PWR_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define PWR_PRIVCFGR_PRIV1              PWR_PRIVCFGR_PRIV1_Msk                  /*!< Programmable voltage detector privileged protection */
+#define PWR_PRIVCFGR_PRIV2_Pos          (2U)
+#define PWR_PRIVCFGR_PRIV2_Msk          (0x1UL << PWR_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define PWR_PRIVCFGR_PRIV2              PWR_PRIVCFGR_PRIV2_Msk                  /*!< VDDCORE monitor privileged protection */
+#define PWR_PRIVCFGR_PRIV3_Pos          (3U)
+#define PWR_PRIVCFGR_PRIV3_Msk          (0x1UL << PWR_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define PWR_PRIVCFGR_PRIV3              PWR_PRIVCFGR_PRIV3_Msk                  /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */
+#define PWR_PRIVCFGR_PRIV4_Pos          (4U)
+#define PWR_PRIVCFGR_PRIV4_Msk          (0x1UL << PWR_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define PWR_PRIVCFGR_PRIV4              PWR_PRIVCFGR_PRIV4_Msk                  /*!< Voltage scaling selection privileged protection */
+#define PWR_PRIVCFGR_PRIV5_Pos          (5U)
+#define PWR_PRIVCFGR_PRIV5_Msk          (0x1UL << PWR_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define PWR_PRIVCFGR_PRIV5              PWR_PRIVCFGR_PRIV5_Msk                  /*!< Backup domain privileged protection */
+#define PWR_PRIVCFGR_PRIV6_Pos          (6U)
+#define PWR_PRIVCFGR_PRIV6_Msk          (0x1UL << PWR_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define PWR_PRIVCFGR_PRIV6              PWR_PRIVCFGR_PRIV6_Msk                  /*!< CPU power control privileged protection */
+#define PWR_PRIVCFGR_PRIV7_Pos          (7U)
+#define PWR_PRIVCFGR_PRIV7_Msk          (0x1UL << PWR_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define PWR_PRIVCFGR_PRIV7              PWR_PRIVCFGR_PRIV7_Msk                  /*!< Peripheral voltage monitor privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV1_Pos      (16U)
+#define PWR_PRIVCFGR_WKUPPRIV1_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos)   /*!< 0x00010000 */
+#define PWR_PRIVCFGR_WKUPPRIV1          PWR_PRIVCFGR_WKUPPRIV1_Msk              /*!< WKUP1 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV2_Pos      (17U)
+#define PWR_PRIVCFGR_WKUPPRIV2_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos)   /*!< 0x00020000 */
+#define PWR_PRIVCFGR_WKUPPRIV2          PWR_PRIVCFGR_WKUPPRIV2_Msk              /*!< WKUP2 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV3_Pos      (18U)
+#define PWR_PRIVCFGR_WKUPPRIV3_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos)   /*!< 0x00040000 */
+#define PWR_PRIVCFGR_WKUPPRIV3          PWR_PRIVCFGR_WKUPPRIV3_Msk              /*!< WKUP3 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV4_Pos      (19U)
+#define PWR_PRIVCFGR_WKUPPRIV4_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos)   /*!< 0x00080000 */
+#define PWR_PRIVCFGR_WKUPPRIV4          PWR_PRIVCFGR_WKUPPRIV4_Msk              /*!< WKUP4 privileged protection */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       RAMs configuration controller                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RAMCFG_CR register  ******************/
+#define RAMCFG_CR_ECCE_Pos              (0U)
+#define RAMCFG_CR_ECCE_Msk              (0x1UL << RAMCFG_CR_ECCE_Pos)          /*!< 0x00000001 */
+#define RAMCFG_CR_ECCE                  RAMCFG_CR_ECCE_Msk                     /*!< ECC Enable */
+#define RAMCFG_CR_ALE_Pos               (4U)
+#define RAMCFG_CR_ALE_Msk               (0x1UL << RAMCFG_CR_ALE_Pos)           /*!< 0x00000010 */
+#define RAMCFG_CR_ALE                   RAMCFG_CR_ALE_Msk                      /*!< Address Latching Enable */
+#define RAMCFG_CR_SRAMER_Pos            (8U)
+#define RAMCFG_CR_SRAMER_Msk            (0x1UL << RAMCFG_CR_SRAMER_Pos)        /*!< 0x00000100 */
+#define RAMCFG_CR_SRAMER                RAMCFG_CR_SRAMER_Msk                   /*!< Start Erase */
+#define RAMCFG_CR_SRAMHWERDIS_Pos       (12U)
+#define RAMCFG_CR_SRAMHWERDIS_Msk       (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos)   /*!< 0x00001000 */
+#define RAMCFG_CR_SRAMHWERDIS           RAMCFG_CR_SRAMHWERDIS_Msk              /*!< SRAM hardware erase disable */
+#define RAMCFG_CR_ITCMCFG_Pos           (16U)
+#define RAMCFG_CR_ITCMCFG_Msk           (0x3UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00030000 */
+#define RAMCFG_CR_ITCMCFG               RAMCFG_CR_ITCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+#define RAMCFG_CR_ITCMCFG_0             (0x1UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00010000 */
+#define RAMCFG_CR_ITCMCFG_1             (0x2UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00020000 */
+#define RAMCFG_CR_SRAMSD_Pos            (20U)
+#define RAMCFG_CR_SRAMSD_Msk            (0x1UL << RAMCFG_CR_SRAMSD_Pos)        /*!< 0x00100000 */
+#define RAMCFG_CR_SRAMSD                RAMCFG_CR_SRAMSD_Msk                   /*!< Shutdown AXISRAMx */
+#define RAMCFG_CR_DTCMCFG_Pos           (24U)
+#define RAMCFG_CR_DTCMCFG_Msk           (0x1UL << RAMCFG_CR_DTCMCFG_Pos)       /*!< 0x01000000 */
+#define RAMCFG_CR_DTCMCFG               RAMCFG_CR_DTCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+
+/*******************  Bit definition for RAMCFG_IER register  *****************/
+#define RAMCFG_IER_SEIE_Pos             (0U)
+#define RAMCFG_IER_SEIE_Msk             (0x1UL << RAMCFG_IER_SEIE_Pos)         /*!< 0x00000001 */
+#define RAMCFG_IER_SEIE                 RAMCFG_IER_SEIE_Msk                    /*!< Single Error Interrupt Enable */
+#define RAMCFG_IER_DEIE_Pos             (1U)
+#define RAMCFG_IER_DEIE_Msk             (0x1UL << RAMCFG_IER_DEIE_Pos)         /*!< 0x00000002 */
+#define RAMCFG_IER_DEIE                 RAMCFG_IER_DEIE_Msk                    /*!< Double Error Interrupt Enable */
+
+/*******************  Bit definition for RAMCFG_ISR register  *****************/
+#define RAMCFG_ISR_SEDC_Pos             (0U)
+#define RAMCFG_ISR_SEDC_Msk             (0x1UL << RAMCFG_ISR_SEDC_Pos)         /*!< 0x00000001 */
+#define RAMCFG_ISR_SEDC                 RAMCFG_ISR_SEDC_Msk                    /*!< Single Error Detected and Corrected flag */
+#define RAMCFG_ISR_DED_Pos              (1U)
+#define RAMCFG_ISR_DED_Msk              (0x1UL << RAMCFG_ISR_DED_Pos)          /*!< 0x00000002 */
+#define RAMCFG_ISR_DED                  RAMCFG_ISR_DED_Msk                     /*!< Double Error Detected flag */
+#define RAMCFG_ISR_SRAMBUSY_Pos         (8U)
+#define RAMCFG_ISR_SRAMBUSY_Msk         (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)     /*!< 0x00000100 */
+#define RAMCFG_ISR_SRAMBUSY             RAMCFG_ISR_SRAMBUSY_Msk                /*!< SRAM busy flag */
+
+/*******************  Bit definition for RAMCFG_ESEAR register  ****************/
+#define RAMCFG_ESEAR_ESEA_Pos           (0U)
+#define RAMCFG_ESEAR_ESEA_Msk           (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_ESEAR_ESEA               RAMCFG_ESEAR_ESEA_Msk                  /*!< ECC Single Error Address */
+
+/*******************  Bit definition for RAMCFG_EDEAR register  ****************/
+#define RAMCFG_EDEAR_EDEA_Pos           (0U)
+#define RAMCFG_EDEAR_EDEA_Msk           (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_EDEAR_EDEA               RAMCFG_EDEAR_EDEA_Msk                  /*!< ECC Double Error Address */
+
+/*******************  Bit definition for RAMCFG_ICR register  *****************/
+#define RAMCFG_ICR_CSEDC_Pos            (0U)
+#define RAMCFG_ICR_CSEDC_Msk            (0x1UL << RAMCFG_ICR_CSEDC_Pos)        /*!< 0x00000001 */
+#define RAMCFG_ICR_CSEDC                RAMCFG_ICR_CSEDC_Msk                   /*!< Clear ECC Single Error Detected and Corrected Flag */
+#define RAMCFG_ICR_CDED_Pos             (1U)
+#define RAMCFG_ICR_CDED_Msk             (0x1UL << RAMCFG_ICR_CDED_Pos)         /*!< 0x00000002 */
+#define RAMCFG_ICR_CDED                 RAMCFG_ICR_CDED_Msk                    /*!< Clear ECC Double Error Detected Flag*/
+
+/*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
+#define RAMCFG_ECCKEYR_ECCKEY_Pos       (0U)
+#define RAMCFG_ECCKEYR_ECCKEY_Msk       (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)  /*!< 0x000000FF */
+#define RAMCFG_ECCKEYR_ECCKEY           RAMCFG_ECCKEYR_ECCKEY_Msk              /*!< ECC Write Protection Key */
+
+/*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
+#define RAMCFG_ERKEYR_ERASEKEY_Pos      (0U)
+#define RAMCFG_ERKEYR_ERASEKEY_Msk      (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */
+#define RAMCFG_ERKEYR_ERASEKEY          RAMCFG_ERKEYR_ERASEKEY_Msk             /*!< Erase Write Protection Key */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (RCC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_LSION_Pos                        (0U)
+#define RCC_CR_LSION_Msk                        (0x1UL << RCC_CR_LSION_Pos)           /*!< 0x00000001 */
+#define RCC_CR_LSION                            RCC_CR_LSION_Msk                     /*!< LSI oscillator enable */
+#define RCC_CR_LSEON_Pos                        (1U)
+#define RCC_CR_LSEON_Msk                        (0x1UL << RCC_CR_LSEON_Pos)           /*!< 0x00000002 */
+#define RCC_CR_LSEON                            RCC_CR_LSEON_Msk                     /*!< LSE oscillator enable */
+#define RCC_CR_MSION_Pos                        (2U)
+#define RCC_CR_MSION_Msk                        (0x1UL << RCC_CR_MSION_Pos)           /*!< 0x00000004 */
+#define RCC_CR_MSION                            RCC_CR_MSION_Msk                     /*!< MSI oscillator enable */
+#define RCC_CR_HSION_Pos                        (3U)
+#define RCC_CR_HSION_Msk                        (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000008 */
+#define RCC_CR_HSION                            RCC_CR_HSION_Msk                     /*!< HSI oscillator enable */
+#define RCC_CR_HSEON_Pos                        (4U)
+#define RCC_CR_HSEON_Msk                        (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00000010 */
+#define RCC_CR_HSEON                            RCC_CR_HSEON_Msk                     /*!< HSE oscillator enable */
+#define RCC_CR_PLL1ON_Pos                       (8U)
+#define RCC_CR_PLL1ON_Msk                       (0x1UL << RCC_CR_PLL1ON_Pos)          /*!< 0x00000100 */
+#define RCC_CR_PLL1ON                           RCC_CR_PLL1ON_Msk                    /*!< PLL1 enable */
+#define RCC_CR_PLL2ON_Pos                       (9U)
+#define RCC_CR_PLL2ON_Msk                       (0x1UL << RCC_CR_PLL2ON_Pos)          /*!< 0x00000200 */
+#define RCC_CR_PLL2ON                           RCC_CR_PLL2ON_Msk                    /*!< PLL2 enable */
+#define RCC_CR_PLL3ON_Pos                       (10U)
+#define RCC_CR_PLL3ON_Msk                       (0x1UL << RCC_CR_PLL3ON_Pos)          /*!< 0x00000400 */
+#define RCC_CR_PLL3ON                           RCC_CR_PLL3ON_Msk                    /*!< PLL3 enable */
+#define RCC_CR_PLL4ON_Pos                       (11U)
+#define RCC_CR_PLL4ON_Msk                       (0x1UL << RCC_CR_PLL4ON_Pos)          /*!< 0x00000800 */
+#define RCC_CR_PLL4ON                           RCC_CR_PLL4ON_Msk                    /*!< PLL4 enable */
+
+/********************  Bit definition for RCC_SR register  ********************/
+#define RCC_SR_LSIRDY_Pos                       (0U)
+#define RCC_SR_LSIRDY_Msk                       (0x1UL << RCC_SR_LSIRDY_Pos)          /*!< 0x00000001 */
+#define RCC_SR_LSIRDY                           RCC_SR_LSIRDY_Msk                    /*!< LSI clock ready flag */
+#define RCC_SR_LSERDY_Pos                       (1U)
+#define RCC_SR_LSERDY_Msk                       (0x1UL << RCC_SR_LSERDY_Pos)          /*!< 0x00000002 */
+#define RCC_SR_LSERDY                           RCC_SR_LSERDY_Msk                    /*!< LSE clock ready flag */
+#define RCC_SR_MSIRDY_Pos                       (2U)
+#define RCC_SR_MSIRDY_Msk                       (0x1UL << RCC_SR_MSIRDY_Pos)          /*!< 0x00000004 */
+#define RCC_SR_MSIRDY                           RCC_SR_MSIRDY_Msk                    /*!< MSI clock ready flag */
+#define RCC_SR_HSIRDY_Pos                       (3U)
+#define RCC_SR_HSIRDY_Msk                       (0x1UL << RCC_SR_HSIRDY_Pos)          /*!< 0x00000008 */
+#define RCC_SR_HSIRDY                           RCC_SR_HSIRDY_Msk                    /*!< HSI clock ready flag */
+#define RCC_SR_HSERDY_Pos                       (4U)
+#define RCC_SR_HSERDY_Msk                       (0x1UL << RCC_SR_HSERDY_Pos)          /*!< 0x00000010 */
+#define RCC_SR_HSERDY                           RCC_SR_HSERDY_Msk                    /*!< HSE clock ready flag */
+#define RCC_SR_PLL1RDY_Pos                      (8U)
+#define RCC_SR_PLL1RDY_Msk                      (0x1UL << RCC_SR_PLL1RDY_Pos)         /*!< 0x00000100 */
+#define RCC_SR_PLL1RDY                          RCC_SR_PLL1RDY_Msk                   /*!< PLL1 clock ready flag */
+#define RCC_SR_PLL2RDY_Pos                      (9U)
+#define RCC_SR_PLL2RDY_Msk                      (0x1UL << RCC_SR_PLL2RDY_Pos)         /*!< 0x00000200 */
+#define RCC_SR_PLL2RDY                          RCC_SR_PLL2RDY_Msk                   /*!< PLL2 clock ready flag */
+#define RCC_SR_PLL3RDY_Pos                      (10U)
+#define RCC_SR_PLL3RDY_Msk                      (0x1UL << RCC_SR_PLL3RDY_Pos)         /*!< 0x00000400 */
+#define RCC_SR_PLL3RDY                          RCC_SR_PLL3RDY_Msk                   /*!< PLL3 clock ready flag */
+#define RCC_SR_PLL4RDY_Pos                      (11U)
+#define RCC_SR_PLL4RDY_Msk                      (0x1UL << RCC_SR_PLL4RDY_Pos)         /*!< 0x00000800 */
+#define RCC_SR_PLL4RDY                          RCC_SR_PLL4RDY_Msk                   /*!< PLL4 clock ready flag */
+
+/******************  Bit definition for RCC_STOPCR register  ******************/
+#define RCC_STOPCR_MSISTOPEN_Pos                (0U)
+#define RCC_STOPCR_MSISTOPEN_Msk                (0x1UL << RCC_STOPCR_MSISTOPEN_Pos)   /*!< 0x00000001 */
+#define RCC_STOPCR_MSISTOPEN                    RCC_STOPCR_MSISTOPEN_Msk             /*!< MSI oscillator enable */
+#define RCC_STOPCR_HSISTOPEN_Pos                (1U)
+#define RCC_STOPCR_HSISTOPEN_Msk                (0x1UL << RCC_STOPCR_HSISTOPEN_Pos)   /*!< 0x00000002 */
+#define RCC_STOPCR_HSISTOPEN                    RCC_STOPCR_HSISTOPEN_Msk             /*!< HSI oscillator enable */
+
+/******************  Bit definition for RCC_CFGR1 register  *******************/
+#define RCC_CFGR1_STOPWUCK_Pos                  (0U)
+#define RCC_CFGR1_STOPWUCK_Msk                  (0x1UL << RCC_CFGR1_STOPWUCK_Pos)     /*!< 0x00000001 */
+#define RCC_CFGR1_STOPWUCK                      RCC_CFGR1_STOPWUCK_Msk               /*!< System clock selection after a wake up from system stop */
+#define RCC_CFGR1_CPUSW_Pos                     (16U)
+#define RCC_CFGR1_CPUSW_Msk                     (0x3UL << RCC_CFGR1_CPUSW_Pos)        /*!< 0x00030000 */
+#define RCC_CFGR1_CPUSW                         RCC_CFGR1_CPUSW_Msk                  /*!< CPU clock switch selection */
+#define RCC_CFGR1_CPUSW_0                       (0x1UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR1_CPUSW_1                       (0x2UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR1_CPUSWS_Pos                    (20U)
+#define RCC_CFGR1_CPUSWS_Msk                    (0x3UL << RCC_CFGR1_CPUSWS_Pos)       /*!< 0x00300000 */
+#define RCC_CFGR1_CPUSWS                        RCC_CFGR1_CPUSWS_Msk                 /*!< CPU clock switch status */
+#define RCC_CFGR1_CPUSWS_0                      (0x1UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00100000 */
+#define RCC_CFGR1_CPUSWS_1                      (0x2UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00200000 */
+#define RCC_CFGR1_SYSSW_Pos                     (24U)
+#define RCC_CFGR1_SYSSW_Msk                     (0x3UL << RCC_CFGR1_SYSSW_Pos)        /*!< 0x03000000 */
+#define RCC_CFGR1_SYSSW                         RCC_CFGR1_SYSSW_Msk                  /*!< System clock switch selection */
+#define RCC_CFGR1_SYSSW_0                       (0x1UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x01000000 */
+#define RCC_CFGR1_SYSSW_1                       (0x2UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x02000000 */
+#define RCC_CFGR1_SYSSWS_Pos                    (28U)
+#define RCC_CFGR1_SYSSWS_Msk                    (0x3UL << RCC_CFGR1_SYSSWS_Pos)       /*!< 0x30000000 */
+#define RCC_CFGR1_SYSSWS                        RCC_CFGR1_SYSSWS_Msk                 /*!< System clock switch status */
+#define RCC_CFGR1_SYSSWS_0                      (0x1UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR1_SYSSWS_1                      (0x2UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x20000000 */
+
+/******************  Bit definition for RCC_CFGR2 register  *******************/
+#define RCC_CFGR2_PPRE1_Pos                     (0U)
+#define RCC_CFGR2_PPRE1_Msk                     (0x7UL << RCC_CFGR2_PPRE1_Pos)        /*!< 0x00000007 */
+#define RCC_CFGR2_PPRE1                         RCC_CFGR2_PPRE1_Msk                  /*!< CPU domain APB1 prescaler */
+#define RCC_CFGR2_PPRE1_0                       (0x1UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000001 */
+#define RCC_CFGR2_PPRE1_1                       (0x2UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000002 */
+#define RCC_CFGR2_PPRE1_2                       (0x4UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000004 */
+#define RCC_CFGR2_PPRE2_Pos                     (4U)
+#define RCC_CFGR2_PPRE2_Msk                     (0x7UL << RCC_CFGR2_PPRE2_Pos)        /*!< 0x00000070 */
+#define RCC_CFGR2_PPRE2                         RCC_CFGR2_PPRE2_Msk                  /*!< CPU domain APB2 prescaler */
+#define RCC_CFGR2_PPRE2_0                       (0x1UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR2_PPRE2_1                       (0x2UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR2_PPRE2_2                       (0x4UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR2_PPRE4_Pos                     (12U)
+#define RCC_CFGR2_PPRE4_Msk                     (0x7UL << RCC_CFGR2_PPRE4_Pos)        /*!< 0x00007000 */
+#define RCC_CFGR2_PPRE4                         RCC_CFGR2_PPRE4_Msk                  /*!< CPU domain APB4 prescaler */
+#define RCC_CFGR2_PPRE4_0                       (0x1UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR2_PPRE4_1                       (0x2UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00002000 */
+#define RCC_CFGR2_PPRE4_2                       (0x4UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00004000 */
+#define RCC_CFGR2_PPRE5_Pos                     (16U)
+#define RCC_CFGR2_PPRE5_Msk                     (0x7UL << RCC_CFGR2_PPRE5_Pos)        /*!< 0x00070000 */
+#define RCC_CFGR2_PPRE5                         RCC_CFGR2_PPRE5_Msk                  /*!< CPU domain APB5 prescaler */
+#define RCC_CFGR2_PPRE5_0                       (0x1UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR2_PPRE5_1                       (0x2UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR2_PPRE5_2                       (0x4UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00040000 */
+#define RCC_CFGR2_HPRE_Pos                      (20U)
+#define RCC_CFGR2_HPRE_Msk                      (0x7UL << RCC_CFGR2_HPRE_Pos)         /*!< 0x00700000 */
+#define RCC_CFGR2_HPRE                          RCC_CFGR2_HPRE_Msk                   /*!< AHB clock prescaler */
+#define RCC_CFGR2_HPRE_0                        (0x1UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00100000 */
+#define RCC_CFGR2_HPRE_1                        (0x2UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00200000 */
+#define RCC_CFGR2_HPRE_2                        (0x4UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00400000 */
+#define RCC_CFGR2_TIMPRE_Pos                    (24U)
+#define RCC_CFGR2_TIMPRE_Msk                    (0x3UL << RCC_CFGR2_TIMPRE_Pos)       /*!< 0x03000000 */
+#define RCC_CFGR2_TIMPRE                        RCC_CFGR2_TIMPRE_Msk                 /*!< Timer clock prescaler selection */
+#define RCC_CFGR2_TIMPRE_0                      (0x1UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR2_TIMPRE_1                      (0x2UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x02000000 */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define RCC_BDCR_VSWRST_Pos                     (31U)
+#define RCC_BDCR_VSWRST_Msk                     (0x1UL << RCC_BDCR_VSWRST_Pos)       /*!< 0x80000000 */
+#define RCC_BDCR_VSWRST                         RCC_BDCR_VSWRST_Msk                  /*!< Vswitch (VSW) domain software reset */
+
+/******************  Bit definition for RCC_HWRSR register  *******************/
+#define RCC_HWRSR_RMVF_Pos                      (16U)
+#define RCC_HWRSR_RMVF_Msk                      (0x1UL << RCC_HWRSR_RMVF_Pos)         /*!< 0x00010000 */
+#define RCC_HWRSR_RMVF                          RCC_HWRSR_RMVF_Msk                   /*!< Remove reset flag */
+#define RCC_HWRSR_LCKRSTF_Pos                   (17U)
+#define RCC_HWRSR_LCKRSTF_Msk                   (0x1UL << RCC_HWRSR_LCKRSTF_Pos)      /*!< 0x00020000 */
+#define RCC_HWRSR_LCKRSTF                       RCC_HWRSR_LCKRSTF_Msk                /*!< CPU lockup reset flag */
+#define RCC_HWRSR_BORRSTF_Pos                   (21U)
+#define RCC_HWRSR_BORRSTF_Msk                   (0x1UL << RCC_HWRSR_BORRSTF_Pos)      /*!< 0x00200000 */
+#define RCC_HWRSR_BORRSTF                       RCC_HWRSR_BORRSTF_Msk                /*!< BOR reset flag */
+#define RCC_HWRSR_PINRSTF_Pos                   (22U)
+#define RCC_HWRSR_PINRSTF_Msk                   (0x1UL << RCC_HWRSR_PINRSTF_Pos)      /*!< 0x00400000 */
+#define RCC_HWRSR_PINRSTF                       RCC_HWRSR_PINRSTF_Msk                /*!< Pin reset flag (NRST)  */
+#define RCC_HWRSR_PORRSTF_Pos                   (23U)
+#define RCC_HWRSR_PORRSTF_Msk                   (0x1UL << RCC_HWRSR_PORRSTF_Pos)      /*!< 0x00800000 */
+#define RCC_HWRSR_PORRSTF                       RCC_HWRSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
+#define RCC_HWRSR_SFTRSTF_Pos                   (24U)
+#define RCC_HWRSR_SFTRSTF_Msk                   (0x1UL << RCC_HWRSR_SFTRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_HWRSR_SFTRSTF                       RCC_HWRSR_SFTRSTF_Msk                /*!< Software system reset flag  */
+#define RCC_HWRSR_IWDGRSTF_Pos                  (26U)
+#define RCC_HWRSR_IWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_IWDGRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_HWRSR_IWDGRSTF                      RCC_HWRSR_IWDGRSTF_Msk               /*!< Independent watchdog reset flag */
+#define RCC_HWRSR_WWDGRSTF_Pos                  (28U)
+#define RCC_HWRSR_WWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_WWDGRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_HWRSR_WWDGRSTF                      RCC_HWRSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
+#define RCC_HWRSR_LPWRRSTF_Pos                  (30U)
+#define RCC_HWRSR_LPWRRSTF_Msk                  (0x1UL << RCC_HWRSR_LPWRRSTF_Pos)     /*!< 0x40000000 */
+#define RCC_HWRSR_LPWRRSTF                      RCC_HWRSR_LPWRRSTF_Msk               /*!< Illegal Stop or Standby flag */
+
+/*******************  Bit definition for RCC_RSR register  ********************/
+#define RCC_RSR_RMVF_Pos                        (16U)
+#define RCC_RSR_RMVF_Msk                        (0x1UL << RCC_RSR_RMVF_Pos)           /*!< 0x00010000 */
+#define RCC_RSR_RMVF                            RCC_RSR_RMVF_Msk                     /*!< Remove reset flag */
+#define RCC_RSR_LCKRSTF_Pos                     (17U)
+#define RCC_RSR_LCKRSTF_Msk                     (0x1UL << RCC_RSR_LCKRSTF_Pos)        /*!< 0x00020000 */
+#define RCC_RSR_LCKRSTF                         RCC_RSR_LCKRSTF_Msk                  /*!< CPU lockup reset flag */
+#define RCC_RSR_BORRSTF_Pos                     (21U)
+#define RCC_RSR_BORRSTF_Msk                     (0x1UL << RCC_RSR_BORRSTF_Pos)        /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                         RCC_RSR_BORRSTF_Msk                  /*!< BOR reset flag */
+#define RCC_RSR_PINRSTF_Pos                     (22U)
+#define RCC_RSR_PINRSTF_Msk                     (0x1UL << RCC_RSR_PINRSTF_Pos)        /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                         RCC_RSR_PINRSTF_Msk                  /*!< Pin reset flag (NRST)  */
+#define RCC_RSR_PORRSTF_Pos                     (23U)
+#define RCC_RSR_PORRSTF_Msk                     (0x1UL << RCC_RSR_PORRSTF_Pos)        /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                         RCC_RSR_PORRSTF_Msk                  /*!< POR/PDR reset flag */
+#define RCC_RSR_SFTRSTF_Pos                     (24U)
+#define RCC_RSR_SFTRSTF_Msk                     (0x1UL << RCC_RSR_SFTRSTF_Pos)        /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                         RCC_RSR_SFTRSTF_Msk                  /*!< Software system reset flag  */
+#define RCC_RSR_IWDGRSTF_Pos                    (26U)
+#define RCC_RSR_IWDGRSTF_Msk                    (0x1UL << RCC_RSR_IWDGRSTF_Pos)       /*!< 0x04000000 */
+#define RCC_RSR_IWDGRSTF                        RCC_RSR_IWDGRSTF_Msk                 /*!< Independent watchdog reset flag */
+#define RCC_RSR_WWDGRSTF_Pos                    (28U)
+#define RCC_RSR_WWDGRSTF_Msk                    (0x1UL << RCC_RSR_WWDGRSTF_Pos)       /*!< 0x10000000 */
+#define RCC_RSR_WWDGRSTF                        RCC_RSR_WWDGRSTF_Msk                 /*!< Window watchdog reset flag */
+#define RCC_RSR_LPWRRSTF_Pos                    (30U)
+#define RCC_RSR_LPWRRSTF_Msk                    (0x1UL << RCC_RSR_LPWRRSTF_Pos)       /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                        RCC_RSR_LPWRRSTF_Msk                 /*!< Illegal Stop or Standby flag */
+
+/*****************  Bit definition for RCC_LSECFGR register  ******************/
+#define RCC_LSECFGR_LSECSSON_Pos                (7U)
+#define RCC_LSECFGR_LSECSSON_Msk                (0x1UL << RCC_LSECFGR_LSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_LSECFGR_LSECSSON                    RCC_LSECFGR_LSECSSON_Msk             /*!< LSE clock security system (CSS) enable */
+#define RCC_LSECFGR_LSECSSRA_Pos                (8U)
+#define RCC_LSECFGR_LSECSSRA_Msk                (0x1UL << RCC_LSECFGR_LSECSSRA_Pos)   /*!< 0x00000100 */
+#define RCC_LSECFGR_LSECSSRA                    RCC_LSECFGR_LSECSSRA_Msk             /*!< LSE clock security system (CSS) rearm function */
+#define RCC_LSECFGR_LSECSSD_Pos                 (9U)
+#define RCC_LSECFGR_LSECSSD_Msk                 (0x1UL << RCC_LSECFGR_LSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_LSECFGR_LSECSSD                     RCC_LSECFGR_LSECSSD_Msk              /*!< LSE clock security system (CSS) failure detection */
+#define RCC_LSECFGR_LSEBYP_Pos                  (15U)
+#define RCC_LSECFGR_LSEBYP_Msk                  (0x1UL << RCC_LSECFGR_LSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_LSECFGR_LSEBYP                      RCC_LSECFGR_LSEBYP_Msk               /*!< LSE clock bypass */
+#define RCC_LSECFGR_LSEEXT_Pos                  (16U)
+#define RCC_LSECFGR_LSEEXT_Msk                  (0x1UL << RCC_LSECFGR_LSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_LSECFGR_LSEEXT                      RCC_LSECFGR_LSEEXT_Msk               /*!< LSE clock type in bypass mode */
+#define RCC_LSECFGR_LSEGFON_Pos                 (17U)
+#define RCC_LSECFGR_LSEGFON_Msk                 (0x1UL << RCC_LSECFGR_LSEGFON_Pos)    /*!< 0x00020000 */
+#define RCC_LSECFGR_LSEGFON                     RCC_LSECFGR_LSEGFON_Msk              /*!< LSE clock glitch filter enable */
+#define RCC_LSECFGR_LSEDRV_Pos                  (18U)
+#define RCC_LSECFGR_LSEDRV_Msk                  (0x3UL << RCC_LSECFGR_LSEDRV_Pos)     /*!< 0x000C0000 */
+#define RCC_LSECFGR_LSEDRV                      RCC_LSECFGR_LSEDRV_Msk               /*!< LSE oscillator driving capability */
+#define RCC_LSECFGR_LSEDRV_0                    (0x1UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00040000 */
+#define RCC_LSECFGR_LSEDRV_1                    (0x2UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for RCC_MSICFGR register  ******************/
+#define RCC_MSICFGR_MSIFREQSEL_Pos              (9U)
+#define RCC_MSICFGR_MSIFREQSEL_Msk              (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */
+#define RCC_MSICFGR_MSIFREQSEL                  RCC_MSICFGR_MSIFREQSEL_Msk           /*!< MSI oscillator frequency selection */
+#define RCC_MSICFGR_MSITRIM_Pos                 (16U)
+#define RCC_MSICFGR_MSITRIM_Msk                 (0x1FUL << RCC_MSICFGR_MSITRIM_Pos)   /*!< 0x001F0000 */
+#define RCC_MSICFGR_MSITRIM                     RCC_MSICFGR_MSITRIM_Msk              /*!< MSI clock trimming */
+#define RCC_MSICFGR_MSICAL_Pos                  (23U)
+#define RCC_MSICFGR_MSICAL_Msk                  (0xFFUL << RCC_MSICFGR_MSICAL_Pos)    /*!< 0x7F800000 */
+#define RCC_MSICFGR_MSICAL                      RCC_MSICFGR_MSICAL_Msk               /*!< MSI clock calibration */
+
+/*****************  Bit definition for RCC_HSICFGR register  ******************/
+#define RCC_HSICFGR_HSIDIV_Pos                  (7U)
+#define RCC_HSICFGR_HSIDIV_Msk                  (0x3UL << RCC_HSICFGR_HSIDIV_Pos)     /*!< 0x00000180 */
+#define RCC_HSICFGR_HSIDIV                      RCC_HSICFGR_HSIDIV_Msk               /*!< HSI clock divider */
+#define RCC_HSICFGR_HSIDIV_0                    (0x1UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000080 */
+#define RCC_HSICFGR_HSIDIV_1                    (0x2UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000100 */
+#define RCC_HSICFGR_HSITRIM_Pos                 (16U)
+#define RCC_HSICFGR_HSITRIM_Msk                 (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)   /*!< 0x007F0000 */
+#define RCC_HSICFGR_HSITRIM                     RCC_HSICFGR_HSITRIM_Msk              /*!< HSI clock trimming */
+#define RCC_HSICFGR_HSICAL_Pos                  (23U)
+#define RCC_HSICFGR_HSICAL_Msk                  (0x1FFUL << RCC_HSICFGR_HSICAL_Pos)   /*!< 0xFF800000 */
+#define RCC_HSICFGR_HSICAL                      RCC_HSICFGR_HSICAL_Msk               /*!< HSI clock calibration */
+
+/******************  Bit definition for RCC_HSIMCR register  ******************/
+#define RCC_HSIMCR_HSIREF_Pos                   (0U)
+#define RCC_HSIMCR_HSIREF_Msk                   (0x7FFUL << RCC_HSIMCR_HSIREF_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMCR_HSIREF                       RCC_HSIMCR_HSIREF_Msk                /*!< HSI clock-cycle counter reference value */
+#define RCC_HSIMCR_HSIDEV_Pos                   (16U)
+#define RCC_HSIMCR_HSIDEV_Msk                   (0x3FUL << RCC_HSIMCR_HSIDEV_Pos)     /*!< 0x003F0000 */
+#define RCC_HSIMCR_HSIDEV                       RCC_HSIMCR_HSIDEV_Msk                /*!< HSI clock count deviation value */
+#define RCC_HSIMCR_HSIMONEN_Pos                 (31U)
+#define RCC_HSIMCR_HSIMONEN_Msk                 (0x1UL << RCC_HSIMCR_HSIMONEN_Pos)    /*!< 0x80000000 */
+#define RCC_HSIMCR_HSIMONEN                     RCC_HSIMCR_HSIMONEN_Msk              /*!< HSI clock period monitor enable */
+
+/******************  Bit definition for RCC_HSIMSR register  ******************/
+#define RCC_HSIMSR_HSIVAL_Pos                   (0U)
+#define RCC_HSIMSR_HSIVAL_Msk                   (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMSR_HSIVAL                       RCC_HSIMSR_HSIVAL_Msk                /*!< HSI clock-cycle counter measured value */
+
+/*****************  Bit definition for RCC_HSECFGR register  ******************/
+#define RCC_HSECFGR_HSEDIV2SEL_Pos              (6U)
+#define RCC_HSECFGR_HSEDIV2SEL_Msk              (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */
+#define RCC_HSECFGR_HSEDIV2SEL                  RCC_HSECFGR_HSEDIV2SEL_Msk           /*!< HSE div2 clock source select */
+#define RCC_HSECFGR_HSECSSON_Pos                (7U)
+#define RCC_HSECFGR_HSECSSON_Msk                (0x1UL << RCC_HSECFGR_HSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_HSECFGR_HSECSSON                    RCC_HSECFGR_HSECSSON_Msk             /*!< HSE CSS enable */
+#define RCC_HSECFGR_HSECSSD_Pos                 (9U)
+#define RCC_HSECFGR_HSECSSD_Msk                 (0x1UL << RCC_HSECFGR_HSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_HSECFGR_HSECSSD                     RCC_HSECFGR_HSECSSD_Msk              /*!< HSE CSS failure detection */
+#define RCC_HSECFGR_HSECSSBYP_Pos               (10U)
+#define RCC_HSECFGR_HSECSSBYP_Msk               (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos)  /*!< 0x00000400 */
+#define RCC_HSECFGR_HSECSSBYP                   RCC_HSECFGR_HSECSSBYP_Msk            /*!< HSE CSS bypass enable */
+#define RCC_HSECFGR_HSECSSBPRE_Pos              (11U)
+#define RCC_HSECFGR_HSECSSBPRE_Msk              (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */
+#define RCC_HSECFGR_HSECSSBPRE                  RCC_HSECFGR_HSECSSBPRE_Msk           /*!< HSE CSS bypass divider */
+#define RCC_HSECFGR_HSECSSBPRE_0                (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */
+#define RCC_HSECFGR_HSECSSBPRE_1                (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */
+#define RCC_HSECFGR_HSECSSBPRE_2                (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */
+#define RCC_HSECFGR_HSECSSBPRE_3                (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */
+#define RCC_HSECFGR_HSEBYP_Pos                  (15U)
+#define RCC_HSECFGR_HSEBYP_Msk                  (0x1UL << RCC_HSECFGR_HSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_HSECFGR_HSEBYP                      RCC_HSECFGR_HSEBYP_Msk               /*!< HSE clock bypass */
+#define RCC_HSECFGR_HSEEXT_Pos                  (16U)
+#define RCC_HSECFGR_HSEEXT_Msk                  (0x1UL << RCC_HSECFGR_HSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_HSECFGR_HSEEXT                      RCC_HSECFGR_HSEEXT_Msk               /*!< HSE clock type in bypass mode */
+
+/****************  Bit definition for RCC_PLL1CFGR1 register  *****************/
+#define RCC_PLL1CFGR1_PLL1DIVN_Pos              (8U)
+#define RCC_PLL1CFGR1_PLL1DIVN_Msk              (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL1CFGR1_PLL1DIVN                  RCC_PLL1CFGR1_PLL1DIVN_Msk           /*!< PLL1 integer part for the VCO multiplication factor */
+#define RCC_PLL1CFGR1_PLL1DIVM_Pos              (20U)
+#define RCC_PLL1CFGR1_PLL1DIVM_Msk              (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL1CFGR1_PLL1DIVM                  RCC_PLL1CFGR1_PLL1DIVM_Msk           /*!< PLL1 reference input clock divide frequency ratio */
+#define RCC_PLL1CFGR1_PLL1BYP_Pos               (27U)
+#define RCC_PLL1CFGR1_PLL1BYP_Msk               (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL1CFGR1_PLL1BYP                   RCC_PLL1CFGR1_PLL1BYP_Msk            /*!< PLL1 bypass */
+#define RCC_PLL1CFGR1_PLL1SEL_Pos               (28U)
+#define RCC_PLL1CFGR1_PLL1SEL_Msk               (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL1CFGR1_PLL1SEL                   RCC_PLL1CFGR1_PLL1SEL_Msk            /*!< PLL1 source selection of the reference clock */
+#define RCC_PLL1CFGR1_PLL1SEL_0                 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_1                 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_2                 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL1CFGR2 register  *****************/
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos          (0U)
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC              RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk       /*!< PLL1 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL1CFGR3 register  *****************/
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos          (0U)
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL1CFGR3_PLL1MODSSRST              RCC_PLL1CFGR3_PLL1MODSSRST_Msk       /*!< PLL1 modulation spread spectrum reset */
+#define RCC_PLL1CFGR3_PLL1DACEN_Pos             (1U)
+#define RCC_PLL1CFGR3_PLL1DACEN_Msk             (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL1CFGR3_PLL1DACEN                 RCC_PLL1CFGR3_PLL1DACEN_Msk          /*!< PLL1 noise canceling DAC enable in fractional mode */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos          (2U)
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS              RCC_PLL1CFGR3_PLL1MODSSDIS_Msk       /*!< PLL1 modulation spread spectrum disable  */
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos           (3U)
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk           (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL1CFGR3_PLL1MODDSEN               RCC_PLL1CFGR3_PLL1MODDSEN_Msk        /*!< PLL1 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos          (4U)
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW              RCC_PLL1CFGR3_PLL1MODSPRDW_Msk       /*!< PLL1 modulation spread spectrum down */
+#define RCC_PLL1CFGR3_PLL1MODDIV_Pos            (8U)
+#define RCC_PLL1CFGR3_PLL1MODDIV_Msk            (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL1CFGR3_PLL1MODDIV                RCC_PLL1CFGR3_PLL1MODDIV_Msk         /*!< PLL1 modulation division frequency adjustment  */
+#define RCC_PLL1CFGR3_PLL1MODSPR_Pos            (16U)
+#define RCC_PLL1CFGR3_PLL1MODSPR_Msk            (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL1CFGR3_PLL1MODSPR                RCC_PLL1CFGR3_PLL1MODSPR_Msk         /*!< PLL1 modulation spread depth adjustment */
+#define RCC_PLL1CFGR3_PLL1PDIV2_Pos             (24U)
+#define RCC_PLL1CFGR3_PLL1PDIV2_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV2                 RCC_PLL1CFGR3_PLL1PDIV2_Msk          /*!< PLL1 VCO frequency divider level 2 */
+#define RCC_PLL1CFGR3_PLL1PDIV1_Pos             (27U)
+#define RCC_PLL1CFGR3_PLL1PDIV1_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV1                 RCC_PLL1CFGR3_PLL1PDIV1_Msk          /*!< PLL1 VCO frequency divider level 1 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos            (30U)
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk            (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN                RCC_PLL1CFGR3_PLL1PDIVEN_Msk         /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL2CFGR1 register  *****************/
+#define RCC_PLL2CFGR1_PLL2DIVN_Pos              (8U)
+#define RCC_PLL2CFGR1_PLL2DIVN_Msk              (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL2CFGR1_PLL2DIVN                  RCC_PLL2CFGR1_PLL2DIVN_Msk           /*!< PLL2 integer part for the VCO multiplication factor */
+#define RCC_PLL2CFGR1_PLL2DIVM_Pos              (20U)
+#define RCC_PLL2CFGR1_PLL2DIVM_Msk              (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL2CFGR1_PLL2DIVM                  RCC_PLL2CFGR1_PLL2DIVM_Msk           /*!< PLL2 reference input clock divide frequency ratio */
+#define RCC_PLL2CFGR1_PLL2BYP_Pos               (27U)
+#define RCC_PLL2CFGR1_PLL2BYP_Msk               (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL2CFGR1_PLL2BYP                   RCC_PLL2CFGR1_PLL2BYP_Msk            /*!< PLL2 bypass */
+#define RCC_PLL2CFGR1_PLL2SEL_Pos               (28U)
+#define RCC_PLL2CFGR1_PLL2SEL_Msk               (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL2CFGR1_PLL2SEL                   RCC_PLL2CFGR1_PLL2SEL_Msk            /*!< PLL2 source selection of the reference clock */
+#define RCC_PLL2CFGR1_PLL2SEL_0                 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_1                 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_2                 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL2CFGR2 register  *****************/
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos          (0U)
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC              RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk       /*!< PLL2 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL2CFGR3 register  *****************/
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos          (0U)
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL2CFGR3_PLL2MODSSRST              RCC_PLL2CFGR3_PLL2MODSSRST_Msk       /*!< PLL2 modulation spread spectrum reset */
+#define RCC_PLL2CFGR3_PLL2DACEN_Pos             (1U)
+#define RCC_PLL2CFGR3_PLL2DACEN_Msk             (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL2CFGR3_PLL2DACEN                 RCC_PLL2CFGR3_PLL2DACEN_Msk          /*!< PLL2 noise canceling DAC enable in fractional mode */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos          (2U)
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS              RCC_PLL2CFGR3_PLL2MODSSDIS_Msk       /*!< PLL2 modulation spread spectrum disable  */
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos           (3U)
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk           (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL2CFGR3_PLL2MODDSEN               RCC_PLL2CFGR3_PLL2MODDSEN_Msk        /*!< PLL2 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos          (4U)
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW              RCC_PLL2CFGR3_PLL2MODSPRDW_Msk       /*!< PLL2 modulation down spread */
+#define RCC_PLL2CFGR3_PLL2MODDIV_Pos            (8U)
+#define RCC_PLL2CFGR3_PLL2MODDIV_Msk            (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL2CFGR3_PLL2MODDIV                RCC_PLL2CFGR3_PLL2MODDIV_Msk         /*!< PLL2 modulation division frequency adjustment  */
+#define RCC_PLL2CFGR3_PLL2MODSPR_Pos            (16U)
+#define RCC_PLL2CFGR3_PLL2MODSPR_Msk            (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL2CFGR3_PLL2MODSPR                RCC_PLL2CFGR3_PLL2MODSPR_Msk         /*!< PLL2 modulation spread depth adjustment */
+#define RCC_PLL2CFGR3_PLL2PDIV2_Pos             (24U)
+#define RCC_PLL2CFGR3_PLL2PDIV2_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV2                 RCC_PLL2CFGR3_PLL2PDIV2_Msk          /*!< PLL2 VCO frequency divider level 2 */
+#define RCC_PLL2CFGR3_PLL2PDIV1_Pos             (27U)
+#define RCC_PLL2CFGR3_PLL2PDIV1_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV1                 RCC_PLL2CFGR3_PLL2PDIV1_Msk          /*!< PLL2 VCO frequency divider level 1 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos            (30U)
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk            (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN                RCC_PLL2CFGR3_PLL2PDIVEN_Msk         /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL3CFGR1 register  *****************/
+#define RCC_PLL3CFGR1_PLL3DIVN_Pos              (8U)
+#define RCC_PLL3CFGR1_PLL3DIVN_Msk              (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL3CFGR1_PLL3DIVN                  RCC_PLL3CFGR1_PLL3DIVN_Msk           /*!< PLL3 Integer part for the VCO multiplication factor */
+#define RCC_PLL3CFGR1_PLL3DIVM_Pos              (20U)
+#define RCC_PLL3CFGR1_PLL3DIVM_Msk              (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL3CFGR1_PLL3DIVM                  RCC_PLL3CFGR1_PLL3DIVM_Msk           /*!< PLL3 reference input clock divide frequency ratio */
+#define RCC_PLL3CFGR1_PLL3BYP_Pos               (27U)
+#define RCC_PLL3CFGR1_PLL3BYP_Msk               (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL3CFGR1_PLL3BYP                   RCC_PLL3CFGR1_PLL3BYP_Msk            /*!< PLL3 bypass */
+#define RCC_PLL3CFGR1_PLL3SEL_Pos               (28U)
+#define RCC_PLL3CFGR1_PLL3SEL_Msk               (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL3CFGR1_PLL3SEL                   RCC_PLL3CFGR1_PLL3SEL_Msk            /*!< PLL3 source selection of the reference clock */
+#define RCC_PLL3CFGR1_PLL3SEL_0                 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_1                 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_2                 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL3CFGR2 register  *****************/
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos          (0U)
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC              RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk       /*!< PLL3 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL3CFGR3 register  *****************/
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos          (0U)
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL3CFGR3_PLL3MODSSRST              RCC_PLL3CFGR3_PLL3MODSSRST_Msk       /*!< PLL3 modulation spread spectrum reset */
+#define RCC_PLL3CFGR3_PLL3DACEN_Pos             (1U)
+#define RCC_PLL3CFGR3_PLL3DACEN_Msk             (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL3CFGR3_PLL3DACEN                 RCC_PLL3CFGR3_PLL3DACEN_Msk          /*!< PLL3 noise canceling DAC enable in fractional mode */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos          (2U)
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS              RCC_PLL3CFGR3_PLL3MODSSDIS_Msk       /*!< PLL3 modulation spread spectrum disable  */
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos           (3U)
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk           (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL3CFGR3_PLL3MODDSEN               RCC_PLL3CFGR3_PLL3MODDSEN_Msk        /*!< PLL3 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos          (4U)
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW              RCC_PLL3CFGR3_PLL3MODSPRDW_Msk       /*!< PLL3 modulation down spread */
+#define RCC_PLL3CFGR3_PLL3MODDIV_Pos            (8U)
+#define RCC_PLL3CFGR3_PLL3MODDIV_Msk            (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL3CFGR3_PLL3MODDIV                RCC_PLL3CFGR3_PLL3MODDIV_Msk         /*!< PLL3 modulation division frequency adjustment  */
+#define RCC_PLL3CFGR3_PLL3MODSPR_Pos            (16U)
+#define RCC_PLL3CFGR3_PLL3MODSPR_Msk            (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL3CFGR3_PLL3MODSPR                RCC_PLL3CFGR3_PLL3MODSPR_Msk         /*!< PLL3 modulation spread depth adjustment */
+#define RCC_PLL3CFGR3_PLL3PDIV2_Pos             (24U)
+#define RCC_PLL3CFGR3_PLL3PDIV2_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV2                 RCC_PLL3CFGR3_PLL3PDIV2_Msk          /*!< PLL3 VCO frequency divider level 2 */
+#define RCC_PLL3CFGR3_PLL3PDIV1_Pos             (27U)
+#define RCC_PLL3CFGR3_PLL3PDIV1_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV1                 RCC_PLL3CFGR3_PLL3PDIV1_Msk          /*!< PLL3 VCO frequency divider level 1 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos            (30U)
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk            (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN                RCC_PLL3CFGR3_PLL3PDIVEN_Msk         /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL4CFGR1 register  *****************/
+#define RCC_PLL4CFGR1_PLL4DIVN_Pos              (8U)
+#define RCC_PLL4CFGR1_PLL4DIVN_Msk              (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL4CFGR1_PLL4DIVN                  RCC_PLL4CFGR1_PLL4DIVN_Msk           /*!< PLL4 integer part for the VCO multiplication factor */
+#define RCC_PLL4CFGR1_PLL4DIVM_Pos              (20U)
+#define RCC_PLL4CFGR1_PLL4DIVM_Msk              (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL4CFGR1_PLL4DIVM                  RCC_PLL4CFGR1_PLL4DIVM_Msk           /*!< PLL4 reference input clock divide frequency ratio */
+#define RCC_PLL4CFGR1_PLL4BYP_Pos               (27U)
+#define RCC_PLL4CFGR1_PLL4BYP_Msk               (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL4CFGR1_PLL4BYP                   RCC_PLL4CFGR1_PLL4BYP_Msk            /*!< PLL4 bypass */
+#define RCC_PLL4CFGR1_PLL4SEL_Pos               (28U)
+#define RCC_PLL4CFGR1_PLL4SEL_Msk               (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL4CFGR1_PLL4SEL                   RCC_PLL4CFGR1_PLL4SEL_Msk            /*!< PLL4 source selection of the reference clock */
+#define RCC_PLL4CFGR1_PLL4SEL_0                 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_1                 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_2                 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL4CFGR2 register  *****************/
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos          (0U)
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC              RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk       /*!< PLL4 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL4CFGR3 register  *****************/
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos          (0U)
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL4CFGR3_PLL4MODSSRST              RCC_PLL4CFGR3_PLL4MODSSRST_Msk       /*!< PLL4 modulation spread spectrum reset */
+#define RCC_PLL4CFGR3_PLL4DACEN_Pos             (1U)
+#define RCC_PLL4CFGR3_PLL4DACEN_Msk             (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL4CFGR3_PLL4DACEN                 RCC_PLL4CFGR3_PLL4DACEN_Msk          /*!< PLL4 noise canceling DAC enable in fractional mode */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos          (2U)
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS              RCC_PLL4CFGR3_PLL4MODSSDIS_Msk       /*!< PLL4 modulation spread spectrum disable  */
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos           (3U)
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk           (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL4CFGR3_PLL4MODDSEN               RCC_PLL4CFGR3_PLL4MODDSEN_Msk        /*!< PLL4 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos          (4U)
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW              RCC_PLL4CFGR3_PLL4MODSPRDW_Msk       /*!< PLL4 modulation down spread */
+#define RCC_PLL4CFGR3_PLL4MODDIV_Pos            (8U)
+#define RCC_PLL4CFGR3_PLL4MODDIV_Msk            (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL4CFGR3_PLL4MODDIV                RCC_PLL4CFGR3_PLL4MODDIV_Msk         /*!< PLL4 modulation division frequency adjustment  */
+#define RCC_PLL4CFGR3_PLL4MODSPR_Pos            (16U)
+#define RCC_PLL4CFGR3_PLL4MODSPR_Msk            (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL4CFGR3_PLL4MODSPR                RCC_PLL4CFGR3_PLL4MODSPR_Msk         /*!< PLL4 modulation spread depth adjustment */
+#define RCC_PLL4CFGR3_PLL4PDIV2_Pos             (24U)
+#define RCC_PLL4CFGR3_PLL4PDIV2_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV2                 RCC_PLL4CFGR3_PLL4PDIV2_Msk          /*!< PLL4 VCO frequency divider level 2 */
+#define RCC_PLL4CFGR3_PLL4PDIV1_Pos             (27U)
+#define RCC_PLL4CFGR3_PLL4PDIV1_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV1                 RCC_PLL4CFGR3_PLL4PDIV1_Msk          /*!< PLL4 VCO frequency divider level 1 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos            (30U)
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk            (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN                RCC_PLL4CFGR3_PLL4PDIVEN_Msk         /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/*****************  Bit definition for RCC_IC1CFGR register  ******************/
+#define RCC_IC1CFGR_IC1INT_Pos                  (16U)
+#define RCC_IC1CFGR_IC1INT_Msk                  (0xFFUL << RCC_IC1CFGR_IC1INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC1CFGR_IC1INT                      RCC_IC1CFGR_IC1INT_Msk               /*!< Divider IC1 integer division factor */
+#define RCC_IC1CFGR_IC1SEL_Pos                  (28U)
+#define RCC_IC1CFGR_IC1SEL_Msk                  (0x3UL << RCC_IC1CFGR_IC1SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC1CFGR_IC1SEL                      RCC_IC1CFGR_IC1SEL_Msk               /*!< Divider IC1 source selection */
+#define RCC_IC1CFGR_IC1SEL_0                    (0x1UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC1CFGR_IC1SEL_1                    (0x2UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC2CFGR register  ******************/
+#define RCC_IC2CFGR_IC2INT_Pos                  (16U)
+#define RCC_IC2CFGR_IC2INT_Msk                  (0xFFUL << RCC_IC2CFGR_IC2INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC2CFGR_IC2INT                      RCC_IC2CFGR_IC2INT_Msk               /*!< Divider IC2 integer division factor */
+#define RCC_IC2CFGR_IC2SEL_Pos                  (28U)
+#define RCC_IC2CFGR_IC2SEL_Msk                  (0x3UL << RCC_IC2CFGR_IC2SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC2CFGR_IC2SEL                      RCC_IC2CFGR_IC2SEL_Msk               /*!< Divider IC2 source selection */
+#define RCC_IC2CFGR_IC2SEL_0                    (0x1UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC2CFGR_IC2SEL_1                    (0x2UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC3CFGR register  ******************/
+#define RCC_IC3CFGR_IC3INT_Pos                  (16U)
+#define RCC_IC3CFGR_IC3INT_Msk                  (0xFFUL << RCC_IC3CFGR_IC3INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC3CFGR_IC3INT                      RCC_IC3CFGR_IC3INT_Msk               /*!< Divider IC3 integer division factor */
+#define RCC_IC3CFGR_IC3SEL_Pos                  (28U)
+#define RCC_IC3CFGR_IC3SEL_Msk                  (0x3UL << RCC_IC3CFGR_IC3SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC3CFGR_IC3SEL                      RCC_IC3CFGR_IC3SEL_Msk               /*!< Divider IC3 source selection */
+#define RCC_IC3CFGR_IC3SEL_0                    (0x1UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC3CFGR_IC3SEL_1                    (0x2UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC4CFGR register  ******************/
+#define RCC_IC4CFGR_IC4INT_Pos                  (16U)
+#define RCC_IC4CFGR_IC4INT_Msk                  (0xFFUL << RCC_IC4CFGR_IC4INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC4CFGR_IC4INT                      RCC_IC4CFGR_IC4INT_Msk               /*!< Divider IC4 integer division factor */
+#define RCC_IC4CFGR_IC4SEL_Pos                  (28U)
+#define RCC_IC4CFGR_IC4SEL_Msk                  (0x3UL << RCC_IC4CFGR_IC4SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC4CFGR_IC4SEL                      RCC_IC4CFGR_IC4SEL_Msk               /*!< Divider IC4 source selection */
+#define RCC_IC4CFGR_IC4SEL_0                    (0x1UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC4CFGR_IC4SEL_1                    (0x2UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC5CFGR register  ******************/
+#define RCC_IC5CFGR_IC5INT_Pos                  (16U)
+#define RCC_IC5CFGR_IC5INT_Msk                  (0xFFUL << RCC_IC5CFGR_IC5INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC5CFGR_IC5INT                      RCC_IC5CFGR_IC5INT_Msk               /*!< Divider IC5 integer division factor */
+#define RCC_IC5CFGR_IC5SEL_Pos                  (28U)
+#define RCC_IC5CFGR_IC5SEL_Msk                  (0x3UL << RCC_IC5CFGR_IC5SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC5CFGR_IC5SEL                      RCC_IC5CFGR_IC5SEL_Msk               /*!< Divider IC5 source selection */
+#define RCC_IC5CFGR_IC5SEL_0                    (0x1UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC5CFGR_IC5SEL_1                    (0x2UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC6CFGR register  ******************/
+#define RCC_IC6CFGR_IC6INT_Pos                  (16U)
+#define RCC_IC6CFGR_IC6INT_Msk                  (0xFFUL << RCC_IC6CFGR_IC6INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC6CFGR_IC6INT                      RCC_IC6CFGR_IC6INT_Msk               /*!< Divider IC6 integer division factor */
+#define RCC_IC6CFGR_IC6SEL_Pos                  (28U)
+#define RCC_IC6CFGR_IC6SEL_Msk                  (0x3UL << RCC_IC6CFGR_IC6SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC6CFGR_IC6SEL                      RCC_IC6CFGR_IC6SEL_Msk               /*!< Divider IC6 source selection */
+#define RCC_IC6CFGR_IC6SEL_0                    (0x1UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC6CFGR_IC6SEL_1                    (0x2UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC7CFGR register  ******************/
+#define RCC_IC7CFGR_IC7INT_Pos                  (16U)
+#define RCC_IC7CFGR_IC7INT_Msk                  (0xFFUL << RCC_IC7CFGR_IC7INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC7CFGR_IC7INT                      RCC_IC7CFGR_IC7INT_Msk               /*!< Divider IC7 integer division factor */
+#define RCC_IC7CFGR_IC7SEL_Pos                  (28U)
+#define RCC_IC7CFGR_IC7SEL_Msk                  (0x3UL << RCC_IC7CFGR_IC7SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC7CFGR_IC7SEL                      RCC_IC7CFGR_IC7SEL_Msk               /*!< Divider IC7 source selection */
+#define RCC_IC7CFGR_IC7SEL_0                    (0x1UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC7CFGR_IC7SEL_1                    (0x2UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC8CFGR register  ******************/
+#define RCC_IC8CFGR_IC8INT_Pos                  (16U)
+#define RCC_IC8CFGR_IC8INT_Msk                  (0xFFUL << RCC_IC8CFGR_IC8INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC8CFGR_IC8INT                      RCC_IC8CFGR_IC8INT_Msk               /*!< Divider IC8 integer division factor */
+#define RCC_IC8CFGR_IC8SEL_Pos                  (28U)
+#define RCC_IC8CFGR_IC8SEL_Msk                  (0x3UL << RCC_IC8CFGR_IC8SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC8CFGR_IC8SEL                      RCC_IC8CFGR_IC8SEL_Msk               /*!< Divider IC8 source selection */
+#define RCC_IC8CFGR_IC8SEL_0                    (0x1UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC8CFGR_IC8SEL_1                    (0x2UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC9CFGR register  ******************/
+#define RCC_IC9CFGR_IC9INT_Pos                  (16U)
+#define RCC_IC9CFGR_IC9INT_Msk                  (0xFFUL << RCC_IC9CFGR_IC9INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC9CFGR_IC9INT                      RCC_IC9CFGR_IC9INT_Msk               /*!< Divider IC9 integer division factor */
+#define RCC_IC9CFGR_IC9SEL_Pos                  (28U)
+#define RCC_IC9CFGR_IC9SEL_Msk                  (0x3UL << RCC_IC9CFGR_IC9SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC9CFGR_IC9SEL                      RCC_IC9CFGR_IC9SEL_Msk               /*!< Divider IC9 source selection */
+#define RCC_IC9CFGR_IC9SEL_0                    (0x1UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC9CFGR_IC9SEL_1                    (0x2UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC10CFGR register  *****************/
+#define RCC_IC10CFGR_IC10INT_Pos                (16U)
+#define RCC_IC10CFGR_IC10INT_Msk                (0xFFUL << RCC_IC10CFGR_IC10INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC10CFGR_IC10INT                    RCC_IC10CFGR_IC10INT_Msk             /*!< Divider IC10 integer division factor */
+#define RCC_IC10CFGR_IC10SEL_Pos                (28U)
+#define RCC_IC10CFGR_IC10SEL_Msk                (0x3UL << RCC_IC10CFGR_IC10SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC10CFGR_IC10SEL                    RCC_IC10CFGR_IC10SEL_Msk             /*!< Divider IC10 source selection */
+#define RCC_IC10CFGR_IC10SEL_0                  (0x1UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC10CFGR_IC10SEL_1                  (0x2UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC11CFGR register  *****************/
+#define RCC_IC11CFGR_IC11INT_Pos                (16U)
+#define RCC_IC11CFGR_IC11INT_Msk                (0xFFUL << RCC_IC11CFGR_IC11INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC11CFGR_IC11INT                    RCC_IC11CFGR_IC11INT_Msk             /*!< Divider IC11 integer division factor */
+#define RCC_IC11CFGR_IC11SEL_Pos                (28U)
+#define RCC_IC11CFGR_IC11SEL_Msk                (0x3UL << RCC_IC11CFGR_IC11SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC11CFGR_IC11SEL                    RCC_IC11CFGR_IC11SEL_Msk             /*!< Divider IC11 source selection */
+#define RCC_IC11CFGR_IC11SEL_0                  (0x1UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC11CFGR_IC11SEL_1                  (0x2UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC12CFGR register  *****************/
+#define RCC_IC12CFGR_IC12INT_Pos                (16U)
+#define RCC_IC12CFGR_IC12INT_Msk                (0xFFUL << RCC_IC12CFGR_IC12INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC12CFGR_IC12INT                    RCC_IC12CFGR_IC12INT_Msk             /*!< Divider IC12 integer division factor */
+#define RCC_IC12CFGR_IC12SEL_Pos                (28U)
+#define RCC_IC12CFGR_IC12SEL_Msk                (0x3UL << RCC_IC12CFGR_IC12SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC12CFGR_IC12SEL                    RCC_IC12CFGR_IC12SEL_Msk             /*!< Divider IC12 source selection */
+#define RCC_IC12CFGR_IC12SEL_0                  (0x1UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC12CFGR_IC12SEL_1                  (0x2UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC13CFGR register  *****************/
+#define RCC_IC13CFGR_IC13INT_Pos                (16U)
+#define RCC_IC13CFGR_IC13INT_Msk                (0xFFUL << RCC_IC13CFGR_IC13INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC13CFGR_IC13INT                    RCC_IC13CFGR_IC13INT_Msk             /*!< Divider IC13 integer division factor */
+#define RCC_IC13CFGR_IC13SEL_Pos                (28U)
+#define RCC_IC13CFGR_IC13SEL_Msk                (0x3UL << RCC_IC13CFGR_IC13SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC13CFGR_IC13SEL                    RCC_IC13CFGR_IC13SEL_Msk             /*!< Divider IC13 source selection */
+#define RCC_IC13CFGR_IC13SEL_0                  (0x1UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC13CFGR_IC13SEL_1                  (0x2UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC14CFGR register  *****************/
+#define RCC_IC14CFGR_IC14INT_Pos                (16U)
+#define RCC_IC14CFGR_IC14INT_Msk                (0xFFUL << RCC_IC14CFGR_IC14INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC14CFGR_IC14INT                    RCC_IC14CFGR_IC14INT_Msk             /*!< Divider IC14 integer division factor */
+#define RCC_IC14CFGR_IC14SEL_Pos                (28U)
+#define RCC_IC14CFGR_IC14SEL_Msk                (0x3UL << RCC_IC14CFGR_IC14SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC14CFGR_IC14SEL                    RCC_IC14CFGR_IC14SEL_Msk             /*!< Divider IC14 source selection */
+#define RCC_IC14CFGR_IC14SEL_0                  (0x1UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC14CFGR_IC14SEL_1                  (0x2UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC15CFGR register  *****************/
+#define RCC_IC15CFGR_IC15INT_Pos                (16U)
+#define RCC_IC15CFGR_IC15INT_Msk                (0xFFUL << RCC_IC15CFGR_IC15INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC15CFGR_IC15INT                    RCC_IC15CFGR_IC15INT_Msk             /*!< Divider IC15 integer division factor */
+#define RCC_IC15CFGR_IC15SEL_Pos                (28U)
+#define RCC_IC15CFGR_IC15SEL_Msk                (0x3UL << RCC_IC15CFGR_IC15SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC15CFGR_IC15SEL                    RCC_IC15CFGR_IC15SEL_Msk             /*!< Divider IC15 source selection */
+#define RCC_IC15CFGR_IC15SEL_0                  (0x1UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC15CFGR_IC15SEL_1                  (0x2UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC16CFGR register  *****************/
+#define RCC_IC16CFGR_IC16INT_Pos                (16U)
+#define RCC_IC16CFGR_IC16INT_Msk                (0xFFUL << RCC_IC16CFGR_IC16INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC16CFGR_IC16INT                    RCC_IC16CFGR_IC16INT_Msk             /*!< Divider IC16 integer division factor */
+#define RCC_IC16CFGR_IC16SEL_Pos                (28U)
+#define RCC_IC16CFGR_IC16SEL_Msk                (0x3UL << RCC_IC16CFGR_IC16SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC16CFGR_IC16SEL                    RCC_IC16CFGR_IC16SEL_Msk             /*!< Divider IC16 source selection */
+#define RCC_IC16CFGR_IC16SEL_0                  (0x1UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC16CFGR_IC16SEL_1                  (0x2UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC17CFGR register  *****************/
+#define RCC_IC17CFGR_IC17INT_Pos                (16U)
+#define RCC_IC17CFGR_IC17INT_Msk                (0xFFUL << RCC_IC17CFGR_IC17INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC17CFGR_IC17INT                    RCC_IC17CFGR_IC17INT_Msk             /*!< Divider IC17 integer division factor */
+#define RCC_IC17CFGR_IC17SEL_Pos                (28U)
+#define RCC_IC17CFGR_IC17SEL_Msk                (0x3UL << RCC_IC17CFGR_IC17SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC17CFGR_IC17SEL                    RCC_IC17CFGR_IC17SEL_Msk             /*!< Divider IC17 source selection */
+#define RCC_IC17CFGR_IC17SEL_0                  (0x1UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC17CFGR_IC17SEL_1                  (0x2UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC18CFGR register  *****************/
+#define RCC_IC18CFGR_IC18INT_Pos                (16U)
+#define RCC_IC18CFGR_IC18INT_Msk                (0xFFUL << RCC_IC18CFGR_IC18INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC18CFGR_IC18INT                    RCC_IC18CFGR_IC18INT_Msk             /*!< Divider IC18 integer division factor */
+#define RCC_IC18CFGR_IC18SEL_Pos                (28U)
+#define RCC_IC18CFGR_IC18SEL_Msk                (0x3UL << RCC_IC18CFGR_IC18SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC18CFGR_IC18SEL                    RCC_IC18CFGR_IC18SEL_Msk             /*!< Divider IC18 source selection */
+#define RCC_IC18CFGR_IC18SEL_0                  (0x1UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC18CFGR_IC18SEL_1                  (0x2UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC19CFGR register  *****************/
+#define RCC_IC19CFGR_IC19INT_Pos                (16U)
+#define RCC_IC19CFGR_IC19INT_Msk                (0xFFUL << RCC_IC19CFGR_IC19INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC19CFGR_IC19INT                    RCC_IC19CFGR_IC19INT_Msk             /*!< Divider IC19 integer division factor */
+#define RCC_IC19CFGR_IC19SEL_Pos                (28U)
+#define RCC_IC19CFGR_IC19SEL_Msk                (0x3UL << RCC_IC19CFGR_IC19SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC19CFGR_IC19SEL                    RCC_IC19CFGR_IC19SEL_Msk             /*!< Divider IC19 source selection */
+#define RCC_IC19CFGR_IC19SEL_0                  (0x1UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC19CFGR_IC19SEL_1                  (0x2UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC20CFGR register  *****************/
+#define RCC_IC20CFGR_IC20INT_Pos                (16U)
+#define RCC_IC20CFGR_IC20INT_Msk                (0xFFUL << RCC_IC20CFGR_IC20INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC20CFGR_IC20INT                    RCC_IC20CFGR_IC20INT_Msk             /*!< Divider IC20 integer division factor */
+#define RCC_IC20CFGR_IC20SEL_Pos                (28U)
+#define RCC_IC20CFGR_IC20SEL_Msk                (0x3UL << RCC_IC20CFGR_IC20SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC20CFGR_IC20SEL                    RCC_IC20CFGR_IC20SEL_Msk             /*!< Divider IC20 source selection */
+#define RCC_IC20CFGR_IC20SEL_0                  (0x1UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC20CFGR_IC20SEL_1                  (0x2UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x20000000 */
+
+/*******************  Bit definition for RCC_CIER register  *******************/
+#define RCC_CIER_LSIRDYIE_Pos                   (0U)
+#define RCC_CIER_LSIRDYIE_Msk                   (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                       RCC_CIER_LSIRDYIE_Msk                /*!< LSI ready interrupt enable */
+#define RCC_CIER_LSERDYIE_Pos                   (1U)
+#define RCC_CIER_LSERDYIE_Msk                   (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                       RCC_CIER_LSERDYIE_Msk                /*!< LSE ready interrupt enable */
+#define RCC_CIER_MSIRDYIE_Pos                   (2U)
+#define RCC_CIER_MSIRDYIE_Msk                   (0x1UL << RCC_CIER_MSIRDYIE_Pos)      /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                       RCC_CIER_MSIRDYIE_Msk                /*!< MSI ready interrupt enable */
+#define RCC_CIER_HSIRDYIE_Pos                   (3U)
+#define RCC_CIER_HSIRDYIE_Msk                   (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                       RCC_CIER_HSIRDYIE_Msk                /*!< HSI ready interrupt enable */
+#define RCC_CIER_HSERDYIE_Pos                   (4U)
+#define RCC_CIER_HSERDYIE_Msk                   (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                       RCC_CIER_HSERDYIE_Msk                /*!< HSE ready interrupt enable */
+#define RCC_CIER_PLL1RDYIE_Pos                  (8U)
+#define RCC_CIER_PLL1RDYIE_Msk                  (0x1UL << RCC_CIER_PLL1RDYIE_Pos)     /*!< 0x00000100 */
+#define RCC_CIER_PLL1RDYIE                      RCC_CIER_PLL1RDYIE_Msk               /*!< PLL1 ready interrupt enable */
+#define RCC_CIER_PLL2RDYIE_Pos                  (9U)
+#define RCC_CIER_PLL2RDYIE_Msk                  (0x1UL << RCC_CIER_PLL2RDYIE_Pos)     /*!< 0x00000200 */
+#define RCC_CIER_PLL2RDYIE                      RCC_CIER_PLL2RDYIE_Msk               /*!< PLL2 ready interrupt enable */
+#define RCC_CIER_PLL3RDYIE_Pos                  (10U)
+#define RCC_CIER_PLL3RDYIE_Msk                  (0x1UL << RCC_CIER_PLL3RDYIE_Pos)     /*!< 0x00000400 */
+#define RCC_CIER_PLL3RDYIE                      RCC_CIER_PLL3RDYIE_Msk               /*!< PLL3 ready interrupt enable */
+#define RCC_CIER_PLL4RDYIE_Pos                  (11U)
+#define RCC_CIER_PLL4RDYIE_Msk                  (0x1UL << RCC_CIER_PLL4RDYIE_Pos)     /*!< 0x00000800 */
+#define RCC_CIER_PLL4RDYIE                      RCC_CIER_PLL4RDYIE_Msk               /*!< PLL4 ready interrupt enable */
+#define RCC_CIER_LSECSSIE_Pos                   (16U)
+#define RCC_CIER_LSECSSIE_Msk                   (0x1UL << RCC_CIER_LSECSSIE_Pos)      /*!< 0x00010000 */
+#define RCC_CIER_LSECSSIE                       RCC_CIER_LSECSSIE_Msk                /*!< LSE CSS interrupt enable */
+#define RCC_CIER_HSECSSIE_Pos                   (17U)
+#define RCC_CIER_HSECSSIE_Msk                   (0x1UL << RCC_CIER_HSECSSIE_Pos)      /*!< 0x00020000 */
+#define RCC_CIER_HSECSSIE                       RCC_CIER_HSECSSIE_Msk                /*!< HSE CSS interrupt enable */
+#define RCC_CIER_WKUPIE_Pos                     (24U)
+#define RCC_CIER_WKUPIE_Msk                     (0x1UL << RCC_CIER_WKUPIE_Pos)        /*!< 0x01000000 */
+#define RCC_CIER_WKUPIE                         RCC_CIER_WKUPIE_Msk                  /*!< CPU wake-up from Stop interrupt enable */
+
+/*******************  Bit definition for RCC_CIFR register  *******************/
+#define RCC_CIFR_LSIRDYF_Pos                    (0U)
+#define RCC_CIFR_LSIRDYF_Msk                    (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                        RCC_CIFR_LSIRDYF_Msk                 /*!< LSI ready interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos                    (1U)
+#define RCC_CIFR_LSERDYF_Msk                    (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                        RCC_CIFR_LSERDYF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos                    (2U)
+#define RCC_CIFR_MSIRDYF_Msk                    (0x1UL << RCC_CIFR_MSIRDYF_Pos)       /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                        RCC_CIFR_MSIRDYF_Msk                 /*!< MSI ready interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos                    (3U)
+#define RCC_CIFR_HSIRDYF_Msk                    (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                        RCC_CIFR_HSIRDYF_Msk                 /*!< HSI ready interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos                    (4U)
+#define RCC_CIFR_HSERDYF_Msk                    (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                        RCC_CIFR_HSERDYF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_PLL1RDYF_Pos                   (8U)
+#define RCC_CIFR_PLL1RDYF_Msk                   (0x1UL << RCC_CIFR_PLL1RDYF_Pos)      /*!< 0x00000100 */
+#define RCC_CIFR_PLL1RDYF                       RCC_CIFR_PLL1RDYF_Msk                /*!< PLL1 ready interrupt flag */
+#define RCC_CIFR_PLL2RDYF_Pos                   (9U)
+#define RCC_CIFR_PLL2RDYF_Msk                   (0x1UL << RCC_CIFR_PLL2RDYF_Pos)      /*!< 0x00000200 */
+#define RCC_CIFR_PLL2RDYF                       RCC_CIFR_PLL2RDYF_Msk                /*!< PLL2 ready interrupt flag */
+#define RCC_CIFR_PLL3RDYF_Pos                   (10U)
+#define RCC_CIFR_PLL3RDYF_Msk                   (0x1UL << RCC_CIFR_PLL3RDYF_Pos)      /*!< 0x00000400 */
+#define RCC_CIFR_PLL3RDYF                       RCC_CIFR_PLL3RDYF_Msk                /*!< PLL3 ready interrupt flag */
+#define RCC_CIFR_PLL4RDYF_Pos                   (11U)
+#define RCC_CIFR_PLL4RDYF_Msk                   (0x1UL << RCC_CIFR_PLL4RDYF_Pos)      /*!< 0x00000800 */
+#define RCC_CIFR_PLL4RDYF                       RCC_CIFR_PLL4RDYF_Msk                /*!< PLL4 ready interrupt flag */
+#define RCC_CIFR_LSECSSF_Pos                    (16U)
+#define RCC_CIFR_LSECSSF_Msk                    (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00010000 */
+#define RCC_CIFR_LSECSSF                        RCC_CIFR_LSECSSF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_HSECSSF_Pos                    (17U)
+#define RCC_CIFR_HSECSSF_Msk                    (0x1UL << RCC_CIFR_HSECSSF_Pos)       /*!< 0x00020000 */
+#define RCC_CIFR_HSECSSF                        RCC_CIFR_HSECSSF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_WKUPF_Pos                      (24U)
+#define RCC_CIFR_WKUPF_Msk                      (0x1UL << RCC_CIFR_WKUPF_Pos)         /*!< 0x01000000 */
+#define RCC_CIFR_WKUPF                          RCC_CIFR_WKUPF_Msk                   /*!< CPU wake-up from Stop interrupt flag */
+
+/*******************  Bit definition for RCC_CICR register  *******************/
+#define RCC_CICR_LSIRDYC_Pos                    (0U)
+#define RCC_CICR_LSIRDYC_Msk                    (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                        RCC_CICR_LSIRDYC_Msk                 /*!< LSI ready interrupt clear */
+#define RCC_CICR_LSERDYC_Pos                    (1U)
+#define RCC_CICR_LSERDYC_Msk                    (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                        RCC_CICR_LSERDYC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_MSIRDYC_Pos                    (2U)
+#define RCC_CICR_MSIRDYC_Msk                    (0x1UL << RCC_CICR_MSIRDYC_Pos)       /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                        RCC_CICR_MSIRDYC_Msk                 /*!< MSI ready interrupt clear */
+#define RCC_CICR_HSIRDYC_Pos                    (3U)
+#define RCC_CICR_HSIRDYC_Msk                    (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                        RCC_CICR_HSIRDYC_Msk                 /*!< HSI ready interrupt clear */
+#define RCC_CICR_HSERDYC_Pos                    (4U)
+#define RCC_CICR_HSERDYC_Msk                    (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                        RCC_CICR_HSERDYC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_PLL1RDYC_Pos                   (8U)
+#define RCC_CICR_PLL1RDYC_Msk                   (0x1UL << RCC_CICR_PLL1RDYC_Pos)      /*!< 0x00000100 */
+#define RCC_CICR_PLL1RDYC                       RCC_CICR_PLL1RDYC_Msk                /*!< PLL1 ready interrupt clear */
+#define RCC_CICR_PLL2RDYC_Pos                   (9U)
+#define RCC_CICR_PLL2RDYC_Msk                   (0x1UL << RCC_CICR_PLL2RDYC_Pos)      /*!< 0x00000200 */
+#define RCC_CICR_PLL2RDYC                       RCC_CICR_PLL2RDYC_Msk                /*!< PLL2 ready interrupt clear */
+#define RCC_CICR_PLL3RDYC_Pos                   (10U)
+#define RCC_CICR_PLL3RDYC_Msk                   (0x1UL << RCC_CICR_PLL3RDYC_Pos)      /*!< 0x00000400 */
+#define RCC_CICR_PLL3RDYC                       RCC_CICR_PLL3RDYC_Msk                /*!< PLL3 ready interrupt clear */
+#define RCC_CICR_PLL4RDYC_Pos                   (11U)
+#define RCC_CICR_PLL4RDYC_Msk                   (0x1UL << RCC_CICR_PLL4RDYC_Pos)      /*!< 0x00000800 */
+#define RCC_CICR_PLL4RDYC                       RCC_CICR_PLL4RDYC_Msk                /*!< PLL4 ready interrupt clear */
+#define RCC_CICR_LSECSSC_Pos                    (16U)
+#define RCC_CICR_LSECSSC_Msk                    (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00010000 */
+#define RCC_CICR_LSECSSC                        RCC_CICR_LSECSSC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_HSECSSC_Pos                    (17U)
+#define RCC_CICR_HSECSSC_Msk                    (0x1UL << RCC_CICR_HSECSSC_Pos)       /*!< 0x00020000 */
+#define RCC_CICR_HSECSSC                        RCC_CICR_HSECSSC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_WKUPFC_Pos                     (24U)
+#define RCC_CICR_WKUPFC_Msk                     (0x1UL << RCC_CICR_WKUPFC_Pos)        /*!< 0x01000000 */
+#define RCC_CICR_WKUPFC                         RCC_CICR_WKUPFC_Msk                  /*!< CPU wake-up ready interrupt clear */
+
+/******************  Bit definition for RCC_CCIPR1 register  ******************/
+#define RCC_CCIPR1_ADF1SEL_Pos                  (0U)
+#define RCC_CCIPR1_ADF1SEL_Msk                  (0x7UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR1_ADF1SEL                      RCC_CCIPR1_ADF1SEL_Msk                            /*!< Source selection for the ADF1 kernel clock */
+#define RCC_CCIPR1_ADF1SEL_0                    (0x1UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR1_ADF1SEL_1                    (0x2UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR1_ADF1SEL_2                    (0x4UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR1_ADC12SEL_Pos                 (4U)
+#define RCC_CCIPR1_ADC12SEL_Msk                 (0x7UL << RCC_CCIPR1_ADC12SEL_Pos)                 /*!< 0x00000070 */
+#define RCC_CCIPR1_ADC12SEL                     RCC_CCIPR1_ADC12SEL_Msk                           /*!< Source selection for the ADC12 kernel clock */
+#define RCC_CCIPR1_ADC12SEL_0                   (0x1UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR1_ADC12SEL_1                   (0x2UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR1_ADC12SEL_2                   (0x4UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000040 */
+#define RCC_CCIPR1_ADCPRE_Pos                   (8U)
+#define RCC_CCIPR1_ADCPRE_Msk                   (0xFFUL << RCC_CCIPR1_ADCPRE_Pos)                  /*!< 0x0000FF00 */
+#define RCC_CCIPR1_ADCPRE                       RCC_CCIPR1_ADCPRE_Msk                             /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */
+#define RCC_CCIPR1_ADCPRE_0                     (0x1UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR1_ADCPRE_1                     (0x2UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR1_ADCPRE_2                     (0x4UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000400 */
+#define RCC_CCIPR1_ADCPRE_3                     (0x8UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000800 */
+#define RCC_CCIPR1_ADCPRE_4                     (0x10UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR1_ADCPRE_5                     (0x20UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR1_ADCPRE_6                     (0x40UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR1_ADCPRE_7                     (0x80UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR1_DCMIPPSEL_Pos                (20U)
+#define RCC_CCIPR1_DCMIPPSEL_Msk                (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos)                /*!< 0x00300000 */
+#define RCC_CCIPR1_DCMIPPSEL                    RCC_CCIPR1_DCMIPPSEL_Msk                          /*!< Source selection for the DCMIPP kernel clock */
+#define RCC_CCIPR1_DCMIPPSEL_0                  (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00100000 */
+#define RCC_CCIPR1_DCMIPPSEL_1                  (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00200000 */
+
+/******************  Bit definition for RCC_CCIPR2 register  ******************/
+#define RCC_CCIPR2_ETH1PTPSEL_Pos               (0U)
+#define RCC_CCIPR2_ETH1PTPSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000003 */
+#define RCC_CCIPR2_ETH1PTPSEL                   RCC_CCIPR2_ETH1PTPSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1PTPSEL_0                 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR2_ETH1PTPSEL_1                 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR2_ETH1PTPDIV_Pos               (4U)
+#define RCC_CCIPR2_ETH1PTPDIV_Msk               (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos)               /*!< 0x000000F0 */
+#define RCC_CCIPR2_ETH1PTPDIV                   RCC_CCIPR2_ETH1PTPDIV_Msk                         /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */
+#define RCC_CCIPR2_ETH1PTPDIV_0                 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR2_ETH1PTPDIV_1                 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR2_ETH1PTPDIV_2                 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR2_ETH1PTPDIV_3                 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000080 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos           (8U)
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk           (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos)           /*!< 0x00000100 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK               RCC_CCIPR2_ETH1PWRDOWNACK_Msk                     /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1CLKSEL_Pos               (12U)
+#define RCC_CCIPR2_ETH1CLKSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR2_ETH1CLKSEL                   RCC_CCIPR2_ETH1CLKSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1CLKSEL_0                 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR2_ETH1CLKSEL_1                 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR2_ETH1SEL_Pos                  (16U)
+#define RCC_CCIPR2_ETH1SEL_Msk                  (0x7UL << RCC_CCIPR2_ETH1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR2_ETH1SEL                      RCC_CCIPR2_ETH1SEL_Msk                            /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1SEL_0                    (0x1UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR2_ETH1SEL_1                    (0x2UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR2_ETH1SEL_2                    (0x4UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL_Pos            (20U)
+#define RCC_CCIPR2_ETH1REFCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos)            /*!< 0x00100000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL                RCC_CCIPR2_ETH1REFCLKSEL_Msk                      /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos            (24U)
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR2_ETH1GTXCLKSEL                RCC_CCIPR2_ETH1GTXCLKSEL_Msk                      /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR3 register  ******************/
+#define RCC_CCIPR3_FDCANSEL_Pos                 (0U)
+#define RCC_CCIPR3_FDCANSEL_Msk                 (0x3UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR3_FDCANSEL                     RCC_CCIPR3_FDCANSEL_Msk                           /*!< Source selection for the FDCAN kernel clock */
+#define RCC_CCIPR3_FDCANSEL_0                   (0x1UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR3_FDCANSEL_1                   (0x2UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR3_FMCSEL_Pos                   (4U)
+#define RCC_CCIPR3_FMCSEL_Msk                   (0x3UL << RCC_CCIPR3_FMCSEL_Pos)                   /*!< 0x00000030 */
+#define RCC_CCIPR3_FMCSEL                       RCC_CCIPR3_FMCSEL_Msk                             /*!< Source selection for the FMC kernel clock */
+#define RCC_CCIPR3_FMCSEL_0                     (0x1UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000010 */
+#define RCC_CCIPR3_FMCSEL_1                     (0x2UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000020 */
+#define RCC_CCIPR3_DFTSEL_Pos                   (8U)
+#define RCC_CCIPR3_DFTSEL_Msk                   (0x1UL << RCC_CCIPR3_DFTSEL_Pos)                   /*!< 0x00000100 */
+#define RCC_CCIPR3_DFTSEL                       RCC_CCIPR3_DFTSEL_Msk                             /*!< Source selection for the DFT kernel clock */
+
+/******************  Bit definition for RCC_CCIPR4 register  ******************/
+#define RCC_CCIPR4_I2C1SEL_Pos                  (0U)
+#define RCC_CCIPR4_I2C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR4_I2C1SEL                      RCC_CCIPR4_I2C1SEL_Msk                            /*!< Source selection for the I2C1 kernel clock */
+#define RCC_CCIPR4_I2C1SEL_0                    (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR4_I2C1SEL_1                    (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR4_I2C1SEL_2                    (0x4UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR4_I2C2SEL_Pos                  (4U)
+#define RCC_CCIPR4_I2C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C2SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR4_I2C2SEL                      RCC_CCIPR4_I2C2SEL_Msk                            /*!< Source selection for the I2C2 kernel clock */
+#define RCC_CCIPR4_I2C2SEL_0                    (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR4_I2C2SEL_1                    (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR4_I2C2SEL_2                    (0x4UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR4_I2C3SEL_Pos                  (8U)
+#define RCC_CCIPR4_I2C3SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C3SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR4_I2C3SEL                      RCC_CCIPR4_I2C3SEL_Msk                            /*!< Source selection for the I2C3 kernel clock */
+#define RCC_CCIPR4_I2C3SEL_0                    (0x1UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR4_I2C3SEL_1                    (0x2UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR4_I2C3SEL_2                    (0x4UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR4_I2C4SEL_Pos                  (12U)
+#define RCC_CCIPR4_I2C4SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C4SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR4_I2C4SEL                      RCC_CCIPR4_I2C4SEL_Msk                            /*!< Source selection for the I2C4 kernel clock */
+#define RCC_CCIPR4_I2C4SEL_0                    (0x1UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR4_I2C4SEL_1                    (0x2UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR4_I2C4SEL_2                    (0x4UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR4_I3C1SEL_Pos                  (16U)
+#define RCC_CCIPR4_I3C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR4_I3C1SEL                      RCC_CCIPR4_I3C1SEL_Msk                            /*!< Source selection for the I3C1 kernel clock */
+#define RCC_CCIPR4_I3C1SEL_0                    (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR4_I3C1SEL_1                    (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR4_I3C1SEL_2                    (0x4UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR4_I3C2SEL_Pos                  (20U)
+#define RCC_CCIPR4_I3C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C2SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR4_I3C2SEL                      RCC_CCIPR4_I3C2SEL_Msk                            /*!< Source selection for the I3C2 kernel clock */
+#define RCC_CCIPR4_I3C2SEL_0                    (0x1UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR4_I3C2SEL_1                    (0x2UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR4_I3C2SEL_2                    (0x4UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR4_LTDCSEL_Pos                  (24U)
+#define RCC_CCIPR4_LTDCSEL_Msk                  (0x3UL << RCC_CCIPR4_LTDCSEL_Pos)                  /*!< 0x03000000 */
+#define RCC_CCIPR4_LTDCSEL                      RCC_CCIPR4_LTDCSEL_Msk                            /*!< Source selection for the LTDC kernel clock */
+#define RCC_CCIPR4_LTDCSEL_0                    (0x1UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR4_LTDCSEL_1                    (0x2UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x02000000 */
+
+/******************  Bit definition for RCC_CCIPR5 register  ******************/
+#define RCC_CCIPR5_MCO1SEL_Pos                  (0U)
+#define RCC_CCIPR5_MCO1SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR5_MCO1SEL                      RCC_CCIPR5_MCO1SEL_Msk                            /*!< Source selection for the MCO1 kernel clock */
+#define RCC_CCIPR5_MCO1SEL_0                    (0x1UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR5_MCO1SEL_1                    (0x2UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR5_MCO1SEL_2                    (0x4UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR5_MCO1PRE_Pos                  (4U)
+#define RCC_CCIPR5_MCO1PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO1PRE_Pos)                  /*!< 0x000000F0 */
+#define RCC_CCIPR5_MCO1PRE                      RCC_CCIPR5_MCO1PRE_Msk                            /*!< MCO1 Kernel clock divider selection (for clock MCO1) */
+#define RCC_CCIPR5_MCO1PRE_0                    (0x1UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR5_MCO1PRE_1                    (0x2UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR5_MCO1PRE_2                    (0x4UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR5_MCO1PRE_3                    (0x8UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000080 */
+#define RCC_CCIPR5_MCO2SEL_Pos                  (8U)
+#define RCC_CCIPR5_MCO2SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR5_MCO2SEL                      RCC_CCIPR5_MCO2SEL_Msk                            /*!< Source selection for the MCO2 kernel clock */
+#define RCC_CCIPR5_MCO2SEL_0                    (0x1UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR5_MCO2SEL_1                    (0x2UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR5_MCO2SEL_2                    (0x4UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR5_MCO2PRE_Pos                  (12U)
+#define RCC_CCIPR5_MCO2PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO2PRE_Pos)                  /*!< 0x0000F000 */
+#define RCC_CCIPR5_MCO2PRE                      RCC_CCIPR5_MCO2PRE_Msk                            /*!< MCO2 Kernel clock divider selection (for clock MCO2) */
+#define RCC_CCIPR5_MCO2PRE_0                    (0x1UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR5_MCO2PRE_1                    (0x2UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR5_MCO2PRE_2                    (0x4UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR5_MCO2PRE_3                    (0x8UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00008000 */
+#define RCC_CCIPR5_MDF1SEL_Pos                  (16U)
+#define RCC_CCIPR5_MDF1SEL_Msk                  (0x7UL << RCC_CCIPR5_MDF1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR5_MDF1SEL                      RCC_CCIPR5_MDF1SEL_Msk                            /*!< Source selection for the MDF1 kernel clock */
+#define RCC_CCIPR5_MDF1SEL_0                    (0x1UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR5_MDF1SEL_1                    (0x2UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR5_MDF1SEL_2                    (0x4UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00040000 */
+
+/******************  Bit definition for RCC_CCIPR6 register  ******************/
+#define RCC_CCIPR6_XSPI1SEL_Pos                 (0U)
+#define RCC_CCIPR6_XSPI1SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR6_XSPI1SEL                     RCC_CCIPR6_XSPI1SEL_Msk                           /*!< Source selection for the XSPI1 kernel clock */
+#define RCC_CCIPR6_XSPI1SEL_0                   (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR6_XSPI1SEL_1                   (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR6_XSPI2SEL_Pos                 (4U)
+#define RCC_CCIPR6_XSPI2SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos)                 /*!< 0x00000030 */
+#define RCC_CCIPR6_XSPI2SEL                     RCC_CCIPR6_XSPI2SEL_Msk                           /*!< Source selection for the XSPI2 kernel clock */
+#define RCC_CCIPR6_XSPI2SEL_0                   (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR6_XSPI2SEL_1                   (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR6_XSPI3SEL_Pos                 (8U)
+#define RCC_CCIPR6_XSPI3SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos)                 /*!< 0x00000300 */
+#define RCC_CCIPR6_XSPI3SEL                     RCC_CCIPR6_XSPI3SEL_Msk                           /*!< Source selection for the XSPI3 kernel clock */
+#define RCC_CCIPR6_XSPI3SEL_0                   (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000100 */
+#define RCC_CCIPR6_XSPI3SEL_1                   (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000200 */
+#define RCC_CCIPR6_OTGPHY1SEL_Pos               (12U)
+#define RCC_CCIPR6_OTGPHY1SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR6_OTGPHY1SEL                   RCC_CCIPR6_OTGPHY1SEL_Msk                         /*!< Source selection for the OTGPHY1 kernel clock */
+#define RCC_CCIPR6_OTGPHY1SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR6_OTGPHY1SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos          (16U)
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos)          /*!< 0x00010000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL              RCC_CCIPR6_OTGPHY1CKREFSEL_Msk                    /*!< Set and reset by software */
+#define RCC_CCIPR6_OTGPHY2SEL_Pos               (20U)
+#define RCC_CCIPR6_OTGPHY2SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos)               /*!< 0x00300000 */
+#define RCC_CCIPR6_OTGPHY2SEL                   RCC_CCIPR6_OTGPHY2SEL_Msk                         /*!< Source selection for the OTGPHY2 kernel clock */
+#define RCC_CCIPR6_OTGPHY2SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR6_OTGPHY2SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos          (24U)
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL              RCC_CCIPR6_OTGPHY2CKREFSEL_Msk                    /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR7 register  ******************/
+#define RCC_CCIPR7_PERSEL_Pos                   (0U)
+#define RCC_CCIPR7_PERSEL_Msk                   (0x7UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000007 */
+#define RCC_CCIPR7_PERSEL                       RCC_CCIPR7_PERSEL_Msk                             /*!< Source selection for the PER kernel clock */
+#define RCC_CCIPR7_PERSEL_0                     (0x1UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000001 */
+#define RCC_CCIPR7_PERSEL_1                     (0x2UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000002 */
+#define RCC_CCIPR7_PERSEL_2                     (0x4UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000004 */
+#define RCC_CCIPR7_PSSISEL_Pos                  (4U)
+#define RCC_CCIPR7_PSSISEL_Msk                  (0x3UL << RCC_CCIPR7_PSSISEL_Pos)                  /*!< 0x00000030 */
+#define RCC_CCIPR7_PSSISEL                      RCC_CCIPR7_PSSISEL_Msk                            /*!< Source selection for the PSSI kernel clock */
+#define RCC_CCIPR7_PSSISEL_0                    (0x1UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR7_PSSISEL_1                    (0x2UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR7_RTCSEL_Pos                   (8U)
+#define RCC_CCIPR7_RTCSEL_Msk                   (0x3UL << RCC_CCIPR7_RTCSEL_Pos)                   /*!< 0x00000300 */
+#define RCC_CCIPR7_RTCSEL                       RCC_CCIPR7_RTCSEL_Msk                             /*!< Source selection for the RTC kernel clock */
+#define RCC_CCIPR7_RTCSEL_0                     (0x1UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR7_RTCSEL_1                     (0x2UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR7_RTCPRE_Pos                   (12U)
+#define RCC_CCIPR7_RTCPRE_Msk                   (0x3FUL << RCC_CCIPR7_RTCPRE_Pos)                  /*!< 0x0003F000 */
+#define RCC_CCIPR7_RTCPRE                       RCC_CCIPR7_RTCPRE_Msk                             /*!< RTC OSC clock divider selection (for clock hse_ck) */
+#define RCC_CCIPR7_RTCPRE_0                     (0x1UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR7_RTCPRE_1                     (0x2UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR7_RTCPRE_2                     (0x4UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR7_RTCPRE_3                     (0x8UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR7_RTCPRE_4                     (0x10UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00010000 */
+#define RCC_CCIPR7_RTCPRE_5                     (0x20UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00020000 */
+#define RCC_CCIPR7_SAI1SEL_Pos                  (20U)
+#define RCC_CCIPR7_SAI1SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI1SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR7_SAI1SEL                      RCC_CCIPR7_SAI1SEL_Msk                            /*!< Source selection for the SAI1 kernel clock */
+#define RCC_CCIPR7_SAI1SEL_0                    (0x1UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR7_SAI1SEL_1                    (0x2UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR7_SAI1SEL_2                    (0x4UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR7_SAI2SEL_Pos                  (24U)
+#define RCC_CCIPR7_SAI2SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI2SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR7_SAI2SEL                      RCC_CCIPR7_SAI2SEL_Msk                            /*!< Source selection for the SAI2 kernel clock */
+#define RCC_CCIPR7_SAI2SEL_0                    (0x1UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR7_SAI2SEL_1                    (0x2UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR7_SAI2SEL_2                    (0x4UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x04000000 */
+
+/******************  Bit definition for RCC_CCIPR8 register  ******************/
+#define RCC_CCIPR8_SDMMC1SEL_Pos                (0U)
+#define RCC_CCIPR8_SDMMC1SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000003 */
+#define RCC_CCIPR8_SDMMC1SEL                    RCC_CCIPR8_SDMMC1SEL_Msk                          /*!< Source selection for the SDMMC1 kernel clock */
+#define RCC_CCIPR8_SDMMC1SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR8_SDMMC1SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR8_SDMMC2SEL_Pos                (4U)
+#define RCC_CCIPR8_SDMMC2SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos)                /*!< 0x00000030 */
+#define RCC_CCIPR8_SDMMC2SEL                    RCC_CCIPR8_SDMMC2SEL_Msk                          /*!< Source selection for the SDMMC2 kernel clock */
+#define RCC_CCIPR8_SDMMC2SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000010 */
+#define RCC_CCIPR8_SDMMC2SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000020 */
+
+/******************  Bit definition for RCC_CCIPR9 register  ******************/
+#define RCC_CCIPR9_SPDIFRX1SEL_Pos              (0U)
+#define RCC_CCIPR9_SPDIFRX1SEL_Msk              (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000007 */
+#define RCC_CCIPR9_SPDIFRX1SEL                  RCC_CCIPR9_SPDIFRX1SEL_Msk                        /*!< Source selection for the SPDIFRX1 kernel clock */
+#define RCC_CCIPR9_SPDIFRX1SEL_0                (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000001 */
+#define RCC_CCIPR9_SPDIFRX1SEL_1                (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000002 */
+#define RCC_CCIPR9_SPDIFRX1SEL_2                (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000004 */
+#define RCC_CCIPR9_SPI1SEL_Pos                  (4U)
+#define RCC_CCIPR9_SPI1SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI1SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR9_SPI1SEL                      RCC_CCIPR9_SPI1SEL_Msk                            /*!< Source selection for the SPI1 kernel clock */
+#define RCC_CCIPR9_SPI1SEL_0                    (0x1UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR9_SPI1SEL_1                    (0x2UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR9_SPI1SEL_2                    (0x4UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR9_SPI2SEL_Pos                  (8U)
+#define RCC_CCIPR9_SPI2SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR9_SPI2SEL                      RCC_CCIPR9_SPI2SEL_Msk                            /*!< Source selection for the SPI2 kernel clock */
+#define RCC_CCIPR9_SPI2SEL_0                    (0x1UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR9_SPI2SEL_1                    (0x2UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR9_SPI2SEL_2                    (0x4UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR9_SPI3SEL_Pos                  (12U)
+#define RCC_CCIPR9_SPI3SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI3SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR9_SPI3SEL                      RCC_CCIPR9_SPI3SEL_Msk                            /*!< Source selection for the SPI3 kernel clock */
+#define RCC_CCIPR9_SPI3SEL_0                    (0x1UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR9_SPI3SEL_1                    (0x2UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR9_SPI3SEL_2                    (0x4UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR9_SPI4SEL_Pos                  (16U)
+#define RCC_CCIPR9_SPI4SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI4SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR9_SPI4SEL                      RCC_CCIPR9_SPI4SEL_Msk                            /*!< Source selection for the SPI4 kernel clock */
+#define RCC_CCIPR9_SPI4SEL_0                    (0x1UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR9_SPI4SEL_1                    (0x2UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR9_SPI4SEL_2                    (0x4UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR9_SPI5SEL_Pos                  (20U)
+#define RCC_CCIPR9_SPI5SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI5SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR9_SPI5SEL                      RCC_CCIPR9_SPI5SEL_Msk                            /*!< Source selection for the SPI5 kernel clock */
+#define RCC_CCIPR9_SPI5SEL_0                    (0x1UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR9_SPI5SEL_1                    (0x2UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR9_SPI5SEL_2                    (0x4UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR9_SPI6SEL_Pos                  (24U)
+#define RCC_CCIPR9_SPI6SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI6SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR9_SPI6SEL                      RCC_CCIPR9_SPI6SEL_Msk                            /*!< Source selection for the SPI6 kernel clock */
+#define RCC_CCIPR9_SPI6SEL_0                    (0x1UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR9_SPI6SEL_1                    (0x2UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR9_SPI6SEL_2                    (0x4UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR12 register  ******************/
+#define RCC_CCIPR12_LPTIM1SEL_Pos               (8U)
+#define RCC_CCIPR12_LPTIM1SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR12_LPTIM1SEL                   RCC_CCIPR12_LPTIM1SEL_Msk                         /*!< Source selection for the LPTIM1 kernel clock */
+#define RCC_CCIPR12_LPTIM1SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR12_LPTIM1SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR12_LPTIM1SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR12_LPTIM2SEL_Pos               (12U)
+#define RCC_CCIPR12_LPTIM2SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos)               /*!< 0x00007000 */
+#define RCC_CCIPR12_LPTIM2SEL                   RCC_CCIPR12_LPTIM2SEL_Msk                         /*!< Source selection for the LPTIM2 kernel clock */
+#define RCC_CCIPR12_LPTIM2SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR12_LPTIM2SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR12_LPTIM2SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00004000 */
+#define RCC_CCIPR12_LPTIM3SEL_Pos               (16U)
+#define RCC_CCIPR12_LPTIM3SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos)               /*!< 0x00070000 */
+#define RCC_CCIPR12_LPTIM3SEL                   RCC_CCIPR12_LPTIM3SEL_Msk                         /*!< Source selection for the LPTIM3 kernel clock */
+#define RCC_CCIPR12_LPTIM3SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00010000 */
+#define RCC_CCIPR12_LPTIM3SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00020000 */
+#define RCC_CCIPR12_LPTIM3SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00040000 */
+#define RCC_CCIPR12_LPTIM4SEL_Pos               (20U)
+#define RCC_CCIPR12_LPTIM4SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR12_LPTIM4SEL                   RCC_CCIPR12_LPTIM4SEL_Msk                         /*!< Source selection for the LPTIM4 kernel clock */
+#define RCC_CCIPR12_LPTIM4SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR12_LPTIM4SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR12_LPTIM4SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR12_LPTIM5SEL_Pos               (24U)
+#define RCC_CCIPR12_LPTIM5SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos)               /*!< 0x07000000 */
+#define RCC_CCIPR12_LPTIM5SEL                   RCC_CCIPR12_LPTIM5SEL_Msk                         /*!< Source selection for the LPTIM5 kernel clock */
+#define RCC_CCIPR12_LPTIM5SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x01000000 */
+#define RCC_CCIPR12_LPTIM5SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x02000000 */
+#define RCC_CCIPR12_LPTIM5SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR13 register  ******************/
+#define RCC_CCIPR13_USART1SEL_Pos               (0U)
+#define RCC_CCIPR13_USART1SEL_Msk               (0x7UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000007 */
+#define RCC_CCIPR13_USART1SEL                   RCC_CCIPR13_USART1SEL_Msk                         /*!< Source selection for the USART1 kernel clock */
+#define RCC_CCIPR13_USART1SEL_0                 (0x1UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR13_USART1SEL_1                 (0x2UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR13_USART1SEL_2                 (0x4UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000004 */
+#define RCC_CCIPR13_USART2SEL_Pos               (4U)
+#define RCC_CCIPR13_USART2SEL_Msk               (0x7UL << RCC_CCIPR13_USART2SEL_Pos)               /*!< 0x00000070 */
+#define RCC_CCIPR13_USART2SEL                   RCC_CCIPR13_USART2SEL_Msk                         /*!< Source selection for the USART2 kernel clock */
+#define RCC_CCIPR13_USART2SEL_0                 (0x1UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR13_USART2SEL_1                 (0x2UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR13_USART2SEL_2                 (0x4UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR13_USART3SEL_Pos               (8U)
+#define RCC_CCIPR13_USART3SEL_Msk               (0x7UL << RCC_CCIPR13_USART3SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR13_USART3SEL                   RCC_CCIPR13_USART3SEL_Msk                         /*!< Source selection for the USART3 kernel clock */
+#define RCC_CCIPR13_USART3SEL_0                 (0x1UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR13_USART3SEL_1                 (0x2UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR13_USART3SEL_2                 (0x4UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR13_UART4SEL_Pos                (12U)
+#define RCC_CCIPR13_UART4SEL_Msk                (0x7UL << RCC_CCIPR13_UART4SEL_Pos)                /*!< 0x00007000 */
+#define RCC_CCIPR13_UART4SEL                    RCC_CCIPR13_UART4SEL_Msk                          /*!< Source selection for the UART4 kernel clock */
+#define RCC_CCIPR13_UART4SEL_0                  (0x1UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00001000 */
+#define RCC_CCIPR13_UART4SEL_1                  (0x2UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00002000 */
+#define RCC_CCIPR13_UART4SEL_2                  (0x4UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00004000 */
+#define RCC_CCIPR13_UART5SEL_Pos                (16U)
+#define RCC_CCIPR13_UART5SEL_Msk                (0x7UL << RCC_CCIPR13_UART5SEL_Pos)                /*!< 0x00070000 */
+#define RCC_CCIPR13_UART5SEL                    RCC_CCIPR13_UART5SEL_Msk                          /*!< Source selection for the UART5 kernel clock */
+#define RCC_CCIPR13_UART5SEL_0                  (0x1UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00010000 */
+#define RCC_CCIPR13_UART5SEL_1                  (0x2UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00020000 */
+#define RCC_CCIPR13_UART5SEL_2                  (0x4UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00040000 */
+#define RCC_CCIPR13_USART6SEL_Pos               (20U)
+#define RCC_CCIPR13_USART6SEL_Msk               (0x7UL << RCC_CCIPR13_USART6SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR13_USART6SEL                   RCC_CCIPR13_USART6SEL_Msk                         /*!< Source selection for the USART6 kernel clock */
+#define RCC_CCIPR13_USART6SEL_0                 (0x1UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR13_USART6SEL_1                 (0x2UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR13_USART6SEL_2                 (0x4UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR13_UART7SEL_Pos                (24U)
+#define RCC_CCIPR13_UART7SEL_Msk                (0x7UL << RCC_CCIPR13_UART7SEL_Pos)                /*!< 0x07000000 */
+#define RCC_CCIPR13_UART7SEL                    RCC_CCIPR13_UART7SEL_Msk                          /*!< Source selection for the UART7 kernel clock */
+#define RCC_CCIPR13_UART7SEL_0                  (0x1UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR13_UART7SEL_1                  (0x2UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x02000000 */
+#define RCC_CCIPR13_UART7SEL_2                  (0x4UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x04000000 */
+#define RCC_CCIPR13_UART8SEL_Pos                (28U)
+#define RCC_CCIPR13_UART8SEL_Msk                (0x7UL << RCC_CCIPR13_UART8SEL_Pos)                /*!< 0x70000000 */
+#define RCC_CCIPR13_UART8SEL                    RCC_CCIPR13_UART8SEL_Msk                          /*!< Source selection for the UART8 kernel clock */
+#define RCC_CCIPR13_UART8SEL_0                  (0x1UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x10000000 */
+#define RCC_CCIPR13_UART8SEL_1                  (0x2UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x20000000 */
+#define RCC_CCIPR13_UART8SEL_2                  (0x4UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x40000000 */
+
+/*****************  Bit definition for RCC_CCIPR14 register  ******************/
+#define RCC_CCIPR14_UART9SEL_Pos                (0U)
+#define RCC_CCIPR14_UART9SEL_Msk                (0x7UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000007 */
+#define RCC_CCIPR14_UART9SEL                    RCC_CCIPR14_UART9SEL_Msk                          /*!< Source selection for the UART9 kernel clock */
+#define RCC_CCIPR14_UART9SEL_0                  (0x1UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR14_UART9SEL_1                  (0x2UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR14_UART9SEL_2                  (0x4UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000004 */
+#define RCC_CCIPR14_USART10SEL_Pos              (4U)
+#define RCC_CCIPR14_USART10SEL_Msk              (0x7UL << RCC_CCIPR14_USART10SEL_Pos)              /*!< 0x00000070 */
+#define RCC_CCIPR14_USART10SEL                  RCC_CCIPR14_USART10SEL_Msk                        /*!< Source selection for the USART10 kernel clock */
+#define RCC_CCIPR14_USART10SEL_0                (0x1UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000010 */
+#define RCC_CCIPR14_USART10SEL_1                (0x2UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000020 */
+#define RCC_CCIPR14_USART10SEL_2                (0x4UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000040 */
+#define RCC_CCIPR14_LPUART1SEL_Pos              (8U)
+#define RCC_CCIPR14_LPUART1SEL_Msk              (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos)              /*!< 0x00000700 */
+#define RCC_CCIPR14_LPUART1SEL                  RCC_CCIPR14_LPUART1SEL_Msk                        /*!< Source selection for the LPUART1 kernel clock */
+#define RCC_CCIPR14_LPUART1SEL_0                (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000100 */
+#define RCC_CCIPR14_LPUART1SEL_1                (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000200 */
+#define RCC_CCIPR14_LPUART1SEL_2                (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000400 */
+
+/*****************  Bit definition for RCC_MISCRSTR register  *****************/
+#define RCC_MISCRSTR_DBGRST_Pos                 (0U)
+#define RCC_MISCRSTR_DBGRST_Msk                 (0x1UL << RCC_MISCRSTR_DBGRST_Pos)    /*!< 0x00000001 */
+#define RCC_MISCRSTR_DBGRST                     RCC_MISCRSTR_DBGRST_Msk              /*!< DBG reset */
+#define RCC_MISCRSTR_XSPIPHY1RST_Pos            (4U)
+#define RCC_MISCRSTR_XSPIPHY1RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */
+#define RCC_MISCRSTR_XSPIPHY1RST                RCC_MISCRSTR_XSPIPHY1RST_Msk         /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTR_XSPIPHY2RST_Pos            (5U)
+#define RCC_MISCRSTR_XSPIPHY2RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */
+#define RCC_MISCRSTR_XSPIPHY2RST                RCC_MISCRSTR_XSPIPHY2RST_Msk         /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTR_SDMMC1DLLRST_Pos           (7U)
+#define RCC_MISCRSTR_SDMMC1DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos)  /*!< 0x00000080 */
+#define RCC_MISCRSTR_SDMMC1DLLRST               RCC_MISCRSTR_SDMMC1DLLRST_Msk        /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTR_SDMMC2DLLRST_Pos           (8U)
+#define RCC_MISCRSTR_SDMMC2DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos)  /*!< 0x00000100 */
+#define RCC_MISCRSTR_SDMMC2DLLRST               RCC_MISCRSTR_SDMMC2DLLRST_Msk        /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTR register  ******************/
+#define RCC_MEMRSTR_AXISRAM3RST_Pos             (0U)
+#define RCC_MEMRSTR_AXISRAM3RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */
+#define RCC_MEMRSTR_AXISRAM3RST                 RCC_MEMRSTR_AXISRAM3RST_Msk          /*!< AXISRAM3 reset */
+#define RCC_MEMRSTR_AXISRAM4RST_Pos             (1U)
+#define RCC_MEMRSTR_AXISRAM4RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */
+#define RCC_MEMRSTR_AXISRAM4RST                 RCC_MEMRSTR_AXISRAM4RST_Msk          /*!< AXISRAM4 reset */
+#define RCC_MEMRSTR_AXISRAM5RST_Pos             (2U)
+#define RCC_MEMRSTR_AXISRAM5RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */
+#define RCC_MEMRSTR_AXISRAM5RST                 RCC_MEMRSTR_AXISRAM5RST_Msk          /*!< AXISRAM5 reset */
+#define RCC_MEMRSTR_AXISRAM6RST_Pos             (3U)
+#define RCC_MEMRSTR_AXISRAM6RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */
+#define RCC_MEMRSTR_AXISRAM6RST                 RCC_MEMRSTR_AXISRAM6RST_Msk          /*!< AXISRAM6 reset */
+#define RCC_MEMRSTR_AHBSRAM1RST_Pos             (4U)
+#define RCC_MEMRSTR_AHBSRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */
+#define RCC_MEMRSTR_AHBSRAM1RST                 RCC_MEMRSTR_AHBSRAM1RST_Msk          /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTR_AHBSRAM2RST_Pos             (5U)
+#define RCC_MEMRSTR_AHBSRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */
+#define RCC_MEMRSTR_AHBSRAM2RST                 RCC_MEMRSTR_AHBSRAM2RST_Msk          /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTR_AXISRAM1RST_Pos             (7U)
+#define RCC_MEMRSTR_AXISRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */
+#define RCC_MEMRSTR_AXISRAM1RST                 RCC_MEMRSTR_AXISRAM1RST_Msk          /*!< AXISRAM1 reset */
+#define RCC_MEMRSTR_AXISRAM2RST_Pos             (8U)
+#define RCC_MEMRSTR_AXISRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */
+#define RCC_MEMRSTR_AXISRAM2RST                 RCC_MEMRSTR_AXISRAM2RST_Msk          /*!< AXISRAM2 reset */
+#define RCC_MEMRSTR_FLEXRAMRST_Pos              (9U)
+#define RCC_MEMRSTR_FLEXRAMRST_Msk              (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTR_FLEXRAMRST                  RCC_MEMRSTR_FLEXRAMRST_Msk           /*!< FLEXRAM reset */
+#define RCC_MEMRSTR_VENCRAMRST_Pos              (11U)
+#define RCC_MEMRSTR_VENCRAMRST_Msk              (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTR_VENCRAMRST                  RCC_MEMRSTR_VENCRAMRST_Msk           /*!< VENCRAM reset */
+#define RCC_MEMRSTR_BOOTROMRST_Pos              (12U)
+#define RCC_MEMRSTR_BOOTROMRST_Msk              (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTR_BOOTROMRST                  RCC_MEMRSTR_BOOTROMRST_Msk           /*!< Boot ROM reset */
+
+/*****************  Bit definition for RCC_AHB1RSTR register  *****************/
+#define RCC_AHB1RSTR_GPDMA1RST_Pos              (4U)
+#define RCC_AHB1RSTR_GPDMA1RST_Msk              (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPDMA1RST                  RCC_AHB1RSTR_GPDMA1RST_Msk           /*!< GPDMA1 reset */
+#define RCC_AHB1RSTR_ADC12RST_Pos               (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk               (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                   RCC_AHB1RSTR_ADC12RST_Msk            /*!< ADC12 reset */
+
+/*****************  Bit definition for RCC_AHB2RSTR register  *****************/
+#define RCC_AHB2RSTR_RAMCFGRST_Pos              (12U)
+#define RCC_AHB2RSTR_RAMCFGRST_Msk              (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_RAMCFGRST                  RCC_AHB2RSTR_RAMCFGRST_Msk           /*!< RAMCFG reset */
+#define RCC_AHB2RSTR_MDF1RST_Pos                (16U)
+#define RCC_AHB2RSTR_MDF1RST_Msk                (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2RSTR_MDF1RST                    RCC_AHB2RSTR_MDF1RST_Msk             /*!< MDF1 reset */
+#define RCC_AHB2RSTR_ADF1RST_Pos                (17U)
+#define RCC_AHB2RSTR_ADF1RST_Msk                (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2RSTR_ADF1RST                    RCC_AHB2RSTR_ADF1RST_Msk             /*!< ADF1 reset */
+
+/*****************  Bit definition for RCC_AHB3RSTR register  *****************/
+#define RCC_AHB3RSTR_RNGRST_Pos                 (0U)
+#define RCC_AHB3RSTR_RNGRST_Msk                 (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3RSTR_RNGRST                     RCC_AHB3RSTR_RNGRST_Msk              /*!< RNG reset */
+#define RCC_AHB3RSTR_HASHRST_Pos                (1U)
+#define RCC_AHB3RSTR_HASHRST_Msk                (0x1UL << RCC_AHB3RSTR_HASHRST_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3RSTR_HASHRST                    RCC_AHB3RSTR_HASHRST_Msk             /*!< HASH reset */
+#define RCC_AHB3RSTR_PKARST_Pos                 (8U)
+#define RCC_AHB3RSTR_PKARST_Msk                 (0x1UL << RCC_AHB3RSTR_PKARST_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3RSTR_PKARST                     RCC_AHB3RSTR_PKARST_Msk              /*!< PKA reset */
+#define RCC_AHB3RSTR_IACRST_Pos                 (10U)
+#define RCC_AHB3RSTR_IACRST_Msk                 (0x1UL << RCC_AHB3RSTR_IACRST_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3RSTR_IACRST                     RCC_AHB3RSTR_IACRST_Msk              /*!< IAC reset */
+
+/*****************  Bit definition for RCC_AHB4RSTR register  *****************/
+#define RCC_AHB4RSTR_GPIOARST_Pos               (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                   RCC_AHB4RSTR_GPIOARST_Msk            /*!< GPIO A reset */
+#define RCC_AHB4RSTR_GPIOBRST_Pos               (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                   RCC_AHB4RSTR_GPIOBRST_Msk            /*!< GPIO B reset */
+#define RCC_AHB4RSTR_GPIOCRST_Pos               (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                   RCC_AHB4RSTR_GPIOCRST_Msk            /*!< GPIO C reset */
+#define RCC_AHB4RSTR_GPIODRST_Pos               (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                   RCC_AHB4RSTR_GPIODRST_Msk            /*!< GPIO D reset */
+#define RCC_AHB4RSTR_GPIOERST_Pos               (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                   RCC_AHB4RSTR_GPIOERST_Msk            /*!< GPIO E reset */
+#define RCC_AHB4RSTR_GPIOFRST_Pos               (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                   RCC_AHB4RSTR_GPIOFRST_Msk            /*!< GPIO F reset */
+#define RCC_AHB4RSTR_GPIOGRST_Pos               (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                   RCC_AHB4RSTR_GPIOGRST_Msk            /*!< GPIO G reset */
+#define RCC_AHB4RSTR_GPIOHRST_Pos               (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                   RCC_AHB4RSTR_GPIOHRST_Msk            /*!< GPIO H reset */
+#define RCC_AHB4RSTR_GPIONRST_Pos               (13U)
+#define RCC_AHB4RSTR_GPIONRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4RSTR_GPIONRST                   RCC_AHB4RSTR_GPIONRST_Msk            /*!< GPIO N reset */
+#define RCC_AHB4RSTR_GPIOORST_Pos               (14U)
+#define RCC_AHB4RSTR_GPIOORST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4RSTR_GPIOORST                   RCC_AHB4RSTR_GPIOORST_Msk            /*!< GPIO O reset */
+#define RCC_AHB4RSTR_GPIOPRST_Pos               (15U)
+#define RCC_AHB4RSTR_GPIOPRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4RSTR_GPIOPRST                   RCC_AHB4RSTR_GPIOPRST_Msk            /*!< GPIO P reset */
+#define RCC_AHB4RSTR_GPIOQRST_Pos               (16U)
+#define RCC_AHB4RSTR_GPIOQRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4RSTR_GPIOQRST                   RCC_AHB4RSTR_GPIOQRST_Msk            /*!< GPIO Q reset */
+#define RCC_AHB4RSTR_PWRRST_Pos                 (18U)
+#define RCC_AHB4RSTR_PWRRST_Msk                 (0x1UL << RCC_AHB4RSTR_PWRRST_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4RSTR_PWRRST                     RCC_AHB4RSTR_PWRRST_Msk              /*!< PWR reset */
+#define RCC_AHB4RSTR_CRCRST_Pos                 (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                 (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                     RCC_AHB4RSTR_CRCRST_Msk              /*!< CRC reset */
+
+/*****************  Bit definition for RCC_AHB5RSTR register  *****************/
+#define RCC_AHB5RSTR_HPDMA1RST_Pos              (0U)
+#define RCC_AHB5RSTR_HPDMA1RST_Msk              (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTR_HPDMA1RST                  RCC_AHB5RSTR_HPDMA1RST_Msk           /*!< HPDMA1 reset */
+#define RCC_AHB5RSTR_DMA2DRST_Pos               (1U)
+#define RCC_AHB5RSTR_DMA2DRST_Msk               (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5RSTR_DMA2DRST                   RCC_AHB5RSTR_DMA2DRST_Msk            /*!< DMA2D reset */
+#define RCC_AHB5RSTR_JPEGRST_Pos                (3U)
+#define RCC_AHB5RSTR_JPEGRST_Msk                (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5RSTR_JPEGRST                    RCC_AHB5RSTR_JPEGRST_Msk             /*!< JPEG reset */
+#define RCC_AHB5RSTR_FMCRST_Pos                 (4U)
+#define RCC_AHB5RSTR_FMCRST_Msk                 (0x1UL << RCC_AHB5RSTR_FMCRST_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5RSTR_FMCRST                     RCC_AHB5RSTR_FMCRST_Msk              /*!< FMC reset */
+#define RCC_AHB5RSTR_XSPI1RST_Pos               (5U)
+#define RCC_AHB5RSTR_XSPI1RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5RSTR_XSPI1RST                   RCC_AHB5RSTR_XSPI1RST_Msk            /*!< XSPI1 reset */
+#define RCC_AHB5RSTR_PSSIRST_Pos                (6U)
+#define RCC_AHB5RSTR_PSSIRST_Msk                (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5RSTR_PSSIRST                    RCC_AHB5RSTR_PSSIRST_Msk             /*!< PSSI reset */
+#define RCC_AHB5RSTR_SDMMC2RST_Pos              (7U)
+#define RCC_AHB5RSTR_SDMMC2RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTR_SDMMC2RST                  RCC_AHB5RSTR_SDMMC2RST_Msk           /*!< SDMMC2 reset */
+#define RCC_AHB5RSTR_SDMMC1RST_Pos              (8U)
+#define RCC_AHB5RSTR_SDMMC1RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTR_SDMMC1RST                  RCC_AHB5RSTR_SDMMC1RST_Msk           /*!< SDMMC1 reset */
+#define RCC_AHB5RSTR_XSPI2RST_Pos               (12U)
+#define RCC_AHB5RSTR_XSPI2RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5RSTR_XSPI2RST                   RCC_AHB5RSTR_XSPI2RST_Msk            /*!< XSPI2 reset */
+#define RCC_AHB5RSTR_XSPIMRST_Pos               (13U)
+#define RCC_AHB5RSTR_XSPIMRST_Msk               (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5RSTR_XSPIMRST                   RCC_AHB5RSTR_XSPIMRST_Msk            /*!< XSPIM reset */
+#define RCC_AHB5RSTR_XSPI3RST_Pos               (17U)
+#define RCC_AHB5RSTR_XSPI3RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5RSTR_XSPI3RST                   RCC_AHB5RSTR_XSPI3RST_Msk            /*!< XSPI3 reset */
+#define RCC_AHB5RSTR_GFXMMURST_Pos              (19U)
+#define RCC_AHB5RSTR_GFXMMURST_Msk              (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTR_GFXMMURST                  RCC_AHB5RSTR_GFXMMURST_Msk           /*!< GFXMMU reset */
+#define RCC_AHB5RSTR_GPU2DRST_Pos               (20U)
+#define RCC_AHB5RSTR_GPU2DRST_Msk               (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5RSTR_GPU2DRST                   RCC_AHB5RSTR_GPU2DRST_Msk            /*!< GPU2D reset */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos          (23U)
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST              RCC_AHB5RSTR_OTG1PHYCTLRST_Msk       /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos          (24U)
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST              RCC_AHB5RSTR_OTG2PHYCTLRST_Msk       /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTR_ETH1RST_Pos                (25U)
+#define RCC_AHB5RSTR_ETH1RST_Msk                (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5RSTR_ETH1RST                    RCC_AHB5RSTR_ETH1RST_Msk             /*!< ETH1 reset */
+#define RCC_AHB5RSTR_OTG1RST_Pos                (26U)
+#define RCC_AHB5RSTR_OTG1RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5RSTR_OTG1RST                    RCC_AHB5RSTR_OTG1RST_Msk             /*!< OTG1 reset */
+#define RCC_AHB5RSTR_OTGPHY1RST_Pos             (27U)
+#define RCC_AHB5RSTR_OTGPHY1RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */
+#define RCC_AHB5RSTR_OTGPHY1RST                 RCC_AHB5RSTR_OTGPHY1RST_Msk          /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTR_OTGPHY2RST_Pos             (28U)
+#define RCC_AHB5RSTR_OTGPHY2RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */
+#define RCC_AHB5RSTR_OTGPHY2RST                 RCC_AHB5RSTR_OTGPHY2RST_Msk          /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTR_OTG2RST_Pos                (29U)
+#define RCC_AHB5RSTR_OTG2RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5RSTR_OTG2RST                    RCC_AHB5RSTR_OTG2RST_Msk             /*!< OTG2 reset */
+
+/****************  Bit definition for RCC_APB1RSTR1 register  *****************/
+#define RCC_APB1RSTR1_TIM2RST_Pos               (0U)
+#define RCC_APB1RSTR1_TIM2RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                   RCC_APB1RSTR1_TIM2RST_Msk            /*!< TIM2 reset */
+#define RCC_APB1RSTR1_TIM3RST_Pos               (1U)
+#define RCC_APB1RSTR1_TIM3RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                   RCC_APB1RSTR1_TIM3RST_Msk            /*!< TIM3 reset */
+#define RCC_APB1RSTR1_TIM4RST_Pos               (2U)
+#define RCC_APB1RSTR1_TIM4RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)  /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                   RCC_APB1RSTR1_TIM4RST_Msk            /*!< TIM4 reset */
+#define RCC_APB1RSTR1_TIM5RST_Pos               (3U)
+#define RCC_APB1RSTR1_TIM5RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)  /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                   RCC_APB1RSTR1_TIM5RST_Msk            /*!< TIM5 reset */
+#define RCC_APB1RSTR1_TIM6RST_Pos               (4U)
+#define RCC_APB1RSTR1_TIM6RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)  /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                   RCC_APB1RSTR1_TIM6RST_Msk            /*!< TIM6 reset */
+#define RCC_APB1RSTR1_TIM7RST_Pos               (5U)
+#define RCC_APB1RSTR1_TIM7RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                   RCC_APB1RSTR1_TIM7RST_Msk            /*!< TIM7 reset */
+#define RCC_APB1RSTR1_TIM12RST_Pos              (6U)
+#define RCC_APB1RSTR1_TIM12RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR1_TIM12RST                  RCC_APB1RSTR1_TIM12RST_Msk           /*!< TIM12 reset */
+#define RCC_APB1RSTR1_TIM13RST_Pos              (7U)
+#define RCC_APB1RSTR1_TIM13RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR1_TIM13RST                  RCC_APB1RSTR1_TIM13RST_Msk           /*!< TIM13 reset */
+#define RCC_APB1RSTR1_TIM14RST_Pos              (8U)
+#define RCC_APB1RSTR1_TIM14RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR1_TIM14RST                  RCC_APB1RSTR1_TIM14RST_Msk           /*!< TIM14 reset */
+#define RCC_APB1RSTR1_LPTIM1RST_Pos             (9U)
+#define RCC_APB1RSTR1_LPTIM1RST_Msk             (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */
+#define RCC_APB1RSTR1_LPTIM1RST                 RCC_APB1RSTR1_LPTIM1RST_Msk          /*!< LPTIM1 reset */
+#define RCC_APB1RSTR1_WWDGRST_Pos               (11U)
+#define RCC_APB1RSTR1_WWDGRST_Msk               (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos)  /*!< 0x00000800 */
+#define RCC_APB1RSTR1_WWDGRST                   RCC_APB1RSTR1_WWDGRST_Msk            /*!< WWDG reset */
+#define RCC_APB1RSTR1_TIM10RST_Pos              (12U)
+#define RCC_APB1RSTR1_TIM10RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTR1_TIM10RST                  RCC_APB1RSTR1_TIM10RST_Msk           /*!< TIM10 reset */
+#define RCC_APB1RSTR1_TIM11RST_Pos              (13U)
+#define RCC_APB1RSTR1_TIM11RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTR1_TIM11RST                  RCC_APB1RSTR1_TIM11RST_Msk           /*!< TIM11 reset */
+#define RCC_APB1RSTR1_SPI2RST_Pos               (14U)
+#define RCC_APB1RSTR1_SPI2RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                   RCC_APB1RSTR1_SPI2RST_Msk            /*!< SPI2 reset */
+#define RCC_APB1RSTR1_SPI3RST_Pos               (15U)
+#define RCC_APB1RSTR1_SPI3RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                   RCC_APB1RSTR1_SPI3RST_Msk            /*!< SPI3 reset */
+#define RCC_APB1RSTR1_SPDIFRX1RST_Pos           (16U)
+#define RCC_APB1RSTR1_SPDIFRX1RST_Msk           (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB1RSTR1_SPDIFRX1RST               RCC_APB1RSTR1_SPDIFRX1RST_Msk        /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTR1_USART2RST_Pos             (17U)
+#define RCC_APB1RSTR1_USART2RST_Msk             (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST                 RCC_APB1RSTR1_USART2RST_Msk          /*!< USART2 reset */
+#define RCC_APB1RSTR1_USART3RST_Pos             (18U)
+#define RCC_APB1RSTR1_USART3RST_Msk             (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST                 RCC_APB1RSTR1_USART3RST_Msk          /*!< USART3 reset */
+#define RCC_APB1RSTR1_UART4RST_Pos              (19U)
+#define RCC_APB1RSTR1_UART4RST_Msk              (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST                  RCC_APB1RSTR1_UART4RST_Msk           /*!< UART4 reset */
+#define RCC_APB1RSTR1_UART5RST_Pos              (20U)
+#define RCC_APB1RSTR1_UART5RST_Msk              (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST                  RCC_APB1RSTR1_UART5RST_Msk           /*!< UART5 reset */
+#define RCC_APB1RSTR1_I2C1RST_Pos               (21U)
+#define RCC_APB1RSTR1_I2C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                   RCC_APB1RSTR1_I2C1RST_Msk            /*!< I2C1 reset */
+#define RCC_APB1RSTR1_I2C2RST_Pos               (22U)
+#define RCC_APB1RSTR1_I2C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                   RCC_APB1RSTR1_I2C2RST_Msk            /*!< I2C2 reset */
+#define RCC_APB1RSTR1_I2C3RST_Pos               (23U)
+#define RCC_APB1RSTR1_I2C3RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                   RCC_APB1RSTR1_I2C3RST_Msk            /*!< I2C3 reset */
+#define RCC_APB1RSTR1_I3C1RST_Pos               (24U)
+#define RCC_APB1RSTR1_I3C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos)  /*!< 0x01000000 */
+#define RCC_APB1RSTR1_I3C1RST                   RCC_APB1RSTR1_I3C1RST_Msk            /*!< I3C1 reset */
+#define RCC_APB1RSTR1_I3C2RST_Pos               (25U)
+#define RCC_APB1RSTR1_I3C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos)  /*!< 0x02000000 */
+#define RCC_APB1RSTR1_I3C2RST                   RCC_APB1RSTR1_I3C2RST_Msk            /*!< I3C2 reset */
+#define RCC_APB1RSTR1_UART7RST_Pos              (30U)
+#define RCC_APB1RSTR1_UART7RST_Msk              (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_UART7RST                  RCC_APB1RSTR1_UART7RST_Msk           /*!< UART7 reset */
+#define RCC_APB1RSTR1_UART8RST_Pos              (31U)
+#define RCC_APB1RSTR1_UART8RST_Msk              (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_UART8RST                  RCC_APB1RSTR1_UART8RST_Msk           /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTR2 register  *****************/
+#define RCC_APB1RSTR2_MDIOSRST_Pos              (5U)
+#define RCC_APB1RSTR2_MDIOSRST_Msk              (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_MDIOSRST                  RCC_APB1RSTR2_MDIOSRST_Msk            /*!< MDIOS reset */
+#define RCC_APB1RSTR2_FDCANRST_Pos              (8U)
+#define RCC_APB1RSTR2_FDCANRST_Msk              (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR2_FDCANRST                  RCC_APB1RSTR2_FDCANRST_Msk            /*!< FDCAN reset */
+#define RCC_APB1RSTR2_UCPD1RST_Pos              (18U)
+#define RCC_APB1RSTR2_UCPD1RST_Msk              (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR2_UCPD1RST                  RCC_APB1RSTR2_UCPD1RST_Msk            /*!< UCPD1 reset */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define RCC_APB2RSTR_TIM1RST_Pos                (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk                (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)   /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                    RCC_APB2RSTR_TIM1RST_Msk             /*!< TIM1 reset */
+#define RCC_APB2RSTR_TIM8RST_Pos                (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk                (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)   /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                    RCC_APB2RSTR_TIM8RST_Msk             /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST_Pos              (4U)
+#define RCC_APB2RSTR_USART1RST_Msk              (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                  RCC_APB2RSTR_USART1RST_Msk           /*!< USART1 reset */
+#define RCC_APB2RSTR_USART6RST_Pos              (5U)
+#define RCC_APB2RSTR_USART6RST_Msk              (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                  RCC_APB2RSTR_USART6RST_Msk           /*!< USART6 reset */
+#define RCC_APB2RSTR_UART9RST_Pos               (6U)
+#define RCC_APB2RSTR_UART9RST_Msk               (0x1UL << RCC_APB2RSTR_UART9RST_Pos)  /*!< 0x00000040 */
+#define RCC_APB2RSTR_UART9RST                   RCC_APB2RSTR_UART9RST_Msk            /*!< UART9 reset */
+#define RCC_APB2RSTR_USART10RST_Pos             (7U)
+#define RCC_APB2RSTR_USART10RST_Msk             (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */
+#define RCC_APB2RSTR_USART10RST                 RCC_APB2RSTR_USART10RST_Msk          /*!< USART10 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos                (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk                (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)   /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                    RCC_APB2RSTR_SPI1RST_Msk             /*!< SPI1 reset */
+#define RCC_APB2RSTR_SPI4RST_Pos                (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk                (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)   /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                    RCC_APB2RSTR_SPI4RST_Msk             /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM18RST_Pos               (15U)
+#define RCC_APB2RSTR_TIM18RST_Msk               (0x1UL << RCC_APB2RSTR_TIM18RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB2RSTR_TIM18RST                   RCC_APB2RSTR_TIM18RST_Msk            /*!< TIM18 reset */
+#define RCC_APB2RSTR_TIM15RST_Pos               (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk               (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                   RCC_APB2RSTR_TIM15RST_Msk            /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST_Pos               (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk               (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)  /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                   RCC_APB2RSTR_TIM16RST_Msk            /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST_Pos               (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk               (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)  /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                   RCC_APB2RSTR_TIM17RST_Msk            /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM9RST_Pos                (19U)
+#define RCC_APB2RSTR_TIM9RST_Msk                (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)   /*!< 0x00080000 */
+#define RCC_APB2RSTR_TIM9RST                    RCC_APB2RSTR_TIM9RST_Msk             /*!< TIM9 reset */
+#define RCC_APB2RSTR_SPI5RST_Pos                (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk                (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)   /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                    RCC_APB2RSTR_SPI5RST_Msk             /*!< SPI5 reset */
+#define RCC_APB2RSTR_SAI1RST_Pos                (21U)
+#define RCC_APB2RSTR_SAI1RST_Msk                (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)   /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                    RCC_APB2RSTR_SAI1RST_Msk             /*!< SAI1 reset */
+#define RCC_APB2RSTR_SAI2RST_Pos                (22U)
+#define RCC_APB2RSTR_SAI2RST_Msk                (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)   /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                    RCC_APB2RSTR_SAI2RST_Msk             /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTR1 register  *****************/
+#define RCC_APB4RSTR1_HDPRST_Pos                (2U)
+#define RCC_APB4RSTR1_HDPRST_Msk                (0x1UL << RCC_APB4RSTR1_HDPRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR1_HDPRST                    RCC_APB4RSTR1_HDPRST_Msk             /*!< HDP reset */
+#define RCC_APB4RSTR1_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR1_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR1_LPUART1RST                RCC_APB4RSTR1_LPUART1RST_Msk         /*!< LPUART1 reset */
+#define RCC_APB4RSTR1_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR1_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB4RSTR1_SPI6RST                   RCC_APB4RSTR1_SPI6RST_Msk            /*!< SPI6 reset */
+#define RCC_APB4RSTR1_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR1_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos)  /*!< 0x00000080 */
+#define RCC_APB4RSTR1_I2C4RST                   RCC_APB4RSTR1_I2C4RST_Msk            /*!< I2C4 reset */
+#define RCC_APB4RSTR1_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR1_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */
+#define RCC_APB4RSTR1_LPTIM2RST                 RCC_APB4RSTR1_LPTIM2RST_Msk          /*!< LPTIM2 reset */
+#define RCC_APB4RSTR1_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR1_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */
+#define RCC_APB4RSTR1_LPTIM3RST                 RCC_APB4RSTR1_LPTIM3RST_Msk          /*!< LPTIM3 reset */
+#define RCC_APB4RSTR1_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR1_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */
+#define RCC_APB4RSTR1_LPTIM4RST                 RCC_APB4RSTR1_LPTIM4RST_Msk          /*!< LPTIM4 reset */
+#define RCC_APB4RSTR1_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR1_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */
+#define RCC_APB4RSTR1_LPTIM5RST                 RCC_APB4RSTR1_LPTIM5RST_Msk          /*!< LPTIM5 reset */
+#define RCC_APB4RSTR1_VREFBUFRST_Pos            (15U)
+#define RCC_APB4RSTR1_VREFBUFRST_Msk            (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR1_VREFBUFRST                RCC_APB4RSTR1_VREFBUFRST_Msk         /*!< VREFBUF reset */
+#define RCC_APB4RSTR1_RTCRST_Pos                (16U)
+#define RCC_APB4RSTR1_RTCRST_Msk                (0x1UL << RCC_APB4RSTR1_RTCRST_Pos)   /*!< 0x00010000 */
+#define RCC_APB4RSTR1_RTCRST                    RCC_APB4RSTR1_RTCRST_Msk             /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTR2 register  *****************/
+#define RCC_APB4RSTR2_SYSCFGRST_Pos             (0U)
+#define RCC_APB4RSTR2_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */
+#define RCC_APB4RSTR2_SYSCFGRST                 RCC_APB4RSTR2_SYSCFGRST_Msk          /*!< SYSCFG reset */
+#define RCC_APB4RSTR2_DTSRST_Pos                (2U)
+#define RCC_APB4RSTR2_DTSRST_Msk                (0x1UL << RCC_APB4RSTR2_DTSRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR2_DTSRST                    RCC_APB4RSTR2_DTSRST_Msk             /*!< DTS reset */
+
+/*****************  Bit definition for RCC_APB5RSTR register  *****************/
+#define RCC_APB5RSTR_LTDCRST_Pos                (1U)
+#define RCC_APB5RSTR_LTDCRST_Msk                (0x1UL << RCC_APB5RSTR_LTDCRST_Pos)   /*!< 0x00000002 */
+#define RCC_APB5RSTR_LTDCRST                    RCC_APB5RSTR_LTDCRST_Msk             /*!< LTDC reset */
+#define RCC_APB5RSTR_DCMIPPRST_Pos              (2U)
+#define RCC_APB5RSTR_DCMIPPRST_Msk              (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTR_DCMIPPRST                  RCC_APB5RSTR_DCMIPPRST_Msk           /*!< DCMIPP reset */
+#define RCC_APB5RSTR_GFXTIMRST_Pos              (4U)
+#define RCC_APB5RSTR_GFXTIMRST_Msk              (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTR_GFXTIMRST                  RCC_APB5RSTR_GFXTIMRST_Msk           /*!< GFXTIM reset */
+#define RCC_APB5RSTR_VENCRST_Pos                (5U)
+#define RCC_APB5RSTR_VENCRST_Msk                (0x1UL << RCC_APB5RSTR_VENCRST_Pos)   /*!< 0x00000020 */
+#define RCC_APB5RSTR_VENCRST                    RCC_APB5RSTR_VENCRST_Msk             /*!< VENC reset */
+#define RCC_APB5RSTR_CSIRST_Pos                 (6U)
+#define RCC_APB5RSTR_CSIRST_Msk                 (0x1UL << RCC_APB5RSTR_CSIRST_Pos)    /*!< 0x00000040 */
+#define RCC_APB5RSTR_CSIRST                     RCC_APB5RSTR_CSIRST_Msk              /*!< CSI reset */
+
+/******************  Bit definition for RCC_DIVENR register  ******************/
+#define RCC_DIVENR_IC1EN_Pos                    (0U)
+#define RCC_DIVENR_IC1EN_Msk                    (0x1UL << RCC_DIVENR_IC1EN_Pos)       /*!< 0x00000001 */
+#define RCC_DIVENR_IC1EN                        RCC_DIVENR_IC1EN_Msk                 /*!< IC1 enable */
+#define RCC_DIVENR_IC2EN_Pos                    (1U)
+#define RCC_DIVENR_IC2EN_Msk                    (0x1UL << RCC_DIVENR_IC2EN_Pos)       /*!< 0x00000002 */
+#define RCC_DIVENR_IC2EN                        RCC_DIVENR_IC2EN_Msk                 /*!< IC2 enable */
+#define RCC_DIVENR_IC3EN_Pos                    (2U)
+#define RCC_DIVENR_IC3EN_Msk                    (0x1UL << RCC_DIVENR_IC3EN_Pos)       /*!< 0x00000004 */
+#define RCC_DIVENR_IC3EN                        RCC_DIVENR_IC3EN_Msk                 /*!< IC3 enable */
+#define RCC_DIVENR_IC4EN_Pos                    (3U)
+#define RCC_DIVENR_IC4EN_Msk                    (0x1UL << RCC_DIVENR_IC4EN_Pos)       /*!< 0x00000008 */
+#define RCC_DIVENR_IC4EN                        RCC_DIVENR_IC4EN_Msk                 /*!< IC4 enable */
+#define RCC_DIVENR_IC5EN_Pos                    (4U)
+#define RCC_DIVENR_IC5EN_Msk                    (0x1UL << RCC_DIVENR_IC5EN_Pos)       /*!< 0x00000010 */
+#define RCC_DIVENR_IC5EN                        RCC_DIVENR_IC5EN_Msk                 /*!< IC5 enable */
+#define RCC_DIVENR_IC6EN_Pos                    (5U)
+#define RCC_DIVENR_IC6EN_Msk                    (0x1UL << RCC_DIVENR_IC6EN_Pos)       /*!< 0x00000020 */
+#define RCC_DIVENR_IC6EN                        RCC_DIVENR_IC6EN_Msk                 /*!< IC6 enable */
+#define RCC_DIVENR_IC7EN_Pos                    (6U)
+#define RCC_DIVENR_IC7EN_Msk                    (0x1UL << RCC_DIVENR_IC7EN_Pos)       /*!< 0x00000040 */
+#define RCC_DIVENR_IC7EN                        RCC_DIVENR_IC7EN_Msk                 /*!< IC7 enable */
+#define RCC_DIVENR_IC8EN_Pos                    (7U)
+#define RCC_DIVENR_IC8EN_Msk                    (0x1UL << RCC_DIVENR_IC8EN_Pos)       /*!< 0x00000080 */
+#define RCC_DIVENR_IC8EN                        RCC_DIVENR_IC8EN_Msk                 /*!< IC8 enable */
+#define RCC_DIVENR_IC9EN_Pos                    (8U)
+#define RCC_DIVENR_IC9EN_Msk                    (0x1UL << RCC_DIVENR_IC9EN_Pos)       /*!< 0x00000100 */
+#define RCC_DIVENR_IC9EN                        RCC_DIVENR_IC9EN_Msk                 /*!< IC9 enable */
+#define RCC_DIVENR_IC10EN_Pos                   (9U)
+#define RCC_DIVENR_IC10EN_Msk                   (0x1UL << RCC_DIVENR_IC10EN_Pos)      /*!< 0x00000200 */
+#define RCC_DIVENR_IC10EN                       RCC_DIVENR_IC10EN_Msk                /*!< IC10 enable */
+#define RCC_DIVENR_IC11EN_Pos                   (10U)
+#define RCC_DIVENR_IC11EN_Msk                   (0x1UL << RCC_DIVENR_IC11EN_Pos)      /*!< 0x00000400 */
+#define RCC_DIVENR_IC11EN                       RCC_DIVENR_IC11EN_Msk                /*!< IC11 enable */
+#define RCC_DIVENR_IC12EN_Pos                   (11U)
+#define RCC_DIVENR_IC12EN_Msk                   (0x1UL << RCC_DIVENR_IC12EN_Pos)      /*!< 0x00000800 */
+#define RCC_DIVENR_IC12EN                       RCC_DIVENR_IC12EN_Msk                /*!< IC12 enable */
+#define RCC_DIVENR_IC13EN_Pos                   (12U)
+#define RCC_DIVENR_IC13EN_Msk                   (0x1UL << RCC_DIVENR_IC13EN_Pos)      /*!< 0x00001000 */
+#define RCC_DIVENR_IC13EN                       RCC_DIVENR_IC13EN_Msk                /*!< IC13 enable */
+#define RCC_DIVENR_IC14EN_Pos                   (13U)
+#define RCC_DIVENR_IC14EN_Msk                   (0x1UL << RCC_DIVENR_IC14EN_Pos)      /*!< 0x00002000 */
+#define RCC_DIVENR_IC14EN                       RCC_DIVENR_IC14EN_Msk                /*!< IC14 enable */
+#define RCC_DIVENR_IC15EN_Pos                   (14U)
+#define RCC_DIVENR_IC15EN_Msk                   (0x1UL << RCC_DIVENR_IC15EN_Pos)      /*!< 0x00004000 */
+#define RCC_DIVENR_IC15EN                       RCC_DIVENR_IC15EN_Msk                /*!< IC15 enable */
+#define RCC_DIVENR_IC16EN_Pos                   (15U)
+#define RCC_DIVENR_IC16EN_Msk                   (0x1UL << RCC_DIVENR_IC16EN_Pos)      /*!< 0x00008000 */
+#define RCC_DIVENR_IC16EN                       RCC_DIVENR_IC16EN_Msk                /*!< IC16 enable */
+#define RCC_DIVENR_IC17EN_Pos                   (16U)
+#define RCC_DIVENR_IC17EN_Msk                   (0x1UL << RCC_DIVENR_IC17EN_Pos)      /*!< 0x00010000 */
+#define RCC_DIVENR_IC17EN                       RCC_DIVENR_IC17EN_Msk                /*!< IC17 enable */
+#define RCC_DIVENR_IC18EN_Pos                   (17U)
+#define RCC_DIVENR_IC18EN_Msk                   (0x1UL << RCC_DIVENR_IC18EN_Pos)      /*!< 0x00020000 */
+#define RCC_DIVENR_IC18EN                       RCC_DIVENR_IC18EN_Msk                /*!< IC18 enable */
+#define RCC_DIVENR_IC19EN_Pos                   (18U)
+#define RCC_DIVENR_IC19EN_Msk                   (0x1UL << RCC_DIVENR_IC19EN_Pos)      /*!< 0x00040000 */
+#define RCC_DIVENR_IC19EN                       RCC_DIVENR_IC19EN_Msk                /*!< IC19 enable */
+#define RCC_DIVENR_IC20EN_Pos                   (19U)
+#define RCC_DIVENR_IC20EN_Msk                   (0x1UL << RCC_DIVENR_IC20EN_Pos)      /*!< 0x00080000 */
+#define RCC_DIVENR_IC20EN                       RCC_DIVENR_IC20EN_Msk                /*!< IC20 enable */
+
+/******************  Bit definition for RCC_BUSENR register  ******************/
+#define RCC_BUSENR_ACLKNEN_Pos                  (0U)
+#define RCC_BUSENR_ACLKNEN_Msk                  (0x1UL << RCC_BUSENR_ACLKNEN_Pos)     /*!< 0x00000001 */
+#define RCC_BUSENR_ACLKNEN                      RCC_BUSENR_ACLKNEN_Msk               /*!< ACLKN enable */
+#define RCC_BUSENR_ACLKNCEN_Pos                 (1U)
+#define RCC_BUSENR_ACLKNCEN_Msk                 (0x1UL << RCC_BUSENR_ACLKNCEN_Pos)    /*!< 0x00000002 */
+#define RCC_BUSENR_ACLKNCEN                     RCC_BUSENR_ACLKNCEN_Msk              /*!< ACLKNC enable */
+#define RCC_BUSENR_AHBMEN_Pos                   (2U)
+#define RCC_BUSENR_AHBMEN_Msk                   (0x1UL << RCC_BUSENR_AHBMEN_Pos)      /*!< 0x00000004 */
+#define RCC_BUSENR_AHBMEN                       RCC_BUSENR_AHBMEN_Msk                /*!< AHBM enable */
+#define RCC_BUSENR_AHB1EN_Pos                   (3U)
+#define RCC_BUSENR_AHB1EN_Msk                   (0x1UL << RCC_BUSENR_AHB1EN_Pos)      /*!< 0x00000008 */
+#define RCC_BUSENR_AHB1EN                       RCC_BUSENR_AHB1EN_Msk                /*!< AHB1 enable */
+#define RCC_BUSENR_AHB2EN_Pos                   (4U)
+#define RCC_BUSENR_AHB2EN_Msk                   (0x1UL << RCC_BUSENR_AHB2EN_Pos)      /*!< 0x00000010 */
+#define RCC_BUSENR_AHB2EN                       RCC_BUSENR_AHB2EN_Msk                /*!< AHB2 enable */
+#define RCC_BUSENR_AHB3EN_Pos                   (5U)
+#define RCC_BUSENR_AHB3EN_Msk                   (0x1UL << RCC_BUSENR_AHB3EN_Pos)      /*!< 0x00000020 */
+#define RCC_BUSENR_AHB3EN                       RCC_BUSENR_AHB3EN_Msk                /*!< AHB3 enable */
+#define RCC_BUSENR_AHB4EN_Pos                   (6U)
+#define RCC_BUSENR_AHB4EN_Msk                   (0x1UL << RCC_BUSENR_AHB4EN_Pos)      /*!< 0x00000040 */
+#define RCC_BUSENR_AHB4EN                       RCC_BUSENR_AHB4EN_Msk                /*!< AHB4 enable */
+#define RCC_BUSENR_AHB5EN_Pos                   (7U)
+#define RCC_BUSENR_AHB5EN_Msk                   (0x1UL << RCC_BUSENR_AHB5EN_Pos)      /*!< 0x00000080 */
+#define RCC_BUSENR_AHB5EN                       RCC_BUSENR_AHB5EN_Msk                /*!< AHB5 enable */
+#define RCC_BUSENR_APB1EN_Pos                   (8U)
+#define RCC_BUSENR_APB1EN_Msk                   (0x1UL << RCC_BUSENR_APB1EN_Pos)      /*!< 0x00000100 */
+#define RCC_BUSENR_APB1EN                       RCC_BUSENR_APB1EN_Msk                /*!< APB1 enable */
+#define RCC_BUSENR_APB2EN_Pos                   (9U)
+#define RCC_BUSENR_APB2EN_Msk                   (0x1UL << RCC_BUSENR_APB2EN_Pos)      /*!< 0x00000200 */
+#define RCC_BUSENR_APB2EN                       RCC_BUSENR_APB2EN_Msk                /*!< APB2 enable */
+#define RCC_BUSENR_APB3EN_Pos                   (10U)
+#define RCC_BUSENR_APB3EN_Msk                   (0x1UL << RCC_BUSENR_APB3EN_Pos)      /*!< 0x00000400 */
+#define RCC_BUSENR_APB3EN                       RCC_BUSENR_APB3EN_Msk                /*!< APB3 enable */
+#define RCC_BUSENR_APB4EN_Pos                   (11U)
+#define RCC_BUSENR_APB4EN_Msk                   (0x1UL << RCC_BUSENR_APB4EN_Pos)      /*!< 0x00000800 */
+#define RCC_BUSENR_APB4EN                       RCC_BUSENR_APB4EN_Msk                /*!< APB4 enable */
+#define RCC_BUSENR_APB5EN_Pos                   (12U)
+#define RCC_BUSENR_APB5EN_Msk                   (0x1UL << RCC_BUSENR_APB5EN_Pos)      /*!< 0x00001000 */
+#define RCC_BUSENR_APB5EN                       RCC_BUSENR_APB5EN_Msk                /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENR register  ******************/
+#define RCC_MISCENR_DBGEN_Pos                   (0U)
+#define RCC_MISCENR_DBGEN_Msk                   (0x1UL << RCC_MISCENR_DBGEN_Pos)      /*!< 0x00000001 */
+#define RCC_MISCENR_DBGEN                       RCC_MISCENR_DBGEN_Msk                /*!< DBG enable */
+#define RCC_MISCENR_MCO1EN_Pos                  (1U)
+#define RCC_MISCENR_MCO1EN_Msk                  (0x1UL << RCC_MISCENR_MCO1EN_Pos)     /*!< 0x00000002 */
+#define RCC_MISCENR_MCO1EN                      RCC_MISCENR_MCO1EN_Msk               /*!< MCO1 enable */
+#define RCC_MISCENR_MCO2EN_Pos                  (2U)
+#define RCC_MISCENR_MCO2EN_Msk                  (0x1UL << RCC_MISCENR_MCO2EN_Pos)     /*!< 0x00000004 */
+#define RCC_MISCENR_MCO2EN                      RCC_MISCENR_MCO2EN_Msk               /*!< MCO2 enable */
+#define RCC_MISCENR_XSPIPHYCOMPEN_Pos           (3U)
+#define RCC_MISCENR_XSPIPHYCOMPEN_Msk           (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MISCENR_XSPIPHYCOMPEN               RCC_MISCENR_XSPIPHYCOMPEN_Msk        /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENR_PEREN_Pos                   (6U)
+#define RCC_MISCENR_PEREN_Msk                   (0x1UL << RCC_MISCENR_PEREN_Pos)      /*!< 0x00000040 */
+#define RCC_MISCENR_PEREN                       RCC_MISCENR_PEREN_Msk                /*!< PER enable */
+
+/******************  Bit definition for RCC_MEMENR register  ******************/
+#define RCC_MEMENR_AXISRAM3EN_Pos               (0U)
+#define RCC_MEMENR_AXISRAM3EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMENR_AXISRAM3EN                   RCC_MEMENR_AXISRAM3EN_Msk            /*!< AXISRAM3 enable */
+#define RCC_MEMENR_AXISRAM4EN_Pos               (1U)
+#define RCC_MEMENR_AXISRAM4EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMENR_AXISRAM4EN                   RCC_MEMENR_AXISRAM4EN_Msk            /*!< AXISRAM4 enable */
+#define RCC_MEMENR_AXISRAM5EN_Pos               (2U)
+#define RCC_MEMENR_AXISRAM5EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMENR_AXISRAM5EN                   RCC_MEMENR_AXISRAM5EN_Msk            /*!< AXISRAM5 enable */
+#define RCC_MEMENR_AXISRAM6EN_Pos               (3U)
+#define RCC_MEMENR_AXISRAM6EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMENR_AXISRAM6EN                   RCC_MEMENR_AXISRAM6EN_Msk            /*!< AXISRAM6 enable */
+#define RCC_MEMENR_AHBSRAM1EN_Pos               (4U)
+#define RCC_MEMENR_AHBSRAM1EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMENR_AHBSRAM1EN                   RCC_MEMENR_AHBSRAM1EN_Msk            /*!< AHBSRAM1 enable */
+#define RCC_MEMENR_AHBSRAM2EN_Pos               (5U)
+#define RCC_MEMENR_AHBSRAM2EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMENR_AHBSRAM2EN                   RCC_MEMENR_AHBSRAM2EN_Msk            /*!< AHBSRAM2 enable */
+#define RCC_MEMENR_BKPSRAMEN_Pos                (6U)
+#define RCC_MEMENR_BKPSRAMEN_Msk                (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos)   /*!< 0x00000040 */
+#define RCC_MEMENR_BKPSRAMEN                    RCC_MEMENR_BKPSRAMEN_Msk             /*!< BKPSRAM enable */
+#define RCC_MEMENR_AXISRAM1EN_Pos               (7U)
+#define RCC_MEMENR_AXISRAM1EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMENR_AXISRAM1EN                   RCC_MEMENR_AXISRAM1EN_Msk            /*!< AXISRAM1 enable */
+#define RCC_MEMENR_AXISRAM2EN_Pos               (8U)
+#define RCC_MEMENR_AXISRAM2EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMENR_AXISRAM2EN                   RCC_MEMENR_AXISRAM2EN_Msk            /*!< AXISRAM2 enable */
+#define RCC_MEMENR_FLEXRAMEN_Pos                (9U)
+#define RCC_MEMENR_FLEXRAMEN_Msk                (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos)   /*!< 0x00000200 */
+#define RCC_MEMENR_FLEXRAMEN                    RCC_MEMENR_FLEXRAMEN_Msk             /*!< FLEXRAM enable */
+#define RCC_MEMENR_VENCRAMEN_Pos                (11U)
+#define RCC_MEMENR_VENCRAMEN_Msk                (0x1UL << RCC_MEMENR_VENCRAMEN_Pos)   /*!< 0x00000800 */
+#define RCC_MEMENR_VENCRAMEN                    RCC_MEMENR_VENCRAMEN_Msk             /*!< VENCRAM enable */
+#define RCC_MEMENR_BOOTROMEN_Pos                (12U)
+#define RCC_MEMENR_BOOTROMEN_Msk                (0x1UL << RCC_MEMENR_BOOTROMEN_Pos)   /*!< 0x00001000 */
+#define RCC_MEMENR_BOOTROMEN                    RCC_MEMENR_BOOTROMEN_Msk             /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENR register  ******************/
+#define RCC_AHB1ENR_GPDMA1EN_Pos                (4U)
+#define RCC_AHB1ENR_GPDMA1EN_Msk                (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPDMA1EN                    RCC_AHB1ENR_GPDMA1EN_Msk             /*!< GPDMA1 enable */
+#define RCC_AHB1ENR_ADC12EN_Pos                 (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                 (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                     RCC_AHB1ENR_ADC12EN_Msk              /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENR register  ******************/
+#define RCC_AHB2ENR_RAMCFGEN_Pos                (12U)
+#define RCC_AHB2ENR_RAMCFGEN_Msk                (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2ENR_RAMCFGEN                    RCC_AHB2ENR_RAMCFGEN_Msk             /*!< RAMCFG enable */
+#define RCC_AHB2ENR_MDF1EN_Pos                  (16U)
+#define RCC_AHB2ENR_MDF1EN_Msk                  (0x1UL << RCC_AHB2ENR_MDF1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB2ENR_MDF1EN                      RCC_AHB2ENR_MDF1EN_Msk               /*!< MDF1 enable */
+#define RCC_AHB2ENR_ADF1EN_Pos                  (17U)
+#define RCC_AHB2ENR_ADF1EN_Msk                  (0x1UL << RCC_AHB2ENR_ADF1EN_Pos)     /*!< 0x00020000 */
+#define RCC_AHB2ENR_ADF1EN                      RCC_AHB2ENR_ADF1EN_Msk               /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENR register  ******************/
+#define RCC_AHB3ENR_RNGEN_Pos                   (0U)
+#define RCC_AHB3ENR_RNGEN_Msk                   (0x1UL << RCC_AHB3ENR_RNGEN_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3ENR_RNGEN                       RCC_AHB3ENR_RNGEN_Msk                /*!< RNG enable */
+#define RCC_AHB3ENR_HASHEN_Pos                  (1U)
+#define RCC_AHB3ENR_HASHEN_Msk                  (0x1UL << RCC_AHB3ENR_HASHEN_Pos)     /*!< 0x00000002 */
+#define RCC_AHB3ENR_HASHEN                      RCC_AHB3ENR_HASHEN_Msk               /*!< HASH enable */
+#define RCC_AHB3ENR_PKAEN_Pos                   (8U)
+#define RCC_AHB3ENR_PKAEN_Msk                   (0x1UL << RCC_AHB3ENR_PKAEN_Pos)      /*!< 0x00000100 */
+#define RCC_AHB3ENR_PKAEN                       RCC_AHB3ENR_PKAEN_Msk                /*!< PKA enable */
+#define RCC_AHB3ENR_RIFSCEN_Pos                 (9U)
+#define RCC_AHB3ENR_RIFSCEN_Msk                 (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos)    /*!< 0x00000200 */
+#define RCC_AHB3ENR_RIFSCEN                     RCC_AHB3ENR_RIFSCEN_Msk              /*!< RIFSC enable */
+#define RCC_AHB3ENR_IACEN_Pos                   (10U)
+#define RCC_AHB3ENR_IACEN_Msk                   (0x1UL << RCC_AHB3ENR_IACEN_Pos)      /*!< 0x00000400 */
+#define RCC_AHB3ENR_IACEN                       RCC_AHB3ENR_IACEN_Msk                /*!< IAC enable */
+#define RCC_AHB3ENR_RISAFEN_Pos                 (14U)
+#define RCC_AHB3ENR_RISAFEN_Msk                 (0x1UL << RCC_AHB3ENR_RISAFEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB3ENR_RISAFEN                     RCC_AHB3ENR_RISAFEN_Msk              /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                 (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                     RCC_AHB4ENR_GPIOAEN_Msk              /*!< GPIO A enable */
+#define RCC_AHB4ENR_GPIOBEN_Pos                 (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                     RCC_AHB4ENR_GPIOBEN_Msk              /*!< GPIO B enable */
+#define RCC_AHB4ENR_GPIOCEN_Pos                 (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)    /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                     RCC_AHB4ENR_GPIOCEN_Msk              /*!< GPIO C enable */
+#define RCC_AHB4ENR_GPIODEN_Pos                 (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)    /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                     RCC_AHB4ENR_GPIODEN_Msk              /*!< GPIO D enable */
+#define RCC_AHB4ENR_GPIOEEN_Pos                 (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)    /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                     RCC_AHB4ENR_GPIOEEN_Msk              /*!< GPIO E enable */
+#define RCC_AHB4ENR_GPIOFEN_Pos                 (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                     RCC_AHB4ENR_GPIOFEN_Msk              /*!< GPIO F enable */
+#define RCC_AHB4ENR_GPIOGEN_Pos                 (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)    /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                     RCC_AHB4ENR_GPIOGEN_Msk              /*!< GPIO G enable */
+#define RCC_AHB4ENR_GPIOHEN_Pos                 (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)    /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                     RCC_AHB4ENR_GPIOHEN_Msk              /*!< GPIO H enable */
+#define RCC_AHB4ENR_GPIONEN_Pos                 (13U)
+#define RCC_AHB4ENR_GPIONEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIONEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB4ENR_GPIONEN                     RCC_AHB4ENR_GPIONEN_Msk              /*!< GPIO N enable */
+#define RCC_AHB4ENR_GPIOOEN_Pos                 (14U)
+#define RCC_AHB4ENR_GPIOOEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB4ENR_GPIOOEN                     RCC_AHB4ENR_GPIOOEN_Msk              /*!< GPIO O enable */
+#define RCC_AHB4ENR_GPIOPEN_Pos                 (15U)
+#define RCC_AHB4ENR_GPIOPEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos)    /*!< 0x00008000 */
+#define RCC_AHB4ENR_GPIOPEN                     RCC_AHB4ENR_GPIOPEN_Msk              /*!< GPIO P enable */
+#define RCC_AHB4ENR_GPIOQEN_Pos                 (16U)
+#define RCC_AHB4ENR_GPIOQEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos)    /*!< 0x00010000 */
+#define RCC_AHB4ENR_GPIOQEN                     RCC_AHB4ENR_GPIOQEN_Msk              /*!< GPIO Q enable */
+#define RCC_AHB4ENR_PWREN_Pos                   (18U)
+#define RCC_AHB4ENR_PWREN_Msk                   (0x1UL << RCC_AHB4ENR_PWREN_Pos)      /*!< 0x00040000 */
+#define RCC_AHB4ENR_PWREN                       RCC_AHB4ENR_PWREN_Msk                /*!< PWR enable */
+#define RCC_AHB4ENR_CRCEN_Pos                   (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                   (0x1UL << RCC_AHB4ENR_CRCEN_Pos)      /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                       RCC_AHB4ENR_CRCEN_Msk                /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENR register  ******************/
+#define RCC_AHB5ENR_HPDMA1EN_Pos                (0U)
+#define RCC_AHB5ENR_HPDMA1EN_Msk                (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5ENR_HPDMA1EN                    RCC_AHB5ENR_HPDMA1EN_Msk             /*!< HPDMA1 enable */
+#define RCC_AHB5ENR_DMA2DEN_Pos                 (1U)
+#define RCC_AHB5ENR_DMA2DEN_Msk                 (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB5ENR_DMA2DEN                     RCC_AHB5ENR_DMA2DEN_Msk              /*!< DMA2D enable */
+#define RCC_AHB5ENR_JPEGEN_Pos                  (3U)
+#define RCC_AHB5ENR_JPEGEN_Msk                  (0x1UL << RCC_AHB5ENR_JPEGEN_Pos)     /*!< 0x00000008 */
+#define RCC_AHB5ENR_JPEGEN                      RCC_AHB5ENR_JPEGEN_Msk               /*!< JPEG enable */
+#define RCC_AHB5ENR_FMCEN_Pos                   (4U)
+#define RCC_AHB5ENR_FMCEN_Msk                   (0x1UL << RCC_AHB5ENR_FMCEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB5ENR_FMCEN                       RCC_AHB5ENR_FMCEN_Msk                /*!< FMC enable */
+#define RCC_AHB5ENR_XSPI1EN_Pos                 (5U)
+#define RCC_AHB5ENR_XSPI1EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB5ENR_XSPI1EN                     RCC_AHB5ENR_XSPI1EN_Msk              /*!< XSPI1 enable */
+#define RCC_AHB5ENR_PSSIEN_Pos                  (6U)
+#define RCC_AHB5ENR_PSSIEN_Msk                  (0x1UL << RCC_AHB5ENR_PSSIEN_Pos)     /*!< 0x00000040 */
+#define RCC_AHB5ENR_PSSIEN                      RCC_AHB5ENR_PSSIEN_Msk               /*!< PSSI enable */
+#define RCC_AHB5ENR_SDMMC2EN_Pos                (7U)
+#define RCC_AHB5ENR_SDMMC2EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5ENR_SDMMC2EN                    RCC_AHB5ENR_SDMMC2EN_Msk             /*!< SDMMC2 enable */
+#define RCC_AHB5ENR_SDMMC1EN_Pos                (8U)
+#define RCC_AHB5ENR_SDMMC1EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5ENR_SDMMC1EN                    RCC_AHB5ENR_SDMMC1EN_Msk             /*!< SDMMC1 enable */
+#define RCC_AHB5ENR_XSPI2EN_Pos                 (12U)
+#define RCC_AHB5ENR_XSPI2EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos)    /*!< 0x00001000 */
+#define RCC_AHB5ENR_XSPI2EN                     RCC_AHB5ENR_XSPI2EN_Msk              /*!< XSPI2 enable */
+#define RCC_AHB5ENR_XSPIMEN_Pos                 (13U)
+#define RCC_AHB5ENR_XSPIMEN_Msk                 (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB5ENR_XSPIMEN                     RCC_AHB5ENR_XSPIMEN_Msk              /*!< XSPIM enable */
+#define RCC_AHB5ENR_XSPI3EN_Pos                 (17U)
+#define RCC_AHB5ENR_XSPI3EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos)    /*!< 0x00020000 */
+#define RCC_AHB5ENR_XSPI3EN                     RCC_AHB5ENR_XSPI3EN_Msk              /*!< XSPI3 enable */
+#define RCC_AHB5ENR_GFXMMUEN_Pos                (19U)
+#define RCC_AHB5ENR_GFXMMUEN_Msk                (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5ENR_GFXMMUEN                    RCC_AHB5ENR_GFXMMUEN_Msk             /*!< GFXMMU enable */
+#define RCC_AHB5ENR_GPU2DEN_Pos                 (20U)
+#define RCC_AHB5ENR_GPU2DEN_Msk                 (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos)    /*!< 0x00100000 */
+#define RCC_AHB5ENR_GPU2DEN                     RCC_AHB5ENR_GPU2DEN_Msk              /*!< GPU2D enable */
+#define RCC_AHB5ENR_ETH1MACEN_Pos               (22U)
+#define RCC_AHB5ENR_ETH1MACEN_Msk               (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5ENR_ETH1MACEN                   RCC_AHB5ENR_ETH1MACEN_Msk            /*!< ETH1MAC enable */
+#define RCC_AHB5ENR_ETH1TXEN_Pos                (23U)
+#define RCC_AHB5ENR_ETH1TXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5ENR_ETH1TXEN                    RCC_AHB5ENR_ETH1TXEN_Msk             /*!< ETH1TX enable */
+#define RCC_AHB5ENR_ETH1RXEN_Pos                (24U)
+#define RCC_AHB5ENR_ETH1RXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5ENR_ETH1RXEN                    RCC_AHB5ENR_ETH1RXEN_Msk             /*!< ETH1RX enable */
+#define RCC_AHB5ENR_ETH1EN_Pos                  (25U)
+#define RCC_AHB5ENR_ETH1EN_Msk                  (0x1UL << RCC_AHB5ENR_ETH1EN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB5ENR_ETH1EN                      RCC_AHB5ENR_ETH1EN_Msk               /*!< ETH1 enable */
+#define RCC_AHB5ENR_OTG1EN_Pos                  (26U)
+#define RCC_AHB5ENR_OTG1EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG1EN_Pos)     /*!< 0x04000000 */
+#define RCC_AHB5ENR_OTG1EN                      RCC_AHB5ENR_OTG1EN_Msk               /*!< OTG1 enable */
+#define RCC_AHB5ENR_OTGPHY1EN_Pos               (27U)
+#define RCC_AHB5ENR_OTGPHY1EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5ENR_OTGPHY1EN                   RCC_AHB5ENR_OTGPHY1EN_Msk            /*!< OTGPHY1 enable */
+#define RCC_AHB5ENR_OTGPHY2EN_Pos               (28U)
+#define RCC_AHB5ENR_OTGPHY2EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5ENR_OTGPHY2EN                   RCC_AHB5ENR_OTGPHY2EN_Msk            /*!< OTGPHY2 enable */
+#define RCC_AHB5ENR_OTG2EN_Pos                  (29U)
+#define RCC_AHB5ENR_OTG2EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG2EN_Pos)     /*!< 0x20000000 */
+#define RCC_AHB5ENR_OTG2EN                      RCC_AHB5ENR_OTG2EN_Msk               /*!< OTG2 enable */
+
+/*****************  Bit definition for RCC_APB1ENR1 register  *****************/
+#define RCC_APB1ENR1_TIM2EN_Pos                 (0U)
+#define RCC_APB1ENR1_TIM2EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                     RCC_APB1ENR1_TIM2EN_Msk              /*!< TIM2 enable */
+#define RCC_APB1ENR1_TIM3EN_Pos                 (1U)
+#define RCC_APB1ENR1_TIM3EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                     RCC_APB1ENR1_TIM3EN_Msk              /*!< TIM3 enable */
+#define RCC_APB1ENR1_TIM4EN_Pos                 (2U)
+#define RCC_APB1ENR1_TIM4EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)    /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                     RCC_APB1ENR1_TIM4EN_Msk              /*!< TIM4 enable */
+#define RCC_APB1ENR1_TIM5EN_Pos                 (3U)
+#define RCC_APB1ENR1_TIM5EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)    /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                     RCC_APB1ENR1_TIM5EN_Msk              /*!< TIM5 enable */
+#define RCC_APB1ENR1_TIM6EN_Pos                 (4U)
+#define RCC_APB1ENR1_TIM6EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)    /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                     RCC_APB1ENR1_TIM6EN_Msk              /*!< TIM6 enable */
+#define RCC_APB1ENR1_TIM7EN_Pos                 (5U)
+#define RCC_APB1ENR1_TIM7EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                     RCC_APB1ENR1_TIM7EN_Msk              /*!< TIM7 enable */
+#define RCC_APB1ENR1_TIM12EN_Pos                (6U)
+#define RCC_APB1ENR1_TIM12EN_Msk                (0x1UL << RCC_APB1ENR1_TIM12EN_Pos)   /*!< 0x00000040 */
+#define RCC_APB1ENR1_TIM12EN                    RCC_APB1ENR1_TIM12EN_Msk             /*!< TIM12 enable */
+#define RCC_APB1ENR1_TIM13EN_Pos                (7U)
+#define RCC_APB1ENR1_TIM13EN_Msk                (0x1UL << RCC_APB1ENR1_TIM13EN_Pos)   /*!< 0x00000080 */
+#define RCC_APB1ENR1_TIM13EN                    RCC_APB1ENR1_TIM13EN_Msk             /*!< TIM13 enable */
+#define RCC_APB1ENR1_TIM14EN_Pos                (8U)
+#define RCC_APB1ENR1_TIM14EN_Msk                (0x1UL << RCC_APB1ENR1_TIM14EN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR1_TIM14EN                    RCC_APB1ENR1_TIM14EN_Msk             /*!< TIM14 enable */
+#define RCC_APB1ENR1_LPTIM1EN_Pos               (9U)
+#define RCC_APB1ENR1_LPTIM1EN_Msk               (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LPTIM1EN                   RCC_APB1ENR1_LPTIM1EN_Msk            /*!< LPTIM1 enable */
+#define RCC_APB1ENR1_WWDGEN_Pos                 (11U)
+#define RCC_APB1ENR1_WWDGEN_Msk                 (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                     RCC_APB1ENR1_WWDGEN_Msk              /*!< WWDG enable */
+#define RCC_APB1ENR1_TIM10EN_Pos                (12U)
+#define RCC_APB1ENR1_TIM10EN_Msk                (0x1UL << RCC_APB1ENR1_TIM10EN_Pos)   /*!< 0x00001000 */
+#define RCC_APB1ENR1_TIM10EN                    RCC_APB1ENR1_TIM10EN_Msk             /*!< TIM10 enable */
+#define RCC_APB1ENR1_TIM11EN_Pos                (13U)
+#define RCC_APB1ENR1_TIM11EN_Msk                (0x1UL << RCC_APB1ENR1_TIM11EN_Pos)   /*!< 0x00002000 */
+#define RCC_APB1ENR1_TIM11EN                    RCC_APB1ENR1_TIM11EN_Msk             /*!< TIM11 enable */
+#define RCC_APB1ENR1_SPI2EN_Pos                 (14U)
+#define RCC_APB1ENR1_SPI2EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                     RCC_APB1ENR1_SPI2EN_Msk              /*!< SPI2 enable */
+#define RCC_APB1ENR1_SPI3EN_Pos                 (15U)
+#define RCC_APB1ENR1_SPI3EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                     RCC_APB1ENR1_SPI3EN_Msk              /*!< SPI3 enable */
+#define RCC_APB1ENR1_SPDIFRX1EN_Pos             (16U)
+#define RCC_APB1ENR1_SPDIFRX1EN_Msk             (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */
+#define RCC_APB1ENR1_SPDIFRX1EN                 RCC_APB1ENR1_SPDIFRX1EN_Msk          /*!< SPDIFRX1 enable */
+#define RCC_APB1ENR1_USART2EN_Pos               (17U)
+#define RCC_APB1ENR1_USART2EN_Msk               (0x1UL << RCC_APB1ENR1_USART2EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                   RCC_APB1ENR1_USART2EN_Msk            /*!< USART2 enable */
+#define RCC_APB1ENR1_USART3EN_Pos               (18U)
+#define RCC_APB1ENR1_USART3EN_Msk               (0x1UL << RCC_APB1ENR1_USART3EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                   RCC_APB1ENR1_USART3EN_Msk            /*!< USART3 enable */
+#define RCC_APB1ENR1_UART4EN_Pos                (19U)
+#define RCC_APB1ENR1_UART4EN_Msk                (0x1UL << RCC_APB1ENR1_UART4EN_Pos)   /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                    RCC_APB1ENR1_UART4EN_Msk             /*!< UART4 enable */
+#define RCC_APB1ENR1_UART5EN_Pos                (20U)
+#define RCC_APB1ENR1_UART5EN_Msk                (0x1UL << RCC_APB1ENR1_UART5EN_Pos)   /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                    RCC_APB1ENR1_UART5EN_Msk             /*!< UART5 enable */
+#define RCC_APB1ENR1_I2C1EN_Pos                 (21U)
+#define RCC_APB1ENR1_I2C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                     RCC_APB1ENR1_I2C1EN_Msk              /*!< I2C1 enable */
+#define RCC_APB1ENR1_I2C2EN_Pos                 (22U)
+#define RCC_APB1ENR1_I2C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                     RCC_APB1ENR1_I2C2EN_Msk              /*!< I2C2 enable */
+#define RCC_APB1ENR1_I2C3EN_Pos                 (23U)
+#define RCC_APB1ENR1_I2C3EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                     RCC_APB1ENR1_I2C3EN_Msk              /*!< I2C3 enable */
+#define RCC_APB1ENR1_I3C1EN_Pos                 (24U)
+#define RCC_APB1ENR1_I3C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C1EN_Pos)    /*!< 0x01000000 */
+#define RCC_APB1ENR1_I3C1EN                     RCC_APB1ENR1_I3C1EN_Msk              /*!< I3C1 enable */
+#define RCC_APB1ENR1_I3C2EN_Pos                 (25U)
+#define RCC_APB1ENR1_I3C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C2EN_Pos)    /*!< 0x02000000 */
+#define RCC_APB1ENR1_I3C2EN                     RCC_APB1ENR1_I3C2EN_Msk              /*!< I3C2 enable */
+#define RCC_APB1ENR1_UART7EN_Pos                (30U)
+#define RCC_APB1ENR1_UART7EN_Msk                (0x1UL << RCC_APB1ENR1_UART7EN_Pos)   /*!< 0x40000000 */
+#define RCC_APB1ENR1_UART7EN                    RCC_APB1ENR1_UART7EN_Msk             /*!< UART7 enable */
+#define RCC_APB1ENR1_UART8EN_Pos                (31U)
+#define RCC_APB1ENR1_UART8EN_Msk                (0x1UL << RCC_APB1ENR1_UART8EN_Pos)   /*!< 0x80000000 */
+#define RCC_APB1ENR1_UART8EN                    RCC_APB1ENR1_UART8EN_Msk             /*!< UART8 enable */
+
+/*****************  Bit definition for RCC_APB1ENR2 register  *****************/
+#define RCC_APB1ENR2_MDIOSEN_Pos                (5U)
+#define RCC_APB1ENR2_MDIOSEN_Msk                (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos)   /*!< 0x00000020 */
+#define RCC_APB1ENR2_MDIOSEN                    RCC_APB1ENR2_MDIOSEN_Msk             /*!< MDIOS enable */
+#define RCC_APB1ENR2_FDCANEN_Pos                (8U)
+#define RCC_APB1ENR2_FDCANEN_Msk                (0x1UL << RCC_APB1ENR2_FDCANEN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR2_FDCANEN                    RCC_APB1ENR2_FDCANEN_Msk             /*!< FDCAN enable */
+#define RCC_APB1ENR2_UCPD1EN_Pos                (18U)
+#define RCC_APB1ENR2_UCPD1EN_Msk                (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB1ENR2_UCPD1EN                    RCC_APB1ENR2_UCPD1EN_Msk             /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                  (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                  (0x1UL << RCC_APB2ENR_TIM1EN_Pos)     /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                      RCC_APB2ENR_TIM1EN_Msk               /*!< TIM1 enable */
+#define RCC_APB2ENR_TIM8EN_Pos                  (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                  (0x1UL << RCC_APB2ENR_TIM8EN_Pos)     /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                      RCC_APB2ENR_TIM8EN_Msk               /*!< TIM8 enable */
+#define RCC_APB2ENR_USART1EN_Pos                (4U)
+#define RCC_APB2ENR_USART1EN_Msk                (0x1UL << RCC_APB2ENR_USART1EN_Pos)   /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                    RCC_APB2ENR_USART1EN_Msk             /*!< USART1 enable */
+#define RCC_APB2ENR_USART6EN_Pos                (5U)
+#define RCC_APB2ENR_USART6EN_Msk                (0x1UL << RCC_APB2ENR_USART6EN_Pos)   /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                    RCC_APB2ENR_USART6EN_Msk             /*!< USART6 enable */
+#define RCC_APB2ENR_UART9EN_Pos                 (6U)
+#define RCC_APB2ENR_UART9EN_Msk                 (0x1UL << RCC_APB2ENR_UART9EN_Pos)    /*!< 0x00000040 */
+#define RCC_APB2ENR_UART9EN                     RCC_APB2ENR_UART9EN_Msk              /*!< UART9 enable */
+#define RCC_APB2ENR_USART10EN_Pos               (7U)
+#define RCC_APB2ENR_USART10EN_Msk               (0x1UL << RCC_APB2ENR_USART10EN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk            /*!< USART10 enable */
+#define RCC_APB2ENR_SPI1EN_Pos                  (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                  (0x1UL << RCC_APB2ENR_SPI1EN_Pos)     /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                      RCC_APB2ENR_SPI1EN_Msk               /*!< SPI1 enable */
+#define RCC_APB2ENR_SPI4EN_Pos                  (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                  (0x1UL << RCC_APB2ENR_SPI4EN_Pos)     /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                      RCC_APB2ENR_SPI4EN_Msk               /*!< SPI4 enable */
+#define RCC_APB2ENR_TIM18EN_Pos                 (15U)
+#define RCC_APB2ENR_TIM18EN_Msk                 (0x1UL << RCC_APB2ENR_TIM18EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB2ENR_TIM18EN                     RCC_APB2ENR_TIM18EN_Msk              /*!< TIM18 enable */
+#define RCC_APB2ENR_TIM15EN_Pos                 (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                 (0x1UL << RCC_APB2ENR_TIM15EN_Pos)    /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                     RCC_APB2ENR_TIM15EN_Msk              /*!< TIM15 enable */
+#define RCC_APB2ENR_TIM16EN_Pos                 (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                 (0x1UL << RCC_APB2ENR_TIM16EN_Pos)    /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                     RCC_APB2ENR_TIM16EN_Msk              /*!< TIM16 enable */
+#define RCC_APB2ENR_TIM17EN_Pos                 (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                 (0x1UL << RCC_APB2ENR_TIM17EN_Pos)    /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                     RCC_APB2ENR_TIM17EN_Msk              /*!< TIM17 enable */
+#define RCC_APB2ENR_TIM9EN_Pos                  (19U)
+#define RCC_APB2ENR_TIM9EN_Msk                  (0x1UL << RCC_APB2ENR_TIM9EN_Pos)     /*!< 0x00080000 */
+#define RCC_APB2ENR_TIM9EN                      RCC_APB2ENR_TIM9EN_Msk               /*!< TIM9 enable */
+#define RCC_APB2ENR_SPI5EN_Pos                  (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                  (0x1UL << RCC_APB2ENR_SPI5EN_Pos)     /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                      RCC_APB2ENR_SPI5EN_Msk               /*!< SPI5 enable */
+#define RCC_APB2ENR_SAI1EN_Pos                  (21U)
+#define RCC_APB2ENR_SAI1EN_Msk                  (0x1UL << RCC_APB2ENR_SAI1EN_Pos)     /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                      RCC_APB2ENR_SAI1EN_Msk               /*!< SAI1 enable */
+#define RCC_APB2ENR_SAI2EN_Pos                  (22U)
+#define RCC_APB2ENR_SAI2EN_Msk                  (0x1UL << RCC_APB2ENR_SAI2EN_Pos)     /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                      RCC_APB2ENR_SAI2EN_Msk               /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_DFTEN_Pos                   (2U)
+#define RCC_APB3ENR_DFTEN_Msk                   (0x1UL << RCC_APB3ENR_DFTEN_Pos)      /*!< 0x00000004 */
+#define RCC_APB3ENR_DFTEN                       RCC_APB3ENR_DFTEN_Msk                /*!< DFT enable */
+
+/*****************  Bit definition for RCC_APB4ENR1 register  *****************/
+#define RCC_APB4ENR1_HDPEN_Pos                  (2U)
+#define RCC_APB4ENR1_HDPEN_Msk                  (0x1UL << RCC_APB4ENR1_HDPEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR1_HDPEN                      RCC_APB4ENR1_HDPEN_Msk               /*!< HDP enable */
+#define RCC_APB4ENR1_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR1_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR1_LPUART1EN                  RCC_APB4ENR1_LPUART1EN_Msk           /*!< LPUART1 enable */
+#define RCC_APB4ENR1_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR1_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR1_SPI6EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB4ENR1_SPI6EN                     RCC_APB4ENR1_SPI6EN_Msk              /*!< SPI6 enable */
+#define RCC_APB4ENR1_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR1_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR1_I2C4EN_Pos)    /*!< 0x00000080 */
+#define RCC_APB4ENR1_I2C4EN                     RCC_APB4ENR1_I2C4EN_Msk              /*!< I2C4 enable */
+#define RCC_APB4ENR1_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR1_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4ENR1_LPTIM2EN                   RCC_APB4ENR1_LPTIM2EN_Msk            /*!< LPTIM2 enable */
+#define RCC_APB4ENR1_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR1_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4ENR1_LPTIM3EN                   RCC_APB4ENR1_LPTIM3EN_Msk            /*!< LPTIM3 enable */
+#define RCC_APB4ENR1_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR1_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4ENR1_LPTIM4EN                   RCC_APB4ENR1_LPTIM4EN_Msk            /*!< LPTIM4 enable */
+#define RCC_APB4ENR1_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR1_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4ENR1_LPTIM5EN                   RCC_APB4ENR1_LPTIM5EN_Msk            /*!< LPTIM5 enable */
+#define RCC_APB4ENR1_VREFBUFEN_Pos              (15U)
+#define RCC_APB4ENR1_VREFBUFEN_Msk              (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR1_VREFBUFEN                  RCC_APB4ENR1_VREFBUFEN_Msk           /*!< VREFBUF enable */
+#define RCC_APB4ENR1_RTCEN_Pos                  (16U)
+#define RCC_APB4ENR1_RTCEN_Msk                  (0x1UL << RCC_APB4ENR1_RTCEN_Pos)     /*!< 0x00010000 */
+#define RCC_APB4ENR1_RTCEN                      RCC_APB4ENR1_RTCEN_Msk               /*!< RTC enable */
+#define RCC_APB4ENR1_RTCAPBEN_Pos               (17U)
+#define RCC_APB4ENR1_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4ENR1_RTCAPBEN                   RCC_APB4ENR1_RTCAPBEN_Msk            /*!< RTCAPB enable */
+
+/*****************  Bit definition for RCC_APB4ENR2 register  *****************/
+#define RCC_APB4ENR2_SYSCFGEN_Pos               (0U)
+#define RCC_APB4ENR2_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4ENR2_SYSCFGEN                   RCC_APB4ENR2_SYSCFGEN_Msk            /*!< SYSCFG enable */
+#define RCC_APB4ENR2_BSECEN_Pos                 (1U)
+#define RCC_APB4ENR2_BSECEN_Msk                 (0x1UL << RCC_APB4ENR2_BSECEN_Pos)    /*!< 0x00000002 */
+#define RCC_APB4ENR2_BSECEN                     RCC_APB4ENR2_BSECEN_Msk              /*!< BSEC enable */
+#define RCC_APB4ENR2_DTSEN_Pos                  (2U)
+#define RCC_APB4ENR2_DTSEN_Msk                  (0x1UL << RCC_APB4ENR2_DTSEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR2_DTSEN                      RCC_APB4ENR2_DTSEN_Msk               /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENR register  ******************/
+#define RCC_APB5ENR_LTDCEN_Pos                  (1U)
+#define RCC_APB5ENR_LTDCEN_Msk                  (0x1UL << RCC_APB5ENR_LTDCEN_Pos)     /*!< 0x00000002 */
+#define RCC_APB5ENR_LTDCEN                      RCC_APB5ENR_LTDCEN_Msk               /*!< LTDC enable */
+#define RCC_APB5ENR_DCMIPPEN_Pos                (2U)
+#define RCC_APB5ENR_DCMIPPEN_Msk                (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos)   /*!< 0x00000004 */
+#define RCC_APB5ENR_DCMIPPEN                    RCC_APB5ENR_DCMIPPEN_Msk             /*!< DCMIPP enable */
+#define RCC_APB5ENR_GFXTIMEN_Pos                (4U)
+#define RCC_APB5ENR_GFXTIMEN_Msk                (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos)   /*!< 0x00000010 */
+#define RCC_APB5ENR_GFXTIMEN                    RCC_APB5ENR_GFXTIMEN_Msk             /*!< GFXTIM enable */
+#define RCC_APB5ENR_VENCEN_Pos                  (5U)
+#define RCC_APB5ENR_VENCEN_Msk                  (0x1UL << RCC_APB5ENR_VENCEN_Pos)     /*!< 0x00000020 */
+#define RCC_APB5ENR_VENCEN                      RCC_APB5ENR_VENCEN_Msk               /*!< VENC enable */
+#define RCC_APB5ENR_CSIEN_Pos                   (6U)
+#define RCC_APB5ENR_CSIEN_Msk                   (0x1UL << RCC_APB5ENR_CSIEN_Pos)      /*!< 0x00000040 */
+#define RCC_APB5ENR_CSIEN                       RCC_APB5ENR_CSIEN_Msk                /*!< CSI enable */
+
+/*****************  Bit definition for RCC_BUSLPENR register  *****************/
+#define RCC_BUSLPENR_ACLKNLPEN_Pos              (0U)
+#define RCC_BUSLPENR_ACLKNLPEN_Msk              (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENR_ACLKNLPEN                  RCC_BUSLPENR_ACLKNLPEN_Msk           /*!< ACLKN enable  */
+#define RCC_BUSLPENR_ACLKNCLPEN_Pos             (1U)
+#define RCC_BUSLPENR_ACLKNCLPEN_Msk             (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */
+#define RCC_BUSLPENR_ACLKNCLPEN                 RCC_BUSLPENR_ACLKNCLPEN_Msk          /*!< ACLKNC enable */
+
+/****************  Bit definition for RCC_MISCLPENR register  *****************/
+#define RCC_MISCLPENR_DBGLPEN_Pos               (0U)
+#define RCC_MISCLPENR_DBGLPEN_Msk               (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MISCLPENR_DBGLPEN                   RCC_MISCLPENR_DBGLPEN_Msk            /*!< DBG enable  */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos       (3U)
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk       (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos)      /*!< 0x00000008 */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN           RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk    /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENR_PERLPEN_Pos               (6U)
+#define RCC_MISCLPENR_PERLPEN_Msk               (0x1UL << RCC_MISCLPENR_PERLPEN_Pos)  /*!< 0x00000040 */
+#define RCC_MISCLPENR_PERLPEN                   RCC_MISCLPENR_PERLPEN_Msk            /*!< PER enable  */
+
+/*****************  Bit definition for RCC_MEMLPENR register  *****************/
+#define RCC_MEMLPENR_AXISRAM3LPEN_Pos           (0U)
+#define RCC_MEMLPENR_AXISRAM3LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMLPENR_AXISRAM3LPEN               RCC_MEMLPENR_AXISRAM3LPEN_Msk        /*!< AXISRAM3 enable */
+#define RCC_MEMLPENR_AXISRAM4LPEN_Pos           (1U)
+#define RCC_MEMLPENR_AXISRAM4LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMLPENR_AXISRAM4LPEN               RCC_MEMLPENR_AXISRAM4LPEN_Msk        /*!< AXISRAM4 enable */
+#define RCC_MEMLPENR_AXISRAM5LPEN_Pos           (2U)
+#define RCC_MEMLPENR_AXISRAM5LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMLPENR_AXISRAM5LPEN               RCC_MEMLPENR_AXISRAM5LPEN_Msk        /*!< AXISRAM5 enable */
+#define RCC_MEMLPENR_AXISRAM6LPEN_Pos           (3U)
+#define RCC_MEMLPENR_AXISRAM6LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMLPENR_AXISRAM6LPEN               RCC_MEMLPENR_AXISRAM6LPEN_Msk        /*!< AXISRAM6 enable */
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos           (4U)
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMLPENR_AHBSRAM1LPEN               RCC_MEMLPENR_AHBSRAM1LPEN_Msk        /*!< AHBSRAM1 enable */
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos           (5U)
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMLPENR_AHBSRAM2LPEN               RCC_MEMLPENR_AHBSRAM2LPEN_Msk        /*!< AHBSRAM2 enable */
+#define RCC_MEMLPENR_BKPSRAMLPEN_Pos            (6U)
+#define RCC_MEMLPENR_BKPSRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MEMLPENR_BKPSRAMLPEN                RCC_MEMLPENR_BKPSRAMLPEN_Msk         /*!< BKPSRAM enable */
+#define RCC_MEMLPENR_AXISRAM1LPEN_Pos           (7U)
+#define RCC_MEMLPENR_AXISRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMLPENR_AXISRAM1LPEN               RCC_MEMLPENR_AXISRAM1LPEN_Msk        /*!< AXISRAM1 enable */
+#define RCC_MEMLPENR_AXISRAM2LPEN_Pos           (8U)
+#define RCC_MEMLPENR_AXISRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMLPENR_AXISRAM2LPEN               RCC_MEMLPENR_AXISRAM2LPEN_Msk        /*!< AXISRAM2 enable */
+#define RCC_MEMLPENR_FLEXRAMLPEN_Pos            (9U)
+#define RCC_MEMLPENR_FLEXRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MEMLPENR_FLEXRAMLPEN                RCC_MEMLPENR_FLEXRAMLPEN_Msk         /*!< FLEXRAM enable */
+#define RCC_MEMLPENR_VENCRAMLPEN_Pos            (11U)
+#define RCC_MEMLPENR_VENCRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MEMLPENR_VENCRAMLPEN                RCC_MEMLPENR_VENCRAMLPEN_Msk         /*!< VENCRAM enable */
+#define RCC_MEMLPENR_BOOTROMLPEN_Pos            (12U)
+#define RCC_MEMLPENR_BOOTROMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MEMLPENR_BOOTROMLPEN                RCC_MEMLPENR_BOOTROMLPEN_Msk         /*!< Boot ROM enable */
+
+/****************  Bit definition for RCC_AHB1LPENR register  *****************/
+#define RCC_AHB1LPENR_GPDMA1LPEN_Pos            (4U)
+#define RCC_AHB1LPENR_GPDMA1LPEN_Msk            (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPDMA1LPEN                RCC_AHB1LPENR_GPDMA1LPEN_Msk         /*!< GPDMA1 enable */
+#define RCC_AHB1LPENR_ADC12LPEN_Pos             (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk             (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                 RCC_AHB1LPENR_ADC12LPEN_Msk          /*!< ADC12 enable */
+
+/****************  Bit definition for RCC_AHB2LPENR register  *****************/
+#define RCC_AHB2LPENR_RAMCFGLPEN_Pos            (12U)
+#define RCC_AHB2LPENR_RAMCFGLPEN_Msk            (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2LPENR_RAMCFGLPEN                RCC_AHB2LPENR_RAMCFGLPEN_Msk         /*!< RAMCFG enable */
+#define RCC_AHB2LPENR_MDF1LPEN_Pos              (16U)
+#define RCC_AHB2LPENR_MDF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENR_MDF1LPEN                  RCC_AHB2LPENR_MDF1LPEN_Msk           /*!< MDF1 enable */
+#define RCC_AHB2LPENR_ADF1LPEN_Pos              (17U)
+#define RCC_AHB2LPENR_ADF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENR_ADF1LPEN                  RCC_AHB2LPENR_ADF1LPEN_Msk           /*!< ADF1 enable */
+
+/****************  Bit definition for RCC_AHB3LPENR register  *****************/
+#define RCC_AHB3LPENR_RNGLPEN_Pos               (0U)
+#define RCC_AHB3LPENR_RNGLPEN_Msk               (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3LPENR_RNGLPEN                   RCC_AHB3LPENR_RNGLPEN_Msk            /*!< RNG enable */
+#define RCC_AHB3LPENR_HASHLPEN_Pos              (1U)
+#define RCC_AHB3LPENR_HASHLPEN_Msk              (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_HASHLPEN                  RCC_AHB3LPENR_HASHLPEN_Msk           /*!< HASH enable */
+#define RCC_AHB3LPENR_PKALPEN_Pos               (8U)
+#define RCC_AHB3LPENR_PKALPEN_Msk               (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3LPENR_PKALPEN                   RCC_AHB3LPENR_PKALPEN_Msk            /*!< PKA enable */
+#define RCC_AHB3LPENR_RIFSCLPEN_Pos             (9U)
+#define RCC_AHB3LPENR_RIFSCLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */
+#define RCC_AHB3LPENR_RIFSCLPEN                 RCC_AHB3LPENR_RIFSCLPEN_Msk          /*!< RIFSC enable */
+#define RCC_AHB3LPENR_IACLPEN_Pos               (10U)
+#define RCC_AHB3LPENR_IACLPEN_Msk               (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3LPENR_IACLPEN                   RCC_AHB3LPENR_IACLPEN_Msk            /*!< IAC enable */
+#define RCC_AHB3LPENR_RISAFLPEN_Pos             (14U)
+#define RCC_AHB3LPENR_RISAFLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB3LPENR_RISAFLPEN                 RCC_AHB3LPENR_RISAFLPEN_Msk          /*!< RISAF enable */
+
+/****************  Bit definition for RCC_AHB4LPENR register  *****************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos             (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                 RCC_AHB4LPENR_GPIOALPEN_Msk          /*!< GPIO A enable */
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos             (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                 RCC_AHB4LPENR_GPIOBLPEN_Msk          /*!< GPIO B enable */
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos             (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                 RCC_AHB4LPENR_GPIOCLPEN_Msk          /*!< GPIO C enable */
+#define RCC_AHB4LPENR_GPIODLPEN_Pos             (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                 RCC_AHB4LPENR_GPIODLPEN_Msk          /*!< GPIO D enable */
+#define RCC_AHB4LPENR_GPIOELPEN_Pos             (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                 RCC_AHB4LPENR_GPIOELPEN_Msk          /*!< GPIO E enable */
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos             (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                 RCC_AHB4LPENR_GPIOFLPEN_Msk          /*!< GPIO F enable */
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos             (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                 RCC_AHB4LPENR_GPIOGLPEN_Msk          /*!< GPIO G enable */
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos             (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                 RCC_AHB4LPENR_GPIOHLPEN_Msk          /*!< GPIO H enable */
+#define RCC_AHB4LPENR_GPIONLPEN_Pos             (13U)
+#define RCC_AHB4LPENR_GPIONLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB4LPENR_GPIONLPEN                 RCC_AHB4LPENR_GPIONLPEN_Msk          /*!< GPIO N enable */
+#define RCC_AHB4LPENR_GPIOOLPEN_Pos             (14U)
+#define RCC_AHB4LPENR_GPIOOLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB4LPENR_GPIOOLPEN                 RCC_AHB4LPENR_GPIOOLPEN_Msk          /*!< GPIO O enable */
+#define RCC_AHB4LPENR_GPIOPLPEN_Pos             (15U)
+#define RCC_AHB4LPENR_GPIOPLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */
+#define RCC_AHB4LPENR_GPIOPLPEN                 RCC_AHB4LPENR_GPIOPLPEN_Msk          /*!< GPIO P enable */
+#define RCC_AHB4LPENR_GPIOQLPEN_Pos             (16U)
+#define RCC_AHB4LPENR_GPIOQLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */
+#define RCC_AHB4LPENR_GPIOQLPEN                 RCC_AHB4LPENR_GPIOQLPEN_Msk          /*!< GPIO Q enable */
+#define RCC_AHB4LPENR_PWRLPEN_Pos               (18U)
+#define RCC_AHB4LPENR_PWRLPEN_Msk               (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4LPENR_PWRLPEN                   RCC_AHB4LPENR_PWRLPEN_Msk            /*!< PWR enable */
+#define RCC_AHB4LPENR_CRCLPEN_Pos               (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk               (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                   RCC_AHB4LPENR_CRCLPEN_Msk            /*!< CRC enable */
+
+/****************  Bit definition for RCC_AHB5LPENR register  *****************/
+#define RCC_AHB5LPENR_HPDMA1LPEN_Pos            (0U)
+#define RCC_AHB5LPENR_HPDMA1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB5LPENR_HPDMA1LPEN                RCC_AHB5LPENR_HPDMA1LPEN_Msk         /*!< HPDMA1 enable */
+#define RCC_AHB5LPENR_DMA2DLPEN_Pos             (1U)
+#define RCC_AHB5LPENR_DMA2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB5LPENR_DMA2DLPEN                 RCC_AHB5LPENR_DMA2DLPEN_Msk          /*!< DMA2D enable */
+#define RCC_AHB5LPENR_JPEGLPEN_Pos              (3U)
+#define RCC_AHB5LPENR_JPEGLPEN_Msk              (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENR_JPEGLPEN                  RCC_AHB5LPENR_JPEGLPEN_Msk           /*!< JPEG enable */
+#define RCC_AHB5LPENR_FMCLPEN_Pos               (4U)
+#define RCC_AHB5LPENR_FMCLPEN_Msk               (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5LPENR_FMCLPEN                   RCC_AHB5LPENR_FMCLPEN_Msk            /*!< FMC enable */
+#define RCC_AHB5LPENR_XSPI1LPEN_Pos             (5U)
+#define RCC_AHB5LPENR_XSPI1LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB5LPENR_XSPI1LPEN                 RCC_AHB5LPENR_XSPI1LPEN_Msk          /*!< XSPI1 enable */
+#define RCC_AHB5LPENR_PSSILPEN_Pos              (6U)
+#define RCC_AHB5LPENR_PSSILPEN_Msk              (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENR_PSSILPEN                  RCC_AHB5LPENR_PSSILPEN_Msk           /*!< PSSI enable */
+#define RCC_AHB5LPENR_SDMMC2LPEN_Pos            (7U)
+#define RCC_AHB5LPENR_SDMMC2LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB5LPENR_SDMMC2LPEN                RCC_AHB5LPENR_SDMMC2LPEN_Msk         /*!< SDMMC2 enable */
+#define RCC_AHB5LPENR_SDMMC1LPEN_Pos            (8U)
+#define RCC_AHB5LPENR_SDMMC1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB5LPENR_SDMMC1LPEN                RCC_AHB5LPENR_SDMMC1LPEN_Msk         /*!< SDMMC1 enable */
+#define RCC_AHB5LPENR_XSPI2LPEN_Pos             (12U)
+#define RCC_AHB5LPENR_XSPI2LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */
+#define RCC_AHB5LPENR_XSPI2LPEN                 RCC_AHB5LPENR_XSPI2LPEN_Msk          /*!< XSPI2 enable */
+#define RCC_AHB5LPENR_XSPIMLPEN_Pos             (13U)
+#define RCC_AHB5LPENR_XSPIMLPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB5LPENR_XSPIMLPEN                 RCC_AHB5LPENR_XSPIMLPEN_Msk          /*!< XSPIM enable */
+#define RCC_AHB5LPENR_XSPI3LPEN_Pos             (17U)
+#define RCC_AHB5LPENR_XSPI3LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */
+#define RCC_AHB5LPENR_XSPI3LPEN                 RCC_AHB5LPENR_XSPI3LPEN_Msk          /*!< XSPI3 enable */
+#define RCC_AHB5LPENR_GFXMMULPEN_Pos            (19U)
+#define RCC_AHB5LPENR_GFXMMULPEN_Msk            (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB5LPENR_GFXMMULPEN                RCC_AHB5LPENR_GFXMMULPEN_Msk         /*!< GFXMMU enable */
+#define RCC_AHB5LPENR_GPU2DLPEN_Pos             (20U)
+#define RCC_AHB5LPENR_GPU2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */
+#define RCC_AHB5LPENR_GPU2DLPEN                 RCC_AHB5LPENR_GPU2DLPEN_Msk          /*!< GPU2D enable */
+#define RCC_AHB5LPENR_ETH1MACLPEN_Pos           (22U)
+#define RCC_AHB5LPENR_ETH1MACLPEN_Msk           (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5LPENR_ETH1MACLPEN               RCC_AHB5LPENR_ETH1MACLPEN_Msk        /*!< ETH1MAC enable */
+#define RCC_AHB5LPENR_ETH1TXLPEN_Pos            (23U)
+#define RCC_AHB5LPENR_ETH1TXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB5LPENR_ETH1TXLPEN                RCC_AHB5LPENR_ETH1TXLPEN_Msk         /*!< ETH1TX enable */
+#define RCC_AHB5LPENR_ETH1RXLPEN_Pos            (24U)
+#define RCC_AHB5LPENR_ETH1RXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB5LPENR_ETH1RXLPEN                RCC_AHB5LPENR_ETH1RXLPEN_Msk         /*!< ETH1RX enable */
+#define RCC_AHB5LPENR_ETH1LPEN_Pos              (25U)
+#define RCC_AHB5LPENR_ETH1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENR_ETH1LPEN                  RCC_AHB5LPENR_ETH1LPEN_Msk           /*!< ETH1 enable */
+#define RCC_AHB5LPENR_OTG1LPEN_Pos              (26U)
+#define RCC_AHB5LPENR_OTG1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENR_OTG1LPEN                  RCC_AHB5LPENR_OTG1LPEN_Msk           /*!< OTG1 enable */
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos           (27U)
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5LPENR_OTGPHY1LPEN               RCC_AHB5LPENR_OTGPHY1LPEN_Msk        /*!< OTGPHY1 enable */
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos           (28U)
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5LPENR_OTGPHY2LPEN               RCC_AHB5LPENR_OTGPHY2LPEN_Msk        /*!< OTGPHY2 enable */
+#define RCC_AHB5LPENR_OTG2LPEN_Pos              (29U)
+#define RCC_AHB5LPENR_OTG2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENR_OTG2LPEN                  RCC_AHB5LPENR_OTG2LPEN_Msk           /*!< OTG2 enable */
+
+/****************  Bit definition for RCC_APB1LPENR1 register  ****************/
+#define RCC_APB1LPENR1_TIM2LPEN_Pos             (0U)
+#define RCC_APB1LPENR1_TIM2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */
+#define RCC_APB1LPENR1_TIM2LPEN                 RCC_APB1LPENR1_TIM2LPEN_Msk          /*!< TIM2 enable */
+#define RCC_APB1LPENR1_TIM3LPEN_Pos             (1U)
+#define RCC_APB1LPENR1_TIM3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB1LPENR1_TIM3LPEN                 RCC_APB1LPENR1_TIM3LPEN_Msk          /*!< TIM3 enable */
+#define RCC_APB1LPENR1_TIM4LPEN_Pos             (2U)
+#define RCC_APB1LPENR1_TIM4LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */
+#define RCC_APB1LPENR1_TIM4LPEN                 RCC_APB1LPENR1_TIM4LPEN_Msk          /*!< TIM4 enable */
+#define RCC_APB1LPENR1_TIM5LPEN_Pos             (3U)
+#define RCC_APB1LPENR1_TIM5LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */
+#define RCC_APB1LPENR1_TIM5LPEN                 RCC_APB1LPENR1_TIM5LPEN_Msk          /*!< TIM5 enable */
+#define RCC_APB1LPENR1_TIM6LPEN_Pos             (4U)
+#define RCC_APB1LPENR1_TIM6LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */
+#define RCC_APB1LPENR1_TIM6LPEN                 RCC_APB1LPENR1_TIM6LPEN_Msk          /*!< TIM6 enable */
+#define RCC_APB1LPENR1_TIM7LPEN_Pos             (5U)
+#define RCC_APB1LPENR1_TIM7LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB1LPENR1_TIM7LPEN                 RCC_APB1LPENR1_TIM7LPEN_Msk          /*!< TIM7 enable */
+#define RCC_APB1LPENR1_TIM12LPEN_Pos            (6U)
+#define RCC_APB1LPENR1_TIM12LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR1_TIM12LPEN                RCC_APB1LPENR1_TIM12LPEN_Msk         /*!< TIM12 enable */
+#define RCC_APB1LPENR1_TIM13LPEN_Pos            (7U)
+#define RCC_APB1LPENR1_TIM13LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR1_TIM13LPEN                RCC_APB1LPENR1_TIM13LPEN_Msk         /*!< TIM13 enable */
+#define RCC_APB1LPENR1_TIM14LPEN_Pos            (8U)
+#define RCC_APB1LPENR1_TIM14LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR1_TIM14LPEN                RCC_APB1LPENR1_TIM14LPEN_Msk         /*!< TIM14 enable */
+#define RCC_APB1LPENR1_LPTIM1LPEN_Pos           (9U)
+#define RCC_APB1LPENR1_LPTIM1LPEN_Msk           (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1LPENR1_LPTIM1LPEN               RCC_APB1LPENR1_LPTIM1LPEN_Msk        /*!< LPTIM1 enable */
+#define RCC_APB1LPENR1_WWDGLPEN_Pos             (11U)
+#define RCC_APB1LPENR1_WWDGLPEN_Msk             (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */
+#define RCC_APB1LPENR1_WWDGLPEN                 RCC_APB1LPENR1_WWDGLPEN_Msk          /*!< WWDG enable */
+#define RCC_APB1LPENR1_TIM10LPEN_Pos            (12U)
+#define RCC_APB1LPENR1_TIM10LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB1LPENR1_TIM10LPEN                RCC_APB1LPENR1_TIM10LPEN_Msk         /*!< TIM10 enable */
+#define RCC_APB1LPENR1_TIM11LPEN_Pos            (13U)
+#define RCC_APB1LPENR1_TIM11LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB1LPENR1_TIM11LPEN                RCC_APB1LPENR1_TIM11LPEN_Msk         /*!< TIM11 enable */
+#define RCC_APB1LPENR1_SPI2LPEN_Pos             (14U)
+#define RCC_APB1LPENR1_SPI2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */
+#define RCC_APB1LPENR1_SPI2LPEN                 RCC_APB1LPENR1_SPI2LPEN_Msk          /*!< SPI2 enable */
+#define RCC_APB1LPENR1_SPI3LPEN_Pos             (15U)
+#define RCC_APB1LPENR1_SPI3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB1LPENR1_SPI3LPEN                 RCC_APB1LPENR1_SPI3LPEN_Msk          /*!< SPI3 enable */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos         (16U)
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk         (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos)    /*!< 0x00010000 */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN             RCC_APB1LPENR1_SPDIFRX1LPEN_Msk      /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENR1_USART2LPEN_Pos           (17U)
+#define RCC_APB1LPENR1_USART2LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1LPENR1_USART2LPEN               RCC_APB1LPENR1_USART2LPEN_Msk        /*!< USART2 enable */
+#define RCC_APB1LPENR1_USART3LPEN_Pos           (18U)
+#define RCC_APB1LPENR1_USART3LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1LPENR1_USART3LPEN               RCC_APB1LPENR1_USART3LPEN_Msk        /*!< USART3 enable */
+#define RCC_APB1LPENR1_UART4LPEN_Pos            (19U)
+#define RCC_APB1LPENR1_UART4LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR1_UART4LPEN                RCC_APB1LPENR1_UART4LPEN_Msk         /*!< UART4 enable */
+#define RCC_APB1LPENR1_UART5LPEN_Pos            (20U)
+#define RCC_APB1LPENR1_UART5LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR1_UART5LPEN                RCC_APB1LPENR1_UART5LPEN_Msk         /*!< UART5 enable */
+#define RCC_APB1LPENR1_I2C1LPEN_Pos             (21U)
+#define RCC_APB1LPENR1_I2C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */
+#define RCC_APB1LPENR1_I2C1LPEN                 RCC_APB1LPENR1_I2C1LPEN_Msk          /*!< I2C1 enable */
+#define RCC_APB1LPENR1_I2C2LPEN_Pos             (22U)
+#define RCC_APB1LPENR1_I2C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */
+#define RCC_APB1LPENR1_I2C2LPEN                 RCC_APB1LPENR1_I2C2LPEN_Msk          /*!< I2C2 enable */
+#define RCC_APB1LPENR1_I2C3LPEN_Pos             (23U)
+#define RCC_APB1LPENR1_I2C3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */
+#define RCC_APB1LPENR1_I2C3LPEN                 RCC_APB1LPENR1_I2C3LPEN_Msk          /*!< I2C3 enable */
+#define RCC_APB1LPENR1_I3C1LPEN_Pos             (24U)
+#define RCC_APB1LPENR1_I3C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */
+#define RCC_APB1LPENR1_I3C1LPEN                 RCC_APB1LPENR1_I3C1LPEN_Msk          /*!< I3C1 enable */
+#define RCC_APB1LPENR1_I3C2LPEN_Pos             (25U)
+#define RCC_APB1LPENR1_I3C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */
+#define RCC_APB1LPENR1_I3C2LPEN                 RCC_APB1LPENR1_I3C2LPEN_Msk          /*!< I3C2 enable */
+#define RCC_APB1LPENR1_UART7LPEN_Pos            (30U)
+#define RCC_APB1LPENR1_UART7LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR1_UART7LPEN                RCC_APB1LPENR1_UART7LPEN_Msk         /*!< UART7 enable */
+#define RCC_APB1LPENR1_UART8LPEN_Pos            (31U)
+#define RCC_APB1LPENR1_UART8LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR1_UART8LPEN                RCC_APB1LPENR1_UART8LPEN_Msk         /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1LPENR2 register  ****************/
+#define RCC_APB1LPENR2_MDIOSLPEN_Pos            (5U)
+#define RCC_APB1LPENR2_MDIOSLPEN_Msk            (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR2_MDIOSLPEN                RCC_APB1LPENR2_MDIOSLPEN_Msk         /*!< MDIOS enable in Sleep mode */
+#define RCC_APB1LPENR2_FDCANLPEN_Pos            (8U)
+#define RCC_APB1LPENR2_FDCANLPEN_Msk            (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR2_FDCANLPEN                RCC_APB1LPENR2_FDCANLPEN_Msk         /*!< FDCAN enablein Sleep mode */
+#define RCC_APB1LPENR2_UCPD1LPEN_Pos            (18U)
+#define RCC_APB1LPENR2_UCPD1LPEN_Msk            (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR2_UCPD1LPEN                RCC_APB1LPENR2_UCPD1LPEN_Msk         /*!< UCPD1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_APB2LPENR register  *****************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos              (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                  RCC_APB2LPENR_TIM1LPEN_Msk           /*!< TIM1 enable */
+#define RCC_APB2LPENR_TIM8LPEN_Pos              (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                  RCC_APB2LPENR_TIM8LPEN_Msk           /*!< TIM8 enable */
+#define RCC_APB2LPENR_USART1LPEN_Pos            (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN                RCC_APB2LPENR_USART1LPEN_Msk         /*!< USART1 enable */
+#define RCC_APB2LPENR_USART6LPEN_Pos            (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN                RCC_APB2LPENR_USART6LPEN_Msk         /*!< USART6 enable */
+#define RCC_APB2LPENR_UART9LPEN_Pos             (6U)
+#define RCC_APB2LPENR_UART9LPEN_Msk             (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */
+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk          /*!< UART9 enable */
+#define RCC_APB2LPENR_USART10LPEN_Pos           (7U)
+#define RCC_APB2LPENR_USART10LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk        /*!< USART10 enable */
+#define RCC_APB2LPENR_SPI1LPEN_Pos              (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                  RCC_APB2LPENR_SPI1LPEN_Msk           /*!< SPI1 enable */
+#define RCC_APB2LPENR_SPI4LPEN_Pos              (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                  RCC_APB2LPENR_SPI4LPEN_Msk           /*!< SPI4 enable */
+#define RCC_APB2LPENR_TIM18LPEN_Pos             (15U)
+#define RCC_APB2LPENR_TIM18LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB2LPENR_TIM18LPEN                 RCC_APB2LPENR_TIM18LPEN_Msk          /*!< TIM18 enable */
+#define RCC_APB2LPENR_TIM15LPEN_Pos             (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                 RCC_APB2LPENR_TIM15LPEN_Msk          /*!< TIM15 enable */
+#define RCC_APB2LPENR_TIM16LPEN_Pos             (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                 RCC_APB2LPENR_TIM16LPEN_Msk          /*!< TIM16 enable */
+#define RCC_APB2LPENR_TIM17LPEN_Pos             (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                 RCC_APB2LPENR_TIM17LPEN_Msk          /*!< TIM17 enable */
+#define RCC_APB2LPENR_TIM9LPEN_Pos              (19U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENR_TIM9LPEN                  RCC_APB2LPENR_TIM9LPEN_Msk           /*!< TIM9 enable */
+#define RCC_APB2LPENR_SPI5LPEN_Pos              (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                  RCC_APB2LPENR_SPI5LPEN_Msk           /*!< SPI5 enable */
+#define RCC_APB2LPENR_SAI1LPEN_Pos              (21U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SAI1LPEN                  RCC_APB2LPENR_SAI1LPEN_Msk           /*!< SAI1 enable */
+#define RCC_APB2LPENR_SAI2LPEN_Pos              (22U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI2LPEN                  RCC_APB2LPENR_SAI2LPEN_Msk           /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENR register  *****************/
+#define RCC_APB3LPENR_DFTLPEN_Pos               (2U)
+#define RCC_APB3LPENR_DFTLPEN_Msk               (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos)  /*!< 0x00000004 */
+#define RCC_APB3LPENR_DFTLPEN                   RCC_APB3LPENR_DFTLPEN_Msk            /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4LPENR1 register  ****************/
+#define RCC_APB4LPENR1_HDPLPEN_Pos              (2U)
+#define RCC_APB4LPENR1_HDPLPEN_Msk              (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR1_HDPLPEN                  RCC_APB4LPENR1_HDPLPEN_Msk           /*!< HDP enable */
+#define RCC_APB4LPENR1_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR1_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos)   /*!< 0x00000008 */
+#define RCC_APB4LPENR1_LPUART1LPEN              RCC_APB4LPENR1_LPUART1LPEN_Msk       /*!< LPUART1 enable */
+#define RCC_APB4LPENR1_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR1_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB4LPENR1_SPI6LPEN                 RCC_APB4LPENR1_SPI6LPEN_Msk          /*!< SPI6 enable */
+#define RCC_APB4LPENR1_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR1_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */
+#define RCC_APB4LPENR1_I2C4LPEN                 RCC_APB4LPENR1_I2C4LPEN_Msk          /*!< I2C4 enable */
+#define RCC_APB4LPENR1_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR1_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4LPENR1_LPTIM2LPEN               RCC_APB4LPENR1_LPTIM2LPEN_Msk        /*!< LPTIM2 enable */
+#define RCC_APB4LPENR1_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR1_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4LPENR1_LPTIM3LPEN               RCC_APB4LPENR1_LPTIM3LPEN_Msk        /*!< LPTIM3 enable */
+#define RCC_APB4LPENR1_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR1_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4LPENR1_LPTIM4LPEN               RCC_APB4LPENR1_LPTIM4LPEN_Msk        /*!< LPTIM4 enable */
+#define RCC_APB4LPENR1_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR1_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4LPENR1_LPTIM5LPEN               RCC_APB4LPENR1_LPTIM5LPEN_Msk        /*!< LPTIM5 enable */
+#define RCC_APB4LPENR1_VREFBUFLPEN_Pos          (15U)
+#define RCC_APB4LPENR1_VREFBUFLPEN_Msk          (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos)   /*!< 0x00008000 */
+#define RCC_APB4LPENR1_VREFBUFLPEN              RCC_APB4LPENR1_VREFBUFLPEN_Msk       /*!< VREFBUF enable */
+#define RCC_APB4LPENR1_RTCLPEN_Pos              (16U)
+#define RCC_APB4LPENR1_RTCLPEN_Msk              (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR1_RTCLPEN                  RCC_APB4LPENR1_RTCLPEN_Msk           /*!< RTC enable */
+#define RCC_APB4LPENR1_RTCAPBLPEN_Pos           (17U)
+#define RCC_APB4LPENR1_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4LPENR1_RTCAPBLPEN               RCC_APB4LPENR1_RTCAPBLPEN_Msk        /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4LPENR2 register  ****************/
+#define RCC_APB4LPENR2_SYSCFGLPEN_Pos           (0U)
+#define RCC_APB4LPENR2_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4LPENR2_SYSCFGLPEN               RCC_APB4LPENR2_SYSCFGLPEN_Msk        /*!< SYSCFG enable */
+#define RCC_APB4LPENR2_BSECLPEN_Pos             (1U)
+#define RCC_APB4LPENR2_BSECLPEN_Msk             (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB4LPENR2_BSECLPEN                 RCC_APB4LPENR2_BSECLPEN_Msk          /*!< BSEC enable */
+#define RCC_APB4LPENR2_DTSLPEN_Pos              (2U)
+#define RCC_APB4LPENR2_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR2_DTSLPEN                  RCC_APB4LPENR2_DTSLPEN_Msk           /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENR register  *****************/
+#define RCC_APB5LPENR_LTDCLPEN_Pos              (1U)
+#define RCC_APB5LPENR_LTDCLPEN_Msk              (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENR_LTDCLPEN                  RCC_APB5LPENR_LTDCLPEN_Msk           /*!< LTDC enable */
+#define RCC_APB5LPENR_DCMIPPLPEN_Pos            (2U)
+#define RCC_APB5LPENR_DCMIPPLPEN_Msk            (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB5LPENR_DCMIPPLPEN                RCC_APB5LPENR_DCMIPPLPEN_Msk         /*!< DCMIPP enable */
+#define RCC_APB5LPENR_GFXTIMLPEN_Pos            (4U)
+#define RCC_APB5LPENR_GFXTIMLPEN_Msk            (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB5LPENR_GFXTIMLPEN                RCC_APB5LPENR_GFXTIMLPEN_Msk         /*!< GFXTIM enable */
+#define RCC_APB5LPENR_VENCLPEN_Pos              (5U)
+#define RCC_APB5LPENR_VENCLPEN_Msk              (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENR_VENCLPEN                  RCC_APB5LPENR_VENCLPEN_Msk           /*!< VENC enable */
+#define RCC_APB5LPENR_CSILPEN_Pos               (6U)
+#define RCC_APB5LPENR_CSILPEN_Msk               (0x1UL << RCC_APB5LPENR_CSILPEN_Pos)  /*!< 0x00000040 */
+#define RCC_APB5LPENR_CSILPEN                   RCC_APB5LPENR_CSILPEN_Msk            /*!< CSI enable */
+
+/*******************  Bit definition for RCC_RDCR register  *******************/
+#define RCC_RDCR_MRD_Pos                        (16U)
+#define RCC_RDCR_MRD_Msk                        (0x1FUL << RCC_RDCR_MRD_Pos)          /*!< 0x001F0000 */
+#define RCC_RDCR_MRD                            RCC_RDCR_MRD_Msk                     /*!< Minimum reset duration */
+
+/*****************  Bit definition for RCC_SECCFGR0 register  *****************/
+#define RCC_SECCFGR0_LSISEC_Pos                 (0U)
+#define RCC_SECCFGR0_LSISEC_Msk                 (0x1UL << RCC_SECCFGR0_LSISEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR0_LSISEC                     RCC_SECCFGR0_LSISEC_Msk              /*!< Secure protection of LSI oscillator configuration bits */
+#define RCC_SECCFGR0_LSESEC_Pos                 (1U)
+#define RCC_SECCFGR0_LSESEC_Msk                 (0x1UL << RCC_SECCFGR0_LSESEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR0_LSESEC                     RCC_SECCFGR0_LSESEC_Msk              /*!< Secure protection of LSE oscillator configuration bits */
+#define RCC_SECCFGR0_MSISEC_Pos                 (2U)
+#define RCC_SECCFGR0_MSISEC_Msk                 (0x1UL << RCC_SECCFGR0_MSISEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR0_MSISEC                     RCC_SECCFGR0_MSISEC_Msk              /*!< Secure protection of MSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSISEC_Pos                 (3U)
+#define RCC_SECCFGR0_HSISEC_Msk                 (0x1UL << RCC_SECCFGR0_HSISEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR0_HSISEC                     RCC_SECCFGR0_HSISEC_Msk              /*!< Secure protection of HSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSESEC_Pos                 (4U)
+#define RCC_SECCFGR0_HSESEC_Msk                 (0x1UL << RCC_SECCFGR0_HSESEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR0_HSESEC                     RCC_SECCFGR0_HSESEC_Msk              /*!< Secure protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR0 register  *****************/
+#define RCC_PRIVCFGR0_LSIPRIV_Pos               (0U)
+#define RCC_PRIVCFGR0_LSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR0_LSIPRIV                   RCC_PRIVCFGR0_LSIPRIV_Msk            /*!< Privileged protection of LSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_LSEPRIV_Pos               (1U)
+#define RCC_PRIVCFGR0_LSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR0_LSEPRIV                   RCC_PRIVCFGR0_LSEPRIV_Msk            /*!< Privileged protection of LSE oscillator configuration bits */
+#define RCC_PRIVCFGR0_MSIPRIV_Pos               (2U)
+#define RCC_PRIVCFGR0_MSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR0_MSIPRIV                   RCC_PRIVCFGR0_MSIPRIV_Msk            /*!< Privileged protection of MSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSIPRIV_Pos               (3U)
+#define RCC_PRIVCFGR0_HSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR0_HSIPRIV                   RCC_PRIVCFGR0_HSIPRIV_Msk            /*!< Privileged protection of HSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSEPRIV_Pos               (4U)
+#define RCC_PRIVCFGR0_HSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR0_HSEPRIV                   RCC_PRIVCFGR0_HSEPRIV_Msk            /*!< Privileged protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR0 register  *****************/
+#define RCC_LOCKCFGR0_LSILOCK_Pos               (0U)
+#define RCC_LOCKCFGR0_LSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR0_LSILOCK                   RCC_LOCKCFGR0_LSILOCK_Msk            /*!< Locked protection of LSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_LSELOCK_Pos               (1U)
+#define RCC_LOCKCFGR0_LSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR0_LSELOCK                   RCC_LOCKCFGR0_LSELOCK_Msk            /*!< Locked protection of LSE oscillator configuration bits */
+#define RCC_LOCKCFGR0_MSILOCK_Pos               (2U)
+#define RCC_LOCKCFGR0_MSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR0_MSILOCK                   RCC_LOCKCFGR0_MSILOCK_Msk            /*!< Locked protection of MSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSILOCK_Pos               (3U)
+#define RCC_LOCKCFGR0_HSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR0_HSILOCK                   RCC_LOCKCFGR0_HSILOCK_Msk            /*!< Locked protection of HSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSELOCK_Pos               (4U)
+#define RCC_LOCKCFGR0_HSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR0_HSELOCK                   RCC_LOCKCFGR0_HSELOCK_Msk            /*!< Locked protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR0 register  *****************/
+#define RCC_PUBCFGR0_LSIPUB_Pos                 (0U)
+#define RCC_PUBCFGR0_LSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR0_LSIPUB                     RCC_PUBCFGR0_LSIPUB_Msk              /*!< Public protection of LSI oscillator configuration bits */
+#define RCC_PUBCFGR0_LSEPUB_Pos                 (1U)
+#define RCC_PUBCFGR0_LSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR0_LSEPUB                     RCC_PUBCFGR0_LSEPUB_Msk              /*!< Public protection of LSE oscillator configuration bits */
+#define RCC_PUBCFGR0_MSIPUB_Pos                 (2U)
+#define RCC_PUBCFGR0_MSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR0_MSIPUB                     RCC_PUBCFGR0_MSIPUB_Msk              /*!< Public protection of MSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSIPUB_Pos                 (3U)
+#define RCC_PUBCFGR0_HSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR0_HSIPUB                     RCC_PUBCFGR0_HSIPUB_Msk              /*!< Public protection of HSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSEPUB_Pos                 (4U)
+#define RCC_PUBCFGR0_HSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR0_HSEPUB                     RCC_PUBCFGR0_HSEPUB_Msk              /*!< Public protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR1 register  *****************/
+#define RCC_SECCFGR1_PLL1SEC_Pos                (0U)
+#define RCC_SECCFGR1_PLL1SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos)   /*!< 0x00000001 */
+#define RCC_SECCFGR1_PLL1SEC                    RCC_SECCFGR1_PLL1SEC_Msk             /*!< Secure protection of PLL1 configuration bits */
+#define RCC_SECCFGR1_PLL2SEC_Pos                (1U)
+#define RCC_SECCFGR1_PLL2SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos)   /*!< 0x00000002 */
+#define RCC_SECCFGR1_PLL2SEC                    RCC_SECCFGR1_PLL2SEC_Msk             /*!< Secure protection of PLL2 configuration bits */
+#define RCC_SECCFGR1_PLL3SEC_Pos                (2U)
+#define RCC_SECCFGR1_PLL3SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR1_PLL3SEC                    RCC_SECCFGR1_PLL3SEC_Msk             /*!< Secure protection of PLL3 configuration bits */
+#define RCC_SECCFGR1_PLL4SEC_Pos                (3U)
+#define RCC_SECCFGR1_PLL4SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR1_PLL4SEC                    RCC_SECCFGR1_PLL4SEC_Msk             /*!< Secure protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR1 register  *****************/
+#define RCC_PRIVCFGR1_PLL1PRIV_Pos              (0U)
+#define RCC_PRIVCFGR1_PLL1PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGR1_PLL1PRIV                  RCC_PRIVCFGR1_PLL1PRIV_Msk           /*!< Privileged protection of PLL1 configuration bits */
+#define RCC_PRIVCFGR1_PLL2PRIV_Pos              (1U)
+#define RCC_PRIVCFGR1_PLL2PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR1_PLL2PRIV                  RCC_PRIVCFGR1_PLL2PRIV_Msk           /*!< Privileged protection of PLL2 configuration bits */
+#define RCC_PRIVCFGR1_PLL3PRIV_Pos              (2U)
+#define RCC_PRIVCFGR1_PLL3PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR1_PLL3PRIV                  RCC_PRIVCFGR1_PLL3PRIV_Msk           /*!< Privileged protection of PLL3 configuration bits */
+#define RCC_PRIVCFGR1_PLL4PRIV_Pos              (3U)
+#define RCC_PRIVCFGR1_PLL4PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR1_PLL4PRIV                  RCC_PRIVCFGR1_PLL4PRIV_Msk           /*!< Privileged protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR1 register  *****************/
+#define RCC_LOCKCFGR1_PLL1LOCK_Pos              (0U)
+#define RCC_LOCKCFGR1_PLL1LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */
+#define RCC_LOCKCFGR1_PLL1LOCK                  RCC_LOCKCFGR1_PLL1LOCK_Msk           /*!< Locked protection of PLL1 configuration bits */
+#define RCC_LOCKCFGR1_PLL2LOCK_Pos              (1U)
+#define RCC_LOCKCFGR1_PLL2LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR1_PLL2LOCK                  RCC_LOCKCFGR1_PLL2LOCK_Msk           /*!< Locked protection of PLL2 configuration bits */
+#define RCC_LOCKCFGR1_PLL3LOCK_Pos              (2U)
+#define RCC_LOCKCFGR1_PLL3LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR1_PLL3LOCK                  RCC_LOCKCFGR1_PLL3LOCK_Msk           /*!< Locked protection of PLL3 configuration bits */
+#define RCC_LOCKCFGR1_PLL4LOCK_Pos              (3U)
+#define RCC_LOCKCFGR1_PLL4LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR1_PLL4LOCK                  RCC_LOCKCFGR1_PLL4LOCK_Msk           /*!< Locked protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR1 register  *****************/
+#define RCC_PUBCFGR1_PLL1PUB_Pos                (0U)
+#define RCC_PUBCFGR1_PLL1PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGR1_PLL1PUB                    RCC_PUBCFGR1_PLL1PUB_Msk             /*!< Public protection of PLL1 configuration bits */
+#define RCC_PUBCFGR1_PLL2PUB_Pos                (1U)
+#define RCC_PUBCFGR1_PLL2PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGR1_PLL2PUB                    RCC_PUBCFGR1_PLL2PUB_Msk             /*!< Public protection of PLL2 configuration bits */
+#define RCC_PUBCFGR1_PLL3PUB_Pos                (2U)
+#define RCC_PUBCFGR1_PLL3PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR1_PLL3PUB                    RCC_PUBCFGR1_PLL3PUB_Msk             /*!< Public protection of PLL3 configuration bits */
+#define RCC_PUBCFGR1_PLL4PUB_Pos                (3U)
+#define RCC_PUBCFGR1_PLL4PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR1_PLL4PUB                    RCC_PUBCFGR1_PLL4PUB_Msk             /*!< Public protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR2 register  *****************/
+#define RCC_SECCFGR2_IC1SEC_Pos                 (0U)
+#define RCC_SECCFGR2_IC1SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC1SEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR2_IC1SEC                     RCC_SECCFGR2_IC1SEC_Msk              /*!< Secure protection of IC1 divider configuration bits */
+#define RCC_SECCFGR2_IC2SEC_Pos                 (1U)
+#define RCC_SECCFGR2_IC2SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC2SEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR2_IC2SEC                     RCC_SECCFGR2_IC2SEC_Msk              /*!< Secure protection of IC2 divider configuration bits */
+#define RCC_SECCFGR2_IC3SEC_Pos                 (2U)
+#define RCC_SECCFGR2_IC3SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC3SEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR2_IC3SEC                     RCC_SECCFGR2_IC3SEC_Msk              /*!< Secure protection of IC3 divider configuration bits */
+#define RCC_SECCFGR2_IC4SEC_Pos                 (3U)
+#define RCC_SECCFGR2_IC4SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC4SEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR2_IC4SEC                     RCC_SECCFGR2_IC4SEC_Msk              /*!< Secure protection of IC4 divider configuration bits */
+#define RCC_SECCFGR2_IC5SEC_Pos                 (4U)
+#define RCC_SECCFGR2_IC5SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC5SEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR2_IC5SEC                     RCC_SECCFGR2_IC5SEC_Msk              /*!< Secure protection of IC5 divider configuration bits */
+#define RCC_SECCFGR2_IC6SEC_Pos                 (5U)
+#define RCC_SECCFGR2_IC6SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC6SEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR2_IC6SEC                     RCC_SECCFGR2_IC6SEC_Msk              /*!< Secure protection of IC6 divider configuration bits */
+#define RCC_SECCFGR2_IC7SEC_Pos                 (6U)
+#define RCC_SECCFGR2_IC7SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC7SEC_Pos)    /*!< 0x00000040 */
+#define RCC_SECCFGR2_IC7SEC                     RCC_SECCFGR2_IC7SEC_Msk              /*!< Secure protection of IC7 divider configuration bits */
+#define RCC_SECCFGR2_IC8SEC_Pos                 (7U)
+#define RCC_SECCFGR2_IC8SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC8SEC_Pos)    /*!< 0x00000080 */
+#define RCC_SECCFGR2_IC8SEC                     RCC_SECCFGR2_IC8SEC_Msk              /*!< Secure protection of IC8 divider configuration bits */
+#define RCC_SECCFGR2_IC9SEC_Pos                 (8U)
+#define RCC_SECCFGR2_IC9SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC9SEC_Pos)    /*!< 0x00000100 */
+#define RCC_SECCFGR2_IC9SEC                     RCC_SECCFGR2_IC9SEC_Msk              /*!< Secure protection of IC9 divider configuration bits */
+#define RCC_SECCFGR2_IC10SEC_Pos                (9U)
+#define RCC_SECCFGR2_IC10SEC_Msk                (0x1UL << RCC_SECCFGR2_IC10SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR2_IC10SEC                    RCC_SECCFGR2_IC10SEC_Msk             /*!< Secure protection of IC10 divider configuration bits */
+#define RCC_SECCFGR2_IC11SEC_Pos                (10U)
+#define RCC_SECCFGR2_IC11SEC_Msk                (0x1UL << RCC_SECCFGR2_IC11SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR2_IC11SEC                    RCC_SECCFGR2_IC11SEC_Msk             /*!< Secure protection of IC11 divider configuration bits */
+#define RCC_SECCFGR2_IC12SEC_Pos                (11U)
+#define RCC_SECCFGR2_IC12SEC_Msk                (0x1UL << RCC_SECCFGR2_IC12SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR2_IC12SEC                    RCC_SECCFGR2_IC12SEC_Msk             /*!< Secure protection of IC12 divider configuration bits */
+#define RCC_SECCFGR2_IC13SEC_Pos                (12U)
+#define RCC_SECCFGR2_IC13SEC_Msk                (0x1UL << RCC_SECCFGR2_IC13SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR2_IC13SEC                    RCC_SECCFGR2_IC13SEC_Msk             /*!< Secure protection of IC13 divider configuration bits */
+#define RCC_SECCFGR2_IC14SEC_Pos                (13U)
+#define RCC_SECCFGR2_IC14SEC_Msk                (0x1UL << RCC_SECCFGR2_IC14SEC_Pos)   /*!< 0x00002000 */
+#define RCC_SECCFGR2_IC14SEC                    RCC_SECCFGR2_IC14SEC_Msk             /*!< Secure protection of IC14 divider configuration bits */
+#define RCC_SECCFGR2_IC15SEC_Pos                (14U)
+#define RCC_SECCFGR2_IC15SEC_Msk                (0x1UL << RCC_SECCFGR2_IC15SEC_Pos)   /*!< 0x00004000 */
+#define RCC_SECCFGR2_IC15SEC                    RCC_SECCFGR2_IC15SEC_Msk             /*!< Secure protection of IC15 divider configuration bits */
+#define RCC_SECCFGR2_IC16SEC_Pos                (15U)
+#define RCC_SECCFGR2_IC16SEC_Msk                (0x1UL << RCC_SECCFGR2_IC16SEC_Pos)   /*!< 0x00008000 */
+#define RCC_SECCFGR2_IC16SEC                    RCC_SECCFGR2_IC16SEC_Msk             /*!< Secure protection of IC16 divider configuration bits */
+#define RCC_SECCFGR2_IC17SEC_Pos                (16U)
+#define RCC_SECCFGR2_IC17SEC_Msk                (0x1UL << RCC_SECCFGR2_IC17SEC_Pos)   /*!< 0x00010000 */
+#define RCC_SECCFGR2_IC17SEC                    RCC_SECCFGR2_IC17SEC_Msk             /*!< Secure protection of IC17 divider configuration bits */
+#define RCC_SECCFGR2_IC18SEC_Pos                (17U)
+#define RCC_SECCFGR2_IC18SEC_Msk                (0x1UL << RCC_SECCFGR2_IC18SEC_Pos)   /*!< 0x00020000 */
+#define RCC_SECCFGR2_IC18SEC                    RCC_SECCFGR2_IC18SEC_Msk             /*!< Secure protection of IC18 divider configuration bits */
+#define RCC_SECCFGR2_IC19SEC_Pos                (18U)
+#define RCC_SECCFGR2_IC19SEC_Msk                (0x1UL << RCC_SECCFGR2_IC19SEC_Pos)   /*!< 0x00040000 */
+#define RCC_SECCFGR2_IC19SEC                    RCC_SECCFGR2_IC19SEC_Msk             /*!< Secure protection of IC19 divider configuration bits */
+#define RCC_SECCFGR2_IC20SEC_Pos                (19U)
+#define RCC_SECCFGR2_IC20SEC_Msk                (0x1UL << RCC_SECCFGR2_IC20SEC_Pos)   /*!< 0x00080000 */
+#define RCC_SECCFGR2_IC20SEC                    RCC_SECCFGR2_IC20SEC_Msk             /*!< Secure protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR2 register  *****************/
+#define RCC_PRIVCFGR2_IC1PRIV_Pos               (0U)
+#define RCC_PRIVCFGR2_IC1PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR2_IC1PRIV                   RCC_PRIVCFGR2_IC1PRIV_Msk            /*!< Privileged protection of IC1 divider configuration bits */
+#define RCC_PRIVCFGR2_IC2PRIV_Pos               (1U)
+#define RCC_PRIVCFGR2_IC2PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR2_IC2PRIV                   RCC_PRIVCFGR2_IC2PRIV_Msk            /*!< Privileged protection of IC2 divider configuration bits */
+#define RCC_PRIVCFGR2_IC3PRIV_Pos               (2U)
+#define RCC_PRIVCFGR2_IC3PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR2_IC3PRIV                   RCC_PRIVCFGR2_IC3PRIV_Msk            /*!< Privileged protection of IC3 divider configuration bits */
+#define RCC_PRIVCFGR2_IC4PRIV_Pos               (3U)
+#define RCC_PRIVCFGR2_IC4PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR2_IC4PRIV                   RCC_PRIVCFGR2_IC4PRIV_Msk            /*!< Privileged protection of IC4 divider configuration bits */
+#define RCC_PRIVCFGR2_IC5PRIV_Pos               (4U)
+#define RCC_PRIVCFGR2_IC5PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR2_IC5PRIV                   RCC_PRIVCFGR2_IC5PRIV_Msk            /*!< Privileged protection of IC5 divider configuration bits */
+#define RCC_PRIVCFGR2_IC6PRIV_Pos               (5U)
+#define RCC_PRIVCFGR2_IC6PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR2_IC6PRIV                   RCC_PRIVCFGR2_IC6PRIV_Msk            /*!< Privileged protection of IC6 divider configuration bits */
+#define RCC_PRIVCFGR2_IC7PRIV_Pos               (6U)
+#define RCC_PRIVCFGR2_IC7PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos)  /*!< 0x00000040 */
+#define RCC_PRIVCFGR2_IC7PRIV                   RCC_PRIVCFGR2_IC7PRIV_Msk            /*!< Privileged protection of IC7 divider configuration bits */
+#define RCC_PRIVCFGR2_IC8PRIV_Pos               (7U)
+#define RCC_PRIVCFGR2_IC8PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos)  /*!< 0x00000080 */
+#define RCC_PRIVCFGR2_IC8PRIV                   RCC_PRIVCFGR2_IC8PRIV_Msk            /*!< Privileged protection of IC8 divider configuration bits */
+#define RCC_PRIVCFGR2_IC9PRIV_Pos               (8U)
+#define RCC_PRIVCFGR2_IC9PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos)  /*!< 0x00000100 */
+#define RCC_PRIVCFGR2_IC9PRIV                   RCC_PRIVCFGR2_IC9PRIV_Msk            /*!< Privileged protection of IC9 divider configuration bits */
+#define RCC_PRIVCFGR2_IC10PRIV_Pos              (9U)
+#define RCC_PRIVCFGR2_IC10PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR2_IC10PRIV                  RCC_PRIVCFGR2_IC10PRIV_Msk           /*!< Privileged protection of IC10 divider configuration bits */
+#define RCC_PRIVCFGR2_IC11PRIV_Pos              (10U)
+#define RCC_PRIVCFGR2_IC11PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR2_IC11PRIV                  RCC_PRIVCFGR2_IC11PRIV_Msk           /*!< Privileged protection of IC11 divider configuration bits */
+#define RCC_PRIVCFGR2_IC12PRIV_Pos              (11U)
+#define RCC_PRIVCFGR2_IC12PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR2_IC12PRIV                  RCC_PRIVCFGR2_IC12PRIV_Msk           /*!< Privileged protection of IC12 divider configuration bits */
+#define RCC_PRIVCFGR2_IC13PRIV_Pos              (12U)
+#define RCC_PRIVCFGR2_IC13PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR2_IC13PRIV                  RCC_PRIVCFGR2_IC13PRIV_Msk           /*!< Privileged protection of IC13 divider configuration bits */
+#define RCC_PRIVCFGR2_IC14PRIV_Pos              (13U)
+#define RCC_PRIVCFGR2_IC14PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGR2_IC14PRIV                  RCC_PRIVCFGR2_IC14PRIV_Msk           /*!< Privileged protection of IC14 divider configuration bits */
+#define RCC_PRIVCFGR2_IC15PRIV_Pos              (14U)
+#define RCC_PRIVCFGR2_IC15PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGR2_IC15PRIV                  RCC_PRIVCFGR2_IC15PRIV_Msk           /*!< Privileged protection of IC15 divider configuration bits */
+#define RCC_PRIVCFGR2_IC16PRIV_Pos              (15U)
+#define RCC_PRIVCFGR2_IC16PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGR2_IC16PRIV                  RCC_PRIVCFGR2_IC16PRIV_Msk           /*!< Privileged protection of IC16 divider configuration bits */
+#define RCC_PRIVCFGR2_IC17PRIV_Pos              (16U)
+#define RCC_PRIVCFGR2_IC17PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGR2_IC17PRIV                  RCC_PRIVCFGR2_IC17PRIV_Msk           /*!< Privileges protection of IC17 divider configuration bits */
+#define RCC_PRIVCFGR2_IC18PRIV_Pos              (17U)
+#define RCC_PRIVCFGR2_IC18PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGR2_IC18PRIV                  RCC_PRIVCFGR2_IC18PRIV_Msk           /*!< Privilege protection of IC18 divider configuration bits */
+#define RCC_PRIVCFGR2_IC19PRIV_Pos              (18U)
+#define RCC_PRIVCFGR2_IC19PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGR2_IC19PRIV                  RCC_PRIVCFGR2_IC19PRIV_Msk           /*!< Privileged protection of IC19 divider configuration bits */
+#define RCC_PRIVCFGR2_IC20PRIV_Pos              (19U)
+#define RCC_PRIVCFGR2_IC20PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGR2_IC20PRIV                  RCC_PRIVCFGR2_IC20PRIV_Msk           /*!< Privileged protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR2 register  *****************/
+#define RCC_LOCKCFGR2_IC1LOCK_Pos               (0U)
+#define RCC_LOCKCFGR2_IC1LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR2_IC1LOCK                   RCC_LOCKCFGR2_IC1LOCK_Msk            /*!< Locked protection of IC1 divider configuration bits */
+#define RCC_LOCKCFGR2_IC2LOCK_Pos               (1U)
+#define RCC_LOCKCFGR2_IC2LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR2_IC2LOCK                   RCC_LOCKCFGR2_IC2LOCK_Msk            /*!< Locked protection of IC2 divider configuration bits */
+#define RCC_LOCKCFGR2_IC3LOCK_Pos               (2U)
+#define RCC_LOCKCFGR2_IC3LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR2_IC3LOCK                   RCC_LOCKCFGR2_IC3LOCK_Msk            /*!< Locked protection of IC3 divider configuration bits */
+#define RCC_LOCKCFGR2_IC4LOCK_Pos               (3U)
+#define RCC_LOCKCFGR2_IC4LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR2_IC4LOCK                   RCC_LOCKCFGR2_IC4LOCK_Msk            /*!< Locked protection of IC4 divider configuration bits */
+#define RCC_LOCKCFGR2_IC5LOCK_Pos               (4U)
+#define RCC_LOCKCFGR2_IC5LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR2_IC5LOCK                   RCC_LOCKCFGR2_IC5LOCK_Msk            /*!< Locked protection of IC5 divider configuration bits */
+#define RCC_LOCKCFGR2_IC6LOCK_Pos               (5U)
+#define RCC_LOCKCFGR2_IC6LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR2_IC6LOCK                   RCC_LOCKCFGR2_IC6LOCK_Msk            /*!< Locked protection of IC6 divider configuration bits */
+#define RCC_LOCKCFGR2_IC7LOCK_Pos               (6U)
+#define RCC_LOCKCFGR2_IC7LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos)  /*!< 0x00000040 */
+#define RCC_LOCKCFGR2_IC7LOCK                   RCC_LOCKCFGR2_IC7LOCK_Msk            /*!< Locked protection of IC7 divider configuration bits */
+#define RCC_LOCKCFGR2_IC8LOCK_Pos               (7U)
+#define RCC_LOCKCFGR2_IC8LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos)  /*!< 0x00000080 */
+#define RCC_LOCKCFGR2_IC8LOCK                   RCC_LOCKCFGR2_IC8LOCK_Msk            /*!< Locked protection of IC8 divider configuration bits */
+#define RCC_LOCKCFGR2_IC9LOCK_Pos               (8U)
+#define RCC_LOCKCFGR2_IC9LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos)  /*!< 0x00000100 */
+#define RCC_LOCKCFGR2_IC9LOCK                   RCC_LOCKCFGR2_IC9LOCK_Msk            /*!< Locked protection of IC9 divider configuration bits */
+#define RCC_LOCKCFGR2_IC10LOCK_Pos              (9U)
+#define RCC_LOCKCFGR2_IC10LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR2_IC10LOCK                  RCC_LOCKCFGR2_IC10LOCK_Msk           /*!< Locked protection of IC10 divider configuration bits */
+#define RCC_LOCKCFGR2_IC11LOCK_Pos              (10U)
+#define RCC_LOCKCFGR2_IC11LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR2_IC11LOCK                  RCC_LOCKCFGR2_IC11LOCK_Msk           /*!< Locked protection of IC11 divider configuration bits */
+#define RCC_LOCKCFGR2_IC12LOCK_Pos              (11U)
+#define RCC_LOCKCFGR2_IC12LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR2_IC12LOCK                  RCC_LOCKCFGR2_IC12LOCK_Msk           /*!< Locked protection of IC12 divider configuration bits */
+#define RCC_LOCKCFGR2_IC13LOCK_Pos              (12U)
+#define RCC_LOCKCFGR2_IC13LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR2_IC13LOCK                  RCC_LOCKCFGR2_IC13LOCK_Msk           /*!< Locked protection of IC13 divider configuration bits */
+#define RCC_LOCKCFGR2_IC14LOCK_Pos              (13U)
+#define RCC_LOCKCFGR2_IC14LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */
+#define RCC_LOCKCFGR2_IC14LOCK                  RCC_LOCKCFGR2_IC14LOCK_Msk           /*!< Locked protection of IC14 divider configuration bits */
+#define RCC_LOCKCFGR2_IC15LOCK_Pos              (14U)
+#define RCC_LOCKCFGR2_IC15LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */
+#define RCC_LOCKCFGR2_IC15LOCK                  RCC_LOCKCFGR2_IC15LOCK_Msk           /*!< Locked protection of IC15 divider configuration bits */
+#define RCC_LOCKCFGR2_IC16LOCK_Pos              (15U)
+#define RCC_LOCKCFGR2_IC16LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */
+#define RCC_LOCKCFGR2_IC16LOCK                  RCC_LOCKCFGR2_IC16LOCK_Msk           /*!< Locked protection of IC16 divider configuration bits */
+#define RCC_LOCKCFGR2_IC17LOCK_Pos              (16U)
+#define RCC_LOCKCFGR2_IC17LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */
+#define RCC_LOCKCFGR2_IC17LOCK                  RCC_LOCKCFGR2_IC17LOCK_Msk           /*!< Locked protection of IC17 divider configuration bits */
+#define RCC_LOCKCFGR2_IC18LOCK_Pos              (17U)
+#define RCC_LOCKCFGR2_IC18LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */
+#define RCC_LOCKCFGR2_IC18LOCK                  RCC_LOCKCFGR2_IC18LOCK_Msk           /*!< Locked protection of IC18 divider configuration bits */
+#define RCC_LOCKCFGR2_IC19LOCK_Pos              (18U)
+#define RCC_LOCKCFGR2_IC19LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */
+#define RCC_LOCKCFGR2_IC19LOCK                  RCC_LOCKCFGR2_IC19LOCK_Msk           /*!< Locked protection of IC19 divider configuration bits */
+#define RCC_LOCKCFGR2_IC20LOCK_Pos              (19U)
+#define RCC_LOCKCFGR2_IC20LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */
+#define RCC_LOCKCFGR2_IC20LOCK                  RCC_LOCKCFGR2_IC20LOCK_Msk           /*!< Locked protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR2 register  *****************/
+#define RCC_PUBCFGR2_IC1PUB_Pos                 (0U)
+#define RCC_PUBCFGR2_IC1PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR2_IC1PUB                     RCC_PUBCFGR2_IC1PUB_Msk              /*!< Public protection of IC1 divider configuration bits */
+#define RCC_PUBCFGR2_IC2PUB_Pos                 (1U)
+#define RCC_PUBCFGR2_IC2PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR2_IC2PUB                     RCC_PUBCFGR2_IC2PUB_Msk              /*!< Public protection of IC2 divider configuration bits */
+#define RCC_PUBCFGR2_IC3PUB_Pos                 (2U)
+#define RCC_PUBCFGR2_IC3PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR2_IC3PUB                     RCC_PUBCFGR2_IC3PUB_Msk              /*!< Public protection of IC3 divider configuration bits */
+#define RCC_PUBCFGR2_IC4PUB_Pos                 (3U)
+#define RCC_PUBCFGR2_IC4PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR2_IC4PUB                     RCC_PUBCFGR2_IC4PUB_Msk              /*!< Public protection of IC4 divider configuration bits */
+#define RCC_PUBCFGR2_IC5PUB_Pos                 (4U)
+#define RCC_PUBCFGR2_IC5PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR2_IC5PUB                     RCC_PUBCFGR2_IC5PUB_Msk              /*!< Public protection of IC5 divider configuration bits */
+#define RCC_PUBCFGR2_IC6PUB_Pos                 (5U)
+#define RCC_PUBCFGR2_IC6PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR2_IC6PUB                     RCC_PUBCFGR2_IC6PUB_Msk              /*!< Public protection of IC6 divider configuration bits */
+#define RCC_PUBCFGR2_IC7PUB_Pos                 (6U)
+#define RCC_PUBCFGR2_IC7PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos)    /*!< 0x00000040 */
+#define RCC_PUBCFGR2_IC7PUB                     RCC_PUBCFGR2_IC7PUB_Msk              /*!< Public protection of IC7 divider configuration bits */
+#define RCC_PUBCFGR2_IC8PUB_Pos                 (7U)
+#define RCC_PUBCFGR2_IC8PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos)    /*!< 0x00000080 */
+#define RCC_PUBCFGR2_IC8PUB                     RCC_PUBCFGR2_IC8PUB_Msk              /*!< Public protection of IC8 divider configuration bits */
+#define RCC_PUBCFGR2_IC9PUB_Pos                 (8U)
+#define RCC_PUBCFGR2_IC9PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos)    /*!< 0x00000100 */
+#define RCC_PUBCFGR2_IC9PUB                     RCC_PUBCFGR2_IC9PUB_Msk              /*!< Public protection of IC9 divider configuration bits */
+#define RCC_PUBCFGR2_IC10PUB_Pos                (9U)
+#define RCC_PUBCFGR2_IC10PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR2_IC10PUB                    RCC_PUBCFGR2_IC10PUB_Msk             /*!< Public protection of IC10 divider configuration bits */
+#define RCC_PUBCFGR2_IC11PUB_Pos                (10U)
+#define RCC_PUBCFGR2_IC11PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR2_IC11PUB                    RCC_PUBCFGR2_IC11PUB_Msk             /*!< Public protection of IC11 divider configuration bits */
+#define RCC_PUBCFGR2_IC12PUB_Pos                (11U)
+#define RCC_PUBCFGR2_IC12PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR2_IC12PUB                    RCC_PUBCFGR2_IC12PUB_Msk             /*!< Public protection of IC12 divider configuration bits */
+#define RCC_PUBCFGR2_IC13PUB_Pos                (12U)
+#define RCC_PUBCFGR2_IC13PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR2_IC13PUB                    RCC_PUBCFGR2_IC13PUB_Msk             /*!< Public protection of IC13 divider configuration bits */
+#define RCC_PUBCFGR2_IC14PUB_Pos                (13U)
+#define RCC_PUBCFGR2_IC14PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos)   /*!< 0x00002000 */
+#define RCC_PUBCFGR2_IC14PUB                    RCC_PUBCFGR2_IC14PUB_Msk             /*!< Public protection of IC14 divider configuration bits */
+#define RCC_PUBCFGR2_IC15PUB_Pos                (14U)
+#define RCC_PUBCFGR2_IC15PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos)   /*!< 0x00004000 */
+#define RCC_PUBCFGR2_IC15PUB                    RCC_PUBCFGR2_IC15PUB_Msk             /*!< Public protection of IC15 divider configuration bits */
+#define RCC_PUBCFGR2_IC16PUB_Pos                (15U)
+#define RCC_PUBCFGR2_IC16PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos)   /*!< 0x00008000 */
+#define RCC_PUBCFGR2_IC16PUB                    RCC_PUBCFGR2_IC16PUB_Msk             /*!< Public protection of IC16 divider configuration bits */
+#define RCC_PUBCFGR2_IC17PUB_Pos                (16U)
+#define RCC_PUBCFGR2_IC17PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos)   /*!< 0x00010000 */
+#define RCC_PUBCFGR2_IC17PUB                    RCC_PUBCFGR2_IC17PUB_Msk             /*!< Public protection of IC17 divider configuration bits */
+#define RCC_PUBCFGR2_IC18PUB_Pos                (17U)
+#define RCC_PUBCFGR2_IC18PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos)   /*!< 0x00020000 */
+#define RCC_PUBCFGR2_IC18PUB                    RCC_PUBCFGR2_IC18PUB_Msk             /*!< Public protection of IC18 divider configuration bits */
+#define RCC_PUBCFGR2_IC19PUB_Pos                (18U)
+#define RCC_PUBCFGR2_IC19PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos)   /*!< 0x00040000 */
+#define RCC_PUBCFGR2_IC19PUB                    RCC_PUBCFGR2_IC19PUB_Msk             /*!< Public protection of IC19 divider configuration bits */
+#define RCC_PUBCFGR2_IC20PUB_Pos                (19U)
+#define RCC_PUBCFGR2_IC20PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos)   /*!< 0x00080000 */
+#define RCC_PUBCFGR2_IC20PUB                    RCC_PUBCFGR2_IC20PUB_Msk             /*!< Public protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR3 register  *****************/
+#define RCC_SECCFGR3_MODSEC_Pos                 (0U)
+#define RCC_SECCFGR3_MODSEC_Msk                 (0x1UL << RCC_SECCFGR3_MODSEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR3_MODSEC                     RCC_SECCFGR3_MODSEC_Msk              /*!< Secure protection of MOD system configuration bits */
+#define RCC_SECCFGR3_SYSSEC_Pos                 (1U)
+#define RCC_SECCFGR3_SYSSEC_Msk                 (0x1UL << RCC_SECCFGR3_SYSSEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR3_SYSSEC                     RCC_SECCFGR3_SYSSEC_Msk              /*!< Secure protection of SYS system configuration bit */
+#define RCC_SECCFGR3_BUSSEC_Pos                 (2U)
+#define RCC_SECCFGR3_BUSSEC_Msk                 (0x1UL << RCC_SECCFGR3_BUSSEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR3_BUSSEC                     RCC_SECCFGR3_BUSSEC_Msk              /*!< Secure protection of BUS system configuration bits */
+#define RCC_SECCFGR3_PERSEC_Pos                 (3U)
+#define RCC_SECCFGR3_PERSEC_Msk                 (0x1UL << RCC_SECCFGR3_PERSEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR3_PERSEC                     RCC_SECCFGR3_PERSEC_Msk              /*!< Secure protection of PER system configuration bits */
+#define RCC_SECCFGR3_INTSEC_Pos                 (4U)
+#define RCC_SECCFGR3_INTSEC_Msk                 (0x1UL << RCC_SECCFGR3_INTSEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR3_INTSEC                     RCC_SECCFGR3_INTSEC_Msk              /*!< Secure protection of INT system configuration bits */
+#define RCC_SECCFGR3_RSTSEC_Pos                 (5U)
+#define RCC_SECCFGR3_RSTSEC_Msk                 (0x1UL << RCC_SECCFGR3_RSTSEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR3_RSTSEC                     RCC_SECCFGR3_RSTSEC_Msk              /*!< Secure protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR3 register  *****************/
+#define RCC_PRIVCFGR3_MODPRIV_Pos               (0U)
+#define RCC_PRIVCFGR3_MODPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR3_MODPRIV                   RCC_PRIVCFGR3_MODPRIV_Msk            /*!< Privileged protection of MOD system configuration bits */
+#define RCC_PRIVCFGR3_SYSPRIV_Pos               (1U)
+#define RCC_PRIVCFGR3_SYSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR3_SYSPRIV                   RCC_PRIVCFGR3_SYSPRIV_Msk            /*!< Privileged protection of SYS system configuration bits */
+#define RCC_PRIVCFGR3_BUSPRIV_Pos               (2U)
+#define RCC_PRIVCFGR3_BUSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR3_BUSPRIV                   RCC_PRIVCFGR3_BUSPRIV_Msk            /*!< Privileged protection of BUS system configuration bits */
+#define RCC_PRIVCFGR3_PERPRIV_Pos               (3U)
+#define RCC_PRIVCFGR3_PERPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR3_PERPRIV                   RCC_PRIVCFGR3_PERPRIV_Msk            /*!< Privileged protection of PER system configuration bits */
+#define RCC_PRIVCFGR3_INTPRIV_Pos               (4U)
+#define RCC_PRIVCFGR3_INTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR3_INTPRIV                   RCC_PRIVCFGR3_INTPRIV_Msk            /*!< Privileged protection of INT system configuration bits */
+#define RCC_PRIVCFGR3_RSTPRIV_Pos               (5U)
+#define RCC_PRIVCFGR3_RSTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR3_RSTPRIV                   RCC_PRIVCFGR3_RSTPRIV_Msk            /*!< Privileged protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR3 register  *****************/
+#define RCC_LOCKCFGR3_MODLOCK_Pos               (0U)
+#define RCC_LOCKCFGR3_MODLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR3_MODLOCK                   RCC_LOCKCFGR3_MODLOCK_Msk            /*!< Locked protection of MOD system configuration bits */
+#define RCC_LOCKCFGR3_SYSLOCK_Pos               (1U)
+#define RCC_LOCKCFGR3_SYSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR3_SYSLOCK                   RCC_LOCKCFGR3_SYSLOCK_Msk            /*!< Locked protection of SYS system configuration bits */
+#define RCC_LOCKCFGR3_BUSLOCK_Pos               (2U)
+#define RCC_LOCKCFGR3_BUSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR3_BUSLOCK                   RCC_LOCKCFGR3_BUSLOCK_Msk            /*!< Locked protection of BUS system configuration bits */
+#define RCC_LOCKCFGR3_PERLOCK_Pos               (3U)
+#define RCC_LOCKCFGR3_PERLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR3_PERLOCK                   RCC_LOCKCFGR3_PERLOCK_Msk            /*!< Locked protection of PER system configuration bits */
+#define RCC_LOCKCFGR3_INTLOCK_Pos               (4U)
+#define RCC_LOCKCFGR3_INTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR3_INTLOCK                   RCC_LOCKCFGR3_INTLOCK_Msk            /*!< Locked protection of INT system configuration bits */
+#define RCC_LOCKCFGR3_RSTLOCK_Pos               (5U)
+#define RCC_LOCKCFGR3_RSTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR3_RSTLOCK                   RCC_LOCKCFGR3_RSTLOCK_Msk            /*!< Locked protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR3 register  *****************/
+#define RCC_PUBCFGR3_MODPUB_Pos                 (0U)
+#define RCC_PUBCFGR3_MODPUB_Msk                 (0x1UL << RCC_PUBCFGR3_MODPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR3_MODPUB                     RCC_PUBCFGR3_MODPUB_Msk              /*!< Public protection of MOD system configuration bits */
+#define RCC_PUBCFGR3_SYSPUB_Pos                 (1U)
+#define RCC_PUBCFGR3_SYSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR3_SYSPUB                     RCC_PUBCFGR3_SYSPUB_Msk              /*!< Public protection of SYS system configuration bits */
+#define RCC_PUBCFGR3_BUSPUB_Pos                 (2U)
+#define RCC_PUBCFGR3_BUSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR3_BUSPUB                     RCC_PUBCFGR3_BUSPUB_Msk              /*!< Public protection of BUS system configuration bits */
+#define RCC_PUBCFGR3_PERPUB_Pos                 (3U)
+#define RCC_PUBCFGR3_PERPUB_Msk                 (0x1UL << RCC_PUBCFGR3_PERPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR3_PERPUB                     RCC_PUBCFGR3_PERPUB_Msk              /*!< Public protection of PER system configuration bits */
+#define RCC_PUBCFGR3_INTPUB_Pos                 (4U)
+#define RCC_PUBCFGR3_INTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_INTPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR3_INTPUB                     RCC_PUBCFGR3_INTPUB_Msk              /*!< Public protection of INT system configuration bits */
+#define RCC_PUBCFGR3_RSTPUB_Pos                 (5U)
+#define RCC_PUBCFGR3_RSTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR3_RSTPUB                     RCC_PUBCFGR3_RSTPUB_Msk              /*!< Public protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR4 register  *****************/
+#define RCC_SECCFGR4_ACLKNSEC_Pos               (0U)
+#define RCC_SECCFGR4_ACLKNSEC_Msk               (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos)  /*!< 0x00000001 */
+#define RCC_SECCFGR4_ACLKNSEC                   RCC_SECCFGR4_ACLKNSEC_Msk            /*!< Secure protection of ACLKN bus configuration bits */
+#define RCC_SECCFGR4_ACLKNCSEC_Pos              (1U)
+#define RCC_SECCFGR4_ACLKNCSEC_Msk              (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */
+#define RCC_SECCFGR4_ACLKNCSEC                  RCC_SECCFGR4_ACLKNCSEC_Msk           /*!< Secure protection of ACLKNC bus configuration bits */
+#define RCC_SECCFGR4_AHBMSEC_Pos                (2U)
+#define RCC_SECCFGR4_AHBMSEC_Msk                (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR4_AHBMSEC                    RCC_SECCFGR4_AHBMSEC_Msk             /*!< Secure protection of AHBM bus configuration bits */
+#define RCC_SECCFGR4_AHB1SEC_Pos                (3U)
+#define RCC_SECCFGR4_AHB1SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR4_AHB1SEC                    RCC_SECCFGR4_AHB1SEC_Msk             /*!< Secure protection of AHB1 bus configuration bits */
+#define RCC_SECCFGR4_AHB2SEC_Pos                (4U)
+#define RCC_SECCFGR4_AHB2SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos)   /*!< 0x00000010 */
+#define RCC_SECCFGR4_AHB2SEC                    RCC_SECCFGR4_AHB2SEC_Msk             /*!< Secure protection of AHB2 bus configuration bits */
+#define RCC_SECCFGR4_AHB3SEC_Pos                (5U)
+#define RCC_SECCFGR4_AHB3SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos)   /*!< 0x00000020 */
+#define RCC_SECCFGR4_AHB3SEC                    RCC_SECCFGR4_AHB3SEC_Msk             /*!< Secure protection of AHB3 bus configuration bits */
+#define RCC_SECCFGR4_AHB4SEC_Pos                (6U)
+#define RCC_SECCFGR4_AHB4SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos)   /*!< 0x00000040 */
+#define RCC_SECCFGR4_AHB4SEC                    RCC_SECCFGR4_AHB4SEC_Msk             /*!< Secure protection of AHB4 bus configuration bits */
+#define RCC_SECCFGR4_AHB5SEC_Pos                (7U)
+#define RCC_SECCFGR4_AHB5SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos)   /*!< 0x00000080 */
+#define RCC_SECCFGR4_AHB5SEC                    RCC_SECCFGR4_AHB5SEC_Msk             /*!< Secure protection of AHB5 bus configuration bits */
+#define RCC_SECCFGR4_APB1SEC_Pos                (8U)
+#define RCC_SECCFGR4_APB1SEC_Msk                (0x1UL << RCC_SECCFGR4_APB1SEC_Pos)   /*!< 0x00000100 */
+#define RCC_SECCFGR4_APB1SEC                    RCC_SECCFGR4_APB1SEC_Msk             /*!< Secure protection of APB1 bus configuration bits */
+#define RCC_SECCFGR4_APB2SEC_Pos                (9U)
+#define RCC_SECCFGR4_APB2SEC_Msk                (0x1UL << RCC_SECCFGR4_APB2SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR4_APB2SEC                    RCC_SECCFGR4_APB2SEC_Msk             /*!< Secure protection of APB2 bus configuration bits */
+#define RCC_SECCFGR4_APB3SEC_Pos                (10U)
+#define RCC_SECCFGR4_APB3SEC_Msk                (0x1UL << RCC_SECCFGR4_APB3SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR4_APB3SEC                    RCC_SECCFGR4_APB3SEC_Msk             /*!< Secure protection of APB3 bus configuration bits */
+#define RCC_SECCFGR4_APB4SEC_Pos                (11U)
+#define RCC_SECCFGR4_APB4SEC_Msk                (0x1UL << RCC_SECCFGR4_APB4SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR4_APB4SEC                    RCC_SECCFGR4_APB4SEC_Msk             /*!< Secure protection of APB4 bus configuration bits */
+#define RCC_SECCFGR4_APB5SEC_Pos                (12U)
+#define RCC_SECCFGR4_APB5SEC_Msk                (0x1UL << RCC_SECCFGR4_APB5SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR4_APB5SEC                    RCC_SECCFGR4_APB5SEC_Msk             /*!< Secure protection of APB5 bus configuration bits */
+#define RCC_SECCFGR4_NOCSEC_Pos                 (13U)
+#define RCC_SECCFGR4_NOCSEC_Msk                 (0x1UL << RCC_SECCFGR4_NOCSEC_Pos)    /*!< 0x00002000 */
+#define RCC_SECCFGR4_NOCSEC                     RCC_SECCFGR4_NOCSEC_Msk              /*!< Secure protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR4 register  *****************/
+#define RCC_PRIVCFGR4_ACLKNPRIV_Pos             (0U)
+#define RCC_PRIVCFGR4_ACLKNPRIV_Msk             (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGR4_ACLKNPRIV                 RCC_PRIVCFGR4_ACLKNPRIV_Msk          /*!< Privileged protection of ACLKN bus configuration bits */
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos            (1U)
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk            (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR4_ACLKNCPRIV                RCC_PRIVCFGR4_ACLKNCPRIV_Msk         /*!< Privileged protection of ACLKNC bus configuration bits */
+#define RCC_PRIVCFGR4_AHBMPRIV_Pos              (2U)
+#define RCC_PRIVCFGR4_AHBMPRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR4_AHBMPRIV                  RCC_PRIVCFGR4_AHBMPRIV_Msk           /*!< Privileged protection of AHBM bus configuration bits */
+#define RCC_PRIVCFGR4_AHB1PRIV_Pos              (3U)
+#define RCC_PRIVCFGR4_AHB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR4_AHB1PRIV                  RCC_PRIVCFGR4_AHB1PRIV_Msk           /*!< Privileged protection of AHB1 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB2PRIV_Pos              (4U)
+#define RCC_PRIVCFGR4_AHB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGR4_AHB2PRIV                  RCC_PRIVCFGR4_AHB2PRIV_Msk           /*!< Privileged protection of AHB2 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB3PRIV_Pos              (5U)
+#define RCC_PRIVCFGR4_AHB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGR4_AHB3PRIV                  RCC_PRIVCFGR4_AHB3PRIV_Msk           /*!< Privileged protection of AHB3 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB4PRIV_Pos              (6U)
+#define RCC_PRIVCFGR4_AHB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGR4_AHB4PRIV                  RCC_PRIVCFGR4_AHB4PRIV_Msk           /*!< Privileged protection of AHB4 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB5PRIV_Pos              (7U)
+#define RCC_PRIVCFGR4_AHB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGR4_AHB5PRIV                  RCC_PRIVCFGR4_AHB5PRIV_Msk           /*!< Privileged protection of AHB5 bus configuration bits */
+#define RCC_PRIVCFGR4_APB1PRIV_Pos              (8U)
+#define RCC_PRIVCFGR4_APB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGR4_APB1PRIV                  RCC_PRIVCFGR4_APB1PRIV_Msk           /*!< Privileged protection of APB1 bus configuration bits */
+#define RCC_PRIVCFGR4_APB2PRIV_Pos              (9U)
+#define RCC_PRIVCFGR4_APB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR4_APB2PRIV                  RCC_PRIVCFGR4_APB2PRIV_Msk           /*!< Privileged protection of APB2 bus configuration bits */
+#define RCC_PRIVCFGR4_APB3PRIV_Pos              (10U)
+#define RCC_PRIVCFGR4_APB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR4_APB3PRIV                  RCC_PRIVCFGR4_APB3PRIV_Msk           /*!< Privileged protection of APB3 bus configuration bits */
+#define RCC_PRIVCFGR4_APB4PRIV_Pos              (11U)
+#define RCC_PRIVCFGR4_APB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR4_APB4PRIV                  RCC_PRIVCFGR4_APB4PRIV_Msk           /*!< Privileged protection of APB4 bus configuration bits */
+#define RCC_PRIVCFGR4_APB5PRIV_Pos              (12U)
+#define RCC_PRIVCFGR4_APB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR4_APB5PRIV                  RCC_PRIVCFGR4_APB5PRIV_Msk           /*!< Privileged protection of APB5 bus configuration bits */
+#define RCC_PRIVCFGR4_NOCPRIV_Pos               (13U)
+#define RCC_PRIVCFGR4_NOCPRIV_Msk               (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos)  /*!< 0x00002000 */
+#define RCC_PRIVCFGR4_NOCPRIV                   RCC_PRIVCFGR4_NOCPRIV_Msk            /*!< Privileged protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR4 register  *****************/
+#define RCC_LOCKCFGR4_ACLKNLOCK_Pos             (0U)
+#define RCC_LOCKCFGR4_ACLKNLOCK_Msk             (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */
+#define RCC_LOCKCFGR4_ACLKNLOCK                 RCC_LOCKCFGR4_ACLKNLOCK_Msk          /*!< Locked protection of ACLKN bus configuration bits */
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos            (1U)
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk            (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR4_ACLKNCLOCK                RCC_LOCKCFGR4_ACLKNCLOCK_Msk         /*!< Locked protection of ACLKNC bus configuration bits */
+#define RCC_LOCKCFGR4_AHBMLOCK_Pos              (2U)
+#define RCC_LOCKCFGR4_AHBMLOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR4_AHBMLOCK                  RCC_LOCKCFGR4_AHBMLOCK_Msk           /*!< Locked protection of AHBM bus configuration bits */
+#define RCC_LOCKCFGR4_AHB1LOCK_Pos              (3U)
+#define RCC_LOCKCFGR4_AHB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR4_AHB1LOCK                  RCC_LOCKCFGR4_AHB1LOCK_Msk           /*!< Locked protection of AHB1 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB2LOCK_Pos              (4U)
+#define RCC_LOCKCFGR4_AHB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */
+#define RCC_LOCKCFGR4_AHB2LOCK                  RCC_LOCKCFGR4_AHB2LOCK_Msk           /*!< Locked protection of AHB2 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB3LOCK_Pos              (5U)
+#define RCC_LOCKCFGR4_AHB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */
+#define RCC_LOCKCFGR4_AHB3LOCK                  RCC_LOCKCFGR4_AHB3LOCK_Msk           /*!< Locked protection of AHB3 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB4LOCK_Pos              (6U)
+#define RCC_LOCKCFGR4_AHB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */
+#define RCC_LOCKCFGR4_AHB4LOCK                  RCC_LOCKCFGR4_AHB4LOCK_Msk           /*!< Locked protection of AHB4 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB5LOCK_Pos              (7U)
+#define RCC_LOCKCFGR4_AHB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */
+#define RCC_LOCKCFGR4_AHB5LOCK                  RCC_LOCKCFGR4_AHB5LOCK_Msk           /*!< Locked protection of AHB5 bus configuration bits */
+#define RCC_LOCKCFGR4_APB1LOCK_Pos              (8U)
+#define RCC_LOCKCFGR4_APB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */
+#define RCC_LOCKCFGR4_APB1LOCK                  RCC_LOCKCFGR4_APB1LOCK_Msk           /*!< Locked protection of APB1 bus configuration bits */
+#define RCC_LOCKCFGR4_APB2LOCK_Pos              (9U)
+#define RCC_LOCKCFGR4_APB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR4_APB2LOCK                  RCC_LOCKCFGR4_APB2LOCK_Msk           /*!< Locked protection of APB2 bus configuration bits */
+#define RCC_LOCKCFGR4_APB3LOCK_Pos              (10U)
+#define RCC_LOCKCFGR4_APB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR4_APB3LOCK                  RCC_LOCKCFGR4_APB3LOCK_Msk           /*!< Locked protection of APB3 bus configuration bits */
+#define RCC_LOCKCFGR4_APB4LOCK_Pos              (11U)
+#define RCC_LOCKCFGR4_APB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR4_APB4LOCK                  RCC_LOCKCFGR4_APB4LOCK_Msk           /*!< Locked protection of APB4 bus configuration bits */
+#define RCC_LOCKCFGR4_APB5LOCK_Pos              (12U)
+#define RCC_LOCKCFGR4_APB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR4_APB5LOCK                  RCC_LOCKCFGR4_APB5LOCK_Msk           /*!< Locked protection of APB5 bus configuration bits */
+#define RCC_LOCKCFGR4_NOCLOCK_Pos               (13U)
+#define RCC_LOCKCFGR4_NOCLOCK_Msk               (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos)  /*!< 0x00002000 */
+#define RCC_LOCKCFGR4_NOCLOCK                   RCC_LOCKCFGR4_NOCLOCK_Msk            /*!< Locked protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR4 register  *****************/
+#define RCC_PUBCFGR4_ACLKNPUB_Pos               (0U)
+#define RCC_PUBCFGR4_ACLKNPUB_Msk               (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGR4_ACLKNPUB                   RCC_PUBCFGR4_ACLKNPUB_Msk            /*!< Public protection of the ACLKN bus configuration bits */
+#define RCC_PUBCFGR4_ACLKNCPUB_Pos              (1U)
+#define RCC_PUBCFGR4_ACLKNCPUB_Msk              (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR4_ACLKNCPUB                  RCC_PUBCFGR4_ACLKNCPUB_Msk           /*!< Public protection of ACLKNC bus configuration bits */
+#define RCC_PUBCFGR4_AHBMPUB_Pos                (2U)
+#define RCC_PUBCFGR4_AHBMPUB_Msk                (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR4_AHBMPUB                    RCC_PUBCFGR4_AHBMPUB_Msk             /*!< Public protection of AHBM bus configuration bits */
+#define RCC_PUBCFGR4_AHB1PUB_Pos                (3U)
+#define RCC_PUBCFGR4_AHB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR4_AHB1PUB                    RCC_PUBCFGR4_AHB1PUB_Msk             /*!< Public protection of AHB1 bus configuration bits */
+#define RCC_PUBCFGR4_AHB2PUB_Pos                (4U)
+#define RCC_PUBCFGR4_AHB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGR4_AHB2PUB                    RCC_PUBCFGR4_AHB2PUB_Msk             /*!< Public protection of AHB2 bus configuration bits */
+#define RCC_PUBCFGR4_AHB3PUB_Pos                (5U)
+#define RCC_PUBCFGR4_AHB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGR4_AHB3PUB                    RCC_PUBCFGR4_AHB3PUB_Msk             /*!< Public protection of AHB3 bus configuration bits */
+#define RCC_PUBCFGR4_AHB4PUB_Pos                (6U)
+#define RCC_PUBCFGR4_AHB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos)   /*!< 0x00000040 */
+#define RCC_PUBCFGR4_AHB4PUB                    RCC_PUBCFGR4_AHB4PUB_Msk             /*!< Public protection of AHB4 bus configuration bits */
+#define RCC_PUBCFGR4_AHB5PUB_Pos                (7U)
+#define RCC_PUBCFGR4_AHB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGR4_AHB5PUB                    RCC_PUBCFGR4_AHB5PUB_Msk             /*!< Public protection of AHB5 bus configuration bits */
+#define RCC_PUBCFGR4_APB1PUB_Pos                (8U)
+#define RCC_PUBCFGR4_APB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGR4_APB1PUB                    RCC_PUBCFGR4_APB1PUB_Msk             /*!< Public protection of APB1 bus configuration bits */
+#define RCC_PUBCFGR4_APB2PUB_Pos                (9U)
+#define RCC_PUBCFGR4_APB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR4_APB2PUB                    RCC_PUBCFGR4_APB2PUB_Msk             /*!< Public protection of APB2 bus configuration bits */
+#define RCC_PUBCFGR4_APB3PUB_Pos                (10U)
+#define RCC_PUBCFGR4_APB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR4_APB3PUB                    RCC_PUBCFGR4_APB3PUB_Msk             /*!< Public protection of APB3 bus configuration bits */
+#define RCC_PUBCFGR4_APB4PUB_Pos                (11U)
+#define RCC_PUBCFGR4_APB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR4_APB4PUB                    RCC_PUBCFGR4_APB4PUB_Msk             /*!< Public protection of APB4 bus configuration bits */
+#define RCC_PUBCFGR4_APB5PUB_Pos                (12U)
+#define RCC_PUBCFGR4_APB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR4_APB5PUB                    RCC_PUBCFGR4_APB5PUB_Msk             /*!< Public protection of APB5 bus configuration bits */
+#define RCC_PUBCFGR4_NOCPUB_Pos                 (13U)
+#define RCC_PUBCFGR4_NOCPUB_Msk                 (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos)    /*!< 0x00002000 */
+#define RCC_PUBCFGR4_NOCPUB                     RCC_PUBCFGR4_NOCPUB_Msk              /*!< Public protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR5 register  *****************/
+#define RCC_PUBCFGR5_AXISRAM3PUB_Pos            (0U)
+#define RCC_PUBCFGR5_AXISRAM3PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGR5_AXISRAM3PUB                RCC_PUBCFGR5_AXISRAM3PUB_Msk         /*!< Public protection of AXISRAM3 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM4PUB_Pos            (1U)
+#define RCC_PUBCFGR5_AXISRAM4PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR5_AXISRAM4PUB                RCC_PUBCFGR5_AXISRAM4PUB_Msk         /*!< Public protection of AXISRAM4 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM5PUB_Pos            (2U)
+#define RCC_PUBCFGR5_AXISRAM5PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGR5_AXISRAM5PUB                RCC_PUBCFGR5_AXISRAM5PUB_Msk         /*!< Public protection of AXISRAM5 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM6PUB_Pos            (3U)
+#define RCC_PUBCFGR5_AXISRAM6PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGR5_AXISRAM6PUB                RCC_PUBCFGR5_AXISRAM6PUB_Msk         /*!< Public protection of AXISRAM6 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos            (4U)
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGR5_AHBSRAM1PUB                RCC_PUBCFGR5_AHBSRAM1PUB_Msk         /*!< Public protection of AHBSRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos            (5U)
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGR5_AHBSRAM2PUB                RCC_PUBCFGR5_AHBSRAM2PUB_Msk         /*!< Public protection of AHBSRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_BKPSRAMPUB_Pos             (6U)
+#define RCC_PUBCFGR5_BKPSRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */
+#define RCC_PUBCFGR5_BKPSRAMPUB                 RCC_PUBCFGR5_BKPSRAMPUB_Msk          /*!< Public protection of BKPSRAM bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM1PUB_Pos            (7U)
+#define RCC_PUBCFGR5_AXISRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGR5_AXISRAM1PUB                RCC_PUBCFGR5_AXISRAM1PUB_Msk         /*!< Public protection of AXISRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM2PUB_Pos            (8U)
+#define RCC_PUBCFGR5_AXISRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGR5_AXISRAM2PUB                RCC_PUBCFGR5_AXISRAM2PUB_Msk         /*!< Public protection of AXISRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_FLEXRAMPUB_Pos             (9U)
+#define RCC_PUBCFGR5_FLEXRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */
+#define RCC_PUBCFGR5_FLEXRAMPUB                 RCC_PUBCFGR5_FLEXRAMPUB_Msk          /*!< Public protection of FLEXRAM bus configuration bits */
+#define RCC_PUBCFGR5_VENCRAMPUB_Pos             (11U)
+#define RCC_PUBCFGR5_VENCRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */
+#define RCC_PUBCFGR5_VENCRAMPUB                 RCC_PUBCFGR5_VENCRAMPUB_Msk          /*!< Public protection of VENCRAM bus configuration bits */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define RCC_CSR_LSIONS_Pos                      (0U)
+#define RCC_CSR_LSIONS_Msk                      (0x1UL << RCC_CSR_LSIONS_Pos)         /*!< 0x00000001 */
+#define RCC_CSR_LSIONS                          RCC_CSR_LSIONS_Msk                   /*!< LSI oscillator enable */
+#define RCC_CSR_LSEONS_Pos                      (1U)
+#define RCC_CSR_LSEONS_Msk                      (0x1UL << RCC_CSR_LSEONS_Pos)         /*!< 0x00000002 */
+#define RCC_CSR_LSEONS                          RCC_CSR_LSEONS_Msk                   /*!< LSE oscillator enable */
+#define RCC_CSR_MSIONS_Pos                      (2U)
+#define RCC_CSR_MSIONS_Msk                      (0x1UL << RCC_CSR_MSIONS_Pos)         /*!< 0x00000004 */
+#define RCC_CSR_MSIONS                          RCC_CSR_MSIONS_Msk                   /*!< MSI oscillator enable */
+#define RCC_CSR_HSIONS_Pos                      (3U)
+#define RCC_CSR_HSIONS_Msk                      (0x1UL << RCC_CSR_HSIONS_Pos)         /*!< 0x00000008 */
+#define RCC_CSR_HSIONS                          RCC_CSR_HSIONS_Msk                   /*!< HSI oscillator enable */
+#define RCC_CSR_HSEONS_Pos                      (4U)
+#define RCC_CSR_HSEONS_Msk                      (0x1UL << RCC_CSR_HSEONS_Pos)         /*!< 0x00000010 */
+#define RCC_CSR_HSEONS                          RCC_CSR_HSEONS_Msk                   /*!< HSE oscillator enable */
+#define RCC_CSR_PLL1ONS_Pos                     (8U)
+#define RCC_CSR_PLL1ONS_Msk                     (0x1UL << RCC_CSR_PLL1ONS_Pos)        /*!< 0x00000100 */
+#define RCC_CSR_PLL1ONS                         RCC_CSR_PLL1ONS_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CSR_PLL2ONS_Pos                     (9U)
+#define RCC_CSR_PLL2ONS_Msk                     (0x1UL << RCC_CSR_PLL2ONS_Pos)        /*!< 0x00000200 */
+#define RCC_CSR_PLL2ONS                         RCC_CSR_PLL2ONS_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CSR_PLL3ONS_Pos                     (10U)
+#define RCC_CSR_PLL3ONS_Msk                     (0x1UL << RCC_CSR_PLL3ONS_Pos)        /*!< 0x00000400 */
+#define RCC_CSR_PLL3ONS                         RCC_CSR_PLL3ONS_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CSR_PLL4ONS_Pos                     (11U)
+#define RCC_CSR_PLL4ONS_Msk                     (0x1UL << RCC_CSR_PLL4ONS_Pos)        /*!< 0x00000800 */
+#define RCC_CSR_PLL4ONS                         RCC_CSR_PLL4ONS_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCSR register  ******************/
+#define RCC_STOPCSR_MSISTOPENS_Pos              (0U)
+#define RCC_STOPCSR_MSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */
+#define RCC_STOPCSR_MSISTOPENS                  RCC_STOPCSR_MSISTOPENS_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCSR_HSISTOPENS_Pos              (1U)
+#define RCC_STOPCSR_HSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */
+#define RCC_STOPCSR_HSISTOPENS                  RCC_STOPCSR_HSISTOPENS_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTSR register  *****************/
+#define RCC_MISCRSTSR_DBGRSTS_Pos               (0U)
+#define RCC_MISCRSTSR_DBGRSTS_Msk               (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTSR_DBGRSTS                   RCC_MISCRSTSR_DBGRSTS_Msk            /*!< DBG reset */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos          (4U)
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS              RCC_MISCRSTSR_XSPIPHY1RSTS_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos          (5U)
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS              RCC_MISCRSTSR_XSPIPHY2RSTS_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos         (7U)
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS             RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos         (8U)
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS             RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTSR register  *****************/
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos           (0U)
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTSR_AXISRAM3RSTS               RCC_MEMRSTSR_AXISRAM3RSTS_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos           (1U)
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTSR_AXISRAM4RSTS               RCC_MEMRSTSR_AXISRAM4RSTS_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos           (2U)
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTSR_AXISRAM5RSTS               RCC_MEMRSTSR_AXISRAM5RSTS_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos           (3U)
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTSR_AXISRAM6RSTS               RCC_MEMRSTSR_AXISRAM6RSTS_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos           (4U)
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS               RCC_MEMRSTSR_AHBSRAM1RSTS_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos           (5U)
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS               RCC_MEMRSTSR_AHBSRAM2RSTS_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos           (7U)
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTSR_AXISRAM1RSTS               RCC_MEMRSTSR_AXISRAM1RSTS_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos           (8U)
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTSR_AXISRAM2RSTS               RCC_MEMRSTSR_AXISRAM2RSTS_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos            (9U)
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTSR_FLEXRAMRSTS                RCC_MEMRSTSR_FLEXRAMRSTS_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTSR_VENCRAMRSTS_Pos            (11U)
+#define RCC_MEMRSTSR_VENCRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTSR_VENCRAMRSTS                RCC_MEMRSTSR_VENCRAMRSTS_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTSR_BOOTROMRSTS_Pos            (12U)
+#define RCC_MEMRSTSR_BOOTROMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTSR_BOOTROMRSTS                RCC_MEMRSTSR_BOOTROMRSTS_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTSR register  *****************/
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos            (4U)
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk            (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTSR_GPDMA1RSTS                RCC_AHB1RSTSR_GPDMA1RSTS_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTSR_ADC12RSTS_Pos             (5U)
+#define RCC_AHB1RSTSR_ADC12RSTS_Msk             (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTSR_ADC12RSTS                 RCC_AHB1RSTSR_ADC12RSTS_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTSR register  *****************/
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos            (12U)
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk            (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTSR_RAMCFGRSTS                RCC_AHB2RSTSR_RAMCFGRSTS_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTSR_MDF1RSTS_Pos              (16U)
+#define RCC_AHB2RSTSR_MDF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTSR_MDF1RSTS                  RCC_AHB2RSTSR_MDF1RSTS_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTSR_ADF1RSTS_Pos              (17U)
+#define RCC_AHB2RSTSR_ADF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTSR_ADF1RSTS                  RCC_AHB2RSTSR_ADF1RSTS_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTSR register  *****************/
+#define RCC_AHB3RSTSR_RNGRSTS_Pos               (0U)
+#define RCC_AHB3RSTSR_RNGRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTSR_RNGRSTS                   RCC_AHB3RSTSR_RNGRSTS_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTSR_HASHRSTS_Pos              (1U)
+#define RCC_AHB3RSTSR_HASHRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTSR_HASHRSTS                  RCC_AHB3RSTSR_HASHRSTS_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTSR_PKARSTS_Pos               (8U)
+#define RCC_AHB3RSTSR_PKARSTS_Msk               (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTSR_PKARSTS                   RCC_AHB3RSTSR_PKARSTS_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTSR_IACRSTS_Pos               (10U)
+#define RCC_AHB3RSTSR_IACRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTSR_IACRSTS                   RCC_AHB3RSTSR_IACRSTS_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTSR register  *****************/
+#define RCC_AHB4RSTSR_GPIOARSTS_Pos             (0U)
+#define RCC_AHB4RSTSR_GPIOARSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTSR_GPIOARSTS                 RCC_AHB4RSTSR_GPIOARSTS_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTSR_GPIOBRSTS_Pos             (1U)
+#define RCC_AHB4RSTSR_GPIOBRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTSR_GPIOBRSTS                 RCC_AHB4RSTSR_GPIOBRSTS_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTSR_GPIOCRSTS_Pos             (2U)
+#define RCC_AHB4RSTSR_GPIOCRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTSR_GPIOCRSTS                 RCC_AHB4RSTSR_GPIOCRSTS_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTSR_GPIODRSTS_Pos             (3U)
+#define RCC_AHB4RSTSR_GPIODRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTSR_GPIODRSTS                 RCC_AHB4RSTSR_GPIODRSTS_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTSR_GPIOERSTS_Pos             (4U)
+#define RCC_AHB4RSTSR_GPIOERSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTSR_GPIOERSTS                 RCC_AHB4RSTSR_GPIOERSTS_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTSR_GPIOFRSTS_Pos             (5U)
+#define RCC_AHB4RSTSR_GPIOFRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTSR_GPIOFRSTS                 RCC_AHB4RSTSR_GPIOFRSTS_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTSR_GPIOGRSTS_Pos             (6U)
+#define RCC_AHB4RSTSR_GPIOGRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTSR_GPIOGRSTS                 RCC_AHB4RSTSR_GPIOGRSTS_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTSR_GPIOHRSTS_Pos             (7U)
+#define RCC_AHB4RSTSR_GPIOHRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTSR_GPIOHRSTS                 RCC_AHB4RSTSR_GPIOHRSTS_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTSR_GPIONRSTS_Pos             (13U)
+#define RCC_AHB4RSTSR_GPIONRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTSR_GPIONRSTS                 RCC_AHB4RSTSR_GPIONRSTS_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTSR_GPIOORSTS_Pos             (14U)
+#define RCC_AHB4RSTSR_GPIOORSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTSR_GPIOORSTS                 RCC_AHB4RSTSR_GPIOORSTS_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTSR_GPIOPRSTS_Pos             (15U)
+#define RCC_AHB4RSTSR_GPIOPRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTSR_GPIOPRSTS                 RCC_AHB4RSTSR_GPIOPRSTS_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTSR_GPIOQRSTS_Pos             (16U)
+#define RCC_AHB4RSTSR_GPIOQRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTSR_GPIOQRSTS                 RCC_AHB4RSTSR_GPIOQRSTS_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTSR_PWRRSTS_Pos               (18U)
+#define RCC_AHB4RSTSR_PWRRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTSR_PWRRSTS                   RCC_AHB4RSTSR_PWRRSTS_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTSR_CRCRSTS_Pos               (19U)
+#define RCC_AHB4RSTSR_CRCRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTSR_CRCRSTS                   RCC_AHB4RSTSR_CRCRSTS_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTSR register  *****************/
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos            (0U)
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTSR_HPDMA1RSTS                RCC_AHB5RSTSR_HPDMA1RSTS_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTSR_DMA2DRSTS_Pos             (1U)
+#define RCC_AHB5RSTSR_DMA2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTSR_DMA2DRSTS                 RCC_AHB5RSTSR_DMA2DRSTS_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTSR_JPEGRSTS_Pos              (3U)
+#define RCC_AHB5RSTSR_JPEGRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTSR_JPEGRSTS                  RCC_AHB5RSTSR_JPEGRSTS_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTSR_FMCRSTS_Pos               (4U)
+#define RCC_AHB5RSTSR_FMCRSTS_Msk               (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTSR_FMCRSTS                   RCC_AHB5RSTSR_FMCRSTS_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTSR_XSPI1RSTS_Pos             (5U)
+#define RCC_AHB5RSTSR_XSPI1RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTSR_XSPI1RSTS                 RCC_AHB5RSTSR_XSPI1RSTS_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTSR_PSSIRSTS_Pos              (6U)
+#define RCC_AHB5RSTSR_PSSIRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTSR_PSSIRSTS                  RCC_AHB5RSTSR_PSSIRSTS_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos            (7U)
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTSR_SDMMC2RSTS                RCC_AHB5RSTSR_SDMMC2RSTS_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos            (8U)
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTSR_SDMMC1RSTS                RCC_AHB5RSTSR_SDMMC1RSTS_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTSR_XSPI2RSTS_Pos             (12U)
+#define RCC_AHB5RSTSR_XSPI2RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTSR_XSPI2RSTS                 RCC_AHB5RSTSR_XSPI2RSTS_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTSR_XSPIMRSTS_Pos             (13U)
+#define RCC_AHB5RSTSR_XSPIMRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTSR_XSPIMRSTS                 RCC_AHB5RSTSR_XSPIMRSTS_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTSR_XSPI3RSTS_Pos             (17U)
+#define RCC_AHB5RSTSR_XSPI3RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTSR_XSPI3RSTS                 RCC_AHB5RSTSR_XSPI3RSTS_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTSR_GFXMMURSTS_Pos            (19U)
+#define RCC_AHB5RSTSR_GFXMMURSTS_Msk            (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTSR_GFXMMURSTS                RCC_AHB5RSTSR_GFXMMURSTS_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTSR_GPU2DRSTS_Pos             (20U)
+#define RCC_AHB5RSTSR_GPU2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTSR_GPU2DRSTS                 RCC_AHB5RSTSR_GPU2DRSTS_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos        (23U)
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS            RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos        (24U)
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS            RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTSR_ETH1RSTS_Pos              (25U)
+#define RCC_AHB5RSTSR_ETH1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTSR_ETH1RSTS                  RCC_AHB5RSTSR_ETH1RSTS_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTSR_OTG1RSTS_Pos              (26U)
+#define RCC_AHB5RSTSR_OTG1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTSR_OTG1RSTS                  RCC_AHB5RSTSR_OTG1RSTS_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos           (27U)
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS               RCC_AHB5RSTSR_OTGPHY1RSTS_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos           (28U)
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS               RCC_AHB5RSTSR_OTGPHY2RSTS_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTSR_OTG2RSTS_Pos              (29U)
+#define RCC_AHB5RSTSR_OTG2RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTSR_OTG2RSTS                  RCC_AHB5RSTSR_OTG2RSTS_Msk           /*!< OTG2 reset */
+
+/****************  Bit definition for RCC_APB1RSTSR1 register  ****************/
+#define RCC_APB1RSTSR1_TIM2RSTS_Pos             (0U)
+#define RCC_APB1RSTSR1_TIM2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTSR1_TIM2RSTS                 RCC_APB1RSTSR1_TIM2RSTS_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTSR1_TIM3RSTS_Pos             (1U)
+#define RCC_APB1RSTSR1_TIM3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTSR1_TIM3RSTS                 RCC_APB1RSTSR1_TIM3RSTS_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTSR1_TIM4RSTS_Pos             (2U)
+#define RCC_APB1RSTSR1_TIM4RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTSR1_TIM4RSTS                 RCC_APB1RSTSR1_TIM4RSTS_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTSR1_TIM5RSTS_Pos             (3U)
+#define RCC_APB1RSTSR1_TIM5RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTSR1_TIM5RSTS                 RCC_APB1RSTSR1_TIM5RSTS_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTSR1_TIM6RSTS_Pos             (4U)
+#define RCC_APB1RSTSR1_TIM6RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTSR1_TIM6RSTS                 RCC_APB1RSTSR1_TIM6RSTS_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTSR1_TIM7RSTS_Pos             (5U)
+#define RCC_APB1RSTSR1_TIM7RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTSR1_TIM7RSTS                 RCC_APB1RSTSR1_TIM7RSTS_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTSR1_TIM12RSTS_Pos            (6U)
+#define RCC_APB1RSTSR1_TIM12RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTSR1_TIM12RSTS                RCC_APB1RSTSR1_TIM12RSTS_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTSR1_TIM13RSTS_Pos            (7U)
+#define RCC_APB1RSTSR1_TIM13RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTSR1_TIM13RSTS                RCC_APB1RSTSR1_TIM13RSTS_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTSR1_TIM14RSTS_Pos            (8U)
+#define RCC_APB1RSTSR1_TIM14RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR1_TIM14RSTS                RCC_APB1RSTSR1_TIM14RSTS_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos           (9U)
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTSR1_LPTIM1RSTS               RCC_APB1RSTSR1_LPTIM1RSTS_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTSR1_WWDGRSTS_Pos             (11U)
+#define RCC_APB1RSTSR1_WWDGRSTS_Msk             (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTSR1_WWDGRSTS                 RCC_APB1RSTSR1_WWDGRSTS_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTSR1_TIM10RSTS_Pos            (12U)
+#define RCC_APB1RSTSR1_TIM10RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTSR1_TIM10RSTS                RCC_APB1RSTSR1_TIM10RSTS_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTSR1_TIM11RSTS_Pos            (13U)
+#define RCC_APB1RSTSR1_TIM11RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTSR1_TIM11RSTS                RCC_APB1RSTSR1_TIM11RSTS_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTSR1_SPI2RSTS_Pos             (14U)
+#define RCC_APB1RSTSR1_SPI2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTSR1_SPI2RSTS                 RCC_APB1RSTSR1_SPI2RSTS_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTSR1_SPI3RSTS_Pos             (15U)
+#define RCC_APB1RSTSR1_SPI3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTSR1_SPI3RSTS                 RCC_APB1RSTSR1_SPI3RSTS_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos         (16U)
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk         (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS             RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTSR1_USART2RSTS_Pos           (17U)
+#define RCC_APB1RSTSR1_USART2RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTSR1_USART2RSTS               RCC_APB1RSTSR1_USART2RSTS_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTSR1_USART3RSTS_Pos           (18U)
+#define RCC_APB1RSTSR1_USART3RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTSR1_USART3RSTS               RCC_APB1RSTSR1_USART3RSTS_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTSR1_UART4RSTS_Pos            (19U)
+#define RCC_APB1RSTSR1_UART4RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTSR1_UART4RSTS                RCC_APB1RSTSR1_UART4RSTS_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTSR1_UART5RSTS_Pos            (20U)
+#define RCC_APB1RSTSR1_UART5RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTSR1_UART5RSTS                RCC_APB1RSTSR1_UART5RSTS_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTSR1_I2C1RSTS_Pos             (21U)
+#define RCC_APB1RSTSR1_I2C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTSR1_I2C1RSTS                 RCC_APB1RSTSR1_I2C1RSTS_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTSR1_I2C2RSTS_Pos             (22U)
+#define RCC_APB1RSTSR1_I2C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTSR1_I2C2RSTS                 RCC_APB1RSTSR1_I2C2RSTS_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTSR1_I2C3RSTS_Pos             (23U)
+#define RCC_APB1RSTSR1_I2C3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTSR1_I2C3RSTS                 RCC_APB1RSTSR1_I2C3RSTS_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTSR1_I3C1RSTS_Pos             (24U)
+#define RCC_APB1RSTSR1_I3C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTSR1_I3C1RSTS                 RCC_APB1RSTSR1_I3C1RSTS_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTSR1_I3C2RSTS_Pos             (25U)
+#define RCC_APB1RSTSR1_I3C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTSR1_I3C2RSTS                 RCC_APB1RSTSR1_I3C2RSTS_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTSR1_UART7RSTS_Pos            (30U)
+#define RCC_APB1RSTSR1_UART7RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTSR1_UART7RSTS                RCC_APB1RSTSR1_UART7RSTS_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTSR1_UART8RSTS_Pos            (31U)
+#define RCC_APB1RSTSR1_UART8RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTSR1_UART8RSTS                RCC_APB1RSTSR1_UART8RSTS_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTSR2 register  ****************/
+#define RCC_APB1RSTSR2_MDIOSRSTS_Pos            (5U)
+#define RCC_APB1RSTSR2_MDIOSRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTSR2_MDIOSRSTS                RCC_APB1RSTSR2_MDIOSRSTS_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTSR2_FDCANRSTS_Pos            (8U)
+#define RCC_APB1RSTSR2_FDCANRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR2_FDCANRSTS                RCC_APB1RSTSR2_FDCANRSTS_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTSR2_UCPD1RSTS_Pos            (18U)
+#define RCC_APB1RSTSR2_UCPD1RSTS_Msk            (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTSR2_UCPD1RSTS                RCC_APB1RSTSR2_UCPD1RSTS_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTSR register  *****************/
+#define RCC_APB2RSTSR_TIM1RSTS_Pos              (0U)
+#define RCC_APB2RSTSR_TIM1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTSR_TIM1RSTS                  RCC_APB2RSTSR_TIM1RSTS_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTSR_TIM8RSTS_Pos              (1U)
+#define RCC_APB2RSTSR_TIM8RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTSR_TIM8RSTS                  RCC_APB2RSTSR_TIM8RSTS_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTSR_USART1RSTS_Pos            (4U)
+#define RCC_APB2RSTSR_USART1RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTSR_USART1RSTS                RCC_APB2RSTSR_USART1RSTS_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTSR_USART6RSTS_Pos            (5U)
+#define RCC_APB2RSTSR_USART6RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTSR_USART6RSTS                RCC_APB2RSTSR_USART6RSTS_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTSR_UART9RSTS_Pos             (6U)
+#define RCC_APB2RSTSR_UART9RSTS_Msk             (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTSR_UART9RSTS                 RCC_APB2RSTSR_UART9RSTS_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTSR_USART10RSTS_Pos           (7U)
+#define RCC_APB2RSTSR_USART10RSTS_Msk           (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTSR_USART10RSTS               RCC_APB2RSTSR_USART10RSTS_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTSR_SPI1RSTS_Pos              (12U)
+#define RCC_APB2RSTSR_SPI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTSR_SPI1RSTS                  RCC_APB2RSTSR_SPI1RSTS_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTSR_SPI4RSTS_Pos              (13U)
+#define RCC_APB2RSTSR_SPI4RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTSR_SPI4RSTS                  RCC_APB2RSTSR_SPI4RSTS_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTSR_TIM18RSTS_Pos             (15U)
+#define RCC_APB2RSTSR_TIM18RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTSR_TIM18RSTS                 RCC_APB2RSTSR_TIM18RSTS_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTSR_TIM15RSTS_Pos             (16U)
+#define RCC_APB2RSTSR_TIM15RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTSR_TIM15RSTS                 RCC_APB2RSTSR_TIM15RSTS_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTSR_TIM16RSTS_Pos             (17U)
+#define RCC_APB2RSTSR_TIM16RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTSR_TIM16RSTS                 RCC_APB2RSTSR_TIM16RSTS_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTSR_TIM17RSTS_Pos             (18U)
+#define RCC_APB2RSTSR_TIM17RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTSR_TIM17RSTS                 RCC_APB2RSTSR_TIM17RSTS_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTSR_TIM9RSTS_Pos              (19U)
+#define RCC_APB2RSTSR_TIM9RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTSR_TIM9RSTS                  RCC_APB2RSTSR_TIM9RSTS_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTSR_SPI5RSTS_Pos              (20U)
+#define RCC_APB2RSTSR_SPI5RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTSR_SPI5RSTS                  RCC_APB2RSTSR_SPI5RSTS_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTSR_SAI1RSTS_Pos              (21U)
+#define RCC_APB2RSTSR_SAI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTSR_SAI1RSTS                  RCC_APB2RSTSR_SAI1RSTS_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTSR_SAI2RSTS_Pos              (22U)
+#define RCC_APB2RSTSR_SAI2RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTSR_SAI2RSTS                  RCC_APB2RSTSR_SAI2RSTS_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTSR1 register  ****************/
+#define RCC_APB4RSTSR1_HDPRSTS_Pos              (2U)
+#define RCC_APB4RSTSR1_HDPRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR1_HDPRSTS                  RCC_APB4RSTSR1_HDPRSTS_Msk           /*!< HDP reset */
+#define RCC_APB4RSTSR1_LPUART1RSTS_Pos          (3U)
+#define RCC_APB4RSTSR1_LPUART1RSTS_Msk          (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTSR1_LPUART1RSTS              RCC_APB4RSTSR1_LPUART1RSTS_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTSR1_SPI6RSTS_Pos             (5U)
+#define RCC_APB4RSTSR1_SPI6RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTSR1_SPI6RSTS                 RCC_APB4RSTSR1_SPI6RSTS_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTSR1_I2C4RSTS_Pos             (7U)
+#define RCC_APB4RSTSR1_I2C4RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTSR1_I2C4RSTS                 RCC_APB4RSTSR1_I2C4RSTS_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos           (9U)
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTSR1_LPTIM2RSTS               RCC_APB4RSTSR1_LPTIM2RSTS_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos           (10U)
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTSR1_LPTIM3RSTS               RCC_APB4RSTSR1_LPTIM3RSTS_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos           (11U)
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTSR1_LPTIM4RSTS               RCC_APB4RSTSR1_LPTIM4RSTS_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos           (12U)
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTSR1_LPTIM5RSTS               RCC_APB4RSTSR1_LPTIM5RSTS_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos          (15U)
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk          (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTSR1_VREFBUFRSTS              RCC_APB4RSTSR1_VREFBUFRSTS_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTSR1_RTCRSTS_Pos              (16U)
+#define RCC_APB4RSTSR1_RTCRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTSR1_RTCRSTS                  RCC_APB4RSTSR1_RTCRSTS_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTSR2 register  ****************/
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos           (0U)
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk           (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTSR2_SYSCFGRSTS               RCC_APB4RSTSR2_SYSCFGRSTS_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTSR2_DTSRSTS_Pos              (2U)
+#define RCC_APB4RSTSR2_DTSRSTS_Msk              (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR2_DTSRSTS                  RCC_APB4RSTSR2_DTSRSTS_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTSR register  *****************/
+#define RCC_APB5RSTSR_LTDCRSTS_Pos              (1U)
+#define RCC_APB5RSTSR_LTDCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTSR_LTDCRSTS                  RCC_APB5RSTSR_LTDCRSTS_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTSR_DCMIPPRSTS_Pos            (2U)
+#define RCC_APB5RSTSR_DCMIPPRSTS_Msk            (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTSR_DCMIPPRSTS                RCC_APB5RSTSR_DCMIPPRSTS_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTSR_GFXTIMRSTS_Pos            (4U)
+#define RCC_APB5RSTSR_GFXTIMRSTS_Msk            (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTSR_GFXTIMRSTS                RCC_APB5RSTSR_GFXTIMRSTS_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTSR_VENCRSTS_Pos              (5U)
+#define RCC_APB5RSTSR_VENCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTSR_VENCRSTS                  RCC_APB5RSTSR_VENCRSTS_Msk           /*!< VENC reset */
+#define RCC_APB5RSTSR_CSIRSTS_Pos               (6U)
+#define RCC_APB5RSTSR_CSIRSTS_Msk               (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTSR_CSIRSTS                   RCC_APB5RSTSR_CSIRSTS_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENSR register  ******************/
+#define RCC_DIVENSR_IC1ENS_Pos                  (0U)
+#define RCC_DIVENSR_IC1ENS_Msk                  (0x1UL << RCC_DIVENSR_IC1ENS_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENSR_IC1ENS                      RCC_DIVENSR_IC1ENS_Msk               /*!< IC1 enable */
+#define RCC_DIVENSR_IC2ENS_Pos                  (1U)
+#define RCC_DIVENSR_IC2ENS_Msk                  (0x1UL << RCC_DIVENSR_IC2ENS_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENSR_IC2ENS                      RCC_DIVENSR_IC2ENS_Msk               /*!< IC2 enable */
+#define RCC_DIVENSR_IC3ENS_Pos                  (2U)
+#define RCC_DIVENSR_IC3ENS_Msk                  (0x1UL << RCC_DIVENSR_IC3ENS_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENSR_IC3ENS                      RCC_DIVENSR_IC3ENS_Msk               /*!< IC3 enable */
+#define RCC_DIVENSR_IC4ENS_Pos                  (3U)
+#define RCC_DIVENSR_IC4ENS_Msk                  (0x1UL << RCC_DIVENSR_IC4ENS_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENSR_IC4ENS                      RCC_DIVENSR_IC4ENS_Msk               /*!< IC4 enable */
+#define RCC_DIVENSR_IC5ENS_Pos                  (4U)
+#define RCC_DIVENSR_IC5ENS_Msk                  (0x1UL << RCC_DIVENSR_IC5ENS_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENSR_IC5ENS                      RCC_DIVENSR_IC5ENS_Msk               /*!< IC5 enable */
+#define RCC_DIVENSR_IC6ENS_Pos                  (5U)
+#define RCC_DIVENSR_IC6ENS_Msk                  (0x1UL << RCC_DIVENSR_IC6ENS_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENSR_IC6ENS                      RCC_DIVENSR_IC6ENS_Msk               /*!< IC6 enable */
+#define RCC_DIVENSR_IC7ENS_Pos                  (6U)
+#define RCC_DIVENSR_IC7ENS_Msk                  (0x1UL << RCC_DIVENSR_IC7ENS_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENSR_IC7ENS                      RCC_DIVENSR_IC7ENS_Msk               /*!< IC7 enable */
+#define RCC_DIVENSR_IC8ENS_Pos                  (7U)
+#define RCC_DIVENSR_IC8ENS_Msk                  (0x1UL << RCC_DIVENSR_IC8ENS_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENSR_IC8ENS                      RCC_DIVENSR_IC8ENS_Msk               /*!< IC8 enable */
+#define RCC_DIVENSR_IC9ENS_Pos                  (8U)
+#define RCC_DIVENSR_IC9ENS_Msk                  (0x1UL << RCC_DIVENSR_IC9ENS_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENSR_IC9ENS                      RCC_DIVENSR_IC9ENS_Msk               /*!< IC9 enable */
+#define RCC_DIVENSR_IC10ENS_Pos                 (9U)
+#define RCC_DIVENSR_IC10ENS_Msk                 (0x1UL << RCC_DIVENSR_IC10ENS_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENSR_IC10ENS                     RCC_DIVENSR_IC10ENS_Msk              /*!< IC10 enable */
+#define RCC_DIVENSR_IC11ENS_Pos                 (10U)
+#define RCC_DIVENSR_IC11ENS_Msk                 (0x1UL << RCC_DIVENSR_IC11ENS_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENSR_IC11ENS                     RCC_DIVENSR_IC11ENS_Msk              /*!< IC11 enable */
+#define RCC_DIVENSR_IC12ENS_Pos                 (11U)
+#define RCC_DIVENSR_IC12ENS_Msk                 (0x1UL << RCC_DIVENSR_IC12ENS_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENSR_IC12ENS                     RCC_DIVENSR_IC12ENS_Msk              /*!< IC12 enable */
+#define RCC_DIVENSR_IC13ENS_Pos                 (12U)
+#define RCC_DIVENSR_IC13ENS_Msk                 (0x1UL << RCC_DIVENSR_IC13ENS_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENSR_IC13ENS                     RCC_DIVENSR_IC13ENS_Msk              /*!< IC13 enable */
+#define RCC_DIVENSR_IC14ENS_Pos                 (13U)
+#define RCC_DIVENSR_IC14ENS_Msk                 (0x1UL << RCC_DIVENSR_IC14ENS_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENSR_IC14ENS                     RCC_DIVENSR_IC14ENS_Msk              /*!< IC14 enable */
+#define RCC_DIVENSR_IC15ENS_Pos                 (14U)
+#define RCC_DIVENSR_IC15ENS_Msk                 (0x1UL << RCC_DIVENSR_IC15ENS_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENSR_IC15ENS                     RCC_DIVENSR_IC15ENS_Msk              /*!< IC15 enable */
+#define RCC_DIVENSR_IC16ENS_Pos                 (15U)
+#define RCC_DIVENSR_IC16ENS_Msk                 (0x1UL << RCC_DIVENSR_IC16ENS_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENSR_IC16ENS                     RCC_DIVENSR_IC16ENS_Msk              /*!< IC16 enable */
+#define RCC_DIVENSR_IC17ENS_Pos                 (16U)
+#define RCC_DIVENSR_IC17ENS_Msk                 (0x1UL << RCC_DIVENSR_IC17ENS_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENSR_IC17ENS                     RCC_DIVENSR_IC17ENS_Msk              /*!< IC17 enable */
+#define RCC_DIVENSR_IC18ENS_Pos                 (17U)
+#define RCC_DIVENSR_IC18ENS_Msk                 (0x1UL << RCC_DIVENSR_IC18ENS_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENSR_IC18ENS                     RCC_DIVENSR_IC18ENS_Msk              /*!< IC18 enable */
+#define RCC_DIVENSR_IC19ENS_Pos                 (18U)
+#define RCC_DIVENSR_IC19ENS_Msk                 (0x1UL << RCC_DIVENSR_IC19ENS_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENSR_IC19ENS                     RCC_DIVENSR_IC19ENS_Msk              /*!< IC19 enable */
+#define RCC_DIVENSR_IC20ENS_Pos                 (19U)
+#define RCC_DIVENSR_IC20ENS_Msk                 (0x1UL << RCC_DIVENSR_IC20ENS_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENSR_IC20ENS                     RCC_DIVENSR_IC20ENS_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENSR register  ******************/
+#define RCC_BUSENSR_ACLKNENS_Pos                (0U)
+#define RCC_BUSENSR_ACLKNENS_Msk                (0x1UL << RCC_BUSENSR_ACLKNENS_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENSR_ACLKNENS                    RCC_BUSENSR_ACLKNENS_Msk             /*!< ACLKN enable */
+#define RCC_BUSENSR_ACLKNCENS_Pos               (1U)
+#define RCC_BUSENSR_ACLKNCENS_Msk               (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENSR_ACLKNCENS                   RCC_BUSENSR_ACLKNCENS_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENSR_AHBMENS_Pos                 (2U)
+#define RCC_BUSENSR_AHBMENS_Msk                 (0x1UL << RCC_BUSENSR_AHBMENS_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENSR_AHBMENS                     RCC_BUSENSR_AHBMENS_Msk              /*!< AHBM enable */
+#define RCC_BUSENSR_AHB1ENS_Pos                 (3U)
+#define RCC_BUSENSR_AHB1ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB1ENS_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENSR_AHB1ENS                     RCC_BUSENSR_AHB1ENS_Msk              /*!< AHB1 enable */
+#define RCC_BUSENSR_AHB2ENS_Pos                 (4U)
+#define RCC_BUSENSR_AHB2ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB2ENS_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENSR_AHB2ENS                     RCC_BUSENSR_AHB2ENS_Msk              /*!< AHB2 enable */
+#define RCC_BUSENSR_AHB3ENS_Pos                 (5U)
+#define RCC_BUSENSR_AHB3ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB3ENS_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENSR_AHB3ENS                     RCC_BUSENSR_AHB3ENS_Msk              /*!< AHB3 enable */
+#define RCC_BUSENSR_AHB4ENS_Pos                 (6U)
+#define RCC_BUSENSR_AHB4ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB4ENS_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENSR_AHB4ENS                     RCC_BUSENSR_AHB4ENS_Msk              /*!< AHB4 enable */
+#define RCC_BUSENSR_AHB5ENS_Pos                 (7U)
+#define RCC_BUSENSR_AHB5ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB5ENS_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENSR_AHB5ENS                     RCC_BUSENSR_AHB5ENS_Msk              /*!< AHB5 enable */
+#define RCC_BUSENSR_APB1ENS_Pos                 (8U)
+#define RCC_BUSENSR_APB1ENS_Msk                 (0x1UL << RCC_BUSENSR_APB1ENS_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENSR_APB1ENS                     RCC_BUSENSR_APB1ENS_Msk              /*!< APB1 enable */
+#define RCC_BUSENSR_APB2ENS_Pos                 (9U)
+#define RCC_BUSENSR_APB2ENS_Msk                 (0x1UL << RCC_BUSENSR_APB2ENS_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENSR_APB2ENS                     RCC_BUSENSR_APB2ENS_Msk              /*!< APB2 enable */
+#define RCC_BUSENSR_APB3ENS_Pos                 (10U)
+#define RCC_BUSENSR_APB3ENS_Msk                 (0x1UL << RCC_BUSENSR_APB3ENS_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENSR_APB3ENS                     RCC_BUSENSR_APB3ENS_Msk              /*!< APB3 enable */
+#define RCC_BUSENSR_APB4ENS_Pos                 (11U)
+#define RCC_BUSENSR_APB4ENS_Msk                 (0x1UL << RCC_BUSENSR_APB4ENS_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENSR_APB4ENS                     RCC_BUSENSR_APB4ENS_Msk              /*!< APB4 enable */
+#define RCC_BUSENSR_APB5ENS_Pos                 (12U)
+#define RCC_BUSENSR_APB5ENS_Msk                 (0x1UL << RCC_BUSENSR_APB5ENS_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENSR_APB5ENS                     RCC_BUSENSR_APB5ENS_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENSR register  *****************/
+#define RCC_MISCENSR_DBGENS_Pos                 (0U)
+#define RCC_MISCENSR_DBGENS_Msk                 (0x1UL << RCC_MISCENSR_DBGENS_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENSR_DBGENS                     RCC_MISCENSR_DBGENS_Msk              /*!< DBG enable */
+#define RCC_MISCENSR_MCO1ENS_Pos                (1U)
+#define RCC_MISCENSR_MCO1ENS_Msk                (0x1UL << RCC_MISCENSR_MCO1ENS_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENSR_MCO1ENS                    RCC_MISCENSR_MCO1ENS_Msk             /*!< MCO1 enable */
+#define RCC_MISCENSR_MCO2ENS_Pos                (2U)
+#define RCC_MISCENSR_MCO2ENS_Msk                (0x1UL << RCC_MISCENSR_MCO2ENS_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENSR_MCO2ENS                    RCC_MISCENSR_MCO2ENS_Msk             /*!< MCO2 enable */
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos         (3U)
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk         (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENSR_XSPIPHYCOMPENS             RCC_MISCENSR_XSPIPHYCOMPENS_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENSR_PERENS_Pos                 (6U)
+#define RCC_MISCENSR_PERENS_Msk                 (0x1UL << RCC_MISCENSR_PERENS_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENSR_PERENS                     RCC_MISCENSR_PERENS_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENSR register  ******************/
+#define RCC_MEMENSR_AXISRAM3ENS_Pos             (0U)
+#define RCC_MEMENSR_AXISRAM3ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */
+#define RCC_MEMENSR_AXISRAM3ENS                 RCC_MEMENSR_AXISRAM3ENS_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENSR_AXISRAM4ENS_Pos             (1U)
+#define RCC_MEMENSR_AXISRAM4ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */
+#define RCC_MEMENSR_AXISRAM4ENS                 RCC_MEMENSR_AXISRAM4ENS_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENSR_AXISRAM5ENS_Pos             (2U)
+#define RCC_MEMENSR_AXISRAM5ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */
+#define RCC_MEMENSR_AXISRAM5ENS                 RCC_MEMENSR_AXISRAM5ENS_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENSR_AXISRAM6ENS_Pos             (3U)
+#define RCC_MEMENSR_AXISRAM6ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */
+#define RCC_MEMENSR_AXISRAM6ENS                 RCC_MEMENSR_AXISRAM6ENS_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENSR_AHBSRAM1ENS_Pos             (4U)
+#define RCC_MEMENSR_AHBSRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */
+#define RCC_MEMENSR_AHBSRAM1ENS                 RCC_MEMENSR_AHBSRAM1ENS_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENSR_AHBSRAM2ENS_Pos             (5U)
+#define RCC_MEMENSR_AHBSRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */
+#define RCC_MEMENSR_AHBSRAM2ENS                 RCC_MEMENSR_AHBSRAM2ENS_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENSR_BKPSRAMENS_Pos              (6U)
+#define RCC_MEMENSR_BKPSRAMENS_Msk              (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */
+#define RCC_MEMENSR_BKPSRAMENS                  RCC_MEMENSR_BKPSRAMENS_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENSR_AXISRAM1ENS_Pos             (7U)
+#define RCC_MEMENSR_AXISRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */
+#define RCC_MEMENSR_AXISRAM1ENS                 RCC_MEMENSR_AXISRAM1ENS_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENSR_AXISRAM2ENS_Pos             (8U)
+#define RCC_MEMENSR_AXISRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */
+#define RCC_MEMENSR_AXISRAM2ENS                 RCC_MEMENSR_AXISRAM2ENS_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENSR_FLEXRAMENS_Pos              (9U)
+#define RCC_MEMENSR_FLEXRAMENS_Msk              (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */
+#define RCC_MEMENSR_FLEXRAMENS                  RCC_MEMENSR_FLEXRAMENS_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENSR_VENCRAMENS_Pos              (11U)
+#define RCC_MEMENSR_VENCRAMENS_Msk              (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */
+#define RCC_MEMENSR_VENCRAMENS                  RCC_MEMENSR_VENCRAMENS_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENSR_BOOTROMENS_Pos              (12U)
+#define RCC_MEMENSR_BOOTROMENS_Msk              (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */
+#define RCC_MEMENSR_BOOTROMENS                  RCC_MEMENSR_BOOTROMENS_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENSR register  *****************/
+#define RCC_AHB1ENSR_GPDMA1ENS_Pos              (4U)
+#define RCC_AHB1ENSR_GPDMA1ENS_Msk              (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENSR_GPDMA1ENS                  RCC_AHB1ENSR_GPDMA1ENS_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENSR_ADC12ENS_Pos               (5U)
+#define RCC_AHB1ENSR_ADC12ENS_Msk               (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENSR_ADC12ENS                   RCC_AHB1ENSR_ADC12ENS_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENSR register  *****************/
+#define RCC_AHB2ENSR_RAMCFGENS_Pos              (12U)
+#define RCC_AHB2ENSR_RAMCFGENS_Msk              (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENSR_RAMCFGENS                  RCC_AHB2ENSR_RAMCFGENS_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENSR_MDF1ENS_Pos                (16U)
+#define RCC_AHB2ENSR_MDF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENSR_MDF1ENS                    RCC_AHB2ENSR_MDF1ENS_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENSR_ADF1ENS_Pos                (17U)
+#define RCC_AHB2ENSR_ADF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENSR_ADF1ENS                    RCC_AHB2ENSR_ADF1ENS_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENSR register  *****************/
+#define RCC_AHB3ENSR_RNGENS_Pos                 (0U)
+#define RCC_AHB3ENSR_RNGENS_Msk                 (0x1UL << RCC_AHB3ENSR_RNGENS_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENSR_RNGENS                     RCC_AHB3ENSR_RNGENS_Msk              /*!< RNG enable */
+#define RCC_AHB3ENSR_HASHENS_Pos                (1U)
+#define RCC_AHB3ENSR_HASHENS_Msk                (0x1UL << RCC_AHB3ENSR_HASHENS_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENSR_HASHENS                    RCC_AHB3ENSR_HASHENS_Msk             /*!< HASH enable */
+#define RCC_AHB3ENSR_PKAENS_Pos                 (8U)
+#define RCC_AHB3ENSR_PKAENS_Msk                 (0x1UL << RCC_AHB3ENSR_PKAENS_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENSR_PKAENS                     RCC_AHB3ENSR_PKAENS_Msk              /*!< PKA enable */
+#define RCC_AHB3ENSR_RIFSCENS_Pos               (9U)
+#define RCC_AHB3ENSR_RIFSCENS_Msk               (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENSR_RIFSCENS                   RCC_AHB3ENSR_RIFSCENS_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENSR_IACENS_Pos                 (10U)
+#define RCC_AHB3ENSR_IACENS_Msk                 (0x1UL << RCC_AHB3ENSR_IACENS_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENSR_IACENS                     RCC_AHB3ENSR_IACENS_Msk              /*!< IAC enable */
+#define RCC_AHB3ENSR_RISAFENS_Pos               (14U)
+#define RCC_AHB3ENSR_RISAFENS_Msk               (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENSR_RISAFENS                   RCC_AHB3ENSR_RISAFENS_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENSR register  *****************/
+#define RCC_AHB4ENSR_GPIOAENS_Pos               (0U)
+#define RCC_AHB4ENSR_GPIOAENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENSR_GPIOAENS                   RCC_AHB4ENSR_GPIOAENS_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENSR_GPIOBENS_Pos               (1U)
+#define RCC_AHB4ENSR_GPIOBENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENSR_GPIOBENS                   RCC_AHB4ENSR_GPIOBENS_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENSR_GPIOCENS_Pos               (2U)
+#define RCC_AHB4ENSR_GPIOCENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENSR_GPIOCENS                   RCC_AHB4ENSR_GPIOCENS_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENSR_GPIODENS_Pos               (3U)
+#define RCC_AHB4ENSR_GPIODENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENSR_GPIODENS                   RCC_AHB4ENSR_GPIODENS_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENSR_GPIOEENS_Pos               (4U)
+#define RCC_AHB4ENSR_GPIOEENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENSR_GPIOEENS                   RCC_AHB4ENSR_GPIOEENS_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENSR_GPIOFENS_Pos               (5U)
+#define RCC_AHB4ENSR_GPIOFENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENSR_GPIOFENS                   RCC_AHB4ENSR_GPIOFENS_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENSR_GPIOGENS_Pos               (6U)
+#define RCC_AHB4ENSR_GPIOGENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENSR_GPIOGENS                   RCC_AHB4ENSR_GPIOGENS_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENSR_GPIOHENS_Pos               (7U)
+#define RCC_AHB4ENSR_GPIOHENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENSR_GPIOHENS                   RCC_AHB4ENSR_GPIOHENS_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENSR_GPIONENS_Pos               (13U)
+#define RCC_AHB4ENSR_GPIONENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENSR_GPIONENS                   RCC_AHB4ENSR_GPIONENS_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENSR_GPIOOENS_Pos               (14U)
+#define RCC_AHB4ENSR_GPIOOENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENSR_GPIOOENS                   RCC_AHB4ENSR_GPIOOENS_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENSR_GPIOPENS_Pos               (15U)
+#define RCC_AHB4ENSR_GPIOPENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENSR_GPIOPENS                   RCC_AHB4ENSR_GPIOPENS_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENSR_GPIOQENS_Pos               (16U)
+#define RCC_AHB4ENSR_GPIOQENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENSR_GPIOQENS                   RCC_AHB4ENSR_GPIOQENS_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENSR_PWRENS_Pos                 (18U)
+#define RCC_AHB4ENSR_PWRENS_Msk                 (0x1UL << RCC_AHB4ENSR_PWRENS_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENSR_PWRENS                     RCC_AHB4ENSR_PWRENS_Msk              /*!< PWR enable */
+#define RCC_AHB4ENSR_CRCENS_Pos                 (19U)
+#define RCC_AHB4ENSR_CRCENS_Msk                 (0x1UL << RCC_AHB4ENSR_CRCENS_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENSR_CRCENS                     RCC_AHB4ENSR_CRCENS_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENSR register  *****************/
+#define RCC_AHB5ENSR_HPDMA1ENS_Pos              (0U)
+#define RCC_AHB5ENSR_HPDMA1ENS_Msk              (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENSR_HPDMA1ENS                  RCC_AHB5ENSR_HPDMA1ENS_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENSR_DMA2DENS_Pos               (1U)
+#define RCC_AHB5ENSR_DMA2DENS_Msk               (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENSR_DMA2DENS                   RCC_AHB5ENSR_DMA2DENS_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENSR_JPEGENS_Pos                (3U)
+#define RCC_AHB5ENSR_JPEGENS_Msk                (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENSR_JPEGENS                    RCC_AHB5ENSR_JPEGENS_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENSR_FMCENS_Pos                 (4U)
+#define RCC_AHB5ENSR_FMCENS_Msk                 (0x1UL << RCC_AHB5ENSR_FMCENS_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENSR_FMCENS                     RCC_AHB5ENSR_FMCENS_Msk              /*!< FMC enable */
+#define RCC_AHB5ENSR_XSPI1ENS_Pos               (5U)
+#define RCC_AHB5ENSR_XSPI1ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENSR_XSPI1ENS                   RCC_AHB5ENSR_XSPI1ENS_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENSR_PSSIENS_Pos                (6U)
+#define RCC_AHB5ENSR_PSSIENS_Msk                (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENSR_PSSIENS                    RCC_AHB5ENSR_PSSIENS_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENSR_SDMMC2ENS_Pos              (7U)
+#define RCC_AHB5ENSR_SDMMC2ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENSR_SDMMC2ENS                  RCC_AHB5ENSR_SDMMC2ENS_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENSR_SDMMC1ENS_Pos              (8U)
+#define RCC_AHB5ENSR_SDMMC1ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENSR_SDMMC1ENS                  RCC_AHB5ENSR_SDMMC1ENS_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENSR_XSPI2ENS_Pos               (12U)
+#define RCC_AHB5ENSR_XSPI2ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENSR_XSPI2ENS                   RCC_AHB5ENSR_XSPI2ENS_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENSR_XSPIMENS_Pos               (13U)
+#define RCC_AHB5ENSR_XSPIMENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENSR_XSPIMENS                   RCC_AHB5ENSR_XSPIMENS_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENSR_XSPI3ENS_Pos               (17U)
+#define RCC_AHB5ENSR_XSPI3ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENSR_XSPI3ENS                   RCC_AHB5ENSR_XSPI3ENS_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENSR_GFXMMUENS_Pos              (19U)
+#define RCC_AHB5ENSR_GFXMMUENS_Msk              (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENSR_GFXMMUENS                  RCC_AHB5ENSR_GFXMMUENS_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENSR_GPU2DENS_Pos               (20U)
+#define RCC_AHB5ENSR_GPU2DENS_Msk               (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENSR_GPU2DENS                   RCC_AHB5ENSR_GPU2DENS_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENSR_ETH1MACENS_Pos             (22U)
+#define RCC_AHB5ENSR_ETH1MACENS_Msk             (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENSR_ETH1MACENS                 RCC_AHB5ENSR_ETH1MACENS_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENSR_ETH1TXENS_Pos              (23U)
+#define RCC_AHB5ENSR_ETH1TXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENSR_ETH1TXENS                  RCC_AHB5ENSR_ETH1TXENS_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENSR_ETH1RXENS_Pos              (24U)
+#define RCC_AHB5ENSR_ETH1RXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENSR_ETH1RXENS                  RCC_AHB5ENSR_ETH1RXENS_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENSR_ETH1ENS_Pos                (25U)
+#define RCC_AHB5ENSR_ETH1ENS_Msk                (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENSR_ETH1ENS                    RCC_AHB5ENSR_ETH1ENS_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENSR_OTG1ENS_Pos                (26U)
+#define RCC_AHB5ENSR_OTG1ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENSR_OTG1ENS                    RCC_AHB5ENSR_OTG1ENS_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENSR_OTGPHY1ENS_Pos             (27U)
+#define RCC_AHB5ENSR_OTGPHY1ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENSR_OTGPHY1ENS                 RCC_AHB5ENSR_OTGPHY1ENS_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENSR_OTGPHY2ENS_Pos             (28U)
+#define RCC_AHB5ENSR_OTGPHY2ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENSR_OTGPHY2ENS                 RCC_AHB5ENSR_OTGPHY2ENS_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENSR_OTG2ENS_Pos                (29U)
+#define RCC_AHB5ENSR_OTG2ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENSR_OTG2ENS                    RCC_AHB5ENSR_OTG2ENS_Msk             /*!< OTG2 enable */
+
+/****************  Bit definition for RCC_APB1ENSR1 register  *****************/
+#define RCC_APB1ENSR1_TIM2ENS_Pos               (0U)
+#define RCC_APB1ENSR1_TIM2ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENSR1_TIM2ENS                   RCC_APB1ENSR1_TIM2ENS_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENSR1_TIM3ENS_Pos               (1U)
+#define RCC_APB1ENSR1_TIM3ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENSR1_TIM3ENS                   RCC_APB1ENSR1_TIM3ENS_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENSR1_TIM4ENS_Pos               (2U)
+#define RCC_APB1ENSR1_TIM4ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENSR1_TIM4ENS                   RCC_APB1ENSR1_TIM4ENS_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENSR1_TIM5ENS_Pos               (3U)
+#define RCC_APB1ENSR1_TIM5ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENSR1_TIM5ENS                   RCC_APB1ENSR1_TIM5ENS_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENSR1_TIM6ENS_Pos               (4U)
+#define RCC_APB1ENSR1_TIM6ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENSR1_TIM6ENS                   RCC_APB1ENSR1_TIM6ENS_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENSR1_TIM7ENS_Pos               (5U)
+#define RCC_APB1ENSR1_TIM7ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENSR1_TIM7ENS                   RCC_APB1ENSR1_TIM7ENS_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENSR1_TIM12ENS_Pos              (6U)
+#define RCC_APB1ENSR1_TIM12ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENSR1_TIM12ENS                  RCC_APB1ENSR1_TIM12ENS_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENSR1_TIM13ENS_Pos              (7U)
+#define RCC_APB1ENSR1_TIM13ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENSR1_TIM13ENS                  RCC_APB1ENSR1_TIM13ENS_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENSR1_TIM14ENS_Pos              (8U)
+#define RCC_APB1ENSR1_TIM14ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR1_TIM14ENS                  RCC_APB1ENSR1_TIM14ENS_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENSR1_LPTIM1ENS_Pos             (9U)
+#define RCC_APB1ENSR1_LPTIM1ENS_Msk             (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENSR1_LPTIM1ENS                 RCC_APB1ENSR1_LPTIM1ENS_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENSR1_WWDGENS_Pos               (11U)
+#define RCC_APB1ENSR1_WWDGENS_Msk               (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1ENSR1_WWDGENS                   RCC_APB1ENSR1_WWDGENS_Msk            /*!< WWDG enable */
+#define RCC_APB1ENSR1_TIM10ENS_Pos              (12U)
+#define RCC_APB1ENSR1_TIM10ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENSR1_TIM10ENS                  RCC_APB1ENSR1_TIM10ENS_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENSR1_TIM11ENS_Pos              (13U)
+#define RCC_APB1ENSR1_TIM11ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENSR1_TIM11ENS                  RCC_APB1ENSR1_TIM11ENS_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENSR1_SPI2ENS_Pos               (14U)
+#define RCC_APB1ENSR1_SPI2ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENSR1_SPI2ENS                   RCC_APB1ENSR1_SPI2ENS_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENSR1_SPI3ENS_Pos               (15U)
+#define RCC_APB1ENSR1_SPI3ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENSR1_SPI3ENS                   RCC_APB1ENSR1_SPI3ENS_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos           (16U)
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk           (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENSR1_SPDIFRX1ENS               RCC_APB1ENSR1_SPDIFRX1ENS_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENSR1_USART2ENS_Pos             (17U)
+#define RCC_APB1ENSR1_USART2ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENSR1_USART2ENS                 RCC_APB1ENSR1_USART2ENS_Msk          /*!< USART2 enable */
+#define RCC_APB1ENSR1_USART3ENS_Pos             (18U)
+#define RCC_APB1ENSR1_USART3ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENSR1_USART3ENS                 RCC_APB1ENSR1_USART3ENS_Msk          /*!< USART3 enable */
+#define RCC_APB1ENSR1_UART4ENS_Pos              (19U)
+#define RCC_APB1ENSR1_UART4ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENSR1_UART4ENS                  RCC_APB1ENSR1_UART4ENS_Msk           /*!< UART4 enable */
+#define RCC_APB1ENSR1_UART5ENS_Pos              (20U)
+#define RCC_APB1ENSR1_UART5ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENSR1_UART5ENS                  RCC_APB1ENSR1_UART5ENS_Msk           /*!< UART5 enable */
+#define RCC_APB1ENSR1_I2C1ENS_Pos               (21U)
+#define RCC_APB1ENSR1_I2C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENSR1_I2C1ENS                   RCC_APB1ENSR1_I2C1ENS_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENSR1_I2C2ENS_Pos               (22U)
+#define RCC_APB1ENSR1_I2C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENSR1_I2C2ENS                   RCC_APB1ENSR1_I2C2ENS_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENSR1_I2C3ENS_Pos               (23U)
+#define RCC_APB1ENSR1_I2C3ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENSR1_I2C3ENS                   RCC_APB1ENSR1_I2C3ENS_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENSR1_I3C1ENS_Pos               (24U)
+#define RCC_APB1ENSR1_I3C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENSR1_I3C1ENS                   RCC_APB1ENSR1_I3C1ENS_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENSR1_I3C2ENS_Pos               (25U)
+#define RCC_APB1ENSR1_I3C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENSR1_I3C2ENS                   RCC_APB1ENSR1_I3C2ENS_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENSR1_UART7ENS_Pos              (30U)
+#define RCC_APB1ENSR1_UART7ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENSR1_UART7ENS                  RCC_APB1ENSR1_UART7ENS_Msk           /*!< UART7 enable */
+#define RCC_APB1ENSR1_UART8ENS_Pos              (31U)
+#define RCC_APB1ENSR1_UART8ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENSR1_UART8ENS                  RCC_APB1ENSR1_UART8ENS_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENSR2 register  *****************/
+#define RCC_APB1ENSR2_MDIOSENS_Pos              (5U)
+#define RCC_APB1ENSR2_MDIOSENS_Msk              (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENSR2_MDIOSENS                  RCC_APB1ENSR2_MDIOSENS_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENSR2_FDCANENS_Pos              (8U)
+#define RCC_APB1ENSR2_FDCANENS_Msk              (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR2_FDCANENS                  RCC_APB1ENSR2_FDCANENS_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENSR2_UCPD1ENS_Pos              (18U)
+#define RCC_APB1ENSR2_UCPD1ENS_Msk              (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENSR2_UCPD1ENS                  RCC_APB1ENSR2_UCPD1ENS_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENSR register  *****************/
+#define RCC_APB2ENSR_TIM1ENS_Pos                (0U)
+#define RCC_APB2ENSR_TIM1ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENSR_TIM1ENS                    RCC_APB2ENSR_TIM1ENS_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENSR_TIM8ENS_Pos                (1U)
+#define RCC_APB2ENSR_TIM8ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENSR_TIM8ENS                    RCC_APB2ENSR_TIM8ENS_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENSR_USART1ENS_Pos              (4U)
+#define RCC_APB2ENSR_USART1ENS_Msk              (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENSR_USART1ENS                  RCC_APB2ENSR_USART1ENS_Msk           /*!< USART1 enable */
+#define RCC_APB2ENSR_USART6ENS_Pos              (5U)
+#define RCC_APB2ENSR_USART6ENS_Msk              (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENSR_USART6ENS                  RCC_APB2ENSR_USART6ENS_Msk           /*!< USART6 enable */
+#define RCC_APB2ENSR_UART9ENS_Pos               (6U)
+#define RCC_APB2ENSR_UART9ENS_Msk               (0x1UL << RCC_APB2ENSR_UART9ENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENSR_UART9ENS                   RCC_APB2ENSR_UART9ENS_Msk            /*!< UART9 enable */
+#define RCC_APB2ENSR_USART10ENS_Pos             (7U)
+#define RCC_APB2ENSR_USART10ENS_Msk             (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENSR_USART10ENS                 RCC_APB2ENSR_USART10ENS_Msk          /*!< USART10 enable */
+#define RCC_APB2ENSR_SPI1ENS_Pos                (12U)
+#define RCC_APB2ENSR_SPI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENSR_SPI1ENS                    RCC_APB2ENSR_SPI1ENS_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENSR_SPI4ENS_Pos                (13U)
+#define RCC_APB2ENSR_SPI4ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENSR_SPI4ENS                    RCC_APB2ENSR_SPI4ENS_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENSR_TIM18ENS_Pos               (15U)
+#define RCC_APB2ENSR_TIM18ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENSR_TIM18ENS                   RCC_APB2ENSR_TIM18ENS_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENSR_TIM15ENS_Pos               (16U)
+#define RCC_APB2ENSR_TIM15ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENSR_TIM15ENS                   RCC_APB2ENSR_TIM15ENS_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENSR_TIM16ENS_Pos               (17U)
+#define RCC_APB2ENSR_TIM16ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENSR_TIM16ENS                   RCC_APB2ENSR_TIM16ENS_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENSR_TIM17ENS_Pos               (18U)
+#define RCC_APB2ENSR_TIM17ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENSR_TIM17ENS                   RCC_APB2ENSR_TIM17ENS_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENSR_TIM9ENS_Pos                (19U)
+#define RCC_APB2ENSR_TIM9ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENSR_TIM9ENS                    RCC_APB2ENSR_TIM9ENS_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENSR_SPI5ENS_Pos                (20U)
+#define RCC_APB2ENSR_SPI5ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENSR_SPI5ENS                    RCC_APB2ENSR_SPI5ENS_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENSR_SAI1ENS_Pos                (21U)
+#define RCC_APB2ENSR_SAI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENSR_SAI1ENS                    RCC_APB2ENSR_SAI1ENS_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENSR_SAI2ENS_Pos                (22U)
+#define RCC_APB2ENSR_SAI2ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENSR_SAI2ENS                    RCC_APB2ENSR_SAI2ENS_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENSR register  *****************/
+#define RCC_APB3ENSR_DFTENS_Pos                 (2U)
+#define RCC_APB3ENSR_DFTENS_Msk                 (0x1UL << RCC_APB3ENSR_DFTENS_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENSR_DFTENS                     RCC_APB3ENSR_DFTENS_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENSR1 register  *****************/
+#define RCC_APB4ENSR1_HDPENS_Pos                (2U)
+#define RCC_APB4ENSR1_HDPENS_Msk                (0x1UL << RCC_APB4ENSR1_HDPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR1_HDPENS                    RCC_APB4ENSR1_HDPENS_Msk             /*!< HDP enable */
+#define RCC_APB4ENSR1_LPUART1ENS_Pos            (3U)
+#define RCC_APB4ENSR1_LPUART1ENS_Msk            (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENSR1_LPUART1ENS                RCC_APB4ENSR1_LPUART1ENS_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENSR1_SPI6ENS_Pos               (5U)
+#define RCC_APB4ENSR1_SPI6ENS_Msk               (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENSR1_SPI6ENS                   RCC_APB4ENSR1_SPI6ENS_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENSR1_I2C4ENS_Pos               (7U)
+#define RCC_APB4ENSR1_I2C4ENS_Msk               (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENSR1_I2C4ENS                   RCC_APB4ENSR1_I2C4ENS_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENSR1_LPTIM2ENS_Pos             (9U)
+#define RCC_APB4ENSR1_LPTIM2ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENSR1_LPTIM2ENS                 RCC_APB4ENSR1_LPTIM2ENS_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENSR1_LPTIM3ENS_Pos             (10U)
+#define RCC_APB4ENSR1_LPTIM3ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENSR1_LPTIM3ENS                 RCC_APB4ENSR1_LPTIM3ENS_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENSR1_LPTIM4ENS_Pos             (11U)
+#define RCC_APB4ENSR1_LPTIM4ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENSR1_LPTIM4ENS                 RCC_APB4ENSR1_LPTIM4ENS_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENSR1_LPTIM5ENS_Pos             (12U)
+#define RCC_APB4ENSR1_LPTIM5ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENSR1_LPTIM5ENS                 RCC_APB4ENSR1_LPTIM5ENS_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENSR1_VREFBUFENS_Pos            (15U)
+#define RCC_APB4ENSR1_VREFBUFENS_Msk            (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENSR1_VREFBUFENS                RCC_APB4ENSR1_VREFBUFENS_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENSR1_RTCENS_Pos                (16U)
+#define RCC_APB4ENSR1_RTCENS_Msk                (0x1UL << RCC_APB4ENSR1_RTCENS_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENSR1_RTCENS                    RCC_APB4ENSR1_RTCENS_Msk             /*!< RTC enable */
+#define RCC_APB4ENSR1_RTCAPBENS_Pos             (17U)
+#define RCC_APB4ENSR1_RTCAPBENS_Msk             (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENSR1_RTCAPBENS                 RCC_APB4ENSR1_RTCAPBENS_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENSR2 register  *****************/
+#define RCC_APB4ENSR2_SYSCFGENS_Pos             (0U)
+#define RCC_APB4ENSR2_SYSCFGENS_Msk             (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENSR2_SYSCFGENS                 RCC_APB4ENSR2_SYSCFGENS_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENSR2_BSECENS_Pos               (1U)
+#define RCC_APB4ENSR2_BSECENS_Msk               (0x1UL << RCC_APB4ENSR2_BSECENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENSR2_BSECENS                   RCC_APB4ENSR2_BSECENS_Msk            /*!< BSEC enable */
+#define RCC_APB4ENSR2_DTSENS_Pos                (2U)
+#define RCC_APB4ENSR2_DTSENS_Msk                (0x1UL << RCC_APB4ENSR2_DTSENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR2_DTSENS                    RCC_APB4ENSR2_DTSENS_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENSR register  *****************/
+#define RCC_APB5ENSR_LTDCENS_Pos                (1U)
+#define RCC_APB5ENSR_LTDCENS_Msk                (0x1UL << RCC_APB5ENSR_LTDCENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENSR_LTDCENS                    RCC_APB5ENSR_LTDCENS_Msk             /*!< LTDC enable */
+#define RCC_APB5ENSR_DCMIPPENS_Pos              (2U)
+#define RCC_APB5ENSR_DCMIPPENS_Msk              (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENSR_DCMIPPENS                  RCC_APB5ENSR_DCMIPPENS_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENSR_GFXTIMENS_Pos              (4U)
+#define RCC_APB5ENSR_GFXTIMENS_Msk              (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENSR_GFXTIMENS                  RCC_APB5ENSR_GFXTIMENS_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENSR_VENCENS_Pos                (5U)
+#define RCC_APB5ENSR_VENCENS_Msk                (0x1UL << RCC_APB5ENSR_VENCENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENSR_VENCENS                    RCC_APB5ENSR_VENCENS_Msk             /*!< VENC enable */
+#define RCC_APB5ENSR_CSIENS_Pos                 (6U)
+#define RCC_APB5ENSR_CSIENS_Msk                 (0x1UL << RCC_APB5ENSR_CSIENS_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENSR_CSIENS                     RCC_APB5ENSR_CSIENS_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENSR register  *****************/
+#define RCC_BUSLPENSR_ACLKNLPENS_Pos            (0U)
+#define RCC_BUSLPENSR_ACLKNLPENS_Msk            (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENSR_ACLKNLPENS                RCC_BUSLPENSR_ACLKNLPENS_Msk         /*!< ACLKN enable  */
+#define RCC_BUSLPENSR_ACLKNCLPENS_Pos           (1U)
+#define RCC_BUSLPENSR_ACLKNCLPENS_Msk           (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENSR_ACLKNCLPENS               RCC_BUSLPENSR_ACLKNCLPENS_Msk        /*!< ACLKNC enable  */
+
+/****************  Bit definition for RCC_MISCLPENSR register  ****************/
+#define RCC_MISCLPENSR_DBGLPENS_Pos             (0U)
+#define RCC_MISCLPENSR_DBGLPENS_Msk             (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENSR_DBGLPENS                 RCC_MISCLPENSR_DBGLPENS_Msk          /*!< DBG enable  */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos     (3U)
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk     (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS         RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk  /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENSR_PERLPENS_Pos             (6U)
+#define RCC_MISCLPENSR_PERLPENS_Msk             (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENSR_PERLPENS                 RCC_MISCLPENSR_PERLPENS_Msk          /*!< PER enable  */
+
+/****************  Bit definition for RCC_MEMLPENSR register  *****************/
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos         (0U)
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENSR_AXISRAM3LPENS             RCC_MEMLPENSR_AXISRAM3LPENS_Msk      /*!< AXISRAM3 enable  */
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos         (1U)
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENSR_AXISRAM4LPENS             RCC_MEMLPENSR_AXISRAM4LPENS_Msk      /*!< AXISRAM4 enable  */
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos         (2U)
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENSR_AXISRAM5LPENS             RCC_MEMLPENSR_AXISRAM5LPENS_Msk      /*!< AXISRAM5 enable  */
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos         (3U)
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENSR_AXISRAM6LPENS             RCC_MEMLPENSR_AXISRAM6LPENS_Msk      /*!< AXISRAM6 enable  */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos         (4U)
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS             RCC_MEMLPENSR_AHBSRAM1LPENS_Msk      /*!< AHBSRAM1 enable  */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos         (5U)
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS             RCC_MEMLPENSR_AHBSRAM2LPENS_Msk      /*!< AHBSRAM2 enable  */
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos          (6U)
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENSR_BKPSRAMLPENS              RCC_MEMLPENSR_BKPSRAMLPENS_Msk       /*!< BKPSRAM enable  */
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos         (7U)
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENSR_AXISRAM1LPENS             RCC_MEMLPENSR_AXISRAM1LPENS_Msk      /*!< AXISRAM1 enable  */
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos         (8U)
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENSR_AXISRAM2LPENS             RCC_MEMLPENSR_AXISRAM2LPENS_Msk      /*!< AXISRAM2 enable  */
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos          (9U)
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENSR_FLEXRAMLPENS              RCC_MEMLPENSR_FLEXRAMLPENS_Msk       /*!< FLEXRAM enable  */
+#define RCC_MEMLPENSR_VENCRAMLPENS_Pos          (11U)
+#define RCC_MEMLPENSR_VENCRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENSR_VENCRAMLPENS              RCC_MEMLPENSR_VENCRAMLPENS_Msk       /*!< VENCRAM enable  */
+#define RCC_MEMLPENSR_BOOTROMLPENS_Pos          (12U)
+#define RCC_MEMLPENSR_BOOTROMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENSR_BOOTROMLPENS              RCC_MEMLPENSR_BOOTROMLPENS_Msk       /*!< Boot ROM enable  */
+
+/****************  Bit definition for RCC_AHB1LPENSR register  ****************/
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos          (4U)
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk          (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENSR_GPDMA1LPENS              RCC_AHB1LPENSR_GPDMA1LPENS_Msk       /*!< GPDMA1 enable  */
+#define RCC_AHB1LPENSR_ADC12LPENS_Pos           (5U)
+#define RCC_AHB1LPENSR_ADC12LPENS_Msk           (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENSR_ADC12LPENS               RCC_AHB1LPENSR_ADC12LPENS_Msk        /*!< ADC12 enable  */
+
+/****************  Bit definition for RCC_AHB2LPENSR register  ****************/
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos          (12U)
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk          (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENSR_RAMCFGLPENS              RCC_AHB2LPENSR_RAMCFGLPENS_Msk       /*!< RAMCFG enable  */
+#define RCC_AHB2LPENSR_MDF1LPENS_Pos            (16U)
+#define RCC_AHB2LPENSR_MDF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENSR_MDF1LPENS                RCC_AHB2LPENSR_MDF1LPENS_Msk         /*!< MDF1 enable  */
+#define RCC_AHB2LPENSR_ADF1LPENS_Pos            (17U)
+#define RCC_AHB2LPENSR_ADF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENSR_ADF1LPENS                RCC_AHB2LPENSR_ADF1LPENS_Msk         /*!< ADF1 enable  */
+
+/****************  Bit definition for RCC_AHB3LPENSR register  ****************/
+#define RCC_AHB3LPENSR_RNGLPENS_Pos             (0U)
+#define RCC_AHB3LPENSR_RNGLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENSR_RNGLPENS                 RCC_AHB3LPENSR_RNGLPENS_Msk          /*!< RNG enable  */
+#define RCC_AHB3LPENSR_HASHLPENS_Pos            (1U)
+#define RCC_AHB3LPENSR_HASHLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENSR_HASHLPENS                RCC_AHB3LPENSR_HASHLPENS_Msk         /*!< HASH enable  */
+#define RCC_AHB3LPENSR_PKALPENS_Pos             (8U)
+#define RCC_AHB3LPENSR_PKALPENS_Msk             (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENSR_PKALPENS                 RCC_AHB3LPENSR_PKALPENS_Msk          /*!< PKA enable  */
+#define RCC_AHB3LPENSR_RIFSCLPENS_Pos           (9U)
+#define RCC_AHB3LPENSR_RIFSCLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENSR_RIFSCLPENS               RCC_AHB3LPENSR_RIFSCLPENS_Msk        /*!< RIFSC enable  */
+#define RCC_AHB3LPENSR_IACLPENS_Pos             (10U)
+#define RCC_AHB3LPENSR_IACLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENSR_IACLPENS                 RCC_AHB3LPENSR_IACLPENS_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENSR_RISAFLPENS_Pos           (14U)
+#define RCC_AHB3LPENSR_RISAFLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENSR_RISAFLPENS               RCC_AHB3LPENSR_RISAFLPENS_Msk        /*!< RISAF enable  */
+
+/****************  Bit definition for RCC_AHB4LPENSR register  ****************/
+#define RCC_AHB4LPENSR_GPIOALPENS_Pos           (0U)
+#define RCC_AHB4LPENSR_GPIOALPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENSR_GPIOALPENS               RCC_AHB4LPENSR_GPIOALPENS_Msk        /*!< GPIO A enable  */
+#define RCC_AHB4LPENSR_GPIOBLPENS_Pos           (1U)
+#define RCC_AHB4LPENSR_GPIOBLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENSR_GPIOBLPENS               RCC_AHB4LPENSR_GPIOBLPENS_Msk        /*!< GPIO B enable  */
+#define RCC_AHB4LPENSR_GPIOCLPENS_Pos           (2U)
+#define RCC_AHB4LPENSR_GPIOCLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENSR_GPIOCLPENS               RCC_AHB4LPENSR_GPIOCLPENS_Msk        /*!< GPIO C enable  */
+#define RCC_AHB4LPENSR_GPIODLPENS_Pos           (3U)
+#define RCC_AHB4LPENSR_GPIODLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENSR_GPIODLPENS               RCC_AHB4LPENSR_GPIODLPENS_Msk        /*!< GPIO D enable  */
+#define RCC_AHB4LPENSR_GPIOELPENS_Pos           (4U)
+#define RCC_AHB4LPENSR_GPIOELPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENSR_GPIOELPENS               RCC_AHB4LPENSR_GPIOELPENS_Msk        /*!< GPIO E enable  */
+#define RCC_AHB4LPENSR_GPIOFLPENS_Pos           (5U)
+#define RCC_AHB4LPENSR_GPIOFLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENSR_GPIOFLPENS               RCC_AHB4LPENSR_GPIOFLPENS_Msk        /*!< GPIO F enable  */
+#define RCC_AHB4LPENSR_GPIOGLPENS_Pos           (6U)
+#define RCC_AHB4LPENSR_GPIOGLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENSR_GPIOGLPENS               RCC_AHB4LPENSR_GPIOGLPENS_Msk        /*!< GPIO G enable  */
+#define RCC_AHB4LPENSR_GPIOHLPENS_Pos           (7U)
+#define RCC_AHB4LPENSR_GPIOHLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENSR_GPIOHLPENS               RCC_AHB4LPENSR_GPIOHLPENS_Msk        /*!< GPIO H enable  */
+#define RCC_AHB4LPENSR_GPIONLPENS_Pos           (13U)
+#define RCC_AHB4LPENSR_GPIONLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENSR_GPIONLPENS               RCC_AHB4LPENSR_GPIONLPENS_Msk        /*!< GPIO N enable  */
+#define RCC_AHB4LPENSR_GPIOOLPENS_Pos           (14U)
+#define RCC_AHB4LPENSR_GPIOOLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENSR_GPIOOLPENS               RCC_AHB4LPENSR_GPIOOLPENS_Msk        /*!< GPIO O enable  */
+#define RCC_AHB4LPENSR_GPIOPLPENS_Pos           (15U)
+#define RCC_AHB4LPENSR_GPIOPLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENSR_GPIOPLPENS               RCC_AHB4LPENSR_GPIOPLPENS_Msk        /*!< GPIO P enable  */
+#define RCC_AHB4LPENSR_GPIOQLPENS_Pos           (16U)
+#define RCC_AHB4LPENSR_GPIOQLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENSR_GPIOQLPENS               RCC_AHB4LPENSR_GPIOQLPENS_Msk        /*!< GPIO Q enable  */
+#define RCC_AHB4LPENSR_PWRLPENS_Pos             (18U)
+#define RCC_AHB4LPENSR_PWRLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENSR_PWRLPENS                 RCC_AHB4LPENSR_PWRLPENS_Msk          /*!< PWR enable  */
+#define RCC_AHB4LPENSR_CRCLPENS_Pos             (19U)
+#define RCC_AHB4LPENSR_CRCLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENSR_CRCLPENS                 RCC_AHB4LPENSR_CRCLPENS_Msk          /*!< CRC enable  */
+
+/****************  Bit definition for RCC_AHB5LPENSR register  ****************/
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos          (0U)
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENSR_HPDMA1LPENS              RCC_AHB5LPENSR_HPDMA1LPENS_Msk       /*!< HPDMA1 enable  */
+#define RCC_AHB5LPENSR_DMA2DLPENS_Pos           (1U)
+#define RCC_AHB5LPENSR_DMA2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENSR_DMA2DLPENS               RCC_AHB5LPENSR_DMA2DLPENS_Msk        /*!< DMA2D enable  */
+#define RCC_AHB5LPENSR_JPEGLPENS_Pos            (3U)
+#define RCC_AHB5LPENSR_JPEGLPENS_Msk            (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENSR_JPEGLPENS                RCC_AHB5LPENSR_JPEGLPENS_Msk         /*!< JPEG enable  */
+#define RCC_AHB5LPENSR_FMCLPENS_Pos             (4U)
+#define RCC_AHB5LPENSR_FMCLPENS_Msk             (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENSR_FMCLPENS                 RCC_AHB5LPENSR_FMCLPENS_Msk          /*!< FMC enable  */
+#define RCC_AHB5LPENSR_XSPI1LPENS_Pos           (5U)
+#define RCC_AHB5LPENSR_XSPI1LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENSR_XSPI1LPENS               RCC_AHB5LPENSR_XSPI1LPENS_Msk        /*!< XSPI1 enable  */
+#define RCC_AHB5LPENSR_PSSILPENS_Pos            (6U)
+#define RCC_AHB5LPENSR_PSSILPENS_Msk            (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENSR_PSSILPENS                RCC_AHB5LPENSR_PSSILPENS_Msk         /*!< PSSI enable  */
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos          (7U)
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENSR_SDMMC2LPENS              RCC_AHB5LPENSR_SDMMC2LPENS_Msk       /*!< SDMMC2 enable  */
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos          (8U)
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENSR_SDMMC1LPENS              RCC_AHB5LPENSR_SDMMC1LPENS_Msk       /*!< SDMMC1 enable  */
+#define RCC_AHB5LPENSR_XSPI2LPENS_Pos           (12U)
+#define RCC_AHB5LPENSR_XSPI2LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENSR_XSPI2LPENS               RCC_AHB5LPENSR_XSPI2LPENS_Msk        /*!< XSPI2 enable  */
+#define RCC_AHB5LPENSR_XSPIMLPENS_Pos           (13U)
+#define RCC_AHB5LPENSR_XSPIMLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENSR_XSPIMLPENS               RCC_AHB5LPENSR_XSPIMLPENS_Msk        /*!< XSPIM enable  */
+#define RCC_AHB5LPENSR_XSPI3LPENS_Pos           (17U)
+#define RCC_AHB5LPENSR_XSPI3LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENSR_XSPI3LPENS               RCC_AHB5LPENSR_XSPI3LPENS_Msk        /*!< XSPI3 enable  */
+#define RCC_AHB5LPENSR_GFXMMULPENS_Pos          (19U)
+#define RCC_AHB5LPENSR_GFXMMULPENS_Msk          (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENSR_GFXMMULPENS              RCC_AHB5LPENSR_GFXMMULPENS_Msk       /*!< GFXMMU enable  */
+#define RCC_AHB5LPENSR_GPU2DLPENS_Pos           (20U)
+#define RCC_AHB5LPENSR_GPU2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENSR_GPU2DLPENS               RCC_AHB5LPENSR_GPU2DLPENS_Msk        /*!< GPU2D enable */
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos         (22U)
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk         (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENSR_ETH1MACLPENS             RCC_AHB5LPENSR_ETH1MACLPENS_Msk      /*!< ETH1MAC enable  */
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos          (23U)
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENSR_ETH1TXLPENS              RCC_AHB5LPENSR_ETH1TXLPENS_Msk       /*!< ETH1TX enable  */
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos          (24U)
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENSR_ETH1RXLPENS              RCC_AHB5LPENSR_ETH1RXLPENS_Msk       /*!< ETH1RX enable  */
+#define RCC_AHB5LPENSR_ETH1LPENS_Pos            (25U)
+#define RCC_AHB5LPENSR_ETH1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENSR_ETH1LPENS                RCC_AHB5LPENSR_ETH1LPENS_Msk         /*!< ETH1 enable  */
+#define RCC_AHB5LPENSR_OTG1LPENS_Pos            (26U)
+#define RCC_AHB5LPENSR_OTG1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENSR_OTG1LPENS                RCC_AHB5LPENSR_OTG1LPENS_Msk         /*!< OTG1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos         (27U)
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS             RCC_AHB5LPENSR_OTGPHY1LPENS_Msk      /*!< OTGPHY1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos         (28U)
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS             RCC_AHB5LPENSR_OTGPHY2LPENS_Msk      /*!< OTGPHY2 enable  */
+#define RCC_AHB5LPENSR_OTG2LPENS_Pos            (29U)
+#define RCC_AHB5LPENSR_OTG2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENSR_OTG2LPENS                RCC_AHB5LPENSR_OTG2LPENS_Msk         /*!< OTG2 enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR1 register  ****************/
+#define RCC_APB1LPENSR1_TIM2LPENS_Pos           (0U)
+#define RCC_APB1LPENSR1_TIM2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENSR1_TIM2LPENS               RCC_APB1LPENSR1_TIM2LPENS_Msk        /*!< TIM2 enable  */
+#define RCC_APB1LPENSR1_TIM3LPENS_Pos           (1U)
+#define RCC_APB1LPENSR1_TIM3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENSR1_TIM3LPENS               RCC_APB1LPENSR1_TIM3LPENS_Msk        /*!< TIM3 enable  */
+#define RCC_APB1LPENSR1_TIM4LPENS_Pos           (2U)
+#define RCC_APB1LPENSR1_TIM4LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENSR1_TIM4LPENS               RCC_APB1LPENSR1_TIM4LPENS_Msk        /*!< TIM4 enable  */
+#define RCC_APB1LPENSR1_TIM5LPENS_Pos           (3U)
+#define RCC_APB1LPENSR1_TIM5LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENSR1_TIM5LPENS               RCC_APB1LPENSR1_TIM5LPENS_Msk        /*!< TIM5 enable  */
+#define RCC_APB1LPENSR1_TIM6LPENS_Pos           (4U)
+#define RCC_APB1LPENSR1_TIM6LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENSR1_TIM6LPENS               RCC_APB1LPENSR1_TIM6LPENS_Msk        /*!< TIM6 enable  */
+#define RCC_APB1LPENSR1_TIM7LPENS_Pos           (5U)
+#define RCC_APB1LPENSR1_TIM7LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENSR1_TIM7LPENS               RCC_APB1LPENSR1_TIM7LPENS_Msk        /*!< TIM7 enable  */
+#define RCC_APB1LPENSR1_TIM12LPENS_Pos          (6U)
+#define RCC_APB1LPENSR1_TIM12LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENSR1_TIM12LPENS              RCC_APB1LPENSR1_TIM12LPENS_Msk       /*!< TIM12 enable  */
+#define RCC_APB1LPENSR1_TIM13LPENS_Pos          (7U)
+#define RCC_APB1LPENSR1_TIM13LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENSR1_TIM13LPENS              RCC_APB1LPENSR1_TIM13LPENS_Msk       /*!< TIM13 enable  */
+#define RCC_APB1LPENSR1_TIM14LPENS_Pos          (8U)
+#define RCC_APB1LPENSR1_TIM14LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR1_TIM14LPENS              RCC_APB1LPENSR1_TIM14LPENS_Msk       /*!< TIM14 enable  */
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos         (9U)
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENSR1_LPTIM1LPENS             RCC_APB1LPENSR1_LPTIM1LPENS_Msk      /*!< LPTIM1 enable  */
+#define RCC_APB1LPENSR1_WWDGLPENS_Pos           (11U)
+#define RCC_APB1LPENSR1_WWDGLPENS_Msk           (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENSR1_WWDGLPENS               RCC_APB1LPENSR1_WWDGLPENS_Msk        /*!< WWDG enable  */
+#define RCC_APB1LPENSR1_TIM10LPENS_Pos          (12U)
+#define RCC_APB1LPENSR1_TIM10LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENSR1_TIM10LPENS              RCC_APB1LPENSR1_TIM10LPENS_Msk       /*!< TIM10 enable  */
+#define RCC_APB1LPENSR1_TIM11LPENS_Pos          (13U)
+#define RCC_APB1LPENSR1_TIM11LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENSR1_TIM11LPENS              RCC_APB1LPENSR1_TIM11LPENS_Msk       /*!< TIM11 enable  */
+#define RCC_APB1LPENSR1_SPI2LPENS_Pos           (14U)
+#define RCC_APB1LPENSR1_SPI2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENSR1_SPI2LPENS               RCC_APB1LPENSR1_SPI2LPENS_Msk        /*!< SPI2 enable  */
+#define RCC_APB1LPENSR1_SPI3LPENS_Pos           (15U)
+#define RCC_APB1LPENSR1_SPI3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENSR1_SPI3LPENS               RCC_APB1LPENSR1_SPI3LPENS_Msk        /*!< SPI3 enable  */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos       (16U)
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk       (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS           RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk    /*!< SPDIFRX1 enable  */
+#define RCC_APB1LPENSR1_USART2LPENS_Pos         (17U)
+#define RCC_APB1LPENSR1_USART2LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENSR1_USART2LPENS             RCC_APB1LPENSR1_USART2LPENS_Msk      /*!< USART2 enable  */
+#define RCC_APB1LPENSR1_USART3LPENS_Pos         (18U)
+#define RCC_APB1LPENSR1_USART3LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENSR1_USART3LPENS             RCC_APB1LPENSR1_USART3LPENS_Msk      /*!< USART3 enable  */
+#define RCC_APB1LPENSR1_UART4LPENS_Pos          (19U)
+#define RCC_APB1LPENSR1_UART4LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENSR1_UART4LPENS              RCC_APB1LPENSR1_UART4LPENS_Msk       /*!< UART4 enable  */
+#define RCC_APB1LPENSR1_UART5LPENS_Pos          (20U)
+#define RCC_APB1LPENSR1_UART5LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENSR1_UART5LPENS              RCC_APB1LPENSR1_UART5LPENS_Msk       /*!< UART5 enable  */
+#define RCC_APB1LPENSR1_I2C1LPENS_Pos           (21U)
+#define RCC_APB1LPENSR1_I2C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENSR1_I2C1LPENS               RCC_APB1LPENSR1_I2C1LPENS_Msk        /*!< I2C1 enable  */
+#define RCC_APB1LPENSR1_I2C2LPENS_Pos           (22U)
+#define RCC_APB1LPENSR1_I2C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENSR1_I2C2LPENS               RCC_APB1LPENSR1_I2C2LPENS_Msk        /*!< I2C2 enable  */
+#define RCC_APB1LPENSR1_I2C3LPENS_Pos           (23U)
+#define RCC_APB1LPENSR1_I2C3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENSR1_I2C3LPENS               RCC_APB1LPENSR1_I2C3LPENS_Msk        /*!< I2C3 enable  */
+#define RCC_APB1LPENSR1_I3C1LPENS_Pos           (24U)
+#define RCC_APB1LPENSR1_I3C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENSR1_I3C1LPENS               RCC_APB1LPENSR1_I3C1LPENS_Msk        /*!< I3C1 enable  */
+#define RCC_APB1LPENSR1_I3C2LPENS_Pos           (25U)
+#define RCC_APB1LPENSR1_I3C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENSR1_I3C2LPENS               RCC_APB1LPENSR1_I3C2LPENS_Msk        /*!< I3C2 enable  */
+#define RCC_APB1LPENSR1_UART7LPENS_Pos          (30U)
+#define RCC_APB1LPENSR1_UART7LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENSR1_UART7LPENS              RCC_APB1LPENSR1_UART7LPENS_Msk       /*!< UART7 enable  */
+#define RCC_APB1LPENSR1_UART8LPENS_Pos          (31U)
+#define RCC_APB1LPENSR1_UART8LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENSR1_UART8LPENS              RCC_APB1LPENSR1_UART8LPENS_Msk       /*!< UART8 enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR2 register  ****************/
+#define RCC_APB1LPENSR2_MDIOSLPENS_Pos          (5U)
+#define RCC_APB1LPENSR2_MDIOSLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENSR2_MDIOSLPENS              RCC_APB1LPENSR2_MDIOSLPENS_Msk       /*!< MDIOS enable  */
+#define RCC_APB1LPENSR2_FDCANLPENS_Pos          (8U)
+#define RCC_APB1LPENSR2_FDCANLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR2_FDCANLPENS              RCC_APB1LPENSR2_FDCANLPENS_Msk       /*!< FDCAN enable  */
+#define RCC_APB1LPENSR2_UCPD1LPENS_Pos          (18U)
+#define RCC_APB1LPENSR2_UCPD1LPENS_Msk          (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENSR2_UCPD1LPENS              RCC_APB1LPENSR2_UCPD1LPENS_Msk       /*!< UCPD1 enable  */
+
+/****************  Bit definition for RCC_APB2LPENSR register  ****************/
+#define RCC_APB2LPENSR_TIM1LPENS_Pos            (0U)
+#define RCC_APB2LPENSR_TIM1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENSR_TIM1LPENS                RCC_APB2LPENSR_TIM1LPENS_Msk         /*!< TIM1 enable  */
+#define RCC_APB2LPENSR_TIM8LPENS_Pos            (1U)
+#define RCC_APB2LPENSR_TIM8LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENSR_TIM8LPENS                RCC_APB2LPENSR_TIM8LPENS_Msk         /*!< TIM8 enable  */
+#define RCC_APB2LPENSR_USART1LPENS_Pos          (4U)
+#define RCC_APB2LPENSR_USART1LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENSR_USART1LPENS              RCC_APB2LPENSR_USART1LPENS_Msk       /*!< USART1 enable  */
+#define RCC_APB2LPENSR_USART6LPENS_Pos          (5U)
+#define RCC_APB2LPENSR_USART6LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENSR_USART6LPENS              RCC_APB2LPENSR_USART6LPENS_Msk       /*!< USART6 enable  */
+#define RCC_APB2LPENSR_UART9LPENS_Pos           (6U)
+#define RCC_APB2LPENSR_UART9LPENS_Msk           (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENSR_UART9LPENS               RCC_APB2LPENSR_UART9LPENS_Msk        /*!< UART9 enable  */
+#define RCC_APB2LPENSR_USART10LPENS_Pos         (7U)
+#define RCC_APB2LPENSR_USART10LPENS_Msk         (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENSR_USART10LPENS             RCC_APB2LPENSR_USART10LPENS_Msk      /*!< USART10 enable  */
+#define RCC_APB2LPENSR_SPI1LPENS_Pos            (12U)
+#define RCC_APB2LPENSR_SPI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENSR_SPI1LPENS                RCC_APB2LPENSR_SPI1LPENS_Msk         /*!< SPI1 enable  */
+#define RCC_APB2LPENSR_SPI4LPENS_Pos            (13U)
+#define RCC_APB2LPENSR_SPI4LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENSR_SPI4LPENS                RCC_APB2LPENSR_SPI4LPENS_Msk         /*!< SPI4 enable  */
+#define RCC_APB2LPENSR_TIM18LPENS_Pos           (15U)
+#define RCC_APB2LPENSR_TIM18LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENSR_TIM18LPENS               RCC_APB2LPENSR_TIM18LPENS_Msk        /*!< TIM18 enable  */
+#define RCC_APB2LPENSR_TIM15LPENS_Pos           (16U)
+#define RCC_APB2LPENSR_TIM15LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENSR_TIM15LPENS               RCC_APB2LPENSR_TIM15LPENS_Msk        /*!< TIM15 enable  */
+#define RCC_APB2LPENSR_TIM16LPENS_Pos           (17U)
+#define RCC_APB2LPENSR_TIM16LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENSR_TIM16LPENS               RCC_APB2LPENSR_TIM16LPENS_Msk        /*!< TIM16 enable  */
+#define RCC_APB2LPENSR_TIM17LPENS_Pos           (18U)
+#define RCC_APB2LPENSR_TIM17LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENSR_TIM17LPENS               RCC_APB2LPENSR_TIM17LPENS_Msk        /*!< TIM17 enable  */
+#define RCC_APB2LPENSR_TIM9LPENS_Pos            (19U)
+#define RCC_APB2LPENSR_TIM9LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENSR_TIM9LPENS                RCC_APB2LPENSR_TIM9LPENS_Msk         /*!< TIM9 enable  */
+#define RCC_APB2LPENSR_SPI5LPENS_Pos            (20U)
+#define RCC_APB2LPENSR_SPI5LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENSR_SPI5LPENS                RCC_APB2LPENSR_SPI5LPENS_Msk         /*!< SPI5 enable  */
+#define RCC_APB2LPENSR_SAI1LPENS_Pos            (21U)
+#define RCC_APB2LPENSR_SAI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENSR_SAI1LPENS                RCC_APB2LPENSR_SAI1LPENS_Msk         /*!< SAI1 enable  */
+#define RCC_APB2LPENSR_SAI2LPENS_Pos            (22U)
+#define RCC_APB2LPENSR_SAI2LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENSR_SAI2LPENS                RCC_APB2LPENSR_SAI2LPENS_Msk         /*!< SAI2 enable  */
+
+/****************  Bit definition for RCC_APB3LPENSR register  ****************/
+#define RCC_APB3LPENSR_DFTLPENS_Pos             (2U)
+#define RCC_APB3LPENSR_DFTLPENS_Msk             (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENSR_DFTLPENS                 RCC_APB3LPENSR_DFTLPENS_Msk          /*!< DFT enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR1 register  ****************/
+#define RCC_APB4LPENSR1_HDPLPENS_Pos            (2U)
+#define RCC_APB4LPENSR1_HDPLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR1_HDPLPENS                RCC_APB4LPENSR1_HDPLPENS_Msk         /*!< HDP enable  */
+#define RCC_APB4LPENSR1_LPUART1LPENS_Pos        (3U)
+#define RCC_APB4LPENSR1_LPUART1LPENS_Msk        (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENSR1_LPUART1LPENS            RCC_APB4LPENSR1_LPUART1LPENS_Msk     /*!< LPUART1 enable  */
+#define RCC_APB4LPENSR1_SPI6LPENS_Pos           (5U)
+#define RCC_APB4LPENSR1_SPI6LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENSR1_SPI6LPENS               RCC_APB4LPENSR1_SPI6LPENS_Msk        /*!< SPI6 enable  */
+#define RCC_APB4LPENSR1_I2C4LPENS_Pos           (7U)
+#define RCC_APB4LPENSR1_I2C4LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENSR1_I2C4LPENS               RCC_APB4LPENSR1_I2C4LPENS_Msk        /*!< I2C4 enable  */
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos         (9U)
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENSR1_LPTIM2LPENS             RCC_APB4LPENSR1_LPTIM2LPENS_Msk      /*!< LPTIM2 enable  */
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos         (10U)
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENSR1_LPTIM3LPENS             RCC_APB4LPENSR1_LPTIM3LPENS_Msk      /*!< LPTIM3 enable  */
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos         (11U)
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENSR1_LPTIM4LPENS             RCC_APB4LPENSR1_LPTIM4LPENS_Msk      /*!< LPTIM4 enable  */
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos         (12U)
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENSR1_LPTIM5LPENS             RCC_APB4LPENSR1_LPTIM5LPENS_Msk      /*!< LPTIM5 enable  */
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos        (15U)
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk        (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENSR1_VREFBUFLPENS            RCC_APB4LPENSR1_VREFBUFLPENS_Msk     /*!< VREFBUF enable  */
+#define RCC_APB4LPENSR1_RTCLPENS_Pos            (16U)
+#define RCC_APB4LPENSR1_RTCLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENSR1_RTCLPENS                RCC_APB4LPENSR1_RTCLPENS_Msk         /*!< RTC enable  */
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos         (17U)
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk         (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENSR1_RTCAPBLPENS             RCC_APB4LPENSR1_RTCAPBLPENS_Msk      /*!< RTCAPB enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR2 register  ****************/
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos         (0U)
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk         (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENSR2_SYSCFGLPENS             RCC_APB4LPENSR2_SYSCFGLPENS_Msk      /*!< SYSCFG enable  */
+#define RCC_APB4LPENSR2_BSECLPENS_Pos           (1U)
+#define RCC_APB4LPENSR2_BSECLPENS_Msk           (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENSR2_BSECLPENS               RCC_APB4LPENSR2_BSECLPENS_Msk        /*!< BSEC enable  */
+#define RCC_APB4LPENSR2_DTSLPENS_Pos            (2U)
+#define RCC_APB4LPENSR2_DTSLPENS_Msk            (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR2_DTSLPENS                RCC_APB4LPENSR2_DTSLPENS_Msk         /*!< DTS enable  */
+
+/****************  Bit definition for RCC_APB5LPENSR register  ****************/
+#define RCC_APB5LPENSR_LTDCLPENS_Pos            (1U)
+#define RCC_APB5LPENSR_LTDCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENSR_LTDCLPENS                RCC_APB5LPENSR_LTDCLPENS_Msk         /*!< LTDC enable */
+#define RCC_APB5LPENSR_DCMIPPLPENS_Pos          (2U)
+#define RCC_APB5LPENSR_DCMIPPLPENS_Msk          (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENSR_DCMIPPLPENS              RCC_APB5LPENSR_DCMIPPLPENS_Msk       /*!< DCMIPP enable */
+#define RCC_APB5LPENSR_GFXTIMLPENS_Pos          (4U)
+#define RCC_APB5LPENSR_GFXTIMLPENS_Msk          (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENSR_GFXTIMLPENS              RCC_APB5LPENSR_GFXTIMLPENS_Msk       /*!< GFXTIM enable */
+#define RCC_APB5LPENSR_VENCLPENS_Pos            (5U)
+#define RCC_APB5LPENSR_VENCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENSR_VENCLPENS                RCC_APB5LPENSR_VENCLPENS_Msk         /*!< VENC enable */
+#define RCC_APB5LPENSR_CSILPENS_Pos             (6U)
+#define RCC_APB5LPENSR_CSILPENS_Msk             (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENSR_CSILPENS                 RCC_APB5LPENSR_CSILPENS_Msk          /*!< CSI enable */
+
+/****************  Bit definition for RCC_PRIVCFGSR0 register  ****************/
+#define RCC_PRIVCFGSR0_LSIPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR0_LSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR0_LSIPRIVS                 RCC_PRIVCFGSR0_LSIPRIVS_Msk          /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_LSEPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR0_LSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR0_LSEPRIVS                 RCC_PRIVCFGSR0_LSEPRIVS_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_MSIPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR0_MSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR0_MSIPRIVS                 RCC_PRIVCFGSR0_MSIPRIVS_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSIPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR0_HSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR0_HSIPRIVS                 RCC_PRIVCFGSR0_HSIPRIVS_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSEPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR0_HSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR0_HSEPRIVS                 RCC_PRIVCFGSR0_HSEPRIVS_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR0 register  *****************/
+#define RCC_PUBCFGSR0_LSIPUBS_Pos               (0U)
+#define RCC_PUBCFGSR0_LSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR0_LSIPUBS                   RCC_PUBCFGSR0_LSIPUBS_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_LSEPUBS_Pos               (1U)
+#define RCC_PUBCFGSR0_LSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR0_LSEPUBS                   RCC_PUBCFGSR0_LSEPUBS_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_MSIPUBS_Pos               (2U)
+#define RCC_PUBCFGSR0_MSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR0_MSIPUBS                   RCC_PUBCFGSR0_MSIPUBS_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSIPUBS_Pos               (3U)
+#define RCC_PUBCFGSR0_HSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR0_HSIPUBS                   RCC_PUBCFGSR0_HSIPUBS_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSEPUBS_Pos               (4U)
+#define RCC_PUBCFGSR0_HSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR0_HSEPUBS                   RCC_PUBCFGSR0_HSEPUBS_Msk            /*!< Public protection of he HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR1 register  ****************/
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos            (0U)
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGSR1_PLL1PRIVS                RCC_PRIVCFGSR1_PLL1PRIVS_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos            (1U)
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGSR1_PLL2PRIVS                RCC_PRIVCFGSR1_PLL2PRIVS_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR1_PLL3PRIVS                RCC_PRIVCFGSR1_PLL3PRIVS_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR1_PLL4PRIVS                RCC_PRIVCFGSR1_PLL4PRIVS_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR1 register  *****************/
+#define RCC_PUBCFGSR1_PLL1PUBS_Pos              (0U)
+#define RCC_PUBCFGSR1_PLL1PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGSR1_PLL1PUBS                  RCC_PUBCFGSR1_PLL1PUBS_Msk           /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL2PUBS_Pos              (1U)
+#define RCC_PUBCFGSR1_PLL2PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR1_PLL2PUBS                  RCC_PUBCFGSR1_PLL2PUBS_Msk           /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL3PUBS_Pos              (2U)
+#define RCC_PUBCFGSR1_PLL3PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR1_PLL3PUBS                  RCC_PUBCFGSR1_PLL3PUBS_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL4PUBS_Pos              (3U)
+#define RCC_PUBCFGSR1_PLL4PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR1_PLL4PUBS                  RCC_PUBCFGSR1_PLL4PUBS_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR2 register  ****************/
+#define RCC_PRIVCFGSR2_IC1PRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR2_IC1PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR2_IC1PRIVS                 RCC_PRIVCFGSR2_IC1PRIVS_Msk          /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC2PRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR2_IC2PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR2_IC2PRIVS                 RCC_PRIVCFGSR2_IC2PRIVS_Msk          /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC3PRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR2_IC3PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR2_IC3PRIVS                 RCC_PRIVCFGSR2_IC3PRIVS_Msk          /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC4PRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR2_IC4PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR2_IC4PRIVS                 RCC_PRIVCFGSR2_IC4PRIVS_Msk          /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC5PRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR2_IC5PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR2_IC5PRIVS                 RCC_PRIVCFGSR2_IC5PRIVS_Msk          /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC6PRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR2_IC6PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR2_IC6PRIVS                 RCC_PRIVCFGSR2_IC6PRIVS_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC7PRIVS_Pos             (6U)
+#define RCC_PRIVCFGSR2_IC7PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGSR2_IC7PRIVS                 RCC_PRIVCFGSR2_IC7PRIVS_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC8PRIVS_Pos             (7U)
+#define RCC_PRIVCFGSR2_IC8PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGSR2_IC8PRIVS                 RCC_PRIVCFGSR2_IC8PRIVS_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC9PRIVS_Pos             (8U)
+#define RCC_PRIVCFGSR2_IC9PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGSR2_IC9PRIVS                 RCC_PRIVCFGSR2_IC9PRIVS_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC10PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR2_IC10PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR2_IC10PRIVS                RCC_PRIVCFGSR2_IC10PRIVS_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC11PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR2_IC11PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR2_IC11PRIVS                RCC_PRIVCFGSR2_IC11PRIVS_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC12PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR2_IC12PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR2_IC12PRIVS                RCC_PRIVCFGSR2_IC12PRIVS_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC13PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR2_IC13PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR2_IC13PRIVS                RCC_PRIVCFGSR2_IC13PRIVS_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC14PRIVS_Pos            (13U)
+#define RCC_PRIVCFGSR2_IC14PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGSR2_IC14PRIVS                RCC_PRIVCFGSR2_IC14PRIVS_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC15PRIVS_Pos            (14U)
+#define RCC_PRIVCFGSR2_IC15PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGSR2_IC15PRIVS                RCC_PRIVCFGSR2_IC15PRIVS_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC16PRIVS_Pos            (15U)
+#define RCC_PRIVCFGSR2_IC16PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGSR2_IC16PRIVS                RCC_PRIVCFGSR2_IC16PRIVS_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC17PRIVS_Pos            (16U)
+#define RCC_PRIVCFGSR2_IC17PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGSR2_IC17PRIVS                RCC_PRIVCFGSR2_IC17PRIVS_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC18PRIVS_Pos            (17U)
+#define RCC_PRIVCFGSR2_IC18PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGSR2_IC18PRIVS                RCC_PRIVCFGSR2_IC18PRIVS_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC19PRIVS_Pos            (18U)
+#define RCC_PRIVCFGSR2_IC19PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGSR2_IC19PRIVS                RCC_PRIVCFGSR2_IC19PRIVS_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC20PRIVS_Pos            (19U)
+#define RCC_PRIVCFGSR2_IC20PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGSR2_IC20PRIVS                RCC_PRIVCFGSR2_IC20PRIVS_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR2 register  *****************/
+#define RCC_PUBCFGSR2_IC1PUBS_Pos               (0U)
+#define RCC_PUBCFGSR2_IC1PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR2_IC1PUBS                   RCC_PUBCFGSR2_IC1PUBS_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC2PUBS_Pos               (1U)
+#define RCC_PUBCFGSR2_IC2PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR2_IC2PUBS                   RCC_PUBCFGSR2_IC2PUBS_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC3PUBS_Pos               (2U)
+#define RCC_PUBCFGSR2_IC3PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR2_IC3PUBS                   RCC_PUBCFGSR2_IC3PUBS_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC4PUBS_Pos               (3U)
+#define RCC_PUBCFGSR2_IC4PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR2_IC4PUBS                   RCC_PUBCFGSR2_IC4PUBS_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC5PUBS_Pos               (4U)
+#define RCC_PUBCFGSR2_IC5PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR2_IC5PUBS                   RCC_PUBCFGSR2_IC5PUBS_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC6PUBS_Pos               (5U)
+#define RCC_PUBCFGSR2_IC6PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR2_IC6PUBS                   RCC_PUBCFGSR2_IC6PUBS_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC7PUBS_Pos               (6U)
+#define RCC_PUBCFGSR2_IC7PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR2_IC7PUBS                   RCC_PUBCFGSR2_IC7PUBS_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC8PUBS_Pos               (7U)
+#define RCC_PUBCFGSR2_IC8PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGSR2_IC8PUBS                   RCC_PUBCFGSR2_IC8PUBS_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC9PUBS_Pos               (8U)
+#define RCC_PUBCFGSR2_IC9PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGSR2_IC9PUBS                   RCC_PUBCFGSR2_IC9PUBS_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC10PUBS_Pos              (9U)
+#define RCC_PUBCFGSR2_IC10PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR2_IC10PUBS                  RCC_PUBCFGSR2_IC10PUBS_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC11PUBS_Pos              (10U)
+#define RCC_PUBCFGSR2_IC11PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR2_IC11PUBS                  RCC_PUBCFGSR2_IC11PUBS_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC12PUBS_Pos              (11U)
+#define RCC_PUBCFGSR2_IC12PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR2_IC12PUBS                  RCC_PUBCFGSR2_IC12PUBS_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC13PUBS_Pos              (12U)
+#define RCC_PUBCFGSR2_IC13PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR2_IC13PUBS                  RCC_PUBCFGSR2_IC13PUBS_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC14PUBS_Pos              (13U)
+#define RCC_PUBCFGSR2_IC14PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGSR2_IC14PUBS                  RCC_PUBCFGSR2_IC14PUBS_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC15PUBS_Pos              (14U)
+#define RCC_PUBCFGSR2_IC15PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGSR2_IC15PUBS                  RCC_PUBCFGSR2_IC15PUBS_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC16PUBS_Pos              (15U)
+#define RCC_PUBCFGSR2_IC16PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGSR2_IC16PUBS                  RCC_PUBCFGSR2_IC16PUBS_Msk           /*!< Public protection of th IC16 configuration bits (enable, ready, divider */
+#define RCC_PUBCFGSR2_IC17PUBS_Pos              (16U)
+#define RCC_PUBCFGSR2_IC17PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGSR2_IC17PUBS                  RCC_PUBCFGSR2_IC17PUBS_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC18PUBS_Pos              (17U)
+#define RCC_PUBCFGSR2_IC18PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGSR2_IC18PUBS                  RCC_PUBCFGSR2_IC18PUBS_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC19PUBS_Pos              (18U)
+#define RCC_PUBCFGSR2_IC19PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGSR2_IC19PUBS                  RCC_PUBCFGSR2_IC19PUBS_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC20PUBS_Pos              (19U)
+#define RCC_PUBCFGSR2_IC20PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGSR2_IC20PUBS                  RCC_PUBCFGSR2_IC20PUBS_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR3 register  ****************/
+#define RCC_PRIVCFGSR3_MODPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR3_MODPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR3_MODPRIVS                 RCC_PRIVCFGSR3_MODPRIVS_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_SYSPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR3_SYSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR3_SYSPRIVS                 RCC_PRIVCFGSR3_SYSPRIVS_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_BUSPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR3_BUSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR3_BUSPRIVS                 RCC_PRIVCFGSR3_BUSPRIVS_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_PERPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR3_PERPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR3_PERPRIVS                 RCC_PRIVCFGSR3_PERPRIVS_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_INTPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR3_INTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR3_INTPRIVS                 RCC_PRIVCFGSR3_INTPRIVS_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_RSTPRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR3_RSTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR3_RSTPRIVS                 RCC_PRIVCFGSR3_RSTPRIVS_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR3 register  *****************/
+#define RCC_PUBCFGSR3_MODPUBS_Pos               (0U)
+#define RCC_PUBCFGSR3_MODPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR3_MODPUBS                   RCC_PUBCFGSR3_MODPUBS_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_SYSPUBS_Pos               (1U)
+#define RCC_PUBCFGSR3_SYSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR3_SYSPUBS                   RCC_PUBCFGSR3_SYSPUBS_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_BUSPUBS_Pos               (2U)
+#define RCC_PUBCFGSR3_BUSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR3_BUSPUBS                   RCC_PUBCFGSR3_BUSPUBS_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_PERPUBS_Pos               (3U)
+#define RCC_PUBCFGSR3_PERPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR3_PERPUBS                   RCC_PUBCFGSR3_PERPUBS_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_INTPUBS_Pos               (4U)
+#define RCC_PUBCFGSR3_INTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR3_INTPUBS                   RCC_PUBCFGSR3_INTPUBS_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_RSTPUBS_Pos               (5U)
+#define RCC_PUBCFGSR3_RSTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR3_RSTPUBS                   RCC_PUBCFGSR3_RSTPUBS_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR4 register  ****************/
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos           (0U)
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk           (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGSR4_ACLKNPRIVS               RCC_PRIVCFGSR4_ACLKNPRIVS_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos          (1U)
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk          (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS              RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk       /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR4_AHBMPRIVS                RCC_PRIVCFGSR4_AHBMPRIVS_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR4_AHB1PRIVS                RCC_PRIVCFGSR4_AHB1PRIVS_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos            (4U)
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGSR4_AHB2PRIVS                RCC_PRIVCFGSR4_AHB2PRIVS_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos            (5U)
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGSR4_AHB3PRIVS                RCC_PRIVCFGSR4_AHB3PRIVS_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos            (6U)
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGSR4_AHB4PRIVS                RCC_PRIVCFGSR4_AHB4PRIVS_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos            (7U)
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGSR4_AHB5PRIVS                RCC_PRIVCFGSR4_AHB5PRIVS_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB1PRIVS_Pos            (8U)
+#define RCC_PRIVCFGSR4_APB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGSR4_APB1PRIVS                RCC_PRIVCFGSR4_APB1PRIVS_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB2PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR4_APB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR4_APB2PRIVS                RCC_PRIVCFGSR4_APB2PRIVS_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB3PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR4_APB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR4_APB3PRIVS                RCC_PRIVCFGSR4_APB3PRIVS_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB4PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR4_APB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR4_APB4PRIVS                RCC_PRIVCFGSR4_APB4PRIVS_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB5PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR4_APB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR4_APB5PRIVS                RCC_PRIVCFGSR4_APB5PRIVS_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_NOCPRIVS_Pos             (13U)
+#define RCC_PRIVCFGSR4_NOCPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGSR4_NOCPRIVS                 RCC_PRIVCFGSR4_NOCPRIVS_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR4 register  *****************/
+#define RCC_PUBCFGSR4_ACLKNPUBS_Pos             (0U)
+#define RCC_PUBCFGSR4_ACLKNPUBS_Msk             (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGSR4_ACLKNPUBS                 RCC_PUBCFGSR4_ACLKNPUBS_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos            (1U)
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk            (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR4_ACLKNCPUBS                RCC_PUBCFGSR4_ACLKNCPUBS_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHBMPUBS_Pos              (2U)
+#define RCC_PUBCFGSR4_AHBMPUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR4_AHBMPUBS                  RCC_PUBCFGSR4_AHBMPUBS_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB1PUBS_Pos              (3U)
+#define RCC_PUBCFGSR4_AHB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR4_AHB1PUBS                  RCC_PUBCFGSR4_AHB1PUBS_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB2PUBS_Pos              (4U)
+#define RCC_PUBCFGSR4_AHB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGSR4_AHB2PUBS                  RCC_PUBCFGSR4_AHB2PUBS_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB3PUBS_Pos              (5U)
+#define RCC_PUBCFGSR4_AHB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGSR4_AHB3PUBS                  RCC_PUBCFGSR4_AHB3PUBS_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB4PUBS_Pos              (6U)
+#define RCC_PUBCFGSR4_AHB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGSR4_AHB4PUBS                  RCC_PUBCFGSR4_AHB4PUBS_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB5PUBS_Pos              (7U)
+#define RCC_PUBCFGSR4_AHB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGSR4_AHB5PUBS                  RCC_PUBCFGSR4_AHB5PUBS_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB1PUBS_Pos              (8U)
+#define RCC_PUBCFGSR4_APB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGSR4_APB1PUBS                  RCC_PUBCFGSR4_APB1PUBS_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB2PUBS_Pos              (9U)
+#define RCC_PUBCFGSR4_APB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR4_APB2PUBS                  RCC_PUBCFGSR4_APB2PUBS_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB3PUBS_Pos              (10U)
+#define RCC_PUBCFGSR4_APB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR4_APB3PUBS                  RCC_PUBCFGSR4_APB3PUBS_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB4PUBS_Pos              (11U)
+#define RCC_PUBCFGSR4_APB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR4_APB4PUBS                  RCC_PUBCFGSR4_APB4PUBS_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB5PUBS_Pos              (12U)
+#define RCC_PUBCFGSR4_APB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR4_APB5PUBS                  RCC_PUBCFGSR4_APB5PUBS_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_NOCPUBS_Pos               (13U)
+#define RCC_PUBCFGSR4_NOCPUBS_Msk               (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGSR4_NOCPUBS                   RCC_PUBCFGSR4_NOCPUBS_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR5 register  *****************/
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos          (0U)
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGSR5_AXISRAM3PUBS              RCC_PUBCFGSR5_AXISRAM3PUBS_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos          (1U)
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS              RCC_PUBCFGSR5_AXISRAM4PUBS_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos          (2U)
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS              RCC_PUBCFGSR5_AXISRAM5PUBS_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos          (3U)
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS              RCC_PUBCFGSR5_AXISRAM6PUBS_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos          (4U)
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS              RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos          (5U)
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS              RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos           (6U)
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS               RCC_PUBCFGSR5_BKPSRAMPUBS_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos          (7U)
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS              RCC_PUBCFGSR5_AXISRAM1PUBS_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos          (8U)
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS              RCC_PUBCFGSR5_AXISRAM2PUBS_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos           (9U)
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS               RCC_PUBCFGSR5_FLEXRAMPUBS_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos           (11U)
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGSR5_VENCRAMPUBS               RCC_PUBCFGSR5_VENCRAMPUBS_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+/*******************  Bit definition for RCC_CCR register  ********************/
+#define RCC_CCR_LSIONC_Pos                      (0U)
+#define RCC_CCR_LSIONC_Msk                      (0x1UL << RCC_CCR_LSIONC_Pos)         /*!< 0x00000001 */
+#define RCC_CCR_LSIONC                          RCC_CCR_LSIONC_Msk                   /*!< LSI oscillator enable */
+#define RCC_CCR_LSEONC_Pos                      (1U)
+#define RCC_CCR_LSEONC_Msk                      (0x1UL << RCC_CCR_LSEONC_Pos)         /*!< 0x00000002 */
+#define RCC_CCR_LSEONC                          RCC_CCR_LSEONC_Msk                   /*!< LSE oscillator enable */
+#define RCC_CCR_MSIONC_Pos                      (2U)
+#define RCC_CCR_MSIONC_Msk                      (0x1UL << RCC_CCR_MSIONC_Pos)         /*!< 0x00000004 */
+#define RCC_CCR_MSIONC                          RCC_CCR_MSIONC_Msk                   /*!< MSI oscillator enable */
+#define RCC_CCR_HSIONC_Pos                      (3U)
+#define RCC_CCR_HSIONC_Msk                      (0x1UL << RCC_CCR_HSIONC_Pos)         /*!< 0x00000008 */
+#define RCC_CCR_HSIONC                          RCC_CCR_HSIONC_Msk                   /*!< HSI oscillator enable */
+#define RCC_CCR_HSEONC_Pos                      (4U)
+#define RCC_CCR_HSEONC_Msk                      (0x1UL << RCC_CCR_HSEONC_Pos)         /*!< 0x00000010 */
+#define RCC_CCR_HSEONC                          RCC_CCR_HSEONC_Msk                   /*!< HSE oscillator enable */
+#define RCC_CCR_PLL1ONC_Pos                     (8U)
+#define RCC_CCR_PLL1ONC_Msk                     (0x1UL << RCC_CCR_PLL1ONC_Pos)        /*!< 0x00000100 */
+#define RCC_CCR_PLL1ONC                         RCC_CCR_PLL1ONC_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CCR_PLL2ONC_Pos                     (9U)
+#define RCC_CCR_PLL2ONC_Msk                     (0x1UL << RCC_CCR_PLL2ONC_Pos)        /*!< 0x00000200 */
+#define RCC_CCR_PLL2ONC                         RCC_CCR_PLL2ONC_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CCR_PLL3ONC_Pos                     (10U)
+#define RCC_CCR_PLL3ONC_Msk                     (0x1UL << RCC_CCR_PLL3ONC_Pos)        /*!< 0x00000400 */
+#define RCC_CCR_PLL3ONC                         RCC_CCR_PLL3ONC_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CCR_PLL4ONC_Pos                     (11U)
+#define RCC_CCR_PLL4ONC_Msk                     (0x1UL << RCC_CCR_PLL4ONC_Pos)        /*!< 0x00000800 */
+#define RCC_CCR_PLL4ONC                         RCC_CCR_PLL4ONC_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCCR register  ******************/
+#define RCC_STOPCCR_MSISTOPENC_Pos              (0U)
+#define RCC_STOPCCR_MSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */
+#define RCC_STOPCCR_MSISTOPENC                  RCC_STOPCCR_MSISTOPENC_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCCR_HSISTOPENC_Pos              (1U)
+#define RCC_STOPCCR_HSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */
+#define RCC_STOPCCR_HSISTOPENC                  RCC_STOPCCR_HSISTOPENC_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTCR register  *****************/
+#define RCC_MISCRSTCR_DBGRSTC_Pos               (0U)
+#define RCC_MISCRSTCR_DBGRSTC_Msk               (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTCR_DBGRSTC                   RCC_MISCRSTCR_DBGRSTC_Msk            /*!< DBG reset */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos          (4U)
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC              RCC_MISCRSTCR_XSPIPHY1RSTC_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos          (5U)
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC              RCC_MISCRSTCR_XSPIPHY2RSTC_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos         (7U)
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC             RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos         (8U)
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC             RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTCR register  *****************/
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos           (0U)
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTCR_AXISRAM3RSTC               RCC_MEMRSTCR_AXISRAM3RSTC_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos           (1U)
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTCR_AXISRAM4RSTC               RCC_MEMRSTCR_AXISRAM4RSTC_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos           (2U)
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTCR_AXISRAM5RSTC               RCC_MEMRSTCR_AXISRAM5RSTC_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos           (3U)
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTCR_AXISRAM6RSTC               RCC_MEMRSTCR_AXISRAM6RSTC_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos           (4U)
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC               RCC_MEMRSTCR_AHBSRAM1RSTC_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos           (5U)
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC               RCC_MEMRSTCR_AHBSRAM2RSTC_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos           (7U)
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTCR_AXISRAM1RSTC               RCC_MEMRSTCR_AXISRAM1RSTC_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos           (8U)
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTCR_AXISRAM2RSTC               RCC_MEMRSTCR_AXISRAM2RSTC_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos            (9U)
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTCR_FLEXRAMRSTC                RCC_MEMRSTCR_FLEXRAMRSTC_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTCR_VENCRAMRSTC_Pos            (11U)
+#define RCC_MEMRSTCR_VENCRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTCR_VENCRAMRSTC                RCC_MEMRSTCR_VENCRAMRSTC_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTCR_BOOTROMRSTC_Pos            (12U)
+#define RCC_MEMRSTCR_BOOTROMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTCR_BOOTROMRSTC                RCC_MEMRSTCR_BOOTROMRSTC_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTCR register  *****************/
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos            (4U)
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk            (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTCR_GPDMA1RSTC                RCC_AHB1RSTCR_GPDMA1RSTC_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTCR_ADC12RSTC_Pos             (5U)
+#define RCC_AHB1RSTCR_ADC12RSTC_Msk             (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTCR_ADC12RSTC                 RCC_AHB1RSTCR_ADC12RSTC_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTCR register  *****************/
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos            (12U)
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk            (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTCR_RAMCFGRSTC                RCC_AHB2RSTCR_RAMCFGRSTC_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTCR_MDF1RSTC_Pos              (16U)
+#define RCC_AHB2RSTCR_MDF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTCR_MDF1RSTC                  RCC_AHB2RSTCR_MDF1RSTC_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTCR_ADF1RSTC_Pos              (17U)
+#define RCC_AHB2RSTCR_ADF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTCR_ADF1RSTC                  RCC_AHB2RSTCR_ADF1RSTC_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTCR register  *****************/
+#define RCC_AHB3RSTCR_RNGRSTC_Pos               (0U)
+#define RCC_AHB3RSTCR_RNGRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTCR_RNGRSTC                   RCC_AHB3RSTCR_RNGRSTC_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTCR_HASHRSTC_Pos              (1U)
+#define RCC_AHB3RSTCR_HASHRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTCR_HASHRSTC                  RCC_AHB3RSTCR_HASHRSTC_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTCR_PKARSTC_Pos               (8U)
+#define RCC_AHB3RSTCR_PKARSTC_Msk               (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTCR_PKARSTC                   RCC_AHB3RSTCR_PKARSTC_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTCR_IACRSTC_Pos               (10U)
+#define RCC_AHB3RSTCR_IACRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTCR_IACRSTC                   RCC_AHB3RSTCR_IACRSTC_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTCR register  *****************/
+#define RCC_AHB4RSTCR_GPIOARSTC_Pos             (0U)
+#define RCC_AHB4RSTCR_GPIOARSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTCR_GPIOARSTC                 RCC_AHB4RSTCR_GPIOARSTC_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTCR_GPIOBRSTC_Pos             (1U)
+#define RCC_AHB4RSTCR_GPIOBRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTCR_GPIOBRSTC                 RCC_AHB4RSTCR_GPIOBRSTC_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTCR_GPIOCRSTC_Pos             (2U)
+#define RCC_AHB4RSTCR_GPIOCRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTCR_GPIOCRSTC                 RCC_AHB4RSTCR_GPIOCRSTC_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTCR_GPIODRSTC_Pos             (3U)
+#define RCC_AHB4RSTCR_GPIODRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTCR_GPIODRSTC                 RCC_AHB4RSTCR_GPIODRSTC_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTCR_GPIOERSTC_Pos             (4U)
+#define RCC_AHB4RSTCR_GPIOERSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTCR_GPIOERSTC                 RCC_AHB4RSTCR_GPIOERSTC_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTCR_GPIOFRSTC_Pos             (5U)
+#define RCC_AHB4RSTCR_GPIOFRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTCR_GPIOFRSTC                 RCC_AHB4RSTCR_GPIOFRSTC_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTCR_GPIOGRSTC_Pos             (6U)
+#define RCC_AHB4RSTCR_GPIOGRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTCR_GPIOGRSTC                 RCC_AHB4RSTCR_GPIOGRSTC_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTCR_GPIOHRSTC_Pos             (7U)
+#define RCC_AHB4RSTCR_GPIOHRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTCR_GPIOHRSTC                 RCC_AHB4RSTCR_GPIOHRSTC_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTCR_GPIONRSTC_Pos             (13U)
+#define RCC_AHB4RSTCR_GPIONRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTCR_GPIONRSTC                 RCC_AHB4RSTCR_GPIONRSTC_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTCR_GPIOORSTC_Pos             (14U)
+#define RCC_AHB4RSTCR_GPIOORSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTCR_GPIOORSTC                 RCC_AHB4RSTCR_GPIOORSTC_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTCR_GPIOPRSTC_Pos             (15U)
+#define RCC_AHB4RSTCR_GPIOPRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTCR_GPIOPRSTC                 RCC_AHB4RSTCR_GPIOPRSTC_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTCR_GPIOQRSTC_Pos             (16U)
+#define RCC_AHB4RSTCR_GPIOQRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTCR_GPIOQRSTC                 RCC_AHB4RSTCR_GPIOQRSTC_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTCR_PWRRSTC_Pos               (18U)
+#define RCC_AHB4RSTCR_PWRRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTCR_PWRRSTC                   RCC_AHB4RSTCR_PWRRSTC_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTCR_CRCRSTC_Pos               (19U)
+#define RCC_AHB4RSTCR_CRCRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTCR_CRCRSTC                   RCC_AHB4RSTCR_CRCRSTC_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTCR register  *****************/
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos            (0U)
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTCR_HPDMA1RSTC                RCC_AHB5RSTCR_HPDMA1RSTC_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTCR_DMA2DRSTC_Pos             (1U)
+#define RCC_AHB5RSTCR_DMA2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTCR_DMA2DRSTC                 RCC_AHB5RSTCR_DMA2DRSTC_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTCR_JPEGRSTC_Pos              (3U)
+#define RCC_AHB5RSTCR_JPEGRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTCR_JPEGRSTC                  RCC_AHB5RSTCR_JPEGRSTC_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTCR_FMCRSTC_Pos               (4U)
+#define RCC_AHB5RSTCR_FMCRSTC_Msk               (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTCR_FMCRSTC                   RCC_AHB5RSTCR_FMCRSTC_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTCR_XSPI1RSTC_Pos             (5U)
+#define RCC_AHB5RSTCR_XSPI1RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTCR_XSPI1RSTC                 RCC_AHB5RSTCR_XSPI1RSTC_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTCR_PSSIRSTC_Pos              (6U)
+#define RCC_AHB5RSTCR_PSSIRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTCR_PSSIRSTC                  RCC_AHB5RSTCR_PSSIRSTC_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos            (7U)
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTCR_SDMMC2RSTC                RCC_AHB5RSTCR_SDMMC2RSTC_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos            (8U)
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTCR_SDMMC1RSTC                RCC_AHB5RSTCR_SDMMC1RSTC_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTCR_XSPI2RSTC_Pos             (12U)
+#define RCC_AHB5RSTCR_XSPI2RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTCR_XSPI2RSTC                 RCC_AHB5RSTCR_XSPI2RSTC_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTCR_XSPIMRSTC_Pos             (13U)
+#define RCC_AHB5RSTCR_XSPIMRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTCR_XSPIMRSTC                 RCC_AHB5RSTCR_XSPIMRSTC_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTCR_XSPI3RSTC_Pos             (17U)
+#define RCC_AHB5RSTCR_XSPI3RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTCR_XSPI3RSTC                 RCC_AHB5RSTCR_XSPI3RSTC_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTCR_GFXMMURSTC_Pos            (19U)
+#define RCC_AHB5RSTCR_GFXMMURSTC_Msk            (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTCR_GFXMMURSTC                RCC_AHB5RSTCR_GFXMMURSTC_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTCR_GPU2DRSTC_Pos             (20U)
+#define RCC_AHB5RSTCR_GPU2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTCR_GPU2DRSTC                 RCC_AHB5RSTCR_GPU2DRSTC_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos        (23U)
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC            RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos        (24U)
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC            RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTCR_ETH1RSTC_Pos              (25U)
+#define RCC_AHB5RSTCR_ETH1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTCR_ETH1RSTC                  RCC_AHB5RSTCR_ETH1RSTC_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTCR_OTG1RSTC_Pos              (26U)
+#define RCC_AHB5RSTCR_OTG1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTCR_OTG1RSTC                  RCC_AHB5RSTCR_OTG1RSTC_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos           (27U)
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC               RCC_AHB5RSTCR_OTGPHY1RSTC_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos           (28U)
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC               RCC_AHB5RSTCR_OTGPHY2RSTC_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTCR_OTG2RSTC_Pos              (29U)
+#define RCC_AHB5RSTCR_OTG2RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTCR_OTG2RSTC                  RCC_AHB5RSTCR_OTG2RSTC_Msk           /*!< OTG2 reset */
+
+/****************  Bit definition for RCC_APB1RSTCR1 register  ****************/
+#define RCC_APB1RSTCR1_TIM2RSTC_Pos             (0U)
+#define RCC_APB1RSTCR1_TIM2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTCR1_TIM2RSTC                 RCC_APB1RSTCR1_TIM2RSTC_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTCR1_TIM3RSTC_Pos             (1U)
+#define RCC_APB1RSTCR1_TIM3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTCR1_TIM3RSTC                 RCC_APB1RSTCR1_TIM3RSTC_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTCR1_TIM4RSTC_Pos             (2U)
+#define RCC_APB1RSTCR1_TIM4RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTCR1_TIM4RSTC                 RCC_APB1RSTCR1_TIM4RSTC_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTCR1_TIM5RSTC_Pos             (3U)
+#define RCC_APB1RSTCR1_TIM5RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTCR1_TIM5RSTC                 RCC_APB1RSTCR1_TIM5RSTC_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTCR1_TIM6RSTC_Pos             (4U)
+#define RCC_APB1RSTCR1_TIM6RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTCR1_TIM6RSTC                 RCC_APB1RSTCR1_TIM6RSTC_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTCR1_TIM7RSTC_Pos             (5U)
+#define RCC_APB1RSTCR1_TIM7RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTCR1_TIM7RSTC                 RCC_APB1RSTCR1_TIM7RSTC_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTCR1_TIM12RSTC_Pos            (6U)
+#define RCC_APB1RSTCR1_TIM12RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTCR1_TIM12RSTC                RCC_APB1RSTCR1_TIM12RSTC_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTCR1_TIM13RSTC_Pos            (7U)
+#define RCC_APB1RSTCR1_TIM13RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTCR1_TIM13RSTC                RCC_APB1RSTCR1_TIM13RSTC_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTCR1_TIM14RSTC_Pos            (8U)
+#define RCC_APB1RSTCR1_TIM14RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR1_TIM14RSTC                RCC_APB1RSTCR1_TIM14RSTC_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos           (9U)
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTCR1_LPTIM1RSTC               RCC_APB1RSTCR1_LPTIM1RSTC_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTCR1_WWDGRSTC_Pos             (11U)
+#define RCC_APB1RSTCR1_WWDGRSTC_Msk             (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTCR1_WWDGRSTC                 RCC_APB1RSTCR1_WWDGRSTC_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTCR1_TIM10RSTC_Pos            (12U)
+#define RCC_APB1RSTCR1_TIM10RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTCR1_TIM10RSTC                RCC_APB1RSTCR1_TIM10RSTC_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTCR1_TIM11RSTC_Pos            (13U)
+#define RCC_APB1RSTCR1_TIM11RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTCR1_TIM11RSTC                RCC_APB1RSTCR1_TIM11RSTC_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTCR1_SPI2RSTC_Pos             (14U)
+#define RCC_APB1RSTCR1_SPI2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTCR1_SPI2RSTC                 RCC_APB1RSTCR1_SPI2RSTC_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTCR1_SPI3RSTC_Pos             (15U)
+#define RCC_APB1RSTCR1_SPI3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTCR1_SPI3RSTC                 RCC_APB1RSTCR1_SPI3RSTC_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos         (16U)
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk         (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC             RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTCR1_USART2RSTC_Pos           (17U)
+#define RCC_APB1RSTCR1_USART2RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTCR1_USART2RSTC               RCC_APB1RSTCR1_USART2RSTC_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTCR1_USART3RSTC_Pos           (18U)
+#define RCC_APB1RSTCR1_USART3RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTCR1_USART3RSTC               RCC_APB1RSTCR1_USART3RSTC_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTCR1_UART4RSTC_Pos            (19U)
+#define RCC_APB1RSTCR1_UART4RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTCR1_UART4RSTC                RCC_APB1RSTCR1_UART4RSTC_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTCR1_UART5RSTC_Pos            (20U)
+#define RCC_APB1RSTCR1_UART5RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTCR1_UART5RSTC                RCC_APB1RSTCR1_UART5RSTC_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTCR1_I2C1RSTC_Pos             (21U)
+#define RCC_APB1RSTCR1_I2C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTCR1_I2C1RSTC                 RCC_APB1RSTCR1_I2C1RSTC_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTCR1_I2C2RSTC_Pos             (22U)
+#define RCC_APB1RSTCR1_I2C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTCR1_I2C2RSTC                 RCC_APB1RSTCR1_I2C2RSTC_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTCR1_I2C3RSTC_Pos             (23U)
+#define RCC_APB1RSTCR1_I2C3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTCR1_I2C3RSTC                 RCC_APB1RSTCR1_I2C3RSTC_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTCR1_I3C1RSTC_Pos             (24U)
+#define RCC_APB1RSTCR1_I3C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTCR1_I3C1RSTC                 RCC_APB1RSTCR1_I3C1RSTC_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTCR1_I3C2RSTC_Pos             (25U)
+#define RCC_APB1RSTCR1_I3C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTCR1_I3C2RSTC                 RCC_APB1RSTCR1_I3C2RSTC_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTCR1_UART7RSTC_Pos            (30U)
+#define RCC_APB1RSTCR1_UART7RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTCR1_UART7RSTC                RCC_APB1RSTCR1_UART7RSTC_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTCR1_UART8RSTC_Pos            (31U)
+#define RCC_APB1RSTCR1_UART8RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTCR1_UART8RSTC                RCC_APB1RSTCR1_UART8RSTC_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTCR2 register  ****************/
+#define RCC_APB1RSTCR2_MDIOSRSTC_Pos            (5U)
+#define RCC_APB1RSTCR2_MDIOSRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTCR2_MDIOSRSTC                RCC_APB1RSTCR2_MDIOSRSTC_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTCR2_FDCANRSTC_Pos            (8U)
+#define RCC_APB1RSTCR2_FDCANRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR2_FDCANRSTC                RCC_APB1RSTCR2_FDCANRSTC_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTCR2_UCPD1RSTC_Pos            (18U)
+#define RCC_APB1RSTCR2_UCPD1RSTC_Msk            (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTCR2_UCPD1RSTC                RCC_APB1RSTCR2_UCPD1RSTC_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTCR register  *****************/
+#define RCC_APB2RSTCR_TIM1RSTC_Pos              (0U)
+#define RCC_APB2RSTCR_TIM1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTCR_TIM1RSTC                  RCC_APB2RSTCR_TIM1RSTC_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTCR_TIM8RSTC_Pos              (1U)
+#define RCC_APB2RSTCR_TIM8RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTCR_TIM8RSTC                  RCC_APB2RSTCR_TIM8RSTC_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTCR_USART1RSTC_Pos            (4U)
+#define RCC_APB2RSTCR_USART1RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTCR_USART1RSTC                RCC_APB2RSTCR_USART1RSTC_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTCR_USART6RSTC_Pos            (5U)
+#define RCC_APB2RSTCR_USART6RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTCR_USART6RSTC                RCC_APB2RSTCR_USART6RSTC_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTCR_UART9RSTC_Pos             (6U)
+#define RCC_APB2RSTCR_UART9RSTC_Msk             (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTCR_UART9RSTC                 RCC_APB2RSTCR_UART9RSTC_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTCR_USART10RSTC_Pos           (7U)
+#define RCC_APB2RSTCR_USART10RSTC_Msk           (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTCR_USART10RSTC               RCC_APB2RSTCR_USART10RSTC_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTCR_SPI1RSTC_Pos              (12U)
+#define RCC_APB2RSTCR_SPI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTCR_SPI1RSTC                  RCC_APB2RSTCR_SPI1RSTC_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTCR_SPI4RSTC_Pos              (13U)
+#define RCC_APB2RSTCR_SPI4RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTCR_SPI4RSTC                  RCC_APB2RSTCR_SPI4RSTC_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTCR_TIM18RSTC_Pos             (15U)
+#define RCC_APB2RSTCR_TIM18RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTCR_TIM18RSTC                 RCC_APB2RSTCR_TIM18RSTC_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTCR_TIM15RSTC_Pos             (16U)
+#define RCC_APB2RSTCR_TIM15RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTCR_TIM15RSTC                 RCC_APB2RSTCR_TIM15RSTC_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTCR_TIM16RSTC_Pos             (17U)
+#define RCC_APB2RSTCR_TIM16RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTCR_TIM16RSTC                 RCC_APB2RSTCR_TIM16RSTC_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTCR_TIM17RSTC_Pos             (18U)
+#define RCC_APB2RSTCR_TIM17RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTCR_TIM17RSTC                 RCC_APB2RSTCR_TIM17RSTC_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTCR_TIM9RSTC_Pos              (19U)
+#define RCC_APB2RSTCR_TIM9RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTCR_TIM9RSTC                  RCC_APB2RSTCR_TIM9RSTC_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTCR_SPI5RSTC_Pos              (20U)
+#define RCC_APB2RSTCR_SPI5RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTCR_SPI5RSTC                  RCC_APB2RSTCR_SPI5RSTC_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTCR_SAI1RSTC_Pos              (21U)
+#define RCC_APB2RSTCR_SAI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTCR_SAI1RSTC                  RCC_APB2RSTCR_SAI1RSTC_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTCR_SAI2RSTC_Pos              (22U)
+#define RCC_APB2RSTCR_SAI2RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTCR_SAI2RSTC                  RCC_APB2RSTCR_SAI2RSTC_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTCR1 register  ****************/
+#define RCC_APB4RSTCR1_HDPRSTC_Pos              (2U)
+#define RCC_APB4RSTCR1_HDPRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR1_HDPRSTC                  RCC_APB4RSTCR1_HDPRSTC_Msk           /*!< HDP reset */
+#define RCC_APB4RSTCR1_LPUART1RSTC_Pos          (3U)
+#define RCC_APB4RSTCR1_LPUART1RSTC_Msk          (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTCR1_LPUART1RSTC              RCC_APB4RSTCR1_LPUART1RSTC_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTCR1_SPI6RSTC_Pos             (5U)
+#define RCC_APB4RSTCR1_SPI6RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTCR1_SPI6RSTC                 RCC_APB4RSTCR1_SPI6RSTC_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTCR1_I2C4RSTC_Pos             (7U)
+#define RCC_APB4RSTCR1_I2C4RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTCR1_I2C4RSTC                 RCC_APB4RSTCR1_I2C4RSTC_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos           (9U)
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTCR1_LPTIM2RSTC               RCC_APB4RSTCR1_LPTIM2RSTC_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos           (10U)
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTCR1_LPTIM3RSTC               RCC_APB4RSTCR1_LPTIM3RSTC_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos           (11U)
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTCR1_LPTIM4RSTC               RCC_APB4RSTCR1_LPTIM4RSTC_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos           (12U)
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTCR1_LPTIM5RSTC               RCC_APB4RSTCR1_LPTIM5RSTC_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos          (15U)
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk          (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTCR1_VREFBUFRSTC              RCC_APB4RSTCR1_VREFBUFRSTC_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTCR1_RTCRSTC_Pos              (16U)
+#define RCC_APB4RSTCR1_RTCRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTCR1_RTCRSTC                  RCC_APB4RSTCR1_RTCRSTC_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTCR2 register  ****************/
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos           (0U)
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk           (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTCR2_SYSCFGRSTC               RCC_APB4RSTCR2_SYSCFGRSTC_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTCR2_DTSRSTC_Pos              (2U)
+#define RCC_APB4RSTCR2_DTSRSTC_Msk              (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR2_DTSRSTC                  RCC_APB4RSTCR2_DTSRSTC_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTCR register  *****************/
+#define RCC_APB5RSTCR_LTDCRSTC_Pos              (1U)
+#define RCC_APB5RSTCR_LTDCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTCR_LTDCRSTC                  RCC_APB5RSTCR_LTDCRSTC_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTCR_DCMIPPRSTC_Pos            (2U)
+#define RCC_APB5RSTCR_DCMIPPRSTC_Msk            (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTCR_DCMIPPRSTC                RCC_APB5RSTCR_DCMIPPRSTC_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTCR_GFXTIMRSTC_Pos            (4U)
+#define RCC_APB5RSTCR_GFXTIMRSTC_Msk            (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTCR_GFXTIMRSTC                RCC_APB5RSTCR_GFXTIMRSTC_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTCR_VENCRSTC_Pos              (5U)
+#define RCC_APB5RSTCR_VENCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTCR_VENCRSTC                  RCC_APB5RSTCR_VENCRSTC_Msk           /*!< VENC reset */
+#define RCC_APB5RSTCR_CSIRSTC_Pos               (6U)
+#define RCC_APB5RSTCR_CSIRSTC_Msk               (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTCR_CSIRSTC                   RCC_APB5RSTCR_CSIRSTC_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENCR register  ******************/
+#define RCC_DIVENCR_IC1ENC_Pos                  (0U)
+#define RCC_DIVENCR_IC1ENC_Msk                  (0x1UL << RCC_DIVENCR_IC1ENC_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENCR_IC1ENC                      RCC_DIVENCR_IC1ENC_Msk               /*!< IC1 enable */
+#define RCC_DIVENCR_IC2ENC_Pos                  (1U)
+#define RCC_DIVENCR_IC2ENC_Msk                  (0x1UL << RCC_DIVENCR_IC2ENC_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENCR_IC2ENC                      RCC_DIVENCR_IC2ENC_Msk               /*!< IC2 enable */
+#define RCC_DIVENCR_IC3ENC_Pos                  (2U)
+#define RCC_DIVENCR_IC3ENC_Msk                  (0x1UL << RCC_DIVENCR_IC3ENC_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENCR_IC3ENC                      RCC_DIVENCR_IC3ENC_Msk               /*!< IC3 enable */
+#define RCC_DIVENCR_IC4ENC_Pos                  (3U)
+#define RCC_DIVENCR_IC4ENC_Msk                  (0x1UL << RCC_DIVENCR_IC4ENC_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENCR_IC4ENC                      RCC_DIVENCR_IC4ENC_Msk               /*!< IC4 enable */
+#define RCC_DIVENCR_IC5ENC_Pos                  (4U)
+#define RCC_DIVENCR_IC5ENC_Msk                  (0x1UL << RCC_DIVENCR_IC5ENC_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENCR_IC5ENC                      RCC_DIVENCR_IC5ENC_Msk               /*!< IC5 enable */
+#define RCC_DIVENCR_IC6ENC_Pos                  (5U)
+#define RCC_DIVENCR_IC6ENC_Msk                  (0x1UL << RCC_DIVENCR_IC6ENC_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENCR_IC6ENC                      RCC_DIVENCR_IC6ENC_Msk               /*!< IC6 enable */
+#define RCC_DIVENCR_IC7ENC_Pos                  (6U)
+#define RCC_DIVENCR_IC7ENC_Msk                  (0x1UL << RCC_DIVENCR_IC7ENC_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENCR_IC7ENC                      RCC_DIVENCR_IC7ENC_Msk               /*!< IC7 enable */
+#define RCC_DIVENCR_IC8ENC_Pos                  (7U)
+#define RCC_DIVENCR_IC8ENC_Msk                  (0x1UL << RCC_DIVENCR_IC8ENC_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENCR_IC8ENC                      RCC_DIVENCR_IC8ENC_Msk               /*!< IC8 enable */
+#define RCC_DIVENCR_IC9ENC_Pos                  (8U)
+#define RCC_DIVENCR_IC9ENC_Msk                  (0x1UL << RCC_DIVENCR_IC9ENC_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENCR_IC9ENC                      RCC_DIVENCR_IC9ENC_Msk               /*!< IC9 enable */
+#define RCC_DIVENCR_IC10ENC_Pos                 (9U)
+#define RCC_DIVENCR_IC10ENC_Msk                 (0x1UL << RCC_DIVENCR_IC10ENC_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENCR_IC10ENC                     RCC_DIVENCR_IC10ENC_Msk              /*!< IC10 enable */
+#define RCC_DIVENCR_IC11ENC_Pos                 (10U)
+#define RCC_DIVENCR_IC11ENC_Msk                 (0x1UL << RCC_DIVENCR_IC11ENC_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENCR_IC11ENC                     RCC_DIVENCR_IC11ENC_Msk              /*!< IC11 enable */
+#define RCC_DIVENCR_IC12ENC_Pos                 (11U)
+#define RCC_DIVENCR_IC12ENC_Msk                 (0x1UL << RCC_DIVENCR_IC12ENC_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENCR_IC12ENC                     RCC_DIVENCR_IC12ENC_Msk              /*!< IC12 enable */
+#define RCC_DIVENCR_IC13ENC_Pos                 (12U)
+#define RCC_DIVENCR_IC13ENC_Msk                 (0x1UL << RCC_DIVENCR_IC13ENC_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENCR_IC13ENC                     RCC_DIVENCR_IC13ENC_Msk              /*!< IC13 enable */
+#define RCC_DIVENCR_IC14ENC_Pos                 (13U)
+#define RCC_DIVENCR_IC14ENC_Msk                 (0x1UL << RCC_DIVENCR_IC14ENC_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENCR_IC14ENC                     RCC_DIVENCR_IC14ENC_Msk              /*!< IC14 enable */
+#define RCC_DIVENCR_IC15ENC_Pos                 (14U)
+#define RCC_DIVENCR_IC15ENC_Msk                 (0x1UL << RCC_DIVENCR_IC15ENC_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENCR_IC15ENC                     RCC_DIVENCR_IC15ENC_Msk              /*!< IC15 enable */
+#define RCC_DIVENCR_IC16ENC_Pos                 (15U)
+#define RCC_DIVENCR_IC16ENC_Msk                 (0x1UL << RCC_DIVENCR_IC16ENC_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENCR_IC16ENC                     RCC_DIVENCR_IC16ENC_Msk              /*!< IC16 enable */
+#define RCC_DIVENCR_IC17ENC_Pos                 (16U)
+#define RCC_DIVENCR_IC17ENC_Msk                 (0x1UL << RCC_DIVENCR_IC17ENC_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENCR_IC17ENC                     RCC_DIVENCR_IC17ENC_Msk              /*!< IC17 enable */
+#define RCC_DIVENCR_IC18ENC_Pos                 (17U)
+#define RCC_DIVENCR_IC18ENC_Msk                 (0x1UL << RCC_DIVENCR_IC18ENC_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENCR_IC18ENC                     RCC_DIVENCR_IC18ENC_Msk              /*!< IC18 enable */
+#define RCC_DIVENCR_IC19ENC_Pos                 (18U)
+#define RCC_DIVENCR_IC19ENC_Msk                 (0x1UL << RCC_DIVENCR_IC19ENC_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENCR_IC19ENC                     RCC_DIVENCR_IC19ENC_Msk              /*!< IC19 enable */
+#define RCC_DIVENCR_IC20ENC_Pos                 (19U)
+#define RCC_DIVENCR_IC20ENC_Msk                 (0x1UL << RCC_DIVENCR_IC20ENC_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENCR_IC20ENC                     RCC_DIVENCR_IC20ENC_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENCR register  ******************/
+#define RCC_BUSENCR_ACLKNENC_Pos                (0U)
+#define RCC_BUSENCR_ACLKNENC_Msk                (0x1UL << RCC_BUSENCR_ACLKNENC_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENCR_ACLKNENC                    RCC_BUSENCR_ACLKNENC_Msk             /*!< ACLKN enable */
+#define RCC_BUSENCR_ACLKNCENC_Pos               (1U)
+#define RCC_BUSENCR_ACLKNCENC_Msk               (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENCR_ACLKNCENC                   RCC_BUSENCR_ACLKNCENC_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENCR_AHBMENC_Pos                 (2U)
+#define RCC_BUSENCR_AHBMENC_Msk                 (0x1UL << RCC_BUSENCR_AHBMENC_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENCR_AHBMENC                     RCC_BUSENCR_AHBMENC_Msk              /*!< AHBM enable */
+#define RCC_BUSENCR_AHB1ENC_Pos                 (3U)
+#define RCC_BUSENCR_AHB1ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB1ENC_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENCR_AHB1ENC                     RCC_BUSENCR_AHB1ENC_Msk              /*!< AHB1 enable */
+#define RCC_BUSENCR_AHB2ENC_Pos                 (4U)
+#define RCC_BUSENCR_AHB2ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB2ENC_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENCR_AHB2ENC                     RCC_BUSENCR_AHB2ENC_Msk              /*!< AHB2 enable */
+#define RCC_BUSENCR_AHB3ENC_Pos                 (5U)
+#define RCC_BUSENCR_AHB3ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB3ENC_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENCR_AHB3ENC                     RCC_BUSENCR_AHB3ENC_Msk              /*!< AHB3 enable */
+#define RCC_BUSENCR_AHB4ENC_Pos                 (6U)
+#define RCC_BUSENCR_AHB4ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB4ENC_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENCR_AHB4ENC                     RCC_BUSENCR_AHB4ENC_Msk              /*!< AHB4 enable */
+#define RCC_BUSENCR_AHB5ENC_Pos                 (7U)
+#define RCC_BUSENCR_AHB5ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB5ENC_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENCR_AHB5ENC                     RCC_BUSENCR_AHB5ENC_Msk              /*!< AHB5 enable */
+#define RCC_BUSENCR_APB1ENC_Pos                 (8U)
+#define RCC_BUSENCR_APB1ENC_Msk                 (0x1UL << RCC_BUSENCR_APB1ENC_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENCR_APB1ENC                     RCC_BUSENCR_APB1ENC_Msk              /*!< APB1 enable */
+#define RCC_BUSENCR_APB2ENC_Pos                 (9U)
+#define RCC_BUSENCR_APB2ENC_Msk                 (0x1UL << RCC_BUSENCR_APB2ENC_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENCR_APB2ENC                     RCC_BUSENCR_APB2ENC_Msk              /*!< APB2 enable */
+#define RCC_BUSENCR_APB3ENC_Pos                 (10U)
+#define RCC_BUSENCR_APB3ENC_Msk                 (0x1UL << RCC_BUSENCR_APB3ENC_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENCR_APB3ENC                     RCC_BUSENCR_APB3ENC_Msk              /*!< APB3 enable */
+#define RCC_BUSENCR_APB4ENC_Pos                 (11U)
+#define RCC_BUSENCR_APB4ENC_Msk                 (0x1UL << RCC_BUSENCR_APB4ENC_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENCR_APB4ENC                     RCC_BUSENCR_APB4ENC_Msk              /*!< APB4 enable */
+#define RCC_BUSENCR_APB5ENC_Pos                 (12U)
+#define RCC_BUSENCR_APB5ENC_Msk                 (0x1UL << RCC_BUSENCR_APB5ENC_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENCR_APB5ENC                     RCC_BUSENCR_APB5ENC_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENCR register  *****************/
+#define RCC_MISCENCR_DBGENC_Pos                 (0U)
+#define RCC_MISCENCR_DBGENC_Msk                 (0x1UL << RCC_MISCENCR_DBGENC_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENCR_DBGENC                     RCC_MISCENCR_DBGENC_Msk              /*!< DBG enable */
+#define RCC_MISCENCR_MCO1ENC_Pos                (1U)
+#define RCC_MISCENCR_MCO1ENC_Msk                (0x1UL << RCC_MISCENCR_MCO1ENC_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENCR_MCO1ENC                    RCC_MISCENCR_MCO1ENC_Msk             /*!< MCO1 enable */
+#define RCC_MISCENCR_MCO2ENC_Pos                (2U)
+#define RCC_MISCENCR_MCO2ENC_Msk                (0x1UL << RCC_MISCENCR_MCO2ENC_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENCR_MCO2ENC                    RCC_MISCENCR_MCO2ENC_Msk             /*!< MCO2 enable */
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos         (3U)
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk         (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENCR_XSPIPHYCOMPENC             RCC_MISCENCR_XSPIPHYCOMPENC_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENCR_PERENC_Pos                 (6U)
+#define RCC_MISCENCR_PERENC_Msk                 (0x1UL << RCC_MISCENCR_PERENC_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENCR_PERENC                     RCC_MISCENCR_PERENC_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENCR register  ******************/
+#define RCC_MEMENCR_AXISRAM3ENC_Pos             (0U)
+#define RCC_MEMENCR_AXISRAM3ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */
+#define RCC_MEMENCR_AXISRAM3ENC                 RCC_MEMENCR_AXISRAM3ENC_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENCR_AXISRAM4ENC_Pos             (1U)
+#define RCC_MEMENCR_AXISRAM4ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */
+#define RCC_MEMENCR_AXISRAM4ENC                 RCC_MEMENCR_AXISRAM4ENC_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENCR_AXISRAM5ENC_Pos             (2U)
+#define RCC_MEMENCR_AXISRAM5ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */
+#define RCC_MEMENCR_AXISRAM5ENC                 RCC_MEMENCR_AXISRAM5ENC_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENCR_AXISRAM6ENC_Pos             (3U)
+#define RCC_MEMENCR_AXISRAM6ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */
+#define RCC_MEMENCR_AXISRAM6ENC                 RCC_MEMENCR_AXISRAM6ENC_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENCR_AHBSRAM1ENC_Pos             (4U)
+#define RCC_MEMENCR_AHBSRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */
+#define RCC_MEMENCR_AHBSRAM1ENC                 RCC_MEMENCR_AHBSRAM1ENC_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENCR_AHBSRAM2ENC_Pos             (5U)
+#define RCC_MEMENCR_AHBSRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */
+#define RCC_MEMENCR_AHBSRAM2ENC                 RCC_MEMENCR_AHBSRAM2ENC_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENCR_BKPSRAMENC_Pos              (6U)
+#define RCC_MEMENCR_BKPSRAMENC_Msk              (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */
+#define RCC_MEMENCR_BKPSRAMENC                  RCC_MEMENCR_BKPSRAMENC_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENCR_AXISRAM1ENC_Pos             (7U)
+#define RCC_MEMENCR_AXISRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */
+#define RCC_MEMENCR_AXISRAM1ENC                 RCC_MEMENCR_AXISRAM1ENC_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENCR_AXISRAM2ENC_Pos             (8U)
+#define RCC_MEMENCR_AXISRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */
+#define RCC_MEMENCR_AXISRAM2ENC                 RCC_MEMENCR_AXISRAM2ENC_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENCR_FLEXRAMENC_Pos              (9U)
+#define RCC_MEMENCR_FLEXRAMENC_Msk              (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */
+#define RCC_MEMENCR_FLEXRAMENC                  RCC_MEMENCR_FLEXRAMENC_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENCR_VENCRAMENC_Pos              (11U)
+#define RCC_MEMENCR_VENCRAMENC_Msk              (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */
+#define RCC_MEMENCR_VENCRAMENC                  RCC_MEMENCR_VENCRAMENC_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENCR_BOOTROMENC_Pos              (12U)
+#define RCC_MEMENCR_BOOTROMENC_Msk              (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */
+#define RCC_MEMENCR_BOOTROMENC                  RCC_MEMENCR_BOOTROMENC_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENCR register  *****************/
+#define RCC_AHB1ENCR_GPDMA1ENC_Pos              (4U)
+#define RCC_AHB1ENCR_GPDMA1ENC_Msk              (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENCR_GPDMA1ENC                  RCC_AHB1ENCR_GPDMA1ENC_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENCR_ADC12ENC_Pos               (5U)
+#define RCC_AHB1ENCR_ADC12ENC_Msk               (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENCR_ADC12ENC                   RCC_AHB1ENCR_ADC12ENC_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENCR register  *****************/
+#define RCC_AHB2ENCR_RAMCFGENC_Pos              (12U)
+#define RCC_AHB2ENCR_RAMCFGENC_Msk              (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENCR_RAMCFGENC                  RCC_AHB2ENCR_RAMCFGENC_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENCR_MDF1ENC_Pos                (16U)
+#define RCC_AHB2ENCR_MDF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENCR_MDF1ENC                    RCC_AHB2ENCR_MDF1ENC_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENCR_ADF1ENC_Pos                (17U)
+#define RCC_AHB2ENCR_ADF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENCR_ADF1ENC                    RCC_AHB2ENCR_ADF1ENC_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENCR register  *****************/
+#define RCC_AHB3ENCR_RNGENC_Pos                 (0U)
+#define RCC_AHB3ENCR_RNGENC_Msk                 (0x1UL << RCC_AHB3ENCR_RNGENC_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENCR_RNGENC                     RCC_AHB3ENCR_RNGENC_Msk              /*!< RNG enable */
+#define RCC_AHB3ENCR_HASHENC_Pos                (1U)
+#define RCC_AHB3ENCR_HASHENC_Msk                (0x1UL << RCC_AHB3ENCR_HASHENC_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENCR_HASHENC                    RCC_AHB3ENCR_HASHENC_Msk             /*!< HASH enable */
+#define RCC_AHB3ENCR_PKAENC_Pos                 (8U)
+#define RCC_AHB3ENCR_PKAENC_Msk                 (0x1UL << RCC_AHB3ENCR_PKAENC_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENCR_PKAENC                     RCC_AHB3ENCR_PKAENC_Msk              /*!< PKA enable */
+#define RCC_AHB3ENCR_RIFSCENC_Pos               (9U)
+#define RCC_AHB3ENCR_RIFSCENC_Msk               (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENCR_RIFSCENC                   RCC_AHB3ENCR_RIFSCENC_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENCR_IACENC_Pos                 (10U)
+#define RCC_AHB3ENCR_IACENC_Msk                 (0x1UL << RCC_AHB3ENCR_IACENC_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENCR_IACENC                     RCC_AHB3ENCR_IACENC_Msk              /*!< IAC enable */
+#define RCC_AHB3ENCR_RISAFENC_Pos               (14U)
+#define RCC_AHB3ENCR_RISAFENC_Msk               (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENCR_RISAFENC                   RCC_AHB3ENCR_RISAFENC_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENCR register  *****************/
+#define RCC_AHB4ENCR_GPIOAENC_Pos               (0U)
+#define RCC_AHB4ENCR_GPIOAENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENCR_GPIOAENC                   RCC_AHB4ENCR_GPIOAENC_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENCR_GPIOBENC_Pos               (1U)
+#define RCC_AHB4ENCR_GPIOBENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENCR_GPIOBENC                   RCC_AHB4ENCR_GPIOBENC_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENCR_GPIOCENC_Pos               (2U)
+#define RCC_AHB4ENCR_GPIOCENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENCR_GPIOCENC                   RCC_AHB4ENCR_GPIOCENC_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENCR_GPIODENC_Pos               (3U)
+#define RCC_AHB4ENCR_GPIODENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENCR_GPIODENC                   RCC_AHB4ENCR_GPIODENC_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENCR_GPIOEENC_Pos               (4U)
+#define RCC_AHB4ENCR_GPIOEENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENCR_GPIOEENC                   RCC_AHB4ENCR_GPIOEENC_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENCR_GPIOFENC_Pos               (5U)
+#define RCC_AHB4ENCR_GPIOFENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENCR_GPIOFENC                   RCC_AHB4ENCR_GPIOFENC_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENCR_GPIOGENC_Pos               (6U)
+#define RCC_AHB4ENCR_GPIOGENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENCR_GPIOGENC                   RCC_AHB4ENCR_GPIOGENC_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENCR_GPIOHENC_Pos               (7U)
+#define RCC_AHB4ENCR_GPIOHENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENCR_GPIOHENC                   RCC_AHB4ENCR_GPIOHENC_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENCR_GPIONENC_Pos               (13U)
+#define RCC_AHB4ENCR_GPIONENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENCR_GPIONENC                   RCC_AHB4ENCR_GPIONENC_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENCR_GPIOOENC_Pos               (14U)
+#define RCC_AHB4ENCR_GPIOOENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENCR_GPIOOENC                   RCC_AHB4ENCR_GPIOOENC_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENCR_GPIOPENC_Pos               (15U)
+#define RCC_AHB4ENCR_GPIOPENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENCR_GPIOPENC                   RCC_AHB4ENCR_GPIOPENC_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENCR_GPIOQENC_Pos               (16U)
+#define RCC_AHB4ENCR_GPIOQENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENCR_GPIOQENC                   RCC_AHB4ENCR_GPIOQENC_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENCR_PWRENC_Pos                 (18U)
+#define RCC_AHB4ENCR_PWRENC_Msk                 (0x1UL << RCC_AHB4ENCR_PWRENC_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENCR_PWRENC                     RCC_AHB4ENCR_PWRENC_Msk              /*!< PWR enable */
+#define RCC_AHB4ENCR_CRCENC_Pos                 (19U)
+#define RCC_AHB4ENCR_CRCENC_Msk                 (0x1UL << RCC_AHB4ENCR_CRCENC_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENCR_CRCENC                     RCC_AHB4ENCR_CRCENC_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENCR register  *****************/
+#define RCC_AHB5ENCR_HPDMA1ENC_Pos              (0U)
+#define RCC_AHB5ENCR_HPDMA1ENC_Msk              (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENCR_HPDMA1ENC                  RCC_AHB5ENCR_HPDMA1ENC_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENCR_DMA2DENC_Pos               (1U)
+#define RCC_AHB5ENCR_DMA2DENC_Msk               (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENCR_DMA2DENC                   RCC_AHB5ENCR_DMA2DENC_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENCR_JPEGENC_Pos                (3U)
+#define RCC_AHB5ENCR_JPEGENC_Msk                (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENCR_JPEGENC                    RCC_AHB5ENCR_JPEGENC_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENCR_FMCENC_Pos                 (4U)
+#define RCC_AHB5ENCR_FMCENC_Msk                 (0x1UL << RCC_AHB5ENCR_FMCENC_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENCR_FMCENC                     RCC_AHB5ENCR_FMCENC_Msk              /*!< FMC enable */
+#define RCC_AHB5ENCR_XSPI1ENC_Pos               (5U)
+#define RCC_AHB5ENCR_XSPI1ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENCR_XSPI1ENC                   RCC_AHB5ENCR_XSPI1ENC_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENCR_PSSIENC_Pos                (6U)
+#define RCC_AHB5ENCR_PSSIENC_Msk                (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENCR_PSSIENC                    RCC_AHB5ENCR_PSSIENC_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENCR_SDMMC2ENC_Pos              (7U)
+#define RCC_AHB5ENCR_SDMMC2ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENCR_SDMMC2ENC                  RCC_AHB5ENCR_SDMMC2ENC_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENCR_SDMMC1ENC_Pos              (8U)
+#define RCC_AHB5ENCR_SDMMC1ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENCR_SDMMC1ENC                  RCC_AHB5ENCR_SDMMC1ENC_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENCR_XSPI2ENC_Pos               (12U)
+#define RCC_AHB5ENCR_XSPI2ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENCR_XSPI2ENC                   RCC_AHB5ENCR_XSPI2ENC_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENCR_XSPIMENC_Pos               (13U)
+#define RCC_AHB5ENCR_XSPIMENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENCR_XSPIMENC                   RCC_AHB5ENCR_XSPIMENC_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENCR_XSPI3ENC_Pos               (17U)
+#define RCC_AHB5ENCR_XSPI3ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENCR_XSPI3ENC                   RCC_AHB5ENCR_XSPI3ENC_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENCR_GFXMMUENC_Pos              (19U)
+#define RCC_AHB5ENCR_GFXMMUENC_Msk              (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENCR_GFXMMUENC                  RCC_AHB5ENCR_GFXMMUENC_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENCR_GPU2DENC_Pos               (20U)
+#define RCC_AHB5ENCR_GPU2DENC_Msk               (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENCR_GPU2DENC                   RCC_AHB5ENCR_GPU2DENC_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENCR_ETH1MACENC_Pos             (22U)
+#define RCC_AHB5ENCR_ETH1MACENC_Msk             (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENCR_ETH1MACENC                 RCC_AHB5ENCR_ETH1MACENC_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENCR_ETH1TXENC_Pos              (23U)
+#define RCC_AHB5ENCR_ETH1TXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENCR_ETH1TXENC                  RCC_AHB5ENCR_ETH1TXENC_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENCR_ETH1RXENC_Pos              (24U)
+#define RCC_AHB5ENCR_ETH1RXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENCR_ETH1RXENC                  RCC_AHB5ENCR_ETH1RXENC_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENCR_ETH1ENC_Pos                (25U)
+#define RCC_AHB5ENCR_ETH1ENC_Msk                (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENCR_ETH1ENC                    RCC_AHB5ENCR_ETH1ENC_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENCR_OTG1ENC_Pos                (26U)
+#define RCC_AHB5ENCR_OTG1ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENCR_OTG1ENC                    RCC_AHB5ENCR_OTG1ENC_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENCR_OTGPHY1ENC_Pos             (27U)
+#define RCC_AHB5ENCR_OTGPHY1ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENCR_OTGPHY1ENC                 RCC_AHB5ENCR_OTGPHY1ENC_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENCR_OTGPHY2ENC_Pos             (28U)
+#define RCC_AHB5ENCR_OTGPHY2ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENCR_OTGPHY2ENC                 RCC_AHB5ENCR_OTGPHY2ENC_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENCR_OTG2ENC_Pos                (29U)
+#define RCC_AHB5ENCR_OTG2ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENCR_OTG2ENC                    RCC_AHB5ENCR_OTG2ENC_Msk             /*!< OTG2 enable */
+
+/****************  Bit definition for RCC_APB1ENCR1 register  *****************/
+#define RCC_APB1ENCR1_TIM2ENC_Pos               (0U)
+#define RCC_APB1ENCR1_TIM2ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENCR1_TIM2ENC                   RCC_APB1ENCR1_TIM2ENC_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENCR1_TIM3ENC_Pos               (1U)
+#define RCC_APB1ENCR1_TIM3ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENCR1_TIM3ENC                   RCC_APB1ENCR1_TIM3ENC_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENCR1_TIM4ENC_Pos               (2U)
+#define RCC_APB1ENCR1_TIM4ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENCR1_TIM4ENC                   RCC_APB1ENCR1_TIM4ENC_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENCR1_TIM5ENC_Pos               (3U)
+#define RCC_APB1ENCR1_TIM5ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENCR1_TIM5ENC                   RCC_APB1ENCR1_TIM5ENC_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENCR1_TIM6ENC_Pos               (4U)
+#define RCC_APB1ENCR1_TIM6ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENCR1_TIM6ENC                   RCC_APB1ENCR1_TIM6ENC_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENCR1_TIM7ENC_Pos               (5U)
+#define RCC_APB1ENCR1_TIM7ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENCR1_TIM7ENC                   RCC_APB1ENCR1_TIM7ENC_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENCR1_TIM12ENC_Pos              (6U)
+#define RCC_APB1ENCR1_TIM12ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENCR1_TIM12ENC                  RCC_APB1ENCR1_TIM12ENC_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENCR1_TIM13ENC_Pos              (7U)
+#define RCC_APB1ENCR1_TIM13ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENCR1_TIM13ENC                  RCC_APB1ENCR1_TIM13ENC_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENCR1_TIM14ENC_Pos              (8U)
+#define RCC_APB1ENCR1_TIM14ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR1_TIM14ENC                  RCC_APB1ENCR1_TIM14ENC_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENCR1_LPTIM1ENC_Pos             (9U)
+#define RCC_APB1ENCR1_LPTIM1ENC_Msk             (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENCR1_LPTIM1ENC                 RCC_APB1ENCR1_LPTIM1ENC_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENCR1_TIM10ENC_Pos              (12U)
+#define RCC_APB1ENCR1_TIM10ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENCR1_TIM10ENC                  RCC_APB1ENCR1_TIM10ENC_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENCR1_TIM11ENC_Pos              (13U)
+#define RCC_APB1ENCR1_TIM11ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENCR1_TIM11ENC                  RCC_APB1ENCR1_TIM11ENC_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENCR1_SPI2ENC_Pos               (14U)
+#define RCC_APB1ENCR1_SPI2ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENCR1_SPI2ENC                   RCC_APB1ENCR1_SPI2ENC_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENCR1_SPI3ENC_Pos               (15U)
+#define RCC_APB1ENCR1_SPI3ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENCR1_SPI3ENC                   RCC_APB1ENCR1_SPI3ENC_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos           (16U)
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk           (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENCR1_SPDIFRX1ENC               RCC_APB1ENCR1_SPDIFRX1ENC_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENCR1_USART2ENC_Pos             (17U)
+#define RCC_APB1ENCR1_USART2ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENCR1_USART2ENC                 RCC_APB1ENCR1_USART2ENC_Msk          /*!< USART2 enable */
+#define RCC_APB1ENCR1_USART3ENC_Pos             (18U)
+#define RCC_APB1ENCR1_USART3ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENCR1_USART3ENC                 RCC_APB1ENCR1_USART3ENC_Msk          /*!< USART3 enable */
+#define RCC_APB1ENCR1_UART4ENC_Pos              (19U)
+#define RCC_APB1ENCR1_UART4ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENCR1_UART4ENC                  RCC_APB1ENCR1_UART4ENC_Msk           /*!< UART4 enable */
+#define RCC_APB1ENCR1_UART5ENC_Pos              (20U)
+#define RCC_APB1ENCR1_UART5ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENCR1_UART5ENC                  RCC_APB1ENCR1_UART5ENC_Msk           /*!< UART5 enable */
+#define RCC_APB1ENCR1_I2C1ENC_Pos               (21U)
+#define RCC_APB1ENCR1_I2C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENCR1_I2C1ENC                   RCC_APB1ENCR1_I2C1ENC_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENCR1_I2C2ENC_Pos               (22U)
+#define RCC_APB1ENCR1_I2C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENCR1_I2C2ENC                   RCC_APB1ENCR1_I2C2ENC_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENCR1_I2C3ENC_Pos               (23U)
+#define RCC_APB1ENCR1_I2C3ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENCR1_I2C3ENC                   RCC_APB1ENCR1_I2C3ENC_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENCR1_I3C1ENC_Pos               (24U)
+#define RCC_APB1ENCR1_I3C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENCR1_I3C1ENC                   RCC_APB1ENCR1_I3C1ENC_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENCR1_I3C2ENC_Pos               (25U)
+#define RCC_APB1ENCR1_I3C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENCR1_I3C2ENC                   RCC_APB1ENCR1_I3C2ENC_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENCR1_UART7ENC_Pos              (30U)
+#define RCC_APB1ENCR1_UART7ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENCR1_UART7ENC                  RCC_APB1ENCR1_UART7ENC_Msk           /*!< UART7 enable */
+#define RCC_APB1ENCR1_UART8ENC_Pos              (31U)
+#define RCC_APB1ENCR1_UART8ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENCR1_UART8ENC                  RCC_APB1ENCR1_UART8ENC_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENCR2 register  *****************/
+#define RCC_APB1ENCR2_MDIOSENC_Pos              (5U)
+#define RCC_APB1ENCR2_MDIOSENC_Msk              (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENCR2_MDIOSENC                  RCC_APB1ENCR2_MDIOSENC_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENCR2_FDCANENC_Pos              (8U)
+#define RCC_APB1ENCR2_FDCANENC_Msk              (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR2_FDCANENC                  RCC_APB1ENCR2_FDCANENC_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENCR2_UCPD1ENC_Pos              (18U)
+#define RCC_APB1ENCR2_UCPD1ENC_Msk              (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENCR2_UCPD1ENC                  RCC_APB1ENCR2_UCPD1ENC_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENCR register  *****************/
+#define RCC_APB2ENCR_TIM1ENC_Pos                (0U)
+#define RCC_APB2ENCR_TIM1ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENCR_TIM1ENC                    RCC_APB2ENCR_TIM1ENC_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENCR_TIM8ENC_Pos                (1U)
+#define RCC_APB2ENCR_TIM8ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENCR_TIM8ENC                    RCC_APB2ENCR_TIM8ENC_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENCR_USART1ENC_Pos              (4U)
+#define RCC_APB2ENCR_USART1ENC_Msk              (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENCR_USART1ENC                  RCC_APB2ENCR_USART1ENC_Msk           /*!< USART1 enable */
+#define RCC_APB2ENCR_USART6ENC_Pos              (5U)
+#define RCC_APB2ENCR_USART6ENC_Msk              (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENCR_USART6ENC                  RCC_APB2ENCR_USART6ENC_Msk           /*!< USART6 enable */
+#define RCC_APB2ENCR_UART9ENC_Pos               (6U)
+#define RCC_APB2ENCR_UART9ENC_Msk               (0x1UL << RCC_APB2ENCR_UART9ENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENCR_UART9ENC                   RCC_APB2ENCR_UART9ENC_Msk            /*!< UART9 enable */
+#define RCC_APB2ENCR_USART10ENC_Pos             (7U)
+#define RCC_APB2ENCR_USART10ENC_Msk             (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENCR_USART10ENC                 RCC_APB2ENCR_USART10ENC_Msk          /*!< USART10 enable */
+#define RCC_APB2ENCR_SPI1ENC_Pos                (12U)
+#define RCC_APB2ENCR_SPI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENCR_SPI1ENC                    RCC_APB2ENCR_SPI1ENC_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENCR_SPI4ENC_Pos                (13U)
+#define RCC_APB2ENCR_SPI4ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENCR_SPI4ENC                    RCC_APB2ENCR_SPI4ENC_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENCR_TIM18ENC_Pos               (15U)
+#define RCC_APB2ENCR_TIM18ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENCR_TIM18ENC                   RCC_APB2ENCR_TIM18ENC_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENCR_TIM15ENC_Pos               (16U)
+#define RCC_APB2ENCR_TIM15ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENCR_TIM15ENC                   RCC_APB2ENCR_TIM15ENC_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENCR_TIM16ENC_Pos               (17U)
+#define RCC_APB2ENCR_TIM16ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENCR_TIM16ENC                   RCC_APB2ENCR_TIM16ENC_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENCR_TIM17ENC_Pos               (18U)
+#define RCC_APB2ENCR_TIM17ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENCR_TIM17ENC                   RCC_APB2ENCR_TIM17ENC_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENCR_TIM9ENC_Pos                (19U)
+#define RCC_APB2ENCR_TIM9ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENCR_TIM9ENC                    RCC_APB2ENCR_TIM9ENC_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENCR_SPI5ENC_Pos                (20U)
+#define RCC_APB2ENCR_SPI5ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENCR_SPI5ENC                    RCC_APB2ENCR_SPI5ENC_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENCR_SAI1ENC_Pos                (21U)
+#define RCC_APB2ENCR_SAI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENCR_SAI1ENC                    RCC_APB2ENCR_SAI1ENC_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENCR_SAI2ENC_Pos                (22U)
+#define RCC_APB2ENCR_SAI2ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENCR_SAI2ENC                    RCC_APB2ENCR_SAI2ENC_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENCR register  *****************/
+#define RCC_APB3ENCR_DFTENC_Pos                 (2U)
+#define RCC_APB3ENCR_DFTENC_Msk                 (0x1UL << RCC_APB3ENCR_DFTENC_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENCR_DFTENC                     RCC_APB3ENCR_DFTENC_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENCR1 register  *****************/
+#define RCC_APB4ENCR1_HDPENC_Pos                (2U)
+#define RCC_APB4ENCR1_HDPENC_Msk                (0x1UL << RCC_APB4ENCR1_HDPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR1_HDPENC                    RCC_APB4ENCR1_HDPENC_Msk             /*!< HDP enable */
+#define RCC_APB4ENCR1_LPUART1ENC_Pos            (3U)
+#define RCC_APB4ENCR1_LPUART1ENC_Msk            (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENCR1_LPUART1ENC                RCC_APB4ENCR1_LPUART1ENC_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENCR1_SPI6ENC_Pos               (5U)
+#define RCC_APB4ENCR1_SPI6ENC_Msk               (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENCR1_SPI6ENC                   RCC_APB4ENCR1_SPI6ENC_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENCR1_I2C4ENC_Pos               (7U)
+#define RCC_APB4ENCR1_I2C4ENC_Msk               (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENCR1_I2C4ENC                   RCC_APB4ENCR1_I2C4ENC_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENCR1_LPTIM2ENC_Pos             (9U)
+#define RCC_APB4ENCR1_LPTIM2ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENCR1_LPTIM2ENC                 RCC_APB4ENCR1_LPTIM2ENC_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENCR1_LPTIM3ENC_Pos             (10U)
+#define RCC_APB4ENCR1_LPTIM3ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENCR1_LPTIM3ENC                 RCC_APB4ENCR1_LPTIM3ENC_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENCR1_LPTIM4ENC_Pos             (11U)
+#define RCC_APB4ENCR1_LPTIM4ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENCR1_LPTIM4ENC                 RCC_APB4ENCR1_LPTIM4ENC_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENCR1_LPTIM5ENC_Pos             (12U)
+#define RCC_APB4ENCR1_LPTIM5ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENCR1_LPTIM5ENC                 RCC_APB4ENCR1_LPTIM5ENC_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENCR1_VREFBUFENC_Pos            (15U)
+#define RCC_APB4ENCR1_VREFBUFENC_Msk            (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENCR1_VREFBUFENC                RCC_APB4ENCR1_VREFBUFENC_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENCR1_RTCENC_Pos                (16U)
+#define RCC_APB4ENCR1_RTCENC_Msk                (0x1UL << RCC_APB4ENCR1_RTCENC_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENCR1_RTCENC                    RCC_APB4ENCR1_RTCENC_Msk             /*!< RTC enable */
+#define RCC_APB4ENCR1_RTCAPBENC_Pos             (17U)
+#define RCC_APB4ENCR1_RTCAPBENC_Msk             (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENCR1_RTCAPBENC                 RCC_APB4ENCR1_RTCAPBENC_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENCR2 register  *****************/
+#define RCC_APB4ENCR2_SYSCFGENC_Pos             (0U)
+#define RCC_APB4ENCR2_SYSCFGENC_Msk             (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENCR2_SYSCFGENC                 RCC_APB4ENCR2_SYSCFGENC_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENCR2_BSECENC_Pos               (1U)
+#define RCC_APB4ENCR2_BSECENC_Msk               (0x1UL << RCC_APB4ENCR2_BSECENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENCR2_BSECENC                   RCC_APB4ENCR2_BSECENC_Msk            /*!< BSEC enable */
+#define RCC_APB4ENCR2_DTSENC_Pos                (2U)
+#define RCC_APB4ENCR2_DTSENC_Msk                (0x1UL << RCC_APB4ENCR2_DTSENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR2_DTSENC                    RCC_APB4ENCR2_DTSENC_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENCR register  *****************/
+#define RCC_APB5ENCR_LTDCENC_Pos                (1U)
+#define RCC_APB5ENCR_LTDCENC_Msk                (0x1UL << RCC_APB5ENCR_LTDCENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENCR_LTDCENC                    RCC_APB5ENCR_LTDCENC_Msk             /*!< LTDC enable */
+#define RCC_APB5ENCR_DCMIPPENC_Pos              (2U)
+#define RCC_APB5ENCR_DCMIPPENC_Msk              (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENCR_DCMIPPENC                  RCC_APB5ENCR_DCMIPPENC_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENCR_GFXTIMENC_Pos              (4U)
+#define RCC_APB5ENCR_GFXTIMENC_Msk              (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENCR_GFXTIMENC                  RCC_APB5ENCR_GFXTIMENC_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENCR_VENCENC_Pos                (5U)
+#define RCC_APB5ENCR_VENCENC_Msk                (0x1UL << RCC_APB5ENCR_VENCENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENCR_VENCENC                    RCC_APB5ENCR_VENCENC_Msk             /*!< VENC enable */
+#define RCC_APB5ENCR_CSIENC_Pos                 (6U)
+#define RCC_APB5ENCR_CSIENC_Msk                 (0x1UL << RCC_APB5ENCR_CSIENC_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENCR_CSIENC                     RCC_APB5ENCR_CSIENC_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENCR register  *****************/
+#define RCC_BUSLPENCR_ACLKNLPENC_Pos            (0U)
+#define RCC_BUSLPENCR_ACLKNLPENC_Msk            (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENCR_ACLKNLPENC                RCC_BUSLPENCR_ACLKNLPENC_Msk         /*!< ACLKN enable in Sleep mode */
+#define RCC_BUSLPENCR_ACLKNCLPENC_Pos           (1U)
+#define RCC_BUSLPENCR_ACLKNCLPENC_Msk           (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENCR_ACLKNCLPENC               RCC_BUSLPENCR_ACLKNCLPENC_Msk        /*!< ACLKNC enable in Sleep mode */
+
+/****************  Bit definition for RCC_MISCLPENCR register  ****************/
+#define RCC_MISCLPENCR_DBGLPENC_Pos             (0U)
+#define RCC_MISCLPENCR_DBGLPENC_Msk             (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENCR_DBGLPENC                 RCC_MISCLPENCR_DBGLPENC_Msk          /*!< DBG enable in Sleep mode */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos     (3U)
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk     (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC         RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk  /*!< XSPIPHYCOMP enable in Sleep mode */
+#define RCC_MISCLPENCR_PERLPENC_Pos             (6U)
+#define RCC_MISCLPENCR_PERLPENC_Msk             (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENCR_PERLPENC                 RCC_MISCLPENCR_PERLPENC_Msk          /*!< PER enable in Sleep mode */
+
+/****************  Bit definition for RCC_MEMLPENCR register  *****************/
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos         (0U)
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENCR_AXISRAM3LPENC             RCC_MEMLPENCR_AXISRAM3LPENC_Msk      /*!< AXISRAM3 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos         (1U)
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENCR_AXISRAM4LPENC             RCC_MEMLPENCR_AXISRAM4LPENC_Msk      /*!< AXISRAM4 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos         (2U)
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENCR_AXISRAM5LPENC             RCC_MEMLPENCR_AXISRAM5LPENC_Msk      /*!< AXISRAM5 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos         (3U)
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENCR_AXISRAM6LPENC             RCC_MEMLPENCR_AXISRAM6LPENC_Msk      /*!< AXISRAM6 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos         (4U)
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC             RCC_MEMLPENCR_AHBSRAM1LPENC_Msk      /*!< AHBSRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos         (5U)
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC             RCC_MEMLPENCR_AHBSRAM2LPENC_Msk      /*!< AHBSRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos          (6U)
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENCR_BKPSRAMLPENC              RCC_MEMLPENCR_BKPSRAMLPENC_Msk       /*!< BKPSRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos         (7U)
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENCR_AXISRAM1LPENC             RCC_MEMLPENCR_AXISRAM1LPENC_Msk      /*!< AXISRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos         (8U)
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENCR_AXISRAM2LPENC             RCC_MEMLPENCR_AXISRAM2LPENC_Msk      /*!< AXISRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos          (9U)
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENCR_FLEXRAMLPENC              RCC_MEMLPENCR_FLEXRAMLPENC_Msk       /*!< FLEXRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_VENCRAMLPENC_Pos          (11U)
+#define RCC_MEMLPENCR_VENCRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENCR_VENCRAMLPENC              RCC_MEMLPENCR_VENCRAMLPENC_Msk       /*!< VENCRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_BOOTROMLPENC_Pos          (12U)
+#define RCC_MEMLPENCR_BOOTROMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENCR_BOOTROMLPENC              RCC_MEMLPENCR_BOOTROMLPENC_Msk       /*!< Boot ROM enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB1LPENCR register  ****************/
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos          (4U)
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk          (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENCR_GPDMA1LPENC              RCC_AHB1LPENCR_GPDMA1LPENC_Msk       /*!< GPDMA1 enable in Sleep mode */
+#define RCC_AHB1LPENCR_ADC12LPENC_Pos           (5U)
+#define RCC_AHB1LPENCR_ADC12LPENC_Msk           (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENCR_ADC12LPENC               RCC_AHB1LPENCR_ADC12LPENC_Msk        /*!< ADC12 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB2LPENCR register  ****************/
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos          (12U)
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk          (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENCR_RAMCFGLPENC              RCC_AHB2LPENCR_RAMCFGLPENC_Msk       /*!< RAMCFG enable in Sleep mode */
+#define RCC_AHB2LPENCR_MDF1LPENC_Pos            (16U)
+#define RCC_AHB2LPENCR_MDF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENCR_MDF1LPENC                RCC_AHB2LPENCR_MDF1LPENC_Msk         /*!< MDF1 enable in Sleep mode */
+#define RCC_AHB2LPENCR_ADF1LPENC_Pos            (17U)
+#define RCC_AHB2LPENCR_ADF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENCR_ADF1LPENC                RCC_AHB2LPENCR_ADF1LPENC_Msk         /*!< ADF1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB3LPENCR register  ****************/
+#define RCC_AHB3LPENCR_RNGLPENC_Pos             (0U)
+#define RCC_AHB3LPENCR_RNGLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENCR_RNGLPENC                 RCC_AHB3LPENCR_RNGLPENC_Msk          /*!< RNG enable in Sleep mode */
+#define RCC_AHB3LPENCR_HASHLPENC_Pos            (1U)
+#define RCC_AHB3LPENCR_HASHLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENCR_HASHLPENC                RCC_AHB3LPENCR_HASHLPENC_Msk         /*!< HASH enable in Sleep mode */
+#define RCC_AHB3LPENCR_PKALPENC_Pos             (8U)
+#define RCC_AHB3LPENCR_PKALPENC_Msk             (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENCR_PKALPENC                 RCC_AHB3LPENCR_PKALPENC_Msk          /*!< PKA enable in Sleep mode */
+#define RCC_AHB3LPENCR_RIFSCLPENC_Pos           (9U)
+#define RCC_AHB3LPENCR_RIFSCLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENCR_RIFSCLPENC               RCC_AHB3LPENCR_RIFSCLPENC_Msk        /*!< RIFSC enable in Sleep mode */
+#define RCC_AHB3LPENCR_IACLPENC_Pos             (10U)
+#define RCC_AHB3LPENCR_IACLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENCR_IACLPENC                 RCC_AHB3LPENCR_IACLPENC_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENCR_RISAFLPENC_Pos           (14U)
+#define RCC_AHB3LPENCR_RISAFLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENCR_RISAFLPENC               RCC_AHB3LPENCR_RISAFLPENC_Msk        /*!< RISAF enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB4LPENCR register  ****************/
+#define RCC_AHB4LPENCR_GPIOALPENC_Pos           (0U)
+#define RCC_AHB4LPENCR_GPIOALPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENCR_GPIOALPENC               RCC_AHB4LPENCR_GPIOALPENC_Msk        /*!< GPIO A enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOBLPENC_Pos           (1U)
+#define RCC_AHB4LPENCR_GPIOBLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENCR_GPIOBLPENC               RCC_AHB4LPENCR_GPIOBLPENC_Msk        /*!< GPIO B enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOCLPENC_Pos           (2U)
+#define RCC_AHB4LPENCR_GPIOCLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENCR_GPIOCLPENC               RCC_AHB4LPENCR_GPIOCLPENC_Msk        /*!< GPIO C enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIODLPENC_Pos           (3U)
+#define RCC_AHB4LPENCR_GPIODLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENCR_GPIODLPENC               RCC_AHB4LPENCR_GPIODLPENC_Msk        /*!< GPIO D enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOELPENC_Pos           (4U)
+#define RCC_AHB4LPENCR_GPIOELPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENCR_GPIOELPENC               RCC_AHB4LPENCR_GPIOELPENC_Msk        /*!< GPIO E enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOFLPENC_Pos           (5U)
+#define RCC_AHB4LPENCR_GPIOFLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENCR_GPIOFLPENC               RCC_AHB4LPENCR_GPIOFLPENC_Msk        /*!< GPIO F enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOGLPENC_Pos           (6U)
+#define RCC_AHB4LPENCR_GPIOGLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENCR_GPIOGLPENC               RCC_AHB4LPENCR_GPIOGLPENC_Msk        /*!< GPIO G enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOHLPENC_Pos           (7U)
+#define RCC_AHB4LPENCR_GPIOHLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENCR_GPIOHLPENC               RCC_AHB4LPENCR_GPIOHLPENC_Msk        /*!< GPIO H enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIONLPENC_Pos           (13U)
+#define RCC_AHB4LPENCR_GPIONLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENCR_GPIONLPENC               RCC_AHB4LPENCR_GPIONLPENC_Msk        /*!< GPIO N enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOOLPENC_Pos           (14U)
+#define RCC_AHB4LPENCR_GPIOOLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENCR_GPIOOLPENC               RCC_AHB4LPENCR_GPIOOLPENC_Msk        /*!< GPIO O enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOPLPENC_Pos           (15U)
+#define RCC_AHB4LPENCR_GPIOPLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENCR_GPIOPLPENC               RCC_AHB4LPENCR_GPIOPLPENC_Msk        /*!< GPIO P enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOQLPENC_Pos           (16U)
+#define RCC_AHB4LPENCR_GPIOQLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENCR_GPIOQLPENC               RCC_AHB4LPENCR_GPIOQLPENC_Msk        /*!< GPIO Q enable in Sleep mode */
+#define RCC_AHB4LPENCR_PWRLPENC_Pos             (18U)
+#define RCC_AHB4LPENCR_PWRLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENCR_PWRLPENC                 RCC_AHB4LPENCR_PWRLPENC_Msk          /*!< PWR enable in Sleep mode */
+#define RCC_AHB4LPENCR_CRCLPENC_Pos             (19U)
+#define RCC_AHB4LPENCR_CRCLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENCR_CRCLPENC                 RCC_AHB4LPENCR_CRCLPENC_Msk          /*!< CRC enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB5LPENCR register  ****************/
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos          (0U)
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENCR_HPDMA1LPENC              RCC_AHB5LPENCR_HPDMA1LPENC_Msk       /*!< HPDMA1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_DMA2DLPENC_Pos           (1U)
+#define RCC_AHB5LPENCR_DMA2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENCR_DMA2DLPENC               RCC_AHB5LPENCR_DMA2DLPENC_Msk        /*!< DMA2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_JPEGLPENC_Pos            (3U)
+#define RCC_AHB5LPENCR_JPEGLPENC_Msk            (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENCR_JPEGLPENC                RCC_AHB5LPENCR_JPEGLPENC_Msk         /*!< JPEG enable in Sleep mode */
+#define RCC_AHB5LPENCR_FMCLPENC_Pos             (4U)
+#define RCC_AHB5LPENCR_FMCLPENC_Msk             (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENCR_FMCLPENC                 RCC_AHB5LPENCR_FMCLPENC_Msk          /*!< FMC enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI1LPENC_Pos           (5U)
+#define RCC_AHB5LPENCR_XSPI1LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENCR_XSPI1LPENC               RCC_AHB5LPENCR_XSPI1LPENC_Msk        /*!< XSPI1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_PSSILPENC_Pos            (6U)
+#define RCC_AHB5LPENCR_PSSILPENC_Msk            (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENCR_PSSILPENC                RCC_AHB5LPENCR_PSSILPENC_Msk         /*!< PSSI enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos          (7U)
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENCR_SDMMC2LPENC              RCC_AHB5LPENCR_SDMMC2LPENC_Msk       /*!< SDMMC2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos          (8U)
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENCR_SDMMC1LPENC              RCC_AHB5LPENCR_SDMMC1LPENC_Msk       /*!< SDMMC1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI2LPENC_Pos           (12U)
+#define RCC_AHB5LPENCR_XSPI2LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENCR_XSPI2LPENC               RCC_AHB5LPENCR_XSPI2LPENC_Msk        /*!< XSPI2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPIMLPENC_Pos           (13U)
+#define RCC_AHB5LPENCR_XSPIMLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENCR_XSPIMLPENC               RCC_AHB5LPENCR_XSPIMLPENC_Msk        /*!< XSPIM enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI3LPENC_Pos           (17U)
+#define RCC_AHB5LPENCR_XSPI3LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENCR_XSPI3LPENC               RCC_AHB5LPENCR_XSPI3LPENC_Msk        /*!< XSPI3 enable in Sleep mode */
+#define RCC_AHB5LPENCR_GFXMMULPENC_Pos          (19U)
+#define RCC_AHB5LPENCR_GFXMMULPENC_Msk          (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENCR_GFXMMULPENC              RCC_AHB5LPENCR_GFXMMULPENC_Msk       /*!< GFXMMU enable in Sleep mode */
+#define RCC_AHB5LPENCR_GPU2DLPENC_Pos           (20U)
+#define RCC_AHB5LPENCR_GPU2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENCR_GPU2DLPENC               RCC_AHB5LPENCR_GPU2DLPENC_Msk        /*!< GPU2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos         (22U)
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk         (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENCR_ETH1MACLPENC             RCC_AHB5LPENCR_ETH1MACLPENC_Msk      /*!< ETH1MAC enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos          (23U)
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENCR_ETH1TXLPENC              RCC_AHB5LPENCR_ETH1TXLPENC_Msk       /*!< ETH1TX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos          (24U)
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENCR_ETH1RXLPENC              RCC_AHB5LPENCR_ETH1RXLPENC_Msk       /*!< ETH1RX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1LPENC_Pos            (25U)
+#define RCC_AHB5LPENCR_ETH1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENCR_ETH1LPENC                RCC_AHB5LPENCR_ETH1LPENC_Msk         /*!< ETH1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG1LPENC_Pos            (26U)
+#define RCC_AHB5LPENCR_OTG1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENCR_OTG1LPENC                RCC_AHB5LPENCR_OTG1LPENC_Msk         /*!< OTG1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos         (27U)
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC             RCC_AHB5LPENCR_OTGPHY1LPENC_Msk      /*!< OTGPHY1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos         (28U)
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC             RCC_AHB5LPENCR_OTGPHY2LPENC_Msk      /*!< OTGPHY2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG2LPENC_Pos            (29U)
+#define RCC_AHB5LPENCR_OTG2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENCR_OTG2LPENC                RCC_AHB5LPENCR_OTG2LPENC_Msk         /*!< OTG2 enable in Sleep mode */
+
+/***************  Bit definition for RCC_APB1LPENCR1 register  ****************/
+#define RCC_APB1LPENCR1_TIM2LPENC_Pos           (0U)
+#define RCC_APB1LPENCR1_TIM2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENCR1_TIM2LPENC               RCC_APB1LPENCR1_TIM2LPENC_Msk        /*!< TIM2 enable */
+#define RCC_APB1LPENCR1_TIM3LPENC_Pos           (1U)
+#define RCC_APB1LPENCR1_TIM3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENCR1_TIM3LPENC               RCC_APB1LPENCR1_TIM3LPENC_Msk        /*!< TIM3 enable */
+#define RCC_APB1LPENCR1_TIM4LPENC_Pos           (2U)
+#define RCC_APB1LPENCR1_TIM4LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENCR1_TIM4LPENC               RCC_APB1LPENCR1_TIM4LPENC_Msk        /*!< TIM4 enable */
+#define RCC_APB1LPENCR1_TIM5LPENC_Pos           (3U)
+#define RCC_APB1LPENCR1_TIM5LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENCR1_TIM5LPENC               RCC_APB1LPENCR1_TIM5LPENC_Msk        /*!< TIM5 enable */
+#define RCC_APB1LPENCR1_TIM6LPENC_Pos           (4U)
+#define RCC_APB1LPENCR1_TIM6LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENCR1_TIM6LPENC               RCC_APB1LPENCR1_TIM6LPENC_Msk        /*!< TIM6 enable */
+#define RCC_APB1LPENCR1_TIM7LPENC_Pos           (5U)
+#define RCC_APB1LPENCR1_TIM7LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENCR1_TIM7LPENC               RCC_APB1LPENCR1_TIM7LPENC_Msk        /*!< TIM7 enable */
+#define RCC_APB1LPENCR1_TIM12LPENC_Pos          (6U)
+#define RCC_APB1LPENCR1_TIM12LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENCR1_TIM12LPENC              RCC_APB1LPENCR1_TIM12LPENC_Msk       /*!< TIM12 enable */
+#define RCC_APB1LPENCR1_TIM13LPENC_Pos          (7U)
+#define RCC_APB1LPENCR1_TIM13LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENCR1_TIM13LPENC              RCC_APB1LPENCR1_TIM13LPENC_Msk       /*!< TIM13 enable */
+#define RCC_APB1LPENCR1_TIM14LPENC_Pos          (8U)
+#define RCC_APB1LPENCR1_TIM14LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR1_TIM14LPENC              RCC_APB1LPENCR1_TIM14LPENC_Msk       /*!< TIM14 enable */
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos         (9U)
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENCR1_LPTIM1LPENC             RCC_APB1LPENCR1_LPTIM1LPENC_Msk      /*!< LPTIM1 enable */
+#define RCC_APB1LPENCR1_WWDGLPENC_Pos           (11U)
+#define RCC_APB1LPENCR1_WWDGLPENC_Msk           (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENCR1_WWDGLPENC               RCC_APB1LPENCR1_WWDGLPENC_Msk        /*!< WWDG enable */
+#define RCC_APB1LPENCR1_TIM10LPENC_Pos          (12U)
+#define RCC_APB1LPENCR1_TIM10LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENCR1_TIM10LPENC              RCC_APB1LPENCR1_TIM10LPENC_Msk       /*!< TIM10 enable */
+#define RCC_APB1LPENCR1_TIM11LPENC_Pos          (13U)
+#define RCC_APB1LPENCR1_TIM11LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENCR1_TIM11LPENC              RCC_APB1LPENCR1_TIM11LPENC_Msk       /*!< TIM11 enable */
+#define RCC_APB1LPENCR1_SPI2LPENC_Pos           (14U)
+#define RCC_APB1LPENCR1_SPI2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENCR1_SPI2LPENC               RCC_APB1LPENCR1_SPI2LPENC_Msk        /*!< SPI2 enable */
+#define RCC_APB1LPENCR1_SPI3LPENC_Pos           (15U)
+#define RCC_APB1LPENCR1_SPI3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENCR1_SPI3LPENC               RCC_APB1LPENCR1_SPI3LPENC_Msk        /*!< SPI3 enable */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos       (16U)
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk       (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC           RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk    /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENCR1_USART2LPENC_Pos         (17U)
+#define RCC_APB1LPENCR1_USART2LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENCR1_USART2LPENC             RCC_APB1LPENCR1_USART2LPENC_Msk      /*!< USART2 enable */
+#define RCC_APB1LPENCR1_USART3LPENC_Pos         (18U)
+#define RCC_APB1LPENCR1_USART3LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENCR1_USART3LPENC             RCC_APB1LPENCR1_USART3LPENC_Msk      /*!< USART3 enable */
+#define RCC_APB1LPENCR1_UART4LPENC_Pos          (19U)
+#define RCC_APB1LPENCR1_UART4LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENCR1_UART4LPENC              RCC_APB1LPENCR1_UART4LPENC_Msk       /*!< UART4 enable */
+#define RCC_APB1LPENCR1_UART5LPENC_Pos          (20U)
+#define RCC_APB1LPENCR1_UART5LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENCR1_UART5LPENC              RCC_APB1LPENCR1_UART5LPENC_Msk       /*!< UART5 enable */
+#define RCC_APB1LPENCR1_I2C1LPENC_Pos           (21U)
+#define RCC_APB1LPENCR1_I2C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENCR1_I2C1LPENC               RCC_APB1LPENCR1_I2C1LPENC_Msk        /*!< I2C1 enable */
+#define RCC_APB1LPENCR1_I2C2LPENC_Pos           (22U)
+#define RCC_APB1LPENCR1_I2C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENCR1_I2C2LPENC               RCC_APB1LPENCR1_I2C2LPENC_Msk        /*!< I2C2 enable */
+#define RCC_APB1LPENCR1_I2C3LPENC_Pos           (23U)
+#define RCC_APB1LPENCR1_I2C3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENCR1_I2C3LPENC               RCC_APB1LPENCR1_I2C3LPENC_Msk        /*!< I2C3 enable */
+#define RCC_APB1LPENCR1_I3C1LPENC_Pos           (24U)
+#define RCC_APB1LPENCR1_I3C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENCR1_I3C1LPENC               RCC_APB1LPENCR1_I3C1LPENC_Msk        /*!< I3C1 enable */
+#define RCC_APB1LPENCR1_I3C2LPENC_Pos           (25U)
+#define RCC_APB1LPENCR1_I3C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENCR1_I3C2LPENC               RCC_APB1LPENCR1_I3C2LPENC_Msk        /*!< I3C2 enable */
+#define RCC_APB1LPENCR1_UART7LPENC_Pos          (30U)
+#define RCC_APB1LPENCR1_UART7LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENCR1_UART7LPENC              RCC_APB1LPENCR1_UART7LPENC_Msk       /*!< UART7 enable */
+#define RCC_APB1LPENCR1_UART8LPENC_Pos          (31U)
+#define RCC_APB1LPENCR1_UART8LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENCR1_UART8LPENC              RCC_APB1LPENCR1_UART8LPENC_Msk       /*!< UART8 enable */
+
+/***************  Bit definition for RCC_APB1LPENCR2 register  ****************/
+#define RCC_APB1LPENCR2_MDIOSLPENC_Pos          (5U)
+#define RCC_APB1LPENCR2_MDIOSLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENCR2_MDIOSLPENC              RCC_APB1LPENCR2_MDIOSLPENC_Msk       /*!< MDIOS enable */
+#define RCC_APB1LPENCR2_FDCANLPENC_Pos          (8U)
+#define RCC_APB1LPENCR2_FDCANLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR2_FDCANLPENC              RCC_APB1LPENCR2_FDCANLPENC_Msk       /*!< FDCAN enable */
+#define RCC_APB1LPENCR2_UCPD1LPENC_Pos          (18U)
+#define RCC_APB1LPENCR2_UCPD1LPENC_Msk          (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENCR2_UCPD1LPENC              RCC_APB1LPENCR2_UCPD1LPENC_Msk       /*!< UCPD1 enable */
+
+/****************  Bit definition for RCC_APB2LPENCR register  ****************/
+#define RCC_APB2LPENCR_TIM1LPENC_Pos            (0U)
+#define RCC_APB2LPENCR_TIM1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENCR_TIM1LPENC                RCC_APB2LPENCR_TIM1LPENC_Msk         /*!< TIM1 enable */
+#define RCC_APB2LPENCR_TIM8LPENC_Pos            (1U)
+#define RCC_APB2LPENCR_TIM8LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENCR_TIM8LPENC                RCC_APB2LPENCR_TIM8LPENC_Msk         /*!< TIM8 enable */
+#define RCC_APB2LPENCR_USART1LPENC_Pos          (4U)
+#define RCC_APB2LPENCR_USART1LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENCR_USART1LPENC              RCC_APB2LPENCR_USART1LPENC_Msk       /*!< USART1 enable */
+#define RCC_APB2LPENCR_USART6LPENC_Pos          (5U)
+#define RCC_APB2LPENCR_USART6LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENCR_USART6LPENC              RCC_APB2LPENCR_USART6LPENC_Msk       /*!< USART6 enable */
+#define RCC_APB2LPENCR_UART9LPENC_Pos           (6U)
+#define RCC_APB2LPENCR_UART9LPENC_Msk           (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENCR_UART9LPENC               RCC_APB2LPENCR_UART9LPENC_Msk        /*!< UART9 enable */
+#define RCC_APB2LPENCR_USART10LPENC_Pos         (7U)
+#define RCC_APB2LPENCR_USART10LPENC_Msk         (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENCR_USART10LPENC             RCC_APB2LPENCR_USART10LPENC_Msk      /*!< USART10 enable */
+#define RCC_APB2LPENCR_SPI1LPENC_Pos            (12U)
+#define RCC_APB2LPENCR_SPI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENCR_SPI1LPENC                RCC_APB2LPENCR_SPI1LPENC_Msk         /*!< SPI1 enable */
+#define RCC_APB2LPENCR_SPI4LPENC_Pos            (13U)
+#define RCC_APB2LPENCR_SPI4LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENCR_SPI4LPENC                RCC_APB2LPENCR_SPI4LPENC_Msk         /*!< SPI4 enable */
+#define RCC_APB2LPENCR_TIM18LPENC_Pos           (15U)
+#define RCC_APB2LPENCR_TIM18LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENCR_TIM18LPENC               RCC_APB2LPENCR_TIM18LPENC_Msk        /*!< TIM18 enable */
+#define RCC_APB2LPENCR_TIM15LPENC_Pos           (16U)
+#define RCC_APB2LPENCR_TIM15LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENCR_TIM15LPENC               RCC_APB2LPENCR_TIM15LPENC_Msk        /*!< TIM15 enable */
+#define RCC_APB2LPENCR_TIM16LPENC_Pos           (17U)
+#define RCC_APB2LPENCR_TIM16LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENCR_TIM16LPENC               RCC_APB2LPENCR_TIM16LPENC_Msk        /*!< TIM16 enable */
+#define RCC_APB2LPENCR_TIM17LPENC_Pos           (18U)
+#define RCC_APB2LPENCR_TIM17LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENCR_TIM17LPENC               RCC_APB2LPENCR_TIM17LPENC_Msk        /*!< TIM17 enable */
+#define RCC_APB2LPENCR_TIM9LPENC_Pos            (19U)
+#define RCC_APB2LPENCR_TIM9LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENCR_TIM9LPENC                RCC_APB2LPENCR_TIM9LPENC_Msk         /*!< TIM9 enable */
+#define RCC_APB2LPENCR_SPI5LPENC_Pos            (20U)
+#define RCC_APB2LPENCR_SPI5LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENCR_SPI5LPENC                RCC_APB2LPENCR_SPI5LPENC_Msk         /*!< SPI5 enable */
+#define RCC_APB2LPENCR_SAI1LPENC_Pos            (21U)
+#define RCC_APB2LPENCR_SAI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENCR_SAI1LPENC                RCC_APB2LPENCR_SAI1LPENC_Msk         /*!< SAI1 enable */
+#define RCC_APB2LPENCR_SAI2LPENC_Pos            (22U)
+#define RCC_APB2LPENCR_SAI2LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENCR_SAI2LPENC                RCC_APB2LPENCR_SAI2LPENC_Msk         /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENCR register  ****************/
+#define RCC_APB3LPENCR_DFTLPENC_Pos             (2U)
+#define RCC_APB3LPENCR_DFTLPENC_Msk             (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENCR_DFTLPENC                 RCC_APB3LPENCR_DFTLPENC_Msk          /*!< DFT enable */
+
+/***************  Bit definition for RCC_APB4LPENCR1 register  ****************/
+#define RCC_APB4LPENCR1_HDPLPENC_Pos            (2U)
+#define RCC_APB4LPENCR1_HDPLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR1_HDPLPENC                RCC_APB4LPENCR1_HDPLPENC_Msk         /*!< HDP enable */
+#define RCC_APB4LPENCR1_LPUART1LPENC_Pos        (3U)
+#define RCC_APB4LPENCR1_LPUART1LPENC_Msk        (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENCR1_LPUART1LPENC            RCC_APB4LPENCR1_LPUART1LPENC_Msk     /*!< LPUART1 enable */
+#define RCC_APB4LPENCR1_SPI6LPENC_Pos           (5U)
+#define RCC_APB4LPENCR1_SPI6LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENCR1_SPI6LPENC               RCC_APB4LPENCR1_SPI6LPENC_Msk        /*!< SPI6 enable */
+#define RCC_APB4LPENCR1_I2C4LPENC_Pos           (7U)
+#define RCC_APB4LPENCR1_I2C4LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENCR1_I2C4LPENC               RCC_APB4LPENCR1_I2C4LPENC_Msk        /*!< I2C4 enable */
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos         (9U)
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENCR1_LPTIM2LPENC             RCC_APB4LPENCR1_LPTIM2LPENC_Msk      /*!< LPTIM2 enable */
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos         (10U)
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENCR1_LPTIM3LPENC             RCC_APB4LPENCR1_LPTIM3LPENC_Msk      /*!< LPTIM3 enable */
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos         (11U)
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENCR1_LPTIM4LPENC             RCC_APB4LPENCR1_LPTIM4LPENC_Msk      /*!< LPTIM4 enable */
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos         (12U)
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENCR1_LPTIM5LPENC             RCC_APB4LPENCR1_LPTIM5LPENC_Msk      /*!< LPTIM5 enable */
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos        (15U)
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk        (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENCR1_VREFBUFLPENC            RCC_APB4LPENCR1_VREFBUFLPENC_Msk     /*!< VREFBUF enable */
+#define RCC_APB4LPENCR1_RTCLPENC_Pos            (16U)
+#define RCC_APB4LPENCR1_RTCLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENCR1_RTCLPENC                RCC_APB4LPENCR1_RTCLPENC_Msk         /*!< RTC enable */
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos         (17U)
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk         (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENCR1_RTCAPBLPENC             RCC_APB4LPENCR1_RTCAPBLPENC_Msk      /*!< RTCAPB enable */
+
+/***************  Bit definition for RCC_APB4LPENCR2 register  ****************/
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos         (0U)
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk         (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENCR2_SYSCFGLPENC             RCC_APB4LPENCR2_SYSCFGLPENC_Msk      /*!< SYSCFG enable */
+#define RCC_APB4LPENCR2_BSECLPENC_Pos           (1U)
+#define RCC_APB4LPENCR2_BSECLPENC_Msk           (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENCR2_BSECLPENC               RCC_APB4LPENCR2_BSECLPENC_Msk        /*!< BSEC enable */
+#define RCC_APB4LPENCR2_DTSLPENC_Pos            (2U)
+#define RCC_APB4LPENCR2_DTSLPENC_Msk            (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR2_DTSLPENC                RCC_APB4LPENCR2_DTSLPENC_Msk         /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENCR register  ****************/
+#define RCC_APB5LPENCR_LTDCLPENC_Pos            (1U)
+#define RCC_APB5LPENCR_LTDCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENCR_LTDCLPENC                RCC_APB5LPENCR_LTDCLPENC_Msk         /*!< LTDC sleep enable */
+#define RCC_APB5LPENCR_DCMIPPLPENC_Pos          (2U)
+#define RCC_APB5LPENCR_DCMIPPLPENC_Msk          (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENCR_DCMIPPLPENC              RCC_APB5LPENCR_DCMIPPLPENC_Msk       /*!< DCMIPP sleep enable */
+#define RCC_APB5LPENCR_GFXTIMLPENC_Pos          (4U)
+#define RCC_APB5LPENCR_GFXTIMLPENC_Msk          (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENCR_GFXTIMLPENC              RCC_APB5LPENCR_GFXTIMLPENC_Msk       /*!< GFXTIM sleep enable */
+#define RCC_APB5LPENCR_VENCLPENC_Pos            (5U)
+#define RCC_APB5LPENCR_VENCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENCR_VENCLPENC                RCC_APB5LPENCR_VENCLPENC_Msk         /*!< VENC sleep enable */
+#define RCC_APB5LPENCR_CSILPENC_Pos             (6U)
+#define RCC_APB5LPENCR_CSILPENC_Msk             (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENCR_CSILPENC                 RCC_APB5LPENCR_CSILPENC_Msk          /*!< CSI sleep enable */
+
+/****************  Bit definition for RCC_PRIVCFGCR0 register  ****************/
+#define RCC_PRIVCFGCR0_LSIPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR0_LSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR0_LSIPRIVC                 RCC_PRIVCFGCR0_LSIPRIVC_Msk          /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_LSEPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR0_LSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR0_LSEPRIVC                 RCC_PRIVCFGCR0_LSEPRIVC_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_MSIPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR0_MSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR0_MSIPRIVC                 RCC_PRIVCFGCR0_MSIPRIVC_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSIPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR0_HSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR0_HSIPRIVC                 RCC_PRIVCFGCR0_HSIPRIVC_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSEPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR0_HSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR0_HSEPRIVC                 RCC_PRIVCFGCR0_HSEPRIVC_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR0 register  *****************/
+#define RCC_PUBCFGCR0_LSIPUBC_Pos               (0U)
+#define RCC_PUBCFGCR0_LSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR0_LSIPUBC                   RCC_PUBCFGCR0_LSIPUBC_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_LSEPUBC_Pos               (1U)
+#define RCC_PUBCFGCR0_LSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR0_LSEPUBC                   RCC_PUBCFGCR0_LSEPUBC_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_MSIPUBC_Pos               (2U)
+#define RCC_PUBCFGCR0_MSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR0_MSIPUBC                   RCC_PUBCFGCR0_MSIPUBC_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSIPUBC_Pos               (3U)
+#define RCC_PUBCFGCR0_HSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR0_HSIPUBC                   RCC_PUBCFGCR0_HSIPUBC_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSEPUBC_Pos               (4U)
+#define RCC_PUBCFGCR0_HSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR0_HSEPUBC                   RCC_PUBCFGCR0_HSEPUBC_Msk            /*!< Public protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR1 register  ****************/
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos            (0U)
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGCR1_PLL1PRIVC                RCC_PRIVCFGCR1_PLL1PRIVC_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos            (1U)
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGCR1_PLL2PRIVC                RCC_PRIVCFGCR1_PLL2PRIVC_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR1_PLL3PRIVC                RCC_PRIVCFGCR1_PLL3PRIVC_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR1_PLL4PRIVC                RCC_PRIVCFGCR1_PLL4PRIVC_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR1 register  *****************/
+#define RCC_PUBCFGCR1_PLL1PUBC_Pos              (0U)
+#define RCC_PUBCFGCR1_PLL1PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGCR1_PLL1PUBC                  RCC_PUBCFGCR1_PLL1PUBC_Msk           /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL2PUBC_Pos              (1U)
+#define RCC_PUBCFGCR1_PLL2PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR1_PLL2PUBC                  RCC_PUBCFGCR1_PLL2PUBC_Msk           /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL3PUBC_Pos              (2U)
+#define RCC_PUBCFGCR1_PLL3PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR1_PLL3PUBC                  RCC_PUBCFGCR1_PLL3PUBC_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL4PUBC_Pos              (3U)
+#define RCC_PUBCFGCR1_PLL4PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR1_PLL4PUBC                  RCC_PUBCFGCR1_PLL4PUBC_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR2 register  ****************/
+#define RCC_PRIVCFGCR2_IC1PRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR2_IC1PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR2_IC1PRIVC                 RCC_PRIVCFGCR2_IC1PRIVC_Msk          /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC2PRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR2_IC2PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR2_IC2PRIVC                 RCC_PRIVCFGCR2_IC2PRIVC_Msk          /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC3PRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR2_IC3PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR2_IC3PRIVC                 RCC_PRIVCFGCR2_IC3PRIVC_Msk          /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC4PRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR2_IC4PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR2_IC4PRIVC                 RCC_PRIVCFGCR2_IC4PRIVC_Msk          /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC5PRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR2_IC5PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR2_IC5PRIVC                 RCC_PRIVCFGCR2_IC5PRIVC_Msk          /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC6PRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR2_IC6PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR2_IC6PRIVC                 RCC_PRIVCFGCR2_IC6PRIVC_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC7PRIVC_Pos             (6U)
+#define RCC_PRIVCFGCR2_IC7PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGCR2_IC7PRIVC                 RCC_PRIVCFGCR2_IC7PRIVC_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC8PRIVC_Pos             (7U)
+#define RCC_PRIVCFGCR2_IC8PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGCR2_IC8PRIVC                 RCC_PRIVCFGCR2_IC8PRIVC_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC9PRIVC_Pos             (8U)
+#define RCC_PRIVCFGCR2_IC9PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGCR2_IC9PRIVC                 RCC_PRIVCFGCR2_IC9PRIVC_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC10PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR2_IC10PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR2_IC10PRIVC                RCC_PRIVCFGCR2_IC10PRIVC_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC11PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR2_IC11PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR2_IC11PRIVC                RCC_PRIVCFGCR2_IC11PRIVC_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC12PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR2_IC12PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR2_IC12PRIVC                RCC_PRIVCFGCR2_IC12PRIVC_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC13PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR2_IC13PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR2_IC13PRIVC                RCC_PRIVCFGCR2_IC13PRIVC_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC14PRIVC_Pos            (13U)
+#define RCC_PRIVCFGCR2_IC14PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGCR2_IC14PRIVC                RCC_PRIVCFGCR2_IC14PRIVC_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC15PRIVC_Pos            (14U)
+#define RCC_PRIVCFGCR2_IC15PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGCR2_IC15PRIVC                RCC_PRIVCFGCR2_IC15PRIVC_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC16PRIVC_Pos            (15U)
+#define RCC_PRIVCFGCR2_IC16PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGCR2_IC16PRIVC                RCC_PRIVCFGCR2_IC16PRIVC_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC17PRIVC_Pos            (16U)
+#define RCC_PRIVCFGCR2_IC17PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGCR2_IC17PRIVC                RCC_PRIVCFGCR2_IC17PRIVC_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC18PRIVC_Pos            (17U)
+#define RCC_PRIVCFGCR2_IC18PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGCR2_IC18PRIVC                RCC_PRIVCFGCR2_IC18PRIVC_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC19PRIVC_Pos            (18U)
+#define RCC_PRIVCFGCR2_IC19PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGCR2_IC19PRIVC                RCC_PRIVCFGCR2_IC19PRIVC_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC20PRIVC_Pos            (19U)
+#define RCC_PRIVCFGCR2_IC20PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGCR2_IC20PRIVC                RCC_PRIVCFGCR2_IC20PRIVC_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR2 register  *****************/
+#define RCC_PUBCFGCR2_IC1PUBC_Pos               (0U)
+#define RCC_PUBCFGCR2_IC1PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR2_IC1PUBC                   RCC_PUBCFGCR2_IC1PUBC_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC2PUBC_Pos               (1U)
+#define RCC_PUBCFGCR2_IC2PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR2_IC2PUBC                   RCC_PUBCFGCR2_IC2PUBC_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC3PUBC_Pos               (2U)
+#define RCC_PUBCFGCR2_IC3PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR2_IC3PUBC                   RCC_PUBCFGCR2_IC3PUBC_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC4PUBC_Pos               (3U)
+#define RCC_PUBCFGCR2_IC4PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR2_IC4PUBC                   RCC_PUBCFGCR2_IC4PUBC_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC5PUBC_Pos               (4U)
+#define RCC_PUBCFGCR2_IC5PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR2_IC5PUBC                   RCC_PUBCFGCR2_IC5PUBC_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC6PUBC_Pos               (5U)
+#define RCC_PUBCFGCR2_IC6PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR2_IC6PUBC                   RCC_PUBCFGCR2_IC6PUBC_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC7PUBC_Pos               (6U)
+#define RCC_PUBCFGCR2_IC7PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR2_IC7PUBC                   RCC_PUBCFGCR2_IC7PUBC_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC8PUBC_Pos               (7U)
+#define RCC_PUBCFGCR2_IC8PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGCR2_IC8PUBC                   RCC_PUBCFGCR2_IC8PUBC_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC9PUBC_Pos               (8U)
+#define RCC_PUBCFGCR2_IC9PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGCR2_IC9PUBC                   RCC_PUBCFGCR2_IC9PUBC_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC10PUBC_Pos              (9U)
+#define RCC_PUBCFGCR2_IC10PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR2_IC10PUBC                  RCC_PUBCFGCR2_IC10PUBC_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC11PUBC_Pos              (10U)
+#define RCC_PUBCFGCR2_IC11PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR2_IC11PUBC                  RCC_PUBCFGCR2_IC11PUBC_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC12PUBC_Pos              (11U)
+#define RCC_PUBCFGCR2_IC12PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR2_IC12PUBC                  RCC_PUBCFGCR2_IC12PUBC_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC13PUBC_Pos              (12U)
+#define RCC_PUBCFGCR2_IC13PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR2_IC13PUBC                  RCC_PUBCFGCR2_IC13PUBC_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC14PUBC_Pos              (13U)
+#define RCC_PUBCFGCR2_IC14PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGCR2_IC14PUBC                  RCC_PUBCFGCR2_IC14PUBC_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC15PUBC_Pos              (14U)
+#define RCC_PUBCFGCR2_IC15PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGCR2_IC15PUBC                  RCC_PUBCFGCR2_IC15PUBC_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC16PUBC_Pos              (15U)
+#define RCC_PUBCFGCR2_IC16PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGCR2_IC16PUBC                  RCC_PUBCFGCR2_IC16PUBC_Msk           /*!< Public protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC17PUBC_Pos              (16U)
+#define RCC_PUBCFGCR2_IC17PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGCR2_IC17PUBC                  RCC_PUBCFGCR2_IC17PUBC_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC18PUBC_Pos              (17U)
+#define RCC_PUBCFGCR2_IC18PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGCR2_IC18PUBC                  RCC_PUBCFGCR2_IC18PUBC_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC19PUBC_Pos              (18U)
+#define RCC_PUBCFGCR2_IC19PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGCR2_IC19PUBC                  RCC_PUBCFGCR2_IC19PUBC_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC20PUBC_Pos              (19U)
+#define RCC_PUBCFGCR2_IC20PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGCR2_IC20PUBC                  RCC_PUBCFGCR2_IC20PUBC_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR3 register  ****************/
+#define RCC_PRIVCFGCR3_MODPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR3_MODPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR3_MODPRIVC                 RCC_PRIVCFGCR3_MODPRIVC_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_SYSPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR3_SYSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR3_SYSPRIVC                 RCC_PRIVCFGCR3_SYSPRIVC_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_BUSPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR3_BUSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR3_BUSPRIVC                 RCC_PRIVCFGCR3_BUSPRIVC_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_PERPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR3_PERPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR3_PERPRIVC                 RCC_PRIVCFGCR3_PERPRIVC_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_INTPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR3_INTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR3_INTPRIVC                 RCC_PRIVCFGCR3_INTPRIVC_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_RSTPRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR3_RSTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR3_RSTPRIVC                 RCC_PRIVCFGCR3_RSTPRIVC_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR3 register  *****************/
+#define RCC_PUBCFGCR3_MODPUBC_Pos               (0U)
+#define RCC_PUBCFGCR3_MODPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR3_MODPUBC                   RCC_PUBCFGCR3_MODPUBC_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_SYSPUBC_Pos               (1U)
+#define RCC_PUBCFGCR3_SYSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR3_SYSPUBC                   RCC_PUBCFGCR3_SYSPUBC_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_BUSPUBC_Pos               (2U)
+#define RCC_PUBCFGCR3_BUSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR3_BUSPUBC                   RCC_PUBCFGCR3_BUSPUBC_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_PERPUBC_Pos               (3U)
+#define RCC_PUBCFGCR3_PERPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR3_PERPUBC                   RCC_PUBCFGCR3_PERPUBC_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_INTPUBC_Pos               (4U)
+#define RCC_PUBCFGCR3_INTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR3_INTPUBC                   RCC_PUBCFGCR3_INTPUBC_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_RSTPUBC_Pos               (5U)
+#define RCC_PUBCFGCR3_RSTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR3_RSTPUBC                   RCC_PUBCFGCR3_RSTPUBC_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR4 register  ****************/
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos           (0U)
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk           (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGCR4_ACLKNPRIVC               RCC_PRIVCFGCR4_ACLKNPRIVC_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos          (1U)
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk          (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC              RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk       /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR4_AHBMPRIVC                RCC_PRIVCFGCR4_AHBMPRIVC_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR4_AHB1PRIVC                RCC_PRIVCFGCR4_AHB1PRIVC_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos            (4U)
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGCR4_AHB2PRIVC                RCC_PRIVCFGCR4_AHB2PRIVC_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos            (5U)
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGCR4_AHB3PRIVC                RCC_PRIVCFGCR4_AHB3PRIVC_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos            (6U)
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGCR4_AHB4PRIVC                RCC_PRIVCFGCR4_AHB4PRIVC_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos            (7U)
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGCR4_AHB5PRIVC                RCC_PRIVCFGCR4_AHB5PRIVC_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB1PRIVC_Pos            (8U)
+#define RCC_PRIVCFGCR4_APB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGCR4_APB1PRIVC                RCC_PRIVCFGCR4_APB1PRIVC_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB2PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR4_APB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR4_APB2PRIVC                RCC_PRIVCFGCR4_APB2PRIVC_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB3PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR4_APB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR4_APB3PRIVC                RCC_PRIVCFGCR4_APB3PRIVC_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB4PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR4_APB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR4_APB4PRIVC                RCC_PRIVCFGCR4_APB4PRIVC_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB5PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR4_APB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR4_APB5PRIVC                RCC_PRIVCFGCR4_APB5PRIVC_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_NOCPRIVC_Pos             (13U)
+#define RCC_PRIVCFGCR4_NOCPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGCR4_NOCPRIVC                 RCC_PRIVCFGCR4_NOCPRIVC_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR4 register  *****************/
+#define RCC_PUBCFGCR4_ACLKNPUBC_Pos             (0U)
+#define RCC_PUBCFGCR4_ACLKNPUBC_Msk             (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGCR4_ACLKNPUBC                 RCC_PUBCFGCR4_ACLKNPUBC_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos            (1U)
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk            (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR4_ACLKNCPUBC                RCC_PUBCFGCR4_ACLKNCPUBC_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHBMPUBC_Pos              (2U)
+#define RCC_PUBCFGCR4_AHBMPUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR4_AHBMPUBC                  RCC_PUBCFGCR4_AHBMPUBC_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB1PUBC_Pos              (3U)
+#define RCC_PUBCFGCR4_AHB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR4_AHB1PUBC                  RCC_PUBCFGCR4_AHB1PUBC_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB2PUBC_Pos              (4U)
+#define RCC_PUBCFGCR4_AHB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGCR4_AHB2PUBC                  RCC_PUBCFGCR4_AHB2PUBC_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB3PUBC_Pos              (5U)
+#define RCC_PUBCFGCR4_AHB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGCR4_AHB3PUBC                  RCC_PUBCFGCR4_AHB3PUBC_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB4PUBC_Pos              (6U)
+#define RCC_PUBCFGCR4_AHB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGCR4_AHB4PUBC                  RCC_PUBCFGCR4_AHB4PUBC_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB5PUBC_Pos              (7U)
+#define RCC_PUBCFGCR4_AHB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGCR4_AHB5PUBC                  RCC_PUBCFGCR4_AHB5PUBC_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB1PUBC_Pos              (8U)
+#define RCC_PUBCFGCR4_APB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGCR4_APB1PUBC                  RCC_PUBCFGCR4_APB1PUBC_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB2PUBC_Pos              (9U)
+#define RCC_PUBCFGCR4_APB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR4_APB2PUBC                  RCC_PUBCFGCR4_APB2PUBC_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB3PUBC_Pos              (10U)
+#define RCC_PUBCFGCR4_APB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR4_APB3PUBC                  RCC_PUBCFGCR4_APB3PUBC_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB4PUBC_Pos              (11U)
+#define RCC_PUBCFGCR4_APB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR4_APB4PUBC                  RCC_PUBCFGCR4_APB4PUBC_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB5PUBC_Pos              (12U)
+#define RCC_PUBCFGCR4_APB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR4_APB5PUBC                  RCC_PUBCFGCR4_APB5PUBC_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_NOCPUBC_Pos               (13U)
+#define RCC_PUBCFGCR4_NOCPUBC_Msk               (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGCR4_NOCPUBC                   RCC_PUBCFGCR4_NOCPUBC_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR5 register  *****************/
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos          (0U)
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGCR5_AXISRAM3PUBC              RCC_PUBCFGCR5_AXISRAM3PUBC_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos          (1U)
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC              RCC_PUBCFGCR5_AXISRAM4PUBC_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos          (2U)
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC              RCC_PUBCFGCR5_AXISRAM5PUBC_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos          (3U)
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC              RCC_PUBCFGCR5_AXISRAM6PUBC_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos          (4U)
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC              RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos          (5U)
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC              RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos           (6U)
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC               RCC_PUBCFGCR5_BKPSRAMPUBC_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos          (7U)
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC              RCC_PUBCFGCR5_AXISRAM1PUBC_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos          (8U)
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC              RCC_PUBCFGCR5_AXISRAM2PUBC_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos           (9U)
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC               RCC_PUBCFGCR5_FLEXRAMPUBC_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos           (11U)
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGCR5_VENCRAMPUBC               RCC_PUBCFGCR5_VENCRAMPUBC_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*          Resource Isolation Framework Security Controller (RIFSC)          */
+/*                                                                            */
+/******************************************************************************/
+/****************  Bit definition for RIFSC_RISC_CR register  *****************/
+#define RIFSC_RISC_CR_GLOCK_Pos             (0UL)
+#define RIFSC_RISC_CR_GLOCK_Msk             (0x1UL << RIFSC_RISC_CR_GLOCK_Pos)             /*!< 0x00000001 */
+#define RIFSC_RISC_CR_GLOCK                 RIFSC_RISC_CR_GLOCK_Msk                        /*!< Global lock */
+
+/*************  Bit definition for RIFSC_RISC_SECCFGRx register  **************/
+#define RIFSC_RISC_SECCFGRx_SEC0_Pos        (0U)
+#define RIFSC_RISC_SECCFGRx_SEC0_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos)         /*!< 0x00000001 */
+#define RIFSC_RISC_SECCFGRx_SEC0            RIFSC_RISC_SECCFGRx_SEC0_Msk                   /*!< Security configuration for peripheral 0 */
+#define RIFSC_RISC_SECCFGRx_SEC1_Pos        (1U)
+#define RIFSC_RISC_SECCFGRx_SEC1_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos)         /*!< 0x00000002 */
+#define RIFSC_RISC_SECCFGRx_SEC1            RIFSC_RISC_SECCFGRx_SEC1_Msk                   /*!< Security configuration for peripheral 1 */
+#define RIFSC_RISC_SECCFGRx_SEC2_Pos        (2U)
+#define RIFSC_RISC_SECCFGRx_SEC2_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos)         /*!< 0x00000004 */
+#define RIFSC_RISC_SECCFGRx_SEC2            RIFSC_RISC_SECCFGRx_SEC2_Msk                   /*!< Security configuration for peripheral 2 */
+#define RIFSC_RISC_SECCFGRx_SEC3_Pos        (3U)
+#define RIFSC_RISC_SECCFGRx_SEC3_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos)         /*!< 0x00000008 */
+#define RIFSC_RISC_SECCFGRx_SEC3            RIFSC_RISC_SECCFGRx_SEC3_Msk                   /*!< Security configuration for peripheral 3 */
+#define RIFSC_RISC_SECCFGRx_SEC4_Pos        (4U)
+#define RIFSC_RISC_SECCFGRx_SEC4_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos)         /*!< 0x00000010 */
+#define RIFSC_RISC_SECCFGRx_SEC4            RIFSC_RISC_SECCFGRx_SEC4_Msk                   /*!< Security configuration for peripheral 4 */
+#define RIFSC_RISC_SECCFGRx_SEC5_Pos        (5U)
+#define RIFSC_RISC_SECCFGRx_SEC5_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos)         /*!< 0x00000020 */
+#define RIFSC_RISC_SECCFGRx_SEC5            RIFSC_RISC_SECCFGRx_SEC5_Msk                   /*!< Security configuration for peripheral 5 */
+#define RIFSC_RISC_SECCFGRx_SEC6_Pos        (6U)
+#define RIFSC_RISC_SECCFGRx_SEC6_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos)         /*!< 0x00000040 */
+#define RIFSC_RISC_SECCFGRx_SEC6            RIFSC_RISC_SECCFGRx_SEC6_Msk                   /*!< Security configuration for peripheral 6 */
+#define RIFSC_RISC_SECCFGRx_SEC7_Pos        (7U)
+#define RIFSC_RISC_SECCFGRx_SEC7_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos)         /*!< 0x00000080 */
+#define RIFSC_RISC_SECCFGRx_SEC7            RIFSC_RISC_SECCFGRx_SEC7_Msk                   /*!< Security configuration for peripheral 7 */
+#define RIFSC_RISC_SECCFGRx_SEC8_Pos        (8U)
+#define RIFSC_RISC_SECCFGRx_SEC8_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos)         /*!< 0x00000100 */
+#define RIFSC_RISC_SECCFGRx_SEC8            RIFSC_RISC_SECCFGRx_SEC8_Msk                   /*!< Security configuration for peripheral 8 */
+#define RIFSC_RISC_SECCFGRx_SEC9_Pos        (9U)
+#define RIFSC_RISC_SECCFGRx_SEC9_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos)         /*!< 0x00000200 */
+#define RIFSC_RISC_SECCFGRx_SEC9            RIFSC_RISC_SECCFGRx_SEC9_Msk                   /*!< Security configuration for peripheral 9 */
+#define RIFSC_RISC_SECCFGRx_SEC10_Pos       (10U)
+#define RIFSC_RISC_SECCFGRx_SEC10_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos)        /*!< 0x00000400 */
+#define RIFSC_RISC_SECCFGRx_SEC10           RIFSC_RISC_SECCFGRx_SEC10_Msk                  /*!< Security configuration for peripheral 10 */
+#define RIFSC_RISC_SECCFGRx_SEC11_Pos       (11U)
+#define RIFSC_RISC_SECCFGRx_SEC11_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos)        /*!< 0x00000800 */
+#define RIFSC_RISC_SECCFGRx_SEC11           RIFSC_RISC_SECCFGRx_SEC11_Msk                  /*!< Security configuration for peripheral 11 */
+#define RIFSC_RISC_SECCFGRx_SEC12_Pos       (12U)
+#define RIFSC_RISC_SECCFGRx_SEC12_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos)        /*!< 0x00001000 */
+#define RIFSC_RISC_SECCFGRx_SEC12           RIFSC_RISC_SECCFGRx_SEC12_Msk                  /*!< Security configuration for peripheral 12 */
+#define RIFSC_RISC_SECCFGRx_SEC13_Pos       (13U)
+#define RIFSC_RISC_SECCFGRx_SEC13_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos)        /*!< 0x00002000 */
+#define RIFSC_RISC_SECCFGRx_SEC13           RIFSC_RISC_SECCFGRx_SEC13_Msk                  /*!< Security configuration for peripheral 13 */
+#define RIFSC_RISC_SECCFGRx_SEC14_Pos       (14U)
+#define RIFSC_RISC_SECCFGRx_SEC14_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos)        /*!< 0x00004000 */
+#define RIFSC_RISC_SECCFGRx_SEC14           RIFSC_RISC_SECCFGRx_SEC14_Msk                  /*!< Security configuration for peripheral 14 */
+#define RIFSC_RISC_SECCFGRx_SEC15_Pos       (15U)
+#define RIFSC_RISC_SECCFGRx_SEC15_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos)        /*!< 0x00008000 */
+#define RIFSC_RISC_SECCFGRx_SEC15           RIFSC_RISC_SECCFGRx_SEC15_Msk                  /*!< Security configuration for peripheral 15 */
+#define RIFSC_RISC_SECCFGRx_SEC16_Pos       (16U)
+#define RIFSC_RISC_SECCFGRx_SEC16_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos)        /*!< 0x00010000 */
+#define RIFSC_RISC_SECCFGRx_SEC16           RIFSC_RISC_SECCFGRx_SEC16_Msk                  /*!< Security configuration for peripheral 16 */
+#define RIFSC_RISC_SECCFGRx_SEC17_Pos       (17U)
+#define RIFSC_RISC_SECCFGRx_SEC17_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos)        /*!< 0x00020000 */
+#define RIFSC_RISC_SECCFGRx_SEC17           RIFSC_RISC_SECCFGRx_SEC17_Msk                  /*!< Security configuration for peripheral 17 */
+#define RIFSC_RISC_SECCFGRx_SEC18_Pos       (18U)
+#define RIFSC_RISC_SECCFGRx_SEC18_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos)        /*!< 0x00040000 */
+#define RIFSC_RISC_SECCFGRx_SEC18           RIFSC_RISC_SECCFGRx_SEC18_Msk                  /*!< Security configuration for peripheral 18 */
+#define RIFSC_RISC_SECCFGRx_SEC19_Pos       (19U)
+#define RIFSC_RISC_SECCFGRx_SEC19_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos)        /*!< 0x00080000 */
+#define RIFSC_RISC_SECCFGRx_SEC19           RIFSC_RISC_SECCFGRx_SEC19_Msk                  /*!< Security configuration for peripheral 19 */
+#define RIFSC_RISC_SECCFGRx_SEC20_Pos       (20U)
+#define RIFSC_RISC_SECCFGRx_SEC20_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos)        /*!< 0x00100000 */
+#define RIFSC_RISC_SECCFGRx_SEC20           RIFSC_RISC_SECCFGRx_SEC20_Msk                  /*!< Security configuration for peripheral 20 */
+#define RIFSC_RISC_SECCFGRx_SEC21_Pos       (21U)
+#define RIFSC_RISC_SECCFGRx_SEC21_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos)        /*!< 0x00200000 */
+#define RIFSC_RISC_SECCFGRx_SEC21           RIFSC_RISC_SECCFGRx_SEC21_Msk                  /*!< Security configuration for peripheral 21 */
+#define RIFSC_RISC_SECCFGRx_SEC22_Pos       (22U)
+#define RIFSC_RISC_SECCFGRx_SEC22_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos)        /*!< 0x00400000 */
+#define RIFSC_RISC_SECCFGRx_SEC22           RIFSC_RISC_SECCFGRx_SEC22_Msk                  /*!< Security configuration for peripheral 22 */
+#define RIFSC_RISC_SECCFGRx_SEC23_Pos       (23U)
+#define RIFSC_RISC_SECCFGRx_SEC23_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos)        /*!< 0x00800000 */
+#define RIFSC_RISC_SECCFGRx_SEC23           RIFSC_RISC_SECCFGRx_SEC23_Msk                  /*!< Security configuration for peripheral 23 */
+#define RIFSC_RISC_SECCFGRx_SEC24_Pos       (24U)
+#define RIFSC_RISC_SECCFGRx_SEC24_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos)        /*!< 0x01000000 */
+#define RIFSC_RISC_SECCFGRx_SEC24           RIFSC_RISC_SECCFGRx_SEC24_Msk                  /*!< Security configuration for peripheral 24 */
+#define RIFSC_RISC_SECCFGRx_SEC25_Pos       (25U)
+#define RIFSC_RISC_SECCFGRx_SEC25_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos)        /*!< 0x02000000 */
+#define RIFSC_RISC_SECCFGRx_SEC25           RIFSC_RISC_SECCFGRx_SEC25_Msk                  /*!< Security configuration for peripheral 25 */
+#define RIFSC_RISC_SECCFGRx_SEC26_Pos       (26U)
+#define RIFSC_RISC_SECCFGRx_SEC26_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos)        /*!< 0x04000000 */
+#define RIFSC_RISC_SECCFGRx_SEC26           RIFSC_RISC_SECCFGRx_SEC26_Msk                  /*!< Security configuration for peripheral 26 */
+#define RIFSC_RISC_SECCFGRx_SEC27_Pos       (27U)
+#define RIFSC_RISC_SECCFGRx_SEC27_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos)        /*!< 0x08000000 */
+#define RIFSC_RISC_SECCFGRx_SEC27           RIFSC_RISC_SECCFGRx_SEC27_Msk                  /*!< Security configuration for peripheral 27 */
+#define RIFSC_RISC_SECCFGRx_SEC28_Pos       (28U)
+#define RIFSC_RISC_SECCFGRx_SEC28_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos)        /*!< 0x10000000 */
+#define RIFSC_RISC_SECCFGRx_SEC28           RIFSC_RISC_SECCFGRx_SEC28_Msk                  /*!< Security configuration for peripheral 28 */
+#define RIFSC_RISC_SECCFGRx_SEC29_Pos       (29U)
+#define RIFSC_RISC_SECCFGRx_SEC29_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos)        /*!< 0x20000000 */
+#define RIFSC_RISC_SECCFGRx_SEC29           RIFSC_RISC_SECCFGRx_SEC29_Msk                  /*!< Security configuration for peripheral 29 */
+#define RIFSC_RISC_SECCFGRx_SEC30_Pos       (30U)
+#define RIFSC_RISC_SECCFGRx_SEC30_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos)        /*!< 0x40000000 */
+#define RIFSC_RISC_SECCFGRx_SEC30           RIFSC_RISC_SECCFGRx_SEC30_Msk                  /*!< Security configuration for peripheral 30 */
+#define RIFSC_RISC_SECCFGRx_SEC31_Pos       (31U)
+#define RIFSC_RISC_SECCFGRx_SEC31_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos)        /*!< 0x80000000 */
+#define RIFSC_RISC_SECCFGRx_SEC31           RIFSC_RISC_SECCFGRx_SEC31_Msk                  /*!< Security configuration for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_PRIVCFGRx register  *************/
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos      (0U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos)       /*!< 0x00000001 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV0          RIFSC_RISC_PRIVCFGRx_PRIV0_Msk                 /*!< privileged-only access permission for peripheral 0 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos      (1U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos)       /*!< 0x00000002 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1          RIFSC_RISC_PRIVCFGRx_PRIV1_Msk                 /*!< privileged-only access permission for peripheral 1 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos      (2U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos)       /*!< 0x00000004 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2          RIFSC_RISC_PRIVCFGRx_PRIV2_Msk                 /*!< privileged-only access permission for peripheral 2 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos      (3U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos)       /*!< 0x00000008 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3          RIFSC_RISC_PRIVCFGRx_PRIV3_Msk                 /*!< privileged-only access permission for peripheral 3 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos      (4U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos)       /*!< 0x00000010 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4          RIFSC_RISC_PRIVCFGRx_PRIV4_Msk                 /*!< privileged-only access permission for peripheral 4 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos      (5U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos)       /*!< 0x00000020 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5          RIFSC_RISC_PRIVCFGRx_PRIV5_Msk                 /*!< privileged-only access permission for peripheral 5 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos      (6U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos)       /*!< 0x00000040 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6          RIFSC_RISC_PRIVCFGRx_PRIV6_Msk                 /*!< privileged-only access permission for peripheral 6 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos      (7U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos)       /*!< 0x00000080 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7          RIFSC_RISC_PRIVCFGRx_PRIV7_Msk                 /*!< privileged-only access permission for peripheral 7 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos      (8U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos)       /*!< 0x00000100 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8          RIFSC_RISC_PRIVCFGRx_PRIV8_Msk                 /*!< privileged-only access permission for peripheral 8 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos      (9U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos)       /*!< 0x00000200 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9          RIFSC_RISC_PRIVCFGRx_PRIV9_Msk                 /*!< privileged-only access permission for peripheral 9 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos     (10U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos)      /*!< 0x00000400 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10         RIFSC_RISC_PRIVCFGRx_PRIV10_Msk                /*!< privileged-only access permission for peripheral 10 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos     (11U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos)      /*!< 0x00000800 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11         RIFSC_RISC_PRIVCFGRx_PRIV11_Msk                /*!< privileged-only access permission for peripheral 11 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos     (12U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos)      /*!< 0x00001000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12         RIFSC_RISC_PRIVCFGRx_PRIV12_Msk                /*!< privileged-only access permission for peripheral 12 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos     (13U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos)      /*!< 0x00002000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13         RIFSC_RISC_PRIVCFGRx_PRIV13_Msk                /*!< privileged-only access permission for peripheral 13 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos     (14U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos)      /*!< 0x00004000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14         RIFSC_RISC_PRIVCFGRx_PRIV14_Msk                /*!< privileged-only access permission for peripheral 14 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos     (15U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos)      /*!< 0x00008000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15         RIFSC_RISC_PRIVCFGRx_PRIV15_Msk                /*!< privileged-only access permission for peripheral 15 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos     (16U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos)      /*!< 0x00010000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16         RIFSC_RISC_PRIVCFGRx_PRIV16_Msk                /*!< privileged-only access permission for peripheral 16 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos     (17U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos)      /*!< 0x00020000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17         RIFSC_RISC_PRIVCFGRx_PRIV17_Msk                /*!< privileged-only access permission for peripheral 17 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos     (18U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos)      /*!< 0x00040000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18         RIFSC_RISC_PRIVCFGRx_PRIV18_Msk                /*!< privileged-only access permission for peripheral 18 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos     (19U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos)      /*!< 0x00080000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19         RIFSC_RISC_PRIVCFGRx_PRIV19_Msk                /*!< privileged-only access permission for peripheral 19 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos     (20U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos)      /*!< 0x00100000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20         RIFSC_RISC_PRIVCFGRx_PRIV20_Msk                /*!< privileged-only access permission for peripheral 20 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos     (21U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos)      /*!< 0x00200000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21         RIFSC_RISC_PRIVCFGRx_PRIV21_Msk                /*!< privileged-only access permission for peripheral 21 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos     (22U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos)      /*!< 0x00400000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22         RIFSC_RISC_PRIVCFGRx_PRIV22_Msk                /*!< privileged-only access permission for peripheral 22 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos     (23U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos)      /*!< 0x00800000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23         RIFSC_RISC_PRIVCFGRx_PRIV23_Msk                /*!< privileged-only access permission for peripheral 23 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos     (24U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos)      /*!< 0x01000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24         RIFSC_RISC_PRIVCFGRx_PRIV24_Msk                /*!< privileged-only access permission for peripheral 24 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos     (25U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos)      /*!< 0x02000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25         RIFSC_RISC_PRIVCFGRx_PRIV25_Msk                /*!< privileged-only access permission for peripheral 25 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos     (26U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos)      /*!< 0x04000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26         RIFSC_RISC_PRIVCFGRx_PRIV26_Msk                /*!< privileged-only access permission for peripheral 26 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos     (27U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos)      /*!< 0x08000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27         RIFSC_RISC_PRIVCFGRx_PRIV27_Msk                /*!< privileged-only access permission for peripheral 27 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos     (28U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos)      /*!< 0x10000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28         RIFSC_RISC_PRIVCFGRx_PRIV28_Msk                /*!< privileged-only access permission for peripheral 28 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos     (29U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos)      /*!< 0x20000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29         RIFSC_RISC_PRIVCFGRx_PRIV29_Msk                /*!< privileged-only access permission for peripheral 29 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos     (30U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos)      /*!< 0x40000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30         RIFSC_RISC_PRIVCFGRx_PRIV30_Msk                /*!< privileged-only access permission for peripheral 30 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos     (31U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos)      /*!< 0x80000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31         RIFSC_RISC_PRIVCFGRx_PRIV31_Msk                /*!< privileged-only access permission for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_RCFGLOCKRx register  *************/
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos    (0U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos)     /*!< 0x00000001 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0        RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk               /*!< Resource lock for peripheral 0 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos    (1U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos)     /*!< 0x00000002 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1        RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk               /*!< Resource lock for peripheral 1 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos    (2U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos)     /*!< 0x00000004 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2        RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk               /*!< Resource lock for peripheral 2 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos    (3U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos)     /*!< 0x00000008 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3        RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk               /*!< Resource lock for peripheral 3 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos    (4U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos)     /*!< 0x00000010 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4        RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk               /*!< Resource lock for peripheral 4 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos    (5U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos)     /*!< 0x00000020 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5        RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk               /*!< Resource lock for peripheral 5 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos    (6U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos)     /*!< 0x00000040 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6        RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk               /*!< Resource lock for peripheral 6 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos    (7U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos)     /*!< 0x00000080 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7        RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk               /*!< Resource lock for peripheral 7 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos    (8U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos)     /*!< 0x00000100 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8        RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk               /*!< Resource lock for peripheral 8 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos    (9U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos)     /*!< 0x00000200 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9        RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk               /*!< Resource lock for peripheral 9 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos   (10U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos)    /*!< 0x00000400 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10       RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk              /*!< Resource lock for peripheral 10 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos   (11U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos)    /*!< 0x00000800 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11       RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk              /*!< Resource lock for peripheral 11 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos   (12U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos)    /*!< 0x00001000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12       RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk              /*!< Resource lock for peripheral 12 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos   (13U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos)    /*!< 0x00002000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13       RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk              /*!< Resource lock for peripheral 13 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos   (14U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos)    /*!< 0x00004000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14       RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk              /*!< Resource lock for peripheral 14 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos   (15U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos)    /*!< 0x00008000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15       RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk              /*!< Resource lock for peripheral 15 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos   (16U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos)    /*!< 0x00010000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16       RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk              /*!< Resource lock for peripheral 16 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos   (17U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos)    /*!< 0x00020000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17       RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk              /*!< Resource lock for peripheral 17 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos   (18U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos)    /*!< 0x00040000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18       RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk              /*!< Resource lock for peripheral 18 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos   (19U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos)    /*!< 0x00080000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19       RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk              /*!< Resource lock for peripheral 19 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos   (20U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos)    /*!< 0x00100000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20       RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk              /*!< Resource lock for peripheral 20 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos   (21U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos)    /*!< 0x00200000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21       RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk              /*!< Resource lock for peripheral 21 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos   (22U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos)    /*!< 0x00400000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22       RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk              /*!< Resource lock for peripheral 22 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos   (23U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos)    /*!< 0x00800000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23       RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk              /*!< Resource lock for peripheral 23 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos   (24U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos)    /*!< 0x01000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24       RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk              /*!< Resource lock for peripheral 24 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos   (25U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos)    /*!< 0x02000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25       RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk              /*!< Resource lock for peripheral 25 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos   (26U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos)    /*!< 0x04000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26       RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk              /*!< Resource lock for peripheral 26 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos   (27U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos)    /*!< 0x08000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27       RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk              /*!< Resource lock for peripheral 27 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos   (28U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos)    /*!< 0x10000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28       RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk              /*!< Resource lock for peripheral 28 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos   (29U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos)    /*!< 0x20000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29       RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk              /*!< Resource lock for peripheral 29 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos   (30U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos)    /*!< 0x40000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30       RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk              /*!< Resource lock for peripheral 30 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos   (31U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos)    /*!< 0x80000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31       RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk              /*!< Resource lock for peripheral 31 */
+
+/****************  Bit definition for RIFSC_RIMC_CR register  *****************/
+#define RIFSC_RIMC_CR_GLOCK_Pos             (0U)
+#define RIFSC_RIMC_CR_GLOCK_Msk             (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos)              /*!< 0x00000001 */
+#define RIFSC_RIMC_CR_GLOCK                 RIFSC_RIMC_CR_GLOCK_Msk                        /*!< Global lock */
+#define RIFSC_RIMC_CR_DAPCID_Pos            (8U)
+#define RIFSC_RIMC_CR_DAPCID_Msk            (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000700 */
+#define RIFSC_RIMC_CR_DAPCID                RIFSC_RIMC_CR_DAPCID_Msk                       /*!< Debug access port compartment ID */
+#define RIFSC_RIMC_CR_DAPCID_0              (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000100 */
+#define RIFSC_RIMC_CR_DAPCID_1              (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000200 */
+#define RIFSC_RIMC_CR_DAPCID_2              (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000400 */
+
+/***************  Bit definition for RIFSC_RIMC_ATTRx register  ***************/
+#define RIFSC_RIMC_ATTRx_MCID_Pos           (4U)
+#define RIFSC_RIMC_ATTRx_MCID_Msk           (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000070 */
+#define RIFSC_RIMC_ATTRx_MCID               RIFSC_RIMC_ATTRx_MCID_Msk                      /*!< Master CID */
+#define RIFSC_RIMC_ATTRx_MCID_0             (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000010 */
+#define RIFSC_RIMC_ATTRx_MCID_1             (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000020 */
+#define RIFSC_RIMC_ATTRx_MCID_2             (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000040 */
+#define RIFSC_RIMC_ATTRx_MSEC_Pos           (8U)
+#define RIFSC_RIMC_ATTRx_MSEC_Msk           (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos)            /*!< 0x00000100 */
+#define RIFSC_RIMC_ATTRx_MSEC               RIFSC_RIMC_ATTRx_MSEC_Msk                      /*!< Master secure */
+#define RIFSC_RIMC_ATTRx_MPRIV_Pos          (9U)
+#define RIFSC_RIMC_ATTRx_MPRIV_Msk          (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos)           /*!< 0x00000200 */
+#define RIFSC_RIMC_ATTRx_MPRIV              RIFSC_RIMC_ATTRx_MPRIV_Msk                     /*!< Master privileged */
+
+/******************************************************************************/
+/*                                                                            */
+/*     Resource Isolation Slave unit for Address space protection (RISAF)     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RISAF_CR register  *******************/
+#define RISAF_CR_GLOCK_Pos                 (0U)
+#define RISAF_CR_GLOCK_Msk                 (0x1UL << RISAF_CR_GLOCK_Pos)                      /*!< 0x00000001 */
+#define RISAF_CR_GLOCK                     RISAF_CR_GLOCK_Msk                                /*!< Global lock */
+
+/******************  Bit definition for RISAF_IASR register  ******************/
+#define RISAF_IASR_CAEF_Pos                (0U)
+#define RISAF_IASR_CAEF_Msk                (0x1UL << RISAF_IASR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IASR_CAEF                    RISAF_IASR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IASR_IAEF_Pos                (1U)
+#define RISAF_IASR_IAEF_Msk                (0x1UL << RISAF_IASR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IASR_IAEF                    RISAF_IASR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/******************  Bit definition for RISAF_IACR register  ******************/
+#define RISAF_IACR_CAEF_Pos                (0U)
+#define RISAF_IACR_CAEF_Msk                (0x1UL << RISAF_IACR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IACR_CAEF                    RISAF_IACR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IACR_IAEF_Pos                (1U)
+#define RISAF_IACR_IAEF_Msk                (0x1UL << RISAF_IACR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IACR_IAEF                    RISAF_IACR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/*****************  Bit definition for RISAF_IAESR register  *****************/
+#define RISAF_IAESR_IACID_Pos              (0U)
+#define RISAF_IAESR_IACID_Msk              (0x7UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000007 */
+#define RISAF_IAESR_IACID                  RISAF_IAESR_IACID_Msk                            /*!< Illegal access compartment ID */
+#define RISAF_IAESR_IACID_0                (0x1UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000001 */
+#define RISAF_IAESR_IACID_1                (0x2UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000002 */
+#define RISAF_IAESR_IACID_2                (0x4UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000004 */
+#define RISAF_IAESR_IAPRIV_Pos             (4U)
+#define RISAF_IAESR_IAPRIV_Msk             (0x1UL << RISAF_IAESR_IAPRIV_Pos)                 /*!< 0x00000010 */
+#define RISAF_IAESR_IAPRIV                 RISAF_IAESR_IAPRIV_Msk                           /*!< Illegal access privileged */
+#define RISAF_IAESR_IASEC_Pos              (5U)
+#define RISAF_IAESR_IASEC_Msk              (0x1UL << RISAF_IAESR_IASEC_Pos)                  /*!< 0x00000020 */
+#define RISAF_IAESR_IASEC                  RISAF_IAESR_IASEC_Msk                            /*!< Illegal access security */
+#define RISAF_IAESR_IANRW_Pos              (7U)
+#define RISAF_IAESR_IANRW_Msk              (0x1UL << RISAF_IAESR_IANRW_Pos)                  /*!< 0x00000080 */
+#define RISAF_IAESR_IANRW                  RISAF_IAESR_IANRW_Msk                            /*!< Illegal access read/write */
+
+/*****************  Bit definition for RISAF_IADDR register  *****************/
+#define RISAF_IADDR_IADD_Pos                (0U)
+#define RISAF_IADDR_IADD_Msk                (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos)            /*!< 0xFFFFFFFF */
+#define RISAF_IADDR_IADD                    RISAF_IADDR_IADD_Msk                             /*!< Illegal address */
+#define RISAF_IADDR_IADD_0                  (0x1UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000001 */
+#define RISAF_IADDR_IADD_1                  (0x2UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000002 */
+#define RISAF_IADDR_IADD_2                  (0x4UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000004 */
+#define RISAF_IADDR_IADD_3                  (0x8UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000008 */
+#define RISAF_IADDR_IADD_4                  (0x10UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000010 */
+#define RISAF_IADDR_IADD_5                  (0x20UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000020 */
+#define RISAF_IADDR_IADD_6                  (0x40UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000040 */
+#define RISAF_IADDR_IADD_7                  (0x80UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000080 */
+#define RISAF_IADDR_IADD_8                  (0x100UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000100 */
+#define RISAF_IADDR_IADD_9                  (0x200UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000200 */
+#define RISAF_IADDR_IADD_10                 (0x400UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000400 */
+#define RISAF_IADDR_IADD_11                 (0x800UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000800 */
+#define RISAF_IADDR_IADD_12                 (0x1000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00001000 */
+#define RISAF_IADDR_IADD_13                 (0x2000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00002000 */
+#define RISAF_IADDR_IADD_14                 (0x4000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00004000 */
+#define RISAF_IADDR_IADD_15                 (0x8000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00008000 */
+#define RISAF_IADDR_IADD_16                 (0x10000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00010000 */
+#define RISAF_IADDR_IADD_17                 (0x20000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00020000 */
+#define RISAF_IADDR_IADD_18                 (0x40000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00040000 */
+#define RISAF_IADDR_IADD_19                 (0x80000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00080000 */
+#define RISAF_IADDR_IADD_20                 (0x100000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00100000 */
+#define RISAF_IADDR_IADD_21                 (0x200000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00200000 */
+#define RISAF_IADDR_IADD_22                 (0x400000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00400000 */
+#define RISAF_IADDR_IADD_23                 (0x800000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00800000 */
+#define RISAF_IADDR_IADD_24                 (0x1000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x01000000 */
+#define RISAF_IADDR_IADD_25                 (0x2000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x02000000 */
+#define RISAF_IADDR_IADD_26                 (0x4000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x04000000 */
+#define RISAF_IADDR_IADD_27                 (0x8000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x08000000 */
+#define RISAF_IADDR_IADD_28                 (0x10000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x10000000 */
+#define RISAF_IADDR_IADD_29                 (0x20000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x20000000 */
+#define RISAF_IADDR_IADD_30                 (0x40000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x40000000 */
+#define RISAF_IADDR_IADD_31                 (0x80000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_CFGR register  ****************/
+#define RISAF_REGx_CFGR_BREN_Pos           (0U)
+#define RISAF_REGx_CFGR_BREN_Msk           (0x1UL << RISAF_REGx_CFGR_BREN_Pos)                /*!< 0x00000001 */
+#define RISAF_REGx_CFGR_BREN               RISAF_REGx_CFGR_BREN_Msk                          /*!< Base region enable */
+#define RISAF_REGx_CFGR_SEC_Pos            (8U)
+#define RISAF_REGx_CFGR_SEC_Msk            (0x1UL << RISAF_REGx_CFGR_SEC_Pos)                 /*!< 0x00000100 */
+#define RISAF_REGx_CFGR_SEC                RISAF_REGx_CFGR_SEC_Msk                           /*!< Secure region */
+#define RISAF_REGx_CFGR_PRIVC0_Pos         (16U)
+#define RISAF_REGx_CFGR_PRIVC0_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos)              /*!< 0x00010000 */
+#define RISAF_REGx_CFGR_PRIVC0             RISAF_REGx_CFGR_PRIVC0_Msk                        /*!< Privileged access for compartment 0 */
+#define RISAF_REGx_CFGR_PRIVC1_Pos         (17U)
+#define RISAF_REGx_CFGR_PRIVC1_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos)              /*!< 0x00020000 */
+#define RISAF_REGx_CFGR_PRIVC1             RISAF_REGx_CFGR_PRIVC1_Msk                        /*!< Privileged access for compartment 1 */
+#define RISAF_REGx_CFGR_PRIVC2_Pos         (18U)
+#define RISAF_REGx_CFGR_PRIVC2_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos)              /*!< 0x00040000 */
+#define RISAF_REGx_CFGR_PRIVC2             RISAF_REGx_CFGR_PRIVC2_Msk                        /*!< Privileged access for compartment 2 */
+#define RISAF_REGx_CFGR_PRIVC3_Pos         (19U)
+#define RISAF_REGx_CFGR_PRIVC3_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos)              /*!< 0x00080000 */
+#define RISAF_REGx_CFGR_PRIVC3             RISAF_REGx_CFGR_PRIVC3_Msk                        /*!< Privileged access for compartment 3 */
+#define RISAF_REGx_CFGR_PRIVC4_Pos         (20U)
+#define RISAF_REGx_CFGR_PRIVC4_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos)              /*!< 0x00100000 */
+#define RISAF_REGx_CFGR_PRIVC4             RISAF_REGx_CFGR_PRIVC4_Msk                        /*!< Privileged access for compartment 4 */
+#define RISAF_REGx_CFGR_PRIVC5_Pos         (21U)
+#define RISAF_REGx_CFGR_PRIVC5_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos)              /*!< 0x00200000 */
+#define RISAF_REGx_CFGR_PRIVC5             RISAF_REGx_CFGR_PRIVC5_Msk                        /*!< Privileged access for compartment 5 */
+#define RISAF_REGx_CFGR_PRIVC6_Pos         (22U)
+#define RISAF_REGx_CFGR_PRIVC6_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos)              /*!< 0x00400000 */
+#define RISAF_REGx_CFGR_PRIVC6             RISAF_REGx_CFGR_PRIVC6_Msk                        /*!< Privileged access for compartment 6 */
+#define RISAF_REGx_CFGR_PRIVC7_Pos         (23U)
+#define RISAF_REGx_CFGR_PRIVC7_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos)              /*!< 0x00800000 */
+#define RISAF_REGx_CFGR_PRIVC7             RISAF_REGx_CFGR_PRIVC7_Msk                        /*!< Privileged access for compartment 7 */
+
+/**************  Bit definition for RISAF_REGx_STARTR register  ***************/
+#define RISAF_REGx_STARTR_BADDSTART_Pos    (0U)
+#define RISAF_REGx_STARTR_BADDSTART_Msk    (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0xFFFFFFFF */
+#define RISAF_REGx_STARTR_BADDSTART        RISAF_REGx_STARTR_BADDSTART_Msk                   /*!< Base region address start */
+#define RISAF_REGx_STARTR_BADDSTART_0      (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000001 */
+#define RISAF_REGx_STARTR_BADDSTART_1      (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000002 */
+#define RISAF_REGx_STARTR_BADDSTART_2      (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000004 */
+#define RISAF_REGx_STARTR_BADDSTART_3      (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000008 */
+#define RISAF_REGx_STARTR_BADDSTART_4      (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000010 */
+#define RISAF_REGx_STARTR_BADDSTART_5      (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000020 */
+#define RISAF_REGx_STARTR_BADDSTART_6      (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000040 */
+#define RISAF_REGx_STARTR_BADDSTART_7      (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000080 */
+#define RISAF_REGx_STARTR_BADDSTART_8      (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000100 */
+#define RISAF_REGx_STARTR_BADDSTART_9      (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000200 */
+#define RISAF_REGx_STARTR_BADDSTART_10     (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000400 */
+#define RISAF_REGx_STARTR_BADDSTART_11     (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000800 */
+#define RISAF_REGx_STARTR_BADDSTART_12     (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00001000 */
+#define RISAF_REGx_STARTR_BADDSTART_13     (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00002000 */
+#define RISAF_REGx_STARTR_BADDSTART_14     (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00004000 */
+#define RISAF_REGx_STARTR_BADDSTART_15     (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00008000 */
+#define RISAF_REGx_STARTR_BADDSTART_16     (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00010000 */
+#define RISAF_REGx_STARTR_BADDSTART_17     (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00020000 */
+#define RISAF_REGx_STARTR_BADDSTART_18     (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00040000 */
+#define RISAF_REGx_STARTR_BADDSTART_19     (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00080000 */
+#define RISAF_REGx_STARTR_BADDSTART_20     (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00100000 */
+#define RISAF_REGx_STARTR_BADDSTART_21     (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00200000 */
+#define RISAF_REGx_STARTR_BADDSTART_22     (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00400000 */
+#define RISAF_REGx_STARTR_BADDSTART_23     (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00800000 */
+#define RISAF_REGx_STARTR_BADDSTART_24     (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x01000000 */
+#define RISAF_REGx_STARTR_BADDSTART_25     (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x02000000 */
+#define RISAF_REGx_STARTR_BADDSTART_26     (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x04000000 */
+#define RISAF_REGx_STARTR_BADDSTART_27     (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x08000000 */
+#define RISAF_REGx_STARTR_BADDSTART_28     (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x10000000 */
+#define RISAF_REGx_STARTR_BADDSTART_29     (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x20000000 */
+#define RISAF_REGx_STARTR_BADDSTART_30     (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x40000000 */
+#define RISAF_REGx_STARTR_BADDSTART_31     (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_ENDR register  ****************/
+#define RISAF_REGx_ENDR_BADDEND_Pos        (0U)
+#define RISAF_REGx_ENDR_BADDEND_Msk        (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0xFFFFFFFF */
+#define RISAF_REGx_ENDR_BADDEND            RISAF_REGx_ENDR_BADDEND_Msk                       /*!< Base region address end */
+#define RISAF_REGx_ENDR_BADDEND_0          (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000001 */
+#define RISAF_REGx_ENDR_BADDEND_1          (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000002 */
+#define RISAF_REGx_ENDR_BADDEND_2          (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000004 */
+#define RISAF_REGx_ENDR_BADDEND_3          (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000008 */
+#define RISAF_REGx_ENDR_BADDEND_4          (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000010 */
+#define RISAF_REGx_ENDR_BADDEND_5          (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000020 */
+#define RISAF_REGx_ENDR_BADDEND_6          (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000040 */
+#define RISAF_REGx_ENDR_BADDEND_7          (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000080 */
+#define RISAF_REGx_ENDR_BADDEND_8          (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000100 */
+#define RISAF_REGx_ENDR_BADDEND_9          (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000200 */
+#define RISAF_REGx_ENDR_BADDEND_10         (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000400 */
+#define RISAF_REGx_ENDR_BADDEND_11         (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000800 */
+#define RISAF_REGx_ENDR_BADDEND_12         (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00001000 */
+#define RISAF_REGx_ENDR_BADDEND_13         (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00002000 */
+#define RISAF_REGx_ENDR_BADDEND_14         (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00004000 */
+#define RISAF_REGx_ENDR_BADDEND_15         (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00008000 */
+#define RISAF_REGx_ENDR_BADDEND_16         (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00010000 */
+#define RISAF_REGx_ENDR_BADDEND_17         (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00020000 */
+#define RISAF_REGx_ENDR_BADDEND_18         (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00040000 */
+#define RISAF_REGx_ENDR_BADDEND_19         (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00080000 */
+#define RISAF_REGx_ENDR_BADDEND_20         (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00100000 */
+#define RISAF_REGx_ENDR_BADDEND_21         (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00200000 */
+#define RISAF_REGx_ENDR_BADDEND_22         (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00400000 */
+#define RISAF_REGx_ENDR_BADDEND_23         (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00800000 */
+#define RISAF_REGx_ENDR_BADDEND_24         (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x01000000 */
+#define RISAF_REGx_ENDR_BADDEND_25         (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x02000000 */
+#define RISAF_REGx_ENDR_BADDEND_26         (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x04000000 */
+#define RISAF_REGx_ENDR_BADDEND_27         (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x08000000 */
+#define RISAF_REGx_ENDR_BADDEND_28         (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x10000000 */
+#define RISAF_REGx_ENDR_BADDEND_29         (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x20000000 */
+#define RISAF_REGx_ENDR_BADDEND_30         (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x40000000 */
+#define RISAF_REGx_ENDR_BADDEND_31         (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_CIDCFGR register  **************/
+#define RISAF_REGx_CIDCFGR_RDENC0_Pos      (0U)
+#define RISAF_REGx_CIDCFGR_RDENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos)           /*!< 0x00000001 */
+#define RISAF_REGx_CIDCFGR_RDENC0          RISAF_REGx_CIDCFGR_RDENC0_Msk                     /*!< Read enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_RDENC1_Pos      (1U)
+#define RISAF_REGx_CIDCFGR_RDENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos)           /*!< 0x00000002 */
+#define RISAF_REGx_CIDCFGR_RDENC1          RISAF_REGx_CIDCFGR_RDENC1_Msk                     /*!< Read enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_RDENC2_Pos      (2U)
+#define RISAF_REGx_CIDCFGR_RDENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos)           /*!< 0x00000004 */
+#define RISAF_REGx_CIDCFGR_RDENC2          RISAF_REGx_CIDCFGR_RDENC2_Msk                     /*!< Read enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_RDENC3_Pos      (3U)
+#define RISAF_REGx_CIDCFGR_RDENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos)           /*!< 0x00000008 */
+#define RISAF_REGx_CIDCFGR_RDENC3          RISAF_REGx_CIDCFGR_RDENC3_Msk                     /*!< Read enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_RDENC4_Pos      (4U)
+#define RISAF_REGx_CIDCFGR_RDENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_CIDCFGR_RDENC4          RISAF_REGx_CIDCFGR_RDENC4_Msk                     /*!< Read enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_RDENC5_Pos      (5U)
+#define RISAF_REGx_CIDCFGR_RDENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_CIDCFGR_RDENC5          RISAF_REGx_CIDCFGR_RDENC5_Msk                     /*!< Read enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_RDENC6_Pos      (6U)
+#define RISAF_REGx_CIDCFGR_RDENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_CIDCFGR_RDENC6          RISAF_REGx_CIDCFGR_RDENC6_Msk                     /*!< Read enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_RDENC7_Pos      (7U)
+#define RISAF_REGx_CIDCFGR_RDENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_CIDCFGR_RDENC7          RISAF_REGx_CIDCFGR_RDENC7_Msk                     /*!< Read enable for compartment 7 */
+#define RISAF_REGx_CIDCFGR_WRENC0_Pos      (16U)
+#define RISAF_REGx_CIDCFGR_WRENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos)           /*!< 0x00010000 */
+#define RISAF_REGx_CIDCFGR_WRENC0          RISAF_REGx_CIDCFGR_WRENC0_Msk                     /*!< Write enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_WRENC1_Pos      (17U)
+#define RISAF_REGx_CIDCFGR_WRENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos)           /*!< 0x00020000 */
+#define RISAF_REGx_CIDCFGR_WRENC1          RISAF_REGx_CIDCFGR_WRENC1_Msk                     /*!< Write enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_WRENC2_Pos      (18U)
+#define RISAF_REGx_CIDCFGR_WRENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos)           /*!< 0x00040000 */
+#define RISAF_REGx_CIDCFGR_WRENC2          RISAF_REGx_CIDCFGR_WRENC2_Msk                     /*!< Write enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_WRENC3_Pos      (19U)
+#define RISAF_REGx_CIDCFGR_WRENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos)           /*!< 0x00080000 */
+#define RISAF_REGx_CIDCFGR_WRENC3          RISAF_REGx_CIDCFGR_WRENC3_Msk                     /*!< Write enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_WRENC4_Pos      (20U)
+#define RISAF_REGx_CIDCFGR_WRENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos)           /*!< 0x00100000 */
+#define RISAF_REGx_CIDCFGR_WRENC4          RISAF_REGx_CIDCFGR_WRENC4_Msk                     /*!< Write enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_WRENC5_Pos      (21U)
+#define RISAF_REGx_CIDCFGR_WRENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos)           /*!< 0x00200000 */
+#define RISAF_REGx_CIDCFGR_WRENC5          RISAF_REGx_CIDCFGR_WRENC5_Msk                     /*!< Write enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_WRENC6_Pos      (22U)
+#define RISAF_REGx_CIDCFGR_WRENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos)           /*!< 0x00400000 */
+#define RISAF_REGx_CIDCFGR_WRENC6          RISAF_REGx_CIDCFGR_WRENC6_Msk                     /*!< Write enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_WRENC7_Pos      (23U)
+#define RISAF_REGx_CIDCFGR_WRENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos)           /*!< 0x00800000 */
+#define RISAF_REGx_CIDCFGR_WRENC7          RISAF_REGx_CIDCFGR_WRENC7_Msk                     /*!< Write enable for compartment 7 */
+
+/***************  Bit definition for RISAF_REGx_zCFGR register  ***************/
+#define RISAF_REGx_zCFGR_SREN_Pos          (0U)
+#define RISAF_REGx_zCFGR_SREN_Msk          (0x1UL << RISAF_REGx_zCFGR_SREN_Pos)               /*!< 0x00000001 */
+#define RISAF_REGx_zCFGR_SREN              RISAF_REGx_zCFGR_SREN_Msk                         /*!< Subregion enable */
+#define RISAF_REGx_zCFGR_RLOCK_Pos         (1U)
+#define RISAF_REGx_zCFGR_RLOCK_Msk         (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos)              /*!< 0x00000002 */
+#define RISAF_REGx_zCFGR_RLOCK             RISAF_REGx_zCFGR_RLOCK_Msk                        /*!< Resource lock */
+#define RISAF_REGx_zCFGR_SRCID_Pos         (4U)
+#define RISAF_REGx_zCFGR_SRCID_Msk         (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000070 */
+#define RISAF_REGx_zCFGR_SRCID             RISAF_REGx_zCFGR_SRCID_Msk                        /*!< Subregion CID */
+#define RISAF_REGx_zCFGR_SRCID_0           (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000010 */
+#define RISAF_REGx_zCFGR_SRCID_1           (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000020 */
+#define RISAF_REGx_zCFGR_SRCID_2           (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000040 */
+#define RISAF_REGx_zCFGR_SEC_Pos           (8U)
+#define RISAF_REGx_zCFGR_SEC_Msk           (0x1UL << RISAF_REGx_zCFGR_SEC_Pos)                /*!< 0x00000100 */
+#define RISAF_REGx_zCFGR_SEC               RISAF_REGx_zCFGR_SEC_Msk                          /*!< Secure subregion */
+#define RISAF_REGx_zCFGR_PRIV_Pos          (9U)
+#define RISAF_REGx_zCFGR_PRIV_Msk          (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos)               /*!< 0x00000200 */
+#define RISAF_REGx_zCFGR_PRIV              RISAF_REGx_zCFGR_PRIV_Msk                         /*!< Privileged subregion */
+#define RISAF_REGx_zCFGR_RDEN_Pos          (12U)
+#define RISAF_REGx_zCFGR_RDEN_Msk          (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos)               /*!< 0x00001000 */
+#define RISAF_REGx_zCFGR_RDEN              RISAF_REGx_zCFGR_RDEN_Msk                         /*!< Read enable */
+#define RISAF_REGx_zCFGR_WREN_Pos          (13U)
+#define RISAF_REGx_zCFGR_WREN_Msk          (0x1UL << RISAF_REGx_zCFGR_WREN_Pos)               /*!< 0x00002000 */
+#define RISAF_REGx_zCFGR_WREN              RISAF_REGx_zCFGR_WREN_Msk                         /*!< Write enable */
+
+/**************  Bit definition for RISAF_REGx_zSTARTR register  **************/
+#define RISAF_REGx_zSTARTR_SADDSTART_Pos   (0U)
+#define RISAF_REGx_zSTARTR_SADDSTART_Msk   (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zSTARTR_SADDSTART       RISAF_REGx_zSTARTR_SADDSTART_Msk                  /*!< Subregion address start */
+#define RISAF_REGx_zSTARTR_SADDSTART_0     (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000001 */
+#define RISAF_REGx_zSTARTR_SADDSTART_1     (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000002 */
+#define RISAF_REGx_zSTARTR_SADDSTART_2     (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000004 */
+#define RISAF_REGx_zSTARTR_SADDSTART_3     (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000008 */
+#define RISAF_REGx_zSTARTR_SADDSTART_4     (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000010 */
+#define RISAF_REGx_zSTARTR_SADDSTART_5     (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000020 */
+#define RISAF_REGx_zSTARTR_SADDSTART_6     (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000040 */
+#define RISAF_REGx_zSTARTR_SADDSTART_7     (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000080 */
+#define RISAF_REGx_zSTARTR_SADDSTART_8     (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000100 */
+#define RISAF_REGx_zSTARTR_SADDSTART_9     (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000200 */
+#define RISAF_REGx_zSTARTR_SADDSTART_10    (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000400 */
+#define RISAF_REGx_zSTARTR_SADDSTART_11    (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000800 */
+#define RISAF_REGx_zSTARTR_SADDSTART_12    (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00001000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_13    (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00002000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_14    (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00004000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_15    (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00008000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_16    (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00010000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_17    (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00020000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_18    (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00040000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_19    (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00080000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_20    (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00100000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_21    (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00200000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_22    (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00400000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_23    (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00800000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_24    (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x01000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_25    (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x02000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_26    (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x04000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_27    (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x08000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_28    (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_29    (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_30    (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_31    (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_zENDR register  ***************/
+#define RISAF_REGx_zENDR_SADDEND_Pos       (0U)
+#define RISAF_REGx_zENDR_SADDEND_Msk       (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zENDR_SADDEND           RISAF_REGx_zENDR_SADDEND_Msk                      /*!< Subregion address end */
+#define RISAF_REGx_zENDR_SADDEND_0         (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000001 */
+#define RISAF_REGx_zENDR_SADDEND_1         (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000002 */
+#define RISAF_REGx_zENDR_SADDEND_2         (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000004 */
+#define RISAF_REGx_zENDR_SADDEND_3         (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000008 */
+#define RISAF_REGx_zENDR_SADDEND_4         (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_zENDR_SADDEND_5         (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_zENDR_SADDEND_6         (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_zENDR_SADDEND_7         (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_zENDR_SADDEND_8         (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000100 */
+#define RISAF_REGx_zENDR_SADDEND_9         (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000200 */
+#define RISAF_REGx_zENDR_SADDEND_10        (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000400 */
+#define RISAF_REGx_zENDR_SADDEND_11        (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000800 */
+#define RISAF_REGx_zENDR_SADDEND_12        (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00001000 */
+#define RISAF_REGx_zENDR_SADDEND_13        (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00002000 */
+#define RISAF_REGx_zENDR_SADDEND_14        (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00004000 */
+#define RISAF_REGx_zENDR_SADDEND_15        (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00008000 */
+#define RISAF_REGx_zENDR_SADDEND_16        (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00010000 */
+#define RISAF_REGx_zENDR_SADDEND_17        (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00020000 */
+#define RISAF_REGx_zENDR_SADDEND_18        (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00040000 */
+#define RISAF_REGx_zENDR_SADDEND_19        (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00080000 */
+#define RISAF_REGx_zENDR_SADDEND_20        (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00100000 */
+#define RISAF_REGx_zENDR_SADDEND_21        (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00200000 */
+#define RISAF_REGx_zENDR_SADDEND_22        (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00400000 */
+#define RISAF_REGx_zENDR_SADDEND_23        (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00800000 */
+#define RISAF_REGx_zENDR_SADDEND_24        (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x01000000 */
+#define RISAF_REGx_zENDR_SADDEND_25        (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x02000000 */
+#define RISAF_REGx_zENDR_SADDEND_26        (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x04000000 */
+#define RISAF_REGx_zENDR_SADDEND_27        (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x08000000 */
+#define RISAF_REGx_zENDR_SADDEND_28        (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x10000000 */
+#define RISAF_REGx_zENDR_SADDEND_29        (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x20000000 */
+#define RISAF_REGx_zENDR_SADDEND_30        (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x40000000 */
+#define RISAF_REGx_zENDR_SADDEND_31        (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_zNESTR register  ***************/
+#define RISAF_REGx_zNESTR_DCEN_Pos         (2U)
+#define RISAF_REGx_zNESTR_DCEN_Msk         (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos)              /*!< 0x00000004 */
+#define RISAF_REGx_zNESTR_DCEN             RISAF_REGx_zNESTR_DCEN_Msk                        /*!< Delegated configuration enable */
+#define RISAF_REGx_zNESTR_DCCID_Pos        (4U)
+#define RISAF_REGx_zNESTR_DCCID_Msk        (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000070 */
+#define RISAF_REGx_zNESTR_DCCID            RISAF_REGx_zNESTR_DCCID_Msk                       /*!< Delegated configuration CID */
+#define RISAF_REGx_zNESTR_DCCID_0          (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000010 */
+#define RISAF_REGx_zNESTR_DCCID_1          (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000020 */
+#define RISAF_REGx_zNESTR_DCCID_2          (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000040 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (IAC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IAC_IER0 register  *******************/
+#define IAC_IERx_IAIE0_Pos         (0U)
+#define IAC_IERx_IAIE0_Msk         (0x1UL << IAC_IERx_IAIE0_Pos)        /*!< 0x00000001 */
+#define IAC_IERx_IAIE0             IAC_IERx_IAIE0_Msk                  /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_IERx_IAIE1_Pos         (1U)
+#define IAC_IERx_IAIE1_Msk         (0x1UL << IAC_IERx_IAIE1_Pos)        /*!< 0x00000002 */
+#define IAC_IERx_IAIE1             IAC_IERx_IAIE1_Msk                  /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_IERx_IAIE2_Pos         (2U)
+#define IAC_IERx_IAIE2_Msk         (0x1UL << IAC_IERx_IAIE2_Pos)        /*!< 0x00000004 */
+#define IAC_IERx_IAIE2             IAC_IERx_IAIE2_Msk                  /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_IERx_IAIE3_Pos         (3U)
+#define IAC_IERx_IAIE3_Msk         (0x1UL << IAC_IERx_IAIE3_Pos)        /*!< 0x00000008 */
+#define IAC_IERx_IAIE3             IAC_IERx_IAIE3_Msk                  /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_IERx_IAIE4_Pos         (4U)
+#define IAC_IERx_IAIE4_Msk         (0x1UL << IAC_IERx_IAIE4_Pos)        /*!< 0x00000010 */
+#define IAC_IERx_IAIE4             IAC_IERx_IAIE4_Msk                  /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_IERx_IAIE5_Pos         (5U)
+#define IAC_IERx_IAIE5_Msk         (0x1UL << IAC_IERx_IAIE5_Pos)        /*!< 0x00000020 */
+#define IAC_IERx_IAIE5             IAC_IERx_IAIE5_Msk                  /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_IERx_IAIE6_Pos         (6U)
+#define IAC_IERx_IAIE6_Msk         (0x1UL << IAC_IERx_IAIE6_Pos)        /*!< 0x00000040 */
+#define IAC_IERx_IAIE6             IAC_IERx_IAIE6_Msk                  /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_IERx_IAIE7_Pos         (7U)
+#define IAC_IERx_IAIE7_Msk         (0x1UL << IAC_IERx_IAIE7_Pos)        /*!< 0x00000080 */
+#define IAC_IERx_IAIE7             IAC_IERx_IAIE7_Msk                  /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_IERx_IAIE8_Pos         (8U)
+#define IAC_IERx_IAIE8_Msk         (0x1UL << IAC_IERx_IAIE8_Pos)        /*!< 0x00000100 */
+#define IAC_IERx_IAIE8             IAC_IERx_IAIE8_Msk                  /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_IERx_IAIE9_Pos         (9U)
+#define IAC_IERx_IAIE9_Msk         (0x1UL << IAC_IERx_IAIE9_Pos)        /*!< 0x00000200 */
+#define IAC_IERx_IAIE9             IAC_IERx_IAIE9_Msk                  /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_IERx_IAIE10_Pos        (10U)
+#define IAC_IERx_IAIE10_Msk        (0x1UL << IAC_IERx_IAIE10_Pos)       /*!< 0x00000400 */
+#define IAC_IERx_IAIE10            IAC_IERx_IAIE10_Msk                 /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_IERx_IAIE11_Pos        (11U)
+#define IAC_IERx_IAIE11_Msk        (0x1UL << IAC_IERx_IAIE11_Pos)       /*!< 0x00000800 */
+#define IAC_IERx_IAIE11            IAC_IERx_IAIE11_Msk                 /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_IERx_IAIE12_Pos        (12U)
+#define IAC_IERx_IAIE12_Msk        (0x1UL << IAC_IERx_IAIE12_Pos)       /*!< 0x00001000 */
+#define IAC_IERx_IAIE12            IAC_IERx_IAIE12_Msk                 /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_IERx_IAIE13_Pos        (13U)
+#define IAC_IERx_IAIE13_Msk        (0x1UL << IAC_IERx_IAIE13_Pos)       /*!< 0x00002000 */
+#define IAC_IERx_IAIE13            IAC_IERx_IAIE13_Msk                 /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_IERx_IAIE14_Pos        (14U)
+#define IAC_IERx_IAIE14_Msk        (0x1UL << IAC_IERx_IAIE14_Pos)       /*!< 0x00004000 */
+#define IAC_IERx_IAIE14            IAC_IERx_IAIE14_Msk                 /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_IERx_IAIE15_Pos        (15U)
+#define IAC_IERx_IAIE15_Msk        (0x1UL << IAC_IERx_IAIE15_Pos)       /*!< 0x00008000 */
+#define IAC_IERx_IAIE15            IAC_IERx_IAIE15_Msk                 /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_IERx_IAIE16_Pos        (16U)
+#define IAC_IERx_IAIE16_Msk        (0x1UL << IAC_IERx_IAIE16_Pos)       /*!< 0x00010000 */
+#define IAC_IERx_IAIE16            IAC_IERx_IAIE16_Msk                 /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_IERx_IAIE17_Pos        (17U)
+#define IAC_IERx_IAIE17_Msk        (0x1UL << IAC_IERx_IAIE17_Pos)       /*!< 0x00020000 */
+#define IAC_IERx_IAIE17            IAC_IERx_IAIE17_Msk                 /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_IERx_IAIE18_Pos        (18U)
+#define IAC_IERx_IAIE18_Msk        (0x1UL << IAC_IERx_IAIE18_Pos)       /*!< 0x00040000 */
+#define IAC_IERx_IAIE18            IAC_IERx_IAIE18_Msk                 /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_IERx_IAIE19_Pos        (19U)
+#define IAC_IERx_IAIE19_Msk        (0x1UL << IAC_IERx_IAIE19_Pos)       /*!< 0x00080000 */
+#define IAC_IERx_IAIE19            IAC_IERx_IAIE19_Msk                 /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_IERx_IAIE20_Pos        (20U)
+#define IAC_IERx_IAIE20_Msk        (0x1UL << IAC_IERx_IAIE20_Pos)       /*!< 0x00100000 */
+#define IAC_IERx_IAIE20            IAC_IERx_IAIE20_Msk                 /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_IERx_IAIE21_Pos        (21U)
+#define IAC_IERx_IAIE21_Msk        (0x1UL << IAC_IERx_IAIE21_Pos)       /*!< 0x00200000 */
+#define IAC_IERx_IAIE21            IAC_IERx_IAIE21_Msk                 /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_IERx_IAIE22_Pos        (22U)
+#define IAC_IERx_IAIE22_Msk        (0x1UL << IAC_IERx_IAIE22_Pos)       /*!< 0x00400000 */
+#define IAC_IERx_IAIE22            IAC_IERx_IAIE22_Msk                 /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_IERx_IAIE23_Pos        (23U)
+#define IAC_IERx_IAIE23_Msk        (0x1UL << IAC_IERx_IAIE23_Pos)       /*!< 0x00800000 */
+#define IAC_IERx_IAIE23            IAC_IERx_IAIE23_Msk                 /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_IERx_IAIE24_Pos        (24U)
+#define IAC_IERx_IAIE24_Msk        (0x1UL << IAC_IERx_IAIE24_Pos)       /*!< 0x01000000 */
+#define IAC_IERx_IAIE24            IAC_IERx_IAIE24_Msk                 /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_IERx_IAIE25_Pos        (25U)
+#define IAC_IERx_IAIE25_Msk        (0x1UL << IAC_IERx_IAIE25_Pos)       /*!< 0x02000000 */
+#define IAC_IERx_IAIE25            IAC_IERx_IAIE25_Msk                 /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_IERx_IAIE26_Pos        (26U)
+#define IAC_IERx_IAIE26_Msk        (0x1UL << IAC_IERx_IAIE26_Pos)       /*!< 0x04000000 */
+#define IAC_IERx_IAIE26            IAC_IERx_IAIE26_Msk                 /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_IERx_IAIE27_Pos        (27U)
+#define IAC_IERx_IAIE27_Msk        (0x1UL << IAC_IERx_IAIE27_Pos)       /*!< 0x08000000 */
+#define IAC_IERx_IAIE27            IAC_IERx_IAIE27_Msk                 /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_IERx_IAIE28_Pos        (28U)
+#define IAC_IERx_IAIE28_Msk        (0x1UL << IAC_IERx_IAIE28_Pos)       /*!< 0x10000000 */
+#define IAC_IERx_IAIE28            IAC_IERx_IAIE28_Msk                 /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_IERx_IAIE29_Pos        (29U)
+#define IAC_IERx_IAIE29_Msk        (0x1UL << IAC_IERx_IAIE29_Pos)       /*!< 0x20000000 */
+#define IAC_IERx_IAIE29            IAC_IERx_IAIE29_Msk                 /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_IERx_IAIE30_Pos        (30U)
+#define IAC_IERx_IAIE30_Msk        (0x1UL << IAC_IERx_IAIE30_Pos)       /*!< 0x40000000 */
+#define IAC_IERx_IAIE30            IAC_IERx_IAIE30_Msk                 /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_IERx_IAIE31_Pos        (31U)
+#define IAC_IERx_IAIE31_Msk        (0x1UL << IAC_IERx_IAIE31_Pos)       /*!< 0x80000000 */
+#define IAC_IERx_IAIE31            IAC_IERx_IAIE31_Msk                 /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ISRx register  *******************/
+#define IAC_ISRx_IAF0_Pos          (0U)
+#define IAC_ISRx_IAF0_Msk          (0x1UL << IAC_ISRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ISRx_IAF0              IAC_ISRx_IAF0_Msk                   /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_ISRx_IAF1_Pos          (1U)
+#define IAC_ISRx_IAF1_Msk          (0x1UL << IAC_ISRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ISRx_IAF1              IAC_ISRx_IAF1_Msk                   /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_ISRx_IAF2_Pos          (2U)
+#define IAC_ISRx_IAF2_Msk          (0x1UL << IAC_ISRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ISRx_IAF2              IAC_ISRx_IAF2_Msk                   /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_ISRx_IAF3_Pos          (3U)
+#define IAC_ISRx_IAF3_Msk          (0x1UL << IAC_ISRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ISRx_IAF3              IAC_ISRx_IAF3_Msk                   /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_ISRx_IAF4_Pos          (4U)
+#define IAC_ISRx_IAF4_Msk          (0x1UL << IAC_ISRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ISRx_IAF4              IAC_ISRx_IAF4_Msk                   /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_ISRx_IAF5_Pos          (5U)
+#define IAC_ISRx_IAF5_Msk          (0x1UL << IAC_ISRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ISRx_IAF5              IAC_ISRx_IAF5_Msk                   /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_ISRx_IAF6_Pos          (6U)
+#define IAC_ISRx_IAF6_Msk          (0x1UL << IAC_ISRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ISRx_IAF6              IAC_ISRx_IAF6_Msk                   /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_ISRx_IAF7_Pos          (7U)
+#define IAC_ISRx_IAF7_Msk          (0x1UL << IAC_ISRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ISRx_IAF7              IAC_ISRx_IAF7_Msk                   /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_ISRx_IAF8_Pos          (8U)
+#define IAC_ISRx_IAF8_Msk          (0x1UL << IAC_ISRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ISRx_IAF8              IAC_ISRx_IAF8_Msk                   /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_ISRx_IAF9_Pos          (9U)
+#define IAC_ISRx_IAF9_Msk          (0x1UL << IAC_ISRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ISRx_IAF9              IAC_ISRx_IAF9_Msk                   /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_ISRx_IAF10_Pos         (10U)
+#define IAC_ISRx_IAF10_Msk         (0x1UL << IAC_ISRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ISRx_IAF10             IAC_ISRx_IAF10_Msk                  /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_ISRx_IAF11_Pos         (11U)
+#define IAC_ISRx_IAF11_Msk         (0x1UL << IAC_ISRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ISRx_IAF11             IAC_ISRx_IAF11_Msk                  /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_ISRx_IAF12_Pos         (12U)
+#define IAC_ISRx_IAF12_Msk         (0x1UL << IAC_ISRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ISRx_IAF12             IAC_ISRx_IAF12_Msk                  /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_ISRx_IAF13_Pos         (13U)
+#define IAC_ISRx_IAF13_Msk         (0x1UL << IAC_ISRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ISRx_IAF13             IAC_ISRx_IAF13_Msk                  /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_ISRx_IAF14_Pos         (14U)
+#define IAC_ISRx_IAF14_Msk         (0x1UL << IAC_ISRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ISRx_IAF14             IAC_ISRx_IAF14_Msk                  /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_ISRx_IAF15_Pos         (15U)
+#define IAC_ISRx_IAF15_Msk         (0x1UL << IAC_ISRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ISRx_IAF15             IAC_ISRx_IAF15_Msk                  /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_ISRx_IAF16_Pos         (16U)
+#define IAC_ISRx_IAF16_Msk         (0x1UL << IAC_ISRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ISRx_IAF16             IAC_ISRx_IAF16_Msk                  /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_ISRx_IAF17_Pos         (17U)
+#define IAC_ISRx_IAF17_Msk         (0x1UL << IAC_ISRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ISRx_IAF17             IAC_ISRx_IAF17_Msk                  /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_ISRx_IAF18_Pos         (18U)
+#define IAC_ISRx_IAF18_Msk         (0x1UL << IAC_ISRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ISRx_IAF18             IAC_ISRx_IAF18_Msk                  /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_ISRx_IAF19_Pos         (19U)
+#define IAC_ISRx_IAF19_Msk         (0x1UL << IAC_ISRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ISRx_IAF19             IAC_ISRx_IAF19_Msk                  /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_ISRx_IAF20_Pos         (20U)
+#define IAC_ISRx_IAF20_Msk         (0x1UL << IAC_ISRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ISRx_IAF20             IAC_ISRx_IAF20_Msk                  /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_ISRx_IAF21_Pos         (21U)
+#define IAC_ISRx_IAF21_Msk         (0x1UL << IAC_ISRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ISRx_IAF21             IAC_ISRx_IAF21_Msk                  /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_ISRx_IAF22_Pos         (22U)
+#define IAC_ISRx_IAF22_Msk         (0x1UL << IAC_ISRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ISRx_IAF22             IAC_ISRx_IAF22_Msk                  /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_ISRx_IAF23_Pos         (23U)
+#define IAC_ISRx_IAF23_Msk         (0x1UL << IAC_ISRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ISRx_IAF23             IAC_ISRx_IAF23_Msk                  /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_ISRx_IAF24_Pos         (24U)
+#define IAC_ISRx_IAF24_Msk         (0x1UL << IAC_ISRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ISRx_IAF24             IAC_ISRx_IAF24_Msk                  /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_ISRx_IAF25_Pos         (25U)
+#define IAC_ISRx_IAF25_Msk         (0x1UL << IAC_ISRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ISRx_IAF25             IAC_ISRx_IAF25_Msk                  /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_ISRx_IAF26_Pos         (26U)
+#define IAC_ISRx_IAF26_Msk         (0x1UL << IAC_ISRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ISRx_IAF26             IAC_ISRx_IAF26_Msk                  /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_ISRx_IAF27_Pos         (27U)
+#define IAC_ISRx_IAF27_Msk         (0x1UL << IAC_ISRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ISRx_IAF27             IAC_ISRx_IAF27_Msk                  /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_ISRx_IAF28_Pos         (28U)
+#define IAC_ISRx_IAF28_Msk         (0x1UL << IAC_ISRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ISRx_IAF28             IAC_ISRx_IAF28_Msk                  /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_ISRx_IAF29_Pos         (29U)
+#define IAC_ISRx_IAF29_Msk         (0x1UL << IAC_ISRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ISRx_IAF29             IAC_ISRx_IAF29_Msk                  /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_ISRx_IAF30_Pos         (30U)
+#define IAC_ISRx_IAF30_Msk         (0x1UL << IAC_ISRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ISRx_IAF30             IAC_ISRx_IAF30_Msk                  /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_ISRx_IAF31_Pos         (31U)
+#define IAC_ISRx_IAF31_Msk         (0x1UL << IAC_ISRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ISRx_IAF31             IAC_ISRx_IAF31_Msk                  /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ICRx register  *******************/
+#define IAC_ICRx_IAF0_Pos          (0U)
+#define IAC_ICRx_IAF0_Msk          (0x1UL << IAC_ICRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ICRx_IAF0              IAC_ICRx_IAF0_Msk                   /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */
+#define IAC_ICRx_IAF1_Pos          (1U)
+#define IAC_ICRx_IAF1_Msk          (0x1UL << IAC_ICRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ICRx_IAF1              IAC_ICRx_IAF1_Msk                   /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */
+#define IAC_ICRx_IAF2_Pos          (2U)
+#define IAC_ICRx_IAF2_Msk          (0x1UL << IAC_ICRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ICRx_IAF2              IAC_ICRx_IAF2_Msk                   /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */
+#define IAC_ICRx_IAF3_Pos          (3U)
+#define IAC_ICRx_IAF3_Msk          (0x1UL << IAC_ICRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ICRx_IAF3              IAC_ICRx_IAF3_Msk                   /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */
+#define IAC_ICRx_IAF4_Pos          (4U)
+#define IAC_ICRx_IAF4_Msk          (0x1UL << IAC_ICRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ICRx_IAF4              IAC_ICRx_IAF4_Msk                   /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */
+#define IAC_ICRx_IAF5_Pos          (5U)
+#define IAC_ICRx_IAF5_Msk          (0x1UL << IAC_ICRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ICRx_IAF5              IAC_ICRx_IAF5_Msk                   /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */
+#define IAC_ICRx_IAF6_Pos          (6U)
+#define IAC_ICRx_IAF6_Msk          (0x1UL << IAC_ICRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ICRx_IAF6              IAC_ICRx_IAF6_Msk                   /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */
+#define IAC_ICRx_IAF7_Pos          (7U)
+#define IAC_ICRx_IAF7_Msk          (0x1UL << IAC_ICRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ICRx_IAF7              IAC_ICRx_IAF7_Msk                   /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */
+#define IAC_ICRx_IAF8_Pos          (8U)
+#define IAC_ICRx_IAF8_Msk          (0x1UL << IAC_ICRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ICRx_IAF8              IAC_ICRx_IAF8_Msk                   /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */
+#define IAC_ICRx_IAF9_Pos          (9U)
+#define IAC_ICRx_IAF9_Msk          (0x1UL << IAC_ICRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ICRx_IAF9              IAC_ICRx_IAF9_Msk                   /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */
+#define IAC_ICRx_IAF10_Pos         (10U)
+#define IAC_ICRx_IAF10_Msk         (0x1UL << IAC_ICRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ICRx_IAF10             IAC_ICRx_IAF10_Msk                  /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */
+#define IAC_ICRx_IAF11_Pos         (11U)
+#define IAC_ICRx_IAF11_Msk         (0x1UL << IAC_ICRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ICRx_IAF11             IAC_ICRx_IAF11_Msk                  /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */
+#define IAC_ICRx_IAF12_Pos         (12U)
+#define IAC_ICRx_IAF12_Msk         (0x1UL << IAC_ICRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ICRx_IAF12             IAC_ICRx_IAF12_Msk                  /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */
+#define IAC_ICRx_IAF13_Pos         (13U)
+#define IAC_ICRx_IAF13_Msk         (0x1UL << IAC_ICRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ICRx_IAF13             IAC_ICRx_IAF13_Msk                  /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */
+#define IAC_ICRx_IAF14_Pos         (14U)
+#define IAC_ICRx_IAF14_Msk         (0x1UL << IAC_ICRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ICRx_IAF14             IAC_ICRx_IAF14_Msk                  /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */
+#define IAC_ICRx_IAF15_Pos         (15U)
+#define IAC_ICRx_IAF15_Msk         (0x1UL << IAC_ICRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ICRx_IAF15             IAC_ICRx_IAF15_Msk                  /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */
+#define IAC_ICRx_IAF16_Pos         (16U)
+#define IAC_ICRx_IAF16_Msk         (0x1UL << IAC_ICRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ICRx_IAF16             IAC_ICRx_IAF16_Msk                  /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */
+#define IAC_ICRx_IAF17_Pos         (17U)
+#define IAC_ICRx_IAF17_Msk         (0x1UL << IAC_ICRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ICRx_IAF17             IAC_ICRx_IAF17_Msk                  /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */
+#define IAC_ICRx_IAF18_Pos         (18U)
+#define IAC_ICRx_IAF18_Msk         (0x1UL << IAC_ICRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ICRx_IAF18             IAC_ICRx_IAF18_Msk                  /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */
+#define IAC_ICRx_IAF19_Pos         (19U)
+#define IAC_ICRx_IAF19_Msk         (0x1UL << IAC_ICRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ICRx_IAF19             IAC_ICRx_IAF19_Msk                  /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */
+#define IAC_ICRx_IAF20_Pos         (20U)
+#define IAC_ICRx_IAF20_Msk         (0x1UL << IAC_ICRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ICRx_IAF20             IAC_ICRx_IAF20_Msk                  /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */
+#define IAC_ICRx_IAF21_Pos         (21U)
+#define IAC_ICRx_IAF21_Msk         (0x1UL << IAC_ICRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ICRx_IAF21             IAC_ICRx_IAF21_Msk                  /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */
+#define IAC_ICRx_IAF22_Pos         (22U)
+#define IAC_ICRx_IAF22_Msk         (0x1UL << IAC_ICRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ICRx_IAF22             IAC_ICRx_IAF22_Msk                  /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */
+#define IAC_ICRx_IAF23_Pos         (23U)
+#define IAC_ICRx_IAF23_Msk         (0x1UL << IAC_ICRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ICRx_IAF23             IAC_ICRx_IAF23_Msk                  /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */
+#define IAC_ICRx_IAF24_Pos         (24U)
+#define IAC_ICRx_IAF24_Msk         (0x1UL << IAC_ICRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ICRx_IAF24             IAC_ICRx_IAF24_Msk                  /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */
+#define IAC_ICRx_IAF25_Pos         (25U)
+#define IAC_ICRx_IAF25_Msk         (0x1UL << IAC_ICRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ICRx_IAF25             IAC_ICRx_IAF25_Msk                  /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */
+#define IAC_ICRx_IAF26_Pos         (26U)
+#define IAC_ICRx_IAF26_Msk         (0x1UL << IAC_ICRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ICRx_IAF26             IAC_ICRx_IAF26_Msk                  /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */
+#define IAC_ICRx_IAF27_Pos         (27U)
+#define IAC_ICRx_IAF27_Msk         (0x1UL << IAC_ICRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ICRx_IAF27             IAC_ICRx_IAF27_Msk                  /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */
+#define IAC_ICRx_IAF28_Pos         (28U)
+#define IAC_ICRx_IAF28_Msk         (0x1UL << IAC_ICRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ICRx_IAF28             IAC_ICRx_IAF28_Msk                  /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */
+#define IAC_ICRx_IAF29_Pos         (29U)
+#define IAC_ICRx_IAF29_Msk         (0x1UL << IAC_ICRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ICRx_IAF29             IAC_ICRx_IAF29_Msk                  /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */
+#define IAC_ICRx_IAF30_Pos         (30U)
+#define IAC_ICRx_IAF30_Msk         (0x1UL << IAC_ICRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ICRx_IAF30             IAC_ICRx_IAF30_Msk                  /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */
+#define IAC_ICRx_IAF31_Pos         (31U)
+#define IAC_ICRx_IAF31_Msk         (0x1UL << IAC_ICRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ICRx_IAF31             IAC_ICRx_IAF31_Msk                  /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */
+
+/******************  Bit definition for IAC_IISRx register  *******************/
+#define IAC_IISRx_ILACIN0_Pos      (0U)
+#define IAC_IISRx_ILACIN0_Msk      (0x1UL << IAC_IISRx_ILACIN0_Pos)     /*!< 0x00000001 */
+#define IAC_IISRx_ILACIN0          IAC_IISRx_ILACIN0_Msk               /*!< illegal access input 0 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN1_Pos      (1U)
+#define IAC_IISRx_ILACIN1_Msk      (0x1UL << IAC_IISRx_ILACIN1_Pos)     /*!< 0x00000002 */
+#define IAC_IISRx_ILACIN1          IAC_IISRx_ILACIN1_Msk               /*!< illegal access input 1 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN2_Pos      (2U)
+#define IAC_IISRx_ILACIN2_Msk      (0x1UL << IAC_IISRx_ILACIN2_Pos)     /*!< 0x00000004 */
+#define IAC_IISRx_ILACIN2          IAC_IISRx_ILACIN2_Msk               /*!< illegal access input 2 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN3_Pos      (3U)
+#define IAC_IISRx_ILACIN3_Msk      (0x1UL << IAC_IISRx_ILACIN3_Pos)     /*!< 0x00000008 */
+#define IAC_IISRx_ILACIN3          IAC_IISRx_ILACIN3_Msk               /*!< illegal access input 3 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN4_Pos      (4U)
+#define IAC_IISRx_ILACIN4_Msk      (0x1UL << IAC_IISRx_ILACIN4_Pos)     /*!< 0x00000010 */
+#define IAC_IISRx_ILACIN4          IAC_IISRx_ILACIN4_Msk               /*!< illegal access input 4 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN5_Pos      (5U)
+#define IAC_IISRx_ILACIN5_Msk      (0x1UL << IAC_IISRx_ILACIN5_Pos)     /*!< 0x00000020 */
+#define IAC_IISRx_ILACIN5          IAC_IISRx_ILACIN5_Msk               /*!< illegal access input 5 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN6_Pos      (6U)
+#define IAC_IISRx_ILACIN6_Msk      (0x1UL << IAC_IISRx_ILACIN6_Pos)     /*!< 0x00000040 */
+#define IAC_IISRx_ILACIN6          IAC_IISRx_ILACIN6_Msk               /*!< illegal access input 6 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN7_Pos      (7U)
+#define IAC_IISRx_ILACIN7_Msk      (0x1UL << IAC_IISRx_ILACIN7_Pos)     /*!< 0x00000080 */
+#define IAC_IISRx_ILACIN7          IAC_IISRx_ILACIN7_Msk               /*!< illegal access input 7 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN8_Pos      (8U)
+#define IAC_IISRx_ILACIN8_Msk      (0x1UL << IAC_IISRx_ILACIN8_Pos)     /*!< 0x00000100 */
+#define IAC_IISRx_ILACIN8          IAC_IISRx_ILACIN8_Msk               /*!< illegal access input 8 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN9_Pos      (9U)
+#define IAC_IISRx_ILACIN9_Msk      (0x1UL << IAC_IISRx_ILACIN9_Pos)     /*!< 0x00000200 */
+#define IAC_IISRx_ILACIN9          IAC_IISRx_ILACIN9_Msk               /*!< illegal access input 9 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN10_Pos     (10U)
+#define IAC_IISRx_ILACIN10_Msk     (0x1UL << IAC_IISRx_ILACIN10_Pos)    /*!< 0x00000400 */
+#define IAC_IISRx_ILACIN10         IAC_IISRx_ILACIN10_Msk              /*!< illegal access input 10 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN11_Pos     (11U)
+#define IAC_IISRx_ILACIN11_Msk     (0x1UL << IAC_IISRx_ILACIN11_Pos)    /*!< 0x00000800 */
+#define IAC_IISRx_ILACIN11         IAC_IISRx_ILACIN11_Msk              /*!< illegal access input 11 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN12_Pos     (12U)
+#define IAC_IISRx_ILACIN12_Msk     (0x1UL << IAC_IISRx_ILACIN12_Pos)    /*!< 0x00001000 */
+#define IAC_IISRx_ILACIN12         IAC_IISRx_ILACIN12_Msk              /*!< illegal access input 12 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN13_Pos     (13U)
+#define IAC_IISRx_ILACIN13_Msk     (0x1UL << IAC_IISRx_ILACIN13_Pos)    /*!< 0x00002000 */
+#define IAC_IISRx_ILACIN13         IAC_IISRx_ILACIN13_Msk              /*!< illegal access input 13 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN14_Pos     (14U)
+#define IAC_IISRx_ILACIN14_Msk     (0x1UL << IAC_IISRx_ILACIN14_Pos)    /*!< 0x00004000 */
+#define IAC_IISRx_ILACIN14         IAC_IISRx_ILACIN14_Msk              /*!< illegal access input 14 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN15_Pos     (15U)
+#define IAC_IISRx_ILACIN15_Msk     (0x1UL << IAC_IISRx_ILACIN15_Pos)    /*!< 0x00008000 */
+#define IAC_IISRx_ILACIN15         IAC_IISRx_ILACIN15_Msk              /*!< illegal access input 15 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN16_Pos     (16U)
+#define IAC_IISRx_ILACIN16_Msk     (0x1UL << IAC_IISRx_ILACIN16_Pos)    /*!< 0x00010000 */
+#define IAC_IISRx_ILACIN16         IAC_IISRx_ILACIN16_Msk              /*!< illegal access input 16 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN17_Pos     (17U)
+#define IAC_IISRx_ILACIN17_Msk     (0x1UL << IAC_IISRx_ILACIN17_Pos)    /*!< 0x00020000 */
+#define IAC_IISRx_ILACIN17         IAC_IISRx_ILACIN17_Msk              /*!< illegal access input 17 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN18_Pos     (18U)
+#define IAC_IISRx_ILACIN18_Msk     (0x1UL << IAC_IISRx_ILACIN18_Pos)    /*!< 0x00040000 */
+#define IAC_IISRx_ILACIN18         IAC_IISRx_ILACIN18_Msk              /*!< illegal access input 18 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN19_Pos     (19U)
+#define IAC_IISRx_ILACIN19_Msk     (0x1UL << IAC_IISRx_ILACIN19_Pos)    /*!< 0x00080000 */
+#define IAC_IISRx_ILACIN19         IAC_IISRx_ILACIN19_Msk              /*!< illegal access input 19 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN20_Pos     (20U)
+#define IAC_IISRx_ILACIN20_Msk     (0x1UL << IAC_IISRx_ILACIN20_Pos)    /*!< 0x00100000 */
+#define IAC_IISRx_ILACIN20         IAC_IISRx_ILACIN20_Msk              /*!< illegal access input 20 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN21_Pos     (21U)
+#define IAC_IISRx_ILACIN21_Msk     (0x1UL << IAC_IISRx_ILACIN21_Pos)    /*!< 0x00200000 */
+#define IAC_IISRx_ILACIN21         IAC_IISRx_ILACIN21_Msk              /*!< illegal access input 21 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN22_Pos     (22U)
+#define IAC_IISRx_ILACIN22_Msk     (0x1UL << IAC_IISRx_ILACIN22_Pos)    /*!< 0x00400000 */
+#define IAC_IISRx_ILACIN22         IAC_IISRx_ILACIN22_Msk              /*!< illegal access input 22 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN23_Pos     (23U)
+#define IAC_IISRx_ILACIN23_Msk     (0x1UL << IAC_IISRx_ILACIN23_Pos)    /*!< 0x00800000 */
+#define IAC_IISRx_ILACIN23         IAC_IISRx_ILACIN23_Msk              /*!< illegal access input 23 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN24_Pos     (24U)
+#define IAC_IISRx_ILACIN24_Msk     (0x1UL << IAC_IISRx_ILACIN24_Pos)    /*!< 0x01000000 */
+#define IAC_IISRx_ILACIN24         IAC_IISRx_ILACIN24_Msk              /*!< illegal access input 24 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN25_Pos     (25U)
+#define IAC_IISRx_ILACIN25_Msk     (0x1UL << IAC_IISRx_ILACIN25_Pos)    /*!< 0x02000000 */
+#define IAC_IISRx_ILACIN25         IAC_IISRx_ILACIN25_Msk              /*!< illegal access input 25 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN26_Pos     (26U)
+#define IAC_IISRx_ILACIN26_Msk     (0x1UL << IAC_IISRx_ILACIN26_Pos)    /*!< 0x04000000 */
+#define IAC_IISRx_ILACIN26         IAC_IISRx_ILACIN26_Msk              /*!< illegal access input 26 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN27_Pos     (27U)
+#define IAC_IISRx_ILACIN27_Msk     (0x1UL << IAC_IISRx_ILACIN27_Pos)    /*!< 0x08000000 */
+#define IAC_IISRx_ILACIN27         IAC_IISRx_ILACIN27_Msk              /*!< illegal access input 27 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN28_Pos     (28U)
+#define IAC_IISRx_ILACIN28_Msk     (0x1UL << IAC_IISRx_ILACIN28_Pos)    /*!< 0x10000000 */
+#define IAC_IISRx_ILACIN28         IAC_IISRx_ILACIN28_Msk              /*!< illegal access input 28 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN29_Pos     (29U)
+#define IAC_IISRx_ILACIN29_Msk     (0x1UL << IAC_IISRx_ILACIN29_Pos)    /*!< 0x20000000 */
+#define IAC_IISRx_ILACIN29         IAC_IISRx_ILACIN29_Msk              /*!< illegal access input 29 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN30_Pos     (30U)
+#define IAC_IISRx_ILACIN30_Msk     (0x1UL << IAC_IISRx_ILACIN30_Pos)    /*!< 0x40000000 */
+#define IAC_IISRx_ILACIN30         IAC_IISRx_ILACIN30_Msk              /*!< illegal access input 30 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN31_Pos     (31U)
+#define IAC_IISRx_ILACIN31_Msk     (0x1UL << IAC_IISRx_ILACIN31_Pos)    /*!< 0x80000000 */
+#define IAC_IISRx_ILACIN31         IAC_IISRx_ILACIN31_Msk              /*!< illegal access input 31 (i = 0 to 31) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos                    (2U)
+#define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
+#define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos                       (3U)
+#define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
+#define RNG_CR_IE                           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos                      (5U)
+#define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
+#define RNG_CR_CED                          RNG_CR_CED_Msk
+#define RNG_CR_ARDIS_Pos                    (7U)
+#define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
+#define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
+#define RNG_CR_RNG_CONFIG3_Pos              (8U)
+#define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
+#define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
+#define RNG_CR_NISTC_Pos                    (12U)
+#define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
+#define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
+#define RNG_CR_RNG_CONFIG2_Pos              (13U)
+#define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
+#define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
+#define RNG_CR_CLKDIV_Pos                   (16U)
+#define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
+#define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
+#define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
+#define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
+#define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
+#define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
+#define RNG_CR_RNG_CONFIG1_Pos              (20U)
+#define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
+#define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
+#define RNG_CR_CONDRST_Pos                  (30U)
+#define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
+#define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
+#define RNG_CR_CONFIGLOCK_Pos               (31U)
+#define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
+#define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos                     (0U)
+#define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
+#define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos                     (1U)
+#define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
+#define RNG_SR_CECS                         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos                     (2U)
+#define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
+#define RNG_SR_SECS                         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos                     (5U)
+#define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
+#define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos                     (6U)
+#define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
+#define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
+
+/********************  Bits definition for RNG_HTCR register  *******************/
+#define RNG_HTCR_HTCFG_Pos                  (0U)
+#define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
+#define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU_Pos                       (0U)
+#define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                           RTC_TR_SU_Msk
+#define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
+#define RTC_TR_ST_Pos                       (4U)
+#define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                           RTC_TR_ST_Msk
+#define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TR_MNU_Pos                      (8U)
+#define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                          RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TR_MNT_Pos                      (12U)
+#define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                          RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TR_HU_Pos                       (16U)
+#define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                           RTC_TR_HU_Msk
+#define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TR_HT_Pos                       (20U)
+#define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                           RTC_TR_HT_Msk
+#define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TR_PM_Pos                       (22U)
+#define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                           RTC_TR_PM_Msk
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU_Pos                       (0U)
+#define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                           RTC_DR_DU_Msk
+#define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
+#define RTC_DR_DT_Pos                       (4U)
+#define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                           RTC_DR_DT_Msk
+#define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_DR_MU_Pos                       (8U)
+#define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                           RTC_DR_MU_Msk
+#define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_DR_MT_Pos                       (12U)
+#define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                           RTC_DR_MT_Msk
+#define RTC_DR_WDU_Pos                      (13U)
+#define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                          RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_DR_YU_Pos                       (16U)
+#define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                           RTC_DR_YU_Msk
+#define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
+#define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
+#define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
+#define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
+#define RTC_DR_YT_Pos                       (20U)
+#define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                           RTC_DR_YT_Msk
+#define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
+#define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
+#define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
+#define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                      (0U)
+#define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_SSR_SS                          RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_ICSR register  ******************/
+#define RTC_ICSR_WUTWF_Pos                  (2U)
+#define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
+#define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
+#define RTC_ICSR_SHPF_Pos                   (3U)
+#define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
+#define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
+#define RTC_ICSR_INITS_Pos                  (4U)
+#define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
+#define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
+#define RTC_ICSR_RSF_Pos                    (5U)
+#define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
+#define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
+#define RTC_ICSR_INITF_Pos                  (6U)
+#define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
+#define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
+#define RTC_ICSR_INIT_Pos                   (7U)
+#define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
+#define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
+#define RTC_ICSR_BIN_Pos                    (8U)
+#define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
+#define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
+#define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
+#define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
+#define RTC_ICSR_BCDU_Pos                   (10U)
+#define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
+#define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
+#define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
+#define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
+#define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
+#define RTC_ICSR_RECALPF_Pos                (16U)
+#define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
+#define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_S_Pos               (0U)
+#define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
+#define RTC_PRER_PREDIV_A_Pos               (16U)
+#define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos                    (0U)
+#define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
+#define RTC_WUTR_WUTOCLR_Pos                (16U)
+#define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
+#define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_WUCKSEL_Pos                  (0U)
+#define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
+#define RTC_CR_TSEDGE_Pos                   (3U)
+#define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
+#define RTC_CR_REFCKON_Pos                  (4U)
+#define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
+#define RTC_CR_BYPSHAD_Pos                  (5U)
+#define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
+#define RTC_CR_FMT_Pos                      (6U)
+#define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                          RTC_CR_FMT_Msk
+#define RTC_CR_SSRUIE_Pos                   (7U)
+#define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
+#define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
+#define RTC_CR_ALRAE_Pos                    (8U)
+#define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
+#define RTC_CR_ALRBE_Pos                    (9U)
+#define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
+#define RTC_CR_WUTE_Pos                     (10U)
+#define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
+#define RTC_CR_TSE_Pos                      (11U)
+#define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                          RTC_CR_TSE_Msk
+#define RTC_CR_ALRAIE_Pos                   (12U)
+#define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
+#define RTC_CR_ALRBIE_Pos                   (13U)
+#define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
+#define RTC_CR_WUTIE_Pos                    (14U)
+#define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
+#define RTC_CR_TSIE_Pos                     (15U)
+#define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
+#define RTC_CR_ADD1H_Pos                    (16U)
+#define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
+#define RTC_CR_SUB1H_Pos                    (17U)
+#define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
+#define RTC_CR_BKP_Pos                      (18U)
+#define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                          RTC_CR_BKP_Msk
+#define RTC_CR_COSEL_Pos                    (19U)
+#define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
+#define RTC_CR_POL_Pos                      (20U)
+#define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                          RTC_CR_POL_Msk
+#define RTC_CR_OSEL_Pos                     (21U)
+#define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
+#define RTC_CR_COE_Pos                      (23U)
+#define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                          RTC_CR_COE_Msk
+#define RTC_CR_ITSE_Pos                     (24U)
+#define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
+#define RTC_CR_TAMPTS_Pos                   (25U)
+#define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
+#define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
+#define RTC_CR_TAMPOE_Pos                   (26U)
+#define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
+#define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
+#define RTC_CR_ALRAFCLR_Pos                 (27U)
+#define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
+#define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
+#define RTC_CR_ALRBFCLR_Pos                 (28U)
+#define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
+#define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
+#define RTC_CR_TAMPALRM_PU_Pos              (29U)
+#define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
+#define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
+#define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
+#define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
+#define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
+#define RTC_CR_OUT2EN_Pos                   (31U)
+#define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
+#define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
+
+/********************  Bits definition for RTC_PRIVCFGR register  *****************/
+#define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
+#define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
+#define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
+#define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
+#define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
+#define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
+#define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
+#define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
+#define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
+#define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
+#define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
+#define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
+#define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
+#define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
+#define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
+#define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
+#define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
+#define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
+#define RTC_PRIVCFGR_PRIV_Pos               (15U)
+#define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
+#define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
+
+/********************  Bits definition for RTC_SECCFGR register  ******************/
+#define RTC_SECCFGR_ALRASEC_Pos             (0U)
+#define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
+#define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
+#define RTC_SECCFGR_ALRBSEC_Pos             (1U)
+#define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
+#define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
+#define RTC_SECCFGR_WUTSEC_Pos              (2U)
+#define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
+#define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
+#define RTC_SECCFGR_TSSEC_Pos               (3U)
+#define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
+#define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
+#define RTC_SECCFGR_CALSEC_Pos              (13U)
+#define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
+#define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
+#define RTC_SECCFGR_INITSEC_Pos             (14U)
+#define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
+#define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
+#define RTC_SECCFGR_SEC_Pos                 (15U)
+#define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
+#define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                     (0U)
+#define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALM_Pos                   (0U)
+#define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
+#define RTC_CALR_LPCAL_Pos                  (12U)
+#define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
+#define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALW16_Pos                 (13U)
+#define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
+#define RTC_CALR_CALW8_Pos                  (14U)
+#define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALP_Pos                   (15U)
+#define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos                (0U)
+#define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos                (31U)
+#define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_SU_Pos                     (0U)
+#define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
+#define RTC_TSTR_ST_Pos                     (4U)
+#define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_TSTR_MNU_Pos                    (8U)
+#define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_TSTR_MNT_Pos                    (12U)
+#define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_TSTR_HU_Pos                     (16U)
+#define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_TSTR_HT_Pos                     (20U)
+#define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_TSTR_PM_Pos                     (22U)
+#define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_DU_Pos                     (0U)
+#define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
+#define RTC_TSDR_DT_Pos                     (4U)
+#define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
+#define RTC_TSDR_MU_Pos                     (8U)
+#define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
+#define RTC_TSDR_MT_Pos                     (12U)
+#define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
+#define RTC_TSDR_WDU_Pos                    (13U)
+#define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos                    (0U)
+#define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
+#define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_SU_Pos                   (0U)
+#define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMAR_ST_Pos                   (4U)
+#define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMAR_MSK1_Pos                 (7U)
+#define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_MNU_Pos                  (8U)
+#define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMAR_MNT_Pos                  (12U)
+#define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMAR_MSK2_Pos                 (15U)
+#define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_HU_Pos                   (16U)
+#define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMAR_HT_Pos                   (20U)
+#define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMAR_PM_Pos                   (22U)
+#define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_MSK3_Pos                 (23U)
+#define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_DU_Pos                   (24U)
+#define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMAR_DT_Pos                   (28U)
+#define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMAR_WDSEL_Pos                (30U)
+#define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_MSK4_Pos                 (31U)
+#define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_SS_Pos                 (0U)
+#define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
+#define RTC_ALRMASSR_MASKSS_Pos             (24U)
+#define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMASSR_SSCLR_Pos              (31U)
+#define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_SU_Pos                   (0U)
+#define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMBR_ST_Pos                   (4U)
+#define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMBR_MSK1_Pos                 (7U)
+#define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_MNU_Pos                  (8U)
+#define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMBR_MNT_Pos                  (12U)
+#define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMBR_MSK2_Pos                 (15U)
+#define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_HU_Pos                   (16U)
+#define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMBR_HT_Pos                   (20U)
+#define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMBR_PM_Pos                   (22U)
+#define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_MSK3_Pos                 (23U)
+#define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_DU_Pos                   (24U)
+#define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMBR_DT_Pos                   (28U)
+#define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMBR_WDSEL_Pos                (30U)
+#define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_MSK4_Pos                 (31U)
+#define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_SS_Pos                 (0U)
+#define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
+#define RTC_ALRMBSSR_MASKSS_Pos             (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMBSSR_SSCLR_Pos              (31U)
+#define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_SR register  *******************/
+#define RTC_SR_ALRAF_Pos                    (0U)
+#define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
+#define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
+#define RTC_SR_ALRBF_Pos                    (1U)
+#define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
+#define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
+#define RTC_SR_WUTF_Pos                     (2U)
+#define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
+#define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
+#define RTC_SR_TSF_Pos                      (3U)
+#define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
+#define RTC_SR_TSF                          RTC_SR_TSF_Msk
+#define RTC_SR_TSOVF_Pos                    (4U)
+#define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
+#define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
+#define RTC_SR_ITSF_Pos                     (5U)
+#define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
+#define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
+#define RTC_SR_SSRUF_Pos                    (6U)
+#define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
+#define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
+
+/********************  Bits definition for RTC_MISR register  *****************/
+#define RTC_MISR_ALRAMF_Pos                 (0U)
+#define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
+#define RTC_MISR_ALRBMF_Pos                 (1U)
+#define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
+#define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
+#define RTC_MISR_WUTMF_Pos                  (2U)
+#define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
+#define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
+#define RTC_MISR_TSMF_Pos                   (3U)
+#define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
+#define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
+#define RTC_MISR_TSOVMF_Pos                 (4U)
+#define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
+#define RTC_MISR_ITSMF_Pos                  (5U)
+#define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
+#define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
+#define RTC_MISR_SSRUMF_Pos                 (6U)
+#define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
+#define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SMISR register  *****************/
+#define RTC_SMISR_ALRAMF_Pos                (0U)
+#define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
+#define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
+#define RTC_SMISR_ALRBMF_Pos                (1U)
+#define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
+#define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
+#define RTC_SMISR_WUTMF_Pos                 (2U)
+#define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
+#define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
+#define RTC_SMISR_TSMF_Pos                  (3U)
+#define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
+#define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
+#define RTC_SMISR_TSOVMF_Pos                (4U)
+#define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
+#define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
+#define RTC_SMISR_ITSMF_Pos                 (5U)
+#define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
+#define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
+#define RTC_SMISR_SSRUMF_Pos                (6U)
+#define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
+#define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SCR register  ******************/
+#define RTC_SCR_CALRAF_Pos                  (0U)
+#define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
+#define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
+#define RTC_SCR_CALRBF_Pos                  (1U)
+#define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
+#define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
+#define RTC_SCR_CWUTF_Pos                   (2U)
+#define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
+#define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
+#define RTC_SCR_CTSF_Pos                    (3U)
+#define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
+#define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
+#define RTC_SCR_CTSOVF_Pos                  (4U)
+#define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
+#define RTC_SCR_CITSF_Pos                   (5U)
+#define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
+#define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
+#define RTC_SCR_CSSRUF_Pos                  (6U)
+#define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
+#define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
+
+/********************  Bits definition for RTC_ALRABINR register  ******************/
+#define RTC_ALRABINR_SS_Pos                 (0U)
+#define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
+
+/********************  Bits definition for RTC_ALRBBINR register  ******************/
+#define RTC_ALRBBINR_SS_Pos                 (0U)
+#define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos                  (0U)
+#define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
+#define SAI_GCR_SYNCOUT_Pos                 (4U)
+#define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos                   (0U)
+#define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
+#define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
+#define SAI_xCR1_PRTCFG_Pos                 (2U)
+#define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
+#define SAI_xCR1_DS_Pos                     (5U)
+#define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
+#define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
+#define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
+#define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
+#define SAI_xCR1_LSBFIRST_Pos               (8U)
+#define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos                  (9U)
+#define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
+#define SAI_xCR1_SYNCEN_Pos                 (10U)
+#define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
+#define SAI_xCR1_MONO_Pos                   (12U)
+#define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
+#define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos                (13U)
+#define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos                  (16U)
+#define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos                  (17U)
+#define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos                  (19U)
+#define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
+#define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
+#define SAI_xCR1_MCKDIV_Pos                 (20U)
+#define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
+#define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
+#define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
+#define SAI_xCR1_OSR_Pos                    (26U)
+#define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
+#define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
+#define SAI_xCR1_MCKEN_Pos                  (27U)
+#define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos                    (0U)
+#define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
+#define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
+#define SAI_xCR2_FFLUSH_Pos                 (3U)
+#define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos                   (4U)
+#define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
+#define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos                   (5U)
+#define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
+#define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos                (6U)
+#define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
+#define SAI_xCR2_MUTECNT_Pos                (7U)
+#define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
+#define SAI_xCR2_CPL_Pos                    (13U)
+#define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
+#define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos                   (14U)
+#define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
+#define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos                   (0U)
+#define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
+#define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
+#define SAI_xFRCR_FSALL_Pos                 (8U)
+#define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
+#define SAI_xFRCR_FSDEF_Pos                 (16U)
+#define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos                 (17U)
+#define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos                 (18U)
+#define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos                (0U)
+#define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
+#define SAI_xSLOTR_SLOTSZ_Pos               (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
+#define SAI_xSLOTR_NBSLOT_Pos               (8U)
+#define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
+#define SAI_xSLOTR_SLOTEN_Pos               (16U)
+#define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos               (0U)
+#define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos              (1U)
+#define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos               (2U)
+#define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos                 (3U)
+#define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos                (4U)
+#define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos               (5U)
+#define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos               (6U)
+#define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos                  (0U)
+#define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos                 (1U)
+#define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos                  (2U)
+#define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos                    (3U)
+#define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos                   (4U)
+#define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos                  (5U)
+#define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos                  (6U)
+#define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
+#define SAI_xSR_FLVL_Pos                    (16U)
+#define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
+#define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos              (0U)
+#define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos             (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos              (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos                (3U)
+#define SAI_xCLRFR_CFREQ_Msk                (0x1UL << SAI_xCLRFR_CFREQ_Pos)         /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ                    SAI_xCLRFR_CFREQ_Msk                    /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos               (4U)
+#define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos              (5U)
+#define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos              (6U)
+#define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos                    (0U)
+#define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA                        SAI_xDR_DATA_Msk
+
+/******************  Bit definition for SAI_PDMCR register  *******************/
+#define SAI_PDMCR_PDMEN_Pos                 (0U)
+#define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
+#define SAI_PDMCR_MICNBR_Pos                (4U)
+#define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
+#define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
+#define SAI_PDMCR_CKEN1_Pos                 (8U)
+#define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
+#define SAI_PDMCR_CKEN2_Pos                 (9U)
+#define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
+#define SAI_PDMCR_CKEN3_Pos                 (10U)
+#define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
+#define SAI_PDMCR_CKEN4_Pos                 (11U)
+#define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos               (0U)
+#define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
+#define SAI_PDMDLY_DLYM1R_Pos               (4U)
+#define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
+#define SAI_PDMDLY_DLYM2L_Pos               (8U)
+#define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
+#define SAI_PDMDLY_DLYM2R_Pos               (12U)
+#define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
+#define SAI_PDMDLY_DLYM3L_Pos               (16U)
+#define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
+#define SAI_PDMDLY_DLYM3R_Pos               (20U)
+#define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
+#define SAI_PDMDLY_DLYM4L_Pos               (24U)
+#define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
+#define SAI_PDMDLY_DLYM4R_Pos               (28U)
+#define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos             (0U)
+#define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos             (2U)
+#define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos           (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos              (4U)
+#define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos              (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos              (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_WIDBUS_Pos              (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
+#define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos                 (18U)
+#define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos                (0U)
+#define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos              (0U)
+#define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos              (6U)
+#define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos               (7U)
+#define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
+#define SDMMC_CMD_WAITRESP_Pos              (8U)
+#define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITINT_Pos               (10U)
+#define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos              (11U)
+#define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos                (12U)
+#define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos                (13U)
+#define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos              (14U)
+#define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos                (15U)
+#define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos           (0U)
+#define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos           (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos                (0U)
+#define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos               (1U)
+#define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos              (2U)
+#define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+#define SDMMC_DCTRL_RWSTART_Pos             (8U)
+#define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos              (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos               (10U)
+#define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos              (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos             (13U)
+#define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos              (0U)
+#define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos              (1U)
+#define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos              (2U)
+#define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos              (3U)
+#define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos              (4U)
+#define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos               (5U)
+#define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos               (6U)
+#define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos               (7U)
+#define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos               (8U)
+#define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos                 (9U)
+#define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos               (10U)
+#define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos                (11U)
+#define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos               (12U)
+#define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos               (13U)
+#define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos              (14U)
+#define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos              (15U)
+#define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos               (16U)
+#define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos               (17U)
+#define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos               (18U)
+#define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos               (19U)
+#define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos                (20U)
+#define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos             (21U)
+#define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos                (22U)
+#define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos               (23U)
+#define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos                (25U)
+#define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos                (26U)
+#define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos                (27U)
+#define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos               (28U)
+#define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos             (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos             (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos             (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos              (5U)
+#define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos              (6U)
+#define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos              (7U)
+#define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos              (8U)
+#define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos                (9U)
+#define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos              (10U)
+#define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos               (11U)
+#define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos               (22U)
+#define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos              (23U)
+#define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos               (25U)
+#define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos               (26U)
+#define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos               (27U)
+#define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos              (28U)
+#define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos            (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos            (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos            (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos            (8U)
+#define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos              (9U)
+#define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos            (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos             (11U)
+#define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
+#define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos             (22U)
+#define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos            (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos             (25U)
+#define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos             (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos            (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFOTHR register  *******************/
+#define SDMMC_FIFOTHR_THR_Pos               (0U)
+#define SDMMC_FIFOTHR_THR_Msk               (0xFUL << SDMMC_FIFOTHR_THR_Pos)        /*!< 0x0000000F */
+#define SDMMC_FIFOTHR_THR                   SDMMC_FIFOTHR_THR_Msk                   /*!<FIFO threshold */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos             (0U)
+#define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos               (0U)
+#define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos            (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos        (6U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0x7FFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0001FFC0 */
+#define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk              /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASER register  ***************/
+#define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */
+
+/*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
+#define SDMMC_IDMALAR_IDMALA_Pos            (0U)
+#define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
+#define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
+#define SDMMC_IDMALAR_ABR_Pos               (29U)
+#define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
+#define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
+#define SDMMC_IDMALAR_ULS_Pos               (30U)
+#define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
+#define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
+#define SDMMC_IDMALAR_ULA_Pos               (31U)
+#define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
+#define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */
+
+/*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
+#define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos                     (0U)
+#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
+#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
+#define SPI_CR1_MASRX_Pos                   (8U)
+#define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
+#define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
+#define SPI_CR1_CSTART_Pos                  (9U)
+#define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
+#define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
+#define SPI_CR1_CSUSP_Pos                   (10U)
+#define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
+#define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
+#define SPI_CR1_HDDIR_Pos                   (11U)
+#define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
+#define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
+#define SPI_CR1_SSI_Pos                     (12U)
+#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
+#define SPI_CR1_CRC33_17_Pos                (13U)
+#define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
+#define SPI_CR1_RCRCINI_Pos                 (14U)
+#define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
+#define SPI_CR1_TCRCINI_Pos                 (15U)
+#define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
+#define SPI_CR1_IOLOCK_Pos                  (16U)
+#define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSIZE_Pos                   (0U)
+#define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
+
+/*******************  Bit definition for SPI_CFG1 register  *******************/
+#define SPI_CFG1_DSIZE_Pos                  (0U)
+#define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
+#define SPI_CFG1_FTHLV_Pos                  (5U)
+#define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
+#define SPI_CFG1_UDRCFG_Pos                 (9U)
+#define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
+#define SPI_CFG1_RXDMAEN_Pos                (14U)
+#define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
+#define SPI_CFG1_TXDMAEN_Pos                (15U)
+#define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
+#define SPI_CFG1_CRCSIZE_Pos                (16U)
+#define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
+#define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
+#define SPI_CFG1_CRCEN_Pos                  (22U)
+#define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
+#define SPI_CFG1_MBR_Pos                    (28U)
+#define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
+#define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
+#define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
+#define SPI_CFG1_BPASS_Pos                  (31U)
+#define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
+#define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
+
+/*******************  Bit definition for SPI_CFG2 register  *******************/
+#define SPI_CFG2_MSSI_Pos                   (0U)
+#define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
+#define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
+#define SPI_CFG2_MIDI_Pos                   (4U)
+#define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
+#define SPI_CFG2_RDIOM_Pos                  (13U)
+#define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
+#define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
+#define SPI_CFG2_RDIOP_Pos                  (14U)
+#define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
+#define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
+#define SPI_CFG2_IOSWP_Pos                  (15U)
+#define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
+#define SPI_CFG2_COMM_Pos                   (17U)
+#define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
+#define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
+#define SPI_CFG2_SP_Pos                     (19U)
+#define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
+#define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
+#define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
+#define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
+#define SPI_CFG2_MASTER_Pos                 (22U)
+#define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
+#define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
+#define SPI_CFG2_LSBFRST_Pos                (23U)
+#define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
+#define SPI_CFG2_CPHA_Pos                   (24U)
+#define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
+#define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
+#define SPI_CFG2_CPOL_Pos                   (25U)
+#define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
+#define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
+#define SPI_CFG2_SSM_Pos                    (26U)
+#define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
+#define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
+#define SPI_CFG2_SSIOP_Pos                  (28U)
+#define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos                   (29U)
+#define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
+#define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos                   (30U)
+#define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
+#define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
+#define SPI_CFG2_AFCNTR_Pos                 (31U)
+#define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos                   (0U)
+#define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
+#define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
+#define SPI_IER_TXPIE_Pos                   (1U)
+#define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
+#define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
+#define SPI_IER_DXPIE_Pos                   (2U)
+#define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
+#define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
+#define SPI_IER_EOTIE_Pos                   (3U)
+#define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
+#define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
+#define SPI_IER_TXTFIE_Pos                  (4U)
+#define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
+#define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
+#define SPI_IER_UDRIE_Pos                   (5U)
+#define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
+#define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
+#define SPI_IER_OVRIE_Pos                   (6U)
+#define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
+#define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
+#define SPI_IER_CRCEIE_Pos                  (7U)
+#define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
+#define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
+#define SPI_IER_TIFREIE_Pos                 (8U)
+#define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
+#define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos                  (9U)
+#define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
+#define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
+
+/*******************  Bit definition for SPI_SR register  *********************/
+#define SPI_SR_RXP_Pos                      (0U)
+#define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
+#define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_TXP_Pos                      (1U)
+#define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
+#define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
+#define SPI_SR_DXP_Pos                      (2U)
+#define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
+#define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_EOT_Pos                      (3U)
+#define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
+#define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_TXTF_Pos                     (4U)
+#define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
+#define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
+#define SPI_SR_UDR_Pos                      (5U)
+#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
+#define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
+#define SPI_SR_OVR_Pos                      (6U)
+#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
+#define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_CRCE_Pos                     (7U)
+#define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
+#define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
+#define SPI_SR_TIFRE_Pos                    (8U)
+#define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
+#define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
+#define SPI_SR_MODF_Pos                     (9U)
+#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
+#define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
+#define SPI_SR_SUSP_Pos                     (11U)
+#define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
+#define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
+#define SPI_SR_TXC_Pos                      (12U)
+#define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
+#define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos                   (13U)
+#define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
+#define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
+#define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos                    (15U)
+#define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
+#define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
+#define SPI_SR_CTSIZE_Pos                   (16U)
+#define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
+
+/*******************  Bit definition for SPI_IFCR register  *******************/
+#define SPI_IFCR_EOTC_Pos                   (3U)
+#define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
+#define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
+#define SPI_IFCR_TXTFC_Pos                  (4U)
+#define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos                   (5U)
+#define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
+#define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
+#define SPI_IFCR_OVRC_Pos                   (6U)
+#define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
+#define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
+#define SPI_IFCR_CRCEC_Pos                  (7U)
+#define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
+#define SPI_IFCR_TIFREC_Pos                 (8U)
+#define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
+#define SPI_IFCR_MODFC_Pos                  (9U)
+#define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
+#define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
+#define SPI_IFCR_SUSPC_Pos                  (11U)
+#define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
+
+/*******************  Bit definition for SPI_TXDR register  *******************/
+#define SPI_TXDR_TXDR_Pos                   (0U)
+#define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  *******************/
+#define SPI_RXDR_RXDR_Pos                   (0U)
+#define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ****************/
+#define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */
+
+/*******************  Bit definition for SPI_TXCRC register  ******************/
+#define SPI_TXCRC_TXCRC_Pos                 (0U)
+#define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ******************/
+#define SPI_RXCRC_RXCRC_Pos                 (0U)
+#define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ******************/
+#define SPI_UDRDR_UDRDR_Pos                 (0U)
+#define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */
+
+/*******************  Bits definition for SPI_I2SCFGR register  ***************/
+#define SPI_I2SCFGR_I2SMOD_Pos              (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)        /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk                  /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos              (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk              (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk                  /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2                (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos              (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk                  /*!<I2SSTD[1:0] I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)       /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk                 /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_DATLEN_Pos              (8U)
+#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk                  /*!<DATLEN[1:0] Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos               (10U)
+#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)         /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk                   /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos               (11U)
+#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)         /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk                   /*!<Serial audio clock polarity */
+#define SPI_I2SCFGR_FIXCH_Pos               (12U)
+#define SPI_I2SCFGR_FIXCH_Msk               (0x1UL << SPI_I2SCFGR_FIXCH_Pos)         /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH                   SPI_I2SCFGR_FIXCH_Msk                   /*!<Fixed channel length in SLAVE */
+#define SPI_I2SCFGR_WSINV_Pos               (13U)
+#define SPI_I2SCFGR_WSINV_Msk               (0x1UL << SPI_I2SCFGR_WSINV_Pos)         /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV                   SPI_I2SCFGR_WSINV_Msk                   /*!<Word select inversion */
+#define SPI_I2SCFGR_DATFMT_Pos              (14U)
+#define SPI_I2SCFGR_DATFMT_Msk              (0x1UL << SPI_I2SCFGR_DATFMT_Pos)        /*!< 0x00003000 */
+#define SPI_I2SCFGR_DATFMT                  SPI_I2SCFGR_DATFMT_Msk                  /*!<Data format */
+#define SPI_I2SCFGR_I2SDIV_Pos              (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk              (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)       /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV                  SPI_I2SCFGR_I2SDIV_Msk                  /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos                 (24U)
+#define SPI_I2SCFGR_ODD_Msk                 (0x1UL << SPI_I2SCFGR_ODD_Pos)           /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD                     SPI_I2SCFGR_ODD_Msk                     /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos               (25U)
+#define SPI_I2SCFGR_MCKOE_Msk               (0x1UL << SPI_I2SCFGR_MCKOE_Pos)         /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE                   SPI_I2SCFGR_MCKOE_Msk                   /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFRXEN_Pos       (0U)
+#define SPDIFRX_CR_SPDIFRXEN_Msk       (0x3UL << SPDIFRX_CR_SPDIFRXEN_Pos)     /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFRXEN           SPDIFRX_CR_SPDIFRXEN_Msk                /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_SPDIFRXEN_0         (0x01UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000001 */
+#define SPDIFRX_CR_SPDIFRXEN_1         (0x02UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000002 */
+#define SPDIFRX_CR_RXDMAEN_Pos         (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk         (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN             SPDIFRX_CR_RXDMAEN_Msk                  /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos          (3U)
+#define SPDIFRX_CR_RXSTEO_Msk          (0x1UL << SPDIFRX_CR_RXSTEO_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO              SPDIFRX_CR_RXSTEO_Msk                   /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos           (4U)
+#define SPDIFRX_CR_DRFMT_Msk           (0x3UL << SPDIFRX_CR_DRFMT_Pos)         /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT               SPDIFRX_CR_DRFMT_Msk                    /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos            (6U)
+#define SPDIFRX_CR_PMSK_Msk            (0x1UL << SPDIFRX_CR_PMSK_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK                SPDIFRX_CR_PMSK_Msk                     /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos            (7U)
+#define SPDIFRX_CR_VMSK_Msk            (0x1UL << SPDIFRX_CR_VMSK_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK                SPDIFRX_CR_VMSK_Msk                     /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos           (8U)
+#define SPDIFRX_CR_CUMSK_Msk           (0x1UL << SPDIFRX_CR_CUMSK_Pos)         /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK               SPDIFRX_CR_CUMSK_Msk                    /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos           (9U)
+#define SPDIFRX_CR_PTMSK_Msk           (0x1UL << SPDIFRX_CR_PTMSK_Pos)         /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK               SPDIFRX_CR_PTMSK_Msk                    /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos         (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk         (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)       /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN             SPDIFRX_CR_CBDMAEN_Msk                  /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos           (11U)
+#define SPDIFRX_CR_CHSEL_Msk           (0x1UL << SPDIFRX_CR_CHSEL_Pos)         /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL               SPDIFRX_CR_CHSEL_Msk                    /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos            (12U)
+#define SPDIFRX_CR_NBTR_Msk            (0x3UL << SPDIFRX_CR_NBTR_Pos)          /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR                SPDIFRX_CR_NBTR_Msk                     /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos             (14U)
+#define SPDIFRX_CR_WFA_Msk             (0x1UL << SPDIFRX_CR_WFA_Pos)           /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA                 SPDIFRX_CR_WFA_Msk                      /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos           (16U)
+#define SPDIFRX_CR_INSEL_Msk           (0x7UL << SPDIFRX_CR_INSEL_Pos)         /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL               SPDIFRX_CR_INSEL_Msk                    /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos           (20U)
+#define SPDIFRX_CR_CKSEN_Msk           (0x1UL << SPDIFRX_CR_CKSEN_Pos)         /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN               SPDIFRX_CR_CKSEN_Msk                    /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos        (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk        (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)      /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN            SPDIFRX_CR_CKSBKPEN_Msk                 /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos         (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk         (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)       /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE             SPDIFRX_IMR_RXNEIE_Msk                  /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos        (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk        (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)      /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE            SPDIFRX_IMR_CSRNEIE_Msk                 /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos         (2U)
+#define SPDIFRX_IMR_PERRIE_Msk         (0x1UL << SPDIFRX_IMR_PERRIE_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE             SPDIFRX_IMR_PERRIE_Msk                  /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos          (3U)
+#define SPDIFRX_IMR_OVRIE_Msk          (0x1UL << SPDIFRX_IMR_OVRIE_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE              SPDIFRX_IMR_OVRIE_Msk                   /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos         (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk         (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE             SPDIFRX_IMR_SBLKIE_Msk                  /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos        (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk        (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)      /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE            SPDIFRX_IMR_SYNCDIE_Msk                 /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos          (6U)
+#define SPDIFRX_IMR_IFEIE_Msk          (0x1UL << SPDIFRX_IMR_IFEIE_Pos)        /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE              SPDIFRX_IMR_IFEIE_Msk                   /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos            (0U)
+#define SPDIFRX_SR_RXNE_Msk            (0x1UL << SPDIFRX_SR_RXNE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE                SPDIFRX_SR_RXNE_Msk                     /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos           (1U)
+#define SPDIFRX_SR_CSRNE_Msk           (0x1UL << SPDIFRX_SR_CSRNE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE               SPDIFRX_SR_CSRNE_Msk                    /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos            (2U)
+#define SPDIFRX_SR_PERR_Msk            (0x1UL << SPDIFRX_SR_PERR_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR                SPDIFRX_SR_PERR_Msk                     /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos             (3U)
+#define SPDIFRX_SR_OVR_Msk             (0x1UL << SPDIFRX_SR_OVR_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR                 SPDIFRX_SR_OVR_Msk                      /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos             (4U)
+#define SPDIFRX_SR_SBD_Msk             (0x1UL << SPDIFRX_SR_SBD_Pos)           /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD                 SPDIFRX_SR_SBD_Msk                      /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos           (5U)
+#define SPDIFRX_SR_SYNCD_Msk           (0x1UL << SPDIFRX_SR_SYNCD_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD               SPDIFRX_SR_SYNCD_Msk                    /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos            (6U)
+#define SPDIFRX_SR_FERR_Msk            (0x1UL << SPDIFRX_SR_FERR_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR                SPDIFRX_SR_FERR_Msk                     /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos            (7U)
+#define SPDIFRX_SR_SERR_Msk            (0x1UL << SPDIFRX_SR_SERR_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR                SPDIFRX_SR_SERR_Msk                     /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos            (8U)
+#define SPDIFRX_SR_TERR_Msk            (0x1UL << SPDIFRX_SR_TERR_Pos)          /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR                SPDIFRX_SR_TERR_Msk                     /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos          (16U)
+#define SPDIFRX_SR_WIDTH5_Msk          (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)     /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5              SPDIFRX_SR_WIDTH5_Msk                   /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos        (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk        (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)      /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF            SPDIFRX_IFCR_PERRCF_Msk                 /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos         (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk         (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)       /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF             SPDIFRX_IFCR_OVRCF_Msk                  /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos         (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk         (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF             SPDIFRX_IFCR_SBDCF_Msk                  /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos       (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk       (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)     /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF           SPDIFRX_IFCR_SYNCDCF_Msk                /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos             (0U)
+#define SPDIFRX_DR0_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)      /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR                 SPDIFRX_DR0_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos             (24U)
+#define SPDIFRX_DR0_PE_Msk             (0x1UL << SPDIFRX_DR0_PE_Pos)           /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE                 SPDIFRX_DR0_PE_Msk                      /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos              (25U)
+#define SPDIFRX_DR0_V_Msk              (0x1UL << SPDIFRX_DR0_V_Pos)            /*!< 0x02000000 */
+#define SPDIFRX_DR0_V                  SPDIFRX_DR0_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos              (26U)
+#define SPDIFRX_DR0_U_Msk              (0x1UL << SPDIFRX_DR0_U_Pos)            /*!< 0x04000000 */
+#define SPDIFRX_DR0_U                  SPDIFRX_DR0_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos              (27U)
+#define SPDIFRX_DR0_C_Msk              (0x1UL << SPDIFRX_DR0_C_Pos)            /*!< 0x08000000 */
+#define SPDIFRX_DR0_C                  SPDIFRX_DR0_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos             (28U)
+#define SPDIFRX_DR0_PT_Msk             (0x3UL << SPDIFRX_DR0_PT_Pos)           /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT                 SPDIFRX_DR0_PT_Msk                      /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos             (8U)
+#define SPDIFRX_DR1_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)      /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR                 SPDIFRX_DR1_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos             (4U)
+#define SPDIFRX_DR1_PT_Msk             (0x3UL << SPDIFRX_DR1_PT_Pos)           /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT                 SPDIFRX_DR1_PT_Msk                      /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos              (3U)
+#define SPDIFRX_DR1_C_Msk              (0x1UL << SPDIFRX_DR1_C_Pos)            /*!< 0x00000008 */
+#define SPDIFRX_DR1_C                  SPDIFRX_DR1_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos              (2U)
+#define SPDIFRX_DR1_U_Msk              (0x1UL << SPDIFRX_DR1_U_Pos)            /*!< 0x00000004 */
+#define SPDIFRX_DR1_U                  SPDIFRX_DR1_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos              (1U)
+#define SPDIFRX_DR1_V_Msk              (0x1UL << SPDIFRX_DR1_V_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_DR1_V                  SPDIFRX_DR1_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos             (0U)
+#define SPDIFRX_DR1_PE_Msk             (0x1UL << SPDIFRX_DR1_PE_Pos)           /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE                 SPDIFRX_DR1_PE_Msk                      /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos          (16U)
+#define SPDIFRX_DR1_DRNL1_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)     /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1              SPDIFRX_DR1_DRNL1_Msk                   /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos          (0U)
+#define SPDIFRX_DR1_DRNL2_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)     /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2              SPDIFRX_DR1_DRNL2_Msk                   /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos            (0U)
+#define SPDIFRX_CSR_USR_Msk            (0xFFFFUL << SPDIFRX_CSR_USR_Pos)       /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR                SPDIFRX_CSR_USR_Msk                     /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos             (16U)
+#define SPDIFRX_CSR_CS_Msk             (0xFFUL << SPDIFRX_CSR_CS_Pos)          /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS                 SPDIFRX_CSR_CS_Msk                      /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos            (24U)
+#define SPDIFRX_CSR_SOB_Msk            (0x1UL << SPDIFRX_CSR_SOB_Pos)          /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB                SPDIFRX_CSR_SOB_Msk                     /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos            (0U)
+#define SPDIFRX_DIR_THI_Msk            (0x1FFFUL << SPDIFRX_DIR_THI_Pos)       /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI                SPDIFRX_DIR_THI_Msk                     /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos            (16U)
+#define SPDIFRX_DIR_TLO_Msk            (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)       /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO                SPDIFRX_DIR_TLO_Msk                     /*!<Threshold HIGH     */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_BOOTCR register  ****************/
+#define SYSCFG_BOOTCR_BOOT0_PD_Pos          (0U)
+#define SYSCFG_BOOTCR_BOOT0_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT0_PD_Pos)   /*!< 0x00000001 */
+#define SYSCFG_BOOTCR_BOOT0_PD              SYSCFG_BOOTCR_BOOT0_PD_Msk              /*!< BOOT0 pin pull-down disable */
+#define SYSCFG_BOOTCR_BOOT1_PD_Pos          (1U)
+#define SYSCFG_BOOTCR_BOOT1_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT1_PD_Pos)   /*!< 0x00000002 */
+#define SYSCFG_BOOTCR_BOOT1_PD              SYSCFG_BOOTCR_BOOT1_PD_Msk              /*!< BOOT1 pin pull-down disable */
+
+/******************  Bit definition for SYSCFG_CM55CR register  ****************/
+#define SYSCFG_CM55CR_FPU_IT_EN_Pos         (0U)
+#define SYSCFG_CM55CR_FPU_IT_EN_Msk         (0x3FUL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x0000003F */
+#define SYSCFG_CM55CR_FPU_IT_EN             SYSCFG_CM55CR_FPU_IT_EN_Msk             /*!< Enable FPU exception */
+#define SYSCFG_CM55CR_FPU_IT_EN_0           (0x1UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55CR_FPU_IT_EN_1           (0x2UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55CR_FPU_IT_EN_2           (0x4UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55CR_FPU_IT_EN_3           (0x8UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000008 */
+#define SYSCFG_CM55CR_FPU_IT_EN_4           (0x10UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000010 */
+#define SYSCFG_CM55CR_FPU_IT_EN_5           (0x20UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000020 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Pos      (16U)
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Msk      (0x1UL << SYSCFG_CM55CR_LOCKSVTAIRCR_Pos) /*!< 0x00010000 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR          SYSCFG_CM55CR_LOCKSVTAIRCR_Msk
+#define SYSCFG_CM55CR_LOCKNSVTOR_Pos        (17U)
+#define SYSCFG_CM55CR_LOCKNSVTOR_Msk        (0x1UL << SYSCFG_CM55CR_LOCKNSVTOR_Pos) /*!< 0x00020000 */
+#define SYSCFG_CM55CR_LOCKNSVTOR            SYSCFG_CM55CR_LOCKNSVTOR_Msk            /*!< Prevent changes to the non-secure vector table base address */
+#define SYSCFG_CM55CR_LOCKSMPU_Pos          (18U)
+#define SYSCFG_CM55CR_LOCKSMPU_Msk          (0x1UL << SYSCFG_CM55CR_LOCKSMPU_Pos)   /*!< 0x00040000 */
+#define SYSCFG_CM55CR_LOCKSMPU              SYSCFG_CM55CR_LOCKSMPU_Msk              /*!< Prevent changes to programmed secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKNSMPU_Pos         (19U)
+#define SYSCFG_CM55CR_LOCKNSMPU_Msk         (0x1UL << SYSCFG_CM55CR_LOCKNSMPU_Pos)  /*!< 0x00080000 */
+#define SYSCFG_CM55CR_LOCKNSMPU             SYSCFG_CM55CR_LOCKNSMPU_Msk             /*!< Prevent changes to programmed non-secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKSAU_Pos           (20U)
+#define SYSCFG_CM55CR_LOCKSAU_Msk           (0x1UL << SYSCFG_CM55CR_LOCKSAU_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CM55CR_LOCKSAU               SYSCFG_CM55CR_LOCKSAU_Msk               /*!< Prevent changes to secure SAU memory regions already programmed */
+#define SYSCFG_CM55CR_LOCKDCAIC_Pos         (21U)
+#define SYSCFG_CM55CR_LOCKDCAIC_Msk         (0x1UL << SYSCFG_CM55CR_LOCKDCAIC_Pos)  /*!< 0x00200000 */
+#define SYSCFG_CM55CR_LOCKDCAIC             SYSCFG_CM55CR_LOCKDCAIC_Msk
+
+/******************  Bit definition for SYSCFG_CM55TCMCR register  ***************/
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Pos      (0U)
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x0000000F */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ          SYSCFG_CM55TCMCR_CFGITCMSZ_Msk               /*!< Select ITCM memory size */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000001 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000002 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000004 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000008 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos      (4U)
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ          SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk               /*!< Select DTCM memory size */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000010 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000020 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000040 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000080 */
+#define SYSCFG_CM55TCMCR_LOCKTCM_Pos        (16U)
+#define SYSCFG_CM55TCMCR_LOCKTCM_Msk        (0x1UL << SYSCFG_CM55TCMCR_LOCKTCM_Pos)      /*!< 0x00010000 */
+#define SYSCFG_CM55TCMCR_LOCKTCM            SYSCFG_CM55TCMCR_LOCKTCM_Msk                 /*!< Disable writes to registers associated with the TCM region */
+#define SYSCFG_CM55TCMCR_LOCKITGU_Pos       (17U)
+#define SYSCFG_CM55TCMCR_LOCKITGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKITGU_Pos)     /*!< 0x00020000 */
+#define SYSCFG_CM55TCMCR_LOCKITGU           SYSCFG_CM55TCMCR_LOCKITGU_Msk                /*!< Disable writes to registers associated with the ITCM interface security/gating */
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Pos       (18U)
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKDTGU_Pos)     /*!< 0x00040000 */
+#define SYSCFG_CM55TCMCR_LOCKDTGU           SYSCFG_CM55TCMCR_LOCKDTGU_Msk                /*!< Disable writes to registers associated with the DTCM interface security/gating. */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos  (23U)
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos) /*!< 0x00800000 */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE      SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended ITCM memory */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos  (24U)
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos) /*!< 0x01000000 */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE      SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended DTCM memory */
+
+
+/******************  Bit definition for SYSCFG_CM55RWMCR register  **************/
+#define SYSCFG_CM55RWMCR_RME_TCM_Pos        (0U)
+#define SYSCFG_CM55RWMCR_RME_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_RME_TCM_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55RWMCR_RME_TCM            SYSCFG_CM55RWMCR_RME_TCM_Msk              /*!< RW margin enable input for TCM memories */
+#define SYSCFG_CM55RWMCR_RM_TCM_Pos         (1U)
+#define SYSCFG_CM55RWMCR_RM_TCM_Msk         (0xFUL << SYSCFG_CM55RWMCR_RM_TCM_Pos)    /*!< 0x0000001E */
+#define SYSCFG_CM55RWMCR_RM_TCM             SYSCFG_CM55RWMCR_RM_TCM_Msk               /*!< External RW margin inputs for TCM memories */
+#define SYSCFG_CM55RWMCR_BC1_TCM_Pos        (5U)
+#define SYSCFG_CM55RWMCR_BC1_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC1_TCM_Pos)   /*!< 0x00000020 */
+#define SYSCFG_CM55RWMCR_BC1_TCM            SYSCFG_CM55RWMCR_BC1_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_TCM_Pos        (6U)
+#define SYSCFG_CM55RWMCR_BC2_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC2_TCM_Pos)   /*!< 0x00000040 */
+#define SYSCFG_CM55RWMCR_BC2_TCM            SYSCFG_CM55RWMCR_BC2_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom + 10% */
+#define SYSCFG_CM55RWMCR_RME_CACHE_Pos      (7U)
+#define SYSCFG_CM55RWMCR_RME_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_RME_CACHE_Pos) /*!< 0x00000080 */
+#define SYSCFG_CM55RWMCR_RME_CACHE          SYSCFG_CM55RWMCR_RME_CACHE_Msk            /*!< RW margin enable input for caches memories */
+#define SYSCFG_CM55RWMCR_RM_CACHE_Pos       (8U)
+#define SYSCFG_CM55RWMCR_RM_CACHE_Msk       (0xFUL << SYSCFG_CM55RWMCR_RM_CACHE_Pos)  /*!< 0x00000F00 */
+#define SYSCFG_CM55RWMCR_RM_CACHE           SYSCFG_CM55RWMCR_RM_CACHE_Msk             /*!< External read/write (RW) margin inputs for caches memories */
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Pos      (12U)
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC1_CACHE_Pos) /*!< 0x0001000 */
+#define SYSCFG_CM55RWMCR_BC1_CACHE          SYSCFG_CM55RWMCR_BC1_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Pos      (13U)
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC2_CACHE_Pos) /*!< 0x00002000 */
+#define SYSCFG_CM55RWMCR_BC2_CACHE          SYSCFG_CM55RWMCR_BC2_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom + 10% */
+
+/******************  Bit definition for SYSCFG_INITSVTORCR register  **************/
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos   (7U)
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk   (0x1FFFFFFUL << SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos)   /*!< 0xFFFFFF80 */
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR       SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk                    /*!< Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_INITNSVTORCR register  **************/
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos  (7U)
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk  (0x1FFFFFFUL << SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos)  /*!< 0xFFFFFF80 */
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR      SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk                   /*!< Non-Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_CM55RSTCR register  **************/
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos     (0U)
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk     (0x1UL << SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE         SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk            /*!< Select reset to apply on core upon SYSRESETREQ */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos       (1U)
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN           SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos       (2U)
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN           SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+
+/******************  Bit definition for SYSCFG_CM55PAHBWPR register  **************/
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos       (0U)
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk       (0x1UL << SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK           SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk            /*!< Error capture in write posting buffer */
+
+/******************  Bit definition for SYSCFG_VENCRAMCR register  **************/
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Pos     (0U)
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Msk     (0x1UL << SYSCFG_VENCRAMCR_VENCRAM_EN_Pos)               /*!< 0x00000001 */
+#define SYSCFG_VENCRAMCR_VENCRAM_EN         SYSCFG_VENCRAMCR_VENCRAM_EN_Msk                          /*!< VENCRAM allocation VENC if active, or to system (if VENC inactive) */
+
+/******************  Bit definition for SYSCFG_POTTAMPRSTCR register  **************/
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos       (0U)
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk       (0x1UL << SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos) /*!< 0x00000001 */
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK           SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk            /*!< mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper */
+
+/******************  Bit definition for SYSCFG_ICNEWRCR register  **************/
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos     (0U)
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000001 */
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC1 early-write response */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos     (1U)
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC2 early-write response */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos       (2U)
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000004 */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk              /*!< USB1 early-write response */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos       (3U)
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000008 */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk              /*!< USB2 early-write response */
+
+/******************  Bit definition for SYSCFG_ICNCGCR register  **************/
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos              (1U)
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk            /*!< CPU_NIC clock gating disable */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos              (2U)
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos) /*!< 0x00000004 */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk            /*!< CPU_NOC clock gating disable */
+
+/******************  Bit definition for SYSCFG_IOCR register  **************/
+#define SYSCFG_IOCR_IOCR_Pos                (0U)
+#define SYSCFG_IOCR_IOCR_Msk                (0xFFFFFFFFUL << SYSCFG_IOCR_IOCR_Pos)         /*!< 0xFFFFFFFF */
+#define SYSCFG_IOCR_IOCR                    SYSCFG_IOCR_IOCR_Msk                           /*!< Digital or analog pins */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCCR register  **************/
+#define SYSCFG_VDDIO2CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO2CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCCR_RANSRC            SYSCFG_VDDIO2CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC            SYSCFG_VDDIO2CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO2CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCCR_EN                SYSCFG_VDDIO2CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO2 */
+#define SYSCFG_VDDIO2CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO2CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO2CCCR_CS                SYSCFG_VDDIO2CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCSR register  **************/
+#define SYSCFG_VDDIO2CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO2CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCSR_ANSRC             SYSCFG_VDDIO2CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO2CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO2CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCSR_APSRC             SYSCFG_VDDIO2CCSR_APSRC_Msk
+#define SYSCFG_VDDIO2CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO2CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO2CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCSR_READY             SYSCFG_VDDIO2CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCCR register  **************/
+#define SYSCFG_VDDIO3CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO3CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCCR_RANSRC            SYSCFG_VDDIO3CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC            SYSCFG_VDDIO3CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO3CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCCR_EN                SYSCFG_VDDIO3CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO3 */
+#define SYSCFG_VDDIO3CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO3CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO3CCCR_CS                SYSCFG_VDDIO3CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCSR register  **************/
+#define SYSCFG_VDDIO3CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO3CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCSR_ANSRC             SYSCFG_VDDIO3CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO3CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO3CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCSR_APSRC             SYSCFG_VDDIO3CCSR_APSRC_Msk
+#define SYSCFG_VDDIO3CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO3CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO3CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCSR_READY             SYSCFG_VDDIO3CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCCR register  **************/
+#define SYSCFG_VDDIO4CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO4CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCCR_RANSRC            SYSCFG_VDDIO4CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC            SYSCFG_VDDIO4CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO4CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCCR_EN                SYSCFG_VDDIO4CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO4 */
+#define SYSCFG_VDDIO4CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO4CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO4CCCR_CS                SYSCFG_VDDIO4CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCSR register  **************/
+#define SYSCFG_VDDIO4CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO4CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCSR_ANSRC             SYSCFG_VDDIO4CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO4CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO4CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCSR_APSRC             SYSCFG_VDDIO4CCSR_APSRC_Msk
+#define SYSCFG_VDDIO4CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO4CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO4CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCSR_READY             SYSCFG_VDDIO4CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCCR register  **************/
+#define SYSCFG_VDDIO5CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO5CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCCR_RANSRC            SYSCFG_VDDIO5CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC            SYSCFG_VDDIO5CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO5CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCCR_EN                SYSCFG_VDDIO5CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO5 */
+#define SYSCFG_VDDIO5CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO5CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO5CCCR_CS                SYSCFG_VDDIO5CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCSR register  **************/
+#define SYSCFG_VDDIO5CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO5CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCSR_ANSRC             SYSCFG_VDDIO5CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO5CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO5CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCSR_APSRC             SYSCFG_VDDIO5CCSR_APSRC_Msk
+#define SYSCFG_VDDIO5CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO5CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO5CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCSR_READY             SYSCFG_VDDIO5CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDCCCR register  **************/
+#define SYSCFG_VDDCCCR_RANSRC_Pos           (0U)
+#define SYSCFG_VDDCCCR_RANSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x0000000F */
+#define SYSCFG_VDDCCCR_RANSRC               SYSCFG_VDDCCCR_RANSRC_Msk                      /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDCCCR_RANSRC_0             (0x1UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000001 */
+#define SYSCFG_VDDCCCR_RANSRC_1             (0x2UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000002 */
+#define SYSCFG_VDDCCCR_RANSRC_2             (0x4UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000004 */
+#define SYSCFG_VDDCCCR_RANSRC_3             (0x8UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000008 */
+#define SYSCFG_VDDCCCR_RAPSRC_Pos           (4U)
+#define SYSCFG_VDDCCCR_RAPSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x000000F0 */
+#define SYSCFG_VDDCCCR_RAPSRC               SYSCFG_VDDCCCR_RAPSRC_Msk                      /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDCCCR_RAPSRC_0             (0x1UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000010 */
+#define SYSCFG_VDDCCCR_RAPSRC_1             (0x2UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000020 */
+#define SYSCFG_VDDCCCR_RAPSRC_2             (0x4UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000040 */
+#define SYSCFG_VDDCCCR_RAPSRC_3             (0x8UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000080 */
+#define SYSCFG_VDDCCCR_EN_Pos               (8U)
+#define SYSCFG_VDDCCCR_EN_Msk               (0x1UL << SYSCFG_VDDCCCR_EN_Pos)               /*!< 0x00000100 */
+#define SYSCFG_VDDCCCR_EN                   SYSCFG_VDDCCCR_EN_Msk                          /*!< Enables the compensation cell of I/Os supplied by VDD */
+#define SYSCFG_VDDCCCR_CS_Pos               (9U)
+#define SYSCFG_VDDCCCR_CS_Msk               (0x1UL << SYSCFG_VDDCCCR_CS_Pos)               /*!< 0x00000200 */
+#define SYSCFG_VDDCCCR_CS                   SYSCFG_VDDCCCR_CS_Msk                          /*!< Code selection for the compensation cell of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_VDDCCSR register  **************/
+#define SYSCFG_VDDCCSR_ANSRC_Pos            (0U)
+#define SYSCFG_VDDCCSR_ANSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x0000000F */
+#define SYSCFG_VDDCCSR_ANSRC                SYSCFG_VDDCCSR_ANSRC_Msk
+#define SYSCFG_VDDCCSR_ANSRC_0              (0x1UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000001 */
+#define SYSCFG_VDDCCSR_ANSRC_1              (0x2UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000002 */
+#define SYSCFG_VDDCCSR_ANSRC_2              (0x4UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000004 */
+#define SYSCFG_VDDCCSR_ANSRC_3              (0x8UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000008 */
+#define SYSCFG_VDDCCSR_APSRC_Pos            (4U)
+#define SYSCFG_VDDCCSR_APSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x000000F0 */
+#define SYSCFG_VDDCCSR_APSRC                SYSCFG_VDDCCSR_APSRC_Msk
+#define SYSCFG_VDDCCSR_APSRC_0              (0x1UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000010 */
+#define SYSCFG_VDDCCSR_APSRC_1              (0x2UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000020 */
+#define SYSCFG_VDDCCSR_APSRC_2              (0x4UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000040 */
+#define SYSCFG_VDDCCSR_APSRC_3              (0x8UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000080 */
+#define SYSCFG_VDDCCSR_READY_Pos            (8U)
+#define SYSCFG_VDDCCSR_READY_Msk            (0x1UL << SYSCFG_VDDCCSR_READY_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDCCSR_READY                SYSCFG_VDDCCSR_READY_Msk                       /*!< Provides the compensation cell status of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_CBR register  **************/
+#define SYSCFG_CBR_CM55L_Pos                (0U)
+#define SYSCFG_CBR_CM55L_Msk                (0x1UL << SYSCFG_CBR_CM55L_Pos)                /*!< 0x00000001 */
+#define SYSCFG_CBR_CM55L                    SYSCFG_CBR_CM55L_Msk                           /*!< CM55 lockup lock enable */
+#define SYSCFG_CBR_PVDL_LOCK_Pos            (2U)
+#define SYSCFG_CBR_PVDL_LOCK_Msk            (0x1UL << SYSCFG_CBR_PVDL_LOCK_Pos)            /*!< 0x00000004 */
+#define SYSCFG_CBR_PVDL_LOCK                SYSCFG_CBR_PVDL_LOCK_Msk                       /*!< PVD lock enable */
+#define SYSCFG_CBR_BKPRAML_Pos              (8U)
+#define SYSCFG_CBR_BKPRAML_Msk              (0x1UL << SYSCFG_CBR_BKPRAML_Pos)              /*!< 0x00000100 */
+#define SYSCFG_CBR_BKPRAML                  SYSCFG_CBR_BKPRAML_Msk                         /*!< Backup SRAM double ECC error lock */
+#define SYSCFG_CBR_CM55CACHEL_Pos           (9U)
+#define SYSCFG_CBR_CM55CACHEL_Msk           (0x1UL << SYSCFG_CBR_CM55CACHEL_Pos)           /*!< 0x00000200 */
+#define SYSCFG_CBR_CM55CACHEL               SYSCFG_CBR_CM55CACHEL_Msk                      /*!< CM55 cache double ECC error lock */
+#define SYSCFG_CBR_CM55TCML_Pos             (10U)
+#define SYSCFG_CBR_CM55TCML_Msk             (0x1UL << SYSCFG_CBR_CM55TCML_Pos)             /*!< 0x00000400 */
+#define SYSCFG_CBR_CM55TCML                 SYSCFG_CBR_CM55TCML_Msk                        /*!< CM55 TCM double ECC error lock */
+
+/******************  Bit definition for SYSCFG_SEC_AIDCR register  **************/
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Pos     (0U)
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Msk     (0x7UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x0000000F */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC         SYSCFG_SEC_AIDCR_DMACID_SEC_Msk                /* Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_0       (0x1UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000001 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_1       (0x2UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_2       (0x4UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000004 */
+
+/******************  Bit definition for SYSCFG_FMC_RETIMECR register  **************/
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos       (0U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos) /*!< 0x00000001 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX           SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk            /*!< Retiming on Rx path */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos       (1U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos) /*!< 0x00000002 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX           SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk            /*!< Retiming on Tx path */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos         (2U)
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk         (0x1UL << SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos)   /*!< 0x00000004 */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180             SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk              /*!< Delay on feedback clock */
+
+/******************  Bit definition for SYSCFG_BOOTSR register  **************/
+#define SYSCFG_BOOTSR_BOOT0_Pos             (0U)
+#define SYSCFG_BOOTSR_BOOT0_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT0_Pos)             /*!< 0x00000001 */
+#define SYSCFG_BOOTSR_BOOT0                 SYSCFG_BOOTSR_BOOT0_Msk                        /*!< BOOT0 pin value */
+#define SYSCFG_BOOTSR_BOOT1_Pos             (1U)
+#define SYSCFG_BOOTSR_BOOT1_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT1_Pos)             /*!< 0x00000002 */
+#define SYSCFG_BOOTSR_BOOT1                 SYSCFG_BOOTSR_BOOT1_Msk                        /*!< BOOT1 pin value */
+
+/******************  Bit definition for SYSCFG_AHBWP_ERROR_SR register  **************/
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos  (0U)
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk  (0xFFFFFFFFUL << SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR      SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk                   /*!< Reports address of the first error in P-AHB write-posting buffer */
+
+/******************  Bit definition for SYSCFG_SECPRIV_AIDCR register  **************/
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos  (0U)
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk  (0x7UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x0000000F */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC      SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk             /* Non-Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_0    (0x1UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000001 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_1    (0x2UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000002 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_2    (0x4UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000004 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Tamper and backup register (TAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for TAMP_CR1 register  *****************/
+#define TAMP_CR1_TAMP1E_Pos                 (0U)
+#define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
+#define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
+#define TAMP_CR1_TAMP2E_Pos                 (1U)
+#define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
+#define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
+#define TAMP_CR1_TAMP3E_Pos                 (2U)
+#define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
+#define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
+#define TAMP_CR1_TAMP4E_Pos                 (3U)
+#define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
+#define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
+#define TAMP_CR1_TAMP5E_Pos                 (4U)
+#define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
+#define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
+#define TAMP_CR1_TAMP6E_Pos                 (5U)
+#define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
+#define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
+#define TAMP_CR1_TAMP7E_Pos                 (6U)
+#define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
+#define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
+#define TAMP_CR1_ITAMP1E_Pos                (16U)
+#define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
+#define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
+#define TAMP_CR1_ITAMP2E_Pos                (17U)
+#define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
+#define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
+#define TAMP_CR1_ITAMP3E_Pos                (18U)
+#define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
+#define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
+#define TAMP_CR1_ITAMP4E_Pos                (19U)
+#define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
+#define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
+#define TAMP_CR1_ITAMP5E_Pos                (20U)
+#define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
+#define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
+#define TAMP_CR1_ITAMP6E_Pos                (21U)
+#define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
+#define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
+#define TAMP_CR1_ITAMP7E_Pos                (22U)
+#define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
+#define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
+#define TAMP_CR1_ITAMP8E_Pos                (23U)
+#define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
+#define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
+#define TAMP_CR1_ITAMP9E_Pos                (24U)
+#define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
+#define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
+#define TAMP_CR1_ITAMP11E_Pos               (26U)
+#define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
+#define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
+
+/********************  Bits definition for TAMP_CR2 register  *****************/
+#define TAMP_CR2_TAMP1POM_Pos               (0U)
+#define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk
+#define TAMP_CR2_TAMP2POM_Pos               (1U)
+#define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk
+#define TAMP_CR2_TAMP3POM_Pos               (2U)
+#define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
+#define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk
+#define TAMP_CR2_TAMP4POM_Pos               (3U)
+#define TAMP_CR2_TAMP4POM_Msk               (0x1UL << TAMP_CR2_TAMP4POM_Pos)        /*!< 0x00000008 */
+#define TAMP_CR2_TAMP4POM                   TAMP_CR2_TAMP4POM_Msk
+#define TAMP_CR2_TAMP5POM_Pos               (4U)
+#define TAMP_CR2_TAMP5POM_Msk               (0x1UL << TAMP_CR2_TAMP5POM_Pos)        /*!< 0x00000010 */
+#define TAMP_CR2_TAMP5POM                   TAMP_CR2_TAMP5POM_Msk
+#define TAMP_CR2_TAMP6POM_Pos               (5U)
+#define TAMP_CR2_TAMP6POM_Msk               (0x1UL << TAMP_CR2_TAMP6POM_Pos)        /*!< 0x00000020 */
+#define TAMP_CR2_TAMP6POM                   TAMP_CR2_TAMP6POM_Msk
+#define TAMP_CR2_TAMP7POM_Pos               (6U)
+#define TAMP_CR2_TAMP7POM_Msk               (0x1UL << TAMP_CR2_TAMP7POM_Pos)        /*!< 0x00000040 */
+#define TAMP_CR2_TAMP7POM                   TAMP_CR2_TAMP7POM_Msk
+#define TAMP_CR2_TAMP1MSK_Pos               (16U)
+#define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos               (17U)
+#define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP3MSK_Pos               (18U)
+#define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
+#define TAMP_CR2_BKBLOCK_Pos                (22U)
+#define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
+#define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
+#define TAMP_CR2_BKERASE_Pos                (23U)
+#define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
+#define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
+#define TAMP_CR2_TAMP1TRG_Pos               (24U)
+#define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos               (25U)
+#define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
+#define TAMP_CR2_TAMP3TRG_Pos               (26U)
+#define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
+#define TAMP_CR2_TAMP4TRG_Pos               (27U)
+#define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
+#define TAMP_CR2_TAMP5TRG_Pos               (28U)
+#define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
+#define TAMP_CR2_TAMP6TRG_Pos               (29U)
+#define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
+#define TAMP_CR2_TAMP7TRG_Pos               (30U)
+#define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
+
+/********************  Bits definition for TAMP_CR3 register  *****************/
+#define TAMP_CR3_ITAMP1POM_Pos              (0U)
+#define TAMP_CR3_ITAMP1POM_Msk              (0x1UL << TAMP_CR3_ITAMP1POM_Pos)       /*!< 0x00000001 */
+#define TAMP_CR3_ITAMP1POM                  TAMP_CR3_ITAMP1POM_Msk
+#define TAMP_CR3_ITAMP2POM_Pos              (1U)
+#define TAMP_CR3_ITAMP2POM_Msk              (0x1UL << TAMP_CR3_ITAMP2POM_Pos)       /*!< 0x00000002 */
+#define TAMP_CR3_ITAMP2POM                  TAMP_CR3_ITAMP2POM_Msk
+#define TAMP_CR3_ITAMP3POM_Pos              (2U)
+#define TAMP_CR3_ITAMP3POM_Msk              (0x1UL << TAMP_CR3_ITAMP3POM_Pos)       /*!< 0x00000004 */
+#define TAMP_CR3_ITAMP3POM                  TAMP_CR3_ITAMP3POM_Msk
+#define TAMP_CR3_ITAMP4POM_Pos              (3U)
+#define TAMP_CR3_ITAMP4POM_Msk              (0x1UL << TAMP_CR3_ITAMP4POM_Pos)       /*!< 0x00000008 */
+#define TAMP_CR3_ITAMP4POM                  TAMP_CR3_ITAMP4POM_Msk
+#define TAMP_CR3_ITAMP5POM_Pos              (4U)
+#define TAMP_CR3_ITAMP5POM_Msk              (0x1UL << TAMP_CR3_ITAMP5POM_Pos)       /*!< 0x00000010 */
+#define TAMP_CR3_ITAMP5POM                  TAMP_CR3_ITAMP5POM_Msk
+#define TAMP_CR3_ITAMP6POM_Pos              (5U)
+#define TAMP_CR3_ITAMP6POM_Msk              (0x1UL << TAMP_CR3_ITAMP6POM_Pos)       /*!< 0x00000020 */
+#define TAMP_CR3_ITAMP6POM                  TAMP_CR3_ITAMP6POM_Msk
+#define TAMP_CR3_ITAMP7POM_Pos              (6U)
+#define TAMP_CR3_ITAMP7POM_Msk              (0x1UL << TAMP_CR3_ITAMP7POM_Pos)       /*!< 0x00000040 */
+#define TAMP_CR3_ITAMP7POM                  TAMP_CR3_ITAMP7POM_Msk
+#define TAMP_CR3_ITAMP8POM_Pos              (7U)
+#define TAMP_CR3_ITAMP8POM_Msk              (0x1UL << TAMP_CR3_ITAMP8POM_Pos)       /*!< 0x00000080 */
+#define TAMP_CR3_ITAMP8POM                  TAMP_CR3_ITAMP8POM_Msk
+#define TAMP_CR3_ITAMP9POM_Pos              (8U)
+#define TAMP_CR3_ITAMP9POM_Msk              (0x1UL << TAMP_CR3_ITAMP9POM_Pos)       /*!< 0x00000100 */
+#define TAMP_CR3_ITAMP9POM                  TAMP_CR3_ITAMP9POM_Msk
+#define TAMP_CR3_ITAMP11POM_Pos             (10U)
+#define TAMP_CR3_ITAMP11POM_Msk             (0x1UL << TAMP_CR3_ITAMP11POM_Pos)      /*!< 0x00000400 */
+#define TAMP_CR3_ITAMP11POM                 TAMP_CR3_ITAMP11POM_Msk
+
+/********************  Bits definition for TAMP_FLTCR register  ***************/
+#define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
+#define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
+#define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
+#define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
+#define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
+#define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
+#define TAMP_FLTCR_TAMPFLT_Pos              (3U)
+#define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
+#define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
+#define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
+#define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
+#define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
+#define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
+#define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
+#define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
+#define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
+#define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
+#define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
+#define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
+
+/********************  Bits definition for TAMP_ATCR1 register  ***************/
+#define TAMP_ATCR1_TAMP1AM_Pos              (0U)
+#define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
+#define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
+#define TAMP_ATCR1_TAMP2AM_Pos              (1U)
+#define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
+#define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
+#define TAMP_ATCR1_TAMP3AM_Pos              (2U)
+#define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
+#define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
+#define TAMP_ATCR1_TAMP4AM_Pos              (3U)
+#define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
+#define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
+#define TAMP_ATCR1_TAMP5AM_Pos              (4U)
+#define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
+#define TAMP_ATCR1_TAMP6AM_Pos              (5U)
+#define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
+#define TAMP_ATCR1_TAMP7AM_Pos              (6U)
+#define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
+#define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
+#define TAMP_ATCR1_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
+#define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
+#define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR1_ATOSEL2_Pos              (10U)
+#define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
+#define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
+#define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR1_ATOSEL3_Pos              (12U)
+#define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
+#define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
+#define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR1_ATOSEL4_Pos              (14U)
+#define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
+#define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
+#define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR1_ATCKSEL_Pos              (16U)
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
+#define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
+#define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR1_ATPER_Pos                (24U)
+#define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
+#define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
+#define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
+#define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
+#define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
+#define TAMP_ATCR1_ATOSHARE_Pos             (30U)
+#define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
+#define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
+#define TAMP_ATCR1_FLTEN_Pos                (31U)
+#define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
+#define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
+
+/********************  Bits definition for TAMP_ATSEEDR register  ******************/
+#define TAMP_ATSEEDR_SEED_Pos               (0U)
+#define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
+
+/********************  Bits definition for TAMP_ATOR register  ******************/
+#define TAMP_ATOR_PRNG_Pos                  (0U)
+#define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)          /*!< 0x000000FF */
+#define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
+#define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
+#define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
+#define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
+#define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
+#define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
+#define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
+#define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
+#define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
+#define TAMP_ATOR_SEEDF_Pos                 (14U)
+#define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
+#define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
+#define TAMP_ATOR_INITS_Pos                 (15U)
+#define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
+#define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
+
+/********************  Bits definition for TAMP_ATCR2 register  ***************/
+#define TAMP_ATCR2_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
+#define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
+#define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR2_ATOSEL2_Pos              (11U)
+#define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
+#define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
+#define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR2_ATOSEL3_Pos              (14U)
+#define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
+#define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
+#define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR2_ATOSEL4_Pos              (17U)
+#define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
+#define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
+#define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR2_ATOSEL5_Pos              (20U)
+#define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
+#define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
+#define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
+#define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
+#define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
+#define TAMP_ATCR2_ATOSEL6_Pos              (23U)
+#define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
+#define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
+#define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
+#define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
+#define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
+#define TAMP_ATCR2_ATOSEL7_Pos              (26U)
+#define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
+#define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
+#define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
+#define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
+#define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
+
+/********************  Bits definition for TAMP_SECCFGR register  *************/
+#define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
+#define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
+#define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
+#define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
+#define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
+#define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
+#define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
+#define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
+#define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
+#define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
+#define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
+#define TAMP_SECCFGR_CNT1SEC_Pos            (15U)
+#define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)     /*!< 0x00008000 */
+#define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
+#define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
+#define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
+#define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
+#define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
+#define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
+#define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
+#define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
+#define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
+#define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
+#define TAMP_SECCFGR_BHKLOCK_Pos            (30U)
+#define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
+#define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
+#define TAMP_SECCFGR_TAMPSEC_Pos            (31U)
+#define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
+#define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk
+
+/********************  Bits definition for TAMP_PRIVCFGR register  ************/
+#define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
+#define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
+#define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
+#define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
+#define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
+#define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
+#define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
+#define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
+#define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
+#define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
+
+/********************  Bits definition for TAMP_IER register  *****************/
+#define TAMP_IER_TAMP1IE_Pos                (0U)
+#define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
+#define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
+#define TAMP_IER_TAMP2IE_Pos                (1U)
+#define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
+#define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
+#define TAMP_IER_TAMP3IE_Pos                (2U)
+#define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
+#define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
+#define TAMP_IER_TAMP4IE_Pos                (3U)
+#define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
+#define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
+#define TAMP_IER_TAMP5IE_Pos                (4U)
+#define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
+#define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
+#define TAMP_IER_TAMP6IE_Pos                (5U)
+#define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
+#define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
+#define TAMP_IER_TAMP7IE_Pos                (6U)
+#define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
+#define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
+#define TAMP_IER_ITAMP1IE_Pos               (16U)
+#define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
+#define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
+#define TAMP_IER_ITAMP2IE_Pos               (17U)
+#define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
+#define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
+#define TAMP_IER_ITAMP3IE_Pos               (18U)
+#define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
+#define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
+#define TAMP_IER_ITAMP4IE_Pos               (19U)
+#define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
+#define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
+#define TAMP_IER_ITAMP5IE_Pos               (20U)
+#define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
+#define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
+#define TAMP_IER_ITAMP6IE_Pos               (21U)
+#define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
+#define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
+#define TAMP_IER_ITAMP7IE_Pos               (22U)
+#define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
+#define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
+#define TAMP_IER_ITAMP8IE_Pos               (23U)
+#define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
+#define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
+#define TAMP_IER_ITAMP9IE_Pos               (24U)
+#define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
+#define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
+#define TAMP_IER_ITAMP11IE_Pos              (26U)
+#define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
+#define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
+
+/********************  Bits definition for TAMP_SR register  *****************/
+#define TAMP_SR_TAMP1F_Pos                  (0U)
+#define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
+#define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
+#define TAMP_SR_TAMP2F_Pos                  (1U)
+#define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
+#define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
+#define TAMP_SR_TAMP3F_Pos                  (2U)
+#define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
+#define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
+#define TAMP_SR_TAMP4F_Pos                  (3U)
+#define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
+#define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
+#define TAMP_SR_TAMP5F_Pos                  (4U)
+#define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
+#define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
+#define TAMP_SR_TAMP6F_Pos                  (5U)
+#define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
+#define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
+#define TAMP_SR_TAMP7F_Pos                  (6U)
+#define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
+#define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
+#define TAMP_SR_ITAMP1F_Pos                 (16U)
+#define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
+#define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
+#define TAMP_SR_ITAMP2F_Pos                 (17U)
+#define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
+#define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
+#define TAMP_SR_ITAMP3F_Pos                 (18U)
+#define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
+#define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
+#define TAMP_SR_ITAMP4F_Pos                 (19U)
+#define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
+#define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
+#define TAMP_SR_ITAMP5F_Pos                 (20U)
+#define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
+#define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
+#define TAMP_SR_ITAMP6F_Pos                 (21U)
+#define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
+#define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
+#define TAMP_SR_ITAMP7F_Pos                 (22U)
+#define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
+#define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
+#define TAMP_SR_ITAMP8F_Pos                 (23U)
+#define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
+#define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
+#define TAMP_SR_ITAMP9F_Pos                 (24U)
+#define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
+#define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
+#define TAMP_SR_ITAMP11F_Pos                (26U)
+#define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
+#define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
+
+/********************  Bits definition for TAMP_MISR register  ****************/
+#define TAMP_MISR_TAMP1MF_Pos               (0U)
+#define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
+#define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
+#define TAMP_MISR_TAMP2MF_Pos               (1U)
+#define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
+#define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
+#define TAMP_MISR_TAMP3MF_Pos               (2U)
+#define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
+#define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
+#define TAMP_MISR_TAMP4MF_Pos               (3U)
+#define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
+#define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
+#define TAMP_MISR_TAMP5MF_Pos               (4U)
+#define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
+#define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
+#define TAMP_MISR_TAMP6MF_Pos               (5U)
+#define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
+#define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
+#define TAMP_MISR_TAMP7MF_Pos               (6U)
+#define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
+#define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
+#define TAMP_MISR_ITAMP1MF_Pos              (16U)
+#define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
+#define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
+#define TAMP_MISR_ITAMP2MF_Pos              (17U)
+#define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
+#define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
+#define TAMP_MISR_ITAMP3MF_Pos              (18U)
+#define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
+#define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
+#define TAMP_MISR_ITAMP4MF_Pos              (19U)
+#define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
+#define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
+#define TAMP_MISR_ITAMP5MF_Pos              (20U)
+#define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
+#define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
+#define TAMP_MISR_ITAMP6MF_Pos              (21U)
+#define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
+#define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
+#define TAMP_MISR_ITAMP7MF_Pos              (22U)
+#define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
+#define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
+#define TAMP_MISR_ITAMP8MF_Pos              (23U)
+#define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
+#define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
+#define TAMP_MISR_ITAMP9MF_Pos              (24U)
+#define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
+#define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
+#define TAMP_MISR_ITAMP11MF_Pos             (26U)
+#define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
+#define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SMISR register  ************ *****/
+#define TAMP_SMISR_TAMP1MF_Pos              (0U)
+#define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
+#define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
+#define TAMP_SMISR_TAMP2MF_Pos              (1U)
+#define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
+#define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
+#define TAMP_SMISR_TAMP3MF_Pos              (2U)
+#define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
+#define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
+#define TAMP_SMISR_TAMP4MF_Pos              (3U)
+#define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
+#define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
+#define TAMP_SMISR_TAMP5MF_Pos              (4U)
+#define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
+#define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
+#define TAMP_SMISR_TAMP6MF_Pos              (5U)
+#define TAMP_SMISR_TAMP6MF_Msk              (0x1UL << TAMP_SMISR_TAMP6MF_Pos)       /*!< 0x00000020 */
+#define TAMP_SMISR_TAMP6MF                  TAMP_SMISR_TAMP6MF_Msk
+#define TAMP_SMISR_TAMP7MF_Pos              (6U)
+#define TAMP_SMISR_TAMP7MF_Msk              (0x1UL << TAMP_SMISR_TAMP7MF_Pos)       /*!< 0x00000040 */
+#define TAMP_SMISR_TAMP7MF                  TAMP_SMISR_TAMP7MF_Msk
+#define TAMP_SMISR_ITAMP1MF_Pos             (16U)
+#define TAMP_SMISR_ITAMP1MF_Msk             (0x1UL << TAMP_SMISR_ITAMP1MF_Pos)      /*!< 0x00010000 */
+#define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
+#define TAMP_SMISR_ITAMP2MF_Pos             (17U)
+#define TAMP_SMISR_ITAMP2MF_Msk             (0x1UL << TAMP_SMISR_ITAMP2MF_Pos)      /*!< 0x00020000 */
+#define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
+#define TAMP_SMISR_ITAMP3MF_Pos             (18U)
+#define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
+#define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
+#define TAMP_SMISR_ITAMP4MF_Pos             (19U)
+#define TAMP_SMISR_ITAMP4MF_Msk             (0x1UL << TAMP_SMISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
+#define TAMP_SMISR_ITAMP4MF                 TAMP_SMISR_ITAMP4MF_Msk
+#define TAMP_SMISR_ITAMP5MF_Pos             (20U)
+#define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
+#define TAMP_SMISR_ITAMP6MF_Pos             (21U)
+#define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
+#define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
+#define TAMP_SMISR_ITAMP7MF_Pos             (22U)
+#define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
+#define TAMP_SMISR_ITAMP8MF_Pos             (23U)
+#define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
+#define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
+#define TAMP_SMISR_ITAMP9MF_Pos             (24U)
+#define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
+#define TAMP_SMISR_ITAMP11MF_Pos            (26U)
+#define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SCR register  *****************/
+#define TAMP_SCR_CTAMP1F_Pos                (0U)
+#define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
+#define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
+#define TAMP_SCR_CTAMP2F_Pos                (1U)
+#define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
+#define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
+#define TAMP_SCR_CTAMP3F_Pos                (2U)
+#define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
+#define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
+#define TAMP_SCR_CTAMP4F_Pos                (3U)
+#define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
+#define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
+#define TAMP_SCR_CTAMP5F_Pos                (4U)
+#define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
+#define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
+#define TAMP_SCR_CTAMP6F_Pos                (5U)
+#define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
+#define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
+#define TAMP_SCR_CTAMP7F_Pos                (6U)
+#define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
+#define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
+#define TAMP_SCR_CTAMP8F_Pos                (7U)
+#define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
+#define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
+#define TAMP_SCR_CITAMP1F_Pos               (16U)
+#define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
+#define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
+#define TAMP_SCR_CITAMP2F_Pos               (17U)
+#define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
+#define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
+#define TAMP_SCR_CITAMP3F_Pos               (18U)
+#define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
+#define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
+#define TAMP_SCR_CITAMP4F_Pos               (19U)
+#define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
+#define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
+#define TAMP_SCR_CITAMP5F_Pos               (20U)
+#define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
+#define TAMP_SCR_CITAMP6F_Pos               (21U)
+#define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
+#define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
+#define TAMP_SCR_CITAMP7F_Pos               (22U)
+#define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
+#define TAMP_SCR_CITAMP8F_Pos               (23U)
+#define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
+#define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
+#define TAMP_SCR_CITAMP9F_Pos               (24U)
+#define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
+#define TAMP_SCR_CITAMP11F_Pos              (26U)
+#define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
+
+/********************  Bits definition for TAMP_COUNT1R register  ***************/
+#define TAMP_COUNT1R_COUNT_Pos              (0U)
+#define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
+#define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
+
+/********************  Bits definition for TAMP_OR register  ***************/
+#define TAMP_OR_VCOREMEN_Pos                (0U)
+#define TAMP_OR_VCOREMEN_Msk                (0x1UL << TAMP_OR_VCOREMEN_Pos)         /*!< 0x00000001 */
+#define TAMP_OR_VCOREMEN                    TAMP_OR_VCOREMEN_Msk
+
+/********************  Bits definition for TAMP_RPCFGR register  ***************/
+#define TAMP_RPCFGR_RPCFG0_Pos              (0U)
+#define TAMP_RPCFGR_RPCFG0_Msk              (0x1UL << TAMP_RPCFGR_RPCFG0_Pos)       /*!< 0x00000001 */
+#define TAMP_RPCFGR_RPCFG0                  TAMP_RPCFGR_RPCFG0_Msk
+
+/********************  Bits definition for TAMP_BKP0R register  ***************/
+#define TAMP_BKP0R_Pos                      (0U)
+#define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP0R                          TAMP_BKP0R_Msk
+
+/********************  Bits definition for TAMP_BKP1R register  ****************/
+#define TAMP_BKP1R_Pos                      (0U)
+#define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP1R                          TAMP_BKP1R_Msk
+
+/********************  Bits definition for TAMP_BKP2R register  ****************/
+#define TAMP_BKP2R_Pos                      (0U)
+#define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP2R                          TAMP_BKP2R_Msk
+
+/********************  Bits definition for TAMP_BKP3R register  ****************/
+#define TAMP_BKP3R_Pos                      (0U)
+#define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP3R                          TAMP_BKP3R_Msk
+
+/********************  Bits definition for TAMP_BKP4R register  ****************/
+#define TAMP_BKP4R_Pos                      (0U)
+#define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP4R                          TAMP_BKP4R_Msk
+
+/********************  Bits definition for TAMP_BKP5R register  ****************/
+#define TAMP_BKP5R_Pos                      (0U)
+#define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP5R                          TAMP_BKP5R_Msk
+
+/********************  Bits definition for TAMP_BKP6R register  ****************/
+#define TAMP_BKP6R_Pos                      (0U)
+#define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP6R                          TAMP_BKP6R_Msk
+
+/********************  Bits definition for TAMP_BKP7R register  ****************/
+#define TAMP_BKP7R_Pos                      (0U)
+#define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP7R                          TAMP_BKP7R_Msk
+
+/********************  Bits definition for TAMP_BKP8R register  ****************/
+#define TAMP_BKP8R_Pos                      (0U)
+#define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP8R                          TAMP_BKP8R_Msk
+
+/********************  Bits definition for TAMP_BKP9R register  ****************/
+#define TAMP_BKP9R_Pos                      (0U)
+#define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP9R                          TAMP_BKP9R_Msk
+
+/********************  Bits definition for TAMP_BKP10R register  ***************/
+#define TAMP_BKP10R_Pos                     (0U)
+#define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP10R                         TAMP_BKP10R_Msk
+
+/********************  Bits definition for TAMP_BKP11R register  ***************/
+#define TAMP_BKP11R_Pos                     (0U)
+#define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP11R                         TAMP_BKP11R_Msk
+
+/********************  Bits definition for TAMP_BKP12R register  ***************/
+#define TAMP_BKP12R_Pos                     (0U)
+#define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP12R                         TAMP_BKP12R_Msk
+
+/********************  Bits definition for TAMP_BKP13R register  ***************/
+#define TAMP_BKP13R_Pos                     (0U)
+#define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP13R                         TAMP_BKP13R_Msk
+
+/********************  Bits definition for TAMP_BKP14R register  ***************/
+#define TAMP_BKP14R_Pos                     (0U)
+#define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP14R                         TAMP_BKP14R_Msk
+
+/********************  Bits definition for TAMP_BKP15R register  ***************/
+#define TAMP_BKP15R_Pos                     (0U)
+#define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP15R                         TAMP_BKP15R_Msk
+
+/********************  Bits definition for TAMP_BKP16R register  ***************/
+#define TAMP_BKP16R_Pos                     (0U)
+#define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP16R                         TAMP_BKP16R_Msk
+
+/********************  Bits definition for TAMP_BKP17R register  ***************/
+#define TAMP_BKP17R_Pos                     (0U)
+#define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP17R                         TAMP_BKP17R_Msk
+
+/********************  Bits definition for TAMP_BKP18R register  ***************/
+#define TAMP_BKP18R_Pos                     (0U)
+#define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP18R                         TAMP_BKP18R_Msk
+
+/********************  Bits definition for TAMP_BKP19R register  ***************/
+#define TAMP_BKP19R_Pos                     (0U)
+#define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP19R                         TAMP_BKP19R_Msk
+
+/********************  Bits definition for TAMP_BKP20R register  ***************/
+#define TAMP_BKP20R_Pos                     (0U)
+#define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP20R                         TAMP_BKP20R_Msk
+
+/********************  Bits definition for TAMP_BKP21R register  ***************/
+#define TAMP_BKP21R_Pos                     (0U)
+#define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP21R                         TAMP_BKP21R_Msk
+
+/********************  Bits definition for TAMP_BKP22R register  ***************/
+#define TAMP_BKP22R_Pos                     (0U)
+#define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP22R                         TAMP_BKP22R_Msk
+
+/********************  Bits definition for TAMP_BKP23R register  ***************/
+#define TAMP_BKP23R_Pos                     (0U)
+#define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP23R                         TAMP_BKP23R_Msk
+
+/********************  Bits definition for TAMP_BKP24R register  ***************/
+#define TAMP_BKP24R_Pos                     (0U)
+#define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP24R                         TAMP_BKP24R_Msk
+
+/********************  Bits definition for TAMP_BKP25R register  ***************/
+#define TAMP_BKP25R_Pos                     (0U)
+#define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP25R                         TAMP_BKP25R_Msk
+
+/********************  Bits definition for TAMP_BKP26R register  ***************/
+#define TAMP_BKP26R_Pos                     (0U)
+#define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP26R                         TAMP_BKP26R_Msk
+
+/********************  Bits definition for TAMP_BKP27R register  ***************/
+#define TAMP_BKP27R_Pos                     (0U)
+#define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP27R                         TAMP_BKP27R_Msk
+
+/********************  Bits definition for TAMP_BKP28R register  ***************/
+#define TAMP_BKP28R_Pos                     (0U)
+#define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP28R                         TAMP_BKP28R_Msk
+
+/********************  Bits definition for TAMP_BKP29R register  ***************/
+#define TAMP_BKP29R_Pos                     (0U)
+#define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP29R                         TAMP_BKP29R_Msk
+
+/********************  Bits definition for TAMP_BKP30R register  ***************/
+#define TAMP_BKP30R_Pos                     (0U)
+#define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP30R                         TAMP_BKP30R_Msk
+
+/********************  Bits definition for TAMP_BKP31R register  ***************/
+#define TAMP_BKP31R_Pos                     (0U)
+#define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP31R                         TAMP_BKP31R_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+#define TIM_CR1_DITHEN_Pos        (12U)
+#define TIM_CR1_DITHEN_Msk        (0x1UL << TIM_CR1_DITHEN_Pos)                /*!< 0x00001000 */
+#define TIM_CR1_DITHEN            TIM_CR1_DITHEN_Msk                           /*!<Dithering enable */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (     0x1UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (     0x2UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (     0x4UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
+#define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS4N_Pos         (15U)
+#define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
+#define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
+#define TIM_CR2_ADSYNC_Pos        (28U)
+#define TIM_CR2_ADSYNC_Msk        (0x1UL << TIM_CR2_ADSYNC_Pos)                /*!< 0x10000000 */
+#define TIM_CR2_ADSYNC            TIM_CR2_ADSYNC_Msk                           /*!<ADC synchronization */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+#define TIM_SMCR_SMSPE_Pos        (24U)
+#define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
+#define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
+#define TIM_SMCR_SMSPS_Pos        (25U)
+#define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
+#define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+#define TIM_DIER_IDXIE_Pos        (20U)
+#define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
+#define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
+#define TIM_DIER_DIRIE_Pos        (21U)
+#define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
+#define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
+#define TIM_DIER_IERRIE_Pos       (22U)
+#define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
+#define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
+#define TIM_DIER_TERRIE_Pos       (23U)
+#define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
+#define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_IDXF_Pos           (20U)
+#define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
+#define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
+#define TIM_SR_DIRF_Pos           (21U)
+#define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
+#define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
+#define TIM_SR_IERRF_Pos          (22U)
+#define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
+#define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
+#define TIM_SR_TERRF_Pos          (23U)
+#define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
+#define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NE_Pos        (14U)
+#define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
+#define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFUL << TIM_CCR5_CCR5_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFFUL << TIM_CCR6_CCR6_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_DTR2 register  *********************/
+#define TIM_DTR2_DTGF_Pos         (0U)
+#define TIM_DTR2_DTGF_Msk         (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
+#define TIM_DTR2_DTGF             TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
+#define TIM_DTR2_DTGF_0           (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
+#define TIM_DTR2_DTGF_1           (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
+#define TIM_DTR2_DTGF_2           (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
+#define TIM_DTR2_DTGF_3           (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
+#define TIM_DTR2_DTGF_4           (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
+#define TIM_DTR2_DTGF_5           (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
+#define TIM_DTR2_DTGF_6           (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
+#define TIM_DTR2_DTGF_7           (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
+#define TIM_DTR2_DTAE_Pos         (16U)
+#define TIM_DTR2_DTAE_Msk         (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
+#define TIM_DTR2_DTAE             TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
+#define TIM_DTR2_DTPE_Pos         (17U)
+#define TIM_DTR2_DTPE_Msk         (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
+#define TIM_DTR2_DTPE             TIM_DTR2_DTPE_Msk                            /*!<Deadtime preload enable */
+
+/*******************  Bit definition for TIM_ECR register  *********************/
+#define TIM_ECR_IE_Pos            (0U)
+#define TIM_ECR_IE_Msk            (0x1UL << TIM_ECR_IE_Pos)                    /*!< 0x00000001 */
+#define TIM_ECR_IE                TIM_ECR_IE_Msk                               /*!<Index enable */
+#define TIM_ECR_IDIR_Pos          (1U)
+#define TIM_ECR_IDIR_Msk          (0x3UL << TIM_ECR_IDIR_Pos)                  /*!< 0x00000006 */
+#define TIM_ECR_IDIR              TIM_ECR_IDIR_Msk                             /*!<IDIR[1:0] bits (Index direction)*/
+#define TIM_ECR_IDIR_0            (0x01UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000001 */
+#define TIM_ECR_IDIR_1            (0x02UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000002 */
+#define TIM_ECR_IBLK_Pos          (3U)
+#define TIM_ECR_IBLK_Msk          (0x3UL << TIM_ECR_IBLK_Pos)                  /*!< 0x00000018 */
+#define TIM_ECR_IBLK              TIM_ECR_IBLK_Msk                             /*!<IBLK[1:0] bits (Index blanking)*/
+#define TIM_ECR_IBLK_0            (0x01UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000008 */
+#define TIM_ECR_IBLK_1            (0x02UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000010 */
+#define TIM_ECR_FIDX_Pos          (5U)
+#define TIM_ECR_FIDX_Msk          (0x1UL << TIM_ECR_FIDX_Pos)                  /*!< 0x00000020 */
+#define TIM_ECR_FIDX              TIM_ECR_FIDX_Msk                             /*!<First index enable */
+#define TIM_ECR_IPOS_Pos          (6U)
+#define TIM_ECR_IPOS_Msk          (0x3UL << TIM_ECR_IPOS_Pos)                  /*!< 0x000000C0 */
+#define TIM_ECR_IPOS              TIM_ECR_IPOS_Msk                             /*!<IPOS[1:0] bits (Index positioning)*/
+#define TIM_ECR_IPOS_0            (0x01UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000040 */
+#define TIM_ECR_IPOS_1            (0x02UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000080 */
+#define TIM_ECR_PW_Pos            (16U)
+#define TIM_ECR_PW_Msk            (0xFFUL << TIM_ECR_PW_Pos)                   /*!< 0x00FF0000 */
+#define TIM_ECR_PW                TIM_ECR_PW_Msk                               /*!<PW[7:0] bits (Pulse width)*/
+#define TIM_ECR_PW_0              (0x01UL << TIM_ECR_PW_Pos)                   /*!< 0x00010000 */
+#define TIM_ECR_PW_1              (0x02UL << TIM_ECR_PW_Pos)                   /*!< 0x00020000 */
+#define TIM_ECR_PW_2              (0x04UL << TIM_ECR_PW_Pos)                   /*!< 0x00040000 */
+#define TIM_ECR_PW_3              (0x08UL << TIM_ECR_PW_Pos)                   /*!< 0x00080000 */
+#define TIM_ECR_PW_4              (0x10UL << TIM_ECR_PW_Pos)                   /*!< 0x00100000 */
+#define TIM_ECR_PW_5              (0x20UL << TIM_ECR_PW_Pos)                   /*!< 0x00200000 */
+#define TIM_ECR_PW_6              (0x40UL << TIM_ECR_PW_Pos)                   /*!< 0x00400000 */
+#define TIM_ECR_PW_7              (0x80UL << TIM_ECR_PW_Pos)                   /*!< 0x00800000 */
+#define TIM_ECR_PWPRSC_Pos        (24U)
+#define TIM_ECR_PWPRSC_Msk        (0x7UL << TIM_ECR_PWPRSC_Pos)                /*!< 0x07000000 */
+#define TIM_ECR_PWPRSC            TIM_ECR_PWPRSC_Msk                           /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
+#define TIM_ECR_PWPRSC_0          (0x01UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x01000000 */
+#define TIM_ECR_PWPRSC_1          (0x02UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x02000000 */
+#define TIM_ECR_PWPRSC_2          (0x04UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x04000000 */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits */
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits */
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits */
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits */
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM_AF1 register  ********************/
+#define TIM_AF1_BKINE_Pos        (0U)
+#define TIM_AF1_BKINE_Msk        (0x1UL << TIM_AF1_BKINE_Pos)                  /*!< 0x00000001 */
+#define TIM_AF1_BKINE            TIM_AF1_BKINE_Msk                             /*!<BRK BKIN input enable */
+#define TIM_AF1_BKCMP1E_Pos      (1U)
+#define TIM_AF1_BKCMP1E_Msk      (0x1UL << TIM_AF1_BKCMP1E_Pos)                /*!< 0x00000002 */
+#define TIM_AF1_BKCMP1E          TIM_AF1_BKCMP1E_Msk                           /*!<BRK CMP1 enable */
+#define TIM_AF1_BKCMP2E_Pos      (2U)
+#define TIM_AF1_BKCMP2E_Msk      (0x1UL << TIM_AF1_BKCMP2E_Pos)                /*!< 0x00000004 */
+#define TIM_AF1_BKCMP2E          TIM_AF1_BKCMP2E_Msk                           /*!<BRK CMP2 enable */
+#define TIM_AF1_BKCMP3E_Pos      (3U)
+#define TIM_AF1_BKCMP3E_Msk      (0x1UL << TIM_AF1_BKCMP3E_Pos)                /*!< 0x00000008 */
+#define TIM_AF1_BKCMP3E          TIM_AF1_BKCMP3E_Msk                           /*!<BRK CMP3 enable */
+#define TIM_AF1_BKCMP4E_Pos      (4U)
+#define TIM_AF1_BKCMP4E_Msk      (0x1UL << TIM_AF1_BKCMP4E_Pos)                /*!< 0x00000010 */
+#define TIM_AF1_BKCMP4E          TIM_AF1_BKCMP4E_Msk                           /*!<BRK CMP4 enable */
+#define TIM_AF1_BKCMP5E_Pos      (5U)
+#define TIM_AF1_BKCMP5E_Msk      (0x1UL << TIM_AF1_BKCMP5E_Pos)                /*!< 0x00000020 */
+#define TIM_AF1_BKCMP5E          TIM_AF1_BKCMP5E_Msk                           /*!<BRK CMP5 enable */
+#define TIM_AF1_BKCMP6E_Pos      (6U)
+#define TIM_AF1_BKCMP6E_Msk      (0x1UL << TIM_AF1_BKCMP6E_Pos)                /*!< 0x00000040 */
+#define TIM_AF1_BKCMP6E          TIM_AF1_BKCMP6E_Msk                           /*!<BRK CMP6 enable */
+#define TIM_AF1_BKCMP7E_Pos      (7U)
+#define TIM_AF1_BKCMP7E_Msk      (0x1UL << TIM_AF1_BKCMP7E_Pos)                /*!< 0x00000080 */
+#define TIM_AF1_BKCMP7E          TIM_AF1_BKCMP7E_Msk                           /*!<BRK CMP7 enable */
+#define TIM_AF1_BKCMP8E_Pos      (8U)
+#define TIM_AF1_BKCMP8E_Msk      (0x1UL << TIM_AF1_BKCMP8E_Pos)                /*!< 0x00000100 */
+#define TIM_AF1_BKCMP8E          TIM_AF1_BKCMP8E_Msk                           /*!<BRK CMP8 enable */
+#define TIM_AF1_BKINP_Pos        (9U)
+#define TIM_AF1_BKINP_Msk        (0x1UL << TIM_AF1_BKINP_Pos)                  /*!< 0x00000200 */
+#define TIM_AF1_BKINP            TIM_AF1_BKINP_Msk                             /*!<BRK BKIN input polarity */
+#define TIM_AF1_BKCMP1P_Pos      (10U)
+#define TIM_AF1_BKCMP1P_Msk      (0x1UL << TIM_AF1_BKCMP1P_Pos)                /*!< 0x00000400 */
+#define TIM_AF1_BKCMP1P          TIM_AF1_BKCMP1P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP2P_Pos      (11U)
+#define TIM_AF1_BKCMP2P_Msk      (0x1UL << TIM_AF1_BKCMP2P_Pos)                /*!< 0x00000800 */
+#define TIM_AF1_BKCMP2P          TIM_AF1_BKCMP2P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP3P_Pos      (12U)
+#define TIM_AF1_BKCMP3P_Msk      (0x1UL << TIM_AF1_BKCMP3P_Pos)                /*!< 0x00001000 */
+#define TIM_AF1_BKCMP3P          TIM_AF1_BKCMP3P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP4P_Pos      (13U)
+#define TIM_AF1_BKCMP4P_Msk      (0x1UL << TIM_AF1_BKCMP4P_Pos)                /*!< 0x00002000 */
+#define TIM_AF1_BKCMP4P          TIM_AF1_BKCMP4P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_ETRSEL_Pos       (14U)
+#define TIM_AF1_ETRSEL_Msk       (0xFUL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x0003C000 */
+#define TIM_AF1_ETRSEL           TIM_AF1_ETRSEL_Msk                            /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
+#define TIM_AF1_ETRSEL_0         (0x1UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM_AF1_ETRSEL_1         (0x2UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM_AF1_ETRSEL_2         (0x4UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM_AF1_ETRSEL_3         (0x8UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM_AF2 register  ********************/
+#define TIM_AF2_BK2INE_Pos       (0U)
+#define TIM_AF2_BK2INE_Msk       (0x1UL << TIM_AF2_BK2INE_Pos)                 /*!< 0x00000001 */
+#define TIM_AF2_BK2INE           TIM_AF2_BK2INE_Msk                            /*!<BRK2 BKIN input enable */
+#define TIM_AF2_BK2CMP8E_Pos     (8U)
+#define TIM_AF2_BK2CMP8E_Msk     (0x1UL << TIM_AF2_BK2CMP8E_Pos)               /*!< 0x00000100 */
+#define TIM_AF2_BK2CMP8E         TIM_AF2_BK2CMP8E_Msk                          /*!<BRK2 CMP8 enable */
+#define TIM_AF2_BK2INP_Pos       (9U)
+#define TIM_AF2_BK2INP_Msk       (0x1UL << TIM_AF2_BK2INP_Pos)                 /*!< 0x00000200 */
+#define TIM_AF2_BK2INP           TIM_AF2_BK2INP_Msk                            /*!<BRK2 BKIN input polarity */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
+#define TIM_DCR_DBSS_Pos          (16U)
+#define TIM_DCR_DBSS_Msk          (0xFUL << TIM_DCR_DBSS_Pos)                  /*!< 0x000F0000 */
+#define TIM_DCR_DBSS              TIM_DCR_DBSS_Msk                             /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
+#define TIM_DCR_DBSS_0            (0x01UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00010000 */
+#define TIM_DCR_DBSS_1            (0x02UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00020000 */
+#define TIM_DCR_DBSS_2            (0x04UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00040000 */
+#define TIM_DCR_DBSS_3            (0x08UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                    UCPD                                       */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bits definition for UCPD_CFG1 register  *******************/
+#define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
+#define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
+#define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
+#define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
+#define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
+#define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
+#define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
+#define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
+#define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
+#define UCPD_CFG1_IFRGAP_Pos                (6U)
+#define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
+#define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
+#define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
+#define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
+#define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
+#define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
+#define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
+#define UCPD_CFG1_TRANSWIN_Pos              (11U)
+#define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
+#define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
+#define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
+#define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
+#define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
+#define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
+#define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
+#define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
+#define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
+#define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
+#define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
+#define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
+#define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
+#define UCPD_CFG1_RXORDSETEN_Pos            (20U)
+#define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
+#define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
+#define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
+#define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
+#define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
+#define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
+#define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
+#define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
+#define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
+#define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
+#define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
+#define UCPD_CFG1_TXDMAEN_Pos               (29U)
+#define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
+#define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
+#define UCPD_CFG1_RXDMAEN_Pos               (30U)
+#define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
+#define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
+#define UCPD_CFG1_UCPDEN_Pos                (31U)
+#define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
+#define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
+
+/********************  Bits definition for UCPD_CFG2 register  *******************/
+#define UCPD_CFG2_RXFILTDIS_Pos             (0U)
+#define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
+#define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
+#define UCPD_CFG2_RXFILT2N3_Pos             (1U)
+#define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
+#define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
+#define UCPD_CFG2_FORCECLK_Pos              (2U)
+#define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
+#define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
+#define UCPD_CFG2_WUPEN_Pos                 (3U)
+#define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
+#define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
+#define UCPD_CFG2_RXAFILTEN_Pos             (8U)
+#define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)   /*!< 0x00000100 */
+#define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk              /*!< Rx analog filter enable */
+
+/********************  Bits definition for UCPD_CR register  *********************/
+#define UCPD_CR_TXMODE_Pos                  (0U)
+#define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
+#define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
+#define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
+#define UCPD_CR_TXSEND_Pos                  (2U)
+#define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
+#define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXHRST_Pos                  (3U)
+#define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
+#define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
+#define UCPD_CR_RXMODE_Pos                  (4U)
+#define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
+#define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
+#define UCPD_CR_PHYRXEN_Pos                 (5U)
+#define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
+#define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
+#define UCPD_CR_PHYCCSEL_Pos                (6U)
+#define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
+#define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
+#define UCPD_CR_ANASUBMODE_Pos              (7U)
+#define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
+#define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
+#define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
+#define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
+#define UCPD_CR_ANAMODE_Pos                 (9U)
+#define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
+#define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
+#define UCPD_CR_CCENABLE_Pos                (10U)
+#define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
+#define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
+#define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
+#define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
+#define UCPD_CR_USEEXTPHY_Pos               (12U)
+#define UCPD_CR_USEEXTPHY_Msk               (0x1UL << UCPD_CR_USEEXTPHY_Pos)     /*!< 0x00001000 */
+#define UCPD_CR_USEEXTPHY                   UCPD_CR_USEEXTPHY_Msk                /*!< Controls enable of USB Power Delivery transmitter */
+#define UCPD_CR_CC2VCONNEN_Pos              (13U)
+#define UCPD_CR_CC2VCONNEN_Msk              (0x1UL << UCPD_CR_CC2VCONNEN_Pos)    /*!< 0x00002000 */
+#define UCPD_CR_CC2VCONNEN                  UCPD_CR_CC2VCONNEN_Msk               /*!< VCONN enable for CC2 */
+#define UCPD_CR_CC1VCONNEN_Pos              (14U)
+#define UCPD_CR_CC1VCONNEN_Msk              (0x1UL << UCPD_CR_CC1VCONNEN_Pos)    /*!< 0x00004000 */
+#define UCPD_CR_CC1VCONNEN                  UCPD_CR_CC1VCONNEN_Msk               /*!< VCONN enable for CC1 */
+#define UCPD_CR_DBATEN_Pos                  (15U)
+#define UCPD_CR_DBATEN_Msk                  (0x1UL << UCPD_CR_DBATEN_Pos)        /*!< 0x00008000 */
+#define UCPD_CR_DBATEN                      UCPD_CR_DBATEN_Msk                   /*!< Enable dead battery behavior (Active High) */
+#define UCPD_CR_FRSTX_Pos                   (17U)
+#define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
+#define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
+#define UCPD_CR_RDCH_Pos                    (18U)
+#define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
+#define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
+#define UCPD_CR_RPUSBABSENT_Pos             (19U)
+#define UCPD_CR_RPUSBABSENT_Msk             (0x1UL << UCPD_CR_RPUSBABSENT_Pos)   /*!< 0x00080000 */
+#define UCPD_CR_RPUSBABSENT                 UCPD_CR_RPUSBABSENT_Msk              /*!<  */
+#define UCPD_CR_CC1TCDIS_Pos                (20U)
+#define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
+#define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
+#define UCPD_CR_CC2TCDIS_Pos                (21U)
+#define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
+#define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
+
+/********************  Bits definition for UCPD_IMR register  ********************/
+#define UCPD_IMR_TXISIE_Pos                 (0U)
+#define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
+#define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
+#define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
+#define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
+#define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
+#define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
+#define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
+#define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
+#define UCPD_IMR_TXMSGABTIE_Pos             (3U)
+#define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
+#define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
+#define UCPD_IMR_HRSTDISCIE_Pos             (4U)
+#define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
+#define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
+#define UCPD_IMR_HRSTSENTIE_Pos             (5U)
+#define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
+#define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
+#define UCPD_IMR_TXUNDIE_Pos                (6U)
+#define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
+#define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
+#define UCPD_IMR_RXNEIE_Pos                 (8U)
+#define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
+#define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
+#define UCPD_IMR_RXORDDETIE_Pos             (9U)
+#define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
+#define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
+#define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
+#define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
+#define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
+#define UCPD_IMR_RXOVRIE_Pos                (11U)
+#define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
+#define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
+#define UCPD_IMR_RXMSGENDIE_Pos             (12U)
+#define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
+#define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
+#define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
+#define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
+#define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
+#define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
+#define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
+#define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
+
+/********************  Bits definition for UCPD_SR register  *********************/
+#define UCPD_SR_TXIS_Pos                    (0U)
+#define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
+#define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
+#define UCPD_SR_TXMSGDISC_Pos               (1U)
+#define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
+#define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
+#define UCPD_SR_TXMSGSENT_Pos               (2U)
+#define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
+#define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
+#define UCPD_SR_TXMSGABT_Pos                (3U)
+#define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
+#define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
+#define UCPD_SR_HRSTDISC_Pos                (4U)
+#define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
+#define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
+#define UCPD_SR_HRSTSENT_Pos                (5U)
+#define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
+#define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
+#define UCPD_SR_TXUND_Pos                   (6U)
+#define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
+#define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
+#define UCPD_SR_RXNE_Pos                    (8U)
+#define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
+#define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
+#define UCPD_SR_RXORDDET_Pos                (9U)
+#define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
+#define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
+#define UCPD_SR_RXHRSTDET_Pos               (10U)
+#define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
+#define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
+#define UCPD_SR_RXOVR_Pos                   (11U)
+#define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
+#define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
+#define UCPD_SR_RXMSGEND_Pos                (12U)
+#define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
+#define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
+#define UCPD_SR_RXERR_Pos                   (13U)
+#define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
+#define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
+#define UCPD_SR_TYPECEVT1_Pos               (14U)
+#define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
+#define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
+#define UCPD_SR_TYPECEVT2_Pos               (15U)
+#define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
+#define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
+#define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
+#define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
+
+/********************  Bits definition for UCPD_ICR register  ********************/
+#define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
+#define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
+#define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
+#define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
+#define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
+#define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
+#define UCPD_ICR_TXMSGABTCF_Pos             (3U)
+#define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
+#define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
+#define UCPD_ICR_HRSTDISCCF_Pos             (4U)
+#define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
+#define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
+#define UCPD_ICR_HRSTSENTCF_Pos             (5U)
+#define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
+#define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
+#define UCPD_ICR_TXUNDCF_Pos                (6U)
+#define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
+#define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
+#define UCPD_ICR_RXORDDETCF_Pos             (9U)
+#define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
+#define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
+#define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
+#define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
+#define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
+#define UCPD_ICR_RXOVRCF_Pos                (11U)
+#define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
+#define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
+#define UCPD_ICR_RXMSGENDCF_Pos             (12U)
+#define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
+#define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
+#define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
+#define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
+#define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
+#define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
+#define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
+#define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
+
+/********************  Bits definition for UCPD_TXORDSET register  ***************/
+#define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
+#define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
+#define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
+
+/********************  Bits definition for UCPD_TXPAYSZ register  ****************/
+#define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
+#define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
+
+/********************  Bits definition for UCPD_TXDR register  *******************/
+#define UCPD_TXDR_TXDATA_Pos                (0U)
+#define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                 /*!< Tx Data Register */
+
+/********************  Bits definition for UCPD_RXORDSET register  ***************/
+#define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
+#define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
+#define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
+#define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
+#define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
+#define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
+#define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
+#define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
+#define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
+#define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
+
+/********************  Bits definition for UCPD_RXPAYSZ register  ****************/
+#define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
+#define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
+
+/********************  Bits definition for UCPD_RXDR register  *******************/
+#define UCPD_RXDR_RXDATA_Pos                (0U)
+#define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
+
+/********************  Bits definition for UCPD_RXORDEXT1 register  **************/
+#define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
+#define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+/********************  Bits definition for UCPD_RXORDEXT2 register  **************/
+#define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
+#define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                    (0U)
+#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
+#define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
+#define USART_CR1_UESM_Pos                  (1U)
+#define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
+#define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                    (2U)
+#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
+#define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                    (3U)
+#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
+#define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos                (4U)
+#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos                (5U)
+#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
+#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
+#define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos                  (6U)
+#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
+#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos                 (7U)
+#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos                  (8U)
+#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
+#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                    (9U)
+#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
+#define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
+#define USART_CR1_PCE_Pos                   (10U)
+#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
+#define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos                  (11U)
+#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
+#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                     (12U)
+#define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                         USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                    (12U)
+#define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
+#define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos                   (13U)
+#define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
+#define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos                  (14U)
+#define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
+#define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match Interrupt Enable */
+#define USART_CR1_OVER8_Pos                 (15U)
+#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos                  (16U)
+#define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
+#define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos                  (21U)
+#define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
+#define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos                 (26U)
+#define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
+#define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
+#define USART_CR1_EOBIE_Pos                 (27U)
+#define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
+#define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
+#define USART_CR1_M1_Pos                    (28U)
+#define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
+#define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos                (29U)
+#define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos                (30U)
+#define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
+#define USART_CR1_RXFFIE_Pos                (31U)
+#define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos                 (0U)
+#define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
+#define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
+#define USART_CR2_DIS_NSS_Pos               (3U)
+#define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos                 (4U)
+#define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
+#define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos                  (5U)
+#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
+#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos                 (6U)
+#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
+#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos                  (8U)
+#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
+#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos                  (9U)
+#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
+#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos                  (10U)
+#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
+#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos                 (11U)
+#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
+#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
+#define USART_CR2_STOP_Pos                  (12U)
+#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
+#define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos                 (14U)
+#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
+#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos                  (15U)
+#define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
+#define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos                 (16U)
+#define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
+#define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos                 (17U)
+#define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
+#define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos               (18U)
+#define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
+#define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos              (19U)
+#define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos                 (20U)
+#define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
+#define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos               (21U)
+#define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
+#define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos                 (23U)
+#define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
+#define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos                   (24U)
+#define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
+#define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos                   (0U)
+#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
+#define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos                  (1U)
+#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
+#define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos                  (2U)
+#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
+#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos                 (3U)
+#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
+#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos                  (4U)
+#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
+#define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos                  (5U)
+#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
+#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos                  (6U)
+#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
+#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos                  (7U)
+#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
+#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos                  (8U)
+#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
+#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos                  (9U)
+#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
+#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos                 (10U)
+#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
+#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos                (11U)
+#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos                (12U)
+#define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos                  (13U)
+#define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
+#define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos                   (14U)
+#define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
+#define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos                   (15U)
+#define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
+#define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos               (17U)
+#define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos                   (20U)
+#define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
+#define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos                 (22U)
+#define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
+#define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos                (23U)
+#define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TCBGTIE_Pos               (24U)
+#define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_Pos               (25U)
+#define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
+#define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos                (28U)
+#define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TXFTCFG_Pos               (29U)
+#define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
+#define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_LPUART                    ((uint32_t)0x000FFFFF)                  /*!< LPUART Baud rate register [19:0] */
+#define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos                  (0U)
+#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
+#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos                   (8U)
+#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
+#define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos                  (0U)
+#define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Timeout Value */
+#define USART_RTOR_BLEN_Pos                 (24U)
+#define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos                 (0U)
+#define USART_RQR_ABRRQ_Msk                 (0x1UL << USART_RQR_ABRRQ_Pos)          /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                     USART_RQR_ABRRQ_Msk                     /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos                 (1U)
+#define USART_RQR_SBKRQ_Msk                 (0x1UL << USART_RQR_SBKRQ_Pos)          /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                     USART_RQR_SBKRQ_Msk                     /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos                  (2U)
+#define USART_RQR_MMRQ_Msk                  (0x1UL << USART_RQR_MMRQ_Pos)           /*!< 0x00000004 */
+#define USART_RQR_MMRQ                      USART_RQR_MMRQ_Msk                      /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos                 (3U)
+#define USART_RQR_RXFRQ_Msk                 (0x1UL << USART_RQR_RXFRQ_Pos)          /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                     USART_RQR_RXFRQ_Msk                     /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos                 (4U)
+#define USART_RQR_TXFRQ_Msk                 (0x1UL << USART_RQR_TXFRQ_Pos)          /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                     USART_RQR_TXFRQ_Msk                     /*!< Transmit Data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                    (0U)
+#define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
+#define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
+#define USART_ISR_FE_Pos                    (1U)
+#define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
+#define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
+#define USART_ISR_NE_Pos                    (2U)
+#define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
+#define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise Error detection Flag */
+#define USART_ISR_ORE_Pos                   (3U)
+#define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
+#define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos                  (4U)
+#define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
+#define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos                  (5U)
+#define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
+#define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
+#define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
+#define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                    (6U)
+#define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
+#define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos                   (7U)
+#define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
+#define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
+#define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
+#define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos                  (8U)
+#define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
+#define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos                 (9U)
+#define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
+#define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
+#define USART_ISR_CTS_Pos                   (10U)
+#define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
+#define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS Flag */
+#define USART_ISR_RTOF_Pos                  (11U)
+#define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
+#define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Timeout */
+#define USART_ISR_EOBF_Pos                  (12U)
+#define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
+#define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos                   (13U)
+#define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
+#define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
+#define USART_ISR_ABRE_Pos                  (14U)
+#define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
+#define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos                  (15U)
+#define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
+#define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos                  (16U)
+#define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
+#define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
+#define USART_ISR_CMF_Pos                   (17U)
+#define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
+#define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos                  (18U)
+#define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
+#define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos                   (19U)
+#define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
+#define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos                   (20U)
+#define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
+#define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
+#define USART_ISR_TEACK_Pos                 (21U)
+#define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
+#define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos                 (22U)
+#define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
+#define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos                  (23U)
+#define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
+#define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
+#define USART_ISR_RXFF_Pos                  (24U)
+#define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
+#define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
+#define USART_ISR_TCBGT_Pos                 (25U)
+#define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
+#define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
+#define USART_ISR_RXFT_Pos                  (26U)
+#define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
+#define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
+#define USART_ISR_TXFT_Pos                  (27U)
+#define USART_ISR_TXFT_Msk                 (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
+#define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos                  (0U)
+#define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
+#define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos                  (1U)
+#define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
+#define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos                  (2U)
+#define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
+#define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
+#define USART_ICR_ORECF_Pos                 (3U)
+#define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
+#define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos                (4U)
+#define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
+#define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos                (5U)
+#define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
+#define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
+#define USART_ICR_TCCF_Pos                  (6U)
+#define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
+#define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos               (7U)
+#define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos                 (8U)
+#define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
+#define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos                 (9U)
+#define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
+#define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos                 (11U)
+#define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
+#define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos                 (12U)
+#define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
+#define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos                 (13U)
+#define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
+#define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF_Pos                  (17U)
+#define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
+#define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos                  (20U)
+#define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
+#define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ****************/
+#define USART_PRESC_PRESCALER_Pos           (0U)
+#define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_CSRSTDONE_Pos            (29U)
+#define USB_OTG_GRSTCTL_CSRSTDONE_Msk            (0x1UL << USB_OTG_GRSTCTL_CSRSTDONE_Pos) /*!< 0x20000000 */
+#define USB_OTG_GRSTCTL_CSRSTDONE                USB_OTG_GRSTCTL_CSRSTDONE_Msk   /*!< Core soft reset done            */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_HS_GCCFG register  ********************/
+#define USB_OTG_GCCFG_CHGDET_Pos                 (0U)
+#define USB_OTG_GCCFG_CHGDET_Msk                 (0x1U << USB_OTG_GCCFG_CHGDET_Pos)           /*!< 0x00000001 */
+#define USB_OTG_GCCFG_CHGDET                     USB_OTG_GCCFG_CHGDET_Msk                     /*!< Battery Charger Detection */
+#define USB_OTG_GCCFG_FSVPLUS_Pos                (1U)
+#define USB_OTG_GCCFG_FSVPLUS_Msk                (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos)          /*!< 0x00000002 */
+#define USB_OTG_GCCFG_FSVPLUS                    USB_OTG_GCCFG_FSVPLUS_Msk                    /*!< Single-Ended DP2 indicator DP voltage level  */
+#define USB_OTG_GCCFG_FSVMINUS_Pos               (2U)
+#define USB_OTG_GCCFG_FSVMINUS_Msk               0x1U << USB_OTG_GCCFG_FSVMINUS_Pos)         /*!< 0x00000004 */
+#define USB_OTG_GCCFG_FSVMINUS                   USB_OTG_GCCFG_FSVMINUS_Msk                  /*!< Single-Ended DM2 indicator DM voltage level  */
+#define USB_OTG_GCCFG_SESSVLD_Pos                (3U)
+#define USB_OTG_GCCFG_SESSVLD_Msk                (0x1U << USB_OTG_GCCFG_SESSVLD_Pos)          /*!< 0x00000008 */
+#define USB_OTG_GCCFG_SESSVLD                    USB_OTG_GCCFG_SESSVLD_Msk                    /*!< VBUS session valid indicator: Vbus is above VBUS session threshold.  */
+#define USB_OTG_GCCFG_VBUSVLD_Pos                (4U)
+#define USB_OTG_GCCFG_VBUSVLD_Msk                (0x1U << USB_OTG_GCCFG_VBUSVLD_Pos)          /*!< 0x00000010 */
+#define USB_OTG_GCCFG_VBUSVLD                    USB_OTG_GCCFG_VBUSVLD_Msk                    /*!< VBUS session valid indicator: VBUS is above VBUS valid threshold.  */
+#define USB_OTG_GCCFG_H_CDPEN_Pos                (16U)
+#define USB_OTG_GCCFG_H_CDPEN_Msk                (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos)          /*!< 0x00010000 */
+#define USB_OTG_GCCFG_H_CDPEN                    USB_OTG_GCCFG_H_CDPEN_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
+#define USB_OTG_GCCFG_H_CDPDETEN_Pos             (17U)
+#define USB_OTG_GCCFG_H_CDPDETEN_Msk             (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos)       /*!< 0x00020000 */
+#define USB_OTG_GCCFG_H_CDPDETEN                 USB_OTG_GCCFG_H_CDPDETEN_Msk                 /*!< Enable of voltage detector on DP for CDP port  */
+#define USB_OTG_GCCFG_H_VDMSRCEN_Pos             (18U)
+#define USB_OTG_GCCFG_H_VDMSRCEN_Msk             (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos)       /*!< 0x00040000 */
+#define USB_OTG_GCCFG_H_VDMSRCEN                 USB_OTG_GCCFG_H_VDMSRCEN_Msk                 /*!< Enable Voltage source on DM for CDP port */
+#define USB_OTG_GCCFG_DCDETEN_Pos                (19U)
+#define USB_OTG_GCCFG_DCDETEN_Msk                (0x1U << USB_OTG_GCCFG_DCDETEN_Pos)          /*!< 0x00080000 */
+#define USB_OTG_GCCFG_DCDETEN                    USB_OTG_GCCFG_DCDETEN_Msk                    /*!< Data contact detection (DCD) mode enable */
+#define USB_OTG_GCCFG_PDETEN_Pos                 (20U)
+#define USB_OTG_GCCFG_PDETEN_Msk                 (0x1U << USB_OTG_GCCFG_PDETEN_Pos)           /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDETEN                     USB_OTG_GCCFG_PDETEN_Msk                     /*!< Primary detection (PD) mode enable */
+#define USB_OTG_GCCFG_SDETEN_Pos                 (22U)
+#define USB_OTG_GCCFG_SDETEN_Msk                 (0x1U << USB_OTG_GCCFG_SDETEN_Pos)           /*!< 0x00400000 */
+#define USB_OTG_GCCFG_SDETEN                     USB_OTG_GCCFG_SDETEN_Msk                     /*!< Secondary detection (PD) mode enable */
+#define USB_OTG_GCCFG_VBVALOVAL_Pos              (23U)
+#define USB_OTG_GCCFG_VBVALOVAL_Msk              (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos)        /*!< 0x00800000 */
+#define USB_OTG_GCCFG_VBVALOVAL                  USB_OTG_GCCFG_VBVALOVAL_Msk                  /*!< Value of VBUSVLDEXT0 PHY input */
+#define USB_OTG_GCCFG_VBVALEXTOEN_Pos            (24U)
+#define USB_OTG_GCCFG_VBVALEXTOEN_Msk            (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos)      /*!< 0x01000000 */
+#define USB_OTG_GCCFG_VBVALEXTOEN                USB_OTG_GCCFG_VBVALEXTOEN_Msk                /*!< Enables of VBUSVLDEXT0 PHY input override */
+#define USB_OTG_GCCFG_PULLDOWNEN_Pos             (25U)
+#define USB_OTG_GCCFG_PULLDOWNEN_Msk             (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos)       /*!< 0x02000000 */
+#define USB_OTG_GCCFG_PULLDOWNEN                 USB_OTG_GCCFG_PULLDOWNEN_Msk                 /*!< Enables Host pulldown resistors, used when ID PAD is disabled */
+#define USB_OTG_GCCFG_FORCEBCMODE_Pos            (26U)
+#define USB_OTG_GCCFG_FORCEBCMODE_Msk            (0x1U << USB_OTG_GCCFG_FORCEBCMODE_Pos)      /*!< 0x04000000 */
+#define USB_OTG_GCCFG_FORCEBCMODE                USB_OTG_GCCFG_FORCEBCMODE_Msk                /*!< Force Battery charging (BC) mode */
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Pos           (28U)
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Msk           (0x1U << USB_OTG_GCCFG_IDPULLUP_DIS_Pos)      /*!< 0x10000000 */
+#define USB_OTG_GCCFG_IDPULLUP_DIS               USB_OTG_GCCFG_IDPULLUP_DIS_Msk                /*!< Analog ID Input Sample Disable: disable sampling on the analog ID line */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL1 register  ********************/
+#define USB_OTG_PCGCCTL1_GATEEN_Pos               (0U)
+#define USB_OTG_PCGCCTL1_GATEEN_Msk               (0x1UL << USB_OTG_PCGCCTL1_GATEEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL1_GATEEN                   USB_OTG_PCGCCTL1_GATEEN_Msk   /*!< Enable Active Clock Gating */
+#define USB_OTG_PCGCCTL1_COUNTER_Pos              (1U)
+#define USB_OTG_PCGCCTL1_COUNTER_Msk              (0x3UL << USB_OTG_PCGCCTL1_COUNTER_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL1_COUNTER                  USB_OTG_PCGCCTL1_COUNTER_Msk   /*!< Count to Gate Clock */
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Pos            (3U)
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Msk            (0x1UL << USB_OTG_PCGCCTL1_RAMGATEEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL1_RAMGATEEN                USB_OTG_PCGCCTL1_RAMGATEEN_Msk   /*!< RAM Clock Gating Enable */
+
+/*!< USB registers base address */
+#define USB_OTG_GLOBAL_BASE                       (0x000UL)
+#define USB_OTG_DEVICE_BASE                       (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE                  (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE                 (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                       (0x20UL)
+#define USB_OTG_HOST_BASE                         (0x400UL)
+#define USB_OTG_HOST_PORT_BASE                    (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE                 (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE                 (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                      (0xE00UL)
+#define USB_OTG_FIFO_BASE                         (0x1000UL)
+#define USB_OTG_FIFO_SIZE                         (0x1000UL)
+#define USB_OTG_HS_EP_NBR                         (9UL)            /*!< Number of USB HS Device endpoints */
+#define USB_OTG_HS_CH_NBR                         (16UL)           /*!< Number of USB HS Host channels */
+
+/********************  Bit definition for USB_USBPHYC_CR register  ********************/
+#define USB_USBPHYC_CR_RETENABLEN1_Pos          (0U)
+#define USB_USBPHYC_CR_RETENABLEN1_Msk          (0x1UL << USB_USBPHYC_CR_RETENABLEN1_Pos)    /*!< 0x00000001 */
+#define USB_USBPHYC_CR_RETENABLEN1              USB_USBPHYC_CR_RETENABLEN1_Msk               /*!< Retention mode enable */
+#define USB_USBPHYC_CR_AUTORSMENB1_Pos          (1U)
+#define USB_USBPHYC_CR_AUTORSMENB1_Msk          (0x1UL << USB_USBPHYC_CR_AUTORSMENB1_Pos)    /*!< 0x00000002 */
+#define USB_USBPHYC_CR_AUTORSMENB1              USB_USBPHYC_CR_AUTORSMENB1_Msk               /*!< Auto-resume mode enable */
+#define USB_USBPHYC_CR_CMN_Pos                  (2U)
+#define USB_USBPHYC_CR_CMN_Msk                  (0x1UL << USB_USBPHYC_CR_CMN_Pos)            /*!< 0x00000004 */
+#define USB_USBPHYC_CR_CMN                      USB_USBPHYC_CR_CMN_Msk                       /*!< Controls the power down of analog blocks during Suspend and Sleep */
+#define USB_USBPHYC_CR_FSEL_Pos                 (4U)
+#define USB_USBPHYC_CR_FSEL_Msk                 (0x7UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000070 */
+#define USB_USBPHYC_CR_FSEL                     USB_USBPHYC_CR_FSEL_Msk                      /*!< Frequency selection */
+#define USB_USBPHYC_CR_FSEL_0                   (0x1UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000010 */
+#define USB_USBPHYC_CR_FSEL_1                   (0x2UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000020 */
+#define USB_USBPHYC_CR_FSEL_2                   (0x3UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000040 */
+#define USB_USBPHYC_CR_OTGDISABLE0_Pos          (16U)
+#define USB_USBPHYC_CR_OTGDISABLE0_Msk          (0x1UL << USB_USBPHYC_CR_OTGDISABLE0_Pos)    /*!< 0x00010000 */
+#define USB_USBPHYC_CR_OTGDISABLE0              USB_USBPHYC_CR_OTGDISABLE0_Msk               /*!< OTG disable 0 */
+#define USB_USBPHYC_CR_DRVVBUS0_Pos             (17U)
+#define USB_USBPHYC_CR_DRVVBUS0_Msk             (0x1UL << USB_USBPHYC_CR_DRVVBUS0_Pos)       /*!< 0x00020000 */
+#define USB_USBPHYC_CR_DRVVBUS0                 USB_USBPHYC_CR_DRVVBUS0_Msk                  /*!< Drive VBUS 0 */
+#define USB_USBPHYC_CR_SELOTGDBG_Pos            (31U)
+#define USB_USBPHYC_CR_SELOTGDBG_Msk            (0x1UL << USB_USBPHYC_CR_SELOTGDBG_Pos)      /*!< 0x80000000 */
+#define USB_USBPHYC_CR_SELOTGDBG                USB_USBPHYC_CR_SELOTGDBG_Msk                 /*!< Select HS PHY debug port */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)
+#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)
+#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos     (3U)
+#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos     (4U)
+#define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
+#define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000040 */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos                (0U)
+#define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos                       (0U)
+#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
+#define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
+#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
+#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
+#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
+#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
+#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
+#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
+#define WWDG_CR_WDGA_Pos                    (7U)
+#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
+#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos                      (0U)
+#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
+#define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
+#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
+#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
+#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
+#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
+#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
+#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
+#define WWDG_CFR_EWI_Pos                    (9U)
+#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
+#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
+#define WWDG_CFR_WDGTB_Pos                  (11U)
+#define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos                    (0U)
+#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
+#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Extended-SPI Interface (XSPI)                         */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for XSPI_CR register  *******************/
+#define XSPI_CR_EN_Pos                   (0U)
+#define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)            /*!< 0x00000001 */
+#define XSPI_CR_EN                       XSPI_CR_EN_Msk                       /*!< Enable */
+#define XSPI_CR_ABORT_Pos                (1U)
+#define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
+#define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define XSPI_CR_DMAEN_Pos                (2U)
+#define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
+#define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define XSPI_CR_TCEN_Pos                 (3U)
+#define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
+#define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define XSPI_CR_DMM_Pos                  (6U)
+#define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)           /*!< 0x00000040 */
+#define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                      /*!< Dual Memory Mode */
+#define XSPI_CR_FSEL_Pos                 (7U)
+#define XSPI_CR_FSEL_Msk                 (0x1UL << XSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
+#define XSPI_CR_FSEL                     XSPI_CR_FSEL_Msk                     /*!< Flash Select */
+#define XSPI_CR_FTHRES_Pos               (8U)
+#define XSPI_CR_FTHRES_Msk               (0x3FUL << XSPI_CR_FTHRES_Pos)       /*!< 0x00003F00 */
+#define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */
+#define XSPI_CR_TEIE_Pos                 (16U)
+#define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
+#define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define XSPI_CR_TCIE_Pos                 (17U)
+#define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
+#define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define XSPI_CR_FTIE_Pos                 (18U)
+#define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
+#define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define XSPI_CR_SMIE_Pos                 (19U)
+#define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
+#define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define XSPI_CR_TOIE_Pos                 (20U)
+#define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
+#define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define XSPI_CR_APMS_Pos                 (22U)
+#define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)          /*!< 0x00400000 */
+#define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */
+#define XSPI_CR_PMM_Pos                  (23U)
+#define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)           /*!< 0x00800000 */
+#define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define XSPI_CR_CSSEL_Pos                (24U)
+#define XSPI_CR_CSSEL_Msk                (0x1UL << XSPI_CR_CSSEL_Pos)         /*!< 0x01000000 */
+#define XSPI_CR_CSSEL                    XSPI_CR_CSSEL_Msk                    /*!< Chip Select Selection */
+#define XSPI_CR_NOPREF_Pos               (25U)
+#define XSPI_CR_NOPREF_Msk               (0x1UL << XSPI_CR_NOPREF_Pos)        /*!< 0x02000000 */
+#define XSPI_CR_NOPREF                   XSPI_CR_NOPREF_Msk                   /*!< No Prefetch Data */
+#define XSPI_CR_NOPREF_AXI_Pos           (26U)
+#define XSPI_CR_NOPREF_AXI_Msk           (0x1UL << XSPI_CR_NOPREF_AXI_Pos)    /*!< 0x04000000 */
+#define XSPI_CR_NOPREF_AXI               XSPI_CR_NOPREF_AXI_Msk               /*!< No Prefetch For Signaled AXI Transactions */
+#define XSPI_CR_FMODE_Pos                (28U)
+#define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)         /*!< 0x30000000 */
+#define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                    /*!< Functional Mode */
+#define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)         /*!< 0x10000000 */
+#define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)         /*!< 0x20000000 */
+#define XSPI_CR_MSEL_Pos                 (30U)
+#define XSPI_CR_MSEL_Msk                 (0x3UL << XSPI_CR_MSEL_Pos)          /*!< 0xC0000000 */
+#define XSPI_CR_MSEL                     XSPI_CR_MSEL_Msk                     /*!< Memory Select */
+#define XSPI_CR_MSEL_0                   (0x1UL << XSPI_CR_MSEL_Pos)          /*!< 0x40000000 */
+#define XSPI_CR_MSEL_1                   (0x2UL << XSPI_CR_MSEL_Pos)          /*!< 0x80000000 */
+
+/****************  Bit definition for XSPI_DCR1 register  ******************/
+#define XSPI_DCR1_CKMODE_Pos             (0U)
+#define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */
+#define XSPI_DCR1_FRCK_Pos               (1U)
+#define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)        /*!< 0x00000002 */
+#define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */
+#define XSPI_DCR1_CSHT_Pos               (8U)
+#define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)       /*!< 0x00003F00 */
+#define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
+#define XSPI_DCR1_DEVSIZE_Pos            (16U)
+#define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */
+#define XSPI_DCR1_EXTENDMEM_Pos          (21U)
+#define XSPI_DCR1_EXTENDMEM_Msk          (0x1UL << XSPI_DCR1_EXTENDMEM_Pos)   /*!< 0x00200000 */
+#define XSPI_DCR1_EXTENDMEM              XSPI_DCR1_EXTENDMEM_Msk              /*!< Extended Memory Support */
+#define XSPI_DCR1_MTYP_Pos               (24U)
+#define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x07000000 */
+#define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                   /*!< Memory Type */
+#define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x01000000 */
+#define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x02000000 */
+#define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x04000000 */
+
+/****************  Bit definition for XSPI_DCR2 register  ******************/
+#define XSPI_DCR2_PRESCALER_Pos          (0U)
+#define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)  /*!< 0x000000FF */
+#define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */
+#define XSPI_DCR2_WRAPSIZE_Pos           (16U)
+#define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00070000 */
+#define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */
+#define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00010000 */
+#define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00020000 */
+#define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00040000 */
+
+/****************  Bit definition for XSPI_DCR3 register  ******************/
+#define XSPI_DCR3_MAXTRAN_Pos            (0U)
+#define XSPI_DCR3_MAXTRAN_Msk            (0xFFUL << XSPI_DCR3_MAXTRAN_Pos)    /*!< 0x000000FF */
+#define XSPI_DCR3_MAXTRAN                XSPI_DCR3_MAXTRAN_Msk                /*!< Maximum transfer */
+#define XSPI_DCR3_CSBOUND_Pos            (16U)
+#define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                /*!< Maximum transfer */
+
+/****************  Bit definition for XSPI_DCR4 register  ******************/
+#define XSPI_DCR4_REFRESH_Pos            (0U)
+#define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */
+
+/*****************  Bit definition for XSPI_SR register  *******************/
+#define XSPI_SR_TEF_Pos                  (0U)
+#define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)           /*!< 0x00000001 */
+#define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define XSPI_SR_TCF_Pos                  (1U)
+#define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)           /*!< 0x00000002 */
+#define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define XSPI_SR_FTF_Pos                  (2U)
+#define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)           /*!< 0x00000004 */
+#define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */
+#define XSPI_SR_SMF_Pos                  (3U)
+#define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)           /*!< 0x00000008 */
+#define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define XSPI_SR_TOF_Pos                  (4U)
+#define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)           /*!< 0x00000010 */
+#define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define XSPI_SR_BUSY_Pos                 (5U)
+#define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
+#define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                     /*!< Busy */
+#define XSPI_SR_FLEVEL_Pos               (8U)
+#define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)       /*!< 0x00007F00 */
+#define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */
+
+/****************  Bit definition for XSPI_FCR register  *******************/
+#define XSPI_FCR_CTEF_Pos                (0U)
+#define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
+#define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define XSPI_FCR_CTCF_Pos                (1U)
+#define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
+#define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define XSPI_FCR_CSMF_Pos                (3U)
+#define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
+#define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define XSPI_FCR_CTOF_Pos                (4U)
+#define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
+#define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/****************  Bit definition for XSPI_DLR register  *******************/
+#define XSPI_DLR_DL_Pos                  (0U)
+#define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
+#define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                      /*!< Data Length */
+
+/*****************  Bit definition for XSPI_AR register  *******************/
+#define XSPI_AR_ADDRESS_Pos              (0U)
+#define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                  /*!< Address */
+
+/*****************  Bit definition for XSPI_DR register  *******************/
+#define XSPI_DR_DATA_Pos                 (0U)
+#define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
+#define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                     /*!< Data */
+
+/***************  Bit definition for XSPI_PSMKR register  ******************/
+#define XSPI_PSMKR_MASK_Pos              (0U)
+#define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                  /*!< Status mask */
+
+/***************  Bit definition for XSPI_PSMAR register  ******************/
+#define XSPI_PSMAR_MATCH_Pos             (0U)
+#define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                 /*!< Status match */
+
+/****************  Bit definition for XSPI_PIR register  *******************/
+#define XSPI_PIR_INTERVAL_Pos            (0U)
+#define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
+#define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */
+
+/****************  Bit definition for XSPI_CCR register  *******************/
+#define XSPI_CCR_IMODE_Pos               (0U)
+#define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000007 */
+#define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */
+#define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000001 */
+#define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000002 */
+#define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000004 */
+#define XSPI_CCR_IDTR_Pos                (3U)
+#define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)         /*!< 0x00000008 */
+#define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */
+#define XSPI_CCR_ISIZE_Pos               (4U)
+#define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000030 */
+#define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */
+#define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000010 */
+#define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000020 */
+#define XSPI_CCR_ADMODE_Pos              (8U)
+#define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000700 */
+#define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                  /*!< Address Mode */
+#define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000100 */
+#define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000200 */
+#define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define XSPI_CCR_ADDTR_Pos               (11U)
+#define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)        /*!< 0x00000800 */
+#define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */
+#define XSPI_CCR_ADSIZE_Pos              (12U)
+#define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                  /*!< Address Size */
+#define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define XSPI_CCR_ABMODE_Pos              (16U)
+#define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00070000 */
+#define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */
+#define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00010000 */
+#define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00020000 */
+#define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00040000 */
+#define XSPI_CCR_ABDTR_Pos               (19U)
+#define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)        /*!< 0x00080000 */
+#define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_CCR_ABSIZE_Pos              (20U)
+#define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00300000 */
+#define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */
+#define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00100000 */
+#define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00200000 */
+#define XSPI_CCR_DMODE_Pos               (24U)
+#define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)        /*!< 0x07000000 */
+#define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                   /*!< Data Mode */
+#define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)        /*!< 0x04000000 */
+#define XSPI_CCR_DDTR_Pos                (27U)
+#define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)         /*!< 0x08000000 */
+#define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */
+#define XSPI_CCR_DQSE_Pos                (29U)
+#define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)         /*!< 0x20000000 */
+#define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                    /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_TCR register  *******************/
+#define XSPI_TCR_DCYC_Pos                (0U)
+#define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)        /*!< 0x0000001F */
+#define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */
+#define XSPI_TCR_DHQC_Pos                (28U)
+#define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)         /*!< 0x10000000 */
+#define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */
+#define XSPI_TCR_SSHIFT_Pos              (30U)
+#define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)       /*!< 0x40000000 */
+#define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_IR register  *******************/
+#define XSPI_IR_INSTRUCTION_Pos          (0U)
+#define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk              /*!< Instruction */
+
+/****************  Bit definition for XSPI_ABR register  *******************/
+#define XSPI_ABR_ALTERNATE_Pos           (0U)
+#define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_LPTR register  ******************/
+#define XSPI_LPTR_TIMEOUT_Pos            (0U)
+#define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
+#define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */
+
+/****************  Bit definition for XSPI_WPCCR register  *******************/
+#define XSPI_WPCCR_IMODE_Pos             (0U)
+#define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000007 */
+#define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */
+#define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000002 */
+#define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000004 */
+#define XSPI_WPCCR_IDTR_Pos              (3U)
+#define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)       /*!< 0x00000008 */
+#define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */
+#define XSPI_WPCCR_ISIZE_Pos             (4U)
+#define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000030 */
+#define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */
+#define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000010 */
+#define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000020 */
+#define XSPI_WPCCR_ADMODE_Pos            (8U)
+#define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000700 */
+#define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */
+#define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000100 */
+#define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000200 */
+#define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000400 */
+#define XSPI_WPCCR_ADDTR_Pos             (11U)
+#define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)      /*!< 0x00000800 */
+#define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */
+#define XSPI_WPCCR_ADSIZE_Pos            (12U)
+#define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00003000 */
+#define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */
+#define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00001000 */
+#define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00002000 */
+#define XSPI_WPCCR_ABMODE_Pos            (16U)
+#define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00070000 */
+#define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */
+#define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00010000 */
+#define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00020000 */
+#define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00040000 */
+#define XSPI_WPCCR_ABDTR_Pos             (19U)
+#define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)      /*!< 0x00080000 */
+#define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WPCCR_ABSIZE_Pos            (20U)
+#define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00300000 */
+#define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */
+#define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00100000 */
+#define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00200000 */
+#define XSPI_WPCCR_DMODE_Pos             (24U)
+#define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x07000000 */
+#define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */
+#define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x01000000 */
+#define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x02000000 */
+#define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x04000000 */
+#define XSPI_WPCCR_DDTR_Pos              (27U)
+#define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)       /*!< 0x08000000 */
+#define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */
+#define XSPI_WPCCR_DQSE_Pos              (29U)
+#define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)       /*!< 0x20000000 */
+#define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WPTCR register  *******************/
+#define XSPI_WPTCR_DCYC_Pos              (0U)
+#define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)      /*!< 0x0000001F */
+#define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */
+#define XSPI_WPTCR_DHQC_Pos              (28U)
+#define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)       /*!< 0x10000000 */
+#define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */
+#define XSPI_WPTCR_SSHIFT_Pos            (30U)
+#define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)     /*!< 0x40000000 */
+#define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_WPIR register  *******************/
+#define XSPI_WPIR_INSTRUCTION_Pos        (0U)
+#define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */
+
+/****************  Bit definition for XSPI_WPABR register  *******************/
+#define XSPI_WPABR_ALTERNATE_Pos         (0U)
+#define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_WCCR register  ******************/
+#define XSPI_WCCR_IMODE_Pos              (0U)
+#define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000007 */
+#define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */
+#define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000001 */
+#define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000002 */
+#define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000004 */
+#define XSPI_WCCR_IDTR_Pos               (3U)
+#define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)        /*!< 0x00000008 */
+#define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */
+#define XSPI_WCCR_ISIZE_Pos              (4U)
+#define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000030 */
+#define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */
+#define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000010 */
+#define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000020 */
+#define XSPI_WCCR_ADMODE_Pos             (8U)
+#define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000700 */
+#define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */
+#define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000100 */
+#define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000200 */
+#define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000400 */
+#define XSPI_WCCR_ADDTR_Pos              (11U)
+#define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)       /*!< 0x00000800 */
+#define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */
+#define XSPI_WCCR_ADSIZE_Pos             (12U)
+#define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00003000 */
+#define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */
+#define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00001000 */
+#define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00002000 */
+#define XSPI_WCCR_ABMODE_Pos             (16U)
+#define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00070000 */
+#define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */
+#define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00010000 */
+#define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00020000 */
+#define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00040000 */
+#define XSPI_WCCR_ABDTR_Pos              (19U)
+#define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)       /*!< 0x00080000 */
+#define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WCCR_ABSIZE_Pos             (20U)
+#define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00300000 */
+#define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */
+#define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00100000 */
+#define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00200000 */
+#define XSPI_WCCR_DMODE_Pos              (24U)
+#define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x07000000 */
+#define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                  /*!< Data Mode */
+#define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x01000000 */
+#define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x02000000 */
+#define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x04000000 */
+#define XSPI_WCCR_DDTR_Pos               (27U)
+#define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)        /*!< 0x08000000 */
+#define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */
+#define XSPI_WCCR_DQSE_Pos               (29U)
+#define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)        /*!< 0x20000000 */
+#define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WTCR register  ******************/
+#define XSPI_WTCR_DCYC_Pos               (0U)
+#define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)       /*!< 0x0000001F */
+#define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */
+
+/****************  Bit definition for XSPI_WIR register  *******************/
+#define XSPI_WIR_INSTRUCTION_Pos         (0U)
+#define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */
+
+/****************  Bit definition for XSPI_WABR register  ******************/
+#define XSPI_WABR_ALTERNATE_Pos          (0U)
+#define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_HLCR register  ******************/
+#define XSPI_HLCR_LM_Pos                 (0U)
+#define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)          /*!< 0x00000001 */
+#define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                     /*!< Latency Mode */
+#define XSPI_HLCR_WZL_Pos                (1U)
+#define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)         /*!< 0x00000002 */
+#define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */
+#define XSPI_HLCR_TACC_Pos               (8U)
+#define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)       /*!< 0x0000FF00 */
+#define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                   /*!< Access Time */
+#define XSPI_HLCR_TRWR_Pos               (16U)
+#define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)       /*!< 0x00FF0000 */
+#define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */
+
+/****************  Bit definition for XSPI_CALFCR register  ****************/
+#define XSPI_CALFCR_FINE_Pos             (0U)
+#define XSPI_CALFCR_FINE_Msk             (0x7FUL << XSPI_CALFCR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALFCR_FINE                 XSPI_CALFCR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALFCR_COARSE_Pos           (16U)
+#define XSPI_CALFCR_COARSE_Msk           (0x1FUL << XSPI_CALFCR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALFCR_COARSE               XSPI_CALFCR_COARSE_Msk               /*!< Coarse Calibration */
+#define XSPI_CALFCR_CALMAX_Pos           (31U)
+#define XSPI_CALFCR_CALMAX_Msk           (0x1UL << XSPI_CALFCR_CALMAX_Pos)    /*!< 0x80000000 */
+#define XSPI_CALFCR_CALMAX               XSPI_CALFCR_CALMAX_Msk               /*!< Max Value */
+
+/****************  Bit definition for XSPI_CALMR register  *****************/
+#define XSPI_CALMR_FINE_Pos              (0U)
+#define XSPI_CALMR_FINE_Msk              (0x7FUL << XSPI_CALMR_FINE_Pos)      /*!< 0x0000007F */
+#define XSPI_CALMR_FINE                  XSPI_CALMR_FINE_Msk                  /*!< Fine Calibration */
+#define XSPI_CALMR_COARSE_Pos            (16U)
+#define XSPI_CALMR_COARSE_Msk            (0x1FUL << XSPI_CALMR_COARSE_Pos)    /*!< 0x001F0000 */
+#define XSPI_CALMR_COARSE                XSPI_CALMR_COARSE_Msk                /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSOR register  ****************/
+#define XSPI_CALSOR_FINE_Pos             (0U)
+#define XSPI_CALSOR_FINE_Msk             (0x7FUL << XSPI_CALSOR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSOR_FINE                 XSPI_CALSOR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSOR_COARSE_Pos           (16U)
+#define XSPI_CALSOR_COARSE_Msk           (0x1FUL << XSPI_CALSOR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSOR_COARSE               XSPI_CALSOR_COARSE_Msk               /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSIR register  ****************/
+#define XSPI_CALSIR_FINE_Pos             (0U)
+#define XSPI_CALSIR_FINE_Msk             (0x7FUL << XSPI_CALSIR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSIR_FINE                 XSPI_CALSIR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSIR_COARSE_Pos           (16U)
+#define XSPI_CALSIR_COARSE_Msk           (0x1FUL << XSPI_CALSIR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSIR_COARSE               XSPI_CALSIR_COARSE_Msk               /*!< Coarse Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 XSPIM                                      */
+/*                                                                            */
+/******************************************************************************/
+/***************  Bit definition for XSPIM_CR register  ********************/
+#define XSPIM_CR_MUXEN_Pos               (0U)
+#define XSPIM_CR_MUXEN_Msk               (0x1UL << XSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */
+#define XSPIM_CR_MUXEN                   XSPIM_CR_MUXEN_Msk                   /*!< Multiplexed Mode Enable */
+#define XSPIM_CR_MODE_Pos                (1U)
+#define XSPIM_CR_MODE_Msk                (0x1UL << XSPIM_CR_MODE_Pos)         /*!< 0x00000002 */
+#define XSPIM_CR_MODE                    XSPIM_CR_MODE_Msk                    /*!< Multiplexing Mode */
+#define XSPIM_CR_CSSEL_OVR_EN_Pos        (4U)
+#define XSPIM_CR_CSSEL_OVR_EN_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_EN_Pos) /*!< 0x00000010 */
+#define XSPIM_CR_CSSEL_OVR_EN            XSPIM_CR_CSSEL_OVR_EN_Msk            /*!< Chip Select Selector Override Enable */
+#define XSPIM_CR_CSSEL_OVR_O1_Pos        (5U)
+#define XSPIM_CR_CSSEL_OVR_O1_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O1_Pos) /*!< 0x00000020 */
+#define XSPIM_CR_CSSEL_OVR_O1            XSPIM_CR_CSSEL_OVR_O1_Msk            /*!< Chip Select Selector Override Setting For XSPI1 */
+#define XSPIM_CR_CSSEL_OVR_O2_Pos        (6U)
+#define XSPIM_CR_CSSEL_OVR_O2_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O2_Pos) /*!< 0x00000040 */
+#define XSPIM_CR_CSSEL_OVR_O2            XSPIM_CR_CSSEL_OVR_O2_Msk            /*!< Chip Select Selector Override Setting For XSPI2 */
+#define XSPIM_CR_REQ2ACK_TIME_Pos        (16U)
+#define XSPIM_CR_REQ2ACK_TIME_Msk        (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
+#define XSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK Time */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Exported_macros
+  * @{
+  */
+#if defined (CPU_IN_SECURE_STATE)
+/* Instances allowed from Secure state */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_S) || ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_S) || ((INSTANCE) == ADC12_COMMON_NS))
+
+/****************************** BSEC Instances *******************************/
+#define IS_BSEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == BSEC_S)
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_S) || ((INSTANCE) == CRC_NS))
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMI_S) || ((INSTANCE) == DCMI_NS))
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMIPP_S) || ((INSTANCE) == DCMIPP_NS))
+
+/********************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_S) || ((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_S) || ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S)  || ((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_S)  || ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_S)  || ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_S)  || ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA2D_S) || ((INSTANCE) == DMA2D_NS))
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DTS_S) || ((INSTANCE) == DTS_NS))
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ETH1_S) || ((INSTANCE) == ETH1_NS))
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_S) || ((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_S) || ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_S) || ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN_CONFIG_S) || ((INSTANCE) == FDCAN_CONFIG_NS))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_S)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_S) || ((INSTANCE) == GFXMMU_NS))
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXTIM_S) || ((INSTANCE) == GFXTIM_NS))
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_S) || ((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_S) || ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_S) || ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_S) || ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_S) || ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_S) || ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_S) || ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_S) || ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_S) || ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_S) || ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_S) || ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_S) || ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPU2D_BASE_S) || ((INSTANCE) == GPU2D_BASE_NS))
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_S) || ((INSTANCE) == I3C1_NS) || \
+                                       ((INSTANCE) == I3C2_S) || ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_S) || ((INSTANCE) == IWDG_NS))
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == JPEG_S) || ((INSTANCE) == JPEG_NS))
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LTDC_S) || ((INSTANCE) == LTDC_NS))
+
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_S) || ((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_S) || ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_S) || ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_S) || ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_S) || ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_S) || ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_S) || ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDIOS_S) || ((INSTANCE) == MDIOS_NS))
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_S) || ((INSTANCE) == PKA_NS))
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PSSI_S) || ((INSTANCE) == PSSI_NS))
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM1_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM2_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM1_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_S)    || ((INSTANCE) == RAMCFG_BKPSRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)    || ((INSTANCE) == RAMCFG_FLEXRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_S)   || ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_S)  || ((INSTANCE) == RAMCFG_BKPSRAM_NS)  || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)  || ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_S) || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_S) || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_S) || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_S) || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_S) || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_S) || ((INSTANCE) == RNG_NS))
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_S) || ((INSTANCE) == RTC_NS))
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_S) || ((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_S) || ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_S) || ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_S) || ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_S) || ((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_S) || ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPDIFRX_S) || ((INSTANCE) == SPDIFRX_NS))
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_S) || ((INSTANCE) == UCPD1_NS))
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_S) || ((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_S) || ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                        ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS) || \
+                                         ((INSTANCE) == TIM18_S)  || ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                               ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                               ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                               ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                          ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                          ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                          ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                          ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                          ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                          ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                          ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                          ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     (((INSTANCE) == TIM15_S)   &&                               \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)                  \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                      ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                      ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                      ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                      ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                      ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_S)  || ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_S)  || ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_S) || ((INSTANCE) == WWDG_NS))
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_S) || ((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_S) || ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_S) || ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPIM_S) || ((INSTANCE) == XSPIM_NS))
+
+#else
+/* Instances allowed from Non-Secure state - only alias Non-Secure */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS)
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI_NS)
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP_NS)
+
+/******************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_NS) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_NS) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D_NS)
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS_NS)
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH1_NS)
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_NS)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU_NS)
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXTIM_NS)
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPU2D_BASE_NS)
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
+                                      ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS)
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == JPEG_NS)
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC_NS)
+
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS_NS)
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI_NS)
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS)
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS)
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX_NS)
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_NS)
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                        ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || \
+                                               ((INSTANCE) == TIM3_NS)  || \
+                                               ((INSTANCE) == TIM4_NS)  || \
+                                               ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || \
+                                          ((INSTANCE) == TIM2_NS)   || \
+                                          ((INSTANCE) == TIM3_NS)   || \
+                                          ((INSTANCE) == TIM4_NS)   || \
+                                          ((INSTANCE) == TIM5_NS)   || \
+                                          ((INSTANCE) == TIM8_NS)   || \
+                                          ((INSTANCE) == TIM15_NS)  || \
+                                          ((INSTANCE) == TIM16_NS)  || \
+                                          ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM9_NS)   &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM10_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM11_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM12_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM13_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM14_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM8_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM15_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM16_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM17_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                      ((INSTANCE) == TIM2_NS)  || \
+                                                      ((INSTANCE) == TIM3_NS)  || \
+                                                      ((INSTANCE) == TIM4_NS)  || \
+                                                      ((INSTANCE) == TIM5_NS)  || \
+                                                      ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS)
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == XSPIM_NS)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Exported_macros */
+
+/** @} */ /* End of group STM32N645xx */
+
+/** @} */ /* End of group ST */
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* STM32N645xx_H */
diff --git a/stm32cube/stm32n6xx/soc/stm32n647xx.h b/stm32cube/stm32n6xx/soc/stm32n647xx.h
new file mode 100644
index 000000000..d6efe3025
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/stm32n647xx.h
@@ -0,0 +1,41832 @@
+/**
+  ******************************************************************************
+  * @file    stm32n647xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N647xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+#ifndef STM32N647xx_H
+#define STM32N647xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup ST
+  * @{
+  */
+
+/** @addtogroup STM32N647xx
+  * @{
+  */
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+typedef enum
+{
+/* ======================================  ARM Cortex-M55 Specific Interrupt Numbers  ======================================== */
+  NonMaskableInt_IRQn        = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted                         */
+  HardFault_IRQn             = -13,    /*!< -13 Hard Fault, all classes of Fault                                               */
+  MemoryManagement_IRQn      = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match       */
+  BusFault_IRQn              = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn            = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition                  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  SecureFault_IRQn           = -9,     /*!< -9  Secure Fault                                                                   */
+#endif
+  SVCall_IRQn                = -5,     /*!< -5  System Service Call via SVC instruction                                        */
+  DebugMonitor_IRQn          = -4,     /*!< -4  Debug Monitor                                                                  */
+  PendSV_IRQn                = -2,     /*!< -2  Pendable request for system service                                            */
+  SysTick_IRQn               = -1,     /*!< -1  System Tick Timer                                                              */
+
+/* ======================================  STM32N6xx Specific Interrupt Numbers  ============================================= */
+  PVD_PVM_IRQn               = 0,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection                                */
+  DTS_IRQn                   = 2,      /*!< Thermal Sensor interruption                                                        */
+  RCC_IRQn                   = 3,      /*!< RCC non-secure global interrupts through EXTI Line detection                       */
+  LOCKUP_IRQn                = 4,      /*!< LOCKUP / (no Overstack in CM55)                                                    */
+  CACHE_ECC_IRQn             = 5,      /*!< Error ECC cache interrupt                                                          */
+  TCM_ECC_IRQn               = 6,      /*!< TCM ECC interrupts                                                                 */
+  BKP_ECC_IRQn               = 7,      /*!< Backup RAM Interrupts                                                              */
+  FPU_IRQn                   = 8,      /*!< FPU interrupt                                                                      */
+  RTC_S_IRQn                 = 10,     /*!< RTC secure interrupts through EXTI Line detection                                  */
+  TAMP_IRQn                  = 11,     /*!< Tamper secure and non-secure interrupts through EXTI Line detection                */
+  RIFSC_TAMPER_IRQn          = 12,     /*!< RIF Tamper interrupts                                                              */
+  IAC_IRQn                   = 13,     /*!< IAC interrupt                                                                      */
+  RCC_S_IRQn                 = 14,     /*!< RCC secure global interrupts through EXTI Line detection                           */
+  RTC_IRQn                   = 16,     /*!< RTC non-secure interrupts through EXTI Line detection                              */
+  IWDG_IRQn                  = 18,     /*!< Internal Watchdog interrupt                                                        */
+  WWDG_IRQn                  = 19,     /*!< Window Watchdog interrupt                                                          */
+  EXTI0_IRQn                 = 20,     /*!< EXTI Line0 interrupt                                                               */
+  EXTI1_IRQn                 = 21,     /*!< EXTI Line1 interrupt                                                               */
+  EXTI2_IRQn                 = 22,     /*!< EXTI Line2 interrupt                                                               */
+  EXTI3_IRQn                 = 23,     /*!< EXTI Line3 interrupt                                                               */
+  EXTI4_IRQn                 = 24,     /*!< EXTI Line4 interrupt                                                               */
+  EXTI5_IRQn                 = 25,     /*!< EXTI Line5 interrupt                                                               */
+  EXTI6_IRQn                 = 26,     /*!< EXTI Line6 interrupt                                                               */
+  EXTI7_IRQn                 = 27,     /*!< EXTI Line7 interrupt                                                               */
+  EXTI8_IRQn                 = 28,     /*!< EXTI Line8 interrupt                                                               */
+  EXTI9_IRQn                 = 29,     /*!< EXTI Line9 interrupt                                                               */
+  EXTI10_IRQn                = 30,     /*!< EXTI Line10 interrupt                                                              */
+  EXTI11_IRQn                = 31,     /*!< EXTI Line11 interrupt                                                              */
+  EXTI12_IRQn                = 32,     /*!< EXTI Line12 interrupt                                                              */
+  EXTI13_IRQn                = 33,     /*!< EXTI Line13 interrupt                                                              */
+  EXTI14_IRQn                = 34,     /*!< EXTI Line14 interrupt                                                              */
+  EXTI15_IRQn                = 35,     /*!< EXTI Line15 interrupt                                                              */
+  PKA_IRQn                   = 38,     /*!< PKA interrupt                                                                      */
+  HASH_IRQn                  = 39,     /*!< HASH interrupt                                                                     */
+  RNG_IRQn                   = 40,     /*!< RNG global interrupt                                                               */
+  ADC1_2_IRQn                = 46,     /*!< ADC1 & ADC2 interrupt                                                              */
+  CSI_IRQn                   = 47,     /*!< CSI global interrupt                                                               */
+  DCMIPP_IRQn                = 48,     /*!< DCMIPP global interrupt                                                            */
+  PAHB_ERR_IRQn              = 52,     /*!< PAHB error interrupt                                                               */
+  NPU0_IRQn                  = 53,     /*!< NPU mst_ints[0] line interrupt                                                     */
+  NPU1_IRQn                  = 54,     /*!< NPU mst_ints[1] line interrupt                                                     */
+  NPU2_IRQn                  = 55,     /*!< NPU mst_ints[2] line interrupt                                                     */
+  NPU3_IRQn                  = 56,     /*!< NPU mst_ints[3] line interrupt                                                     */
+  CACHEAXI_IRQn              = 57,     /*!< NPU cache interrupt                                                                */
+  LTDC_LO_IRQn               = 58,     /*!< LTDC low-layer global interrupt                                                    */
+  LTDC_LO_ERR_IRQn           = 59,     /*!< LTDC low-layer error interrupt                                                     */
+  DMA2D_IRQn                 = 60,     /*!< DMA2D global interrupt                                                             */
+  JPEG_IRQn                  = 61,     /*!< JPEG global interrupt                                                              */
+  VENC_IRQn                  = 62,     /*!< VENC global interrupt                                                              */
+  GFXMMU_IRQn                = 63,     /*!< GFXMMU global interrupt                                                            */
+  GFXTIM_IRQn                = 64,     /*!< GFXTIM global interrupt                                                            */
+  GPU2D_IRQn                 = 65,     /*!< GPU2D interrupt                                                                    */
+  GPU2D_ER_IRQn              = 66,     /*!< GPU2D error interrupt                                                              */
+  ICACHE_IRQn                = 67,     /*!< GPU2D cache interrupt                                                              */
+  HPDMA1_Channel0_IRQn       = 68,     /*!< HPDMA1 Channel 0 global interrupt                                                  */
+  HPDMA1_Channel1_IRQn       = 69,     /*!< HPDMA1 Channel 1 global interrupt                                                  */
+  HPDMA1_Channel2_IRQn       = 70,     /*!< HPDMA1 Channel 2 global interrupt                                                  */
+  HPDMA1_Channel3_IRQn       = 71,     /*!< HPDMA1 Channel 3 global interrupt                                                  */
+  HPDMA1_Channel4_IRQn       = 72,     /*!< HPDMA1 Channel 4 global interrupt                                                  */
+  HPDMA1_Channel5_IRQn       = 73,     /*!< HPDMA1 Channel 5 global interrupt                                                  */
+  HPDMA1_Channel6_IRQn       = 74,     /*!< HPDMA1 Channel 6 global interrupt                                                  */
+  HPDMA1_Channel7_IRQn       = 75,     /*!< HPDMA1 Channel 7 global interrupt                                                  */
+  HPDMA1_Channel8_IRQn       = 76,     /*!< HPDMA1 Channel 8 global interrupt                                                  */
+  HPDMA1_Channel9_IRQn       = 77,     /*!< HPDMA1 Channel 9 global interrupt                                                  */
+  HPDMA1_Channel10_IRQn      = 78,     /*!< HPDMA1 Channel 10 global interrupt                                                 */
+  HPDMA1_Channel11_IRQn      = 79,     /*!< HPDMA1 Channel 11 global interrupt                                                 */
+  HPDMA1_Channel12_IRQn      = 80,     /*!< HPDMA1 Channel 12 global interrupt                                                 */
+  HPDMA1_Channel13_IRQn      = 81,     /*!< HPDMA1 Channel 13 global interrupt                                                 */
+  HPDMA1_Channel14_IRQn      = 82,     /*!< HPDMA1 Channel 14 global interrupt                                                 */
+  HPDMA1_Channel15_IRQn      = 83,     /*!< HPDMA1 Channel 15 global interrupt                                                 */
+  GPDMA1_Channel0_IRQn       = 84,     /*!< GPDMA1 Channel 0 interrupt                                                         */
+  GPDMA1_Channel1_IRQn       = 85,     /*!< GPDMA1 Channel 1 interrupt                                                         */
+  GPDMA1_Channel2_IRQn       = 86,     /*!< GPDMA1 Channel 2 interrupt                                                         */
+  GPDMA1_Channel3_IRQn       = 87,     /*!< GPDMA1 Channel 3 interrupt                                                         */
+  GPDMA1_Channel4_IRQn       = 88,     /*!< GPDMA1 Channel 4 interrupt                                                         */
+  GPDMA1_Channel5_IRQn       = 89,     /*!< GPDMA1 Channel 5 interrupt                                                         */
+  GPDMA1_Channel6_IRQn       = 90,     /*!< GPDMA1 Channel 6 interrupt                                                         */
+  GPDMA1_Channel7_IRQn       = 91,     /*!< GPDMA1 Channel 7 interrupt                                                         */
+  GPDMA1_Channel8_IRQn       = 92,     /*!< GPDMA1 Channel 8 interrupt                                                         */
+  GPDMA1_Channel9_IRQn       = 93,     /*!< GPDMA1 Channel 9 interrupt                                                         */
+  GPDMA1_Channel10_IRQn      = 94,     /*!< GPDMA1 Channel 10 interrupt                                                        */
+  GPDMA1_Channel11_IRQn      = 95,     /*!< GPDMA1 Channel 11 interrupt                                                        */
+  GPDMA1_Channel12_IRQn      = 96,     /*!< GPDMA1 Channel 12 interrupt                                                        */
+  GPDMA1_Channel13_IRQn      = 97,     /*!< GPDMA1 Channel 13 interrupt                                                        */
+  GPDMA1_Channel14_IRQn      = 98,     /*!< GPDMA1 Channel 14 interrupt                                                        */
+  GPDMA1_Channel15_IRQn      = 99,     /*!< GPDMA1 Channel 15 interrupt                                                        */
+  I2C1_EV_IRQn               = 100,    /*!< I2C1 event interrupt                                                               */
+  I2C1_ER_IRQn               = 101,    /*!< I2C1 error interrupt                                                               */
+  I2C2_EV_IRQn               = 102,    /*!< I2C2 event interrupt                                                               */
+  I2C2_ER_IRQn               = 103,    /*!< I2C2 error interrupt                                                               */
+  I2C3_EV_IRQn               = 104,    /*!< I2C3 event interrupt                                                               */
+  I2C3_ER_IRQn               = 105,    /*!< I2C3 error interrupt                                                               */
+  I2C4_EV_IRQn               = 106,    /*!< I2C4 event interrupt                                                               */
+  I2C4_ER_IRQn               = 107,    /*!< I2C4 error interrupt                                                               */
+  I3C1_EV_IRQn               = 108,    /*!< I3C1 event interrupt                                                               */
+  I3C1_ER_IRQn               = 109,    /*!< I3C1 error interrupt                                                               */
+  I3C2_EV_IRQn               = 110,    /*!< I3C2 event interrupt                                                               */
+  I3C2_ER_IRQn               = 111,    /*!< I3C2 error interrupt                                                               */
+  TIM1_BRK_IRQn              = 112,    /*!< TIM1 Break interrupt                                                               */
+  TIM1_UP_IRQn               = 113,    /*!< TIM1 Update interrupt                                                              */
+  TIM1_TRG_COM_IRQn          = 114,    /*!< TIM1 Trigger and Commutation interrupt                                             */
+  TIM1_CC_IRQn               = 115,    /*!< TIM1 Capture Compare interrupt                                                     */
+  TIM2_IRQn                  = 116,    /*!< TIM2 global interrupt                                                              */
+  TIM3_IRQn                  = 117,    /*!< TIM3 global interrupt                                                              */
+  TIM4_IRQn                  = 118,    /*!< TIM4 global interrupt                                                              */
+  TIM5_IRQn                  = 119,    /*!< TIM5 global interrupt                                                              */
+  TIM6_IRQn                  = 120,    /*!< TIM6 global interrupt                                                              */
+  TIM7_IRQn                  = 121,    /*!< TIM7 global interrupt                                                              */
+  TIM8_BRK_IRQn              = 122,    /*!< TIM8 Break interrupt                                                               */
+  TIM8_UP_IRQn               = 123,    /*!< TIM8 Update interrupt                                                              */
+  TIM8_TRG_COM_IRQn          = 124,    /*!< TIM8 Trigger and Commutation interrupt                                             */
+  TIM8_CC_IRQn               = 125,    /*!< TIM8 Capture Compare interrupt                                                     */
+  TIM9_IRQn                  = 126,    /*!< TIM9 global interrupt                                                              */
+  TIM10_IRQn                 = 127,    /*!< TIM10 global interrupt                                                             */
+  TIM11_IRQn                 = 128,    /*!< TIM11 global interrupt                                                             */
+  TIM12_IRQn                 = 129,    /*!< TIM12 global interrupt                                                             */
+  TIM13_IRQn                 = 130,    /*!< TIM13 global interrupt                                                             */
+  TIM14_IRQn                 = 131,    /*!< TIM14 global interrupt                                                             */
+  TIM15_IRQn                 = 132,    /*!< TIM15 global interrupt                                                             */
+  TIM16_IRQn                 = 133,    /*!< TIM16 global interrupt                                                             */
+  TIM17_IRQn                 = 134,    /*!< TIM17 global interrupt                                                             */
+  TIM18_IRQn                 = 135,    /*!< TIM18 global interrupt                                                             */
+  LPTIM1_IRQn                = 136,    /*!< LPTIM1 global interrupt                                                            */
+  LPTIM2_IRQn                = 137,    /*!< LPTIM2 global interrupt                                                            */
+  LPTIM3_IRQn                = 138,    /*!< LPTIM3 global interrupt                                                            */
+  LPTIM4_IRQn                = 139,    /*!< LPTIM4 global interrupt                                                            */
+  LPTIM5_IRQn                = 140,    /*!< LPTIM5 global interrupt                                                            */
+  ADF1_FLT0_IRQn             = 141,    /*!< ADF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT0_IRQn             = 142,    /*!< MDF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT1_IRQn             = 143,    /*!< MDF1 Filter 1 global interrupt                                                     */
+  MDF1_FLT2_IRQn             = 144,    /*!< MDF1 Filter 2 global interrupt                                                     */
+  MDF1_FLT3_IRQn             = 145,    /*!< MDF1 Filter 3 global interrupt                                                     */
+  MDF1_FLT4_IRQn             = 146,    /*!< MDF1 Filter 4 global interrupt                                                     */
+  MDF1_FLT5_IRQn             = 147,    /*!< MDF1 Filter 5 global interrupt                                                     */
+  SAI1_A_IRQn                = 148,    /*!< Serial Audio Interface 1 block A interrupt                                         */
+  SAI1_B_IRQn                = 149,    /*!< Serial Audio Interface 1 block B interrupt                                         */
+  SAI2_A_IRQn                = 150,    /*!< Serial Audio Interface 2 block A interrupt                                         */
+  SAI2_B_IRQn                = 151,    /*!< Serial Audio Interface 2 block B interrupt                                         */
+  SPDIFRX1_IRQn              = 152,    /*!< SPDIFRX1 interrupt                                                                 */
+  SPI1_IRQn                  = 153,    /*!< SPI1 global interrupt                                                              */
+  SPI2_IRQn                  = 154,    /*!< SPI2 global interrupt                                                              */
+  SPI3_IRQn                  = 155,    /*!< SPI3 global interrupt                                                              */
+  SPI4_IRQn                  = 156,    /*!< SPI4 global interrupt                                                              */
+  SPI5_IRQn                  = 157,    /*!< SPI5 global interrupt                                                              */
+  SPI6_IRQn                  = 158,    /*!< SPI6 global interrupt                                                              */
+  USART1_IRQn                = 159,    /*!< USART1 global interrupt                                                            */
+  USART2_IRQn                = 160,    /*!< USART2 global interrupt                                                            */
+  USART3_IRQn                = 161,    /*!< USART3 global interrupt                                                            */
+  UART4_IRQn                 = 162,    /*!< UART4 global interrupt                                                             */
+  UART5_IRQn                 = 163,    /*!< UART5 global interrupt                                                             */
+  USART6_IRQn                = 164,    /*!< USART3 global interrupt                                                            */
+  UART7_IRQn                 = 165,    /*!< UART7 global interrupt                                                             */
+  UART8_IRQn                 = 166,    /*!< UART8 global interrupt                                                             */
+  UART9_IRQn                 = 167,    /*!< UART9 global interrupt                                                             */
+  USART10_IRQn               = 168,    /*!< USART10 global interrupt                                                           */
+  LPUART1_IRQn               = 169,    /*!< LPUART1 global interrupt                                                           */
+  XSPI1_IRQn                 = 170,    /*!< XSPI1 global interrupt                                                             */
+  XSPI2_IRQn                 = 171,    /*!< XSPI2 global interrupt                                                             */
+  XSPI3_IRQn                 = 172,    /*!< XSPI3 global interrupt                                                             */
+  FMC_IRQn                   = 173,    /*!< FMC global interrupt                                                               */
+  SDMMC1_IRQn                = 174,    /*!< SDMMC1 global interrupt                                                            */
+  SDMMC2_IRQn                = 175,    /*!< SDMMC2 global interrupt                                                            */
+  UCPD1_IRQn                 = 176,    /*!< UCPD1 global interrupt                                                             */
+  USB1_OTG_HS_IRQn           = 177,    /*!< USB1 OTG HS interrupt                                                              */
+  USB2_OTG_HS_IRQn           = 178,    /*!< USB2 OTG HS interrupt                                                              */
+  ETH1_IRQn                  = 179,    /*!< ETH1 global interrupt                                                              */
+  FDCAN1_IT0_IRQn            = 180,    /*!< FDCAN1 interrupt 0                                                                 */
+  FDCAN1_IT1_IRQn            = 181,    /*!< FDCAN1 interrupt 1                                                                 */
+  FDCAN2_IT0_IRQn            = 182,    /*!< FDCAN2 interrupt 0                                                                 */
+  FDCAN2_IT1_IRQn            = 183,    /*!< FDCAN2 interrupt 1                                                                 */
+  FDCAN3_IT0_IRQn            = 184,    /*!< FDCAN3 interrupt 0                                                                 */
+  FDCAN3_IT1_IRQn            = 185,    /*!< FDCAN3 interrupt 1                                                                 */
+  FDCAN_CU_IRQn              = 186,    /*!< FDCAN Clock Unit interrupt                                                         */
+  MDIOS_IRQn                 = 187,    /*!< MDIOS global interrupt                                                             */
+  DCMI_PSSI_IRQn             = 188,    /*!< DCMI/PSSI global interrupt                                                         */
+  WAKEUP_PIN_IRQn            = 189,    /*!< Wake-up pins interrupt                                                             */
+  CTI_INT0_IRQn              = 190,    /*!< CTI INT0 interrupt                                                                 */
+  CTI_INT1_IRQn              = 191,    /*!< CTI INT1 interrupt                                                                 */
+  LTDC_UP_IRQn               = 193,    /*!< LTDC up-layer global interrupt                                                     */
+  LTDC_UP_ERR_IRQn           = 194,    /*!< LTDC up-layer error interrupt                                                      */
+} IRQn_Type;
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/**
+  * @brief Configuration of the Cortex-M55 Processor and Core Peripherals
+   */
+#define __CM55_REV                0x0101U /*!< Cortex-M55 revision r1p1                      */
+#define __FPU_PRESENT             1U      /*!< CM55 Floating Point Unit present              */
+#define __DSP_PRESENT             1U      /*!< CM55 Digital Signal Processing Unit present   */
+#define __MPU_PRESENT             1U      /*!< CM55 Memory Programming Unit present          */
+#define __ICACHE_PRESENT          1U      /*!< CM55 Instruction cache present                */
+#define __DCACHE_PRESENT          1U      /*!< CM55 Data cache present                       */
+#define __VTOR_PRESENT            1U      /*!< CM55 Vector table offset register present     */
+#define __PMU_PRESENT             1U      /*!< CM55 Performance Monitoring Unit present      */
+#define __PMU_NUM_EVENTCNT        8U      /*!< CM55 can monitor up to 8 PMU events           */
+#define __NVIC_PRIO_BITS          4U      /*!< CM55 uses 4 bits for the Priority Levels      */
+#define __Vendor_SysTickConfig    0U      /*!< Set to 1 if different SysTick Config is used  */
+#define __SAUREGION_PRESENT       1U      /*!< SAU regions present                           */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define CPU_IN_SECURE_STATE
+#endif
+
+#define CPU_AS_TRUSTED_DOMAIN
+
+#include "core_cm55.h"                    /*!< ARM Cortex-M55 processor and core peripherals */
+#include "system_stm32n6xx.h"             /*!< STM32N6xx System */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup STM32N6xx_peripherals
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter (ADC)
+  */
+typedef struct
+{
+  __IO uint32_t ISR;           /*!< ADC interrupt and status register,                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< ADC interrupt enable register,                         Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< ADC control register,                                  Address offset: 0x08 */
+  __IO uint32_t CFGR1;         /*!< ADC configuration register 1,                          Address offset: 0x0C */
+  __IO uint32_t CFGR2;         /*!< ADC configuration register 2,                          Address offset: 0x10 */
+  __IO uint32_t SMPR1;         /*!< ADC sample time register 1,                            Address offset: 0x14 */
+  __IO uint32_t SMPR2;         /*!< ADC sample time register 2,                            Address offset: 0x18 */
+  __IO uint32_t PCSEL;         /*!< ADC channel preselection register,                     Address offset: 0x1C */
+  uint32_t      RESERVED1[4];  /*!< Reserved,                                              Address offset: 0x020-0x02C */
+  __IO uint32_t SQR1;          /*!< ADC regular sequence register 1,                       Address offset: 0x30 */
+  __IO uint32_t SQR2;          /*!< ADC regular sequence register 2,                       Address offset: 0x34 */
+  __IO uint32_t SQR3;          /*!< ADC regular sequence register 3,                       Address offset: 0x38 */
+  __IO uint32_t SQR4;          /*!< ADC regular sequence register 4,                       Address offset: 0x3C */
+  __IO uint32_t DR;            /*!< ADC regular data register,                             Address offset: 0x40 */
+  uint32_t      RESERVED2[2];  /*!< Reserved,                                              Address offset: 0x044-0x048 */
+  __IO uint32_t JSQR;          /*!< ADC injected sequence register,                        Address offset: 0x4C */
+  __IO uint32_t OFCFGR1;       /*!< ADC offset configuration register 1,                   Address offset: 0x50 */
+  __IO uint32_t OFCFGR2;       /*!< ADC offset configuration register 2,                   Address offset: 0x54 */
+  __IO uint32_t OFCFGR3;       /*!< ADC offset configuration register 3,                   Address offset: 0x58 */
+  __IO uint32_t OFCFGR4;       /*!< ADC offset configuration register 4,                   Address offset: 0x5C */
+  __IO uint32_t OFR1;          /*!< ADC offset register 1,                                 Address offset: 0x60 */
+  __IO uint32_t OFR2;          /*!< ADC offset register 2,                                 Address offset: 0x64 */
+  __IO uint32_t OFR3;          /*!< ADC offset register 3,                                 Address offset: 0x68 */
+  __IO uint32_t OFR4;          /*!< ADC offset register 4,                                 Address offset: 0x6C */
+  __IO uint32_t GCOMP;         /*!< ADC gain compensation register,                        Address offset: 0x70 */
+  uint32_t      RESERVED3[3];  /*!< Reserved,                                              Address offset: 0x074-0x07C */
+  __IO uint32_t JDR1;          /*!< ADC injected data register 1,                          Address offset: 0x80 */
+  __IO uint32_t JDR2;          /*!< ADC injected data register 2,                          Address offset: 0x84 */
+  __IO uint32_t JDR3;          /*!< ADC injected data register 3,                          Address offset: 0x88 */
+  __IO uint32_t JDR4;          /*!< ADC injected data register 4,                          Address offset: 0x8C */
+  uint32_t      RESERVED4[4];  /*!< Reserved,                                              Address offset: 0x090-0x09C */
+  __IO uint32_t AWD2CR;        /*!< ADC analog watchdog 2 configuration register,          Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;        /*!< ADC analog watchdog 3 configuration register,          Address offset: 0xA4 */
+  __IO uint32_t AWD1LTR;       /*!< ADC analog watchdog 1 low threshold register,          Address offset: 0xA8 */
+  __IO uint32_t AWD1HTR;       /*!< ADC analog watchdog 1 high threshold register,         Address offset: 0xAC */
+  __IO uint32_t AWD2LTR;       /*!< ADC analog watchdog 2 low threshold register,          Address offset: 0xB0 */
+  __IO uint32_t AWD2HTR;       /*!< ADC analog watchdog 2 high threshold register,         Address offset: 0xB4 */
+  __IO uint32_t AWD3LTR;       /*!< ADC analog watchdog 3 low threshold register,          Address offset: 0xB8 */
+  __IO uint32_t AWD3HTR;       /*!< ADC analog watchdog 3 high threshold register,         Address offset: 0xBC */
+  __IO uint32_t DIFSEL;        /*!< ADC differential mode selection register,              Address offset: 0xC0 */
+  __IO uint32_t CALFACT;       /*!< ADC calibration factors,                               Address offset: 0xC4 */
+  uint32_t      RESERVED5[2];  /*!< Reserved,                                              Address offset: 0x0C8-0x0CC */
+  __IO uint32_t OR;            /*!< ADC option register,                                   Address offset: 0xD0 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;           /*!< ADC common status register,                            Address offset: 0x300 */
+  uint32_t RESERVED;           /*!< Reserved,                                              Address offset: 0x304 */
+  __IO uint32_t CCR;           /*!< ADC common control register,                           Address offset: 0x308 */
+  __IO uint32_t CDR;           /*!< ADC common regular data register for dual mode,        Address offset: 0x30C */
+  __IO uint32_t CDR2;          /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Boot and Security
+  */
+
+typedef struct
+{
+  __IO uint32_t FVRw[384];       /*!< BSEC fuse word (0-383) value register,       Address offset: 0x000-0x5FC */
+       uint32_t RESERVED0[128];  /*!< Reserved,                                    Address offset: 0x600-0x7FC */
+  __IO uint32_t SPLOCKx[12];     /*!< BSEC sticky program lock register (0-11),    Address offset: 0x800-0x82C */
+       uint32_t RESERVED1[4];    /*!< Reserved,                                    Address offset: 0x830-0x83C */
+  __IO uint32_t SWLOCKx[12];     /*!< BSEC sticky write lock register (0-11),      Address offset: 0x840-0x86C */
+       uint32_t RESERVED2[4];    /*!< Reserved,                                    Address offset: 0x870-0x87C */
+  __IO uint32_t SRLOCKx[12];     /*!< BSEC sticky reload lock register (0-11),     Address offset: 0x880-0x8AC */
+       uint32_t RESERVED3[4];    /*!< Reserved,                                    Address offset: 0x8B0-0x8BC */
+  __IO uint32_t OTPVLDRx[12];    /*!< BSEC OTP valid register (0-11),              Address offset: 0x8C0-0x8EC */
+       uint32_t RESERVED4[20];   /*!< Reserved,                                    Address offset: 0x8F0-0x93C */
+  __IO uint32_t SFSRx[12];       /*!< BSEC shadowed fuses status register (0-11),  Address offset: 0x940-0x96C */
+       uint32_t RESERVED5[165];  /*!< Reserved,                                    Address offset: 0x970-0xC00 */
+  __IO uint32_t OTPCR;           /*!< BSEC OTP control register,                   Address offset: 0xC04 */
+  __IO uint32_t WDR;             /*!< BSEC write data register,                    Address offset: 0xC08 */
+       uint32_t RESERVED6[125];  /*!< Reserved,                                    Address offset: 0xC0C-0xDFC */
+  __IO uint32_t SCRATCHRx[4];    /*!< BSEC scratch register (0-3),                 Address offset: 0xE00-0xE0C */
+  __IO uint32_t LOCKR;           /*!< BSEC lock register,                          Address offset: 0xE10 */
+  __IO uint32_t JTAGINR;         /*!< BSEC JTAG input register,                    Address offset: 0xE14 */
+  __IO uint32_t JTAGOUTR;        /*!< BSEC JTAG output register,                   Address offset: 0xE18 */
+       uint32_t RESERVED7[2];    /*!< Reserved,                                    Address offset: 0xE1C-0xE20 */
+  __IO uint32_t UNMAPR;          /*!< BSEC unmap register,                         Address offset: 0xE24 */
+       uint32_t RESERVED8[6];    /*!< Reserved,                                    Address offset: 0xE28-0xE3C */
+  __IO uint32_t SR;              /*!< BSEC status register,                        Address offset: 0xE40 */
+  __IO uint32_t OTPSR;           /*!< BSEC OTP status register,                    Address offset: 0xE44 */
+       uint32_t RESERVED9[14];   /*!< Reserved,                                    Address offset: 0xE48-0xE7C */
+  __IO uint32_t EPOCHRx[2];      /*!< BSEC epoch register (0-1),                   Address offset: 0xE80-0xE84 */
+  __IO uint32_t EPOCHSELR;       /*!< BSEC epoch select register,                  Address offset: 0xE88 */
+  __IO uint32_t DBGCR;           /*!< BSEC debug control register,                 Address offset: 0xE8C */
+  __IO uint32_t AP_UNLOCK;       /*!< BSEC AP unlock,                              Address offset: 0xE90 */
+  __IO uint32_t HDPLSR;          /*!< BSEC hide protection level status register,  Address offset: 0xE94 */
+  __IO uint32_t HDPLCR;          /*!< BSEC hide protection level control register, Address offset: 0xE98 */
+  __IO uint32_t NEXTLR;          /*!< BSEC next hide protection level register,    Address offset: 0xE9C */
+       uint32_t RESERVED10[40];  /*!< Reserved,                                    Address offset: 0xEA0-0xF3C */
+  __IO uint32_t WOSCRx[8];       /*!< BSEC write once scratch register (0-7),      Address offset: 0xF40-0xF5C */
+       uint32_t RESERVED11[34];  /*!< Reserved,                                    Address offset: 0xF60-0xFE4 */
+  __IO uint32_t HRCR;            /*!< BSEC hot reset count register,               Address offset: 0xFE8 */
+  __IO uint32_t WRCR;            /*!< BSEC warm reset count register,              Address offset: 0xFEC */
+} BSEC_TypeDef;
+
+/**
+  * @brief Axi Cache
+  */
+typedef struct
+{
+  __IO uint32_t CR1;            /*!< CACHEAXI control register 1,                   Address offset: 0x00 */
+  __IO uint32_t SR;             /*!< CACHEAXI status register,                      Address offset: 0x04 */
+  __IO uint32_t IER;            /*!< CACHEAXI interrupt enable register,            Address offset: 0x08 */
+  __IO uint32_t FCR;            /*!< CACHEAXI flag clear register,                  Address offset: 0x0C */
+  __IO uint32_t RHMONR;         /*!< CACHEAXI read hit monitor register,            Address offset: 0x10 */
+  __IO uint32_t RMMONR;         /*!< CACHEAXI read miss monitor register,           Address offset: 0x14 */
+  __IO uint32_t RAMMONR;        /*!< CACHEAXI read-allocate miss monitor register,  Address offset: 0x18 */
+  __IO uint32_t EVIMONR;        /*!< CACHEAXI eviction monitor register,            Address offset: 0x1C */
+  __IO uint32_t WHMONR;         /*!< CACHEAXI write-hit monitor register,           Address offset: 0x20 */
+  __IO uint32_t WMMONR;         /*!< CACHEAXI write-miss monitor register,          Address offset: 0x24 */
+  __IO uint32_t WAMMONR;        /*!< CACHEAXI write-allocate miss monitor register, Address offset: 0x28 */
+  __IO uint32_t WTMONR;         /*!< CACHEAXI write-through monitor register,       Address offset: 0x2C */
+       uint32_t RESERVED1[52];  /*!< Reserved,                                      Address offset: 0x30-0xFC */
+  __IO uint32_t CR2;            /*!< CACHEAXI control register 2,                   Address offset: 0x100 */
+  __IO uint32_t CMDRSADDRR;     /*!< CACHEAXI command start address register,       Address offset: 0x104 */
+  __IO uint32_t CMDREADDRR;     /*!< CACHEAXI command end address register,         Address offset: 0x108 */
+} CACHEAXI_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+typedef struct
+{
+  __IO uint32_t DR;            /*!< CRC Data register,                              Address offset: 0x00 */
+  __IO uint32_t IDR;           /*!< CRC Independent data register,                  Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< CRC Control register,                           Address offset: 0x08 */
+       uint32_t RESERVED1;     /*!< Reserved,                                                       0x0C */
+  __IO uint32_t INIT;          /*!< Initial CRC value register,                     Address offset: 0x10 */
+  __IO uint32_t POL;           /*!< CRC polynomial register,                        Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/*
+ * @brief  (CSI)
+ */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< CSI-2 Host control register                           Address offset: 0x0000 */
+  __IO uint32_t PCR;              /*!< CSI-2 Host DPHY_RX control register                   Address offset: 0x0004 */
+       uint32_t RESERVED0[2];     /*!< Reserved                                              Address offset: 0x0008-0x000C */
+  __IO uint32_t VC0CFGR1;         /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */
+  __IO uint32_t VC0CFGR2;         /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */
+  __IO uint32_t VC0CFGR3;         /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */
+  __IO uint32_t VC0CFGR4;         /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */
+  __IO uint32_t VC1CFGR1;         /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */
+  __IO uint32_t VC1CFGR2;         /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */
+  __IO uint32_t VC1CFGR3;         /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */
+  __IO uint32_t VC1CFGR4;         /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */
+  __IO uint32_t VC2CFGR1;         /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */
+  __IO uint32_t VC2CFGR2;         /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */
+  __IO uint32_t VC2CFGR3;         /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */
+  __IO uint32_t VC2CFGR4;         /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */
+  __IO uint32_t VC3CFGR1;         /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */
+  __IO uint32_t VC3CFGR2;         /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */
+  __IO uint32_t VC3CFGR3;         /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */
+  __IO uint32_t VC3CFGR4;         /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */
+  __IO uint32_t LB0CFGR;          /*!< CSI-2 Host line byte 0 configuration register         Address offset: 0x0050 */
+  __IO uint32_t LB1CFGR;          /*!< CSI-2 Host line byte 1 configuration register         Address offset: 0x0054 */
+  __IO uint32_t LB2CFGR;          /*!< CSI-2 Host line byte 2 configuration register         Address offset: 0x0058 */
+  __IO uint32_t LB3CFGR;          /*!< CSI-2 Host line byte 3 configuration register         Address offset: 0x005C */
+  __IO uint32_t TIM0CFGR;         /*!< CSI-2 Host timer 0 configuration register             Address offset: 0x0060 */
+  __IO uint32_t TIM1CFGR;         /*!< CSI-2 Host timer 1 configuration register             Address offset: 0x0064 */
+  __IO uint32_t TIM2CFGR;         /*!< CSI-2 Host timer 2 configuration register             Address offset: 0x0068 */
+  __IO uint32_t TIM3CFGR;         /*!< CSI-2 Host timer 3 configuration register             Address offset: 0x006C */
+  __IO uint32_t LMCFGR;           /*!< CSI-2 Host lane merger configuration register         Address offset: 0x0070 */
+  __IO uint32_t PRGITR;           /*!< CSI-2 Host program interrupt register                 Address offset: 0x0074 */
+  __IO uint32_t WDR;              /*!< CSI-2 Host watchdog register                          Address offset: 0x0078 */
+       uint32_t RESERVED1;        /*!< Reserved                                              Address offset: 0x007C */
+  __IO uint32_t IER0;             /*!< CSI-2 Host Interrupt enable register 0                Address offset: 0x0080 */
+  __IO uint32_t IER1;             /*!< CSI-2 Host Interrupt enable register 1                Address offset: 0x0084 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                              Address offset: 0x0088-0x008C */
+  __IO uint32_t SR0;              /*!< CSI-2 Host status register 0                          Address offset: 0x0090 */
+  __IO uint32_t SR1;              /*!< CSI-2 Host status register 1                          Address offset: 0x0094 */
+       uint32_t RESERVED3[26];    /*!< Reserved                                              Address offset: 0x0098-0x00FC */
+  __IO uint32_t FCR0;             /*!< CSI-2 Host Flag clear register 0                      Address offset: 0x0100 */
+  __IO uint32_t FCR1;             /*!< CSI-2 Host Flag clear register 1                      Address offset: 0x0104 */
+       uint32_t RESERVED4[2];     /*!< Reserved                                              Address offset: 0x0108-0x010C */
+  __IO uint32_t SPDFR;            /*!< CSI-2 Host short packet data field register           Address offset: 0x0110 */
+  __IO uint32_t ERR1;             /*!< CSI-2 Host error register 1                           Address offset: 0x0114 */
+  __IO uint32_t ERR2;             /*!< CSI-2 Host error register 2                           Address offset: 0x0118 */
+       uint32_t RESERVED5[953];   /*!< Reserved                                              Address offset: 0x011C-0x0FFC */
+  __IO uint32_t PRCR;             /*!< CSI PHY reset control register                        Address offset: 0x1000 */
+  __IO uint32_t PMCR;             /*!< CSI PHY mode control register                         Address offset: 0x1004 */
+  __IO uint32_t PFCR;             /*!< CSI PHY frequency control register                    Address offset: 0x1008 */
+       uint32_t RESERVED6;        /*!< Reserved                                              Address offset: 0x100C */
+  __IO uint32_t PTCR0;            /*!< CSI PHY test control register 0                       Address offset: 0x1010 */
+  __IO uint32_t PTCR1;            /*!< CSI PHY test control register 1                       Address offset: 0x1014 */
+  __IO uint32_t PTSR;             /*!< CSI PHY test status register                          Address offset: 0x1018 */
+       uint32_t RESERVED7[1017];  /*!< Reserved                                              Address offset: 0x101C-0x1FFC */
+} CSI_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                            Address offset: 0x00  */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,              Address offset: 0x04  */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t APB1LFZ1;      /*!< Debug MCU APB1LFZ1 freeze register,            Address offset: 0x10  */
+  __IO uint32_t APB1HFZ1;      /*!< Debug MCU APB1HFZ1 freeze register,            Address offset: 0x14  */
+  __IO uint32_t APB2FZ1;       /*!< Debug MCU APB2FZ1 freeze register,             Address offset: 0x18  */
+  __IO uint32_t APB4FZ1;       /*!< Debug MCU APB4FZ1 freeze register,             Address offset: 0x1C  */
+  __IO uint32_t APB5FZ1;       /*!< Debug MCU APB5FZ1 freeze register,             Address offset: 0x20  */
+  __IO uint32_t AHB1FZ1;       /*!< Debug MCU AHB1FZ1 freeze register,             Address offset: 0x24  */
+  __IO uint32_t AHB5FZ1;       /*!< Debug MCU AHB5FZ1 freeze register,             Address offset: 0x28  */
+  uint32_t RESERVED2[52];      /*!< Reserved,                                  Address offset: 0x2C-0xF8 */
+  __IO uint32_t SR;            /*!< Debug MCU status register,                     Address offset: 0xFC  */
+  __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register,        Address offset: 0x100 */
+  __IO uint32_t DBG_AUTH_DEV;  /*!< Debug MCU authentication device register,      Address offset: 0x104 */
+  __IO uint32_t DBG_AUTH_ACK;  /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */
+} DBGMCU_TypeDef;
+
+/**
+  * @brief DCMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+#define DCMIPP_NUM_OF_PIPES 0x03U
+
+typedef struct
+{
+  uint32_t PxRIxCR1;      /*! DCMIPP Pipex ROIx configuration register 1  Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2)  */
+  uint32_t PxRIxCR2;      /*! DCMIPP Pipex ROIx configuration register 2  Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2)  */
+} DCMIPP_Region_TypeDef;
+
+/*
+ * @brief Digital camera interface pixel pipeline DCMIPP
+ */
+typedef struct
+{
+  __IO uint32_t IPGR1;           /*!< DCMIPP IPPLUG global register 1                                    Address offset: 0x000 */
+  __IO uint32_t IPGR2;           /*!< DCMIPP IPPLUG global register 2                                    Address offset: 0x004 */
+  __IO uint32_t IPGR3;           /*!< DCMIPP IPPLUG global register 3                                    Address offset: 0x008 */
+       uint32_t RESERVED0[4];    /*!< Reserved                                                           Address offset: 0x00C-0x018 */
+  __IO uint32_t IPGR8;           /*!< DCMIPP IPPLUG identification register                              Address offset: 0x01C */
+  __IO uint32_t IPC1R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */
+       uint32_t RESERVED1;       /*!< Reserved                                                           Address offset: 0x02C */
+  __IO uint32_t IPC2R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x030 */
+  __IO uint32_t IPC2R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x034 */
+  __IO uint32_t IPC2R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x038 */
+       uint32_t RESERVED2;       /*!< Reserved                                                           Address offset: 0x03C */
+  __IO uint32_t IPC3R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x040 */
+  __IO uint32_t IPC3R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x044 */
+  __IO uint32_t IPC3R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x048 */
+       uint32_t RESERVED3;       /*!< Reserved                                                           Address offset: 0x04C */
+  __IO uint32_t IPC4R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x050 */
+  __IO uint32_t IPC4R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x054 */
+  __IO uint32_t IPC4R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x058 */
+       uint32_t RESERVED4;       /*!< Reserved                                                           Address offset: 0x05C */
+  __IO uint32_t IPC5R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x060 */
+  __IO uint32_t IPC5R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x064 */
+  __IO uint32_t IPC5R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x068 */
+       uint32_t RESERVED5[38];   /*!< Reserved                                                           Address offset: 0x06C-0x100 */
+  __IO uint32_t PRCR;            /*!< DCMIPP parallel interface control register                         Address offset: 0x104 */
+  __IO uint32_t PRESCR;          /*!< DCMIPP parallel interface embedded synchronization code register   Address offset: 0x108 */
+  __IO uint32_t PRESUR;          /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */
+       uint32_t RESERVED6[57];   /*!< Reserved                                                           Address offset: 0x110-0x1F0 */
+  __IO uint32_t PRIER;           /*!< DCMIPP parallel interface interrupt enable register                Address offset: 0x1F4 */
+  __IO uint32_t PRSR;            /*!< DCMIPP parallel interface status register                          Address offset: 0x1F8 */
+  __IO uint32_t PRFCR;           /*!< DCMIPP parallel interface interrupt clear register                 Address offset: 0x1FC */
+       uint32_t RESERVED7;       /*!< Reserved                                                           Address offset: 0x200 */
+  __IO uint32_t CMCR;            /*!< DCMIPP common configuration register                               Address offset: 0x204 */
+  __IO uint32_t CMFRCR;          /*!< DCMIPP common frame counter register                               Address offset: 0x208 */
+       uint32_t RESERVED8[121];  /*!< Reserved                                                           Address offset: 0x20C-0x3EC */
+  __IO uint32_t CMIER;           /*!< DCMIPP common interrupt enable register                            Address offset: 0x3F0 */
+  __IO uint32_t CMSR1;           /*!< DCMIPP common status register 1                                    Address offset: 0x3F4 */
+  __IO uint32_t CMSR2;           /*!< DCMIPP common status register 2                                    Address offset: 0x3F8 */
+  __IO uint32_t CMFCR;           /*!< DCMIPP common interrupt clear register                             Address offset: 0x3FC */
+       uint32_t RESERVED9;            /*!< Reserved                                                      Address offset: 0x400 */
+  __IO uint32_t P0FSCR;          /*!< DCMIPP Pipe0 flow selection configuration register                 Address offset: 0x404 */
+       uint32_t RESERVED10[62];  /*!< Reserved                                                           Address offset: 0x408-0x4FC */
+  __IO uint32_t P0FCTCR;         /*!< DCMIPP Pipe0 flow control configuration register                   Address offset: 0x500 */
+  __IO uint32_t P0SCSTR;         /*!< DCMIPP Pipe0 stat/crop start register                              Address offset: 0x504 */
+  __IO uint32_t P0SCSZR;         /*!< DCMIPP Pipe0 stat/crop size register                               Address offset: 0x508 */
+       uint32_t RESERVED11[41];  /*!< Reserved                                                           Address offset: 0x50C-0x5AC */
+  __IO uint32_t P0DCCNTR;        /*!< DCMIPP Pipe0 dump counter register                                 Address offset: 0x5B0 */
+  __IO uint32_t P0DCLMTR;        /*!< DCMIPP Pipe0 dump limit register                                   Address offset: 0x5B4 */
+       uint32_t RESERVED12[2];   /*!< Reserved                                                           Address offset: 0x5B8-0x5BC */
+  __IO uint32_t P0PPCR;          /*!< DCMIPP Pipe0 pixel packer configuration register                   Address offset: 0x5C0 */
+  __IO uint32_t P0PPM0AR1;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1               Address offset: 0x5C4 */
+  __IO uint32_t P0PPM0AR2;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2               Address offset: 0x5C8 */
+       uint32_t RESERVED13;      /*!< Reserved                                                           Address offset: 0x5C8-0x5CC */
+  __IO uint32_t P0STM0AR;        /*!< DCMIPP Pipe0 status Memory0 address register                       Address offset: 0x5D0 */
+       uint32_t RESERVED14[8];   /*!< Reserved                                                           Address offset: 0x5D4-0x5F0 */
+  __IO uint32_t P0IER;           /*!< DCMIPP Pipe0 interrupt enable register                             Address offset: 0x5F4 */
+  __IO uint32_t P0SR;            /*!< DCMIPP Pipe0 status register                                       Address offset: 0x5F8 */
+  __IO uint32_t P0FCR;           /*!< DCMIPP Pipe0 interrupt clear register                              Address offset: 0x5FC */
+       uint32_t RESERVED15;      /*!< Reserved                                                           Address offset: 0x600 */
+  __IO uint32_t P0CFSCR;         /*!< DCMIPP Pipe0 current flow selection configuration register         Address offset: 0x604 */
+       uint32_t RESERVED17[62];  /*!< Reserved                                                           Address offset: 0x608-0x6FC */
+  __IO uint32_t P0CFCTCR;        /*!< DCMIPP Pipe0 current flow control configuration register           Address offset: 0x700 */
+  __IO uint32_t P0CSCSTR;        /*!< DCMIPP Pipe0 current stat/crop start register                      Address offset: 0x704 */
+  __IO uint32_t P0CSCSZR;        /*!< DCMIPP Pipe0 current stat/crop size register                       Address offset: 0x708 */
+       uint32_t RESERVED18[45];  /*!< Reserved                                                           Address offset: 0x70C-0x7BC */
+  __IO uint32_t P0CPPCR;         /*!< DCMIPP Pipe0 current pixel packer configuration register           Address offset: 0x7C0 */
+  __IO uint32_t P0CPPM0AR1;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1       Address offset: 0x7C4 */
+  __IO uint32_t P0CPPM0AR2;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2       Address offset: */
+       uint32_t RESERVED19[14];  /*!< Reserved                                                           Address offset: 0x7C8-0x7FC */
+  __IO uint32_t P1FSCR;          /*!< DCMIPP Pipe1 flow selection configuration register                 Address offset: 0x804 */
+       uint32_t RESERVED20[6];   /*!< Reserved                                                           Address offset: 0x808-0x81C */
+  __IO uint32_t P1SRCR;          /*!< DCMIPP Pipe1 stat removal configuration register                   Address offset: 0x820 */
+  __IO uint32_t P1BPRCR;         /*!< DCMIPP Pipe1 bad pixel removal control register                    Address offset: 0x824 */
+  __IO uint32_t P1BPRSR;         /*!< DCMIPP Pipe1 bad pixel removal status register                     Address offset: 0x828 */
+       uint32_t RESERVED21;      /*!< Reserved                                                           Address offset: 0x82C */
+  __IO uint32_t P1DECR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x830 */
+       uint32_t RESERVED22[3];   /*!< Reserved                                                           Address offset: 0x834-0x83C */
+  __IO uint32_t P1BLCCR;         /*!< DCMIPP Pipe1 black level calibration control register              Address offset: 0x840 */
+  __IO uint32_t P1EXCR1;         /*!< DCMIPP Pipe1 exposure control register 1                           Address offset: 0x844 */
+  __IO uint32_t P1EXCR2;         /*!< DCMIPP Pipe1 exposure control register 2                           Address offset: 0x848 */
+       uint32_t RESERVED23;      /*!< Reserved                                                           Address offset: 0x84C */
+  __IO uint32_t P1ST1CR;         /*!< DCMIPP Pipe1 statistics 1 control register                         Address offset: 0x850 */
+  __IO uint32_t P1ST2CR;         /*!< DCMIPP Pipe1 statistics 2 control register                         Address offset: 0x854 */
+  __IO uint32_t P1ST3CR;         /*!< DCMIPP Pipe1 statistics 3 control register                         Address offset: 0x858 */
+  __IO uint32_t P1STSTR;         /*!< DCMIPP Pipe1 statistics window start register                      Address offset: 0x85C */
+  __IO uint32_t P1STSZR;         /*!< DCMIPP Pipe1 statistics window size register                       Address offset: 0x860 */
+  __IO uint32_t P1ST1SR;         /*!< DCMIPP Pipe1 statistics 1 status register                          Address offset: 0x864 */
+  __IO uint32_t P1ST2SR;         /*!< DCMIPP Pipe1 statistics 2 status register                          Address offset: 0x868 */
+  __IO uint32_t P1ST3SR;         /*!< DCMIPP Pipe1 statistics 3 status register                          Address offset: 0x86C */
+  __IO uint32_t P1DMCR;          /*!< DCMIPP Pipe1 demosaicing configuration register                    Address offset: 0x870 */
+       uint32_t RESERVED24[3];   /*!< Reserved                                                           Address offset: 0x874-0x87C */
+  __IO uint32_t P1CCCR;          /*!< DCMIPP Pipe1 ColorConv configuration register                      Address offset: 0x880 */
+  __IO uint32_t P1CCRR1;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 1                  Address offset: 0x884 */
+  __IO uint32_t P1CCRR2;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 2                  Address offset: 0x888 */
+  __IO uint32_t P1CCGR1;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 1                Address offset: 0x88C */
+  __IO uint32_t P1CCGR2;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 2                Address offset: 0x890 */
+  __IO uint32_t P1CCBR1;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1                 Address offset: 0x894 */
+  __IO uint32_t P1CCBR2;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2                 Address offset: 0x898 */
+       uint32_t RESERVED25;      /*!< Reserved                                                           Address offset: 0x89C */
+  __IO uint32_t P1CTCR1;         /*!< DCMIPP Pipe1 contrast control register 1                           Address offset: 0x8A0 */
+  __IO uint32_t P1CTCR2;         /*!< DCMIPP Pipe1 contrast control register 2                           Address offset: 0x8A4 */
+  __IO uint32_t P1CTCR3;         /*!< DCMIPP Pipe1 contrast control register 3                           Address offset: 0x8A8 */
+       uint32_t RESERVED26[21];  /*!< Reserved                                                           Address offset: 0x8AC-0x8FC */
+  __IO uint32_t P1FCTCR;         /*!< DCMIPP Pipe1 flow control configuration register                   Address offset: 0x900 */
+  __IO uint32_t P1CRSTR;         /*!< DCMIPP Pipe1 crop window start register                            Address offset: 0x904 */
+  __IO uint32_t P1CRSZR;         /*!< DCMIPP Pipe1 crop window size register                             Address offset: 0x908 */
+  __IO uint32_t P1DCCR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x90C */
+  __IO uint32_t P1DSCR;          /*!< DCMIPP Pipe1 downsize configuration register                       Address offset: 0x910 */
+  __IO uint32_t P1DSRTIOR;       /*!< DCMIPP Pipe1 downsize ratio register                               Address offset: 0x914 */
+  __IO uint32_t P1DSSZR;         /*!< DCMIPP Pipe1 downsize destination size register                    Address offset: 0x918 */
+       uint32_t RESERVED28;      /*!< Reserved                                                           Address offset:  */
+  __IO uint32_t P1CMRICR;        /*!< DCMIPP Pipe1 common ROI configuration register                     Address offset: 0x920 */
+  __IO uint32_t P1RIxCR1;        /*!< DCMIPP Pipe1 ROIx configuration register 1                         Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P1RIxCR2;        /*!< DCMIPP Pipe1 ROIx configuration register 2                         Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED29[17];      /*!< Reserved                                                       Address offset:  */
+  __IO uint32_t P1GMCR;          /*!< DCMIPP Pipe1 gamma configuration register                          Address offset: 0x970 */
+       uint32_t RESERVED30[3];   /*!< Reserved                                                           Address offset: 0x974-0x97C */
+  __IO uint32_t P1YUVCR;         /*!< DCMIPP Pipe1 YUVConv configuration register                        Address offset: 0x980 */
+  __IO uint32_t P1YUVRR1;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 1                    Address offset: 0x984 */
+  __IO uint32_t P1YUVRR2;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 2                    Address offset: 0x988 */
+  __IO uint32_t P1YUVGR1;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 1                  Address offset: 0x98C */
+  __IO uint32_t P1YUVGR2;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 2                  Address offset: 0x990 */
+  __IO uint32_t P1YUVBR1;        /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1                   Address offset: 0x994 */
+  __IO uint32_t P1YUVBR2;        /*!< DCMIPP Pipe1 YUV blue coefficient register 2                       Address offset: 0x998 */
+       uint32_t RESERVED31[9];   /*!< Reserved                                                           Address offset: 0x99C-0x9BC */
+  __IO uint32_t P1PPCR;          /*!< DCMIPP Pipe1 pixel packer configuration register                   Address offset: 0x9C0 */
+  __IO uint32_t P1PPM0AR1;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1               Address offset: 0x9C4 */
+  __IO uint32_t P1PPM0AR2;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2               Address offset: 0x9C8 */
+  __IO uint32_t P1PPM0PR;        /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register                   Address offset: 0x9CC */
+  __IO uint32_t P1STM0AR;        /*!< DCMIPP Pipe1 status Memory0 address register                       Address offset: 0x9D0 */
+  __IO uint32_t P1PPM1AR1;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1               Address offset: 0x9D4 */
+  __IO uint32_t P1PPM1AR2;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2               Address offset: 0x9D8 */
+  __IO uint32_t P1PPM1PR;        /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register                   Address offset: 0x9DC */
+  __IO uint32_t P1STM1AR;        /*!< DCMIPP Pipe1 status Memory1 address register                       Address offset: 0x9E0 */
+  __IO uint32_t P1PPM2AR1;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 1               Address offset: 0x9E4 */
+  __IO uint32_t P1PPM2AR2;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 2               Address offset: 0x9E8 */
+  __IO uint32_t RESERVED34;      /*!< Reserved                                                           Address offset: 0x9EC */
+  __IO uint32_t P1STM2AR;        /*!< DCMIPP Pipe1 status Memory2 address register                       Address offset: 0x9F0 */
+  __IO uint32_t P1IER;           /*!< DCMIPP Pipe1 interrupt enable register                             Address offset: 0x9F4 */
+  __IO uint32_t P1SR;            /*!< DCMIPP Pipe1 status register                                       Address offset: 0x9F8 */
+  __IO uint32_t P1FCR;           /*!< DCMIPP Pipe1 interrupt clear register                              Address offset: 0x9FC */
+       uint32_t RESERVED35;      /*!< Reserved                                                           Address offset: 0xA00 */
+  __IO uint32_t P1CFSCR;         /*!< DCMIPP Pipe1 current flow selection configuration register         Address offset: 0xA04 */
+       uint32_t RESERVED36[7];   /*!< Reserved                                                           Address offset: 0xA08-0xA20 */
+  __IO uint32_t P1CBPRCR;        /*!< DCMIPP Pipe1 current bad pixel removal register                    Address offset: 0xA24 */
+       uint32_t RESERVED37[6];   /*!< Reserved                                                           Address offset: 0xA28-0xA3C */
+  __IO uint32_t P1CBLCCR;        /*!< DCMIPP Pipe1 current black level calibration control register      Address offset: 0xA40 */
+  __IO uint32_t P1CEXCR1;        /*!< DCMIPP Pipe1 current exposure control register 1                   Address offset: 0xA44 */
+  __IO uint32_t P1CEXCR2;        /*!< DCMIPP Pipe1 current exposure control register 2                   Address offset: 0xA48 */
+       uint32_t RESERVED38;      /*!< Reserved                                                           Address offset: 0xA4C */
+  __IO uint32_t P1CST1CR;        /*!< DCMIPP Pipe1 current statistics 1 control register                 Address offset: 0xA50 */
+  __IO uint32_t P1CST2CR;        /*!< DCMIPP Pipe1 current statistics 2 control register                 Address offset: 0xA54 */
+  __IO uint32_t P1CST3CR;        /*!< DCMIPP Pipe1 current statistics 3 control register                 Address offset: 0xA58 */
+  __IO uint32_t P1CSTSTR;        /*!< DCMIPP Pipe1 current statistics window start register              Address offset: 0xA5C */
+  __IO uint32_t P1CSTSZR;        /*!< DCMIPP Pipe1 current statistics window size register               Address offset: 0xA60 */
+       uint32_t RESERVED39[7];   /*!< Reserved                                                           Address offset: 0xA64-0xA7C */
+  __IO uint32_t P1CCCCR;         /*!< DCMIPP Pipe1 current ColorConv configuration register              Address offset: 0xA80 */
+  __IO uint32_t P1CCCRR1;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1          Address offset: 0xA84 */
+  __IO uint32_t P1CCCRR2;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2          Address offset: 0xA88 */
+  __IO uint32_t P1CCCGR1;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1        Address offset: 0xA8C */
+  __IO uint32_t P1CCCGR2;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2        Address offset: 0xA90 */
+  __IO uint32_t P1CCCBR1;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1         Address offset: 0xA94 */
+  __IO uint32_t P1CCCBR2;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2         Address offset: 0xA98 */
+       uint32_t RESERVED40;      /*!< Reserved                                                           Address offset: 0xA9C */
+  __IO uint32_t P1CCTCR1;        /*!< DCMIPP Pipe1 current contrast control register 1                   Address offset: 0xAA0 */
+  __IO uint32_t P1CCTCR2;        /*!< DCMIPP Pipe1 current contrast control register 2                   Address offset: 0xAA4 */
+  __IO uint32_t P1CCTCR3;        /*!< DCMIPP Pipe1 current contrast control register 3                   Address offset: 0xAA8 */
+       uint32_t RESERVED41[21];  /*!< Reserved                                                           Address offset: 0xAAC-0xAFC */
+  __IO uint32_t P1CFCTCR;        /*!< DCMIPP Pipe1 current flow control configuration register           Address offset: 0xB00 */
+  __IO uint32_t P1CCRSTR;        /*!< DCMIPP Pipe1 current crop window start register                    Address offset: 0xB04 */
+  __IO uint32_t P1CCRSZR;        /*!< DCMIPP Pipe1 current crop window size register                     Address offset: 0xB08 */
+  __IO uint32_t P1CDCCR;         /*!< DCMIPP Pipe1 current decimation register                           Address offset: 0xB0C */
+  __IO uint32_t P1CDSCR;         /*!< DCMIPP Pipe1 current downsize configuration register               Address offset: 0xB10 */
+  __IO uint32_t P1CDSRTIOR;      /*!< DCMIPP Pipe1 current downsize ratio register                       Address offset: 0xB14 */
+  __IO uint32_t P1CDSSZR;        /*!< DCMIPP Pipe1 current downsize destination size register            Address offset: 0xB18 */
+       uint32_t RESERVED43;      /*!< Reserved                                                           Address offset: 0xB1C */
+       uint32_t P1CCMRICR;       /*!< DCMIPP Pipe1 current common ROI configuration register             Address offset: 0xB20 */
+  __IO uint32_t P1CRIxCR1;       /*!< DCMIPP Pipe1 current ROIx configuration register 1                 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */
+  __IO uint32_t P1CRIxCR2;       /*!< DCMIPP Pipe1 current ROIx configuration register 2                 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */
+  uint32_t RESERVED44[37];       /*!< Reserved                                                           Address offset: 0xB64-0xBBC */
+  __IO uint32_t P1CPPCR;         /*!< DCMIPP Pipe1 current pixel packer configuration register           Address offset: 0xBC0 */
+  __IO uint32_t P1CPPM0AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC4 */
+  __IO uint32_t P1CPPM0AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC8 */
+  __IO uint32_t P1CPPM0PR;       /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register           Address offset: 0xBCC */
+       uint32_t RESERVED45;      /*!< Reserved                                                           Address offset: 0xBD0 */
+  __IO uint32_t P1CPPM1AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1       Address offset: 0xBD4 */
+  __IO uint32_t P1CPPM1AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2       Address offset: 0xBD8 */
+  __IO uint32_t P1CPPM1PR;       /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register           Address offset: 0xBDC */
+       uint32_t RESERVED47;      /*!< Reserved                                                           Address offset: 0xBE0 */
+  __IO uint32_t P1CPPM2AR1;      /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1       Address offset: 0xBE4 */
+  __IO uint32_t P1CPPM2AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2       Address offset: 0xBE8 */
+       uint32_t RESERVED48[6];   /*!< Reserved                                                           Address offset: 0xBE8-0xBFC */
+  __IO uint32_t P2FSCR;          /*!< DCMIPP Pipe2 flow selection configuration register                 Address offset: 0xC04 */
+       uint32_t RESERVED49[62];  /*!< Reserved                                                           Address offset: 0xC08-0xCFC */
+  __IO uint32_t P2FCTCR;         /*!< DCMIPP Pipe2 flow control configuration register                   Address offset: 0xD00 */
+  __IO uint32_t P2CRSTR;         /*!< DCMIPP Pipe2 crop window start register                            Address offset: 0xD04 */
+  __IO uint32_t P2CRSZR;         /*!< DCMIPP Pipe2 crop window size register                             Address offset: 0xD08 */
+  __IO uint32_t P2DCCR;          /*!< DCMIPP Pipe2 decimation register                                   Address offset: 0xD0C */
+  __IO uint32_t P2DSCR;          /*!< DCMIPP Pipe2 downsize configuration register                       Address offset: 0xD10 */
+  __IO uint32_t P2DSRTIOR;       /*!< DCMIPP Pipe2 downsize ratio register                               Address offset: 0xD14 */
+  __IO uint32_t P2DSSZR;         /*!< DCMIPP Pipe2 downsize destination size register                    Address offset: 0xD18 */
+       uint32_t RESERVED51;      /*!< Reserved                                                           Address offset:  0xD1C */
+  __IO uint32_t P2CMRICR;        /*!< DCMIPP Pipe2 common ROI configuration register                     Address offset:  0xD20 */
+  __IO uint32_t P2RIxCR1;        /*!< DCMIPP Pipe2 ROIx configuration register 1                         Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P2RIxCR2;        /*!< DCMIPP Pipe2 ROIx configuration register 2                         Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED53[17];  /*!< Reserved                                                           Address offset: */
+  __IO uint32_t P2GMCR;          /*!< DCMIPP Pipe2 gamma configuration register                          Address offset: 0xD70 */
+       uint32_t RESERVED54[19];  /*!< Reserved                                                           Address offset: 0xD74-0xDBC */
+  __IO uint32_t P2PPCR;          /*!< DCMIPP Pipe2 pixel packer configuration register                   Address offset: 0xDC0 */
+  __IO uint32_t P2PPM0AR1;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1               Address offset: 0xDC4 */
+  __IO uint32_t P2PPM0AR2;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2               Address offset: 0xDC8 */
+  __IO uint32_t P2PPM0PR;        /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register                   Address offset: 0xDCC */
+  __IO uint32_t P2STM0AR;        /*!< DCMIPP Pipe2 status Memory0 address register                       Address offset: 0xDD0 */
+       uint32_t RESERVED55[8];   /*!< Reserved                                                           Address offset: 0xDD4-0xDF0 */
+  __IO uint32_t P2IER;           /*!< DCMIPP Pipe2 interrupt enable register                             Address offset: 0xDF4 */
+  __IO uint32_t P2SR;            /*!< DCMIPP Pipe2 status register                                       Address offset: 0xDF8 */
+  __IO uint32_t P2FCR;           /*!< DCMIPP Pipe2 interrupt clear register                              Address offset: 0xDFC */
+       uint32_t RESERVED56;      /*!< Reserved                                                           Address offset: 0xE00 */
+  __IO uint32_t P2CFSCR;         /*!< DCMIPP Pipe2 current flow selection configuration register         Address offset: 0xE04 */
+       uint32_t RESERVED57[62];  /*!< Reserved                                                           Address offset: 0xE08-0xEFC */
+  __IO uint32_t P2CFCTCR;        /*!< DCMIPP Pipe2 current flow control configuration register           Address offset: 0xF00 */
+  __IO uint32_t P2CCRSTR;        /*!< DCMIPP Pipe2 current crop window start register                    Address offset: 0xF04 */
+  __IO uint32_t P2CCRSZR;        /*!< DCMIPP Pipe2 current crop window size register                     Address offset: 0xF08 */
+  __IO uint32_t P2CDCCR;         /*!< DCMIPP Pipe2 current decimation register                           Address offset: 0xF0C */
+  __IO uint32_t P2CDSCR;         /*!< DCMIPP Pipe2 current downsize configuration register               Address offset: 0xF10 */
+  __IO uint32_t P2CDSRTIOR;      /*!< DCMIPP Pipe2 current downsize ratio register                       Address offset: 0xF14 */
+  __IO uint32_t P2CDSSZR;        /*!< DCMIPP Pipe2 current downsize destination size register            Address offset: 0xF18 */
+  __IO uint32_t RESERVED59[2];   /*!< Reserved                                                           Address offset: 0xF1C-0xF20 */
+  __IO uint32_t P2CRIxCR1;       /*!< Pipe2 current ROIx configuration register 1                        Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/
+  __IO uint32_t P2CRIxCR2;       /*!< Pipe2 current ROIx configuration register 2                        Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/
+       uint32_t RESERVED60[37];  /*!< Reserved                                                           Address offset: 0xF64-0xFBC */
+  __IO uint32_t P2CPPCR;         /*!< DCMIPP Pipe2 current pixel packer configuration register           Address offset: 0xFC0 */
+  __IO uint32_t P2CPPM0AR1;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1       Address offset: 0xFC4 */
+  __IO uint32_t P2CPPM0AR2;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2       Address offset: 0xFC8 */
+  __IO uint32_t P2CPPM0PR;       /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register           Address offset: 0xFCC */
+       uint32_t RESERVED61[7];   /*!< Reserved                                                           Address offset: 0xFD0-0xFE8 */
+  __IO uint32_t HWCFGR2;         /*!< DCMIPP hardware configuration register 2                           Address offset: 0xFEC */
+  __IO uint32_t HWCFGR1;         /*!< DCMIPP hardware configuration register 1                           Address offset: 0xFF0 */
+  __IO uint32_t VERR;            /*!< DCMIPP version register                                            Address offset: 0xFF4 */
+  __IO uint32_t IPIDR;           /*!< DCMIPP identification register                                     Address offset: 0xFF8 */
+  __IO uint32_t SIDR;            /*!< DCMIPP size identification register                                Address offset: 0xFFC */
+} DCMIPP_TypeDef;
+
+/**
+  * @ brief Delay Block
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< Delay Block Control Register,       Address offset: 0x00 */
+  __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t SECCFGR;      /*!< DMA secure configuration register,               Address offset: 0x00  */
+  __IO uint32_t PRIVCFGR;     /*!< DMA privileged configuration register,           Address offset: 0x04 */
+  __IO uint32_t RCFGLOCKR;    /*!< DMA configuration lock register,                 Address offset: 0x08 */
+  __IO uint32_t MISR;         /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
+  __IO uint32_t SMISR;        /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CLBAR;         /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
+  __IO uint32_t CCIDCFGR;      /*!< DMA channel x CID register,                      Address offset: 0x54 + (x * 0x80) */
+       uint32_t RESERVED1[1];  /*!< Reserved 1,                                      Address offset: 0x58 + (x * 0x80) */
+  __IO uint32_t CFCR;          /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
+  __IO uint32_t CSR;           /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
+  __IO uint32_t CCR;           /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
+       uint32_t RESERVED2[10]; /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C + (x * 0x80) */
+  __IO uint32_t CTR1;          /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
+  __IO uint32_t CTR2;          /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
+  __IO uint32_t CBR1;          /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
+  __IO uint32_t CSAR;          /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
+  __IO uint32_t CDAR;          /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
+  __IO uint32_t CTR3;          /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
+  __IO uint32_t CBR2;          /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
+       uint32_t RESERVED3[8];  /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8 + (x * 0x80) */
+  __IO uint32_t CLLR;          /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
+} DMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
+} DMA2D_TypeDef;
+
+/**
+  * @brief DTS Controller
+  */
+typedef struct
+{
+  uint32_t      RESERVED1[4];    /*!< Reserved,                                 Address offset: 0x00-0x0F */
+  __IO uint32_t PVTREG_LOCKR;    /*!< DTS PVT Register Lock Register,           Address offset: 0x10 */
+  __IO uint32_t PVTLOCK_SR;      /*!< DTS PVT Lock Status Register,             Address offset: 0x14 */
+  uint32_t      RESERVED2[2];    /*!< Reserved,                                 Address offset: 0x18-0x1F */
+  __IO uint32_t PVTTMR_CR;       /*!< DTS PVT Timer Control Register,           Address offset: 0x20 */
+  __IO uint32_t PVTTMR_SR;       /*!< DTS PVT Timer Status Register,            Address offset: 0x24 */
+  uint32_t      RESERVED3[6];    /*!< Reserved,                                 Address offset: 0x28-0x3F */
+  __IO uint32_t PVT_IER;         /*!< DTS PVT IRQ Enable Register,              Address offset: 0x40 */
+  uint32_t      RESERVED4[3];    /*!< Reserved,                                 Address offset: 0x44-0x4F */
+  __IO uint32_t PVTIRQTRMASKR;   /*!< DTS PVT IRQ Timer Mask Register,          Address offset: 0x50 */
+  __IO uint32_t TS_MR;           /*!< DTS PVT IRQ TS Mask Register,             Address offset: 0x54 */
+  uint32_t      RESERVED5[2];    /*!< Reserved,                                 Address offset: 0x58-0x5F */
+  __IO uint32_t PVTTR_SR;        /*!< DTS PVT IRQ Timer Status Register,        Address offset: 0x60 */
+  __IO uint32_t TS_ISR;          /*!< DTS PVT IRQ TS Status Register,           Address offset: 0x64 */
+  uint32_t      RESERVED6[2];    /*!< Reserved,                                 Address offset: 0x68-0x6F */
+  __IO uint32_t PVTTMRRAW_ISR;   /*!< DTS PVT IRQ Timer Raw Status Register,    Address offset: 0x70 */
+  __IO uint32_t TSRAW_ISR;       /*!< DTS PVT IRQ TS Raw Status Register,       Address offset: 0x74 */
+  uint32_t      RESERVED7[2];    /*!< Reserved,                                 Address offset: 0x78-0x7F */
+  __IO uint32_t TSCCLKSYNTHR;    /*!< DTS TSC Clock Synthesizer Register,       Address offset: 0x80 */
+  __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register,  Address offset: 0x84 */
+  __IO uint32_t TSCSDIF_SR;      /*!< DTS TSC SDIF Status Register,             Address offset: 0x88 */
+  __IO uint32_t TSCSDIF_CR;      /*!< DTS TSC SDIF Register,                    Address offset: 0x8C */
+  __IO uint32_t TSCSDIFHALTR;    /*!< DTS TSC SDIF Halt Register,               Address offset: 0x90 */
+  __IO uint32_t TSCSDIF_CFGR;    /*!< DTS TSC SDIF Control Register,            Address offset: 0x94 */
+  uint32_t      RESERVED8[2];    /*!< Reserved,                                 Address offset: 0x98-0x9F */
+  __IO uint32_t TSCSMPL_CR;      /*!< DTS TSC Sample Control Register,          Address offset: 0xA0 */
+  __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register,            Address offset: 0xA4 */
+  __IO uint32_t TSCSMPLCNTR;     /*!< DTS TSC Sample Count Register,            Address offset: 0xA8 */
+} DTS_TypeDef;
+
+/**
+  * @brief DTS Sensor Controller
+  */
+typedef struct
+{
+  __IO uint32_t TS_IER;          /*!< DTS TSx IRQ Enable Register,              Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ISR;          /*!< DTS TSx IRQ Status Register,              Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ICR;          /*!< DTS TSx IRQ Clear Register,               Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSIRQTESTR;      /*!< DTS TSx IRQ Test Register,                Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFRDATAR;    /*!< DTS TSx SDIF RDATA Register,              Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDONER;     /*!< DTS TSx SDIF Done Register,               Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDATAR;     /*!< DTS TSx SDIF Data Register,               Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */
+  uint32_t      RESERVED1[1];    /*!< Reserved,                                 Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMA_CFGR;   /*!< DTS TSx Alarm A Configuration Register,   Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMB_CFGR;   /*!< DTS TSx Alarm B Configuration Register,   Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHLSAMPLER;     /*!< DTS TSx High/Low Sample Register,         Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHILORESETR;    /*!< DTS TSx High/Low Reset Register,          Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */
+} DTS_SensorTypeDef;
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;               /*!< Operating mode configuration register,                        Address offset: 0x00 */
+  __IO uint32_t MACECR;              /*!< Extended operating mode configuration register,               Address offset: 0x04 */
+  __IO uint32_t MACPFR;              /*!< Packet filtering control register             ,               Address offset: 0x08 */
+  __IO uint32_t MACWTR;              /*!< Watchdog timeout register,                                    Address offset: 0x0C */
+  __IO uint32_t MACHT0R;             /*!< Hash Table 0 register,                                        Address offset: 0x10 */
+  __IO uint32_t MACHT1R;             /*!< Hash Table 1 register,                                        Address offset: 0x14 */
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTCR;             /*!< VLAN tag Control register,                                    Address offset: 0x50 */
+  __IO uint32_t MACVTDR;             /*!< VLAN tag data register,                                       Address offset: 0x54 */
+  __IO uint32_t MACVHTR;             /*!< VLAN Hash table register,                                     Address offset: 0x58 */
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVIR;              /*!< VLAN inclusion register,                                      Address offset: 0x60 */
+  __IO uint32_t MACIVIR;             /*!< Inner VLAN inclusion register,                                Address offset: 0x64 */
+  uint32_t      RESERVED3[2];
+  __IO uint32_t MACQ0TXFCR;          /*!< Tx Queue 0 flow control register,                             Address offset: 0x70 */
+  uint32_t      RESERVED4[7];
+  __IO uint32_t MACRXFCR;            /*!< Rx flow control register,                                     Address offset: 0x90 */
+  __IO uint32_t MACRXQCR;            /*!< Rx Queue control register,                                    Address offset: 0x94 */
+  uint32_t      RESERVED5[2];
+  __IO uint32_t MACRXQC0R;           /*!< Rx queue control 0 register,                                  Address offset: 0xA0 */
+  __IO uint32_t MACRXQC1R;           /*!< Rx queue control 1 register,                                  Address offset: 0xA4 */
+  __IO uint32_t MACRXQC2R;           /*!< Rx queue control 2 register,                                  Address offset: 0xA8 */
+  uint32_t      RESERVED6;
+  __IO uint32_t MACISR;              /*!< Interrupt status register,                                    Address offset: 0xB0 */
+  __IO uint32_t MACIER;              /*!< Interrupt enable register,                                    Address offset: 0xB4 */
+  __IO uint32_t MACRXTXSR;           /*!< Rx Tx status register,                                        Address offset: 0xB8 */
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;             /*!< PMT control status register,                                  Address offset: 0xC0 */
+  __IO uint32_t MACRWKPFR;           /*!< Remote wakeup packet filter register,                         Address offset: 0xC4 */
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;             /*!< LPI control and status register,                              Address offset: 0xD0 */
+  __IO uint32_t MACLTCR;             /*!< LPI timers control register,                                  Address offset: 0xD4 */
+  __IO uint32_t MACLETR;             /*!< LPI entry timer register,                                     Address offset: 0xD8 */
+  __IO uint32_t MAC1USTCR;           /*!< One-microsecond-tick counter register,                        Address offset: 0xDC */
+  uint32_t      RESERVED9[6];
+  __IO uint32_t MACPHYCSR;           /*!< PHYIF control status register,                                Address offset: 0xF8 */
+  uint32_t      RESERVED10[5];
+  __IO uint32_t MACVR;               /*!< Version register,                                             Address offset: 0x110 */
+  __IO uint32_t MACDR;               /*!< Debug register,                                               Address offset: 0x114 */
+  uint32_t      RESERVED11;
+  __IO uint32_t MACHWF0R;            /*!< HW feature 0 register,                                        Address offset: 0x11C */
+  __IO uint32_t MACHWF1R;            /*!< HW feature 1 register,                                        Address offset: 0x120 */
+  __IO uint32_t MACHWF2R;            /*!< HW feature 2 register,                                        Address offset: 0x124 */
+  __IO uint32_t MACHWF3R;            /*!< HW feature 3 register,                                        Address offset: 0x128 */
+  uint32_t      RESERVED12[53];
+  __IO uint32_t MACMDIOAR;           /*!< MDIO address register,                                        Address offset: 0x200 */
+  __IO uint32_t MACMDIODR;           /*!< MDIO data register,                                           Address offset: 0x204 */
+  uint32_t      RESERVED13[2];
+  __IO uint32_t MACARPAR;            /*!< ARP address register,                                         Address offset: 0x210 */
+  uint32_t      RESERVED14[7];
+  __IO uint32_t MACCSRSWCR;          /*!< CSR software control register,                                Address offset: 0x230 */
+  __IO uint32_t MACFPECSR;           /*!< FPE control and status register,                              Address offset: 0x234 */
+   uint32_t     RESERVED15[2];
+  __IO uint32_t MACPRSTIMR;          /*!< MAC presentation time register,                               Address offset: 0x0240 */
+  __IO uint32_t MACPRSTIMUR;         /*!< MAC presentation time update register,                        Address offset: 0x0244 */
+   uint32_t     RESERVED16[46];
+  __IO uint32_t MACA0HR;             /*!< MAC Address 0 high register,                                  Address offset: 0x0300 */
+  __IO uint32_t MACA0LR;             /*!< MAC Address 0 low register,                                   Address offset: 0x0304 */
+  __IO uint32_t MACA1HR;             /*!< MAC Address 1 high register,                                  Address offset: 0x0308 */
+  __IO uint32_t MACA1LR;             /*!< MAC Address 1 low register,                                   Address offset: 0x030C */
+  __IO uint32_t MACA2HR;             /*!< MAC Address 2 high register,                                  Address offset: 0x0310 */
+  __IO uint32_t MACA2LR;             /*!< MAC Address 2 low register,                                   Address offset: 0x0314 */
+  __IO uint32_t MACA3HR;             /*!< MAC Address 3 high register,                                  Address offset: 0x0318 */
+  __IO uint32_t MACA3LR;             /*!< MAC Address 3 low register,                                   Address offset: 0x031C */
+  uint32_t      RESERVED17[248];
+  __IO uint32_t MMCCR;               /*!< MMC control register,                                         Address offset: 0x0700 */
+  __IO uint32_t MMCRIR;              /*!< MMC Rx interrupt register,                                    Address offset: 0x0704 */
+  __IO uint32_t MMCTIR;              /*!< MMC Tx interrupt register,                                    Address offset: 0x0708 */
+  __IO uint32_t MMCRIMR;             /*!< MMC Rx interrupt mask register,                               Address offset: 0x070C */
+  __IO uint32_t MMCTIMR;             /*!< MMC Tx interrupt mask register,                               Address offset: 0x0710 */
+  uint32_t      RESERVED18[14];
+  __IO uint32_t MMCTSCGPR;           /*!< Tx single collision good packets register,                    Address offset: 0x074C */
+  __IO uint32_t MMCTMCGPR;           /*!< Tx multiple collision good packets register,                  Address offset: 0x0750 */
+  uint32_t      RESERVED19[5];
+  __IO uint32_t MMCTPCGR;            /*!< Tx packet count good register,                                Address offset: 0x0768 */
+  uint32_t      RESERVED20[10];
+  __IO uint32_t MMCRCRCEPR;          /*!< Rx CRC error packets register,                                Address offset: 0x0794 */
+  __IO uint32_t MMCRAEPR;            /*!< Rx alignment error packets register,                          Address offset: 0x0798 */
+  uint32_t      RESERVED21[10];
+  __IO uint32_t MMCRUPGR;            /*!< Rx unicast packets good register,                             Address offset: 0x07C4 */
+  uint32_t      RESERVED22[9];
+  __IO uint32_t MMCTLPIMSTR;         /*!< Tx LPI microsecond timer register,                            Address offset: 0x07EC */
+  __IO uint32_t MMCTLPITCR;          /*!< Tx LPI transition counter register,                           Address offset: 0x07F0 */
+  __IO uint32_t MMCRLPIMSTR;         /*!< Rx LPI microsecond counter register,                          Address offset: 0x07F4 */
+  __IO uint32_t MMCRLPITCR;          /*!< Rx LPI transition counter register,                           Address offset: 0x07F8 */
+  uint32_t      RESERVED23[41];
+  __IO uint32_t MMCFPETISR;          /*!< MMC FPE Tx interrupt status register,                         Address offset: 0x08A0 */
+  __IO uint32_t MMCFPETIMR;          /*!< MMC FPE Tx interrupt mask register,                           Address offset: 0x08A4 */
+  __IO uint32_t MMCFPETFCR;          /*!< MMC FPE Tx fragment counter register,       -                 Address offset: 0x08A8 */
+  __IO uint32_t MMCTHRCR;            /*!< MMC Tx hold request counter register,                         Address offset: 0x08AC */
+  uint32_t      RESERVED24[4];
+  __IO uint32_t MMCFPERISR;          /*!< MMC FPE Rx interrupt status register,                         Address offset: 0x08C0 */
+  __IO uint32_t MMCFPERIMR;          /*!< MMC FPE Rx interrupt mask register,                           Address offset: 0x08C4 */
+  __IO uint32_t MMCRPAER;            /*!< MMC Rx packet assembly error register,                        Address offset: 0x08C8 */
+  __IO uint32_t MMCRPSMDER;          /*!< MMC Rx packet SMD error register,                             Address offset: 0x08CC */
+  __IO uint32_t MMCRPAOKR;           /*!< MMC Rx packet assembly OK register,                           Address offset: 0x08D0 */
+  __IO uint32_t MMCFPERFCR;          /*!< MMC Rx FPE fragments counter register,                        Address offset: 0x08D4 */
+  uint32_t      RESERVED25[10];
+  __IO uint32_t MACL3L4C0R;          /*!< L3 and L4 control 0 register,                                 Address offset: 0x0900 */
+  __IO uint32_t MACL4A0R;            /*!< Layer4 Address filter 0 register,                             Address offset: 0x0904 */
+  uint32_t      RESERVED26[2];
+  __IO uint32_t MACL3A0R0R;           /*!< Layer3 Address 0 filter 0 register,                           Address offset: 0x0910 */
+  __IO uint32_t MACL3A1R0R;           /*!< Layer3 Address 1 filter 0 register,                           Address offset: 0x0914 */
+  __IO uint32_t MACL3A2R0R;           /*!< Layer3 Address 2 filter 0 register,                           Address offset: 0x0918 */
+  __IO uint32_t MACL3A3R0R;           /*!< Layer3 Address 3 filter 0 register,                           Address offset: 0x091C */
+  uint32_t      RESERVED27[4];
+  __IO uint32_t MACL3L4C1R;          /*!< L3 and L4 control 1 register,                                 Address offset: 0x0930 */
+  __IO uint32_t MACL4A1R;            /*!< Layer 4 address filter 1 register,                            Address offset: 0x0934 */
+  uint32_t      RESERVED28[2];
+  __IO uint32_t MACL3A01R;           /*!< Layer3 address 0 filter 1 Register,                           Address offset: 0x0940 */
+  __IO uint32_t MACL3A11R;           /*!< Layer3 address 1 filter 1 register,                           Address offset: 0x0944 */
+  __IO uint32_t MACL3A21R;           /*!< Layer3 address 2 filter 1 Register,                           Address offset: 0x0948 */
+  __IO uint32_t MACL3A31R;           /*!< Layer3 address 3 filter 1 register,                           Address offset: 0x094C */
+  uint32_t      RESERVED29[72];
+  __IO uint32_t MACIACR;             /*!< MAC Indirect Access Control register,                         Address offset: 0x0A70 */
+  __IO uint32_t MACTMRQR;            /*!< MAC type-based Rx Queue mapping register,                     Address offset: 0x0A74 */
+  uint32_t      RESERVED30[34];
+  __IO uint32_t MACTSCR;             /*!< Timestamp control Register,                                   Address offset: 0x0B00 */
+  __IO uint32_t MACSSIR;             /*!< Subsecond increment register,                                 Address offset: 0x0B04 */
+  __IO uint32_t MACSTSR;             /*!< System time seconds register,                                 Address offset: 0x0B08 */
+  __IO uint32_t MACSTNR;             /*!< System time nanoseconds register,                             Address offset: 0x0B0C */
+  __IO uint32_t MACSTSUR;            /*!< System time seconds update register,                          Address offset: 0x0B10 */
+  __IO uint32_t MACSTNUR;            /*!< System time nanoseconds update register,                      Address offset: 0x0B14 */
+  __IO uint32_t MACTSAR;             /*!< Timestamp addend register,                                    Address offset: 0x0B18 */
+  uint32_t      RESERVED31;
+  __IO uint32_t MACTSSR;             /*!< Timestamp status register,                                    Address offset: 0x0B20 */
+  uint32_t      RESERVED32[3];
+  __IO uint32_t MACTXTSSNR;          /*!< Tx timestamp status nanoseconds register,                     Address offset: 0x0B30 */
+  __IO uint32_t MACTXTSSSR;          /*!< Tx timestamp status seconds register,                         Address offset: 0x0B34 */
+  uint32_t      RESERVED33[2];
+  __IO uint32_t MACACR;              /*!< Auxiliary control register,                                   Address offset: 0x0B40 */
+  uint32_t      RESERVED34;
+  __IO uint32_t MACATSNR;            /*!< Auxiliary timestamp nanoseconds register,                     Address offset: 0x0B48 */
+  __IO uint32_t MACATSSR;            /*!< Auxiliary timestamp seconds register,                         Address offset: 0x0B4C */
+  __IO uint32_t MACTSIACR;           /*!< Timestamp Ingress asymmetric correction register,             Address offset: 0x0B50 */
+  __IO uint32_t MACTSEACR;           /*!< Timestamp Egress asymmetric correction register,              Address offset: 0x0B54 */
+  __IO uint32_t MACTSICNR;           /*!< Timestamp Ingress correction nanosecond register,             Address offset: 0x0B58 */
+  __IO uint32_t MACTSECNR;           /*!< Timestamp Egress correction nanosecond register,              Address offset: 0x0B5C */
+  uint32_t      RESERVED35[2];
+  __IO uint32_t MACTSILR;            /*!< Timestamp Ingress Latency register,                           Address offset: 0x0B68 */
+  __IO uint32_t MACTSELR;            /*!< Timestamp Egress Latency register,                            Address offset: 0x0B6C */
+  __IO uint32_t MACPPSCR;            /*!< PPS control register,                                         Address offset: 0x0B70 */
+  uint32_t      RESERVED36[3];
+  __IO uint32_t MACPPSTTS0R;         /*!< PPS 0 target time seconds register,                           Address offset: 0x0B80 */
+  __IO uint32_t MACPPSTTN0R;         /*!< PPS 0 target time nanoseconds register,                       Address offset: 0x0B84 */
+  __IO uint32_t MACPPSI0R;           /*!< PPS 0 interval register,                                      Address offset: 0x0B88 */
+  __IO uint32_t MACPPSW0R;           /*!< PPS 0 width register,                                         Address offset: 0x0B8C */
+  __IO uint32_t MACPPSTTS1R;         /*!< PPS 1 target time seconds register,                           Address offset: 0x0B90 */
+  __IO uint32_t MACPPSTTN1R;         /*!< PPS 1 target time nanoseconds register,                       Address offset: 0x0B94 */
+  __IO uint32_t MACPPSI1R;           /*!< PPS 1 interval register,                                      Address offset: 0x0B98 */
+  __IO uint32_t MACPPSW1R;           /*!< PPS 1 width register,                                         Address offset: 0x0B9C */
+  uint32_t      RESERVED37[8];
+  __IO uint32_t MACPOCR;             /*!< PTP Offload control register,                                 Address offset: 0x0BC0 */
+  __IO uint32_t MACSPI0R;            /*!< PTP Source Port Identity 0 Register,                          Address offset: 0x0BC4 */
+  __IO uint32_t MACSPI1R;            /*!< PTP Source port identity 1 register,                          Address offset: 0x0BC8 */
+  __IO uint32_t MACSPI2R;            /*!< PTP Source port identity 2 register,                          Address offset: 0x0BCC */
+  __IO uint32_t MACLMIR;             /*!< Log message interval register,                                Address offset: 0x0BD0 */
+  uint32_t      RESERVED38[11];
+  __IO uint32_t MTLOMR;              /*!< Operating mode Register,                                      Address offset: 0x0C00 */
+  uint32_t      RESERVED39[7];
+  __IO uint32_t MTLISR;              /*!< Interrupt status Register,                                    Address offset: 0x0C20 */
+  uint32_t      RESERVED40[3];
+  __IO uint32_t MTLRXQDMAMR;         /*!< Rx Queue and DMA Channel Mapping Register,                    Address offset: 0x0C30 */
+  uint32_t      RESERVED41[3];
+  __IO uint32_t MTLTBSCR;            /*!< TBS control register,                                         Address offset: 0x0C40 */
+  uint32_t      RESERVED42[3];
+  __IO uint32_t MTLESTCR;            /*!< EST Control Register,                                         Address offset: 0x0C50 */
+  __IO uint32_t MTLESTECR;           /*!< EST Extended Control Register,                                Address offset: 0x0C54 */
+  __IO uint32_t MTLESTSR;            /*!< EST Status Register,                                          Address offset: 0x0C58 */
+  uint32_t      RESERVED43;
+  __IO uint32_t MTLESTSCHER;         /*!< EST Schedule Error Register,                                  Address offset: 0x0C60 */
+  __IO uint32_t MTLESTFSER;          /*!< EST Frame size Error Register,                                Address offset: 0x0C64 */
+  __IO uint32_t MTLESTFSCR;          /*!< EST Frame size Capture Register,                              Address offset: 0x0C68 */
+  uint32_t      RESERVED44;
+  __IO uint32_t MTLESTIER;           /*!< EST Interrupt Enable Register,                                Address offset: 0x0C70 */
+  uint32_t      RESERVED45[3];
+  __IO uint32_t MTLESTGCLCR;         /*!< EST Gate Control List Register,                               Address offset: 0x0C80 */
+  __IO uint32_t MTLESTGCLDR;         /*!< EST Gate Control List Data Register,                          Address offset: 0x0C84 */
+  uint32_t      RESERVED46[2];
+  __IO uint32_t MTLFPECSR;           /*!< FPE Frame Preemption Control Status Register,                 Address offset: 0x0C90 */
+  __IO uint32_t MTLFPEAR;            /*!< FPE Frame Preemption Advance Register,                        Address offset: 0x0C94 */
+  uint32_t      RESERVED47[26];
+  struct {
+  __IO uint32_t MTLTXQOMR;           /*!< Tx queue x operating mode Register,                           Address offset: 0x0D00 */
+  __IO uint32_t MTLTXQUR;            /*!< Tx queue x underflow register,                                Address offset: 0x0D04 */
+  __IO uint32_t MTLTXQDR;            /*!< Tx queue x debug register,                                    Address offset: 0x0D08 */
+  uint32_t      RESERVED48[1];
+  __IO uint32_t MTLTXQ1ECR;           /*!< Tx queue 1 ETS control Register,                              Address offset: 0x0D50 */
+  __IO uint32_t MTLTXQESR;           /*!< Tx queue x ETS status Register,                               Address offset: 0x0D14 */
+  __IO uint32_t MTLTXQQWR;           /*!< Tx queue x quantum weight register,                           Address offset: 0x0D18 */
+  __IO uint32_t MTLTXQ1SSCR;          /*!< Tx queue 1 send slope credit Register,                        Address offset: 0x0D5C */
+  __IO uint32_t MTLTXQ1HCR;           /*!< Tx Queue 1 hiCredit register,                                 Address offset: 0x0D60 */
+  __IO uint32_t MTLTXQ1LCR;           /*!< Tx queue 1 loCredit register,                                 Address offset: 0x0D64 */
+  uint32_t      RESERVED49[1];
+  __IO uint32_t MTLQICSR;           /*!< Queue 0 interrupt control status Register,                    Address offset: 0x0D2C */
+  __IO uint32_t MTLRXQOMR;          /*!< Rx queue x operating mode register,                           Address offset: 0x0D30 */
+  __IO uint32_t MTLRXQMPOCR;        /*!< Rx queue x missed packet and overflow counter register,       Address offset: 0x0D34 */
+  __IO uint32_t MTLRXQDR;           /*!< Rx queue x debug register,                                    Address offset: 0x0D38 */
+  __IO uint32_t MTLRXQCR;           /*!< Rx queue x control register,                                  Address offset: 0x0D3C */
+  } MTL_QUEUE[2];
+  uint32_t      RESERVED52[160];
+  __IO uint32_t DMAMR;               /*!< DMA mode register,                                            Address offset: 0x1000 */
+  __IO uint32_t DMASBMR;             /*!< System bus mode register,                                     Address offset: 0x1004 */
+  __IO uint32_t DMAISR;              /*!< Interrupt status register,                                    Address offset: 0x1008 */
+  __IO uint32_t DMADSR;              /*!< Debug status register,                                        Address offset: 0x100C */
+  uint32_t      RESERVED53[4];
+  __IO uint32_t DMAA4TXACR;          /*!< AXI4 transmit channel ACE control register,                   Address offset: 0x1020 */
+  __IO uint32_t DMAA4RXACR;          /*!< AXI4 receive channel ACE control register,                    Address offset: 0x1024 */
+  __IO uint32_t DMAA4DACR;           /*!< AXI4 descriptor ACE control register,                         Address offset: 0x1028 */
+  uint32_t      RESERVED54[5];
+  __IO uint32_t DMALPIEI;            /*!< AXI4 LPI Entry Interval register,                             Address offset: 0x1040 */
+  uint32_t      RESERVED55[3];
+  __IO uint32_t DMATBSCTRL0R;        /*!< DMA TBS control register 0,                                   Address offset: 0x1050 */
+  uint32_t      RESERVED56[37];
+  struct {
+  uint32_t      RESERVED57[6];
+  __IO uint32_t DMACCR;             /*!< Channel x control register,                                   Address offset: 0x1100 */
+  __IO uint32_t DMACTXCR;           /*!< Channel x transmit control register,                          Address offset: 0x1104 */
+  __IO uint32_t DMACRXCR;           /*!< Channel x receive control register,                           Address offset: 0x1108 */
+  uint32_t      RESERVED58[2];
+  __IO uint32_t DMACTXDLAR;         /*!< Channel x Tx descriptor list address register,                Address offset: 0x1114 */
+  uint32_t      RESERVED59;
+  __IO uint32_t DMACRXDLAR;         /*!< Channel x Rx descriptor list address register,                Address offset: 0x111C */
+  __IO uint32_t DMACTXDTPR;         /*!< Channel x Tx descriptor tail pointer register,                Address offset: 0x1120 */
+  uint32_t      RESERVED60;
+  __IO uint32_t DMACRXDTPR;         /*!< Channel x Rx descriptor tail pointer register,                Address offset: 0x1128 */
+  __IO uint32_t DMACTXRLR;          /*!< Channel x Tx descriptor ring length register,                 Address offset: 0x112C */
+  __IO uint32_t DMACRXRLR;          /*!< Channel x Rx descriptor ring length register,                 Address offset: 0x1130 */
+  __IO uint32_t DMACIER;            /*!< Channel x interrupt enable register,                          Address offset: 0x1134 */
+  __IO uint32_t DMACRXIWTR;         /*!< Channel x Rx interrupt watchdog timer register,               Address offset: 0x1138 */
+  __IO uint32_t DMACSFCSR;          /*!< Channel x slot function control status register,              Address offset: 0x113C */
+  uint32_t      RESERVED61;
+  __IO uint32_t DMACCATXDR;         /*!< Channel x current application transmit descriptor register,   Address offset: 0x1144 */
+  uint32_t      RESERVED62;
+  __IO uint32_t DMACCARXDR;         /*!< Channel x current application receive descriptor register,    Address offset: 0x114C */
+  uint32_t      RESERVED63;
+  __IO uint32_t DMACCATXBR;         /*!< Channel x current application transmit buffer register,       Address offset: 0x1154 */
+  uint32_t      RESERVED64;
+  __IO uint32_t DMACCARXBR;         /*!< Channel x current application receive buffer register,        Address offset: 0x115C */
+  __IO uint32_t DMACSR;             /*!< Channel x status register,                                    Address offset: 0x1160 */
+  __IO uint32_t DMACMFCR;            /*!< Channel x missed frame count register,                        Address offset: 0x1164 */
+  } DMA_CH[2];
+}ETH_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+typedef struct
+{
+  __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
+  __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
+  __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
+  __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
+  __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
+  __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
+  __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
+       uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x1C */
+  __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
+  __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
+  __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
+  __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
+  __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
+  __IO uint32_t SECCFGR2;       /*!< EXTI Security Configuration Register 2,          Address offset:   0x34 */
+  __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
+       uint32_t RESERVED2;      /*!< Reserved 2,                                      Address offset:   0x3C */
+  __IO uint32_t RTSR3;          /*!< EXTI Rising Trigger Selection Register 3,        Address offset:   0x40 */
+  __IO uint32_t FTSR3;          /*!< EXTI Falling Trigger Selection Register 3,       Address offset:   0x44 */
+  __IO uint32_t SWIER3;         /*!< EXTI Software Interrupt event Register 3,        Address offset:   0x48 */
+  __IO uint32_t RPR3;           /*!< EXTI Rising Pending Register 3,                  Address offset:   0x4C */
+  __IO uint32_t FPR3;           /*!< EXTI Falling Pending Register 3,                 Address offset:   0x50 */
+  __IO uint32_t SECCFGR3;       /*!< EXTI Security Configuration Register 3,          Address offset:   0x54 */
+  __IO uint32_t PRIVCFGR3;      /*!< EXTI Privilege Configuration Register 3,         Address offset:   0x58 */
+       uint32_t RESERVED3;      /*!< Reserved 3,                                      Address offset:   0x5C */
+  __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
+  __IO uint32_t LOCKR;          /*!< EXTI Lock Register,                              Address offset:   0x70 */
+       uint32_t RESERVED4[3];   /*!< Reserved 4,                                                0x74 -- 0x7C */
+  __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
+  __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
+       uint32_t RESERVED5[2];   /*!< Reserved 5,                                                0x88 -- 0x8C */
+  __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
+  __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
+       uint32_t RESERVED6[2];   /*!< Reserved 6,                                                0x98 -- 0x9C */
+  __IO uint32_t IMR3;           /*!< EXTI Interrupt Mask Register 3,                  Address offset:   0xA0 */
+  __IO uint32_t EMR3;           /*!< EXTI Event Mask Register 3,                      Address offset:   0xA4 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t CREL;           /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+ __IO uint32_t ENDN;           /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+ __IO uint32_t RESERVED1;      /*!< Reserved,                                                                        0x008 */
+ __IO uint32_t DBTP;           /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+ __IO uint32_t TEST;           /*!< FDCAN Test register,                                             Address offset: 0x010 */
+ __IO uint32_t RWD;            /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+ __IO uint32_t CCCR;           /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+ __IO uint32_t NBTP;           /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+ __IO uint32_t TSCC;           /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+ __IO uint32_t TSCV;           /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+ __IO uint32_t TOCC;           /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+ __IO uint32_t TOCV;           /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+ __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                                0x030 - 0x03C */
+ __IO uint32_t ECR;            /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+ __IO uint32_t PSR;            /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+ __IO uint32_t TDCR;           /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+ __IO uint32_t RESERVED3;      /*!< Reserved,                                                                        0x04C */
+ __IO uint32_t IR;             /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+ __IO uint32_t IE;             /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+ __IO uint32_t ILS;            /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+ __IO uint32_t ILE;            /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+ __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                                0x060 - 0x07C */
+ __IO uint32_t GFC;            /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+ __IO uint32_t SIDFC;          /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+ __IO uint32_t XIDFC;          /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+ __IO uint32_t RESERVED5;      /*!< Reserved,                                                                        0x08C */
+ __IO uint32_t XIDAM;          /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+ __IO uint32_t HPMS;           /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+ __IO uint32_t NDAT1;          /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+ __IO uint32_t NDAT2;          /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+ __IO uint32_t RXF0C;          /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+ __IO uint32_t RXF0S;          /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+ __IO uint32_t RXF0A;          /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+ __IO uint32_t RXBC;           /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+ __IO uint32_t RXF1C;          /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+ __IO uint32_t RXF1S;          /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+ __IO uint32_t RXF1A;          /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+ __IO uint32_t RXESC;          /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+ __IO uint32_t TXBC;           /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+ __IO uint32_t TXFQS;          /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+ __IO uint32_t TXESC;          /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+ __IO uint32_t TXBRP;          /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+ __IO uint32_t TXBAR;          /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+ __IO uint32_t TXBCR;          /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+ __IO uint32_t TXBTO;          /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+ __IO uint32_t TXBCF;          /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+ __IO uint32_t TXBTIE;         /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+ __IO uint32_t TXBCIE;         /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+ __IO uint32_t RESERVED6[2];   /*!< Reserved,                                                                0x0E8 - 0x0EC */
+ __IO uint32_t TXEFC;          /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+ __IO uint32_t TXEFS;          /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+ __IO uint32_t TXEFA;          /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+ __IO uint32_t RESERVED7;      /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;         /*!< TT Trigger Memory Configuration register,        Address offset: 0x100 */
+  __IO uint32_t TTRMC;         /*!< TT Reference Message Configuration register,     Address offset: 0x104 */
+  __IO uint32_t TTOCF;         /*!< TT Operation Configuration register,             Address offset: 0x108 */
+  __IO uint32_t TTMLM;         /*!< TT Matrix Limits register,                       Address offset: 0x10C */
+  __IO uint32_t TURCF;         /*!< TUR Configuration register,                      Address offset: 0x110 */
+  __IO uint32_t TTOCN;         /*!< TT Operation Control register,                   Address offset: 0x114 */
+  __IO uint32_t TTGTP;         /*!< TT Global Time Preset register,                  Address offset: 0x118 */
+  __IO uint32_t TTTMK;         /*!< TT Time Mark register,                          Address offset: 0x11C */
+  __IO uint32_t TTIR;          /*!< TT Interrupt register,                           Address offset: 0x120 */
+  __IO uint32_t TTIE;          /*!< TT Interrupt Enable register,                    Address offset: 0x124 */
+  __IO uint32_t TTILS;         /*!< TT Interrupt Line Select register,               Address offset: 0x128 */
+  __IO uint32_t TTOST;         /*!< TT Operation Status register,                    Address offset: 0x12C */
+  __IO uint32_t TURNA;         /*!< TT TUR Numerator Actual register,                Address offset: 0x130 */
+  __IO uint32_t TTLGT;         /*!< TT Local and Global Time register,               Address offset: 0x134 */
+  __IO uint32_t TTCTC;         /*!< TT Cycle Time and Count register,                Address offset: 0x138 */
+  __IO uint32_t TTCPT;         /*!< TT Capture Time register,                        Address offset: 0x13C */
+  __IO uint32_t TTCSM;         /*!< TT Cycle Sync Mark register,                     Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111];/*!< Reserved,                                                0x144 - 0x2FC */
+  __IO uint32_t TTTS;          /*!< TT Trigger Select register,                      Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;          /*!< Clock Calibration Unit Core Release register,    Address offset: 0x00 */
+  __IO uint32_t CCFG;          /*!< Calibration Configuration register,              Address offset: 0x04 */
+  __IO uint32_t CSTAT;         /*!< Calibration Status register,                     Address offset: 0x08 */
+  __IO uint32_t CWD;           /*!< Calibration Watchdog register,                   Address offset: 0x0C */
+  __IO uint32_t IR;            /*!< CCU Interrupt register,                          Address offset: 0x10 */
+  __IO uint32_t IE;            /*!< CCU Interrupt Enable register,                   Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+/**
+ * @brief FD Controller Area Network Configuration
+ */
+typedef struct
+{
+ __IO uint32_t CKDIV;          /*!< FDCAN clock divider register,            Address offset: 0x100 + 0x000 */
+      uint32_t RESERVED1[128]; /*!< Reserved,                                0x100 + 0x004 - 0x100 + 0x200 */
+ __IO uint32_t OPTR;           /*!< FDCAN option register,                   Address offset: 0x100 + 0x204 */
+      uint32_t RESERVED2[58];  /*!< Reserved,                                0x100 + 0x208 - 0x100 + 0x2EC */
+ __IO uint32_t HWCFG;          /*!< FDCAN hardware configuration register,   Address offset: 0x100 + 0x2F0 */
+ __IO uint32_t VERR;           /*!< FDCAN IP version register,               Address offset: 0x100 + 0x2F4 */
+ __IO uint32_t IPIDR;          /*!< FDCAN IP ID register,                    Address offset: 0x100 + 0x2F8 */
+ __IO uint32_t SIDR;           /*!< FDCAN size ID register,                  Address offset: 0x100 + 0x2FC */
+} FDCAN_Config_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1
+  */
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+typedef struct
+{
+  __IO uint32_t SDCR[2];         /*!< SDRAM device 1/2 control register                      Address offset: 0x140-0x144 */
+  __IO uint32_t SDTR;            /*!< SDRAM timing register                                  Address offset: 0x148 */
+       uint32_t RESERVED0;       /*!< Reserved                                               Address offset: 0x14C */
+  __IO uint32_t SDCMR;           /*!< SDRAM command mode register                            Address offset: 0x150 */
+  __IO uint32_t SDRTR;           /*!< SDRAM refresh timer register                           Address offset: 0x154 */
+  __IO uint32_t SDSR;            /*!< SDRAM status register                                  Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+typedef struct
+{
+  __IO uint32_t PCR;             /*!< NAND Flash Programmable control register               Address offset: 0x080 */
+  __IO uint32_t SR;              /*!< FMC status register                                    Address offset: 0x084 */
+  __IO uint32_t PMEM;            /*!< Common memory space timing register                    Address offset: 0x088 */
+  __IO uint32_t PATT;            /*!< Attribute memory space timing registers                Address offset: 0x08C */
+  __IO uint32_t HPR;             /*!< FMC Hamming parity result registers                    Address offset: 0x090 */
+  __IO uint32_t HECCR;           /*!< FMC Hamming code ECC result register                   Address offset: 0x094 */
+       uint32_t RESERVED0[58];   /*!< Reserved                                               Address offset: 0x098-0x17C */
+  __IO uint32_t IER;             /*!< FMC NAND Interrupt Enable Register                     Address offset: 0x180 */
+  __IO uint32_t ISR;             /*!< FMC Controller Interrupt Status Register               Address offset: 0x184 */
+  __IO uint32_t ICR;             /*!< FMC NAND Controller Interrupt Clear Register           Address offset: 0x188 */
+       uint32_t RESERVED1[29];   /*!< Reserved                                               Address offset: 0x18C-0x1FC */
+  __IO uint32_t CSQCR;           /*!< FMC NAND Command Sequencer Control Register            Address offset: 0x200 */
+  __IO uint32_t CSQCFGR1;        /*!< FMC NAND Command Sequencer Configuration Register 1    Address offset: 0x204 */
+  __IO uint32_t CSQCFGR2;        /*!< FMC NAND Command Sequencer Configuration Register 2    Address offset: 0x208 */
+  __IO uint32_t CSQCFGR3;        /*!< FMC NAND sequencer configuration register 3            Address offset: 0x20C */
+  __IO uint32_t CSQAR1;          /*!< FMC NAND Command Sequencer Address Register 1          Address offset: 0x210 */
+  __IO uint32_t CSQAR2;          /*!< FMC NAND Command Sequencer Address Register 2          Address offset: 0x214 */
+       uint32_t RESERVED2[2];    /*!< Reserved                                               Address offset: 0x218-0x21C */
+  __IO uint32_t CSQIER;          /*!< FMC NAND Command Sequencer Interrupt Enable Register   Address offset: 0x220 */
+  __IO uint32_t CSQISR;          /*!< FMC NAND Command Sequencer Interrupt Status Register   Address offset: 0x224 */
+  __IO uint32_t CSQICR;          /*!< FMC NAND Command Sequencer Interrupt Clear Register    Address offset: 0x228 */
+       uint32_t RESERVED3;       /*!< Reserved                                               Address offset: 0x22C */
+  __IO uint32_t CSQEMSR;         /*!< FMC Command Sequencer Error Mapping Status register    Address offset: 0x230 */
+       uint32_t RESERVED4[7];    /*!< Reserved                                               Address offset: 0x234-0x24C */
+  __IO uint32_t BCHIER;          /*!< FMC BCH Interrupt enable register                      Address offset: 0x250 */
+  __IO uint32_t BCHISR;          /*!< FMC BCH Interrupt and Status Register                  Address offset: 0x254 */
+  __IO uint32_t BCHICR;          /*!< FMC BCH Interrupt Clear Register                       Address offset: 0x258 */
+       uint32_t RESERVED5;       /*!< Reserved                                               Address offset: 0x25C */
+  __IO uint32_t BCHPBR1;         /*!< FMC BCH Parity Bits Register 1                         Address offset: 0x260 */
+  __IO uint32_t BCHPBR2;         /*!< FMC BCH Parity Bits Register 2                         Address offset: 0x264 */
+  __IO uint32_t BCHPBR3;         /*!< FMC BCH Parity Bits Register 3                         Address offset: 0x268 */
+  __IO uint32_t BCHPBR4;         /*!< FMC BCH Parity Bits Register 4                         Address offset: 0x26C */
+       uint32_t RESERVED6[3];    /*!< Reserved                                               Address offset: 0x270-0x278 */
+  __IO uint32_t BCHDSR0;         /*!< FMC BCH Decoder Status register 0                      Address offset: 0x27C */
+  __IO uint32_t BCHDSR1;         /*!< FMC BCH Decoder Status register for bank 1             Address offset: 0x280 */
+  __IO uint32_t BCHDSR2;         /*!< FMC BCH Decoder Status register for bank 2             Address offset: 0x284 */
+  __IO uint32_t BCHDSR3;         /*!< FMC BCH Decoder Status register for bank 3             Address offset: 0x288 */
+  __IO uint32_t BCHDSR4;         /*!< FMC BCH Decoder Status register for bank 4             Address offset: 0x28C */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Common
+  */
+typedef struct{
+  __IO uint32_t CFGR;            /*!< FMC common configuration register                      Address offset: 0x020 */
+} FMC_Common_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+typedef struct
+{
+  __IO uint32_t MODER;         /*!< GPIO port mode register,                     Address offset: 0x00      */
+  __IO uint32_t OTYPER;        /*!< GPIO port output type register,              Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;       /*!< GPIO port output speed register,             Address offset: 0x08      */
+  __IO uint32_t PUPDR;         /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
+  __IO uint32_t IDR;           /*!< GPIO port input data register,               Address offset: 0x10      */
+  __IO uint32_t ODR;           /*!< GPIO port output data register,              Address offset: 0x14      */
+  __IO uint32_t BSRR;          /*!< GPIO port bit set/reset  register,           Address offset: 0x18      */
+  __IO uint32_t LCKR;          /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
+  __IO uint32_t AFR[2];        /*!< GPIO alternate function registers,           Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;           /*!< GPIO bit reset register,                     Address offset: 0x28      */
+       uint32_t RESERVED0;     /*!< Reserved,                                    Address offset: 0x2C      */
+  __IO uint32_t SECCFGR;       /*!< GPIO port secure configuration register,     Address offset: 0x30      */
+  __IO uint32_t PRIVCFGR;      /*!< GPIO port privileged configuration register, Address offset: 0x34      */
+  __IO uint32_t RCFGLOCKR;     /*!< GPIO port resource configuration register,   Address offset: 0x38      */
+       uint32_t RESERVED1;     /*!< Reserved,                                    Address offset: 0x3C      */
+  __IO uint32_t DELAYR[2];     /*!< GPIO port delay register,                    Address offset: 0x40-0x44 */
+  __IO uint32_t ADVCFGR[2];    /*!< GPIO port advanced configuration register,   Address offset: 0x48-0x4C */
+} GPIO_TypeDef;
+
+/**
+  * @brief GFXMMU
+  */
+typedef struct
+{
+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
+       uint32_t RESERVED0;       /*!< Reserved0,                                         Address offset: 0x0C */
+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
+  __IO uint32_t DAR;             /*!< GFXMMU default alpha register,                     Address offset: 0x14 */
+       uint32_t RESERVED1[2];    /*!< Reserved1,                                 Address offset: 0x18 to 0x1C */
+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                 Address offset: 0x30 to 0xFFC */
+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                      Address offset: 0x1000 to 0x2FFC
+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
+} GFXMMU_TypeDef;
+
+/**
+  * @brief GFXTIM
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< GFXTIM configuration register,                    Address offset: 0x00 */
+  __IO uint32_t CGCR;          /*!< GFXTIM clock generator configuration register,    Address offset: 0x04 */
+  __IO uint32_t TCR;           /*!< GFXTIM timers configuration register,             Address offset: 0x08 */
+  __IO uint32_t TDR;           /*!< GFXTIM timers disable register,                   Address offset: 0x0C */
+  __IO uint32_t EVCR;          /*!< GFXTIM events control register,                   Address offset: 0x10 */
+  __IO uint32_t EVSR;          /*!< GFXTIM events selection register,                 Address offset: 0x14 */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                         Address offset: 0x18-0x1C */
+  __IO uint32_t WDGTCR;        /*!< GFXTIM watchdog timer configuration register,     Address offset: 0x20 */
+  uint32_t RESERVED2[3];       /*!< Reserved,                                         Address offset: 0x24-0x2C */
+  __IO uint32_t ISR;           /*!< GFXTIM interrupt status register,                 Address offset: 0x30 */
+  __IO uint32_t ICR;           /*!< GFXTIM interrupt clear register,                  Address offset: 0x34 */
+  __IO uint32_t IER;           /*!< GFXTIM interrupt enable register,                 Address offset: 0x38 */
+  __IO uint32_t TSR;           /*!< GFXTIM timers status register,                    Address offset: 0x3C */
+  __IO uint32_t LCCRR;         /*!< GFXTIM line clock counter reload register,        Address offset: 0x40 */
+  __IO uint32_t FCCRR;         /*!< GFXTIM frame clock counter reload register,       Address offset: 0x44 */
+  uint32_t RESERVED3[2];       /*!< Reserved,                                         Address offset: 0x48-0x4C */
+  __IO uint32_t ATR;           /*!< GFXTIM absolute time register,                    Address offset: 0x50 */
+  __IO uint32_t AFCR;          /*!< GFXTIM absolute frame counter register,           Address offset: 0x54 */
+  __IO uint32_t ALCR;          /*!< GFXTIM absolute line counter register,            Address offset: 0x58 */
+  uint32_t RESERVED4[1];       /*!< Reserved,                                         Address offset: 0x5C */
+  __IO uint32_t AFCC1R;        /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
+  uint32_t RESERVED5[3];       /*!< Reserved,                                         Address offset: 0x64-0X6C */
+  __IO uint32_t ALCC1R;        /*!< GFXTIM absolute line counter compare 1 register,  Address offset: 0x70 */
+  __IO uint32_t ALCC2R;        /*!< GFXTIM absolute line counter compare 2 register,  Address offset: 0x74 */
+  uint32_t RESERVED6[2];       /*!< Reserved,                                         Address offset: 0x78-0X7C */
+  __IO uint32_t RFC1R;         /*!< GFXTIM relative frame counter 1 register,         Address offset: 0x80 */
+  __IO uint32_t RFC1RR;        /*!< GFXTIM relative frame counter 1 reload register,  Address offset: 0x84 */
+  __IO uint32_t RFC2R;         /*!< GFXTIM relative frame counter 2 register,         Address offset: 0x88 */
+  __IO uint32_t RFC2RR;        /*!< GFXTIM relative frame counter 2 reload register,  Address offset: 0x8C */
+  uint32_t RESERVED7[4];       /*!< Reserved,                                         Address offset: 0x90-0X9C */
+  __IO uint32_t WDGCR;         /*!< GFXTIM watchdog counter register,                 Address offset: 0xA0 */
+  __IO uint32_t WDGRR;         /*!< GFXTIM watchdog reload register,                  Address offset: 0xA4 */
+  __IO uint32_t WDGPAR;        /*!< GFXTIM watchdog pre-alarm register,               Address offset: 0xA8 */
+  uint32_t RESERVED8[209];     /*!< Reserved,                                         Address offset: 0xAC-0X3EC */
+  __IO uint32_t HWCFGR;        /*!< GFXTIM HW configuration register,                 Address offset: 0x3F0 */
+  __IO uint32_t VERR;          /*!< GFXTIM version register,                          Address offset: 0x3F4 */
+  __IO uint32_t IPIDR;         /*!< GFXTIM identification register,                   Address offset: 0x3F8 */
+  __IO uint32_t SIDR;          /*!< GFXTIM size identification register,              Address offset: 0x3FC */
+} GFXTIM_TypeDef;
+
+/**
+  * @brief HASH
+  */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
+} HASH_TypeDef;
+
+/**
+  * @brief HASH_DIGEST
+  */
+typedef struct
+{
+  __IO uint32_t HR[16];           /*!< HASH digest registers,          Address offset: 0x310-0x34C */
+} HASH_DIGEST_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Improved Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
+  uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
+  __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
+  __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
+  __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
+  __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
+  __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
+  __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
+  __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
+  uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
+  __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
+  uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
+  __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
+  __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
+  __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
+  uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
+  __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
+  __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
+  uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
+  __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
+  __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
+  uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
+  __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
+  __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
+  __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
+  uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
+  __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
+  __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
+  __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
+  __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
+  __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
+  __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
+} I3C_TypeDef;
+
+/**
+  * @brief Illegal Access Controller
+  */
+typedef struct
+{
+  __IO uint32_t IER[5];         /*!< Interrupt Enable register,                 Address offset: 0x000       */
+  uint32_t      RESERVED1[27];  /*!< Reserved,                                  Address offset: 0x014-0x07C */
+  __IO uint32_t ISR[5];         /*!< Interrupt Status register,                 Address offset: 0x080       */
+  uint32_t      RESERVED2[27];  /*!< Reserved,                                  Address offset: 0x094-0x0FC */
+  __IO uint32_t ICR[5];         /*!< Interrupt Clear register,                  Address offset: 0x100       */
+} IAC_TypeDef;
+
+/**
+  * @brief Instruction Cache
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
+  __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
+  __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
+  __IO uint32_t FCR;            /*!< ICACHE flag clear register,             Address offset: 0x0C */
+  __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
+  __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
+} ICACHE_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t KR;              /*!< IWDG key register                    Address offset: 0x000 */
+  __IO uint32_t PR;              /*!< IWDG prescaler register              Address offset: 0x004 */
+  __IO uint32_t RLR;             /*!< IWDG reload register                 Address offset: 0x008 */
+  __IO uint32_t SR;              /*!< IWDG status register                 Address offset: 0x00C */
+  __IO uint32_t WINR;            /*!< IWDG window register                 Address offset: 0x010 */
+  __IO uint32_t EWCR;            /*!< IWDG early wakeup interrupt register Address offset: 0x014 */
+  __IO uint32_t ICR;             /*!< IWDG interrupt clear register        Address offset: 0x018 */
+} IWDG_TypeDef;
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+
+/**
+  * @brief LCD-TFT Display Controller (LTDC)
+  */
+typedef struct
+{
+       uint32_t RESERVED0[2];   /*!< Reserved Address offset: 0x00-0x04 */
+  __IO uint32_t SSCR;           /*!< LTDC synchronization size configuration register Address offset: 0x8 */
+  __IO uint32_t BPCR;           /*!< LTDC back porch configuration register Address offset: 0xc */
+  __IO uint32_t AWCR;           /*!< LTDC active width configuration register Address offset: 0x10 */
+  __IO uint32_t TWCR;           /*!< LTDC total width configuration register Address offset: 0x14 */
+  __IO uint32_t GCR;            /*!< LTDC global control register Address offset: 0x18 */
+       uint32_t RESERVED1[2];   /*!< Reserved Address offset: */
+  __IO uint32_t SRCR;           /*!< LTDC shadow reload configuration register Address offset: 0x24 */
+  __IO uint32_t GCCR;           /*!< LTDC gamma correction configuration register Address offset: 0x28 */
+  __IO uint32_t BCCR;           /*!< LTDC background color configuration register Address offset: 0x2c */
+       uint32_t RESERVED2;      /*!< Reserved Address offset: 0x30 */
+  __IO uint32_t IER;            /*!< LTDC interrupt enable register Address offset: 0x34 */
+  __IO uint32_t ISR;            /*!< LTDC interrupt status register Address offset: 0x38 */
+  __IO uint32_t ICR;            /*!< LTDC Interrupt Clear Register Address offset: 0x3c */
+  __IO uint32_t LIPCR;          /*!< LTDC line interrupt position configuration register Address offset: 0x40 */
+  __IO uint32_t CPSR;           /*!< LTDC current position status register Address offset: 0x44 */
+  __IO uint32_t CDSR;           /*!< LTDC current display status register Address offset: 0x48 */
+       uint32_t RESERVED3[5];   /*!< Reserved Address offset: 0x4c */
+  __IO uint32_t EDCR;           /*!< LTDC external display control register Address offset: 0x60 */
+  __IO uint32_t IER2;           /*!< LTDC interrupt enable register 2 Address offset: 0x64 */
+  __IO uint32_t ISR2;           /*!< LTDC interrupt status register 2 Address offset: 0x68 */
+  __IO uint32_t ICR2;           /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */
+  __IO uint32_t LIPCR2;         /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */
+       uint32_t RESERVED4;      /*!< Reserved Address offset: 0x74 */
+  __IO uint32_t ECRCR;          /*!< LTDC expected CRC register Address offset: 0x78 */
+  __IO uint32_t CCRCR;          /*!< LTDC computed CRC register Address offset: 0x7c */
+  __IO uint32_t RB0AR;          /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */
+  __IO uint32_t RB1AR;          /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */
+  __IO uint32_t RBPR;           /*!< LTDC rotation buffer pitch register Address offset: 0x88 */
+  __IO uint32_t RIFCR;          /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */
+  __IO uint32_t FUTR;           /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller (LTDC)
+  */
+typedef struct
+{
+  __IO uint32_t C0R;          /*!< LTDC layer x configuration 0 register Address offset: 0x100 */
+  __IO uint32_t C1R;          /*!< LTDC layer x configuration 1 register Address offset: 0x104 */
+  __IO uint32_t RCR;          /*!< LTDC layer x reload control register Address offset: 0x108 */
+  __IO uint32_t CR;           /*!< LTDC layer x control register Address offset: 0x10c */
+  __IO uint32_t WHPCR;        /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */
+  __IO uint32_t WVPCR;        /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */
+  __IO uint32_t CKCR;         /*!< LTDC layer x color keying configuration register Address offset: 0x118 */
+  __IO uint32_t PFCR;         /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */
+  __IO uint32_t CACR;         /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */
+  __IO uint32_t DCCR;         /*!< LTDC layer x default color configuration register Address offset: 0x124 */
+  __IO uint32_t BFCR;         /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */
+  __IO uint32_t BLCR;         /*!< LTDC layer x burst length configuration register Address offset: 0x12c */
+  __IO uint32_t PCR;          /*!< LTDC layer x planar configuration register Address offset: 0x130 */
+  __IO uint32_t CFBAR;        /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */
+  __IO uint32_t CFBLR;        /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */
+  __IO uint32_t CFBLNR;       /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */
+  __IO uint32_t AFBA0R;       /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */
+  __IO uint32_t AFBA1R;       /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */
+  __IO uint32_t AFBLR;        /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */
+  __IO uint32_t AFBLNR;       /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */
+  __IO uint32_t CLUTWR;       /*!< LTDC layer x CLUT write register Address offset: 0x150 */
+  __IO uint32_t SISR;         /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */
+  __IO uint32_t SOSR;         /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */
+  __IO uint32_t SVSFR;        /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */
+  __IO uint32_t SVSPR;        /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */
+  __IO uint32_t SHSFR;        /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */
+  __IO uint32_t SHSPR;        /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */
+  __IO uint32_t CYR0R;        /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */
+  __IO uint32_t CYR1R;        /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */
+  __IO uint32_t FPF0R;        /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */
+  __IO uint32_t FPF1R;        /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */
+} LTDC_Layer_TypeDef;
+
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
+  __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
+  __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
+  __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
+  __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
+  __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
+  __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
+  __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
+  __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x20 */
+  __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
+  __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
+  __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
+  __IO uint32_t RESERVED2;      /*!< Reserved,                               Address offset: 0x30 */
+  __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
+} LPTIM_TypeDef;
+
+
+
+/**
+  * @brief ADF
+  */
+typedef struct
+{
+  __IO uint32_t GCR;            /*!< MDF Global Control register,             Address offset: 0x00  */
+  __IO uint32_t CKGCR;          /*!< MDF Clock Generator Control Register,    Address offset: 0x04  */
+  uint32_t      RESERVED1[6];   /*!< Reserved, 0x08-0x1C                                            */
+  __IO uint32_t OR;             /*!< MDF  Option Register,                    Address offset: 0x20  */
+} MDF_TypeDef;
+
+/**
+  * @brief ADF filter
+  */
+typedef struct
+{
+ __IO uint32_t SITFCR;         /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
+ __IO uint32_t BSMXCR;         /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
+ __IO uint32_t DFLTCR;         /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
+ __IO uint32_t DFLTCICR;       /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
+ __IO uint32_t DFLTRSFR;       /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
+ __IO uint32_t DFLTINTR;       /*!< MDF Integrator Configuration Register,          Address offset: 0x94 */
+ __IO uint32_t OLDCR;          /*!< MDF Out-Of Limit Detector Control Register,     Address offset: 0x98 */
+ __IO uint32_t OLDTHLR;        /*!< MDF OLD Threshold Low Register,                 Address offset: 0x9C */
+ __IO uint32_t OLDTHHR;        /*!< MDF OLD Threshold High Register,                Address offset: 0xA0 */
+ __IO uint32_t DLYCR;          /*!< MDF Delay control Register,                     Address offset: 0xA4 */
+ __IO uint32_t SCDCR;          /*!< MDF short circuit detector control Register,    Address offset: 0xA8 */
+ __IO uint32_t DFLTIER;        /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
+ __IO uint32_t DFLTISR;        /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
+ __IO uint32_t OECCR;          /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
+ __IO uint32_t SADCR;          /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
+ __IO uint32_t SADCFGR;        /*!< MDF SAD configuration register,                 Address offset: 0xBC */
+ __IO uint32_t SADSDLVR;       /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
+ __IO uint32_t SADANLVR;       /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
+ uint32_t     RESERVED1[9];    /*!< Reserved, 0xC8-0xE8                                                  */
+ __IO uint32_t SNPSDR;         /*!< MDF Snapshot Data Register,                     Address offset: 0xEC */
+ __IO uint32_t DFLTDR;         /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
+} MDF_Filter_TypeDef;
+
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+/**
+  * @brief PSSI
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< PSSI control register,                 Address offset: 0x000 */
+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
+} PSSI_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+typedef struct
+{
+  __IO uint32_t CR1;             /*!< PWR Control register 1                           Address offset: 0x000 */
+  __IO uint32_t CR2;             /*!< PWR Control Register 2                           Address offset: 0x004 */
+  __IO uint32_t CR3;             /*!< PWR Control Register 3                           Address offset: 0x008 */
+  __IO uint32_t CR4;             /*!< PWR Control Register 4                           Address offset: 0x00C */
+       uint32_t RESERVED0[4];    /*!< Reserved                                         Address offset: 0x010-0x01C */
+  __IO uint32_t VOSCR;           /*!< PWR Voltage scaling control register             Address offset: 0x020 */
+  __IO uint32_t BDCR1;           /*!< PWR Backup domain control register 1             Address offset: 0x024 */
+  __IO uint32_t BDCR2;           /*!< PWR Backup domain control register 2             Address offset: 0x028 */
+  __IO uint32_t DBPCR;           /*!< PWR Disable backup protection control register   Address offset: 0x02C */
+  __IO uint32_t CPUCR;           /*!< PWR CPU control register                         Address offset: 0x030 */
+  __IO uint32_t SVMCR1;          /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */
+  __IO uint32_t SVMCR2;          /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */
+  __IO uint32_t SVMCR3;          /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */
+       uint32_t RESERVED1[4];    /*!< Reserved                                         Address offset: 0x040-0x04C */
+  __IO uint32_t WKUPCR;          /*!< PWR Wakeup control register 1                    Address offset: 0x050 */
+  __IO uint32_t WKUPSR;          /*!< PWR Wakeup control register 2                    Address offset: 0x054 */
+  __IO uint32_t WKUPEPR;         /*!< PWR Wakeup control register 3                    Address offset: 0x058 */
+       uint32_t RESERVED2[5];    /*!< Reserved                                         Address offset: 0x05C-0x06C */
+  __IO uint32_t SECCFGR;         /*!< PWR Security configuration register              Address offset: 0x070 */
+  __IO uint32_t PRIVCFGR;        /*!< PWR Privilege configuration register             Address offset: 0x074 */
+} PWR_TypeDef;
+
+/**
+  * @brief PKA
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< PKA control register,             Address offset: 0x00 */
+  __IO uint32_t SR;            /*!< PKA status register,              Address offset: 0x04 */
+  __IO uint32_t CLRFR;         /*!< PKA clear flag register,          Address offset: 0x08 */
+  uint32_t Reserved[253];      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
+  __IO uint32_t RAM[1334];     /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
+} PKA_TypeDef;
+
+/**
+  * @brief RAMs configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control Register,                    Address offset: 0x00 */
+  __IO uint32_t IER;         /*!< Interrupt Enable Register,           Address offset: 0x04 */
+  __IO uint32_t ISR;         /*!< Interrupt Status Register,           Address offset: 0x08 */
+  __IO uint32_t ESEAR;       /*!< ECC Single Error Address Register,   Address offset: 0x0C */
+  __IO uint32_t EDEAR;       /*!< ECC Double Error Address Register,   Address offset: 0x10 */
+  __IO uint32_t ICR;         /*!< Interrupt Clear Register,            Address offset: 0x14 */
+  uint32_t      RESERVED[3]; /*!< Reserved,                       Address offset: 0x18-0x20 */
+  __IO uint32_t ECCKEYR;     /*!< RAM ECC Key Register,                Address offset: 0x24 */
+  __IO uint32_t ERKEYR;      /*!< RAM Erase Key Register,              Address offset: 0x28 */
+}RAMCFG_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< RCC control register                                           Address offset: 0x0000 */
+  __IO uint32_t SR;               /*!< RCC status register                                            Address offset: 0x0004 */
+  __IO uint32_t STOPCR;           /*!< RCC Stop mode control register                                 Address offset: 0x0008 */
+       uint32_t RESERVED0[5];     /*!< Reserved                                                       Address offset: 0x000C-0x001C */
+  __IO uint32_t CFGR1;            /*!< RCC configuration register 1                                   Address offset: 0x0020 */
+  __IO uint32_t CFGR2;            /*!< RCC configuration register 2                                   Address offset: 0x0024 */
+       uint32_t RESERVED1;        /*!< Reserved                                                       Address offset: 0x0028 */
+  __IO uint32_t BDCR;             /*!< RCC backup domain protection register                          Address offset: 0x002C */
+  __IO uint32_t HWRSR;            /*!< RCC reset status register for hardware                         Address offset: 0x0030 */
+  __IO uint32_t RSR;              /*!< RCC reset register                                             Address offset: 0x0034 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                                       Address offset: 0x0038-0x003C */
+  __IO uint32_t LSECFGR;          /*!< RCC LSE configuration register                                 Address offset: 0x0040 */
+  __IO uint32_t MSICFGR;          /*!< RCC MSI configuration register                                 Address offset: 0x0044 */
+  __IO uint32_t HSICFGR;          /*!< RCC HSI configuration register                                 Address offset: 0x0048 */
+  __IO uint32_t HSIMCR;           /*!< RCC HSI Monitor control register                               Address offset: 0x004C */
+  __IO uint32_t HSIMSR;           /*!< RCC HSI Monitor status register                                Address offset: 0x0050 */
+  __IO uint32_t HSECFGR;          /*!< RCC HSE configuration register                                 Address offset: 0x0054 */
+       uint32_t RESERVED3[10];    /*!< Reserved                                                       Address offset: 0x0058-0x007C */
+  __IO uint32_t PLL1CFGR1;        /*!< RCC PLL1 configuration register 1                              Address offset: 0x0080 */
+  __IO uint32_t PLL1CFGR2;        /*!< RCC PLL1 configuration register 2                              Address offset: 0x0084 */
+  __IO uint32_t PLL1CFGR3;        /*!< RCC PLL1 configuration register 3                              Address offset: 0x0088 */
+       uint32_t RESERVED4;        /*!< Reserved                                                       Address offset: 0x008C */
+  __IO uint32_t PLL2CFGR1;        /*!< RCC PLL2 configuration register 1                              Address offset: 0x0090 */
+  __IO uint32_t PLL2CFGR2;        /*!< RCC PLL2 configuration register 2                              Address offset: 0x0094 */
+  __IO uint32_t PLL2CFGR3;        /*!< RCC PLL2 configuration register 3                              Address offset: 0x0098 */
+       uint32_t RESERVED5;        /*!< Reserved                                                       Address offset: 0x009C */
+  __IO uint32_t PLL3CFGR1;        /*!< RCC PLL3 configuration register 1                              Address offset: 0x00A0 */
+  __IO uint32_t PLL3CFGR2;        /*!< RCC PLL3 configuration register 2                              Address offset: 0x00A4 */
+  __IO uint32_t PLL3CFGR3;        /*!< RCC PLL3 configuration register 3                              Address offset: 0x00A8 */
+       uint32_t RESERVED6;        /*!< Reserved                                                       Address offset: 0x00AC */
+  __IO uint32_t PLL4CFGR1;        /*!< RCC PLL4 configuration register 1                              Address offset: 0x00B0 */
+  __IO uint32_t PLL4CFGR2;        /*!< RCC PLL4 configuration register 2                              Address offset: 0x00B4 */
+  __IO uint32_t PLL4CFGR3;        /*!< RCC PLL4 configuration register 3                              Address offset: 0x00B8 */
+       uint32_t RESERVED7[2];     /*!< Reserved                                                       Address offset: 0x00BC-0x00C0 */
+  __IO uint32_t IC1CFGR;          /*!< RCC IC1 configuration register                                 Address offset: 0x00C4 */
+  __IO uint32_t IC2CFGR;          /*!< RCC IC2 configuration register                                 Address offset: 0x00C8 */
+  __IO uint32_t IC3CFGR;          /*!< RCC IC3 configuration register                                 Address offset: 0x00CC */
+  __IO uint32_t IC4CFGR;          /*!< RCC IC4 configuration register                                 Address offset: 0x00D0 */
+  __IO uint32_t IC5CFGR;          /*!< RCC IC5 configuration register                                 Address offset: 0x00D4 */
+  __IO uint32_t IC6CFGR;          /*!< RCC IC6 configuration register                                 Address offset: 0x00D8 */
+  __IO uint32_t IC7CFGR;          /*!< RCC IC7 configuration register                                 Address offset: 0x00DC */
+  __IO uint32_t IC8CFGR;          /*!< RCC IC8 configuration register                                 Address offset: 0x00E0 */
+  __IO uint32_t IC9CFGR;          /*!< RCC IC9 configuration register                                 Address offset: 0x00E4 */
+  __IO uint32_t IC10CFGR;         /*!< RCC IC10 configuration register                                Address offset: 0x00E8 */
+  __IO uint32_t IC11CFGR;         /*!< RCC IC11 configuration register                                Address offset: 0x00EC */
+  __IO uint32_t IC12CFGR;         /*!< RCC IC12 configuration register                                Address offset: 0x00F0 */
+  __IO uint32_t IC13CFGR;         /*!< RCC IC13 configuration register                                Address offset: 0x00F4 */
+  __IO uint32_t IC14CFGR;         /*!< RCC IC14 configuration register                                Address offset: 0x00F8 */
+  __IO uint32_t IC15CFGR;         /*!< RCC IC15 configuration register                                Address offset: 0x00FC */
+  __IO uint32_t IC16CFGR;         /*!< RCC IC16 configuration register                                Address offset: 0x0100 */
+  __IO uint32_t IC17CFGR;         /*!< RCC IC17 configuration register                                Address offset: 0x0104 */
+  __IO uint32_t IC18CFGR;         /*!< RCC IC18 configuration register                                Address offset: 0x0108 */
+  __IO uint32_t IC19CFGR;         /*!< RCC IC19 configuration register                                Address offset: 0x010C */
+  __IO uint32_t IC20CFGR;         /*!< RCC IC20 configuration register                                Address offset: 0x0110 */
+       uint32_t RESERVED8[4];     /*!< Reserved                                                       Address offset: 0x0114-0x0120 */
+  __IO uint32_t CIER;             /*!< RCC clock-source interrupt enable register                     Address offset: 0x0124 */
+  __IO uint32_t CIFR;             /*!< RCC clock-source interrupt flag register                       Address offset: 0x0128 */
+  __IO uint32_t CICR;             /*!< RCC clock-source interrupt clear register                      Address offset: 0x012C */
+       uint32_t RESERVED9[5];     /*!< Reserved                                                       Address offset: 0x0130-0x0140 */
+  __IO uint32_t CCIPR1;           /*!< RCC clock configuration for independent peripheral register 1  Address offset: 0x0144 */
+  __IO uint32_t CCIPR2;           /*!< RCC clock configuration for independent peripheral register 2  Address offset: 0x0148 */
+  __IO uint32_t CCIPR3;           /*!< RCC clock configuration for independent peripheral register 3  Address offset: 0x014C */
+  __IO uint32_t CCIPR4;           /*!< RCC clock configuration for independent peripheral register 4  Address offset: 0x0150 */
+  __IO uint32_t CCIPR5;           /*!< RCC clock configuration for independent peripheral register 5  Address offset: 0x0154 */
+  __IO uint32_t CCIPR6;           /*!< RCC clock configuration for independent peripheral register 6  Address offset: 0x0158 */
+  __IO uint32_t CCIPR7;           /*!< RCC clock configuration for independent peripheral register 7  Address offset: 0x015C */
+  __IO uint32_t CCIPR8;           /*!< RCC clock configuration for independent peripheral register 8  Address offset: 0x0160 */
+  __IO uint32_t CCIPR9;           /*!< RCC clock configuration for independent peripheral register 9  Address offset: 0x0164 */
+       uint32_t RESERVED10[2];    /*!< Reserved                                                       Address offset: 0x0168-0x016C */
+  __IO uint32_t CCIPR12;          /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */
+  __IO uint32_t CCIPR13;          /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */
+  __IO uint32_t CCIPR14;          /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */
+       uint32_t RESERVED11[35];   /*!< Reserved                                                       Address offset: 0x017C-0x0204 */
+  __IO uint32_t MISCRSTR;         /*!< RCC miscellaneous configurations reset register                Address offset: 0x0208 */
+  __IO uint32_t MEMRSTR;          /*!< RCC embedded memories reset register                           Address offset: 0x020C */
+  __IO uint32_t AHB1RSTR;         /*!< RCC AHB1 reset register                                        Address offset: 0x0210 */
+  __IO uint32_t AHB2RSTR;         /*!< RCC AHB2 reset register                                        Address offset: 0x0214 */
+  __IO uint32_t AHB3RSTR;         /*!< RCC AHB3 reset register                                        Address offset: 0x0218 */
+  __IO uint32_t AHB4RSTR;         /*!< RCC AHB4 reset register                                        Address offset: 0x021C */
+  __IO uint32_t AHB5RSTR;         /*!< RCC AHB5 reset register                                        Address offset: 0x0220 */
+  __IO uint32_t APB1RSTR1;        /*!< RCC APB1 reset register 1                                      Address offset: 0x0224 */
+  __IO uint32_t APB1RSTR2;        /*!< RCC APB1 reset register 2                                      Address offset: 0x0228 */
+  __IO uint32_t APB2RSTR;         /*!< RCC APB2 reset register                                        Address offset: 0x022C */
+       uint32_t RESERVED12;       /*!< Reserved                                                       Address offset: 0x0230 */
+  __IO uint32_t APB4RSTR1;        /*!< RCC APB4 reset register 1                                      Address offset: 0x0234 */
+  __IO uint32_t APB4RSTR2;        /*!< RCC APB4 reset register 2                                      Address offset: 0x0238 */
+  __IO uint32_t APB5RSTR;         /*!< RCC APB5 reset register                                        Address offset: 0x023C */
+  __IO uint32_t DIVENR;           /*!< RCC IC dividers enable register                                Address offset: 0x0240 */
+  __IO uint32_t BUSENR;           /*!< RCC embedded buses enable register                             Address offset: 0x0244 */
+  __IO uint32_t MISCENR;          /*!< RCC miscellaneous configurations enable register               Address offset: 0x0248 */
+  __IO uint32_t MEMENR;           /*!< RCC embedded memories enable register                          Address offset: 0x024C */
+  __IO uint32_t AHB1ENR;          /*!< RCC AHB1 enable register                                       Address offset: 0x0250 */
+  __IO uint32_t AHB2ENR;          /*!< RCC AHB2 enable register                                       Address offset: 0x0254 */
+  __IO uint32_t AHB3ENR;          /*!< RCC AHB3 enable register                                       Address offset: 0x0258 */
+  __IO uint32_t AHB4ENR;          /*!< RCC AHB4 enable register                                       Address offset: 0x025C */
+  __IO uint32_t AHB5ENR;          /*!< RCC AHB5 enable register                                       Address offset: 0x0260 */
+  __IO uint32_t APB1ENR1;         /*!< RCC APB1 enable register 1                                     Address offset: 0x0264 */
+  __IO uint32_t APB1ENR2;         /*!< RCC APB1 enable register 2                                     Address offset: 0x0268 */
+  __IO uint32_t APB2ENR;          /*!< RCC APB2 enable register                                       Address offset: 0x026C */
+  __IO uint32_t APB3ENR;          /*!< RCC APB3 enable register                                       Address offset: 0x0270 */
+  __IO uint32_t APB4ENR1;         /*!< RCC APB4 enable register 1                                     Address offset: 0x0274 */
+  __IO uint32_t APB4ENR2;         /*!< RCC APB4 enable register 2                                     Address offset: 0x0278 */
+  __IO uint32_t APB5ENR;          /*!< RCC APB5 enable register                                       Address offset: 0x027C */
+       uint32_t RESERVED13;       /*!< Reserved                                                       Address offset: 0x0280 */
+  __IO uint32_t BUSLPENR;         /*!< RCC embedded buses sleep enable register                       Address offset: 0x0284 */
+  __IO uint32_t MISCLPENR;        /*!< RCC miscellaneous configurations sleep enable register         Address offset: 0x0288 */
+  __IO uint32_t MEMLPENR;         /*!< RCC embedded memories sleep enable register                    Address offset: 0x028C */
+  __IO uint32_t AHB1LPENR;        /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0290 */
+  __IO uint32_t AHB2LPENR;        /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0294 */
+  __IO uint32_t AHB3LPENR;        /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0298 */
+  __IO uint32_t AHB4LPENR;        /*!< RCC AHB4 sleep enable register                                 Address offset: 0x029C */
+  __IO uint32_t AHB5LPENR;        /*!< RCC AHB5 sleep enable register                                 Address offset: 0x02A0 */
+  __IO uint32_t APB1LPENR1;       /*!< RCC APB1 sleep enable register 1                               Address offset: 0x02A4 */
+  __IO uint32_t APB1LPENR2;       /*!< RCC APB1 sleep enable register 2                               Address offset: 0x02A8 */
+  __IO uint32_t APB2LPENR;        /*!< RCC APB2 sleep enable register                                 Address offset: 0x02AC */
+  __IO uint32_t APB3LPENR;        /*!< RCC APB3 sleep enable register                                 Address offset: 0x02B0 */
+  __IO uint32_t APB4LPENR1;       /*!< RCC APB4 sleep enable register 1                               Address offset: 0x02B4 */
+  __IO uint32_t APB4LPENR2;       /*!< RCC APB4 sleep enable register 2                               Address offset: 0x02B8 */
+  __IO uint32_t APB5LPENR;        /*!< RCC APB5 sleep enable register                                 Address offset: 0x02BC */
+       uint32_t RESERVED14[99];   /*!< Reserved                                                       Address offset: 0x02C0-0x0448 */
+  __IO uint32_t RDCR;             /*!< RCC reset duration control register                            Address offset: 0x044C */
+       uint32_t RESERVED15[204];  /*!< Reserved                                                       Address offset: 0x0450-0x077C */
+  __IO uint32_t SECCFGR0;         /*!< RCC oscillator secure configuration register 0                 Address offset: 0x0780 */
+  __IO uint32_t PRIVCFGR0;        /*!< RCC oscillator privilege configuration register 0              Address offset: 0x0784 */
+  __IO uint32_t LOCKCFGR0;        /*!< RCC oscillator lock configuration register 0                   Address offset: 0x0788 */
+  __IO uint32_t PUBCFGR0;         /*!< RCC oscillator public configuration register 0                 Address offset: 0x078C */
+  __IO uint32_t SECCFGR1;         /*!< RCC PLL secure configuration register 1                        Address offset: 0x0790 */
+  __IO uint32_t PRIVCFGR1;        /*!< RCC PLL privilege configuration register 1                     Address offset: 0x0794 */
+  __IO uint32_t LOCKCFGR1;        /*!< RCC PLL lock configuration register 1                          Address offset: 0x0798 */
+  __IO uint32_t PUBCFGR1;         /*!< RCC PLL public configuration register 1                        Address offset: 0x079C */
+  __IO uint32_t SECCFGR2;         /*!< RCC divider secure configuration register 2                    Address offset: 0x07A0 */
+  __IO uint32_t PRIVCFGR2;        /*!< RCC divider privilege configuration register 2                 Address offset: 0x07A4 */
+  __IO uint32_t LOCKCFGR2;        /*!< RCC divider lock configuration register 2                      Address offset: 0x07A8 */
+  __IO uint32_t PUBCFGR2;         /*!< RCC divider public configuration register 2                    Address offset: 0x07AC */
+  __IO uint32_t SECCFGR3;         /*!< RCC system secure configuration register 3                     Address offset: 0x07B0 */
+  __IO uint32_t PRIVCFGR3;        /*!< RCC system privilege configuration register 3                  Address offset: 0x07B4 */
+  __IO uint32_t LOCKCFGR3;        /*!< RCC system lock configuration register 3                       Address offset: 0x07B8 */
+  __IO uint32_t PUBCFGR3;         /*!< RCC system public configuration register 3                     Address offset: 0x07BC */
+  __IO uint32_t SECCFGR4;         /*!< RCC bus secure configuration register 4                        Address offset: 0x07C0 */
+  __IO uint32_t PRIVCFGR4;        /*!< RCC bus privilege configuration register 4                     Address offset: 0x07C4 */
+  __IO uint32_t LOCKCFGR4;        /*!< RCC bus lock configuration register 4                          Address offset: 0x07C8 */
+  __IO uint32_t PUBCFGR4;         /*!< RCC bus public configuration register 4                        Address offset: 0x07CC */
+  __IO uint32_t PUBCFGR5;         /*!< RCC bus public configuration register 4                        Address offset: 0x07D0 */
+       uint32_t RESERVED16[11];   /*!< Reserved                                                       Address offset: 0x07D4-0x07FC */
+  __IO uint32_t CSR;              /*!< RCC control Set register                                       Address offset: 0x0800 */
+       uint32_t RESERVED17;       /*!< Reserved                                                       Address offset: 0x0804 */
+  __IO uint32_t STOPCSR;          /*!< RCC STOPCSR configuration register                             Address offset: 0x0808 */
+       uint32_t RESERVED18[127];  /*!< Reserved                                                       Address offset: 0x080C-0x0A00 */
+  __IO uint32_t MISCRSTSR;        /*!< RCC miscellaneous reset register                               Address offset: 0x0A08 */
+  __IO uint32_t MEMRSTSR;         /*!< RCC memory reset register                                      Address offset: 0x0A0C */
+  __IO uint32_t AHB1RSTSR;        /*!< RCC AHB1 reset register                                        Address offset: 0x0A10 */
+  __IO uint32_t AHB2RSTSR;        /*!< RCC AHB2 reset register                                        Address offset: 0x0A14 */
+  __IO uint32_t AHB3RSTSR;        /*!< RCC AHB3 reset register                                        Address offset: 0x0A18 */
+  __IO uint32_t AHB4RSTSR;        /*!< RCC AHB4 reset register                                        Address offset: 0x0A1C */
+  __IO uint32_t AHB5RSTSR;        /*!< RCC AHB5 reset register                                        Address offset: 0x0A20 */
+  __IO uint32_t APB1RSTSR1;       /*!< RCC APB1 reset register 1                                      Address offset: 0x0A24 */
+  __IO uint32_t APB1RSTSR2;       /*!< RCC APB1 reset register 2                                      Address offset: 0x0A28 */
+  __IO uint32_t APB2RSTSR;        /*!< RCC APB2 reset register                                        Address offset: 0x0A2C */
+       uint32_t RESERVED19;       /*!< Reserved                                                       Address offset: 0x0A30 */
+  __IO uint32_t APB4RSTSR1;       /*!< RCC APB4 reset register 1                                      Address offset: 0x0A34 */
+  __IO uint32_t APB4RSTSR2;       /*!< RCC APB4 reset register 2                                      Address offset: 0x0A38 */
+  __IO uint32_t APB5RSTSR;        /*!< RCC APB5 reset register                                        Address offset: 0x0A3C */
+  __IO uint32_t DIVENSR;          /*!< RCC divider enable register                                    Address offset: 0x0A40 */
+  __IO uint32_t BUSENSR;          /*!< RCC bus enable register                                        Address offset: 0x0A44 */
+  __IO uint32_t MISCENSR;         /*!< RCC miscellaneous enable register                              Address offset: 0x0A48 */
+  __IO uint32_t MEMENSR;          /*!< RCC memory enable register                                     Address offset: 0x0A4C */
+  __IO uint32_t AHB1ENSR;         /*!< RCC AHB1 enable register                                       Address offset: 0x0A50 */
+  __IO uint32_t AHB2ENSR;         /*!< RCC AHB2 enable register                                       Address offset: 0x0A54 */
+  __IO uint32_t AHB3ENSR;         /*!< RCC AHB3 enable register                                       Address offset: 0x0A58 */
+  __IO uint32_t AHB4ENSR;         /*!< RCC AHB4 enable register                                       Address offset: 0x0A5C */
+  __IO uint32_t AHB5ENSR;         /*!< RCC AHB5 enable register                                       Address offset: 0x0A60 */
+  __IO uint32_t APB1ENSR1;        /*!< RCC APB1 enable register 1                                     Address offset: 0x0A64 */
+  __IO uint32_t APB1ENSR2;        /*!< RCC APB1 enable register 2                                     Address offset: 0x0A68 */
+  __IO uint32_t APB2ENSR;         /*!< RCC APB2 enable register                                       Address offset: 0x0A6C */
+  __IO uint32_t APB3ENSR;         /*!< RCC APB3 enable register                                       Address offset: 0x0A70 */
+  __IO uint32_t APB4ENSR1;        /*!< RCC APB4 enable register 1                                     Address offset: 0x0A74 */
+  __IO uint32_t APB4ENSR2;        /*!< RCC APB4 enable register 2                                     Address offset: 0x0A78 */
+  __IO uint32_t APB5ENSR;         /*!< RCC APB5 enable register                                       Address offset: 0x0A7C */
+       uint32_t RESERVED20;       /*!< Reserved                                                       Address offset: 0x0A80 */
+  __IO uint32_t BUSLPENSR;        /*!< RCC bus sleep enable register                                  Address offset: 0x0A84 */
+  __IO uint32_t MISCLPENSR;       /*!< RCC miscellaneous sleep enable register                        Address offset: 0x0A88 */
+  __IO uint32_t MEMLPENSR;        /*!< RCC memory sleep enable register                               Address offset: 0x0A8C */
+  __IO uint32_t AHB1LPENSR;       /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0A90 */
+  __IO uint32_t AHB2LPENSR;       /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0A94 */
+  __IO uint32_t AHB3LPENSR;       /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0A98 */
+  __IO uint32_t AHB4LPENSR;       /*!< RCC AHB4 sleep enable register                                 Address offset: 0x0A9C */
+  __IO uint32_t AHB5LPENSR;       /*!< RCC AHB5 sleep enable register                                 Address offset: 0x0AA0 */
+  __IO uint32_t APB1LPENSR1;      /*!< RCC APB1 sleep enable register 1                               Address offset: 0x0AA4 */
+  __IO uint32_t APB1LPENSR2;      /*!< RCC APB1 sleep enable register 2                               Address offset: 0x0AA8 */
+  __IO uint32_t APB2LPENSR;       /*!< RCC APB2 sleep enable register                                 Address offset: 0x0AAC */
+  __IO uint32_t APB3LPENSR;       /*!< RCC APB3 sleep enable register                                 Address offset: 0x0AB0 */
+  __IO uint32_t APB4LPENSR1;      /*!< RCC APB4 sleep enable register 1                               Address offset: 0x0AB4 */
+  __IO uint32_t APB4LPENSR2;      /*!< RCC APB4 sleep enable register 2                               Address offset: 0x0AB8 */
+  __IO uint32_t APB5LPENSR;       /*!< RCC APB5 sleep enable register                                 Address offset: 0x0ABC */
+       uint32_t RESERVED21[305];  /*!< Reserved                                                       Address offset: 0x0AC0-0x0F80 */
+  __IO uint32_t PRIVCFGSR0;       /*!< RCC oscillator privilege configuration set register 0          Address offset: 0x0F84 */
+       uint32_t RESERVED22;       /*!< Reserved                                                       Address offset: 0x0F88 */
+  __IO uint32_t PUBCFGSR0;        /*!< RCC oscillator public configuration set register 0             Address offset: 0x0F8C */
+       uint32_t RESERVED23;       /*!< Reserved                                                       Address offset: 0x0F90 */
+  __IO uint32_t PRIVCFGSR1;       /*!< RCC PLL privilege configuration set register 1                 Address offset: 0x0F94 */
+       uint32_t RESERVED24;       /*!< Reserved                                                       Address offset: 0x0F98 */
+  __IO uint32_t PUBCFGSR1;        /*!< RCC PLL public configuration set register 1                    Address offset: 0x0F9C */
+       uint32_t RESERVED25;       /*!< Reserved                                                       Address offset: 0x0FA0 */
+  __IO uint32_t PRIVCFGSR2;       /*!< RCC divider privilege configuration set register 2             Address offset: 0x0FA4 */
+       uint32_t RESERVED26;       /*!< Reserved                                                       Address offset: 0x0FA8 */
+  __IO uint32_t PUBCFGSR2;        /*!< RCC divider public configuration set register 2                Address offset: 0x0FAC */
+       uint32_t RESERVED27;       /*!< Reserved                                                       Address offset: 0x0FB0 */
+  __IO uint32_t PRIVCFGSR3;       /*!< RCC system privilege configuration set register 3              Address offset: 0x0FB4 */
+       uint32_t RESERVED28;       /*!< Reserved                                                       Address offset: 0x0FB8 */
+  __IO uint32_t PUBCFGSR3;        /*!< RCC system public configuration set register 3                 Address offset: 0x0FBC */
+       uint32_t RESERVED29;       /*!< Reserved                                                       Address offset: 0x0FC0 */
+  __IO uint32_t PRIVCFGSR4;       /*!< RCC privilege configuration set register 4                     Address offset: 0x0FC4 */
+       uint32_t RESERVED30;       /*!< Reserved                                                       Address offset: 0x0FC8 */
+  __IO uint32_t PUBCFGSR4;        /*!< RCC public configuration set register 4                            Address offset: 0x0FCC */
+  __IO uint32_t PUBCFGSR5;        /*!< RCC public configuration set register 5                            Address offset: 0x0FD0 */
+       uint32_t RESERVED31[11];   /*!< Reserved                                                       Address offset: 0x0FD4-0x0FFC */
+  __IO uint32_t CCR;              /*!< RCC control clear register                                     Address offset: 0x1000 */
+       uint32_t RESERVED32;       /*!< Reserved                                                       Address offset: 0x1004 */
+  __IO uint32_t STOPCCR;          /*!< RCC Stop mode configuration clear register                     Address offset: 0x1008 */
+       uint32_t RESERVED33[127];  /*!< Reserved                                                       Address offset: 0x100C-0x1200 */
+  __IO uint32_t MISCRSTCR;        /*!< RCC miscellaneous reset clear register                         Address offset: 0x1208 */
+  __IO uint32_t MEMRSTCR;         /*!< RCC memory reset clear register                                Address offset: 0x120C */
+  __IO uint32_t AHB1RSTCR;        /*!< RCC AHB1 reset clear register                                  Address offset: 0x1210 */
+  __IO uint32_t AHB2RSTCR;        /*!< RCC AHB2 reset clear register                                  Address offset: 0x1214 */
+  __IO uint32_t AHB3RSTCR;        /*!< RCC AHB3 reset r clear register                                Address offset: 0x1218 */
+  __IO uint32_t AHB4RSTCR;        /*!< RCC AHB4 reset clear register                                  Address offset: 0x121C */
+  __IO uint32_t AHB5RSTCR;        /*!< RCC AHB5 reset clear register                                  Address offset: 0x1220 */
+  __IO uint32_t APB1RSTCR1;       /*!< RCC APB1 reset clear register 1                                Address offset: 0x1224 */
+  __IO uint32_t APB1RSTCR2;       /*!< RCC APB1 reset clear register 2                                Address offset: 0x1228 */
+  __IO uint32_t APB2RSTCR;        /*!< RCC APB2 reset clear register                                  Address offset: 0x122C */
+       uint32_t RESERVED34;       /*!< Reserved                                                       Address offset: 0x1230 */
+  __IO uint32_t APB4RSTCR1;       /*!< RCC APB4 reset clear register 1                                Address offset: 0x1234 */
+  __IO uint32_t APB4RSTCR2;       /*!< RCC APB4 reset clear register 2                                Address offset: 0x1238 */
+  __IO uint32_t APB5RSTCR;        /*!< RCC APB5 reset clear register                                  Address offset: 0x123C */
+  __IO uint32_t DIVENCR;          /*!< RCC divider enable clear register                              Address offset: 0x1240 */
+  __IO uint32_t BUSENCR;          /*!< RCC bus enable clear register                                  Address offset: 0x1244 */
+  __IO uint32_t MISCENCR;         /*!< RCC miscellaneous enable clear register                        Address offset: 0x1248 */
+  __IO uint32_t MEMENCR;          /*!< RCC memory enable clear register                               Address offset: 0x124C */
+  __IO uint32_t AHB1ENCR;         /*!< RCC AHB1 enable clear register                                 Address offset: 0x1250 */
+  __IO uint32_t AHB2ENCR;         /*!< RCC AHB2 enable clear register                                 Address offset: 0x1254 */
+  __IO uint32_t AHB3ENCR;         /*!< RCC AHB3 enable clear register                                 Address offset: 0x1258 */
+  __IO uint32_t AHB4ENCR;         /*!< RCC AHB4 enable clear register                                 Address offset: 0x125C */
+  __IO uint32_t AHB5ENCR;         /*!< RCC AHB5 enable clear register                                 Address offset: 0x1260 */
+  __IO uint32_t APB1ENCR1;        /*!< RCC APB1 enable clear register 1                               Address offset: 0x1264 */
+  __IO uint32_t APB1ENCR2;        /*!< RCC APB1 enable clear register 2                               Address offset: 0x1268 */
+  __IO uint32_t APB2ENCR;         /*!< RCC APB2 enable clear register                                 Address offset: 0x126C */
+  __IO uint32_t APB3ENCR;         /*!< RCC APB3 enable clear register                                 Address offset: 0x1270 */
+  __IO uint32_t APB4ENCR1;        /*!< RCC APB4 enable clear register 1                               Address offset: 0x1274 */
+  __IO uint32_t APB4ENCR2;        /*!< RCC APB4 enable clear register 2                               Address offset: 0x1278 */
+  __IO uint32_t APB5ENCR;         /*!< RCC APB5 enable clear register                                 Address offset: 0x127C */
+       uint32_t RESERVED35;       /*!< Reserved                                                       Address offset: 0x1280 */
+  __IO uint32_t BUSLPENCR;        /*!< RCC bus sleep enable clear register                            Address offset: 0x1284 */
+  __IO uint32_t MISCLPENCR;       /*!< RCC miscellaneous sleep enable clear register                  Address offset: 0x1288 */
+  __IO uint32_t MEMLPENCR;        /*!< RCC memory sleep enable clear register                         Address offset: 0x128C */
+  __IO uint32_t AHB1LPENCR;       /*!< RCC AHB1 sleep enable clear register                           Address offset: 0x1290 */
+  __IO uint32_t AHB2LPENCR;       /*!< RCC AHB2 sleep enable clear register                           Address offset: 0x1294 */
+  __IO uint32_t AHB3LPENCR;       /*!< RCC AHB3 sleep enable clear register                           Address offset: 0x1298 */
+  __IO uint32_t AHB4LPENCR;       /*!< RCC AHB4 sleep enable clear register                           Address offset: 0x129C */
+  __IO uint32_t AHB5LPENCR;       /*!< RCC AHB5 sleep enable clear register                           Address offset: 0x12A0 */
+  __IO uint32_t APB1LPENCR1;      /*!< RCC APB1 sleep enable clear register 1                         Address offset: 0x12A4 */
+  __IO uint32_t APB1LPENCR2;      /*!< RCC APB1 sleep enable clear register 2                         Address offset: 0x12A8 */
+  __IO uint32_t APB2LPENCR;       /*!< RCC APB2 sleep enable clear register                           Address offset: 0x12AC */
+  __IO uint32_t APB3LPENCR;       /*!< RCC APB3 sleep enable clear register                           Address offset: 0x12B0 */
+  __IO uint32_t APB4LPENCR1;      /*!< RCC APB4 sleep enable clear register 1                         Address offset: 0x12B4 */
+  __IO uint32_t APB4LPENCR2;      /*!< RCC APB4 sleep enable clear register 2                         Address offset: 0x12B8 */
+  __IO uint32_t APB5LPENCR;       /*!< RCC APB5 sleep enable clear register                           Address offset: 0x12BC */
+       uint32_t RESERVED36[305];  /*!< Reserved                                                       Address offset: 0x12C0-0x1780 */
+  __IO uint32_t PRIVCFGCR0;       /*!< RCC oscillator privilege configuration clear register 0        Address offset: 0x1784 */
+       uint32_t RESERVED37;       /*!< Reserved                                                       Address offset: 0x1788 */
+  __IO uint32_t PUBCFGCR0;        /*!< RCC oscillator public configuration clear register 0           Address offset: 0x178C */
+       uint32_t RESERVED38;       /*!< Reserved                                                       Address offset: 0x1790 */
+  __IO uint32_t PRIVCFGCR1;       /*!< RCC PLL privilege configuration clear register 1               Address offset: 0x1794 */
+       uint32_t RESERVED39;       /*!< Reserved                                                       Address offset: 0x1798 */
+  __IO uint32_t PUBCFGCR1;        /*!< RCC PLL public configuration clear register 1                  Address offset: 0x179C */
+       uint32_t RESERVED40;       /*!< Reserved                                                       Address offset: 0x17A0 */
+  __IO uint32_t PRIVCFGCR2;       /*!< RCC divider privilege configuration clear register 2           Address offset: 0x17A4 */
+       uint32_t RESERVED41;       /*!< Reserved                                                       Address offset: 0x17A8 */
+  __IO uint32_t PUBCFGCR2;        /*!< RCC divider public configuration clear register 2              Address offset: 0x17AC */
+       uint32_t RESERVED42;       /*!< Reserved                                                       Address offset: 0x17B0 */
+  __IO uint32_t PRIVCFGCR3;       /*!< RCC system privilege configuration clear register 3            Address offset: 0x17B4 */
+       uint32_t RESERVED43;       /*!< Reserved                                                       Address offset: 0x17B8 */
+  __IO uint32_t PUBCFGCR3;        /*!< RCC system public configuration clear register 3               Address offset: 0x17BC */
+       uint32_t RESERVED44;       /*!< Reserved                                                       Address offset: 0x17C0 */
+  __IO uint32_t PRIVCFGCR4;       /*!< RCC privilege configuration clear register 4                   Address offset: 0x17C4 */
+       uint32_t RESERVED45;       /*!< Reserved                                                       Address offset: 0x17C8 */
+  __IO uint32_t PUBCFGCR4;        /*!< RCC public configuration clear register 4                      Address offset: 0x17CC */
+  __IO uint32_t PUBCFGCR5;        /*!< RCC public configuration clear register 5                      Address offset: 0x17D0 */
+} RCC_TypeDef;
+
+/*
+ * @brief  RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1)
+ */
+typedef struct
+{
+  __IO uint32_t RISC_CR;            /*!< RIFSC RISC slave configuration register x               Address offset: 0x000 */
+       uint32_t RESERVED0[3];       /*!< Reserved                                                Address offset: 0x004-0x00C */
+  __IO uint32_t RISC_SECCFGRx[6];   /*!< RIFSC RISC slave security configuration register x      Address offset: 0x010-0x24 */
+       uint32_t RESERVED1[2];       /*!< Reserved                                                Address offset: 0x028-0x02C */
+  __IO uint32_t RISC_PRIVCFGRx[6];  /*!< RIFSC RISFC slave privileged register x                 Address offset: 0x030-0x44 */
+       uint32_t RESERVED2[2];       /*!< Reserved                                                Address offset: 0x048-0x04C */
+  __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */
+       uint32_t RESERVED3[742];     /*!< Reserved                                                Address offset: 0x068-0xBFC */
+  __IO uint32_t RIMC_CR;            /*!< RIFSC RIMC master configuration register                Address offset: 0xC00 */
+       uint32_t RESERVED4[3];       /*!< Reserved                                                Address offset: 0xC04-0xC0C */
+  __IO uint32_t RIMC_ATTRx[13];     /*!< RIFSC RIMC master attribute register x                  Address offset: 0xC10-0xC40 */
+       uint32_t RESERVED5[219];     /*!< Reserved                                                Address offset: 0xC40-0xFAC */
+  __IO uint32_t PPSRx[6];           /*!< RIFSC peripheral protection status register x           Address offset: 0xFB0-0xFC4 */
+       uint32_t RESERVED6[8];       /*!< Reserved                                                Address offset: 0xFC8-0xFE4 */
+} RIFSC_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version)
+  */
+typedef struct
+{
+  __IO uint32_t CFGR;          /*!< RISAF Region X configuration register             */
+  __IO uint32_t STARTR;        /*!< RISAF Region X start address register             */
+  __IO uint32_t ENDR;          /*!< RISAF Region X end address register               */
+  __IO uint32_t CIDCFGR;       /*!< RISAF Region X CID configuration register         */
+  __IO uint32_t ACFGR;         /*!< RISAF Region X subregion A configuration register */
+  __IO uint32_t ASTARTR;       /*!< RISAF Region X subregion A start address register */
+  __IO uint32_t AENDR;         /*!< RISAF Region X subregion A end address register   */
+  __IO uint32_t ANESTR;        /*!< RISAF Region X subregion A nested mode register   */
+  __IO uint32_t BCFGR;         /*!< RISAF Region X subregion B configuration register */
+  __IO uint32_t BSTARTR;       /*!< RISAF Region X subregion B start address register */
+  __IO uint32_t BENDR;         /*!< RISAF Region X subregion B end address register   */
+  __IO uint32_t BNESTR;        /*!< RISAF Region X subregion B nested mode register   */
+       uint32_t RESERVED0[4];  /*!< Reserved                                          */
+} RISAF_Region_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t IAESR;         /*!< RISAF Illegal access error status register */
+  __IO uint32_t IADDR;         /*!< RISAF Illegal address register,            */
+} RISAF_Illegal_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t              CR;            /*!< RISAF Configuration register,                            Address offset: 0x000 */
+  __IO uint32_t              RESERVED0;     /*!< Reserved,                                                Address offset: 0x004 */
+  __IO uint32_t              IASR;          /*!< RISAF Illegal access status register,                    Address offset: 0x008 */
+  __IO uint32_t              IACR;          /*!< RISAF Illegal access clear register,                     Address offset: 0x00C */
+       uint32_t              RESERVED1[4];  /*!< Reserved,                                                          0x010-0x01C */
+       RISAF_Illegal_TypeDef IAR[1];        /*!< RISAF Illegal access error status and address register,            0x020-0x024 */
+       uint32_t              RESERVED2[6];  /*!< Reserved,                                                          0x028-0x03C */
+       RISAF_Region_TypeDef  REG[15];       /*!< RISAF Region X configuration register,                             0x040-0x3FC */
+} RISAF_TypeDef;
+
+/**
+  * @brief RNG
+  */
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+  uint32_t RESERVED;
+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
+} RNG_TypeDef;
+
+/*
+* @brief RTC Specific device feature definitions
+*/
+#define RTC_BKP_NB         32U
+#define RTC_TAMP_NB        7U
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
+ __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
+ __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
+ __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
+ __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
+ __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
+ __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
+__IO uint32_t SECCFGR;      /*!< RTC secure mode control register,               Address offset: 0x20 */
+ __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
+ __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
+ __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
+ __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
+ __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
+ __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
+      uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
+ __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
+ __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
+ __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
+ __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
+ __IO uint32_t SMISR;       /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
+ __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
+      uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
+ __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
+ __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+typedef struct
+{
+  __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
+  uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
+  __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
+  __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,              Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,              Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                   Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                    Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,           Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                 Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                 Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                 Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                 Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                 Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,                Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,               Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,               Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,                     Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,            Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                       Address offset: 0x3C */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,      Address offset: 0x40 */
+  __IO uint32_t FIFOTHR;        /*!< SDMMC data FIFO threshold register,        Address offset: 0x44 */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x48 - 0x4C                                           */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,                Address offset: 0x50 */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,            Address offset: 0x54 */
+  __IO uint32_t IDMABASER;      /*!< SDMMC DMA buffer base address register,    Address offset: 0x58 */
+  uint32_t      RESERVED1[2];   /*!< Reserved, 0x5C - 0x60                                           */
+  __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,    Address offset: 0x64 */
+  __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
+  uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                  Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/**
+  * @brief SPI
+  */
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief UCPD
+  */
+typedef struct
+{
+  __IO uint32_t CFG1;        /*!< UCPD configuration register 1,            Address offset: 0x00 */
+  __IO uint32_t CFG2;        /*!< UCPD configuration register 2,            Address offset: 0x04 */
+  __IO uint32_t RESERVED0;   /*!< UCPD reserved register,                   Address offset: 0x08 */
+  __IO uint32_t CR;          /*!< UCPD control register,                    Address offset: 0x0C */
+  __IO uint32_t IMR;         /*!< UCPD interrupt mask register,             Address offset: 0x10 */
+  __IO uint32_t SR;          /*!< UCPD status register,                     Address offset: 0x14 */
+  __IO uint32_t ICR;         /*!< UCPD interrupt flag clear register        Address offset: 0x18 */
+  __IO uint32_t TX_ORDSET;   /*!< UCPD Tx ordered set type register,        Address offset: 0x1C */
+  __IO uint32_t TX_PAYSZ;    /*!< UCPD Tx payload size register,            Address offset: 0x20 */
+  __IO uint32_t TXDR;        /*!< UCPD Tx data register,                    Address offset: 0x24 */
+  __IO uint32_t RX_ORDSET;   /*!< UCPD Rx ordered set type register,        Address offset: 0x28 */
+  __IO uint32_t RX_PAYSZ;    /*!< UCPD Rx payload size register,            Address offset: 0x2C */
+  __IO uint32_t RXDR;        /*!< UCPD Rx data register,                    Address offset: 0x30 */
+  __IO uint32_t RX_ORDEXT1;  /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
+  __IO uint32_t RX_ORDEXT2;  /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
+} UCPD_TypeDef;
+
+/**
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;             /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t GOTGINT;             /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t GAHBCFG;             /*!< Core AHB Configuration Register,           Address offset: 008h */
+  __IO uint32_t GUSBCFG;             /*!< Core USB Configuration Register,           Address offset: 00Ch */
+  __IO uint32_t GRSTCTL;             /*!< Core Reset Register,                       Address offset: 010h */
+  __IO uint32_t GINTSTS;             /*!< Core Interrupt Register,                   Address offset: 014h */
+  __IO uint32_t GINTMSK;             /*!< Core Interrupt Mask Register,              Address offset: 018h */
+  __IO uint32_t GRXSTSR;             /*!< Receive Sts Q Read Register,               Address offset: 01Ch */
+  __IO uint32_t GRXSTSP;             /*!< Receive Sts Q Read & POP Register,         Address offset: 020h */
+  __IO uint32_t GRXFSIZ;             /*!< Receive FIFO Size Register,                Address offset: 024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;  /*!< EP0 / Non Periodic Tx FIFO Size Register,  Address offset: 028h */
+  __IO uint32_t HNPTXSTS;            /*!< Non Periodic Tx FIFO/Queue Sts reg,        Address offset: 02Ch */
+  __IO uint32_t Reserved30[2];       /*!< Reserved,                                  Address offset: 030h */
+  __IO uint32_t GCCFG;               /*!< General Purpose IO Register,               Address offset: 038h */
+  __IO uint32_t CID;                 /*!< User ID Register,                          Address offset: 03Ch */
+  __IO uint32_t GSNPSID;             /*!< USB_OTG core ID,                           Address offset: 040h */
+  __IO uint32_t GHWCFG1;             /*!< User HW config1,                           Address offset: 044h */
+  __IO uint32_t GHWCFG2;             /*!< User HW config2,                           Address offset: 048h */
+  __IO uint32_t GHWCFG3;             /*!< User HW config3,                           Address offset: 04Ch */
+  __IO uint32_t Reserved6;           /*!< Reserved,                                  Address offset: 050h */
+  __IO uint32_t GLPMCFG;             /*!< LPM Register,                              Address offset: 054h */
+  __IO uint32_t GPWRDN;              /*!< Power Down Register,                       Address offset: 058h */
+  __IO uint32_t GDFIFOCFG;           /*!< DFIFO Software Config Register,            Address offset: 05Ch */
+  __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register,    Address offset: 60Ch */
+  __IO uint32_t Reserved43[39];      /*!< Reserved,                                  Address offset: 058h */
+  __IO uint32_t HPTXFSIZ;            /*!< Host Periodic Tx FIFO Size Reg,            Address offset: 100h */
+  __IO uint32_t DIEPTXF[0x0F];       /*!< dev Periodic Transmit FIFO                 Address offset: 104h */
+} USB_OTG_GlobalTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;          /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;     /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;     /*!< Core AHB Configuration Register,           Address offset: 008h */
+} USB_PHY_GlobalTypeDef;
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;                /*!< dev Configuration Register,   Address offset: 800h */
+  __IO uint32_t DCTL;                /*!< dev Control Register,         Address offset: 804h */
+  __IO uint32_t DSTS;                /*!< dev Status Register (RO),     Address offset: 808h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                     Address offset: 80Ch */
+  __IO uint32_t DIEPMSK;             /*!< dev IN Endpoint Mask,         Address offset: 810h */
+  __IO uint32_t DOEPMSK;             /*!< dev OUT Endpoint Mask,        Address offset: 814h */
+  __IO uint32_t DAINT;               /*!< dev All Endpoints Itr Reg,    Address offset: 818h */
+  __IO uint32_t DAINTMSK;            /*!< dev All Endpoints Itr Mask,   Address offset: 81Ch */
+  __IO uint32_t Reserved20;          /*!< Reserved,                     Address offset: 820h */
+  __IO uint32_t Reserved9;           /*!< Reserved,                     Address offset: 824h */
+  __IO uint32_t DVBUSDIS;            /*!< dev VBUS discharge Register,  Address offset: 828h */
+  __IO uint32_t DVBUSPULSE;          /*!< dev VBUS Pulse Register,      Address offset: 82Ch */
+  __IO uint32_t DTHRCTL;             /*!< dev threshold,                Address offset: 830h */
+  __IO uint32_t DIEPEMPMSK;          /*!< dev empty msk,                Address offset: 834h */
+  __IO uint32_t DEACHINT;            /*!< dedicated EP interrupt,       Address offset: 838h */
+  __IO uint32_t DEACHMSK;            /*!< dedicated EP msk,             Address offset: 83Ch */
+  __IO uint32_t Reserved40;          /*!< dedicated EP mask,            Address offset: 840h */
+  __IO uint32_t DINEP1MSK;           /*!< dedicated EP mask,            Address offset: 844h */
+  __IO uint32_t Reserved44[15];      /*!< Reserved,                     Address offset: 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;          /*!< dedicated EP msk,             Address offset: 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;             /*!< dev IN Endpoint Control Register,          Address offset: 900h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;             /*!< dev IN Endpoint Itr Register,              Address offset: 900h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;            /*!< IN Endpoint Txfer Size Register,           Address offset: 900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;             /*!< IN Endpoint DMA Address Register,          Address offset: 900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;             /*!< IN Endpoint Tx FIFO Status Register,       Address offset: 900h + (ep_num * 20h) + 18h */
+  __IO uint32_t Reserved18;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;             /*!< dev OUT Endpoint Control Register,         Address offset: B00h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;             /*!< dev OUT Endpoint Itr Register,             Address offset: B00h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;            /*!< dev OUT Endpoint Txfer Size Register,      Address offset: B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;             /*!< dev OUT Endpoint DMA Address Register,     Address offset: B00h + (ep_num * 20h) + 14h */
+  __IO uint32_t Reserved18[2];       /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 18h */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;                 /*!< Host Configuration Register,              Address offset: 400h */
+  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register,             Address offset: 404h */
+  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining,           Address offset: 408h */
+  __IO uint32_t Reserved40C;          /*!< Reserved,                                 Address offset: 40Ch */
+  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status,      Address offset: 410h */
+  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register,     Address offset: 414h */
+  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask,         Address offset: 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;               /*!< Host Channel Characteristics Register,    Address offset: 500h */
+  __IO uint32_t HCSPLT;               /*!< Host Channel Split Control Register,      Address offset: 504h */
+  __IO uint32_t HCINT;                /*!< Host Channel Interrupt Register,          Address offset: 508h */
+  __IO uint32_t HCINTMSK;             /*!< Host Channel Interrupt Mask Register,     Address offset: 50Ch */
+  __IO uint32_t HCTSIZ;               /*!< Host Channel Transfer Size Register,      Address offset: 510h */
+  __IO uint32_t HCDMA;                /*!< Host Channel DMA Address Register,        Address offset: 514h */
+  uint32_t Reserved[2];               /*!< Reserved,                                 Address offset: 518h */
+} USB_OTG_HostChannelTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;           /*!< USB HS PHY Control Register,              Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;      /*!< USB HS PHY Trimming_1 Register,           Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;      /*!< USB HS PHY Trimming_2 Register,           Address offset: 008h */
+} USB_HS_PHYC_GlobalTypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t IMR;         /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t IFCR;        /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t DR;          /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t CSR;         /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t DIR;         /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t BOOTCR;         /*!< SYSCFG boot pin control register,                                            Address offset: 0x00 */
+  __IO uint32_t CM55CR;         /*!< SYSCFG Cortex-M55 control register,                                          Address offset: 0x04 */
+  __IO uint32_t CM55TCMCR;      /*!< SYSCFG Cortex-M55 TCM control register,                                      Address offset: 0x08 */
+  __IO uint32_t CM55RWMCR;      /*!< SYSCFG Cortex-M55 memory RW margin register,                                 Address offset: 0x0C */
+  __IO uint32_t INITSVTORCR;    /*!< SYSCFG Cortex-M55 SVTOR control register,                                    Address offset: 0x10 */
+  __IO uint32_t INITNSVTORCR;   /*!< Cortex-M55 NSVTOR control register,                                          Address offset: 0x14 */
+  __IO uint32_t CM55RSTCR;      /*!< SYSCFG Cortex-M55 reset type control register,                               Address offset: 0x18 */
+  __IO uint32_t CM55PAHBWPR;    /*!< SYSCFG Cortex-M55 P-AHB write posting control register,                      Address offset: 0x1C */
+  __IO uint32_t VENCRAMCR;      /*!< SYSCFG VENCRAM control register,                                             Address offset: 0x20 */
+  __IO uint32_t POTTAMPRSTCR;   /*!< SYSCFG potential tamper reset register,                                      Address offset: 0x24 */
+  __IO uint32_t NPUNICQOSCR;    /*!< SYSCFG NPUNIC QoS control register,                                          Address offset: 0x28 */
+  uint32_t      RESERVED1[2];   /*!< Reserved,                                                                    Address offset: 0x2C-0x30 */
+  __IO uint32_t ICNEWRCR;       /*!< SYSCFG AHB-AXI bridge early write response,                                  Address offset: 0x34 */
+  __IO uint32_t ICNCGCR;        /*!< SYSCFG ICN clock gating control register,                                    Address offset: 0x38 */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                                                    Address offset: 0x3C-0x40 */
+  __IO uint32_t VDDIO2CCCR;     /*!< SYSCFG VDDIO2 compensation cell control register,                            Address offset: 0x44 */
+  __IO uint32_t VDDIO2CCSR;     /*!< SYSCFG VDDIO2 compensation cell status register,                             Address offset: 0x48 */
+  __IO uint32_t VDDIO3CCCR;     /*!< SYSCFG VDDIO3 compensation cell control register,                            Address offset: 0x4C */
+  __IO uint32_t VDDIO3CCSR;     /*!< SYSCFG VDDIO3 compensation cell status register,                             Address offset: 0x50 */
+  __IO uint32_t VDDIO4CCCR;     /*!< SYSCFG VDDIO4 compensation cell control register,                            Address offset: 0x54 */
+  __IO uint32_t VDDIO4CCSR;     /*!< SYSCFG VDDIO4 compensation cell status register,                             Address offset: 0x58 */
+  __IO uint32_t VDDIO5CCCR;     /*!< SYSCFG VDDIO5 compensation cell control register,                            Address offset: 0x5C */
+  __IO uint32_t VDDIO5CCSR;     /*!< SYSCFG VDDIO5 compensation cell status register,                             Address offset: 0x60 */
+  __IO uint32_t VDDCCCR;        /*!< SYSCFG VDD compensation cell control register,                               Address offset: 0x64 */
+  __IO uint32_t VDDCCSR;        /*!< SYSCFG VDD compensation cell status register,                                Address offset: 0x68 */
+  __IO uint32_t CBR;            /*!< SYSCFG control timer break register,                                         Address offset: 0x6C */
+  __IO uint32_t SEC_AIDCR;      /*!< SYSCFG DMA CID secure control register,                                      Address offset: 0x70 */
+  __IO uint32_t FMC_RETIMECR;   /*!< SYSCFG FMC retiming logic control register,                                  Address offset: 0x74 */
+  __IO uint32_t NPU_ICNCR;      /*!< SYSCFG NPU RAM interleaving control register,                                Address offset: 0x78 */
+  uint32_t      RESERVED3[33];  /*!< Reserved,                                                                    Address offset: 0x7C-0xFC */
+  __IO uint32_t BOOTSR;         /*!< SYSCFG boot pin status register,                                             Address offset: 0x100 */
+  __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register,                             Address offset: 0x104 */
+  uint32_t      RESERVED4[446]; /*!< Reserved,                                                                    Address offset: 0x108-0x3FC */
+  __IO uint32_t SECPRIV_AIDCR;  /*!< SYSCFG DMA CID non-secure control register,                                  Address offset: 0x800 */
+  uint32_t      RESERVED5[507]; /*!< Reserved,                                                                    Address offset: 0x804-0xFEC */
+  __IO uint32_t DEVICEID;       /*!< SYSCFG Device ID,                                                            Address offset: 0xFF0 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Tamper and backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1;           /*!< TAMP configuration register 1,                    Address offset: 0x00 */
+ __IO uint32_t CR2;           /*!< TAMP configuration register 2,                    Address offset: 0x04 */
+ __IO uint32_t CR3;           /*!< TAMP configuration register 3,                    Address offset: 0x08 */
+ __IO uint32_t FLTCR;         /*!< TAMP filter control register,                     Address offset: 0x0C */
+ __IO uint32_t ATCR1;         /*!< TAMP filter control register 1                    Address offset: 0x10 */
+ __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,                 Address offset: 0x14 */
+ __IO uint32_t ATOR;          /*!< TAMP active tamper output register,               Address offset: 0x18 */
+ __IO uint32_t ATCR2;         /*!< TAMP filter control register 2,                   Address offset: 0x1C */
+ __IO uint32_t SECCFGR;       /*!< TAMP secure mode control register,                Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR;      /*!< TAMP privilege mode control register,             Address offset: 0x24 */
+      uint32_t RESERVED2;     /*!< Reserved,                                         Address offset: 0x28 */
+ __IO uint32_t IER;           /*!< TAMP interrupt enable register,                   Address offset: 0x2C */
+ __IO uint32_t SR;            /*!< TAMP status register,                             Address offset: 0x30 */
+ __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,            Address offset: 0x34 */
+ __IO uint32_t SMISR;         /*!< TAMP secure masked interrupt status register,     Address offset: 0x38 */
+ __IO uint32_t SCR;           /*!< TAMP status clear register,                       Address offset: 0x3C */
+ __IO uint32_t COUNT1R;       /*!< TAMP monotonic counter register,                  Address offset: 0x40 */
+      uint32_t RESERVED4[3];  /*!< Reserved,                                         Address offset: 0x43 -- 0x4C */
+ __IO uint32_t OR;            /*!< TAMP option register,                             Address offset: 0x50 */
+ __IO uint32_t RPCFGR;        /*!< TAMP resources protection configuration register, Address offset: 0x54 */
+      uint32_t RESERVED5[42]; /*!< Reserved,                                         Address offset: 0x58 -- 0xFC */
+ __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                           Address offset: 0x100 */
+ __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                           Address offset: 0x104 */
+ __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                           Address offset: 0x108 */
+ __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                           Address offset: 0x10C */
+ __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                           Address offset: 0x110 */
+ __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                           Address offset: 0x114 */
+ __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                           Address offset: 0x118 */
+ __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                           Address offset: 0x11C */
+ __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                           Address offset: 0x120 */
+ __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                           Address offset: 0x124 */
+ __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                          Address offset: 0x128 */
+ __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                          Address offset: 0x12C */
+ __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                          Address offset: 0x130 */
+ __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                          Address offset: 0x134 */
+ __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                          Address offset: 0x138 */
+ __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                          Address offset: 0x13C */
+ __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                          Address offset: 0x140 */
+ __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                          Address offset: 0x144 */
+ __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                          Address offset: 0x148 */
+ __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                          Address offset: 0x14C */
+ __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                          Address offset: 0x150 */
+ __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                          Address offset: 0x154 */
+ __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                          Address offset: 0x158 */
+ __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                          Address offset: 0x15C */
+ __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                          Address offset: 0x160 */
+ __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                          Address offset: 0x164 */
+ __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                          Address offset: 0x168 */
+ __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                          Address offset: 0x16C */
+ __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                          Address offset: 0x170 */
+ __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                          Address offset: 0x174 */
+ __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                          Address offset: 0x178 */
+ __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                          Address offset: 0x17C */
+} TAMP_TypeDef;
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint32_t CR1;            /*!< TIM control register 1,                   Address offset:  0x00 */
+  __IO uint32_t CR2;            /*!< TIM control register 2,                   Address offset:  0x04 */
+  __IO uint32_t SMCR;           /*!< TIM slave mode control register,          Address offset:  0x08 */
+  __IO uint32_t DIER;           /*!< TIM DMA/interrupt enable register,        Address offset:  0x0C */
+  __IO uint32_t SR;             /*!< TIM status register,                      Address offset:  0x10 */
+  __IO uint32_t EGR;            /*!< TIM event generation register,            Address offset:  0x14 */
+  __IO uint32_t CCMR1;          /*!< TIM capture/compare mode register 1,      Address offset:  0x18 */
+  __IO uint32_t CCMR2;          /*!< TIM capture/compare mode register 2,      Address offset:  0x1C */
+  __IO uint32_t CCER;           /*!< TIM capture/compare enable register,      Address offset:  0x20 */
+  __IO uint32_t CNT;            /*!< TIM counter register,                     Address offset:  0x24 */
+  __IO uint32_t PSC;            /*!< TIM prescaler,                            Address offset:  0x28 */
+  __IO uint32_t ARR;            /*!< TIM auto-reload register,                 Address offset:  0x2C */
+  __IO uint32_t RCR;            /*!< TIM repetition counter register,          Address offset:  0x30 */
+  __IO uint32_t CCR1;           /*!< TIM capture/compare register 1,           Address offset:  0x34 */
+  __IO uint32_t CCR2;           /*!< TIM capture/compare register 2,           Address offset:  0x38 */
+  __IO uint32_t CCR3;           /*!< TIM capture/compare register 3,           Address offset:  0x3C */
+  __IO uint32_t CCR4;           /*!< TIM capture/compare register 4,           Address offset:  0x40 */
+  __IO uint32_t BDTR;           /*!< TIM break and dead-time register,         Address offset:  0x44 */
+  __IO uint32_t CCR5;           /*!< TIM capture/compare register 5,           Address offset:  0x48 */
+  __IO uint32_t CCR6;           /*!< TIM capture/compare register 6,           Address offset:  0x4C */
+  __IO uint32_t CCMR3;          /*!< TIM capture/compare mode register 3,      Address offset:  0x50 */
+  __IO uint32_t DTR2;           /*!< TIM deadtime register 2,                  Address offset:  0x54 */
+  __IO uint32_t ECR;            /*!< TIM encoder control register,             Address offset:  0x58 */
+  __IO uint32_t TISEL;          /*!< TIM Input Selection register,             Address offset:  0x5C */
+  __IO uint32_t AF1;            /*!< TIM alternate function option register 1, Address offset:  0x60 */
+  __IO uint32_t AF2;            /*!< TIM alternate function option register 2, Address offset:  0x64 */
+       uint32_t RESERVED1[221]; /*!< Reserved,                                            0x6C-0x3D8 */
+  __IO uint32_t DCR;            /*!< TIM DMA control register,                 Address offset: 0x3DC */
+  __IO uint32_t DMAR;           /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C */
+} USART_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief Window Watchdog
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,              Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,               Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief Extended-SPI Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI Control Register,                                Address offset: 0x000         */
+       uint32_t RESERVED1;      /*!< Reserved,                                             Address offset: 0x004         */
+  __IO uint32_t DCR1;           /*!< XSPI Device Configuration Register 1,                 Address offset: 0x008         */
+  __IO uint32_t DCR2;           /*!< XSPI Device Configuration Register 2,                 Address offset: 0x00C         */
+  __IO uint32_t DCR3;           /*!< XSPI Device Configuration Register 3,                 Address offset: 0x010         */
+  __IO uint32_t DCR4;           /*!< XSPI Device Configuration Register 4,                 Address offset: 0x014         */
+       uint32_t RESERVED2[2];   /*!< Reserved,                                             Address offset: 0x018 - 0x01C */
+  __IO uint32_t SR;             /*!< XSPI Status Register,                                 Address offset: 0x020         */
+  __IO uint32_t FCR;            /*!< XSPI Flag Clear Register,                             Address offset: 0x024         */
+       uint32_t RESERVED3[6];   /*!< Reserved,                                             Address offset: 0x028 - 0x03C */
+  __IO uint32_t DLR;            /*!< XSPI Data Length Register,                            Address offset: 0x040         */
+       uint32_t RESERVED4;      /*!< Reserved,                                             Address offset: 0x044         */
+  __IO uint32_t AR;             /*!< XSPI Address Register,                                Address offset: 0x048         */
+       uint32_t RESERVED5;      /*!< Reserved,                                             Address offset: 0x04C         */
+  __IO uint32_t DR;             /*!< XSPI Data Register,                                   Address offset: 0x050         */
+       uint32_t RESERVED6[11];  /*!< Reserved,                                             Address offset: 0x054 - 0x07C */
+  __IO uint32_t PSMKR;          /*!< XSPI Polling Status Mask Register,                    Address offset: 0x080         */
+       uint32_t RESERVED7;      /*!< Reserved,                                             Address offset: 0x084         */
+  __IO uint32_t PSMAR;          /*!< XSPI Polling Status Match Register,                   Address offset: 0x088         */
+       uint32_t RESERVED8;      /*!< Reserved,                                             Address offset: 0x08C         */
+  __IO uint32_t PIR;            /*!< XSPI Polling Interval Register,                       Address offset: 0x090         */
+       uint32_t RESERVED9[27];  /*!< Reserved,                                             Address offset: 0x094 - 0x0FC */
+  __IO uint32_t CCR;            /*!< XSPI Communication Configuration Register,            Address offset: 0x100         */
+       uint32_t RESERVED10;     /*!< Reserved,                                             Address offset: 0x104         */
+  __IO uint32_t TCR;            /*!< XSPI Timing Configuration Register,                   Address offset: 0x108         */
+       uint32_t RESERVED11;     /*!< Reserved,                                             Address offset: 0x10C         */
+  __IO uint32_t IR;             /*!< XSPI Instruction Register,                            Address offset: 0x110         */
+       uint32_t RESERVED12[3];  /*!< Reserved,                                             Address offset: 0x114 - 0x11C */
+  __IO uint32_t ABR;            /*!< XSPI Alternate Bytes Register,                        Address offset: 0x120         */
+       uint32_t RESERVED13[3];  /*!< Reserved,                                             Address offset: 0x124 - 0x12C */
+  __IO uint32_t LPTR;           /*!< XSPI Low-Power Timeout Register,                      Address offset: 0x130         */
+       uint32_t RESERVED14[3];  /*!< Reserved,                                             Address offset: 0x134 - 0x13C */
+  __IO uint32_t WPCCR;          /*!< XSPI Wrap Communication Configuration Register,       Address offset: 0x140         */
+       uint32_t RESERVED15;     /*!< Reserved,                                             Address offset: 0x144         */
+  __IO uint32_t WPTCR;          /*!< XSPI Wrap Timing Configuration Register,              Address offset: 0x148         */
+       uint32_t RESERVED16;     /*!< Reserved,                                             Address offset: 0x14C         */
+  __IO uint32_t WPIR;           /*!< XSPI Wrap Instruction Register,                       Address offset: 0x150         */
+       uint32_t RESERVED17[3];  /*!< Reserved,                                             Address offset: 0x154 - 0x15C */
+  __IO uint32_t WPABR;          /*!< XSPI Wrap Alternate Bytes Register,                   Address offset: 0x160         */
+       uint32_t RESERVED18[7];  /*!< Reserved,                                             Address offset: 0x164 - 0x17C */
+  __IO uint32_t WCCR;           /*!< XSPI Write Communication Configuration Register,      Address offset: 0x180         */
+       uint32_t RESERVED19;     /*!< Reserved,                                             Address offset: 0x184         */
+  __IO uint32_t WTCR;           /*!< XSPI Write Timing Configuration Register,             Address offset: 0x188         */
+       uint32_t RESERVED20;     /*!< Reserved,                                             Address offset: 0x18C         */
+  __IO uint32_t WIR;            /*!< XSPI Write Instruction Register,                      Address offset: 0x190         */
+       uint32_t RESERVED21[3];  /*!< Reserved,                                             Address offset: 0x194 - 0x19C */
+  __IO uint32_t WABR;           /*!< XSPI Write Alternate Bytes Register,                  Address offset: 0x1A0         */
+       uint32_t RESERVED22[23]; /*!< Reserved,                                             Address offset: 0x1A4 - 0x1FC */
+  __IO uint32_t HLCR;           /*!< XSPI HyperBus Latency Configuration Register,         Address offset: 0x200         */
+       uint32_t RESERVED23[3];  /*!< Reserved,                                             Address offset: 0x204 - 0x20C */
+  __IO uint32_t CALFCR;         /*!< XSPI Full-Cycle Calibration Configuration Register,   Address offset: 0x210         */
+       uint32_t RESERVED24;     /*!< Reserved,                                             Address offset: 0x214         */
+  __IO uint32_t CALMR;          /*!< XSPI DLL Master Calibration Configuration Register,   Address offset: 0x218         */
+       uint32_t RESERVED25;     /*!< Reserved,                                             Address offset: 0x21C         */
+  __IO uint32_t CALSOR;         /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220         */
+       uint32_t RESERVED26;     /*!< Reserved,                                             Address offset: 0x224         */
+  __IO uint32_t CALSIR;         /*!< XSPI Slave Input Calibration Configuration Register,  Address offset: 0x228         */
+} XSPI_TypeDef;
+
+/**
+  * @brief XSPI IO Manager
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI IO Manager Control Register,                     Address offset: 0x00        */
+} XSPIM_TypeDef;
+
+/** @} */ /* End of group STM32N6xx_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_peripheralAddr
+  * @{
+  */
+
+/* Internal RAMs sizes */
+#define SRAM1_AXI_SIZE                  0x100000UL   /*!< SRAM1_AXI = 1024 Kbytes */
+#define SRAM2_AXI_SIZE                  0x100000UL   /*!< SRAM2_AXI = 1024 Kbytes */
+#define FLEXRAM_SIZE                     0x64000UL   /*!< FLEXRAM <= 400 Kbytes   */
+#define SRAM3_AXI_SIZE                   0x70000UL   /*!< SRAM3_AXI = 448 Kbytes  */
+#define SRAM4_AXI_SIZE                   0x70000UL   /*!< SRAM4_AXI = 448 Kbytes  */
+#define SRAM5_AXI_SIZE                   0x70000UL   /*!< SRAM5_AXI = 448 Kbytes  */
+#define SRAM6_AXI_SIZE                   0x70000UL   /*!< SRAM6_AXI = 448 Kbytes  */
+#define SRAM1_AHB_SIZE                    0x4000UL   /*!< SRAM1_AHB = 16 Kbytes   */
+#define SRAM2_AHB_SIZE                    0x4000UL   /*!< SRAM2_AHB = 16 Kbytes   */
+#define VENC_RAM_SIZE                    0x20000UL   /*!< VENC RAM  = 128 Kbytes  */
+#define CACHEAXI_RAM_SIZE                0x40000UL   /*!< CACHEAXI RAM = 256 Kbytes */
+#define BKPSRAM_SIZE                      0x2000UL   /*!< BKPSRAM  = 8 Kbytes     */
+
+
+#define FMC_BASE                        0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */
+#define FMC_BANK1                       FMC_BASE
+#define FMC_BANK1_1                     FMC_BANK1
+#define FMC_BANK1_2                     (FMC_BANK1 + 0x04000000UL)
+#define FMC_BANK1_3                     (FMC_BANK1 + 0x08000000UL)
+#define FMC_BANK1_4                     (FMC_BANK1 + 0x0C000000UL)
+#define FMC_BANK5                       0xC0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK5_1                     FMC_BANK5
+#define FMC_BANK5_2                     (FMC_BANK5 + 0x04000000UL)
+#define FMC_BANK5_3                     (FMC_BANK5 + 0x08000000UL)
+#define FMC_BANK5_4                     (FMC_BANK5 + 0x0C000000UL)
+#define FMC_BANK6                       0xD0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK6_1                     FMC_BANK6
+#define FMC_BANK6_2                     (FMC_BANK6 + 0x04000000UL)
+#define FMC_BANK6_3                     (FMC_BANK6 + 0x08000000UL)
+#define FMC_BANK6_4                     (FMC_BANK6 + 0x0C000000UL)
+#define XSPI1_BASE                      0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI    */
+#define XSPI2_BASE                      0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI    */
+#define XSPI3_BASE                      0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI    */
+
+/**************************************************************************/
+/*                                                                        */
+/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */
+/*                                                                        */
+/**************************************************************************/
+
+#define ITCM_BASE_NS                    0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_NS                 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_NS                    0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_NS               0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_NS               0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_NS               0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_NS               0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_NS               0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_NS               0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_NS                SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define CACHEAXI_RAM_BASE_NS            0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI   */
+#define VENC_RAM_BASE_NS                0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS  0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS  0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS  0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS  0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_NS         0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_NS               0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_NS               0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_NS                SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */
+#define BKPSRAM_BASE_NS                 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge      */
+#define PERIPH_BASE_NS                  0x40000000UL /*!< Base address of : AHB/APB Peripherals                      */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_NS              PERIPH_BASE_NS
+#define AHB1PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00020000UL)
+#define APB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02000000UL)
+#define AHB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02020000UL)
+#define APB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04000000UL)
+#define AHB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04020000UL)
+#define APB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06000000UL)
+#define AHB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06020000UL)
+#define APB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08000000UL)
+#define AHB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0000UL)
+#define TIM3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0400UL)
+#define TIM4_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0800UL)
+#define TIM5_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0C00UL)
+#define TIM6_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1000UL)
+#define TIM7_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1400UL)
+#define TIM12_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1800UL)
+#define TIM13_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1C00UL)
+#define TIM14_BASE_NS                   (APB1PERIPH_BASE_NS + 0x2000UL)
+#define LPTIM1_BASE_NS                  (APB1PERIPH_BASE_NS + 0x2400UL)
+#define WWDG_BASE_NS                    (APB1PERIPH_BASE_NS + 0x2C00UL)
+#define TIM10_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3000UL)
+#define TIM11_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3400UL)
+#define SPI2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3800UL)
+#define SPI3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3C00UL)
+#define SPDIFRX_BASE_NS                 (APB1PERIPH_BASE_NS + 0x4000UL)
+#define USART2_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4400UL)
+#define USART3_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4800UL)
+#define UART4_BASE_NS                   (APB1PERIPH_BASE_NS + 0x4C00UL)
+#define UART5_BASE_NS                   (APB1PERIPH_BASE_NS + 0x5000UL)
+#define I2C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5400UL)
+#define I2C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5800UL)
+#define I2C3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5C00UL)
+#define I3C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6000UL)
+#define I3C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6400UL)
+#define UART7_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7800UL)
+#define UART8_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7C00UL)
+#define MDIOS_BASE_NS                   (APB1PERIPH_BASE_NS + 0x9400UL)
+#define FDCAN1_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA000UL)
+#define FDCAN_CONFIG_BASE_NS            (APB1PERIPH_BASE_NS + 0xA100UL)
+#define FDCAN2_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA400UL)
+#define FDCAN_CCU_BASE_NS               (APB1PERIPH_BASE_NS + 0xA800UL)
+#define SRAMCAN_BASE_NS                 (APB1PERIPH_BASE_NS + 0xC000UL)
+#define FDCAN3_BASE_NS                  (APB1PERIPH_BASE_NS + 0xE800UL)
+#define UCPD1_BASE_NS                   (APB1PERIPH_BASE_NS + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_NS                  (AHB1PERIPH_BASE_NS + 0x1000UL)
+#define GPDMA1_Channel0_BASE_NS         (GPDMA1_BASE_NS + 0x0050UL)
+#define GPDMA1_Channel1_BASE_NS         (GPDMA1_BASE_NS + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_NS         (GPDMA1_BASE_NS + 0x0150UL)
+#define GPDMA1_Channel3_BASE_NS         (GPDMA1_BASE_NS + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_NS         (GPDMA1_BASE_NS + 0x0250UL)
+#define GPDMA1_Channel5_BASE_NS         (GPDMA1_BASE_NS + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_NS         (GPDMA1_BASE_NS + 0x0350UL)
+#define GPDMA1_Channel7_BASE_NS         (GPDMA1_BASE_NS + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_NS         (GPDMA1_BASE_NS + 0x0450UL)
+#define GPDMA1_Channel9_BASE_NS         (GPDMA1_BASE_NS + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_NS        (GPDMA1_BASE_NS + 0x0550UL)
+#define GPDMA1_Channel11_BASE_NS        (GPDMA1_BASE_NS + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_NS        (GPDMA1_BASE_NS + 0x0650UL)
+#define GPDMA1_Channel13_BASE_NS        (GPDMA1_BASE_NS + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_NS        (GPDMA1_BASE_NS + 0x0750UL)
+#define GPDMA1_Channel15_BASE_NS        (GPDMA1_BASE_NS + 0x07D0UL)
+#define ADC1_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2000UL)
+#define ADC2_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2100UL)
+#define ADC12_COMMON_BASE_NS            (AHB1PERIPH_BASE_NS + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0000UL)
+#define TIM8_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0400UL)
+#define USART1_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1000UL)
+#define USART6_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1400UL)
+#define UART9_BASE_NS                   (APB2PERIPH_BASE_NS + 0x1800UL)
+#define USART10_BASE_NS                 (APB2PERIPH_BASE_NS + 0x1C00UL)
+#define SPI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3000UL)
+#define SPI4_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3400UL)
+#define TIM18_BASE_NS                   (APB2PERIPH_BASE_NS + 0x3C00UL)
+#define TIM15_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4000UL)
+#define TIM16_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4400UL)
+#define TIM17_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4800UL)
+#define TIM9_BASE_NS                    (APB2PERIPH_BASE_NS + 0x4C00UL)
+#define SPI5_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5000UL)
+#define SAI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5800UL)
+#define SAI1_Block_A_BASE_NS            (SAI1_BASE_NS + 0x0004UL)
+#define SAI1_Block_B_BASE_NS            (SAI1_BASE_NS + 0x0024UL)
+#define SAI2_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5C00UL)
+#define SAI2_Block_A_BASE_NS            (SAI2_BASE_NS + 0x0004UL)
+#define SAI2_Block_B_BASE_NS            (SAI2_BASE_NS + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_NS                  (AHB2PERIPH_BASE_NS + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_NS        (RAMCFG_BASE_NS)
+#define RAMCFG_SRAM2_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_NS         (RAMCFG_BASE_NS + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0500UL)
+#define MDF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x5000UL)
+#define MDF1_Filter0_BASE_NS            (MDF1_BASE_NS + 0x0080UL)
+#define MDF1_Filter1_BASE_NS            (MDF1_BASE_NS + 0x0100UL)
+#define MDF1_Filter2_BASE_NS            (MDF1_BASE_NS + 0x0180UL)
+#define MDF1_Filter3_BASE_NS            (MDF1_BASE_NS + 0x0200UL)
+#define MDF1_Filter4_BASE_NS            (MDF1_BASE_NS + 0x0280UL)
+#define MDF1_Filter5_BASE_NS            (MDF1_BASE_NS + 0x0300UL)
+#define ADF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x6000UL)
+#define ADF1_Filter0_BASE_NS            (ADF1_BASE_NS + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_NS                 (APB3PERIPH_BASE_NS + 0x0000UL)
+#define DBGMCU_BASE_NS                  (APB3PERIPH_BASE_NS + 0x1000UL)
+#define DFT_APB_BASE_NS                 (APB3PERIPH_BASE_NS + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x0000UL)
+#define HASH_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0400UL)
+#define HASH_DIGEST_BASE_NS             (AHB3PERIPH_BASE_NS + 0x0710UL)
+#define PKA_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x2000UL)
+#define RIFSC_BASE_NS                   (AHB3PERIPH_BASE_NS + 0x4000UL)
+#define RISAF1_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x6000UL)
+#define RISAF2_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x7000UL)
+#define RISAF3_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x8000UL)
+#define RISAF4_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x9000UL)
+#define RISAF5_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xA000UL)
+#define RISAF6_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xB000UL)
+#define RISAF7_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xC000UL)
+#define RISAF8_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xD000UL)
+#define RISAF9_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xE000UL)
+#define RISAF11_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x010000UL)
+#define RISAF12_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x011000UL)
+#define RISAF13_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x012000UL)
+#define RISAF14_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x013000UL)
+#define RISAF15_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x014000UL)
+#define RISAF21_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x015000UL)
+#define RISAF22_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x016000UL)
+#define RISAF23_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_NS                     (APB4PERIPH_BASE_NS + 0x0800UL)
+#define LPUART1_BASE_NS                 (APB4PERIPH_BASE_NS + 0x0C00UL)
+#define SPI6_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1400UL)
+#define I2C4_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1C00UL)
+#define LPTIM2_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2400UL)
+#define LPTIM3_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2800UL)
+#define LPTIM4_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2C00UL)
+#define LPTIM5_BASE_NS                  (APB4PERIPH_BASE_NS + 0x3000UL)
+#define VREFBUF_BASE_NS                 (APB4PERIPH_BASE_NS + 0x3C00UL)
+#define RTC_BASE_NS                     (APB4PERIPH_BASE_NS + 0x4000UL)
+#define TAMP_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4400UL)
+#define IWDG_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4800UL)
+#define SERC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x7C00UL)
+#define SYSCFG_BASE_NS                  (APB4PERIPH_BASE_NS + 0x8000UL)
+#define BSEC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x9000UL)
+#define DTS_BASE_NS                     (APB4PERIPH_BASE_NS + 0xA000UL)
+#define DTS_Sensor0_BASE_NS             (DTS_BASE_NS + 0x0C0UL)
+#define DTS_Sensor1_BASE_NS             (DTS_BASE_NS + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0000UL)
+#define GPIOB_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0400UL)
+#define GPIOC_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0800UL)
+#define GPIOD_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0C00UL)
+#define GPIOE_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1000UL)
+#define GPIOF_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1400UL)
+#define GPIOG_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1800UL)
+#define GPIOH_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1C00UL)
+#define GPION_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3400UL)
+#define GPIOO_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3800UL)
+#define GPIOP_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3C00UL)
+#define GPIOQ_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x4000UL)
+#define PWR_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4800UL)
+#define CRC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4C00UL)
+#define EXTI_BASE_NS                    (AHB4PERIPH_BASE_NS + 0x5000UL)
+#define RCC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x1000UL)
+#define LTDC_Layer1_BASE_NS             (LTDC_BASE_NS + 0x0100UL)
+#define LTDC_Layer2_BASE_NS             (LTDC_BASE_NS + 0x0200UL)
+#define DCMIPP_BASE_NS                  (APB5PERIPH_BASE_NS + 0x2000UL)
+#define GFXTIM_BASE_NS                  (APB5PERIPH_BASE_NS + 0x4000UL)
+#define VENC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x5000UL)
+#define CSI_BASE_NS                     (APB5PERIPH_BASE_NS + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x0000UL)
+#define HPDMA1_Channel0_BASE_NS         (HPDMA1_BASE_NS + 0x0050UL)
+#define HPDMA1_Channel1_BASE_NS         (HPDMA1_BASE_NS + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_NS         (HPDMA1_BASE_NS + 0x0150UL)
+#define HPDMA1_Channel3_BASE_NS         (HPDMA1_BASE_NS + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_NS         (HPDMA1_BASE_NS + 0x0250UL)
+#define HPDMA1_Channel5_BASE_NS         (HPDMA1_BASE_NS + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_NS         (HPDMA1_BASE_NS + 0x0350UL)
+#define HPDMA1_Channel7_BASE_NS         (HPDMA1_BASE_NS + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_NS         (HPDMA1_BASE_NS + 0x0450UL)
+#define HPDMA1_Channel9_BASE_NS         (HPDMA1_BASE_NS + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_NS        (HPDMA1_BASE_NS + 0x0550UL)
+#define HPDMA1_Channel11_BASE_NS        (HPDMA1_BASE_NS + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_NS        (HPDMA1_BASE_NS + 0x0650UL)
+#define HPDMA1_Channel13_BASE_NS        (HPDMA1_BASE_NS + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_NS        (HPDMA1_BASE_NS + 0x0750UL)
+#define HPDMA1_Channel15_BASE_NS        (HPDMA1_BASE_NS + 0x07D0UL)
+#define DMA2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x1000UL)
+#define JPEG_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x3000UL)
+#define FMC_R_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x4000UL)
+#define FMC_Bank1_R_BASE_NS             (FMC_R_BASE_NS + 0x0000UL)
+#define FMC_Bank1E_R_BASE_NS            (FMC_R_BASE_NS + 0x0104UL)
+#define FMC_Bank3_R_BASE_NS             (FMC_R_BASE_NS + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_NS           (FMC_R_BASE_NS + 0x0140UL)
+#define FMC_Common_R_BASE_NS            (FMC_R_BASE_NS + 0x0020UL)
+#define XSPI1_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x5000UL)
+#define PSSI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x6400UL)
+#define SDMMC2_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x6800UL)
+#define DLYB_SDMMC2_BASE_NS             (AHB5PERIPH_BASE_NS + 0x6C00UL)
+#define SDMMC1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x7000UL)
+#define DLYB_SDMMC1_BASE_NS             (AHB5PERIPH_BASE_NS + 0x8000UL)
+#define DCMI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x8400UL)
+#define XSPI2_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xA000UL)
+#define XSPIM_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xB400UL)
+#define XSPI3_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xD000UL)
+#define GFXMMU_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x010000UL)
+#define GPU2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x014000UL)
+#define GPUCACHE_BASE_NS                (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ICACHE_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ETH1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x016000UL)
+#define ETH1_MAC_BASE_NS                (ETH1_BASE_NS)
+#define USB1_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x020000UL)
+#define USB2_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x060000UL)
+#define CACHEAXI_BASE_NS                (AHB5PERIPH_BASE_NS + 0x0BFC00UL)
+#define NPU_BASE_NS                     (AHB5PERIPH_BASE_NS + 0x0C0000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_NS                     (0x46009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_NS                   (BOOTROM_BASE_NS + 0x0047ECUL)
+
+
+#if defined (CPU_IN_SECURE_STATE)
+/*********************************************************************/
+/*                                                                   */
+/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */
+/*                                                                   */
+/*********************************************************************/
+#define ITCM_BASE_S                     0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_S                  0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_S                     0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_S                0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_S                0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_S                0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_S                0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_S                0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_S                0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_S                 SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define CACHEAXI_RAM_BASE_S             0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI   */
+#define VENC_RAM_BASE_S                 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_S   0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_S   0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_S   0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_S   0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_S          0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_S                0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_S                0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_S                 SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge  */
+#define BKPSRAM_BASE_S                  0x3C000000UL   /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge    */
+#define PERIPH_BASE_S                   0x50000000UL   /*!< Base address of : AHB/APB Peripherals                    */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_S               PERIPH_BASE_S
+#define AHB1PERIPH_BASE_S               (PERIPH_BASE_S + 0x00020000UL)
+#define APB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02000000UL)
+#define AHB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02020000UL)
+#define APB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04000000UL)
+#define AHB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04020000UL)
+#define APB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06000000UL)
+#define AHB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06020000UL)
+#define APB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08000000UL)
+#define AHB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_S                     (APB1PERIPH_BASE_S + 0x0000UL)
+#define TIM3_BASE_S                     (APB1PERIPH_BASE_S + 0x0400UL)
+#define TIM4_BASE_S                     (APB1PERIPH_BASE_S + 0x0800UL)
+#define TIM5_BASE_S                     (APB1PERIPH_BASE_S + 0x0C00UL)
+#define TIM6_BASE_S                     (APB1PERIPH_BASE_S + 0x1000UL)
+#define TIM7_BASE_S                     (APB1PERIPH_BASE_S + 0x1400UL)
+#define TIM12_BASE_S                    (APB1PERIPH_BASE_S + 0x1800UL)
+#define TIM13_BASE_S                    (APB1PERIPH_BASE_S + 0x1C00UL)
+#define TIM14_BASE_S                    (APB1PERIPH_BASE_S + 0x2000UL)
+#define LPTIM1_BASE_S                   (APB1PERIPH_BASE_S + 0x2400UL)
+#define WWDG_BASE_S                     (APB1PERIPH_BASE_S + 0x2C00UL)
+#define TIM10_BASE_S                    (APB1PERIPH_BASE_S + 0x3000UL)
+#define TIM11_BASE_S                    (APB1PERIPH_BASE_S + 0x3400UL)
+#define SPI2_BASE_S                     (APB1PERIPH_BASE_S + 0x3800UL)
+#define SPI3_BASE_S                     (APB1PERIPH_BASE_S + 0x3C00UL)
+#define SPDIFRX_BASE_S                  (APB1PERIPH_BASE_S + 0x4000UL)
+#define USART2_BASE_S                   (APB1PERIPH_BASE_S + 0x4400UL)
+#define USART3_BASE_S                   (APB1PERIPH_BASE_S + 0x4800UL)
+#define UART4_BASE_S                    (APB1PERIPH_BASE_S + 0x4C00UL)
+#define UART5_BASE_S                    (APB1PERIPH_BASE_S + 0x5000UL)
+#define I2C1_BASE_S                     (APB1PERIPH_BASE_S + 0x5400UL)
+#define I2C2_BASE_S                     (APB1PERIPH_BASE_S + 0x5800UL)
+#define I2C3_BASE_S                     (APB1PERIPH_BASE_S + 0x5C00UL)
+#define I3C1_BASE_S                     (APB1PERIPH_BASE_S + 0x6000UL)
+#define I3C2_BASE_S                     (APB1PERIPH_BASE_S + 0x6400UL)
+#define UART7_BASE_S                    (APB1PERIPH_BASE_S + 0x7800UL)
+#define UART8_BASE_S                    (APB1PERIPH_BASE_S + 0x7C00UL)
+#define MDIOS_BASE_S                    (APB1PERIPH_BASE_S + 0x9400UL)
+#define FDCAN1_BASE_S                   (APB1PERIPH_BASE_S + 0xA000UL)
+#define FDCAN_CONFIG_BASE_S             (APB1PERIPH_BASE_S + 0xA100UL)
+#define FDCAN2_BASE_S                   (APB1PERIPH_BASE_S + 0xA400UL)
+#define FDCAN_CCU_BASE_S                (APB1PERIPH_BASE_S + 0xA800UL)
+#define SRAMCAN_BASE_S                  (APB1PERIPH_BASE_S + 0xC000UL)
+#define FDCAN3_BASE_S                   (APB1PERIPH_BASE_S + 0xE800UL)
+#define UCPD1_BASE_S                    (APB1PERIPH_BASE_S + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_S                   (AHB1PERIPH_BASE_S + 0x1000UL)
+#define GPDMA1_Channel0_BASE_S          (GPDMA1_BASE_S + 0x0050UL)
+#define GPDMA1_Channel1_BASE_S          (GPDMA1_BASE_S + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_S          (GPDMA1_BASE_S + 0x0150UL)
+#define GPDMA1_Channel3_BASE_S          (GPDMA1_BASE_S + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_S          (GPDMA1_BASE_S + 0x0250UL)
+#define GPDMA1_Channel5_BASE_S          (GPDMA1_BASE_S + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_S          (GPDMA1_BASE_S + 0x0350UL)
+#define GPDMA1_Channel7_BASE_S          (GPDMA1_BASE_S + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_S          (GPDMA1_BASE_S + 0x0450UL)
+#define GPDMA1_Channel9_BASE_S          (GPDMA1_BASE_S + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_S         (GPDMA1_BASE_S + 0x0550UL)
+#define GPDMA1_Channel11_BASE_S         (GPDMA1_BASE_S + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_S         (GPDMA1_BASE_S + 0x0650UL)
+#define GPDMA1_Channel13_BASE_S         (GPDMA1_BASE_S + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_S         (GPDMA1_BASE_S + 0x0750UL)
+#define GPDMA1_Channel15_BASE_S         (GPDMA1_BASE_S + 0x07D0UL)
+#define ADC1_BASE_S                     (AHB1PERIPH_BASE_S + 0x2000UL)
+#define ADC2_BASE_S                     (AHB1PERIPH_BASE_S + 0x2100UL)
+#define ADC12_COMMON_BASE_S             (AHB1PERIPH_BASE_S + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_S                     (APB2PERIPH_BASE_S + 0x0000UL)
+#define TIM8_BASE_S                     (APB2PERIPH_BASE_S + 0x0400UL)
+#define USART1_BASE_S                   (APB2PERIPH_BASE_S + 0x1000UL)
+#define USART6_BASE_S                   (APB2PERIPH_BASE_S + 0x1400UL)
+#define UART9_BASE_S                    (APB2PERIPH_BASE_S + 0x1800UL)
+#define USART10_BASE_S                  (APB2PERIPH_BASE_S + 0x1C00UL)
+#define SPI1_BASE_S                     (APB2PERIPH_BASE_S + 0x3000UL)
+#define SPI4_BASE_S                     (APB2PERIPH_BASE_S + 0x3400UL)
+#define TIM18_BASE_S                    (APB2PERIPH_BASE_S + 0x3C00UL)
+#define TIM15_BASE_S                    (APB2PERIPH_BASE_S + 0x4000UL)
+#define TIM16_BASE_S                    (APB2PERIPH_BASE_S + 0x4400UL)
+#define TIM17_BASE_S                    (APB2PERIPH_BASE_S + 0x4800UL)
+#define TIM9_BASE_S                     (APB2PERIPH_BASE_S + 0x4C00UL)
+#define SPI5_BASE_S                     (APB2PERIPH_BASE_S + 0x5000UL)
+#define SAI1_BASE_S                     (APB2PERIPH_BASE_S + 0x5800UL)
+#define SAI1_Block_A_BASE_S             (SAI1_BASE_S + 0x0004UL)
+#define SAI1_Block_B_BASE_S             (SAI1_BASE_S + 0x0024UL)
+#define SAI2_BASE_S                     (APB2PERIPH_BASE_S + 0x5C00UL)
+#define SAI2_Block_A_BASE_S             (SAI2_BASE_S + 0x0004UL)
+#define SAI2_Block_B_BASE_S             (SAI2_BASE_S + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_S                   (AHB2PERIPH_BASE_S + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_S         (RAMCFG_BASE_S)
+#define RAMCFG_SRAM2_AXI_BASE_S         (RAMCFG_BASE_S + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_S         (RAMCFG_BASE_S + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_S         (RAMCFG_BASE_S + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_S         (RAMCFG_BASE_S + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_S         (RAMCFG_BASE_S + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_S         (RAMCFG_BASE_S + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_S         (RAMCFG_BASE_S + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_S          (RAMCFG_BASE_S + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_S           (RAMCFG_BASE_S + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_S           (RAMCFG_BASE_S + 0x0500UL)
+#define MDF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x5000UL)
+#define MDF1_Filter0_BASE_S             (MDF1_BASE_S + 0x0080UL)
+#define MDF1_Filter1_BASE_S             (MDF1_BASE_S + 0x0100UL)
+#define MDF1_Filter2_BASE_S             (MDF1_BASE_S + 0x0180UL)
+#define MDF1_Filter3_BASE_S             (MDF1_BASE_S + 0x0200UL)
+#define MDF1_Filter4_BASE_S             (MDF1_BASE_S + 0x0280UL)
+#define MDF1_Filter5_BASE_S             (MDF1_BASE_S + 0x0300UL)
+#define ADF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x6000UL)
+#define ADF1_Filter0_BASE_S             (ADF1_BASE_S + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_S                  (APB3PERIPH_BASE_S + 0x0000UL)
+#define DBGMCU_BASE_S                   (APB3PERIPH_BASE_S + 0x1000UL)
+#define DFT_APB_BASE_S                  (APB3PERIPH_BASE_S + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_S                      (AHB3PERIPH_BASE_S + 0x0000UL)
+#define HASH_BASE_S                     (AHB3PERIPH_BASE_S + 0x0400UL)
+#define HASH_DIGEST_BASE_S              (AHB3PERIPH_BASE_S + 0x0710UL)
+#define PKA_BASE_S                      (AHB3PERIPH_BASE_S + 0x2000UL)
+#define RIFSC_BASE_S                    (AHB3PERIPH_BASE_S + 0x4000UL)
+#define IAC_BASE_S                      (AHB3PERIPH_BASE_S + 0x5000UL)
+#define RISAF1_BASE_S                   (AHB3PERIPH_BASE_S + 0x6000UL)
+#define RISAF2_BASE_S                   (AHB3PERIPH_BASE_S + 0x7000UL)
+#define RISAF3_BASE_S                   (AHB3PERIPH_BASE_S + 0x8000UL)
+#define RISAF4_BASE_S                   (AHB3PERIPH_BASE_S + 0x9000UL)
+#define RISAF5_BASE_S                   (AHB3PERIPH_BASE_S + 0xA000UL)
+#define RISAF6_BASE_S                   (AHB3PERIPH_BASE_S + 0xB000UL)
+#define RISAF7_BASE_S                   (AHB3PERIPH_BASE_S + 0xC000UL)
+#define RISAF8_BASE_S                   (AHB3PERIPH_BASE_S + 0xD000UL)
+#define RISAF9_BASE_S                   (AHB3PERIPH_BASE_S + 0xE000UL)
+#define RISAF11_BASE_S                  (AHB3PERIPH_BASE_S + 0x010000UL)
+#define RISAF12_BASE_S                  (AHB3PERIPH_BASE_S + 0x011000UL)
+#define RISAF13_BASE_S                  (AHB3PERIPH_BASE_S + 0x012000UL)
+#define RISAF14_BASE_S                  (AHB3PERIPH_BASE_S + 0x013000UL)
+#define RISAF15_BASE_S                  (AHB3PERIPH_BASE_S + 0x014000UL)
+#define RISAF21_BASE_S                  (AHB3PERIPH_BASE_S + 0x015000UL)
+#define RISAF22_BASE_S                  (AHB3PERIPH_BASE_S + 0x016000UL)
+#define RISAF23_BASE_S                  (AHB3PERIPH_BASE_S + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_S                      (APB4PERIPH_BASE_S + 0x0800UL)
+#define LPUART1_BASE_S                  (APB4PERIPH_BASE_S + 0x0C00UL)
+#define SPI6_BASE_S                     (APB4PERIPH_BASE_S + 0x1400UL)
+#define I2C4_BASE_S                     (APB4PERIPH_BASE_S + 0x1C00UL)
+#define LPTIM2_BASE_S                   (APB4PERIPH_BASE_S + 0x2400UL)
+#define LPTIM3_BASE_S                   (APB4PERIPH_BASE_S + 0x2800UL)
+#define LPTIM4_BASE_S                   (APB4PERIPH_BASE_S + 0x2C00UL)
+#define LPTIM5_BASE_S                   (APB4PERIPH_BASE_S + 0x3000UL)
+#define VREFBUF_BASE_S                  (APB4PERIPH_BASE_S + 0x3C00UL)
+#define RTC_BASE_S                      (APB4PERIPH_BASE_S + 0x4000UL)
+#define TAMP_BASE_S                     (APB4PERIPH_BASE_S + 0x4400UL)
+#define IWDG_BASE_S                     (APB4PERIPH_BASE_S + 0x4800UL)
+
+#define SERC_BASE_S                     (APB4PERIPH_BASE_S + 0x7C00UL)
+#define SYSCFG_BASE_S                   (APB4PERIPH_BASE_S + 0x8000UL)
+#define BSEC_BASE_S                     (APB4PERIPH_BASE_S + 0x9000UL)
+#define DTS_BASE_S                      (APB4PERIPH_BASE_S + 0xA000UL)
+#define DTS_Sensor0_BASE_S              (DTS_BASE_S + 0x0C0UL)
+#define DTS_Sensor1_BASE_S              (DTS_BASE_S + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_S                    (AHB4PERIPH_BASE_S + 0x0000UL)
+#define GPIOB_BASE_S                    (AHB4PERIPH_BASE_S + 0x0400UL)
+#define GPIOC_BASE_S                    (AHB4PERIPH_BASE_S + 0x0800UL)
+#define GPIOD_BASE_S                    (AHB4PERIPH_BASE_S + 0x0C00UL)
+#define GPIOE_BASE_S                    (AHB4PERIPH_BASE_S + 0x1000UL)
+#define GPIOF_BASE_S                    (AHB4PERIPH_BASE_S + 0x1400UL)
+#define GPIOG_BASE_S                    (AHB4PERIPH_BASE_S + 0x1800UL)
+#define GPIOH_BASE_S                    (AHB4PERIPH_BASE_S + 0x1C00UL)
+#define GPION_BASE_S                    (AHB4PERIPH_BASE_S + 0x3400UL)
+#define GPIOO_BASE_S                    (AHB4PERIPH_BASE_S + 0x3800UL)
+#define GPIOP_BASE_S                    (AHB4PERIPH_BASE_S + 0x3C00UL)
+#define GPIOQ_BASE_S                    (AHB4PERIPH_BASE_S + 0x4000UL)
+#define PWR_BASE_S                      (AHB4PERIPH_BASE_S + 0x4800UL)
+#define CRC_BASE_S                      (AHB4PERIPH_BASE_S + 0x4C00UL)
+#define EXTI_BASE_S                     (AHB4PERIPH_BASE_S + 0x5000UL)
+#define RCC_BASE_S                      (AHB4PERIPH_BASE_S + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_S                     (APB5PERIPH_BASE_S + 0x1000UL)
+#define LTDC_Layer1_BASE_S              (LTDC_BASE_S + 0x0100UL)
+#define LTDC_Layer2_BASE_S              (LTDC_BASE_S + 0x0200UL)
+#define DCMIPP_BASE_S                   (APB5PERIPH_BASE_S + 0x2000UL)
+#define GFXTIM_BASE_S                   (APB5PERIPH_BASE_S + 0x4000UL)
+#define VENC_BASE_S                     (APB5PERIPH_BASE_S + 0x5000UL)
+#define CSI_BASE_S                      (APB5PERIPH_BASE_S + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_S                   (AHB5PERIPH_BASE_S + 0x0000UL)
+#define HPDMA1_Channel0_BASE_S          (HPDMA1_BASE_S + 0x0050UL)
+#define HPDMA1_Channel1_BASE_S          (HPDMA1_BASE_S + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_S          (HPDMA1_BASE_S + 0x0150UL)
+#define HPDMA1_Channel3_BASE_S          (HPDMA1_BASE_S + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_S          (HPDMA1_BASE_S + 0x0250UL)
+#define HPDMA1_Channel5_BASE_S          (HPDMA1_BASE_S + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_S          (HPDMA1_BASE_S + 0x0350UL)
+#define HPDMA1_Channel7_BASE_S          (HPDMA1_BASE_S + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_S          (HPDMA1_BASE_S + 0x0450UL)
+#define HPDMA1_Channel9_BASE_S          (HPDMA1_BASE_S + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_S         (HPDMA1_BASE_S + 0x0550UL)
+#define HPDMA1_Channel11_BASE_S         (HPDMA1_BASE_S + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_S         (HPDMA1_BASE_S + 0x0650UL)
+#define HPDMA1_Channel13_BASE_S         (HPDMA1_BASE_S + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_S         (HPDMA1_BASE_S + 0x0750UL)
+#define HPDMA1_Channel15_BASE_S         (HPDMA1_BASE_S + 0x07D0UL)
+#define DMA2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x1000UL)
+#define JPEG_BASE_S                     (AHB5PERIPH_BASE_S + 0x3000UL)
+#define FMC_R_BASE_S                    (AHB5PERIPH_BASE_S + 0x4000UL)
+#define FMC_Bank1_R_BASE_S              (FMC_R_BASE_S + 0x0000UL)
+#define FMC_Bank1E_R_BASE_S             (FMC_R_BASE_S + 0x0104UL)
+#define FMC_Bank3_R_BASE_S              (FMC_R_BASE_S + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_S            (FMC_R_BASE_S + 0x0140UL)
+#define FMC_Common_R_BASE_S             (FMC_R_BASE_S + 0x0020UL)
+#define XSPI1_BASE_S                    (AHB5PERIPH_BASE_S + 0x5000UL)
+#define PSSI_BASE_S                     (AHB5PERIPH_BASE_S + 0x6400UL)
+#define SDMMC2_BASE_S                   (AHB5PERIPH_BASE_S + 0x6800UL)
+#define DLYB_SDMMC2_BASE_S              (AHB5PERIPH_BASE_S + 0x6C00UL)
+#define SDMMC1_BASE_S                   (AHB5PERIPH_BASE_S + 0x7000UL)
+#define DLYB_SDMMC1_BASE_S              (AHB5PERIPH_BASE_S + 0x8000UL)
+#define DCMI_BASE_S                     (AHB5PERIPH_BASE_S + 0x8400UL)
+#define XSPI2_BASE_S                    (AHB5PERIPH_BASE_S + 0xA000UL)
+#define XSPIM_BASE_S                    (AHB5PERIPH_BASE_S + 0xB400UL)
+#define XSPI3_BASE_S                    (AHB5PERIPH_BASE_S + 0xD000UL)
+#define GFXMMU_BASE_S                   (AHB5PERIPH_BASE_S + 0x010000UL)
+#define GPU2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x014000UL)
+#define GPUCACHE_BASE_S                 (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ICACHE_BASE_S                   (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ETH1_BASE_S                     (AHB5PERIPH_BASE_S + 0x016000UL)
+#define ETH1_MAC_BASE_S                 (ETH1_BASE_S)
+#define USB1_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x020000UL)
+#define USB2_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x060000UL)
+#define CACHEAXI_BASE_S                 (AHB5PERIPH_BASE_S + 0x0BFC00UL)
+#define NPU_BASE_S                      (AHB5PERIPH_BASE_S + 0x0C0000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_S                      (0x56009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_S                    (BOOTROM_BASE_S + 0x0047ECUL)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_declaration
+  * @{
+  */
+#define ADC12_COMMON_NS           ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
+#define ADC1_NS                   ((ADC_TypeDef *) ADC1_BASE_NS)
+#define ADC2_NS                   ((ADC_TypeDef *) ADC2_BASE_NS)
+#define ADF1_NS                   ((MDF_TypeDef *) ADF1_BASE_NS)
+#define ADF1_Filter0_NS           ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS)
+#define BSEC_NS                   ((BSEC_TypeDef *) BSEC_BASE_NS)
+#define CACHEAXI_NS               ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS)
+#define CRC_NS                    ((CRC_TypeDef *) CRC_BASE_NS)
+#define CSI_NS                    ((CSI_TypeDef *) CSI_BASE_NS)
+#define DBGMCU_NS                 ((DBGMCU_TypeDef *) DBGMCU_BASE_NS)
+#define DCMI_NS                   ((DCMI_TypeDef *) DCMI_BASE_NS)
+#define DCMIPP_NS                 ((DCMIPP_TypeDef *) DCMIPP_BASE_NS)
+#define DLYB_SDMMC1_NS            ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
+#define DLYB_SDMMC2_NS            ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
+#define DMA2D_NS                  ((DMA2D_TypeDef *) DMA2D_BASE_NS)
+#define DTS_NS                    ((DTS_TypeDef *) DTS_BASE_NS)
+#define DTS_Sensor0_NS            ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS)
+#define DTS_Sensor1_NS            ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS)
+#define ETH1_NS                   ((ETH_TypeDef *) ETH1_BASE_NS)
+#define EXTI_NS                   ((EXTI_TypeDef *) EXTI_BASE_NS)
+#define FDCAN1_NS                 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
+#define FDCAN2_NS                 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS)
+#define FDCAN3_NS                 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS)
+#define FDCAN_CCU_NS              ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS)
+#define FDCAN_CONFIG_NS           ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
+#define FMC_Bank1E_R_NS           ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
+#define FMC_Bank1_R_NS            ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
+#define FMC_Bank3_R_NS            ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
+#define FMC_Bank5_6_R_NS          ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS)
+#define FMC_Common_R_NS           ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS)
+#define GFXMMU_NS                 ((GFXMMU_TypeDef *) GFXMMU_BASE_NS)
+#define GFXTIM_NS                 ((GFXTIM_TypeDef *) GFXTIM_BASE_NS)
+#define GPDMA1_NS                 ((DMA_TypeDef *) GPDMA1_BASE_NS)
+#define GPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
+#define GPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
+#define GPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
+#define GPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
+#define GPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
+#define GPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
+#define GPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
+#define GPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
+#define GPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
+#define GPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
+#define GPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
+#define GPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
+#define GPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
+#define GPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
+#define GPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
+#define GPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
+#define GPIOA_NS                  ((GPIO_TypeDef *) GPIOA_BASE_NS)
+#define GPIOB_NS                  ((GPIO_TypeDef *) GPIOB_BASE_NS)
+#define GPIOC_NS                  ((GPIO_TypeDef *) GPIOC_BASE_NS)
+#define GPIOD_NS                  ((GPIO_TypeDef *) GPIOD_BASE_NS)
+#define GPIOE_NS                  ((GPIO_TypeDef *) GPIOE_BASE_NS)
+#define GPIOF_NS                  ((GPIO_TypeDef *) GPIOF_BASE_NS)
+#define GPIOG_NS                  ((GPIO_TypeDef *) GPIOG_BASE_NS)
+#define GPIOH_NS                  ((GPIO_TypeDef *) GPIOH_BASE_NS)
+#define GPION_NS                  ((GPIO_TypeDef *) GPION_BASE_NS)
+#define GPIOO_NS                  ((GPIO_TypeDef *) GPIOO_BASE_NS)
+#define GPIOP_NS                  ((GPIO_TypeDef *) GPIOP_BASE_NS)
+#define GPIOQ_NS                  ((GPIO_TypeDef *) GPIOQ_BASE_NS)
+#define HASH_NS                   ((HASH_TypeDef *) HASH_BASE_NS)
+#define HASH_DIGEST_NS            ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
+#define HPDMA1_NS                 ((DMA_TypeDef *) HPDMA1_BASE_NS)
+#define HPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS)
+#define HPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS)
+#define HPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS)
+#define HPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS)
+#define HPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS)
+#define HPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS)
+#define HPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS)
+#define HPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS)
+#define HPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS)
+#define HPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS)
+#define HPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS)
+#define HPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS)
+#define HPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS)
+#define HPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS)
+#define HPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS)
+#define HPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS)
+#define I2C1_NS                   ((I2C_TypeDef *) I2C1_BASE_NS)
+#define I2C2_NS                   ((I2C_TypeDef *) I2C2_BASE_NS)
+#define I2C3_NS                   ((I2C_TypeDef *) I2C3_BASE_NS)
+#define I2C4_NS                   ((I2C_TypeDef *) I2C4_BASE_NS)
+#define I3C1_NS                   ((I3C_TypeDef *) I3C1_BASE_NS)
+#define I3C2_NS                   ((I3C_TypeDef *) I3C2_BASE_NS)
+#define ICACHE_NS                 ((ICACHE_TypeDef *) ICACHE_BASE_NS)
+#define IWDG_NS                   ((IWDG_TypeDef *) IWDG_BASE_NS)
+#define JPEG_NS                   ((JPEG_TypeDef *) JPEG_BASE_NS)
+#define LPTIM1_NS                 ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
+#define LPTIM2_NS                 ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
+#define LPTIM3_NS                 ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
+#define LPTIM4_NS                 ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
+#define LPTIM5_NS                 ((LPTIM_TypeDef *) LPTIM5_BASE_NS)
+#define LPUART1_NS                ((USART_TypeDef *) LPUART1_BASE_NS)
+#define LTDC_NS                   ((LTDC_TypeDef *)LTDC_BASE_NS)
+#define LTDC_Layer1_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS)
+#define LTDC_Layer2_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS)
+#define MDF1_NS                   ((MDF_TypeDef *) MDF1_BASE_NS)
+#define MDF1_Filter0_NS           ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS)
+#define MDF1_Filter1_NS           ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS)
+#define MDF1_Filter2_NS           ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS)
+#define MDF1_Filter3_NS           ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS)
+#define MDF1_Filter4_NS           ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS)
+#define MDF1_Filter5_NS           ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS)
+#define MDIOS_NS                  ((MDIOS_TypeDef *) MDIOS_BASE_NS)
+#define PKA_NS                    ((PKA_TypeDef *) PKA_BASE_NS)
+#define PSSI_NS                   ((PSSI_TypeDef *) PSSI_BASE_NS)
+#define PWR_NS                    ((PWR_TypeDef *) PWR_BASE_NS)
+#define RAMCFG_NS                 ((RAMCFG_TypeDef *) RAMCFG_BASE_NS)
+#define RAMCFG_SRAM1_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS)
+#define RAMCFG_SRAM2_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS)
+#define RAMCFG_SRAM3_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS)
+#define RAMCFG_SRAM4_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS)
+#define RAMCFG_SRAM5_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS)
+#define RAMCFG_SRAM6_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS)
+#define RAMCFG_SRAM1_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS)
+#define RAMCFG_SRAM2_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS)
+#define RAMCFG_VENC_RAM_NS        ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS)
+#define RAMCFG_FLEXRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS)
+#define RCC_NS                    ((RCC_TypeDef *) RCC_BASE_NS)
+#define RIFSC_NS                  ((RIFSC_TypeDef *) RIFSC_BASE_NS)
+#define RISAF1_NS                 ((RISAF_TypeDef *) RISAF1_BASE_NS)
+#define RISAF2_NS                 ((RISAF_TypeDef *) RISAF2_BASE_NS)
+#define RISAF3_NS                 ((RISAF_TypeDef *) RISAF3_BASE_NS)
+#define RISAF4_NS                 ((RISAF_TypeDef *) RISAF4_BASE_NS)
+#define RISAF5_NS                 ((RISAF_TypeDef *) RISAF5_BASE_NS)
+#define RISAF6_NS                 ((RISAF_TypeDef *) RISAF6_BASE_NS)
+#define RISAF7_NS                 ((RISAF_TypeDef *) RISAF7_BASE_NS)
+#define RISAF8_NS                 ((RISAF_TypeDef *) RISAF8_BASE_NS)
+#define RISAF9_NS                 ((RISAF_TypeDef *) RISAF9_BASE_NS)
+#define RISAF11_NS                ((RISAF_TypeDef *) RISAF11_BASE_NS)
+#define RISAF12_NS                ((RISAF_TypeDef *) RISAF12_BASE_NS)
+#define RISAF13_NS                ((RISAF_TypeDef *) RISAF13_BASE_NS)
+#define RISAF14_NS                ((RISAF_TypeDef *) RISAF14_BASE_NS)
+#define RISAF15_NS                ((RISAF_TypeDef *) RISAF15_BASE_NS)
+#define RISAF21_NS                ((RISAF_TypeDef *) RISAF21_BASE_NS)
+#define RISAF22_NS                ((RISAF_TypeDef *) RISAF22_BASE_NS)
+#define RISAF23_NS                ((RISAF_TypeDef *) RISAF23_BASE_NS)
+#define RNG_NS                    ((RNG_TypeDef *) RNG_BASE_NS)
+#define RTC_NS                    ((RTC_TypeDef *) RTC_BASE_NS)
+#define SAI1_NS                   ((SAI_TypeDef *) SAI1_BASE_NS)
+#define SAI1_Block_A_NS           ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS)
+#define SAI1_Block_B_NS           ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS)
+#define SAI2_NS                   ((SAI_TypeDef *) SAI2_BASE_NS)
+#define SAI2_Block_A_NS           ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS)
+#define SAI2_Block_B_NS           ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS)
+#define SDMMC1_NS                 ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
+#define SDMMC2_NS                 ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
+#define SPDIFRX_NS                ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS)
+#define SPI1_NS                   ((SPI_TypeDef *) SPI1_BASE_NS)
+#define SPI2_NS                   ((SPI_TypeDef *) SPI2_BASE_NS)
+#define SPI3_NS                   ((SPI_TypeDef *) SPI3_BASE_NS)
+#define SPI4_NS                   ((SPI_TypeDef *) SPI4_BASE_NS)
+#define SPI5_NS                   ((SPI_TypeDef *) SPI5_BASE_NS)
+#define SPI6_NS                   ((SPI_TypeDef *) SPI6_BASE_NS)
+#define SYSCFG_NS                 ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
+#define TAMP_NS                   ((TAMP_TypeDef *) TAMP_BASE_NS)
+#define TIM1_NS                   ((TIM_TypeDef *) TIM1_BASE_NS)
+#define TIM2_NS                   ((TIM_TypeDef *) TIM2_BASE_NS)
+#define TIM3_NS                   ((TIM_TypeDef *) TIM3_BASE_NS)
+#define TIM4_NS                   ((TIM_TypeDef *) TIM4_BASE_NS)
+#define TIM5_NS                   ((TIM_TypeDef *) TIM5_BASE_NS)
+#define TIM6_NS                   ((TIM_TypeDef *) TIM6_BASE_NS)
+#define TIM7_NS                   ((TIM_TypeDef *) TIM7_BASE_NS)
+#define TIM8_NS                   ((TIM_TypeDef *) TIM8_BASE_NS)
+#define TIM9_NS                   ((TIM_TypeDef *) TIM9_BASE_NS)
+#define TIM10_NS                  ((TIM_TypeDef *) TIM10_BASE_NS)
+#define TIM11_NS                  ((TIM_TypeDef *) TIM11_BASE_NS)
+#define TIM12_NS                  ((TIM_TypeDef *) TIM12_BASE_NS)
+#define TIM13_NS                  ((TIM_TypeDef *) TIM13_BASE_NS)
+#define TIM14_NS                  ((TIM_TypeDef *) TIM14_BASE_NS)
+#define TIM15_NS                  ((TIM_TypeDef *) TIM15_BASE_NS)
+#define TIM16_NS                  ((TIM_TypeDef *) TIM16_BASE_NS)
+#define TIM17_NS                  ((TIM_TypeDef *) TIM17_BASE_NS)
+#define TIM18_NS                  ((TIM_TypeDef *) TIM18_BASE_NS)
+#define UART4_NS                  ((USART_TypeDef *) UART4_BASE_NS)
+#define UART5_NS                  ((USART_TypeDef *) UART5_BASE_NS)
+#define UART7_NS                  ((USART_TypeDef *) UART7_BASE_NS)
+#define UART8_NS                  ((USART_TypeDef *) UART8_BASE_NS)
+#define UART9_NS                  ((USART_TypeDef *) UART9_BASE_NS)
+#define UCPD1_NS                  ((UCPD_TypeDef *) UCPD1_BASE_NS)
+#define USART1_NS                 ((USART_TypeDef *) USART1_BASE_NS)
+#define USART2_NS                 ((USART_TypeDef *) USART2_BASE_NS)
+#define USART3_NS                 ((USART_TypeDef *) USART3_BASE_NS)
+#define USART6_NS                 ((USART_TypeDef *) USART6_BASE_NS)
+#define USART10_NS                ((USART_TypeDef *) USART10_BASE_NS)
+#define USB1_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS)
+#define USB2_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS)
+#define USB1_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS)
+#define USB2_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS)
+#define VENC_NS                   ((VENC_TypeDef *) VENC_BASE_NS)
+#define VREFBUF_NS                ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
+#define WWDG_NS                   ((WWDG_TypeDef *) WWDG_BASE_NS)
+#define XSPI1_NS                  ((XSPI_TypeDef *) XSPI1_BASE_NS)
+#define XSPI2_NS                  ((XSPI_TypeDef *) XSPI2_BASE_NS)
+#define XSPI3_NS                  ((XSPI_TypeDef *) XSPI3_BASE_NS)
+#define XSPIM_NS                  ((XSPIM_TypeDef *) XSPIM_BASE_NS)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON_S            ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
+#define ADC1_S                    ((ADC_TypeDef *) ADC1_BASE_S)
+#define ADC2_S                    ((ADC_TypeDef *) ADC2_BASE_S)
+#define ADF1_S                    ((MDF_TypeDef *) ADF1_BASE_S)
+#define ADF1_Filter0_S            ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S)
+#define BSEC_S                    ((BSEC_TypeDef *) BSEC_BASE_S)
+#define CACHEAXI_S                ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S)
+#define CRC_S                     ((CRC_TypeDef *) CRC_BASE_S)
+#define CSI_S                     ((CSI_TypeDef *) CSI_BASE_S)
+#define DBGMCU_S                  ((DBGMCU_TypeDef *) DBGMCU_BASE_S)
+#define DCMI_S                    ((DCMI_TypeDef *) DCMI_BASE_S)
+#define DCMIPP_S                  ((DCMIPP_TypeDef *) DCMIPP_BASE_S)
+#define DLYB_SDMMC1_S             ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
+#define DLYB_SDMMC2_S             ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
+#define DMA2D_S                   ((DMA2D_TypeDef *) DMA2D_BASE_S)
+#define DTS_S                     ((DTS_TypeDef *) DTS_BASE_S)
+#define DTS_Sensor0_S             ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S)
+#define DTS_Sensor1_S             ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S)
+#define ETH1_S                    ((ETH_TypeDef *) ETH1_BASE_S)
+#define EXTI_S                    ((EXTI_TypeDef *) EXTI_BASE_S)
+#define FDCAN1_S                  ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
+#define FDCAN2_S                  ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S)
+#define FDCAN3_S                  ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S)
+#define FDCAN_CCU_S               ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S)
+#define FDCAN_CONFIG_S            ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
+#define FMC_Bank1E_R_S            ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
+#define FMC_Bank1_R_S             ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
+#define FMC_Bank3_R_S             ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
+#define FMC_Bank5_6_R_S           ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S)
+#define FMC_Common_R_S            ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S)
+#define GFXMMU_S                  ((GFXMMU_TypeDef *) GFXMMU_BASE_S)
+#define GFXTIM_S                  ((GFXTIM_TypeDef *) GFXTIM_BASE_S)
+#define GPDMA1_S                  ((DMA_TypeDef *) GPDMA1_BASE_S)
+#define GPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
+#define GPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
+#define GPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
+#define GPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
+#define GPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
+#define GPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
+#define GPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
+#define GPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
+#define GPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
+#define GPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
+#define GPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
+#define GPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
+#define GPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
+#define GPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
+#define GPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
+#define GPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
+#define GPIOA_S                   ((GPIO_TypeDef *) GPIOA_BASE_S)
+#define GPIOB_S                   ((GPIO_TypeDef *) GPIOB_BASE_S)
+#define GPIOC_S                   ((GPIO_TypeDef *) GPIOC_BASE_S)
+#define GPIOD_S                   ((GPIO_TypeDef *) GPIOD_BASE_S)
+#define GPIOE_S                   ((GPIO_TypeDef *) GPIOE_BASE_S)
+#define GPIOF_S                   ((GPIO_TypeDef *) GPIOF_BASE_S)
+#define GPIOG_S                   ((GPIO_TypeDef *) GPIOG_BASE_S)
+#define GPIOH_S                   ((GPIO_TypeDef *) GPIOH_BASE_S)
+#define GPION_S                   ((GPIO_TypeDef *) GPION_BASE_S)
+#define GPIOO_S                   ((GPIO_TypeDef *) GPIOO_BASE_S)
+#define GPIOP_S                   ((GPIO_TypeDef *) GPIOP_BASE_S)
+#define GPIOQ_S                   ((GPIO_TypeDef *) GPIOQ_BASE_S)
+#define HASH_S                    ((HASH_TypeDef *) HASH_BASE_S)
+#define HASH_DIGEST_S             ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
+#define HPDMA1_S                  ((DMA_TypeDef *) HPDMA1_BASE_S)
+#define HPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S)
+#define HPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S)
+#define HPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S)
+#define HPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S)
+#define HPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S)
+#define HPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S)
+#define HPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S)
+#define HPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S)
+#define HPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S)
+#define HPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S)
+#define HPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S)
+#define HPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S)
+#define HPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S)
+#define HPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S)
+#define HPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S)
+#define HPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S)
+#define I2C1_S                    ((I2C_TypeDef *) I2C1_BASE_S)
+#define I2C2_S                    ((I2C_TypeDef *) I2C2_BASE_S)
+#define I2C3_S                    ((I2C_TypeDef *) I2C3_BASE_S)
+#define I2C4_S                    ((I2C_TypeDef *) I2C4_BASE_S)
+#define I3C1_S                    ((I3C_TypeDef *) I3C1_BASE_S)
+#define I3C2_S                    ((I3C_TypeDef *) I3C2_BASE_S)
+#define IAC_S                     ((IAC_TypeDef *) IAC_BASE_S)
+#define ICACHE_S                  ((ICACHE_TypeDef *) ICACHE_BASE_S)
+#define IWDG_S                    ((IWDG_TypeDef *) IWDG_BASE_S)
+#define JPEG_S                    ((JPEG_TypeDef *) JPEG_BASE_S)
+#define LPTIM1_S                  ((LPTIM_TypeDef *) LPTIM1_BASE_S)
+#define LPTIM2_S                  ((LPTIM_TypeDef *) LPTIM2_BASE_S)
+#define LPTIM3_S                  ((LPTIM_TypeDef *) LPTIM3_BASE_S)
+#define LPTIM4_S                  ((LPTIM_TypeDef *) LPTIM4_BASE_S)
+#define LPTIM5_S                  ((LPTIM_TypeDef *) LPTIM5_BASE_S)
+#define LPUART1_S                 ((USART_TypeDef *) LPUART1_BASE_S)
+#define LTDC_S                    ((LTDC_TypeDef *)LTDC_BASE_S)
+#define LTDC_Layer1_S             ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S)
+#define LTDC_Layer2_S             ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S)
+#define MDF1_S                    ((MDF_TypeDef *) MDF1_BASE_S)
+#define MDF1_Filter0_S            ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S)
+#define MDF1_Filter1_S            ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S)
+#define MDF1_Filter2_S            ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S)
+#define MDF1_Filter3_S            ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S)
+#define MDF1_Filter4_S            ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S)
+#define MDF1_Filter5_S            ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S)
+#define MDIOS_S                   ((MDIOS_TypeDef *) MDIOS_BASE_S)
+#define PKA_S                     ((PKA_TypeDef *) PKA_BASE_S)
+#define PSSI_S                    ((PSSI_TypeDef *) PSSI_BASE_S)
+#define PWR_S                     ((PWR_TypeDef *) PWR_BASE_S)
+#define RAMCFG_S                  ((RAMCFG_TypeDef *) RAMCFG_BASE_S)
+#define RAMCFG_SRAM1_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S)
+#define RAMCFG_SRAM2_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S)
+#define RAMCFG_SRAM3_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S)
+#define RAMCFG_SRAM4_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S)
+#define RAMCFG_SRAM5_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S)
+#define RAMCFG_SRAM6_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S)
+#define RAMCFG_SRAM1_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S)
+#define RAMCFG_SRAM2_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S)
+#define RAMCFG_VENC_RAM_S         ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_S          ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S)
+#define RAMCFG_FLEXRAM_S          ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S)
+#define RCC_S                     ((RCC_TypeDef *) RCC_BASE_S)
+#define RIFSC_S                   ((RIFSC_TypeDef *) RIFSC_BASE_S)
+#define RISAF1_S                  ((RISAF_TypeDef *) RISAF1_BASE_S)
+#define RISAF2_S                  ((RISAF_TypeDef *) RISAF2_BASE_S)
+#define RISAF3_S                  ((RISAF_TypeDef *) RISAF3_BASE_S)
+#define RISAF4_S                  ((RISAF_TypeDef *) RISAF4_BASE_S)
+#define RISAF5_S                  ((RISAF_TypeDef *) RISAF5_BASE_S)
+#define RISAF6_S                  ((RISAF_TypeDef *) RISAF6_BASE_S)
+#define RISAF7_S                  ((RISAF_TypeDef *) RISAF7_BASE_S)
+#define RISAF8_S                  ((RISAF_TypeDef *) RISAF8_BASE_S)
+#define RISAF9_S                  ((RISAF_TypeDef *) RISAF9_BASE_S)
+#define RISAF11_S                 ((RISAF_TypeDef *) RISAF11_BASE_S)
+#define RISAF12_S                 ((RISAF_TypeDef *) RISAF12_BASE_S)
+#define RISAF13_S                 ((RISAF_TypeDef *) RISAF13_BASE_S)
+#define RISAF14_S                 ((RISAF_TypeDef *) RISAF14_BASE_S)
+#define RISAF15_S                 ((RISAF_TypeDef *) RISAF15_BASE_S)
+#define RISAF21_S                 ((RISAF_TypeDef *) RISAF21_BASE_S)
+#define RISAF22_S                 ((RISAF_TypeDef *) RISAF22_BASE_S)
+#define RISAF23_S                 ((RISAF_TypeDef *) RISAF23_BASE_S)
+#define RNG_S                     ((RNG_TypeDef *) RNG_BASE_S)
+#define RTC_S                     ((RTC_TypeDef *) RTC_BASE_S)
+#define SAI1_S                    ((SAI_TypeDef *) SAI1_BASE_S)
+#define SAI1_Block_A_S            ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S)
+#define SAI1_Block_B_S            ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S)
+#define SAI2_S                    ((SAI_TypeDef *) SAI2_BASE_S)
+#define SAI2_Block_A_S            ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S)
+#define SAI2_Block_B_S            ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S)
+#define SDMMC1_S                  ((SDMMC_TypeDef *) SDMMC1_BASE_S)
+#define SDMMC2_S                  ((SDMMC_TypeDef *) SDMMC2_BASE_S)
+#define SPDIFRX_S                 ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S)
+#define SPI1_S                    ((SPI_TypeDef *) SPI1_BASE_S)
+#define SPI2_S                    ((SPI_TypeDef *) SPI2_BASE_S)
+#define SPI3_S                    ((SPI_TypeDef *) SPI3_BASE_S)
+#define SPI4_S                    ((SPI_TypeDef *) SPI4_BASE_S)
+#define SPI5_S                    ((SPI_TypeDef *) SPI5_BASE_S)
+#define SPI6_S                    ((SPI_TypeDef *) SPI6_BASE_S)
+#define SYSCFG_S                  ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
+#define TAMP_S                    ((TAMP_TypeDef *) TAMP_BASE_S)
+#define TIM1_S                    ((TIM_TypeDef *) TIM1_BASE_S)
+#define TIM2_S                    ((TIM_TypeDef *) TIM2_BASE_S)
+#define TIM3_S                    ((TIM_TypeDef *) TIM3_BASE_S)
+#define TIM4_S                    ((TIM_TypeDef *) TIM4_BASE_S)
+#define TIM5_S                    ((TIM_TypeDef *) TIM5_BASE_S)
+#define TIM6_S                    ((TIM_TypeDef *) TIM6_BASE_S)
+#define TIM7_S                    ((TIM_TypeDef *) TIM7_BASE_S)
+#define TIM8_S                    ((TIM_TypeDef *) TIM8_BASE_S)
+#define TIM9_S                    ((TIM_TypeDef *) TIM9_BASE_S)
+#define TIM10_S                   ((TIM_TypeDef *) TIM10_BASE_S)
+#define TIM11_S                   ((TIM_TypeDef *) TIM11_BASE_S)
+#define TIM12_S                   ((TIM_TypeDef *) TIM12_BASE_S)
+#define TIM13_S                   ((TIM_TypeDef *) TIM13_BASE_S)
+#define TIM14_S                   ((TIM_TypeDef *) TIM14_BASE_S)
+#define TIM15_S                   ((TIM_TypeDef *) TIM15_BASE_S)
+#define TIM16_S                   ((TIM_TypeDef *) TIM16_BASE_S)
+#define TIM17_S                   ((TIM_TypeDef *) TIM17_BASE_S)
+#define TIM18_S                   ((TIM_TypeDef *) TIM18_BASE_S)
+#define UART4_S                   ((USART_TypeDef *) UART4_BASE_S)
+#define UART5_S                   ((USART_TypeDef *) UART5_BASE_S)
+#define UART7_S                   ((USART_TypeDef *) UART7_BASE_S)
+#define UART8_S                   ((USART_TypeDef *) UART8_BASE_S)
+#define UART9_S                   ((USART_TypeDef *) UART9_BASE_S)
+#define UCPD1_S                   ((UCPD_TypeDef *) UCPD1_BASE_S)
+#define USART1_S                  ((USART_TypeDef *) USART1_BASE_S)
+#define USART2_S                  ((USART_TypeDef *) USART2_BASE_S)
+#define USART3_S                  ((USART_TypeDef *) USART3_BASE_S)
+#define USART6_S                  ((USART_TypeDef *) USART6_BASE_S)
+#define USART10_S                 ((USART_TypeDef *) USART10_BASE_S)
+#define USB1_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S)
+#define USB2_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S)
+#define USB1_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S)
+#define USB2_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S)
+#define VENC_S                    ((VENC_TypeDef *) VENC_BASE_S)
+#define VREFBUF_S                 ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
+#define WWDG_S                    ((WWDG_TypeDef *) WWDG_BASE_S)
+#define XSPI1_S                   ((XSPI_TypeDef *) XSPI1_BASE_S)
+#define XSPI2_S                   ((XSPI_TypeDef *) XSPI2_BASE_S)
+#define XSPI3_S                   ((XSPI_TypeDef *) XSPI3_BASE_S)
+#define XSPIM_S                   ((XSPIM_TypeDef *) XSPIM_BASE_S)
+#endif
+
+/*!< Peripheral Instance aliases for Non-Secure/Secure execution  */
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON              ADC12_COMMON_S
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_S
+
+#define ADC1                      ADC1_S
+#define ADC1_BASE                 ADC1_BASE_S
+
+#define ADC2                      ADC2_S
+#define ADC2_BASE                 ADC2_BASE_S
+
+#define ADF1                      ADF1_S
+#define ADF1_BASE                 ADF1_BASE_S
+
+#define ADF1_Filter0              ADF1_Filter0_S
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_S
+
+#define BSEC                      BSEC_S
+#define BSEC_BASE                 BSEC_BASE_S
+
+#define CACHEAXI                  CACHEAXI_S
+#define CACHEAXI_BASE             CACHEAXI_BASE_S
+
+#define CRC                       CRC_S
+#define CRC_BASE                  CRC_BASE_S
+
+
+#define CSI                       CSI_S
+#define CSI_BASE                  CSI_BASE_S
+
+#define DBGMCU                    DBGMCU_S
+#define DBGMCU_BASE               DBGMCU_BASE_S
+
+#define DCMI                      DCMI_S
+#define DCMI_BASE                 DCMI_BASE_S
+
+#define DCMIPP                    DCMIPP_S
+#define DCMIPP_BASE               DCMIPP_BASE_S
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_S
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_S
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_S
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_S
+
+#define DMA2D                     DMA2D_S
+#define DMA2D_BASE                DMA2D_BASE_S
+
+#define DTS                       DTS_S
+#define DTS_BASE                  DTS_BASE_S
+
+#define DTS_Sensor0               DTS_Sensor0_S
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_S
+
+#define DTS_Sensor1               DTS_Sensor1_S
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_S
+
+#define ETH1                      ETH1_S
+#define ETH1_BASE                 ETH1_BASE_S
+
+#define EXTI                      EXTI_S
+#define EXTI_BASE                 EXTI_BASE_S
+
+#define FDCAN1                    FDCAN1_S
+#define FDCAN1_BASE               FDCAN1_BASE_S
+
+#define FDCAN2                    FDCAN2_S
+#define FDCAN2_BASE               FDCAN2_BASE_S
+
+#define FDCAN3                    FDCAN3_S
+#define FDCAN3_BASE               FDCAN3_BASE_S
+
+#define FDCAN_CCU                 FDCAN_CCU_S
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_S
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_S
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_S
+
+#define FMC_R_BASE                FMC_R_BASE_S
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_S
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_S
+
+#define FMC_Bank1_R               FMC_Bank1_R_S
+#define FMC_Bank1_R_BASE          FMC_Bank1_R_BASE_S
+
+#define FMC_Bank3_R               FMC_Bank3_R_S
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_S
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_S
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_S
+
+#define FMC_Common_R              FMC_Common_R_S
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_S
+
+#define GFXMMU                       GFXMMU_S
+#define GFXMMU_BASE                  GFXMMU_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_S
+
+#define GFXTIM                    GFXTIM_S
+#define GFXTIM_BASE               GFXTIM_BASE_S
+
+#define GPDMA1                    GPDMA1_S
+#define GPDMA1_BASE               GPDMA1_BASE_S
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_S
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_S
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_S
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_S
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_S
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_S
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_S
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_S
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_S
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_S
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_S
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_S
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_S
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_S
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_S
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_S
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_S
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_S
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_S
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_S
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_S
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_S
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_S
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_S
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_S
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_S
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_S
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_S
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_S
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_S
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_S
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_S
+
+#define GPIOA                     GPIOA_S
+#define GPIOA_BASE                GPIOA_BASE_S
+
+#define GPIOB                     GPIOB_S
+#define GPIOB_BASE                GPIOB_BASE_S
+
+#define GPIOC                     GPIOC_S
+#define GPIOC_BASE                GPIOC_BASE_S
+
+#define GPIOD                     GPIOD_S
+#define GPIOD_BASE                GPIOD_BASE_S
+
+#define GPIOE                     GPIOE_S
+#define GPIOE_BASE                GPIOE_BASE_S
+
+#define GPIOF                     GPIOF_S
+#define GPIOF_BASE                GPIOF_BASE_S
+
+#define GPIOG                     GPIOG_S
+#define GPIOG_BASE                GPIOG_BASE_S
+
+#define GPIOH                     GPIOH_S
+#define GPIOH_BASE                GPIOH_BASE_S
+
+#define GPION                     GPION_S
+#define GPION_BASE                GPION_BASE_S
+
+#define GPIOO                     GPIOO_S
+#define GPIOO_BASE                GPIOO_BASE_S
+
+#define GPIOP                     GPIOP_S
+#define GPIOP_BASE                GPIOP_BASE_S
+
+#define GPIOQ                     GPIOQ_S
+#define GPIOQ_BASE                GPIOQ_BASE_S
+
+#define GPU2D                     GPU2D_BASE_S
+#define GPU2D_BASE                GPU2D_BASE_S
+
+#define HASH                      HASH_S
+#define HASH_BASE                 HASH_BASE_S
+
+#define HASH_DIGEST               HASH_DIGEST_S
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_S
+
+#define HPDMA1                    HPDMA1_S
+#define HPDMA1_BASE               HPDMA1_BASE_S
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_S
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_S
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_S
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_S
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_S
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_S
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_S
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_S
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_S
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_S
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_S
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_S
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_S
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_S
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_S
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_S
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_S
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_S
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_S
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_S
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_S
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_S
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_S
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_S
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_S
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_S
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_S
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_S
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_S
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_S
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_S
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_S
+
+#define I2C1                      I2C1_S
+#define I2C1_BASE                 I2C1_BASE_S
+
+#define I2C2                      I2C2_S
+#define I2C2_BASE                 I2C2_BASE_S
+
+#define I2C3                      I2C3_S
+#define I2C3_BASE                 I2C3_BASE_S
+
+#define I2C4                      I2C4_S
+#define I2C4_BASE                 I2C4_BASE_S
+
+#define I3C1                      I3C1_S
+#define I3C1_BASE                 I3C1_BASE_S
+
+#define I3C2                      I3C2_S
+#define I3C2_BASE                 I3C2_BASE_S
+
+#define IAC                       IAC_S
+#define IAC_BASE                  IAC_BASE_S
+
+#define ICACHE                    ICACHE_S
+#define ICACHE_BASE               ICACHE_BASE_S
+
+#define IWDG                      IWDG_S
+#define IWDG_BASE                 IWDG_BASE_S
+
+#define JPEG                      JPEG_S
+#define JPEG_BASE                 JPEG_BASE_S
+
+#define LPTIM1                    LPTIM1_S
+#define LPTIM1_BASE               LPTIM1_BASE_S
+
+#define LPTIM2                    LPTIM2_S
+#define LPTIM2_BASE               LPTIM2_BASE_S
+
+#define LPTIM3                    LPTIM3_S
+#define LPTIM3_BASE               LPTIM3_BASE_S
+
+#define LPTIM4                    LPTIM4_S
+#define LPTIM4_BASE               LPTIM4_BASE_S
+
+#define LPTIM5                    LPTIM5_S
+#define LPTIM5_BASE               LPTIM5_BASE_S
+
+#define LPUART1                   LPUART1_S
+#define LPUART1_BASE              LPUART1_BASE_S
+
+#define LTDC                      LTDC_S
+#define LTDC_BASE                 LTDC_BASE_S
+
+#define LTDC_Layer1               LTDC_Layer1_S
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_S
+
+#define LTDC_Layer2               LTDC_Layer2_S
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_S
+
+
+#define MDF1                      MDF1_S
+#define MDF1_BASE                 MDF1_BASE_S
+
+#define MDF1_Filter0              MDF1_Filter0_S
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_S
+
+#define MDF1_Filter1              MDF1_Filter1_S
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_S
+
+#define MDF1_Filter2              MDF1_Filter2_S
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_S
+
+#define MDF1_Filter3              MDF1_Filter3_S
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_S
+
+#define MDF1_Filter4              MDF1_Filter4_S
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_S
+
+#define MDF1_Filter5              MDF1_Filter5_S
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_S
+
+#define MDIOS                     MDIOS_S
+#define MDIOS_BASE                MDIOS_BASE_S
+
+#define NPU_PRESENT
+#define NPU_BASE                  NPU_BASE_S
+
+#define PKA                       PKA_S
+#define PKA_BASE                  PKA_BASE_S
+
+#define PSSI                      PSSI_S
+#define PSSI_BASE                 PSSI_BASE_S
+
+#define PWR                       PWR_S
+#define PWR_BASE                  PWR_BASE_S
+
+#define RAMCFG                    RAMCFG_S
+#define RAMCFG_BASE               RAMCFG_BASE_S
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_S
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_S
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_S
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_S
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_S
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_S
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_S
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_S
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_S
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_S
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_S
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_S
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_S
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_S
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_S
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_S
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_S
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_S
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_S
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_S
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_S
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_S
+
+#define RCC                       RCC_S
+#define RCC_BASE                  RCC_BASE_S
+
+#define RIFSC                     RIFSC_S
+#define RIFSC_BASE                RIFSC_BASE_S
+
+#define RISAF1                    RISAF1_S
+#define RISAF1_BASE               RISAF1_BASE_S
+
+#define RISAF2                    RISAF2_S
+#define RISAF2_BASE               RISAF2_BASE_S
+
+#define RISAF3                    RISAF3_S
+#define RISAF3_BASE               RISAF3_BASE_S
+
+#define RISAF4                    RISAF4_S
+#define RISAF4_BASE               RISAF4_BASE_S
+
+#define RISAF5                    RISAF5_S
+#define RISAF5_BASE               RISAF5_BASE_S
+
+#define RISAF6                    RISAF6_S
+#define RISAF6_BASE               RISAF6_BASE_S
+
+#define RISAF7                    RISAF7_S
+#define RISAF7_BASE               RISAF7_BASE_S
+
+#define RISAF8                    RISAF8_S
+#define RISAF8_BASE               RISAF8_BASE_S
+
+#define RISAF9                    RISAF9_S
+#define RISAF9_BASE               RISAF9_BASE_S
+
+#define RISAF11                   RISAF11_S
+#define RISAF11_BASE              RISAF11_BASE_S
+
+#define RISAF12                   RISAF12_S
+#define RISAF12_BASE              RISAF12_BASE_S
+
+#define RISAF13                   RISAF13_S
+#define RISAF13_BASE              RISAF13_BASE_S
+
+#define RISAF14                   RISAF14_S
+#define RISAF14_BASE              RISAF14_BASE_S
+
+#define RISAF15                   RISAF15_S
+#define RISAF15_BASE              RISAF15_BASE_S
+
+#define RISAF21                   RISAF21_S
+#define RISAF21_BASE              RISAF21_BASE_S
+
+#define RISAF22                   RISAF22_S
+#define RISAF22_BASE              RISAF22_BASE_S
+
+#define RISAF23                   RISAF23_S
+#define RISAF23_BASE              RISAF23_BASE_S
+
+#define RNG                       RNG_S
+#define RNG_BASE                  RNG_BASE_S
+
+#define RTC                       RTC_S
+#define RTC_BASE                  RTC_BASE_S
+
+
+#define SAI1                      SAI1_S
+#define SAI1_BASE                 SAI1_BASE_S
+
+#define SAI1_Block_A              SAI1_Block_A_S
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_S
+
+#define SAI1_Block_B              SAI1_Block_B_S
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_S
+
+#define SAI2                      SAI2_S
+#define SAI2_BASE                 SAI2_BASE_S
+
+#define SAI2_Block_A              SAI2_Block_A_S
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_S
+
+#define SAI2_Block_B              SAI2_Block_B_S
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_S
+
+#define SDMMC1                    SDMMC1_S
+#define SDMMC1_BASE               SDMMC1_BASE_S
+
+#define SDMMC2                    SDMMC2_S
+#define SDMMC2_BASE               SDMMC2_BASE_S
+
+#define SPDIFRX                   SPDIFRX_S
+#define SPDIFRX_BASE              SPDIFRX_BASE_S
+
+#define SPI1                      SPI1_S
+#define SPI1_BASE                 SPI1_BASE_S
+
+#define SPI2                      SPI2_S
+#define SPI2_BASE                 SPI2_BASE_S
+
+#define SPI3                      SPI3_S
+#define SPI3_BASE                 SPI3_BASE_S
+
+#define SPI4                      SPI4_S
+#define SPI4_BASE                 SPI4_BASE_S
+
+#define SPI5                      SPI5_S
+#define SPI5_BASE                 SPI5_BASE_S
+
+#define SPI6                      SPI6_S
+#define SPI6_BASE                 SPI6_BASE_S
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_S
+
+#define SYSCFG                    SYSCFG_S
+#define SYSCFG_BASE               SYSCFG_BASE_S
+
+#define TAMP                      TAMP_S
+#define TAMP_BASE                 TAMP_BASE_S
+
+#define TIM1                      TIM1_S
+#define TIM1_BASE                 TIM1_BASE_S
+
+#define TIM2                      TIM2_S
+#define TIM2_BASE                 TIM2_BASE_S
+
+#define TIM3                      TIM3_S
+#define TIM3_BASE                 TIM3_BASE_S
+
+#define TIM4                      TIM4_S
+#define TIM4_BASE                 TIM4_BASE_S
+
+#define TIM5                      TIM5_S
+#define TIM5_BASE                 TIM5_BASE_S
+
+#define TIM6                      TIM6_S
+#define TIM6_BASE                 TIM6_BASE_S
+
+#define TIM7                      TIM7_S
+#define TIM7_BASE                 TIM7_BASE_S
+
+#define TIM8                      TIM8_S
+#define TIM8_BASE                 TIM8_BASE_S
+
+#define TIM9                      TIM9_S
+#define TIM9_BASE                 TIM9_BASE_S
+
+#define TIM10                     TIM10_S
+#define TIM10_BASE                TIM10_BASE_S
+
+#define TIM11                     TIM11_S
+#define TIM11_BASE                TIM11_BASE_S
+
+#define TIM12                     TIM12_S
+#define TIM12_BASE                TIM12_BASE_S
+
+#define TIM13                     TIM13_S
+#define TIM13_BASE                TIM13_BASE_S
+
+#define TIM14                     TIM14_S
+#define TIM14_BASE                TIM14_BASE_S
+
+#define TIM15                     TIM15_S
+#define TIM15_BASE                TIM15_BASE_S
+
+#define TIM16                     TIM16_S
+#define TIM16_BASE                TIM16_BASE_S
+
+#define TIM17                     TIM17_S
+#define TIM17_BASE                TIM17_BASE_S
+
+#define TIM18                     TIM18_S
+#define TIM18_BASE                TIM18_BASE_S
+
+#define UART4                     UART4_S
+#define UART4_BASE                UART4_BASE_S
+
+#define UART5                     UART5_S
+#define UART5_BASE                UART5_BASE_S
+
+#define UART7                     UART7_S
+#define UART7_BASE                UART7_BASE_S
+
+#define UART8                     UART8_S
+#define UART8_BASE                UART8_BASE_S
+
+#define UART9                     UART9_S
+#define UART9_BASE                UART9_BASE_S
+
+#define UCPD1                     UCPD1_S
+#define UCPD1_BASE                UCPD1_BASE_S
+
+#define USART1                    USART1_S
+#define USART1_BASE               USART1_BASE_S
+
+#define USART2                    USART2_S
+#define USART2_BASE               USART2_BASE_S
+
+#define USART3                    USART3_S
+#define USART3_BASE               USART3_BASE_S
+
+#define USART6                    USART6_S
+#define USART6_BASE               USART6_BASE_S
+
+#define USART10                   USART10_S
+#define USART10_BASE              USART10_BASE_S
+
+#define USB1_OTG_HS               USB1_OTG_HS_S
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_S
+
+#define USB2_OTG_HS               USB2_OTG_HS_S
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_S
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_S
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_S
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_S
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_S
+
+#define VENC                      VENC_S
+#define VENC_BASE                 VENC_BASE_S
+
+#define VREFBUF                   VREFBUF_S
+#define VREFBUF_BASE              VREFBUF_BASE_S
+
+#define WWDG                      WWDG_S
+#define WWDG_BASE                 WWDG_BASE_S
+
+#define XSPI1                     XSPI1_S
+
+#define XSPI2                     XSPI2_S
+
+#define XSPI3                     XSPI3_S
+
+#define XSPIM                     XSPIM_S
+#define XSPIM_BASE                XSPIM_BASE_S
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_S
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_S
+
+#else
+
+#define ADC12_COMMON              ADC12_COMMON_NS
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_NS
+
+#define ADC1                      ADC1_NS
+#define ADC1_BASE                 ADC1_BASE_NS
+
+#define ADC2                      ADC2_NS
+#define ADC2_BASE                 ADC2_BASE_NS
+
+#define ADF1                      ADF1_NS
+#define ADF1_BASE                 ADF1_BASE_NS
+
+#define ADF1_Filter0              ADF1_Filter0_NS
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_NS
+
+#define BSEC                      BSEC_NS
+#define BSEC_BASE                 BSEC_BASE_NS
+
+#define CACHEAXI                  CACHEAXI_NS
+#define CACHEAXI_BASE             CACHEAXI_BASE_NS
+
+#define CRC                       CRC_NS
+#define CRC_BASE                  CRC_BASE_NS
+
+
+#define CSI                       CSI_NS
+#define CSI_BASE                  CSI_BASE_NS
+
+#define DBGMCU                    DBGMCU_NS
+#define DBGMCU_BASE               DBGMCU_BASE_NS
+
+#define DCMI                      DCMI_NS
+#define DCMI_BASE                 DCMI_BASE_NS
+
+#define DCMIPP                    DCMIPP_NS
+#define DCMIPP_BASE               DCMIPP_BASE_NS
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_NS
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_NS
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_NS
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_NS
+
+#define DMA2D                     DMA2D_NS
+#define DMA2D_BASE                DMA2D_BASE_NS
+
+#define DTS                       DTS_NS
+#define DTS_BASE                  DTS_BASE_NS
+
+#define DTS_Sensor0               DTS_Sensor0_NS
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_NS
+
+#define DTS_Sensor1               DTS_Sensor1_NS
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_NS
+
+#define ETH1                      ETH1_NS
+#define ETH1_BASE                 ETH1_BASE_NS
+
+#define EXTI                      EXTI_NS
+#define EXTI_BASE                 EXTI_BASE_NS
+
+#define FDCAN1                    FDCAN1_NS
+#define FDCAN1_BASE               FDCAN1_BASE_NS
+
+#define FDCAN2                    FDCAN2_NS
+#define FDCAN2_BASE               FDCAN2_BASE_NS
+
+#define FDCAN3                    FDCAN3_NS
+#define FDCAN3_BASE               FDCAN3_BASE_NS
+
+#define FDCAN_CCU                 FDCAN_CCU_NS
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_NS
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_NS
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_NS
+
+#define FMC_R_BASE                FMC_R_BASE_NS
+#define FMC_R_BASE_BASE           FMC_R_BASE_BASE_NS
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_NS
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_NS
+
+#define FMC_Bank1_R               FMC_Bank1_R_NS
+#define FMC_Bank1_Rv              FMC_Bank1_R_BASE_NS
+
+#define FMC_Bank3_R               FMC_Bank3_R_NS
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_NS
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_NS
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_NS
+
+#define FMC_Common_R              FMC_Common_R_NS
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_NS
+
+#define GFXMMU                       GFXMMU_NS
+#define GFXMMU_BASE                  GFXMMU_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_NS
+
+#define GFXTIM                    GFXTIM_NS
+#define GFXTIM_BASE               GFXTIM_BASE_NS
+
+#define GPDMA1                    GPDMA1_NS
+#define GPDMA1_BASE               GPDMA1_BASE_NS
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_NS
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_NS
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_NS
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_NS
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_NS
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_NS
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_NS
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_NS
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_NS
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_NS
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_NS
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_NS
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_NS
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_NS
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_NS
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_NS
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_NS
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_NS
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_NS
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_NS
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_NS
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_NS
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_NS
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_NS
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_NS
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_NS
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_NS
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_NS
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_NS
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_NS
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_NS
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_NS
+
+#define GPIOA                     GPIOA_NS
+#define GPIOA_BASE                GPIOA_BASE_NS
+
+#define GPIOB                     GPIOB_NS
+#define GPIOB_BASE                GPIOB_BASE_NS
+
+#define GPIOC                     GPIOC_NS
+#define GPIOC_BASE                GPIOC_BASE_NS
+
+#define GPIOD                     GPIOD_NS
+#define GPIOD_BASE                GPIOD_BASE_NS
+
+#define GPIOE                     GPIOE_NS
+#define GPIOE_BASE                GPIOE_BASE_NS
+
+#define GPIOF                     GPIOF_NS
+#define GPIOF_BASE                GPIOF_BASE_NS
+
+#define GPIOG                     GPIOG_NS
+#define GPIOG_BASE                GPIOG_BASE_NS
+
+#define GPIOH                     GPIOH_NS
+#define GPIOH_BASE                GPIOH_BASE_NS
+
+#define GPION                     GPION_NS
+#define GPION_BASE                GPION_BASE_NS
+
+#define GPIOO                     GPIOO_NS
+#define GPIOO_BASE                GPIOO_BASE_NS
+
+#define GPIOP                     GPIOP_NS
+#define GPIOP_BASE                GPIOP_BASE_NS
+
+#define GPIOQ                     GPIOQ_NS
+#define GPIOQ_BASE                GPIOQ_BASE_NS
+
+#define GPU2D                     GPU2D_BASE_NS
+#define GPU2D_BASE                GPU2D_BASE_NS
+
+#define HASH                      HASH_NS
+#define HASH_BASE                 HASH_BASE_NS
+
+#define HASH_DIGEST               HASH_DIGEST_NS
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_NS
+
+#define HPDMA1                    HPDMA1_NS
+#define HPDMA1_BASE               HPDMA1_BASE_NS
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_NS
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_NS
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_NS
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_NS
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_NS
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_NS
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_NS
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_NS
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_NS
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_NS
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_NS
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_NS
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_NS
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_NS
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_NS
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_NS
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_NS
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_NS
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_NS
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_NS
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_NS
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_NS
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_NS
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_NS
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_NS
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_NS
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_NS
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_NS
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_NS
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_NS
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_NS
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_NS
+
+#define I2C1                      I2C1_NS
+#define I2C1_BASE                 I2C1_BASE_NS
+
+#define I2C2                      I2C2_NS
+#define I2C2_BASE                 I2C2_BASE_NS
+
+#define I2C3                      I2C3_NS
+#define I2C3_BASE                 I2C3_BASE_NS
+
+#define I2C4                      I2C4_NS
+#define I2C4_BASE                 I2C4_BASE_NS
+
+#define I3C1                      I3C1_NS
+#define I3C1_BASE                 I3C1_BASE_NS
+
+#define I3C2                      I3C2_NS
+#define I3C2_BASE                 I3C2_BASE_NS
+
+#define ICACHE                    ICACHE_NS
+#define ICACHE_BASE               ICACHE_BASE_NS
+
+#define IWDG                      IWDG_NS
+#define IWDG_BASE                 IWDG_BASE_NS
+
+#define JPEG                      JPEG_NS
+#define JPEG_BASE                 JPEG_BASE_NS
+
+#define LPTIM1                    LPTIM1_NS
+#define LPTIM1_BASE               LPTIM1_BASE_NS
+
+#define LPTIM2                    LPTIM2_NS
+#define LPTIM2_BASE               LPTIM2_BASE_NS
+
+#define LPTIM3                    LPTIM3_NS
+#define LPTIM3_BASE               LPTIM3_BASE_NS
+
+#define LPTIM4                    LPTIM4_NS
+#define LPTIM4_BASE               LPTIM4_BASE_NS
+
+#define LPTIM5                    LPTIM5_NS
+#define LPTIM5_BASE               LPTIM5_BASE_NS
+
+#define LPUART1                   LPUART1_NS
+#define LPUART1_BASE              LPUART1_BASE_NS
+
+#define LTDC                      LTDC_NS
+#define LTDC_BASE                 LTDC_BASE_NS
+
+#define LTDC_Layer1               LTDC_Layer1_NS
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_NS
+
+#define LTDC_Layer2               LTDC_Layer2_NS
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_NS
+
+
+#define MDF1                      MDF1_NS
+#define MDF1_BASE                 MDF1_BASE_NS
+
+#define MDF1_Filter0              MDF1_Filter0_NS
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_NS
+
+#define MDF1_Filter1              MDF1_Filter1_NS
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_NS
+
+#define MDF1_Filter2              MDF1_Filter2_NS
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_NS
+
+#define MDF1_Filter3              MDF1_Filter3_NS
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_NS
+
+#define MDF1_Filter4              MDF1_Filter4_NS
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_NS
+
+#define MDF1_Filter5              MDF1_Filter5_NS
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_NS
+
+#define MDIOS                     MDIOS_NS
+#define MDIOS_BASE                MDIOS_BASE_NS
+
+#define NPU_PRESENT
+#define NPU_BASE                  NPU_BASE_NS
+
+#define PKA                       PKA_NS
+#define PKA_BASE                  PKA_BASE_NS
+
+#define PSSI                      PSSI_NS
+#define PSSI_BASE                 PSSI_BASE_NS
+
+#define PWR                       PWR_NS
+#define PWR_BASE                  PWR_BASE_NS
+
+#define RAMCFG                    RAMCFG_NS
+#define RAMCFG_BASE               RAMCFG_BASE_NS
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_NS
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_NS
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_NS
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_NS
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_NS
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_NS
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_NS
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_NS
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_NS
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_NS
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_NS
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_NS
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_NS
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_NS
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_NS
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_NS
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_NS
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_NS
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_NS
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_NS
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_NS
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_NS
+
+#define RCC                       RCC_NS
+#define RCC_BASE                  RCC_BASE_NS
+
+#define RIFSC                     RIFSC_NS
+#define RIFSC_BASE                RIFSC_BASE_NS
+
+#define RISAF1                    RISAF1_NS
+#define RISAF1_BASE               RISAF1_BASE_NS
+
+#define RISAF2                    RISAF2_NS
+#define RISAF2_BASE               RISAF2_BASE_NS
+
+#define RISAF3                    RISAF3_NS
+#define RISAF3_BASE               RISAF3_BASE_NS
+
+#define RISAF4                    RISAF4_NS
+#define RISAF4_BASE               RISAF4_BASE_NS
+
+#define RISAF5                    RISAF5_NS
+#define RISAF5_BASE               RISAF5_BASE_NS
+
+#define RISAF6                    RISAF6_NS
+#define RISAF6_BASE               RISAF6_BASE_NS
+
+#define RISAF7                    RISAF7_NS
+#define RISAF7_BASE               RISAF7_BASE_NS
+
+#define RISAF8                    RISAF8_NS
+#define RISAF8_BASE               RISAF8_BASE_NS
+
+#define RISAF9                    RISAF9_NS
+#define RISAF9_BASE               RISAF9_BASE_NS
+
+#define RISAF11                   RISAF11_NS
+#define RISAF11_BASE              RISAF11_BASE_NS
+
+#define RISAF12                   RISAF12_NS
+#define RISAF12_BASE              RISAF12_BASE_NS
+
+#define RISAF13                   RISAF13_NS
+#define RISAF13_BASE              RISAF13_BASE_NS
+
+#define RISAF14                   RISAF14_NS
+#define RISAF14_BASE              RISAF14_BASE_NS
+
+#define RISAF15                   RISAF15_NS
+#define RISAF15_BASE              RISAF15_BASE_NS
+
+#define RISAF21                   RISAF21_NS
+#define RISAF21_BASE              RISAF21_BASE_NS
+
+#define RISAF22                   RISAF22_NS
+#define RISAF22_BASE              RISAF22_BASE_NS
+
+#define RISAF23                   RISAF23_NS
+#define RISAF23_BASE              RISAF23_BASE_NS
+
+#define RNG                       RNG_NS
+#define RNG_BASE                  RNG_BASE_NS
+
+#define RTC                       RTC_NS
+#define RTC_BASE                  RTC_BASE_NS
+
+
+#define SAI1                      SAI1_NS
+#define SAI1_BASE                 SAI1_BASE_NS
+
+#define SAI1_Block_A              SAI1_Block_A_NS
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_NS
+
+#define SAI1_Block_B              SAI1_Block_B_NS
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_NS
+
+#define SAI2                      SAI2_NS
+#define SAI2_BASE                 SAI2_BASE_NS
+
+#define SAI2_Block_A              SAI2_Block_A_NS
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_NS
+
+#define SAI2_Block_B              SAI2_Block_B_NS
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_NS
+
+#define SDMMC1                    SDMMC1_NS
+#define SDMMC1_BASE               SDMMC1_BASE_NS
+
+#define SDMMC2                    SDMMC2_NS
+#define SDMMC2_BASE               SDMMC2_BASE_NS
+
+#define SPDIFRX                   SPDIFRX_NS
+#define SPDIFRX_BASE              SPDIFRX_BASE_NS
+
+#define SPI1                      SPI1_NS
+#define SPI1_BASE                 SPI1_BASE_NS
+
+#define SPI2                      SPI2_NS
+#define SPI2_BASE                 SPI2_BASE_NS
+
+#define SPI3                      SPI3_NS
+#define SPI3_BASE                 SPI3_BASE_NS
+
+#define SPI4                      SPI4_NS
+#define SPI4_BASE                 SPI4_BASE_NS
+
+#define SPI5                      SPI5_NS
+#define SPI5_BASE                 SPI5_BASE_NS
+
+#define SPI6                      SPI6_NS
+#define SPI6_BASE                 SPI6_BASE_NS
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_NS
+
+#define SYSCFG                    SYSCFG_NS
+#define SYSCFG_BASE               SYSCFG_BASE_NS
+
+#define TAMP                      TAMP_NS
+#define TAMP_BASE                 TAMP_BASE_NS
+
+#define TIM1                      TIM1_NS
+#define TIM1_BASE                 TIM1_BASE_NS
+
+#define TIM2                      TIM2_NS
+#define TIM2_BASE                 TIM2_BASE_NS
+
+#define TIM3                      TIM3_NS
+#define TIM3_BASE                 TIM3_BASE_NS
+
+#define TIM4                      TIM4_NS
+#define TIM4_BASE                 TIM4_BASE_NS
+
+#define TIM5                      TIM5_NS
+#define TIM5_BASE                 TIM5_BASE_NS
+
+#define TIM6                      TIM6_NS
+#define TIM6_BASE                 TIM6_BASE_NS
+
+#define TIM7                      TIM7_NS
+#define TIM7_BASE                 TIM7_BASE_NS
+
+#define TIM8                      TIM8_NS
+#define TIM8_BASE                 TIM8_BASE_NS
+
+#define TIM9                      TIM9_NS
+#define TIM9_BASE                 TIM9_BASE_NS
+
+#define TIM10                     TIM10_NS
+#define TIM10_BASE                TIM10_BASE_NS
+
+#define TIM11                     TIM11_NS
+#define TIM11_BASE                TIM11_BASE_NS
+
+#define TIM12                     TIM12_NS
+#define TIM12_BASE                TIM12_BASE_NS
+
+#define TIM13                     TIM13_NS
+#define TIM13_BASE                TIM13_BASE_NS
+
+#define TIM14                     TIM14_NS
+#define TIM14_BASE                TIM14_BASE_NS
+
+#define TIM15                     TIM15_NS
+#define TIM15_BASE                TIM15_BASE_NS
+
+#define TIM16                     TIM16_NS
+#define TIM16_BASE                TIM16_BASE_NS
+
+#define TIM17                     TIM17_NS
+#define TIM17_BASE                TIM17_BASE_NS
+
+#define TIM18                     TIM18_NS
+#define TIM18_BASE                TIM18_BASE_NS
+
+#define UART4                     UART4_NS
+#define UART4_BASE                UART4_BASE_NS
+
+#define UART5                     UART5_NS
+#define UART5_BASE                UART5_BASE_NS
+
+#define UART7                     UART7_NS
+#define UART7_BASE                UART7_BASE_NS
+
+#define UART8                     UART8_NS
+#define UART8_BASE                UART8_BASE_NS
+
+#define UART9                     UART9_NS
+#define UART9_BASE                UART9_BASE_NS
+
+#define UCPD1                     UCPD1_NS
+#define UCPD1_BASE                UCPD1_BASE_NS
+
+#define USART1                    USART1_NS
+#define USART1_BASE               USART1_BASE_NS
+
+#define USART2                    USART2_NS
+#define USART2_BASE               USART2_BASE_NS
+
+#define USART3                    USART3_NS
+#define USART3_BASE               USART3_BASE_NS
+
+#define USART6                    USART6_NS
+#define USART6_BASE               USART6_BASE_NS
+
+#define USART10                   USART10_NS
+#define USART10_BASE              USART10_BASE_NS
+
+#define USB1_OTG_HS               USB1_OTG_HS_NS
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_NS
+
+#define USB2_OTG_HS               USB2_OTG_HS_NS
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_NS
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_NS
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_NS
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_NS
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_NS
+
+#define VENC                      VENC_NS
+#define VENC_BASE                 VENC_BASE_NS
+
+#define VREFBUF                   VREFBUF_NS
+#define VREFBUF_BASE              VREFBUF_BASE_NS
+
+#define WWDG                      WWDG_NS
+#define WWDG_BASE                 WWDG_BASE_NS
+
+#define XSPI1                     XSPI1_NS
+
+#define XSPI2                     XSPI2_NS
+
+#define XSPI3                     XSPI3_NS
+
+#define XSPIM                     XSPIM_NS
+#define XSPIM_BASE                XSPIM_BASE_NS
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_NS
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_NS
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Timing_Definition
+  * @{
+  */
+
+#define LSI_STARTUP_TIME                16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter (ADC)                   */
+/*                                                                            */
+/******************************************************************************/
+
+/* Specific device feature definitions */
+#define ADC_MULTIMODE_SUPPORT         /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)
+#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)
+#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)
+#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)
+#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)
+#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)
+#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)
+#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)
+#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)
+#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)
+#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)
+#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)
+#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)
+#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)
+#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)
+#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)
+#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)
+#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)
+#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)
+#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)
+#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)
+#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)
+#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)
+#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)
+#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)
+#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)
+#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_DEEPPWD_Pos             (29U)
+#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)
+#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)
+#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR1 register  ******************/
+#define ADC_CFGR1_DMNGT_Pos            (0U)
+#define ADC_CFGR1_DMNGT_Msk            (0x3UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000003 */
+#define ADC_CFGR1_DMNGT                ADC_CFGR1_DMNGT_Msk                     /*!< ADC data management configuration */
+#define ADC_CFGR1_DMNGT_0              (0x1UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR1_DMNGT_1              (0x2UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000002 */
+
+#define ADC_CFGR1_RES_Pos              (2U)
+#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x0000000C */
+#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
+#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
+
+#define ADC_CFGR1_EXTSEL_Pos           (5U)
+#define ADC_CFGR1_EXTSEL_Msk           (0x1FUL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x000003E0 */
+#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
+#define ADC_CFGR1_EXTSEL_0             (0x01UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_CFGR1_EXTSEL_1             (0x02UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_2             (0x04UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_3             (0x08UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000100 */
+#define ADC_CFGR1_EXTSEL_4             (0x10UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000200 */
+
+#define ADC_CFGR1_EXTEN_Pos            (10U)
+#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
+
+#define ADC_CFGR1_OVRMOD_Pos           (12U)
+#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
+#define ADC_CFGR1_CONT_Pos             (13U)
+#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
+#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR1_AUTDLY_Pos           (14U)
+#define ADC_CFGR1_AUTDLY_Msk           (0x1UL << ADC_CFGR1_AUTDLY_Pos)         /*!< 0x00004000 */
+#define ADC_CFGR1_AUTDLY               ADC_CFGR1_AUTDLY_Msk                    /*!< ADC low power auto wait */
+
+#define ADC_CFGR1_DISCEN_Pos           (16U)
+#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR1_DISCNUM_Pos          (17U)
+#define ADC_CFGR1_DISCNUM_Msk          (0x7UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x000E0000 */
+#define ADC_CFGR1_DISCNUM              ADC_CFGR1_DISCNUM_Msk                   /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR1_DISCNUM_0            (0x1UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00020000 */
+#define ADC_CFGR1_DISCNUM_1            (0x2UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00040000 */
+#define ADC_CFGR1_DISCNUM_2            (0x4UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00080000 */
+
+#define ADC_CFGR1_JDISCEN_Pos          (20U)
+#define ADC_CFGR1_JDISCEN_Msk          (0x1UL << ADC_CFGR1_JDISCEN_Pos)        /*!< 0x00100000 */
+#define ADC_CFGR1_JDISCEN              ADC_CFGR1_JDISCEN_Msk                   /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CFGR1_AWD1SGL_Pos          (22U)
+#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
+#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR1_AWD1EN_Pos           (23U)
+#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
+#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR1_JAWD1EN_Pos          (24U)
+#define ADC_CFGR1_JAWD1EN_Msk          (0x1UL << ADC_CFGR1_JAWD1EN_Pos)        /*!< 0x01000000 */
+#define ADC_CFGR1_JAWD1EN              ADC_CFGR1_JAWD1EN_Msk                   /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR1_JAUTO_Pos            (25U)
+#define ADC_CFGR1_JAUTO_Msk            (0x1UL << ADC_CFGR1_JAUTO_Pos)          /*!< 0x02000000 */
+#define ADC_CFGR1_JAUTO                ADC_CFGR1_JAUTO_Msk                     /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR1_AWD1CH_Pos           (26U)
+#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
+#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
+#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
+#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
+#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
+#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)
+#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)
+#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)
+#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)
+#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)
+#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+#define ADC_CFGR2_BULB_Pos             (13U)
+#define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)            /*!< 0x00002000 */
+#define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                       /*!< ADC bulb sampling mode */
+
+#define ADC_CFGR2_SWTRIG_Pos           (14U)
+#define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)          /*!< 0x00004000 */
+#define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                     /*!< ADC software trigger bit for sampling time control trigger mode */
+
+#define ADC_CFGR2_SMPTRIG_Pos          (15U)
+#define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)         /*!< 0x00008000 */
+#define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                    /*!< ADC sampling time control trigger mode */
+
+#define ADC_CFGR2_OVSR_Pos             (16U)
+#define ADC_CFGR2_OVSR_Msk             (0x3FFUL << ADC_CFGR2_OVSR_Pos)          /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                       /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x001UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1               (0x002UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2               (0x004UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3               (0x008UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4               (0x010UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5               (0x020UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6               (0x040UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7               (0x080UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8               (0x100UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9               (0x200UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos           (28U)
+#define ADC_CFGR2_LSHIFT_Msk           (0xFUL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT               ADC_CFGR2_LSHIFT_Msk                     /*!< ADC left shift factor */
+#define ADC_CFGR2_LSHIFT_0             (0x1UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1             (0x2UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2             (0x4UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3             (0x8UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)
+#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)
+#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)
+#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)
+#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)
+#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)
+#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)
+#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)
+#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)
+#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)
+#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)
+#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)
+#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)
+#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)
+#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)
+#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)
+#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)
+#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)
+#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)
+#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos            (27U)
+#define ADC_SMPR2_SMP19_Msk            (0x7UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                ADC_SMPR2_SMP19_Msk                     /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0              (0x1UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1              (0x2UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2              (0x4UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  *****************/
+#define ADC_PCSEL_PCSEL_Pos            (0U)
+#define ADC_PCSEL_PCSEL_Msk            (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                ADC_PCSEL_PCSEL_Msk                   /*!< ADC channel preselection */
+#define ADC_PCSEL_PCSEL_0              (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1              (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2              (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3              (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4              (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5              (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6              (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7              (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8              (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9              (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10             (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11             (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12             (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13             (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14             (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15             (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16             (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17             (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18             (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19             (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)
+#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)
+#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)
+#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)
+#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)
+#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)
+#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)
+#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)
+#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)
+#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)
+#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)
+#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)
+#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)
+#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)
+#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)
+#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)
+#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)
+#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)
+#define ADC_DR_RDATA_Msk               (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)      /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x00000001UL << ADC_DR_RDATA_Pos)      /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x00000002UL << ADC_DR_RDATA_Pos)      /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x00000004UL << ADC_DR_RDATA_Pos)      /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x00000008UL << ADC_DR_RDATA_Pos)      /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x00000010UL << ADC_DR_RDATA_Pos)      /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x00000020UL << ADC_DR_RDATA_Pos)      /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x00000040UL << ADC_DR_RDATA_Pos)      /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x00000080UL << ADC_DR_RDATA_Pos)      /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x00000100UL << ADC_DR_RDATA_Pos)      /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x00000200UL << ADC_DR_RDATA_Pos)      /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x00000400UL << ADC_DR_RDATA_Pos)      /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x00000800UL << ADC_DR_RDATA_Pos)      /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x00001000UL << ADC_DR_RDATA_Pos)      /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x00002000UL << ADC_DR_RDATA_Pos)      /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x00004000UL << ADC_DR_RDATA_Pos)      /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x00008000UL << ADC_DR_RDATA_Pos)      /*!< 0x00008000 */
+#define ADC_DR_RDATA_16                (0x00010000UL << ADC_DR_RDATA_Pos)      /*!< 0x00010000 */
+#define ADC_DR_RDATA_17                (0x00020000UL << ADC_DR_RDATA_Pos)      /*!< 0x00020000 */
+#define ADC_DR_RDATA_18                (0x00040000UL << ADC_DR_RDATA_Pos)      /*!< 0x00040000 */
+#define ADC_DR_RDATA_19                (0x00080000UL << ADC_DR_RDATA_Pos)      /*!< 0x00080000 */
+#define ADC_DR_RDATA_20                (0x00100000UL << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
+#define ADC_DR_RDATA_21                (0x00200000UL << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
+#define ADC_DR_RDATA_22                (0x00400000UL << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
+#define ADC_DR_RDATA_23                (0x00800000UL << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
+#define ADC_DR_RDATA_24                (0x01000000UL << ADC_DR_RDATA_Pos)      /*!< 0x01000000 */
+#define ADC_DR_RDATA_25                (0x02000000UL << ADC_DR_RDATA_Pos)      /*!< 0x02000000 */
+#define ADC_DR_RDATA_26                (0x04000000UL << ADC_DR_RDATA_Pos)      /*!< 0x04000000 */
+#define ADC_DR_RDATA_27                (0x08000000UL << ADC_DR_RDATA_Pos)      /*!< 0x08000000 */
+#define ADC_DR_RDATA_28                (0x10000000UL << ADC_DR_RDATA_Pos)      /*!< 0x10000000 */
+#define ADC_DR_RDATA_29                (0x20000000UL << ADC_DR_RDATA_Pos)      /*!< 0x20000000 */
+#define ADC_DR_RDATA_30                (0x40000000UL << ADC_DR_RDATA_Pos)      /*!< 0x40000000 */
+#define ADC_DR_RDATA_31                (0x80000000UL << ADC_DR_RDATA_Pos)      /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)
+#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)
+#define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x01UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x02UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x04UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x08UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos            (7U)
+#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos              (9U)
+#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos              (15U)
+#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos              (21U)
+#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (27U)
+#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR1 register  ***************/
+#define ADC_OFCFGR1_POSOFF_Pos         (24U)
+#define ADC_OFCFGR1_POSOFF_Msk         (0x01UL << ADC_OFCFGR1_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR1_POSOFF             ADC_OFCFGR1_POSOFF_Msk                  /*!< ADC offset instance 1 positive offset enable */
+
+#define ADC_OFCFGR1_USAT_Pos           (25U)
+#define ADC_OFCFGR1_USAT_Msk           (0x01UL << ADC_OFCFGR1_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR1_USAT               ADC_OFCFGR1_USAT_Msk                    /*!< ADC offset instance 1  unsigned saturation value */
+
+#define ADC_OFCFGR1_SSAT_Pos           (26U)
+#define ADC_OFCFGR1_SSAT_Msk           (0x01UL << ADC_OFCFGR1_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR1_SSAT               ADC_OFCFGR1_SSAT_Msk                    /*!< ADC offset instance 1 signed satuaration enable */
+
+#define ADC_OFCFGR1_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR1_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR1_OFFSET_CH          ADC_OFCFGR1_OFFSET_CH_Msk               /*!< ADC offset instance 1 channel selection */
+#define ADC_OFCFGR1_OFFSET_CH_0        (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR1_OFFSET_CH_1        (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR1_OFFSET_CH_2        (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR1_OFFSET_CH_3        (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR1_OFFSET_CH_4        (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR2 register  ***************/
+#define ADC_OFCFGR2_POSOFF_Pos         (24U)
+#define ADC_OFCFGR2_POSOFF_Msk         (0x01UL << ADC_OFCFGR2_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR2_POSOFF             ADC_OFCFGR2_POSOFF_Msk                  /*!< ADC offset instance 2 positive offset enable */
+
+#define ADC_OFCFGR2_USAT_Pos           (25U)
+#define ADC_OFCFGR2_USAT_Msk           (0x01UL << ADC_OFCFGR2_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR2_USAT               ADC_OFCFGR2_USAT_Msk                    /*!< ADC offset instance 2 unsigned saturation value */
+
+#define ADC_OFCFGR2_SSAT_Pos           (26U)
+#define ADC_OFCFGR2_SSAT_Msk           (0x01UL << ADC_OFCFGR2_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR2_SSAT               ADC_OFCFGR2_SSAT_Msk                    /*!< ADC offset instance 2 signed satuaration enable */
+
+#define ADC_OFCFGR2_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR2_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR2_OFFSET_CH          ADC_OFCFGR2_OFFSET_CH_Msk               /*!< ADC offset instance 2 channel selection */
+#define ADC_OFCFGR2_OFFSET_CH_0        (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR2_OFFSET_CH_1        (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR2_OFFSET_CH_2        (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR2_OFFSET_CH_3        (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR2_OFFSET_CH_4        (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR3 register  ***************/
+#define ADC_OFCFGR3_POSOFF_Pos         (24U)
+#define ADC_OFCFGR3_POSOFF_Msk         (0x01UL << ADC_OFCFGR3_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR3_POSOFF             ADC_OFCFGR3_POSOFF_Msk                  /*!< ADC offset instance 3 positive offset enable */
+
+#define ADC_OFCFGR3_USAT_Pos           (25U)
+#define ADC_OFCFGR3_USAT_Msk           (0x01UL << ADC_OFCFGR3_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR3_USAT               ADC_OFCFGR3_USAT_Msk                    /*!< ADC offset instance 3 unsigned saturation value */
+
+#define ADC_OFCFGR3_SSAT_Pos           (26U)
+#define ADC_OFCFGR3_SSAT_Msk           (0x01UL << ADC_OFCFGR3_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR3_SSAT               ADC_OFCFGR3_SSAT_Msk                    /*!< ADC offset instance 3 signed satuaration enable */
+
+#define ADC_OFCFGR3_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR3_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR3_OFFSET_CH          ADC_OFCFGR3_OFFSET_CH_Msk               /*!< ADC offset instance 3 channel selection for the data offset */
+#define ADC_OFCFGR3_OFFSET_CH_0        (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR3_OFFSET_CH_1        (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR3_OFFSET_CH_2        (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR3_OFFSET_CH_3        (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR3_OFFSET_CH_4        (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR4 register  ***************/
+#define ADC_OFCFGR4_POSOFF_Pos         (24U)
+#define ADC_OFCFGR4_POSOFF_Msk         (0x01UL << ADC_OFCFGR4_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR4_POSOFF             ADC_OFCFGR4_POSOFF_Msk                  /*!< ADC offset instance 4 positive offset enable */
+
+#define ADC_OFCFGR4_USAT_Pos           (25U)
+#define ADC_OFCFGR4_USAT_Msk           (0x01UL << ADC_OFCFGR4_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR4_USAT               ADC_OFCFGR4_USAT_Msk                    /*!< ADC offset instance 4 unsigned saturation value */
+
+#define ADC_OFCFGR4_SSAT_Pos           (26U)
+#define ADC_OFCFGR4_SSAT_Msk           (0x01UL << ADC_OFCFGR4_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR4_SSAT               ADC_OFCFGR4_SSAT_Msk                    /*!< ADC offset instance 4 signed satuaration enable */
+
+#define ADC_OFCFGR4_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR4_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR4_OFFSET_CH          ADC_OFCFGR4_OFFSET_CH_Msk               /*!< ADC offset instance 4 channel selection for the data offset */
+#define ADC_OFCFGR4_OFFSET_CH_0        (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR4_OFFSET_CH_1        (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR4_OFFSET_CH_2        (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR4_OFFSET_CH_3        (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR4_OFFSET_CH_4        (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET_Pos            (0U)
+#define ADC_OFR1_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR1_OFFSET                ADC_OFR1_OFFSET_Msk                     /*!< ADC offset instance 1 offset level */
+#define ADC_OFR1_OFFSET_0              (0x0000001UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET_1              (0x0000002UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET_2              (0x0000004UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET_3              (0x0000008UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET_4              (0x0000010UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET_5              (0x0000020UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET_6              (0x0000040UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET_7              (0x0000080UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET_8              (0x0000100UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET_9              (0x0000200UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET_10             (0x0000400UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET_11             (0x0000800UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET_12             (0x0001000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET_13             (0x0002000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET_14             (0x0004000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET_15             (0x0008000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET_16             (0x0010000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET_17             (0x0020000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET_18             (0x0040000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET_19             (0x0080000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET_20             (0x0100000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET_21             (0x0200000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET_Pos            (0U)
+#define ADC_OFR2_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR2_OFFSET                ADC_OFR2_OFFSET_Msk                     /*!< ADC offset instance 2 offset level */
+#define ADC_OFR2_OFFSET_0              (0x0000001UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET_1              (0x0000002UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET_2              (0x0000004UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET_3              (0x0000008UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET_4              (0x0000010UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET_5              (0x0000020UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET_6              (0x0000040UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET_7              (0x0000080UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET_8              (0x0000100UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET_9              (0x0000200UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET_10             (0x0000400UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET_11             (0x0000800UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET_12             (0x0001000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET_13             (0x0002000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET_14             (0x0004000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET_15             (0x0008000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET_16             (0x0010000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET_17             (0x0020000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET_18             (0x0040000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET_19             (0x0080000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET_20             (0x0100000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET_21             (0x0200000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET_Pos            (0U)
+#define ADC_OFR3_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR3_OFFSET                ADC_OFR3_OFFSET_Msk                     /*!< ADC offset instance 3 offset level */
+#define ADC_OFR3_OFFSET_0              (0x0000001UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET_1              (0x0000002UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET_2              (0x0000004UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET_3              (0x0000008UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET_4              (0x0000010UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET_5              (0x0000020UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET_6              (0x0000040UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET_7              (0x0000080UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET_8              (0x0000100UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET_9              (0x0000200UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET_10             (0x0000400UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET_11             (0x0000800UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET_12             (0x0001000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET_13             (0x0002000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET_14             (0x0004000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET_15             (0x0008000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET_16             (0x0010000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET_17             (0x0020000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET_18             (0x0040000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET_19             (0x0080000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET_20             (0x0100000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET_21             (0x0200000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET_Pos            (0U)
+#define ADC_OFR4_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR4_OFFSET                ADC_OFR4_OFFSET_Msk                     /*!< ADC offset instance 4 offset level */
+#define ADC_OFR4_OFFSET_0              (0x0000001UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET_1              (0x0000002UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET_2              (0x0000004UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET_3              (0x0000008UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET_4              (0x0000010UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET_5              (0x0000020UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET_6              (0x0000040UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET_7              (0x0000080UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET_8              (0x0000100UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET_9              (0x0000200UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET_10             (0x0000400UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET_11             (0x0000800UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET_12             (0x0001000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET_13             (0x0002000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET_14             (0x0004000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET_15             (0x0008000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET_16             (0x0010000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET_17             (0x0020000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET_18             (0x0040000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET_19             (0x0080000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET_20             (0x0100000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET_21             (0x0200000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_GCOMP register  *****************/
+#define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
+#define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< Gain compensation coefficient */
+#define ADC_GCOMP_GCOMP_Pos            (31U)
+#define ADC_GCOMP_GCOMP_Msk            (0x1UL << ADC_GCOMP_GCOMP_Pos)          /*!< 0x80000000 */
+#define ADC_GCOMP_GCOMP                ADC_GCOMP_GCOMP_Msk                     /*!< Gain compensation mode */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)
+#define ADC_JDR1_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x00000001UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x00000002UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x00000004UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x00000008UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x00000010UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x00000020UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x00000040UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x00000080UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x00000100UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x00000200UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x00000400UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x00000800UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x00001000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x00002000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x00004000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x00008000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16              (0x00010000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17              (0x00020000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18              (0x00040000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19              (0x00080000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20              (0x00100000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21              (0x00200000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22              (0x00400000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23              (0x00800000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24              (0x01000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25              (0x02000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26              (0x04000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27              (0x08000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28              (0x10000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29              (0x20000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30              (0x40000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31              (0x80000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos             (0U)
+#define ADC_JDR2_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x00000001UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x00000002UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x00000004UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x00000008UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x00000010UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x00000020UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x00000040UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x00000080UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x00000100UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x00000200UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x00000400UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x00000800UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x00001000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x00002000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x00004000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x00008000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16              (0x00010000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17              (0x00020000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18              (0x00040000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19              (0x00080000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20              (0x00100000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21              (0x00200000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22              (0x00400000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23              (0x00800000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24              (0x01000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25              (0x02000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26              (0x04000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27              (0x08000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28              (0x10000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29              (0x20000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30              (0x40000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31              (0x80000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos             (0U)
+#define ADC_JDR3_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x00000001UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x00000002UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x00000004UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x00000008UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x00000010UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x00000020UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x00000040UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x00000080UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x00000100UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x00000200UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x00000400UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x00000800UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x00001000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x00002000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x00004000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x00008000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16              (0x00010000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17              (0x00020000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18              (0x00040000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19              (0x00080000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20              (0x00100000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21              (0x00200000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22              (0x00400000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23              (0x00800000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24              (0x01000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25              (0x02000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26              (0x04000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27              (0x08000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28              (0x10000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29              (0x20000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30              (0x40000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31              (0x80000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos             (0U)
+#define ADC_JDR4_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x00000001UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x00000002UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x00000004UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x00000008UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x00000010UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x00000020UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x00000040UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x00000080UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x00000100UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x00000200UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x00000400UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x00000800UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x00001000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x00002000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x00004000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x00008000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16              (0x00010000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17              (0x00020000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18              (0x00040000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19              (0x00080000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20              (0x00100000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21              (0x00200000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22              (0x00400000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23              (0x00800000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24              (0x01000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25              (0x02000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26              (0x04000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27              (0x08000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28              (0x10000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29              (0x20000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30              (0x40000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31              (0x80000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)
+#define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)
+#define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19           (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD1TR_LT register  *************/
+#define ADC_AWD1LTR_LTR_Pos            (0U)
+#define ADC_AWD1LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1LTR_LTR                ADC_AWD1LTR_LTR_Msk                    /*!< ADC analog watchdog 1 threshold low */
+#define ADC_AWD1LTR_LTR_0              (0x000001UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1LTR_LTR_1              (0x000002UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1LTR_LTR_2              (0x000004UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1LTR_LTR_3              (0x000008UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1LTR_LTR_4              (0x000010UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1LTR_LTR_5              (0x000020UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1LTR_LTR_6              (0x000040UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1LTR_LTR_7              (0x000080UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1LTR_LTR_8              (0x000100UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1LTR_LTR_9              (0x000200UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1LTR_LTR_10             (0x000400UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1LTR_LTR_11             (0x000800UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1LTR_LTR_12             (0x001000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1LTR_LTR_13             (0x002000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1LTR_LTR_14             (0x004000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1LTR_LTR_15             (0x008000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1LTR_LTR_16             (0x010000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1LTR_LTR_17             (0x020000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1LTR_LTR_18             (0x040000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1LTR_LTR_19             (0x080000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1LTR_LTR_20             (0x100000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1LTR_LTR_21             (0x200000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1LTR_LTR_22             (0x400000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD1TR_HT register  *******************/
+#define ADC_AWD1HTR_HTR_Pos            (0U)
+#define ADC_AWD1HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1HTR_HTR                ADC_AWD1HTR_HTR_Msk                    /*!< ADC analog watchdog 1 threshold high */
+#define ADC_AWD1HTR_HTR_0              (0x000001UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1HTR_HTR_1              (0x000002UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1HTR_HTR_2              (0x000004UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1HTR_HTR_3              (0x000008UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1HTR_HTR_4              (0x000010UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1HTR_HTR_5              (0x000020UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1HTR_HTR_6              (0x000040UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1HTR_HTR_7              (0x000080UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1HTR_HTR_8              (0x000100UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1HTR_HTR_9              (0x000200UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1HTR_HTR_10             (0x000400UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1HTR_HTR_11             (0x000800UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1HTR_HTR_12             (0x001000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1HTR_HTR_13             (0x002000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1HTR_HTR_14             (0x004000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1HTR_HTR_15             (0x008000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1HTR_HTR_16             (0x010000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1HTR_HTR_17             (0x020000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1HTR_HTR_18             (0x040000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1HTR_HTR_19             (0x080000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1HTR_HTR_20             (0x100000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1HTR_HTR_21             (0x200000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1HTR_HTR_22             (0x400000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00400000 */
+
+#define ADC_AWD1HTR_AWDFILT_Pos         (29U)
+#define ADC_AWD1HTR_AWDFILT_Msk         (0x7UL << ADC_AWD1HTR_AWDFILT_Pos)      /*!< 0x00000007 */
+#define ADC_AWD1HTR_AWDFILT             ADC_AWD1HTR_AWDFILT_Msk                 /*!< ADC analog watchdog 1 filtering */
+#define ADC_AWD1HTR_AWDFILT_0           (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */
+#define ADC_AWD1HTR_AWDFILT_1           (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */
+#define ADC_AWD1HTR_AWDFILT_2           (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */
+
+/********************  Bit definition for ADC_AWD2TR_LT register  *******************/
+#define ADC_AWD2LTR_LTR_Pos            (0U)
+#define ADC_AWD2LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2LTR_LTR                ADC_AWD2LTR_LTR_Msk                    /*!< ADC analog watchdog 2 threshold low */
+#define ADC_AWD2LTR_LTR_0              (0x000001UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2LTR_LTR_1              (0x000002UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2LTR_LTR_2              (0x000004UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2LTR_LTR_3              (0x000008UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2LTR_LTR_4              (0x000010UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2LTR_LTR_5              (0x000020UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2LTR_LTR_6              (0x000040UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2LTR_LTR_7              (0x000080UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2LTR_LTR_8              (0x000100UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2LTR_LTR_9              (0x000200UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2LTR_LTR_10             (0x000400UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2LTR_LTR_11             (0x000800UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2LTR_LTR_12             (0x001000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2LTR_LTR_13             (0x002000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2LTR_LTR_14             (0x004000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2LTR_LTR_15             (0x008000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2LTR_LTR_16             (0x010000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2LTR_LTR_17             (0x020000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2LTR_LTR_18             (0x040000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2LTR_LTR_19             (0x080000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2LTR_LTR_20             (0x100000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2LTR_LTR_21             (0x200000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2LTR_LTR_22             (0x400000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD2TR_HT register  *******************/
+#define ADC_AWD2HTR_HTR_Pos            (0U)
+#define ADC_AWD2HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2HTR_HTR                ADC_AWD2HTR_HTR_Msk                    /*!< ADC analog watchdog 2 threshold high */
+#define ADC_AWD2HTR_HTR_0              (0x000001UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2HTR_HTR_1              (0x000002UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2HTR_HTR_2              (0x000004UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2HTR_HTR_3              (0x000008UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2HTR_HTR_4              (0x000010UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2HTR_HTR_5              (0x000020UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2HTR_HTR_6              (0x000040UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2HTR_HTR_7              (0x000080UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2HTR_HTR_8              (0x000100UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2HTR_HTR_9              (0x000200UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2HTR_HTR_10             (0x000400UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2HTR_HTR_11             (0x000800UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2HTR_HTR_12             (0x001000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2HTR_HTR_13             (0x002000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2HTR_HTR_14             (0x004000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2HTR_HTR_15             (0x008000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2HTR_HTR_16             (0x010000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2HTR_HTR_17             (0x020000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2HTR_HTR_18             (0x040000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2HTR_HTR_19             (0x080000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2HTR_HTR_20             (0x100000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2HTR_HTR_21             (0x200000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2HTR_HTR_22             (0x400000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_LT register  *******************/
+#define ADC_AWD3LTR_LTR_Pos            (0U)
+#define ADC_AWD3LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3LTR_LTR                ADC_AWD3LTR_LTR_Msk                    /*!< ADC analog watchdog 3 threshold low */
+#define ADC_AWD3LTR_LTR_0              (0x000001UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3LTR_LTR_1              (0x000002UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3LTR_LTR_2              (0x000004UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3LTR_LTR_3              (0x000008UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3LTR_LTR_4              (0x000010UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3LTR_LTR_5              (0x000020UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3LTR_LTR_6              (0x000040UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3LTR_LTR_7              (0x000080UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3LTR_LTR_8              (0x000100UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3LTR_LTR_9              (0x000200UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3LTR_LTR_10             (0x000400UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3LTR_LTR_11             (0x000800UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3LTR_LTR_12             (0x001000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3LTR_LTR_13             (0x002000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3LTR_LTR_14             (0x004000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3LTR_LTR_15             (0x008000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3LTR_LTR_16             (0x010000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3LTR_LTR_17             (0x020000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3LTR_LTR_18             (0x040000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3LTR_LTR_19             (0x080000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3LTR_LTR_20             (0x100000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3LTR_LTR_21             (0x200000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3LTR_LTR_22             (0x400000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_HT register  *******************/
+#define ADC_AWD3HTR_HTR_Pos            (0U)
+#define ADC_AWD3HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3HTR_HTR                ADC_AWD3HTR_HTR_Msk                    /*!< ADC analog watchdog 3 threshold high */
+#define ADC_AWD3HTR_HTR_0              (0x000001UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3HTR_HTR_1              (0x000002UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3HTR_HTR_2              (0x000004UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3HTR_HTR_3              (0x000008UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3HTR_HTR_4              (0x000010UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3HTR_HTR_5              (0x000020UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3HTR_HTR_6              (0x000040UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3HTR_HTR_7              (0x000080UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3HTR_HTR_8              (0x000100UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3HTR_HTR_9              (0x000200UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3HTR_HTR_10             (0x000400UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3HTR_HTR_11             (0x000800UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3HTR_HTR_12             (0x001000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3HTR_HTR_13             (0x002000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3HTR_HTR_14             (0x004000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3HTR_HTR_15             (0x008000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3HTR_HTR_16             (0x010000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3HTR_HTR_17             (0x020000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3HTR_HTR_18             (0x040000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3HTR_HTR_19             (0x080000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3HTR_HTR_20             (0x100000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3HTR_HTR_21             (0x200000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3HTR_HTR_22             (0x400000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)
+#define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode selection */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)
+#define ADC_CALFACT_CALFACT_S_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos)  /*!< 0x000003FF */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7        (0x80UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8        (0x100UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9        (0x200UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000200 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)
+#define ADC_CALFACT_CALFACT_D_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos)  /*!< 0x03FF0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7        (0x80UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8        (0x100UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9        (0x200UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x02000000 */
+
+#define ADC_CALFACT_CALADDOS_Pos       (31U)
+#define ADC_CALFACT_CALADDOS_Msk       (0x01UL << ADC_CALFACT_CALADDOS_Pos)    /*!< 0x80000000 */
+#define ADC_CALFACT_CALADDOS           ADC_CALFACT_CALADDOS_Msk                /*!< ADC calibration additional offset mode */
+
+/********************  Bit definition for ADC_OR option register  ***************/
+#define ADC_OR_OP0_Pos                 (0U)
+#define ADC_OR_OP0_Msk                 (0x1UL << ADC_OR_OP0_Pos)               /*!< 0x00000001 */
+#define ADC_OR_OP0                     ADC_OR_OP0_Msk                          /*!< ADC internal reference voltage buffer */
+
+#define ADC_OR_OP1_Pos                 (1U)
+#define ADC_OR_OP1_Msk                 (0x1UL << ADC_OR_OP1_Pos)               /*!< 0x00000002 */
+#define ADC_OR_OP1                     ADC_OR_OP1_Msk                          /*!< ADC internal bandgap */
+
+#define ADC_OR_OP2_Pos                 (2U)
+#define ADC_OR_OP2_Msk                 (0x1UL << ADC_OR_OP2_Pos)               /*!< 0x00000004 */
+#define ADC_OR_OP2                     ADC_OR_OP2_Msk                          /*!< ADC internal path to VDDCORE */
+
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)
+#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)
+#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)
+#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)
+#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)
+#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)
+#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)
+#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)
+#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)
+#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)
+#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)
+#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)
+#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)
+#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)
+#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)
+#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)
+#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)
+#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)
+#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)
+#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)
+#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
+
+#define ADC_CCR_DAMDF_Pos              (14U)
+#define ADC_CCR_DAMDF_Msk              (0x3UL << ADC_CCR_DAMDF_Pos)            /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                  ADC_CCR_DAMDF_Msk                       /*!< ADC multimode data format */
+#define ADC_CCR_DAMDF_0                (0x1UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                (0x2UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00008000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)
+#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+
+#define ADC_CCR_VBATEN_Pos             (24U)
+#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos         (0U)
+#define ADC_CDR2_RDATA_ALT_Msk         (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT             ADC_CDR2_RDATA_ALT_Msk                   /*!< ADC multimode master or slave (alternated) group regular conversion data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       BSEC unit (Boot and Security)                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for BSEC_FVRw register  *******************/
+#define BSEC_FVRw_FV_Pos               (0U)
+#define BSEC_FVRw_FV_Msk               (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos)           /*!< 0xFFFFFFFF */
+#define BSEC_FVRw_FV                   BSEC_FVRw_FV_Msk                            /*!< Fuse value */
+
+/*****************  Bit definition for BSEC_SPLOCKx register  *****************/
+#define BSEC_SPLOCKx_SPLOCK0_Pos       (0U)
+#define BSEC_SPLOCKx_SPLOCK0_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SPLOCKx_SPLOCK0           BSEC_SPLOCKx_SPLOCK0_Msk                    /*!< Sticky programming lock for word (32*x) */
+#define BSEC_SPLOCKx_SPLOCK1_Pos       (1U)
+#define BSEC_SPLOCKx_SPLOCK1_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SPLOCKx_SPLOCK1           BSEC_SPLOCKx_SPLOCK1_Msk                    /*!< Sticky programming lock for word (1+32*x) */
+#define BSEC_SPLOCKx_SPLOCK2_Pos       (2U)
+#define BSEC_SPLOCKx_SPLOCK2_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SPLOCKx_SPLOCK2           BSEC_SPLOCKx_SPLOCK2_Msk                    /*!< Sticky programming lock for word (2+32*x) */
+#define BSEC_SPLOCKx_SPLOCK3_Pos       (3U)
+#define BSEC_SPLOCKx_SPLOCK3_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SPLOCKx_SPLOCK3           BSEC_SPLOCKx_SPLOCK3_Msk                    /*!< Sticky programming lock for word (3+32*x) */
+#define BSEC_SPLOCKx_SPLOCK4_Pos       (4U)
+#define BSEC_SPLOCKx_SPLOCK4_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SPLOCKx_SPLOCK4           BSEC_SPLOCKx_SPLOCK4_Msk                    /*!< Sticky programming lock for word (4+32*x) */
+#define BSEC_SPLOCKx_SPLOCK5_Pos       (5U)
+#define BSEC_SPLOCKx_SPLOCK5_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SPLOCKx_SPLOCK5           BSEC_SPLOCKx_SPLOCK5_Msk                    /*!< Sticky programming lock for word (5+32*x) */
+#define BSEC_SPLOCKx_SPLOCK6_Pos       (6U)
+#define BSEC_SPLOCKx_SPLOCK6_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SPLOCKx_SPLOCK6           BSEC_SPLOCKx_SPLOCK6_Msk                    /*!< Sticky programming lock for word (6+32*x) */
+#define BSEC_SPLOCKx_SPLOCK7_Pos       (7U)
+#define BSEC_SPLOCKx_SPLOCK7_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SPLOCKx_SPLOCK7           BSEC_SPLOCKx_SPLOCK7_Msk                    /*!< Sticky programming lock for word (7+32*x) */
+#define BSEC_SPLOCKx_SPLOCK8_Pos       (8U)
+#define BSEC_SPLOCKx_SPLOCK8_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SPLOCKx_SPLOCK8           BSEC_SPLOCKx_SPLOCK8_Msk                    /*!< Sticky programming lock for word (8+32*x) */
+#define BSEC_SPLOCKx_SPLOCK9_Pos       (9U)
+#define BSEC_SPLOCKx_SPLOCK9_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SPLOCKx_SPLOCK9           BSEC_SPLOCKx_SPLOCK9_Msk                    /*!< Sticky programming lock for word (9+32*x) */
+#define BSEC_SPLOCKx_SPLOCK10_Pos      (10U)
+#define BSEC_SPLOCKx_SPLOCK10_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SPLOCKx_SPLOCK10          BSEC_SPLOCKx_SPLOCK10_Msk                   /*!< Sticky programming lock for word (10+32*x) */
+#define BSEC_SPLOCKx_SPLOCK11_Pos      (11U)
+#define BSEC_SPLOCKx_SPLOCK11_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SPLOCKx_SPLOCK11          BSEC_SPLOCKx_SPLOCK11_Msk                   /*!< Sticky programming lock for word (11+32*x) */
+#define BSEC_SPLOCKx_SPLOCK12_Pos      (12U)
+#define BSEC_SPLOCKx_SPLOCK12_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SPLOCKx_SPLOCK12          BSEC_SPLOCKx_SPLOCK12_Msk                   /*!< Sticky programming lock for word (12+32*x) */
+#define BSEC_SPLOCKx_SPLOCK13_Pos      (13U)
+#define BSEC_SPLOCKx_SPLOCK13_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SPLOCKx_SPLOCK13          BSEC_SPLOCKx_SPLOCK13_Msk                   /*!< Sticky programming lock for word (13+32*x) */
+#define BSEC_SPLOCKx_SPLOCK14_Pos      (14U)
+#define BSEC_SPLOCKx_SPLOCK14_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SPLOCKx_SPLOCK14          BSEC_SPLOCKx_SPLOCK14_Msk                   /*!< Sticky programming lock for word (14+32*x) */
+#define BSEC_SPLOCKx_SPLOCK15_Pos      (15U)
+#define BSEC_SPLOCKx_SPLOCK15_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SPLOCKx_SPLOCK15          BSEC_SPLOCKx_SPLOCK15_Msk                   /*!< Sticky programming lock for word (15+32*x) */
+#define BSEC_SPLOCKx_SPLOCK16_Pos      (16U)
+#define BSEC_SPLOCKx_SPLOCK16_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SPLOCKx_SPLOCK16          BSEC_SPLOCKx_SPLOCK16_Msk                   /*!< Sticky programming lock for word (16+32*x) */
+#define BSEC_SPLOCKx_SPLOCK17_Pos      (17U)
+#define BSEC_SPLOCKx_SPLOCK17_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SPLOCKx_SPLOCK17          BSEC_SPLOCKx_SPLOCK17_Msk                   /*!< Sticky programming lock for word (17+32*x) */
+#define BSEC_SPLOCKx_SPLOCK18_Pos      (18U)
+#define BSEC_SPLOCKx_SPLOCK18_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SPLOCKx_SPLOCK18          BSEC_SPLOCKx_SPLOCK18_Msk                   /*!< Sticky programming lock for word (18+32*x) */
+#define BSEC_SPLOCKx_SPLOCK19_Pos      (19U)
+#define BSEC_SPLOCKx_SPLOCK19_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SPLOCKx_SPLOCK19          BSEC_SPLOCKx_SPLOCK19_Msk                   /*!< Sticky programming lock for word (19+32*x) */
+#define BSEC_SPLOCKx_SPLOCK20_Pos      (20U)
+#define BSEC_SPLOCKx_SPLOCK20_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SPLOCKx_SPLOCK20          BSEC_SPLOCKx_SPLOCK20_Msk                   /*!< Sticky programming lock for word (20+32*x) */
+#define BSEC_SPLOCKx_SPLOCK21_Pos      (21U)
+#define BSEC_SPLOCKx_SPLOCK21_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SPLOCKx_SPLOCK21          BSEC_SPLOCKx_SPLOCK21_Msk                   /*!< Sticky programming lock for word (21+32*x) */
+#define BSEC_SPLOCKx_SPLOCK22_Pos      (22U)
+#define BSEC_SPLOCKx_SPLOCK22_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SPLOCKx_SPLOCK22          BSEC_SPLOCKx_SPLOCK22_Msk                   /*!< Sticky programming lock for word (22+32*x) */
+#define BSEC_SPLOCKx_SPLOCK23_Pos      (23U)
+#define BSEC_SPLOCKx_SPLOCK23_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SPLOCKx_SPLOCK23          BSEC_SPLOCKx_SPLOCK23_Msk                   /*!< Sticky programming lock for word (23+32*x) */
+#define BSEC_SPLOCKx_SPLOCK24_Pos      (24U)
+#define BSEC_SPLOCKx_SPLOCK24_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SPLOCKx_SPLOCK24          BSEC_SPLOCKx_SPLOCK24_Msk                   /*!< Sticky programming lock for word (24+32*x) */
+#define BSEC_SPLOCKx_SPLOCK25_Pos      (25U)
+#define BSEC_SPLOCKx_SPLOCK25_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SPLOCKx_SPLOCK25          BSEC_SPLOCKx_SPLOCK25_Msk                   /*!< Sticky programming lock for word (25+32*x) */
+#define BSEC_SPLOCKx_SPLOCK26_Pos      (26U)
+#define BSEC_SPLOCKx_SPLOCK26_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SPLOCKx_SPLOCK26          BSEC_SPLOCKx_SPLOCK26_Msk                   /*!< Sticky programming lock for word (26+32*x) */
+#define BSEC_SPLOCKx_SPLOCK27_Pos      (27U)
+#define BSEC_SPLOCKx_SPLOCK27_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SPLOCKx_SPLOCK27          BSEC_SPLOCKx_SPLOCK27_Msk                   /*!< Sticky programming lock for word (27+32*x) */
+#define BSEC_SPLOCKx_SPLOCK28_Pos      (28U)
+#define BSEC_SPLOCKx_SPLOCK28_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SPLOCKx_SPLOCK28          BSEC_SPLOCKx_SPLOCK28_Msk                   /*!< Sticky programming lock for word (28+32*x) */
+#define BSEC_SPLOCKx_SPLOCK29_Pos      (29U)
+#define BSEC_SPLOCKx_SPLOCK29_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SPLOCKx_SPLOCK29          BSEC_SPLOCKx_SPLOCK29_Msk                   /*!< Sticky programming lock for word (29+32*x) */
+#define BSEC_SPLOCKx_SPLOCK30_Pos      (30U)
+#define BSEC_SPLOCKx_SPLOCK30_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SPLOCKx_SPLOCK30          BSEC_SPLOCKx_SPLOCK30_Msk                   /*!< Sticky programming lock for word (30+32*x) */
+#define BSEC_SPLOCKx_SPLOCK31_Pos      (31U)
+#define BSEC_SPLOCKx_SPLOCK31_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SPLOCKx_SPLOCK31          BSEC_SPLOCKx_SPLOCK31_Msk                   /*!< Sticky programming lock for word (31+32*x) */
+
+/*****************  Bit definition for BSEC_SWLOCKx register  *****************/
+#define BSEC_SWLOCKx_SWLOCK0_Pos       (0U)
+#define BSEC_SWLOCKx_SWLOCK0_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SWLOCKx_SWLOCK0           BSEC_SWLOCKx_SWLOCK0_Msk                    /*!< Sticky write lock for shadow register (32*x) */
+#define BSEC_SWLOCKx_SWLOCK1_Pos       (1U)
+#define BSEC_SWLOCKx_SWLOCK1_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SWLOCKx_SWLOCK1           BSEC_SWLOCKx_SWLOCK1_Msk                    /*!< Sticky write lock for shadow register (1+32*x) */
+#define BSEC_SWLOCKx_SWLOCK2_Pos       (2U)
+#define BSEC_SWLOCKx_SWLOCK2_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SWLOCKx_SWLOCK2           BSEC_SWLOCKx_SWLOCK2_Msk                    /*!< Sticky write lock for shadow register (2+32*x) */
+#define BSEC_SWLOCKx_SWLOCK3_Pos       (3U)
+#define BSEC_SWLOCKx_SWLOCK3_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SWLOCKx_SWLOCK3           BSEC_SWLOCKx_SWLOCK3_Msk                    /*!< Sticky write lock for shadow register (3+32*x) */
+#define BSEC_SWLOCKx_SWLOCK4_Pos       (4U)
+#define BSEC_SWLOCKx_SWLOCK4_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SWLOCKx_SWLOCK4           BSEC_SWLOCKx_SWLOCK4_Msk                    /*!< Sticky write lock for shadow register (4+32*x) */
+#define BSEC_SWLOCKx_SWLOCK5_Pos       (5U)
+#define BSEC_SWLOCKx_SWLOCK5_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SWLOCKx_SWLOCK5           BSEC_SWLOCKx_SWLOCK5_Msk                    /*!< Sticky write lock for shadow register (5+32*x) */
+#define BSEC_SWLOCKx_SWLOCK6_Pos       (6U)
+#define BSEC_SWLOCKx_SWLOCK6_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SWLOCKx_SWLOCK6           BSEC_SWLOCKx_SWLOCK6_Msk                    /*!< Sticky write lock for shadow register (6+32*x) */
+#define BSEC_SWLOCKx_SWLOCK7_Pos       (7U)
+#define BSEC_SWLOCKx_SWLOCK7_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SWLOCKx_SWLOCK7           BSEC_SWLOCKx_SWLOCK7_Msk                    /*!< Sticky write lock for shadow register (7+32*x) */
+#define BSEC_SWLOCKx_SWLOCK8_Pos       (8U)
+#define BSEC_SWLOCKx_SWLOCK8_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SWLOCKx_SWLOCK8           BSEC_SWLOCKx_SWLOCK8_Msk                    /*!< Sticky write lock for shadow register (8+32*x) */
+#define BSEC_SWLOCKx_SWLOCK9_Pos       (9U)
+#define BSEC_SWLOCKx_SWLOCK9_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SWLOCKx_SWLOCK9           BSEC_SWLOCKx_SWLOCK9_Msk                    /*!< Sticky write lock for shadow register (9+32*x) */
+#define BSEC_SWLOCKx_SWLOCK10_Pos      (10U)
+#define BSEC_SWLOCKx_SWLOCK10_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SWLOCKx_SWLOCK10          BSEC_SWLOCKx_SWLOCK10_Msk                   /*!< Sticky write lock for shadow register (10+32*x) */
+#define BSEC_SWLOCKx_SWLOCK11_Pos      (11U)
+#define BSEC_SWLOCKx_SWLOCK11_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SWLOCKx_SWLOCK11          BSEC_SWLOCKx_SWLOCK11_Msk                   /*!< Sticky write lock for shadow register (11+32*x) */
+#define BSEC_SWLOCKx_SWLOCK12_Pos      (12U)
+#define BSEC_SWLOCKx_SWLOCK12_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SWLOCKx_SWLOCK12          BSEC_SWLOCKx_SWLOCK12_Msk                   /*!< Sticky write lock for shadow register (12+32*x) */
+#define BSEC_SWLOCKx_SWLOCK13_Pos      (13U)
+#define BSEC_SWLOCKx_SWLOCK13_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SWLOCKx_SWLOCK13          BSEC_SWLOCKx_SWLOCK13_Msk                   /*!< Sticky write lock for shadow register (13+32*x) */
+#define BSEC_SWLOCKx_SWLOCK14_Pos      (14U)
+#define BSEC_SWLOCKx_SWLOCK14_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SWLOCKx_SWLOCK14          BSEC_SWLOCKx_SWLOCK14_Msk                   /*!< Sticky write lock for shadow register (14+32*x) */
+#define BSEC_SWLOCKx_SWLOCK15_Pos      (15U)
+#define BSEC_SWLOCKx_SWLOCK15_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SWLOCKx_SWLOCK15          BSEC_SWLOCKx_SWLOCK15_Msk                   /*!< Sticky write lock for shadow register (15+32*x) */
+#define BSEC_SWLOCKx_SWLOCK16_Pos      (16U)
+#define BSEC_SWLOCKx_SWLOCK16_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SWLOCKx_SWLOCK16          BSEC_SWLOCKx_SWLOCK16_Msk                   /*!< Sticky write lock for shadow register (16+32*x) */
+#define BSEC_SWLOCKx_SWLOCK17_Pos      (17U)
+#define BSEC_SWLOCKx_SWLOCK17_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SWLOCKx_SWLOCK17          BSEC_SWLOCKx_SWLOCK17_Msk                   /*!< Sticky write lock for shadow register (17+32*x) */
+#define BSEC_SWLOCKx_SWLOCK18_Pos      (18U)
+#define BSEC_SWLOCKx_SWLOCK18_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SWLOCKx_SWLOCK18          BSEC_SWLOCKx_SWLOCK18_Msk                   /*!< Sticky write lock for shadow register (18+32*x) */
+#define BSEC_SWLOCKx_SWLOCK19_Pos      (19U)
+#define BSEC_SWLOCKx_SWLOCK19_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SWLOCKx_SWLOCK19          BSEC_SWLOCKx_SWLOCK19_Msk                   /*!< Sticky write lock for shadow register (19+32*x) */
+#define BSEC_SWLOCKx_SWLOCK20_Pos      (20U)
+#define BSEC_SWLOCKx_SWLOCK20_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SWLOCKx_SWLOCK20          BSEC_SWLOCKx_SWLOCK20_Msk                   /*!< Sticky write lock for shadow register (20+32*x) */
+#define BSEC_SWLOCKx_SWLOCK21_Pos      (21U)
+#define BSEC_SWLOCKx_SWLOCK21_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SWLOCKx_SWLOCK21          BSEC_SWLOCKx_SWLOCK21_Msk                   /*!< Sticky write lock for shadow register (21+32*x) */
+#define BSEC_SWLOCKx_SWLOCK22_Pos      (22U)
+#define BSEC_SWLOCKx_SWLOCK22_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SWLOCKx_SWLOCK22          BSEC_SWLOCKx_SWLOCK22_Msk                   /*!< Sticky write lock for shadow register (22+32*x) */
+#define BSEC_SWLOCKx_SWLOCK23_Pos      (23U)
+#define BSEC_SWLOCKx_SWLOCK23_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SWLOCKx_SWLOCK23          BSEC_SWLOCKx_SWLOCK23_Msk                   /*!< Sticky write lock for shadow register (23+32*x) */
+#define BSEC_SWLOCKx_SWLOCK24_Pos      (24U)
+#define BSEC_SWLOCKx_SWLOCK24_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SWLOCKx_SWLOCK24          BSEC_SWLOCKx_SWLOCK24_Msk                   /*!< Sticky write lock for shadow register (24+32*x) */
+#define BSEC_SWLOCKx_SWLOCK25_Pos      (25U)
+#define BSEC_SWLOCKx_SWLOCK25_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SWLOCKx_SWLOCK25          BSEC_SWLOCKx_SWLOCK25_Msk                   /*!< Sticky write lock for shadow register (25+32*x) */
+#define BSEC_SWLOCKx_SWLOCK26_Pos      (26U)
+#define BSEC_SWLOCKx_SWLOCK26_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SWLOCKx_SWLOCK26          BSEC_SWLOCKx_SWLOCK26_Msk                   /*!< Sticky write lock for shadow register (26+32*x) */
+#define BSEC_SWLOCKx_SWLOCK27_Pos      (27U)
+#define BSEC_SWLOCKx_SWLOCK27_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SWLOCKx_SWLOCK27          BSEC_SWLOCKx_SWLOCK27_Msk                   /*!< Sticky write lock for shadow register (27+32*x) */
+#define BSEC_SWLOCKx_SWLOCK28_Pos      (28U)
+#define BSEC_SWLOCKx_SWLOCK28_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SWLOCKx_SWLOCK28          BSEC_SWLOCKx_SWLOCK28_Msk                   /*!< Sticky write lock for shadow register (28+32*x) */
+#define BSEC_SWLOCKx_SWLOCK29_Pos      (29U)
+#define BSEC_SWLOCKx_SWLOCK29_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SWLOCKx_SWLOCK29          BSEC_SWLOCKx_SWLOCK29_Msk                   /*!< Sticky write lock for shadow register (29+32*x) */
+#define BSEC_SWLOCKx_SWLOCK30_Pos      (30U)
+#define BSEC_SWLOCKx_SWLOCK30_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SWLOCKx_SWLOCK30          BSEC_SWLOCKx_SWLOCK30_Msk                   /*!< Sticky write lock for shadow register (30+32*x) */
+#define BSEC_SWLOCKx_SWLOCK31_Pos      (31U)
+#define BSEC_SWLOCKx_SWLOCK31_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SWLOCKx_SWLOCK31          BSEC_SWLOCKx_SWLOCK31_Msk                   /*!< Sticky write lock for shadow register (31+32*x) */
+
+/*****************  Bit definition for BSEC_SRLOCKx register  *****************/
+#define BSEC_SRLOCKx_SRLOCK0_Pos       (0U)
+#define BSEC_SRLOCKx_SRLOCK0_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SRLOCKx_SRLOCK0           BSEC_SRLOCKx_SRLOCK0_Msk                    /*!< Sticky reload lock for fuse word (32*x) */
+#define BSEC_SRLOCKx_SRLOCK1_Pos       (1U)
+#define BSEC_SRLOCKx_SRLOCK1_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SRLOCKx_SRLOCK1           BSEC_SRLOCKx_SRLOCK1_Msk                    /*!< Sticky reload lock for fuse word (1+32*x) */
+#define BSEC_SRLOCKx_SRLOCK2_Pos       (2U)
+#define BSEC_SRLOCKx_SRLOCK2_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SRLOCKx_SRLOCK2           BSEC_SRLOCKx_SRLOCK2_Msk                    /*!< Sticky reload lock for fuse word (2+32*x) */
+#define BSEC_SRLOCKx_SRLOCK3_Pos       (3U)
+#define BSEC_SRLOCKx_SRLOCK3_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SRLOCKx_SRLOCK3           BSEC_SRLOCKx_SRLOCK3_Msk                    /*!< Sticky reload lock for fuse word (3+32*x) */
+#define BSEC_SRLOCKx_SRLOCK4_Pos       (4U)
+#define BSEC_SRLOCKx_SRLOCK4_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SRLOCKx_SRLOCK4           BSEC_SRLOCKx_SRLOCK4_Msk                    /*!< Sticky reload lock for fuse word (4+32*x) */
+#define BSEC_SRLOCKx_SRLOCK5_Pos       (5U)
+#define BSEC_SRLOCKx_SRLOCK5_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SRLOCKx_SRLOCK5           BSEC_SRLOCKx_SRLOCK5_Msk                    /*!< Sticky reload lock for fuse word (5+32*x) */
+#define BSEC_SRLOCKx_SRLOCK6_Pos       (6U)
+#define BSEC_SRLOCKx_SRLOCK6_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SRLOCKx_SRLOCK6           BSEC_SRLOCKx_SRLOCK6_Msk                    /*!< Sticky reload lock for fuse word (6+32*x) */
+#define BSEC_SRLOCKx_SRLOCK7_Pos       (7U)
+#define BSEC_SRLOCKx_SRLOCK7_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SRLOCKx_SRLOCK7           BSEC_SRLOCKx_SRLOCK7_Msk                    /*!< Sticky reload lock for fuse word (7+32*x) */
+#define BSEC_SRLOCKx_SRLOCK8_Pos       (8U)
+#define BSEC_SRLOCKx_SRLOCK8_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SRLOCKx_SRLOCK8           BSEC_SRLOCKx_SRLOCK8_Msk                    /*!< Sticky reload lock for fuse word (8+32*x) */
+#define BSEC_SRLOCKx_SRLOCK9_Pos       (9U)
+#define BSEC_SRLOCKx_SRLOCK9_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SRLOCKx_SRLOCK9           BSEC_SRLOCKx_SRLOCK9_Msk                    /*!< Sticky reload lock for fuse word (9+32*x) */
+#define BSEC_SRLOCKx_SRLOCK10_Pos      (10U)
+#define BSEC_SRLOCKx_SRLOCK10_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SRLOCKx_SRLOCK10          BSEC_SRLOCKx_SRLOCK10_Msk                   /*!< Sticky reload lock for fuse word (10+2*x) */
+#define BSEC_SRLOCKx_SRLOCK11_Pos      (11U)
+#define BSEC_SRLOCKx_SRLOCK11_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SRLOCKx_SRLOCK11          BSEC_SRLOCKx_SRLOCK11_Msk                   /*!< Sticky reload lock for fuse word (11+32*x) */
+#define BSEC_SRLOCKx_SRLOCK12_Pos      (12U)
+#define BSEC_SRLOCKx_SRLOCK12_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SRLOCKx_SRLOCK12          BSEC_SRLOCKx_SRLOCK12_Msk                   /*!< Sticky reload lock for fuse word (12+32*x) */
+#define BSEC_SRLOCKx_SRLOCK13_Pos      (13U)
+#define BSEC_SRLOCKx_SRLOCK13_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SRLOCKx_SRLOCK13          BSEC_SRLOCKx_SRLOCK13_Msk                   /*!< Sticky reload lock for fuse word (13+32*x) */
+#define BSEC_SRLOCKx_SRLOCK14_Pos      (14U)
+#define BSEC_SRLOCKx_SRLOCK14_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SRLOCKx_SRLOCK14          BSEC_SRLOCKx_SRLOCK14_Msk                   /*!< Sticky reload lock for fuse word (14+32*x) */
+#define BSEC_SRLOCKx_SRLOCK15_Pos      (15U)
+#define BSEC_SRLOCKx_SRLOCK15_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SRLOCKx_SRLOCK15          BSEC_SRLOCKx_SRLOCK15_Msk                   /*!< Sticky reload lock for fuse word (15+32*x) */
+#define BSEC_SRLOCKx_SRLOCK16_Pos      (16U)
+#define BSEC_SRLOCKx_SRLOCK16_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SRLOCKx_SRLOCK16          BSEC_SRLOCKx_SRLOCK16_Msk                   /*!< Sticky reload lock for fuse word (16+32*x) */
+#define BSEC_SRLOCKx_SRLOCK17_Pos      (17U)
+#define BSEC_SRLOCKx_SRLOCK17_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SRLOCKx_SRLOCK17          BSEC_SRLOCKx_SRLOCK17_Msk                   /*!< Sticky reload lock for fuse word (17+32*x) */
+#define BSEC_SRLOCKx_SRLOCK18_Pos      (18U)
+#define BSEC_SRLOCKx_SRLOCK18_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SRLOCKx_SRLOCK18          BSEC_SRLOCKx_SRLOCK18_Msk                   /*!< Sticky reload lock for fuse word (18+32*x) */
+#define BSEC_SRLOCKx_SRLOCK19_Pos      (19U)
+#define BSEC_SRLOCKx_SRLOCK19_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SRLOCKx_SRLOCK19          BSEC_SRLOCKx_SRLOCK19_Msk                   /*!< Sticky reload lock for fuse word (19+32*x) */
+#define BSEC_SRLOCKx_SRLOCK20_Pos      (20U)
+#define BSEC_SRLOCKx_SRLOCK20_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SRLOCKx_SRLOCK20          BSEC_SRLOCKx_SRLOCK20_Msk                   /*!< Sticky reload lock for fuse word (20+32*x) */
+#define BSEC_SRLOCKx_SRLOCK21_Pos      (21U)
+#define BSEC_SRLOCKx_SRLOCK21_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SRLOCKx_SRLOCK21          BSEC_SRLOCKx_SRLOCK21_Msk                   /*!< Sticky reload lock for fuse word (21+32*x) */
+#define BSEC_SRLOCKx_SRLOCK22_Pos      (22U)
+#define BSEC_SRLOCKx_SRLOCK22_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SRLOCKx_SRLOCK22          BSEC_SRLOCKx_SRLOCK22_Msk                   /*!< Sticky reload lock for fuse word (22+32*x) */
+#define BSEC_SRLOCKx_SRLOCK23_Pos      (23U)
+#define BSEC_SRLOCKx_SRLOCK23_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SRLOCKx_SRLOCK23          BSEC_SRLOCKx_SRLOCK23_Msk                   /*!< Sticky reload lock for fuse word (23+32*x) */
+#define BSEC_SRLOCKx_SRLOCK24_Pos      (24U)
+#define BSEC_SRLOCKx_SRLOCK24_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SRLOCKx_SRLOCK24          BSEC_SRLOCKx_SRLOCK24_Msk                   /*!< Sticky reload lock for fuse word (24+32*x) */
+#define BSEC_SRLOCKx_SRLOCK25_Pos      (25U)
+#define BSEC_SRLOCKx_SRLOCK25_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SRLOCKx_SRLOCK25          BSEC_SRLOCKx_SRLOCK25_Msk                   /*!< Sticky reload lock for fuse word (25+32*x) */
+#define BSEC_SRLOCKx_SRLOCK26_Pos      (26U)
+#define BSEC_SRLOCKx_SRLOCK26_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SRLOCKx_SRLOCK26          BSEC_SRLOCKx_SRLOCK26_Msk                   /*!< Sticky reload lock for fuse word (26+32*x) */
+#define BSEC_SRLOCKx_SRLOCK27_Pos      (27U)
+#define BSEC_SRLOCKx_SRLOCK27_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SRLOCKx_SRLOCK27          BSEC_SRLOCKx_SRLOCK27_Msk                   /*!< Sticky reload lock for fuse word (27+32*x) */
+#define BSEC_SRLOCKx_SRLOCK28_Pos      (28U)
+#define BSEC_SRLOCKx_SRLOCK28_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SRLOCKx_SRLOCK28          BSEC_SRLOCKx_SRLOCK28_Msk                   /*!< Sticky reload lock for fuse word (28+32*x) */
+#define BSEC_SRLOCKx_SRLOCK29_Pos      (29U)
+#define BSEC_SRLOCKx_SRLOCK29_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SRLOCKx_SRLOCK29          BSEC_SRLOCKx_SRLOCK29_Msk                   /*!< Sticky reload lock for fuse word (29+32*x) */
+#define BSEC_SRLOCKx_SRLOCK30_Pos      (30U)
+#define BSEC_SRLOCKx_SRLOCK30_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SRLOCKx_SRLOCK30          BSEC_SRLOCKx_SRLOCK30_Msk                   /*!< Sticky reload lock for fuse word (30+32*x) */
+#define BSEC_SRLOCKx_SRLOCK31_Pos      (31U)
+#define BSEC_SRLOCKx_SRLOCK31_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SRLOCKx_SRLOCK31          BSEC_SRLOCKx_SRLOCK31_Msk                   /*!< Sticky reload lock for fuse word (31+32*x) */
+
+/****************  Bit definition for BSEC_OTPVLDRx register  *****************/
+#define BSEC_OTPVLDRx_VLDF0_Pos        (0U)
+#define BSEC_OTPVLDRx_VLDF0_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos)           /*!< 0x00000001 */
+#define BSEC_OTPVLDRx_VLDF0            BSEC_OTPVLDRx_VLDF0_Msk                     /*!< Valid flag for shadow register (32*x) */
+#define BSEC_OTPVLDRx_VLDF1_Pos        (1U)
+#define BSEC_OTPVLDRx_VLDF1_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos)           /*!< 0x00000002 */
+#define BSEC_OTPVLDRx_VLDF1            BSEC_OTPVLDRx_VLDF1_Msk                     /*!< Valid flag for shadow register (1+32*x) */
+#define BSEC_OTPVLDRx_VLDF2_Pos        (2U)
+#define BSEC_OTPVLDRx_VLDF2_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos)           /*!< 0x00000004 */
+#define BSEC_OTPVLDRx_VLDF2            BSEC_OTPVLDRx_VLDF2_Msk                     /*!< Valid flag for shadow register (2+32*x) */
+#define BSEC_OTPVLDRx_VLDF3_Pos        (3U)
+#define BSEC_OTPVLDRx_VLDF3_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos)           /*!< 0x00000008 */
+#define BSEC_OTPVLDRx_VLDF3            BSEC_OTPVLDRx_VLDF3_Msk                     /*!< Valid flag for shadow register (3+32*x) */
+#define BSEC_OTPVLDRx_VLDF4_Pos        (4U)
+#define BSEC_OTPVLDRx_VLDF4_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos)           /*!< 0x00000010 */
+#define BSEC_OTPVLDRx_VLDF4            BSEC_OTPVLDRx_VLDF4_Msk                     /*!< Valid flag for shadow register (4+32*x) */
+#define BSEC_OTPVLDRx_VLDF5_Pos        (5U)
+#define BSEC_OTPVLDRx_VLDF5_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos)           /*!< 0x00000020 */
+#define BSEC_OTPVLDRx_VLDF5            BSEC_OTPVLDRx_VLDF5_Msk                     /*!< Valid flag for shadow register (5+32*x) */
+#define BSEC_OTPVLDRx_VLDF6_Pos        (6U)
+#define BSEC_OTPVLDRx_VLDF6_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos)           /*!< 0x00000040 */
+#define BSEC_OTPVLDRx_VLDF6            BSEC_OTPVLDRx_VLDF6_Msk                     /*!< Valid flag for shadow register (6+32*x) */
+#define BSEC_OTPVLDRx_VLDF7_Pos        (7U)
+#define BSEC_OTPVLDRx_VLDF7_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos)           /*!< 0x00000080 */
+#define BSEC_OTPVLDRx_VLDF7            BSEC_OTPVLDRx_VLDF7_Msk                     /*!< Valid flag for shadow register (7+32*x) */
+#define BSEC_OTPVLDRx_VLDF8_Pos        (8U)
+#define BSEC_OTPVLDRx_VLDF8_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos)           /*!< 0x00000100 */
+#define BSEC_OTPVLDRx_VLDF8            BSEC_OTPVLDRx_VLDF8_Msk                     /*!< Valid flag for shadow register (8+32*x) */
+#define BSEC_OTPVLDRx_VLDF9_Pos        (9U)
+#define BSEC_OTPVLDRx_VLDF9_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos)           /*!< 0x00000200 */
+#define BSEC_OTPVLDRx_VLDF9            BSEC_OTPVLDRx_VLDF9_Msk                     /*!< Valid flag for shadow register (9+32*x) */
+#define BSEC_OTPVLDRx_VLDF10_Pos       (10U)
+#define BSEC_OTPVLDRx_VLDF10_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos)          /*!< 0x00000400 */
+#define BSEC_OTPVLDRx_VLDF10           BSEC_OTPVLDRx_VLDF10_Msk                    /*!< Valid flag for shadow register (10+32*x) */
+#define BSEC_OTPVLDRx_VLDF11_Pos       (11U)
+#define BSEC_OTPVLDRx_VLDF11_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos)          /*!< 0x00000800 */
+#define BSEC_OTPVLDRx_VLDF11           BSEC_OTPVLDRx_VLDF11_Msk                    /*!< Valid flag for shadow register (11+32*x) */
+#define BSEC_OTPVLDRx_VLDF12_Pos       (12U)
+#define BSEC_OTPVLDRx_VLDF12_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos)          /*!< 0x00001000 */
+#define BSEC_OTPVLDRx_VLDF12           BSEC_OTPVLDRx_VLDF12_Msk                    /*!< Valid flag for shadow register (12+32*x) */
+#define BSEC_OTPVLDRx_VLDF13_Pos       (13U)
+#define BSEC_OTPVLDRx_VLDF13_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos)          /*!< 0x00002000 */
+#define BSEC_OTPVLDRx_VLDF13           BSEC_OTPVLDRx_VLDF13_Msk                    /*!< Valid flag for shadow register (13+32*x) */
+#define BSEC_OTPVLDRx_VLDF14_Pos       (14U)
+#define BSEC_OTPVLDRx_VLDF14_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos)          /*!< 0x00004000 */
+#define BSEC_OTPVLDRx_VLDF14           BSEC_OTPVLDRx_VLDF14_Msk                    /*!< Valid flag for shadow register (14+32*x) */
+#define BSEC_OTPVLDRx_VLDF15_Pos       (15U)
+#define BSEC_OTPVLDRx_VLDF15_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos)          /*!< 0x00008000 */
+#define BSEC_OTPVLDRx_VLDF15           BSEC_OTPVLDRx_VLDF15_Msk                    /*!< Valid flag for shadow register (15+32*x) */
+#define BSEC_OTPVLDRx_VLDF16_Pos       (16U)
+#define BSEC_OTPVLDRx_VLDF16_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos)          /*!< 0x00010000 */
+#define BSEC_OTPVLDRx_VLDF16           BSEC_OTPVLDRx_VLDF16_Msk                    /*!< Valid flag for shadow register (16+32*x) */
+#define BSEC_OTPVLDRx_VLDF17_Pos       (17U)
+#define BSEC_OTPVLDRx_VLDF17_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos)          /*!< 0x00020000 */
+#define BSEC_OTPVLDRx_VLDF17           BSEC_OTPVLDRx_VLDF17_Msk                    /*!< Valid flag for shadow register (17+32*x) */
+#define BSEC_OTPVLDRx_VLDF18_Pos       (18U)
+#define BSEC_OTPVLDRx_VLDF18_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos)          /*!< 0x00040000 */
+#define BSEC_OTPVLDRx_VLDF18           BSEC_OTPVLDRx_VLDF18_Msk                    /*!< Valid flag for shadow register (18+32*x) */
+#define BSEC_OTPVLDRx_VLDF19_Pos       (19U)
+#define BSEC_OTPVLDRx_VLDF19_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos)          /*!< 0x00080000 */
+#define BSEC_OTPVLDRx_VLDF19           BSEC_OTPVLDRx_VLDF19_Msk                    /*!< Valid flag for shadow register (19+32*x) */
+#define BSEC_OTPVLDRx_VLDF20_Pos       (20U)
+#define BSEC_OTPVLDRx_VLDF20_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos)          /*!< 0x00100000 */
+#define BSEC_OTPVLDRx_VLDF20           BSEC_OTPVLDRx_VLDF20_Msk                    /*!< Valid flag for shadow register (20+32*x) */
+#define BSEC_OTPVLDRx_VLDF21_Pos       (21U)
+#define BSEC_OTPVLDRx_VLDF21_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos)          /*!< 0x00200000 */
+#define BSEC_OTPVLDRx_VLDF21           BSEC_OTPVLDRx_VLDF21_Msk                    /*!< Valid flag for shadow register (21+32*x) */
+#define BSEC_OTPVLDRx_VLDF22_Pos       (22U)
+#define BSEC_OTPVLDRx_VLDF22_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos)          /*!< 0x00400000 */
+#define BSEC_OTPVLDRx_VLDF22           BSEC_OTPVLDRx_VLDF22_Msk                    /*!< Valid flag for shadow register (22+32*x) */
+#define BSEC_OTPVLDRx_VLDF23_Pos       (23U)
+#define BSEC_OTPVLDRx_VLDF23_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos)          /*!< 0x00800000 */
+#define BSEC_OTPVLDRx_VLDF23           BSEC_OTPVLDRx_VLDF23_Msk                    /*!< Valid flag for shadow register (23+32*x) */
+#define BSEC_OTPVLDRx_VLDF24_Pos       (24U)
+#define BSEC_OTPVLDRx_VLDF24_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos)          /*!< 0x01000000 */
+#define BSEC_OTPVLDRx_VLDF24           BSEC_OTPVLDRx_VLDF24_Msk                    /*!< Valid flag for shadow register (24+32*x) */
+#define BSEC_OTPVLDRx_VLDF25_Pos       (25U)
+#define BSEC_OTPVLDRx_VLDF25_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos)          /*!< 0x02000000 */
+#define BSEC_OTPVLDRx_VLDF25           BSEC_OTPVLDRx_VLDF25_Msk                    /*!< Valid flag for shadow register (25+32*x) */
+#define BSEC_OTPVLDRx_VLDF26_Pos       (26U)
+#define BSEC_OTPVLDRx_VLDF26_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos)          /*!< 0x04000000 */
+#define BSEC_OTPVLDRx_VLDF26           BSEC_OTPVLDRx_VLDF26_Msk                    /*!< Valid flag for shadow register (26+32*x) */
+#define BSEC_OTPVLDRx_VLDF27_Pos       (27U)
+#define BSEC_OTPVLDRx_VLDF27_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos)          /*!< 0x08000000 */
+#define BSEC_OTPVLDRx_VLDF27           BSEC_OTPVLDRx_VLDF27_Msk                    /*!< Valid flag for shadow register (27+32*x) */
+#define BSEC_OTPVLDRx_VLDF28_Pos       (28U)
+#define BSEC_OTPVLDRx_VLDF28_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos)          /*!< 0x10000000 */
+#define BSEC_OTPVLDRx_VLDF28           BSEC_OTPVLDRx_VLDF28_Msk                    /*!< Valid flag for shadow register (28+32*x) */
+#define BSEC_OTPVLDRx_VLDF29_Pos       (29U)
+#define BSEC_OTPVLDRx_VLDF29_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos)          /*!< 0x20000000 */
+#define BSEC_OTPVLDRx_VLDF29           BSEC_OTPVLDRx_VLDF29_Msk                    /*!< Valid flag for shadow register (29+32*x) */
+#define BSEC_OTPVLDRx_VLDF30_Pos       (30U)
+#define BSEC_OTPVLDRx_VLDF30_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos)          /*!< 0x40000000 */
+#define BSEC_OTPVLDRx_VLDF30           BSEC_OTPVLDRx_VLDF30_Msk                    /*!< Valid flag for shadow register (30+32*x) */
+#define BSEC_OTPVLDRx_VLDF31_Pos       (31U)
+#define BSEC_OTPVLDRx_VLDF31_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos)          /*!< 0x80000000 */
+#define BSEC_OTPVLDRx_VLDF31           BSEC_OTPVLDRx_VLDF31_Msk                    /*!< Valid flag for shadow register (31+32*x) */
+
+/******************  Bit definition for BSEC_SFSRx register  ******************/
+#define BSEC_SFSRx_SFW0_Pos            (0U)
+#define BSEC_SFSRx_SFW0_Msk            (0x1UL << BSEC_SFSRx_SFW0_Pos)               /*!< 0x00000001 */
+#define BSEC_SFSRx_SFW0                BSEC_SFSRx_SFW0_Msk                         /*!< Shadowed fuse word (32*x) */
+#define BSEC_SFSRx_SFW1_Pos            (1U)
+#define BSEC_SFSRx_SFW1_Msk            (0x1UL << BSEC_SFSRx_SFW1_Pos)               /*!< 0x00000002 */
+#define BSEC_SFSRx_SFW1                BSEC_SFSRx_SFW1_Msk                         /*!< Shadowed fuse word (1+32*x) */
+#define BSEC_SFSRx_SFW2_Pos            (2U)
+#define BSEC_SFSRx_SFW2_Msk            (0x1UL << BSEC_SFSRx_SFW2_Pos)               /*!< 0x00000004 */
+#define BSEC_SFSRx_SFW2                BSEC_SFSRx_SFW2_Msk                         /*!< Shadowed fuse word (2+32*x) */
+#define BSEC_SFSRx_SFW3_Pos            (3U)
+#define BSEC_SFSRx_SFW3_Msk            (0x1UL << BSEC_SFSRx_SFW3_Pos)               /*!< 0x00000008 */
+#define BSEC_SFSRx_SFW3                BSEC_SFSRx_SFW3_Msk                         /*!< Shadowed fuse word (3+32*x) */
+#define BSEC_SFSRx_SFW4_Pos            (4U)
+#define BSEC_SFSRx_SFW4_Msk            (0x1UL << BSEC_SFSRx_SFW4_Pos)               /*!< 0x00000010 */
+#define BSEC_SFSRx_SFW4                BSEC_SFSRx_SFW4_Msk                         /*!< Shadowed fuse word (4+32*x) */
+#define BSEC_SFSRx_SFW5_Pos            (5U)
+#define BSEC_SFSRx_SFW5_Msk            (0x1UL << BSEC_SFSRx_SFW5_Pos)               /*!< 0x00000020 */
+#define BSEC_SFSRx_SFW5                BSEC_SFSRx_SFW5_Msk                         /*!< Shadowed fuse word (5+32*x) */
+#define BSEC_SFSRx_SFW6_Pos            (6U)
+#define BSEC_SFSRx_SFW6_Msk            (0x1UL << BSEC_SFSRx_SFW6_Pos)               /*!< 0x00000040 */
+#define BSEC_SFSRx_SFW6                BSEC_SFSRx_SFW6_Msk                         /*!< Shadowed fuse word (6+32*x) */
+#define BSEC_SFSRx_SFW7_Pos            (7U)
+#define BSEC_SFSRx_SFW7_Msk            (0x1UL << BSEC_SFSRx_SFW7_Pos)               /*!< 0x00000080 */
+#define BSEC_SFSRx_SFW7                BSEC_SFSRx_SFW7_Msk                         /*!< Shadowed fuse word (7+32*x) */
+#define BSEC_SFSRx_SFW8_Pos            (8U)
+#define BSEC_SFSRx_SFW8_Msk            (0x1UL << BSEC_SFSRx_SFW8_Pos)               /*!< 0x00000100 */
+#define BSEC_SFSRx_SFW8                BSEC_SFSRx_SFW8_Msk                         /*!< Shadowed fuse word (8+32*x) */
+#define BSEC_SFSRx_SFW9_Pos            (9U)
+#define BSEC_SFSRx_SFW9_Msk            (0x1UL << BSEC_SFSRx_SFW9_Pos)               /*!< 0x00000200 */
+#define BSEC_SFSRx_SFW9                BSEC_SFSRx_SFW9_Msk                         /*!< Shadowed fuse word (9+32*x) */
+#define BSEC_SFSRx_SFW10_Pos           (10U)
+#define BSEC_SFSRx_SFW10_Msk           (0x1UL << BSEC_SFSRx_SFW10_Pos)              /*!< 0x00000400 */
+#define BSEC_SFSRx_SFW10               BSEC_SFSRx_SFW10_Msk                        /*!< Shadowed fuse word (10+32*x) */
+#define BSEC_SFSRx_SFW11_Pos           (11U)
+#define BSEC_SFSRx_SFW11_Msk           (0x1UL << BSEC_SFSRx_SFW11_Pos)              /*!< 0x00000800 */
+#define BSEC_SFSRx_SFW11               BSEC_SFSRx_SFW11_Msk                        /*!< Shadowed fuse word (11+32*x) */
+#define BSEC_SFSRx_SFW12_Pos           (12U)
+#define BSEC_SFSRx_SFW12_Msk           (0x1UL << BSEC_SFSRx_SFW12_Pos)              /*!< 0x00001000 */
+#define BSEC_SFSRx_SFW12               BSEC_SFSRx_SFW12_Msk                        /*!< Shadowed fuse word (12+32*x) */
+#define BSEC_SFSRx_SFW13_Pos           (13U)
+#define BSEC_SFSRx_SFW13_Msk           (0x1UL << BSEC_SFSRx_SFW13_Pos)              /*!< 0x00002000 */
+#define BSEC_SFSRx_SFW13               BSEC_SFSRx_SFW13_Msk                        /*!< Shadowed fuse word (13+32*x) */
+#define BSEC_SFSRx_SFW14_Pos           (14U)
+#define BSEC_SFSRx_SFW14_Msk           (0x1UL << BSEC_SFSRx_SFW14_Pos)              /*!< 0x00004000 */
+#define BSEC_SFSRx_SFW14               BSEC_SFSRx_SFW14_Msk                        /*!< Shadowed fuse word (14+32*x) */
+#define BSEC_SFSRx_SFW15_Pos           (15U)
+#define BSEC_SFSRx_SFW15_Msk           (0x1UL << BSEC_SFSRx_SFW15_Pos)              /*!< 0x00008000 */
+#define BSEC_SFSRx_SFW15               BSEC_SFSRx_SFW15_Msk                        /*!< Shadowed fuse word (15+32*x) */
+#define BSEC_SFSRx_SFW16_Pos           (16U)
+#define BSEC_SFSRx_SFW16_Msk           (0x1UL << BSEC_SFSRx_SFW16_Pos)              /*!< 0x00010000 */
+#define BSEC_SFSRx_SFW16               BSEC_SFSRx_SFW16_Msk                        /*!< Shadowed fuse word (16+32*x) */
+#define BSEC_SFSRx_SFW17_Pos           (17U)
+#define BSEC_SFSRx_SFW17_Msk           (0x1UL << BSEC_SFSRx_SFW17_Pos)              /*!< 0x00020000 */
+#define BSEC_SFSRx_SFW17               BSEC_SFSRx_SFW17_Msk                        /*!< Shadowed fuse word (17+32*x) */
+#define BSEC_SFSRx_SFW18_Pos           (18U)
+#define BSEC_SFSRx_SFW18_Msk           (0x1UL << BSEC_SFSRx_SFW18_Pos)              /*!< 0x00040000 */
+#define BSEC_SFSRx_SFW18               BSEC_SFSRx_SFW18_Msk                        /*!< Shadowed fuse word (18+32*x) */
+#define BSEC_SFSRx_SFW19_Pos           (19U)
+#define BSEC_SFSRx_SFW19_Msk           (0x1UL << BSEC_SFSRx_SFW19_Pos)              /*!< 0x00080000 */
+#define BSEC_SFSRx_SFW19               BSEC_SFSRx_SFW19_Msk                        /*!< Shadowed fuse word (19+32*x) */
+#define BSEC_SFSRx_SFW20_Pos           (20U)
+#define BSEC_SFSRx_SFW20_Msk           (0x1UL << BSEC_SFSRx_SFW20_Pos)              /*!< 0x00100000 */
+#define BSEC_SFSRx_SFW20               BSEC_SFSRx_SFW20_Msk                        /*!< Shadowed fuse word (20+32*x) */
+#define BSEC_SFSRx_SFW21_Pos           (21U)
+#define BSEC_SFSRx_SFW21_Msk           (0x1UL << BSEC_SFSRx_SFW21_Pos)              /*!< 0x00200000 */
+#define BSEC_SFSRx_SFW21               BSEC_SFSRx_SFW21_Msk                        /*!< Shadowed fuse word (21+32*x) */
+#define BSEC_SFSRx_SFW22_Pos           (22U)
+#define BSEC_SFSRx_SFW22_Msk           (0x1UL << BSEC_SFSRx_SFW22_Pos)              /*!< 0x00400000 */
+#define BSEC_SFSRx_SFW22               BSEC_SFSRx_SFW22_Msk                        /*!< Shadowed fuse word (22+32*x) */
+#define BSEC_SFSRx_SFW23_Pos           (23U)
+#define BSEC_SFSRx_SFW23_Msk           (0x1UL << BSEC_SFSRx_SFW23_Pos)              /*!< 0x00800000 */
+#define BSEC_SFSRx_SFW23               BSEC_SFSRx_SFW23_Msk                        /*!< Shadowed fuse word (23+32*x) */
+#define BSEC_SFSRx_SFW24_Pos           (24U)
+#define BSEC_SFSRx_SFW24_Msk           (0x1UL << BSEC_SFSRx_SFW24_Pos)              /*!< 0x01000000 */
+#define BSEC_SFSRx_SFW24               BSEC_SFSRx_SFW24_Msk                        /*!< Shadowed fuse word (24+32*x) */
+#define BSEC_SFSRx_SFW25_Pos           (25U)
+#define BSEC_SFSRx_SFW25_Msk           (0x1UL << BSEC_SFSRx_SFW25_Pos)              /*!< 0x02000000 */
+#define BSEC_SFSRx_SFW25               BSEC_SFSRx_SFW25_Msk                        /*!< Shadowed fuse word (25+32*x) */
+#define BSEC_SFSRx_SFW26_Pos           (26U)
+#define BSEC_SFSRx_SFW26_Msk           (0x1UL << BSEC_SFSRx_SFW26_Pos)              /*!< 0x04000000 */
+#define BSEC_SFSRx_SFW26               BSEC_SFSRx_SFW26_Msk                        /*!< Shadowed fuse word (26+32*x) */
+#define BSEC_SFSRx_SFW27_Pos           (27U)
+#define BSEC_SFSRx_SFW27_Msk           (0x1UL << BSEC_SFSRx_SFW27_Pos)              /*!< 0x08000000 */
+#define BSEC_SFSRx_SFW27               BSEC_SFSRx_SFW27_Msk                        /*!< Shadowed fuse word (27+32*x) */
+#define BSEC_SFSRx_SFW28_Pos           (28U)
+#define BSEC_SFSRx_SFW28_Msk           (0x1UL << BSEC_SFSRx_SFW28_Pos)              /*!< 0x10000000 */
+#define BSEC_SFSRx_SFW28               BSEC_SFSRx_SFW28_Msk                        /*!< Shadowed fuse word (28+32*x) */
+#define BSEC_SFSRx_SFW29_Pos           (29U)
+#define BSEC_SFSRx_SFW29_Msk           (0x1UL << BSEC_SFSRx_SFW29_Pos)              /*!< 0x20000000 */
+#define BSEC_SFSRx_SFW29               BSEC_SFSRx_SFW29_Msk                        /*!< Shadowed fuse word (29+32*x) */
+#define BSEC_SFSRx_SFW30_Pos           (30U)
+#define BSEC_SFSRx_SFW30_Msk           (0x1UL << BSEC_SFSRx_SFW30_Pos)              /*!< 0x40000000 */
+#define BSEC_SFSRx_SFW30               BSEC_SFSRx_SFW30_Msk                        /*!< Shadowed fuse word (30+32*x) */
+#define BSEC_SFSRx_SFW31_Pos           (31U)
+#define BSEC_SFSRx_SFW31_Msk           (0x1UL << BSEC_SFSRx_SFW31_Pos)              /*!< 0x80000000 */
+#define BSEC_SFSRx_SFW31               BSEC_SFSRx_SFW31_Msk                        /*!< Shadowed fuse word (31+32*x) */
+
+/******************  Bit definition for BSEC_OTPCR register  ******************/
+#define BSEC_OTPCR_ADDR_Pos            (0U)
+#define BSEC_OTPCR_ADDR_Msk            (0x1FFUL << BSEC_OTPCR_ADDR_Pos)             /*!< 0x000001FF */
+#define BSEC_OTPCR_ADDR                BSEC_OTPCR_ADDR_Msk                         /*!< Fuse word address */
+#define BSEC_OTPCR_PROG_Pos            (13U)
+#define BSEC_OTPCR_PROG_Msk            (0x1UL << BSEC_OTPCR_PROG_Pos)               /*!< 0x00002000 */
+#define BSEC_OTPCR_PROG                BSEC_OTPCR_PROG_Msk                         /*!< Fuse word programming */
+#define BSEC_OTPCR_PPLOCK_Pos          (14U)
+#define BSEC_OTPCR_PPLOCK_Msk          (0x1UL << BSEC_OTPCR_PPLOCK_Pos)             /*!< 0x00004000 */
+#define BSEC_OTPCR_PPLOCK              BSEC_OTPCR_PPLOCK_Msk                       /*!< Permanent programming lock */
+#define BSEC_OTPCR_LASTCID_Pos         (19U)
+#define BSEC_OTPCR_LASTCID_Msk         (0x7UL << BSEC_OTPCR_LASTCID_Pos)            /*!< 0x00380000 */
+#define BSEC_OTPCR_LASTCID             BSEC_OTPCR_LASTCID_Msk                      /*!< Last CID */
+
+/*******************  Bit definition for BSEC_WDR register  *******************/
+#define BSEC_WDR_WRDATA_Pos            (0U)
+#define BSEC_WDR_WRDATA_Msk            (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos)        /*!< 0xFFFFFFFF */
+#define BSEC_WDR_WRDATA                BSEC_WDR_WRDATA_Msk                         /*!< OTP write data */
+
+/****************  Bit definition for BSEC_SCRATCHRx register  ****************/
+#define BSEC_SCRATCHRx_SDATA_Pos       (0U)
+#define BSEC_SCRATCHRx_SDATA_Msk       (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_SCRATCHRx_SDATA           BSEC_SCRATCHRx_SDATA_Msk                    /*!< Scratch data */
+
+/******************  Bit definition for BSEC_LOCKR register  ******************/
+#define BSEC_LOCKR_GWLOCK_Pos          (0U)
+#define BSEC_LOCKR_GWLOCK_Msk          (0x1UL << BSEC_LOCKR_GWLOCK_Pos)             /*!< 0x00000001 */
+#define BSEC_LOCKR_GWLOCK              BSEC_LOCKR_GWLOCK_Msk                       /*!< Global write lock */
+#define BSEC_LOCKR_HKLOCK_Pos          (2U)
+#define BSEC_LOCKR_HKLOCK_Msk          (0x1UL << BSEC_LOCKR_HKLOCK_Pos)             /*!< 0x00000004 */
+#define BSEC_LOCKR_HKLOCK              BSEC_LOCKR_HKLOCK_Msk                       /*!< Hardware key lock */
+
+/*****************  Bit definition for BSEC_JTAGINR register  *****************/
+#define BSEC_JTAGINR_JDATAIN_Pos       (0U)
+#define BSEC_JTAGINR_JDATAIN_Msk       (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_JTAGINR_JDATAIN           BSEC_JTAGINR_JDATAIN_Msk                    /*!< JTAG input data */
+
+/****************  Bit definition for BSEC_JTAGOUTR register  *****************/
+#define BSEC_JTAGOUTR_JDATAOUT_Pos     (0U)
+#define BSEC_JTAGOUTR_JDATAOUT_Msk     (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define BSEC_JTAGOUTR_JDATAOUT         BSEC_JTAGOUTR_JDATAOUT_Msk                  /*!< JTAG output data */
+
+/*****************  Bit definition for BSEC_UNMAPR register  ******************/
+#define BSEC_UNMAPR_UNMAP_Pos          (0U)
+#define BSEC_UNMAPR_UNMAP_Msk          (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos)      /*!< 0xFFFFFFFF */
+#define BSEC_UNMAPR_UNMAP              BSEC_UNMAPR_UNMAP_Msk                       /*!< Unmap key */
+
+/*******************  Bit definition for BSEC_SR register  ********************/
+#define BSEC_SR_HVALID_Pos             (1U)
+#define BSEC_SR_HVALID_Msk             (0x1UL << BSEC_SR_HVALID_Pos)                /*!< 0x00000002 */
+#define BSEC_SR_HVALID                 BSEC_SR_HVALID_Msk                          /*!< Hardware key valid */
+#define BSEC_SR_DBGREQ_Pos             (16U)
+#define BSEC_SR_DBGREQ_Msk             (0x1UL << BSEC_SR_DBGREQ_Pos)                /*!< 0x00010000 */
+#define BSEC_SR_DBGREQ                 BSEC_SR_DBGREQ_Msk                          /*!< Debug request */
+#define BSEC_SR_NVSTATE_Pos            (26U)
+#define BSEC_SR_NVSTATE_Msk            (0x3FUL << BSEC_SR_NVSTATE_Pos)              /*!< 0xFC000000 */
+#define BSEC_SR_NVSTATE                BSEC_SR_NVSTATE_Msk                         /*!< Non-volatile state */
+
+/******************  Bit definition for BSEC_OTPSR register  ******************/
+#define BSEC_OTPSR_BUSY_Pos            (0U)
+#define BSEC_OTPSR_BUSY_Msk            (0x1UL << BSEC_OTPSR_BUSY_Pos)               /*!< 0x00000001 */
+#define BSEC_OTPSR_BUSY                BSEC_OTPSR_BUSY_Msk                         /*!< Busy flag */
+#define BSEC_OTPSR_INIT_DONE_Pos       (1U)
+#define BSEC_OTPSR_INIT_DONE_Msk       (0x1UL << BSEC_OTPSR_INIT_DONE_Pos)          /*!< 0x00000002 */
+#define BSEC_OTPSR_INIT_DONE           BSEC_OTPSR_INIT_DONE_Msk                    /*!< Initialization done */
+#define BSEC_OTPSR_HIDEUP_Pos          (2U)
+#define BSEC_OTPSR_HIDEUP_Msk          (0x1UL << BSEC_OTPSR_HIDEUP_Pos)             /*!< 0x00000004 */
+#define BSEC_OTPSR_HIDEUP              BSEC_OTPSR_HIDEUP_Msk                       /*!< Hide upper fuse words */
+#define BSEC_OTPSR_OTPNVIR_Pos         (4U)
+#define BSEC_OTPSR_OTPNVIR_Msk         (0x1UL << BSEC_OTPSR_OTPNVIR_Pos)            /*!< 0x00000010 */
+#define BSEC_OTPSR_OTPNVIR             BSEC_OTPSR_OTPNVIR_Msk                      /*!< OTP not virgin */
+#define BSEC_OTPSR_OTPERR_Pos          (5U)
+#define BSEC_OTPSR_OTPERR_Msk          (0x1UL << BSEC_OTPSR_OTPERR_Pos)             /*!< 0x00000020 */
+#define BSEC_OTPSR_OTPERR              BSEC_OTPSR_OTPERR_Msk                       /*!< OTP with error */
+#define BSEC_OTPSR_OTPSEC_Pos          (6U)
+#define BSEC_OTPSR_OTPSEC_Msk          (0x1UL << BSEC_OTPSR_OTPSEC_Pos)             /*!< 0x00000040 */
+#define BSEC_OTPSR_OTPSEC              BSEC_OTPSR_OTPSEC_Msk                       /*!< OTP with single error correction */
+#define BSEC_OTPSR_PROGFAIL_Pos        (16U)
+#define BSEC_OTPSR_PROGFAIL_Msk        (0x1UL << BSEC_OTPSR_PROGFAIL_Pos)           /*!< 0x00010000 */
+#define BSEC_OTPSR_PROGFAIL            BSEC_OTPSR_PROGFAIL_Msk                     /*!< Programming failed */
+#define BSEC_OTPSR_DISTURBF_Pos        (17U)
+#define BSEC_OTPSR_DISTURBF_Msk        (0x1UL << BSEC_OTPSR_DISTURBF_Pos)           /*!< 0x00020000 */
+#define BSEC_OTPSR_DISTURBF            BSEC_OTPSR_DISTURBF_Msk                     /*!< Disturb flag */
+#define BSEC_OTPSR_DEDF_Pos            (18U)
+#define BSEC_OTPSR_DEDF_Msk            (0x1UL << BSEC_OTPSR_DEDF_Pos)               /*!< 0x00040000 */
+#define BSEC_OTPSR_DEDF                BSEC_OTPSR_DEDF_Msk                         /*!< Double error detection flag */
+#define BSEC_OTPSR_SECF_Pos            (19U)
+#define BSEC_OTPSR_SECF_Msk            (0x1UL << BSEC_OTPSR_SECF_Pos)               /*!< 0x00080000 */
+#define BSEC_OTPSR_SECF                BSEC_OTPSR_SECF_Msk                         /*!< Single error correction flag */
+#define BSEC_OTPSR_PPLF_Pos            (20U)
+#define BSEC_OTPSR_PPLF_Msk            (0x1UL << BSEC_OTPSR_PPLF_Pos)               /*!< 0x00100000 */
+#define BSEC_OTPSR_PPLF                BSEC_OTPSR_PPLF_Msk                         /*!< Permanent programming lock flag */
+#define BSEC_OTPSR_PPLMF_Pos           (21U)
+#define BSEC_OTPSR_PPLMF_Msk           (0x1UL << BSEC_OTPSR_PPLMF_Pos)              /*!< 0x00200000 */
+#define BSEC_OTPSR_PPLMF               BSEC_OTPSR_PPLMF_Msk                        /*!< Permanent programming lock mismatch flag */
+#define BSEC_OTPSR_AMEF_Pos            (22U)
+#define BSEC_OTPSR_AMEF_Msk            (0x1UL << BSEC_OTPSR_AMEF_Pos)               /*!< 0x00400000 */
+#define BSEC_OTPSR_AMEF                BSEC_OTPSR_AMEF_Msk                         /*!< Addresses mismatch error flag */
+
+/*****************  Bit definition for BSEC_EPOCHRx register  *****************/
+#define BSEC_EPOCHRx_EPOCH_Pos         (0U)
+#define BSEC_EPOCHRx_EPOCH_Msk         (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos)     /*!< 0xFFFFFFFF */
+#define BSEC_EPOCHRx_EPOCH             BSEC_EPOCHRx_EPOCH_Msk                      /*!< Epoch */
+
+/****************  Bit definition for BSEC_EPOCHSELR register  ****************/
+#define BSEC_EPOCHSELR_EPSEL_Pos       (0U)
+#define BSEC_EPOCHSELR_EPSEL_Msk       (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos)          /*!< 0x00000001 */
+#define BSEC_EPOCHSELR_EPSEL           BSEC_EPOCHSELR_EPSEL_Msk                    /*!< Epoch selection */
+
+/******************  Bit definition for BSEC_DBGCR register  ******************/
+#define BSEC_DBGCR_UNLOCK_Pos          (8U)
+#define BSEC_DBGCR_UNLOCK_Msk          (0xFFUL << BSEC_DBGCR_UNLOCK_Pos)            /*!< 0x0000FF00 */
+#define BSEC_DBGCR_UNLOCK              BSEC_DBGCR_UNLOCK_Msk                       /*!< Non-secure debug authorization */
+#define BSEC_DBGCR_AUTH_HDPL_Pos       (16U)
+#define BSEC_DBGCR_AUTH_HDPL_Msk       (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos)         /*!< 0x00FF0000 */
+#define BSEC_DBGCR_AUTH_HDPL           BSEC_DBGCR_AUTH_HDPL_Msk                    /*!< Level at which debug may be opened */
+#define BSEC_DBGCR_AUTH_SEC_Pos        (24U)
+#define BSEC_DBGCR_AUTH_SEC_Msk        (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos)          /*!< 0xFF000000 */
+#define BSEC_DBGCR_AUTH_SEC            BSEC_DBGCR_AUTH_SEC_Msk                     /*!< Secure debug authorization */
+
+/***************  Bit definition for BSEC_AP_UNLOCK register  *****************/
+#define BSEC_AP_UNLOCK_UNLOCK_Pos      (0U)
+#define BSEC_AP_UNLOCK_UNLOCK_Msk      (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos)        /*!< 0x000000FF */
+#define BSEC_AP_UNLOCK_UNLOCK          BSEC_AP_UNLOCK_UNLOCK_Msk                   /*!< Unlock DBG_MCU AP interface */
+
+/*****************  Bit definition for BSEC_HDPLSR register  ******************/
+#define BSEC_HDPLSR_HDPL_Pos           (0U)
+#define BSEC_HDPLSR_HDPL_Msk           (0xFFUL << BSEC_HDPLSR_HDPL_Pos)             /*!< 0x000000FF */
+#define BSEC_HDPLSR_HDPL               BSEC_HDPLSR_HDPL_Msk                        /*!< Current HDPL */
+
+/*****************  Bit definition for BSEC_HDPLCR register  ******************/
+#define BSEC_HDPLCR_INCR_HDPL_Pos      (0U)
+#define BSEC_HDPLCR_INCR_HDPL_Msk      (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos)  /*!< 0xFFFFFFFF */
+#define BSEC_HDPLCR_INCR_HDPL          BSEC_HDPLCR_INCR_HDPL_Msk                   /*!< Increment HDPL */
+
+/*****************  Bit definition for BSEC_NEXTLR register  ******************/
+#define BSEC_NEXTLR_INCR_Pos           (0U)
+#define BSEC_NEXTLR_INCR_Msk           (0x3UL << BSEC_NEXTLR_INCR_Pos)              /*!< 0x00000003 */
+#define BSEC_NEXTLR_INCR               BSEC_NEXTLR_INCR_Msk                        /*!< Increment */
+
+/*****************  Bit definition for BSEC_WOSCRx register  ******************/
+#define BSEC_WOSCRx_WOSDATA_Pos        (0U)
+#define BSEC_WOSCRx_WOSDATA_Msk        (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos)    /*!< 0xFFFFFFFF */
+#define BSEC_WOSCRx_WOSDATA            BSEC_WOSCRx_WOSDATA_Msk                     /*!< Write once scratch data */
+
+/******************  Bit definition for BSEC_HRCR register  *******************/
+#define BSEC_HRCR_HRC_Pos              (0U)
+#define BSEC_HRCR_HRC_Msk              (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_HRCR_HRC                  BSEC_HRCR_HRC_Msk                           /*!< Hot reset counter */
+
+/******************  Bit definition for BSEC_WRCR register  *******************/
+#define BSEC_WRCR_WRC_Pos              (0U)
+#define BSEC_WRCR_WRC_Msk              (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_WRCR_WRC                  BSEC_WRCR_WRC_Msk                           /*!< Warm reset counter */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 CACHEAXI                                   */
+/*                                                                            */
+/******************************************************************************/
+/****************  Bit definition for CACHEAXI_CR1 register  ******************/
+#define CACHEAXI_CR1_EN_Pos                   (0U)
+#define CACHEAXI_CR1_EN_Msk                   (0x1UL << CACHEAXI_CR1_EN_Pos)             /*!< 0x00000001 */
+#define CACHEAXI_CR1_EN                       CACHEAXI_CR1_EN_Msk                        /*!< Enable */
+#define CACHEAXI_CR1_CACHEINV_Pos             (1U)
+#define CACHEAXI_CR1_CACHEINV_Msk             (0x1UL << CACHEAXI_CR1_CACHEINV_Pos)       /*!< 0x00000002 */
+#define CACHEAXI_CR1_CACHEINV                 CACHEAXI_CR1_CACHEINV_Msk                  /*!< Cache invalidation */
+#define CACHEAXI_CR1_RHITMEN_Pos              (16U)
+#define CACHEAXI_CR1_RHITMEN_Msk              (0x1UL << CACHEAXI_CR1_RHITMEN_Pos)        /*!< 0x00010000 */
+#define CACHEAXI_CR1_RHITMEN                  CACHEAXI_CR1_RHITMEN_Msk                   /*!< Read Hit monitor enable */
+#define CACHEAXI_CR1_RMISSMEN_Pos             (17U)
+#define CACHEAXI_CR1_RMISSMEN_Msk             (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos)       /*!< 0x00020000 */
+#define CACHEAXI_CR1_RMISSMEN                 CACHEAXI_CR1_RMISSMEN_Msk                  /*!< Read Miss monitor enable */
+#define CACHEAXI_CR1_RHITMRST_Pos             (18U)
+#define CACHEAXI_CR1_RHITMRST_Msk             (0x1UL << CACHEAXI_CR1_RHITMRST_Pos)       /*!< 0x00040000 */
+#define CACHEAXI_CR1_RHITMRST                 CACHEAXI_CR1_RHITMRST_Msk                  /*!< Read Hit monitor reset */
+#define CACHEAXI_CR1_RMISSMRST_Pos            (19U)
+#define CACHEAXI_CR1_RMISSMRST_Msk            (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos)      /*!< 0x00080000 */
+#define CACHEAXI_CR1_RMISSMRST                CACHEAXI_CR1_RMISSMRST_Msk                 /*!< Read Miss monitor reset */
+#define CACHEAXI_CR1_WHITMEN_Pos              (20U)
+#define CACHEAXI_CR1_WHITMEN_Msk              (0x1UL << CACHEAXI_CR1_WHITMEN_Pos)        /*!< 0x00100000 */
+#define CACHEAXI_CR1_WHITMEN                  CACHEAXI_CR1_WHITMEN_Msk                   /*!< Write Hit monitor enable */
+#define CACHEAXI_CR1_WMISSMEN_Pos             (21U)
+#define CACHEAXI_CR1_WMISSMEN_Msk             (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos)       /*!< 0x00200000 */
+#define CACHEAXI_CR1_WMISSMEN                 CACHEAXI_CR1_WMISSMEN_Msk                  /*!< Write Miss monitor enable */
+#define CACHEAXI_CR1_WHITMRST_Pos             (22U)
+#define CACHEAXI_CR1_WHITMRST_Msk             (0x1UL << CACHEAXI_CR1_WHITMRST_Pos)       /*!< 0x00400000 */
+#define CACHEAXI_CR1_WHITMRST                 CACHEAXI_CR1_WHITMRST_Msk                  /*!< Write Hit monitor reset */
+#define CACHEAXI_CR1_WMISSMRST_Pos            (23U)
+#define CACHEAXI_CR1_WMISSMRST_Msk            (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos)      /*!< 0x00800000 */
+#define CACHEAXI_CR1_WMISSMRST                CACHEAXI_CR1_WMISSMRST_Msk                 /*!< Write Miss monitor reset */
+#define CACHEAXI_CR1_RAMMEN_Pos               (24U)
+#define CACHEAXI_CR1_RAMMEN_Msk               (0x1UL << CACHEAXI_CR1_RAMMEN_Pos)         /*!< 0x01000000 */
+#define CACHEAXI_CR1_RAMMEN                   CACHEAXI_CR1_RAMMEN_Msk                    /*!< Read-allocate miss monitor enable */
+#define CACHEAXI_CR1_WAMMEN_Pos               (25U)
+#define CACHEAXI_CR1_WAMMEN_Msk               (0x1UL << CACHEAXI_CR1_WAMMEN_Pos)         /*!< 0x02000000 */
+#define CACHEAXI_CR1_WAMMEN                   CACHEAXI_CR1_WAMMEN_Msk                    /*!< Write-allocate miss monitor enable */
+#define CACHEAXI_CR1_RAMMRST_Pos              (26U)
+#define CACHEAXI_CR1_RAMMRST_Msk              (0x1UL << CACHEAXI_CR1_RAMMRST_Pos)        /*!< 0x04000000 */
+#define CACHEAXI_CR1_RAMMRST                  CACHEAXI_CR1_RAMMRST_Msk                   /*!< Read-allocate miss monitor reset */
+#define CACHEAXI_CR1_WAMMRST_Pos              (27U)
+#define CACHEAXI_CR1_WAMMRST_Msk              (0x1UL << CACHEAXI_CR1_WAMMRST_Pos)        /*!< 0x08000000 */
+#define CACHEAXI_CR1_WAMMRST                  CACHEAXI_CR1_WAMMRST_Msk                   /*!< Write-allocate miss monitor reset */
+#define CACHEAXI_CR1_WTMEN_Pos                (28U)
+#define CACHEAXI_CR1_WTMEN_Msk                (0x1UL << CACHEAXI_CR1_WTMEN_Pos)          /*!< 0x10000000 */
+#define CACHEAXI_CR1_WTMEN                    CACHEAXI_CR1_WTMEN_Msk                     /*!< Write-through monitor enable */
+#define CACHEAXI_CR1_EVIMEN_Pos               (29U)
+#define CACHEAXI_CR1_EVIMEN_Msk               (0x1UL << CACHEAXI_CR1_EVIMEN_Pos)         /*!< 0x20000000 */
+#define CACHEAXI_CR1_EVIMEN                   CACHEAXI_CR1_EVIMEN_Msk                    /*!< Eviction monitor enable */
+#define CACHEAXI_CR1_WTMRST_Pos               (30U)
+#define CACHEAXI_CR1_WTMRST_Msk               (0x1UL << CACHEAXI_CR1_WTMRST_Pos)         /*!< 0x40000000 */
+#define CACHEAXI_CR1_WTMRST                   CACHEAXI_CR1_WTMRST_Msk                    /*!< Write-through monitor reset */
+#define CACHEAXI_CR1_EVIMRST_Pos              (31U)
+#define CACHEAXI_CR1_EVIMRST_Msk              (0x1UL << CACHEAXI_CR1_EVIMRST_Pos)        /*!< 0x80000000 */
+#define CACHEAXI_CR1_EVIMRST                  CACHEAXI_CR1_EVIMRST_Msk                   /*!< Eviction monitor reset */
+
+/******************  Bit definition for CACHEAXI_SR register  *******************/
+#define CACHEAXI_SR_BUSYF_Pos                 (0U)
+#define CACHEAXI_SR_BUSYF_Msk                 (0x1UL << CACHEAXI_SR_BUSYF_Pos)           /*!< 0x00000001 */
+#define CACHEAXI_SR_BUSYF                     CACHEAXI_SR_BUSYF_Msk                      /*!< Busy flag */
+#define CACHEAXI_SR_BSYENDF_Pos               (1U)
+#define CACHEAXI_SR_BSYENDF_Msk               (0x1UL << CACHEAXI_SR_BSYENDF_Pos)         /*!< 0x00000002 */
+#define CACHEAXI_SR_BSYENDF                   CACHEAXI_SR_BSYENDF_Msk                    /*!< Busy end flag */
+#define CACHEAXI_SR_ERRF_Pos                  (2U)
+#define CACHEAXI_SR_ERRF_Msk                  (0x1UL << CACHEAXI_SR_ERRF_Pos)            /*!< 0x00000004 */
+#define CACHEAXI_SR_ERRF                      CACHEAXI_SR_ERRF_Msk                       /*!< Cache error flag */
+#define CACHEAXI_SR_BUSYCMDF_Pos              (3U)
+#define CACHEAXI_SR_BUSYCMDF_Msk              (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos)        /*!< 0x00000008 */
+#define CACHEAXI_SR_BUSYCMDF                  CACHEAXI_SR_BUSYCMDF_Msk                   /*!< Busy command flag */
+#define CACHEAXI_SR_CMDENDF_Pos               (4U)
+#define CACHEAXI_SR_CMDENDF_Msk               (0x1UL << CACHEAXI_SR_CMDENDF_Pos)         /*!< 0x00000010 */
+#define CACHEAXI_SR_CMDENDF                   CACHEAXI_SR_CMDENDF_Msk                    /*!< Command end flag */
+
+/******************  Bit definition for CACHEAXI_IER register  ******************/
+#define CACHEAXI_IER_BSYENDIE_Pos             (1U)
+#define CACHEAXI_IER_BSYENDIE_Msk             (0x1UL << CACHEAXI_IER_BSYENDIE_Pos)       /*!< 0x00000002 */
+#define CACHEAXI_IER_BSYENDIE                 CACHEAXI_IER_BSYENDIE_Msk                  /*!< Busy end interrupt enable */
+#define CACHEAXI_IER_ERRIE_Pos                (2U)
+#define CACHEAXI_IER_ERRIE_Msk                (0x1UL << CACHEAXI_IER_ERRIE_Pos)          /*!< 0x00000004 */
+#define CACHEAXI_IER_ERRIE                    CACHEAXI_IER_ERRIE_Msk                     /*!< Cache error interrupt enable */
+#define CACHEAXI_IER_CMDENDIE_Pos             (4U)
+#define CACHEAXI_IER_CMDENDIE_Msk             (0x1UL << CACHEAXI_IER_CMDENDIE_Pos)       /*!< 0x00000010 */
+#define CACHEAXI_IER_CMDENDIE                 CACHEAXI_IER_CMDENDIE_Msk                  /*!< Command end interrupt enable */
+
+/******************  Bit definition for CACHEAXI_FCR register  ******************/
+#define CACHEAXI_FCR_CBSYENDF_Pos             (1U)
+#define CACHEAXI_FCR_CBSYENDF_Msk             (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos)       /*!< 0x00000002 */
+#define CACHEAXI_FCR_CBSYENDF                 CACHEAXI_FCR_CBSYENDF_Msk                  /*!< Busy end flag clear */
+#define CACHEAXI_FCR_CERRF_Pos                (2U)
+#define CACHEAXI_FCR_CERRF_Msk                (0x1UL << CACHEAXI_FCR_CERRF_Pos)          /*!< 0x00000004 */
+#define CACHEAXI_FCR_CERRF                    CACHEAXI_FCR_CERRF_Msk                     /*!< Cache error flag clear */
+#define CACHEAXI_FCR_CCMDENDF_Pos             (4U)
+#define CACHEAXI_FCR_CCMDENDF_Msk             (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos)       /*!< 0x00000010 */
+#define CACHEAXI_FCR_CCMDENDF                 CACHEAXI_FCR_CCMDENDF_Msk                  /*!< Command end flag clear */
+
+/******************  Bit definition for CACHEAXI_RHMONR register  ****************/
+#define CACHEAXI_RHMONR_RHITMON_Pos           (0U)
+#define CACHEAXI_RHMONR_RHITMON_Msk           (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_RHMONR_RHITMON               CACHEAXI_RHMONR_RHITMON_Msk                    /*!< Cache read hit monitor register */
+
+/******************  Bit definition for CACHEAXI_RMMONR register  ****************/
+#define CACHEAXI_RMMONR_RMISSMON_Pos          (0U)
+#define CACHEAXI_RMMONR_RMISSMON_Msk          (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */
+#define CACHEAXI_RMMONR_RMISSMON              CACHEAXI_RMMONR_RMISSMON_Msk                   /*!< Cache read miss monitor register */
+
+/******************  Bit definition for CACHEAXI_RAMMONR register  ****************/
+#define CACHEAXI_RAMMONR_RAMMON_Pos           (0U)
+#define CACHEAXI_RAMMONR_RAMMON_Msk           (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_RAMMONR_RAMMON               CACHEAXI_RAMMONR_RAMMON_Msk                    /*!< Cache read-allocate miss monitor counter */
+
+/******************  Bit definition for CACHEAXI_EVIMONR register  ****************/
+#define CACHEAXI_EVIMONR_EVIMON_Pos           (0U)
+#define CACHEAXI_EVIMONR_EVIMON_Msk           (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_EVIMONR_EVIMON               CACHEAXI_EVIMONR_EVIMON_Msk                    /*!< Cache eviction monitor counter */
+
+/******************  Bit definition for CACHEAXI_WHMONR register  ****************/
+#define CACHEAXI_WHMONR_WHITMON_Pos           (0U)
+#define CACHEAXI_WHMONR_WHITMON_Msk           (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_WHMONR_WHITMON               CACHEAXI_WHMONR_WHITMON_Msk                    /*!< Cache write hit monitor register */
+
+/******************  Bit definition for CACHEAXI_WMMONR register  ****************/
+#define CACHEAXI_WMMONR_WMISSMON_Pos          (0U)
+#define CACHEAXI_WMMONR_WMISSMON_Msk          (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */
+#define CACHEAXI_WMMONR_WMISSMON              CACHEAXI_WMMONR_WMISSMON_Msk                   /*!< Cache write miss monitor register */
+
+/******************  Bit definition for CACHEAXI_WAMMONR register  ****************/
+#define CACHEAXI_WAMMONR_WAMMON_Pos           (0U)
+#define CACHEAXI_WAMMONR_WAMMON_Msk           (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_WAMMONR_WAMMON               CACHEAXI_WAMMONR_WAMMON_Msk                    /*!< Cache write-allocate miss monitor register */
+
+/******************  Bit definition for CACHEAXI_WTMONR register  ****************/
+#define CACHEAXI_WTMONR_WTMON_Pos             (0U)
+#define CACHEAXI_WTMONR_WTMON_Msk             (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos)    /*!< 0xFFFFFFFF */
+#define CACHEAXI_WTMONR_WTMON                 CACHEAXI_WTMONR_WTMON_Msk                      /*!< Cache write-through monitor register */
+
+/****************  Bit definition for CACHEAXI_CR2 register  ******************/
+#define CACHEAXI_CR2_STARTCMD_Pos             (0U)
+#define CACHEAXI_CR2_STARTCMD_Msk             (0x1UL << CACHEAXI_CR2_STARTCMD_Pos)           /*!< 0x00000001 */
+#define CACHEAXI_CR2_STARTCMD                 CACHEAXI_CR2_STARTCMD_Msk                      /*!< Starts maintenance range command */
+#define CACHEAXI_CR2_CACHECMD_Pos             (1U)
+#define CACHEAXI_CR2_CACHECMD_Msk             (0x3UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000006 */
+#define CACHEAXI_CR2_CACHECMD                 CACHEAXI_CR2_CACHECMD_Msk                      /*!< Cache command maintenance operation */
+#define CACHEAXI_CR2_CACHECMD_0               (0x1UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000002 */
+#define CACHEAXI_CR2_CACHECMD_1               (0x2UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000004 */
+
+/******************  Bit definition for CACHEAXI_CMDRSADDRR register  ****************/
+#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos  (0U)
+#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk  (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */
+#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR      CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk           /*!< Command start address */
+
+/******************  Bit definition for CACHEAXI_CMDREADDRR register  ****************/
+#define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos    (0U)
+#define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk    (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos)   /*!< 0xFFFFFFC0 */
+#define CACHEAXI_CMDREADDRR_CMDENDADDR        CACHEAXI_CMDREADDRR_CMDENDADDR_Msk             /*!< Command end address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos              (0U)
+#define CRC_DR_DR_Msk              (0xFFFFFFFFUL << CRC_DR_DR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                  CRC_DR_DR_Msk                               /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos            (0U)
+#define CRC_IDR_IDR_Msk            (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR                CRC_IDR_IDR_Msk                             /*!< General-purpose 32-bits data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos           (0U)
+#define CRC_CR_RESET_Msk           (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
+#define CRC_CR_RESET               CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos        (3U)
+#define CRC_CR_POLYSIZE_Msk        (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE            CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0          (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1          (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos          (5U)
+#define CRC_CR_REV_IN_Msk          (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
+#define CRC_CR_REV_IN              CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0            (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1            (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos         (7U)
+#define CRC_CR_REV_OUT_Msk         (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
+#define CRC_CR_REV_OUT             CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
+#define CRC_CR_REV_OUT_0           (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
+#define CRC_CR_REV_OUT_1           (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
+#define CRC_CR_RTYPE_IN_Pos        (9U)
+#define CRC_CR_RTYPE_IN_Msk        (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
+#define CRC_CR_RTYPE_IN            CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
+#define CRC_CR_RTYPE_OUT_Pos       (10U)
+#define CRC_CR_RTYPE_OUT_Msk       (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
+#define CRC_CR_RTYPE_OUT           CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos          (0U)
+#define CRC_INIT_INIT_Msk          (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)         /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT              CRC_INIT_INIT_Msk                           /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos            (0U)
+#define CRC_POL_POL_Msk            (0xFFFFFFFFUL << CRC_POL_POL_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_POL_POL                CRC_POL_POL_Msk                             /*!< Coefficients of the polynomial */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (CSI)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CSI_CR register  ********************/
+#define CSI_CR_CSIEN_Pos                (0U)
+#define CSI_CR_CSIEN_Msk                (0x1UL << CSI_CR_CSIEN_Pos)               /*!< 0x00000001 */
+#define CSI_CR_CSIEN                    CSI_CR_CSIEN_Msk                         /*!< CSI-2 enable */
+#define CSI_CR_VC0START_Pos             (2U)
+#define CSI_CR_VC0START_Msk             (0x1UL << CSI_CR_VC0START_Pos)            /*!< 0x00000004 */
+#define CSI_CR_VC0START                 CSI_CR_VC0START_Msk                      /*!< Virtual channel 0 start */
+#define CSI_CR_VC0STOP_Pos              (3U)
+#define CSI_CR_VC0STOP_Msk              (0x1UL << CSI_CR_VC0STOP_Pos)             /*!< 0x00000008 */
+#define CSI_CR_VC0STOP                  CSI_CR_VC0STOP_Msk                       /*!< Virtual channel 0 stop */
+#define CSI_CR_VC1START_Pos             (6U)
+#define CSI_CR_VC1START_Msk             (0x1UL << CSI_CR_VC1START_Pos)            /*!< 0x00000040 */
+#define CSI_CR_VC1START                 CSI_CR_VC1START_Msk                      /*!< Virtual channel 1 start */
+#define CSI_CR_VC1STOP_Pos              (7U)
+#define CSI_CR_VC1STOP_Msk              (0x1UL << CSI_CR_VC1STOP_Pos)             /*!< 0x00000080 */
+#define CSI_CR_VC1STOP                  CSI_CR_VC1STOP_Msk                       /*!< Virtual channel 1 stop */
+#define CSI_CR_VC2START_Pos             (10U)
+#define CSI_CR_VC2START_Msk             (0x1UL << CSI_CR_VC2START_Pos)            /*!< 0x00000400 */
+#define CSI_CR_VC2START                 CSI_CR_VC2START_Msk                      /*!< Virtual channel 2 start */
+#define CSI_CR_VC2STOP_Pos              (11U)
+#define CSI_CR_VC2STOP_Msk              (0x1UL << CSI_CR_VC2STOP_Pos)             /*!< 0x00000800 */
+#define CSI_CR_VC2STOP                  CSI_CR_VC2STOP_Msk                       /*!< Virtual channel 2 stop */
+#define CSI_CR_VC3START_Pos             (14U)
+#define CSI_CR_VC3START_Msk             (0x1UL << CSI_CR_VC3START_Pos)            /*!< 0x00004000 */
+#define CSI_CR_VC3START                 CSI_CR_VC3START_Msk                      /*!< Virtual channel 3 start */
+#define CSI_CR_VC3STOP_Pos              (15U)
+#define CSI_CR_VC3STOP_Msk              (0x1UL << CSI_CR_VC3STOP_Pos)             /*!< 0x00008000 */
+#define CSI_CR_VC3STOP                  CSI_CR_VC3STOP_Msk                       /*!< Virtual channel 3 stop */
+
+/*******************  Bit definition for CSI_PCR register  ********************/
+#define CSI_PCR_PWRDOWN_Pos             (0U)
+#define CSI_PCR_PWRDOWN_Msk             (0x1UL << CSI_PCR_PWRDOWN_Pos)            /*!< 0x00000001 */
+#define CSI_PCR_PWRDOWN                 CSI_PCR_PWRDOWN_Msk                      /*!< Virtual channel 3 start */
+#define CSI_PCR_CLEN_Pos                (1U)
+#define CSI_PCR_CLEN_Msk                (0x1UL << CSI_PCR_CLEN_Pos)               /*!< 0x00000002 */
+#define CSI_PCR_CLEN                    CSI_PCR_CLEN_Msk                         /*!< Clock lane enable */
+#define CSI_PCR_DL0EN_Pos               (2U)
+#define CSI_PCR_DL0EN_Msk               (0x1UL << CSI_PCR_DL0EN_Pos)              /*!< 0x00000004 */
+#define CSI_PCR_DL0EN                   CSI_PCR_DL0EN_Msk                        /*!< D-PHY_RX data lane 0 enable */
+#define CSI_PCR_DL1EN_Pos               (3U)
+#define CSI_PCR_DL1EN_Msk               (0x1UL << CSI_PCR_DL1EN_Pos)              /*!< 0x00000008 */
+#define CSI_PCR_DL1EN                   CSI_PCR_DL1EN_Msk                        /*!< D-PHY_RX data lane 1 enable */
+
+/*****************  Bit definition for CSI_VC0CFGR1 register  *****************/
+#define CSI_VC0CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC0CFGR1_ALLDT_Msk          (0x1UL << CSI_VC0CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC0CFGR1_ALLDT              CSI_VC0CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC0CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC0CFGR1_DT0EN_Msk          (0x1UL << CSI_VC0CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC0CFGR1_DT0EN              CSI_VC0CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC0CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC0CFGR1_DT1EN_Msk          (0x1UL << CSI_VC0CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC0CFGR1_DT1EN              CSI_VC0CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC0CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC0CFGR1_DT2EN_Msk          (0x1UL << CSI_VC0CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC0CFGR1_DT2EN              CSI_VC0CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC0CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC0CFGR1_DT3EN_Msk          (0x1UL << CSI_VC0CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC0CFGR1_DT3EN              CSI_VC0CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC0CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC0CFGR1_DT4EN_Msk          (0x1UL << CSI_VC0CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC0CFGR1_DT4EN              CSI_VC0CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC0CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC0CFGR1_DT5EN_Msk          (0x1UL << CSI_VC0CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC0CFGR1_DT5EN              CSI_VC0CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC0CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC0CFGR1_DT6EN_Msk          (0x1UL << CSI_VC0CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC0CFGR1_DT6EN              CSI_VC0CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC0CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC0CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR1_CDTFT              CSI_VC0CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC0CFGR1_DT0_Pos            (16U)
+#define CSI_VC0CFGR1_DT0_Msk            (0x3FUL << CSI_VC0CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR1_DT0                CSI_VC0CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC0CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC0CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR1_DT0FT              CSI_VC0CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC0CFGR2 register  *****************/
+#define CSI_VC0CFGR2_DT1_Pos            (0U)
+#define CSI_VC0CFGR2_DT1_Msk            (0x3FUL << CSI_VC0CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR2_DT1                CSI_VC0CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC0CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR2_DT1FT              CSI_VC0CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC0CFGR2_DT2_Pos            (16U)
+#define CSI_VC0CFGR2_DT2_Msk            (0x3FUL << CSI_VC0CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR2_DT2                CSI_VC0CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC0CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR2_DT2FT              CSI_VC0CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC0CFGR3 register  *****************/
+#define CSI_VC0CFGR3_DT3_Pos            (0U)
+#define CSI_VC0CFGR3_DT3_Msk            (0x3FUL << CSI_VC0CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR3_DT3                CSI_VC0CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC0CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR3_DT3FT              CSI_VC0CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC0CFGR3_DT4_Pos            (16U)
+#define CSI_VC0CFGR3_DT4_Msk            (0x3FUL << CSI_VC0CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR3_DT4                CSI_VC0CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC0CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR3_DT4FT              CSI_VC0CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC0CFGR4 register  *****************/
+#define CSI_VC0CFGR4_DT5_Pos            (0U)
+#define CSI_VC0CFGR4_DT5_Msk            (0x3FUL << CSI_VC0CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR4_DT5                CSI_VC0CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC0CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR4_DT5FT              CSI_VC0CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC0CFGR4_DT6_Pos            (16U)
+#define CSI_VC0CFGR4_DT6_Msk            (0x3FUL << CSI_VC0CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR4_DT6                CSI_VC0CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC0CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR4_DT6FT              CSI_VC0CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC1CFGR1 register  *****************/
+#define CSI_VC1CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC1CFGR1_ALLDT_Msk          (0x1UL << CSI_VC1CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC1CFGR1_ALLDT              CSI_VC1CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC1CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC1CFGR1_DT0EN_Msk          (0x1UL << CSI_VC1CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC1CFGR1_DT0EN              CSI_VC1CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC1CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC1CFGR1_DT1EN_Msk          (0x1UL << CSI_VC1CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC1CFGR1_DT1EN              CSI_VC1CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC1CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC1CFGR1_DT2EN_Msk          (0x1UL << CSI_VC1CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC1CFGR1_DT2EN              CSI_VC1CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC1CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC1CFGR1_DT3EN_Msk          (0x1UL << CSI_VC1CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC1CFGR1_DT3EN              CSI_VC1CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC1CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC1CFGR1_DT4EN_Msk          (0x1UL << CSI_VC1CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC1CFGR1_DT4EN              CSI_VC1CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC1CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC1CFGR1_DT5EN_Msk          (0x1UL << CSI_VC1CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC1CFGR1_DT5EN              CSI_VC1CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC1CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC1CFGR1_DT6EN_Msk          (0x1UL << CSI_VC1CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC1CFGR1_DT6EN              CSI_VC1CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC1CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC1CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR1_CDTFT              CSI_VC1CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC1CFGR1_DT0_Pos            (16U)
+#define CSI_VC1CFGR1_DT0_Msk            (0x3FUL << CSI_VC1CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR1_DT0                CSI_VC1CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC1CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC1CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR1_DT0FT              CSI_VC1CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC1CFGR2 register  *****************/
+#define CSI_VC1CFGR2_DT1_Pos            (0U)
+#define CSI_VC1CFGR2_DT1_Msk            (0x3FUL << CSI_VC1CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR2_DT1                CSI_VC1CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC1CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR2_DT1FT              CSI_VC1CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC1CFGR2_DT2_Pos            (16U)
+#define CSI_VC1CFGR2_DT2_Msk            (0x3FUL << CSI_VC1CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR2_DT2                CSI_VC1CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC1CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR2_DT2FT              CSI_VC1CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC1CFGR3 register  *****************/
+#define CSI_VC1CFGR3_DT3_Pos            (0U)
+#define CSI_VC1CFGR3_DT3_Msk            (0x3FUL << CSI_VC1CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR3_DT3                CSI_VC1CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC1CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR3_DT3FT              CSI_VC1CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC1CFGR3_DT4_Pos            (16U)
+#define CSI_VC1CFGR3_DT4_Msk            (0x3FUL << CSI_VC1CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR3_DT4                CSI_VC1CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC1CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR3_DT4FT              CSI_VC1CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC1CFGR4 register  *****************/
+#define CSI_VC1CFGR4_DT5_Pos            (0U)
+#define CSI_VC1CFGR4_DT5_Msk            (0x3FUL << CSI_VC1CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR4_DT5                CSI_VC1CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC1CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR4_DT5FT              CSI_VC1CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC1CFGR4_DT6_Pos            (16U)
+#define CSI_VC1CFGR4_DT6_Msk            (0x3FUL << CSI_VC1CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR4_DT6                CSI_VC1CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC1CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR4_DT6FT              CSI_VC1CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC2CFGR1 register  *****************/
+#define CSI_VC2CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC2CFGR1_ALLDT_Msk          (0x1UL << CSI_VC2CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC2CFGR1_ALLDT              CSI_VC2CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC2CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC2CFGR1_DT0EN_Msk          (0x1UL << CSI_VC2CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC2CFGR1_DT0EN              CSI_VC2CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC2CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC2CFGR1_DT1EN_Msk          (0x1UL << CSI_VC2CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC2CFGR1_DT1EN              CSI_VC2CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC2CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC2CFGR1_DT2EN_Msk          (0x1UL << CSI_VC2CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC2CFGR1_DT2EN              CSI_VC2CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC2CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC2CFGR1_DT3EN_Msk          (0x1UL << CSI_VC2CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC2CFGR1_DT3EN              CSI_VC2CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC2CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC2CFGR1_DT4EN_Msk          (0x1UL << CSI_VC2CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC2CFGR1_DT4EN              CSI_VC2CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC2CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC2CFGR1_DT5EN_Msk          (0x1UL << CSI_VC2CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC2CFGR1_DT5EN              CSI_VC2CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC2CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC2CFGR1_DT6EN_Msk          (0x1UL << CSI_VC2CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC2CFGR1_DT6EN              CSI_VC2CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC2CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC2CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR1_CDTFT              CSI_VC2CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC2CFGR1_DT0_Pos            (16U)
+#define CSI_VC2CFGR1_DT0_Msk            (0x3FUL << CSI_VC2CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR1_DT0                CSI_VC2CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC2CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC2CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR1_DT0FT              CSI_VC2CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC2CFGR2 register  *****************/
+#define CSI_VC2CFGR2_DT1_Pos            (0U)
+#define CSI_VC2CFGR2_DT1_Msk            (0x3FUL << CSI_VC2CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR2_DT1                CSI_VC2CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC2CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR2_DT1FT              CSI_VC2CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC2CFGR2_DT2_Pos            (16U)
+#define CSI_VC2CFGR2_DT2_Msk            (0x3FUL << CSI_VC2CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR2_DT2                CSI_VC2CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC2CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR2_DT2FT              CSI_VC2CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC2CFGR3 register  *****************/
+#define CSI_VC2CFGR3_DT3_Pos            (0U)
+#define CSI_VC2CFGR3_DT3_Msk            (0x3FUL << CSI_VC2CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR3_DT3                CSI_VC2CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC2CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR3_DT3FT              CSI_VC2CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC2CFGR3_DT4_Pos            (16U)
+#define CSI_VC2CFGR3_DT4_Msk            (0x3FUL << CSI_VC2CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR3_DT4                CSI_VC2CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC2CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR3_DT4FT              CSI_VC2CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC2CFGR4 register  *****************/
+#define CSI_VC2CFGR4_DT5_Pos            (0U)
+#define CSI_VC2CFGR4_DT5_Msk            (0x3FUL << CSI_VC2CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR4_DT5                CSI_VC2CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC2CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR4_DT5FT              CSI_VC2CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC2CFGR4_DT6_Pos            (16U)
+#define CSI_VC2CFGR4_DT6_Msk            (0x3FUL << CSI_VC2CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR4_DT6                CSI_VC2CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC2CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR4_DT6FT              CSI_VC2CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC3CFGR1 register  *****************/
+#define CSI_VC3CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC3CFGR1_ALLDT_Msk          (0x1UL << CSI_VC3CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC3CFGR1_ALLDT              CSI_VC3CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC3CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC3CFGR1_DT0EN_Msk          (0x1UL << CSI_VC3CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC3CFGR1_DT0EN              CSI_VC3CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC3CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC3CFGR1_DT1EN_Msk          (0x1UL << CSI_VC3CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC3CFGR1_DT1EN              CSI_VC3CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC3CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC3CFGR1_DT2EN_Msk          (0x1UL << CSI_VC3CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC3CFGR1_DT2EN              CSI_VC3CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC3CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC3CFGR1_DT3EN_Msk          (0x1UL << CSI_VC3CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC3CFGR1_DT3EN              CSI_VC3CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC3CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC3CFGR1_DT4EN_Msk          (0x1UL << CSI_VC3CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC3CFGR1_DT4EN              CSI_VC3CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC3CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC3CFGR1_DT5EN_Msk          (0x1UL << CSI_VC3CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC3CFGR1_DT5EN              CSI_VC3CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC3CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC3CFGR1_DT6EN_Msk          (0x1UL << CSI_VC3CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC3CFGR1_DT6EN              CSI_VC3CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC3CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC3CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR1_CDTFT              CSI_VC3CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC3CFGR1_DT0_Pos            (16U)
+#define CSI_VC3CFGR1_DT0_Msk            (0x3FUL << CSI_VC3CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR1_DT0                CSI_VC3CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC3CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC3CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR1_DT0FT              CSI_VC3CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC3CFGR2 register  *****************/
+#define CSI_VC3CFGR2_DT1_Pos            (0U)
+#define CSI_VC3CFGR2_DT1_Msk            (0x3FUL << CSI_VC3CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR2_DT1                CSI_VC3CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC3CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR2_DT1FT              CSI_VC3CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC3CFGR2_DT2_Pos            (16U)
+#define CSI_VC3CFGR2_DT2_Msk            (0x3FUL << CSI_VC3CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR2_DT2                CSI_VC3CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC3CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR2_DT2FT              CSI_VC3CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC3CFGR3 register  *****************/
+#define CSI_VC3CFGR3_DT3_Pos            (0U)
+#define CSI_VC3CFGR3_DT3_Msk            (0x3FUL << CSI_VC3CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR3_DT3                CSI_VC3CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC3CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR3_DT3FT              CSI_VC3CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC3CFGR3_DT4_Pos            (16U)
+#define CSI_VC3CFGR3_DT4_Msk            (0x3FUL << CSI_VC3CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR3_DT4                CSI_VC3CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC3CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR3_DT4FT              CSI_VC3CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC3CFGR4 register  *****************/
+#define CSI_VC3CFGR4_DT5_Pos            (0U)
+#define CSI_VC3CFGR4_DT5_Msk            (0x3FUL << CSI_VC3CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR4_DT5                CSI_VC3CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC3CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR4_DT5FT              CSI_VC3CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC3CFGR4_DT6_Pos            (16U)
+#define CSI_VC3CFGR4_DT6_Msk            (0x3FUL << CSI_VC3CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR4_DT6                CSI_VC3CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC3CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR4_DT6FT              CSI_VC3CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_LB0CFGR register  ******************/
+#define CSI_LB0CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB0CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB0CFGR_BYTECNT             CSI_LB0CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB0CFGR_LINECNT_Pos         (16U)
+#define CSI_LB0CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB0CFGR_LINECNT             CSI_LB0CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB1CFGR register  ******************/
+#define CSI_LB1CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB1CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB1CFGR_BYTECNT             CSI_LB1CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB1CFGR_LINECNT_Pos         (16U)
+#define CSI_LB1CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB1CFGR_LINECNT             CSI_LB1CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB2CFGR register  ******************/
+#define CSI_LB2CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB2CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB2CFGR_BYTECNT             CSI_LB2CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB2CFGR_LINECNT_Pos         (16U)
+#define CSI_LB2CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB2CFGR_LINECNT             CSI_LB2CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB3CFGR register  ******************/
+#define CSI_LB3CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB3CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB3CFGR_BYTECNT             CSI_LB3CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB3CFGR_LINECNT_Pos         (16U)
+#define CSI_LB3CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB3CFGR_LINECNT             CSI_LB3CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_TIM0CFGR register  *****************/
+#define CSI_TIM0CFGR_COUNT_Pos          (0U)
+#define CSI_TIM0CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM0CFGR_COUNT              CSI_TIM0CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM1CFGR register  *****************/
+#define CSI_TIM1CFGR_COUNT_Pos          (0U)
+#define CSI_TIM1CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM1CFGR_COUNT              CSI_TIM1CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM2CFGR register  *****************/
+#define CSI_TIM2CFGR_COUNT_Pos          (0U)
+#define CSI_TIM2CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM2CFGR_COUNT              CSI_TIM2CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM3CFGR register  *****************/
+#define CSI_TIM3CFGR_COUNT_Pos          (0U)
+#define CSI_TIM3CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM3CFGR_COUNT              CSI_TIM3CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/******************  Bit definition for CSI_LMCFGR register  ******************/
+#define CSI_LMCFGR_LANENB_Pos           (8U)
+#define CSI_LMCFGR_LANENB_Msk           (0x7UL << CSI_LMCFGR_LANENB_Pos)          /*!< 0x00000700 */
+#define CSI_LMCFGR_LANENB               CSI_LMCFGR_LANENB_Msk                    /*!< Number of lanes */
+#define CSI_LMCFGR_DL0MAP_Pos           (16U)
+#define CSI_LMCFGR_DL0MAP_Msk           (0x7UL << CSI_LMCFGR_DL0MAP_Pos)          /*!< 0x00070000 */
+#define CSI_LMCFGR_DL0MAP               CSI_LMCFGR_DL0MAP_Msk                    /*!< Physical mapping of logical data lane 0 */
+#define CSI_LMCFGR_DL1MAP_Pos           (20U)
+#define CSI_LMCFGR_DL1MAP_Msk           (0x7UL << CSI_LMCFGR_DL1MAP_Pos)          /*!< 0x00700000 */
+#define CSI_LMCFGR_DL1MAP               CSI_LMCFGR_DL1MAP_Msk                    /*!< Physical mapping of logical data lane 1 */
+
+/******************  Bit definition for CSI_PRGITR register  ******************/
+#define CSI_PRGITR_LB0VC_Pos            (0U)
+#define CSI_PRGITR_LB0VC_Msk            (0x3UL << CSI_PRGITR_LB0VC_Pos)           /*!< 0x00000003 */
+#define CSI_PRGITR_LB0VC                CSI_PRGITR_LB0VC_Msk                     /*!< Line/Byte counter 0 linked to a virtual channel */
+#define CSI_PRGITR_LB0EN_Pos            (3U)
+#define CSI_PRGITR_LB0EN_Msk            (0x1UL << CSI_PRGITR_LB0EN_Pos)           /*!< 0x00000008 */
+#define CSI_PRGITR_LB0EN                CSI_PRGITR_LB0EN_Msk                     /*!< Line/Byte 0counter enable */
+#define CSI_PRGITR_LB1VC_Pos            (4U)
+#define CSI_PRGITR_LB1VC_Msk            (0x3UL << CSI_PRGITR_LB1VC_Pos)           /*!< 0x00000030 */
+#define CSI_PRGITR_LB1VC                CSI_PRGITR_LB1VC_Msk                     /*!< Line/Byte counter 1 linked to a virtual channel */
+#define CSI_PRGITR_LB1EN_Pos            (7U)
+#define CSI_PRGITR_LB1EN_Msk            (0x1UL << CSI_PRGITR_LB1EN_Pos)           /*!< 0x00000080 */
+#define CSI_PRGITR_LB1EN                CSI_PRGITR_LB1EN_Msk                     /*!< Line/Byte 1 counter enable */
+#define CSI_PRGITR_LB2VC_Pos            (8U)
+#define CSI_PRGITR_LB2VC_Msk            (0x3UL << CSI_PRGITR_LB2VC_Pos)           /*!< 0x00000300 */
+#define CSI_PRGITR_LB2VC                CSI_PRGITR_LB2VC_Msk                     /*!< Line/Byte counter 2 linked to a virtual channel */
+#define CSI_PRGITR_LB2EN_Pos            (11U)
+#define CSI_PRGITR_LB2EN_Msk            (0x1UL << CSI_PRGITR_LB2EN_Pos)           /*!< 0x00000800 */
+#define CSI_PRGITR_LB2EN                CSI_PRGITR_LB2EN_Msk                     /*!< Line/Byte 2 counter enable */
+#define CSI_PRGITR_LB3VC_Pos            (12U)
+#define CSI_PRGITR_LB3VC_Msk            (0x3UL << CSI_PRGITR_LB3VC_Pos)           /*!< 0x00003000 */
+#define CSI_PRGITR_LB3VC                CSI_PRGITR_LB3VC_Msk                     /*!< Line/Byte counter 3 linked to a virtual channel */
+#define CSI_PRGITR_LB3EN_Pos            (15U)
+#define CSI_PRGITR_LB3EN_Msk            (0x1UL << CSI_PRGITR_LB3EN_Pos)           /*!< 0x00008000 */
+#define CSI_PRGITR_LB3EN                CSI_PRGITR_LB3EN_Msk                     /*!< Line/Byte 3 counter enable */
+#define CSI_PRGITR_TIM0VC_Pos           (16U)
+#define CSI_PRGITR_TIM0VC_Msk           (0x3UL << CSI_PRGITR_TIM0VC_Pos)          /*!< 0x00030000 */
+#define CSI_PRGITR_TIM0VC               CSI_PRGITR_TIM0VC_Msk                    /*!< TIM0 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM0EOF_Pos          (18U)
+#define CSI_PRGITR_TIM0EOF_Msk          (0x1UL << CSI_PRGITR_TIM0EOF_Pos)         /*!< 0x00040000 */
+#define CSI_PRGITR_TIM0EOF              CSI_PRGITR_TIM0EOF_Msk                   /*!< TIM0 base time starting from the end of frame */
+#define CSI_PRGITR_TIM0EN_Pos           (19U)
+#define CSI_PRGITR_TIM0EN_Msk           (0x1UL << CSI_PRGITR_TIM0EN_Pos)          /*!< 0x00080000 */
+#define CSI_PRGITR_TIM0EN               CSI_PRGITR_TIM0EN_Msk                    /*!< TIM0 base time enable */
+#define CSI_PRGITR_TIM1VC_Pos           (20U)
+#define CSI_PRGITR_TIM1VC_Msk           (0x3UL << CSI_PRGITR_TIM1VC_Pos)          /*!< 0x00300000 */
+#define CSI_PRGITR_TIM1VC               CSI_PRGITR_TIM1VC_Msk                    /*!< TIM1 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM1EOF_Pos          (22U)
+#define CSI_PRGITR_TIM1EOF_Msk          (0x1UL << CSI_PRGITR_TIM1EOF_Pos)         /*!< 0x00400000 */
+#define CSI_PRGITR_TIM1EOF              CSI_PRGITR_TIM1EOF_Msk                   /*!< TIM1 base time starting from the end of frame */
+#define CSI_PRGITR_TIM1EN_Pos           (23U)
+#define CSI_PRGITR_TIM1EN_Msk           (0x1UL << CSI_PRGITR_TIM1EN_Pos)          /*!< 0x00800000 */
+#define CSI_PRGITR_TIM1EN               CSI_PRGITR_TIM1EN_Msk                    /*!< TIM1 base time enable */
+#define CSI_PRGITR_TIM2VC_Pos           (24U)
+#define CSI_PRGITR_TIM2VC_Msk           (0x3UL << CSI_PRGITR_TIM2VC_Pos)          /*!< 0x03000000 */
+#define CSI_PRGITR_TIM2VC               CSI_PRGITR_TIM2VC_Msk                    /*!< TIM2 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM2EOF_Pos          (26U)
+#define CSI_PRGITR_TIM2EOF_Msk          (0x1UL << CSI_PRGITR_TIM2EOF_Pos)         /*!< 0x04000000 */
+#define CSI_PRGITR_TIM2EOF              CSI_PRGITR_TIM2EOF_Msk                   /*!< TIM2 base time starting from the end of frame */
+#define CSI_PRGITR_TIM2EN_Pos           (27U)
+#define CSI_PRGITR_TIM2EN_Msk           (0x1UL << CSI_PRGITR_TIM2EN_Pos)          /*!< 0x08000000 */
+#define CSI_PRGITR_TIM2EN               CSI_PRGITR_TIM2EN_Msk                    /*!< TIM2 base time enable */
+#define CSI_PRGITR_TIM3VC_Pos           (28U)
+#define CSI_PRGITR_TIM3VC_Msk           (0x3UL << CSI_PRGITR_TIM3VC_Pos)          /*!< 0x30000000 */
+#define CSI_PRGITR_TIM3VC               CSI_PRGITR_TIM3VC_Msk                    /*!< TIM3 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM3EOF_Pos          (30U)
+#define CSI_PRGITR_TIM3EOF_Msk          (0x1UL << CSI_PRGITR_TIM3EOF_Pos)         /*!< 0x40000000 */
+#define CSI_PRGITR_TIM3EOF              CSI_PRGITR_TIM3EOF_Msk                   /*!< TIM3 base time starting from the end of frame */
+#define CSI_PRGITR_TIM3EN_Pos           (31U)
+#define CSI_PRGITR_TIM3EN_Msk           (0x1UL << CSI_PRGITR_TIM3EN_Pos)          /*!< 0x80000000 */
+#define CSI_PRGITR_TIM3EN               CSI_PRGITR_TIM3EN_Msk                    /*!< TIM3 base time enable */
+
+/*******************  Bit definition for CSI_WDR register  ********************/
+#define CSI_WDR_CNT_Pos                 (0U)
+#define CSI_WDR_CNT_Msk                 (0xFFFFFFFFUL << CSI_WDR_CNT_Pos)         /*!< 0xFFFFFFFF */
+#define CSI_WDR_CNT                     CSI_WDR_CNT_Msk                          /*!< Watchdog counter */
+
+/*******************  Bit definition for CSI_IER0 register  *******************/
+#define CSI_IER0_LB0IE_Pos              (0U)
+#define CSI_IER0_LB0IE_Msk              (0x1UL << CSI_IER0_LB0IE_Pos)             /*!< 0x00000001 */
+#define CSI_IER0_LB0IE                  CSI_IER0_LB0IE_Msk                       /*!< Line byte counter 0 interrupt enable */
+#define CSI_IER0_LB1IE_Pos              (1U)
+#define CSI_IER0_LB1IE_Msk              (0x1UL << CSI_IER0_LB1IE_Pos)             /*!< 0x00000002 */
+#define CSI_IER0_LB1IE                  CSI_IER0_LB1IE_Msk                       /*!< Line byte counter 1 interrupt enable */
+#define CSI_IER0_LB2IE_Pos              (2U)
+#define CSI_IER0_LB2IE_Msk              (0x1UL << CSI_IER0_LB2IE_Pos)             /*!< 0x00000004 */
+#define CSI_IER0_LB2IE                  CSI_IER0_LB2IE_Msk                       /*!< Line byte counter 2 interrupt enable */
+#define CSI_IER0_LB3IE_Pos              (3U)
+#define CSI_IER0_LB3IE_Msk              (0x1UL << CSI_IER0_LB3IE_Pos)             /*!< 0x00000008 */
+#define CSI_IER0_LB3IE                  CSI_IER0_LB3IE_Msk                       /*!< Line byte counter 3 interrupt enable */
+#define CSI_IER0_TIM0IE_Pos             (4U)
+#define CSI_IER0_TIM0IE_Msk             (0x1UL << CSI_IER0_TIM0IE_Pos)            /*!< 0x00000010 */
+#define CSI_IER0_TIM0IE                 CSI_IER0_TIM0IE_Msk                      /*!< Timer 0 interrupt enable */
+#define CSI_IER0_TIM1IE_Pos             (5U)
+#define CSI_IER0_TIM1IE_Msk             (0x1UL << CSI_IER0_TIM1IE_Pos)            /*!< 0x00000020 */
+#define CSI_IER0_TIM1IE                 CSI_IER0_TIM1IE_Msk                      /*!< Timer 1 interrupt enable */
+#define CSI_IER0_TIM2IE_Pos             (6U)
+#define CSI_IER0_TIM2IE_Msk             (0x1UL << CSI_IER0_TIM2IE_Pos)            /*!< 0x00000040 */
+#define CSI_IER0_TIM2IE                 CSI_IER0_TIM2IE_Msk                      /*!< Timer 2 interrupt enable */
+#define CSI_IER0_TIM3IE_Pos             (7U)
+#define CSI_IER0_TIM3IE_Msk             (0x1UL << CSI_IER0_TIM3IE_Pos)            /*!< 0x00000080 */
+#define CSI_IER0_TIM3IE                 CSI_IER0_TIM3IE_Msk                      /*!< Timer 3 interrupt enable */
+#define CSI_IER0_SOF0IE_Pos             (8U)
+#define CSI_IER0_SOF0IE_Msk             (0x1UL << CSI_IER0_SOF0IE_Pos)            /*!< 0x00000100 */
+#define CSI_IER0_SOF0IE                 CSI_IER0_SOF0IE_Msk                      /*!< Start of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_SOF1IE_Pos             (9U)
+#define CSI_IER0_SOF1IE_Msk             (0x1UL << CSI_IER0_SOF1IE_Pos)            /*!< 0x00000200 */
+#define CSI_IER0_SOF1IE                 CSI_IER0_SOF1IE_Msk                      /*!< Start of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_SOF2IE_Pos             (10U)
+#define CSI_IER0_SOF2IE_Msk             (0x1UL << CSI_IER0_SOF2IE_Pos)            /*!< 0x00000400 */
+#define CSI_IER0_SOF2IE                 CSI_IER0_SOF2IE_Msk                      /*!< Start of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_SOF3IE_Pos             (11U)
+#define CSI_IER0_SOF3IE_Msk             (0x1UL << CSI_IER0_SOF3IE_Pos)            /*!< 0x00000800 */
+#define CSI_IER0_SOF3IE                 CSI_IER0_SOF3IE_Msk                      /*!< Start of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_EOF0IE_Pos             (12U)
+#define CSI_IER0_EOF0IE_Msk             (0x1UL << CSI_IER0_EOF0IE_Pos)            /*!< 0x00001000 */
+#define CSI_IER0_EOF0IE                 CSI_IER0_EOF0IE_Msk                      /*!< End of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_EOF1IE_Pos             (13U)
+#define CSI_IER0_EOF1IE_Msk             (0x1UL << CSI_IER0_EOF1IE_Pos)            /*!< 0x00002000 */
+#define CSI_IER0_EOF1IE                 CSI_IER0_EOF1IE_Msk                      /*!< End of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_EOF2IE_Pos             (14U)
+#define CSI_IER0_EOF2IE_Msk             (0x1UL << CSI_IER0_EOF2IE_Pos)            /*!< 0x00004000 */
+#define CSI_IER0_EOF2IE                 CSI_IER0_EOF2IE_Msk                      /*!< End of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_EOF3IE_Pos             (15U)
+#define CSI_IER0_EOF3IE_Msk             (0x1UL << CSI_IER0_EOF3IE_Pos)            /*!< 0x00008000 */
+#define CSI_IER0_EOF3IE                 CSI_IER0_EOF3IE_Msk                      /*!< End of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_SPKTIE_Pos             (16U)
+#define CSI_IER0_SPKTIE_Msk             (0x1UL << CSI_IER0_SPKTIE_Pos)            /*!< 0x00010000 */
+#define CSI_IER0_SPKTIE                 CSI_IER0_SPKTIE_Msk                      /*!< Short packet interrupt enable */
+#define CSI_IER0_CCFIFOFIE_Pos          (21U)
+#define CSI_IER0_CCFIFOFIE_Msk          (0x1UL << CSI_IER0_CCFIFOFIE_Pos)         /*!< 0x00200000 */
+#define CSI_IER0_CCFIFOFIE              CSI_IER0_CCFIFOFIE_Msk                   /*!< Clock changer FIFO full interrupt enable */
+#define CSI_IER0_CRCERRIE_Pos           (24U)
+#define CSI_IER0_CRCERRIE_Msk           (0x1UL << CSI_IER0_CRCERRIE_Pos)          /*!< 0x01000000 */
+#define CSI_IER0_CRCERRIE               CSI_IER0_CRCERRIE_Msk                    /*!< CRC error interrupt enable */
+#define CSI_IER0_ECCERRIE_Pos           (25U)
+#define CSI_IER0_ECCERRIE_Msk           (0x1UL << CSI_IER0_ECCERRIE_Pos)          /*!< 0x02000000 */
+#define CSI_IER0_ECCERRIE               CSI_IER0_ECCERRIE_Msk                    /*!< ECC error interrupt enable */
+#define CSI_IER0_CECCERRIE_Pos          (26U)
+#define CSI_IER0_CECCERRIE_Msk          (0x1UL << CSI_IER0_CECCERRIE_Pos)         /*!< 0x04000000 */
+#define CSI_IER0_CECCERRIE              CSI_IER0_CECCERRIE_Msk                   /*!< Corrected ECC error interrupt enable */
+#define CSI_IER0_IDERRIE_Pos            (27U)
+#define CSI_IER0_IDERRIE_Msk            (0x1UL << CSI_IER0_IDERRIE_Pos)           /*!< 0x08000000 */
+#define CSI_IER0_IDERRIE                CSI_IER0_IDERRIE_Msk                     /*!< Data type ID error interrupt enable */
+#define CSI_IER0_SPKTERRIE_Pos          (28U)
+#define CSI_IER0_SPKTERRIE_Msk          (0x1UL << CSI_IER0_SPKTERRIE_Pos)         /*!< 0x10000000 */
+#define CSI_IER0_SPKTERRIE              CSI_IER0_SPKTERRIE_Msk                   /*!< Short packet error interrupt enable */
+#define CSI_IER0_WDERRIE_Pos            (29U)
+#define CSI_IER0_WDERRIE_Msk            (0x1UL << CSI_IER0_WDERRIE_Pos)           /*!< 0x20000000 */
+#define CSI_IER0_WDERRIE                CSI_IER0_WDERRIE_Msk                     /*!< Watchdog error interrupt enable */
+#define CSI_IER0_SYNCERRIE_Pos          (30U)
+#define CSI_IER0_SYNCERRIE_Msk          (0x1UL << CSI_IER0_SYNCERRIE_Pos)         /*!< 0x40000000 */
+#define CSI_IER0_SYNCERRIE              CSI_IER0_SYNCERRIE_Msk                   /*!< Invalid synchronization error interrupt enable */
+
+/*******************  Bit definition for CSI_IER1 register  *******************/
+#define CSI_IER1_ESOTDL0IE_Pos          (0U)
+#define CSI_IER1_ESOTDL0IE_Msk          (0x1UL << CSI_IER1_ESOTDL0IE_Pos)         /*!< 0x00000001 */
+#define CSI_IER1_ESOTDL0IE              CSI_IER1_ESOTDL0IE_Msk                   /*!< Start of transmission error interrupt enable on lane 0 */
+#define CSI_IER1_ESOTSYNCDL0IE_Pos      (1U)
+#define CSI_IER1_ESOTSYNCDL0IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos)     /*!< 0x00000002 */
+#define CSI_IER1_ESOTSYNCDL0IE          CSI_IER1_ESOTSYNCDL0IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 0 */
+#define CSI_IER1_EESCDL0IE_Pos          (2U)
+#define CSI_IER1_EESCDL0IE_Msk          (0x1UL << CSI_IER1_EESCDL0IE_Pos)         /*!< 0x00000004 */
+#define CSI_IER1_EESCDL0IE              CSI_IER1_EESCDL0IE_Msk                   /*!< D-PHY_RX lane 0 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL0IE_Pos      (3U)
+#define CSI_IER1_ESYNCESCDL0IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos)     /*!< 0x00000008 */
+#define CSI_IER1_ESYNCESCDL0IE          CSI_IER1_ESYNCESCDL0IE_Msk               /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL0IE_Pos         (4U)
+#define CSI_IER1_ECTRLDL0IE_Msk         (0x1UL << CSI_IER1_ECTRLDL0IE_Pos)        /*!< 0x00000010 */
+#define CSI_IER1_ECTRLDL0IE             CSI_IER1_ECTRLDL0IE_Msk                  /*!< D-PHY_RX lane 0 control error interrupt enable */
+#define CSI_IER1_ESOTDL1IE_Pos          (8U)
+#define CSI_IER1_ESOTDL1IE_Msk          (0x1UL << CSI_IER1_ESOTDL1IE_Pos)         /*!< 0x00000100 */
+#define CSI_IER1_ESOTDL1IE              CSI_IER1_ESOTDL1IE_Msk                   /*!< Start of transmission error interrupt enable on lane 1 */
+#define CSI_IER1_ESOTSYNCDL1IE_Pos      (9U)
+#define CSI_IER1_ESOTSYNCDL1IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos)     /*!< 0x00000200 */
+#define CSI_IER1_ESOTSYNCDL1IE          CSI_IER1_ESOTSYNCDL1IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 1 */
+#define CSI_IER1_EESCDL1IE_Pos          (10U)
+#define CSI_IER1_EESCDL1IE_Msk          (0x1UL << CSI_IER1_EESCDL1IE_Pos)         /*!< 0x00000400 */
+#define CSI_IER1_EESCDL1IE              CSI_IER1_EESCDL1IE_Msk                   /*!< D-PHY_RX lane 1 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL1IE_Pos      (11U)
+#define CSI_IER1_ESYNCESCDL1IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos)     /*!< 0x00000800 */
+#define CSI_IER1_ESYNCESCDL1IE          CSI_IER1_ESYNCESCDL1IE_Msk               /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL1IE_Pos         (12U)
+#define CSI_IER1_ECTRLDL1IE_Msk         (0x1UL << CSI_IER1_ECTRLDL1IE_Pos)        /*!< 0x00001000 */
+#define CSI_IER1_ECTRLDL1IE             CSI_IER1_ECTRLDL1IE_Msk                  /*!< D-PHY_RX lane 1 control error interrupt enable */
+
+/*******************  Bit definition for CSI_SR0 register  ********************/
+#define CSI_SR0_LB0F_Pos                (0U)
+#define CSI_SR0_LB0F_Msk                (0x1UL << CSI_SR0_LB0F_Pos)               /*!< 0x00000001 */
+#define CSI_SR0_LB0F                    CSI_SR0_LB0F_Msk                         /*!< Line byte counter 0 flag */
+#define CSI_SR0_LB1F_Pos                (1U)
+#define CSI_SR0_LB1F_Msk                (0x1UL << CSI_SR0_LB1F_Pos)               /*!< 0x00000002 */
+#define CSI_SR0_LB1F                    CSI_SR0_LB1F_Msk                         /*!< Line byte counter 1 flag */
+#define CSI_SR0_LB2F_Pos                (2U)
+#define CSI_SR0_LB2F_Msk                (0x1UL << CSI_SR0_LB2F_Pos)               /*!< 0x00000004 */
+#define CSI_SR0_LB2F                    CSI_SR0_LB2F_Msk                         /*!< Line byte counter 2 flag */
+#define CSI_SR0_LB3F_Pos                (3U)
+#define CSI_SR0_LB3F_Msk                (0x1UL << CSI_SR0_LB3F_Pos)               /*!< 0x00000008 */
+#define CSI_SR0_LB3F                    CSI_SR0_LB3F_Msk                         /*!< Line byte counter 3 flag */
+#define CSI_SR0_TIM0F_Pos               (4U)
+#define CSI_SR0_TIM0F_Msk               (0x1UL << CSI_SR0_TIM0F_Pos)              /*!< 0x00000010 */
+#define CSI_SR0_TIM0F                   CSI_SR0_TIM0F_Msk                        /*!< Timer 0 flag */
+#define CSI_SR0_TIM1F_Pos               (5U)
+#define CSI_SR0_TIM1F_Msk               (0x1UL << CSI_SR0_TIM1F_Pos)              /*!< 0x00000020 */
+#define CSI_SR0_TIM1F                   CSI_SR0_TIM1F_Msk                        /*!< Timer 1 flag */
+#define CSI_SR0_TIM2F_Pos               (6U)
+#define CSI_SR0_TIM2F_Msk               (0x1UL << CSI_SR0_TIM2F_Pos)              /*!< 0x00000040 */
+#define CSI_SR0_TIM2F                   CSI_SR0_TIM2F_Msk                        /*!< Timer 2 flag */
+#define CSI_SR0_TIM3F_Pos               (7U)
+#define CSI_SR0_TIM3F_Msk               (0x1UL << CSI_SR0_TIM3F_Pos)              /*!< 0x00000080 */
+#define CSI_SR0_TIM3F                   CSI_SR0_TIM3F_Msk                        /*!< Timer 3 flag */
+#define CSI_SR0_SOF0F_Pos               (8U)
+#define CSI_SR0_SOF0F_Msk               (0x1UL << CSI_SR0_SOF0F_Pos)              /*!< 0x00000100 */
+#define CSI_SR0_SOF0F                   CSI_SR0_SOF0F_Msk                        /*!< Start of frame flag for virtual channel 0 */
+#define CSI_SR0_SOF1F_Pos               (9U)
+#define CSI_SR0_SOF1F_Msk               (0x1UL << CSI_SR0_SOF1F_Pos)              /*!< 0x00000200 */
+#define CSI_SR0_SOF1F                   CSI_SR0_SOF1F_Msk                        /*!< Start of frame flag for virtual channel 1 */
+#define CSI_SR0_SOF2F_Pos               (10U)
+#define CSI_SR0_SOF2F_Msk               (0x1UL << CSI_SR0_SOF2F_Pos)              /*!< 0x00000400 */
+#define CSI_SR0_SOF2F                   CSI_SR0_SOF2F_Msk                        /*!< Start of frame flag for virtual channel 2 */
+#define CSI_SR0_SOF3F_Pos               (11U)
+#define CSI_SR0_SOF3F_Msk               (0x1UL << CSI_SR0_SOF3F_Pos)              /*!< 0x00000800 */
+#define CSI_SR0_SOF3F                   CSI_SR0_SOF3F_Msk                        /*!< Start of frame flag for virtual channel 3 */
+#define CSI_SR0_EOF0F_Pos               (12U)
+#define CSI_SR0_EOF0F_Msk               (0x1UL << CSI_SR0_EOF0F_Pos)              /*!< 0x00001000 */
+#define CSI_SR0_EOF0F                   CSI_SR0_EOF0F_Msk                        /*!< End of frame flag for virtual channel 0 */
+#define CSI_SR0_EOF1F_Pos               (13U)
+#define CSI_SR0_EOF1F_Msk               (0x1UL << CSI_SR0_EOF1F_Pos)              /*!< 0x00002000 */
+#define CSI_SR0_EOF1F                   CSI_SR0_EOF1F_Msk                        /*!< End of frame flag for virtual channel 1 */
+#define CSI_SR0_EOF2F_Pos               (14U)
+#define CSI_SR0_EOF2F_Msk               (0x1UL << CSI_SR0_EOF2F_Pos)              /*!< 0x00004000 */
+#define CSI_SR0_EOF2F                   CSI_SR0_EOF2F_Msk                        /*!< End of frame flag for virtual channel 2 */
+#define CSI_SR0_EOF3F_Pos               (15U)
+#define CSI_SR0_EOF3F_Msk               (0x1UL << CSI_SR0_EOF3F_Pos)              /*!< 0x00008000 */
+#define CSI_SR0_EOF3F                   CSI_SR0_EOF3F_Msk                        /*!< End of frame flag for virtual channel 3 */
+#define CSI_SR0_SPKTF_Pos               (16U)
+#define CSI_SR0_SPKTF_Msk               (0x1UL << CSI_SR0_SPKTF_Pos)              /*!< 0x00010000 */
+#define CSI_SR0_SPKTF                   CSI_SR0_SPKTF_Msk                        /*!< Short packet flag */
+#define CSI_SR0_VC0STATEF_Pos           (17U)
+#define CSI_SR0_VC0STATEF_Msk           (0x1UL << CSI_SR0_VC0STATEF_Pos)          /*!< 0x00020000 */
+#define CSI_SR0_VC0STATEF               CSI_SR0_VC0STATEF_Msk                    /*!< Virtual channel 0 state flag */
+#define CSI_SR0_VC1STATEF_Pos           (18U)
+#define CSI_SR0_VC1STATEF_Msk           (0x1UL << CSI_SR0_VC1STATEF_Pos)          /*!< 0x00040000 */
+#define CSI_SR0_VC1STATEF               CSI_SR0_VC1STATEF_Msk                    /*!< Virtual channel 1 state flag */
+#define CSI_SR0_VC2STATEF_Pos           (19U)
+#define CSI_SR0_VC2STATEF_Msk           (0x1UL << CSI_SR0_VC2STATEF_Pos)          /*!< 0x00080000 */
+#define CSI_SR0_VC2STATEF               CSI_SR0_VC2STATEF_Msk                    /*!< Virtual channel 2 state flag */
+#define CSI_SR0_VC3STATEF_Pos           (20U)
+#define CSI_SR0_VC3STATEF_Msk           (0x1UL << CSI_SR0_VC3STATEF_Pos)          /*!< 0x00100000 */
+#define CSI_SR0_VC3STATEF               CSI_SR0_VC3STATEF_Msk                    /*!< Virtual channel 3 state flag */
+#define CSI_SR0_CCFIFOFF_Pos            (21U)
+#define CSI_SR0_CCFIFOFF_Msk            (0x1UL << CSI_SR0_CCFIFOFF_Pos)           /*!< 0x00200000 */
+#define CSI_SR0_CCFIFOFF                CSI_SR0_CCFIFOFF_Msk                     /*!< Clock changer FIFO full flag */
+#define CSI_SR0_CRCERRF_Pos             (24U)
+#define CSI_SR0_CRCERRF_Msk             (0x1UL << CSI_SR0_CRCERRF_Pos)            /*!< 0x01000000 */
+#define CSI_SR0_CRCERRF                 CSI_SR0_CRCERRF_Msk                      /*!< CRC error flag */
+#define CSI_SR0_ECCERRF_Pos             (25U)
+#define CSI_SR0_ECCERRF_Msk             (0x1UL << CSI_SR0_ECCERRF_Pos)            /*!< 0x02000000 */
+#define CSI_SR0_ECCERRF                 CSI_SR0_ECCERRF_Msk                      /*!< ECC error flag */
+#define CSI_SR0_CECCERRF_Pos            (26U)
+#define CSI_SR0_CECCERRF_Msk            (0x1UL << CSI_SR0_CECCERRF_Pos)           /*!< 0x04000000 */
+#define CSI_SR0_CECCERRF                CSI_SR0_CECCERRF_Msk                     /*!< Corrected ECC error flag */
+#define CSI_SR0_IDERRF_Pos              (27U)
+#define CSI_SR0_IDERRF_Msk              (0x1UL << CSI_SR0_IDERRF_Pos)             /*!< 0x08000000 */
+#define CSI_SR0_IDERRF                  CSI_SR0_IDERRF_Msk                       /*!< Data type ID error flag */
+#define CSI_SR0_SPKTERRF_Pos            (28U)
+#define CSI_SR0_SPKTERRF_Msk            (0x1UL << CSI_SR0_SPKTERRF_Pos)           /*!< 0x10000000 */
+#define CSI_SR0_SPKTERRF                CSI_SR0_SPKTERRF_Msk                     /*!< Short packet error flag */
+#define CSI_SR0_WDERRF_Pos              (29U)
+#define CSI_SR0_WDERRF_Msk              (0x1UL << CSI_SR0_WDERRF_Pos)             /*!< 0x20000000 */
+#define CSI_SR0_WDERRF                  CSI_SR0_WDERRF_Msk                       /*!< Watchdog error flag */
+#define CSI_SR0_SYNCERRF_Pos            (30U)
+#define CSI_SR0_SYNCERRF_Msk            (0x1UL << CSI_SR0_SYNCERRF_Pos)           /*!< 0x40000000 */
+#define CSI_SR0_SYNCERRF                CSI_SR0_SYNCERRF_Msk                     /*!< Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_SR1 register  ********************/
+#define CSI_SR1_ESOTDL0F_Pos            (0U)
+#define CSI_SR1_ESOTDL0F_Msk            (0x1UL << CSI_SR1_ESOTDL0F_Pos)           /*!< 0x00000001 */
+#define CSI_SR1_ESOTDL0F                CSI_SR1_ESOTDL0F_Msk                     /*!< Start of transmission error flag on lane 0 */
+#define CSI_SR1_ESOTSYNCDL0F_Pos        (1U)
+#define CSI_SR1_ESOTSYNCDL0F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos)       /*!< 0x00000002 */
+#define CSI_SR1_ESOTSYNCDL0F            CSI_SR1_ESOTSYNCDL0F_Msk                 /*!< Start of transmission synchronization error flag on lane 0 */
+#define CSI_SR1_EESCDL0F_Pos            (2U)
+#define CSI_SR1_EESCDL0F_Msk            (0x1UL << CSI_SR1_EESCDL0F_Pos)           /*!< 0x00000004 */
+#define CSI_SR1_EESCDL0F                CSI_SR1_EESCDL0F_Msk                     /*!< D-PHY_RX lane 0 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL0F_Pos        (3U)
+#define CSI_SR1_ESYNCESCDL0F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos)       /*!< 0x00000008 */
+#define CSI_SR1_ESYNCESCDL0F            CSI_SR1_ESYNCESCDL0F_Msk                 /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL0F_Pos           (4U)
+#define CSI_SR1_ECTRLDL0F_Msk           (0x1UL << CSI_SR1_ECTRLDL0F_Pos)          /*!< 0x00000010 */
+#define CSI_SR1_ECTRLDL0F               CSI_SR1_ECTRLDL0F_Msk                    /*!< D-PHY_RX lane 0 control error flag */
+#define CSI_SR1_ESOTDL1F_Pos            (8U)
+#define CSI_SR1_ESOTDL1F_Msk            (0x1UL << CSI_SR1_ESOTDL1F_Pos)           /*!< 0x00000100 */
+#define CSI_SR1_ESOTDL1F                CSI_SR1_ESOTDL1F_Msk                     /*!< Start of transmission error flag on lane 1 */
+#define CSI_SR1_ESOTSYNCDL1F_Pos        (9U)
+#define CSI_SR1_ESOTSYNCDL1F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos)       /*!< 0x00000200 */
+#define CSI_SR1_ESOTSYNCDL1F            CSI_SR1_ESOTSYNCDL1F_Msk                 /*!< Start of transmission synchronization error flag on lane 1 */
+#define CSI_SR1_EESCDL1F_Pos            (10U)
+#define CSI_SR1_EESCDL1F_Msk            (0x1UL << CSI_SR1_EESCDL1F_Pos)           /*!< 0x00000400 */
+#define CSI_SR1_EESCDL1F                CSI_SR1_EESCDL1F_Msk                     /*!< D-PHY_RX lane 1 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL1F_Pos        (11U)
+#define CSI_SR1_ESYNCESCDL1F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos)       /*!< 0x00000800 */
+#define CSI_SR1_ESYNCESCDL1F            CSI_SR1_ESYNCESCDL1F_Msk                 /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL1F_Pos           (12U)
+#define CSI_SR1_ECTRLDL1F_Msk           (0x1UL << CSI_SR1_ECTRLDL1F_Pos)          /*!< 0x00001000 */
+#define CSI_SR1_ECTRLDL1F               CSI_SR1_ECTRLDL1F_Msk                    /*!< D-PHY_RX lane 1 control error flag */
+#define CSI_SR1_ACTDL0F_Pos             (16U)
+#define CSI_SR1_ACTDL0F_Msk             (0x1UL << CSI_SR1_ACTDL0F_Pos)            /*!< 0x00010000 */
+#define CSI_SR1_ACTDL0F                 CSI_SR1_ACTDL0F_Msk                      /*!< D-PHY_RX lane 0 High speed reception active */
+#define CSI_SR1_SYNCDL0F_Pos            (17U)
+#define CSI_SR1_SYNCDL0F_Msk            (0x1UL << CSI_SR1_SYNCDL0F_Pos)           /*!< 0x00020000 */
+#define CSI_SR1_SYNCDL0F                CSI_SR1_SYNCDL0F_Msk                     /*!< D-PHY_RX lane 0 receiver synchronization observed */
+#define CSI_SR1_SKCALDL0F_Pos           (18U)
+#define CSI_SR1_SKCALDL0F_Msk           (0x1UL << CSI_SR1_SKCALDL0F_Pos)          /*!< 0x00040000 */
+#define CSI_SR1_SKCALDL0F               CSI_SR1_SKCALDL0F_Msk                    /*!< D-PHY_RX lane 0 High speed skew calibration */
+#define CSI_SR1_STOPDL0F_Pos            (19U)
+#define CSI_SR1_STOPDL0F_Msk            (0x1UL << CSI_SR1_STOPDL0F_Pos)           /*!< 0x00080000 */
+#define CSI_SR1_STOPDL0F                CSI_SR1_STOPDL0F_Msk                     /*!< D-PHY_RX receiver data lane 0 in stop state */
+#define CSI_SR1_ULPNDL0F_Pos            (20U)
+#define CSI_SR1_ULPNDL0F_Msk            (0x1UL << CSI_SR1_ULPNDL0F_Pos)           /*!< 0x00100000 */
+#define CSI_SR1_ULPNDL0F                CSI_SR1_ULPNDL0F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */
+#define CSI_SR1_ACTDL1F_Pos             (22U)
+#define CSI_SR1_ACTDL1F_Msk             (0x1UL << CSI_SR1_ACTDL1F_Pos)            /*!< 0x00400000 */
+#define CSI_SR1_ACTDL1F                 CSI_SR1_ACTDL1F_Msk                      /*!< D-PHY_RX lane 1 High speed reception active */
+#define CSI_SR1_SYNCDL1F_Pos            (23U)
+#define CSI_SR1_SYNCDL1F_Msk            (0x1UL << CSI_SR1_SYNCDL1F_Pos)           /*!< 0x00800000 */
+#define CSI_SR1_SYNCDL1F                CSI_SR1_SYNCDL1F_Msk                     /*!< D-PHY_RX lane 1 receiver synchronization observed */
+#define CSI_SR1_SKCALDL1F_Pos           (24U)
+#define CSI_SR1_SKCALDL1F_Msk           (0x1UL << CSI_SR1_SKCALDL1F_Pos)          /*!< 0x01000000 */
+#define CSI_SR1_SKCALDL1F               CSI_SR1_SKCALDL1F_Msk                    /*!< D-PHY_RX lane 1 High speed skew calibration */
+#define CSI_SR1_STOPDL1F_Pos            (25U)
+#define CSI_SR1_STOPDL1F_Msk            (0x1UL << CSI_SR1_STOPDL1F_Pos)           /*!< 0x02000000 */
+#define CSI_SR1_STOPDL1F                CSI_SR1_STOPDL1F_Msk                     /*!< D-PHY_RX receiver data lane 1 in stop state */
+#define CSI_SR1_ULPNDL1F_Pos            (26U)
+#define CSI_SR1_ULPNDL1F_Msk            (0x1UL << CSI_SR1_ULPNDL1F_Pos)           /*!< 0x04000000 */
+#define CSI_SR1_ULPNDL1F                CSI_SR1_ULPNDL1F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */
+#define CSI_SR1_STOPCLF_Pos             (28U)
+#define CSI_SR1_STOPCLF_Msk             (0x1UL << CSI_SR1_STOPCLF_Pos)            /*!< 0x10000000 */
+#define CSI_SR1_STOPCLF                 CSI_SR1_STOPCLF_Msk                      /*!< D-PHY_RX receiver in stop state for the clock lane */
+#define CSI_SR1_ULPNACTF_Pos            (29U)
+#define CSI_SR1_ULPNACTF_Msk            (0x1UL << CSI_SR1_ULPNACTF_Pos)           /*!< 0x20000000 */
+#define CSI_SR1_ULPNACTF                CSI_SR1_ULPNACTF_Msk                     /*!< D-PHY_RX receiver ULP state (not) active */
+#define CSI_SR1_ULPNCLF_Pos             (30U)
+#define CSI_SR1_ULPNCLF_Msk             (0x1UL << CSI_SR1_ULPNCLF_Pos)            /*!< 0x40000000 */
+#define CSI_SR1_ULPNCLF                 CSI_SR1_ULPNCLF_Msk                      /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */
+#define CSI_SR1_ACTCLF_Pos              (31U)
+#define CSI_SR1_ACTCLF_Msk              (0x1UL << CSI_SR1_ACTCLF_Pos)             /*!< 0x80000000 */
+#define CSI_SR1_ACTCLF                  CSI_SR1_ACTCLF_Msk                       /*!< D-PHY_RX receiver clock active flag */
+
+/*******************  Bit definition for CSI_FCR0 register  *******************/
+#define CSI_FCR0_CLB0F_Pos              (0U)
+#define CSI_FCR0_CLB0F_Msk              (0x1UL << CSI_FCR0_CLB0F_Pos)             /*!< 0x00000001 */
+#define CSI_FCR0_CLB0F                  CSI_FCR0_CLB0F_Msk                       /*!< Clear Line byte counter 0 flag */
+#define CSI_FCR0_CLB1F_Pos              (1U)
+#define CSI_FCR0_CLB1F_Msk              (0x1UL << CSI_FCR0_CLB1F_Pos)             /*!< 0x00000002 */
+#define CSI_FCR0_CLB1F                  CSI_FCR0_CLB1F_Msk                       /*!< Clear Line byte counter 1 flag */
+#define CSI_FCR0_CLB2F_Pos              (2U)
+#define CSI_FCR0_CLB2F_Msk              (0x1UL << CSI_FCR0_CLB2F_Pos)             /*!< 0x00000004 */
+#define CSI_FCR0_CLB2F                  CSI_FCR0_CLB2F_Msk                       /*!< Clear Line byte counter 2 flag */
+#define CSI_FCR0_CLB3F_Pos              (3U)
+#define CSI_FCR0_CLB3F_Msk              (0x1UL << CSI_FCR0_CLB3F_Pos)             /*!< 0x00000008 */
+#define CSI_FCR0_CLB3F                  CSI_FCR0_CLB3F_Msk                       /*!< Clear Line byte counter 3 flag */
+#define CSI_FCR0_CTIM0F_Pos             (4U)
+#define CSI_FCR0_CTIM0F_Msk             (0x1UL << CSI_FCR0_CTIM0F_Pos)            /*!< 0x00000010 */
+#define CSI_FCR0_CTIM0F                 CSI_FCR0_CTIM0F_Msk                      /*!< Clear Timer 0 flag */
+#define CSI_FCR0_CTIM1F_Pos             (5U)
+#define CSI_FCR0_CTIM1F_Msk             (0x1UL << CSI_FCR0_CTIM1F_Pos)            /*!< 0x00000020 */
+#define CSI_FCR0_CTIM1F                 CSI_FCR0_CTIM1F_Msk                      /*!< Clear Timer 1 flag */
+#define CSI_FCR0_CTIM2F_Pos             (6U)
+#define CSI_FCR0_CTIM2F_Msk             (0x1UL << CSI_FCR0_CTIM2F_Pos)            /*!< 0x00000040 */
+#define CSI_FCR0_CTIM2F                 CSI_FCR0_CTIM2F_Msk                      /*!< Clear Timer 2 flag */
+#define CSI_FCR0_CTIM3F_Pos             (7U)
+#define CSI_FCR0_CTIM3F_Msk             (0x1UL << CSI_FCR0_CTIM3F_Pos)            /*!< 0x00000080 */
+#define CSI_FCR0_CTIM3F                 CSI_FCR0_CTIM3F_Msk                      /*!< Clear Timer 3 flag */
+#define CSI_FCR0_CSOF0F_Pos             (8U)
+#define CSI_FCR0_CSOF0F_Msk             (0x1UL << CSI_FCR0_CSOF0F_Pos)            /*!< 0x00000100 */
+#define CSI_FCR0_CSOF0F                 CSI_FCR0_CSOF0F_Msk                      /*!< Clear Start of frame flag for virtual channel 0 */
+#define CSI_FCR0_CSOF1F_Pos             (9U)
+#define CSI_FCR0_CSOF1F_Msk             (0x1UL << CSI_FCR0_CSOF1F_Pos)            /*!< 0x00000200 */
+#define CSI_FCR0_CSOF1F                 CSI_FCR0_CSOF1F_Msk                      /*!< Clear Start of frame flag for virtual channel 1 */
+#define CSI_FCR0_CSOF2F_Pos             (10U)
+#define CSI_FCR0_CSOF2F_Msk             (0x1UL << CSI_FCR0_CSOF2F_Pos)            /*!< 0x00000400 */
+#define CSI_FCR0_CSOF2F                 CSI_FCR0_CSOF2F_Msk                      /*!< Clear Start of frame flag for virtual channel 2 */
+#define CSI_FCR0_CSOF3F_Pos             (11U)
+#define CSI_FCR0_CSOF3F_Msk             (0x1UL << CSI_FCR0_CSOF3F_Pos)            /*!< 0x00000800 */
+#define CSI_FCR0_CSOF3F                 CSI_FCR0_CSOF3F_Msk                      /*!< Clear Start of frame flag for virtual channel 3 */
+#define CSI_FCR0_CEOF0F_Pos             (12U)
+#define CSI_FCR0_CEOF0F_Msk             (0x1UL << CSI_FCR0_CEOF0F_Pos)            /*!< 0x00001000 */
+#define CSI_FCR0_CEOF0F                 CSI_FCR0_CEOF0F_Msk                      /*!< Clear End of frame flag for virtual channel 0 */
+#define CSI_FCR0_CEOF1F_Pos             (13U)
+#define CSI_FCR0_CEOF1F_Msk             (0x1UL << CSI_FCR0_CEOF1F_Pos)            /*!< 0x00002000 */
+#define CSI_FCR0_CEOF1F                 CSI_FCR0_CEOF1F_Msk                      /*!< Clear End of frame flag for virtual channel 1 */
+#define CSI_FCR0_CEOF2F_Pos             (14U)
+#define CSI_FCR0_CEOF2F_Msk             (0x1UL << CSI_FCR0_CEOF2F_Pos)            /*!< 0x00004000 */
+#define CSI_FCR0_CEOF2F                 CSI_FCR0_CEOF2F_Msk                      /*!< Clear End of frame flag for virtual channel 2 */
+#define CSI_FCR0_CEOF3F_Pos             (15U)
+#define CSI_FCR0_CEOF3F_Msk             (0x1UL << CSI_FCR0_CEOF3F_Pos)            /*!< 0x00008000 */
+#define CSI_FCR0_CEOF3F                 CSI_FCR0_CEOF3F_Msk                      /*!< Clear End of frame flag for virtual channel 3 */
+#define CSI_FCR0_CSPKTF_Pos             (16U)
+#define CSI_FCR0_CSPKTF_Msk             (0x1UL << CSI_FCR0_CSPKTF_Pos)            /*!< 0x00010000 */
+#define CSI_FCR0_CSPKTF                 CSI_FCR0_CSPKTF_Msk                      /*!< Clear Short packet flag */
+#define CSI_FCR0_CCCFIFOFF_Pos          (21U)
+#define CSI_FCR0_CCCFIFOFF_Msk          (0x1UL << CSI_FCR0_CCCFIFOFF_Pos)         /*!< 0x00200000 */
+#define CSI_FCR0_CCCFIFOFF              CSI_FCR0_CCCFIFOFF_Msk                   /*!< Clear Clock changer FIFO full flag */
+#define CSI_FCR0_CCRCERRF_Pos           (24U)
+#define CSI_FCR0_CCRCERRF_Msk           (0x1UL << CSI_FCR0_CCRCERRF_Pos)          /*!< 0x01000000 */
+#define CSI_FCR0_CCRCERRF               CSI_FCR0_CCRCERRF_Msk                    /*!< Clear CRC error flag */
+#define CSI_FCR0_CECCERRF_Pos           (25U)
+#define CSI_FCR0_CECCERRF_Msk           (0x1UL << CSI_FCR0_CECCERRF_Pos)          /*!< 0x02000000 */
+#define CSI_FCR0_CECCERRF               CSI_FCR0_CECCERRF_Msk                    /*!< Clear ECC error flag */
+#define CSI_FCR0_CCECCERRF_Pos          (26U)
+#define CSI_FCR0_CCECCERRF_Msk          (0x1UL << CSI_FCR0_CCECCERRF_Pos)         /*!< 0x04000000 */
+#define CSI_FCR0_CCECCERRF              CSI_FCR0_CCECCERRF_Msk                   /*!< Clear Corrected ECC error flag */
+#define CSI_FCR0_CIDERRF_Pos            (27U)
+#define CSI_FCR0_CIDERRF_Msk            (0x1UL << CSI_FCR0_CIDERRF_Pos)           /*!< 0x08000000 */
+#define CSI_FCR0_CIDERRF                CSI_FCR0_CIDERRF_Msk                     /*!< Clear Data type ID error flag */
+#define CSI_FCR0_CSPKTERRF_Pos          (28U)
+#define CSI_FCR0_CSPKTERRF_Msk          (0x1UL << CSI_FCR0_CSPKTERRF_Pos)         /*!< 0x10000000 */
+#define CSI_FCR0_CSPKTERRF              CSI_FCR0_CSPKTERRF_Msk                   /*!< Clear Short packet error flag */
+#define CSI_FCR0_CWDERRF_Pos            (29U)
+#define CSI_FCR0_CWDERRF_Msk            (0x1UL << CSI_FCR0_CWDERRF_Pos)           /*!< 0x20000000 */
+#define CSI_FCR0_CWDERRF                CSI_FCR0_CWDERRF_Msk                     /*!< Clear Watchdog error flag */
+#define CSI_FCR0_CSYNCERRF_Pos          (30U)
+#define CSI_FCR0_CSYNCERRF_Msk          (0x1UL << CSI_FCR0_CSYNCERRF_Pos)         /*!< 0x40000000 */
+#define CSI_FCR0_CSYNCERRF              CSI_FCR0_CSYNCERRF_Msk                   /*!< Clear Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_FCR1 register  *******************/
+#define CSI_FCR1_CESOTDL0F_Pos          (0U)
+#define CSI_FCR1_CESOTDL0F_Msk          (0x1UL << CSI_FCR1_CESOTDL0F_Pos)         /*!< 0x00000001 */
+#define CSI_FCR1_CESOTDL0F              CSI_FCR1_CESOTDL0F_Msk                   /*!< Clear Start of transmission error flag on lane 0 */
+#define CSI_FCR1_CESOTSYNCDL0F_Pos      (1U)
+#define CSI_FCR1_CESOTSYNCDL0F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos)     /*!< 0x00000002 */
+#define CSI_FCR1_CESOTSYNCDL0F          CSI_FCR1_CESOTSYNCDL0F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 0 */
+#define CSI_FCR1_CEESCDL0F_Pos          (2U)
+#define CSI_FCR1_CEESCDL0F_Msk          (0x1UL << CSI_FCR1_CEESCDL0F_Pos)         /*!< 0x00000004 */
+#define CSI_FCR1_CEESCDL0F              CSI_FCR1_CEESCDL0F_Msk                   /*!< Clear D-PHY_RX lane 0 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL0F_Pos      (3U)
+#define CSI_FCR1_CESYNCESCDL0F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos)     /*!< 0x00000008 */
+#define CSI_FCR1_CESYNCESCDL0F          CSI_FCR1_CESYNCESCDL0F_Msk               /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL0F_Pos         (4U)
+#define CSI_FCR1_CECTRLDL0F_Msk         (0x1UL << CSI_FCR1_CECTRLDL0F_Pos)        /*!< 0x00000010 */
+#define CSI_FCR1_CECTRLDL0F             CSI_FCR1_CECTRLDL0F_Msk                  /*!< Clear D-PHY_RX lane 0 control error flag */
+#define CSI_FCR1_CESOTDL1F_Pos          (8U)
+#define CSI_FCR1_CESOTDL1F_Msk          (0x1UL << CSI_FCR1_CESOTDL1F_Pos)         /*!< 0x00000100 */
+#define CSI_FCR1_CESOTDL1F              CSI_FCR1_CESOTDL1F_Msk                   /*!< Clear Start of transmission error flag on lane 1 */
+#define CSI_FCR1_CESOTSYNCDL1F_Pos      (9U)
+#define CSI_FCR1_CESOTSYNCDL1F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos)     /*!< 0x00000200 */
+#define CSI_FCR1_CESOTSYNCDL1F          CSI_FCR1_CESOTSYNCDL1F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 1 */
+#define CSI_FCR1_CEESCDL1F_Pos          (10U)
+#define CSI_FCR1_CEESCDL1F_Msk          (0x1UL << CSI_FCR1_CEESCDL1F_Pos)         /*!< 0x00000400 */
+#define CSI_FCR1_CEESCDL1F              CSI_FCR1_CEESCDL1F_Msk                   /*!< Clear D-PHY_RX lane 1 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL1F_Pos      (11U)
+#define CSI_FCR1_CESYNCESCDL1F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos)     /*!< 0x00000800 */
+#define CSI_FCR1_CESYNCESCDL1F          CSI_FCR1_CESYNCESCDL1F_Msk               /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL1F_Pos         (12U)
+#define CSI_FCR1_CECTRLDL1F_Msk         (0x1UL << CSI_FCR1_CECTRLDL1F_Pos)        /*!< 0x00001000 */
+#define CSI_FCR1_CECTRLDL1F             CSI_FCR1_CECTRLDL1F_Msk                  /*!< Clear D-PHY_RX lane 1 control error flag */
+
+/******************  Bit definition for CSI_SPDFR register  *******************/
+#define CSI_SPDFR_DATAFIELD_Pos         (0U)
+#define CSI_SPDFR_DATAFIELD_Msk         (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos)     /*!< 0x0000FFFF */
+#define CSI_SPDFR_DATAFIELD             CSI_SPDFR_DATAFIELD_Msk                  /*!< Data field */
+#define CSI_SPDFR_DATATYPE_Pos          (16U)
+#define CSI_SPDFR_DATATYPE_Msk          (0x3FUL << CSI_SPDFR_DATATYPE_Pos)        /*!< 0x003F0000 */
+#define CSI_SPDFR_DATATYPE              CSI_SPDFR_DATATYPE_Msk                   /*!< Data type class */
+#define CSI_SPDFR_VCHANNEL_Pos          (22U)
+#define CSI_SPDFR_VCHANNEL_Msk          (0x3UL << CSI_SPDFR_VCHANNEL_Pos)         /*!< 0x00C00000 */
+#define CSI_SPDFR_VCHANNEL              CSI_SPDFR_VCHANNEL_Msk                   /*!< Virtual channel */
+
+/*******************  Bit definition for CSI_ERR1 register  *******************/
+#define CSI_ERR1_CRCDTERR_Pos           (0U)
+#define CSI_ERR1_CRCDTERR_Msk           (0x3FUL << CSI_ERR1_CRCDTERR_Pos)         /*!< 0x0000003F */
+#define CSI_ERR1_CRCDTERR               CSI_ERR1_CRCDTERR_Msk                    /*!< Data type having a CRC error */
+#define CSI_ERR1_CRCVCERR_Pos           (6U)
+#define CSI_ERR1_CRCVCERR_Msk           (0x3UL << CSI_ERR1_CRCVCERR_Pos)          /*!< 0x000000C0 */
+#define CSI_ERR1_CRCVCERR               CSI_ERR1_CRCVCERR_Msk                    /*!< Virtual channel having a CRC error */
+#define CSI_ERR1_CECCDTERR_Pos          (8U)
+#define CSI_ERR1_CECCDTERR_Msk          (0x3FUL << CSI_ERR1_CECCDTERR_Pos)        /*!< 0x00003F00 */
+#define CSI_ERR1_CECCDTERR              CSI_ERR1_CECCDTERR_Msk                   /*!< Data type having a corrected ECC error */
+#define CSI_ERR1_CECCVCERR_Pos          (14U)
+#define CSI_ERR1_CECCVCERR_Msk          (0x3UL << CSI_ERR1_CECCVCERR_Pos)         /*!< 0x0000C000 */
+#define CSI_ERR1_CECCVCERR              CSI_ERR1_CECCVCERR_Msk                   /*!< Virtual channel having a corrected ECC error */
+#define CSI_ERR1_IDDTERR_Pos            (16U)
+#define CSI_ERR1_IDDTERR_Msk            (0x3FUL << CSI_ERR1_IDDTERR_Pos)          /*!< 0x003F0000 */
+#define CSI_ERR1_IDDTERR                CSI_ERR1_IDDTERR_Msk                     /*!< Data type in error */
+#define CSI_ERR1_IDVCERR_Pos            (22U)
+#define CSI_ERR1_IDVCERR_Msk            (0x3UL << CSI_ERR1_IDVCERR_Pos)           /*!< 0x00C00000 */
+#define CSI_ERR1_IDVCERR                CSI_ERR1_IDVCERR_Msk                     /*!< Virtual channel having ID error */
+
+/*******************  Bit definition for CSI_ERR2 register  *******************/
+#define CSI_ERR2_SPKTDTERR_Pos          (0U)
+#define CSI_ERR2_SPKTDTERR_Msk          (0x3FUL << CSI_ERR2_SPKTDTERR_Pos)        /*!< 0x0000003F */
+#define CSI_ERR2_SPKTDTERR              CSI_ERR2_SPKTDTERR_Msk                   /*!< Data type having a short packet error */
+#define CSI_ERR2_SPKTVCERR_Pos          (6U)
+#define CSI_ERR2_SPKTVCERR_Msk          (0x3UL << CSI_ERR2_SPKTVCERR_Pos)         /*!< 0x000000C0 */
+#define CSI_ERR2_SPKTVCERR              CSI_ERR2_SPKTVCERR_Msk                   /*!< Virtual channel having a short packet error */
+#define CSI_ERR2_WDVCERR_Pos            (16U)
+#define CSI_ERR2_WDVCERR_Msk            (0x3UL << CSI_ERR2_WDVCERR_Pos)           /*!< 0x00030000 */
+#define CSI_ERR2_WDVCERR                CSI_ERR2_WDVCERR_Msk                     /*!< Virtual channel having a watchdog error */
+#define CSI_ERR2_SYNCVCERR_Pos          (18U)
+#define CSI_ERR2_SYNCVCERR_Msk          (0x3UL << CSI_ERR2_SYNCVCERR_Pos)         /*!< 0x000C0000 */
+#define CSI_ERR2_SYNCVCERR              CSI_ERR2_SYNCVCERR_Msk                   /*!< Virtual channel having synchronization error */
+
+/*******************  Bit definition for CSI_PRCR register  *******************/
+#define CSI_PRCR_PEN_Pos                (1U)
+#define CSI_PRCR_PEN_Msk                (0x1UL << CSI_PRCR_PEN_Pos)               /*!< 0x00000002 */
+#define CSI_PRCR_PEN                    CSI_PRCR_PEN_Msk                         /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */
+
+/*******************  Bit definition for CSI_PMCR register  *******************/
+#define CSI_PMCR_FRXMDL0_Pos            (0U)
+#define CSI_PMCR_FRXMDL0_Msk            (0x1UL << CSI_PMCR_FRXMDL0_Pos)           /*!< 0x00000001 */
+#define CSI_PMCR_FRXMDL0                CSI_PMCR_FRXMDL0_Msk                     /*!< Force to Rx Mode the Data Lane 0 */
+#define CSI_PMCR_FRXMDL1_Pos            (1U)
+#define CSI_PMCR_FRXMDL1_Msk            (0x1UL << CSI_PMCR_FRXMDL1_Pos)           /*!< 0x00000002 */
+#define CSI_PMCR_FRXMDL1                CSI_PMCR_FRXMDL1_Msk                     /*!< Force to Rx Mode the Data Lane 1 */
+#define CSI_PMCR_FTXSMDL0_Pos           (2U)
+#define CSI_PMCR_FTXSMDL0_Msk           (0x1UL << CSI_PMCR_FTXSMDL0_Pos)          /*!< 0x00000004 */
+#define CSI_PMCR_FTXSMDL0               CSI_PMCR_FTXSMDL0_Msk                    /*!< Force to Tx Stop Mode the Data Lane 0 */
+#define CSI_PMCR_DTDL_Pos               (4U)
+#define CSI_PMCR_DTDL_Msk               (0x1UL << CSI_PMCR_DTDL_Pos)              /*!< 0x00000010 */
+#define CSI_PMCR_DTDL                   CSI_PMCR_DTDL_Msk                        /*!< Disable Turn-around Data Lane 0 */
+#define CSI_PMCR_RTDL0_Pos              (8U)
+#define CSI_PMCR_RTDL0_Msk              (0x1UL << CSI_PMCR_RTDL0_Pos)             /*!< 0x00000100 */
+#define CSI_PMCR_RTDL0                  CSI_PMCR_RTDL0_Msk                       /*!< Turn-around Request Data Lane 0 */
+#define CSI_PMCR_TUESDL0_Pos            (12U)
+#define CSI_PMCR_TUESDL0_Msk            (0x1UL << CSI_PMCR_TUESDL0_Pos)           /*!< 0x00001000 */
+#define CSI_PMCR_TUESDL0                CSI_PMCR_TUESDL0_Msk                     /*!< Tx ULP Escape-mode Data Lane 0 */
+#define CSI_PMCR_TUEXDL0_Pos            (16U)
+#define CSI_PMCR_TUEXDL0_Msk            (0x1UL << CSI_PMCR_TUEXDL0_Pos)           /*!< 0x00010000 */
+#define CSI_PMCR_TUEXDL0                CSI_PMCR_TUEXDL0_Msk                     /*!< Tx ULP Exit-sequence Data Lane 0 */
+
+/*******************  Bit definition for CSI_PFCR register  *******************/
+#define CSI_PFCR_CCFR_Pos               (0U)
+#define CSI_PFCR_CCFR_Msk               (0x3FUL << CSI_PFCR_CCFR_Pos)             /*!< 0x0000003F */
+#define CSI_PFCR_CCFR                   CSI_PFCR_CCFR_Msk                        /*!< Configuration Clock Frequency Range selection */
+#define CSI_PFCR_HSFR_Pos               (8U)
+#define CSI_PFCR_HSFR_Msk               (0x7FUL << CSI_PFCR_HSFR_Pos)             /*!< 0x00007F00 */
+#define CSI_PFCR_HSFR                   CSI_PFCR_HSFR_Msk                        /*!< PHY-high-speed Frequency Range selection */
+#define CSI_PFCR_DLD_Pos                (16U)
+#define CSI_PFCR_DLD_Msk                (0x1UL << CSI_PFCR_DLD_Pos)               /*!< 0x00010000 */
+#define CSI_PFCR_DLD                    CSI_PFCR_DLD_Msk                         /*!< Data Lane Direction of lane0 */
+
+/******************  Bit definition for CSI_PTCR0 register  *******************/
+#define CSI_PTCR0_TCKEN_Pos             (0U)
+#define CSI_PTCR0_TCKEN_Msk             (0x1UL << CSI_PTCR0_TCKEN_Pos)            /*!< 0x00000001 */
+#define CSI_PTCR0_TCKEN                 CSI_PTCR0_TCKEN_Msk                      /*!< Test-interface Clock Enable for the TDI bus into the PHY */
+#define CSI_PTCR0_TRSEN_Pos             (1U)
+#define CSI_PTCR0_TRSEN_Msk             (0x1UL << CSI_PTCR0_TRSEN_Pos)            /*!< 0x00000002 */
+#define CSI_PTCR0_TRSEN                 CSI_PTCR0_TRSEN_Msk                      /*!< Test-interface Reset Enable for the TDI bus into the PHY */
+
+/******************  Bit definition for CSI_PTCR1 register  *******************/
+#define CSI_PTCR1_TDI_Pos               (0U)
+#define CSI_PTCR1_TDI_Msk               (0xFFUL << CSI_PTCR1_TDI_Pos)             /*!< 0x000000FF */
+#define CSI_PTCR1_TDI                   CSI_PTCR1_TDI_Msk                        /*!< Test-interface Data In */
+#define CSI_PTCR1_TWM_Pos               (16U)
+#define CSI_PTCR1_TWM_Msk               (0x1UL << CSI_PTCR1_TWM_Pos)              /*!< 0x00010000 */
+#define CSI_PTCR1_TWM                   CSI_PTCR1_TWM_Msk                        /*!< Test-interface Write Mode selector */
+
+/*******************  Bit definition for CSI_PTSR register  *******************/
+#define CSI_PTSR_TDO_Pos                (0U)
+#define CSI_PTSR_TDO_Msk                (0xFFUL << CSI_PTSR_TDO_Pos)              /*!< 0x000000FF */
+#define CSI_PTSR_TDO                    CSI_PTSR_TDO_Msk                         /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                DBGMCU                                         */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  ****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos             (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk             (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)          /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                 DBGMCU_IDCODE_DEV_ID_Msk                       /*!< Device ID */
+#define DBGMCU_IDCODE_REV_ID_Pos             (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk             (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)         /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                 DBGMCU_IDCODE_REV_ID_Msk                       /*!< Revision ID */
+
+/********************  Bit definition for DBGMCU_CR register  ********************/
+#define DBGMCU_CR_DBG_SLEEP_Pos              (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk              (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)             /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                  DBGMCU_CR_DBG_SLEEP_Msk                        /*!< Allow debug in Sleep mode */
+#define DBGMCU_CR_DBG_STOP_Pos               (1U)
+#define DBGMCU_CR_DBG_STOP_Msk               (0x1UL << DBGMCU_CR_DBG_STOP_Pos)              /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                   DBGMCU_CR_DBG_STOP_Msk                         /*!< Allow debug in Stop mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos            (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk            (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)           /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                DBGMCU_CR_DBG_STANDBY_Msk                      /*!< Allow debug in Standby mode */
+#define DBGMCU_CR_DBGCLKEN_Pos               (20U)
+#define DBGMCU_CR_DBGCLKEN_Msk               (0x1UL << DBGMCU_CR_DBGCLKEN_Pos)              /*!< 0x00100000 */
+#define DBGMCU_CR_DBGCLKEN                   DBGMCU_CR_DBGCLKEN_Msk                         /*!< Debug clock enable through software */
+#define DBGMCU_CR_TRACECLKEN_Pos             (21U)
+#define DBGMCU_CR_TRACECLKEN_Msk             (0x1UL << DBGMCU_CR_TRACECLKEN_Pos)            /*!< 0x00200000 */
+#define DBGMCU_CR_TRACECLKEN                 DBGMCU_CR_TRACECLKEN_Msk                       /*!< TPIU export clock enable through software */
+#define DBGMCU_CR_DBTRGOEN_Pos               (28U)
+#define DBGMCU_CR_DBTRGOEN_Msk               (0x1UL << DBGMCU_CR_DBTRGOEN_Pos)              /*!< 0x10000000 */
+#define DBGMCU_CR_DBTRGOEN                   DBGMCU_CR_DBTRGOEN_Msk                         /*!< DBTRGIO connection control */
+#define DBGMCU_CR_HLT_TSGEN_EN_Pos           (31U)
+#define DBGMCU_CR_HLT_TSGEN_EN_Msk           (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos)          /*!< 0x80000000 */
+#define DBGMCU_CR_HLT_TSGEN_EN               DBGMCU_CR_HLT_TSGEN_EN_Msk                     /*!< TSGEN halt enable */
+
+/********************  Bit definition for DBGMCU_APB1LFZ1 register  ***************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos    (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP        DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk              /*!< TIM2 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos    (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP        DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk              /*!< TIM3 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos    (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP        DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk              /*!< TIM4 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos    (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP        DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk              /*!< TIM5 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos    (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP        DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk              /*!< TIM6 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos    (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos)  /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP        DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk             /*!< TIM7 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos   (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos)  /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP       DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk             /*!< TIM12 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos   (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos)  /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP       DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk             /*!< TIM13 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos   (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP       DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk             /*!< TIM14 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos  (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP      DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk            /*!< LPTIM1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos   (11U)
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP       DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk             /*!< WWDG1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos   (12U)
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP       DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk             /*!< TIM10 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos   (13U)
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP       DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk             /*!< TIM11 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos    (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos)   /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP        DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk              /*!< I2C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos    (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos)   /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP        DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk              /*!< I2C2 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos    (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos)   /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP        DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk              /*!< I2C3 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos    (24U)
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos)   /*!< 0x01000000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP        DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk              /*!< I3C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos    (25U)
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP        DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk              /*!< I3C2 SMBUS timeout stop in debug */
+
+/********************  Bit definition for DBGMCU_APB1HFZ1 register  ***************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos   (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk   (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP       DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk             /*!< FDCAN stop in debug */
+
+/********************  Bit definition for DBGMCU_APB2FZ1 register  ***************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos     (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos)    /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP         DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk               /*!< TIM1 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos     (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos)    /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP         DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk               /*!< TIM8 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos    (15U)
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP        DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk              /*!< TIM18 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos    (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos)   /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP        DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk              /*!< TIM15 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos    (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos)   /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP        DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk              /*!< TIM16 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos    (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos)   /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP        DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk              /*!< TIM17 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos     (19U)
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos)    /*!< 0x00080000 */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP         DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk               /*!< TIM9 stop in debug */
+
+/********************  Bit definition for DBGMCU_APB4FZ1 register  ***************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos     (8U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos)    /*!< 0x00000100 */
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP         DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk               /*!< I2C4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos   (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos)  /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP       DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk             /*!< LPTIM2 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos   (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP       DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk             /*!< LPTIM3 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos   (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP       DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk             /*!< LPTIM4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos   (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP       DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk             /*!< LPTIM5 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos      (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos)     /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP          DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk                /*!< RTC stop in debug */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos     (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos)    /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP         DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk               /*!< IWDG stop in debug */
+
+/********************  Bit definition for DBGMCU_APB5FZ1 register  ***************/
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos   (4U)
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk   (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos)  /*!< 0x00000010 */
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP       DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk             /*!< GFXTIM stop in debug */
+
+/********************  Bit definition for DBGMCU_AHB1FZ1 register  ***************/
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk              /*!< GPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk              /*!< GPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk              /*!< GPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk              /*!< GPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk              /*!< GPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk              /*!< GPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk              /*!< GPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk              /*!< GPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk              /*!< GPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk              /*!< GPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk             /*!< GPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk             /*!< GPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk             /*!< GPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk             /*!< GPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk             /*!< GPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk             /*!< GPDMA1_CH15 suspend in debug */
+
+/********************  Bit definition for DBGMCU_AHB5FZ1 register  ***************/
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk              /*!< HPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk              /*!< HPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk              /*!< HPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk              /*!< HPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk              /*!< HPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk              /*!< HPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk              /*!< HPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk              /*!< HPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk              /*!< HPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk              /*!< HPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk             /*!< HPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk             /*!< HPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk             /*!< HPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk             /*!< HPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk             /*!< HPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk             /*!< HPDMA1_CH15 suspend in debug */
+#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos         (16U)
+#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk         (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos)        /*!< 0x00010000 */
+#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE             DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk                   /*!< NPU stop in debug mode */
+
+/********************  Bit definition for DBGMCU_SR register  ***************/
+#define DBGMCU_SR_AP0_PRESENT_Pos            (0U)
+#define DBGMCU_SR_AP0_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos)           /*!< 0x00000001 */
+#define DBGMCU_SR_AP0_PRESENT                DBGMCU_SR_AP0_PRESENT_Msk                      /*!< Access point 0 presence */
+#define DBGMCU_SR_AP1_PRESENT_Pos            (1U)
+#define DBGMCU_SR_AP1_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos)           /*!< 0x00000002 */
+#define DBGMCU_SR_AP1_PRESENT                DBGMCU_SR_AP1_PRESENT_Msk                      /*!< Access point 1 presence */
+#define DBGMCU_SR_AP0_ENABLE_Pos             (16U)
+#define DBGMCU_SR_AP0_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos)            /*!< 0x00010000 */
+#define DBGMCU_SR_AP0_ENABLE                 DBGMCU_SR_AP0_ENABLE_Msk                       /*!< Access point 0 enable */
+#define DBGMCU_SR_AP1_ENABLE_Pos             (17U)
+#define DBGMCU_SR_AP1_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos)            /*!< 0x00020000 */
+#define DBGMCU_SR_AP1_ENABLE                 DBGMCU_SR_AP1_ENABLE_Msk                       /*!< Access point 1 enable */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_HOST register  **********************/
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos     (0U)
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk     (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE         DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk                   /*!< Message[31:0] */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos      (0U)
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk      (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE          DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk                    /*!< Message[31:0] */
+
+/********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***************/
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos     (0U)
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk     (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos)    /*!< 0x00000001 */
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK         DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk               /*!< Access status to DBG_AUTH_HOST register */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos   (1U)
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk   (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos)  /*!< 0x00000002 */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK       DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk             /*!< Access status to DBG_AUTH_DEV register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos                 (0U)
+#define DCMI_CR_CAPTURE_Msk                 (0x1UL << DCMI_CR_CAPTURE_Pos)          /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE                     DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos                      (1U)
+#define DCMI_CR_CM_Msk                      (0x1UL << DCMI_CR_CM_Pos)               /*!< 0x00000002 */
+#define DCMI_CR_CM                          DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos                    (2U)
+#define DCMI_CR_CROP_Msk                    (0x1UL << DCMI_CR_CROP_Pos)             /*!< 0x00000004 */
+#define DCMI_CR_CROP                        DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos                    (3U)
+#define DCMI_CR_JPEG_Msk                    (0x1UL << DCMI_CR_JPEG_Pos)             /*!< 0x00000008 */
+#define DCMI_CR_JPEG                        DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos                     (4U)
+#define DCMI_CR_ESS_Msk                     (0x1UL << DCMI_CR_ESS_Pos)              /*!< 0x00000010 */
+#define DCMI_CR_ESS                         DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos                  (5U)
+#define DCMI_CR_PCKPOL_Msk                  (0x1UL << DCMI_CR_PCKPOL_Pos)           /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL                      DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos                   (6U)
+#define DCMI_CR_HSPOL_Msk                   (0x1UL << DCMI_CR_HSPOL_Pos)            /*!< 0x00000040 */
+#define DCMI_CR_HSPOL                       DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos                   (7U)
+#define DCMI_CR_VSPOL_Msk                   (0x1UL << DCMI_CR_VSPOL_Pos)            /*!< 0x00000080 */
+#define DCMI_CR_VSPOL                       DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_Pos                    (8U)
+#define DCMI_CR_FCRC_Msk                    (0x3UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000300 */
+#define DCMI_CR_FCRC                        DCMI_CR_FCRC_Msk                        /*!< DCMI Frame capture rate control FCRC[1:0] */
+#define DCMI_CR_FCRC_0                      (0x1UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000100 */
+#define DCMI_CR_FCRC_1                      (0x2UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000200 */
+#define DCMI_CR_EDM_Pos                     (10U)
+#define DCMI_CR_EDM_Msk                     (0x3UL << DCMI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define DCMI_CR_EDM                         DCMI_CR_EDM_Msk                         /*!< DCMI Extended data mode EDM[1:0] */
+#define DCMI_CR_EDM_0                       (0x1UL << DCMI_CR_EDM_Pos)              /*!< 0x00000400 */
+#define DCMI_CR_EDM_1                       (0x2UL << DCMI_CR_EDM_Pos)              /*!< 0x00000800 */
+#define DCMI_CR_ENABLE_Pos                  (14U)
+#define DCMI_CR_ENABLE_Msk                  (0x1UL << DCMI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define DCMI_CR_ENABLE                      DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos                     (16U)
+#define DCMI_CR_BSM_Msk                     (0x3UL << DCMI_CR_BSM_Pos)              /*!< 0x00030000 */
+#define DCMI_CR_BSM                         DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0                       (0x1UL << DCMI_CR_BSM_Pos)              /*!< 0x00010000 */
+#define DCMI_CR_BSM_1                       (0x2UL << DCMI_CR_BSM_Pos)              /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos                    (18U)
+#define DCMI_CR_OEBS_Msk                    (0x1UL << DCMI_CR_OEBS_Pos)             /*!< 0x00040000 */
+#define DCMI_CR_OEBS                        DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos                     (19U)
+#define DCMI_CR_LSM_Msk                     (0x1UL << DCMI_CR_LSM_Pos)              /*!< 0x00080000 */
+#define DCMI_CR_LSM                         DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos                    (20U)
+#define DCMI_CR_OELS_Msk                    (0x1UL << DCMI_CR_OELS_Pos)             /*!< 0x00100000 */
+#define DCMI_CR_OELS                        DCMI_CR_OELS_Msk
+#define DCMI_CR_PSDM_Pos                    (31U)
+#define DCMI_CR_PSDM_Msk                    (0x0UL << DCMI_CR_PSDM_Pos)             /*!< 0x00000000 */
+#define DCMI_CR_PSDM                        DCMI_CR_PSDM_Msk                        /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos                   (0U)
+#define DCMI_SR_HSYNC_Msk                   (0x1UL << DCMI_SR_HSYNC_Pos)            /*!< 0x00000001 */
+#define DCMI_SR_HSYNC                       DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos                   (1U)
+#define DCMI_SR_VSYNC_Msk                   (0x1UL << DCMI_SR_VSYNC_Pos)            /*!< 0x00000002 */
+#define DCMI_SR_VSYNC                       DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos                     (2U)
+#define DCMI_SR_FNE_Msk                     (0x1UL << DCMI_SR_FNE_Pos)              /*!< 0x00000004 */
+#define DCMI_SR_FNE                         DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos              (0U)
+#define DCMI_RIS_FRAME_RIS_Msk              (0x1UL << DCMI_RIS_FRAME_RIS_Pos)       /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS                  DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos                (1U)
+#define DCMI_RIS_OVR_RIS_Msk                (0x1UL << DCMI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS                    DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos                (2U)
+#define DCMI_RIS_ERR_RIS_Msk                (0x1UL << DCMI_RIS_ERR_RIS_Pos)         /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS                    DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos              (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk              (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)       /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos               (4U)
+#define DCMI_RIS_LINE_RIS_Msk               (0x1UL << DCMI_RIS_LINE_RIS_Pos)        /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS                   DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos               (0U)
+#define DCMI_IER_FRAME_IE_Msk               (0x1UL << DCMI_IER_FRAME_IE_Pos)        /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE                   DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos                 (1U)
+#define DCMI_IER_OVR_IE_Msk                 (0x1UL << DCMI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE                     DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos                 (2U)
+#define DCMI_IER_ERR_IE_Msk                 (0x1UL << DCMI_IER_ERR_IE_Pos)          /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE                     DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos               (3U)
+#define DCMI_IER_VSYNC_IE_Msk               (0x1UL << DCMI_IER_VSYNC_IE_Pos)        /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE                   DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos                (4U)
+#define DCMI_IER_LINE_IE_Msk                (0x1UL << DCMI_IER_LINE_IE_Pos)         /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE                    DCMI_IER_LINE_IE_Msk
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos              (0U)
+#define DCMI_MIS_FRAME_MIS_Msk              (0x1UL << DCMI_MIS_FRAME_MIS_Pos)       /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS                  DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos                (1U)
+#define DCMI_MIS_OVR_MIS_Msk                (0x1UL << DCMI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS                    DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos                (2U)
+#define DCMI_MIS_ERR_MIS_Msk                (0x1UL << DCMI_MIS_ERR_MIS_Pos)         /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS                    DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos              (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk              (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)       /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos               (4U)
+#define DCMI_MIS_LINE_MIS_Msk               (0x1UL << DCMI_MIS_LINE_MIS_Pos)        /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS                   DCMI_MIS_LINE_MIS_Msk
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos              (0U)
+#define DCMI_ICR_FRAME_ISC_Msk              (0x1UL << DCMI_ICR_FRAME_ISC_Pos)       /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC                  DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos                (1U)
+#define DCMI_ICR_OVR_ISC_Msk                (0x1UL << DCMI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC                    DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos                (2U)
+#define DCMI_ICR_ERR_ISC_Msk                (0x1UL << DCMI_ICR_ERR_ISC_Pos)         /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC                    DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos              (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk              (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)       /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC                  DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos               (4U)
+#define DCMI_ICR_LINE_ISC_Msk               (0x1UL << DCMI_ICR_LINE_ISC_Pos)        /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC                   DCMI_ICR_LINE_ISC_Msk
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos                   (0U)
+#define DCMI_ESCR_FSC_Msk                   (0xFFUL << DCMI_ESCR_FSC_Pos)           /*!< 0x000000FF */
+#define DCMI_ESCR_FSC                       DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos                   (8U)
+#define DCMI_ESCR_LSC_Msk                   (0xFFUL << DCMI_ESCR_LSC_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC                       DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos                   (16U)
+#define DCMI_ESCR_LEC_Msk                   (0xFFUL << DCMI_ESCR_LEC_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC                       DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos                   (24U)
+#define DCMI_ESCR_FEC_Msk                   (0xFFUL << DCMI_ESCR_FEC_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC                       DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos                   (0U)
+#define DCMI_ESUR_FSU_Msk                   (0xFFUL << DCMI_ESUR_FSU_Pos)           /*!< 0x000000FF */
+#define DCMI_ESUR_FSU                       DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos                   (8U)
+#define DCMI_ESUR_LSU_Msk                   (0xFFUL << DCMI_ESUR_LSU_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU                       DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos                   (16U)
+#define DCMI_ESUR_LEU_Msk                   (0xFFUL << DCMI_ESUR_LEU_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU                       DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos                   (24U)
+#define DCMI_ESUR_FEU_Msk                   (0xFFUL << DCMI_ESUR_FEU_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU                       DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos             (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk             (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)   /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT                 DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos                 (16U)
+#define DCMI_CWSTRT_VST_Msk                 (0x1FFFUL << DCMI_CWSTRT_VST_Pos)       /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST                     DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos              (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk              (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)    /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT                  DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos               (16U)
+#define DCMI_CWSIZE_VLINE_Msk               (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)     /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE                   DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos                   (0U)
+#define DCMI_DR_BYTE0_Msk                   (0xFFUL << DCMI_DR_BYTE0_Pos)           /*!< 0x000000FF */
+#define DCMI_DR_BYTE0                       DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos                   (8U)
+#define DCMI_DR_BYTE1_Msk                   (0xFFUL << DCMI_DR_BYTE1_Pos)           /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1                       DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos                   (16U)
+#define DCMI_DR_BYTE2_Msk                   (0xFFUL << DCMI_DR_BYTE2_Pos)           /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2                       DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos                   (24U)
+#define DCMI_DR_BYTE3_Msk                   (0xFFUL << DCMI_DR_BYTE3_Pos)           /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3                       DCMI_DR_BYTE3_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   DCMIPP                                   */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for DCMIPP_IPGR1 register  *****************/
+#define DCMIPP_IPGR1_MEMORYPAGE_Pos         (0U)
+#define DCMIPP_IPGR1_MEMORYPAGE_Msk         (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos)           /*!< 0x00000007 */
+#define DCMIPP_IPGR1_MEMORYPAGE             DCMIPP_IPGR1_MEMORYPAGE_Msk                     /*!< Memory page size, as power of 2 of 64-byte units: */
+#define DCMIPP_IPGR1_QOS_MODE_Pos           (24U)
+#define DCMIPP_IPGR1_QOS_MODE_Msk           (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_IPGR1_QOS_MODE               DCMIPP_IPGR1_QOS_MODE_Msk                       /*!< Quality of service */
+
+/*****************  Bit definition for DCMIPP_IPGR2 register  *****************/
+#define DCMIPP_IPGR2_PSTART_Pos             (0U)
+#define DCMIPP_IPGR2_PSTART_Msk             (0x1UL << DCMIPP_IPGR2_PSTART_Pos)               /*!< 0x00000001 */
+#define DCMIPP_IPGR2_PSTART                 DCMIPP_IPGR2_PSTART_Msk                         /*!< Request to lock the IP-Plug, to allow reconfiguration */
+
+/*****************  Bit definition for DCMIPP_IPGR3 register  *****************/
+#define DCMIPP_IPGR3_IDLE_Pos               (0U)
+#define DCMIPP_IPGR3_IDLE_Msk               (0x1UL << DCMIPP_IPGR3_IDLE_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_IPGR3_IDLE                   DCMIPP_IPGR3_IDLE_Msk                           /*!< Status of IP-Plug */
+
+/*****************  Bit definition for DCMIPP_IPGR8 register  *****************/
+#define DCMIPP_IPGR8_DID_Pos                (0U)
+#define DCMIPP_IPGR8_DID_Msk                (0x3FUL << DCMIPP_IPGR8_DID_Pos)                 /*!< 0x0000003F */
+#define DCMIPP_IPGR8_DID                    DCMIPP_IPGR8_DID_Msk                            /*!< Division identifier (0x14) */
+#define DCMIPP_IPGR8_REVID_Pos              (8U)
+#define DCMIPP_IPGR8_REVID_Msk              (0x1FUL << DCMIPP_IPGR8_REVID_Pos)               /*!< 0x00001F00 */
+#define DCMIPP_IPGR8_REVID                  DCMIPP_IPGR8_REVID_Msk                          /*!< Revision identifier (0x03) */
+#define DCMIPP_IPGR8_ARCHIID_Pos            (16U)
+#define DCMIPP_IPGR8_ARCHIID_Msk            (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos)             /*!< 0x001F0000 */
+#define DCMIPP_IPGR8_ARCHIID                DCMIPP_IPGR8_ARCHIID_Msk                        /*!< Architecture identifier (0x04) */
+#define DCMIPP_IPGR8_IPPID_Pos              (24U)
+#define DCMIPP_IPGR8_IPPID_Msk              (0xFFUL << DCMIPP_IPGR8_IPPID_Pos)               /*!< 0xFF000000 */
+#define DCMIPP_IPGR8_IPPID                  DCMIPP_IPGR8_IPPID_Msk                          /*!< IP identifier (0xAA) */
+
+/****************  Bit definition for DCMIPP_IPC1R1 register  *****************/
+#define DCMIPP_IPC1R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC1R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC1R1_TRAFFIC               DCMIPP_IPC1R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC1R1_OTR_Pos               (8U)
+#define DCMIPP_IPC1R1_OTR_Msk               (0xFUL << DCMIPP_IPC1R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC1R1_OTR                   DCMIPP_IPC1R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC1R2 register  *****************/
+#define DCMIPP_IPC1R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC1R2_WLRU_Msk              (0xFUL << DCMIPP_IPC1R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC1R2_WLRU                  DCMIPP_IPC1R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC1R3 register  *****************/
+#define DCMIPP_IPC1R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC1R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC1R3_DPREGSTART            DCMIPP_IPC1R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC1R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC1R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC1R3_DPREGEND              DCMIPP_IPC1R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC2R1 register  *****************/
+#define DCMIPP_IPC2R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC2R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC2R1_TRAFFIC               DCMIPP_IPC2R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC2R1_OTR_Pos               (8U)
+#define DCMIPP_IPC2R1_OTR_Msk               (0xFUL << DCMIPP_IPC2R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC2R1_OTR                   DCMIPP_IPC2R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC2R2 register  *****************/
+#define DCMIPP_IPC2R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC2R2_WLRU_Msk              (0xFUL << DCMIPP_IPC2R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC2R2_WLRU                  DCMIPP_IPC2R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC2R3 register  *****************/
+#define DCMIPP_IPC2R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC2R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC2R3_DPREGSTART            DCMIPP_IPC2R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC2R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC2R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC2R3_DPREGEND              DCMIPP_IPC2R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC3R1 register  *****************/
+#define DCMIPP_IPC3R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC3R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC3R1_TRAFFIC               DCMIPP_IPC3R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC3R1_OTR_Pos               (8U)
+#define DCMIPP_IPC3R1_OTR_Msk               (0xFUL << DCMIPP_IPC3R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC3R1_OTR                   DCMIPP_IPC3R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC3R2 register  *****************/
+#define DCMIPP_IPC3R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC3R2_WLRU_Msk              (0xFUL << DCMIPP_IPC3R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC3R2_WLRU                  DCMIPP_IPC3R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC3R3 register  *****************/
+#define DCMIPP_IPC3R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC3R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC3R3_DPREGSTART            DCMIPP_IPC3R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC3R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC3R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC3R3_DPREGEND              DCMIPP_IPC3R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC4R1 register  *****************/
+#define DCMIPP_IPC4R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC4R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC4R1_TRAFFIC               DCMIPP_IPC4R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC4R1_OTR_Pos               (8U)
+#define DCMIPP_IPC4R1_OTR_Msk               (0xFUL << DCMIPP_IPC4R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC4R1_OTR                   DCMIPP_IPC4R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC4R2 register  *****************/
+#define DCMIPP_IPC4R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC4R2_WLRU_Msk              (0xFUL << DCMIPP_IPC4R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC4R2_WLRU                  DCMIPP_IPC4R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC4R3 register  *****************/
+#define DCMIPP_IPC4R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC4R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC4R3_DPREGSTART            DCMIPP_IPC4R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC4R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC4R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC4R3_DPREGEND              DCMIPP_IPC4R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC5R1 register  *****************/
+#define DCMIPP_IPC5R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC5R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC5R1_TRAFFIC               DCMIPP_IPC5R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC5R1_OTR_Pos               (8U)
+#define DCMIPP_IPC5R1_OTR_Msk               (0xFUL << DCMIPP_IPC5R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC5R1_OTR                   DCMIPP_IPC5R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC5R2 register  *****************/
+#define DCMIPP_IPC5R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC5R2_WLRU_Msk              (0xFUL << DCMIPP_IPC5R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC5R2_WLRU                  DCMIPP_IPC5R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC5R3 register  *****************/
+#define DCMIPP_IPC5R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC5R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC5R3_DPREGSTART            DCMIPP_IPC5R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC5R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC5R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC5R3_DPREGEND              DCMIPP_IPC5R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/***************  Bit definition for DCMIPP_PRHWCFGR register  ****************/
+
+/*****************  Bit definition for DCMIPP_PRCR register  ******************/
+#define DCMIPP_PRCR_ESS_Pos                 (4U)
+#define DCMIPP_PRCR_ESS_Msk                 (0x1UL << DCMIPP_PRCR_ESS_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_PRCR_ESS                     DCMIPP_PRCR_ESS_Msk                             /*!< Embedded synchronization select */
+#define DCMIPP_PRCR_PCKPOL_Pos              (5U)
+#define DCMIPP_PRCR_PCKPOL_Msk              (0x1UL << DCMIPP_PRCR_PCKPOL_Pos)                /*!< 0x00000020 */
+#define DCMIPP_PRCR_PCKPOL                  DCMIPP_PRCR_PCKPOL_Msk                          /*!< Pixel clock polarity */
+#define DCMIPP_PRCR_HSPOL_Pos               (6U)
+#define DCMIPP_PRCR_HSPOL_Msk               (0x1UL << DCMIPP_PRCR_HSPOL_Pos)                 /*!< 0x00000040 */
+#define DCMIPP_PRCR_HSPOL                   DCMIPP_PRCR_HSPOL_Msk                           /*!< Horizontal synchronization polarity */
+#define DCMIPP_PRCR_VSPOL_Pos               (7U)
+#define DCMIPP_PRCR_VSPOL_Msk               (0x1UL << DCMIPP_PRCR_VSPOL_Pos)                 /*!< 0x00000080 */
+#define DCMIPP_PRCR_VSPOL                   DCMIPP_PRCR_VSPOL_Msk                           /*!< Vertical synchronization polarity */
+#define DCMIPP_PRCR_EDM_Pos                 (10U)
+#define DCMIPP_PRCR_EDM_Msk                 (0x7UL << DCMIPP_PRCR_EDM_Pos)                   /*!< 0x00001C00 */
+#define DCMIPP_PRCR_EDM                     DCMIPP_PRCR_EDM_Msk                             /*!< Extended data mode */
+#define DCMIPP_PRCR_ENABLE_Pos              (14U)
+#define DCMIPP_PRCR_ENABLE_Msk              (0x1UL << DCMIPP_PRCR_ENABLE_Pos)                /*!< 0x00004000 */
+#define DCMIPP_PRCR_ENABLE                  DCMIPP_PRCR_ENABLE_Msk                          /*!< Parallel interface enable */
+#define DCMIPP_PRCR_FORMAT_Pos              (16U)
+#define DCMIPP_PRCR_FORMAT_Msk              (0xFFUL << DCMIPP_PRCR_FORMAT_Pos)               /*!< 0x00FF0000 */
+#define DCMIPP_PRCR_FORMAT                  DCMIPP_PRCR_FORMAT_Msk                          /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */
+#define DCMIPP_PRCR_SWAPCYCLES_Pos          (25U)
+#define DCMIPP_PRCR_SWAPCYCLES_Msk          (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos)            /*!< 0x02000000 */
+#define DCMIPP_PRCR_SWAPCYCLES              DCMIPP_PRCR_SWAPCYCLES_Msk                      /*!< Swap data from cycle 0 vs */
+#define DCMIPP_PRCR_SWAPBITS_Pos            (26U)
+#define DCMIPP_PRCR_SWAPBITS_Msk            (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos)              /*!< 0x04000000 */
+#define DCMIPP_PRCR_SWAPBITS                DCMIPP_PRCR_SWAPBITS_Msk                        /*!< Swap LSB vs */
+
+/****************  Bit definition for DCMIPP_PRESCR register  *****************/
+#define DCMIPP_PRESCR_FSC_Pos               (0U)
+#define DCMIPP_PRESCR_FSC_Msk               (0xFFUL << DCMIPP_PRESCR_FSC_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESCR_FSC                   DCMIPP_PRESCR_FSC_Msk                           /*!< Frame start delimiter code */
+#define DCMIPP_PRESCR_LSC_Pos               (8U)
+#define DCMIPP_PRESCR_LSC_Msk               (0xFFUL << DCMIPP_PRESCR_LSC_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESCR_LSC                   DCMIPP_PRESCR_LSC_Msk                           /*!< Line start delimiter code */
+#define DCMIPP_PRESCR_LEC_Pos               (16U)
+#define DCMIPP_PRESCR_LEC_Msk               (0xFFUL << DCMIPP_PRESCR_LEC_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESCR_LEC                   DCMIPP_PRESCR_LEC_Msk                           /*!< Line end delimiter code */
+#define DCMIPP_PRESCR_FEC_Pos               (24U)
+#define DCMIPP_PRESCR_FEC_Msk               (0xFFUL << DCMIPP_PRESCR_FEC_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESCR_FEC                   DCMIPP_PRESCR_FEC_Msk                           /*!< Frame end delimiter code */
+
+/****************  Bit definition for DCMIPP_PRESUR register  *****************/
+#define DCMIPP_PRESUR_FSU_Pos               (0U)
+#define DCMIPP_PRESUR_FSU_Msk               (0xFFUL << DCMIPP_PRESUR_FSU_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESUR_FSU                   DCMIPP_PRESUR_FSU_Msk                           /*!< Frame start delimiter unmask */
+#define DCMIPP_PRESUR_LSU_Pos               (8U)
+#define DCMIPP_PRESUR_LSU_Msk               (0xFFUL << DCMIPP_PRESUR_LSU_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESUR_LSU                   DCMIPP_PRESUR_LSU_Msk                           /*!< Line start delimiter unmask */
+#define DCMIPP_PRESUR_LEU_Pos               (16U)
+#define DCMIPP_PRESUR_LEU_Msk               (0xFFUL << DCMIPP_PRESUR_LEU_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESUR_LEU                   DCMIPP_PRESUR_LEU_Msk                           /*!< Line end delimiter unmask */
+#define DCMIPP_PRESUR_FEU_Pos               (24U)
+#define DCMIPP_PRESUR_FEU_Msk               (0xFFUL << DCMIPP_PRESUR_FEU_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESUR_FEU                   DCMIPP_PRESUR_FEU_Msk                           /*!< Frame end delimiter unmask */
+
+/*****************  Bit definition for DCMIPP_PRIER register  *****************/
+#define DCMIPP_PRIER_ERRIE_Pos              (6U)
+#define DCMIPP_PRIER_ERRIE_Msk              (0x1UL << DCMIPP_PRIER_ERRIE_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRIER_ERRIE                  DCMIPP_PRIER_ERRIE_Msk                          /*!< Synchronization error interrupt enable */
+
+/*****************  Bit definition for DCMIPP_PRSR register  ******************/
+#define DCMIPP_PRSR_ERRF_Pos                (6U)
+#define DCMIPP_PRSR_ERRF_Msk                (0x1UL << DCMIPP_PRSR_ERRF_Pos)                  /*!< 0x00000040 */
+#define DCMIPP_PRSR_ERRF                    DCMIPP_PRSR_ERRF_Msk                            /*!< Synchronization error raw interrupt status */
+#define DCMIPP_PRSR_HSYNC_Pos               (16U)
+#define DCMIPP_PRSR_HSYNC_Msk               (0x1UL << DCMIPP_PRSR_HSYNC_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_PRSR_HSYNC                   DCMIPP_PRSR_HSYNC_Msk                           /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */
+#define DCMIPP_PRSR_VSYNC_Pos               (17U)
+#define DCMIPP_PRSR_VSYNC_Msk               (0x1UL << DCMIPP_PRSR_VSYNC_Pos)                 /*!< 0x00020000 */
+#define DCMIPP_PRSR_VSYNC                   DCMIPP_PRSR_VSYNC_Msk                           /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */
+
+/*****************  Bit definition for DCMIPP_PRFCR register  *****************/
+#define DCMIPP_PRFCR_CERRF_Pos              (6U)
+#define DCMIPP_PRFCR_CERRF_Msk              (0x1UL << DCMIPP_PRFCR_CERRF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRFCR_CERRF                  DCMIPP_PRFCR_CERRF_Msk                          /*!< Synchronization error interrupt status clear */
+
+/*****************  Bit definition for DCMIPP_CMCR register  ******************/
+#define DCMIPP_CMCR_INSEL_Pos               (0U)
+#define DCMIPP_CMCR_INSEL_Msk               (0x1UL << DCMIPP_CMCR_INSEL_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_CMCR_INSEL                   DCMIPP_CMCR_INSEL_Msk                           /*!< input selection */
+#define DCMIPP_CMCR_PSFC_Pos                (1U)
+#define DCMIPP_CMCR_PSFC_Msk                (0x3UL << DCMIPP_CMCR_PSFC_Pos)                  /*!< 0x00000006 */
+#define DCMIPP_CMCR_PSFC                    DCMIPP_CMCR_PSFC_Msk                            /*!< Pipe selection for the frame counter */
+#define DCMIPP_CMCR_CFC_Pos                 (4U)
+#define DCMIPP_CMCR_CFC_Msk                 (0x1UL << DCMIPP_CMCR_CFC_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_CMCR_CFC                     DCMIPP_CMCR_CFC_Msk                             /*!< Clear frame counter */
+#define DCMIPP_CMCR_SWAPRB_Pos              (7U)
+#define DCMIPP_CMCR_SWAPRB_Msk              (0x1UL << DCMIPP_CMCR_SWAPRB_Pos)                /*!< 0x00000080 */
+#define DCMIPP_CMCR_SWAPRB                  DCMIPP_CMCR_SWAPRB_Msk                          /*!< Swap R/U and B/V */
+
+/****************  Bit definition for DCMIPP_CMFRCR register  *****************/
+#define DCMIPP_CMFRCR_FRMCNT_Pos            (0U)
+#define DCMIPP_CMFRCR_FRMCNT_Msk            (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_CMFRCR_FRMCNT                DCMIPP_CMFRCR_FRMCNT_Msk                        /*!< Frame counter, read-only, loops around */
+
+/*****************  Bit definition for DCMIPP_CMIER register  *****************/
+#define DCMIPP_CMIER_ATXERRIE_Pos           (5U)
+#define DCMIPP_CMIER_ATXERRIE_Msk           (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMIER_ATXERRIE               DCMIPP_CMIER_ATXERRIE_Msk                       /*!< AXI Transfer error interrupt enable for IPPLUG */
+#define DCMIPP_CMIER_PRERRIE_Pos            (6U)
+#define DCMIPP_CMIER_PRERRIE_Msk            (0x1UL << DCMIPP_CMIER_PRERRIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMIER_PRERRIE                DCMIPP_CMIER_PRERRIE_Msk                        /*!< limit interrupt enable for the Parallel Interface */
+#define DCMIPP_CMIER_P0LINEIE_Pos           (8U)
+#define DCMIPP_CMIER_P0LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMIER_P0LINEIE               DCMIPP_CMIER_P0LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0FRAMEIE_Pos          (9U)
+#define DCMIPP_CMIER_P0FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMIER_P0FRAMEIE              DCMIPP_CMIER_P0FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0VSYNCIE_Pos          (10U)
+#define DCMIPP_CMIER_P0VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMIER_P0VSYNCIE              DCMIPP_CMIER_P0VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0LIMITIE_Pos          (14U)
+#define DCMIPP_CMIER_P0LIMITIE_Msk          (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMIER_P0LIMITIE              DCMIPP_CMIER_P0LIMITIE_Msk                      /*!< limit interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0OVRIE_Pos            (15U)
+#define DCMIPP_CMIER_P0OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMIER_P0OVRIE                DCMIPP_CMIER_P0OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P1LINEIE_Pos           (16U)
+#define DCMIPP_CMIER_P1LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMIER_P1LINEIE               DCMIPP_CMIER_P1LINEIE_Msk                       /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */
+#define DCMIPP_CMIER_P1FRAMEIE_Pos          (17U)
+#define DCMIPP_CMIER_P1FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMIER_P1FRAMEIE              DCMIPP_CMIER_P1FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1VSYNCIE_Pos          (18U)
+#define DCMIPP_CMIER_P1VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMIER_P1VSYNCIE              DCMIPP_CMIER_P1VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1OVRIE_Pos            (23U)
+#define DCMIPP_CMIER_P1OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMIER_P1OVRIE                DCMIPP_CMIER_P1OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P2LINEIE_Pos           (24U)
+#define DCMIPP_CMIER_P2LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMIER_P2LINEIE               DCMIPP_CMIER_P2LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2FRAMEIE_Pos          (25U)
+#define DCMIPP_CMIER_P2FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMIER_P2FRAMEIE              DCMIPP_CMIER_P2FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2VSYNCIE_Pos          (26U)
+#define DCMIPP_CMIER_P2VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMIER_P2VSYNCIE              DCMIPP_CMIER_P2VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2OVRIE_Pos            (31U)
+#define DCMIPP_CMIER_P2OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMIER_P2OVRIE                DCMIPP_CMIER_P2OVRIE_Msk                        /*!< Overrun interrupt status enable for the Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR1 register  *****************/
+#define DCMIPP_CMSR1_PRHSYNC_Pos            (0U)
+#define DCMIPP_CMSR1_PRHSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos)              /*!< 0x00000001 */
+#define DCMIPP_CMSR1_PRHSYNC                DCMIPP_CMSR1_PRHSYNC_Msk                        /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_PRVSYNC_Pos            (1U)
+#define DCMIPP_CMSR1_PRVSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos)              /*!< 0x00000002 */
+#define DCMIPP_CMSR1_PRVSYNC                DCMIPP_CMSR1_PRVSYNC_Msk                        /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_P0LSTLINE_Pos          (8U)
+#define DCMIPP_CMSR1_P0LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos)            /*!< 0x00000100 */
+#define DCMIPP_CMSR1_P0LSTLINE              DCMIPP_CMSR1_P0LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0LSTFRM_Pos           (9U)
+#define DCMIPP_CMSR1_P0LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR1_P0LSTFRM               DCMIPP_CMSR1_P0LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0CPTACT_Pos           (15U)
+#define DCMIPP_CMSR1_P0CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos)             /*!< 0x00008000 */
+#define DCMIPP_CMSR1_P0CPTACT               DCMIPP_CMSR1_P0CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */
+#define DCMIPP_CMSR1_P1LSTLINE_Pos          (16U)
+#define DCMIPP_CMSR1_P1LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos)            /*!< 0x00010000 */
+#define DCMIPP_CMSR1_P1LSTLINE              DCMIPP_CMSR1_P1LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1LSTFRM_Pos           (17U)
+#define DCMIPP_CMSR1_P1LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR1_P1LSTFRM               DCMIPP_CMSR1_P1LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1CPTACT_Pos           (23U)
+#define DCMIPP_CMSR1_P1CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos)             /*!< 0x00800000 */
+#define DCMIPP_CMSR1_P1CPTACT               DCMIPP_CMSR1_P1CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */
+#define DCMIPP_CMSR1_P2LSTLINE_Pos          (24U)
+#define DCMIPP_CMSR1_P2LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos)            /*!< 0x01000000 */
+#define DCMIPP_CMSR1_P2LSTLINE              DCMIPP_CMSR1_P2LSTLINE_Msk                      /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2LSTFRM_Pos           (25U)
+#define DCMIPP_CMSR1_P2LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR1_P2LSTFRM               DCMIPP_CMSR1_P2LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2CPTACT_Pos           (31U)
+#define DCMIPP_CMSR1_P2CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos)             /*!< 0x80000000 */
+#define DCMIPP_CMSR1_P2CPTACT               DCMIPP_CMSR1_P2CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR2 register  *****************/
+#define DCMIPP_CMSR2_ATXERRF_Pos            (5U)
+#define DCMIPP_CMSR2_ATXERRF_Msk            (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos)              /*!< 0x00000020 */
+#define DCMIPP_CMSR2_ATXERRF                DCMIPP_CMSR2_ATXERRF_Msk                        /*!< AXI transfer error interrupt status flag for the IPPLUG */
+#define DCMIPP_CMSR2_PRERRF_Pos             (6U)
+#define DCMIPP_CMSR2_PRERRF_Msk             (0x1UL << DCMIPP_CMSR2_PRERRF_Pos)               /*!< 0x00000040 */
+#define DCMIPP_CMSR2_PRERRF                 DCMIPP_CMSR2_PRERRF_Msk                         /*!< Synchronization error raw interrupt status for the parallel interface */
+#define DCMIPP_CMSR2_P0LINEF_Pos            (8U)
+#define DCMIPP_CMSR2_P0LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos)              /*!< 0x00000100 */
+#define DCMIPP_CMSR2_P0LINEF                DCMIPP_CMSR2_P0LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0FRAMEF_Pos           (9U)
+#define DCMIPP_CMSR2_P0FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR2_P0FRAMEF               DCMIPP_CMSR2_P0FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0VSYNCF_Pos           (10U)
+#define DCMIPP_CMSR2_P0VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos)             /*!< 0x00000400 */
+#define DCMIPP_CMSR2_P0VSYNCF               DCMIPP_CMSR2_P0VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0LIMITF_Pos           (14U)
+#define DCMIPP_CMSR2_P0LIMITF_Msk           (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos)             /*!< 0x00004000 */
+#define DCMIPP_CMSR2_P0LIMITF               DCMIPP_CMSR2_P0LIMITF_Msk                       /*!< Limit raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0OVRF_Pos             (15U)
+#define DCMIPP_CMSR2_P0OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos)               /*!< 0x00008000 */
+#define DCMIPP_CMSR2_P0OVRF                 DCMIPP_CMSR2_P0OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P1LINEF_Pos            (16U)
+#define DCMIPP_CMSR2_P1LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos)              /*!< 0x00010000 */
+#define DCMIPP_CMSR2_P1LINEF                DCMIPP_CMSR2_P1LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1FRAMEF_Pos           (17U)
+#define DCMIPP_CMSR2_P1FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR2_P1FRAMEF               DCMIPP_CMSR2_P1FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1VSYNCF_Pos           (18U)
+#define DCMIPP_CMSR2_P1VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos)             /*!< 0x00040000 */
+#define DCMIPP_CMSR2_P1VSYNCF               DCMIPP_CMSR2_P1VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1OVRF_Pos             (23U)
+#define DCMIPP_CMSR2_P1OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos)               /*!< 0x00800000 */
+#define DCMIPP_CMSR2_P1OVRF                 DCMIPP_CMSR2_P1OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P2LINEF_Pos            (24U)
+#define DCMIPP_CMSR2_P2LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos)              /*!< 0x01000000 */
+#define DCMIPP_CMSR2_P2LINEF                DCMIPP_CMSR2_P2LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2FRAMEF_Pos           (25U)
+#define DCMIPP_CMSR2_P2FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR2_P2FRAMEF               DCMIPP_CMSR2_P2FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2VSYNCF_Pos           (26U)
+#define DCMIPP_CMSR2_P2VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos)             /*!< 0x04000000 */
+#define DCMIPP_CMSR2_P2VSYNCF               DCMIPP_CMSR2_P2VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2OVRF_Pos             (31U)
+#define DCMIPP_CMSR2_P2OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos)               /*!< 0x80000000 */
+#define DCMIPP_CMSR2_P2OVRF                 DCMIPP_CMSR2_P2OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMFCR register  *****************/
+#define DCMIPP_CMFCR_CATXERRF_Pos           (5U)
+#define DCMIPP_CMFCR_CATXERRF_Msk           (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMFCR_CATXERRF               DCMIPP_CMFCR_CATXERRF_Msk                       /*!< AXI Transfer error interrupt status clear */
+#define DCMIPP_CMFCR_CPRERRF_Pos            (6U)
+#define DCMIPP_CMFCR_CPRERRF_Msk            (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMFCR_CPRERRF                DCMIPP_CMFCR_CPRERRF_Msk                        /*!< Synchronization error interrupt status clear */
+#define DCMIPP_CMFCR_CP0LINEF_Pos           (8U)
+#define DCMIPP_CMFCR_CP0LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMFCR_CP0LINEF               DCMIPP_CMFCR_CP0LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0FRAMEF_Pos          (9U)
+#define DCMIPP_CMFCR_CP0FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMFCR_CP0FRAMEF              DCMIPP_CMFCR_CP0FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0VSYNCF_Pos          (10U)
+#define DCMIPP_CMFCR_CP0VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMFCR_CP0VSYNCF              DCMIPP_CMFCR_CP0VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP0LIMITF_Pos          (14U)
+#define DCMIPP_CMFCR_CP0LIMITF_Msk          (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMFCR_CP0LIMITF              DCMIPP_CMFCR_CP0LIMITF_Msk                      /*!< limit interrupt status clear */
+#define DCMIPP_CMFCR_CP0OVRF_Pos            (15U)
+#define DCMIPP_CMFCR_CP0OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMFCR_CP0OVRF                DCMIPP_CMFCR_CP0OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP1LINEF_Pos           (16U)
+#define DCMIPP_CMFCR_CP1LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMFCR_CP1LINEF               DCMIPP_CMFCR_CP1LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1FRAMEF_Pos          (17U)
+#define DCMIPP_CMFCR_CP1FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMFCR_CP1FRAMEF              DCMIPP_CMFCR_CP1FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1VSYNCF_Pos          (18U)
+#define DCMIPP_CMFCR_CP1VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMFCR_CP1VSYNCF              DCMIPP_CMFCR_CP1VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP1OVRF_Pos            (23U)
+#define DCMIPP_CMFCR_CP1OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMFCR_CP1OVRF                DCMIPP_CMFCR_CP1OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP2LINEF_Pos           (24U)
+#define DCMIPP_CMFCR_CP2LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMFCR_CP2LINEF               DCMIPP_CMFCR_CP2LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2FRAMEF_Pos          (25U)
+#define DCMIPP_CMFCR_CP2FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMFCR_CP2FRAMEF              DCMIPP_CMFCR_CP2FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2VSYNCF_Pos          (26U)
+#define DCMIPP_CMFCR_CP2VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMFCR_CP2VSYNCF              DCMIPP_CMFCR_CP2VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP2OVRF_Pos            (31U)
+#define DCMIPP_CMFCR_CP2OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMFCR_CP2OVRF                DCMIPP_CMFCR_CP2OVRF_Msk                        /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0FSCR register  *****************/
+#define DCMIPP_P0FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P0FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P0FSCR_DTIDA                 DCMIPP_P0FSCR_DTIDA_Msk                         /*!< Data type selection ID A */
+#define DCMIPP_P0FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P0FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P0FSCR_DTIDB                 DCMIPP_P0FSCR_DTIDB_Msk                         /*!< Data type selection ID B */
+#define DCMIPP_P0FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P0FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P0FSCR_DTMODE                DCMIPP_P0FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_VC_Pos                (19U)
+#define DCMIPP_P0FSCR_VC_Msk                (0x3UL << DCMIPP_P0FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P0FSCR_VC                    DCMIPP_P0FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P0FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P0FSCR_PIPEN                 DCMIPP_P0FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P0FCTCR register  ****************/
+#define DCMIPP_P0FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P0FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P0FCTCR_FRATE                DCMIPP_P0FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P0FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P0FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P0FCTCR_CPTMODE              DCMIPP_P0FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P0FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P0FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P0FCTCR_CPTREQ               DCMIPP_P0FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P0SCSTR register  ****************/
+#define DCMIPP_P0SCSTR_HSTART_Pos           (0U)
+#define DCMIPP_P0SCSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0SCSTR_HSTART               DCMIPP_P0SCSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0SCSTR_VSTART_Pos           (16U)
+#define DCMIPP_P0SCSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSTR_VSTART               DCMIPP_P0SCSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P0SCSZR register  ****************/
+#define DCMIPP_P0SCSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P0SCSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P0SCSZR_HSIZE                DCMIPP_P0SCSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0SCSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P0SCSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSZR_VSIZE                DCMIPP_P0SCSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0SCSZR_POSNEG_Pos           (30U)
+#define DCMIPP_P0SCSZR_POSNEG_Msk           (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P0SCSZR_POSNEG               DCMIPP_P0SCSZR_POSNEG_Msk                       /*!< This bit is set and cleared by software */
+#define DCMIPP_P0SCSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P0SCSZR_ENABLE_Msk           (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P0SCSZR_ENABLE               DCMIPP_P0SCSZR_ENABLE_Msk                       /*!< This bit is set and cleared by software */
+
+/***************  Bit definition for DCMIPP_P0DCCNTR register  ****************/
+#define DCMIPP_P0DCCNTR_CNT_Pos             (0U)
+#define DCMIPP_P0DCCNTR_CNT_Msk             (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos)         /*!< 0x03FFFFFF */
+#define DCMIPP_P0DCCNTR_CNT                 DCMIPP_P0DCCNTR_CNT_Msk                         /*!< Number of data dumped during the frame */
+
+/***************  Bit definition for DCMIPP_P0DCLMTR register  ****************/
+#define DCMIPP_P0DCLMTR_LIMIT_Pos           (0U)
+#define DCMIPP_P0DCLMTR_LIMIT_Msk           (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos)        /*!< 0x00FFFFFF */
+#define DCMIPP_P0DCLMTR_LIMIT               DCMIPP_P0DCLMTR_LIMIT_Msk                       /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */
+#define DCMIPP_P0DCLMTR_ENABLE_Pos          (31U)
+#define DCMIPP_P0DCLMTR_ENABLE_Msk          (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0DCLMTR_ENABLE              DCMIPP_P0DCLMTR_ENABLE_Msk                      /*!<  */
+
+/****************  Bit definition for DCMIPP_P0PPCR register  *****************/
+#define DCMIPP_P0PPCR_SWAPYUV_Pos           (0U)
+#define DCMIPP_P0PPCR_SWAPYUV_Msk           (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P0PPCR_SWAPYUV               DCMIPP_P0PPCR_SWAPYUV_Msk                       /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0PPCR_PAD_Pos               (5U)
+#define DCMIPP_P0PPCR_PAD_Msk               (0x1UL << DCMIPP_P0PPCR_PAD_Pos)                 /*!< 0x00000020 */
+#define DCMIPP_P0PPCR_PAD                   DCMIPP_P0PPCR_PAD_Msk                           /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0PPCR_HEADEREN_Pos          (6U)
+#define DCMIPP_P0PPCR_HEADEREN_Msk          (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos)            /*!< 0x00000040 */
+#define DCMIPP_P0PPCR_HEADEREN              DCMIPP_P0PPCR_HEADEREN_Msk                      /*!< CSI header dump enable */
+#define DCMIPP_P0PPCR_BSM_Pos               (7U)
+#define DCMIPP_P0PPCR_BSM_Msk               (0x3UL << DCMIPP_P0PPCR_BSM_Pos)                 /*!< 0x00000180 */
+#define DCMIPP_P0PPCR_BSM                   DCMIPP_P0PPCR_BSM_Msk                           /*!< Byte select mode */
+#define DCMIPP_P0PPCR_OEBS_Pos              (9U)
+#define DCMIPP_P0PPCR_OEBS_Msk              (0x1UL << DCMIPP_P0PPCR_OEBS_Pos)                /*!< 0x00000200 */
+#define DCMIPP_P0PPCR_OEBS                  DCMIPP_P0PPCR_OEBS_Msk                          /*!< Odd/even byte select (byte select start) */
+#define DCMIPP_P0PPCR_LSM_Pos               (10U)
+#define DCMIPP_P0PPCR_LSM_Msk               (0x1UL << DCMIPP_P0PPCR_LSM_Pos)                 /*!< 0x00000400 */
+#define DCMIPP_P0PPCR_LSM                   DCMIPP_P0PPCR_LSM_Msk                           /*!< Line select mode */
+#define DCMIPP_P0PPCR_OELS_Pos              (11U)
+#define DCMIPP_P0PPCR_OELS_Msk              (0x1UL << DCMIPP_P0PPCR_OELS_Pos)                /*!< 0x00000800 */
+#define DCMIPP_P0PPCR_OELS                  DCMIPP_P0PPCR_OELS_Msk                          /*!< Odd/even line select (line select start) */
+#define DCMIPP_P0PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P0PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P0PPCR_LINEMULT              DCMIPP_P0PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0PPCR_DBM_Pos               (16U)
+#define DCMIPP_P0PPCR_DBM_Msk               (0x1UL << DCMIPP_P0PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P0PPCR_DBM                   DCMIPP_P0PPCR_DBM_Msk                           /*!< Double buffer mode */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR1 register  ***************/
+#define DCMIPP_P0PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR1_M0A                DCMIPP_P0PPM0AR1_M0A_Msk                        /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR2 register  ***************/
+#define DCMIPP_P0PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR2_M0A                DCMIPP_P0PPM0AR2_M0A_Msk                        /*!< Memory0 address */
+
+/*****************  Bit definition for DCMIPP_P0IER register  *****************/
+#define DCMIPP_P0IER_LINEIE_Pos             (0U)
+#define DCMIPP_P0IER_LINEIE_Msk             (0x1UL << DCMIPP_P0IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0IER_LINEIE                 DCMIPP_P0IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P0IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P0IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0IER_FRAMEIE                DCMIPP_P0IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P0IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P0IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0IER_VSYNCIE                DCMIPP_P0IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P0IER_LIMITIE_Pos            (6U)
+#define DCMIPP_P0IER_LIMITIE_Msk            (0x1UL << DCMIPP_P0IER_LIMITIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0IER_LIMITIE                DCMIPP_P0IER_LIMITIE_Msk                        /*!< Limit interrupt enable */
+#define DCMIPP_P0IER_OVRIE_Pos              (7U)
+#define DCMIPP_P0IER_OVRIE_Msk              (0x1UL << DCMIPP_P0IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0IER_OVRIE                  DCMIPP_P0IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P0SR register  ******************/
+#define DCMIPP_P0SR_LINEF_Pos               (0U)
+#define DCMIPP_P0SR_LINEF_Msk               (0x1UL << DCMIPP_P0SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P0SR_LINEF                   DCMIPP_P0SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P0SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P0SR_FRAMEF_Msk              (0x1UL << DCMIPP_P0SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P0SR_FRAMEF                  DCMIPP_P0SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P0SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P0SR_VSYNCF_Msk              (0x1UL << DCMIPP_P0SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P0SR_VSYNCF                  DCMIPP_P0SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P0SR_LIMITF_Pos              (6U)
+#define DCMIPP_P0SR_LIMITF_Msk              (0x1UL << DCMIPP_P0SR_LIMITF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_P0SR_LIMITF                  DCMIPP_P0SR_LIMITF_Msk                          /*!< Limit raw interrupt status */
+#define DCMIPP_P0SR_OVRF_Pos                (7U)
+#define DCMIPP_P0SR_OVRF_Msk                (0x1UL << DCMIPP_P0SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P0SR_OVRF                    DCMIPP_P0SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P0SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P0SR_LSTLINE_Msk             (0x1UL << DCMIPP_P0SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P0SR_LSTLINE                 DCMIPP_P0SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P0SR_LSTFRM_Msk              (0x1UL << DCMIPP_P0SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P0SR_LSTFRM                  DCMIPP_P0SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_CPTACT_Pos              (23U)
+#define DCMIPP_P0SR_CPTACT_Msk              (0x1UL << DCMIPP_P0SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P0SR_CPTACT                  DCMIPP_P0SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P0FCR register  *****************/
+#define DCMIPP_P0FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P0FCR_CLINEF_Msk             (0x1UL << DCMIPP_P0FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0FCR_CLINEF                 DCMIPP_P0FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P0FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0FCR_CFRAMEF                DCMIPP_P0FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P0FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0FCR_CVSYNCF                DCMIPP_P0FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P0FCR_CLIMITF_Pos            (6U)
+#define DCMIPP_P0FCR_CLIMITF_Msk            (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0FCR_CLIMITF                DCMIPP_P0FCR_CLIMITF_Msk                        /*!< limit interrupt status clear */
+#define DCMIPP_P0FCR_COVRF_Pos              (7U)
+#define DCMIPP_P0FCR_COVRF_Msk              (0x1UL << DCMIPP_P0FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0FCR_COVRF                  DCMIPP_P0FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0CFSCR register  ****************/
+#define DCMIPP_P0CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P0CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P0CFSCR_DTIDA                DCMIPP_P0CFSCR_DTIDA_Msk                        /*!< Current Data type selection ID A */
+#define DCMIPP_P0CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P0CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P0CFSCR_DTIDB                DCMIPP_P0CFSCR_DTIDB_Msk                        /*!< Current Data type selection ID B */
+#define DCMIPP_P0CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P0CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P0CFSCR_DTMODE               DCMIPP_P0CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P0CFSCR_VC_Pos               (19U)
+#define DCMIPP_P0CFSCR_VC_Msk               (0x3UL << DCMIPP_P0CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P0CFSCR_VC                   DCMIPP_P0CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P0CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P0CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P0CFSCR_PIPEN                DCMIPP_P0CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P0CFCTCR register  ****************/
+#define DCMIPP_P0CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P0CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P0CFCTCR_FRATE               DCMIPP_P0CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P0CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P0CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P0CFCTCR_CPTMODE             DCMIPP_P0CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P0CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P0CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P0CFCTCR_CPTREQ              DCMIPP_P0CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P0CSCSTR register  ****************/
+#define DCMIPP_P0CSCSTR_HSTART_Pos          (0U)
+#define DCMIPP_P0CSCSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSTR_HSTART              DCMIPP_P0CSCSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0CSCSTR_VSTART_Pos          (16U)
+#define DCMIPP_P0CSCSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSTR_VSTART              DCMIPP_P0CSCSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P0CSCSZR register  ****************/
+#define DCMIPP_P0CSCSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P0CSCSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSZR_HSIZE               DCMIPP_P0CSCSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0CSCSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P0CSCSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSZR_VSIZE               DCMIPP_P0CSCSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0CSCSZR_POSNEG_Pos          (30U)
+#define DCMIPP_P0CSCSZR_POSNEG_Msk          (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos)            /*!< 0x40000000 */
+#define DCMIPP_P0CSCSZR_POSNEG              DCMIPP_P0CSCSZR_POSNEG_Msk                      /*!< Current value of the POSNEG bit */
+#define DCMIPP_P0CSCSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P0CSCSZR_ENABLE_Msk          (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0CSCSZR_ENABLE              DCMIPP_P0CSCSZR_ENABLE_Msk                      /*!< Current value of the ENABLE bit */
+
+/****************  Bit definition for DCMIPP_P0CPPCR register  ****************/
+#define DCMIPP_P0CPPCR_SWAPYUV_Pos          (0U)
+#define DCMIPP_P0CPPCR_SWAPYUV_Msk          (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P0CPPCR_SWAPYUV              DCMIPP_P0CPPCR_SWAPYUV_Msk                      /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0CPPCR_PAD_Pos              (5U)
+#define DCMIPP_P0CPPCR_PAD_Msk              (0x1UL << DCMIPP_P0CPPCR_PAD_Pos)                /*!< 0x00000020 */
+#define DCMIPP_P0CPPCR_PAD                  DCMIPP_P0CPPCR_PAD_Msk                          /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0CPPCR_HEADEREN_Pos         (6U)
+#define DCMIPP_P0CPPCR_HEADEREN_Msk         (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos)           /*!< 0x00000040 */
+#define DCMIPP_P0CPPCR_HEADEREN             DCMIPP_P0CPPCR_HEADEREN_Msk                     /*!< Current CSI header dump enable */
+#define DCMIPP_P0CPPCR_BSM_Pos              (7U)
+#define DCMIPP_P0CPPCR_BSM_Msk              (0x3UL << DCMIPP_P0CPPCR_BSM_Pos)                /*!< 0x00000180 */
+#define DCMIPP_P0CPPCR_BSM                  DCMIPP_P0CPPCR_BSM_Msk                          /*!< Current Byte select mode */
+#define DCMIPP_P0CPPCR_OEBS_Pos             (9U)
+#define DCMIPP_P0CPPCR_OEBS_Msk             (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos)               /*!< 0x00000200 */
+#define DCMIPP_P0CPPCR_OEBS                 DCMIPP_P0CPPCR_OEBS_Msk                         /*!< Current odd/even byte select (Byte select start) */
+#define DCMIPP_P0CPPCR_LSM_Pos              (10U)
+#define DCMIPP_P0CPPCR_LSM_Msk              (0x1UL << DCMIPP_P0CPPCR_LSM_Pos)                /*!< 0x00000400 */
+#define DCMIPP_P0CPPCR_LSM                  DCMIPP_P0CPPCR_LSM_Msk                          /*!< Current Line select mode */
+#define DCMIPP_P0CPPCR_OELS_Pos             (11U)
+#define DCMIPP_P0CPPCR_OELS_Msk             (0x1UL << DCMIPP_P0CPPCR_OELS_Pos)               /*!< 0x00000800 */
+#define DCMIPP_P0CPPCR_OELS                 DCMIPP_P0CPPCR_OELS_Msk                         /*!< Current odd/even line select (Line select start) */
+#define DCMIPP_P0CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P0CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P0CPPCR_LINEMULT             DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Current amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P0CPPCR_DBM_Msk              (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P0CPPCR_DBM                  DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Double buffer mode */
+
+/**************  Bit definition for DCMIPP_P0CPPM0AR1 register  ***************/
+#define DCMIPP_P0CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P0CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P0CPPM0AR1_M0A               DCMIPP_P0CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/****************  Bit definition for DCMIPP_P1FSCR register  *****************/
+#define DCMIPP_P1FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P1FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P1FSCR_DTIDA                 DCMIPP_P1FSCR_DTIDA_Msk                         /*!< Data type ID A */
+#define DCMIPP_P1FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P1FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P1FSCR_DTIDB                 DCMIPP_P1FSCR_DTIDB_Msk                         /*!< Data type ID B */
+#define DCMIPP_P1FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P1FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P1FSCR_DTMODE                DCMIPP_P1FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_PIPEDIFF_Pos          (18U)
+#define DCMIPP_P1FSCR_PIPEDIFF_Msk          (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_P1FSCR_PIPEDIFF              DCMIPP_P1FSCR_PIPEDIFF_Msk                      /*!< Differentiates Pipe2 vs */
+#define DCMIPP_P1FSCR_VC_Pos                (19U)
+#define DCMIPP_P1FSCR_VC_Msk                (0x3UL << DCMIPP_P1FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P1FSCR_VC                    DCMIPP_P1FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P1FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P1FSCR_FDTF                  DCMIPP_P1FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P1FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P1FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P1FSCR_FDTFEN                DCMIPP_P1FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P1FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P1FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P1FSCR_PIPEN                 DCMIPP_P1FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P1SRCR register  *****************/
+#define DCMIPP_P1SRCR_LASTLINE_Pos          (0U)
+#define DCMIPP_P1SRCR_LASTLINE_Msk          (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1SRCR_LASTLINE              DCMIPP_P1SRCR_LASTLINE_Msk                      /*!< Number of the last line to be kept when CROPEN = 1 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos      (12U)
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk      (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos)        /*!< 0x00007000 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL          DCMIPP_P1SRCR_FIRSTLINEDEL_Msk                  /*!< Number of lines to be deleted when CROPEN = 1 */
+#define DCMIPP_P1SRCR_CROPEN_Pos            (15U)
+#define DCMIPP_P1SRCR_CROPEN_Msk            (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos)              /*!< 0x00008000 */
+#define DCMIPP_P1SRCR_CROPEN                DCMIPP_P1SRCR_CROPEN_Msk                        /*!< Crop line enable */
+
+/****************  Bit definition for DCMIPP_P1BPRCR register  ****************/
+#define DCMIPP_P1BPRCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BPRCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BPRCR_ENABLE               DCMIPP_P1BPRCR_ENABLE_Msk                       /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */
+#define DCMIPP_P1BPRCR_STRENGTH_Pos         (1U)
+#define DCMIPP_P1BPRCR_STRENGTH_Msk         (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos)           /*!< 0x0000000E */
+#define DCMIPP_P1BPRCR_STRENGTH             DCMIPP_P1BPRCR_STRENGTH_Msk                     /*!< Strength (aggressivity) of the bad pixel detection: */
+
+/****************  Bit definition for DCMIPP_P1BPRSR register  ****************/
+#define DCMIPP_P1BPRSR_BADCNT_Pos           (0U)
+#define DCMIPP_P1BPRSR_BADCNT_Msk           (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1BPRSR_BADCNT               DCMIPP_P1BPRSR_BADCNT_Msk                       /*!< Amount of detected bad pixels */
+
+/****************  Bit definition for DCMIPP_P1DECR register  *****************/
+#define DCMIPP_P1DECR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DECR_ENABLE_Msk            (0x1UL << DCMIPP_P1DECR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DECR_ENABLE                DCMIPP_P1DECR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DECR_HDEC_Pos              (1U)
+#define DCMIPP_P1DECR_HDEC_Msk              (0x3UL << DCMIPP_P1DECR_HDEC_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DECR_HDEC                  DCMIPP_P1DECR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DECR_VDEC_Pos              (3U)
+#define DCMIPP_P1DECR_VDEC_Msk              (0x3UL << DCMIPP_P1DECR_VDEC_Pos)                /*!< 0x00000018 */
+#define DCMIPP_P1DECR_VDEC                  DCMIPP_P1DECR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1BLCCR register  ****************/
+#define DCMIPP_P1BLCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BLCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BLCCR_ENABLE               DCMIPP_P1BLCCR_ENABLE_Msk                       /*!< Black level calibration */
+#define DCMIPP_P1BLCCR_BLCB_Pos             (8U)
+#define DCMIPP_P1BLCCR_BLCB_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos)              /*!< 0x0000FF00 */
+#define DCMIPP_P1BLCCR_BLCB                 DCMIPP_P1BLCCR_BLCB_Msk                         /*!< Black level calibration - Blue */
+#define DCMIPP_P1BLCCR_BLCG_Pos             (16U)
+#define DCMIPP_P1BLCCR_BLCG_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos)              /*!< 0x00FF0000 */
+#define DCMIPP_P1BLCCR_BLCG                 DCMIPP_P1BLCCR_BLCG_Msk                         /*!< Black level calibration - Green */
+#define DCMIPP_P1BLCCR_BLCR_Pos             (24U)
+#define DCMIPP_P1BLCCR_BLCR_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos)              /*!< 0xFF000000 */
+#define DCMIPP_P1BLCCR_BLCR                 DCMIPP_P1BLCCR_BLCR_Msk                         /*!< Black level calibration - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR1 register  ****************/
+#define DCMIPP_P1EXCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1EXCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1EXCR1_ENABLE               DCMIPP_P1EXCR1_ENABLE_Msk                       /*!< Exposure control (multiplication and shift) of all red, green and blue */
+#define DCMIPP_P1EXCR1_MULTR_Pos            (20U)
+#define DCMIPP_P1EXCR1_MULTR_Msk            (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR1_MULTR                DCMIPP_P1EXCR1_MULTR_Msk                        /*!< Exposure multiplier - Red */
+#define DCMIPP_P1EXCR1_SHFR_Pos             (28U)
+#define DCMIPP_P1EXCR1_SHFR_Msk             (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR1_SHFR                 DCMIPP_P1EXCR1_SHFR_Msk                         /*!< Exposure shift - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR2 register  ****************/
+#define DCMIPP_P1EXCR2_MULTB_Pos            (4U)
+#define DCMIPP_P1EXCR2_MULTB_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos)             /*!< 0x00000FF0 */
+#define DCMIPP_P1EXCR2_MULTB                DCMIPP_P1EXCR2_MULTB_Msk                        /*!< Exposure multiplier - Blue */
+#define DCMIPP_P1EXCR2_SHFB_Pos             (12U)
+#define DCMIPP_P1EXCR2_SHFB_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos)               /*!< 0x00007000 */
+#define DCMIPP_P1EXCR2_SHFB                 DCMIPP_P1EXCR2_SHFB_Msk                         /*!< Exposure shift - Blue */
+#define DCMIPP_P1EXCR2_MULTG_Pos            (20U)
+#define DCMIPP_P1EXCR2_MULTG_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR2_MULTG                DCMIPP_P1EXCR2_MULTG_Msk                        /*!< Exposure multiplier - Green */
+#define DCMIPP_P1EXCR2_SHFG_Pos             (28U)
+#define DCMIPP_P1EXCR2_SHFG_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR2_SHFG                 DCMIPP_P1EXCR2_SHFG_Msk                         /*!< Exposure shift - Green */
+
+/****************  Bit definition for DCMIPP_P1ST1CR register  ****************/
+#define DCMIPP_P1ST1CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST1CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST1CR_ENABLE               DCMIPP_P1ST1CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST1CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST1CR_BINS_Msk             (0x3UL << DCMIPP_P1ST1CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST1CR_BINS                 DCMIPP_P1ST1CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST1CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST1CR_SRC_Msk              (0x7UL << DCMIPP_P1ST1CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST1CR_SRC                  DCMIPP_P1ST1CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST1CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST1CR_MODE_Msk             (0x1UL << DCMIPP_P1ST1CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST1CR_MODE                 DCMIPP_P1ST1CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST2CR register  ****************/
+#define DCMIPP_P1ST2CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST2CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST2CR_ENABLE               DCMIPP_P1ST2CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST2CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST2CR_BINS_Msk             (0x3UL << DCMIPP_P1ST2CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST2CR_BINS                 DCMIPP_P1ST2CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST2CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST2CR_SRC_Msk              (0x7UL << DCMIPP_P1ST2CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST2CR_SRC                  DCMIPP_P1ST2CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST2CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST2CR_MODE_Msk             (0x1UL << DCMIPP_P1ST2CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST2CR_MODE                 DCMIPP_P1ST2CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST3CR register  ****************/
+#define DCMIPP_P1ST3CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST3CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST3CR_ENABLE               DCMIPP_P1ST3CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST3CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST3CR_BINS_Msk             (0x3UL << DCMIPP_P1ST3CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST3CR_BINS                 DCMIPP_P1ST3CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST3CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST3CR_SRC_Msk              (0x7UL << DCMIPP_P1ST3CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST3CR_SRC                  DCMIPP_P1ST3CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST3CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST3CR_MODE_Msk             (0x1UL << DCMIPP_P1ST3CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST3CR_MODE                 DCMIPP_P1ST3CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1STSTR register  ****************/
+#define DCMIPP_P1STSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1STSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1STSTR_HSTART               DCMIPP_P1STSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1STSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSTR_VSTART               DCMIPP_P1STSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1STSZR register  ****************/
+#define DCMIPP_P1STSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1STSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1STSZR_HSIZE                DCMIPP_P1STSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1STSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSZR_VSIZE                DCMIPP_P1STSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1STSZR_CROPEN_Pos           (31U)
+#define DCMIPP_P1STSZR_CROPEN_Msk           (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1STSZR_CROPEN               DCMIPP_P1STSZR_CROPEN_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1ST1SR register  ****************/
+#define DCMIPP_P1ST1SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST1SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST1SR_ACCU                 DCMIPP_P1ST1SR_ACCU_Msk                         /*!< Accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST2SR register  ****************/
+#define DCMIPP_P1ST2SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST2SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST2SR_ACCU                 DCMIPP_P1ST2SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST3SR register  ****************/
+#define DCMIPP_P1ST3SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST3SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST3SR_ACCU                 DCMIPP_P1ST3SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1DMCR register  *****************/
+#define DCMIPP_P1DMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DMCR_ENABLE                DCMIPP_P1DMCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DMCR_TYPE_Pos              (1U)
+#define DCMIPP_P1DMCR_TYPE_Msk              (0x3UL << DCMIPP_P1DMCR_TYPE_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DMCR_TYPE                  DCMIPP_P1DMCR_TYPE_Msk                          /*!< Raw Bayer type */
+#define DCMIPP_P1DMCR_PEAK_Pos              (16U)
+#define DCMIPP_P1DMCR_PEAK_Msk              (0x7UL << DCMIPP_P1DMCR_PEAK_Pos)                /*!< 0x00070000 */
+#define DCMIPP_P1DMCR_PEAK                  DCMIPP_P1DMCR_PEAK_Msk                          /*!< Strength of the peak detection */
+#define DCMIPP_P1DMCR_LINEV_Pos             (20U)
+#define DCMIPP_P1DMCR_LINEV_Msk             (0x7UL << DCMIPP_P1DMCR_LINEV_Pos)               /*!< 0x00700000 */
+#define DCMIPP_P1DMCR_LINEV                 DCMIPP_P1DMCR_LINEV_Msk                         /*!< Strength of the vertical line detection */
+#define DCMIPP_P1DMCR_LINEH_Pos             (24U)
+#define DCMIPP_P1DMCR_LINEH_Msk             (0x7UL << DCMIPP_P1DMCR_LINEH_Pos)               /*!< 0x07000000 */
+#define DCMIPP_P1DMCR_LINEH                 DCMIPP_P1DMCR_LINEH_Msk                         /*!< Strength of the horizontal line detection */
+#define DCMIPP_P1DMCR_EDGE_Pos              (28U)
+#define DCMIPP_P1DMCR_EDGE_Msk              (0x7UL << DCMIPP_P1DMCR_EDGE_Pos)                /*!< 0x70000000 */
+#define DCMIPP_P1DMCR_EDGE                  DCMIPP_P1DMCR_EDGE_Msk                          /*!< Strength of the edge detection */
+
+/****************  Bit definition for DCMIPP_P1CCCR register  *****************/
+#define DCMIPP_P1CCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1CCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1CCCR_ENABLE                DCMIPP_P1CCCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1CCCR_TYPE_Pos              (1U)
+#define DCMIPP_P1CCCR_TYPE_Msk              (0x1UL << DCMIPP_P1CCCR_TYPE_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1CCCR_TYPE                  DCMIPP_P1CCCR_TYPE_Msk                          /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCR_CLAMP_Pos             (2U)
+#define DCMIPP_P1CCCR_CLAMP_Msk             (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos)               /*!< 0x00000004 */
+#define DCMIPP_P1CCCR_CLAMP                 DCMIPP_P1CCCR_CLAMP_Msk                         /*!< Clamp the output samples */
+
+/****************  Bit definition for DCMIPP_P1CCRR1 register  ****************/
+#define DCMIPP_P1CCRR1_RR_Pos               (0U)
+#define DCMIPP_P1CCRR1_RR_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR1_RR                   DCMIPP_P1CCRR1_RR_Msk                           /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCRR1_RG_Pos               (16U)
+#define DCMIPP_P1CCRR1_RG_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCRR1_RG                   DCMIPP_P1CCRR1_RG_Msk                           /*!< Coefficient row 1 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCRR2 register  ****************/
+#define DCMIPP_P1CCRR2_RB_Pos               (0U)
+#define DCMIPP_P1CCRR2_RB_Msk               (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR2_RB                   DCMIPP_P1CCRR2_RB_Msk                           /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCRR2_RA_Pos               (16U)
+#define DCMIPP_P1CCRR2_RA_Msk               (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCRR2_RA                   DCMIPP_P1CCRR2_RA_Msk                           /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCGR1 register  ****************/
+#define DCMIPP_P1CCGR1_GR_Pos               (0U)
+#define DCMIPP_P1CCGR1_GR_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR1_GR                   DCMIPP_P1CCGR1_GR_Msk                           /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCGR1_GG_Pos               (16U)
+#define DCMIPP_P1CCGR1_GG_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCGR1_GG                   DCMIPP_P1CCGR1_GG_Msk                           /*!< Coefficient row 2 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCGR2 register  ****************/
+#define DCMIPP_P1CCGR2_GB_Pos               (0U)
+#define DCMIPP_P1CCGR2_GB_Msk               (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR2_GB                   DCMIPP_P1CCGR2_GB_Msk                           /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCGR2_GA_Pos               (16U)
+#define DCMIPP_P1CCGR2_GA_Msk               (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCGR2_GA                   DCMIPP_P1CCGR2_GA_Msk                           /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCBR1 register  ****************/
+#define DCMIPP_P1CCBR1_BR_Pos               (0U)
+#define DCMIPP_P1CCBR1_BR_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR1_BR                   DCMIPP_P1CCBR1_BR_Msk                           /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCBR1_BG_Pos               (16U)
+#define DCMIPP_P1CCBR1_BG_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCBR1_BG                   DCMIPP_P1CCBR1_BG_Msk                           /*!< Coefficient row 3 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCBR2 register  ****************/
+#define DCMIPP_P1CCBR2_BB_Pos               (0U)
+#define DCMIPP_P1CCBR2_BB_Msk               (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR2_BB                   DCMIPP_P1CCBR2_BB_Msk                           /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCBR2_BA_Pos               (16U)
+#define DCMIPP_P1CCBR2_BA_Msk               (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCBR2_BA                   DCMIPP_P1CCBR2_BA_Msk                           /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CTCR1 register  ****************/
+#define DCMIPP_P1CTCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1CTCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CTCR1_ENABLE               DCMIPP_P1CTCR1_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1CTCR1_LUM0_Pos             (9U)
+#define DCMIPP_P1CTCR1_LUM0_Msk             (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR1_LUM0                 DCMIPP_P1CTCR1_LUM0_Msk                         /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR2 register  ****************/
+#define DCMIPP_P1CTCR2_LUM4_Pos             (1U)
+#define DCMIPP_P1CTCR2_LUM4_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR2_LUM4                 DCMIPP_P1CTCR2_LUM4_Msk                         /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM3_Pos             (9U)
+#define DCMIPP_P1CTCR2_LUM3_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR2_LUM3                 DCMIPP_P1CTCR2_LUM3_Msk                         /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM2_Pos             (17U)
+#define DCMIPP_P1CTCR2_LUM2_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR2_LUM2                 DCMIPP_P1CTCR2_LUM2_Msk                         /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM1_Pos             (25U)
+#define DCMIPP_P1CTCR2_LUM1_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR2_LUM1                 DCMIPP_P1CTCR2_LUM1_Msk                         /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR3 register  ****************/
+#define DCMIPP_P1CTCR3_LUM8_Pos             (1U)
+#define DCMIPP_P1CTCR3_LUM8_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR3_LUM8                 DCMIPP_P1CTCR3_LUM8_Msk                         /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM7_Pos             (9U)
+#define DCMIPP_P1CTCR3_LUM7_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR3_LUM7                 DCMIPP_P1CTCR3_LUM7_Msk                         /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM6_Pos             (17U)
+#define DCMIPP_P1CTCR3_LUM6_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR3_LUM6                 DCMIPP_P1CTCR3_LUM6_Msk                         /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM5_Pos             (25U)
+#define DCMIPP_P1CTCR3_LUM5_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR3_LUM5                 DCMIPP_P1CTCR3_LUM5_Msk                         /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1FCTCR register  ****************/
+#define DCMIPP_P1FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P1FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P1FCTCR_FRATE                DCMIPP_P1FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P1FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P1FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P1FCTCR_CPTMODE              DCMIPP_P1FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P1FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P1FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P1FCTCR_CPTREQ               DCMIPP_P1FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P1CRSTR register  ****************/
+#define DCMIPP_P1CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CRSTR_HSTART               DCMIPP_P1CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSTR_VSTART               DCMIPP_P1CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CRSZR register  ****************/
+#define DCMIPP_P1CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1CRSZR_HSIZE                DCMIPP_P1CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSZR_VSIZE                DCMIPP_P1CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CRSZR_ENABLE               DCMIPP_P1CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1DCCR register  *****************/
+#define DCMIPP_P1DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1DCCR_ENABLE                DCMIPP_P1DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P1DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P1DCCR_HDEC_Msk              (0x3UL << DCMIPP_P1DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1DCCR_HDEC                  DCMIPP_P1DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P1DCCR_VDEC_Msk              (0x3UL << DCMIPP_P1DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1DCCR_VDEC                  DCMIPP_P1DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1DSCR register  *****************/
+#define DCMIPP_P1DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P1DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P1DSCR_HDIV                  DCMIPP_P1DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P1DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1DSCR_VDIV                  DCMIPP_P1DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P1DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1DSCR_ENABLE                DCMIPP_P1DSCR_ENABLE_Msk                        /*!<  Downscaler Enable */
+
+/***************  Bit definition for DCMIPP_P1DSRTIOR register  ***************/
+#define DCMIPP_P1DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P1DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P1DSRTIOR_HRATIO             DCMIPP_P1DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P1DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P1DSRTIOR_VRATIO             DCMIPP_P1DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P1DSSZR register  ****************/
+#define DCMIPP_P1DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1DSSZR_HSIZE                DCMIPP_P1DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1DSSZR_VSIZE                DCMIPP_P1DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CMRICR register  ***************/
+#define DCMIPP_P1CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P1CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P1CMRICR_ROILSZ              DCMIPP_P1CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P1CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P1CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P1CMRICR_ROI1EN              DCMIPP_P1CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P1CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P1CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P1CMRICR_ROI2EN              DCMIPP_P1CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P1CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P1CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CMRICR_ROI3EN              DCMIPP_P1CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P1CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P1CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P1CMRICR_ROI4EN              DCMIPP_P1CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P1CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P1CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P1CMRICR_ROI5EN              DCMIPP_P1CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P1CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P1CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P1CMRICR_ROI6EN              DCMIPP_P1CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P1CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P1CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P1CMRICR_ROI7EN              DCMIPP_P1CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P1CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P1CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P1CMRICR_ROI8EN              DCMIPP_P1CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P1RIxCR1 register  ***************/
+#define DCMIPP_P1RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P1RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P1RIxCR1_HSTART              DCMIPP_P1RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P1RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P1RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P1RIxCR1_CLB                 DCMIPP_P1RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P1RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P1RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P1RIxCR1_CLG                 DCMIPP_P1RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P1RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P1RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P1RIxCR1_VSTART              DCMIPP_P1RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P1RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P1RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P1RIxCR1_CLR                 DCMIPP_P1RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P1RIxCR2 register  ***************/
+#define DCMIPP_P1RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P1RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P1RIxCR2_VSIZE               DCMIPP_P1RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P1RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P1RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P1RIxCR2_HSIZE               DCMIPP_P1RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P1GMCR register  *****************/
+#define DCMIPP_P1GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos)              /*!< 0x00000001   */
+#define DCMIPP_P1GMCR_ENABLE                DCMIPP_P1GMCR_ENABLE_Msk                        /*!<  Gamma  enable*/
+
+/****************  Bit definition for DCMIPP_P1YUVCR register  ****************/
+#define DCMIPP_P1YUVCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1YUVCR_ENABLE_Msk           (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1YUVCR_ENABLE               DCMIPP_P1YUVCR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1YUVCR_TYPE_Pos             (1U)
+#define DCMIPP_P1YUVCR_TYPE_Msk             (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1YUVCR_TYPE                 DCMIPP_P1YUVCR_TYPE_Msk                         /*!< Output samples type used while CLAMP is activated */
+#define DCMIPP_P1YUVCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1YUVCR_CLAMP_Msk            (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1YUVCR_CLAMP                DCMIPP_P1YUVCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1YUVRR1 register  ****************/
+#define DCMIPP_P1YUVRR1_RR_Pos              (0U)
+#define DCMIPP_P1YUVRR1_RR_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR1_RR                  DCMIPP_P1YUVRR1_RR_Msk                          /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1YUVRR1_RG_Pos              (16U)
+#define DCMIPP_P1YUVRR1_RG_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVRR1_RG                  DCMIPP_P1YUVRR1_RG_Msk                          /*!< Coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVRR2 register  ****************/
+#define DCMIPP_P1YUVRR2_RB_Pos              (0U)
+#define DCMIPP_P1YUVRR2_RB_Msk              (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR2_RB                  DCMIPP_P1YUVRR2_RB_Msk                          /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1YUVRR2_RA_Pos              (16U)
+#define DCMIPP_P1YUVRR2_RA_Msk              (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVRR2_RA                  DCMIPP_P1YUVRR2_RA_Msk                          /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVGR1 register  ****************/
+#define DCMIPP_P1YUVGR1_GR_Pos              (0U)
+#define DCMIPP_P1YUVGR1_GR_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR1_GR                  DCMIPP_P1YUVGR1_GR_Msk                          /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1YUVGR1_GG_Pos              (16U)
+#define DCMIPP_P1YUVGR1_GG_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVGR1_GG                  DCMIPP_P1YUVGR1_GG_Msk                          /*!< Coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVGR2 register  ****************/
+#define DCMIPP_P1YUVGR2_GB_Pos              (0U)
+#define DCMIPP_P1YUVGR2_GB_Msk              (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR2_GB                  DCMIPP_P1YUVGR2_GB_Msk                          /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1YUVGR2_GA_Pos              (16U)
+#define DCMIPP_P1YUVGR2_GA_Msk              (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVGR2_GA                  DCMIPP_P1YUVGR2_GA_Msk                          /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVBR1 register  ****************/
+#define DCMIPP_P1YUVBR1_BR_Pos              (0U)
+#define DCMIPP_P1YUVBR1_BR_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR1_BR                  DCMIPP_P1YUVBR1_BR_Msk                          /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1YUVBR1_BG_Pos              (16U)
+#define DCMIPP_P1YUVBR1_BG_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVBR1_BG                  DCMIPP_P1YUVBR1_BG_Msk                          /*!< Coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVBR2 register  ****************/
+#define DCMIPP_P1YUVBR2_BB_Pos              (0U)
+#define DCMIPP_P1YUVBR2_BB_Msk              (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR2_BB                  DCMIPP_P1YUVBR2_BB_Msk                          /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1YUVBR2_BA_Pos              (16U)
+#define DCMIPP_P1YUVBR2_BA_Msk              (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVBR2_BA                  DCMIPP_P1YUVBR2_BA_Msk                          /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1PPCR register  *****************/
+#define DCMIPP_P1PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P1PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P1PPCR_FORMAT                DCMIPP_P1PPCR_FORMAT_Msk                        /*!< Memory format */
+#define DCMIPP_P1PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P1PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P1PPCR_SWAPRB                DCMIPP_P1PPCR_SWAPRB_Msk                        /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P1PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P1PPCR_LINEMULT              DCMIPP_P1PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P1PPCR_DBM_Pos               (16U)
+#define DCMIPP_P1PPCR_DBM_Msk               (0x1UL << DCMIPP_P1PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P1PPCR_DBM                   DCMIPP_P1PPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P1PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P1PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos)                /*!< 0x000E0000 */
+#define DCMIPP_P1PPCR_LMAWM                 DCMIPP_P1PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P1PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P1PPCR_LMAWE_Msk             (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos)                /*!< 0x00100000 */
+#define DCMIPP_P1PPCR_LMAWE                 DCMIPP_P1PPCR_LMAWE_Msk                           /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P1PPM0AR1 register  ***************/
+#define DCMIPP_P1PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR1_M0A                DCMIPP_P1PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM0AR2 register  ***************/
+#define DCMIPP_P1PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR2_M0A                DCMIPP_P1PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1PPM0PR register  ****************/
+#define DCMIPP_P1PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM0PR_PITCH               DCMIPP_P1PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR1 register  ***************/
+#define DCMIPP_P1PPM1AR1_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR1_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR1_M1A                DCMIPP_P1PPM1AR1_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR2 register  ***************/
+#define DCMIPP_P1PPM1AR2_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR2_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR2_M1A                DCMIPP_P1PPM1AR2_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1PR register  ****************/
+#define DCMIPP_P1PPM1PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM1PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM1PR_PITCH               DCMIPP_P1PPM1PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1STM1AR register  ****************/
+#define DCMIPP_P1STM1AR_M1A_Pos             (0U)
+#define DCMIPP_P1STM1AR_M1A_Msk             (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM1AR_M1A                 DCMIPP_P1STM1AR_M1A_Msk                         /*!< status Memory1 address register */
+
+/***************  Bit definition for DCMIPP_P1PPM2AR1 register  ***************/
+#define DCMIPP_P1PPM2AR1_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR1_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR1_M2A                DCMIPP_P1PPM2AR1_M2A_Msk                        /*!< Memory2 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM2AR2 register  ***************/
+#define DCMIPP_P1PPM2AR2_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR2_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR2_M2A                DCMIPP_P1PPM2AR2_M2A_Msk                        /*!< Memory2 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1STM2AR register  ****************/
+#define DCMIPP_P1STM2AR_M2A_Pos             (0U)
+#define DCMIPP_P1STM2AR_M2A_Msk             (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM2AR_M2A                 DCMIPP_P1STM2AR_M2A_Msk                         /*!< status Memory2 address register */
+
+/*****************  Bit definition for DCMIPP_P1IER register  *****************/
+#define DCMIPP_P1IER_LINEIE_Pos             (0U)
+#define DCMIPP_P1IER_LINEIE_Msk             (0x1UL << DCMIPP_P1IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1IER_LINEIE                 DCMIPP_P1IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P1IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P1IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1IER_FRAMEIE                DCMIPP_P1IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P1IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P1IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1IER_VSYNCIE                DCMIPP_P1IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P1IER_OVRIE_Pos              (7U)
+#define DCMIPP_P1IER_OVRIE_Msk              (0x1UL << DCMIPP_P1IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1IER_OVRIE                  DCMIPP_P1IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P1SR register  ******************/
+#define DCMIPP_P1SR_LINEF_Pos               (0U)
+#define DCMIPP_P1SR_LINEF_Msk               (0x1UL << DCMIPP_P1SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P1SR_LINEF                   DCMIPP_P1SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P1SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P1SR_FRAMEF_Msk              (0x1UL << DCMIPP_P1SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1SR_FRAMEF                  DCMIPP_P1SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P1SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P1SR_VSYNCF_Msk              (0x1UL << DCMIPP_P1SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P1SR_VSYNCF                  DCMIPP_P1SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P1SR_OVRF_Pos                (7U)
+#define DCMIPP_P1SR_OVRF_Msk                (0x1UL << DCMIPP_P1SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P1SR_OVRF                    DCMIPP_P1SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P1SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P1SR_LSTLINE_Msk             (0x1UL << DCMIPP_P1SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P1SR_LSTLINE                 DCMIPP_P1SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P1SR_LSTFRM_Msk              (0x1UL << DCMIPP_P1SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P1SR_LSTFRM                  DCMIPP_P1SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_CPTACT_Pos              (23U)
+#define DCMIPP_P1SR_CPTACT_Msk              (0x1UL << DCMIPP_P1SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P1SR_CPTACT                  DCMIPP_P1SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P1FCR register  *****************/
+#define DCMIPP_P1FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P1FCR_CLINEF_Msk             (0x1UL << DCMIPP_P1FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1FCR_CLINEF                 DCMIPP_P1FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P1FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1FCR_CFRAMEF                DCMIPP_P1FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P1FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1FCR_CVSYNCF                DCMIPP_P1FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P1FCR_COVRF_Pos              (7U)
+#define DCMIPP_P1FCR_COVRF_Msk              (0x1UL << DCMIPP_P1FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1FCR_COVRF                  DCMIPP_P1FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P1CFSCR register  ****************/
+#define DCMIPP_P1CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P1CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P1CFSCR_DTIDA                DCMIPP_P1CFSCR_DTIDA_Msk                        /*!< Current Data type ID A */
+#define DCMIPP_P1CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P1CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P1CFSCR_DTIDB                DCMIPP_P1CFSCR_DTIDB_Msk                        /*!< Current Data type ID B */
+#define DCMIPP_P1CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P1CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P1CFSCR_DTMODE               DCMIPP_P1CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P1CFSCR_PIPEDIFF_Pos         (18U)
+#define DCMIPP_P1CFSCR_PIPEDIFF_Msk         (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CFSCR_PIPEDIFF             DCMIPP_P1CFSCR_PIPEDIFF_Msk                     /*!< Current differentiates Pipe2 vs */
+#define DCMIPP_P1CFSCR_VC_Pos               (19U)
+#define DCMIPP_P1CFSCR_VC_Msk               (0x3UL << DCMIPP_P1CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P1CFSCR_VC                   DCMIPP_P1CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P1CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P1CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P1CFSCR_FDTF                 DCMIPP_P1CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P1CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P1CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P1CFSCR_FDTFEN               DCMIPP_P1CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P1CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P1CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1CFSCR_PIPEN                DCMIPP_P1CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P1CBPRCR register  ****************/
+#define DCMIPP_P1CBPRCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBPRCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBPRCR_ENABLE              DCMIPP_P1CBPRCR_ENABLE_Msk                      /*!< Current status of enable bit */
+#define DCMIPP_P1CBPRCR_STRENGTH_Pos        (1U)
+#define DCMIPP_P1CBPRCR_STRENGTH_Msk        (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos)          /*!< 0x0000000E */
+#define DCMIPP_P1CBPRCR_STRENGTH            DCMIPP_P1CBPRCR_STRENGTH_Msk                    /*!< Current strength (aggressivity) of the bad pixel detection: */
+
+/***************  Bit definition for DCMIPP_P1CBLCCR register  ****************/
+#define DCMIPP_P1CBLCCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBLCCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBLCCR_ENABLE              DCMIPP_P1CBLCCR_ENABLE_Msk                      /*!< For current black level calibration */
+#define DCMIPP_P1CBLCCR_BLCB_Pos            (8U)
+#define DCMIPP_P1CBLCCR_BLCB_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos)             /*!< 0x0000FF00 */
+#define DCMIPP_P1CBLCCR_BLCB                DCMIPP_P1CBLCCR_BLCB_Msk                        /*!< Current black level calibration - Blue */
+#define DCMIPP_P1CBLCCR_BLCG_Pos            (16U)
+#define DCMIPP_P1CBLCCR_BLCG_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos)             /*!< 0x00FF0000 */
+#define DCMIPP_P1CBLCCR_BLCG                DCMIPP_P1CBLCCR_BLCG_Msk                        /*!< Current black level calibration - Green */
+#define DCMIPP_P1CBLCCR_BLCR_Pos            (24U)
+#define DCMIPP_P1CBLCCR_BLCR_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos)             /*!< 0xFF000000 */
+#define DCMIPP_P1CBLCCR_BLCR                DCMIPP_P1CBLCCR_BLCR_Msk                        /*!< Current black level calibration - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR1 register  ****************/
+#define DCMIPP_P1CEXCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CEXCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CEXCR1_ENABLE              DCMIPP_P1CEXCR1_ENABLE_Msk                      /*!< for exposure control (multiplication and shift) */
+#define DCMIPP_P1CEXCR1_MULTR_Pos           (20U)
+#define DCMIPP_P1CEXCR1_MULTR_Msk           (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR1_MULTR               DCMIPP_P1CEXCR1_MULTR_Msk                       /*!< Current exposure multiplier - Red */
+#define DCMIPP_P1CEXCR1_SHFR_Pos            (28U)
+#define DCMIPP_P1CEXCR1_SHFR_Msk            (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR1_SHFR                DCMIPP_P1CEXCR1_SHFR_Msk                        /*!< Current exposure shift - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR2 register  ****************/
+#define DCMIPP_P1CEXCR2_MULTB_Pos           (4U)
+#define DCMIPP_P1CEXCR2_MULTB_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos)            /*!< 0x00000FF0 */
+#define DCMIPP_P1CEXCR2_MULTB               DCMIPP_P1CEXCR2_MULTB_Msk                       /*!< Current exposure multiplier - Blue */
+#define DCMIPP_P1CEXCR2_SHFB_Pos            (12U)
+#define DCMIPP_P1CEXCR2_SHFB_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos)              /*!< 0x00007000 */
+#define DCMIPP_P1CEXCR2_SHFB                DCMIPP_P1CEXCR2_SHFB_Msk                        /*!< Current exposure shift - Blue */
+#define DCMIPP_P1CEXCR2_MULTG_Pos           (20U)
+#define DCMIPP_P1CEXCR2_MULTG_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR2_MULTG               DCMIPP_P1CEXCR2_MULTG_Msk                       /*!< Current exposure multiplier - Green */
+#define DCMIPP_P1CEXCR2_SHFG_Pos            (28U)
+#define DCMIPP_P1CEXCR2_SHFG_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR2_SHFG                DCMIPP_P1CEXCR2_SHFG_Msk                        /*!< Current exposure shift - Green */
+
+/***************  Bit definition for DCMIPP_P1CST1CR register  ****************/
+#define DCMIPP_P1CST1CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST1CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST1CR_ENABLE              DCMIPP_P1CST1CR_ENABLE_Msk                      /*!< Current enable bit value */
+#define DCMIPP_P1CST1CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST1CR_BINS_Msk            (0x3UL << DCMIPP_P1CST1CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST1CR_BINS                DCMIPP_P1CST1CR_BINS_Msk                        /*!< Current bin definition */
+#define DCMIPP_P1CST1CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST1CR_SRC_Msk             (0x7UL << DCMIPP_P1CST1CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST1CR_SRC                 DCMIPP_P1CST1CR_SRC_Msk                         /*!< Current source of statistics */
+#define DCMIPP_P1CST1CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST1CR_MODE_Msk            (0x1UL << DCMIPP_P1CST1CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST1CR_MODE                DCMIPP_P1CST1CR_MODE_Msk                        /*!< Current statistics mode */
+#define DCMIPP_P1CST1CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST1CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST1CR_ACCU                DCMIPP_P1CST1CR_ACCU_Msk                        /*!< Current accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST2CR register  ****************/
+#define DCMIPP_P1CST2CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST2CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST2CR_ENABLE              DCMIPP_P1CST2CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST2CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST2CR_BINS_Msk            (0x3UL << DCMIPP_P1CST2CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST2CR_BINS                DCMIPP_P1CST2CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST2CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST2CR_SRC_Msk             (0x7UL << DCMIPP_P1CST2CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST2CR_SRC                 DCMIPP_P1CST2CR_SRC_Msk                         /*!< source of stat */
+#define DCMIPP_P1CST2CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST2CR_MODE_Msk            (0x1UL << DCMIPP_P1CST2CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST2CR_MODE                DCMIPP_P1CST2CR_MODE_Msk                        /*!< statistics mode */
+#define DCMIPP_P1CST2CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST2CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST2CR_ACCU                DCMIPP_P1CST2CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST3CR register  ****************/
+#define DCMIPP_P1CST3CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST3CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST3CR_ENABLE              DCMIPP_P1CST3CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST3CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST3CR_BINS_Msk            (0x3UL << DCMIPP_P1CST3CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST3CR_BINS                DCMIPP_P1CST3CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST3CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST3CR_SRC_Msk             (0x7UL << DCMIPP_P1CST3CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST3CR_SRC                 DCMIPP_P1CST3CR_SRC_Msk                         /*!< Statistics source */
+#define DCMIPP_P1CST3CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST3CR_MODE_Msk            (0x1UL << DCMIPP_P1CST3CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST3CR_MODE                DCMIPP_P1CST3CR_MODE_Msk                        /*!< Statistics mode */
+#define DCMIPP_P1CST3CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST3CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST3CR_ACCU                DCMIPP_P1CST3CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CSTSTR register  ****************/
+#define DCMIPP_P1CSTSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CSTSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSTR_HSTART              DCMIPP_P1CSTSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CSTSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSTR_VSTART              DCMIPP_P1CSTSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CSTSZR register  ****************/
+#define DCMIPP_P1CSTSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CSTSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSZR_HSIZE               DCMIPP_P1CSTSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CSTSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSZR_VSIZE               DCMIPP_P1CSTSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CSTSZR_CROPEN_Pos          (31U)
+#define DCMIPP_P1CSTSZR_CROPEN_Msk          (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CSTSZR_CROPEN              DCMIPP_P1CSTSZR_CROPEN_Msk                      /*!< Current CROPEN bit value */
+
+/****************  Bit definition for DCMIPP_P1CCCCR register  ****************/
+#define DCMIPP_P1CCCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CCCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CCCCR_ENABLE               DCMIPP_P1CCCCR_ENABLE_Msk                       /*!< This bit indicates the current value applied */
+#define DCMIPP_P1CCCCR_TYPE_Pos             (1U)
+#define DCMIPP_P1CCCCR_TYPE_Msk             (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1CCCCR_TYPE                 DCMIPP_P1CCCCR_TYPE_Msk                         /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1CCCCR_CLAMP_Msk            (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1CCCCR_CLAMP                DCMIPP_P1CCCCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1CCCRR1 register  ****************/
+#define DCMIPP_P1CCCRR1_RR_Pos              (0U)
+#define DCMIPP_P1CCCRR1_RR_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR1_RR                  DCMIPP_P1CCCRR1_RR_Msk                          /*!< Current coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCCRR1_RG_Pos              (16U)
+#define DCMIPP_P1CCCRR1_RG_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCRR1_RG                  DCMIPP_P1CCCRR1_RG_Msk                          /*!< Current coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCRR2 register  ****************/
+#define DCMIPP_P1CCCRR2_RB_Pos              (0U)
+#define DCMIPP_P1CCCRR2_RB_Msk              (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR2_RB                  DCMIPP_P1CCCRR2_RB_Msk                          /*!< Current coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCCRR2_RA_Pos              (16U)
+#define DCMIPP_P1CCCRR2_RA_Msk              (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCRR2_RA                  DCMIPP_P1CCCRR2_RA_Msk                          /*!< Current coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCGR1 register  ****************/
+#define DCMIPP_P1CCCGR1_GR_Pos              (0U)
+#define DCMIPP_P1CCCGR1_GR_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR1_GR                  DCMIPP_P1CCCGR1_GR_Msk                          /*!< Current coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCCGR1_GG_Pos              (16U)
+#define DCMIPP_P1CCCGR1_GG_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCGR1_GG                  DCMIPP_P1CCCGR1_GG_Msk                          /*!< Current coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCGR2 register  ****************/
+#define DCMIPP_P1CCCGR2_GB_Pos              (0U)
+#define DCMIPP_P1CCCGR2_GB_Msk              (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR2_GB                  DCMIPP_P1CCCGR2_GB_Msk                          /*!< Current coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCCGR2_GA_Pos              (16U)
+#define DCMIPP_P1CCCGR2_GA_Msk              (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCGR2_GA                  DCMIPP_P1CCCGR2_GA_Msk                          /*!< Current coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCBR1 register  ****************/
+#define DCMIPP_P1CCCBR1_BR_Pos              (0U)
+#define DCMIPP_P1CCCBR1_BR_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR1_BR                  DCMIPP_P1CCCBR1_BR_Msk                          /*!< Current coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCCBR1_BG_Pos              (16U)
+#define DCMIPP_P1CCCBR1_BG_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCBR1_BG                  DCMIPP_P1CCCBR1_BG_Msk                          /*!< Current coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCBR2 register  ****************/
+#define DCMIPP_P1CCCBR2_BB_Pos              (0U)
+#define DCMIPP_P1CCCBR2_BB_Msk              (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR2_BB                  DCMIPP_P1CCCBR2_BB_Msk                          /*!< Current coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCCBR2_BA_Pos              (16U)
+#define DCMIPP_P1CCCBR2_BA_Msk              (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCBR2_BA                  DCMIPP_P1CCCBR2_BA_Msk                          /*!< Current coefficient row 3 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR1 register  ****************/
+#define DCMIPP_P1CCTCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CCTCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CCTCR1_ENABLE              DCMIPP_P1CCTCR1_ENABLE_Msk                      /*!< Current ENABLE bit value */
+#define DCMIPP_P1CCTCR1_LUM0_Pos            (9U)
+#define DCMIPP_P1CCTCR1_LUM0_Msk            (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR1_LUM0                DCMIPP_P1CCTCR1_LUM0_Msk                        /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR2 register  ****************/
+#define DCMIPP_P1CCTCR2_LUM4_Pos            (1U)
+#define DCMIPP_P1CCTCR2_LUM4_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR2_LUM4                DCMIPP_P1CCTCR2_LUM4_Msk                        /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM3_Pos            (9U)
+#define DCMIPP_P1CCTCR2_LUM3_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR2_LUM3                DCMIPP_P1CCTCR2_LUM3_Msk                        /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM2_Pos            (17U)
+#define DCMIPP_P1CCTCR2_LUM2_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR2_LUM2                DCMIPP_P1CCTCR2_LUM2_Msk                        /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM1_Pos            (25U)
+#define DCMIPP_P1CCTCR2_LUM1_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR2_LUM1                DCMIPP_P1CCTCR2_LUM1_Msk                        /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR3 register  ****************/
+#define DCMIPP_P1CCTCR3_LUM8_Pos            (1U)
+#define DCMIPP_P1CCTCR3_LUM8_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR3_LUM8                DCMIPP_P1CCTCR3_LUM8_Msk                        /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM7_Pos            (9U)
+#define DCMIPP_P1CCTCR3_LUM7_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR3_LUM7                DCMIPP_P1CCTCR3_LUM7_Msk                        /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM6_Pos            (17U)
+#define DCMIPP_P1CCTCR3_LUM6_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR3_LUM6                DCMIPP_P1CCTCR3_LUM6_Msk                        /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM5_Pos            (25U)
+#define DCMIPP_P1CCTCR3_LUM5_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR3_LUM5                DCMIPP_P1CCTCR3_LUM5_Msk                        /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CFCTCR register  ****************/
+#define DCMIPP_P1CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P1CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P1CFCTCR_FRATE               DCMIPP_P1CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P1CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P1CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P1CFCTCR_CPTMODE             DCMIPP_P1CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P1CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P1CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P1CFCTCR_CPTREQ              DCMIPP_P1CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P1CCRSTR register  ****************/
+#define DCMIPP_P1CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSTR_HSTART              DCMIPP_P1CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSTR_VSTART              DCMIPP_P1CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CCRSZR register  ****************/
+#define DCMIPP_P1CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSZR_HSIZE               DCMIPP_P1CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSZR_VSIZE               DCMIPP_P1CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P1CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CCRSZR_ENABLE              DCMIPP_P1CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P1CDCCR register  *****************/
+#define DCMIPP_P1CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CDCCR_ENABLE               DCMIPP_P1CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P1CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P1CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1CDCCR_HDEC                 DCMIPP_P1CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P1CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P1CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1CDCCR_VDEC                 DCMIPP_P1CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1CDSCR register  ****************/
+#define DCMIPP_P1CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P1CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P1CDSCR_HDIV                 DCMIPP_P1CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P1CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P1CDSCR_VDIV                 DCMIPP_P1CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CDSCR_ENABLE               DCMIPP_P1CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P1CDSRTIOR register  ***************/
+#define DCMIPP_P1CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P1CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P1CDSRTIOR_HRATIO            DCMIPP_P1CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P1CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P1CDSRTIOR_VRATIO            DCMIPP_P1CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P1CDSSZR register  ****************/
+#define DCMIPP_P1CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CDSSZR_HSIZE               DCMIPP_P1CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CDSSZR_VSIZE               DCMIPP_P1CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CPPCR register  ****************/
+#define DCMIPP_P1CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P1CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P1CPPCR_FORMAT               DCMIPP_P1CPPCR_FORMAT_Msk                       /*!< Memory format */
+#define DCMIPP_P1CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P1CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P1CPPCR_SWAPRB               DCMIPP_P1CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P1CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P1CPPCR_LINEMULT             DCMIPP_P1CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+
+/**************  Bit definition for DCMIPP_P1CPPM0AR1 register  ***************/
+#define DCMIPP_P1CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P1CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM0AR1_M0A               DCMIPP_P1CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM0PR register  ***************/
+#define DCMIPP_P1CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM0PR_PITCH              DCMIPP_P1CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM1AR1 register  ***************/
+#define DCMIPP_P1CPPM1AR1_M1A_Pos           (0U)
+#define DCMIPP_P1CPPM1AR1_M1A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM1AR1_M1A               DCMIPP_P1CPPM1AR1_M1A_Msk                       /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM1PR register  ***************/
+#define DCMIPP_P1CPPM1PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM1PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM1PR_PITCH              DCMIPP_P1CPPM1PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM2AR1 register  ***************/
+#define DCMIPP_P1CPPM2AR1_M2A_Pos           (0U)
+#define DCMIPP_P1CPPM2AR1_M2A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM2AR1_M2A               DCMIPP_P1CPPM2AR1_M2A_Msk                       /*!< Memory 2 address */
+
+/****************  Bit definition for DCMIPP_P2FSCR register  *****************/
+#define DCMIPP_P2FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P2FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2FSCR_DTIDA                 DCMIPP_P2FSCR_DTIDA_Msk                         /*!< Data type ID */
+#define DCMIPP_P2FSCR_VC_Pos                (19U)
+#define DCMIPP_P2FSCR_VC_Msk                (0x3UL << DCMIPP_P2FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P2FSCR_VC                    DCMIPP_P2FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P2FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P2FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P2FSCR_FDTF                  DCMIPP_P2FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P2FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P2FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P2FSCR_FDTFEN                DCMIPP_P2FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P2FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P2FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P2FSCR_PIPEN                 DCMIPP_P2FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P2FCTCR register  ****************/
+#define DCMIPP_P2FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P2FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P2FCTCR_FRATE                DCMIPP_P2FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P2FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P2FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P2FCTCR_CPTMODE              DCMIPP_P2FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P2FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P2FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P2FCTCR_CPTREQ               DCMIPP_P2FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P2CRSTR register  ****************/
+#define DCMIPP_P2CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P2CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CRSTR_HSTART               DCMIPP_P2CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P2CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSTR_VSTART               DCMIPP_P2CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CRSZR register  ****************/
+#define DCMIPP_P2CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2CRSZR_HSIZE                DCMIPP_P2CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSZR_VSIZE                DCMIPP_P2CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CRSZR_ENABLE               DCMIPP_P2CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P2DCCR register  *****************/
+#define DCMIPP_P2DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P2DCCR_ENABLE                DCMIPP_P2DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P2DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P2DCCR_HDEC_Msk              (0x3UL << DCMIPP_P2DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P2DCCR_HDEC                  DCMIPP_P2DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P2DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P2DCCR_VDEC_Msk              (0x3UL << DCMIPP_P2DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P2DCCR_VDEC                  DCMIPP_P2DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2DSCR register  *****************/
+#define DCMIPP_P2DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P2DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P2DSCR_HDIV                  DCMIPP_P2DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P2DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P2DSCR_VDIV                  DCMIPP_P2DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P2DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2DSCR_ENABLE                DCMIPP_P2DSCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2DSRTIOR register  ***************/
+#define DCMIPP_P2DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P2DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P2DSRTIOR_HRATIO             DCMIPP_P2DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P2DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P2DSRTIOR_VRATIO             DCMIPP_P2DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P2DSSZR register  ****************/
+#define DCMIPP_P2DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2DSSZR_HSIZE                DCMIPP_P2DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2DSSZR_VSIZE                DCMIPP_P2DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2GMCR register  *****************/
+#define DCMIPP_P2GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P2GMCR_ENABLE                DCMIPP_P2GMCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2CMRICR register  ***************/
+#define DCMIPP_P2CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P2CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P2CMRICR_ROILSZ              DCMIPP_P2CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P2CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P2CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P2CMRICR_ROI1EN              DCMIPP_P2CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P2CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P2CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P2CMRICR_ROI2EN              DCMIPP_P2CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P2CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P2CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P2CMRICR_ROI3EN              DCMIPP_P2CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P2CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P2CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P2CMRICR_ROI4EN              DCMIPP_P2CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P2CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P2CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P2CMRICR_ROI5EN              DCMIPP_P2CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P2CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P2CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P2CMRICR_ROI6EN              DCMIPP_P2CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P2CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P2CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P2CMRICR_ROI7EN              DCMIPP_P2CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P2CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P2CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P2CMRICR_ROI8EN              DCMIPP_P2CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P2RIxCR1 register  ***************/
+#define DCMIPP_P2RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P2RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P2RIxCR1_HSTART              DCMIPP_P2RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P2RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P2RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P2RIxCR1_CLB                 DCMIPP_P2RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P2RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P2RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P2RIxCR1_CLG                 DCMIPP_P2RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P2RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P2RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P2RIxCR1_VSTART              DCMIPP_P2RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P2RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P2RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P2RIxCR1_CLR                 DCMIPP_P2RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P2RIxCR2 register  ***************/
+#define DCMIPP_P2RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P2RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P2RIxCR2_VSIZE               DCMIPP_P2RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P2RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P2RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P2RIxCR2_HSIZE               DCMIPP_P2RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P2PPCR register  *****************/
+#define DCMIPP_P2PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P2PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P2PPCR_FORMAT                DCMIPP_P2PPCR_FORMAT_Msk                         /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P2PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P2PPCR_SWAPRB                DCMIPP_P2PPCR_SWAPRB_Msk                         /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P2PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P2PPCR_LINEMULT              DCMIPP_P2PPCR_LINEMULT_Msk                       /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2PPCR_DBM_Pos               (16U)
+#define DCMIPP_P2PPCR_DBM_Msk               (0x1UL << DCMIPP_P2PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P2PPCR_DBM                   DCMIPP_P2PPCR_DBM_Msk                            /*!< Double buffer mode */
+#define DCMIPP_P2PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P2PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos)               /*!< 0x000E0000 */
+#define DCMIPP_P2PPCR_LMAWM                 DCMIPP_P2PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P2PPCR_LMAWE_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos)               /*!< 0x00100000 */
+#define DCMIPP_P2PPCR_LMAWE                 DCMIPP_P2PPCR_LMAWE_Msk                          /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR1 register  ***************/
+#define DCMIPP_P2PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR1_M0A                DCMIPP_P2PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1 */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR2 register  ***************/
+#define DCMIPP_P2PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR2_M0A                DCMIPP_P2PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2*/
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P2PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P2PPM0PR_PITCH               DCMIPP_P2PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2STM0AR_Pos                 (0U)
+#define DCMIPP_P2STM0AR_Msk                 (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P2STM0AR                     DCMIPP_P2STM0AR_Msk                             /*!< Pipe2 status Memory0 address register */
+
+/*****************  Bit definition for DCMIPP_P2IER register  *****************/
+#define DCMIPP_P2IER_LINEIE_Pos             (0U)
+#define DCMIPP_P2IER_LINEIE_Msk             (0x1UL << DCMIPP_P2IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2IER_LINEIE                 DCMIPP_P2IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P2IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P2IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2IER_FRAMEIE                DCMIPP_P2IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P2IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P2IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2IER_VSYNCIE                DCMIPP_P2IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P2IER_OVRIE_Pos              (7U)
+#define DCMIPP_P2IER_OVRIE_Msk              (0x1UL << DCMIPP_P2IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2IER_OVRIE                  DCMIPP_P2IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P2SR register  ******************/
+#define DCMIPP_P2SR_LINEF_Pos               (0U)
+#define DCMIPP_P2SR_LINEF_Msk               (0x1UL << DCMIPP_P2SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P2SR_LINEF                   DCMIPP_P2SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P2SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P2SR_FRAMEF_Msk              (0x1UL << DCMIPP_P2SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P2SR_FRAMEF                  DCMIPP_P2SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P2SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P2SR_VSYNCF_Msk              (0x1UL << DCMIPP_P2SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P2SR_VSYNCF                  DCMIPP_P2SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P2SR_OVRF_Pos                (7U)
+#define DCMIPP_P2SR_OVRF_Msk                (0x1UL << DCMIPP_P2SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P2SR_OVRF                    DCMIPP_P2SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P2SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P2SR_LSTLINE_Msk             (0x1UL << DCMIPP_P2SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P2SR_LSTLINE                 DCMIPP_P2SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P2SR_LSTFRM_Msk              (0x1UL << DCMIPP_P2SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P2SR_LSTFRM                  DCMIPP_P2SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_CPTACT_Pos              (23U)
+#define DCMIPP_P2SR_CPTACT_Msk              (0x1UL << DCMIPP_P2SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P2SR_CPTACT                  DCMIPP_P2SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P2FCR register  *****************/
+#define DCMIPP_P2FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P2FCR_CLINEF_Msk             (0x1UL << DCMIPP_P2FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2FCR_CLINEF                 DCMIPP_P2FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P2FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2FCR_CFRAMEF                DCMIPP_P2FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P2FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2FCR_CVSYNCF                DCMIPP_P2FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P2FCR_COVRF_Pos              (7U)
+#define DCMIPP_P2FCR_COVRF_Msk              (0x1UL << DCMIPP_P2FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2FCR_COVRF                  DCMIPP_P2FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P2CFSCR register  ****************/
+#define DCMIPP_P2CFSCR_DTID_Pos             (0U)
+#define DCMIPP_P2CFSCR_DTID_Msk             (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2CFSCR_DTID                 DCMIPP_P2CFSCR_DTID_Msk                         /*!< Current Data type ID */
+#define DCMIPP_P2CFSCR_VC_Pos               (19U)
+#define DCMIPP_P2CFSCR_VC_Msk               (0x3UL << DCMIPP_P2CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P2CFSCR_VC                   DCMIPP_P2CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P2CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P2CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P2CFSCR_FDTF                 DCMIPP_P2CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P2CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P2CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P2CFSCR_FDTFEN               DCMIPP_P2CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P2CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P2CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2CFSCR_PIPEN                DCMIPP_P2CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P2CFCTCR register  ****************/
+#define DCMIPP_P2CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P2CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P2CFCTCR_FRATE               DCMIPP_P2CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P2CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P2CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P2CFCTCR_CPTMODE             DCMIPP_P2CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P2CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P2CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P2CFCTCR_CPTREQ              DCMIPP_P2CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P2CCRSTR register  ****************/
+#define DCMIPP_P2CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P2CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSTR_HSTART              DCMIPP_P2CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P2CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSTR_VSTART              DCMIPP_P2CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P2CCRSZR register  ****************/
+#define DCMIPP_P2CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSZR_HSIZE               DCMIPP_P2CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSZR_VSIZE               DCMIPP_P2CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P2CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P2CCRSZR_ENABLE              DCMIPP_P2CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P2CDCCR register  *****************/
+#define DCMIPP_P2CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P2CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P2CDCCR_ENABLE               DCMIPP_P2CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P2CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P2CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos)              /*!< 0x00000006 */
+#define DCMIPP_P2CDCCR_HDEC                 DCMIPP_P2CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P2CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P2CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos)              /*!< 0x00000018 */
+#define DCMIPP_P2CDCCR_VDEC                 DCMIPP_P2CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2CDSCR register  ****************/
+#define DCMIPP_P2CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P2CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P2CDSCR_HDIV                 DCMIPP_P2CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P2CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P2CDSCR_VDIV                 DCMIPP_P2CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CDSCR_ENABLE               DCMIPP_P2CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P2CDSRTIOR register  ***************/
+#define DCMIPP_P2CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P2CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P2CDSRTIOR_HRATIO            DCMIPP_P2CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P2CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P2CDSRTIOR_VRATIO            DCMIPP_P2CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P2CDSSZR register  ****************/
+#define DCMIPP_P2CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CDSSZR_HSIZE               DCMIPP_P2CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CDSSZR_VSIZE               DCMIPP_P2CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CPPCR register  ****************/
+#define DCMIPP_P2CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P2CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P2CPPCR_FORMAT               DCMIPP_P2CPPCR_FORMAT_Msk                       /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P2CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P2CPPCR_SWAPRB               DCMIPP_P2CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P2CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P2CPPCR_LINEMULT             DCMIPP_P2CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P2CPPCR_DBM_Msk              (0x1UL << DCMIPP_P2CPPCR_DBM_Pos)                /*!< 0x00010000 */
+#define DCMIPP_P2CPPCR_DBM                  DCMIPP_P2CPPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P2CPPCR_LMAWM_Pos            (17U)
+#define DCMIPP_P2CPPCR_LMAWM_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos)              /*!< 0x000E0000 */
+#define DCMIPP_P2CPPCR_LMAWM                DCMIPP_P2CPPCR_LMAWM_Msk                         /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2CPPCR_LMAWE_Pos            (20U)
+#define DCMIPP_P2CPPCR_LMAWE_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos)              /*!< 0x00100000 */
+#define DCMIPP_P2CPPCR_LMAWE                DCMIPP_P2CPPCR_LMAWE_Msk                         /*!< Line multi address wrapping enable */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR1 register  ***************/
+#define DCMIPP_P2CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR1_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR2 register  ***************/
+#define DCMIPP_P2CPPM0AR2_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR2_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR2_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address Register 2 */
+
+/***************  Bit definition for DCMIPP_P2CPPM0PR register  ***************/
+#define DCMIPP_P2CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P2CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P2CPPM0PR_PITCH              DCMIPP_P2CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/****************  Bit definition for DCMIPP_HWCFGR2 register  ****************/
+#define DCMIPP_HWCFGR2_VPFT_Pos             (0U)
+#define DCMIPP_HWCFGR2_VPFT_Msk             (0x7U << DCMIPP_HWCFGR2_VPFT_Pos)               /*!< 0x00000007 */
+#define DCMIPP_HWCFGR2_VPFT                 DCMIPP_HWCFGR2_VPFT_Msk                         /*!< Virtual pipe function */
+#define DCMIPP_HWCFGR2_DBMFT_Pos            (4U)
+#define DCMIPP_HWCFGR2_DBMFT_Msk            (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos)              /*!< 0x00000010 */
+#define DCMIPP_HWCFGR2_DBMFT                DCMIPP_HWCFGR2_DBMFT_Msk                        /*!< Double buffer mode featured */
+#define DCMIPP_HWCFGR2_PROCCLK_Pos          (8U)
+#define DCMIPP_HWCFGR2_PROCCLK_Msk          (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos)            /*!< 0x00000100 */
+#define DCMIPP_HWCFGR2_PROCCLK              DCMIPP_HWCFGR2_PROCCLK_Msk                      /*!< Processing clock linked to AXI clock featured */
+#define DCMIPP_HWCFGR2_ADDMOD_Pos           (12U)
+#define DCMIPP_HWCFGR2_ADDMOD_Msk           (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR2_ADDMOD               DCMIPP_HWCFGR2_ADDMOD_Msk                       /*!< Address modulo computation to access a small buffer in streaming featured */
+#define DCMIPP_HWCFGR2_DEC1_Pos             (16U)
+#define DCMIPP_HWCFGR2_DEC1_Msk             (0x1U << DCMIPP_HWCFGR2_DEC1_Pos)               /*!< 0x00010000 */
+#define DCMIPP_HWCFGR2_DEC1                 DCMIPP_HWCFGR2_DEC1_Msk                         /*!< Decimation on Pipe1 before downsize */
+#define DCMIPP_HWCFGR2_DEC2_Pos             (17U)
+#define DCMIPP_HWCFGR2_DEC2_Msk             (0x1U << DCMIPP_HWCFGR2_DEC2_Pos)               /*!< 0x00020000 */
+#define DCMIPP_HWCFGR2_DEC2                 DCMIPP_HWCFGR2_DEC2_Msk                         /*!< Decimation on Pipe2 before downsize */
+#define DCMIPP_HWCFGR2_MCU_Pos              (20U)
+#define DCMIPP_HWCFGR2_MCU_Msk              (0x1U << DCMIPP_HWCFGR2_MCU_Pos)                /*!< 0x00100000 */
+#define DCMIPP_HWCFGR2_MCU                  DCMIPP_HWCFGR2_MCU_Msk                          /*!< Macroblock unit as pixel format  */
+#define DCMIPP_HWCFGR2_TPG_Pos              (24U)
+#define DCMIPP_HWCFGR2_TPG_Msk              (0x1U << DCMIPP_HWCFGR2_TPG_Pos)                /*!< 0x01000000 */
+#define DCMIPP_HWCFGR2_TPG                  DCMIPP_HWCFGR2_TPG_Msk                          /*!< Test Pattern Generator */
+#define DCMIPP_HWCFGR2_STV_Pos              (28U)
+#define DCMIPP_HWCFGR2_STV_Msk              (0x1U << DCMIPP_HWCFGR2_STV_Pos)                /*!< 0x10000000 */
+#define DCMIPP_HWCFGR2_STV                  DCMIPP_HWCFGR2_STV_Msk                          /*!< Statistic Version */
+
+/****************  Bit definition for DCMIPP_HWCFGR1 register  ****************/
+#define DCMIPP_HWCFGR1_CSIFT_Pos            (0U)
+#define DCMIPP_HWCFGR1_CSIFT_Msk            (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos)              /*!< 0x00000001 */
+#define DCMIPP_HWCFGR1_CSIFT                DCMIPP_HWCFGR1_CSIFT_Msk                        /*!< CSI2 host protocol compliant */
+#define DCMIPP_HWCFGR1_PIPENB_Pos           (4U)
+#define DCMIPP_HWCFGR1_PIPENB_Msk           (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos)             /*!< 0x00000030 */
+#define DCMIPP_HWCFGR1_PIPENB               DCMIPP_HWCFGR1_PIPENB_Msk                       /*!< Number of pipes */
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos        (8U)
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk        (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos)          /*!< 0x00000100 */
+#define DCMIPP_HWCFGR1_IPPLUGCFG            DCMIPP_HWCFGR1_IPPLUGCFG_Msk                    /*!< IP-Plug configuration */
+#define DCMIPP_HWCFGR1_DSP1FT_Pos           (12U)
+#define DCMIPP_HWCFGR1_DSP1FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR1_DSP1FT               DCMIPP_HWCFGR1_DSP1FT_Msk                       /*!< Down-sampling feature for the pixel Pipe1 */
+#define DCMIPP_HWCFGR1_DSP2FT_Pos           (13U)
+#define DCMIPP_HWCFGR1_DSP2FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos)             /*!< 0x00002000 */
+#define DCMIPP_HWCFGR1_DSP2FT               DCMIPP_HWCFGR1_DSP2FT_Msk                       /*!< Down-sampling feature for the pixel Pipe2 */
+#define DCMIPP_HWCFGR1_RB2RGB_Pos           (16U)
+#define DCMIPP_HWCFGR1_RB2RGB_Msk           (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos)             /*!< 0x00010000 */
+#define DCMIPP_HWCFGR1_RB2RGB               DCMIPP_HWCFGR1_RB2RGB_Msk                       /*!< Raw Bayer to RGB feature (demosaicer) */
+#define DCMIPP_HWCFGR1_PLANARFT_Pos         (20U)
+#define DCMIPP_HWCFGR1_PLANARFT_Msk         (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos)           /*!< 0x00300000 */
+#define DCMIPP_HWCFGR1_PLANARFT             DCMIPP_HWCFGR1_PLANARFT_Msk                     /*!< Buffer features for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI1NB_Pos           (24U)
+#define DCMIPP_HWCFGR1_ROI1NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos)             /*!< 0x0F000000 */
+#define DCMIPP_HWCFGR1_ROI1NB               DCMIPP_HWCFGR1_ROI1NB_Msk                       /*!< Number of ROIs for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI2NB_Pos           (28U)
+#define DCMIPP_HWCFGR1_ROI2NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos)             /*!< 0xF0000000 */
+#define DCMIPP_HWCFGR1_ROI2NB               DCMIPP_HWCFGR1_ROI2NB_Msk                       /*!< Number of ROIs for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_VERR register  ******************/
+#define DCMIPP_VERR_MINREV_Pos              (0U)
+#define DCMIPP_VERR_MINREV_Msk              (0xFU << DCMIPP_VERR_MINREV_Pos)                /*!< 0x0000000F */
+#define DCMIPP_VERR_MINREV                  DCMIPP_VERR_MINREV_Msk                          /*!< DCMIPP minor revision */
+#define DCMIPP_VERR_MAJREV_Pos              (4U)
+#define DCMIPP_VERR_MAJREV_Msk              (0xFU << DCMIPP_VERR_MAJREV_Pos)                /*!< 0x000000F0 */
+#define DCMIPP_VERR_MAJREV                  DCMIPP_VERR_MAJREV_Msk                          /*!< DCMIPP major revision */
+
+/*****************  Bit definition for DCMIPP_IPIDR register  *****************/
+#define DCMIPP_IPIDR_IDR_Pos                (0U)
+#define DCMIPP_IPIDR_IDR_Msk                (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_IPIDR_IDR                    DCMIPP_IPIDR_IDR_Msk                            /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */
+
+/*****************  Bit definition for DCMIPP_SIDR register  ******************/
+#define DCMIPP_SIDR_SID_Pos                 (0U)
+#define DCMIPP_SIDR_SID_Msk                 (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos)            /*!< 0xFFFFFFFF */
+#define DCMIPP_SIDR_SID                     DCMIPP_SIDR_SID_Msk                             /*!< 4-Kbyte decoding space */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos                     (0U)
+#define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
+#define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos                     (1U)
+#define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
+#define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos                   (0U)
+#define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
+#define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos                  (8U)
+#define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos                   (16U)
+#define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos                  (31U)
+#define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_SECCFGR register  ****************/
+#define DMA_SECCFGR_SEC0_Pos     (0U)
+#define DMA_SECCFGR_SEC0_Msk     (0x1UL << DMA_SECCFGR_SEC0_Pos)                /*!< 0x00000001 */
+#define DMA_SECCFGR_SEC0         DMA_SECCFGR_SEC0_Msk                          /*!< Secure State of Channel 0 */
+#define DMA_SECCFGR_SEC1_Pos     (1U)
+#define DMA_SECCFGR_SEC1_Msk     (0x1UL << DMA_SECCFGR_SEC1_Pos)                /*!< 0x00000002 */
+#define DMA_SECCFGR_SEC1         DMA_SECCFGR_SEC1_Msk                          /*!< Secure State of Channel 1 */
+#define DMA_SECCFGR_SEC2_Pos     (2U)
+#define DMA_SECCFGR_SEC2_Msk     (0x1UL << DMA_SECCFGR_SEC2_Pos)                /*!< 0x00000004 */
+#define DMA_SECCFGR_SEC2         DMA_SECCFGR_SEC2_Msk                          /*!< Secure State of Channel 2 */
+#define DMA_SECCFGR_SEC3_Pos     (3U)
+#define DMA_SECCFGR_SEC3_Msk     (0x1UL << DMA_SECCFGR_SEC3_Pos)                /*!< 0x00000008 */
+#define DMA_SECCFGR_SEC3         DMA_SECCFGR_SEC3_Msk                          /*!< Secure State of Channel 3 */
+#define DMA_SECCFGR_SEC4_Pos     (4U)
+#define DMA_SECCFGR_SEC4_Msk     (0x1UL << DMA_SECCFGR_SEC4_Pos)                /*!< 0x00000010 */
+#define DMA_SECCFGR_SEC4         DMA_SECCFGR_SEC4_Msk                          /*!< Secure State of Channel 4 */
+#define DMA_SECCFGR_SEC5_Pos     (5U)
+#define DMA_SECCFGR_SEC5_Msk     (0x1UL << DMA_SECCFGR_SEC5_Pos)                /*!< 0x00000020 */
+#define DMA_SECCFGR_SEC5         DMA_SECCFGR_SEC5_Msk                          /*!< Secure State of Channel 5 */
+#define DMA_SECCFGR_SEC6_Pos     (6U)
+#define DMA_SECCFGR_SEC6_Msk     (0x1UL << DMA_SECCFGR_SEC6_Pos)                /*!< 0x00000040 */
+#define DMA_SECCFGR_SEC6         DMA_SECCFGR_SEC6_Msk                          /*!< Secure State of Channel 6 */
+#define DMA_SECCFGR_SEC7_Pos     (7U)
+#define DMA_SECCFGR_SEC7_Msk     (0x1UL << DMA_SECCFGR_SEC7_Pos)                /*!< 0x00000080 */
+#define DMA_SECCFGR_SEC7         DMA_SECCFGR_SEC7_Msk                          /*!< Secure State of Channel 7 */
+#define DMA_SECCFGR_SEC8_Pos     (8U)
+#define DMA_SECCFGR_SEC8_Msk     (0x1UL << DMA_SECCFGR_SEC8_Pos)                /*!< 0x00000100 */
+#define DMA_SECCFGR_SEC8         DMA_SECCFGR_SEC8_Msk                          /*!< Secure State of Channel 8 */
+#define DMA_SECCFGR_SEC9_Pos     (9U)
+#define DMA_SECCFGR_SEC9_Msk     (0x1UL << DMA_SECCFGR_SEC9_Pos)                /*!< 0x00000200 */
+#define DMA_SECCFGR_SEC9         DMA_SECCFGR_SEC9_Msk                          /*!< Secure State of Channel 9 */
+#define DMA_SECCFGR_SEC10_Pos    (10U)
+#define DMA_SECCFGR_SEC10_Msk    (0x1UL << DMA_SECCFGR_SEC10_Pos)               /*!< 0x00000400 */
+#define DMA_SECCFGR_SEC10        DMA_SECCFGR_SEC10_Msk                         /*!< Secure State of Channel 10 */
+#define DMA_SECCFGR_SEC11_Pos    (11U)
+#define DMA_SECCFGR_SEC11_Msk    (0x1UL << DMA_SECCFGR_SEC11_Pos)               /*!< 0x00000800 */
+#define DMA_SECCFGR_SEC11        DMA_SECCFGR_SEC11_Msk                         /*!< Secure State of Channel 11 */
+#define DMA_SECCFGR_SEC12_Pos    (12U)
+#define DMA_SECCFGR_SEC12_Msk    (0x1UL << DMA_SECCFGR_SEC12_Pos)               /*!< 0x00001000 */
+#define DMA_SECCFGR_SEC12        DMA_SECCFGR_SEC12_Msk                         /*!< Secure State of Channel 12 */
+#define DMA_SECCFGR_SEC13_Pos    (13U)
+#define DMA_SECCFGR_SEC13_Msk    (0x1UL << DMA_SECCFGR_SEC13_Pos)               /*!< 0x00002000 */
+#define DMA_SECCFGR_SEC13        DMA_SECCFGR_SEC13_Msk                         /*!< Secure State of Channel 13 */
+#define DMA_SECCFGR_SEC14_Pos    (14U)
+#define DMA_SECCFGR_SEC14_Msk    (0x1UL << DMA_SECCFGR_SEC14_Pos)               /*!< 0x00004000 */
+#define DMA_SECCFGR_SEC14        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 14 */
+#define DMA_SECCFGR_SEC15_Pos    (15U)
+#define DMA_SECCFGR_SEC15_Msk    (0x1UL << DMA_SECCFGR_SEC15_Pos)               /*!< 0x00008000 */
+#define DMA_SECCFGR_SEC15        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 15 */
+
+/*******************  Bit definition for DMA_PRIVCFGR register  ****************/
+#define DMA_PRIVCFGR_PRIV0_Pos              (0U)
+#define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0 */
+#define DMA_PRIVCFGR_PRIV1_Pos              (1U)
+#define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1 */
+#define DMA_PRIVCFGR_PRIV2_Pos              (2U)
+#define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2 */
+#define DMA_PRIVCFGR_PRIV3_Pos              (3U)
+#define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3 */
+#define DMA_PRIVCFGR_PRIV4_Pos              (4U)
+#define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4 */
+#define DMA_PRIVCFGR_PRIV5_Pos              (5U)
+#define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5 */
+#define DMA_PRIVCFGR_PRIV6_Pos              (6U)
+#define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6 */
+#define DMA_PRIVCFGR_PRIV7_Pos              (7U)
+#define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7 */
+#define DMA_PRIVCFGR_PRIV8_Pos              (8U)
+#define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
+#define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8 */
+#define DMA_PRIVCFGR_PRIV9_Pos              (9U)
+#define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
+#define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9 */
+#define DMA_PRIVCFGR_PRIV10_Pos             (10U)
+#define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
+#define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
+#define DMA_PRIVCFGR_PRIV11_Pos             (11U)
+#define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
+#define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */
+#define DMA_PRIVCFGR_PRIV12_Pos             (12U)
+#define DMA_PRIVCFGR_PRIV12_Msk             (0x1UL << DMA_PRIVCFGR_PRIV12_Pos)      /*!< 0x00001000 */
+#define DMA_PRIVCFGR_PRIV12                 DMA_PRIVCFGR_PRIV12_Msk                 /*!< Privileged State of Channel 12 */
+#define DMA_PRIVCFGR_PRIV13_Pos             (13U)
+#define DMA_PRIVCFGR_PRIV13_Msk             (0x1UL << DMA_PRIVCFGR_PRIV13_Pos)      /*!< 0x00002000 */
+#define DMA_PRIVCFGR_PRIV13                 DMA_PRIVCFGR_PRIV13_Msk                 /*!< Privileged State of Channel 13 */
+#define DMA_PRIVCFGR_PRIV14_Pos             (14U)
+#define DMA_PRIVCFGR_PRIV14_Msk             (0x1UL << DMA_PRIVCFGR_PRIV14_Pos)      /*!< 0x00004000 */
+#define DMA_PRIVCFGR_PRIV14                 DMA_PRIVCFGR_PRIV14_Msk                 /*!< Privileged State of Channel 14 */
+#define DMA_PRIVCFGR_PRIV15_Pos             (15U)
+#define DMA_PRIVCFGR_PRIV15_Msk             (0x1UL << DMA_PRIVCFGR_PRIV15_Pos)      /*!< 0x00008000 */
+#define DMA_PRIVCFGR_PRIV15                 DMA_PRIVCFGR_PRIV15_Msk                 /*!< Privileged State of Channel 15 */
+
+/*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
+#define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
+#define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
+#define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
+#define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
+#define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
+#define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
+#define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
+#define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
+#define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
+#define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
+#define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
+#define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
+#define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
+#define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
+#define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
+#define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
+#define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
+#define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
+#define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
+#define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
+#define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
+#define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
+#define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
+#define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
+#define DMA_RCFGLOCKR_LOCK8_Pos              (8U)
+#define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
+#define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
+#define DMA_RCFGLOCKR_LOCK9_Pos              (9U)
+#define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
+#define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
+#define DMA_RCFGLOCKR_LOCK10_Pos             (10U)
+#define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
+#define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
+#define DMA_RCFGLOCKR_LOCK11_Pos             (11U)
+#define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
+#define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */
+#define DMA_RCFGLOCKR_LOCK12_Pos             (12U)
+#define DMA_RCFGLOCKR_LOCK12_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos)      /*!< 0x00001000 */
+#define DMA_RCFGLOCKR_LOCK12                 DMA_RCFGLOCKR_LOCK12_Msk                 /*!< Lock the configuration of Channel 12 */
+#define DMA_RCFGLOCKR_LOCK13_Pos             (13U)
+#define DMA_RCFGLOCKR_LOCK13_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos)      /*!< 0x00002000 */
+#define DMA_RCFGLOCKR_LOCK13                 DMA_RCFGLOCKR_LOCK13_Msk                 /*!< Lock the configuration of Channel 13 */
+#define DMA_RCFGLOCKR_LOCK14_Pos             (14U)
+#define DMA_RCFGLOCKR_LOCK14_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos)      /*!< 0x00004000 */
+#define DMA_RCFGLOCKR_LOCK14                 DMA_RCFGLOCKR_LOCK14_Msk                 /*!< Lock the configuration of Channel 14 */
+#define DMA_RCFGLOCKR_LOCK15_Pos             (15U)
+#define DMA_RCFGLOCKR_LOCK15_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos)      /*!< 0x00008000 */
+#define DMA_RCFGLOCKR_LOCK15                 DMA_RCFGLOCKR_LOCK15_Msk                 /*!< Lock the configuration of Channel 15 */
+
+/*******************  Bit definition for DMA_MISR register  ****************/
+#define DMA_MISR_MIS0_Pos                   (0U)
+#define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
+#define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0 */
+#define DMA_MISR_MIS1_Pos                   (1U)
+#define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
+#define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1 */
+#define DMA_MISR_MIS2_Pos                   (2U)
+#define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
+#define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2 */
+#define DMA_MISR_MIS3_Pos                   (3U)
+#define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
+#define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3 */
+#define DMA_MISR_MIS4_Pos                   (4U)
+#define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
+#define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4 */
+#define DMA_MISR_MIS5_Pos                   (5U)
+#define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
+#define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5 */
+#define DMA_MISR_MIS6_Pos                   (6U)
+#define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
+#define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6 */
+#define DMA_MISR_MIS7_Pos                   (7U)
+#define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
+#define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7 */
+#define DMA_MISR_MIS8_Pos                   (8U)
+#define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
+#define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 8 */
+#define DMA_MISR_MIS9_Pos                   (9U)
+#define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
+#define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 9 */
+#define DMA_MISR_MIS10_Pos                  (10U)
+#define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
+#define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 10 */
+#define DMA_MISR_MIS11_Pos                  (11U)
+#define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
+#define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 11 */
+#define DMA_MISR_MIS12_Pos                  (12U)
+#define DMA_MISR_MIS12_Msk                  (0x1UL << DMA_MISR_MIS12_Pos)           /*!< 0x00001000 */
+#define DMA_MISR_MIS12                      DMA_MISR_MIS12_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 12 */
+#define DMA_MISR_MIS13_Pos                  (13U)
+#define DMA_MISR_MIS13_Msk                  (0x1UL << DMA_MISR_MIS13_Pos)           /*!< 0x00002000 */
+#define DMA_MISR_MIS13                      DMA_MISR_MIS13_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 13 */
+#define DMA_MISR_MIS14_Pos                  (14U)
+#define DMA_MISR_MIS14_Msk                  (0x1UL << DMA_MISR_MIS14_Pos)           /*!< 0x00004000 */
+#define DMA_MISR_MIS14                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 14 */
+#define DMA_MISR_MIS15_Pos                  (15U)
+#define DMA_MISR_MIS15_Msk                  (0x1UL << DMA_MISR_MIS15_Pos)           /*!< 0x00008000 */
+#define DMA_MISR_MIS15                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 15 */
+
+/*******************  Bit definition for DMA_SMISR register  ****************/
+#define DMA_SMISR_MIS0_Pos       (0U)
+#define DMA_SMISR_MIS0_Msk       (0x1UL << DMA_SMISR_MIS0_Pos)                  /*!< 0x00000001 */
+#define DMA_SMISR_MIS0           DMA_SMISR_MIS0_Msk                            /*!< Masked Interrupt State of Secure Channel 0 */
+#define DMA_SMISR_MIS1_Pos       (1U)
+#define DMA_SMISR_MIS1_Msk       (0x1UL << DMA_SMISR_MIS1_Pos)                  /*!< 0x00000002 */
+#define DMA_SMISR_MIS1           DMA_SMISR_MIS1_Msk                            /*!< Masked Interrupt State of Secure Channel 1 */
+#define DMA_SMISR_MIS2_Pos       (2U)
+#define DMA_SMISR_MIS2_Msk       (0x1UL << DMA_SMISR_MIS2_Pos)                  /*!< 0x00000004 */
+#define DMA_SMISR_MIS2           DMA_SMISR_MIS2_Msk                            /*!< Masked Interrupt State of Secure Channel 2 */
+#define DMA_SMISR_MIS3_Pos       (3U)
+#define DMA_SMISR_MIS3_Msk       (0x1UL << DMA_SMISR_MIS3_Pos)                  /*!< 0x00000008 */
+#define DMA_SMISR_MIS3           DMA_SMISR_MIS3_Msk                            /*!< Masked Interrupt State of Secure Channel 3 */
+#define DMA_SMISR_MIS4_Pos       (4U)
+#define DMA_SMISR_MIS4_Msk       (0x1UL << DMA_SMISR_MIS4_Pos)                  /*!< 0x00000010 */
+#define DMA_SMISR_MIS4           DMA_SMISR_MIS4_Msk                            /*!< Masked Interrupt State of Secure Channel 4 */
+#define DMA_SMISR_MIS5_Pos       (5U)
+#define DMA_SMISR_MIS5_Msk       (0x1UL << DMA_SMISR_MIS5_Pos)                  /*!< 0x00000020 */
+#define DMA_SMISR_MIS5           DMA_SMISR_MIS5_Msk                            /*!< Masked Interrupt State of Secure Channel 5 */
+#define DMA_SMISR_MIS6_Pos       (6U)
+#define DMA_SMISR_MIS6_Msk       (0x1UL << DMA_SMISR_MIS6_Pos)                  /*!< 0x00000040 */
+#define DMA_SMISR_MIS6           DMA_SMISR_MIS6_Msk                            /*!< Masked Interrupt State of Secure Channel 6 */
+#define DMA_SMISR_MIS7_Pos       (7U)
+#define DMA_SMISR_MIS7_Msk       (0x1UL << DMA_SMISR_MIS7_Pos)                  /*!< 0x00000080 */
+#define DMA_SMISR_MIS7           DMA_SMISR_MIS7_Msk                            /*!< Masked Interrupt State of Secure Channel 7 */
+#define DMA_SMISR_MIS8_Pos       (8U)
+#define DMA_SMISR_MIS8_Msk       (0x1UL << DMA_SMISR_MIS8_Pos)                  /*!< 0x00000100 */
+#define DMA_SMISR_MIS8           DMA_SMISR_MIS8_Msk                            /*!< Masked Interrupt State of Secure Channel 8 */
+#define DMA_SMISR_MIS9_Pos       (9U)
+#define DMA_SMISR_MIS9_Msk       (0x1UL << DMA_SMISR_MIS9_Pos)                  /*!< 0x00000200 */
+#define DMA_SMISR_MIS9           DMA_SMISR_MIS9_Msk                            /*!< Masked Interrupt State of Secure Channel 9 */
+#define DMA_SMISR_MIS10_Pos      (10U)
+#define DMA_SMISR_MIS10_Msk      (0x1UL << DMA_SMISR_MIS10_Pos)                 /*!< 0x00000400 */
+#define DMA_SMISR_MIS10          DMA_SMISR_MIS10_Msk                           /*!< Masked Interrupt State of Secure Channel 10 */
+#define DMA_SMISR_MIS11_Pos      (11U)
+#define DMA_SMISR_MIS11_Msk      (0x1UL << DMA_SMISR_MIS11_Pos)                 /*!< 0x00000800 */
+#define DMA_SMISR_MIS11          DMA_SMISR_MIS11_Msk                           /*!< Masked Interrupt State of Secure Channel 11 */
+#define DMA_SMISR_MIS12_Pos      (12U)
+#define DMA_SMISR_MIS12_Msk      (0x1UL << DMA_SMISR_MIS12_Pos)                 /*!< 0x00001000 */
+#define DMA_SMISR_MIS12          DMA_SMISR_MIS12_Msk                           /*!< Masked Interrupt State of Secure Channel 12 */
+#define DMA_SMISR_MIS13_Pos      (13U)
+#define DMA_SMISR_MIS13_Msk      (0x1UL << DMA_SMISR_MIS13_Pos)                 /*!< 0x00002000 */
+#define DMA_SMISR_MIS13          DMA_SMISR_MIS13_Msk                           /*!< Masked Interrupt State of Secure Channel 13 */
+#define DMA_SMISR_MIS14_Pos      (14U)
+#define DMA_SMISR_MIS14_Msk      (0x1UL << DMA_SMISR_MIS14_Pos)                 /*!< 0x00004000 */
+#define DMA_SMISR_MIS14          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 14 */
+#define DMA_SMISR_MIS15_Pos      (15U)
+#define DMA_SMISR_MIS15_Msk      (0x1UL << DMA_SMISR_MIS15_Pos)                 /*!< 0x00008000 */
+#define DMA_SMISR_MIS15          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 15 */
+
+/*******************  Bit definition for DMA_CLBAR register  ****************/
+#define DMA_CLBAR_LBA_Pos                   (16U)
+#define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
+#define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
+
+/*******************  Bit definition for DMA_CCIDCFGR register  *******************/
+#define DMA_CCIDCFGR_CFEN_Pos           (0U)
+#define DMA_CCIDCFGR_CFEN_Msk           (0x1UL << DMA_CCIDCFGR_CFEN_Pos)         /*!< 0x00000001 */
+#define DMA_CCIDCFGR_CFEN               DMA_CCIDCFGR_CFEN_Msk                   /*!< CID filtering enable of the channel x */
+#define DMA_CCIDCFGR_SCID_Pos           (4U)
+#define DMA_CCIDCFGR_SCID_Msk           (0x7UL << DMA_CCIDCFGR_SCID_Pos)         /*!< 0x00000070 */
+#define DMA_CCIDCFGR_SCID               DMA_CCIDCFGR_SCID_Msk                   /*!< select a static CID to the channel x */
+
+/*******************  Bit definition for DMA_CFCR register  *******************/
+#define DMA_CFCR_TCF_Pos                    (8U)
+#define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
+#define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear */
+#define DMA_CFCR_HTF_Pos                    (9U)
+#define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
+#define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear */
+#define DMA_CFCR_DTEF_Pos                   (10U)
+#define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
+#define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear */
+#define DMA_CFCR_ULEF_Pos                   (11U)
+#define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
+#define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
+#define DMA_CFCR_USEF_Pos                   (12U)
+#define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
+#define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear */
+#define DMA_CFCR_SUSPF_Pos                  (13U)
+#define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
+#define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear */
+#define DMA_CFCR_TOF_Pos                    (14U)
+#define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
+#define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun clear flag */
+
+/*******************  Bit definition for DMA_CSR register  *******************/
+#define DMA_CSR_IDLEF_Pos                   (0U)
+#define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
+#define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag */
+#define DMA_CSR_TCF_Pos                     (8U)
+#define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
+#define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag */
+#define DMA_CSR_HTF_Pos                     (9U)
+#define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
+#define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag */
+#define DMA_CSR_DTEF_Pos                    (10U)
+#define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
+#define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag */
+#define DMA_CSR_ULEF_Pos                    (11U)
+#define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
+#define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
+#define DMA_CSR_USEF_Pos                    (12U)
+#define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
+#define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag */
+#define DMA_CSR_SUSPF_Pos                   (13U)
+#define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
+#define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag */
+#define DMA_CSR_TOF_Pos                     (14U)
+#define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
+#define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag */
+#define DMA_CSR_FIFOL_Pos                   (16U)
+#define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
+#define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos                      (0U)
+#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable */
+#define DMA_CCR_RESET_Pos                   (1U)
+#define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
+#define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset */
+#define DMA_CCR_SUSP_Pos                    (2U)
+#define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
+#define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend */
+#define DMA_CCR_TCIE_Pos                    (8U)
+#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
+#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos                    (9U)
+#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
+#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable */
+#define DMA_CCR_DTEIE_Pos                   (10U)
+#define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
+#define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable */
+#define DMA_CCR_ULEIE_Pos                   (11U)
+#define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
+#define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
+#define DMA_CCR_USEIE_Pos                   (12U)
+#define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
+#define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable */
+#define DMA_CCR_SUSPIE_Pos                  (13U)
+#define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
+#define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable */
+#define DMA_CCR_TOIE_Pos                    (14U)
+#define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
+#define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable */
+#define DMA_CCR_LSM_Pos                     (16U)
+#define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
+#define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode */
+#define DMA_CCR_LAP_Pos                     (17U)
+#define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
+#define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port */
+#define DMA_CCR_PRIO_Pos                    (22U)
+#define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
+#define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level */
+#define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
+#define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
+
+/*******************  Bit definition for DMA_CTR1 register  *******************/
+#define DMA_CTR1_SDW_LOG2_Pos               (0U)
+#define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
+#define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst */
+#define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_SINC_Pos                   (3U)
+#define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
+#define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst */
+#define DMA_CTR1_SBL_1_Pos                  (4U)
+#define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
+#define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1 */
+#define DMA_CTR1_PAM_Pos                    (11U)
+#define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
+#define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode */
+#define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
+#define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
+#define DMA_CTR1_SBX_Pos                    (13U)
+#define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
+#define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
+#define DMA_CTR1_SAP_Pos                    (14U)
+#define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
+#define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port */
+#define DMA_CTR1_SSEC_Pos                   (15U)
+#define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
+#define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source */
+#define DMA_CTR1_DDW_LOG2_Pos               (16U)
+#define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
+#define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst */
+#define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_DINC_Pos                   (19U)
+#define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
+#define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst */
+#define DMA_CTR1_DBL_1_Pos                  (20U)
+#define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
+#define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1 */
+#define DMA_CTR1_DBX_Pos                    (26U)
+#define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
+#define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange */
+#define DMA_CTR1_DHX_Pos                    (27U)
+#define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
+#define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange */
+#define DMA_CTR1_DWX_Pos                    (28U)
+#define DMA_CTR1_DWX_Msk                    (0x1UL << DMA_CTR1_DWX_Pos)             /*!< 0x10000000 */
+#define DMA_CTR1_DWX                        DMA_CTR1_DWX_Msk                        /*!< Destination word-word exchange */
+#define DMA_CTR1_DAP_Pos                    (30U)
+#define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
+#define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port */
+#define DMA_CTR1_DSEC_Pos                   (31U)
+#define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
+#define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination */
+
+/******************  Bit definition for DMA_CTR2 register  *******************/
+#define DMA_CTR2_REQSEL_Pos                 (0U)
+#define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
+#define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
+#define DMA_CTR2_SWREQ_Pos                  (9U)
+#define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
+#define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request */
+#define DMA_CTR2_DREQ_Pos                   (10U)
+#define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
+#define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request */
+#define DMA_CTR2_BREQ_Pos                   (11U)
+#define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
+#define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request */
+#define DMA_CTR2_PFREQ_Pos                  (12U)
+#define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)           /*!< 0x00001000 */
+#define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Hardware request in peripheral flow control mode */
+#define DMA_CTR2_TRIGM_Pos                  (14U)
+#define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
+#define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode */
+#define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
+#define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
+#define DMA_CTR2_TRIGSEL_Pos                (16U)
+#define DMA_CTR2_TRIGSEL_Msk                (0x7FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x007F0000 */
+#define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection */
+#define DMA_CTR2_TRIGPOL_Pos                (24U)
+#define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
+#define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity */
+#define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
+#define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
+#define DMA_CTR2_TCEM_Pos                   (30U)
+#define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
+#define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode */
+#define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
+#define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
+
+/******************  Bit definition for DMA_CBR1 register  *******************/
+#define DMA_CBR1_BNDT_Pos                   (0U)
+#define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
+#define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
+#define DMA_CBR1_BRC_Pos                    (16U)
+#define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
+#define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter */
+#define DMA_CBR1_SDEC_Pos                   (28U)
+#define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
+#define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement */
+#define DMA_CBR1_DDEC_Pos                   (29U)
+#define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
+#define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement */
+#define DMA_CBR1_BRSDEC_Pos                 (30U)
+#define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
+#define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement */
+#define DMA_CBR1_BRDDEC_Pos                 (31U)
+#define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
+#define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement */
+
+/******************  Bit definition for DMA_CSAR register  ********************/
+#define DMA_CSAR_SA_Pos                     (0U)
+#define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
+
+/******************  Bit definition for DMA_CDAR register  *******************/
+#define DMA_CDAR_DA_Pos                     (0U)
+#define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
+
+/******************  Bit definition for DMA_CTR3 register  *******************/
+#define DMA_CTR3_SAO_Pos                    (0U)
+#define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
+#define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment */
+#define DMA_CTR3_DAO_Pos                    (16U)
+#define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
+#define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
+
+/******************  Bit definition for DMA_CBR2 register  *******************/
+#define DMA_CBR2_BRSAO_Pos                  (0U)
+#define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
+#define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset */
+#define DMA_CBR2_BRDAO_Pos                  (16U)
+#define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
+#define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
+
+/******************  Bit definition for DMA_CLLR register  *******************/
+#define DMA_CLLR_LA_Pos                     (2U)
+#define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
+#define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
+#define DMA_CLLR_ULL_Pos                    (16U)
+#define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
+#define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory */
+#define DMA_CLLR_UB2_Pos                    (25U)
+#define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
+#define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory */
+#define DMA_CLLR_UT3_Pos                    (26U)
+#define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
+#define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM */
+#define DMA_CLLR_UDA_Pos                    (27U)
+#define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
+#define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM */
+#define DMA_CLLR_USA_Pos                    (28U)
+#define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
+#define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM */
+#define DMA_CLLR_UB1_Pos                    (29U)
+#define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
+#define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM */
+#define DMA_CLLR_UT2_Pos                    (30U)
+#define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
+#define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM */
+#define DMA_CLLR_UT1_Pos                    (31U)
+#define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
+#define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          DMA2D Controller (DMA2D)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DMA2D_CR register  ******************/
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0] */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /*!< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+/*!<Mode_ARGB8888/RGB888 */
+#define DMA2D_OCOLR_BLUE_1         (0x000000FFUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_1        (0x0000FF00UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_1          (0x00FF0000UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1        (0xFF000000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_2        (0x000007E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_2          (0x0000F800UL)                              /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_3        (0x000003E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_3          (0x00007C00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3        (0x00008000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4         (0x0000000FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_4        (0x000000F0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_4          (0x00000F00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4        (0x0000F000UL)                              /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital Temperature Sensor                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DTS_PVTREG_LOCKR register  *****************/
+#define DTS_PVTREG_LOCKR_LOCK_Pos                 (0U)
+#define DTS_PVTREG_LOCKR_LOCK_Msk                 (0xFFFFFFFFUL << DTS_PVTREG_LOCKR_LOCK_Pos)         /*!< 0xFFFFFFFF */
+#define DTS_PVTREG_LOCKR_LOCK                     DTS_PVTREG_LOCKR_LOCK_Msk                           /*!< PVT software lock */
+
+/*******************  Bit definition for DTS_PVTLOCK_SR register  *****************/
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos         (0U)
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos)        /*!< 0x00000001 */
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS             DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk                   /*!< Software lock status */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos         (1U)
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos)        /*!< 0x00000002 */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS             DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk                   /*!< Hardware lock status */
+
+/*******************  Bit definition for DTS_PVTTMR_CR register  *****************/
+#define DTS_PVTTMR_CR_TMR_DELAY_Pos               (0U)
+#define DTS_PVTTMR_CR_TMR_DELAY_Msk               (0xFFFFUL << DTS_PVTTMR_CR_TMR_DELAY_Pos)           /*!< 0x0000FFFF */
+#define DTS_PVTTMR_CR_TMR_DELAY                   DTS_PVTTMR_CR_TMR_DELAY_Msk                         /*!< Timer delay */
+#define DTS_PVTTMR_CR_TMR_RUN_Pos                 (16U)
+#define DTS_PVTTMR_CR_TMR_RUN_Msk                 (0x1UL << DTS_PVTTMR_CR_TMR_RUN_Pos)                /*!< 0x00010000 */
+#define DTS_PVTTMR_CR_TMR_RUN                     DTS_PVTTMR_CR_TMR_RUN_Msk                           /*!< Enable */
+
+/*******************  Bit definition for DTS_PVTTMR_SR register  *****************/
+#define DTS_PVTTMR_SR_TMR_BUSY_Pos                (0U)
+#define DTS_PVTTMR_SR_TMR_BUSY_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_BUSY_Pos)               /*!< 0x00000001 */
+#define DTS_PVTTMR_SR_TMR_BUSY                    DTS_PVTTMR_SR_TMR_BUSY_Msk                          /*!< Counter busy flag */
+#define DTS_PVTTMR_SR_TMR_DONE_Pos                (1U)
+#define DTS_PVTTMR_SR_TMR_DONE_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_PVTTMR_SR_TMR_DONE                    DTS_PVTTMR_SR_TMR_DONE_Msk                          /*!< Cnt delay timeout */
+
+/*******************  Bit definition for DTS_PVT_IER register  *****************/
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Pos            (0U)
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Msk            (0x1UL << DTS_PVT_IER_TMR_IRQ_ENABLE_Pos)           /*!< 0x00000001 */
+#define DTS_PVT_IER_TMR_IRQ_ENABLE                DTS_PVT_IER_TMR_IRQ_ENABLE_Msk                      /*!< Timer IRQ enable */
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Pos             (1U)
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Msk             (0x1UL << DTS_PVT_IER_TS_IRQ_ENABLE_Pos)            /*!< 0x00000002 */
+#define DTS_PVT_IER_TS_IRQ_ENABLE                 DTS_PVT_IER_TS_IRQ_ENABLE_Msk                       /*!< TS IRQ enable */
+
+/*******************  Bit definition for DTS_PVTIRQTRMASKR register  *****************/
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos        (0U)
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk        (0x1UL << DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos)       /*!< 0x00000001 */
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK            DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk                  /*!< Timer IRQ mask */
+
+/*******************  Bit definition for DTS_TS_MR register  *****************/
+#define DTS_TS_MR_TS0_IRQ_MASK_Pos                (0U)
+#define DTS_TS_MR_TS0_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS0_IRQ_MASK_Pos)               /*!< 0x00000001 */
+#define DTS_TS_MR_TS0_IRQ_MASK                    DTS_TS_MR_TS0_IRQ_MASK_Msk                          /*!< TS0 IRQ mask */
+#define DTS_TS_MR_TS1_IRQ_MASK_Pos                (1U)
+#define DTS_TS_MR_TS1_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS1_IRQ_MASK_Pos)               /*!< 0x00000002 */
+#define DTS_TS_MR_TS1_IRQ_MASK                    DTS_TS_MR_TS1_IRQ_MASK_Msk                          /*!< TS1 IRQ mask */
+
+/*******************  Bit definition for DTS_PVTTR_SR register  *****************/
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos           (0U)
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk           (0x1UL << DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos)          /*!< 0x00000001 */
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS               DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk                     /*!< Timer IRQ status after masking */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Pos             (0U)
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS0_IRQ_STATUS_Pos)            /*!< 0x00000001 */
+#define DTS_TS_ISR_TS0_IRQ_STATUS                 DTS_TS_ISR_TS0_IRQ_STATUS_Msk                       /*!< TS0 IRQ status after masking */
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Pos             (1U)
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS1_IRQ_STATUS_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ISR_TS1_IRQ_STATUS                 DTS_TS_ISR_TS1_IRQ_STATUS_Msk                       /*!< TS1 IRQ status after masking */
+
+/*******************  Bit definition for DTS_PVTTMRRAW_ISR register  *****************/
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos  (0U)
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk  (0x1UL << DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos) /*!< 0x00000001 */
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS      DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk            /*!< Timer IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSRAW_ISR register  *****************/
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos      (0U)
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos)     /*!< 0x00000001 */
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS0_RAW_IRQ_STATUS_Msk                /*!< TS0 IRQ status before masking */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos      (1U)
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos)     /*!< 0x00000002 */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk                /*!< TS1 IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSCCLKSYNTHR register  *****************/
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos         (0U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos)       /*!< 0x000000FF */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO             DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk                   /*!< Synthesized clk_ts low period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos         (8U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos)       /*!< 0x0000FF00 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI             DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk                   /*!< Synthesized clk_ts ghigh period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos       (16U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk       (0xFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos)      /*!< 0x000F0000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD           DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk                 /*!< Hold input or output delay */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos         (24U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk         (0x1UL << DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos)        /*!< 0x01000000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN             DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk                   /*!< Synthesized enable */
+
+/*******************  Bit definition for DTS_TSCSDIFDISABLER register  *****************/
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos  (0U)
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk            /*!< TS0 SDIF disable */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos  (1U)
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos) /*!< 0x00000002 */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk            /*!< TS1 SDIF disable */
+
+/*******************  Bit definition for DTS_TSCSDIF_SR register  *****************/
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Pos              (0U)
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_BUSY_Pos)             /*!< 0x00000001 */
+#define DTS_TSCSDIF_SR_SDIF_BUSY                  DTS_TSCSDIF_SR_SDIF_BUSY_Msk                        /*!< SDIF busy flag */
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Pos              (1U)
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_LOCK_Pos)             /*!< 0x00000002 */
+#define DTS_TSCSDIF_SR_SDIF_LOCK                  DTS_TSCSDIF_SR_SDIF_LOCK_Msk                        /*!< SDIF locked flag */
+
+/*******************  Bit definition for DTS_TSCSDIF_CR register  *****************/
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Pos             (0U)
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Msk             (0xFFFFFFUL << DTS_TSCSDIF_CR_SDIF_WDATA_Pos)       /*!< 0x00FFFFFF */
+#define DTS_TSCSDIF_CR_SDIF_WDATA                 DTS_TSCSDIF_CR_SDIF_WDATA_Msk                       /*!< SDIF write data */
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Pos              (24U)
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Msk              (0x7UL << DTS_TSCSDIF_CR_SDIF_ADDR_Pos)             /*!< 0x07000000 */
+#define DTS_TSCSDIF_CR_SDIF_ADDR                  DTS_TSCSDIF_CR_SDIF_ADDR_Msk                        /*!< SDIF register address */
+#define DTS_TSCSDIF_CR_SDIF_WRN_Pos               (27U)
+#define DTS_TSCSDIF_CR_SDIF_WRN_Msk               (0x1UL << DTS_TSCSDIF_CR_SDIF_WRN_Pos)              /*!< 0x08000000 */
+#define DTS_TSCSDIF_CR_SDIF_WRN                   DTS_TSCSDIF_CR_SDIF_WRN_Msk                         /*!< SDIF write no read control */
+#define DTS_TSCSDIF_CR_SDIF_PROG_Pos              (31U)
+#define DTS_TSCSDIF_CR_SDIF_PROG_Msk              (0x1UL << DTS_TSCSDIF_CR_SDIF_PROG_Pos)             /*!< 0x80000000 */
+#define DTS_TSCSDIF_CR_SDIF_PROG                  DTS_TSCSDIF_CR_SDIF_PROG_Msk                        /*!< SDIF program request */
+
+/*******************  Bit definition for DTS_TSCSDIFHALTR register  *****************/
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Pos            (0U)
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Msk            (0x1UL << DTS_TSCSDIFHALTR_SDIF_STOP_Pos)           /*!< 0x00000001 */
+#define DTS_TSCSDIFHALTR_SDIF_STOP                DTS_TSCSDIFHALTR_SDIF_STOP_Msk                      /*!< SDIF stop */
+
+/*******************  Bit definition for DTS_TSCSDIF_CFGR register  *****************/
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos         (0U)
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk         (0x3UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000003 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT             DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk                   /*!< SDIF programming inhibit */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_0           (0x1UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000001 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_1           (0x2UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000002 */
+
+/*******************  Bit definition for DTS_TSCSMPL_CR register  *****************/
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos       (0U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk       (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos)      /*!< 0x00000001 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE           DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk                 /*!< Sample counter disable */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos          (1U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk          (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos)         /*!< 0x00000002 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD              DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk                    /*!< Sample counter hold */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Pos           (2U)
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Msk           (0x1UL << DTS_TSCSMPL_CR_SMPL_DISCARD_Pos)          /*!< 0x00000004 */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD               DTS_TSCSMPL_CR_SMPL_DISCARD_Msk                     /*!< Sample discard */
+
+/*******************  Bit definition for DTS_TSCSDIFSMPLCLRR register  *****************/
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos  (0U)
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk  (0x1UL << DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR      DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk            /*!< Sample counter clear */
+
+/*******************  Bit definition for DTS_TSCSMPLCNTR register  *****************/
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Pos            (0U)
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Msk            (0xFFFFUL << DTS_TSCSMPLCNTR_SMPL_COUNT_Pos)        /*!< 0x0000FFFF */
+#define DTS_TSCSMPLCNTR_SMPL_COUNT                DTS_TSCSMPLCNTR_SMPL_COUNT_Msk                      /*!< Sample counter  */
+
+/*******************  Bit definition for DTS_TS_IER register  *****************/
+#define DTS_TS_IER_IRQ_EN_FAULT_Pos               (0U)
+#define DTS_TS_IER_IRQ_EN_FAULT_Msk               (0x1UL << DTS_TS_IER_IRQ_EN_FAULT_Pos)              /*!< 0x00000001 */
+#define DTS_TS_IER_IRQ_EN_FAULT                   DTS_TS_IER_IRQ_EN_FAULT_Msk                         /*!< TS Fault IRQ enable */
+#define DTS_TS_IER_IRQ_EN_DONE_Pos                (1U)
+#define DTS_TS_IER_IRQ_EN_DONE_Msk                (0x1UL << DTS_TS_IER_IRQ_EN_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_TS_IER_IRQ_EN_DONE                    DTS_TS_IER_IRQ_EN_DONE_Msk                          /*!< TS Sample done IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMA_Pos              (3U)
+#define DTS_TS_IER_IRQ_EN_ALARMA_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMA_Pos)             /*!< 0x00000008 */
+#define DTS_TS_IER_IRQ_EN_ALARMA                  DTS_TS_IER_IRQ_EN_ALARMA_Msk                        /*!< TS Alarm A IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMB_Pos              (4U)
+#define DTS_TS_IER_IRQ_EN_ALARMB_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMB_Pos)             /*!< 0x00000010 */
+#define DTS_TS_IER_IRQ_EN_ALARMB                  DTS_TS_IER_IRQ_EN_ALARMB_Msk                        /*!< TS Alarm B IRQ enable */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Pos           (0U)
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Msk           (0x1UL << DTS_TS_ISR_IRQ_STATUS_FAULT_Pos)          /*!< 0x00000001 */
+#define DTS_TS_ISR_IRQ_STATUS_FAULT               DTS_TS_ISR_IRQ_STATUS_FAULT_Msk                     /*!< TS Fault IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Pos            (1U)
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Msk            (0x1UL << DTS_TS_ISR_IRQ_STATUS_DONE_Pos)           /*!< 0x00000002 */
+#define DTS_TS_ISR_IRQ_STATUS_DONE                DTS_TS_ISR_IRQ_STATUS_DONE_Msk                      /*!< TS Sample done IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos          (3U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos)         /*!< 0x00000008 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA              DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk                    /*!< TS Alarm A IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos          (4U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos)         /*!< 0x00000010 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB              DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk                    /*!< TS Alarm B IRQ status */
+
+/*******************  Bit definition for DTS_TS_ICR register  *****************/
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos            (0U)
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk            (0x1UL << DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos)           /*!< 0x00000001 */
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT                DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk                      /*!< TS Fault IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Pos             (1U)
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Msk             (0x1UL << DTS_TS_ICR_IRQ_CLEAR_DONE_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE                 DTS_TS_ICR_IRQ_CLEAR_DONE_Msk                       /*!< TS Sample done IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos           (3U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos)          /*!< 0x00000008 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA               DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk                     /*!< TS Alarm A IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos           (4U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos)          /*!< 0x00000010 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB               DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk                     /*!< TS Alarm B IRQ clear */
+
+/*******************  Bit definition for DTS_TSIRQTESTR register  *****************/
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos         (0U)
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk         (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos)        /*!< 0x00000001 */
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT             DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk                   /*!< TS Fault IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos          (1U)
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk          (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos)         /*!< 0x00000002 */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE              DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk                    /*!< TS Sample done IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos        (3U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos)       /*!< 0x00000008 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA            DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk                  /*!< TS Alarm A IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos        (4U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos)       /*!< 0x00000010 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB            DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk                  /*!< TS Alarm B IRQ test */
+
+/*******************  Bit definition for DTS_TSSDIFRDATAR register  *****************/
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Pos           (0U)
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Msk           (0xFFFFFFUL << DTS_TSSDIFRDATAR_SDIF_RDATA_Pos)     /*!< 0x00FFFFFF */
+#define DTS_TSSDIFRDATAR_SDIF_RDATA               DTS_TSSDIFRDATAR_SDIF_RDATA_Msk                     /*!< TS SDIF read data */
+
+/*******************  Bit definition for DTS_TSSDIFDONER register  *****************/
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos        (0U)
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk        (0x1UL << DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos)       /*!< 0x00000001 */
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE            DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk                  /*!< TS Sample done flag */
+
+/*******************  Bit definition for DTS_TSSDIFDATAR register  *****************/
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Pos           (0U)
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Msk           (0xFFFFUL << DTS_TSSDIFDATAR_SAMPLE_DATA_Pos)       /*!< 0x0000FFFF */
+#define DTS_TSSDIFDATAR_SAMPLE_DATA               DTS_TSSDIFDATAR_SAMPLE_DATA_Msk                     /*!< TS Sample data */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos           (16U)
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk           (0x1UL << DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos)          /*!< 0x00010000 */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE               DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk                     /*!< TS Sample type */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos          (17U)
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk          (0x1UL << DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos)         /*!< 0x00020000 */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT              DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk                    /*!< TS Sample fault */
+
+/*******************  Bit definition for DTS_TSALARMA_CFGR register  *****************/
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos        (0U)
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk        (0xFFFFUL << DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH            DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk                  /*!< TS Alarm A hysteresis threshold */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos       (16U)
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk       (0xFFFFUL << DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH           DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk                 /*!< TS Alarm A threshold */
+
+/*******************  Bit definition for DTS_TSALARMB_CFGR register  *****************/
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos        (0U)
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk        (0xFFFFUL << DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH            DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk                  /*!< TS Alarm B hysteresis threshold */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos       (16U)
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk       (0xFFFFUL << DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH           DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk                 /*!< TS Alarm B threshold */
+
+/*******************  Bit definition for DTS_TSHLSAMPLER register  *****************/
+#define DTS_TSHLSAMPLER_SMPL_LO_Pos               (0U)
+#define DTS_TSHLSAMPLER_SMPL_LO_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_LO_Pos)           /*!< 0x0000FFFF */
+#define DTS_TSHLSAMPLER_SMPL_LO                   DTS_TSHLSAMPLER_SMPL_LO_Msk                         /*!< TS Lowest valid data sample value received */
+#define DTS_TSHLSAMPLER_SMPL_HI_Pos               (16U)
+#define DTS_TSHLSAMPLER_SMPL_HI_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_HI_Pos)           /*!< 0xFFFF0000 */
+#define DTS_TSHLSAMPLER_SMPL_HI                   DTS_TSHLSAMPLER_SMPL_HI_Msk                         /*!< TS Highest valid data sample value received */
+
+/*******************  Bit definition for DTS_TSHILORESETR register  *****************/
+#define DTS_TSHILORESETR_SMPL_LO_SET_Pos          (0U)
+#define DTS_TSHILORESETR_SMPL_LO_SET_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_LO_SET_Pos)         /*!< 0x00000001 */
+#define DTS_TSHILORESETR_SMPL_LO_SET              DTS_TSHILORESETR_SMPL_LO_SET_Msk                    /*!< TS Sample Low Set */
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Pos          (1U)
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_HI_CLR_Pos)         /*!< 0x00000002 */
+#define DTS_TSHILORESETR_SMPL_HI_CLR              DTS_TSHILORESETR_SMPL_HI_CLR_Msk                    /*!< TS Sample high clear 0 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              Ethernet MAC                                  */
+/*                                                                            */
+/******************************************************************************/
+/******  Bit definition for Ethernet MAC Configuration Register  **************/
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_PB_Pos                              (18U)
+#define ETH_MACCR_PB_Msk                              (0x1UL << ETH_MACCR_PB_Pos) /*!< 0x00040000 */
+#define ETH_MACCR_PB                                  ETH_MACCR_PB_Msk         /* Packet Burst Enable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_PS_Pos                              (15U)
+#define ETH_MACCR_PS_Msk                              (0x1UL << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
+#define ETH_MACCR_PS                                  ETH_MACCR_PS_Msk         /* Port Select */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* MAC speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/******  Bit definition for Ethernet MAC Extended Configuration Register  ***********/
+#define ETH_MACECR_APDIM_Pos                          (30U)
+#define ETH_MACECR_APDIM_Msk                          (0x1FUL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */
+#define ETH_MACECR_APDIM                              ETH_MACECR_APDIM_Msk      /* ARP Packet Drop if IP Address Mismatch */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/************  Bit definition for Ethernet MAC Packet Filter Register  ***************/
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/************  Bit definition for Ethernet MAC Watchdog Timeout Register  ***************/
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/************  Bit definition for Ethernet MAC Hash Table 0 register  ***************/
+#define ETH_MACHT0R_HTH_Pos                           (0U)
+#define ETH_MACHT0R_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT0R_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/************  Bit definition for Ethernet MAC Hash Table 1 register  ***************/
+#define ETH_MACHT1R_HTL_Pos                           (0U)
+#define ETH_MACHT1R_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT1R_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/************  Bit definition for Ethernet MAC VLAN tag Control register  ***************/
+#define ETH_MACVTCR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTCR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTCR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTCR_EIVLRXS                            ETH_MACVTCR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTCR_EIVLS_Pos                          (28U)
+#define ETH_MACVTCR_EIVLS_Msk                          (0x3UL << ETH_MACVTCR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS                              ETH_MACVTCR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS                  ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS                 ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP                  ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTCR_ERIVLT_Msk                         (0x1UL << ETH_MACVTCR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTCR_ERIVLT                             ETH_MACVTCR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTCR_EDVLP_Pos                          (26U)
+#define ETH_MACVTCR_EDVLP_Msk                          (0x1UL << ETH_MACVTCR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTCR_EDVLP                              ETH_MACVTCR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTCR_VTHM_Pos                           (25U)
+#define ETH_MACVTCR_VTHM_Msk                           (0x1UL << ETH_MACVTCR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTCR_VTHM                               ETH_MACVTCR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTCR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTCR_EVLRXS_Msk                         (0x1UL << ETH_MACVTCR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTCR_EVLRXS                             ETH_MACVTCR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTCR_EVLS_Pos                           (21U)
+#define ETH_MACVTCR_EVLS_Msk                           (0x3UL << ETH_MACVTCR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS                               ETH_MACVTCR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTCR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS                   ETH_MACVTCR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS                  ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP                   ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTCR_DOVLTC_Msk                         (0x1UL << ETH_MACVTCR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTCR_DOVLTC                             ETH_MACVTCR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTCR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTCR_ERSVLM_Msk                         (0x1UL << ETH_MACVTCR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTCR_ERSVLM                             ETH_MACVTCR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTCR_ESVL_Pos                           (18U)
+#define ETH_MACVTCR_ESVL_Msk                           (0x1UL << ETH_MACVTCR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTCR_ESVL                               ETH_MACVTCR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTCR_VTIM_Pos                           (17U)
+#define ETH_MACVTCR_VTIM_Msk                           (0x1UL << ETH_MACVTCR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTCR_VTIM                               ETH_MACVTCR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTCR_ETV_Pos                            (16U)
+#define ETH_MACVTCR_ETV_Msk                            (0x1UL << ETH_MACVTCR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTCR_ETV                                ETH_MACVTCR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTCR_OFS_Pos                            (2U)
+#define ETH_MACVTCR_OFS_Msk                            (0x3UL << ETH_MACVTCR_OFS_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS                                ETH_MACVTCR_EVLS_Msk      /* Offset */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER0             ((uint32_t)0x00000000)   /* holds MAC VLAN Tag Filter0 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos) /*!< 0x00000004 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk /* holds MAC VLAN Tag Filter1 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos         (3U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos) /*!< 0x00000008 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk /* holds MAC VLAN Tag Filter2 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk         (0x3UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk /* holds MAC VLAN Tag Filter3 content */
+#define ETH_MACVTCR_CT_Pos                             (1U)
+#define ETH_MACVTCR_CT_Msk                             (0x1UL << ETH_MACVTCR_CT_Pos) /*!< 0x00000002 */
+#define ETH_MACVTCR_CT                                 ETH_MACVTCR_CT_Msk       /* Command Type */
+#define ETH_MACVTCR_OB_Pos                             (0U)
+#define ETH_MACVTCR_OB_Msk                             (0x1UL << ETH_MACVTCR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACVTCR_OB                                 ETH_MACVTCR_OB_Msk       /* Operation Busy */
+
+/************  Bit definition for Ethernet MAC VLAN tag data register  ***************/
+#define ETH_MACVTDR_DMACHN_Pos                        (25U)
+#define ETH_MACVTDR_DMACHN_Msk                        (0x1UL << ETH_MACVTDR_DMACHN_Pos) /*!< 0x02000000 */
+#define ETH_MACVTDR_DMACHN                            ETH_MACVTDR_DMACHN_Msk   /* DMA Channel Number */
+#define ETH_MACVTDR_DMACHEN_Pos                       (24U)
+#define ETH_MACVTDR_DMACHEN_Msk                       (0x1UL << ETH_MACVTDR_DMACHEN_Pos) /*!< 0x01000000 */
+#define ETH_MACVTDR_DMACHEN                           ETH_MACVTDR_DMACHEN_Msk   /* DMA Channel Number Enable */
+#define ETH_MACVTDR_ERIVLT_Pos                        (20U)
+#define ETH_MACVTDR_ERIVLT_Msk                        (0x1UL << ETH_MACVTDR_ERIVLT_Pos) /*!< 0x00100000 */
+#define ETH_MACVTDR_ERIVLT                            ETH_MACVTDR_ERIVLT_Msk   /* Enable Inner VLAN Tag Comparison */
+#define ETH_MACVTDR_ERSVLM_Pos                        (19U)
+#define ETH_MACVTDR_ERSVLM_Msk                        (0x1UL << ETH_MACVTDR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_ERSVLM                            ETH_MACVTDR_ERSVLM_Msk   /* Enable S-VLAN Match for received Frames */
+#define ETH_MACVTDR_DOVLTC_Pos                        (18U)
+#define ETH_MACVTDR_DOVLTC_Msk                        (0x1UL << ETH_MACVTDR_DOVLTC_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_DOVLTC                            ETH_MACVTDR_DOVLTC_Msk   /* Disable VLAN Type Comparison */
+#define ETH_MACVTDR_ETV_Pos                           (17U)
+#define ETH_MACVTDR_ETV_Msk                           (0x1UL << ETH_MACVTDR_ETV_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV                               ETH_MACVTDR_ETV_Msk   /* 12-bit or 16-bit VLAN comparison */
+#define ETH_MACVTDR_ETV_VLAN16B                       ((uint32_t)0x00000000)   /* 16-bit VLAN */
+#define ETH_MACVTDR_ETV_VLAN12B_Pos                   (17U)
+#define ETH_MACVTDR_ETV_VLAN12B_Msk                   (0x1UL << ETH_MACVTDR_ETV_VLAN12B_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV_VLAN12B                       ETH_MACVTDR_ETV_VLAN12B_Msk   /* 12-bit VLAN */
+#define ETH_MACVTDR_VEN_Pos                           (16U)
+#define ETH_MACVTDR_VEN_Msk                           (0x1UL << ETH_MACVTDR_VEN_Pos) /*!< 0x00010000 */
+#define ETH_MACVTDR_VEN                               ETH_MACVTDR_VEN_Msk   /* VLAN Tag Enable */
+#define ETH_MACVTDR_VID_Pos                           (0U)
+#define ETH_MACVTDR_VID_Msk                           (0xFFFFUL << ETH_MACVTDR_VID_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID                               ETH_MACVTDR_VID_Msk        /* VLAN Tag ID */
+#define ETH_MACVTDR_VID_12BIT_Msk                     (0xFFFU << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000FFF */
+#define ETH_MACVTDR_VID_12BIT                         ETH_MACVTDR_VID_12BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 12bit */
+#define ETH_MACVTDR_VID_16BIT_Msk                     (0xFFFFU << ETH_MACVTDR_VID_Pos)                    /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID_16BIT                         ETH_MACVTDR_VID_16BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 16bit */
+#define ETH_MACVTDR_VID_0                             (0x1U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000001 */
+#define ETH_MACVTDR_VID_1                             (0x2U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000002 */
+#define ETH_MACVTDR_VID_2                             (0x4U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000004 */
+#define ETH_MACVTDR_VID_3                             (0x8U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000008 */
+#define ETH_MACVTDR_VID_4                             (0x10U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000010 */
+#define ETH_MACVTDR_VID_5                             (0x20U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000020 */
+#define ETH_MACVTDR_VID_6                             (0x40U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000040 */
+#define ETH_MACVTDR_VID_7                             (0x80U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000080 */
+#define ETH_MACVTDR_VID_8                             (0x100U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000100 */
+#define ETH_MACVTDR_VID_9                             (0x200U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000200 */
+#define ETH_MACVTDR_VID_10                            (0x400U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000400 */
+#define ETH_MACVTDR_VID_11                            (0x800U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000800 */
+#define ETH_MACVTDR_VID_12                            (0x1000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00001000 */
+#define ETH_MACVTDR_VID_13                            (0x2000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00002000 */
+#define ETH_MACVTDR_VID_14                            (0x4000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00004000 */
+#define ETH_MACVTDR_VID_15                            (0x8000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00008000 */
+
+/************  Bit definition for Ethernet MAC VLAN Hash Table Register  ***************/
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/************  Bit definition for Ethernet MAC VLAN inclusion Register  ***************/
+#define ETH_MACVIR_BUSY_Pos                           (31U)
+#define ETH_MACVIR_BUSY_Msk                           (0x1UL << ETH_MACVIR_BUSY_Pos) /*!< 0x80000000 */
+#define ETH_MACVIR_BUSY                               ETH_MACVIR_BUSY_Msk      /* Busy */
+#define ETH_MACVIR_RDWR_Pos                           (30U)
+#define ETH_MACVIR_RDWR_Msk                           (0x1UL << ETH_MACVIR_RDWR_Pos) /*!< 0x40000000 */
+#define ETH_MACVIR_RDWR                               ETH_MACVIR_RDWR_Msk      /* Read write control */
+#define ETH_MACVIR_ADDR_Pos                           (24U)
+#define ETH_MACVIR_ADDR_Msk                           (0x1UL << ETH_MACVIR_ADDR_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR                               ETH_MACVIR_ADDR_Msk      /* Address */
+#define ETH_MACVIR_ADDR_VLANINSTXQ0                   ((uint32_t)0x00000000)   /* VLAN tag for insertion in the Transmit packets from Tx Queue 0 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Pos               (24U)
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Msk               (0x1UL << ETH_MACVIR_ADDR_VLANINSTXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1                   ETH_MACVIR_ADDR_VLANINSTXQ1_Msk   /* VLAN tag for insertion in the Transmit packets from Tx Queue 1 */
+#define ETH_MACVIR_CBTI_Pos                           (21U)
+#define ETH_MACVIR_CBTI_Msk                           (0x1UL << ETH_MACVIR_CBTI_Pos) /*!< 0x00200000 */
+#define ETH_MACVIR_CBTI                               ETH_MACVIR_CBTI_Msk      /* Channel based tag insertion */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Inner_VLAN Incl Register   ***************/
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Tx Queue 0 flow control Register   ***************/
+#define ETH_MACQ0TXFCR_PT_Pos                         (16U)
+#define ETH_MACQ0TXFCR_PT_Msk                         (0xFFFFUL << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACQ0TXFCR_PT                             ETH_MACQ0TXFCR_PT_Msk       /* Pause Time */
+#define ETH_MACQ0TXFCR_DZPQ_Pos                       (7U)
+#define ETH_MACQ0TXFCR_DZPQ_Msk                       (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACQ0TXFCR_DZPQ                           ETH_MACQ0TXFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACQ0TXFCR_PLT_Pos                        (4U)
+#define ETH_MACQ0TXFCR_PLT_Msk                        (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACQ0TXFCR_PLT                            ETH_MACQ0TXFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACQ0TXFCR_PLT_MINUS4                     ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Pos                (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACQ0TXFCR_PLT_MINUS28                    ETH_MACQ0TXFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Pos                (5U)
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACQ0TXFCR_PLT_MINUS36                    ETH_MACQ0TXFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Msk               (0x3UL << ETH_MACQ0TXFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACQ0TXFCR_PLT_MINUS144                   ETH_MACQ0TXFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Pos               (6U)
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Msk               (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACQ0TXFCR_PLT_MINUS256                   ETH_MACQ0TXFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Msk               (0x5UL << ETH_MACQ0TXFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACQ0TXFCR_PLT_MINUS512                   ETH_MACQ0TXFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACQ0TXFCR_TFE_Pos                        (1U)
+#define ETH_MACQ0TXFCR_TFE_Msk                        (0x1UL << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACQ0TXFCR_TFE                            ETH_MACQ0TXFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACQ0TXFCR_FCB_Pos                        (0U)
+#define ETH_MACQ0TXFCR_FCB_Msk                        (0x1UL << ETH_MACQ0TXFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACQ0TXFCR_FCB                            ETH_MACQ0TXFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/************ Bit definition for Ethernet MAC Rx flow control Register   ***************/
+#define ETH_MACRXFCR_UP_Pos                            (1U)
+#define ETH_MACRXFCR_UP_Msk                            (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRXFCR_UP                                ETH_MACRXFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRXFCR_RFE_Pos                           (0U)
+#define ETH_MACRXFCR_RFE_Msk                           (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXFCR_RFE                               ETH_MACRXFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/************ Bit definition for Ethernet MAC Rx Queue control Register  ***************/
+#define ETH_MACRXQCR_VFFQ_Pos                         (17U)
+#define ETH_MACRXQCR_VFFQ_Msk                         (0x1UL << ETH_MACRXQCR_VFFQ_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ                             ETH_MACRXQCR_VFFQ_Msk       /* VLAN Tag Filter Fail Packets Queue */
+#define ETH_MACRXQCR_VFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_VFFQ_Q1_Pos                      (17U)
+#define ETH_MACRXQCR_VFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_VFFQ_Q1_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ_Q1                          ETH_MACRXQCR_VFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_VFFQE_Pos                        (16U)
+#define ETH_MACRXQCR_VFFQE_Msk                        (0x1UL << ETH_MACRXQCR_VFFQE_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQCR_VFFQE                            ETH_MACRXQCR_VFFQE_Msk       /* VLAN Tag Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_MFFQ_Pos                         (9U)
+#define ETH_MACRXQCR_MFFQ_Msk                         (0x1UL << ETH_MACRXQCR_MFFQ_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ                             ETH_MACRXQCR_MFFQ_Msk       /* Multicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_MFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_MFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_MFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_MFFQ_Q1_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ_Q1                          ETH_MACRXQCR_MFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_MFFQE_Pos                        (8U)
+#define ETH_MACRXQCR_MFFQE_Msk                        (0x1UL << ETH_MACRXQCR_MFFQE_Pos) /*!< 0x00000100 */
+#define ETH_MACRXQCR_MFFQE                            ETH_MACRXQCR_MFFQE_Msk       /* Multicast Address Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_UFFQ_Pos                         (1U)
+#define ETH_MACRXQCR_UFFQ_Msk                         (0x1UL << ETH_MACRXQCR_UFFQ_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ                             ETH_MACRXQCR_UFFQ_Msk       /* Unicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_UFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_UFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_UFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_UFFQ_Q1_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ_Q1                          ETH_MACRXQCR_UFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_UFFQE_Pos                        (0U)
+#define ETH_MACRXQCR_UFFQE_Msk                        (0x1UL << ETH_MACRXQCR_UFFQE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQCR_UFFQE                            ETH_MACRXQCR_UFFQE_Msk       /* Unicast Address Filter Fail Packets Queuing Enable */
+
+/************ Bit definition for Ethernet MAC Rx queue control 0 Register   ***************/
+#define ETH_MACRXQC0R_RXQ1EN_Pos                      (2U)
+#define ETH_MACRXQC0R_RXQ1EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
+#define ETH_MACRXQC0R_RXQ1EN                          ETH_MACRXQC0R_RXQ1EN_Msk       /* Receive Queue 1 Enable */
+#define ETH_MACRXQC0R_RXQ1EN_NOT                      ((uint32_t)0x00000000)        /* Queue 1 Not enabled */
+#define ETH_MACRXQC0R_RXQ1EN_AV_Pos                   (2U)
+#define ETH_MACRXQC0R_RXQ1EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_AV_Pos) /*!< 0x00000004 */
+#define ETH_MACRXQC0R_RXQ1EN_AV                       ETH_MACRXQC0R_RXQ1EN_AV_Msk   /* Queue 1 enabled for AV */
+#define ETH_MACRXQC0R_RXQ1EN_GT_Pos                   (3U)
+#define ETH_MACRXQC0R_RXQ1EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_GT_Pos) /*!< 0x00000008 */
+#define ETH_MACRXQC0R_RXQ1EN_GT                       ETH_MACRXQC0R_RXQ1EN_GT_Msk   /* Queue 1 enabled for Generic traffic */
+#define ETH_MACRXQC0R_RXQ0EN_Pos                      (0U)
+#define ETH_MACRXQC0R_RXQ0EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
+#define ETH_MACRXQC0R_RXQ0EN                          ETH_MACRXQC0R_RXQ0EN_Msk       /* Receive Queue 0 Enable */
+#define ETH_MACRXQC0R_RXQ0EN_NOT                      ((uint32_t)0x00000000)        /* Queue 0 Not enabled */
+#define ETH_MACRXQC0R_RXQ0EN_AV_Pos                   (0U)
+#define ETH_MACRXQC0R_RXQ0EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_AV_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC0R_RXQ0EN_AV                       ETH_MACRXQC0R_RXQ0EN_AV_Msk   /* Queue 0 enabled for AV */
+#define ETH_MACRXQC0R_RXQ0EN_GT_Pos                   (1U)
+#define ETH_MACRXQC0R_RXQ0EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_GT_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQC0R_RXQ0EN_GT                       ETH_MACRXQC0R_RXQ0EN_GT_Msk   /* Queue 0 enabled for Generic traffic */
+
+/************ Bit definition for Ethernet MAC Rx queue control 1 Register   ***************/
+#define ETH_MACRXQC1R_TBRQE_Pos                       (29U)
+#define ETH_MACRXQC1R_TBRQE_Msk                       (0x1UL << ETH_MACRXQC1R_TBRQE_Pos) /*!< 0x20000000 */
+#define ETH_MACRXQC1R_TBRQE                           ETH_MACRXQC1R_TBRQE_Msk       /* Type Field Based Rx Queuing Enable */
+#define ETH_MACRXQC1R_OMCBCQ_Pos                      (28U)
+#define ETH_MACRXQC1R_OMCBCQ_Msk                      (0x1UL << ETH_MACRXQC1R_OMCBCQ_Pos) /*!< 0x10000000 */
+#define ETH_MACRXQC1R_OMCBCQ                          ETH_MACRXQC1R_OMCBCQ_Msk       /* Overriding MC-BC queue priority select */
+#define ETH_MACRXQC1R_FPRQ_Pos                        (24U)
+#define ETH_MACRXQC1R_FPRQ_Msk                        (0x7UL << ETH_MACRXQC1R_FPRQ_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_FPRQ                            ETH_MACRXQC1R_FPRQ_Msk       /* Frame Preemption Residue Queue */
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Pos                   (24U)
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_FPRQ_RXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACRXQC1R_FPRQ_RXQ1                       ETH_MACRXQC1R_FPRQ_RXQ1_Msk       /* Rx queue 1 */
+#define ETH_MACRXQC1R_TPQC_Pos                        (22U)
+#define ETH_MACRXQC1R_TPQC_Msk                        (0x3UL << ETH_MACRXQC1R_TPQC_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_TPQC                            ETH_MACRXQC1R_TPQC_Msk   /* Tagged PTP over Ethernet Packets Queuing Control */
+#define ETH_MACRXQC1R_TPQC_PTPGENVLANTAG              ((uint32_t)0x00000000)   /* VLAN tagged PTPoE packets are routed as generic VLAN tagged packet */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos             (22U)
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk             (0x1UL << ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos) /*!< 0x000400000 */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ                 ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk /* VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos           (23U)
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk           (0x1UL << ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos) /*!< 0x00080000 */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ               ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk /* VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ */
+#define ETH_MACRXQC1R_TACPQE_Pos                      (21U)
+#define ETH_MACRXQC1R_TACPQE_Msk                      (0x1UL << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
+#define ETH_MACRXQC1R_TACPQE                          ETH_MACRXQC1R_TACPQE_Msk       /* Tagged AV Control Packets Queuing Enable */
+#define ETH_MACRXQC1R_MCBCQEN_Pos                     (20U)
+#define ETH_MACRXQC1R_MCBCQEN_Msk                     (0x1UL << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
+#define ETH_MACRXQC1R_MCBCQEN                         ETH_MACRXQC1R_MCBCQEN_Msk     /* Multicast and Broadcast Queue Enable */
+#define ETH_MACRXQC1R_MCBCQ_Pos                       (16U)
+#define ETH_MACRXQC1R_MCBCQ_Msk                       (0x7UL << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
+#define ETH_MACRXQC1R_MCBCQ                           ETH_MACRXQC1R_MCBCQ_Msk       /* Multicast and Broadcast Queue */
+#define ETH_MACRXQC1R_MCBCQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Pos                  (16U)
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_MCBCQ_RXQ1_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1                      ETH_MACRXQC1R_MCBCQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_UPQ_Pos                         (12U)
+#define ETH_MACRXQC1R_UPQ_Msk                         (0x7UL << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
+#define ETH_MACRXQC1R_UPQ                             ETH_MACRXQC1R_UPQ_Msk       /* Untagged Packet Queue */
+#define ETH_MACRXQC1R_UPQ_RXQ0                        ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_UPQ_RXQ1_Pos                    (12U)
+#define ETH_MACRXQC1R_UPQ_RXQ1_Msk                    (0x1UL << ETH_MACRXQC1R_UPQ_RXQ1_Pos) /*!< 0x00001000 */
+#define ETH_MACRXQC1R_UPQ_RXQ1                        ETH_MACRXQC1R_UPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_PTPQ_Pos                        (4U)
+#define ETH_MACRXQC1R_PTPQ_Msk                        (0x7UL << ETH_MACRXQC1R_PTPQ_Pos) /*!< 0x00000070 */
+#define ETH_MACRXQC1R_PTPQ                            ETH_MACRXQC1R_PTPQ_Msk       /* PTP Packets Queue */
+#define ETH_MACRXQC1R_PTPQ_RXQ0                       ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Pos                   (4U)
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_PTPQ_RXQ1_Pos) /*!< 0x00000010 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1                       ETH_MACRXQC1R_PTPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_AVCPQ_Pos                       (0U)
+#define ETH_MACRXQC1R_AVCPQ_Msk                       (0x7UL << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
+#define ETH_MACRXQC1R_AVCPQ                           ETH_MACRXQC1R_AVCPQ_Msk       /* AV Untagged Control Packets Queue */
+#define ETH_MACRXQC1R_AVCPQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Pos                  (0U)
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_AVCPQ_RXQ1_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1                      ETH_MACRXQC1R_AVCPQ_RXQ1_Msk  /* Rx queue 1 */
+
+/************ Bit definition for Ethernet MAC Rx queue control 2 Register   ***************/
+#define ETH_MACRXQC2R_PSRQ1_Pos                       (8U)
+#define ETH_MACRXQC2R_PSRQ1_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
+#define ETH_MACRXQC2R_PSRQ1                           ETH_MACRXQC2R_PSRQ1_Msk       /* Priorities Selected in the Receive Queue 1 */
+#define ETH_MACRXQC2R_PSRQ0_Pos                       (0U)
+#define ETH_MACRXQC2R_PSRQ0_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
+#define ETH_MACRXQC2R_PSRQ0                           ETH_MACRXQC2R_PSRQ0_Msk       /* Priorities Selected in the Receive Queue 0 */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MFRIS_Pos                          (20U)
+#define ETH_MACISR_MFRIS_Msk                          (0x1UL << ETH_MACISR_MFRIS_Pos) /*!< 0x00100000 */
+#define ETH_MACISR_MFRIS                              ETH_MACISR_MFRIS_Msk   /* MMC FPE Receive Interrupt Status */
+#define ETH_MACISR_MFTIS_Pos                          (19U)
+#define ETH_MACISR_MFTIS_Msk                          (0x1UL << ETH_MACISR_MFTIS_Pos) /*!< 0x00080000 */
+#define ETH_MACISR_MFTIS                              ETH_MACISR_MFTIS_Msk   /* MMC FPE Transmit Interrupt Status */
+#define ETH_MACISR_MDIOIS_Pos                         (18U)
+#define ETH_MACISR_MDIOIS_Msk                         (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIS                             ETH_MACISR_MDIOIS_Msk   /* MDIO Interrupt Status*/
+#define ETH_MACISR_FPEIS_Pos                          (17U)
+#define ETH_MACISR_FPEIS_Msk                          (0x1UL << ETH_MACISR_FPEIS_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIS                              ETH_MACISR_FPEIS_Msk   /* Frame Preemption Interrupt Status */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+#define ETH_MACISR_RGSMIIIS_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIS_Msk                       (0x1UL << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIS                           ETH_MACISR_RGSMIIIS_Msk     /* RGMII Interrupt Status */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MDIOIE_Pos                         (18U)
+#define ETH_MACISR_MDIOIE_Msk                         (0x1UL << ETH_MACISR_MDIOIE_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIE                             ETH_MACISR_MDIOIE_Msk   /* Receive Interrupt Enable*/
+#define ETH_MACISR_FPEIE_Pos                          (17U)
+#define ETH_MACISR_FPEIE_Msk                          (0x1UL << ETH_MACISR_FPEIE_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIE                              ETH_MACISR_FPEIE_Msk   /* Frame Preemption Interrupt Enable */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+#define ETH_MACISR_RGSMIIIE_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIE_Msk                       (0x1UL << ETH_MACISR_RGSMIIIE_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIE                           ETH_MACISR_RGSMIIIE_Msk     /* RGMII Interrupt Enable */
+
+/************ Bit definition for Ethernet MAC Rx Tx Status Register   ***************/
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/************ Bit definition for Ethernet MAC PMT Control Status Register   ***************/
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/************ Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register   ***************/
+#define ETH_MACRWKPFR_MACRWKPFR_Pos                   (0U)
+#define ETH_MACRWKPFR_MACRWKPFR_Msk                   (0xFFFFFFFFUL << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWKPFR_MACRWKPFR                       ETH_MACRWKPFR_MACRWKPFR_Msk  /* Wake-up Packet filter register data */
+
+/************ Bit definition for Ethernet MAC LPI Control Status Register   ***************/
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLSEN_Pos                         (18U)
+#define ETH_MACLCSR_PLSEN_Msk                         (0x1UL << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
+#define ETH_MACLCSR_PLSEN                             ETH_MACLCSR_PLSEN_Msk      /* PHY Link Status Enable */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/************ Bit definition for Ethernet MAC LPI Timers Control Register   ***************/
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/************ Bit definition for Ethernet MAC LPI Entry Timer Register   ***************/
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/************ Bit definition for Ethernet MAC 1US Tic Counter Register   ***************/
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/************ Bit definition for Ethernet MAC PHYIF control status Register   ***************/
+#define ETH_MACPHYCSR_LNKSTS_Pos                      (19U)
+#define ETH_MACPHYCSR_LNKSTS_Msk                      (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS                          ETH_MACPHYCSR_LNKSTS_Msk  /* Link Status */
+#define ETH_MACPHYCSR_LNKSTS_LD                       ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LNKSTS_LU_Pos                   (19U)
+#define ETH_MACPHYCSR_LNKSTS_LU_Msk                   (0x1UL << ETH_MACPHYCSR_LNKSTS_LU_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS_LU                       ETH_MACPHYCSR_LNKSTS_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_LNKSPEED_Pos                    (17U)
+#define ETH_MACPHYCSR_LNKSPEED_Msk                    (0x3UL << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
+#define ETH_MACPHYCSR_LNKSPEED                        ETH_MACPHYCSR_LNKSPEED_Msk  /* Link Speed */
+#define ETH_MACPHYCSR_LNKSPEED_2_5MHZ                 ((uint32_t)0x00000000)    /* 2.5 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos              (17U)
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk              (0x1UL << ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos) /*!< 0x00020000 */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ                  ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk   /* 25 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos             (18U)
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk             (0x1UL << ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos) /*!< 0x00040000 */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ                 ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk  /* 125 MHz */
+#define ETH_MACPHYCSR_LNKMOD_Pos                      (16U)
+#define ETH_MACPHYCSR_LNKMOD_Msk                      (0x1UL << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKMOD                          ETH_MACPHYCSR_LNKMOD_Msk  /* Link Mode */
+#define ETH_MACPHYCSR_LNKMOD_HD                       ((uint32_t)0x00000000)    /* Half-duplex mode */
+#define ETH_MACPHYCSR_LNKMOD_FD_Pos                   (16U)
+#define ETH_MACPHYCSR_LNKMOD_FD_Msk                   (0x1UL << ETH_MACPHYCSR_LNKMOD_FD_Pos) /*!< 0x00010000 */
+#define ETH_MACPHYCSR_LNKMOD_FD                       ETH_MACPHYCSR_LNKMOD_FD_Msk  /* Full-duplex mode */
+#define ETH_MACPHYCSR_LUD_Pos                         (1U)
+#define ETH_MACPHYCSR_LUD_Msk                         (0x1UL << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD                             ETH_MACPHYCSR_LUD_Msk  /* Link Up or Down */
+#define ETH_MACPHYCSR_LUD_LD                          ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LUD_LU_Pos                      (1U)
+#define ETH_MACPHYCSR_LUD_LU_Msk                      (0x1UL << ETH_MACPHYCSR_LUD_LU_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD_LU                          ETH_MACPHYCSR_LUD_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_TC_Pos                          (0U)
+#define ETH_MACPHYCSR_TC_Msk                          (0x1UL << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
+#define ETH_MACPHYCSR_TC                              ETH_MACPHYCSR_TC_Msk  /* Transmit Configuration in RGMII */
+
+/************ Bit definition for Ethernet MAC Version Register   ***************/
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/************ Bit definition for Ethernet MAC Debug Register   ***************/
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/************ Bit definition for Ethernet MAC HW Feature 0 Register   ***************/
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos              (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII                  ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk /* RGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos              (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII                  ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Pos                (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Msk                (0x3UL << ETH_MACHWF0R_ACTPHYSEL_TBI_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI                    ETH_MACHWF0R_ACTPHYSEL_TBI_Msk /* TBI */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos               (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk               (0x5UL << ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos) /*!< 0x50000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI                   ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk /* RTBI */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Pos               (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Msk               (0x3UL << ETH_MACHWF0R_ACTPHYSEL_SMII_Pos) /*!< 0x60000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII                   ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/************ Bit definition for Ethernet MAC HW Feature 1 Register   ***************/
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_HASHTBLSZ_NOHASH                 ((uint32_t)0x00000000)   /* No Hash table */
+#define ETH_MACHWF1R_HASHTBLSZ_64_Pos                 (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_64_Msk                 (0x1UL << ETH_MACHWF1R_HASHTBLSZ_64_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_64                     ETH_MACHWF1R_HASHTBLSZ_64_Msk /* 64 */
+#define ETH_MACHWF1R_HASHTBLSZ_128_Pos                (25U)
+#define ETH_MACHWF1R_HASHTBLSZ_128_Msk                (0x1UL << ETH_MACHWF1R_HASHTBLSZ_128_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_128                    ETH_MACHWF1R_HASHTBLSZ_128_Msk /* 128 */
+#define ETH_MACHWF1R_HASHTBLSZ_256_Pos                (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_256_Msk                (0x3UL << ETH_MACHWF1R_HASHTBLSZ_256_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_256                    ETH_MACHWF1R_HASHTBLSZ_256_Msk /* 256 */
+#define ETH_MACHWF1R_POUOST_Pos                       (23U)
+#define ETH_MACHWF1R_POUOST_Msk                       (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_POUOST                           ETH_MACHWF1R_POUOST_Msk   /* One Step for PTP over UDP/IP Feature Enable */
+#define ETH_MACHWF1R_RAVSEL_Pos                       (21U)
+#define ETH_MACHWF1R_RAVSEL_Msk                       (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_RAVSEL                           ETH_MACHWF1R_RAVSEL_Msk   /* Rx Side Only AV Feature Enable */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_SPRAM_Pos                        (5U)
+#define ETH_MACHWF1R_SPRAM_Msk                        (0x1FUL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF1R_SPRAM                            ETH_MACHWF1R_SPRAM_Msk /* MTL Receive FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/************ Bit definition for Ethernet MAC HW Feature 2 Register   ***************/
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TDCSZ_Pos                        (22U)
+#define ETH_MACHWF2R_TDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_TDCSZ                            ETH_MACHWF2R_TDCSZ_Msk /* Tx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_TXCHCNT_1DMATXCH                 ((uint32_t)0x00000000) /* 1 DMA Tx Channel */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos             (18U)
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk             (0x1UL << ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH                 ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk  /* 2 DMA Tx Channels */
+#define ETH_MACHWF2R_RDCSZ_Pos                        (16U)
+#define ETH_MACHWF2R_RDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_RDCSZ                            ETH_MACHWF2R_RDCSZ_Msk /* Rx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (12U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_RXCHCNT_1DMARXCH                 ((uint32_t)0x00000000) /* 1 DMA Rx Channel */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos             (12U)
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk             (0x1UL << ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH                 ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk  /* 2 DMA Rx Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_TXQCNT_1MTLTXQ                   ((uint32_t)0x00000000) /* 1 MTL Tx queue */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos               (6U)
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk               (0x1UL << ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ                   ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk  /* 2 MTL Tx queue */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+#define ETH_MACHWF2R_RXQCNT_1MTLRXQ                   ((uint32_t)0x00000000) /* 1 MTL Rx queue */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos               (0U)
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk               (0x1UL << ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ                   ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk  /* 2 MTL Rx queue */
+
+/************ Bit definition for Ethernet MAC HW Feature 3 Register    ***************/
+#define ETH_MACHWF3R_ASP_Pos                          (28U)
+#define ETH_MACHWF3R_ASP_Msk                          (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP                              ETH_MACHWF3R_ASP_Msk /* Automotive Safety Package */
+#define ETH_MACHWF3R_ASP_NONE                         ((uint32_t)0x00000000) /* None */
+#define ETH_MACHWF3R_ASP_ECC_Pos                      (28U)
+#define ETH_MACHWF3R_ASP_ECC_Msk                      (0x1UL << ETH_MACHWF3R_ASP_ECC_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF3R_ASP_ECC                          ETH_MACHWF3R_ASP_ECC_Msk  /* ECC only */
+#define ETH_MACHWF3R_ASP_ASNPPE_Pos                   (29U)
+#define ETH_MACHWF3R_ASP_ASNPPE_Msk                   (0x1UL << ETH_MACHWF3R_ASP_ASNPPE_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF3R_ASP_ASNPPE                       ETH_MACHWF3R_ASP_ASNPPE_Msk  /* AS_NPPE */
+#define ETH_MACHWF3R_ASP_ASPPE_Pos                    (28U)
+#define ETH_MACHWF3R_ASP_ASPPE_Msk                    (0x3UL << ETH_MACHWF3R_ASP_ASPPE_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP_ASPPE                        ETH_MACHWF3R_ASP_ASPPE_Msk  /* AS_PPE */
+#define ETH_MACHWF3R_TBSSEL_Pos                       (27U)
+#define ETH_MACHWF3R_TBSSEL_Msk                       (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF3R_TBSSEL                           ETH_MACHWF3R_TBSSEL_Msk /* Time-based scheduling Enable */
+#define ETH_MACHWF3R_FPESEL_Pos                       (26U)
+#define ETH_MACHWF3R_FPESEL_Msk                       (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF3R_FPESEL                           ETH_MACHWF3R_FPESEL_Msk /* Frame Preemption Enable */
+#define ETH_MACHWF3R_ESTWID_Pos                       (20U)
+#define ETH_MACHWF3R_ESTWID_Msk                       (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID                           ETH_MACHWF3R_ESTWID_Msk /* Width of the Time Interval field in the Gate Control List */
+#define ETH_MACHWF3R_ESTWID_NOWIDTH                   ((uint32_t)0x00000000) /* No Width */
+#define ETH_MACHWF3R_ESTWID_16_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_16_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_16_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF3R_ESTWID_16                        ETH_MACHWF3R_ESTWID_16_Msk  /* 16 Width */
+#define ETH_MACHWF3R_ESTWID_20_Pos                    (21U)
+#define ETH_MACHWF3R_ESTWID_20_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_20_Pos) /*!< 0x00200000 */
+#define ETH_MACHWF3R_ESTWID_20                        ETH_MACHWF3R_ESTWID_20_Msk  /* 20 Width */
+#define ETH_MACHWF3R_ESTWID_24_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_24_Msk                    (0x3UL << ETH_MACHWF3R_ESTWID_24_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID_24                        ETH_MACHWF3R_ESTWID_24_Msk  /* 24 Width */
+#define ETH_MACHWF3R_ESTDEP_Pos                       (17U)
+#define ETH_MACHWF3R_ESTDEP_Msk                       (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */
+#define ETH_MACHWF3R_ESTDEP                           ETH_MACHWF3R_ESTDEP_Msk /* Depth of the Gate Control List */
+#define ETH_MACHWF3R_ESTDEP_NODEPTH                   ((uint32_t)0x00000000) /* No depth */
+#define ETH_MACHWF3R_ESTDEP_64_Pos                    (17U)
+#define ETH_MACHWF3R_ESTDEP_64_Msk                    (0x1UL << ETH_MACHWF3R_ESTDEP_64_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF3R_ESTDEP_64                        ETH_MACHWF3R_ESTDEP_64_Msk  /* 64 depth */
+#define ETH_MACHWF3R_ESTDEP_128_Pos                   (18U)
+#define ETH_MACHWF3R_ESTDEP_128_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_128_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF3R_ESTDEP_128                       ETH_MACHWF3R_ESTDEP_128_Msk  /* 128 depth */
+#define ETH_MACHWF3R_ESTDEP_256_Pos                   (17U)
+#define ETH_MACHWF3R_ESTDEP_256_Msk                   (0x3UL << ETH_MACHWF3R_ESTDEP_256_Pos) /*!< 0x00060000 */
+#define ETH_MACHWF3R_ESTDEP_256                       ETH_MACHWF3R_ESTDEP_256_Msk  /* 256 depth */
+#define ETH_MACHWF3R_ESTDEP_512_Pos                   (19U)
+#define ETH_MACHWF3R_ESTDEP_512_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_512_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF3R_ESTDEP_512                       ETH_MACHWF3R_ESTDEP_512_Msk  /* 512 depth */
+#define ETH_MACHWF3R_ESTDEP_1024_Pos                  (17U)
+#define ETH_MACHWF3R_ESTDEP_1024_Msk                  (0x5UL << ETH_MACHWF3R_ESTDEP_1024_Pos) /*!< 0x000A0000 */
+#define ETH_MACHWF3R_ESTDEP_1024                      ETH_MACHWF3R_ESTDEP_1024_Msk  /* 1024 depth */
+#define ETH_MACHWF3R_ESTSEL_Pos                       (16U)
+#define ETH_MACHWF3R_ESTSEL_Msk                       (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF3R_ESTSEL                           ETH_MACHWF3R_ESTSEL_Msk  /* Enhancements to Scheduled Traffic Enable */
+#define ETH_MACHWF3R_FRPES_Pos                        (13U)
+#define ETH_MACHWF3R_FRPES_Msk                        (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */
+#define ETH_MACHWF3R_FRPES                            ETH_MACHWF3R_FRPES_Msk  /* Flexible Receive Parser Table Entries size */
+#define ETH_MACHWF3R_FRPES_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPES_128_Pos                    (13U)
+#define ETH_MACHWF3R_FRPES_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_128_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF3R_FRPES_128                        ETH_MACHWF3R_FRPES_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPES_256_Pos                    (14U)
+#define ETH_MACHWF3R_FRPES_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_256_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF3R_FRPES_256                        ETH_MACHWF3R_FRPES_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPBS_Pos                        (11U)
+#define ETH_MACHWF3R_FRPBS_Msk                        (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */
+#define ETH_MACHWF3R_FRPBS                            ETH_MACHWF3R_FRPBS_Msk  /* Flexible Receive Parser Buffer size */
+#define ETH_MACHWF3R_FRPBS_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPBS_128_Pos                    (11U)
+#define ETH_MACHWF3R_FRPBS_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_128_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF3R_FRPBS_128                        ETH_MACHWF3R_FRPBS_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPBS_256_Pos                    (12U)
+#define ETH_MACHWF3R_FRPBS_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_256_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF3R_FRPBS_256                        ETH_MACHWF3R_FRPBS_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPSEL_Pos                       (10U)
+#define ETH_MACHWF3R_FRPSEL_Msk                       (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */
+#define ETH_MACHWF3R_FRPSEL                           ETH_MACHWF3R_FRPSEL_Msk  /* Flexible Receive Parser Selected */
+#define ETH_MACHWF3R_PDUPSEL_Pos                      (9U)
+#define ETH_MACHWF3R_PDUPSEL_Msk                      (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF3R_PDUPSEL                          ETH_MACHWF3R_PDUPSEL_Msk  /* Broadcast/Multicast Packet Duplication */
+#define ETH_MACHWF3R_DVLAN_Pos                        (5U)
+#define ETH_MACHWF3R_DVLAN_Msk                        (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF3R_DVLAN                            ETH_MACHWF3R_DVLAN_Msk  /* Double VLAN processing enable */
+#define ETH_MACHWF3R_CBTISEL_Pos                      (4U)
+#define ETH_MACHWF3R_CBTISEL_Msk                      (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF3R_CBTISEL                          ETH_MACHWF3R_CBTISEL_Msk  /* Queue/Channel based VLAN tag insertion on Tx enable */
+#define ETH_MACHWF3R_NRVF_Pos                         (0U)
+#define ETH_MACHWF3R_NRVF_Msk                         (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */
+#define ETH_MACHWF3R_NRVF                             ETH_MACHWF3R_NRVF_Msk  /* Number of Extended VLAN Tag Filters Enabled */
+#define ETH_MACHWF3R_NRVF_NOEXRXVLANFLTR              ((uint32_t)0x00000000) /* No Extended Rx VLAN Filters */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos           (0U)
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR               ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos           (1U)
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR               ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk          (0x3UL << ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos) /*!< 0x00000003 */
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR              ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos          (2U)
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk          (0x1UL << ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR              ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk          (0x5UL << ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos) /*!< 0x00000005 */
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR              ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk
+
+/************ Bit definition for Ethernet MAC MDIO Address Register   ***************/
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV204_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV204_Msk                   (0x3UL << ETH_MACMDIOAR_CR_DIV204_Pos) /*!< 0x00000600 */
+#define ETH_MACMDIOAR_CR_DIV204                       ETH_MACMDIOAR_CR_DIV204_Msk /* CSR clock/204 */
+#define ETH_MACMDIOAR_CR_DIV324_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV324_Msk                   (0x7UL << ETH_MACMDIOAR_CR_DIV324_Pos) /*!< 0x00000700 */
+#define ETH_MACMDIOAR_CR_DIV324                       ETH_MACMDIOAR_CR_DIV324_Msk /* CSR clock/304 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_GOC_Pos                         (2U)
+#define ETH_MACMDIOAR_GOC_Msk                         (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_GOC_0                           (0x1U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000004 */
+#define ETH_MACMDIOAR_GOC_1                           (0x2U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000008 */
+#define ETH_MACMDIOAR_GOC                             ETH_MACMDIOAR_GOC_Msk    /* GMII Operation Command */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_GB_Pos                          (0U)
+#define ETH_MACMDIOAR_GB_Msk                          (0x1UL << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_GB                              ETH_MACMDIOAR_GB_Msk     /* GMII Busy */
+
+/************ Bit definition for Ethernet MAC MDIO Data Register   ***************/
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_GD_Pos                          (0U)
+#define ETH_MACMDIODR_GD_Msk                          (0xFFFFUL << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_GD                              ETH_MACMDIODR_GD_Msk     /* GMII Data */
+
+/************ Bit definition for Ethernet ARP Address Register    ***************/
+#define ETH_MACARPAR_ARPPA_Pos                        (0U)
+#define ETH_MACARPAR_ARPPA_Msk                        (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                            ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/************ Bit definition for Ethernet MAC CSR software control Register   ***************/
+#define ETH_MACCSRSWCR_SEEN_Pos                       (8U)
+#define ETH_MACCSRSWCR_SEEN_Msk                       (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */
+#define ETH_MACCSRSWCR_SEEN                           ETH_MACCSRSWCR_SEEN_Msk /* Slave Error Response Enable */
+#define ETH_MACCSRSWCR_RCWE_Pos                       (0U)
+#define ETH_MACCSRSWCR_RCWE_Msk                       (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */
+#define ETH_MACCSRSWCR_RCWE                           ETH_MACCSRSWCR_RCWE_Msk /* Register Clear on Write 1 Enable */
+
+/************ Bit definition for Ethernet MAC FPE control and status Register   ***************/
+#define ETH_MACFPECSR_TRSP_Pos                        (19U)
+#define ETH_MACFPECSR_TRSP_Msk                        (0x1UL << ETH_MACFPECSR_TRSP_Pos) /*!< 0x00080000 */
+#define ETH_MACFPECSR_TRSP                            ETH_MACFPECSR_TRSP_Msk /* Transmitted Respond Frame */
+#define ETH_MACFPECSR_TVER_Pos                        (18U)
+#define ETH_MACFPECSR_TVER_Msk                        (0x1UL << ETH_MACFPECSR_TVER_Pos) /*!< 0x00040000 */
+#define ETH_MACFPECSR_TVER                            ETH_MACFPECSR_TVER_Msk /* Transmitted Verify Frame */
+#define ETH_MACFPECSR_RRSP_Pos                        (17U)
+#define ETH_MACFPECSR_RRSP_Msk                        (0x1UL << ETH_MACFPECSR_RRSP_Pos) /*!< 0x00020000 */
+#define ETH_MACFPECSR_RRSP                            ETH_MACFPECSR_RRSP_Msk /* Received Respond Frame */
+#define ETH_MACFPECSR_RVER_Pos                        (16U)
+#define ETH_MACFPECSR_RVER_Msk                        (0x1UL << ETH_MACFPECSR_RVER_Pos) /*!< 0x00010000 */
+#define ETH_MACFPECSR_RVER                            ETH_MACFPECSR_RVER_Msk /* Received Verify Frame */
+#define ETH_MACFPECSR_SRSP_Pos                        (2U)
+#define ETH_MACFPECSR_SRSP_Msk                        (0x1UL << ETH_MACFPECSR_SRSP_Pos) /*!< 0x00000004 */
+#define ETH_MACFPECSR_SRSP                            ETH_MACFPECSR_SRSP_Msk /* Send Respond mPacket */
+#define ETH_MACFPECSR_SVER_Pos                        (1U)
+#define ETH_MACFPECSR_SVER_Msk                        (0x1UL << ETH_MACFPECSR_SVER_Pos) /*!< 0x00000002 */
+#define ETH_MACFPECSR_SVER                            ETH_MACFPECSR_SVER_Msk /* Send Verify mPacket */
+#define ETH_MACFPECSR_EFPE_Pos                        (0U)
+#define ETH_MACFPECSR_EFPE_Msk                        (0x1UL << ETH_MACFPECSR_EFPE_Pos) /*!< 0x00000001 */
+#define ETH_MACFPECSR_EFPE                            ETH_MACFPECSR_EFPE_Msk /* Enable Tx Frame Preemption */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMR_MPTN_Pos                        (0U)
+#define ETH_MACPRSTIMR_MPTN_Msk                        (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMR_MPTN                            ETH_MACPRSTIMR_MPTN_Msk /* MAC 1722 Presentation Time in ns */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMUR_MPTU_Pos                       (0U)
+#define ETH_MACPRSTIMUR_MPTU_Msk                       (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMUR_MPTU                           ETH_MACPRSTIMUR_MPTU_Msk /* MAC 1722 Presentation Time Update */
+
+/************ Bit definition for Ethernet MAC Address 0 High Register   ***************/
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_DCS_Pos                           (16U)
+#define ETH_MACA0HR_DCS_Msk                           (0x1UL << ETH_MACA0HR_DCS_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_DCS                               ETH_MACA0HR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/************ Bit definition for Ethernet MAC Address x Low Register   ***************/
+#define ETH_MACAxLR_ADDRLO_Pos                        (0U)
+#define ETH_MACAxLR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACAxLR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACAxLR_ADDRLO                            ETH_MACAxLR_ADDRLO_Msk   /* MAC Address x*/
+
+/************ Bit definition for Ethernet MAC Address x High Register  ***************/
+#define ETH_MACAxHR_AE_Pos                            (31U)
+#define ETH_MACAxHR_AE_Msk                            (0x1UL << ETH_MACAxHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAxHR_AE                                ETH_MACAxHR_AE_Msk /* Address Enable*/
+#define ETH_MACAxHR_SA_Pos                            (30U)
+#define ETH_MACAxHR_SA_Msk                            (0x1UL << ETH_MACAxHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAxHR_SA                                ETH_MACAxHR_SA_Msk /* Source Address */
+#define ETH_MACAxHR_MBC_Pos                           (24U)
+#define ETH_MACAxHR_MBC_Msk                           (0x3FUL << ETH_MACAxHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAxHR_MBC                               ETH_MACAxHR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACAxHR_DCS_Pos                           (16U)
+#define ETH_MACAxHR_DCS_Msk                           (0x1UL << ETH_MACAxHR_DCS_Pos) /*!< 0x00010000 */
+#define ETH_MACAxHR_DCS                               ETH_MACAxHR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACAxHR_ADDRHI_Pos                        (0U)
+#define ETH_MACAxHR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACAxHR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAxHR_ADDRHI                            ETH_MACAxHR_ADDRHI_Msk   /* MAC Address 1*/
+
+/************ Bit definition for Ethernet MMC Control Register   ***************/
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/************ Bit definition for Ethernet MMC Rx Interrupt Register  ***************/
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Register   ***************/
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Rx interrupt Mask Register   ***************/
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Mask Register   ***************/
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Single Collision Good Packets Register   ***************/
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register   ***************/
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Packet Count Good Register  ***************/
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/************ Bit definition for Ethernet MMC Rx CRC Error Packets Register  ***************/
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx alignment error packets Register   ***************/
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx Unicast Packets Good Register   ***************/
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/************ Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register   ***************/
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Tx LPI Transition Counter Register   ***************/
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register   ***************/
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Transition Counter Register   ***************/
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt status Register   ***************/
+#define ETH_MMCFPETISR_HRCIS_Pos                      (1U)
+#define ETH_MMCFPETISR_HRCIS_msk                      (0x1UL <<  ETH_MMCFPETISR_HRCIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETISR_HRCIS                          ETH_MMCFPETISR_HRCIS_msk /* MMC Tx Hold Request Counter Interrupt Status */
+#define ETH_MMCFPETISR_FCIS_Pos                       (0U)
+#define ETH_MMCFPETISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPETISR_FCIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETISR_FCIS                           ETH_MMCFPETISR_FCIS_msk /* MMC Tx FPE Fragment Counter Interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt mask Register   ***************/
+#define ETH_MMCFPETIMR_HRCIM_Pos                      (1U)
+#define ETH_MMCFPETIMR_HRCIM_msk                      (0x1UL <<  ETH_MMCFPETIMR_HRCIM_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETIMR_HRCIM                          ETH_MMCFPETIMR_HRCIM_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+#define ETH_MMCFPETIMR_FCIM_Pos                       (0U)
+#define ETH_MMCFPETIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPETIMR_FCIM_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETIMR_FCIM                           ETH_MMCFPETIMR_FCIM_msk /* MMC Transmit Fragment Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC FPE Tx fragment counter Register   ***************/
+#define ETH_MMCFPETFCR_TXFFC_Pos                      (0U)
+#define ETH_MMCFPETFCR_TXFFC_msk                      (0xFFFFFFFFUL <<  ETH_MMCFPETFCR_TXFFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPETFCR_TXFFC                          ETH_MMCFPETFCR_TXFFC_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx hold request counter Register   ***************/
+#define ETH_MMCTHRCR_TXHRC_Pos                        (0U)
+#define ETH_MMCTHRCR_TXHRC_msk                        (0xFFFFFFFFUL <<  ETH_MMCTHRCR_TXHRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTHRCR_TXHRC                            ETH_MMCTHRCR_TXHRC_msk /* Tx hold request counter */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt status Register   ***************/
+#define ETH_MMCFPERISR_FCIS_Pos                       (3U)
+#define ETH_MMCFPERISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPERISR_FCIS_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERISR_FCIS                           ETH_MMCFPERISR_FCIS_msk /* MMC Rx FPE Fragment Counter Interrupt Status */
+#define ETH_MMCFPERISR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERISR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERISR_PAOCIS                         ETH_MMCFPERISR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt status */
+#define ETH_MMCFPERISR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERISR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERISR_PSECIS                         ETH_MMCFPERISR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt status */
+#define ETH_MMCFPERISR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERISR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERISR_PAECIS                         ETH_MMCFPERISR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt mask Register   ***************/
+#define ETH_MMCFPERIMR_FCIM_Pos                       (3U)
+#define ETH_MMCFPERIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPERIMR_FCIM_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERIMR_FCIM                           ETH_MMCFPERIMR_FCIM_msk /* MMC Rx FPE Fragment Counter Interrupt Mask */
+#define ETH_MMCFPERIMR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERIMR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERIMR_PAOCIS                         ETH_MMCFPERIMR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt Mask */
+#define ETH_MMCFPERIMR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERIMR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERIMR_PSECIS                         ETH_MMCFPERIMR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt Mask */
+#define ETH_MMCFPERIMR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERIMR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERIMR_PAECIS                         ETH_MMCFPERIMR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly error Register   ***************/
+#define ETH_MMCRPAER_PAEC_Pos                         (0U)
+#define ETH_MMCRPAER_PAEC_msk                         (0xFFFFFFFFUL <<  ETH_MMCRPAER_PAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAER_PAEC                             ETH_MMCRPAER_PAEC_msk /* Rx Packet Assembly Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet SMD error Register   ***************/
+#define ETH_MMCRPSMDER_PSEC_Pos                       (0U)
+#define ETH_MMCRPSMDER_PSEC_msk                       (0xFFFFFFFFUL <<  ETH_MMCRPSMDER_PSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPSMDER_PSEC                           ETH_MMCRPSMDER_PSEC_msk /* Rx Packet SMD Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly OK Register   ***************/
+#define ETH_MMCRPAOKR_PAOC_Pos                        (0U)
+#define ETH_MMCRPAOKR_PAOC_msk                        (0xFFFFFFFFUL <<  ETH_MMCRPAOKR_PAOC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAOKR_PAOC                            ETH_MMCRPAOKR_PAOC_msk /* Rx Packet Assembly OK Counter */
+
+/************ Bit definition for Ethernet MMC Rx FPE fragments counter Register   ***************/
+#define ETH_MMCFPERFCR_FFC_Pos                        (0U)
+#define ETH_MMCFPERFCR_FFC_msk                        (0xFFFFFFFFUL <<  ETH_MMCFPERFCR_FFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPERFCR_FFC                            ETH_MMCFPERFCR_FFC_msk /* Rx FPE Fragment Counter */
+
+/************ Bit definition for Ethernet MAC L3 and L4 control 0 Register   ***************/
+#define ETH_MACL3L4C0R_DMCHEN0_Pos                     (28U)
+#define ETH_MACL3L4C0R_DMCHEN0_Msk                     (0x1UL << ETH_MACL3L4C0R_DMCHEN0_Pos) /*!< 0x10000000 */
+#define ETH_MACL3L4C0R_DMCHEN0                         ETH_MACL3L4C0R_DMCHEN0_Msk /* DMA Channel Select Enable */
+#define ETH_MACL3L4C0R_DMCHN0_Pos                      (24U)
+#define ETH_MACL3L4C0R_DMCHN0_Msk                      (0x1UL << ETH_MACL3L4C0R_DMCHN0_Pos) /*!< 0x01000000 */
+#define ETH_MACL3L4C0R_DMCHN0                          ETH_MACL3L4C0R_DMCHN0_Msk /* DMA Channel Number */
+#define ETH_MACL3L4C0R_L4DPIM0_Pos                     (21U)
+#define ETH_MACL3L4C0R_L4DPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4C0R_L4DPIM0                         ETH_MACL3L4C0R_L4DPIM0_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4DPM0_Pos                      (20U)
+#define ETH_MACL3L4C0R_L4DPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4C0R_L4DPM0                          ETH_MACL3L4C0R_L4DPM0_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4C0R_L4SPIM0_Pos                     (19U)
+#define ETH_MACL3L4C0R_L4SPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4C0R_L4SPIM0                         ETH_MACL3L4C0R_L4SPIM0_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4SPM0_Pos                      (18U)
+#define ETH_MACL3L4C0R_L4SPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4C0R_L4SPM0                          ETH_MACL3L4C0R_L4SPM0_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4C0R_L4PEN0_Pos                      (16U)
+#define ETH_MACL3L4C0R_L4PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4C0R_L4PEN0                          ETH_MACL3L4C0R_L4PEN0_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4C0R_L3HDBM0_Pos                     (11U)
+#define ETH_MACL3L4C0R_L3HDBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4C0R_L3HDBM0                         ETH_MACL3L4C0R_L3HDBM0_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3HSBM0_Pos                     (6U)
+#define ETH_MACL3L4C0R_L3HSBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4C0R_L3HSBM0                         ETH_MACL3L4C0R_L3HSBM0_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3DAIM0_Pos                     (5U)
+#define ETH_MACL3L4C0R_L3DAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4C0R_L3DAIM0                         ETH_MACL3L4C0R_L3DAIM0_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3DAM0_Pos                      (4U)
+#define ETH_MACL3L4C0R_L3DAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4C0R_L3DAM0                          ETH_MACL3L4C0R_L3DAM0_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4C0R_L3SAIM0_Pos                     (3U)
+#define ETH_MACL3L4C0R_L3SAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4C0R_L3SAIM0                         ETH_MACL3L4C0R_L3SAIM0_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3SAM0_Pos                      (2U)
+#define ETH_MACL3L4C0R_L3SAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4C0R_L3SAM0                          ETH_MACL3L4C0R_L3SAM0_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4C0R_L3PEN0_Pos                      (0U)
+#define ETH_MACL3L4C0R_L3PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4C0R_L3PEN0                          ETH_MACL3L4C0R_L3PEN0_Msk  /* Layer 3 Protocol Enable */
+
+/************ Bit definition for Ethernet MAC Layer4 Address filter Register   ***************/
+#define ETH_MACL4A0R_L4DP0_Pos                        (16U)
+#define ETH_MACL4A0R_L4DP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4A0R_L4DP0                            ETH_MACL4A0R_L4DP0_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4A0R_L4SP0_Pos                        (0U)
+#define ETH_MACL4A0R_L4SP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4A0R_L4SP0                            ETH_MACL4A0R_L4SP0_Msk     /* Layer 4 Source Port Number Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 0 Register   ***************/
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 1 Register   ***************/
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 2 Register   ***************/
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 3 Register   ***************/
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/************ Bit definition for Ethernet MAC Indirect Access Control Register   ***************/
+#define ETH_MACIACR_MSEL_Pos                           (16U)
+#define ETH_MACIACR_MSEL_Msk                           (0xFUL << ETH_MACIACR_MSEL_Pos) /*!< 0x000F0000 */
+#define ETH_MACIACR_MSEL                               ETH_MACIACR_MSEL_Msk    /* Mode Select */
+#define ETH_MACIACR_MSEL_RXQ                           ((uint32_t)0x00000000)   /* Type-based RXQ mapping */
+#define ETH_MACIACR_AOFF_Pos                           (8U)
+#define ETH_MACIACR_AOFF_Msk                           (0xFFUL << ETH_MACIACR_AOFF_Pos) /*!< 0x0000FF00 */
+#define ETH_MACIACR_AOFF                               ETH_MACIACR_AOFF_Msk    /* Address Offset */
+#define ETH_MACIACR_AOFF_IndReg0                       ((uint32_t)0x00000000)   /* Indirect register 0 */
+#define ETH_MACIACR_AOFF_IndReg1_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg1_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg1_Pos) /*!< 0x00000100 */
+#define ETH_MACIACR_AOFF_IndReg1                       ETH_MACIACR_AOFF_IndReg1_Msk  /* Indirect register 1 */
+#define ETH_MACIACR_AOFF_IndReg2_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg2_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg2_Pos) /*!< 0x00000200 */
+#define ETH_MACIACR_AOFF_IndReg2                       ETH_MACIACR_AOFF_IndReg2_Msk  /* Indirect register 2 */
+#define ETH_MACIACR_AOFF_IndReg3_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg3_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg3_Pos) /*!< 0x00000300 */
+#define ETH_MACIACR_AOFF_IndReg3                       ETH_MACIACR_AOFF_IndReg3_Msk  /* Indirect register 3 */
+#define ETH_MACIACR_AOFF_IndReg4_Pos                   (10U)
+#define ETH_MACIACR_AOFF_IndReg4_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg4_Pos) /*!< 0x00000400 */
+#define ETH_MACIACR_AOFF_IndReg4                       ETH_MACIACR_AOFF_IndReg4_Msk  /* Indirect register 4 */
+#define ETH_MACIACR_AOFF_IndReg5_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg5_Msk                   (0x5UL << ETH_MACIACR_AOFF_IndReg5_Pos) /*!< 0x00000500 */
+#define ETH_MACIACR_AOFF_IndReg5                       ETH_MACIACR_AOFF_IndReg5_Msk  /* Indirect register 5 */
+#define ETH_MACIACR_AOFF_IndReg6_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg6_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg6_Pos) /*!< 0x00000600 */
+#define ETH_MACIACR_AOFF_IndReg6                       ETH_MACIACR_AOFF_IndReg6_Msk  /* Indirect register 6 */
+#define ETH_MACIACR_AOFF_IndReg7_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg7_Msk                   (0x7UL << ETH_MACIACR_AOFF_IndReg7_Pos) /*!< 0x00000700 */
+#define ETH_MACIACR_AOFF_IndReg7                       ETH_MACIACR_AOFF_IndReg7_Msk  /* Indirect register 7 */
+#define ETH_MACIACR_AUTO_Pos                           (5U)
+#define ETH_MACIACR_AUTO_Msk                           (0x1UL << ETH_MACIACR_AUTO_Pos) /*!< 0x00000020 */
+#define ETH_MACIACR_AUTO                               ETH_MACIACR_AUTO_Msk    /* Auto-increment */
+#define ETH_MACIACR_COM_Pos                            (1U)
+#define ETH_MACIACR_COM_Msk                            (0x1UL << ETH_MACIACR_COM_Pos) /*!< 0x00000002 */
+#define ETH_MACIACR_COM                                ETH_MACIACR_COM_Msk    /* Command type: 1: read operation / 0: write operation */
+#define ETH_MACIACR_OB_Pos                             (0U)
+#define ETH_MACIACR_OB_Msk                             (0x1UL << ETH_MACIACR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACIACR_OB                                 ETH_MACIACR_OB_Msk    /* Operation Busy */
+
+/************ Bit definition for Ethernet MAC type-based Rx Queue mapping Register   ***************/
+#define ETH_MACTMRQR_PFEX_Pos                          (20U)
+#define ETH_MACTMRQR_PFEX_Msk                          (0x1UL << ETH_MACTMRQR_PFEX_Pos) /*!< 0x00100000 */
+#define ETH_MACTMRQR_PFEX                              ETH_MACTMRQR_PFEX_Msk    /* Preemption or Express Packet */
+#define ETH_MACTMRQR_TMRQ_Pos                          (16U)
+#define ETH_MACTMRQR_TMRQ_Msk                          (0x7UL << ETH_MACTMRQR_TMRQ_Pos) /*!< 0x00070000 */
+#define ETH_MACTMRQR_TMRQ                              ETH_MACTMRQR_TMRQ_Msk    /* Type Match Rx Queue Number */
+#define ETH_MACTMRQR_TYP_Pos                           (0U)
+#define ETH_MACTMRQR_TYP_Msk                           (0xFFFFUL << ETH_MACTMRQR_TYP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACTMRQR_TYP                               ETH_MACTMRQR_TYP_Msk    /* Type field Value */
+
+/************ Bit definition for Ethernet MAC Timestamp Control Register   ***************/
+#define ETH_MACTSCR_AV8021ASMEN_Pos                   (28U)
+#define ETH_MACTSCR_AV8021ASMEN_Msk                   (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
+#define ETH_MACTSCR_AV8021ASMEN                       ETH_MACTSCR_AV8021ASMEN_Msk  /* AV 802.1AS Mode Enable */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_ESTI_Pos                          (20U)
+#define ETH_MACTSCR_ESTI_Msk                          (0x1UL << ETH_MACTSCR_ESTI_Pos) /*!< 0x00100000 */
+#define ETH_MACTSCR_ESTI                              ETH_MACTSCR_ESTI_Msk  /* External System Time Input */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_PTGE_Pos                          (6U)
+#define ETH_MACTSCR_PTGE_Msk                          (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */
+#define ETH_MACTSCR_PTGE                              ETH_MACTSCR_PTGE_Msk  /* Presentation Time Generation Enable */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/************ Bit definition for Ethernet MAC Sub-second Increment Register   ***************/
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Register   ***************/
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Register   ***************/
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Update Register   ***************/
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Update Register   ***************/
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Addend Register   ***************/
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/************ Bit definition for Ethernet MAC Timestamp Status Register   ***************/
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR1_Pos                    (5U)
+#define ETH_MACTSSR_TSTRGTERR1_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR1_Pos) /*!< 0x00000020 */
+#define ETH_MACTSSR_TSTRGTERR1                        ETH_MACTSSR_TSTRGTERR1_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_TSTARGT1_Pos                      (4U)
+#define ETH_MACTSSR_TSTARGT1_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT1_Pos) /*!< 0x00000010 */
+#define ETH_MACTSSR_TSTARGT1                          ETH_MACTSSR_TSTARGT1_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register   ***************/
+#define ETH_MACTXTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTXTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTXTSSNR_TXTSSMIS                        ETH_MACTXTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTXTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTXTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTXTSSNR_TXTSSLO                         ETH_MACTXTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register   ***************/
+#define ETH_MACTXTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTXTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTXTSSSR_TXTSSHI                         ETH_MACTXTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/************ Bit definition for Ethernet MAC Auxiliary Control Register   ***************/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register   ***************/
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register   ***************/
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register   ***************/
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction  ***************/
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond   ***************/
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond   ***************/
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Latency   ***************/
+#define ETH_MACTSILR_ITLNS_Pos                        (16U)
+#define ETH_MACTSILR_ITLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSILR_ITLNS                            ETH_MACTSILR_ITLNS_Msk  /* Ingress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSILR_ITLSNS_Pos                       (8U)
+#define ETH_MACTSILR_ITLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSILR_ITLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Ingress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Latency Register   ***************/
+#define ETH_MACTSELR_ETLNS_Pos                        (16U)
+#define ETH_MACTSELR_ETLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSELR_ETLNS                            ETH_MACTSILR_ITLNS_Msk  /* Egress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSELR_ETLSNS_Pos                       (8U)
+#define ETH_MACTSELR_ETLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSELR_ETLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Egress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC PPS Control Register   ***************/
+#define ETH_MACPPSCR_TIMESEL_Pos                      (28U)
+#define ETH_MACPPSCR_TIMESEL_Msk                      (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSCR_TIMESEL                          ETH_MACPPSCR_TIMESEL_Msk  /* Time Select */
+#define ETH_MACPPSCR_MCGREN0_Pos                      (7U)
+#define ETH_MACPPSCR_MCGREN0_Msk                      (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0                          ETH_MACPPSCR_MCGREN0_Msk  /* MCGR Mode Enable for PPS0 Output */
+#define ETH_MACPPSCR_MCGREN0_PPS                      ((uint32_t)0x00000000)   /* PPS mode */
+#define ETH_MACPPSCR_MCGREN0_MCGR_Pos                 (7U)
+#define ETH_MACPPSCR_MCGREN0_MCGR_Msk                 (0x1UL << ETH_MACPPSCR_MCGREN0_MCGR_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0_MCGR                     ETH_MACPPSCR_MCGREN0_MCGR_Msk  /* MCGR mode */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/************ Bit definition for Ethernet MAC PPS x target time seconds Register   ***************/
+#define ETH_MACPPSTTSxR_TSTRH0_Pos                    (0U)
+#define ETH_MACPPSTTSxR_TSTRH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSTTSxR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSxR_TSTRH0                        ETH_MACPPSTTSxR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/************ Bit definition for Ethernet MAC PPS x target time nanoseconds Register   ***************/
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Pos                 (31U)
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Msk                 (0x1UL << ETH_MACPPSTTNxR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNxR_TRGTBUSY0                     ETH_MACPPSTTNxR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNxR_TTSL0_Pos                     (0U)
+#define ETH_MACPPSTTNxR_TTSL0_Msk                     (0x7FFFFFFFUL << ETH_MACPPSTTNxR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNxR_TTSL0                         ETH_MACPPSTTNxR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/************ Bit definition for Ethernet MAC PPS x Interval Register   ***************/
+#define ETH_MACPPSIxR_PPSINT0_Pos                     (0U)
+#define ETH_MACPPSIxR_PPSINT0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSIxR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIxR_PPSINT0                         ETH_MACPPSIxR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/************ Bit definition for Ethernet MAC PPS x Width Register   ***************/
+#define ETH_MACPPSWxR_PPSWIDTH0_Pos                   (0U)
+#define ETH_MACPPSWxR_PPSWIDTH0_Msk                   (0xFFFFFFFFUL << ETH_MACPPSWxR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWxR_PPSWIDTH0                       ETH_MACPPSWxR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/************ Bit definition for Ethernet MAC PTP Offload Control Register   ***************/
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_PDRDIS_Pos                        (7U)
+#define ETH_MACPOCR_PDRDIS_Msk                        (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */
+#define ETH_MACPOCR_PDRDIS                            ETH_MACPOCR_PDRDIS_Msk  /* Disable Peer Delay Response response generation */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 0 Register   ***************/
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 1 Register   ***************/
+#define ETH_MACSPI1R_SPI1_Pos                        (0U)
+#define ETH_MACSPI1R_SPI1_Msk                        (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                            ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 2 Register   ***************/
+#define ETH_MACSPI2R_SPI2_Pos                        (0U)
+#define ETH_MACSPI2R_SPI2_Msk                        (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                            ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/************ Bit definition for Ethernet MAC Log Message Interval Register   ***************/
+#define ETH_MACLMIR_LMPDRI_Pos                       (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                       (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                            ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                      (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                      (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                          ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                          (0U)
+#define ETH_MACLMIR_LSI_Msk                          (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                              ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/************ Bit definition for Ethernet MTL Operation Mode Register   ***************/
+#define ETH_MTLOMR_CNTCLR_Pos                        (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                        (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                            ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                       (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                       (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                           ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_SCHALG_Pos                        (5U)
+#define ETH_MTLOMR_SCHALG_Msk                        (0x3UL << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG                            ETH_MTLOMR_SCHALG_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_SCHALG_WRR                        ((uint32_t)0x00000000)   /* Weighted round robin (WRR) algorithm */
+#define ETH_MTLOMR_SCHALG_SP_Pos                     (5U)
+#define ETH_MTLOMR_SCHALG_SP_Msk                     (0x3UL << ETH_MTLOMR_SCHALG_SP_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG_SP                         ETH_MTLOMR_SCHALG_SP_Msk  /* Strict priority (SP) algorithm */
+#define ETH_MTLOMR_RAA_Pos                           (2U)
+#define ETH_MTLOMR_RAA_Msk                           (0x1UL << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA                               ETH_MTLOMR_RAA_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_RAA_SP                            ((uint32_t)0x00000000)   /* Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest */
+#define ETH_MTLOMR_RAA_WSP_Pos                       (2U)
+#define ETH_MTLOMR_RAA_WSP_Msk                       (0x1UL << ETH_MTLOMR_RAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA_WSP                           ETH_MTLOMR_RAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_MTLOMR_DTXSTS_Pos                        (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                        (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                            ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/************ Bit definition for Ethernet MTL Interrupt Status Register   ***************/
+#define ETH_MTLISR_ESTIS_Pos                          (18U)
+#define ETH_MTLISR_ESTIS_Msk                          (0x1UL << ETH_MTLISR_ESTIS_Pos) /*!< 0x00040000 */
+#define ETH_MTLISR_ESTIS                              ETH_MTLISR_ESTIS_Msk     /* EST (TAS- 802.1Qbv) Interrupt Status */
+#define ETH_MTLISR_Q1IS_Pos                           (1U)
+#define ETH_MTLISR_Q1IS_Msk                           (0x1UL << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
+#define ETH_MTLISR_Q1IS                               ETH_MTLISR_Q1IS_Msk       /* Queue 1 Interrupt status */
+#define ETH_MTLISR_Q0IS_Pos                           (0U)
+#define ETH_MTLISR_Q0IS_Msk                           (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_Q0IS                               ETH_MTLISR_Q0IS_Msk       /* Queue 0 Interrupt status */
+
+/************ Bit definition for Ethernet MTL Rx Queue and DMA Channel Mapping   ***************/
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Pos                 (12U)
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1DDMACH_Pos) /*!< 0x00001000 */
+#define ETH_MTLRXQDMAMR_Q1DDMACH                     ETH_MTLRXQDMAMR_Q1DDMACH_Msk /* Queue 1 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Pos                 (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH                     ETH_MTLRXQDMAMR_Q1MDMACH_Msk /* Queue 1 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos          (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk /* DMA Channel 1 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Pos                 (4U)
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0DDMACH_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH                     ETH_MTLRXQDMAMR_Q0DDMACH_Msk /* Queue 0 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Pos                 (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH                     ETH_MTLRXQDMAMR_Q0MDMACH_Msk /* Queue 0 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos          (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk /* DMA Channel 1 */
+
+/************ Bit definition for Ethernet MTL TBS control Register   ***************/
+#define ETH_MTLTBSCR_LEOS_Pos                       (8U)
+#define ETH_MTLTBSCR_LEOS_Msk                       (0xFFFFFFUL << ETH_MTLTBSCR_LEOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEOS                           ETH_MTLTBSCR_LEOS_Msk /* Launch Expiry Offset */
+#define ETH_MTLTBSCR_LEGOS_Pos                      (4U)
+#define ETH_MTLTBSCR_LEGOS_Msk                      (0x7UL << ETH_MTLTBSCR_LEGOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEGOS                          ETH_MTLTBSCR_LEGOS_Msk /* Launch Expiry GSN Offset */
+#define ETH_MTLTBSCR_LEOV_Pos                       (1U)
+#define ETH_MTLTBSCR_LEOV_Msk                       (0x1UL << ETH_MTLTBSCR_LEOV_Pos) /*!< 0x00000002 */
+#define ETH_MTLTBSCR_LEOV                           ETH_MTLTBSCR_LEOV_Msk /* Launch expiry offset valid */
+#define ETH_MTLTBSCR_ESTM_Pos                       (0U)
+#define ETH_MTLTBSCR_ESTM_Msk                       (0x1UL << ETH_MTLTBSCR_ESTM_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM                           ETH_MTLTBSCR_ESTM_Msk /* EST offset mode */
+#define ETH_MTLTBSCR_ESTM_ESTOFFDIS                 ((uint32_t)0x00000000)   /* EST offset mode disabled */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos              (0U)
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk              (0x1UL << ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN                   ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk  /* EST offset mode enabled */
+
+/************ Bit definition for Ethernet MTL EST Control Register   ***************/
+#define ETH_MTLESTCR_PTOV_Pos                       (24U)
+#define ETH_MTLESTCR_PTOV_Msk                       (0xFFFFFFUL << ETH_MTLESTCR_PTOV_Pos) /*!< 0xFF000000 */
+#define ETH_MTLESTCR_PTOV                           ETH_MTLESTCR_PTOV_Msk /* PTP Time Offset Value */
+#define ETH_MTLESTCR_CTOV_Pos                       (12U)
+#define ETH_MTLESTCR_CTOV_Msk                       (0xFFFUL << ETH_MTLESTCR_CTOV_Pos) /*!< 0x00FFF000 */
+#define ETH_MTLESTCR_CTOV                           ETH_MTLESTCR_CTOV_Msk /* Current Time Offset Value */
+#define ETH_MTLESTCR_TILS_Pos                       (8U)
+#define ETH_MTLESTCR_TILS_Msk                       (0x7UL << ETH_MTLESTCR_TILS_Pos) /*!< 0x00000700 */
+#define ETH_MTLESTCR_TILS                           ETH_MTLESTCR_TILS_Msk /* Time Interval Left Shift Amount */
+#define ETH_MTLESTCR_LCSE_Pos                       (6U)
+#define ETH_MTLESTCR_LCSE_Msk                       (0x3UL << ETH_MTLESTCR_LCSE_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE                           ETH_MTLESTCR_LCSE_Msk /* Loop Count to report Scheduling Error */
+#define ETH_MTLESTCR_LCSE_4IT                       ((uint32_t)0x00000000)   /* 4 iterations */
+#define ETH_MTLESTCR_LCSE_8IT_Pos                   (6U)
+#define ETH_MTLESTCR_LCSE_8IT_Msk                   (0x1UL << ETH_MTLESTCR_LCSE_8IT_Pos) /*!< 0x00000040 */
+#define ETH_MTLESTCR_LCSE_8IT                       ETH_MTLESTCR_LCSE_8IT_Msk   /* 8 iterations */
+#define ETH_MTLESTCR_LCSE_16IT_Pos                  (7U)
+#define ETH_MTLESTCR_LCSE_16IT_Msk                  (0x1UL << ETH_MTLESTCR_LCSE_16IT_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTCR_LCSE_16IT                      ETH_MTLESTCR_LCSE_16IT_Msk  /* 16 iterations */
+#define ETH_MTLESTCR_LCSE_32IT_Pos                  (6U)
+#define ETH_MTLESTCR_LCSE_32IT_Msk                  (0x3UL << ETH_MTLESTCR_LCSE_32IT_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE_32IT                      ETH_MTLESTCR_LCSE_32IT_Msk  /* 32 iterations */
+#define ETH_MTLESTCR_DFBS_Pos                       (5U)
+#define ETH_MTLESTCR_DFBS_Msk                       (0x1UL << ETH_MTLESTCR_DFBS_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTCR_DFBS                           ETH_MTLESTCR_DFBS_Msk /* Drop Frames causing Scheduling Error */
+#define ETH_MTLESTCR_DDBF_Pos                       (4U)
+#define ETH_MTLESTCR_DDBF_Msk                       (0x1UL << ETH_MTLESTCR_DDBF_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTCR_DDBF                           ETH_MTLESTCR_DDBF_Msk /* Do not Drop frames during Frame Size Error */
+#define ETH_MTLESTCR_SSWL_Pos                       (1U)
+#define ETH_MTLESTCR_SSWL_Msk                       (0x1UL << ETH_MTLESTCR_SSWL_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTCR_SSWL                           ETH_MTLESTCR_SSWL_Msk /* Switch to S/W owned list */
+#define ETH_MTLESTCR_EEST_Pos                       (0U)
+#define ETH_MTLESTCR_EEST_Msk                       (0x1UL << ETH_MTLESTCR_EEST_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTCR_EEST                           ETH_MTLESTCR_EEST_Msk /* Enable EST */
+
+/************ Bit definition for Ethernet MTL EST Extended Control Register   ***************/
+/* Bit definition for Ethernet MTL EST Extended Control Register */
+#define ETH_MTLESTECR_OVHD_Pos                       (0U)
+#define ETH_MTLESTECR_OVHD_Msk                       (0x3FUL << ETH_MTLESTECR_OVHD_Pos) /*!< 0x0000003F */
+#define ETH_MTLESTECR_OVHD                           ETH_MTLESTECR_OVHD_Msk /* Overhead Bytes Value */
+
+/************ Bit definition for Ethernet MTL EST Status Register   ***************/
+#define ETH_MTLESTSR_CGSN_Pos                       (16U)
+#define ETH_MTLESTSR_CGSN_Msk                       (0xFUL << ETH_MTLESTSR_CGSN_Pos) /*!< 0x000F0000 */
+#define ETH_MTLESTSR_CGSN                           ETH_MTLESTSR_CGSN_Msk /* Current GCL slot number */
+#define ETH_MTLESTSR_BTRL_Pos                       (8U)
+#define ETH_MTLESTSR_BTRL_Msk                       (0xFFUL << ETH_MTLESTSR_BTRL_Pos) /*!< 0x00000F00 */
+#define ETH_MTLESTSR_BTRL                           ETH_MTLESTSR_CGSN_Msk /* BTR Error Loop Count */
+#define ETH_MTLESTSR_SWOL_Pos                       (7U)
+#define ETH_MTLESTSR_SWOL_Msk                       (0x1UL << ETH_MTLESTSR_SWOL_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTSR_SWOL                           ETH_MTLESTSR_SWOL_Msk /* S/W owned list */
+#define ETH_MTLESTSR_CGCE_Pos                       (4U)
+#define ETH_MTLESTSR_CGCE_Msk                       (0x1UL << ETH_MTLESTSR_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTSR_CGCE                           ETH_MTLESTSR_CGCE_Msk /* Constant Gate Control Error */
+#define ETH_MTLESTSR_HLBS_Pos                       (3U)
+#define ETH_MTLESTSR_HLBS_Msk                       (0x1UL << ETH_MTLESTSR_HLBS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTSR_HLBS                           ETH_MTLESTSR_HLBS_Msk /* Head-Of-Line Blocking due to Scheduling */
+#define ETH_MTLESTSR_HLBF_Pos                       (2U)
+#define ETH_MTLESTSR_HLBF_Msk                       (0x1UL << ETH_MTLESTSR_HLBF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTSR_HLBF                           ETH_MTLESTSR_HLBF_Msk /* Head-Of-Line Blocking due to Frame Size */
+#define ETH_MTLESTSR_BTRE_Pos                       (1U)
+#define ETH_MTLESTSR_BTRE_Msk                       (0x1UL << ETH_MTLESTSR_BTRE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTSR_BTRE                           ETH_MTLESTSR_BTRE_Msk /* BTR Error */
+#define ETH_MTLESTSR_SWLC_Pos                       (0U)
+#define ETH_MTLESTSR_SWLC_Msk                       (0x1UL << ETH_MTLESTSR_SWLC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTSR_SWLC                           ETH_MTLESTSR_SWLC_Msk /* Switch to S/W owned list Complete */
+
+/************ Bit definition for Ethernet MTL EST Schedule Error Register   ***************/
+/* Bit definition for Ethernet MTL EST Schedule Error Register */
+#define ETH_MTLESTSCHER_SEQN_Pos                       (0U)
+#define ETH_MTLESTSCHER_SEQN_Msk                       (0x3UL << ETH_MTLESTSCHER_SEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTSCHER_SEQN                           ETH_MTLESTSCHER_SEQN_Msk /* Schedule Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Error Register   ***************/
+#define ETH_MTLESTFSER_FEQN_Pos                       (0U)
+#define ETH_MTLESTFSER_FEQN_Msk                       (0x3UL << ETH_MTLESTFSER_FEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTFSER_FEQN                           ETH_MTLESTFSER_FEQN_Msk /* Frame Size Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Capture Register   ***************/
+#define ETH_MTLESTFSCR_HBFQ_Pos                       (16U)
+#define ETH_MTLESTFSCR_HBFQ_Msk                       (0x1UL << ETH_MTLESTFSCR_HBFQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLESTFSCR_HBFQ                           ETH_MTLESTFSCR_HBFQ_Msk /* Queue Number of HLBF */
+#define ETH_MTLESTFSCR_HBFS_Pos                       (0U)
+#define ETH_MTLESTFSCR_HBFS_Msk                       (0x7FFFUL << ETH_MTLESTFSCR_HBFS_Pos) /*!< 0x00007FFF */
+#define ETH_MTLESTFSCR_HBFS                           ETH_MTLESTFSCR_HBFS_Msk /* Frame Size of HLBF */
+
+/************ Bit definition for Ethernet MTL EST Interrupt Enable Register   ***************/
+/* Bit definition for Ethernet MTL EST Interrupt Enable Register */
+#define ETH_MTLESTIER_CGCE_Pos                       (4U)
+#define ETH_MTLESTIER_CGCE_Msk                       (0x1UL << ETH_MTLESTIER_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTIER_CGCE                           ETH_MTLESTIER_CGCE_Msk /* Interrupt Enable for CGCE */
+#define ETH_MTLESTIER_IEHS_Pos                       (3U)
+#define ETH_MTLESTIER_IEHS_Msk                       (0x1UL << ETH_MTLESTIER_IEHS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTIER_IEHS                           ETH_MTLESTIER_IEHS_Msk /* Interrupt Enable for HLBS */
+#define ETH_MTLESTIER_IEHF_Pos                       (2U)
+#define ETH_MTLESTIER_IEHF_Msk                       (0x1UL << ETH_MTLESTIER_IEHF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTIER_IEHF                           ETH_MTLESTIER_IEHF_Msk /* Interrupt Enable for HLBF */
+#define ETH_MTLESTIER_IEBE_Pos                       (1U)
+#define ETH_MTLESTIER_IEBE_Msk                       (0x1UL << ETH_MTLESTIER_IEBE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTIER_IEBE                           ETH_MTLESTIER_IEBE_Msk /* Interrupt Enable for BTR Error */
+#define ETH_MTLESTIER_IECC_Pos                       (0U)
+#define ETH_MTLESTIER_IECC_Msk                       (0x1UL << ETH_MTLESTIER_IECC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTIER_IECC                           ETH_MTLESTIER_IECC_Msk /* Interrupt Enable for Switch List */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Register   ***************/
+#define ETH_MTLESTGCLCR_ADDR_Pos                       (8U)
+#define ETH_MTLESTGCLCR_ADDR_Msk                       (0x3FUL << ETH_MTLESTGCLCR_ADDR_Pos) /*!< 0x00003F00 */
+#define ETH_MTLESTGCLCR_ADDR                           ETH_MTLESTGCLCR_ADDR_Msk /* Gate Control List Address */
+#define ETH_MTLESTGCLCR_ADDR_BTRLOW                    ((uint32_t)0x00000000)   /* BTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk               (0x1UL << ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos) /*!< 0x00000100 */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH                   ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk /* BTR High (63:31) */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos                (9U)
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk                (0x1UL << ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos) /*!< 0x00000200 */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW                    ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk /* CTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk               (0x3UL << ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos) /*!< 0x00000300 */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH                   ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk /* CTR High (39:32) */
+#define ETH_MTLESTGCLCR_ADDR_TER_Pos                   (10U)
+#define ETH_MTLESTGCLCR_ADDR_TER_Msk                   (0x1UL << ETH_MTLESTGCLCR_ADDR_TER_Pos) /*!< 0x00000400 */
+#define ETH_MTLESTGCLCR_ADDR_TER                       ETH_MTLESTGCLCR_ADDR_TER_Msk /* TER (30:0) */
+#define ETH_MTLESTGCLCR_ADDR_LLR_Pos                   (8U)
+#define ETH_MTLESTGCLCR_ADDR_LLR_Msk                   (0x5UL << ETH_MTLESTGCLCR_ADDR_LLR_Pos) /*!< 0x00000500 */
+#define ETH_MTLESTGCLCR_ADDR_LLR                       ETH_MTLESTGCLCR_ADDR_LLR_Msk /* LLR (6:0) */
+#define ETH_MTLESTGCLCR_DBGB_Pos                       (5U)
+#define ETH_MTLESTGCLCR_DBGB_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGB_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTGCLCR_DBGB                           ETH_MTLESTGCLCR_DBGB_Msk /* Debug Mode Bank Select */
+#define ETH_MTLESTGCLCR_DBGM_Pos                       (4U)
+#define ETH_MTLESTGCLCR_DBGM_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGM_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTGCLCR_DBGM                           ETH_MTLESTGCLCR_DBGM_Msk /* Debug Mode */
+#define ETH_MTLESTGCLCR_GCRR_Pos                       (2U)
+#define ETH_MTLESTGCLCR_GCRR_Msk                       (0x1UL << ETH_MTLESTGCLCR_GCRR_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTGCLCR_GCRR                           ETH_MTLESTGCLCR_GCRR_Msk /* Gate Control Related Registers */
+#define ETH_MTLESTGCLCR_R1W0_Pos                       (1U)
+#define ETH_MTLESTGCLCR_R1W0_Msk                       (0x1UL << ETH_MTLESTGCLCR_R1W0_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTGCLCR_R1W0                           ETH_MTLESTGCLCR_R1W0_Msk /* Read 1, Write 0 */
+#define ETH_MTLESTGCLCR_SRWO_Pos                       (0U)
+#define ETH_MTLESTGCLCR_SRWO_Msk                       (0x1UL << ETH_MTLESTGCLCR_SRWO_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTGCLCR_SRWO                           ETH_MTLESTGCLCR_SRWO_Msk /* Start Read/Write Operation */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Data Register   ***************/
+#define ETH_MTLESTGCLDR_GCD_Pos                        (0U)
+#define ETH_MTLESTGCLDR_GCD_Msk                        (0xFFFFFFFFUL << ETH_MTLESTGCLDR_GCD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MTLESTGCLDR_GCD                            ETH_MTLESTGCLDR_GCD_Msk /* Gate Control Data */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Control Status Register   ***************/
+#define ETH_MTLFPECSR_HRS_Pos                          (28U)
+#define ETH_MTLFPECSR_HRS_Msk                          (0x1UL << ETH_MTLFPECSR_HRS_Pos) /*!< 0x10000000 */
+#define ETH_MTLFPECSR_HRS                              ETH_MTLFPECSR_HRS_Msk /* Hold/Release Status */
+#define ETH_MTLFPECSR_PEC_Pos                          (8U)
+#define ETH_MTLFPECSR_PEC_Msk                          (0x3UL << ETH_MTLFPECSR_PEC_Pos) /*!< 0x00000300 */
+#define ETH_MTLFPECSR_PEC                              ETH_MTLFPECSR_PEC_Msk /* Preemption Classification */
+#define ETH_MTLFPECSR_AFSZ_Pos                         (0U)
+#define ETH_MTLFPECSR_AFSZ_Msk                         (0x3UL << ETH_MTLFPECSR_AFSZ_Pos) /*!< 0x00000003 */
+#define ETH_MTLFPECSR_AFSZ                             ETH_MTLFPECSR_AFSZ_Msk /* Additional Fragment Size */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Advance Register   ***************/
+#define ETH_MTLFPEAR_RADV_Pos                          (16U)
+#define ETH_MTLFPEAR_RADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_RADV_Pos) /*!< 0xFFFF0000 */
+#define ETH_MTLFPEAR_RADV                              ETH_MTLFPEAR_RADV_Msk /* Release Advance */
+#define ETH_MTLFPEAR_HADV_Pos                          (0U)
+#define ETH_MTLFPEAR_HADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_HADV_Pos) /*!< 0x0000FFFF */
+#define ETH_MTLFPEAR_HADV                              ETH_MTLFPEAR_HADV_Msk /* Hold Advance */
+
+/************ Bit definition for Ethernet MTL Tx queue x operating mode Register   ***************/
+#define ETH_MTLTXQxOMR_TQS_Pos                          (16U)
+#define ETH_MTLTXQxOMR_TQS_Msk                          (0xFUL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x000F0000 */
+#define ETH_MTLTXQxOMR_TQS                              ETH_MTLTXQxOMR_TQS_Msk     /* Transmit queue size */
+#define ETH_MTLTXQxOMR_TQS_0                            (0x1UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00010000 */
+#define ETH_MTLTXQxOMR_TQS_1                            (0x2UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00020000 */
+#define ETH_MTLTXQxOMR_TQS_2                            (0x4UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00040000 */
+#define ETH_MTLTXQxOMR_TQS_3                            (0x8UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00080000 */
+#define ETH_MTLTXQxOMR_TTC_Pos                          (4U)
+#define ETH_MTLTXQxOMR_TTC_Msk                          (0x7UL << ETH_MTLTXQxOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQxOMR_TTC                              ETH_MTLTXQxOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTXQxOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTXQxOMR_TXQEN_Pos                        (2U)
+#define ETH_MTLTXQxOMR_TXQEN_Msk                        (0x3UL << ETH_MTLTXQxOMR_TXQEN_Pos) /*!< 0x0000000C */
+#define ETH_MTLTXQxOMR_TXQEN                            ETH_MTLTXQxOMR_TXQEN_Msk     /* Transmit Queue Enable */
+#define ETH_MTLTXQxOMR_TXQEN_NOT                        ((uint32_t)0x00000000)   /* Not enabled */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos                 (2U)
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk                 (0x1UL << ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE                     ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk     /* Enable in AV mode */
+#define ETH_MTLTXQxOMR_TXQEN_EN_Pos                     (3U)
+#define ETH_MTLTXQxOMR_TXQEN_EN_Msk                     (0x1UL << ETH_MTLTXQxOMR_TXQEN_EN_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxOMR_TXQEN_EN                         ETH_MTLTXQxOMR_TXQEN_EN_Msk     /* Enabled */
+#define ETH_MTLTXQxOMR_TSF_Pos                          (1U)
+#define ETH_MTLTXQxOMR_TSF_Msk                          (0x1UL << ETH_MTLTXQxOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQxOMR_TSF                              ETH_MTLTXQxOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTXQxOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTXQxOMR_FTQ_Msk                          (0x1UL << ETH_MTLTXQxOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxOMR_FTQ                              ETH_MTLTXQxOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Underflow Register   ***************/
+#define ETH_MTLTXQxUR_UFCNTOVF_Pos                     (11U)
+#define ETH_MTLTXQxUR_UFCNTOVF_Msk                     (0x1UL << ETH_MTLTXQxUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQxUR_UFCNTOVF                         ETH_MTLTXQxUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTXQxUR_UFPKTCNT_Pos                     (0U)
+#define ETH_MTLTXQxUR_UFPKTCNT_Msk                     (0x7FFUL << ETH_MTLTXQxUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTXQxUR_UFPKTCNT                         ETH_MTLTXQxUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Debug Register   ***************/
+#define ETH_MTLTXQxDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTXQxDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTXQxDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTXQxDR_STXSTSF                           ETH_MTLTXQxDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTXQxDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTXQxDR_PTXQ_Msk                          (0x7UL << ETH_MTLTXQxDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTXQxDR_PTXQ                              ETH_MTLTXQxDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTXQxDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTXQxDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTXQxDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQxDR_TXSTSFSTS                         ETH_MTLTXQxDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTXQxDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTXQxDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQxDR_TXQSTS                            ETH_MTLTXQxDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTXQxDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTXQxDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxDR_TWCSTS                            ETH_MTLTXQxDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTXQxDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTXQxDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTXQxDR_TRCSTS                            ETH_MTLTXQ0DR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTXQxDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTXQxDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTXQxDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTXQxDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTXQxDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTXQxDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxDR_TXQPAUSED                         ETH_MTLTXQxDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/************ Bit definition for Ethernet MTL Tx queue x ETS status Register   ***************/
+#define ETH_MTLTXQxESR_ABS_Pos                       (0U)
+#define ETH_MTLTXQxESR_ABS_Msk                       (0xFFFFFFUL << ETH_MTLTXQxESR_ABS_Pos) /*!< 0x00FFFFFF */
+#define ETH_MTLTXQxESR_ABS                           ETH_MTLTXQxESR_ABS_Msk  /* Average Bits per Slot */
+
+/************ Bit definition for Ethernet MTL Tx queue 0 quantum weight Register   ***************/
+#define ETH_MTLTXQ0QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ0QWR_ISCQW_Msk                       (0x7FUL << ETH_MTLTXQ0QWR_ISCQW_Pos) /*!< 0x0000007F */
+#define ETH_MTLTXQ0QWR_ISCQW                           ETH_MTLTXQ0QWR_ISCQW_Msk  /* Weights */
+
+/************ Bit definition for Ethernet MTL Queue x Interrupt Control Status Register   ***************/
+#define ETH_MTLQxICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQxICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQxICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQxICSR_RXOIE                            ETH_MTLQxICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQxICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQxICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQxICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQxICSR_RXOVFIS                          ETH_MTLQxICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQxICSR_ABPSIE_Pos                       (9U)
+#define ETH_MTLQxICSR_ABPSIE_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIE_Pos) /*!< 0x00000200 */
+#define ETH_MTLQxICSR_ABPSIE                           ETH_MTLQxICSR_ABPSIE_Msk   /* Average Bits Per Slot Interrupt Enable */
+#define ETH_MTLQxICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQxICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQxICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQxICSR_TXUIE                            ETH_MTLQxICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQxICSR_ABPSIS_Pos                       (1U)
+#define ETH_MTLQxICSR_ABPSIS_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIS_Pos) /*!< 0x00000002 */
+#define ETH_MTLQxICSR_ABPSIS                           ETH_MTLQxICSR_ABPSIS_Msk /* Average Bits Per Slot Interrupt Status */
+#define ETH_MTLQxICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQxICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQxICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQxICSR_TXUNFIS                          ETH_MTLQxICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Operation Mode Register   ***************/
+#define ETH_MTLRXQxOMR_RQS_Pos                          (20U)
+#define ETH_MTLRXQxOMR_RQS_Msk                          (0xFUL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00F00000 */
+#define ETH_MTLRXQxOMR_RQS                              ETH_MTLRXQxOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRXQxOMR_RQS_0                            (0x1UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00100000 */
+#define ETH_MTLRXQxOMR_RQS_1                            (0x2UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00200000 */
+#define ETH_MTLRXQxOMR_RQS_2                            (0x4UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00400000 */
+#define ETH_MTLRXQxOMR_RQS_3                            (0x8UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00800000 */
+#define ETH_MTLRXQxOMR_RFD_Pos                          (14U)
+#define ETH_MTLRXQxOMR_RFD_Msk                          (0x7UL << ETH_MTLRXQxOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRXQxOMR_RFD                              ETH_MTLRXQxOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRXQxOMR_RFA_Pos                          (8U)
+#define ETH_MTLRXQxOMR_RFA_Msk                          (0x7UL << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRXQxOMR_RFA                              ETH_MTLRXQxOMR_RFA_Pos /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRXQxOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRXQxOMR_EHFC_Msk                         (0x1UL << ETH_MTLRXQxOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQxOMR_EHFC                             ETH_MTLRXQxOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRXQxOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRXQxOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRXQxOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQxOMR_DISTCPEF                         ETH_MTLRXQxOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRXQxOMR_RSF_Pos                          (5U)
+#define ETH_MTLRXQxOMR_RSF_Msk                          (0x1UL << ETH_MTLRXQxOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxOMR_RSF                              ETH_MTLRXQxOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRXQxOMR_FEP_Pos                          (4U)
+#define ETH_MTLRXQxOMR_FEP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxOMR_FEP                              ETH_MTLRXQxOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRXQxOMR_FUP_Pos                          (3U)
+#define ETH_MTLRXQxOMR_FUP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxOMR_FUP                              ETH_MTLRXQxOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRXQxOMR_RTC_Pos                          (0U)
+#define ETH_MTLRXQxOMR_RTC_Msk                          (0x3UL << ETH_MTLRXQxOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRXQxOMR_RTC                              ETH_MTLRXQxOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRXQxOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Missed Packet Overflow Cnt Register   ***************/
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQxMPOCR_MISCNTOVF                      ETH_MTLRXQxMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT                      ETH_MTLRXQxMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF                      ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT                      ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Debug Register   ***************/
+#define ETH_MTLRXQxDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRXQxDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRXQxDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRXQxDR_PRXQ                              ETH_MTLRXQxDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRXQxDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRXQxDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS                            ETH_MTLRXQxDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRXQxDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRXQxDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS_FULL                       ETH_MTLRXQxDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRXQxDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRXQxDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS                            ETH_MTLRXQxDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRXQxDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS              ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING                   ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRXQxDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRXQxDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRXQxDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQxDR_RWCSTS                            ETH_MTLRXQxDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Control Register   ***************/
+#define ETH_MTLRXQxCR_RQPA_Pos                          (3U)
+#define ETH_MTLRXQxCR_RQPA_Msk                          (0x1UL << ETH_MTLRXQxCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxCR_RQPA                              ETH_MTLRXQxCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRXQxCR_RQW_Pos                           (0U)
+#define ETH_MTLRXQxCR_RQW_Msk                           (0x7UL << ETH_MTLRXQxCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRXQxCR_RQW                               ETH_MTLRXQxCR_RQW_Msk      /* Receive Queue Weight */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 ETS control Register   ***************/
+#define ETH_MTLTXQ1ECR_SLC_Pos                         (4U)
+#define ETH_MTLTXQ1ECR_SLC_Msk                         (0x7UL << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQ1ECR_SLC                             ETH_MTLTXQ1ECR_SLC_Msk     /* Slot Count */
+#define ETH_MTLTXQ1ECR_SLC_1SLOT                       ((uint32_t)0x00000000)   /* 1 Slot */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_2SLOT_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT                       ETH_MTLTXQ1ECR_SLC_2SLOT_Msk     /* 2 Slots */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Pos                   (5U)
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_4SLOT_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT                       ETH_MTLTXQ1ECR_SLC_4SLOT_Msk     /* 4 Slots */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Msk                   (0x3UL << ETH_MTLTXQ1ECR_SLC_8SLOT_Pos) /*!< 0x00000030 */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT                       ETH_MTLTXQ1ECR_SLC_8SLOT_Msk     /* 8 Slots */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Pos                  (6U)
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Msk                  (0x1UL << ETH_MTLTXQ1ECR_SLC_16SLOT_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT                      ETH_MTLTXQ1ECR_SLC_16SLOT_Msk     /* 16 Slots */
+#define ETH_MTLTXQ1ECR_CC_Pos                          (3U)
+#define ETH_MTLTXQ1ECR_CC_Msk                          (0x1UL << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1ECR_CC                              ETH_MTLTXQ1ECR_CC_Msk     /* Credit Control */
+#define ETH_MTLTXQ1ECR_AVALG_Pos                       (2U)
+#define ETH_MTLTXQ1ECR_AVALG_Msk                       (0x1UL << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1ECR_AVALG                           ETH_MTLTXQ1ECR_AVALG_Msk     /* Credit Control */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 quantum weight Register   ***************/
+#define ETH_MTLTXQ1QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ1QWR_ISCQW_Msk                       (0x3FFFUL << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1QWR_ISCQW                           ETH_MTLTXQ1QWR_ISCQW_Msk     /* IdleSlopeCredit or Weights */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 send slope credit Register   ***************/
+#define ETH_MTLTXQ1SSCR_SSC_Pos                        (0U)
+#define ETH_MTLTXQ1SSCR_SSC_Msk                        (0x3FFFUL << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1SSCR_SSC                            ETH_MTLTXQ1SSCR_SSC_Msk     /* sendSlopeCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx Queue 1 hiCredit Register   ***************/
+#define ETH_MTLTXQ1HCR_HC_Pos                          (0U)
+#define ETH_MTLTXQ1HCR_HC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1HCR_HC                              ETH_MTLTXQ1HCR_HC_Msk     /* hiCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 loCredit Register   ***************/
+#define ETH_MTLTXQ1LCR_LC_Pos                          (0U)
+#define ETH_MTLTXQ1LCR_LC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1LCR_LC                              ETH_MTLTXQ1LCR_LC_Msk     /* loCredit Value */
+
+/************ Bit definition for Ethernet DMA Mode Register   ***************/
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk         /* Transmit priority */
+#define ETH_DMAMR_DSPW_Pos                            (8U)
+#define ETH_DMAMR_DSPW_Msk                            (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */
+#define ETH_DMAMR_DSPW                                ETH_DMAMR_DSPW_Msk         /* Descriptor Posted Write */
+#define ETH_DMAMR_TAA_Pos                             (2U)
+#define ETH_DMAMR_TAA_Msk                             (0x7UL << ETH_DMAMR_TAA_Pos) /*!< 0x000001C0 */
+#define ETH_DMAMR_TAA                                 ETH_DMAMR_TAA_Msk         /* Transmit Arbitration Algorithm */
+#define ETH_DMAMR_TAA_FP                              ((uint32_t)0x00000000)    /* Fixed priority */
+#define ETH_DMAMR_TAA_WSP_Pos                         (2U)
+#define ETH_DMAMR_TAA_WSP_Msk                         (0x1UL << ETH_DMAMR_TAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_DMAMR_TAA_WSP                             ETH_DMAMR_TAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_DMAMR_TAA_WRR_Pos                         (3U)
+#define ETH_DMAMR_TAA_WRR_Msk                         (0x1UL << ETH_DMAMR_TAA_WRR_Pos) /*!< 0x00000008 */
+#define ETH_DMAMR_TAA_WRR                             ETH_DMAMR_TAA_WRR_Msk  /* Weighted Round-Robin (WRR) */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk  /* Software Reset */
+
+/************ Bit definition for Ethernet DMA System bus mode Register   ***************/
+#define ETH_DMASBMR_ENLPI_Pos                         (31U)
+#define ETH_DMASBMR_ENLPI_Msk                         (0x1UL << ETH_DMASBMR_ENLPI_Pos) /*!< 0x80000000 */
+#define ETH_DMASBMR_ENLPI                             ETH_DMASBMR_ENLPI_Msk       /* Enable Low Power Interface (LPI) */
+#define ETH_DMASBMR_LPIXPKT_Pos                       (30U)
+#define ETH_DMASBMR_LPIXPKT_Msk                       (0x1UL << ETH_DMASBMR_LPIXPKT_Pos) /*!< 0x40000000 */
+#define ETH_DMASBMR_LPIXPKT                           ETH_DMASBMR_LPIXPKT_Msk       /* Unlock on Magic Packet or Remote wakeup Packet */
+#define ETH_DMASBMR_WR_OSR_LMT_Pos                    (24U)
+#define ETH_DMASBMR_WR_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
+#define ETH_DMASBMR_WR_OSR_LMT                        ETH_DMASBMR_WR_OSR_LMT_Msk            /*!< AXI Maximum Write Outstanding Request Limit */
+#define ETH_DMASBMR_WR_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
+#define ETH_DMASBMR_WR_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
+#define ETH_DMASBMR_RD_OSR_LMT_Pos                    (16U)
+#define ETH_DMASBMR_RD_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
+#define ETH_DMASBMR_RD_OSR_LMT                        ETH_DMASBMR_RD_OSR_LMT_Msk            /*!< AXI Maximum Read Outstanding Request Limit */
+#define ETH_DMASBMR_RD_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
+#define ETH_DMASBMR_RD_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
+#define ETH_DMASBMR_ONEKBBE_Pos                       (13U)
+#define ETH_DMASBMR_ONEKBBE_Msk                       (0x1UL << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
+#define ETH_DMASBMR_ONEKBBE                           ETH_DMASBMR_ONEKBBE_Msk       /* 1 Kbyte Boundary Crossing Enable for the AXI Master */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_AALE_Pos                          (10U)
+#define ETH_DMASBMR_AALE_Msk                          (0x1UL << ETH_DMASBMR_AALE_Pos) /*!< 0x00000400 */
+#define ETH_DMASBMR_AALE                              ETH_DMASBMR_AALE_Msk       /* Automatic AXI LPI enable */
+#define ETH_DMASBMR_BLEN256_Pos                       (7U)
+#define ETH_DMASBMR_BLEN256_Msk                       (0x1UL << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
+#define ETH_DMASBMR_BLEN256                           ETH_DMASBMR_BLEN256_Msk       /* AXI Burst Length 256 */
+#define ETH_DMASBMR_BLEN128_Pos                       (6U)
+#define ETH_DMASBMR_BLEN128_Msk                       (0x1UL << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
+#define ETH_DMASBMR_BLEN128                           ETH_DMASBMR_BLEN128_Msk       /* AXI Burst Length 128 */
+#define ETH_DMASBMR_BLEN64_Pos                        (5U)
+#define ETH_DMASBMR_BLEN64_Msk                        (0x1UL << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
+#define ETH_DMASBMR_BLEN64                            ETH_DMASBMR_BLEN64_Msk       /* AXI Burst Length 64 */
+#define ETH_DMASBMR_BLEN32_Pos                        (4U)
+#define ETH_DMASBMR_BLEN32_Msk                        (0x1UL << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
+#define ETH_DMASBMR_BLEN32                            ETH_DMASBMR_BLEN32_Msk       /* AXI Burst Length 32 */
+#define ETH_DMASBMR_BLEN16_Pos                        (3U)
+#define ETH_DMASBMR_BLEN16_Msk                        (0x1UL << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
+#define ETH_DMASBMR_BLEN16                            ETH_DMASBMR_BLEN16_Msk       /* AXI Burst Length 16 */
+#define ETH_DMASBMR_BLEN8_Pos                         (2U)
+#define ETH_DMASBMR_BLEN8_Msk                         (0x1UL << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
+#define ETH_DMASBMR_BLEN8                             ETH_DMASBMR_BLEN8_Msk       /* AXI Burst Length 8 */
+#define ETH_DMASBMR_BLEN4_Pos                         (1U)
+#define ETH_DMASBMR_BLEN4_Msk                         (0x1UL << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
+#define ETH_DMASBMR_BLEN4                             ETH_DMASBMR_BLEN4_Msk       /* AXI Burst Length 4 */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/************ Bit definition for Ethernet DMA Interrupt Status Register   ***************/
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMAC1IS_Pos                        (1U)
+#define ETH_DMAISR_DMAC1IS_Msk                        (0x1UL << ETH_DMAISR_DMAC1IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC1IS                            ETH_DMAISR_DMAC1IS_Msk    /* DMA Channel 1 Interrupt Status */
+#define ETH_DMAISR_DMAC0IS_Pos                        (0U)
+#define ETH_DMAISR_DMAC0IS_Msk                        (0x1UL << ETH_DMAISR_DMAC0IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC0IS                            ETH_DMAISR_DMAC0IS_Msk    /* DMA Channel 0 Interrupt Status */
+
+/************ Bit definition for Ethernet DMA Debug Status Register   ***************/
+#define ETH_DMADSR_TPS1_Pos                            (20U)
+#define ETH_DMADSR_TPS1_Msk                            (0xFUL << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
+#define ETH_DMADSR_TPS1                                ETH_DMADSR_TPS1_Msk       /* DMA Channel 1 Transmit Process State */
+#define ETH_DMADSR_TPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS1_FETCHING_Pos                   (20U)
+#define ETH_DMADSR_TPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS1_FETCHING_Pos) /*!< 0x00100000 */
+#define ETH_DMADSR_TPS1_FETCHING                       ETH_DMADSR_TPS1_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS1_WAITING_Pos                    (21U)
+#define ETH_DMADSR_TPS1_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS1_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_DMADSR_TPS1_WAITING                        ETH_DMADSR_TPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS1_READING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_READING_Msk                    (0x3UL << ETH_DMADSR_TPS1_READING_Pos) /*!< 0x00300000 */
+#define ETH_DMADSR_TPS1_READING                        ETH_DMADSR_TPS1_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos               (22U)
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos) /*!< 0x00400000 */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR                   ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS1_SUSPENDED_Pos                  (21U)
+#define ETH_DMADSR_TPS1_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS1_SUSPENDED_Pos) /*!< 0x00600000 */
+#define ETH_DMADSR_TPS1_SUSPENDED                      ETH_DMADSR_TPS1_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS1_CLOSING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS1_CLOSING_Pos) /*!< 0x00700000 */
+#define ETH_DMADSR_TPS1_CLOSING                        ETH_DMADSR_TPS1_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS1_Pos                            (16U)
+#define ETH_DMADSR_RPS1_Msk                            (0xFUL << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
+#define ETH_DMADSR_RPS1                                ETH_DMADSR_RPS1_Msk       /* DMA Channel 1 Receive Process State */
+#define ETH_DMADSR_RPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS1_FETCHING_Pos                   (16U)
+#define ETH_DMADSR_RPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS1_FETCHING_Pos) /*!< 0x00010000 */
+#define ETH_DMADSR_RPS1_FETCHING                       ETH_DMADSR_RPS1_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS1_WAITING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS1_WAITING_Pos) /*!< 0x00030000 */
+#define ETH_DMADSR_RPS1_WAITING                        ETH_DMADSR_RPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS1_SUSPENDED_Pos                  (18U)
+#define ETH_DMADSR_RPS1_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS1_SUSPENDED_Pos) /*!< 0x00040000 */
+#define ETH_DMADSR_RPS1_SUSPENDED                      ETH_DMADSR_RPS1_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS1_CLOSING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS1_CLOSING_Pos) /*!< 0x00050000 */
+#define ETH_DMADSR_RPS1_CLOSING                        ETH_DMADSR_RPS1_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos               (17U)
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos) /*!< 0x00060000 */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR                   ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS1_TRANSFERRING_Pos               (16U)
+#define ETH_DMADSR_RPS1_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS1_TRANSFERRING_Pos) /*!< 0x00070000 */
+#define ETH_DMADSR_RPS1_TRANSFERRING                   ETH_DMADSR_RPS1_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_TPS0_Pos                            (12U)
+#define ETH_DMADSR_TPS0_Msk                            (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS0                                ETH_DMADSR_TPS0_Msk       /* DMA Channel 0 Transmit Process State */
+#define ETH_DMADSR_TPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS0_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS0_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS0_FETCHING                       ETH_DMADSR_TPS0_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS0_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS0_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS0_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS0_WAITING                        ETH_DMADSR_TPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS0_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_READING_Msk                    (0x3UL << ETH_DMADSR_TPS0_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS0_READING                        ETH_DMADSR_TPS0_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR                   ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS0_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS0_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS0_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS0_SUSPENDED                      ETH_DMADSR_TPS0_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS0_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS0_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS0_CLOSING                        ETH_DMADSR_TPS0_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS0_Pos                            (8U)
+#define ETH_DMADSR_RPS0_Msk                            (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS0                                ETH_DMADSR_RPS0_Msk       /* DMA Channel 0 Receive Process State */
+#define ETH_DMADSR_RPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS0_FETCHING_Pos                   (8U)
+#define ETH_DMADSR_RPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS0_FETCHING_Pos) /*!< 0x00000100 */
+#define ETH_DMADSR_RPS0_FETCHING                       ETH_DMADSR_RPS0_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS0_WAITING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS0_WAITING_Pos) /*!< 0x00000300 */
+#define ETH_DMADSR_RPS0_WAITING                        ETH_DMADSR_RPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS0_SUSPENDED_Pos                  (10U)
+#define ETH_DMADSR_RPS0_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS0_SUSPENDED_Pos) /*!< 0x00000400 */
+#define ETH_DMADSR_RPS0_SUSPENDED                      ETH_DMADSR_RPS0_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS0_CLOSING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS0_CLOSING_Pos) /*!< 0x00000500 */
+#define ETH_DMADSR_RPS0_CLOSING                        ETH_DMADSR_RPS0_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos               (9U)
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos) /*!< 0x00000600 */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR                   ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS0_TRANSFERRING_Pos               (8U)
+#define ETH_DMADSR_RPS0_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS0_TRANSFERRING_Pos) /*!< 0x00000700 */
+#define ETH_DMADSR_RPS0_TRANSFERRING                   ETH_DMADSR_RPS0_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_AXRHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXRHSTS_Msk                         (0x1UL << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
+#define ETH_DMADSR_AXRHSTS                             ETH_DMADSR_AXRHSTS_Msk /* AXI Master Read Channel Status */
+#define ETH_DMADSR_AXWHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXWHSTS_Msk                         (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
+#define ETH_DMADSR_AXWHSTS                             ETH_DMADSR_AXWHSTS_Msk /* AXI Master Write Channel */
+
+/************ Bit definition for Ethernet DMA AXI4 transmit channel ACE control Register   ***************/
+#define ETH_DMAA4TXACR_THC_Pos                         (16U)
+#define ETH_DMAA4TXACR_THC_Msk                         (0xFUL << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4TXACR_THC                             ETH_DMAA4TXACR_THC_Msk       /* Transmit DMA First Packet Buffer or TSO Header Cache Control */
+#define ETH_DMAA4TXACR_TEC_Pos                         (8U)
+#define ETH_DMAA4TXACR_TEC_Msk                         (0xFUL << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4TXACR_TEC                             ETH_DMAA4TXACR_TEC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+#define ETH_DMAA4TXACR_TDRC_Pos                        (0U)
+#define ETH_DMAA4TXACR_TDRC_Msk                        (0xFUL << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4TXACR_TDRC                            ETH_DMAA4TXACR_TDRC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 receive channel ACE control Register   ***************/
+#define ETH_DMAA4RXACR_RDC_Pos                         (24U)
+#define ETH_DMAA4RXACR_RDC_Msk                         (0xFUL << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
+#define ETH_DMAA4RXACR_RDC                             ETH_DMAA4RXACR_RDC_Msk       /* Receive DMA Buffer Cache Control */
+#define ETH_DMAA4RXACR_RHC_Pos                         (16U)
+#define ETH_DMAA4RXACR_RHC_Msk                         (0xFUL << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4RXACR_RHC                             ETH_DMAA4RXACR_RHC_Msk       /* Receive DMA Header Cache Control */
+#define ETH_DMAA4RXACR_RPC_Pos                         (8U)
+#define ETH_DMAA4RXACR_RPC_Msk                         (0xFUL << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4RXACR_RPC                             ETH_DMAA4RXACR_RPC_Msk       /* Receive DMA Payload Cache Control */
+#define ETH_DMAA4RXACR_RDWC_Pos                        (0U)
+#define ETH_DMAA4RXACR_RDWC_Msk                        (0xFUL << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4RXACR_RDWC                            ETH_DMAA4RXACR_RDWC_Msk   /* Receive DMA Write Descriptor Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 descriptor ACE control Register   ***************/
+#define ETH_DMAA4DACR_RDRC_Pos                         (8U)
+#define ETH_DMAA4DACR_RDRC_Msk                         (0xFUL << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4DACR_RDRC                             ETH_DMAA4DACR_RDRC_Msk       /* Receive DMA Read Descriptor Cache control */
+#define ETH_DMAA4DACR_TDWD_Pos                         (4U)
+#define ETH_DMAA4DACR_TDWD_Msk                         (0xFUL << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
+#define ETH_DMAA4DACR_TDWD                             ETH_DMAA4DACR_TDWD_Msk       /* Transmit DMA Write Descriptor Domain control */
+#define ETH_DMAA4DACR_TDWC_Pos                         (0U)
+#define ETH_DMAA4DACR_TDWC_Msk                         (0xFUL << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4DACR_TDWC                             ETH_DMAA4DACR_TDWC_Msk       /* Transmit DMA Write Descriptor Cache control */
+
+/************ Bit definition for Ethernet DMA AXI4 LPI Entry Interval Register   ***************/
+/* Bit definition for Ethernet DMA AXI4 LPI Entry Interval register */
+#define ETH_DMALPIEI_LPIEI_Pos                         (0U)
+#define ETH_DMALPIEI_LPIEI_Msk                         (0xFUL << ETH_DMALPIEI_LPIEI_Pos) /*!< 0x0000000F */
+#define ETH_DMALPIEI_LPIEI                             ETH_DMALPIEI_LPIEI_Msk   /* LPI Entry Interval */
+
+/************ Bit definition for Ethernet DMA TBS control Register   ***************/
+#define ETH_DMATBSCTRL0R_FTOS_Pos                      (8U)
+#define ETH_DMATBSCTRL0R_FTOS_Msk                      (0xFFFFFFUL << ETH_DMATBSCTRL0R_FTOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_DMATBSCTRL0R_FTOS                          ETH_DMATBSCTRL0R_FTOS_Msk   /* Fetch time offset */
+#define ETH_DMATBSCTRL0R_FGOS_Pos                      (4U)
+#define ETH_DMATBSCTRL0R_FGOS_Msk                      (0x7UL << ETH_DMATBSCTRL0R_FGOS_Pos) /*!< 0x00000070 */
+#define ETH_DMATBSCTRL0R_FGOS                          ETH_DMATBSCTRL0R_FGOS_Msk   /* Fetch GSN offset */
+#define ETH_DMATBSCTRL0R_FTOV_Pos                      (0U)
+#define ETH_DMATBSCTRL0R_FTOV_Msk                      (0x1UL << ETH_DMATBSCTRL0R_FTOV_Pos) /*!< 0x00000001 */
+#define ETH_DMATBSCTRL0R_FTOV                          ETH_DMATBSCTRL0R_FTOV_Msk   /* Fetch time offset valid */
+
+/************ Bit definition for Ethernet DMA Channel x Control Register   ***************/
+#define ETH_DMACxCR_DSL_Pos                            (18U)
+#define ETH_DMACxCR_DSL_Msk                            (0x7UL << ETH_DMACxCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACxCR_DSL                                ETH_DMACxCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACxCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACxCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACxCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACxCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACxCR_PBLX8_Pos                          (16U)
+#define ETH_DMACxCR_PBLX8_Msk                          (0x1UL << ETH_DMACxCR_PBLX8_Pos) /*!< 0x00010000 */
+#define ETH_DMACxCR_PBLX8                              ETH_DMACxCR_PBLX8_Msk  /* 8xPBL mode */
+#define ETH_DMACxCR_MSS_Pos                            (0U)
+#define ETH_DMACxCR_MSS_Msk                            (0x3FFFUL << ETH_DMACxCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACxCR_MSS                                ETH_DMACxCR_MSS_Msk       /* Maximum Segment Size */
+
+/************ Bit definition for Ethernet DMA Channel x transmit control Register   ***************/
+#define ETH_DMACxTXCR_EDSE_Pos                         (28U)
+#define ETH_DMACxTXCR_EDSE_Msk                         (0x1UL << ETH_DMACxTXCR_EDSE_Pos) /*!< 0x10000000 */
+#define ETH_DMACxTXCR_EDSE                             ETH_DMACxTXCR_EDSE_Msk       /* Enhanced Descriptor Enable */
+#define ETH_DMACxTXCR_TQOS_Pos                         (24U)
+#define ETH_DMACxTXCR_TQOS_Msk                         (0xFUL << ETH_DMACxTXCR_TQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxTXCR_TQOS                             ETH_DMACxTXCR_TQOS_Msk       /* Transmit QOS */
+#define ETH_DMACxTXCR_TXPBL_Pos                        (16U)
+#define ETH_DMACxTXCR_TXPBL_Msk                        (0x3FUL << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxTXCR_TXPBL                            ETH_DMACxTXCR_TXPBL_Msk       /* Transmit Programmable Burst Length */
+#define ETH_DMACxTXCR_TXPBL_1PBL                       (0x1U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00010000 */
+#define ETH_DMACxTXCR_TXPBL_2PBL                       (0x2U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00020000 */
+#define ETH_DMACxTXCR_TXPBL_4PBL                       (0x4U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00040000 */
+#define ETH_DMACxTXCR_TXPBL_8PBL                       (0x8U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00080000 */
+#define ETH_DMACxTXCR_TXPBL_16PBL                      (0x10U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00100000 */
+#define ETH_DMACxTXCR_TXPBL_32PBL                      (0x20U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00200000 */
+#define ETH_DMACxTXCR_IPBL_Pos                         (15U)
+#define ETH_DMACxTXCR_IPBL_Msk                         (0x1UL << ETH_DMACxTXCR_IPBL_Pos) /*!< 0x00008000 */
+#define ETH_DMACxTXCR_IPBL                             ETH_DMACxTXCR_IPBL_Msk       /* Ignore PBL Requirement */
+#define ETH_DMACxTXCR_TSE_Pos                          (12U)
+#define ETH_DMACxTXCR_TSE_Msk                          (0x1UL << ETH_DMACxTXCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxTXCR_TSE                              ETH_DMACxTXCR_TSE_Msk       /* TCP Segmentation Enabled */
+#define ETH_DMACxTXCR_OSF_Pos                          (4U)
+#define ETH_DMACxTXCR_OSF_Msk                          (0x1UL << ETH_DMACxTXCR_OSF_Pos) /*!< 0x00000010 */
+#define ETH_DMACxTXCR_OSF                              ETH_DMACxTXCR_OSF_Msk       /* Operate on Second Packet */
+#define ETH_DMACxTXCR_TCW_Pos                          (1U)
+#define ETH_DMACxTXCR_TCW_Msk                          (0x7UL << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000E */
+#define ETH_DMACxTXCR_TCW                              ETH_DMACxTXCR_TCW_Msk       /* Transmit Channel Weight */
+#define ETH_DMACxTXCR_TCW_1                            (0x1U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000002 */
+#define ETH_DMACxTXCR_TCW_2                            (0x2U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000004 */
+#define ETH_DMACxTXCR_TCW_3                            (0x3U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000006 */
+#define ETH_DMACxTXCR_TCW_4                            (0x4U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000008 */
+#define ETH_DMACxTXCR_TCW_5                            (0x5U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000A */
+#define ETH_DMACxTXCR_TCW_6                            (0x6U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000C */
+#define ETH_DMACxTXCR_TCW_7                            (0x7U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000E */
+#define ETH_DMACxTXCR_ST_Pos                           (0U)
+#define ETH_DMACxTXCR_ST_Msk                           (0x1UL << ETH_DMACxTXCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACxTXCR_ST                               ETH_DMACxTXCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/************ Bit definition for Ethernet DMA Channel x receive control Register   ***************/
+#define ETH_DMACxRXCR_RPF_Pos                         (31U)
+#define ETH_DMACxRXCR_RPF_Msk                         (0x1UL << ETH_DMACxRXCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACxRXCR_RPF                             ETH_DMACxRXCR_RPF_Msk       /* DMA Rx Channel Packet Flush */
+#define ETH_DMACxRXCR_RQOS_Pos                        (24U)
+#define ETH_DMACxRXCR_RQOS_Msk                        (0xFUL << ETH_DMACxRXCR_RQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxRXCR_RQOS                            ETH_DMACxRXCR_RQOS_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_Pos                       (16U)
+#define ETH_DMACxRXCR_RXPBL_Msk                       (0x3FUL << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxRXCR_RXPBL                           ETH_DMACxRXCR_RXPBL_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_1PBL                      (0x1U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00010000 */
+#define ETH_DMACxRXCR_RXPBL_2PBL                      (0x2U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00020000 */
+#define ETH_DMACxRXCR_RXPBL_4PBL                      (0x4U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00040000 */
+#define ETH_DMACxRXCR_RXPBL_8PBL                      (0x8U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00080000 */
+#define ETH_DMACxRXCR_RXPBL_16PBL                     (0x10U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00100000 */
+#define ETH_DMACxRXCR_RXPBL_32PBL                     (0x20U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00200000 */
+#define ETH_DMACxRXCR_RBSZ_Pos                        (1U)
+#define ETH_DMACxRXCR_RBSZ_Msk                        (0x1FFFUL << ETH_DMACxRXCR_RBSZ_Pos) /*!< 0x00003FFE */
+#define ETH_DMACxRXCR_RBSZ                            ETH_DMACxRXCR_RBSZ_Msk       /* Receive Buffer size */
+#define ETH_DMACxRXCR_SR_Pos                          (0U)
+#define ETH_DMACxRXCR_SR_Msk                          (0x1UL << ETH_DMACxRXCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACxRXCR_SR                              ETH_DMACxRXCR_SR_Msk       /* Start or Stop Receive */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor list address Register   ***************/
+#define ETH_DMACxTXDLAR_TDESLA_Pos                    (0U)
+#define ETH_DMACxTXDLAR_TDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDLAR_TDESLA                        ETH_DMACxTXDLAR_TDESLA_Msk   /* Start of Transmit List */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor list address Register   ***************/
+#define ETH_DMACxRXDLAR_RDESLA_Pos                    (0U)
+#define ETH_DMACxRXDLAR_RDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDLAR_RDESLA                        ETH_DMACxRXDLAR_RDESLA_Msk   /* Start of Receive List */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor tail pointer Register   ***************/
+#define ETH_DMACxTXDTPR_TDT_Pos                       (0U)
+#define ETH_DMACxTXDTPR_TDT_Msk                       (0xFFFFFFFFUL << ETH_DMACxTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDTPR_TDT                           ETH_DMACxTXDTPR_TDT_Msk   /* Transmit Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor tail pointer Register   ***************/
+#define ETH_DMACxRXDTPR_TDT_Pos                      (0U)
+#define ETH_DMACxRXDTPR_TDT_Msk                      (0xFFFFFFFFUL << ETH_DMACxRXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDTPR_TDT                          ETH_DMACxRXDTPR_TDT_Msk   /* Receive Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor ring length Register   ***************/
+#define ETH_DMACxTXRLR_TDRL_Pos                       (0U)
+#define ETH_DMACxTXRLR_TDRL_Msk                       (0x3FFUL << ETH_DMACxTXRLR_TDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxTXRLR_TDRL                           ETH_DMACxTXRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor ring length Register   ***************/
+#define ETH_DMACxRXRLR_ARBS_Pos                       (17U)
+#define ETH_DMACxRXRLR_ARBS_Msk                       (0x7FUL << ETH_DMACxRXRLR_ARBS_Pos) /*!< 0x000FE0000 */
+#define ETH_DMACxRXRLR_ARBS                           ETH_DMACxRXRLR_ARBS_Msk   /* Alternate Receive Buffer Size */
+#define ETH_DMACxRXRLR_RDRL_Pos                       (0U)
+#define ETH_DMACxRXRLR_RDRL_Msk                       (0x3FFUL << ETH_DMACxRXRLR_RDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxRXRLR_RDRL                           ETH_DMACxRXRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Interrupt Enable Register   ***************/
+#define ETH_DMACxIER_NIE_Pos                           (15U)
+#define ETH_DMACxIER_NIE_Msk                           (0x1UL << ETH_DMACxIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACxIER_NIE                               ETH_DMACxIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACxIER_AIE_Pos                           (14U)
+#define ETH_DMACxIER_AIE_Msk                           (0x1UL << ETH_DMACxIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACxIER_AIE                               ETH_DMACxIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACxIER_CDEE_Pos                          (13U)
+#define ETH_DMACxIER_CDEE_Msk                          (0x1UL << ETH_DMACxIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxIER_CDEE                              ETH_DMACxIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACxIER_FBEE_Pos                          (12U)
+#define ETH_DMACxIER_FBEE_Msk                          (0x1UL << ETH_DMACxIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxIER_FBEE                              ETH_DMACxIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACxIER_ERIE_Pos                          (11U)
+#define ETH_DMACxIER_ERIE_Msk                          (0x1UL << ETH_DMACxIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACxIER_ERIE                              ETH_DMACxIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACxIER_ETIE_Pos                          (10U)
+#define ETH_DMACxIER_ETIE_Msk                          (0x1UL << ETH_DMACxIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACxIER_ETIE                              ETH_DMACxIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACxIER_RWTE_Pos                          (9U)
+#define ETH_DMACxIER_RWTE_Msk                          (0x1UL << ETH_DMACxIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACxIER_RWTE                              ETH_DMACxIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACxIER_RSE_Pos                           (8U)
+#define ETH_DMACxIER_RSE_Msk                           (0x1UL << ETH_DMACxIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACxIER_RSE                               ETH_DMACxIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACxIER_RBUE_Pos                          (7U)
+#define ETH_DMACxIER_RBUE_Msk                          (0x1UL << ETH_DMACxIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACxIER_RBUE                              ETH_DMACxIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACxIER_RIE_Pos                           (6U)
+#define ETH_DMACxIER_RIE_Msk                           (0x1UL << ETH_DMACxIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACxIER_RIE                               ETH_DMACxIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACxIER_TBUE_Pos                          (2U)
+#define ETH_DMACxIER_TBUE_Msk                          (0x1UL << ETH_DMACxIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACxIER_TBUE                              ETH_DMACxIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACxIER_TXSE_Pos                          (1U)
+#define ETH_DMACxIER_TXSE_Msk                          (0x1UL << ETH_DMACxIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACxIER_TXSE                              ETH_DMACxIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACxIER_TIE_Pos                           (0U)
+#define ETH_DMACxIER_TIE_Msk                           (0x1UL << ETH_DMACxIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACxIER_TIE                               ETH_DMACxIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/************ Bit definition for Ethernet DMA Channel x Rx Interrupt Watchdog Timer Register   ***************/
+#define ETH_DMACxRXIWTR_RWTU_Pos                        (16U)
+#define ETH_DMACxRXIWTR_RWTU_Msk                        (0x3UL << ETH_DMACxRXIWTR_RWTU_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU                            ETH_DMACxRXIWTR_RWTU_Msk    /* Receive Interrupt Watchdog Timer Count Units */
+#define ETH_DMACxRXIWTR_RWTU_256                        ((uint32_t)0x00000000)   /* 256 */
+#define ETH_DMACxRXIWTR_RWTU_512_Pos                    (16U)
+#define ETH_DMACxRXIWTR_RWTU_512_Msk                    (0x1UL << ETH_DMACxRXIWTR_RWTU_512_Pos) /*!< 0x00010000 */
+#define ETH_DMACxRXIWTR_RWTU_512                        ETH_DMACxRXIWTR_RWTU_512_Msk    /* 512 */
+#define ETH_DMACxRXIWTR_RWTU_1024_Pos                   (17U)
+#define ETH_DMACxRXIWTR_RWTU_1024_Msk                   (0x1UL << ETH_DMACxRXIWTR_RWTU_1024_Pos) /*!< 0x00020000 */
+#define ETH_DMACxRXIWTR_RWTU_1024                       ETH_DMACxRXIWTR_RWTU_1024_Msk    /* 1024 */
+#define ETH_DMACxRXIWTR_RWTU_2048_Pos                   (16U)
+#define ETH_DMACxRXIWTR_RWTU_2048_Msk                   (0x3UL << ETH_DMACxRXIWTR_RWTU_2048_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU_2048                       ETH_DMACxRXIWTR_RWTU_2048_Msk    /* 2048 */
+#define ETH_DMACxRXIWTR_RWT_Pos                         (0U)
+#define ETH_DMACxRXIWTR_RWT_Msk                         (0xFFUL << ETH_DMACxRXIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACxRXIWTR_RWT                             ETH_DMACxRXIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/************ Bit definition for Ethernet DMA Channel x slot function control status Register   ***************/
+#define ETH_DMACxSFCSR_RSN_Pos                        (16U)
+#define ETH_DMACxSFCSR_RSN_Msk                        (0xFUL << ETH_DMACxSFCSR_RSN_Pos) /*!< 0x000F0000 */
+#define ETH_DMACxSFCSR_RSN                            ETH_DMACxSFCSR_RSN_Msk    /* Reference Slot Number */
+#define ETH_DMACxSFCSR_SIV_Pos                        (4U)
+#define ETH_DMACxSFCSR_SIV_Msk                        (0xFFFUL << ETH_DMACxSFCSR_SIV_Pos) /*!< 0x0000FFF0 */
+#define ETH_DMACxSFCSR_SIV                            ETH_DMACxSFCSR_SIV_Msk    /* Slot Interval Value */
+#define ETH_DMACxSFCSR_ASC_Pos                        (1U)
+#define ETH_DMACxSFCSR_ASC_Msk                        (0x1UL << ETH_DMACxSFCSR_ASC_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSFCSR_ASC                            ETH_DMACxSFCSR_ASC_Msk    /* Advance Slot Check */
+#define ETH_DMACxSFCSR_ESC_Pos                        (0U)
+#define ETH_DMACxSFCSR_ESC_Msk                        (0x1UL << ETH_DMACxSFCSR_ESC_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSFCSR_ESC                            ETH_DMACxSFCSR_ESC_Msk    /* Enable Slot Comparison */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Desc Register   ***************/
+#define ETH_DMACxCATXDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACxCATXDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXDR_CURTDESAPTR                     ETH_DMACxCATXDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Desc Register   ***************/
+#define ETH_DMACxCARXDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACxCARXDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXDR_CURRDESAPTR                     ETH_DMACxCARXDR_CURRDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Buffer Register   ***************/
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXBR_CURTBUFAPTR                     ETH_DMACxCATXBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Buffer Register   ***************/
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXBR_CURRBUFAPTR                     ETH_DMACxCARXBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Status Register   ***************/
+#define ETH_DMACxSR_REB_Pos                            (19U)
+#define ETH_DMACxSR_REB_Msk                            (0x7UL << ETH_DMACxSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACxSR_REB                                ETH_DMACxSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACxSR_TEB_Pos                            (16U)
+#define ETH_DMACxSR_TEB_Msk                            (0x7UL << ETH_DMACxSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACxSR_TEB                                ETH_DMACxSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACxSR_NIS_Pos                            (15U)
+#define ETH_DMACxSR_NIS_Msk                            (0x1UL << ETH_DMACxSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACxSR_NIS                                ETH_DMACxSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACxSR_AIS_Pos                            (14U)
+#define ETH_DMACxSR_AIS_Msk                            (0x1UL << ETH_DMACxSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACxSR_AIS                                ETH_DMACxSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACxSR_CDE_Pos                            (13U)
+#define ETH_DMACxSR_CDE_Msk                            (0x1UL << ETH_DMACxSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxSR_CDE                                ETH_DMACxSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACxSR_FBE_Pos                            (12U)
+#define ETH_DMACxSR_FBE_Msk                            (0x1UL << ETH_DMACxSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxSR_FBE                                ETH_DMACxSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACxSR_ERI_Pos                            (11U)
+#define ETH_DMACxSR_ERI_Msk                            (0x1UL << ETH_DMACxSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACxSR_ERI                                ETH_DMACxSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACxSR_ETI_Pos                            (10U)
+#define ETH_DMACxSR_ETI_Msk                            (0x1UL << ETH_DMACxSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACxSR_ETI                                ETH_DMACxSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACxSR_RWT_Pos                            (9U)
+#define ETH_DMACxSR_RWT_Msk                            (0x1UL << ETH_DMACxSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACxSR_RWT                                ETH_DMACxSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACxSR_RPS_Pos                            (8U)
+#define ETH_DMACxSR_RPS_Msk                            (0x1UL << ETH_DMACxSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACxSR_RPS                                ETH_DMACxSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACxSR_RBU_Pos                            (7U)
+#define ETH_DMACxSR_RBU_Msk                            (0x1UL << ETH_DMACxSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACxSR_RBU                                ETH_DMACxSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACxSR_RI_Pos                             (6U)
+#define ETH_DMACxSR_RI_Msk                             (0x1UL << ETH_DMACxSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACxSR_RI                                 ETH_DMACxSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACxSR_TBU_Pos                            (2U)
+#define ETH_DMACxSR_TBU_Msk                            (0x1UL << ETH_DMACxSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACxSR_TBU                                ETH_DMACxSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACxSR_TPS_Pos                            (1U)
+#define ETH_DMACxSR_TPS_Msk                            (0x1UL << ETH_DMACxSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSR_TPS                                ETH_DMACxSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACxSR_TI_Pos                             (0U)
+#define ETH_DMACxSR_TI_Msk                             (0x1UL << ETH_DMACxSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSR_TI                                 ETH_DMACxSR_TI_Msk        /* Transmit Interrupt */
+
+/************ Bit definition for Ethernet DMA Channel x missed frame count Register   ***************/
+#define ETH_DMACxMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACxMFCR_MFCO_Msk                         (0x1UL << ETH_DMACxMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACxMFCR_MFCO                             ETH_DMACxMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACxMFCR_MFC_Pos                          (0U)
+#define ETH_DMACxMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACxMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACxMFCR_MFC                              ETH_DMACxMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_RTSR1 register  *****************/
+#define EXTI_RTSR1_RT0_Pos           (0U)
+#define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
+#define EXTI_RTSR1_RT1_Pos           (1U)
+#define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
+#define EXTI_RTSR1_RT2_Pos           (2U)
+#define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
+#define EXTI_RTSR1_RT3_Pos           (3U)
+#define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
+#define EXTI_RTSR1_RT4_Pos           (4U)
+#define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
+#define EXTI_RTSR1_RT5_Pos           (5U)
+#define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
+#define EXTI_RTSR1_RT6_Pos           (6U)
+#define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
+#define EXTI_RTSR1_RT7_Pos           (7U)
+#define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
+#define EXTI_RTSR1_RT8_Pos           (8U)
+#define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
+#define EXTI_RTSR1_RT9_Pos           (9U)
+#define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
+#define EXTI_RTSR1_RT10_Pos          (10U)
+#define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
+#define EXTI_RTSR1_RT11_Pos          (11U)
+#define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
+#define EXTI_RTSR1_RT12_Pos          (12U)
+#define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
+#define EXTI_RTSR1_RT13_Pos          (13U)
+#define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
+#define EXTI_RTSR1_RT14_Pos          (14U)
+#define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
+#define EXTI_RTSR1_RT15_Pos          (15U)
+#define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
+#define EXTI_RTSR1_RT20_Pos          (20U)
+#define EXTI_RTSR1_RT20_Msk          (0x1UL << EXTI_RTSR1_RT20_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20              EXTI_RTSR1_RT20_Msk                       /*!< Rising trigger configuration for input line 20 */
+#define EXTI_RTSR1_RT21_Pos          (21U)
+#define EXTI_RTSR1_RT21_Msk          (0x1UL << EXTI_RTSR1_RT21_Pos)            /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21              EXTI_RTSR1_RT21_Msk                       /*!< Rising trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_FTSR1 register  *****************/
+#define EXTI_FTSR1_FT0_Pos           (0U)
+#define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
+#define EXTI_FTSR1_FT1_Pos           (1U)
+#define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
+#define EXTI_FTSR1_FT2_Pos           (2U)
+#define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
+#define EXTI_FTSR1_FT3_Pos           (3U)
+#define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
+#define EXTI_FTSR1_FT4_Pos           (4U)
+#define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
+#define EXTI_FTSR1_FT5_Pos           (5U)
+#define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
+#define EXTI_FTSR1_FT6_Pos           (6U)
+#define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
+#define EXTI_FTSR1_FT7_Pos           (7U)
+#define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
+#define EXTI_FTSR1_FT8_Pos           (8U)
+#define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
+#define EXTI_FTSR1_FT9_Pos           (9U)
+#define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
+#define EXTI_FTSR1_FT10_Pos          (10U)
+#define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
+#define EXTI_FTSR1_FT11_Pos          (11U)
+#define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
+#define EXTI_FTSR1_FT12_Pos          (12U)
+#define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
+#define EXTI_FTSR1_FT13_Pos          (13U)
+#define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
+#define EXTI_FTSR1_FT14_Pos          (14U)
+#define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
+#define EXTI_FTSR1_FT15_Pos          (15U)
+#define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
+#define EXTI_FTSR1_FT20_Pos          (20U)
+#define EXTI_FTSR1_FT20_Msk          (0x1UL << EXTI_FTSR1_FT20_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20              EXTI_FTSR1_FT20_Msk                       /*!< Falling trigger configuration for input line 20 */
+#define EXTI_FTSR1_FT21_Pos          (21U)
+#define EXTI_FTSR1_FT21_Msk          (0x1UL << EXTI_FTSR1_FT21_Pos)            /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21              EXTI_FTSR1_FT21_Msk                       /*!< Falling trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_SWIER1 register  ****************/
+#define EXTI_SWIER1_SWI0_Pos         (0U)
+#define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos         (1U)
+#define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos         (2U)
+#define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos         (3U)
+#define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos         (4U)
+#define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos         (5U)
+#define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos         (6U)
+#define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos         (7U)
+#define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos         (8U)
+#define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos         (9U)
+#define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos        (10U)
+#define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos        (11U)
+#define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos        (12U)
+#define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos        (13U)
+#define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos        (14U)
+#define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos        (15U)
+#define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI20_Pos        (20U)
+#define EXTI_SWIER1_SWI20_Msk        (0x1UL << EXTI_SWIER1_SWI20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20            EXTI_SWIER1_SWI20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos        (21U)
+#define EXTI_SWIER1_SWI21_Msk        (0x1UL << EXTI_SWIER1_SWI21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21            EXTI_SWIER1_SWI21_Msk                     /*!< Software Interrupt on line 21 */
+
+/*******************  Bit definition for EXTI_RPR1 register  ******************/
+#define EXTI_RPR1_RPIF0_Pos          (0U)
+#define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
+#define EXTI_RPR1_RPIF1_Pos          (1U)
+#define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
+#define EXTI_RPR1_RPIF2_Pos          (2U)
+#define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
+#define EXTI_RPR1_RPIF3_Pos          (3U)
+#define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
+#define EXTI_RPR1_RPIF4_Pos          (4U)
+#define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
+#define EXTI_RPR1_RPIF5_Pos          (5U)
+#define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
+#define EXTI_RPR1_RPIF6_Pos          (6U)
+#define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
+#define EXTI_RPR1_RPIF7_Pos          (7U)
+#define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
+#define EXTI_RPR1_RPIF8_Pos          (8U)
+#define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
+#define EXTI_RPR1_RPIF9_Pos          (9U)
+#define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
+#define EXTI_RPR1_RPIF10_Pos         (10U)
+#define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
+#define EXTI_RPR1_RPIF11_Pos         (11U)
+#define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
+#define EXTI_RPR1_RPIF12_Pos         (12U)
+#define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
+#define EXTI_RPR1_RPIF13_Pos         (13U)
+#define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
+#define EXTI_RPR1_RPIF14_Pos         (14U)
+#define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
+#define EXTI_RPR1_RPIF15_Pos         (15U)
+#define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
+#define EXTI_RPR1_RPIF20_Pos         (20U)
+#define EXTI_RPR1_RPIF20_Msk         (0x1UL << EXTI_RPR1_RPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_RPR1_RPIF20             EXTI_RPR1_RPIF20_Msk                      /*!< Rising Pending Interrupt Flag on line 20 */
+#define EXTI_RPR1_RPIF21_Pos         (21U)
+#define EXTI_RPR1_RPIF21_Msk         (0x1UL << EXTI_RPR1_RPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_RPR1_RPIF21             EXTI_RPR1_RPIF21_Msk                      /*!< Rising Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_FPR1 register  ******************/
+#define EXTI_FPR1_FPIF0_Pos          (0U)
+#define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
+#define EXTI_FPR1_FPIF1_Pos          (1U)
+#define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
+#define EXTI_FPR1_FPIF2_Pos          (2U)
+#define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
+#define EXTI_FPR1_FPIF3_Pos          (3U)
+#define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
+#define EXTI_FPR1_FPIF4_Pos          (4U)
+#define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
+#define EXTI_FPR1_FPIF5_Pos          (5U)
+#define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
+#define EXTI_FPR1_FPIF6_Pos          (6U)
+#define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
+#define EXTI_FPR1_FPIF7_Pos          (7U)
+#define EXTI_FPR1_FPIF7_Msk           (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
+#define EXTI_FPR1_FPIF8_Pos          (8U)
+#define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
+#define EXTI_FPR1_FPIF9_Pos          (9U)
+#define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
+#define EXTI_FPR1_FPIF10_Pos         (10U)
+#define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
+#define EXTI_FPR1_FPIF11_Pos         (11U)
+#define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
+#define EXTI_FPR1_FPIF12_Pos         (12U)
+#define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
+#define EXTI_FPR1_FPIF13_Pos         (13U)
+#define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
+#define EXTI_FPR1_FPIF14_Pos         (14U)
+#define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
+#define EXTI_FPR1_FPIF15_Pos         (15U)
+#define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
+#define EXTI_FPR1_FPIF20_Pos         (20U)
+#define EXTI_FPR1_FPIF20_Msk         (0x1UL << EXTI_FPR1_FPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_FPR1_FPIF20             EXTI_FPR1_FPIF20_Msk                      /*!< Falling Pending Interrupt Flag on line 20 */
+#define EXTI_FPR1_FPIF21_Pos         (21U)
+#define EXTI_FPR1_FPIF21_Msk         (0x1UL << EXTI_FPR1_FPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_FPR1_FPIF21             EXTI_FPR1_FPIF21_Msk                      /*!< Falling Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_SECCFGR1 register  ******************/
+#define EXTI_SECCFGR1_SEC0_Pos       (0U)
+#define EXTI_SECCFGR1_SEC0_Msk       (0x1UL << EXTI_SECCFGR1_SEC0_Pos)         /*!< 0x00000001 */
+#define EXTI_SECCFGR1_SEC0           EXTI_SECCFGR1_SEC0_Msk                    /*!< Security enable on line 0 */
+#define EXTI_SECCFGR1_SEC1_Pos       (1U)
+#define EXTI_SECCFGR1_SEC1_Msk       (0x1UL << EXTI_SECCFGR1_SEC1_Pos)         /*!< 0x00000002 */
+#define EXTI_SECCFGR1_SEC1           EXTI_SECCFGR1_SEC1_Msk                    /*!< Security enable on line 1 */
+#define EXTI_SECCFGR1_SEC2_Pos       (2U)
+#define EXTI_SECCFGR1_SEC2_Msk       (0x1UL << EXTI_SECCFGR1_SEC2_Pos)         /*!< 0x00000004 */
+#define EXTI_SECCFGR1_SEC2           EXTI_SECCFGR1_SEC2_Msk                    /*!< Security enable on line 2 */
+#define EXTI_SECCFGR1_SEC3_Pos       (3U)
+#define EXTI_SECCFGR1_SEC3_Msk       (0x1UL << EXTI_SECCFGR1_SEC3_Pos)         /*!< 0x00000008 */
+#define EXTI_SECCFGR1_SEC3           EXTI_SECCFGR1_SEC3_Msk                    /*!< Security enable on line 3 */
+#define EXTI_SECCFGR1_SEC4_Pos       (4U)
+#define EXTI_SECCFGR1_SEC4_Msk       (0x1UL << EXTI_SECCFGR1_SEC4_Pos)         /*!< 0x00000010 */
+#define EXTI_SECCFGR1_SEC4           EXTI_SECCFGR1_SEC4_Msk                    /*!< Security enable on line 4 */
+#define EXTI_SECCFGR1_SEC5_Pos       (5U)
+#define EXTI_SECCFGR1_SEC5_Msk       (0x1UL << EXTI_SECCFGR1_SEC5_Pos)         /*!< 0x00000020 */
+#define EXTI_SECCFGR1_SEC5           EXTI_SECCFGR1_SEC5_Msk                    /*!< Security enable on line 5 */
+#define EXTI_SECCFGR1_SEC6_Pos       (6U)
+#define EXTI_SECCFGR1_SEC6_Msk       (0x1UL << EXTI_SECCFGR1_SEC6_Pos)         /*!< 0x00000040 */
+#define EXTI_SECCFGR1_SEC6           EXTI_SECCFGR1_SEC6_Msk                    /*!< Security enable on line 6 */
+#define EXTI_SECCFGR1_SEC7_Pos       (7U)
+#define EXTI_SECCFGR1_SEC7_Msk       (0x1UL << EXTI_SECCFGR1_SEC7_Pos)         /*!< 0x00000080 */
+#define EXTI_SECCFGR1_SEC7           EXTI_SECCFGR1_SEC7_Msk                    /*!< Security enable on line 7 */
+#define EXTI_SECCFGR1_SEC8_Pos       (8U)
+#define EXTI_SECCFGR1_SEC8_Msk       (0x1UL << EXTI_SECCFGR1_SEC8_Pos)         /*!< 0x00000100 */
+#define EXTI_SECCFGR1_SEC8           EXTI_SECCFGR1_SEC8_Msk                    /*!< Security enable on line 8 */
+#define EXTI_SECCFGR1_SEC9_Pos       (9U)
+#define EXTI_SECCFGR1_SEC9_Msk       (0x1UL << EXTI_SECCFGR1_SEC9_Pos)         /*!< 0x00000200 */
+#define EXTI_SECCFGR1_SEC9           EXTI_SECCFGR1_SEC9_Msk                    /*!< Security enable on line 9 */
+#define EXTI_SECCFGR1_SEC10_Pos      (10U)
+#define EXTI_SECCFGR1_SEC10_Msk      (0x1UL << EXTI_SECCFGR1_SEC10_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR1_SEC10          EXTI_SECCFGR1_SEC10_Msk                   /*!< Security enable on line 10 */
+#define EXTI_SECCFGR1_SEC11_Pos      (11U)
+#define EXTI_SECCFGR1_SEC11_Msk      (0x1UL << EXTI_SECCFGR1_SEC11_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR1_SEC11          EXTI_SECCFGR1_SEC11_Msk                   /*!< Security enable on line 11 */
+#define EXTI_SECCFGR1_SEC12_Pos      (12U)
+#define EXTI_SECCFGR1_SEC12_Msk      (0x1UL << EXTI_SECCFGR1_SEC12_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR1_SEC12          EXTI_SECCFGR1_SEC12_Msk                   /*!< Security enable on line 12 */
+#define EXTI_SECCFGR1_SEC13_Pos      (13U)
+#define EXTI_SECCFGR1_SEC13_Msk      (0x1UL << EXTI_SECCFGR1_SEC13_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR1_SEC13          EXTI_SECCFGR1_SEC13_Msk                   /*!< Security enable on line 13 */
+#define EXTI_SECCFGR1_SEC14_Pos      (14U)
+#define EXTI_SECCFGR1_SEC14_Msk      (0x1UL << EXTI_SECCFGR1_SEC14_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR1_SEC14          EXTI_SECCFGR1_SEC14_Msk                   /*!< Security enable on line 14 */
+#define EXTI_SECCFGR1_SEC15_Pos      (15U)
+#define EXTI_SECCFGR1_SEC15_Msk      (0x1UL << EXTI_SECCFGR1_SEC15_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR1_SEC15          EXTI_SECCFGR1_SEC15_Msk                   /*!< Security enable on line 15 */
+#define EXTI_SECCFGR1_SEC17_Pos      (17U)
+#define EXTI_SECCFGR1_SEC17_Msk      (0x1UL << EXTI_SECCFGR1_SEC17_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR1_SEC17          EXTI_SECCFGR1_SEC17_Msk                   /*!< Security enable on line 17 */
+#define EXTI_SECCFGR1_SEC18_Pos      (18U)
+#define EXTI_SECCFGR1_SEC18_Msk      (0x1UL << EXTI_SECCFGR1_SEC18_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR1_SEC18          EXTI_SECCFGR1_SEC18_Msk                   /*!< Security enable on line 18 */
+#define EXTI_SECCFGR1_SEC19_Pos      (19U)
+#define EXTI_SECCFGR1_SEC19_Msk      (0x1UL << EXTI_SECCFGR1_SEC19_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR1_SEC19          EXTI_SECCFGR1_SEC19_Msk                   /*!< Security enable on line 19 */
+#define EXTI_SECCFGR1_SEC20_Pos      (20U)
+#define EXTI_SECCFGR1_SEC20_Msk      (0x1UL << EXTI_SECCFGR1_SEC20_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR1_SEC20          EXTI_SECCFGR1_SEC20_Msk                   /*!< Security enable on line 20 */
+#define EXTI_SECCFGR1_SEC21_Pos      (21U)
+#define EXTI_SECCFGR1_SEC21_Msk      (0x1UL << EXTI_SECCFGR1_SEC21_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR1_SEC21          EXTI_SECCFGR1_SEC21_Msk                   /*!< Security enable on line 21 */
+#define EXTI_SECCFGR1_SEC22_Pos      (22U)
+#define EXTI_SECCFGR1_SEC22_Msk      (0x1UL << EXTI_SECCFGR1_SEC22_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR1_SEC22          EXTI_SECCFGR1_SEC22_Msk                   /*!< Security enable on line 22 */
+#define EXTI_SECCFGR1_SEC23_Pos      (23U)
+#define EXTI_SECCFGR1_SEC23_Msk      (0x1UL << EXTI_SECCFGR1_SEC23_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR1_SEC23          EXTI_SECCFGR1_SEC23_Msk                   /*!< Security enable on line 23 */
+#define EXTI_SECCFGR1_SEC24_Pos      (24U)
+#define EXTI_SECCFGR1_SEC24_Msk      (0x1UL << EXTI_SECCFGR1_SEC24_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR1_SEC24          EXTI_SECCFGR1_SEC24_Msk                   /*!< Security enable on line 24 */
+#define EXTI_SECCFGR1_SEC25_Pos      (25U)
+#define EXTI_SECCFGR1_SEC25_Msk      (0x1UL << EXTI_SECCFGR1_SEC25_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR1_SEC25          EXTI_SECCFGR1_SEC25_Msk                   /*!< Security enable on line 25 */
+#define EXTI_SECCFGR1_SEC26_Pos      (26U)
+#define EXTI_SECCFGR1_SEC26_Msk      (0x1UL << EXTI_SECCFGR1_SEC26_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR1_SEC26          EXTI_SECCFGR1_SEC26_Msk                   /*!< Security enable on line 26 */
+#define EXTI_SECCFGR1_SEC27_Pos      (27U)
+#define EXTI_SECCFGR1_SEC27_Msk      (0x1UL << EXTI_SECCFGR1_SEC27_Pos)        /*!< 0x08000000 */
+#define EXTI_SECCFGR1_SEC27          EXTI_SECCFGR1_SEC27_Msk                   /*!< Security enable on line 27 */
+#define EXTI_SECCFGR1_SEC28_Pos      (28U)
+#define EXTI_SECCFGR1_SEC28_Msk      (0x1UL << EXTI_SECCFGR1_SEC28_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR1_SEC28          EXTI_SECCFGR1_SEC28_Msk                   /*!< Security enable on line 28 */
+#define EXTI_SECCFGR1_SEC29_Pos      (29U)
+#define EXTI_SECCFGR1_SEC29_Msk      (0x1UL << EXTI_SECCFGR1_SEC29_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR1_SEC29          EXTI_SECCFGR1_SEC29_Msk                   /*!< Security enable on line 29 */
+#define EXTI_SECCFGR1_SEC30_Pos      (30U)
+#define EXTI_SECCFGR1_SEC30_Msk      (0x1UL << EXTI_SECCFGR1_SEC30_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR1_SEC30          EXTI_SECCFGR1_SEC30_Msk                   /*!< Security enable on line 30 */
+#define EXTI_SECCFGR1_SEC31_Pos      (31U)
+#define EXTI_SECCFGR1_SEC31_Msk      (0x1UL << EXTI_SECCFGR1_SEC31_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR1_SEC31          EXTI_SECCFGR1_SEC31_Msk                   /*!< Security enable on line 31 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR1 register  ******************/
+#define EXTI_PRIVCFGR1_PRIV0_Pos     (0U)
+#define EXTI_PRIVCFGR1_PRIV0_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos)       /*!< 0x00000001 */
+#define EXTI_PRIVCFGR1_PRIV0         EXTI_PRIVCFGR1_PRIV0_Msk                  /*!< Privilege enable on line 0 */
+#define EXTI_PRIVCFGR1_PRIV1_Pos     (1U)
+#define EXTI_PRIVCFGR1_PRIV1_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos)       /*!< 0x00000002 */
+#define EXTI_PRIVCFGR1_PRIV1         EXTI_PRIVCFGR1_PRIV1_Msk                  /*!< Privilege enable on line 1 */
+#define EXTI_PRIVCFGR1_PRIV2_Pos     (2U)
+#define EXTI_PRIVCFGR1_PRIV2_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos)       /*!< 0x00000004 */
+#define EXTI_PRIVCFGR1_PRIV2         EXTI_PRIVCFGR1_PRIV2_Msk                  /*!< Privilege enable on line 2 */
+#define EXTI_PRIVCFGR1_PRIV3_Pos     (3U)
+#define EXTI_PRIVCFGR1_PRIV3_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos)       /*!< 0x00000008 */
+#define EXTI_PRIVCFGR1_PRIV3         EXTI_PRIVCFGR1_PRIV3_Msk                  /*!< Privilege enable on line 3 */
+#define EXTI_PRIVCFGR1_PRIV4_Pos     (4U)
+#define EXTI_PRIVCFGR1_PRIV4_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos)       /*!< 0x00000010 */
+#define EXTI_PRIVCFGR1_PRIV4         EXTI_PRIVCFGR1_PRIV4_Msk                  /*!< Privilege enable on line 4 */
+#define EXTI_PRIVCFGR1_PRIV5_Pos     (5U)
+#define EXTI_PRIVCFGR1_PRIV5_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos)       /*!< 0x00000020 */
+#define EXTI_PRIVCFGR1_PRIV5         EXTI_PRIVCFGR1_PRIV5_Msk                  /*!< Privilege enable on line 5 */
+#define EXTI_PRIVCFGR1_PRIV6_Pos     (6U)
+#define EXTI_PRIVCFGR1_PRIV6_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos)       /*!< 0x00000040 */
+#define EXTI_PRIVCFGR1_PRIV6         EXTI_PRIVCFGR1_PRIV6_Msk                  /*!< Privilege enable on line 6 */
+#define EXTI_PRIVCFGR1_PRIV7_Pos     (7U)
+#define EXTI_PRIVCFGR1_PRIV7_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos)       /*!< 0x00000080 */
+#define EXTI_PRIVCFGR1_PRIV7         EXTI_PRIVCFGR1_PRIV7_Msk                  /*!< Privilege enable on line 7 */
+#define EXTI_PRIVCFGR1_PRIV8_Pos     (8U)
+#define EXTI_PRIVCFGR1_PRIV8_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos)       /*!< 0x00000100 */
+#define EXTI_PRIVCFGR1_PRIV8         EXTI_PRIVCFGR1_PRIV8_Msk                  /*!< Privilege enable on line 8 */
+#define EXTI_PRIVCFGR1_PRIV9_Pos     (9U)
+#define EXTI_PRIVCFGR1_PRIV9_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos)       /*!< 0x00000200 */
+#define EXTI_PRIVCFGR1_PRIV9         EXTI_PRIVCFGR1_PRIV9_Msk                  /*!< Privilege enable on line 9 */
+#define EXTI_PRIVCFGR1_PRIV10_Pos    (10U)
+#define EXTI_PRIVCFGR1_PRIV10_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR1_PRIV10        EXTI_PRIVCFGR1_PRIV10_Msk                 /*!< Privilege enable on line 10 */
+#define EXTI_PRIVCFGR1_PRIV11_Pos    (11U)
+#define EXTI_PRIVCFGR1_PRIV11_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR1_PRIV11        EXTI_PRIVCFGR1_PRIV11_Msk                 /*!< Privilege enable on line 11 */
+#define EXTI_PRIVCFGR1_PRIV12_Pos    (12U)
+#define EXTI_PRIVCFGR1_PRIV12_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR1_PRIV12        EXTI_PRIVCFGR1_PRIV12_Msk                 /*!< Privilege enable on line 12 */
+#define EXTI_PRIVCFGR1_PRIV13_Pos    (13U)
+#define EXTI_PRIVCFGR1_PRIV13_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR1_PRIV13        EXTI_PRIVCFGR1_PRIV13_Msk                 /*!< Privilege enable on line 13 */
+#define EXTI_PRIVCFGR1_PRIV14_Pos    (14U)
+#define EXTI_PRIVCFGR1_PRIV14_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR1_PRIV14        EXTI_PRIVCFGR1_PRIV14_Msk                 /*!< Privilege enable on line 14 */
+#define EXTI_PRIVCFGR1_PRIV15_Pos    (15U)
+#define EXTI_PRIVCFGR1_PRIV15_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR1_PRIV15        EXTI_PRIVCFGR1_PRIV15_Msk                 /*!< Privilege enable on line 15 */
+#define EXTI_PRIVCFGR1_PRIV17_Pos    (17U)
+#define EXTI_PRIVCFGR1_PRIV17_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR1_PRIV17        EXTI_PRIVCFGR1_PRIV17_Msk                 /*!< Privilege enable on line 17 */
+#define EXTI_PRIVCFGR1_PRIV18_Pos    (18U)
+#define EXTI_PRIVCFGR1_PRIV18_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR1_PRIV18        EXTI_PRIVCFGR1_PRIV18_Msk                 /*!< Privilege enable on line 18 */
+#define EXTI_PRIVCFGR1_PRIV19_Pos    (19U)
+#define EXTI_PRIVCFGR1_PRIV19_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR1_PRIV19        EXTI_PRIVCFGR1_PRIV19_Msk                 /*!< Privilege enable on line 19 */
+#define EXTI_PRIVCFGR1_PRIV20_Pos    (20U)
+#define EXTI_PRIVCFGR1_PRIV20_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR1_PRIV20        EXTI_PRIVCFGR1_PRIV20_Msk                 /*!< Privilege enable on line 20 */
+#define EXTI_PRIVCFGR1_PRIV21_Pos    (21U)
+#define EXTI_PRIVCFGR1_PRIV21_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR1_PRIV21        EXTI_PRIVCFGR1_PRIV21_Msk                 /*!< Privilege enable on line 21 */
+#define EXTI_PRIVCFGR1_PRIV22_Pos    (22U)
+#define EXTI_PRIVCFGR1_PRIV22_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR1_PRIV22        EXTI_PRIVCFGR1_PRIV22_Msk                 /*!< Privilege enable on line 22 */
+#define EXTI_PRIVCFGR1_PRIV23_Pos    (23U)
+#define EXTI_PRIVCFGR1_PRIV23_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR1_PRIV23        EXTI_PRIVCFGR1_PRIV23_Msk                 /*!< Privilege enable on line 23 */
+#define EXTI_PRIVCFGR1_PRIV24_Pos    (24U)
+#define EXTI_PRIVCFGR1_PRIV24_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR1_PRIV24        EXTI_PRIVCFGR1_PRIV24_Msk                 /*!< Privilege enable on line 24 */
+#define EXTI_PRIVCFGR1_PRIV25_Pos    (25U)
+#define EXTI_PRIVCFGR1_PRIV25_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR1_PRIV25        EXTI_PRIVCFGR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
+#define EXTI_PRIVCFGR1_PRIV26_Pos    (26U)
+#define EXTI_PRIVCFGR1_PRIV26_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR1_PRIV26        EXTI_PRIVCFGR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
+#define EXTI_PRIVCFGR1_PRIV27_Pos    (27U)
+#define EXTI_PRIVCFGR1_PRIV27_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos)      /*!< 0x08000000 */
+#define EXTI_PRIVCFGR1_PRIV27        EXTI_PRIVCFGR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
+#define EXTI_PRIVCFGR1_PRIV28_Pos    (28U)
+#define EXTI_PRIVCFGR1_PRIV28_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR1_PRIV28        EXTI_PRIVCFGR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
+#define EXTI_PRIVCFGR1_PRIV29_Pos    (29U)
+#define EXTI_PRIVCFGR1_PRIV29_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR1_PRIV29        EXTI_PRIVCFGR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
+#define EXTI_PRIVCFGR1_PRIV30_Pos    (30U)
+#define EXTI_PRIVCFGR1_PRIV30_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR1_PRIV30        EXTI_PRIVCFGR1_PRIV30_Msk                 /*!< Privilege enable on line 30 */
+#define EXTI_PRIVCFGR1_PRIV31_Pos    (31U)
+#define EXTI_PRIVCFGR1_PRIV31_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR1_PRIV31        EXTI_PRIVCFGR1_PRIV31_Msk                 /*!< Privilege enable on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR2 register  *****************/
+#define EXTI_RTSR2_RT39_Pos          (7U)
+#define EXTI_RTSR2_RT39_Msk          (0x1UL << EXTI_RTSR2_RT39_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR2_RT39              EXTI_RTSR2_RT39_Msk                       /*!< Rising trigger configuration for input line 39 */
+#define EXTI_RTSR2_RT40_Pos          (8U)
+#define EXTI_RTSR2_RT40_Msk          (0x1UL << EXTI_RTSR2_RT40_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR2_RT40              EXTI_RTSR2_RT40_Msk                       /*!< Rising trigger configuration for input line 40 */
+#define EXTI_RTSR2_RT51_Pos          (19U)
+#define EXTI_RTSR2_RT51_Msk          (0x1UL << EXTI_RTSR2_RT51_Pos)            /*!< 0x00080000 */
+#define EXTI_RTSR2_RT51              EXTI_RTSR2_RT51_Msk                       /*!< Rising trigger configuration for input line 51 */
+#define EXTI_RTSR2_RT54_Pos          (22U)
+#define EXTI_RTSR2_RT54_Msk          (0x1UL << EXTI_RTSR2_RT54_Pos)            /*!< 0x00400000 */
+#define EXTI_RTSR2_RT54              EXTI_RTSR2_RT54_Msk                       /*!< Rising trigger configuration for input line 54 */
+#define EXTI_RTSR2_RT56_Pos          (24U)
+#define EXTI_RTSR2_RT56_Msk          (0x1UL << EXTI_RTSR2_RT56_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR2_RT56              EXTI_RTSR2_RT56_Msk                       /*!< Rising trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_FTSR2 register  *****************/
+#define EXTI_FTSR2_FT39_Pos          (7U)
+#define EXTI_FTSR2_FT39_Msk          (0x1UL << EXTI_FTSR2_FT39_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR2_FT39              EXTI_FTSR2_FT39_Msk                       /*!< Falling trigger configuration for input line 39 */
+#define EXTI_FTSR2_FT40_Pos          (8U)
+#define EXTI_FTSR2_FT40_Msk          (0x1UL << EXTI_FTSR2_FT40_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR2_FT40              EXTI_FTSR2_FT40_Msk                       /*!< Falling trigger configuration for input line 40 */
+#define EXTI_FTSR2_FT51_Pos          (19U)
+#define EXTI_FTSR2_FT51_Msk          (0x1UL << EXTI_FTSR2_FT51_Pos)            /*!< 0x00080000 */
+#define EXTI_FTSR2_FT51              EXTI_FTSR2_FT51_Msk                       /*!< Falling trigger configuration for input line 51 */
+#define EXTI_FTSR2_FT54_Pos          (22U)
+#define EXTI_FTSR2_FT54_Msk          (0x1UL << EXTI_FTSR2_FT54_Pos)            /*!< 0x00400000 */
+#define EXTI_FTSR2_FT54              EXTI_FTSR2_FT54_Msk                       /*!< Falling trigger configuration for input line 54 */
+#define EXTI_FTSR2_FT56_Pos          (24U)
+#define EXTI_FTSR2_FT56_Msk          (0x1UL << EXTI_FTSR2_FT56_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR2_FT56              EXTI_FTSR2_FT56_Msk                       /*!< Falling trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_SWIER2 register  ****************/
+#define EXTI_SWIER2_SWI39_Pos        (7U)
+#define EXTI_SWIER2_SWI39_Msk        (0x1UL << EXTI_SWIER2_SWI39_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER2_SWI39            EXTI_SWIER2_SWI39_Msk                     /*!< Software Interrupt on line 39 */
+#define EXTI_SWIER2_SWI40_Pos        (8U)
+#define EXTI_SWIER2_SWI40_Msk        (0x1UL << EXTI_SWIER2_SWI40_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER2_SWI40            EXTI_SWIER2_SWI40_Msk                     /*!< Software Interrupt on line 40 */
+#define EXTI_SWIER2_SWI51_Pos        (19U)
+#define EXTI_SWIER2_SWI51_Msk        (0x1UL << EXTI_SWIER2_SWI51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWI51            EXTI_SWIER2_SWI51_Msk                     /*!< Software Interrupt on line 51 */
+#define EXTI_SWIER2_SWI54_Pos        (22U)
+#define EXTI_SWIER2_SWI54_Msk        (0x1UL << EXTI_SWIER2_SWI54_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER2_SWI54            EXTI_SWIER2_SWI54_Msk                     /*!< Software Interrupt on line 54 */
+#define EXTI_SWIER2_SWI56_Pos        (24U)
+#define EXTI_SWIER2_SWI56_Msk        (0x1UL << EXTI_SWIER2_SWI56_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER2_SWI56            EXTI_SWIER2_SWI56_Msk                     /*!< Software Interrupt on line 56 */
+
+/*******************  Bit definition for EXTI_RPR2 register  ******************/
+#define EXTI_RPR2_RPIF39_Pos         (7U)
+#define EXTI_RPR2_RPIF39_Msk         (0x1UL << EXTI_RPR2_RPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR2_RPIF39             EXTI_RPR2_RPIF39_Msk                      /*!< Rising Pending Interrupt Flag on line 39 */
+#define EXTI_RPR2_RPIF40_Pos         (8U)
+#define EXTI_RPR2_RPIF40_Msk         (0x1UL << EXTI_RPR2_RPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR2_RPIF40             EXTI_RPR2_RPIF40_Msk                      /*!< Rising Pending Interrupt Flag on line 40 */
+#define EXTI_RPR2_RPIF51_Pos         (19U)
+#define EXTI_RPR2_RPIF51_Msk         (0x1UL << EXTI_RPR2_RPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_RPR2_RPIF51             EXTI_RPR2_RPIF51_Msk                      /*!< Rising Pending Interrupt Flag on line 51 */
+#define EXTI_RPR2_RPIF54_Pos         (22U)
+#define EXTI_RPR2_RPIF54_Msk         (0x1UL << EXTI_RPR2_RPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_RPR2_RPIF54             EXTI_RPR2_RPIF54_Msk                      /*!< Rising Pending Interrupt Flag on line 54 */
+#define EXTI_RPR2_RPIF56_Pos         (24U)
+#define EXTI_RPR2_RPIF56_Msk         (0x1UL << EXTI_RPR2_RPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_RPR2_RPIF56             EXTI_RPR2_RPIF56_Msk                      /*!< Rising Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_FPR2 register  ******************/
+#define EXTI_FPR2_FPIF39_Pos         (7U)
+#define EXTI_FPR2_FPIF39_Msk         (0x1UL << EXTI_FPR2_FPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR2_FPIF39             EXTI_FPR2_FPIF39_Msk                      /*!< Falling Pending Interrupt Flag on line 39 */
+#define EXTI_FPR2_FPIF40_Pos         (8U)
+#define EXTI_FPR2_FPIF40_Msk         (0x1UL << EXTI_FPR2_FPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR2_FPIF40             EXTI_FPR2_FPIF40_Msk                      /*!< Falling Pending Interrupt Flag on line 40 */
+#define EXTI_FPR2_FPIF51_Pos         (19U)
+#define EXTI_FPR2_FPIF51_Msk         (0x1UL << EXTI_FPR2_FPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_FPR2_FPIF51             EXTI_FPR2_FPIF51_Msk                      /*!< Falling Pending Interrupt Flag on line 51 */
+#define EXTI_FPR2_FPIF54_Pos         (22U)
+#define EXTI_FPR2_FPIF54_Msk         (0x1UL << EXTI_FPR2_FPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_FPR2_FPIF54             EXTI_FPR2_FPIF54_Msk                      /*!< Falling Pending Interrupt Flag on line 54 */
+#define EXTI_FPR2_FPIF56_Pos         (24U)
+#define EXTI_FPR2_FPIF56_Msk         (0x1UL << EXTI_FPR2_FPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_FPR2_FPIF56             EXTI_FPR2_FPIF56_Msk                      /*!< Falling Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_SECCFGR2 register  ******************/
+#define EXTI_SECCFGR2_SEC32_Pos      (0U)
+#define EXTI_SECCFGR2_SEC32_Msk      (0x1UL << EXTI_SECCFGR2_SEC32_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR2_SEC32          EXTI_SECCFGR2_SEC32_Msk                   /*!< Security enable on line 32 */
+#define EXTI_SECCFGR2_SEC33_Pos      (1U)
+#define EXTI_SECCFGR2_SEC33_Msk      (0x1UL << EXTI_SECCFGR2_SEC33_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR2_SEC33          EXTI_SECCFGR2_SEC33_Msk                   /*!< Security enable on line 33 */
+#define EXTI_SECCFGR2_SEC34_Pos      (2U)
+#define EXTI_SECCFGR2_SEC34_Msk      (0x1UL << EXTI_SECCFGR2_SEC34_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR2_SEC34          EXTI_SECCFGR2_SEC34_Msk                   /*!< Security enable on line 34 */
+#define EXTI_SECCFGR2_SEC35_Pos      (3U)
+#define EXTI_SECCFGR2_SEC35_Msk      (0x1UL << EXTI_SECCFGR2_SEC35_Pos)        /*!< 0x00000008 */
+#define EXTI_SECCFGR2_SEC35          EXTI_SECCFGR2_SEC35_Msk                   /*!< Security enable on line 35 */
+#define EXTI_SECCFGR2_SEC36_Pos      (4U)
+#define EXTI_SECCFGR2_SEC36_Msk      (0x1UL << EXTI_SECCFGR2_SEC36_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR2_SEC36          EXTI_SECCFGR2_SEC36_Msk                   /*!< Security enable on line 36 */
+#define EXTI_SECCFGR2_SEC37_Pos      (5U)
+#define EXTI_SECCFGR2_SEC37_Msk      (0x1UL << EXTI_SECCFGR2_SEC37_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR2_SEC37          EXTI_SECCFGR2_SEC37_Msk                   /*!< Security enable on line 37 */
+#define EXTI_SECCFGR2_SEC38_Pos      (6U)
+#define EXTI_SECCFGR2_SEC38_Msk      (0x1UL << EXTI_SECCFGR2_SEC38_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR2_SEC38          EXTI_SECCFGR2_SEC38_Msk                   /*!< Security enable on line 38 */
+#define EXTI_SECCFGR2_SEC39_Pos      (7U)
+#define EXTI_SECCFGR2_SEC39_Msk      (0x1UL << EXTI_SECCFGR2_SEC39_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR2_SEC39          EXTI_SECCFGR2_SEC39_Msk                   /*!< Security enable on line 39 */
+#define EXTI_SECCFGR2_SEC40_Pos      (8U)
+#define EXTI_SECCFGR2_SEC40_Msk      (0x1UL << EXTI_SECCFGR2_SEC40_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR2_SEC40          EXTI_SECCFGR2_SEC40_Msk                   /*!< Security enable on line 40 */
+#define EXTI_SECCFGR2_SEC41_Pos      (9U)
+#define EXTI_SECCFGR2_SEC41_Msk      (0x1UL << EXTI_SECCFGR2_SEC41_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR2_SEC41          EXTI_SECCFGR2_SEC41_Msk                   /*!< Security enable on line 41 */
+#define EXTI_SECCFGR2_SEC42_Pos      (10U)
+#define EXTI_SECCFGR2_SEC42_Msk      (0x1UL << EXTI_SECCFGR2_SEC42_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR2_SEC42          EXTI_SECCFGR2_SEC42_Msk                   /*!< Security enable on line 42 */
+#define EXTI_SECCFGR2_SEC43_Pos      (11U)
+#define EXTI_SECCFGR2_SEC43_Msk      (0x1UL << EXTI_SECCFGR2_SEC43_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR2_SEC43          EXTI_SECCFGR2_SEC43_Msk                   /*!< Security enable on line 43 */
+#define EXTI_SECCFGR2_SEC44_Pos      (12U)
+#define EXTI_SECCFGR2_SEC44_Msk      (0x1UL << EXTI_SECCFGR2_SEC44_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR2_SEC44          EXTI_SECCFGR2_SEC44_Msk                   /*!< Security enable on line 44 */
+#define EXTI_SECCFGR2_SEC45_Pos      (13U)
+#define EXTI_SECCFGR2_SEC45_Msk      (0x1UL << EXTI_SECCFGR2_SEC45_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR2_SEC45          EXTI_SECCFGR2_SEC45                       /*!< Security enable on line 45 */
+#define EXTI_SECCFGR2_SEC46_Pos      (14U)
+#define EXTI_SECCFGR2_SEC46_Msk      (0x1UL << EXTI_SECCFGR2_SEC46_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR2_SEC46          EXTI_SECCFGR2_SEC46_Msk                   /*!< Security enable on line 46 */
+#define EXTI_SECCFGR2_SEC47_Pos      (15U)
+#define EXTI_SECCFGR2_SEC47_Msk      (0x1UL << EXTI_SECCFGR2_SEC47_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR2_SEC47          EXTI_SECCFGR2_SEC47_Msk                   /*!< Security enable on line 47 */
+#define EXTI_SECCFGR2_SEC48_Pos      (16U)
+#define EXTI_SECCFGR2_SEC48_Msk      (0x1UL << EXTI_SECCFGR2_SEC48_Pos)        /*!< 0x00010000 */
+#define EXTI_SECCFGR2_SEC48          EXTI_SECCFGR2_SEC48_Msk                   /*!< Security enable on line 48 */
+#define EXTI_SECCFGR2_SEC49_Pos      (17U)
+#define EXTI_SECCFGR2_SEC49_Msk      (0x1UL << EXTI_SECCFGR2_SEC49_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR2_SEC49          EXTI_SECCFGR2_SEC49_Msk                   /*!< Security enable on line 49 */
+#define EXTI_SECCFGR2_SEC50_Pos      (18U)
+#define EXTI_SECCFGR2_SEC50_Msk      (0x1UL << EXTI_SECCFGR2_SEC50_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR2_SEC50          EXTI_SECCFGR2_SEC50_Msk                   /*!< Security enable on line 50 */
+#define EXTI_SECCFGR2_SEC51_Pos      (19U)
+#define EXTI_SECCFGR2_SEC51_Msk      (0x1UL << EXTI_SECCFGR2_SEC51_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR2_SEC51          EXTI_SECCFGR2_SEC51_Msk                   /*!< Security enable on line 51 */
+#define EXTI_SECCFGR2_SEC52_Pos      (20U)
+#define EXTI_SECCFGR2_SEC52_Msk      (0x1UL << EXTI_SECCFGR2_SEC52_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR2_SEC52          EXTI_SECCFGR2_SEC52_Msk                   /*!< Security enable on line 52 */
+#define EXTI_SECCFGR2_SEC53_Pos      (21U)
+#define EXTI_SECCFGR2_SEC53_Msk      (0x1UL << EXTI_SECCFGR2_SEC53_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR2_SEC53          EXTI_SECCFGR2_SEC53_Msk                   /*!< Security enable on line 53 */
+#define EXTI_SECCFGR2_SEC54_Pos      (22U)
+#define EXTI_SECCFGR2_SEC54_Msk      (0x1UL << EXTI_SECCFGR2_SEC54_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR2_SEC54          EXTI_SECCFGR2_SEC54_Msk                   /*!< Security enable on line 54 */
+#define EXTI_SECCFGR2_SEC55_Pos      (23U)
+#define EXTI_SECCFGR2_SEC55_Msk      (0x1UL << EXTI_SECCFGR2_SEC55_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR2_SEC55          EXTI_SECCFGR2_SEC55_Msk                   /*!< Security enable on line 55 */
+#define EXTI_SECCFGR2_SEC56_Pos      (24U)
+#define EXTI_SECCFGR2_SEC56_Msk      (0x1UL << EXTI_SECCFGR2_SEC56_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR2_SEC56          EXTI_SECCFGR2_SEC56_Msk                   /*!< Security enable on line 56 */
+#define EXTI_SECCFGR2_SEC57_Pos      (25U)
+#define EXTI_SECCFGR2_SEC57_Msk      (0x1UL << EXTI_SECCFGR2_SEC57_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR2_SEC57          EXTI_SECCFGR2_SEC57_Msk                   /*!< Security enable on line 57 */
+#define EXTI_SECCFGR2_SEC58_Pos      (26U)
+#define EXTI_SECCFGR2_SEC58_Msk      (0x1UL << EXTI_SECCFGR2_SEC58_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR2_SEC58          EXTI_SECCFGR2_SEC58_Msk                   /*!< Security enable on line 58 */
+#define EXTI_SECCFGR2_SEC60_Pos      (28U)
+#define EXTI_SECCFGR2_SEC60_Msk      (0x1UL << EXTI_SECCFGR2_SEC60_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR2_SEC60          EXTI_SECCFGR2_SEC60_Msk                   /*!< Security enable on line 60 */
+#define EXTI_SECCFGR2_SEC61_Pos      (29U)
+#define EXTI_SECCFGR2_SEC61_Msk      (0x1UL << EXTI_SECCFGR2_SEC61_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR2_SEC61          EXTI_SECCFGR2_SEC61_Msk                   /*!< Security enable on line 61 */
+#define EXTI_SECCFGR2_SEC62_Pos      (30U)
+#define EXTI_SECCFGR2_SEC62_Msk      (0x1UL << EXTI_SECCFGR2_SEC62_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR2_SEC62          EXTI_SECCFGR2_SEC62_Msk                   /*!< Security enable on line 62 */
+#define EXTI_SECCFGR2_SEC63_Pos      (31U)
+#define EXTI_SECCFGR2_SEC63_Msk      (0x1UL << EXTI_SECCFGR2_SEC63_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR2_SEC63          EXTI_SECCFGR2_SEC63_Msk                   /*!< Security enable on line 63 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR2 register  ******************/
+#define EXTI_PRIVCFGR2_PRIV32_Pos    (0U)
+#define EXTI_PRIVCFGR2_PRIV32_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR2_PRIV32        EXTI_PRIVCFGR2_PRIV32_Msk                 /*!< Privilege enable on line 32 */
+#define EXTI_PRIVCFGR2_PRIV33_Pos    (1U)
+#define EXTI_PRIVCFGR2_PRIV33_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR2_PRIV33        EXTI_PRIVCFGR2_PRIV33_Msk                 /*!< Privilege enable on line 33 */
+#define EXTI_PRIVCFGR2_PRIV34_Pos    (2U)
+#define EXTI_PRIVCFGR2_PRIV34_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR2_PRIV34        EXTI_PRIVCFGR2_PRIV34_Msk                 /*!< Privilege enable on line 34 */
+#define EXTI_PRIVCFGR2_PRIV35_Pos    (3U)
+#define EXTI_PRIVCFGR2_PRIV35_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos)      /*!< 0x00000008 */
+#define EXTI_PRIVCFGR2_PRIV35        EXTI_PRIVCFGR2_PRIV35_Msk                 /*!< Privilege enable on line 35 */
+#define EXTI_PRIVCFGR2_PRIV36_Pos    (4U)
+#define EXTI_PRIVCFGR2_PRIV36_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR2_PRIV36        EXTI_PRIVCFGR2_PRIV36_Msk                 /*!< Privilege enable on line 36 */
+#define EXTI_PRIVCFGR2_PRIV37_Pos    (5U)
+#define EXTI_PRIVCFGR2_PRIV37_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR2_PRIV37        EXTI_PRIVCFGR2_PRIV37_Msk                 /*!< Privilege enable on line 37 */
+#define EXTI_PRIVCFGR2_PRIV38_Pos    (6U)
+#define EXTI_PRIVCFGR2_PRIV38_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR2_PRIV38        EXTI_PRIVCFGR2_PRIV38_Msk                 /*!< Privilege enable on line 38 */
+#define EXTI_PRIVCFGR2_PRIV39_Pos    (7U)
+#define EXTI_PRIVCFGR2_PRIV39_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR2_PRIV39        EXTI_PRIVCFGR2_PRIV39_Msk                 /*!< Privilege enable on line 39 */
+#define EXTI_PRIVCFGR2_PRIV40_Pos    (8U)
+#define EXTI_PRIVCFGR2_PRIV40_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV40_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR2_PRIV40        EXTI_PRIVCFGR2_PRIV40_Msk                 /*!< Privilege enable on line 40 */
+#define EXTI_PRIVCFGR2_PRIV41_Pos    (9U)
+#define EXTI_PRIVCFGR2_PRIV41_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV41_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR2_PRIV41        EXTI_PRIVCFGR2_PRIV41_Msk                 /*!< Privilege enable on line 41 */
+#define EXTI_PRIVCFGR2_PRIV42_Pos    (10U)
+#define EXTI_PRIVCFGR2_PRIV42_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV42_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR2_PRIV42        EXTI_PRIVCFGR2_PRIV42_Msk                 /*!< Privilege enable on line 42 */
+#define EXTI_PRIVCFGR2_PRIV43_Pos    (11U)
+#define EXTI_PRIVCFGR2_PRIV43_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV43_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR2_PRIV43        EXTI_PRIVCFGR2_PRIV43_Msk                 /*!< Privilege enable on line 43 */
+#define EXTI_PRIVCFGR2_PRIV44_Pos    (12U)
+#define EXTI_PRIVCFGR2_PRIV44_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV44_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR2_PRIV44        EXTI_PRIVCFGR2_PRIV44_Msk                 /*!< Privilege enable on line 44 */
+#define EXTI_PRIVCFGR2_PRIV45_Pos    (13U)
+#define EXTI_PRIVCFGR2_PRIV45_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV45_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR2_PRIV45        EXTI_PRIVCFGR2_PRIV45                     /*!< Privilege enable on line 45 */
+#define EXTI_PRIVCFGR2_PRIV46_Pos    (14U)
+#define EXTI_PRIVCFGR2_PRIV46_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV46_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR2_PRIV46        EXTI_PRIVCFGR2_PRIV46_Msk                 /*!< Privilege enable on line 46 */
+#define EXTI_PRIVCFGR2_PRIV47_Pos    (15U)
+#define EXTI_PRIVCFGR2_PRIV47_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV47_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR2_PRIV47        EXTI_PRIVCFGR2_PRIV47_Msk                 /*!< Privilege enable on line 47 */
+#define EXTI_PRIVCFGR2_PRIV48_Pos    (16U)
+#define EXTI_PRIVCFGR2_PRIV48_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV48_Pos)      /*!< 0x00010000 */
+#define EXTI_PRIVCFGR2_PRIV48        EXTI_PRIVCFGR2_PRIV48_Msk                 /*!< Privilege enable on line 48 */
+#define EXTI_PRIVCFGR2_PRIV49_Pos    (17U)
+#define EXTI_PRIVCFGR2_PRIV49_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV49_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR2_PRIV49        EXTI_PRIVCFGR2_PRIV49_Msk                 /*!< Privilege enable on line 49 */
+#define EXTI_PRIVCFGR2_PRIV50_Pos    (18U)
+#define EXTI_PRIVCFGR2_PRIV50_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV50_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR2_PRIV50        EXTI_PRIVCFGR2_PRIV50_Msk                 /*!< Privilege enable on line 50 */
+#define EXTI_PRIVCFGR2_PRIV51_Pos    (19U)
+#define EXTI_PRIVCFGR2_PRIV51_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV51_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR2_PRIV51        EXTI_PRIVCFGR2_PRIV51_Msk                 /*!< Privilege enable on line 51 */
+#define EXTI_PRIVCFGR2_PRIV52_Pos    (20U)
+#define EXTI_PRIVCFGR2_PRIV52_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV52_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR2_PRIV52        EXTI_PRIVCFGR2_PRIV52_Msk                 /*!< Privilege enable on line 52 */
+#define EXTI_PRIVCFGR2_PRIV53_Pos    (21U)
+#define EXTI_PRIVCFGR2_PRIV53_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV53_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR2_PRIV53        EXTI_PRIVCFGR2_PRIV53_Msk                 /*!< Privilege enable on line 53 */
+#define EXTI_PRIVCFGR2_PRIV54_Pos    (22U)
+#define EXTI_PRIVCFGR2_PRIV54_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV54_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR2_PRIV54        EXTI_PRIVCFGR2_PRIV54_Msk                 /*!< Privilege enable on line 54 */
+#define EXTI_PRIVCFGR2_PRIV55_Pos    (23U)
+#define EXTI_PRIVCFGR2_PRIV55_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV55_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR2_PRIV55        EXTI_PRIVCFGR2_PRIV55_Msk                 /*!< Privilege enable on line 55 */
+#define EXTI_PRIVCFGR2_PRIV56_Pos    (24U)
+#define EXTI_PRIVCFGR2_PRIV56_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV56_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR2_PRIV56        EXTI_PRIVCFGR2_PRIV56_Msk                 /*!< Privilege enable on line 56 */
+#define EXTI_PRIVCFGR2_PRIV57_Pos    (25U)
+#define EXTI_PRIVCFGR2_PRIV57_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV57_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR2_PRIV57        EXTI_PRIVCFGR2_PRIV57_Msk                 /*!< Privilege enable on line 57 */
+#define EXTI_PRIVCFGR2_PRIV58_Pos    (26U)
+#define EXTI_PRIVCFGR2_PRIV58_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV58_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR2_PRIV58        EXTI_PRIVCFGR2_PRIV58_Msk                 /*!< Privilege enable on line 58 */
+#define EXTI_PRIVCFGR2_PRIV60_Pos    (28U)
+#define EXTI_PRIVCFGR2_PRIV60_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV60_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR2_PRIV60        EXTI_PRIVCFGR2_PRIV60_Msk                 /*!< Privilege enable on line 60 */
+#define EXTI_PRIVCFGR2_PRIV61_Pos    (29U)
+#define EXTI_PRIVCFGR2_PRIV61_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV61_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR2_PRIV61        EXTI_PRIVCFGR2_PRIV61_Msk                 /*!< Privilege enable on line 61 */
+#define EXTI_PRIVCFGR2_PRIV62_Pos    (30U)
+#define EXTI_PRIVCFGR2_PRIV62_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV62_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR2_PRIV62        EXTI_PRIVCFGR2_PRIV62_Msk                 /*!< Privilege enable on line 62 */
+#define EXTI_PRIVCFGR2_PRIV63_Pos    (31U)
+#define EXTI_PRIVCFGR2_PRIV63_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV63_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR2_PRIV63        EXTI_PRIVCFGR2_PRIV63_Msk                 /*!< Privilege enable on line 63 */
+
+/*******************  Bit definition for EXTI_RTSR3 register  *****************/
+#define EXTI_RTSR3_RT66_Pos          (2U)
+#define EXTI_RTSR3_RT66_Msk          (0x1UL << EXTI_RTSR3_RT66_Pos)            /*!< 0x00000004 */
+#define EXTI_RTSR3_RT66              EXTI_RTSR3_RT66_Msk                       /*!< Rising trigger configuration for input line 66 */
+#define EXTI_RTSR3_RT68_Pos          (4U)
+#define EXTI_RTSR3_RT68_Msk          (0x1UL << EXTI_RTSR3_RT68_Pos)            /*!< 0x00000010 */
+#define EXTI_RTSR3_RT68              EXTI_RTSR3_RT68_Msk                       /*!< Rising trigger configuration for input line 68 */
+#define EXTI_RTSR3_RT69_Pos          (5U)
+#define EXTI_RTSR3_RT69_Msk          (0x1UL << EXTI_RTSR3_RT69_Pos)            /*!< 0x00000020 */
+#define EXTI_RTSR3_RT69              EXTI_RTSR3_RT69_Msk                       /*!< Rising trigger configuration for input line 69 */
+#define EXTI_RTSR3_RT70_Pos          (6U)
+#define EXTI_RTSR3_RT70_Msk          (0x1UL << EXTI_RTSR3_RT70_Pos)            /*!< 0x00000040 */
+#define EXTI_RTSR3_RT70              EXTI_RTSR3_RT70_Msk                       /*!< Rising trigger configuration for input line 70 */
+#define EXTI_RTSR3_RT71_Pos          (7U)
+#define EXTI_RTSR3_RT71_Msk          (0x1UL << EXTI_RTSR3_RT71_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR3_RT71              EXTI_RTSR3_RT71_Msk                       /*!< Rising trigger configuration for input line 71 */
+#define EXTI_RTSR3_RT72_Pos          (8U)
+#define EXTI_RTSR3_RT72_Msk          (0x1UL << EXTI_RTSR3_RT72_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR3_RT72              EXTI_RTSR3_RT72_Msk                       /*!< Rising trigger configuration for input line 72 */
+#define EXTI_RTSR3_RT73_Pos          (9U)
+#define EXTI_RTSR3_RT73_Msk          (0x1UL << EXTI_RTSR3_RT73_Pos)            /*!< 0x00000200 */
+#define EXTI_RTSR3_RT73              EXTI_RTSR3_RT73_Msk                       /*!< Rising trigger configuration for input line 73 */
+#define EXTI_RTSR3_RT74_Pos          (10U)
+#define EXTI_RTSR3_RT74_Msk          (0x1UL << EXTI_RTSR3_RT74_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR3_RT74              EXTI_RTSR3_RT74_Msk                       /*!< Rising trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_FTSR3 register  *****************/
+#define EXTI_FTSR3_FT66_Pos          (2U)
+#define EXTI_FTSR3_FT66_Msk          (0x1UL << EXTI_FTSR3_FT66_Pos)            /*!< 0x00000004 */
+#define EXTI_FTSR3_FT66              EXTI_FTSR3_FT66_Msk                       /*!< Falling trigger configuration for input line 66 */
+#define EXTI_FTSR3_FT68_Pos          (4U)
+#define EXTI_FTSR3_FT68_Msk          (0x1UL << EXTI_FTSR3_FT68_Pos)            /*!< 0x00000010 */
+#define EXTI_FTSR3_FT68              EXTI_FTSR3_FT68_Msk                       /*!< Falling trigger configuration for input line 68 */
+#define EXTI_FTSR3_FT69_Pos          (5U)
+#define EXTI_FTSR3_FT69_Msk          (0x1UL << EXTI_FTSR3_FT69_Pos)            /*!< 0x00000020 */
+#define EXTI_FTSR3_FT69              EXTI_FTSR3_FT69_Msk                       /*!< Falling trigger configuration for input line 69 */
+#define EXTI_FTSR3_FT70_Pos          (6U)
+#define EXTI_FTSR3_FT70_Msk          (0x1UL << EXTI_FTSR3_FT70_Pos)            /*!< 0x00000040 */
+#define EXTI_FTSR3_FT70              EXTI_FTSR3_FT70_Msk                       /*!< Falling trigger configuration for input line 70 */
+#define EXTI_FTSR3_FT71_Pos          (7U)
+#define EXTI_FTSR3_FT71_Msk          (0x1UL << EXTI_FTSR3_FT71_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR3_FT71              EXTI_FTSR3_FT71_Msk                       /*!< Falling trigger configuration for input line 71 */
+#define EXTI_FTSR3_FT72_Pos          (8U)
+#define EXTI_FTSR3_FT72_Msk          (0x1UL << EXTI_FTSR3_FT72_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR3_FT72              EXTI_FTSR3_FT72_Msk                       /*!< Falling trigger configuration for input line 72 */
+#define EXTI_FTSR3_FT73_Pos          (9U)
+#define EXTI_FTSR3_FT73_Msk          (0x1UL << EXTI_FTSR3_FT73_Pos)            /*!< 0x00000200 */
+#define EXTI_FTSR3_FT73              EXTI_FTSR3_FT73_Msk                       /*!< Falling trigger configuration for input line 73 */
+#define EXTI_FTSR3_FT74_Pos          (10U)
+#define EXTI_FTSR3_FT74_Msk          (0x1UL << EXTI_FTSR3_FT74_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR3_FT74              EXTI_FTSR3_FT74_Msk                       /*!< Falling trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_SWIER3 register  ****************/
+#define EXTI_SWIER3_SWI66_Pos        (2U)
+#define EXTI_SWIER3_SWI66_Msk        (0x1UL << EXTI_SWIER3_SWI66_Pos)          /*!< 0x00000004 */
+#define EXTI_SWIER3_SWI66            EXTI_SWIER3_SWI66_Msk                     /*!< Software Interrupt on line 66 */
+#define EXTI_SWIER3_SWI68_Pos        (4U)
+#define EXTI_SWIER3_SWI68_Msk        (0x1UL << EXTI_SWIER3_SWI68_Pos)          /*!< 0x00000010 */
+#define EXTI_SWIER3_SWI68            EXTI_SWIER3_SWI68_Msk                     /*!< Software Interrupt on line 68 */
+#define EXTI_SWIER3_SWI69_Pos        (5U)
+#define EXTI_SWIER3_SWI69_Msk        (0x1UL << EXTI_SWIER3_SWI69_Pos)          /*!< 0x00000020 */
+#define EXTI_SWIER3_SWI69            EXTI_SWIER3_SWI69_Msk                     /*!< Software Interrupt on line 69 */
+#define EXTI_SWIER3_SWI70_Pos        (6U)
+#define EXTI_SWIER3_SWI70_Msk        (0x1UL << EXTI_SWIER3_SWI70_Pos)          /*!< 0x00000040 */
+#define EXTI_SWIER3_SWI70            EXTI_SWIER3_SWI70_Msk                     /*!< Software Interrupt on line 70 */
+#define EXTI_SWIER3_SWI71_Pos        (7U)
+#define EXTI_SWIER3_SWI71_Msk        (0x1UL << EXTI_SWIER3_SWI71_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER3_SWI71            EXTI_SWIER3_SWI71_Msk                     /*!< Software Interrupt on line 71 */
+#define EXTI_SWIER3_SWI72_Pos        (8U)
+#define EXTI_SWIER3_SWI72_Msk        (0x1UL << EXTI_SWIER3_SWI72_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER3_SWI72            EXTI_SWIER3_SWI72_Msk                     /*!< Software Interrupt on line 72 */
+#define EXTI_SWIER3_SWI73_Pos        (9U)
+#define EXTI_SWIER3_SWI73_Msk        (0x1UL << EXTI_SWIER3_SWI73_Pos)          /*!< 0x00000200 */
+#define EXTI_SWIER3_SWI73            EXTI_SWIER3_SWI73_Msk                     /*!< Software Interrupt on line 73 */
+#define EXTI_SWIER3_SWI74_Pos        (10U)
+#define EXTI_SWIER3_SWI74_Msk        (0x1UL << EXTI_SWIER3_SWI74_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER3_SWI74            EXTI_SWIER3_SWI74_Msk                     /*!< Software Interrupt on line 74 */
+
+/*******************  Bit definition for EXTI_RPR3 register  ******************/
+#define EXTI_RPR3_RPIF66_Pos         (2U)
+#define EXTI_RPR3_RPIF66_Msk         (0x1UL << EXTI_RPR3_RPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_RPR3_RPIF66             EXTI_RPR3_RPIF66_Msk                      /*!< Rising Pending Interrupt Flag on line 66 */
+#define EXTI_RPR3_RPIF68_Pos         (4U)
+#define EXTI_RPR3_RPIF68_Msk         (0x1UL << EXTI_RPR3_RPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_RPR3_RPIF68             EXTI_RPR3_RPIF68_Msk                      /*!< Rising Pending Interrupt Flag on line 68 */
+#define EXTI_RPR3_RPIF69_Pos         (5U)
+#define EXTI_RPR3_RPIF69_Msk         (0x1UL << EXTI_RPR3_RPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_RPR3_RPIF69             EXTI_RPR3_RPIF69_Msk                      /*!< Rising Pending Interrupt Flag on line 69 */
+#define EXTI_RPR3_RPIF70_Pos         (6U)
+#define EXTI_RPR3_RPIF70_Msk         (0x1UL << EXTI_RPR3_RPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_RPR3_RPIF70             EXTI_RPR3_RPIF70_Msk                      /*!< Rising Pending Interrupt Flag on line 70 */
+#define EXTI_RPR3_RPIF71_Pos         (7U)
+#define EXTI_RPR3_RPIF71_Msk         (0x1UL << EXTI_RPR3_RPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR3_RPIF71             EXTI_RPR3_RPIF71_Msk                      /*!< Rising Pending Interrupt Flag on line 71 */
+#define EXTI_RPR3_RPIF72_Pos         (8U)
+#define EXTI_RPR3_RPIF72_Msk         (0x1UL << EXTI_RPR3_RPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR3_RPIF72             EXTI_RPR3_RPIF72_Msk                      /*!< Rising Pending Interrupt Flag on line 72 */
+#define EXTI_RPR3_RPIF73_Pos         (9U)
+#define EXTI_RPR3_RPIF73_Msk         (0x1UL << EXTI_RPR3_RPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_RPR3_RPIF73             EXTI_RPR3_RPIF73_Msk                      /*!< Rising Pending Interrupt Flag on line 73 */
+#define EXTI_RPR3_RPIF74_Pos         (10U)
+#define EXTI_RPR3_RPIF74_Msk         (0x1UL << EXTI_RPR3_RPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR3_RPIF74             EXTI_RPR3_RPIF74_Msk                      /*!< Rising Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_FPR3 register  ******************/
+#define EXTI_FPR3_FPIF66_Pos         (2U)
+#define EXTI_FPR3_FPIF66_Msk         (0x1UL << EXTI_FPR3_FPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_FPR3_FPIF66             EXTI_FPR3_FPIF66_Msk                      /*!< Falling Pending Interrupt Flag on line 66 */
+#define EXTI_FPR3_FPIF68_Pos         (4U)
+#define EXTI_FPR3_FPIF68_Msk         (0x1UL << EXTI_FPR3_FPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_FPR3_FPIF68             EXTI_FPR3_FPIF68_Msk                      /*!< Falling Pending Interrupt Flag on line 68 */
+#define EXTI_FPR3_FPIF69_Pos         (5U)
+#define EXTI_FPR3_FPIF69_Msk         (0x1UL << EXTI_FPR3_FPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_FPR3_FPIF69             EXTI_FPR3_FPIF69_Msk                      /*!< Falling Pending Interrupt Flag online  69 */
+#define EXTI_FPR3_FPIF70_Pos         (6U)
+#define EXTI_FPR3_FPIF70_Msk         (0x1UL << EXTI_FPR3_FPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_FPR3_FPIF70             EXTI_FPR3_FPIF70_Msk                      /*!< Falling Pending Interrupt Flag on line 70 */
+#define EXTI_FPR3_FPIF71_Pos         (7U)
+#define EXTI_FPR3_FPIF71_Msk         (0x1UL << EXTI_FPR3_FPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR3_FPIF71             EXTI_FPR3_FPIF71_Msk                      /*!< Falling Pending Interrupt Flag on line 71 */
+#define EXTI_FPR3_FPIF72_Pos         (8U)
+#define EXTI_FPR3_FPIF72_Msk         (0x1UL << EXTI_FPR3_FPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR3_FPIF72             EXTI_FPR3_FPIF72_Msk                      /*!< Falling Pending Interrupt Flag on line 72 */
+#define EXTI_FPR3_FPIF73_Pos         (9U)
+#define EXTI_FPR3_FPIF73_Msk         (0x1UL << EXTI_FPR3_FPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_FPR3_FPIF73             EXTI_FPR3_FPIF73_Msk                      /*!< Falling Pending Interrupt Flag on line 73 */
+#define EXTI_FPR3_FPIF74_Pos         (10U)
+#define EXTI_FPR3_FPIF74_Msk         (0x1UL << EXTI_FPR3_FPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR3_FPIF74             EXTI_FPR3_FPIF74_Msk                      /*!< Falling Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_SECCFGR3 register  ******************/
+#define EXTI_SECCFGR3_SEC64_Pos      (0U)
+#define EXTI_SECCFGR3_SEC64_Msk      (0x1UL << EXTI_SECCFGR3_SEC64_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR3_SEC64          EXTI_SECCFGR3_SEC64_Msk                   /*!< Security enable on line 64 */
+#define EXTI_SECCFGR3_SEC65_Pos      (1U)
+#define EXTI_SECCFGR3_SEC65_Msk      (0x1UL << EXTI_SECCFGR3_SEC65_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR3_SEC65          EXTI_SECCFGR3_SEC65_Msk                   /*!< Security enable on line 65 */
+#define EXTI_SECCFGR3_SEC66_Pos      (2U)
+#define EXTI_SECCFGR3_SEC66_Msk      (0x1UL << EXTI_SECCFGR3_SEC66_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR3_SEC66          EXTI_SECCFGR3_SEC66_Msk                   /*!< Security enable on line 66  */
+#define EXTI_SECCFGR3_SEC68_Pos      (4U)
+#define EXTI_SECCFGR3_SEC68_Msk      (0x1UL << EXTI_SECCFGR3_SEC68_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR3_SEC68          EXTI_SECCFGR3_SEC68_Msk                   /*!< Security enable on line 68 */
+#define EXTI_SECCFGR3_SEC69_Pos      (5U)
+#define EXTI_SECCFGR3_SEC69_Msk      (0x1UL << EXTI_SECCFGR3_SEC69_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR3_SEC69          EXTI_SECCFGR3_SEC69_Msk                   /*!< Security enable on line 69 */
+#define EXTI_SECCFGR3_SEC70_Pos      (6U)
+#define EXTI_SECCFGR3_SEC70_Msk      (0x1UL << EXTI_SECCFGR3_SEC70_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR3_SEC70          EXTI_SECCFGR3_SEC70_Msk                   /*!< Security enable on line 70 */
+#define EXTI_SECCFGR3_SEC71_Pos      (7U)
+#define EXTI_SECCFGR3_SEC71_Msk      (0x1UL << EXTI_SECCFGR3_SEC71_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR3_SEC71          EXTI_SECCFGR3_SEC71_Msk                   /*!< Security enable on line 71 */
+#define EXTI_SECCFGR3_SEC72_Pos      (8U)
+#define EXTI_SECCFGR3_SEC72_Msk      (0x1UL << EXTI_SECCFGR3_SEC72_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR3_SEC72          EXTI_SECCFGR3_SEC72_Msk                   /*!< Security enable on line 72 */
+#define EXTI_SECCFGR3_SEC73_Pos      (9U)
+#define EXTI_SECCFGR3_SEC73_Msk      (0x1UL << EXTI_SECCFGR3_SEC73_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR3_SEC73          EXTI_SECCFGR3_SEC73_Msk                   /*!< Security enable on line 73 */
+#define EXTI_SECCFGR3_SEC74_Pos      (10U)
+#define EXTI_SECCFGR3_SEC74_Msk      (0x1UL << EXTI_SECCFGR3_SEC74_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR3_SEC74          EXTI_SECCFGR3_SEC74_Msk                   /*!< Security enable on line 74 */
+#define EXTI_SECCFGR3_SEC77_Pos      (13U)
+#define EXTI_SECCFGR3_SEC77_Msk      (0x1UL << EXTI_SECCFGR3_SEC77_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR3_SEC77          EXTI_SECCFGR3_SEC77_Msk                   /*!< Security enable on line 77 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR3 register  ******************/
+#define EXTI_PRIVCFGR3_PRIV64_Pos    (0U)
+#define EXTI_PRIVCFGR3_PRIV64_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV64_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR3_PRIV64        EXTI_PRIVCFGR3_PRIV64_Msk                 /*!< Privilege enable on line 64 */
+#define EXTI_PRIVCFGR3_PRIV65_Pos    (1U)
+#define EXTI_PRIVCFGR3_PRIV65_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV65_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR3_PRIV65        EXTI_PRIVCFGR3_PRIV65_Msk                 /*!< Privilege enable on line 65 */
+#define EXTI_PRIVCFGR3_PRIV66_Pos    (2U)
+#define EXTI_PRIVCFGR3_PRIV66_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV66_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR3_PRIV66        EXTI_PRIVCFGR3_PRIV66_Msk                 /*!< Privilege enable on line 66  */
+#define EXTI_PRIVCFGR3_PRIV68_Pos    (4U)
+#define EXTI_PRIVCFGR3_PRIV68_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV68_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR3_PRIV68        EXTI_PRIVCFGR3_PRIV68_Msk                 /*!< Privilege enable on line 68 */
+#define EXTI_PRIVCFGR3_PRIV69_Pos    (5U)
+#define EXTI_PRIVCFGR3_PRIV69_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV69_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR3_PRIV69        EXTI_PRIVCFGR3_PRIV69_Msk                 /*!< Privilege enable on line 69 */
+#define EXTI_PRIVCFGR3_PRIV70_Pos    (6U)
+#define EXTI_PRIVCFGR3_PRIV70_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV70_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR3_PRIV70        EXTI_PRIVCFGR3_PRIV70_Msk                 /*!< Privilege enable on line 70 */
+#define EXTI_PRIVCFGR3_PRIV71_Pos    (7U)
+#define EXTI_PRIVCFGR3_PRIV71_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV71_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR3_PRIV71        EXTI_PRIVCFGR3_PRIV71_Msk                 /*!< Privilege enable on line 71 */
+#define EXTI_PRIVCFGR3_PRIV72_Pos    (8U)
+#define EXTI_PRIVCFGR3_PRIV72_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV72_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR3_PRIV72        EXTI_PRIVCFGR3_PRIV72_Msk                 /*!< Privilege enable on line 72 */
+#define EXTI_PRIVCFGR3_PRIV73_Pos    (9U)
+#define EXTI_PRIVCFGR3_PRIV73_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV73_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR3_PRIV73        EXTI_PRIVCFGR3_PRIV73_Msk                 /*!< Privilege enable on line 73 */
+#define EXTI_PRIVCFGR3_PRIV74_Pos    (10U)
+#define EXTI_PRIVCFGR3_PRIV74_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV74_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR3_PRIV74        EXTI_PRIVCFGR3_PRIV74_Msk                 /*!< Privilege enable on line 74 */
+#define EXTI_PRIVCFGR3_PRIV77_Pos    (13U)
+#define EXTI_PRIVCFGR3_PRIV77_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV77_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR3_PRIV77        EXTI_PRIVCFGR3_PRIV77_Msk                 /*!< Privilege enable on line 77 */
+
+/*****************  Bit definition for EXTI_EXTICR1 register  **************/
+#define EXTI_EXTICR1_EXTI0_Pos       (0U)
+#define EXTI_EXTICR1_EXTI0_Msk       (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
+#define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR1_EXTI0_3         (0x8UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR1_EXTI0_4         (0x10UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR1_EXTI0_5         (0x20UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR1_EXTI0_6         (0x40UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR1_EXTI0_7         (0x80UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR1_EXTI1_Pos       (8U)
+#define EXTI_EXTICR1_EXTI1_Msk       (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
+#define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR1_EXTI1_3         (0x8UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR1_EXTI1_4         (0x10UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR1_EXTI1_5         (0x20UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR1_EXTI1_6         (0x40UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR1_EXTI1_7         (0x80UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR1_EXTI2_Pos       (16U)
+#define EXTI_EXTICR1_EXTI2_Msk       (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
+#define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR1_EXTI2_3         (0x8UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR1_EXTI2_4         (0x10UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR1_EXTI2_5         (0x20UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR1_EXTI2_6         (0x40UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR1_EXTI2_7         (0x80UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR1_EXTI3_Pos       (24U)
+#define EXTI_EXTICR1_EXTI3_Msk       (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
+#define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR1_EXTI3_3         (0x8UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR1_EXTI3_4         (0x10UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR1_EXTI3_5         (0x20UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR1_EXTI3_6         (0x40UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR1_EXTI3_7         (0x80UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR2 register  **************/
+#define EXTI_EXTICR2_EXTI4_Pos       (0U)
+#define EXTI_EXTICR2_EXTI4_Msk       (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
+#define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR2_EXTI4_3         (0x8UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR2_EXTI4_4         (0x10UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR2_EXTI4_5         (0x20UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR2_EXTI4_6         (0x40UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR2_EXTI4_7         (0x80UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR2_EXTI5_Pos       (8U)
+#define EXTI_EXTICR2_EXTI5_Msk       (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
+#define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR2_EXTI5_3         (0x8UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR2_EXTI5_4         (0x10UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR2_EXTI5_5         (0x20UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR2_EXTI5_6         (0x40UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR2_EXTI5_7         (0x80UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR2_EXTI6_Pos       (16U)
+#define EXTI_EXTICR2_EXTI6_Msk       (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
+#define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR2_EXTI6_3         (0x8UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR2_EXTI6_4         (0x10UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR2_EXTI6_5         (0x20UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR2_EXTI6_6         (0x40UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR2_EXTI6_7         (0x80UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR2_EXTI7_Pos       (24U)
+#define EXTI_EXTICR2_EXTI7_Msk       (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
+#define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR2_EXTI7_3         (0x8UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR2_EXTI7_4         (0x10UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR2_EXTI7_5         (0x20UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR2_EXTI7_6         (0x40UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR2_EXTI7_7         (0x80UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR3 register  **************/
+#define EXTI_EXTICR3_EXTI8_Pos       (0U)
+#define EXTI_EXTICR3_EXTI8_Msk       (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
+#define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR3_EXTI8_3         (0x8UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR3_EXTI8_4         (0x10UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR3_EXTI8_5         (0x20UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR3_EXTI8_6         (0x40UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR3_EXTI8_7         (0x80UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR3_EXTI9_Pos       (8U)
+#define EXTI_EXTICR3_EXTI9_Msk       (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
+#define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR3_EXTI9_3         (0x8UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR3_EXTI9_4         (0x10UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR3_EXTI9_5         (0x20UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR3_EXTI9_6         (0x40UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR3_EXTI9_7         (0x80UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR3_EXTI10_Pos      (16U)
+#define EXTI_EXTICR3_EXTI10_Msk      (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
+#define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR3_EXTI10_3        (0x8UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR3_EXTI10_4        (0x10UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR3_EXTI10_5        (0x20UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR3_EXTI10_6        (0x40UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR3_EXTI10_7        (0x80UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR3_EXTI11_Pos      (24U)
+#define EXTI_EXTICR3_EXTI11_Msk      (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
+#define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR3_EXTI11_3        (0x8UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR3_EXTI11_4        (0x10UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR3_EXTI11_5        (0x20UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR3_EXTI11_6        (0x40UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR3_EXTI11_7        (0x80UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR4 register  **************/
+#define EXTI_EXTICR4_EXTI12_Pos      (0U)
+#define EXTI_EXTICR4_EXTI12_Msk      (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x000000FF */
+#define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
+#define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
+#define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
+#define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
+#define EXTI_EXTICR4_EXTI12_3        (0x8UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000008 */
+#define EXTI_EXTICR4_EXTI12_4        (0x10UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000010 */
+#define EXTI_EXTICR4_EXTI12_5        (0x20UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000020 */
+#define EXTI_EXTICR4_EXTI12_6        (0x40UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000040 */
+#define EXTI_EXTICR4_EXTI12_7        (0x80UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000080 */
+#define EXTI_EXTICR4_EXTI13_Pos      (8U)
+#define EXTI_EXTICR4_EXTI13_Msk      (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x0000FF00 */
+#define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
+#define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
+#define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000200 */
+#define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000400 */
+#define EXTI_EXTICR4_EXTI13_3        (0x8UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000800 */
+#define EXTI_EXTICR4_EXTI13_4        (0x10UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00001000 */
+#define EXTI_EXTICR4_EXTI13_5        (0x20UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00002000 */
+#define EXTI_EXTICR4_EXTI13_6        (0x40UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00004000 */
+#define EXTI_EXTICR4_EXTI13_7        (0x80UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00008000 */
+#define EXTI_EXTICR4_EXTI14_Pos      (16U)
+#define EXTI_EXTICR4_EXTI14_Msk      (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
+#define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR4_EXTI14_3        (0x8UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR4_EXTI14_4        (0x10UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR4_EXTI14_5        (0x20UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR4_EXTI14_6        (0x40UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR4_EXTI14_7        (0x80UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR4_EXTI15_Pos      (24U)
+#define EXTI_EXTICR4_EXTI15_Msk      (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
+#define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR4_EXTI15_3        (0x8UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR4_EXTI15_4        (0x10UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR4_EXTI15_5        (0x20UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR4_EXTI15_6        (0x40UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR4_EXTI15_7        (0x80UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x80000000 */
+
+/*******************  Bit definition I_LOCKR register  ******************/
+#define EXTI_LOCKR_LOCK_Pos          (0U)
+#define EXTI_LOCKR_LOCK_Msk          (0x1UL << EXTI_LOCKR_LOCK_Pos)            /*!< 0x00000001 */
+#define EXTI_LOCKR_LOCK              EXTI_LOCKR_LOCK_Msk                       /*!< Security and privilege configuration lock */
+
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos            (0U)
+#define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
+#define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos            (1U)
+#define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
+#define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos            (2U)
+#define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
+#define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos            (3U)
+#define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
+#define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos            (4U)
+#define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
+#define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos            (5U)
+#define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
+#define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos            (6U)
+#define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
+#define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos            (7U)
+#define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
+#define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos            (8U)
+#define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
+#define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos            (9U)
+#define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
+#define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos           (10U)
+#define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos           (11U)
+#define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos           (12U)
+#define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos           (13U)
+#define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos           (14U)
+#define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos           (15U)
+#define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM17_Pos           (17U)
+#define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos           (18U)
+#define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos           (19U)
+#define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos           (20U)
+#define EXTI_IMR1_IM20_Msk           (0x1UL << EXTI_IMR1_IM20_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR1_IM20               EXTI_IMR1_IM20_Msk                        /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos           (21U)
+#define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos           (22U)
+#define EXTI_IMR1_IM22_Msk           (0x1UL << EXTI_IMR1_IM22_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR1_IM22               EXTI_IMR1_IM22_Msk                        /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos           (23U)
+#define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos           (24U)
+#define EXTI_IMR1_IM24_Msk           (0x1UL << EXTI_IMR1_IM24_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR1_IM24               EXTI_IMR1_IM24_Msk                        /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos           (25U)
+#define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos           (26U)
+#define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos           (27U)
+#define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */
+#define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos           (28U)
+#define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos           (29U)
+#define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos           (30U)
+#define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos           (31U)
+#define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos             (0U)
+#define EXTI_IMR1_IM_Msk             (0xFFFEFFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos            (0U)
+#define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
+#define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos            (1U)
+#define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
+#define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos            (2U)
+#define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
+#define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos            (3U)
+#define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
+#define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos            (4U)
+#define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
+#define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos            (5U)
+#define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
+#define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos            (6U)
+#define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
+#define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos            (7U)
+#define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
+#define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos            (8U)
+#define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
+#define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos            (9U)
+#define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
+#define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos           (10U)
+#define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos           (11U)
+#define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos           (12U)
+#define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos           (13U)
+#define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos           (14U)
+#define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos           (15U)
+#define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM17_Pos           (17U)
+#define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos           (18U)
+#define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos           (19U)
+#define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos           (20U)
+#define EXTI_EMR1_EM20_Msk           (0x1UL << EXTI_EMR1_EM20_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR1_EM20               EXTI_EMR1_EM20_Msk                        /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos           (21U)
+#define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos           (22U)
+#define EXTI_EMR1_EM22_Msk           (0x1UL << EXTI_EMR1_EM22_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR1_EM22               EXTI_EMR1_EM22_Msk                        /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos           (23U)
+#define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos           (24U)
+#define EXTI_EMR1_EM24_Msk           (0x1UL << EXTI_EMR1_EM24_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR1_EM24               EXTI_EMR1_EM24_Msk                        /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos           (25U)
+#define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos           (26U)
+#define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos           (27U)
+#define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */
+#define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos           (28U)
+#define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos           (29U)
+#define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos           (30U)
+#define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos           (31U)
+#define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */
+#define EXTI_EMR1_EM_Pos             (0U)
+#define EXTI_EMR1_EM_Msk             (0xFFFEFFFFUL << EXTI_EMR1_EM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_EMR1_EM                 EXTI_EMR1_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos           (0U)
+#define EXTI_IMR2_IM32_Msk           (0x1UL << EXTI_IMR2_IM32_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR2_IM32               EXTI_IMR2_IM32_Msk                        /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos           (1U)
+#define EXTI_IMR2_IM33_Msk           (0x1UL << EXTI_IMR2_IM33_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR2_IM33               EXTI_IMR2_IM33_Msk                        /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos           (2U)
+#define EXTI_IMR2_IM34_Msk           (0x1UL << EXTI_IMR2_IM34_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR2_IM34               EXTI_IMR2_IM34_Msk                        /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos           (3U)
+#define EXTI_IMR2_IM35_Msk           (0x1UL << EXTI_IMR2_IM35_Pos)             /*!< 0x00000008 */
+#define EXTI_IMR2_IM35               EXTI_IMR2_IM35_Msk                        /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos           (4U)
+#define EXTI_IMR2_IM36_Msk           (0x1UL << EXTI_IMR2_IM36_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR2_IM36               EXTI_IMR2_IM36_Msk                        /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos           (5U)
+#define EXTI_IMR2_IM37_Msk           (0x1UL << EXTI_IMR2_IM37_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR2_IM37               EXTI_IMR2_IM37_Msk                        /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos           (6U)
+#define EXTI_IMR2_IM38_Msk           (0x1UL << EXTI_IMR2_IM38_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR2_IM38               EXTI_IMR2_IM38_Msk                        /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos           (7U)
+#define EXTI_IMR2_IM39_Msk           (0x1UL << EXTI_IMR2_IM39_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR2_IM39               EXTI_IMR2_IM39_Msk                        /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos           (8U)
+#define EXTI_IMR2_IM40_Msk           (0x1UL << EXTI_IMR2_IM40_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR2_IM40               EXTI_IMR2_IM40_Msk                        /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos           (9U)
+#define EXTI_IMR2_IM41_Msk           (0x1UL << EXTI_IMR2_IM41_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR2_IM41               EXTI_IMR2_IM41_Msk                        /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos           (10U)
+#define EXTI_IMR2_IM42_Msk           (0x1UL << EXTI_IMR2_IM42_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR2_IM42               EXTI_IMR2_IM42_Msk                        /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos           (11U)
+#define EXTI_IMR2_IM43_Msk           (0x1UL << EXTI_IMR2_IM43_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR2_IM43               EXTI_IMR2_IM43_Msk                        /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos           (12U)
+#define EXTI_IMR2_IM44_Msk           (0x1UL << EXTI_IMR2_IM44_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR2_IM44               EXTI_IMR2_IM44_Msk                        /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM45_Pos           (13U)
+#define EXTI_IMR2_IM45_Msk           (0x1UL << EXTI_IMR2_IM45_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR2_IM45               EXTI_IMR2_IM45_Msk                        /*!< Interrupt Mask on line 45 */
+#define EXTI_IMR2_IM46_Pos           (14U)
+#define EXTI_IMR2_IM46_Msk           (0x1UL << EXTI_IMR2_IM46_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR2_IM46               EXTI_IMR2_IM46_Msk                        /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos           (15U)
+#define EXTI_IMR2_IM47_Msk           (0x1UL << EXTI_IMR2_IM47_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR2_IM47               EXTI_IMR2_IM47_Msk                        /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos           (16U)
+#define EXTI_IMR2_IM48_Msk           (0x1UL << EXTI_IMR2_IM48_Pos)             /*!< 0x00010000 */
+#define EXTI_IMR2_IM48               EXTI_IMR2_IM48_Msk                        /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos           (17U)
+#define EXTI_IMR2_IM49_Msk           (0x1UL << EXTI_IMR2_IM49_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR2_IM49               EXTI_IMR2_IM49_Msk                        /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos           (18U)
+#define EXTI_IMR2_IM50_Msk           (0x1UL << EXTI_IMR2_IM50_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR2_IM50               EXTI_IMR2_IM50_Msk                        /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos           (19U)
+#define EXTI_IMR2_IM51_Msk           (0x1UL << EXTI_IMR2_IM51_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR2_IM51               EXTI_IMR2_IM51_Msk                        /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos           (20U)
+#define EXTI_IMR2_IM52_Msk           (0x1UL << EXTI_IMR2_IM52_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR2_IM52               EXTI_IMR2_IM52_Msk                        /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos           (21U)
+#define EXTI_IMR2_IM53_Msk           (0x1UL << EXTI_IMR2_IM53_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR2_IM53               EXTI_IMR2_IM53_Msk                        /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos           (22U)
+#define EXTI_IMR2_IM54_Msk           (0x1UL << EXTI_IMR2_IM54_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR2_IM54               EXTI_IMR2_IM54_Msk                        /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos           (23U)
+#define EXTI_IMR2_IM55_Msk           (0x1UL << EXTI_IMR2_IM55_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR2_IM55               EXTI_IMR2_IM55_Msk                        /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos           (24U)
+#define EXTI_IMR2_IM56_Msk           (0x1UL << EXTI_IMR2_IM56_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR2_IM56               EXTI_IMR2_IM56_Msk                        /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos           (25U)
+#define EXTI_IMR2_IM57_Msk           (0x1UL << EXTI_IMR2_IM57_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR2_IM57               EXTI_IMR2_IM57_Msk                        /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos           (26U)
+#define EXTI_IMR2_IM58_Msk           (0x1UL << EXTI_IMR2_IM58_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR2_IM58               EXTI_IMR2_IM58_Msk                        /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM60_Pos           (28U)
+#define EXTI_IMR2_IM60_Msk           (0x1UL << EXTI_IMR2_IM60_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR2_IM60               EXTI_IMR2_IM60_Msk                        /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos           (29U)
+#define EXTI_IMR2_IM61_Msk           (0x1UL << EXTI_IMR2_IM61_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR2_IM61               EXTI_IMR2_IM61_Msk                        /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos           (30U)
+#define EXTI_IMR2_IM62_Msk           (0x1UL << EXTI_IMR2_IM62_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR2_IM62               EXTI_IMR2_IM62_Msk                        /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos           (31U)
+#define EXTI_IMR2_IM63_Msk           (0x1UL << EXTI_IMR2_IM63_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR2_IM63               EXTI_IMR2_IM63_Msk                        /*!< Interrupt Mask on line 63 */
+#define EXTI_IMR2_IM_Pos             (0U)
+#define EXTI_IMR2_IM_Msk             (0xF7FFFFFFUL << EXTI_IMR2_IM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_IMR2_IM                 EXTI_IMR2_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos           (0U)
+#define EXTI_EMR2_EM32_Msk           (0x1UL << EXTI_EMR2_EM32_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR2_EM32               EXTI_EMR2_EM32_Msk                        /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos           (1U)
+#define EXTI_EMR2_EM33_Msk           (0x1UL << EXTI_EMR2_EM33_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR2_EM33               EXTI_EMR2_EM33_Msk                        /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos           (2U)
+#define EXTI_EMR2_EM34_Msk           (0x1UL << EXTI_EMR2_EM34_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR2_EM34               EXTI_EMR2_EM34_Msk                        /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos           (3U)
+#define EXTI_EMR2_EM35_Msk           (0x1UL << EXTI_EMR2_EM35_Pos)             /*!< 0x00000008 */
+#define EXTI_EMR2_EM35               EXTI_EMR2_EM35_Msk                        /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos           (4U)
+#define EXTI_EMR2_EM36_Msk           (0x1UL << EXTI_EMR2_EM36_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR2_EM36               EXTI_EMR2_EM36_Msk                        /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos           (5U)
+#define EXTI_EMR2_EM37_Msk           (0x1UL << EXTI_EMR2_EM37_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR2_EM37               EXTI_EMR2_EM37_Msk                        /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos           (6U)
+#define EXTI_EMR2_EM38_Msk           (0x1UL << EXTI_EMR2_EM38_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR2_EM38               EXTI_EMR2_EM38_Msk                        /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos           (7U)
+#define EXTI_EMR2_EM39_Msk           (0x1UL << EXTI_EMR2_EM39_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR2_EM39               EXTI_EMR2_EM39_Msk                        /*!< Event Mask on line 39 */
+#define EXTI_EMR2_EM40_Pos           (8U)
+#define EXTI_EMR2_EM40_Msk           (0x1UL << EXTI_EMR2_EM40_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR2_EM40               EXTI_EMR2_EM40_Msk                        /*!< Event Mask on line 40 */
+#define EXTI_EMR2_EM41_Pos           (9U)
+#define EXTI_EMR2_EM41_Msk           (0x1UL << EXTI_EMR2_EM41_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR2_EM41               EXTI_EMR2_EM41_Msk                        /*!< Event Mask on line 41 */
+#define EXTI_EMR2_EM42_Pos           (10U)
+#define EXTI_EMR2_EM42_Msk           (0x1UL << EXTI_EMR2_EM42_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR2_EM42               EXTI_EMR2_EM42_Msk                        /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos           (11U)
+#define EXTI_EMR2_EM43_Msk           (0x1UL << EXTI_EMR2_EM43_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR2_EM43               EXTI_EMR2_EM43_Msk                        /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos           (12U)
+#define EXTI_EMR2_EM44_Msk           (0x1UL << EXTI_EMR2_EM44_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR2_EM44               EXTI_EMR2_EM44_Msk                        /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM45_Pos           (13U)
+#define EXTI_EMR2_EM45_Msk           (0x1UL << EXTI_EMR2_EM45_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR2_EM45               EXTI_EMR2_EM45_Msk                        /*!< Event Mask on line 45 */
+#define EXTI_EMR2_EM46_Pos           (14U)
+#define EXTI_EMR2_EM46_Msk           (0x1UL << EXTI_EMR2_EM46_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR2_EM46               EXTI_EMR2_EM46_Msk                        /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos           (15U)
+#define EXTI_EMR2_EM47_Msk           (0x1UL << EXTI_EMR2_EM47_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR2_EM47               EXTI_EMR2_EM47_Msk                        /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos           (16U)
+#define EXTI_EMR2_EM48_Msk           (0x1UL << EXTI_EMR2_EM48_Pos)             /*!< 0x00010000 */
+#define EXTI_EMR2_EM48               EXTI_EMR2_EM48_Msk                        /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos           (17U)
+#define EXTI_EMR2_EM49_Msk           (0x1UL << EXTI_EMR2_EM49_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR2_EM49               EXTI_EMR2_EM49_Msk                        /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos           (18U)
+#define EXTI_EMR2_EM50_Msk           (0x1UL << EXTI_EMR2_EM50_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR2_EM50               EXTI_EMR2_EM50_Msk                        /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos           (19U)
+#define EXTI_EMR2_EM51_Msk           (0x1UL << EXTI_EMR2_EM51_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR2_EM51               EXTI_EMR2_EM51_Msk                        /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos           (20U)
+#define EXTI_EMR2_EM52_Msk           (0x1UL << EXTI_EMR2_EM52_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR2_EM52               EXTI_EMR2_EM52_Msk                        /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos           (21U)
+#define EXTI_EMR2_EM53_Msk           (0x1UL << EXTI_EMR2_EM53_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR2_EM53               EXTI_EMR2_EM53_Msk                        /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos           (22U)
+#define EXTI_EMR2_EM54_Msk           (0x1UL << EXTI_EMR2_EM54_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR2_EM54               EXTI_EMR2_EM54_Msk                        /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos           (23U)
+#define EXTI_EMR2_EM55_Msk           (0x1UL << EXTI_EMR2_EM55_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR2_EM55               EXTI_EMR2_EM55_Msk                        /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos           (24U)
+#define EXTI_EMR2_EM56_Msk           (0x1UL << EXTI_EMR2_EM56_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR2_EM56               EXTI_EMR2_EM56_Msk                        /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos           (25U)
+#define EXTI_EMR2_EM57_Msk           (0x1UL << EXTI_EMR2_EM57_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR2_EM57               EXTI_EMR2_EM57_Msk                        /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos           (26U)
+#define EXTI_EMR2_EM58_Msk           (0x1UL << EXTI_EMR2_EM58_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR2_EM58               EXTI_EMR2_EM58_Msk                        /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM60_Pos           (28U)
+#define EXTI_EMR2_EM60_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR2_EM60               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos           (29U)
+#define EXTI_EMR2_EM61_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR2_EM61               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos           (30U)
+#define EXTI_EMR2_EM62_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR2_EM62               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos           (31U)
+#define EXTI_EMR2_EM63_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR2_EM63               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 63 */
+#define EXTI_EMR2_EM_Pos             (0U)
+#define EXTI_EMR2_EM_Msk             (0xF7FFFFFFUL << EXTI_EMR2_EM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_EMR2_EM                 EXTI_EMR2_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR3 register  ******************/
+#define EXTI_IMR3_IM64_Pos           (0U)
+#define EXTI_IMR3_IM64_Msk           (0x1UL << EXTI_IMR3_IM64_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR3_IM64               EXTI_IMR3_IM64_Msk                        /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos           (1U)
+#define EXTI_IMR3_IM65_Msk           (0x1UL << EXTI_IMR3_IM65_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR3_IM65               EXTI_IMR3_IM65_Msk                        /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos           (2U)
+#define EXTI_IMR3_IM66_Msk           (0x1UL << EXTI_IMR3_IM66_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR3_IM66               EXTI_IMR3_IM66_Msk                        /*!< Interrupt Mask on line 66  */
+#define EXTI_IMR3_IM68_Pos           (4U)
+#define EXTI_IMR3_IM68_Msk           (0x1UL << EXTI_IMR3_IM68_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR3_IM68               EXTI_IMR3_IM68_Msk                        /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos           (5U)
+#define EXTI_IMR3_IM69_Msk           (0x1UL << EXTI_IMR3_IM69_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR3_IM69               EXTI_IMR3_IM69_Msk                        /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos           (6U)
+#define EXTI_IMR3_IM70_Msk           (0x1UL << EXTI_IMR3_IM70_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR3_IM70               EXTI_IMR3_IM70_Msk                        /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos           (7U)
+#define EXTI_IMR3_IM71_Msk           (0x1UL << EXTI_IMR3_IM71_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR3_IM71               EXTI_IMR3_IM71_Msk                        /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos           (8U)
+#define EXTI_IMR3_IM72_Msk           (0x1UL << EXTI_IMR3_IM72_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR3_IM72               EXTI_IMR3_IM72_Msk                        /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos           (9U)
+#define EXTI_IMR3_IM73_Msk           (0x1UL << EXTI_IMR3_IM73_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR3_IM73               EXTI_IMR3_IM73_Msk                        /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos           (10U)
+#define EXTI_IMR3_IM74_Msk           (0x1UL << EXTI_IMR3_IM74_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR3_IM74               EXTI_IMR3_IM74_Msk                        /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM77_Pos           (13U)
+#define EXTI_IMR3_IM77_Msk           (0x1UL << EXTI_IMR3_IM77_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR3_IM77               EXTI_IMR3_IM77_Msk                        /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM_Pos             (0U)
+#define EXTI_IMR3_IM_Msk             (0x27F7UL << EXTI_IMR3_IM_Pos)             /*!< 0x000027F7 */
+#define EXTI_IMR3_IM                 EXTI_IMR3_IM_Msk                           /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR3 register  ******************/
+#define EXTI_EMR3_EM64_Pos           (0U)
+#define EXTI_EMR3_EM64_Msk           (0x1UL << EXTI_EMR3_EM64_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR3_EM64               EXTI_EMR3_EM64_Msk                        /*!< Event Mask on line 64 */
+#define EXTI_EMR3_EM65_Pos           (1U)
+#define EXTI_EMR3_EM65_Msk           (0x1UL << EXTI_EMR3_EM65_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR3_EM65               EXTI_EMR3_EM65_Msk                        /*!< Event Mask on line 65 */
+#define EXTI_EMR3_EM66_Pos           (2U)
+#define EXTI_EMR3_EM66_Msk           (0x1UL << EXTI_EMR3_EM66_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR3_EM66               EXTI_EMR3_EM66_Msk                        /*!< Event Mask on line 66  */
+#define EXTI_EMR3_EM68_Pos           (4U)
+#define EXTI_EMR3_EM68_Msk           (0x1UL << EXTI_EMR3_EM68_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR3_EM68               EXTI_EMR3_EM68_Msk                        /*!< Event Mask on line 68 */
+#define EXTI_EMR3_EM69_Pos           (5U)
+#define EXTI_EMR3_EM69_Msk           (0x1UL << EXTI_EMR3_EM69_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR3_EM69               EXTI_EMR3_EM69_Msk                        /*!< Event Mask on line 69 */
+#define EXTI_EMR3_EM70_Pos           (6U)
+#define EXTI_EMR3_EM70_Msk           (0x1UL << EXTI_EMR3_EM70_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR3_EM70               EXTI_EMR3_EM70_Msk                        /*!< Event Mask on line 70 */
+#define EXTI_EMR3_EM71_Pos           (7U)
+#define EXTI_EMR3_EM71_Msk           (0x1UL << EXTI_EMR3_EM71_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR3_EM71               EXTI_EMR3_EM71_Msk                        /*!< Event Mask on line 71 */
+#define EXTI_EMR3_EM72_Pos           (8U)
+#define EXTI_EMR3_EM72_Msk           (0x1UL << EXTI_EMR3_EM72_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR3_EM72               EXTI_EMR3_EM72_Msk                        /*!< Event Mask on line 72 */
+#define EXTI_EMR3_EM73_Pos           (9U)
+#define EXTI_EMR3_EM73_Msk           (0x1UL << EXTI_EMR3_EM73_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR3_EM73               EXTI_EMR3_EM73_Msk                        /*!< Event Mask on line 73 */
+#define EXTI_EMR3_EM74_Pos           (10U)
+#define EXTI_EMR3_EM74_Msk           (0x1UL << EXTI_EMR3_EM74_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR3_EM74               EXTI_EMR3_EM74_Msk                        /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM77_Pos           (13U)
+#define EXTI_EMR3_EM77_Msk           (0x1UL << EXTI_EMR3_EM77_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR3_EM77               EXTI_EMR3_EM77_Msk                        /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM_Pos             (0U)
+#define EXTI_EMR3_EM_Msk             (0x27F7UL << EXTI_EMR3_EM_Pos)             /*!< 0x000027F7 */
+#define EXTI_EMR3_EM                 EXTI_EMR3_EM_Msk                           /*!< Event Mask All */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos           (0U)
+#define FDCAN_CREL_DAY_Msk           (0xFFUL << FDCAN_CREL_DAY_Pos)            /*!< 0x000000FF */
+#define FDCAN_CREL_DAY               FDCAN_CREL_DAY_Msk                        /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos           (8U)
+#define FDCAN_CREL_MON_Msk           (0xFFUL << FDCAN_CREL_MON_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON               FDCAN_CREL_MON_Msk                        /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos          (16U)
+#define FDCAN_CREL_YEAR_Msk          (0xFUL << FDCAN_CREL_YEAR_Pos)            /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR              FDCAN_CREL_YEAR_Msk                       /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos       (20U)
+#define FDCAN_CREL_SUBSTEP_Msk       (0xFUL << FDCAN_CREL_SUBSTEP_Pos)         /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP           FDCAN_CREL_SUBSTEP_Msk                    /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos          (24U)
+#define FDCAN_CREL_STEP_Msk          (0xFUL << FDCAN_CREL_STEP_Pos)            /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP              FDCAN_CREL_STEP_Msk                       /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos           (28U)
+#define FDCAN_CREL_REL_Msk           (0xFUL << FDCAN_CREL_REL_Pos)             /*!< 0xF0000000 */
+#define FDCAN_CREL_REL               FDCAN_CREL_REL_Msk                        /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos           (0U)
+#define FDCAN_ENDN_ETV_Msk           (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV               FDCAN_ENDN_ETV_Msk                        /*!<Endianness Test Value                   */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos          (0U)
+#define FDCAN_DBTP_DSJW_Msk          (0xFUL << FDCAN_DBTP_DSJW_Pos)            /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW              FDCAN_DBTP_DSJW_Msk                       /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos        (4U)
+#define FDCAN_DBTP_DTSEG2_Msk        (0xFUL << FDCAN_DBTP_DTSEG2_Pos)          /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2            FDCAN_DBTP_DTSEG2_Msk                     /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos        (8U)
+#define FDCAN_DBTP_DTSEG1_Msk        (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)         /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1            FDCAN_DBTP_DTSEG1_Msk                     /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos          (16U)
+#define FDCAN_DBTP_DBRP_Msk          (0x1FUL << FDCAN_DBTP_DBRP_Pos)           /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP              FDCAN_DBTP_DBRP_Msk                       /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos           (23U)
+#define FDCAN_DBTP_TDC_Msk           (0x1UL << FDCAN_DBTP_TDC_Pos)             /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC               FDCAN_DBTP_TDC_Msk                        /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos          (4U)
+#define FDCAN_TEST_LBCK_Msk          (0x1UL << FDCAN_TEST_LBCK_Pos)            /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK              FDCAN_TEST_LBCK_Msk                       /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos            (5U)
+#define FDCAN_TEST_TX_Msk            (0x3UL << FDCAN_TEST_TX_Pos)              /*!< 0x00000060 */
+#define FDCAN_TEST_TX                FDCAN_TEST_TX_Msk                         /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos            (7U)
+#define FDCAN_TEST_RX_Msk            (0x1UL << FDCAN_TEST_RX_Pos)              /*!< 0x00000080 */
+#define FDCAN_TEST_RX                FDCAN_TEST_RX_Msk                         /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos            (0U)
+#define FDCAN_RWD_WDC_Msk            (0xFFUL << FDCAN_RWD_WDC_Pos)             /*!< 0x000000FF */
+#define FDCAN_RWD_WDC                FDCAN_RWD_WDC_Msk                         /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos            (8U)
+#define FDCAN_RWD_WDV_Msk            (0xFFUL << FDCAN_RWD_WDV_Pos)             /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV                FDCAN_RWD_WDV_Msk                         /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  *******************/
+#define FDCAN_CCCR_INIT_Pos          (0U)
+#define FDCAN_CCCR_INIT_Msk          (0x1UL << FDCAN_CCCR_INIT_Pos)            /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT              FDCAN_CCCR_INIT_Msk                       /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos           (1U)
+#define FDCAN_CCCR_CCE_Msk           (0x1UL << FDCAN_CCCR_CCE_Pos)             /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE               FDCAN_CCCR_CCE_Msk                        /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos           (2U)
+#define FDCAN_CCCR_ASM_Msk           (0x1UL << FDCAN_CCCR_ASM_Pos)             /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM               FDCAN_CCCR_ASM_Msk                        /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos           (3U)
+#define FDCAN_CCCR_CSA_Msk           (0x1UL << FDCAN_CCCR_CSA_Pos)             /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA               FDCAN_CCCR_CSA_Msk                        /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos           (4U)
+#define FDCAN_CCCR_CSR_Msk           (0x1UL << FDCAN_CCCR_CSR_Pos)             /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR               FDCAN_CCCR_CSR_Msk                        /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos           (5U)
+#define FDCAN_CCCR_MON_Msk           (0x1UL << FDCAN_CCCR_MON_Pos)             /*!< 0x00000020 */
+#define FDCAN_CCCR_MON               FDCAN_CCCR_MON_Msk                        /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos           (6U)
+#define FDCAN_CCCR_DAR_Msk           (0x1UL << FDCAN_CCCR_DAR_Pos)             /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR               FDCAN_CCCR_DAR_Msk                        /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos          (7U)
+#define FDCAN_CCCR_TEST_Msk          (0x1UL << FDCAN_CCCR_TEST_Pos)            /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST              FDCAN_CCCR_TEST_Msk                       /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos          (8U)
+#define FDCAN_CCCR_FDOE_Msk          (0x1UL << FDCAN_CCCR_FDOE_Pos)            /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE              FDCAN_CCCR_FDOE_Msk                       /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos          (9U)
+#define FDCAN_CCCR_BRSE_Msk          (0x1UL << FDCAN_CCCR_BRSE_Pos)            /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE              FDCAN_CCCR_BRSE_Msk                       /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos          (12U)
+#define FDCAN_CCCR_PXHD_Msk          (0x1UL << FDCAN_CCCR_PXHD_Pos)            /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD              FDCAN_CCCR_PXHD_Msk                       /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos          (13U)
+#define FDCAN_CCCR_EFBI_Msk          (0x1UL << FDCAN_CCCR_EFBI_Pos)            /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI              FDCAN_CCCR_EFBI_Msk                       /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos           (14U)
+#define FDCAN_CCCR_TXP_Msk           (0x1UL << FDCAN_CCCR_TXP_Pos)             /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP               FDCAN_CCCR_TXP_Msk                        /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos          (15U)
+#define FDCAN_CCCR_NISO_Msk          (0x1UL << FDCAN_CCCR_NISO_Pos)            /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO              FDCAN_CCCR_NISO_Msk                       /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  *******************/
+#define FDCAN_NBTP_NTSEG2_Pos        (0U)
+#define FDCAN_NBTP_NTSEG2_Msk        (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)         /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2            FDCAN_NBTP_NTSEG2_Msk                     /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos        (8U)
+#define FDCAN_NBTP_NTSEG1_Msk        (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)         /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1            FDCAN_NBTP_NTSEG1_Msk                     /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos          (16U)
+#define FDCAN_NBTP_NBRP_Msk          (0x1FFUL << FDCAN_NBTP_NBRP_Pos)          /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP              FDCAN_NBTP_NBRP_Msk                       /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos          (25U)
+#define FDCAN_NBTP_NSJW_Msk          (0x7FUL << FDCAN_NBTP_NSJW_Pos)           /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW              FDCAN_NBTP_NSJW_Msk                       /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  *******************/
+#define FDCAN_TSCC_TSS_Pos           (0U)
+#define FDCAN_TSCC_TSS_Msk           (0x3UL << FDCAN_TSCC_TSS_Pos)             /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS               FDCAN_TSCC_TSS_Msk                        /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos           (16U)
+#define FDCAN_TSCC_TCP_Msk           (0xFUL << FDCAN_TSCC_TCP_Pos)             /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP               FDCAN_TSCC_TCP_Msk                        /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  *******************/
+#define FDCAN_TSCV_TSC_Pos           (0U)
+#define FDCAN_TSCV_TSC_Msk           (0xFFFFUL << FDCAN_TSCV_TSC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC               FDCAN_TSCV_TSC_Msk                        /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  *******************/
+#define FDCAN_TOCC_ETOC_Pos          (0U)
+#define FDCAN_TOCC_ETOC_Msk          (0x1UL << FDCAN_TOCC_ETOC_Pos)            /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC              FDCAN_TOCC_ETOC_Msk                       /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos           (1U)
+#define FDCAN_TOCC_TOS_Msk           (0x3UL << FDCAN_TOCC_TOS_Pos)             /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS               FDCAN_TOCC_TOS_Msk                        /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos           (16U)
+#define FDCAN_TOCC_TOP_Msk           (0xFFFFUL << FDCAN_TOCC_TOP_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP               FDCAN_TOCC_TOP_Msk                        /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  *******************/
+#define FDCAN_TOCV_TOC_Pos           (0U)
+#define FDCAN_TOCV_TOC_Msk           (0xFFFFUL << FDCAN_TOCV_TOC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC               FDCAN_TOCV_TOC_Msk                        /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  ********************/
+#define FDCAN_ECR_TEC_Pos            (0U)
+#define FDCAN_ECR_TEC_Msk            (0xFFUL << FDCAN_ECR_TEC_Pos)             /*!< 0x000000FF */
+#define FDCAN_ECR_TEC                FDCAN_ECR_TEC_Msk                         /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos            (8U)
+#define FDCAN_ECR_REC_Msk            (0x7FUL << FDCAN_ECR_REC_Pos)             /*!< 0x00007F00 */
+#define FDCAN_ECR_REC                FDCAN_ECR_REC_Msk                         /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos             (15U)
+#define FDCAN_ECR_RP_Msk             (0x1UL << FDCAN_ECR_RP_Pos)               /*!< 0x00008000 */
+#define FDCAN_ECR_RP                 FDCAN_ECR_RP_Msk                          /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos            (16U)
+#define FDCAN_ECR_CEL_Msk            (0xFFUL << FDCAN_ECR_CEL_Pos)             /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL                FDCAN_ECR_CEL_Msk                         /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  ********************/
+#define FDCAN_PSR_LEC_Pos            (0U)
+#define FDCAN_PSR_LEC_Msk            (0x7UL << FDCAN_PSR_LEC_Pos)              /*!< 0x00000007 */
+#define FDCAN_PSR_LEC                FDCAN_PSR_LEC_Msk                         /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos            (3U)
+#define FDCAN_PSR_ACT_Msk            (0x3UL << FDCAN_PSR_ACT_Pos)              /*!< 0x00000018 */
+#define FDCAN_PSR_ACT                FDCAN_PSR_ACT_Msk                         /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos             (5U)
+#define FDCAN_PSR_EP_Msk             (0x1UL << FDCAN_PSR_EP_Pos)               /*!< 0x00000020 */
+#define FDCAN_PSR_EP                 FDCAN_PSR_EP_Msk                          /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos             (6U)
+#define FDCAN_PSR_EW_Msk             (0x1UL << FDCAN_PSR_EW_Pos)               /*!< 0x00000040 */
+#define FDCAN_PSR_EW                 FDCAN_PSR_EW_Msk                          /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos             (7U)
+#define FDCAN_PSR_BO_Msk             (0x1UL << FDCAN_PSR_BO_Pos)               /*!< 0x00000080 */
+#define FDCAN_PSR_BO                 FDCAN_PSR_BO_Msk                          /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos           (8U)
+#define FDCAN_PSR_DLEC_Msk           (0x7UL << FDCAN_PSR_DLEC_Pos)             /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC               FDCAN_PSR_DLEC_Msk                        /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos           (11U)
+#define FDCAN_PSR_RESI_Msk           (0x1UL << FDCAN_PSR_RESI_Pos)             /*!< 0x00000800 */
+#define FDCAN_PSR_RESI               FDCAN_PSR_RESI_Msk                        /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos           (12U)
+#define FDCAN_PSR_RBRS_Msk           (0x1UL << FDCAN_PSR_RBRS_Pos)             /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS               FDCAN_PSR_RBRS_Msk                        /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos           (13U)
+#define FDCAN_PSR_REDL_Msk           (0x1UL << FDCAN_PSR_REDL_Pos)             /*!< 0x00002000 */
+#define FDCAN_PSR_REDL               FDCAN_PSR_REDL_Msk                        /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos            (14U)
+#define FDCAN_PSR_PXE_Msk            (0x1UL << FDCAN_PSR_PXE_Pos)              /*!< 0x00004000 */
+#define FDCAN_PSR_PXE                FDCAN_PSR_PXE_Msk                         /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos           (16U)
+#define FDCAN_PSR_TDCV_Msk           (0x7FUL << FDCAN_PSR_TDCV_Pos)            /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV               FDCAN_PSR_TDCV_Msk                        /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  *******************/
+#define FDCAN_TDCR_TDCF_Pos          (0U)
+#define FDCAN_TDCR_TDCF_Msk          (0x7FUL << FDCAN_TDCR_TDCF_Pos)           /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF              FDCAN_TDCR_TDCF_Msk                       /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos          (8U)
+#define FDCAN_TDCR_TDCO_Msk          (0x7FUL << FDCAN_TDCR_TDCO_Pos)           /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO              FDCAN_TDCR_TDCO_Msk                       /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  *********************/
+#define FDCAN_IR_RF0N_Pos            (0U)
+#define FDCAN_IR_RF0N_Msk            (0x1UL << FDCAN_IR_RF0N_Pos)              /*!< 0x00000001 */
+#define FDCAN_IR_RF0N                FDCAN_IR_RF0N_Msk                         /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos            (1U)
+#define FDCAN_IR_RF0W_Msk            (0x1UL << FDCAN_IR_RF0W_Pos)              /*!< 0x00000002 */
+#define FDCAN_IR_RF0W                FDCAN_IR_RF0W_Msk                         /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos            (2U)
+#define FDCAN_IR_RF0F_Msk            (0x1UL << FDCAN_IR_RF0F_Pos)              /*!< 0x00000004 */
+#define FDCAN_IR_RF0F                FDCAN_IR_RF0F_Msk                         /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos            (3U)
+#define FDCAN_IR_RF0L_Msk            (0x1UL << FDCAN_IR_RF0L_Pos)              /*!< 0x00000008 */
+#define FDCAN_IR_RF0L                FDCAN_IR_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos            (4U)
+#define FDCAN_IR_RF1N_Msk            (0x1UL << FDCAN_IR_RF1N_Pos)              /*!< 0x00000010 */
+#define FDCAN_IR_RF1N                FDCAN_IR_RF1N_Msk                         /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos            (5U)
+#define FDCAN_IR_RF1W_Msk            (0x1UL << FDCAN_IR_RF1W_Pos)              /*!< 0x00000020 */
+#define FDCAN_IR_RF1W                FDCAN_IR_RF1W_Msk                         /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos            (6U)
+#define FDCAN_IR_RF1F_Msk            (0x1UL << FDCAN_IR_RF1F_Pos)              /*!< 0x00000040 */
+#define FDCAN_IR_RF1F                FDCAN_IR_RF1F_Msk                         /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos            (7U)
+#define FDCAN_IR_RF1L_Msk            (0x1UL << FDCAN_IR_RF1L_Pos)              /*!< 0x00000080 */
+#define FDCAN_IR_RF1L                FDCAN_IR_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos             (8U)
+#define FDCAN_IR_HPM_Msk             (0x1UL << FDCAN_IR_HPM_Pos)               /*!< 0x00000100 */
+#define FDCAN_IR_HPM                 FDCAN_IR_HPM_Msk                          /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos              (9U)
+#define FDCAN_IR_TC_Msk              (0x1UL << FDCAN_IR_TC_Pos)                /*!< 0x00000200 */
+#define FDCAN_IR_TC                  FDCAN_IR_TC_Msk                           /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos             (10U)
+#define FDCAN_IR_TCF_Msk             (0x1UL << FDCAN_IR_TCF_Pos)               /*!< 0x00000400 */
+#define FDCAN_IR_TCF                 FDCAN_IR_TCF_Msk                          /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos             (11U)
+#define FDCAN_IR_TFE_Msk             (0x1UL << FDCAN_IR_TFE_Pos)               /*!< 0x00000800 */
+#define FDCAN_IR_TFE                 FDCAN_IR_TFE_Msk                          /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos            (12U)
+#define FDCAN_IR_TEFN_Msk            (0x1UL << FDCAN_IR_TEFN_Pos)              /*!< 0x00001000 */
+#define FDCAN_IR_TEFN                FDCAN_IR_TEFN_Msk                         /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos            (13U)
+#define FDCAN_IR_TEFW_Msk            (0x1UL << FDCAN_IR_TEFW_Pos)              /*!< 0x00002000 */
+#define FDCAN_IR_TEFW                FDCAN_IR_TEFW_Msk                         /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos            (14U)
+#define FDCAN_IR_TEFF_Msk            (0x1UL << FDCAN_IR_TEFF_Pos)              /*!< 0x00004000 */
+#define FDCAN_IR_TEFF                FDCAN_IR_TEFF_Msk                         /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos            (15U)
+#define FDCAN_IR_TEFL_Msk            (0x1UL << FDCAN_IR_TEFL_Pos)              /*!< 0x00008000 */
+#define FDCAN_IR_TEFL                FDCAN_IR_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos             (16U)
+#define FDCAN_IR_TSW_Msk             (0x1UL << FDCAN_IR_TSW_Pos)               /*!< 0x00010000 */
+#define FDCAN_IR_TSW                 FDCAN_IR_TSW_Msk                          /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos            (17U)
+#define FDCAN_IR_MRAF_Msk            (0x1UL << FDCAN_IR_MRAF_Pos)              /*!< 0x00020000 */
+#define FDCAN_IR_MRAF                FDCAN_IR_MRAF_Msk                         /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos             (18U)
+#define FDCAN_IR_TOO_Msk             (0x1UL << FDCAN_IR_TOO_Pos)               /*!< 0x00040000 */
+#define FDCAN_IR_TOO                 FDCAN_IR_TOO_Msk                          /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos             (19U)
+#define FDCAN_IR_DRX_Msk             (0x1UL << FDCAN_IR_DRX_Pos)               /*!< 0x00080000 */
+#define FDCAN_IR_DRX                 FDCAN_IR_DRX_Msk                          /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos             (22U)
+#define FDCAN_IR_ELO_Msk             (0x1UL << FDCAN_IR_ELO_Pos)               /*!< 0x00400000 */
+#define FDCAN_IR_ELO                 FDCAN_IR_ELO_Msk                          /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos              (23U)
+#define FDCAN_IR_EP_Msk              (0x1UL << FDCAN_IR_EP_Pos)                /*!< 0x00800000 */
+#define FDCAN_IR_EP                  FDCAN_IR_EP_Msk                           /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos              (24U)
+#define FDCAN_IR_EW_Msk              (0x1UL << FDCAN_IR_EW_Pos)                /*!< 0x01000000 */
+#define FDCAN_IR_EW                  FDCAN_IR_EW_Msk                           /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos              (25U)
+#define FDCAN_IR_BO_Msk              (0x1UL << FDCAN_IR_BO_Pos)                /*!< 0x02000000 */
+#define FDCAN_IR_BO                  FDCAN_IR_BO_Msk                           /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos             (26U)
+#define FDCAN_IR_WDI_Msk             (0x1UL << FDCAN_IR_WDI_Pos)               /*!< 0x04000000 */
+#define FDCAN_IR_WDI                 FDCAN_IR_WDI_Msk                          /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos             (27U)
+#define FDCAN_IR_PEA_Msk             (0x1UL << FDCAN_IR_PEA_Pos)               /*!< 0x08000000 */
+#define FDCAN_IR_PEA                 FDCAN_IR_PEA_Msk                          /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos             (28U)
+#define FDCAN_IR_PED_Msk             (0x1UL << FDCAN_IR_PED_Pos)               /*!< 0x10000000 */
+#define FDCAN_IR_PED                 FDCAN_IR_PED_Msk                          /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos             (29U)
+#define FDCAN_IR_ARA_Msk             (0x1UL << FDCAN_IR_ARA_Pos)               /*!< 0x20000000 */
+#define FDCAN_IR_ARA                 FDCAN_IR_ARA_Msk                          /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  *********************/
+#define FDCAN_IE_RF0NE_Pos           (0U)
+#define FDCAN_IE_RF0NE_Msk           (0x1UL << FDCAN_IE_RF0NE_Pos)             /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE               FDCAN_IE_RF0NE_Msk                        /*!<Rx FIFO 0 New Message Enable             */
+#define FDCAN_IE_RF0WE_Pos           (1U)
+#define FDCAN_IE_RF0WE_Msk           (0x1UL << FDCAN_IE_RF0WE_Pos)             /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE               FDCAN_IE_RF0WE_Msk                        /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos           (2U)
+#define FDCAN_IE_RF0FE_Msk           (0x1UL << FDCAN_IE_RF0FE_Pos)             /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE               FDCAN_IE_RF0FE_Msk                        /*!<Rx FIFO 0 Full Enable                    */
+#define FDCAN_IE_RF0LE_Pos           (3U)
+#define FDCAN_IE_RF0LE_Msk           (0x1UL << FDCAN_IE_RF0LE_Pos)             /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE               FDCAN_IE_RF0LE_Msk                        /*!<Rx FIFO 0 Message Lost Enable            */
+#define FDCAN_IE_RF1NE_Pos           (4U)
+#define FDCAN_IE_RF1NE_Msk           (0x1UL << FDCAN_IE_RF1NE_Pos)             /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE               FDCAN_IE_RF1NE_Msk                        /*!<Rx FIFO 1 New Message Enable             */
+#define FDCAN_IE_RF1WE_Pos           (5U)
+#define FDCAN_IE_RF1WE_Msk           (0x1UL << FDCAN_IE_RF1WE_Pos)             /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE               FDCAN_IE_RF1WE_Msk                        /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos           (6U)
+#define FDCAN_IE_RF1FE_Msk           (0x1UL << FDCAN_IE_RF1FE_Pos)             /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE               FDCAN_IE_RF1FE_Msk                        /*!<Rx FIFO 1 Full Enable                    */
+#define FDCAN_IE_RF1LE_Pos           (7U)
+#define FDCAN_IE_RF1LE_Msk           (0x1UL << FDCAN_IE_RF1LE_Pos)             /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE               FDCAN_IE_RF1LE_Msk                        /*!<Rx FIFO 1 Message Lost Enable            */
+#define FDCAN_IE_HPME_Pos            (8U)
+#define FDCAN_IE_HPME_Msk            (0x1UL << FDCAN_IE_HPME_Pos)              /*!< 0x00000100 */
+#define FDCAN_IE_HPME                FDCAN_IE_HPME_Msk                         /*!<High Priority Message Enable             */
+#define FDCAN_IE_TCE_Pos             (9U)
+#define FDCAN_IE_TCE_Msk             (0x1UL << FDCAN_IE_TCE_Pos)               /*!< 0x00000200 */
+#define FDCAN_IE_TCE                 FDCAN_IE_TCE_Msk                          /*!<Transmission Completed Enable            */
+#define FDCAN_IE_TCFE_Pos            (10U)
+#define FDCAN_IE_TCFE_Msk            (0x1UL << FDCAN_IE_TCFE_Pos)              /*!< 0x00000400 */
+#define FDCAN_IE_TCFE                FDCAN_IE_TCFE_Msk                         /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos            (11U)
+#define FDCAN_IE_TFEE_Msk            (0x1UL << FDCAN_IE_TFEE_Pos)              /*!< 0x00000800 */
+#define FDCAN_IE_TFEE                FDCAN_IE_TFEE_Msk                         /*!<Tx FIFO Empty Enable                     */
+#define FDCAN_IE_TEFNE_Pos           (12U)
+#define FDCAN_IE_TEFNE_Msk           (0x1UL << FDCAN_IE_TEFNE_Pos)             /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE               FDCAN_IE_TEFNE_Msk                        /*!<Tx Event FIFO New Entry Enable           */
+#define FDCAN_IE_TEFWE_Pos           (13U)
+#define FDCAN_IE_TEFWE_Msk           (0x1UL << FDCAN_IE_TEFWE_Pos)             /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE               FDCAN_IE_TEFWE_Msk                        /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos           (14U)
+#define FDCAN_IE_TEFFE_Msk           (0x1UL << FDCAN_IE_TEFFE_Pos)             /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE               FDCAN_IE_TEFFE_Msk                        /*!<Tx Event FIFO Full Enable                */
+#define FDCAN_IE_TEFLE_Pos           (15U)
+#define FDCAN_IE_TEFLE_Msk           (0x1UL << FDCAN_IE_TEFLE_Pos)             /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE               FDCAN_IE_TEFLE_Msk                        /*!<Tx Event FIFO Element Lost Enable        */
+#define FDCAN_IE_TSWE_Pos            (16U)
+#define FDCAN_IE_TSWE_Msk            (0x1UL << FDCAN_IE_TSWE_Pos)              /*!< 0x00010000 */
+#define FDCAN_IE_TSWE                FDCAN_IE_TSWE_Msk                         /*!<Timestamp Wraparound Enable              */
+#define FDCAN_IE_MRAFE_Pos           (17U)
+#define FDCAN_IE_MRAFE_Msk           (0x1UL << FDCAN_IE_MRAFE_Pos)             /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE               FDCAN_IE_MRAFE_Msk                        /*!<Message RAM Access Failure Enable        */
+#define FDCAN_IE_TOOE_Pos            (18U)
+#define FDCAN_IE_TOOE_Msk            (0x1UL << FDCAN_IE_TOOE_Pos)              /*!< 0x00040000 */
+#define FDCAN_IE_TOOE                FDCAN_IE_TOOE_Msk                         /*!<Timeout Occurred Enable                  */
+#define FDCAN_IE_DRXE_Pos            (19U)
+#define FDCAN_IE_DRXE_Msk            (0x1UL << FDCAN_IE_DRXE_Pos)              /*!< 0x00080000 */
+#define FDCAN_IE_DRXE                FDCAN_IE_DRXE_Msk                         /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos            (20U)
+#define FDCAN_IE_BECE_Msk            (0x1UL << FDCAN_IE_BECE_Pos)              /*!< 0x00100000 */
+#define FDCAN_IE_BECE                FDCAN_IE_BECE_Msk                         /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos            (21U)
+#define FDCAN_IE_BEUE_Msk            (0x1UL << FDCAN_IE_BEUE_Pos)              /*!< 0x00200000 */
+#define FDCAN_IE_BEUE                FDCAN_IE_BEUE_Msk                         /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos            (22U)
+#define FDCAN_IE_ELOE_Msk            (0x1UL << FDCAN_IE_ELOE_Pos)              /*!< 0x00400000 */
+#define FDCAN_IE_ELOE                FDCAN_IE_ELOE_Msk                         /*!<Error Logging Overflow Enable            */
+#define FDCAN_IE_EPE_Pos             (23U)
+#define FDCAN_IE_EPE_Msk             (0x1UL << FDCAN_IE_EPE_Pos)               /*!< 0x00800000 */
+#define FDCAN_IE_EPE                 FDCAN_IE_EPE_Msk                          /*!<Error Passive Enable                     */
+#define FDCAN_IE_EWE_Pos             (24U)
+#define FDCAN_IE_EWE_Msk             (0x1UL << FDCAN_IE_EWE_Pos)               /*!< 0x01000000 */
+#define FDCAN_IE_EWE                 FDCAN_IE_EWE_Msk                          /*!<Warning Status Enable                    */
+#define FDCAN_IE_BOE_Pos             (25U)
+#define FDCAN_IE_BOE_Msk             (0x1UL << FDCAN_IE_BOE_Pos)               /*!< 0x02000000 */
+#define FDCAN_IE_BOE                 FDCAN_IE_BOE_Msk                          /*!<Bus_Off Status Enable                    */
+#define FDCAN_IE_WDIE_Pos            (26U)
+#define FDCAN_IE_WDIE_Msk            (0x1UL << FDCAN_IE_WDIE_Pos)              /*!< 0x04000000 */
+#define FDCAN_IE_WDIE                FDCAN_IE_WDIE_Msk                         /*!<Watchdog Interrupt Enable                */
+#define FDCAN_IE_PEAE_Pos            (27U)
+#define FDCAN_IE_PEAE_Msk            (0x1UL << FDCAN_IE_PEAE_Pos)              /*!< 0x08000000 */
+#define FDCAN_IE_PEAE                FDCAN_IE_PEAE_Msk                         /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos            (28U)
+#define FDCAN_IE_PEDE_Msk            (0x1UL << FDCAN_IE_PEDE_Pos)              /*!< 0x10000000 */
+#define FDCAN_IE_PEDE                FDCAN_IE_PEDE_Msk                         /*!<Protocol Error in Data Phase Enable      */
+#define FDCAN_IE_ARAE_Pos            (29U)
+#define FDCAN_IE_ARAE_Msk            (0x1UL << FDCAN_IE_ARAE_Pos)              /*!< 0x20000000 */
+#define FDCAN_IE_ARAE                FDCAN_IE_ARAE_Msk                         /*!<Access to Reserved Address Enable        */
+
+/*****************  Bit definition for FDCAN_ILS register  ********************/
+#define FDCAN_ILS_RF0NL_Pos          (0U)
+#define FDCAN_ILS_RF0NL_Msk          (0x1UL << FDCAN_ILS_RF0NL_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL              FDCAN_ILS_RF0NL_Msk                       /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos          (1U)
+#define FDCAN_ILS_RF0WL_Msk          (0x1UL << FDCAN_ILS_RF0WL_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL              FDCAN_ILS_RF0WL_Msk                       /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos          (2U)
+#define FDCAN_ILS_RF0FL_Msk          (0x1UL << FDCAN_ILS_RF0FL_Pos)            /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL              FDCAN_ILS_RF0FL_Msk                       /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos          (3U)
+#define FDCAN_ILS_RF0LL_Msk          (0x1UL << FDCAN_ILS_RF0LL_Pos)            /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL              FDCAN_ILS_RF0LL_Msk                       /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos          (4U)
+#define FDCAN_ILS_RF1NL_Msk          (0x1UL << FDCAN_ILS_RF1NL_Pos)            /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL              FDCAN_ILS_RF1NL_Msk                       /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos          (5U)
+#define FDCAN_ILS_RF1WL_Msk          (0x1UL << FDCAN_ILS_RF1WL_Pos)            /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL              FDCAN_ILS_RF1WL_Msk                       /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos          (6U)
+#define FDCAN_ILS_RF1FL_Msk          (0x1UL << FDCAN_ILS_RF1FL_Pos)            /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL              FDCAN_ILS_RF1FL_Msk                       /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos          (7U)
+#define FDCAN_ILS_RF1LL_Msk          (0x1UL << FDCAN_ILS_RF1LL_Pos)            /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL              FDCAN_ILS_RF1LL_Msk                       /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos           (8U)
+#define FDCAN_ILS_HPML_Msk           (0x1UL << FDCAN_ILS_HPML_Pos)             /*!< 0x00000100 */
+#define FDCAN_ILS_HPML               FDCAN_ILS_HPML_Msk                        /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos            (9U)
+#define FDCAN_ILS_TCL_Msk            (0x1UL << FDCAN_ILS_TCL_Pos)              /*!< 0x00000200 */
+#define FDCAN_ILS_TCL                FDCAN_ILS_TCL_Msk                         /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos           (10U)
+#define FDCAN_ILS_TCFL_Msk           (0x1UL << FDCAN_ILS_TCFL_Pos)             /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL               FDCAN_ILS_TCFL_Msk                        /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos           (11U)
+#define FDCAN_ILS_TFEL_Msk           (0x1UL << FDCAN_ILS_TFEL_Pos)             /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL               FDCAN_ILS_TFEL_Msk                        /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos          (12U)
+#define FDCAN_ILS_TEFNL_Msk          (0x1UL << FDCAN_ILS_TEFNL_Pos)            /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL              FDCAN_ILS_TEFNL_Msk                       /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos          (13U)
+#define FDCAN_ILS_TEFWL_Msk          (0x1UL << FDCAN_ILS_TEFWL_Pos)            /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL              FDCAN_ILS_TEFWL_Msk                       /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos          (14U)
+#define FDCAN_ILS_TEFFL_Msk          (0x1UL << FDCAN_ILS_TEFFL_Pos)            /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL              FDCAN_ILS_TEFFL_Msk                       /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos          (15U)
+#define FDCAN_ILS_TEFLL_Msk          (0x1UL << FDCAN_ILS_TEFLL_Pos)            /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL              FDCAN_ILS_TEFLL_Msk                       /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos           (16U)
+#define FDCAN_ILS_TSWL_Msk           (0x1UL << FDCAN_ILS_TSWL_Pos)             /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL               FDCAN_ILS_TSWL_Msk                        /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFL_Pos          (17U)
+#define FDCAN_ILS_MRAFL_Msk          (0x1UL << FDCAN_ILS_MRAFL_Pos)            /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFL              FDCAN_ILS_MRAFL_Msk                       /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOL_Pos           (18U)
+#define FDCAN_ILS_TOOL_Msk           (0x1UL << FDCAN_ILS_TOOL_Pos)             /*!< 0x00040000 */
+#define FDCAN_ILS_TOOL               FDCAN_ILS_TOOL_Msk                        /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXL_Pos           (19U)
+#define FDCAN_ILS_DRXL_Msk           (0x1UL << FDCAN_ILS_DRXL_Pos)             /*!< 0x00080000 */
+#define FDCAN_ILS_DRXL               FDCAN_ILS_DRXL_Msk                        /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_ELOL_Pos           (22U)
+#define FDCAN_ILS_ELOL_Msk           (0x1UL << FDCAN_ILS_ELOL_Pos)             /*!< 0x00400000 */
+#define FDCAN_ILS_ELOL               FDCAN_ILS_ELOL_Msk                        /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPL_Pos            (23U)
+#define FDCAN_ILS_EPL_Msk            (0x1UL << FDCAN_ILS_EPL_Pos)              /*!< 0x00800000 */
+#define FDCAN_ILS_EPL                FDCAN_ILS_EPL_Msk                         /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWL_Pos            (24U)
+#define FDCAN_ILS_EWL_Msk            (0x1UL << FDCAN_ILS_EWL_Pos)              /*!< 0x01000000 */
+#define FDCAN_ILS_EWL                FDCAN_ILS_EWL_Msk                         /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOL_Pos            (25U)
+#define FDCAN_ILS_BOL_Msk            (0x1UL << FDCAN_ILS_BOL_Pos)              /*!< 0x02000000 */
+#define FDCAN_ILS_BOL                FDCAN_ILS_BOL_Msk                         /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIL_Pos           (26U)
+#define FDCAN_ILS_WDIL_Msk           (0x1UL << FDCAN_ILS_WDIL_Pos)             /*!< 0x04000000 */
+#define FDCAN_ILS_WDIL               FDCAN_ILS_WDIL_Msk                        /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAL_Pos           (27U)
+#define FDCAN_ILS_PEAL_Msk           (0x1UL << FDCAN_ILS_PEAL_Pos)             /*!< 0x08000000 */
+#define FDCAN_ILS_PEAL               FDCAN_ILS_PEAL_Msk                        /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDL_Pos           (28U)
+#define FDCAN_ILS_PEDL_Msk           (0x1UL << FDCAN_ILS_PEDL_Pos)             /*!< 0x10000000 */
+#define FDCAN_ILS_PEDL               FDCAN_ILS_PEDL_Msk                        /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAL_Pos           (29U)
+#define FDCAN_ILS_ARAL_Msk           (0x1UL << FDCAN_ILS_ARAL_Pos)             /*!< 0x20000000 */
+#define FDCAN_ILS_ARAL               FDCAN_ILS_ARAL_Msk                        /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  ********************/
+#define FDCAN_ILE_EINT0_Pos          (0U)
+#define FDCAN_ILE_EINT0_Msk          (0x1UL << FDCAN_ILE_EINT0_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0              FDCAN_ILE_EINT0_Msk                       /*!<Enable Interrupt Line 0                  */
+#define FDCAN_ILE_EINT1_Pos          (1U)
+#define FDCAN_ILE_EINT1_Msk          (0x1UL << FDCAN_ILE_EINT1_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1              FDCAN_ILE_EINT1_Msk                       /*!<Enable Interrupt Line 1                  */
+
+/*****************  Bit definition for FDCAN_GFC register  ******************/
+#define FDCAN_GFC_RRFE_Pos           (0U)
+#define FDCAN_GFC_RRFE_Msk           (0x1UL << FDCAN_GFC_RRFE_Pos)             /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE               FDCAN_GFC_RRFE_Msk                        /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos           (1U)
+#define FDCAN_GFC_RRFS_Msk           (0x1UL << FDCAN_GFC_RRFS_Pos)             /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS               FDCAN_GFC_RRFS_Msk                        /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos           (2U)
+#define FDCAN_GFC_ANFE_Msk           (0x3UL << FDCAN_GFC_ANFE_Pos)             /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE               FDCAN_GFC_ANFE_Msk                        /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos           (4U)
+#define FDCAN_GFC_ANFS_Msk           (0x3UL << FDCAN_GFC_ANFS_Pos)             /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS               FDCAN_GFC_ANFS_Msk                        /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos        (2U)
+#define FDCAN_SIDFC_FLSSA_Msk        (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA            FDCAN_SIDFC_FLSSA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos          (16U)
+#define FDCAN_SIDFC_LSS_Msk          (0xFFUL << FDCAN_SIDFC_LSS_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS              FDCAN_SIDFC_LSS_Msk                       /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos        (2U)
+#define FDCAN_XIDFC_FLESA_Msk        (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA            FDCAN_XIDFC_FLESA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos          (16U)
+#define FDCAN_XIDFC_LSE_Msk          (0x7FUL << FDCAN_XIDFC_LSE_Pos)           /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE              FDCAN_XIDFC_LSE_Msk                       /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ******************/
+#define FDCAN_XIDAM_EIDM_Pos         (0U)
+#define FDCAN_XIDAM_EIDM_Msk         (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)    /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM             FDCAN_XIDAM_EIDM_Msk                      /*!<Extended ID Mask                         */
+
+/*****************  Bit definition for FDCAN_HPMS register  *******************/
+#define FDCAN_HPMS_BIDX_Pos          (0U)
+#define FDCAN_HPMS_BIDX_Msk          (0x3FUL << FDCAN_HPMS_BIDX_Pos)           /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX              FDCAN_HPMS_BIDX_Msk                       /*!<Buffer Index                             */
+#define FDCAN_HPMS_MSI_Pos           (6U)
+#define FDCAN_HPMS_MSI_Msk           (0x3UL << FDCAN_HPMS_MSI_Pos)             /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI               FDCAN_HPMS_MSI_Msk                        /*!<Message Storage Indicator                */
+#define FDCAN_HPMS_FIDX_Pos          (8U)
+#define FDCAN_HPMS_FIDX_Msk          (0x7FUL << FDCAN_HPMS_FIDX_Pos)           /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX              FDCAN_HPMS_FIDX_Msk                       /*!<Filter Index                             */
+#define FDCAN_HPMS_FLST_Pos          (15U)
+#define FDCAN_HPMS_FLST_Msk          (0x1UL << FDCAN_HPMS_FLST_Pos)            /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST              FDCAN_HPMS_FLST_Msk                       /*!<Filter List                              */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos          (0U)
+#define FDCAN_NDAT1_ND0_Msk          (0x1UL << FDCAN_NDAT1_ND0_Pos)            /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0              FDCAN_NDAT1_ND0_Msk                       /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos          (1U)
+#define FDCAN_NDAT1_ND1_Msk          (0x1UL << FDCAN_NDAT1_ND1_Pos)            /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1              FDCAN_NDAT1_ND1_Msk                       /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos          (2U)
+#define FDCAN_NDAT1_ND2_Msk          (0x1UL << FDCAN_NDAT1_ND2_Pos)            /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2              FDCAN_NDAT1_ND2_Msk                       /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos          (3U)
+#define FDCAN_NDAT1_ND3_Msk          (0x1UL << FDCAN_NDAT1_ND3_Pos)            /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3              FDCAN_NDAT1_ND3_Msk                       /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos          (4U)
+#define FDCAN_NDAT1_ND4_Msk          (0x1UL << FDCAN_NDAT1_ND4_Pos)            /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4              FDCAN_NDAT1_ND4_Msk                       /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos          (5U)
+#define FDCAN_NDAT1_ND5_Msk          (0x1UL << FDCAN_NDAT1_ND5_Pos)            /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5              FDCAN_NDAT1_ND5_Msk                       /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos          (6U)
+#define FDCAN_NDAT1_ND6_Msk          (0x1UL << FDCAN_NDAT1_ND6_Pos)            /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6              FDCAN_NDAT1_ND6_Msk                       /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos          (7U)
+#define FDCAN_NDAT1_ND7_Msk          (0x1UL << FDCAN_NDAT1_ND7_Pos)            /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7              FDCAN_NDAT1_ND7_Msk                       /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos          (8U)
+#define FDCAN_NDAT1_ND8_Msk          (0x1UL << FDCAN_NDAT1_ND8_Pos)            /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8              FDCAN_NDAT1_ND8_Msk                       /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos              (9U)
+#define FDCAN_NDAT1_ND9_Msk          (0x1UL << FDCAN_NDAT1_ND9_Pos)            /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9              FDCAN_NDAT1_ND9_Msk                       /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos            (10U)
+#define FDCAN_NDAT1_ND10_Msk         (0x1UL << FDCAN_NDAT1_ND10_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10             FDCAN_NDAT1_ND10_Msk                      /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos         (11U)
+#define FDCAN_NDAT1_ND11_Msk         (0x1UL << FDCAN_NDAT1_ND11_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11             FDCAN_NDAT1_ND11_Msk                      /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos         (12U)
+#define FDCAN_NDAT1_ND12_Msk         (0x1UL << FDCAN_NDAT1_ND12_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12             FDCAN_NDAT1_ND12_Msk                      /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos         (13U)
+#define FDCAN_NDAT1_ND13_Msk         (0x1UL << FDCAN_NDAT1_ND13_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13             FDCAN_NDAT1_ND13_Msk                      /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos         (14U)
+#define FDCAN_NDAT1_ND14_Msk         (0x1UL << FDCAN_NDAT1_ND14_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14             FDCAN_NDAT1_ND14_Msk                      /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos         (15U)
+#define FDCAN_NDAT1_ND15_Msk         (0x1UL << FDCAN_NDAT1_ND15_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15             FDCAN_NDAT1_ND15_Msk                      /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos         (16U)
+#define FDCAN_NDAT1_ND16_Msk         (0x1UL << FDCAN_NDAT1_ND16_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16             FDCAN_NDAT1_ND16_Msk                      /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos         (17U)
+#define FDCAN_NDAT1_ND17_Msk         (0x1UL << FDCAN_NDAT1_ND17_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17             FDCAN_NDAT1_ND17_Msk                      /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos         (18U)
+#define FDCAN_NDAT1_ND18_Msk         (0x1UL << FDCAN_NDAT1_ND18_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18             FDCAN_NDAT1_ND18_Msk                      /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos         (19U)
+#define FDCAN_NDAT1_ND19_Msk         (0x1UL << FDCAN_NDAT1_ND19_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19             FDCAN_NDAT1_ND19_Msk                      /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos         (20U)
+#define FDCAN_NDAT1_ND20_Msk         (0x1UL << FDCAN_NDAT1_ND20_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20             FDCAN_NDAT1_ND20_Msk                      /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos         (21U)
+#define FDCAN_NDAT1_ND21_Msk         (0x1UL << FDCAN_NDAT1_ND21_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21             FDCAN_NDAT1_ND21_Msk                      /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos         (22U)
+#define FDCAN_NDAT1_ND22_Msk         (0x1UL << FDCAN_NDAT1_ND22_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22             FDCAN_NDAT1_ND22_Msk                      /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos         (23U)
+#define FDCAN_NDAT1_ND23_Msk         (0x1UL << FDCAN_NDAT1_ND23_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23             FDCAN_NDAT1_ND23_Msk                      /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos         (24U)
+#define FDCAN_NDAT1_ND24_Msk         (0x1UL << FDCAN_NDAT1_ND24_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24             FDCAN_NDAT1_ND24_Msk                      /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos         (25U)
+#define FDCAN_NDAT1_ND25_Msk         (0x1UL << FDCAN_NDAT1_ND25_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25             FDCAN_NDAT1_ND25_Msk                      /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos         (26U)
+#define FDCAN_NDAT1_ND26_Msk         (0x1UL << FDCAN_NDAT1_ND26_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26             FDCAN_NDAT1_ND26_Msk                      /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos         (27U)
+#define FDCAN_NDAT1_ND27_Msk         (0x1UL << FDCAN_NDAT1_ND27_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27             FDCAN_NDAT1_ND27_Msk                      /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos         (28U)
+#define FDCAN_NDAT1_ND28_Msk         (0x1UL << FDCAN_NDAT1_ND28_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28             FDCAN_NDAT1_ND28_Msk                      /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos         (29U)
+#define FDCAN_NDAT1_ND29_Msk         (0x1UL << FDCAN_NDAT1_ND29_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29             FDCAN_NDAT1_ND29_Msk                      /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos         (30U)
+#define FDCAN_NDAT1_ND30_Msk         (0x1UL << FDCAN_NDAT1_ND30_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30             FDCAN_NDAT1_ND30_Msk                      /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos         (31U)
+#define FDCAN_NDAT1_ND31_Msk         (0x1UL << FDCAN_NDAT1_ND31_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31             FDCAN_NDAT1_ND31_Msk                      /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos         (0U)
+#define FDCAN_NDAT2_ND32_Msk         (0x1UL << FDCAN_NDAT2_ND32_Pos)           /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32             FDCAN_NDAT2_ND32_Msk                      /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos         (1U)
+#define FDCAN_NDAT2_ND33_Msk         (0x1UL << FDCAN_NDAT2_ND33_Pos)           /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33             FDCAN_NDAT2_ND33_Msk                      /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos         (2U)
+#define FDCAN_NDAT2_ND34_Msk         (0x1UL << FDCAN_NDAT2_ND34_Pos)           /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34             FDCAN_NDAT2_ND34_Msk                      /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos         (3U)
+#define FDCAN_NDAT2_ND35_Msk         (0x1UL << FDCAN_NDAT2_ND35_Pos)           /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35             FDCAN_NDAT2_ND35_Msk                      /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos         (4U)
+#define FDCAN_NDAT2_ND36_Msk         (0x1UL << FDCAN_NDAT2_ND36_Pos)           /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36             FDCAN_NDAT2_ND36_Msk                      /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos         (5U)
+#define FDCAN_NDAT2_ND37_Msk         (0x1UL << FDCAN_NDAT2_ND37_Pos)           /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37             FDCAN_NDAT2_ND37_Msk                      /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos         (6U)
+#define FDCAN_NDAT2_ND38_Msk         (0x1UL << FDCAN_NDAT2_ND38_Pos)           /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38             FDCAN_NDAT2_ND38_Msk                      /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos         (7U)
+#define FDCAN_NDAT2_ND39_Msk         (0x1UL << FDCAN_NDAT2_ND39_Pos)           /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39             FDCAN_NDAT2_ND39_Msk                      /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos         (8U)
+#define FDCAN_NDAT2_ND40_Msk         (0x1UL << FDCAN_NDAT2_ND40_Pos)           /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40             FDCAN_NDAT2_ND40_Msk                      /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos         (9U)
+#define FDCAN_NDAT2_ND41_Msk         (0x1UL << FDCAN_NDAT2_ND41_Pos)           /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41             FDCAN_NDAT2_ND41_Msk                      /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos         (10U)
+#define FDCAN_NDAT2_ND42_Msk         (0x1UL << FDCAN_NDAT2_ND42_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42             FDCAN_NDAT2_ND42_Msk                      /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos         (11U)
+#define FDCAN_NDAT2_ND43_Msk         (0x1UL << FDCAN_NDAT2_ND43_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43             FDCAN_NDAT2_ND43_Msk                      /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos         (12U)
+#define FDCAN_NDAT2_ND44_Msk         (0x1UL << FDCAN_NDAT2_ND44_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44             FDCAN_NDAT2_ND44_Msk                      /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos         (13U)
+#define FDCAN_NDAT2_ND45_Msk         (0x1UL << FDCAN_NDAT2_ND45_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45             FDCAN_NDAT2_ND45_Msk                      /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos         (14U)
+#define FDCAN_NDAT2_ND46_Msk         (0x1UL << FDCAN_NDAT2_ND46_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46             FDCAN_NDAT2_ND46_Msk                      /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos         (15U)
+#define FDCAN_NDAT2_ND47_Msk         (0x1UL << FDCAN_NDAT2_ND47_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47             FDCAN_NDAT2_ND47_Msk                      /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos         (16U)
+#define FDCAN_NDAT2_ND48_Msk         (0x1UL << FDCAN_NDAT2_ND48_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48             FDCAN_NDAT2_ND48_Msk                      /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos         (17U)
+#define FDCAN_NDAT2_ND49_Msk         (0x1UL << FDCAN_NDAT2_ND49_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49             FDCAN_NDAT2_ND49_Msk                      /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos         (18U)
+#define FDCAN_NDAT2_ND50_Msk         (0x1UL << FDCAN_NDAT2_ND50_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50             FDCAN_NDAT2_ND50_Msk                      /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos         (19U)
+#define FDCAN_NDAT2_ND51_Msk         (0x1UL << FDCAN_NDAT2_ND51_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51             FDCAN_NDAT2_ND51_Msk                      /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos         (20U)
+#define FDCAN_NDAT2_ND52_Msk         (0x1UL << FDCAN_NDAT2_ND52_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52             FDCAN_NDAT2_ND52_Msk                      /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos         (21U)
+#define FDCAN_NDAT2_ND53_Msk         (0x1UL << FDCAN_NDAT2_ND53_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53             FDCAN_NDAT2_ND53_Msk                      /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos         (22U)
+#define FDCAN_NDAT2_ND54_Msk         (0x1UL << FDCAN_NDAT2_ND54_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54             FDCAN_NDAT2_ND54_Msk                      /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos         (23U)
+#define FDCAN_NDAT2_ND55_Msk         (0x1UL << FDCAN_NDAT2_ND55_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55             FDCAN_NDAT2_ND55_Msk                      /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos         (24U)
+#define FDCAN_NDAT2_ND56_Msk         (0x1UL << FDCAN_NDAT2_ND56_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56             FDCAN_NDAT2_ND56_Msk                      /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos         (25U)
+#define FDCAN_NDAT2_ND57_Msk         (0x1UL << FDCAN_NDAT2_ND57_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57             FDCAN_NDAT2_ND57_Msk                      /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos         (26U)
+#define FDCAN_NDAT2_ND58_Msk         (0x1UL << FDCAN_NDAT2_ND58_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58             FDCAN_NDAT2_ND58_Msk                      /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos         (27U)
+#define FDCAN_NDAT2_ND59_Msk         (0x1UL << FDCAN_NDAT2_ND59_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59             FDCAN_NDAT2_ND59_Msk                      /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos         (28U)
+#define FDCAN_NDAT2_ND60_Msk         (0x1UL << FDCAN_NDAT2_ND60_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60             FDCAN_NDAT2_ND60_Msk                      /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos         (29U)
+#define FDCAN_NDAT2_ND61_Msk         (0x1UL << FDCAN_NDAT2_ND61_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61             FDCAN_NDAT2_ND61_Msk                      /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos         (30U)
+#define FDCAN_NDAT2_ND62_Msk         (0x1UL << FDCAN_NDAT2_ND62_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62             FDCAN_NDAT2_ND62_Msk                      /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos         (31U)
+#define FDCAN_NDAT2_ND63_Msk         (0x1UL << FDCAN_NDAT2_ND63_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63             FDCAN_NDAT2_ND63_Msk                      /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos         (2U)
+#define FDCAN_RXF0C_F0SA_Msk         (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA             FDCAN_RXF0C_F0SA_Msk                      /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos          (16U)
+#define FDCAN_RXF0C_F0S_Msk          (0x7FUL << FDCAN_RXF0C_F0S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S              FDCAN_RXF0C_F0S_Msk                       /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos         (24U)
+#define FDCAN_RXF0C_F0WM_Msk         (0x7FUL << FDCAN_RXF0C_F0WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM             FDCAN_RXF0C_F0WM_Msk                      /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos         (31U)
+#define FDCAN_RXF0C_F0OM_Msk         (0x1UL << FDCAN_RXF0C_F0OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM             FDCAN_RXF0C_F0OM_Msk                      /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ******************/
+#define FDCAN_RXF0S_F0FL_Pos         (0U)
+#define FDCAN_RXF0S_F0FL_Msk         (0x7FUL << FDCAN_RXF0S_F0FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL             FDCAN_RXF0S_F0FL_Msk                      /*!<Rx FIFO 0 Fill Level                     */
+#define FDCAN_RXF0S_F0GI_Pos         (8U)
+#define FDCAN_RXF0S_F0GI_Msk         (0x3FUL << FDCAN_RXF0S_F0GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI             FDCAN_RXF0S_F0GI_Msk                      /*!<Rx FIFO 0 Get Index                      */
+#define FDCAN_RXF0S_F0PI_Pos         (16U)
+#define FDCAN_RXF0S_F0PI_Msk         (0x3FUL << FDCAN_RXF0S_F0PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI             FDCAN_RXF0S_F0PI_Msk                      /*!<Rx FIFO 0 Put Index                      */
+#define FDCAN_RXF0S_F0F_Pos          (24U)
+#define FDCAN_RXF0S_F0F_Msk          (0x1UL << FDCAN_RXF0S_F0F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F              FDCAN_RXF0S_F0F_Msk                       /*!<Rx FIFO 0 Full                           */
+#define FDCAN_RXF0S_RF0L_Pos         (25U)
+#define FDCAN_RXF0S_RF0L_Msk         (0x1UL << FDCAN_RXF0S_RF0L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L             FDCAN_RXF0S_RF0L_Msk                      /*!<Rx FIFO 0 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ******************/
+#define FDCAN_RXF0A_F0AI_Pos         (0U)
+#define FDCAN_RXF0A_F0AI_Msk         (0x3FUL << FDCAN_RXF0A_F0AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI             FDCAN_RXF0A_F0AI_Msk                      /*!<Rx FIFO 0 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos          (2U)
+#define FDCAN_RXBC_RBSA_Msk          (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA              FDCAN_RXBC_RBSA_Msk                       /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ******************/
+#define FDCAN_RXF1C_F1SA_Pos         (2U)
+#define FDCAN_RXF1C_F1SA_Msk         (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA             FDCAN_RXF1C_F1SA_Msk                      /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos          (16U)
+#define FDCAN_RXF1C_F1S_Msk          (0x7FUL << FDCAN_RXF1C_F1S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S              FDCAN_RXF1C_F1S_Msk                       /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos         (24U)
+#define FDCAN_RXF1C_F1WM_Msk         (0x7FUL << FDCAN_RXF1C_F1WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM             FDCAN_RXF1C_F1WM_Msk                      /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos         (31U)
+#define FDCAN_RXF1C_F1OM_Msk         (0x1UL << FDCAN_RXF1C_F1OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM             FDCAN_RXF1C_F1OM_Msk                      /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ******************/
+#define FDCAN_RXF1S_F1FL_Pos         (0U)
+#define FDCAN_RXF1S_F1FL_Msk         (0x7FUL << FDCAN_RXF1S_F1FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL             FDCAN_RXF1S_F1FL_Msk                      /*!<Rx FIFO 1 Fill Level                     */
+#define FDCAN_RXF1S_F1GI_Pos         (8U)
+#define FDCAN_RXF1S_F1GI_Msk         (0x3FUL << FDCAN_RXF1S_F1GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI             FDCAN_RXF1S_F1GI_Msk                      /*!<Rx FIFO 1 Get Index                      */
+#define FDCAN_RXF1S_F1PI_Pos         (16U)
+#define FDCAN_RXF1S_F1PI_Msk         (0x3FUL << FDCAN_RXF1S_F1PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI             FDCAN_RXF1S_F1PI_Msk                      /*!<Rx FIFO 1 Put Index                      */
+#define FDCAN_RXF1S_F1F_Pos          (24U)
+#define FDCAN_RXF1S_F1F_Msk          (0x1UL << FDCAN_RXF1S_F1F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F              FDCAN_RXF1S_F1F_Msk                       /*!<Rx FIFO 1 Full                           */
+#define FDCAN_RXF1S_RF1L_Pos         (25U)
+#define FDCAN_RXF1S_RF1L_Msk         (0x1UL << FDCAN_RXF1S_RF1L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L             FDCAN_RXF1S_RF1L_Msk                      /*!<Rx FIFO 1 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ******************/
+#define FDCAN_RXF1A_F1AI_Pos         (0U)
+#define FDCAN_RXF1A_F1AI_Msk         (0x3FUL << FDCAN_RXF1A_F1AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI             FDCAN_RXF1A_F1AI_Msk                      /*!<Rx FIFO 1 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXESC register  ******************/
+#define FDCAN_RXESC_F0DS_Pos         (0U)
+#define FDCAN_RXESC_F0DS_Msk         (0x7UL << FDCAN_RXESC_F0DS_Pos)           /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS             FDCAN_RXESC_F0DS_Msk                      /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos         (4U)
+#define FDCAN_RXESC_F1DS_Msk         (0x7UL << FDCAN_RXESC_F1DS_Pos)           /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS             FDCAN_RXESC_F1DS_Msk                      /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos         (8U)
+#define FDCAN_RXESC_RBDS_Msk         (0x7UL << FDCAN_RXESC_RBDS_Pos)           /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS             FDCAN_RXESC_RBDS_Msk                      /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *******************/
+#define FDCAN_TXBC_TBSA_Pos          (2U)
+#define FDCAN_TXBC_TBSA_Msk          (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA              FDCAN_TXBC_TBSA_Msk                       /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos          (16U)
+#define FDCAN_TXBC_NDTB_Msk          (0x3FUL << FDCAN_TXBC_NDTB_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB              FDCAN_TXBC_NDTB_Msk                       /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos          (24U)
+#define FDCAN_TXBC_TFQS_Msk          (0x3FUL << FDCAN_TXBC_TFQS_Pos)           /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS              FDCAN_TXBC_TFQS_Msk                       /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos          (30U)
+#define FDCAN_TXBC_TFQM_Msk          (0x1UL << FDCAN_TXBC_TFQM_Pos)            /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM              FDCAN_TXBC_TFQM_Msk                       /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  ******************/
+#define FDCAN_TXFQS_TFFL_Pos         (0U)
+#define FDCAN_TXFQS_TFFL_Msk         (0x3FUL << FDCAN_TXFQS_TFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL             FDCAN_TXFQS_TFFL_Msk                      /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos         (8U)
+#define FDCAN_TXFQS_TFGI_Msk         (0x1FUL << FDCAN_TXFQS_TFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI             FDCAN_TXFQS_TFGI_Msk                      /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos        (16U)
+#define FDCAN_TXFQS_TFQPI_Msk        (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)         /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI            FDCAN_TXFQS_TFQPI_Msk                     /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos         (21U)
+#define FDCAN_TXFQS_TFQF_Msk         (0x1UL << FDCAN_TXFQS_TFQF_Pos)           /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF             FDCAN_TXFQS_TFQF_Msk                      /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  ******************/
+#define FDCAN_TXESC_TBDS_Pos         (0U)
+#define FDCAN_TXESC_TBDS_Msk         (0x7UL << FDCAN_TXESC_TBDS_Pos)           /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS             FDCAN_TXESC_TBDS_Msk                      /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  ******************/
+#define FDCAN_TXBRP_TRP_Pos          (0U)
+#define FDCAN_TXBRP_TRP_Msk          (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)     /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP              FDCAN_TXBRP_TRP_Msk                       /*!<Transmission Request Pending             */
+
+/*****************  Bit definition for FDCAN_TXBAR register  ******************/
+#define FDCAN_TXBAR_AR_Pos           (0U)
+#define FDCAN_TXBAR_AR_Msk           (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR               FDCAN_TXBAR_AR_Msk                        /*!<Add Request                              */
+
+/*****************  Bit definition for FDCAN_TXBCR register  ******************/
+#define FDCAN_TXBCR_CR_Pos           (0U)
+#define FDCAN_TXBCR_CR_Msk           (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR               FDCAN_TXBCR_CR_Msk                        /*!<Cancellation Request                     */
+
+/*****************  Bit definition for FDCAN_TXBTO register  ******************/
+#define FDCAN_TXBTO_TO_Pos           (0U)
+#define FDCAN_TXBTO_TO_Msk           (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO               FDCAN_TXBTO_TO_Msk                        /*!<Transmission Occurred                    */
+
+/*****************  Bit definition for FDCAN_TXBCF register  ******************/
+#define FDCAN_TXBCF_CF_Pos           (0U)
+#define FDCAN_TXBCF_CF_Msk           (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF               FDCAN_TXBCF_CF_Msk                        /*!<Cancellation Finished                    */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  *****************/
+#define FDCAN_TXBTIE_TIE_Pos         (0U)
+#define FDCAN_TXBTIE_TIE_Msk         (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)    /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE             FDCAN_TXBTIE_TIE_Msk                      /*!<Transmission Interrupt Enable            */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  ****************/
+#define FDCAN_TXBCIE_CFIE_Pos        (0U)
+#define FDCAN_TXBCIE_CFIE_Msk        (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)   /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE            FDCAN_TXBCIE_CFIE_Msk                     /*!<Cancellation Finished Interrupt Enable   */
+
+/*****************  Bit definition for FDCAN_TXEFC register  ******************/
+#define FDCAN_TXEFC_EFSA_Pos         (2U)
+#define FDCAN_TXEFC_EFSA_Msk         (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA             FDCAN_TXEFC_EFSA_Msk                      /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos          (16U)
+#define FDCAN_TXEFC_EFS_Msk          (0x3FUL << FDCAN_TXEFC_EFS_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS              FDCAN_TXEFC_EFS_Msk                       /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos         (24U)
+#define FDCAN_TXEFC_EFWM_Msk         (0x3FUL << FDCAN_TXEFC_EFWM_Pos)          /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM             FDCAN_TXEFC_EFWM_Msk                      /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  ******************/
+#define FDCAN_TXEFS_EFFL_Pos         (0U)
+#define FDCAN_TXEFS_EFFL_Msk         (0x3FUL << FDCAN_TXEFS_EFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL             FDCAN_TXEFS_EFFL_Msk                      /*!<Event FIFO Fill Level                    */
+#define FDCAN_TXEFS_EFGI_Pos         (8U)
+#define FDCAN_TXEFS_EFGI_Msk         (0x1FUL << FDCAN_TXEFS_EFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI             FDCAN_TXEFS_EFGI_Msk                      /*!<Event FIFO Get Index                     */
+#define FDCAN_TXEFS_EFPI_Pos         (16U)
+#define FDCAN_TXEFS_EFPI_Msk         (0x1FUL << FDCAN_TXEFS_EFPI_Pos)          /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI             FDCAN_TXEFS_EFPI_Msk                      /*!<Event FIFO Put Index                     */
+#define FDCAN_TXEFS_EFF_Pos          (24U)
+#define FDCAN_TXEFS_EFF_Msk          (0x1UL << FDCAN_TXEFS_EFF_Pos)            /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF              FDCAN_TXEFS_EFF_Msk                       /*!<Event FIFO Full                          */
+#define FDCAN_TXEFS_TEFL_Pos         (25U)
+#define FDCAN_TXEFS_TEFL_Msk         (0x1UL << FDCAN_TXEFS_TEFL_Pos)           /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL             FDCAN_TXEFS_TEFL_Msk                      /*!<Tx Event FIFO Element Lost               */
+
+/*****************  Bit definition for FDCAN_TXEFA register  ******************/
+#define FDCAN_TXEFA_EFAI_Pos         (0U)
+#define FDCAN_TXEFA_EFAI_Msk         (0x1FUL << FDCAN_TXEFA_EFAI_Pos)          /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI             FDCAN_TXEFA_EFAI_Msk                      /*!<Event FIFO Acknowledge Index             */
+
+/*****************  Bit definition for FDCAN_TTTMC register  ******************/
+#define FDCAN_TTTMC_TMSA_Pos         (2U)
+#define FDCAN_TTTMC_TMSA_Msk         (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA             FDCAN_TTTMC_TMSA_Msk                      /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos          (16U)
+#define FDCAN_TTTMC_TME_Msk          (0x7FUL << FDCAN_TTTMC_TME_Pos)           /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME              FDCAN_TTTMC_TME_Msk                       /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  ******************/
+#define FDCAN_TTRMC_RID_Pos          (0U)
+#define FDCAN_TTRMC_RID_Msk          (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)     /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID              FDCAN_TTRMC_RID_Msk                       /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos          (30U)
+#define FDCAN_TTRMC_XTD_Msk          (0x1UL << FDCAN_TTRMC_XTD_Pos)            /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD              FDCAN_TTRMC_XTD_Msk                       /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos         (31U)
+#define FDCAN_TTRMC_RMPS_Msk         (0x1UL << FDCAN_TTRMC_RMPS_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS             FDCAN_TTRMC_RMPS_Msk                      /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  ******************/
+#define FDCAN_TTOCF_OM_Pos           (0U)
+#define FDCAN_TTOCF_OM_Msk           (0x3UL << FDCAN_TTOCF_OM_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM               FDCAN_TTOCF_OM_Msk                        /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos          (3U)
+#define FDCAN_TTOCF_GEN_Msk          (0x1UL << FDCAN_TTOCF_GEN_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN              FDCAN_TTOCF_GEN_Msk                       /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos           (4U)
+#define FDCAN_TTOCF_TM_Msk           (0x1UL << FDCAN_TTOCF_TM_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM               FDCAN_TTOCF_TM_Msk                        /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos        (5U)
+#define FDCAN_TTOCF_LDSDL_Msk        (0x7UL << FDCAN_TTOCF_LDSDL_Pos)          /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL            FDCAN_TTOCF_LDSDL_Msk                     /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos         (8U)
+#define FDCAN_TTOCF_IRTO_Msk         (0x7FUL << FDCAN_TTOCF_IRTO_Pos)          /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO             FDCAN_TTOCF_IRTO_Msk                      /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos         (15U)
+#define FDCAN_TTOCF_EECS_Msk         (0x1UL << FDCAN_TTOCF_EECS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS             FDCAN_TTOCF_EECS_Msk                      /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos          (16U)
+#define FDCAN_TTOCF_AWL_Msk          (0xFFUL << FDCAN_TTOCF_AWL_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL              FDCAN_TTOCF_AWL_Msk                       /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos         (24U)
+#define FDCAN_TTOCF_EGTF_Msk         (0x1UL << FDCAN_TTOCF_EGTF_Pos)           /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF             FDCAN_TTOCF_EGTF_Msk                      /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos          (25U)
+#define FDCAN_TTOCF_ECC_Msk          (0x1UL << FDCAN_TTOCF_ECC_Pos)            /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC              FDCAN_TTOCF_ECC_Msk                       /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos         (26U)
+#define FDCAN_TTOCF_EVTP_Msk         (0x1UL << FDCAN_TTOCF_EVTP_Pos)           /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP             FDCAN_TTOCF_EVTP_Msk                      /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  ******************/
+#define FDCAN_TTMLM_CCM_Pos          (0U)
+#define FDCAN_TTMLM_CCM_Msk          (0x3FUL << FDCAN_TTMLM_CCM_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM              FDCAN_TTMLM_CCM_Msk                       /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos          (6U)
+#define FDCAN_TTMLM_CSS_Msk          (0x3UL << FDCAN_TTMLM_CSS_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS              FDCAN_TTMLM_CSS_Msk                       /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos         (8U)
+#define FDCAN_TTMLM_TXEW_Msk         (0xFUL << FDCAN_TTMLM_TXEW_Pos)           /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW             FDCAN_TTMLM_TXEW_Msk                      /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos         (16U)
+#define FDCAN_TTMLM_ENTT_Msk         (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)         /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT             FDCAN_TTMLM_ENTT_Msk                      /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  ******************/
+#define FDCAN_TURCF_NCL_Pos          (0U)
+#define FDCAN_TURCF_NCL_Msk          (0xFFFFUL << FDCAN_TURCF_NCL_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL              FDCAN_TURCF_NCL_Msk                       /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos           (16U)
+#define FDCAN_TURCF_DC_Msk           (0x3FFFUL << FDCAN_TURCF_DC_Pos)          /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC               FDCAN_TURCF_DC_Msk                        /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos          (31U)
+#define FDCAN_TURCF_ELT_Msk          (0x1UL << FDCAN_TURCF_ELT_Pos)            /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT              FDCAN_TURCF_ELT_Msk                       /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ******************/
+#define FDCAN_TTOCN_SGT_Pos          (0U)
+#define FDCAN_TTOCN_SGT_Msk          (0x1UL << FDCAN_TTOCN_SGT_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT              FDCAN_TTOCN_SGT_Msk                       /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos          (1U)
+#define FDCAN_TTOCN_ECS_Msk          (0x1UL << FDCAN_TTOCN_ECS_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS              FDCAN_TTOCN_ECS_Msk                       /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos          (2U)
+#define FDCAN_TTOCN_SWP_Msk          (0x1UL << FDCAN_TTOCN_SWP_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP              FDCAN_TTOCN_SWP_Msk                       /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos          (3U)
+#define FDCAN_TTOCN_SWS_Msk          (0x3UL << FDCAN_TTOCN_SWS_Pos)            /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS              FDCAN_TTOCN_SWS_Msk                       /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos         (5U)
+#define FDCAN_TTOCN_RTIE_Msk         (0x1UL << FDCAN_TTOCN_RTIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE             FDCAN_TTOCN_RTIE_Msk                      /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos          (6U)
+#define FDCAN_TTOCN_TMC_Msk          (0x3UL << FDCAN_TTOCN_TMC_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC              FDCAN_TTOCN_TMC_Msk                       /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos         (8U)
+#define FDCAN_TTOCN_TTIE_Msk         (0x1UL << FDCAN_TTOCN_TTIE_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE             FDCAN_TTOCN_TTIE_Msk                      /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos          (9U)
+#define FDCAN_TTOCN_GCS_Msk          (0x1UL << FDCAN_TTOCN_GCS_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS              FDCAN_TTOCN_GCS_Msk                       /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos          (10U)
+#define FDCAN_TTOCN_FGP_Msk          (0x1UL << FDCAN_TTOCN_FGP_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP              FDCAN_TTOCN_FGP_Msk                       /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos          (11U)
+#define FDCAN_TTOCN_TMG_Msk          (0x1UL << FDCAN_TTOCN_TMG_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG              FDCAN_TTOCN_TMG_Msk                       /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos          (12U)
+#define FDCAN_TTOCN_NIG_Msk          (0x1UL << FDCAN_TTOCN_NIG_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG              FDCAN_TTOCN_NIG_Msk                       /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos         (13U)
+#define FDCAN_TTOCN_ESCN_Msk         (0x1UL << FDCAN_TTOCN_ESCN_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN             FDCAN_TTOCN_ESCN_Msk                      /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos         (15U)
+#define FDCAN_TTOCN_LCKC_Msk         (0x1UL << FDCAN_TTOCN_LCKC_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC             FDCAN_TTOCN_LCKC_Msk                      /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ******************/
+#define FDCAN_TTGTP_TP_Pos           (0U)
+#define FDCAN_TTGTP_TP_Msk           (0xFFFFUL << FDCAN_TTGTP_TP_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP               FDCAN_TTGTP_TP_Msk                        /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos          (16U)
+#define FDCAN_TTGTP_CTP_Msk          (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP              FDCAN_TTGTP_CTP_Msk                       /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ******************/
+#define FDCAN_TTTMK_TM_Pos           (0U)
+#define FDCAN_TTTMK_TM_Msk           (0xFFFFUL << FDCAN_TTTMK_TM_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM               FDCAN_TTTMK_TM_Msk                        /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos         (16U)
+#define FDCAN_TTTMK_TICC_Msk         (0x7FUL << FDCAN_TTTMK_TICC_Pos)          /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC             FDCAN_TTTMK_TICC_Msk                      /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos         (31U)
+#define FDCAN_TTTMK_LCKM_Msk         (0x1UL << FDCAN_TTTMK_LCKM_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM             FDCAN_TTTMK_LCKM_Msk                      /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  *******************/
+#define FDCAN_TTIR_SBC_Pos           (0U)
+#define FDCAN_TTIR_SBC_Msk           (0x1UL << FDCAN_TTIR_SBC_Pos)             /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC               FDCAN_TTIR_SBC_Msk                        /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos           (1U)
+#define FDCAN_TTIR_SMC_Msk           (0x1UL << FDCAN_TTIR_SMC_Pos)             /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC               FDCAN_TTIR_SMC_Msk                        /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos           (2U)
+#define FDCAN_TTIR_CSM_Msk           (0x1UL << FDCAN_TTIR_CSM_Pos)             /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM               FDCAN_TTIR_CSM_Msk                        /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos           (3U)
+#define FDCAN_TTIR_SOG_Msk           (0x1UL << FDCAN_TTIR_SOG_Pos)             /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG               FDCAN_TTIR_SOG_Msk                        /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos          (4U)
+#define FDCAN_TTIR_RTMI_Msk          (0x1UL << FDCAN_TTIR_RTMI_Pos)            /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI              FDCAN_TTIR_RTMI_Msk                       /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos          (5U)
+#define FDCAN_TTIR_TTMI_Msk          (0x1UL << FDCAN_TTIR_TTMI_Pos)            /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI              FDCAN_TTIR_TTMI_Msk                       /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos           (6U)
+#define FDCAN_TTIR_SWE_Msk           (0x1UL << FDCAN_TTIR_SWE_Pos)             /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE               FDCAN_TTIR_SWE_Msk                        /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos           (7U)
+#define FDCAN_TTIR_GTW_Msk           (0x1UL << FDCAN_TTIR_GTW_Pos)             /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW               FDCAN_TTIR_GTW_Msk                        /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos           (8U)
+#define FDCAN_TTIR_GTD_Msk           (0x1UL << FDCAN_TTIR_GTD_Pos)             /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD               FDCAN_TTIR_GTD_Msk                        /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos           (9U)
+#define FDCAN_TTIR_GTE_Msk           (0x1UL << FDCAN_TTIR_GTE_Pos)             /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE               FDCAN_TTIR_GTE_Msk                        /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos           (10U)
+#define FDCAN_TTIR_TXU_Msk           (0x1UL << FDCAN_TTIR_TXU_Pos)             /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU               FDCAN_TTIR_TXU_Msk                        /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos           (11U)
+#define FDCAN_TTIR_TXO_Msk           (0x1UL << FDCAN_TTIR_TXO_Pos)             /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO               FDCAN_TTIR_TXO_Msk                        /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos           (12U)
+#define FDCAN_TTIR_SE1_Msk           (0x1UL << FDCAN_TTIR_SE1_Pos)             /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1               FDCAN_TTIR_SE1_Msk                        /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos           (13U)
+#define FDCAN_TTIR_SE2_Msk           (0x1UL << FDCAN_TTIR_SE2_Pos)             /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2               FDCAN_TTIR_SE2_Msk                        /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos           (14U)
+#define FDCAN_TTIR_ELC_Msk           (0x1UL << FDCAN_TTIR_ELC_Pos)             /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC               FDCAN_TTIR_ELC_Msk                        /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos           (15U)
+#define FDCAN_TTIR_IWT_Msk           (0x1UL << FDCAN_TTIR_IWT_Pos)             /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT               FDCAN_TTIR_IWT_Msk                        /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos            (16U)
+#define FDCAN_TTIR_WT_Msk            (0x1UL << FDCAN_TTIR_WT_Pos)              /*!< 0x00010000 */
+#define FDCAN_TTIR_WT                FDCAN_TTIR_WT_Msk                         /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos            (17U)
+#define FDCAN_TTIR_AW_Msk            (0x1UL << FDCAN_TTIR_AW_Pos)              /*!< 0x00020000 */
+#define FDCAN_TTIR_AW                FDCAN_TTIR_AW_Msk                         /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos           (18U)
+#define FDCAN_TTIR_CER_Msk           (0x1UL << FDCAN_TTIR_CER_Pos)             /*!< 0x00040000 */
+#define FDCAN_TTIR_CER               FDCAN_TTIR_CER_Msk                        /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  *******************/
+#define FDCAN_TTIE_SBCE_Pos          (0U)
+#define FDCAN_TTIE_SBCE_Msk          (0x1UL << FDCAN_TTIE_SBCE_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE              FDCAN_TTIE_SBCE_Msk                       /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos          (1U)
+#define FDCAN_TTIE_SMCE_Msk          (0x1UL << FDCAN_TTIE_SMCE_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE              FDCAN_TTIE_SMCE_Msk                       /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos          (2U)
+#define FDCAN_TTIE_CSME_Msk          (0x1UL << FDCAN_TTIE_CSME_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME              FDCAN_TTIE_CSME_Msk                       /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos          (3U)
+#define FDCAN_TTIE_SOGE_Msk          (0x1UL << FDCAN_TTIE_SOGE_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE              FDCAN_TTIE_SOGE_Msk                       /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos         (4U)
+#define FDCAN_TTIE_RTMIE_Msk         (0x1UL << FDCAN_TTIE_RTMIE_Pos)           /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE             FDCAN_TTIE_RTMIE_Msk                      /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos         (5U)
+#define FDCAN_TTIE_TTMIE_Msk         (0x1UL << FDCAN_TTIE_TTMIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE             FDCAN_TTIE_TTMIE_Msk                      /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos          (6U)
+#define FDCAN_TTIE_SWEE_Msk          (0x1UL << FDCAN_TTIE_SWEE_Pos)            /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE              FDCAN_TTIE_SWEE_Msk                       /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos          (7U)
+#define FDCAN_TTIE_GTWE_Msk          (0x1UL << FDCAN_TTIE_GTWE_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE              FDCAN_TTIE_GTWE_Msk                       /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos          (8U)
+#define FDCAN_TTIE_GTDE_Msk          (0x1UL << FDCAN_TTIE_GTDE_Pos)            /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE              FDCAN_TTIE_GTDE_Msk                       /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos          (9U)
+#define FDCAN_TTIE_GTEE_Msk          (0x1UL << FDCAN_TTIE_GTEE_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE              FDCAN_TTIE_GTEE_Msk                       /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos          (10U)
+#define FDCAN_TTIE_TXUE_Msk          (0x1UL << FDCAN_TTIE_TXUE_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE              FDCAN_TTIE_TXUE_Msk                       /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos          (11U)
+#define FDCAN_TTIE_TXOE_Msk          (0x1UL << FDCAN_TTIE_TXOE_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE              FDCAN_TTIE_TXOE_Msk                       /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos          (12U)
+#define FDCAN_TTIE_SE1E_Msk          (0x1UL << FDCAN_TTIE_SE1E_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E              FDCAN_TTIE_SE1E_Msk                       /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos          (13U)
+#define FDCAN_TTIE_SE2E_Msk          (0x1UL << FDCAN_TTIE_SE2E_Pos)            /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E              FDCAN_TTIE_SE2E_Msk                       /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos          (14U)
+#define FDCAN_TTIE_ELCE_Msk          (0x1UL << FDCAN_TTIE_ELCE_Pos)            /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE              FDCAN_TTIE_ELCE_Msk                       /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos          (15U)
+#define FDCAN_TTIE_IWTE_Msk          (0x1UL << FDCAN_TTIE_IWTE_Pos)            /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE              FDCAN_TTIE_IWTE_Msk                       /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos           (16U)
+#define FDCAN_TTIE_WTE_Msk           (0x1UL << FDCAN_TTIE_WTE_Pos)             /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE               FDCAN_TTIE_WTE_Msk                        /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos           (17U)
+#define FDCAN_TTIE_AWE_Msk           (0x1UL << FDCAN_TTIE_AWE_Pos)             /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE               FDCAN_TTIE_AWE_Msk                        /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos          (18U)
+#define FDCAN_TTIE_CERE_Msk          (0x1UL << FDCAN_TTIE_CERE_Pos)            /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE              FDCAN_TTIE_CERE_Msk                       /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ******************/
+#define FDCAN_TTILS_SBCS_Pos         (0U)
+#define FDCAN_TTILS_SBCS_Msk         (0x1UL << FDCAN_TTILS_SBCS_Pos)           /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS             FDCAN_TTILS_SBCS_Msk                      /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos         (1U)
+#define FDCAN_TTILS_SMCS_Msk         (0x1UL << FDCAN_TTILS_SMCS_Pos)           /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS             FDCAN_TTILS_SMCS_Msk                      /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos         (2U)
+#define FDCAN_TTILS_CSMS_Msk         (0x1UL << FDCAN_TTILS_CSMS_Pos)           /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS             FDCAN_TTILS_CSMS_Msk                      /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos         (3U)
+#define FDCAN_TTILS_SOGS_Msk         (0x1UL << FDCAN_TTILS_SOGS_Pos)           /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS             FDCAN_TTILS_SOGS_Msk                      /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos        (4U)
+#define FDCAN_TTILS_RTMIS_Msk        (0x1UL << FDCAN_TTILS_RTMIS_Pos)          /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS            FDCAN_TTILS_RTMIS_Msk                     /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos        (5U)
+#define FDCAN_TTILS_TTMIS_Msk        (0x1UL << FDCAN_TTILS_TTMIS_Pos)          /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS            FDCAN_TTILS_TTMIS_Msk                     /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos         (6U)
+#define FDCAN_TTILS_SWES_Msk         (0x1UL << FDCAN_TTILS_SWES_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES             FDCAN_TTILS_SWES_Msk                      /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos         (7U)
+#define FDCAN_TTILS_GTWS_Msk         (0x1UL << FDCAN_TTILS_GTWS_Pos)           /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS             FDCAN_TTILS_GTWS_Msk                      /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos         (8U)
+#define FDCAN_TTILS_GTDS_Msk         (0x1UL << FDCAN_TTILS_GTDS_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS             FDCAN_TTILS_GTDS_Msk                      /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos         (9U)
+#define FDCAN_TTILS_GTES_Msk         (0x1UL << FDCAN_TTILS_GTES_Pos)           /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES             FDCAN_TTILS_GTES_Msk                      /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos         (10U)
+#define FDCAN_TTILS_TXUS_Msk         (0x1UL << FDCAN_TTILS_TXUS_Pos)           /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS             FDCAN_TTILS_TXUS_Msk                      /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos         (11U)
+#define FDCAN_TTILS_TXOS_Msk         (0x1UL << FDCAN_TTILS_TXOS_Pos)           /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS             FDCAN_TTILS_TXOS_Msk                      /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos         (12U)
+#define FDCAN_TTILS_SE1S_Msk         (0x1UL << FDCAN_TTILS_SE1S_Pos)           /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S             FDCAN_TTILS_SE1S_Msk                      /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos         (13U)
+#define FDCAN_TTILS_SE2S_Msk         (0x1UL << FDCAN_TTILS_SE2S_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S             FDCAN_TTILS_SE2S_Msk                      /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos         (14U)
+#define FDCAN_TTILS_ELCS_Msk         (0x1UL << FDCAN_TTILS_ELCS_Pos)           /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS             FDCAN_TTILS_ELCS_Msk                      /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos         (15U)
+#define FDCAN_TTILS_IWTS_Msk         (0x1UL << FDCAN_TTILS_IWTS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS             FDCAN_TTILS_IWTS_Msk                      /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos          (16U)
+#define FDCAN_TTILS_WTS_Msk          (0x1UL << FDCAN_TTILS_WTS_Pos)            /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS              FDCAN_TTILS_WTS_Msk                       /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos          (17U)
+#define FDCAN_TTILS_AWS_Msk          (0x1UL << FDCAN_TTILS_AWS_Pos)            /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS              FDCAN_TTILS_AWS_Msk                       /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos         (18U)
+#define FDCAN_TTILS_CERS_Msk         (0x1UL << FDCAN_TTILS_CERS_Pos)           /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS             FDCAN_TTILS_CERS_Msk                      /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ******************/
+#define FDCAN_TTOST_EL_Pos           (0U)
+#define FDCAN_TTOST_EL_Msk           (0x3UL << FDCAN_TTOST_EL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOST_EL               FDCAN_TTOST_EL_Msk                        /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos           (2U)
+#define FDCAN_TTOST_MS_Msk           (0x3UL << FDCAN_TTOST_MS_Pos)             /*!< 0x0000000C */
+#define FDCAN_TTOST_MS               FDCAN_TTOST_MS_Msk                        /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos          (4U)
+#define FDCAN_TTOST_SYS_Msk          (0x3UL << FDCAN_TTOST_SYS_Pos)            /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS              FDCAN_TTOST_SYS_Msk                       /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos         (6U)
+#define FDCAN_TTOST_QGTP_Msk         (0x1UL << FDCAN_TTOST_QGTP_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP             FDCAN_TTOST_QGTP_Msk                      /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos          (7U)
+#define FDCAN_TTOST_QCS_Msk          (0x1UL << FDCAN_TTOST_QCS_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS              FDCAN_TTOST_QCS_Msk                       /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos          (8U)
+#define FDCAN_TTOST_RTO_Msk          (0xFFUL << FDCAN_TTOST_RTO_Pos)           /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO              FDCAN_TTOST_RTO_Msk                       /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos         (22U)
+#define FDCAN_TTOST_WGTD_Msk         (0x1UL << FDCAN_TTOST_WGTD_Pos)           /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD             FDCAN_TTOST_WGTD_Msk                      /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos          (23U)
+#define FDCAN_TTOST_GFI_Msk          (0x1UL << FDCAN_TTOST_GFI_Pos)            /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI              FDCAN_TTOST_GFI_Msk                       /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos          (24U)
+#define FDCAN_TTOST_TMP_Msk          (0x7UL << FDCAN_TTOST_TMP_Pos)            /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP              FDCAN_TTOST_TMP_Msk                       /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos          (27U)
+#define FDCAN_TTOST_GSI_Msk          (0x1UL << FDCAN_TTOST_GSI_Pos)            /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI              FDCAN_TTOST_GSI_Msk                       /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos          (28U)
+#define FDCAN_TTOST_WFE_Msk          (0x1UL << FDCAN_TTOST_WFE_Pos)            /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE              FDCAN_TTOST_WFE_Msk                       /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos          (29U)
+#define FDCAN_TTOST_AWE_Msk          (0x1UL << FDCAN_TTOST_AWE_Pos)            /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE              FDCAN_TTOST_AWE_Msk                       /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos         (30U)
+#define FDCAN_TTOST_WECS_Msk         (0x1UL << FDCAN_TTOST_WECS_Pos)           /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS             FDCAN_TTOST_WECS_Msk                      /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos          (31U)
+#define FDCAN_TTOST_SPL_Msk          (0x1UL << FDCAN_TTOST_SPL_Pos)            /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL              FDCAN_TTOST_SPL_Msk                       /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ******************/
+#define FDCAN_TURNA_NAV_Pos          (0U)
+#define FDCAN_TURNA_NAV_Msk          (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)        /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV              FDCAN_TURNA_NAV_Msk                       /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ******************/
+#define FDCAN_TTLGT_LT_Pos           (0U)
+#define FDCAN_TTLGT_LT_Msk           (0xFFFFUL << FDCAN_TTLGT_LT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT               FDCAN_TTLGT_LT_Msk                        /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos           (16U)
+#define FDCAN_TTLGT_GT_Msk           (0xFFFFUL << FDCAN_TTLGT_GT_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT               FDCAN_TTLGT_GT_Msk                        /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ******************/
+#define FDCAN_TTCTC_CT_Pos           (0U)
+#define FDCAN_TTCTC_CT_Msk           (0xFFFFUL << FDCAN_TTCTC_CT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT               FDCAN_TTCTC_CT_Msk                        /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos           (16U)
+#define FDCAN_TTCTC_CC_Msk           (0x3FUL << FDCAN_TTCTC_CC_Pos)            /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC               FDCAN_TTCTC_CC_Msk                        /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ******************/
+#define FDCAN_TTCPT_CCV_Pos          (0U)
+#define FDCAN_TTCPT_CCV_Msk          (0x3FUL << FDCAN_TTCPT_CCV_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV              FDCAN_TTCPT_CCV_Msk                       /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos          (16U)
+#define FDCAN_TTCPT_SWV_Msk          (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV              FDCAN_TTCPT_SWV_Msk                       /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ******************/
+#define FDCAN_TTCSM_CSM_Pos          (0U)
+#define FDCAN_TTCSM_CSM_Msk          (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM              FDCAN_TTCSM_CSM_Msk                       /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *******************/
+#define FDCAN_TTTS_SWTSEL_Pos        (0U)
+#define FDCAN_TTTS_SWTSEL_Msk        (0x3UL << FDCAN_TTTS_SWTSEL_Pos)          /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL            FDCAN_TTTS_SWTSEL_Msk                     /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos        (4U)
+#define FDCAN_TTTS_EVTSEL_Msk        (0x3UL << FDCAN_TTTS_EVTSEL_Pos)          /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL            FDCAN_TTTS_EVTSEL_Msk                     /*!<Event trigger input selection            */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FDCANCCU (Clock Calibration unit)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ****************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ****************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  ***************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ****************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *****************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *****************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  **********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!< Memory bank enable bit */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!< Address/data multiplexing enable bit */
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!< Memory type */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!< Memory data bus width */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!< Flash access enable */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!< Burst enable bit */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!< Wait signal polarity bit */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!< Wait timing configuration */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!< Write enable bit */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!< Wait enable bit */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!< Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!< Wait signal during asynchronous transfers */
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!< CRAM page size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!< Write burst enable */
+#define FMC_BCRx_CSCOUNT_Pos       (20U)
+#define FMC_BCRx_CSCOUNT_Msk       (0x3UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00300000 */
+#define FMC_BCRx_CSCOUNT           FMC_BCRx_CSCOUNT_Msk                        /*!< Chip Select (CS) counter */
+#define FMC_BCRx_CSCOUNT_0         (0x1UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00100000 */
+#define FMC_BCRx_CSCOUNT_1         (0x2UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00200000 */
+#define FMC_BCRx_NBLSET_Pos        (22U)
+#define FMC_BCRx_NBLSET_Msk        (0x3UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00C00000 */
+#define FMC_BCRx_NBLSET            FMC_BCRx_NBLSET_Msk                         /*!< Byte lane (NBL) setup */
+#define FMC_BCRx_NBLSET_0          (0x1UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00400000 */
+#define FMC_BCRx_NBLSET_1          (0x2UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00800000 */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  **********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!< Address setup phase duration */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!< Address-hold phase duration */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!< Data-phase duration */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!< Bus turnaround phase duration */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!< Clock divide ratio */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!< Data latency for synchronous memory */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!< Access mode */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+#define FMC_BTRx_DATAHLD_Pos       (30U)
+#define FMC_BTRx_DATAHLD_Msk       (0x3UL << FMC_BTRx_DATAHLD_Pos)              /*!< 0xC0000000 */
+#define FMC_BTRx_DATAHLD           FMC_BTRx_DATAHLD_Msk                        /*!< Data Hold phase duration */
+#define FMC_BTRx_DATAHLD_0         (0x1UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x40000000 */
+#define FMC_BTRx_DATAHLD_1         (0x2UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_CFGR register  *****************/
+#define FMC_CFGR_CLKDIV_Pos        (16U)
+#define FMC_CFGR_CLKDIV_Msk        (0xFUL << FMC_CFGR_CLKDIV_Pos)               /*!< 0x000F0000 */
+#define FMC_CFGR_CLKDIV            FMC_CFGR_CLKDIV_Msk                         /*!< Clock divide ratio (for FMC_CLK signal) */
+#define FMC_CFGR_CLKDIV_0          (0x1UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00010000 */
+#define FMC_CFGR_CLKDIV_1          (0x2UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00020000 */
+#define FMC_CFGR_CLKDIV_2          (0x4UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00040000 */
+#define FMC_CFGR_CLKDIV_3          (0x8UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00080000 */
+#define FMC_CFGR_CCLKEN_Pos        (20U)
+#define FMC_CFGR_CCLKEN_Msk        (0x1UL << FMC_CFGR_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_CFGR_CCLKEN            FMC_CFGR_CCLKEN_Msk                         /*!< Continuous clock enable */
+#define FMC_CFGR_BMAP_Pos          (24U)
+#define FMC_CFGR_BMAP_Msk          (0x3UL << FMC_CFGR_BMAP_Pos)                 /*!< 0x03000000 */
+#define FMC_CFGR_BMAP              FMC_CFGR_BMAP_Msk                           /*!< FMC memory region mapping */
+#define FMC_CFGR_BMAP_0            (0x1UL << FMC_CFGR_BMAP_Pos)                /*!< 0x01000000 */
+#define FMC_CFGR_BMAP_1            (0x2UL << FMC_CFGR_BMAP_Pos)                /*!< 0x02000000 */
+#define FMC_CFGR_FMCEN_Pos         (31U)
+#define FMC_CFGR_FMCEN_Msk         (0x1UL << FMC_CFGR_FMCEN_Pos)                /*!< 0x80000000 */
+#define FMC_CFGR_FMCEN             FMC_CFGR_FMCEN_Msk                          /*!< FMC controller enable */
+
+/******************  Bit definition for FMC_PCR register  *********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!< Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!< NAND Flash memory bank enable bit */
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!< Data bus width */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!< ECC computation logic enable bit */
+#define FMC_PCR_ECCALG_Pos         (8U)
+#define FMC_PCR_ECCALG_Msk         (0x1UL << FMC_PCR_ECCALG_Pos)               /*!< 0x00000100 */
+#define FMC_PCR_ECCALG             FMC_PCR_ECCALG_Msk                          /*!< ECC algorithm */
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!< CLE to RE delay */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!< ALE to RE delay */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
+#define FMC_PCR_ECCSS_Pos          (17U)
+#define FMC_PCR_ECCSS_Msk          (0x7UL << FMC_PCR_ECCSS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCSS              FMC_PCR_ECCSS_Msk                           /*!< ECC page size */
+#define FMC_PCR_ECCSS_0            (0x1UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00020000 */
+#define FMC_PCR_ECCSS_1            (0x2UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00040000 */
+#define FMC_PCR_ECCSS_2            (0x4UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00080000 */
+#define FMC_PCR_BCHECC_Pos         (24U)
+#define FMC_PCR_BCHECC_Msk         (0x1UL << FMC_PCR_BCHECC_Pos)                /*!< 0x01000000 */
+#define FMC_PCR_BCHECC             FMC_PCR_BCHECC_Msk                          /*!< BCH error correction capability */
+#define FMC_PCR_WEN_Pos            (25U)
+#define FMC_PCR_WEN_Msk            (0x1UL << FMC_PCR_WEN_Pos)                   /*!< 0x02000000 */
+#define FMC_PCR_WEN                FMC_PCR_WEN_Msk                             /*!< Write enable */
+
+/******************  Bit definition for FMC_SR register  ******************/
+#define FMC_SR_ISOST_Pos           (0U)
+#define FMC_SR_ISOST_Msk           (0x3UL << FMC_SR_ISOST_Pos)                  /*!< 0x00000003 */
+#define FMC_SR_ISOST               FMC_SR_ISOST_Msk                            /*!< FMC isolation state with respect to the AXI interface */
+#define FMC_SR_PEF_Pos             (4U)
+#define FMC_SR_PEF_Msk             (0x1UL << FMC_SR_PEF_Pos)                    /*!< 0x00000010 */
+#define FMC_SR_PEF                 FMC_SR_PEF_Msk                              /*!< Pipe Empty Flag */
+#define FMC_SR_NWRF_Pos            (6U)
+#define FMC_SR_NWRF_Msk            (0x1UL << FMC_SR_NWRF_Pos)                   /*!< 0x00000040 */
+#define FMC_SR_NWRF                FMC_SR_NWRF_Msk                             /*!< NAND write request flag */
+
+/******************  Bit definition for FMC_PMEM register  ********************/
+#define FMC_PMEM_MEMSET_Pos        (0U)
+#define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!< Common memory setup time */
+#define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+#define FMC_PMEM_MEMWAIT_Pos       (8U)
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!< Common memory wait time */
+#define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PMEM_MEMHOLD_Pos       (16U)
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!< Common memory hold time */
+#define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PMEM_MEMHIZ_Pos        (24U)
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!< Common memory databus Hi-Z time */
+#define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ********************/
+#define FMC_PATT_ATTSET_Pos        (0U)
+#define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!< Attribute memory setup time */
+#define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+#define FMC_PATT_ATTWAIT_Pos       (8U)
+#define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!< Attribute memory wait time */
+#define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PATT_ATTHOLD_Pos       (16U)
+#define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!< Attribute memory hold time */
+#define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PATT_ATTHIZ_Pos        (24U)
+#define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!< Attribute memory data bus Hi-Z time */
+#define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_HPR register  ******************/
+#define FMC_HPR_HPR_Pos            (0U)
+#define FMC_HPR_HPR_Msk            (0xFFFFFFFFUL << FMC_HPR_HPR_Pos)            /*!< 0xFFFFFFFF */
+#define FMC_HPR_HPR                FMC_HPR_HPR_Msk                             /*!< Hamming parity result */
+
+/****************  Bit definition for FMC_HECCR register  *****************/
+#define FMC_HECCR_HECC_Pos         (0U)
+#define FMC_HECCR_HECC_Msk         (0xFFFFFFFFUL << FMC_HECCR_HECC_Pos)         /*!< 0xFFFFFFFF */
+#define FMC_HECCR_HECC             FMC_HECCR_HECC_Msk                          /*!< ECC result */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!< Address setup phase duration */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!< Address-hold phase duration */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!< Data-phase duration */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!< Bus turnaround phase duration */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!< Access mode */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
+#define FMC_BWTRx_DATAHLD_Pos      (30U)
+#define FMC_BWTRx_DATAHLD_Msk      (0x3UL << FMC_BWTRx_DATAHLD_Pos)             /*!< 0xC0000000 */
+#define FMC_BWTRx_DATAHLD          FMC_BWTRx_DATAHLD_Msk                       /*!< Data Hold phase duration */
+#define FMC_BWTRx_DATAHLD_0        (0x1UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x40000000 */
+#define FMC_BWTRx_DATAHLD_1        (0x2UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!< Number of column address bits */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000002 */
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!< Number of row address bits */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000008 */
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!< Memory data bus width */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000020 */
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!< Number of internal banks */
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!< CAS latency */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!< Write protection */
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!< SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000800 */
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!< Read pipe */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00004000 */
+#define FMC_SDCRx_SDEN_Pos         (16U)
+#define FMC_SDCRx_SDEN_Msk         (0x1UL << FMC_SDCRx_SDEN_Pos)               /*!< 0x00010000 */
+#define FMC_SDCRx_SDEN             FMC_SDCRx_SDEN_Msk                          /*!< SDRAM device enable */
+#define FMC_SDCRx_SDINIT_Pos       (17U)
+#define FMC_SDCRx_SDINIT_Msk       (0x1UL << FMC_SDCRx_SDINIT_Pos)             /*!< 0x00020000 */
+#define FMC_SDCRx_SDINIT           FMC_SDCRx_SDINIT_Msk                        /*!< SDRAM device initialization */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  **************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!< Load mode register to active */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000008 */
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<Exit self-refresh delay */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000080 */
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!< Self refresh time */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000800 */
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!< Row cycle delay */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00004000 */
+#define FMC_SDTRx_TRC_3            (0x8UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00008000 */
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!< Recovery delay */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00040000 */
+#define FMC_SDTRx_TWR_3            (0x8UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00080000 */
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!< Row precharge delay */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00400000 */
+#define FMC_SDTRx_TRP_3            (0x8UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00800000 */
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!< Row to column delay */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x04000000 */
+#define FMC_SDTRx_TRCD_3           (0x8UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x08000000 */
+
+/******************  Bit definition for FMC_SDCMR register  *******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!< Command mode */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
+#define FMC_SDCMR_DS2_Pos          (3U)
+#define FMC_SDCMR_DS2_Msk          (0x1UL << FMC_SDCMR_DS2_Pos)                /*!< 0x00000008 */
+#define FMC_SDCMR_DS2              FMC_SDCMR_DS2_Msk                           /*!< Command targeting SDRAM device 2 */
+#define FMC_SDCMR_DS1_Pos          (4U)
+#define FMC_SDCMR_DS1_Msk          (0x1UL << FMC_SDCMR_DS1_Pos)                /*!< 0x00000010 */
+#define FMC_SDCMR_DS1              FMC_SDCMR_DS1_Msk                           /*!< Command targeting SDRAM device 1 */
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!< Number of auto-refresh */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x3FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x007FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!< Mode register definition */
+
+/******************  Bit definition for FMC_SDRTR register  *******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!< Clear refresh error flag */
+#define FMC_SDRTR_RFSCNT_Pos       (1U)
+#define FMC_SDRTR_RFSCNT_Msk       (0x1FFFUL << FMC_SDRTR_RFSCNT_Pos)          /*!< 0x00003FFE */
+#define FMC_SDRTR_RFSCNT           FMC_SDRTR_RFSCNT_Msk                        /*!< Refresh timer count */
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!< RES interrupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ********************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!< Refresh error flag */
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!< Status mode for bank 1 */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!< Status mode for bank 2 */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
+#define FMC_SDSR_CMDOK_Pos         (15U)
+#define FMC_SDSR_CMDOK_Msk         (0x1UL << FMC_SDSR_CMDOK_Pos)               /*!< 0x00004000 */
+#define FMC_SDSR_CMDOK             FMC_SDSR_CMDOK_Msk                          /*!< Previous command status */
+
+/*******************  Bit definition for FMC_IER register  ********************/
+#define FMC_IER_IREE_Pos              (0U)
+#define FMC_IER_IREE_Msk              (0x1UL << FMC_IER_IREE_Pos)               /*!< 0x00000001 */
+#define FMC_IER_IREE                  FMC_IER_IREE_Msk                         /*!< Interrupt rising edge detection enable bit */
+#define FMC_IER_IHLE_Pos              (1U)
+#define FMC_IER_IHLE_Msk              (0x1UL << FMC_IER_IHLE_Pos)               /*!< 0x00000002 */
+#define FMC_IER_IHLE                  FMC_IER_IHLE_Msk                         /*!< Interrupt high-level detection enable bit */
+#define FMC_IER_IFEE_Pos              (2U)
+#define FMC_IER_IFEE_Msk              (0x1UL << FMC_IER_IFEE_Pos)               /*!< 0x00000004 */
+#define FMC_IER_IFEE                  FMC_IER_IFEE_Msk                         /*!< Interrupt falling edge detection enable bit */
+
+/*******************  Bit definition for FMC_ISR register  ********************/
+#define FMC_ISR_IREF_Pos              (0U)
+#define FMC_ISR_IREF_Msk              (0x1UL << FMC_ISR_IREF_Pos)               /*!< 0x00000001 */
+#define FMC_ISR_IREF                  FMC_ISR_IREF_Msk                         /*!< Interrupt rising edge flag */
+#define FMC_ISR_IHLF_Pos              (1U)
+#define FMC_ISR_IHLF_Msk              (0x1UL << FMC_ISR_IHLF_Pos)               /*!< 0x00000002 */
+#define FMC_ISR_IHLF                  FMC_ISR_IHLF_Msk                         /*!< Interrupt high-level flag */
+#define FMC_ISR_IFEF_Pos              (2U)
+#define FMC_ISR_IFEF_Msk              (0x1UL << FMC_ISR_IFEF_Pos)               /*!< 0x00000004 */
+#define FMC_ISR_IFEF                  FMC_ISR_IFEF_Msk                         /*!< Interrupt falling edge flag */
+
+/*******************  Bit definition for FMC_ICR register  ********************/
+#define FMC_ICR_CIREF_Pos             (0U)
+#define FMC_ICR_CIREF_Msk             (0x1UL << FMC_ICR_CIREF_Pos)              /*!< 0x00000001 */
+#define FMC_ICR_CIREF                 FMC_ICR_CIREF_Msk                        /*!< Clear Interrupt rising edge flag */
+#define FMC_ICR_CIHLF_Pos             (1U)
+#define FMC_ICR_CIHLF_Msk             (0x1UL << FMC_ICR_CIHLF_Pos)              /*!< 0x00000002 */
+#define FMC_ICR_CIHLF                 FMC_ICR_CIHLF_Msk                        /*!< Clear Interrupt high-level flag */
+#define FMC_ICR_CIFEF_Pos             (2U)
+#define FMC_ICR_CIFEF_Msk             (0x1UL << FMC_ICR_CIFEF_Pos)              /*!< 0x00000004 */
+#define FMC_ICR_CIFEF                 FMC_ICR_CIFEF_Msk                        /*!< Clear Interrupt falling edge flag */
+
+/****************  Bit definition for FMC_CSQCR register  *****************/
+#define FMC_CSQCR_CSQSTART_Pos        (0U)
+#define FMC_CSQCR_CSQSTART_Msk        (0x1UL << FMC_CSQCR_CSQSTART_Pos)         /*!< 0x00000001 */
+#define FMC_CSQCR_CSQSTART            FMC_CSQCR_CSQSTART_Msk                   /*!< Command Sequencer Enable */
+
+/***************  Bit definition for FMC_CSQCFGR1 register  ***************/
+#define FMC_CSQCFGR1_CMD2EN_Pos       (1U)
+#define FMC_CSQCFGR1_CMD2EN_Msk       (0x1UL << FMC_CSQCFGR1_CMD2EN_Pos)        /*!< 0x00000002 */
+#define FMC_CSQCFGR1_CMD2EN           FMC_CSQCFGR1_CMD2EN_Msk                  /*!< Command cycle 2 Enable */
+#define FMC_CSQCFGR1_DMADEN_Pos       (2U)
+#define FMC_CSQCFGR1_DMADEN_Msk       (0x1UL << FMC_CSQCFGR1_DMADEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR1_DMADEN           FMC_CSQCFGR1_DMADEN_Msk                  /*!< Command sequencer DMA request data enable */
+#define FMC_CSQCFGR1_ACYNBR_Pos       (4U)
+#define FMC_CSQCFGR1_ACYNBR_Msk       (0x7UL << FMC_CSQCFGR1_ACYNBR_Pos)        /*!< 0x00000070 */
+#define FMC_CSQCFGR1_ACYNBR           FMC_CSQCFGR1_ACYNBR_Msk                  /*!< Address Cycle number */
+#define FMC_CSQCFGR1_CMD1_Pos         (8U)
+#define FMC_CSQCFGR1_CMD1_Msk         (0xFFUL << FMC_CSQCFGR1_CMD1_Pos)         /*!< 0x0000FF00 */
+#define FMC_CSQCFGR1_CMD1             FMC_CSQCFGR1_CMD1_Msk                    /*!< Command 1 sequencer */
+#define FMC_CSQCFGR1_CMD2_Pos         (16U)
+#define FMC_CSQCFGR1_CMD2_Msk         (0xFFUL << FMC_CSQCFGR1_CMD2_Pos)         /*!< 0x00FF0000 */
+#define FMC_CSQCFGR1_CMD2             FMC_CSQCFGR1_CMD2_Msk                    /*!< Command 2 sequencer */
+#define FMC_CSQCFGR1_CMD1T_Pos        (24U)
+#define FMC_CSQCFGR1_CMD1T_Msk        (0x1UL << FMC_CSQCFGR1_CMD1T_Pos)         /*!< 0x01000000 */
+#define FMC_CSQCFGR1_CMD1T            FMC_CSQCFGR1_CMD1T_Msk                   /*!< Command 1 Sequencer timings */
+#define FMC_CSQCFGR1_CMD2T_Pos        (25U)
+#define FMC_CSQCFGR1_CMD2T_Msk        (0x1UL << FMC_CSQCFGR1_CMD2T_Pos)         /*!< 0x02000000 */
+#define FMC_CSQCFGR1_CMD2T            FMC_CSQCFGR1_CMD2T_Msk                   /*!< Command 2 Sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR2 register  ***************/
+#define FMC_CSQCFGR2_SQSDTEN_Pos      (0U)
+#define FMC_CSQCFGR2_SQSDTEN_Msk      (0x1UL << FMC_CSQCFGR2_SQSDTEN_Pos)       /*!< 0x00000001 */
+#define FMC_CSQCFGR2_SQSDTEN          FMC_CSQCFGR2_SQSDTEN_Msk                 /*!< Sequencer spare data transfer enable */
+#define FMC_CSQCFGR2_RCMD2EN_Pos      (1U)
+#define FMC_CSQCFGR2_RCMD2EN_Msk      (0x1UL << FMC_CSQCFGR2_RCMD2EN_Pos)       /*!< 0x00000002 */
+#define FMC_CSQCFGR2_RCMD2EN          FMC_CSQCFGR2_RCMD2EN_Msk                 /*!< Random Command 2 sequencer enable */
+#define FMC_CSQCFGR2_DMASEN_Pos       (2U)
+#define FMC_CSQCFGR2_DMASEN_Msk       (0x1UL << FMC_CSQCFGR2_DMASEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR2_DMASEN           FMC_CSQCFGR2_DMASEN_Msk                  /*!< Command sequencer DMA request decoding status enable */
+#define FMC_CSQCFGR2_RCMD1_Pos        (8U)
+#define FMC_CSQCFGR2_RCMD1_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD1_Pos)        /*!< 0x0000FF00 */
+#define FMC_CSQCFGR2_RCMD1            FMC_CSQCFGR2_RCMD1_Msk                   /*!< Random Command 1 sequencer */
+#define FMC_CSQCFGR2_RCMD2_Pos        (16U)
+#define FMC_CSQCFGR2_RCMD2_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD2_Pos)        /*!< 0x00FF0000 */
+#define FMC_CSQCFGR2_RCMD2            FMC_CSQCFGR2_RCMD2_Msk                   /*!< Random Command 2 sequencer */
+#define FMC_CSQCFGR2_RCMD1T_Pos       (24U)
+#define FMC_CSQCFGR2_RCMD1T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD1T_Pos)        /*!< 0x01000000 */
+#define FMC_CSQCFGR2_RCMD1T           FMC_CSQCFGR2_RCMD1T_Msk                  /*!< Command 1 sequencer timings */
+#define FMC_CSQCFGR2_RCMD2T_Pos       (25U)
+#define FMC_CSQCFGR2_RCMD2T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD2T_Pos)        /*!< 0x02000000 */
+#define FMC_CSQCFGR2_RCMD2T           FMC_CSQCFGR2_RCMD2T_Msk                  /*!< Command 1 sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR3 register  ***************/
+#define FMC_CSQCFGR3_SNBR_Pos         (8U)
+#define FMC_CSQCFGR3_SNBR_Msk         (0x3FUL << FMC_CSQCFGR3_SNBR_Pos)         /*!< 0x00003F00 */
+#define FMC_CSQCFGR3_SNBR             FMC_CSQCFGR3_SNBR_Msk                    /*!< Number of sectors to be read/written */
+#define FMC_CSQCFGR3_AC1T_Pos         (16U)
+#define FMC_CSQCFGR3_AC1T_Msk         (0x1UL << FMC_CSQCFGR3_AC1T_Pos)          /*!< 0x00010000 */
+#define FMC_CSQCFGR3_AC1T             FMC_CSQCFGR3_AC1T_Msk                    /*!< Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_AC2T_Pos         (17U)
+#define FMC_CSQCFGR3_AC2T_Msk         (0x1UL << FMC_CSQCFGR3_AC2T_Pos)          /*!< 0x00020000 */
+#define FMC_CSQCFGR3_AC2T             FMC_CSQCFGR3_AC2T_Msk                    /*!< Address cycle 2 sequencer timings */
+#define FMC_CSQCFGR3_AC3T_Pos         (18U)
+#define FMC_CSQCFGR3_AC3T_Msk         (0x1UL << FMC_CSQCFGR3_AC3T_Pos)          /*!< 0x00040000 */
+#define FMC_CSQCFGR3_AC3T             FMC_CSQCFGR3_AC3T_Msk                    /*!< Address cycle 3 sequencer timings */
+#define FMC_CSQCFGR3_AC4T_Pos         (19U)
+#define FMC_CSQCFGR3_AC4T_Msk         (0x1UL << FMC_CSQCFGR3_AC4T_Pos)          /*!< 0x00080000 */
+#define FMC_CSQCFGR3_AC4T             FMC_CSQCFGR3_AC4T_Msk                    /*!< Address cycle 4sequencer timings */
+#define FMC_CSQCFGR3_AC5T_Pos         (20U)
+#define FMC_CSQCFGR3_AC5T_Msk         (0x1UL << FMC_CSQCFGR3_AC5T_Pos)          /*!< 0x00100000 */
+#define FMC_CSQCFGR3_AC5T             FMC_CSQCFGR3_AC5T_Msk                    /*!< Address cycle 5 sequencer timings */
+#define FMC_CSQCFGR3_SDT_Pos          (21U)
+#define FMC_CSQCFGR3_SDT_Msk          (0x1UL << FMC_CSQCFGR3_SDT_Pos)           /*!< 0x00200000 */
+#define FMC_CSQCFGR3_SDT              FMC_CSQCFGR3_SDT_Msk                     /*!< Spare data transfer sequencer timings */
+#define FMC_CSQCFGR3_RAC1T_Pos        (22U)
+#define FMC_CSQCFGR3_RAC1T_Msk        (0x1UL << FMC_CSQCFGR3_RAC1T_Pos)         /*!< 0x00400000 */
+#define FMC_CSQCFGR3_RAC1T            FMC_CSQCFGR3_RAC1T_Msk                   /*!< Random Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_RAC2T_Pos        (23U)
+#define FMC_CSQCFGR3_RAC2T_Msk        (0x1UL << FMC_CSQCFGR3_RAC2T_Pos)         /*!< 0x00800000 */
+#define FMC_CSQCFGR3_RAC2T            FMC_CSQCFGR3_RAC2T_Msk                   /*!< Random Address cycle 2 sequencer timings */
+
+/****************  Bit definition for FMC_CSQAR1 register  ****************/
+#define FMC_CSQAR1_ADDC1_Pos          (0U)
+#define FMC_CSQAR1_ADDC1_Msk          (0xFFUL << FMC_CSQAR1_ADDC1_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR1_ADDC1              FMC_CSQAR1_ADDC1_Msk                     /*!< Address Cycle 1 */
+#define FMC_CSQAR1_ADDC2_Pos          (8U)
+#define FMC_CSQAR1_ADDC2_Msk          (0xFFUL << FMC_CSQAR1_ADDC2_Pos)          /*!< 0x0000FF00 */
+#define FMC_CSQAR1_ADDC2              FMC_CSQAR1_ADDC2_Msk                     /*!< Address Cycle 2 */
+#define FMC_CSQAR1_ADDC3_Pos          (16U)
+#define FMC_CSQAR1_ADDC3_Msk          (0xFFUL << FMC_CSQAR1_ADDC3_Pos)          /*!< 0x00FF0000 */
+#define FMC_CSQAR1_ADDC3              FMC_CSQAR1_ADDC3_Msk                     /*!< Address Cycle 3 */
+#define FMC_CSQAR1_ADDC4_Pos          (24U)
+#define FMC_CSQAR1_ADDC4_Msk          (0xFFUL << FMC_CSQAR1_ADDC4_Pos)          /*!< 0xFF000000 */
+#define FMC_CSQAR1_ADDC4              FMC_CSQAR1_ADDC4_Msk                     /*!< Address Cycle 4 */
+
+/****************  Bit definition for FMC_CSQAR2 register  ****************/
+#define FMC_CSQAR2_ADDC5_Pos          (0U)
+#define FMC_CSQAR2_ADDC5_Msk          (0xFFUL << FMC_CSQAR2_ADDC5_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR2_ADDC5              FMC_CSQAR2_ADDC5_Msk                     /*!< Address Cycle 5 */
+#define FMC_CSQAR2_SAO_Pos            (16U)
+#define FMC_CSQAR2_SAO_Msk            (0xFFFFUL << FMC_CSQAR2_SAO_Pos)          /*!< 0xFFFF0000 */
+#define FMC_CSQAR2_SAO                FMC_CSQAR2_SAO_Msk                       /*!< Spare Area Address Offset. */
+
+/****************  Bit definition for FMC_CSQIER register  ****************/
+#define FMC_CSQIER_TCIE_Pos           (0U)
+#define FMC_CSQIER_TCIE_Msk           (0x1UL << FMC_CSQIER_TCIE_Pos)            /*!< 0x00000001 */
+#define FMC_CSQIER_TCIE               FMC_CSQIER_TCIE_Msk                      /*!< Transfer Complete Interrupt enable */
+#define FMC_CSQIER_SCIE_Pos           (1U)
+#define FMC_CSQIER_SCIE_Msk           (0x1UL << FMC_CSQIER_SCIE_Pos)            /*!< 0x00000002 */
+#define FMC_CSQIER_SCIE               FMC_CSQIER_SCIE_Msk                      /*!< Sector Complete interrupt enable */
+#define FMC_CSQIER_SEIE_Pos           (2U)
+#define FMC_CSQIER_SEIE_Msk           (0x1UL << FMC_CSQIER_SEIE_Pos)            /*!< 0x00000004 */
+#define FMC_CSQIER_SEIE               FMC_CSQIER_SEIE_Msk                      /*!< Sector Error interrupt enable */
+#define FMC_CSQIER_SUEIE_Pos          (3U)
+#define FMC_CSQIER_SUEIE_Msk          (0x1UL << FMC_CSQIER_SUEIE_Pos)           /*!< 0x00000008 */
+#define FMC_CSQIER_SUEIE              FMC_CSQIER_SUEIE_Msk                     /*!< Sector Uncorrectable Error interrupt enable */
+#define FMC_CSQIER_CMDTCIE_Pos        (4U)
+#define FMC_CSQIER_CMDTCIE_Msk        (0x1UL << FMC_CSQIER_CMDTCIE_Pos)         /*!< 0x00000010 */
+#define FMC_CSQIER_CMDTCIE            FMC_CSQIER_CMDTCIE_Msk                   /*!< Command Transfer Complete interrupt enable */
+
+/****************  Bit definition for FMC_CSQISR register  ****************/
+#define FMC_CSQISR_TCF_Pos            (0U)
+#define FMC_CSQISR_TCF_Msk            (0x1UL << FMC_CSQISR_TCF_Pos)             /*!< 0x00000001 */
+#define FMC_CSQISR_TCF                FMC_CSQISR_TCF_Msk                       /*!< Transfer Complete flag */
+#define FMC_CSQISR_SCF_Pos            (1U)
+#define FMC_CSQISR_SCF_Msk            (0x1UL << FMC_CSQISR_SCF_Pos)             /*!< 0x00000002 */
+#define FMC_CSQISR_SCF                FMC_CSQISR_SCF_Msk                       /*!< Sector Complete flag */
+#define FMC_CSQISR_SEF_Pos            (2U)
+#define FMC_CSQISR_SEF_Msk            (0x1UL << FMC_CSQISR_SEF_Pos)             /*!< 0x00000004 */
+#define FMC_CSQISR_SEF                FMC_CSQISR_SEF_Msk                       /*!< Sector Error flag */
+#define FMC_CSQISR_SUEF_Pos           (3U)
+#define FMC_CSQISR_SUEF_Msk           (0x1UL << FMC_CSQISR_SUEF_Pos)            /*!< 0x00000008 */
+#define FMC_CSQISR_SUEF               FMC_CSQISR_SUEF_Msk                      /*!< Sector Uncorrectable Error flag */
+#define FMC_CSQISR_CMDTCF_Pos         (4U)
+#define FMC_CSQISR_CMDTCF_Msk         (0x1UL << FMC_CSQISR_CMDTCF_Pos)          /*!< 0x00000010 */
+#define FMC_CSQISR_CMDTCF             FMC_CSQISR_CMDTCF_Msk                    /*!< Command Transfer Complete flag */
+
+/****************  Bit definition for FMC_CSQICR register  ****************/
+#define FMC_CSQICR_CTCF_Pos           (0U)
+#define FMC_CSQICR_CTCF_Msk           (0x1UL << FMC_CSQICR_CTCF_Pos)            /*!< 0x00000001 */
+#define FMC_CSQICR_CTCF               FMC_CSQICR_CTCF_Msk                      /*!< Clear Transfer Complete flag */
+#define FMC_CSQICR_CSCF_Pos           (1U)
+#define FMC_CSQICR_CSCF_Msk           (0x1UL << FMC_CSQICR_CSCF_Pos)            /*!< 0x00000002 */
+#define FMC_CSQICR_CSCF               FMC_CSQICR_CSCF_Msk                      /*!< Clear Sector Complete flag */
+#define FMC_CSQICR_CSEF_Pos           (2U)
+#define FMC_CSQICR_CSEF_Msk           (0x1UL << FMC_CSQICR_CSEF_Pos)            /*!< 0x00000004 */
+#define FMC_CSQICR_CSEF               FMC_CSQICR_CSEF_Msk                      /*!< Clear Sector Error flag */
+#define FMC_CSQICR_CSUEF_Pos          (3U)
+#define FMC_CSQICR_CSUEF_Msk          (0x1UL << FMC_CSQICR_CSUEF_Pos)           /*!< 0x00000008 */
+#define FMC_CSQICR_CSUEF              FMC_CSQICR_CSUEF_Msk                     /*!< Clear Sector uncorrectable Error flag */
+#define FMC_CSQICR_CCMDTCF_Pos        (4U)
+#define FMC_CSQICR_CCMDTCF_Msk        (0x1UL << FMC_CSQICR_CCMDTCF_Pos)         /*!< 0x00000010 */
+#define FMC_CSQICR_CCMDTCF            FMC_CSQICR_CCMDTCF_Msk                   /*!< Clear Command Transfer Complete flag */
+
+/***************  Bit definition for FMC_CSQEMSR register  ****************/
+#define FMC_CSQEMSR_SEM_Pos           (0U)
+#define FMC_CSQEMSR_SEM_Msk           (0xFFFFUL << FMC_CSQEMSR_SEM_Pos)         /*!< 0x0000FFFF */
+#define FMC_CSQEMSR_SEM               FMC_CSQEMSR_SEM_Msk                      /*!< Sector Error mapping */
+
+/****************  Bit definition for FMC_BCHIER register  ****************/
+#define FMC_BCHIER_DUEIE_Pos          (0U)
+#define FMC_BCHIER_DUEIE_Msk          (0x1UL << FMC_BCHIER_DUEIE_Pos)           /*!< 0x00000001 */
+#define FMC_BCHIER_DUEIE              FMC_BCHIER_DUEIE_Msk                     /*!< Decoder Uncorrectable Errors Interrupt enable */
+#define FMC_BCHIER_DERIE_Pos          (1U)
+#define FMC_BCHIER_DERIE_Msk          (0x1UL << FMC_BCHIER_DERIE_Pos)           /*!< 0x00000002 */
+#define FMC_BCHIER_DERIE              FMC_BCHIER_DERIE_Msk                     /*!< Decoder Error Ready Interrupt enable */
+#define FMC_BCHIER_DEFIE_Pos          (2U)
+#define FMC_BCHIER_DEFIE_Msk          (0x1UL << FMC_BCHIER_DEFIE_Pos)           /*!< 0x00000004 */
+#define FMC_BCHIER_DEFIE              FMC_BCHIER_DEFIE_Msk                     /*!< Decoder Error Found Interrupt enable */
+#define FMC_BCHIER_DSRIE_Pos          (3U)
+#define FMC_BCHIER_DSRIE_Msk          (0x1UL << FMC_BCHIER_DSRIE_Pos)           /*!< 0x00000008 */
+#define FMC_BCHIER_DSRIE              FMC_BCHIER_DSRIE_Msk                     /*!< Decoder Syndrome Ready Interrupt enable */
+#define FMC_BCHIER_EPBRIE_Pos         (4U)
+#define FMC_BCHIER_EPBRIE_Msk         (0x1UL << FMC_BCHIER_EPBRIE_Pos)          /*!< 0x00000010 */
+#define FMC_BCHIER_EPBRIE             FMC_BCHIER_EPBRIE_Msk                    /*!< Decoder Parity Bits Ready Interrupt enable */
+
+/****************  Bit definition for FMC_BCHISR register  ****************/
+#define FMC_BCHISR_DUEF_Pos           (0U)
+#define FMC_BCHISR_DUEF_Msk           (0x1UL << FMC_BCHISR_DUEF_Pos)            /*!< 0x00000001 */
+#define FMC_BCHISR_DUEF               FMC_BCHISR_DUEF_Msk                      /*!< Decoder Uncorrectable Errors flag */
+#define FMC_BCHISR_DERF_Pos           (1U)
+#define FMC_BCHISR_DERF_Msk           (0x1UL << FMC_BCHISR_DERF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHISR_DERF               FMC_BCHISR_DERF_Msk                      /*!< Decoder Error Ready flag */
+#define FMC_BCHISR_DEFF_Pos           (2U)
+#define FMC_BCHISR_DEFF_Msk           (0x1UL << FMC_BCHISR_DEFF_Pos)            /*!< 0x00000004 */
+#define FMC_BCHISR_DEFF               FMC_BCHISR_DEFF_Msk                      /*!< Decoder Error Found flag */
+#define FMC_BCHISR_DSRF_Pos           (3U)
+#define FMC_BCHISR_DSRF_Msk           (0x1UL << FMC_BCHISR_DSRF_Pos)            /*!< 0x00000008 */
+#define FMC_BCHISR_DSRF               FMC_BCHISR_DSRF_Msk                      /*!< Decoder Syndrome Ready flag */
+#define FMC_BCHISR_EPBRF_Pos          (4U)
+#define FMC_BCHISR_EPBRF_Msk          (0x1UL << FMC_BCHISR_EPBRF_Pos)           /*!< 0x00000010 */
+#define FMC_BCHISR_EPBRF              FMC_BCHISR_EPBRF_Msk                     /*!< Encoder Parity Bits Ready flag */
+
+/****************  Bit definition for FMC_BCHICR register  ****************/
+#define FMC_BCHICR_CDUEF_Pos          (0U)
+#define FMC_BCHICR_CDUEF_Msk          (0x1UL << FMC_BCHICR_CDUEF_Pos)           /*!< 0x00000001 */
+#define FMC_BCHICR_CDUEF              FMC_BCHICR_CDUEF_Msk                     /*!< Clear Decoder Uncorrectable Error flag */
+#define FMC_BCHICR_CDERF_Pos          (1U)
+#define FMC_BCHICR_CDERF_Msk          (0x1UL << FMC_BCHICR_CDERF_Pos)           /*!< 0x00000002 */
+#define FMC_BCHICR_CDERF              FMC_BCHICR_CDERF_Msk                     /*!< Clear Decoder Error ready flag */
+#define FMC_BCHICR_CDEFF_Pos          (2U)
+#define FMC_BCHICR_CDEFF_Msk          (0x1UL << FMC_BCHICR_CDEFF_Pos)           /*!< 0x00000004 */
+#define FMC_BCHICR_CDEFF              FMC_BCHICR_CDEFF_Msk                     /*!< Clear Decoder Error Found flag */
+#define FMC_BCHICR_CDSRF_Pos          (3U)
+#define FMC_BCHICR_CDSRF_Msk          (0x1UL << FMC_BCHICR_CDSRF_Pos)           /*!< 0x00000008 */
+#define FMC_BCHICR_CDSRF              FMC_BCHICR_CDSRF_Msk                     /*!< Clear Decoder Syndrome Ready flag */
+#define FMC_BCHICR_CEPBRF_Pos         (4U)
+#define FMC_BCHICR_CEPBRF_Msk         (0x1UL << FMC_BCHICR_CEPBRF_Pos)          /*!< 0x00000010 */
+#define FMC_BCHICR_CEPBRF             FMC_BCHICR_CEPBRF_Msk                    /*!< Clear Encoder Parity Bits Ready flag */
+
+/***************  Bit definition for FMC_BCHPBR1 register  ****************/
+#define FMC_BCHPBR1_BCHPB_Pos         (0U)
+#define FMC_BCHPBR1_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR1_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR1_BCHPB             FMC_BCHPBR1_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR2 register  ****************/
+#define FMC_BCHPBR2_BCHPB_Pos         (0U)
+#define FMC_BCHPBR2_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR2_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR2_BCHPB             FMC_BCHPBR2_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR3 register  ****************/
+#define FMC_BCHPBR3_BCHPB_Pos         (0U)
+#define FMC_BCHPBR3_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR3_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR3_BCHPB             FMC_BCHPBR3_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR4 register  ****************/
+#define FMC_BCHPBR4_BCHPB_Pos         (0U)
+#define FMC_BCHPBR4_BCHPB_Msk         (0xFFUL << FMC_BCHPBR4_BCHPB_Pos)         /*!< 0x000000FF */
+#define FMC_BCHPBR4_BCHPB             FMC_BCHPBR4_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHDSR0 register  ****************/
+#define FMC_BCHDSR0_DUE_Pos           (0U)
+#define FMC_BCHDSR0_DUE_Msk           (0x1UL << FMC_BCHDSR0_DUE_Pos)            /*!< 0x00000001 */
+#define FMC_BCHDSR0_DUE               FMC_BCHDSR0_DUE_Msk                      /*!< Decoder uncorrectable error */
+#define FMC_BCHDSR0_DEF_Pos           (1U)
+#define FMC_BCHDSR0_DEF_Msk           (0x1UL << FMC_BCHDSR0_DEF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHDSR0_DEF               FMC_BCHDSR0_DEF_Msk                      /*!< Decoder error found */
+#define FMC_BCHDSR0_DEN_Pos           (4U)
+#define FMC_BCHDSR0_DEN_Msk           (0xFUL << FMC_BCHDSR0_DEN_Pos)            /*!< 0x000000F0 */
+#define FMC_BCHDSR0_DEN               FMC_BCHDSR0_DEN_Msk                      /*!< Decoder error number */
+
+/***************  Bit definition for FMC_BCHDSR1 register  ****************/
+#define FMC_BCHDSR1_EBP1_Pos          (0U)
+#define FMC_BCHDSR1_EBP1_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP1_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR1_EBP1              FMC_BCHDSR1_EBP1_Msk                     /*!< Error bit position for error number 1 */
+#define FMC_BCHDSR1_EBP2_Pos          (16U)
+#define FMC_BCHDSR1_EBP2_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP2_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR1_EBP2              FMC_BCHDSR1_EBP2_Msk                     /*!< Error bit position for error number 2 */
+
+/***************  Bit definition for FMC_BCHDSR2 register  ****************/
+#define FMC_BCHDSR2_EBP3_Pos          (0U)
+#define FMC_BCHDSR2_EBP3_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP3_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR2_EBP3              FMC_BCHDSR2_EBP3_Msk                     /*!< Error bit position for error number 3 */
+#define FMC_BCHDSR2_EBP4_Pos          (16U)
+#define FMC_BCHDSR2_EBP4_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP4_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR2_EBP4              FMC_BCHDSR2_EBP4_Msk                     /*!< Error bit position for error number 4 */
+
+/***************  Bit definition for FMC_BCHDSR3 register  ****************/
+#define FMC_BCHDSR3_EBP5_Pos          (0U)
+#define FMC_BCHDSR3_EBP5_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP5_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR3_EBP5              FMC_BCHDSR3_EBP5_Msk                     /*!< Error bit position for error number 5 */
+#define FMC_BCHDSR3_EBP6_Pos          (16U)
+#define FMC_BCHDSR3_EBP6_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP6_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR3_EBP6              FMC_BCHDSR3_EBP6_Msk                     /*!< Error bit position for error number 6 */
+
+/***************  Bit definition for FMC_BCHDSR4 register  ****************/
+#define FMC_BCHDSR4_EBP7_Pos          (0U)
+#define FMC_BCHDSR4_EBP7_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP7_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR4_EBP7              FMC_BCHDSR4_EBP7_Msk                     /*!< Error bit position for error number 7 */
+#define FMC_BCHDSR4_EBP8_Pos          (16U)
+#define FMC_BCHDSR4_EBP8_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP8_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR4_EBP8              FMC_BCHDSR4_EBP8_Msk                     /*!< Error bit position for error number 8 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic MMU (GFXMMU)                                 */
+/*                                                                            */
+/******************************************************************************/
+/****************** Bits definition for GFXMMU_CR register ********************/
+#define GFXMMU_CR_B0OIE_Pos                (0U)
+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)      /*!< 0x00000001 */
+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */
+#define GFXMMU_CR_B1OIE_Pos                (1U)
+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)      /*!< 0x00000002 */
+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */
+#define GFXMMU_CR_B2OIE_Pos                (2U)
+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)      /*!< 0x00000004 */
+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */
+#define GFXMMU_CR_B3OIE_Pos                (3U)
+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)      /*!< 0x00000008 */
+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */
+#define GFXMMU_CR_AMEIE_Pos                (4U)
+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)      /*!< 0x00000010 */
+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */
+#define GFXMMU_CR_BS_Pos                   (6U)
+#define GFXMMU_CR_BS_Msk                   (0x1UL << GFXMMU_CR_BS_Pos)         /*!< 0x00000040 */
+#define GFXMMU_CR_BS                       GFXMMU_CR_BS_Msk                    /*!< Block size */
+#define GFXMMU_CR_ATE_Pos                  (15U)
+#define GFXMMU_CR_ATE_Msk                  (0x1UL << GFXMMU_CR_ATE_Pos)        /*!< 0x00008000 */
+#define GFXMMU_CR_ATE                      GFXMMU_CR_ATE_Msk                   /*!< Address translation enable */
+#define GFXMMU_CR_B0PE_Pos                 (24U)
+#define GFXMMU_CR_B0PE_Msk                 (0x1UL << GFXMMU_CR_B0PE_Pos)       /*!< 0x01000000 */
+#define GFXMMU_CR_B0PE                     GFXMMU_CR_B0PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B0PM_Pos                 (25U)
+#define GFXMMU_CR_B0PM_Msk                 (0x1UL << GFXMMU_CR_B0PM_Pos)       /*!< 0x02000000 */
+#define GFXMMU_CR_B0PM                     GFXMMU_CR_B0PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B1PE_Pos                 (26U)
+#define GFXMMU_CR_B1PE_Msk                 (0x1UL << GFXMMU_CR_B1PE_Pos)       /*!< 0x04000000 */
+#define GFXMMU_CR_B1PE                     GFXMMU_CR_B1PE_Msk                  /*!< Buffer 1 packing enable */
+#define GFXMMU_CR_B1PM_Pos                 (27U)
+#define GFXMMU_CR_B1PM_Msk                 (0x1UL << GFXMMU_CR_B1PM_Pos)       /*!< 0x08000000 */
+#define GFXMMU_CR_B1PM                     GFXMMU_CR_B1PM_Msk                  /*!< Buffer 1 packing mode */
+#define GFXMMU_CR_B2PE_Pos                 (28U)
+#define GFXMMU_CR_B2PE_Msk                 (0x1UL << GFXMMU_CR_B2PE_Pos)       /*!< 0x10000000 */
+#define GFXMMU_CR_B2PE                     GFXMMU_CR_B2PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B2PM_Pos                 (29U)
+#define GFXMMU_CR_B2PM_Msk                 (0x1UL << GFXMMU_CR_B2PM_Pos)       /*!< 0x20000000 */
+#define GFXMMU_CR_B2PM                     GFXMMU_CR_B2PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B3PE_Pos                 (30U)
+#define GFXMMU_CR_B3PE_Msk                 (0x1UL << GFXMMU_CR_B3PE_Pos)       /*!< 0x40000000 */
+#define GFXMMU_CR_B3PE                     GFXMMU_CR_B3PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B3PM_Pos                 (31U)
+#define GFXMMU_CR_B3PM_Msk                 (0x1UL << GFXMMU_CR_B3PM_Pos)       /*!< 0x80000000 */
+#define GFXMMU_CR_B3PM                     GFXMMU_CR_B3PM_Msk                  /*!< Buffer 0 packing mode */
+
+/****************** Bits definition for GFXMMU_SR register ********************/
+#define GFXMMU_SR_B0OF_Pos                 (0U)
+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)       /*!< 0x00000001 */
+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */
+#define GFXMMU_SR_B1OF_Pos                 (1U)
+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)       /*!< 0x00000002 */
+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */
+#define GFXMMU_SR_B2OF_Pos                 (2U)
+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)       /*!< 0x00000004 */
+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */
+#define GFXMMU_SR_B3OF_Pos                 (3U)
+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)       /*!< 0x00000008 */
+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */
+#define GFXMMU_SR_AMEF_Pos                 (4U)
+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)       /*!< 0x00000010 */
+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AXI master error flag */
+
+/****************** Bits definition for GFXMMU_FCR register *******************/
+#define GFXMMU_FCR_CB0OF_Pos               (0U)
+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)     /*!< 0x00000001 */
+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */
+#define GFXMMU_FCR_CB1OF_Pos               (1U)
+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)     /*!< 0x00000002 */
+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */
+#define GFXMMU_FCR_CB2OF_Pos               (2U)
+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)     /*!< 0x00000004 */
+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */
+#define GFXMMU_FCR_CB3OF_Pos               (3U)
+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)     /*!< 0x00000008 */
+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */
+#define GFXMMU_FCR_CAMEF_Pos               (4U)
+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)     /*!< 0x00000010 */
+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */
+
+/****************** Bits definition for GFXMMU_DVR register *******************/
+#define GFXMMU_DVR_DV_Pos                  (0U)
+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */
+
+/****************** Bits definition for GFXMMU_DAR register *******************/
+#define GFXMMU_DAR_DA_Pos                  (0U)
+#define GFXMMU_DAR_DA_Msk                  (0xFFUL << GFXMMU_DVR_DA_Pos)       /*!< 0x000000FF */
+#define GFXMMU_DAR_DA                      GFXMMU_DVR_DA_Msk                   /*!< DA[7:0] bits (Default alpha) */
+
+/****************** Bits definition for GFXMMU_B0CR register ******************/
+#define GFXMMU_B0CR_PBO_Pos                (4U)
+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B0CR_PBBA_Pos               (23U)
+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B1CR register ******************/
+#define GFXMMU_B1CR_PBO_Pos                (4U)
+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B1CR_PBBA_Pos               (23U)
+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B2CR register ******************/
+#define GFXMMU_B2CR_PBO_Pos                (4U)
+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B2CR_PBBA_Pos               (23U)
+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B3CR register ******************/
+#define GFXMMU_B3CR_PBO_Pos                (4U)
+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B3CR_PBBA_Pos               (23U)
+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_LUTxL register *****************/
+#define GFXMMU_LUTxL_EN_Pos                (0U)
+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)      /*!< 0x00000001 */
+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */
+#define GFXMMU_LUTxL_FVB_Pos               (8U)
+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)    /*!< 0x0000FF00 */
+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */
+#define GFXMMU_LUTxL_LVB_Pos               (16U)
+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)    /*!< 0x00FF0000 */
+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */
+
+/****************** Bits definition for GFXMMU_LUTxH register *****************/
+#define GFXMMU_LUTxH_LO_Pos                (0U)
+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)  /*!< 0x0003FFFF */
+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[17:0] bits (Line offset) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic Timer (GFXTIM)                               */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CR_TES_Pos              (0U)
+#define GFXTIM_CR_TES_Msk              (0x3UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000003 */
+#define GFXTIM_CR_TES                  GFXTIM_CR_TES_Msk
+#define GFXTIM_CR_TES_0                (0x1UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000001 */
+#define GFXTIM_CR_TES_1                (0x2UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000002 */
+
+#define GFXTIM_CR_TEPOL_Pos            (4U)
+#define GFXTIM_CR_TEPOL_Msk            (0x1UL << GFXTIM_CR_TEPOL_Pos)          /*!< 0x00000010 */
+#define GFXTIM_CR_TEPOL                GFXTIM_CR_TEPOL_Msk
+
+#define GFXTIM_CR_SYNCS_Pos            (8U)
+#define GFXTIM_CR_SYNCS_Msk            (0x3UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000300 */
+#define GFXTIM_CR_SYNCS                GFXTIM_CR_SYNCS_Msk
+#define GFXTIM_CR_SYNCS_0              (0x1UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000100 */
+#define GFXTIM_CR_SYNCS_1              (0x2UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000200 */
+
+#define GFXTIM_CR_FCCOE_Pos            (16U)
+#define GFXTIM_CR_FCCOE_Msk            (0x1UL << GFXTIM_CR_FCCOE_Pos)          /*!< 0x00010000 */
+#define GFXTIM_CR_FCCOE                GFXTIM_CR_FCCOE_Msk
+
+#define GFXTIM_CR_LCCOE_Pos            (17U)
+#define GFXTIM_CR_LCCOE_Msk            (0x1UL << GFXTIM_CR_LCCOE_Pos)          /*!< 0x00020000 */
+#define GFXTIM_CR_LCCOE                GFXTIM_CR_LCCOE_Msk
+
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CGCR_LCS_Pos           (0U)
+#define GFXTIM_CGCR_LCS_Msk           (0x7UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_LCS               GFXTIM_CGCR_LCS_Msk
+#define GFXTIM_CGCR_LCS_0             (0x1UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000001 */
+#define GFXTIM_CGCR_LCS_1             (0x2UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000002 */
+#define GFXTIM_CGCR_LCS_2             (0x4UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000004 */
+
+#define GFXTIM_CGCR_LCCCS_Pos         (4U)
+#define GFXTIM_CGCR_LCCCS_Msk         (0x1UL << GFXTIM_CGCR_LCCCS_Pos)         /*!< 0x00000010 */
+#define GFXTIM_CGCR_LCCCS             GFXTIM_CGCR_LCCCS_Msk
+
+#define GFXTIM_CGCR_LCCFR_Pos         (8U)
+#define GFXTIM_CGCR_LCCFR_Msk         (0x1UL << GFXTIM_CGCR_LCCFR_Pos)         /*!< 0x00000100 */
+#define GFXTIM_CGCR_LCCFR             GFXTIM_CGCR_LCCFR_Msk
+
+#define GFXTIM_CGCR_LCCHRS_Pos        (12U)
+#define GFXTIM_CGCR_LCCHRS_Msk        (0x7UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00007000 */
+#define GFXTIM_CGCR_LCCHRS            GFXTIM_CGCR_LCCHRS_Msk
+#define GFXTIM_CGCR_LCCHRS_0          (0x1UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00001000 */
+#define GFXTIM_CGCR_LCCHRS_1          (0x2UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00002000 */
+#define GFXTIM_CGCR_LCCHRS_2          (0x4UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCS_Pos           (16U)
+#define GFXTIM_CGCR_FCS_Msk           (0x7UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_FCS               GFXTIM_CGCR_FCS_Msk
+#define GFXTIM_CGCR_FCS_0             (0x1UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00001000 */
+#define GFXTIM_CGCR_FCS_1             (0x2UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00002000 */
+#define GFXTIM_CGCR_FCS_2             (0x4UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCCCS_Pos         (20U)
+#define GFXTIM_CGCR_FCCCS_Msk         (0x7UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00070000 */
+#define GFXTIM_CGCR_FCCCS             GFXTIM_CGCR_FCCCS_Msk
+#define GFXTIM_CGCR_FCCCS_0           (0x1UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00010000 */
+#define GFXTIM_CGCR_FCCCS_1           (0x2UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00020000 */
+#define GFXTIM_CGCR_FCCCS_2           (0x4UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_CGCR_FCCFR_Pos         (24U)
+#define GFXTIM_CGCR_FCCFR_Msk         (0x1UL << GFXTIM_CGCR_FCCFR_Pos)         /*!< 0x00100000 */
+#define GFXTIM_CGCR_FCCFR             GFXTIM_CGCR_FCCFR_Msk
+
+#define GFXTIM_CGCR_FCCHRS_Pos        (28U)
+#define GFXTIM_CGCR_FCCHRS_Msk        (0x7UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x70000000 */
+#define GFXTIM_CGCR_FCCHRS            GFXTIM_CGCR_FCCHRS_Msk
+#define GFXTIM_CGCR_FCCHRS_0          (0x1UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x10000000 */
+#define GFXTIM_CGCR_FCCHRS_1          (0x2UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x20000000 */
+#define GFXTIM_CGCR_FCCHRS_2          (0x4UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_TCR register  *****************/
+#define GFXTIM_TCR_AFCEN_Pos           (0U)
+#define GFXTIM_TCR_AFCEN_Msk           (0x1UL << GFXTIM_TCR_AFCEN_Pos)         /*!< 0x00000001 */
+#define GFXTIM_TCR_AFCEN               GFXTIM_TCR_AFCEN_Msk
+
+#define GFXTIM_TCR_FAFCR_Pos           (1U)
+#define GFXTIM_TCR_FAFCR_Msk           (0x1UL << GFXTIM_TCR_FAFCR_Pos)         /*!< 0x00000002 */
+#define GFXTIM_TCR_FAFCR               GFXTIM_TCR_FAFCR_Msk
+
+#define GFXTIM_TCR_ALCEN_Pos           (4U)
+#define GFXTIM_TCR_ALCEN_Msk           (0x1UL << GFXTIM_TCR_ALCEN_Pos)         /*!< 0x00000010 */
+#define GFXTIM_TCR_ALCEN               GFXTIM_TCR_ALCEN_Msk
+
+#define GFXTIM_TCR_FALCR_Pos           (5U)
+#define GFXTIM_TCR_FALCR_Msk           (0x1UL << GFXTIM_TCR_FALCR_Pos)         /*!< 0x00000020 */
+#define GFXTIM_TCR_FALCR               GFXTIM_TCR_FALCR_Msk
+
+#define GFXTIM_TCR_RFC1EN_Pos          (16U)
+#define GFXTIM_TCR_RFC1EN_Msk          (0x1UL << GFXTIM_TCR_RFC1EN_Pos)        /*!< 0x00010000 */
+#define GFXTIM_TCR_RFC1EN              GFXTIM_TCR_RFC1EN_Msk
+
+#define GFXTIM_TCR_RFC1CM_Pos          (17U)
+#define GFXTIM_TCR_RFC1CM_Msk          (0x1UL << GFXTIM_TCR_RFC1CM_Pos)        /*!< 0x00020000 */
+#define GFXTIM_TCR_RFC1CM              GFXTIM_TCR_RFC1CM_Msk
+
+#define GFXTIM_TCR_FRFC1R_Pos          (18U)
+#define GFXTIM_TCR_FRFC1R_Msk          (0x1UL << GFXTIM_TCR_FRFC1R_Pos)        /*!< 0x00040000 */
+#define GFXTIM_TCR_FRFC1R              GFXTIM_TCR_FRFC1R_Msk
+
+#define GFXTIM_TCR_RFC2EN_Pos          (20U)
+#define GFXTIM_TCR_RFC2EN_Msk          (0x1UL << GFXTIM_TCR_RFC2EN_Pos)        /*!< 0x00100000 */
+#define GFXTIM_TCR_RFC2EN              GFXTIM_TCR_RFC2EN_Msk
+
+#define GFXTIM_TCR_RFC2CM_Pos          (21U)
+#define GFXTIM_TCR_RFC2CM_Msk          (0x1UL << GFXTIM_TCR_RFC2CM_Pos)        /*!< 0x00200000 */
+#define GFXTIM_TCR_RFC2CM              GFXTIM_TCR_RFC2CM_Msk
+
+#define GFXTIM_TCR_FRFC2R_Pos          (22U)
+#define GFXTIM_TCR_FRFC2R_Msk          (0x1UL << GFXTIM_TCR_FRFC2R_Pos)        /*!< 0x00400000 */
+#define GFXTIM_TCR_FRFC2R              GFXTIM_TCR_FRFC2R_Msk
+
+/******************  Bits definition for GFXTIM_TDR register  *****************/
+#define GFXTIM_TDR_AFCDIS_Pos          (0U)
+#define GFXTIM_TDR_AFCDIS_Msk          (0x1UL << GFXTIM_TDR_AFCDIS_Pos)        /*!< 0x00000001 */
+#define GFXTIM_TDR_AFCDIS              GFXTIM_TDR_AFCDIS_Msk
+
+#define GFXTIM_TDR_ALCDIS_Pos          (4U)
+#define GFXTIM_TDR_ALCDIS_Msk          (0x1UL << GFXTIM_TDR_ALCDIS_Pos)        /*!< 0x00000010 */
+#define GFXTIM_TDR_ALCDIS              GFXTIM_TDR_ALCDIS_Msk
+
+#define GFXTIM_TDR_RFC1DIS_Pos         (16U)
+#define GFXTIM_TDR_RFC1DIS_Msk         (0x1UL << GFXTIM_TDR_RFC1DIS_Pos)       /*!< 0x00010000 */
+#define GFXTIM_TDR_RFC1DIS             GFXTIM_TDR_RFC1DIS_Msk
+
+#define GFXTIM_TDR_RFC2DIS_Pos         (20U)
+#define GFXTIM_TDR_RFC2DIS_Msk         (0x1UL << GFXTIM_TDR_RFC2DIS_Pos)       /*!< 0x00100000 */
+#define GFXTIM_TDR_RFC2DIS             GFXTIM_TDR_RFC2DIS_Msk
+
+/******************  Bits definition for GFXTIM_EVCR register  ****************/
+#define GFXTIM_EVCR_EV1EN_Pos          (0U)
+#define GFXTIM_EVCR_EV1EN_Msk          (0x1UL << GFXTIM_EVCR_EV1EN_Pos)        /*!< 0x00000001 */
+#define GFXTIM_EVCR_EV1EN              GFXTIM_EVCR_EV1EN_Msk
+
+#define GFXTIM_EVCR_EV2EN_Pos          (1U)
+#define GFXTIM_EVCR_EV2EN_Msk          (0x1UL << GFXTIM_EVCR_EV2EN_Pos)        /*!< 0x00000002 */
+#define GFXTIM_EVCR_EV2EN              GFXTIM_EVCR_EV2EN_Msk
+
+#define GFXTIM_EVCR_EV3EN_Pos          (2U)
+#define GFXTIM_EVCR_EV3EN_Msk          (0x1UL << GFXTIM_EVCR_EV3EN_Pos)        /*!< 0x00000004 */
+#define GFXTIM_EVCR_EV3EN              GFXTIM_EVCR_EV3EN_Msk
+
+#define GFXTIM_EVCR_EV4EN_Pos          (3U)
+#define GFXTIM_EVCR_EV4EN_Msk          (0x1UL << GFXTIM_EVCR_EV4EN_Pos)        /*!< 0x00000008 */
+#define GFXTIM_EVCR_EV4EN              GFXTIM_EVCR_EV4EN_Msk
+
+/******************  Bits definition for GFXTIM_EVSR register  ****************/
+#define GFXTIM_EVSR_LES1_Pos           (0U)
+#define GFXTIM_EVSR_LES1_Msk           (0x7UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000007 */
+#define GFXTIM_EVSR_LES1               GFXTIM_EVSR_LES1_Msk
+#define GFXTIM_EVSR_LES1_0             (0x1UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000001 */
+#define GFXTIM_EVSR_LES1_1             (0x2UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000002 */
+#define GFXTIM_EVSR_LES1_2             (0x4UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000004 */
+
+#define GFXTIM_EVSR_FES1_Pos           (4U)
+#define GFXTIM_EVSR_FES1_Msk           (0x7UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000070 */
+#define GFXTIM_EVSR_FES1               GFXTIM_EVSR_FES1_Msk
+#define GFXTIM_EVSR_FES1_0             (0x1UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000010 */
+#define GFXTIM_EVSR_FES1_1             (0x2UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000020 */
+#define GFXTIM_EVSR_FES1_2             (0x4UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000040 */
+
+#define GFXTIM_EVSR_LES2_Pos           (8U)
+#define GFXTIM_EVSR_LES2_Msk           (0x7UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000700 */
+#define GFXTIM_EVSR_LES2               GFXTIM_EVSR_LES2_Msk
+#define GFXTIM_EVSR_LES2_0             (0x1UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000100 */
+#define GFXTIM_EVSR_LES2_1             (0x2UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000200 */
+#define GFXTIM_EVSR_LES2_2             (0x4UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000400 */
+
+#define GFXTIM_EVSR_FES2_Pos           (12U)
+#define GFXTIM_EVSR_FES2_Msk           (0x7UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00007000 */
+#define GFXTIM_EVSR_FES2               GFXTIM_EVSR_FES2_Msk
+#define GFXTIM_EVSR_FES2_0             (0x1UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00001000 */
+#define GFXTIM_EVSR_FES2_1             (0x2UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00002000 */
+#define GFXTIM_EVSR_FES2_2             (0x4UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00004000 */
+
+#define GFXTIM_EVSR_LES3_Pos           (16U)
+#define GFXTIM_EVSR_LES3_Msk           (0x7UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00070000 */
+#define GFXTIM_EVSR_LES3               GFXTIM_EVSR_LES3_Msk
+#define GFXTIM_EVSR_LES3_0             (0x1UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00010000 */
+#define GFXTIM_EVSR_LES3_1             (0x2UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00020000 */
+#define GFXTIM_EVSR_LES3_2             (0x4UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_EVSR_FES3_Pos           (20U)
+#define GFXTIM_EVSR_FES3_Msk           (0x7UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00700000 */
+#define GFXTIM_EVSR_FES3               GFXTIM_EVSR_FES3_Msk
+#define GFXTIM_EVSR_FES3_0             (0x1UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00100000 */
+#define GFXTIM_EVSR_FES3_1             (0x2UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00200000 */
+#define GFXTIM_EVSR_FES3_2             (0x4UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00400000 */
+
+#define GFXTIM_EVSR_LES4_Pos           (24U)
+#define GFXTIM_EVSR_LES4_Msk           (0x7UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x07000000 */
+#define GFXTIM_EVSR_LES4               GFXTIM_EVSR_LES4_Msk
+#define GFXTIM_EVSR_LES4_0             (0x1UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x01000000 */
+#define GFXTIM_EVSR_LES4_1             (0x2UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x02000000 */
+#define GFXTIM_EVSR_LES4_2             (0x4UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x04000000 */
+
+#define GFXTIM_EVSR_FES4_Pos           (28U)
+#define GFXTIM_EVSR_FES4_Msk           (0x7UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x70000000 */
+#define GFXTIM_EVSR_FES4               GFXTIM_EVSR_FES4_Msk
+#define GFXTIM_EVSR_FES4_0             (0x1UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x10000000 */
+#define GFXTIM_EVSR_FES4_1             (0x2UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x20000000 */
+#define GFXTIM_EVSR_FES4_2             (0x4UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_WDGTCR register  **************/
+#define GFXTIM_WDGTCR_WDGEN_Pos        (0U)
+#define GFXTIM_WDGTCR_WDGEN_Msk        (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos)      /*!< 0x00000001 */
+#define GFXTIM_WDGTCR_WDGEN            GFXTIM_WDGTCR_WDGEN_Msk
+
+#define GFXTIM_WDGTCR_WDGDIS_Pos       (1U)
+#define GFXTIM_WDGTCR_WDGDIS_Msk       (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos)     /*!< 0x00000002 */
+#define GFXTIM_WDGTCR_WDGDIS           GFXTIM_WDGTCR_WDGDIS_Msk
+
+#define GFXTIM_WDGTCR_WDGS_Pos         (2U)
+#define GFXTIM_WDGTCR_WDGS_Msk         (0x1UL << GFXTIM_WDGTCR_WDGS_Pos)       /*!< 0x00000004 */
+#define GFXTIM_WDGTCR_WDGS             GFXTIM_WDGTCR_WDGS_Msk
+
+#define GFXTIM_WDGTCR_WDGHRC_Pos       (4U)
+#define GFXTIM_WDGTCR_WDGHRC_Msk       (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000030 */
+#define GFXTIM_WDGTCR_WDGHRC           GFXTIM_WDGTCR_WDGHRC_Msk
+#define GFXTIM_WDGTCR_WDGHRC_0         (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000010 */
+#define GFXTIM_WDGTCR_WDGHRC_1         (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000020 */
+
+#define GFXTIM_WDGTCR_WDGCS_Pos        (8U)
+#define GFXTIM_WDGTCR_WDGCS_Msk        (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000700 */
+#define GFXTIM_WDGTCR_WDGCS            GFXTIM_WDGTCR_WDGCS_Msk
+#define GFXTIM_WDGTCR_WDGCS_0          (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000100 */
+#define GFXTIM_WDGTCR_WDGCS_1          (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000200 */
+#define GFXTIM_WDGTCR_WDGCS_2          (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000400 */
+#define GFXTIM_WDGTCR_WDGCS_3          (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000800 */
+
+#define GFXTIM_WDGTCR_FWDGR_Pos        (16U)
+#define GFXTIM_WDGTCR_FWDGR_Msk        (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos)      /*!< 0x00010000 */
+#define GFXTIM_WDGTCR_FWDGR            GFXTIM_WDGTCR_FWDGR_Msk
+
+/******************  Bits definition for GFXTIM_ISR register  *****************/
+#define GFXTIM_ISR_AFCOF_Pos           (0U)
+#define GFXTIM_ISR_AFCOF_Msk           (0x1UL << GFXTIM_ISR_AFCOF_Pos)         /*!< 0x00000001 */
+#define GFXTIM_ISR_AFCOF               GFXTIM_ISR_AFCOF_Msk
+
+#define GFXTIM_ISR_ALCOF_Pos           (1U)
+#define GFXTIM_ISR_ALCOF_Msk           (0x1UL << GFXTIM_ISR_ALCOF_Pos)         /*!< 0x00000002 */
+#define GFXTIM_ISR_ALCOF               GFXTIM_ISR_ALCOF_Msk
+
+#define GFXTIM_ISR_TEF_Pos             (2U)
+#define GFXTIM_ISR_TEF_Msk             (0x1UL << GFXTIM_ISR_TEF_Pos)           /*!< 0x00000004 */
+#define GFXTIM_ISR_TEF                 GFXTIM_ISR_TEF_Msk
+
+#define GFXTIM_ISR_AFCC1F_Pos          (4U)
+#define GFXTIM_ISR_AFCC1F_Msk          (0x1UL << GFXTIM_ISR_AFCC1F_Pos)        /*!< 0x00000010 */
+#define GFXTIM_ISR_AFCC1F              GFXTIM_ISR_AFCC1F_Msk
+
+#define GFXTIM_ISR_ALCC1F_Pos          (8U)
+#define GFXTIM_ISR_ALCC1F_Msk          (0x1UL << GFXTIM_ISR_ALCC1F_Pos)        /*!< 0x00000100 */
+#define GFXTIM_ISR_ALCC1F              GFXTIM_ISR_ALCC1F_Msk
+
+#define GFXTIM_ISR_ALCC2F_Pos          (9U)
+#define GFXTIM_ISR_ALCC2F_Msk          (0x1UL << GFXTIM_ISR_ALCC2F_Pos)        /*!< 0x00000200 */
+#define GFXTIM_ISR_ALCC2F              GFXTIM_ISR_ALCC2F_Msk
+
+#define GFXTIM_ISR_RFC1RF_Pos          (12U)
+#define GFXTIM_ISR_RFC1RF_Msk          (0x1UL << GFXTIM_ISR_RFC1RF_Pos)        /*!< 0x00001000 */
+#define GFXTIM_ISR_RFC1RF              GFXTIM_ISR_RFC1RF_Msk
+
+#define GFXTIM_ISR_RFC2RF_Pos          (13U)
+#define GFXTIM_ISR_RFC2RF_Msk          (0x1UL << GFXTIM_ISR_RFC2RF_Pos)        /*!< 0x00002000 */
+#define GFXTIM_ISR_RFC2RF              GFXTIM_ISR_RFC2RF_Msk
+
+#define GFXTIM_ISR_EV1F_Pos            (16U)
+#define GFXTIM_ISR_EV1F_Msk            (0x1UL << GFXTIM_ISR_EV1F_Pos)          /*!< 0x00010000 */
+#define GFXTIM_ISR_EV1F                GFXTIM_ISR_EV1F_Msk
+
+#define GFXTIM_ISR_EV2F_Pos            (17U)
+#define GFXTIM_ISR_EV2F_Msk            (0x1UL << GFXTIM_ISR_EV2F_Pos)          /*!< 0x00020000 */
+#define GFXTIM_ISR_EV2F                GFXTIM_ISR_EV2F_Msk
+
+#define GFXTIM_ISR_EV3F_Pos            (18U)
+#define GFXTIM_ISR_EV3F_Msk            (0x1UL << GFXTIM_ISR_EV3F_Pos)          /*!< 0x00040000 */
+#define GFXTIM_ISR_EV3F                GFXTIM_ISR_EV3F_Msk
+
+#define GFXTIM_ISR_EV4F_Pos            (19U)
+#define GFXTIM_ISR_EV4F_Msk            (0x1UL << GFXTIM_ISR_EV4F_Pos)          /*!< 0x00080000 */
+#define GFXTIM_ISR_EV4F                GFXTIM_ISR_EV4F_Msk
+
+#define GFXTIM_ISR_WDGAF_Pos           (24U)
+#define GFXTIM_ISR_WDGAF_Msk           (0x1UL << GFXTIM_ISR_WDGAF_Pos)         /*!< 0x01000000 */
+#define GFXTIM_ISR_WDGAF               GFXTIM_ISR_WDGAF_Msk
+
+#define GFXTIM_ISR_WDGPF_Pos           (25U)
+#define GFXTIM_ISR_WDGPF_Msk           (0x1UL << GFXTIM_ISR_WDGPF_Pos)         /*!< 0x02000000 */
+#define GFXTIM_ISR_WDGPF               GFXTIM_ISR_WDGPF_Msk
+
+/******************  Bits definition for GFXTIM_ICR register  *****************/
+#define GFXTIM_ICR_CAFCOF_Pos          (0U)
+#define GFXTIM_ICR_CAFCOF_Msk          (0x1UL << GFXTIM_ICR_CAFCOF_Pos)        /*!< 0x00000001 */
+#define GFXTIM_ICR_CAFCOF              GFXTIM_ICR_CAFCOF_Msk
+
+#define GFXTIM_ICR_CALCOF_Pos          (1U)
+#define GFXTIM_ICR_CALCOF_Msk          (0x1UL << GFXTIM_ICR_CALCOF_Pos)        /*!< 0x00000002 */
+#define GFXTIM_ICR_CALCOF              GFXTIM_ICR_CALCOF_Msk
+
+#define GFXTIM_ICR_CTEF_Pos            (2U)
+#define GFXTIM_ICR_CTEF_Msk            (0x1UL << GFXTIM_ICR_CTEF_Pos)          /*!< 0x00000004 */
+#define GFXTIM_ICR_CTEF                GFXTIM_ICR_CTEF_Msk
+
+#define GFXTIM_ICR_CAFCC1F_Pos         (4U)
+#define GFXTIM_ICR_CAFCC1F_Msk         (0x1UL << GFXTIM_ICR_CAFCC1F_Pos)       /*!< 0x00000010 */
+#define GFXTIM_ICR_CAFCC1F             GFXTIM_ICR_CAFCC1F_Msk
+
+#define GFXTIM_ICR_CALCC1F_Pos         (8U)
+#define GFXTIM_ICR_CALCC1F_Msk         (0x1UL << GFXTIM_ICR_CALCC1F_Pos)       /*!< 0x00000100 */
+#define GFXTIM_ICR_CALCC1F             GFXTIM_ICR_CALCC1F_Msk
+
+#define GFXTIM_ICR_CALCC2F_Pos         (9U)
+#define GFXTIM_ICR_CALCC2F_Msk         (0x1UL << GFXTIM_ICR_CALCC2F_Pos)       /*!< 0x00000200 */
+#define GFXTIM_ICR_CALCC2F             GFXTIM_ICR_CALCC2F_Msk
+
+#define GFXTIM_ICR_CRFC1RF_Pos         (12U)
+#define GFXTIM_ICR_CRFC1RF_Msk         (0x1UL << GFXTIM_ICR_CRFC1RF_Pos)       /*!< 0x00001000 */
+#define GFXTIM_ICR_CRFC1RF             GFXTIM_ICR_CRFC1RF_Msk
+
+#define GFXTIM_ICR_CRFC2RF_Pos         (13U)
+#define GFXTIM_ICR_CRFC2RF_Msk         (0x1UL << GFXTIM_ICR_CRFC2RF_Pos)       /*!< 0x00002000 */
+#define GFXTIM_ICR_CRFC2RF             GFXTIM_ICR_CRFC2RF_Msk
+
+#define GFXTIM_ICR_CEV1F_Pos           (16U)
+#define GFXTIM_ICR_CEV1F_Msk           (0x1UL << GFXTIM_ICR_CEV1F_Pos)         /*!< 0x00010000 */
+#define GFXTIM_ICR_CEV1F               GFXTIM_ICR_CEV1F_Msk
+
+#define GFXTIM_ICR_CEV2F_Pos           (17U)
+#define GFXTIM_ICR_CEV2F_Msk           (0x1UL << GFXTIM_ICR_CEV2F_Pos)         /*!< 0x00020000 */
+#define GFXTIM_ICR_CEV2F               GFXTIM_ICR_CEV2F_Msk
+
+#define GFXTIM_ICR_CEV3F_Pos           (18U)
+#define GFXTIM_ICR_CEV3F_Msk           (0x1UL << GFXTIM_ICR_CEV3F_Pos)         /*!< 0x00040000 */
+#define GFXTIM_ICR_CEV3F               GFXTIM_ICR_CEV3F_Msk
+
+#define GFXTIM_ICR_CEV4F_Pos           (19U)
+#define GFXTIM_ICR_CEV4F_Msk           (0x1UL << GFXTIM_ICR_CEV4F_Pos)         /*!< 0x00080000 */
+#define GFXTIM_ICR_CEV4F               GFXTIM_ICR_CEV4F_Msk
+
+#define GFXTIM_ICR_CWDGAF_Pos          (24U)
+#define GFXTIM_ICR_CWDGAF_Msk          (0x1UL << GFXTIM_ICR_CWDGAF_Pos)        /*!< 0x01000000 */
+#define GFXTIM_ICR_CWDGAF              GFXTIM_ICR_CWDGAF_Msk
+
+#define GFXTIM_ICR_CWDGPF_Pos          (25U)
+#define GFXTIM_ICR_CWDGPF_Msk          (0x1UL << GFXTIM_ICR_CWDGPF_Pos)        /*!< 0x02000000 */
+#define GFXTIM_ICR_CWDGPF              GFXTIM_ICR_CWDGPF_Msk
+
+/******************  Bits definition for GFXTIM_IER register  *****************/
+#define GFXTIM_IER_AFCOIE_Pos          (0U)
+#define GFXTIM_IER_AFCOIE_Msk          (0x1UL << GFXTIM_IER_AFCOIE_Pos)        /*!< 0x00000001 */
+#define GFXTIM_IER_AFCOIE              GFXTIM_IER_AFCOIE_Msk
+
+#define GFXTIM_IER_ALCOIE_Pos          (1U)
+#define GFXTIM_IER_ALCOIE_Msk          (0x1UL << GFXTIM_IER_ALCOIE_Pos)        /*!< 0x00000002 */
+#define GFXTIM_IER_ALCOIE              GFXTIM_IER_ALCOIE_Msk
+
+#define GFXTIM_IER_TEIE_Pos            (2U)
+#define GFXTIM_IER_TEIE_Msk            (0x1UL << GFXTIM_IER_TEIE_Pos)          /*!< 0x00000004 */
+#define GFXTIM_IER_TEIE                GFXTIM_IER_TEIE_Msk
+
+#define GFXTIM_IER_AFCC1IE_Pos         (4U)
+#define GFXTIM_IER_AFCC1IE_Msk         (0x1UL << GFXTIM_IER_AFCC1IE_Pos)       /*!< 0x00000010 */
+#define GFXTIM_IER_AFCC1IE             GFXTIM_IER_AFCC1IE_Msk
+
+#define GFXTIM_IER_ALCC1IE_Pos         (8U)
+#define GFXTIM_IER_ALCC1IE_Msk         (0x1UL << GFXTIM_IER_ALCC1IE_Pos)       /*!< 0x00000100 */
+#define GFXTIM_IER_ALCC1IE             GFXTIM_IER_ALCC1IE_Msk
+
+#define GFXTIM_IER_ALCC2IE_Pos         (9U)
+#define GFXTIM_IER_ALCC2IE_Msk         (0x1UL << GFXTIM_IER_ALCC2IE_Pos)       /*!< 0x00000200 */
+#define GFXTIM_IER_ALCC2IE             GFXTIM_IER_ALCC2IE_Msk
+
+#define GFXTIM_IER_RFC1RIE_Pos         (12U)
+#define GFXTIM_IER_RFC1RIE_Msk         (0x1UL << GFXTIM_IER_RFC1RIE_Pos)       /*!< 0x00001000 */
+#define GFXTIM_IER_RFC1RIE             GFXTIM_IER_RFC1RIE_Msk
+
+#define GFXTIM_IER_RFC2RIE_Pos         (13U)
+#define GFXTIM_IER_RFC2RIE_Msk         (0x1UL << GFXTIM_IER_RFC2RIE_Pos)       /*!< 0x00002000 */
+#define GFXTIM_IER_RFC2RIE             GFXTIM_IER_RFC2RIE_Msk
+
+#define GFXTIM_IER_EV1IE_Pos           (16U)
+#define GFXTIM_IER_EV1IE_Msk           (0x1UL << GFXTIM_IER_EV1IE_Pos)         /*!< 0x00010000 */
+#define GFXTIM_IER_EV1IE               GFXTIM_IER_EV1IE_Msk
+
+#define GFXTIM_IER_EV2IE_Pos           (17U)
+#define GFXTIM_IER_EV2IE_Msk           (0x1UL << GFXTIM_IER_EV2IE_Pos)         /*!< 0x00020000 */
+#define GFXTIM_IER_EV2IE               GFXTIM_IER_EV2IE_Msk
+
+#define GFXTIM_IER_EV3IE_Pos           (18U)
+#define GFXTIM_IER_EV3IE_Msk           (0x1UL << GFXTIM_IER_EV3IE_Pos)         /*!< 0x00040000 */
+#define GFXTIM_IER_EV3IE               GFXTIM_IER_EV3IE_Msk
+
+#define GFXTIM_IER_EV4IE_Pos           (19U)
+#define GFXTIM_IER_EV4IE_Msk           (0x1UL << GFXTIM_IER_EV4IE_Pos)         /*!< 0x00080000 */
+#define GFXTIM_IER_EV4IE               GFXTIM_IER_EV4IE_Msk
+
+#define GFXTIM_IER_WDGAIE_Pos          (24U)
+#define GFXTIM_IER_WDGAIE_Msk          (0x1UL << GFXTIM_IER_WDGAIE_Pos)        /*!< 0x01000000 */
+#define GFXTIM_IER_WDGAIE              GFXTIM_IER_WDGAIE_Msk
+
+#define GFXTIM_IER_WDGPIE_Pos          (25U)
+#define GFXTIM_IER_WDGPIE_Msk          (0x1UL << GFXTIM_IER_WDGPIE_Pos)        /*!< 0x02000000 */
+#define GFXTIM_IER_WDGPIE              GFXTIM_IER_WDGPIE_Msk
+
+/******************  Bits definition for GFXTIM_TSR register  *****************/
+#define GFXTIM_TSR_AFCS_Pos            (0U)
+#define GFXTIM_TSR_AFCS_Msk            (0x1UL << GFXTIM_TSR_AFCS_Pos)          /*!< 0x00000001 */
+#define GFXTIM_TSR_AFCS                GFXTIM_TSR_AFCS_Msk
+
+#define GFXTIM_TSR_ALCS_Pos            (4U)
+#define GFXTIM_TSR_ALCS_Msk            (0x1UL << GFXTIM_TSR_ALCS_Pos)          /*!< 0x00000010 */
+#define GFXTIM_TSR_ALCS                GFXTIM_TSR_ALCS_Msk
+
+#define GFXTIM_TSR_RFC1S_Pos           (16U)
+#define GFXTIM_TSR_RFC1S_Msk           (0x1UL << GFXTIM_TSR_RFC1S_Pos)         /*!< 0x00010000 */
+#define GFXTIM_TSR_RFC1S               GFXTIM_TSR_RFC1S_Msk
+
+#define GFXTIM_TSR_RFC2S_Pos           (20U)
+#define GFXTIM_TSR_RFC2S_Msk           (0x1UL << GFXTIM_TSR_RFC2S_Pos)         /*!< 0x00100000 */
+#define GFXTIM_TSR_RFC2S               GFXTIM_TSR_RFC2S_Msk
+
+/******************  Bits definition for GFXTIM_LCCRR register  ***************/
+#define GFXTIM_LCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_LCCRR_RELOAD_Msk        (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
+#define GFXTIM_LCCRR_RELOAD            GFXTIM_LCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_FCCRR register  ***************/
+#define GFXTIM_FCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_FCCRR_RELOAD_Msk        (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_FCCRR_RELOAD            GFXTIM_FCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_ATR register  *****************/
+#define GFXTIM_ATR_LINE_Pos            (0U)
+#define GFXTIM_ATR_LINE_Msk            (0xFFFUL << GFXTIM_ATR_LINE_Pos)        /*!< 0x00000FFF */
+#define GFXTIM_ATR_LINE                GFXTIM_ATR_LINE_Msk
+
+#define GFXTIM_ATR_FRAME_Pos           (12U)
+#define GFXTIM_ATR_FRAME_Msk           (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos)     /*!< 0xFFFFF000 */
+#define GFXTIM_ATR_FRAME               GFXTIM_ATR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_AFCR register  ****************/
+#define GFXTIM_AFCR_FRAME_Pos          (0U)
+#define GFXTIM_AFCR_FRAME_Msk          (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos)    /*!< 0x000FFFFF */
+#define GFXTIM_AFCR_FRAME              GFXTIM_AFCR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCR register  ****************/
+#define GFXTIM_ALCR_LINE_Pos           (0U)
+#define GFXTIM_ALCR_LINE_Msk           (0xFFFUL << GFXTIM_ALCR_LINE_Pos)       /*!< 0x00000FFF */
+#define GFXTIM_ALCR_LINE               GFXTIM_ALCR_LINE_Msk
+
+/******************  Bits definition for GFXTIM_AFCC1R register  **************/
+#define GFXTIM_AFCC1R_FRAME_Pos        (0U)
+#define GFXTIM_AFCC1R_FRAME_Msk        (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos)  /*!< 0x000FFFFF */
+#define GFXTIM_AFCC1R_FRAME            GFXTIM_AFCC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCC1R register  **************/
+#define GFXTIM_ALCC1R_LINE_Pos         (0U)
+#define GFXTIM_ALCC1R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC1R_LINE             GFXTIM_ALCC1R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_ALCC2R register  **************/
+#define GFXTIM_ALCC2R_LINE_Pos         (0U)
+#define GFXTIM_ALCC2R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC2R_LINE             GFXTIM_ALCC2R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_RFC1R register  ***************/
+#define GFXTIM_RFC1R_FRAME_Pos         (0U)
+#define GFXTIM_RFC1R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC1R_FRAME             GFXTIM_RFC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC1RR register  **************/
+#define GFXTIM_RFC1RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC1RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC1RR_FRAME            GFXTIM_RFC1RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2R register  ***************/
+#define GFXTIM_RFC2R_FRAME_Pos         (0U)
+#define GFXTIM_RFC2R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC2R_FRAME             GFXTIM_RFC2R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2RR register  **************/
+#define GFXTIM_RFC2RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC2RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC2RR_FRAME            GFXTIM_RFC2RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_WDGCR register  ***************/
+#define GFXTIM_WDGCR_VALUE_Pos         (0U)
+#define GFXTIM_WDGCR_VALUE_Msk         (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos)    /*!< 0x0000FFFF */
+#define GFXTIM_WDGCR_VALUE             GFXTIM_WDGCR_VALUE_Msk
+
+/******************  Bits definition for GFXTIM_WDGRR register  ***************/
+#define GFXTIM_WDGRR_RELOAD_Pos        (0U)
+#define GFXTIM_WDGRR_RELOAD_Msk        (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos)   /*!< 0x0000FFFF */
+#define GFXTIM_WDGRR_RELOAD            GFXTIM_WDGRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_WDGPAR register  **************/
+#define GFXTIM_WDGPAR_PREALARM_Pos      (0U)
+#define GFXTIM_WDGPAR_PREALARM_Msk     (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
+#define GFXTIM_WDGPAR_PREALARM          GFXTIM_WDGPAR_PREALARM_Msk
+
+/******************  Bits definition for GFXTIM_HWCFGR register  **************/
+
+/******************  Bits definition for GFXTIM_VERR register  ****************/
+#define GFXTIM_VERR_MINREV_Pos         (0U)
+#define GFXTIM_VERR_MINREV_Msk         (0xFUL << GFXTIM_VERR_MINREV_Pos)       /*!< 0x0000000F */
+#define GFXTIM_VERR_MINREV             GFXTIM_VERR_MINREV_Msk
+
+#define GFXTIM_VERR_MAJREV_Pos         (4U)
+#define GFXTIM_VERR_MAJREV_Msk         (0xFUL << GFXTIM_VERR_MAJREV_Pos)       /*!< 0x000000F0 */
+#define GFXTIM_VERR_MAJREV             GFXTIM_VERR_MAJREV_Msk
+
+/******************  Bits definition for GFXTIM_IPIDR register  ***************/
+#define GFXTIM_IPIDR_ID_Pos            (0U)
+#define GFXTIM_IPIDR_ID_Msk            (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_IPIDR_ID                GFXTIM_IPIDR_ID_Msk
+
+/******************  Bits definition for GFXTIM_SIDR register  ****************/
+#define GFXTIM_SIDR_SID_Pos            (0U)
+#define GFXTIM_SIDR_SID_Msk            (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_SIDR_SID                GFXTIM_SIDR_SID_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)
+#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos               (1U)
+#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos               (2U)
+#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos               (3U)
+#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos               (4U)
+#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos               (5U)
+#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos               (6U)
+#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos               (7U)
+#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos               (8U)
+#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos               (9U)
+#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos              (10U)
+#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos              (11U)
+#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos              (12U)
+#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos              (13U)
+#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos              (14U)
+#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos              (15U)
+#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
+
+/******************  Bits definition for GPIO_SECCFGR register  ******************/
+#define GPIO_SECCFGR_SEC0_Pos          (0U)
+#define GPIO_SECCFGR_SEC0_Msk          (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
+#define GPIO_SECCFGR_SEC0              GPIO_SECCFGR_SEC0_Msk
+#define GPIO_SECCFGR_SEC1_Pos          (1U)
+#define GPIO_SECCFGR_SEC1_Msk          (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
+#define GPIO_SECCFGR_SEC1              GPIO_SECCFGR_SEC1_Msk
+#define GPIO_SECCFGR_SEC2_Pos          (2U)
+#define GPIO_SECCFGR_SEC2_Msk          (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
+#define GPIO_SECCFGR_SEC2              GPIO_SECCFGR_SEC2_Msk
+#define GPIO_SECCFGR_SEC3_Pos          (3U)
+#define GPIO_SECCFGR_SEC3_Msk          (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
+#define GPIO_SECCFGR_SEC3              GPIO_SECCFGR_SEC3_Msk
+#define GPIO_SECCFGR_SEC4_Pos          (4U)
+#define GPIO_SECCFGR_SEC4_Msk          (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
+#define GPIO_SECCFGR_SEC4              GPIO_SECCFGR_SEC4_Msk
+#define GPIO_SECCFGR_SEC5_Pos          (5U)
+#define GPIO_SECCFGR_SEC5_Msk          (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
+#define GPIO_SECCFGR_SEC5              GPIO_SECCFGR_SEC5_Msk
+#define GPIO_SECCFGR_SEC6_Pos          (6U)
+#define GPIO_SECCFGR_SEC6_Msk          (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
+#define GPIO_SECCFGR_SEC6              GPIO_SECCFGR_SEC6_Msk
+#define GPIO_SECCFGR_SEC7_Pos          (7U)
+#define GPIO_SECCFGR_SEC7_Msk          (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
+#define GPIO_SECCFGR_SEC7              GPIO_SECCFGR_SEC7_Msk
+#define GPIO_SECCFGR_SEC8_Pos          (8U)
+#define GPIO_SECCFGR_SEC8_Msk          (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
+#define GPIO_SECCFGR_SEC8              GPIO_SECCFGR_SEC8_Msk
+#define GPIO_SECCFGR_SEC9_Pos          (9U)
+#define GPIO_SECCFGR_SEC9_Msk          (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
+#define GPIO_SECCFGR_SEC9              GPIO_SECCFGR_SEC9_Msk
+#define GPIO_SECCFGR_SEC10_Pos         (10U)
+#define GPIO_SECCFGR_SEC10_Msk         (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
+#define GPIO_SECCFGR_SEC10             GPIO_SECCFGR_SEC10_Msk
+#define GPIO_SECCFGR_SEC11_Pos         (11U)
+#define GPIO_SECCFGR_SEC11_Msk         (0x1UL << GPIO_SECCFGR_SEC11_Pos)       /*!< 0x00000800 */
+#define GPIO_SECCFGR_SEC11             GPIO_SECCFGR_SEC11_Msk
+#define GPIO_SECCFGR_SEC12_Pos         (12U)
+#define GPIO_SECCFGR_SEC12_Msk         (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
+#define GPIO_SECCFGR_SEC12             GPIO_SECCFGR_SEC12_Msk
+#define GPIO_SECCFGR_SEC13_Pos         (13U)
+#define GPIO_SECCFGR_SEC13_Msk         (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
+#define GPIO_SECCFGR_SEC13             GPIO_SECCFGR_SEC13_Msk
+#define GPIO_SECCFGR_SEC14_Pos         (14U)
+#define GPIO_SECCFGR_SEC14_Msk         (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
+#define GPIO_SECCFGR_SEC14             GPIO_SECCFGR_SEC14_Msk
+#define GPIO_SECCFGR_SEC15_Pos         (15U)
+#define GPIO_SECCFGR_SEC15_Msk         (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
+#define GPIO_SECCFGR_SEC15             GPIO_SECCFGR_SEC15_Msk
+
+/******************  Bits definition for GPIO_PRIVCFGR register  ******************/
+#define GPIO_PRIVCFGR_PRIV0_Pos        (0U)
+#define GPIO_PRIVCFGR_PRIV0_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV0_Pos)      /*!< 0x00000001 */
+#define GPIO_PRIVCFGR_PRIV0            GPIO_PRIVCFGR_PRIV0_Msk
+#define GPIO_PRIVCFGR_PRIV1_Pos        (1U)
+#define GPIO_PRIVCFGR_PRIV1_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV1_Pos)      /*!< 0x00000002 */
+#define GPIO_PRIVCFGR_PRIV1            GPIO_PRIVCFGR_PRIV1_Msk
+#define GPIO_PRIVCFGR_PRIV2_Pos        (2U)
+#define GPIO_PRIVCFGR_PRIV2_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV2_Pos)      /*!< 0x00000004 */
+#define GPIO_PRIVCFGR_PRIV2            GPIO_PRIVCFGR_PRIV2_Msk
+#define GPIO_PRIVCFGR_PRIV3_Pos        (3U)
+#define GPIO_PRIVCFGR_PRIV3_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV3_Pos)      /*!< 0x00000008 */
+#define GPIO_PRIVCFGR_PRIV3            GPIO_PRIVCFGR_PRIV3_Msk
+#define GPIO_PRIVCFGR_PRIV4_Pos        (4U)
+#define GPIO_PRIVCFGR_PRIV4_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV4_Pos)      /*!< 0x00000010 */
+#define GPIO_PRIVCFGR_PRIV4            GPIO_PRIVCFGR_PRIV4_Msk
+#define GPIO_PRIVCFGR_PRIV5_Pos        (5U)
+#define GPIO_PRIVCFGR_PRIV5_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV5_Pos)      /*!< 0x00000020 */
+#define GPIO_PRIVCFGR_PRIV5            GPIO_PRIVCFGR_PRIV5_Msk
+#define GPIO_PRIVCFGR_PRIV6_Pos        (6U)
+#define GPIO_PRIVCFGR_PRIV6_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV6_Pos)      /*!< 0x00000040 */
+#define GPIO_PRIVCFGR_PRIV6            GPIO_PRIVCFGR_PRIV6_Msk
+#define GPIO_PRIVCFGR_PRIV7_Pos        (7U)
+#define GPIO_PRIVCFGR_PRIV7_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV7_Pos)      /*!< 0x00000080 */
+#define GPIO_PRIVCFGR_PRIV7            GPIO_PRIVCFGR_PRIV7_Msk
+#define GPIO_PRIVCFGR_PRIV8_Pos        (8U)
+#define GPIO_PRIVCFGR_PRIV8_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV8_Pos)      /*!< 0x00000100 */
+#define GPIO_PRIVCFGR_PRIV8            GPIO_PRIVCFGR_PRIV8_Msk
+#define GPIO_PRIVCFGR_PRIV9_Pos        (9U)
+#define GPIO_PRIVCFGR_PRIV9_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV9_Pos)      /*!< 0x00000200 */
+#define GPIO_PRIVCFGR_PRIV9            GPIO_PRIVCFGR_PRIV9_Msk
+#define GPIO_PRIVCFGR_PRIV10_Pos       (10U)
+#define GPIO_PRIVCFGR_PRIV10_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV10_Pos)     /*!< 0x00000400 */
+#define GPIO_PRIVCFGR_PRIV10           GPIO_PRIVCFGR_PRIV10_Msk
+#define GPIO_PRIVCFGR_PRIV11_Pos       (11U)
+#define GPIO_PRIVCFGR_PRIV11_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV11_Pos)     /*!< 0x00000800 */
+#define GPIO_PRIVCFGR_PRIV11           GPIO_PRIVCFGR_PRIV11_Msk
+#define GPIO_PRIVCFGR_PRIV12_Pos       (12U)
+#define GPIO_PRIVCFGR_PRIV12_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV12_Pos)     /*!< 0x00001000 */
+#define GPIO_PRIVCFGR_PRIV12           GPIO_PRIVCFGR_PRIV12_Msk
+#define GPIO_PRIVCFGR_PRIV13_Pos       (13U)
+#define GPIO_PRIVCFGR_PRIV13_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV13_Pos)     /*!< 0x00002000 */
+#define GPIO_PRIVCFGR_PRIV13           GPIO_PRIVCFGR_PRIV13_Msk
+#define GPIO_PRIVCFGR_PRIV14_Pos       (14U)
+#define GPIO_PRIVCFGR_PRIV14_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV14_Pos)     /*!< 0x00004000 */
+#define GPIO_PRIVCFGR_PRIV14           GPIO_PRIVCFGR_PRIV14_Msk
+#define GPIO_PRIVCFGR_PRIV15_Pos       (15U)
+#define GPIO_PRIVCFGR_PRIV15_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV15_Pos)     /*!< 0x00008000 */
+#define GPIO_PRIVCFGR_PRIV15           GPIO_PRIVCFGR_PRIV15_Msk
+
+/******************  Bits definition for GPIO_RCFGLOCKR register  ******************/
+#define GPIO_RCFGLOCKR_RLOCK0_Pos      (0U)
+#define GPIO_RCFGLOCKR_RLOCK0_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK0_Pos)    /*!< 0x00000001 */
+#define GPIO_RCFGLOCKR_RLOCK0          GPIO_RCFGLOCKR_RLOCK0_Msk
+#define GPIO_RCFGLOCKR_RLOCK1_Pos      (1U)
+#define GPIO_RCFGLOCKR_RLOCK1_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK1_Pos)    /*!< 0x00000002 */
+#define GPIO_RCFGLOCKR_RLOCK1          GPIO_RCFGLOCKR_RLOCK1_Msk
+#define GPIO_RCFGLOCKR_RLOCK2_Pos      (2U)
+#define GPIO_RCFGLOCKR_RLOCK2_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK2_Pos)    /*!< 0x00000004 */
+#define GPIO_RCFGLOCKR_RLOCK2          GPIO_RCFGLOCKR_RLOCK2_Msk
+#define GPIO_RCFGLOCKR_RLOCK3_Pos      (3U)
+#define GPIO_RCFGLOCKR_RLOCK3_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK3_Pos)    /*!< 0x00000008 */
+#define GPIO_RCFGLOCKR_RLOCK3          GPIO_RCFGLOCKR_RLOCK3_Msk
+#define GPIO_RCFGLOCKR_RLOCK4_Pos      (4U)
+#define GPIO_RCFGLOCKR_RLOCK4_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK4_Pos)    /*!< 0x00000010 */
+#define GPIO_RCFGLOCKR_RLOCK4          GPIO_RCFGLOCKR_RLOCK4_Msk
+#define GPIO_RCFGLOCKR_RLOCK5_Pos      (5U)
+#define GPIO_RCFGLOCKR_RLOCK5_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK5_Pos)    /*!< 0x00000020 */
+#define GPIO_RCFGLOCKR_RLOCK5          GPIO_RCFGLOCKR_RLOCK5_Msk
+#define GPIO_RCFGLOCKR_RLOCK6_Pos      (6U)
+#define GPIO_RCFGLOCKR_RLOCK6_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK6_Pos)    /*!< 0x00000040 */
+#define GPIO_RCFGLOCKR_RLOCK6          GPIO_RCFGLOCKR_RLOCK6_Msk
+#define GPIO_RCFGLOCKR_RLOCK7_Pos      (7U)
+#define GPIO_RCFGLOCKR_RLOCK7_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK7_Pos)    /*!< 0x00000080 */
+#define GPIO_RCFGLOCKR_RLOCK7          GPIO_RCFGLOCKR_RLOCK7_Msk
+#define GPIO_RCFGLOCKR_RLOCK8_Pos      (8U)
+#define GPIO_RCFGLOCKR_RLOCK8_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK8_Pos)    /*!< 0x00000100 */
+#define GPIO_RCFGLOCKR_RLOCK8          GPIO_RCFGLOCKR_RLOCK8_Msk
+#define GPIO_RCFGLOCKR_RLOCK9_Pos      (9U)
+#define GPIO_RCFGLOCKR_RLOCK9_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK9_Pos)    /*!< 0x00000200 */
+#define GPIO_RCFGLOCKR_RLOCK9          GPIO_RCFGLOCKR_RLOCK9_Msk
+#define GPIO_RCFGLOCKR_RLOCK10_Pos     (10U)
+#define GPIO_RCFGLOCKR_RLOCK10_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK10_Pos)   /*!< 0x00000400 */
+#define GPIO_RCFGLOCKR_RLOCK10         GPIO_RCFGLOCKR_RLOCK10_Msk
+#define GPIO_RCFGLOCKR_RLOCK11_Pos     (11U)
+#define GPIO_RCFGLOCKR_RLOCK11_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK11_Pos)   /*!< 0x00000800 */
+#define GPIO_RCFGLOCKR_RLOCK11         GPIO_RCFGLOCKR_RLOCK11_Msk
+#define GPIO_RCFGLOCKR_RLOCK12_Pos     (12U)
+#define GPIO_RCFGLOCKR_RLOCK12_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK12_Pos)   /*!< 0x00001000 */
+#define GPIO_RCFGLOCKR_RLOCK12         GPIO_RCFGLOCKR_RLOCK12_Msk
+#define GPIO_RCFGLOCKR_RLOCK13_Pos     (13U)
+#define GPIO_RCFGLOCKR_RLOCK13_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK13_Pos)   /*!< 0x00002000 */
+#define GPIO_RCFGLOCKR_RLOCK13         GPIO_RCFGLOCKR_RLOCK13_Msk
+#define GPIO_RCFGLOCKR_RLOCK14_Pos     (14U)
+#define GPIO_RCFGLOCKR_RLOCK14_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK14_Pos)   /*!< 0x00004000 */
+#define GPIO_RCFGLOCKR_RLOCK14         GPIO_RCFGLOCKR_RLOCK14_Msk
+#define GPIO_RCFGLOCKR_RLOCK15_Pos     (15U)
+#define GPIO_RCFGLOCKR_RLOCK15_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK15_Pos)   /*!< 0x00008000 */
+#define GPIO_RCFGLOCKR_RLOCK15         GPIO_RCFGLOCKR_RLOCK15_Msk
+
+/****************** Bit definition for GPIO_DELAYRL register *********************/
+#define GPIO_DELAYRL_DLY0_Pos        (0U)
+#define GPIO_DELAYRL_DLY0_Msk        (0xFUL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRL_DLY0            GPIO_DELAYRL_DLY0_Msk
+#define GPIO_DELAYRL_DLY0_0          (0x1UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRL_DLY0_1          (0x2UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRL_DLY0_2          (0x4UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRL_DLY0_3          (0x8UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRL_DLY1_Pos        (4U)
+#define GPIO_DELAYRL_DLY1_Msk        (0xFUL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRL_DLY1            GPIO_DELAYRL_DLY1_Msk
+#define GPIO_DELAYRL_DLY1_0          (0x1UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRL_DLY1_1          (0x2UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRL_DLY1_2          (0x4UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRL_DLY1_3          (0x8UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRL_DLY2_Pos        (8U)
+#define GPIO_DELAYRL_DLY2_Msk        (0xFUL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000F00 */
+#define GPIO_DELAYRL_DLY2            GPIO_DELAYRL_DLY2_Msk
+#define GPIO_DELAYRL_DLY2_0          (0x1UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000100 */
+#define GPIO_DELAYRL_DLY2_1          (0x2UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000200 */
+#define GPIO_DELAYRL_DLY2_2          (0x4UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000400 */
+#define GPIO_DELAYRL_DLY2_3          (0x8UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000800 */
+#define GPIO_DELAYRL_DLY3_Pos        (12U)
+#define GPIO_DELAYRL_DLY3_Msk        (0xFUL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x0000F000 */
+#define GPIO_DELAYRL_DLY3            GPIO_DELAYRL_DLY3_Msk
+#define GPIO_DELAYRL_DLY3_0          (0x1UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00001000 */
+#define GPIO_DELAYRL_DLY3_1          (0x2UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00002000 */
+#define GPIO_DELAYRL_DLY3_2          (0x4UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00004000 */
+#define GPIO_DELAYRL_DLY3_3          (0x8UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00008000 */
+#define GPIO_DELAYRL_DLY4_Pos        (16U)
+#define GPIO_DELAYRL_DLY4_Msk        (0xFUL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x000F0000 */
+#define GPIO_DELAYRL_DLY4            GPIO_DELAYRL_DLY4_Msk
+#define GPIO_DELAYRL_DLY4_0          (0x1UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00010000 */
+#define GPIO_DELAYRL_DLY4_1          (0x2UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00020000 */
+#define GPIO_DELAYRL_DLY4_2          (0x4UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00040000 */
+#define GPIO_DELAYRL_DLY4_3          (0x8UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00080000 */
+#define GPIO_DELAYRL_DLY5_Pos        (20U)
+#define GPIO_DELAYRL_DLY5_Msk        (0xFUL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00F00000 */
+#define GPIO_DELAYRL_DLY5            GPIO_DELAYRL_DLY5_Msk
+#define GPIO_DELAYRL_DLY5_0          (0x1UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00100000 */
+#define GPIO_DELAYRL_DLY5_1          (0x2UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00200000 */
+#define GPIO_DELAYRL_DLY5_2          (0x4UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00400000 */
+#define GPIO_DELAYRL_DLY5_3          (0x8UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00800000 */
+#define GPIO_DELAYRL_DLY6_Pos        (24U)
+#define GPIO_DELAYRL_DLY6_Msk        (0xFUL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x0F000000 */
+#define GPIO_DELAYRL_DLY6            GPIO_DELAYRL_DLY6_Msk
+#define GPIO_DELAYRL_DLY6_0          (0x1UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x01000000 */
+#define GPIO_DELAYRL_DLY6_1          (0x2UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x02000000 */
+#define GPIO_DELAYRL_DLY6_2          (0x4UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x04000000 */
+#define GPIO_DELAYRL_DLY6_3          (0x8UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x08000000 */
+#define GPIO_DELAYRL_DLY7_Pos        (28U)
+#define GPIO_DELAYRL_DLY7_Msk        (0xFUL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0xF0000000 */
+#define GPIO_DELAYRL_DLY7            GPIO_DELAYRL_DLY7_Msk
+#define GPIO_DELAYRL_DLY7_0          (0x1UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x10000000 */
+#define GPIO_DELAYRL_DLY7_1          (0x2UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x20000000 */
+#define GPIO_DELAYRL_DLY7_2          (0x4UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x40000000 */
+#define GPIO_DELAYRL_DLY7_3          (0x8UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_DELAYRH register *********************/
+#define GPIO_DELAYRH_DLY8_Pos        (0U)
+#define GPIO_DELAYRH_DLY8_Msk        (0xFUL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRH_DLY8            GPIO_DELAYRH_DLY8_Msk
+#define GPIO_DELAYRH_DLY8_0          (0x1UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRH_DLY8_1          (0x2UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRH_DLY8_2          (0x4UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRH_DLY8_3          (0x8UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRH_DLY9_Pos        (4U)
+#define GPIO_DELAYRH_DLY9_Msk        (0xFUL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRH_DLY9            GPIO_DELAYRH_DLY9_Msk
+#define GPIO_DELAYRH_DLY9_0          (0x1UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRH_DLY9_1          (0x2UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRH_DLY9_2          (0x4UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRH_DLY9_3          (0x8UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRH_DLY10_Pos       (8U)
+#define GPIO_DELAYRH_DLY10_Msk       (0xFUL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000F00 */
+#define GPIO_DELAYRH_DLY10           GPIO_DELAYRH_DLY10_Msk
+#define GPIO_DELAYRH_DLY10_0         (0x1UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000100 */
+#define GPIO_DELAYRH_DLY10_1         (0x2UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000200 */
+#define GPIO_DELAYRH_DLY10_2         (0x4UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000400 */
+#define GPIO_DELAYRH_DLY10_3         (0x8UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000800 */
+#define GPIO_DELAYRH_DLY11_Pos       (12U)
+#define GPIO_DELAYRH_DLY11_Msk       (0xFUL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x0000F000 */
+#define GPIO_DELAYRH_DLY11           GPIO_DELAYRH_DLY11_Msk
+#define GPIO_DELAYRH_DLY11_0         (0x1UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00001000 */
+#define GPIO_DELAYRH_DLY11_1         (0x2UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00002000 */
+#define GPIO_DELAYRH_DLY11_2         (0x4UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00004000 */
+#define GPIO_DELAYRH_DLY11_3         (0x8UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00008000 */
+#define GPIO_DELAYRH_DLY12_Pos       (16U)
+#define GPIO_DELAYRH_DLY12_Msk       (0xFUL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x000F0000 */
+#define GPIO_DELAYRH_DLY12           GPIO_DELAYRH_DLY12_Msk
+#define GPIO_DELAYRH_DLY12_0         (0x1UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00010000 */
+#define GPIO_DELAYRH_DLY12_1         (0x2UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00020000 */
+#define GPIO_DELAYRH_DLY12_2         (0x4UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00040000 */
+#define GPIO_DELAYRH_DLY12_3         (0x8UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00080000 */
+#define GPIO_DELAYRH_DLY13_Pos       (20U)
+#define GPIO_DELAYRH_DLY13_Msk       (0xFUL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00F00000 */
+#define GPIO_DELAYRH_DLY13           GPIO_DELAYRH_DLY13_Msk
+#define GPIO_DELAYRH_DLY13_0         (0x1UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00100000 */
+#define GPIO_DELAYRH_DLY13_1         (0x2UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00200000 */
+#define GPIO_DELAYRH_DLY13_2         (0x4UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00400000 */
+#define GPIO_DELAYRH_DLY13_3         (0x8UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00800000 */
+#define GPIO_DELAYRH_DLY14_Pos       (24U)
+#define GPIO_DELAYRH_DLY14_Msk       (0xFUL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x0F000000 */
+#define GPIO_DELAYRH_DLY14           GPIO_DELAYRH_DLY14_Msk
+#define GPIO_DELAYRH_DLY14_0         (0x1UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x01000000 */
+#define GPIO_DELAYRH_DLY14_1         (0x2UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x02000000 */
+#define GPIO_DELAYRH_DLY14_2         (0x4UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x04000000 */
+#define GPIO_DELAYRH_DLY14_3         (0x8UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x08000000 */
+#define GPIO_DELAYRH_DLY15_Pos       (28U)
+#define GPIO_DELAYRH_DLY15_Msk       (0xFUL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0xF0000000 */
+#define GPIO_DELAYRH_DLY15           GPIO_DELAYRH_DLY15_Msk
+#define GPIO_DELAYRH_DLY15_0         (0x1UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x10000000 */
+#define GPIO_DELAYRH_DLY15_1         (0x2UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x20000000 */
+#define GPIO_DELAYRH_DLY15_2         (0x4UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x40000000 */
+#define GPIO_DELAYRH_DLY15_3         (0x8UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRL register *********************/
+#define GPIO_ADVCFGRL_0_Pos            (0U)
+#define GPIO_ADVCFGRL_0_Msk            (0xFUL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRL_0                GPIO_ADVCFGRL_0_Msk
+#define GPIO_ADVCFGRL_DLYPATH0         (0x1UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRL_DE0              (0x2UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRL_INVCLK0          (0x4UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRL_RET0             (0x8UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRL_1_Pos            (4U)
+#define GPIO_ADVCFGRL_1_Msk            (0xFUL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRL_1                GPIO_ADVCFGRL_1_Msk
+#define GPIO_ADVCFGRL_DLYPATH1         (0x1UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRL_DE1              (0x2UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRL_INVCLK1          (0x4UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRL_RET1             (0x8UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRL_2_Pos            (8U)
+#define GPIO_ADVCFGRL_2_Msk            (0xFUL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000F00 */
+#define GPIO_ADVCFGRL_2                GPIO_ADVCFGRL_2_Msk
+#define GPIO_ADVCFGRL_DLYPATH2         (0x1UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000100 */
+#define GPIO_ADVCFGRL_DE2              (0x2UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000200 */
+#define GPIO_ADVCFGRL_INVCLK2          (0x4UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000400 */
+#define GPIO_ADVCFGRL_RET2             (0x8UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000800 */
+#define GPIO_ADVCFGRL_3_Pos            (12U)
+#define GPIO_ADVCFGRL_3_Msk            (0xFUL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x0000F000 */
+#define GPIO_ADVCFGRL_3                GPIO_ADVCFGRL_3_Msk
+#define GPIO_ADVCFGRL_DLYPATH3         (0x1UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00001000 */
+#define GPIO_ADVCFGRL_DE3              (0x2UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00002000 */
+#define GPIO_ADVCFGRL_INVCLK3          (0x4UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00004000 */
+#define GPIO_ADVCFGRL_RET3             (0x8UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00008000 */
+#define GPIO_ADVCFGRL_4_Pos            (16U)
+#define GPIO_ADVCFGRL_4_Msk            (0xFUL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x000F0000 */
+#define GPIO_ADVCFGRL_4                GPIO_ADVCFGRL_4_Msk
+#define GPIO_ADVCFGRL_DLYPATH4         (0x1UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00010000 */
+#define GPIO_ADVCFGRL_DE4              (0x2UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00020000 */
+#define GPIO_ADVCFGRL_INVCLK4          (0x4UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00040000 */
+#define GPIO_ADVCFGRL_RET4             (0x8UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00080000 */
+#define GPIO_ADVCFGRL_5_Pos            (20U)
+#define GPIO_ADVCFGRL_5_Msk            (0xFUL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00F00000 */
+#define GPIO_ADVCFGRL_5                GPIO_ADVCFGRL_5_Msk
+#define GPIO_ADVCFGRL_DLYPATH5         (0x1UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00100000 */
+#define GPIO_ADVCFGRL_DE5              (0x2UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00200000 */
+#define GPIO_ADVCFGRL_INVCLK5          (0x4UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00400000 */
+#define GPIO_ADVCFGRL_RET5             (0x8UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00800000 */
+#define GPIO_ADVCFGRL_6_Pos            (24U)
+#define GPIO_ADVCFGRL_6_Msk            (0xFUL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x0F000000 */
+#define GPIO_ADVCFGRL_6                GPIO_ADVCFGRL_6_Msk
+#define GPIO_ADVCFGRL_DLYPATH6         (0x1UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x01000000 */
+#define GPIO_ADVCFGRL_DE6              (0x2UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x02000000 */
+#define GPIO_ADVCFGRL_INVCLK6          (0x4UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x04000000 */
+#define GPIO_ADVCFGRL_RET6             (0x8UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x08000000 */
+#define GPIO_ADVCFGRL_7_Pos            (28U)
+#define GPIO_ADVCFGRL_7_Msk            (0xFUL << GPIO_ADVCFGRL_7_Pos)          /*!< 0xF0000000 */
+#define GPIO_ADVCFGRL_7                GPIO_ADVCFGRL_7_Msk
+#define GPIO_ADVCFGRL_DLYPATH7         (0x1UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x10000000 */
+#define GPIO_ADVCFGRL_DE7              (0x2UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x20000000 */
+#define GPIO_ADVCFGRL_INVCLK7          (0x4UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x40000000 */
+#define GPIO_ADVCFGRL_RET7             (0x8UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRH register *********************/
+#define GPIO_ADVCFGRH_8_Pos            (0U)
+#define GPIO_ADVCFGRH_8_Msk            (0xFUL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRH_8                GPIO_ADVCFGRH_8_Msk
+#define GPIO_ADVCFGRH_DLYPATH8         (0x1UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRH_DE8              (0x2UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRH_INVCLK8          (0x4UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRH_RET8             (0x8UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRH_9_Pos            (4U)
+#define GPIO_ADVCFGRH_9_Msk            (0xFUL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRH_9                GPIO_ADVCFGRH_9_Msk
+#define GPIO_ADVCFGRH_DLYPATH9         (0x1UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRH_DE9              (0x2UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRH_INVCLK9          (0x4UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRH_RET9             (0x8UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRH_10_Pos           (8U)
+#define GPIO_ADVCFGRH_10_Msk           (0xFUL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000F00 */
+#define GPIO_ADVCFGRH_10               GPIO_ADVCFGRH_10_Msk
+#define GPIO_ADVCFGRH_DLYPATH10        (0x1UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000100 */
+#define GPIO_ADVCFGRH_DE10             (0x2UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000200 */
+#define GPIO_ADVCFGRH_INVCLK10         (0x4UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000400 */
+#define GPIO_ADVCFGRH_RET10            (0x8UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000800 */
+#define GPIO_ADVCFGRH_11_Pos           (12U)
+#define GPIO_ADVCFGRH_11_Msk           (0xFUL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x0000F000 */
+#define GPIO_ADVCFGRH_11               GPIO_ADVCFGRH_11_Msk
+#define GPIO_ADVCFGRH_DLYPATH11        (0x1UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00001000 */
+#define GPIO_ADVCFGRH_DE11             (0x2UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00002000 */
+#define GPIO_ADVCFGRH_INVCLK11         (0x4UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00004000 */
+#define GPIO_ADVCFGRH_RET11            (0x8UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00008000 */
+#define GPIO_ADVCFGRH_12_Pos           (16U)
+#define GPIO_ADVCFGRH_12_Msk           (0xFUL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x000F0000 */
+#define GPIO_ADVCFGRH_12               GPIO_ADVCFGRH_12_Msk
+#define GPIO_ADVCFGRH_DLYPATH12        (0x1UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00010000 */
+#define GPIO_ADVCFGRH_DE12             (0x2UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00020000 */
+#define GPIO_ADVCFGRH_INVCLK12         (0x4UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00040000 */
+#define GPIO_ADVCFGRH_RET12            (0x8UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00080000 */
+#define GPIO_ADVCFGRH_13_Pos           (20U)
+#define GPIO_ADVCFGRH_13_Msk           (0xFUL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00F00000 */
+#define GPIO_ADVCFGRH_13               GPIO_ADVCFGRH_13_Msk
+#define GPIO_ADVCFGRH_DLYPATH13        (0x1UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00100000 */
+#define GPIO_ADVCFGRH_DE13             (0x2UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00200000 */
+#define GPIO_ADVCFGRH_INVCLK13         (0x4UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00400000 */
+#define GPIO_ADVCFGRH_RET13            (0x8UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00800000 */
+#define GPIO_ADVCFGRH_14_Pos           (24U)
+#define GPIO_ADVCFGRH_14_Msk           (0xFUL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x0F000000 */
+#define GPIO_ADVCFGRH_14               GPIO_ADVCFGRH_14_Msk
+#define GPIO_ADVCFGRH_DLYPATH14        (0x1UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x01000000 */
+#define GPIO_ADVCFGRH_DE14             (0x2UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x02000000 */
+#define GPIO_ADVCFGRH_INVCLK14         (0x4UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x04000000 */
+#define GPIO_ADVCFGRH_RET14            (0x8UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x08000000 */
+#define GPIO_ADVCFGRH_15_Pos           (28U)
+#define GPIO_ADVCFGRH_15_Msk           (0xFUL << GPIO_ADVCFGRH_15_Pos)         /*!< 0xF0000000 */
+#define GPIO_ADVCFGRH_15               GPIO_ADVCFGRH_15_Msk
+#define GPIO_ADVCFGRH_DLYPATH15        (0x1UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x10000000 */
+#define GPIO_ADVCFGRH_DE15             (0x2UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x20000000 */
+#define GPIO_ADVCFGRH_INVCLK15         (0x4UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x40000000 */
+#define GPIO_ADVCFGRH_RET15            (0x8UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x80000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT_Pos                    (2U)
+#define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
+#define HASH_CR_INIT                        HASH_CR_INIT_Msk
+#define HASH_CR_DMAE_Pos                    (3U)
+#define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
+#define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
+#define HASH_CR_DATATYPE_Pos                (4U)
+#define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
+#define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
+#define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos                    (6U)
+#define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
+#define HASH_CR_MODE                        HASH_CR_MODE_Msk
+#define HASH_CR_NBW_Pos                     (8U)
+#define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
+#define HASH_CR_NBW                         HASH_CR_NBW_Msk
+#define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
+#define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
+#define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
+#define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos                   (12U)
+#define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
+#define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
+#define HASH_CR_MDMAT_Pos                   (13U)
+#define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
+#define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
+#define HASH_CR_LKEY_Pos                    (16U)
+#define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
+#define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
+#define HASH_CR_ALGO_Pos                    (17U)
+#define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
+#define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
+#define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
+#define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
+#define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
+#define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBLW_Pos                   (0U)
+#define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
+#define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
+#define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
+#define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
+#define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
+#define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
+#define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos                   (8U)
+#define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
+#define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIE_Pos                  (0U)
+#define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
+#define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
+#define HASH_IMR_DCIE_Pos                   (1U)
+#define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
+#define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS_Pos                   (0U)
+#define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
+#define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
+#define HASH_SR_DCIS_Pos                    (1U)
+#define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
+#define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
+#define HASH_SR_DMAS_Pos                    (2U)
+#define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
+#define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
+#define HASH_SR_BUSY_Pos                    (3U)
+#define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
+#define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
+#define HASH_SR_NBWE_Pos                    (16U)
+#define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
+#define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
+#define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
+#define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
+#define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
+#define HASH_SR_DINNE_Pos                   (15U)
+#define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
+#define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
+#define HASH_SR_NBWP_Pos                    (9U)
+#define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
+#define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
+#define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
+#define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
+#define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos                      (0U)
+#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
+#define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos                    (1U)
+#define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
+#define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos                    (2U)
+#define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
+#define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos                  (3U)
+#define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos                  (4U)
+#define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
+#define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos                  (5U)
+#define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
+#define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos                    (6U)
+#define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos                   (7U)
+#define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos                     (8U)
+#define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
+#define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos                  (12U)
+#define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos                   (13U)
+#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
+#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos                 (14U)
+#define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos                 (15U)
+#define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos                     (16U)
+#define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
+#define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos               (17U)
+#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos                   (18U)
+#define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos                    (19U)
+#define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
+#define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos                  (20U)
+#define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos                  (21U)
+#define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos                 (22U)
+#define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos                   (23U)
+#define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
+#define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
+#define I2C_CR1_FMP_Pos                     (24U)
+#define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
+#define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
+#define I2C_CR1_ADDRACLR_Pos                (30U)
+#define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
+#define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
+#define I2C_CR1_STOPFACLR_Pos               (31U)
+#define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
+#define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos                    (0U)
+#define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
+#define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos                  (10U)
+#define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos                   (11U)
+#define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
+#define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos                 (12U)
+#define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos                   (13U)
+#define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
+#define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
+#define I2C_CR2_STOP_Pos                    (14U)
+#define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
+#define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos                    (15U)
+#define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
+#define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos                  (16U)
+#define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos                  (24U)
+#define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
+#define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos                 (25U)
+#define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos                 (26U)
+#define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos                    (0U)
+#define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
+#define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos                (10U)
+#define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos                  (15U)
+#define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos                    (1U)
+#define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
+#define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos                 (8U)
+#define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos              (8U)
+#define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos              (9U)
+#define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos              (8U)
+#define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos              (10U)
+#define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos              (8U)
+#define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos              (9U)
+#define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos              (8U)
+#define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos                  (15U)
+#define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos                (0U)
+#define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos                (8U)
+#define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos              (16U)
+#define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos              (20U)
+#define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos               (28U)
+#define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos              (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos                     (0U)
+#define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
+#define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos                    (1U)
+#define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
+#define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos                    (2U)
+#define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
+#define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos                    (3U)
+#define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
+#define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos                   (4U)
+#define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
+#define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos                   (5U)
+#define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
+#define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos                      (6U)
+#define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
+#define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos                     (7U)
+#define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
+#define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos                    (8U)
+#define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
+#define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
+#define I2C_ISR_ARLO_Pos                    (9U)
+#define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
+#define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos                     (10U)
+#define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
+#define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos                  (11U)
+#define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
+#define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos                 (12U)
+#define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos                   (13U)
+#define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
+#define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos                    (15U)
+#define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
+#define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
+#define I2C_ISR_DIR_Pos                     (16U)
+#define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
+#define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos                 (17U)
+#define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos                  (3U)
+#define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos                  (4U)
+#define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
+#define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos                  (5U)
+#define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
+#define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos                  (8U)
+#define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
+#define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos                  (9U)
+#define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos                   (10U)
+#define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos                   (11U)
+#define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
+#define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos                (12U)
+#define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos                 (13U)
+#define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos                    (0U)
+#define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
+#define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos                 (0U)
+#define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos                 (0U)
+#define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Improved Inter-integrated Circuit Interface (I3C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I3C_CR register  *********************/
+#define I3C_CR_DCNT_Pos                     (0U)
+#define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
+#define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
+#define I3C_CR_RNW_Pos                      (16U)
+#define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
+#define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
+#define I3C_CR_CCC_Pos                      (16U)
+#define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
+#define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
+#define I3C_CR_ADD_Pos                      (17U)
+#define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
+#define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
+#define I3C_CR_MTYPE_Pos                    (27U)
+#define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
+#define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
+#define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
+#define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
+#define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
+#define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
+#define I3C_CR_MEND_Pos                     (31U)
+#define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
+#define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
+
+/*******************  Bit definition for I3C_CFGR register  *******************/
+#define I3C_CFGR_EN_Pos                     (0U)
+#define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
+#define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
+#define I3C_CFGR_CRINIT_Pos                 (1U)
+#define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
+#define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
+#define I3C_CFGR_NOARBH_Pos                 (2U)
+#define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
+#define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
+#define I3C_CFGR_RSTPTRN_Pos                (3U)
+#define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
+#define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
+#define I3C_CFGR_EXITPTRN_Pos               (4U)
+#define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
+#define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
+#define I3C_CFGR_HKSDAEN_Pos                (5U)
+#define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
+#define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
+#define I3C_CFGR_HJACK_Pos                  (7U)
+#define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
+#define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
+#define I3C_CFGR_RXDMAEN_Pos                (8U)
+#define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
+#define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
+#define I3C_CFGR_RXFLUSH_Pos                (9U)
+#define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
+#define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
+#define I3C_CFGR_RXTHRES_Pos                (10U)
+#define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
+#define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
+#define I3C_CFGR_TXDMAEN_Pos                (12U)
+#define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
+#define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
+#define I3C_CFGR_TXFLUSH_Pos                (13U)
+#define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
+#define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
+#define I3C_CFGR_TXTHRES_Pos                (14U)
+#define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
+#define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
+#define I3C_CFGR_SDMAEN_Pos                 (16U)
+#define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
+#define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
+#define I3C_CFGR_SFLUSH_Pos                 (17U)
+#define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
+#define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
+#define I3C_CFGR_SMODE_Pos                  (18U)
+#define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
+#define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
+#define I3C_CFGR_TMODE_Pos                  (19U)
+#define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
+#define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
+#define I3C_CFGR_CDMAEN_Pos                 (20U)
+#define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
+#define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
+#define I3C_CFGR_CFLUSH_Pos                 (21U)
+#define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
+#define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
+#define I3C_CFGR_TSFSET_Pos                 (30U)
+#define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
+#define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
+
+/*******************  Bit definition for I3C_RDR register  ********************/
+#define I3C_RDR_RDB0_Pos                    (0U)
+#define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
+#define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
+
+/******************  Bit definition for I3C_RDWR register  ********************/
+#define I3C_RDWR_RDBx_Pos                   (0U)
+#define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
+#define I3C_RDWR_RDB0_Pos                   (0U)
+#define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
+#define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
+#define I3C_RDWR_RDB1_Pos                   (8U)
+#define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
+#define I3C_RDWR_RDB2_Pos                   (16U)
+#define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
+#define I3C_RDWR_RDB3_Pos                   (24U)
+#define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
+
+/*******************  Bit definition for I3C_TDR register  ********************/
+#define I3C_TDR_TDB0_Pos                    (0U)
+#define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
+#define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
+
+/******************  Bit definition for I3C_TDWR register  ********************/
+#define I3C_TDWR_TDBx_Pos                   (0U)
+#define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
+#define I3C_TDWR_TDB0_Pos                   (0U)
+#define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
+#define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
+#define I3C_TDWR_TDB1_Pos                   (8U)
+#define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
+#define I3C_TDWR_TDB2_Pos                   (16U)
+#define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
+#define I3C_TDWR_TDB3_Pos                   (24U)
+#define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
+
+/*******************  Bit definition for I3C_IBIDR register  ******************/
+#define I3C_IBIDR_IBIDBx_Pos                (0U)
+#define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
+#define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
+#define I3C_IBIDR_IBIDB0_Pos                (0U)
+#define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
+#define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
+#define I3C_IBIDR_IBIDB1_Pos                (8U)
+#define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
+#define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
+#define I3C_IBIDR_IBIDB2_Pos                (16U)
+#define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
+#define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
+#define I3C_IBIDR_IBIDB3_Pos                (24U)
+#define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
+#define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
+
+/******************  Bit definition for I3C_TGTTDR register  ******************/
+#define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
+#define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
+#define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
+#define I3C_TGTTDR_PRELOAD_Pos              (16U)
+#define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
+#define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
+
+/*******************  Bit definition for I3C_SR register  *********************/
+#define I3C_SR_XDCNT_Pos                    (0U)
+#define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
+#define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
+#define I3C_SR_ABT_Pos                      (17U)
+#define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
+#define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
+#define I3C_SR_DIR_Pos                      (18U)
+#define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
+#define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
+#define I3C_SR_MID_Pos                      (24U)
+#define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
+#define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
+
+/*******************  Bit definition for I3C_SER register  ********************/
+#define I3C_SER_CODERR_Pos                  (0U)
+#define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
+#define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
+#define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
+#define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
+#define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
+#define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
+#define I3C_SER_PERR_Pos                    (4U)
+#define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
+#define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
+#define I3C_SER_STALL_Pos                   (5U)
+#define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
+#define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
+#define I3C_SER_DOVR_Pos                    (6U)
+#define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
+#define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
+#define I3C_SER_COVR_Pos                    (7U)
+#define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
+#define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
+#define I3C_SER_ANACK_Pos                   (8U)
+#define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
+#define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
+#define I3C_SER_DNACK_Pos                   (9U)
+#define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
+#define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
+#define I3C_SER_DERR_Pos                    (10U)
+#define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
+#define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
+
+/*******************  Bit definition for I3C_RMR register  ********************/
+#define I3C_RMR_IBIRDCNT_Pos                (0U)
+#define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
+#define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
+#define I3C_RMR_RCODE_Pos                   (8U)
+#define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
+#define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
+#define I3C_RMR_RADD_Pos                    (17U)
+#define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
+#define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
+
+/*******************  Bit definition for I3C_EVR register  ********************/
+#define I3C_EVR_CFEF_Pos                    (0U)
+#define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
+#define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
+#define I3C_EVR_TXFEF_Pos                   (1U)
+#define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
+#define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
+#define I3C_EVR_CFNFF_Pos                   (2U)
+#define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
+#define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
+#define I3C_EVR_SFNEF_Pos                   (3U)
+#define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
+#define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
+#define I3C_EVR_TXFNFF_Pos                  (4U)
+#define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
+#define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
+#define I3C_EVR_RXFNEF_Pos                  (5U)
+#define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
+#define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
+#define I3C_EVR_TXLASTF_Pos                 (6U)
+#define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
+#define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
+#define I3C_EVR_RXLASTF_Pos                 (7U)
+#define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
+#define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
+#define I3C_EVR_FCF_Pos                     (9U)
+#define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
+#define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
+#define I3C_EVR_RXTGTENDF_Pos               (10U)
+#define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
+#define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
+#define I3C_EVR_ERRF_Pos                    (11U)
+#define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
+#define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
+#define I3C_EVR_IBIF_Pos                    (15U)
+#define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
+#define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
+#define I3C_EVR_IBIENDF_Pos                 (16U)
+#define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
+#define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
+#define I3C_EVR_CRF_Pos                     (17U)
+#define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
+#define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
+#define I3C_EVR_CRUPDF_Pos                  (18U)
+#define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
+#define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
+#define I3C_EVR_HJF_Pos                     (19U)
+#define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
+#define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
+#define I3C_EVR_WKPF_Pos                    (21U)
+#define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
+#define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
+#define I3C_EVR_GETF_Pos                    (22U)
+#define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
+#define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
+#define I3C_EVR_STAF_Pos                    (23U)
+#define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
+#define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
+#define I3C_EVR_DAUPDF_Pos                  (24U)
+#define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
+#define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
+#define I3C_EVR_MWLUPDF_Pos                 (25U)
+#define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
+#define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
+#define I3C_EVR_MRLUPDF_Pos                 (26U)
+#define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
+#define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
+#define I3C_EVR_RSTF_Pos                    (27U)
+#define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
+#define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
+#define I3C_EVR_ASUPDF_Pos                  (28U)
+#define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
+#define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
+#define I3C_EVR_INTUPDF_Pos                 (29U)
+#define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
+#define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
+#define I3C_EVR_DEFF_Pos                    (30U)
+#define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
+#define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
+#define I3C_EVR_GRPF_Pos                    (31U)
+#define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
+#define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
+
+/*******************  Bit definition for I3C_IER register  ********************/
+#define I3C_IER_CFNFIE_Pos                  (2U)
+#define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
+#define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
+#define I3C_IER_SFNEIE_Pos                  (3U)
+#define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
+#define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
+#define I3C_IER_TXFNFIE_Pos                 (4U)
+#define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
+#define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
+#define I3C_IER_RXFNEIE_Pos                 (5U)
+#define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
+#define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
+#define I3C_IER_FCIE_Pos                    (9U)
+#define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
+#define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
+#define I3C_IER_RXTGTENDIE_Pos              (10U)
+#define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
+#define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
+#define I3C_IER_ERRIE_Pos                   (11U)
+#define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
+#define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
+#define I3C_IER_IBIIE_Pos                   (15U)
+#define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
+#define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
+#define I3C_IER_IBIENDIE_Pos                (16U)
+#define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
+#define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
+#define I3C_IER_CRIE_Pos                    (17U)
+#define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
+#define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
+#define I3C_IER_CRUPDIE_Pos                 (18U)
+#define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
+#define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
+#define I3C_IER_HJIE_Pos                    (19U)
+#define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
+#define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
+#define I3C_IER_WKPIE_Pos                   (21U)
+#define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
+#define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
+#define I3C_IER_GETIE_Pos                   (22U)
+#define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
+#define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
+#define I3C_IER_STAIE_Pos                   (23U)
+#define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
+#define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
+#define I3C_IER_DAUPDIE_Pos                 (24U)
+#define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
+#define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
+#define I3C_IER_MWLUPDIE_Pos                (25U)
+#define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
+#define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
+#define I3C_IER_MRLUPDIE_Pos                (26U)
+#define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
+#define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
+#define I3C_IER_RSTIE_Pos                   (27U)
+#define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
+#define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
+#define I3C_IER_ASUPDIE_Pos                 (28U)
+#define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
+#define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
+#define I3C_IER_INTUPDIE_Pos                (29U)
+#define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
+#define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
+#define I3C_IER_DEFIE_Pos                   (30U)
+#define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
+#define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
+#define I3C_IER_GRPIE_Pos                   (31U)
+#define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
+#define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
+
+/*******************  Bit definition for I3C_CEVR register  *******************/
+#define I3C_CEVR_CFCF_Pos                   (9U)
+#define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
+#define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
+#define I3C_CEVR_CRXTGTENDF_Pos             (10U)
+#define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
+#define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
+#define I3C_CEVR_CERRF_Pos                  (11U)
+#define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
+#define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
+#define I3C_CEVR_CIBIF_Pos                  (15U)
+#define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
+#define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
+#define I3C_CEVR_CIBIENDF_Pos               (16U)
+#define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
+#define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
+#define I3C_CEVR_CCRF_Pos                   (17U)
+#define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
+#define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
+#define I3C_CEVR_CCRUPDF_Pos                (18U)
+#define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
+#define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
+#define I3C_CEVR_CHJF_Pos                   (19U)
+#define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
+#define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
+#define I3C_CEVR_CWKPF_Pos                  (21U)
+#define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
+#define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
+#define I3C_CEVR_CGETF_Pos                  (22U)
+#define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
+#define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
+#define I3C_CEVR_CSTAF_Pos                  (23U)
+#define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
+#define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
+#define I3C_CEVR_CDAUPDF_Pos                (24U)
+#define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
+#define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
+#define I3C_CEVR_CMWLUPDF_Pos               (25U)
+#define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
+#define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
+#define I3C_CEVR_CMRLUPDF_Pos               (26U)
+#define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
+#define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
+#define I3C_CEVR_CRSTF_Pos                  (27U)
+#define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
+#define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
+#define I3C_CEVR_CASUPDF_Pos                (28U)
+#define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
+#define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
+#define I3C_CEVR_CINTUPDF_Pos               (29U)
+#define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
+#define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
+#define I3C_CEVR_CDEFF_Pos                  (30U)
+#define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
+#define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
+#define I3C_CEVR_CGRPF_Pos                  (31U)
+#define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
+#define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
+
+/******************  Bit definition for I3C_DEVR0 register  *******************/
+#define I3C_DEVR0_DAVAL_Pos                 (0U)
+#define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
+#define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
+#define I3C_DEVR0_DA_Pos                    (1U)
+#define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
+#define I3C_DEVR0_IBIEN_Pos                 (16U)
+#define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
+#define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
+#define I3C_DEVR0_CREN_Pos                  (17U)
+#define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
+#define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
+#define I3C_DEVR0_HJEN_Pos                  (19U)
+#define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
+#define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
+#define I3C_DEVR0_AS_Pos                    (20U)
+#define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
+#define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
+#define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
+#define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
+#define I3C_DEVR0_RSTACT_Pos                (22U)
+#define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
+#define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
+#define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
+#define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
+#define I3C_DEVR0_RSTVAL_Pos                (24U)
+#define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
+#define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
+
+/******************  Bit definition for I3C_DEVRX register  *******************/
+#define I3C_DEVRX_DA_Pos                    (1U)
+#define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
+#define I3C_DEVRX_IBIACK_Pos                (16U)
+#define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
+#define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
+#define I3C_DEVRX_CRACK_Pos                 (17U)
+#define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
+#define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
+#define I3C_DEVRX_IBIDEN_Pos                (18U)
+#define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
+#define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
+#define I3C_DEVRX_SUSP_Pos                  (19U)
+#define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
+#define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
+#define I3C_DEVRX_DIS_Pos                   (31U)
+#define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
+#define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
+
+/******************  Bit definition for I3C_MAXRLR register  ******************/
+#define I3C_MAXRLR_MRL_Pos                  (0U)
+#define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
+#define I3C_MAXRLR_IBIP_Pos                 (16U)
+#define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
+#define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
+#define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
+#define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
+#define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
+
+/******************  Bit definition for I3C_MAXWLR register  ******************/
+#define I3C_MAXWLR_MWL_Pos                  (0U)
+#define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
+
+/****************  Bit definition for I3C_TIMINGR0 register  ******************/
+#define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
+#define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
+#define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
+#define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
+#define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
+#define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
+#define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
+#define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
+#define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
+#define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
+#define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
+#define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
+
+/****************  Bit definition for I3C_TIMINGR1 register  ******************/
+#define I3C_TIMINGR1_AVAL_Pos               (0U)
+#define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
+#define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
+#define I3C_TIMINGR1_ASNCR_Pos              (8U)
+#define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
+#define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
+#define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
+#define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
+#define I3C_TIMINGR1_FREE_Pos               (16U)
+#define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
+#define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
+#define I3C_TIMINGR1_SDA_HD_Pos             (28U)
+#define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
+#define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
+
+/****************  Bit definition for I3C_TIMINGR2 register  ******************/
+#define I3C_TIMINGR2_STALLT_Pos             (0U)
+#define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x0000001 */
+#define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
+#define I3C_TIMINGR2_STALLD_Pos             (1U)
+#define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x0000002 */
+#define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
+#define I3C_TIMINGR2_STALLC_Pos             (2U)
+#define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x0000004 */
+#define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
+#define I3C_TIMINGR2_STALLA_Pos             (3U)
+#define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x0000008 */
+#define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
+#define I3C_TIMINGR2_STALL_Pos              (8U)
+#define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x000FF00 */
+#define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
+
+/*******************  Bit definition for I3C_BCR register  ********************/
+#define I3C_BCR_BCR_Pos                     (0U)
+#define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
+#define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
+#define I3C_BCR_BCR0_Pos                    (0U)
+#define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
+#define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
+#define I3C_BCR_BCR1_Pos                    (1U)
+#define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
+#define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
+#define I3C_BCR_BCR2_Pos                    (2U)
+#define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
+#define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
+#define I3C_BCR_BCR3_Pos                    (3U)
+#define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
+#define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
+#define I3C_BCR_BCR4_Pos                    (4U)
+#define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
+#define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
+#define I3C_BCR_BCR5_Pos                    (5U)
+#define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
+#define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
+#define I3C_BCR_BCR6_Pos                    (6U)
+#define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
+#define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
+
+/*******************  Bit definition for I3C_DCR register  ********************/
+#define I3C_DCR_DCR_Pos                     (0U)
+#define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x00000FF */
+#define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
+
+/*****************  Bit definition for I3C_GETCAPR register  ******************/
+#define I3C_GETCAPR_CAPPEND_Pos             (14U)
+#define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
+#define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
+
+/*****************  Bit definition for I3C_CRCAPR register  *******************/
+#define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
+#define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
+#define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
+#define I3C_CRCAPR_CAPGRP_Pos               (9U)
+#define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
+#define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
+
+/****************  Bit definition for I3C_GETMXDSR register  ******************/
+#define I3C_GETMXDSR_HOFFAS_Pos             (0U)
+#define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
+#define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
+#define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
+#define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
+#define I3C_GETMXDSR_FMT_Pos                (8U)
+#define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
+#define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
+#define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
+#define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
+#define I3C_GETMXDSR_RDTURN_Pos             (16U)
+#define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
+#define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
+#define I3C_GETMXDSR_TSCO_Pos               (24U)
+#define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
+#define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
+
+/******************  Bit definition for I3C_EPIDR register  *******************/
+#define I3C_EPIDR_MIPIID_Pos                (12U)
+#define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
+#define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
+#define I3C_EPIDR_IDTSEL_Pos                (16U)
+#define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
+#define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
+#define I3C_EPIDR_MIPIMID_Pos               (17U)
+#define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
+#define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Illegal Access Controller (IAC)                                */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for IAC_IER0 register *******************/
+#define IAC_IER0_IAIE0_Pos            (0U)
+#define IAC_IER0_IAIE0_Msk            (0x1UL << IAC_IER0_IAIE0_Pos)              /*!< 0x00000001 */
+#define IAC_IER0_IAIE0                IAC_IER0_IAIE0_Msk
+#define IAC_IER0_IAIE1_Pos            (1U)
+#define IAC_IER0_IAIE1_Msk            (0x1UL << IAC_IER0_IAIE1_Pos)              /*!< 0x00000002 */
+#define IAC_IER0_IAIE1                IAC_IER0_IAIE1_Msk
+#define IAC_IER0_IAIE2_Pos            (2U)
+#define IAC_IER0_IAIE2_Msk            (0x1UL << IAC_IER0_IAIE2_Pos)              /*!< 0x00000004 */
+#define IAC_IER0_IAIE2                IAC_IER0_IAIE2_Msk
+#define IAC_IER0_IAIE3_Pos            (3U)
+#define IAC_IER0_IAIE3_Msk            (0x1UL << IAC_IER0_IAIE3_Pos)              /*!< 0x00000008 */
+#define IAC_IER0_IAIE3                IAC_IER0_IAIE3_Msk
+#define IAC_IER0_IAIE4_Pos            (4U)
+#define IAC_IER0_IAIE4_Msk            (0x1UL << IAC_IER0_IAIE4_Pos)              /*!< 0x00000010 */
+#define IAC_IER0_IAIE4                IAC_IER0_IAIE4_Msk
+#define IAC_IER0_IAIE5_Pos            (5U)
+#define IAC_IER0_IAIE5_Msk            (0x1UL << IAC_IER0_IAIE5_Pos)              /*!< 0x00000020 */
+#define IAC_IER0_IAIE5                IAC_IER0_IAIE5_Msk
+#define IAC_IER0_IAIE6_Pos            (6U)
+#define IAC_IER0_IAIE6_Msk            (0x1UL << IAC_IER0_IAIE6_Pos)              /*!< 0x00000040 */
+#define IAC_IER0_IAIE6                IAC_IER0_IAIE6_Msk
+#define IAC_IER0_IAIE8_Pos            (8U)
+#define IAC_IER0_IAIE8_Msk            (0x1UL << IAC_IER0_IAIE8_Pos)              /*!< 0x00000100 */
+#define IAC_IER0_IAIE8                IAC_IER0_IAIE8_Msk
+#define IAC_IER0_IAIE9_Pos            (9U)
+#define IAC_IER0_IAIE9_Msk            (0x1UL << IAC_IER0_IAIE9_Pos)              /*!< 0x00000200 */
+#define IAC_IER0_IAIE9                IAC_IER0_IAIE9_Msk
+#define IAC_IER0_IAIE10_Pos           (10U)
+#define IAC_IER0_IAIE10_Msk           (0x1UL << IAC_IER0_IAIE10_Pos)             /*!< 0x00000400 */
+#define IAC_IER0_IAIE10               IAC_IER0_IAIE10_Msk
+#define IAC_IER0_IAIE11_Pos           (11U)
+#define IAC_IER0_IAIE11_Msk           (0x1UL << IAC_IER0_IAIE11_Pos)             /*!< 0x00000800 */
+#define IAC_IER0_IAIE11               IAC_IER0_IAIE11_Msk
+#define IAC_IER0_IAIE12_Pos           (12U)
+#define IAC_IER0_IAIE12_Msk           (0x1UL << IAC_IER0_IAIE12_Pos)             /*!< 0x00001000 */
+#define IAC_IER0_IAIE12               IAC_IER0_IAIE12_Msk
+#define IAC_IER0_IAIE13_Pos           (13U)
+#define IAC_IER0_IAIE13_Msk           (0x1UL << IAC_IER0_IAIE13_Pos)             /*!< 0x00002000 */
+#define IAC_IER0_IAIE13               IAC_IER0_IAIE13_Msk
+#define IAC_IER0_IAIE14_Pos           (14U)
+#define IAC_IER0_IAIE14_Msk           (0x1UL << IAC_IER0_IAIE14_Pos)             /*!< 0x00004000 */
+#define IAC_IER0_IAIE14               IAC_IER0_IAIE14_Msk
+#define IAC_IER0_IAIE15_Pos           (15U)
+#define IAC_IER0_IAIE15_Msk           (0x1UL << IAC_IER0_IAIE15_Pos)             /*!< 0x00008000 */
+#define IAC_IER0_IAIE15               IAC_IER0_IAIE15_Msk
+#define IAC_IER0_IAIE16_Pos           (16U)
+#define IAC_IER0_IAIE16_Msk           (0x1UL << IAC_IER0_IAIE16_Pos)             /*!< 0x00010000 */
+#define IAC_IER0_IAIE16               IAC_IER0_IAIE16_Msk
+#define IAC_IER0_IAIE17_Pos           (17U)
+#define IAC_IER0_IAIE17_Msk           (0x1UL << IAC_IER0_IAIE17_Pos)             /*!< 0x00020000 */
+#define IAC_IER0_IAIE17               IAC_IER0_IAIE17_Msk
+#define IAC_IER0_IAIE18_Pos           (18U)
+#define IAC_IER0_IAIE18_Msk           (0x1UL << IAC_IER0_IAIE18_Pos)             /*!< 0x00040000 */
+#define IAC_IER0_IAIE18               IAC_IER0_IAIE18_Msk
+#define IAC_IER0_IAIE19_Pos           (19U)
+#define IAC_IER0_IAIE19_Msk           (0x1UL << IAC_IER0_IAIE19_Pos)             /*!< 0x00080000 */
+#define IAC_IER0_IAIE19               IAC_IER0_IAIE19_Msk
+#define IAC_IER0_IAIE20_Pos           (20U)
+#define IAC_IER0_IAIE20_Msk           (0x1UL << IAC_IER0_IAIE20_Pos)             /*!< 0x00100000 */
+#define IAC_IER0_IAIE20               IAC_IER0_IAIE20_Msk
+#define IAC_IER0_IAIE21_Pos           (21U)
+#define IAC_IER0_IAIE21_Msk           (0x1UL << IAC_IER0_IAIE21_Pos)             /*!< 0x00200000 */
+#define IAC_IER0_IAIE21               IAC_IER0_IAIE21_Msk
+#define IAC_IER0_IAIE22_Pos           (22U)
+#define IAC_IER0_IAIE22_Msk           (0x1UL << IAC_IER0_IAIE22_Pos)             /*!< 0x00400000 */
+#define IAC_IER0_IAIE22               IAC_IER0_IAIE22_Msk
+#define IAC_IER0_IAIE23_Pos           (23U)
+#define IAC_IER0_IAIE23_Msk           (0x1UL << IAC_IER0_IAIE23_Pos)             /*!< 0x00800000 */
+#define IAC_IER0_IAIE23               IAC_IER0_IAIE23_Msk
+#define IAC_IER0_IAIE24_Pos           (24U)
+#define IAC_IER0_IAIE24_Msk           (0x1UL << IAC_IER0_IAIE24_Pos)             /*!< 0x01000000 */
+#define IAC_IER0_IAIE24               IAC_IER0_IAIE24_Msk
+#define IAC_IER0_IAIE25_Pos           (25U)
+#define IAC_IER0_IAIE25_Msk           (0x1UL << IAC_IER0_IAIE25_Pos)             /*!< 0x02000000 */
+#define IAC_IER0_IAIE25               IAC_IER0_IAIE25_Msk
+#define IAC_IER0_IAIE26_Pos           (26U)
+#define IAC_IER0_IAIE26_Msk           (0x1UL << IAC_IER0_IAIE26_Pos)             /*!< 0x04000000 */
+#define IAC_IER0_IAIE26               IAC_IER0_IAIE26_Msk
+#define IAC_IER0_IAIE27_Pos           (27U)
+#define IAC_IER0_IAIE27_Msk           (0x1UL << IAC_IER0_IAIE27_Pos)             /*!< 0x08000000 */
+#define IAC_IER0_IAIE27               IAC_IER0_IAIE27_Msk
+#define IAC_IER0_IAIE28_Pos           (28U)
+#define IAC_IER0_IAIE28_Msk           (0x1UL << IAC_IER0_IAIE28_Pos)             /*!< 0x10000000 */
+#define IAC_IER0_IAIE28               IAC_IER0_IAIE28_Msk
+#define IAC_IER0_IAIE29_Pos           (29U)
+#define IAC_IER0_IAIE29_Msk           (0x1UL << IAC_IER0_IAIE29_Pos)             /*!< 0x20000000 */
+#define IAC_IER0_IAIE29               IAC_IER0_IAIE29_Msk
+#define IAC_IER0_IAIE30_Pos           (30U)
+#define IAC_IER0_IAIE30_Msk           (0x1UL << IAC_IER0_IAIE30_Pos)             /*!< 0x40000000 */
+#define IAC_IER0_IAIE30               IAC_IER0_IAIE30_Msk
+#define IAC_IER0_IAIE31_Pos           (31U)
+#define IAC_IER0_IAIE31_Msk           (0x1UL << IAC_IER0_IAIE31_Pos)             /*!< 0x80000000 */
+#define IAC_IER0_IAIE31               IAC_IER0_IAIE31_Msk
+
+/*******************  Bits definition for IAC_IER1 register *******************/
+#define IAC_IER1_IAIE32_Pos           (0U)
+#define IAC_IER1_IAIE32_Msk           (0x1UL << IAC_IER1_IAIE32_Pos)             /*!< 0x00000001 */
+#define IAC_IER1_IAIE32               IAC_IER1_IAIE32_Msk
+#define IAC_IER1_IAIE33_Pos           (1U)
+#define IAC_IER1_IAIE33_Msk           (0x1UL << IAC_IER1_IAIE33_Pos)             /*!< 0x00000002 */
+#define IAC_IER1_IAIE33               IAC_IER1_IAIE33_Msk
+#define IAC_IER1_IAIE34_Pos           (2U)
+#define IAC_IER1_IAIE34_Msk           (0x1UL << IAC_IER1_IAIE34_Pos)             /*!< 0x00000004 */
+#define IAC_IER1_IAIE34               IAC_IER1_IAIE34_Msk
+#define IAC_IER1_IAIE35_Pos           (3U)
+#define IAC_IER1_IAIE35_Msk           (0x1UL << IAC_IER1_IAIE35_Pos)             /*!< 0x00000008 */
+#define IAC_IER1_IAIE35               IAC_IER1_IAIE35_Msk
+#define IAC_IER1_IAIE36_Pos           (4U)
+#define IAC_IER1_IAIE36_Msk           (0x1UL << IAC_IER1_IAIE36_Pos)             /*!< 0x00000010 */
+#define IAC_IER1_IAIE36               IAC_IER1_IAIE36_Msk
+#define IAC_IER1_IAIE37_Pos           (5U)
+#define IAC_IER1_IAIE37_Msk           (0x1UL << IAC_IER1_IAIE37_Pos)             /*!< 0x00000020 */
+#define IAC_IER1_IAIE37               IAC_IER1_IAIE37_Msk
+#define IAC_IER1_IAIE38_Pos           (6U)
+#define IAC_IER1_IAIE38_Msk           (0x1UL << IAC_IER1_IAIE38_Pos)             /*!< 0x00000040 */
+#define IAC_IER1_IAIE38               IAC_IER1_IAIE38_Msk
+#define IAC_IER1_IAIE39_Pos           (7U)
+#define IAC_IER1_IAIE39_Msk           (0x1UL << IAC_IER1_IAIE39_Pos)             /*!< 0x00000080 */
+#define IAC_IER1_IAIE39               IAC_IER1_IAIE39_Msk
+#define IAC_IER1_IAIE40_Pos           (8U)
+#define IAC_IER1_IAIE40_Msk           (0x1UL << IAC_IER1_IAIE40_Pos)             /*!< 0x00000100 */
+#define IAC_IER1_IAIE40               IAC_IER1_IAIE40_Msk
+#define IAC_IER1_IAIE41_Pos           (9U)
+#define IAC_IER1_IAIE41_Msk           (0x1UL << IAC_IER1_IAIE41_Pos)             /*!< 0x00000200 */
+#define IAC_IER1_IAIE41               IAC_IER1_IAIE41_Msk
+#define IAC_IER1_IAIE42_Pos           (10U)
+#define IAC_IER1_IAIE42_Msk           (0x1UL << IAC_IER1_IAIE42_Pos)             /*!< 0x00000400 */
+#define IAC_IER1_IAIE42               IAC_IER1_IAIE42_Msk
+#define IAC_IER1_IAIE43_Pos           (11U)
+#define IAC_IER1_IAIE43_Msk           (0x1UL << IAC_IER1_IAIE43_Pos)             /*!< 0x00000800 */
+#define IAC_IER1_IAIE43               IAC_IER1_IAIE43_Msk
+#define IAC_IER1_IAIE44_Pos           (12U)
+#define IAC_IER1_IAIE44_Msk           (0x1UL << IAC_IER1_IAIE44_Pos)             /*!< 0x00001000 */
+#define IAC_IER1_IAIE44               IAC_IER1_IAIE44_Msk
+#define IAC_IER1_IAIE45_Pos           (13U)
+#define IAC_IER1_IAIE45_Msk           (0x1UL << IAC_IER1_IAIE45_Pos)             /*!< 0x00002000 */
+#define IAC_IER1_IAIE45               IAC_IER1_IAIE45_Msk
+#define IAC_IER1_IAIE46_Pos           (14U)
+#define IAC_IER1_IAIE46_Msk           (0x1UL << IAC_IER1_IAIE46_Pos)             /*!< 0x00004000 */
+#define IAC_IER1_IAIE46               IAC_IER1_IAIE46_Msk
+#define IAC_IER1_IAIE47_Pos           (15U)
+#define IAC_IER1_IAIE47_Msk           (0x1UL << IAC_IER1_IAIE47_Pos)             /*!< 0x00008000 */
+#define IAC_IER1_IAIE47               IAC_IER1_IAIE47_Msk
+#define IAC_IER1_IAIE48_Pos           (16U)
+#define IAC_IER1_IAIE48_Msk           (0x1UL << IAC_IER1_IAIE48_Pos)             /*!< 0x00010000 */
+#define IAC_IER1_IAIE48               IAC_IER1_IAIE48_Msk
+#define IAC_IER1_IAIE49_Pos           (17U)
+#define IAC_IER1_IAIE49_Msk           (0x1UL << IAC_IER1_IAIE49_Pos)             /*!< 0x00020000 */
+#define IAC_IER1_IAIE49               IAC_IER1_IAIE49_Msk
+#define IAC_IER1_IAIE50_Pos           (18U)
+#define IAC_IER1_IAIE50_Msk           (0x1UL << IAC_IER1_IAIE50_Pos)             /*!< 0x00040000 */
+#define IAC_IER1_IAIE50               IAC_IER1_IAIE50_Msk
+#define IAC_IER1_IAIE51_Pos           (19U)
+#define IAC_IER1_IAIE51_Msk           (0x1UL << IAC_IER1_IAIE51_Pos)             /*!< 0x00080000 */
+#define IAC_IER1_IAIE51               IAC_IER1_IAIE51_Msk
+#define IAC_IER1_IAIE52_Pos           (20U)
+#define IAC_IER1_IAIE52_Msk           (0x1UL << IAC_IER1_IAIE52_Pos)             /*!< 0x00100000 */
+#define IAC_IER1_IAIE52               IAC_IER1_IAIE52_Msk
+#define IAC_IER1_IAIE53_Pos           (21U)
+#define IAC_IER1_IAIE53_Msk           (0x1UL << IAC_IER1_IAIE53_Pos)             /*!< 0x00200000 */
+#define IAC_IER1_IAIE53               IAC_IER1_IAIE53_Msk
+#define IAC_IER1_IAIE54_Pos           (22U)
+#define IAC_IER1_IAIE54_Msk           (0x1UL << IAC_IER1_IAIE54_Pos)             /*!< 0x00400000 */
+#define IAC_IER1_IAIE54               IAC_IER1_IAIE54_Msk
+#define IAC_IER1_IAIE55_Pos           (23U)
+#define IAC_IER1_IAIE55_Msk           (0x1UL << IAC_IER1_IAIE55_Pos)             /*!< 0x00800000 */
+#define IAC_IER1_IAIE55               IAC_IER1_IAIE55_Msk
+#define IAC_IER1_IAIE56_Pos           (24U)
+#define IAC_IER1_IAIE56_Msk           (0x1UL << IAC_IER1_IAIE56_Pos)             /*!< 0x01000000 */
+#define IAC_IER1_IAIE56               IAC_IER1_IAIE56_Msk
+#define IAC_IER1_IAIE57_Pos           (25U)
+#define IAC_IER1_IAIE57_Msk           (0x1UL << IAC_IER1_IAIE57_Pos)             /*!< 0x02000000 */
+#define IAC_IER1_IAIE57               IAC_IER1_IAIE57_Msk
+#define IAC_IER1_IAIE58_Pos           (26U)
+#define IAC_IER1_IAIE58_Msk           (0x1UL << IAC_IER1_IAIE58_Pos)             /*!< 0x04000000 */
+#define IAC_IER1_IAIE58               IAC_IER1_IAIE58_Msk
+#define IAC_IER1_IAIE60_Pos           (28U)
+#define IAC_IER1_IAIE60_Msk           (0x1UL << IAC_IER1_IAIE60_Pos)             /*!< 0x10000000 */
+#define IAC_IER1_IAIE60               IAC_IER1_IAIE60_Msk
+#define IAC_IER1_IAIE61_Pos           (29U)
+#define IAC_IER1_IAIE61_Msk           (0x1UL << IAC_IER1_IAIE61_Pos)             /*!< 0x20000000 */
+#define IAC_IER1_IAIE61               IAC_IER1_IAIE61_Msk
+#define IAC_IER1_IAIE62_Pos           (30U)
+#define IAC_IER1_IAIE62_Msk           (0x1UL << IAC_IER1_IAIE62_Pos)             /*!< 0x40000000 */
+#define IAC_IER1_IAIE62               IAC_IER1_IAIE62_Msk
+
+/*******************  Bits definition for IAC_IER2 register *******************/
+#define IAC_IER2_IAIE64_Pos           (0U)
+#define IAC_IER2_IAIE64_Msk           (0x1UL << IAC_IER2_IAIE64_Pos)             /*!< 0x00000001 */
+#define IAC_IER2_IAIE64               IAC_IER2_IAIE64_Msk
+#define IAC_IER2_IAIE65_Pos           (1U)
+#define IAC_IER2_IAIE65_Msk           (0x1UL << IAC_IER2_IAIE65_Pos)             /*!< 0x00000002 */
+#define IAC_IER2_IAIE65               IAC_IER2_IAIE65_Msk
+#define IAC_IER2_IAIE67_Pos           (3U)
+#define IAC_IER2_IAIE67_Msk           (0x1UL << IAC_IER2_IAIE67_Pos)             /*!< 0x00000008 */
+#define IAC_IER2_IAIE67               IAC_IER2_IAIE67_Msk
+#define IAC_IER2_IAIE68_Pos           (4U)
+#define IAC_IER2_IAIE68_Msk           (0x1UL << IAC_IER2_IAIE68_Pos)             /*!< 0x00000010 */
+#define IAC_IER2_IAIE68               IAC_IER2_IAIE68_Msk
+#define IAC_IER2_IAIE69_Pos           (5U)
+#define IAC_IER2_IAIE69_Msk           (0x1UL << IAC_IER2_IAIE69_Pos)             /*!< 0x00000020 */
+#define IAC_IER2_IAIE69               IAC_IER2_IAIE69_Msk
+#define IAC_IER2_IAIE76_Pos           (12U)
+#define IAC_IER2_IAIE76_Msk           (0x1UL << IAC_IER2_IAIE76_Pos)             /*!< 0x00001000 */
+#define IAC_IER2_IAIE76               IAC_IER2_IAIE76_Msk
+#define IAC_IER2_IAIE77_Pos           (13U)
+#define IAC_IER2_IAIE77_Msk           (0x1UL << IAC_IER2_IAIE77_Pos)             /*!< 0x00002000 */
+#define IAC_IER2_IAIE77               IAC_IER2_IAIE77_Msk
+#define IAC_IER2_IAIE78_Pos           (14U)
+#define IAC_IER2_IAIE78_Msk           (0x1UL << IAC_IER2_IAIE78_Pos)             /*!< 0x00004000 */
+#define IAC_IER2_IAIE78               IAC_IER2_IAIE78_Msk
+#define IAC_IER2_IAIE79_Pos           (15U)
+#define IAC_IER2_IAIE79_Msk           (0x1UL << IAC_IER2_IAIE79_Pos)             /*!< 0x00008000 */
+#define IAC_IER2_IAIE79               IAC_IER2_IAIE79_Msk
+#define IAC_IER2_IAIE80_Pos           (16U)
+#define IAC_IER2_IAIE80_Msk           (0x1UL << IAC_IER2_IAIE80_Pos)             /*!< 0x00010000 */
+#define IAC_IER2_IAIE80               IAC_IER2_IAIE80_Msk
+#define IAC_IER2_IAIE81_Pos           (17U)
+#define IAC_IER2_IAIE81_Msk           (0x1UL << IAC_IER2_IAIE81_Pos)             /*!< 0x00020000 */
+#define IAC_IER2_IAIE81               IAC_IER2_IAIE81_Msk
+#define IAC_IER2_IAIE82_Pos           (18U)
+#define IAC_IER2_IAIE82_Msk           (0x1UL << IAC_IER2_IAIE82_Pos)             /*!< 0x00040000 */
+#define IAC_IER2_IAIE82               IAC_IER2_IAIE82_Msk
+#define IAC_IER2_IAIE83_Pos           (19U)
+#define IAC_IER2_IAIE83_Msk           (0x1UL << IAC_IER2_IAIE83_Pos)             /*!< 0x00080000 */
+#define IAC_IER2_IAIE83               IAC_IER2_IAIE83_Msk
+#define IAC_IER2_IAIE84_Pos           (20U)
+#define IAC_IER2_IAIE84_Msk           (0x1UL << IAC_IER2_IAIE84_Pos)             /*!< 0x00100000 */
+#define IAC_IER2_IAIE84               IAC_IER2_IAIE84_Msk
+#define IAC_IER2_IAIE86_Pos           (22U)
+#define IAC_IER2_IAIE86_Msk           (0x1UL << IAC_IER2_IAIE86_Pos)             /*!< 0x00400000 */
+#define IAC_IER2_IAIE86               IAC_IER2_IAIE86_Msk
+#define IAC_IER2_IAIE87_Pos           (23U)
+#define IAC_IER2_IAIE87_Msk           (0x1UL << IAC_IER2_IAIE87_Pos)             /*!< 0x00800000 */
+#define IAC_IER2_IAIE87               IAC_IER2_IAIE87_Msk
+#define IAC_IER2_IAIE88_Pos           (24U)
+#define IAC_IER2_IAIE88_Msk           (0x1UL << IAC_IER2_IAIE88_Pos)             /*!< 0x01000000 */
+#define IAC_IER2_IAIE88               IAC_IER2_IAIE88_Msk
+#define IAC_IER2_IAIE89_Pos           (25U)
+#define IAC_IER2_IAIE89_Msk           (0x1UL << IAC_IER2_IAIE89_Pos)             /*!< 0x02000000 */
+#define IAC_IER2_IAIE89               IAC_IER2_IAIE89_Msk
+#define IAC_IER2_IAIE90_Pos           (26U)
+#define IAC_IER2_IAIE90_Msk           (0x1UL << IAC_IER2_IAIE90_Pos)             /*!< 0x04000000 */
+#define IAC_IER2_IAIE90               IAC_IER2_IAIE90_Msk
+#define IAC_IER2_IAIE92_Pos           (28U)
+#define IAC_IER2_IAIE92_Msk           (0x1UL << IAC_IER2_IAIE92_Pos)             /*!< 0x10000000 */
+#define IAC_IER2_IAIE92               IAC_IER2_IAIE92_Msk
+#define IAC_IER2_IAIE93_Pos           (29U)
+#define IAC_IER2_IAIE93_Msk           (0x1UL << IAC_IER2_IAIE93_Pos)             /*!< 0x20000000 */
+#define IAC_IER2_IAIE93               IAC_IER2_IAIE93_Msk
+#define IAC_IER2_IAIE94_Pos           (30U)
+#define IAC_IER2_IAIE94_Msk           (0x1UL << IAC_IER2_IAIE94_Pos)             /*!< 0x40000000 */
+#define IAC_IER2_IAIE94               IAC_IER2_IAIE94_Msk
+#define IAC_IER2_IAIE95_Pos           (31U)
+#define IAC_IER2_IAIE95_Msk           (0x1UL << IAC_IER2_IAIE95_Pos)             /*!< 0x80000000 */
+#define IAC_IER2_IAIE95               IAC_IER2_IAIE95_Msk
+
+/*******************  Bits definition for IAC_IER3 register *******************/
+#define IAC_IER3_IAIE96_Pos           (0U)
+#define IAC_IER3_IAIE96_Msk           (0x1UL << IAC_IER3_IAIE96_Pos)             /*!< 0x00000001 */
+#define IAC_IER3_IAIE96               IAC_IER3_IAIE96_Msk
+#define IAC_IER3_IAIE97_Pos           (1U)
+#define IAC_IER3_IAIE97_Msk           (0x1UL << IAC_IER3_IAIE97_Pos)             /*!< 0x00000002 */
+#define IAC_IER3_IAIE97               IAC_IER3_IAIE97_Msk
+#define IAC_IER3_IAIE98_Pos           (2U)
+#define IAC_IER3_IAIE98_Msk           (0x1UL << IAC_IER3_IAIE98_Pos)             /*!< 0x00000004 */
+#define IAC_IER3_IAIE98               IAC_IER3_IAIE98_Msk
+#define IAC_IER3_IAIE99_Pos           (3U)
+#define IAC_IER3_IAIE99_Msk           (0x1UL << IAC_IER3_IAIE99_Pos)             /*!< 0x00000008 */
+#define IAC_IER3_IAIE99               IAC_IER3_IAIE99_Msk
+#define IAC_IER3_IAIE100_Pos          (4U)
+#define IAC_IER3_IAIE100_Msk          (0x1UL << IAC_IER3_IAIE100_Pos)            /*!< 0x00000010 */
+#define IAC_IER3_IAIE100              IAC_IER3_IAIE100_Msk
+#define IAC_IER3_IAIE101_Pos          (5U)
+#define IAC_IER3_IAIE101_Msk          (0x1UL << IAC_IER3_IAIE101_Pos)            /*!< 0x00000020 */
+#define IAC_IER3_IAIE101              IAC_IER3_IAIE101_Msk
+#define IAC_IER3_IAIE102_Pos          (6U)
+#define IAC_IER3_IAIE102_Msk          (0x1UL << IAC_IER3_IAIE102_Pos)            /*!< 0x00000040 */
+#define IAC_IER3_IAIE102              IAC_IER3_IAIE102_Msk
+#define IAC_IER3_IAIE103_Pos          (7U)
+#define IAC_IER3_IAIE103_Msk          (0x1UL << IAC_IER3_IAIE103_Pos)            /*!< 0x00000080 */
+#define IAC_IER3_IAIE103              IAC_IER3_IAIE103_Msk
+#define IAC_IER3_IAIE104_Pos          (8U)
+#define IAC_IER3_IAIE104_Msk          (0x1UL << IAC_IER3_IAIE104_Pos)            /*!< 0x00000100 */
+#define IAC_IER3_IAIE104              IAC_IER3_IAIE104_Msk
+#define IAC_IER3_IAIE106_Pos          (10U)
+#define IAC_IER3_IAIE106_Msk          (0x1UL << IAC_IER3_IAIE106_Pos)            /*!< 0x00000400 */
+#define IAC_IER3_IAIE106              IAC_IER3_IAIE106_Msk
+
+/*******************  Bits definition for IAC_IER4 register *******************/
+#define IAC_IER4_IAIE128_Pos          (0U)
+#define IAC_IER4_IAIE128_Msk          (0x1UL << IAC_IER4_IAIE128_Pos)            /*!< 0x00000001 */
+#define IAC_IER4_IAIE128              IAC_IER4_IAIE128_Msk
+#define IAC_IER4_IAIE129_Pos          (1U)
+#define IAC_IER4_IAIE129_Msk          (0x1UL << IAC_IER4_IAIE129_Pos)            /*!< 0x00000002 */
+#define IAC_IER4_IAIE129              IAC_IER4_IAIE129_Msk
+#define IAC_IER4_IAIE130_Pos          (2U)
+#define IAC_IER4_IAIE130_Msk          (0x1UL << IAC_IER4_IAIE130_Pos)            /*!< 0x00000004 */
+#define IAC_IER4_IAIE130              IAC_IER4_IAIE130_Msk
+#define IAC_IER4_IAIE131_Pos          (3U)
+#define IAC_IER4_IAIE131_Msk          (0x1UL << IAC_IER4_IAIE131_Pos)            /*!< 0x00000008 */
+#define IAC_IER4_IAIE131              IAC_IER4_IAIE131_Msk
+#define IAC_IER4_IAIE133_Pos          (5U)
+#define IAC_IER4_IAIE133_Msk          (0x1UL << IAC_IER4_IAIE133_Pos)            /*!< 0x00000020 */
+#define IAC_IER4_IAIE133              IAC_IER4_IAIE133_Msk
+#define IAC_IER4_IAIE134_Pos          (6U)
+#define IAC_IER4_IAIE134_Msk          (0x1UL << IAC_IER4_IAIE134_Pos)            /*!< 0x00000040 */
+#define IAC_IER4_IAIE134              IAC_IER4_IAIE134_Msk
+#define IAC_IER4_IAIE135_Pos          (7U)
+#define IAC_IER4_IAIE135_Msk          (0x1UL << IAC_IER4_IAIE135_Pos)            /*!< 0x00000080 */
+#define IAC_IER4_IAIE135              IAC_IER4_IAIE135_Msk
+#define IAC_IER4_IAIE136_Pos          (8U)
+#define IAC_IER4_IAIE136_Msk          (0x1UL << IAC_IER4_IAIE136_Pos)            /*!< 0x00000100 */
+#define IAC_IER4_IAIE136              IAC_IER4_IAIE136_Msk
+#define IAC_IER4_IAIE137_Pos          (9U)
+#define IAC_IER4_IAIE137_Msk          (0x1UL << IAC_IER4_IAIE137_Pos)            /*!< 0x00000200 */
+#define IAC_IER4_IAIE137              IAC_IER4_IAIE137_Msk
+#define IAC_IER4_IAIE138_Pos          (10U)
+#define IAC_IER4_IAIE138_Msk          (0x1UL << IAC_IER4_IAIE138_Pos)            /*!< 0x00000400 */
+#define IAC_IER4_IAIE138              IAC_IER4_IAIE138_Msk
+#define IAC_IER4_IAIE139_Pos          (11U)
+#define IAC_IER4_IAIE139_Msk          (0x1UL << IAC_IER4_IAIE139_Pos)            /*!< 0x00000800 */
+#define IAC_IER4_IAIE139              IAC_IER4_IAIE139_Msk
+#define IAC_IER4_IAIE140_Pos          (12U)
+#define IAC_IER4_IAIE140_Msk          (0x1UL << IAC_IER4_IAIE140_Pos)            /*!< 0x00001000 */
+#define IAC_IER4_IAIE140              IAC_IER4_IAIE140_Msk
+#define IAC_IER4_IAIE141_Pos          (13U)
+#define IAC_IER4_IAIE141_Msk          (0x1UL << IAC_IER4_IAIE141_Pos)            /*!< 0x00002000 */
+#define IAC_IER4_IAIE141              IAC_IER4_IAIE141_Msk
+#define IAC_IER4_IAIE142_Pos          (14U)
+#define IAC_IER4_IAIE142_Msk          (0x1UL << IAC_IER4_IAIE142_Pos)            /*!< 0x00004000 */
+#define IAC_IER4_IAIE142              IAC_IER4_IAIE142_Msk
+#define IAC_IER4_IAIE143_Pos          (15U)
+#define IAC_IER4_IAIE143_Msk          (0x1UL << IAC_IER4_IAIE143_Pos)            /*!< 0x00008000 */
+#define IAC_IER4_IAIE143              IAC_IER4_IAIE143_Msk
+#define IAC_IER4_IAIE144_Pos          (16U)
+#define IAC_IER4_IAIE144_Msk          (0x1UL << IAC_IER4_IAIE144_Pos)            /*!< 0x00010000 */
+#define IAC_IER4_IAIE144              IAC_IER4_IAIE144_Msk
+#define IAC_IER4_IAIE145_Pos          (17U)
+#define IAC_IER4_IAIE145_Msk          (0x1UL << IAC_IER4_IAIE145_Pos)            /*!< 0x00020000 */
+#define IAC_IER4_IAIE145              IAC_IER4_IAIE145_Msk
+#define IAC_IER4_IAIE146_Pos          (18U)
+#define IAC_IER4_IAIE146_Msk          (0x1UL << IAC_IER4_IAIE146_Pos)            /*!< 0x00040000 */
+#define IAC_IER4_IAIE146              IAC_IER4_IAIE146_Msk
+#define IAC_IER4_IAIE147_Pos          (19U)
+#define IAC_IER4_IAIE147_Msk          (0x1UL << IAC_IER4_IAIE147_Pos)            /*!< 0x00080000 */
+#define IAC_IER4_IAIE147              IAC_IER4_IAIE147_Msk
+#define IAC_IER4_IAIE149_Pos          (21U)
+#define IAC_IER4_IAIE149_Msk          (0x1UL << IAC_IER4_IAIE149_Pos)            /*!< 0x00200000 */
+#define IAC_IER4_IAIE149              IAC_IER4_IAIE149_Msk
+#define IAC_IER4_IAIE150_Pos          (22U)
+#define IAC_IER4_IAIE150_Msk          (0x1UL << IAC_IER4_IAIE150_Pos)            /*!< 0x00400000 */
+#define IAC_IER4_IAIE150              IAC_IER4_IAIE150_Msk
+#define IAC_IER4_IAIE151_Pos          (23U)
+#define IAC_IER4_IAIE151_Msk          (0x1UL << IAC_IER4_IAIE151_Pos)            /*!< 0x00800000 */
+#define IAC_IER4_IAIE151              IAC_IER4_IAIE151_Msk
+#define IAC_IER4_IAIE152_Pos          (24U)
+#define IAC_IER4_IAIE152_Msk          (0x1UL << IAC_IER4_IAIE152_Pos)            /*!< 0x01000000 */
+#define IAC_IER4_IAIE152              IAC_IER4_IAIE152_Msk
+#define IAC_IER4_IAIE153_Pos          (25U)
+#define IAC_IER4_IAIE153_Msk          (0x1UL << IAC_IER4_IAIE153_Pos)            /*!< 0x02000000 */
+#define IAC_IER4_IAIE153              IAC_IER4_IAIE153_Msk
+#define IAC_IER4_IAIE155_Pos          (27U)
+#define IAC_IER4_IAIE155_Msk          (0x1UL << IAC_IER4_IAIE155_Pos)            /*!< 0x08000000 */
+#define IAC_IER4_IAIE155              IAC_IER4_IAIE155_Msk
+#define IAC_IER4_IAIE156_Pos          (28U)
+#define IAC_IER4_IAIE156_Msk          (0x1UL << IAC_IER4_IAIE156_Pos)            /*!< 0x10000000 */
+#define IAC_IER4_IAIE156              IAC_IER4_IAIE156_Msk
+#define IAC_IER4_IAIE157_Pos          (29U)
+#define IAC_IER4_IAIE157_Msk          (0x1UL << IAC_IER4_IAIE157_Pos)            /*!< 0x20000000 */
+#define IAC_IER4_IAIE157              IAC_IER4_IAIE157_Msk
+
+/*******************  Bits definition for IAC_ISR0 register *******************/
+#define IAC_ISR0_IAF0_Pos             (0U)
+#define IAC_ISR0_IAF0_Msk             (0x1UL << IAC_ISR0_IAF0_Pos)               /*!< 0x00000001 */
+#define IAC_ISR0_IAF0                 IAC_ISR0_IAF0_Msk
+#define IAC_ISR0_IAF1_Pos             (1U)
+#define IAC_ISR0_IAF1_Msk             (0x1UL << IAC_ISR0_IAF1_Pos)               /*!< 0x00000002 */
+#define IAC_ISR0_IAF1                 IAC_ISR0_IAF1_Msk
+#define IAC_ISR0_IAF2_Pos             (2U)
+#define IAC_ISR0_IAF2_Msk             (0x1UL << IAC_ISR0_IAF2_Pos)               /*!< 0x00000004 */
+#define IAC_ISR0_IAF2                 IAC_ISR0_IAF2_Msk
+#define IAC_ISR0_IAF3_Pos             (3U)
+#define IAC_ISR0_IAF3_Msk             (0x1UL << IAC_ISR0_IAF3_Pos)               /*!< 0x00000008 */
+#define IAC_ISR0_IAF3                 IAC_ISR0_IAF3_Msk
+#define IAC_ISR0_IAF4_Pos             (4U)
+#define IAC_ISR0_IAF4_Msk             (0x1UL << IAC_ISR0_IAF4_Pos)               /*!< 0x00000010 */
+#define IAC_ISR0_IAF4                 IAC_ISR0_IAF4_Msk
+#define IAC_ISR0_IAF5_Pos             (5U)
+#define IAC_ISR0_IAF5_Msk             (0x1UL << IAC_ISR0_IAF5_Pos)               /*!< 0x00000020 */
+#define IAC_ISR0_IAF5                 IAC_ISR0_IAF5_Msk
+#define IAC_ISR0_IAF6_Pos             (6U)
+#define IAC_ISR0_IAF6_Msk             (0x1UL << IAC_ISR0_IAF6_Pos)               /*!< 0x00000040 */
+#define IAC_ISR0_IAF6                 IAC_ISR0_IAF6_Msk
+#define IAC_ISR0_IAF8_Pos             (8U)
+#define IAC_ISR0_IAF8_Msk             (0x1UL << IAC_ISR0_IAF8_Pos)               /*!< 0x00000100 */
+#define IAC_ISR0_IAF8                 IAC_ISR0_IAF8_Msk
+#define IAC_ISR0_IAF9_Pos             (9U)
+#define IAC_ISR0_IAF9_Msk             (0x1UL << IAC_ISR0_IAF9_Pos)               /*!< 0x00000200 */
+#define IAC_ISR0_IAF9                 IAC_ISR0_IAF9_Msk
+#define IAC_ISR0_IAF10_Pos            (10U)
+#define IAC_ISR0_IAF10_Msk            (0x1UL << IAC_ISR0_IAF10_Pos)              /*!< 0x00000400 */
+#define IAC_ISR0_IAF10                IAC_ISR0_IAF10_Msk
+#define IAC_ISR0_IAF11_Pos            (11U)
+#define IAC_ISR0_IAF11_Msk            (0x1UL << IAC_ISR0_IAF11_Pos)              /*!< 0x00000800 */
+#define IAC_ISR0_IAF11                IAC_ISR0_IAF11_Msk
+#define IAC_ISR0_IAF12_Pos            (12U)
+#define IAC_ISR0_IAF12_Msk            (0x1UL << IAC_ISR0_IAF12_Pos)              /*!< 0x00001000 */
+#define IAC_ISR0_IAF12                IAC_ISR0_IAF12_Msk
+#define IAC_ISR0_IAF13_Pos            (13U)
+#define IAC_ISR0_IAF13_Msk            (0x1UL << IAC_ISR0_IAF13_Pos)              /*!< 0x00002000 */
+#define IAC_ISR0_IAF13                IAC_ISR0_IAF13_Msk
+#define IAC_ISR0_IAF14_Pos            (14U)
+#define IAC_ISR0_IAF14_Msk            (0x1UL << IAC_ISR0_IAF14_Pos)              /*!< 0x00004000 */
+#define IAC_ISR0_IAF14                IAC_ISR0_IAF14_Msk
+#define IAC_ISR0_IAF15_Pos            (15U)
+#define IAC_ISR0_IAF15_Msk            (0x1UL << IAC_ISR0_IAF15_Pos)              /*!< 0x00008000 */
+#define IAC_ISR0_IAF15                IAC_ISR0_IAF15_Msk
+#define IAC_ISR0_IAF16_Pos            (16U)
+#define IAC_ISR0_IAF16_Msk            (0x1UL << IAC_ISR0_IAF16_Pos)              /*!< 0x00010000 */
+#define IAC_ISR0_IAF16                IAC_ISR0_IAF16_Msk
+#define IAC_ISR0_IAF17_Pos            (17U)
+#define IAC_ISR0_IAF17_Msk            (0x1UL << IAC_ISR0_IAF17_Pos)              /*!< 0x00020000 */
+#define IAC_ISR0_IAF17                IAC_ISR0_IAF17_Msk
+#define IAC_ISR0_IAF18_Pos            (18U)
+#define IAC_ISR0_IAF18_Msk            (0x1UL << IAC_ISR0_IAF18_Pos)              /*!< 0x00040000 */
+#define IAC_ISR0_IAF18                IAC_ISR0_IAF18_Msk
+#define IAC_ISR0_IAF19_Pos            (19U)
+#define IAC_ISR0_IAF19_Msk            (0x1UL << IAC_ISR0_IAF19_Pos)              /*!< 0x00080000 */
+#define IAC_ISR0_IAF19                IAC_ISR0_IAF19_Msk
+#define IAC_ISR0_IAF20_Pos            (20U)
+#define IAC_ISR0_IAF20_Msk            (0x1UL << IAC_ISR0_IAF20_Pos)              /*!< 0x00100000 */
+#define IAC_ISR0_IAF20                IAC_ISR0_IAF20_Msk
+#define IAC_ISR0_IAF21_Pos            (21U)
+#define IAC_ISR0_IAF21_Msk            (0x1UL << IAC_ISR0_IAF21_Pos)              /*!< 0x00200000 */
+#define IAC_ISR0_IAF21                IAC_ISR0_IAF21_Msk
+#define IAC_ISR0_IAF22_Pos            (22U)
+#define IAC_ISR0_IAF22_Msk            (0x1UL << IAC_ISR0_IAF22_Pos)              /*!< 0x00400000 */
+#define IAC_ISR0_IAF22                IAC_ISR0_IAF22_Msk
+#define IAC_ISR0_IAF23_Pos            (23U)
+#define IAC_ISR0_IAF23_Msk            (0x1UL << IAC_ISR0_IAF23_Pos)              /*!< 0x00800000 */
+#define IAC_ISR0_IAF23                IAC_ISR0_IAF23_Msk
+#define IAC_ISR0_IAF24_Pos            (24U)
+#define IAC_ISR0_IAF24_Msk            (0x1UL << IAC_ISR0_IAF24_Pos)              /*!< 0x01000000 */
+#define IAC_ISR0_IAF24                IAC_ISR0_IAF24_Msk
+#define IAC_ISR0_IAF25_Pos            (25U)
+#define IAC_ISR0_IAF25_Msk            (0x1UL << IAC_ISR0_IAF25_Pos)              /*!< 0x02000000 */
+#define IAC_ISR0_IAF25                IAC_ISR0_IAF25_Msk
+#define IAC_ISR0_IAF26_Pos            (26U)
+#define IAC_ISR0_IAF26_Msk            (0x1UL << IAC_ISR0_IAF26_Pos)              /*!< 0x04000000 */
+#define IAC_ISR0_IAF26                IAC_ISR0_IAF26_Msk
+#define IAC_ISR0_IAF27_Pos            (27U)
+#define IAC_ISR0_IAF27_Msk            (0x1UL << IAC_ISR0_IAF27_Pos)              /*!< 0x08000000 */
+#define IAC_ISR0_IAF27                IAC_ISR0_IAF27_Msk
+#define IAC_ISR0_IAF28_Pos            (28U)
+#define IAC_ISR0_IAF28_Msk            (0x1UL << IAC_ISR0_IAF28_Pos)              /*!< 0x10000000 */
+#define IAC_ISR0_IAF28                IAC_ISR0_IAF28_Msk
+#define IAC_ISR0_IAF29_Pos            (29U)
+#define IAC_ISR0_IAF29_Msk            (0x1UL << IAC_ISR0_IAF29_Pos)              /*!< 0x20000000 */
+#define IAC_ISR0_IAF29                IAC_ISR0_IAF29_Msk
+#define IAC_ISR0_IAF30_Pos            (30U)
+#define IAC_ISR0_IAF30_Msk            (0x1UL << IAC_ISR0_IAF30_Pos)              /*!< 0x40000000 */
+#define IAC_ISR0_IAF30                IAC_ISR0_IAF30_Msk
+#define IAC_ISR0_IAF31_Pos            (31U)
+#define IAC_ISR0_IAF31_Msk            (0x1UL << IAC_ISR0_IAF31_Pos)              /*!< 0x80000000 */
+#define IAC_ISR0_IAF31                IAC_ISR0_IAF31_Msk
+
+/*******************  Bits definition for IAC_ISR1 register *******************/
+#define IAC_ISR1_IAF32_Pos            (0U)
+#define IAC_ISR1_IAF32_Msk            (0x1UL << IAC_ISR1_IAF32_Pos)              /*!< 0x00000001 */
+#define IAC_ISR1_IAF32                IAC_ISR1_IAF32_Msk
+#define IAC_ISR1_IAF33_Pos            (1U)
+#define IAC_ISR1_IAF33_Msk            (0x1UL << IAC_ISR1_IAF33_Pos)              /*!< 0x00000002 */
+#define IAC_ISR1_IAF33                IAC_ISR1_IAF33_Msk
+#define IAC_ISR1_IAF34_Pos            (2U)
+#define IAC_ISR1_IAF34_Msk            (0x1UL << IAC_ISR1_IAF34_Pos)              /*!< 0x00000004 */
+#define IAC_ISR1_IAF34                IAC_ISR1_IAF34_Msk
+#define IAC_ISR1_IAF35_Pos            (3U)
+#define IAC_ISR1_IAF35_Msk            (0x1UL << IAC_ISR1_IAF35_Pos)              /*!< 0x00000008 */
+#define IAC_ISR1_IAF35                IAC_ISR1_IAF35_Msk
+#define IAC_ISR1_IAF36_Pos            (4U)
+#define IAC_ISR1_IAF36_Msk            (0x1UL << IAC_ISR1_IAF36_Pos)              /*!< 0x00000010 */
+#define IAC_ISR1_IAF36                IAC_ISR1_IAF36_Msk
+#define IAC_ISR1_IAF37_Pos            (5U)
+#define IAC_ISR1_IAF37_Msk            (0x1UL << IAC_ISR1_IAF37_Pos)              /*!< 0x00000020 */
+#define IAC_ISR1_IAF37                IAC_ISR1_IAF37_Msk
+#define IAC_ISR1_IAF38_Pos            (6U)
+#define IAC_ISR1_IAF38_Msk            (0x1UL << IAC_ISR1_IAF38_Pos)              /*!< 0x00000040 */
+#define IAC_ISR1_IAF38                IAC_ISR1_IAF38_Msk
+#define IAC_ISR1_IAF39_Pos            (7U)
+#define IAC_ISR1_IAF39_Msk            (0x1UL << IAC_ISR1_IAF39_Pos)              /*!< 0x00000080 */
+#define IAC_ISR1_IAF39                IAC_ISR1_IAF39_Msk
+#define IAC_ISR1_IAF40_Pos            (8U)
+#define IAC_ISR1_IAF40_Msk            (0x1UL << IAC_ISR1_IAF40_Pos)              /*!< 0x00000100 */
+#define IAC_ISR1_IAF40                IAC_ISR1_IAF40_Msk
+#define IAC_ISR1_IAF41_Pos            (9U)
+#define IAC_ISR1_IAF41_Msk            (0x1UL << IAC_ISR1_IAF41_Pos)              /*!< 0x00000200 */
+#define IAC_ISR1_IAF41                IAC_ISR1_IAF41_Msk
+#define IAC_ISR1_IAF42_Pos            (10U)
+#define IAC_ISR1_IAF42_Msk            (0x1UL << IAC_ISR1_IAF42_Pos)              /*!< 0x00000400 */
+#define IAC_ISR1_IAF42                IAC_ISR1_IAF42_Msk
+#define IAC_ISR1_IAF43_Pos            (11U)
+#define IAC_ISR1_IAF43_Msk            (0x1UL << IAC_ISR1_IAF43_Pos)              /*!< 0x00000800 */
+#define IAC_ISR1_IAF43                IAC_ISR1_IAF43_Msk
+#define IAC_ISR1_IAF44_Pos            (12U)
+#define IAC_ISR1_IAF44_Msk            (0x1UL << IAC_ISR1_IAF44_Pos)              /*!< 0x00001000 */
+#define IAC_ISR1_IAF44                IAC_ISR1_IAF44_Msk
+#define IAC_ISR1_IAF45_Pos            (13U)
+#define IAC_ISR1_IAF45_Msk            (0x1UL << IAC_ISR1_IAF45_Pos)              /*!< 0x00002000 */
+#define IAC_ISR1_IAF45                IAC_ISR1_IAF45_Msk
+#define IAC_ISR1_IAF46_Pos            (14U)
+#define IAC_ISR1_IAF46_Msk            (0x1UL << IAC_ISR1_IAF46_Pos)              /*!< 0x00004000 */
+#define IAC_ISR1_IAF46                IAC_ISR1_IAF46_Msk
+#define IAC_ISR1_IAF47_Pos            (15U)
+#define IAC_ISR1_IAF47_Msk            (0x1UL << IAC_ISR1_IAF47_Pos)              /*!< 0x00008000 */
+#define IAC_ISR1_IAF47                IAC_ISR1_IAF47_Msk
+#define IAC_ISR1_IAF48_Pos            (16U)
+#define IAC_ISR1_IAF48_Msk            (0x1UL << IAC_ISR1_IAF48_Pos)              /*!< 0x00010000 */
+#define IAC_ISR1_IAF48                IAC_ISR1_IAF48_Msk
+#define IAC_ISR1_IAF49_Pos            (17U)
+#define IAC_ISR1_IAF49_Msk            (0x1UL << IAC_ISR1_IAF49_Pos)              /*!< 0x00020000 */
+#define IAC_ISR1_IAF49                IAC_ISR1_IAF49_Msk
+#define IAC_ISR1_IAF50_Pos            (18U)
+#define IAC_ISR1_IAF50_Msk            (0x1UL << IAC_ISR1_IAF50_Pos)              /*!< 0x00040000 */
+#define IAC_ISR1_IAF50                IAC_ISR1_IAF50_Msk
+#define IAC_ISR1_IAF51_Pos            (19U)
+#define IAC_ISR1_IAF51_Msk            (0x1UL << IAC_ISR1_IAF51_Pos)              /*!< 0x00080000 */
+#define IAC_ISR1_IAF51                IAC_ISR1_IAF51_Msk
+#define IAC_ISR1_IAF52_Pos            (20U)
+#define IAC_ISR1_IAF52_Msk            (0x1UL << IAC_ISR1_IAF52_Pos)              /*!< 0x00100000 */
+#define IAC_ISR1_IAF52                IAC_ISR1_IAF52_Msk
+#define IAC_ISR1_IAF53_Pos            (21U)
+#define IAC_ISR1_IAF53_Msk            (0x1UL << IAC_ISR1_IAF53_Pos)              /*!< 0x00200000 */
+#define IAC_ISR1_IAF53                IAC_ISR1_IAF53_Msk
+#define IAC_ISR1_IAF54_Pos            (22U)
+#define IAC_ISR1_IAF54_Msk            (0x1UL << IAC_ISR1_IAF54_Pos)              /*!< 0x00400000 */
+#define IAC_ISR1_IAF54                IAC_ISR1_IAF54_Msk
+#define IAC_ISR1_IAF55_Pos            (23U)
+#define IAC_ISR1_IAF55_Msk            (0x1UL << IAC_ISR1_IAF55_Pos)              /*!< 0x00800000 */
+#define IAC_ISR1_IAF55                IAC_ISR1_IAF55_Msk
+#define IAC_ISR1_IAF56_Pos            (24U)
+#define IAC_ISR1_IAF56_Msk            (0x1UL << IAC_ISR1_IAF56_Pos)              /*!< 0x01000000 */
+#define IAC_ISR1_IAF56                IAC_ISR1_IAF56_Msk
+#define IAC_ISR1_IAF57_Pos            (25U)
+#define IAC_ISR1_IAF57_Msk            (0x1UL << IAC_ISR1_IAF57_Pos)              /*!< 0x02000000 */
+#define IAC_ISR1_IAF57                IAC_ISR1_IAF57_Msk
+#define IAC_ISR1_IAF58_Pos            (26U)
+#define IAC_ISR1_IAF58_Msk            (0x1UL << IAC_ISR1_IAF58_Pos)              /*!< 0x04000000 */
+#define IAC_ISR1_IAF58                IAC_ISR1_IAF58_Msk
+#define IAC_ISR1_IAF60_Pos            (28U)
+#define IAC_ISR1_IAF60_Msk            (0x1UL << IAC_ISR1_IAF60_Pos)              /*!< 0x10000000 */
+#define IAC_ISR1_IAF60                IAC_ISR1_IAF60_Msk
+#define IAC_ISR1_IAF61_Pos            (29U)
+#define IAC_ISR1_IAF61_Msk            (0x1UL << IAC_ISR1_IAF61_Pos)              /*!< 0x20000000 */
+#define IAC_ISR1_IAF61                IAC_ISR1_IAF61_Msk
+#define IAC_ISR1_IAF62_Pos            (30U)
+#define IAC_ISR1_IAF62_Msk            (0x1UL << IAC_ISR1_IAF62_Pos)              /*!< 0x40000000 */
+#define IAC_ISR1_IAF62                IAC_ISR1_IAF62_Msk
+
+/*******************  Bits definition for IAC_ISR2 register *******************/
+#define IAC_ISR2_IAF64_Pos            (0U)
+#define IAC_ISR2_IAF64_Msk            (0x1UL << IAC_ISR2_IAF64_Pos)              /*!< 0x00000001 */
+#define IAC_ISR2_IAF64                IAC_ISR2_IAF64_Msk
+#define IAC_ISR2_IAF65_Pos            (1U)
+#define IAC_ISR2_IAF65_Msk            (0x1UL << IAC_ISR2_IAF65_Pos)              /*!< 0x00000002 */
+#define IAC_ISR2_IAF65                IAC_ISR2_IAF65_Msk
+#define IAC_ISR2_IAF67_Pos            (3U)
+#define IAC_ISR2_IAF67_Msk            (0x1UL << IAC_ISR2_IAF67_Pos)              /*!< 0x00000008 */
+#define IAC_ISR2_IAF67                IAC_ISR2_IAF67_Msk
+#define IAC_ISR2_IAF68_Pos            (4U)
+#define IAC_ISR2_IAF68_Msk            (0x1UL << IAC_ISR2_IAF68_Pos)              /*!< 0x00000010 */
+#define IAC_ISR2_IAF68                IAC_ISR2_IAF68_Msk
+#define IAC_ISR2_IAF69_Pos            (5U)
+#define IAC_ISR2_IAF69_Msk            (0x1UL << IAC_ISR2_IAF69_Pos)              /*!< 0x00000020 */
+#define IAC_ISR2_IAF69                IAC_ISR2_IAF69_Msk
+#define IAC_ISR2_IAF76_Pos            (12U)
+#define IAC_ISR2_IAF76_Msk            (0x1UL << IAC_ISR2_IAF76_Pos)              /*!< 0x00001000 */
+#define IAC_ISR2_IAF76                IAC_ISR2_IAF76_Msk
+#define IAC_ISR2_IAF77_Pos            (13U)
+#define IAC_ISR2_IAF77_Msk            (0x1UL << IAC_ISR2_IAF77_Pos)              /*!< 0x00002000 */
+#define IAC_ISR2_IAF77                IAC_ISR2_IAF77_Msk
+#define IAC_ISR2_IAF78_Pos            (14U)
+#define IAC_ISR2_IAF78_Msk            (0x1UL << IAC_ISR2_IAF78_Pos)              /*!< 0x00004000 */
+#define IAC_ISR2_IAF78                IAC_ISR2_IAF78_Msk
+#define IAC_ISR2_IAF79_Pos            (15U)
+#define IAC_ISR2_IAF79_Msk            (0x1UL << IAC_ISR2_IAF79_Pos)              /*!< 0x00008000 */
+#define IAC_ISR2_IAF79                IAC_ISR2_IAF79_Msk
+#define IAC_ISR2_IAF80_Pos            (16U)
+#define IAC_ISR2_IAF80_Msk            (0x1UL << IAC_ISR2_IAF80_Pos)              /*!< 0x00010000 */
+#define IAC_ISR2_IAF80                IAC_ISR2_IAF80_Msk
+#define IAC_ISR2_IAF81_Pos            (17U)
+#define IAC_ISR2_IAF81_Msk            (0x1UL << IAC_ISR2_IAF81_Pos)              /*!< 0x00020000 */
+#define IAC_ISR2_IAF81                IAC_ISR2_IAF81_Msk
+#define IAC_ISR2_IAF82_Pos            (18U)
+#define IAC_ISR2_IAF82_Msk            (0x1UL << IAC_ISR2_IAF82_Pos)              /*!< 0x00040000 */
+#define IAC_ISR2_IAF82                IAC_ISR2_IAF82_Msk
+#define IAC_ISR2_IAF83_Pos            (19U)
+#define IAC_ISR2_IAF83_Msk            (0x1UL << IAC_ISR2_IAF83_Pos)              /*!< 0x00080000 */
+#define IAC_ISR2_IAF83                IAC_ISR2_IAF83_Msk
+#define IAC_ISR2_IAF84_Pos            (20U)
+#define IAC_ISR2_IAF84_Msk            (0x1UL << IAC_ISR2_IAF84_Pos)              /*!< 0x00100000 */
+#define IAC_ISR2_IAF84                IAC_ISR2_IAF84_Msk
+#define IAC_ISR2_IAF86_Pos            (22U)
+#define IAC_ISR2_IAF86_Msk            (0x1UL << IAC_ISR2_IAF86_Pos)              /*!< 0x00400000 */
+#define IAC_ISR2_IAF86                IAC_ISR2_IAF86_Msk
+#define IAC_ISR2_IAF87_Pos            (23U)
+#define IAC_ISR2_IAF87_Msk            (0x1UL << IAC_ISR2_IAF87_Pos)              /*!< 0x00800000 */
+#define IAC_ISR2_IAF87                IAC_ISR2_IAF87_Msk
+#define IAC_ISR2_IAF88_Pos            (24U)
+#define IAC_ISR2_IAF88_Msk            (0x1UL << IAC_ISR2_IAF88_Pos)              /*!< 0x01000000 */
+#define IAC_ISR2_IAF88                IAC_ISR2_IAF88_Msk
+#define IAC_ISR2_IAF89_Pos            (25U)
+#define IAC_ISR2_IAF89_Msk            (0x1UL << IAC_ISR2_IAF89_Pos)              /*!< 0x02000000 */
+#define IAC_ISR2_IAF89                IAC_ISR2_IAF89_Msk
+#define IAC_ISR2_IAF90_Pos            (26U)
+#define IAC_ISR2_IAF90_Msk            (0x1UL << IAC_ISR2_IAF90_Pos)              /*!< 0x04000000 */
+#define IAC_ISR2_IAF90                IAC_ISR2_IAF90_Msk
+#define IAC_ISR2_IAF92_Pos            (28U)
+#define IAC_ISR2_IAF92_Msk            (0x1UL << IAC_ISR2_IAF92_Pos)              /*!< 0x10000000 */
+#define IAC_ISR2_IAF92                IAC_ISR2_IAF92_Msk
+#define IAC_ISR2_IAF93_Pos            (29U)
+#define IAC_ISR2_IAF93_Msk            (0x1UL << IAC_ISR2_IAF93_Pos)              /*!< 0x20000000 */
+#define IAC_ISR2_IAF93                IAC_ISR2_IAF93_Msk
+#define IAC_ISR2_IAF94_Pos            (30U)
+#define IAC_ISR2_IAF94_Msk            (0x1UL << IAC_ISR2_IAF94_Pos)              /*!< 0x40000000 */
+#define IAC_ISR2_IAF94                IAC_ISR2_IAF94_Msk
+#define IAC_ISR2_IAF95_Pos            (31U)
+#define IAC_ISR2_IAF95_Msk            (0x1UL << IAC_ISR2_IAF95_Pos)              /*!< 0x80000000 */
+#define IAC_ISR2_IAF95                IAC_ISR2_IAF95_Msk
+
+/*******************  Bits definition for IAC_ISR3 register *******************/
+#define IAC_ISR3_IAF96_Pos            (0U)
+#define IAC_ISR3_IAF96_Msk            (0x1UL << IAC_ISR3_IAF96_Pos)              /*!< 0x00000001 */
+#define IAC_ISR3_IAF96                IAC_ISR3_IAF96_Msk
+#define IAC_ISR3_IAF97_Pos            (1U)
+#define IAC_ISR3_IAF97_Msk            (0x1UL << IAC_ISR3_IAF97_Pos)              /*!< 0x00000002 */
+#define IAC_ISR3_IAF97                IAC_ISR3_IAF97_Msk
+#define IAC_ISR3_IAF98_Pos            (2U)
+#define IAC_ISR3_IAF98_Msk            (0x1UL << IAC_ISR3_IAF98_Pos)              /*!< 0x00000004 */
+#define IAC_ISR3_IAF98                IAC_ISR3_IAF98_Msk
+#define IAC_ISR3_IAF99_Pos            (3U)
+#define IAC_ISR3_IAF99_Msk            (0x1UL << IAC_ISR3_IAF99_Pos)              /*!< 0x00000008 */
+#define IAC_ISR3_IAF99                IAC_ISR3_IAF99_Msk
+#define IAC_ISR3_IAF100_Pos           (4U)
+#define IAC_ISR3_IAF100_Msk           (0x1UL << IAC_ISR3_IAF100_Pos)             /*!< 0x00000010 */
+#define IAC_ISR3_IAF100               IAC_ISR3_IAF100_Msk
+#define IAC_ISR3_IAF101_Pos           (5U)
+#define IAC_ISR3_IAF101_Msk           (0x1UL << IAC_ISR3_IAF101_Pos)             /*!< 0x00000020 */
+#define IAC_ISR3_IAF101               IAC_ISR3_IAF101_Msk
+#define IAC_ISR3_IAF102_Pos           (6U)
+#define IAC_ISR3_IAF102_Msk           (0x1UL << IAC_ISR3_IAF102_Pos)             /*!< 0x00000040 */
+#define IAC_ISR3_IAF102               IAC_ISR3_IAF102_Msk
+#define IAC_ISR3_IAF103_Pos           (7U)
+#define IAC_ISR3_IAF103_Msk           (0x1UL << IAC_ISR3_IAF103_Pos)             /*!< 0x00000080 */
+#define IAC_ISR3_IAF103               IAC_ISR3_IAF103_Msk
+#define IAC_ISR3_IAF104_Pos           (8U)
+#define IAC_ISR3_IAF104_Msk           (0x1UL << IAC_ISR3_IAF104_Pos)             /*!< 0x00000100 */
+#define IAC_ISR3_IAF104               IAC_ISR3_IAF104_Msk
+#define IAC_ISR3_IAF106_Pos           (10U)
+#define IAC_ISR3_IAF106_Msk           (0x1UL << IAC_ISR3_IAF106_Pos)             /*!< 0x00000400 */
+#define IAC_ISR3_IAF106               IAC_ISR3_IAF106_Msk
+
+/*******************  Bits definition for IAC_ISR4 register *******************/
+#define IAC_ISR4_IAF128_Pos           (0U)
+#define IAC_ISR4_IAF128_Msk           (0x1UL << IAC_ISR4_IAF128_Pos)             /*!< 0x00000001 */
+#define IAC_ISR4_IAF128               IAC_ISR4_IAF128_Msk
+#define IAC_ISR4_IAF129_Pos           (1U)
+#define IAC_ISR4_IAF129_Msk           (0x1UL << IAC_ISR4_IAF129_Pos)             /*!< 0x00000002 */
+#define IAC_ISR4_IAF129               IAC_ISR4_IAF129_Msk
+#define IAC_ISR4_IAF130_Pos           (2U)
+#define IAC_ISR4_IAF130_Msk           (0x1UL << IAC_ISR4_IAF130_Pos)             /*!< 0x00000004 */
+#define IAC_ISR4_IAF130               IAC_ISR4_IAF130_Msk
+#define IAC_ISR4_IAF131_Pos           (3U)
+#define IAC_ISR4_IAF131_Msk           (0x1UL << IAC_ISR4_IAF131_Pos)             /*!< 0x00000008 */
+#define IAC_ISR4_IAF131               IAC_ISR4_IAF131_Msk
+#define IAC_ISR4_IAF133_Pos           (5U)
+#define IAC_ISR4_IAF133_Msk           (0x1UL << IAC_ISR4_IAF133_Pos)             /*!< 0x00000020 */
+#define IAC_ISR4_IAF133               IAC_ISR4_IAF133_Msk
+#define IAC_ISR4_IAF134_Pos           (6U)
+#define IAC_ISR4_IAF134_Msk           (0x1UL << IAC_ISR4_IAF134_Pos)             /*!< 0x00000040 */
+#define IAC_ISR4_IAF134               IAC_ISR4_IAF134_Msk
+#define IAC_ISR4_IAF135_Pos           (7U)
+#define IAC_ISR4_IAF135_Msk           (0x1UL << IAC_ISR4_IAF135_Pos)             /*!< 0x00000080 */
+#define IAC_ISR4_IAF135               IAC_ISR4_IAF135_Msk
+#define IAC_ISR4_IAF136_Pos           (8U)
+#define IAC_ISR4_IAF136_Msk           (0x1UL << IAC_ISR4_IAF136_Pos)             /*!< 0x00000100 */
+#define IAC_ISR4_IAF136               IAC_ISR4_IAF136_Msk
+#define IAC_ISR4_IAF137_Pos           (9U)
+#define IAC_ISR4_IAF137_Msk           (0x1UL << IAC_ISR4_IAF137_Pos)             /*!< 0x00000200 */
+#define IAC_ISR4_IAF137               IAC_ISR4_IAF137_Msk
+#define IAC_ISR4_IAF138_Pos           (10U)
+#define IAC_ISR4_IAF138_Msk           (0x1UL << IAC_ISR4_IAF138_Pos)             /*!< 0x00000400 */
+#define IAC_ISR4_IAF138               IAC_ISR4_IAF138_Msk
+#define IAC_ISR4_IAF139_Pos           (11U)
+#define IAC_ISR4_IAF139_Msk           (0x1UL << IAC_ISR4_IAF139_Pos)             /*!< 0x00000800 */
+#define IAC_ISR4_IAF139               IAC_ISR4_IAF139_Msk
+#define IAC_ISR4_IAF140_Pos           (12U)
+#define IAC_ISR4_IAF140_Msk           (0x1UL << IAC_ISR4_IAF140_Pos)             /*!< 0x00001000 */
+#define IAC_ISR4_IAF140               IAC_ISR4_IAF140_Msk
+#define IAC_ISR4_IAF141_Pos           (13U)
+#define IAC_ISR4_IAF141_Msk           (0x1UL << IAC_ISR4_IAF141_Pos)             /*!< 0x00002000 */
+#define IAC_ISR4_IAF141               IAC_ISR4_IAF141_Msk
+#define IAC_ISR4_IAF142_Pos           (14U)
+#define IAC_ISR4_IAF142_Msk           (0x1UL << IAC_ISR4_IAF142_Pos)             /*!< 0x00004000 */
+#define IAC_ISR4_IAF142               IAC_ISR4_IAF142_Msk
+#define IAC_ISR4_IAF143_Pos           (15U)
+#define IAC_ISR4_IAF143_Msk           (0x1UL << IAC_ISR4_IAF143_Pos)             /*!< 0x00008000 */
+#define IAC_ISR4_IAF143               IAC_ISR4_IAF143_Msk
+#define IAC_ISR4_IAF144_Pos           (16U)
+#define IAC_ISR4_IAF144_Msk           (0x1UL << IAC_ISR4_IAF144_Pos)             /*!< 0x00010000 */
+#define IAC_ISR4_IAF144               IAC_ISR4_IAF144_Msk
+#define IAC_ISR4_IAF145_Pos           (17U)
+#define IAC_ISR4_IAF145_Msk           (0x1UL << IAC_ISR4_IAF145_Pos)             /*!< 0x00020000 */
+#define IAC_ISR4_IAF145               IAC_ISR4_IAF145_Msk
+#define IAC_ISR4_IAF146_Pos           (18U)
+#define IAC_ISR4_IAF146_Msk           (0x1UL << IAC_ISR4_IAF146_Pos)             /*!< 0x00040000 */
+#define IAC_ISR4_IAF146               IAC_ISR4_IAF146_Msk
+#define IAC_ISR4_IAF147_Pos           (19U)
+#define IAC_ISR4_IAF147_Msk           (0x1UL << IAC_ISR4_IAF147_Pos)             /*!< 0x00080000 */
+#define IAC_ISR4_IAF147               IAC_ISR4_IAF147_Msk
+#define IAC_ISR4_IAF149_Pos           (21U)
+#define IAC_ISR4_IAF149_Msk           (0x1UL << IAC_ISR4_IAF149_Pos)             /*!< 0x00200000 */
+#define IAC_ISR4_IAF149               IAC_ISR4_IAF149_Msk
+#define IAC_ISR4_IAF150_Pos           (22U)
+#define IAC_ISR4_IAF150_Msk           (0x1UL << IAC_ISR4_IAF150_Pos)             /*!< 0x00400000 */
+#define IAC_ISR4_IAF150               IAC_ISR4_IAF150_Msk
+#define IAC_ISR4_IAF151_Pos           (23U)
+#define IAC_ISR4_IAF151_Msk           (0x1UL << IAC_ISR4_IAF151_Pos)             /*!< 0x00800000 */
+#define IAC_ISR4_IAF151               IAC_ISR4_IAF151_Msk
+#define IAC_ISR4_IAF152_Pos           (24U)
+#define IAC_ISR4_IAF152_Msk           (0x1UL << IAC_ISR4_IAF152_Pos)             /*!< 0x01000000 */
+#define IAC_ISR4_IAF152               IAC_ISR4_IAF152_Msk
+#define IAC_ISR4_IAF153_Pos           (25U)
+#define IAC_ISR4_IAF153_Msk           (0x1UL << IAC_ISR4_IAF153_Pos)             /*!< 0x02000000 */
+#define IAC_ISR4_IAF153               IAC_ISR4_IAF153_Msk
+#define IAC_ISR4_IAF155_Pos           (27U)
+#define IAC_ISR4_IAF155_Msk           (0x1UL << IAC_ISR4_IAF155_Pos)             /*!< 0x08000000 */
+#define IAC_ISR4_IAF155               IAC_ISR4_IAF155_Msk
+#define IAC_ISR4_IAF156_Pos           (28U)
+#define IAC_ISR4_IAF156_Msk           (0x1UL << IAC_ISR4_IAF156_Pos)             /*!< 0x10000000 */
+#define IAC_ISR4_IAF156               IAC_ISR4_IAF156_Msk
+#define IAC_ISR4_IAF157_Pos           (29U)
+#define IAC_ISR4_IAF157_Msk           (0x1UL << IAC_ISR4_IAF157_Pos)             /*!< 0x20000000 */
+#define IAC_ISR4_IAF157               IAC_ISR4_IAF157_Msk
+
+/*******************  Bits definition for IAC_ICR0 register *******************/
+#define IAC_ICR0_IACF0_Pos            (0U)
+#define IAC_ICR0_IACF0_Msk            (0x1UL << IAC_ICR0_IACF0_Pos)               /*!< 0x00000001 */
+#define IAC_ICR0_IACF0                IAC_ICR0_IACF0_Msk
+#define IAC_ICR0_IACF1_Pos            (1U)
+#define IAC_ICR0_IACF1_Msk            (0x1UL << IAC_ICR0_IACF1_Pos)               /*!< 0x00000002 */
+#define IAC_ICR0_IACF1                IAC_ICR0_IACF1_Msk
+#define IAC_ICR0_IACF2_Pos            (2U)
+#define IAC_ICR0_IACF2_Msk            (0x1UL << IAC_ICR0_IACF2_Pos)               /*!< 0x00000004 */
+#define IAC_ICR0_IACF2                IAC_ICR0_IACF2_Msk
+#define IAC_ICR0_IACF3_Pos            (3U)
+#define IAC_ICR0_IACF3_Msk            (0x1UL << IAC_ICR0_IACF3_Pos)               /*!< 0x00000008 */
+#define IAC_ICR0_IACF3                IAC_ICR0_IACF3_Msk
+#define IAC_ICR0_IACF4_Pos            (4U)
+#define IAC_ICR0_IACF4_Msk            (0x1UL << IAC_ICR0_IACF4_Pos)               /*!< 0x00000010 */
+#define IAC_ICR0_IACF4                IAC_ICR0_IACF4_Msk
+#define IAC_ICR0_IACF5_Pos            (5U)
+#define IAC_ICR0_IACF5_Msk            (0x1UL << IAC_ICR0_IACF5_Pos)               /*!< 0x00000020 */
+#define IAC_ICR0_IACF5                IAC_ICR0_IACF5_Msk
+#define IAC_ICR0_IACF6_Pos            (6U)
+#define IAC_ICR0_IACF6_Msk            (0x1UL << IAC_ICR0_IACF6_Pos)               /*!< 0x00000040 */
+#define IAC_ICR0_IACF6                IAC_ICR0_IACF6_Msk
+#define IAC_ICR0_IACF8_Pos            (8U)
+#define IAC_ICR0_IACF8_Msk            (0x1UL << IAC_ICR0_IACF8_Pos)               /*!< 0x00000100 */
+#define IAC_ICR0_IACF8                IAC_ICR0_IACF8_Msk
+#define IAC_ICR0_IACF9_Pos            (9U)
+#define IAC_ICR0_IACF9_Msk            (0x1UL << IAC_ICR0_IACF9_Pos)               /*!< 0x00000200 */
+#define IAC_ICR0_IACF9                IAC_ICR0_IACF9_Msk
+#define IAC_ICR0_IACF10_Pos           (10U)
+#define IAC_ICR0_IACF10_Msk           (0x1UL << IAC_ICR0_IACF10_Pos)              /*!< 0x00000400 */
+#define IAC_ICR0_IACF10               IAC_ICR0_IACF10_Msk
+#define IAC_ICR0_IACF11_Pos           (11U)
+#define IAC_ICR0_IACF11_Msk           (0x1UL << IAC_ICR0_IACF11_Pos)              /*!< 0x00000800 */
+#define IAC_ICR0_IACF11               IAC_ICR0_IACF11_Msk
+#define IAC_ICR0_IACF12_Pos           (12U)
+#define IAC_ICR0_IACF12_Msk           (0x1UL << IAC_ICR0_IACF12_Pos)              /*!< 0x00001000 */
+#define IAC_ICR0_IACF12               IAC_ICR0_IACF12_Msk
+#define IAC_ICR0_IACF13_Pos           (13U)
+#define IAC_ICR0_IACF13_Msk           (0x1UL << IAC_ICR0_IACF13_Pos)              /*!< 0x00002000 */
+#define IAC_ICR0_IACF13               IAC_ICR0_IACF13_Msk
+#define IAC_ICR0_IACF14_Pos           (14U)
+#define IAC_ICR0_IACF14_Msk           (0x1UL << IAC_ICR0_IACF14_Pos)              /*!< 0x00004000 */
+#define IAC_ICR0_IACF14               IAC_ICR0_IACF14_Msk
+#define IAC_ICR0_IACF15_Pos           (15U)
+#define IAC_ICR0_IACF15_Msk           (0x1UL << IAC_ICR0_IACF15_Pos)              /*!< 0x00008000 */
+#define IAC_ICR0_IACF15               IAC_ICR0_IACF15_Msk
+#define IAC_ICR0_IACF16_Pos           (16U)
+#define IAC_ICR0_IACF16_Msk           (0x1UL << IAC_ICR0_IACF16_Pos)              /*!< 0x00010000 */
+#define IAC_ICR0_IACF16               IAC_ICR0_IACF16_Msk
+#define IAC_ICR0_IACF17_Pos           (17U)
+#define IAC_ICR0_IACF17_Msk           (0x1UL << IAC_ICR0_IACF17_Pos)              /*!< 0x00020000 */
+#define IAC_ICR0_IACF17               IAC_ICR0_IACF17_Msk
+#define IAC_ICR0_IACF18_Pos           (18U)
+#define IAC_ICR0_IACF18_Msk           (0x1UL << IAC_ICR0_IACF18_Pos)              /*!< 0x00040000 */
+#define IAC_ICR0_IACF18               IAC_ICR0_IACF18_Msk
+#define IAC_ICR0_IACF19_Pos           (19U)
+#define IAC_ICR0_IACF19_Msk           (0x1UL << IAC_ICR0_IACF19_Pos)              /*!< 0x00080000 */
+#define IAC_ICR0_IACF19               IAC_ICR0_IACF19_Msk
+#define IAC_ICR0_IACF20_Pos           (20U)
+#define IAC_ICR0_IACF20_Msk           (0x1UL << IAC_ICR0_IACF20_Pos)              /*!< 0x00100000 */
+#define IAC_ICR0_IACF20               IAC_ICR0_IACF20_Msk
+#define IAC_ICR0_IACF21_Pos           (21U)
+#define IAC_ICR0_IACF21_Msk           (0x1UL << IAC_ICR0_IACF21_Pos)              /*!< 0x00200000 */
+#define IAC_ICR0_IACF21               IAC_ICR0_IACF21_Msk
+#define IAC_ICR0_IACF22_Pos           (22U)
+#define IAC_ICR0_IACF22_Msk           (0x1UL << IAC_ICR0_IACF22_Pos)              /*!< 0x00400000 */
+#define IAC_ICR0_IACF22               IAC_ICR0_IACF22_Msk
+#define IAC_ICR0_IACF23_Pos           (23U)
+#define IAC_ICR0_IACF23_Msk           (0x1UL << IAC_ICR0_IACF23_Pos)              /*!< 0x00800000 */
+#define IAC_ICR0_IACF23               IAC_ICR0_IACF23_Msk
+#define IAC_ICR0_IACF24_Pos           (24U)
+#define IAC_ICR0_IACF24_Msk           (0x1UL << IAC_ICR0_IACF24_Pos)              /*!< 0x01000000 */
+#define IAC_ICR0_IACF24               IAC_ICR0_IACF24_Msk
+#define IAC_ICR0_IACF25_Pos           (25U)
+#define IAC_ICR0_IACF25_Msk           (0x1UL << IAC_ICR0_IACF25_Pos)              /*!< 0x02000000 */
+#define IAC_ICR0_IACF25               IAC_ICR0_IACF25_Msk
+#define IAC_ICR0_IACF26_Pos           (26U)
+#define IAC_ICR0_IACF26_Msk           (0x1UL << IAC_ICR0_IACF26_Pos)              /*!< 0x04000000 */
+#define IAC_ICR0_IACF26               IAC_ICR0_IACF26_Msk
+#define IAC_ICR0_IACF27_Pos           (27U)
+#define IAC_ICR0_IACF27_Msk           (0x1UL << IAC_ICR0_IACF27_Pos)              /*!< 0x08000000 */
+#define IAC_ICR0_IACF27               IAC_ICR0_IACF27_Msk
+#define IAC_ICR0_IACF28_Pos           (28U)
+#define IAC_ICR0_IACF28_Msk           (0x1UL << IAC_ICR0_IACF28_Pos)              /*!< 0x10000000 */
+#define IAC_ICR0_IACF28               IAC_ICR0_IACF28_Msk
+#define IAC_ICR0_IACF29_Pos           (29U)
+#define IAC_ICR0_IACF29_Msk           (0x1UL << IAC_ICR0_IACF29_Pos)              /*!< 0x20000000 */
+#define IAC_ICR0_IACF29               IAC_ICR0_IACF29_Msk
+#define IAC_ICR0_IACF30_Pos           (30U)
+#define IAC_ICR0_IACF30_Msk           (0x1UL << IAC_ICR0_IACF30_Pos)              /*!< 0x40000000 */
+#define IAC_ICR0_IACF30               IAC_ICR0_IACF30_Msk
+#define IAC_ICR0_IACF31_Pos           (31U)
+#define IAC_ICR0_IACF31_Msk           (0x1UL << IAC_ICR0_IACF31_Pos)              /*!< 0x80000000 */
+#define IAC_ICR0_IACF31               IAC_ICR0_IACF31_Msk
+
+/*******************  Bits definition for IAC_ICR1 register *******************/
+#define IAC_ICR1_IACF32_Pos           (0U)
+#define IAC_ICR1_IACF32_Msk           (0x1UL << IAC_ICR1_IACF32_Pos)              /*!< 0x00000001 */
+#define IAC_ICR1_IACF32               IAC_ICR1_IACF32_Msk
+#define IAC_ICR1_IACF33_Pos           (1U)
+#define IAC_ICR1_IACF33_Msk           (0x1UL << IAC_ICR1_IACF33_Pos)              /*!< 0x00000002 */
+#define IAC_ICR1_IACF33               IAC_ICR1_IACF33_Msk
+#define IAC_ICR1_IACF34_Pos           (2U)
+#define IAC_ICR1_IACF34_Msk           (0x1UL << IAC_ICR1_IACF34_Pos)              /*!< 0x00000004 */
+#define IAC_ICR1_IACF34               IAC_ICR1_IACF34_Msk
+#define IAC_ICR1_IACF35_Pos           (3U)
+#define IAC_ICR1_IACF35_Msk           (0x1UL << IAC_ICR1_IACF35_Pos)              /*!< 0x00000008 */
+#define IAC_ICR1_IACF35               IAC_ICR1_IACF35_Msk
+#define IAC_ICR1_IACF36_Pos           (4U)
+#define IAC_ICR1_IACF36_Msk           (0x1UL << IAC_ICR1_IACF36_Pos)              /*!< 0x00000010 */
+#define IAC_ICR1_IACF36               IAC_ICR1_IACF36_Msk
+#define IAC_ICR1_IACF37_Pos           (5U)
+#define IAC_ICR1_IACF37_Msk           (0x1UL << IAC_ICR1_IACF37_Pos)              /*!< 0x00000020 */
+#define IAC_ICR1_IACF37               IAC_ICR1_IACF37_Msk
+#define IAC_ICR1_IACF38_Pos           (6U)
+#define IAC_ICR1_IACF38_Msk           (0x1UL << IAC_ICR1_IACF38_Pos)              /*!< 0x00000040 */
+#define IAC_ICR1_IACF38               IAC_ICR1_IACF38_Msk
+#define IAC_ICR1_IACF39_Pos           (7U)
+#define IAC_ICR1_IACF39_Msk           (0x1UL << IAC_ICR1_IACF39_Pos)              /*!< 0x00000080 */
+#define IAC_ICR1_IACF39               IAC_ICR1_IACF39_Msk
+#define IAC_ICR1_IACF40_Pos           (8U)
+#define IAC_ICR1_IACF40_Msk           (0x1UL << IAC_ICR1_IACF40_Pos)              /*!< 0x00000100 */
+#define IAC_ICR1_IACF40               IAC_ICR1_IACF40_Msk
+#define IAC_ICR1_IACF41_Pos           (9U)
+#define IAC_ICR1_IACF41_Msk           (0x1UL << IAC_ICR1_IACF41_Pos)              /*!< 0x00000200 */
+#define IAC_ICR1_IACF41               IAC_ICR1_IACF41_Msk
+#define IAC_ICR1_IACF42_Pos           (10U)
+#define IAC_ICR1_IACF42_Msk           (0x1UL << IAC_ICR1_IACF42_Pos)              /*!< 0x00000400 */
+#define IAC_ICR1_IACF42               IAC_ICR1_IACF42_Msk
+#define IAC_ICR1_IACF43_Pos           (11U)
+#define IAC_ICR1_IACF43_Msk           (0x1UL << IAC_ICR1_IACF43_Pos)              /*!< 0x00000800 */
+#define IAC_ICR1_IACF43               IAC_ICR1_IACF43_Msk
+#define IAC_ICR1_IACF44_Pos           (12U)
+#define IAC_ICR1_IACF44_Msk           (0x1UL << IAC_ICR1_IACF44_Pos)              /*!< 0x00001000 */
+#define IAC_ICR1_IACF44               IAC_ICR1_IACF44_Msk
+#define IAC_ICR1_IACF45_Pos           (13U)
+#define IAC_ICR1_IACF45_Msk           (0x1UL << IAC_ICR1_IACF45_Pos)              /*!< 0x00002000 */
+#define IAC_ICR1_IACF45               IAC_ICR1_IACF45_Msk
+#define IAC_ICR1_IACF46_Pos           (14U)
+#define IAC_ICR1_IACF46_Msk           (0x1UL << IAC_ICR1_IACF46_Pos)              /*!< 0x00004000 */
+#define IAC_ICR1_IACF46               IAC_ICR1_IACF46_Msk
+#define IAC_ICR1_IACF47_Pos           (15U)
+#define IAC_ICR1_IACF47_Msk           (0x1UL << IAC_ICR1_IACF47_Pos)              /*!< 0x00008000 */
+#define IAC_ICR1_IACF47               IAC_ICR1_IACF47_Msk
+#define IAC_ICR1_IACF48_Pos           (16U)
+#define IAC_ICR1_IACF48_Msk           (0x1UL << IAC_ICR1_IACF48_Pos)              /*!< 0x00010000 */
+#define IAC_ICR1_IACF48               IAC_ICR1_IACF48_Msk
+#define IAC_ICR1_IACF49_Pos           (17U)
+#define IAC_ICR1_IACF49_Msk           (0x1UL << IAC_ICR1_IACF49_Pos)              /*!< 0x00020000 */
+#define IAC_ICR1_IACF49               IAC_ICR1_IACF49_Msk
+#define IAC_ICR1_IACF50_Pos           (18U)
+#define IAC_ICR1_IACF50_Msk           (0x1UL << IAC_ICR1_IACF50_Pos)              /*!< 0x00040000 */
+#define IAC_ICR1_IACF50               IAC_ICR1_IACF50_Msk
+#define IAC_ICR1_IACF51_Pos           (19U)
+#define IAC_ICR1_IACF51_Msk           (0x1UL << IAC_ICR1_IACF51_Pos)              /*!< 0x00080000 */
+#define IAC_ICR1_IACF51               IAC_ICR1_IACF51_Msk
+#define IAC_ICR1_IACF52_Pos           (20U)
+#define IAC_ICR1_IACF52_Msk           (0x1UL << IAC_ICR1_IACF52_Pos)              /*!< 0x00100000 */
+#define IAC_ICR1_IACF52               IAC_ICR1_IACF52_Msk
+#define IAC_ICR1_IACF53_Pos           (21U)
+#define IAC_ICR1_IACF53_Msk           (0x1UL << IAC_ICR1_IACF53_Pos)              /*!< 0x00200000 */
+#define IAC_ICR1_IACF53               IAC_ICR1_IACF53_Msk
+#define IAC_ICR1_IACF54_Pos           (22U)
+#define IAC_ICR1_IACF54_Msk           (0x1UL << IAC_ICR1_IACF54_Pos)              /*!< 0x00400000 */
+#define IAC_ICR1_IACF54               IAC_ICR1_IACF54_Msk
+#define IAC_ICR1_IACF55_Pos           (23U)
+#define IAC_ICR1_IACF55_Msk           (0x1UL << IAC_ICR1_IACF55_Pos)              /*!< 0x00800000 */
+#define IAC_ICR1_IACF55               IAC_ICR1_IACF55_Msk
+#define IAC_ICR1_IACF56_Pos           (24U)
+#define IAC_ICR1_IACF56_Msk           (0x1UL << IAC_ICR1_IACF56_Pos)              /*!< 0x01000000 */
+#define IAC_ICR1_IACF56               IAC_ICR1_IACF56_Msk
+#define IAC_ICR1_IACF57_Pos           (25U)
+#define IAC_ICR1_IACF57_Msk           (0x1UL << IAC_ICR1_IACF57_Pos)              /*!< 0x02000000 */
+#define IAC_ICR1_IACF57               IAC_ICR1_IACF57_Msk
+#define IAC_ICR1_IACF58_Pos           (26U)
+#define IAC_ICR1_IACF58_Msk           (0x1UL << IAC_ICR1_IACF58_Pos)              /*!< 0x04000000 */
+#define IAC_ICR1_IACF58               IAC_ICR1_IACF58_Msk
+#define IAC_ICR1_IACF60_Pos           (28U)
+#define IAC_ICR1_IACF60_Msk           (0x1UL << IAC_ICR1_IACF60_Pos)              /*!< 0x10000000 */
+#define IAC_ICR1_IACF60               IAC_ICR1_IACF60_Msk
+#define IAC_ICR1_IACF61_Pos           (29U)
+#define IAC_ICR1_IACF61_Msk           (0x1UL << IAC_ICR1_IACF61_Pos)              /*!< 0x20000000 */
+#define IAC_ICR1_IACF61               IAC_ICR1_IACF61_Msk
+#define IAC_ICR1_IACF62_Pos           (30U)
+#define IAC_ICR1_IACF62_Msk           (0x1UL << IAC_ICR1_IACF62_Pos)              /*!< 0x40000000 */
+#define IAC_ICR1_IACF62               IAC_ICR1_IACF62_Msk
+
+/*******************  Bits definition for IAC_ICR2 register *******************/
+#define IAC_ICR2_IACF64_Pos           (0U)
+#define IAC_ICR2_IACF64_Msk           (0x1UL << IAC_ICR2_IACF64_Pos)              /*!< 0x00000001 */
+#define IAC_ICR2_IACF64               IAC_ICR2_IACF64_Msk
+#define IAC_ICR2_IACF65_Pos           (1U)
+#define IAC_ICR2_IACF65_Msk           (0x1UL << IAC_ICR2_IACF65_Pos)              /*!< 0x00000002 */
+#define IAC_ICR2_IACF65               IAC_ICR2_IACF65_Msk
+#define IAC_ICR2_IACF67_Pos           (3U)
+#define IAC_ICR2_IACF67_Msk           (0x1UL << IAC_ICR2_IACF67_Pos)              /*!< 0x00000008 */
+#define IAC_ICR2_IACF67               IAC_ICR2_IACF67_Msk
+#define IAC_ICR2_IACF68_Pos           (4U)
+#define IAC_ICR2_IACF68_Msk           (0x1UL << IAC_ICR2_IACF68_Pos)              /*!< 0x00000010 */
+#define IAC_ICR2_IACF68               IAC_ICR2_IACF68_Msk
+#define IAC_ICR2_IACF69_Pos           (5U)
+#define IAC_ICR2_IACF69_Msk           (0x1UL << IAC_ICR2_IACF69_Pos)              /*!< 0x00000020 */
+#define IAC_ICR2_IACF69               IAC_ICR2_IACF69_Msk
+#define IAC_ICR2_IACF76_Pos           (12U)
+#define IAC_ICR2_IACF76_Msk           (0x1UL << IAC_ICR2_IACF76_Pos)              /*!< 0x00001000 */
+#define IAC_ICR2_IACF76               IAC_ICR2_IACF76_Msk
+#define IAC_ICR2_IACF77_Pos           (13U)
+#define IAC_ICR2_IACF77_Msk           (0x1UL << IAC_ICR2_IACF77_Pos)              /*!< 0x00002000 */
+#define IAC_ICR2_IACF77               IAC_ICR2_IACF77_Msk
+#define IAC_ICR2_IACF78_Pos           (14U)
+#define IAC_ICR2_IACF78_Msk           (0x1UL << IAC_ICR2_IACF78_Pos)              /*!< 0x00004000 */
+#define IAC_ICR2_IACF78               IAC_ICR2_IACF78_Msk
+#define IAC_ICR2_IACF79_Pos           (15U)
+#define IAC_ICR2_IACF79_Msk           (0x1UL << IAC_ICR2_IACF79_Pos)              /*!< 0x00008000 */
+#define IAC_ICR2_IACF79               IAC_ICR2_IACF79_Msk
+#define IAC_ICR2_IACF80_Pos           (16U)
+#define IAC_ICR2_IACF80_Msk           (0x1UL << IAC_ICR2_IACF80_Pos)              /*!< 0x00010000 */
+#define IAC_ICR2_IACF80               IAC_ICR2_IACF80_Msk
+#define IAC_ICR2_IACF81_Pos           (17U)
+#define IAC_ICR2_IACF81_Msk           (0x1UL << IAC_ICR2_IACF81_Pos)              /*!< 0x00020000 */
+#define IAC_ICR2_IACF81               IAC_ICR2_IACF81_Msk
+#define IAC_ICR2_IACF82_Pos           (18U)
+#define IAC_ICR2_IACF82_Msk           (0x1UL << IAC_ICR2_IACF82_Pos)              /*!< 0x00040000 */
+#define IAC_ICR2_IACF82               IAC_ICR2_IACF82_Msk
+#define IAC_ICR2_IACF83_Pos           (19U)
+#define IAC_ICR2_IACF83_Msk           (0x1UL << IAC_ICR2_IACF83_Pos)              /*!< 0x00080000 */
+#define IAC_ICR2_IACF83               IAC_ICR2_IACF83_Msk
+#define IAC_ICR2_IACF84_Pos           (20U)
+#define IAC_ICR2_IACF84_Msk           (0x1UL << IAC_ICR2_IACF84_Pos)              /*!< 0x00100000 */
+#define IAC_ICR2_IACF84               IAC_ICR2_IACF84_Msk
+#define IAC_ICR2_IACF86_Pos           (22U)
+#define IAC_ICR2_IACF86_Msk           (0x1UL << IAC_ICR2_IACF86_Pos)              /*!< 0x00400000 */
+#define IAC_ICR2_IACF86               IAC_ICR2_IACF86_Msk
+#define IAC_ICR2_IACF87_Pos           (23U)
+#define IAC_ICR2_IACF87_Msk           (0x1UL << IAC_ICR2_IACF87_Pos)              /*!< 0x00800000 */
+#define IAC_ICR2_IACF87               IAC_ICR2_IACF87_Msk
+#define IAC_ICR2_IACF88_Pos           (24U)
+#define IAC_ICR2_IACF88_Msk           (0x1UL << IAC_ICR2_IACF88_Pos)              /*!< 0x01000000 */
+#define IAC_ICR2_IACF88               IAC_ICR2_IACF88_Msk
+#define IAC_ICR2_IACF89_Pos           (25U)
+#define IAC_ICR2_IACF89_Msk           (0x1UL << IAC_ICR2_IACF89_Pos)              /*!< 0x02000000 */
+#define IAC_ICR2_IACF89               IAC_ICR2_IACF89_Msk
+#define IAC_ICR2_IACF90_Pos           (26U)
+#define IAC_ICR2_IACF90_Msk           (0x1UL << IAC_ICR2_IACF90_Pos)              /*!< 0x04000000 */
+#define IAC_ICR2_IACF90               IAC_ICR2_IACF90_Msk
+#define IAC_ICR2_IACF92_Pos           (28U)
+#define IAC_ICR2_IACF92_Msk           (0x1UL << IAC_ICR2_IACF92_Pos)              /*!< 0x10000000 */
+#define IAC_ICR2_IACF92               IAC_ICR2_IACF92_Msk
+#define IAC_ICR2_IACF93_Pos           (29U)
+#define IAC_ICR2_IACF93_Msk           (0x1UL << IAC_ICR2_IACF93_Pos)              /*!< 0x20000000 */
+#define IAC_ICR2_IACF93               IAC_ICR2_IACF93_Msk
+#define IAC_ICR2_IACF94_Pos           (30U)
+#define IAC_ICR2_IACF94_Msk           (0x1UL << IAC_ICR2_IACF94_Pos)              /*!< 0x40000000 */
+#define IAC_ICR2_IACF94               IAC_ICR2_IACF94_Msk
+#define IAC_ICR2_IACF95_Pos           (31U)
+#define IAC_ICR2_IACF95_Msk           (0x1UL << IAC_ICR2_IACF95_Pos)              /*!< 0x80000000 */
+#define IAC_ICR2_IACF95               IAC_ICR2_IACF95_Msk
+
+/*******************  Bits definition for IAC_ICR3 register *******************/
+#define IAC_ICR3_IACF96_Pos           (0U)
+#define IAC_ICR3_IACF96_Msk           (0x1UL << IAC_ICR3_IACF96_Pos)              /*!< 0x00000001 */
+#define IAC_ICR3_IACF96               IAC_ICR3_IACF96_Msk
+#define IAC_ICR3_IACF97_Pos           (1U)
+#define IAC_ICR3_IACF97_Msk           (0x1UL << IAC_ICR3_IACF97_Pos)              /*!< 0x00000002 */
+#define IAC_ICR3_IACF97               IAC_ICR3_IACF97_Msk
+#define IAC_ICR3_IACF98_Pos           (2U)
+#define IAC_ICR3_IACF98_Msk           (0x1UL << IAC_ICR3_IACF98_Pos)              /*!< 0x00000004 */
+#define IAC_ICR3_IACF98               IAC_ICR3_IACF98_Msk
+#define IAC_ICR3_IACF99_Pos           (3U)
+#define IAC_ICR3_IACF99_Msk           (0x1UL << IAC_ICR3_IACF99_Pos)              /*!< 0x00000008 */
+#define IAC_ICR3_IACF99               IAC_ICR3_IACF99_Msk
+#define IAC_ICR3_IACF100_Pos          (4U)
+#define IAC_ICR3_IACF100_Msk          (0x1UL << IAC_ICR3_IACF100_Pos)             /*!< 0x00000010 */
+#define IAC_ICR3_IACF100              IAC_ICR3_IACF100_Msk
+#define IAC_ICR3_IACF101_Pos          (5U)
+#define IAC_ICR3_IACF101_Msk          (0x1UL << IAC_ICR3_IACF101_Pos)             /*!< 0x00000020 */
+#define IAC_ICR3_IACF101              IAC_ICR3_IACF101_Msk
+#define IAC_ICR3_IACF102_Pos          (6U)
+#define IAC_ICR3_IACF102_Msk          (0x1UL << IAC_ICR3_IACF102_Pos)             /*!< 0x00000040 */
+#define IAC_ICR3_IACF102              IAC_ICR3_IACF102_Msk
+#define IAC_ICR3_IACF103_Pos          (7U)
+#define IAC_ICR3_IACF103_Msk          (0x1UL << IAC_ICR3_IACF103_Pos)             /*!< 0x00000080 */
+#define IAC_ICR3_IACF103              IAC_ICR3_IACF103_Msk
+#define IAC_ICR3_IACF104_Pos          (8U)
+#define IAC_ICR3_IACF104_Msk          (0x1UL << IAC_ICR3_IACF104_Pos)             /*!< 0x00000100 */
+#define IAC_ICR3_IACF104              IAC_ICR3_IACF104_Msk
+#define IAC_ICR3_IACF106_Pos          (10U)
+#define IAC_ICR3_IACF106_Msk          (0x1UL << IAC_ICR3_IACF106_Pos)             /*!< 0x00000400 */
+#define IAC_ICR3_IACF106              IAC_ICR3_IACF106_Msk
+
+/*******************  Bits definition for IAC_ICR4 register *******************/
+#define IAC_ICR4_IACF128_Pos          (0U)
+#define IAC_ICR4_IACF128_Msk          (0x1UL << IAC_ICR4_IACF128_Pos)             /*!< 0x00000001 */
+#define IAC_ICR4_IACF128              IAC_ICR4_IACF128_Msk
+#define IAC_ICR4_IACF129_Pos          (1U)
+#define IAC_ICR4_IACF129_Msk          (0x1UL << IAC_ICR4_IACF129_Pos)             /*!< 0x00000002 */
+#define IAC_ICR4_IACF129              IAC_ICR4_IACF129_Msk
+#define IAC_ICR4_IACF130_Pos          (2U)
+#define IAC_ICR4_IACF130_Msk          (0x1UL << IAC_ICR4_IACF130_Pos)             /*!< 0x00000004 */
+#define IAC_ICR4_IACF130              IAC_ICR4_IACF130_Msk
+#define IAC_ICR4_IACF131_Pos          (3U)
+#define IAC_ICR4_IACF131_Msk          (0x1UL << IAC_ICR4_IACF131_Pos)             /*!< 0x00000008 */
+#define IAC_ICR4_IACF131              IAC_ICR4_IACF131_Msk
+#define IAC_ICR4_IACF133_Pos          (5U)
+#define IAC_ICR4_IACF133_Msk          (0x1UL << IAC_ICR4_IACF133_Pos)             /*!< 0x00000020 */
+#define IAC_ICR4_IACF133              IAC_ICR4_IACF133_Msk
+#define IAC_ICR4_IACF134_Pos          (6U)
+#define IAC_ICR4_IACF134_Msk          (0x1UL << IAC_ICR4_IACF134_Pos)             /*!< 0x00000040 */
+#define IAC_ICR4_IACF134              IAC_ICR4_IACF134_Msk
+#define IAC_ICR4_IACF135_Pos          (7U)
+#define IAC_ICR4_IACF135_Msk          (0x1UL << IAC_ICR4_IACF135_Pos)             /*!< 0x00000080 */
+#define IAC_ICR4_IACF135              IAC_ICR4_IACF135_Msk
+#define IAC_ICR4_IACF136_Pos          (8U)
+#define IAC_ICR4_IACF136_Msk          (0x1UL << IAC_ICR4_IACF136_Pos)             /*!< 0x00000100 */
+#define IAC_ICR4_IACF136              IAC_ICR4_IACF136_Msk
+#define IAC_ICR4_IACF137_Pos          (9U)
+#define IAC_ICR4_IACF137_Msk          (0x1UL << IAC_ICR4_IACF137_Pos)             /*!< 0x00000200 */
+#define IAC_ICR4_IACF137              IAC_ICR4_IACF137_Msk
+#define IAC_ICR4_IACF138_Pos          (10U)
+#define IAC_ICR4_IACF138_Msk          (0x1UL << IAC_ICR4_IACF138_Pos)             /*!< 0x00000400 */
+#define IAC_ICR4_IACF138              IAC_ICR4_IACF138_Msk
+#define IAC_ICR4_IACF139_Pos          (11U)
+#define IAC_ICR4_IACF139_Msk          (0x1UL << IAC_ICR4_IACF139_Pos)             /*!< 0x00000800 */
+#define IAC_ICR4_IACF139              IAC_ICR4_IACF139_Msk
+#define IAC_ICR4_IACF140_Pos          (12U)
+#define IAC_ICR4_IACF140_Msk          (0x1UL << IAC_ICR4_IACF140_Pos)             /*!< 0x00001000 */
+#define IAC_ICR4_IACF140              IAC_ICR4_IACF140_Msk
+#define IAC_ICR4_IACF141_Pos          (13U)
+#define IAC_ICR4_IACF141_Msk          (0x1UL << IAC_ICR4_IACF141_Pos)             /*!< 0x00002000 */
+#define IAC_ICR4_IACF141              IAC_ICR4_IACF141_Msk
+#define IAC_ICR4_IACF142_Pos          (14U)
+#define IAC_ICR4_IACF142_Msk          (0x1UL << IAC_ICR4_IACF142_Pos)             /*!< 0x00004000 */
+#define IAC_ICR4_IACF142              IAC_ICR4_IACF142_Msk
+#define IAC_ICR4_IACF143_Pos          (15U)
+#define IAC_ICR4_IACF143_Msk          (0x1UL << IAC_ICR4_IACF143_Pos)             /*!< 0x00008000 */
+#define IAC_ICR4_IACF143              IAC_ICR4_IACF143_Msk
+#define IAC_ICR4_IACF144_Pos          (16U)
+#define IAC_ICR4_IACF144_Msk          (0x1UL << IAC_ICR4_IACF144_Pos)             /*!< 0x00010000 */
+#define IAC_ICR4_IACF144              IAC_ICR4_IACF144_Msk
+#define IAC_ICR4_IACF145_Pos          (17U)
+#define IAC_ICR4_IACF145_Msk          (0x1UL << IAC_ICR4_IACF145_Pos)             /*!< 0x00020000 */
+#define IAC_ICR4_IACF145              IAC_ICR4_IACF145_Msk
+#define IAC_ICR4_IACF146_Pos          (18U)
+#define IAC_ICR4_IACF146_Msk          (0x1UL << IAC_ICR4_IACF146_Pos)             /*!< 0x00040000 */
+#define IAC_ICR4_IACF146              IAC_ICR4_IACF146_Msk
+#define IAC_ICR4_IACF147_Pos          (19U)
+#define IAC_ICR4_IACF147_Msk          (0x1UL << IAC_ICR4_IACF147_Pos)             /*!< 0x00080000 */
+#define IAC_ICR4_IACF147              IAC_ICR4_IACF147_Msk
+#define IAC_ICR4_IACF149_Pos          (21U)
+#define IAC_ICR4_IACF149_Msk          (0x1UL << IAC_ICR4_IACF149_Pos)             /*!< 0x00200000 */
+#define IAC_ICR4_IACF149              IAC_ICR4_IACF149_Msk
+#define IAC_ICR4_IACF150_Pos          (22U)
+#define IAC_ICR4_IACF150_Msk          (0x1UL << IAC_ICR4_IACF150_Pos)             /*!< 0x00400000 */
+#define IAC_ICR4_IACF150              IAC_ICR4_IACF150_Msk
+#define IAC_ICR4_IACF151_Pos          (23U)
+#define IAC_ICR4_IACF151_Msk          (0x1UL << IAC_ICR4_IACF151_Pos)             /*!< 0x00800000 */
+#define IAC_ICR4_IACF151              IAC_ICR4_IACF151_Msk
+#define IAC_ICR4_IACF152_Pos          (24U)
+#define IAC_ICR4_IACF152_Msk          (0x1UL << IAC_ICR4_IACF152_Pos)             /*!< 0x01000000 */
+#define IAC_ICR4_IACF152              IAC_ICR4_IACF152_Msk
+#define IAC_ICR4_IACF153_Pos          (25U)
+#define IAC_ICR4_IACF153_Msk          (0x1UL << IAC_ICR4_IACF153_Pos)             /*!< 0x02000000 */
+#define IAC_ICR4_IACF153              IAC_ICR4_IACF153_Msk
+#define IAC_ICR4_IACF155_Pos          (27U)
+#define IAC_ICR4_IACF155_Msk          (0x1UL << IAC_ICR4_IACF155_Pos)             /*!< 0x08000000 */
+#define IAC_ICR4_IACF155              IAC_ICR4_IACF155_Msk
+#define IAC_ICR4_IACF156_Pos          (28U)
+#define IAC_ICR4_IACF156_Msk          (0x1UL << IAC_ICR4_IACF156_Pos)             /*!< 0x10000000 */
+#define IAC_ICR4_IACF156              IAC_ICR4_IACF156_Msk
+#define IAC_ICR4_IACF157_Pos          (29U)
+#define IAC_ICR4_IACF157_Msk          (0x1UL << IAC_ICR4_IACF157_Pos)             /*!< 0x20000000 */
+#define IAC_ICR4_IACF157              IAC_ICR4_IACF157_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 ICACHE                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for ICACHE_CR register  *******************/
+#define ICACHE_CR_EN_Pos               (0U)
+#define ICACHE_CR_EN_Msk               (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
+#define ICACHE_CR_EN                   ICACHE_CR_EN_Msk                        /*!< Enable */
+#define ICACHE_CR_CACHEINV_Pos         (1U)
+#define ICACHE_CR_CACHEINV_Msk         (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
+#define ICACHE_CR_CACHEINV             ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
+#define ICACHE_CR_WAYSEL_Pos           (2U)
+#define ICACHE_CR_WAYSEL_Msk           (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
+#define ICACHE_CR_WAYSEL               ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
+#define ICACHE_CR_HITMEN_Pos           (16U)
+#define ICACHE_CR_HITMEN_Msk           (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
+#define ICACHE_CR_HITMEN               ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
+#define ICACHE_CR_MISSMEN_Pos          (17U)
+#define ICACHE_CR_MISSMEN_Msk          (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
+#define ICACHE_CR_MISSMEN              ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
+#define ICACHE_CR_HITMRST_Pos          (18U)
+#define ICACHE_CR_HITMRST_Msk          (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
+#define ICACHE_CR_HITMRST              ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
+#define ICACHE_CR_MISSMRST_Pos         (19U)
+#define ICACHE_CR_MISSMRST_Msk         (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
+#define ICACHE_CR_MISSMRST             ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
+
+/******************  Bit definition for ICACHE_SR register  *******************/
+#define ICACHE_SR_BUSYF_Pos            (0U)
+#define ICACHE_SR_BUSYF_Msk            (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
+#define ICACHE_SR_BUSYF                ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
+#define ICACHE_SR_BSYENDF_Pos          (1U)
+#define ICACHE_SR_BSYENDF_Msk          (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
+#define ICACHE_SR_BSYENDF              ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
+#define ICACHE_SR_ERRF_Pos             (2U)
+#define ICACHE_SR_ERRF_Msk             (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
+#define ICACHE_SR_ERRF                 ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
+
+/******************  Bit definition for ICACHE_IER register  ******************/
+#define ICACHE_IER_BSYENDIE_Pos        (1U)
+#define ICACHE_IER_BSYENDIE_Msk        (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
+#define ICACHE_IER_BSYENDIE            ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
+#define ICACHE_IER_ERRIE_Pos           (2U)
+#define ICACHE_IER_ERRIE_Msk           (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
+#define ICACHE_IER_ERRIE               ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
+
+/******************  Bit definition for ICACHE_FCR register  ******************/
+#define ICACHE_FCR_CBSYENDF_Pos        (1U)
+#define ICACHE_FCR_CBSYENDF_Msk        (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
+#define ICACHE_FCR_CBSYENDF            ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
+#define ICACHE_FCR_CERRF_Pos           (2U)
+#define ICACHE_FCR_CERRF_Msk           (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
+#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
+
+/******************  Bit definition for ICACHE_HMONR register  ****************/
+#define ICACHE_HMONR_HITMON_Pos         (0U)
+#define ICACHE_HMONR_HITMON_Msk         (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)/*!< 0xFFFFFFFF */
+#define ICACHE_HMONR_HITMON             ICACHE_HMONR_HITMON_Msk                /*!< Cache hit monitor register */
+
+/******************  Bit definition for ICACHE_MMONR register  ****************/
+#define ICACHE_MMONR_MISSMON_Pos        (0U)
+#define ICACHE_MMONR_MISSMON_Msk        (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
+#define ICACHE_MMONR_MISSMON            ICACHE_MMONR_MISSMON_Msk               /*!< Cache miss monitor register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent Watchdog (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos             (0U)
+#define IWDG_KR_KEY_Msk             (0xFFFFUL << IWDG_KR_KEY_Pos)          /*!< 0x0000FFFF */
+#define IWDG_KR_KEY                 IWDG_KR_KEY_Msk                       /*!< Key value (write only, read 0x0000) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos              (0U)
+#define IWDG_PR_PR_Msk              (0xFUL << IWDG_PR_PR_Pos)              /*!< 0x0000000F */
+#define IWDG_PR_PR                  IWDG_PR_PR_Msk                        /*!< Prescaler divider */
+#define IWDG_PR_PR_0                (0x1UL << IWDG_PR_PR_Pos)              /*!< 0x00000001 */
+#define IWDG_PR_PR_1                (0x2UL << IWDG_PR_PR_Pos)              /*!< 0x00000002 */
+#define IWDG_PR_PR_2                (0x4UL << IWDG_PR_PR_Pos)              /*!< 0x00000004 */
+#define IWDG_PR_PR_3                (0x8UL << IWDG_PR_PR_Pos)              /*!< 0x00000008 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos             (0U)
+#define IWDG_RLR_RL_Msk             (0xFFFUL << IWDG_RLR_RL_Pos)           /*!< 0x00000FFF */
+#define IWDG_RLR_RL                 IWDG_RLR_RL_Msk                       /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos             (0U)
+#define IWDG_SR_PVU_Msk             (0x1UL << IWDG_SR_PVU_Pos)             /*!< 0x00000001 */
+#define IWDG_SR_PVU                 IWDG_SR_PVU_Msk                       /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos             (1U)
+#define IWDG_SR_RVU_Msk             (0x1UL << IWDG_SR_RVU_Pos)             /*!< 0x00000002 */
+#define IWDG_SR_RVU                 IWDG_SR_RVU_Msk                       /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos             (2U)
+#define IWDG_SR_WVU_Msk             (0x1UL << IWDG_SR_WVU_Pos)             /*!< 0x00000004 */
+#define IWDG_SR_WVU                 IWDG_SR_WVU_Msk                       /*!< Watchdog counter window value update */
+#define IWDG_SR_EWU_Pos             (3U)
+#define IWDG_SR_EWU_Msk             (0x1UL << IWDG_SR_EWU_Pos)             /*!< 0x00000008 */
+#define IWDG_SR_EWU                 IWDG_SR_EWU_Msk                       /*!< Watchdog interrupt comparator value update */
+#define IWDG_SR_ONF_Pos             (8U)
+#define IWDG_SR_ONF_Msk             (0x1UL << IWDG_SR_ONF_Pos)             /*!< 0x00000100 */
+#define IWDG_SR_ONF                 IWDG_SR_ONF_Msk                       /*!< Watchdog Enable status bit */
+#define IWDG_SR_EWIF_Pos            (15U)
+#define IWDG_SR_EWIF_Msk            (0x1UL << IWDG_SR_EWIF_Pos)            /*!< 0x00008000 */
+#define IWDG_SR_EWIF                IWDG_SR_EWIF_Msk                      /*!< Watchdog Early Interrupt flag */
+
+/******************  Bit definition for IWDG_WINR register  *******************/
+#define IWDG_WINR_WIN_Pos           (0U)
+#define IWDG_WINR_WIN_Msk           (0xFFFUL << IWDG_WINR_WIN_Pos)         /*!< 0x00000FFF */
+#define IWDG_WINR_WIN               IWDG_WINR_WIN_Msk                     /*!< Watchdog counter window value */
+
+/******************  Bit definition for IWDG_EWCR register  *******************/
+#define IWDG_EWCR_EWIT_Pos          (0U)
+#define IWDG_EWCR_EWIT_Msk          (0xFFFUL << IWDG_EWCR_EWIT_Pos)        /*!< 0x00000FFF */
+#define IWDG_EWCR_EWIT              IWDG_EWCR_EWIT_Msk                    /*!< Watchdog counter window value */
+#define IWDG_EWCR_EWIE_Pos          (15U)
+#define IWDG_EWCR_EWIE_Msk          (0x1UL << IWDG_EWCR_EWIE_Pos)          /*!< 0x00008000 */
+#define IWDG_EWCR_EWIE              IWDG_EWCR_EWIE_Msk                    /*!< Watchdog early interrupt enable */
+
+/*******************  Bit definition for IWDG_ICR register  *******************/
+#define IWDG_ICR_EWIC_Pos           (15U)
+#define IWDG_ICR_EWIC_Msk           (0x1UL << IWDG_ICR_EWIC_Pos)           /*!< 0x00008000 */
+#define IWDG_ICR_EWIC               IWDG_ICR_EWIC_Msk                     /*!< Watchdog early interrupt acknowledge */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)         /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                    /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                       /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                       /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk               /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)            /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                       /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                      /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                    /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)    /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                     /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                    /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                      /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                      /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)              /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                         /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)             /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                        /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)            /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                       /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)             /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                        /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)            /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                       /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)             /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                        /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)             /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                        /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IDMAEN_Pos              (11U)
+#define JPEG_CR_IDMAEN_Msk              (0x1UL << JPEG_CR_IDMAEN_Pos)            /*!< 0x00000800 */
+#define JPEG_CR_IDMAEN                  JPEG_CR_IDMAEN_Msk                       /*!<Input DMA enable */
+#define JPEG_CR_ODMAEN_Pos              (12U)
+#define JPEG_CR_ODMAEN_Msk              (0x1UL << JPEG_CR_ODMAEN_Pos)            /*!< 0x00001000 */
+#define JPEG_CR_ODMAEN                  JPEG_CR_ODMAEN_Msk                       /*!<Output DMA enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)               /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                          /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)               /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                          /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)              /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                         /*!<Input FIFO is not full and is below its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)             /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                        /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)              /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                         /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)             /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                        /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)              /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                         /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)              /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                         /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)               /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                          /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (5U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                       /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (6U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                       /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)    /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                      /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)   /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                     /*!<Data Output FIFO */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                            */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CC1IF_Pos         (0U)
+#define LPTIM_ISR_CC1IF_Msk         (0x1UL << LPTIM_ISR_CC1IF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ISR_CC1IF             LPTIM_ISR_CC1IF_Msk                        /*!< Capture/Compare 1 interrupt flag */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMP1OK_Pos        (3U)
+#define LPTIM_ISR_CMP1OK_Msk        (0x1UL << LPTIM_ISR_CMP1OK_Pos)            /*!< 0x00000008 */
+#define LPTIM_ISR_CMP1OK            LPTIM_ISR_CMP1OK_Msk                       /*!< Compare register 1 update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+#define LPTIM_ISR_UE_Pos            (7U)
+#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
+#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
+#define LPTIM_ISR_REPOK_Pos         (8U)
+#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
+#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
+#define LPTIM_ISR_CC2IF_Pos         (9U)
+#define LPTIM_ISR_CC2IF_Msk         (0x1UL << LPTIM_ISR_CC2IF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ISR_CC2IF             LPTIM_ISR_CC2IF_Msk                        /*!< Capture/Compare 2 interrupt flag */
+#define LPTIM_ISR_CC1OF_Pos         (12U)
+#define LPTIM_ISR_CC1OF_Msk         (0x1UL << LPTIM_ISR_CC1OF_Pos)             /*!< 0x00001000 */
+#define LPTIM_ISR_CC1OF             LPTIM_ISR_CC1OF_Msk                        /*!< Capture/Compare 1 over-capture flag */
+#define LPTIM_ISR_CC2OF_Pos         (13U)
+#define LPTIM_ISR_CC2OF_Msk         (0x1UL << LPTIM_ISR_CC2OF_Pos)             /*!< 0x00002000 */
+#define LPTIM_ISR_CC2OF             LPTIM_ISR_CC2OF_Msk                        /*!< Capture/Compare 2 over-capture flag */
+#define LPTIM_ISR_CMP2OK_Pos        (19U)
+#define LPTIM_ISR_CMP2OK_Msk        (0x1UL << LPTIM_ISR_CMP2OK_Pos)            /*!< 0x00080000 */
+#define LPTIM_ISR_CMP2OK            LPTIM_ISR_CMP2OK_Msk                       /*!< Compare register 2 update OK */
+#define LPTIM_ISR_DIEROK_Pos        (24U)
+#define LPTIM_ISR_DIEROK_Msk        (0x1UL << LPTIM_ISR_DIEROK_Pos)            /*!< 0x01000000 */
+#define LPTIM_ISR_DIEROK            LPTIM_ISR_DIEROK_Msk                       /*!< Interrupt enable register update OK */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CC1CF_Pos         (0U)
+#define LPTIM_ICR_CC1CF_Msk         (0x1UL << LPTIM_ICR_CC1CF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CC1CF              LPTIM_ICR_CC1CF_Msk                       /*!< Capture/Compare 1 clear flag  */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMP1OKCF_Pos      (3U)
+#define LPTIM_ICR_CMP1OKCF_Msk      (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)          /*!< 0x00000008 */
+#define LPTIM_ICR_CMP1OKCF          LPTIM_ICR_CMP1OKCF_Msk                     /*!< Compare register 1 update OK clear flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+#define LPTIM_ICR_UECF_Pos          (7U)
+#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
+#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
+#define LPTIM_ICR_REPOKCF_Pos       (8U)
+#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
+#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
+#define LPTIM_ICR_CC2CF_Pos         (9U)
+#define LPTIM_ICR_CC2CF_Msk         (0x1UL << LPTIM_ICR_CC2CF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ICR_CC2CF             LPTIM_ICR_CC2CF_Msk                        /*!< Capture/Compare 2 clear flag  */
+#define LPTIM_ICR_CC1OCF_Pos        (12U)
+#define LPTIM_ICR_CC1OCF_Msk        (0x1UL << LPTIM_ICR_CC1OCF_Pos)            /*!< 0x00001000 */
+#define LPTIM_ICR_CC1OCF            LPTIM_ICR_CC1OCF_Msk                       /*!< Capture/Compare 1 over-capture clear flag */
+#define LPTIM_ICR_CC2OCF_Pos        (13U)
+#define LPTIM_ICR_CC2OCF_Msk        (0x1UL << LPTIM_ICR_CC2OCF_Pos)            /*!< 0x00002000 */
+#define LPTIM_ICR_CC2OCF            LPTIM_ICR_CC2OCF_Msk                       /*!< Capture/Compare 2 over-capture clear flag */
+#define LPTIM_ICR_CMP2OKCF_Pos      (19U)
+#define LPTIM_ICR_CMP2OKCF_Msk      (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)          /*!< 0x00080000 */
+#define LPTIM_ICR_CMP2OKCF          LPTIM_ICR_CMP2OKCF_Msk                     /*!< Compare register 2 update OK clear flag */
+#define LPTIM_ICR_DIEROKCF_Pos      (24U)
+#define LPTIM_ICR_DIEROKCF_Msk      (0x1UL << LPTIM_ICR_DIEROKCF_Pos)          /*!< 0x01000000 */
+#define LPTIM_ICR_DIEROKCF          LPTIM_ICR_DIEROKCF_Msk                     /*!< Interrupt enable register update OK clear flag */
+
+/******************  Bit definition for LPTIM_DIER register *******************/
+#define LPTIM_DIER_CC1IE_Pos        (0U)
+#define LPTIM_DIER_CC1IE_Msk        (0x1UL << LPTIM_DIER_CC1IE_Pos)            /*!< 0x00000001 */
+#define LPTIM_DIER_CC1IE            LPTIM_DIER_CC1IE_Msk                       /*!< Compare/Compare interrupt enable */
+#define LPTIM_DIER_ARRMIE_Pos        (1U)
+#define LPTIM_DIER_ARRMIE_Msk       (0x1UL << LPTIM_DIER_ARRMIE_Pos)           /*!< 0x00000002 */
+#define LPTIM_DIER_ARRMIE           LPTIM_DIER_ARRMIE_Msk                      /*!< Autoreload match Interrupt Enable */
+#define LPTIM_DIER_EXTTRIGIE_Pos    (2U)
+#define LPTIM_DIER_EXTTRIGIE_Msk    (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)        /*!< 0x00000004 */
+#define LPTIM_DIER_EXTTRIGIE        LPTIM_DIER_EXTTRIGIE_Msk                   /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_DIER_CMP1OKIE_Pos     (3U)
+#define LPTIM_DIER_CMP1OKIE_Msk     (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)         /*!< 0x00000008 */
+#define LPTIM_DIER_CMP1OKIE         LPTIM_DIER_CMP1OKIE_Msk                    /*!< Compare register 1 update OK interrupt enable */
+#define LPTIM_DIER_ARROKIE_Pos      (4U)
+#define LPTIM_DIER_ARROKIE_Msk      (0x1UL << LPTIM_DIER_ARROKIE_Pos)          /*!< 0x00000010 */
+#define LPTIM_DIER_ARROKIE          LPTIM_DIER_ARROKIE_Msk                     /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_DIER_UPIE_Pos         (5U)
+#define LPTIM_DIER_UPIE_Msk         (0x1UL << LPTIM_DIER_UPIE_Pos)             /*!< 0x00000020 */
+#define LPTIM_DIER_UPIE             LPTIM_DIER_UPIE_Msk                        /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_DIER_DOWNIE_Pos       (6U)
+#define LPTIM_DIER_DOWNIE_Msk       (0x1UL << LPTIM_DIER_DOWNIE_Pos)           /*!< 0x00000040 */
+#define LPTIM_DIER_DOWNIE           LPTIM_DIER_DOWNIE_Msk                      /*!< Counter direction change up to down Interrupt Enable */
+#define LPTIM_DIER_UEIE_Pos         (7U)
+#define LPTIM_DIER_UEIE_Msk         (0x1UL << LPTIM_DIER_UEIE_Pos)             /*!< 0x00000080 */
+#define LPTIM_DIER_UEIE             LPTIM_DIER_UEIE_Msk                        /*!< Update event Interrupt Enable */
+#define LPTIM_DIER_REPOKIE_Pos      (8U)
+#define LPTIM_DIER_REPOKIE_Msk      (0x1UL << LPTIM_DIER_REPOKIE_Pos)          /*!< 0x00000100 */
+#define LPTIM_DIER_REPOKIE          LPTIM_DIER_REPOKIE_Msk                     /*!< Repetition register update OK Interrupt Enable */
+#define LPTIM_DIER_CC2IE_Pos        (9U)
+#define LPTIM_DIER_CC2IE_Msk        (0x1UL << LPTIM_DIER_CC2IE_Pos)            /*!< 0x00000200 */
+#define LPTIM_DIER_CC2IE            LPTIM_DIER_CC2IE_Msk                       /*!< Capture/Compare 2 interrupt interrupt enable */
+#define LPTIM_DIER_CC1OIE_Pos       (12U)
+#define LPTIM_DIER_CC1OIE_Msk       (0x1UL << LPTIM_DIER_CC1OIE_Pos)           /*!< 0x00001000 */
+#define LPTIM_DIER_CC1OIE           LPTIM_DIER_CC1OIE_Msk                      /*!< Capture/Compare 1 over-capture interrupt enable */
+#define LPTIM_DIER_CC2OIE_Pos       (13U)
+#define LPTIM_DIER_CC2OIE_Msk       (0x1UL << LPTIM_DIER_CC2OIE_Pos)           /*!< 0x00002000 */
+#define LPTIM_DIER_CC2OIE           LPTIM_DIER_CC2OIE_Msk                      /*!< Capture/Compare 2 over-capture interrupt enable */
+#define LPTIM_DIER_CC1DE_Pos        (16U)
+#define LPTIM_DIER_CC1DE_Msk        (0x1UL << LPTIM_DIER_CC1DE_Pos)            /*!< 0x00010000 */
+#define LPTIM_DIER_CC1DE            LPTIM_DIER_CC1DE_Msk                       /*!< Capture/Compare 1 DMA request enable */
+#define LPTIM_DIER_CMP2OKIE_Pos     (19U)
+#define LPTIM_DIER_CMP2OKIE_Msk     (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)         /*!< 0x00080000 */
+#define LPTIM_DIER_CMP2OKIE         LPTIM_DIER_CMP2OKIE_Msk                    /*!< Compare register 2 update OK interrupt enable */
+#define LPTIM_DIER_UEDE_Pos         (23U)
+#define LPTIM_DIER_UEDE_Msk         (0x1UL << LPTIM_DIER_UEDE_Pos)             /*!< 0x00800000 */
+#define LPTIM_DIER_UEDE             LPTIM_DIER_UEDE_Msk                        /*!< Update event DMA request enable */
+#define LPTIM_DIER_CC2DE_Pos        (25U)
+#define LPTIM_DIER_CC2DE_Msk        (0x1UL << LPTIM_DIER_CC2DE_Pos)            /*!< 0x02000000 */
+#define LPTIM_DIER_CC2DE            LPTIM_DIER_CC2DE_Msk                       /*!< Capture/Compare 2 DMA request enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CCR1_CCR1_Pos           (0U)
+#define LPTIM_CCR1_CCR1_Msk           (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)        /*!< 0x0000FFFF */
+#define LPTIM_CCR1_CCR1               LPTIM_CCR1_CCR1_Msk                      /*!< Compare register 1 */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000020 */
+#define LPTIM_CFGR2_IC1SEL_Pos      (16U)
+#define LPTIM_CFGR2_IC1SEL_Msk      (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IC1SEL          LPTIM_CFGR2_IC1SEL_Msk                     /*!< IC1SEL[17:16] bits */
+#define LPTIM_CFGR2_IC1SEL_0        (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CFGR2_IC1SEL_1        (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00020000 */
+#define LPTIM_CFGR2_IC2SEL_Pos      (20U)
+#define LPTIM_CFGR2_IC2SEL_Msk      (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IC2SEL          LPTIM_CFGR2_IC2SEL_Msk                     /*!< IC2SEL[21:20] bits */
+#define LPTIM_CFGR2_IC2SEL_0        (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00100000 */
+#define LPTIM_CFGR2_IC2SEL_1        (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00200000 */
+
+/******************  Bit definition for LPTIM_RCR register  *******************/
+#define LPTIM_RCR_REP_Pos           (0U)
+#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
+#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!< Repetition Counter Value */
+
+/*****************  Bit definition for LPTIM_CCMR1 register  ******************/
+#define LPTIM_CCMR1_CC1SEL_Pos      (0U)
+#define LPTIM_CCMR1_CC1SEL_Msk      (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CCMR1_CC1SEL          LPTIM_CCMR1_CC1SEL_Msk                     /*!< Capture/Compare 1 selection */
+#define LPTIM_CCMR1_CC1E_Pos        (1U)
+#define LPTIM_CCMR1_CC1E_Msk        (0x1UL << LPTIM_CCMR1_CC1E_Pos)            /*!< 0x00000002 */
+#define LPTIM_CCMR1_CC1E            LPTIM_CCMR1_CC1E_Msk                       /*!< Capture/Compare 1 output enable */
+#define LPTIM_CCMR1_CC1P_Pos        (2U)
+#define LPTIM_CCMR1_CC1P_Msk        (0x3UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x0000000C */
+#define LPTIM_CCMR1_CC1P            LPTIM_CCMR1_CC1P_Msk                       /*!< Capture/Compare 1 output polarity */
+#define LPTIM_CCMR1_CC1P_0          (0x1UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000004 */
+#define LPTIM_CCMR1_CC1P_1          (0x2UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000008 */
+#define LPTIM_CCMR1_IC1PSC_Pos      (8U)
+#define LPTIM_CCMR1_IC1PSC_Msk      (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000300 */
+#define LPTIM_CCMR1_IC1PSC          LPTIM_CCMR1_IC1PSC_Msk                     /*!< Input capture 1 prescaler */
+#define LPTIM_CCMR1_IC1PSC_0        (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000100 */
+#define LPTIM_CCMR1_IC1PSC_1        (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000200 */
+#define LPTIM_CCMR1_IC1F_Pos        (12U)
+#define LPTIM_CCMR1_IC1F_Msk        (0x3UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00003000 */
+#define LPTIM_CCMR1_IC1F            LPTIM_CCMR1_IC1F_Msk                       /*!< Input capture 1 filter */
+#define LPTIM_CCMR1_IC1F_0          (0x1UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00001000 */
+#define LPTIM_CCMR1_IC1F_1          (0x2UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00002000 */
+#define LPTIM_CCMR1_CC2SEL_Pos      (16U)
+#define LPTIM_CCMR1_CC2SEL_Msk      (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CCMR1_CC2SEL          LPTIM_CCMR1_CC2SEL_Msk                     /*!< Capture/Compare 2 selection */
+#define LPTIM_CCMR1_CC2E_Pos        (17U)
+#define LPTIM_CCMR1_CC2E_Msk        (0x1UL << LPTIM_CCMR1_CC2E_Pos)            /*!< 0x00020000 */
+#define LPTIM_CCMR1_CC2E            LPTIM_CCMR1_CC2E_Msk                       /*!< Capture/Compare 2 output enable */
+#define LPTIM_CCMR1_CC2P_Pos        (18U)
+#define LPTIM_CCMR1_CC2P_Msk        (0x3UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x000C0000 */
+#define LPTIM_CCMR1_CC2P            LPTIM_CCMR1_CC2P_Msk                       /*!< Capture/Compare 2 output polarity */
+#define LPTIM_CCMR1_CC2P_0          (0x1UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00040000 */
+#define LPTIM_CCMR1_CC2P_1          (0x2UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00080000 */
+#define LPTIM_CCMR1_IC2PSC_Pos      (24U)
+#define LPTIM_CCMR1_IC2PSC_Msk      (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x03000000 */
+#define LPTIM_CCMR1_IC2PSC          LPTIM_CCMR1_IC2PSC_Msk                     /*!< Input capture 2 prescaler */
+#define LPTIM_CCMR1_IC2PSC_0        (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x01000000 */
+#define LPTIM_CCMR1_IC2PSC_1        (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x02000000 */
+#define LPTIM_CCMR1_IC2F_Pos        (28U)
+#define LPTIM_CCMR1_IC2F_Msk        (0x3UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x30000000 */
+#define LPTIM_CCMR1_IC2F            LPTIM_CCMR1_IC2F_Msk                       /*!< Input capture 2 filter */
+#define LPTIM_CCMR1_IC2F_0          (0x1UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x10000000 */
+#define LPTIM_CCMR1_IC2F_1          (0x2UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x20000000 */
+
+/******************  Bit definition for LPTIM_CCR2 register  ******************/
+#define LPTIM_CCR2_CCR2_Pos         (0U)
+#define LPTIM_CCR2_CCR2_Msk         (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)           /*!< 0x0000FFFF */
+#define LPTIM_CCR2_CCR2             LPTIM_CCR2_CCR2_Msk                         /*!< Compare register 2 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/* Bit fields for LTDC_SSCR register */
+#define LTDC_SSCR_VSH_Pos                (0U)
+#define LTDC_SSCR_VSH_Msk                (0xfffUL << LTDC_SSCR_VSH_Pos)
+#define LTDC_SSCR_VSH                    LTDC_SSCR_VSH_Msk  /*!< vertical synchronization height (in units of horizontal scan line)These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. */
+#define LTDC_SSCR_HSW_Pos                (16U)
+#define LTDC_SSCR_HSW_Msk                (0xfffUL << LTDC_SSCR_HSW_Pos)
+#define LTDC_SSCR_HSW                    LTDC_SSCR_HSW_Msk  /*!< horizontal synchronization width (in units of pixel clock period)These bits define the number of Horizontal Synchronization pixel minus 1. */
+
+/* Bit fields for LTDC_BPCR register */
+#define LTDC_BPCR_AVBP_Pos               (0U)
+#define LTDC_BPCR_AVBP_Msk               (0xfffUL << LTDC_BPCR_AVBP_Pos)
+#define LTDC_BPCR_AVBP                   LTDC_BPCR_AVBP_Msk  /*!< accumulated Vertical back porch (in units of horizontal scan line)These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1.The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. */
+#define LTDC_BPCR_AHBP_Pos               (16U)
+#define LTDC_BPCR_AHBP_Msk               (0xfffUL << LTDC_BPCR_AHBP_Pos)
+#define LTDC_BPCR_AHBP                   LTDC_BPCR_AHBP_Msk  /*!< accumulated horizontal back porch (in units of pixel clock period)These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1.The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. */
+
+/* Bit fields for LTDC_AWCR register */
+#define LTDC_AWCR_AAH_Pos                (0U)
+#define LTDC_AWCR_AAH_Msk                (0xfffUL << LTDC_AWCR_AAH_Pos)
+#define LTDC_AWCR_AAH                    LTDC_AWCR_AAH_Msk  /*!< accumulated active height (in units of horizontal scan line)These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel.Refer to device datasheet for maximum active height supported following maximum pixel clock. */
+#define LTDC_AWCR_AAW_Pos                (16U)
+#define LTDC_AWCR_AAW_Msk                (0xfffUL << LTDC_AWCR_AAW_Pos)
+#define LTDC_AWCR_AAW                    LTDC_AWCR_AAW_Msk  /*!< accumulated active width (in units of pixel clock period)These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1.The active width is the number of pixels in active display area of the panel scan line.Refer to device datasheet for maximum active width supported following maximum pixel clock. */
+
+/* Bit fields for LTDC_TWCR register */
+#define LTDC_TWCR_TOTALH_Pos             (0U)
+#define LTDC_TWCR_TOTALH_Msk             (0xfffUL << LTDC_TWCR_TOTALH_Pos)
+#define LTDC_TWCR_TOTALH                 LTDC_TWCR_TOTALH_Msk  /*!< total height (in units of horizontal scan line)These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. */
+#define LTDC_TWCR_TOTALW_Pos             (16U)
+#define LTDC_TWCR_TOTALW_Msk             (0xfffUL << LTDC_TWCR_TOTALW_Pos)
+#define LTDC_TWCR_TOTALW                 LTDC_TWCR_TOTALW_Msk  /*!< total width (in units of pixel clock period)These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. */
+
+/* Bit fields for LTDC_GCR register */
+#define LTDC_GCR_LTDCEN_Pos              (0U)
+#define LTDC_GCR_LTDCEN_Msk              (0x1UL << LTDC_GCR_LTDCEN_Pos)
+#define LTDC_GCR_LTDCEN                  LTDC_GCR_LTDCEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: LTDC disable- 1: LTDC enable */
+#define LTDC_GCR_GAMEN_Pos               (1U)
+#define LTDC_GCR_GAMEN_Msk               (0x1UL << LTDC_GCR_GAMEN_Pos)
+#define LTDC_GCR_GAMEN                   LTDC_GCR_GAMEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: GammaCorrection disable (pixels bypass the gamma operator)- 1: Gamma Correction enable */
+#define LTDC_GCR_ROTEN_Pos               (2U)
+#define LTDC_GCR_ROTEN_Msk               (0x1UL << LTDC_GCR_ROTEN_Pos)
+#define LTDC_GCR_ROTEN                   LTDC_GCR_ROTEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: Rotation disable- 1: Rotation enable (for a pure visual rotation, the mirroring has to be activated) */
+#define LTDC_GCR_DBW_Pos                 (4U)
+#define LTDC_GCR_DBW_Msk                 (0x7UL << LTDC_GCR_DBW_Pos)
+#define LTDC_GCR_DBW                     LTDC_GCR_DBW_Msk  /*!< dither blue widthThese bits return the dither blue bits. */
+#define LTDC_GCR_DGW_Pos                 (8U)
+#define LTDC_GCR_DGW_Msk                 (0x7UL << LTDC_GCR_DGW_Pos)
+#define LTDC_GCR_DGW                     LTDC_GCR_DGW_Msk  /*!< dither green widthThese bits return the dither green bits. */
+#define LTDC_GCR_DRW_Pos                 (12U)
+#define LTDC_GCR_DRW_Msk                 (0x7UL << LTDC_GCR_DRW_Pos)
+#define LTDC_GCR_DRW                     LTDC_GCR_DRW_Msk  /*!< dither red widthThese bits return the Dither Red Bits. */
+#define LTDC_GCR_DEN_Pos                 (16U)
+#define LTDC_GCR_DEN_Msk                 (0x1UL << LTDC_GCR_DEN_Pos)
+#define LTDC_GCR_DEN                     LTDC_GCR_DEN_Msk  /*!< dither enableThis bit is set and cleared by software.- 0: dither disable- 1: dither enable */
+#define LTDC_GCR_BCKEN_Pos               (17U)
+#define LTDC_GCR_BCKEN_Msk               (0x1UL << LTDC_GCR_BCKEN_Pos)
+#define LTDC_GCR_BCKEN                   LTDC_GCR_BCKEN_Msk  /*!< backgroundlayer enableThis bit is set and cleared by software.- 0: backgrounddisable- 1: background enable */
+#define LTDC_GCR_CRCEN_Pos               (19U)
+#define LTDC_GCR_CRCEN_Msk               (0x1UL << LTDC_GCR_CRCEN_Pos)
+#define LTDC_GCR_CRCEN                   LTDC_GCR_CRCEN_Msk  /*!< CRC enableThis bit is set and cleared by software.- 0: CRC disable- 1: CRC enable */
+#define LTDC_GCR_SFEN_Pos                (24U)
+#define LTDC_GCR_SFEN_Msk                (0x1UL << LTDC_GCR_SFEN_Pos)
+#define LTDC_GCR_SFEN                    LTDC_GCR_SFEN_Msk  /*!< single-frame mode: mode enableThis bit is set and cleared by software.- 0: single-frame disable:a trigger (on SFSW or External) will generate a continuous flow.- 1: single-frame enable: a trigger (on SFSW or External) will generate a single frame. */
+#define LTDC_GCR_SFSWTR_Pos              (25U)
+#define LTDC_GCR_SFSWTR_Msk              (0x1UL << LTDC_GCR_SFSWTR_Pos)
+#define LTDC_GCR_SFSWTR                  LTDC_GCR_SFSWTR_Msk  /*!< single-frame mode: software triggerThis bit is set by software and cleared by hardware.- 0: no action- 1: triggers one frame */
+#define LTDC_GCR_SFEXEN_Pos              (26U)
+#define LTDC_GCR_SFEXEN_Msk              (0x1UL << LTDC_GCR_SFEXEN_Pos)
+#define LTDC_GCR_SFEXEN                  LTDC_GCR_SFEXEN_Msk  /*!< single-frame mode: external trigger enableThis bit is set and cleared by software.- 0: external trigger disable- 1: external trigger enable: a trigger on the external trigger will generate one single frame. */
+#define LTDC_GCR_PCPOL_Pos               (28U)
+#define LTDC_GCR_PCPOL_Msk               (0x1UL << LTDC_GCR_PCPOL_Pos)
+#define LTDC_GCR_PCPOL                   LTDC_GCR_PCPOL_Msk  /*!< pixel clock polarityThis bit is set and cleared by software.- 0: pixel clock polarity is active low.- 1: pixel clock is active high. */
+#define LTDC_GCR_DEPOL_Pos               (29U)
+#define LTDC_GCR_DEPOL_Msk               (0x1UL << LTDC_GCR_DEPOL_Pos)
+#define LTDC_GCR_DEPOL                   LTDC_GCR_DEPOL_Msk  /*!< blanking (=no data/pixel) polarityThis bit is set and cleared by software.- 0: blanking (no data/pixel) polarity is active low.- 1: blanking (no data/pixel) polarity is active high. */
+#define LTDC_GCR_VSPOL_Pos               (30U)
+#define LTDC_GCR_VSPOL_Msk               (0x1UL << LTDC_GCR_VSPOL_Pos)
+#define LTDC_GCR_VSPOL                   LTDC_GCR_VSPOL_Msk  /*!< vertical synchronization polarityThis bit is set and cleared by software.- 0: vertical synchronization is active low.- 1: vertical synchronization is active high. */
+#define LTDC_GCR_HSPOL_Pos               (31U)
+#define LTDC_GCR_HSPOL_Msk               (0x1UL << LTDC_GCR_HSPOL_Pos)
+#define LTDC_GCR_HSPOL                   LTDC_GCR_HSPOL_Msk  /*!< horizontal synchronization polarityThis bit is set and cleared by software.- 0: horizontal synchronization polarity is active low.- 1: horizontal synchronization polarity is active high. */
+
+/* Bit fields for LTDC_SRCR register */
+#define LTDC_SRCR_IMR_Pos                (0U)
+#define LTDC_SRCR_IMR_Msk                (0x1UL << LTDC_SRCR_IMR_Pos)
+#define LTDC_SRCR_IMR                    LTDC_SRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_SRCR_VBR_Pos                (1U)
+#define LTDC_SRCR_VBR_Msk                (0x1UL << LTDC_SRCR_VBR_Pos)
+#define LTDC_SRCR_VBR                    LTDC_SRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+
+/* Bit fields for LTDC_GCCR register */
+#define LTDC_GCCR_ADDR_Pos               (0U)
+#define LTDC_GCCR_ADDR_Msk               (0xffUL << LTDC_GCCR_ADDR_Pos)
+#define LTDC_GCCR_ADDR                   LTDC_GCCR_ADDR_Msk  /*!< address of the R,G,B table where the COMP component is written.When LTDC_GC1R.GCT=2, the gamma is implemented with 8 interpolated segment. In that case, the valid ADDR addresses are: 0, 32, 64, 96, 128, 160, 192, 224, 255.Note that for ADDR=255, the gamma interpolation hardware considers that the address is 256. */
+#define LTDC_GCCR_COMP_Pos               (8U)
+#define LTDC_GCCR_COMP_Msk               (0xffUL << LTDC_GCCR_COMP_Pos)
+#define LTDC_GCCR_COMP                   LTDC_GCCR_COMP_Msk  /*!< color component to be written, in either (or all) the R,G,B tables.. */
+#define LTDC_GCCR_BEN_Pos                (16U)
+#define LTDC_GCCR_BEN_Msk                (0x1UL << LTDC_GCCR_BEN_Pos)
+#define LTDC_GCCR_BEN                    LTDC_GCCR_BEN_Msk  /*!< write trigger to the blue table- 0: no action done- 1: COMP is written at ADDR in the Blue table. */
+#define LTDC_GCCR_GEN_Pos                (17U)
+#define LTDC_GCCR_GEN_Msk                (0x1UL << LTDC_GCCR_GEN_Pos)
+#define LTDC_GCCR_GEN                    LTDC_GCCR_GEN_Msk  /*!< write trigger to the green table- 0: no action done- 1: COMP is written at ADDR in the Green table. */
+#define LTDC_GCCR_REN_Pos                (18U)
+#define LTDC_GCCR_REN_Msk                (0x1UL << LTDC_GCCR_REN_Pos)
+#define LTDC_GCCR_REN                    LTDC_GCCR_REN_Msk  /*!< write trigger to the red table- 0: no action done- 1: COMP is written at ADDR in the Red table. */
+
+/* Bit fields for LTDC_BCCR register */
+#define LTDC_BCCR_BCBLUE_Pos             (0U)
+#define LTDC_BCCR_BCBLUE_Msk             (0xffUL << LTDC_BCCR_BCBLUE_Pos)
+#define LTDC_BCCR_BCBLUE                 LTDC_BCCR_BCBLUE_Msk  /*!< background color blue valueThese bits configure the background blue value. */
+#define LTDC_BCCR_BCGREEN_Pos            (8U)
+#define LTDC_BCCR_BCGREEN_Msk            (0xffUL << LTDC_BCCR_BCGREEN_Pos)
+#define LTDC_BCCR_BCGREEN                LTDC_BCCR_BCGREEN_Msk  /*!< background color green valueThese bits configure the background green value. */
+#define LTDC_BCCR_BCRED_Pos              (16U)
+#define LTDC_BCCR_BCRED_Msk              (0xffUL << LTDC_BCCR_BCRED_Pos)
+#define LTDC_BCCR_BCRED                  LTDC_BCCR_BCRED_Msk  /*!< background color red valueThese bits configure the background red value. */
+
+/* Bit fields for LTDC_IER register */
+#define LTDC_IER_LIE_Pos                 (0U)
+#define LTDC_IER_LIE_Msk                 (0x1UL << LTDC_IER_LIE_Pos)
+#define LTDC_IER_LIE                     LTDC_IER_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER_FUWIE_Pos               (1U)
+#define LTDC_IER_FUWIE_Msk               (0x1UL << LTDC_IER_FUWIE_Pos)
+#define LTDC_IER_FUWIE                   LTDC_IER_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER_TERRIE_Pos              (2U)
+#define LTDC_IER_TERRIE_Msk              (0x1UL << LTDC_IER_TERRIE_Pos)
+#define LTDC_IER_TERRIE                  LTDC_IER_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER_RRIE_Pos                (3U)
+#define LTDC_IER_RRIE_Msk                (0x1UL << LTDC_IER_RRIE_Pos)
+#define LTDC_IER_RRIE                    LTDC_IER_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER_FUIE_Pos                (6U)
+#define LTDC_IER_FUIE_Msk                (0x1UL << LTDC_IER_FUIE_Pos)
+#define LTDC_IER_FUIE                    LTDC_IER_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER_CRCIE_Pos               (7U)
+#define LTDC_IER_CRCIE_Msk               (0x1UL << LTDC_IER_CRCIE_Pos)
+#define LTDC_IER_CRCIE                   LTDC_IER_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+#define LTDC_IER_FURIE_Pos               (8U)
+#define LTDC_IER_FURIE_Msk               (0x1UL << LTDC_IER_FURIE_Pos)
+#define LTDC_IER_FURIE                   LTDC_IER_FURIE_Msk  /*!< FIFOunderrun at rotation interrupt enableThis bit is set and cleared by software.- 0: FIFOunderrun at rotation interrupt disable- 1: FIFO underrunat rotation interrupt enable */
+
+/* Bit fields for LTDC_ISR register */
+#define LTDC_ISR_LIF_Pos                 (0U)
+#define LTDC_ISR_LIF_Msk                 (0x1UL << LTDC_ISR_LIF_Pos)
+#define LTDC_ISR_LIF                     LTDC_ISR_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR_FUWIF_Pos               (1U)
+#define LTDC_ISR_FUWIF_Msk               (0x1UL << LTDC_ISR_FUWIF_Pos)
+#define LTDC_ISR_FUWIF                   LTDC_ISR_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR_TERRIF_Pos              (2U)
+#define LTDC_ISR_TERRIF_Msk              (0x1UL << LTDC_ISR_TERRIF_Pos)
+#define LTDC_ISR_TERRIF                  LTDC_ISR_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR_RRIF_Pos                (3U)
+#define LTDC_ISR_RRIF_Msk                (0x1UL << LTDC_ISR_RRIF_Pos)
+#define LTDC_ISR_RRIF                    LTDC_ISR_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR_FUIF_Pos                (6U)
+#define LTDC_ISR_FUIF_Msk                (0x1UL << LTDC_ISR_FUIF_Pos)
+#define LTDC_ISR_FUIF                    LTDC_ISR_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data is read from the FIFO */
+#define LTDC_ISR_CRCIF_Pos               (7U)
+#define LTDC_ISR_CRCIF_Msk               (0x1UL << LTDC_ISR_CRCIF_Pos)
+#define LTDC_ISR_CRCIF                   LTDC_ISR_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when the computed CRC is different from the expected CRC. */
+#define LTDC_ISR_FURIF_Pos               (8U)
+#define LTDC_ISR_FURIF_Msk               (0x1UL << LTDC_ISR_FURIF_Pos)
+#define LTDC_ISR_FURIF                   LTDC_ISR_FURIF_Msk  /*!< FIFO underrun at rotation interrupt flag- 0: no FIFO underrun at rotation interrupt generated- 1: FIFO underrun at rotation interrupt generated */
+
+/* Bit fields for LTDC_ICR register */
+#define LTDC_ICR_CLIF_Pos                (0U)
+#define LTDC_ICR_CLIF_Msk                (0x1UL << LTDC_ICR_CLIF_Pos)
+#define LTDC_ICR_CLIF                    LTDC_ICR_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFUWIF_Pos              (1U)
+#define LTDC_ICR_CFUWIF_Msk              (0x1UL << LTDC_ICR_CFUWIF_Pos)
+#define LTDC_ICR_CFUWIF                  LTDC_ICR_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CTERRIF_Pos             (2U)
+#define LTDC_ICR_CTERRIF_Msk             (0x1UL << LTDC_ICR_CTERRIF_Pos)
+#define LTDC_ICR_CTERRIF                 LTDC_ICR_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CRRIF_Pos               (3U)
+#define LTDC_ICR_CRRIF_Msk               (0x1UL << LTDC_ICR_CRRIF_Pos)
+#define LTDC_ICR_CRRIF                   LTDC_ICR_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR_CFUIF_Pos               (6U)
+#define LTDC_ICR_CFUIF_Msk               (0x1UL << LTDC_ICR_CFUIF_Pos)
+#define LTDC_ICR_CFUIF                   LTDC_ICR_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CCRCIF_Pos              (7U)
+#define LTDC_ICR_CCRCIF_Msk              (0x1UL << LTDC_ICR_CCRCIF_Pos)
+#define LTDC_ICR_CCRCIF                  LTDC_ICR_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFURIF_Pos              (8U)
+#define LTDC_ICR_CFURIF_Msk              (0x1UL << LTDC_ICR_CFURIF_Pos)
+#define LTDC_ICR_CFURIF                  LTDC_ICR_CFURIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the FURIF flag in the LTDC_ISR register */
+
+/* Bit fields for LTDC_LIPCR register */
+#define LTDC_LIPCR_LIPOS_Pos             (0U)
+#define LTDC_LIPCR_LIPOS_Msk             (0xfffUL << LTDC_LIPCR_LIPOS_Pos)
+#define LTDC_LIPCR_LIPOS                 LTDC_LIPCR_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR register */
+#define LTDC_CPSR_CYPOS_Pos              (0U)
+#define LTDC_CPSR_CYPOS_Msk              (0xfffUL << LTDC_CPSR_CYPOS_Pos)
+#define LTDC_CPSR_CYPOS                  LTDC_CPSR_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR_CXPOS_Pos              (16U)
+#define LTDC_CPSR_CXPOS_Msk              (0xfffUL << LTDC_CPSR_CXPOS_Pos)
+#define LTDC_CPSR_CXPOS                  LTDC_CPSR_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_CDSR register */
+#define LTDC_CDSR_VDES_Pos               (0U)
+#define LTDC_CDSR_VDES_Msk               (0x1UL << LTDC_CDSR_VDES_Pos)
+#define LTDC_CDSR_VDES                   LTDC_CDSR_VDES_Msk  /*!< vertical data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HDES_Pos               (1U)
+#define LTDC_CDSR_HDES_Msk               (0x1UL << LTDC_CDSR_HDES_Pos)
+#define LTDC_CDSR_HDES                   LTDC_CDSR_HDES_Msk  /*!< horizontal data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_VSYNCS_Pos             (2U)
+#define LTDC_CDSR_VSYNCS_Msk             (0x1UL << LTDC_CDSR_VSYNCS_Pos)
+#define LTDC_CDSR_VSYNCS                 LTDC_CDSR_VSYNCS_Msk  /*!< vertical synchronization display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HSYNCS_Pos             (3U)
+#define LTDC_CDSR_HSYNCS_Msk             (0x1UL << LTDC_CDSR_HSYNCS_Pos)
+#define LTDC_CDSR_HSYNCS                 LTDC_CDSR_HSYNCS_Msk  /*!< horizontal synchronization display status- 0: active low- 1: active high */
+
+/* Bit fields for LTDC_EDCR register */
+#define LTDC_EDCR_OCYEN_Pos              (25U)
+#define LTDC_EDCR_OCYEN_Msk              (0x1UL << LTDC_EDCR_OCYEN_Pos)
+#define LTDC_EDCR_OCYEN                  LTDC_EDCR_OCYEN_Msk  /*!< output conversion to YCbCr 422: Enable- 0: conversion is disabled- 1: conversion is enabled */
+#define LTDC_EDCR_OCYSEL_Pos             (26U)
+#define LTDC_EDCR_OCYSEL_Msk             (0x1UL << LTDC_EDCR_OCYSEL_Pos)
+#define LTDC_EDCR_OCYSEL                 LTDC_EDCR_OCYSEL_Msk  /*!< output conversion to YCbCr 422: selection of the CCIR hard-wired coefficients:- 0: use CCIR-BT601 set (for typically SDTV analog-like displays)- 1: use CCIR-BT709 set (for typically HDTV digital-like displays) */
+#define LTDC_EDCR_OCYCO_Pos              (27U)
+#define LTDC_EDCR_OCYCO_Msk              (0x1UL << LTDC_EDCR_OCYCO_Pos)
+#define LTDC_EDCR_OCYCO                  LTDC_EDCR_OCYCO_Msk  /*!< output conversion to YCbCr 422: chrominance order.- 0: Cb is output first (so: Y0Cb, then Y1Cr, Y2Cb, etc .. ).- 1: Cr is output first (so: Y0Cr, then Y1Cb, Y2Cr, etc ..). */
+
+/* Bit fields for LTDC_IER2 register */
+#define LTDC_IER2_LIE_Pos                (0U)
+#define LTDC_IER2_LIE_Msk                (0x1UL << LTDC_IER2_LIE_Pos)
+#define LTDC_IER2_LIE                    LTDC_IER2_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER2_FUWIE_Pos              (1U)
+#define LTDC_IER2_FUWIE_Msk              (0x1UL << LTDC_IER2_FUWIE_Pos)
+#define LTDC_IER2_FUWIE                  LTDC_IER2_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER2_TERRIE_Pos             (2U)
+#define LTDC_IER2_TERRIE_Msk             (0x1UL << LTDC_IER2_TERRIE_Pos)
+#define LTDC_IER2_TERRIE                 LTDC_IER2_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER2_RRIE_Pos               (3U)
+#define LTDC_IER2_RRIE_Msk               (0x1UL << LTDC_IER2_RRIE_Pos)
+#define LTDC_IER2_RRIE                   LTDC_IER2_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER2_FUIE_Pos               (6U)
+#define LTDC_IER2_FUIE_Msk               (0x1UL << LTDC_IER2_FUIE_Pos)
+#define LTDC_IER2_FUIE                   LTDC_IER2_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER2_CRCIE_Pos              (7U)
+#define LTDC_IER2_CRCIE_Msk              (0x1UL << LTDC_IER2_CRCIE_Pos)
+#define LTDC_IER2_CRCIE                  LTDC_IER2_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+
+/* Bit fields for LTDC_ISR2 register */
+#define LTDC_ISR2_LIF_Pos                (0U)
+#define LTDC_ISR2_LIF_Msk                (0x1UL << LTDC_ISR2_LIF_Pos)
+#define LTDC_ISR2_LIF                    LTDC_ISR2_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR2_FUWIF_Pos              (1U)
+#define LTDC_ISR2_FUWIF_Msk              (0x1UL << LTDC_ISR2_FUWIF_Pos)
+#define LTDC_ISR2_FUWIF                  LTDC_ISR2_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR2_TERRIF_Pos             (2U)
+#define LTDC_ISR2_TERRIF_Msk             (0x1UL << LTDC_ISR2_TERRIF_Pos)
+#define LTDC_ISR2_TERRIF                 LTDC_ISR2_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR2_RRIF_Pos               (3U)
+#define LTDC_ISR2_RRIF_Msk               (0x1UL << LTDC_ISR2_RRIF_Pos)
+#define LTDC_ISR2_RRIF                   LTDC_ISR2_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR2_FUIF_Pos               (6U)
+#define LTDC_ISR2_FUIF_Msk               (0x1UL << LTDC_ISR2_FUIF_Pos)
+#define LTDC_ISR2_FUIF                   LTDC_ISR2_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO */
+#define LTDC_ISR2_CRCIF_Pos              (7U)
+#define LTDC_ISR2_CRCIF_Msk              (0x1UL << LTDC_ISR2_CRCIF_Pos)
+#define LTDC_ISR2_CRCIF                  LTDC_ISR2_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when a bus error occurs */
+
+/* Bit fields for LTDC_ICR2 register */
+#define LTDC_ICR2_CLIF_Pos               (0U)
+#define LTDC_ICR2_CLIF_Msk               (0x1UL << LTDC_ICR2_CLIF_Pos)
+#define LTDC_ICR2_CLIF                   LTDC_ICR2_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CFUWIF_Pos             (1U)
+#define LTDC_ICR2_CFUWIF_Msk             (0x1UL << LTDC_ICR2_CFUWIF_Pos)
+#define LTDC_ICR2_CFUWIF                 LTDC_ICR2_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CTERRIF_Pos            (2U)
+#define LTDC_ICR2_CTERRIF_Msk            (0x1UL << LTDC_ICR2_CTERRIF_Pos)
+#define LTDC_ICR2_CTERRIF                LTDC_ICR2_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CRRIF_Pos              (3U)
+#define LTDC_ICR2_CRRIF_Msk              (0x1UL << LTDC_ICR2_CRRIF_Pos)
+#define LTDC_ICR2_CRRIF                  LTDC_ICR2_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR2_CFUIF_Pos              (6U)
+#define LTDC_ICR2_CFUIF_Msk              (0x1UL << LTDC_ICR2_CFUIF_Pos)
+#define LTDC_ICR2_CFUIF                  LTDC_ICR2_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CCRCIF_Pos             (7U)
+#define LTDC_ICR2_CCRCIF_Msk             (0x1UL << LTDC_ICR2_CCRCIF_Pos)
+#define LTDC_ICR2_CCRCIF                 LTDC_ICR2_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+
+/* Bit fields for LTDC_LIPCR2 register */
+#define LTDC_LIPCR2_LIPOS_Pos             (0U)
+#define LTDC_LIPCR2_LIPOS_Msk             (0xffffUL << LTDC_LIPCR2_LIPOS_Pos)
+#define LTDC_LIPCR2_LIPOS                 LTDC_LIPCR2_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR2 register */
+#define LTDC_CPSR2_CYPOS_Pos             (0U)
+#define LTDC_CPSR2_CYPOS_Msk             (0xffffUL << LTDC_CPSR2_CYPOS_Pos)
+#define LTDC_CPSR2_CYPOS                 LTDC_CPSR2_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR2_CXPOS_Pos             (16U)
+#define LTDC_CPSR2_CXPOS_Msk             (0xffffUL << LTDC_CPSR2_CXPOS_Pos)
+#define LTDC_CPSR2_CXPOS                 LTDC_CPSR2_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_ECRCR register */
+#define LTDC_ECRCR_ECRC_Pos              (0U)
+#define LTDC_ECRCR_ECRC_Msk              (0xffffUL << LTDC_ECRCR_ECRC_Pos)
+#define LTDC_ECRCR_ECRC                  LTDC_ECRCR_ECRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_CCRCR register */
+#define LTDC_CCRCR_CCRC_Pos              (0U)
+#define LTDC_CCRCR_CCRC_Msk              (0xffffUL << LTDC_CCRCR_CCRC_Pos)
+#define LTDC_CCRCR_CCRC                  LTDC_CCRCR_CCRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_FUTR register */
+#define LTDC_FUTR_THRE_Pos               (0U)
+#define LTDC_FUTR_THRE_Msk               (0xffffUL << LTDC_FUTR_THRE_Pos)
+#define LTDC_FUTR_THRE                   LTDC_FUTR_THRE_Msk  /*!< threshold to trigger a FIFO underrun killing interrupt (unit is per fifo word, 64bit) */
+
+/* Bit fields for LTDC_LxC0R register */
+#define LTDC_LxC0R_CKTA_Pos              (0U)
+#define LTDC_LxC0R_CKTA_Msk              (0x1UL << LTDC_LxC0R_CKTA_Pos)
+#define LTDC_LxC0R_CKTA                  LTDC_LxC0R_CKTA_Msk  /*!< color key transparency Ability */
+#define LTDC_LxC0R_CFBDA_Pos             (1U)
+#define LTDC_LxC0R_CFBDA_Msk             (0x1UL << LTDC_LxC0R_CFBDA_Pos)
+#define LTDC_LxC0R_CFBDA                 LTDC_LxC0R_CFBDA_Msk  /*!< color frame buffer duplication ability */
+#define LTDC_LxC0R_CFBPA_Pos             (2U)
+#define LTDC_LxC0R_CFBPA_Msk             (0x1UL << LTDC_LxC0R_CFBPA_Pos)
+#define LTDC_LxC0R_CFBPA                 LTDC_LxC0R_CFBPA_Msk  /*!< color frame buffer pitch ability */
+#define LTDC_LxC0R_APA_Pos               (3U)
+#define LTDC_LxC0R_APA_Msk               (0x1UL << LTDC_LxC0R_APA_Pos)
+#define LTDC_LxC0R_APA                   LTDC_LxC0R_APA_Msk  /*!< alpha plane ability */
+#define LTDC_LxC0R_DCP_Pos               (4U)
+#define LTDC_LxC0R_DCP_Msk               (0x1UL << LTDC_LxC0R_DCP_Pos)
+#define LTDC_LxC0R_DCP                   LTDC_LxC0R_DCP_Msk  /*!< default color programmability */
+#define LTDC_LxC0R_WINA_Pos              (5U)
+#define LTDC_LxC0R_WINA_Msk              (0x1UL << LTDC_LxC0R_WINA_Pos)
+#define LTDC_LxC0R_WINA                  LTDC_LxC0R_WINA_Msk  /*!< windowing ability */
+#define LTDC_LxC0R_CLUTA_Pos             (6U)
+#define LTDC_LxC0R_CLUTA_Msk             (0x1UL << LTDC_LxC0R_CLUTA_Pos)
+#define LTDC_LxC0R_CLUTA                 LTDC_LxC0R_CLUTA_Msk  /*!< CLUT ability */
+#define LTDC_LxC0R_CKRA_Pos              (7U)
+#define LTDC_LxC0R_CKRA_Msk              (0x1UL << LTDC_LxC0R_CKRA_Pos)
+#define LTDC_LxC0R_CKRA                  LTDC_LxC0R_CKRA_Msk  /*!< color key replace ability */
+#define LTDC_LxC0R_F21_Pos               (8U)
+#define LTDC_LxC0R_F21_Msk               (0x1UL << LTDC_LxC0R_F21_Pos)
+#define LTDC_LxC0R_F21                   LTDC_LxC0R_F21_Msk  /*!< blending factor 2, ability for: 1.0 */
+#define LTDC_LxC0R_F20_Pos               (9U)
+#define LTDC_LxC0R_F20_Msk               (0x1UL << LTDC_LxC0R_F20_Pos)
+#define LTDC_LxC0R_F20                   LTDC_LxC0R_F20_Msk  /*!< blending factor 2, ability for: 0.0 */
+#define LTDC_LxC0R_F2P_Pos               (10U)
+#define LTDC_LxC0R_F2P_Msk               (0x1UL << LTDC_LxC0R_F2P_Pos)
+#define LTDC_LxC0R_F2P                   LTDC_LxC0R_F2P_Msk  /*!< blending factor 2, ability for: pixel_alpha */
+#define LTDC_LxC0R_F21P_Pos              (11U)
+#define LTDC_LxC0R_F21P_Msk              (0x1UL << LTDC_LxC0R_F21P_Pos)
+#define LTDC_LxC0R_F21P                  LTDC_LxC0R_F21P_Msk  /*!< blending factor 2, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F2C_Pos               (12U)
+#define LTDC_LxC0R_F2C_Msk               (0x1UL << LTDC_LxC0R_F2C_Pos)
+#define LTDC_LxC0R_F2C                   LTDC_LxC0R_F2C_Msk  /*!< blending factor 2, ability for: constant_alpha */
+#define LTDC_LxC0R_F21C_Pos              (13U)
+#define LTDC_LxC0R_F21C_Msk              (0x1UL << LTDC_LxC0R_F21C_Pos)
+#define LTDC_LxC0R_F21C                  LTDC_LxC0R_F21C_Msk  /*!< blending factor 2, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F2PC_Pos              (14U)
+#define LTDC_LxC0R_F2PC_Msk              (0x1UL << LTDC_LxC0R_F2PC_Pos)
+#define LTDC_LxC0R_F2PC                  LTDC_LxC0R_F2PC_Msk  /*!< blending factor 2, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F21PC_Pos             (15U)
+#define LTDC_LxC0R_F21PC_Msk             (0x1UL << LTDC_LxC0R_F21PC_Pos)
+#define LTDC_LxC0R_F21PC                 LTDC_LxC0R_F21PC_Msk  /*!< blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_F11_Pos               (16U)
+#define LTDC_LxC0R_F11_Msk               (0x1UL << LTDC_LxC0R_F11_Pos)
+#define LTDC_LxC0R_F11                   LTDC_LxC0R_F11_Msk  /*!< blending factor 1, ability for: 1.0 */
+#define LTDC_LxC0R_F10_Pos               (17U)
+#define LTDC_LxC0R_F10_Msk               (0x1UL << LTDC_LxC0R_F10_Pos)
+#define LTDC_LxC0R_F10                   LTDC_LxC0R_F10_Msk  /*!< blending factor 1,ability for: 0.0 */
+#define LTDC_LxC0R_F1P_Pos               (18U)
+#define LTDC_LxC0R_F1P_Msk               (0x1UL << LTDC_LxC0R_F1P_Pos)
+#define LTDC_LxC0R_F1P                   LTDC_LxC0R_F1P_Msk  /*!< blending factor 1, ability for: pixel_alpha */
+#define LTDC_LxC0R_F11P_Pos              (19U)
+#define LTDC_LxC0R_F11P_Msk              (0x1UL << LTDC_LxC0R_F11P_Pos)
+#define LTDC_LxC0R_F11P                  LTDC_LxC0R_F11P_Msk  /*!< blending factor 1, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F1C_Pos               (20U)
+#define LTDC_LxC0R_F1C_Msk               (0x1UL << LTDC_LxC0R_F1C_Pos)
+#define LTDC_LxC0R_F1C                   LTDC_LxC0R_F1C_Msk  /*!< blending factor 1, ability for: constant_alpha */
+#define LTDC_LxC0R_F11C_Pos              (21U)
+#define LTDC_LxC0R_F11C_Msk              (0x1UL << LTDC_LxC0R_F11C_Pos)
+#define LTDC_LxC0R_F11C                  LTDC_LxC0R_F11C_Msk  /*!< blending factor 1, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F1PC_Pos              (22U)
+#define LTDC_LxC0R_F1PC_Msk              (0x1UL << LTDC_LxC0R_F1PC_Pos)
+#define LTDC_LxC0R_F1PC                  LTDC_LxC0R_F1PC_Msk  /*!< blending factor 1, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F11PC_Pos             (23U)
+#define LTDC_LxC0R_F11PC_Msk             (0x1UL << LTDC_LxC0R_F11PC_Pos)
+#define LTDC_LxC0R_F11PC                 LTDC_LxC0R_F11PC_Msk  /*!< blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_P88_Pos               (24U)
+#define LTDC_LxC0R_P88_Msk               (0x1UL << LTDC_LxC0R_P88_Pos)
+#define LTDC_LxC0R_P88                   LTDC_LxC0R_P88_Msk  /*!< pixel format, ability for: AL88. */
+#define LTDC_LxC0R_P44_Pos               (25U)
+#define LTDC_LxC0R_P44_Msk               (0x1UL << LTDC_LxC0R_P44_Pos)
+#define LTDC_LxC0R_P44                   LTDC_LxC0R_P44_Msk  /*!< pixel format, ability for: AL44. */
+#define LTDC_LxC0R_P8_Pos                (26U)
+#define LTDC_LxC0R_P8_Msk                (0x1UL << LTDC_LxC0R_P8_Pos)
+#define LTDC_LxC0R_P8                    LTDC_LxC0R_P8_Msk  /*!< pixel format, ability for: L8. */
+#define LTDC_LxC0R_P4444_Pos             (27U)
+#define LTDC_LxC0R_P4444_Msk             (0x1UL << LTDC_LxC0R_P4444_Pos)
+#define LTDC_LxC0R_P4444                 LTDC_LxC0R_P4444_Msk  /*!< pixel format, ability for: ARGB4444. */
+#define LTDC_LxC0R_P1555_Pos             (28U)
+#define LTDC_LxC0R_P1555_Msk             (0x1UL << LTDC_LxC0R_P1555_Pos)
+#define LTDC_LxC0R_P1555                 LTDC_LxC0R_P1555_Msk  /*!< pixel format, ability for: ARGB1555. */
+#define LTDC_LxC0R_P565_Pos              (29U)
+#define LTDC_LxC0R_P565_Msk              (0x1UL << LTDC_LxC0R_P565_Pos)
+#define LTDC_LxC0R_P565                  LTDC_LxC0R_P565_Msk  /*!< pixel format, ability for: RGB565. */
+#define LTDC_LxC0R_P888_Pos              (30U)
+#define LTDC_LxC0R_P888_Msk              (0x1UL << LTDC_LxC0R_P888_Pos)
+#define LTDC_LxC0R_P888                  LTDC_LxC0R_P888_Msk  /*!< pixel format, ability for: RGB888. */
+#define LTDC_LxC0R_P8888_Pos             (31U)
+#define LTDC_LxC0R_P8888_Msk             (0x1UL << LTDC_LxC0R_P8888_Pos)
+#define LTDC_LxC0R_P8888                 LTDC_LxC0R_P8888_Msk  /*!< pixel format, ability for: ARGB8888. */
+
+/* Bit fields for LTDC_LxC1R register */
+#define LTDC_LxC1R_YIA_Pos               (0U)
+#define LTDC_LxC1R_YIA_Msk               (0x1UL << LTDC_LxC1R_YIA_Pos)
+#define LTDC_LxC1R_YIA                   LTDC_LxC1R_YIA_Msk  /*!< YCbCr 422 interleaved ability for that layer.- 0: interleaved not available- 1: interleaved available */
+#define LTDC_LxC1R_YSPA_Pos              (1U)
+#define LTDC_LxC1R_YSPA_Msk              (0x1UL << LTDC_LxC1R_YSPA_Pos)
+#define LTDC_LxC1R_YSPA                  LTDC_LxC1R_YSPA_Msk  /*!< YCbCr 420 semi-planar ability for that layer.- 0: semiplanar not available- 1: semi-planar available */
+#define LTDC_LxC1R_YFPA_Pos              (2U)
+#define LTDC_LxC1R_YFPA_Msk              (0x1UL << LTDC_LxC1R_YFPA_Pos)
+#define LTDC_LxC1R_YFPA                  LTDC_LxC1R_YFPA_Msk  /*!< YCbCr 420 full-planar ability for that layer.- 0: full planar not available- 1: full planar available */
+#define LTDC_LxC1R_SCA_Pos               (31U)
+#define LTDC_LxC1R_SCA_Msk               (0x1UL << LTDC_LxC1R_SCA_Pos)
+#define LTDC_LxC1R_SCA                   LTDC_LxC1R_SCA_Msk  /*!< scaling ability for that layer.- 0: scaling not available- 1: scaling available */
+
+/* Bit fields for LTDC_LxRCR register */
+#define LTDC_LxRCR_IMR_Pos               (0U)
+#define LTDC_LxRCR_IMR_Msk               (0x1UL << LTDC_LxRCR_IMR_Pos)
+#define LTDC_LxRCR_IMR                   LTDC_LxRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_LxRCR_VBR_Pos               (1U)
+#define LTDC_LxRCR_VBR_Msk               (0x1UL << LTDC_LxRCR_VBR_Pos)
+#define LTDC_LxRCR_VBR                   LTDC_LxRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+#define LTDC_LxRCR_GRMSK_Pos             (2U)
+#define LTDC_LxRCR_GRMSK_Msk             (0x1UL << LTDC_LxRCR_GRMSK_Pos)
+#define LTDC_LxRCR_GRMSK                 LTDC_LxRCR_GRMSK_Msk  /*!< shadow reload control: global (centralized) reload maskedThis bit is set and cleared by software.- 0: global reload active (the control from the LTDC_SRCR are enabled)- 1: global reload is masked (the control from the LTDC_SRCR are disabled) */
+
+/* Bit fields for LTDC_LxCR register */
+#define LTDC_LxCR_LEN_Pos                (0U)
+#define LTDC_LxCR_LEN_Msk                (0x1UL << LTDC_LxCR_LEN_Pos)
+#define LTDC_LxCR_LEN                    LTDC_LxCR_LEN_Msk  /*!< layer enable: the bit is used to enable/disable the presence of this whole layer.This bit is set and cleared by software.- 0: layer disabled- 1: layer enabled */
+#define LTDC_LxCR_CKEN_Pos               (1U)
+#define LTDC_LxCR_CKEN_Msk               (0x1UL << LTDC_LxCR_CKEN_Pos)
+#define LTDC_LxCR_CKEN                   LTDC_LxCR_CKEN_Msk  /*!< color keying enableThis bit is set and cleared by software.- 0: color keying disabled- 1: color keying enabled: if RGB matches, then the ARGB are set to 0. */
+#define LTDC_LxCR_VPDEN_Pos              (2U)
+#define LTDC_LxCR_VPDEN_Msk              (0x1UL << LTDC_LxCR_VPDEN_Pos)
+#define LTDC_LxCR_VPDEN                  LTDC_LxCR_VPDEN_Msk  /*!< vertical pixel duplication enableThis bit is set and cleared by software.- 0: duplication disabled- 1: duplication enabled */
+#define LTDC_LxCR_CLUTEN_Pos             (4U)
+#define LTDC_LxCR_CLUTEN_Msk             (0x1UL << LTDC_LxCR_CLUTEN_Pos)
+#define LTDC_LxCR_CLUTEN                 LTDC_LxCR_CLUTEN_Msk  /*!< color look-up table enableThis bit is set and cleared by software.- 0: color look-up table disabled- 1: color look-up table enabledThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up table (CLUT) */
+#define LTDC_LxCR_HMEN_Pos               (8U)
+#define LTDC_LxCR_HMEN_Msk               (0x1UL << LTDC_LxCR_HMEN_Pos)
+#define LTDC_LxCR_HMEN                   LTDC_LxCR_HMEN_Msk  /*!< horizontal mirroring enableThis bit is set and cleared by software.- 0: mirror disabled- 1: mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instannce: if line is 100 pixels, 24bpp, then address is set to 299) */
+#define LTDC_LxCR_DCBEN_Pos              (9U)
+#define LTDC_LxCR_DCBEN_Msk              (0x1UL << LTDC_LxCR_DCBEN_Pos)
+#define LTDC_LxCR_DCBEN                  LTDC_LxCR_DCBEN_Msk  /*!< default color blending enableThis bit is set and cleared by software.- 0: blending disabled- 1: blending enabled */
+
+/* Bit fields for LTDC_LxWHPCR register */
+#define LTDC_LxWHPCR_WHSTPOS_Pos         (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSTPOS_Pos)
+#define LTDC_LxWHPCR_WHSTPOS             LTDC_LxWHPCR_WHSTPOS_Msk  /*!< window horizontal start positionThese bits configure the first visible pixel of a line of the layer window.WHSTPOS[15:0] must be >= AAW[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWHPCR_WHSPPOS_Pos         (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos)
+#define LTDC_LxWHPCR_WHSPPOS             LTDC_LxWHPCR_WHSPPOS_Msk  /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxWVPCR register */
+#define LTDC_LxWVPCR_WVSTPOS_Pos         (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos)
+#define LTDC_LxWVPCR_WVSTPOS             LTDC_LxWVPCR_WVSTPOS_Msk  /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWVPCR_WVSPPOS_Pos         (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos)
+#define LTDC_LxWVPCR_WVSPPOS             LTDC_LxWVPCR_WVSPPOS_Msk  /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxCKCR register */
+#define LTDC_LxCKCR_CKBLUE_Pos           (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk           (0xffUL << LTDC_LxCKCR_CKBLUE_Pos)
+#define LTDC_LxCKCR_CKBLUE               LTDC_LxCKCR_CKBLUE_Msk  /*!< color key blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos          (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk          (0xffUL << LTDC_LxCKCR_CKGREEN_Pos)
+#define LTDC_LxCKCR_CKGREEN              LTDC_LxCKCR_CKGREEN_Msk  /*!< color key green value */
+#define LTDC_LxCKCR_CKRED_Pos            (16U)
+#define LTDC_LxCKCR_CKRED_Msk            (0xffUL << LTDC_LxCKCR_CKRED_Pos)
+#define LTDC_LxCKCR_CKRED                LTDC_LxCKCR_CKRED_Msk  /*!< color key red value */
+
+/* Bit fields for LTDC_LxPFCR register */
+#define LTDC_LxPFCR_PF_Pos               (0U)
+#define LTDC_LxPFCR_PF_Msk               (0x7UL << LTDC_LxPFCR_PF_Pos)
+#define LTDC_LxPFCR_PF                   LTDC_LxPFCR_PF_Msk  /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */
+
+/* Bit fields for LTDC_LxCACR register */
+#define LTDC_LxCACR_CONSTA_Pos           (0U)
+#define LTDC_LxCACR_CONSTA_Msk           (0xffUL << LTDC_LxCACR_CONSTA_Pos)
+#define LTDC_LxCACR_CONSTA               LTDC_LxCACR_CONSTA_Msk  /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */
+
+/* Bit fields for LTDC_LxDCCR register */
+#define LTDC_LxDCCR_DCBLUE_Pos           (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk           (0xffUL << LTDC_LxDCCR_DCBLUE_Pos)
+#define LTDC_LxDCCR_DCBLUE               LTDC_LxDCCR_DCBLUE_Msk  /*!< default color blueThese bits configure the default blue value. */
+#define LTDC_LxDCCR_DCGREEN_Pos          (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk          (0xffUL << LTDC_LxDCCR_DCGREEN_Pos)
+#define LTDC_LxDCCR_DCGREEN              LTDC_LxDCCR_DCGREEN_Msk  /*!< default color greenThese bits configure the default green value. */
+#define LTDC_LxDCCR_DCRED_Pos            (16U)
+#define LTDC_LxDCCR_DCRED_Msk            (0xffUL << LTDC_LxDCCR_DCRED_Pos)
+#define LTDC_LxDCCR_DCRED                LTDC_LxDCCR_DCRED_Msk  /*!< default color redThese bits configure the default red value. */
+#define LTDC_LxDCCR_DCALPHA_Pos          (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk          (0xffUL << LTDC_LxDCCR_DCALPHA_Pos)
+#define LTDC_LxDCCR_DCALPHA              LTDC_LxDCCR_DCALPHA_Msk  /*!< default color alphaThese bits configure the default alpha value. */
+
+/* Bit fields for LTDC_LxBFCR register */
+#define LTDC_LxBFCR_BF2_Pos              (0U)
+#define LTDC_LxBFCR_BF2_Msk              (0x7UL << LTDC_LxBFCR_BF2_Pos)
+#define LTDC_LxBFCR_BF2                  LTDC_LxBFCR_BF2_Msk  /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */
+#define LTDC_LxBFCR_BF1_Pos              (8U)
+#define LTDC_LxBFCR_BF1_Msk              (0x7UL << LTDC_LxBFCR_BF1_Pos)
+#define LTDC_LxBFCR_BF1                  LTDC_LxBFCR_BF1_Msk  /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */
+#define LTDC_LxBFCR_BOR_Pos              (16U)
+#define LTDC_LxBFCR_BOR_Msk              (0x1UL << LTDC_LxBFCR_BOR_Pos)
+#define LTDC_LxBFCR_BOR                  LTDC_LxBFCR_BOR_Msk  /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */
+
+/* Bit fields for LTDC_LxBLCR register */
+#define LTDC_LxBLCR_BL_Pos               (0U)
+#define LTDC_LxBLCR_BL_Msk               (0x1fUL << LTDC_LxBLCR_BL_Pos)
+#define LTDC_LxBLCR_BL                   LTDC_LxBLCR_BL_Msk  /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */
+
+/* Bit fields for LTDC_LxPCR register */
+#define LTDC_LxPCR_YCEN_Pos              (3U)
+#define LTDC_LxPCR_YCEN_Msk              (0x1UL << LTDC_LxPCR_YCEN_Pos)
+#define LTDC_LxPCR_YCEN                  LTDC_LxPCR_YCEN_Msk  /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */
+#define LTDC_LxPCR_YCM_Pos               (4U)
+#define LTDC_LxPCR_YCM_Msk               (0x3UL << LTDC_LxPCR_YCM_Pos)
+#define LTDC_LxPCR_YCM                   LTDC_LxPCR_YCM_Msk  /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */
+#define LTDC_LxPCR_YF_Pos                (6U)
+#define LTDC_LxPCR_YF_Msk                (0x1UL << LTDC_LxPCR_YF_Pos)
+#define LTDC_LxPCR_YF                    LTDC_LxPCR_YF_Msk  /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */
+#define LTDC_LxPCR_CBF_Pos               (7U)
+#define LTDC_LxPCR_CBF_Msk               (0x1UL << LTDC_LxPCR_CBF_Pos)
+#define LTDC_LxPCR_CBF                   LTDC_LxPCR_CBF_Msk  /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */
+#define LTDC_LxPCR_OF_Pos                (8U)
+#define LTDC_LxPCR_OF_Msk                (0x1UL << LTDC_LxPCR_OF_Pos)
+#define LTDC_LxPCR_OF                    LTDC_LxPCR_OF_Msk  /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */
+#define LTDC_LxPCR_YREN_Pos              (9U)
+#define LTDC_LxPCR_YREN_Msk              (0x1UL << LTDC_LxPCR_YREN_Pos)
+#define LTDC_LxPCR_YREN                  LTDC_LxPCR_YREN_Msk  /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */
+
+/* Bit fields for LTDC_LxCFBAR register */
+#define LTDC_LxCFBAR_CFBADD_Pos          (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk          (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos)
+#define LTDC_LxCFBAR_CFBADD              LTDC_LxCFBAR_CFBADD_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxCFBLR register */
+#define LTDC_LxCFBLR_CFBLL_Pos           (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk           (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos)
+#define LTDC_LxCFBLR_CFBLL               LTDC_LxCFBLR_CFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_LxCFBLR_CFBP_Pos            (16U)
+#define LTDC_LxCFBLR_CFBP_Msk            (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos)
+#define LTDC_LxCFBLR_CFBP                LTDC_LxCFBLR_CFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxCFBLNR register */
+#define LTDC_LxCFBLNR_CFBLNBR_Pos        (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk        (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
+#define LTDC_LxCFBLNR_CFBLNBR            LTDC_LxCFBLNR_CFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_L1AFBA0R register */
+#define LTDC_L1AFBA0R_AFBADD0_Pos        (0U)
+#define LTDC_L1AFBA0R_AFBADD0_Msk        (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos)
+#define LTDC_L1AFBA0R_AFBADD0            LTDC_L1AFBA0R_AFBADD0_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBA1R register */
+#define LTDC_L1AFBA1R_AFBADD1_Pos        (0U)
+#define LTDC_L1AFBA1R_AFBADD1_Msk        (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos)
+#define LTDC_L1AFBA1R_AFBADD1            LTDC_L1AFBA1R_AFBADD1_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBLR register */
+#define LTDC_L1AFBLR_AFBLL_Pos           (0U)
+#define LTDC_L1AFBLR_AFBLL_Msk           (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos)
+#define LTDC_L1AFBLR_AFBLL               LTDC_L1AFBLR_AFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_L1AFBLR_AFBP_Pos            (16U)
+#define LTDC_L1AFBLR_AFBP_Msk            (0xffffUL << LTDC_L1AFBLR_AFBP_Pos)
+#define LTDC_L1AFBLR_AFBP                LTDC_L1AFBLR_AFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxAFBLNR register */
+#define LTDC_L1AFBLNR_AFBLNBR_Pos        (0U)
+#define LTDC_L1AFBLNR_AFBLNBR_Msk        (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos)
+#define LTDC_L1AFBLNR_AFBLNBR            LTDC_L1AFBLNR_AFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_LxCLUTWR register */
+#define LTDC_LxCLUTWR_BLUE_Pos           (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk           (0xffUL << LTDC_LxCLUTWR_BLUE_Pos)
+#define LTDC_LxCLUTWR_BLUE               LTDC_LxCLUTWR_BLUE_Msk  /*!< blue valueThese bits configure the blue value. */
+#define LTDC_LxCLUTWR_GREEN_Pos          (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk          (0xffUL << LTDC_LxCLUTWR_GREEN_Pos)
+#define LTDC_LxCLUTWR_GREEN              LTDC_LxCLUTWR_GREEN_Msk  /*!< green valueThese bits configure the green value. */
+#define LTDC_LxCLUTWR_RED_Pos            (16U)
+#define LTDC_LxCLUTWR_RED_Msk            (0xffUL << LTDC_LxCLUTWR_RED_Pos)
+#define LTDC_LxCLUTWR_RED                LTDC_LxCLUTWR_RED_Msk  /*!< red valueThese bits configure the red value. */
+#define LTDC_LxCLUTWR_CLUTADD_Pos        (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk        (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos)
+#define LTDC_LxCLUTWR_CLUTADD            LTDC_LxCLUTWR_CLUTADD_Msk  /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */
+
+/* Bit fields for LTDC_LxCYR0R register */
+#define LTDC_LxCYR0R_CR2R_Pos            (0U)
+#define LTDC_LxCYR0R_CR2R_Msk            (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos)
+#define LTDC_LxCYR0R_CR2R                LTDC_LxCYR0R_CR2R_Msk  /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR0R_CB2B_Pos            (16U)
+#define LTDC_LxCYR0R_CB2B_Msk            (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos)
+#define LTDC_LxCYR0R_CB2B                LTDC_LxCYR0R_CB2B_Msk  /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxCYR1R register */
+#define LTDC_LxCYR1R_CR2G_Pos            (0U)
+#define LTDC_LxCYR1R_CR2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos)
+#define LTDC_LxCYR1R_CR2G                LTDC_LxCYR1R_CR2G_Msk  /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR1R_CB2G_Pos            (16U)
+#define LTDC_LxCYR1R_CB2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos)
+#define LTDC_LxCYR1R_CB2G                LTDC_LxCYR1R_CB2G_Msk  /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxFPF0R register */
+#define LTDC_LxFPF0R_APOS_Pos            (0U)
+#define LTDC_LxFPF0R_APOS_Msk            (0x1fUL << LTDC_LxFPF0R_APOS_Pos)
+#define LTDC_LxFPF0R_APOS                LTDC_LxFPF0R_APOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_ALEN_Pos            (5U)
+#define LTDC_LxFPF0R_ALEN_Msk            (0xfUL << LTDC_LxFPF0R_ALEN_Pos)
+#define LTDC_LxFPF0R_ALEN                LTDC_LxFPF0R_ALEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF0R_RPOS_Pos            (9U)
+#define LTDC_LxFPF0R_RPOS_Msk            (0x1fUL << LTDC_LxFPF0R_RPOS_Pos)
+#define LTDC_LxFPF0R_RPOS                LTDC_LxFPF0R_RPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_RLEN_Pos            (14U)
+#define LTDC_LxFPF0R_RLEN_Msk            (0xfUL << LTDC_LxFPF0R_RLEN_Pos)
+#define LTDC_LxFPF0R_RLEN                LTDC_LxFPF0R_RLEN_Msk  /*!< Width of the red component (in bits). */
+
+/* Bit fields for LTDC_LxFPF1R register */
+#define LTDC_LxFPF1R_GPOS_Pos            (0U)
+#define LTDC_LxFPF1R_GPOS_Msk            (0x1fUL << LTDC_LxFPF1R_GPOS_Pos)
+#define LTDC_LxFPF1R_GPOS                LTDC_LxFPF1R_GPOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_GLEN_Pos            (5U)
+#define LTDC_LxFPF1R_GLEN_Msk            (0xfUL << LTDC_LxFPF1R_GLEN_Pos)
+#define LTDC_LxFPF1R_GLEN                LTDC_LxFPF1R_GLEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF1R_BPOS_Pos            (9U)
+#define LTDC_LxFPF1R_BPOS_Msk            (0x1fUL << LTDC_LxFPF1R_BPOS_Pos)
+#define LTDC_LxFPF1R_BPOS                LTDC_LxFPF1R_BPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_BLEN_Pos            (14U)
+#define LTDC_LxFPF1R_BLEN_Msk            (0xfUL << LTDC_LxFPF1R_BLEN_Pos)
+#define LTDC_LxFPF1R_BLEN                LTDC_LxFPF1R_BLEN_Msk  /*!< Width of the red component (in bits). */
+
+#define LTDC_LxFPF1R_PSIZE_Pos            (18U)
+#define LTDC_LxFPF1R_PSIZE_Msk            (0x7UL << LTDC_LxFPF1R_PSIZE_Pos)
+#define LTDC_LxFPF1R_PSIZE                LTDC_LxFPF1R_PSIZE_Msk  /*!< Width of the red component (in bits). */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDF/ADF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for MDF/ADF_GCR register  ****************/
+#define MDF_GCR_TRGO_Pos                    (0U)
+#define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
+#define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!< Trigger output control */
+#define MDF_GCR_ILVNB_Pos                   (4U)
+#define MDF_GCR_ILVNB_Msk                   (0xFUL << MDF_GCR_ILVNB_Pos)            /*!< 0x000000F0 */
+#define MDF_GCR_ILVNB                       MDF_GCR_ILVNB_Msk                       /*!< Interleaved Number */
+
+/*******************  Bit definition for MDF/ADF_CKGCR register  ********************/
+#define MDF_CKGCR_CKDEN_Pos                 (0U)
+#define MDF_CKGCR_CKDEN_Msk                 (0x1UL << MDF_CKGCR_CKDEN_Pos)          /*!< 0x00000001 */
+#define MDF_CKGCR_CKDEN                     MDF_CKGCR_CKDEN_Msk                     /*!<CKGEN diveders enable */
+#define MDF_CKGCR_CCK0EN_Pos                (1U)
+#define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
+#define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!<CCK0 clock enable */
+#define MDF_CKGCR_CCK1EN_Pos                (2U)
+#define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
+#define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!<CCK1 clock enable */
+#define MDF_CKGCR_CKGMOD_Pos                (4U)
+#define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
+#define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!<Clock genartor mode */
+#define MDF_CKGCR_CCK0DIR_Pos               (5U)
+#define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
+#define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!<CCK0 clock direction */
+#define MDF_CKGCR_CCK1DIR_Pos               (6U)
+#define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
+#define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!<CCK1 clock direction */
+#define MDF_CKGCR_TRGSENS_Pos               (8U)
+#define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
+#define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!<CKGEN trigger sensitivity selection */
+#define MDF_CKGCR_TRGSRC_Pos                (12U)
+#define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
+#define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!<Digital Filter trigger signal selection */
+#define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
+#define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
+#define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
+#define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
+#define MDF_CKGCR_CCKDIV_Pos                (16U)
+#define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
+#define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!<Divider to control the MDF_CCK clock */
+#define MDF_CKGCR_PROCDIV_Pos               (24U)
+#define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
+#define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!<Divider to control the serial interface clock */
+#define MDF_CKGCR_CCKACTIVE_Pos             (31U)
+#define MDF_CKGCR_CCKACTIVE_Msk             (0x1UL << MDF_CKGCR_CCKACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_CKGCR_CCKACTIVE                 MDF_CKGCR_CCKACTIVE_Msk                 /*!<Clock generator active flag */
+
+/*******************  Bit definition for MDF/ADF_OR register  ********************/
+#define MDF_OR_OPTION_Pos                   (0U)
+#define MDF_OR_OPTION_Msk                   (0xFFFFFFFFUL << MDF_OR_OPTION_Pos)     /*!< 0xFFFFFFFF */
+#define MDF_OR_OPTION                       MDF_OR_OPTION_Msk                       /*!<Option Control Bits */
+
+/*******************  Bit definition for MDF/ADF_SITFxCR register  ********************/
+#define MDF_SITFCR_SITFEN_Pos               (0U)
+#define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
+#define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!<Serial interface enable */
+#define MDF_SITFCR_SCKSRC_Pos               (1U)
+#define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
+#define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!<Serial clock source */
+#define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SITFMOD_Pos              (4U)
+#define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
+#define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!<Serial interface type */
+#define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
+#define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
+#define MDF_SITFCR_STH_Pos                  (8U)
+#define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
+#define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!<Manchester Symbol threshold / SPI threshold */
+#define MDF_SITFCR_SITFACTIVE_Pos           (31U)
+#define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
+#define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!<Serial interface active flag */
+
+/*******************  Bit definition for MDF/ADF_BSMXxCR register  ********************/
+#define MDF_BSMXCR_BSSEL_Pos                (0U)
+#define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
+#define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!<Bit Streal selection */
+#define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
+#define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
+#define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
+#define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
+#define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
+#define MDF_BSMXCR_BSMXACTIVATE_Pos         (31U)
+#define MDF_BSMXCR_BSMXACTIVATE_Msk         (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos)  /*!< 0x80000000 */
+#define MDF_BSMXCR_BSMXACTIVATE             MDF_BSMXCR_BSMXACTIVATE_Msk             /*!<Bit Streal activation flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCR register  ********************/
+#define MDF_DFLTCR_DFLTEN_Pos               (0U)
+#define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!<Digital filter enable */
+#define MDF_DFLTCR_DMAEN_Pos                (1U)
+#define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
+#define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!<DMA request enable */
+#define MDF_DFLTCR_FTH_Pos                  (2U)
+#define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
+#define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!<RXFIFO Threshold selection */
+#define MDF_DFLTCR_ACQMOD_Pos               (4U)
+#define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!<Digital filter trigger mode */
+#define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
+#define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
+#define MDF_DFLTCR_TRGSENS_Pos              (8U)
+#define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!<Digital filter trigger sensitivity selection */
+#define MDF_DFLTCR_TRGSRC_Pos               (12U)
+#define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!<Digital filter trigger signal selection */
+#define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
+#define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
+#define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
+#define MDF_DFLTCR_SNPSFMT_Pos              (16U)
+#define MDF_DFLTCR_SNPSFMT_Msk              (0x1UL << MDF_DFLTCR_SNPSFMT_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_SNPSFMT                  MDF_DFLTCR_SNPSFMT_Msk                  /*!<SnapShot Data format */
+#define MDF_DFLTCR_NBDIS_Pos                (20U)
+#define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!<Number of samples to be discard */
+#define MDF_DFLTCR_DFLTRUN_Pos              (30U)
+#define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!<Digital filter run status flag */
+#define MDF_DFLTCR_DFLTACTIVE_Pos           (31U)
+#define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!<Digital filter active flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCICR register  ********************/
+#define MDF_DFLTCICR_DATSRC_Pos             (0U)
+#define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!<Source Data for the digital filter */
+#define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTCICR_CICMOD_Pos             (4U)
+#define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
+#define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!<Select the CIC Mode*/
+#define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
+#define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
+#define MDF_DFLTCICR_MCICD_Pos              (8U)
+#define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
+#define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!<CIC decimation ratio selection*/
+#define MDF_DFLTCICR_SCALE_Pos              (20U)
+#define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
+#define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!<Scaling factor selection*/
+
+/*******************  Bit definition for MDF/ADF_DFLTxRSFR register  ********************/
+#define MDF_DFLTRSFR_RSFLTBYP_Pos           (0U)
+#define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
+#define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!<Reshape filter bypass*/
+#define MDF_DFLTRSFR_RSFLTD_Pos             (4U)
+#define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!<Reshape filter decimation ratio*/
+#define MDF_DFLTRSFR_HPFBYP_Pos             (7U)
+#define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!<High-pass filter bypass*/
+#define MDF_DFLTRSFR_HPFC_Pos               (8U)
+#define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!<High-pass filter cut-off frequency*/
+#define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
+#define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)
+
+/*******************  Bit definition for MDF/ADF_DFLTxINTR register  ********************/
+#define MDF_DFLTINTR_INTDIV_Pos             (0U)
+#define MDF_DFLTINTR_INTDIV_Msk             (0x3UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTINTR_INTDIV                 MDF_DFLTINTR_INTDIV_Msk                 /*!<Integrator output dividion*/
+#define MDF_DFLTINTR_INTDIV_0               (0x1UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTINTR_INTDIV_1               (0x2UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTINTR_INTVAL_Pos             (4U)
+#define MDF_DFLTINTR_INTVAL_Msk             (0x7FUL << MDF_DFLTINTR_INTVAL_Pos)     /*!< 0x000007F0 */
+#define MDF_DFLTINTR_INTVAL                 MDF_DFLTINTR_INTVAL_Msk                 /*!<Integrator value selection*/
+
+/*******************  Bit definition for MDF/ADF_OLDxCR register  ********************/
+#define MDF_OLDCR_OLDEN_Pos                 (0U)
+#define MDF_OLDCR_OLDEN_Msk                 (0x1UL << MDF_OLDCR_OLDEN_Pos)          /*!< 0x00000001 */
+#define MDF_OLDCR_OLDEN                     MDF_OLDCR_OLDEN_Msk                     /*!<OLD enable*/
+#define MDF_OLDCR_THINB_Pos                 (1U)
+#define MDF_OLDCR_THINB_Msk                 (0x1UL << MDF_OLDCR_THINB_Pos)          /*!< 0x00000002 */
+#define MDF_OLDCR_THINB                     MDF_OLDCR_THINB_Msk                     /*!<OLD threshold in band*/
+#define MDF_OLDCR_BKOLD_Pos                 (4U)
+#define MDF_OLDCR_BKOLD_Msk                 (0xFUL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x000000F0 */
+#define MDF_OLDCR_BKOLD                     MDF_OLDCR_BKOLD_Msk                     /*!<Bteak signal assignment for OLD*/
+#define MDF_OLDCR_BKOLD_0                   (0x1UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000010 */
+#define MDF_OLDCR_BKOLD_1                   (0x2UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000020 */
+#define MDF_OLDCR_BKOLD_2                   (0x4UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000040 */
+#define MDF_OLDCR_BKOLD_3                   (0x8UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000080 */
+#define MDF_OLDCR_ACICN_Pos                 (12U)
+#define MDF_OLDCR_ACICN_Msk                 (0x3UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00003000 */
+#define MDF_OLDCR_ACICN                     MDF_OLDCR_ACICN_Msk                     /*!<OLD CIC order selection*/
+#define MDF_OLDCR_ACICN_0                   (0x1UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00001000 */
+#define MDF_OLDCR_ACICN_1                   (0x2UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00002000 */
+#define MDF_OLDCR_ACICD_Pos                 (17U)
+#define MDF_OLDCR_ACICD_Msk                 (0x1FUL << MDF_OLDCR_ACICD_Pos)         /*!< 0x003E0000 */
+#define MDF_OLDCR_ACICD                     MDF_OLDCR_ACICD_Msk                     /*!<OLD CIC decimation ratio selection*/
+#define MDF_OLDCR_OLDACTIVE_Pos             (31U)
+#define MDF_OLDCR_OLDACTIVE_Msk             (0x1UL << MDF_OLDCR_OLDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_OLDCR_OLDACTIVE                 MDF_OLDCR_OLDACTIVE_Msk                 /*!<OLD active flag*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHLR register  ********************/
+#define MDF_OLDTHLR_OLDTHL_Pos              (0U)
+#define MDF_OLDTHLR_OLDTHL_Msk              (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHLR_OLDTHL                  MDF_OLDTHLR_OLDTHL_Msk                  /*!<OLD Low threshold value*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHHR register  ********************/
+#define MDF_OLDTHHR_OLDTHH_Pos              (0U)
+#define MDF_OLDTHHR_OLDTHH_Msk              (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHHR_OLDTHH                  MDF_OLDTHHR_OLDTHH_Msk                  /*!<OLD High threshold value*/
+
+/*******************  Bit definition for MDF/ADF_DLYxCR register  ********************/
+#define MDF_DLYCR_SKPDLY_Pos                (0U)
+#define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
+#define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!<Delay to apply to a bitstream*/
+#define MDF_DLYCR_SKPBF_Pos                 (31U)
+#define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
+#define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!<DSkip Busy Flag*/
+
+/*******************  Bit definition for MDF/ADF_SCDxCR register  ********************/
+#define MDF_SCDCR_SCDEN_Pos                 (0U)
+#define MDF_SCDCR_SCDEN_Msk                 (0x1UL << MDF_SCDCR_SCDEN_Pos)          /*!< 0x00000001 */
+#define MDF_SCDCR_SCDEN                     MDF_SCDCR_SCDEN_Msk                     /*!<Short circuit detector enable*/
+#define MDF_SCDCR_BKSCD_Pos                 (4U)
+#define MDF_SCDCR_BKSCD_Msk                 (0xFUL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x000000F0 */
+#define MDF_SCDCR_BKSCD                     MDF_SCDCR_BKSCD_Msk                     /*!<Break signal assignment to short circuit detector */
+#define MDF_SCDCR_BKSCD_0                   (0x1UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000010 */
+#define MDF_SCDCR_BKSCD_1                   (0x2UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000020 */
+#define MDF_SCDCR_BKSCD_2                   (0x4UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000040 */
+#define MDF_SCDCR_BKSCD_3                   (0x8UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000080 */
+#define MDF_SCDCR_SCDT_Pos                  (12U)
+#define MDF_SCDCR_SCDT_Msk                  (0xFFUL << MDF_SCDCR_SCDT_Pos)          /*!< 0x00000FF00 */
+#define MDF_SCDCR_SCDT                      MDF_SCDCR_SCDT_Msk                      /*!<Short circuit detector threshold*/
+#define MDF_SCDCR_SCDACTIVE_Pos             (31U)
+#define MDF_SCDCR_SCDACTIVE_Msk             (0x1UL << MDF_SCDCR_SCDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SCDCR_SCDACTIVE                 MDF_SCDCR_SCDACTIVE_Msk                 /*!<Short circuit detector active flag*/
+
+/*******************  Bit definition for MDF/ADF_DFLTIER register  ********************/
+#define MDF_DFLTIER_FTHIE_Pos               (0U)
+#define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!<RXFIFO threshold interrupt enable*/
+#define MDF_DFLTIER_DOVRIE_Pos              (1U)
+#define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
+#define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!<Data overflow interrupt enable*/
+#define MDF_DFLTIER_SSDRIE_Pos              (2U)
+#define MDF_DFLTIER_SSDRIE_Msk              (0x1UL << MDF_DFLTIER_SSDRIE_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTIER_SSDRIE                  MDF_DFLTIER_SSDRIE_Msk                  /*!<Snapshot data ready interrupt enable*/
+#define MDF_DFLTIER_OLDIE_Pos               (4U)
+#define MDF_DFLTIER_OLDIE_Msk               (0x1UL << MDF_DFLTIER_OLDIE_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTIER_OLDIE                   MDF_DFLTIER_OLDIE_Msk                   /*!<OLD interrupt enable*/
+#define MDF_DFLTIER_SSOVRIE_Pos             (7U)
+#define MDF_DFLTIER_SSOVRIE_Msk             (0x1UL << MDF_DFLTIER_SSOVRIE_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTIER_SSOVRIE                 MDF_DFLTIER_SSOVRIE_Msk                 /*!<Snapshot overrun interrupt enable*/
+#define MDF_DFLTIER_SCDIE_Pos               (8U)
+#define MDF_DFLTIER_SCDIE_Msk               (0x1UL << MDF_DFLTIER_SCDIE_Pos)        /*!< 0x00000100 */
+#define MDF_DFLTIER_SCDIE                   MDF_DFLTIER_SCDIE_Msk                   /*!<Short circuit dtector interrupt enable*/
+#define MDF_DFLTIER_SATIE_Pos               (9U)
+#define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
+#define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!<Saturation detection interrupt enable*/
+#define MDF_DFLTIER_CKABIE_Pos              (10U)
+#define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
+#define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!<Clock absence detection interrupt enable*/
+#define MDF_DFLTIER_RFOVRIE_Pos             (11U)
+#define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
+#define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!<reshape filter overrun interrupt enable*/
+#define MDF_DFLTIER_SDDETIE_Pos             (12U)
+#define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
+#define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!<SAD interrupt enable*/
+#define MDF_DFLTIER_SDLVLIE_Pos             (13U)
+#define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
+#define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!<Sound level value ready interrupt enable*/
+
+/*******************  Bit definition for MDF/ADF_DFLTISR register  ********************/
+#define MDF_DFLTISR_FTHF_Pos                (0U)
+#define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
+#define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!<RXFIFO threshold interrupt flag*/
+#define MDF_DFLTISR_DOVRF_Pos               (1U)
+#define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
+#define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!<Data overflow interrupt flag*/
+#define MDF_DFLTISR_SSDRF_Pos               (2U)
+#define MDF_DFLTISR_SSDRF_Msk               (0x1UL << MDF_DFLTISR_SSDRF_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTISR_SSDRF                   MDF_DFLTISR_SSDRF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_RXNEF_Pos               (3U)
+#define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
+#define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_OLDF_Pos                (4U)
+#define MDF_DFLTISR_OLDF_Msk                (0x1UL << MDF_DFLTISR_OLDF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_OLDF                    MDF_DFLTISR_OLDF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THLF_Pos                (5U)
+#define MDF_DFLTISR_THLF_Msk                (0x1UL << MDF_DFLTISR_THLF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THLF                    MDF_DFLTISR_THLF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THHF_Pos                (6U)
+#define MDF_DFLTISR_THHF_Msk                (0x1UL << MDF_DFLTISR_THHF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THHF                    MDF_DFLTISR_THHF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_SSOVRF_Pos              (7U)
+#define MDF_DFLTISR_SSOVRF_Msk              (0x1UL << MDF_DFLTISR_SSOVRF_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTISR_SSOVRF                  MDF_DFLTISR_SSOVRF_Msk                  /*!<Snapshot overrun interrupt flag*/
+#define MDF_DFLTISR_SCDF_Pos                (8U)
+#define MDF_DFLTISR_SCDF_Msk                (0x1UL << MDF_DFLTISR_SCDF_Pos)         /*!< 0x00000100 */
+#define MDF_DFLTISR_SCDF                    MDF_DFLTISR_SCDF_Msk                    /*!<Short circuit dtector interrupt flag*/
+#define MDF_DFLTISR_SATF_Pos                (9U)
+#define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
+#define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!<Saturation detection interrupt flag*/
+#define MDF_DFLTISR_CKABF_Pos               (10U)
+#define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
+#define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!<Clock absence detection interrupt flag*/
+#define MDF_DFLTISR_RFOVRF_Pos              (11U)
+#define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
+#define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!<reshape filter overrun interrupt flag*/
+#define MDF_DFLTISR_SDDETF_Pos              (12U)
+#define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!<SAD interrupt flag*/
+#define MDF_DFLTISR_SDLVLF_Pos              (13U)
+#define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
+#define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!<Sound level value ready interrupt flag*/
+
+/*******************  Bit definition for MDF/ADF_OECCR register  ********************/
+#define MDF_OECCR_OFFSET_Pos                (0U)
+#define MDF_OECCR_OFFSET_Msk                (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos)   /*!< 0x03FFFFFF */
+#define MDF_OECCR_OFFSET                    MDF_OECCR_OFFSET_Msk                    /*!<Short circuit detector enable*/
+
+/*******************  Bit definition for MDF/ADF_SADCR register  ********************/
+#define MDF_SADCR_SADEN_Pos                 (0U)
+#define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
+#define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!<SAD enable*/
+#define MDF_SADCR_DATCAP_Pos                (1U)
+#define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
+#define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!<SAD data capture mode*/
+#define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
+#define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
+#define MDF_SADCR_DETCFG_Pos                (3U)
+#define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
+#define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!<SAD trigger event configuration*/
+#define MDF_SADCR_SADST_Pos                 (4U)
+#define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
+#define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!<SAD state*/
+#define MDF_SADCR_HYSTEN_Pos                (7U)
+#define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
+#define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!<Hysteresis enable*/
+#define MDF_SADCR_FRSIZE_Pos                (8U)
+#define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
+#define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!<Frame size*/
+#define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
+#define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
+#define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
+#define MDF_SADCR_SADMOD_Pos                (12U)
+#define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
+#define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!<SAD working mode*/
+#define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
+#define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
+#define MDF_SADCR_SADACTIVE_Pos             (31U)
+#define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!<SAD active flag*/
+
+/*******************  Bit definition for MDF/ADF_SADCFGR register  ********************/
+#define MDF_SADCFGR_SNTHR_Pos               (0U)
+#define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
+#define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!<Signal to noise threshold*/
+#define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
+#define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
+#define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
+#define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
+#define MDF_SADCFGR_ANSLP_Pos               (4U)
+#define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
+#define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!<Ambiant noise slope control*/
+#define MDF_SADCFGR_LFRNB_Pos               (8U)
+#define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
+#define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!<Number of learning frames*/
+#define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
+#define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
+#define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
+#define MDF_SADCFGR_HGOVR_Pos               (12U)
+#define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
+#define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!<Hangover time window*/
+#define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
+#define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
+#define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
+#define MDF_SADCFGR_ANMIN_Pos               (16U)
+#define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
+#define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!<Hangover time window*/
+
+/*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
+#define MDF_SADSDLVR_SDLVL_Pos              (0U)
+#define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!<Short term sound level*/
+
+/*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
+#define MDF_SADANLVR_ANLVL_Pos              (0U)
+#define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!<Ambiant noise level estimation*/
+
+/*******************  Bit definition for MDF/ADF_SNPSDR register  ********************/
+#define MDF_SNPSDR_MCICDC_Pos               (0U)
+#define MDF_SNPSDR_MCICDC_Msk               (0x1FFUL << MDF_SNPSDR_MCICDC_Pos)      /*!< 0x000001FF */
+#define MDF_SNPSDR_MCICDC                   MDF_SNPSDR_MCICDC_Msk                   /*!<MCIC decimation counter*/
+#define MDF_SNPSDR_EXTSDR_Pos               (9U)
+#define MDF_SNPSDR_EXTSDR_Msk               (0x7FUL << MDF_SNPSDR_EXTSDR_Pos)       /*!< 0x0000FE00 */
+#define MDF_SNPSDR_EXTSDR                   MDF_SNPSDR_EXTSDR_Msk                   /*!<Extended data size*/
+#define MDF_SNPSDR_SDR_Pos                  (16U)
+#define MDF_SNPSDR_SDR_Msk                  (0xFFFFUL << MDF_SNPSDR_SDR_Pos)        /*!< 0xFFFF0000 */
+#define MDF_SNPSDR_SDR                      MDF_SNPSDR_SDR_Msk                      /*!<Extended data size*/
+
+/*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
+#define MDF_DFLTDR_DR_Pos                   (8U)
+#define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
+#define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!<MCIC decimation counter*/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDIOS                                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Public Key Accelerator (PKA)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PKA_CR register  *********************/
+#define PKA_CR_EN_Pos                       (0U)
+#define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
+#define PKA_CR_EN                           PKA_CR_EN_Msk                           /*!< PKA enable */
+#define PKA_CR_START_Pos                    (1U)
+#define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
+#define PKA_CR_START                        PKA_CR_START_Msk                        /*!< Start operation */
+#define PKA_CR_MODE_Pos                     (8U)
+#define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
+#define PKA_CR_MODE                         PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
+#define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
+#define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
+#define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
+#define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
+#define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
+#define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
+#define PKA_CR_PROCENDIE_Pos                (17U)
+#define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
+#define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
+#define PKA_CR_RAMERRIE_Pos                 (19U)
+#define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
+#define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
+#define PKA_CR_ADDRERRIE_Pos                (20U)
+#define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
+#define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                    /*!< Address error interrupt enable */
+#define PKA_CR_OPERRIE_Pos                  (21U)
+#define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)           /*!< 0x00200000 */
+#define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                      /*!< Operation Error interrupt enable */
+
+/*******************  Bit definition for PKA_SR register  *********************/
+#define PKA_SR_INITOK_Pos                   (0U)
+#define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)            /*!< 0x00000001 */
+#define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                       /*!< PKA initialisation flag */
+#define PKA_SR_BUSY_Pos                     (16U)
+#define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
+#define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
+#define PKA_SR_PROCENDF_Pos                 (17U)
+#define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
+#define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
+#define PKA_SR_RAMERRF_Pos                  (19U)
+#define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
+#define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
+#define PKA_SR_ADDRERRF_Pos                 (20U)
+#define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
+#define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
+#define PKA_SR_OPERRF_Pos                   (21U)
+#define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)            /*!< 0x00200000 */
+#define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                       /*!< PKA operation Error flag*/
+
+/*******************  Bit definition for PKA_CLRFR register  ******************/
+#define PKA_CLRFR_PROCENDFC_Pos             (17U)
+#define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
+#define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
+#define PKA_CLRFR_RAMERRFC_Pos              (19U)
+#define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
+#define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
+#define PKA_CLRFR_ADDRERRFC_Pos             (20U)
+#define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
+#define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
+#define PKA_CLRFR_OPERRFC_Pos               (21U)
+#define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)        /*!< 0x00200000 */
+#define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                   /*!< Clear PKA operation Error flag*/
+
+/*******************  Bits definition for PKA RAM  *************************/
+#define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */
+
+/* Compute Montgomery parameter input data */
+#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Compute Montgomery parameter output data */
+#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */
+
+/* Compute modular exponentiation input data */
+#define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
+#define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+#define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
+#define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
+#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */
+
+/* Compute modular exponentiation output data */
+#define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */
+
+/* Compute ECC scalar multiplication input data */
+#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */
+
+/* Compute ECC scalar multiplication output data */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
+
+/* Point check input data */
+#define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+
+/* Point check output data */
+#define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+
+/* ECDSA signature input data */
+#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
+#define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA signature output data */
+#define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */
+
+
+/* ECDSA verification input data */
+#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
+#define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA verification output data */
+#define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* RSA CRT exponentiation input data */
+#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
+#define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
+#define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
+#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+
+/* RSA CRT exponentiation output data */
+#define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular reduction input data */
+#define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
+#define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
+#define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
+#define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Modular reduction output data */
+#define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic addition input data */
+#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic addition output data */
+#define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic subtraction input data */
+#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic subtraction output data */
+#define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic multiplication input data */
+#define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic multiplication output data */
+#define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Comparison input data */
+#define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Comparison output data */
+#define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular addition input data */
+#define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
+
+/* Modular addition output data */
+#define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular inversion input data */
+#define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
+
+/* Modular inversion output data */
+#define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular subtraction input data */
+#define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
+
+/* Modular subtraction output data */
+#define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Montgomery multiplication input data */
+#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
+
+/* Montgomery multiplication output data */
+#define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Generic Arithmetic input data */
+#define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
+
+/* Generic Arithmetic output data */
+#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)   /*!< Output result for arithmetic operations */
+
+/* Compute ECC complete addition input data */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)   /*!< Input Modulus number of bits */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Z coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC complete addition output data */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Z coordinate */
+
+/* Compute ECC double base ladder input data */
+#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS  ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN         ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF              ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER            ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X             ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y             ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z             ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X             ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y             ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z             ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC double base ladder output data */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)      /*!< Output result X coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y          ((0x05D0UL - PKA_RAM_OFFSET)>>2)      /*!< Output result Y coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR             ((0x0520UL - PKA_RAM_OFFSET)>>2)      /*!< Output result error */
+
+/* Compute ECC projective to affine conversion input data */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)  /*!< Input Modulus number of bits */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)  /*!< Input modulus GF(p) */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X               ((0x0D60UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P X coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y               ((0x0DB8UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Y coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z               ((0x0E10UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Z coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2   ((0x04C8UL - PKA_RAM_OFFSET)>>2)  /*!< Input storage area for Montgomery parameter */
+
+/* Compute ECC projective to affine conversion output data */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X      ((0x0578UL - PKA_RAM_OFFSET)>>2)         /*!< Output result x affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y      ((0x05D0UL - PKA_RAM_OFFSET)>>2)         /*!< Output result y affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR         ((0x0680UL - PKA_RAM_OFFSET)>>2)         /*!< Output result error */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                Parallel Synchronous Slave Interface (PSSI )                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PSSI_CR register  *******************/
+#define PSSI_CR_CKPOL_Pos                   (5U)
+#define PSSI_CR_CKPOL_Msk                   (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
+#define PSSI_CR_CKPOL                       PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
+#define PSSI_CR_DEPOL_Pos                   (6U)
+#define PSSI_CR_DEPOL_Msk                   (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
+#define PSSI_CR_DEPOL                       PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
+#define PSSI_CR_RDYPOL_Pos                  (8U)
+#define PSSI_CR_RDYPOL_Msk                  (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
+#define PSSI_CR_RDYPOL                      PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
+#define PSSI_CR_EDM_Pos                     (10U)
+#define PSSI_CR_EDM_Msk                     (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define PSSI_CR_EDM                         PSSI_CR_EDM_Msk                         /*!< Extended data mode */
+#define PSSI_CR_ENABLE_Pos                  (14U)
+#define PSSI_CR_ENABLE_Msk                  (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define PSSI_CR_ENABLE                      PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
+#define PSSI_CR_DERDYCFG_Pos                (18U)
+#define PSSI_CR_DERDYCFG_Msk                (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
+#define PSSI_CR_DERDYCFG                    PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
+#define PSSI_CR_CKSRC_Pos                   (29U)
+#define PSSI_CR_CKSRC_Msk                   (0x1UL << PSSI_CR_CKSRC_Pos)            /*!< 0x20000000 */
+#define PSSI_CR_CKSRC                       PSSI_CR_CKSRC_Msk                       /*!< Clock source */
+#define PSSI_CR_DMAEN_Pos                   (30U)
+#define PSSI_CR_DMAEN_Msk                   (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
+#define PSSI_CR_DMAEN                       PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
+#define PSSI_CR_OUTEN_Pos                   (31U)
+#define PSSI_CR_OUTEN_Msk                   (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
+#define PSSI_CR_OUTEN                       PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */
+
+/********************  Bit definition for PSSI_SR register  *******************/
+#define PSSI_SR_RTT4B_Pos                   (2U)
+#define PSSI_SR_RTT4B_Msk                   (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
+#define PSSI_SR_RTT4B                       PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
+#define PSSI_SR_RTT1B_Pos                   (3U)
+#define PSSI_SR_RTT1B_Msk                   (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
+#define PSSI_SR_RTT1B                       PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */
+
+/********************  Bit definition for PSSI_RIS register  *******************/
+#define PSSI_RIS_OVR_RIS_Pos                (1U)
+#define PSSI_RIS_OVR_RIS_Msk                (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define PSSI_RIS_OVR_RIS                    PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */
+
+/********************  Bit definition for PSSI_IER register  *******************/
+#define PSSI_IER_OVR_IE_Pos                 (1U)
+#define PSSI_IER_OVR_IE_Msk                 (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define PSSI_IER_OVR_IE                     PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */
+
+/********************  Bit definition for PSSI_MIS register  *******************/
+#define PSSI_MIS_OVR_MIS_Pos                (1U)
+#define PSSI_MIS_OVR_MIS_Msk                (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define PSSI_MIS_OVR_MIS                    PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */
+
+/********************  Bit definition for PSSI_ICR register  *******************/
+#define PSSI_ICR_OVR_ISC_Pos                (1U)
+#define PSSI_ICR_OVR_ISC_Msk                (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define PSSI_ICR_OVR_ISC                    PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */
+
+/********************  Bit definition for PSSI_DR register  *******************/
+#define PSSI_DR_DR_Pos                      (0U)
+#define PSSI_DR_DR_Msk                      (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
+#define PSSI_DR_DR                          PSSI_DR_DR_Msk                          /*!< Data register  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PWR_CR1 register  ********************/
+#define PWR_CR1_SDEN_Pos                (2U)
+#define PWR_CR1_SDEN_Msk                (0x1UL << PWR_CR1_SDEN_Pos)             /*!< 0x00000004 */
+#define PWR_CR1_SDEN                    PWR_CR1_SDEN_Msk                        /*!< SMPS step-down converter enable */
+#define PWR_CR1_MODE_PDN_Pos            (4U)
+#define PWR_CR1_MODE_PDN_Msk            (0x1UL << PWR_CR1_MODE_PDN_Pos)         /*!< 0x00000010 */
+#define PWR_CR1_MODE_PDN                PWR_CR1_MODE_PDN_Msk                    /*!< Pull down on output voltage during power down mode */
+#define PWR_CR1_LPDS08V_Pos             (5U)
+#define PWR_CR1_LPDS08V_Msk             (0x1UL << PWR_CR1_LPDS08V_Pos)          /*!< 0x00000020 */
+#define PWR_CR1_LPDS08V                 PWR_CR1_LPDS08V_Msk                     /*!< SMPS Low power mode enable (SVOS high only) */
+#define PWR_CR1_VDD18SMPSVMEN_Pos       (8U)
+#define PWR_CR1_VDD18SMPSVMEN_Msk       (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos)    /*!< 0x00000100 */
+#define PWR_CR1_VDD18SMPSVMEN           PWR_CR1_VDD18SMPSVMEN_Msk               /*!< VDD18SMPS voltage monitor enable */
+#define PWR_CR1_VDD18SMPSRDY_Pos        (15U)
+#define PWR_CR1_VDD18SMPSRDY_Msk        (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos)     /*!< 0x00008000 */
+#define PWR_CR1_VDD18SMPSRDY            PWR_CR1_VDD18SMPSRDY_Msk                /*!< VDD18SMPS ready */
+#define PWR_CR1_POPL_Pos                (16U)
+#define PWR_CR1_POPL_Msk                (0x1FUL << PWR_CR1_POPL_Pos)            /*!< 0x001F0000 */
+#define PWR_CR1_POPL                    PWR_CR1_POPL_Msk                        /*!< pwr_on pulse low configuration */
+#define PWR_CR1_POPL_0                  (0x1UL << PWR_CR1_POPL_Pos)             /*!< 0x00010000 */
+#define PWR_CR1_POPL_1                  (0x2UL << PWR_CR1_POPL_Pos)             /*!< 0x00020000 */
+#define PWR_CR1_POPL_2                  (0x4UL << PWR_CR1_POPL_Pos)             /*!< 0x00040000 */
+#define PWR_CR1_POPL_3                  (0x8UL << PWR_CR1_POPL_Pos)             /*!< 0x00080000 */
+#define PWR_CR1_POPL_4                  (0x10UL << PWR_CR1_POPL_Pos)            /*!< 0x00100000 */
+
+/*******************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_PVDEN_Pos               (0U)
+#define PWR_CR2_PVDEN_Msk               (0x1UL << PWR_CR2_PVDEN_Pos)            /*!< 0x00000001 */
+#define PWR_CR2_PVDEN                   PWR_CR2_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR2_PVDO_Pos                (8U)
+#define PWR_CR2_PVDO_Msk                (0x1UL << PWR_CR2_PVDO_Pos)             /*!< 0x00000100 */
+#define PWR_CR2_PVDO                    PWR_CR2_PVDO_Msk                        /*!< Programmable Voltage Detect Output */
+
+/*******************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_VCOREMONEN_Pos          (0U)
+#define PWR_CR3_VCOREMONEN_Msk          (0x1UL << PWR_CR3_VCOREMONEN_Pos)       /*!< 0x00000001 */
+#define PWR_CR3_VCOREMONEN              PWR_CR3_VCOREMONEN_Msk                  /*!< VDDCORE monitoring enable */
+#define PWR_CR3_VCORELLS_Pos            (4U)
+#define PWR_CR3_VCORELLS_Msk            (0x1UL << PWR_CR3_VCORELLS_Pos)         /*!< 0x00000010 */
+#define PWR_CR3_VCORELLS                PWR_CR3_VCORELLS_Msk                    /*!< VDDCORE Voltage Detector low level selection */
+#define PWR_CR3_VCOREL_Pos              (8U)
+#define PWR_CR3_VCOREL_Msk              (0x1UL << PWR_CR3_VCOREL_Pos)           /*!< 0x00000100 */
+#define PWR_CR3_VCOREL                  PWR_CR3_VCOREL_Msk                      /*!< Monitored VDDCORE level above low threshold */
+#define PWR_CR3_VCOREH_Pos              (9U)
+#define PWR_CR3_VCOREH_Msk              (0x1UL << PWR_CR3_VCOREH_Pos)           /*!< 0x00000200 */
+#define PWR_CR3_VCOREH                  PWR_CR3_VCOREH_Msk                      /*!< Monitored VDDCORE level above high threshold */
+
+/*******************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_TCMRBSEN_Pos            (0U)
+#define PWR_CR4_TCMRBSEN_Msk            (0x1UL << PWR_CR4_TCMRBSEN_Pos)         /*!< 0x00000001 */
+#define PWR_CR4_TCMRBSEN                PWR_CR4_TCMRBSEN_Msk                    /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */
+#define PWR_CR4_TCMFLXRBSEN_Pos         (4U)
+#define PWR_CR4_TCMFLXRBSEN_Msk         (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos)      /*!< 0x00000010 */
+#define PWR_CR4_TCMFLXRBSEN             PWR_CR4_TCMFLXRBSEN_Msk                 /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */
+
+/******************  Bit definition for PWR_VOSCR register  *******************/
+#define PWR_VOSCR_VOS_Pos               (0U)
+#define PWR_VOSCR_VOS_Msk               (0x1UL << PWR_VOSCR_VOS_Pos)            /*!< 0x00000001 */
+#define PWR_VOSCR_VOS                   PWR_VOSCR_VOS_Msk                       /*!< Voltage scaling selection according to performance */
+#define PWR_VOSCR_VOSRDY_Pos            (1U)
+#define PWR_VOSCR_VOSRDY_Msk            (0x1UL << PWR_VOSCR_VOSRDY_Pos)         /*!< 0x00000002 */
+#define PWR_VOSCR_VOSRDY                PWR_VOSCR_VOSRDY_Msk                    /*!< VOS Ready bit for VCORE voltage scaling output selection */
+#define PWR_VOSCR_ACTVOS_Pos            (16U)
+#define PWR_VOSCR_ACTVOS_Msk            (0x1UL << PWR_VOSCR_ACTVOS_Pos)         /*!< 0x00010000 */
+#define PWR_VOSCR_ACTVOS                PWR_VOSCR_ACTVOS_Msk                    /*!< VOS currently applied for VCORE voltage scaling selection */
+#define PWR_VOSCR_ACTVOSRDY_Pos         (17U)
+#define PWR_VOSCR_ACTVOSRDY_Msk         (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos)      /*!< 0x00020000 */
+#define PWR_VOSCR_ACTVOSRDY             PWR_VOSCR_ACTVOSRDY_Msk                 /*!< Voltage levels ready bit for currently used ACTVOS */
+
+/******************  Bit definition for PWR_BDCR1 register  *******************/
+#define PWR_BDCR1_MONEN_Pos             (0U)
+#define PWR_BDCR1_MONEN_Msk             (0x1UL << PWR_BDCR1_MONEN_Pos)          /*!< 0x00000001 */
+#define PWR_BDCR1_MONEN                 PWR_BDCR1_MONEN_Msk                     /*!< VBAT and temperature monitoring enable */
+#define PWR_BDCR1_VBATL_Pos             (16U)
+#define PWR_BDCR1_VBATL_Msk             (0x1UL << PWR_BDCR1_VBATL_Pos)          /*!< 0x00010000 */
+#define PWR_BDCR1_VBATL                 PWR_BDCR1_VBATL_Msk                     /*!< VBAT level monitoring versus low threshold */
+#define PWR_BDCR1_VBATH_Pos             (17U)
+#define PWR_BDCR1_VBATH_Msk             (0x1UL << PWR_BDCR1_VBATH_Pos)          /*!< 0x00020000 */
+#define PWR_BDCR1_VBATH                 PWR_BDCR1_VBATH_Msk                     /*!< VBAT level monitoring versus high threshold */
+#define PWR_BDCR1_TEMPL_Pos             (18U)
+#define PWR_BDCR1_TEMPL_Msk             (0x1UL << PWR_BDCR1_TEMPL_Pos)          /*!< 0x00040000 */
+#define PWR_BDCR1_TEMPL                 PWR_BDCR1_TEMPL_Msk                     /*!< Temperature level monitoring versus low threshold */
+#define PWR_BDCR1_TEMPH_Pos             (19U)
+#define PWR_BDCR1_TEMPH_Msk             (0x1UL << PWR_BDCR1_TEMPH_Pos)          /*!< 0x00080000 */
+#define PWR_BDCR1_TEMPH                 PWR_BDCR1_TEMPH_Msk                     /*!< Temperature level monitoring versus high threshold */
+
+/******************  Bit definition for PWR_BDCR2 register  *******************/
+#define PWR_BDCR2_BKPRBSEN_Pos          (0U)
+#define PWR_BDCR2_BKPRBSEN_Msk          (0x1UL << PWR_BDCR2_BKPRBSEN_Pos)       /*!< 0x00000001 */
+#define PWR_BDCR2_BKPRBSEN              PWR_BDCR2_BKPRBSEN_Msk                  /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */
+
+/******************  Bit definition for PWR_DBPCR register  *******************/
+#define PWR_DBPCR_DBP_Pos               (0U)
+#define PWR_DBPCR_DBP_Msk               (0x1UL << PWR_DBPCR_DBP_Pos)            /*!< 0x00000001 */
+#define PWR_DBPCR_DBP                   PWR_DBPCR_DBP_Msk                       /*!< Disable backup domain write protection */
+
+/******************  Bit definition for PWR_CPUCR register  *******************/
+#define PWR_CPUCR_PDDS_Pos              (0U)
+#define PWR_CPUCR_PDDS_Msk              (0x1UL << PWR_CPUCR_PDDS_Pos)           /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS                  PWR_CPUCR_PDDS_Msk                      /*!< Power Down Deepsleep selection */
+#define PWR_CPUCR_CSSF_Pos              (1U)
+#define PWR_CPUCR_CSSF_Msk              (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000002 */
+#define PWR_CPUCR_CSSF                  PWR_CPUCR_CSSF_Msk                      /*!< Clear Standby and Stop flags (always read as 0) */
+#define PWR_CPUCR_STOPF_Pos             (8U)
+#define PWR_CPUCR_STOPF_Msk             (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000100 */
+#define PWR_CPUCR_STOPF                 PWR_CPUCR_STOPF_Msk                     /*!< STOP flag */
+#define PWR_CPUCR_SBF_Pos               (9U)
+#define PWR_CPUCR_SBF_Msk               (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000200 */
+#define PWR_CPUCR_SBF                   PWR_CPUCR_SBF_Msk                       /*!< System Standby flag */
+#define PWR_CPUCR_SVOS_Pos              (16U)
+#define PWR_CPUCR_SVOS_Msk              (0x1UL << PWR_CPUCR_SVOS_Pos)           /*!< 0x00010000 */
+#define PWR_CPUCR_SVOS                  PWR_CPUCR_SVOS_Msk                      /*!< System Stop mode voltage scaling selection */
+
+/******************  Bit definition for PWR_SVMCR1 register  ******************/
+#define PWR_SVMCR1_VDDIO4VMEN_Pos       (0U)
+#define PWR_SVMCR1_VDDIO4VMEN_Msk       (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR1_VDDIO4VMEN           PWR_SVMCR1_VDDIO4VMEN_Msk               /*!< VDDOI4 Independent I/Os voltage monitor enable */
+#define PWR_SVMCR1_VDDIO4SV_Pos         (8U)
+#define PWR_SVMCR1_VDDIO4SV_Msk         (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR1_VDDIO4SV             PWR_SVMCR1_VDDIO4SV_Msk                 /*!< VDDIO4 Independent I/Os supply valid */
+#define PWR_SVMCR1_VDDIO4RDY_Pos        (16U)
+#define PWR_SVMCR1_VDDIO4RDY_Msk        (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR1_VDDIO4RDY            PWR_SVMCR1_VDDIO4RDY_Msk                /*!< VDDIO4 ready */
+#define PWR_SVMCR1_VDDIO4VRSEL_Pos      (24U)
+#define PWR_SVMCR1_VDDIO4VRSEL_Msk      (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR1_VDDIO4VRSEL          PWR_SVMCR1_VDDIO4VRSEL_Msk              /*!< VDDIO4 IO voltage range selection */
+#define PWR_SVMCR1_VDDIO4VRSTBY_Pos     (25U)
+#define PWR_SVMCR1_VDDIO4VRSTBY_Msk     (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos)  /*!< 0x04000000 */
+#define PWR_SVMCR1_VDDIO4VRSTBY         PWR_SVMCR1_VDDIO4VRSTBY_Msk             /*!< VDDIO4 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR2 register  ******************/
+#define PWR_SVMCR2_VDDIO5VMEN_Pos       (0U)
+#define PWR_SVMCR2_VDDIO5VMEN_Msk       (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR2_VDDIO5VMEN           PWR_SVMCR2_VDDIO5VMEN_Msk               /*!< VDDIO5 Independent voltage monitor enable */
+#define PWR_SVMCR2_VDDIO5SV_Pos         (8U)
+#define PWR_SVMCR2_VDDIO5SV_Msk         (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR2_VDDIO5SV             PWR_SVMCR2_VDDIO5SV_Msk                 /*!< VDDIO5 Independent supply valid */
+#define PWR_SVMCR2_VDDIO5RDY_Pos        (16U)
+#define PWR_SVMCR2_VDDIO5RDY_Msk        (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR2_VDDIO5RDY            PWR_SVMCR2_VDDIO5RDY_Msk                /*!< VDDIO5 ready */
+#define PWR_SVMCR2_VDDIO5VRSEL_Pos      (24U)
+#define PWR_SVMCR2_VDDIO5VRSEL_Msk      (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR2_VDDIO5VRSEL          PWR_SVMCR2_VDDIO5VRSEL_Msk              /*!< VDDIO5 IO voltage range selection */
+#define PWR_SVMCR2_VDDIO5VRSTBY_Pos     (25U)
+#define PWR_SVMCR2_VDDIO5VRSTBY_Msk     (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos)  /*!< 0x02000000 */
+#define PWR_SVMCR2_VDDIO5VRSTBY         PWR_SVMCR2_VDDIO5VRSTBY_Msk             /*!< VDDIO5 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR3 register  ******************/
+#define PWR_SVMCR3_VDDIO2VMEN_Pos       (0U)
+#define PWR_SVMCR3_VDDIO2VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR3_VDDIO2VMEN           PWR_SVMCR3_VDDIO2VMEN_Msk               /*!< VDDIO2 Independent voltage monitor enable */
+#define PWR_SVMCR3_VDDIO3VMEN_Pos       (1U)
+#define PWR_SVMCR3_VDDIO3VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos)    /*!< 0x00000002 */
+#define PWR_SVMCR3_VDDIO3VMEN           PWR_SVMCR3_VDDIO3VMEN_Msk               /*!< VDDIO3 Independent voltage monitor enable */
+#define PWR_SVMCR3_USB33VMEN_Pos        (2U)
+#define PWR_SVMCR3_USB33VMEN_Msk        (0x1UL << PWR_SVMCR3_USB33VMEN_Pos)     /*!< 0x00000004 */
+#define PWR_SVMCR3_USB33VMEN            PWR_SVMCR3_USB33VMEN_Msk                /*!< VDD33USB Independent USB 33 voltage monitor enable */
+#define PWR_SVMCR3_AVMEN_Pos            (4U)
+#define PWR_SVMCR3_AVMEN_Msk            (0x1UL << PWR_SVMCR3_AVMEN_Pos)         /*!< 0x00000010 */
+#define PWR_SVMCR3_AVMEN                PWR_SVMCR3_AVMEN_Msk                    /*!< VDDA18ADC Independent ADC voltage monitor enable */
+#define PWR_SVMCR3_VDDIO2SV_Pos         (8U)
+#define PWR_SVMCR3_VDDIO2SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR3_VDDIO2SV             PWR_SVMCR3_VDDIO2SV_Msk                 /*!< VDDIO2 Independent supply valid */
+#define PWR_SVMCR3_VDDIO3SV_Pos         (9U)
+#define PWR_SVMCR3_VDDIO3SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos)      /*!< 0x00000200 */
+#define PWR_SVMCR3_VDDIO3SV             PWR_SVMCR3_VDDIO3SV_Msk                 /*!< VDDIO3 Independent supply valid */
+#define PWR_SVMCR3_USB33SV_Pos          (10U)
+#define PWR_SVMCR3_USB33SV_Msk          (0x1UL << PWR_SVMCR3_USB33SV_Pos)       /*!< 0x00000400 */
+#define PWR_SVMCR3_USB33SV              PWR_SVMCR3_USB33SV_Msk                  /*!< VDD33USB Independent supply valid */
+#define PWR_SVMCR3_ASV_Pos              (12U)
+#define PWR_SVMCR3_ASV_Msk              (0x1UL << PWR_SVMCR3_ASV_Pos)           /*!< 0x00001000 */
+#define PWR_SVMCR3_ASV                  PWR_SVMCR3_ASV_Msk                      /*!< VDDA18ADC Independent supply valid */
+#define PWR_SVMCR3_VDDIO2RDY_Pos        (16U)
+#define PWR_SVMCR3_VDDIO2RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR3_VDDIO2RDY            PWR_SVMCR3_VDDIO2RDY_Msk                /*!< VDDIO2 ready */
+#define PWR_SVMCR3_VDDIO3RDY_Pos        (17U)
+#define PWR_SVMCR3_VDDIO3RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos)     /*!< 0x00020000 */
+#define PWR_SVMCR3_VDDIO3RDY            PWR_SVMCR3_VDDIO3RDY_Msk                /*!< VDDIO3 ready */
+#define PWR_SVMCR3_USB33RDY_Pos         (18U)
+#define PWR_SVMCR3_USB33RDY_Msk         (0x1UL << PWR_SVMCR3_USB33RDY_Pos)      /*!< 0x00040000 */
+#define PWR_SVMCR3_USB33RDY             PWR_SVMCR3_USB33RDY_Msk                 /*!< VDD33USB ready */
+#define PWR_SVMCR3_ARDY_Pos             (20U)
+#define PWR_SVMCR3_ARDY_Msk             (0x1UL << PWR_SVMCR3_ARDY_Pos)          /*!< 0x00100000 */
+#define PWR_SVMCR3_ARDY                 PWR_SVMCR3_ARDY_Msk                     /*!< VDDA18ADC ready */
+#define PWR_SVMCR3_VDDIOVRSEL_Pos       (24U)
+#define PWR_SVMCR3_VDDIOVRSEL_Msk       (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos)    /*!< 0x01000000 */
+#define PWR_SVMCR3_VDDIOVRSEL           PWR_SVMCR3_VDDIOVRSEL_Msk               /*!< VDD IO voltage range selection */
+#define PWR_SVMCR3_VDDIO2VRSEL_Pos      (25U)
+#define PWR_SVMCR3_VDDIO2VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos)   /*!< 0x02000000 */
+#define PWR_SVMCR3_VDDIO2VRSEL          PWR_SVMCR3_VDDIO2VRSEL_Msk              /*!< VDDIO2 IO voltage range selection */
+#define PWR_SVMCR3_VDDIO3VRSEL_Pos      (26U)
+#define PWR_SVMCR3_VDDIO3VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos)   /*!< 0x04000000 */
+#define PWR_SVMCR3_VDDIO3VRSEL          PWR_SVMCR3_VDDIO3VRSEL_Msk              /*!< VDDIO3 IO voltage range selection */
+
+/*****************  Bit definition for PWR_WKUPCR register  *******************/
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                    /*!< Clear Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                    /*!< Clear Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                    /*!< Clear Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                    /*!< Clear Wakeup Flag for WKUP4 pin */
+#define PWR_WKUPCR_WKUPC_Pos           (0U)
+#define PWR_WKUPCR_WKUPC_Msk           (0xFUL << PWR_WKUPCR_WKUPC_Pos)         /*!< 0x0000000F */
+#define PWR_WKUPCR_WKUPC               PWR_WKUPCR_WKUPC_Msk                    /*!< Clear Wakeup Flag 1 to 4 */
+
+/*****************  Bit definition for PWR_WKUPSR register  *******************/
+#define PWR_WKUPSR_WKUPF1_Pos          (0U)
+#define PWR_WKUPSR_WKUPF1_Msk          (0x1UL << PWR_WKUPSR_WKUPF1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPSR_WKUPF1              PWR_WKUPSR_WKUPF1_Msk                    /*!< Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPSR_WKUPF2_Pos          (1U)
+#define PWR_WKUPSR_WKUPF2_Msk          (0x1UL << PWR_WKUPSR_WKUPF2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPSR_WKUPF2              PWR_WKUPSR_WKUPF2_Msk                    /*!< Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPSR_WKUPF3_Pos          (2U)
+#define PWR_WKUPSR_WKUPF3_Msk          (0x1UL << PWR_WKUPSR_WKUPF3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPSR_WKUPF3              PWR_WKUPSR_WKUPF3_Msk                    /*!< Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPSR_WKUPF4_Pos          (3U)
+#define PWR_WKUPSR_WKUPF4_Msk          (0x1UL << PWR_WKUPSR_WKUPF4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPSR_WKUPF4              PWR_WKUPSR_WKUPF4_Msk                    /*!< Wakeup Flag for WKUP4 pin */
+
+/*****************  Bit definition for PWR_WKUPEPR register  *******************/
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)       /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                  /*!< Enable Wakeup pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)       /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                  /*!< Enable Wakeup pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)       /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                  /*!< Enable Wakeup pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)       /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                  /*!< Enable Wakeup pin WKUP4 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)        /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                   /*!< Wakeup Polarity bit for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)        /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                   /*!< Wakeup Polarity bit for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)        /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                   /*!< Wakeup Polarity bit for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)        /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                   /*!< Wakeup Polarity bit for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPP_Pos          (8U)
+#define PWR_WKUPEPR_WKUPP_Msk          (0x0FUL << PWR_WKUPEPR_WKUPP_Pos)        /*!< 0x0000300F */
+#define PWR_WKUPEPR_WKUPP              PWR_WKUPEPR_WKUPP_Msk                    /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk                /*!< Wakeup pull configuration for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk                /*!< Wakeup pull configuration for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk                /*!< Wakeup pull configuration for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk                /*!< Wakeup pull configuration for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos)       /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                   /*!< Enable all Wakeup Pin */
+
+/*****************  Bit definition for PWR_SECCFGR register  ******************/
+#define PWR_SECCFGR_SEC0_Pos            (0U)
+#define PWR_SECCFGR_SEC0_Msk            (0x1UL << PWR_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
+#define PWR_SECCFGR_SEC0                PWR_SECCFGR_SEC0_Msk                    /*!< System supply configuration secure protection */
+#define PWR_SECCFGR_SEC1_Pos            (1U)
+#define PWR_SECCFGR_SEC1_Msk            (0x1UL << PWR_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
+#define PWR_SECCFGR_SEC1                PWR_SECCFGR_SEC1_Msk                    /*!< Programmable voltage detector secure protection */
+#define PWR_SECCFGR_SEC2_Pos            (2U)
+#define PWR_SECCFGR_SEC2_Msk            (0x1UL << PWR_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
+#define PWR_SECCFGR_SEC2                PWR_SECCFGR_SEC2_Msk                    /*!< VDDCORE monitor secure protection */
+#define PWR_SECCFGR_SEC3_Pos            (3U)
+#define PWR_SECCFGR_SEC3_Msk            (0x1UL << PWR_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
+#define PWR_SECCFGR_SEC3                PWR_SECCFGR_SEC3_Msk                    /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */
+#define PWR_SECCFGR_SEC4_Pos            (4U)
+#define PWR_SECCFGR_SEC4_Msk            (0x1UL << PWR_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
+#define PWR_SECCFGR_SEC4                PWR_SECCFGR_SEC4_Msk                    /*!< Voltage scaling selection secure protection */
+#define PWR_SECCFGR_SEC5_Pos            (5U)
+#define PWR_SECCFGR_SEC5_Msk            (0x1UL << PWR_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
+#define PWR_SECCFGR_SEC5                PWR_SECCFGR_SEC5_Msk                    /*!< Backup domain secure protection */
+#define PWR_SECCFGR_SEC6_Pos            (6U)
+#define PWR_SECCFGR_SEC6_Msk            (0x1UL << PWR_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
+#define PWR_SECCFGR_SEC6                PWR_SECCFGR_SEC6_Msk                    /*!< CPU power control secure protection */
+#define PWR_SECCFGR_SEC7_Pos            (7U)
+#define PWR_SECCFGR_SEC7_Msk            (0x1UL << PWR_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
+#define PWR_SECCFGR_SEC7                PWR_SECCFGR_SEC7_Msk                    /*!< Peripheral voltage monitor secure protection */
+#define PWR_SECCFGR_WKUPSEC1_Pos        (16U)
+#define PWR_SECCFGR_WKUPSEC1_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos)     /*!< 0x00010000 */
+#define PWR_SECCFGR_WKUPSEC1            PWR_SECCFGR_WKUPSEC1_Msk                /*!< WKUP1 secure protection */
+#define PWR_SECCFGR_WKUPSEC2_Pos        (17U)
+#define PWR_SECCFGR_WKUPSEC2_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos)     /*!< 0x00020000 */
+#define PWR_SECCFGR_WKUPSEC2            PWR_SECCFGR_WKUPSEC2_Msk                /*!< WKUP2 secure protection */
+#define PWR_SECCFGR_WKUPSEC3_Pos        (18U)
+#define PWR_SECCFGR_WKUPSEC3_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos)     /*!< 0x00040000 */
+#define PWR_SECCFGR_WKUPSEC3            PWR_SECCFGR_WKUPSEC3_Msk                /*!< WKUP3 secure protection */
+#define PWR_SECCFGR_WKUPSEC4_Pos        (19U)
+#define PWR_SECCFGR_WKUPSEC4_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos)     /*!< 0x00080000 */
+#define PWR_SECCFGR_WKUPSEC4            PWR_SECCFGR_WKUPSEC4_Msk                /*!< WKUP4 secure protection */
+
+/*****************  Bit definition for PWR_PRIVCFGR register  *****************/
+#define PWR_PRIVCFGR_PRIV0_Pos          (0U)
+#define PWR_PRIVCFGR_PRIV0_Msk          (0x1UL << PWR_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define PWR_PRIVCFGR_PRIV0              PWR_PRIVCFGR_PRIV0_Msk                  /*!< System supply configuration privileged protection */
+#define PWR_PRIVCFGR_PRIV1_Pos          (1U)
+#define PWR_PRIVCFGR_PRIV1_Msk          (0x1UL << PWR_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define PWR_PRIVCFGR_PRIV1              PWR_PRIVCFGR_PRIV1_Msk                  /*!< Programmable voltage detector privileged protection */
+#define PWR_PRIVCFGR_PRIV2_Pos          (2U)
+#define PWR_PRIVCFGR_PRIV2_Msk          (0x1UL << PWR_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define PWR_PRIVCFGR_PRIV2              PWR_PRIVCFGR_PRIV2_Msk                  /*!< VDDCORE monitor privileged protection */
+#define PWR_PRIVCFGR_PRIV3_Pos          (3U)
+#define PWR_PRIVCFGR_PRIV3_Msk          (0x1UL << PWR_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define PWR_PRIVCFGR_PRIV3              PWR_PRIVCFGR_PRIV3_Msk                  /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */
+#define PWR_PRIVCFGR_PRIV4_Pos          (4U)
+#define PWR_PRIVCFGR_PRIV4_Msk          (0x1UL << PWR_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define PWR_PRIVCFGR_PRIV4              PWR_PRIVCFGR_PRIV4_Msk                  /*!< Voltage scaling selection privileged protection */
+#define PWR_PRIVCFGR_PRIV5_Pos          (5U)
+#define PWR_PRIVCFGR_PRIV5_Msk          (0x1UL << PWR_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define PWR_PRIVCFGR_PRIV5              PWR_PRIVCFGR_PRIV5_Msk                  /*!< Backup domain privileged protection */
+#define PWR_PRIVCFGR_PRIV6_Pos          (6U)
+#define PWR_PRIVCFGR_PRIV6_Msk          (0x1UL << PWR_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define PWR_PRIVCFGR_PRIV6              PWR_PRIVCFGR_PRIV6_Msk                  /*!< CPU power control privileged protection */
+#define PWR_PRIVCFGR_PRIV7_Pos          (7U)
+#define PWR_PRIVCFGR_PRIV7_Msk          (0x1UL << PWR_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define PWR_PRIVCFGR_PRIV7              PWR_PRIVCFGR_PRIV7_Msk                  /*!< Peripheral voltage monitor privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV1_Pos      (16U)
+#define PWR_PRIVCFGR_WKUPPRIV1_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos)   /*!< 0x00010000 */
+#define PWR_PRIVCFGR_WKUPPRIV1          PWR_PRIVCFGR_WKUPPRIV1_Msk              /*!< WKUP1 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV2_Pos      (17U)
+#define PWR_PRIVCFGR_WKUPPRIV2_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos)   /*!< 0x00020000 */
+#define PWR_PRIVCFGR_WKUPPRIV2          PWR_PRIVCFGR_WKUPPRIV2_Msk              /*!< WKUP2 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV3_Pos      (18U)
+#define PWR_PRIVCFGR_WKUPPRIV3_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos)   /*!< 0x00040000 */
+#define PWR_PRIVCFGR_WKUPPRIV3          PWR_PRIVCFGR_WKUPPRIV3_Msk              /*!< WKUP3 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV4_Pos      (19U)
+#define PWR_PRIVCFGR_WKUPPRIV4_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos)   /*!< 0x00080000 */
+#define PWR_PRIVCFGR_WKUPPRIV4          PWR_PRIVCFGR_WKUPPRIV4_Msk              /*!< WKUP4 privileged protection */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       RAMs configuration controller                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RAMCFG_CR register  ******************/
+#define RAMCFG_CR_ECCE_Pos              (0U)
+#define RAMCFG_CR_ECCE_Msk              (0x1UL << RAMCFG_CR_ECCE_Pos)          /*!< 0x00000001 */
+#define RAMCFG_CR_ECCE                  RAMCFG_CR_ECCE_Msk                     /*!< ECC Enable */
+#define RAMCFG_CR_ALE_Pos               (4U)
+#define RAMCFG_CR_ALE_Msk               (0x1UL << RAMCFG_CR_ALE_Pos)           /*!< 0x00000010 */
+#define RAMCFG_CR_ALE                   RAMCFG_CR_ALE_Msk                      /*!< Address Latching Enable */
+#define RAMCFG_CR_SRAMER_Pos            (8U)
+#define RAMCFG_CR_SRAMER_Msk            (0x1UL << RAMCFG_CR_SRAMER_Pos)        /*!< 0x00000100 */
+#define RAMCFG_CR_SRAMER                RAMCFG_CR_SRAMER_Msk                   /*!< Start Erase */
+#define RAMCFG_CR_SRAMHWERDIS_Pos       (12U)
+#define RAMCFG_CR_SRAMHWERDIS_Msk       (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos)   /*!< 0x00001000 */
+#define RAMCFG_CR_SRAMHWERDIS           RAMCFG_CR_SRAMHWERDIS_Msk              /*!< SRAM hardware erase disable */
+#define RAMCFG_CR_ITCMCFG_Pos           (16U)
+#define RAMCFG_CR_ITCMCFG_Msk           (0x3UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00030000 */
+#define RAMCFG_CR_ITCMCFG               RAMCFG_CR_ITCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+#define RAMCFG_CR_ITCMCFG_0             (0x1UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00010000 */
+#define RAMCFG_CR_ITCMCFG_1             (0x2UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00020000 */
+#define RAMCFG_CR_SRAMSD_Pos            (20U)
+#define RAMCFG_CR_SRAMSD_Msk            (0x1UL << RAMCFG_CR_SRAMSD_Pos)        /*!< 0x00100000 */
+#define RAMCFG_CR_SRAMSD                RAMCFG_CR_SRAMSD_Msk                   /*!< Shutdown AXISRAMx */
+#define RAMCFG_CR_DTCMCFG_Pos           (24U)
+#define RAMCFG_CR_DTCMCFG_Msk           (0x1UL << RAMCFG_CR_DTCMCFG_Pos)       /*!< 0x01000000 */
+#define RAMCFG_CR_DTCMCFG               RAMCFG_CR_DTCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+
+/*******************  Bit definition for RAMCFG_IER register  *****************/
+#define RAMCFG_IER_SEIE_Pos             (0U)
+#define RAMCFG_IER_SEIE_Msk             (0x1UL << RAMCFG_IER_SEIE_Pos)         /*!< 0x00000001 */
+#define RAMCFG_IER_SEIE                 RAMCFG_IER_SEIE_Msk                    /*!< Single Error Interrupt Enable */
+#define RAMCFG_IER_DEIE_Pos             (1U)
+#define RAMCFG_IER_DEIE_Msk             (0x1UL << RAMCFG_IER_DEIE_Pos)         /*!< 0x00000002 */
+#define RAMCFG_IER_DEIE                 RAMCFG_IER_DEIE_Msk                    /*!< Double Error Interrupt Enable */
+
+/*******************  Bit definition for RAMCFG_ISR register  *****************/
+#define RAMCFG_ISR_SEDC_Pos             (0U)
+#define RAMCFG_ISR_SEDC_Msk             (0x1UL << RAMCFG_ISR_SEDC_Pos)         /*!< 0x00000001 */
+#define RAMCFG_ISR_SEDC                 RAMCFG_ISR_SEDC_Msk                    /*!< Single Error Detected and Corrected flag */
+#define RAMCFG_ISR_DED_Pos              (1U)
+#define RAMCFG_ISR_DED_Msk              (0x1UL << RAMCFG_ISR_DED_Pos)          /*!< 0x00000002 */
+#define RAMCFG_ISR_DED                  RAMCFG_ISR_DED_Msk                     /*!< Double Error Detected flag */
+#define RAMCFG_ISR_SRAMBUSY_Pos         (8U)
+#define RAMCFG_ISR_SRAMBUSY_Msk         (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)     /*!< 0x00000100 */
+#define RAMCFG_ISR_SRAMBUSY             RAMCFG_ISR_SRAMBUSY_Msk                /*!< SRAM busy flag */
+
+/*******************  Bit definition for RAMCFG_ESEAR register  ****************/
+#define RAMCFG_ESEAR_ESEA_Pos           (0U)
+#define RAMCFG_ESEAR_ESEA_Msk           (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_ESEAR_ESEA               RAMCFG_ESEAR_ESEA_Msk                  /*!< ECC Single Error Address */
+
+/*******************  Bit definition for RAMCFG_EDEAR register  ****************/
+#define RAMCFG_EDEAR_EDEA_Pos           (0U)
+#define RAMCFG_EDEAR_EDEA_Msk           (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_EDEAR_EDEA               RAMCFG_EDEAR_EDEA_Msk                  /*!< ECC Double Error Address */
+
+/*******************  Bit definition for RAMCFG_ICR register  *****************/
+#define RAMCFG_ICR_CSEDC_Pos            (0U)
+#define RAMCFG_ICR_CSEDC_Msk            (0x1UL << RAMCFG_ICR_CSEDC_Pos)        /*!< 0x00000001 */
+#define RAMCFG_ICR_CSEDC                RAMCFG_ICR_CSEDC_Msk                   /*!< Clear ECC Single Error Detected and Corrected Flag */
+#define RAMCFG_ICR_CDED_Pos             (1U)
+#define RAMCFG_ICR_CDED_Msk             (0x1UL << RAMCFG_ICR_CDED_Pos)         /*!< 0x00000002 */
+#define RAMCFG_ICR_CDED                 RAMCFG_ICR_CDED_Msk                    /*!< Clear ECC Double Error Detected Flag*/
+
+/*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
+#define RAMCFG_ECCKEYR_ECCKEY_Pos       (0U)
+#define RAMCFG_ECCKEYR_ECCKEY_Msk       (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)  /*!< 0x000000FF */
+#define RAMCFG_ECCKEYR_ECCKEY           RAMCFG_ECCKEYR_ECCKEY_Msk              /*!< ECC Write Protection Key */
+
+/*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
+#define RAMCFG_ERKEYR_ERASEKEY_Pos      (0U)
+#define RAMCFG_ERKEYR_ERASEKEY_Msk      (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */
+#define RAMCFG_ERKEYR_ERASEKEY          RAMCFG_ERKEYR_ERASEKEY_Msk             /*!< Erase Write Protection Key */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (RCC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_LSION_Pos                        (0U)
+#define RCC_CR_LSION_Msk                        (0x1UL << RCC_CR_LSION_Pos)           /*!< 0x00000001 */
+#define RCC_CR_LSION                            RCC_CR_LSION_Msk                     /*!< LSI oscillator enable */
+#define RCC_CR_LSEON_Pos                        (1U)
+#define RCC_CR_LSEON_Msk                        (0x1UL << RCC_CR_LSEON_Pos)           /*!< 0x00000002 */
+#define RCC_CR_LSEON                            RCC_CR_LSEON_Msk                     /*!< LSE oscillator enable */
+#define RCC_CR_MSION_Pos                        (2U)
+#define RCC_CR_MSION_Msk                        (0x1UL << RCC_CR_MSION_Pos)           /*!< 0x00000004 */
+#define RCC_CR_MSION                            RCC_CR_MSION_Msk                     /*!< MSI oscillator enable */
+#define RCC_CR_HSION_Pos                        (3U)
+#define RCC_CR_HSION_Msk                        (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000008 */
+#define RCC_CR_HSION                            RCC_CR_HSION_Msk                     /*!< HSI oscillator enable */
+#define RCC_CR_HSEON_Pos                        (4U)
+#define RCC_CR_HSEON_Msk                        (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00000010 */
+#define RCC_CR_HSEON                            RCC_CR_HSEON_Msk                     /*!< HSE oscillator enable */
+#define RCC_CR_PLL1ON_Pos                       (8U)
+#define RCC_CR_PLL1ON_Msk                       (0x1UL << RCC_CR_PLL1ON_Pos)          /*!< 0x00000100 */
+#define RCC_CR_PLL1ON                           RCC_CR_PLL1ON_Msk                    /*!< PLL1 enable */
+#define RCC_CR_PLL2ON_Pos                       (9U)
+#define RCC_CR_PLL2ON_Msk                       (0x1UL << RCC_CR_PLL2ON_Pos)          /*!< 0x00000200 */
+#define RCC_CR_PLL2ON                           RCC_CR_PLL2ON_Msk                    /*!< PLL2 enable */
+#define RCC_CR_PLL3ON_Pos                       (10U)
+#define RCC_CR_PLL3ON_Msk                       (0x1UL << RCC_CR_PLL3ON_Pos)          /*!< 0x00000400 */
+#define RCC_CR_PLL3ON                           RCC_CR_PLL3ON_Msk                    /*!< PLL3 enable */
+#define RCC_CR_PLL4ON_Pos                       (11U)
+#define RCC_CR_PLL4ON_Msk                       (0x1UL << RCC_CR_PLL4ON_Pos)          /*!< 0x00000800 */
+#define RCC_CR_PLL4ON                           RCC_CR_PLL4ON_Msk                    /*!< PLL4 enable */
+
+/********************  Bit definition for RCC_SR register  ********************/
+#define RCC_SR_LSIRDY_Pos                       (0U)
+#define RCC_SR_LSIRDY_Msk                       (0x1UL << RCC_SR_LSIRDY_Pos)          /*!< 0x00000001 */
+#define RCC_SR_LSIRDY                           RCC_SR_LSIRDY_Msk                    /*!< LSI clock ready flag */
+#define RCC_SR_LSERDY_Pos                       (1U)
+#define RCC_SR_LSERDY_Msk                       (0x1UL << RCC_SR_LSERDY_Pos)          /*!< 0x00000002 */
+#define RCC_SR_LSERDY                           RCC_SR_LSERDY_Msk                    /*!< LSE clock ready flag */
+#define RCC_SR_MSIRDY_Pos                       (2U)
+#define RCC_SR_MSIRDY_Msk                       (0x1UL << RCC_SR_MSIRDY_Pos)          /*!< 0x00000004 */
+#define RCC_SR_MSIRDY                           RCC_SR_MSIRDY_Msk                    /*!< MSI clock ready flag */
+#define RCC_SR_HSIRDY_Pos                       (3U)
+#define RCC_SR_HSIRDY_Msk                       (0x1UL << RCC_SR_HSIRDY_Pos)          /*!< 0x00000008 */
+#define RCC_SR_HSIRDY                           RCC_SR_HSIRDY_Msk                    /*!< HSI clock ready flag */
+#define RCC_SR_HSERDY_Pos                       (4U)
+#define RCC_SR_HSERDY_Msk                       (0x1UL << RCC_SR_HSERDY_Pos)          /*!< 0x00000010 */
+#define RCC_SR_HSERDY                           RCC_SR_HSERDY_Msk                    /*!< HSE clock ready flag */
+#define RCC_SR_PLL1RDY_Pos                      (8U)
+#define RCC_SR_PLL1RDY_Msk                      (0x1UL << RCC_SR_PLL1RDY_Pos)         /*!< 0x00000100 */
+#define RCC_SR_PLL1RDY                          RCC_SR_PLL1RDY_Msk                   /*!< PLL1 clock ready flag */
+#define RCC_SR_PLL2RDY_Pos                      (9U)
+#define RCC_SR_PLL2RDY_Msk                      (0x1UL << RCC_SR_PLL2RDY_Pos)         /*!< 0x00000200 */
+#define RCC_SR_PLL2RDY                          RCC_SR_PLL2RDY_Msk                   /*!< PLL2 clock ready flag */
+#define RCC_SR_PLL3RDY_Pos                      (10U)
+#define RCC_SR_PLL3RDY_Msk                      (0x1UL << RCC_SR_PLL3RDY_Pos)         /*!< 0x00000400 */
+#define RCC_SR_PLL3RDY                          RCC_SR_PLL3RDY_Msk                   /*!< PLL3 clock ready flag */
+#define RCC_SR_PLL4RDY_Pos                      (11U)
+#define RCC_SR_PLL4RDY_Msk                      (0x1UL << RCC_SR_PLL4RDY_Pos)         /*!< 0x00000800 */
+#define RCC_SR_PLL4RDY                          RCC_SR_PLL4RDY_Msk                   /*!< PLL4 clock ready flag */
+
+/******************  Bit definition for RCC_STOPCR register  ******************/
+#define RCC_STOPCR_MSISTOPEN_Pos                (0U)
+#define RCC_STOPCR_MSISTOPEN_Msk                (0x1UL << RCC_STOPCR_MSISTOPEN_Pos)   /*!< 0x00000001 */
+#define RCC_STOPCR_MSISTOPEN                    RCC_STOPCR_MSISTOPEN_Msk             /*!< MSI oscillator enable */
+#define RCC_STOPCR_HSISTOPEN_Pos                (1U)
+#define RCC_STOPCR_HSISTOPEN_Msk                (0x1UL << RCC_STOPCR_HSISTOPEN_Pos)   /*!< 0x00000002 */
+#define RCC_STOPCR_HSISTOPEN                    RCC_STOPCR_HSISTOPEN_Msk             /*!< HSI oscillator enable */
+
+/******************  Bit definition for RCC_CFGR1 register  *******************/
+#define RCC_CFGR1_STOPWUCK_Pos                  (0U)
+#define RCC_CFGR1_STOPWUCK_Msk                  (0x1UL << RCC_CFGR1_STOPWUCK_Pos)     /*!< 0x00000001 */
+#define RCC_CFGR1_STOPWUCK                      RCC_CFGR1_STOPWUCK_Msk               /*!< System clock selection after a wake up from system stop */
+#define RCC_CFGR1_CPUSW_Pos                     (16U)
+#define RCC_CFGR1_CPUSW_Msk                     (0x3UL << RCC_CFGR1_CPUSW_Pos)        /*!< 0x00030000 */
+#define RCC_CFGR1_CPUSW                         RCC_CFGR1_CPUSW_Msk                  /*!< CPU clock switch selection */
+#define RCC_CFGR1_CPUSW_0                       (0x1UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR1_CPUSW_1                       (0x2UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR1_CPUSWS_Pos                    (20U)
+#define RCC_CFGR1_CPUSWS_Msk                    (0x3UL << RCC_CFGR1_CPUSWS_Pos)       /*!< 0x00300000 */
+#define RCC_CFGR1_CPUSWS                        RCC_CFGR1_CPUSWS_Msk                 /*!< CPU clock switch status */
+#define RCC_CFGR1_CPUSWS_0                      (0x1UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00100000 */
+#define RCC_CFGR1_CPUSWS_1                      (0x2UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00200000 */
+#define RCC_CFGR1_SYSSW_Pos                     (24U)
+#define RCC_CFGR1_SYSSW_Msk                     (0x3UL << RCC_CFGR1_SYSSW_Pos)        /*!< 0x03000000 */
+#define RCC_CFGR1_SYSSW                         RCC_CFGR1_SYSSW_Msk                  /*!< System clock switch selection */
+#define RCC_CFGR1_SYSSW_0                       (0x1UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x01000000 */
+#define RCC_CFGR1_SYSSW_1                       (0x2UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x02000000 */
+#define RCC_CFGR1_SYSSWS_Pos                    (28U)
+#define RCC_CFGR1_SYSSWS_Msk                    (0x3UL << RCC_CFGR1_SYSSWS_Pos)       /*!< 0x30000000 */
+#define RCC_CFGR1_SYSSWS                        RCC_CFGR1_SYSSWS_Msk                 /*!< System clock switch status */
+#define RCC_CFGR1_SYSSWS_0                      (0x1UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR1_SYSSWS_1                      (0x2UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x20000000 */
+
+/******************  Bit definition for RCC_CFGR2 register  *******************/
+#define RCC_CFGR2_PPRE1_Pos                     (0U)
+#define RCC_CFGR2_PPRE1_Msk                     (0x7UL << RCC_CFGR2_PPRE1_Pos)        /*!< 0x00000007 */
+#define RCC_CFGR2_PPRE1                         RCC_CFGR2_PPRE1_Msk                  /*!< CPU domain APB1 prescaler */
+#define RCC_CFGR2_PPRE1_0                       (0x1UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000001 */
+#define RCC_CFGR2_PPRE1_1                       (0x2UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000002 */
+#define RCC_CFGR2_PPRE1_2                       (0x4UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000004 */
+#define RCC_CFGR2_PPRE2_Pos                     (4U)
+#define RCC_CFGR2_PPRE2_Msk                     (0x7UL << RCC_CFGR2_PPRE2_Pos)        /*!< 0x00000070 */
+#define RCC_CFGR2_PPRE2                         RCC_CFGR2_PPRE2_Msk                  /*!< CPU domain APB2 prescaler */
+#define RCC_CFGR2_PPRE2_0                       (0x1UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR2_PPRE2_1                       (0x2UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR2_PPRE2_2                       (0x4UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR2_PPRE4_Pos                     (12U)
+#define RCC_CFGR2_PPRE4_Msk                     (0x7UL << RCC_CFGR2_PPRE4_Pos)        /*!< 0x00007000 */
+#define RCC_CFGR2_PPRE4                         RCC_CFGR2_PPRE4_Msk                  /*!< CPU domain APB4 prescaler */
+#define RCC_CFGR2_PPRE4_0                       (0x1UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR2_PPRE4_1                       (0x2UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00002000 */
+#define RCC_CFGR2_PPRE4_2                       (0x4UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00004000 */
+#define RCC_CFGR2_PPRE5_Pos                     (16U)
+#define RCC_CFGR2_PPRE5_Msk                     (0x7UL << RCC_CFGR2_PPRE5_Pos)        /*!< 0x00070000 */
+#define RCC_CFGR2_PPRE5                         RCC_CFGR2_PPRE5_Msk                  /*!< CPU domain APB5 prescaler */
+#define RCC_CFGR2_PPRE5_0                       (0x1UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR2_PPRE5_1                       (0x2UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR2_PPRE5_2                       (0x4UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00040000 */
+#define RCC_CFGR2_HPRE_Pos                      (20U)
+#define RCC_CFGR2_HPRE_Msk                      (0x7UL << RCC_CFGR2_HPRE_Pos)         /*!< 0x00700000 */
+#define RCC_CFGR2_HPRE                          RCC_CFGR2_HPRE_Msk                   /*!< AHB clock prescaler */
+#define RCC_CFGR2_HPRE_0                        (0x1UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00100000 */
+#define RCC_CFGR2_HPRE_1                        (0x2UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00200000 */
+#define RCC_CFGR2_HPRE_2                        (0x4UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00400000 */
+#define RCC_CFGR2_TIMPRE_Pos                    (24U)
+#define RCC_CFGR2_TIMPRE_Msk                    (0x3UL << RCC_CFGR2_TIMPRE_Pos)       /*!< 0x03000000 */
+#define RCC_CFGR2_TIMPRE                        RCC_CFGR2_TIMPRE_Msk                 /*!< Timer clock prescaler selection */
+#define RCC_CFGR2_TIMPRE_0                      (0x1UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR2_TIMPRE_1                      (0x2UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x02000000 */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define RCC_BDCR_VSWRST_Pos                     (31U)
+#define RCC_BDCR_VSWRST_Msk                     (0x1UL << RCC_BDCR_VSWRST_Pos)       /*!< 0x80000000 */
+#define RCC_BDCR_VSWRST                         RCC_BDCR_VSWRST_Msk                  /*!< Vswitch (VSW) domain software reset */
+
+/******************  Bit definition for RCC_HWRSR register  *******************/
+#define RCC_HWRSR_RMVF_Pos                      (16U)
+#define RCC_HWRSR_RMVF_Msk                      (0x1UL << RCC_HWRSR_RMVF_Pos)         /*!< 0x00010000 */
+#define RCC_HWRSR_RMVF                          RCC_HWRSR_RMVF_Msk                   /*!< Remove reset flag */
+#define RCC_HWRSR_LCKRSTF_Pos                   (17U)
+#define RCC_HWRSR_LCKRSTF_Msk                   (0x1UL << RCC_HWRSR_LCKRSTF_Pos)      /*!< 0x00020000 */
+#define RCC_HWRSR_LCKRSTF                       RCC_HWRSR_LCKRSTF_Msk                /*!< CPU lockup reset flag */
+#define RCC_HWRSR_BORRSTF_Pos                   (21U)
+#define RCC_HWRSR_BORRSTF_Msk                   (0x1UL << RCC_HWRSR_BORRSTF_Pos)      /*!< 0x00200000 */
+#define RCC_HWRSR_BORRSTF                       RCC_HWRSR_BORRSTF_Msk                /*!< BOR reset flag */
+#define RCC_HWRSR_PINRSTF_Pos                   (22U)
+#define RCC_HWRSR_PINRSTF_Msk                   (0x1UL << RCC_HWRSR_PINRSTF_Pos)      /*!< 0x00400000 */
+#define RCC_HWRSR_PINRSTF                       RCC_HWRSR_PINRSTF_Msk                /*!< Pin reset flag (NRST)  */
+#define RCC_HWRSR_PORRSTF_Pos                   (23U)
+#define RCC_HWRSR_PORRSTF_Msk                   (0x1UL << RCC_HWRSR_PORRSTF_Pos)      /*!< 0x00800000 */
+#define RCC_HWRSR_PORRSTF                       RCC_HWRSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
+#define RCC_HWRSR_SFTRSTF_Pos                   (24U)
+#define RCC_HWRSR_SFTRSTF_Msk                   (0x1UL << RCC_HWRSR_SFTRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_HWRSR_SFTRSTF                       RCC_HWRSR_SFTRSTF_Msk                /*!< Software system reset flag  */
+#define RCC_HWRSR_IWDGRSTF_Pos                  (26U)
+#define RCC_HWRSR_IWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_IWDGRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_HWRSR_IWDGRSTF                      RCC_HWRSR_IWDGRSTF_Msk               /*!< Independent watchdog reset flag */
+#define RCC_HWRSR_WWDGRSTF_Pos                  (28U)
+#define RCC_HWRSR_WWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_WWDGRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_HWRSR_WWDGRSTF                      RCC_HWRSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
+#define RCC_HWRSR_LPWRRSTF_Pos                  (30U)
+#define RCC_HWRSR_LPWRRSTF_Msk                  (0x1UL << RCC_HWRSR_LPWRRSTF_Pos)     /*!< 0x40000000 */
+#define RCC_HWRSR_LPWRRSTF                      RCC_HWRSR_LPWRRSTF_Msk               /*!< Illegal Stop or Standby flag */
+
+/*******************  Bit definition for RCC_RSR register  ********************/
+#define RCC_RSR_RMVF_Pos                        (16U)
+#define RCC_RSR_RMVF_Msk                        (0x1UL << RCC_RSR_RMVF_Pos)           /*!< 0x00010000 */
+#define RCC_RSR_RMVF                            RCC_RSR_RMVF_Msk                     /*!< Remove reset flag */
+#define RCC_RSR_LCKRSTF_Pos                     (17U)
+#define RCC_RSR_LCKRSTF_Msk                     (0x1UL << RCC_RSR_LCKRSTF_Pos)        /*!< 0x00020000 */
+#define RCC_RSR_LCKRSTF                         RCC_RSR_LCKRSTF_Msk                  /*!< CPU lockup reset flag */
+#define RCC_RSR_BORRSTF_Pos                     (21U)
+#define RCC_RSR_BORRSTF_Msk                     (0x1UL << RCC_RSR_BORRSTF_Pos)        /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                         RCC_RSR_BORRSTF_Msk                  /*!< BOR reset flag */
+#define RCC_RSR_PINRSTF_Pos                     (22U)
+#define RCC_RSR_PINRSTF_Msk                     (0x1UL << RCC_RSR_PINRSTF_Pos)        /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                         RCC_RSR_PINRSTF_Msk                  /*!< Pin reset flag (NRST)  */
+#define RCC_RSR_PORRSTF_Pos                     (23U)
+#define RCC_RSR_PORRSTF_Msk                     (0x1UL << RCC_RSR_PORRSTF_Pos)        /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                         RCC_RSR_PORRSTF_Msk                  /*!< POR/PDR reset flag */
+#define RCC_RSR_SFTRSTF_Pos                     (24U)
+#define RCC_RSR_SFTRSTF_Msk                     (0x1UL << RCC_RSR_SFTRSTF_Pos)        /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                         RCC_RSR_SFTRSTF_Msk                  /*!< Software system reset flag  */
+#define RCC_RSR_IWDGRSTF_Pos                    (26U)
+#define RCC_RSR_IWDGRSTF_Msk                    (0x1UL << RCC_RSR_IWDGRSTF_Pos)       /*!< 0x04000000 */
+#define RCC_RSR_IWDGRSTF                        RCC_RSR_IWDGRSTF_Msk                 /*!< Independent watchdog reset flag */
+#define RCC_RSR_WWDGRSTF_Pos                    (28U)
+#define RCC_RSR_WWDGRSTF_Msk                    (0x1UL << RCC_RSR_WWDGRSTF_Pos)       /*!< 0x10000000 */
+#define RCC_RSR_WWDGRSTF                        RCC_RSR_WWDGRSTF_Msk                 /*!< Window watchdog reset flag */
+#define RCC_RSR_LPWRRSTF_Pos                    (30U)
+#define RCC_RSR_LPWRRSTF_Msk                    (0x1UL << RCC_RSR_LPWRRSTF_Pos)       /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                        RCC_RSR_LPWRRSTF_Msk                 /*!< Illegal Stop or Standby flag */
+
+/*****************  Bit definition for RCC_LSECFGR register  ******************/
+#define RCC_LSECFGR_LSECSSON_Pos                (7U)
+#define RCC_LSECFGR_LSECSSON_Msk                (0x1UL << RCC_LSECFGR_LSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_LSECFGR_LSECSSON                    RCC_LSECFGR_LSECSSON_Msk             /*!< LSE clock security system (CSS) enable */
+#define RCC_LSECFGR_LSECSSRA_Pos                (8U)
+#define RCC_LSECFGR_LSECSSRA_Msk                (0x1UL << RCC_LSECFGR_LSECSSRA_Pos)   /*!< 0x00000100 */
+#define RCC_LSECFGR_LSECSSRA                    RCC_LSECFGR_LSECSSRA_Msk             /*!< LSE clock security system (CSS) rearm function */
+#define RCC_LSECFGR_LSECSSD_Pos                 (9U)
+#define RCC_LSECFGR_LSECSSD_Msk                 (0x1UL << RCC_LSECFGR_LSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_LSECFGR_LSECSSD                     RCC_LSECFGR_LSECSSD_Msk              /*!< LSE clock security system (CSS) failure detection */
+#define RCC_LSECFGR_LSEBYP_Pos                  (15U)
+#define RCC_LSECFGR_LSEBYP_Msk                  (0x1UL << RCC_LSECFGR_LSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_LSECFGR_LSEBYP                      RCC_LSECFGR_LSEBYP_Msk               /*!< LSE clock bypass */
+#define RCC_LSECFGR_LSEEXT_Pos                  (16U)
+#define RCC_LSECFGR_LSEEXT_Msk                  (0x1UL << RCC_LSECFGR_LSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_LSECFGR_LSEEXT                      RCC_LSECFGR_LSEEXT_Msk               /*!< LSE clock type in bypass mode */
+#define RCC_LSECFGR_LSEGFON_Pos                 (17U)
+#define RCC_LSECFGR_LSEGFON_Msk                 (0x1UL << RCC_LSECFGR_LSEGFON_Pos)    /*!< 0x00020000 */
+#define RCC_LSECFGR_LSEGFON                     RCC_LSECFGR_LSEGFON_Msk              /*!< LSE clock glitch filter enable */
+#define RCC_LSECFGR_LSEDRV_Pos                  (18U)
+#define RCC_LSECFGR_LSEDRV_Msk                  (0x3UL << RCC_LSECFGR_LSEDRV_Pos)     /*!< 0x000C0000 */
+#define RCC_LSECFGR_LSEDRV                      RCC_LSECFGR_LSEDRV_Msk               /*!< LSE oscillator driving capability */
+#define RCC_LSECFGR_LSEDRV_0                    (0x1UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00040000 */
+#define RCC_LSECFGR_LSEDRV_1                    (0x2UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for RCC_MSICFGR register  ******************/
+#define RCC_MSICFGR_MSIFREQSEL_Pos              (9U)
+#define RCC_MSICFGR_MSIFREQSEL_Msk              (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */
+#define RCC_MSICFGR_MSIFREQSEL                  RCC_MSICFGR_MSIFREQSEL_Msk           /*!< MSI oscillator frequency selection */
+#define RCC_MSICFGR_MSITRIM_Pos                 (16U)
+#define RCC_MSICFGR_MSITRIM_Msk                 (0x1FUL << RCC_MSICFGR_MSITRIM_Pos)   /*!< 0x001F0000 */
+#define RCC_MSICFGR_MSITRIM                     RCC_MSICFGR_MSITRIM_Msk              /*!< MSI clock trimming */
+#define RCC_MSICFGR_MSICAL_Pos                  (23U)
+#define RCC_MSICFGR_MSICAL_Msk                  (0xFFUL << RCC_MSICFGR_MSICAL_Pos)    /*!< 0x7F800000 */
+#define RCC_MSICFGR_MSICAL                      RCC_MSICFGR_MSICAL_Msk               /*!< MSI clock calibration */
+
+/*****************  Bit definition for RCC_HSICFGR register  ******************/
+#define RCC_HSICFGR_HSIDIV_Pos                  (7U)
+#define RCC_HSICFGR_HSIDIV_Msk                  (0x3UL << RCC_HSICFGR_HSIDIV_Pos)     /*!< 0x00000180 */
+#define RCC_HSICFGR_HSIDIV                      RCC_HSICFGR_HSIDIV_Msk               /*!< HSI clock divider */
+#define RCC_HSICFGR_HSIDIV_0                    (0x1UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000080 */
+#define RCC_HSICFGR_HSIDIV_1                    (0x2UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000100 */
+#define RCC_HSICFGR_HSITRIM_Pos                 (16U)
+#define RCC_HSICFGR_HSITRIM_Msk                 (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)   /*!< 0x007F0000 */
+#define RCC_HSICFGR_HSITRIM                     RCC_HSICFGR_HSITRIM_Msk              /*!< HSI clock trimming */
+#define RCC_HSICFGR_HSICAL_Pos                  (23U)
+#define RCC_HSICFGR_HSICAL_Msk                  (0x1FFUL << RCC_HSICFGR_HSICAL_Pos)   /*!< 0xFF800000 */
+#define RCC_HSICFGR_HSICAL                      RCC_HSICFGR_HSICAL_Msk               /*!< HSI clock calibration */
+
+/******************  Bit definition for RCC_HSIMCR register  ******************/
+#define RCC_HSIMCR_HSIREF_Pos                   (0U)
+#define RCC_HSIMCR_HSIREF_Msk                   (0x7FFUL << RCC_HSIMCR_HSIREF_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMCR_HSIREF                       RCC_HSIMCR_HSIREF_Msk                /*!< HSI clock-cycle counter reference value */
+#define RCC_HSIMCR_HSIDEV_Pos                   (16U)
+#define RCC_HSIMCR_HSIDEV_Msk                   (0x3FUL << RCC_HSIMCR_HSIDEV_Pos)     /*!< 0x003F0000 */
+#define RCC_HSIMCR_HSIDEV                       RCC_HSIMCR_HSIDEV_Msk                /*!< HSI clock count deviation value */
+#define RCC_HSIMCR_HSIMONEN_Pos                 (31U)
+#define RCC_HSIMCR_HSIMONEN_Msk                 (0x1UL << RCC_HSIMCR_HSIMONEN_Pos)    /*!< 0x80000000 */
+#define RCC_HSIMCR_HSIMONEN                     RCC_HSIMCR_HSIMONEN_Msk              /*!< HSI clock period monitor enable */
+
+/******************  Bit definition for RCC_HSIMSR register  ******************/
+#define RCC_HSIMSR_HSIVAL_Pos                   (0U)
+#define RCC_HSIMSR_HSIVAL_Msk                   (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMSR_HSIVAL                       RCC_HSIMSR_HSIVAL_Msk                /*!< HSI clock-cycle counter measured value */
+
+/*****************  Bit definition for RCC_HSECFGR register  ******************/
+#define RCC_HSECFGR_HSEDIV2SEL_Pos              (6U)
+#define RCC_HSECFGR_HSEDIV2SEL_Msk              (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */
+#define RCC_HSECFGR_HSEDIV2SEL                  RCC_HSECFGR_HSEDIV2SEL_Msk           /*!< HSE div2 clock source select */
+#define RCC_HSECFGR_HSECSSON_Pos                (7U)
+#define RCC_HSECFGR_HSECSSON_Msk                (0x1UL << RCC_HSECFGR_HSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_HSECFGR_HSECSSON                    RCC_HSECFGR_HSECSSON_Msk             /*!< HSE CSS enable */
+#define RCC_HSECFGR_HSECSSD_Pos                 (9U)
+#define RCC_HSECFGR_HSECSSD_Msk                 (0x1UL << RCC_HSECFGR_HSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_HSECFGR_HSECSSD                     RCC_HSECFGR_HSECSSD_Msk              /*!< HSE CSS failure detection */
+#define RCC_HSECFGR_HSECSSBYP_Pos               (10U)
+#define RCC_HSECFGR_HSECSSBYP_Msk               (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos)  /*!< 0x00000400 */
+#define RCC_HSECFGR_HSECSSBYP                   RCC_HSECFGR_HSECSSBYP_Msk            /*!< HSE CSS bypass enable */
+#define RCC_HSECFGR_HSECSSBPRE_Pos              (11U)
+#define RCC_HSECFGR_HSECSSBPRE_Msk              (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */
+#define RCC_HSECFGR_HSECSSBPRE                  RCC_HSECFGR_HSECSSBPRE_Msk           /*!< HSE CSS bypass divider */
+#define RCC_HSECFGR_HSECSSBPRE_0                (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */
+#define RCC_HSECFGR_HSECSSBPRE_1                (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */
+#define RCC_HSECFGR_HSECSSBPRE_2                (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */
+#define RCC_HSECFGR_HSECSSBPRE_3                (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */
+#define RCC_HSECFGR_HSEBYP_Pos                  (15U)
+#define RCC_HSECFGR_HSEBYP_Msk                  (0x1UL << RCC_HSECFGR_HSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_HSECFGR_HSEBYP                      RCC_HSECFGR_HSEBYP_Msk               /*!< HSE clock bypass */
+#define RCC_HSECFGR_HSEEXT_Pos                  (16U)
+#define RCC_HSECFGR_HSEEXT_Msk                  (0x1UL << RCC_HSECFGR_HSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_HSECFGR_HSEEXT                      RCC_HSECFGR_HSEEXT_Msk               /*!< HSE clock type in bypass mode */
+
+/****************  Bit definition for RCC_PLL1CFGR1 register  *****************/
+#define RCC_PLL1CFGR1_PLL1DIVN_Pos              (8U)
+#define RCC_PLL1CFGR1_PLL1DIVN_Msk              (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL1CFGR1_PLL1DIVN                  RCC_PLL1CFGR1_PLL1DIVN_Msk           /*!< PLL1 integer part for the VCO multiplication factor */
+#define RCC_PLL1CFGR1_PLL1DIVM_Pos              (20U)
+#define RCC_PLL1CFGR1_PLL1DIVM_Msk              (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL1CFGR1_PLL1DIVM                  RCC_PLL1CFGR1_PLL1DIVM_Msk           /*!< PLL1 reference input clock divide frequency ratio */
+#define RCC_PLL1CFGR1_PLL1BYP_Pos               (27U)
+#define RCC_PLL1CFGR1_PLL1BYP_Msk               (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL1CFGR1_PLL1BYP                   RCC_PLL1CFGR1_PLL1BYP_Msk            /*!< PLL1 bypass */
+#define RCC_PLL1CFGR1_PLL1SEL_Pos               (28U)
+#define RCC_PLL1CFGR1_PLL1SEL_Msk               (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL1CFGR1_PLL1SEL                   RCC_PLL1CFGR1_PLL1SEL_Msk            /*!< PLL1 source selection of the reference clock */
+#define RCC_PLL1CFGR1_PLL1SEL_0                 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_1                 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_2                 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL1CFGR2 register  *****************/
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos          (0U)
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC              RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk       /*!< PLL1 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL1CFGR3 register  *****************/
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos          (0U)
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL1CFGR3_PLL1MODSSRST              RCC_PLL1CFGR3_PLL1MODSSRST_Msk       /*!< PLL1 modulation spread spectrum reset */
+#define RCC_PLL1CFGR3_PLL1DACEN_Pos             (1U)
+#define RCC_PLL1CFGR3_PLL1DACEN_Msk             (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL1CFGR3_PLL1DACEN                 RCC_PLL1CFGR3_PLL1DACEN_Msk          /*!< PLL1 noise canceling DAC enable in fractional mode */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos          (2U)
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS              RCC_PLL1CFGR3_PLL1MODSSDIS_Msk       /*!< PLL1 modulation spread spectrum disable  */
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos           (3U)
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk           (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL1CFGR3_PLL1MODDSEN               RCC_PLL1CFGR3_PLL1MODDSEN_Msk        /*!< PLL1 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos          (4U)
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW              RCC_PLL1CFGR3_PLL1MODSPRDW_Msk       /*!< PLL1 modulation spread spectrum down */
+#define RCC_PLL1CFGR3_PLL1MODDIV_Pos            (8U)
+#define RCC_PLL1CFGR3_PLL1MODDIV_Msk            (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL1CFGR3_PLL1MODDIV                RCC_PLL1CFGR3_PLL1MODDIV_Msk         /*!< PLL1 modulation division frequency adjustment  */
+#define RCC_PLL1CFGR3_PLL1MODSPR_Pos            (16U)
+#define RCC_PLL1CFGR3_PLL1MODSPR_Msk            (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL1CFGR3_PLL1MODSPR                RCC_PLL1CFGR3_PLL1MODSPR_Msk         /*!< PLL1 modulation spread depth adjustment */
+#define RCC_PLL1CFGR3_PLL1PDIV2_Pos             (24U)
+#define RCC_PLL1CFGR3_PLL1PDIV2_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV2                 RCC_PLL1CFGR3_PLL1PDIV2_Msk          /*!< PLL1 VCO frequency divider level 2 */
+#define RCC_PLL1CFGR3_PLL1PDIV1_Pos             (27U)
+#define RCC_PLL1CFGR3_PLL1PDIV1_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV1                 RCC_PLL1CFGR3_PLL1PDIV1_Msk          /*!< PLL1 VCO frequency divider level 1 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos            (30U)
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk            (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN                RCC_PLL1CFGR3_PLL1PDIVEN_Msk         /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL2CFGR1 register  *****************/
+#define RCC_PLL2CFGR1_PLL2DIVN_Pos              (8U)
+#define RCC_PLL2CFGR1_PLL2DIVN_Msk              (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL2CFGR1_PLL2DIVN                  RCC_PLL2CFGR1_PLL2DIVN_Msk           /*!< PLL2 integer part for the VCO multiplication factor */
+#define RCC_PLL2CFGR1_PLL2DIVM_Pos              (20U)
+#define RCC_PLL2CFGR1_PLL2DIVM_Msk              (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL2CFGR1_PLL2DIVM                  RCC_PLL2CFGR1_PLL2DIVM_Msk           /*!< PLL2 reference input clock divide frequency ratio */
+#define RCC_PLL2CFGR1_PLL2BYP_Pos               (27U)
+#define RCC_PLL2CFGR1_PLL2BYP_Msk               (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL2CFGR1_PLL2BYP                   RCC_PLL2CFGR1_PLL2BYP_Msk            /*!< PLL2 bypass */
+#define RCC_PLL2CFGR1_PLL2SEL_Pos               (28U)
+#define RCC_PLL2CFGR1_PLL2SEL_Msk               (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL2CFGR1_PLL2SEL                   RCC_PLL2CFGR1_PLL2SEL_Msk            /*!< PLL2 source selection of the reference clock */
+#define RCC_PLL2CFGR1_PLL2SEL_0                 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_1                 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_2                 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL2CFGR2 register  *****************/
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos          (0U)
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC              RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk       /*!< PLL2 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL2CFGR3 register  *****************/
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos          (0U)
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL2CFGR3_PLL2MODSSRST              RCC_PLL2CFGR3_PLL2MODSSRST_Msk       /*!< PLL2 modulation spread spectrum reset */
+#define RCC_PLL2CFGR3_PLL2DACEN_Pos             (1U)
+#define RCC_PLL2CFGR3_PLL2DACEN_Msk             (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL2CFGR3_PLL2DACEN                 RCC_PLL2CFGR3_PLL2DACEN_Msk          /*!< PLL2 noise canceling DAC enable in fractional mode */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos          (2U)
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS              RCC_PLL2CFGR3_PLL2MODSSDIS_Msk       /*!< PLL2 modulation spread spectrum disable  */
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos           (3U)
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk           (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL2CFGR3_PLL2MODDSEN               RCC_PLL2CFGR3_PLL2MODDSEN_Msk        /*!< PLL2 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos          (4U)
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW              RCC_PLL2CFGR3_PLL2MODSPRDW_Msk       /*!< PLL2 modulation down spread */
+#define RCC_PLL2CFGR3_PLL2MODDIV_Pos            (8U)
+#define RCC_PLL2CFGR3_PLL2MODDIV_Msk            (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL2CFGR3_PLL2MODDIV                RCC_PLL2CFGR3_PLL2MODDIV_Msk         /*!< PLL2 modulation division frequency adjustment  */
+#define RCC_PLL2CFGR3_PLL2MODSPR_Pos            (16U)
+#define RCC_PLL2CFGR3_PLL2MODSPR_Msk            (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL2CFGR3_PLL2MODSPR                RCC_PLL2CFGR3_PLL2MODSPR_Msk         /*!< PLL2 modulation spread depth adjustment */
+#define RCC_PLL2CFGR3_PLL2PDIV2_Pos             (24U)
+#define RCC_PLL2CFGR3_PLL2PDIV2_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV2                 RCC_PLL2CFGR3_PLL2PDIV2_Msk          /*!< PLL2 VCO frequency divider level 2 */
+#define RCC_PLL2CFGR3_PLL2PDIV1_Pos             (27U)
+#define RCC_PLL2CFGR3_PLL2PDIV1_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV1                 RCC_PLL2CFGR3_PLL2PDIV1_Msk          /*!< PLL2 VCO frequency divider level 1 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos            (30U)
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk            (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN                RCC_PLL2CFGR3_PLL2PDIVEN_Msk         /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL3CFGR1 register  *****************/
+#define RCC_PLL3CFGR1_PLL3DIVN_Pos              (8U)
+#define RCC_PLL3CFGR1_PLL3DIVN_Msk              (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL3CFGR1_PLL3DIVN                  RCC_PLL3CFGR1_PLL3DIVN_Msk           /*!< PLL3 Integer part for the VCO multiplication factor */
+#define RCC_PLL3CFGR1_PLL3DIVM_Pos              (20U)
+#define RCC_PLL3CFGR1_PLL3DIVM_Msk              (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL3CFGR1_PLL3DIVM                  RCC_PLL3CFGR1_PLL3DIVM_Msk           /*!< PLL3 reference input clock divide frequency ratio */
+#define RCC_PLL3CFGR1_PLL3BYP_Pos               (27U)
+#define RCC_PLL3CFGR1_PLL3BYP_Msk               (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL3CFGR1_PLL3BYP                   RCC_PLL3CFGR1_PLL3BYP_Msk            /*!< PLL3 bypass */
+#define RCC_PLL3CFGR1_PLL3SEL_Pos               (28U)
+#define RCC_PLL3CFGR1_PLL3SEL_Msk               (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL3CFGR1_PLL3SEL                   RCC_PLL3CFGR1_PLL3SEL_Msk            /*!< PLL3 source selection of the reference clock */
+#define RCC_PLL3CFGR1_PLL3SEL_0                 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_1                 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_2                 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL3CFGR2 register  *****************/
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos          (0U)
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC              RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk       /*!< PLL3 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL3CFGR3 register  *****************/
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos          (0U)
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL3CFGR3_PLL3MODSSRST              RCC_PLL3CFGR3_PLL3MODSSRST_Msk       /*!< PLL3 modulation spread spectrum reset */
+#define RCC_PLL3CFGR3_PLL3DACEN_Pos             (1U)
+#define RCC_PLL3CFGR3_PLL3DACEN_Msk             (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL3CFGR3_PLL3DACEN                 RCC_PLL3CFGR3_PLL3DACEN_Msk          /*!< PLL3 noise canceling DAC enable in fractional mode */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos          (2U)
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS              RCC_PLL3CFGR3_PLL3MODSSDIS_Msk       /*!< PLL3 modulation spread spectrum disable  */
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos           (3U)
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk           (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL3CFGR3_PLL3MODDSEN               RCC_PLL3CFGR3_PLL3MODDSEN_Msk        /*!< PLL3 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos          (4U)
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW              RCC_PLL3CFGR3_PLL3MODSPRDW_Msk       /*!< PLL3 modulation down spread */
+#define RCC_PLL3CFGR3_PLL3MODDIV_Pos            (8U)
+#define RCC_PLL3CFGR3_PLL3MODDIV_Msk            (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL3CFGR3_PLL3MODDIV                RCC_PLL3CFGR3_PLL3MODDIV_Msk         /*!< PLL3 modulation division frequency adjustment  */
+#define RCC_PLL3CFGR3_PLL3MODSPR_Pos            (16U)
+#define RCC_PLL3CFGR3_PLL3MODSPR_Msk            (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL3CFGR3_PLL3MODSPR                RCC_PLL3CFGR3_PLL3MODSPR_Msk         /*!< PLL3 modulation spread depth adjustment */
+#define RCC_PLL3CFGR3_PLL3PDIV2_Pos             (24U)
+#define RCC_PLL3CFGR3_PLL3PDIV2_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV2                 RCC_PLL3CFGR3_PLL3PDIV2_Msk          /*!< PLL3 VCO frequency divider level 2 */
+#define RCC_PLL3CFGR3_PLL3PDIV1_Pos             (27U)
+#define RCC_PLL3CFGR3_PLL3PDIV1_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV1                 RCC_PLL3CFGR3_PLL3PDIV1_Msk          /*!< PLL3 VCO frequency divider level 1 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos            (30U)
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk            (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN                RCC_PLL3CFGR3_PLL3PDIVEN_Msk         /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL4CFGR1 register  *****************/
+#define RCC_PLL4CFGR1_PLL4DIVN_Pos              (8U)
+#define RCC_PLL4CFGR1_PLL4DIVN_Msk              (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL4CFGR1_PLL4DIVN                  RCC_PLL4CFGR1_PLL4DIVN_Msk           /*!< PLL4 integer part for the VCO multiplication factor */
+#define RCC_PLL4CFGR1_PLL4DIVM_Pos              (20U)
+#define RCC_PLL4CFGR1_PLL4DIVM_Msk              (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL4CFGR1_PLL4DIVM                  RCC_PLL4CFGR1_PLL4DIVM_Msk           /*!< PLL4 reference input clock divide frequency ratio */
+#define RCC_PLL4CFGR1_PLL4BYP_Pos               (27U)
+#define RCC_PLL4CFGR1_PLL4BYP_Msk               (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL4CFGR1_PLL4BYP                   RCC_PLL4CFGR1_PLL4BYP_Msk            /*!< PLL4 bypass */
+#define RCC_PLL4CFGR1_PLL4SEL_Pos               (28U)
+#define RCC_PLL4CFGR1_PLL4SEL_Msk               (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL4CFGR1_PLL4SEL                   RCC_PLL4CFGR1_PLL4SEL_Msk            /*!< PLL4 source selection of the reference clock */
+#define RCC_PLL4CFGR1_PLL4SEL_0                 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_1                 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_2                 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL4CFGR2 register  *****************/
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos          (0U)
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC              RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk       /*!< PLL4 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL4CFGR3 register  *****************/
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos          (0U)
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL4CFGR3_PLL4MODSSRST              RCC_PLL4CFGR3_PLL4MODSSRST_Msk       /*!< PLL4 modulation spread spectrum reset */
+#define RCC_PLL4CFGR3_PLL4DACEN_Pos             (1U)
+#define RCC_PLL4CFGR3_PLL4DACEN_Msk             (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL4CFGR3_PLL4DACEN                 RCC_PLL4CFGR3_PLL4DACEN_Msk          /*!< PLL4 noise canceling DAC enable in fractional mode */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos          (2U)
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS              RCC_PLL4CFGR3_PLL4MODSSDIS_Msk       /*!< PLL4 modulation spread spectrum disable  */
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos           (3U)
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk           (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL4CFGR3_PLL4MODDSEN               RCC_PLL4CFGR3_PLL4MODDSEN_Msk        /*!< PLL4 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos          (4U)
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW              RCC_PLL4CFGR3_PLL4MODSPRDW_Msk       /*!< PLL4 modulation down spread */
+#define RCC_PLL4CFGR3_PLL4MODDIV_Pos            (8U)
+#define RCC_PLL4CFGR3_PLL4MODDIV_Msk            (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL4CFGR3_PLL4MODDIV                RCC_PLL4CFGR3_PLL4MODDIV_Msk         /*!< PLL4 modulation division frequency adjustment  */
+#define RCC_PLL4CFGR3_PLL4MODSPR_Pos            (16U)
+#define RCC_PLL4CFGR3_PLL4MODSPR_Msk            (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL4CFGR3_PLL4MODSPR                RCC_PLL4CFGR3_PLL4MODSPR_Msk         /*!< PLL4 modulation spread depth adjustment */
+#define RCC_PLL4CFGR3_PLL4PDIV2_Pos             (24U)
+#define RCC_PLL4CFGR3_PLL4PDIV2_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV2                 RCC_PLL4CFGR3_PLL4PDIV2_Msk          /*!< PLL4 VCO frequency divider level 2 */
+#define RCC_PLL4CFGR3_PLL4PDIV1_Pos             (27U)
+#define RCC_PLL4CFGR3_PLL4PDIV1_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV1                 RCC_PLL4CFGR3_PLL4PDIV1_Msk          /*!< PLL4 VCO frequency divider level 1 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos            (30U)
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk            (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN                RCC_PLL4CFGR3_PLL4PDIVEN_Msk         /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/*****************  Bit definition for RCC_IC1CFGR register  ******************/
+#define RCC_IC1CFGR_IC1INT_Pos                  (16U)
+#define RCC_IC1CFGR_IC1INT_Msk                  (0xFFUL << RCC_IC1CFGR_IC1INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC1CFGR_IC1INT                      RCC_IC1CFGR_IC1INT_Msk               /*!< Divider IC1 integer division factor */
+#define RCC_IC1CFGR_IC1SEL_Pos                  (28U)
+#define RCC_IC1CFGR_IC1SEL_Msk                  (0x3UL << RCC_IC1CFGR_IC1SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC1CFGR_IC1SEL                      RCC_IC1CFGR_IC1SEL_Msk               /*!< Divider IC1 source selection */
+#define RCC_IC1CFGR_IC1SEL_0                    (0x1UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC1CFGR_IC1SEL_1                    (0x2UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC2CFGR register  ******************/
+#define RCC_IC2CFGR_IC2INT_Pos                  (16U)
+#define RCC_IC2CFGR_IC2INT_Msk                  (0xFFUL << RCC_IC2CFGR_IC2INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC2CFGR_IC2INT                      RCC_IC2CFGR_IC2INT_Msk               /*!< Divider IC2 integer division factor */
+#define RCC_IC2CFGR_IC2SEL_Pos                  (28U)
+#define RCC_IC2CFGR_IC2SEL_Msk                  (0x3UL << RCC_IC2CFGR_IC2SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC2CFGR_IC2SEL                      RCC_IC2CFGR_IC2SEL_Msk               /*!< Divider IC2 source selection */
+#define RCC_IC2CFGR_IC2SEL_0                    (0x1UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC2CFGR_IC2SEL_1                    (0x2UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC3CFGR register  ******************/
+#define RCC_IC3CFGR_IC3INT_Pos                  (16U)
+#define RCC_IC3CFGR_IC3INT_Msk                  (0xFFUL << RCC_IC3CFGR_IC3INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC3CFGR_IC3INT                      RCC_IC3CFGR_IC3INT_Msk               /*!< Divider IC3 integer division factor */
+#define RCC_IC3CFGR_IC3SEL_Pos                  (28U)
+#define RCC_IC3CFGR_IC3SEL_Msk                  (0x3UL << RCC_IC3CFGR_IC3SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC3CFGR_IC3SEL                      RCC_IC3CFGR_IC3SEL_Msk               /*!< Divider IC3 source selection */
+#define RCC_IC3CFGR_IC3SEL_0                    (0x1UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC3CFGR_IC3SEL_1                    (0x2UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC4CFGR register  ******************/
+#define RCC_IC4CFGR_IC4INT_Pos                  (16U)
+#define RCC_IC4CFGR_IC4INT_Msk                  (0xFFUL << RCC_IC4CFGR_IC4INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC4CFGR_IC4INT                      RCC_IC4CFGR_IC4INT_Msk               /*!< Divider IC4 integer division factor */
+#define RCC_IC4CFGR_IC4SEL_Pos                  (28U)
+#define RCC_IC4CFGR_IC4SEL_Msk                  (0x3UL << RCC_IC4CFGR_IC4SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC4CFGR_IC4SEL                      RCC_IC4CFGR_IC4SEL_Msk               /*!< Divider IC4 source selection */
+#define RCC_IC4CFGR_IC4SEL_0                    (0x1UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC4CFGR_IC4SEL_1                    (0x2UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC5CFGR register  ******************/
+#define RCC_IC5CFGR_IC5INT_Pos                  (16U)
+#define RCC_IC5CFGR_IC5INT_Msk                  (0xFFUL << RCC_IC5CFGR_IC5INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC5CFGR_IC5INT                      RCC_IC5CFGR_IC5INT_Msk               /*!< Divider IC5 integer division factor */
+#define RCC_IC5CFGR_IC5SEL_Pos                  (28U)
+#define RCC_IC5CFGR_IC5SEL_Msk                  (0x3UL << RCC_IC5CFGR_IC5SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC5CFGR_IC5SEL                      RCC_IC5CFGR_IC5SEL_Msk               /*!< Divider IC5 source selection */
+#define RCC_IC5CFGR_IC5SEL_0                    (0x1UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC5CFGR_IC5SEL_1                    (0x2UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC6CFGR register  ******************/
+#define RCC_IC6CFGR_IC6INT_Pos                  (16U)
+#define RCC_IC6CFGR_IC6INT_Msk                  (0xFFUL << RCC_IC6CFGR_IC6INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC6CFGR_IC6INT                      RCC_IC6CFGR_IC6INT_Msk               /*!< Divider IC6 integer division factor */
+#define RCC_IC6CFGR_IC6SEL_Pos                  (28U)
+#define RCC_IC6CFGR_IC6SEL_Msk                  (0x3UL << RCC_IC6CFGR_IC6SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC6CFGR_IC6SEL                      RCC_IC6CFGR_IC6SEL_Msk               /*!< Divider IC6 source selection */
+#define RCC_IC6CFGR_IC6SEL_0                    (0x1UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC6CFGR_IC6SEL_1                    (0x2UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC7CFGR register  ******************/
+#define RCC_IC7CFGR_IC7INT_Pos                  (16U)
+#define RCC_IC7CFGR_IC7INT_Msk                  (0xFFUL << RCC_IC7CFGR_IC7INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC7CFGR_IC7INT                      RCC_IC7CFGR_IC7INT_Msk               /*!< Divider IC7 integer division factor */
+#define RCC_IC7CFGR_IC7SEL_Pos                  (28U)
+#define RCC_IC7CFGR_IC7SEL_Msk                  (0x3UL << RCC_IC7CFGR_IC7SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC7CFGR_IC7SEL                      RCC_IC7CFGR_IC7SEL_Msk               /*!< Divider IC7 source selection */
+#define RCC_IC7CFGR_IC7SEL_0                    (0x1UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC7CFGR_IC7SEL_1                    (0x2UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC8CFGR register  ******************/
+#define RCC_IC8CFGR_IC8INT_Pos                  (16U)
+#define RCC_IC8CFGR_IC8INT_Msk                  (0xFFUL << RCC_IC8CFGR_IC8INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC8CFGR_IC8INT                      RCC_IC8CFGR_IC8INT_Msk               /*!< Divider IC8 integer division factor */
+#define RCC_IC8CFGR_IC8SEL_Pos                  (28U)
+#define RCC_IC8CFGR_IC8SEL_Msk                  (0x3UL << RCC_IC8CFGR_IC8SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC8CFGR_IC8SEL                      RCC_IC8CFGR_IC8SEL_Msk               /*!< Divider IC8 source selection */
+#define RCC_IC8CFGR_IC8SEL_0                    (0x1UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC8CFGR_IC8SEL_1                    (0x2UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC9CFGR register  ******************/
+#define RCC_IC9CFGR_IC9INT_Pos                  (16U)
+#define RCC_IC9CFGR_IC9INT_Msk                  (0xFFUL << RCC_IC9CFGR_IC9INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC9CFGR_IC9INT                      RCC_IC9CFGR_IC9INT_Msk               /*!< Divider IC9 integer division factor */
+#define RCC_IC9CFGR_IC9SEL_Pos                  (28U)
+#define RCC_IC9CFGR_IC9SEL_Msk                  (0x3UL << RCC_IC9CFGR_IC9SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC9CFGR_IC9SEL                      RCC_IC9CFGR_IC9SEL_Msk               /*!< Divider IC9 source selection */
+#define RCC_IC9CFGR_IC9SEL_0                    (0x1UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC9CFGR_IC9SEL_1                    (0x2UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC10CFGR register  *****************/
+#define RCC_IC10CFGR_IC10INT_Pos                (16U)
+#define RCC_IC10CFGR_IC10INT_Msk                (0xFFUL << RCC_IC10CFGR_IC10INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC10CFGR_IC10INT                    RCC_IC10CFGR_IC10INT_Msk             /*!< Divider IC10 integer division factor */
+#define RCC_IC10CFGR_IC10SEL_Pos                (28U)
+#define RCC_IC10CFGR_IC10SEL_Msk                (0x3UL << RCC_IC10CFGR_IC10SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC10CFGR_IC10SEL                    RCC_IC10CFGR_IC10SEL_Msk             /*!< Divider IC10 source selection */
+#define RCC_IC10CFGR_IC10SEL_0                  (0x1UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC10CFGR_IC10SEL_1                  (0x2UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC11CFGR register  *****************/
+#define RCC_IC11CFGR_IC11INT_Pos                (16U)
+#define RCC_IC11CFGR_IC11INT_Msk                (0xFFUL << RCC_IC11CFGR_IC11INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC11CFGR_IC11INT                    RCC_IC11CFGR_IC11INT_Msk             /*!< Divider IC11 integer division factor */
+#define RCC_IC11CFGR_IC11SEL_Pos                (28U)
+#define RCC_IC11CFGR_IC11SEL_Msk                (0x3UL << RCC_IC11CFGR_IC11SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC11CFGR_IC11SEL                    RCC_IC11CFGR_IC11SEL_Msk             /*!< Divider IC11 source selection */
+#define RCC_IC11CFGR_IC11SEL_0                  (0x1UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC11CFGR_IC11SEL_1                  (0x2UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC12CFGR register  *****************/
+#define RCC_IC12CFGR_IC12INT_Pos                (16U)
+#define RCC_IC12CFGR_IC12INT_Msk                (0xFFUL << RCC_IC12CFGR_IC12INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC12CFGR_IC12INT                    RCC_IC12CFGR_IC12INT_Msk             /*!< Divider IC12 integer division factor */
+#define RCC_IC12CFGR_IC12SEL_Pos                (28U)
+#define RCC_IC12CFGR_IC12SEL_Msk                (0x3UL << RCC_IC12CFGR_IC12SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC12CFGR_IC12SEL                    RCC_IC12CFGR_IC12SEL_Msk             /*!< Divider IC12 source selection */
+#define RCC_IC12CFGR_IC12SEL_0                  (0x1UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC12CFGR_IC12SEL_1                  (0x2UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC13CFGR register  *****************/
+#define RCC_IC13CFGR_IC13INT_Pos                (16U)
+#define RCC_IC13CFGR_IC13INT_Msk                (0xFFUL << RCC_IC13CFGR_IC13INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC13CFGR_IC13INT                    RCC_IC13CFGR_IC13INT_Msk             /*!< Divider IC13 integer division factor */
+#define RCC_IC13CFGR_IC13SEL_Pos                (28U)
+#define RCC_IC13CFGR_IC13SEL_Msk                (0x3UL << RCC_IC13CFGR_IC13SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC13CFGR_IC13SEL                    RCC_IC13CFGR_IC13SEL_Msk             /*!< Divider IC13 source selection */
+#define RCC_IC13CFGR_IC13SEL_0                  (0x1UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC13CFGR_IC13SEL_1                  (0x2UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC14CFGR register  *****************/
+#define RCC_IC14CFGR_IC14INT_Pos                (16U)
+#define RCC_IC14CFGR_IC14INT_Msk                (0xFFUL << RCC_IC14CFGR_IC14INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC14CFGR_IC14INT                    RCC_IC14CFGR_IC14INT_Msk             /*!< Divider IC14 integer division factor */
+#define RCC_IC14CFGR_IC14SEL_Pos                (28U)
+#define RCC_IC14CFGR_IC14SEL_Msk                (0x3UL << RCC_IC14CFGR_IC14SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC14CFGR_IC14SEL                    RCC_IC14CFGR_IC14SEL_Msk             /*!< Divider IC14 source selection */
+#define RCC_IC14CFGR_IC14SEL_0                  (0x1UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC14CFGR_IC14SEL_1                  (0x2UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC15CFGR register  *****************/
+#define RCC_IC15CFGR_IC15INT_Pos                (16U)
+#define RCC_IC15CFGR_IC15INT_Msk                (0xFFUL << RCC_IC15CFGR_IC15INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC15CFGR_IC15INT                    RCC_IC15CFGR_IC15INT_Msk             /*!< Divider IC15 integer division factor */
+#define RCC_IC15CFGR_IC15SEL_Pos                (28U)
+#define RCC_IC15CFGR_IC15SEL_Msk                (0x3UL << RCC_IC15CFGR_IC15SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC15CFGR_IC15SEL                    RCC_IC15CFGR_IC15SEL_Msk             /*!< Divider IC15 source selection */
+#define RCC_IC15CFGR_IC15SEL_0                  (0x1UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC15CFGR_IC15SEL_1                  (0x2UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC16CFGR register  *****************/
+#define RCC_IC16CFGR_IC16INT_Pos                (16U)
+#define RCC_IC16CFGR_IC16INT_Msk                (0xFFUL << RCC_IC16CFGR_IC16INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC16CFGR_IC16INT                    RCC_IC16CFGR_IC16INT_Msk             /*!< Divider IC16 integer division factor */
+#define RCC_IC16CFGR_IC16SEL_Pos                (28U)
+#define RCC_IC16CFGR_IC16SEL_Msk                (0x3UL << RCC_IC16CFGR_IC16SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC16CFGR_IC16SEL                    RCC_IC16CFGR_IC16SEL_Msk             /*!< Divider IC16 source selection */
+#define RCC_IC16CFGR_IC16SEL_0                  (0x1UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC16CFGR_IC16SEL_1                  (0x2UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC17CFGR register  *****************/
+#define RCC_IC17CFGR_IC17INT_Pos                (16U)
+#define RCC_IC17CFGR_IC17INT_Msk                (0xFFUL << RCC_IC17CFGR_IC17INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC17CFGR_IC17INT                    RCC_IC17CFGR_IC17INT_Msk             /*!< Divider IC17 integer division factor */
+#define RCC_IC17CFGR_IC17SEL_Pos                (28U)
+#define RCC_IC17CFGR_IC17SEL_Msk                (0x3UL << RCC_IC17CFGR_IC17SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC17CFGR_IC17SEL                    RCC_IC17CFGR_IC17SEL_Msk             /*!< Divider IC17 source selection */
+#define RCC_IC17CFGR_IC17SEL_0                  (0x1UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC17CFGR_IC17SEL_1                  (0x2UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC18CFGR register  *****************/
+#define RCC_IC18CFGR_IC18INT_Pos                (16U)
+#define RCC_IC18CFGR_IC18INT_Msk                (0xFFUL << RCC_IC18CFGR_IC18INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC18CFGR_IC18INT                    RCC_IC18CFGR_IC18INT_Msk             /*!< Divider IC18 integer division factor */
+#define RCC_IC18CFGR_IC18SEL_Pos                (28U)
+#define RCC_IC18CFGR_IC18SEL_Msk                (0x3UL << RCC_IC18CFGR_IC18SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC18CFGR_IC18SEL                    RCC_IC18CFGR_IC18SEL_Msk             /*!< Divider IC18 source selection */
+#define RCC_IC18CFGR_IC18SEL_0                  (0x1UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC18CFGR_IC18SEL_1                  (0x2UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC19CFGR register  *****************/
+#define RCC_IC19CFGR_IC19INT_Pos                (16U)
+#define RCC_IC19CFGR_IC19INT_Msk                (0xFFUL << RCC_IC19CFGR_IC19INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC19CFGR_IC19INT                    RCC_IC19CFGR_IC19INT_Msk             /*!< Divider IC19 integer division factor */
+#define RCC_IC19CFGR_IC19SEL_Pos                (28U)
+#define RCC_IC19CFGR_IC19SEL_Msk                (0x3UL << RCC_IC19CFGR_IC19SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC19CFGR_IC19SEL                    RCC_IC19CFGR_IC19SEL_Msk             /*!< Divider IC19 source selection */
+#define RCC_IC19CFGR_IC19SEL_0                  (0x1UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC19CFGR_IC19SEL_1                  (0x2UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC20CFGR register  *****************/
+#define RCC_IC20CFGR_IC20INT_Pos                (16U)
+#define RCC_IC20CFGR_IC20INT_Msk                (0xFFUL << RCC_IC20CFGR_IC20INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC20CFGR_IC20INT                    RCC_IC20CFGR_IC20INT_Msk             /*!< Divider IC20 integer division factor */
+#define RCC_IC20CFGR_IC20SEL_Pos                (28U)
+#define RCC_IC20CFGR_IC20SEL_Msk                (0x3UL << RCC_IC20CFGR_IC20SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC20CFGR_IC20SEL                    RCC_IC20CFGR_IC20SEL_Msk             /*!< Divider IC20 source selection */
+#define RCC_IC20CFGR_IC20SEL_0                  (0x1UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC20CFGR_IC20SEL_1                  (0x2UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x20000000 */
+
+/*******************  Bit definition for RCC_CIER register  *******************/
+#define RCC_CIER_LSIRDYIE_Pos                   (0U)
+#define RCC_CIER_LSIRDYIE_Msk                   (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                       RCC_CIER_LSIRDYIE_Msk                /*!< LSI ready interrupt enable */
+#define RCC_CIER_LSERDYIE_Pos                   (1U)
+#define RCC_CIER_LSERDYIE_Msk                   (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                       RCC_CIER_LSERDYIE_Msk                /*!< LSE ready interrupt enable */
+#define RCC_CIER_MSIRDYIE_Pos                   (2U)
+#define RCC_CIER_MSIRDYIE_Msk                   (0x1UL << RCC_CIER_MSIRDYIE_Pos)      /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                       RCC_CIER_MSIRDYIE_Msk                /*!< MSI ready interrupt enable */
+#define RCC_CIER_HSIRDYIE_Pos                   (3U)
+#define RCC_CIER_HSIRDYIE_Msk                   (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                       RCC_CIER_HSIRDYIE_Msk                /*!< HSI ready interrupt enable */
+#define RCC_CIER_HSERDYIE_Pos                   (4U)
+#define RCC_CIER_HSERDYIE_Msk                   (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                       RCC_CIER_HSERDYIE_Msk                /*!< HSE ready interrupt enable */
+#define RCC_CIER_PLL1RDYIE_Pos                  (8U)
+#define RCC_CIER_PLL1RDYIE_Msk                  (0x1UL << RCC_CIER_PLL1RDYIE_Pos)     /*!< 0x00000100 */
+#define RCC_CIER_PLL1RDYIE                      RCC_CIER_PLL1RDYIE_Msk               /*!< PLL1 ready interrupt enable */
+#define RCC_CIER_PLL2RDYIE_Pos                  (9U)
+#define RCC_CIER_PLL2RDYIE_Msk                  (0x1UL << RCC_CIER_PLL2RDYIE_Pos)     /*!< 0x00000200 */
+#define RCC_CIER_PLL2RDYIE                      RCC_CIER_PLL2RDYIE_Msk               /*!< PLL2 ready interrupt enable */
+#define RCC_CIER_PLL3RDYIE_Pos                  (10U)
+#define RCC_CIER_PLL3RDYIE_Msk                  (0x1UL << RCC_CIER_PLL3RDYIE_Pos)     /*!< 0x00000400 */
+#define RCC_CIER_PLL3RDYIE                      RCC_CIER_PLL3RDYIE_Msk               /*!< PLL3 ready interrupt enable */
+#define RCC_CIER_PLL4RDYIE_Pos                  (11U)
+#define RCC_CIER_PLL4RDYIE_Msk                  (0x1UL << RCC_CIER_PLL4RDYIE_Pos)     /*!< 0x00000800 */
+#define RCC_CIER_PLL4RDYIE                      RCC_CIER_PLL4RDYIE_Msk               /*!< PLL4 ready interrupt enable */
+#define RCC_CIER_LSECSSIE_Pos                   (16U)
+#define RCC_CIER_LSECSSIE_Msk                   (0x1UL << RCC_CIER_LSECSSIE_Pos)      /*!< 0x00010000 */
+#define RCC_CIER_LSECSSIE                       RCC_CIER_LSECSSIE_Msk                /*!< LSE CSS interrupt enable */
+#define RCC_CIER_HSECSSIE_Pos                   (17U)
+#define RCC_CIER_HSECSSIE_Msk                   (0x1UL << RCC_CIER_HSECSSIE_Pos)      /*!< 0x00020000 */
+#define RCC_CIER_HSECSSIE                       RCC_CIER_HSECSSIE_Msk                /*!< HSE CSS interrupt enable */
+#define RCC_CIER_WKUPIE_Pos                     (24U)
+#define RCC_CIER_WKUPIE_Msk                     (0x1UL << RCC_CIER_WKUPIE_Pos)        /*!< 0x01000000 */
+#define RCC_CIER_WKUPIE                         RCC_CIER_WKUPIE_Msk                  /*!< CPU wake-up from Stop interrupt enable */
+
+/*******************  Bit definition for RCC_CIFR register  *******************/
+#define RCC_CIFR_LSIRDYF_Pos                    (0U)
+#define RCC_CIFR_LSIRDYF_Msk                    (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                        RCC_CIFR_LSIRDYF_Msk                 /*!< LSI ready interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos                    (1U)
+#define RCC_CIFR_LSERDYF_Msk                    (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                        RCC_CIFR_LSERDYF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos                    (2U)
+#define RCC_CIFR_MSIRDYF_Msk                    (0x1UL << RCC_CIFR_MSIRDYF_Pos)       /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                        RCC_CIFR_MSIRDYF_Msk                 /*!< MSI ready interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos                    (3U)
+#define RCC_CIFR_HSIRDYF_Msk                    (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                        RCC_CIFR_HSIRDYF_Msk                 /*!< HSI ready interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos                    (4U)
+#define RCC_CIFR_HSERDYF_Msk                    (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                        RCC_CIFR_HSERDYF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_PLL1RDYF_Pos                   (8U)
+#define RCC_CIFR_PLL1RDYF_Msk                   (0x1UL << RCC_CIFR_PLL1RDYF_Pos)      /*!< 0x00000100 */
+#define RCC_CIFR_PLL1RDYF                       RCC_CIFR_PLL1RDYF_Msk                /*!< PLL1 ready interrupt flag */
+#define RCC_CIFR_PLL2RDYF_Pos                   (9U)
+#define RCC_CIFR_PLL2RDYF_Msk                   (0x1UL << RCC_CIFR_PLL2RDYF_Pos)      /*!< 0x00000200 */
+#define RCC_CIFR_PLL2RDYF                       RCC_CIFR_PLL2RDYF_Msk                /*!< PLL2 ready interrupt flag */
+#define RCC_CIFR_PLL3RDYF_Pos                   (10U)
+#define RCC_CIFR_PLL3RDYF_Msk                   (0x1UL << RCC_CIFR_PLL3RDYF_Pos)      /*!< 0x00000400 */
+#define RCC_CIFR_PLL3RDYF                       RCC_CIFR_PLL3RDYF_Msk                /*!< PLL3 ready interrupt flag */
+#define RCC_CIFR_PLL4RDYF_Pos                   (11U)
+#define RCC_CIFR_PLL4RDYF_Msk                   (0x1UL << RCC_CIFR_PLL4RDYF_Pos)      /*!< 0x00000800 */
+#define RCC_CIFR_PLL4RDYF                       RCC_CIFR_PLL4RDYF_Msk                /*!< PLL4 ready interrupt flag */
+#define RCC_CIFR_LSECSSF_Pos                    (16U)
+#define RCC_CIFR_LSECSSF_Msk                    (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00010000 */
+#define RCC_CIFR_LSECSSF                        RCC_CIFR_LSECSSF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_HSECSSF_Pos                    (17U)
+#define RCC_CIFR_HSECSSF_Msk                    (0x1UL << RCC_CIFR_HSECSSF_Pos)       /*!< 0x00020000 */
+#define RCC_CIFR_HSECSSF                        RCC_CIFR_HSECSSF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_WKUPF_Pos                      (24U)
+#define RCC_CIFR_WKUPF_Msk                      (0x1UL << RCC_CIFR_WKUPF_Pos)         /*!< 0x01000000 */
+#define RCC_CIFR_WKUPF                          RCC_CIFR_WKUPF_Msk                   /*!< CPU wake-up from Stop interrupt flag */
+
+/*******************  Bit definition for RCC_CICR register  *******************/
+#define RCC_CICR_LSIRDYC_Pos                    (0U)
+#define RCC_CICR_LSIRDYC_Msk                    (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                        RCC_CICR_LSIRDYC_Msk                 /*!< LSI ready interrupt clear */
+#define RCC_CICR_LSERDYC_Pos                    (1U)
+#define RCC_CICR_LSERDYC_Msk                    (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                        RCC_CICR_LSERDYC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_MSIRDYC_Pos                    (2U)
+#define RCC_CICR_MSIRDYC_Msk                    (0x1UL << RCC_CICR_MSIRDYC_Pos)       /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                        RCC_CICR_MSIRDYC_Msk                 /*!< MSI ready interrupt clear */
+#define RCC_CICR_HSIRDYC_Pos                    (3U)
+#define RCC_CICR_HSIRDYC_Msk                    (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                        RCC_CICR_HSIRDYC_Msk                 /*!< HSI ready interrupt clear */
+#define RCC_CICR_HSERDYC_Pos                    (4U)
+#define RCC_CICR_HSERDYC_Msk                    (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                        RCC_CICR_HSERDYC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_PLL1RDYC_Pos                   (8U)
+#define RCC_CICR_PLL1RDYC_Msk                   (0x1UL << RCC_CICR_PLL1RDYC_Pos)      /*!< 0x00000100 */
+#define RCC_CICR_PLL1RDYC                       RCC_CICR_PLL1RDYC_Msk                /*!< PLL1 ready interrupt clear */
+#define RCC_CICR_PLL2RDYC_Pos                   (9U)
+#define RCC_CICR_PLL2RDYC_Msk                   (0x1UL << RCC_CICR_PLL2RDYC_Pos)      /*!< 0x00000200 */
+#define RCC_CICR_PLL2RDYC                       RCC_CICR_PLL2RDYC_Msk                /*!< PLL2 ready interrupt clear */
+#define RCC_CICR_PLL3RDYC_Pos                   (10U)
+#define RCC_CICR_PLL3RDYC_Msk                   (0x1UL << RCC_CICR_PLL3RDYC_Pos)      /*!< 0x00000400 */
+#define RCC_CICR_PLL3RDYC                       RCC_CICR_PLL3RDYC_Msk                /*!< PLL3 ready interrupt clear */
+#define RCC_CICR_PLL4RDYC_Pos                   (11U)
+#define RCC_CICR_PLL4RDYC_Msk                   (0x1UL << RCC_CICR_PLL4RDYC_Pos)      /*!< 0x00000800 */
+#define RCC_CICR_PLL4RDYC                       RCC_CICR_PLL4RDYC_Msk                /*!< PLL4 ready interrupt clear */
+#define RCC_CICR_LSECSSC_Pos                    (16U)
+#define RCC_CICR_LSECSSC_Msk                    (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00010000 */
+#define RCC_CICR_LSECSSC                        RCC_CICR_LSECSSC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_HSECSSC_Pos                    (17U)
+#define RCC_CICR_HSECSSC_Msk                    (0x1UL << RCC_CICR_HSECSSC_Pos)       /*!< 0x00020000 */
+#define RCC_CICR_HSECSSC                        RCC_CICR_HSECSSC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_WKUPFC_Pos                     (24U)
+#define RCC_CICR_WKUPFC_Msk                     (0x1UL << RCC_CICR_WKUPFC_Pos)        /*!< 0x01000000 */
+#define RCC_CICR_WKUPFC                         RCC_CICR_WKUPFC_Msk                  /*!< CPU wake-up ready interrupt clear */
+
+/******************  Bit definition for RCC_CCIPR1 register  ******************/
+#define RCC_CCIPR1_ADF1SEL_Pos                  (0U)
+#define RCC_CCIPR1_ADF1SEL_Msk                  (0x7UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR1_ADF1SEL                      RCC_CCIPR1_ADF1SEL_Msk                            /*!< Source selection for the ADF1 kernel clock */
+#define RCC_CCIPR1_ADF1SEL_0                    (0x1UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR1_ADF1SEL_1                    (0x2UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR1_ADF1SEL_2                    (0x4UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR1_ADC12SEL_Pos                 (4U)
+#define RCC_CCIPR1_ADC12SEL_Msk                 (0x7UL << RCC_CCIPR1_ADC12SEL_Pos)                 /*!< 0x00000070 */
+#define RCC_CCIPR1_ADC12SEL                     RCC_CCIPR1_ADC12SEL_Msk                           /*!< Source selection for the ADC12 kernel clock */
+#define RCC_CCIPR1_ADC12SEL_0                   (0x1UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR1_ADC12SEL_1                   (0x2UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR1_ADC12SEL_2                   (0x4UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000040 */
+#define RCC_CCIPR1_ADCPRE_Pos                   (8U)
+#define RCC_CCIPR1_ADCPRE_Msk                   (0xFFUL << RCC_CCIPR1_ADCPRE_Pos)                  /*!< 0x0000FF00 */
+#define RCC_CCIPR1_ADCPRE                       RCC_CCIPR1_ADCPRE_Msk                             /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */
+#define RCC_CCIPR1_ADCPRE_0                     (0x1UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR1_ADCPRE_1                     (0x2UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR1_ADCPRE_2                     (0x4UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000400 */
+#define RCC_CCIPR1_ADCPRE_3                     (0x8UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000800 */
+#define RCC_CCIPR1_ADCPRE_4                     (0x10UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR1_ADCPRE_5                     (0x20UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR1_ADCPRE_6                     (0x40UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR1_ADCPRE_7                     (0x80UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR1_DCMIPPSEL_Pos                (20U)
+#define RCC_CCIPR1_DCMIPPSEL_Msk                (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos)                /*!< 0x00300000 */
+#define RCC_CCIPR1_DCMIPPSEL                    RCC_CCIPR1_DCMIPPSEL_Msk                          /*!< Source selection for the DCMIPP kernel clock */
+#define RCC_CCIPR1_DCMIPPSEL_0                  (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00100000 */
+#define RCC_CCIPR1_DCMIPPSEL_1                  (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00200000 */
+
+/******************  Bit definition for RCC_CCIPR2 register  ******************/
+#define RCC_CCIPR2_ETH1PTPSEL_Pos               (0U)
+#define RCC_CCIPR2_ETH1PTPSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000003 */
+#define RCC_CCIPR2_ETH1PTPSEL                   RCC_CCIPR2_ETH1PTPSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1PTPSEL_0                 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR2_ETH1PTPSEL_1                 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR2_ETH1PTPDIV_Pos               (4U)
+#define RCC_CCIPR2_ETH1PTPDIV_Msk               (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos)               /*!< 0x000000F0 */
+#define RCC_CCIPR2_ETH1PTPDIV                   RCC_CCIPR2_ETH1PTPDIV_Msk                         /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */
+#define RCC_CCIPR2_ETH1PTPDIV_0                 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR2_ETH1PTPDIV_1                 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR2_ETH1PTPDIV_2                 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR2_ETH1PTPDIV_3                 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000080 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos           (8U)
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk           (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos)           /*!< 0x00000100 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK               RCC_CCIPR2_ETH1PWRDOWNACK_Msk                     /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1CLKSEL_Pos               (12U)
+#define RCC_CCIPR2_ETH1CLKSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR2_ETH1CLKSEL                   RCC_CCIPR2_ETH1CLKSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1CLKSEL_0                 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR2_ETH1CLKSEL_1                 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR2_ETH1SEL_Pos                  (16U)
+#define RCC_CCIPR2_ETH1SEL_Msk                  (0x7UL << RCC_CCIPR2_ETH1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR2_ETH1SEL                      RCC_CCIPR2_ETH1SEL_Msk                            /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1SEL_0                    (0x1UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR2_ETH1SEL_1                    (0x2UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR2_ETH1SEL_2                    (0x4UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL_Pos            (20U)
+#define RCC_CCIPR2_ETH1REFCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos)            /*!< 0x00100000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL                RCC_CCIPR2_ETH1REFCLKSEL_Msk                      /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos            (24U)
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR2_ETH1GTXCLKSEL                RCC_CCIPR2_ETH1GTXCLKSEL_Msk                      /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR3 register  ******************/
+#define RCC_CCIPR3_FDCANSEL_Pos                 (0U)
+#define RCC_CCIPR3_FDCANSEL_Msk                 (0x3UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR3_FDCANSEL                     RCC_CCIPR3_FDCANSEL_Msk                           /*!< Source selection for the FDCAN kernel clock */
+#define RCC_CCIPR3_FDCANSEL_0                   (0x1UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR3_FDCANSEL_1                   (0x2UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR3_FMCSEL_Pos                   (4U)
+#define RCC_CCIPR3_FMCSEL_Msk                   (0x3UL << RCC_CCIPR3_FMCSEL_Pos)                   /*!< 0x00000030 */
+#define RCC_CCIPR3_FMCSEL                       RCC_CCIPR3_FMCSEL_Msk                             /*!< Source selection for the FMC kernel clock */
+#define RCC_CCIPR3_FMCSEL_0                     (0x1UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000010 */
+#define RCC_CCIPR3_FMCSEL_1                     (0x2UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000020 */
+#define RCC_CCIPR3_DFTSEL_Pos                   (8U)
+#define RCC_CCIPR3_DFTSEL_Msk                   (0x1UL << RCC_CCIPR3_DFTSEL_Pos)                   /*!< 0x00000100 */
+#define RCC_CCIPR3_DFTSEL                       RCC_CCIPR3_DFTSEL_Msk                             /*!< Source selection for the DFT kernel clock */
+
+/******************  Bit definition for RCC_CCIPR4 register  ******************/
+#define RCC_CCIPR4_I2C1SEL_Pos                  (0U)
+#define RCC_CCIPR4_I2C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR4_I2C1SEL                      RCC_CCIPR4_I2C1SEL_Msk                            /*!< Source selection for the I2C1 kernel clock */
+#define RCC_CCIPR4_I2C1SEL_0                    (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR4_I2C1SEL_1                    (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR4_I2C1SEL_2                    (0x4UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR4_I2C2SEL_Pos                  (4U)
+#define RCC_CCIPR4_I2C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C2SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR4_I2C2SEL                      RCC_CCIPR4_I2C2SEL_Msk                            /*!< Source selection for the I2C2 kernel clock */
+#define RCC_CCIPR4_I2C2SEL_0                    (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR4_I2C2SEL_1                    (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR4_I2C2SEL_2                    (0x4UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR4_I2C3SEL_Pos                  (8U)
+#define RCC_CCIPR4_I2C3SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C3SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR4_I2C3SEL                      RCC_CCIPR4_I2C3SEL_Msk                            /*!< Source selection for the I2C3 kernel clock */
+#define RCC_CCIPR4_I2C3SEL_0                    (0x1UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR4_I2C3SEL_1                    (0x2UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR4_I2C3SEL_2                    (0x4UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR4_I2C4SEL_Pos                  (12U)
+#define RCC_CCIPR4_I2C4SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C4SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR4_I2C4SEL                      RCC_CCIPR4_I2C4SEL_Msk                            /*!< Source selection for the I2C4 kernel clock */
+#define RCC_CCIPR4_I2C4SEL_0                    (0x1UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR4_I2C4SEL_1                    (0x2UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR4_I2C4SEL_2                    (0x4UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR4_I3C1SEL_Pos                  (16U)
+#define RCC_CCIPR4_I3C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR4_I3C1SEL                      RCC_CCIPR4_I3C1SEL_Msk                            /*!< Source selection for the I3C1 kernel clock */
+#define RCC_CCIPR4_I3C1SEL_0                    (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR4_I3C1SEL_1                    (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR4_I3C1SEL_2                    (0x4UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR4_I3C2SEL_Pos                  (20U)
+#define RCC_CCIPR4_I3C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C2SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR4_I3C2SEL                      RCC_CCIPR4_I3C2SEL_Msk                            /*!< Source selection for the I3C2 kernel clock */
+#define RCC_CCIPR4_I3C2SEL_0                    (0x1UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR4_I3C2SEL_1                    (0x2UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR4_I3C2SEL_2                    (0x4UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR4_LTDCSEL_Pos                  (24U)
+#define RCC_CCIPR4_LTDCSEL_Msk                  (0x3UL << RCC_CCIPR4_LTDCSEL_Pos)                  /*!< 0x03000000 */
+#define RCC_CCIPR4_LTDCSEL                      RCC_CCIPR4_LTDCSEL_Msk                            /*!< Source selection for the LTDC kernel clock */
+#define RCC_CCIPR4_LTDCSEL_0                    (0x1UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR4_LTDCSEL_1                    (0x2UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x02000000 */
+
+/******************  Bit definition for RCC_CCIPR5 register  ******************/
+#define RCC_CCIPR5_MCO1SEL_Pos                  (0U)
+#define RCC_CCIPR5_MCO1SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR5_MCO1SEL                      RCC_CCIPR5_MCO1SEL_Msk                            /*!< Source selection for the MCO1 kernel clock */
+#define RCC_CCIPR5_MCO1SEL_0                    (0x1UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR5_MCO1SEL_1                    (0x2UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR5_MCO1SEL_2                    (0x4UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR5_MCO1PRE_Pos                  (4U)
+#define RCC_CCIPR5_MCO1PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO1PRE_Pos)                  /*!< 0x000000F0 */
+#define RCC_CCIPR5_MCO1PRE                      RCC_CCIPR5_MCO1PRE_Msk                            /*!< MCO1 Kernel clock divider selection (for clock MCO1) */
+#define RCC_CCIPR5_MCO1PRE_0                    (0x1UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR5_MCO1PRE_1                    (0x2UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR5_MCO1PRE_2                    (0x4UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR5_MCO1PRE_3                    (0x8UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000080 */
+#define RCC_CCIPR5_MCO2SEL_Pos                  (8U)
+#define RCC_CCIPR5_MCO2SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR5_MCO2SEL                      RCC_CCIPR5_MCO2SEL_Msk                            /*!< Source selection for the MCO2 kernel clock */
+#define RCC_CCIPR5_MCO2SEL_0                    (0x1UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR5_MCO2SEL_1                    (0x2UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR5_MCO2SEL_2                    (0x4UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR5_MCO2PRE_Pos                  (12U)
+#define RCC_CCIPR5_MCO2PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO2PRE_Pos)                  /*!< 0x0000F000 */
+#define RCC_CCIPR5_MCO2PRE                      RCC_CCIPR5_MCO2PRE_Msk                            /*!< MCO2 Kernel clock divider selection (for clock MCO2) */
+#define RCC_CCIPR5_MCO2PRE_0                    (0x1UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR5_MCO2PRE_1                    (0x2UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR5_MCO2PRE_2                    (0x4UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR5_MCO2PRE_3                    (0x8UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00008000 */
+#define RCC_CCIPR5_MDF1SEL_Pos                  (16U)
+#define RCC_CCIPR5_MDF1SEL_Msk                  (0x7UL << RCC_CCIPR5_MDF1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR5_MDF1SEL                      RCC_CCIPR5_MDF1SEL_Msk                            /*!< Source selection for the MDF1 kernel clock */
+#define RCC_CCIPR5_MDF1SEL_0                    (0x1UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR5_MDF1SEL_1                    (0x2UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR5_MDF1SEL_2                    (0x4UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00040000 */
+
+/******************  Bit definition for RCC_CCIPR6 register  ******************/
+#define RCC_CCIPR6_XSPI1SEL_Pos                 (0U)
+#define RCC_CCIPR6_XSPI1SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR6_XSPI1SEL                     RCC_CCIPR6_XSPI1SEL_Msk                           /*!< Source selection for the XSPI1 kernel clock */
+#define RCC_CCIPR6_XSPI1SEL_0                   (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR6_XSPI1SEL_1                   (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR6_XSPI2SEL_Pos                 (4U)
+#define RCC_CCIPR6_XSPI2SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos)                 /*!< 0x00000030 */
+#define RCC_CCIPR6_XSPI2SEL                     RCC_CCIPR6_XSPI2SEL_Msk                           /*!< Source selection for the XSPI2 kernel clock */
+#define RCC_CCIPR6_XSPI2SEL_0                   (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR6_XSPI2SEL_1                   (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR6_XSPI3SEL_Pos                 (8U)
+#define RCC_CCIPR6_XSPI3SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos)                 /*!< 0x00000300 */
+#define RCC_CCIPR6_XSPI3SEL                     RCC_CCIPR6_XSPI3SEL_Msk                           /*!< Source selection for the XSPI3 kernel clock */
+#define RCC_CCIPR6_XSPI3SEL_0                   (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000100 */
+#define RCC_CCIPR6_XSPI3SEL_1                   (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000200 */
+#define RCC_CCIPR6_OTGPHY1SEL_Pos               (12U)
+#define RCC_CCIPR6_OTGPHY1SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR6_OTGPHY1SEL                   RCC_CCIPR6_OTGPHY1SEL_Msk                         /*!< Source selection for the OTGPHY1 kernel clock */
+#define RCC_CCIPR6_OTGPHY1SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR6_OTGPHY1SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos          (16U)
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos)          /*!< 0x00010000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL              RCC_CCIPR6_OTGPHY1CKREFSEL_Msk                    /*!< Set and reset by software */
+#define RCC_CCIPR6_OTGPHY2SEL_Pos               (20U)
+#define RCC_CCIPR6_OTGPHY2SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos)               /*!< 0x00300000 */
+#define RCC_CCIPR6_OTGPHY2SEL                   RCC_CCIPR6_OTGPHY2SEL_Msk                         /*!< Source selection for the OTGPHY2 kernel clock */
+#define RCC_CCIPR6_OTGPHY2SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR6_OTGPHY2SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos          (24U)
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL              RCC_CCIPR6_OTGPHY2CKREFSEL_Msk                    /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR7 register  ******************/
+#define RCC_CCIPR7_PERSEL_Pos                   (0U)
+#define RCC_CCIPR7_PERSEL_Msk                   (0x7UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000007 */
+#define RCC_CCIPR7_PERSEL                       RCC_CCIPR7_PERSEL_Msk                             /*!< Source selection for the PER kernel clock */
+#define RCC_CCIPR7_PERSEL_0                     (0x1UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000001 */
+#define RCC_CCIPR7_PERSEL_1                     (0x2UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000002 */
+#define RCC_CCIPR7_PERSEL_2                     (0x4UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000004 */
+#define RCC_CCIPR7_PSSISEL_Pos                  (4U)
+#define RCC_CCIPR7_PSSISEL_Msk                  (0x3UL << RCC_CCIPR7_PSSISEL_Pos)                  /*!< 0x00000030 */
+#define RCC_CCIPR7_PSSISEL                      RCC_CCIPR7_PSSISEL_Msk                            /*!< Source selection for the PSSI kernel clock */
+#define RCC_CCIPR7_PSSISEL_0                    (0x1UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR7_PSSISEL_1                    (0x2UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR7_RTCSEL_Pos                   (8U)
+#define RCC_CCIPR7_RTCSEL_Msk                   (0x3UL << RCC_CCIPR7_RTCSEL_Pos)                   /*!< 0x00000300 */
+#define RCC_CCIPR7_RTCSEL                       RCC_CCIPR7_RTCSEL_Msk                             /*!< Source selection for the RTC kernel clock */
+#define RCC_CCIPR7_RTCSEL_0                     (0x1UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR7_RTCSEL_1                     (0x2UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR7_RTCPRE_Pos                   (12U)
+#define RCC_CCIPR7_RTCPRE_Msk                   (0x3FUL << RCC_CCIPR7_RTCPRE_Pos)                  /*!< 0x0003F000 */
+#define RCC_CCIPR7_RTCPRE                       RCC_CCIPR7_RTCPRE_Msk                             /*!< RTC OSC clock divider selection (for clock hse_ck) */
+#define RCC_CCIPR7_RTCPRE_0                     (0x1UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR7_RTCPRE_1                     (0x2UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR7_RTCPRE_2                     (0x4UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR7_RTCPRE_3                     (0x8UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR7_RTCPRE_4                     (0x10UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00010000 */
+#define RCC_CCIPR7_RTCPRE_5                     (0x20UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00020000 */
+#define RCC_CCIPR7_SAI1SEL_Pos                  (20U)
+#define RCC_CCIPR7_SAI1SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI1SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR7_SAI1SEL                      RCC_CCIPR7_SAI1SEL_Msk                            /*!< Source selection for the SAI1 kernel clock */
+#define RCC_CCIPR7_SAI1SEL_0                    (0x1UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR7_SAI1SEL_1                    (0x2UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR7_SAI1SEL_2                    (0x4UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR7_SAI2SEL_Pos                  (24U)
+#define RCC_CCIPR7_SAI2SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI2SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR7_SAI2SEL                      RCC_CCIPR7_SAI2SEL_Msk                            /*!< Source selection for the SAI2 kernel clock */
+#define RCC_CCIPR7_SAI2SEL_0                    (0x1UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR7_SAI2SEL_1                    (0x2UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR7_SAI2SEL_2                    (0x4UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x04000000 */
+
+/******************  Bit definition for RCC_CCIPR8 register  ******************/
+#define RCC_CCIPR8_SDMMC1SEL_Pos                (0U)
+#define RCC_CCIPR8_SDMMC1SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000003 */
+#define RCC_CCIPR8_SDMMC1SEL                    RCC_CCIPR8_SDMMC1SEL_Msk                          /*!< Source selection for the SDMMC1 kernel clock */
+#define RCC_CCIPR8_SDMMC1SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR8_SDMMC1SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR8_SDMMC2SEL_Pos                (4U)
+#define RCC_CCIPR8_SDMMC2SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos)                /*!< 0x00000030 */
+#define RCC_CCIPR8_SDMMC2SEL                    RCC_CCIPR8_SDMMC2SEL_Msk                          /*!< Source selection for the SDMMC2 kernel clock */
+#define RCC_CCIPR8_SDMMC2SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000010 */
+#define RCC_CCIPR8_SDMMC2SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000020 */
+
+/******************  Bit definition for RCC_CCIPR9 register  ******************/
+#define RCC_CCIPR9_SPDIFRX1SEL_Pos              (0U)
+#define RCC_CCIPR9_SPDIFRX1SEL_Msk              (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000007 */
+#define RCC_CCIPR9_SPDIFRX1SEL                  RCC_CCIPR9_SPDIFRX1SEL_Msk                        /*!< Source selection for the SPDIFRX1 kernel clock */
+#define RCC_CCIPR9_SPDIFRX1SEL_0                (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000001 */
+#define RCC_CCIPR9_SPDIFRX1SEL_1                (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000002 */
+#define RCC_CCIPR9_SPDIFRX1SEL_2                (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000004 */
+#define RCC_CCIPR9_SPI1SEL_Pos                  (4U)
+#define RCC_CCIPR9_SPI1SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI1SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR9_SPI1SEL                      RCC_CCIPR9_SPI1SEL_Msk                            /*!< Source selection for the SPI1 kernel clock */
+#define RCC_CCIPR9_SPI1SEL_0                    (0x1UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR9_SPI1SEL_1                    (0x2UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR9_SPI1SEL_2                    (0x4UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR9_SPI2SEL_Pos                  (8U)
+#define RCC_CCIPR9_SPI2SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR9_SPI2SEL                      RCC_CCIPR9_SPI2SEL_Msk                            /*!< Source selection for the SPI2 kernel clock */
+#define RCC_CCIPR9_SPI2SEL_0                    (0x1UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR9_SPI2SEL_1                    (0x2UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR9_SPI2SEL_2                    (0x4UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR9_SPI3SEL_Pos                  (12U)
+#define RCC_CCIPR9_SPI3SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI3SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR9_SPI3SEL                      RCC_CCIPR9_SPI3SEL_Msk                            /*!< Source selection for the SPI3 kernel clock */
+#define RCC_CCIPR9_SPI3SEL_0                    (0x1UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR9_SPI3SEL_1                    (0x2UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR9_SPI3SEL_2                    (0x4UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR9_SPI4SEL_Pos                  (16U)
+#define RCC_CCIPR9_SPI4SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI4SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR9_SPI4SEL                      RCC_CCIPR9_SPI4SEL_Msk                            /*!< Source selection for the SPI4 kernel clock */
+#define RCC_CCIPR9_SPI4SEL_0                    (0x1UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR9_SPI4SEL_1                    (0x2UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR9_SPI4SEL_2                    (0x4UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR9_SPI5SEL_Pos                  (20U)
+#define RCC_CCIPR9_SPI5SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI5SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR9_SPI5SEL                      RCC_CCIPR9_SPI5SEL_Msk                            /*!< Source selection for the SPI5 kernel clock */
+#define RCC_CCIPR9_SPI5SEL_0                    (0x1UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR9_SPI5SEL_1                    (0x2UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR9_SPI5SEL_2                    (0x4UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR9_SPI6SEL_Pos                  (24U)
+#define RCC_CCIPR9_SPI6SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI6SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR9_SPI6SEL                      RCC_CCIPR9_SPI6SEL_Msk                            /*!< Source selection for the SPI6 kernel clock */
+#define RCC_CCIPR9_SPI6SEL_0                    (0x1UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR9_SPI6SEL_1                    (0x2UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR9_SPI6SEL_2                    (0x4UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR12 register  ******************/
+#define RCC_CCIPR12_LPTIM1SEL_Pos               (8U)
+#define RCC_CCIPR12_LPTIM1SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR12_LPTIM1SEL                   RCC_CCIPR12_LPTIM1SEL_Msk                         /*!< Source selection for the LPTIM1 kernel clock */
+#define RCC_CCIPR12_LPTIM1SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR12_LPTIM1SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR12_LPTIM1SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR12_LPTIM2SEL_Pos               (12U)
+#define RCC_CCIPR12_LPTIM2SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos)               /*!< 0x00007000 */
+#define RCC_CCIPR12_LPTIM2SEL                   RCC_CCIPR12_LPTIM2SEL_Msk                         /*!< Source selection for the LPTIM2 kernel clock */
+#define RCC_CCIPR12_LPTIM2SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR12_LPTIM2SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR12_LPTIM2SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00004000 */
+#define RCC_CCIPR12_LPTIM3SEL_Pos               (16U)
+#define RCC_CCIPR12_LPTIM3SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos)               /*!< 0x00070000 */
+#define RCC_CCIPR12_LPTIM3SEL                   RCC_CCIPR12_LPTIM3SEL_Msk                         /*!< Source selection for the LPTIM3 kernel clock */
+#define RCC_CCIPR12_LPTIM3SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00010000 */
+#define RCC_CCIPR12_LPTIM3SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00020000 */
+#define RCC_CCIPR12_LPTIM3SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00040000 */
+#define RCC_CCIPR12_LPTIM4SEL_Pos               (20U)
+#define RCC_CCIPR12_LPTIM4SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR12_LPTIM4SEL                   RCC_CCIPR12_LPTIM4SEL_Msk                         /*!< Source selection for the LPTIM4 kernel clock */
+#define RCC_CCIPR12_LPTIM4SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR12_LPTIM4SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR12_LPTIM4SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR12_LPTIM5SEL_Pos               (24U)
+#define RCC_CCIPR12_LPTIM5SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos)               /*!< 0x07000000 */
+#define RCC_CCIPR12_LPTIM5SEL                   RCC_CCIPR12_LPTIM5SEL_Msk                         /*!< Source selection for the LPTIM5 kernel clock */
+#define RCC_CCIPR12_LPTIM5SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x01000000 */
+#define RCC_CCIPR12_LPTIM5SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x02000000 */
+#define RCC_CCIPR12_LPTIM5SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR13 register  ******************/
+#define RCC_CCIPR13_USART1SEL_Pos               (0U)
+#define RCC_CCIPR13_USART1SEL_Msk               (0x7UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000007 */
+#define RCC_CCIPR13_USART1SEL                   RCC_CCIPR13_USART1SEL_Msk                         /*!< Source selection for the USART1 kernel clock */
+#define RCC_CCIPR13_USART1SEL_0                 (0x1UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR13_USART1SEL_1                 (0x2UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR13_USART1SEL_2                 (0x4UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000004 */
+#define RCC_CCIPR13_USART2SEL_Pos               (4U)
+#define RCC_CCIPR13_USART2SEL_Msk               (0x7UL << RCC_CCIPR13_USART2SEL_Pos)               /*!< 0x00000070 */
+#define RCC_CCIPR13_USART2SEL                   RCC_CCIPR13_USART2SEL_Msk                         /*!< Source selection for the USART2 kernel clock */
+#define RCC_CCIPR13_USART2SEL_0                 (0x1UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR13_USART2SEL_1                 (0x2UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR13_USART2SEL_2                 (0x4UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR13_USART3SEL_Pos               (8U)
+#define RCC_CCIPR13_USART3SEL_Msk               (0x7UL << RCC_CCIPR13_USART3SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR13_USART3SEL                   RCC_CCIPR13_USART3SEL_Msk                         /*!< Source selection for the USART3 kernel clock */
+#define RCC_CCIPR13_USART3SEL_0                 (0x1UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR13_USART3SEL_1                 (0x2UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR13_USART3SEL_2                 (0x4UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR13_UART4SEL_Pos                (12U)
+#define RCC_CCIPR13_UART4SEL_Msk                (0x7UL << RCC_CCIPR13_UART4SEL_Pos)                /*!< 0x00007000 */
+#define RCC_CCIPR13_UART4SEL                    RCC_CCIPR13_UART4SEL_Msk                          /*!< Source selection for the UART4 kernel clock */
+#define RCC_CCIPR13_UART4SEL_0                  (0x1UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00001000 */
+#define RCC_CCIPR13_UART4SEL_1                  (0x2UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00002000 */
+#define RCC_CCIPR13_UART4SEL_2                  (0x4UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00004000 */
+#define RCC_CCIPR13_UART5SEL_Pos                (16U)
+#define RCC_CCIPR13_UART5SEL_Msk                (0x7UL << RCC_CCIPR13_UART5SEL_Pos)                /*!< 0x00070000 */
+#define RCC_CCIPR13_UART5SEL                    RCC_CCIPR13_UART5SEL_Msk                          /*!< Source selection for the UART5 kernel clock */
+#define RCC_CCIPR13_UART5SEL_0                  (0x1UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00010000 */
+#define RCC_CCIPR13_UART5SEL_1                  (0x2UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00020000 */
+#define RCC_CCIPR13_UART5SEL_2                  (0x4UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00040000 */
+#define RCC_CCIPR13_USART6SEL_Pos               (20U)
+#define RCC_CCIPR13_USART6SEL_Msk               (0x7UL << RCC_CCIPR13_USART6SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR13_USART6SEL                   RCC_CCIPR13_USART6SEL_Msk                         /*!< Source selection for the USART6 kernel clock */
+#define RCC_CCIPR13_USART6SEL_0                 (0x1UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR13_USART6SEL_1                 (0x2UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR13_USART6SEL_2                 (0x4UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR13_UART7SEL_Pos                (24U)
+#define RCC_CCIPR13_UART7SEL_Msk                (0x7UL << RCC_CCIPR13_UART7SEL_Pos)                /*!< 0x07000000 */
+#define RCC_CCIPR13_UART7SEL                    RCC_CCIPR13_UART7SEL_Msk                          /*!< Source selection for the UART7 kernel clock */
+#define RCC_CCIPR13_UART7SEL_0                  (0x1UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR13_UART7SEL_1                  (0x2UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x02000000 */
+#define RCC_CCIPR13_UART7SEL_2                  (0x4UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x04000000 */
+#define RCC_CCIPR13_UART8SEL_Pos                (28U)
+#define RCC_CCIPR13_UART8SEL_Msk                (0x7UL << RCC_CCIPR13_UART8SEL_Pos)                /*!< 0x70000000 */
+#define RCC_CCIPR13_UART8SEL                    RCC_CCIPR13_UART8SEL_Msk                          /*!< Source selection for the UART8 kernel clock */
+#define RCC_CCIPR13_UART8SEL_0                  (0x1UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x10000000 */
+#define RCC_CCIPR13_UART8SEL_1                  (0x2UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x20000000 */
+#define RCC_CCIPR13_UART8SEL_2                  (0x4UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x40000000 */
+
+/*****************  Bit definition for RCC_CCIPR14 register  ******************/
+#define RCC_CCIPR14_UART9SEL_Pos                (0U)
+#define RCC_CCIPR14_UART9SEL_Msk                (0x7UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000007 */
+#define RCC_CCIPR14_UART9SEL                    RCC_CCIPR14_UART9SEL_Msk                          /*!< Source selection for the UART9 kernel clock */
+#define RCC_CCIPR14_UART9SEL_0                  (0x1UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR14_UART9SEL_1                  (0x2UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR14_UART9SEL_2                  (0x4UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000004 */
+#define RCC_CCIPR14_USART10SEL_Pos              (4U)
+#define RCC_CCIPR14_USART10SEL_Msk              (0x7UL << RCC_CCIPR14_USART10SEL_Pos)              /*!< 0x00000070 */
+#define RCC_CCIPR14_USART10SEL                  RCC_CCIPR14_USART10SEL_Msk                        /*!< Source selection for the USART10 kernel clock */
+#define RCC_CCIPR14_USART10SEL_0                (0x1UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000010 */
+#define RCC_CCIPR14_USART10SEL_1                (0x2UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000020 */
+#define RCC_CCIPR14_USART10SEL_2                (0x4UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000040 */
+#define RCC_CCIPR14_LPUART1SEL_Pos              (8U)
+#define RCC_CCIPR14_LPUART1SEL_Msk              (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos)              /*!< 0x00000700 */
+#define RCC_CCIPR14_LPUART1SEL                  RCC_CCIPR14_LPUART1SEL_Msk                        /*!< Source selection for the LPUART1 kernel clock */
+#define RCC_CCIPR14_LPUART1SEL_0                (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000100 */
+#define RCC_CCIPR14_LPUART1SEL_1                (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000200 */
+#define RCC_CCIPR14_LPUART1SEL_2                (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000400 */
+
+/*****************  Bit definition for RCC_MISCRSTR register  *****************/
+#define RCC_MISCRSTR_DBGRST_Pos                 (0U)
+#define RCC_MISCRSTR_DBGRST_Msk                 (0x1UL << RCC_MISCRSTR_DBGRST_Pos)    /*!< 0x00000001 */
+#define RCC_MISCRSTR_DBGRST                     RCC_MISCRSTR_DBGRST_Msk              /*!< DBG reset */
+#define RCC_MISCRSTR_XSPIPHY1RST_Pos            (4U)
+#define RCC_MISCRSTR_XSPIPHY1RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */
+#define RCC_MISCRSTR_XSPIPHY1RST                RCC_MISCRSTR_XSPIPHY1RST_Msk         /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTR_XSPIPHY2RST_Pos            (5U)
+#define RCC_MISCRSTR_XSPIPHY2RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */
+#define RCC_MISCRSTR_XSPIPHY2RST                RCC_MISCRSTR_XSPIPHY2RST_Msk         /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTR_SDMMC1DLLRST_Pos           (7U)
+#define RCC_MISCRSTR_SDMMC1DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos)  /*!< 0x00000080 */
+#define RCC_MISCRSTR_SDMMC1DLLRST               RCC_MISCRSTR_SDMMC1DLLRST_Msk        /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTR_SDMMC2DLLRST_Pos           (8U)
+#define RCC_MISCRSTR_SDMMC2DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos)  /*!< 0x00000100 */
+#define RCC_MISCRSTR_SDMMC2DLLRST               RCC_MISCRSTR_SDMMC2DLLRST_Msk        /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTR register  ******************/
+#define RCC_MEMRSTR_AXISRAM3RST_Pos             (0U)
+#define RCC_MEMRSTR_AXISRAM3RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */
+#define RCC_MEMRSTR_AXISRAM3RST                 RCC_MEMRSTR_AXISRAM3RST_Msk          /*!< AXISRAM3 reset */
+#define RCC_MEMRSTR_AXISRAM4RST_Pos             (1U)
+#define RCC_MEMRSTR_AXISRAM4RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */
+#define RCC_MEMRSTR_AXISRAM4RST                 RCC_MEMRSTR_AXISRAM4RST_Msk          /*!< AXISRAM4 reset */
+#define RCC_MEMRSTR_AXISRAM5RST_Pos             (2U)
+#define RCC_MEMRSTR_AXISRAM5RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */
+#define RCC_MEMRSTR_AXISRAM5RST                 RCC_MEMRSTR_AXISRAM5RST_Msk          /*!< AXISRAM5 reset */
+#define RCC_MEMRSTR_AXISRAM6RST_Pos             (3U)
+#define RCC_MEMRSTR_AXISRAM6RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */
+#define RCC_MEMRSTR_AXISRAM6RST                 RCC_MEMRSTR_AXISRAM6RST_Msk          /*!< AXISRAM6 reset */
+#define RCC_MEMRSTR_AHBSRAM1RST_Pos             (4U)
+#define RCC_MEMRSTR_AHBSRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */
+#define RCC_MEMRSTR_AHBSRAM1RST                 RCC_MEMRSTR_AHBSRAM1RST_Msk          /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTR_AHBSRAM2RST_Pos             (5U)
+#define RCC_MEMRSTR_AHBSRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */
+#define RCC_MEMRSTR_AHBSRAM2RST                 RCC_MEMRSTR_AHBSRAM2RST_Msk          /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTR_AXISRAM1RST_Pos             (7U)
+#define RCC_MEMRSTR_AXISRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */
+#define RCC_MEMRSTR_AXISRAM1RST                 RCC_MEMRSTR_AXISRAM1RST_Msk          /*!< AXISRAM1 reset */
+#define RCC_MEMRSTR_AXISRAM2RST_Pos             (8U)
+#define RCC_MEMRSTR_AXISRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */
+#define RCC_MEMRSTR_AXISRAM2RST                 RCC_MEMRSTR_AXISRAM2RST_Msk          /*!< AXISRAM2 reset */
+#define RCC_MEMRSTR_FLEXRAMRST_Pos              (9U)
+#define RCC_MEMRSTR_FLEXRAMRST_Msk              (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTR_FLEXRAMRST                  RCC_MEMRSTR_FLEXRAMRST_Msk           /*!< FLEXRAM reset */
+#define RCC_MEMRSTR_CACHEAXIRAMRST_Pos          (10U)
+#define RCC_MEMRSTR_CACHEAXIRAMRST_Msk          (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos)   /*!< 0x00000400 */
+#define RCC_MEMRSTR_CACHEAXIRAMRST              RCC_MEMRSTR_CACHEAXIRAMRST_Msk       /*!< CACHEAXIRAM reset */
+#define RCC_MEMRSTR_VENCRAMRST_Pos              (11U)
+#define RCC_MEMRSTR_VENCRAMRST_Msk              (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTR_VENCRAMRST                  RCC_MEMRSTR_VENCRAMRST_Msk           /*!< VENCRAM reset */
+#define RCC_MEMRSTR_BOOTROMRST_Pos              (12U)
+#define RCC_MEMRSTR_BOOTROMRST_Msk              (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTR_BOOTROMRST                  RCC_MEMRSTR_BOOTROMRST_Msk           /*!< Boot ROM reset */
+
+/*****************  Bit definition for RCC_AHB1RSTR register  *****************/
+#define RCC_AHB1RSTR_GPDMA1RST_Pos              (4U)
+#define RCC_AHB1RSTR_GPDMA1RST_Msk              (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPDMA1RST                  RCC_AHB1RSTR_GPDMA1RST_Msk           /*!< GPDMA1 reset */
+#define RCC_AHB1RSTR_ADC12RST_Pos               (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk               (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                   RCC_AHB1RSTR_ADC12RST_Msk            /*!< ADC12 reset */
+
+/*****************  Bit definition for RCC_AHB2RSTR register  *****************/
+#define RCC_AHB2RSTR_RAMCFGRST_Pos              (12U)
+#define RCC_AHB2RSTR_RAMCFGRST_Msk              (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_RAMCFGRST                  RCC_AHB2RSTR_RAMCFGRST_Msk           /*!< RAMCFG reset */
+#define RCC_AHB2RSTR_MDF1RST_Pos                (16U)
+#define RCC_AHB2RSTR_MDF1RST_Msk                (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2RSTR_MDF1RST                    RCC_AHB2RSTR_MDF1RST_Msk             /*!< MDF1 reset */
+#define RCC_AHB2RSTR_ADF1RST_Pos                (17U)
+#define RCC_AHB2RSTR_ADF1RST_Msk                (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2RSTR_ADF1RST                    RCC_AHB2RSTR_ADF1RST_Msk             /*!< ADF1 reset */
+
+/*****************  Bit definition for RCC_AHB3RSTR register  *****************/
+#define RCC_AHB3RSTR_RNGRST_Pos                 (0U)
+#define RCC_AHB3RSTR_RNGRST_Msk                 (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3RSTR_RNGRST                     RCC_AHB3RSTR_RNGRST_Msk              /*!< RNG reset */
+#define RCC_AHB3RSTR_HASHRST_Pos                (1U)
+#define RCC_AHB3RSTR_HASHRST_Msk                (0x1UL << RCC_AHB3RSTR_HASHRST_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3RSTR_HASHRST                    RCC_AHB3RSTR_HASHRST_Msk             /*!< HASH reset */
+#define RCC_AHB3RSTR_PKARST_Pos                 (8U)
+#define RCC_AHB3RSTR_PKARST_Msk                 (0x1UL << RCC_AHB3RSTR_PKARST_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3RSTR_PKARST                     RCC_AHB3RSTR_PKARST_Msk              /*!< PKA reset */
+#define RCC_AHB3RSTR_IACRST_Pos                 (10U)
+#define RCC_AHB3RSTR_IACRST_Msk                 (0x1UL << RCC_AHB3RSTR_IACRST_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3RSTR_IACRST                     RCC_AHB3RSTR_IACRST_Msk              /*!< IAC reset */
+
+/*****************  Bit definition for RCC_AHB4RSTR register  *****************/
+#define RCC_AHB4RSTR_GPIOARST_Pos               (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                   RCC_AHB4RSTR_GPIOARST_Msk            /*!< GPIO A reset */
+#define RCC_AHB4RSTR_GPIOBRST_Pos               (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                   RCC_AHB4RSTR_GPIOBRST_Msk            /*!< GPIO B reset */
+#define RCC_AHB4RSTR_GPIOCRST_Pos               (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                   RCC_AHB4RSTR_GPIOCRST_Msk            /*!< GPIO C reset */
+#define RCC_AHB4RSTR_GPIODRST_Pos               (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                   RCC_AHB4RSTR_GPIODRST_Msk            /*!< GPIO D reset */
+#define RCC_AHB4RSTR_GPIOERST_Pos               (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                   RCC_AHB4RSTR_GPIOERST_Msk            /*!< GPIO E reset */
+#define RCC_AHB4RSTR_GPIOFRST_Pos               (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                   RCC_AHB4RSTR_GPIOFRST_Msk            /*!< GPIO F reset */
+#define RCC_AHB4RSTR_GPIOGRST_Pos               (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                   RCC_AHB4RSTR_GPIOGRST_Msk            /*!< GPIO G reset */
+#define RCC_AHB4RSTR_GPIOHRST_Pos               (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                   RCC_AHB4RSTR_GPIOHRST_Msk            /*!< GPIO H reset */
+#define RCC_AHB4RSTR_GPIONRST_Pos               (13U)
+#define RCC_AHB4RSTR_GPIONRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4RSTR_GPIONRST                   RCC_AHB4RSTR_GPIONRST_Msk            /*!< GPIO N reset */
+#define RCC_AHB4RSTR_GPIOORST_Pos               (14U)
+#define RCC_AHB4RSTR_GPIOORST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4RSTR_GPIOORST                   RCC_AHB4RSTR_GPIOORST_Msk            /*!< GPIO O reset */
+#define RCC_AHB4RSTR_GPIOPRST_Pos               (15U)
+#define RCC_AHB4RSTR_GPIOPRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4RSTR_GPIOPRST                   RCC_AHB4RSTR_GPIOPRST_Msk            /*!< GPIO P reset */
+#define RCC_AHB4RSTR_GPIOQRST_Pos               (16U)
+#define RCC_AHB4RSTR_GPIOQRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4RSTR_GPIOQRST                   RCC_AHB4RSTR_GPIOQRST_Msk            /*!< GPIO Q reset */
+#define RCC_AHB4RSTR_PWRRST_Pos                 (18U)
+#define RCC_AHB4RSTR_PWRRST_Msk                 (0x1UL << RCC_AHB4RSTR_PWRRST_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4RSTR_PWRRST                     RCC_AHB4RSTR_PWRRST_Msk              /*!< PWR reset */
+#define RCC_AHB4RSTR_CRCRST_Pos                 (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                 (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                     RCC_AHB4RSTR_CRCRST_Msk              /*!< CRC reset */
+
+/*****************  Bit definition for RCC_AHB5RSTR register  *****************/
+#define RCC_AHB5RSTR_HPDMA1RST_Pos              (0U)
+#define RCC_AHB5RSTR_HPDMA1RST_Msk              (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTR_HPDMA1RST                  RCC_AHB5RSTR_HPDMA1RST_Msk           /*!< HPDMA1 reset */
+#define RCC_AHB5RSTR_DMA2DRST_Pos               (1U)
+#define RCC_AHB5RSTR_DMA2DRST_Msk               (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5RSTR_DMA2DRST                   RCC_AHB5RSTR_DMA2DRST_Msk            /*!< DMA2D reset */
+#define RCC_AHB5RSTR_JPEGRST_Pos                (3U)
+#define RCC_AHB5RSTR_JPEGRST_Msk                (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5RSTR_JPEGRST                    RCC_AHB5RSTR_JPEGRST_Msk             /*!< JPEG reset */
+#define RCC_AHB5RSTR_FMCRST_Pos                 (4U)
+#define RCC_AHB5RSTR_FMCRST_Msk                 (0x1UL << RCC_AHB5RSTR_FMCRST_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5RSTR_FMCRST                     RCC_AHB5RSTR_FMCRST_Msk              /*!< FMC reset */
+#define RCC_AHB5RSTR_XSPI1RST_Pos               (5U)
+#define RCC_AHB5RSTR_XSPI1RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5RSTR_XSPI1RST                   RCC_AHB5RSTR_XSPI1RST_Msk            /*!< XSPI1 reset */
+#define RCC_AHB5RSTR_PSSIRST_Pos                (6U)
+#define RCC_AHB5RSTR_PSSIRST_Msk                (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5RSTR_PSSIRST                    RCC_AHB5RSTR_PSSIRST_Msk             /*!< PSSI reset */
+#define RCC_AHB5RSTR_SDMMC2RST_Pos              (7U)
+#define RCC_AHB5RSTR_SDMMC2RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTR_SDMMC2RST                  RCC_AHB5RSTR_SDMMC2RST_Msk           /*!< SDMMC2 reset */
+#define RCC_AHB5RSTR_SDMMC1RST_Pos              (8U)
+#define RCC_AHB5RSTR_SDMMC1RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTR_SDMMC1RST                  RCC_AHB5RSTR_SDMMC1RST_Msk           /*!< SDMMC1 reset */
+#define RCC_AHB5RSTR_XSPI2RST_Pos               (12U)
+#define RCC_AHB5RSTR_XSPI2RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5RSTR_XSPI2RST                   RCC_AHB5RSTR_XSPI2RST_Msk            /*!< XSPI2 reset */
+#define RCC_AHB5RSTR_XSPIMRST_Pos               (13U)
+#define RCC_AHB5RSTR_XSPIMRST_Msk               (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5RSTR_XSPIMRST                   RCC_AHB5RSTR_XSPIMRST_Msk            /*!< XSPIM reset */
+#define RCC_AHB5RSTR_XSPI3RST_Pos               (17U)
+#define RCC_AHB5RSTR_XSPI3RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5RSTR_XSPI3RST                   RCC_AHB5RSTR_XSPI3RST_Msk            /*!< XSPI3 reset */
+#define RCC_AHB5RSTR_GFXMMURST_Pos              (19U)
+#define RCC_AHB5RSTR_GFXMMURST_Msk              (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTR_GFXMMURST                  RCC_AHB5RSTR_GFXMMURST_Msk           /*!< GFXMMU reset */
+#define RCC_AHB5RSTR_GPU2DRST_Pos               (20U)
+#define RCC_AHB5RSTR_GPU2DRST_Msk               (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5RSTR_GPU2DRST                   RCC_AHB5RSTR_GPU2DRST_Msk            /*!< GPU2D reset */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos          (23U)
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST              RCC_AHB5RSTR_OTG1PHYCTLRST_Msk       /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos          (24U)
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST              RCC_AHB5RSTR_OTG2PHYCTLRST_Msk       /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTR_ETH1RST_Pos                (25U)
+#define RCC_AHB5RSTR_ETH1RST_Msk                (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5RSTR_ETH1RST                    RCC_AHB5RSTR_ETH1RST_Msk             /*!< ETH1 reset */
+#define RCC_AHB5RSTR_OTG1RST_Pos                (26U)
+#define RCC_AHB5RSTR_OTG1RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5RSTR_OTG1RST                    RCC_AHB5RSTR_OTG1RST_Msk             /*!< OTG1 reset */
+#define RCC_AHB5RSTR_OTGPHY1RST_Pos             (27U)
+#define RCC_AHB5RSTR_OTGPHY1RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */
+#define RCC_AHB5RSTR_OTGPHY1RST                 RCC_AHB5RSTR_OTGPHY1RST_Msk          /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTR_OTGPHY2RST_Pos             (28U)
+#define RCC_AHB5RSTR_OTGPHY2RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */
+#define RCC_AHB5RSTR_OTGPHY2RST                 RCC_AHB5RSTR_OTGPHY2RST_Msk          /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTR_OTG2RST_Pos                (29U)
+#define RCC_AHB5RSTR_OTG2RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5RSTR_OTG2RST                    RCC_AHB5RSTR_OTG2RST_Msk             /*!< OTG2 reset */
+#define RCC_AHB5RSTR_CACHEAXIRST_Pos            (30U)
+#define RCC_AHB5RSTR_CACHEAXIRST_Msk            (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */
+#define RCC_AHB5RSTR_CACHEAXIRST                RCC_AHB5RSTR_CACHEAXIRST_Msk         /*!< CACHEAXI reset */
+#define RCC_AHB5RSTR_NPURST_Pos                 (31U)
+#define RCC_AHB5RSTR_NPURST_Msk                 (0x1UL << RCC_AHB5RSTR_NPURST_Pos)    /*!< 0x80000000 */
+#define RCC_AHB5RSTR_NPURST                     RCC_AHB5RSTR_NPURST_Msk              /*!< NPU reset */
+
+/****************  Bit definition for RCC_APB1RSTR1 register  *****************/
+#define RCC_APB1RSTR1_TIM2RST_Pos               (0U)
+#define RCC_APB1RSTR1_TIM2RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                   RCC_APB1RSTR1_TIM2RST_Msk            /*!< TIM2 reset */
+#define RCC_APB1RSTR1_TIM3RST_Pos               (1U)
+#define RCC_APB1RSTR1_TIM3RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                   RCC_APB1RSTR1_TIM3RST_Msk            /*!< TIM3 reset */
+#define RCC_APB1RSTR1_TIM4RST_Pos               (2U)
+#define RCC_APB1RSTR1_TIM4RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)  /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                   RCC_APB1RSTR1_TIM4RST_Msk            /*!< TIM4 reset */
+#define RCC_APB1RSTR1_TIM5RST_Pos               (3U)
+#define RCC_APB1RSTR1_TIM5RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)  /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                   RCC_APB1RSTR1_TIM5RST_Msk            /*!< TIM5 reset */
+#define RCC_APB1RSTR1_TIM6RST_Pos               (4U)
+#define RCC_APB1RSTR1_TIM6RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)  /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                   RCC_APB1RSTR1_TIM6RST_Msk            /*!< TIM6 reset */
+#define RCC_APB1RSTR1_TIM7RST_Pos               (5U)
+#define RCC_APB1RSTR1_TIM7RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                   RCC_APB1RSTR1_TIM7RST_Msk            /*!< TIM7 reset */
+#define RCC_APB1RSTR1_TIM12RST_Pos              (6U)
+#define RCC_APB1RSTR1_TIM12RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR1_TIM12RST                  RCC_APB1RSTR1_TIM12RST_Msk           /*!< TIM12 reset */
+#define RCC_APB1RSTR1_TIM13RST_Pos              (7U)
+#define RCC_APB1RSTR1_TIM13RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR1_TIM13RST                  RCC_APB1RSTR1_TIM13RST_Msk           /*!< TIM13 reset */
+#define RCC_APB1RSTR1_TIM14RST_Pos              (8U)
+#define RCC_APB1RSTR1_TIM14RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR1_TIM14RST                  RCC_APB1RSTR1_TIM14RST_Msk           /*!< TIM14 reset */
+#define RCC_APB1RSTR1_LPTIM1RST_Pos             (9U)
+#define RCC_APB1RSTR1_LPTIM1RST_Msk             (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */
+#define RCC_APB1RSTR1_LPTIM1RST                 RCC_APB1RSTR1_LPTIM1RST_Msk          /*!< LPTIM1 reset */
+#define RCC_APB1RSTR1_WWDGRST_Pos               (11U)
+#define RCC_APB1RSTR1_WWDGRST_Msk               (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos)  /*!< 0x00000800 */
+#define RCC_APB1RSTR1_WWDGRST                   RCC_APB1RSTR1_WWDGRST_Msk            /*!< WWDG reset */
+#define RCC_APB1RSTR1_TIM10RST_Pos              (12U)
+#define RCC_APB1RSTR1_TIM10RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTR1_TIM10RST                  RCC_APB1RSTR1_TIM10RST_Msk           /*!< TIM10 reset */
+#define RCC_APB1RSTR1_TIM11RST_Pos              (13U)
+#define RCC_APB1RSTR1_TIM11RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTR1_TIM11RST                  RCC_APB1RSTR1_TIM11RST_Msk           /*!< TIM11 reset */
+#define RCC_APB1RSTR1_SPI2RST_Pos               (14U)
+#define RCC_APB1RSTR1_SPI2RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                   RCC_APB1RSTR1_SPI2RST_Msk            /*!< SPI2 reset */
+#define RCC_APB1RSTR1_SPI3RST_Pos               (15U)
+#define RCC_APB1RSTR1_SPI3RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                   RCC_APB1RSTR1_SPI3RST_Msk            /*!< SPI3 reset */
+#define RCC_APB1RSTR1_SPDIFRX1RST_Pos           (16U)
+#define RCC_APB1RSTR1_SPDIFRX1RST_Msk           (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB1RSTR1_SPDIFRX1RST               RCC_APB1RSTR1_SPDIFRX1RST_Msk        /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTR1_USART2RST_Pos             (17U)
+#define RCC_APB1RSTR1_USART2RST_Msk             (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST                 RCC_APB1RSTR1_USART2RST_Msk          /*!< USART2 reset */
+#define RCC_APB1RSTR1_USART3RST_Pos             (18U)
+#define RCC_APB1RSTR1_USART3RST_Msk             (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST                 RCC_APB1RSTR1_USART3RST_Msk          /*!< USART3 reset */
+#define RCC_APB1RSTR1_UART4RST_Pos              (19U)
+#define RCC_APB1RSTR1_UART4RST_Msk              (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST                  RCC_APB1RSTR1_UART4RST_Msk           /*!< UART4 reset */
+#define RCC_APB1RSTR1_UART5RST_Pos              (20U)
+#define RCC_APB1RSTR1_UART5RST_Msk              (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST                  RCC_APB1RSTR1_UART5RST_Msk           /*!< UART5 reset */
+#define RCC_APB1RSTR1_I2C1RST_Pos               (21U)
+#define RCC_APB1RSTR1_I2C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                   RCC_APB1RSTR1_I2C1RST_Msk            /*!< I2C1 reset */
+#define RCC_APB1RSTR1_I2C2RST_Pos               (22U)
+#define RCC_APB1RSTR1_I2C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                   RCC_APB1RSTR1_I2C2RST_Msk            /*!< I2C2 reset */
+#define RCC_APB1RSTR1_I2C3RST_Pos               (23U)
+#define RCC_APB1RSTR1_I2C3RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                   RCC_APB1RSTR1_I2C3RST_Msk            /*!< I2C3 reset */
+#define RCC_APB1RSTR1_I3C1RST_Pos               (24U)
+#define RCC_APB1RSTR1_I3C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos)  /*!< 0x01000000 */
+#define RCC_APB1RSTR1_I3C1RST                   RCC_APB1RSTR1_I3C1RST_Msk            /*!< I3C1 reset */
+#define RCC_APB1RSTR1_I3C2RST_Pos               (25U)
+#define RCC_APB1RSTR1_I3C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos)  /*!< 0x02000000 */
+#define RCC_APB1RSTR1_I3C2RST                   RCC_APB1RSTR1_I3C2RST_Msk            /*!< I3C2 reset */
+#define RCC_APB1RSTR1_UART7RST_Pos              (30U)
+#define RCC_APB1RSTR1_UART7RST_Msk              (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_UART7RST                  RCC_APB1RSTR1_UART7RST_Msk           /*!< UART7 reset */
+#define RCC_APB1RSTR1_UART8RST_Pos              (31U)
+#define RCC_APB1RSTR1_UART8RST_Msk              (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_UART8RST                  RCC_APB1RSTR1_UART8RST_Msk           /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTR2 register  *****************/
+#define RCC_APB1RSTR2_MDIOSRST_Pos              (5U)
+#define RCC_APB1RSTR2_MDIOSRST_Msk              (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_MDIOSRST                  RCC_APB1RSTR2_MDIOSRST_Msk            /*!< MDIOS reset */
+#define RCC_APB1RSTR2_FDCANRST_Pos              (8U)
+#define RCC_APB1RSTR2_FDCANRST_Msk              (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR2_FDCANRST                  RCC_APB1RSTR2_FDCANRST_Msk            /*!< FDCAN reset */
+#define RCC_APB1RSTR2_UCPD1RST_Pos              (18U)
+#define RCC_APB1RSTR2_UCPD1RST_Msk              (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR2_UCPD1RST                  RCC_APB1RSTR2_UCPD1RST_Msk            /*!< UCPD1 reset */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define RCC_APB2RSTR_TIM1RST_Pos                (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk                (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)   /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                    RCC_APB2RSTR_TIM1RST_Msk             /*!< TIM1 reset */
+#define RCC_APB2RSTR_TIM8RST_Pos                (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk                (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)   /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                    RCC_APB2RSTR_TIM8RST_Msk             /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST_Pos              (4U)
+#define RCC_APB2RSTR_USART1RST_Msk              (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                  RCC_APB2RSTR_USART1RST_Msk           /*!< USART1 reset */
+#define RCC_APB2RSTR_USART6RST_Pos              (5U)
+#define RCC_APB2RSTR_USART6RST_Msk              (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                  RCC_APB2RSTR_USART6RST_Msk           /*!< USART6 reset */
+#define RCC_APB2RSTR_UART9RST_Pos               (6U)
+#define RCC_APB2RSTR_UART9RST_Msk               (0x1UL << RCC_APB2RSTR_UART9RST_Pos)  /*!< 0x00000040 */
+#define RCC_APB2RSTR_UART9RST                   RCC_APB2RSTR_UART9RST_Msk            /*!< UART9 reset */
+#define RCC_APB2RSTR_USART10RST_Pos             (7U)
+#define RCC_APB2RSTR_USART10RST_Msk             (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */
+#define RCC_APB2RSTR_USART10RST                 RCC_APB2RSTR_USART10RST_Msk          /*!< USART10 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos                (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk                (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)   /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                    RCC_APB2RSTR_SPI1RST_Msk             /*!< SPI1 reset */
+#define RCC_APB2RSTR_SPI4RST_Pos                (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk                (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)   /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                    RCC_APB2RSTR_SPI4RST_Msk             /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM18RST_Pos               (15U)
+#define RCC_APB2RSTR_TIM18RST_Msk               (0x1UL << RCC_APB2RSTR_TIM18RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB2RSTR_TIM18RST                   RCC_APB2RSTR_TIM18RST_Msk            /*!< TIM18 reset */
+#define RCC_APB2RSTR_TIM15RST_Pos               (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk               (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                   RCC_APB2RSTR_TIM15RST_Msk            /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST_Pos               (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk               (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)  /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                   RCC_APB2RSTR_TIM16RST_Msk            /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST_Pos               (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk               (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)  /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                   RCC_APB2RSTR_TIM17RST_Msk            /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM9RST_Pos                (19U)
+#define RCC_APB2RSTR_TIM9RST_Msk                (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)   /*!< 0x00080000 */
+#define RCC_APB2RSTR_TIM9RST                    RCC_APB2RSTR_TIM9RST_Msk             /*!< TIM9 reset */
+#define RCC_APB2RSTR_SPI5RST_Pos                (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk                (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)   /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                    RCC_APB2RSTR_SPI5RST_Msk             /*!< SPI5 reset */
+#define RCC_APB2RSTR_SAI1RST_Pos                (21U)
+#define RCC_APB2RSTR_SAI1RST_Msk                (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)   /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                    RCC_APB2RSTR_SAI1RST_Msk             /*!< SAI1 reset */
+#define RCC_APB2RSTR_SAI2RST_Pos                (22U)
+#define RCC_APB2RSTR_SAI2RST_Msk                (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)   /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                    RCC_APB2RSTR_SAI2RST_Msk             /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTR1 register  *****************/
+#define RCC_APB4RSTR1_HDPRST_Pos                (2U)
+#define RCC_APB4RSTR1_HDPRST_Msk                (0x1UL << RCC_APB4RSTR1_HDPRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR1_HDPRST                    RCC_APB4RSTR1_HDPRST_Msk             /*!< HDP reset */
+#define RCC_APB4RSTR1_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR1_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR1_LPUART1RST                RCC_APB4RSTR1_LPUART1RST_Msk         /*!< LPUART1 reset */
+#define RCC_APB4RSTR1_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR1_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB4RSTR1_SPI6RST                   RCC_APB4RSTR1_SPI6RST_Msk            /*!< SPI6 reset */
+#define RCC_APB4RSTR1_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR1_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos)  /*!< 0x00000080 */
+#define RCC_APB4RSTR1_I2C4RST                   RCC_APB4RSTR1_I2C4RST_Msk            /*!< I2C4 reset */
+#define RCC_APB4RSTR1_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR1_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */
+#define RCC_APB4RSTR1_LPTIM2RST                 RCC_APB4RSTR1_LPTIM2RST_Msk          /*!< LPTIM2 reset */
+#define RCC_APB4RSTR1_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR1_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */
+#define RCC_APB4RSTR1_LPTIM3RST                 RCC_APB4RSTR1_LPTIM3RST_Msk          /*!< LPTIM3 reset */
+#define RCC_APB4RSTR1_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR1_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */
+#define RCC_APB4RSTR1_LPTIM4RST                 RCC_APB4RSTR1_LPTIM4RST_Msk          /*!< LPTIM4 reset */
+#define RCC_APB4RSTR1_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR1_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */
+#define RCC_APB4RSTR1_LPTIM5RST                 RCC_APB4RSTR1_LPTIM5RST_Msk          /*!< LPTIM5 reset */
+#define RCC_APB4RSTR1_VREFBUFRST_Pos            (15U)
+#define RCC_APB4RSTR1_VREFBUFRST_Msk            (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR1_VREFBUFRST                RCC_APB4RSTR1_VREFBUFRST_Msk         /*!< VREFBUF reset */
+#define RCC_APB4RSTR1_RTCRST_Pos                (16U)
+#define RCC_APB4RSTR1_RTCRST_Msk                (0x1UL << RCC_APB4RSTR1_RTCRST_Pos)   /*!< 0x00010000 */
+#define RCC_APB4RSTR1_RTCRST                    RCC_APB4RSTR1_RTCRST_Msk             /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTR2 register  *****************/
+#define RCC_APB4RSTR2_SYSCFGRST_Pos             (0U)
+#define RCC_APB4RSTR2_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */
+#define RCC_APB4RSTR2_SYSCFGRST                 RCC_APB4RSTR2_SYSCFGRST_Msk          /*!< SYSCFG reset */
+#define RCC_APB4RSTR2_DTSRST_Pos                (2U)
+#define RCC_APB4RSTR2_DTSRST_Msk                (0x1UL << RCC_APB4RSTR2_DTSRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR2_DTSRST                    RCC_APB4RSTR2_DTSRST_Msk             /*!< DTS reset */
+
+/*****************  Bit definition for RCC_APB5RSTR register  *****************/
+#define RCC_APB5RSTR_LTDCRST_Pos                (1U)
+#define RCC_APB5RSTR_LTDCRST_Msk                (0x1UL << RCC_APB5RSTR_LTDCRST_Pos)   /*!< 0x00000002 */
+#define RCC_APB5RSTR_LTDCRST                    RCC_APB5RSTR_LTDCRST_Msk             /*!< LTDC reset */
+#define RCC_APB5RSTR_DCMIPPRST_Pos              (2U)
+#define RCC_APB5RSTR_DCMIPPRST_Msk              (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTR_DCMIPPRST                  RCC_APB5RSTR_DCMIPPRST_Msk           /*!< DCMIPP reset */
+#define RCC_APB5RSTR_GFXTIMRST_Pos              (4U)
+#define RCC_APB5RSTR_GFXTIMRST_Msk              (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTR_GFXTIMRST                  RCC_APB5RSTR_GFXTIMRST_Msk           /*!< GFXTIM reset */
+#define RCC_APB5RSTR_VENCRST_Pos                (5U)
+#define RCC_APB5RSTR_VENCRST_Msk                (0x1UL << RCC_APB5RSTR_VENCRST_Pos)   /*!< 0x00000020 */
+#define RCC_APB5RSTR_VENCRST                    RCC_APB5RSTR_VENCRST_Msk             /*!< VENC reset */
+#define RCC_APB5RSTR_CSIRST_Pos                 (6U)
+#define RCC_APB5RSTR_CSIRST_Msk                 (0x1UL << RCC_APB5RSTR_CSIRST_Pos)    /*!< 0x00000040 */
+#define RCC_APB5RSTR_CSIRST                     RCC_APB5RSTR_CSIRST_Msk              /*!< CSI reset */
+
+/******************  Bit definition for RCC_DIVENR register  ******************/
+#define RCC_DIVENR_IC1EN_Pos                    (0U)
+#define RCC_DIVENR_IC1EN_Msk                    (0x1UL << RCC_DIVENR_IC1EN_Pos)       /*!< 0x00000001 */
+#define RCC_DIVENR_IC1EN                        RCC_DIVENR_IC1EN_Msk                 /*!< IC1 enable */
+#define RCC_DIVENR_IC2EN_Pos                    (1U)
+#define RCC_DIVENR_IC2EN_Msk                    (0x1UL << RCC_DIVENR_IC2EN_Pos)       /*!< 0x00000002 */
+#define RCC_DIVENR_IC2EN                        RCC_DIVENR_IC2EN_Msk                 /*!< IC2 enable */
+#define RCC_DIVENR_IC3EN_Pos                    (2U)
+#define RCC_DIVENR_IC3EN_Msk                    (0x1UL << RCC_DIVENR_IC3EN_Pos)       /*!< 0x00000004 */
+#define RCC_DIVENR_IC3EN                        RCC_DIVENR_IC3EN_Msk                 /*!< IC3 enable */
+#define RCC_DIVENR_IC4EN_Pos                    (3U)
+#define RCC_DIVENR_IC4EN_Msk                    (0x1UL << RCC_DIVENR_IC4EN_Pos)       /*!< 0x00000008 */
+#define RCC_DIVENR_IC4EN                        RCC_DIVENR_IC4EN_Msk                 /*!< IC4 enable */
+#define RCC_DIVENR_IC5EN_Pos                    (4U)
+#define RCC_DIVENR_IC5EN_Msk                    (0x1UL << RCC_DIVENR_IC5EN_Pos)       /*!< 0x00000010 */
+#define RCC_DIVENR_IC5EN                        RCC_DIVENR_IC5EN_Msk                 /*!< IC5 enable */
+#define RCC_DIVENR_IC6EN_Pos                    (5U)
+#define RCC_DIVENR_IC6EN_Msk                    (0x1UL << RCC_DIVENR_IC6EN_Pos)       /*!< 0x00000020 */
+#define RCC_DIVENR_IC6EN                        RCC_DIVENR_IC6EN_Msk                 /*!< IC6 enable */
+#define RCC_DIVENR_IC7EN_Pos                    (6U)
+#define RCC_DIVENR_IC7EN_Msk                    (0x1UL << RCC_DIVENR_IC7EN_Pos)       /*!< 0x00000040 */
+#define RCC_DIVENR_IC7EN                        RCC_DIVENR_IC7EN_Msk                 /*!< IC7 enable */
+#define RCC_DIVENR_IC8EN_Pos                    (7U)
+#define RCC_DIVENR_IC8EN_Msk                    (0x1UL << RCC_DIVENR_IC8EN_Pos)       /*!< 0x00000080 */
+#define RCC_DIVENR_IC8EN                        RCC_DIVENR_IC8EN_Msk                 /*!< IC8 enable */
+#define RCC_DIVENR_IC9EN_Pos                    (8U)
+#define RCC_DIVENR_IC9EN_Msk                    (0x1UL << RCC_DIVENR_IC9EN_Pos)       /*!< 0x00000100 */
+#define RCC_DIVENR_IC9EN                        RCC_DIVENR_IC9EN_Msk                 /*!< IC9 enable */
+#define RCC_DIVENR_IC10EN_Pos                   (9U)
+#define RCC_DIVENR_IC10EN_Msk                   (0x1UL << RCC_DIVENR_IC10EN_Pos)      /*!< 0x00000200 */
+#define RCC_DIVENR_IC10EN                       RCC_DIVENR_IC10EN_Msk                /*!< IC10 enable */
+#define RCC_DIVENR_IC11EN_Pos                   (10U)
+#define RCC_DIVENR_IC11EN_Msk                   (0x1UL << RCC_DIVENR_IC11EN_Pos)      /*!< 0x00000400 */
+#define RCC_DIVENR_IC11EN                       RCC_DIVENR_IC11EN_Msk                /*!< IC11 enable */
+#define RCC_DIVENR_IC12EN_Pos                   (11U)
+#define RCC_DIVENR_IC12EN_Msk                   (0x1UL << RCC_DIVENR_IC12EN_Pos)      /*!< 0x00000800 */
+#define RCC_DIVENR_IC12EN                       RCC_DIVENR_IC12EN_Msk                /*!< IC12 enable */
+#define RCC_DIVENR_IC13EN_Pos                   (12U)
+#define RCC_DIVENR_IC13EN_Msk                   (0x1UL << RCC_DIVENR_IC13EN_Pos)      /*!< 0x00001000 */
+#define RCC_DIVENR_IC13EN                       RCC_DIVENR_IC13EN_Msk                /*!< IC13 enable */
+#define RCC_DIVENR_IC14EN_Pos                   (13U)
+#define RCC_DIVENR_IC14EN_Msk                   (0x1UL << RCC_DIVENR_IC14EN_Pos)      /*!< 0x00002000 */
+#define RCC_DIVENR_IC14EN                       RCC_DIVENR_IC14EN_Msk                /*!< IC14 enable */
+#define RCC_DIVENR_IC15EN_Pos                   (14U)
+#define RCC_DIVENR_IC15EN_Msk                   (0x1UL << RCC_DIVENR_IC15EN_Pos)      /*!< 0x00004000 */
+#define RCC_DIVENR_IC15EN                       RCC_DIVENR_IC15EN_Msk                /*!< IC15 enable */
+#define RCC_DIVENR_IC16EN_Pos                   (15U)
+#define RCC_DIVENR_IC16EN_Msk                   (0x1UL << RCC_DIVENR_IC16EN_Pos)      /*!< 0x00008000 */
+#define RCC_DIVENR_IC16EN                       RCC_DIVENR_IC16EN_Msk                /*!< IC16 enable */
+#define RCC_DIVENR_IC17EN_Pos                   (16U)
+#define RCC_DIVENR_IC17EN_Msk                   (0x1UL << RCC_DIVENR_IC17EN_Pos)      /*!< 0x00010000 */
+#define RCC_DIVENR_IC17EN                       RCC_DIVENR_IC17EN_Msk                /*!< IC17 enable */
+#define RCC_DIVENR_IC18EN_Pos                   (17U)
+#define RCC_DIVENR_IC18EN_Msk                   (0x1UL << RCC_DIVENR_IC18EN_Pos)      /*!< 0x00020000 */
+#define RCC_DIVENR_IC18EN                       RCC_DIVENR_IC18EN_Msk                /*!< IC18 enable */
+#define RCC_DIVENR_IC19EN_Pos                   (18U)
+#define RCC_DIVENR_IC19EN_Msk                   (0x1UL << RCC_DIVENR_IC19EN_Pos)      /*!< 0x00040000 */
+#define RCC_DIVENR_IC19EN                       RCC_DIVENR_IC19EN_Msk                /*!< IC19 enable */
+#define RCC_DIVENR_IC20EN_Pos                   (19U)
+#define RCC_DIVENR_IC20EN_Msk                   (0x1UL << RCC_DIVENR_IC20EN_Pos)      /*!< 0x00080000 */
+#define RCC_DIVENR_IC20EN                       RCC_DIVENR_IC20EN_Msk                /*!< IC20 enable */
+
+/******************  Bit definition for RCC_BUSENR register  ******************/
+#define RCC_BUSENR_ACLKNEN_Pos                  (0U)
+#define RCC_BUSENR_ACLKNEN_Msk                  (0x1UL << RCC_BUSENR_ACLKNEN_Pos)     /*!< 0x00000001 */
+#define RCC_BUSENR_ACLKNEN                      RCC_BUSENR_ACLKNEN_Msk               /*!< ACLKN enable */
+#define RCC_BUSENR_ACLKNCEN_Pos                 (1U)
+#define RCC_BUSENR_ACLKNCEN_Msk                 (0x1UL << RCC_BUSENR_ACLKNCEN_Pos)    /*!< 0x00000002 */
+#define RCC_BUSENR_ACLKNCEN                     RCC_BUSENR_ACLKNCEN_Msk              /*!< ACLKNC enable */
+#define RCC_BUSENR_AHBMEN_Pos                   (2U)
+#define RCC_BUSENR_AHBMEN_Msk                   (0x1UL << RCC_BUSENR_AHBMEN_Pos)      /*!< 0x00000004 */
+#define RCC_BUSENR_AHBMEN                       RCC_BUSENR_AHBMEN_Msk                /*!< AHBM enable */
+#define RCC_BUSENR_AHB1EN_Pos                   (3U)
+#define RCC_BUSENR_AHB1EN_Msk                   (0x1UL << RCC_BUSENR_AHB1EN_Pos)      /*!< 0x00000008 */
+#define RCC_BUSENR_AHB1EN                       RCC_BUSENR_AHB1EN_Msk                /*!< AHB1 enable */
+#define RCC_BUSENR_AHB2EN_Pos                   (4U)
+#define RCC_BUSENR_AHB2EN_Msk                   (0x1UL << RCC_BUSENR_AHB2EN_Pos)      /*!< 0x00000010 */
+#define RCC_BUSENR_AHB2EN                       RCC_BUSENR_AHB2EN_Msk                /*!< AHB2 enable */
+#define RCC_BUSENR_AHB3EN_Pos                   (5U)
+#define RCC_BUSENR_AHB3EN_Msk                   (0x1UL << RCC_BUSENR_AHB3EN_Pos)      /*!< 0x00000020 */
+#define RCC_BUSENR_AHB3EN                       RCC_BUSENR_AHB3EN_Msk                /*!< AHB3 enable */
+#define RCC_BUSENR_AHB4EN_Pos                   (6U)
+#define RCC_BUSENR_AHB4EN_Msk                   (0x1UL << RCC_BUSENR_AHB4EN_Pos)      /*!< 0x00000040 */
+#define RCC_BUSENR_AHB4EN                       RCC_BUSENR_AHB4EN_Msk                /*!< AHB4 enable */
+#define RCC_BUSENR_AHB5EN_Pos                   (7U)
+#define RCC_BUSENR_AHB5EN_Msk                   (0x1UL << RCC_BUSENR_AHB5EN_Pos)      /*!< 0x00000080 */
+#define RCC_BUSENR_AHB5EN                       RCC_BUSENR_AHB5EN_Msk                /*!< AHB5 enable */
+#define RCC_BUSENR_APB1EN_Pos                   (8U)
+#define RCC_BUSENR_APB1EN_Msk                   (0x1UL << RCC_BUSENR_APB1EN_Pos)      /*!< 0x00000100 */
+#define RCC_BUSENR_APB1EN                       RCC_BUSENR_APB1EN_Msk                /*!< APB1 enable */
+#define RCC_BUSENR_APB2EN_Pos                   (9U)
+#define RCC_BUSENR_APB2EN_Msk                   (0x1UL << RCC_BUSENR_APB2EN_Pos)      /*!< 0x00000200 */
+#define RCC_BUSENR_APB2EN                       RCC_BUSENR_APB2EN_Msk                /*!< APB2 enable */
+#define RCC_BUSENR_APB3EN_Pos                   (10U)
+#define RCC_BUSENR_APB3EN_Msk                   (0x1UL << RCC_BUSENR_APB3EN_Pos)      /*!< 0x00000400 */
+#define RCC_BUSENR_APB3EN                       RCC_BUSENR_APB3EN_Msk                /*!< APB3 enable */
+#define RCC_BUSENR_APB4EN_Pos                   (11U)
+#define RCC_BUSENR_APB4EN_Msk                   (0x1UL << RCC_BUSENR_APB4EN_Pos)      /*!< 0x00000800 */
+#define RCC_BUSENR_APB4EN                       RCC_BUSENR_APB4EN_Msk                /*!< APB4 enable */
+#define RCC_BUSENR_APB5EN_Pos                   (12U)
+#define RCC_BUSENR_APB5EN_Msk                   (0x1UL << RCC_BUSENR_APB5EN_Pos)      /*!< 0x00001000 */
+#define RCC_BUSENR_APB5EN                       RCC_BUSENR_APB5EN_Msk                /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENR register  ******************/
+#define RCC_MISCENR_DBGEN_Pos                   (0U)
+#define RCC_MISCENR_DBGEN_Msk                   (0x1UL << RCC_MISCENR_DBGEN_Pos)      /*!< 0x00000001 */
+#define RCC_MISCENR_DBGEN                       RCC_MISCENR_DBGEN_Msk                /*!< DBG enable */
+#define RCC_MISCENR_MCO1EN_Pos                  (1U)
+#define RCC_MISCENR_MCO1EN_Msk                  (0x1UL << RCC_MISCENR_MCO1EN_Pos)     /*!< 0x00000002 */
+#define RCC_MISCENR_MCO1EN                      RCC_MISCENR_MCO1EN_Msk               /*!< MCO1 enable */
+#define RCC_MISCENR_MCO2EN_Pos                  (2U)
+#define RCC_MISCENR_MCO2EN_Msk                  (0x1UL << RCC_MISCENR_MCO2EN_Pos)     /*!< 0x00000004 */
+#define RCC_MISCENR_MCO2EN                      RCC_MISCENR_MCO2EN_Msk               /*!< MCO2 enable */
+#define RCC_MISCENR_XSPIPHYCOMPEN_Pos           (3U)
+#define RCC_MISCENR_XSPIPHYCOMPEN_Msk           (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MISCENR_XSPIPHYCOMPEN               RCC_MISCENR_XSPIPHYCOMPEN_Msk        /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENR_PEREN_Pos                   (6U)
+#define RCC_MISCENR_PEREN_Msk                   (0x1UL << RCC_MISCENR_PEREN_Pos)      /*!< 0x00000040 */
+#define RCC_MISCENR_PEREN                       RCC_MISCENR_PEREN_Msk                /*!< PER enable */
+
+/******************  Bit definition for RCC_MEMENR register  ******************/
+#define RCC_MEMENR_AXISRAM3EN_Pos               (0U)
+#define RCC_MEMENR_AXISRAM3EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMENR_AXISRAM3EN                   RCC_MEMENR_AXISRAM3EN_Msk            /*!< AXISRAM3 enable */
+#define RCC_MEMENR_AXISRAM4EN_Pos               (1U)
+#define RCC_MEMENR_AXISRAM4EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMENR_AXISRAM4EN                   RCC_MEMENR_AXISRAM4EN_Msk            /*!< AXISRAM4 enable */
+#define RCC_MEMENR_AXISRAM5EN_Pos               (2U)
+#define RCC_MEMENR_AXISRAM5EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMENR_AXISRAM5EN                   RCC_MEMENR_AXISRAM5EN_Msk            /*!< AXISRAM5 enable */
+#define RCC_MEMENR_AXISRAM6EN_Pos               (3U)
+#define RCC_MEMENR_AXISRAM6EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMENR_AXISRAM6EN                   RCC_MEMENR_AXISRAM6EN_Msk            /*!< AXISRAM6 enable */
+#define RCC_MEMENR_AHBSRAM1EN_Pos               (4U)
+#define RCC_MEMENR_AHBSRAM1EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMENR_AHBSRAM1EN                   RCC_MEMENR_AHBSRAM1EN_Msk            /*!< AHBSRAM1 enable */
+#define RCC_MEMENR_AHBSRAM2EN_Pos               (5U)
+#define RCC_MEMENR_AHBSRAM2EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMENR_AHBSRAM2EN                   RCC_MEMENR_AHBSRAM2EN_Msk            /*!< AHBSRAM2 enable */
+#define RCC_MEMENR_BKPSRAMEN_Pos                (6U)
+#define RCC_MEMENR_BKPSRAMEN_Msk                (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos)   /*!< 0x00000040 */
+#define RCC_MEMENR_BKPSRAMEN                    RCC_MEMENR_BKPSRAMEN_Msk             /*!< BKPSRAM enable */
+#define RCC_MEMENR_AXISRAM1EN_Pos               (7U)
+#define RCC_MEMENR_AXISRAM1EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMENR_AXISRAM1EN                   RCC_MEMENR_AXISRAM1EN_Msk            /*!< AXISRAM1 enable */
+#define RCC_MEMENR_AXISRAM2EN_Pos               (8U)
+#define RCC_MEMENR_AXISRAM2EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMENR_AXISRAM2EN                   RCC_MEMENR_AXISRAM2EN_Msk            /*!< AXISRAM2 enable */
+#define RCC_MEMENR_FLEXRAMEN_Pos                (9U)
+#define RCC_MEMENR_FLEXRAMEN_Msk                (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos)   /*!< 0x00000200 */
+#define RCC_MEMENR_FLEXRAMEN                    RCC_MEMENR_FLEXRAMEN_Msk             /*!< FLEXRAM enable */
+#define RCC_MEMENR_CACHEAXIRAMEN_Pos            (10U)
+#define RCC_MEMENR_CACHEAXIRAMEN_Msk            (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */
+#define RCC_MEMENR_CACHEAXIRAMEN                RCC_MEMENR_CACHEAXIRAMEN_Msk         /*!< CACHEAXIRAM enable */
+#define RCC_MEMENR_VENCRAMEN_Pos                (11U)
+#define RCC_MEMENR_VENCRAMEN_Msk                (0x1UL << RCC_MEMENR_VENCRAMEN_Pos)   /*!< 0x00000800 */
+#define RCC_MEMENR_VENCRAMEN                    RCC_MEMENR_VENCRAMEN_Msk             /*!< VENCRAM enable */
+#define RCC_MEMENR_BOOTROMEN_Pos                (12U)
+#define RCC_MEMENR_BOOTROMEN_Msk                (0x1UL << RCC_MEMENR_BOOTROMEN_Pos)   /*!< 0x00001000 */
+#define RCC_MEMENR_BOOTROMEN                    RCC_MEMENR_BOOTROMEN_Msk             /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENR register  ******************/
+#define RCC_AHB1ENR_GPDMA1EN_Pos                (4U)
+#define RCC_AHB1ENR_GPDMA1EN_Msk                (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPDMA1EN                    RCC_AHB1ENR_GPDMA1EN_Msk             /*!< GPDMA1 enable */
+#define RCC_AHB1ENR_ADC12EN_Pos                 (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                 (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                     RCC_AHB1ENR_ADC12EN_Msk              /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENR register  ******************/
+#define RCC_AHB2ENR_RAMCFGEN_Pos                (12U)
+#define RCC_AHB2ENR_RAMCFGEN_Msk                (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2ENR_RAMCFGEN                    RCC_AHB2ENR_RAMCFGEN_Msk             /*!< RAMCFG enable */
+#define RCC_AHB2ENR_MDF1EN_Pos                  (16U)
+#define RCC_AHB2ENR_MDF1EN_Msk                  (0x1UL << RCC_AHB2ENR_MDF1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB2ENR_MDF1EN                      RCC_AHB2ENR_MDF1EN_Msk               /*!< MDF1 enable */
+#define RCC_AHB2ENR_ADF1EN_Pos                  (17U)
+#define RCC_AHB2ENR_ADF1EN_Msk                  (0x1UL << RCC_AHB2ENR_ADF1EN_Pos)     /*!< 0x00020000 */
+#define RCC_AHB2ENR_ADF1EN                      RCC_AHB2ENR_ADF1EN_Msk               /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENR register  ******************/
+#define RCC_AHB3ENR_RNGEN_Pos                   (0U)
+#define RCC_AHB3ENR_RNGEN_Msk                   (0x1UL << RCC_AHB3ENR_RNGEN_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3ENR_RNGEN                       RCC_AHB3ENR_RNGEN_Msk                /*!< RNG enable */
+#define RCC_AHB3ENR_HASHEN_Pos                  (1U)
+#define RCC_AHB3ENR_HASHEN_Msk                  (0x1UL << RCC_AHB3ENR_HASHEN_Pos)     /*!< 0x00000002 */
+#define RCC_AHB3ENR_HASHEN                      RCC_AHB3ENR_HASHEN_Msk               /*!< HASH enable */
+#define RCC_AHB3ENR_PKAEN_Pos                   (8U)
+#define RCC_AHB3ENR_PKAEN_Msk                   (0x1UL << RCC_AHB3ENR_PKAEN_Pos)      /*!< 0x00000100 */
+#define RCC_AHB3ENR_PKAEN                       RCC_AHB3ENR_PKAEN_Msk                /*!< PKA enable */
+#define RCC_AHB3ENR_RIFSCEN_Pos                 (9U)
+#define RCC_AHB3ENR_RIFSCEN_Msk                 (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos)    /*!< 0x00000200 */
+#define RCC_AHB3ENR_RIFSCEN                     RCC_AHB3ENR_RIFSCEN_Msk              /*!< RIFSC enable */
+#define RCC_AHB3ENR_IACEN_Pos                   (10U)
+#define RCC_AHB3ENR_IACEN_Msk                   (0x1UL << RCC_AHB3ENR_IACEN_Pos)      /*!< 0x00000400 */
+#define RCC_AHB3ENR_IACEN                       RCC_AHB3ENR_IACEN_Msk                /*!< IAC enable */
+#define RCC_AHB3ENR_RISAFEN_Pos                 (14U)
+#define RCC_AHB3ENR_RISAFEN_Msk                 (0x1UL << RCC_AHB3ENR_RISAFEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB3ENR_RISAFEN                     RCC_AHB3ENR_RISAFEN_Msk              /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                 (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                     RCC_AHB4ENR_GPIOAEN_Msk              /*!< GPIO A enable */
+#define RCC_AHB4ENR_GPIOBEN_Pos                 (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                     RCC_AHB4ENR_GPIOBEN_Msk              /*!< GPIO B enable */
+#define RCC_AHB4ENR_GPIOCEN_Pos                 (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)    /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                     RCC_AHB4ENR_GPIOCEN_Msk              /*!< GPIO C enable */
+#define RCC_AHB4ENR_GPIODEN_Pos                 (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)    /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                     RCC_AHB4ENR_GPIODEN_Msk              /*!< GPIO D enable */
+#define RCC_AHB4ENR_GPIOEEN_Pos                 (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)    /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                     RCC_AHB4ENR_GPIOEEN_Msk              /*!< GPIO E enable */
+#define RCC_AHB4ENR_GPIOFEN_Pos                 (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                     RCC_AHB4ENR_GPIOFEN_Msk              /*!< GPIO F enable */
+#define RCC_AHB4ENR_GPIOGEN_Pos                 (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)    /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                     RCC_AHB4ENR_GPIOGEN_Msk              /*!< GPIO G enable */
+#define RCC_AHB4ENR_GPIOHEN_Pos                 (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)    /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                     RCC_AHB4ENR_GPIOHEN_Msk              /*!< GPIO H enable */
+#define RCC_AHB4ENR_GPIONEN_Pos                 (13U)
+#define RCC_AHB4ENR_GPIONEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIONEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB4ENR_GPIONEN                     RCC_AHB4ENR_GPIONEN_Msk              /*!< GPIO N enable */
+#define RCC_AHB4ENR_GPIOOEN_Pos                 (14U)
+#define RCC_AHB4ENR_GPIOOEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB4ENR_GPIOOEN                     RCC_AHB4ENR_GPIOOEN_Msk              /*!< GPIO O enable */
+#define RCC_AHB4ENR_GPIOPEN_Pos                 (15U)
+#define RCC_AHB4ENR_GPIOPEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos)    /*!< 0x00008000 */
+#define RCC_AHB4ENR_GPIOPEN                     RCC_AHB4ENR_GPIOPEN_Msk              /*!< GPIO P enable */
+#define RCC_AHB4ENR_GPIOQEN_Pos                 (16U)
+#define RCC_AHB4ENR_GPIOQEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos)    /*!< 0x00010000 */
+#define RCC_AHB4ENR_GPIOQEN                     RCC_AHB4ENR_GPIOQEN_Msk              /*!< GPIO Q enable */
+#define RCC_AHB4ENR_PWREN_Pos                   (18U)
+#define RCC_AHB4ENR_PWREN_Msk                   (0x1UL << RCC_AHB4ENR_PWREN_Pos)      /*!< 0x00040000 */
+#define RCC_AHB4ENR_PWREN                       RCC_AHB4ENR_PWREN_Msk                /*!< PWR enable */
+#define RCC_AHB4ENR_CRCEN_Pos                   (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                   (0x1UL << RCC_AHB4ENR_CRCEN_Pos)      /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                       RCC_AHB4ENR_CRCEN_Msk                /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENR register  ******************/
+#define RCC_AHB5ENR_HPDMA1EN_Pos                (0U)
+#define RCC_AHB5ENR_HPDMA1EN_Msk                (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5ENR_HPDMA1EN                    RCC_AHB5ENR_HPDMA1EN_Msk             /*!< HPDMA1 enable */
+#define RCC_AHB5ENR_DMA2DEN_Pos                 (1U)
+#define RCC_AHB5ENR_DMA2DEN_Msk                 (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB5ENR_DMA2DEN                     RCC_AHB5ENR_DMA2DEN_Msk              /*!< DMA2D enable */
+#define RCC_AHB5ENR_JPEGEN_Pos                  (3U)
+#define RCC_AHB5ENR_JPEGEN_Msk                  (0x1UL << RCC_AHB5ENR_JPEGEN_Pos)     /*!< 0x00000008 */
+#define RCC_AHB5ENR_JPEGEN                      RCC_AHB5ENR_JPEGEN_Msk               /*!< JPEG enable */
+#define RCC_AHB5ENR_FMCEN_Pos                   (4U)
+#define RCC_AHB5ENR_FMCEN_Msk                   (0x1UL << RCC_AHB5ENR_FMCEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB5ENR_FMCEN                       RCC_AHB5ENR_FMCEN_Msk                /*!< FMC enable */
+#define RCC_AHB5ENR_XSPI1EN_Pos                 (5U)
+#define RCC_AHB5ENR_XSPI1EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB5ENR_XSPI1EN                     RCC_AHB5ENR_XSPI1EN_Msk              /*!< XSPI1 enable */
+#define RCC_AHB5ENR_PSSIEN_Pos                  (6U)
+#define RCC_AHB5ENR_PSSIEN_Msk                  (0x1UL << RCC_AHB5ENR_PSSIEN_Pos)     /*!< 0x00000040 */
+#define RCC_AHB5ENR_PSSIEN                      RCC_AHB5ENR_PSSIEN_Msk               /*!< PSSI enable */
+#define RCC_AHB5ENR_SDMMC2EN_Pos                (7U)
+#define RCC_AHB5ENR_SDMMC2EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5ENR_SDMMC2EN                    RCC_AHB5ENR_SDMMC2EN_Msk             /*!< SDMMC2 enable */
+#define RCC_AHB5ENR_SDMMC1EN_Pos                (8U)
+#define RCC_AHB5ENR_SDMMC1EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5ENR_SDMMC1EN                    RCC_AHB5ENR_SDMMC1EN_Msk             /*!< SDMMC1 enable */
+#define RCC_AHB5ENR_XSPI2EN_Pos                 (12U)
+#define RCC_AHB5ENR_XSPI2EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos)    /*!< 0x00001000 */
+#define RCC_AHB5ENR_XSPI2EN                     RCC_AHB5ENR_XSPI2EN_Msk              /*!< XSPI2 enable */
+#define RCC_AHB5ENR_XSPIMEN_Pos                 (13U)
+#define RCC_AHB5ENR_XSPIMEN_Msk                 (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB5ENR_XSPIMEN                     RCC_AHB5ENR_XSPIMEN_Msk              /*!< XSPIM enable */
+#define RCC_AHB5ENR_XSPI3EN_Pos                 (17U)
+#define RCC_AHB5ENR_XSPI3EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos)    /*!< 0x00020000 */
+#define RCC_AHB5ENR_XSPI3EN                     RCC_AHB5ENR_XSPI3EN_Msk              /*!< XSPI3 enable */
+#define RCC_AHB5ENR_GFXMMUEN_Pos                (19U)
+#define RCC_AHB5ENR_GFXMMUEN_Msk                (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5ENR_GFXMMUEN                    RCC_AHB5ENR_GFXMMUEN_Msk             /*!< GFXMMU enable */
+#define RCC_AHB5ENR_GPU2DEN_Pos                 (20U)
+#define RCC_AHB5ENR_GPU2DEN_Msk                 (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos)    /*!< 0x00100000 */
+#define RCC_AHB5ENR_GPU2DEN                     RCC_AHB5ENR_GPU2DEN_Msk              /*!< GPU2D enable */
+#define RCC_AHB5ENR_ETH1MACEN_Pos               (22U)
+#define RCC_AHB5ENR_ETH1MACEN_Msk               (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5ENR_ETH1MACEN                   RCC_AHB5ENR_ETH1MACEN_Msk            /*!< ETH1MAC enable */
+#define RCC_AHB5ENR_ETH1TXEN_Pos                (23U)
+#define RCC_AHB5ENR_ETH1TXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5ENR_ETH1TXEN                    RCC_AHB5ENR_ETH1TXEN_Msk             /*!< ETH1TX enable */
+#define RCC_AHB5ENR_ETH1RXEN_Pos                (24U)
+#define RCC_AHB5ENR_ETH1RXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5ENR_ETH1RXEN                    RCC_AHB5ENR_ETH1RXEN_Msk             /*!< ETH1RX enable */
+#define RCC_AHB5ENR_ETH1EN_Pos                  (25U)
+#define RCC_AHB5ENR_ETH1EN_Msk                  (0x1UL << RCC_AHB5ENR_ETH1EN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB5ENR_ETH1EN                      RCC_AHB5ENR_ETH1EN_Msk               /*!< ETH1 enable */
+#define RCC_AHB5ENR_OTG1EN_Pos                  (26U)
+#define RCC_AHB5ENR_OTG1EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG1EN_Pos)     /*!< 0x04000000 */
+#define RCC_AHB5ENR_OTG1EN                      RCC_AHB5ENR_OTG1EN_Msk               /*!< OTG1 enable */
+#define RCC_AHB5ENR_OTGPHY1EN_Pos               (27U)
+#define RCC_AHB5ENR_OTGPHY1EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5ENR_OTGPHY1EN                   RCC_AHB5ENR_OTGPHY1EN_Msk            /*!< OTGPHY1 enable */
+#define RCC_AHB5ENR_OTGPHY2EN_Pos               (28U)
+#define RCC_AHB5ENR_OTGPHY2EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5ENR_OTGPHY2EN                   RCC_AHB5ENR_OTGPHY2EN_Msk            /*!< OTGPHY2 enable */
+#define RCC_AHB5ENR_OTG2EN_Pos                  (29U)
+#define RCC_AHB5ENR_OTG2EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG2EN_Pos)     /*!< 0x20000000 */
+#define RCC_AHB5ENR_OTG2EN                      RCC_AHB5ENR_OTG2EN_Msk               /*!< OTG2 enable */
+#define RCC_AHB5ENR_CACHEAXIEN_Pos              (30U)
+#define RCC_AHB5ENR_CACHEAXIEN_Msk              (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB5ENR_CACHEAXIEN                  RCC_AHB5ENR_CACHEAXIEN_Msk           /*!< CACHEAXI enable */
+#define RCC_AHB5ENR_NPUEN_Pos                   (31U)
+#define RCC_AHB5ENR_NPUEN_Msk                   (0x1UL << RCC_AHB5ENR_NPUEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB5ENR_NPUEN                       RCC_AHB5ENR_NPUEN_Msk                /*!< NPU enable */
+
+/*****************  Bit definition for RCC_APB1ENR1 register  *****************/
+#define RCC_APB1ENR1_TIM2EN_Pos                 (0U)
+#define RCC_APB1ENR1_TIM2EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                     RCC_APB1ENR1_TIM2EN_Msk              /*!< TIM2 enable */
+#define RCC_APB1ENR1_TIM3EN_Pos                 (1U)
+#define RCC_APB1ENR1_TIM3EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                     RCC_APB1ENR1_TIM3EN_Msk              /*!< TIM3 enable */
+#define RCC_APB1ENR1_TIM4EN_Pos                 (2U)
+#define RCC_APB1ENR1_TIM4EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)    /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                     RCC_APB1ENR1_TIM4EN_Msk              /*!< TIM4 enable */
+#define RCC_APB1ENR1_TIM5EN_Pos                 (3U)
+#define RCC_APB1ENR1_TIM5EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)    /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                     RCC_APB1ENR1_TIM5EN_Msk              /*!< TIM5 enable */
+#define RCC_APB1ENR1_TIM6EN_Pos                 (4U)
+#define RCC_APB1ENR1_TIM6EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)    /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                     RCC_APB1ENR1_TIM6EN_Msk              /*!< TIM6 enable */
+#define RCC_APB1ENR1_TIM7EN_Pos                 (5U)
+#define RCC_APB1ENR1_TIM7EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                     RCC_APB1ENR1_TIM7EN_Msk              /*!< TIM7 enable */
+#define RCC_APB1ENR1_TIM12EN_Pos                (6U)
+#define RCC_APB1ENR1_TIM12EN_Msk                (0x1UL << RCC_APB1ENR1_TIM12EN_Pos)   /*!< 0x00000040 */
+#define RCC_APB1ENR1_TIM12EN                    RCC_APB1ENR1_TIM12EN_Msk             /*!< TIM12 enable */
+#define RCC_APB1ENR1_TIM13EN_Pos                (7U)
+#define RCC_APB1ENR1_TIM13EN_Msk                (0x1UL << RCC_APB1ENR1_TIM13EN_Pos)   /*!< 0x00000080 */
+#define RCC_APB1ENR1_TIM13EN                    RCC_APB1ENR1_TIM13EN_Msk             /*!< TIM13 enable */
+#define RCC_APB1ENR1_TIM14EN_Pos                (8U)
+#define RCC_APB1ENR1_TIM14EN_Msk                (0x1UL << RCC_APB1ENR1_TIM14EN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR1_TIM14EN                    RCC_APB1ENR1_TIM14EN_Msk             /*!< TIM14 enable */
+#define RCC_APB1ENR1_LPTIM1EN_Pos               (9U)
+#define RCC_APB1ENR1_LPTIM1EN_Msk               (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LPTIM1EN                   RCC_APB1ENR1_LPTIM1EN_Msk            /*!< LPTIM1 enable */
+#define RCC_APB1ENR1_WWDGEN_Pos                 (11U)
+#define RCC_APB1ENR1_WWDGEN_Msk                 (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                     RCC_APB1ENR1_WWDGEN_Msk              /*!< WWDG enable */
+#define RCC_APB1ENR1_TIM10EN_Pos                (12U)
+#define RCC_APB1ENR1_TIM10EN_Msk                (0x1UL << RCC_APB1ENR1_TIM10EN_Pos)   /*!< 0x00001000 */
+#define RCC_APB1ENR1_TIM10EN                    RCC_APB1ENR1_TIM10EN_Msk             /*!< TIM10 enable */
+#define RCC_APB1ENR1_TIM11EN_Pos                (13U)
+#define RCC_APB1ENR1_TIM11EN_Msk                (0x1UL << RCC_APB1ENR1_TIM11EN_Pos)   /*!< 0x00002000 */
+#define RCC_APB1ENR1_TIM11EN                    RCC_APB1ENR1_TIM11EN_Msk             /*!< TIM11 enable */
+#define RCC_APB1ENR1_SPI2EN_Pos                 (14U)
+#define RCC_APB1ENR1_SPI2EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                     RCC_APB1ENR1_SPI2EN_Msk              /*!< SPI2 enable */
+#define RCC_APB1ENR1_SPI3EN_Pos                 (15U)
+#define RCC_APB1ENR1_SPI3EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                     RCC_APB1ENR1_SPI3EN_Msk              /*!< SPI3 enable */
+#define RCC_APB1ENR1_SPDIFRX1EN_Pos             (16U)
+#define RCC_APB1ENR1_SPDIFRX1EN_Msk             (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */
+#define RCC_APB1ENR1_SPDIFRX1EN                 RCC_APB1ENR1_SPDIFRX1EN_Msk          /*!< SPDIFRX1 enable */
+#define RCC_APB1ENR1_USART2EN_Pos               (17U)
+#define RCC_APB1ENR1_USART2EN_Msk               (0x1UL << RCC_APB1ENR1_USART2EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                   RCC_APB1ENR1_USART2EN_Msk            /*!< USART2 enable */
+#define RCC_APB1ENR1_USART3EN_Pos               (18U)
+#define RCC_APB1ENR1_USART3EN_Msk               (0x1UL << RCC_APB1ENR1_USART3EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                   RCC_APB1ENR1_USART3EN_Msk            /*!< USART3 enable */
+#define RCC_APB1ENR1_UART4EN_Pos                (19U)
+#define RCC_APB1ENR1_UART4EN_Msk                (0x1UL << RCC_APB1ENR1_UART4EN_Pos)   /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                    RCC_APB1ENR1_UART4EN_Msk             /*!< UART4 enable */
+#define RCC_APB1ENR1_UART5EN_Pos                (20U)
+#define RCC_APB1ENR1_UART5EN_Msk                (0x1UL << RCC_APB1ENR1_UART5EN_Pos)   /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                    RCC_APB1ENR1_UART5EN_Msk             /*!< UART5 enable */
+#define RCC_APB1ENR1_I2C1EN_Pos                 (21U)
+#define RCC_APB1ENR1_I2C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                     RCC_APB1ENR1_I2C1EN_Msk              /*!< I2C1 enable */
+#define RCC_APB1ENR1_I2C2EN_Pos                 (22U)
+#define RCC_APB1ENR1_I2C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                     RCC_APB1ENR1_I2C2EN_Msk              /*!< I2C2 enable */
+#define RCC_APB1ENR1_I2C3EN_Pos                 (23U)
+#define RCC_APB1ENR1_I2C3EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                     RCC_APB1ENR1_I2C3EN_Msk              /*!< I2C3 enable */
+#define RCC_APB1ENR1_I3C1EN_Pos                 (24U)
+#define RCC_APB1ENR1_I3C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C1EN_Pos)    /*!< 0x01000000 */
+#define RCC_APB1ENR1_I3C1EN                     RCC_APB1ENR1_I3C1EN_Msk              /*!< I3C1 enable */
+#define RCC_APB1ENR1_I3C2EN_Pos                 (25U)
+#define RCC_APB1ENR1_I3C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C2EN_Pos)    /*!< 0x02000000 */
+#define RCC_APB1ENR1_I3C2EN                     RCC_APB1ENR1_I3C2EN_Msk              /*!< I3C2 enable */
+#define RCC_APB1ENR1_UART7EN_Pos                (30U)
+#define RCC_APB1ENR1_UART7EN_Msk                (0x1UL << RCC_APB1ENR1_UART7EN_Pos)   /*!< 0x40000000 */
+#define RCC_APB1ENR1_UART7EN                    RCC_APB1ENR1_UART7EN_Msk             /*!< UART7 enable */
+#define RCC_APB1ENR1_UART8EN_Pos                (31U)
+#define RCC_APB1ENR1_UART8EN_Msk                (0x1UL << RCC_APB1ENR1_UART8EN_Pos)   /*!< 0x80000000 */
+#define RCC_APB1ENR1_UART8EN                    RCC_APB1ENR1_UART8EN_Msk             /*!< UART8 enable */
+
+/*****************  Bit definition for RCC_APB1ENR2 register  *****************/
+#define RCC_APB1ENR2_MDIOSEN_Pos                (5U)
+#define RCC_APB1ENR2_MDIOSEN_Msk                (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos)   /*!< 0x00000020 */
+#define RCC_APB1ENR2_MDIOSEN                    RCC_APB1ENR2_MDIOSEN_Msk             /*!< MDIOS enable */
+#define RCC_APB1ENR2_FDCANEN_Pos                (8U)
+#define RCC_APB1ENR2_FDCANEN_Msk                (0x1UL << RCC_APB1ENR2_FDCANEN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR2_FDCANEN                    RCC_APB1ENR2_FDCANEN_Msk             /*!< FDCAN enable */
+#define RCC_APB1ENR2_UCPD1EN_Pos                (18U)
+#define RCC_APB1ENR2_UCPD1EN_Msk                (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB1ENR2_UCPD1EN                    RCC_APB1ENR2_UCPD1EN_Msk             /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                  (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                  (0x1UL << RCC_APB2ENR_TIM1EN_Pos)     /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                      RCC_APB2ENR_TIM1EN_Msk               /*!< TIM1 enable */
+#define RCC_APB2ENR_TIM8EN_Pos                  (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                  (0x1UL << RCC_APB2ENR_TIM8EN_Pos)     /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                      RCC_APB2ENR_TIM8EN_Msk               /*!< TIM8 enable */
+#define RCC_APB2ENR_USART1EN_Pos                (4U)
+#define RCC_APB2ENR_USART1EN_Msk                (0x1UL << RCC_APB2ENR_USART1EN_Pos)   /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                    RCC_APB2ENR_USART1EN_Msk             /*!< USART1 enable */
+#define RCC_APB2ENR_USART6EN_Pos                (5U)
+#define RCC_APB2ENR_USART6EN_Msk                (0x1UL << RCC_APB2ENR_USART6EN_Pos)   /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                    RCC_APB2ENR_USART6EN_Msk             /*!< USART6 enable */
+#define RCC_APB2ENR_UART9EN_Pos                 (6U)
+#define RCC_APB2ENR_UART9EN_Msk                 (0x1UL << RCC_APB2ENR_UART9EN_Pos)    /*!< 0x00000040 */
+#define RCC_APB2ENR_UART9EN                     RCC_APB2ENR_UART9EN_Msk              /*!< UART9 enable */
+#define RCC_APB2ENR_USART10EN_Pos               (7U)
+#define RCC_APB2ENR_USART10EN_Msk               (0x1UL << RCC_APB2ENR_USART10EN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk            /*!< USART10 enable */
+#define RCC_APB2ENR_SPI1EN_Pos                  (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                  (0x1UL << RCC_APB2ENR_SPI1EN_Pos)     /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                      RCC_APB2ENR_SPI1EN_Msk               /*!< SPI1 enable */
+#define RCC_APB2ENR_SPI4EN_Pos                  (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                  (0x1UL << RCC_APB2ENR_SPI4EN_Pos)     /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                      RCC_APB2ENR_SPI4EN_Msk               /*!< SPI4 enable */
+#define RCC_APB2ENR_TIM18EN_Pos                 (15U)
+#define RCC_APB2ENR_TIM18EN_Msk                 (0x1UL << RCC_APB2ENR_TIM18EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB2ENR_TIM18EN                     RCC_APB2ENR_TIM18EN_Msk              /*!< TIM18 enable */
+#define RCC_APB2ENR_TIM15EN_Pos                 (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                 (0x1UL << RCC_APB2ENR_TIM15EN_Pos)    /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                     RCC_APB2ENR_TIM15EN_Msk              /*!< TIM15 enable */
+#define RCC_APB2ENR_TIM16EN_Pos                 (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                 (0x1UL << RCC_APB2ENR_TIM16EN_Pos)    /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                     RCC_APB2ENR_TIM16EN_Msk              /*!< TIM16 enable */
+#define RCC_APB2ENR_TIM17EN_Pos                 (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                 (0x1UL << RCC_APB2ENR_TIM17EN_Pos)    /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                     RCC_APB2ENR_TIM17EN_Msk              /*!< TIM17 enable */
+#define RCC_APB2ENR_TIM9EN_Pos                  (19U)
+#define RCC_APB2ENR_TIM9EN_Msk                  (0x1UL << RCC_APB2ENR_TIM9EN_Pos)     /*!< 0x00080000 */
+#define RCC_APB2ENR_TIM9EN                      RCC_APB2ENR_TIM9EN_Msk               /*!< TIM9 enable */
+#define RCC_APB2ENR_SPI5EN_Pos                  (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                  (0x1UL << RCC_APB2ENR_SPI5EN_Pos)     /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                      RCC_APB2ENR_SPI5EN_Msk               /*!< SPI5 enable */
+#define RCC_APB2ENR_SAI1EN_Pos                  (21U)
+#define RCC_APB2ENR_SAI1EN_Msk                  (0x1UL << RCC_APB2ENR_SAI1EN_Pos)     /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                      RCC_APB2ENR_SAI1EN_Msk               /*!< SAI1 enable */
+#define RCC_APB2ENR_SAI2EN_Pos                  (22U)
+#define RCC_APB2ENR_SAI2EN_Msk                  (0x1UL << RCC_APB2ENR_SAI2EN_Pos)     /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                      RCC_APB2ENR_SAI2EN_Msk               /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_DFTEN_Pos                   (2U)
+#define RCC_APB3ENR_DFTEN_Msk                   (0x1UL << RCC_APB3ENR_DFTEN_Pos)      /*!< 0x00000004 */
+#define RCC_APB3ENR_DFTEN                       RCC_APB3ENR_DFTEN_Msk                /*!< DFT enable */
+
+/*****************  Bit definition for RCC_APB4ENR1 register  *****************/
+#define RCC_APB4ENR1_HDPEN_Pos                  (2U)
+#define RCC_APB4ENR1_HDPEN_Msk                  (0x1UL << RCC_APB4ENR1_HDPEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR1_HDPEN                      RCC_APB4ENR1_HDPEN_Msk               /*!< HDP enable */
+#define RCC_APB4ENR1_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR1_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR1_LPUART1EN                  RCC_APB4ENR1_LPUART1EN_Msk           /*!< LPUART1 enable */
+#define RCC_APB4ENR1_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR1_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR1_SPI6EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB4ENR1_SPI6EN                     RCC_APB4ENR1_SPI6EN_Msk              /*!< SPI6 enable */
+#define RCC_APB4ENR1_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR1_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR1_I2C4EN_Pos)    /*!< 0x00000080 */
+#define RCC_APB4ENR1_I2C4EN                     RCC_APB4ENR1_I2C4EN_Msk              /*!< I2C4 enable */
+#define RCC_APB4ENR1_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR1_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4ENR1_LPTIM2EN                   RCC_APB4ENR1_LPTIM2EN_Msk            /*!< LPTIM2 enable */
+#define RCC_APB4ENR1_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR1_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4ENR1_LPTIM3EN                   RCC_APB4ENR1_LPTIM3EN_Msk            /*!< LPTIM3 enable */
+#define RCC_APB4ENR1_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR1_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4ENR1_LPTIM4EN                   RCC_APB4ENR1_LPTIM4EN_Msk            /*!< LPTIM4 enable */
+#define RCC_APB4ENR1_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR1_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4ENR1_LPTIM5EN                   RCC_APB4ENR1_LPTIM5EN_Msk            /*!< LPTIM5 enable */
+#define RCC_APB4ENR1_VREFBUFEN_Pos              (15U)
+#define RCC_APB4ENR1_VREFBUFEN_Msk              (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR1_VREFBUFEN                  RCC_APB4ENR1_VREFBUFEN_Msk           /*!< VREFBUF enable */
+#define RCC_APB4ENR1_RTCEN_Pos                  (16U)
+#define RCC_APB4ENR1_RTCEN_Msk                  (0x1UL << RCC_APB4ENR1_RTCEN_Pos)     /*!< 0x00010000 */
+#define RCC_APB4ENR1_RTCEN                      RCC_APB4ENR1_RTCEN_Msk               /*!< RTC enable */
+#define RCC_APB4ENR1_RTCAPBEN_Pos               (17U)
+#define RCC_APB4ENR1_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4ENR1_RTCAPBEN                   RCC_APB4ENR1_RTCAPBEN_Msk            /*!< RTCAPB enable */
+
+/*****************  Bit definition for RCC_APB4ENR2 register  *****************/
+#define RCC_APB4ENR2_SYSCFGEN_Pos               (0U)
+#define RCC_APB4ENR2_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4ENR2_SYSCFGEN                   RCC_APB4ENR2_SYSCFGEN_Msk            /*!< SYSCFG enable */
+#define RCC_APB4ENR2_BSECEN_Pos                 (1U)
+#define RCC_APB4ENR2_BSECEN_Msk                 (0x1UL << RCC_APB4ENR2_BSECEN_Pos)    /*!< 0x00000002 */
+#define RCC_APB4ENR2_BSECEN                     RCC_APB4ENR2_BSECEN_Msk              /*!< BSEC enable */
+#define RCC_APB4ENR2_DTSEN_Pos                  (2U)
+#define RCC_APB4ENR2_DTSEN_Msk                  (0x1UL << RCC_APB4ENR2_DTSEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR2_DTSEN                      RCC_APB4ENR2_DTSEN_Msk               /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENR register  ******************/
+#define RCC_APB5ENR_LTDCEN_Pos                  (1U)
+#define RCC_APB5ENR_LTDCEN_Msk                  (0x1UL << RCC_APB5ENR_LTDCEN_Pos)     /*!< 0x00000002 */
+#define RCC_APB5ENR_LTDCEN                      RCC_APB5ENR_LTDCEN_Msk               /*!< LTDC enable */
+#define RCC_APB5ENR_DCMIPPEN_Pos                (2U)
+#define RCC_APB5ENR_DCMIPPEN_Msk                (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos)   /*!< 0x00000004 */
+#define RCC_APB5ENR_DCMIPPEN                    RCC_APB5ENR_DCMIPPEN_Msk             /*!< DCMIPP enable */
+#define RCC_APB5ENR_GFXTIMEN_Pos                (4U)
+#define RCC_APB5ENR_GFXTIMEN_Msk                (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos)   /*!< 0x00000010 */
+#define RCC_APB5ENR_GFXTIMEN                    RCC_APB5ENR_GFXTIMEN_Msk             /*!< GFXTIM enable */
+#define RCC_APB5ENR_VENCEN_Pos                  (5U)
+#define RCC_APB5ENR_VENCEN_Msk                  (0x1UL << RCC_APB5ENR_VENCEN_Pos)     /*!< 0x00000020 */
+#define RCC_APB5ENR_VENCEN                      RCC_APB5ENR_VENCEN_Msk               /*!< VENC enable */
+#define RCC_APB5ENR_CSIEN_Pos                   (6U)
+#define RCC_APB5ENR_CSIEN_Msk                   (0x1UL << RCC_APB5ENR_CSIEN_Pos)      /*!< 0x00000040 */
+#define RCC_APB5ENR_CSIEN                       RCC_APB5ENR_CSIEN_Msk                /*!< CSI enable */
+
+/*****************  Bit definition for RCC_BUSLPENR register  *****************/
+#define RCC_BUSLPENR_ACLKNLPEN_Pos              (0U)
+#define RCC_BUSLPENR_ACLKNLPEN_Msk              (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENR_ACLKNLPEN                  RCC_BUSLPENR_ACLKNLPEN_Msk           /*!< ACLKN enable  */
+#define RCC_BUSLPENR_ACLKNCLPEN_Pos             (1U)
+#define RCC_BUSLPENR_ACLKNCLPEN_Msk             (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */
+#define RCC_BUSLPENR_ACLKNCLPEN                 RCC_BUSLPENR_ACLKNCLPEN_Msk          /*!< ACLKNC enable */
+
+/****************  Bit definition for RCC_MISCLPENR register  *****************/
+#define RCC_MISCLPENR_DBGLPEN_Pos               (0U)
+#define RCC_MISCLPENR_DBGLPEN_Msk               (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MISCLPENR_DBGLPEN                   RCC_MISCLPENR_DBGLPEN_Msk            /*!< DBG enable  */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos       (3U)
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk       (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos)      /*!< 0x00000008 */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN           RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk    /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENR_PERLPEN_Pos               (6U)
+#define RCC_MISCLPENR_PERLPEN_Msk               (0x1UL << RCC_MISCLPENR_PERLPEN_Pos)  /*!< 0x00000040 */
+#define RCC_MISCLPENR_PERLPEN                   RCC_MISCLPENR_PERLPEN_Msk            /*!< PER enable  */
+
+/*****************  Bit definition for RCC_MEMLPENR register  *****************/
+#define RCC_MEMLPENR_AXISRAM3LPEN_Pos           (0U)
+#define RCC_MEMLPENR_AXISRAM3LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMLPENR_AXISRAM3LPEN               RCC_MEMLPENR_AXISRAM3LPEN_Msk        /*!< AXISRAM3 enable */
+#define RCC_MEMLPENR_AXISRAM4LPEN_Pos           (1U)
+#define RCC_MEMLPENR_AXISRAM4LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMLPENR_AXISRAM4LPEN               RCC_MEMLPENR_AXISRAM4LPEN_Msk        /*!< AXISRAM4 enable */
+#define RCC_MEMLPENR_AXISRAM5LPEN_Pos           (2U)
+#define RCC_MEMLPENR_AXISRAM5LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMLPENR_AXISRAM5LPEN               RCC_MEMLPENR_AXISRAM5LPEN_Msk        /*!< AXISRAM5 enable */
+#define RCC_MEMLPENR_AXISRAM6LPEN_Pos           (3U)
+#define RCC_MEMLPENR_AXISRAM6LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMLPENR_AXISRAM6LPEN               RCC_MEMLPENR_AXISRAM6LPEN_Msk        /*!< AXISRAM6 enable */
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos           (4U)
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMLPENR_AHBSRAM1LPEN               RCC_MEMLPENR_AHBSRAM1LPEN_Msk        /*!< AHBSRAM1 enable */
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos           (5U)
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMLPENR_AHBSRAM2LPEN               RCC_MEMLPENR_AHBSRAM2LPEN_Msk        /*!< AHBSRAM2 enable */
+#define RCC_MEMLPENR_BKPSRAMLPEN_Pos            (6U)
+#define RCC_MEMLPENR_BKPSRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MEMLPENR_BKPSRAMLPEN                RCC_MEMLPENR_BKPSRAMLPEN_Msk         /*!< BKPSRAM enable */
+#define RCC_MEMLPENR_AXISRAM1LPEN_Pos           (7U)
+#define RCC_MEMLPENR_AXISRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMLPENR_AXISRAM1LPEN               RCC_MEMLPENR_AXISRAM1LPEN_Msk        /*!< AXISRAM1 enable */
+#define RCC_MEMLPENR_AXISRAM2LPEN_Pos           (8U)
+#define RCC_MEMLPENR_AXISRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMLPENR_AXISRAM2LPEN               RCC_MEMLPENR_AXISRAM2LPEN_Msk        /*!< AXISRAM2 enable */
+#define RCC_MEMLPENR_FLEXRAMLPEN_Pos            (9U)
+#define RCC_MEMLPENR_FLEXRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MEMLPENR_FLEXRAMLPEN                RCC_MEMLPENR_FLEXRAMLPEN_Msk         /*!< FLEXRAM enable */
+#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos        (10U)
+#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk        (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos)     /*!< 0x00000400 */
+#define RCC_MEMLPENR_CACHEAXIRAMLPEN            RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk     /*!< CACHEAXIRAM enable */
+#define RCC_MEMLPENR_VENCRAMLPEN_Pos            (11U)
+#define RCC_MEMLPENR_VENCRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MEMLPENR_VENCRAMLPEN                RCC_MEMLPENR_VENCRAMLPEN_Msk         /*!< VENCRAM enable */
+#define RCC_MEMLPENR_BOOTROMLPEN_Pos            (12U)
+#define RCC_MEMLPENR_BOOTROMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MEMLPENR_BOOTROMLPEN                RCC_MEMLPENR_BOOTROMLPEN_Msk         /*!< Boot ROM enable */
+
+/****************  Bit definition for RCC_AHB1LPENR register  *****************/
+#define RCC_AHB1LPENR_GPDMA1LPEN_Pos            (4U)
+#define RCC_AHB1LPENR_GPDMA1LPEN_Msk            (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPDMA1LPEN                RCC_AHB1LPENR_GPDMA1LPEN_Msk         /*!< GPDMA1 enable */
+#define RCC_AHB1LPENR_ADC12LPEN_Pos             (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk             (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                 RCC_AHB1LPENR_ADC12LPEN_Msk          /*!< ADC12 enable */
+
+/****************  Bit definition for RCC_AHB2LPENR register  *****************/
+#define RCC_AHB2LPENR_RAMCFGLPEN_Pos            (12U)
+#define RCC_AHB2LPENR_RAMCFGLPEN_Msk            (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2LPENR_RAMCFGLPEN                RCC_AHB2LPENR_RAMCFGLPEN_Msk         /*!< RAMCFG enable */
+#define RCC_AHB2LPENR_MDF1LPEN_Pos              (16U)
+#define RCC_AHB2LPENR_MDF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENR_MDF1LPEN                  RCC_AHB2LPENR_MDF1LPEN_Msk           /*!< MDF1 enable */
+#define RCC_AHB2LPENR_ADF1LPEN_Pos              (17U)
+#define RCC_AHB2LPENR_ADF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENR_ADF1LPEN                  RCC_AHB2LPENR_ADF1LPEN_Msk           /*!< ADF1 enable */
+
+/****************  Bit definition for RCC_AHB3LPENR register  *****************/
+#define RCC_AHB3LPENR_RNGLPEN_Pos               (0U)
+#define RCC_AHB3LPENR_RNGLPEN_Msk               (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3LPENR_RNGLPEN                   RCC_AHB3LPENR_RNGLPEN_Msk            /*!< RNG enable */
+#define RCC_AHB3LPENR_HASHLPEN_Pos              (1U)
+#define RCC_AHB3LPENR_HASHLPEN_Msk              (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_HASHLPEN                  RCC_AHB3LPENR_HASHLPEN_Msk           /*!< HASH enable */
+#define RCC_AHB3LPENR_PKALPEN_Pos               (8U)
+#define RCC_AHB3LPENR_PKALPEN_Msk               (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3LPENR_PKALPEN                   RCC_AHB3LPENR_PKALPEN_Msk            /*!< PKA enable */
+#define RCC_AHB3LPENR_RIFSCLPEN_Pos             (9U)
+#define RCC_AHB3LPENR_RIFSCLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */
+#define RCC_AHB3LPENR_RIFSCLPEN                 RCC_AHB3LPENR_RIFSCLPEN_Msk          /*!< RIFSC enable */
+#define RCC_AHB3LPENR_IACLPEN_Pos               (10U)
+#define RCC_AHB3LPENR_IACLPEN_Msk               (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3LPENR_IACLPEN                   RCC_AHB3LPENR_IACLPEN_Msk            /*!< IAC enable */
+#define RCC_AHB3LPENR_RISAFLPEN_Pos             (14U)
+#define RCC_AHB3LPENR_RISAFLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB3LPENR_RISAFLPEN                 RCC_AHB3LPENR_RISAFLPEN_Msk          /*!< RISAF enable */
+
+/****************  Bit definition for RCC_AHB4LPENR register  *****************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos             (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                 RCC_AHB4LPENR_GPIOALPEN_Msk          /*!< GPIO A enable */
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos             (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                 RCC_AHB4LPENR_GPIOBLPEN_Msk          /*!< GPIO B enable */
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos             (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                 RCC_AHB4LPENR_GPIOCLPEN_Msk          /*!< GPIO C enable */
+#define RCC_AHB4LPENR_GPIODLPEN_Pos             (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                 RCC_AHB4LPENR_GPIODLPEN_Msk          /*!< GPIO D enable */
+#define RCC_AHB4LPENR_GPIOELPEN_Pos             (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                 RCC_AHB4LPENR_GPIOELPEN_Msk          /*!< GPIO E enable */
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos             (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                 RCC_AHB4LPENR_GPIOFLPEN_Msk          /*!< GPIO F enable */
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos             (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                 RCC_AHB4LPENR_GPIOGLPEN_Msk          /*!< GPIO G enable */
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos             (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                 RCC_AHB4LPENR_GPIOHLPEN_Msk          /*!< GPIO H enable */
+#define RCC_AHB4LPENR_GPIONLPEN_Pos             (13U)
+#define RCC_AHB4LPENR_GPIONLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB4LPENR_GPIONLPEN                 RCC_AHB4LPENR_GPIONLPEN_Msk          /*!< GPIO N enable */
+#define RCC_AHB4LPENR_GPIOOLPEN_Pos             (14U)
+#define RCC_AHB4LPENR_GPIOOLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB4LPENR_GPIOOLPEN                 RCC_AHB4LPENR_GPIOOLPEN_Msk          /*!< GPIO O enable */
+#define RCC_AHB4LPENR_GPIOPLPEN_Pos             (15U)
+#define RCC_AHB4LPENR_GPIOPLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */
+#define RCC_AHB4LPENR_GPIOPLPEN                 RCC_AHB4LPENR_GPIOPLPEN_Msk          /*!< GPIO P enable */
+#define RCC_AHB4LPENR_GPIOQLPEN_Pos             (16U)
+#define RCC_AHB4LPENR_GPIOQLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */
+#define RCC_AHB4LPENR_GPIOQLPEN                 RCC_AHB4LPENR_GPIOQLPEN_Msk          /*!< GPIO Q enable */
+#define RCC_AHB4LPENR_PWRLPEN_Pos               (18U)
+#define RCC_AHB4LPENR_PWRLPEN_Msk               (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4LPENR_PWRLPEN                   RCC_AHB4LPENR_PWRLPEN_Msk            /*!< PWR enable */
+#define RCC_AHB4LPENR_CRCLPEN_Pos               (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk               (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                   RCC_AHB4LPENR_CRCLPEN_Msk            /*!< CRC enable */
+
+/****************  Bit definition for RCC_AHB5LPENR register  *****************/
+#define RCC_AHB5LPENR_HPDMA1LPEN_Pos            (0U)
+#define RCC_AHB5LPENR_HPDMA1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB5LPENR_HPDMA1LPEN                RCC_AHB5LPENR_HPDMA1LPEN_Msk         /*!< HPDMA1 enable */
+#define RCC_AHB5LPENR_DMA2DLPEN_Pos             (1U)
+#define RCC_AHB5LPENR_DMA2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB5LPENR_DMA2DLPEN                 RCC_AHB5LPENR_DMA2DLPEN_Msk          /*!< DMA2D enable */
+#define RCC_AHB5LPENR_JPEGLPEN_Pos              (3U)
+#define RCC_AHB5LPENR_JPEGLPEN_Msk              (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENR_JPEGLPEN                  RCC_AHB5LPENR_JPEGLPEN_Msk           /*!< JPEG enable */
+#define RCC_AHB5LPENR_FMCLPEN_Pos               (4U)
+#define RCC_AHB5LPENR_FMCLPEN_Msk               (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5LPENR_FMCLPEN                   RCC_AHB5LPENR_FMCLPEN_Msk            /*!< FMC enable */
+#define RCC_AHB5LPENR_XSPI1LPEN_Pos             (5U)
+#define RCC_AHB5LPENR_XSPI1LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB5LPENR_XSPI1LPEN                 RCC_AHB5LPENR_XSPI1LPEN_Msk          /*!< XSPI1 enable */
+#define RCC_AHB5LPENR_PSSILPEN_Pos              (6U)
+#define RCC_AHB5LPENR_PSSILPEN_Msk              (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENR_PSSILPEN                  RCC_AHB5LPENR_PSSILPEN_Msk           /*!< PSSI enable */
+#define RCC_AHB5LPENR_SDMMC2LPEN_Pos            (7U)
+#define RCC_AHB5LPENR_SDMMC2LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB5LPENR_SDMMC2LPEN                RCC_AHB5LPENR_SDMMC2LPEN_Msk         /*!< SDMMC2 enable */
+#define RCC_AHB5LPENR_SDMMC1LPEN_Pos            (8U)
+#define RCC_AHB5LPENR_SDMMC1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB5LPENR_SDMMC1LPEN                RCC_AHB5LPENR_SDMMC1LPEN_Msk         /*!< SDMMC1 enable */
+#define RCC_AHB5LPENR_XSPI2LPEN_Pos             (12U)
+#define RCC_AHB5LPENR_XSPI2LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */
+#define RCC_AHB5LPENR_XSPI2LPEN                 RCC_AHB5LPENR_XSPI2LPEN_Msk          /*!< XSPI2 enable */
+#define RCC_AHB5LPENR_XSPIMLPEN_Pos             (13U)
+#define RCC_AHB5LPENR_XSPIMLPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB5LPENR_XSPIMLPEN                 RCC_AHB5LPENR_XSPIMLPEN_Msk          /*!< XSPIM enable */
+#define RCC_AHB5LPENR_XSPI3LPEN_Pos             (17U)
+#define RCC_AHB5LPENR_XSPI3LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */
+#define RCC_AHB5LPENR_XSPI3LPEN                 RCC_AHB5LPENR_XSPI3LPEN_Msk          /*!< XSPI3 enable */
+#define RCC_AHB5LPENR_GFXMMULPEN_Pos            (19U)
+#define RCC_AHB5LPENR_GFXMMULPEN_Msk            (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB5LPENR_GFXMMULPEN                RCC_AHB5LPENR_GFXMMULPEN_Msk         /*!< GFXMMU enable */
+#define RCC_AHB5LPENR_GPU2DLPEN_Pos             (20U)
+#define RCC_AHB5LPENR_GPU2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */
+#define RCC_AHB5LPENR_GPU2DLPEN                 RCC_AHB5LPENR_GPU2DLPEN_Msk          /*!< GPU2D enable */
+#define RCC_AHB5LPENR_ETH1MACLPEN_Pos           (22U)
+#define RCC_AHB5LPENR_ETH1MACLPEN_Msk           (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5LPENR_ETH1MACLPEN               RCC_AHB5LPENR_ETH1MACLPEN_Msk        /*!< ETH1MAC enable */
+#define RCC_AHB5LPENR_ETH1TXLPEN_Pos            (23U)
+#define RCC_AHB5LPENR_ETH1TXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB5LPENR_ETH1TXLPEN                RCC_AHB5LPENR_ETH1TXLPEN_Msk         /*!< ETH1TX enable */
+#define RCC_AHB5LPENR_ETH1RXLPEN_Pos            (24U)
+#define RCC_AHB5LPENR_ETH1RXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB5LPENR_ETH1RXLPEN                RCC_AHB5LPENR_ETH1RXLPEN_Msk         /*!< ETH1RX enable */
+#define RCC_AHB5LPENR_ETH1LPEN_Pos              (25U)
+#define RCC_AHB5LPENR_ETH1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENR_ETH1LPEN                  RCC_AHB5LPENR_ETH1LPEN_Msk           /*!< ETH1 enable */
+#define RCC_AHB5LPENR_OTG1LPEN_Pos              (26U)
+#define RCC_AHB5LPENR_OTG1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENR_OTG1LPEN                  RCC_AHB5LPENR_OTG1LPEN_Msk           /*!< OTG1 enable */
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos           (27U)
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5LPENR_OTGPHY1LPEN               RCC_AHB5LPENR_OTGPHY1LPEN_Msk        /*!< OTGPHY1 enable */
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos           (28U)
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5LPENR_OTGPHY2LPEN               RCC_AHB5LPENR_OTGPHY2LPEN_Msk        /*!< OTGPHY2 enable */
+#define RCC_AHB5LPENR_OTG2LPEN_Pos              (29U)
+#define RCC_AHB5LPENR_OTG2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENR_OTG2LPEN                  RCC_AHB5LPENR_OTG2LPEN_Msk           /*!< OTG2 enable */
+#define RCC_AHB5LPENR_CACHEAXILPEN_Pos          (30U)
+#define RCC_AHB5LPENR_CACHEAXILPEN_Msk          (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos)   /*!< 0x40000000 */
+#define RCC_AHB5LPENR_CACHEAXILPEN              RCC_AHB5LPENR_CACHEAXILPEN_Msk       /*!< CACHEAXI enable */
+#define RCC_AHB5LPENR_NPULPEN_Pos               (31U)
+#define RCC_AHB5LPENR_NPULPEN_Msk               (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos)  /*!< 0x80000000 */
+#define RCC_AHB5LPENR_NPULPEN                   RCC_AHB5LPENR_NPULPEN_Msk            /*!< NPU enable */
+
+/****************  Bit definition for RCC_APB1LPENR1 register  ****************/
+#define RCC_APB1LPENR1_TIM2LPEN_Pos             (0U)
+#define RCC_APB1LPENR1_TIM2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */
+#define RCC_APB1LPENR1_TIM2LPEN                 RCC_APB1LPENR1_TIM2LPEN_Msk          /*!< TIM2 enable */
+#define RCC_APB1LPENR1_TIM3LPEN_Pos             (1U)
+#define RCC_APB1LPENR1_TIM3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB1LPENR1_TIM3LPEN                 RCC_APB1LPENR1_TIM3LPEN_Msk          /*!< TIM3 enable */
+#define RCC_APB1LPENR1_TIM4LPEN_Pos             (2U)
+#define RCC_APB1LPENR1_TIM4LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */
+#define RCC_APB1LPENR1_TIM4LPEN                 RCC_APB1LPENR1_TIM4LPEN_Msk          /*!< TIM4 enable */
+#define RCC_APB1LPENR1_TIM5LPEN_Pos             (3U)
+#define RCC_APB1LPENR1_TIM5LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */
+#define RCC_APB1LPENR1_TIM5LPEN                 RCC_APB1LPENR1_TIM5LPEN_Msk          /*!< TIM5 enable */
+#define RCC_APB1LPENR1_TIM6LPEN_Pos             (4U)
+#define RCC_APB1LPENR1_TIM6LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */
+#define RCC_APB1LPENR1_TIM6LPEN                 RCC_APB1LPENR1_TIM6LPEN_Msk          /*!< TIM6 enable */
+#define RCC_APB1LPENR1_TIM7LPEN_Pos             (5U)
+#define RCC_APB1LPENR1_TIM7LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB1LPENR1_TIM7LPEN                 RCC_APB1LPENR1_TIM7LPEN_Msk          /*!< TIM7 enable */
+#define RCC_APB1LPENR1_TIM12LPEN_Pos            (6U)
+#define RCC_APB1LPENR1_TIM12LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR1_TIM12LPEN                RCC_APB1LPENR1_TIM12LPEN_Msk         /*!< TIM12 enable */
+#define RCC_APB1LPENR1_TIM13LPEN_Pos            (7U)
+#define RCC_APB1LPENR1_TIM13LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR1_TIM13LPEN                RCC_APB1LPENR1_TIM13LPEN_Msk         /*!< TIM13 enable */
+#define RCC_APB1LPENR1_TIM14LPEN_Pos            (8U)
+#define RCC_APB1LPENR1_TIM14LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR1_TIM14LPEN                RCC_APB1LPENR1_TIM14LPEN_Msk         /*!< TIM14 enable */
+#define RCC_APB1LPENR1_LPTIM1LPEN_Pos           (9U)
+#define RCC_APB1LPENR1_LPTIM1LPEN_Msk           (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1LPENR1_LPTIM1LPEN               RCC_APB1LPENR1_LPTIM1LPEN_Msk        /*!< LPTIM1 enable */
+#define RCC_APB1LPENR1_WWDGLPEN_Pos             (11U)
+#define RCC_APB1LPENR1_WWDGLPEN_Msk             (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */
+#define RCC_APB1LPENR1_WWDGLPEN                 RCC_APB1LPENR1_WWDGLPEN_Msk          /*!< WWDG enable */
+#define RCC_APB1LPENR1_TIM10LPEN_Pos            (12U)
+#define RCC_APB1LPENR1_TIM10LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB1LPENR1_TIM10LPEN                RCC_APB1LPENR1_TIM10LPEN_Msk         /*!< TIM10 enable */
+#define RCC_APB1LPENR1_TIM11LPEN_Pos            (13U)
+#define RCC_APB1LPENR1_TIM11LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB1LPENR1_TIM11LPEN                RCC_APB1LPENR1_TIM11LPEN_Msk         /*!< TIM11 enable */
+#define RCC_APB1LPENR1_SPI2LPEN_Pos             (14U)
+#define RCC_APB1LPENR1_SPI2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */
+#define RCC_APB1LPENR1_SPI2LPEN                 RCC_APB1LPENR1_SPI2LPEN_Msk          /*!< SPI2 enable */
+#define RCC_APB1LPENR1_SPI3LPEN_Pos             (15U)
+#define RCC_APB1LPENR1_SPI3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB1LPENR1_SPI3LPEN                 RCC_APB1LPENR1_SPI3LPEN_Msk          /*!< SPI3 enable */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos         (16U)
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk         (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos)    /*!< 0x00010000 */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN             RCC_APB1LPENR1_SPDIFRX1LPEN_Msk      /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENR1_USART2LPEN_Pos           (17U)
+#define RCC_APB1LPENR1_USART2LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1LPENR1_USART2LPEN               RCC_APB1LPENR1_USART2LPEN_Msk        /*!< USART2 enable */
+#define RCC_APB1LPENR1_USART3LPEN_Pos           (18U)
+#define RCC_APB1LPENR1_USART3LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1LPENR1_USART3LPEN               RCC_APB1LPENR1_USART3LPEN_Msk        /*!< USART3 enable */
+#define RCC_APB1LPENR1_UART4LPEN_Pos            (19U)
+#define RCC_APB1LPENR1_UART4LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR1_UART4LPEN                RCC_APB1LPENR1_UART4LPEN_Msk         /*!< UART4 enable */
+#define RCC_APB1LPENR1_UART5LPEN_Pos            (20U)
+#define RCC_APB1LPENR1_UART5LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR1_UART5LPEN                RCC_APB1LPENR1_UART5LPEN_Msk         /*!< UART5 enable */
+#define RCC_APB1LPENR1_I2C1LPEN_Pos             (21U)
+#define RCC_APB1LPENR1_I2C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */
+#define RCC_APB1LPENR1_I2C1LPEN                 RCC_APB1LPENR1_I2C1LPEN_Msk          /*!< I2C1 enable */
+#define RCC_APB1LPENR1_I2C2LPEN_Pos             (22U)
+#define RCC_APB1LPENR1_I2C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */
+#define RCC_APB1LPENR1_I2C2LPEN                 RCC_APB1LPENR1_I2C2LPEN_Msk          /*!< I2C2 enable */
+#define RCC_APB1LPENR1_I2C3LPEN_Pos             (23U)
+#define RCC_APB1LPENR1_I2C3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */
+#define RCC_APB1LPENR1_I2C3LPEN                 RCC_APB1LPENR1_I2C3LPEN_Msk          /*!< I2C3 enable */
+#define RCC_APB1LPENR1_I3C1LPEN_Pos             (24U)
+#define RCC_APB1LPENR1_I3C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */
+#define RCC_APB1LPENR1_I3C1LPEN                 RCC_APB1LPENR1_I3C1LPEN_Msk          /*!< I3C1 enable */
+#define RCC_APB1LPENR1_I3C2LPEN_Pos             (25U)
+#define RCC_APB1LPENR1_I3C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */
+#define RCC_APB1LPENR1_I3C2LPEN                 RCC_APB1LPENR1_I3C2LPEN_Msk          /*!< I3C2 enable */
+#define RCC_APB1LPENR1_UART7LPEN_Pos            (30U)
+#define RCC_APB1LPENR1_UART7LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR1_UART7LPEN                RCC_APB1LPENR1_UART7LPEN_Msk         /*!< UART7 enable */
+#define RCC_APB1LPENR1_UART8LPEN_Pos            (31U)
+#define RCC_APB1LPENR1_UART8LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR1_UART8LPEN                RCC_APB1LPENR1_UART8LPEN_Msk         /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1LPENR2 register  ****************/
+#define RCC_APB1LPENR2_MDIOSLPEN_Pos            (5U)
+#define RCC_APB1LPENR2_MDIOSLPEN_Msk            (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR2_MDIOSLPEN                RCC_APB1LPENR2_MDIOSLPEN_Msk         /*!< MDIOS enable in Sleep mode */
+#define RCC_APB1LPENR2_FDCANLPEN_Pos            (8U)
+#define RCC_APB1LPENR2_FDCANLPEN_Msk            (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR2_FDCANLPEN                RCC_APB1LPENR2_FDCANLPEN_Msk         /*!< FDCAN enablein Sleep mode */
+#define RCC_APB1LPENR2_UCPD1LPEN_Pos            (18U)
+#define RCC_APB1LPENR2_UCPD1LPEN_Msk            (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR2_UCPD1LPEN                RCC_APB1LPENR2_UCPD1LPEN_Msk         /*!< UCPD1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_APB2LPENR register  *****************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos              (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                  RCC_APB2LPENR_TIM1LPEN_Msk           /*!< TIM1 enable */
+#define RCC_APB2LPENR_TIM8LPEN_Pos              (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                  RCC_APB2LPENR_TIM8LPEN_Msk           /*!< TIM8 enable */
+#define RCC_APB2LPENR_USART1LPEN_Pos            (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN                RCC_APB2LPENR_USART1LPEN_Msk         /*!< USART1 enable */
+#define RCC_APB2LPENR_USART6LPEN_Pos            (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN                RCC_APB2LPENR_USART6LPEN_Msk         /*!< USART6 enable */
+#define RCC_APB2LPENR_UART9LPEN_Pos             (6U)
+#define RCC_APB2LPENR_UART9LPEN_Msk             (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */
+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk          /*!< UART9 enable */
+#define RCC_APB2LPENR_USART10LPEN_Pos           (7U)
+#define RCC_APB2LPENR_USART10LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk        /*!< USART10 enable */
+#define RCC_APB2LPENR_SPI1LPEN_Pos              (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                  RCC_APB2LPENR_SPI1LPEN_Msk           /*!< SPI1 enable */
+#define RCC_APB2LPENR_SPI4LPEN_Pos              (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                  RCC_APB2LPENR_SPI4LPEN_Msk           /*!< SPI4 enable */
+#define RCC_APB2LPENR_TIM18LPEN_Pos             (15U)
+#define RCC_APB2LPENR_TIM18LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB2LPENR_TIM18LPEN                 RCC_APB2LPENR_TIM18LPEN_Msk          /*!< TIM18 enable */
+#define RCC_APB2LPENR_TIM15LPEN_Pos             (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                 RCC_APB2LPENR_TIM15LPEN_Msk          /*!< TIM15 enable */
+#define RCC_APB2LPENR_TIM16LPEN_Pos             (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                 RCC_APB2LPENR_TIM16LPEN_Msk          /*!< TIM16 enable */
+#define RCC_APB2LPENR_TIM17LPEN_Pos             (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                 RCC_APB2LPENR_TIM17LPEN_Msk          /*!< TIM17 enable */
+#define RCC_APB2LPENR_TIM9LPEN_Pos              (19U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENR_TIM9LPEN                  RCC_APB2LPENR_TIM9LPEN_Msk           /*!< TIM9 enable */
+#define RCC_APB2LPENR_SPI5LPEN_Pos              (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                  RCC_APB2LPENR_SPI5LPEN_Msk           /*!< SPI5 enable */
+#define RCC_APB2LPENR_SAI1LPEN_Pos              (21U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SAI1LPEN                  RCC_APB2LPENR_SAI1LPEN_Msk           /*!< SAI1 enable */
+#define RCC_APB2LPENR_SAI2LPEN_Pos              (22U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI2LPEN                  RCC_APB2LPENR_SAI2LPEN_Msk           /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENR register  *****************/
+#define RCC_APB3LPENR_DFTLPEN_Pos               (2U)
+#define RCC_APB3LPENR_DFTLPEN_Msk               (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos)  /*!< 0x00000004 */
+#define RCC_APB3LPENR_DFTLPEN                   RCC_APB3LPENR_DFTLPEN_Msk            /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4LPENR1 register  ****************/
+#define RCC_APB4LPENR1_HDPLPEN_Pos              (2U)
+#define RCC_APB4LPENR1_HDPLPEN_Msk              (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR1_HDPLPEN                  RCC_APB4LPENR1_HDPLPEN_Msk           /*!< HDP enable */
+#define RCC_APB4LPENR1_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR1_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos)   /*!< 0x00000008 */
+#define RCC_APB4LPENR1_LPUART1LPEN              RCC_APB4LPENR1_LPUART1LPEN_Msk       /*!< LPUART1 enable */
+#define RCC_APB4LPENR1_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR1_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB4LPENR1_SPI6LPEN                 RCC_APB4LPENR1_SPI6LPEN_Msk          /*!< SPI6 enable */
+#define RCC_APB4LPENR1_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR1_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */
+#define RCC_APB4LPENR1_I2C4LPEN                 RCC_APB4LPENR1_I2C4LPEN_Msk          /*!< I2C4 enable */
+#define RCC_APB4LPENR1_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR1_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4LPENR1_LPTIM2LPEN               RCC_APB4LPENR1_LPTIM2LPEN_Msk        /*!< LPTIM2 enable */
+#define RCC_APB4LPENR1_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR1_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4LPENR1_LPTIM3LPEN               RCC_APB4LPENR1_LPTIM3LPEN_Msk        /*!< LPTIM3 enable */
+#define RCC_APB4LPENR1_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR1_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4LPENR1_LPTIM4LPEN               RCC_APB4LPENR1_LPTIM4LPEN_Msk        /*!< LPTIM4 enable */
+#define RCC_APB4LPENR1_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR1_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4LPENR1_LPTIM5LPEN               RCC_APB4LPENR1_LPTIM5LPEN_Msk        /*!< LPTIM5 enable */
+#define RCC_APB4LPENR1_VREFBUFLPEN_Pos          (15U)
+#define RCC_APB4LPENR1_VREFBUFLPEN_Msk          (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos)   /*!< 0x00008000 */
+#define RCC_APB4LPENR1_VREFBUFLPEN              RCC_APB4LPENR1_VREFBUFLPEN_Msk       /*!< VREFBUF enable */
+#define RCC_APB4LPENR1_RTCLPEN_Pos              (16U)
+#define RCC_APB4LPENR1_RTCLPEN_Msk              (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR1_RTCLPEN                  RCC_APB4LPENR1_RTCLPEN_Msk           /*!< RTC enable */
+#define RCC_APB4LPENR1_RTCAPBLPEN_Pos           (17U)
+#define RCC_APB4LPENR1_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4LPENR1_RTCAPBLPEN               RCC_APB4LPENR1_RTCAPBLPEN_Msk        /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4LPENR2 register  ****************/
+#define RCC_APB4LPENR2_SYSCFGLPEN_Pos           (0U)
+#define RCC_APB4LPENR2_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4LPENR2_SYSCFGLPEN               RCC_APB4LPENR2_SYSCFGLPEN_Msk        /*!< SYSCFG enable */
+#define RCC_APB4LPENR2_BSECLPEN_Pos             (1U)
+#define RCC_APB4LPENR2_BSECLPEN_Msk             (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB4LPENR2_BSECLPEN                 RCC_APB4LPENR2_BSECLPEN_Msk          /*!< BSEC enable */
+#define RCC_APB4LPENR2_DTSLPEN_Pos              (2U)
+#define RCC_APB4LPENR2_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR2_DTSLPEN                  RCC_APB4LPENR2_DTSLPEN_Msk           /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENR register  *****************/
+#define RCC_APB5LPENR_LTDCLPEN_Pos              (1U)
+#define RCC_APB5LPENR_LTDCLPEN_Msk              (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENR_LTDCLPEN                  RCC_APB5LPENR_LTDCLPEN_Msk           /*!< LTDC enable */
+#define RCC_APB5LPENR_DCMIPPLPEN_Pos            (2U)
+#define RCC_APB5LPENR_DCMIPPLPEN_Msk            (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB5LPENR_DCMIPPLPEN                RCC_APB5LPENR_DCMIPPLPEN_Msk         /*!< DCMIPP enable */
+#define RCC_APB5LPENR_GFXTIMLPEN_Pos            (4U)
+#define RCC_APB5LPENR_GFXTIMLPEN_Msk            (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB5LPENR_GFXTIMLPEN                RCC_APB5LPENR_GFXTIMLPEN_Msk         /*!< GFXTIM enable */
+#define RCC_APB5LPENR_VENCLPEN_Pos              (5U)
+#define RCC_APB5LPENR_VENCLPEN_Msk              (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENR_VENCLPEN                  RCC_APB5LPENR_VENCLPEN_Msk           /*!< VENC enable */
+#define RCC_APB5LPENR_CSILPEN_Pos               (6U)
+#define RCC_APB5LPENR_CSILPEN_Msk               (0x1UL << RCC_APB5LPENR_CSILPEN_Pos)  /*!< 0x00000040 */
+#define RCC_APB5LPENR_CSILPEN                   RCC_APB5LPENR_CSILPEN_Msk            /*!< CSI enable */
+
+/*******************  Bit definition for RCC_RDCR register  *******************/
+#define RCC_RDCR_MRD_Pos                        (16U)
+#define RCC_RDCR_MRD_Msk                        (0x1FUL << RCC_RDCR_MRD_Pos)          /*!< 0x001F0000 */
+#define RCC_RDCR_MRD                            RCC_RDCR_MRD_Msk                     /*!< Minimum reset duration */
+
+/*****************  Bit definition for RCC_SECCFGR0 register  *****************/
+#define RCC_SECCFGR0_LSISEC_Pos                 (0U)
+#define RCC_SECCFGR0_LSISEC_Msk                 (0x1UL << RCC_SECCFGR0_LSISEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR0_LSISEC                     RCC_SECCFGR0_LSISEC_Msk              /*!< Secure protection of LSI oscillator configuration bits */
+#define RCC_SECCFGR0_LSESEC_Pos                 (1U)
+#define RCC_SECCFGR0_LSESEC_Msk                 (0x1UL << RCC_SECCFGR0_LSESEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR0_LSESEC                     RCC_SECCFGR0_LSESEC_Msk              /*!< Secure protection of LSE oscillator configuration bits */
+#define RCC_SECCFGR0_MSISEC_Pos                 (2U)
+#define RCC_SECCFGR0_MSISEC_Msk                 (0x1UL << RCC_SECCFGR0_MSISEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR0_MSISEC                     RCC_SECCFGR0_MSISEC_Msk              /*!< Secure protection of MSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSISEC_Pos                 (3U)
+#define RCC_SECCFGR0_HSISEC_Msk                 (0x1UL << RCC_SECCFGR0_HSISEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR0_HSISEC                     RCC_SECCFGR0_HSISEC_Msk              /*!< Secure protection of HSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSESEC_Pos                 (4U)
+#define RCC_SECCFGR0_HSESEC_Msk                 (0x1UL << RCC_SECCFGR0_HSESEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR0_HSESEC                     RCC_SECCFGR0_HSESEC_Msk              /*!< Secure protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR0 register  *****************/
+#define RCC_PRIVCFGR0_LSIPRIV_Pos               (0U)
+#define RCC_PRIVCFGR0_LSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR0_LSIPRIV                   RCC_PRIVCFGR0_LSIPRIV_Msk            /*!< Privileged protection of LSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_LSEPRIV_Pos               (1U)
+#define RCC_PRIVCFGR0_LSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR0_LSEPRIV                   RCC_PRIVCFGR0_LSEPRIV_Msk            /*!< Privileged protection of LSE oscillator configuration bits */
+#define RCC_PRIVCFGR0_MSIPRIV_Pos               (2U)
+#define RCC_PRIVCFGR0_MSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR0_MSIPRIV                   RCC_PRIVCFGR0_MSIPRIV_Msk            /*!< Privileged protection of MSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSIPRIV_Pos               (3U)
+#define RCC_PRIVCFGR0_HSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR0_HSIPRIV                   RCC_PRIVCFGR0_HSIPRIV_Msk            /*!< Privileged protection of HSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSEPRIV_Pos               (4U)
+#define RCC_PRIVCFGR0_HSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR0_HSEPRIV                   RCC_PRIVCFGR0_HSEPRIV_Msk            /*!< Privileged protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR0 register  *****************/
+#define RCC_LOCKCFGR0_LSILOCK_Pos               (0U)
+#define RCC_LOCKCFGR0_LSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR0_LSILOCK                   RCC_LOCKCFGR0_LSILOCK_Msk            /*!< Locked protection of LSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_LSELOCK_Pos               (1U)
+#define RCC_LOCKCFGR0_LSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR0_LSELOCK                   RCC_LOCKCFGR0_LSELOCK_Msk            /*!< Locked protection of LSE oscillator configuration bits */
+#define RCC_LOCKCFGR0_MSILOCK_Pos               (2U)
+#define RCC_LOCKCFGR0_MSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR0_MSILOCK                   RCC_LOCKCFGR0_MSILOCK_Msk            /*!< Locked protection of MSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSILOCK_Pos               (3U)
+#define RCC_LOCKCFGR0_HSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR0_HSILOCK                   RCC_LOCKCFGR0_HSILOCK_Msk            /*!< Locked protection of HSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSELOCK_Pos               (4U)
+#define RCC_LOCKCFGR0_HSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR0_HSELOCK                   RCC_LOCKCFGR0_HSELOCK_Msk            /*!< Locked protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR0 register  *****************/
+#define RCC_PUBCFGR0_LSIPUB_Pos                 (0U)
+#define RCC_PUBCFGR0_LSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR0_LSIPUB                     RCC_PUBCFGR0_LSIPUB_Msk              /*!< Public protection of LSI oscillator configuration bits */
+#define RCC_PUBCFGR0_LSEPUB_Pos                 (1U)
+#define RCC_PUBCFGR0_LSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR0_LSEPUB                     RCC_PUBCFGR0_LSEPUB_Msk              /*!< Public protection of LSE oscillator configuration bits */
+#define RCC_PUBCFGR0_MSIPUB_Pos                 (2U)
+#define RCC_PUBCFGR0_MSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR0_MSIPUB                     RCC_PUBCFGR0_MSIPUB_Msk              /*!< Public protection of MSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSIPUB_Pos                 (3U)
+#define RCC_PUBCFGR0_HSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR0_HSIPUB                     RCC_PUBCFGR0_HSIPUB_Msk              /*!< Public protection of HSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSEPUB_Pos                 (4U)
+#define RCC_PUBCFGR0_HSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR0_HSEPUB                     RCC_PUBCFGR0_HSEPUB_Msk              /*!< Public protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR1 register  *****************/
+#define RCC_SECCFGR1_PLL1SEC_Pos                (0U)
+#define RCC_SECCFGR1_PLL1SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos)   /*!< 0x00000001 */
+#define RCC_SECCFGR1_PLL1SEC                    RCC_SECCFGR1_PLL1SEC_Msk             /*!< Secure protection of PLL1 configuration bits */
+#define RCC_SECCFGR1_PLL2SEC_Pos                (1U)
+#define RCC_SECCFGR1_PLL2SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos)   /*!< 0x00000002 */
+#define RCC_SECCFGR1_PLL2SEC                    RCC_SECCFGR1_PLL2SEC_Msk             /*!< Secure protection of PLL2 configuration bits */
+#define RCC_SECCFGR1_PLL3SEC_Pos                (2U)
+#define RCC_SECCFGR1_PLL3SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR1_PLL3SEC                    RCC_SECCFGR1_PLL3SEC_Msk             /*!< Secure protection of PLL3 configuration bits */
+#define RCC_SECCFGR1_PLL4SEC_Pos                (3U)
+#define RCC_SECCFGR1_PLL4SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR1_PLL4SEC                    RCC_SECCFGR1_PLL4SEC_Msk             /*!< Secure protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR1 register  *****************/
+#define RCC_PRIVCFGR1_PLL1PRIV_Pos              (0U)
+#define RCC_PRIVCFGR1_PLL1PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGR1_PLL1PRIV                  RCC_PRIVCFGR1_PLL1PRIV_Msk           /*!< Privileged protection of PLL1 configuration bits */
+#define RCC_PRIVCFGR1_PLL2PRIV_Pos              (1U)
+#define RCC_PRIVCFGR1_PLL2PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR1_PLL2PRIV                  RCC_PRIVCFGR1_PLL2PRIV_Msk           /*!< Privileged protection of PLL2 configuration bits */
+#define RCC_PRIVCFGR1_PLL3PRIV_Pos              (2U)
+#define RCC_PRIVCFGR1_PLL3PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR1_PLL3PRIV                  RCC_PRIVCFGR1_PLL3PRIV_Msk           /*!< Privileged protection of PLL3 configuration bits */
+#define RCC_PRIVCFGR1_PLL4PRIV_Pos              (3U)
+#define RCC_PRIVCFGR1_PLL4PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR1_PLL4PRIV                  RCC_PRIVCFGR1_PLL4PRIV_Msk           /*!< Privileged protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR1 register  *****************/
+#define RCC_LOCKCFGR1_PLL1LOCK_Pos              (0U)
+#define RCC_LOCKCFGR1_PLL1LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */
+#define RCC_LOCKCFGR1_PLL1LOCK                  RCC_LOCKCFGR1_PLL1LOCK_Msk           /*!< Locked protection of PLL1 configuration bits */
+#define RCC_LOCKCFGR1_PLL2LOCK_Pos              (1U)
+#define RCC_LOCKCFGR1_PLL2LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR1_PLL2LOCK                  RCC_LOCKCFGR1_PLL2LOCK_Msk           /*!< Locked protection of PLL2 configuration bits */
+#define RCC_LOCKCFGR1_PLL3LOCK_Pos              (2U)
+#define RCC_LOCKCFGR1_PLL3LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR1_PLL3LOCK                  RCC_LOCKCFGR1_PLL3LOCK_Msk           /*!< Locked protection of PLL3 configuration bits */
+#define RCC_LOCKCFGR1_PLL4LOCK_Pos              (3U)
+#define RCC_LOCKCFGR1_PLL4LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR1_PLL4LOCK                  RCC_LOCKCFGR1_PLL4LOCK_Msk           /*!< Locked protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR1 register  *****************/
+#define RCC_PUBCFGR1_PLL1PUB_Pos                (0U)
+#define RCC_PUBCFGR1_PLL1PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGR1_PLL1PUB                    RCC_PUBCFGR1_PLL1PUB_Msk             /*!< Public protection of PLL1 configuration bits */
+#define RCC_PUBCFGR1_PLL2PUB_Pos                (1U)
+#define RCC_PUBCFGR1_PLL2PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGR1_PLL2PUB                    RCC_PUBCFGR1_PLL2PUB_Msk             /*!< Public protection of PLL2 configuration bits */
+#define RCC_PUBCFGR1_PLL3PUB_Pos                (2U)
+#define RCC_PUBCFGR1_PLL3PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR1_PLL3PUB                    RCC_PUBCFGR1_PLL3PUB_Msk             /*!< Public protection of PLL3 configuration bits */
+#define RCC_PUBCFGR1_PLL4PUB_Pos                (3U)
+#define RCC_PUBCFGR1_PLL4PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR1_PLL4PUB                    RCC_PUBCFGR1_PLL4PUB_Msk             /*!< Public protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR2 register  *****************/
+#define RCC_SECCFGR2_IC1SEC_Pos                 (0U)
+#define RCC_SECCFGR2_IC1SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC1SEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR2_IC1SEC                     RCC_SECCFGR2_IC1SEC_Msk              /*!< Secure protection of IC1 divider configuration bits */
+#define RCC_SECCFGR2_IC2SEC_Pos                 (1U)
+#define RCC_SECCFGR2_IC2SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC2SEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR2_IC2SEC                     RCC_SECCFGR2_IC2SEC_Msk              /*!< Secure protection of IC2 divider configuration bits */
+#define RCC_SECCFGR2_IC3SEC_Pos                 (2U)
+#define RCC_SECCFGR2_IC3SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC3SEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR2_IC3SEC                     RCC_SECCFGR2_IC3SEC_Msk              /*!< Secure protection of IC3 divider configuration bits */
+#define RCC_SECCFGR2_IC4SEC_Pos                 (3U)
+#define RCC_SECCFGR2_IC4SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC4SEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR2_IC4SEC                     RCC_SECCFGR2_IC4SEC_Msk              /*!< Secure protection of IC4 divider configuration bits */
+#define RCC_SECCFGR2_IC5SEC_Pos                 (4U)
+#define RCC_SECCFGR2_IC5SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC5SEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR2_IC5SEC                     RCC_SECCFGR2_IC5SEC_Msk              /*!< Secure protection of IC5 divider configuration bits */
+#define RCC_SECCFGR2_IC6SEC_Pos                 (5U)
+#define RCC_SECCFGR2_IC6SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC6SEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR2_IC6SEC                     RCC_SECCFGR2_IC6SEC_Msk              /*!< Secure protection of IC6 divider configuration bits */
+#define RCC_SECCFGR2_IC7SEC_Pos                 (6U)
+#define RCC_SECCFGR2_IC7SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC7SEC_Pos)    /*!< 0x00000040 */
+#define RCC_SECCFGR2_IC7SEC                     RCC_SECCFGR2_IC7SEC_Msk              /*!< Secure protection of IC7 divider configuration bits */
+#define RCC_SECCFGR2_IC8SEC_Pos                 (7U)
+#define RCC_SECCFGR2_IC8SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC8SEC_Pos)    /*!< 0x00000080 */
+#define RCC_SECCFGR2_IC8SEC                     RCC_SECCFGR2_IC8SEC_Msk              /*!< Secure protection of IC8 divider configuration bits */
+#define RCC_SECCFGR2_IC9SEC_Pos                 (8U)
+#define RCC_SECCFGR2_IC9SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC9SEC_Pos)    /*!< 0x00000100 */
+#define RCC_SECCFGR2_IC9SEC                     RCC_SECCFGR2_IC9SEC_Msk              /*!< Secure protection of IC9 divider configuration bits */
+#define RCC_SECCFGR2_IC10SEC_Pos                (9U)
+#define RCC_SECCFGR2_IC10SEC_Msk                (0x1UL << RCC_SECCFGR2_IC10SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR2_IC10SEC                    RCC_SECCFGR2_IC10SEC_Msk             /*!< Secure protection of IC10 divider configuration bits */
+#define RCC_SECCFGR2_IC11SEC_Pos                (10U)
+#define RCC_SECCFGR2_IC11SEC_Msk                (0x1UL << RCC_SECCFGR2_IC11SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR2_IC11SEC                    RCC_SECCFGR2_IC11SEC_Msk             /*!< Secure protection of IC11 divider configuration bits */
+#define RCC_SECCFGR2_IC12SEC_Pos                (11U)
+#define RCC_SECCFGR2_IC12SEC_Msk                (0x1UL << RCC_SECCFGR2_IC12SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR2_IC12SEC                    RCC_SECCFGR2_IC12SEC_Msk             /*!< Secure protection of IC12 divider configuration bits */
+#define RCC_SECCFGR2_IC13SEC_Pos                (12U)
+#define RCC_SECCFGR2_IC13SEC_Msk                (0x1UL << RCC_SECCFGR2_IC13SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR2_IC13SEC                    RCC_SECCFGR2_IC13SEC_Msk             /*!< Secure protection of IC13 divider configuration bits */
+#define RCC_SECCFGR2_IC14SEC_Pos                (13U)
+#define RCC_SECCFGR2_IC14SEC_Msk                (0x1UL << RCC_SECCFGR2_IC14SEC_Pos)   /*!< 0x00002000 */
+#define RCC_SECCFGR2_IC14SEC                    RCC_SECCFGR2_IC14SEC_Msk             /*!< Secure protection of IC14 divider configuration bits */
+#define RCC_SECCFGR2_IC15SEC_Pos                (14U)
+#define RCC_SECCFGR2_IC15SEC_Msk                (0x1UL << RCC_SECCFGR2_IC15SEC_Pos)   /*!< 0x00004000 */
+#define RCC_SECCFGR2_IC15SEC                    RCC_SECCFGR2_IC15SEC_Msk             /*!< Secure protection of IC15 divider configuration bits */
+#define RCC_SECCFGR2_IC16SEC_Pos                (15U)
+#define RCC_SECCFGR2_IC16SEC_Msk                (0x1UL << RCC_SECCFGR2_IC16SEC_Pos)   /*!< 0x00008000 */
+#define RCC_SECCFGR2_IC16SEC                    RCC_SECCFGR2_IC16SEC_Msk             /*!< Secure protection of IC16 divider configuration bits */
+#define RCC_SECCFGR2_IC17SEC_Pos                (16U)
+#define RCC_SECCFGR2_IC17SEC_Msk                (0x1UL << RCC_SECCFGR2_IC17SEC_Pos)   /*!< 0x00010000 */
+#define RCC_SECCFGR2_IC17SEC                    RCC_SECCFGR2_IC17SEC_Msk             /*!< Secure protection of IC17 divider configuration bits */
+#define RCC_SECCFGR2_IC18SEC_Pos                (17U)
+#define RCC_SECCFGR2_IC18SEC_Msk                (0x1UL << RCC_SECCFGR2_IC18SEC_Pos)   /*!< 0x00020000 */
+#define RCC_SECCFGR2_IC18SEC                    RCC_SECCFGR2_IC18SEC_Msk             /*!< Secure protection of IC18 divider configuration bits */
+#define RCC_SECCFGR2_IC19SEC_Pos                (18U)
+#define RCC_SECCFGR2_IC19SEC_Msk                (0x1UL << RCC_SECCFGR2_IC19SEC_Pos)   /*!< 0x00040000 */
+#define RCC_SECCFGR2_IC19SEC                    RCC_SECCFGR2_IC19SEC_Msk             /*!< Secure protection of IC19 divider configuration bits */
+#define RCC_SECCFGR2_IC20SEC_Pos                (19U)
+#define RCC_SECCFGR2_IC20SEC_Msk                (0x1UL << RCC_SECCFGR2_IC20SEC_Pos)   /*!< 0x00080000 */
+#define RCC_SECCFGR2_IC20SEC                    RCC_SECCFGR2_IC20SEC_Msk             /*!< Secure protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR2 register  *****************/
+#define RCC_PRIVCFGR2_IC1PRIV_Pos               (0U)
+#define RCC_PRIVCFGR2_IC1PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR2_IC1PRIV                   RCC_PRIVCFGR2_IC1PRIV_Msk            /*!< Privileged protection of IC1 divider configuration bits */
+#define RCC_PRIVCFGR2_IC2PRIV_Pos               (1U)
+#define RCC_PRIVCFGR2_IC2PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR2_IC2PRIV                   RCC_PRIVCFGR2_IC2PRIV_Msk            /*!< Privileged protection of IC2 divider configuration bits */
+#define RCC_PRIVCFGR2_IC3PRIV_Pos               (2U)
+#define RCC_PRIVCFGR2_IC3PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR2_IC3PRIV                   RCC_PRIVCFGR2_IC3PRIV_Msk            /*!< Privileged protection of IC3 divider configuration bits */
+#define RCC_PRIVCFGR2_IC4PRIV_Pos               (3U)
+#define RCC_PRIVCFGR2_IC4PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR2_IC4PRIV                   RCC_PRIVCFGR2_IC4PRIV_Msk            /*!< Privileged protection of IC4 divider configuration bits */
+#define RCC_PRIVCFGR2_IC5PRIV_Pos               (4U)
+#define RCC_PRIVCFGR2_IC5PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR2_IC5PRIV                   RCC_PRIVCFGR2_IC5PRIV_Msk            /*!< Privileged protection of IC5 divider configuration bits */
+#define RCC_PRIVCFGR2_IC6PRIV_Pos               (5U)
+#define RCC_PRIVCFGR2_IC6PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR2_IC6PRIV                   RCC_PRIVCFGR2_IC6PRIV_Msk            /*!< Privileged protection of IC6 divider configuration bits */
+#define RCC_PRIVCFGR2_IC7PRIV_Pos               (6U)
+#define RCC_PRIVCFGR2_IC7PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos)  /*!< 0x00000040 */
+#define RCC_PRIVCFGR2_IC7PRIV                   RCC_PRIVCFGR2_IC7PRIV_Msk            /*!< Privileged protection of IC7 divider configuration bits */
+#define RCC_PRIVCFGR2_IC8PRIV_Pos               (7U)
+#define RCC_PRIVCFGR2_IC8PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos)  /*!< 0x00000080 */
+#define RCC_PRIVCFGR2_IC8PRIV                   RCC_PRIVCFGR2_IC8PRIV_Msk            /*!< Privileged protection of IC8 divider configuration bits */
+#define RCC_PRIVCFGR2_IC9PRIV_Pos               (8U)
+#define RCC_PRIVCFGR2_IC9PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos)  /*!< 0x00000100 */
+#define RCC_PRIVCFGR2_IC9PRIV                   RCC_PRIVCFGR2_IC9PRIV_Msk            /*!< Privileged protection of IC9 divider configuration bits */
+#define RCC_PRIVCFGR2_IC10PRIV_Pos              (9U)
+#define RCC_PRIVCFGR2_IC10PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR2_IC10PRIV                  RCC_PRIVCFGR2_IC10PRIV_Msk           /*!< Privileged protection of IC10 divider configuration bits */
+#define RCC_PRIVCFGR2_IC11PRIV_Pos              (10U)
+#define RCC_PRIVCFGR2_IC11PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR2_IC11PRIV                  RCC_PRIVCFGR2_IC11PRIV_Msk           /*!< Privileged protection of IC11 divider configuration bits */
+#define RCC_PRIVCFGR2_IC12PRIV_Pos              (11U)
+#define RCC_PRIVCFGR2_IC12PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR2_IC12PRIV                  RCC_PRIVCFGR2_IC12PRIV_Msk           /*!< Privileged protection of IC12 divider configuration bits */
+#define RCC_PRIVCFGR2_IC13PRIV_Pos              (12U)
+#define RCC_PRIVCFGR2_IC13PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR2_IC13PRIV                  RCC_PRIVCFGR2_IC13PRIV_Msk           /*!< Privileged protection of IC13 divider configuration bits */
+#define RCC_PRIVCFGR2_IC14PRIV_Pos              (13U)
+#define RCC_PRIVCFGR2_IC14PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGR2_IC14PRIV                  RCC_PRIVCFGR2_IC14PRIV_Msk           /*!< Privileged protection of IC14 divider configuration bits */
+#define RCC_PRIVCFGR2_IC15PRIV_Pos              (14U)
+#define RCC_PRIVCFGR2_IC15PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGR2_IC15PRIV                  RCC_PRIVCFGR2_IC15PRIV_Msk           /*!< Privileged protection of IC15 divider configuration bits */
+#define RCC_PRIVCFGR2_IC16PRIV_Pos              (15U)
+#define RCC_PRIVCFGR2_IC16PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGR2_IC16PRIV                  RCC_PRIVCFGR2_IC16PRIV_Msk           /*!< Privileged protection of IC16 divider configuration bits */
+#define RCC_PRIVCFGR2_IC17PRIV_Pos              (16U)
+#define RCC_PRIVCFGR2_IC17PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGR2_IC17PRIV                  RCC_PRIVCFGR2_IC17PRIV_Msk           /*!< Privileges protection of IC17 divider configuration bits */
+#define RCC_PRIVCFGR2_IC18PRIV_Pos              (17U)
+#define RCC_PRIVCFGR2_IC18PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGR2_IC18PRIV                  RCC_PRIVCFGR2_IC18PRIV_Msk           /*!< Privilege protection of IC18 divider configuration bits */
+#define RCC_PRIVCFGR2_IC19PRIV_Pos              (18U)
+#define RCC_PRIVCFGR2_IC19PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGR2_IC19PRIV                  RCC_PRIVCFGR2_IC19PRIV_Msk           /*!< Privileged protection of IC19 divider configuration bits */
+#define RCC_PRIVCFGR2_IC20PRIV_Pos              (19U)
+#define RCC_PRIVCFGR2_IC20PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGR2_IC20PRIV                  RCC_PRIVCFGR2_IC20PRIV_Msk           /*!< Privileged protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR2 register  *****************/
+#define RCC_LOCKCFGR2_IC1LOCK_Pos               (0U)
+#define RCC_LOCKCFGR2_IC1LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR2_IC1LOCK                   RCC_LOCKCFGR2_IC1LOCK_Msk            /*!< Locked protection of IC1 divider configuration bits */
+#define RCC_LOCKCFGR2_IC2LOCK_Pos               (1U)
+#define RCC_LOCKCFGR2_IC2LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR2_IC2LOCK                   RCC_LOCKCFGR2_IC2LOCK_Msk            /*!< Locked protection of IC2 divider configuration bits */
+#define RCC_LOCKCFGR2_IC3LOCK_Pos               (2U)
+#define RCC_LOCKCFGR2_IC3LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR2_IC3LOCK                   RCC_LOCKCFGR2_IC3LOCK_Msk            /*!< Locked protection of IC3 divider configuration bits */
+#define RCC_LOCKCFGR2_IC4LOCK_Pos               (3U)
+#define RCC_LOCKCFGR2_IC4LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR2_IC4LOCK                   RCC_LOCKCFGR2_IC4LOCK_Msk            /*!< Locked protection of IC4 divider configuration bits */
+#define RCC_LOCKCFGR2_IC5LOCK_Pos               (4U)
+#define RCC_LOCKCFGR2_IC5LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR2_IC5LOCK                   RCC_LOCKCFGR2_IC5LOCK_Msk            /*!< Locked protection of IC5 divider configuration bits */
+#define RCC_LOCKCFGR2_IC6LOCK_Pos               (5U)
+#define RCC_LOCKCFGR2_IC6LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR2_IC6LOCK                   RCC_LOCKCFGR2_IC6LOCK_Msk            /*!< Locked protection of IC6 divider configuration bits */
+#define RCC_LOCKCFGR2_IC7LOCK_Pos               (6U)
+#define RCC_LOCKCFGR2_IC7LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos)  /*!< 0x00000040 */
+#define RCC_LOCKCFGR2_IC7LOCK                   RCC_LOCKCFGR2_IC7LOCK_Msk            /*!< Locked protection of IC7 divider configuration bits */
+#define RCC_LOCKCFGR2_IC8LOCK_Pos               (7U)
+#define RCC_LOCKCFGR2_IC8LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos)  /*!< 0x00000080 */
+#define RCC_LOCKCFGR2_IC8LOCK                   RCC_LOCKCFGR2_IC8LOCK_Msk            /*!< Locked protection of IC8 divider configuration bits */
+#define RCC_LOCKCFGR2_IC9LOCK_Pos               (8U)
+#define RCC_LOCKCFGR2_IC9LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos)  /*!< 0x00000100 */
+#define RCC_LOCKCFGR2_IC9LOCK                   RCC_LOCKCFGR2_IC9LOCK_Msk            /*!< Locked protection of IC9 divider configuration bits */
+#define RCC_LOCKCFGR2_IC10LOCK_Pos              (9U)
+#define RCC_LOCKCFGR2_IC10LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR2_IC10LOCK                  RCC_LOCKCFGR2_IC10LOCK_Msk           /*!< Locked protection of IC10 divider configuration bits */
+#define RCC_LOCKCFGR2_IC11LOCK_Pos              (10U)
+#define RCC_LOCKCFGR2_IC11LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR2_IC11LOCK                  RCC_LOCKCFGR2_IC11LOCK_Msk           /*!< Locked protection of IC11 divider configuration bits */
+#define RCC_LOCKCFGR2_IC12LOCK_Pos              (11U)
+#define RCC_LOCKCFGR2_IC12LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR2_IC12LOCK                  RCC_LOCKCFGR2_IC12LOCK_Msk           /*!< Locked protection of IC12 divider configuration bits */
+#define RCC_LOCKCFGR2_IC13LOCK_Pos              (12U)
+#define RCC_LOCKCFGR2_IC13LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR2_IC13LOCK                  RCC_LOCKCFGR2_IC13LOCK_Msk           /*!< Locked protection of IC13 divider configuration bits */
+#define RCC_LOCKCFGR2_IC14LOCK_Pos              (13U)
+#define RCC_LOCKCFGR2_IC14LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */
+#define RCC_LOCKCFGR2_IC14LOCK                  RCC_LOCKCFGR2_IC14LOCK_Msk           /*!< Locked protection of IC14 divider configuration bits */
+#define RCC_LOCKCFGR2_IC15LOCK_Pos              (14U)
+#define RCC_LOCKCFGR2_IC15LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */
+#define RCC_LOCKCFGR2_IC15LOCK                  RCC_LOCKCFGR2_IC15LOCK_Msk           /*!< Locked protection of IC15 divider configuration bits */
+#define RCC_LOCKCFGR2_IC16LOCK_Pos              (15U)
+#define RCC_LOCKCFGR2_IC16LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */
+#define RCC_LOCKCFGR2_IC16LOCK                  RCC_LOCKCFGR2_IC16LOCK_Msk           /*!< Locked protection of IC16 divider configuration bits */
+#define RCC_LOCKCFGR2_IC17LOCK_Pos              (16U)
+#define RCC_LOCKCFGR2_IC17LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */
+#define RCC_LOCKCFGR2_IC17LOCK                  RCC_LOCKCFGR2_IC17LOCK_Msk           /*!< Locked protection of IC17 divider configuration bits */
+#define RCC_LOCKCFGR2_IC18LOCK_Pos              (17U)
+#define RCC_LOCKCFGR2_IC18LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */
+#define RCC_LOCKCFGR2_IC18LOCK                  RCC_LOCKCFGR2_IC18LOCK_Msk           /*!< Locked protection of IC18 divider configuration bits */
+#define RCC_LOCKCFGR2_IC19LOCK_Pos              (18U)
+#define RCC_LOCKCFGR2_IC19LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */
+#define RCC_LOCKCFGR2_IC19LOCK                  RCC_LOCKCFGR2_IC19LOCK_Msk           /*!< Locked protection of IC19 divider configuration bits */
+#define RCC_LOCKCFGR2_IC20LOCK_Pos              (19U)
+#define RCC_LOCKCFGR2_IC20LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */
+#define RCC_LOCKCFGR2_IC20LOCK                  RCC_LOCKCFGR2_IC20LOCK_Msk           /*!< Locked protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR2 register  *****************/
+#define RCC_PUBCFGR2_IC1PUB_Pos                 (0U)
+#define RCC_PUBCFGR2_IC1PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR2_IC1PUB                     RCC_PUBCFGR2_IC1PUB_Msk              /*!< Public protection of IC1 divider configuration bits */
+#define RCC_PUBCFGR2_IC2PUB_Pos                 (1U)
+#define RCC_PUBCFGR2_IC2PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR2_IC2PUB                     RCC_PUBCFGR2_IC2PUB_Msk              /*!< Public protection of IC2 divider configuration bits */
+#define RCC_PUBCFGR2_IC3PUB_Pos                 (2U)
+#define RCC_PUBCFGR2_IC3PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR2_IC3PUB                     RCC_PUBCFGR2_IC3PUB_Msk              /*!< Public protection of IC3 divider configuration bits */
+#define RCC_PUBCFGR2_IC4PUB_Pos                 (3U)
+#define RCC_PUBCFGR2_IC4PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR2_IC4PUB                     RCC_PUBCFGR2_IC4PUB_Msk              /*!< Public protection of IC4 divider configuration bits */
+#define RCC_PUBCFGR2_IC5PUB_Pos                 (4U)
+#define RCC_PUBCFGR2_IC5PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR2_IC5PUB                     RCC_PUBCFGR2_IC5PUB_Msk              /*!< Public protection of IC5 divider configuration bits */
+#define RCC_PUBCFGR2_IC6PUB_Pos                 (5U)
+#define RCC_PUBCFGR2_IC6PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR2_IC6PUB                     RCC_PUBCFGR2_IC6PUB_Msk              /*!< Public protection of IC6 divider configuration bits */
+#define RCC_PUBCFGR2_IC7PUB_Pos                 (6U)
+#define RCC_PUBCFGR2_IC7PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos)    /*!< 0x00000040 */
+#define RCC_PUBCFGR2_IC7PUB                     RCC_PUBCFGR2_IC7PUB_Msk              /*!< Public protection of IC7 divider configuration bits */
+#define RCC_PUBCFGR2_IC8PUB_Pos                 (7U)
+#define RCC_PUBCFGR2_IC8PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos)    /*!< 0x00000080 */
+#define RCC_PUBCFGR2_IC8PUB                     RCC_PUBCFGR2_IC8PUB_Msk              /*!< Public protection of IC8 divider configuration bits */
+#define RCC_PUBCFGR2_IC9PUB_Pos                 (8U)
+#define RCC_PUBCFGR2_IC9PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos)    /*!< 0x00000100 */
+#define RCC_PUBCFGR2_IC9PUB                     RCC_PUBCFGR2_IC9PUB_Msk              /*!< Public protection of IC9 divider configuration bits */
+#define RCC_PUBCFGR2_IC10PUB_Pos                (9U)
+#define RCC_PUBCFGR2_IC10PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR2_IC10PUB                    RCC_PUBCFGR2_IC10PUB_Msk             /*!< Public protection of IC10 divider configuration bits */
+#define RCC_PUBCFGR2_IC11PUB_Pos                (10U)
+#define RCC_PUBCFGR2_IC11PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR2_IC11PUB                    RCC_PUBCFGR2_IC11PUB_Msk             /*!< Public protection of IC11 divider configuration bits */
+#define RCC_PUBCFGR2_IC12PUB_Pos                (11U)
+#define RCC_PUBCFGR2_IC12PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR2_IC12PUB                    RCC_PUBCFGR2_IC12PUB_Msk             /*!< Public protection of IC12 divider configuration bits */
+#define RCC_PUBCFGR2_IC13PUB_Pos                (12U)
+#define RCC_PUBCFGR2_IC13PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR2_IC13PUB                    RCC_PUBCFGR2_IC13PUB_Msk             /*!< Public protection of IC13 divider configuration bits */
+#define RCC_PUBCFGR2_IC14PUB_Pos                (13U)
+#define RCC_PUBCFGR2_IC14PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos)   /*!< 0x00002000 */
+#define RCC_PUBCFGR2_IC14PUB                    RCC_PUBCFGR2_IC14PUB_Msk             /*!< Public protection of IC14 divider configuration bits */
+#define RCC_PUBCFGR2_IC15PUB_Pos                (14U)
+#define RCC_PUBCFGR2_IC15PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos)   /*!< 0x00004000 */
+#define RCC_PUBCFGR2_IC15PUB                    RCC_PUBCFGR2_IC15PUB_Msk             /*!< Public protection of IC15 divider configuration bits */
+#define RCC_PUBCFGR2_IC16PUB_Pos                (15U)
+#define RCC_PUBCFGR2_IC16PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos)   /*!< 0x00008000 */
+#define RCC_PUBCFGR2_IC16PUB                    RCC_PUBCFGR2_IC16PUB_Msk             /*!< Public protection of IC16 divider configuration bits */
+#define RCC_PUBCFGR2_IC17PUB_Pos                (16U)
+#define RCC_PUBCFGR2_IC17PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos)   /*!< 0x00010000 */
+#define RCC_PUBCFGR2_IC17PUB                    RCC_PUBCFGR2_IC17PUB_Msk             /*!< Public protection of IC17 divider configuration bits */
+#define RCC_PUBCFGR2_IC18PUB_Pos                (17U)
+#define RCC_PUBCFGR2_IC18PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos)   /*!< 0x00020000 */
+#define RCC_PUBCFGR2_IC18PUB                    RCC_PUBCFGR2_IC18PUB_Msk             /*!< Public protection of IC18 divider configuration bits */
+#define RCC_PUBCFGR2_IC19PUB_Pos                (18U)
+#define RCC_PUBCFGR2_IC19PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos)   /*!< 0x00040000 */
+#define RCC_PUBCFGR2_IC19PUB                    RCC_PUBCFGR2_IC19PUB_Msk             /*!< Public protection of IC19 divider configuration bits */
+#define RCC_PUBCFGR2_IC20PUB_Pos                (19U)
+#define RCC_PUBCFGR2_IC20PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos)   /*!< 0x00080000 */
+#define RCC_PUBCFGR2_IC20PUB                    RCC_PUBCFGR2_IC20PUB_Msk             /*!< Public protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR3 register  *****************/
+#define RCC_SECCFGR3_MODSEC_Pos                 (0U)
+#define RCC_SECCFGR3_MODSEC_Msk                 (0x1UL << RCC_SECCFGR3_MODSEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR3_MODSEC                     RCC_SECCFGR3_MODSEC_Msk              /*!< Secure protection of MOD system configuration bits */
+#define RCC_SECCFGR3_SYSSEC_Pos                 (1U)
+#define RCC_SECCFGR3_SYSSEC_Msk                 (0x1UL << RCC_SECCFGR3_SYSSEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR3_SYSSEC                     RCC_SECCFGR3_SYSSEC_Msk              /*!< Secure protection of SYS system configuration bit */
+#define RCC_SECCFGR3_BUSSEC_Pos                 (2U)
+#define RCC_SECCFGR3_BUSSEC_Msk                 (0x1UL << RCC_SECCFGR3_BUSSEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR3_BUSSEC                     RCC_SECCFGR3_BUSSEC_Msk              /*!< Secure protection of BUS system configuration bits */
+#define RCC_SECCFGR3_PERSEC_Pos                 (3U)
+#define RCC_SECCFGR3_PERSEC_Msk                 (0x1UL << RCC_SECCFGR3_PERSEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR3_PERSEC                     RCC_SECCFGR3_PERSEC_Msk              /*!< Secure protection of PER system configuration bits */
+#define RCC_SECCFGR3_INTSEC_Pos                 (4U)
+#define RCC_SECCFGR3_INTSEC_Msk                 (0x1UL << RCC_SECCFGR3_INTSEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR3_INTSEC                     RCC_SECCFGR3_INTSEC_Msk              /*!< Secure protection of INT system configuration bits */
+#define RCC_SECCFGR3_RSTSEC_Pos                 (5U)
+#define RCC_SECCFGR3_RSTSEC_Msk                 (0x1UL << RCC_SECCFGR3_RSTSEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR3_RSTSEC                     RCC_SECCFGR3_RSTSEC_Msk              /*!< Secure protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR3 register  *****************/
+#define RCC_PRIVCFGR3_MODPRIV_Pos               (0U)
+#define RCC_PRIVCFGR3_MODPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR3_MODPRIV                   RCC_PRIVCFGR3_MODPRIV_Msk            /*!< Privileged protection of MOD system configuration bits */
+#define RCC_PRIVCFGR3_SYSPRIV_Pos               (1U)
+#define RCC_PRIVCFGR3_SYSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR3_SYSPRIV                   RCC_PRIVCFGR3_SYSPRIV_Msk            /*!< Privileged protection of SYS system configuration bits */
+#define RCC_PRIVCFGR3_BUSPRIV_Pos               (2U)
+#define RCC_PRIVCFGR3_BUSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR3_BUSPRIV                   RCC_PRIVCFGR3_BUSPRIV_Msk            /*!< Privileged protection of BUS system configuration bits */
+#define RCC_PRIVCFGR3_PERPRIV_Pos               (3U)
+#define RCC_PRIVCFGR3_PERPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR3_PERPRIV                   RCC_PRIVCFGR3_PERPRIV_Msk            /*!< Privileged protection of PER system configuration bits */
+#define RCC_PRIVCFGR3_INTPRIV_Pos               (4U)
+#define RCC_PRIVCFGR3_INTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR3_INTPRIV                   RCC_PRIVCFGR3_INTPRIV_Msk            /*!< Privileged protection of INT system configuration bits */
+#define RCC_PRIVCFGR3_RSTPRIV_Pos               (5U)
+#define RCC_PRIVCFGR3_RSTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR3_RSTPRIV                   RCC_PRIVCFGR3_RSTPRIV_Msk            /*!< Privileged protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR3 register  *****************/
+#define RCC_LOCKCFGR3_MODLOCK_Pos               (0U)
+#define RCC_LOCKCFGR3_MODLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR3_MODLOCK                   RCC_LOCKCFGR3_MODLOCK_Msk            /*!< Locked protection of MOD system configuration bits */
+#define RCC_LOCKCFGR3_SYSLOCK_Pos               (1U)
+#define RCC_LOCKCFGR3_SYSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR3_SYSLOCK                   RCC_LOCKCFGR3_SYSLOCK_Msk            /*!< Locked protection of SYS system configuration bits */
+#define RCC_LOCKCFGR3_BUSLOCK_Pos               (2U)
+#define RCC_LOCKCFGR3_BUSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR3_BUSLOCK                   RCC_LOCKCFGR3_BUSLOCK_Msk            /*!< Locked protection of BUS system configuration bits */
+#define RCC_LOCKCFGR3_PERLOCK_Pos               (3U)
+#define RCC_LOCKCFGR3_PERLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR3_PERLOCK                   RCC_LOCKCFGR3_PERLOCK_Msk            /*!< Locked protection of PER system configuration bits */
+#define RCC_LOCKCFGR3_INTLOCK_Pos               (4U)
+#define RCC_LOCKCFGR3_INTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR3_INTLOCK                   RCC_LOCKCFGR3_INTLOCK_Msk            /*!< Locked protection of INT system configuration bits */
+#define RCC_LOCKCFGR3_RSTLOCK_Pos               (5U)
+#define RCC_LOCKCFGR3_RSTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR3_RSTLOCK                   RCC_LOCKCFGR3_RSTLOCK_Msk            /*!< Locked protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR3 register  *****************/
+#define RCC_PUBCFGR3_MODPUB_Pos                 (0U)
+#define RCC_PUBCFGR3_MODPUB_Msk                 (0x1UL << RCC_PUBCFGR3_MODPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR3_MODPUB                     RCC_PUBCFGR3_MODPUB_Msk              /*!< Public protection of MOD system configuration bits */
+#define RCC_PUBCFGR3_SYSPUB_Pos                 (1U)
+#define RCC_PUBCFGR3_SYSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR3_SYSPUB                     RCC_PUBCFGR3_SYSPUB_Msk              /*!< Public protection of SYS system configuration bits */
+#define RCC_PUBCFGR3_BUSPUB_Pos                 (2U)
+#define RCC_PUBCFGR3_BUSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR3_BUSPUB                     RCC_PUBCFGR3_BUSPUB_Msk              /*!< Public protection of BUS system configuration bits */
+#define RCC_PUBCFGR3_PERPUB_Pos                 (3U)
+#define RCC_PUBCFGR3_PERPUB_Msk                 (0x1UL << RCC_PUBCFGR3_PERPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR3_PERPUB                     RCC_PUBCFGR3_PERPUB_Msk              /*!< Public protection of PER system configuration bits */
+#define RCC_PUBCFGR3_INTPUB_Pos                 (4U)
+#define RCC_PUBCFGR3_INTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_INTPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR3_INTPUB                     RCC_PUBCFGR3_INTPUB_Msk              /*!< Public protection of INT system configuration bits */
+#define RCC_PUBCFGR3_RSTPUB_Pos                 (5U)
+#define RCC_PUBCFGR3_RSTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR3_RSTPUB                     RCC_PUBCFGR3_RSTPUB_Msk              /*!< Public protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR4 register  *****************/
+#define RCC_SECCFGR4_ACLKNSEC_Pos               (0U)
+#define RCC_SECCFGR4_ACLKNSEC_Msk               (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos)  /*!< 0x00000001 */
+#define RCC_SECCFGR4_ACLKNSEC                   RCC_SECCFGR4_ACLKNSEC_Msk            /*!< Secure protection of ACLKN bus configuration bits */
+#define RCC_SECCFGR4_ACLKNCSEC_Pos              (1U)
+#define RCC_SECCFGR4_ACLKNCSEC_Msk              (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */
+#define RCC_SECCFGR4_ACLKNCSEC                  RCC_SECCFGR4_ACLKNCSEC_Msk           /*!< Secure protection of ACLKNC bus configuration bits */
+#define RCC_SECCFGR4_AHBMSEC_Pos                (2U)
+#define RCC_SECCFGR4_AHBMSEC_Msk                (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR4_AHBMSEC                    RCC_SECCFGR4_AHBMSEC_Msk             /*!< Secure protection of AHBM bus configuration bits */
+#define RCC_SECCFGR4_AHB1SEC_Pos                (3U)
+#define RCC_SECCFGR4_AHB1SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR4_AHB1SEC                    RCC_SECCFGR4_AHB1SEC_Msk             /*!< Secure protection of AHB1 bus configuration bits */
+#define RCC_SECCFGR4_AHB2SEC_Pos                (4U)
+#define RCC_SECCFGR4_AHB2SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos)   /*!< 0x00000010 */
+#define RCC_SECCFGR4_AHB2SEC                    RCC_SECCFGR4_AHB2SEC_Msk             /*!< Secure protection of AHB2 bus configuration bits */
+#define RCC_SECCFGR4_AHB3SEC_Pos                (5U)
+#define RCC_SECCFGR4_AHB3SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos)   /*!< 0x00000020 */
+#define RCC_SECCFGR4_AHB3SEC                    RCC_SECCFGR4_AHB3SEC_Msk             /*!< Secure protection of AHB3 bus configuration bits */
+#define RCC_SECCFGR4_AHB4SEC_Pos                (6U)
+#define RCC_SECCFGR4_AHB4SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos)   /*!< 0x00000040 */
+#define RCC_SECCFGR4_AHB4SEC                    RCC_SECCFGR4_AHB4SEC_Msk             /*!< Secure protection of AHB4 bus configuration bits */
+#define RCC_SECCFGR4_AHB5SEC_Pos                (7U)
+#define RCC_SECCFGR4_AHB5SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos)   /*!< 0x00000080 */
+#define RCC_SECCFGR4_AHB5SEC                    RCC_SECCFGR4_AHB5SEC_Msk             /*!< Secure protection of AHB5 bus configuration bits */
+#define RCC_SECCFGR4_APB1SEC_Pos                (8U)
+#define RCC_SECCFGR4_APB1SEC_Msk                (0x1UL << RCC_SECCFGR4_APB1SEC_Pos)   /*!< 0x00000100 */
+#define RCC_SECCFGR4_APB1SEC                    RCC_SECCFGR4_APB1SEC_Msk             /*!< Secure protection of APB1 bus configuration bits */
+#define RCC_SECCFGR4_APB2SEC_Pos                (9U)
+#define RCC_SECCFGR4_APB2SEC_Msk                (0x1UL << RCC_SECCFGR4_APB2SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR4_APB2SEC                    RCC_SECCFGR4_APB2SEC_Msk             /*!< Secure protection of APB2 bus configuration bits */
+#define RCC_SECCFGR4_APB3SEC_Pos                (10U)
+#define RCC_SECCFGR4_APB3SEC_Msk                (0x1UL << RCC_SECCFGR4_APB3SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR4_APB3SEC                    RCC_SECCFGR4_APB3SEC_Msk             /*!< Secure protection of APB3 bus configuration bits */
+#define RCC_SECCFGR4_APB4SEC_Pos                (11U)
+#define RCC_SECCFGR4_APB4SEC_Msk                (0x1UL << RCC_SECCFGR4_APB4SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR4_APB4SEC                    RCC_SECCFGR4_APB4SEC_Msk             /*!< Secure protection of APB4 bus configuration bits */
+#define RCC_SECCFGR4_APB5SEC_Pos                (12U)
+#define RCC_SECCFGR4_APB5SEC_Msk                (0x1UL << RCC_SECCFGR4_APB5SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR4_APB5SEC                    RCC_SECCFGR4_APB5SEC_Msk             /*!< Secure protection of APB5 bus configuration bits */
+#define RCC_SECCFGR4_NOCSEC_Pos                 (13U)
+#define RCC_SECCFGR4_NOCSEC_Msk                 (0x1UL << RCC_SECCFGR4_NOCSEC_Pos)    /*!< 0x00002000 */
+#define RCC_SECCFGR4_NOCSEC                     RCC_SECCFGR4_NOCSEC_Msk              /*!< Secure protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR4 register  *****************/
+#define RCC_PRIVCFGR4_ACLKNPRIV_Pos             (0U)
+#define RCC_PRIVCFGR4_ACLKNPRIV_Msk             (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGR4_ACLKNPRIV                 RCC_PRIVCFGR4_ACLKNPRIV_Msk          /*!< Privileged protection of ACLKN bus configuration bits */
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos            (1U)
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk            (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR4_ACLKNCPRIV                RCC_PRIVCFGR4_ACLKNCPRIV_Msk         /*!< Privileged protection of ACLKNC bus configuration bits */
+#define RCC_PRIVCFGR4_AHBMPRIV_Pos              (2U)
+#define RCC_PRIVCFGR4_AHBMPRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR4_AHBMPRIV                  RCC_PRIVCFGR4_AHBMPRIV_Msk           /*!< Privileged protection of AHBM bus configuration bits */
+#define RCC_PRIVCFGR4_AHB1PRIV_Pos              (3U)
+#define RCC_PRIVCFGR4_AHB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR4_AHB1PRIV                  RCC_PRIVCFGR4_AHB1PRIV_Msk           /*!< Privileged protection of AHB1 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB2PRIV_Pos              (4U)
+#define RCC_PRIVCFGR4_AHB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGR4_AHB2PRIV                  RCC_PRIVCFGR4_AHB2PRIV_Msk           /*!< Privileged protection of AHB2 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB3PRIV_Pos              (5U)
+#define RCC_PRIVCFGR4_AHB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGR4_AHB3PRIV                  RCC_PRIVCFGR4_AHB3PRIV_Msk           /*!< Privileged protection of AHB3 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB4PRIV_Pos              (6U)
+#define RCC_PRIVCFGR4_AHB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGR4_AHB4PRIV                  RCC_PRIVCFGR4_AHB4PRIV_Msk           /*!< Privileged protection of AHB4 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB5PRIV_Pos              (7U)
+#define RCC_PRIVCFGR4_AHB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGR4_AHB5PRIV                  RCC_PRIVCFGR4_AHB5PRIV_Msk           /*!< Privileged protection of AHB5 bus configuration bits */
+#define RCC_PRIVCFGR4_APB1PRIV_Pos              (8U)
+#define RCC_PRIVCFGR4_APB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGR4_APB1PRIV                  RCC_PRIVCFGR4_APB1PRIV_Msk           /*!< Privileged protection of APB1 bus configuration bits */
+#define RCC_PRIVCFGR4_APB2PRIV_Pos              (9U)
+#define RCC_PRIVCFGR4_APB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR4_APB2PRIV                  RCC_PRIVCFGR4_APB2PRIV_Msk           /*!< Privileged protection of APB2 bus configuration bits */
+#define RCC_PRIVCFGR4_APB3PRIV_Pos              (10U)
+#define RCC_PRIVCFGR4_APB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR4_APB3PRIV                  RCC_PRIVCFGR4_APB3PRIV_Msk           /*!< Privileged protection of APB3 bus configuration bits */
+#define RCC_PRIVCFGR4_APB4PRIV_Pos              (11U)
+#define RCC_PRIVCFGR4_APB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR4_APB4PRIV                  RCC_PRIVCFGR4_APB4PRIV_Msk           /*!< Privileged protection of APB4 bus configuration bits */
+#define RCC_PRIVCFGR4_APB5PRIV_Pos              (12U)
+#define RCC_PRIVCFGR4_APB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR4_APB5PRIV                  RCC_PRIVCFGR4_APB5PRIV_Msk           /*!< Privileged protection of APB5 bus configuration bits */
+#define RCC_PRIVCFGR4_NOCPRIV_Pos               (13U)
+#define RCC_PRIVCFGR4_NOCPRIV_Msk               (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos)  /*!< 0x00002000 */
+#define RCC_PRIVCFGR4_NOCPRIV                   RCC_PRIVCFGR4_NOCPRIV_Msk            /*!< Privileged protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR4 register  *****************/
+#define RCC_LOCKCFGR4_ACLKNLOCK_Pos             (0U)
+#define RCC_LOCKCFGR4_ACLKNLOCK_Msk             (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */
+#define RCC_LOCKCFGR4_ACLKNLOCK                 RCC_LOCKCFGR4_ACLKNLOCK_Msk          /*!< Locked protection of ACLKN bus configuration bits */
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos            (1U)
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk            (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR4_ACLKNCLOCK                RCC_LOCKCFGR4_ACLKNCLOCK_Msk         /*!< Locked protection of ACLKNC bus configuration bits */
+#define RCC_LOCKCFGR4_AHBMLOCK_Pos              (2U)
+#define RCC_LOCKCFGR4_AHBMLOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR4_AHBMLOCK                  RCC_LOCKCFGR4_AHBMLOCK_Msk           /*!< Locked protection of AHBM bus configuration bits */
+#define RCC_LOCKCFGR4_AHB1LOCK_Pos              (3U)
+#define RCC_LOCKCFGR4_AHB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR4_AHB1LOCK                  RCC_LOCKCFGR4_AHB1LOCK_Msk           /*!< Locked protection of AHB1 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB2LOCK_Pos              (4U)
+#define RCC_LOCKCFGR4_AHB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */
+#define RCC_LOCKCFGR4_AHB2LOCK                  RCC_LOCKCFGR4_AHB2LOCK_Msk           /*!< Locked protection of AHB2 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB3LOCK_Pos              (5U)
+#define RCC_LOCKCFGR4_AHB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */
+#define RCC_LOCKCFGR4_AHB3LOCK                  RCC_LOCKCFGR4_AHB3LOCK_Msk           /*!< Locked protection of AHB3 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB4LOCK_Pos              (6U)
+#define RCC_LOCKCFGR4_AHB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */
+#define RCC_LOCKCFGR4_AHB4LOCK                  RCC_LOCKCFGR4_AHB4LOCK_Msk           /*!< Locked protection of AHB4 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB5LOCK_Pos              (7U)
+#define RCC_LOCKCFGR4_AHB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */
+#define RCC_LOCKCFGR4_AHB5LOCK                  RCC_LOCKCFGR4_AHB5LOCK_Msk           /*!< Locked protection of AHB5 bus configuration bits */
+#define RCC_LOCKCFGR4_APB1LOCK_Pos              (8U)
+#define RCC_LOCKCFGR4_APB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */
+#define RCC_LOCKCFGR4_APB1LOCK                  RCC_LOCKCFGR4_APB1LOCK_Msk           /*!< Locked protection of APB1 bus configuration bits */
+#define RCC_LOCKCFGR4_APB2LOCK_Pos              (9U)
+#define RCC_LOCKCFGR4_APB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR4_APB2LOCK                  RCC_LOCKCFGR4_APB2LOCK_Msk           /*!< Locked protection of APB2 bus configuration bits */
+#define RCC_LOCKCFGR4_APB3LOCK_Pos              (10U)
+#define RCC_LOCKCFGR4_APB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR4_APB3LOCK                  RCC_LOCKCFGR4_APB3LOCK_Msk           /*!< Locked protection of APB3 bus configuration bits */
+#define RCC_LOCKCFGR4_APB4LOCK_Pos              (11U)
+#define RCC_LOCKCFGR4_APB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR4_APB4LOCK                  RCC_LOCKCFGR4_APB4LOCK_Msk           /*!< Locked protection of APB4 bus configuration bits */
+#define RCC_LOCKCFGR4_APB5LOCK_Pos              (12U)
+#define RCC_LOCKCFGR4_APB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR4_APB5LOCK                  RCC_LOCKCFGR4_APB5LOCK_Msk           /*!< Locked protection of APB5 bus configuration bits */
+#define RCC_LOCKCFGR4_NOCLOCK_Pos               (13U)
+#define RCC_LOCKCFGR4_NOCLOCK_Msk               (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos)  /*!< 0x00002000 */
+#define RCC_LOCKCFGR4_NOCLOCK                   RCC_LOCKCFGR4_NOCLOCK_Msk            /*!< Locked protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR4 register  *****************/
+#define RCC_PUBCFGR4_ACLKNPUB_Pos               (0U)
+#define RCC_PUBCFGR4_ACLKNPUB_Msk               (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGR4_ACLKNPUB                   RCC_PUBCFGR4_ACLKNPUB_Msk            /*!< Public protection of the ACLKN bus configuration bits */
+#define RCC_PUBCFGR4_ACLKNCPUB_Pos              (1U)
+#define RCC_PUBCFGR4_ACLKNCPUB_Msk              (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR4_ACLKNCPUB                  RCC_PUBCFGR4_ACLKNCPUB_Msk           /*!< Public protection of ACLKNC bus configuration bits */
+#define RCC_PUBCFGR4_AHBMPUB_Pos                (2U)
+#define RCC_PUBCFGR4_AHBMPUB_Msk                (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR4_AHBMPUB                    RCC_PUBCFGR4_AHBMPUB_Msk             /*!< Public protection of AHBM bus configuration bits */
+#define RCC_PUBCFGR4_AHB1PUB_Pos                (3U)
+#define RCC_PUBCFGR4_AHB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR4_AHB1PUB                    RCC_PUBCFGR4_AHB1PUB_Msk             /*!< Public protection of AHB1 bus configuration bits */
+#define RCC_PUBCFGR4_AHB2PUB_Pos                (4U)
+#define RCC_PUBCFGR4_AHB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGR4_AHB2PUB                    RCC_PUBCFGR4_AHB2PUB_Msk             /*!< Public protection of AHB2 bus configuration bits */
+#define RCC_PUBCFGR4_AHB3PUB_Pos                (5U)
+#define RCC_PUBCFGR4_AHB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGR4_AHB3PUB                    RCC_PUBCFGR4_AHB3PUB_Msk             /*!< Public protection of AHB3 bus configuration bits */
+#define RCC_PUBCFGR4_AHB4PUB_Pos                (6U)
+#define RCC_PUBCFGR4_AHB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos)   /*!< 0x00000040 */
+#define RCC_PUBCFGR4_AHB4PUB                    RCC_PUBCFGR4_AHB4PUB_Msk             /*!< Public protection of AHB4 bus configuration bits */
+#define RCC_PUBCFGR4_AHB5PUB_Pos                (7U)
+#define RCC_PUBCFGR4_AHB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGR4_AHB5PUB                    RCC_PUBCFGR4_AHB5PUB_Msk             /*!< Public protection of AHB5 bus configuration bits */
+#define RCC_PUBCFGR4_APB1PUB_Pos                (8U)
+#define RCC_PUBCFGR4_APB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGR4_APB1PUB                    RCC_PUBCFGR4_APB1PUB_Msk             /*!< Public protection of APB1 bus configuration bits */
+#define RCC_PUBCFGR4_APB2PUB_Pos                (9U)
+#define RCC_PUBCFGR4_APB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR4_APB2PUB                    RCC_PUBCFGR4_APB2PUB_Msk             /*!< Public protection of APB2 bus configuration bits */
+#define RCC_PUBCFGR4_APB3PUB_Pos                (10U)
+#define RCC_PUBCFGR4_APB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR4_APB3PUB                    RCC_PUBCFGR4_APB3PUB_Msk             /*!< Public protection of APB3 bus configuration bits */
+#define RCC_PUBCFGR4_APB4PUB_Pos                (11U)
+#define RCC_PUBCFGR4_APB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR4_APB4PUB                    RCC_PUBCFGR4_APB4PUB_Msk             /*!< Public protection of APB4 bus configuration bits */
+#define RCC_PUBCFGR4_APB5PUB_Pos                (12U)
+#define RCC_PUBCFGR4_APB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR4_APB5PUB                    RCC_PUBCFGR4_APB5PUB_Msk             /*!< Public protection of APB5 bus configuration bits */
+#define RCC_PUBCFGR4_NOCPUB_Pos                 (13U)
+#define RCC_PUBCFGR4_NOCPUB_Msk                 (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos)    /*!< 0x00002000 */
+#define RCC_PUBCFGR4_NOCPUB                     RCC_PUBCFGR4_NOCPUB_Msk              /*!< Public protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR5 register  *****************/
+#define RCC_PUBCFGR5_AXISRAM3PUB_Pos            (0U)
+#define RCC_PUBCFGR5_AXISRAM3PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGR5_AXISRAM3PUB                RCC_PUBCFGR5_AXISRAM3PUB_Msk         /*!< Public protection of AXISRAM3 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM4PUB_Pos            (1U)
+#define RCC_PUBCFGR5_AXISRAM4PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR5_AXISRAM4PUB                RCC_PUBCFGR5_AXISRAM4PUB_Msk         /*!< Public protection of AXISRAM4 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM5PUB_Pos            (2U)
+#define RCC_PUBCFGR5_AXISRAM5PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGR5_AXISRAM5PUB                RCC_PUBCFGR5_AXISRAM5PUB_Msk         /*!< Public protection of AXISRAM5 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM6PUB_Pos            (3U)
+#define RCC_PUBCFGR5_AXISRAM6PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGR5_AXISRAM6PUB                RCC_PUBCFGR5_AXISRAM6PUB_Msk         /*!< Public protection of AXISRAM6 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos            (4U)
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGR5_AHBSRAM1PUB                RCC_PUBCFGR5_AHBSRAM1PUB_Msk         /*!< Public protection of AHBSRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos            (5U)
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGR5_AHBSRAM2PUB                RCC_PUBCFGR5_AHBSRAM2PUB_Msk         /*!< Public protection of AHBSRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_BKPSRAMPUB_Pos             (6U)
+#define RCC_PUBCFGR5_BKPSRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */
+#define RCC_PUBCFGR5_BKPSRAMPUB                 RCC_PUBCFGR5_BKPSRAMPUB_Msk          /*!< Public protection of BKPSRAM bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM1PUB_Pos            (7U)
+#define RCC_PUBCFGR5_AXISRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGR5_AXISRAM1PUB                RCC_PUBCFGR5_AXISRAM1PUB_Msk         /*!< Public protection of AXISRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM2PUB_Pos            (8U)
+#define RCC_PUBCFGR5_AXISRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGR5_AXISRAM2PUB                RCC_PUBCFGR5_AXISRAM2PUB_Msk         /*!< Public protection of AXISRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_FLEXRAMPUB_Pos             (9U)
+#define RCC_PUBCFGR5_FLEXRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */
+#define RCC_PUBCFGR5_FLEXRAMPUB                 RCC_PUBCFGR5_FLEXRAMPUB_Msk          /*!< Public protection of FLEXRAM bus configuration bits */
+#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos         (10U)
+#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk         (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos)    /*!< 0x00000400 */
+#define RCC_PUBCFGR5_CACHEAXIRAMPUB             RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk      /*!< Public protection of CACHEAXIRAM bus configuration bits */
+#define RCC_PUBCFGR5_VENCRAMPUB_Pos             (11U)
+#define RCC_PUBCFGR5_VENCRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */
+#define RCC_PUBCFGR5_VENCRAMPUB                 RCC_PUBCFGR5_VENCRAMPUB_Msk          /*!< Public protection of VENCRAM bus configuration bits */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define RCC_CSR_LSIONS_Pos                      (0U)
+#define RCC_CSR_LSIONS_Msk                      (0x1UL << RCC_CSR_LSIONS_Pos)         /*!< 0x00000001 */
+#define RCC_CSR_LSIONS                          RCC_CSR_LSIONS_Msk                   /*!< LSI oscillator enable */
+#define RCC_CSR_LSEONS_Pos                      (1U)
+#define RCC_CSR_LSEONS_Msk                      (0x1UL << RCC_CSR_LSEONS_Pos)         /*!< 0x00000002 */
+#define RCC_CSR_LSEONS                          RCC_CSR_LSEONS_Msk                   /*!< LSE oscillator enable */
+#define RCC_CSR_MSIONS_Pos                      (2U)
+#define RCC_CSR_MSIONS_Msk                      (0x1UL << RCC_CSR_MSIONS_Pos)         /*!< 0x00000004 */
+#define RCC_CSR_MSIONS                          RCC_CSR_MSIONS_Msk                   /*!< MSI oscillator enable */
+#define RCC_CSR_HSIONS_Pos                      (3U)
+#define RCC_CSR_HSIONS_Msk                      (0x1UL << RCC_CSR_HSIONS_Pos)         /*!< 0x00000008 */
+#define RCC_CSR_HSIONS                          RCC_CSR_HSIONS_Msk                   /*!< HSI oscillator enable */
+#define RCC_CSR_HSEONS_Pos                      (4U)
+#define RCC_CSR_HSEONS_Msk                      (0x1UL << RCC_CSR_HSEONS_Pos)         /*!< 0x00000010 */
+#define RCC_CSR_HSEONS                          RCC_CSR_HSEONS_Msk                   /*!< HSE oscillator enable */
+#define RCC_CSR_PLL1ONS_Pos                     (8U)
+#define RCC_CSR_PLL1ONS_Msk                     (0x1UL << RCC_CSR_PLL1ONS_Pos)        /*!< 0x00000100 */
+#define RCC_CSR_PLL1ONS                         RCC_CSR_PLL1ONS_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CSR_PLL2ONS_Pos                     (9U)
+#define RCC_CSR_PLL2ONS_Msk                     (0x1UL << RCC_CSR_PLL2ONS_Pos)        /*!< 0x00000200 */
+#define RCC_CSR_PLL2ONS                         RCC_CSR_PLL2ONS_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CSR_PLL3ONS_Pos                     (10U)
+#define RCC_CSR_PLL3ONS_Msk                     (0x1UL << RCC_CSR_PLL3ONS_Pos)        /*!< 0x00000400 */
+#define RCC_CSR_PLL3ONS                         RCC_CSR_PLL3ONS_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CSR_PLL4ONS_Pos                     (11U)
+#define RCC_CSR_PLL4ONS_Msk                     (0x1UL << RCC_CSR_PLL4ONS_Pos)        /*!< 0x00000800 */
+#define RCC_CSR_PLL4ONS                         RCC_CSR_PLL4ONS_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCSR register  ******************/
+#define RCC_STOPCSR_MSISTOPENS_Pos              (0U)
+#define RCC_STOPCSR_MSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */
+#define RCC_STOPCSR_MSISTOPENS                  RCC_STOPCSR_MSISTOPENS_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCSR_HSISTOPENS_Pos              (1U)
+#define RCC_STOPCSR_HSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */
+#define RCC_STOPCSR_HSISTOPENS                  RCC_STOPCSR_HSISTOPENS_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTSR register  *****************/
+#define RCC_MISCRSTSR_DBGRSTS_Pos               (0U)
+#define RCC_MISCRSTSR_DBGRSTS_Msk               (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTSR_DBGRSTS                   RCC_MISCRSTSR_DBGRSTS_Msk            /*!< DBG reset */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos          (4U)
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS              RCC_MISCRSTSR_XSPIPHY1RSTS_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos          (5U)
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS              RCC_MISCRSTSR_XSPIPHY2RSTS_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos         (7U)
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS             RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos         (8U)
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS             RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTSR register  *****************/
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos           (0U)
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTSR_AXISRAM3RSTS               RCC_MEMRSTSR_AXISRAM3RSTS_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos           (1U)
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTSR_AXISRAM4RSTS               RCC_MEMRSTSR_AXISRAM4RSTS_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos           (2U)
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTSR_AXISRAM5RSTS               RCC_MEMRSTSR_AXISRAM5RSTS_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos           (3U)
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTSR_AXISRAM6RSTS               RCC_MEMRSTSR_AXISRAM6RSTS_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos           (4U)
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS               RCC_MEMRSTSR_AHBSRAM1RSTS_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos           (5U)
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS               RCC_MEMRSTSR_AHBSRAM2RSTS_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos           (7U)
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTSR_AXISRAM1RSTS               RCC_MEMRSTSR_AXISRAM1RSTS_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos           (8U)
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTSR_AXISRAM2RSTS               RCC_MEMRSTSR_AXISRAM2RSTS_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos            (9U)
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTSR_FLEXRAMRSTS                RCC_MEMRSTSR_FLEXRAMRSTS_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos        (10U)
+#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk        (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos)     /*!< 0x00000400 */
+#define RCC_MEMRSTSR_CACHEAXIRAMRSTS            RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk     /*!< CACHEAXIRAM reset */
+#define RCC_MEMRSTSR_VENCRAMRSTS_Pos            (11U)
+#define RCC_MEMRSTSR_VENCRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTSR_VENCRAMRSTS                RCC_MEMRSTSR_VENCRAMRSTS_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTSR_BOOTROMRSTS_Pos            (12U)
+#define RCC_MEMRSTSR_BOOTROMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTSR_BOOTROMRSTS                RCC_MEMRSTSR_BOOTROMRSTS_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTSR register  *****************/
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos            (4U)
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk            (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTSR_GPDMA1RSTS                RCC_AHB1RSTSR_GPDMA1RSTS_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTSR_ADC12RSTS_Pos             (5U)
+#define RCC_AHB1RSTSR_ADC12RSTS_Msk             (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTSR_ADC12RSTS                 RCC_AHB1RSTSR_ADC12RSTS_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTSR register  *****************/
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos            (12U)
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk            (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTSR_RAMCFGRSTS                RCC_AHB2RSTSR_RAMCFGRSTS_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTSR_MDF1RSTS_Pos              (16U)
+#define RCC_AHB2RSTSR_MDF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTSR_MDF1RSTS                  RCC_AHB2RSTSR_MDF1RSTS_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTSR_ADF1RSTS_Pos              (17U)
+#define RCC_AHB2RSTSR_ADF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTSR_ADF1RSTS                  RCC_AHB2RSTSR_ADF1RSTS_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTSR register  *****************/
+#define RCC_AHB3RSTSR_RNGRSTS_Pos               (0U)
+#define RCC_AHB3RSTSR_RNGRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTSR_RNGRSTS                   RCC_AHB3RSTSR_RNGRSTS_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTSR_HASHRSTS_Pos              (1U)
+#define RCC_AHB3RSTSR_HASHRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTSR_HASHRSTS                  RCC_AHB3RSTSR_HASHRSTS_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTSR_PKARSTS_Pos               (8U)
+#define RCC_AHB3RSTSR_PKARSTS_Msk               (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTSR_PKARSTS                   RCC_AHB3RSTSR_PKARSTS_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTSR_IACRSTS_Pos               (10U)
+#define RCC_AHB3RSTSR_IACRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTSR_IACRSTS                   RCC_AHB3RSTSR_IACRSTS_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTSR register  *****************/
+#define RCC_AHB4RSTSR_GPIOARSTS_Pos             (0U)
+#define RCC_AHB4RSTSR_GPIOARSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTSR_GPIOARSTS                 RCC_AHB4RSTSR_GPIOARSTS_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTSR_GPIOBRSTS_Pos             (1U)
+#define RCC_AHB4RSTSR_GPIOBRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTSR_GPIOBRSTS                 RCC_AHB4RSTSR_GPIOBRSTS_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTSR_GPIOCRSTS_Pos             (2U)
+#define RCC_AHB4RSTSR_GPIOCRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTSR_GPIOCRSTS                 RCC_AHB4RSTSR_GPIOCRSTS_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTSR_GPIODRSTS_Pos             (3U)
+#define RCC_AHB4RSTSR_GPIODRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTSR_GPIODRSTS                 RCC_AHB4RSTSR_GPIODRSTS_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTSR_GPIOERSTS_Pos             (4U)
+#define RCC_AHB4RSTSR_GPIOERSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTSR_GPIOERSTS                 RCC_AHB4RSTSR_GPIOERSTS_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTSR_GPIOFRSTS_Pos             (5U)
+#define RCC_AHB4RSTSR_GPIOFRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTSR_GPIOFRSTS                 RCC_AHB4RSTSR_GPIOFRSTS_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTSR_GPIOGRSTS_Pos             (6U)
+#define RCC_AHB4RSTSR_GPIOGRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTSR_GPIOGRSTS                 RCC_AHB4RSTSR_GPIOGRSTS_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTSR_GPIOHRSTS_Pos             (7U)
+#define RCC_AHB4RSTSR_GPIOHRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTSR_GPIOHRSTS                 RCC_AHB4RSTSR_GPIOHRSTS_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTSR_GPIONRSTS_Pos             (13U)
+#define RCC_AHB4RSTSR_GPIONRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTSR_GPIONRSTS                 RCC_AHB4RSTSR_GPIONRSTS_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTSR_GPIOORSTS_Pos             (14U)
+#define RCC_AHB4RSTSR_GPIOORSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTSR_GPIOORSTS                 RCC_AHB4RSTSR_GPIOORSTS_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTSR_GPIOPRSTS_Pos             (15U)
+#define RCC_AHB4RSTSR_GPIOPRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTSR_GPIOPRSTS                 RCC_AHB4RSTSR_GPIOPRSTS_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTSR_GPIOQRSTS_Pos             (16U)
+#define RCC_AHB4RSTSR_GPIOQRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTSR_GPIOQRSTS                 RCC_AHB4RSTSR_GPIOQRSTS_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTSR_PWRRSTS_Pos               (18U)
+#define RCC_AHB4RSTSR_PWRRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTSR_PWRRSTS                   RCC_AHB4RSTSR_PWRRSTS_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTSR_CRCRSTS_Pos               (19U)
+#define RCC_AHB4RSTSR_CRCRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTSR_CRCRSTS                   RCC_AHB4RSTSR_CRCRSTS_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTSR register  *****************/
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos            (0U)
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTSR_HPDMA1RSTS                RCC_AHB5RSTSR_HPDMA1RSTS_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTSR_DMA2DRSTS_Pos             (1U)
+#define RCC_AHB5RSTSR_DMA2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTSR_DMA2DRSTS                 RCC_AHB5RSTSR_DMA2DRSTS_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTSR_JPEGRSTS_Pos              (3U)
+#define RCC_AHB5RSTSR_JPEGRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTSR_JPEGRSTS                  RCC_AHB5RSTSR_JPEGRSTS_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTSR_FMCRSTS_Pos               (4U)
+#define RCC_AHB5RSTSR_FMCRSTS_Msk               (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTSR_FMCRSTS                   RCC_AHB5RSTSR_FMCRSTS_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTSR_XSPI1RSTS_Pos             (5U)
+#define RCC_AHB5RSTSR_XSPI1RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTSR_XSPI1RSTS                 RCC_AHB5RSTSR_XSPI1RSTS_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTSR_PSSIRSTS_Pos              (6U)
+#define RCC_AHB5RSTSR_PSSIRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTSR_PSSIRSTS                  RCC_AHB5RSTSR_PSSIRSTS_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos            (7U)
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTSR_SDMMC2RSTS                RCC_AHB5RSTSR_SDMMC2RSTS_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos            (8U)
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTSR_SDMMC1RSTS                RCC_AHB5RSTSR_SDMMC1RSTS_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTSR_XSPI2RSTS_Pos             (12U)
+#define RCC_AHB5RSTSR_XSPI2RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTSR_XSPI2RSTS                 RCC_AHB5RSTSR_XSPI2RSTS_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTSR_XSPIMRSTS_Pos             (13U)
+#define RCC_AHB5RSTSR_XSPIMRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTSR_XSPIMRSTS                 RCC_AHB5RSTSR_XSPIMRSTS_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTSR_XSPI3RSTS_Pos             (17U)
+#define RCC_AHB5RSTSR_XSPI3RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTSR_XSPI3RSTS                 RCC_AHB5RSTSR_XSPI3RSTS_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTSR_GFXMMURSTS_Pos            (19U)
+#define RCC_AHB5RSTSR_GFXMMURSTS_Msk            (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTSR_GFXMMURSTS                RCC_AHB5RSTSR_GFXMMURSTS_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTSR_GPU2DRSTS_Pos             (20U)
+#define RCC_AHB5RSTSR_GPU2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTSR_GPU2DRSTS                 RCC_AHB5RSTSR_GPU2DRSTS_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos        (23U)
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS            RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos        (24U)
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS            RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTSR_ETH1RSTS_Pos              (25U)
+#define RCC_AHB5RSTSR_ETH1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTSR_ETH1RSTS                  RCC_AHB5RSTSR_ETH1RSTS_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTSR_OTG1RSTS_Pos              (26U)
+#define RCC_AHB5RSTSR_OTG1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTSR_OTG1RSTS                  RCC_AHB5RSTSR_OTG1RSTS_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos           (27U)
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS               RCC_AHB5RSTSR_OTGPHY1RSTS_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos           (28U)
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS               RCC_AHB5RSTSR_OTGPHY2RSTS_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTSR_OTG2RSTS_Pos              (29U)
+#define RCC_AHB5RSTSR_OTG2RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTSR_OTG2RSTS                  RCC_AHB5RSTSR_OTG2RSTS_Msk           /*!< OTG2 reset */
+#define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos          (30U)
+#define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk          (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos)   /*!< 0x40000000 */
+#define RCC_AHB5RSTSR_CACHEAXIRSTS              RCC_AHB5RSTSR_CACHEAXIRSTS_Msk       /*!< CACHEAXI reset */
+#define RCC_AHB5RSTSR_NPURSTS_Pos               (31U)
+#define RCC_AHB5RSTSR_NPURSTS_Msk               (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos)  /*!< 0x80000000 */
+#define RCC_AHB5RSTSR_NPURSTS                   RCC_AHB5RSTSR_NPURSTS_Msk            /*!< NPU reset */
+
+/****************  Bit definition for RCC_APB1RSTSR1 register  ****************/
+#define RCC_APB1RSTSR1_TIM2RSTS_Pos             (0U)
+#define RCC_APB1RSTSR1_TIM2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTSR1_TIM2RSTS                 RCC_APB1RSTSR1_TIM2RSTS_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTSR1_TIM3RSTS_Pos             (1U)
+#define RCC_APB1RSTSR1_TIM3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTSR1_TIM3RSTS                 RCC_APB1RSTSR1_TIM3RSTS_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTSR1_TIM4RSTS_Pos             (2U)
+#define RCC_APB1RSTSR1_TIM4RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTSR1_TIM4RSTS                 RCC_APB1RSTSR1_TIM4RSTS_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTSR1_TIM5RSTS_Pos             (3U)
+#define RCC_APB1RSTSR1_TIM5RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTSR1_TIM5RSTS                 RCC_APB1RSTSR1_TIM5RSTS_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTSR1_TIM6RSTS_Pos             (4U)
+#define RCC_APB1RSTSR1_TIM6RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTSR1_TIM6RSTS                 RCC_APB1RSTSR1_TIM6RSTS_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTSR1_TIM7RSTS_Pos             (5U)
+#define RCC_APB1RSTSR1_TIM7RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTSR1_TIM7RSTS                 RCC_APB1RSTSR1_TIM7RSTS_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTSR1_TIM12RSTS_Pos            (6U)
+#define RCC_APB1RSTSR1_TIM12RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTSR1_TIM12RSTS                RCC_APB1RSTSR1_TIM12RSTS_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTSR1_TIM13RSTS_Pos            (7U)
+#define RCC_APB1RSTSR1_TIM13RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTSR1_TIM13RSTS                RCC_APB1RSTSR1_TIM13RSTS_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTSR1_TIM14RSTS_Pos            (8U)
+#define RCC_APB1RSTSR1_TIM14RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR1_TIM14RSTS                RCC_APB1RSTSR1_TIM14RSTS_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos           (9U)
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTSR1_LPTIM1RSTS               RCC_APB1RSTSR1_LPTIM1RSTS_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTSR1_WWDGRSTS_Pos             (11U)
+#define RCC_APB1RSTSR1_WWDGRSTS_Msk             (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTSR1_WWDGRSTS                 RCC_APB1RSTSR1_WWDGRSTS_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTSR1_TIM10RSTS_Pos            (12U)
+#define RCC_APB1RSTSR1_TIM10RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTSR1_TIM10RSTS                RCC_APB1RSTSR1_TIM10RSTS_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTSR1_TIM11RSTS_Pos            (13U)
+#define RCC_APB1RSTSR1_TIM11RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTSR1_TIM11RSTS                RCC_APB1RSTSR1_TIM11RSTS_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTSR1_SPI2RSTS_Pos             (14U)
+#define RCC_APB1RSTSR1_SPI2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTSR1_SPI2RSTS                 RCC_APB1RSTSR1_SPI2RSTS_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTSR1_SPI3RSTS_Pos             (15U)
+#define RCC_APB1RSTSR1_SPI3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTSR1_SPI3RSTS                 RCC_APB1RSTSR1_SPI3RSTS_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos         (16U)
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk         (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS             RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTSR1_USART2RSTS_Pos           (17U)
+#define RCC_APB1RSTSR1_USART2RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTSR1_USART2RSTS               RCC_APB1RSTSR1_USART2RSTS_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTSR1_USART3RSTS_Pos           (18U)
+#define RCC_APB1RSTSR1_USART3RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTSR1_USART3RSTS               RCC_APB1RSTSR1_USART3RSTS_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTSR1_UART4RSTS_Pos            (19U)
+#define RCC_APB1RSTSR1_UART4RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTSR1_UART4RSTS                RCC_APB1RSTSR1_UART4RSTS_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTSR1_UART5RSTS_Pos            (20U)
+#define RCC_APB1RSTSR1_UART5RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTSR1_UART5RSTS                RCC_APB1RSTSR1_UART5RSTS_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTSR1_I2C1RSTS_Pos             (21U)
+#define RCC_APB1RSTSR1_I2C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTSR1_I2C1RSTS                 RCC_APB1RSTSR1_I2C1RSTS_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTSR1_I2C2RSTS_Pos             (22U)
+#define RCC_APB1RSTSR1_I2C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTSR1_I2C2RSTS                 RCC_APB1RSTSR1_I2C2RSTS_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTSR1_I2C3RSTS_Pos             (23U)
+#define RCC_APB1RSTSR1_I2C3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTSR1_I2C3RSTS                 RCC_APB1RSTSR1_I2C3RSTS_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTSR1_I3C1RSTS_Pos             (24U)
+#define RCC_APB1RSTSR1_I3C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTSR1_I3C1RSTS                 RCC_APB1RSTSR1_I3C1RSTS_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTSR1_I3C2RSTS_Pos             (25U)
+#define RCC_APB1RSTSR1_I3C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTSR1_I3C2RSTS                 RCC_APB1RSTSR1_I3C2RSTS_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTSR1_UART7RSTS_Pos            (30U)
+#define RCC_APB1RSTSR1_UART7RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTSR1_UART7RSTS                RCC_APB1RSTSR1_UART7RSTS_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTSR1_UART8RSTS_Pos            (31U)
+#define RCC_APB1RSTSR1_UART8RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTSR1_UART8RSTS                RCC_APB1RSTSR1_UART8RSTS_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTSR2 register  ****************/
+#define RCC_APB1RSTSR2_MDIOSRSTS_Pos            (5U)
+#define RCC_APB1RSTSR2_MDIOSRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTSR2_MDIOSRSTS                RCC_APB1RSTSR2_MDIOSRSTS_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTSR2_FDCANRSTS_Pos            (8U)
+#define RCC_APB1RSTSR2_FDCANRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR2_FDCANRSTS                RCC_APB1RSTSR2_FDCANRSTS_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTSR2_UCPD1RSTS_Pos            (18U)
+#define RCC_APB1RSTSR2_UCPD1RSTS_Msk            (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTSR2_UCPD1RSTS                RCC_APB1RSTSR2_UCPD1RSTS_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTSR register  *****************/
+#define RCC_APB2RSTSR_TIM1RSTS_Pos              (0U)
+#define RCC_APB2RSTSR_TIM1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTSR_TIM1RSTS                  RCC_APB2RSTSR_TIM1RSTS_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTSR_TIM8RSTS_Pos              (1U)
+#define RCC_APB2RSTSR_TIM8RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTSR_TIM8RSTS                  RCC_APB2RSTSR_TIM8RSTS_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTSR_USART1RSTS_Pos            (4U)
+#define RCC_APB2RSTSR_USART1RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTSR_USART1RSTS                RCC_APB2RSTSR_USART1RSTS_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTSR_USART6RSTS_Pos            (5U)
+#define RCC_APB2RSTSR_USART6RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTSR_USART6RSTS                RCC_APB2RSTSR_USART6RSTS_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTSR_UART9RSTS_Pos             (6U)
+#define RCC_APB2RSTSR_UART9RSTS_Msk             (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTSR_UART9RSTS                 RCC_APB2RSTSR_UART9RSTS_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTSR_USART10RSTS_Pos           (7U)
+#define RCC_APB2RSTSR_USART10RSTS_Msk           (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTSR_USART10RSTS               RCC_APB2RSTSR_USART10RSTS_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTSR_SPI1RSTS_Pos              (12U)
+#define RCC_APB2RSTSR_SPI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTSR_SPI1RSTS                  RCC_APB2RSTSR_SPI1RSTS_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTSR_SPI4RSTS_Pos              (13U)
+#define RCC_APB2RSTSR_SPI4RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTSR_SPI4RSTS                  RCC_APB2RSTSR_SPI4RSTS_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTSR_TIM18RSTS_Pos             (15U)
+#define RCC_APB2RSTSR_TIM18RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTSR_TIM18RSTS                 RCC_APB2RSTSR_TIM18RSTS_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTSR_TIM15RSTS_Pos             (16U)
+#define RCC_APB2RSTSR_TIM15RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTSR_TIM15RSTS                 RCC_APB2RSTSR_TIM15RSTS_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTSR_TIM16RSTS_Pos             (17U)
+#define RCC_APB2RSTSR_TIM16RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTSR_TIM16RSTS                 RCC_APB2RSTSR_TIM16RSTS_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTSR_TIM17RSTS_Pos             (18U)
+#define RCC_APB2RSTSR_TIM17RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTSR_TIM17RSTS                 RCC_APB2RSTSR_TIM17RSTS_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTSR_TIM9RSTS_Pos              (19U)
+#define RCC_APB2RSTSR_TIM9RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTSR_TIM9RSTS                  RCC_APB2RSTSR_TIM9RSTS_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTSR_SPI5RSTS_Pos              (20U)
+#define RCC_APB2RSTSR_SPI5RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTSR_SPI5RSTS                  RCC_APB2RSTSR_SPI5RSTS_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTSR_SAI1RSTS_Pos              (21U)
+#define RCC_APB2RSTSR_SAI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTSR_SAI1RSTS                  RCC_APB2RSTSR_SAI1RSTS_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTSR_SAI2RSTS_Pos              (22U)
+#define RCC_APB2RSTSR_SAI2RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTSR_SAI2RSTS                  RCC_APB2RSTSR_SAI2RSTS_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTSR1 register  ****************/
+#define RCC_APB4RSTSR1_HDPRSTS_Pos              (2U)
+#define RCC_APB4RSTSR1_HDPRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR1_HDPRSTS                  RCC_APB4RSTSR1_HDPRSTS_Msk           /*!< HDP reset */
+#define RCC_APB4RSTSR1_LPUART1RSTS_Pos          (3U)
+#define RCC_APB4RSTSR1_LPUART1RSTS_Msk          (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTSR1_LPUART1RSTS              RCC_APB4RSTSR1_LPUART1RSTS_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTSR1_SPI6RSTS_Pos             (5U)
+#define RCC_APB4RSTSR1_SPI6RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTSR1_SPI6RSTS                 RCC_APB4RSTSR1_SPI6RSTS_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTSR1_I2C4RSTS_Pos             (7U)
+#define RCC_APB4RSTSR1_I2C4RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTSR1_I2C4RSTS                 RCC_APB4RSTSR1_I2C4RSTS_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos           (9U)
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTSR1_LPTIM2RSTS               RCC_APB4RSTSR1_LPTIM2RSTS_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos           (10U)
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTSR1_LPTIM3RSTS               RCC_APB4RSTSR1_LPTIM3RSTS_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos           (11U)
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTSR1_LPTIM4RSTS               RCC_APB4RSTSR1_LPTIM4RSTS_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos           (12U)
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTSR1_LPTIM5RSTS               RCC_APB4RSTSR1_LPTIM5RSTS_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos          (15U)
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk          (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTSR1_VREFBUFRSTS              RCC_APB4RSTSR1_VREFBUFRSTS_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTSR1_RTCRSTS_Pos              (16U)
+#define RCC_APB4RSTSR1_RTCRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTSR1_RTCRSTS                  RCC_APB4RSTSR1_RTCRSTS_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTSR2 register  ****************/
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos           (0U)
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk           (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTSR2_SYSCFGRSTS               RCC_APB4RSTSR2_SYSCFGRSTS_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTSR2_DTSRSTS_Pos              (2U)
+#define RCC_APB4RSTSR2_DTSRSTS_Msk              (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR2_DTSRSTS                  RCC_APB4RSTSR2_DTSRSTS_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTSR register  *****************/
+#define RCC_APB5RSTSR_LTDCRSTS_Pos              (1U)
+#define RCC_APB5RSTSR_LTDCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTSR_LTDCRSTS                  RCC_APB5RSTSR_LTDCRSTS_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTSR_DCMIPPRSTS_Pos            (2U)
+#define RCC_APB5RSTSR_DCMIPPRSTS_Msk            (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTSR_DCMIPPRSTS                RCC_APB5RSTSR_DCMIPPRSTS_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTSR_GFXTIMRSTS_Pos            (4U)
+#define RCC_APB5RSTSR_GFXTIMRSTS_Msk            (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTSR_GFXTIMRSTS                RCC_APB5RSTSR_GFXTIMRSTS_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTSR_VENCRSTS_Pos              (5U)
+#define RCC_APB5RSTSR_VENCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTSR_VENCRSTS                  RCC_APB5RSTSR_VENCRSTS_Msk           /*!< VENC reset */
+#define RCC_APB5RSTSR_CSIRSTS_Pos               (6U)
+#define RCC_APB5RSTSR_CSIRSTS_Msk               (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTSR_CSIRSTS                   RCC_APB5RSTSR_CSIRSTS_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENSR register  ******************/
+#define RCC_DIVENSR_IC1ENS_Pos                  (0U)
+#define RCC_DIVENSR_IC1ENS_Msk                  (0x1UL << RCC_DIVENSR_IC1ENS_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENSR_IC1ENS                      RCC_DIVENSR_IC1ENS_Msk               /*!< IC1 enable */
+#define RCC_DIVENSR_IC2ENS_Pos                  (1U)
+#define RCC_DIVENSR_IC2ENS_Msk                  (0x1UL << RCC_DIVENSR_IC2ENS_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENSR_IC2ENS                      RCC_DIVENSR_IC2ENS_Msk               /*!< IC2 enable */
+#define RCC_DIVENSR_IC3ENS_Pos                  (2U)
+#define RCC_DIVENSR_IC3ENS_Msk                  (0x1UL << RCC_DIVENSR_IC3ENS_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENSR_IC3ENS                      RCC_DIVENSR_IC3ENS_Msk               /*!< IC3 enable */
+#define RCC_DIVENSR_IC4ENS_Pos                  (3U)
+#define RCC_DIVENSR_IC4ENS_Msk                  (0x1UL << RCC_DIVENSR_IC4ENS_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENSR_IC4ENS                      RCC_DIVENSR_IC4ENS_Msk               /*!< IC4 enable */
+#define RCC_DIVENSR_IC5ENS_Pos                  (4U)
+#define RCC_DIVENSR_IC5ENS_Msk                  (0x1UL << RCC_DIVENSR_IC5ENS_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENSR_IC5ENS                      RCC_DIVENSR_IC5ENS_Msk               /*!< IC5 enable */
+#define RCC_DIVENSR_IC6ENS_Pos                  (5U)
+#define RCC_DIVENSR_IC6ENS_Msk                  (0x1UL << RCC_DIVENSR_IC6ENS_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENSR_IC6ENS                      RCC_DIVENSR_IC6ENS_Msk               /*!< IC6 enable */
+#define RCC_DIVENSR_IC7ENS_Pos                  (6U)
+#define RCC_DIVENSR_IC7ENS_Msk                  (0x1UL << RCC_DIVENSR_IC7ENS_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENSR_IC7ENS                      RCC_DIVENSR_IC7ENS_Msk               /*!< IC7 enable */
+#define RCC_DIVENSR_IC8ENS_Pos                  (7U)
+#define RCC_DIVENSR_IC8ENS_Msk                  (0x1UL << RCC_DIVENSR_IC8ENS_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENSR_IC8ENS                      RCC_DIVENSR_IC8ENS_Msk               /*!< IC8 enable */
+#define RCC_DIVENSR_IC9ENS_Pos                  (8U)
+#define RCC_DIVENSR_IC9ENS_Msk                  (0x1UL << RCC_DIVENSR_IC9ENS_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENSR_IC9ENS                      RCC_DIVENSR_IC9ENS_Msk               /*!< IC9 enable */
+#define RCC_DIVENSR_IC10ENS_Pos                 (9U)
+#define RCC_DIVENSR_IC10ENS_Msk                 (0x1UL << RCC_DIVENSR_IC10ENS_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENSR_IC10ENS                     RCC_DIVENSR_IC10ENS_Msk              /*!< IC10 enable */
+#define RCC_DIVENSR_IC11ENS_Pos                 (10U)
+#define RCC_DIVENSR_IC11ENS_Msk                 (0x1UL << RCC_DIVENSR_IC11ENS_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENSR_IC11ENS                     RCC_DIVENSR_IC11ENS_Msk              /*!< IC11 enable */
+#define RCC_DIVENSR_IC12ENS_Pos                 (11U)
+#define RCC_DIVENSR_IC12ENS_Msk                 (0x1UL << RCC_DIVENSR_IC12ENS_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENSR_IC12ENS                     RCC_DIVENSR_IC12ENS_Msk              /*!< IC12 enable */
+#define RCC_DIVENSR_IC13ENS_Pos                 (12U)
+#define RCC_DIVENSR_IC13ENS_Msk                 (0x1UL << RCC_DIVENSR_IC13ENS_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENSR_IC13ENS                     RCC_DIVENSR_IC13ENS_Msk              /*!< IC13 enable */
+#define RCC_DIVENSR_IC14ENS_Pos                 (13U)
+#define RCC_DIVENSR_IC14ENS_Msk                 (0x1UL << RCC_DIVENSR_IC14ENS_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENSR_IC14ENS                     RCC_DIVENSR_IC14ENS_Msk              /*!< IC14 enable */
+#define RCC_DIVENSR_IC15ENS_Pos                 (14U)
+#define RCC_DIVENSR_IC15ENS_Msk                 (0x1UL << RCC_DIVENSR_IC15ENS_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENSR_IC15ENS                     RCC_DIVENSR_IC15ENS_Msk              /*!< IC15 enable */
+#define RCC_DIVENSR_IC16ENS_Pos                 (15U)
+#define RCC_DIVENSR_IC16ENS_Msk                 (0x1UL << RCC_DIVENSR_IC16ENS_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENSR_IC16ENS                     RCC_DIVENSR_IC16ENS_Msk              /*!< IC16 enable */
+#define RCC_DIVENSR_IC17ENS_Pos                 (16U)
+#define RCC_DIVENSR_IC17ENS_Msk                 (0x1UL << RCC_DIVENSR_IC17ENS_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENSR_IC17ENS                     RCC_DIVENSR_IC17ENS_Msk              /*!< IC17 enable */
+#define RCC_DIVENSR_IC18ENS_Pos                 (17U)
+#define RCC_DIVENSR_IC18ENS_Msk                 (0x1UL << RCC_DIVENSR_IC18ENS_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENSR_IC18ENS                     RCC_DIVENSR_IC18ENS_Msk              /*!< IC18 enable */
+#define RCC_DIVENSR_IC19ENS_Pos                 (18U)
+#define RCC_DIVENSR_IC19ENS_Msk                 (0x1UL << RCC_DIVENSR_IC19ENS_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENSR_IC19ENS                     RCC_DIVENSR_IC19ENS_Msk              /*!< IC19 enable */
+#define RCC_DIVENSR_IC20ENS_Pos                 (19U)
+#define RCC_DIVENSR_IC20ENS_Msk                 (0x1UL << RCC_DIVENSR_IC20ENS_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENSR_IC20ENS                     RCC_DIVENSR_IC20ENS_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENSR register  ******************/
+#define RCC_BUSENSR_ACLKNENS_Pos                (0U)
+#define RCC_BUSENSR_ACLKNENS_Msk                (0x1UL << RCC_BUSENSR_ACLKNENS_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENSR_ACLKNENS                    RCC_BUSENSR_ACLKNENS_Msk             /*!< ACLKN enable */
+#define RCC_BUSENSR_ACLKNCENS_Pos               (1U)
+#define RCC_BUSENSR_ACLKNCENS_Msk               (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENSR_ACLKNCENS                   RCC_BUSENSR_ACLKNCENS_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENSR_AHBMENS_Pos                 (2U)
+#define RCC_BUSENSR_AHBMENS_Msk                 (0x1UL << RCC_BUSENSR_AHBMENS_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENSR_AHBMENS                     RCC_BUSENSR_AHBMENS_Msk              /*!< AHBM enable */
+#define RCC_BUSENSR_AHB1ENS_Pos                 (3U)
+#define RCC_BUSENSR_AHB1ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB1ENS_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENSR_AHB1ENS                     RCC_BUSENSR_AHB1ENS_Msk              /*!< AHB1 enable */
+#define RCC_BUSENSR_AHB2ENS_Pos                 (4U)
+#define RCC_BUSENSR_AHB2ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB2ENS_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENSR_AHB2ENS                     RCC_BUSENSR_AHB2ENS_Msk              /*!< AHB2 enable */
+#define RCC_BUSENSR_AHB3ENS_Pos                 (5U)
+#define RCC_BUSENSR_AHB3ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB3ENS_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENSR_AHB3ENS                     RCC_BUSENSR_AHB3ENS_Msk              /*!< AHB3 enable */
+#define RCC_BUSENSR_AHB4ENS_Pos                 (6U)
+#define RCC_BUSENSR_AHB4ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB4ENS_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENSR_AHB4ENS                     RCC_BUSENSR_AHB4ENS_Msk              /*!< AHB4 enable */
+#define RCC_BUSENSR_AHB5ENS_Pos                 (7U)
+#define RCC_BUSENSR_AHB5ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB5ENS_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENSR_AHB5ENS                     RCC_BUSENSR_AHB5ENS_Msk              /*!< AHB5 enable */
+#define RCC_BUSENSR_APB1ENS_Pos                 (8U)
+#define RCC_BUSENSR_APB1ENS_Msk                 (0x1UL << RCC_BUSENSR_APB1ENS_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENSR_APB1ENS                     RCC_BUSENSR_APB1ENS_Msk              /*!< APB1 enable */
+#define RCC_BUSENSR_APB2ENS_Pos                 (9U)
+#define RCC_BUSENSR_APB2ENS_Msk                 (0x1UL << RCC_BUSENSR_APB2ENS_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENSR_APB2ENS                     RCC_BUSENSR_APB2ENS_Msk              /*!< APB2 enable */
+#define RCC_BUSENSR_APB3ENS_Pos                 (10U)
+#define RCC_BUSENSR_APB3ENS_Msk                 (0x1UL << RCC_BUSENSR_APB3ENS_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENSR_APB3ENS                     RCC_BUSENSR_APB3ENS_Msk              /*!< APB3 enable */
+#define RCC_BUSENSR_APB4ENS_Pos                 (11U)
+#define RCC_BUSENSR_APB4ENS_Msk                 (0x1UL << RCC_BUSENSR_APB4ENS_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENSR_APB4ENS                     RCC_BUSENSR_APB4ENS_Msk              /*!< APB4 enable */
+#define RCC_BUSENSR_APB5ENS_Pos                 (12U)
+#define RCC_BUSENSR_APB5ENS_Msk                 (0x1UL << RCC_BUSENSR_APB5ENS_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENSR_APB5ENS                     RCC_BUSENSR_APB5ENS_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENSR register  *****************/
+#define RCC_MISCENSR_DBGENS_Pos                 (0U)
+#define RCC_MISCENSR_DBGENS_Msk                 (0x1UL << RCC_MISCENSR_DBGENS_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENSR_DBGENS                     RCC_MISCENSR_DBGENS_Msk              /*!< DBG enable */
+#define RCC_MISCENSR_MCO1ENS_Pos                (1U)
+#define RCC_MISCENSR_MCO1ENS_Msk                (0x1UL << RCC_MISCENSR_MCO1ENS_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENSR_MCO1ENS                    RCC_MISCENSR_MCO1ENS_Msk             /*!< MCO1 enable */
+#define RCC_MISCENSR_MCO2ENS_Pos                (2U)
+#define RCC_MISCENSR_MCO2ENS_Msk                (0x1UL << RCC_MISCENSR_MCO2ENS_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENSR_MCO2ENS                    RCC_MISCENSR_MCO2ENS_Msk             /*!< MCO2 enable */
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos         (3U)
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk         (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENSR_XSPIPHYCOMPENS             RCC_MISCENSR_XSPIPHYCOMPENS_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENSR_PERENS_Pos                 (6U)
+#define RCC_MISCENSR_PERENS_Msk                 (0x1UL << RCC_MISCENSR_PERENS_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENSR_PERENS                     RCC_MISCENSR_PERENS_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENSR register  ******************/
+#define RCC_MEMENSR_AXISRAM3ENS_Pos             (0U)
+#define RCC_MEMENSR_AXISRAM3ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */
+#define RCC_MEMENSR_AXISRAM3ENS                 RCC_MEMENSR_AXISRAM3ENS_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENSR_AXISRAM4ENS_Pos             (1U)
+#define RCC_MEMENSR_AXISRAM4ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */
+#define RCC_MEMENSR_AXISRAM4ENS                 RCC_MEMENSR_AXISRAM4ENS_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENSR_AXISRAM5ENS_Pos             (2U)
+#define RCC_MEMENSR_AXISRAM5ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */
+#define RCC_MEMENSR_AXISRAM5ENS                 RCC_MEMENSR_AXISRAM5ENS_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENSR_AXISRAM6ENS_Pos             (3U)
+#define RCC_MEMENSR_AXISRAM6ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */
+#define RCC_MEMENSR_AXISRAM6ENS                 RCC_MEMENSR_AXISRAM6ENS_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENSR_AHBSRAM1ENS_Pos             (4U)
+#define RCC_MEMENSR_AHBSRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */
+#define RCC_MEMENSR_AHBSRAM1ENS                 RCC_MEMENSR_AHBSRAM1ENS_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENSR_AHBSRAM2ENS_Pos             (5U)
+#define RCC_MEMENSR_AHBSRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */
+#define RCC_MEMENSR_AHBSRAM2ENS                 RCC_MEMENSR_AHBSRAM2ENS_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENSR_BKPSRAMENS_Pos              (6U)
+#define RCC_MEMENSR_BKPSRAMENS_Msk              (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */
+#define RCC_MEMENSR_BKPSRAMENS                  RCC_MEMENSR_BKPSRAMENS_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENSR_AXISRAM1ENS_Pos             (7U)
+#define RCC_MEMENSR_AXISRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */
+#define RCC_MEMENSR_AXISRAM1ENS                 RCC_MEMENSR_AXISRAM1ENS_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENSR_AXISRAM2ENS_Pos             (8U)
+#define RCC_MEMENSR_AXISRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */
+#define RCC_MEMENSR_AXISRAM2ENS                 RCC_MEMENSR_AXISRAM2ENS_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENSR_FLEXRAMENS_Pos              (9U)
+#define RCC_MEMENSR_FLEXRAMENS_Msk              (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */
+#define RCC_MEMENSR_FLEXRAMENS                  RCC_MEMENSR_FLEXRAMENS_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENSR_CACHEAXIRAMENS_Pos          (10U)
+#define RCC_MEMENSR_CACHEAXIRAMENS_Msk          (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos)   /*!< 0x00000400 */
+#define RCC_MEMENSR_CACHEAXIRAMENS              RCC_MEMENSR_CACHEAXIRAMENS_Msk       /*!< CACHEAXIRAM enable */
+#define RCC_MEMENSR_VENCRAMENS_Pos              (11U)
+#define RCC_MEMENSR_VENCRAMENS_Msk              (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */
+#define RCC_MEMENSR_VENCRAMENS                  RCC_MEMENSR_VENCRAMENS_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENSR_BOOTROMENS_Pos              (12U)
+#define RCC_MEMENSR_BOOTROMENS_Msk              (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */
+#define RCC_MEMENSR_BOOTROMENS                  RCC_MEMENSR_BOOTROMENS_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENSR register  *****************/
+#define RCC_AHB1ENSR_GPDMA1ENS_Pos              (4U)
+#define RCC_AHB1ENSR_GPDMA1ENS_Msk              (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENSR_GPDMA1ENS                  RCC_AHB1ENSR_GPDMA1ENS_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENSR_ADC12ENS_Pos               (5U)
+#define RCC_AHB1ENSR_ADC12ENS_Msk               (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENSR_ADC12ENS                   RCC_AHB1ENSR_ADC12ENS_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENSR register  *****************/
+#define RCC_AHB2ENSR_RAMCFGENS_Pos              (12U)
+#define RCC_AHB2ENSR_RAMCFGENS_Msk              (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENSR_RAMCFGENS                  RCC_AHB2ENSR_RAMCFGENS_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENSR_MDF1ENS_Pos                (16U)
+#define RCC_AHB2ENSR_MDF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENSR_MDF1ENS                    RCC_AHB2ENSR_MDF1ENS_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENSR_ADF1ENS_Pos                (17U)
+#define RCC_AHB2ENSR_ADF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENSR_ADF1ENS                    RCC_AHB2ENSR_ADF1ENS_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENSR register  *****************/
+#define RCC_AHB3ENSR_RNGENS_Pos                 (0U)
+#define RCC_AHB3ENSR_RNGENS_Msk                 (0x1UL << RCC_AHB3ENSR_RNGENS_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENSR_RNGENS                     RCC_AHB3ENSR_RNGENS_Msk              /*!< RNG enable */
+#define RCC_AHB3ENSR_HASHENS_Pos                (1U)
+#define RCC_AHB3ENSR_HASHENS_Msk                (0x1UL << RCC_AHB3ENSR_HASHENS_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENSR_HASHENS                    RCC_AHB3ENSR_HASHENS_Msk             /*!< HASH enable */
+#define RCC_AHB3ENSR_PKAENS_Pos                 (8U)
+#define RCC_AHB3ENSR_PKAENS_Msk                 (0x1UL << RCC_AHB3ENSR_PKAENS_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENSR_PKAENS                     RCC_AHB3ENSR_PKAENS_Msk              /*!< PKA enable */
+#define RCC_AHB3ENSR_RIFSCENS_Pos               (9U)
+#define RCC_AHB3ENSR_RIFSCENS_Msk               (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENSR_RIFSCENS                   RCC_AHB3ENSR_RIFSCENS_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENSR_IACENS_Pos                 (10U)
+#define RCC_AHB3ENSR_IACENS_Msk                 (0x1UL << RCC_AHB3ENSR_IACENS_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENSR_IACENS                     RCC_AHB3ENSR_IACENS_Msk              /*!< IAC enable */
+#define RCC_AHB3ENSR_RISAFENS_Pos               (14U)
+#define RCC_AHB3ENSR_RISAFENS_Msk               (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENSR_RISAFENS                   RCC_AHB3ENSR_RISAFENS_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENSR register  *****************/
+#define RCC_AHB4ENSR_GPIOAENS_Pos               (0U)
+#define RCC_AHB4ENSR_GPIOAENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENSR_GPIOAENS                   RCC_AHB4ENSR_GPIOAENS_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENSR_GPIOBENS_Pos               (1U)
+#define RCC_AHB4ENSR_GPIOBENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENSR_GPIOBENS                   RCC_AHB4ENSR_GPIOBENS_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENSR_GPIOCENS_Pos               (2U)
+#define RCC_AHB4ENSR_GPIOCENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENSR_GPIOCENS                   RCC_AHB4ENSR_GPIOCENS_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENSR_GPIODENS_Pos               (3U)
+#define RCC_AHB4ENSR_GPIODENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENSR_GPIODENS                   RCC_AHB4ENSR_GPIODENS_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENSR_GPIOEENS_Pos               (4U)
+#define RCC_AHB4ENSR_GPIOEENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENSR_GPIOEENS                   RCC_AHB4ENSR_GPIOEENS_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENSR_GPIOFENS_Pos               (5U)
+#define RCC_AHB4ENSR_GPIOFENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENSR_GPIOFENS                   RCC_AHB4ENSR_GPIOFENS_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENSR_GPIOGENS_Pos               (6U)
+#define RCC_AHB4ENSR_GPIOGENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENSR_GPIOGENS                   RCC_AHB4ENSR_GPIOGENS_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENSR_GPIOHENS_Pos               (7U)
+#define RCC_AHB4ENSR_GPIOHENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENSR_GPIOHENS                   RCC_AHB4ENSR_GPIOHENS_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENSR_GPIONENS_Pos               (13U)
+#define RCC_AHB4ENSR_GPIONENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENSR_GPIONENS                   RCC_AHB4ENSR_GPIONENS_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENSR_GPIOOENS_Pos               (14U)
+#define RCC_AHB4ENSR_GPIOOENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENSR_GPIOOENS                   RCC_AHB4ENSR_GPIOOENS_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENSR_GPIOPENS_Pos               (15U)
+#define RCC_AHB4ENSR_GPIOPENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENSR_GPIOPENS                   RCC_AHB4ENSR_GPIOPENS_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENSR_GPIOQENS_Pos               (16U)
+#define RCC_AHB4ENSR_GPIOQENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENSR_GPIOQENS                   RCC_AHB4ENSR_GPIOQENS_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENSR_PWRENS_Pos                 (18U)
+#define RCC_AHB4ENSR_PWRENS_Msk                 (0x1UL << RCC_AHB4ENSR_PWRENS_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENSR_PWRENS                     RCC_AHB4ENSR_PWRENS_Msk              /*!< PWR enable */
+#define RCC_AHB4ENSR_CRCENS_Pos                 (19U)
+#define RCC_AHB4ENSR_CRCENS_Msk                 (0x1UL << RCC_AHB4ENSR_CRCENS_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENSR_CRCENS                     RCC_AHB4ENSR_CRCENS_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENSR register  *****************/
+#define RCC_AHB5ENSR_HPDMA1ENS_Pos              (0U)
+#define RCC_AHB5ENSR_HPDMA1ENS_Msk              (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENSR_HPDMA1ENS                  RCC_AHB5ENSR_HPDMA1ENS_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENSR_DMA2DENS_Pos               (1U)
+#define RCC_AHB5ENSR_DMA2DENS_Msk               (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENSR_DMA2DENS                   RCC_AHB5ENSR_DMA2DENS_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENSR_JPEGENS_Pos                (3U)
+#define RCC_AHB5ENSR_JPEGENS_Msk                (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENSR_JPEGENS                    RCC_AHB5ENSR_JPEGENS_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENSR_FMCENS_Pos                 (4U)
+#define RCC_AHB5ENSR_FMCENS_Msk                 (0x1UL << RCC_AHB5ENSR_FMCENS_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENSR_FMCENS                     RCC_AHB5ENSR_FMCENS_Msk              /*!< FMC enable */
+#define RCC_AHB5ENSR_XSPI1ENS_Pos               (5U)
+#define RCC_AHB5ENSR_XSPI1ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENSR_XSPI1ENS                   RCC_AHB5ENSR_XSPI1ENS_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENSR_PSSIENS_Pos                (6U)
+#define RCC_AHB5ENSR_PSSIENS_Msk                (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENSR_PSSIENS                    RCC_AHB5ENSR_PSSIENS_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENSR_SDMMC2ENS_Pos              (7U)
+#define RCC_AHB5ENSR_SDMMC2ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENSR_SDMMC2ENS                  RCC_AHB5ENSR_SDMMC2ENS_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENSR_SDMMC1ENS_Pos              (8U)
+#define RCC_AHB5ENSR_SDMMC1ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENSR_SDMMC1ENS                  RCC_AHB5ENSR_SDMMC1ENS_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENSR_XSPI2ENS_Pos               (12U)
+#define RCC_AHB5ENSR_XSPI2ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENSR_XSPI2ENS                   RCC_AHB5ENSR_XSPI2ENS_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENSR_XSPIMENS_Pos               (13U)
+#define RCC_AHB5ENSR_XSPIMENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENSR_XSPIMENS                   RCC_AHB5ENSR_XSPIMENS_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENSR_XSPI3ENS_Pos               (17U)
+#define RCC_AHB5ENSR_XSPI3ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENSR_XSPI3ENS                   RCC_AHB5ENSR_XSPI3ENS_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENSR_GFXMMUENS_Pos              (19U)
+#define RCC_AHB5ENSR_GFXMMUENS_Msk              (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENSR_GFXMMUENS                  RCC_AHB5ENSR_GFXMMUENS_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENSR_GPU2DENS_Pos               (20U)
+#define RCC_AHB5ENSR_GPU2DENS_Msk               (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENSR_GPU2DENS                   RCC_AHB5ENSR_GPU2DENS_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENSR_ETH1MACENS_Pos             (22U)
+#define RCC_AHB5ENSR_ETH1MACENS_Msk             (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENSR_ETH1MACENS                 RCC_AHB5ENSR_ETH1MACENS_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENSR_ETH1TXENS_Pos              (23U)
+#define RCC_AHB5ENSR_ETH1TXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENSR_ETH1TXENS                  RCC_AHB5ENSR_ETH1TXENS_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENSR_ETH1RXENS_Pos              (24U)
+#define RCC_AHB5ENSR_ETH1RXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENSR_ETH1RXENS                  RCC_AHB5ENSR_ETH1RXENS_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENSR_ETH1ENS_Pos                (25U)
+#define RCC_AHB5ENSR_ETH1ENS_Msk                (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENSR_ETH1ENS                    RCC_AHB5ENSR_ETH1ENS_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENSR_OTG1ENS_Pos                (26U)
+#define RCC_AHB5ENSR_OTG1ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENSR_OTG1ENS                    RCC_AHB5ENSR_OTG1ENS_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENSR_OTGPHY1ENS_Pos             (27U)
+#define RCC_AHB5ENSR_OTGPHY1ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENSR_OTGPHY1ENS                 RCC_AHB5ENSR_OTGPHY1ENS_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENSR_OTGPHY2ENS_Pos             (28U)
+#define RCC_AHB5ENSR_OTGPHY2ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENSR_OTGPHY2ENS                 RCC_AHB5ENSR_OTGPHY2ENS_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENSR_OTG2ENS_Pos                (29U)
+#define RCC_AHB5ENSR_OTG2ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENSR_OTG2ENS                    RCC_AHB5ENSR_OTG2ENS_Msk             /*!< OTG2 enable */
+#define RCC_AHB5ENSR_CACHEAXIENS_Pos            (30U)
+#define RCC_AHB5ENSR_CACHEAXIENS_Msk            (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */
+#define RCC_AHB5ENSR_CACHEAXIENS                RCC_AHB5ENSR_CACHEAXIENS_Msk         /*!< CACHEAXI enable */
+#define RCC_AHB5ENSR_NPUENS_Pos                 (31U)
+#define RCC_AHB5ENSR_NPUENS_Msk                 (0x1UL << RCC_AHB5ENSR_NPUENS_Pos)    /*!< 0x80000000 */
+#define RCC_AHB5ENSR_NPUENS                     RCC_AHB5ENSR_NPUENS_Msk              /*!< NPU enable */
+
+/****************  Bit definition for RCC_APB1ENSR1 register  *****************/
+#define RCC_APB1ENSR1_TIM2ENS_Pos               (0U)
+#define RCC_APB1ENSR1_TIM2ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENSR1_TIM2ENS                   RCC_APB1ENSR1_TIM2ENS_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENSR1_TIM3ENS_Pos               (1U)
+#define RCC_APB1ENSR1_TIM3ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENSR1_TIM3ENS                   RCC_APB1ENSR1_TIM3ENS_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENSR1_TIM4ENS_Pos               (2U)
+#define RCC_APB1ENSR1_TIM4ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENSR1_TIM4ENS                   RCC_APB1ENSR1_TIM4ENS_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENSR1_TIM5ENS_Pos               (3U)
+#define RCC_APB1ENSR1_TIM5ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENSR1_TIM5ENS                   RCC_APB1ENSR1_TIM5ENS_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENSR1_TIM6ENS_Pos               (4U)
+#define RCC_APB1ENSR1_TIM6ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENSR1_TIM6ENS                   RCC_APB1ENSR1_TIM6ENS_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENSR1_TIM7ENS_Pos               (5U)
+#define RCC_APB1ENSR1_TIM7ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENSR1_TIM7ENS                   RCC_APB1ENSR1_TIM7ENS_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENSR1_TIM12ENS_Pos              (6U)
+#define RCC_APB1ENSR1_TIM12ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENSR1_TIM12ENS                  RCC_APB1ENSR1_TIM12ENS_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENSR1_TIM13ENS_Pos              (7U)
+#define RCC_APB1ENSR1_TIM13ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENSR1_TIM13ENS                  RCC_APB1ENSR1_TIM13ENS_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENSR1_TIM14ENS_Pos              (8U)
+#define RCC_APB1ENSR1_TIM14ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR1_TIM14ENS                  RCC_APB1ENSR1_TIM14ENS_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENSR1_LPTIM1ENS_Pos             (9U)
+#define RCC_APB1ENSR1_LPTIM1ENS_Msk             (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENSR1_LPTIM1ENS                 RCC_APB1ENSR1_LPTIM1ENS_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENSR1_WWDGENS_Pos               (11U)
+#define RCC_APB1ENSR1_WWDGENS_Msk               (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1ENSR1_WWDGENS                   RCC_APB1ENSR1_WWDGENS_Msk            /*!< WWDG enable */
+#define RCC_APB1ENSR1_TIM10ENS_Pos              (12U)
+#define RCC_APB1ENSR1_TIM10ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENSR1_TIM10ENS                  RCC_APB1ENSR1_TIM10ENS_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENSR1_TIM11ENS_Pos              (13U)
+#define RCC_APB1ENSR1_TIM11ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENSR1_TIM11ENS                  RCC_APB1ENSR1_TIM11ENS_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENSR1_SPI2ENS_Pos               (14U)
+#define RCC_APB1ENSR1_SPI2ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENSR1_SPI2ENS                   RCC_APB1ENSR1_SPI2ENS_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENSR1_SPI3ENS_Pos               (15U)
+#define RCC_APB1ENSR1_SPI3ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENSR1_SPI3ENS                   RCC_APB1ENSR1_SPI3ENS_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos           (16U)
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk           (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENSR1_SPDIFRX1ENS               RCC_APB1ENSR1_SPDIFRX1ENS_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENSR1_USART2ENS_Pos             (17U)
+#define RCC_APB1ENSR1_USART2ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENSR1_USART2ENS                 RCC_APB1ENSR1_USART2ENS_Msk          /*!< USART2 enable */
+#define RCC_APB1ENSR1_USART3ENS_Pos             (18U)
+#define RCC_APB1ENSR1_USART3ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENSR1_USART3ENS                 RCC_APB1ENSR1_USART3ENS_Msk          /*!< USART3 enable */
+#define RCC_APB1ENSR1_UART4ENS_Pos              (19U)
+#define RCC_APB1ENSR1_UART4ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENSR1_UART4ENS                  RCC_APB1ENSR1_UART4ENS_Msk           /*!< UART4 enable */
+#define RCC_APB1ENSR1_UART5ENS_Pos              (20U)
+#define RCC_APB1ENSR1_UART5ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENSR1_UART5ENS                  RCC_APB1ENSR1_UART5ENS_Msk           /*!< UART5 enable */
+#define RCC_APB1ENSR1_I2C1ENS_Pos               (21U)
+#define RCC_APB1ENSR1_I2C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENSR1_I2C1ENS                   RCC_APB1ENSR1_I2C1ENS_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENSR1_I2C2ENS_Pos               (22U)
+#define RCC_APB1ENSR1_I2C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENSR1_I2C2ENS                   RCC_APB1ENSR1_I2C2ENS_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENSR1_I2C3ENS_Pos               (23U)
+#define RCC_APB1ENSR1_I2C3ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENSR1_I2C3ENS                   RCC_APB1ENSR1_I2C3ENS_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENSR1_I3C1ENS_Pos               (24U)
+#define RCC_APB1ENSR1_I3C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENSR1_I3C1ENS                   RCC_APB1ENSR1_I3C1ENS_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENSR1_I3C2ENS_Pos               (25U)
+#define RCC_APB1ENSR1_I3C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENSR1_I3C2ENS                   RCC_APB1ENSR1_I3C2ENS_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENSR1_UART7ENS_Pos              (30U)
+#define RCC_APB1ENSR1_UART7ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENSR1_UART7ENS                  RCC_APB1ENSR1_UART7ENS_Msk           /*!< UART7 enable */
+#define RCC_APB1ENSR1_UART8ENS_Pos              (31U)
+#define RCC_APB1ENSR1_UART8ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENSR1_UART8ENS                  RCC_APB1ENSR1_UART8ENS_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENSR2 register  *****************/
+#define RCC_APB1ENSR2_MDIOSENS_Pos              (5U)
+#define RCC_APB1ENSR2_MDIOSENS_Msk              (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENSR2_MDIOSENS                  RCC_APB1ENSR2_MDIOSENS_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENSR2_FDCANENS_Pos              (8U)
+#define RCC_APB1ENSR2_FDCANENS_Msk              (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR2_FDCANENS                  RCC_APB1ENSR2_FDCANENS_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENSR2_UCPD1ENS_Pos              (18U)
+#define RCC_APB1ENSR2_UCPD1ENS_Msk              (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENSR2_UCPD1ENS                  RCC_APB1ENSR2_UCPD1ENS_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENSR register  *****************/
+#define RCC_APB2ENSR_TIM1ENS_Pos                (0U)
+#define RCC_APB2ENSR_TIM1ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENSR_TIM1ENS                    RCC_APB2ENSR_TIM1ENS_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENSR_TIM8ENS_Pos                (1U)
+#define RCC_APB2ENSR_TIM8ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENSR_TIM8ENS                    RCC_APB2ENSR_TIM8ENS_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENSR_USART1ENS_Pos              (4U)
+#define RCC_APB2ENSR_USART1ENS_Msk              (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENSR_USART1ENS                  RCC_APB2ENSR_USART1ENS_Msk           /*!< USART1 enable */
+#define RCC_APB2ENSR_USART6ENS_Pos              (5U)
+#define RCC_APB2ENSR_USART6ENS_Msk              (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENSR_USART6ENS                  RCC_APB2ENSR_USART6ENS_Msk           /*!< USART6 enable */
+#define RCC_APB2ENSR_UART9ENS_Pos               (6U)
+#define RCC_APB2ENSR_UART9ENS_Msk               (0x1UL << RCC_APB2ENSR_UART9ENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENSR_UART9ENS                   RCC_APB2ENSR_UART9ENS_Msk            /*!< UART9 enable */
+#define RCC_APB2ENSR_USART10ENS_Pos             (7U)
+#define RCC_APB2ENSR_USART10ENS_Msk             (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENSR_USART10ENS                 RCC_APB2ENSR_USART10ENS_Msk          /*!< USART10 enable */
+#define RCC_APB2ENSR_SPI1ENS_Pos                (12U)
+#define RCC_APB2ENSR_SPI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENSR_SPI1ENS                    RCC_APB2ENSR_SPI1ENS_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENSR_SPI4ENS_Pos                (13U)
+#define RCC_APB2ENSR_SPI4ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENSR_SPI4ENS                    RCC_APB2ENSR_SPI4ENS_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENSR_TIM18ENS_Pos               (15U)
+#define RCC_APB2ENSR_TIM18ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENSR_TIM18ENS                   RCC_APB2ENSR_TIM18ENS_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENSR_TIM15ENS_Pos               (16U)
+#define RCC_APB2ENSR_TIM15ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENSR_TIM15ENS                   RCC_APB2ENSR_TIM15ENS_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENSR_TIM16ENS_Pos               (17U)
+#define RCC_APB2ENSR_TIM16ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENSR_TIM16ENS                   RCC_APB2ENSR_TIM16ENS_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENSR_TIM17ENS_Pos               (18U)
+#define RCC_APB2ENSR_TIM17ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENSR_TIM17ENS                   RCC_APB2ENSR_TIM17ENS_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENSR_TIM9ENS_Pos                (19U)
+#define RCC_APB2ENSR_TIM9ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENSR_TIM9ENS                    RCC_APB2ENSR_TIM9ENS_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENSR_SPI5ENS_Pos                (20U)
+#define RCC_APB2ENSR_SPI5ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENSR_SPI5ENS                    RCC_APB2ENSR_SPI5ENS_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENSR_SAI1ENS_Pos                (21U)
+#define RCC_APB2ENSR_SAI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENSR_SAI1ENS                    RCC_APB2ENSR_SAI1ENS_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENSR_SAI2ENS_Pos                (22U)
+#define RCC_APB2ENSR_SAI2ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENSR_SAI2ENS                    RCC_APB2ENSR_SAI2ENS_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENSR register  *****************/
+#define RCC_APB3ENSR_DFTENS_Pos                 (2U)
+#define RCC_APB3ENSR_DFTENS_Msk                 (0x1UL << RCC_APB3ENSR_DFTENS_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENSR_DFTENS                     RCC_APB3ENSR_DFTENS_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENSR1 register  *****************/
+#define RCC_APB4ENSR1_HDPENS_Pos                (2U)
+#define RCC_APB4ENSR1_HDPENS_Msk                (0x1UL << RCC_APB4ENSR1_HDPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR1_HDPENS                    RCC_APB4ENSR1_HDPENS_Msk             /*!< HDP enable */
+#define RCC_APB4ENSR1_LPUART1ENS_Pos            (3U)
+#define RCC_APB4ENSR1_LPUART1ENS_Msk            (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENSR1_LPUART1ENS                RCC_APB4ENSR1_LPUART1ENS_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENSR1_SPI6ENS_Pos               (5U)
+#define RCC_APB4ENSR1_SPI6ENS_Msk               (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENSR1_SPI6ENS                   RCC_APB4ENSR1_SPI6ENS_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENSR1_I2C4ENS_Pos               (7U)
+#define RCC_APB4ENSR1_I2C4ENS_Msk               (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENSR1_I2C4ENS                   RCC_APB4ENSR1_I2C4ENS_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENSR1_LPTIM2ENS_Pos             (9U)
+#define RCC_APB4ENSR1_LPTIM2ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENSR1_LPTIM2ENS                 RCC_APB4ENSR1_LPTIM2ENS_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENSR1_LPTIM3ENS_Pos             (10U)
+#define RCC_APB4ENSR1_LPTIM3ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENSR1_LPTIM3ENS                 RCC_APB4ENSR1_LPTIM3ENS_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENSR1_LPTIM4ENS_Pos             (11U)
+#define RCC_APB4ENSR1_LPTIM4ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENSR1_LPTIM4ENS                 RCC_APB4ENSR1_LPTIM4ENS_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENSR1_LPTIM5ENS_Pos             (12U)
+#define RCC_APB4ENSR1_LPTIM5ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENSR1_LPTIM5ENS                 RCC_APB4ENSR1_LPTIM5ENS_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENSR1_VREFBUFENS_Pos            (15U)
+#define RCC_APB4ENSR1_VREFBUFENS_Msk            (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENSR1_VREFBUFENS                RCC_APB4ENSR1_VREFBUFENS_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENSR1_RTCENS_Pos                (16U)
+#define RCC_APB4ENSR1_RTCENS_Msk                (0x1UL << RCC_APB4ENSR1_RTCENS_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENSR1_RTCENS                    RCC_APB4ENSR1_RTCENS_Msk             /*!< RTC enable */
+#define RCC_APB4ENSR1_RTCAPBENS_Pos             (17U)
+#define RCC_APB4ENSR1_RTCAPBENS_Msk             (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENSR1_RTCAPBENS                 RCC_APB4ENSR1_RTCAPBENS_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENSR2 register  *****************/
+#define RCC_APB4ENSR2_SYSCFGENS_Pos             (0U)
+#define RCC_APB4ENSR2_SYSCFGENS_Msk             (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENSR2_SYSCFGENS                 RCC_APB4ENSR2_SYSCFGENS_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENSR2_BSECENS_Pos               (1U)
+#define RCC_APB4ENSR2_BSECENS_Msk               (0x1UL << RCC_APB4ENSR2_BSECENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENSR2_BSECENS                   RCC_APB4ENSR2_BSECENS_Msk            /*!< BSEC enable */
+#define RCC_APB4ENSR2_DTSENS_Pos                (2U)
+#define RCC_APB4ENSR2_DTSENS_Msk                (0x1UL << RCC_APB4ENSR2_DTSENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR2_DTSENS                    RCC_APB4ENSR2_DTSENS_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENSR register  *****************/
+#define RCC_APB5ENSR_LTDCENS_Pos                (1U)
+#define RCC_APB5ENSR_LTDCENS_Msk                (0x1UL << RCC_APB5ENSR_LTDCENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENSR_LTDCENS                    RCC_APB5ENSR_LTDCENS_Msk             /*!< LTDC enable */
+#define RCC_APB5ENSR_DCMIPPENS_Pos              (2U)
+#define RCC_APB5ENSR_DCMIPPENS_Msk              (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENSR_DCMIPPENS                  RCC_APB5ENSR_DCMIPPENS_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENSR_GFXTIMENS_Pos              (4U)
+#define RCC_APB5ENSR_GFXTIMENS_Msk              (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENSR_GFXTIMENS                  RCC_APB5ENSR_GFXTIMENS_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENSR_VENCENS_Pos                (5U)
+#define RCC_APB5ENSR_VENCENS_Msk                (0x1UL << RCC_APB5ENSR_VENCENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENSR_VENCENS                    RCC_APB5ENSR_VENCENS_Msk             /*!< VENC enable */
+#define RCC_APB5ENSR_CSIENS_Pos                 (6U)
+#define RCC_APB5ENSR_CSIENS_Msk                 (0x1UL << RCC_APB5ENSR_CSIENS_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENSR_CSIENS                     RCC_APB5ENSR_CSIENS_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENSR register  *****************/
+#define RCC_BUSLPENSR_ACLKNLPENS_Pos            (0U)
+#define RCC_BUSLPENSR_ACLKNLPENS_Msk            (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENSR_ACLKNLPENS                RCC_BUSLPENSR_ACLKNLPENS_Msk         /*!< ACLKN enable  */
+#define RCC_BUSLPENSR_ACLKNCLPENS_Pos           (1U)
+#define RCC_BUSLPENSR_ACLKNCLPENS_Msk           (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENSR_ACLKNCLPENS               RCC_BUSLPENSR_ACLKNCLPENS_Msk        /*!< ACLKNC enable  */
+
+/****************  Bit definition for RCC_MISCLPENSR register  ****************/
+#define RCC_MISCLPENSR_DBGLPENS_Pos             (0U)
+#define RCC_MISCLPENSR_DBGLPENS_Msk             (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENSR_DBGLPENS                 RCC_MISCLPENSR_DBGLPENS_Msk          /*!< DBG enable  */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos     (3U)
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk     (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS         RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk  /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENSR_PERLPENS_Pos             (6U)
+#define RCC_MISCLPENSR_PERLPENS_Msk             (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENSR_PERLPENS                 RCC_MISCLPENSR_PERLPENS_Msk          /*!< PER enable  */
+
+/****************  Bit definition for RCC_MEMLPENSR register  *****************/
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos         (0U)
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENSR_AXISRAM3LPENS             RCC_MEMLPENSR_AXISRAM3LPENS_Msk      /*!< AXISRAM3 enable  */
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos         (1U)
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENSR_AXISRAM4LPENS             RCC_MEMLPENSR_AXISRAM4LPENS_Msk      /*!< AXISRAM4 enable  */
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos         (2U)
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENSR_AXISRAM5LPENS             RCC_MEMLPENSR_AXISRAM5LPENS_Msk      /*!< AXISRAM5 enable  */
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos         (3U)
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENSR_AXISRAM6LPENS             RCC_MEMLPENSR_AXISRAM6LPENS_Msk      /*!< AXISRAM6 enable  */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos         (4U)
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS             RCC_MEMLPENSR_AHBSRAM1LPENS_Msk      /*!< AHBSRAM1 enable  */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos         (5U)
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS             RCC_MEMLPENSR_AHBSRAM2LPENS_Msk      /*!< AHBSRAM2 enable  */
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos          (6U)
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENSR_BKPSRAMLPENS              RCC_MEMLPENSR_BKPSRAMLPENS_Msk       /*!< BKPSRAM enable  */
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos         (7U)
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENSR_AXISRAM1LPENS             RCC_MEMLPENSR_AXISRAM1LPENS_Msk      /*!< AXISRAM1 enable  */
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos         (8U)
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENSR_AXISRAM2LPENS             RCC_MEMLPENSR_AXISRAM2LPENS_Msk      /*!< AXISRAM2 enable  */
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos          (9U)
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENSR_FLEXRAMLPENS              RCC_MEMLPENSR_FLEXRAMLPENS_Msk       /*!< FLEXRAM enable  */
+#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos      (10U)
+#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk      (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos)       /*!< 0x00000400 */
+#define RCC_MEMLPENSR_CACHEAXIRAMLPENS          RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk   /*!< CACHEAXIRAM enable  */
+#define RCC_MEMLPENSR_VENCRAMLPENS_Pos          (11U)
+#define RCC_MEMLPENSR_VENCRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENSR_VENCRAMLPENS              RCC_MEMLPENSR_VENCRAMLPENS_Msk       /*!< VENCRAM enable  */
+#define RCC_MEMLPENSR_BOOTROMLPENS_Pos          (12U)
+#define RCC_MEMLPENSR_BOOTROMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENSR_BOOTROMLPENS              RCC_MEMLPENSR_BOOTROMLPENS_Msk       /*!< Boot ROM enable  */
+
+/****************  Bit definition for RCC_AHB1LPENSR register  ****************/
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos          (4U)
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk          (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENSR_GPDMA1LPENS              RCC_AHB1LPENSR_GPDMA1LPENS_Msk       /*!< GPDMA1 enable  */
+#define RCC_AHB1LPENSR_ADC12LPENS_Pos           (5U)
+#define RCC_AHB1LPENSR_ADC12LPENS_Msk           (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENSR_ADC12LPENS               RCC_AHB1LPENSR_ADC12LPENS_Msk        /*!< ADC12 enable  */
+
+/****************  Bit definition for RCC_AHB2LPENSR register  ****************/
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos          (12U)
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk          (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENSR_RAMCFGLPENS              RCC_AHB2LPENSR_RAMCFGLPENS_Msk       /*!< RAMCFG enable  */
+#define RCC_AHB2LPENSR_MDF1LPENS_Pos            (16U)
+#define RCC_AHB2LPENSR_MDF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENSR_MDF1LPENS                RCC_AHB2LPENSR_MDF1LPENS_Msk         /*!< MDF1 enable  */
+#define RCC_AHB2LPENSR_ADF1LPENS_Pos            (17U)
+#define RCC_AHB2LPENSR_ADF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENSR_ADF1LPENS                RCC_AHB2LPENSR_ADF1LPENS_Msk         /*!< ADF1 enable  */
+
+/****************  Bit definition for RCC_AHB3LPENSR register  ****************/
+#define RCC_AHB3LPENSR_RNGLPENS_Pos             (0U)
+#define RCC_AHB3LPENSR_RNGLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENSR_RNGLPENS                 RCC_AHB3LPENSR_RNGLPENS_Msk          /*!< RNG enable  */
+#define RCC_AHB3LPENSR_HASHLPENS_Pos            (1U)
+#define RCC_AHB3LPENSR_HASHLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENSR_HASHLPENS                RCC_AHB3LPENSR_HASHLPENS_Msk         /*!< HASH enable  */
+#define RCC_AHB3LPENSR_PKALPENS_Pos             (8U)
+#define RCC_AHB3LPENSR_PKALPENS_Msk             (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENSR_PKALPENS                 RCC_AHB3LPENSR_PKALPENS_Msk          /*!< PKA enable  */
+#define RCC_AHB3LPENSR_RIFSCLPENS_Pos           (9U)
+#define RCC_AHB3LPENSR_RIFSCLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENSR_RIFSCLPENS               RCC_AHB3LPENSR_RIFSCLPENS_Msk        /*!< RIFSC enable  */
+#define RCC_AHB3LPENSR_IACLPENS_Pos             (10U)
+#define RCC_AHB3LPENSR_IACLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENSR_IACLPENS                 RCC_AHB3LPENSR_IACLPENS_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENSR_RISAFLPENS_Pos           (14U)
+#define RCC_AHB3LPENSR_RISAFLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENSR_RISAFLPENS               RCC_AHB3LPENSR_RISAFLPENS_Msk        /*!< RISAF enable  */
+
+/****************  Bit definition for RCC_AHB4LPENSR register  ****************/
+#define RCC_AHB4LPENSR_GPIOALPENS_Pos           (0U)
+#define RCC_AHB4LPENSR_GPIOALPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENSR_GPIOALPENS               RCC_AHB4LPENSR_GPIOALPENS_Msk        /*!< GPIO A enable  */
+#define RCC_AHB4LPENSR_GPIOBLPENS_Pos           (1U)
+#define RCC_AHB4LPENSR_GPIOBLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENSR_GPIOBLPENS               RCC_AHB4LPENSR_GPIOBLPENS_Msk        /*!< GPIO B enable  */
+#define RCC_AHB4LPENSR_GPIOCLPENS_Pos           (2U)
+#define RCC_AHB4LPENSR_GPIOCLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENSR_GPIOCLPENS               RCC_AHB4LPENSR_GPIOCLPENS_Msk        /*!< GPIO C enable  */
+#define RCC_AHB4LPENSR_GPIODLPENS_Pos           (3U)
+#define RCC_AHB4LPENSR_GPIODLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENSR_GPIODLPENS               RCC_AHB4LPENSR_GPIODLPENS_Msk        /*!< GPIO D enable  */
+#define RCC_AHB4LPENSR_GPIOELPENS_Pos           (4U)
+#define RCC_AHB4LPENSR_GPIOELPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENSR_GPIOELPENS               RCC_AHB4LPENSR_GPIOELPENS_Msk        /*!< GPIO E enable  */
+#define RCC_AHB4LPENSR_GPIOFLPENS_Pos           (5U)
+#define RCC_AHB4LPENSR_GPIOFLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENSR_GPIOFLPENS               RCC_AHB4LPENSR_GPIOFLPENS_Msk        /*!< GPIO F enable  */
+#define RCC_AHB4LPENSR_GPIOGLPENS_Pos           (6U)
+#define RCC_AHB4LPENSR_GPIOGLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENSR_GPIOGLPENS               RCC_AHB4LPENSR_GPIOGLPENS_Msk        /*!< GPIO G enable  */
+#define RCC_AHB4LPENSR_GPIOHLPENS_Pos           (7U)
+#define RCC_AHB4LPENSR_GPIOHLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENSR_GPIOHLPENS               RCC_AHB4LPENSR_GPIOHLPENS_Msk        /*!< GPIO H enable  */
+#define RCC_AHB4LPENSR_GPIONLPENS_Pos           (13U)
+#define RCC_AHB4LPENSR_GPIONLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENSR_GPIONLPENS               RCC_AHB4LPENSR_GPIONLPENS_Msk        /*!< GPIO N enable  */
+#define RCC_AHB4LPENSR_GPIOOLPENS_Pos           (14U)
+#define RCC_AHB4LPENSR_GPIOOLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENSR_GPIOOLPENS               RCC_AHB4LPENSR_GPIOOLPENS_Msk        /*!< GPIO O enable  */
+#define RCC_AHB4LPENSR_GPIOPLPENS_Pos           (15U)
+#define RCC_AHB4LPENSR_GPIOPLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENSR_GPIOPLPENS               RCC_AHB4LPENSR_GPIOPLPENS_Msk        /*!< GPIO P enable  */
+#define RCC_AHB4LPENSR_GPIOQLPENS_Pos           (16U)
+#define RCC_AHB4LPENSR_GPIOQLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENSR_GPIOQLPENS               RCC_AHB4LPENSR_GPIOQLPENS_Msk        /*!< GPIO Q enable  */
+#define RCC_AHB4LPENSR_PWRLPENS_Pos             (18U)
+#define RCC_AHB4LPENSR_PWRLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENSR_PWRLPENS                 RCC_AHB4LPENSR_PWRLPENS_Msk          /*!< PWR enable  */
+#define RCC_AHB4LPENSR_CRCLPENS_Pos             (19U)
+#define RCC_AHB4LPENSR_CRCLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENSR_CRCLPENS                 RCC_AHB4LPENSR_CRCLPENS_Msk          /*!< CRC enable  */
+
+/****************  Bit definition for RCC_AHB5LPENSR register  ****************/
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos          (0U)
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENSR_HPDMA1LPENS              RCC_AHB5LPENSR_HPDMA1LPENS_Msk       /*!< HPDMA1 enable  */
+#define RCC_AHB5LPENSR_DMA2DLPENS_Pos           (1U)
+#define RCC_AHB5LPENSR_DMA2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENSR_DMA2DLPENS               RCC_AHB5LPENSR_DMA2DLPENS_Msk        /*!< DMA2D enable  */
+#define RCC_AHB5LPENSR_JPEGLPENS_Pos            (3U)
+#define RCC_AHB5LPENSR_JPEGLPENS_Msk            (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENSR_JPEGLPENS                RCC_AHB5LPENSR_JPEGLPENS_Msk         /*!< JPEG enable  */
+#define RCC_AHB5LPENSR_FMCLPENS_Pos             (4U)
+#define RCC_AHB5LPENSR_FMCLPENS_Msk             (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENSR_FMCLPENS                 RCC_AHB5LPENSR_FMCLPENS_Msk          /*!< FMC enable  */
+#define RCC_AHB5LPENSR_XSPI1LPENS_Pos           (5U)
+#define RCC_AHB5LPENSR_XSPI1LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENSR_XSPI1LPENS               RCC_AHB5LPENSR_XSPI1LPENS_Msk        /*!< XSPI1 enable  */
+#define RCC_AHB5LPENSR_PSSILPENS_Pos            (6U)
+#define RCC_AHB5LPENSR_PSSILPENS_Msk            (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENSR_PSSILPENS                RCC_AHB5LPENSR_PSSILPENS_Msk         /*!< PSSI enable  */
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos          (7U)
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENSR_SDMMC2LPENS              RCC_AHB5LPENSR_SDMMC2LPENS_Msk       /*!< SDMMC2 enable  */
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos          (8U)
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENSR_SDMMC1LPENS              RCC_AHB5LPENSR_SDMMC1LPENS_Msk       /*!< SDMMC1 enable  */
+#define RCC_AHB5LPENSR_XSPI2LPENS_Pos           (12U)
+#define RCC_AHB5LPENSR_XSPI2LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENSR_XSPI2LPENS               RCC_AHB5LPENSR_XSPI2LPENS_Msk        /*!< XSPI2 enable  */
+#define RCC_AHB5LPENSR_XSPIMLPENS_Pos           (13U)
+#define RCC_AHB5LPENSR_XSPIMLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENSR_XSPIMLPENS               RCC_AHB5LPENSR_XSPIMLPENS_Msk        /*!< XSPIM enable  */
+#define RCC_AHB5LPENSR_XSPI3LPENS_Pos           (17U)
+#define RCC_AHB5LPENSR_XSPI3LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENSR_XSPI3LPENS               RCC_AHB5LPENSR_XSPI3LPENS_Msk        /*!< XSPI3 enable  */
+#define RCC_AHB5LPENSR_GFXMMULPENS_Pos          (19U)
+#define RCC_AHB5LPENSR_GFXMMULPENS_Msk          (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENSR_GFXMMULPENS              RCC_AHB5LPENSR_GFXMMULPENS_Msk       /*!< GFXMMU enable  */
+#define RCC_AHB5LPENSR_GPU2DLPENS_Pos           (20U)
+#define RCC_AHB5LPENSR_GPU2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENSR_GPU2DLPENS               RCC_AHB5LPENSR_GPU2DLPENS_Msk        /*!< GPU2D enable */
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos         (22U)
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk         (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENSR_ETH1MACLPENS             RCC_AHB5LPENSR_ETH1MACLPENS_Msk      /*!< ETH1MAC enable  */
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos          (23U)
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENSR_ETH1TXLPENS              RCC_AHB5LPENSR_ETH1TXLPENS_Msk       /*!< ETH1TX enable  */
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos          (24U)
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENSR_ETH1RXLPENS              RCC_AHB5LPENSR_ETH1RXLPENS_Msk       /*!< ETH1RX enable  */
+#define RCC_AHB5LPENSR_ETH1LPENS_Pos            (25U)
+#define RCC_AHB5LPENSR_ETH1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENSR_ETH1LPENS                RCC_AHB5LPENSR_ETH1LPENS_Msk         /*!< ETH1 enable  */
+#define RCC_AHB5LPENSR_OTG1LPENS_Pos            (26U)
+#define RCC_AHB5LPENSR_OTG1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENSR_OTG1LPENS                RCC_AHB5LPENSR_OTG1LPENS_Msk         /*!< OTG1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos         (27U)
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS             RCC_AHB5LPENSR_OTGPHY1LPENS_Msk      /*!< OTGPHY1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos         (28U)
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS             RCC_AHB5LPENSR_OTGPHY2LPENS_Msk      /*!< OTGPHY2 enable  */
+#define RCC_AHB5LPENSR_OTG2LPENS_Pos            (29U)
+#define RCC_AHB5LPENSR_OTG2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENSR_OTG2LPENS                RCC_AHB5LPENSR_OTG2LPENS_Msk         /*!< OTG2 enable  */
+#define RCC_AHB5LPENSR_CACHEAXILPENS_Pos        (30U)
+#define RCC_AHB5LPENSR_CACHEAXILPENS_Msk        (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos)     /*!< 0x40000000 */
+#define RCC_AHB5LPENSR_CACHEAXILPENS            RCC_AHB5LPENSR_CACHEAXILPENS_Msk     /*!< CACHEAXI enable  */
+#define RCC_AHB5LPENSR_NPULPENS_Pos             (31U)
+#define RCC_AHB5LPENSR_NPULPENS_Msk             (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */
+#define RCC_AHB5LPENSR_NPULPENS                 RCC_AHB5LPENSR_NPULPENS_Msk          /*!< NPU enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR1 register  ****************/
+#define RCC_APB1LPENSR1_TIM2LPENS_Pos           (0U)
+#define RCC_APB1LPENSR1_TIM2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENSR1_TIM2LPENS               RCC_APB1LPENSR1_TIM2LPENS_Msk        /*!< TIM2 enable  */
+#define RCC_APB1LPENSR1_TIM3LPENS_Pos           (1U)
+#define RCC_APB1LPENSR1_TIM3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENSR1_TIM3LPENS               RCC_APB1LPENSR1_TIM3LPENS_Msk        /*!< TIM3 enable  */
+#define RCC_APB1LPENSR1_TIM4LPENS_Pos           (2U)
+#define RCC_APB1LPENSR1_TIM4LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENSR1_TIM4LPENS               RCC_APB1LPENSR1_TIM4LPENS_Msk        /*!< TIM4 enable  */
+#define RCC_APB1LPENSR1_TIM5LPENS_Pos           (3U)
+#define RCC_APB1LPENSR1_TIM5LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENSR1_TIM5LPENS               RCC_APB1LPENSR1_TIM5LPENS_Msk        /*!< TIM5 enable  */
+#define RCC_APB1LPENSR1_TIM6LPENS_Pos           (4U)
+#define RCC_APB1LPENSR1_TIM6LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENSR1_TIM6LPENS               RCC_APB1LPENSR1_TIM6LPENS_Msk        /*!< TIM6 enable  */
+#define RCC_APB1LPENSR1_TIM7LPENS_Pos           (5U)
+#define RCC_APB1LPENSR1_TIM7LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENSR1_TIM7LPENS               RCC_APB1LPENSR1_TIM7LPENS_Msk        /*!< TIM7 enable  */
+#define RCC_APB1LPENSR1_TIM12LPENS_Pos          (6U)
+#define RCC_APB1LPENSR1_TIM12LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENSR1_TIM12LPENS              RCC_APB1LPENSR1_TIM12LPENS_Msk       /*!< TIM12 enable  */
+#define RCC_APB1LPENSR1_TIM13LPENS_Pos          (7U)
+#define RCC_APB1LPENSR1_TIM13LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENSR1_TIM13LPENS              RCC_APB1LPENSR1_TIM13LPENS_Msk       /*!< TIM13 enable  */
+#define RCC_APB1LPENSR1_TIM14LPENS_Pos          (8U)
+#define RCC_APB1LPENSR1_TIM14LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR1_TIM14LPENS              RCC_APB1LPENSR1_TIM14LPENS_Msk       /*!< TIM14 enable  */
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos         (9U)
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENSR1_LPTIM1LPENS             RCC_APB1LPENSR1_LPTIM1LPENS_Msk      /*!< LPTIM1 enable  */
+#define RCC_APB1LPENSR1_WWDGLPENS_Pos           (11U)
+#define RCC_APB1LPENSR1_WWDGLPENS_Msk           (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENSR1_WWDGLPENS               RCC_APB1LPENSR1_WWDGLPENS_Msk        /*!< WWDG enable  */
+#define RCC_APB1LPENSR1_TIM10LPENS_Pos          (12U)
+#define RCC_APB1LPENSR1_TIM10LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENSR1_TIM10LPENS              RCC_APB1LPENSR1_TIM10LPENS_Msk       /*!< TIM10 enable  */
+#define RCC_APB1LPENSR1_TIM11LPENS_Pos          (13U)
+#define RCC_APB1LPENSR1_TIM11LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENSR1_TIM11LPENS              RCC_APB1LPENSR1_TIM11LPENS_Msk       /*!< TIM11 enable  */
+#define RCC_APB1LPENSR1_SPI2LPENS_Pos           (14U)
+#define RCC_APB1LPENSR1_SPI2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENSR1_SPI2LPENS               RCC_APB1LPENSR1_SPI2LPENS_Msk        /*!< SPI2 enable  */
+#define RCC_APB1LPENSR1_SPI3LPENS_Pos           (15U)
+#define RCC_APB1LPENSR1_SPI3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENSR1_SPI3LPENS               RCC_APB1LPENSR1_SPI3LPENS_Msk        /*!< SPI3 enable  */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos       (16U)
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk       (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS           RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk    /*!< SPDIFRX1 enable  */
+#define RCC_APB1LPENSR1_USART2LPENS_Pos         (17U)
+#define RCC_APB1LPENSR1_USART2LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENSR1_USART2LPENS             RCC_APB1LPENSR1_USART2LPENS_Msk      /*!< USART2 enable  */
+#define RCC_APB1LPENSR1_USART3LPENS_Pos         (18U)
+#define RCC_APB1LPENSR1_USART3LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENSR1_USART3LPENS             RCC_APB1LPENSR1_USART3LPENS_Msk      /*!< USART3 enable  */
+#define RCC_APB1LPENSR1_UART4LPENS_Pos          (19U)
+#define RCC_APB1LPENSR1_UART4LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENSR1_UART4LPENS              RCC_APB1LPENSR1_UART4LPENS_Msk       /*!< UART4 enable  */
+#define RCC_APB1LPENSR1_UART5LPENS_Pos          (20U)
+#define RCC_APB1LPENSR1_UART5LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENSR1_UART5LPENS              RCC_APB1LPENSR1_UART5LPENS_Msk       /*!< UART5 enable  */
+#define RCC_APB1LPENSR1_I2C1LPENS_Pos           (21U)
+#define RCC_APB1LPENSR1_I2C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENSR1_I2C1LPENS               RCC_APB1LPENSR1_I2C1LPENS_Msk        /*!< I2C1 enable  */
+#define RCC_APB1LPENSR1_I2C2LPENS_Pos           (22U)
+#define RCC_APB1LPENSR1_I2C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENSR1_I2C2LPENS               RCC_APB1LPENSR1_I2C2LPENS_Msk        /*!< I2C2 enable  */
+#define RCC_APB1LPENSR1_I2C3LPENS_Pos           (23U)
+#define RCC_APB1LPENSR1_I2C3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENSR1_I2C3LPENS               RCC_APB1LPENSR1_I2C3LPENS_Msk        /*!< I2C3 enable  */
+#define RCC_APB1LPENSR1_I3C1LPENS_Pos           (24U)
+#define RCC_APB1LPENSR1_I3C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENSR1_I3C1LPENS               RCC_APB1LPENSR1_I3C1LPENS_Msk        /*!< I3C1 enable  */
+#define RCC_APB1LPENSR1_I3C2LPENS_Pos           (25U)
+#define RCC_APB1LPENSR1_I3C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENSR1_I3C2LPENS               RCC_APB1LPENSR1_I3C2LPENS_Msk        /*!< I3C2 enable  */
+#define RCC_APB1LPENSR1_UART7LPENS_Pos          (30U)
+#define RCC_APB1LPENSR1_UART7LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENSR1_UART7LPENS              RCC_APB1LPENSR1_UART7LPENS_Msk       /*!< UART7 enable  */
+#define RCC_APB1LPENSR1_UART8LPENS_Pos          (31U)
+#define RCC_APB1LPENSR1_UART8LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENSR1_UART8LPENS              RCC_APB1LPENSR1_UART8LPENS_Msk       /*!< UART8 enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR2 register  ****************/
+#define RCC_APB1LPENSR2_MDIOSLPENS_Pos          (5U)
+#define RCC_APB1LPENSR2_MDIOSLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENSR2_MDIOSLPENS              RCC_APB1LPENSR2_MDIOSLPENS_Msk       /*!< MDIOS enable  */
+#define RCC_APB1LPENSR2_FDCANLPENS_Pos          (8U)
+#define RCC_APB1LPENSR2_FDCANLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR2_FDCANLPENS              RCC_APB1LPENSR2_FDCANLPENS_Msk       /*!< FDCAN enable  */
+#define RCC_APB1LPENSR2_UCPD1LPENS_Pos          (18U)
+#define RCC_APB1LPENSR2_UCPD1LPENS_Msk          (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENSR2_UCPD1LPENS              RCC_APB1LPENSR2_UCPD1LPENS_Msk       /*!< UCPD1 enable  */
+
+/****************  Bit definition for RCC_APB2LPENSR register  ****************/
+#define RCC_APB2LPENSR_TIM1LPENS_Pos            (0U)
+#define RCC_APB2LPENSR_TIM1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENSR_TIM1LPENS                RCC_APB2LPENSR_TIM1LPENS_Msk         /*!< TIM1 enable  */
+#define RCC_APB2LPENSR_TIM8LPENS_Pos            (1U)
+#define RCC_APB2LPENSR_TIM8LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENSR_TIM8LPENS                RCC_APB2LPENSR_TIM8LPENS_Msk         /*!< TIM8 enable  */
+#define RCC_APB2LPENSR_USART1LPENS_Pos          (4U)
+#define RCC_APB2LPENSR_USART1LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENSR_USART1LPENS              RCC_APB2LPENSR_USART1LPENS_Msk       /*!< USART1 enable  */
+#define RCC_APB2LPENSR_USART6LPENS_Pos          (5U)
+#define RCC_APB2LPENSR_USART6LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENSR_USART6LPENS              RCC_APB2LPENSR_USART6LPENS_Msk       /*!< USART6 enable  */
+#define RCC_APB2LPENSR_UART9LPENS_Pos           (6U)
+#define RCC_APB2LPENSR_UART9LPENS_Msk           (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENSR_UART9LPENS               RCC_APB2LPENSR_UART9LPENS_Msk        /*!< UART9 enable  */
+#define RCC_APB2LPENSR_USART10LPENS_Pos         (7U)
+#define RCC_APB2LPENSR_USART10LPENS_Msk         (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENSR_USART10LPENS             RCC_APB2LPENSR_USART10LPENS_Msk      /*!< USART10 enable  */
+#define RCC_APB2LPENSR_SPI1LPENS_Pos            (12U)
+#define RCC_APB2LPENSR_SPI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENSR_SPI1LPENS                RCC_APB2LPENSR_SPI1LPENS_Msk         /*!< SPI1 enable  */
+#define RCC_APB2LPENSR_SPI4LPENS_Pos            (13U)
+#define RCC_APB2LPENSR_SPI4LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENSR_SPI4LPENS                RCC_APB2LPENSR_SPI4LPENS_Msk         /*!< SPI4 enable  */
+#define RCC_APB2LPENSR_TIM18LPENS_Pos           (15U)
+#define RCC_APB2LPENSR_TIM18LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENSR_TIM18LPENS               RCC_APB2LPENSR_TIM18LPENS_Msk        /*!< TIM18 enable  */
+#define RCC_APB2LPENSR_TIM15LPENS_Pos           (16U)
+#define RCC_APB2LPENSR_TIM15LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENSR_TIM15LPENS               RCC_APB2LPENSR_TIM15LPENS_Msk        /*!< TIM15 enable  */
+#define RCC_APB2LPENSR_TIM16LPENS_Pos           (17U)
+#define RCC_APB2LPENSR_TIM16LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENSR_TIM16LPENS               RCC_APB2LPENSR_TIM16LPENS_Msk        /*!< TIM16 enable  */
+#define RCC_APB2LPENSR_TIM17LPENS_Pos           (18U)
+#define RCC_APB2LPENSR_TIM17LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENSR_TIM17LPENS               RCC_APB2LPENSR_TIM17LPENS_Msk        /*!< TIM17 enable  */
+#define RCC_APB2LPENSR_TIM9LPENS_Pos            (19U)
+#define RCC_APB2LPENSR_TIM9LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENSR_TIM9LPENS                RCC_APB2LPENSR_TIM9LPENS_Msk         /*!< TIM9 enable  */
+#define RCC_APB2LPENSR_SPI5LPENS_Pos            (20U)
+#define RCC_APB2LPENSR_SPI5LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENSR_SPI5LPENS                RCC_APB2LPENSR_SPI5LPENS_Msk         /*!< SPI5 enable  */
+#define RCC_APB2LPENSR_SAI1LPENS_Pos            (21U)
+#define RCC_APB2LPENSR_SAI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENSR_SAI1LPENS                RCC_APB2LPENSR_SAI1LPENS_Msk         /*!< SAI1 enable  */
+#define RCC_APB2LPENSR_SAI2LPENS_Pos            (22U)
+#define RCC_APB2LPENSR_SAI2LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENSR_SAI2LPENS                RCC_APB2LPENSR_SAI2LPENS_Msk         /*!< SAI2 enable  */
+
+/****************  Bit definition for RCC_APB3LPENSR register  ****************/
+#define RCC_APB3LPENSR_DFTLPENS_Pos             (2U)
+#define RCC_APB3LPENSR_DFTLPENS_Msk             (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENSR_DFTLPENS                 RCC_APB3LPENSR_DFTLPENS_Msk          /*!< DFT enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR1 register  ****************/
+#define RCC_APB4LPENSR1_HDPLPENS_Pos            (2U)
+#define RCC_APB4LPENSR1_HDPLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR1_HDPLPENS                RCC_APB4LPENSR1_HDPLPENS_Msk         /*!< HDP enable  */
+#define RCC_APB4LPENSR1_LPUART1LPENS_Pos        (3U)
+#define RCC_APB4LPENSR1_LPUART1LPENS_Msk        (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENSR1_LPUART1LPENS            RCC_APB4LPENSR1_LPUART1LPENS_Msk     /*!< LPUART1 enable  */
+#define RCC_APB4LPENSR1_SPI6LPENS_Pos           (5U)
+#define RCC_APB4LPENSR1_SPI6LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENSR1_SPI6LPENS               RCC_APB4LPENSR1_SPI6LPENS_Msk        /*!< SPI6 enable  */
+#define RCC_APB4LPENSR1_I2C4LPENS_Pos           (7U)
+#define RCC_APB4LPENSR1_I2C4LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENSR1_I2C4LPENS               RCC_APB4LPENSR1_I2C4LPENS_Msk        /*!< I2C4 enable  */
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos         (9U)
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENSR1_LPTIM2LPENS             RCC_APB4LPENSR1_LPTIM2LPENS_Msk      /*!< LPTIM2 enable  */
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos         (10U)
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENSR1_LPTIM3LPENS             RCC_APB4LPENSR1_LPTIM3LPENS_Msk      /*!< LPTIM3 enable  */
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos         (11U)
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENSR1_LPTIM4LPENS             RCC_APB4LPENSR1_LPTIM4LPENS_Msk      /*!< LPTIM4 enable  */
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos         (12U)
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENSR1_LPTIM5LPENS             RCC_APB4LPENSR1_LPTIM5LPENS_Msk      /*!< LPTIM5 enable  */
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos        (15U)
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk        (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENSR1_VREFBUFLPENS            RCC_APB4LPENSR1_VREFBUFLPENS_Msk     /*!< VREFBUF enable  */
+#define RCC_APB4LPENSR1_RTCLPENS_Pos            (16U)
+#define RCC_APB4LPENSR1_RTCLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENSR1_RTCLPENS                RCC_APB4LPENSR1_RTCLPENS_Msk         /*!< RTC enable  */
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos         (17U)
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk         (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENSR1_RTCAPBLPENS             RCC_APB4LPENSR1_RTCAPBLPENS_Msk      /*!< RTCAPB enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR2 register  ****************/
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos         (0U)
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk         (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENSR2_SYSCFGLPENS             RCC_APB4LPENSR2_SYSCFGLPENS_Msk      /*!< SYSCFG enable  */
+#define RCC_APB4LPENSR2_BSECLPENS_Pos           (1U)
+#define RCC_APB4LPENSR2_BSECLPENS_Msk           (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENSR2_BSECLPENS               RCC_APB4LPENSR2_BSECLPENS_Msk        /*!< BSEC enable  */
+#define RCC_APB4LPENSR2_DTSLPENS_Pos            (2U)
+#define RCC_APB4LPENSR2_DTSLPENS_Msk            (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR2_DTSLPENS                RCC_APB4LPENSR2_DTSLPENS_Msk         /*!< DTS enable  */
+
+/****************  Bit definition for RCC_APB5LPENSR register  ****************/
+#define RCC_APB5LPENSR_LTDCLPENS_Pos            (1U)
+#define RCC_APB5LPENSR_LTDCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENSR_LTDCLPENS                RCC_APB5LPENSR_LTDCLPENS_Msk         /*!< LTDC enable */
+#define RCC_APB5LPENSR_DCMIPPLPENS_Pos          (2U)
+#define RCC_APB5LPENSR_DCMIPPLPENS_Msk          (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENSR_DCMIPPLPENS              RCC_APB5LPENSR_DCMIPPLPENS_Msk       /*!< DCMIPP enable */
+#define RCC_APB5LPENSR_GFXTIMLPENS_Pos          (4U)
+#define RCC_APB5LPENSR_GFXTIMLPENS_Msk          (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENSR_GFXTIMLPENS              RCC_APB5LPENSR_GFXTIMLPENS_Msk       /*!< GFXTIM enable */
+#define RCC_APB5LPENSR_VENCLPENS_Pos            (5U)
+#define RCC_APB5LPENSR_VENCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENSR_VENCLPENS                RCC_APB5LPENSR_VENCLPENS_Msk         /*!< VENC enable */
+#define RCC_APB5LPENSR_CSILPENS_Pos             (6U)
+#define RCC_APB5LPENSR_CSILPENS_Msk             (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENSR_CSILPENS                 RCC_APB5LPENSR_CSILPENS_Msk          /*!< CSI enable */
+
+/****************  Bit definition for RCC_PRIVCFGSR0 register  ****************/
+#define RCC_PRIVCFGSR0_LSIPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR0_LSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR0_LSIPRIVS                 RCC_PRIVCFGSR0_LSIPRIVS_Msk          /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_LSEPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR0_LSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR0_LSEPRIVS                 RCC_PRIVCFGSR0_LSEPRIVS_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_MSIPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR0_MSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR0_MSIPRIVS                 RCC_PRIVCFGSR0_MSIPRIVS_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSIPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR0_HSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR0_HSIPRIVS                 RCC_PRIVCFGSR0_HSIPRIVS_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSEPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR0_HSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR0_HSEPRIVS                 RCC_PRIVCFGSR0_HSEPRIVS_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR0 register  *****************/
+#define RCC_PUBCFGSR0_LSIPUBS_Pos               (0U)
+#define RCC_PUBCFGSR0_LSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR0_LSIPUBS                   RCC_PUBCFGSR0_LSIPUBS_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_LSEPUBS_Pos               (1U)
+#define RCC_PUBCFGSR0_LSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR0_LSEPUBS                   RCC_PUBCFGSR0_LSEPUBS_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_MSIPUBS_Pos               (2U)
+#define RCC_PUBCFGSR0_MSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR0_MSIPUBS                   RCC_PUBCFGSR0_MSIPUBS_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSIPUBS_Pos               (3U)
+#define RCC_PUBCFGSR0_HSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR0_HSIPUBS                   RCC_PUBCFGSR0_HSIPUBS_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSEPUBS_Pos               (4U)
+#define RCC_PUBCFGSR0_HSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR0_HSEPUBS                   RCC_PUBCFGSR0_HSEPUBS_Msk            /*!< Public protection of he HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR1 register  ****************/
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos            (0U)
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGSR1_PLL1PRIVS                RCC_PRIVCFGSR1_PLL1PRIVS_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos            (1U)
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGSR1_PLL2PRIVS                RCC_PRIVCFGSR1_PLL2PRIVS_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR1_PLL3PRIVS                RCC_PRIVCFGSR1_PLL3PRIVS_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR1_PLL4PRIVS                RCC_PRIVCFGSR1_PLL4PRIVS_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR1 register  *****************/
+#define RCC_PUBCFGSR1_PLL1PUBS_Pos              (0U)
+#define RCC_PUBCFGSR1_PLL1PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGSR1_PLL1PUBS                  RCC_PUBCFGSR1_PLL1PUBS_Msk           /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL2PUBS_Pos              (1U)
+#define RCC_PUBCFGSR1_PLL2PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR1_PLL2PUBS                  RCC_PUBCFGSR1_PLL2PUBS_Msk           /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL3PUBS_Pos              (2U)
+#define RCC_PUBCFGSR1_PLL3PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR1_PLL3PUBS                  RCC_PUBCFGSR1_PLL3PUBS_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL4PUBS_Pos              (3U)
+#define RCC_PUBCFGSR1_PLL4PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR1_PLL4PUBS                  RCC_PUBCFGSR1_PLL4PUBS_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR2 register  ****************/
+#define RCC_PRIVCFGSR2_IC1PRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR2_IC1PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR2_IC1PRIVS                 RCC_PRIVCFGSR2_IC1PRIVS_Msk          /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC2PRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR2_IC2PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR2_IC2PRIVS                 RCC_PRIVCFGSR2_IC2PRIVS_Msk          /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC3PRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR2_IC3PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR2_IC3PRIVS                 RCC_PRIVCFGSR2_IC3PRIVS_Msk          /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC4PRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR2_IC4PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR2_IC4PRIVS                 RCC_PRIVCFGSR2_IC4PRIVS_Msk          /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC5PRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR2_IC5PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR2_IC5PRIVS                 RCC_PRIVCFGSR2_IC5PRIVS_Msk          /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC6PRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR2_IC6PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR2_IC6PRIVS                 RCC_PRIVCFGSR2_IC6PRIVS_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC7PRIVS_Pos             (6U)
+#define RCC_PRIVCFGSR2_IC7PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGSR2_IC7PRIVS                 RCC_PRIVCFGSR2_IC7PRIVS_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC8PRIVS_Pos             (7U)
+#define RCC_PRIVCFGSR2_IC8PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGSR2_IC8PRIVS                 RCC_PRIVCFGSR2_IC8PRIVS_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC9PRIVS_Pos             (8U)
+#define RCC_PRIVCFGSR2_IC9PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGSR2_IC9PRIVS                 RCC_PRIVCFGSR2_IC9PRIVS_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC10PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR2_IC10PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR2_IC10PRIVS                RCC_PRIVCFGSR2_IC10PRIVS_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC11PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR2_IC11PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR2_IC11PRIVS                RCC_PRIVCFGSR2_IC11PRIVS_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC12PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR2_IC12PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR2_IC12PRIVS                RCC_PRIVCFGSR2_IC12PRIVS_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC13PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR2_IC13PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR2_IC13PRIVS                RCC_PRIVCFGSR2_IC13PRIVS_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC14PRIVS_Pos            (13U)
+#define RCC_PRIVCFGSR2_IC14PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGSR2_IC14PRIVS                RCC_PRIVCFGSR2_IC14PRIVS_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC15PRIVS_Pos            (14U)
+#define RCC_PRIVCFGSR2_IC15PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGSR2_IC15PRIVS                RCC_PRIVCFGSR2_IC15PRIVS_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC16PRIVS_Pos            (15U)
+#define RCC_PRIVCFGSR2_IC16PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGSR2_IC16PRIVS                RCC_PRIVCFGSR2_IC16PRIVS_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC17PRIVS_Pos            (16U)
+#define RCC_PRIVCFGSR2_IC17PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGSR2_IC17PRIVS                RCC_PRIVCFGSR2_IC17PRIVS_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC18PRIVS_Pos            (17U)
+#define RCC_PRIVCFGSR2_IC18PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGSR2_IC18PRIVS                RCC_PRIVCFGSR2_IC18PRIVS_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC19PRIVS_Pos            (18U)
+#define RCC_PRIVCFGSR2_IC19PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGSR2_IC19PRIVS                RCC_PRIVCFGSR2_IC19PRIVS_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC20PRIVS_Pos            (19U)
+#define RCC_PRIVCFGSR2_IC20PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGSR2_IC20PRIVS                RCC_PRIVCFGSR2_IC20PRIVS_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR2 register  *****************/
+#define RCC_PUBCFGSR2_IC1PUBS_Pos               (0U)
+#define RCC_PUBCFGSR2_IC1PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR2_IC1PUBS                   RCC_PUBCFGSR2_IC1PUBS_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC2PUBS_Pos               (1U)
+#define RCC_PUBCFGSR2_IC2PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR2_IC2PUBS                   RCC_PUBCFGSR2_IC2PUBS_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC3PUBS_Pos               (2U)
+#define RCC_PUBCFGSR2_IC3PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR2_IC3PUBS                   RCC_PUBCFGSR2_IC3PUBS_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC4PUBS_Pos               (3U)
+#define RCC_PUBCFGSR2_IC4PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR2_IC4PUBS                   RCC_PUBCFGSR2_IC4PUBS_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC5PUBS_Pos               (4U)
+#define RCC_PUBCFGSR2_IC5PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR2_IC5PUBS                   RCC_PUBCFGSR2_IC5PUBS_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC6PUBS_Pos               (5U)
+#define RCC_PUBCFGSR2_IC6PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR2_IC6PUBS                   RCC_PUBCFGSR2_IC6PUBS_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC7PUBS_Pos               (6U)
+#define RCC_PUBCFGSR2_IC7PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR2_IC7PUBS                   RCC_PUBCFGSR2_IC7PUBS_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC8PUBS_Pos               (7U)
+#define RCC_PUBCFGSR2_IC8PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGSR2_IC8PUBS                   RCC_PUBCFGSR2_IC8PUBS_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC9PUBS_Pos               (8U)
+#define RCC_PUBCFGSR2_IC9PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGSR2_IC9PUBS                   RCC_PUBCFGSR2_IC9PUBS_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC10PUBS_Pos              (9U)
+#define RCC_PUBCFGSR2_IC10PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR2_IC10PUBS                  RCC_PUBCFGSR2_IC10PUBS_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC11PUBS_Pos              (10U)
+#define RCC_PUBCFGSR2_IC11PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR2_IC11PUBS                  RCC_PUBCFGSR2_IC11PUBS_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC12PUBS_Pos              (11U)
+#define RCC_PUBCFGSR2_IC12PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR2_IC12PUBS                  RCC_PUBCFGSR2_IC12PUBS_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC13PUBS_Pos              (12U)
+#define RCC_PUBCFGSR2_IC13PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR2_IC13PUBS                  RCC_PUBCFGSR2_IC13PUBS_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC14PUBS_Pos              (13U)
+#define RCC_PUBCFGSR2_IC14PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGSR2_IC14PUBS                  RCC_PUBCFGSR2_IC14PUBS_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC15PUBS_Pos              (14U)
+#define RCC_PUBCFGSR2_IC15PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGSR2_IC15PUBS                  RCC_PUBCFGSR2_IC15PUBS_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC16PUBS_Pos              (15U)
+#define RCC_PUBCFGSR2_IC16PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGSR2_IC16PUBS                  RCC_PUBCFGSR2_IC16PUBS_Msk           /*!< Public protection of th IC16 configuration bits (enable, ready, divider */
+#define RCC_PUBCFGSR2_IC17PUBS_Pos              (16U)
+#define RCC_PUBCFGSR2_IC17PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGSR2_IC17PUBS                  RCC_PUBCFGSR2_IC17PUBS_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC18PUBS_Pos              (17U)
+#define RCC_PUBCFGSR2_IC18PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGSR2_IC18PUBS                  RCC_PUBCFGSR2_IC18PUBS_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC19PUBS_Pos              (18U)
+#define RCC_PUBCFGSR2_IC19PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGSR2_IC19PUBS                  RCC_PUBCFGSR2_IC19PUBS_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC20PUBS_Pos              (19U)
+#define RCC_PUBCFGSR2_IC20PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGSR2_IC20PUBS                  RCC_PUBCFGSR2_IC20PUBS_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR3 register  ****************/
+#define RCC_PRIVCFGSR3_MODPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR3_MODPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR3_MODPRIVS                 RCC_PRIVCFGSR3_MODPRIVS_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_SYSPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR3_SYSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR3_SYSPRIVS                 RCC_PRIVCFGSR3_SYSPRIVS_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_BUSPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR3_BUSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR3_BUSPRIVS                 RCC_PRIVCFGSR3_BUSPRIVS_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_PERPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR3_PERPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR3_PERPRIVS                 RCC_PRIVCFGSR3_PERPRIVS_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_INTPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR3_INTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR3_INTPRIVS                 RCC_PRIVCFGSR3_INTPRIVS_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_RSTPRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR3_RSTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR3_RSTPRIVS                 RCC_PRIVCFGSR3_RSTPRIVS_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR3 register  *****************/
+#define RCC_PUBCFGSR3_MODPUBS_Pos               (0U)
+#define RCC_PUBCFGSR3_MODPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR3_MODPUBS                   RCC_PUBCFGSR3_MODPUBS_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_SYSPUBS_Pos               (1U)
+#define RCC_PUBCFGSR3_SYSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR3_SYSPUBS                   RCC_PUBCFGSR3_SYSPUBS_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_BUSPUBS_Pos               (2U)
+#define RCC_PUBCFGSR3_BUSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR3_BUSPUBS                   RCC_PUBCFGSR3_BUSPUBS_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_PERPUBS_Pos               (3U)
+#define RCC_PUBCFGSR3_PERPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR3_PERPUBS                   RCC_PUBCFGSR3_PERPUBS_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_INTPUBS_Pos               (4U)
+#define RCC_PUBCFGSR3_INTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR3_INTPUBS                   RCC_PUBCFGSR3_INTPUBS_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_RSTPUBS_Pos               (5U)
+#define RCC_PUBCFGSR3_RSTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR3_RSTPUBS                   RCC_PUBCFGSR3_RSTPUBS_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR4 register  ****************/
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos           (0U)
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk           (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGSR4_ACLKNPRIVS               RCC_PRIVCFGSR4_ACLKNPRIVS_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos          (1U)
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk          (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS              RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk       /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR4_AHBMPRIVS                RCC_PRIVCFGSR4_AHBMPRIVS_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR4_AHB1PRIVS                RCC_PRIVCFGSR4_AHB1PRIVS_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos            (4U)
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGSR4_AHB2PRIVS                RCC_PRIVCFGSR4_AHB2PRIVS_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos            (5U)
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGSR4_AHB3PRIVS                RCC_PRIVCFGSR4_AHB3PRIVS_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos            (6U)
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGSR4_AHB4PRIVS                RCC_PRIVCFGSR4_AHB4PRIVS_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos            (7U)
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGSR4_AHB5PRIVS                RCC_PRIVCFGSR4_AHB5PRIVS_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB1PRIVS_Pos            (8U)
+#define RCC_PRIVCFGSR4_APB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGSR4_APB1PRIVS                RCC_PRIVCFGSR4_APB1PRIVS_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB2PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR4_APB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR4_APB2PRIVS                RCC_PRIVCFGSR4_APB2PRIVS_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB3PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR4_APB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR4_APB3PRIVS                RCC_PRIVCFGSR4_APB3PRIVS_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB4PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR4_APB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR4_APB4PRIVS                RCC_PRIVCFGSR4_APB4PRIVS_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB5PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR4_APB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR4_APB5PRIVS                RCC_PRIVCFGSR4_APB5PRIVS_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_NOCPRIVS_Pos             (13U)
+#define RCC_PRIVCFGSR4_NOCPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGSR4_NOCPRIVS                 RCC_PRIVCFGSR4_NOCPRIVS_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR4 register  *****************/
+#define RCC_PUBCFGSR4_ACLKNPUBS_Pos             (0U)
+#define RCC_PUBCFGSR4_ACLKNPUBS_Msk             (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGSR4_ACLKNPUBS                 RCC_PUBCFGSR4_ACLKNPUBS_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos            (1U)
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk            (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR4_ACLKNCPUBS                RCC_PUBCFGSR4_ACLKNCPUBS_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHBMPUBS_Pos              (2U)
+#define RCC_PUBCFGSR4_AHBMPUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR4_AHBMPUBS                  RCC_PUBCFGSR4_AHBMPUBS_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB1PUBS_Pos              (3U)
+#define RCC_PUBCFGSR4_AHB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR4_AHB1PUBS                  RCC_PUBCFGSR4_AHB1PUBS_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB2PUBS_Pos              (4U)
+#define RCC_PUBCFGSR4_AHB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGSR4_AHB2PUBS                  RCC_PUBCFGSR4_AHB2PUBS_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB3PUBS_Pos              (5U)
+#define RCC_PUBCFGSR4_AHB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGSR4_AHB3PUBS                  RCC_PUBCFGSR4_AHB3PUBS_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB4PUBS_Pos              (6U)
+#define RCC_PUBCFGSR4_AHB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGSR4_AHB4PUBS                  RCC_PUBCFGSR4_AHB4PUBS_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB5PUBS_Pos              (7U)
+#define RCC_PUBCFGSR4_AHB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGSR4_AHB5PUBS                  RCC_PUBCFGSR4_AHB5PUBS_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB1PUBS_Pos              (8U)
+#define RCC_PUBCFGSR4_APB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGSR4_APB1PUBS                  RCC_PUBCFGSR4_APB1PUBS_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB2PUBS_Pos              (9U)
+#define RCC_PUBCFGSR4_APB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR4_APB2PUBS                  RCC_PUBCFGSR4_APB2PUBS_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB3PUBS_Pos              (10U)
+#define RCC_PUBCFGSR4_APB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR4_APB3PUBS                  RCC_PUBCFGSR4_APB3PUBS_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB4PUBS_Pos              (11U)
+#define RCC_PUBCFGSR4_APB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR4_APB4PUBS                  RCC_PUBCFGSR4_APB4PUBS_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB5PUBS_Pos              (12U)
+#define RCC_PUBCFGSR4_APB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR4_APB5PUBS                  RCC_PUBCFGSR4_APB5PUBS_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_NOCPUBS_Pos               (13U)
+#define RCC_PUBCFGSR4_NOCPUBS_Msk               (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGSR4_NOCPUBS                   RCC_PUBCFGSR4_NOCPUBS_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR5 register  *****************/
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos          (0U)
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGSR5_AXISRAM3PUBS              RCC_PUBCFGSR5_AXISRAM3PUBS_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos          (1U)
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS              RCC_PUBCFGSR5_AXISRAM4PUBS_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos          (2U)
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS              RCC_PUBCFGSR5_AXISRAM5PUBS_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos          (3U)
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS              RCC_PUBCFGSR5_AXISRAM6PUBS_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos          (4U)
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS              RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos          (5U)
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS              RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos           (6U)
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS               RCC_PUBCFGSR5_BKPSRAMPUBS_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos          (7U)
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS              RCC_PUBCFGSR5_AXISRAM1PUBS_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos          (8U)
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS              RCC_PUBCFGSR5_AXISRAM2PUBS_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos           (9U)
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS               RCC_PUBCFGSR5_FLEXRAMPUBS_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos       (10U)
+#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk       (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos)      /*!< 0x00000400 */
+#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS           RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk    /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos           (11U)
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGSR5_VENCRAMPUBS               RCC_PUBCFGSR5_VENCRAMPUBS_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+/*******************  Bit definition for RCC_CCR register  ********************/
+#define RCC_CCR_LSIONC_Pos                      (0U)
+#define RCC_CCR_LSIONC_Msk                      (0x1UL << RCC_CCR_LSIONC_Pos)         /*!< 0x00000001 */
+#define RCC_CCR_LSIONC                          RCC_CCR_LSIONC_Msk                   /*!< LSI oscillator enable */
+#define RCC_CCR_LSEONC_Pos                      (1U)
+#define RCC_CCR_LSEONC_Msk                      (0x1UL << RCC_CCR_LSEONC_Pos)         /*!< 0x00000002 */
+#define RCC_CCR_LSEONC                          RCC_CCR_LSEONC_Msk                   /*!< LSE oscillator enable */
+#define RCC_CCR_MSIONC_Pos                      (2U)
+#define RCC_CCR_MSIONC_Msk                      (0x1UL << RCC_CCR_MSIONC_Pos)         /*!< 0x00000004 */
+#define RCC_CCR_MSIONC                          RCC_CCR_MSIONC_Msk                   /*!< MSI oscillator enable */
+#define RCC_CCR_HSIONC_Pos                      (3U)
+#define RCC_CCR_HSIONC_Msk                      (0x1UL << RCC_CCR_HSIONC_Pos)         /*!< 0x00000008 */
+#define RCC_CCR_HSIONC                          RCC_CCR_HSIONC_Msk                   /*!< HSI oscillator enable */
+#define RCC_CCR_HSEONC_Pos                      (4U)
+#define RCC_CCR_HSEONC_Msk                      (0x1UL << RCC_CCR_HSEONC_Pos)         /*!< 0x00000010 */
+#define RCC_CCR_HSEONC                          RCC_CCR_HSEONC_Msk                   /*!< HSE oscillator enable */
+#define RCC_CCR_PLL1ONC_Pos                     (8U)
+#define RCC_CCR_PLL1ONC_Msk                     (0x1UL << RCC_CCR_PLL1ONC_Pos)        /*!< 0x00000100 */
+#define RCC_CCR_PLL1ONC                         RCC_CCR_PLL1ONC_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CCR_PLL2ONC_Pos                     (9U)
+#define RCC_CCR_PLL2ONC_Msk                     (0x1UL << RCC_CCR_PLL2ONC_Pos)        /*!< 0x00000200 */
+#define RCC_CCR_PLL2ONC                         RCC_CCR_PLL2ONC_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CCR_PLL3ONC_Pos                     (10U)
+#define RCC_CCR_PLL3ONC_Msk                     (0x1UL << RCC_CCR_PLL3ONC_Pos)        /*!< 0x00000400 */
+#define RCC_CCR_PLL3ONC                         RCC_CCR_PLL3ONC_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CCR_PLL4ONC_Pos                     (11U)
+#define RCC_CCR_PLL4ONC_Msk                     (0x1UL << RCC_CCR_PLL4ONC_Pos)        /*!< 0x00000800 */
+#define RCC_CCR_PLL4ONC                         RCC_CCR_PLL4ONC_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCCR register  ******************/
+#define RCC_STOPCCR_MSISTOPENC_Pos              (0U)
+#define RCC_STOPCCR_MSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */
+#define RCC_STOPCCR_MSISTOPENC                  RCC_STOPCCR_MSISTOPENC_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCCR_HSISTOPENC_Pos              (1U)
+#define RCC_STOPCCR_HSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */
+#define RCC_STOPCCR_HSISTOPENC                  RCC_STOPCCR_HSISTOPENC_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTCR register  *****************/
+#define RCC_MISCRSTCR_DBGRSTC_Pos               (0U)
+#define RCC_MISCRSTCR_DBGRSTC_Msk               (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTCR_DBGRSTC                   RCC_MISCRSTCR_DBGRSTC_Msk            /*!< DBG reset */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos          (4U)
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC              RCC_MISCRSTCR_XSPIPHY1RSTC_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos          (5U)
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC              RCC_MISCRSTCR_XSPIPHY2RSTC_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos         (7U)
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC             RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos         (8U)
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC             RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTCR register  *****************/
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos           (0U)
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTCR_AXISRAM3RSTC               RCC_MEMRSTCR_AXISRAM3RSTC_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos           (1U)
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTCR_AXISRAM4RSTC               RCC_MEMRSTCR_AXISRAM4RSTC_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos           (2U)
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTCR_AXISRAM5RSTC               RCC_MEMRSTCR_AXISRAM5RSTC_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos           (3U)
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTCR_AXISRAM6RSTC               RCC_MEMRSTCR_AXISRAM6RSTC_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos           (4U)
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC               RCC_MEMRSTCR_AHBSRAM1RSTC_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos           (5U)
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC               RCC_MEMRSTCR_AHBSRAM2RSTC_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos           (7U)
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTCR_AXISRAM1RSTC               RCC_MEMRSTCR_AXISRAM1RSTC_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos           (8U)
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTCR_AXISRAM2RSTC               RCC_MEMRSTCR_AXISRAM2RSTC_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos            (9U)
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTCR_FLEXRAMRSTC                RCC_MEMRSTCR_FLEXRAMRSTC_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos        (10U)
+#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk        (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos)     /*!< 0x00000400 */
+#define RCC_MEMRSTCR_CACHEAXIRAMRSTC            RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk     /*!< CACHEAXIRAM reset */
+#define RCC_MEMRSTCR_VENCRAMRSTC_Pos            (11U)
+#define RCC_MEMRSTCR_VENCRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTCR_VENCRAMRSTC                RCC_MEMRSTCR_VENCRAMRSTC_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTCR_BOOTROMRSTC_Pos            (12U)
+#define RCC_MEMRSTCR_BOOTROMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTCR_BOOTROMRSTC                RCC_MEMRSTCR_BOOTROMRSTC_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTCR register  *****************/
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos            (4U)
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk            (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTCR_GPDMA1RSTC                RCC_AHB1RSTCR_GPDMA1RSTC_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTCR_ADC12RSTC_Pos             (5U)
+#define RCC_AHB1RSTCR_ADC12RSTC_Msk             (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTCR_ADC12RSTC                 RCC_AHB1RSTCR_ADC12RSTC_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTCR register  *****************/
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos            (12U)
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk            (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTCR_RAMCFGRSTC                RCC_AHB2RSTCR_RAMCFGRSTC_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTCR_MDF1RSTC_Pos              (16U)
+#define RCC_AHB2RSTCR_MDF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTCR_MDF1RSTC                  RCC_AHB2RSTCR_MDF1RSTC_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTCR_ADF1RSTC_Pos              (17U)
+#define RCC_AHB2RSTCR_ADF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTCR_ADF1RSTC                  RCC_AHB2RSTCR_ADF1RSTC_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTCR register  *****************/
+#define RCC_AHB3RSTCR_RNGRSTC_Pos               (0U)
+#define RCC_AHB3RSTCR_RNGRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTCR_RNGRSTC                   RCC_AHB3RSTCR_RNGRSTC_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTCR_HASHRSTC_Pos              (1U)
+#define RCC_AHB3RSTCR_HASHRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTCR_HASHRSTC                  RCC_AHB3RSTCR_HASHRSTC_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTCR_PKARSTC_Pos               (8U)
+#define RCC_AHB3RSTCR_PKARSTC_Msk               (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTCR_PKARSTC                   RCC_AHB3RSTCR_PKARSTC_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTCR_IACRSTC_Pos               (10U)
+#define RCC_AHB3RSTCR_IACRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTCR_IACRSTC                   RCC_AHB3RSTCR_IACRSTC_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTCR register  *****************/
+#define RCC_AHB4RSTCR_GPIOARSTC_Pos             (0U)
+#define RCC_AHB4RSTCR_GPIOARSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTCR_GPIOARSTC                 RCC_AHB4RSTCR_GPIOARSTC_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTCR_GPIOBRSTC_Pos             (1U)
+#define RCC_AHB4RSTCR_GPIOBRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTCR_GPIOBRSTC                 RCC_AHB4RSTCR_GPIOBRSTC_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTCR_GPIOCRSTC_Pos             (2U)
+#define RCC_AHB4RSTCR_GPIOCRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTCR_GPIOCRSTC                 RCC_AHB4RSTCR_GPIOCRSTC_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTCR_GPIODRSTC_Pos             (3U)
+#define RCC_AHB4RSTCR_GPIODRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTCR_GPIODRSTC                 RCC_AHB4RSTCR_GPIODRSTC_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTCR_GPIOERSTC_Pos             (4U)
+#define RCC_AHB4RSTCR_GPIOERSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTCR_GPIOERSTC                 RCC_AHB4RSTCR_GPIOERSTC_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTCR_GPIOFRSTC_Pos             (5U)
+#define RCC_AHB4RSTCR_GPIOFRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTCR_GPIOFRSTC                 RCC_AHB4RSTCR_GPIOFRSTC_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTCR_GPIOGRSTC_Pos             (6U)
+#define RCC_AHB4RSTCR_GPIOGRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTCR_GPIOGRSTC                 RCC_AHB4RSTCR_GPIOGRSTC_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTCR_GPIOHRSTC_Pos             (7U)
+#define RCC_AHB4RSTCR_GPIOHRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTCR_GPIOHRSTC                 RCC_AHB4RSTCR_GPIOHRSTC_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTCR_GPIONRSTC_Pos             (13U)
+#define RCC_AHB4RSTCR_GPIONRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTCR_GPIONRSTC                 RCC_AHB4RSTCR_GPIONRSTC_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTCR_GPIOORSTC_Pos             (14U)
+#define RCC_AHB4RSTCR_GPIOORSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTCR_GPIOORSTC                 RCC_AHB4RSTCR_GPIOORSTC_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTCR_GPIOPRSTC_Pos             (15U)
+#define RCC_AHB4RSTCR_GPIOPRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTCR_GPIOPRSTC                 RCC_AHB4RSTCR_GPIOPRSTC_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTCR_GPIOQRSTC_Pos             (16U)
+#define RCC_AHB4RSTCR_GPIOQRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTCR_GPIOQRSTC                 RCC_AHB4RSTCR_GPIOQRSTC_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTCR_PWRRSTC_Pos               (18U)
+#define RCC_AHB4RSTCR_PWRRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTCR_PWRRSTC                   RCC_AHB4RSTCR_PWRRSTC_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTCR_CRCRSTC_Pos               (19U)
+#define RCC_AHB4RSTCR_CRCRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTCR_CRCRSTC                   RCC_AHB4RSTCR_CRCRSTC_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTCR register  *****************/
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos            (0U)
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTCR_HPDMA1RSTC                RCC_AHB5RSTCR_HPDMA1RSTC_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTCR_DMA2DRSTC_Pos             (1U)
+#define RCC_AHB5RSTCR_DMA2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTCR_DMA2DRSTC                 RCC_AHB5RSTCR_DMA2DRSTC_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTCR_JPEGRSTC_Pos              (3U)
+#define RCC_AHB5RSTCR_JPEGRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTCR_JPEGRSTC                  RCC_AHB5RSTCR_JPEGRSTC_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTCR_FMCRSTC_Pos               (4U)
+#define RCC_AHB5RSTCR_FMCRSTC_Msk               (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTCR_FMCRSTC                   RCC_AHB5RSTCR_FMCRSTC_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTCR_XSPI1RSTC_Pos             (5U)
+#define RCC_AHB5RSTCR_XSPI1RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTCR_XSPI1RSTC                 RCC_AHB5RSTCR_XSPI1RSTC_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTCR_PSSIRSTC_Pos              (6U)
+#define RCC_AHB5RSTCR_PSSIRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTCR_PSSIRSTC                  RCC_AHB5RSTCR_PSSIRSTC_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos            (7U)
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTCR_SDMMC2RSTC                RCC_AHB5RSTCR_SDMMC2RSTC_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos            (8U)
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTCR_SDMMC1RSTC                RCC_AHB5RSTCR_SDMMC1RSTC_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTCR_XSPI2RSTC_Pos             (12U)
+#define RCC_AHB5RSTCR_XSPI2RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTCR_XSPI2RSTC                 RCC_AHB5RSTCR_XSPI2RSTC_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTCR_XSPIMRSTC_Pos             (13U)
+#define RCC_AHB5RSTCR_XSPIMRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTCR_XSPIMRSTC                 RCC_AHB5RSTCR_XSPIMRSTC_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTCR_XSPI3RSTC_Pos             (17U)
+#define RCC_AHB5RSTCR_XSPI3RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTCR_XSPI3RSTC                 RCC_AHB5RSTCR_XSPI3RSTC_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTCR_GFXMMURSTC_Pos            (19U)
+#define RCC_AHB5RSTCR_GFXMMURSTC_Msk            (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTCR_GFXMMURSTC                RCC_AHB5RSTCR_GFXMMURSTC_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTCR_GPU2DRSTC_Pos             (20U)
+#define RCC_AHB5RSTCR_GPU2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTCR_GPU2DRSTC                 RCC_AHB5RSTCR_GPU2DRSTC_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos        (23U)
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC            RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos        (24U)
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC            RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTCR_ETH1RSTC_Pos              (25U)
+#define RCC_AHB5RSTCR_ETH1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTCR_ETH1RSTC                  RCC_AHB5RSTCR_ETH1RSTC_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTCR_OTG1RSTC_Pos              (26U)
+#define RCC_AHB5RSTCR_OTG1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTCR_OTG1RSTC                  RCC_AHB5RSTCR_OTG1RSTC_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos           (27U)
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC               RCC_AHB5RSTCR_OTGPHY1RSTC_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos           (28U)
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC               RCC_AHB5RSTCR_OTGPHY2RSTC_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTCR_OTG2RSTC_Pos              (29U)
+#define RCC_AHB5RSTCR_OTG2RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTCR_OTG2RSTC                  RCC_AHB5RSTCR_OTG2RSTC_Msk           /*!< OTG2 reset */
+#define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos          (30U)
+#define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk          (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos)   /*!< 0x40000000 */
+#define RCC_AHB5RSTCR_CACHEAXIRSTC              RCC_AHB5RSTCR_CACHEAXIRSTC_Msk       /*!< CACHEAXI reset */
+#define RCC_AHB5RSTCR_NPURSTC_Pos               (31U)
+#define RCC_AHB5RSTCR_NPURSTC_Msk               (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos)  /*!< 0x80000000 */
+#define RCC_AHB5RSTCR_NPURSTC                   RCC_AHB5RSTCR_NPURSTC_Msk            /*!< NPU reset */
+
+/****************  Bit definition for RCC_APB1RSTCR1 register  ****************/
+#define RCC_APB1RSTCR1_TIM2RSTC_Pos             (0U)
+#define RCC_APB1RSTCR1_TIM2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTCR1_TIM2RSTC                 RCC_APB1RSTCR1_TIM2RSTC_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTCR1_TIM3RSTC_Pos             (1U)
+#define RCC_APB1RSTCR1_TIM3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTCR1_TIM3RSTC                 RCC_APB1RSTCR1_TIM3RSTC_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTCR1_TIM4RSTC_Pos             (2U)
+#define RCC_APB1RSTCR1_TIM4RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTCR1_TIM4RSTC                 RCC_APB1RSTCR1_TIM4RSTC_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTCR1_TIM5RSTC_Pos             (3U)
+#define RCC_APB1RSTCR1_TIM5RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTCR1_TIM5RSTC                 RCC_APB1RSTCR1_TIM5RSTC_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTCR1_TIM6RSTC_Pos             (4U)
+#define RCC_APB1RSTCR1_TIM6RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTCR1_TIM6RSTC                 RCC_APB1RSTCR1_TIM6RSTC_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTCR1_TIM7RSTC_Pos             (5U)
+#define RCC_APB1RSTCR1_TIM7RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTCR1_TIM7RSTC                 RCC_APB1RSTCR1_TIM7RSTC_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTCR1_TIM12RSTC_Pos            (6U)
+#define RCC_APB1RSTCR1_TIM12RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTCR1_TIM12RSTC                RCC_APB1RSTCR1_TIM12RSTC_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTCR1_TIM13RSTC_Pos            (7U)
+#define RCC_APB1RSTCR1_TIM13RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTCR1_TIM13RSTC                RCC_APB1RSTCR1_TIM13RSTC_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTCR1_TIM14RSTC_Pos            (8U)
+#define RCC_APB1RSTCR1_TIM14RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR1_TIM14RSTC                RCC_APB1RSTCR1_TIM14RSTC_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos           (9U)
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTCR1_LPTIM1RSTC               RCC_APB1RSTCR1_LPTIM1RSTC_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTCR1_WWDGRSTC_Pos             (11U)
+#define RCC_APB1RSTCR1_WWDGRSTC_Msk             (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTCR1_WWDGRSTC                 RCC_APB1RSTCR1_WWDGRSTC_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTCR1_TIM10RSTC_Pos            (12U)
+#define RCC_APB1RSTCR1_TIM10RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTCR1_TIM10RSTC                RCC_APB1RSTCR1_TIM10RSTC_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTCR1_TIM11RSTC_Pos            (13U)
+#define RCC_APB1RSTCR1_TIM11RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTCR1_TIM11RSTC                RCC_APB1RSTCR1_TIM11RSTC_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTCR1_SPI2RSTC_Pos             (14U)
+#define RCC_APB1RSTCR1_SPI2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTCR1_SPI2RSTC                 RCC_APB1RSTCR1_SPI2RSTC_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTCR1_SPI3RSTC_Pos             (15U)
+#define RCC_APB1RSTCR1_SPI3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTCR1_SPI3RSTC                 RCC_APB1RSTCR1_SPI3RSTC_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos         (16U)
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk         (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC             RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTCR1_USART2RSTC_Pos           (17U)
+#define RCC_APB1RSTCR1_USART2RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTCR1_USART2RSTC               RCC_APB1RSTCR1_USART2RSTC_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTCR1_USART3RSTC_Pos           (18U)
+#define RCC_APB1RSTCR1_USART3RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTCR1_USART3RSTC               RCC_APB1RSTCR1_USART3RSTC_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTCR1_UART4RSTC_Pos            (19U)
+#define RCC_APB1RSTCR1_UART4RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTCR1_UART4RSTC                RCC_APB1RSTCR1_UART4RSTC_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTCR1_UART5RSTC_Pos            (20U)
+#define RCC_APB1RSTCR1_UART5RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTCR1_UART5RSTC                RCC_APB1RSTCR1_UART5RSTC_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTCR1_I2C1RSTC_Pos             (21U)
+#define RCC_APB1RSTCR1_I2C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTCR1_I2C1RSTC                 RCC_APB1RSTCR1_I2C1RSTC_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTCR1_I2C2RSTC_Pos             (22U)
+#define RCC_APB1RSTCR1_I2C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTCR1_I2C2RSTC                 RCC_APB1RSTCR1_I2C2RSTC_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTCR1_I2C3RSTC_Pos             (23U)
+#define RCC_APB1RSTCR1_I2C3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTCR1_I2C3RSTC                 RCC_APB1RSTCR1_I2C3RSTC_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTCR1_I3C1RSTC_Pos             (24U)
+#define RCC_APB1RSTCR1_I3C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTCR1_I3C1RSTC                 RCC_APB1RSTCR1_I3C1RSTC_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTCR1_I3C2RSTC_Pos             (25U)
+#define RCC_APB1RSTCR1_I3C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTCR1_I3C2RSTC                 RCC_APB1RSTCR1_I3C2RSTC_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTCR1_UART7RSTC_Pos            (30U)
+#define RCC_APB1RSTCR1_UART7RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTCR1_UART7RSTC                RCC_APB1RSTCR1_UART7RSTC_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTCR1_UART8RSTC_Pos            (31U)
+#define RCC_APB1RSTCR1_UART8RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTCR1_UART8RSTC                RCC_APB1RSTCR1_UART8RSTC_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTCR2 register  ****************/
+#define RCC_APB1RSTCR2_MDIOSRSTC_Pos            (5U)
+#define RCC_APB1RSTCR2_MDIOSRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTCR2_MDIOSRSTC                RCC_APB1RSTCR2_MDIOSRSTC_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTCR2_FDCANRSTC_Pos            (8U)
+#define RCC_APB1RSTCR2_FDCANRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR2_FDCANRSTC                RCC_APB1RSTCR2_FDCANRSTC_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTCR2_UCPD1RSTC_Pos            (18U)
+#define RCC_APB1RSTCR2_UCPD1RSTC_Msk            (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTCR2_UCPD1RSTC                RCC_APB1RSTCR2_UCPD1RSTC_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTCR register  *****************/
+#define RCC_APB2RSTCR_TIM1RSTC_Pos              (0U)
+#define RCC_APB2RSTCR_TIM1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTCR_TIM1RSTC                  RCC_APB2RSTCR_TIM1RSTC_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTCR_TIM8RSTC_Pos              (1U)
+#define RCC_APB2RSTCR_TIM8RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTCR_TIM8RSTC                  RCC_APB2RSTCR_TIM8RSTC_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTCR_USART1RSTC_Pos            (4U)
+#define RCC_APB2RSTCR_USART1RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTCR_USART1RSTC                RCC_APB2RSTCR_USART1RSTC_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTCR_USART6RSTC_Pos            (5U)
+#define RCC_APB2RSTCR_USART6RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTCR_USART6RSTC                RCC_APB2RSTCR_USART6RSTC_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTCR_UART9RSTC_Pos             (6U)
+#define RCC_APB2RSTCR_UART9RSTC_Msk             (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTCR_UART9RSTC                 RCC_APB2RSTCR_UART9RSTC_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTCR_USART10RSTC_Pos           (7U)
+#define RCC_APB2RSTCR_USART10RSTC_Msk           (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTCR_USART10RSTC               RCC_APB2RSTCR_USART10RSTC_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTCR_SPI1RSTC_Pos              (12U)
+#define RCC_APB2RSTCR_SPI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTCR_SPI1RSTC                  RCC_APB2RSTCR_SPI1RSTC_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTCR_SPI4RSTC_Pos              (13U)
+#define RCC_APB2RSTCR_SPI4RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTCR_SPI4RSTC                  RCC_APB2RSTCR_SPI4RSTC_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTCR_TIM18RSTC_Pos             (15U)
+#define RCC_APB2RSTCR_TIM18RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTCR_TIM18RSTC                 RCC_APB2RSTCR_TIM18RSTC_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTCR_TIM15RSTC_Pos             (16U)
+#define RCC_APB2RSTCR_TIM15RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTCR_TIM15RSTC                 RCC_APB2RSTCR_TIM15RSTC_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTCR_TIM16RSTC_Pos             (17U)
+#define RCC_APB2RSTCR_TIM16RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTCR_TIM16RSTC                 RCC_APB2RSTCR_TIM16RSTC_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTCR_TIM17RSTC_Pos             (18U)
+#define RCC_APB2RSTCR_TIM17RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTCR_TIM17RSTC                 RCC_APB2RSTCR_TIM17RSTC_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTCR_TIM9RSTC_Pos              (19U)
+#define RCC_APB2RSTCR_TIM9RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTCR_TIM9RSTC                  RCC_APB2RSTCR_TIM9RSTC_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTCR_SPI5RSTC_Pos              (20U)
+#define RCC_APB2RSTCR_SPI5RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTCR_SPI5RSTC                  RCC_APB2RSTCR_SPI5RSTC_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTCR_SAI1RSTC_Pos              (21U)
+#define RCC_APB2RSTCR_SAI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTCR_SAI1RSTC                  RCC_APB2RSTCR_SAI1RSTC_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTCR_SAI2RSTC_Pos              (22U)
+#define RCC_APB2RSTCR_SAI2RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTCR_SAI2RSTC                  RCC_APB2RSTCR_SAI2RSTC_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTCR1 register  ****************/
+#define RCC_APB4RSTCR1_HDPRSTC_Pos              (2U)
+#define RCC_APB4RSTCR1_HDPRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR1_HDPRSTC                  RCC_APB4RSTCR1_HDPRSTC_Msk           /*!< HDP reset */
+#define RCC_APB4RSTCR1_LPUART1RSTC_Pos          (3U)
+#define RCC_APB4RSTCR1_LPUART1RSTC_Msk          (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTCR1_LPUART1RSTC              RCC_APB4RSTCR1_LPUART1RSTC_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTCR1_SPI6RSTC_Pos             (5U)
+#define RCC_APB4RSTCR1_SPI6RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTCR1_SPI6RSTC                 RCC_APB4RSTCR1_SPI6RSTC_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTCR1_I2C4RSTC_Pos             (7U)
+#define RCC_APB4RSTCR1_I2C4RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTCR1_I2C4RSTC                 RCC_APB4RSTCR1_I2C4RSTC_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos           (9U)
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTCR1_LPTIM2RSTC               RCC_APB4RSTCR1_LPTIM2RSTC_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos           (10U)
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTCR1_LPTIM3RSTC               RCC_APB4RSTCR1_LPTIM3RSTC_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos           (11U)
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTCR1_LPTIM4RSTC               RCC_APB4RSTCR1_LPTIM4RSTC_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos           (12U)
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTCR1_LPTIM5RSTC               RCC_APB4RSTCR1_LPTIM5RSTC_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos          (15U)
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk          (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTCR1_VREFBUFRSTC              RCC_APB4RSTCR1_VREFBUFRSTC_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTCR1_RTCRSTC_Pos              (16U)
+#define RCC_APB4RSTCR1_RTCRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTCR1_RTCRSTC                  RCC_APB4RSTCR1_RTCRSTC_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTCR2 register  ****************/
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos           (0U)
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk           (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTCR2_SYSCFGRSTC               RCC_APB4RSTCR2_SYSCFGRSTC_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTCR2_DTSRSTC_Pos              (2U)
+#define RCC_APB4RSTCR2_DTSRSTC_Msk              (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR2_DTSRSTC                  RCC_APB4RSTCR2_DTSRSTC_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTCR register  *****************/
+#define RCC_APB5RSTCR_LTDCRSTC_Pos              (1U)
+#define RCC_APB5RSTCR_LTDCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTCR_LTDCRSTC                  RCC_APB5RSTCR_LTDCRSTC_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTCR_DCMIPPRSTC_Pos            (2U)
+#define RCC_APB5RSTCR_DCMIPPRSTC_Msk            (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTCR_DCMIPPRSTC                RCC_APB5RSTCR_DCMIPPRSTC_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTCR_GFXTIMRSTC_Pos            (4U)
+#define RCC_APB5RSTCR_GFXTIMRSTC_Msk            (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTCR_GFXTIMRSTC                RCC_APB5RSTCR_GFXTIMRSTC_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTCR_VENCRSTC_Pos              (5U)
+#define RCC_APB5RSTCR_VENCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTCR_VENCRSTC                  RCC_APB5RSTCR_VENCRSTC_Msk           /*!< VENC reset */
+#define RCC_APB5RSTCR_CSIRSTC_Pos               (6U)
+#define RCC_APB5RSTCR_CSIRSTC_Msk               (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTCR_CSIRSTC                   RCC_APB5RSTCR_CSIRSTC_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENCR register  ******************/
+#define RCC_DIVENCR_IC1ENC_Pos                  (0U)
+#define RCC_DIVENCR_IC1ENC_Msk                  (0x1UL << RCC_DIVENCR_IC1ENC_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENCR_IC1ENC                      RCC_DIVENCR_IC1ENC_Msk               /*!< IC1 enable */
+#define RCC_DIVENCR_IC2ENC_Pos                  (1U)
+#define RCC_DIVENCR_IC2ENC_Msk                  (0x1UL << RCC_DIVENCR_IC2ENC_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENCR_IC2ENC                      RCC_DIVENCR_IC2ENC_Msk               /*!< IC2 enable */
+#define RCC_DIVENCR_IC3ENC_Pos                  (2U)
+#define RCC_DIVENCR_IC3ENC_Msk                  (0x1UL << RCC_DIVENCR_IC3ENC_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENCR_IC3ENC                      RCC_DIVENCR_IC3ENC_Msk               /*!< IC3 enable */
+#define RCC_DIVENCR_IC4ENC_Pos                  (3U)
+#define RCC_DIVENCR_IC4ENC_Msk                  (0x1UL << RCC_DIVENCR_IC4ENC_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENCR_IC4ENC                      RCC_DIVENCR_IC4ENC_Msk               /*!< IC4 enable */
+#define RCC_DIVENCR_IC5ENC_Pos                  (4U)
+#define RCC_DIVENCR_IC5ENC_Msk                  (0x1UL << RCC_DIVENCR_IC5ENC_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENCR_IC5ENC                      RCC_DIVENCR_IC5ENC_Msk               /*!< IC5 enable */
+#define RCC_DIVENCR_IC6ENC_Pos                  (5U)
+#define RCC_DIVENCR_IC6ENC_Msk                  (0x1UL << RCC_DIVENCR_IC6ENC_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENCR_IC6ENC                      RCC_DIVENCR_IC6ENC_Msk               /*!< IC6 enable */
+#define RCC_DIVENCR_IC7ENC_Pos                  (6U)
+#define RCC_DIVENCR_IC7ENC_Msk                  (0x1UL << RCC_DIVENCR_IC7ENC_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENCR_IC7ENC                      RCC_DIVENCR_IC7ENC_Msk               /*!< IC7 enable */
+#define RCC_DIVENCR_IC8ENC_Pos                  (7U)
+#define RCC_DIVENCR_IC8ENC_Msk                  (0x1UL << RCC_DIVENCR_IC8ENC_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENCR_IC8ENC                      RCC_DIVENCR_IC8ENC_Msk               /*!< IC8 enable */
+#define RCC_DIVENCR_IC9ENC_Pos                  (8U)
+#define RCC_DIVENCR_IC9ENC_Msk                  (0x1UL << RCC_DIVENCR_IC9ENC_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENCR_IC9ENC                      RCC_DIVENCR_IC9ENC_Msk               /*!< IC9 enable */
+#define RCC_DIVENCR_IC10ENC_Pos                 (9U)
+#define RCC_DIVENCR_IC10ENC_Msk                 (0x1UL << RCC_DIVENCR_IC10ENC_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENCR_IC10ENC                     RCC_DIVENCR_IC10ENC_Msk              /*!< IC10 enable */
+#define RCC_DIVENCR_IC11ENC_Pos                 (10U)
+#define RCC_DIVENCR_IC11ENC_Msk                 (0x1UL << RCC_DIVENCR_IC11ENC_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENCR_IC11ENC                     RCC_DIVENCR_IC11ENC_Msk              /*!< IC11 enable */
+#define RCC_DIVENCR_IC12ENC_Pos                 (11U)
+#define RCC_DIVENCR_IC12ENC_Msk                 (0x1UL << RCC_DIVENCR_IC12ENC_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENCR_IC12ENC                     RCC_DIVENCR_IC12ENC_Msk              /*!< IC12 enable */
+#define RCC_DIVENCR_IC13ENC_Pos                 (12U)
+#define RCC_DIVENCR_IC13ENC_Msk                 (0x1UL << RCC_DIVENCR_IC13ENC_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENCR_IC13ENC                     RCC_DIVENCR_IC13ENC_Msk              /*!< IC13 enable */
+#define RCC_DIVENCR_IC14ENC_Pos                 (13U)
+#define RCC_DIVENCR_IC14ENC_Msk                 (0x1UL << RCC_DIVENCR_IC14ENC_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENCR_IC14ENC                     RCC_DIVENCR_IC14ENC_Msk              /*!< IC14 enable */
+#define RCC_DIVENCR_IC15ENC_Pos                 (14U)
+#define RCC_DIVENCR_IC15ENC_Msk                 (0x1UL << RCC_DIVENCR_IC15ENC_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENCR_IC15ENC                     RCC_DIVENCR_IC15ENC_Msk              /*!< IC15 enable */
+#define RCC_DIVENCR_IC16ENC_Pos                 (15U)
+#define RCC_DIVENCR_IC16ENC_Msk                 (0x1UL << RCC_DIVENCR_IC16ENC_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENCR_IC16ENC                     RCC_DIVENCR_IC16ENC_Msk              /*!< IC16 enable */
+#define RCC_DIVENCR_IC17ENC_Pos                 (16U)
+#define RCC_DIVENCR_IC17ENC_Msk                 (0x1UL << RCC_DIVENCR_IC17ENC_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENCR_IC17ENC                     RCC_DIVENCR_IC17ENC_Msk              /*!< IC17 enable */
+#define RCC_DIVENCR_IC18ENC_Pos                 (17U)
+#define RCC_DIVENCR_IC18ENC_Msk                 (0x1UL << RCC_DIVENCR_IC18ENC_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENCR_IC18ENC                     RCC_DIVENCR_IC18ENC_Msk              /*!< IC18 enable */
+#define RCC_DIVENCR_IC19ENC_Pos                 (18U)
+#define RCC_DIVENCR_IC19ENC_Msk                 (0x1UL << RCC_DIVENCR_IC19ENC_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENCR_IC19ENC                     RCC_DIVENCR_IC19ENC_Msk              /*!< IC19 enable */
+#define RCC_DIVENCR_IC20ENC_Pos                 (19U)
+#define RCC_DIVENCR_IC20ENC_Msk                 (0x1UL << RCC_DIVENCR_IC20ENC_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENCR_IC20ENC                     RCC_DIVENCR_IC20ENC_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENCR register  ******************/
+#define RCC_BUSENCR_ACLKNENC_Pos                (0U)
+#define RCC_BUSENCR_ACLKNENC_Msk                (0x1UL << RCC_BUSENCR_ACLKNENC_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENCR_ACLKNENC                    RCC_BUSENCR_ACLKNENC_Msk             /*!< ACLKN enable */
+#define RCC_BUSENCR_ACLKNCENC_Pos               (1U)
+#define RCC_BUSENCR_ACLKNCENC_Msk               (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENCR_ACLKNCENC                   RCC_BUSENCR_ACLKNCENC_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENCR_AHBMENC_Pos                 (2U)
+#define RCC_BUSENCR_AHBMENC_Msk                 (0x1UL << RCC_BUSENCR_AHBMENC_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENCR_AHBMENC                     RCC_BUSENCR_AHBMENC_Msk              /*!< AHBM enable */
+#define RCC_BUSENCR_AHB1ENC_Pos                 (3U)
+#define RCC_BUSENCR_AHB1ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB1ENC_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENCR_AHB1ENC                     RCC_BUSENCR_AHB1ENC_Msk              /*!< AHB1 enable */
+#define RCC_BUSENCR_AHB2ENC_Pos                 (4U)
+#define RCC_BUSENCR_AHB2ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB2ENC_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENCR_AHB2ENC                     RCC_BUSENCR_AHB2ENC_Msk              /*!< AHB2 enable */
+#define RCC_BUSENCR_AHB3ENC_Pos                 (5U)
+#define RCC_BUSENCR_AHB3ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB3ENC_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENCR_AHB3ENC                     RCC_BUSENCR_AHB3ENC_Msk              /*!< AHB3 enable */
+#define RCC_BUSENCR_AHB4ENC_Pos                 (6U)
+#define RCC_BUSENCR_AHB4ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB4ENC_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENCR_AHB4ENC                     RCC_BUSENCR_AHB4ENC_Msk              /*!< AHB4 enable */
+#define RCC_BUSENCR_AHB5ENC_Pos                 (7U)
+#define RCC_BUSENCR_AHB5ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB5ENC_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENCR_AHB5ENC                     RCC_BUSENCR_AHB5ENC_Msk              /*!< AHB5 enable */
+#define RCC_BUSENCR_APB1ENC_Pos                 (8U)
+#define RCC_BUSENCR_APB1ENC_Msk                 (0x1UL << RCC_BUSENCR_APB1ENC_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENCR_APB1ENC                     RCC_BUSENCR_APB1ENC_Msk              /*!< APB1 enable */
+#define RCC_BUSENCR_APB2ENC_Pos                 (9U)
+#define RCC_BUSENCR_APB2ENC_Msk                 (0x1UL << RCC_BUSENCR_APB2ENC_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENCR_APB2ENC                     RCC_BUSENCR_APB2ENC_Msk              /*!< APB2 enable */
+#define RCC_BUSENCR_APB3ENC_Pos                 (10U)
+#define RCC_BUSENCR_APB3ENC_Msk                 (0x1UL << RCC_BUSENCR_APB3ENC_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENCR_APB3ENC                     RCC_BUSENCR_APB3ENC_Msk              /*!< APB3 enable */
+#define RCC_BUSENCR_APB4ENC_Pos                 (11U)
+#define RCC_BUSENCR_APB4ENC_Msk                 (0x1UL << RCC_BUSENCR_APB4ENC_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENCR_APB4ENC                     RCC_BUSENCR_APB4ENC_Msk              /*!< APB4 enable */
+#define RCC_BUSENCR_APB5ENC_Pos                 (12U)
+#define RCC_BUSENCR_APB5ENC_Msk                 (0x1UL << RCC_BUSENCR_APB5ENC_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENCR_APB5ENC                     RCC_BUSENCR_APB5ENC_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENCR register  *****************/
+#define RCC_MISCENCR_DBGENC_Pos                 (0U)
+#define RCC_MISCENCR_DBGENC_Msk                 (0x1UL << RCC_MISCENCR_DBGENC_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENCR_DBGENC                     RCC_MISCENCR_DBGENC_Msk              /*!< DBG enable */
+#define RCC_MISCENCR_MCO1ENC_Pos                (1U)
+#define RCC_MISCENCR_MCO1ENC_Msk                (0x1UL << RCC_MISCENCR_MCO1ENC_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENCR_MCO1ENC                    RCC_MISCENCR_MCO1ENC_Msk             /*!< MCO1 enable */
+#define RCC_MISCENCR_MCO2ENC_Pos                (2U)
+#define RCC_MISCENCR_MCO2ENC_Msk                (0x1UL << RCC_MISCENCR_MCO2ENC_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENCR_MCO2ENC                    RCC_MISCENCR_MCO2ENC_Msk             /*!< MCO2 enable */
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos         (3U)
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk         (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENCR_XSPIPHYCOMPENC             RCC_MISCENCR_XSPIPHYCOMPENC_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENCR_PERENC_Pos                 (6U)
+#define RCC_MISCENCR_PERENC_Msk                 (0x1UL << RCC_MISCENCR_PERENC_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENCR_PERENC                     RCC_MISCENCR_PERENC_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENCR register  ******************/
+#define RCC_MEMENCR_AXISRAM3ENC_Pos             (0U)
+#define RCC_MEMENCR_AXISRAM3ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */
+#define RCC_MEMENCR_AXISRAM3ENC                 RCC_MEMENCR_AXISRAM3ENC_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENCR_AXISRAM4ENC_Pos             (1U)
+#define RCC_MEMENCR_AXISRAM4ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */
+#define RCC_MEMENCR_AXISRAM4ENC                 RCC_MEMENCR_AXISRAM4ENC_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENCR_AXISRAM5ENC_Pos             (2U)
+#define RCC_MEMENCR_AXISRAM5ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */
+#define RCC_MEMENCR_AXISRAM5ENC                 RCC_MEMENCR_AXISRAM5ENC_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENCR_AXISRAM6ENC_Pos             (3U)
+#define RCC_MEMENCR_AXISRAM6ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */
+#define RCC_MEMENCR_AXISRAM6ENC                 RCC_MEMENCR_AXISRAM6ENC_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENCR_AHBSRAM1ENC_Pos             (4U)
+#define RCC_MEMENCR_AHBSRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */
+#define RCC_MEMENCR_AHBSRAM1ENC                 RCC_MEMENCR_AHBSRAM1ENC_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENCR_AHBSRAM2ENC_Pos             (5U)
+#define RCC_MEMENCR_AHBSRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */
+#define RCC_MEMENCR_AHBSRAM2ENC                 RCC_MEMENCR_AHBSRAM2ENC_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENCR_BKPSRAMENC_Pos              (6U)
+#define RCC_MEMENCR_BKPSRAMENC_Msk              (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */
+#define RCC_MEMENCR_BKPSRAMENC                  RCC_MEMENCR_BKPSRAMENC_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENCR_AXISRAM1ENC_Pos             (7U)
+#define RCC_MEMENCR_AXISRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */
+#define RCC_MEMENCR_AXISRAM1ENC                 RCC_MEMENCR_AXISRAM1ENC_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENCR_AXISRAM2ENC_Pos             (8U)
+#define RCC_MEMENCR_AXISRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */
+#define RCC_MEMENCR_AXISRAM2ENC                 RCC_MEMENCR_AXISRAM2ENC_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENCR_FLEXRAMENC_Pos              (9U)
+#define RCC_MEMENCR_FLEXRAMENC_Msk              (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */
+#define RCC_MEMENCR_FLEXRAMENC                  RCC_MEMENCR_FLEXRAMENC_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENCR_CACHEAXIRAMENC_Pos          (10U)
+#define RCC_MEMENCR_CACHEAXIRAMENC_Msk          (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos)   /*!< 0x00000400 */
+#define RCC_MEMENCR_CACHEAXIRAMENC              RCC_MEMENCR_CACHEAXIRAMENC_Msk       /*!< CACHEAXIRAM enable */
+#define RCC_MEMENCR_VENCRAMENC_Pos              (11U)
+#define RCC_MEMENCR_VENCRAMENC_Msk              (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */
+#define RCC_MEMENCR_VENCRAMENC                  RCC_MEMENCR_VENCRAMENC_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENCR_BOOTROMENC_Pos              (12U)
+#define RCC_MEMENCR_BOOTROMENC_Msk              (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */
+#define RCC_MEMENCR_BOOTROMENC                  RCC_MEMENCR_BOOTROMENC_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENCR register  *****************/
+#define RCC_AHB1ENCR_GPDMA1ENC_Pos              (4U)
+#define RCC_AHB1ENCR_GPDMA1ENC_Msk              (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENCR_GPDMA1ENC                  RCC_AHB1ENCR_GPDMA1ENC_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENCR_ADC12ENC_Pos               (5U)
+#define RCC_AHB1ENCR_ADC12ENC_Msk               (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENCR_ADC12ENC                   RCC_AHB1ENCR_ADC12ENC_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENCR register  *****************/
+#define RCC_AHB2ENCR_RAMCFGENC_Pos              (12U)
+#define RCC_AHB2ENCR_RAMCFGENC_Msk              (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENCR_RAMCFGENC                  RCC_AHB2ENCR_RAMCFGENC_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENCR_MDF1ENC_Pos                (16U)
+#define RCC_AHB2ENCR_MDF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENCR_MDF1ENC                    RCC_AHB2ENCR_MDF1ENC_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENCR_ADF1ENC_Pos                (17U)
+#define RCC_AHB2ENCR_ADF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENCR_ADF1ENC                    RCC_AHB2ENCR_ADF1ENC_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENCR register  *****************/
+#define RCC_AHB3ENCR_RNGENC_Pos                 (0U)
+#define RCC_AHB3ENCR_RNGENC_Msk                 (0x1UL << RCC_AHB3ENCR_RNGENC_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENCR_RNGENC                     RCC_AHB3ENCR_RNGENC_Msk              /*!< RNG enable */
+#define RCC_AHB3ENCR_HASHENC_Pos                (1U)
+#define RCC_AHB3ENCR_HASHENC_Msk                (0x1UL << RCC_AHB3ENCR_HASHENC_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENCR_HASHENC                    RCC_AHB3ENCR_HASHENC_Msk             /*!< HASH enable */
+#define RCC_AHB3ENCR_PKAENC_Pos                 (8U)
+#define RCC_AHB3ENCR_PKAENC_Msk                 (0x1UL << RCC_AHB3ENCR_PKAENC_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENCR_PKAENC                     RCC_AHB3ENCR_PKAENC_Msk              /*!< PKA enable */
+#define RCC_AHB3ENCR_RIFSCENC_Pos               (9U)
+#define RCC_AHB3ENCR_RIFSCENC_Msk               (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENCR_RIFSCENC                   RCC_AHB3ENCR_RIFSCENC_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENCR_IACENC_Pos                 (10U)
+#define RCC_AHB3ENCR_IACENC_Msk                 (0x1UL << RCC_AHB3ENCR_IACENC_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENCR_IACENC                     RCC_AHB3ENCR_IACENC_Msk              /*!< IAC enable */
+#define RCC_AHB3ENCR_RISAFENC_Pos               (14U)
+#define RCC_AHB3ENCR_RISAFENC_Msk               (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENCR_RISAFENC                   RCC_AHB3ENCR_RISAFENC_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENCR register  *****************/
+#define RCC_AHB4ENCR_GPIOAENC_Pos               (0U)
+#define RCC_AHB4ENCR_GPIOAENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENCR_GPIOAENC                   RCC_AHB4ENCR_GPIOAENC_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENCR_GPIOBENC_Pos               (1U)
+#define RCC_AHB4ENCR_GPIOBENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENCR_GPIOBENC                   RCC_AHB4ENCR_GPIOBENC_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENCR_GPIOCENC_Pos               (2U)
+#define RCC_AHB4ENCR_GPIOCENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENCR_GPIOCENC                   RCC_AHB4ENCR_GPIOCENC_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENCR_GPIODENC_Pos               (3U)
+#define RCC_AHB4ENCR_GPIODENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENCR_GPIODENC                   RCC_AHB4ENCR_GPIODENC_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENCR_GPIOEENC_Pos               (4U)
+#define RCC_AHB4ENCR_GPIOEENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENCR_GPIOEENC                   RCC_AHB4ENCR_GPIOEENC_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENCR_GPIOFENC_Pos               (5U)
+#define RCC_AHB4ENCR_GPIOFENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENCR_GPIOFENC                   RCC_AHB4ENCR_GPIOFENC_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENCR_GPIOGENC_Pos               (6U)
+#define RCC_AHB4ENCR_GPIOGENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENCR_GPIOGENC                   RCC_AHB4ENCR_GPIOGENC_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENCR_GPIOHENC_Pos               (7U)
+#define RCC_AHB4ENCR_GPIOHENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENCR_GPIOHENC                   RCC_AHB4ENCR_GPIOHENC_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENCR_GPIONENC_Pos               (13U)
+#define RCC_AHB4ENCR_GPIONENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENCR_GPIONENC                   RCC_AHB4ENCR_GPIONENC_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENCR_GPIOOENC_Pos               (14U)
+#define RCC_AHB4ENCR_GPIOOENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENCR_GPIOOENC                   RCC_AHB4ENCR_GPIOOENC_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENCR_GPIOPENC_Pos               (15U)
+#define RCC_AHB4ENCR_GPIOPENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENCR_GPIOPENC                   RCC_AHB4ENCR_GPIOPENC_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENCR_GPIOQENC_Pos               (16U)
+#define RCC_AHB4ENCR_GPIOQENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENCR_GPIOQENC                   RCC_AHB4ENCR_GPIOQENC_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENCR_PWRENC_Pos                 (18U)
+#define RCC_AHB4ENCR_PWRENC_Msk                 (0x1UL << RCC_AHB4ENCR_PWRENC_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENCR_PWRENC                     RCC_AHB4ENCR_PWRENC_Msk              /*!< PWR enable */
+#define RCC_AHB4ENCR_CRCENC_Pos                 (19U)
+#define RCC_AHB4ENCR_CRCENC_Msk                 (0x1UL << RCC_AHB4ENCR_CRCENC_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENCR_CRCENC                     RCC_AHB4ENCR_CRCENC_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENCR register  *****************/
+#define RCC_AHB5ENCR_HPDMA1ENC_Pos              (0U)
+#define RCC_AHB5ENCR_HPDMA1ENC_Msk              (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENCR_HPDMA1ENC                  RCC_AHB5ENCR_HPDMA1ENC_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENCR_DMA2DENC_Pos               (1U)
+#define RCC_AHB5ENCR_DMA2DENC_Msk               (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENCR_DMA2DENC                   RCC_AHB5ENCR_DMA2DENC_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENCR_JPEGENC_Pos                (3U)
+#define RCC_AHB5ENCR_JPEGENC_Msk                (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENCR_JPEGENC                    RCC_AHB5ENCR_JPEGENC_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENCR_FMCENC_Pos                 (4U)
+#define RCC_AHB5ENCR_FMCENC_Msk                 (0x1UL << RCC_AHB5ENCR_FMCENC_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENCR_FMCENC                     RCC_AHB5ENCR_FMCENC_Msk              /*!< FMC enable */
+#define RCC_AHB5ENCR_XSPI1ENC_Pos               (5U)
+#define RCC_AHB5ENCR_XSPI1ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENCR_XSPI1ENC                   RCC_AHB5ENCR_XSPI1ENC_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENCR_PSSIENC_Pos                (6U)
+#define RCC_AHB5ENCR_PSSIENC_Msk                (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENCR_PSSIENC                    RCC_AHB5ENCR_PSSIENC_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENCR_SDMMC2ENC_Pos              (7U)
+#define RCC_AHB5ENCR_SDMMC2ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENCR_SDMMC2ENC                  RCC_AHB5ENCR_SDMMC2ENC_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENCR_SDMMC1ENC_Pos              (8U)
+#define RCC_AHB5ENCR_SDMMC1ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENCR_SDMMC1ENC                  RCC_AHB5ENCR_SDMMC1ENC_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENCR_XSPI2ENC_Pos               (12U)
+#define RCC_AHB5ENCR_XSPI2ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENCR_XSPI2ENC                   RCC_AHB5ENCR_XSPI2ENC_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENCR_XSPIMENC_Pos               (13U)
+#define RCC_AHB5ENCR_XSPIMENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENCR_XSPIMENC                   RCC_AHB5ENCR_XSPIMENC_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENCR_XSPI3ENC_Pos               (17U)
+#define RCC_AHB5ENCR_XSPI3ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENCR_XSPI3ENC                   RCC_AHB5ENCR_XSPI3ENC_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENCR_GFXMMUENC_Pos              (19U)
+#define RCC_AHB5ENCR_GFXMMUENC_Msk              (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENCR_GFXMMUENC                  RCC_AHB5ENCR_GFXMMUENC_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENCR_GPU2DENC_Pos               (20U)
+#define RCC_AHB5ENCR_GPU2DENC_Msk               (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENCR_GPU2DENC                   RCC_AHB5ENCR_GPU2DENC_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENCR_ETH1MACENC_Pos             (22U)
+#define RCC_AHB5ENCR_ETH1MACENC_Msk             (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENCR_ETH1MACENC                 RCC_AHB5ENCR_ETH1MACENC_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENCR_ETH1TXENC_Pos              (23U)
+#define RCC_AHB5ENCR_ETH1TXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENCR_ETH1TXENC                  RCC_AHB5ENCR_ETH1TXENC_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENCR_ETH1RXENC_Pos              (24U)
+#define RCC_AHB5ENCR_ETH1RXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENCR_ETH1RXENC                  RCC_AHB5ENCR_ETH1RXENC_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENCR_ETH1ENC_Pos                (25U)
+#define RCC_AHB5ENCR_ETH1ENC_Msk                (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENCR_ETH1ENC                    RCC_AHB5ENCR_ETH1ENC_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENCR_OTG1ENC_Pos                (26U)
+#define RCC_AHB5ENCR_OTG1ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENCR_OTG1ENC                    RCC_AHB5ENCR_OTG1ENC_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENCR_OTGPHY1ENC_Pos             (27U)
+#define RCC_AHB5ENCR_OTGPHY1ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENCR_OTGPHY1ENC                 RCC_AHB5ENCR_OTGPHY1ENC_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENCR_OTGPHY2ENC_Pos             (28U)
+#define RCC_AHB5ENCR_OTGPHY2ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENCR_OTGPHY2ENC                 RCC_AHB5ENCR_OTGPHY2ENC_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENCR_OTG2ENC_Pos                (29U)
+#define RCC_AHB5ENCR_OTG2ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENCR_OTG2ENC                    RCC_AHB5ENCR_OTG2ENC_Msk             /*!< OTG2 enable */
+#define RCC_AHB5ENCR_CACHEAXIENC_Pos            (30U)
+#define RCC_AHB5ENCR_CACHEAXIENC_Msk            (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */
+#define RCC_AHB5ENCR_CACHEAXIENC                RCC_AHB5ENCR_CACHEAXIENC_Msk         /*!< CACHEAXI enable */
+#define RCC_AHB5ENCR_NPUENC_Pos                 (31U)
+#define RCC_AHB5ENCR_NPUENC_Msk                 (0x1UL << RCC_AHB5ENCR_NPUENC_Pos)    /*!< 0x80000000 */
+#define RCC_AHB5ENCR_NPUENC                     RCC_AHB5ENCR_NPUENC_Msk              /*!< NPU enable */
+
+/****************  Bit definition for RCC_APB1ENCR1 register  *****************/
+#define RCC_APB1ENCR1_TIM2ENC_Pos               (0U)
+#define RCC_APB1ENCR1_TIM2ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENCR1_TIM2ENC                   RCC_APB1ENCR1_TIM2ENC_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENCR1_TIM3ENC_Pos               (1U)
+#define RCC_APB1ENCR1_TIM3ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENCR1_TIM3ENC                   RCC_APB1ENCR1_TIM3ENC_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENCR1_TIM4ENC_Pos               (2U)
+#define RCC_APB1ENCR1_TIM4ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENCR1_TIM4ENC                   RCC_APB1ENCR1_TIM4ENC_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENCR1_TIM5ENC_Pos               (3U)
+#define RCC_APB1ENCR1_TIM5ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENCR1_TIM5ENC                   RCC_APB1ENCR1_TIM5ENC_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENCR1_TIM6ENC_Pos               (4U)
+#define RCC_APB1ENCR1_TIM6ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENCR1_TIM6ENC                   RCC_APB1ENCR1_TIM6ENC_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENCR1_TIM7ENC_Pos               (5U)
+#define RCC_APB1ENCR1_TIM7ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENCR1_TIM7ENC                   RCC_APB1ENCR1_TIM7ENC_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENCR1_TIM12ENC_Pos              (6U)
+#define RCC_APB1ENCR1_TIM12ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENCR1_TIM12ENC                  RCC_APB1ENCR1_TIM12ENC_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENCR1_TIM13ENC_Pos              (7U)
+#define RCC_APB1ENCR1_TIM13ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENCR1_TIM13ENC                  RCC_APB1ENCR1_TIM13ENC_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENCR1_TIM14ENC_Pos              (8U)
+#define RCC_APB1ENCR1_TIM14ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR1_TIM14ENC                  RCC_APB1ENCR1_TIM14ENC_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENCR1_LPTIM1ENC_Pos             (9U)
+#define RCC_APB1ENCR1_LPTIM1ENC_Msk             (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENCR1_LPTIM1ENC                 RCC_APB1ENCR1_LPTIM1ENC_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENCR1_TIM10ENC_Pos              (12U)
+#define RCC_APB1ENCR1_TIM10ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENCR1_TIM10ENC                  RCC_APB1ENCR1_TIM10ENC_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENCR1_TIM11ENC_Pos              (13U)
+#define RCC_APB1ENCR1_TIM11ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENCR1_TIM11ENC                  RCC_APB1ENCR1_TIM11ENC_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENCR1_SPI2ENC_Pos               (14U)
+#define RCC_APB1ENCR1_SPI2ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENCR1_SPI2ENC                   RCC_APB1ENCR1_SPI2ENC_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENCR1_SPI3ENC_Pos               (15U)
+#define RCC_APB1ENCR1_SPI3ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENCR1_SPI3ENC                   RCC_APB1ENCR1_SPI3ENC_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos           (16U)
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk           (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENCR1_SPDIFRX1ENC               RCC_APB1ENCR1_SPDIFRX1ENC_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENCR1_USART2ENC_Pos             (17U)
+#define RCC_APB1ENCR1_USART2ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENCR1_USART2ENC                 RCC_APB1ENCR1_USART2ENC_Msk          /*!< USART2 enable */
+#define RCC_APB1ENCR1_USART3ENC_Pos             (18U)
+#define RCC_APB1ENCR1_USART3ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENCR1_USART3ENC                 RCC_APB1ENCR1_USART3ENC_Msk          /*!< USART3 enable */
+#define RCC_APB1ENCR1_UART4ENC_Pos              (19U)
+#define RCC_APB1ENCR1_UART4ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENCR1_UART4ENC                  RCC_APB1ENCR1_UART4ENC_Msk           /*!< UART4 enable */
+#define RCC_APB1ENCR1_UART5ENC_Pos              (20U)
+#define RCC_APB1ENCR1_UART5ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENCR1_UART5ENC                  RCC_APB1ENCR1_UART5ENC_Msk           /*!< UART5 enable */
+#define RCC_APB1ENCR1_I2C1ENC_Pos               (21U)
+#define RCC_APB1ENCR1_I2C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENCR1_I2C1ENC                   RCC_APB1ENCR1_I2C1ENC_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENCR1_I2C2ENC_Pos               (22U)
+#define RCC_APB1ENCR1_I2C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENCR1_I2C2ENC                   RCC_APB1ENCR1_I2C2ENC_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENCR1_I2C3ENC_Pos               (23U)
+#define RCC_APB1ENCR1_I2C3ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENCR1_I2C3ENC                   RCC_APB1ENCR1_I2C3ENC_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENCR1_I3C1ENC_Pos               (24U)
+#define RCC_APB1ENCR1_I3C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENCR1_I3C1ENC                   RCC_APB1ENCR1_I3C1ENC_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENCR1_I3C2ENC_Pos               (25U)
+#define RCC_APB1ENCR1_I3C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENCR1_I3C2ENC                   RCC_APB1ENCR1_I3C2ENC_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENCR1_UART7ENC_Pos              (30U)
+#define RCC_APB1ENCR1_UART7ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENCR1_UART7ENC                  RCC_APB1ENCR1_UART7ENC_Msk           /*!< UART7 enable */
+#define RCC_APB1ENCR1_UART8ENC_Pos              (31U)
+#define RCC_APB1ENCR1_UART8ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENCR1_UART8ENC                  RCC_APB1ENCR1_UART8ENC_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENCR2 register  *****************/
+#define RCC_APB1ENCR2_MDIOSENC_Pos              (5U)
+#define RCC_APB1ENCR2_MDIOSENC_Msk              (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENCR2_MDIOSENC                  RCC_APB1ENCR2_MDIOSENC_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENCR2_FDCANENC_Pos              (8U)
+#define RCC_APB1ENCR2_FDCANENC_Msk              (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR2_FDCANENC                  RCC_APB1ENCR2_FDCANENC_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENCR2_UCPD1ENC_Pos              (18U)
+#define RCC_APB1ENCR2_UCPD1ENC_Msk              (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENCR2_UCPD1ENC                  RCC_APB1ENCR2_UCPD1ENC_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENCR register  *****************/
+#define RCC_APB2ENCR_TIM1ENC_Pos                (0U)
+#define RCC_APB2ENCR_TIM1ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENCR_TIM1ENC                    RCC_APB2ENCR_TIM1ENC_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENCR_TIM8ENC_Pos                (1U)
+#define RCC_APB2ENCR_TIM8ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENCR_TIM8ENC                    RCC_APB2ENCR_TIM8ENC_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENCR_USART1ENC_Pos              (4U)
+#define RCC_APB2ENCR_USART1ENC_Msk              (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENCR_USART1ENC                  RCC_APB2ENCR_USART1ENC_Msk           /*!< USART1 enable */
+#define RCC_APB2ENCR_USART6ENC_Pos              (5U)
+#define RCC_APB2ENCR_USART6ENC_Msk              (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENCR_USART6ENC                  RCC_APB2ENCR_USART6ENC_Msk           /*!< USART6 enable */
+#define RCC_APB2ENCR_UART9ENC_Pos               (6U)
+#define RCC_APB2ENCR_UART9ENC_Msk               (0x1UL << RCC_APB2ENCR_UART9ENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENCR_UART9ENC                   RCC_APB2ENCR_UART9ENC_Msk            /*!< UART9 enable */
+#define RCC_APB2ENCR_USART10ENC_Pos             (7U)
+#define RCC_APB2ENCR_USART10ENC_Msk             (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENCR_USART10ENC                 RCC_APB2ENCR_USART10ENC_Msk          /*!< USART10 enable */
+#define RCC_APB2ENCR_SPI1ENC_Pos                (12U)
+#define RCC_APB2ENCR_SPI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENCR_SPI1ENC                    RCC_APB2ENCR_SPI1ENC_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENCR_SPI4ENC_Pos                (13U)
+#define RCC_APB2ENCR_SPI4ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENCR_SPI4ENC                    RCC_APB2ENCR_SPI4ENC_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENCR_TIM18ENC_Pos               (15U)
+#define RCC_APB2ENCR_TIM18ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENCR_TIM18ENC                   RCC_APB2ENCR_TIM18ENC_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENCR_TIM15ENC_Pos               (16U)
+#define RCC_APB2ENCR_TIM15ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENCR_TIM15ENC                   RCC_APB2ENCR_TIM15ENC_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENCR_TIM16ENC_Pos               (17U)
+#define RCC_APB2ENCR_TIM16ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENCR_TIM16ENC                   RCC_APB2ENCR_TIM16ENC_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENCR_TIM17ENC_Pos               (18U)
+#define RCC_APB2ENCR_TIM17ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENCR_TIM17ENC                   RCC_APB2ENCR_TIM17ENC_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENCR_TIM9ENC_Pos                (19U)
+#define RCC_APB2ENCR_TIM9ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENCR_TIM9ENC                    RCC_APB2ENCR_TIM9ENC_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENCR_SPI5ENC_Pos                (20U)
+#define RCC_APB2ENCR_SPI5ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENCR_SPI5ENC                    RCC_APB2ENCR_SPI5ENC_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENCR_SAI1ENC_Pos                (21U)
+#define RCC_APB2ENCR_SAI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENCR_SAI1ENC                    RCC_APB2ENCR_SAI1ENC_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENCR_SAI2ENC_Pos                (22U)
+#define RCC_APB2ENCR_SAI2ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENCR_SAI2ENC                    RCC_APB2ENCR_SAI2ENC_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENCR register  *****************/
+#define RCC_APB3ENCR_DFTENC_Pos                 (2U)
+#define RCC_APB3ENCR_DFTENC_Msk                 (0x1UL << RCC_APB3ENCR_DFTENC_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENCR_DFTENC                     RCC_APB3ENCR_DFTENC_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENCR1 register  *****************/
+#define RCC_APB4ENCR1_HDPENC_Pos                (2U)
+#define RCC_APB4ENCR1_HDPENC_Msk                (0x1UL << RCC_APB4ENCR1_HDPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR1_HDPENC                    RCC_APB4ENCR1_HDPENC_Msk             /*!< HDP enable */
+#define RCC_APB4ENCR1_LPUART1ENC_Pos            (3U)
+#define RCC_APB4ENCR1_LPUART1ENC_Msk            (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENCR1_LPUART1ENC                RCC_APB4ENCR1_LPUART1ENC_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENCR1_SPI6ENC_Pos               (5U)
+#define RCC_APB4ENCR1_SPI6ENC_Msk               (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENCR1_SPI6ENC                   RCC_APB4ENCR1_SPI6ENC_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENCR1_I2C4ENC_Pos               (7U)
+#define RCC_APB4ENCR1_I2C4ENC_Msk               (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENCR1_I2C4ENC                   RCC_APB4ENCR1_I2C4ENC_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENCR1_LPTIM2ENC_Pos             (9U)
+#define RCC_APB4ENCR1_LPTIM2ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENCR1_LPTIM2ENC                 RCC_APB4ENCR1_LPTIM2ENC_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENCR1_LPTIM3ENC_Pos             (10U)
+#define RCC_APB4ENCR1_LPTIM3ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENCR1_LPTIM3ENC                 RCC_APB4ENCR1_LPTIM3ENC_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENCR1_LPTIM4ENC_Pos             (11U)
+#define RCC_APB4ENCR1_LPTIM4ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENCR1_LPTIM4ENC                 RCC_APB4ENCR1_LPTIM4ENC_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENCR1_LPTIM5ENC_Pos             (12U)
+#define RCC_APB4ENCR1_LPTIM5ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENCR1_LPTIM5ENC                 RCC_APB4ENCR1_LPTIM5ENC_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENCR1_VREFBUFENC_Pos            (15U)
+#define RCC_APB4ENCR1_VREFBUFENC_Msk            (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENCR1_VREFBUFENC                RCC_APB4ENCR1_VREFBUFENC_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENCR1_RTCENC_Pos                (16U)
+#define RCC_APB4ENCR1_RTCENC_Msk                (0x1UL << RCC_APB4ENCR1_RTCENC_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENCR1_RTCENC                    RCC_APB4ENCR1_RTCENC_Msk             /*!< RTC enable */
+#define RCC_APB4ENCR1_RTCAPBENC_Pos             (17U)
+#define RCC_APB4ENCR1_RTCAPBENC_Msk             (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENCR1_RTCAPBENC                 RCC_APB4ENCR1_RTCAPBENC_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENCR2 register  *****************/
+#define RCC_APB4ENCR2_SYSCFGENC_Pos             (0U)
+#define RCC_APB4ENCR2_SYSCFGENC_Msk             (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENCR2_SYSCFGENC                 RCC_APB4ENCR2_SYSCFGENC_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENCR2_BSECENC_Pos               (1U)
+#define RCC_APB4ENCR2_BSECENC_Msk               (0x1UL << RCC_APB4ENCR2_BSECENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENCR2_BSECENC                   RCC_APB4ENCR2_BSECENC_Msk            /*!< BSEC enable */
+#define RCC_APB4ENCR2_DTSENC_Pos                (2U)
+#define RCC_APB4ENCR2_DTSENC_Msk                (0x1UL << RCC_APB4ENCR2_DTSENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR2_DTSENC                    RCC_APB4ENCR2_DTSENC_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENCR register  *****************/
+#define RCC_APB5ENCR_LTDCENC_Pos                (1U)
+#define RCC_APB5ENCR_LTDCENC_Msk                (0x1UL << RCC_APB5ENCR_LTDCENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENCR_LTDCENC                    RCC_APB5ENCR_LTDCENC_Msk             /*!< LTDC enable */
+#define RCC_APB5ENCR_DCMIPPENC_Pos              (2U)
+#define RCC_APB5ENCR_DCMIPPENC_Msk              (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENCR_DCMIPPENC                  RCC_APB5ENCR_DCMIPPENC_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENCR_GFXTIMENC_Pos              (4U)
+#define RCC_APB5ENCR_GFXTIMENC_Msk              (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENCR_GFXTIMENC                  RCC_APB5ENCR_GFXTIMENC_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENCR_VENCENC_Pos                (5U)
+#define RCC_APB5ENCR_VENCENC_Msk                (0x1UL << RCC_APB5ENCR_VENCENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENCR_VENCENC                    RCC_APB5ENCR_VENCENC_Msk             /*!< VENC enable */
+#define RCC_APB5ENCR_CSIENC_Pos                 (6U)
+#define RCC_APB5ENCR_CSIENC_Msk                 (0x1UL << RCC_APB5ENCR_CSIENC_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENCR_CSIENC                     RCC_APB5ENCR_CSIENC_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENCR register  *****************/
+#define RCC_BUSLPENCR_ACLKNLPENC_Pos            (0U)
+#define RCC_BUSLPENCR_ACLKNLPENC_Msk            (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENCR_ACLKNLPENC                RCC_BUSLPENCR_ACLKNLPENC_Msk         /*!< ACLKN enable in Sleep mode */
+#define RCC_BUSLPENCR_ACLKNCLPENC_Pos           (1U)
+#define RCC_BUSLPENCR_ACLKNCLPENC_Msk           (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENCR_ACLKNCLPENC               RCC_BUSLPENCR_ACLKNCLPENC_Msk        /*!< ACLKNC enable in Sleep mode */
+
+/****************  Bit definition for RCC_MISCLPENCR register  ****************/
+#define RCC_MISCLPENCR_DBGLPENC_Pos             (0U)
+#define RCC_MISCLPENCR_DBGLPENC_Msk             (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENCR_DBGLPENC                 RCC_MISCLPENCR_DBGLPENC_Msk          /*!< DBG enable in Sleep mode */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos     (3U)
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk     (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC         RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk  /*!< XSPIPHYCOMP enable in Sleep mode */
+#define RCC_MISCLPENCR_PERLPENC_Pos             (6U)
+#define RCC_MISCLPENCR_PERLPENC_Msk             (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENCR_PERLPENC                 RCC_MISCLPENCR_PERLPENC_Msk          /*!< PER enable in Sleep mode */
+
+/****************  Bit definition for RCC_MEMLPENCR register  *****************/
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos         (0U)
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENCR_AXISRAM3LPENC             RCC_MEMLPENCR_AXISRAM3LPENC_Msk      /*!< AXISRAM3 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos         (1U)
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENCR_AXISRAM4LPENC             RCC_MEMLPENCR_AXISRAM4LPENC_Msk      /*!< AXISRAM4 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos         (2U)
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENCR_AXISRAM5LPENC             RCC_MEMLPENCR_AXISRAM5LPENC_Msk      /*!< AXISRAM5 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos         (3U)
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENCR_AXISRAM6LPENC             RCC_MEMLPENCR_AXISRAM6LPENC_Msk      /*!< AXISRAM6 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos         (4U)
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC             RCC_MEMLPENCR_AHBSRAM1LPENC_Msk      /*!< AHBSRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos         (5U)
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC             RCC_MEMLPENCR_AHBSRAM2LPENC_Msk      /*!< AHBSRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos          (6U)
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENCR_BKPSRAMLPENC              RCC_MEMLPENCR_BKPSRAMLPENC_Msk       /*!< BKPSRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos         (7U)
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENCR_AXISRAM1LPENC             RCC_MEMLPENCR_AXISRAM1LPENC_Msk      /*!< AXISRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos         (8U)
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENCR_AXISRAM2LPENC             RCC_MEMLPENCR_AXISRAM2LPENC_Msk      /*!< AXISRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos          (9U)
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENCR_FLEXRAMLPENC              RCC_MEMLPENCR_FLEXRAMLPENC_Msk       /*!< FLEXRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos      (10U)
+#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk      (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos)       /*!< 0x00000400 */
+#define RCC_MEMLPENCR_CACHEAXIRAMLPENC          RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk   /*!< CACHEAXIRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_VENCRAMLPENC_Pos          (11U)
+#define RCC_MEMLPENCR_VENCRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENCR_VENCRAMLPENC              RCC_MEMLPENCR_VENCRAMLPENC_Msk       /*!< VENCRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_BOOTROMLPENC_Pos          (12U)
+#define RCC_MEMLPENCR_BOOTROMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENCR_BOOTROMLPENC              RCC_MEMLPENCR_BOOTROMLPENC_Msk       /*!< Boot ROM enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB1LPENCR register  ****************/
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos          (4U)
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk          (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENCR_GPDMA1LPENC              RCC_AHB1LPENCR_GPDMA1LPENC_Msk       /*!< GPDMA1 enable in Sleep mode */
+#define RCC_AHB1LPENCR_ADC12LPENC_Pos           (5U)
+#define RCC_AHB1LPENCR_ADC12LPENC_Msk           (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENCR_ADC12LPENC               RCC_AHB1LPENCR_ADC12LPENC_Msk        /*!< ADC12 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB2LPENCR register  ****************/
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos          (12U)
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk          (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENCR_RAMCFGLPENC              RCC_AHB2LPENCR_RAMCFGLPENC_Msk       /*!< RAMCFG enable in Sleep mode */
+#define RCC_AHB2LPENCR_MDF1LPENC_Pos            (16U)
+#define RCC_AHB2LPENCR_MDF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENCR_MDF1LPENC                RCC_AHB2LPENCR_MDF1LPENC_Msk         /*!< MDF1 enable in Sleep mode */
+#define RCC_AHB2LPENCR_ADF1LPENC_Pos            (17U)
+#define RCC_AHB2LPENCR_ADF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENCR_ADF1LPENC                RCC_AHB2LPENCR_ADF1LPENC_Msk         /*!< ADF1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB3LPENCR register  ****************/
+#define RCC_AHB3LPENCR_RNGLPENC_Pos             (0U)
+#define RCC_AHB3LPENCR_RNGLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENCR_RNGLPENC                 RCC_AHB3LPENCR_RNGLPENC_Msk          /*!< RNG enable in Sleep mode */
+#define RCC_AHB3LPENCR_HASHLPENC_Pos            (1U)
+#define RCC_AHB3LPENCR_HASHLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENCR_HASHLPENC                RCC_AHB3LPENCR_HASHLPENC_Msk         /*!< HASH enable in Sleep mode */
+#define RCC_AHB3LPENCR_PKALPENC_Pos             (8U)
+#define RCC_AHB3LPENCR_PKALPENC_Msk             (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENCR_PKALPENC                 RCC_AHB3LPENCR_PKALPENC_Msk          /*!< PKA enable in Sleep mode */
+#define RCC_AHB3LPENCR_RIFSCLPENC_Pos           (9U)
+#define RCC_AHB3LPENCR_RIFSCLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENCR_RIFSCLPENC               RCC_AHB3LPENCR_RIFSCLPENC_Msk        /*!< RIFSC enable in Sleep mode */
+#define RCC_AHB3LPENCR_IACLPENC_Pos             (10U)
+#define RCC_AHB3LPENCR_IACLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENCR_IACLPENC                 RCC_AHB3LPENCR_IACLPENC_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENCR_RISAFLPENC_Pos           (14U)
+#define RCC_AHB3LPENCR_RISAFLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENCR_RISAFLPENC               RCC_AHB3LPENCR_RISAFLPENC_Msk        /*!< RISAF enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB4LPENCR register  ****************/
+#define RCC_AHB4LPENCR_GPIOALPENC_Pos           (0U)
+#define RCC_AHB4LPENCR_GPIOALPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENCR_GPIOALPENC               RCC_AHB4LPENCR_GPIOALPENC_Msk        /*!< GPIO A enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOBLPENC_Pos           (1U)
+#define RCC_AHB4LPENCR_GPIOBLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENCR_GPIOBLPENC               RCC_AHB4LPENCR_GPIOBLPENC_Msk        /*!< GPIO B enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOCLPENC_Pos           (2U)
+#define RCC_AHB4LPENCR_GPIOCLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENCR_GPIOCLPENC               RCC_AHB4LPENCR_GPIOCLPENC_Msk        /*!< GPIO C enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIODLPENC_Pos           (3U)
+#define RCC_AHB4LPENCR_GPIODLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENCR_GPIODLPENC               RCC_AHB4LPENCR_GPIODLPENC_Msk        /*!< GPIO D enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOELPENC_Pos           (4U)
+#define RCC_AHB4LPENCR_GPIOELPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENCR_GPIOELPENC               RCC_AHB4LPENCR_GPIOELPENC_Msk        /*!< GPIO E enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOFLPENC_Pos           (5U)
+#define RCC_AHB4LPENCR_GPIOFLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENCR_GPIOFLPENC               RCC_AHB4LPENCR_GPIOFLPENC_Msk        /*!< GPIO F enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOGLPENC_Pos           (6U)
+#define RCC_AHB4LPENCR_GPIOGLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENCR_GPIOGLPENC               RCC_AHB4LPENCR_GPIOGLPENC_Msk        /*!< GPIO G enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOHLPENC_Pos           (7U)
+#define RCC_AHB4LPENCR_GPIOHLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENCR_GPIOHLPENC               RCC_AHB4LPENCR_GPIOHLPENC_Msk        /*!< GPIO H enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIONLPENC_Pos           (13U)
+#define RCC_AHB4LPENCR_GPIONLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENCR_GPIONLPENC               RCC_AHB4LPENCR_GPIONLPENC_Msk        /*!< GPIO N enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOOLPENC_Pos           (14U)
+#define RCC_AHB4LPENCR_GPIOOLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENCR_GPIOOLPENC               RCC_AHB4LPENCR_GPIOOLPENC_Msk        /*!< GPIO O enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOPLPENC_Pos           (15U)
+#define RCC_AHB4LPENCR_GPIOPLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENCR_GPIOPLPENC               RCC_AHB4LPENCR_GPIOPLPENC_Msk        /*!< GPIO P enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOQLPENC_Pos           (16U)
+#define RCC_AHB4LPENCR_GPIOQLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENCR_GPIOQLPENC               RCC_AHB4LPENCR_GPIOQLPENC_Msk        /*!< GPIO Q enable in Sleep mode */
+#define RCC_AHB4LPENCR_PWRLPENC_Pos             (18U)
+#define RCC_AHB4LPENCR_PWRLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENCR_PWRLPENC                 RCC_AHB4LPENCR_PWRLPENC_Msk          /*!< PWR enable in Sleep mode */
+#define RCC_AHB4LPENCR_CRCLPENC_Pos             (19U)
+#define RCC_AHB4LPENCR_CRCLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENCR_CRCLPENC                 RCC_AHB4LPENCR_CRCLPENC_Msk          /*!< CRC enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB5LPENCR register  ****************/
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos          (0U)
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENCR_HPDMA1LPENC              RCC_AHB5LPENCR_HPDMA1LPENC_Msk       /*!< HPDMA1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_DMA2DLPENC_Pos           (1U)
+#define RCC_AHB5LPENCR_DMA2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENCR_DMA2DLPENC               RCC_AHB5LPENCR_DMA2DLPENC_Msk        /*!< DMA2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_JPEGLPENC_Pos            (3U)
+#define RCC_AHB5LPENCR_JPEGLPENC_Msk            (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENCR_JPEGLPENC                RCC_AHB5LPENCR_JPEGLPENC_Msk         /*!< JPEG enable in Sleep mode */
+#define RCC_AHB5LPENCR_FMCLPENC_Pos             (4U)
+#define RCC_AHB5LPENCR_FMCLPENC_Msk             (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENCR_FMCLPENC                 RCC_AHB5LPENCR_FMCLPENC_Msk          /*!< FMC enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI1LPENC_Pos           (5U)
+#define RCC_AHB5LPENCR_XSPI1LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENCR_XSPI1LPENC               RCC_AHB5LPENCR_XSPI1LPENC_Msk        /*!< XSPI1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_PSSILPENC_Pos            (6U)
+#define RCC_AHB5LPENCR_PSSILPENC_Msk            (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENCR_PSSILPENC                RCC_AHB5LPENCR_PSSILPENC_Msk         /*!< PSSI enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos          (7U)
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENCR_SDMMC2LPENC              RCC_AHB5LPENCR_SDMMC2LPENC_Msk       /*!< SDMMC2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos          (8U)
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENCR_SDMMC1LPENC              RCC_AHB5LPENCR_SDMMC1LPENC_Msk       /*!< SDMMC1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI2LPENC_Pos           (12U)
+#define RCC_AHB5LPENCR_XSPI2LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENCR_XSPI2LPENC               RCC_AHB5LPENCR_XSPI2LPENC_Msk        /*!< XSPI2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPIMLPENC_Pos           (13U)
+#define RCC_AHB5LPENCR_XSPIMLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENCR_XSPIMLPENC               RCC_AHB5LPENCR_XSPIMLPENC_Msk        /*!< XSPIM enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI3LPENC_Pos           (17U)
+#define RCC_AHB5LPENCR_XSPI3LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENCR_XSPI3LPENC               RCC_AHB5LPENCR_XSPI3LPENC_Msk        /*!< XSPI3 enable in Sleep mode */
+#define RCC_AHB5LPENCR_GFXMMULPENC_Pos          (19U)
+#define RCC_AHB5LPENCR_GFXMMULPENC_Msk          (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENCR_GFXMMULPENC              RCC_AHB5LPENCR_GFXMMULPENC_Msk       /*!< GFXMMU enable in Sleep mode */
+#define RCC_AHB5LPENCR_GPU2DLPENC_Pos           (20U)
+#define RCC_AHB5LPENCR_GPU2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENCR_GPU2DLPENC               RCC_AHB5LPENCR_GPU2DLPENC_Msk        /*!< GPU2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos         (22U)
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk         (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENCR_ETH1MACLPENC             RCC_AHB5LPENCR_ETH1MACLPENC_Msk      /*!< ETH1MAC enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos          (23U)
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENCR_ETH1TXLPENC              RCC_AHB5LPENCR_ETH1TXLPENC_Msk       /*!< ETH1TX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos          (24U)
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENCR_ETH1RXLPENC              RCC_AHB5LPENCR_ETH1RXLPENC_Msk       /*!< ETH1RX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1LPENC_Pos            (25U)
+#define RCC_AHB5LPENCR_ETH1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENCR_ETH1LPENC                RCC_AHB5LPENCR_ETH1LPENC_Msk         /*!< ETH1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG1LPENC_Pos            (26U)
+#define RCC_AHB5LPENCR_OTG1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENCR_OTG1LPENC                RCC_AHB5LPENCR_OTG1LPENC_Msk         /*!< OTG1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos         (27U)
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC             RCC_AHB5LPENCR_OTGPHY1LPENC_Msk      /*!< OTGPHY1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos         (28U)
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC             RCC_AHB5LPENCR_OTGPHY2LPENC_Msk      /*!< OTGPHY2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG2LPENC_Pos            (29U)
+#define RCC_AHB5LPENCR_OTG2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENCR_OTG2LPENC                RCC_AHB5LPENCR_OTG2LPENC_Msk         /*!< OTG2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_CACHEAXILPENC_Pos        (30U)
+#define RCC_AHB5LPENCR_CACHEAXILPENC_Msk        (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos)     /*!< 0x40000000 */
+#define RCC_AHB5LPENCR_CACHEAXILPENC            RCC_AHB5LPENCR_CACHEAXILPENC_Msk     /*!< CACHEAXI enable in Sleep mode */
+#define RCC_AHB5LPENCR_NPULPENC_Pos             (31U)
+#define RCC_AHB5LPENCR_NPULPENC_Msk             (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */
+#define RCC_AHB5LPENCR_NPULPENC                 RCC_AHB5LPENCR_NPULPENC_Msk          /*!< NPU enable in Sleep mode */
+
+/***************  Bit definition for RCC_APB1LPENCR1 register  ****************/
+#define RCC_APB1LPENCR1_TIM2LPENC_Pos           (0U)
+#define RCC_APB1LPENCR1_TIM2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENCR1_TIM2LPENC               RCC_APB1LPENCR1_TIM2LPENC_Msk        /*!< TIM2 enable */
+#define RCC_APB1LPENCR1_TIM3LPENC_Pos           (1U)
+#define RCC_APB1LPENCR1_TIM3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENCR1_TIM3LPENC               RCC_APB1LPENCR1_TIM3LPENC_Msk        /*!< TIM3 enable */
+#define RCC_APB1LPENCR1_TIM4LPENC_Pos           (2U)
+#define RCC_APB1LPENCR1_TIM4LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENCR1_TIM4LPENC               RCC_APB1LPENCR1_TIM4LPENC_Msk        /*!< TIM4 enable */
+#define RCC_APB1LPENCR1_TIM5LPENC_Pos           (3U)
+#define RCC_APB1LPENCR1_TIM5LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENCR1_TIM5LPENC               RCC_APB1LPENCR1_TIM5LPENC_Msk        /*!< TIM5 enable */
+#define RCC_APB1LPENCR1_TIM6LPENC_Pos           (4U)
+#define RCC_APB1LPENCR1_TIM6LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENCR1_TIM6LPENC               RCC_APB1LPENCR1_TIM6LPENC_Msk        /*!< TIM6 enable */
+#define RCC_APB1LPENCR1_TIM7LPENC_Pos           (5U)
+#define RCC_APB1LPENCR1_TIM7LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENCR1_TIM7LPENC               RCC_APB1LPENCR1_TIM7LPENC_Msk        /*!< TIM7 enable */
+#define RCC_APB1LPENCR1_TIM12LPENC_Pos          (6U)
+#define RCC_APB1LPENCR1_TIM12LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENCR1_TIM12LPENC              RCC_APB1LPENCR1_TIM12LPENC_Msk       /*!< TIM12 enable */
+#define RCC_APB1LPENCR1_TIM13LPENC_Pos          (7U)
+#define RCC_APB1LPENCR1_TIM13LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENCR1_TIM13LPENC              RCC_APB1LPENCR1_TIM13LPENC_Msk       /*!< TIM13 enable */
+#define RCC_APB1LPENCR1_TIM14LPENC_Pos          (8U)
+#define RCC_APB1LPENCR1_TIM14LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR1_TIM14LPENC              RCC_APB1LPENCR1_TIM14LPENC_Msk       /*!< TIM14 enable */
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos         (9U)
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENCR1_LPTIM1LPENC             RCC_APB1LPENCR1_LPTIM1LPENC_Msk      /*!< LPTIM1 enable */
+#define RCC_APB1LPENCR1_WWDGLPENC_Pos           (11U)
+#define RCC_APB1LPENCR1_WWDGLPENC_Msk           (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENCR1_WWDGLPENC               RCC_APB1LPENCR1_WWDGLPENC_Msk        /*!< WWDG enable */
+#define RCC_APB1LPENCR1_TIM10LPENC_Pos          (12U)
+#define RCC_APB1LPENCR1_TIM10LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENCR1_TIM10LPENC              RCC_APB1LPENCR1_TIM10LPENC_Msk       /*!< TIM10 enable */
+#define RCC_APB1LPENCR1_TIM11LPENC_Pos          (13U)
+#define RCC_APB1LPENCR1_TIM11LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENCR1_TIM11LPENC              RCC_APB1LPENCR1_TIM11LPENC_Msk       /*!< TIM11 enable */
+#define RCC_APB1LPENCR1_SPI2LPENC_Pos           (14U)
+#define RCC_APB1LPENCR1_SPI2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENCR1_SPI2LPENC               RCC_APB1LPENCR1_SPI2LPENC_Msk        /*!< SPI2 enable */
+#define RCC_APB1LPENCR1_SPI3LPENC_Pos           (15U)
+#define RCC_APB1LPENCR1_SPI3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENCR1_SPI3LPENC               RCC_APB1LPENCR1_SPI3LPENC_Msk        /*!< SPI3 enable */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos       (16U)
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk       (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC           RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk    /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENCR1_USART2LPENC_Pos         (17U)
+#define RCC_APB1LPENCR1_USART2LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENCR1_USART2LPENC             RCC_APB1LPENCR1_USART2LPENC_Msk      /*!< USART2 enable */
+#define RCC_APB1LPENCR1_USART3LPENC_Pos         (18U)
+#define RCC_APB1LPENCR1_USART3LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENCR1_USART3LPENC             RCC_APB1LPENCR1_USART3LPENC_Msk      /*!< USART3 enable */
+#define RCC_APB1LPENCR1_UART4LPENC_Pos          (19U)
+#define RCC_APB1LPENCR1_UART4LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENCR1_UART4LPENC              RCC_APB1LPENCR1_UART4LPENC_Msk       /*!< UART4 enable */
+#define RCC_APB1LPENCR1_UART5LPENC_Pos          (20U)
+#define RCC_APB1LPENCR1_UART5LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENCR1_UART5LPENC              RCC_APB1LPENCR1_UART5LPENC_Msk       /*!< UART5 enable */
+#define RCC_APB1LPENCR1_I2C1LPENC_Pos           (21U)
+#define RCC_APB1LPENCR1_I2C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENCR1_I2C1LPENC               RCC_APB1LPENCR1_I2C1LPENC_Msk        /*!< I2C1 enable */
+#define RCC_APB1LPENCR1_I2C2LPENC_Pos           (22U)
+#define RCC_APB1LPENCR1_I2C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENCR1_I2C2LPENC               RCC_APB1LPENCR1_I2C2LPENC_Msk        /*!< I2C2 enable */
+#define RCC_APB1LPENCR1_I2C3LPENC_Pos           (23U)
+#define RCC_APB1LPENCR1_I2C3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENCR1_I2C3LPENC               RCC_APB1LPENCR1_I2C3LPENC_Msk        /*!< I2C3 enable */
+#define RCC_APB1LPENCR1_I3C1LPENC_Pos           (24U)
+#define RCC_APB1LPENCR1_I3C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENCR1_I3C1LPENC               RCC_APB1LPENCR1_I3C1LPENC_Msk        /*!< I3C1 enable */
+#define RCC_APB1LPENCR1_I3C2LPENC_Pos           (25U)
+#define RCC_APB1LPENCR1_I3C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENCR1_I3C2LPENC               RCC_APB1LPENCR1_I3C2LPENC_Msk        /*!< I3C2 enable */
+#define RCC_APB1LPENCR1_UART7LPENC_Pos          (30U)
+#define RCC_APB1LPENCR1_UART7LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENCR1_UART7LPENC              RCC_APB1LPENCR1_UART7LPENC_Msk       /*!< UART7 enable */
+#define RCC_APB1LPENCR1_UART8LPENC_Pos          (31U)
+#define RCC_APB1LPENCR1_UART8LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENCR1_UART8LPENC              RCC_APB1LPENCR1_UART8LPENC_Msk       /*!< UART8 enable */
+
+/***************  Bit definition for RCC_APB1LPENCR2 register  ****************/
+#define RCC_APB1LPENCR2_MDIOSLPENC_Pos          (5U)
+#define RCC_APB1LPENCR2_MDIOSLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENCR2_MDIOSLPENC              RCC_APB1LPENCR2_MDIOSLPENC_Msk       /*!< MDIOS enable */
+#define RCC_APB1LPENCR2_FDCANLPENC_Pos          (8U)
+#define RCC_APB1LPENCR2_FDCANLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR2_FDCANLPENC              RCC_APB1LPENCR2_FDCANLPENC_Msk       /*!< FDCAN enable */
+#define RCC_APB1LPENCR2_UCPD1LPENC_Pos          (18U)
+#define RCC_APB1LPENCR2_UCPD1LPENC_Msk          (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENCR2_UCPD1LPENC              RCC_APB1LPENCR2_UCPD1LPENC_Msk       /*!< UCPD1 enable */
+
+/****************  Bit definition for RCC_APB2LPENCR register  ****************/
+#define RCC_APB2LPENCR_TIM1LPENC_Pos            (0U)
+#define RCC_APB2LPENCR_TIM1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENCR_TIM1LPENC                RCC_APB2LPENCR_TIM1LPENC_Msk         /*!< TIM1 enable */
+#define RCC_APB2LPENCR_TIM8LPENC_Pos            (1U)
+#define RCC_APB2LPENCR_TIM8LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENCR_TIM8LPENC                RCC_APB2LPENCR_TIM8LPENC_Msk         /*!< TIM8 enable */
+#define RCC_APB2LPENCR_USART1LPENC_Pos          (4U)
+#define RCC_APB2LPENCR_USART1LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENCR_USART1LPENC              RCC_APB2LPENCR_USART1LPENC_Msk       /*!< USART1 enable */
+#define RCC_APB2LPENCR_USART6LPENC_Pos          (5U)
+#define RCC_APB2LPENCR_USART6LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENCR_USART6LPENC              RCC_APB2LPENCR_USART6LPENC_Msk       /*!< USART6 enable */
+#define RCC_APB2LPENCR_UART9LPENC_Pos           (6U)
+#define RCC_APB2LPENCR_UART9LPENC_Msk           (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENCR_UART9LPENC               RCC_APB2LPENCR_UART9LPENC_Msk        /*!< UART9 enable */
+#define RCC_APB2LPENCR_USART10LPENC_Pos         (7U)
+#define RCC_APB2LPENCR_USART10LPENC_Msk         (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENCR_USART10LPENC             RCC_APB2LPENCR_USART10LPENC_Msk      /*!< USART10 enable */
+#define RCC_APB2LPENCR_SPI1LPENC_Pos            (12U)
+#define RCC_APB2LPENCR_SPI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENCR_SPI1LPENC                RCC_APB2LPENCR_SPI1LPENC_Msk         /*!< SPI1 enable */
+#define RCC_APB2LPENCR_SPI4LPENC_Pos            (13U)
+#define RCC_APB2LPENCR_SPI4LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENCR_SPI4LPENC                RCC_APB2LPENCR_SPI4LPENC_Msk         /*!< SPI4 enable */
+#define RCC_APB2LPENCR_TIM18LPENC_Pos           (15U)
+#define RCC_APB2LPENCR_TIM18LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENCR_TIM18LPENC               RCC_APB2LPENCR_TIM18LPENC_Msk        /*!< TIM18 enable */
+#define RCC_APB2LPENCR_TIM15LPENC_Pos           (16U)
+#define RCC_APB2LPENCR_TIM15LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENCR_TIM15LPENC               RCC_APB2LPENCR_TIM15LPENC_Msk        /*!< TIM15 enable */
+#define RCC_APB2LPENCR_TIM16LPENC_Pos           (17U)
+#define RCC_APB2LPENCR_TIM16LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENCR_TIM16LPENC               RCC_APB2LPENCR_TIM16LPENC_Msk        /*!< TIM16 enable */
+#define RCC_APB2LPENCR_TIM17LPENC_Pos           (18U)
+#define RCC_APB2LPENCR_TIM17LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENCR_TIM17LPENC               RCC_APB2LPENCR_TIM17LPENC_Msk        /*!< TIM17 enable */
+#define RCC_APB2LPENCR_TIM9LPENC_Pos            (19U)
+#define RCC_APB2LPENCR_TIM9LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENCR_TIM9LPENC                RCC_APB2LPENCR_TIM9LPENC_Msk         /*!< TIM9 enable */
+#define RCC_APB2LPENCR_SPI5LPENC_Pos            (20U)
+#define RCC_APB2LPENCR_SPI5LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENCR_SPI5LPENC                RCC_APB2LPENCR_SPI5LPENC_Msk         /*!< SPI5 enable */
+#define RCC_APB2LPENCR_SAI1LPENC_Pos            (21U)
+#define RCC_APB2LPENCR_SAI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENCR_SAI1LPENC                RCC_APB2LPENCR_SAI1LPENC_Msk         /*!< SAI1 enable */
+#define RCC_APB2LPENCR_SAI2LPENC_Pos            (22U)
+#define RCC_APB2LPENCR_SAI2LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENCR_SAI2LPENC                RCC_APB2LPENCR_SAI2LPENC_Msk         /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENCR register  ****************/
+#define RCC_APB3LPENCR_DFTLPENC_Pos             (2U)
+#define RCC_APB3LPENCR_DFTLPENC_Msk             (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENCR_DFTLPENC                 RCC_APB3LPENCR_DFTLPENC_Msk          /*!< DFT enable */
+
+/***************  Bit definition for RCC_APB4LPENCR1 register  ****************/
+#define RCC_APB4LPENCR1_HDPLPENC_Pos            (2U)
+#define RCC_APB4LPENCR1_HDPLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR1_HDPLPENC                RCC_APB4LPENCR1_HDPLPENC_Msk         /*!< HDP enable */
+#define RCC_APB4LPENCR1_LPUART1LPENC_Pos        (3U)
+#define RCC_APB4LPENCR1_LPUART1LPENC_Msk        (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENCR1_LPUART1LPENC            RCC_APB4LPENCR1_LPUART1LPENC_Msk     /*!< LPUART1 enable */
+#define RCC_APB4LPENCR1_SPI6LPENC_Pos           (5U)
+#define RCC_APB4LPENCR1_SPI6LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENCR1_SPI6LPENC               RCC_APB4LPENCR1_SPI6LPENC_Msk        /*!< SPI6 enable */
+#define RCC_APB4LPENCR1_I2C4LPENC_Pos           (7U)
+#define RCC_APB4LPENCR1_I2C4LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENCR1_I2C4LPENC               RCC_APB4LPENCR1_I2C4LPENC_Msk        /*!< I2C4 enable */
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos         (9U)
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENCR1_LPTIM2LPENC             RCC_APB4LPENCR1_LPTIM2LPENC_Msk      /*!< LPTIM2 enable */
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos         (10U)
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENCR1_LPTIM3LPENC             RCC_APB4LPENCR1_LPTIM3LPENC_Msk      /*!< LPTIM3 enable */
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos         (11U)
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENCR1_LPTIM4LPENC             RCC_APB4LPENCR1_LPTIM4LPENC_Msk      /*!< LPTIM4 enable */
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos         (12U)
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENCR1_LPTIM5LPENC             RCC_APB4LPENCR1_LPTIM5LPENC_Msk      /*!< LPTIM5 enable */
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos        (15U)
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk        (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENCR1_VREFBUFLPENC            RCC_APB4LPENCR1_VREFBUFLPENC_Msk     /*!< VREFBUF enable */
+#define RCC_APB4LPENCR1_RTCLPENC_Pos            (16U)
+#define RCC_APB4LPENCR1_RTCLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENCR1_RTCLPENC                RCC_APB4LPENCR1_RTCLPENC_Msk         /*!< RTC enable */
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos         (17U)
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk         (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENCR1_RTCAPBLPENC             RCC_APB4LPENCR1_RTCAPBLPENC_Msk      /*!< RTCAPB enable */
+
+/***************  Bit definition for RCC_APB4LPENCR2 register  ****************/
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos         (0U)
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk         (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENCR2_SYSCFGLPENC             RCC_APB4LPENCR2_SYSCFGLPENC_Msk      /*!< SYSCFG enable */
+#define RCC_APB4LPENCR2_BSECLPENC_Pos           (1U)
+#define RCC_APB4LPENCR2_BSECLPENC_Msk           (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENCR2_BSECLPENC               RCC_APB4LPENCR2_BSECLPENC_Msk        /*!< BSEC enable */
+#define RCC_APB4LPENCR2_DTSLPENC_Pos            (2U)
+#define RCC_APB4LPENCR2_DTSLPENC_Msk            (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR2_DTSLPENC                RCC_APB4LPENCR2_DTSLPENC_Msk         /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENCR register  ****************/
+#define RCC_APB5LPENCR_LTDCLPENC_Pos            (1U)
+#define RCC_APB5LPENCR_LTDCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENCR_LTDCLPENC                RCC_APB5LPENCR_LTDCLPENC_Msk         /*!< LTDC sleep enable */
+#define RCC_APB5LPENCR_DCMIPPLPENC_Pos          (2U)
+#define RCC_APB5LPENCR_DCMIPPLPENC_Msk          (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENCR_DCMIPPLPENC              RCC_APB5LPENCR_DCMIPPLPENC_Msk       /*!< DCMIPP sleep enable */
+#define RCC_APB5LPENCR_GFXTIMLPENC_Pos          (4U)
+#define RCC_APB5LPENCR_GFXTIMLPENC_Msk          (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENCR_GFXTIMLPENC              RCC_APB5LPENCR_GFXTIMLPENC_Msk       /*!< GFXTIM sleep enable */
+#define RCC_APB5LPENCR_VENCLPENC_Pos            (5U)
+#define RCC_APB5LPENCR_VENCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENCR_VENCLPENC                RCC_APB5LPENCR_VENCLPENC_Msk         /*!< VENC sleep enable */
+#define RCC_APB5LPENCR_CSILPENC_Pos             (6U)
+#define RCC_APB5LPENCR_CSILPENC_Msk             (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENCR_CSILPENC                 RCC_APB5LPENCR_CSILPENC_Msk          /*!< CSI sleep enable */
+
+/****************  Bit definition for RCC_PRIVCFGCR0 register  ****************/
+#define RCC_PRIVCFGCR0_LSIPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR0_LSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR0_LSIPRIVC                 RCC_PRIVCFGCR0_LSIPRIVC_Msk          /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_LSEPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR0_LSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR0_LSEPRIVC                 RCC_PRIVCFGCR0_LSEPRIVC_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_MSIPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR0_MSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR0_MSIPRIVC                 RCC_PRIVCFGCR0_MSIPRIVC_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSIPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR0_HSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR0_HSIPRIVC                 RCC_PRIVCFGCR0_HSIPRIVC_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSEPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR0_HSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR0_HSEPRIVC                 RCC_PRIVCFGCR0_HSEPRIVC_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR0 register  *****************/
+#define RCC_PUBCFGCR0_LSIPUBC_Pos               (0U)
+#define RCC_PUBCFGCR0_LSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR0_LSIPUBC                   RCC_PUBCFGCR0_LSIPUBC_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_LSEPUBC_Pos               (1U)
+#define RCC_PUBCFGCR0_LSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR0_LSEPUBC                   RCC_PUBCFGCR0_LSEPUBC_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_MSIPUBC_Pos               (2U)
+#define RCC_PUBCFGCR0_MSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR0_MSIPUBC                   RCC_PUBCFGCR0_MSIPUBC_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSIPUBC_Pos               (3U)
+#define RCC_PUBCFGCR0_HSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR0_HSIPUBC                   RCC_PUBCFGCR0_HSIPUBC_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSEPUBC_Pos               (4U)
+#define RCC_PUBCFGCR0_HSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR0_HSEPUBC                   RCC_PUBCFGCR0_HSEPUBC_Msk            /*!< Public protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR1 register  ****************/
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos            (0U)
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGCR1_PLL1PRIVC                RCC_PRIVCFGCR1_PLL1PRIVC_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos            (1U)
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGCR1_PLL2PRIVC                RCC_PRIVCFGCR1_PLL2PRIVC_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR1_PLL3PRIVC                RCC_PRIVCFGCR1_PLL3PRIVC_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR1_PLL4PRIVC                RCC_PRIVCFGCR1_PLL4PRIVC_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR1 register  *****************/
+#define RCC_PUBCFGCR1_PLL1PUBC_Pos              (0U)
+#define RCC_PUBCFGCR1_PLL1PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGCR1_PLL1PUBC                  RCC_PUBCFGCR1_PLL1PUBC_Msk           /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL2PUBC_Pos              (1U)
+#define RCC_PUBCFGCR1_PLL2PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR1_PLL2PUBC                  RCC_PUBCFGCR1_PLL2PUBC_Msk           /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL3PUBC_Pos              (2U)
+#define RCC_PUBCFGCR1_PLL3PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR1_PLL3PUBC                  RCC_PUBCFGCR1_PLL3PUBC_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL4PUBC_Pos              (3U)
+#define RCC_PUBCFGCR1_PLL4PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR1_PLL4PUBC                  RCC_PUBCFGCR1_PLL4PUBC_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR2 register  ****************/
+#define RCC_PRIVCFGCR2_IC1PRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR2_IC1PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR2_IC1PRIVC                 RCC_PRIVCFGCR2_IC1PRIVC_Msk          /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC2PRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR2_IC2PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR2_IC2PRIVC                 RCC_PRIVCFGCR2_IC2PRIVC_Msk          /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC3PRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR2_IC3PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR2_IC3PRIVC                 RCC_PRIVCFGCR2_IC3PRIVC_Msk          /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC4PRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR2_IC4PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR2_IC4PRIVC                 RCC_PRIVCFGCR2_IC4PRIVC_Msk          /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC5PRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR2_IC5PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR2_IC5PRIVC                 RCC_PRIVCFGCR2_IC5PRIVC_Msk          /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC6PRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR2_IC6PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR2_IC6PRIVC                 RCC_PRIVCFGCR2_IC6PRIVC_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC7PRIVC_Pos             (6U)
+#define RCC_PRIVCFGCR2_IC7PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGCR2_IC7PRIVC                 RCC_PRIVCFGCR2_IC7PRIVC_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC8PRIVC_Pos             (7U)
+#define RCC_PRIVCFGCR2_IC8PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGCR2_IC8PRIVC                 RCC_PRIVCFGCR2_IC8PRIVC_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC9PRIVC_Pos             (8U)
+#define RCC_PRIVCFGCR2_IC9PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGCR2_IC9PRIVC                 RCC_PRIVCFGCR2_IC9PRIVC_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC10PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR2_IC10PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR2_IC10PRIVC                RCC_PRIVCFGCR2_IC10PRIVC_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC11PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR2_IC11PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR2_IC11PRIVC                RCC_PRIVCFGCR2_IC11PRIVC_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC12PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR2_IC12PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR2_IC12PRIVC                RCC_PRIVCFGCR2_IC12PRIVC_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC13PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR2_IC13PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR2_IC13PRIVC                RCC_PRIVCFGCR2_IC13PRIVC_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC14PRIVC_Pos            (13U)
+#define RCC_PRIVCFGCR2_IC14PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGCR2_IC14PRIVC                RCC_PRIVCFGCR2_IC14PRIVC_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC15PRIVC_Pos            (14U)
+#define RCC_PRIVCFGCR2_IC15PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGCR2_IC15PRIVC                RCC_PRIVCFGCR2_IC15PRIVC_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC16PRIVC_Pos            (15U)
+#define RCC_PRIVCFGCR2_IC16PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGCR2_IC16PRIVC                RCC_PRIVCFGCR2_IC16PRIVC_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC17PRIVC_Pos            (16U)
+#define RCC_PRIVCFGCR2_IC17PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGCR2_IC17PRIVC                RCC_PRIVCFGCR2_IC17PRIVC_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC18PRIVC_Pos            (17U)
+#define RCC_PRIVCFGCR2_IC18PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGCR2_IC18PRIVC                RCC_PRIVCFGCR2_IC18PRIVC_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC19PRIVC_Pos            (18U)
+#define RCC_PRIVCFGCR2_IC19PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGCR2_IC19PRIVC                RCC_PRIVCFGCR2_IC19PRIVC_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC20PRIVC_Pos            (19U)
+#define RCC_PRIVCFGCR2_IC20PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGCR2_IC20PRIVC                RCC_PRIVCFGCR2_IC20PRIVC_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR2 register  *****************/
+#define RCC_PUBCFGCR2_IC1PUBC_Pos               (0U)
+#define RCC_PUBCFGCR2_IC1PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR2_IC1PUBC                   RCC_PUBCFGCR2_IC1PUBC_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC2PUBC_Pos               (1U)
+#define RCC_PUBCFGCR2_IC2PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR2_IC2PUBC                   RCC_PUBCFGCR2_IC2PUBC_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC3PUBC_Pos               (2U)
+#define RCC_PUBCFGCR2_IC3PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR2_IC3PUBC                   RCC_PUBCFGCR2_IC3PUBC_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC4PUBC_Pos               (3U)
+#define RCC_PUBCFGCR2_IC4PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR2_IC4PUBC                   RCC_PUBCFGCR2_IC4PUBC_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC5PUBC_Pos               (4U)
+#define RCC_PUBCFGCR2_IC5PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR2_IC5PUBC                   RCC_PUBCFGCR2_IC5PUBC_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC6PUBC_Pos               (5U)
+#define RCC_PUBCFGCR2_IC6PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR2_IC6PUBC                   RCC_PUBCFGCR2_IC6PUBC_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC7PUBC_Pos               (6U)
+#define RCC_PUBCFGCR2_IC7PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR2_IC7PUBC                   RCC_PUBCFGCR2_IC7PUBC_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC8PUBC_Pos               (7U)
+#define RCC_PUBCFGCR2_IC8PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGCR2_IC8PUBC                   RCC_PUBCFGCR2_IC8PUBC_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC9PUBC_Pos               (8U)
+#define RCC_PUBCFGCR2_IC9PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGCR2_IC9PUBC                   RCC_PUBCFGCR2_IC9PUBC_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC10PUBC_Pos              (9U)
+#define RCC_PUBCFGCR2_IC10PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR2_IC10PUBC                  RCC_PUBCFGCR2_IC10PUBC_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC11PUBC_Pos              (10U)
+#define RCC_PUBCFGCR2_IC11PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR2_IC11PUBC                  RCC_PUBCFGCR2_IC11PUBC_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC12PUBC_Pos              (11U)
+#define RCC_PUBCFGCR2_IC12PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR2_IC12PUBC                  RCC_PUBCFGCR2_IC12PUBC_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC13PUBC_Pos              (12U)
+#define RCC_PUBCFGCR2_IC13PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR2_IC13PUBC                  RCC_PUBCFGCR2_IC13PUBC_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC14PUBC_Pos              (13U)
+#define RCC_PUBCFGCR2_IC14PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGCR2_IC14PUBC                  RCC_PUBCFGCR2_IC14PUBC_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC15PUBC_Pos              (14U)
+#define RCC_PUBCFGCR2_IC15PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGCR2_IC15PUBC                  RCC_PUBCFGCR2_IC15PUBC_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC16PUBC_Pos              (15U)
+#define RCC_PUBCFGCR2_IC16PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGCR2_IC16PUBC                  RCC_PUBCFGCR2_IC16PUBC_Msk           /*!< Public protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC17PUBC_Pos              (16U)
+#define RCC_PUBCFGCR2_IC17PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGCR2_IC17PUBC                  RCC_PUBCFGCR2_IC17PUBC_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC18PUBC_Pos              (17U)
+#define RCC_PUBCFGCR2_IC18PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGCR2_IC18PUBC                  RCC_PUBCFGCR2_IC18PUBC_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC19PUBC_Pos              (18U)
+#define RCC_PUBCFGCR2_IC19PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGCR2_IC19PUBC                  RCC_PUBCFGCR2_IC19PUBC_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC20PUBC_Pos              (19U)
+#define RCC_PUBCFGCR2_IC20PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGCR2_IC20PUBC                  RCC_PUBCFGCR2_IC20PUBC_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR3 register  ****************/
+#define RCC_PRIVCFGCR3_MODPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR3_MODPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR3_MODPRIVC                 RCC_PRIVCFGCR3_MODPRIVC_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_SYSPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR3_SYSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR3_SYSPRIVC                 RCC_PRIVCFGCR3_SYSPRIVC_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_BUSPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR3_BUSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR3_BUSPRIVC                 RCC_PRIVCFGCR3_BUSPRIVC_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_PERPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR3_PERPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR3_PERPRIVC                 RCC_PRIVCFGCR3_PERPRIVC_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_INTPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR3_INTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR3_INTPRIVC                 RCC_PRIVCFGCR3_INTPRIVC_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_RSTPRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR3_RSTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR3_RSTPRIVC                 RCC_PRIVCFGCR3_RSTPRIVC_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR3 register  *****************/
+#define RCC_PUBCFGCR3_MODPUBC_Pos               (0U)
+#define RCC_PUBCFGCR3_MODPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR3_MODPUBC                   RCC_PUBCFGCR3_MODPUBC_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_SYSPUBC_Pos               (1U)
+#define RCC_PUBCFGCR3_SYSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR3_SYSPUBC                   RCC_PUBCFGCR3_SYSPUBC_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_BUSPUBC_Pos               (2U)
+#define RCC_PUBCFGCR3_BUSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR3_BUSPUBC                   RCC_PUBCFGCR3_BUSPUBC_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_PERPUBC_Pos               (3U)
+#define RCC_PUBCFGCR3_PERPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR3_PERPUBC                   RCC_PUBCFGCR3_PERPUBC_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_INTPUBC_Pos               (4U)
+#define RCC_PUBCFGCR3_INTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR3_INTPUBC                   RCC_PUBCFGCR3_INTPUBC_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_RSTPUBC_Pos               (5U)
+#define RCC_PUBCFGCR3_RSTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR3_RSTPUBC                   RCC_PUBCFGCR3_RSTPUBC_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR4 register  ****************/
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos           (0U)
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk           (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGCR4_ACLKNPRIVC               RCC_PRIVCFGCR4_ACLKNPRIVC_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos          (1U)
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk          (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC              RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk       /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR4_AHBMPRIVC                RCC_PRIVCFGCR4_AHBMPRIVC_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR4_AHB1PRIVC                RCC_PRIVCFGCR4_AHB1PRIVC_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos            (4U)
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGCR4_AHB2PRIVC                RCC_PRIVCFGCR4_AHB2PRIVC_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos            (5U)
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGCR4_AHB3PRIVC                RCC_PRIVCFGCR4_AHB3PRIVC_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos            (6U)
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGCR4_AHB4PRIVC                RCC_PRIVCFGCR4_AHB4PRIVC_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos            (7U)
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGCR4_AHB5PRIVC                RCC_PRIVCFGCR4_AHB5PRIVC_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB1PRIVC_Pos            (8U)
+#define RCC_PRIVCFGCR4_APB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGCR4_APB1PRIVC                RCC_PRIVCFGCR4_APB1PRIVC_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB2PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR4_APB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR4_APB2PRIVC                RCC_PRIVCFGCR4_APB2PRIVC_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB3PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR4_APB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR4_APB3PRIVC                RCC_PRIVCFGCR4_APB3PRIVC_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB4PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR4_APB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR4_APB4PRIVC                RCC_PRIVCFGCR4_APB4PRIVC_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB5PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR4_APB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR4_APB5PRIVC                RCC_PRIVCFGCR4_APB5PRIVC_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_NOCPRIVC_Pos             (13U)
+#define RCC_PRIVCFGCR4_NOCPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGCR4_NOCPRIVC                 RCC_PRIVCFGCR4_NOCPRIVC_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR4 register  *****************/
+#define RCC_PUBCFGCR4_ACLKNPUBC_Pos             (0U)
+#define RCC_PUBCFGCR4_ACLKNPUBC_Msk             (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGCR4_ACLKNPUBC                 RCC_PUBCFGCR4_ACLKNPUBC_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos            (1U)
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk            (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR4_ACLKNCPUBC                RCC_PUBCFGCR4_ACLKNCPUBC_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHBMPUBC_Pos              (2U)
+#define RCC_PUBCFGCR4_AHBMPUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR4_AHBMPUBC                  RCC_PUBCFGCR4_AHBMPUBC_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB1PUBC_Pos              (3U)
+#define RCC_PUBCFGCR4_AHB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR4_AHB1PUBC                  RCC_PUBCFGCR4_AHB1PUBC_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB2PUBC_Pos              (4U)
+#define RCC_PUBCFGCR4_AHB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGCR4_AHB2PUBC                  RCC_PUBCFGCR4_AHB2PUBC_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB3PUBC_Pos              (5U)
+#define RCC_PUBCFGCR4_AHB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGCR4_AHB3PUBC                  RCC_PUBCFGCR4_AHB3PUBC_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB4PUBC_Pos              (6U)
+#define RCC_PUBCFGCR4_AHB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGCR4_AHB4PUBC                  RCC_PUBCFGCR4_AHB4PUBC_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB5PUBC_Pos              (7U)
+#define RCC_PUBCFGCR4_AHB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGCR4_AHB5PUBC                  RCC_PUBCFGCR4_AHB5PUBC_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB1PUBC_Pos              (8U)
+#define RCC_PUBCFGCR4_APB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGCR4_APB1PUBC                  RCC_PUBCFGCR4_APB1PUBC_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB2PUBC_Pos              (9U)
+#define RCC_PUBCFGCR4_APB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR4_APB2PUBC                  RCC_PUBCFGCR4_APB2PUBC_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB3PUBC_Pos              (10U)
+#define RCC_PUBCFGCR4_APB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR4_APB3PUBC                  RCC_PUBCFGCR4_APB3PUBC_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB4PUBC_Pos              (11U)
+#define RCC_PUBCFGCR4_APB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR4_APB4PUBC                  RCC_PUBCFGCR4_APB4PUBC_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB5PUBC_Pos              (12U)
+#define RCC_PUBCFGCR4_APB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR4_APB5PUBC                  RCC_PUBCFGCR4_APB5PUBC_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_NOCPUBC_Pos               (13U)
+#define RCC_PUBCFGCR4_NOCPUBC_Msk               (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGCR4_NOCPUBC                   RCC_PUBCFGCR4_NOCPUBC_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR5 register  *****************/
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos          (0U)
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGCR5_AXISRAM3PUBC              RCC_PUBCFGCR5_AXISRAM3PUBC_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos          (1U)
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC              RCC_PUBCFGCR5_AXISRAM4PUBC_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos          (2U)
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC              RCC_PUBCFGCR5_AXISRAM5PUBC_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos          (3U)
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC              RCC_PUBCFGCR5_AXISRAM6PUBC_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos          (4U)
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC              RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos          (5U)
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC              RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos           (6U)
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC               RCC_PUBCFGCR5_BKPSRAMPUBC_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos          (7U)
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC              RCC_PUBCFGCR5_AXISRAM1PUBC_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos          (8U)
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC              RCC_PUBCFGCR5_AXISRAM2PUBC_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos           (9U)
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC               RCC_PUBCFGCR5_FLEXRAMPUBC_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos       (10U)
+#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk       (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos)      /*!< 0x00000400 */
+#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC           RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk    /*!< Public protection of CACHEAXIRAM configuration bits  */
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos           (11U)
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGCR5_VENCRAMPUBC               RCC_PUBCFGCR5_VENCRAMPUBC_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*          Resource Isolation Framework Security Controller (RIFSC)          */
+/*                                                                            */
+/******************************************************************************/
+/****************  Bit definition for RIFSC_RISC_CR register  *****************/
+#define RIFSC_RISC_CR_GLOCK_Pos             (0UL)
+#define RIFSC_RISC_CR_GLOCK_Msk             (0x1UL << RIFSC_RISC_CR_GLOCK_Pos)             /*!< 0x00000001 */
+#define RIFSC_RISC_CR_GLOCK                 RIFSC_RISC_CR_GLOCK_Msk                        /*!< Global lock */
+
+/*************  Bit definition for RIFSC_RISC_SECCFGRx register  **************/
+#define RIFSC_RISC_SECCFGRx_SEC0_Pos        (0U)
+#define RIFSC_RISC_SECCFGRx_SEC0_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos)         /*!< 0x00000001 */
+#define RIFSC_RISC_SECCFGRx_SEC0            RIFSC_RISC_SECCFGRx_SEC0_Msk                   /*!< Security configuration for peripheral 0 */
+#define RIFSC_RISC_SECCFGRx_SEC1_Pos        (1U)
+#define RIFSC_RISC_SECCFGRx_SEC1_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos)         /*!< 0x00000002 */
+#define RIFSC_RISC_SECCFGRx_SEC1            RIFSC_RISC_SECCFGRx_SEC1_Msk                   /*!< Security configuration for peripheral 1 */
+#define RIFSC_RISC_SECCFGRx_SEC2_Pos        (2U)
+#define RIFSC_RISC_SECCFGRx_SEC2_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos)         /*!< 0x00000004 */
+#define RIFSC_RISC_SECCFGRx_SEC2            RIFSC_RISC_SECCFGRx_SEC2_Msk                   /*!< Security configuration for peripheral 2 */
+#define RIFSC_RISC_SECCFGRx_SEC3_Pos        (3U)
+#define RIFSC_RISC_SECCFGRx_SEC3_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos)         /*!< 0x00000008 */
+#define RIFSC_RISC_SECCFGRx_SEC3            RIFSC_RISC_SECCFGRx_SEC3_Msk                   /*!< Security configuration for peripheral 3 */
+#define RIFSC_RISC_SECCFGRx_SEC4_Pos        (4U)
+#define RIFSC_RISC_SECCFGRx_SEC4_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos)         /*!< 0x00000010 */
+#define RIFSC_RISC_SECCFGRx_SEC4            RIFSC_RISC_SECCFGRx_SEC4_Msk                   /*!< Security configuration for peripheral 4 */
+#define RIFSC_RISC_SECCFGRx_SEC5_Pos        (5U)
+#define RIFSC_RISC_SECCFGRx_SEC5_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos)         /*!< 0x00000020 */
+#define RIFSC_RISC_SECCFGRx_SEC5            RIFSC_RISC_SECCFGRx_SEC5_Msk                   /*!< Security configuration for peripheral 5 */
+#define RIFSC_RISC_SECCFGRx_SEC6_Pos        (6U)
+#define RIFSC_RISC_SECCFGRx_SEC6_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos)         /*!< 0x00000040 */
+#define RIFSC_RISC_SECCFGRx_SEC6            RIFSC_RISC_SECCFGRx_SEC6_Msk                   /*!< Security configuration for peripheral 6 */
+#define RIFSC_RISC_SECCFGRx_SEC7_Pos        (7U)
+#define RIFSC_RISC_SECCFGRx_SEC7_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos)         /*!< 0x00000080 */
+#define RIFSC_RISC_SECCFGRx_SEC7            RIFSC_RISC_SECCFGRx_SEC7_Msk                   /*!< Security configuration for peripheral 7 */
+#define RIFSC_RISC_SECCFGRx_SEC8_Pos        (8U)
+#define RIFSC_RISC_SECCFGRx_SEC8_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos)         /*!< 0x00000100 */
+#define RIFSC_RISC_SECCFGRx_SEC8            RIFSC_RISC_SECCFGRx_SEC8_Msk                   /*!< Security configuration for peripheral 8 */
+#define RIFSC_RISC_SECCFGRx_SEC9_Pos        (9U)
+#define RIFSC_RISC_SECCFGRx_SEC9_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos)         /*!< 0x00000200 */
+#define RIFSC_RISC_SECCFGRx_SEC9            RIFSC_RISC_SECCFGRx_SEC9_Msk                   /*!< Security configuration for peripheral 9 */
+#define RIFSC_RISC_SECCFGRx_SEC10_Pos       (10U)
+#define RIFSC_RISC_SECCFGRx_SEC10_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos)        /*!< 0x00000400 */
+#define RIFSC_RISC_SECCFGRx_SEC10           RIFSC_RISC_SECCFGRx_SEC10_Msk                  /*!< Security configuration for peripheral 10 */
+#define RIFSC_RISC_SECCFGRx_SEC11_Pos       (11U)
+#define RIFSC_RISC_SECCFGRx_SEC11_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos)        /*!< 0x00000800 */
+#define RIFSC_RISC_SECCFGRx_SEC11           RIFSC_RISC_SECCFGRx_SEC11_Msk                  /*!< Security configuration for peripheral 11 */
+#define RIFSC_RISC_SECCFGRx_SEC12_Pos       (12U)
+#define RIFSC_RISC_SECCFGRx_SEC12_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos)        /*!< 0x00001000 */
+#define RIFSC_RISC_SECCFGRx_SEC12           RIFSC_RISC_SECCFGRx_SEC12_Msk                  /*!< Security configuration for peripheral 12 */
+#define RIFSC_RISC_SECCFGRx_SEC13_Pos       (13U)
+#define RIFSC_RISC_SECCFGRx_SEC13_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos)        /*!< 0x00002000 */
+#define RIFSC_RISC_SECCFGRx_SEC13           RIFSC_RISC_SECCFGRx_SEC13_Msk                  /*!< Security configuration for peripheral 13 */
+#define RIFSC_RISC_SECCFGRx_SEC14_Pos       (14U)
+#define RIFSC_RISC_SECCFGRx_SEC14_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos)        /*!< 0x00004000 */
+#define RIFSC_RISC_SECCFGRx_SEC14           RIFSC_RISC_SECCFGRx_SEC14_Msk                  /*!< Security configuration for peripheral 14 */
+#define RIFSC_RISC_SECCFGRx_SEC15_Pos       (15U)
+#define RIFSC_RISC_SECCFGRx_SEC15_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos)        /*!< 0x00008000 */
+#define RIFSC_RISC_SECCFGRx_SEC15           RIFSC_RISC_SECCFGRx_SEC15_Msk                  /*!< Security configuration for peripheral 15 */
+#define RIFSC_RISC_SECCFGRx_SEC16_Pos       (16U)
+#define RIFSC_RISC_SECCFGRx_SEC16_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos)        /*!< 0x00010000 */
+#define RIFSC_RISC_SECCFGRx_SEC16           RIFSC_RISC_SECCFGRx_SEC16_Msk                  /*!< Security configuration for peripheral 16 */
+#define RIFSC_RISC_SECCFGRx_SEC17_Pos       (17U)
+#define RIFSC_RISC_SECCFGRx_SEC17_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos)        /*!< 0x00020000 */
+#define RIFSC_RISC_SECCFGRx_SEC17           RIFSC_RISC_SECCFGRx_SEC17_Msk                  /*!< Security configuration for peripheral 17 */
+#define RIFSC_RISC_SECCFGRx_SEC18_Pos       (18U)
+#define RIFSC_RISC_SECCFGRx_SEC18_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos)        /*!< 0x00040000 */
+#define RIFSC_RISC_SECCFGRx_SEC18           RIFSC_RISC_SECCFGRx_SEC18_Msk                  /*!< Security configuration for peripheral 18 */
+#define RIFSC_RISC_SECCFGRx_SEC19_Pos       (19U)
+#define RIFSC_RISC_SECCFGRx_SEC19_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos)        /*!< 0x00080000 */
+#define RIFSC_RISC_SECCFGRx_SEC19           RIFSC_RISC_SECCFGRx_SEC19_Msk                  /*!< Security configuration for peripheral 19 */
+#define RIFSC_RISC_SECCFGRx_SEC20_Pos       (20U)
+#define RIFSC_RISC_SECCFGRx_SEC20_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos)        /*!< 0x00100000 */
+#define RIFSC_RISC_SECCFGRx_SEC20           RIFSC_RISC_SECCFGRx_SEC20_Msk                  /*!< Security configuration for peripheral 20 */
+#define RIFSC_RISC_SECCFGRx_SEC21_Pos       (21U)
+#define RIFSC_RISC_SECCFGRx_SEC21_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos)        /*!< 0x00200000 */
+#define RIFSC_RISC_SECCFGRx_SEC21           RIFSC_RISC_SECCFGRx_SEC21_Msk                  /*!< Security configuration for peripheral 21 */
+#define RIFSC_RISC_SECCFGRx_SEC22_Pos       (22U)
+#define RIFSC_RISC_SECCFGRx_SEC22_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos)        /*!< 0x00400000 */
+#define RIFSC_RISC_SECCFGRx_SEC22           RIFSC_RISC_SECCFGRx_SEC22_Msk                  /*!< Security configuration for peripheral 22 */
+#define RIFSC_RISC_SECCFGRx_SEC23_Pos       (23U)
+#define RIFSC_RISC_SECCFGRx_SEC23_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos)        /*!< 0x00800000 */
+#define RIFSC_RISC_SECCFGRx_SEC23           RIFSC_RISC_SECCFGRx_SEC23_Msk                  /*!< Security configuration for peripheral 23 */
+#define RIFSC_RISC_SECCFGRx_SEC24_Pos       (24U)
+#define RIFSC_RISC_SECCFGRx_SEC24_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos)        /*!< 0x01000000 */
+#define RIFSC_RISC_SECCFGRx_SEC24           RIFSC_RISC_SECCFGRx_SEC24_Msk                  /*!< Security configuration for peripheral 24 */
+#define RIFSC_RISC_SECCFGRx_SEC25_Pos       (25U)
+#define RIFSC_RISC_SECCFGRx_SEC25_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos)        /*!< 0x02000000 */
+#define RIFSC_RISC_SECCFGRx_SEC25           RIFSC_RISC_SECCFGRx_SEC25_Msk                  /*!< Security configuration for peripheral 25 */
+#define RIFSC_RISC_SECCFGRx_SEC26_Pos       (26U)
+#define RIFSC_RISC_SECCFGRx_SEC26_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos)        /*!< 0x04000000 */
+#define RIFSC_RISC_SECCFGRx_SEC26           RIFSC_RISC_SECCFGRx_SEC26_Msk                  /*!< Security configuration for peripheral 26 */
+#define RIFSC_RISC_SECCFGRx_SEC27_Pos       (27U)
+#define RIFSC_RISC_SECCFGRx_SEC27_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos)        /*!< 0x08000000 */
+#define RIFSC_RISC_SECCFGRx_SEC27           RIFSC_RISC_SECCFGRx_SEC27_Msk                  /*!< Security configuration for peripheral 27 */
+#define RIFSC_RISC_SECCFGRx_SEC28_Pos       (28U)
+#define RIFSC_RISC_SECCFGRx_SEC28_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos)        /*!< 0x10000000 */
+#define RIFSC_RISC_SECCFGRx_SEC28           RIFSC_RISC_SECCFGRx_SEC28_Msk                  /*!< Security configuration for peripheral 28 */
+#define RIFSC_RISC_SECCFGRx_SEC29_Pos       (29U)
+#define RIFSC_RISC_SECCFGRx_SEC29_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos)        /*!< 0x20000000 */
+#define RIFSC_RISC_SECCFGRx_SEC29           RIFSC_RISC_SECCFGRx_SEC29_Msk                  /*!< Security configuration for peripheral 29 */
+#define RIFSC_RISC_SECCFGRx_SEC30_Pos       (30U)
+#define RIFSC_RISC_SECCFGRx_SEC30_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos)        /*!< 0x40000000 */
+#define RIFSC_RISC_SECCFGRx_SEC30           RIFSC_RISC_SECCFGRx_SEC30_Msk                  /*!< Security configuration for peripheral 30 */
+#define RIFSC_RISC_SECCFGRx_SEC31_Pos       (31U)
+#define RIFSC_RISC_SECCFGRx_SEC31_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos)        /*!< 0x80000000 */
+#define RIFSC_RISC_SECCFGRx_SEC31           RIFSC_RISC_SECCFGRx_SEC31_Msk                  /*!< Security configuration for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_PRIVCFGRx register  *************/
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos      (0U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos)       /*!< 0x00000001 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV0          RIFSC_RISC_PRIVCFGRx_PRIV0_Msk                 /*!< privileged-only access permission for peripheral 0 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos      (1U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos)       /*!< 0x00000002 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1          RIFSC_RISC_PRIVCFGRx_PRIV1_Msk                 /*!< privileged-only access permission for peripheral 1 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos      (2U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos)       /*!< 0x00000004 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2          RIFSC_RISC_PRIVCFGRx_PRIV2_Msk                 /*!< privileged-only access permission for peripheral 2 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos      (3U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos)       /*!< 0x00000008 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3          RIFSC_RISC_PRIVCFGRx_PRIV3_Msk                 /*!< privileged-only access permission for peripheral 3 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos      (4U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos)       /*!< 0x00000010 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4          RIFSC_RISC_PRIVCFGRx_PRIV4_Msk                 /*!< privileged-only access permission for peripheral 4 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos      (5U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos)       /*!< 0x00000020 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5          RIFSC_RISC_PRIVCFGRx_PRIV5_Msk                 /*!< privileged-only access permission for peripheral 5 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos      (6U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos)       /*!< 0x00000040 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6          RIFSC_RISC_PRIVCFGRx_PRIV6_Msk                 /*!< privileged-only access permission for peripheral 6 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos      (7U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos)       /*!< 0x00000080 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7          RIFSC_RISC_PRIVCFGRx_PRIV7_Msk                 /*!< privileged-only access permission for peripheral 7 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos      (8U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos)       /*!< 0x00000100 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8          RIFSC_RISC_PRIVCFGRx_PRIV8_Msk                 /*!< privileged-only access permission for peripheral 8 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos      (9U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos)       /*!< 0x00000200 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9          RIFSC_RISC_PRIVCFGRx_PRIV9_Msk                 /*!< privileged-only access permission for peripheral 9 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos     (10U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos)      /*!< 0x00000400 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10         RIFSC_RISC_PRIVCFGRx_PRIV10_Msk                /*!< privileged-only access permission for peripheral 10 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos     (11U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos)      /*!< 0x00000800 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11         RIFSC_RISC_PRIVCFGRx_PRIV11_Msk                /*!< privileged-only access permission for peripheral 11 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos     (12U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos)      /*!< 0x00001000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12         RIFSC_RISC_PRIVCFGRx_PRIV12_Msk                /*!< privileged-only access permission for peripheral 12 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos     (13U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos)      /*!< 0x00002000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13         RIFSC_RISC_PRIVCFGRx_PRIV13_Msk                /*!< privileged-only access permission for peripheral 13 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos     (14U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos)      /*!< 0x00004000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14         RIFSC_RISC_PRIVCFGRx_PRIV14_Msk                /*!< privileged-only access permission for peripheral 14 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos     (15U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos)      /*!< 0x00008000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15         RIFSC_RISC_PRIVCFGRx_PRIV15_Msk                /*!< privileged-only access permission for peripheral 15 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos     (16U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos)      /*!< 0x00010000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16         RIFSC_RISC_PRIVCFGRx_PRIV16_Msk                /*!< privileged-only access permission for peripheral 16 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos     (17U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos)      /*!< 0x00020000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17         RIFSC_RISC_PRIVCFGRx_PRIV17_Msk                /*!< privileged-only access permission for peripheral 17 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos     (18U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos)      /*!< 0x00040000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18         RIFSC_RISC_PRIVCFGRx_PRIV18_Msk                /*!< privileged-only access permission for peripheral 18 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos     (19U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos)      /*!< 0x00080000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19         RIFSC_RISC_PRIVCFGRx_PRIV19_Msk                /*!< privileged-only access permission for peripheral 19 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos     (20U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos)      /*!< 0x00100000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20         RIFSC_RISC_PRIVCFGRx_PRIV20_Msk                /*!< privileged-only access permission for peripheral 20 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos     (21U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos)      /*!< 0x00200000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21         RIFSC_RISC_PRIVCFGRx_PRIV21_Msk                /*!< privileged-only access permission for peripheral 21 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos     (22U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos)      /*!< 0x00400000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22         RIFSC_RISC_PRIVCFGRx_PRIV22_Msk                /*!< privileged-only access permission for peripheral 22 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos     (23U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos)      /*!< 0x00800000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23         RIFSC_RISC_PRIVCFGRx_PRIV23_Msk                /*!< privileged-only access permission for peripheral 23 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos     (24U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos)      /*!< 0x01000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24         RIFSC_RISC_PRIVCFGRx_PRIV24_Msk                /*!< privileged-only access permission for peripheral 24 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos     (25U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos)      /*!< 0x02000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25         RIFSC_RISC_PRIVCFGRx_PRIV25_Msk                /*!< privileged-only access permission for peripheral 25 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos     (26U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos)      /*!< 0x04000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26         RIFSC_RISC_PRIVCFGRx_PRIV26_Msk                /*!< privileged-only access permission for peripheral 26 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos     (27U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos)      /*!< 0x08000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27         RIFSC_RISC_PRIVCFGRx_PRIV27_Msk                /*!< privileged-only access permission for peripheral 27 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos     (28U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos)      /*!< 0x10000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28         RIFSC_RISC_PRIVCFGRx_PRIV28_Msk                /*!< privileged-only access permission for peripheral 28 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos     (29U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos)      /*!< 0x20000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29         RIFSC_RISC_PRIVCFGRx_PRIV29_Msk                /*!< privileged-only access permission for peripheral 29 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos     (30U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos)      /*!< 0x40000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30         RIFSC_RISC_PRIVCFGRx_PRIV30_Msk                /*!< privileged-only access permission for peripheral 30 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos     (31U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos)      /*!< 0x80000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31         RIFSC_RISC_PRIVCFGRx_PRIV31_Msk                /*!< privileged-only access permission for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_RCFGLOCKRx register  *************/
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos    (0U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos)     /*!< 0x00000001 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0        RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk               /*!< Resource lock for peripheral 0 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos    (1U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos)     /*!< 0x00000002 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1        RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk               /*!< Resource lock for peripheral 1 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos    (2U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos)     /*!< 0x00000004 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2        RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk               /*!< Resource lock for peripheral 2 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos    (3U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos)     /*!< 0x00000008 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3        RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk               /*!< Resource lock for peripheral 3 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos    (4U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos)     /*!< 0x00000010 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4        RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk               /*!< Resource lock for peripheral 4 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos    (5U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos)     /*!< 0x00000020 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5        RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk               /*!< Resource lock for peripheral 5 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos    (6U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos)     /*!< 0x00000040 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6        RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk               /*!< Resource lock for peripheral 6 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos    (7U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos)     /*!< 0x00000080 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7        RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk               /*!< Resource lock for peripheral 7 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos    (8U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos)     /*!< 0x00000100 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8        RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk               /*!< Resource lock for peripheral 8 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos    (9U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos)     /*!< 0x00000200 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9        RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk               /*!< Resource lock for peripheral 9 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos   (10U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos)    /*!< 0x00000400 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10       RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk              /*!< Resource lock for peripheral 10 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos   (11U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos)    /*!< 0x00000800 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11       RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk              /*!< Resource lock for peripheral 11 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos   (12U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos)    /*!< 0x00001000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12       RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk              /*!< Resource lock for peripheral 12 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos   (13U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos)    /*!< 0x00002000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13       RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk              /*!< Resource lock for peripheral 13 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos   (14U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos)    /*!< 0x00004000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14       RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk              /*!< Resource lock for peripheral 14 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos   (15U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos)    /*!< 0x00008000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15       RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk              /*!< Resource lock for peripheral 15 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos   (16U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos)    /*!< 0x00010000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16       RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk              /*!< Resource lock for peripheral 16 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos   (17U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos)    /*!< 0x00020000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17       RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk              /*!< Resource lock for peripheral 17 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos   (18U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos)    /*!< 0x00040000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18       RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk              /*!< Resource lock for peripheral 18 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos   (19U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos)    /*!< 0x00080000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19       RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk              /*!< Resource lock for peripheral 19 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos   (20U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos)    /*!< 0x00100000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20       RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk              /*!< Resource lock for peripheral 20 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos   (21U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos)    /*!< 0x00200000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21       RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk              /*!< Resource lock for peripheral 21 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos   (22U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos)    /*!< 0x00400000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22       RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk              /*!< Resource lock for peripheral 22 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos   (23U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos)    /*!< 0x00800000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23       RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk              /*!< Resource lock for peripheral 23 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos   (24U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos)    /*!< 0x01000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24       RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk              /*!< Resource lock for peripheral 24 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos   (25U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos)    /*!< 0x02000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25       RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk              /*!< Resource lock for peripheral 25 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos   (26U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos)    /*!< 0x04000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26       RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk              /*!< Resource lock for peripheral 26 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos   (27U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos)    /*!< 0x08000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27       RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk              /*!< Resource lock for peripheral 27 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos   (28U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos)    /*!< 0x10000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28       RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk              /*!< Resource lock for peripheral 28 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos   (29U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos)    /*!< 0x20000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29       RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk              /*!< Resource lock for peripheral 29 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos   (30U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos)    /*!< 0x40000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30       RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk              /*!< Resource lock for peripheral 30 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos   (31U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos)    /*!< 0x80000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31       RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk              /*!< Resource lock for peripheral 31 */
+
+/****************  Bit definition for RIFSC_RIMC_CR register  *****************/
+#define RIFSC_RIMC_CR_GLOCK_Pos             (0U)
+#define RIFSC_RIMC_CR_GLOCK_Msk             (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos)              /*!< 0x00000001 */
+#define RIFSC_RIMC_CR_GLOCK                 RIFSC_RIMC_CR_GLOCK_Msk                        /*!< Global lock */
+#define RIFSC_RIMC_CR_DAPCID_Pos            (8U)
+#define RIFSC_RIMC_CR_DAPCID_Msk            (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000700 */
+#define RIFSC_RIMC_CR_DAPCID                RIFSC_RIMC_CR_DAPCID_Msk                       /*!< Debug access port compartment ID */
+#define RIFSC_RIMC_CR_DAPCID_0              (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000100 */
+#define RIFSC_RIMC_CR_DAPCID_1              (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000200 */
+#define RIFSC_RIMC_CR_DAPCID_2              (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000400 */
+
+/***************  Bit definition for RIFSC_RIMC_ATTRx register  ***************/
+#define RIFSC_RIMC_ATTRx_MCID_Pos           (4U)
+#define RIFSC_RIMC_ATTRx_MCID_Msk           (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000070 */
+#define RIFSC_RIMC_ATTRx_MCID               RIFSC_RIMC_ATTRx_MCID_Msk                      /*!< Master CID */
+#define RIFSC_RIMC_ATTRx_MCID_0             (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000010 */
+#define RIFSC_RIMC_ATTRx_MCID_1             (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000020 */
+#define RIFSC_RIMC_ATTRx_MCID_2             (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000040 */
+#define RIFSC_RIMC_ATTRx_MSEC_Pos           (8U)
+#define RIFSC_RIMC_ATTRx_MSEC_Msk           (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos)            /*!< 0x00000100 */
+#define RIFSC_RIMC_ATTRx_MSEC               RIFSC_RIMC_ATTRx_MSEC_Msk                      /*!< Master secure */
+#define RIFSC_RIMC_ATTRx_MPRIV_Pos          (9U)
+#define RIFSC_RIMC_ATTRx_MPRIV_Msk          (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos)           /*!< 0x00000200 */
+#define RIFSC_RIMC_ATTRx_MPRIV              RIFSC_RIMC_ATTRx_MPRIV_Msk                     /*!< Master privileged */
+
+/******************************************************************************/
+/*                                                                            */
+/*     Resource Isolation Slave unit for Address space protection (RISAF)     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RISAF_CR register  *******************/
+#define RISAF_CR_GLOCK_Pos                 (0U)
+#define RISAF_CR_GLOCK_Msk                 (0x1UL << RISAF_CR_GLOCK_Pos)                      /*!< 0x00000001 */
+#define RISAF_CR_GLOCK                     RISAF_CR_GLOCK_Msk                                /*!< Global lock */
+
+/******************  Bit definition for RISAF_IASR register  ******************/
+#define RISAF_IASR_CAEF_Pos                (0U)
+#define RISAF_IASR_CAEF_Msk                (0x1UL << RISAF_IASR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IASR_CAEF                    RISAF_IASR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IASR_IAEF_Pos                (1U)
+#define RISAF_IASR_IAEF_Msk                (0x1UL << RISAF_IASR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IASR_IAEF                    RISAF_IASR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/******************  Bit definition for RISAF_IACR register  ******************/
+#define RISAF_IACR_CAEF_Pos                (0U)
+#define RISAF_IACR_CAEF_Msk                (0x1UL << RISAF_IACR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IACR_CAEF                    RISAF_IACR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IACR_IAEF_Pos                (1U)
+#define RISAF_IACR_IAEF_Msk                (0x1UL << RISAF_IACR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IACR_IAEF                    RISAF_IACR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/*****************  Bit definition for RISAF_IAESR register  *****************/
+#define RISAF_IAESR_IACID_Pos              (0U)
+#define RISAF_IAESR_IACID_Msk              (0x7UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000007 */
+#define RISAF_IAESR_IACID                  RISAF_IAESR_IACID_Msk                            /*!< Illegal access compartment ID */
+#define RISAF_IAESR_IACID_0                (0x1UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000001 */
+#define RISAF_IAESR_IACID_1                (0x2UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000002 */
+#define RISAF_IAESR_IACID_2                (0x4UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000004 */
+#define RISAF_IAESR_IAPRIV_Pos             (4U)
+#define RISAF_IAESR_IAPRIV_Msk             (0x1UL << RISAF_IAESR_IAPRIV_Pos)                 /*!< 0x00000010 */
+#define RISAF_IAESR_IAPRIV                 RISAF_IAESR_IAPRIV_Msk                           /*!< Illegal access privileged */
+#define RISAF_IAESR_IASEC_Pos              (5U)
+#define RISAF_IAESR_IASEC_Msk              (0x1UL << RISAF_IAESR_IASEC_Pos)                  /*!< 0x00000020 */
+#define RISAF_IAESR_IASEC                  RISAF_IAESR_IASEC_Msk                            /*!< Illegal access security */
+#define RISAF_IAESR_IANRW_Pos              (7U)
+#define RISAF_IAESR_IANRW_Msk              (0x1UL << RISAF_IAESR_IANRW_Pos)                  /*!< 0x00000080 */
+#define RISAF_IAESR_IANRW                  RISAF_IAESR_IANRW_Msk                            /*!< Illegal access read/write */
+
+/*****************  Bit definition for RISAF_IADDR register  *****************/
+#define RISAF_IADDR_IADD_Pos                (0U)
+#define RISAF_IADDR_IADD_Msk                (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos)            /*!< 0xFFFFFFFF */
+#define RISAF_IADDR_IADD                    RISAF_IADDR_IADD_Msk                             /*!< Illegal address */
+#define RISAF_IADDR_IADD_0                  (0x1UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000001 */
+#define RISAF_IADDR_IADD_1                  (0x2UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000002 */
+#define RISAF_IADDR_IADD_2                  (0x4UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000004 */
+#define RISAF_IADDR_IADD_3                  (0x8UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000008 */
+#define RISAF_IADDR_IADD_4                  (0x10UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000010 */
+#define RISAF_IADDR_IADD_5                  (0x20UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000020 */
+#define RISAF_IADDR_IADD_6                  (0x40UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000040 */
+#define RISAF_IADDR_IADD_7                  (0x80UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000080 */
+#define RISAF_IADDR_IADD_8                  (0x100UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000100 */
+#define RISAF_IADDR_IADD_9                  (0x200UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000200 */
+#define RISAF_IADDR_IADD_10                 (0x400UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000400 */
+#define RISAF_IADDR_IADD_11                 (0x800UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000800 */
+#define RISAF_IADDR_IADD_12                 (0x1000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00001000 */
+#define RISAF_IADDR_IADD_13                 (0x2000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00002000 */
+#define RISAF_IADDR_IADD_14                 (0x4000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00004000 */
+#define RISAF_IADDR_IADD_15                 (0x8000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00008000 */
+#define RISAF_IADDR_IADD_16                 (0x10000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00010000 */
+#define RISAF_IADDR_IADD_17                 (0x20000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00020000 */
+#define RISAF_IADDR_IADD_18                 (0x40000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00040000 */
+#define RISAF_IADDR_IADD_19                 (0x80000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00080000 */
+#define RISAF_IADDR_IADD_20                 (0x100000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00100000 */
+#define RISAF_IADDR_IADD_21                 (0x200000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00200000 */
+#define RISAF_IADDR_IADD_22                 (0x400000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00400000 */
+#define RISAF_IADDR_IADD_23                 (0x800000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00800000 */
+#define RISAF_IADDR_IADD_24                 (0x1000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x01000000 */
+#define RISAF_IADDR_IADD_25                 (0x2000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x02000000 */
+#define RISAF_IADDR_IADD_26                 (0x4000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x04000000 */
+#define RISAF_IADDR_IADD_27                 (0x8000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x08000000 */
+#define RISAF_IADDR_IADD_28                 (0x10000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x10000000 */
+#define RISAF_IADDR_IADD_29                 (0x20000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x20000000 */
+#define RISAF_IADDR_IADD_30                 (0x40000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x40000000 */
+#define RISAF_IADDR_IADD_31                 (0x80000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_CFGR register  ****************/
+#define RISAF_REGx_CFGR_BREN_Pos           (0U)
+#define RISAF_REGx_CFGR_BREN_Msk           (0x1UL << RISAF_REGx_CFGR_BREN_Pos)                /*!< 0x00000001 */
+#define RISAF_REGx_CFGR_BREN               RISAF_REGx_CFGR_BREN_Msk                          /*!< Base region enable */
+#define RISAF_REGx_CFGR_SEC_Pos            (8U)
+#define RISAF_REGx_CFGR_SEC_Msk            (0x1UL << RISAF_REGx_CFGR_SEC_Pos)                 /*!< 0x00000100 */
+#define RISAF_REGx_CFGR_SEC                RISAF_REGx_CFGR_SEC_Msk                           /*!< Secure region */
+#define RISAF_REGx_CFGR_PRIVC0_Pos         (16U)
+#define RISAF_REGx_CFGR_PRIVC0_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos)              /*!< 0x00010000 */
+#define RISAF_REGx_CFGR_PRIVC0             RISAF_REGx_CFGR_PRIVC0_Msk                        /*!< Privileged access for compartment 0 */
+#define RISAF_REGx_CFGR_PRIVC1_Pos         (17U)
+#define RISAF_REGx_CFGR_PRIVC1_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos)              /*!< 0x00020000 */
+#define RISAF_REGx_CFGR_PRIVC1             RISAF_REGx_CFGR_PRIVC1_Msk                        /*!< Privileged access for compartment 1 */
+#define RISAF_REGx_CFGR_PRIVC2_Pos         (18U)
+#define RISAF_REGx_CFGR_PRIVC2_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos)              /*!< 0x00040000 */
+#define RISAF_REGx_CFGR_PRIVC2             RISAF_REGx_CFGR_PRIVC2_Msk                        /*!< Privileged access for compartment 2 */
+#define RISAF_REGx_CFGR_PRIVC3_Pos         (19U)
+#define RISAF_REGx_CFGR_PRIVC3_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos)              /*!< 0x00080000 */
+#define RISAF_REGx_CFGR_PRIVC3             RISAF_REGx_CFGR_PRIVC3_Msk                        /*!< Privileged access for compartment 3 */
+#define RISAF_REGx_CFGR_PRIVC4_Pos         (20U)
+#define RISAF_REGx_CFGR_PRIVC4_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos)              /*!< 0x00100000 */
+#define RISAF_REGx_CFGR_PRIVC4             RISAF_REGx_CFGR_PRIVC4_Msk                        /*!< Privileged access for compartment 4 */
+#define RISAF_REGx_CFGR_PRIVC5_Pos         (21U)
+#define RISAF_REGx_CFGR_PRIVC5_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos)              /*!< 0x00200000 */
+#define RISAF_REGx_CFGR_PRIVC5             RISAF_REGx_CFGR_PRIVC5_Msk                        /*!< Privileged access for compartment 5 */
+#define RISAF_REGx_CFGR_PRIVC6_Pos         (22U)
+#define RISAF_REGx_CFGR_PRIVC6_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos)              /*!< 0x00400000 */
+#define RISAF_REGx_CFGR_PRIVC6             RISAF_REGx_CFGR_PRIVC6_Msk                        /*!< Privileged access for compartment 6 */
+#define RISAF_REGx_CFGR_PRIVC7_Pos         (23U)
+#define RISAF_REGx_CFGR_PRIVC7_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos)              /*!< 0x00800000 */
+#define RISAF_REGx_CFGR_PRIVC7             RISAF_REGx_CFGR_PRIVC7_Msk                        /*!< Privileged access for compartment 7 */
+
+/**************  Bit definition for RISAF_REGx_STARTR register  ***************/
+#define RISAF_REGx_STARTR_BADDSTART_Pos    (0U)
+#define RISAF_REGx_STARTR_BADDSTART_Msk    (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0xFFFFFFFF */
+#define RISAF_REGx_STARTR_BADDSTART        RISAF_REGx_STARTR_BADDSTART_Msk                   /*!< Base region address start */
+#define RISAF_REGx_STARTR_BADDSTART_0      (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000001 */
+#define RISAF_REGx_STARTR_BADDSTART_1      (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000002 */
+#define RISAF_REGx_STARTR_BADDSTART_2      (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000004 */
+#define RISAF_REGx_STARTR_BADDSTART_3      (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000008 */
+#define RISAF_REGx_STARTR_BADDSTART_4      (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000010 */
+#define RISAF_REGx_STARTR_BADDSTART_5      (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000020 */
+#define RISAF_REGx_STARTR_BADDSTART_6      (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000040 */
+#define RISAF_REGx_STARTR_BADDSTART_7      (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000080 */
+#define RISAF_REGx_STARTR_BADDSTART_8      (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000100 */
+#define RISAF_REGx_STARTR_BADDSTART_9      (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000200 */
+#define RISAF_REGx_STARTR_BADDSTART_10     (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000400 */
+#define RISAF_REGx_STARTR_BADDSTART_11     (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000800 */
+#define RISAF_REGx_STARTR_BADDSTART_12     (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00001000 */
+#define RISAF_REGx_STARTR_BADDSTART_13     (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00002000 */
+#define RISAF_REGx_STARTR_BADDSTART_14     (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00004000 */
+#define RISAF_REGx_STARTR_BADDSTART_15     (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00008000 */
+#define RISAF_REGx_STARTR_BADDSTART_16     (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00010000 */
+#define RISAF_REGx_STARTR_BADDSTART_17     (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00020000 */
+#define RISAF_REGx_STARTR_BADDSTART_18     (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00040000 */
+#define RISAF_REGx_STARTR_BADDSTART_19     (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00080000 */
+#define RISAF_REGx_STARTR_BADDSTART_20     (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00100000 */
+#define RISAF_REGx_STARTR_BADDSTART_21     (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00200000 */
+#define RISAF_REGx_STARTR_BADDSTART_22     (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00400000 */
+#define RISAF_REGx_STARTR_BADDSTART_23     (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00800000 */
+#define RISAF_REGx_STARTR_BADDSTART_24     (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x01000000 */
+#define RISAF_REGx_STARTR_BADDSTART_25     (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x02000000 */
+#define RISAF_REGx_STARTR_BADDSTART_26     (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x04000000 */
+#define RISAF_REGx_STARTR_BADDSTART_27     (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x08000000 */
+#define RISAF_REGx_STARTR_BADDSTART_28     (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x10000000 */
+#define RISAF_REGx_STARTR_BADDSTART_29     (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x20000000 */
+#define RISAF_REGx_STARTR_BADDSTART_30     (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x40000000 */
+#define RISAF_REGx_STARTR_BADDSTART_31     (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_ENDR register  ****************/
+#define RISAF_REGx_ENDR_BADDEND_Pos        (0U)
+#define RISAF_REGx_ENDR_BADDEND_Msk        (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0xFFFFFFFF */
+#define RISAF_REGx_ENDR_BADDEND            RISAF_REGx_ENDR_BADDEND_Msk                       /*!< Base region address end */
+#define RISAF_REGx_ENDR_BADDEND_0          (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000001 */
+#define RISAF_REGx_ENDR_BADDEND_1          (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000002 */
+#define RISAF_REGx_ENDR_BADDEND_2          (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000004 */
+#define RISAF_REGx_ENDR_BADDEND_3          (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000008 */
+#define RISAF_REGx_ENDR_BADDEND_4          (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000010 */
+#define RISAF_REGx_ENDR_BADDEND_5          (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000020 */
+#define RISAF_REGx_ENDR_BADDEND_6          (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000040 */
+#define RISAF_REGx_ENDR_BADDEND_7          (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000080 */
+#define RISAF_REGx_ENDR_BADDEND_8          (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000100 */
+#define RISAF_REGx_ENDR_BADDEND_9          (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000200 */
+#define RISAF_REGx_ENDR_BADDEND_10         (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000400 */
+#define RISAF_REGx_ENDR_BADDEND_11         (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000800 */
+#define RISAF_REGx_ENDR_BADDEND_12         (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00001000 */
+#define RISAF_REGx_ENDR_BADDEND_13         (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00002000 */
+#define RISAF_REGx_ENDR_BADDEND_14         (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00004000 */
+#define RISAF_REGx_ENDR_BADDEND_15         (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00008000 */
+#define RISAF_REGx_ENDR_BADDEND_16         (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00010000 */
+#define RISAF_REGx_ENDR_BADDEND_17         (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00020000 */
+#define RISAF_REGx_ENDR_BADDEND_18         (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00040000 */
+#define RISAF_REGx_ENDR_BADDEND_19         (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00080000 */
+#define RISAF_REGx_ENDR_BADDEND_20         (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00100000 */
+#define RISAF_REGx_ENDR_BADDEND_21         (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00200000 */
+#define RISAF_REGx_ENDR_BADDEND_22         (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00400000 */
+#define RISAF_REGx_ENDR_BADDEND_23         (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00800000 */
+#define RISAF_REGx_ENDR_BADDEND_24         (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x01000000 */
+#define RISAF_REGx_ENDR_BADDEND_25         (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x02000000 */
+#define RISAF_REGx_ENDR_BADDEND_26         (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x04000000 */
+#define RISAF_REGx_ENDR_BADDEND_27         (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x08000000 */
+#define RISAF_REGx_ENDR_BADDEND_28         (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x10000000 */
+#define RISAF_REGx_ENDR_BADDEND_29         (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x20000000 */
+#define RISAF_REGx_ENDR_BADDEND_30         (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x40000000 */
+#define RISAF_REGx_ENDR_BADDEND_31         (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_CIDCFGR register  **************/
+#define RISAF_REGx_CIDCFGR_RDENC0_Pos      (0U)
+#define RISAF_REGx_CIDCFGR_RDENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos)           /*!< 0x00000001 */
+#define RISAF_REGx_CIDCFGR_RDENC0          RISAF_REGx_CIDCFGR_RDENC0_Msk                     /*!< Read enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_RDENC1_Pos      (1U)
+#define RISAF_REGx_CIDCFGR_RDENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos)           /*!< 0x00000002 */
+#define RISAF_REGx_CIDCFGR_RDENC1          RISAF_REGx_CIDCFGR_RDENC1_Msk                     /*!< Read enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_RDENC2_Pos      (2U)
+#define RISAF_REGx_CIDCFGR_RDENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos)           /*!< 0x00000004 */
+#define RISAF_REGx_CIDCFGR_RDENC2          RISAF_REGx_CIDCFGR_RDENC2_Msk                     /*!< Read enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_RDENC3_Pos      (3U)
+#define RISAF_REGx_CIDCFGR_RDENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos)           /*!< 0x00000008 */
+#define RISAF_REGx_CIDCFGR_RDENC3          RISAF_REGx_CIDCFGR_RDENC3_Msk                     /*!< Read enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_RDENC4_Pos      (4U)
+#define RISAF_REGx_CIDCFGR_RDENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_CIDCFGR_RDENC4          RISAF_REGx_CIDCFGR_RDENC4_Msk                     /*!< Read enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_RDENC5_Pos      (5U)
+#define RISAF_REGx_CIDCFGR_RDENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_CIDCFGR_RDENC5          RISAF_REGx_CIDCFGR_RDENC5_Msk                     /*!< Read enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_RDENC6_Pos      (6U)
+#define RISAF_REGx_CIDCFGR_RDENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_CIDCFGR_RDENC6          RISAF_REGx_CIDCFGR_RDENC6_Msk                     /*!< Read enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_RDENC7_Pos      (7U)
+#define RISAF_REGx_CIDCFGR_RDENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_CIDCFGR_RDENC7          RISAF_REGx_CIDCFGR_RDENC7_Msk                     /*!< Read enable for compartment 7 */
+#define RISAF_REGx_CIDCFGR_WRENC0_Pos      (16U)
+#define RISAF_REGx_CIDCFGR_WRENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos)           /*!< 0x00010000 */
+#define RISAF_REGx_CIDCFGR_WRENC0          RISAF_REGx_CIDCFGR_WRENC0_Msk                     /*!< Write enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_WRENC1_Pos      (17U)
+#define RISAF_REGx_CIDCFGR_WRENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos)           /*!< 0x00020000 */
+#define RISAF_REGx_CIDCFGR_WRENC1          RISAF_REGx_CIDCFGR_WRENC1_Msk                     /*!< Write enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_WRENC2_Pos      (18U)
+#define RISAF_REGx_CIDCFGR_WRENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos)           /*!< 0x00040000 */
+#define RISAF_REGx_CIDCFGR_WRENC2          RISAF_REGx_CIDCFGR_WRENC2_Msk                     /*!< Write enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_WRENC3_Pos      (19U)
+#define RISAF_REGx_CIDCFGR_WRENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos)           /*!< 0x00080000 */
+#define RISAF_REGx_CIDCFGR_WRENC3          RISAF_REGx_CIDCFGR_WRENC3_Msk                     /*!< Write enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_WRENC4_Pos      (20U)
+#define RISAF_REGx_CIDCFGR_WRENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos)           /*!< 0x00100000 */
+#define RISAF_REGx_CIDCFGR_WRENC4          RISAF_REGx_CIDCFGR_WRENC4_Msk                     /*!< Write enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_WRENC5_Pos      (21U)
+#define RISAF_REGx_CIDCFGR_WRENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos)           /*!< 0x00200000 */
+#define RISAF_REGx_CIDCFGR_WRENC5          RISAF_REGx_CIDCFGR_WRENC5_Msk                     /*!< Write enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_WRENC6_Pos      (22U)
+#define RISAF_REGx_CIDCFGR_WRENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos)           /*!< 0x00400000 */
+#define RISAF_REGx_CIDCFGR_WRENC6          RISAF_REGx_CIDCFGR_WRENC6_Msk                     /*!< Write enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_WRENC7_Pos      (23U)
+#define RISAF_REGx_CIDCFGR_WRENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos)           /*!< 0x00800000 */
+#define RISAF_REGx_CIDCFGR_WRENC7          RISAF_REGx_CIDCFGR_WRENC7_Msk                     /*!< Write enable for compartment 7 */
+
+/***************  Bit definition for RISAF_REGx_zCFGR register  ***************/
+#define RISAF_REGx_zCFGR_SREN_Pos          (0U)
+#define RISAF_REGx_zCFGR_SREN_Msk          (0x1UL << RISAF_REGx_zCFGR_SREN_Pos)               /*!< 0x00000001 */
+#define RISAF_REGx_zCFGR_SREN              RISAF_REGx_zCFGR_SREN_Msk                         /*!< Subregion enable */
+#define RISAF_REGx_zCFGR_RLOCK_Pos         (1U)
+#define RISAF_REGx_zCFGR_RLOCK_Msk         (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos)              /*!< 0x00000002 */
+#define RISAF_REGx_zCFGR_RLOCK             RISAF_REGx_zCFGR_RLOCK_Msk                        /*!< Resource lock */
+#define RISAF_REGx_zCFGR_SRCID_Pos         (4U)
+#define RISAF_REGx_zCFGR_SRCID_Msk         (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000070 */
+#define RISAF_REGx_zCFGR_SRCID             RISAF_REGx_zCFGR_SRCID_Msk                        /*!< Subregion CID */
+#define RISAF_REGx_zCFGR_SRCID_0           (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000010 */
+#define RISAF_REGx_zCFGR_SRCID_1           (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000020 */
+#define RISAF_REGx_zCFGR_SRCID_2           (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000040 */
+#define RISAF_REGx_zCFGR_SEC_Pos           (8U)
+#define RISAF_REGx_zCFGR_SEC_Msk           (0x1UL << RISAF_REGx_zCFGR_SEC_Pos)                /*!< 0x00000100 */
+#define RISAF_REGx_zCFGR_SEC               RISAF_REGx_zCFGR_SEC_Msk                          /*!< Secure subregion */
+#define RISAF_REGx_zCFGR_PRIV_Pos          (9U)
+#define RISAF_REGx_zCFGR_PRIV_Msk          (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos)               /*!< 0x00000200 */
+#define RISAF_REGx_zCFGR_PRIV              RISAF_REGx_zCFGR_PRIV_Msk                         /*!< Privileged subregion */
+#define RISAF_REGx_zCFGR_RDEN_Pos          (12U)
+#define RISAF_REGx_zCFGR_RDEN_Msk          (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos)               /*!< 0x00001000 */
+#define RISAF_REGx_zCFGR_RDEN              RISAF_REGx_zCFGR_RDEN_Msk                         /*!< Read enable */
+#define RISAF_REGx_zCFGR_WREN_Pos          (13U)
+#define RISAF_REGx_zCFGR_WREN_Msk          (0x1UL << RISAF_REGx_zCFGR_WREN_Pos)               /*!< 0x00002000 */
+#define RISAF_REGx_zCFGR_WREN              RISAF_REGx_zCFGR_WREN_Msk                         /*!< Write enable */
+
+/**************  Bit definition for RISAF_REGx_zSTARTR register  **************/
+#define RISAF_REGx_zSTARTR_SADDSTART_Pos   (0U)
+#define RISAF_REGx_zSTARTR_SADDSTART_Msk   (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zSTARTR_SADDSTART       RISAF_REGx_zSTARTR_SADDSTART_Msk                  /*!< Subregion address start */
+#define RISAF_REGx_zSTARTR_SADDSTART_0     (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000001 */
+#define RISAF_REGx_zSTARTR_SADDSTART_1     (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000002 */
+#define RISAF_REGx_zSTARTR_SADDSTART_2     (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000004 */
+#define RISAF_REGx_zSTARTR_SADDSTART_3     (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000008 */
+#define RISAF_REGx_zSTARTR_SADDSTART_4     (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000010 */
+#define RISAF_REGx_zSTARTR_SADDSTART_5     (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000020 */
+#define RISAF_REGx_zSTARTR_SADDSTART_6     (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000040 */
+#define RISAF_REGx_zSTARTR_SADDSTART_7     (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000080 */
+#define RISAF_REGx_zSTARTR_SADDSTART_8     (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000100 */
+#define RISAF_REGx_zSTARTR_SADDSTART_9     (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000200 */
+#define RISAF_REGx_zSTARTR_SADDSTART_10    (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000400 */
+#define RISAF_REGx_zSTARTR_SADDSTART_11    (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000800 */
+#define RISAF_REGx_zSTARTR_SADDSTART_12    (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00001000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_13    (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00002000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_14    (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00004000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_15    (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00008000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_16    (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00010000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_17    (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00020000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_18    (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00040000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_19    (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00080000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_20    (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00100000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_21    (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00200000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_22    (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00400000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_23    (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00800000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_24    (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x01000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_25    (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x02000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_26    (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x04000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_27    (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x08000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_28    (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_29    (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_30    (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_31    (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_zENDR register  ***************/
+#define RISAF_REGx_zENDR_SADDEND_Pos       (0U)
+#define RISAF_REGx_zENDR_SADDEND_Msk       (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zENDR_SADDEND           RISAF_REGx_zENDR_SADDEND_Msk                      /*!< Subregion address end */
+#define RISAF_REGx_zENDR_SADDEND_0         (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000001 */
+#define RISAF_REGx_zENDR_SADDEND_1         (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000002 */
+#define RISAF_REGx_zENDR_SADDEND_2         (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000004 */
+#define RISAF_REGx_zENDR_SADDEND_3         (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000008 */
+#define RISAF_REGx_zENDR_SADDEND_4         (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_zENDR_SADDEND_5         (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_zENDR_SADDEND_6         (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_zENDR_SADDEND_7         (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_zENDR_SADDEND_8         (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000100 */
+#define RISAF_REGx_zENDR_SADDEND_9         (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000200 */
+#define RISAF_REGx_zENDR_SADDEND_10        (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000400 */
+#define RISAF_REGx_zENDR_SADDEND_11        (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000800 */
+#define RISAF_REGx_zENDR_SADDEND_12        (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00001000 */
+#define RISAF_REGx_zENDR_SADDEND_13        (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00002000 */
+#define RISAF_REGx_zENDR_SADDEND_14        (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00004000 */
+#define RISAF_REGx_zENDR_SADDEND_15        (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00008000 */
+#define RISAF_REGx_zENDR_SADDEND_16        (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00010000 */
+#define RISAF_REGx_zENDR_SADDEND_17        (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00020000 */
+#define RISAF_REGx_zENDR_SADDEND_18        (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00040000 */
+#define RISAF_REGx_zENDR_SADDEND_19        (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00080000 */
+#define RISAF_REGx_zENDR_SADDEND_20        (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00100000 */
+#define RISAF_REGx_zENDR_SADDEND_21        (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00200000 */
+#define RISAF_REGx_zENDR_SADDEND_22        (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00400000 */
+#define RISAF_REGx_zENDR_SADDEND_23        (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00800000 */
+#define RISAF_REGx_zENDR_SADDEND_24        (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x01000000 */
+#define RISAF_REGx_zENDR_SADDEND_25        (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x02000000 */
+#define RISAF_REGx_zENDR_SADDEND_26        (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x04000000 */
+#define RISAF_REGx_zENDR_SADDEND_27        (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x08000000 */
+#define RISAF_REGx_zENDR_SADDEND_28        (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x10000000 */
+#define RISAF_REGx_zENDR_SADDEND_29        (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x20000000 */
+#define RISAF_REGx_zENDR_SADDEND_30        (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x40000000 */
+#define RISAF_REGx_zENDR_SADDEND_31        (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_zNESTR register  ***************/
+#define RISAF_REGx_zNESTR_DCEN_Pos         (2U)
+#define RISAF_REGx_zNESTR_DCEN_Msk         (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos)              /*!< 0x00000004 */
+#define RISAF_REGx_zNESTR_DCEN             RISAF_REGx_zNESTR_DCEN_Msk                        /*!< Delegated configuration enable */
+#define RISAF_REGx_zNESTR_DCCID_Pos        (4U)
+#define RISAF_REGx_zNESTR_DCCID_Msk        (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000070 */
+#define RISAF_REGx_zNESTR_DCCID            RISAF_REGx_zNESTR_DCCID_Msk                       /*!< Delegated configuration CID */
+#define RISAF_REGx_zNESTR_DCCID_0          (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000010 */
+#define RISAF_REGx_zNESTR_DCCID_1          (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000020 */
+#define RISAF_REGx_zNESTR_DCCID_2          (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000040 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (IAC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IAC_IER0 register  *******************/
+#define IAC_IERx_IAIE0_Pos         (0U)
+#define IAC_IERx_IAIE0_Msk         (0x1UL << IAC_IERx_IAIE0_Pos)        /*!< 0x00000001 */
+#define IAC_IERx_IAIE0             IAC_IERx_IAIE0_Msk                  /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_IERx_IAIE1_Pos         (1U)
+#define IAC_IERx_IAIE1_Msk         (0x1UL << IAC_IERx_IAIE1_Pos)        /*!< 0x00000002 */
+#define IAC_IERx_IAIE1             IAC_IERx_IAIE1_Msk                  /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_IERx_IAIE2_Pos         (2U)
+#define IAC_IERx_IAIE2_Msk         (0x1UL << IAC_IERx_IAIE2_Pos)        /*!< 0x00000004 */
+#define IAC_IERx_IAIE2             IAC_IERx_IAIE2_Msk                  /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_IERx_IAIE3_Pos         (3U)
+#define IAC_IERx_IAIE3_Msk         (0x1UL << IAC_IERx_IAIE3_Pos)        /*!< 0x00000008 */
+#define IAC_IERx_IAIE3             IAC_IERx_IAIE3_Msk                  /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_IERx_IAIE4_Pos         (4U)
+#define IAC_IERx_IAIE4_Msk         (0x1UL << IAC_IERx_IAIE4_Pos)        /*!< 0x00000010 */
+#define IAC_IERx_IAIE4             IAC_IERx_IAIE4_Msk                  /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_IERx_IAIE5_Pos         (5U)
+#define IAC_IERx_IAIE5_Msk         (0x1UL << IAC_IERx_IAIE5_Pos)        /*!< 0x00000020 */
+#define IAC_IERx_IAIE5             IAC_IERx_IAIE5_Msk                  /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_IERx_IAIE6_Pos         (6U)
+#define IAC_IERx_IAIE6_Msk         (0x1UL << IAC_IERx_IAIE6_Pos)        /*!< 0x00000040 */
+#define IAC_IERx_IAIE6             IAC_IERx_IAIE6_Msk                  /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_IERx_IAIE7_Pos         (7U)
+#define IAC_IERx_IAIE7_Msk         (0x1UL << IAC_IERx_IAIE7_Pos)        /*!< 0x00000080 */
+#define IAC_IERx_IAIE7             IAC_IERx_IAIE7_Msk                  /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_IERx_IAIE8_Pos         (8U)
+#define IAC_IERx_IAIE8_Msk         (0x1UL << IAC_IERx_IAIE8_Pos)        /*!< 0x00000100 */
+#define IAC_IERx_IAIE8             IAC_IERx_IAIE8_Msk                  /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_IERx_IAIE9_Pos         (9U)
+#define IAC_IERx_IAIE9_Msk         (0x1UL << IAC_IERx_IAIE9_Pos)        /*!< 0x00000200 */
+#define IAC_IERx_IAIE9             IAC_IERx_IAIE9_Msk                  /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_IERx_IAIE10_Pos        (10U)
+#define IAC_IERx_IAIE10_Msk        (0x1UL << IAC_IERx_IAIE10_Pos)       /*!< 0x00000400 */
+#define IAC_IERx_IAIE10            IAC_IERx_IAIE10_Msk                 /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_IERx_IAIE11_Pos        (11U)
+#define IAC_IERx_IAIE11_Msk        (0x1UL << IAC_IERx_IAIE11_Pos)       /*!< 0x00000800 */
+#define IAC_IERx_IAIE11            IAC_IERx_IAIE11_Msk                 /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_IERx_IAIE12_Pos        (12U)
+#define IAC_IERx_IAIE12_Msk        (0x1UL << IAC_IERx_IAIE12_Pos)       /*!< 0x00001000 */
+#define IAC_IERx_IAIE12            IAC_IERx_IAIE12_Msk                 /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_IERx_IAIE13_Pos        (13U)
+#define IAC_IERx_IAIE13_Msk        (0x1UL << IAC_IERx_IAIE13_Pos)       /*!< 0x00002000 */
+#define IAC_IERx_IAIE13            IAC_IERx_IAIE13_Msk                 /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_IERx_IAIE14_Pos        (14U)
+#define IAC_IERx_IAIE14_Msk        (0x1UL << IAC_IERx_IAIE14_Pos)       /*!< 0x00004000 */
+#define IAC_IERx_IAIE14            IAC_IERx_IAIE14_Msk                 /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_IERx_IAIE15_Pos        (15U)
+#define IAC_IERx_IAIE15_Msk        (0x1UL << IAC_IERx_IAIE15_Pos)       /*!< 0x00008000 */
+#define IAC_IERx_IAIE15            IAC_IERx_IAIE15_Msk                 /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_IERx_IAIE16_Pos        (16U)
+#define IAC_IERx_IAIE16_Msk        (0x1UL << IAC_IERx_IAIE16_Pos)       /*!< 0x00010000 */
+#define IAC_IERx_IAIE16            IAC_IERx_IAIE16_Msk                 /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_IERx_IAIE17_Pos        (17U)
+#define IAC_IERx_IAIE17_Msk        (0x1UL << IAC_IERx_IAIE17_Pos)       /*!< 0x00020000 */
+#define IAC_IERx_IAIE17            IAC_IERx_IAIE17_Msk                 /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_IERx_IAIE18_Pos        (18U)
+#define IAC_IERx_IAIE18_Msk        (0x1UL << IAC_IERx_IAIE18_Pos)       /*!< 0x00040000 */
+#define IAC_IERx_IAIE18            IAC_IERx_IAIE18_Msk                 /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_IERx_IAIE19_Pos        (19U)
+#define IAC_IERx_IAIE19_Msk        (0x1UL << IAC_IERx_IAIE19_Pos)       /*!< 0x00080000 */
+#define IAC_IERx_IAIE19            IAC_IERx_IAIE19_Msk                 /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_IERx_IAIE20_Pos        (20U)
+#define IAC_IERx_IAIE20_Msk        (0x1UL << IAC_IERx_IAIE20_Pos)       /*!< 0x00100000 */
+#define IAC_IERx_IAIE20            IAC_IERx_IAIE20_Msk                 /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_IERx_IAIE21_Pos        (21U)
+#define IAC_IERx_IAIE21_Msk        (0x1UL << IAC_IERx_IAIE21_Pos)       /*!< 0x00200000 */
+#define IAC_IERx_IAIE21            IAC_IERx_IAIE21_Msk                 /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_IERx_IAIE22_Pos        (22U)
+#define IAC_IERx_IAIE22_Msk        (0x1UL << IAC_IERx_IAIE22_Pos)       /*!< 0x00400000 */
+#define IAC_IERx_IAIE22            IAC_IERx_IAIE22_Msk                 /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_IERx_IAIE23_Pos        (23U)
+#define IAC_IERx_IAIE23_Msk        (0x1UL << IAC_IERx_IAIE23_Pos)       /*!< 0x00800000 */
+#define IAC_IERx_IAIE23            IAC_IERx_IAIE23_Msk                 /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_IERx_IAIE24_Pos        (24U)
+#define IAC_IERx_IAIE24_Msk        (0x1UL << IAC_IERx_IAIE24_Pos)       /*!< 0x01000000 */
+#define IAC_IERx_IAIE24            IAC_IERx_IAIE24_Msk                 /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_IERx_IAIE25_Pos        (25U)
+#define IAC_IERx_IAIE25_Msk        (0x1UL << IAC_IERx_IAIE25_Pos)       /*!< 0x02000000 */
+#define IAC_IERx_IAIE25            IAC_IERx_IAIE25_Msk                 /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_IERx_IAIE26_Pos        (26U)
+#define IAC_IERx_IAIE26_Msk        (0x1UL << IAC_IERx_IAIE26_Pos)       /*!< 0x04000000 */
+#define IAC_IERx_IAIE26            IAC_IERx_IAIE26_Msk                 /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_IERx_IAIE27_Pos        (27U)
+#define IAC_IERx_IAIE27_Msk        (0x1UL << IAC_IERx_IAIE27_Pos)       /*!< 0x08000000 */
+#define IAC_IERx_IAIE27            IAC_IERx_IAIE27_Msk                 /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_IERx_IAIE28_Pos        (28U)
+#define IAC_IERx_IAIE28_Msk        (0x1UL << IAC_IERx_IAIE28_Pos)       /*!< 0x10000000 */
+#define IAC_IERx_IAIE28            IAC_IERx_IAIE28_Msk                 /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_IERx_IAIE29_Pos        (29U)
+#define IAC_IERx_IAIE29_Msk        (0x1UL << IAC_IERx_IAIE29_Pos)       /*!< 0x20000000 */
+#define IAC_IERx_IAIE29            IAC_IERx_IAIE29_Msk                 /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_IERx_IAIE30_Pos        (30U)
+#define IAC_IERx_IAIE30_Msk        (0x1UL << IAC_IERx_IAIE30_Pos)       /*!< 0x40000000 */
+#define IAC_IERx_IAIE30            IAC_IERx_IAIE30_Msk                 /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_IERx_IAIE31_Pos        (31U)
+#define IAC_IERx_IAIE31_Msk        (0x1UL << IAC_IERx_IAIE31_Pos)       /*!< 0x80000000 */
+#define IAC_IERx_IAIE31            IAC_IERx_IAIE31_Msk                 /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ISRx register  *******************/
+#define IAC_ISRx_IAF0_Pos          (0U)
+#define IAC_ISRx_IAF0_Msk          (0x1UL << IAC_ISRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ISRx_IAF0              IAC_ISRx_IAF0_Msk                   /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_ISRx_IAF1_Pos          (1U)
+#define IAC_ISRx_IAF1_Msk          (0x1UL << IAC_ISRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ISRx_IAF1              IAC_ISRx_IAF1_Msk                   /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_ISRx_IAF2_Pos          (2U)
+#define IAC_ISRx_IAF2_Msk          (0x1UL << IAC_ISRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ISRx_IAF2              IAC_ISRx_IAF2_Msk                   /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_ISRx_IAF3_Pos          (3U)
+#define IAC_ISRx_IAF3_Msk          (0x1UL << IAC_ISRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ISRx_IAF3              IAC_ISRx_IAF3_Msk                   /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_ISRx_IAF4_Pos          (4U)
+#define IAC_ISRx_IAF4_Msk          (0x1UL << IAC_ISRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ISRx_IAF4              IAC_ISRx_IAF4_Msk                   /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_ISRx_IAF5_Pos          (5U)
+#define IAC_ISRx_IAF5_Msk          (0x1UL << IAC_ISRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ISRx_IAF5              IAC_ISRx_IAF5_Msk                   /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_ISRx_IAF6_Pos          (6U)
+#define IAC_ISRx_IAF6_Msk          (0x1UL << IAC_ISRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ISRx_IAF6              IAC_ISRx_IAF6_Msk                   /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_ISRx_IAF7_Pos          (7U)
+#define IAC_ISRx_IAF7_Msk          (0x1UL << IAC_ISRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ISRx_IAF7              IAC_ISRx_IAF7_Msk                   /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_ISRx_IAF8_Pos          (8U)
+#define IAC_ISRx_IAF8_Msk          (0x1UL << IAC_ISRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ISRx_IAF8              IAC_ISRx_IAF8_Msk                   /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_ISRx_IAF9_Pos          (9U)
+#define IAC_ISRx_IAF9_Msk          (0x1UL << IAC_ISRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ISRx_IAF9              IAC_ISRx_IAF9_Msk                   /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_ISRx_IAF10_Pos         (10U)
+#define IAC_ISRx_IAF10_Msk         (0x1UL << IAC_ISRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ISRx_IAF10             IAC_ISRx_IAF10_Msk                  /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_ISRx_IAF11_Pos         (11U)
+#define IAC_ISRx_IAF11_Msk         (0x1UL << IAC_ISRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ISRx_IAF11             IAC_ISRx_IAF11_Msk                  /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_ISRx_IAF12_Pos         (12U)
+#define IAC_ISRx_IAF12_Msk         (0x1UL << IAC_ISRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ISRx_IAF12             IAC_ISRx_IAF12_Msk                  /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_ISRx_IAF13_Pos         (13U)
+#define IAC_ISRx_IAF13_Msk         (0x1UL << IAC_ISRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ISRx_IAF13             IAC_ISRx_IAF13_Msk                  /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_ISRx_IAF14_Pos         (14U)
+#define IAC_ISRx_IAF14_Msk         (0x1UL << IAC_ISRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ISRx_IAF14             IAC_ISRx_IAF14_Msk                  /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_ISRx_IAF15_Pos         (15U)
+#define IAC_ISRx_IAF15_Msk         (0x1UL << IAC_ISRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ISRx_IAF15             IAC_ISRx_IAF15_Msk                  /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_ISRx_IAF16_Pos         (16U)
+#define IAC_ISRx_IAF16_Msk         (0x1UL << IAC_ISRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ISRx_IAF16             IAC_ISRx_IAF16_Msk                  /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_ISRx_IAF17_Pos         (17U)
+#define IAC_ISRx_IAF17_Msk         (0x1UL << IAC_ISRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ISRx_IAF17             IAC_ISRx_IAF17_Msk                  /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_ISRx_IAF18_Pos         (18U)
+#define IAC_ISRx_IAF18_Msk         (0x1UL << IAC_ISRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ISRx_IAF18             IAC_ISRx_IAF18_Msk                  /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_ISRx_IAF19_Pos         (19U)
+#define IAC_ISRx_IAF19_Msk         (0x1UL << IAC_ISRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ISRx_IAF19             IAC_ISRx_IAF19_Msk                  /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_ISRx_IAF20_Pos         (20U)
+#define IAC_ISRx_IAF20_Msk         (0x1UL << IAC_ISRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ISRx_IAF20             IAC_ISRx_IAF20_Msk                  /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_ISRx_IAF21_Pos         (21U)
+#define IAC_ISRx_IAF21_Msk         (0x1UL << IAC_ISRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ISRx_IAF21             IAC_ISRx_IAF21_Msk                  /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_ISRx_IAF22_Pos         (22U)
+#define IAC_ISRx_IAF22_Msk         (0x1UL << IAC_ISRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ISRx_IAF22             IAC_ISRx_IAF22_Msk                  /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_ISRx_IAF23_Pos         (23U)
+#define IAC_ISRx_IAF23_Msk         (0x1UL << IAC_ISRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ISRx_IAF23             IAC_ISRx_IAF23_Msk                  /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_ISRx_IAF24_Pos         (24U)
+#define IAC_ISRx_IAF24_Msk         (0x1UL << IAC_ISRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ISRx_IAF24             IAC_ISRx_IAF24_Msk                  /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_ISRx_IAF25_Pos         (25U)
+#define IAC_ISRx_IAF25_Msk         (0x1UL << IAC_ISRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ISRx_IAF25             IAC_ISRx_IAF25_Msk                  /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_ISRx_IAF26_Pos         (26U)
+#define IAC_ISRx_IAF26_Msk         (0x1UL << IAC_ISRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ISRx_IAF26             IAC_ISRx_IAF26_Msk                  /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_ISRx_IAF27_Pos         (27U)
+#define IAC_ISRx_IAF27_Msk         (0x1UL << IAC_ISRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ISRx_IAF27             IAC_ISRx_IAF27_Msk                  /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_ISRx_IAF28_Pos         (28U)
+#define IAC_ISRx_IAF28_Msk         (0x1UL << IAC_ISRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ISRx_IAF28             IAC_ISRx_IAF28_Msk                  /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_ISRx_IAF29_Pos         (29U)
+#define IAC_ISRx_IAF29_Msk         (0x1UL << IAC_ISRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ISRx_IAF29             IAC_ISRx_IAF29_Msk                  /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_ISRx_IAF30_Pos         (30U)
+#define IAC_ISRx_IAF30_Msk         (0x1UL << IAC_ISRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ISRx_IAF30             IAC_ISRx_IAF30_Msk                  /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_ISRx_IAF31_Pos         (31U)
+#define IAC_ISRx_IAF31_Msk         (0x1UL << IAC_ISRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ISRx_IAF31             IAC_ISRx_IAF31_Msk                  /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ICRx register  *******************/
+#define IAC_ICRx_IAF0_Pos          (0U)
+#define IAC_ICRx_IAF0_Msk          (0x1UL << IAC_ICRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ICRx_IAF0              IAC_ICRx_IAF0_Msk                   /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */
+#define IAC_ICRx_IAF1_Pos          (1U)
+#define IAC_ICRx_IAF1_Msk          (0x1UL << IAC_ICRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ICRx_IAF1              IAC_ICRx_IAF1_Msk                   /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */
+#define IAC_ICRx_IAF2_Pos          (2U)
+#define IAC_ICRx_IAF2_Msk          (0x1UL << IAC_ICRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ICRx_IAF2              IAC_ICRx_IAF2_Msk                   /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */
+#define IAC_ICRx_IAF3_Pos          (3U)
+#define IAC_ICRx_IAF3_Msk          (0x1UL << IAC_ICRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ICRx_IAF3              IAC_ICRx_IAF3_Msk                   /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */
+#define IAC_ICRx_IAF4_Pos          (4U)
+#define IAC_ICRx_IAF4_Msk          (0x1UL << IAC_ICRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ICRx_IAF4              IAC_ICRx_IAF4_Msk                   /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */
+#define IAC_ICRx_IAF5_Pos          (5U)
+#define IAC_ICRx_IAF5_Msk          (0x1UL << IAC_ICRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ICRx_IAF5              IAC_ICRx_IAF5_Msk                   /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */
+#define IAC_ICRx_IAF6_Pos          (6U)
+#define IAC_ICRx_IAF6_Msk          (0x1UL << IAC_ICRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ICRx_IAF6              IAC_ICRx_IAF6_Msk                   /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */
+#define IAC_ICRx_IAF7_Pos          (7U)
+#define IAC_ICRx_IAF7_Msk          (0x1UL << IAC_ICRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ICRx_IAF7              IAC_ICRx_IAF7_Msk                   /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */
+#define IAC_ICRx_IAF8_Pos          (8U)
+#define IAC_ICRx_IAF8_Msk          (0x1UL << IAC_ICRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ICRx_IAF8              IAC_ICRx_IAF8_Msk                   /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */
+#define IAC_ICRx_IAF9_Pos          (9U)
+#define IAC_ICRx_IAF9_Msk          (0x1UL << IAC_ICRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ICRx_IAF9              IAC_ICRx_IAF9_Msk                   /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */
+#define IAC_ICRx_IAF10_Pos         (10U)
+#define IAC_ICRx_IAF10_Msk         (0x1UL << IAC_ICRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ICRx_IAF10             IAC_ICRx_IAF10_Msk                  /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */
+#define IAC_ICRx_IAF11_Pos         (11U)
+#define IAC_ICRx_IAF11_Msk         (0x1UL << IAC_ICRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ICRx_IAF11             IAC_ICRx_IAF11_Msk                  /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */
+#define IAC_ICRx_IAF12_Pos         (12U)
+#define IAC_ICRx_IAF12_Msk         (0x1UL << IAC_ICRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ICRx_IAF12             IAC_ICRx_IAF12_Msk                  /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */
+#define IAC_ICRx_IAF13_Pos         (13U)
+#define IAC_ICRx_IAF13_Msk         (0x1UL << IAC_ICRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ICRx_IAF13             IAC_ICRx_IAF13_Msk                  /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */
+#define IAC_ICRx_IAF14_Pos         (14U)
+#define IAC_ICRx_IAF14_Msk         (0x1UL << IAC_ICRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ICRx_IAF14             IAC_ICRx_IAF14_Msk                  /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */
+#define IAC_ICRx_IAF15_Pos         (15U)
+#define IAC_ICRx_IAF15_Msk         (0x1UL << IAC_ICRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ICRx_IAF15             IAC_ICRx_IAF15_Msk                  /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */
+#define IAC_ICRx_IAF16_Pos         (16U)
+#define IAC_ICRx_IAF16_Msk         (0x1UL << IAC_ICRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ICRx_IAF16             IAC_ICRx_IAF16_Msk                  /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */
+#define IAC_ICRx_IAF17_Pos         (17U)
+#define IAC_ICRx_IAF17_Msk         (0x1UL << IAC_ICRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ICRx_IAF17             IAC_ICRx_IAF17_Msk                  /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */
+#define IAC_ICRx_IAF18_Pos         (18U)
+#define IAC_ICRx_IAF18_Msk         (0x1UL << IAC_ICRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ICRx_IAF18             IAC_ICRx_IAF18_Msk                  /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */
+#define IAC_ICRx_IAF19_Pos         (19U)
+#define IAC_ICRx_IAF19_Msk         (0x1UL << IAC_ICRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ICRx_IAF19             IAC_ICRx_IAF19_Msk                  /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */
+#define IAC_ICRx_IAF20_Pos         (20U)
+#define IAC_ICRx_IAF20_Msk         (0x1UL << IAC_ICRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ICRx_IAF20             IAC_ICRx_IAF20_Msk                  /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */
+#define IAC_ICRx_IAF21_Pos         (21U)
+#define IAC_ICRx_IAF21_Msk         (0x1UL << IAC_ICRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ICRx_IAF21             IAC_ICRx_IAF21_Msk                  /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */
+#define IAC_ICRx_IAF22_Pos         (22U)
+#define IAC_ICRx_IAF22_Msk         (0x1UL << IAC_ICRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ICRx_IAF22             IAC_ICRx_IAF22_Msk                  /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */
+#define IAC_ICRx_IAF23_Pos         (23U)
+#define IAC_ICRx_IAF23_Msk         (0x1UL << IAC_ICRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ICRx_IAF23             IAC_ICRx_IAF23_Msk                  /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */
+#define IAC_ICRx_IAF24_Pos         (24U)
+#define IAC_ICRx_IAF24_Msk         (0x1UL << IAC_ICRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ICRx_IAF24             IAC_ICRx_IAF24_Msk                  /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */
+#define IAC_ICRx_IAF25_Pos         (25U)
+#define IAC_ICRx_IAF25_Msk         (0x1UL << IAC_ICRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ICRx_IAF25             IAC_ICRx_IAF25_Msk                  /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */
+#define IAC_ICRx_IAF26_Pos         (26U)
+#define IAC_ICRx_IAF26_Msk         (0x1UL << IAC_ICRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ICRx_IAF26             IAC_ICRx_IAF26_Msk                  /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */
+#define IAC_ICRx_IAF27_Pos         (27U)
+#define IAC_ICRx_IAF27_Msk         (0x1UL << IAC_ICRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ICRx_IAF27             IAC_ICRx_IAF27_Msk                  /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */
+#define IAC_ICRx_IAF28_Pos         (28U)
+#define IAC_ICRx_IAF28_Msk         (0x1UL << IAC_ICRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ICRx_IAF28             IAC_ICRx_IAF28_Msk                  /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */
+#define IAC_ICRx_IAF29_Pos         (29U)
+#define IAC_ICRx_IAF29_Msk         (0x1UL << IAC_ICRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ICRx_IAF29             IAC_ICRx_IAF29_Msk                  /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */
+#define IAC_ICRx_IAF30_Pos         (30U)
+#define IAC_ICRx_IAF30_Msk         (0x1UL << IAC_ICRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ICRx_IAF30             IAC_ICRx_IAF30_Msk                  /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */
+#define IAC_ICRx_IAF31_Pos         (31U)
+#define IAC_ICRx_IAF31_Msk         (0x1UL << IAC_ICRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ICRx_IAF31             IAC_ICRx_IAF31_Msk                  /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */
+
+/******************  Bit definition for IAC_IISRx register  *******************/
+#define IAC_IISRx_ILACIN0_Pos      (0U)
+#define IAC_IISRx_ILACIN0_Msk      (0x1UL << IAC_IISRx_ILACIN0_Pos)     /*!< 0x00000001 */
+#define IAC_IISRx_ILACIN0          IAC_IISRx_ILACIN0_Msk               /*!< illegal access input 0 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN1_Pos      (1U)
+#define IAC_IISRx_ILACIN1_Msk      (0x1UL << IAC_IISRx_ILACIN1_Pos)     /*!< 0x00000002 */
+#define IAC_IISRx_ILACIN1          IAC_IISRx_ILACIN1_Msk               /*!< illegal access input 1 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN2_Pos      (2U)
+#define IAC_IISRx_ILACIN2_Msk      (0x1UL << IAC_IISRx_ILACIN2_Pos)     /*!< 0x00000004 */
+#define IAC_IISRx_ILACIN2          IAC_IISRx_ILACIN2_Msk               /*!< illegal access input 2 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN3_Pos      (3U)
+#define IAC_IISRx_ILACIN3_Msk      (0x1UL << IAC_IISRx_ILACIN3_Pos)     /*!< 0x00000008 */
+#define IAC_IISRx_ILACIN3          IAC_IISRx_ILACIN3_Msk               /*!< illegal access input 3 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN4_Pos      (4U)
+#define IAC_IISRx_ILACIN4_Msk      (0x1UL << IAC_IISRx_ILACIN4_Pos)     /*!< 0x00000010 */
+#define IAC_IISRx_ILACIN4          IAC_IISRx_ILACIN4_Msk               /*!< illegal access input 4 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN5_Pos      (5U)
+#define IAC_IISRx_ILACIN5_Msk      (0x1UL << IAC_IISRx_ILACIN5_Pos)     /*!< 0x00000020 */
+#define IAC_IISRx_ILACIN5          IAC_IISRx_ILACIN5_Msk               /*!< illegal access input 5 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN6_Pos      (6U)
+#define IAC_IISRx_ILACIN6_Msk      (0x1UL << IAC_IISRx_ILACIN6_Pos)     /*!< 0x00000040 */
+#define IAC_IISRx_ILACIN6          IAC_IISRx_ILACIN6_Msk               /*!< illegal access input 6 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN7_Pos      (7U)
+#define IAC_IISRx_ILACIN7_Msk      (0x1UL << IAC_IISRx_ILACIN7_Pos)     /*!< 0x00000080 */
+#define IAC_IISRx_ILACIN7          IAC_IISRx_ILACIN7_Msk               /*!< illegal access input 7 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN8_Pos      (8U)
+#define IAC_IISRx_ILACIN8_Msk      (0x1UL << IAC_IISRx_ILACIN8_Pos)     /*!< 0x00000100 */
+#define IAC_IISRx_ILACIN8          IAC_IISRx_ILACIN8_Msk               /*!< illegal access input 8 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN9_Pos      (9U)
+#define IAC_IISRx_ILACIN9_Msk      (0x1UL << IAC_IISRx_ILACIN9_Pos)     /*!< 0x00000200 */
+#define IAC_IISRx_ILACIN9          IAC_IISRx_ILACIN9_Msk               /*!< illegal access input 9 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN10_Pos     (10U)
+#define IAC_IISRx_ILACIN10_Msk     (0x1UL << IAC_IISRx_ILACIN10_Pos)    /*!< 0x00000400 */
+#define IAC_IISRx_ILACIN10         IAC_IISRx_ILACIN10_Msk              /*!< illegal access input 10 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN11_Pos     (11U)
+#define IAC_IISRx_ILACIN11_Msk     (0x1UL << IAC_IISRx_ILACIN11_Pos)    /*!< 0x00000800 */
+#define IAC_IISRx_ILACIN11         IAC_IISRx_ILACIN11_Msk              /*!< illegal access input 11 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN12_Pos     (12U)
+#define IAC_IISRx_ILACIN12_Msk     (0x1UL << IAC_IISRx_ILACIN12_Pos)    /*!< 0x00001000 */
+#define IAC_IISRx_ILACIN12         IAC_IISRx_ILACIN12_Msk              /*!< illegal access input 12 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN13_Pos     (13U)
+#define IAC_IISRx_ILACIN13_Msk     (0x1UL << IAC_IISRx_ILACIN13_Pos)    /*!< 0x00002000 */
+#define IAC_IISRx_ILACIN13         IAC_IISRx_ILACIN13_Msk              /*!< illegal access input 13 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN14_Pos     (14U)
+#define IAC_IISRx_ILACIN14_Msk     (0x1UL << IAC_IISRx_ILACIN14_Pos)    /*!< 0x00004000 */
+#define IAC_IISRx_ILACIN14         IAC_IISRx_ILACIN14_Msk              /*!< illegal access input 14 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN15_Pos     (15U)
+#define IAC_IISRx_ILACIN15_Msk     (0x1UL << IAC_IISRx_ILACIN15_Pos)    /*!< 0x00008000 */
+#define IAC_IISRx_ILACIN15         IAC_IISRx_ILACIN15_Msk              /*!< illegal access input 15 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN16_Pos     (16U)
+#define IAC_IISRx_ILACIN16_Msk     (0x1UL << IAC_IISRx_ILACIN16_Pos)    /*!< 0x00010000 */
+#define IAC_IISRx_ILACIN16         IAC_IISRx_ILACIN16_Msk              /*!< illegal access input 16 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN17_Pos     (17U)
+#define IAC_IISRx_ILACIN17_Msk     (0x1UL << IAC_IISRx_ILACIN17_Pos)    /*!< 0x00020000 */
+#define IAC_IISRx_ILACIN17         IAC_IISRx_ILACIN17_Msk              /*!< illegal access input 17 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN18_Pos     (18U)
+#define IAC_IISRx_ILACIN18_Msk     (0x1UL << IAC_IISRx_ILACIN18_Pos)    /*!< 0x00040000 */
+#define IAC_IISRx_ILACIN18         IAC_IISRx_ILACIN18_Msk              /*!< illegal access input 18 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN19_Pos     (19U)
+#define IAC_IISRx_ILACIN19_Msk     (0x1UL << IAC_IISRx_ILACIN19_Pos)    /*!< 0x00080000 */
+#define IAC_IISRx_ILACIN19         IAC_IISRx_ILACIN19_Msk              /*!< illegal access input 19 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN20_Pos     (20U)
+#define IAC_IISRx_ILACIN20_Msk     (0x1UL << IAC_IISRx_ILACIN20_Pos)    /*!< 0x00100000 */
+#define IAC_IISRx_ILACIN20         IAC_IISRx_ILACIN20_Msk              /*!< illegal access input 20 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN21_Pos     (21U)
+#define IAC_IISRx_ILACIN21_Msk     (0x1UL << IAC_IISRx_ILACIN21_Pos)    /*!< 0x00200000 */
+#define IAC_IISRx_ILACIN21         IAC_IISRx_ILACIN21_Msk              /*!< illegal access input 21 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN22_Pos     (22U)
+#define IAC_IISRx_ILACIN22_Msk     (0x1UL << IAC_IISRx_ILACIN22_Pos)    /*!< 0x00400000 */
+#define IAC_IISRx_ILACIN22         IAC_IISRx_ILACIN22_Msk              /*!< illegal access input 22 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN23_Pos     (23U)
+#define IAC_IISRx_ILACIN23_Msk     (0x1UL << IAC_IISRx_ILACIN23_Pos)    /*!< 0x00800000 */
+#define IAC_IISRx_ILACIN23         IAC_IISRx_ILACIN23_Msk              /*!< illegal access input 23 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN24_Pos     (24U)
+#define IAC_IISRx_ILACIN24_Msk     (0x1UL << IAC_IISRx_ILACIN24_Pos)    /*!< 0x01000000 */
+#define IAC_IISRx_ILACIN24         IAC_IISRx_ILACIN24_Msk              /*!< illegal access input 24 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN25_Pos     (25U)
+#define IAC_IISRx_ILACIN25_Msk     (0x1UL << IAC_IISRx_ILACIN25_Pos)    /*!< 0x02000000 */
+#define IAC_IISRx_ILACIN25         IAC_IISRx_ILACIN25_Msk              /*!< illegal access input 25 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN26_Pos     (26U)
+#define IAC_IISRx_ILACIN26_Msk     (0x1UL << IAC_IISRx_ILACIN26_Pos)    /*!< 0x04000000 */
+#define IAC_IISRx_ILACIN26         IAC_IISRx_ILACIN26_Msk              /*!< illegal access input 26 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN27_Pos     (27U)
+#define IAC_IISRx_ILACIN27_Msk     (0x1UL << IAC_IISRx_ILACIN27_Pos)    /*!< 0x08000000 */
+#define IAC_IISRx_ILACIN27         IAC_IISRx_ILACIN27_Msk              /*!< illegal access input 27 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN28_Pos     (28U)
+#define IAC_IISRx_ILACIN28_Msk     (0x1UL << IAC_IISRx_ILACIN28_Pos)    /*!< 0x10000000 */
+#define IAC_IISRx_ILACIN28         IAC_IISRx_ILACIN28_Msk              /*!< illegal access input 28 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN29_Pos     (29U)
+#define IAC_IISRx_ILACIN29_Msk     (0x1UL << IAC_IISRx_ILACIN29_Pos)    /*!< 0x20000000 */
+#define IAC_IISRx_ILACIN29         IAC_IISRx_ILACIN29_Msk              /*!< illegal access input 29 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN30_Pos     (30U)
+#define IAC_IISRx_ILACIN30_Msk     (0x1UL << IAC_IISRx_ILACIN30_Pos)    /*!< 0x40000000 */
+#define IAC_IISRx_ILACIN30         IAC_IISRx_ILACIN30_Msk              /*!< illegal access input 30 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN31_Pos     (31U)
+#define IAC_IISRx_ILACIN31_Msk     (0x1UL << IAC_IISRx_ILACIN31_Pos)    /*!< 0x80000000 */
+#define IAC_IISRx_ILACIN31         IAC_IISRx_ILACIN31_Msk              /*!< illegal access input 31 (i = 0 to 31) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos                    (2U)
+#define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
+#define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos                       (3U)
+#define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
+#define RNG_CR_IE                           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos                      (5U)
+#define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
+#define RNG_CR_CED                          RNG_CR_CED_Msk
+#define RNG_CR_ARDIS_Pos                    (7U)
+#define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
+#define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
+#define RNG_CR_RNG_CONFIG3_Pos              (8U)
+#define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
+#define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
+#define RNG_CR_NISTC_Pos                    (12U)
+#define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
+#define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
+#define RNG_CR_RNG_CONFIG2_Pos              (13U)
+#define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
+#define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
+#define RNG_CR_CLKDIV_Pos                   (16U)
+#define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
+#define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
+#define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
+#define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
+#define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
+#define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
+#define RNG_CR_RNG_CONFIG1_Pos              (20U)
+#define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
+#define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
+#define RNG_CR_CONDRST_Pos                  (30U)
+#define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
+#define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
+#define RNG_CR_CONFIGLOCK_Pos               (31U)
+#define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
+#define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos                     (0U)
+#define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
+#define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos                     (1U)
+#define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
+#define RNG_SR_CECS                         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos                     (2U)
+#define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
+#define RNG_SR_SECS                         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos                     (5U)
+#define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
+#define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos                     (6U)
+#define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
+#define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
+
+/********************  Bits definition for RNG_HTCR register  *******************/
+#define RNG_HTCR_HTCFG_Pos                  (0U)
+#define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
+#define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU_Pos                       (0U)
+#define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                           RTC_TR_SU_Msk
+#define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
+#define RTC_TR_ST_Pos                       (4U)
+#define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                           RTC_TR_ST_Msk
+#define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TR_MNU_Pos                      (8U)
+#define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                          RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TR_MNT_Pos                      (12U)
+#define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                          RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TR_HU_Pos                       (16U)
+#define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                           RTC_TR_HU_Msk
+#define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TR_HT_Pos                       (20U)
+#define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                           RTC_TR_HT_Msk
+#define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TR_PM_Pos                       (22U)
+#define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                           RTC_TR_PM_Msk
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU_Pos                       (0U)
+#define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                           RTC_DR_DU_Msk
+#define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
+#define RTC_DR_DT_Pos                       (4U)
+#define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                           RTC_DR_DT_Msk
+#define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_DR_MU_Pos                       (8U)
+#define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                           RTC_DR_MU_Msk
+#define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_DR_MT_Pos                       (12U)
+#define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                           RTC_DR_MT_Msk
+#define RTC_DR_WDU_Pos                      (13U)
+#define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                          RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_DR_YU_Pos                       (16U)
+#define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                           RTC_DR_YU_Msk
+#define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
+#define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
+#define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
+#define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
+#define RTC_DR_YT_Pos                       (20U)
+#define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                           RTC_DR_YT_Msk
+#define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
+#define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
+#define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
+#define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                      (0U)
+#define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_SSR_SS                          RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_ICSR register  ******************/
+#define RTC_ICSR_WUTWF_Pos                  (2U)
+#define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
+#define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
+#define RTC_ICSR_SHPF_Pos                   (3U)
+#define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
+#define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
+#define RTC_ICSR_INITS_Pos                  (4U)
+#define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
+#define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
+#define RTC_ICSR_RSF_Pos                    (5U)
+#define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
+#define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
+#define RTC_ICSR_INITF_Pos                  (6U)
+#define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
+#define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
+#define RTC_ICSR_INIT_Pos                   (7U)
+#define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
+#define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
+#define RTC_ICSR_BIN_Pos                    (8U)
+#define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
+#define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
+#define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
+#define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
+#define RTC_ICSR_BCDU_Pos                   (10U)
+#define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
+#define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
+#define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
+#define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
+#define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
+#define RTC_ICSR_RECALPF_Pos                (16U)
+#define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
+#define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_S_Pos               (0U)
+#define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
+#define RTC_PRER_PREDIV_A_Pos               (16U)
+#define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos                    (0U)
+#define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
+#define RTC_WUTR_WUTOCLR_Pos                (16U)
+#define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
+#define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_WUCKSEL_Pos                  (0U)
+#define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
+#define RTC_CR_TSEDGE_Pos                   (3U)
+#define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
+#define RTC_CR_REFCKON_Pos                  (4U)
+#define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
+#define RTC_CR_BYPSHAD_Pos                  (5U)
+#define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
+#define RTC_CR_FMT_Pos                      (6U)
+#define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                          RTC_CR_FMT_Msk
+#define RTC_CR_SSRUIE_Pos                   (7U)
+#define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
+#define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
+#define RTC_CR_ALRAE_Pos                    (8U)
+#define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
+#define RTC_CR_ALRBE_Pos                    (9U)
+#define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
+#define RTC_CR_WUTE_Pos                     (10U)
+#define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
+#define RTC_CR_TSE_Pos                      (11U)
+#define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                          RTC_CR_TSE_Msk
+#define RTC_CR_ALRAIE_Pos                   (12U)
+#define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
+#define RTC_CR_ALRBIE_Pos                   (13U)
+#define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
+#define RTC_CR_WUTIE_Pos                    (14U)
+#define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
+#define RTC_CR_TSIE_Pos                     (15U)
+#define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
+#define RTC_CR_ADD1H_Pos                    (16U)
+#define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
+#define RTC_CR_SUB1H_Pos                    (17U)
+#define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
+#define RTC_CR_BKP_Pos                      (18U)
+#define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                          RTC_CR_BKP_Msk
+#define RTC_CR_COSEL_Pos                    (19U)
+#define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
+#define RTC_CR_POL_Pos                      (20U)
+#define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                          RTC_CR_POL_Msk
+#define RTC_CR_OSEL_Pos                     (21U)
+#define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
+#define RTC_CR_COE_Pos                      (23U)
+#define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                          RTC_CR_COE_Msk
+#define RTC_CR_ITSE_Pos                     (24U)
+#define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
+#define RTC_CR_TAMPTS_Pos                   (25U)
+#define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
+#define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
+#define RTC_CR_TAMPOE_Pos                   (26U)
+#define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
+#define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
+#define RTC_CR_ALRAFCLR_Pos                 (27U)
+#define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
+#define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
+#define RTC_CR_ALRBFCLR_Pos                 (28U)
+#define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
+#define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
+#define RTC_CR_TAMPALRM_PU_Pos              (29U)
+#define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
+#define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
+#define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
+#define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
+#define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
+#define RTC_CR_OUT2EN_Pos                   (31U)
+#define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
+#define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
+
+/********************  Bits definition for RTC_PRIVCFGR register  *****************/
+#define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
+#define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
+#define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
+#define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
+#define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
+#define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
+#define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
+#define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
+#define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
+#define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
+#define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
+#define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
+#define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
+#define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
+#define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
+#define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
+#define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
+#define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
+#define RTC_PRIVCFGR_PRIV_Pos               (15U)
+#define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
+#define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
+
+/********************  Bits definition for RTC_SECCFGR register  ******************/
+#define RTC_SECCFGR_ALRASEC_Pos             (0U)
+#define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
+#define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
+#define RTC_SECCFGR_ALRBSEC_Pos             (1U)
+#define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
+#define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
+#define RTC_SECCFGR_WUTSEC_Pos              (2U)
+#define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
+#define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
+#define RTC_SECCFGR_TSSEC_Pos               (3U)
+#define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
+#define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
+#define RTC_SECCFGR_CALSEC_Pos              (13U)
+#define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
+#define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
+#define RTC_SECCFGR_INITSEC_Pos             (14U)
+#define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
+#define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
+#define RTC_SECCFGR_SEC_Pos                 (15U)
+#define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
+#define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                     (0U)
+#define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALM_Pos                   (0U)
+#define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
+#define RTC_CALR_LPCAL_Pos                  (12U)
+#define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
+#define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALW16_Pos                 (13U)
+#define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
+#define RTC_CALR_CALW8_Pos                  (14U)
+#define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALP_Pos                   (15U)
+#define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos                (0U)
+#define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos                (31U)
+#define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_SU_Pos                     (0U)
+#define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
+#define RTC_TSTR_ST_Pos                     (4U)
+#define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_TSTR_MNU_Pos                    (8U)
+#define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_TSTR_MNT_Pos                    (12U)
+#define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_TSTR_HU_Pos                     (16U)
+#define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_TSTR_HT_Pos                     (20U)
+#define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_TSTR_PM_Pos                     (22U)
+#define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_DU_Pos                     (0U)
+#define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
+#define RTC_TSDR_DT_Pos                     (4U)
+#define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
+#define RTC_TSDR_MU_Pos                     (8U)
+#define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
+#define RTC_TSDR_MT_Pos                     (12U)
+#define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
+#define RTC_TSDR_WDU_Pos                    (13U)
+#define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos                    (0U)
+#define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
+#define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_SU_Pos                   (0U)
+#define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMAR_ST_Pos                   (4U)
+#define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMAR_MSK1_Pos                 (7U)
+#define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_MNU_Pos                  (8U)
+#define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMAR_MNT_Pos                  (12U)
+#define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMAR_MSK2_Pos                 (15U)
+#define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_HU_Pos                   (16U)
+#define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMAR_HT_Pos                   (20U)
+#define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMAR_PM_Pos                   (22U)
+#define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_MSK3_Pos                 (23U)
+#define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_DU_Pos                   (24U)
+#define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMAR_DT_Pos                   (28U)
+#define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMAR_WDSEL_Pos                (30U)
+#define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_MSK4_Pos                 (31U)
+#define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_SS_Pos                 (0U)
+#define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
+#define RTC_ALRMASSR_MASKSS_Pos             (24U)
+#define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMASSR_SSCLR_Pos              (31U)
+#define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_SU_Pos                   (0U)
+#define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMBR_ST_Pos                   (4U)
+#define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMBR_MSK1_Pos                 (7U)
+#define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_MNU_Pos                  (8U)
+#define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMBR_MNT_Pos                  (12U)
+#define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMBR_MSK2_Pos                 (15U)
+#define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_HU_Pos                   (16U)
+#define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMBR_HT_Pos                   (20U)
+#define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMBR_PM_Pos                   (22U)
+#define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_MSK3_Pos                 (23U)
+#define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_DU_Pos                   (24U)
+#define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMBR_DT_Pos                   (28U)
+#define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMBR_WDSEL_Pos                (30U)
+#define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_MSK4_Pos                 (31U)
+#define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_SS_Pos                 (0U)
+#define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
+#define RTC_ALRMBSSR_MASKSS_Pos             (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMBSSR_SSCLR_Pos              (31U)
+#define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_SR register  *******************/
+#define RTC_SR_ALRAF_Pos                    (0U)
+#define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
+#define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
+#define RTC_SR_ALRBF_Pos                    (1U)
+#define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
+#define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
+#define RTC_SR_WUTF_Pos                     (2U)
+#define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
+#define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
+#define RTC_SR_TSF_Pos                      (3U)
+#define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
+#define RTC_SR_TSF                          RTC_SR_TSF_Msk
+#define RTC_SR_TSOVF_Pos                    (4U)
+#define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
+#define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
+#define RTC_SR_ITSF_Pos                     (5U)
+#define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
+#define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
+#define RTC_SR_SSRUF_Pos                    (6U)
+#define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
+#define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
+
+/********************  Bits definition for RTC_MISR register  *****************/
+#define RTC_MISR_ALRAMF_Pos                 (0U)
+#define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
+#define RTC_MISR_ALRBMF_Pos                 (1U)
+#define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
+#define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
+#define RTC_MISR_WUTMF_Pos                  (2U)
+#define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
+#define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
+#define RTC_MISR_TSMF_Pos                   (3U)
+#define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
+#define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
+#define RTC_MISR_TSOVMF_Pos                 (4U)
+#define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
+#define RTC_MISR_ITSMF_Pos                  (5U)
+#define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
+#define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
+#define RTC_MISR_SSRUMF_Pos                 (6U)
+#define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
+#define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SMISR register  *****************/
+#define RTC_SMISR_ALRAMF_Pos                (0U)
+#define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
+#define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
+#define RTC_SMISR_ALRBMF_Pos                (1U)
+#define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
+#define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
+#define RTC_SMISR_WUTMF_Pos                 (2U)
+#define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
+#define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
+#define RTC_SMISR_TSMF_Pos                  (3U)
+#define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
+#define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
+#define RTC_SMISR_TSOVMF_Pos                (4U)
+#define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
+#define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
+#define RTC_SMISR_ITSMF_Pos                 (5U)
+#define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
+#define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
+#define RTC_SMISR_SSRUMF_Pos                (6U)
+#define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
+#define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SCR register  ******************/
+#define RTC_SCR_CALRAF_Pos                  (0U)
+#define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
+#define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
+#define RTC_SCR_CALRBF_Pos                  (1U)
+#define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
+#define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
+#define RTC_SCR_CWUTF_Pos                   (2U)
+#define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
+#define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
+#define RTC_SCR_CTSF_Pos                    (3U)
+#define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
+#define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
+#define RTC_SCR_CTSOVF_Pos                  (4U)
+#define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
+#define RTC_SCR_CITSF_Pos                   (5U)
+#define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
+#define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
+#define RTC_SCR_CSSRUF_Pos                  (6U)
+#define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
+#define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
+
+/********************  Bits definition for RTC_ALRABINR register  ******************/
+#define RTC_ALRABINR_SS_Pos                 (0U)
+#define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
+
+/********************  Bits definition for RTC_ALRBBINR register  ******************/
+#define RTC_ALRBBINR_SS_Pos                 (0U)
+#define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos                  (0U)
+#define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
+#define SAI_GCR_SYNCOUT_Pos                 (4U)
+#define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos                   (0U)
+#define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
+#define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
+#define SAI_xCR1_PRTCFG_Pos                 (2U)
+#define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
+#define SAI_xCR1_DS_Pos                     (5U)
+#define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
+#define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
+#define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
+#define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
+#define SAI_xCR1_LSBFIRST_Pos               (8U)
+#define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos                  (9U)
+#define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
+#define SAI_xCR1_SYNCEN_Pos                 (10U)
+#define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
+#define SAI_xCR1_MONO_Pos                   (12U)
+#define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
+#define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos                (13U)
+#define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos                  (16U)
+#define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos                  (17U)
+#define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos                  (19U)
+#define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
+#define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
+#define SAI_xCR1_MCKDIV_Pos                 (20U)
+#define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
+#define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
+#define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
+#define SAI_xCR1_OSR_Pos                    (26U)
+#define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
+#define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
+#define SAI_xCR1_MCKEN_Pos                  (27U)
+#define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos                    (0U)
+#define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
+#define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
+#define SAI_xCR2_FFLUSH_Pos                 (3U)
+#define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos                   (4U)
+#define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
+#define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos                   (5U)
+#define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
+#define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos                (6U)
+#define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
+#define SAI_xCR2_MUTECNT_Pos                (7U)
+#define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
+#define SAI_xCR2_CPL_Pos                    (13U)
+#define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
+#define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos                   (14U)
+#define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
+#define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos                   (0U)
+#define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
+#define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
+#define SAI_xFRCR_FSALL_Pos                 (8U)
+#define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
+#define SAI_xFRCR_FSDEF_Pos                 (16U)
+#define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos                 (17U)
+#define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos                 (18U)
+#define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos                (0U)
+#define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
+#define SAI_xSLOTR_SLOTSZ_Pos               (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
+#define SAI_xSLOTR_NBSLOT_Pos               (8U)
+#define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
+#define SAI_xSLOTR_SLOTEN_Pos               (16U)
+#define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos               (0U)
+#define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos              (1U)
+#define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos               (2U)
+#define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos                 (3U)
+#define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos                (4U)
+#define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos               (5U)
+#define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos               (6U)
+#define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos                  (0U)
+#define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos                 (1U)
+#define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos                  (2U)
+#define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos                    (3U)
+#define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos                   (4U)
+#define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos                  (5U)
+#define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos                  (6U)
+#define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
+#define SAI_xSR_FLVL_Pos                    (16U)
+#define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
+#define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos              (0U)
+#define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos             (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos              (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos                (3U)
+#define SAI_xCLRFR_CFREQ_Msk                (0x1UL << SAI_xCLRFR_CFREQ_Pos)         /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ                    SAI_xCLRFR_CFREQ_Msk                    /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos               (4U)
+#define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos              (5U)
+#define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos              (6U)
+#define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos                    (0U)
+#define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA                        SAI_xDR_DATA_Msk
+
+/******************  Bit definition for SAI_PDMCR register  *******************/
+#define SAI_PDMCR_PDMEN_Pos                 (0U)
+#define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
+#define SAI_PDMCR_MICNBR_Pos                (4U)
+#define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
+#define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
+#define SAI_PDMCR_CKEN1_Pos                 (8U)
+#define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
+#define SAI_PDMCR_CKEN2_Pos                 (9U)
+#define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
+#define SAI_PDMCR_CKEN3_Pos                 (10U)
+#define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
+#define SAI_PDMCR_CKEN4_Pos                 (11U)
+#define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos               (0U)
+#define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
+#define SAI_PDMDLY_DLYM1R_Pos               (4U)
+#define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
+#define SAI_PDMDLY_DLYM2L_Pos               (8U)
+#define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
+#define SAI_PDMDLY_DLYM2R_Pos               (12U)
+#define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
+#define SAI_PDMDLY_DLYM3L_Pos               (16U)
+#define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
+#define SAI_PDMDLY_DLYM3R_Pos               (20U)
+#define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
+#define SAI_PDMDLY_DLYM4L_Pos               (24U)
+#define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
+#define SAI_PDMDLY_DLYM4R_Pos               (28U)
+#define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos             (0U)
+#define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos             (2U)
+#define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos           (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos              (4U)
+#define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos              (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos              (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_WIDBUS_Pos              (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
+#define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos                 (18U)
+#define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos                (0U)
+#define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos              (0U)
+#define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos              (6U)
+#define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos               (7U)
+#define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
+#define SDMMC_CMD_WAITRESP_Pos              (8U)
+#define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITINT_Pos               (10U)
+#define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos              (11U)
+#define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos                (12U)
+#define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos                (13U)
+#define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos              (14U)
+#define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos                (15U)
+#define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos           (0U)
+#define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos           (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos                (0U)
+#define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos               (1U)
+#define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos              (2U)
+#define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+#define SDMMC_DCTRL_RWSTART_Pos             (8U)
+#define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos              (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos               (10U)
+#define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos              (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos             (13U)
+#define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos              (0U)
+#define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos              (1U)
+#define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos              (2U)
+#define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos              (3U)
+#define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos              (4U)
+#define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos               (5U)
+#define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos               (6U)
+#define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos               (7U)
+#define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos               (8U)
+#define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos                 (9U)
+#define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos               (10U)
+#define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos                (11U)
+#define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos               (12U)
+#define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos               (13U)
+#define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos              (14U)
+#define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos              (15U)
+#define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos               (16U)
+#define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos               (17U)
+#define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos               (18U)
+#define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos               (19U)
+#define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos                (20U)
+#define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos             (21U)
+#define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos                (22U)
+#define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos               (23U)
+#define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos                (25U)
+#define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos                (26U)
+#define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos                (27U)
+#define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos               (28U)
+#define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos             (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos             (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos             (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos              (5U)
+#define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos              (6U)
+#define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos              (7U)
+#define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos              (8U)
+#define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos                (9U)
+#define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos              (10U)
+#define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos               (11U)
+#define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos               (22U)
+#define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos              (23U)
+#define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos               (25U)
+#define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos               (26U)
+#define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos               (27U)
+#define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos              (28U)
+#define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos            (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos            (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos            (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos            (8U)
+#define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos              (9U)
+#define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos            (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos             (11U)
+#define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
+#define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos             (22U)
+#define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos            (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos             (25U)
+#define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos             (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos            (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFOTHR register  *******************/
+#define SDMMC_FIFOTHR_THR_Pos               (0U)
+#define SDMMC_FIFOTHR_THR_Msk               (0xFUL << SDMMC_FIFOTHR_THR_Pos)        /*!< 0x0000000F */
+#define SDMMC_FIFOTHR_THR                   SDMMC_FIFOTHR_THR_Msk                   /*!<FIFO threshold */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos             (0U)
+#define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos               (0U)
+#define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos            (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos        (6U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0x7FFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0001FFC0 */
+#define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk              /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASER register  ***************/
+#define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */
+
+/*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
+#define SDMMC_IDMALAR_IDMALA_Pos            (0U)
+#define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
+#define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
+#define SDMMC_IDMALAR_ABR_Pos               (29U)
+#define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
+#define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
+#define SDMMC_IDMALAR_ULS_Pos               (30U)
+#define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
+#define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
+#define SDMMC_IDMALAR_ULA_Pos               (31U)
+#define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
+#define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */
+
+/*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
+#define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos                     (0U)
+#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
+#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
+#define SPI_CR1_MASRX_Pos                   (8U)
+#define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
+#define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
+#define SPI_CR1_CSTART_Pos                  (9U)
+#define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
+#define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
+#define SPI_CR1_CSUSP_Pos                   (10U)
+#define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
+#define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
+#define SPI_CR1_HDDIR_Pos                   (11U)
+#define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
+#define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
+#define SPI_CR1_SSI_Pos                     (12U)
+#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
+#define SPI_CR1_CRC33_17_Pos                (13U)
+#define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
+#define SPI_CR1_RCRCINI_Pos                 (14U)
+#define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
+#define SPI_CR1_TCRCINI_Pos                 (15U)
+#define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
+#define SPI_CR1_IOLOCK_Pos                  (16U)
+#define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSIZE_Pos                   (0U)
+#define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
+
+/*******************  Bit definition for SPI_CFG1 register  *******************/
+#define SPI_CFG1_DSIZE_Pos                  (0U)
+#define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
+#define SPI_CFG1_FTHLV_Pos                  (5U)
+#define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
+#define SPI_CFG1_UDRCFG_Pos                 (9U)
+#define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
+#define SPI_CFG1_RXDMAEN_Pos                (14U)
+#define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
+#define SPI_CFG1_TXDMAEN_Pos                (15U)
+#define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
+#define SPI_CFG1_CRCSIZE_Pos                (16U)
+#define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
+#define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
+#define SPI_CFG1_CRCEN_Pos                  (22U)
+#define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
+#define SPI_CFG1_MBR_Pos                    (28U)
+#define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
+#define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
+#define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
+#define SPI_CFG1_BPASS_Pos                  (31U)
+#define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
+#define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
+
+/*******************  Bit definition for SPI_CFG2 register  *******************/
+#define SPI_CFG2_MSSI_Pos                   (0U)
+#define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
+#define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
+#define SPI_CFG2_MIDI_Pos                   (4U)
+#define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
+#define SPI_CFG2_RDIOM_Pos                  (13U)
+#define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
+#define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
+#define SPI_CFG2_RDIOP_Pos                  (14U)
+#define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
+#define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
+#define SPI_CFG2_IOSWP_Pos                  (15U)
+#define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
+#define SPI_CFG2_COMM_Pos                   (17U)
+#define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
+#define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
+#define SPI_CFG2_SP_Pos                     (19U)
+#define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
+#define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
+#define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
+#define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
+#define SPI_CFG2_MASTER_Pos                 (22U)
+#define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
+#define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
+#define SPI_CFG2_LSBFRST_Pos                (23U)
+#define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
+#define SPI_CFG2_CPHA_Pos                   (24U)
+#define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
+#define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
+#define SPI_CFG2_CPOL_Pos                   (25U)
+#define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
+#define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
+#define SPI_CFG2_SSM_Pos                    (26U)
+#define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
+#define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
+#define SPI_CFG2_SSIOP_Pos                  (28U)
+#define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos                   (29U)
+#define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
+#define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos                   (30U)
+#define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
+#define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
+#define SPI_CFG2_AFCNTR_Pos                 (31U)
+#define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos                   (0U)
+#define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
+#define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
+#define SPI_IER_TXPIE_Pos                   (1U)
+#define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
+#define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
+#define SPI_IER_DXPIE_Pos                   (2U)
+#define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
+#define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
+#define SPI_IER_EOTIE_Pos                   (3U)
+#define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
+#define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
+#define SPI_IER_TXTFIE_Pos                  (4U)
+#define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
+#define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
+#define SPI_IER_UDRIE_Pos                   (5U)
+#define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
+#define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
+#define SPI_IER_OVRIE_Pos                   (6U)
+#define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
+#define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
+#define SPI_IER_CRCEIE_Pos                  (7U)
+#define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
+#define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
+#define SPI_IER_TIFREIE_Pos                 (8U)
+#define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
+#define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos                  (9U)
+#define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
+#define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
+
+/*******************  Bit definition for SPI_SR register  *********************/
+#define SPI_SR_RXP_Pos                      (0U)
+#define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
+#define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_TXP_Pos                      (1U)
+#define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
+#define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
+#define SPI_SR_DXP_Pos                      (2U)
+#define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
+#define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_EOT_Pos                      (3U)
+#define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
+#define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_TXTF_Pos                     (4U)
+#define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
+#define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
+#define SPI_SR_UDR_Pos                      (5U)
+#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
+#define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
+#define SPI_SR_OVR_Pos                      (6U)
+#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
+#define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_CRCE_Pos                     (7U)
+#define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
+#define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
+#define SPI_SR_TIFRE_Pos                    (8U)
+#define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
+#define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
+#define SPI_SR_MODF_Pos                     (9U)
+#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
+#define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
+#define SPI_SR_SUSP_Pos                     (11U)
+#define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
+#define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
+#define SPI_SR_TXC_Pos                      (12U)
+#define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
+#define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos                   (13U)
+#define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
+#define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
+#define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos                    (15U)
+#define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
+#define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
+#define SPI_SR_CTSIZE_Pos                   (16U)
+#define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
+
+/*******************  Bit definition for SPI_IFCR register  *******************/
+#define SPI_IFCR_EOTC_Pos                   (3U)
+#define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
+#define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
+#define SPI_IFCR_TXTFC_Pos                  (4U)
+#define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos                   (5U)
+#define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
+#define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
+#define SPI_IFCR_OVRC_Pos                   (6U)
+#define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
+#define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
+#define SPI_IFCR_CRCEC_Pos                  (7U)
+#define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
+#define SPI_IFCR_TIFREC_Pos                 (8U)
+#define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
+#define SPI_IFCR_MODFC_Pos                  (9U)
+#define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
+#define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
+#define SPI_IFCR_SUSPC_Pos                  (11U)
+#define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
+
+/*******************  Bit definition for SPI_TXDR register  *******************/
+#define SPI_TXDR_TXDR_Pos                   (0U)
+#define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  *******************/
+#define SPI_RXDR_RXDR_Pos                   (0U)
+#define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ****************/
+#define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */
+
+/*******************  Bit definition for SPI_TXCRC register  ******************/
+#define SPI_TXCRC_TXCRC_Pos                 (0U)
+#define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ******************/
+#define SPI_RXCRC_RXCRC_Pos                 (0U)
+#define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ******************/
+#define SPI_UDRDR_UDRDR_Pos                 (0U)
+#define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */
+
+/*******************  Bits definition for SPI_I2SCFGR register  ***************/
+#define SPI_I2SCFGR_I2SMOD_Pos              (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)        /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk                  /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos              (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk              (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk                  /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2                (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos              (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk                  /*!<I2SSTD[1:0] I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)       /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk                 /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_DATLEN_Pos              (8U)
+#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk                  /*!<DATLEN[1:0] Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos               (10U)
+#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)         /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk                   /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos               (11U)
+#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)         /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk                   /*!<Serial audio clock polarity */
+#define SPI_I2SCFGR_FIXCH_Pos               (12U)
+#define SPI_I2SCFGR_FIXCH_Msk               (0x1UL << SPI_I2SCFGR_FIXCH_Pos)         /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH                   SPI_I2SCFGR_FIXCH_Msk                   /*!<Fixed channel length in SLAVE */
+#define SPI_I2SCFGR_WSINV_Pos               (13U)
+#define SPI_I2SCFGR_WSINV_Msk               (0x1UL << SPI_I2SCFGR_WSINV_Pos)         /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV                   SPI_I2SCFGR_WSINV_Msk                   /*!<Word select inversion */
+#define SPI_I2SCFGR_DATFMT_Pos              (14U)
+#define SPI_I2SCFGR_DATFMT_Msk              (0x1UL << SPI_I2SCFGR_DATFMT_Pos)        /*!< 0x00003000 */
+#define SPI_I2SCFGR_DATFMT                  SPI_I2SCFGR_DATFMT_Msk                  /*!<Data format */
+#define SPI_I2SCFGR_I2SDIV_Pos              (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk              (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)       /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV                  SPI_I2SCFGR_I2SDIV_Msk                  /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos                 (24U)
+#define SPI_I2SCFGR_ODD_Msk                 (0x1UL << SPI_I2SCFGR_ODD_Pos)           /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD                     SPI_I2SCFGR_ODD_Msk                     /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos               (25U)
+#define SPI_I2SCFGR_MCKOE_Msk               (0x1UL << SPI_I2SCFGR_MCKOE_Pos)         /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE                   SPI_I2SCFGR_MCKOE_Msk                   /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFRXEN_Pos       (0U)
+#define SPDIFRX_CR_SPDIFRXEN_Msk       (0x3UL << SPDIFRX_CR_SPDIFRXEN_Pos)     /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFRXEN           SPDIFRX_CR_SPDIFRXEN_Msk                /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_SPDIFRXEN_0         (0x01UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000001 */
+#define SPDIFRX_CR_SPDIFRXEN_1         (0x02UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000002 */
+#define SPDIFRX_CR_RXDMAEN_Pos         (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk         (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN             SPDIFRX_CR_RXDMAEN_Msk                  /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos          (3U)
+#define SPDIFRX_CR_RXSTEO_Msk          (0x1UL << SPDIFRX_CR_RXSTEO_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO              SPDIFRX_CR_RXSTEO_Msk                   /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos           (4U)
+#define SPDIFRX_CR_DRFMT_Msk           (0x3UL << SPDIFRX_CR_DRFMT_Pos)         /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT               SPDIFRX_CR_DRFMT_Msk                    /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos            (6U)
+#define SPDIFRX_CR_PMSK_Msk            (0x1UL << SPDIFRX_CR_PMSK_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK                SPDIFRX_CR_PMSK_Msk                     /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos            (7U)
+#define SPDIFRX_CR_VMSK_Msk            (0x1UL << SPDIFRX_CR_VMSK_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK                SPDIFRX_CR_VMSK_Msk                     /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos           (8U)
+#define SPDIFRX_CR_CUMSK_Msk           (0x1UL << SPDIFRX_CR_CUMSK_Pos)         /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK               SPDIFRX_CR_CUMSK_Msk                    /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos           (9U)
+#define SPDIFRX_CR_PTMSK_Msk           (0x1UL << SPDIFRX_CR_PTMSK_Pos)         /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK               SPDIFRX_CR_PTMSK_Msk                    /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos         (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk         (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)       /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN             SPDIFRX_CR_CBDMAEN_Msk                  /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos           (11U)
+#define SPDIFRX_CR_CHSEL_Msk           (0x1UL << SPDIFRX_CR_CHSEL_Pos)         /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL               SPDIFRX_CR_CHSEL_Msk                    /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos            (12U)
+#define SPDIFRX_CR_NBTR_Msk            (0x3UL << SPDIFRX_CR_NBTR_Pos)          /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR                SPDIFRX_CR_NBTR_Msk                     /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos             (14U)
+#define SPDIFRX_CR_WFA_Msk             (0x1UL << SPDIFRX_CR_WFA_Pos)           /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA                 SPDIFRX_CR_WFA_Msk                      /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos           (16U)
+#define SPDIFRX_CR_INSEL_Msk           (0x7UL << SPDIFRX_CR_INSEL_Pos)         /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL               SPDIFRX_CR_INSEL_Msk                    /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos           (20U)
+#define SPDIFRX_CR_CKSEN_Msk           (0x1UL << SPDIFRX_CR_CKSEN_Pos)         /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN               SPDIFRX_CR_CKSEN_Msk                    /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos        (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk        (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)      /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN            SPDIFRX_CR_CKSBKPEN_Msk                 /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos         (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk         (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)       /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE             SPDIFRX_IMR_RXNEIE_Msk                  /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos        (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk        (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)      /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE            SPDIFRX_IMR_CSRNEIE_Msk                 /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos         (2U)
+#define SPDIFRX_IMR_PERRIE_Msk         (0x1UL << SPDIFRX_IMR_PERRIE_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE             SPDIFRX_IMR_PERRIE_Msk                  /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos          (3U)
+#define SPDIFRX_IMR_OVRIE_Msk          (0x1UL << SPDIFRX_IMR_OVRIE_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE              SPDIFRX_IMR_OVRIE_Msk                   /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos         (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk         (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE             SPDIFRX_IMR_SBLKIE_Msk                  /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos        (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk        (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)      /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE            SPDIFRX_IMR_SYNCDIE_Msk                 /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos          (6U)
+#define SPDIFRX_IMR_IFEIE_Msk          (0x1UL << SPDIFRX_IMR_IFEIE_Pos)        /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE              SPDIFRX_IMR_IFEIE_Msk                   /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos            (0U)
+#define SPDIFRX_SR_RXNE_Msk            (0x1UL << SPDIFRX_SR_RXNE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE                SPDIFRX_SR_RXNE_Msk                     /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos           (1U)
+#define SPDIFRX_SR_CSRNE_Msk           (0x1UL << SPDIFRX_SR_CSRNE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE               SPDIFRX_SR_CSRNE_Msk                    /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos            (2U)
+#define SPDIFRX_SR_PERR_Msk            (0x1UL << SPDIFRX_SR_PERR_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR                SPDIFRX_SR_PERR_Msk                     /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos             (3U)
+#define SPDIFRX_SR_OVR_Msk             (0x1UL << SPDIFRX_SR_OVR_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR                 SPDIFRX_SR_OVR_Msk                      /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos             (4U)
+#define SPDIFRX_SR_SBD_Msk             (0x1UL << SPDIFRX_SR_SBD_Pos)           /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD                 SPDIFRX_SR_SBD_Msk                      /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos           (5U)
+#define SPDIFRX_SR_SYNCD_Msk           (0x1UL << SPDIFRX_SR_SYNCD_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD               SPDIFRX_SR_SYNCD_Msk                    /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos            (6U)
+#define SPDIFRX_SR_FERR_Msk            (0x1UL << SPDIFRX_SR_FERR_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR                SPDIFRX_SR_FERR_Msk                     /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos            (7U)
+#define SPDIFRX_SR_SERR_Msk            (0x1UL << SPDIFRX_SR_SERR_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR                SPDIFRX_SR_SERR_Msk                     /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos            (8U)
+#define SPDIFRX_SR_TERR_Msk            (0x1UL << SPDIFRX_SR_TERR_Pos)          /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR                SPDIFRX_SR_TERR_Msk                     /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos          (16U)
+#define SPDIFRX_SR_WIDTH5_Msk          (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)     /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5              SPDIFRX_SR_WIDTH5_Msk                   /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos        (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk        (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)      /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF            SPDIFRX_IFCR_PERRCF_Msk                 /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos         (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk         (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)       /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF             SPDIFRX_IFCR_OVRCF_Msk                  /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos         (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk         (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF             SPDIFRX_IFCR_SBDCF_Msk                  /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos       (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk       (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)     /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF           SPDIFRX_IFCR_SYNCDCF_Msk                /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos             (0U)
+#define SPDIFRX_DR0_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)      /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR                 SPDIFRX_DR0_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos             (24U)
+#define SPDIFRX_DR0_PE_Msk             (0x1UL << SPDIFRX_DR0_PE_Pos)           /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE                 SPDIFRX_DR0_PE_Msk                      /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos              (25U)
+#define SPDIFRX_DR0_V_Msk              (0x1UL << SPDIFRX_DR0_V_Pos)            /*!< 0x02000000 */
+#define SPDIFRX_DR0_V                  SPDIFRX_DR0_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos              (26U)
+#define SPDIFRX_DR0_U_Msk              (0x1UL << SPDIFRX_DR0_U_Pos)            /*!< 0x04000000 */
+#define SPDIFRX_DR0_U                  SPDIFRX_DR0_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos              (27U)
+#define SPDIFRX_DR0_C_Msk              (0x1UL << SPDIFRX_DR0_C_Pos)            /*!< 0x08000000 */
+#define SPDIFRX_DR0_C                  SPDIFRX_DR0_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos             (28U)
+#define SPDIFRX_DR0_PT_Msk             (0x3UL << SPDIFRX_DR0_PT_Pos)           /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT                 SPDIFRX_DR0_PT_Msk                      /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos             (8U)
+#define SPDIFRX_DR1_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)      /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR                 SPDIFRX_DR1_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos             (4U)
+#define SPDIFRX_DR1_PT_Msk             (0x3UL << SPDIFRX_DR1_PT_Pos)           /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT                 SPDIFRX_DR1_PT_Msk                      /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos              (3U)
+#define SPDIFRX_DR1_C_Msk              (0x1UL << SPDIFRX_DR1_C_Pos)            /*!< 0x00000008 */
+#define SPDIFRX_DR1_C                  SPDIFRX_DR1_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos              (2U)
+#define SPDIFRX_DR1_U_Msk              (0x1UL << SPDIFRX_DR1_U_Pos)            /*!< 0x00000004 */
+#define SPDIFRX_DR1_U                  SPDIFRX_DR1_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos              (1U)
+#define SPDIFRX_DR1_V_Msk              (0x1UL << SPDIFRX_DR1_V_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_DR1_V                  SPDIFRX_DR1_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos             (0U)
+#define SPDIFRX_DR1_PE_Msk             (0x1UL << SPDIFRX_DR1_PE_Pos)           /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE                 SPDIFRX_DR1_PE_Msk                      /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos          (16U)
+#define SPDIFRX_DR1_DRNL1_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)     /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1              SPDIFRX_DR1_DRNL1_Msk                   /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos          (0U)
+#define SPDIFRX_DR1_DRNL2_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)     /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2              SPDIFRX_DR1_DRNL2_Msk                   /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos            (0U)
+#define SPDIFRX_CSR_USR_Msk            (0xFFFFUL << SPDIFRX_CSR_USR_Pos)       /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR                SPDIFRX_CSR_USR_Msk                     /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos             (16U)
+#define SPDIFRX_CSR_CS_Msk             (0xFFUL << SPDIFRX_CSR_CS_Pos)          /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS                 SPDIFRX_CSR_CS_Msk                      /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos            (24U)
+#define SPDIFRX_CSR_SOB_Msk            (0x1UL << SPDIFRX_CSR_SOB_Pos)          /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB                SPDIFRX_CSR_SOB_Msk                     /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos            (0U)
+#define SPDIFRX_DIR_THI_Msk            (0x1FFFUL << SPDIFRX_DIR_THI_Pos)       /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI                SPDIFRX_DIR_THI_Msk                     /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos            (16U)
+#define SPDIFRX_DIR_TLO_Msk            (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)       /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO                SPDIFRX_DIR_TLO_Msk                     /*!<Threshold HIGH     */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_BOOTCR register  ****************/
+#define SYSCFG_BOOTCR_BOOT0_PD_Pos          (0U)
+#define SYSCFG_BOOTCR_BOOT0_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT0_PD_Pos)   /*!< 0x00000001 */
+#define SYSCFG_BOOTCR_BOOT0_PD              SYSCFG_BOOTCR_BOOT0_PD_Msk              /*!< BOOT0 pin pull-down disable */
+#define SYSCFG_BOOTCR_BOOT1_PD_Pos          (1U)
+#define SYSCFG_BOOTCR_BOOT1_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT1_PD_Pos)   /*!< 0x00000002 */
+#define SYSCFG_BOOTCR_BOOT1_PD              SYSCFG_BOOTCR_BOOT1_PD_Msk              /*!< BOOT1 pin pull-down disable */
+
+/******************  Bit definition for SYSCFG_CM55CR register  ****************/
+#define SYSCFG_CM55CR_FPU_IT_EN_Pos         (0U)
+#define SYSCFG_CM55CR_FPU_IT_EN_Msk         (0x3FUL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x0000003F */
+#define SYSCFG_CM55CR_FPU_IT_EN             SYSCFG_CM55CR_FPU_IT_EN_Msk             /*!< Enable FPU exception */
+#define SYSCFG_CM55CR_FPU_IT_EN_0           (0x1UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55CR_FPU_IT_EN_1           (0x2UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55CR_FPU_IT_EN_2           (0x4UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55CR_FPU_IT_EN_3           (0x8UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000008 */
+#define SYSCFG_CM55CR_FPU_IT_EN_4           (0x10UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000010 */
+#define SYSCFG_CM55CR_FPU_IT_EN_5           (0x20UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000020 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Pos      (16U)
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Msk      (0x1UL << SYSCFG_CM55CR_LOCKSVTAIRCR_Pos) /*!< 0x00010000 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR          SYSCFG_CM55CR_LOCKSVTAIRCR_Msk
+#define SYSCFG_CM55CR_LOCKNSVTOR_Pos        (17U)
+#define SYSCFG_CM55CR_LOCKNSVTOR_Msk        (0x1UL << SYSCFG_CM55CR_LOCKNSVTOR_Pos) /*!< 0x00020000 */
+#define SYSCFG_CM55CR_LOCKNSVTOR            SYSCFG_CM55CR_LOCKNSVTOR_Msk            /*!< Prevent changes to the non-secure vector table base address */
+#define SYSCFG_CM55CR_LOCKSMPU_Pos          (18U)
+#define SYSCFG_CM55CR_LOCKSMPU_Msk          (0x1UL << SYSCFG_CM55CR_LOCKSMPU_Pos)   /*!< 0x00040000 */
+#define SYSCFG_CM55CR_LOCKSMPU              SYSCFG_CM55CR_LOCKSMPU_Msk              /*!< Prevent changes to programmed secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKNSMPU_Pos         (19U)
+#define SYSCFG_CM55CR_LOCKNSMPU_Msk         (0x1UL << SYSCFG_CM55CR_LOCKNSMPU_Pos)  /*!< 0x00080000 */
+#define SYSCFG_CM55CR_LOCKNSMPU             SYSCFG_CM55CR_LOCKNSMPU_Msk             /*!< Prevent changes to programmed non-secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKSAU_Pos           (20U)
+#define SYSCFG_CM55CR_LOCKSAU_Msk           (0x1UL << SYSCFG_CM55CR_LOCKSAU_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CM55CR_LOCKSAU               SYSCFG_CM55CR_LOCKSAU_Msk               /*!< Prevent changes to secure SAU memory regions already programmed */
+#define SYSCFG_CM55CR_LOCKDCAIC_Pos         (21U)
+#define SYSCFG_CM55CR_LOCKDCAIC_Msk         (0x1UL << SYSCFG_CM55CR_LOCKDCAIC_Pos)  /*!< 0x00200000 */
+#define SYSCFG_CM55CR_LOCKDCAIC             SYSCFG_CM55CR_LOCKDCAIC_Msk
+
+/******************  Bit definition for SYSCFG_CM55TCMCR register  ***************/
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Pos      (0U)
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x0000000F */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ          SYSCFG_CM55TCMCR_CFGITCMSZ_Msk               /*!< Select ITCM memory size */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000001 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000002 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000004 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000008 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos      (4U)
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ          SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk               /*!< Select DTCM memory size */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000010 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000020 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000040 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000080 */
+#define SYSCFG_CM55TCMCR_LOCKTCM_Pos        (16U)
+#define SYSCFG_CM55TCMCR_LOCKTCM_Msk        (0x1UL << SYSCFG_CM55TCMCR_LOCKTCM_Pos)      /*!< 0x00010000 */
+#define SYSCFG_CM55TCMCR_LOCKTCM            SYSCFG_CM55TCMCR_LOCKTCM_Msk                 /*!< Disable writes to registers associated with the TCM region */
+#define SYSCFG_CM55TCMCR_LOCKITGU_Pos       (17U)
+#define SYSCFG_CM55TCMCR_LOCKITGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKITGU_Pos)     /*!< 0x00020000 */
+#define SYSCFG_CM55TCMCR_LOCKITGU           SYSCFG_CM55TCMCR_LOCKITGU_Msk                /*!< Disable writes to registers associated with the ITCM interface security/gating */
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Pos       (18U)
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKDTGU_Pos)     /*!< 0x00040000 */
+#define SYSCFG_CM55TCMCR_LOCKDTGU           SYSCFG_CM55TCMCR_LOCKDTGU_Msk                /*!< Disable writes to registers associated with the DTCM interface security/gating. */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos  (23U)
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos) /*!< 0x00800000 */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE      SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended ITCM memory */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos  (24U)
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos) /*!< 0x01000000 */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE      SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended DTCM memory */
+
+
+/******************  Bit definition for SYSCFG_CM55RWMCR register  **************/
+#define SYSCFG_CM55RWMCR_RME_TCM_Pos        (0U)
+#define SYSCFG_CM55RWMCR_RME_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_RME_TCM_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55RWMCR_RME_TCM            SYSCFG_CM55RWMCR_RME_TCM_Msk              /*!< RW margin enable input for TCM memories */
+#define SYSCFG_CM55RWMCR_RM_TCM_Pos         (1U)
+#define SYSCFG_CM55RWMCR_RM_TCM_Msk         (0xFUL << SYSCFG_CM55RWMCR_RM_TCM_Pos)    /*!< 0x0000001E */
+#define SYSCFG_CM55RWMCR_RM_TCM             SYSCFG_CM55RWMCR_RM_TCM_Msk               /*!< External RW margin inputs for TCM memories */
+#define SYSCFG_CM55RWMCR_BC1_TCM_Pos        (5U)
+#define SYSCFG_CM55RWMCR_BC1_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC1_TCM_Pos)   /*!< 0x00000020 */
+#define SYSCFG_CM55RWMCR_BC1_TCM            SYSCFG_CM55RWMCR_BC1_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_TCM_Pos        (6U)
+#define SYSCFG_CM55RWMCR_BC2_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC2_TCM_Pos)   /*!< 0x00000040 */
+#define SYSCFG_CM55RWMCR_BC2_TCM            SYSCFG_CM55RWMCR_BC2_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom + 10% */
+#define SYSCFG_CM55RWMCR_RME_CACHE_Pos      (7U)
+#define SYSCFG_CM55RWMCR_RME_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_RME_CACHE_Pos) /*!< 0x00000080 */
+#define SYSCFG_CM55RWMCR_RME_CACHE          SYSCFG_CM55RWMCR_RME_CACHE_Msk            /*!< RW margin enable input for caches memories */
+#define SYSCFG_CM55RWMCR_RM_CACHE_Pos       (8U)
+#define SYSCFG_CM55RWMCR_RM_CACHE_Msk       (0xFUL << SYSCFG_CM55RWMCR_RM_CACHE_Pos)  /*!< 0x00000F00 */
+#define SYSCFG_CM55RWMCR_RM_CACHE           SYSCFG_CM55RWMCR_RM_CACHE_Msk             /*!< External read/write (RW) margin inputs for caches memories */
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Pos      (12U)
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC1_CACHE_Pos) /*!< 0x0001000 */
+#define SYSCFG_CM55RWMCR_BC1_CACHE          SYSCFG_CM55RWMCR_BC1_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Pos      (13U)
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC2_CACHE_Pos) /*!< 0x00002000 */
+#define SYSCFG_CM55RWMCR_BC2_CACHE          SYSCFG_CM55RWMCR_BC2_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom + 10% */
+
+/******************  Bit definition for SYSCFG_INITSVTORCR register  **************/
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos   (7U)
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk   (0x1FFFFFFUL << SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos)   /*!< 0xFFFFFF80 */
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR       SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk                    /*!< Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_INITNSVTORCR register  **************/
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos  (7U)
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk  (0x1FFFFFFUL << SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos)  /*!< 0xFFFFFF80 */
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR      SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk                   /*!< Non-Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_CM55RSTCR register  **************/
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos     (0U)
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk     (0x1UL << SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE         SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk            /*!< Select reset to apply on core upon SYSRESETREQ */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos       (1U)
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN           SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos       (2U)
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN           SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+
+/******************  Bit definition for SYSCFG_CM55PAHBWPR register  **************/
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos       (0U)
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk       (0x1UL << SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK           SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk            /*!< Error capture in write posting buffer */
+
+/******************  Bit definition for SYSCFG_VENCRAMCR register  **************/
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Pos     (0U)
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Msk     (0x1UL << SYSCFG_VENCRAMCR_VENCRAM_EN_Pos)               /*!< 0x00000001 */
+#define SYSCFG_VENCRAMCR_VENCRAM_EN         SYSCFG_VENCRAMCR_VENCRAM_EN_Msk                          /*!< VENCRAM allocation VENC if active, or to system (if VENC inactive) */
+
+/******************  Bit definition for SYSCFG_POTTAMPRSTCR register  **************/
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos       (0U)
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk       (0x1UL << SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos) /*!< 0x00000001 */
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK           SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk            /*!< mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper */
+
+/******************  Bit definition for SYSCFG_NPUNICQOSCR register  **************/
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos    (0U)
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR         SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk           /*!< NPUNIC read QoS information for NPU1 master port */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos    (4U)
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW         SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk           /*!< NPUNIC write QoS information for NPU1 master port */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos    (8U)
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR         SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk           /*!< NPUNIC read QoS information for NPU2 master port */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos    (12U)
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW         SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk           /*!< NPUNIC write QoS information for NPU2 master port */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos   (16U)
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk   (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR        SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk           /*!< NPUNIC read QoS information for master port from CPUSS */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_0     (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_1     (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_2     (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_3     (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos   (20U)
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk   (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW        SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk           /*!< NPUNIC write QoS information for master port from CPUSS */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_0     (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_1     (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_2     (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_3     (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000008 */
+
+/******************  Bit definition for SYSCFG_ICNEWRCR register  **************/
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos     (0U)
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000001 */
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC1 early-write response */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos     (1U)
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC2 early-write response */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos       (2U)
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000004 */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk              /*!< USB1 early-write response */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos       (3U)
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000008 */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk              /*!< USB2 early-write response */
+
+/******************  Bit definition for SYSCFG_ICNCGCR register  **************/
+#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos              (0U)
+#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos) /*!< 0x00000001 */
+#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk            /*!< NPU_NIC clock gating disable */
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos              (1U)
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk            /*!< CPU_NIC clock gating disable */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos              (2U)
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos) /*!< 0x00000004 */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk            /*!< CPU_NOC clock gating disable */
+
+/******************  Bit definition for SYSCFG_IOCR register  **************/
+#define SYSCFG_IOCR_IOCR_Pos                (0U)
+#define SYSCFG_IOCR_IOCR_Msk                (0xFFFFFFFFUL << SYSCFG_IOCR_IOCR_Pos)         /*!< 0xFFFFFFFF */
+#define SYSCFG_IOCR_IOCR                    SYSCFG_IOCR_IOCR_Msk                           /*!< Digital or analog pins */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCCR register  **************/
+#define SYSCFG_VDDIO2CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO2CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCCR_RANSRC            SYSCFG_VDDIO2CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC            SYSCFG_VDDIO2CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO2CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCCR_EN                SYSCFG_VDDIO2CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO2 */
+#define SYSCFG_VDDIO2CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO2CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO2CCCR_CS                SYSCFG_VDDIO2CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCSR register  **************/
+#define SYSCFG_VDDIO2CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO2CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCSR_ANSRC             SYSCFG_VDDIO2CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO2CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO2CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCSR_APSRC             SYSCFG_VDDIO2CCSR_APSRC_Msk
+#define SYSCFG_VDDIO2CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO2CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO2CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCSR_READY             SYSCFG_VDDIO2CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCCR register  **************/
+#define SYSCFG_VDDIO3CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO3CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCCR_RANSRC            SYSCFG_VDDIO3CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC            SYSCFG_VDDIO3CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO3CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCCR_EN                SYSCFG_VDDIO3CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO3 */
+#define SYSCFG_VDDIO3CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO3CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO3CCCR_CS                SYSCFG_VDDIO3CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCSR register  **************/
+#define SYSCFG_VDDIO3CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO3CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCSR_ANSRC             SYSCFG_VDDIO3CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO3CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO3CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCSR_APSRC             SYSCFG_VDDIO3CCSR_APSRC_Msk
+#define SYSCFG_VDDIO3CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO3CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO3CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCSR_READY             SYSCFG_VDDIO3CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCCR register  **************/
+#define SYSCFG_VDDIO4CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO4CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCCR_RANSRC            SYSCFG_VDDIO4CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC            SYSCFG_VDDIO4CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO4CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCCR_EN                SYSCFG_VDDIO4CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO4 */
+#define SYSCFG_VDDIO4CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO4CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO4CCCR_CS                SYSCFG_VDDIO4CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCSR register  **************/
+#define SYSCFG_VDDIO4CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO4CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCSR_ANSRC             SYSCFG_VDDIO4CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO4CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO4CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCSR_APSRC             SYSCFG_VDDIO4CCSR_APSRC_Msk
+#define SYSCFG_VDDIO4CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO4CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO4CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCSR_READY             SYSCFG_VDDIO4CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCCR register  **************/
+#define SYSCFG_VDDIO5CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO5CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCCR_RANSRC            SYSCFG_VDDIO5CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC            SYSCFG_VDDIO5CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO5CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCCR_EN                SYSCFG_VDDIO5CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO5 */
+#define SYSCFG_VDDIO5CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO5CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO5CCCR_CS                SYSCFG_VDDIO5CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCSR register  **************/
+#define SYSCFG_VDDIO5CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO5CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCSR_ANSRC             SYSCFG_VDDIO5CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO5CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO5CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCSR_APSRC             SYSCFG_VDDIO5CCSR_APSRC_Msk
+#define SYSCFG_VDDIO5CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO5CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO5CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCSR_READY             SYSCFG_VDDIO5CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDCCCR register  **************/
+#define SYSCFG_VDDCCCR_RANSRC_Pos           (0U)
+#define SYSCFG_VDDCCCR_RANSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x0000000F */
+#define SYSCFG_VDDCCCR_RANSRC               SYSCFG_VDDCCCR_RANSRC_Msk                      /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDCCCR_RANSRC_0             (0x1UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000001 */
+#define SYSCFG_VDDCCCR_RANSRC_1             (0x2UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000002 */
+#define SYSCFG_VDDCCCR_RANSRC_2             (0x4UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000004 */
+#define SYSCFG_VDDCCCR_RANSRC_3             (0x8UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000008 */
+#define SYSCFG_VDDCCCR_RAPSRC_Pos           (4U)
+#define SYSCFG_VDDCCCR_RAPSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x000000F0 */
+#define SYSCFG_VDDCCCR_RAPSRC               SYSCFG_VDDCCCR_RAPSRC_Msk                      /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDCCCR_RAPSRC_0             (0x1UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000010 */
+#define SYSCFG_VDDCCCR_RAPSRC_1             (0x2UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000020 */
+#define SYSCFG_VDDCCCR_RAPSRC_2             (0x4UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000040 */
+#define SYSCFG_VDDCCCR_RAPSRC_3             (0x8UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000080 */
+#define SYSCFG_VDDCCCR_EN_Pos               (8U)
+#define SYSCFG_VDDCCCR_EN_Msk               (0x1UL << SYSCFG_VDDCCCR_EN_Pos)               /*!< 0x00000100 */
+#define SYSCFG_VDDCCCR_EN                   SYSCFG_VDDCCCR_EN_Msk                          /*!< Enables the compensation cell of I/Os supplied by VDD */
+#define SYSCFG_VDDCCCR_CS_Pos               (9U)
+#define SYSCFG_VDDCCCR_CS_Msk               (0x1UL << SYSCFG_VDDCCCR_CS_Pos)               /*!< 0x00000200 */
+#define SYSCFG_VDDCCCR_CS                   SYSCFG_VDDCCCR_CS_Msk                          /*!< Code selection for the compensation cell of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_VDDCCSR register  **************/
+#define SYSCFG_VDDCCSR_ANSRC_Pos            (0U)
+#define SYSCFG_VDDCCSR_ANSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x0000000F */
+#define SYSCFG_VDDCCSR_ANSRC                SYSCFG_VDDCCSR_ANSRC_Msk
+#define SYSCFG_VDDCCSR_ANSRC_0              (0x1UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000001 */
+#define SYSCFG_VDDCCSR_ANSRC_1              (0x2UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000002 */
+#define SYSCFG_VDDCCSR_ANSRC_2              (0x4UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000004 */
+#define SYSCFG_VDDCCSR_ANSRC_3              (0x8UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000008 */
+#define SYSCFG_VDDCCSR_APSRC_Pos            (4U)
+#define SYSCFG_VDDCCSR_APSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x000000F0 */
+#define SYSCFG_VDDCCSR_APSRC                SYSCFG_VDDCCSR_APSRC_Msk
+#define SYSCFG_VDDCCSR_APSRC_0              (0x1UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000010 */
+#define SYSCFG_VDDCCSR_APSRC_1              (0x2UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000020 */
+#define SYSCFG_VDDCCSR_APSRC_2              (0x4UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000040 */
+#define SYSCFG_VDDCCSR_APSRC_3              (0x8UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000080 */
+#define SYSCFG_VDDCCSR_READY_Pos            (8U)
+#define SYSCFG_VDDCCSR_READY_Msk            (0x1UL << SYSCFG_VDDCCSR_READY_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDCCSR_READY                SYSCFG_VDDCCSR_READY_Msk                       /*!< Provides the compensation cell status of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_CBR register  **************/
+#define SYSCFG_CBR_CM55L_Pos                (0U)
+#define SYSCFG_CBR_CM55L_Msk                (0x1UL << SYSCFG_CBR_CM55L_Pos)                /*!< 0x00000001 */
+#define SYSCFG_CBR_CM55L                    SYSCFG_CBR_CM55L_Msk                           /*!< CM55 lockup lock enable */
+#define SYSCFG_CBR_PVDL_LOCK_Pos            (2U)
+#define SYSCFG_CBR_PVDL_LOCK_Msk            (0x1UL << SYSCFG_CBR_PVDL_LOCK_Pos)            /*!< 0x00000004 */
+#define SYSCFG_CBR_PVDL_LOCK                SYSCFG_CBR_PVDL_LOCK_Msk                       /*!< PVD lock enable */
+#define SYSCFG_CBR_BKPRAML_Pos              (8U)
+#define SYSCFG_CBR_BKPRAML_Msk              (0x1UL << SYSCFG_CBR_BKPRAML_Pos)              /*!< 0x00000100 */
+#define SYSCFG_CBR_BKPRAML                  SYSCFG_CBR_BKPRAML_Msk                         /*!< Backup SRAM double ECC error lock */
+#define SYSCFG_CBR_CM55CACHEL_Pos           (9U)
+#define SYSCFG_CBR_CM55CACHEL_Msk           (0x1UL << SYSCFG_CBR_CM55CACHEL_Pos)           /*!< 0x00000200 */
+#define SYSCFG_CBR_CM55CACHEL               SYSCFG_CBR_CM55CACHEL_Msk                      /*!< CM55 cache double ECC error lock */
+#define SYSCFG_CBR_CM55TCML_Pos             (10U)
+#define SYSCFG_CBR_CM55TCML_Msk             (0x1UL << SYSCFG_CBR_CM55TCML_Pos)             /*!< 0x00000400 */
+#define SYSCFG_CBR_CM55TCML                 SYSCFG_CBR_CM55TCML_Msk                        /*!< CM55 TCM double ECC error lock */
+
+/******************  Bit definition for SYSCFG_SEC_AIDCR register  **************/
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Pos     (0U)
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Msk     (0x7UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x0000000F */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC         SYSCFG_SEC_AIDCR_DMACID_SEC_Msk                /* Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_0       (0x1UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000001 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_1       (0x2UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_2       (0x4UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000004 */
+
+/******************  Bit definition for SYSCFG_FMC_RETIMECR register  **************/
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos       (0U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos) /*!< 0x00000001 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX           SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk            /*!< Retiming on Rx path */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos       (1U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos) /*!< 0x00000002 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX           SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk            /*!< Retiming on Tx path */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos         (2U)
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk         (0x1UL << SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos)   /*!< 0x00000004 */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180             SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk              /*!< Delay on feedback clock */
+
+/******************  Bit definition for SYSCFG_NPU_ICNCR register  **************/
+#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos    (0U)
+#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk    (0x1UL << SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE        SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk            /*!< Control interleaving on NPU RAMs */
+
+/******************  Bit definition for SYSCFG_BOOTSR register  **************/
+#define SYSCFG_BOOTSR_BOOT0_Pos             (0U)
+#define SYSCFG_BOOTSR_BOOT0_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT0_Pos)             /*!< 0x00000001 */
+#define SYSCFG_BOOTSR_BOOT0                 SYSCFG_BOOTSR_BOOT0_Msk                        /*!< BOOT0 pin value */
+#define SYSCFG_BOOTSR_BOOT1_Pos             (1U)
+#define SYSCFG_BOOTSR_BOOT1_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT1_Pos)             /*!< 0x00000002 */
+#define SYSCFG_BOOTSR_BOOT1                 SYSCFG_BOOTSR_BOOT1_Msk                        /*!< BOOT1 pin value */
+
+/******************  Bit definition for SYSCFG_AHBWP_ERROR_SR register  **************/
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos  (0U)
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk  (0xFFFFFFFFUL << SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR      SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk                   /*!< Reports address of the first error in P-AHB write-posting buffer */
+
+/******************  Bit definition for SYSCFG_SECPRIV_AIDCR register  **************/
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos  (0U)
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk  (0x7UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x0000000F */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC      SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk             /* Non-Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_0    (0x1UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000001 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_1    (0x2UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000002 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_2    (0x4UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000004 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Tamper and backup register (TAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for TAMP_CR1 register  *****************/
+#define TAMP_CR1_TAMP1E_Pos                 (0U)
+#define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
+#define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
+#define TAMP_CR1_TAMP2E_Pos                 (1U)
+#define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
+#define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
+#define TAMP_CR1_TAMP3E_Pos                 (2U)
+#define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
+#define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
+#define TAMP_CR1_TAMP4E_Pos                 (3U)
+#define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
+#define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
+#define TAMP_CR1_TAMP5E_Pos                 (4U)
+#define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
+#define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
+#define TAMP_CR1_TAMP6E_Pos                 (5U)
+#define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
+#define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
+#define TAMP_CR1_TAMP7E_Pos                 (6U)
+#define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
+#define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
+#define TAMP_CR1_ITAMP1E_Pos                (16U)
+#define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
+#define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
+#define TAMP_CR1_ITAMP2E_Pos                (17U)
+#define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
+#define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
+#define TAMP_CR1_ITAMP3E_Pos                (18U)
+#define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
+#define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
+#define TAMP_CR1_ITAMP4E_Pos                (19U)
+#define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
+#define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
+#define TAMP_CR1_ITAMP5E_Pos                (20U)
+#define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
+#define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
+#define TAMP_CR1_ITAMP6E_Pos                (21U)
+#define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
+#define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
+#define TAMP_CR1_ITAMP7E_Pos                (22U)
+#define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
+#define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
+#define TAMP_CR1_ITAMP8E_Pos                (23U)
+#define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
+#define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
+#define TAMP_CR1_ITAMP9E_Pos                (24U)
+#define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
+#define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
+#define TAMP_CR1_ITAMP11E_Pos               (26U)
+#define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
+#define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
+
+/********************  Bits definition for TAMP_CR2 register  *****************/
+#define TAMP_CR2_TAMP1POM_Pos               (0U)
+#define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk
+#define TAMP_CR2_TAMP2POM_Pos               (1U)
+#define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk
+#define TAMP_CR2_TAMP3POM_Pos               (2U)
+#define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
+#define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk
+#define TAMP_CR2_TAMP4POM_Pos               (3U)
+#define TAMP_CR2_TAMP4POM_Msk               (0x1UL << TAMP_CR2_TAMP4POM_Pos)        /*!< 0x00000008 */
+#define TAMP_CR2_TAMP4POM                   TAMP_CR2_TAMP4POM_Msk
+#define TAMP_CR2_TAMP5POM_Pos               (4U)
+#define TAMP_CR2_TAMP5POM_Msk               (0x1UL << TAMP_CR2_TAMP5POM_Pos)        /*!< 0x00000010 */
+#define TAMP_CR2_TAMP5POM                   TAMP_CR2_TAMP5POM_Msk
+#define TAMP_CR2_TAMP6POM_Pos               (5U)
+#define TAMP_CR2_TAMP6POM_Msk               (0x1UL << TAMP_CR2_TAMP6POM_Pos)        /*!< 0x00000020 */
+#define TAMP_CR2_TAMP6POM                   TAMP_CR2_TAMP6POM_Msk
+#define TAMP_CR2_TAMP7POM_Pos               (6U)
+#define TAMP_CR2_TAMP7POM_Msk               (0x1UL << TAMP_CR2_TAMP7POM_Pos)        /*!< 0x00000040 */
+#define TAMP_CR2_TAMP7POM                   TAMP_CR2_TAMP7POM_Msk
+#define TAMP_CR2_TAMP1MSK_Pos               (16U)
+#define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos               (17U)
+#define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP3MSK_Pos               (18U)
+#define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
+#define TAMP_CR2_BKBLOCK_Pos                (22U)
+#define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
+#define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
+#define TAMP_CR2_BKERASE_Pos                (23U)
+#define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
+#define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
+#define TAMP_CR2_TAMP1TRG_Pos               (24U)
+#define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos               (25U)
+#define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
+#define TAMP_CR2_TAMP3TRG_Pos               (26U)
+#define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
+#define TAMP_CR2_TAMP4TRG_Pos               (27U)
+#define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
+#define TAMP_CR2_TAMP5TRG_Pos               (28U)
+#define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
+#define TAMP_CR2_TAMP6TRG_Pos               (29U)
+#define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
+#define TAMP_CR2_TAMP7TRG_Pos               (30U)
+#define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
+
+/********************  Bits definition for TAMP_CR3 register  *****************/
+#define TAMP_CR3_ITAMP1POM_Pos              (0U)
+#define TAMP_CR3_ITAMP1POM_Msk              (0x1UL << TAMP_CR3_ITAMP1POM_Pos)       /*!< 0x00000001 */
+#define TAMP_CR3_ITAMP1POM                  TAMP_CR3_ITAMP1POM_Msk
+#define TAMP_CR3_ITAMP2POM_Pos              (1U)
+#define TAMP_CR3_ITAMP2POM_Msk              (0x1UL << TAMP_CR3_ITAMP2POM_Pos)       /*!< 0x00000002 */
+#define TAMP_CR3_ITAMP2POM                  TAMP_CR3_ITAMP2POM_Msk
+#define TAMP_CR3_ITAMP3POM_Pos              (2U)
+#define TAMP_CR3_ITAMP3POM_Msk              (0x1UL << TAMP_CR3_ITAMP3POM_Pos)       /*!< 0x00000004 */
+#define TAMP_CR3_ITAMP3POM                  TAMP_CR3_ITAMP3POM_Msk
+#define TAMP_CR3_ITAMP4POM_Pos              (3U)
+#define TAMP_CR3_ITAMP4POM_Msk              (0x1UL << TAMP_CR3_ITAMP4POM_Pos)       /*!< 0x00000008 */
+#define TAMP_CR3_ITAMP4POM                  TAMP_CR3_ITAMP4POM_Msk
+#define TAMP_CR3_ITAMP5POM_Pos              (4U)
+#define TAMP_CR3_ITAMP5POM_Msk              (0x1UL << TAMP_CR3_ITAMP5POM_Pos)       /*!< 0x00000010 */
+#define TAMP_CR3_ITAMP5POM                  TAMP_CR3_ITAMP5POM_Msk
+#define TAMP_CR3_ITAMP6POM_Pos              (5U)
+#define TAMP_CR3_ITAMP6POM_Msk              (0x1UL << TAMP_CR3_ITAMP6POM_Pos)       /*!< 0x00000020 */
+#define TAMP_CR3_ITAMP6POM                  TAMP_CR3_ITAMP6POM_Msk
+#define TAMP_CR3_ITAMP7POM_Pos              (6U)
+#define TAMP_CR3_ITAMP7POM_Msk              (0x1UL << TAMP_CR3_ITAMP7POM_Pos)       /*!< 0x00000040 */
+#define TAMP_CR3_ITAMP7POM                  TAMP_CR3_ITAMP7POM_Msk
+#define TAMP_CR3_ITAMP8POM_Pos              (7U)
+#define TAMP_CR3_ITAMP8POM_Msk              (0x1UL << TAMP_CR3_ITAMP8POM_Pos)       /*!< 0x00000080 */
+#define TAMP_CR3_ITAMP8POM                  TAMP_CR3_ITAMP8POM_Msk
+#define TAMP_CR3_ITAMP9POM_Pos              (8U)
+#define TAMP_CR3_ITAMP9POM_Msk              (0x1UL << TAMP_CR3_ITAMP9POM_Pos)       /*!< 0x00000100 */
+#define TAMP_CR3_ITAMP9POM                  TAMP_CR3_ITAMP9POM_Msk
+#define TAMP_CR3_ITAMP11POM_Pos             (10U)
+#define TAMP_CR3_ITAMP11POM_Msk             (0x1UL << TAMP_CR3_ITAMP11POM_Pos)      /*!< 0x00000400 */
+#define TAMP_CR3_ITAMP11POM                 TAMP_CR3_ITAMP11POM_Msk
+
+/********************  Bits definition for TAMP_FLTCR register  ***************/
+#define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
+#define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
+#define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
+#define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
+#define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
+#define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
+#define TAMP_FLTCR_TAMPFLT_Pos              (3U)
+#define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
+#define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
+#define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
+#define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
+#define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
+#define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
+#define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
+#define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
+#define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
+#define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
+#define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
+#define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
+
+/********************  Bits definition for TAMP_ATCR1 register  ***************/
+#define TAMP_ATCR1_TAMP1AM_Pos              (0U)
+#define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
+#define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
+#define TAMP_ATCR1_TAMP2AM_Pos              (1U)
+#define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
+#define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
+#define TAMP_ATCR1_TAMP3AM_Pos              (2U)
+#define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
+#define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
+#define TAMP_ATCR1_TAMP4AM_Pos              (3U)
+#define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
+#define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
+#define TAMP_ATCR1_TAMP5AM_Pos              (4U)
+#define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
+#define TAMP_ATCR1_TAMP6AM_Pos              (5U)
+#define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
+#define TAMP_ATCR1_TAMP7AM_Pos              (6U)
+#define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
+#define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
+#define TAMP_ATCR1_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
+#define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
+#define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR1_ATOSEL2_Pos              (10U)
+#define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
+#define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
+#define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR1_ATOSEL3_Pos              (12U)
+#define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
+#define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
+#define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR1_ATOSEL4_Pos              (14U)
+#define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
+#define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
+#define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR1_ATCKSEL_Pos              (16U)
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
+#define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
+#define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR1_ATPER_Pos                (24U)
+#define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
+#define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
+#define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
+#define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
+#define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
+#define TAMP_ATCR1_ATOSHARE_Pos             (30U)
+#define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
+#define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
+#define TAMP_ATCR1_FLTEN_Pos                (31U)
+#define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
+#define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
+
+/********************  Bits definition for TAMP_ATSEEDR register  ******************/
+#define TAMP_ATSEEDR_SEED_Pos               (0U)
+#define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
+
+/********************  Bits definition for TAMP_ATOR register  ******************/
+#define TAMP_ATOR_PRNG_Pos                  (0U)
+#define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)          /*!< 0x000000FF */
+#define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
+#define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
+#define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
+#define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
+#define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
+#define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
+#define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
+#define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
+#define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
+#define TAMP_ATOR_SEEDF_Pos                 (14U)
+#define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
+#define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
+#define TAMP_ATOR_INITS_Pos                 (15U)
+#define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
+#define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
+
+/********************  Bits definition for TAMP_ATCR2 register  ***************/
+#define TAMP_ATCR2_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
+#define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
+#define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR2_ATOSEL2_Pos              (11U)
+#define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
+#define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
+#define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR2_ATOSEL3_Pos              (14U)
+#define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
+#define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
+#define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR2_ATOSEL4_Pos              (17U)
+#define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
+#define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
+#define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR2_ATOSEL5_Pos              (20U)
+#define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
+#define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
+#define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
+#define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
+#define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
+#define TAMP_ATCR2_ATOSEL6_Pos              (23U)
+#define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
+#define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
+#define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
+#define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
+#define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
+#define TAMP_ATCR2_ATOSEL7_Pos              (26U)
+#define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
+#define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
+#define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
+#define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
+#define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
+
+/********************  Bits definition for TAMP_SECCFGR register  *************/
+#define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
+#define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
+#define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
+#define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
+#define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
+#define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
+#define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
+#define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
+#define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
+#define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
+#define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
+#define TAMP_SECCFGR_CNT1SEC_Pos            (15U)
+#define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)     /*!< 0x00008000 */
+#define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
+#define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
+#define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
+#define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
+#define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
+#define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
+#define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
+#define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
+#define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
+#define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
+#define TAMP_SECCFGR_BHKLOCK_Pos            (30U)
+#define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
+#define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
+#define TAMP_SECCFGR_TAMPSEC_Pos            (31U)
+#define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
+#define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk
+
+/********************  Bits definition for TAMP_PRIVCFGR register  ************/
+#define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
+#define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
+#define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
+#define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
+#define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
+#define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
+#define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
+#define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
+#define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
+#define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
+
+/********************  Bits definition for TAMP_IER register  *****************/
+#define TAMP_IER_TAMP1IE_Pos                (0U)
+#define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
+#define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
+#define TAMP_IER_TAMP2IE_Pos                (1U)
+#define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
+#define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
+#define TAMP_IER_TAMP3IE_Pos                (2U)
+#define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
+#define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
+#define TAMP_IER_TAMP4IE_Pos                (3U)
+#define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
+#define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
+#define TAMP_IER_TAMP5IE_Pos                (4U)
+#define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
+#define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
+#define TAMP_IER_TAMP6IE_Pos                (5U)
+#define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
+#define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
+#define TAMP_IER_TAMP7IE_Pos                (6U)
+#define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
+#define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
+#define TAMP_IER_ITAMP1IE_Pos               (16U)
+#define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
+#define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
+#define TAMP_IER_ITAMP2IE_Pos               (17U)
+#define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
+#define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
+#define TAMP_IER_ITAMP3IE_Pos               (18U)
+#define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
+#define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
+#define TAMP_IER_ITAMP4IE_Pos               (19U)
+#define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
+#define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
+#define TAMP_IER_ITAMP5IE_Pos               (20U)
+#define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
+#define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
+#define TAMP_IER_ITAMP6IE_Pos               (21U)
+#define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
+#define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
+#define TAMP_IER_ITAMP7IE_Pos               (22U)
+#define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
+#define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
+#define TAMP_IER_ITAMP8IE_Pos               (23U)
+#define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
+#define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
+#define TAMP_IER_ITAMP9IE_Pos               (24U)
+#define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
+#define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
+#define TAMP_IER_ITAMP11IE_Pos              (26U)
+#define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
+#define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
+
+/********************  Bits definition for TAMP_SR register  *****************/
+#define TAMP_SR_TAMP1F_Pos                  (0U)
+#define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
+#define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
+#define TAMP_SR_TAMP2F_Pos                  (1U)
+#define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
+#define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
+#define TAMP_SR_TAMP3F_Pos                  (2U)
+#define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
+#define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
+#define TAMP_SR_TAMP4F_Pos                  (3U)
+#define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
+#define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
+#define TAMP_SR_TAMP5F_Pos                  (4U)
+#define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
+#define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
+#define TAMP_SR_TAMP6F_Pos                  (5U)
+#define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
+#define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
+#define TAMP_SR_TAMP7F_Pos                  (6U)
+#define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
+#define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
+#define TAMP_SR_ITAMP1F_Pos                 (16U)
+#define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
+#define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
+#define TAMP_SR_ITAMP2F_Pos                 (17U)
+#define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
+#define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
+#define TAMP_SR_ITAMP3F_Pos                 (18U)
+#define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
+#define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
+#define TAMP_SR_ITAMP4F_Pos                 (19U)
+#define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
+#define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
+#define TAMP_SR_ITAMP5F_Pos                 (20U)
+#define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
+#define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
+#define TAMP_SR_ITAMP6F_Pos                 (21U)
+#define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
+#define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
+#define TAMP_SR_ITAMP7F_Pos                 (22U)
+#define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
+#define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
+#define TAMP_SR_ITAMP8F_Pos                 (23U)
+#define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
+#define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
+#define TAMP_SR_ITAMP9F_Pos                 (24U)
+#define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
+#define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
+#define TAMP_SR_ITAMP11F_Pos                (26U)
+#define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
+#define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
+
+/********************  Bits definition for TAMP_MISR register  ****************/
+#define TAMP_MISR_TAMP1MF_Pos               (0U)
+#define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
+#define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
+#define TAMP_MISR_TAMP2MF_Pos               (1U)
+#define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
+#define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
+#define TAMP_MISR_TAMP3MF_Pos               (2U)
+#define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
+#define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
+#define TAMP_MISR_TAMP4MF_Pos               (3U)
+#define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
+#define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
+#define TAMP_MISR_TAMP5MF_Pos               (4U)
+#define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
+#define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
+#define TAMP_MISR_TAMP6MF_Pos               (5U)
+#define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
+#define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
+#define TAMP_MISR_TAMP7MF_Pos               (6U)
+#define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
+#define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
+#define TAMP_MISR_ITAMP1MF_Pos              (16U)
+#define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
+#define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
+#define TAMP_MISR_ITAMP2MF_Pos              (17U)
+#define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
+#define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
+#define TAMP_MISR_ITAMP3MF_Pos              (18U)
+#define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
+#define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
+#define TAMP_MISR_ITAMP4MF_Pos              (19U)
+#define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
+#define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
+#define TAMP_MISR_ITAMP5MF_Pos              (20U)
+#define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
+#define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
+#define TAMP_MISR_ITAMP6MF_Pos              (21U)
+#define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
+#define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
+#define TAMP_MISR_ITAMP7MF_Pos              (22U)
+#define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
+#define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
+#define TAMP_MISR_ITAMP8MF_Pos              (23U)
+#define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
+#define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
+#define TAMP_MISR_ITAMP9MF_Pos              (24U)
+#define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
+#define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
+#define TAMP_MISR_ITAMP11MF_Pos             (26U)
+#define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
+#define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SMISR register  ************ *****/
+#define TAMP_SMISR_TAMP1MF_Pos              (0U)
+#define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
+#define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
+#define TAMP_SMISR_TAMP2MF_Pos              (1U)
+#define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
+#define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
+#define TAMP_SMISR_TAMP3MF_Pos              (2U)
+#define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
+#define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
+#define TAMP_SMISR_TAMP4MF_Pos              (3U)
+#define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
+#define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
+#define TAMP_SMISR_TAMP5MF_Pos              (4U)
+#define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
+#define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
+#define TAMP_SMISR_TAMP6MF_Pos              (5U)
+#define TAMP_SMISR_TAMP6MF_Msk              (0x1UL << TAMP_SMISR_TAMP6MF_Pos)       /*!< 0x00000020 */
+#define TAMP_SMISR_TAMP6MF                  TAMP_SMISR_TAMP6MF_Msk
+#define TAMP_SMISR_TAMP7MF_Pos              (6U)
+#define TAMP_SMISR_TAMP7MF_Msk              (0x1UL << TAMP_SMISR_TAMP7MF_Pos)       /*!< 0x00000040 */
+#define TAMP_SMISR_TAMP7MF                  TAMP_SMISR_TAMP7MF_Msk
+#define TAMP_SMISR_ITAMP1MF_Pos             (16U)
+#define TAMP_SMISR_ITAMP1MF_Msk             (0x1UL << TAMP_SMISR_ITAMP1MF_Pos)      /*!< 0x00010000 */
+#define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
+#define TAMP_SMISR_ITAMP2MF_Pos             (17U)
+#define TAMP_SMISR_ITAMP2MF_Msk             (0x1UL << TAMP_SMISR_ITAMP2MF_Pos)      /*!< 0x00020000 */
+#define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
+#define TAMP_SMISR_ITAMP3MF_Pos             (18U)
+#define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
+#define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
+#define TAMP_SMISR_ITAMP4MF_Pos             (19U)
+#define TAMP_SMISR_ITAMP4MF_Msk             (0x1UL << TAMP_SMISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
+#define TAMP_SMISR_ITAMP4MF                 TAMP_SMISR_ITAMP4MF_Msk
+#define TAMP_SMISR_ITAMP5MF_Pos             (20U)
+#define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
+#define TAMP_SMISR_ITAMP6MF_Pos             (21U)
+#define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
+#define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
+#define TAMP_SMISR_ITAMP7MF_Pos             (22U)
+#define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
+#define TAMP_SMISR_ITAMP8MF_Pos             (23U)
+#define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
+#define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
+#define TAMP_SMISR_ITAMP9MF_Pos             (24U)
+#define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
+#define TAMP_SMISR_ITAMP11MF_Pos            (26U)
+#define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SCR register  *****************/
+#define TAMP_SCR_CTAMP1F_Pos                (0U)
+#define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
+#define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
+#define TAMP_SCR_CTAMP2F_Pos                (1U)
+#define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
+#define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
+#define TAMP_SCR_CTAMP3F_Pos                (2U)
+#define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
+#define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
+#define TAMP_SCR_CTAMP4F_Pos                (3U)
+#define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
+#define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
+#define TAMP_SCR_CTAMP5F_Pos                (4U)
+#define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
+#define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
+#define TAMP_SCR_CTAMP6F_Pos                (5U)
+#define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
+#define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
+#define TAMP_SCR_CTAMP7F_Pos                (6U)
+#define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
+#define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
+#define TAMP_SCR_CTAMP8F_Pos                (7U)
+#define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
+#define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
+#define TAMP_SCR_CITAMP1F_Pos               (16U)
+#define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
+#define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
+#define TAMP_SCR_CITAMP2F_Pos               (17U)
+#define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
+#define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
+#define TAMP_SCR_CITAMP3F_Pos               (18U)
+#define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
+#define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
+#define TAMP_SCR_CITAMP4F_Pos               (19U)
+#define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
+#define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
+#define TAMP_SCR_CITAMP5F_Pos               (20U)
+#define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
+#define TAMP_SCR_CITAMP6F_Pos               (21U)
+#define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
+#define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
+#define TAMP_SCR_CITAMP7F_Pos               (22U)
+#define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
+#define TAMP_SCR_CITAMP8F_Pos               (23U)
+#define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
+#define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
+#define TAMP_SCR_CITAMP9F_Pos               (24U)
+#define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
+#define TAMP_SCR_CITAMP11F_Pos              (26U)
+#define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
+
+/********************  Bits definition for TAMP_COUNT1R register  ***************/
+#define TAMP_COUNT1R_COUNT_Pos              (0U)
+#define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
+#define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
+
+/********************  Bits definition for TAMP_OR register  ***************/
+#define TAMP_OR_VCOREMEN_Pos                (0U)
+#define TAMP_OR_VCOREMEN_Msk                (0x1UL << TAMP_OR_VCOREMEN_Pos)         /*!< 0x00000001 */
+#define TAMP_OR_VCOREMEN                    TAMP_OR_VCOREMEN_Msk
+
+/********************  Bits definition for TAMP_RPCFGR register  ***************/
+#define TAMP_RPCFGR_RPCFG0_Pos              (0U)
+#define TAMP_RPCFGR_RPCFG0_Msk              (0x1UL << TAMP_RPCFGR_RPCFG0_Pos)       /*!< 0x00000001 */
+#define TAMP_RPCFGR_RPCFG0                  TAMP_RPCFGR_RPCFG0_Msk
+
+/********************  Bits definition for TAMP_BKP0R register  ***************/
+#define TAMP_BKP0R_Pos                      (0U)
+#define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP0R                          TAMP_BKP0R_Msk
+
+/********************  Bits definition for TAMP_BKP1R register  ****************/
+#define TAMP_BKP1R_Pos                      (0U)
+#define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP1R                          TAMP_BKP1R_Msk
+
+/********************  Bits definition for TAMP_BKP2R register  ****************/
+#define TAMP_BKP2R_Pos                      (0U)
+#define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP2R                          TAMP_BKP2R_Msk
+
+/********************  Bits definition for TAMP_BKP3R register  ****************/
+#define TAMP_BKP3R_Pos                      (0U)
+#define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP3R                          TAMP_BKP3R_Msk
+
+/********************  Bits definition for TAMP_BKP4R register  ****************/
+#define TAMP_BKP4R_Pos                      (0U)
+#define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP4R                          TAMP_BKP4R_Msk
+
+/********************  Bits definition for TAMP_BKP5R register  ****************/
+#define TAMP_BKP5R_Pos                      (0U)
+#define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP5R                          TAMP_BKP5R_Msk
+
+/********************  Bits definition for TAMP_BKP6R register  ****************/
+#define TAMP_BKP6R_Pos                      (0U)
+#define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP6R                          TAMP_BKP6R_Msk
+
+/********************  Bits definition for TAMP_BKP7R register  ****************/
+#define TAMP_BKP7R_Pos                      (0U)
+#define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP7R                          TAMP_BKP7R_Msk
+
+/********************  Bits definition for TAMP_BKP8R register  ****************/
+#define TAMP_BKP8R_Pos                      (0U)
+#define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP8R                          TAMP_BKP8R_Msk
+
+/********************  Bits definition for TAMP_BKP9R register  ****************/
+#define TAMP_BKP9R_Pos                      (0U)
+#define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP9R                          TAMP_BKP9R_Msk
+
+/********************  Bits definition for TAMP_BKP10R register  ***************/
+#define TAMP_BKP10R_Pos                     (0U)
+#define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP10R                         TAMP_BKP10R_Msk
+
+/********************  Bits definition for TAMP_BKP11R register  ***************/
+#define TAMP_BKP11R_Pos                     (0U)
+#define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP11R                         TAMP_BKP11R_Msk
+
+/********************  Bits definition for TAMP_BKP12R register  ***************/
+#define TAMP_BKP12R_Pos                     (0U)
+#define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP12R                         TAMP_BKP12R_Msk
+
+/********************  Bits definition for TAMP_BKP13R register  ***************/
+#define TAMP_BKP13R_Pos                     (0U)
+#define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP13R                         TAMP_BKP13R_Msk
+
+/********************  Bits definition for TAMP_BKP14R register  ***************/
+#define TAMP_BKP14R_Pos                     (0U)
+#define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP14R                         TAMP_BKP14R_Msk
+
+/********************  Bits definition for TAMP_BKP15R register  ***************/
+#define TAMP_BKP15R_Pos                     (0U)
+#define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP15R                         TAMP_BKP15R_Msk
+
+/********************  Bits definition for TAMP_BKP16R register  ***************/
+#define TAMP_BKP16R_Pos                     (0U)
+#define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP16R                         TAMP_BKP16R_Msk
+
+/********************  Bits definition for TAMP_BKP17R register  ***************/
+#define TAMP_BKP17R_Pos                     (0U)
+#define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP17R                         TAMP_BKP17R_Msk
+
+/********************  Bits definition for TAMP_BKP18R register  ***************/
+#define TAMP_BKP18R_Pos                     (0U)
+#define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP18R                         TAMP_BKP18R_Msk
+
+/********************  Bits definition for TAMP_BKP19R register  ***************/
+#define TAMP_BKP19R_Pos                     (0U)
+#define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP19R                         TAMP_BKP19R_Msk
+
+/********************  Bits definition for TAMP_BKP20R register  ***************/
+#define TAMP_BKP20R_Pos                     (0U)
+#define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP20R                         TAMP_BKP20R_Msk
+
+/********************  Bits definition for TAMP_BKP21R register  ***************/
+#define TAMP_BKP21R_Pos                     (0U)
+#define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP21R                         TAMP_BKP21R_Msk
+
+/********************  Bits definition for TAMP_BKP22R register  ***************/
+#define TAMP_BKP22R_Pos                     (0U)
+#define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP22R                         TAMP_BKP22R_Msk
+
+/********************  Bits definition for TAMP_BKP23R register  ***************/
+#define TAMP_BKP23R_Pos                     (0U)
+#define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP23R                         TAMP_BKP23R_Msk
+
+/********************  Bits definition for TAMP_BKP24R register  ***************/
+#define TAMP_BKP24R_Pos                     (0U)
+#define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP24R                         TAMP_BKP24R_Msk
+
+/********************  Bits definition for TAMP_BKP25R register  ***************/
+#define TAMP_BKP25R_Pos                     (0U)
+#define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP25R                         TAMP_BKP25R_Msk
+
+/********************  Bits definition for TAMP_BKP26R register  ***************/
+#define TAMP_BKP26R_Pos                     (0U)
+#define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP26R                         TAMP_BKP26R_Msk
+
+/********************  Bits definition for TAMP_BKP27R register  ***************/
+#define TAMP_BKP27R_Pos                     (0U)
+#define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP27R                         TAMP_BKP27R_Msk
+
+/********************  Bits definition for TAMP_BKP28R register  ***************/
+#define TAMP_BKP28R_Pos                     (0U)
+#define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP28R                         TAMP_BKP28R_Msk
+
+/********************  Bits definition for TAMP_BKP29R register  ***************/
+#define TAMP_BKP29R_Pos                     (0U)
+#define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP29R                         TAMP_BKP29R_Msk
+
+/********************  Bits definition for TAMP_BKP30R register  ***************/
+#define TAMP_BKP30R_Pos                     (0U)
+#define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP30R                         TAMP_BKP30R_Msk
+
+/********************  Bits definition for TAMP_BKP31R register  ***************/
+#define TAMP_BKP31R_Pos                     (0U)
+#define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP31R                         TAMP_BKP31R_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+#define TIM_CR1_DITHEN_Pos        (12U)
+#define TIM_CR1_DITHEN_Msk        (0x1UL << TIM_CR1_DITHEN_Pos)                /*!< 0x00001000 */
+#define TIM_CR1_DITHEN            TIM_CR1_DITHEN_Msk                           /*!<Dithering enable */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (     0x1UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (     0x2UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (     0x4UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
+#define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS4N_Pos         (15U)
+#define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
+#define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
+#define TIM_CR2_ADSYNC_Pos        (28U)
+#define TIM_CR2_ADSYNC_Msk        (0x1UL << TIM_CR2_ADSYNC_Pos)                /*!< 0x10000000 */
+#define TIM_CR2_ADSYNC            TIM_CR2_ADSYNC_Msk                           /*!<ADC synchronization */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+#define TIM_SMCR_SMSPE_Pos        (24U)
+#define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
+#define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
+#define TIM_SMCR_SMSPS_Pos        (25U)
+#define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
+#define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+#define TIM_DIER_IDXIE_Pos        (20U)
+#define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
+#define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
+#define TIM_DIER_DIRIE_Pos        (21U)
+#define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
+#define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
+#define TIM_DIER_IERRIE_Pos       (22U)
+#define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
+#define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
+#define TIM_DIER_TERRIE_Pos       (23U)
+#define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
+#define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_IDXF_Pos           (20U)
+#define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
+#define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
+#define TIM_SR_DIRF_Pos           (21U)
+#define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
+#define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
+#define TIM_SR_IERRF_Pos          (22U)
+#define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
+#define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
+#define TIM_SR_TERRF_Pos          (23U)
+#define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
+#define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NE_Pos        (14U)
+#define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
+#define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFUL << TIM_CCR5_CCR5_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFFUL << TIM_CCR6_CCR6_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_DTR2 register  *********************/
+#define TIM_DTR2_DTGF_Pos         (0U)
+#define TIM_DTR2_DTGF_Msk         (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
+#define TIM_DTR2_DTGF             TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
+#define TIM_DTR2_DTGF_0           (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
+#define TIM_DTR2_DTGF_1           (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
+#define TIM_DTR2_DTGF_2           (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
+#define TIM_DTR2_DTGF_3           (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
+#define TIM_DTR2_DTGF_4           (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
+#define TIM_DTR2_DTGF_5           (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
+#define TIM_DTR2_DTGF_6           (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
+#define TIM_DTR2_DTGF_7           (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
+#define TIM_DTR2_DTAE_Pos         (16U)
+#define TIM_DTR2_DTAE_Msk         (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
+#define TIM_DTR2_DTAE             TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
+#define TIM_DTR2_DTPE_Pos         (17U)
+#define TIM_DTR2_DTPE_Msk         (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
+#define TIM_DTR2_DTPE             TIM_DTR2_DTPE_Msk                            /*!<Deadtime preload enable */
+
+/*******************  Bit definition for TIM_ECR register  *********************/
+#define TIM_ECR_IE_Pos            (0U)
+#define TIM_ECR_IE_Msk            (0x1UL << TIM_ECR_IE_Pos)                    /*!< 0x00000001 */
+#define TIM_ECR_IE                TIM_ECR_IE_Msk                               /*!<Index enable */
+#define TIM_ECR_IDIR_Pos          (1U)
+#define TIM_ECR_IDIR_Msk          (0x3UL << TIM_ECR_IDIR_Pos)                  /*!< 0x00000006 */
+#define TIM_ECR_IDIR              TIM_ECR_IDIR_Msk                             /*!<IDIR[1:0] bits (Index direction)*/
+#define TIM_ECR_IDIR_0            (0x01UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000001 */
+#define TIM_ECR_IDIR_1            (0x02UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000002 */
+#define TIM_ECR_IBLK_Pos          (3U)
+#define TIM_ECR_IBLK_Msk          (0x3UL << TIM_ECR_IBLK_Pos)                  /*!< 0x00000018 */
+#define TIM_ECR_IBLK              TIM_ECR_IBLK_Msk                             /*!<IBLK[1:0] bits (Index blanking)*/
+#define TIM_ECR_IBLK_0            (0x01UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000008 */
+#define TIM_ECR_IBLK_1            (0x02UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000010 */
+#define TIM_ECR_FIDX_Pos          (5U)
+#define TIM_ECR_FIDX_Msk          (0x1UL << TIM_ECR_FIDX_Pos)                  /*!< 0x00000020 */
+#define TIM_ECR_FIDX              TIM_ECR_FIDX_Msk                             /*!<First index enable */
+#define TIM_ECR_IPOS_Pos          (6U)
+#define TIM_ECR_IPOS_Msk          (0x3UL << TIM_ECR_IPOS_Pos)                  /*!< 0x000000C0 */
+#define TIM_ECR_IPOS              TIM_ECR_IPOS_Msk                             /*!<IPOS[1:0] bits (Index positioning)*/
+#define TIM_ECR_IPOS_0            (0x01UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000040 */
+#define TIM_ECR_IPOS_1            (0x02UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000080 */
+#define TIM_ECR_PW_Pos            (16U)
+#define TIM_ECR_PW_Msk            (0xFFUL << TIM_ECR_PW_Pos)                   /*!< 0x00FF0000 */
+#define TIM_ECR_PW                TIM_ECR_PW_Msk                               /*!<PW[7:0] bits (Pulse width)*/
+#define TIM_ECR_PW_0              (0x01UL << TIM_ECR_PW_Pos)                   /*!< 0x00010000 */
+#define TIM_ECR_PW_1              (0x02UL << TIM_ECR_PW_Pos)                   /*!< 0x00020000 */
+#define TIM_ECR_PW_2              (0x04UL << TIM_ECR_PW_Pos)                   /*!< 0x00040000 */
+#define TIM_ECR_PW_3              (0x08UL << TIM_ECR_PW_Pos)                   /*!< 0x00080000 */
+#define TIM_ECR_PW_4              (0x10UL << TIM_ECR_PW_Pos)                   /*!< 0x00100000 */
+#define TIM_ECR_PW_5              (0x20UL << TIM_ECR_PW_Pos)                   /*!< 0x00200000 */
+#define TIM_ECR_PW_6              (0x40UL << TIM_ECR_PW_Pos)                   /*!< 0x00400000 */
+#define TIM_ECR_PW_7              (0x80UL << TIM_ECR_PW_Pos)                   /*!< 0x00800000 */
+#define TIM_ECR_PWPRSC_Pos        (24U)
+#define TIM_ECR_PWPRSC_Msk        (0x7UL << TIM_ECR_PWPRSC_Pos)                /*!< 0x07000000 */
+#define TIM_ECR_PWPRSC            TIM_ECR_PWPRSC_Msk                           /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
+#define TIM_ECR_PWPRSC_0          (0x01UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x01000000 */
+#define TIM_ECR_PWPRSC_1          (0x02UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x02000000 */
+#define TIM_ECR_PWPRSC_2          (0x04UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x04000000 */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits */
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits */
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits */
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits */
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM_AF1 register  ********************/
+#define TIM_AF1_BKINE_Pos        (0U)
+#define TIM_AF1_BKINE_Msk        (0x1UL << TIM_AF1_BKINE_Pos)                  /*!< 0x00000001 */
+#define TIM_AF1_BKINE            TIM_AF1_BKINE_Msk                             /*!<BRK BKIN input enable */
+#define TIM_AF1_BKCMP1E_Pos      (1U)
+#define TIM_AF1_BKCMP1E_Msk      (0x1UL << TIM_AF1_BKCMP1E_Pos)                /*!< 0x00000002 */
+#define TIM_AF1_BKCMP1E          TIM_AF1_BKCMP1E_Msk                           /*!<BRK CMP1 enable */
+#define TIM_AF1_BKCMP2E_Pos      (2U)
+#define TIM_AF1_BKCMP2E_Msk      (0x1UL << TIM_AF1_BKCMP2E_Pos)                /*!< 0x00000004 */
+#define TIM_AF1_BKCMP2E          TIM_AF1_BKCMP2E_Msk                           /*!<BRK CMP2 enable */
+#define TIM_AF1_BKCMP3E_Pos      (3U)
+#define TIM_AF1_BKCMP3E_Msk      (0x1UL << TIM_AF1_BKCMP3E_Pos)                /*!< 0x00000008 */
+#define TIM_AF1_BKCMP3E          TIM_AF1_BKCMP3E_Msk                           /*!<BRK CMP3 enable */
+#define TIM_AF1_BKCMP4E_Pos      (4U)
+#define TIM_AF1_BKCMP4E_Msk      (0x1UL << TIM_AF1_BKCMP4E_Pos)                /*!< 0x00000010 */
+#define TIM_AF1_BKCMP4E          TIM_AF1_BKCMP4E_Msk                           /*!<BRK CMP4 enable */
+#define TIM_AF1_BKCMP5E_Pos      (5U)
+#define TIM_AF1_BKCMP5E_Msk      (0x1UL << TIM_AF1_BKCMP5E_Pos)                /*!< 0x00000020 */
+#define TIM_AF1_BKCMP5E          TIM_AF1_BKCMP5E_Msk                           /*!<BRK CMP5 enable */
+#define TIM_AF1_BKCMP6E_Pos      (6U)
+#define TIM_AF1_BKCMP6E_Msk      (0x1UL << TIM_AF1_BKCMP6E_Pos)                /*!< 0x00000040 */
+#define TIM_AF1_BKCMP6E          TIM_AF1_BKCMP6E_Msk                           /*!<BRK CMP6 enable */
+#define TIM_AF1_BKCMP7E_Pos      (7U)
+#define TIM_AF1_BKCMP7E_Msk      (0x1UL << TIM_AF1_BKCMP7E_Pos)                /*!< 0x00000080 */
+#define TIM_AF1_BKCMP7E          TIM_AF1_BKCMP7E_Msk                           /*!<BRK CMP7 enable */
+#define TIM_AF1_BKCMP8E_Pos      (8U)
+#define TIM_AF1_BKCMP8E_Msk      (0x1UL << TIM_AF1_BKCMP8E_Pos)                /*!< 0x00000100 */
+#define TIM_AF1_BKCMP8E          TIM_AF1_BKCMP8E_Msk                           /*!<BRK CMP8 enable */
+#define TIM_AF1_BKINP_Pos        (9U)
+#define TIM_AF1_BKINP_Msk        (0x1UL << TIM_AF1_BKINP_Pos)                  /*!< 0x00000200 */
+#define TIM_AF1_BKINP            TIM_AF1_BKINP_Msk                             /*!<BRK BKIN input polarity */
+#define TIM_AF1_BKCMP1P_Pos      (10U)
+#define TIM_AF1_BKCMP1P_Msk      (0x1UL << TIM_AF1_BKCMP1P_Pos)                /*!< 0x00000400 */
+#define TIM_AF1_BKCMP1P          TIM_AF1_BKCMP1P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP2P_Pos      (11U)
+#define TIM_AF1_BKCMP2P_Msk      (0x1UL << TIM_AF1_BKCMP2P_Pos)                /*!< 0x00000800 */
+#define TIM_AF1_BKCMP2P          TIM_AF1_BKCMP2P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP3P_Pos      (12U)
+#define TIM_AF1_BKCMP3P_Msk      (0x1UL << TIM_AF1_BKCMP3P_Pos)                /*!< 0x00001000 */
+#define TIM_AF1_BKCMP3P          TIM_AF1_BKCMP3P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP4P_Pos      (13U)
+#define TIM_AF1_BKCMP4P_Msk      (0x1UL << TIM_AF1_BKCMP4P_Pos)                /*!< 0x00002000 */
+#define TIM_AF1_BKCMP4P          TIM_AF1_BKCMP4P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_ETRSEL_Pos       (14U)
+#define TIM_AF1_ETRSEL_Msk       (0xFUL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x0003C000 */
+#define TIM_AF1_ETRSEL           TIM_AF1_ETRSEL_Msk                            /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
+#define TIM_AF1_ETRSEL_0         (0x1UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM_AF1_ETRSEL_1         (0x2UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM_AF1_ETRSEL_2         (0x4UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM_AF1_ETRSEL_3         (0x8UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM_AF2 register  ********************/
+#define TIM_AF2_BK2INE_Pos       (0U)
+#define TIM_AF2_BK2INE_Msk       (0x1UL << TIM_AF2_BK2INE_Pos)                 /*!< 0x00000001 */
+#define TIM_AF2_BK2INE           TIM_AF2_BK2INE_Msk                            /*!<BRK2 BKIN input enable */
+#define TIM_AF2_BK2CMP8E_Pos     (8U)
+#define TIM_AF2_BK2CMP8E_Msk     (0x1UL << TIM_AF2_BK2CMP8E_Pos)               /*!< 0x00000100 */
+#define TIM_AF2_BK2CMP8E         TIM_AF2_BK2CMP8E_Msk                          /*!<BRK2 CMP8 enable */
+#define TIM_AF2_BK2INP_Pos       (9U)
+#define TIM_AF2_BK2INP_Msk       (0x1UL << TIM_AF2_BK2INP_Pos)                 /*!< 0x00000200 */
+#define TIM_AF2_BK2INP           TIM_AF2_BK2INP_Msk                            /*!<BRK2 BKIN input polarity */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
+#define TIM_DCR_DBSS_Pos          (16U)
+#define TIM_DCR_DBSS_Msk          (0xFUL << TIM_DCR_DBSS_Pos)                  /*!< 0x000F0000 */
+#define TIM_DCR_DBSS              TIM_DCR_DBSS_Msk                             /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
+#define TIM_DCR_DBSS_0            (0x01UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00010000 */
+#define TIM_DCR_DBSS_1            (0x02UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00020000 */
+#define TIM_DCR_DBSS_2            (0x04UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00040000 */
+#define TIM_DCR_DBSS_3            (0x08UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                    UCPD                                       */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bits definition for UCPD_CFG1 register  *******************/
+#define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
+#define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
+#define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
+#define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
+#define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
+#define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
+#define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
+#define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
+#define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
+#define UCPD_CFG1_IFRGAP_Pos                (6U)
+#define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
+#define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
+#define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
+#define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
+#define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
+#define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
+#define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
+#define UCPD_CFG1_TRANSWIN_Pos              (11U)
+#define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
+#define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
+#define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
+#define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
+#define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
+#define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
+#define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
+#define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
+#define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
+#define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
+#define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
+#define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
+#define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
+#define UCPD_CFG1_RXORDSETEN_Pos            (20U)
+#define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
+#define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
+#define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
+#define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
+#define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
+#define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
+#define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
+#define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
+#define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
+#define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
+#define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
+#define UCPD_CFG1_TXDMAEN_Pos               (29U)
+#define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
+#define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
+#define UCPD_CFG1_RXDMAEN_Pos               (30U)
+#define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
+#define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
+#define UCPD_CFG1_UCPDEN_Pos                (31U)
+#define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
+#define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
+
+/********************  Bits definition for UCPD_CFG2 register  *******************/
+#define UCPD_CFG2_RXFILTDIS_Pos             (0U)
+#define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
+#define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
+#define UCPD_CFG2_RXFILT2N3_Pos             (1U)
+#define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
+#define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
+#define UCPD_CFG2_FORCECLK_Pos              (2U)
+#define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
+#define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
+#define UCPD_CFG2_WUPEN_Pos                 (3U)
+#define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
+#define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
+#define UCPD_CFG2_RXAFILTEN_Pos             (8U)
+#define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)   /*!< 0x00000100 */
+#define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk              /*!< Rx analog filter enable */
+
+/********************  Bits definition for UCPD_CR register  *********************/
+#define UCPD_CR_TXMODE_Pos                  (0U)
+#define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
+#define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
+#define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
+#define UCPD_CR_TXSEND_Pos                  (2U)
+#define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
+#define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXHRST_Pos                  (3U)
+#define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
+#define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
+#define UCPD_CR_RXMODE_Pos                  (4U)
+#define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
+#define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
+#define UCPD_CR_PHYRXEN_Pos                 (5U)
+#define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
+#define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
+#define UCPD_CR_PHYCCSEL_Pos                (6U)
+#define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
+#define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
+#define UCPD_CR_ANASUBMODE_Pos              (7U)
+#define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
+#define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
+#define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
+#define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
+#define UCPD_CR_ANAMODE_Pos                 (9U)
+#define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
+#define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
+#define UCPD_CR_CCENABLE_Pos                (10U)
+#define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
+#define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
+#define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
+#define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
+#define UCPD_CR_USEEXTPHY_Pos               (12U)
+#define UCPD_CR_USEEXTPHY_Msk               (0x1UL << UCPD_CR_USEEXTPHY_Pos)     /*!< 0x00001000 */
+#define UCPD_CR_USEEXTPHY                   UCPD_CR_USEEXTPHY_Msk                /*!< Controls enable of USB Power Delivery transmitter */
+#define UCPD_CR_CC2VCONNEN_Pos              (13U)
+#define UCPD_CR_CC2VCONNEN_Msk              (0x1UL << UCPD_CR_CC2VCONNEN_Pos)    /*!< 0x00002000 */
+#define UCPD_CR_CC2VCONNEN                  UCPD_CR_CC2VCONNEN_Msk               /*!< VCONN enable for CC2 */
+#define UCPD_CR_CC1VCONNEN_Pos              (14U)
+#define UCPD_CR_CC1VCONNEN_Msk              (0x1UL << UCPD_CR_CC1VCONNEN_Pos)    /*!< 0x00004000 */
+#define UCPD_CR_CC1VCONNEN                  UCPD_CR_CC1VCONNEN_Msk               /*!< VCONN enable for CC1 */
+#define UCPD_CR_DBATEN_Pos                  (15U)
+#define UCPD_CR_DBATEN_Msk                  (0x1UL << UCPD_CR_DBATEN_Pos)        /*!< 0x00008000 */
+#define UCPD_CR_DBATEN                      UCPD_CR_DBATEN_Msk                   /*!< Enable dead battery behavior (Active High) */
+#define UCPD_CR_FRSTX_Pos                   (17U)
+#define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
+#define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
+#define UCPD_CR_RDCH_Pos                    (18U)
+#define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
+#define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
+#define UCPD_CR_RPUSBABSENT_Pos             (19U)
+#define UCPD_CR_RPUSBABSENT_Msk             (0x1UL << UCPD_CR_RPUSBABSENT_Pos)   /*!< 0x00080000 */
+#define UCPD_CR_RPUSBABSENT                 UCPD_CR_RPUSBABSENT_Msk              /*!<  */
+#define UCPD_CR_CC1TCDIS_Pos                (20U)
+#define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
+#define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
+#define UCPD_CR_CC2TCDIS_Pos                (21U)
+#define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
+#define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
+
+/********************  Bits definition for UCPD_IMR register  ********************/
+#define UCPD_IMR_TXISIE_Pos                 (0U)
+#define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
+#define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
+#define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
+#define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
+#define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
+#define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
+#define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
+#define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
+#define UCPD_IMR_TXMSGABTIE_Pos             (3U)
+#define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
+#define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
+#define UCPD_IMR_HRSTDISCIE_Pos             (4U)
+#define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
+#define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
+#define UCPD_IMR_HRSTSENTIE_Pos             (5U)
+#define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
+#define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
+#define UCPD_IMR_TXUNDIE_Pos                (6U)
+#define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
+#define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
+#define UCPD_IMR_RXNEIE_Pos                 (8U)
+#define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
+#define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
+#define UCPD_IMR_RXORDDETIE_Pos             (9U)
+#define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
+#define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
+#define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
+#define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
+#define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
+#define UCPD_IMR_RXOVRIE_Pos                (11U)
+#define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
+#define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
+#define UCPD_IMR_RXMSGENDIE_Pos             (12U)
+#define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
+#define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
+#define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
+#define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
+#define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
+#define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
+#define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
+#define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
+
+/********************  Bits definition for UCPD_SR register  *********************/
+#define UCPD_SR_TXIS_Pos                    (0U)
+#define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
+#define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
+#define UCPD_SR_TXMSGDISC_Pos               (1U)
+#define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
+#define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
+#define UCPD_SR_TXMSGSENT_Pos               (2U)
+#define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
+#define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
+#define UCPD_SR_TXMSGABT_Pos                (3U)
+#define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
+#define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
+#define UCPD_SR_HRSTDISC_Pos                (4U)
+#define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
+#define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
+#define UCPD_SR_HRSTSENT_Pos                (5U)
+#define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
+#define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
+#define UCPD_SR_TXUND_Pos                   (6U)
+#define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
+#define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
+#define UCPD_SR_RXNE_Pos                    (8U)
+#define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
+#define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
+#define UCPD_SR_RXORDDET_Pos                (9U)
+#define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
+#define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
+#define UCPD_SR_RXHRSTDET_Pos               (10U)
+#define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
+#define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
+#define UCPD_SR_RXOVR_Pos                   (11U)
+#define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
+#define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
+#define UCPD_SR_RXMSGEND_Pos                (12U)
+#define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
+#define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
+#define UCPD_SR_RXERR_Pos                   (13U)
+#define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
+#define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
+#define UCPD_SR_TYPECEVT1_Pos               (14U)
+#define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
+#define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
+#define UCPD_SR_TYPECEVT2_Pos               (15U)
+#define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
+#define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
+#define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
+#define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
+
+/********************  Bits definition for UCPD_ICR register  ********************/
+#define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
+#define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
+#define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
+#define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
+#define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
+#define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
+#define UCPD_ICR_TXMSGABTCF_Pos             (3U)
+#define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
+#define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
+#define UCPD_ICR_HRSTDISCCF_Pos             (4U)
+#define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
+#define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
+#define UCPD_ICR_HRSTSENTCF_Pos             (5U)
+#define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
+#define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
+#define UCPD_ICR_TXUNDCF_Pos                (6U)
+#define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
+#define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
+#define UCPD_ICR_RXORDDETCF_Pos             (9U)
+#define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
+#define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
+#define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
+#define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
+#define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
+#define UCPD_ICR_RXOVRCF_Pos                (11U)
+#define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
+#define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
+#define UCPD_ICR_RXMSGENDCF_Pos             (12U)
+#define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
+#define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
+#define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
+#define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
+#define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
+#define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
+#define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
+#define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
+
+/********************  Bits definition for UCPD_TXORDSET register  ***************/
+#define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
+#define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
+#define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
+
+/********************  Bits definition for UCPD_TXPAYSZ register  ****************/
+#define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
+#define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
+
+/********************  Bits definition for UCPD_TXDR register  *******************/
+#define UCPD_TXDR_TXDATA_Pos                (0U)
+#define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                 /*!< Tx Data Register */
+
+/********************  Bits definition for UCPD_RXORDSET register  ***************/
+#define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
+#define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
+#define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
+#define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
+#define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
+#define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
+#define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
+#define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
+#define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
+#define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
+
+/********************  Bits definition for UCPD_RXPAYSZ register  ****************/
+#define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
+#define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
+
+/********************  Bits definition for UCPD_RXDR register  *******************/
+#define UCPD_RXDR_RXDATA_Pos                (0U)
+#define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
+
+/********************  Bits definition for UCPD_RXORDEXT1 register  **************/
+#define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
+#define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+/********************  Bits definition for UCPD_RXORDEXT2 register  **************/
+#define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
+#define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                    (0U)
+#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
+#define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
+#define USART_CR1_UESM_Pos                  (1U)
+#define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
+#define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                    (2U)
+#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
+#define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                    (3U)
+#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
+#define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos                (4U)
+#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos                (5U)
+#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
+#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
+#define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos                  (6U)
+#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
+#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos                 (7U)
+#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos                  (8U)
+#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
+#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                    (9U)
+#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
+#define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
+#define USART_CR1_PCE_Pos                   (10U)
+#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
+#define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos                  (11U)
+#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
+#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                     (12U)
+#define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                         USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                    (12U)
+#define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
+#define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos                   (13U)
+#define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
+#define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos                  (14U)
+#define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
+#define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match Interrupt Enable */
+#define USART_CR1_OVER8_Pos                 (15U)
+#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos                  (16U)
+#define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
+#define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos                  (21U)
+#define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
+#define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos                 (26U)
+#define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
+#define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
+#define USART_CR1_EOBIE_Pos                 (27U)
+#define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
+#define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
+#define USART_CR1_M1_Pos                    (28U)
+#define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
+#define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos                (29U)
+#define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos                (30U)
+#define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
+#define USART_CR1_RXFFIE_Pos                (31U)
+#define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos                 (0U)
+#define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
+#define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
+#define USART_CR2_DIS_NSS_Pos               (3U)
+#define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos                 (4U)
+#define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
+#define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos                  (5U)
+#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
+#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos                 (6U)
+#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
+#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos                  (8U)
+#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
+#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos                  (9U)
+#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
+#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos                  (10U)
+#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
+#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos                 (11U)
+#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
+#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
+#define USART_CR2_STOP_Pos                  (12U)
+#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
+#define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos                 (14U)
+#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
+#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos                  (15U)
+#define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
+#define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos                 (16U)
+#define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
+#define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos                 (17U)
+#define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
+#define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos               (18U)
+#define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
+#define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos              (19U)
+#define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos                 (20U)
+#define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
+#define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos               (21U)
+#define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
+#define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos                 (23U)
+#define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
+#define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos                   (24U)
+#define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
+#define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos                   (0U)
+#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
+#define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos                  (1U)
+#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
+#define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos                  (2U)
+#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
+#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos                 (3U)
+#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
+#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos                  (4U)
+#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
+#define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos                  (5U)
+#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
+#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos                  (6U)
+#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
+#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos                  (7U)
+#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
+#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos                  (8U)
+#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
+#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos                  (9U)
+#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
+#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos                 (10U)
+#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
+#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos                (11U)
+#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos                (12U)
+#define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos                  (13U)
+#define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
+#define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos                   (14U)
+#define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
+#define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos                   (15U)
+#define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
+#define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos               (17U)
+#define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos                   (20U)
+#define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
+#define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos                 (22U)
+#define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
+#define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos                (23U)
+#define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TCBGTIE_Pos               (24U)
+#define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_Pos               (25U)
+#define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
+#define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos                (28U)
+#define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TXFTCFG_Pos               (29U)
+#define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
+#define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_LPUART                    ((uint32_t)0x000FFFFF)                  /*!< LPUART Baud rate register [19:0] */
+#define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos                  (0U)
+#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
+#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos                   (8U)
+#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
+#define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos                  (0U)
+#define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Timeout Value */
+#define USART_RTOR_BLEN_Pos                 (24U)
+#define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos                 (0U)
+#define USART_RQR_ABRRQ_Msk                 (0x1UL << USART_RQR_ABRRQ_Pos)          /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                     USART_RQR_ABRRQ_Msk                     /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos                 (1U)
+#define USART_RQR_SBKRQ_Msk                 (0x1UL << USART_RQR_SBKRQ_Pos)          /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                     USART_RQR_SBKRQ_Msk                     /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos                  (2U)
+#define USART_RQR_MMRQ_Msk                  (0x1UL << USART_RQR_MMRQ_Pos)           /*!< 0x00000004 */
+#define USART_RQR_MMRQ                      USART_RQR_MMRQ_Msk                      /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos                 (3U)
+#define USART_RQR_RXFRQ_Msk                 (0x1UL << USART_RQR_RXFRQ_Pos)          /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                     USART_RQR_RXFRQ_Msk                     /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos                 (4U)
+#define USART_RQR_TXFRQ_Msk                 (0x1UL << USART_RQR_TXFRQ_Pos)          /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                     USART_RQR_TXFRQ_Msk                     /*!< Transmit Data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                    (0U)
+#define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
+#define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
+#define USART_ISR_FE_Pos                    (1U)
+#define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
+#define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
+#define USART_ISR_NE_Pos                    (2U)
+#define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
+#define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise Error detection Flag */
+#define USART_ISR_ORE_Pos                   (3U)
+#define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
+#define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos                  (4U)
+#define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
+#define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos                  (5U)
+#define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
+#define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
+#define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
+#define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                    (6U)
+#define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
+#define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos                   (7U)
+#define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
+#define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
+#define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
+#define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos                  (8U)
+#define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
+#define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos                 (9U)
+#define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
+#define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
+#define USART_ISR_CTS_Pos                   (10U)
+#define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
+#define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS Flag */
+#define USART_ISR_RTOF_Pos                  (11U)
+#define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
+#define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Timeout */
+#define USART_ISR_EOBF_Pos                  (12U)
+#define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
+#define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos                   (13U)
+#define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
+#define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
+#define USART_ISR_ABRE_Pos                  (14U)
+#define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
+#define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos                  (15U)
+#define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
+#define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos                  (16U)
+#define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
+#define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
+#define USART_ISR_CMF_Pos                   (17U)
+#define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
+#define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos                  (18U)
+#define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
+#define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos                   (19U)
+#define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
+#define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos                   (20U)
+#define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
+#define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
+#define USART_ISR_TEACK_Pos                 (21U)
+#define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
+#define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos                 (22U)
+#define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
+#define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos                  (23U)
+#define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
+#define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
+#define USART_ISR_RXFF_Pos                  (24U)
+#define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
+#define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
+#define USART_ISR_TCBGT_Pos                 (25U)
+#define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
+#define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
+#define USART_ISR_RXFT_Pos                  (26U)
+#define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
+#define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
+#define USART_ISR_TXFT_Pos                  (27U)
+#define USART_ISR_TXFT_Msk                 (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
+#define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos                  (0U)
+#define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
+#define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos                  (1U)
+#define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
+#define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos                  (2U)
+#define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
+#define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
+#define USART_ICR_ORECF_Pos                 (3U)
+#define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
+#define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos                (4U)
+#define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
+#define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos                (5U)
+#define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
+#define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
+#define USART_ICR_TCCF_Pos                  (6U)
+#define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
+#define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos               (7U)
+#define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos                 (8U)
+#define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
+#define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos                 (9U)
+#define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
+#define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos                 (11U)
+#define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
+#define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos                 (12U)
+#define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
+#define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos                 (13U)
+#define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
+#define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF_Pos                  (17U)
+#define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
+#define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos                  (20U)
+#define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
+#define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ****************/
+#define USART_PRESC_PRESCALER_Pos           (0U)
+#define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_CSRSTDONE_Pos            (29U)
+#define USB_OTG_GRSTCTL_CSRSTDONE_Msk            (0x1UL << USB_OTG_GRSTCTL_CSRSTDONE_Pos) /*!< 0x20000000 */
+#define USB_OTG_GRSTCTL_CSRSTDONE                USB_OTG_GRSTCTL_CSRSTDONE_Msk   /*!< Core soft reset done            */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_HS_GCCFG register  ********************/
+#define USB_OTG_GCCFG_CHGDET_Pos                 (0U)
+#define USB_OTG_GCCFG_CHGDET_Msk                 (0x1U << USB_OTG_GCCFG_CHGDET_Pos)           /*!< 0x00000001 */
+#define USB_OTG_GCCFG_CHGDET                     USB_OTG_GCCFG_CHGDET_Msk                     /*!< Battery Charger Detection */
+#define USB_OTG_GCCFG_FSVPLUS_Pos                (1U)
+#define USB_OTG_GCCFG_FSVPLUS_Msk                (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos)          /*!< 0x00000002 */
+#define USB_OTG_GCCFG_FSVPLUS                    USB_OTG_GCCFG_FSVPLUS_Msk                    /*!< Single-Ended DP2 indicator DP voltage level  */
+#define USB_OTG_GCCFG_FSVMINUS_Pos               (2U)
+#define USB_OTG_GCCFG_FSVMINUS_Msk               0x1U << USB_OTG_GCCFG_FSVMINUS_Pos)         /*!< 0x00000004 */
+#define USB_OTG_GCCFG_FSVMINUS                   USB_OTG_GCCFG_FSVMINUS_Msk                  /*!< Single-Ended DM2 indicator DM voltage level  */
+#define USB_OTG_GCCFG_SESSVLD_Pos                (3U)
+#define USB_OTG_GCCFG_SESSVLD_Msk                (0x1U << USB_OTG_GCCFG_SESSVLD_Pos)          /*!< 0x00000008 */
+#define USB_OTG_GCCFG_SESSVLD                    USB_OTG_GCCFG_SESSVLD_Msk                    /*!< VBUS session valid indicator: Vbus is above VBUS session threshold.  */
+#define USB_OTG_GCCFG_VBUSVLD_Pos                (4U)
+#define USB_OTG_GCCFG_VBUSVLD_Msk                (0x1U << USB_OTG_GCCFG_VBUSVLD_Pos)          /*!< 0x00000010 */
+#define USB_OTG_GCCFG_VBUSVLD                    USB_OTG_GCCFG_VBUSVLD_Msk                    /*!< VBUS session valid indicator: VBUS is above VBUS valid threshold.  */
+#define USB_OTG_GCCFG_H_CDPEN_Pos                (16U)
+#define USB_OTG_GCCFG_H_CDPEN_Msk                (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos)          /*!< 0x00010000 */
+#define USB_OTG_GCCFG_H_CDPEN                    USB_OTG_GCCFG_H_CDPEN_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
+#define USB_OTG_GCCFG_H_CDPDETEN_Pos             (17U)
+#define USB_OTG_GCCFG_H_CDPDETEN_Msk             (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos)       /*!< 0x00020000 */
+#define USB_OTG_GCCFG_H_CDPDETEN                 USB_OTG_GCCFG_H_CDPDETEN_Msk                 /*!< Enable of voltage detector on DP for CDP port  */
+#define USB_OTG_GCCFG_H_VDMSRCEN_Pos             (18U)
+#define USB_OTG_GCCFG_H_VDMSRCEN_Msk             (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos)       /*!< 0x00040000 */
+#define USB_OTG_GCCFG_H_VDMSRCEN                 USB_OTG_GCCFG_H_VDMSRCEN_Msk                 /*!< Enable Voltage source on DM for CDP port */
+#define USB_OTG_GCCFG_DCDETEN_Pos                (19U)
+#define USB_OTG_GCCFG_DCDETEN_Msk                (0x1U << USB_OTG_GCCFG_DCDETEN_Pos)          /*!< 0x00080000 */
+#define USB_OTG_GCCFG_DCDETEN                    USB_OTG_GCCFG_DCDETEN_Msk                    /*!< Data contact detection (DCD) mode enable */
+#define USB_OTG_GCCFG_PDETEN_Pos                 (20U)
+#define USB_OTG_GCCFG_PDETEN_Msk                 (0x1U << USB_OTG_GCCFG_PDETEN_Pos)           /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDETEN                     USB_OTG_GCCFG_PDETEN_Msk                     /*!< Primary detection (PD) mode enable */
+#define USB_OTG_GCCFG_SDETEN_Pos                 (22U)
+#define USB_OTG_GCCFG_SDETEN_Msk                 (0x1U << USB_OTG_GCCFG_SDETEN_Pos)           /*!< 0x00400000 */
+#define USB_OTG_GCCFG_SDETEN                     USB_OTG_GCCFG_SDETEN_Msk                     /*!< Secondary detection (PD) mode enable */
+#define USB_OTG_GCCFG_VBVALOVAL_Pos              (23U)
+#define USB_OTG_GCCFG_VBVALOVAL_Msk              (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos)        /*!< 0x00800000 */
+#define USB_OTG_GCCFG_VBVALOVAL                  USB_OTG_GCCFG_VBVALOVAL_Msk                  /*!< Value of VBUSVLDEXT0 PHY input */
+#define USB_OTG_GCCFG_VBVALEXTOEN_Pos            (24U)
+#define USB_OTG_GCCFG_VBVALEXTOEN_Msk            (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos)      /*!< 0x01000000 */
+#define USB_OTG_GCCFG_VBVALEXTOEN                USB_OTG_GCCFG_VBVALEXTOEN_Msk                /*!< Enables of VBUSVLDEXT0 PHY input override */
+#define USB_OTG_GCCFG_PULLDOWNEN_Pos             (25U)
+#define USB_OTG_GCCFG_PULLDOWNEN_Msk             (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos)       /*!< 0x02000000 */
+#define USB_OTG_GCCFG_PULLDOWNEN                 USB_OTG_GCCFG_PULLDOWNEN_Msk                 /*!< Enables Host pulldown resistors, used when ID PAD is disabled */
+#define USB_OTG_GCCFG_FORCEBCMODE_Pos            (26U)
+#define USB_OTG_GCCFG_FORCEBCMODE_Msk            (0x1U << USB_OTG_GCCFG_FORCEBCMODE_Pos)      /*!< 0x04000000 */
+#define USB_OTG_GCCFG_FORCEBCMODE                USB_OTG_GCCFG_FORCEBCMODE_Msk                /*!< Force Battery charging (BC) mode */
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Pos           (28U)
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Msk           (0x1U << USB_OTG_GCCFG_IDPULLUP_DIS_Pos)      /*!< 0x10000000 */
+#define USB_OTG_GCCFG_IDPULLUP_DIS               USB_OTG_GCCFG_IDPULLUP_DIS_Msk                /*!< Analog ID Input Sample Disable: disable sampling on the analog ID line */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL1 register  ********************/
+#define USB_OTG_PCGCCTL1_GATEEN_Pos               (0U)
+#define USB_OTG_PCGCCTL1_GATEEN_Msk               (0x1UL << USB_OTG_PCGCCTL1_GATEEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL1_GATEEN                   USB_OTG_PCGCCTL1_GATEEN_Msk   /*!< Enable Active Clock Gating */
+#define USB_OTG_PCGCCTL1_COUNTER_Pos              (1U)
+#define USB_OTG_PCGCCTL1_COUNTER_Msk              (0x3UL << USB_OTG_PCGCCTL1_COUNTER_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL1_COUNTER                  USB_OTG_PCGCCTL1_COUNTER_Msk   /*!< Count to Gate Clock */
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Pos            (3U)
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Msk            (0x1UL << USB_OTG_PCGCCTL1_RAMGATEEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL1_RAMGATEEN                USB_OTG_PCGCCTL1_RAMGATEEN_Msk   /*!< RAM Clock Gating Enable */
+
+/*!< USB registers base address */
+#define USB_OTG_GLOBAL_BASE                       (0x000UL)
+#define USB_OTG_DEVICE_BASE                       (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE                  (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE                 (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                       (0x20UL)
+#define USB_OTG_HOST_BASE                         (0x400UL)
+#define USB_OTG_HOST_PORT_BASE                    (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE                 (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE                 (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                      (0xE00UL)
+#define USB_OTG_FIFO_BASE                         (0x1000UL)
+#define USB_OTG_FIFO_SIZE                         (0x1000UL)
+#define USB_OTG_HS_EP_NBR                         (9UL)            /*!< Number of USB HS Device endpoints */
+#define USB_OTG_HS_CH_NBR                         (16UL)           /*!< Number of USB HS Host channels */
+
+/********************  Bit definition for USB_USBPHYC_CR register  ********************/
+#define USB_USBPHYC_CR_RETENABLEN1_Pos          (0U)
+#define USB_USBPHYC_CR_RETENABLEN1_Msk          (0x1UL << USB_USBPHYC_CR_RETENABLEN1_Pos)    /*!< 0x00000001 */
+#define USB_USBPHYC_CR_RETENABLEN1              USB_USBPHYC_CR_RETENABLEN1_Msk               /*!< Retention mode enable */
+#define USB_USBPHYC_CR_AUTORSMENB1_Pos          (1U)
+#define USB_USBPHYC_CR_AUTORSMENB1_Msk          (0x1UL << USB_USBPHYC_CR_AUTORSMENB1_Pos)    /*!< 0x00000002 */
+#define USB_USBPHYC_CR_AUTORSMENB1              USB_USBPHYC_CR_AUTORSMENB1_Msk               /*!< Auto-resume mode enable */
+#define USB_USBPHYC_CR_CMN_Pos                  (2U)
+#define USB_USBPHYC_CR_CMN_Msk                  (0x1UL << USB_USBPHYC_CR_CMN_Pos)            /*!< 0x00000004 */
+#define USB_USBPHYC_CR_CMN                      USB_USBPHYC_CR_CMN_Msk                       /*!< Controls the power down of analog blocks during Suspend and Sleep */
+#define USB_USBPHYC_CR_FSEL_Pos                 (4U)
+#define USB_USBPHYC_CR_FSEL_Msk                 (0x7UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000070 */
+#define USB_USBPHYC_CR_FSEL                     USB_USBPHYC_CR_FSEL_Msk                      /*!< Frequency selection */
+#define USB_USBPHYC_CR_FSEL_0                   (0x1UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000010 */
+#define USB_USBPHYC_CR_FSEL_1                   (0x2UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000020 */
+#define USB_USBPHYC_CR_FSEL_2                   (0x3UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000040 */
+#define USB_USBPHYC_CR_OTGDISABLE0_Pos          (16U)
+#define USB_USBPHYC_CR_OTGDISABLE0_Msk          (0x1UL << USB_USBPHYC_CR_OTGDISABLE0_Pos)    /*!< 0x00010000 */
+#define USB_USBPHYC_CR_OTGDISABLE0              USB_USBPHYC_CR_OTGDISABLE0_Msk               /*!< OTG disable 0 */
+#define USB_USBPHYC_CR_DRVVBUS0_Pos             (17U)
+#define USB_USBPHYC_CR_DRVVBUS0_Msk             (0x1UL << USB_USBPHYC_CR_DRVVBUS0_Pos)       /*!< 0x00020000 */
+#define USB_USBPHYC_CR_DRVVBUS0                 USB_USBPHYC_CR_DRVVBUS0_Msk                  /*!< Drive VBUS 0 */
+#define USB_USBPHYC_CR_SELOTGDBG_Pos            (31U)
+#define USB_USBPHYC_CR_SELOTGDBG_Msk            (0x1UL << USB_USBPHYC_CR_SELOTGDBG_Pos)      /*!< 0x80000000 */
+#define USB_USBPHYC_CR_SELOTGDBG                USB_USBPHYC_CR_SELOTGDBG_Msk                 /*!< Select HS PHY debug port */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)
+#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)
+#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos     (3U)
+#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos     (4U)
+#define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
+#define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000040 */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos                (0U)
+#define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos                       (0U)
+#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
+#define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
+#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
+#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
+#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
+#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
+#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
+#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
+#define WWDG_CR_WDGA_Pos                    (7U)
+#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
+#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos                      (0U)
+#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
+#define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
+#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
+#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
+#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
+#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
+#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
+#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
+#define WWDG_CFR_EWI_Pos                    (9U)
+#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
+#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
+#define WWDG_CFR_WDGTB_Pos                  (11U)
+#define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos                    (0U)
+#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
+#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Extended-SPI Interface (XSPI)                         */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for XSPI_CR register  *******************/
+#define XSPI_CR_EN_Pos                   (0U)
+#define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)            /*!< 0x00000001 */
+#define XSPI_CR_EN                       XSPI_CR_EN_Msk                       /*!< Enable */
+#define XSPI_CR_ABORT_Pos                (1U)
+#define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
+#define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define XSPI_CR_DMAEN_Pos                (2U)
+#define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
+#define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define XSPI_CR_TCEN_Pos                 (3U)
+#define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
+#define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define XSPI_CR_DMM_Pos                  (6U)
+#define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)           /*!< 0x00000040 */
+#define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                      /*!< Dual Memory Mode */
+#define XSPI_CR_FSEL_Pos                 (7U)
+#define XSPI_CR_FSEL_Msk                 (0x1UL << XSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
+#define XSPI_CR_FSEL                     XSPI_CR_FSEL_Msk                     /*!< Flash Select */
+#define XSPI_CR_FTHRES_Pos               (8U)
+#define XSPI_CR_FTHRES_Msk               (0x3FUL << XSPI_CR_FTHRES_Pos)       /*!< 0x00003F00 */
+#define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */
+#define XSPI_CR_TEIE_Pos                 (16U)
+#define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
+#define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define XSPI_CR_TCIE_Pos                 (17U)
+#define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
+#define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define XSPI_CR_FTIE_Pos                 (18U)
+#define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
+#define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define XSPI_CR_SMIE_Pos                 (19U)
+#define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
+#define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define XSPI_CR_TOIE_Pos                 (20U)
+#define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
+#define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define XSPI_CR_APMS_Pos                 (22U)
+#define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)          /*!< 0x00400000 */
+#define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */
+#define XSPI_CR_PMM_Pos                  (23U)
+#define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)           /*!< 0x00800000 */
+#define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define XSPI_CR_CSSEL_Pos                (24U)
+#define XSPI_CR_CSSEL_Msk                (0x1UL << XSPI_CR_CSSEL_Pos)         /*!< 0x01000000 */
+#define XSPI_CR_CSSEL                    XSPI_CR_CSSEL_Msk                    /*!< Chip Select Selection */
+#define XSPI_CR_NOPREF_Pos               (25U)
+#define XSPI_CR_NOPREF_Msk               (0x1UL << XSPI_CR_NOPREF_Pos)        /*!< 0x02000000 */
+#define XSPI_CR_NOPREF                   XSPI_CR_NOPREF_Msk                   /*!< No Prefetch Data */
+#define XSPI_CR_NOPREF_AXI_Pos           (26U)
+#define XSPI_CR_NOPREF_AXI_Msk           (0x1UL << XSPI_CR_NOPREF_AXI_Pos)    /*!< 0x04000000 */
+#define XSPI_CR_NOPREF_AXI               XSPI_CR_NOPREF_AXI_Msk               /*!< No Prefetch For Signaled AXI Transactions */
+#define XSPI_CR_FMODE_Pos                (28U)
+#define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)         /*!< 0x30000000 */
+#define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                    /*!< Functional Mode */
+#define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)         /*!< 0x10000000 */
+#define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)         /*!< 0x20000000 */
+#define XSPI_CR_MSEL_Pos                 (30U)
+#define XSPI_CR_MSEL_Msk                 (0x3UL << XSPI_CR_MSEL_Pos)          /*!< 0xC0000000 */
+#define XSPI_CR_MSEL                     XSPI_CR_MSEL_Msk                     /*!< Memory Select */
+#define XSPI_CR_MSEL_0                   (0x1UL << XSPI_CR_MSEL_Pos)          /*!< 0x40000000 */
+#define XSPI_CR_MSEL_1                   (0x2UL << XSPI_CR_MSEL_Pos)          /*!< 0x80000000 */
+
+/****************  Bit definition for XSPI_DCR1 register  ******************/
+#define XSPI_DCR1_CKMODE_Pos             (0U)
+#define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */
+#define XSPI_DCR1_FRCK_Pos               (1U)
+#define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)        /*!< 0x00000002 */
+#define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */
+#define XSPI_DCR1_CSHT_Pos               (8U)
+#define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)       /*!< 0x00003F00 */
+#define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
+#define XSPI_DCR1_DEVSIZE_Pos            (16U)
+#define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */
+#define XSPI_DCR1_EXTENDMEM_Pos          (21U)
+#define XSPI_DCR1_EXTENDMEM_Msk          (0x1UL << XSPI_DCR1_EXTENDMEM_Pos)   /*!< 0x00200000 */
+#define XSPI_DCR1_EXTENDMEM              XSPI_DCR1_EXTENDMEM_Msk              /*!< Extended Memory Support */
+#define XSPI_DCR1_MTYP_Pos               (24U)
+#define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x07000000 */
+#define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                   /*!< Memory Type */
+#define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x01000000 */
+#define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x02000000 */
+#define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x04000000 */
+
+/****************  Bit definition for XSPI_DCR2 register  ******************/
+#define XSPI_DCR2_PRESCALER_Pos          (0U)
+#define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)  /*!< 0x000000FF */
+#define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */
+#define XSPI_DCR2_WRAPSIZE_Pos           (16U)
+#define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00070000 */
+#define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */
+#define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00010000 */
+#define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00020000 */
+#define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00040000 */
+
+/****************  Bit definition for XSPI_DCR3 register  ******************/
+#define XSPI_DCR3_MAXTRAN_Pos            (0U)
+#define XSPI_DCR3_MAXTRAN_Msk            (0xFFUL << XSPI_DCR3_MAXTRAN_Pos)    /*!< 0x000000FF */
+#define XSPI_DCR3_MAXTRAN                XSPI_DCR3_MAXTRAN_Msk                /*!< Maximum transfer */
+#define XSPI_DCR3_CSBOUND_Pos            (16U)
+#define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                /*!< Maximum transfer */
+
+/****************  Bit definition for XSPI_DCR4 register  ******************/
+#define XSPI_DCR4_REFRESH_Pos            (0U)
+#define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */
+
+/*****************  Bit definition for XSPI_SR register  *******************/
+#define XSPI_SR_TEF_Pos                  (0U)
+#define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)           /*!< 0x00000001 */
+#define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define XSPI_SR_TCF_Pos                  (1U)
+#define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)           /*!< 0x00000002 */
+#define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define XSPI_SR_FTF_Pos                  (2U)
+#define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)           /*!< 0x00000004 */
+#define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */
+#define XSPI_SR_SMF_Pos                  (3U)
+#define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)           /*!< 0x00000008 */
+#define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define XSPI_SR_TOF_Pos                  (4U)
+#define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)           /*!< 0x00000010 */
+#define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define XSPI_SR_BUSY_Pos                 (5U)
+#define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
+#define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                     /*!< Busy */
+#define XSPI_SR_FLEVEL_Pos               (8U)
+#define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)       /*!< 0x00007F00 */
+#define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */
+
+/****************  Bit definition for XSPI_FCR register  *******************/
+#define XSPI_FCR_CTEF_Pos                (0U)
+#define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
+#define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define XSPI_FCR_CTCF_Pos                (1U)
+#define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
+#define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define XSPI_FCR_CSMF_Pos                (3U)
+#define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
+#define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define XSPI_FCR_CTOF_Pos                (4U)
+#define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
+#define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/****************  Bit definition for XSPI_DLR register  *******************/
+#define XSPI_DLR_DL_Pos                  (0U)
+#define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
+#define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                      /*!< Data Length */
+
+/*****************  Bit definition for XSPI_AR register  *******************/
+#define XSPI_AR_ADDRESS_Pos              (0U)
+#define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                  /*!< Address */
+
+/*****************  Bit definition for XSPI_DR register  *******************/
+#define XSPI_DR_DATA_Pos                 (0U)
+#define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
+#define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                     /*!< Data */
+
+/***************  Bit definition for XSPI_PSMKR register  ******************/
+#define XSPI_PSMKR_MASK_Pos              (0U)
+#define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                  /*!< Status mask */
+
+/***************  Bit definition for XSPI_PSMAR register  ******************/
+#define XSPI_PSMAR_MATCH_Pos             (0U)
+#define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                 /*!< Status match */
+
+/****************  Bit definition for XSPI_PIR register  *******************/
+#define XSPI_PIR_INTERVAL_Pos            (0U)
+#define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
+#define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */
+
+/****************  Bit definition for XSPI_CCR register  *******************/
+#define XSPI_CCR_IMODE_Pos               (0U)
+#define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000007 */
+#define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */
+#define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000001 */
+#define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000002 */
+#define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000004 */
+#define XSPI_CCR_IDTR_Pos                (3U)
+#define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)         /*!< 0x00000008 */
+#define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */
+#define XSPI_CCR_ISIZE_Pos               (4U)
+#define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000030 */
+#define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */
+#define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000010 */
+#define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000020 */
+#define XSPI_CCR_ADMODE_Pos              (8U)
+#define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000700 */
+#define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                  /*!< Address Mode */
+#define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000100 */
+#define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000200 */
+#define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define XSPI_CCR_ADDTR_Pos               (11U)
+#define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)        /*!< 0x00000800 */
+#define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */
+#define XSPI_CCR_ADSIZE_Pos              (12U)
+#define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                  /*!< Address Size */
+#define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define XSPI_CCR_ABMODE_Pos              (16U)
+#define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00070000 */
+#define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */
+#define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00010000 */
+#define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00020000 */
+#define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00040000 */
+#define XSPI_CCR_ABDTR_Pos               (19U)
+#define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)        /*!< 0x00080000 */
+#define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_CCR_ABSIZE_Pos              (20U)
+#define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00300000 */
+#define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */
+#define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00100000 */
+#define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00200000 */
+#define XSPI_CCR_DMODE_Pos               (24U)
+#define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)        /*!< 0x07000000 */
+#define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                   /*!< Data Mode */
+#define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)        /*!< 0x04000000 */
+#define XSPI_CCR_DDTR_Pos                (27U)
+#define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)         /*!< 0x08000000 */
+#define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */
+#define XSPI_CCR_DQSE_Pos                (29U)
+#define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)         /*!< 0x20000000 */
+#define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                    /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_TCR register  *******************/
+#define XSPI_TCR_DCYC_Pos                (0U)
+#define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)        /*!< 0x0000001F */
+#define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */
+#define XSPI_TCR_DHQC_Pos                (28U)
+#define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)         /*!< 0x10000000 */
+#define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */
+#define XSPI_TCR_SSHIFT_Pos              (30U)
+#define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)       /*!< 0x40000000 */
+#define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_IR register  *******************/
+#define XSPI_IR_INSTRUCTION_Pos          (0U)
+#define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk              /*!< Instruction */
+
+/****************  Bit definition for XSPI_ABR register  *******************/
+#define XSPI_ABR_ALTERNATE_Pos           (0U)
+#define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_LPTR register  ******************/
+#define XSPI_LPTR_TIMEOUT_Pos            (0U)
+#define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
+#define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */
+
+/****************  Bit definition for XSPI_WPCCR register  *******************/
+#define XSPI_WPCCR_IMODE_Pos             (0U)
+#define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000007 */
+#define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */
+#define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000002 */
+#define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000004 */
+#define XSPI_WPCCR_IDTR_Pos              (3U)
+#define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)       /*!< 0x00000008 */
+#define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */
+#define XSPI_WPCCR_ISIZE_Pos             (4U)
+#define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000030 */
+#define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */
+#define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000010 */
+#define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000020 */
+#define XSPI_WPCCR_ADMODE_Pos            (8U)
+#define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000700 */
+#define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */
+#define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000100 */
+#define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000200 */
+#define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000400 */
+#define XSPI_WPCCR_ADDTR_Pos             (11U)
+#define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)      /*!< 0x00000800 */
+#define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */
+#define XSPI_WPCCR_ADSIZE_Pos            (12U)
+#define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00003000 */
+#define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */
+#define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00001000 */
+#define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00002000 */
+#define XSPI_WPCCR_ABMODE_Pos            (16U)
+#define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00070000 */
+#define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */
+#define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00010000 */
+#define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00020000 */
+#define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00040000 */
+#define XSPI_WPCCR_ABDTR_Pos             (19U)
+#define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)      /*!< 0x00080000 */
+#define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WPCCR_ABSIZE_Pos            (20U)
+#define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00300000 */
+#define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */
+#define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00100000 */
+#define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00200000 */
+#define XSPI_WPCCR_DMODE_Pos             (24U)
+#define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x07000000 */
+#define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */
+#define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x01000000 */
+#define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x02000000 */
+#define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x04000000 */
+#define XSPI_WPCCR_DDTR_Pos              (27U)
+#define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)       /*!< 0x08000000 */
+#define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */
+#define XSPI_WPCCR_DQSE_Pos              (29U)
+#define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)       /*!< 0x20000000 */
+#define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WPTCR register  *******************/
+#define XSPI_WPTCR_DCYC_Pos              (0U)
+#define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)      /*!< 0x0000001F */
+#define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */
+#define XSPI_WPTCR_DHQC_Pos              (28U)
+#define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)       /*!< 0x10000000 */
+#define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */
+#define XSPI_WPTCR_SSHIFT_Pos            (30U)
+#define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)     /*!< 0x40000000 */
+#define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_WPIR register  *******************/
+#define XSPI_WPIR_INSTRUCTION_Pos        (0U)
+#define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */
+
+/****************  Bit definition for XSPI_WPABR register  *******************/
+#define XSPI_WPABR_ALTERNATE_Pos         (0U)
+#define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_WCCR register  ******************/
+#define XSPI_WCCR_IMODE_Pos              (0U)
+#define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000007 */
+#define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */
+#define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000001 */
+#define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000002 */
+#define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000004 */
+#define XSPI_WCCR_IDTR_Pos               (3U)
+#define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)        /*!< 0x00000008 */
+#define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */
+#define XSPI_WCCR_ISIZE_Pos              (4U)
+#define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000030 */
+#define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */
+#define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000010 */
+#define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000020 */
+#define XSPI_WCCR_ADMODE_Pos             (8U)
+#define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000700 */
+#define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */
+#define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000100 */
+#define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000200 */
+#define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000400 */
+#define XSPI_WCCR_ADDTR_Pos              (11U)
+#define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)       /*!< 0x00000800 */
+#define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */
+#define XSPI_WCCR_ADSIZE_Pos             (12U)
+#define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00003000 */
+#define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */
+#define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00001000 */
+#define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00002000 */
+#define XSPI_WCCR_ABMODE_Pos             (16U)
+#define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00070000 */
+#define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */
+#define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00010000 */
+#define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00020000 */
+#define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00040000 */
+#define XSPI_WCCR_ABDTR_Pos              (19U)
+#define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)       /*!< 0x00080000 */
+#define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WCCR_ABSIZE_Pos             (20U)
+#define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00300000 */
+#define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */
+#define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00100000 */
+#define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00200000 */
+#define XSPI_WCCR_DMODE_Pos              (24U)
+#define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x07000000 */
+#define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                  /*!< Data Mode */
+#define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x01000000 */
+#define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x02000000 */
+#define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x04000000 */
+#define XSPI_WCCR_DDTR_Pos               (27U)
+#define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)        /*!< 0x08000000 */
+#define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */
+#define XSPI_WCCR_DQSE_Pos               (29U)
+#define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)        /*!< 0x20000000 */
+#define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WTCR register  ******************/
+#define XSPI_WTCR_DCYC_Pos               (0U)
+#define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)       /*!< 0x0000001F */
+#define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */
+
+/****************  Bit definition for XSPI_WIR register  *******************/
+#define XSPI_WIR_INSTRUCTION_Pos         (0U)
+#define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */
+
+/****************  Bit definition for XSPI_WABR register  ******************/
+#define XSPI_WABR_ALTERNATE_Pos          (0U)
+#define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_HLCR register  ******************/
+#define XSPI_HLCR_LM_Pos                 (0U)
+#define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)          /*!< 0x00000001 */
+#define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                     /*!< Latency Mode */
+#define XSPI_HLCR_WZL_Pos                (1U)
+#define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)         /*!< 0x00000002 */
+#define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */
+#define XSPI_HLCR_TACC_Pos               (8U)
+#define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)       /*!< 0x0000FF00 */
+#define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                   /*!< Access Time */
+#define XSPI_HLCR_TRWR_Pos               (16U)
+#define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)       /*!< 0x00FF0000 */
+#define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */
+
+/****************  Bit definition for XSPI_CALFCR register  ****************/
+#define XSPI_CALFCR_FINE_Pos             (0U)
+#define XSPI_CALFCR_FINE_Msk             (0x7FUL << XSPI_CALFCR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALFCR_FINE                 XSPI_CALFCR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALFCR_COARSE_Pos           (16U)
+#define XSPI_CALFCR_COARSE_Msk           (0x1FUL << XSPI_CALFCR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALFCR_COARSE               XSPI_CALFCR_COARSE_Msk               /*!< Coarse Calibration */
+#define XSPI_CALFCR_CALMAX_Pos           (31U)
+#define XSPI_CALFCR_CALMAX_Msk           (0x1UL << XSPI_CALFCR_CALMAX_Pos)    /*!< 0x80000000 */
+#define XSPI_CALFCR_CALMAX               XSPI_CALFCR_CALMAX_Msk               /*!< Max Value */
+
+/****************  Bit definition for XSPI_CALMR register  *****************/
+#define XSPI_CALMR_FINE_Pos              (0U)
+#define XSPI_CALMR_FINE_Msk              (0x7FUL << XSPI_CALMR_FINE_Pos)      /*!< 0x0000007F */
+#define XSPI_CALMR_FINE                  XSPI_CALMR_FINE_Msk                  /*!< Fine Calibration */
+#define XSPI_CALMR_COARSE_Pos            (16U)
+#define XSPI_CALMR_COARSE_Msk            (0x1FUL << XSPI_CALMR_COARSE_Pos)    /*!< 0x001F0000 */
+#define XSPI_CALMR_COARSE                XSPI_CALMR_COARSE_Msk                /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSOR register  ****************/
+#define XSPI_CALSOR_FINE_Pos             (0U)
+#define XSPI_CALSOR_FINE_Msk             (0x7FUL << XSPI_CALSOR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSOR_FINE                 XSPI_CALSOR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSOR_COARSE_Pos           (16U)
+#define XSPI_CALSOR_COARSE_Msk           (0x1FUL << XSPI_CALSOR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSOR_COARSE               XSPI_CALSOR_COARSE_Msk               /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSIR register  ****************/
+#define XSPI_CALSIR_FINE_Pos             (0U)
+#define XSPI_CALSIR_FINE_Msk             (0x7FUL << XSPI_CALSIR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSIR_FINE                 XSPI_CALSIR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSIR_COARSE_Pos           (16U)
+#define XSPI_CALSIR_COARSE_Msk           (0x1FUL << XSPI_CALSIR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSIR_COARSE               XSPI_CALSIR_COARSE_Msk               /*!< Coarse Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 XSPIM                                      */
+/*                                                                            */
+/******************************************************************************/
+/***************  Bit definition for XSPIM_CR register  ********************/
+#define XSPIM_CR_MUXEN_Pos               (0U)
+#define XSPIM_CR_MUXEN_Msk               (0x1UL << XSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */
+#define XSPIM_CR_MUXEN                   XSPIM_CR_MUXEN_Msk                   /*!< Multiplexed Mode Enable */
+#define XSPIM_CR_MODE_Pos                (1U)
+#define XSPIM_CR_MODE_Msk                (0x1UL << XSPIM_CR_MODE_Pos)         /*!< 0x00000002 */
+#define XSPIM_CR_MODE                    XSPIM_CR_MODE_Msk                    /*!< Multiplexing Mode */
+#define XSPIM_CR_CSSEL_OVR_EN_Pos        (4U)
+#define XSPIM_CR_CSSEL_OVR_EN_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_EN_Pos) /*!< 0x00000010 */
+#define XSPIM_CR_CSSEL_OVR_EN            XSPIM_CR_CSSEL_OVR_EN_Msk            /*!< Chip Select Selector Override Enable */
+#define XSPIM_CR_CSSEL_OVR_O1_Pos        (5U)
+#define XSPIM_CR_CSSEL_OVR_O1_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O1_Pos) /*!< 0x00000020 */
+#define XSPIM_CR_CSSEL_OVR_O1            XSPIM_CR_CSSEL_OVR_O1_Msk            /*!< Chip Select Selector Override Setting For XSPI1 */
+#define XSPIM_CR_CSSEL_OVR_O2_Pos        (6U)
+#define XSPIM_CR_CSSEL_OVR_O2_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O2_Pos) /*!< 0x00000040 */
+#define XSPIM_CR_CSSEL_OVR_O2            XSPIM_CR_CSSEL_OVR_O2_Msk            /*!< Chip Select Selector Override Setting For XSPI2 */
+#define XSPIM_CR_REQ2ACK_TIME_Pos        (16U)
+#define XSPIM_CR_REQ2ACK_TIME_Msk        (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
+#define XSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK Time */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Exported_macros
+  * @{
+  */
+#if defined (CPU_IN_SECURE_STATE)
+/* Instances allowed from Secure state */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_S) || ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_S) || ((INSTANCE) == ADC12_COMMON_NS))
+
+/****************************** BSEC Instances *******************************/
+#define IS_BSEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == BSEC_S)
+
+/******************************* CACHEAXI Instances ***************************/
+#define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CACHEAXI_S) || ((INSTANCE) == CACHEAXI_NS))
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_S) || ((INSTANCE) == CRC_NS))
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMI_S) || ((INSTANCE) == DCMI_NS))
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMIPP_S) || ((INSTANCE) == DCMIPP_NS))
+
+/********************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_S) || ((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_S) || ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S)  || ((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_S)  || ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_S)  || ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_S)  || ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA2D_S) || ((INSTANCE) == DMA2D_NS))
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DTS_S) || ((INSTANCE) == DTS_NS))
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ETH1_S) || ((INSTANCE) == ETH1_NS))
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_S) || ((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_S) || ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_S) || ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN_CONFIG_S) || ((INSTANCE) == FDCAN_CONFIG_NS))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_S)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_S) || ((INSTANCE) == GFXMMU_NS))
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXTIM_S) || ((INSTANCE) == GFXTIM_NS))
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_S) || ((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_S) || ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_S) || ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_S) || ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_S) || ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_S) || ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_S) || ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_S) || ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_S) || ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_S) || ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_S) || ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_S) || ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPU2D_BASE_S) || ((INSTANCE) == GPU2D_BASE_NS))
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_S) || ((INSTANCE) == I3C1_NS) || \
+                                       ((INSTANCE) == I3C2_S) || ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_S) || ((INSTANCE) == IWDG_NS))
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == JPEG_S) || ((INSTANCE) == JPEG_NS))
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LTDC_S) || ((INSTANCE) == LTDC_NS))
+
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_S) || ((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_S) || ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_S) || ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_S) || ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_S) || ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_S) || ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_S) || ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDIOS_S) || ((INSTANCE) == MDIOS_NS))
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_S) || ((INSTANCE) == PKA_NS))
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PSSI_S) || ((INSTANCE) == PSSI_NS))
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM1_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM2_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM1_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_S)    || ((INSTANCE) == RAMCFG_BKPSRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)    || ((INSTANCE) == RAMCFG_FLEXRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_S)   || ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_S)  || ((INSTANCE) == RAMCFG_BKPSRAM_NS)  || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)  || ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_S) || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_S) || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_S) || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_S) || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_S) || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_S) || ((INSTANCE) == RNG_NS))
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_S) || ((INSTANCE) == RTC_NS))
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_S) || ((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_S) || ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_S) || ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_S) || ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_S) || ((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_S) || ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPDIFRX_S) || ((INSTANCE) == SPDIFRX_NS))
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_S) || ((INSTANCE) == UCPD1_NS))
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_S) || ((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_S) || ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                        ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS) || \
+                                         ((INSTANCE) == TIM18_S)  || ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                               ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                               ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                               ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                          ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                          ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                          ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                          ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                          ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                          ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                          ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                          ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     (((INSTANCE) == TIM15_S)   &&                               \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)                  \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                      ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                      ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                      ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                      ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                      ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_S)  || ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_S)  || ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_S) || ((INSTANCE) == WWDG_NS))
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_S) || ((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_S) || ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_S) || ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPIM_S) || ((INSTANCE) == XSPIM_NS))
+
+#else
+/* Instances allowed from Non-Secure state - only alias Non-Secure */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)
+
+/******************************* CACHEAXI Instances ***************************/
+#define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CACHEAXI_NS)
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS)
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI_NS)
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP_NS)
+
+/******************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_NS) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_NS) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D_NS)
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS_NS)
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH1_NS)
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_NS)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU_NS)
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXTIM_NS)
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPU2D_BASE_NS)
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
+                                      ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS)
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == JPEG_NS)
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC_NS)
+
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS_NS)
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI_NS)
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS)
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS)
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX_NS)
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_NS)
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                        ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || \
+                                               ((INSTANCE) == TIM3_NS)  || \
+                                               ((INSTANCE) == TIM4_NS)  || \
+                                               ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || \
+                                          ((INSTANCE) == TIM2_NS)   || \
+                                          ((INSTANCE) == TIM3_NS)   || \
+                                          ((INSTANCE) == TIM4_NS)   || \
+                                          ((INSTANCE) == TIM5_NS)   || \
+                                          ((INSTANCE) == TIM8_NS)   || \
+                                          ((INSTANCE) == TIM15_NS)  || \
+                                          ((INSTANCE) == TIM16_NS)  || \
+                                          ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM9_NS)   &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM10_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM11_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM12_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM13_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM14_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM8_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM15_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM16_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM17_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                      ((INSTANCE) == TIM2_NS)  || \
+                                                      ((INSTANCE) == TIM3_NS)  || \
+                                                      ((INSTANCE) == TIM4_NS)  || \
+                                                      ((INSTANCE) == TIM5_NS)  || \
+                                                      ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS)
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == XSPIM_NS)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Exported_macros */
+
+/** @} */ /* End of group STM32N647xx */
+
+/** @} */ /* End of group ST */
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* STM32N647xx_H */
diff --git a/stm32cube/stm32n6xx/soc/stm32n655xx.h b/stm32cube/stm32n6xx/soc/stm32n655xx.h
new file mode 100644
index 000000000..da553a119
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/stm32n655xx.h
@@ -0,0 +1,42697 @@
+/**
+  ******************************************************************************
+  * @file    stm32n655xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N655xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+#ifndef STM32N655xx_H
+#define STM32N655xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup ST
+  * @{
+  */
+
+/** @addtogroup STM32N655xx
+  * @{
+  */
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+typedef enum
+{
+/* ======================================  ARM Cortex-M55 Specific Interrupt Numbers  ======================================== */
+  NonMaskableInt_IRQn        = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted                         */
+  HardFault_IRQn             = -13,    /*!< -13 Hard Fault, all classes of Fault                                               */
+  MemoryManagement_IRQn      = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match       */
+  BusFault_IRQn              = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn            = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition                  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  SecureFault_IRQn           = -9,     /*!< -9  Secure Fault                                                                   */
+#endif
+  SVCall_IRQn                = -5,     /*!< -5  System Service Call via SVC instruction                                        */
+  DebugMonitor_IRQn          = -4,     /*!< -4  Debug Monitor                                                                  */
+  PendSV_IRQn                = -2,     /*!< -2  Pendable request for system service                                            */
+  SysTick_IRQn               = -1,     /*!< -1  System Tick Timer                                                              */
+
+/* ======================================  STM32N6xx Specific Interrupt Numbers  ============================================= */
+  PVD_PVM_IRQn               = 0,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection                                */
+  DTS_IRQn                   = 2,      /*!< Thermal Sensor interruption                                                        */
+  RCC_IRQn                   = 3,      /*!< RCC non-secure global interrupts through EXTI Line detection                       */
+  LOCKUP_IRQn                = 4,      /*!< LOCKUP / (no Overstack in CM55)                                                    */
+  CACHE_ECC_IRQn             = 5,      /*!< Error ECC cache interrupt                                                          */
+  TCM_ECC_IRQn               = 6,      /*!< TCM ECC interrupts                                                                 */
+  BKP_ECC_IRQn               = 7,      /*!< Backup RAM Interrupts                                                              */
+  FPU_IRQn                   = 8,      /*!< FPU interrupt                                                                      */
+  RTC_S_IRQn                 = 10,     /*!< RTC secure interrupts through EXTI Line detection                                  */
+  TAMP_IRQn                  = 11,     /*!< Tamper secure and non-secure interrupts through EXTI Line detection                */
+  RIFSC_TAMPER_IRQn          = 12,     /*!< RIF Tamper interrupts                                                              */
+  IAC_IRQn                   = 13,     /*!< IAC interrupt                                                                      */
+  RCC_S_IRQn                 = 14,     /*!< RCC secure global interrupts through EXTI Line detection                           */
+  RTC_IRQn                   = 16,     /*!< RTC non-secure interrupts through EXTI Line detection                              */
+  IWDG_IRQn                  = 18,     /*!< Internal Watchdog interrupt                                                        */
+  WWDG_IRQn                  = 19,     /*!< Window Watchdog interrupt                                                          */
+  EXTI0_IRQn                 = 20,     /*!< EXTI Line0 interrupt                                                               */
+  EXTI1_IRQn                 = 21,     /*!< EXTI Line1 interrupt                                                               */
+  EXTI2_IRQn                 = 22,     /*!< EXTI Line2 interrupt                                                               */
+  EXTI3_IRQn                 = 23,     /*!< EXTI Line3 interrupt                                                               */
+  EXTI4_IRQn                 = 24,     /*!< EXTI Line4 interrupt                                                               */
+  EXTI5_IRQn                 = 25,     /*!< EXTI Line5 interrupt                                                               */
+  EXTI6_IRQn                 = 26,     /*!< EXTI Line6 interrupt                                                               */
+  EXTI7_IRQn                 = 27,     /*!< EXTI Line7 interrupt                                                               */
+  EXTI8_IRQn                 = 28,     /*!< EXTI Line8 interrupt                                                               */
+  EXTI9_IRQn                 = 29,     /*!< EXTI Line9 interrupt                                                               */
+  EXTI10_IRQn                = 30,     /*!< EXTI Line10 interrupt                                                              */
+  EXTI11_IRQn                = 31,     /*!< EXTI Line11 interrupt                                                              */
+  EXTI12_IRQn                = 32,     /*!< EXTI Line12 interrupt                                                              */
+  EXTI13_IRQn                = 33,     /*!< EXTI Line13 interrupt                                                              */
+  EXTI14_IRQn                = 34,     /*!< EXTI Line14 interrupt                                                              */
+  EXTI15_IRQn                = 35,     /*!< EXTI Line15 interrupt                                                              */
+  SAES_IRQn                  = 36,     /*!< SAES interrupt                                                                     */
+  CRYP_IRQn                  = 37,     /*!< CRYP interrupt                                                                     */
+  PKA_IRQn                   = 38,     /*!< PKA interrupt                                                                      */
+  HASH_IRQn                  = 39,     /*!< HASH interrupt                                                                     */
+  RNG_IRQn                   = 40,     /*!< RNG global interrupt                                                               */
+  MCE1_IRQn                  = 42,     /*!< MCE1 global interrupt                                                              */
+  MCE2_IRQn                  = 43,     /*!< MCE2 global interrupt                                                              */
+  MCE3_IRQn                  = 44,     /*!< MCE3 global interrupt                                                              */
+  MCE4_IRQn                  = 45,     /*!< MCE4 global interrupt                                                              */
+  ADC1_2_IRQn                = 46,     /*!< ADC1 & ADC2 interrupt                                                              */
+  CSI_IRQn                   = 47,     /*!< CSI global interrupt                                                               */
+  DCMIPP_IRQn                = 48,     /*!< DCMIPP global interrupt                                                            */
+  PAHB_ERR_IRQn              = 52,     /*!< PAHB error interrupt                                                               */
+  LTDC_LO_IRQn               = 58,     /*!< LTDC low-layer global interrupt                                                    */
+  LTDC_LO_ERR_IRQn           = 59,     /*!< LTDC low-layer error interrupt                                                     */
+  DMA2D_IRQn                 = 60,     /*!< DMA2D global interrupt                                                             */
+  JPEG_IRQn                  = 61,     /*!< JPEG global interrupt                                                              */
+  VENC_IRQn                  = 62,     /*!< VENC global interrupt                                                              */
+  GFXMMU_IRQn                = 63,     /*!< GFXMMU global interrupt                                                            */
+  GFXTIM_IRQn                = 64,     /*!< GFXTIM global interrupt                                                            */
+  GPU2D_IRQn                 = 65,     /*!< GPU2D interrupt                                                                    */
+  GPU2D_ER_IRQn              = 66,     /*!< GPU2D error interrupt                                                              */
+  ICACHE_IRQn                = 67,     /*!< GPU2D cache interrupt                                                              */
+  HPDMA1_Channel0_IRQn       = 68,     /*!< HPDMA1 Channel 0 global interrupt                                                  */
+  HPDMA1_Channel1_IRQn       = 69,     /*!< HPDMA1 Channel 1 global interrupt                                                  */
+  HPDMA1_Channel2_IRQn       = 70,     /*!< HPDMA1 Channel 2 global interrupt                                                  */
+  HPDMA1_Channel3_IRQn       = 71,     /*!< HPDMA1 Channel 3 global interrupt                                                  */
+  HPDMA1_Channel4_IRQn       = 72,     /*!< HPDMA1 Channel 4 global interrupt                                                  */
+  HPDMA1_Channel5_IRQn       = 73,     /*!< HPDMA1 Channel 5 global interrupt                                                  */
+  HPDMA1_Channel6_IRQn       = 74,     /*!< HPDMA1 Channel 6 global interrupt                                                  */
+  HPDMA1_Channel7_IRQn       = 75,     /*!< HPDMA1 Channel 7 global interrupt                                                  */
+  HPDMA1_Channel8_IRQn       = 76,     /*!< HPDMA1 Channel 8 global interrupt                                                  */
+  HPDMA1_Channel9_IRQn       = 77,     /*!< HPDMA1 Channel 9 global interrupt                                                  */
+  HPDMA1_Channel10_IRQn      = 78,     /*!< HPDMA1 Channel 10 global interrupt                                                 */
+  HPDMA1_Channel11_IRQn      = 79,     /*!< HPDMA1 Channel 11 global interrupt                                                 */
+  HPDMA1_Channel12_IRQn      = 80,     /*!< HPDMA1 Channel 12 global interrupt                                                 */
+  HPDMA1_Channel13_IRQn      = 81,     /*!< HPDMA1 Channel 13 global interrupt                                                 */
+  HPDMA1_Channel14_IRQn      = 82,     /*!< HPDMA1 Channel 14 global interrupt                                                 */
+  HPDMA1_Channel15_IRQn      = 83,     /*!< HPDMA1 Channel 15 global interrupt                                                 */
+  GPDMA1_Channel0_IRQn       = 84,     /*!< GPDMA1 Channel 0 interrupt                                                         */
+  GPDMA1_Channel1_IRQn       = 85,     /*!< GPDMA1 Channel 1 interrupt                                                         */
+  GPDMA1_Channel2_IRQn       = 86,     /*!< GPDMA1 Channel 2 interrupt                                                         */
+  GPDMA1_Channel3_IRQn       = 87,     /*!< GPDMA1 Channel 3 interrupt                                                         */
+  GPDMA1_Channel4_IRQn       = 88,     /*!< GPDMA1 Channel 4 interrupt                                                         */
+  GPDMA1_Channel5_IRQn       = 89,     /*!< GPDMA1 Channel 5 interrupt                                                         */
+  GPDMA1_Channel6_IRQn       = 90,     /*!< GPDMA1 Channel 6 interrupt                                                         */
+  GPDMA1_Channel7_IRQn       = 91,     /*!< GPDMA1 Channel 7 interrupt                                                         */
+  GPDMA1_Channel8_IRQn       = 92,     /*!< GPDMA1 Channel 8 interrupt                                                         */
+  GPDMA1_Channel9_IRQn       = 93,     /*!< GPDMA1 Channel 9 interrupt                                                         */
+  GPDMA1_Channel10_IRQn      = 94,     /*!< GPDMA1 Channel 10 interrupt                                                        */
+  GPDMA1_Channel11_IRQn      = 95,     /*!< GPDMA1 Channel 11 interrupt                                                        */
+  GPDMA1_Channel12_IRQn      = 96,     /*!< GPDMA1 Channel 12 interrupt                                                        */
+  GPDMA1_Channel13_IRQn      = 97,     /*!< GPDMA1 Channel 13 interrupt                                                        */
+  GPDMA1_Channel14_IRQn      = 98,     /*!< GPDMA1 Channel 14 interrupt                                                        */
+  GPDMA1_Channel15_IRQn      = 99,     /*!< GPDMA1 Channel 15 interrupt                                                        */
+  I2C1_EV_IRQn               = 100,    /*!< I2C1 event interrupt                                                               */
+  I2C1_ER_IRQn               = 101,    /*!< I2C1 error interrupt                                                               */
+  I2C2_EV_IRQn               = 102,    /*!< I2C2 event interrupt                                                               */
+  I2C2_ER_IRQn               = 103,    /*!< I2C2 error interrupt                                                               */
+  I2C3_EV_IRQn               = 104,    /*!< I2C3 event interrupt                                                               */
+  I2C3_ER_IRQn               = 105,    /*!< I2C3 error interrupt                                                               */
+  I2C4_EV_IRQn               = 106,    /*!< I2C4 event interrupt                                                               */
+  I2C4_ER_IRQn               = 107,    /*!< I2C4 error interrupt                                                               */
+  I3C1_EV_IRQn               = 108,    /*!< I3C1 event interrupt                                                               */
+  I3C1_ER_IRQn               = 109,    /*!< I3C1 error interrupt                                                               */
+  I3C2_EV_IRQn               = 110,    /*!< I3C2 event interrupt                                                               */
+  I3C2_ER_IRQn               = 111,    /*!< I3C2 error interrupt                                                               */
+  TIM1_BRK_IRQn              = 112,    /*!< TIM1 Break interrupt                                                               */
+  TIM1_UP_IRQn               = 113,    /*!< TIM1 Update interrupt                                                              */
+  TIM1_TRG_COM_IRQn          = 114,    /*!< TIM1 Trigger and Commutation interrupt                                             */
+  TIM1_CC_IRQn               = 115,    /*!< TIM1 Capture Compare interrupt                                                     */
+  TIM2_IRQn                  = 116,    /*!< TIM2 global interrupt                                                              */
+  TIM3_IRQn                  = 117,    /*!< TIM3 global interrupt                                                              */
+  TIM4_IRQn                  = 118,    /*!< TIM4 global interrupt                                                              */
+  TIM5_IRQn                  = 119,    /*!< TIM5 global interrupt                                                              */
+  TIM6_IRQn                  = 120,    /*!< TIM6 global interrupt                                                              */
+  TIM7_IRQn                  = 121,    /*!< TIM7 global interrupt                                                              */
+  TIM8_BRK_IRQn              = 122,    /*!< TIM8 Break interrupt                                                               */
+  TIM8_UP_IRQn               = 123,    /*!< TIM8 Update interrupt                                                              */
+  TIM8_TRG_COM_IRQn          = 124,    /*!< TIM8 Trigger and Commutation interrupt                                             */
+  TIM8_CC_IRQn               = 125,    /*!< TIM8 Capture Compare interrupt                                                     */
+  TIM9_IRQn                  = 126,    /*!< TIM9 global interrupt                                                              */
+  TIM10_IRQn                 = 127,    /*!< TIM10 global interrupt                                                             */
+  TIM11_IRQn                 = 128,    /*!< TIM11 global interrupt                                                             */
+  TIM12_IRQn                 = 129,    /*!< TIM12 global interrupt                                                             */
+  TIM13_IRQn                 = 130,    /*!< TIM13 global interrupt                                                             */
+  TIM14_IRQn                 = 131,    /*!< TIM14 global interrupt                                                             */
+  TIM15_IRQn                 = 132,    /*!< TIM15 global interrupt                                                             */
+  TIM16_IRQn                 = 133,    /*!< TIM16 global interrupt                                                             */
+  TIM17_IRQn                 = 134,    /*!< TIM17 global interrupt                                                             */
+  TIM18_IRQn                 = 135,    /*!< TIM18 global interrupt                                                             */
+  LPTIM1_IRQn                = 136,    /*!< LPTIM1 global interrupt                                                            */
+  LPTIM2_IRQn                = 137,    /*!< LPTIM2 global interrupt                                                            */
+  LPTIM3_IRQn                = 138,    /*!< LPTIM3 global interrupt                                                            */
+  LPTIM4_IRQn                = 139,    /*!< LPTIM4 global interrupt                                                            */
+  LPTIM5_IRQn                = 140,    /*!< LPTIM5 global interrupt                                                            */
+  ADF1_FLT0_IRQn             = 141,    /*!< ADF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT0_IRQn             = 142,    /*!< MDF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT1_IRQn             = 143,    /*!< MDF1 Filter 1 global interrupt                                                     */
+  MDF1_FLT2_IRQn             = 144,    /*!< MDF1 Filter 2 global interrupt                                                     */
+  MDF1_FLT3_IRQn             = 145,    /*!< MDF1 Filter 3 global interrupt                                                     */
+  MDF1_FLT4_IRQn             = 146,    /*!< MDF1 Filter 4 global interrupt                                                     */
+  MDF1_FLT5_IRQn             = 147,    /*!< MDF1 Filter 5 global interrupt                                                     */
+  SAI1_A_IRQn                = 148,    /*!< Serial Audio Interface 1 block A interrupt                                         */
+  SAI1_B_IRQn                = 149,    /*!< Serial Audio Interface 1 block B interrupt                                         */
+  SAI2_A_IRQn                = 150,    /*!< Serial Audio Interface 2 block A interrupt                                         */
+  SAI2_B_IRQn                = 151,    /*!< Serial Audio Interface 2 block B interrupt                                         */
+  SPDIFRX1_IRQn              = 152,    /*!< SPDIFRX1 interrupt                                                                 */
+  SPI1_IRQn                  = 153,    /*!< SPI1 global interrupt                                                              */
+  SPI2_IRQn                  = 154,    /*!< SPI2 global interrupt                                                              */
+  SPI3_IRQn                  = 155,    /*!< SPI3 global interrupt                                                              */
+  SPI4_IRQn                  = 156,    /*!< SPI4 global interrupt                                                              */
+  SPI5_IRQn                  = 157,    /*!< SPI5 global interrupt                                                              */
+  SPI6_IRQn                  = 158,    /*!< SPI6 global interrupt                                                              */
+  USART1_IRQn                = 159,    /*!< USART1 global interrupt                                                            */
+  USART2_IRQn                = 160,    /*!< USART2 global interrupt                                                            */
+  USART3_IRQn                = 161,    /*!< USART3 global interrupt                                                            */
+  UART4_IRQn                 = 162,    /*!< UART4 global interrupt                                                             */
+  UART5_IRQn                 = 163,    /*!< UART5 global interrupt                                                             */
+  USART6_IRQn                = 164,    /*!< USART3 global interrupt                                                            */
+  UART7_IRQn                 = 165,    /*!< UART7 global interrupt                                                             */
+  UART8_IRQn                 = 166,    /*!< UART8 global interrupt                                                             */
+  UART9_IRQn                 = 167,    /*!< UART9 global interrupt                                                             */
+  USART10_IRQn               = 168,    /*!< USART10 global interrupt                                                           */
+  LPUART1_IRQn               = 169,    /*!< LPUART1 global interrupt                                                           */
+  XSPI1_IRQn                 = 170,    /*!< XSPI1 global interrupt                                                             */
+  XSPI2_IRQn                 = 171,    /*!< XSPI2 global interrupt                                                             */
+  XSPI3_IRQn                 = 172,    /*!< XSPI3 global interrupt                                                             */
+  FMC_IRQn                   = 173,    /*!< FMC global interrupt                                                               */
+  SDMMC1_IRQn                = 174,    /*!< SDMMC1 global interrupt                                                            */
+  SDMMC2_IRQn                = 175,    /*!< SDMMC2 global interrupt                                                            */
+  UCPD1_IRQn                 = 176,    /*!< UCPD1 global interrupt                                                             */
+  USB1_OTG_HS_IRQn           = 177,    /*!< USB1 OTG HS interrupt                                                              */
+  USB2_OTG_HS_IRQn           = 178,    /*!< USB2 OTG HS interrupt                                                              */
+  ETH1_IRQn                  = 179,    /*!< ETH1 global interrupt                                                              */
+  FDCAN1_IT0_IRQn            = 180,    /*!< FDCAN1 interrupt 0                                                                 */
+  FDCAN1_IT1_IRQn            = 181,    /*!< FDCAN1 interrupt 1                                                                 */
+  FDCAN2_IT0_IRQn            = 182,    /*!< FDCAN2 interrupt 0                                                                 */
+  FDCAN2_IT1_IRQn            = 183,    /*!< FDCAN2 interrupt 1                                                                 */
+  FDCAN3_IT0_IRQn            = 184,    /*!< FDCAN3 interrupt 0                                                                 */
+  FDCAN3_IT1_IRQn            = 185,    /*!< FDCAN3 interrupt 1                                                                 */
+  FDCAN_CU_IRQn              = 186,    /*!< FDCAN Clock Unit interrupt                                                         */
+  MDIOS_IRQn                 = 187,    /*!< MDIOS global interrupt                                                             */
+  DCMI_PSSI_IRQn             = 188,    /*!< DCMI/PSSI global interrupt                                                         */
+  WAKEUP_PIN_IRQn            = 189,    /*!< Wake-up pins interrupt                                                             */
+  CTI_INT0_IRQn              = 190,    /*!< CTI INT0 interrupt                                                                 */
+  CTI_INT1_IRQn              = 191,    /*!< CTI INT1 interrupt                                                                 */
+  LTDC_UP_IRQn               = 193,    /*!< LTDC up-layer global interrupt                                                     */
+  LTDC_UP_ERR_IRQn           = 194,    /*!< LTDC up-layer error interrupt                                                      */
+} IRQn_Type;
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/**
+  * @brief Configuration of the Cortex-M55 Processor and Core Peripherals
+   */
+#define __CM55_REV                0x0101U /*!< Cortex-M55 revision r1p1                      */
+#define __FPU_PRESENT             1U      /*!< CM55 Floating Point Unit present              */
+#define __DSP_PRESENT             1U      /*!< CM55 Digital Signal Processing Unit present   */
+#define __MPU_PRESENT             1U      /*!< CM55 Memory Programming Unit present          */
+#define __ICACHE_PRESENT          1U      /*!< CM55 Instruction cache present                */
+#define __DCACHE_PRESENT          1U      /*!< CM55 Data cache present                       */
+#define __VTOR_PRESENT            1U      /*!< CM55 Vector table offset register present     */
+#define __PMU_PRESENT             1U      /*!< CM55 Performance Monitoring Unit present      */
+#define __PMU_NUM_EVENTCNT        8U      /*!< CM55 can monitor up to 8 PMU events           */
+#define __NVIC_PRIO_BITS          4U      /*!< CM55 uses 4 bits for the Priority Levels      */
+#define __Vendor_SysTickConfig    0U      /*!< Set to 1 if different SysTick Config is used  */
+#define __SAUREGION_PRESENT       1U      /*!< SAU regions present                           */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define CPU_IN_SECURE_STATE
+#endif
+
+#define CPU_AS_TRUSTED_DOMAIN
+
+#include "core_cm55.h"                    /*!< ARM Cortex-M55 processor and core peripherals */
+#include "system_stm32n6xx.h"             /*!< STM32N6xx System */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup STM32N6xx_peripherals
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter (ADC)
+  */
+typedef struct
+{
+  __IO uint32_t ISR;           /*!< ADC interrupt and status register,                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< ADC interrupt enable register,                         Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< ADC control register,                                  Address offset: 0x08 */
+  __IO uint32_t CFGR1;         /*!< ADC configuration register 1,                          Address offset: 0x0C */
+  __IO uint32_t CFGR2;         /*!< ADC configuration register 2,                          Address offset: 0x10 */
+  __IO uint32_t SMPR1;         /*!< ADC sample time register 1,                            Address offset: 0x14 */
+  __IO uint32_t SMPR2;         /*!< ADC sample time register 2,                            Address offset: 0x18 */
+  __IO uint32_t PCSEL;         /*!< ADC channel preselection register,                     Address offset: 0x1C */
+  uint32_t      RESERVED1[4];  /*!< Reserved,                                              Address offset: 0x020-0x02C */
+  __IO uint32_t SQR1;          /*!< ADC regular sequence register 1,                       Address offset: 0x30 */
+  __IO uint32_t SQR2;          /*!< ADC regular sequence register 2,                       Address offset: 0x34 */
+  __IO uint32_t SQR3;          /*!< ADC regular sequence register 3,                       Address offset: 0x38 */
+  __IO uint32_t SQR4;          /*!< ADC regular sequence register 4,                       Address offset: 0x3C */
+  __IO uint32_t DR;            /*!< ADC regular data register,                             Address offset: 0x40 */
+  uint32_t      RESERVED2[2];  /*!< Reserved,                                              Address offset: 0x044-0x048 */
+  __IO uint32_t JSQR;          /*!< ADC injected sequence register,                        Address offset: 0x4C */
+  __IO uint32_t OFCFGR1;       /*!< ADC offset configuration register 1,                   Address offset: 0x50 */
+  __IO uint32_t OFCFGR2;       /*!< ADC offset configuration register 2,                   Address offset: 0x54 */
+  __IO uint32_t OFCFGR3;       /*!< ADC offset configuration register 3,                   Address offset: 0x58 */
+  __IO uint32_t OFCFGR4;       /*!< ADC offset configuration register 4,                   Address offset: 0x5C */
+  __IO uint32_t OFR1;          /*!< ADC offset register 1,                                 Address offset: 0x60 */
+  __IO uint32_t OFR2;          /*!< ADC offset register 2,                                 Address offset: 0x64 */
+  __IO uint32_t OFR3;          /*!< ADC offset register 3,                                 Address offset: 0x68 */
+  __IO uint32_t OFR4;          /*!< ADC offset register 4,                                 Address offset: 0x6C */
+  __IO uint32_t GCOMP;         /*!< ADC gain compensation register,                        Address offset: 0x70 */
+  uint32_t      RESERVED3[3];  /*!< Reserved,                                              Address offset: 0x074-0x07C */
+  __IO uint32_t JDR1;          /*!< ADC injected data register 1,                          Address offset: 0x80 */
+  __IO uint32_t JDR2;          /*!< ADC injected data register 2,                          Address offset: 0x84 */
+  __IO uint32_t JDR3;          /*!< ADC injected data register 3,                          Address offset: 0x88 */
+  __IO uint32_t JDR4;          /*!< ADC injected data register 4,                          Address offset: 0x8C */
+  uint32_t      RESERVED4[4];  /*!< Reserved,                                              Address offset: 0x090-0x09C */
+  __IO uint32_t AWD2CR;        /*!< ADC analog watchdog 2 configuration register,          Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;        /*!< ADC analog watchdog 3 configuration register,          Address offset: 0xA4 */
+  __IO uint32_t AWD1LTR;       /*!< ADC analog watchdog 1 low threshold register,          Address offset: 0xA8 */
+  __IO uint32_t AWD1HTR;       /*!< ADC analog watchdog 1 high threshold register,         Address offset: 0xAC */
+  __IO uint32_t AWD2LTR;       /*!< ADC analog watchdog 2 low threshold register,          Address offset: 0xB0 */
+  __IO uint32_t AWD2HTR;       /*!< ADC analog watchdog 2 high threshold register,         Address offset: 0xB4 */
+  __IO uint32_t AWD3LTR;       /*!< ADC analog watchdog 3 low threshold register,          Address offset: 0xB8 */
+  __IO uint32_t AWD3HTR;       /*!< ADC analog watchdog 3 high threshold register,         Address offset: 0xBC */
+  __IO uint32_t DIFSEL;        /*!< ADC differential mode selection register,              Address offset: 0xC0 */
+  __IO uint32_t CALFACT;       /*!< ADC calibration factors,                               Address offset: 0xC4 */
+  uint32_t      RESERVED5[2];  /*!< Reserved,                                              Address offset: 0x0C8-0x0CC */
+  __IO uint32_t OR;            /*!< ADC option register,                                   Address offset: 0xD0 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;           /*!< ADC common status register,                            Address offset: 0x300 */
+  uint32_t RESERVED;           /*!< Reserved,                                              Address offset: 0x304 */
+  __IO uint32_t CCR;           /*!< ADC common control register,                           Address offset: 0x308 */
+  __IO uint32_t CDR;           /*!< ADC common regular data register for dual mode,        Address offset: 0x30C */
+  __IO uint32_t CDR2;          /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Boot and Security
+  */
+
+typedef struct
+{
+  __IO uint32_t FVRw[384];       /*!< BSEC fuse word (0-383) value register,       Address offset: 0x000-0x5FC */
+       uint32_t RESERVED0[128];  /*!< Reserved,                                    Address offset: 0x600-0x7FC */
+  __IO uint32_t SPLOCKx[12];     /*!< BSEC sticky program lock register (0-11),    Address offset: 0x800-0x82C */
+       uint32_t RESERVED1[4];    /*!< Reserved,                                    Address offset: 0x830-0x83C */
+  __IO uint32_t SWLOCKx[12];     /*!< BSEC sticky write lock register (0-11),      Address offset: 0x840-0x86C */
+       uint32_t RESERVED2[4];    /*!< Reserved,                                    Address offset: 0x870-0x87C */
+  __IO uint32_t SRLOCKx[12];     /*!< BSEC sticky reload lock register (0-11),     Address offset: 0x880-0x8AC */
+       uint32_t RESERVED3[4];    /*!< Reserved,                                    Address offset: 0x8B0-0x8BC */
+  __IO uint32_t OTPVLDRx[12];    /*!< BSEC OTP valid register (0-11),              Address offset: 0x8C0-0x8EC */
+       uint32_t RESERVED4[20];   /*!< Reserved,                                    Address offset: 0x8F0-0x93C */
+  __IO uint32_t SFSRx[12];       /*!< BSEC shadowed fuses status register (0-11),  Address offset: 0x940-0x96C */
+       uint32_t RESERVED5[165];  /*!< Reserved,                                    Address offset: 0x970-0xC00 */
+  __IO uint32_t OTPCR;           /*!< BSEC OTP control register,                   Address offset: 0xC04 */
+  __IO uint32_t WDR;             /*!< BSEC write data register,                    Address offset: 0xC08 */
+       uint32_t RESERVED6[125];  /*!< Reserved,                                    Address offset: 0xC0C-0xDFC */
+  __IO uint32_t SCRATCHRx[4];    /*!< BSEC scratch register (0-3),                 Address offset: 0xE00-0xE0C */
+  __IO uint32_t LOCKR;           /*!< BSEC lock register,                          Address offset: 0xE10 */
+  __IO uint32_t JTAGINR;         /*!< BSEC JTAG input register,                    Address offset: 0xE14 */
+  __IO uint32_t JTAGOUTR;        /*!< BSEC JTAG output register,                   Address offset: 0xE18 */
+       uint32_t RESERVED7[2];    /*!< Reserved,                                    Address offset: 0xE1C-0xE20 */
+  __IO uint32_t UNMAPR;          /*!< BSEC unmap register,                         Address offset: 0xE24 */
+       uint32_t RESERVED8[6];    /*!< Reserved,                                    Address offset: 0xE28-0xE3C */
+  __IO uint32_t SR;              /*!< BSEC status register,                        Address offset: 0xE40 */
+  __IO uint32_t OTPSR;           /*!< BSEC OTP status register,                    Address offset: 0xE44 */
+       uint32_t RESERVED9[14];   /*!< Reserved,                                    Address offset: 0xE48-0xE7C */
+  __IO uint32_t EPOCHRx[2];      /*!< BSEC epoch register (0-1),                   Address offset: 0xE80-0xE84 */
+  __IO uint32_t EPOCHSELR;       /*!< BSEC epoch select register,                  Address offset: 0xE88 */
+  __IO uint32_t DBGCR;           /*!< BSEC debug control register,                 Address offset: 0xE8C */
+  __IO uint32_t AP_UNLOCK;       /*!< BSEC AP unlock,                              Address offset: 0xE90 */
+  __IO uint32_t HDPLSR;          /*!< BSEC hide protection level status register,  Address offset: 0xE94 */
+  __IO uint32_t HDPLCR;          /*!< BSEC hide protection level control register, Address offset: 0xE98 */
+  __IO uint32_t NEXTLR;          /*!< BSEC next hide protection level register,    Address offset: 0xE9C */
+       uint32_t RESERVED10[40];  /*!< Reserved,                                    Address offset: 0xEA0-0xF3C */
+  __IO uint32_t WOSCRx[8];       /*!< BSEC write once scratch register (0-7),      Address offset: 0xF40-0xF5C */
+       uint32_t RESERVED11[34];  /*!< Reserved,                                    Address offset: 0xF60-0xFE4 */
+  __IO uint32_t HRCR;            /*!< BSEC hot reset count register,               Address offset: 0xFE8 */
+  __IO uint32_t WRCR;            /*!< BSEC warm reset count register,              Address offset: 0xFEC */
+} BSEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+typedef struct
+{
+  __IO uint32_t DR;            /*!< CRC Data register,                              Address offset: 0x00 */
+  __IO uint32_t IDR;           /*!< CRC Independent data register,                  Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< CRC Control register,                           Address offset: 0x08 */
+       uint32_t RESERVED1;     /*!< Reserved,                                                       0x0C */
+  __IO uint32_t INIT;          /*!< Initial CRC value register,                     Address offset: 0x10 */
+  __IO uint32_t POL;           /*!< CRC polynomial register,                        Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Cryp Processor
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
+  __IO uint32_t DIN;        /*!< CRYP data input register,                                 Address offset: 0x08 */
+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/*
+ * @brief  (CSI)
+ */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< CSI-2 Host control register                           Address offset: 0x0000 */
+  __IO uint32_t PCR;              /*!< CSI-2 Host DPHY_RX control register                   Address offset: 0x0004 */
+       uint32_t RESERVED0[2];     /*!< Reserved                                              Address offset: 0x0008-0x000C */
+  __IO uint32_t VC0CFGR1;         /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */
+  __IO uint32_t VC0CFGR2;         /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */
+  __IO uint32_t VC0CFGR3;         /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */
+  __IO uint32_t VC0CFGR4;         /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */
+  __IO uint32_t VC1CFGR1;         /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */
+  __IO uint32_t VC1CFGR2;         /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */
+  __IO uint32_t VC1CFGR3;         /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */
+  __IO uint32_t VC1CFGR4;         /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */
+  __IO uint32_t VC2CFGR1;         /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */
+  __IO uint32_t VC2CFGR2;         /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */
+  __IO uint32_t VC2CFGR3;         /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */
+  __IO uint32_t VC2CFGR4;         /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */
+  __IO uint32_t VC3CFGR1;         /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */
+  __IO uint32_t VC3CFGR2;         /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */
+  __IO uint32_t VC3CFGR3;         /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */
+  __IO uint32_t VC3CFGR4;         /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */
+  __IO uint32_t LB0CFGR;          /*!< CSI-2 Host line byte 0 configuration register         Address offset: 0x0050 */
+  __IO uint32_t LB1CFGR;          /*!< CSI-2 Host line byte 1 configuration register         Address offset: 0x0054 */
+  __IO uint32_t LB2CFGR;          /*!< CSI-2 Host line byte 2 configuration register         Address offset: 0x0058 */
+  __IO uint32_t LB3CFGR;          /*!< CSI-2 Host line byte 3 configuration register         Address offset: 0x005C */
+  __IO uint32_t TIM0CFGR;         /*!< CSI-2 Host timer 0 configuration register             Address offset: 0x0060 */
+  __IO uint32_t TIM1CFGR;         /*!< CSI-2 Host timer 1 configuration register             Address offset: 0x0064 */
+  __IO uint32_t TIM2CFGR;         /*!< CSI-2 Host timer 2 configuration register             Address offset: 0x0068 */
+  __IO uint32_t TIM3CFGR;         /*!< CSI-2 Host timer 3 configuration register             Address offset: 0x006C */
+  __IO uint32_t LMCFGR;           /*!< CSI-2 Host lane merger configuration register         Address offset: 0x0070 */
+  __IO uint32_t PRGITR;           /*!< CSI-2 Host program interrupt register                 Address offset: 0x0074 */
+  __IO uint32_t WDR;              /*!< CSI-2 Host watchdog register                          Address offset: 0x0078 */
+       uint32_t RESERVED1;        /*!< Reserved                                              Address offset: 0x007C */
+  __IO uint32_t IER0;             /*!< CSI-2 Host Interrupt enable register 0                Address offset: 0x0080 */
+  __IO uint32_t IER1;             /*!< CSI-2 Host Interrupt enable register 1                Address offset: 0x0084 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                              Address offset: 0x0088-0x008C */
+  __IO uint32_t SR0;              /*!< CSI-2 Host status register 0                          Address offset: 0x0090 */
+  __IO uint32_t SR1;              /*!< CSI-2 Host status register 1                          Address offset: 0x0094 */
+       uint32_t RESERVED3[26];    /*!< Reserved                                              Address offset: 0x0098-0x00FC */
+  __IO uint32_t FCR0;             /*!< CSI-2 Host Flag clear register 0                      Address offset: 0x0100 */
+  __IO uint32_t FCR1;             /*!< CSI-2 Host Flag clear register 1                      Address offset: 0x0104 */
+       uint32_t RESERVED4[2];     /*!< Reserved                                              Address offset: 0x0108-0x010C */
+  __IO uint32_t SPDFR;            /*!< CSI-2 Host short packet data field register           Address offset: 0x0110 */
+  __IO uint32_t ERR1;             /*!< CSI-2 Host error register 1                           Address offset: 0x0114 */
+  __IO uint32_t ERR2;             /*!< CSI-2 Host error register 2                           Address offset: 0x0118 */
+       uint32_t RESERVED5[953];   /*!< Reserved                                              Address offset: 0x011C-0x0FFC */
+  __IO uint32_t PRCR;             /*!< CSI PHY reset control register                        Address offset: 0x1000 */
+  __IO uint32_t PMCR;             /*!< CSI PHY mode control register                         Address offset: 0x1004 */
+  __IO uint32_t PFCR;             /*!< CSI PHY frequency control register                    Address offset: 0x1008 */
+       uint32_t RESERVED6;        /*!< Reserved                                              Address offset: 0x100C */
+  __IO uint32_t PTCR0;            /*!< CSI PHY test control register 0                       Address offset: 0x1010 */
+  __IO uint32_t PTCR1;            /*!< CSI PHY test control register 1                       Address offset: 0x1014 */
+  __IO uint32_t PTSR;             /*!< CSI PHY test status register                          Address offset: 0x1018 */
+       uint32_t RESERVED7[1017];  /*!< Reserved                                              Address offset: 0x101C-0x1FFC */
+} CSI_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                            Address offset: 0x00  */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,              Address offset: 0x04  */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t APB1LFZ1;      /*!< Debug MCU APB1LFZ1 freeze register,            Address offset: 0x10  */
+  __IO uint32_t APB1HFZ1;      /*!< Debug MCU APB1HFZ1 freeze register,            Address offset: 0x14  */
+  __IO uint32_t APB2FZ1;       /*!< Debug MCU APB2FZ1 freeze register,             Address offset: 0x18  */
+  __IO uint32_t APB4FZ1;       /*!< Debug MCU APB4FZ1 freeze register,             Address offset: 0x1C  */
+  __IO uint32_t APB5FZ1;       /*!< Debug MCU APB5FZ1 freeze register,             Address offset: 0x20  */
+  __IO uint32_t AHB1FZ1;       /*!< Debug MCU AHB1FZ1 freeze register,             Address offset: 0x24  */
+  __IO uint32_t AHB5FZ1;       /*!< Debug MCU AHB5FZ1 freeze register,             Address offset: 0x28  */
+  uint32_t RESERVED2[52];      /*!< Reserved,                                  Address offset: 0x2C-0xF8 */
+  __IO uint32_t SR;            /*!< Debug MCU status register,                     Address offset: 0xFC  */
+  __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register,        Address offset: 0x100 */
+  __IO uint32_t DBG_AUTH_DEV;  /*!< Debug MCU authentication device register,      Address offset: 0x104 */
+  __IO uint32_t DBG_AUTH_ACK;  /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */
+} DBGMCU_TypeDef;
+
+/**
+  * @brief DCMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+#define DCMIPP_NUM_OF_PIPES 0x03U
+
+typedef struct
+{
+  uint32_t PxRIxCR1;      /*! DCMIPP Pipex ROIx configuration register 1  Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2)  */
+  uint32_t PxRIxCR2;      /*! DCMIPP Pipex ROIx configuration register 2  Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2)  */
+} DCMIPP_Region_TypeDef;
+
+/*
+ * @brief Digital camera interface pixel pipeline DCMIPP
+ */
+typedef struct
+{
+  __IO uint32_t IPGR1;           /*!< DCMIPP IPPLUG global register 1                                    Address offset: 0x000 */
+  __IO uint32_t IPGR2;           /*!< DCMIPP IPPLUG global register 2                                    Address offset: 0x004 */
+  __IO uint32_t IPGR3;           /*!< DCMIPP IPPLUG global register 3                                    Address offset: 0x008 */
+       uint32_t RESERVED0[4];    /*!< Reserved                                                           Address offset: 0x00C-0x018 */
+  __IO uint32_t IPGR8;           /*!< DCMIPP IPPLUG identification register                              Address offset: 0x01C */
+  __IO uint32_t IPC1R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */
+       uint32_t RESERVED1;       /*!< Reserved                                                           Address offset: 0x02C */
+  __IO uint32_t IPC2R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x030 */
+  __IO uint32_t IPC2R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x034 */
+  __IO uint32_t IPC2R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x038 */
+       uint32_t RESERVED2;       /*!< Reserved                                                           Address offset: 0x03C */
+  __IO uint32_t IPC3R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x040 */
+  __IO uint32_t IPC3R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x044 */
+  __IO uint32_t IPC3R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x048 */
+       uint32_t RESERVED3;       /*!< Reserved                                                           Address offset: 0x04C */
+  __IO uint32_t IPC4R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x050 */
+  __IO uint32_t IPC4R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x054 */
+  __IO uint32_t IPC4R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x058 */
+       uint32_t RESERVED4;       /*!< Reserved                                                           Address offset: 0x05C */
+  __IO uint32_t IPC5R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x060 */
+  __IO uint32_t IPC5R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x064 */
+  __IO uint32_t IPC5R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x068 */
+       uint32_t RESERVED5[38];   /*!< Reserved                                                           Address offset: 0x06C-0x100 */
+  __IO uint32_t PRCR;            /*!< DCMIPP parallel interface control register                         Address offset: 0x104 */
+  __IO uint32_t PRESCR;          /*!< DCMIPP parallel interface embedded synchronization code register   Address offset: 0x108 */
+  __IO uint32_t PRESUR;          /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */
+       uint32_t RESERVED6[57];   /*!< Reserved                                                           Address offset: 0x110-0x1F0 */
+  __IO uint32_t PRIER;           /*!< DCMIPP parallel interface interrupt enable register                Address offset: 0x1F4 */
+  __IO uint32_t PRSR;            /*!< DCMIPP parallel interface status register                          Address offset: 0x1F8 */
+  __IO uint32_t PRFCR;           /*!< DCMIPP parallel interface interrupt clear register                 Address offset: 0x1FC */
+       uint32_t RESERVED7;       /*!< Reserved                                                           Address offset: 0x200 */
+  __IO uint32_t CMCR;            /*!< DCMIPP common configuration register                               Address offset: 0x204 */
+  __IO uint32_t CMFRCR;          /*!< DCMIPP common frame counter register                               Address offset: 0x208 */
+       uint32_t RESERVED8[121];  /*!< Reserved                                                           Address offset: 0x20C-0x3EC */
+  __IO uint32_t CMIER;           /*!< DCMIPP common interrupt enable register                            Address offset: 0x3F0 */
+  __IO uint32_t CMSR1;           /*!< DCMIPP common status register 1                                    Address offset: 0x3F4 */
+  __IO uint32_t CMSR2;           /*!< DCMIPP common status register 2                                    Address offset: 0x3F8 */
+  __IO uint32_t CMFCR;           /*!< DCMIPP common interrupt clear register                             Address offset: 0x3FC */
+       uint32_t RESERVED9;            /*!< Reserved                                                      Address offset: 0x400 */
+  __IO uint32_t P0FSCR;          /*!< DCMIPP Pipe0 flow selection configuration register                 Address offset: 0x404 */
+       uint32_t RESERVED10[62];  /*!< Reserved                                                           Address offset: 0x408-0x4FC */
+  __IO uint32_t P0FCTCR;         /*!< DCMIPP Pipe0 flow control configuration register                   Address offset: 0x500 */
+  __IO uint32_t P0SCSTR;         /*!< DCMIPP Pipe0 stat/crop start register                              Address offset: 0x504 */
+  __IO uint32_t P0SCSZR;         /*!< DCMIPP Pipe0 stat/crop size register                               Address offset: 0x508 */
+       uint32_t RESERVED11[41];  /*!< Reserved                                                           Address offset: 0x50C-0x5AC */
+  __IO uint32_t P0DCCNTR;        /*!< DCMIPP Pipe0 dump counter register                                 Address offset: 0x5B0 */
+  __IO uint32_t P0DCLMTR;        /*!< DCMIPP Pipe0 dump limit register                                   Address offset: 0x5B4 */
+       uint32_t RESERVED12[2];   /*!< Reserved                                                           Address offset: 0x5B8-0x5BC */
+  __IO uint32_t P0PPCR;          /*!< DCMIPP Pipe0 pixel packer configuration register                   Address offset: 0x5C0 */
+  __IO uint32_t P0PPM0AR1;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1               Address offset: 0x5C4 */
+  __IO uint32_t P0PPM0AR2;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2               Address offset: 0x5C8 */
+       uint32_t RESERVED13;      /*!< Reserved                                                           Address offset: 0x5C8-0x5CC */
+  __IO uint32_t P0STM0AR;        /*!< DCMIPP Pipe0 status Memory0 address register                       Address offset: 0x5D0 */
+       uint32_t RESERVED14[8];   /*!< Reserved                                                           Address offset: 0x5D4-0x5F0 */
+  __IO uint32_t P0IER;           /*!< DCMIPP Pipe0 interrupt enable register                             Address offset: 0x5F4 */
+  __IO uint32_t P0SR;            /*!< DCMIPP Pipe0 status register                                       Address offset: 0x5F8 */
+  __IO uint32_t P0FCR;           /*!< DCMIPP Pipe0 interrupt clear register                              Address offset: 0x5FC */
+       uint32_t RESERVED15;      /*!< Reserved                                                           Address offset: 0x600 */
+  __IO uint32_t P0CFSCR;         /*!< DCMIPP Pipe0 current flow selection configuration register         Address offset: 0x604 */
+       uint32_t RESERVED17[62];  /*!< Reserved                                                           Address offset: 0x608-0x6FC */
+  __IO uint32_t P0CFCTCR;        /*!< DCMIPP Pipe0 current flow control configuration register           Address offset: 0x700 */
+  __IO uint32_t P0CSCSTR;        /*!< DCMIPP Pipe0 current stat/crop start register                      Address offset: 0x704 */
+  __IO uint32_t P0CSCSZR;        /*!< DCMIPP Pipe0 current stat/crop size register                       Address offset: 0x708 */
+       uint32_t RESERVED18[45];  /*!< Reserved                                                           Address offset: 0x70C-0x7BC */
+  __IO uint32_t P0CPPCR;         /*!< DCMIPP Pipe0 current pixel packer configuration register           Address offset: 0x7C0 */
+  __IO uint32_t P0CPPM0AR1;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1       Address offset: 0x7C4 */
+  __IO uint32_t P0CPPM0AR2;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2       Address offset: */
+       uint32_t RESERVED19[14];  /*!< Reserved                                                           Address offset: 0x7C8-0x7FC */
+  __IO uint32_t P1FSCR;          /*!< DCMIPP Pipe1 flow selection configuration register                 Address offset: 0x804 */
+       uint32_t RESERVED20[6];   /*!< Reserved                                                           Address offset: 0x808-0x81C */
+  __IO uint32_t P1SRCR;          /*!< DCMIPP Pipe1 stat removal configuration register                   Address offset: 0x820 */
+  __IO uint32_t P1BPRCR;         /*!< DCMIPP Pipe1 bad pixel removal control register                    Address offset: 0x824 */
+  __IO uint32_t P1BPRSR;         /*!< DCMIPP Pipe1 bad pixel removal status register                     Address offset: 0x828 */
+       uint32_t RESERVED21;      /*!< Reserved                                                           Address offset: 0x82C */
+  __IO uint32_t P1DECR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x830 */
+       uint32_t RESERVED22[3];   /*!< Reserved                                                           Address offset: 0x834-0x83C */
+  __IO uint32_t P1BLCCR;         /*!< DCMIPP Pipe1 black level calibration control register              Address offset: 0x840 */
+  __IO uint32_t P1EXCR1;         /*!< DCMIPP Pipe1 exposure control register 1                           Address offset: 0x844 */
+  __IO uint32_t P1EXCR2;         /*!< DCMIPP Pipe1 exposure control register 2                           Address offset: 0x848 */
+       uint32_t RESERVED23;      /*!< Reserved                                                           Address offset: 0x84C */
+  __IO uint32_t P1ST1CR;         /*!< DCMIPP Pipe1 statistics 1 control register                         Address offset: 0x850 */
+  __IO uint32_t P1ST2CR;         /*!< DCMIPP Pipe1 statistics 2 control register                         Address offset: 0x854 */
+  __IO uint32_t P1ST3CR;         /*!< DCMIPP Pipe1 statistics 3 control register                         Address offset: 0x858 */
+  __IO uint32_t P1STSTR;         /*!< DCMIPP Pipe1 statistics window start register                      Address offset: 0x85C */
+  __IO uint32_t P1STSZR;         /*!< DCMIPP Pipe1 statistics window size register                       Address offset: 0x860 */
+  __IO uint32_t P1ST1SR;         /*!< DCMIPP Pipe1 statistics 1 status register                          Address offset: 0x864 */
+  __IO uint32_t P1ST2SR;         /*!< DCMIPP Pipe1 statistics 2 status register                          Address offset: 0x868 */
+  __IO uint32_t P1ST3SR;         /*!< DCMIPP Pipe1 statistics 3 status register                          Address offset: 0x86C */
+  __IO uint32_t P1DMCR;          /*!< DCMIPP Pipe1 demosaicing configuration register                    Address offset: 0x870 */
+       uint32_t RESERVED24[3];   /*!< Reserved                                                           Address offset: 0x874-0x87C */
+  __IO uint32_t P1CCCR;          /*!< DCMIPP Pipe1 ColorConv configuration register                      Address offset: 0x880 */
+  __IO uint32_t P1CCRR1;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 1                  Address offset: 0x884 */
+  __IO uint32_t P1CCRR2;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 2                  Address offset: 0x888 */
+  __IO uint32_t P1CCGR1;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 1                Address offset: 0x88C */
+  __IO uint32_t P1CCGR2;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 2                Address offset: 0x890 */
+  __IO uint32_t P1CCBR1;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1                 Address offset: 0x894 */
+  __IO uint32_t P1CCBR2;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2                 Address offset: 0x898 */
+       uint32_t RESERVED25;      /*!< Reserved                                                           Address offset: 0x89C */
+  __IO uint32_t P1CTCR1;         /*!< DCMIPP Pipe1 contrast control register 1                           Address offset: 0x8A0 */
+  __IO uint32_t P1CTCR2;         /*!< DCMIPP Pipe1 contrast control register 2                           Address offset: 0x8A4 */
+  __IO uint32_t P1CTCR3;         /*!< DCMIPP Pipe1 contrast control register 3                           Address offset: 0x8A8 */
+       uint32_t RESERVED26[21];  /*!< Reserved                                                           Address offset: 0x8AC-0x8FC */
+  __IO uint32_t P1FCTCR;         /*!< DCMIPP Pipe1 flow control configuration register                   Address offset: 0x900 */
+  __IO uint32_t P1CRSTR;         /*!< DCMIPP Pipe1 crop window start register                            Address offset: 0x904 */
+  __IO uint32_t P1CRSZR;         /*!< DCMIPP Pipe1 crop window size register                             Address offset: 0x908 */
+  __IO uint32_t P1DCCR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x90C */
+  __IO uint32_t P1DSCR;          /*!< DCMIPP Pipe1 downsize configuration register                       Address offset: 0x910 */
+  __IO uint32_t P1DSRTIOR;       /*!< DCMIPP Pipe1 downsize ratio register                               Address offset: 0x914 */
+  __IO uint32_t P1DSSZR;         /*!< DCMIPP Pipe1 downsize destination size register                    Address offset: 0x918 */
+       uint32_t RESERVED28;      /*!< Reserved                                                           Address offset:  */
+  __IO uint32_t P1CMRICR;        /*!< DCMIPP Pipe1 common ROI configuration register                     Address offset: 0x920 */
+  __IO uint32_t P1RIxCR1;        /*!< DCMIPP Pipe1 ROIx configuration register 1                         Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P1RIxCR2;        /*!< DCMIPP Pipe1 ROIx configuration register 2                         Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED29[17];      /*!< Reserved                                                       Address offset:  */
+  __IO uint32_t P1GMCR;          /*!< DCMIPP Pipe1 gamma configuration register                          Address offset: 0x970 */
+       uint32_t RESERVED30[3];   /*!< Reserved                                                           Address offset: 0x974-0x97C */
+  __IO uint32_t P1YUVCR;         /*!< DCMIPP Pipe1 YUVConv configuration register                        Address offset: 0x980 */
+  __IO uint32_t P1YUVRR1;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 1                    Address offset: 0x984 */
+  __IO uint32_t P1YUVRR2;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 2                    Address offset: 0x988 */
+  __IO uint32_t P1YUVGR1;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 1                  Address offset: 0x98C */
+  __IO uint32_t P1YUVGR2;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 2                  Address offset: 0x990 */
+  __IO uint32_t P1YUVBR1;        /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1                   Address offset: 0x994 */
+  __IO uint32_t P1YUVBR2;        /*!< DCMIPP Pipe1 YUV blue coefficient register 2                       Address offset: 0x998 */
+       uint32_t RESERVED31[9];   /*!< Reserved                                                           Address offset: 0x99C-0x9BC */
+  __IO uint32_t P1PPCR;          /*!< DCMIPP Pipe1 pixel packer configuration register                   Address offset: 0x9C0 */
+  __IO uint32_t P1PPM0AR1;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1               Address offset: 0x9C4 */
+  __IO uint32_t P1PPM0AR2;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2               Address offset: 0x9C8 */
+  __IO uint32_t P1PPM0PR;        /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register                   Address offset: 0x9CC */
+  __IO uint32_t P1STM0AR;        /*!< DCMIPP Pipe1 status Memory0 address register                       Address offset: 0x9D0 */
+  __IO uint32_t P1PPM1AR1;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1               Address offset: 0x9D4 */
+  __IO uint32_t P1PPM1AR2;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2               Address offset: 0x9D8 */
+  __IO uint32_t P1PPM1PR;        /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register                   Address offset: 0x9DC */
+  __IO uint32_t P1STM1AR;        /*!< DCMIPP Pipe1 status Memory1 address register                       Address offset: 0x9E0 */
+  __IO uint32_t P1PPM2AR1;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 1               Address offset: 0x9E4 */
+  __IO uint32_t P1PPM2AR2;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 2               Address offset: 0x9E8 */
+  __IO uint32_t RESERVED34;      /*!< Reserved                                                           Address offset: 0x9EC */
+  __IO uint32_t P1STM2AR;        /*!< DCMIPP Pipe1 status Memory2 address register                       Address offset: 0x9F0 */
+  __IO uint32_t P1IER;           /*!< DCMIPP Pipe1 interrupt enable register                             Address offset: 0x9F4 */
+  __IO uint32_t P1SR;            /*!< DCMIPP Pipe1 status register                                       Address offset: 0x9F8 */
+  __IO uint32_t P1FCR;           /*!< DCMIPP Pipe1 interrupt clear register                              Address offset: 0x9FC */
+       uint32_t RESERVED35;      /*!< Reserved                                                           Address offset: 0xA00 */
+  __IO uint32_t P1CFSCR;         /*!< DCMIPP Pipe1 current flow selection configuration register         Address offset: 0xA04 */
+       uint32_t RESERVED36[7];   /*!< Reserved                                                           Address offset: 0xA08-0xA20 */
+  __IO uint32_t P1CBPRCR;        /*!< DCMIPP Pipe1 current bad pixel removal register                    Address offset: 0xA24 */
+       uint32_t RESERVED37[6];   /*!< Reserved                                                           Address offset: 0xA28-0xA3C */
+  __IO uint32_t P1CBLCCR;        /*!< DCMIPP Pipe1 current black level calibration control register      Address offset: 0xA40 */
+  __IO uint32_t P1CEXCR1;        /*!< DCMIPP Pipe1 current exposure control register 1                   Address offset: 0xA44 */
+  __IO uint32_t P1CEXCR2;        /*!< DCMIPP Pipe1 current exposure control register 2                   Address offset: 0xA48 */
+       uint32_t RESERVED38;      /*!< Reserved                                                           Address offset: 0xA4C */
+  __IO uint32_t P1CST1CR;        /*!< DCMIPP Pipe1 current statistics 1 control register                 Address offset: 0xA50 */
+  __IO uint32_t P1CST2CR;        /*!< DCMIPP Pipe1 current statistics 2 control register                 Address offset: 0xA54 */
+  __IO uint32_t P1CST3CR;        /*!< DCMIPP Pipe1 current statistics 3 control register                 Address offset: 0xA58 */
+  __IO uint32_t P1CSTSTR;        /*!< DCMIPP Pipe1 current statistics window start register              Address offset: 0xA5C */
+  __IO uint32_t P1CSTSZR;        /*!< DCMIPP Pipe1 current statistics window size register               Address offset: 0xA60 */
+       uint32_t RESERVED39[7];   /*!< Reserved                                                           Address offset: 0xA64-0xA7C */
+  __IO uint32_t P1CCCCR;         /*!< DCMIPP Pipe1 current ColorConv configuration register              Address offset: 0xA80 */
+  __IO uint32_t P1CCCRR1;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1          Address offset: 0xA84 */
+  __IO uint32_t P1CCCRR2;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2          Address offset: 0xA88 */
+  __IO uint32_t P1CCCGR1;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1        Address offset: 0xA8C */
+  __IO uint32_t P1CCCGR2;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2        Address offset: 0xA90 */
+  __IO uint32_t P1CCCBR1;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1         Address offset: 0xA94 */
+  __IO uint32_t P1CCCBR2;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2         Address offset: 0xA98 */
+       uint32_t RESERVED40;      /*!< Reserved                                                           Address offset: 0xA9C */
+  __IO uint32_t P1CCTCR1;        /*!< DCMIPP Pipe1 current contrast control register 1                   Address offset: 0xAA0 */
+  __IO uint32_t P1CCTCR2;        /*!< DCMIPP Pipe1 current contrast control register 2                   Address offset: 0xAA4 */
+  __IO uint32_t P1CCTCR3;        /*!< DCMIPP Pipe1 current contrast control register 3                   Address offset: 0xAA8 */
+       uint32_t RESERVED41[21];  /*!< Reserved                                                           Address offset: 0xAAC-0xAFC */
+  __IO uint32_t P1CFCTCR;        /*!< DCMIPP Pipe1 current flow control configuration register           Address offset: 0xB00 */
+  __IO uint32_t P1CCRSTR;        /*!< DCMIPP Pipe1 current crop window start register                    Address offset: 0xB04 */
+  __IO uint32_t P1CCRSZR;        /*!< DCMIPP Pipe1 current crop window size register                     Address offset: 0xB08 */
+  __IO uint32_t P1CDCCR;         /*!< DCMIPP Pipe1 current decimation register                           Address offset: 0xB0C */
+  __IO uint32_t P1CDSCR;         /*!< DCMIPP Pipe1 current downsize configuration register               Address offset: 0xB10 */
+  __IO uint32_t P1CDSRTIOR;      /*!< DCMIPP Pipe1 current downsize ratio register                       Address offset: 0xB14 */
+  __IO uint32_t P1CDSSZR;        /*!< DCMIPP Pipe1 current downsize destination size register            Address offset: 0xB18 */
+       uint32_t RESERVED43;      /*!< Reserved                                                           Address offset: 0xB1C */
+       uint32_t P1CCMRICR;       /*!< DCMIPP Pipe1 current common ROI configuration register             Address offset: 0xB20 */
+  __IO uint32_t P1CRIxCR1;       /*!< DCMIPP Pipe1 current ROIx configuration register 1                 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */
+  __IO uint32_t P1CRIxCR2;       /*!< DCMIPP Pipe1 current ROIx configuration register 2                 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */
+  uint32_t RESERVED44[37];       /*!< Reserved                                                           Address offset: 0xB64-0xBBC */
+  __IO uint32_t P1CPPCR;         /*!< DCMIPP Pipe1 current pixel packer configuration register           Address offset: 0xBC0 */
+  __IO uint32_t P1CPPM0AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC4 */
+  __IO uint32_t P1CPPM0AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC8 */
+  __IO uint32_t P1CPPM0PR;       /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register           Address offset: 0xBCC */
+       uint32_t RESERVED45;      /*!< Reserved                                                           Address offset: 0xBD0 */
+  __IO uint32_t P1CPPM1AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1       Address offset: 0xBD4 */
+  __IO uint32_t P1CPPM1AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2       Address offset: 0xBD8 */
+  __IO uint32_t P1CPPM1PR;       /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register           Address offset: 0xBDC */
+       uint32_t RESERVED47;      /*!< Reserved                                                           Address offset: 0xBE0 */
+  __IO uint32_t P1CPPM2AR1;      /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1       Address offset: 0xBE4 */
+  __IO uint32_t P1CPPM2AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2       Address offset: 0xBE8 */
+       uint32_t RESERVED48[6];   /*!< Reserved                                                           Address offset: 0xBE8-0xBFC */
+  __IO uint32_t P2FSCR;          /*!< DCMIPP Pipe2 flow selection configuration register                 Address offset: 0xC04 */
+       uint32_t RESERVED49[62];  /*!< Reserved                                                           Address offset: 0xC08-0xCFC */
+  __IO uint32_t P2FCTCR;         /*!< DCMIPP Pipe2 flow control configuration register                   Address offset: 0xD00 */
+  __IO uint32_t P2CRSTR;         /*!< DCMIPP Pipe2 crop window start register                            Address offset: 0xD04 */
+  __IO uint32_t P2CRSZR;         /*!< DCMIPP Pipe2 crop window size register                             Address offset: 0xD08 */
+  __IO uint32_t P2DCCR;          /*!< DCMIPP Pipe2 decimation register                                   Address offset: 0xD0C */
+  __IO uint32_t P2DSCR;          /*!< DCMIPP Pipe2 downsize configuration register                       Address offset: 0xD10 */
+  __IO uint32_t P2DSRTIOR;       /*!< DCMIPP Pipe2 downsize ratio register                               Address offset: 0xD14 */
+  __IO uint32_t P2DSSZR;         /*!< DCMIPP Pipe2 downsize destination size register                    Address offset: 0xD18 */
+       uint32_t RESERVED51;      /*!< Reserved                                                           Address offset:  0xD1C */
+  __IO uint32_t P2CMRICR;        /*!< DCMIPP Pipe2 common ROI configuration register                     Address offset:  0xD20 */
+  __IO uint32_t P2RIxCR1;        /*!< DCMIPP Pipe2 ROIx configuration register 1                         Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P2RIxCR2;        /*!< DCMIPP Pipe2 ROIx configuration register 2                         Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED53[17];  /*!< Reserved                                                           Address offset: */
+  __IO uint32_t P2GMCR;          /*!< DCMIPP Pipe2 gamma configuration register                          Address offset: 0xD70 */
+       uint32_t RESERVED54[19];  /*!< Reserved                                                           Address offset: 0xD74-0xDBC */
+  __IO uint32_t P2PPCR;          /*!< DCMIPP Pipe2 pixel packer configuration register                   Address offset: 0xDC0 */
+  __IO uint32_t P2PPM0AR1;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1               Address offset: 0xDC4 */
+  __IO uint32_t P2PPM0AR2;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2               Address offset: 0xDC8 */
+  __IO uint32_t P2PPM0PR;        /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register                   Address offset: 0xDCC */
+  __IO uint32_t P2STM0AR;        /*!< DCMIPP Pipe2 status Memory0 address register                       Address offset: 0xDD0 */
+       uint32_t RESERVED55[8];   /*!< Reserved                                                           Address offset: 0xDD4-0xDF0 */
+  __IO uint32_t P2IER;           /*!< DCMIPP Pipe2 interrupt enable register                             Address offset: 0xDF4 */
+  __IO uint32_t P2SR;            /*!< DCMIPP Pipe2 status register                                       Address offset: 0xDF8 */
+  __IO uint32_t P2FCR;           /*!< DCMIPP Pipe2 interrupt clear register                              Address offset: 0xDFC */
+       uint32_t RESERVED56;      /*!< Reserved                                                           Address offset: 0xE00 */
+  __IO uint32_t P2CFSCR;         /*!< DCMIPP Pipe2 current flow selection configuration register         Address offset: 0xE04 */
+       uint32_t RESERVED57[62];  /*!< Reserved                                                           Address offset: 0xE08-0xEFC */
+  __IO uint32_t P2CFCTCR;        /*!< DCMIPP Pipe2 current flow control configuration register           Address offset: 0xF00 */
+  __IO uint32_t P2CCRSTR;        /*!< DCMIPP Pipe2 current crop window start register                    Address offset: 0xF04 */
+  __IO uint32_t P2CCRSZR;        /*!< DCMIPP Pipe2 current crop window size register                     Address offset: 0xF08 */
+  __IO uint32_t P2CDCCR;         /*!< DCMIPP Pipe2 current decimation register                           Address offset: 0xF0C */
+  __IO uint32_t P2CDSCR;         /*!< DCMIPP Pipe2 current downsize configuration register               Address offset: 0xF10 */
+  __IO uint32_t P2CDSRTIOR;      /*!< DCMIPP Pipe2 current downsize ratio register                       Address offset: 0xF14 */
+  __IO uint32_t P2CDSSZR;        /*!< DCMIPP Pipe2 current downsize destination size register            Address offset: 0xF18 */
+  __IO uint32_t RESERVED59[2];   /*!< Reserved                                                           Address offset: 0xF1C-0xF20 */
+  __IO uint32_t P2CRIxCR1;       /*!< Pipe2 current ROIx configuration register 1                        Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/
+  __IO uint32_t P2CRIxCR2;       /*!< Pipe2 current ROIx configuration register 2                        Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/
+       uint32_t RESERVED60[37];  /*!< Reserved                                                           Address offset: 0xF64-0xFBC */
+  __IO uint32_t P2CPPCR;         /*!< DCMIPP Pipe2 current pixel packer configuration register           Address offset: 0xFC0 */
+  __IO uint32_t P2CPPM0AR1;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1       Address offset: 0xFC4 */
+  __IO uint32_t P2CPPM0AR2;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2       Address offset: 0xFC8 */
+  __IO uint32_t P2CPPM0PR;       /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register           Address offset: 0xFCC */
+       uint32_t RESERVED61[7];   /*!< Reserved                                                           Address offset: 0xFD0-0xFE8 */
+  __IO uint32_t HWCFGR2;         /*!< DCMIPP hardware configuration register 2                           Address offset: 0xFEC */
+  __IO uint32_t HWCFGR1;         /*!< DCMIPP hardware configuration register 1                           Address offset: 0xFF0 */
+  __IO uint32_t VERR;            /*!< DCMIPP version register                                            Address offset: 0xFF4 */
+  __IO uint32_t IPIDR;           /*!< DCMIPP identification register                                     Address offset: 0xFF8 */
+  __IO uint32_t SIDR;            /*!< DCMIPP size identification register                                Address offset: 0xFFC */
+} DCMIPP_TypeDef;
+
+/**
+  * @ brief Delay Block
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< Delay Block Control Register,       Address offset: 0x00 */
+  __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t SECCFGR;      /*!< DMA secure configuration register,               Address offset: 0x00  */
+  __IO uint32_t PRIVCFGR;     /*!< DMA privileged configuration register,           Address offset: 0x04 */
+  __IO uint32_t RCFGLOCKR;    /*!< DMA configuration lock register,                 Address offset: 0x08 */
+  __IO uint32_t MISR;         /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
+  __IO uint32_t SMISR;        /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CLBAR;         /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
+  __IO uint32_t CCIDCFGR;      /*!< DMA channel x CID register,                      Address offset: 0x54 + (x * 0x80) */
+       uint32_t RESERVED1[1];  /*!< Reserved 1,                                      Address offset: 0x58 + (x * 0x80) */
+  __IO uint32_t CFCR;          /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
+  __IO uint32_t CSR;           /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
+  __IO uint32_t CCR;           /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
+       uint32_t RESERVED2[10]; /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C + (x * 0x80) */
+  __IO uint32_t CTR1;          /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
+  __IO uint32_t CTR2;          /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
+  __IO uint32_t CBR1;          /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
+  __IO uint32_t CSAR;          /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
+  __IO uint32_t CDAR;          /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
+  __IO uint32_t CTR3;          /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
+  __IO uint32_t CBR2;          /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
+       uint32_t RESERVED3[8];  /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8 + (x * 0x80) */
+  __IO uint32_t CLLR;          /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
+} DMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
+} DMA2D_TypeDef;
+
+/**
+  * @brief DTS Controller
+  */
+typedef struct
+{
+  uint32_t      RESERVED1[4];    /*!< Reserved,                                 Address offset: 0x00-0x0F */
+  __IO uint32_t PVTREG_LOCKR;    /*!< DTS PVT Register Lock Register,           Address offset: 0x10 */
+  __IO uint32_t PVTLOCK_SR;      /*!< DTS PVT Lock Status Register,             Address offset: 0x14 */
+  uint32_t      RESERVED2[2];    /*!< Reserved,                                 Address offset: 0x18-0x1F */
+  __IO uint32_t PVTTMR_CR;       /*!< DTS PVT Timer Control Register,           Address offset: 0x20 */
+  __IO uint32_t PVTTMR_SR;       /*!< DTS PVT Timer Status Register,            Address offset: 0x24 */
+  uint32_t      RESERVED3[6];    /*!< Reserved,                                 Address offset: 0x28-0x3F */
+  __IO uint32_t PVT_IER;         /*!< DTS PVT IRQ Enable Register,              Address offset: 0x40 */
+  uint32_t      RESERVED4[3];    /*!< Reserved,                                 Address offset: 0x44-0x4F */
+  __IO uint32_t PVTIRQTRMASKR;   /*!< DTS PVT IRQ Timer Mask Register,          Address offset: 0x50 */
+  __IO uint32_t TS_MR;           /*!< DTS PVT IRQ TS Mask Register,             Address offset: 0x54 */
+  uint32_t      RESERVED5[2];    /*!< Reserved,                                 Address offset: 0x58-0x5F */
+  __IO uint32_t PVTTR_SR;        /*!< DTS PVT IRQ Timer Status Register,        Address offset: 0x60 */
+  __IO uint32_t TS_ISR;          /*!< DTS PVT IRQ TS Status Register,           Address offset: 0x64 */
+  uint32_t      RESERVED6[2];    /*!< Reserved,                                 Address offset: 0x68-0x6F */
+  __IO uint32_t PVTTMRRAW_ISR;   /*!< DTS PVT IRQ Timer Raw Status Register,    Address offset: 0x70 */
+  __IO uint32_t TSRAW_ISR;       /*!< DTS PVT IRQ TS Raw Status Register,       Address offset: 0x74 */
+  uint32_t      RESERVED7[2];    /*!< Reserved,                                 Address offset: 0x78-0x7F */
+  __IO uint32_t TSCCLKSYNTHR;    /*!< DTS TSC Clock Synthesizer Register,       Address offset: 0x80 */
+  __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register,  Address offset: 0x84 */
+  __IO uint32_t TSCSDIF_SR;      /*!< DTS TSC SDIF Status Register,             Address offset: 0x88 */
+  __IO uint32_t TSCSDIF_CR;      /*!< DTS TSC SDIF Register,                    Address offset: 0x8C */
+  __IO uint32_t TSCSDIFHALTR;    /*!< DTS TSC SDIF Halt Register,               Address offset: 0x90 */
+  __IO uint32_t TSCSDIF_CFGR;    /*!< DTS TSC SDIF Control Register,            Address offset: 0x94 */
+  uint32_t      RESERVED8[2];    /*!< Reserved,                                 Address offset: 0x98-0x9F */
+  __IO uint32_t TSCSMPL_CR;      /*!< DTS TSC Sample Control Register,          Address offset: 0xA0 */
+  __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register,            Address offset: 0xA4 */
+  __IO uint32_t TSCSMPLCNTR;     /*!< DTS TSC Sample Count Register,            Address offset: 0xA8 */
+} DTS_TypeDef;
+
+/**
+  * @brief DTS Sensor Controller
+  */
+typedef struct
+{
+  __IO uint32_t TS_IER;          /*!< DTS TSx IRQ Enable Register,              Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ISR;          /*!< DTS TSx IRQ Status Register,              Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ICR;          /*!< DTS TSx IRQ Clear Register,               Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSIRQTESTR;      /*!< DTS TSx IRQ Test Register,                Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFRDATAR;    /*!< DTS TSx SDIF RDATA Register,              Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDONER;     /*!< DTS TSx SDIF Done Register,               Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDATAR;     /*!< DTS TSx SDIF Data Register,               Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */
+  uint32_t      RESERVED1[1];    /*!< Reserved,                                 Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMA_CFGR;   /*!< DTS TSx Alarm A Configuration Register,   Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMB_CFGR;   /*!< DTS TSx Alarm B Configuration Register,   Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHLSAMPLER;     /*!< DTS TSx High/Low Sample Register,         Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHILORESETR;    /*!< DTS TSx High/Low Reset Register,          Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */
+} DTS_SensorTypeDef;
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;               /*!< Operating mode configuration register,                        Address offset: 0x00 */
+  __IO uint32_t MACECR;              /*!< Extended operating mode configuration register,               Address offset: 0x04 */
+  __IO uint32_t MACPFR;              /*!< Packet filtering control register             ,               Address offset: 0x08 */
+  __IO uint32_t MACWTR;              /*!< Watchdog timeout register,                                    Address offset: 0x0C */
+  __IO uint32_t MACHT0R;             /*!< Hash Table 0 register,                                        Address offset: 0x10 */
+  __IO uint32_t MACHT1R;             /*!< Hash Table 1 register,                                        Address offset: 0x14 */
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTCR;             /*!< VLAN tag Control register,                                    Address offset: 0x50 */
+  __IO uint32_t MACVTDR;             /*!< VLAN tag data register,                                       Address offset: 0x54 */
+  __IO uint32_t MACVHTR;             /*!< VLAN Hash table register,                                     Address offset: 0x58 */
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVIR;              /*!< VLAN inclusion register,                                      Address offset: 0x60 */
+  __IO uint32_t MACIVIR;             /*!< Inner VLAN inclusion register,                                Address offset: 0x64 */
+  uint32_t      RESERVED3[2];
+  __IO uint32_t MACQ0TXFCR;          /*!< Tx Queue 0 flow control register,                             Address offset: 0x70 */
+  uint32_t      RESERVED4[7];
+  __IO uint32_t MACRXFCR;            /*!< Rx flow control register,                                     Address offset: 0x90 */
+  __IO uint32_t MACRXQCR;            /*!< Rx Queue control register,                                    Address offset: 0x94 */
+  uint32_t      RESERVED5[2];
+  __IO uint32_t MACRXQC0R;           /*!< Rx queue control 0 register,                                  Address offset: 0xA0 */
+  __IO uint32_t MACRXQC1R;           /*!< Rx queue control 1 register,                                  Address offset: 0xA4 */
+  __IO uint32_t MACRXQC2R;           /*!< Rx queue control 2 register,                                  Address offset: 0xA8 */
+  uint32_t      RESERVED6;
+  __IO uint32_t MACISR;              /*!< Interrupt status register,                                    Address offset: 0xB0 */
+  __IO uint32_t MACIER;              /*!< Interrupt enable register,                                    Address offset: 0xB4 */
+  __IO uint32_t MACRXTXSR;           /*!< Rx Tx status register,                                        Address offset: 0xB8 */
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;             /*!< PMT control status register,                                  Address offset: 0xC0 */
+  __IO uint32_t MACRWKPFR;           /*!< Remote wakeup packet filter register,                         Address offset: 0xC4 */
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;             /*!< LPI control and status register,                              Address offset: 0xD0 */
+  __IO uint32_t MACLTCR;             /*!< LPI timers control register,                                  Address offset: 0xD4 */
+  __IO uint32_t MACLETR;             /*!< LPI entry timer register,                                     Address offset: 0xD8 */
+  __IO uint32_t MAC1USTCR;           /*!< One-microsecond-tick counter register,                        Address offset: 0xDC */
+  uint32_t      RESERVED9[6];
+  __IO uint32_t MACPHYCSR;           /*!< PHYIF control status register,                                Address offset: 0xF8 */
+  uint32_t      RESERVED10[5];
+  __IO uint32_t MACVR;               /*!< Version register,                                             Address offset: 0x110 */
+  __IO uint32_t MACDR;               /*!< Debug register,                                               Address offset: 0x114 */
+  uint32_t      RESERVED11;
+  __IO uint32_t MACHWF0R;            /*!< HW feature 0 register,                                        Address offset: 0x11C */
+  __IO uint32_t MACHWF1R;            /*!< HW feature 1 register,                                        Address offset: 0x120 */
+  __IO uint32_t MACHWF2R;            /*!< HW feature 2 register,                                        Address offset: 0x124 */
+  __IO uint32_t MACHWF3R;            /*!< HW feature 3 register,                                        Address offset: 0x128 */
+  uint32_t      RESERVED12[53];
+  __IO uint32_t MACMDIOAR;           /*!< MDIO address register,                                        Address offset: 0x200 */
+  __IO uint32_t MACMDIODR;           /*!< MDIO data register,                                           Address offset: 0x204 */
+  uint32_t      RESERVED13[2];
+  __IO uint32_t MACARPAR;            /*!< ARP address register,                                         Address offset: 0x210 */
+  uint32_t      RESERVED14[7];
+  __IO uint32_t MACCSRSWCR;          /*!< CSR software control register,                                Address offset: 0x230 */
+  __IO uint32_t MACFPECSR;           /*!< FPE control and status register,                              Address offset: 0x234 */
+   uint32_t     RESERVED15[2];
+  __IO uint32_t MACPRSTIMR;          /*!< MAC presentation time register,                               Address offset: 0x0240 */
+  __IO uint32_t MACPRSTIMUR;         /*!< MAC presentation time update register,                        Address offset: 0x0244 */
+   uint32_t     RESERVED16[46];
+  __IO uint32_t MACA0HR;             /*!< MAC Address 0 high register,                                  Address offset: 0x0300 */
+  __IO uint32_t MACA0LR;             /*!< MAC Address 0 low register,                                   Address offset: 0x0304 */
+  __IO uint32_t MACA1HR;             /*!< MAC Address 1 high register,                                  Address offset: 0x0308 */
+  __IO uint32_t MACA1LR;             /*!< MAC Address 1 low register,                                   Address offset: 0x030C */
+  __IO uint32_t MACA2HR;             /*!< MAC Address 2 high register,                                  Address offset: 0x0310 */
+  __IO uint32_t MACA2LR;             /*!< MAC Address 2 low register,                                   Address offset: 0x0314 */
+  __IO uint32_t MACA3HR;             /*!< MAC Address 3 high register,                                  Address offset: 0x0318 */
+  __IO uint32_t MACA3LR;             /*!< MAC Address 3 low register,                                   Address offset: 0x031C */
+  uint32_t      RESERVED17[248];
+  __IO uint32_t MMCCR;               /*!< MMC control register,                                         Address offset: 0x0700 */
+  __IO uint32_t MMCRIR;              /*!< MMC Rx interrupt register,                                    Address offset: 0x0704 */
+  __IO uint32_t MMCTIR;              /*!< MMC Tx interrupt register,                                    Address offset: 0x0708 */
+  __IO uint32_t MMCRIMR;             /*!< MMC Rx interrupt mask register,                               Address offset: 0x070C */
+  __IO uint32_t MMCTIMR;             /*!< MMC Tx interrupt mask register,                               Address offset: 0x0710 */
+  uint32_t      RESERVED18[14];
+  __IO uint32_t MMCTSCGPR;           /*!< Tx single collision good packets register,                    Address offset: 0x074C */
+  __IO uint32_t MMCTMCGPR;           /*!< Tx multiple collision good packets register,                  Address offset: 0x0750 */
+  uint32_t      RESERVED19[5];
+  __IO uint32_t MMCTPCGR;            /*!< Tx packet count good register,                                Address offset: 0x0768 */
+  uint32_t      RESERVED20[10];
+  __IO uint32_t MMCRCRCEPR;          /*!< Rx CRC error packets register,                                Address offset: 0x0794 */
+  __IO uint32_t MMCRAEPR;            /*!< Rx alignment error packets register,                          Address offset: 0x0798 */
+  uint32_t      RESERVED21[10];
+  __IO uint32_t MMCRUPGR;            /*!< Rx unicast packets good register,                             Address offset: 0x07C4 */
+  uint32_t      RESERVED22[9];
+  __IO uint32_t MMCTLPIMSTR;         /*!< Tx LPI microsecond timer register,                            Address offset: 0x07EC */
+  __IO uint32_t MMCTLPITCR;          /*!< Tx LPI transition counter register,                           Address offset: 0x07F0 */
+  __IO uint32_t MMCRLPIMSTR;         /*!< Rx LPI microsecond counter register,                          Address offset: 0x07F4 */
+  __IO uint32_t MMCRLPITCR;          /*!< Rx LPI transition counter register,                           Address offset: 0x07F8 */
+  uint32_t      RESERVED23[41];
+  __IO uint32_t MMCFPETISR;          /*!< MMC FPE Tx interrupt status register,                         Address offset: 0x08A0 */
+  __IO uint32_t MMCFPETIMR;          /*!< MMC FPE Tx interrupt mask register,                           Address offset: 0x08A4 */
+  __IO uint32_t MMCFPETFCR;          /*!< MMC FPE Tx fragment counter register,       -                 Address offset: 0x08A8 */
+  __IO uint32_t MMCTHRCR;            /*!< MMC Tx hold request counter register,                         Address offset: 0x08AC */
+  uint32_t      RESERVED24[4];
+  __IO uint32_t MMCFPERISR;          /*!< MMC FPE Rx interrupt status register,                         Address offset: 0x08C0 */
+  __IO uint32_t MMCFPERIMR;          /*!< MMC FPE Rx interrupt mask register,                           Address offset: 0x08C4 */
+  __IO uint32_t MMCRPAER;            /*!< MMC Rx packet assembly error register,                        Address offset: 0x08C8 */
+  __IO uint32_t MMCRPSMDER;          /*!< MMC Rx packet SMD error register,                             Address offset: 0x08CC */
+  __IO uint32_t MMCRPAOKR;           /*!< MMC Rx packet assembly OK register,                           Address offset: 0x08D0 */
+  __IO uint32_t MMCFPERFCR;          /*!< MMC Rx FPE fragments counter register,                        Address offset: 0x08D4 */
+  uint32_t      RESERVED25[10];
+  __IO uint32_t MACL3L4C0R;          /*!< L3 and L4 control 0 register,                                 Address offset: 0x0900 */
+  __IO uint32_t MACL4A0R;            /*!< Layer4 Address filter 0 register,                             Address offset: 0x0904 */
+  uint32_t      RESERVED26[2];
+  __IO uint32_t MACL3A0R0R;           /*!< Layer3 Address 0 filter 0 register,                           Address offset: 0x0910 */
+  __IO uint32_t MACL3A1R0R;           /*!< Layer3 Address 1 filter 0 register,                           Address offset: 0x0914 */
+  __IO uint32_t MACL3A2R0R;           /*!< Layer3 Address 2 filter 0 register,                           Address offset: 0x0918 */
+  __IO uint32_t MACL3A3R0R;           /*!< Layer3 Address 3 filter 0 register,                           Address offset: 0x091C */
+  uint32_t      RESERVED27[4];
+  __IO uint32_t MACL3L4C1R;          /*!< L3 and L4 control 1 register,                                 Address offset: 0x0930 */
+  __IO uint32_t MACL4A1R;            /*!< Layer 4 address filter 1 register,                            Address offset: 0x0934 */
+  uint32_t      RESERVED28[2];
+  __IO uint32_t MACL3A01R;           /*!< Layer3 address 0 filter 1 Register,                           Address offset: 0x0940 */
+  __IO uint32_t MACL3A11R;           /*!< Layer3 address 1 filter 1 register,                           Address offset: 0x0944 */
+  __IO uint32_t MACL3A21R;           /*!< Layer3 address 2 filter 1 Register,                           Address offset: 0x0948 */
+  __IO uint32_t MACL3A31R;           /*!< Layer3 address 3 filter 1 register,                           Address offset: 0x094C */
+  uint32_t      RESERVED29[72];
+  __IO uint32_t MACIACR;             /*!< MAC Indirect Access Control register,                         Address offset: 0x0A70 */
+  __IO uint32_t MACTMRQR;            /*!< MAC type-based Rx Queue mapping register,                     Address offset: 0x0A74 */
+  uint32_t      RESERVED30[34];
+  __IO uint32_t MACTSCR;             /*!< Timestamp control Register,                                   Address offset: 0x0B00 */
+  __IO uint32_t MACSSIR;             /*!< Subsecond increment register,                                 Address offset: 0x0B04 */
+  __IO uint32_t MACSTSR;             /*!< System time seconds register,                                 Address offset: 0x0B08 */
+  __IO uint32_t MACSTNR;             /*!< System time nanoseconds register,                             Address offset: 0x0B0C */
+  __IO uint32_t MACSTSUR;            /*!< System time seconds update register,                          Address offset: 0x0B10 */
+  __IO uint32_t MACSTNUR;            /*!< System time nanoseconds update register,                      Address offset: 0x0B14 */
+  __IO uint32_t MACTSAR;             /*!< Timestamp addend register,                                    Address offset: 0x0B18 */
+  uint32_t      RESERVED31;
+  __IO uint32_t MACTSSR;             /*!< Timestamp status register,                                    Address offset: 0x0B20 */
+  uint32_t      RESERVED32[3];
+  __IO uint32_t MACTXTSSNR;          /*!< Tx timestamp status nanoseconds register,                     Address offset: 0x0B30 */
+  __IO uint32_t MACTXTSSSR;          /*!< Tx timestamp status seconds register,                         Address offset: 0x0B34 */
+  uint32_t      RESERVED33[2];
+  __IO uint32_t MACACR;              /*!< Auxiliary control register,                                   Address offset: 0x0B40 */
+  uint32_t      RESERVED34;
+  __IO uint32_t MACATSNR;            /*!< Auxiliary timestamp nanoseconds register,                     Address offset: 0x0B48 */
+  __IO uint32_t MACATSSR;            /*!< Auxiliary timestamp seconds register,                         Address offset: 0x0B4C */
+  __IO uint32_t MACTSIACR;           /*!< Timestamp Ingress asymmetric correction register,             Address offset: 0x0B50 */
+  __IO uint32_t MACTSEACR;           /*!< Timestamp Egress asymmetric correction register,              Address offset: 0x0B54 */
+  __IO uint32_t MACTSICNR;           /*!< Timestamp Ingress correction nanosecond register,             Address offset: 0x0B58 */
+  __IO uint32_t MACTSECNR;           /*!< Timestamp Egress correction nanosecond register,              Address offset: 0x0B5C */
+  uint32_t      RESERVED35[2];
+  __IO uint32_t MACTSILR;            /*!< Timestamp Ingress Latency register,                           Address offset: 0x0B68 */
+  __IO uint32_t MACTSELR;            /*!< Timestamp Egress Latency register,                            Address offset: 0x0B6C */
+  __IO uint32_t MACPPSCR;            /*!< PPS control register,                                         Address offset: 0x0B70 */
+  uint32_t      RESERVED36[3];
+  __IO uint32_t MACPPSTTS0R;         /*!< PPS 0 target time seconds register,                           Address offset: 0x0B80 */
+  __IO uint32_t MACPPSTTN0R;         /*!< PPS 0 target time nanoseconds register,                       Address offset: 0x0B84 */
+  __IO uint32_t MACPPSI0R;           /*!< PPS 0 interval register,                                      Address offset: 0x0B88 */
+  __IO uint32_t MACPPSW0R;           /*!< PPS 0 width register,                                         Address offset: 0x0B8C */
+  __IO uint32_t MACPPSTTS1R;         /*!< PPS 1 target time seconds register,                           Address offset: 0x0B90 */
+  __IO uint32_t MACPPSTTN1R;         /*!< PPS 1 target time nanoseconds register,                       Address offset: 0x0B94 */
+  __IO uint32_t MACPPSI1R;           /*!< PPS 1 interval register,                                      Address offset: 0x0B98 */
+  __IO uint32_t MACPPSW1R;           /*!< PPS 1 width register,                                         Address offset: 0x0B9C */
+  uint32_t      RESERVED37[8];
+  __IO uint32_t MACPOCR;             /*!< PTP Offload control register,                                 Address offset: 0x0BC0 */
+  __IO uint32_t MACSPI0R;            /*!< PTP Source Port Identity 0 Register,                          Address offset: 0x0BC4 */
+  __IO uint32_t MACSPI1R;            /*!< PTP Source port identity 1 register,                          Address offset: 0x0BC8 */
+  __IO uint32_t MACSPI2R;            /*!< PTP Source port identity 2 register,                          Address offset: 0x0BCC */
+  __IO uint32_t MACLMIR;             /*!< Log message interval register,                                Address offset: 0x0BD0 */
+  uint32_t      RESERVED38[11];
+  __IO uint32_t MTLOMR;              /*!< Operating mode Register,                                      Address offset: 0x0C00 */
+  uint32_t      RESERVED39[7];
+  __IO uint32_t MTLISR;              /*!< Interrupt status Register,                                    Address offset: 0x0C20 */
+  uint32_t      RESERVED40[3];
+  __IO uint32_t MTLRXQDMAMR;         /*!< Rx Queue and DMA Channel Mapping Register,                    Address offset: 0x0C30 */
+  uint32_t      RESERVED41[3];
+  __IO uint32_t MTLTBSCR;            /*!< TBS control register,                                         Address offset: 0x0C40 */
+  uint32_t      RESERVED42[3];
+  __IO uint32_t MTLESTCR;            /*!< EST Control Register,                                         Address offset: 0x0C50 */
+  __IO uint32_t MTLESTECR;           /*!< EST Extended Control Register,                                Address offset: 0x0C54 */
+  __IO uint32_t MTLESTSR;            /*!< EST Status Register,                                          Address offset: 0x0C58 */
+  uint32_t      RESERVED43;
+  __IO uint32_t MTLESTSCHER;         /*!< EST Schedule Error Register,                                  Address offset: 0x0C60 */
+  __IO uint32_t MTLESTFSER;          /*!< EST Frame size Error Register,                                Address offset: 0x0C64 */
+  __IO uint32_t MTLESTFSCR;          /*!< EST Frame size Capture Register,                              Address offset: 0x0C68 */
+  uint32_t      RESERVED44;
+  __IO uint32_t MTLESTIER;           /*!< EST Interrupt Enable Register,                                Address offset: 0x0C70 */
+  uint32_t      RESERVED45[3];
+  __IO uint32_t MTLESTGCLCR;         /*!< EST Gate Control List Register,                               Address offset: 0x0C80 */
+  __IO uint32_t MTLESTGCLDR;         /*!< EST Gate Control List Data Register,                          Address offset: 0x0C84 */
+  uint32_t      RESERVED46[2];
+  __IO uint32_t MTLFPECSR;           /*!< FPE Frame Preemption Control Status Register,                 Address offset: 0x0C90 */
+  __IO uint32_t MTLFPEAR;            /*!< FPE Frame Preemption Advance Register,                        Address offset: 0x0C94 */
+  uint32_t      RESERVED47[26];
+  struct {
+  __IO uint32_t MTLTXQOMR;           /*!< Tx queue x operating mode Register,                           Address offset: 0x0D00 */
+  __IO uint32_t MTLTXQUR;            /*!< Tx queue x underflow register,                                Address offset: 0x0D04 */
+  __IO uint32_t MTLTXQDR;            /*!< Tx queue x debug register,                                    Address offset: 0x0D08 */
+  uint32_t      RESERVED48[1];
+  __IO uint32_t MTLTXQ1ECR;           /*!< Tx queue 1 ETS control Register,                              Address offset: 0x0D50 */
+  __IO uint32_t MTLTXQESR;           /*!< Tx queue x ETS status Register,                               Address offset: 0x0D14 */
+  __IO uint32_t MTLTXQQWR;           /*!< Tx queue x quantum weight register,                           Address offset: 0x0D18 */
+  __IO uint32_t MTLTXQ1SSCR;          /*!< Tx queue 1 send slope credit Register,                        Address offset: 0x0D5C */
+  __IO uint32_t MTLTXQ1HCR;           /*!< Tx Queue 1 hiCredit register,                                 Address offset: 0x0D60 */
+  __IO uint32_t MTLTXQ1LCR;           /*!< Tx queue 1 loCredit register,                                 Address offset: 0x0D64 */
+  uint32_t      RESERVED49[1];
+  __IO uint32_t MTLQICSR;           /*!< Queue 0 interrupt control status Register,                    Address offset: 0x0D2C */
+  __IO uint32_t MTLRXQOMR;          /*!< Rx queue x operating mode register,                           Address offset: 0x0D30 */
+  __IO uint32_t MTLRXQMPOCR;        /*!< Rx queue x missed packet and overflow counter register,       Address offset: 0x0D34 */
+  __IO uint32_t MTLRXQDR;           /*!< Rx queue x debug register,                                    Address offset: 0x0D38 */
+  __IO uint32_t MTLRXQCR;           /*!< Rx queue x control register,                                  Address offset: 0x0D3C */
+  } MTL_QUEUE[2];
+  uint32_t      RESERVED52[160];
+  __IO uint32_t DMAMR;               /*!< DMA mode register,                                            Address offset: 0x1000 */
+  __IO uint32_t DMASBMR;             /*!< System bus mode register,                                     Address offset: 0x1004 */
+  __IO uint32_t DMAISR;              /*!< Interrupt status register,                                    Address offset: 0x1008 */
+  __IO uint32_t DMADSR;              /*!< Debug status register,                                        Address offset: 0x100C */
+  uint32_t      RESERVED53[4];
+  __IO uint32_t DMAA4TXACR;          /*!< AXI4 transmit channel ACE control register,                   Address offset: 0x1020 */
+  __IO uint32_t DMAA4RXACR;          /*!< AXI4 receive channel ACE control register,                    Address offset: 0x1024 */
+  __IO uint32_t DMAA4DACR;           /*!< AXI4 descriptor ACE control register,                         Address offset: 0x1028 */
+  uint32_t      RESERVED54[5];
+  __IO uint32_t DMALPIEI;            /*!< AXI4 LPI Entry Interval register,                             Address offset: 0x1040 */
+  uint32_t      RESERVED55[3];
+  __IO uint32_t DMATBSCTRL0R;        /*!< DMA TBS control register 0,                                   Address offset: 0x1050 */
+  uint32_t      RESERVED56[37];
+  struct {
+  uint32_t      RESERVED57[6];
+  __IO uint32_t DMACCR;             /*!< Channel x control register,                                   Address offset: 0x1100 */
+  __IO uint32_t DMACTXCR;           /*!< Channel x transmit control register,                          Address offset: 0x1104 */
+  __IO uint32_t DMACRXCR;           /*!< Channel x receive control register,                           Address offset: 0x1108 */
+  uint32_t      RESERVED58[2];
+  __IO uint32_t DMACTXDLAR;         /*!< Channel x Tx descriptor list address register,                Address offset: 0x1114 */
+  uint32_t      RESERVED59;
+  __IO uint32_t DMACRXDLAR;         /*!< Channel x Rx descriptor list address register,                Address offset: 0x111C */
+  __IO uint32_t DMACTXDTPR;         /*!< Channel x Tx descriptor tail pointer register,                Address offset: 0x1120 */
+  uint32_t      RESERVED60;
+  __IO uint32_t DMACRXDTPR;         /*!< Channel x Rx descriptor tail pointer register,                Address offset: 0x1128 */
+  __IO uint32_t DMACTXRLR;          /*!< Channel x Tx descriptor ring length register,                 Address offset: 0x112C */
+  __IO uint32_t DMACRXRLR;          /*!< Channel x Rx descriptor ring length register,                 Address offset: 0x1130 */
+  __IO uint32_t DMACIER;            /*!< Channel x interrupt enable register,                          Address offset: 0x1134 */
+  __IO uint32_t DMACRXIWTR;         /*!< Channel x Rx interrupt watchdog timer register,               Address offset: 0x1138 */
+  __IO uint32_t DMACSFCSR;          /*!< Channel x slot function control status register,              Address offset: 0x113C */
+  uint32_t      RESERVED61;
+  __IO uint32_t DMACCATXDR;         /*!< Channel x current application transmit descriptor register,   Address offset: 0x1144 */
+  uint32_t      RESERVED62;
+  __IO uint32_t DMACCARXDR;         /*!< Channel x current application receive descriptor register,    Address offset: 0x114C */
+  uint32_t      RESERVED63;
+  __IO uint32_t DMACCATXBR;         /*!< Channel x current application transmit buffer register,       Address offset: 0x1154 */
+  uint32_t      RESERVED64;
+  __IO uint32_t DMACCARXBR;         /*!< Channel x current application receive buffer register,        Address offset: 0x115C */
+  __IO uint32_t DMACSR;             /*!< Channel x status register,                                    Address offset: 0x1160 */
+  __IO uint32_t DMACMFCR;            /*!< Channel x missed frame count register,                        Address offset: 0x1164 */
+  } DMA_CH[2];
+}ETH_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+typedef struct
+{
+  __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
+  __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
+  __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
+  __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
+  __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
+  __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
+  __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
+       uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x1C */
+  __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
+  __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
+  __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
+  __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
+  __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
+  __IO uint32_t SECCFGR2;       /*!< EXTI Security Configuration Register 2,          Address offset:   0x34 */
+  __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
+       uint32_t RESERVED2;      /*!< Reserved 2,                                      Address offset:   0x3C */
+  __IO uint32_t RTSR3;          /*!< EXTI Rising Trigger Selection Register 3,        Address offset:   0x40 */
+  __IO uint32_t FTSR3;          /*!< EXTI Falling Trigger Selection Register 3,       Address offset:   0x44 */
+  __IO uint32_t SWIER3;         /*!< EXTI Software Interrupt event Register 3,        Address offset:   0x48 */
+  __IO uint32_t RPR3;           /*!< EXTI Rising Pending Register 3,                  Address offset:   0x4C */
+  __IO uint32_t FPR3;           /*!< EXTI Falling Pending Register 3,                 Address offset:   0x50 */
+  __IO uint32_t SECCFGR3;       /*!< EXTI Security Configuration Register 3,          Address offset:   0x54 */
+  __IO uint32_t PRIVCFGR3;      /*!< EXTI Privilege Configuration Register 3,         Address offset:   0x58 */
+       uint32_t RESERVED3;      /*!< Reserved 3,                                      Address offset:   0x5C */
+  __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
+  __IO uint32_t LOCKR;          /*!< EXTI Lock Register,                              Address offset:   0x70 */
+       uint32_t RESERVED4[3];   /*!< Reserved 4,                                                0x74 -- 0x7C */
+  __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
+  __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
+       uint32_t RESERVED5[2];   /*!< Reserved 5,                                                0x88 -- 0x8C */
+  __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
+  __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
+       uint32_t RESERVED6[2];   /*!< Reserved 6,                                                0x98 -- 0x9C */
+  __IO uint32_t IMR3;           /*!< EXTI Interrupt Mask Register 3,                  Address offset:   0xA0 */
+  __IO uint32_t EMR3;           /*!< EXTI Event Mask Register 3,                      Address offset:   0xA4 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t CREL;           /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+ __IO uint32_t ENDN;           /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+ __IO uint32_t RESERVED1;      /*!< Reserved,                                                                        0x008 */
+ __IO uint32_t DBTP;           /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+ __IO uint32_t TEST;           /*!< FDCAN Test register,                                             Address offset: 0x010 */
+ __IO uint32_t RWD;            /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+ __IO uint32_t CCCR;           /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+ __IO uint32_t NBTP;           /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+ __IO uint32_t TSCC;           /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+ __IO uint32_t TSCV;           /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+ __IO uint32_t TOCC;           /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+ __IO uint32_t TOCV;           /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+ __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                                0x030 - 0x03C */
+ __IO uint32_t ECR;            /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+ __IO uint32_t PSR;            /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+ __IO uint32_t TDCR;           /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+ __IO uint32_t RESERVED3;      /*!< Reserved,                                                                        0x04C */
+ __IO uint32_t IR;             /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+ __IO uint32_t IE;             /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+ __IO uint32_t ILS;            /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+ __IO uint32_t ILE;            /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+ __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                                0x060 - 0x07C */
+ __IO uint32_t GFC;            /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+ __IO uint32_t SIDFC;          /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+ __IO uint32_t XIDFC;          /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+ __IO uint32_t RESERVED5;      /*!< Reserved,                                                                        0x08C */
+ __IO uint32_t XIDAM;          /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+ __IO uint32_t HPMS;           /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+ __IO uint32_t NDAT1;          /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+ __IO uint32_t NDAT2;          /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+ __IO uint32_t RXF0C;          /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+ __IO uint32_t RXF0S;          /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+ __IO uint32_t RXF0A;          /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+ __IO uint32_t RXBC;           /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+ __IO uint32_t RXF1C;          /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+ __IO uint32_t RXF1S;          /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+ __IO uint32_t RXF1A;          /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+ __IO uint32_t RXESC;          /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+ __IO uint32_t TXBC;           /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+ __IO uint32_t TXFQS;          /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+ __IO uint32_t TXESC;          /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+ __IO uint32_t TXBRP;          /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+ __IO uint32_t TXBAR;          /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+ __IO uint32_t TXBCR;          /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+ __IO uint32_t TXBTO;          /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+ __IO uint32_t TXBCF;          /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+ __IO uint32_t TXBTIE;         /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+ __IO uint32_t TXBCIE;         /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+ __IO uint32_t RESERVED6[2];   /*!< Reserved,                                                                0x0E8 - 0x0EC */
+ __IO uint32_t TXEFC;          /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+ __IO uint32_t TXEFS;          /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+ __IO uint32_t TXEFA;          /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+ __IO uint32_t RESERVED7;      /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;         /*!< TT Trigger Memory Configuration register,        Address offset: 0x100 */
+  __IO uint32_t TTRMC;         /*!< TT Reference Message Configuration register,     Address offset: 0x104 */
+  __IO uint32_t TTOCF;         /*!< TT Operation Configuration register,             Address offset: 0x108 */
+  __IO uint32_t TTMLM;         /*!< TT Matrix Limits register,                       Address offset: 0x10C */
+  __IO uint32_t TURCF;         /*!< TUR Configuration register,                      Address offset: 0x110 */
+  __IO uint32_t TTOCN;         /*!< TT Operation Control register,                   Address offset: 0x114 */
+  __IO uint32_t TTGTP;         /*!< TT Global Time Preset register,                  Address offset: 0x118 */
+  __IO uint32_t TTTMK;         /*!< TT Time Mark register,                          Address offset: 0x11C */
+  __IO uint32_t TTIR;          /*!< TT Interrupt register,                           Address offset: 0x120 */
+  __IO uint32_t TTIE;          /*!< TT Interrupt Enable register,                    Address offset: 0x124 */
+  __IO uint32_t TTILS;         /*!< TT Interrupt Line Select register,               Address offset: 0x128 */
+  __IO uint32_t TTOST;         /*!< TT Operation Status register,                    Address offset: 0x12C */
+  __IO uint32_t TURNA;         /*!< TT TUR Numerator Actual register,                Address offset: 0x130 */
+  __IO uint32_t TTLGT;         /*!< TT Local and Global Time register,               Address offset: 0x134 */
+  __IO uint32_t TTCTC;         /*!< TT Cycle Time and Count register,                Address offset: 0x138 */
+  __IO uint32_t TTCPT;         /*!< TT Capture Time register,                        Address offset: 0x13C */
+  __IO uint32_t TTCSM;         /*!< TT Cycle Sync Mark register,                     Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111];/*!< Reserved,                                                0x144 - 0x2FC */
+  __IO uint32_t TTTS;          /*!< TT Trigger Select register,                      Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;          /*!< Clock Calibration Unit Core Release register,    Address offset: 0x00 */
+  __IO uint32_t CCFG;          /*!< Calibration Configuration register,              Address offset: 0x04 */
+  __IO uint32_t CSTAT;         /*!< Calibration Status register,                     Address offset: 0x08 */
+  __IO uint32_t CWD;           /*!< Calibration Watchdog register,                   Address offset: 0x0C */
+  __IO uint32_t IR;            /*!< CCU Interrupt register,                          Address offset: 0x10 */
+  __IO uint32_t IE;            /*!< CCU Interrupt Enable register,                   Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+/**
+ * @brief FD Controller Area Network Configuration
+ */
+typedef struct
+{
+ __IO uint32_t CKDIV;          /*!< FDCAN clock divider register,            Address offset: 0x100 + 0x000 */
+      uint32_t RESERVED1[128]; /*!< Reserved,                                0x100 + 0x004 - 0x100 + 0x200 */
+ __IO uint32_t OPTR;           /*!< FDCAN option register,                   Address offset: 0x100 + 0x204 */
+      uint32_t RESERVED2[58];  /*!< Reserved,                                0x100 + 0x208 - 0x100 + 0x2EC */
+ __IO uint32_t HWCFG;          /*!< FDCAN hardware configuration register,   Address offset: 0x100 + 0x2F0 */
+ __IO uint32_t VERR;           /*!< FDCAN IP version register,               Address offset: 0x100 + 0x2F4 */
+ __IO uint32_t IPIDR;          /*!< FDCAN IP ID register,                    Address offset: 0x100 + 0x2F8 */
+ __IO uint32_t SIDR;           /*!< FDCAN size ID register,                  Address offset: 0x100 + 0x2FC */
+} FDCAN_Config_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1
+  */
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+typedef struct
+{
+  __IO uint32_t SDCR[2];         /*!< SDRAM device 1/2 control register                      Address offset: 0x140-0x144 */
+  __IO uint32_t SDTR;            /*!< SDRAM timing register                                  Address offset: 0x148 */
+       uint32_t RESERVED0;       /*!< Reserved                                               Address offset: 0x14C */
+  __IO uint32_t SDCMR;           /*!< SDRAM command mode register                            Address offset: 0x150 */
+  __IO uint32_t SDRTR;           /*!< SDRAM refresh timer register                           Address offset: 0x154 */
+  __IO uint32_t SDSR;            /*!< SDRAM status register                                  Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+typedef struct
+{
+  __IO uint32_t PCR;             /*!< NAND Flash Programmable control register               Address offset: 0x080 */
+  __IO uint32_t SR;              /*!< FMC status register                                    Address offset: 0x084 */
+  __IO uint32_t PMEM;            /*!< Common memory space timing register                    Address offset: 0x088 */
+  __IO uint32_t PATT;            /*!< Attribute memory space timing registers                Address offset: 0x08C */
+  __IO uint32_t HPR;             /*!< FMC Hamming parity result registers                    Address offset: 0x090 */
+  __IO uint32_t HECCR;           /*!< FMC Hamming code ECC result register                   Address offset: 0x094 */
+       uint32_t RESERVED0[58];   /*!< Reserved                                               Address offset: 0x098-0x17C */
+  __IO uint32_t IER;             /*!< FMC NAND Interrupt Enable Register                     Address offset: 0x180 */
+  __IO uint32_t ISR;             /*!< FMC Controller Interrupt Status Register               Address offset: 0x184 */
+  __IO uint32_t ICR;             /*!< FMC NAND Controller Interrupt Clear Register           Address offset: 0x188 */
+       uint32_t RESERVED1[29];   /*!< Reserved                                               Address offset: 0x18C-0x1FC */
+  __IO uint32_t CSQCR;           /*!< FMC NAND Command Sequencer Control Register            Address offset: 0x200 */
+  __IO uint32_t CSQCFGR1;        /*!< FMC NAND Command Sequencer Configuration Register 1    Address offset: 0x204 */
+  __IO uint32_t CSQCFGR2;        /*!< FMC NAND Command Sequencer Configuration Register 2    Address offset: 0x208 */
+  __IO uint32_t CSQCFGR3;        /*!< FMC NAND sequencer configuration register 3            Address offset: 0x20C */
+  __IO uint32_t CSQAR1;          /*!< FMC NAND Command Sequencer Address Register 1          Address offset: 0x210 */
+  __IO uint32_t CSQAR2;          /*!< FMC NAND Command Sequencer Address Register 2          Address offset: 0x214 */
+       uint32_t RESERVED2[2];    /*!< Reserved                                               Address offset: 0x218-0x21C */
+  __IO uint32_t CSQIER;          /*!< FMC NAND Command Sequencer Interrupt Enable Register   Address offset: 0x220 */
+  __IO uint32_t CSQISR;          /*!< FMC NAND Command Sequencer Interrupt Status Register   Address offset: 0x224 */
+  __IO uint32_t CSQICR;          /*!< FMC NAND Command Sequencer Interrupt Clear Register    Address offset: 0x228 */
+       uint32_t RESERVED3;       /*!< Reserved                                               Address offset: 0x22C */
+  __IO uint32_t CSQEMSR;         /*!< FMC Command Sequencer Error Mapping Status register    Address offset: 0x230 */
+       uint32_t RESERVED4[7];    /*!< Reserved                                               Address offset: 0x234-0x24C */
+  __IO uint32_t BCHIER;          /*!< FMC BCH Interrupt enable register                      Address offset: 0x250 */
+  __IO uint32_t BCHISR;          /*!< FMC BCH Interrupt and Status Register                  Address offset: 0x254 */
+  __IO uint32_t BCHICR;          /*!< FMC BCH Interrupt Clear Register                       Address offset: 0x258 */
+       uint32_t RESERVED5;       /*!< Reserved                                               Address offset: 0x25C */
+  __IO uint32_t BCHPBR1;         /*!< FMC BCH Parity Bits Register 1                         Address offset: 0x260 */
+  __IO uint32_t BCHPBR2;         /*!< FMC BCH Parity Bits Register 2                         Address offset: 0x264 */
+  __IO uint32_t BCHPBR3;         /*!< FMC BCH Parity Bits Register 3                         Address offset: 0x268 */
+  __IO uint32_t BCHPBR4;         /*!< FMC BCH Parity Bits Register 4                         Address offset: 0x26C */
+       uint32_t RESERVED6[3];    /*!< Reserved                                               Address offset: 0x270-0x278 */
+  __IO uint32_t BCHDSR0;         /*!< FMC BCH Decoder Status register 0                      Address offset: 0x27C */
+  __IO uint32_t BCHDSR1;         /*!< FMC BCH Decoder Status register for bank 1             Address offset: 0x280 */
+  __IO uint32_t BCHDSR2;         /*!< FMC BCH Decoder Status register for bank 2             Address offset: 0x284 */
+  __IO uint32_t BCHDSR3;         /*!< FMC BCH Decoder Status register for bank 3             Address offset: 0x288 */
+  __IO uint32_t BCHDSR4;         /*!< FMC BCH Decoder Status register for bank 4             Address offset: 0x28C */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Common
+  */
+typedef struct{
+  __IO uint32_t CFGR;            /*!< FMC common configuration register                      Address offset: 0x020 */
+} FMC_Common_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+typedef struct
+{
+  __IO uint32_t MODER;         /*!< GPIO port mode register,                     Address offset: 0x00      */
+  __IO uint32_t OTYPER;        /*!< GPIO port output type register,              Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;       /*!< GPIO port output speed register,             Address offset: 0x08      */
+  __IO uint32_t PUPDR;         /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
+  __IO uint32_t IDR;           /*!< GPIO port input data register,               Address offset: 0x10      */
+  __IO uint32_t ODR;           /*!< GPIO port output data register,              Address offset: 0x14      */
+  __IO uint32_t BSRR;          /*!< GPIO port bit set/reset  register,           Address offset: 0x18      */
+  __IO uint32_t LCKR;          /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
+  __IO uint32_t AFR[2];        /*!< GPIO alternate function registers,           Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;           /*!< GPIO bit reset register,                     Address offset: 0x28      */
+       uint32_t RESERVED0;     /*!< Reserved,                                    Address offset: 0x2C      */
+  __IO uint32_t SECCFGR;       /*!< GPIO port secure configuration register,     Address offset: 0x30      */
+  __IO uint32_t PRIVCFGR;      /*!< GPIO port privileged configuration register, Address offset: 0x34      */
+  __IO uint32_t RCFGLOCKR;     /*!< GPIO port resource configuration register,   Address offset: 0x38      */
+       uint32_t RESERVED1;     /*!< Reserved,                                    Address offset: 0x3C      */
+  __IO uint32_t DELAYR[2];     /*!< GPIO port delay register,                    Address offset: 0x40-0x44 */
+  __IO uint32_t ADVCFGR[2];    /*!< GPIO port advanced configuration register,   Address offset: 0x48-0x4C */
+} GPIO_TypeDef;
+
+/**
+  * @brief GFXMMU
+  */
+typedef struct
+{
+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
+       uint32_t RESERVED0;       /*!< Reserved0,                                         Address offset: 0x0C */
+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
+  __IO uint32_t DAR;             /*!< GFXMMU default alpha register,                     Address offset: 0x14 */
+       uint32_t RESERVED1[2];    /*!< Reserved1,                                 Address offset: 0x18 to 0x1C */
+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                 Address offset: 0x30 to 0xFFC */
+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                      Address offset: 0x1000 to 0x2FFC
+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
+} GFXMMU_TypeDef;
+
+/**
+  * @brief GFXTIM
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< GFXTIM configuration register,                    Address offset: 0x00 */
+  __IO uint32_t CGCR;          /*!< GFXTIM clock generator configuration register,    Address offset: 0x04 */
+  __IO uint32_t TCR;           /*!< GFXTIM timers configuration register,             Address offset: 0x08 */
+  __IO uint32_t TDR;           /*!< GFXTIM timers disable register,                   Address offset: 0x0C */
+  __IO uint32_t EVCR;          /*!< GFXTIM events control register,                   Address offset: 0x10 */
+  __IO uint32_t EVSR;          /*!< GFXTIM events selection register,                 Address offset: 0x14 */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                         Address offset: 0x18-0x1C */
+  __IO uint32_t WDGTCR;        /*!< GFXTIM watchdog timer configuration register,     Address offset: 0x20 */
+  uint32_t RESERVED2[3];       /*!< Reserved,                                         Address offset: 0x24-0x2C */
+  __IO uint32_t ISR;           /*!< GFXTIM interrupt status register,                 Address offset: 0x30 */
+  __IO uint32_t ICR;           /*!< GFXTIM interrupt clear register,                  Address offset: 0x34 */
+  __IO uint32_t IER;           /*!< GFXTIM interrupt enable register,                 Address offset: 0x38 */
+  __IO uint32_t TSR;           /*!< GFXTIM timers status register,                    Address offset: 0x3C */
+  __IO uint32_t LCCRR;         /*!< GFXTIM line clock counter reload register,        Address offset: 0x40 */
+  __IO uint32_t FCCRR;         /*!< GFXTIM frame clock counter reload register,       Address offset: 0x44 */
+  uint32_t RESERVED3[2];       /*!< Reserved,                                         Address offset: 0x48-0x4C */
+  __IO uint32_t ATR;           /*!< GFXTIM absolute time register,                    Address offset: 0x50 */
+  __IO uint32_t AFCR;          /*!< GFXTIM absolute frame counter register,           Address offset: 0x54 */
+  __IO uint32_t ALCR;          /*!< GFXTIM absolute line counter register,            Address offset: 0x58 */
+  uint32_t RESERVED4[1];       /*!< Reserved,                                         Address offset: 0x5C */
+  __IO uint32_t AFCC1R;        /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
+  uint32_t RESERVED5[3];       /*!< Reserved,                                         Address offset: 0x64-0X6C */
+  __IO uint32_t ALCC1R;        /*!< GFXTIM absolute line counter compare 1 register,  Address offset: 0x70 */
+  __IO uint32_t ALCC2R;        /*!< GFXTIM absolute line counter compare 2 register,  Address offset: 0x74 */
+  uint32_t RESERVED6[2];       /*!< Reserved,                                         Address offset: 0x78-0X7C */
+  __IO uint32_t RFC1R;         /*!< GFXTIM relative frame counter 1 register,         Address offset: 0x80 */
+  __IO uint32_t RFC1RR;        /*!< GFXTIM relative frame counter 1 reload register,  Address offset: 0x84 */
+  __IO uint32_t RFC2R;         /*!< GFXTIM relative frame counter 2 register,         Address offset: 0x88 */
+  __IO uint32_t RFC2RR;        /*!< GFXTIM relative frame counter 2 reload register,  Address offset: 0x8C */
+  uint32_t RESERVED7[4];       /*!< Reserved,                                         Address offset: 0x90-0X9C */
+  __IO uint32_t WDGCR;         /*!< GFXTIM watchdog counter register,                 Address offset: 0xA0 */
+  __IO uint32_t WDGRR;         /*!< GFXTIM watchdog reload register,                  Address offset: 0xA4 */
+  __IO uint32_t WDGPAR;        /*!< GFXTIM watchdog pre-alarm register,               Address offset: 0xA8 */
+  uint32_t RESERVED8[209];     /*!< Reserved,                                         Address offset: 0xAC-0X3EC */
+  __IO uint32_t HWCFGR;        /*!< GFXTIM HW configuration register,                 Address offset: 0x3F0 */
+  __IO uint32_t VERR;          /*!< GFXTIM version register,                          Address offset: 0x3F4 */
+  __IO uint32_t IPIDR;         /*!< GFXTIM identification register,                   Address offset: 0x3F8 */
+  __IO uint32_t SIDR;          /*!< GFXTIM size identification register,              Address offset: 0x3FC */
+} GFXTIM_TypeDef;
+
+/**
+  * @brief HASH
+  */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
+} HASH_TypeDef;
+
+/**
+  * @brief HASH_DIGEST
+  */
+typedef struct
+{
+  __IO uint32_t HR[16];           /*!< HASH digest registers,          Address offset: 0x310-0x34C */
+} HASH_DIGEST_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Improved Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
+  uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
+  __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
+  __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
+  __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
+  __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
+  __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
+  __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
+  __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
+  uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
+  __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
+  uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
+  __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
+  __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
+  __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
+  uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
+  __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
+  __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
+  uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
+  __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
+  __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
+  uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
+  __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
+  __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
+  __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
+  uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
+  __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
+  __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
+  __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
+  __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
+  __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
+  __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
+} I3C_TypeDef;
+
+/**
+  * @brief Illegal Access Controller
+  */
+typedef struct
+{
+  __IO uint32_t IER[5];         /*!< Interrupt Enable register,                 Address offset: 0x000       */
+  uint32_t      RESERVED1[27];  /*!< Reserved,                                  Address offset: 0x014-0x07C */
+  __IO uint32_t ISR[5];         /*!< Interrupt Status register,                 Address offset: 0x080       */
+  uint32_t      RESERVED2[27];  /*!< Reserved,                                  Address offset: 0x094-0x0FC */
+  __IO uint32_t ICR[5];         /*!< Interrupt Clear register,                  Address offset: 0x100       */
+} IAC_TypeDef;
+
+/**
+  * @brief Instruction Cache
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
+  __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
+  __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
+  __IO uint32_t FCR;            /*!< ICACHE flag clear register,             Address offset: 0x0C */
+  __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
+  __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
+} ICACHE_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t KR;              /*!< IWDG key register                    Address offset: 0x000 */
+  __IO uint32_t PR;              /*!< IWDG prescaler register              Address offset: 0x004 */
+  __IO uint32_t RLR;             /*!< IWDG reload register                 Address offset: 0x008 */
+  __IO uint32_t SR;              /*!< IWDG status register                 Address offset: 0x00C */
+  __IO uint32_t WINR;            /*!< IWDG window register                 Address offset: 0x010 */
+  __IO uint32_t EWCR;            /*!< IWDG early wakeup interrupt register Address offset: 0x014 */
+  __IO uint32_t ICR;             /*!< IWDG interrupt clear register        Address offset: 0x018 */
+} IWDG_TypeDef;
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+
+/**
+  * @brief LCD-TFT Display Controller (LTDC)
+  */
+typedef struct
+{
+       uint32_t RESERVED0[2];   /*!< Reserved Address offset: 0x00-0x04 */
+  __IO uint32_t SSCR;           /*!< LTDC synchronization size configuration register Address offset: 0x8 */
+  __IO uint32_t BPCR;           /*!< LTDC back porch configuration register Address offset: 0xc */
+  __IO uint32_t AWCR;           /*!< LTDC active width configuration register Address offset: 0x10 */
+  __IO uint32_t TWCR;           /*!< LTDC total width configuration register Address offset: 0x14 */
+  __IO uint32_t GCR;            /*!< LTDC global control register Address offset: 0x18 */
+       uint32_t RESERVED1[2];   /*!< Reserved Address offset: */
+  __IO uint32_t SRCR;           /*!< LTDC shadow reload configuration register Address offset: 0x24 */
+  __IO uint32_t GCCR;           /*!< LTDC gamma correction configuration register Address offset: 0x28 */
+  __IO uint32_t BCCR;           /*!< LTDC background color configuration register Address offset: 0x2c */
+       uint32_t RESERVED2;      /*!< Reserved Address offset: 0x30 */
+  __IO uint32_t IER;            /*!< LTDC interrupt enable register Address offset: 0x34 */
+  __IO uint32_t ISR;            /*!< LTDC interrupt status register Address offset: 0x38 */
+  __IO uint32_t ICR;            /*!< LTDC Interrupt Clear Register Address offset: 0x3c */
+  __IO uint32_t LIPCR;          /*!< LTDC line interrupt position configuration register Address offset: 0x40 */
+  __IO uint32_t CPSR;           /*!< LTDC current position status register Address offset: 0x44 */
+  __IO uint32_t CDSR;           /*!< LTDC current display status register Address offset: 0x48 */
+       uint32_t RESERVED3[5];   /*!< Reserved Address offset: 0x4c */
+  __IO uint32_t EDCR;           /*!< LTDC external display control register Address offset: 0x60 */
+  __IO uint32_t IER2;           /*!< LTDC interrupt enable register 2 Address offset: 0x64 */
+  __IO uint32_t ISR2;           /*!< LTDC interrupt status register 2 Address offset: 0x68 */
+  __IO uint32_t ICR2;           /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */
+  __IO uint32_t LIPCR2;         /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */
+       uint32_t RESERVED4;      /*!< Reserved Address offset: 0x74 */
+  __IO uint32_t ECRCR;          /*!< LTDC expected CRC register Address offset: 0x78 */
+  __IO uint32_t CCRCR;          /*!< LTDC computed CRC register Address offset: 0x7c */
+  __IO uint32_t RB0AR;          /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */
+  __IO uint32_t RB1AR;          /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */
+  __IO uint32_t RBPR;           /*!< LTDC rotation buffer pitch register Address offset: 0x88 */
+  __IO uint32_t RIFCR;          /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */
+  __IO uint32_t FUTR;           /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller (LTDC)
+  */
+typedef struct
+{
+  __IO uint32_t C0R;          /*!< LTDC layer x configuration 0 register Address offset: 0x100 */
+  __IO uint32_t C1R;          /*!< LTDC layer x configuration 1 register Address offset: 0x104 */
+  __IO uint32_t RCR;          /*!< LTDC layer x reload control register Address offset: 0x108 */
+  __IO uint32_t CR;           /*!< LTDC layer x control register Address offset: 0x10c */
+  __IO uint32_t WHPCR;        /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */
+  __IO uint32_t WVPCR;        /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */
+  __IO uint32_t CKCR;         /*!< LTDC layer x color keying configuration register Address offset: 0x118 */
+  __IO uint32_t PFCR;         /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */
+  __IO uint32_t CACR;         /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */
+  __IO uint32_t DCCR;         /*!< LTDC layer x default color configuration register Address offset: 0x124 */
+  __IO uint32_t BFCR;         /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */
+  __IO uint32_t BLCR;         /*!< LTDC layer x burst length configuration register Address offset: 0x12c */
+  __IO uint32_t PCR;          /*!< LTDC layer x planar configuration register Address offset: 0x130 */
+  __IO uint32_t CFBAR;        /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */
+  __IO uint32_t CFBLR;        /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */
+  __IO uint32_t CFBLNR;       /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */
+  __IO uint32_t AFBA0R;       /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */
+  __IO uint32_t AFBA1R;       /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */
+  __IO uint32_t AFBLR;        /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */
+  __IO uint32_t AFBLNR;       /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */
+  __IO uint32_t CLUTWR;       /*!< LTDC layer x CLUT write register Address offset: 0x150 */
+  __IO uint32_t SISR;         /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */
+  __IO uint32_t SOSR;         /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */
+  __IO uint32_t SVSFR;        /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */
+  __IO uint32_t SVSPR;        /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */
+  __IO uint32_t SHSFR;        /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */
+  __IO uint32_t SHSPR;        /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */
+  __IO uint32_t CYR0R;        /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */
+  __IO uint32_t CYR1R;        /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */
+  __IO uint32_t FPF0R;        /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */
+  __IO uint32_t FPF1R;        /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */
+} LTDC_Layer_TypeDef;
+
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
+  __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
+  __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
+  __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
+  __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
+  __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
+  __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
+  __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
+  __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x20 */
+  __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
+  __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
+  __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
+  __IO uint32_t RESERVED2;      /*!< Reserved,                               Address offset: 0x30 */
+  __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Memory Cipher Engine (MCE)
+  */
+typedef struct
+{
+  __IO uint32_t REGCR;            /*!< MCE region configuration register,             Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */
+  __IO uint32_t SADDR;            /*!< MCE region start address register,             Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */
+  __IO uint32_t EADDR;            /*!< MCE region end address register,               Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */
+} MCE_Region_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCCFGR;           /*!< MCE cipher context configuration register,     Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCNR0;            /*!< MCE cipher context nonce register 0,           Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCNR1;            /*!< MCE cipher context nonce register 1,           Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR0;          /*!< MCE cipher context key register 0,             Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR1;          /*!< MCE cipher context key register 1,             Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR2;          /*!< MCE cipher context key register 2,             Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR3;          /*!< MCE cipher context key register 3,             Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */
+} MCE_Context_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< MCE configuration register,                           Address offset: 0x000       */
+  __IO uint32_t SR;               /*!< MCE status register,                                  Address offset: 0x004       */
+  __IO uint32_t IASR;             /*!< MCE illegal access status register,                   Address offset: 0x008       */
+  __IO uint32_t IACR;             /*!< MCE illegal access clear register,                    Address offset: 0x00C       */
+  __IO uint32_t IAIER;            /*!< MCE illegal access interrupt enable register,         Address offset: 0x010       */
+  uint32_t RESERVED0[4];          /*!< Reserved,                                             Address offset: 0x014-0x20  */
+  __IO uint32_t IADDR;            /*!< MCE illegal address register,                         Address offset: 0x024       */
+  uint32_t RESERVED1[118];        /*!< Reserved,                                             Address offset: 0x028-0x1FC */
+  __IO uint32_t MKEYR0;           /*!< MCE master key register 0,                            Address offset: 0x200       */
+  __IO uint32_t MKEYR1;           /*!< MCE master key register 1,                            Address offset: 0x204       */
+  __IO uint32_t MKEYR2;           /*!< MCE master key register 2,                            Address offset: 0x208       */
+  __IO uint32_t MKEYR3;           /*!< MCE master key register 3,                            Address offset: 0x20C       */
+  __IO uint32_t MKEYR4;           /*!< MCE master key register 4,                            Address offset: 0x210       */
+  __IO uint32_t MKEYR5;           /*!< MCE master key register 5,                            Address offset: 0x214       */
+  __IO uint32_t MKEYR6;           /*!< MCE master key register 6,                            Address offset: 0x218       */
+  __IO uint32_t MKEYR7;           /*!< MCE master key register 7,                            Address offset: 0x21C       */
+  __IO uint32_t FMKEYR0;          /*!< MCE fast master key register 0,                       Address offset: 0x220       */
+  __IO uint32_t FMKEYR1;          /*!< MCE fast master key register 1,                       Address offset: 0x224       */
+  __IO uint32_t FMKEYR2;          /*!< MCE fast master key register 2,                       Address offset: 0x228       */
+  __IO uint32_t FMKEYR3;          /*!< MCE fast master key register 3,                       Address offset: 0x22C       */
+  __IO uint32_t FMKEYR4;          /*!< MCE fast master key register 4,                       Address offset: 0x230       */
+  __IO uint32_t FMKEYR5;          /*!< MCE fast master key register 5,                       Address offset: 0x234       */
+  __IO uint32_t FMKEYR6;          /*!< MCE fast master key register 6,                       Address offset: 0x238       */
+  __IO uint32_t FMKEYR7;          /*!< MCE fast master key register 7,                       Address offset: 0x23C       */
+} MCE_TypeDef;
+
+
+
+/**
+  * @brief ADF
+  */
+typedef struct
+{
+  __IO uint32_t GCR;            /*!< MDF Global Control register,             Address offset: 0x00  */
+  __IO uint32_t CKGCR;          /*!< MDF Clock Generator Control Register,    Address offset: 0x04  */
+  uint32_t      RESERVED1[6];   /*!< Reserved, 0x08-0x1C                                            */
+  __IO uint32_t OR;             /*!< MDF  Option Register,                    Address offset: 0x20  */
+} MDF_TypeDef;
+
+/**
+  * @brief ADF filter
+  */
+typedef struct
+{
+ __IO uint32_t SITFCR;         /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
+ __IO uint32_t BSMXCR;         /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
+ __IO uint32_t DFLTCR;         /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
+ __IO uint32_t DFLTCICR;       /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
+ __IO uint32_t DFLTRSFR;       /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
+ __IO uint32_t DFLTINTR;       /*!< MDF Integrator Configuration Register,          Address offset: 0x94 */
+ __IO uint32_t OLDCR;          /*!< MDF Out-Of Limit Detector Control Register,     Address offset: 0x98 */
+ __IO uint32_t OLDTHLR;        /*!< MDF OLD Threshold Low Register,                 Address offset: 0x9C */
+ __IO uint32_t OLDTHHR;        /*!< MDF OLD Threshold High Register,                Address offset: 0xA0 */
+ __IO uint32_t DLYCR;          /*!< MDF Delay control Register,                     Address offset: 0xA4 */
+ __IO uint32_t SCDCR;          /*!< MDF short circuit detector control Register,    Address offset: 0xA8 */
+ __IO uint32_t DFLTIER;        /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
+ __IO uint32_t DFLTISR;        /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
+ __IO uint32_t OECCR;          /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
+ __IO uint32_t SADCR;          /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
+ __IO uint32_t SADCFGR;        /*!< MDF SAD configuration register,                 Address offset: 0xBC */
+ __IO uint32_t SADSDLVR;       /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
+ __IO uint32_t SADANLVR;       /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
+ uint32_t     RESERVED1[9];    /*!< Reserved, 0xC8-0xE8                                                  */
+ __IO uint32_t SNPSDR;         /*!< MDF Snapshot Data Register,                     Address offset: 0xEC */
+ __IO uint32_t DFLTDR;         /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
+} MDF_Filter_TypeDef;
+
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+/**
+  * @brief PSSI
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< PSSI control register,                 Address offset: 0x000 */
+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
+} PSSI_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+typedef struct
+{
+  __IO uint32_t CR1;             /*!< PWR Control register 1                           Address offset: 0x000 */
+  __IO uint32_t CR2;             /*!< PWR Control Register 2                           Address offset: 0x004 */
+  __IO uint32_t CR3;             /*!< PWR Control Register 3                           Address offset: 0x008 */
+  __IO uint32_t CR4;             /*!< PWR Control Register 4                           Address offset: 0x00C */
+       uint32_t RESERVED0[4];    /*!< Reserved                                         Address offset: 0x010-0x01C */
+  __IO uint32_t VOSCR;           /*!< PWR Voltage scaling control register             Address offset: 0x020 */
+  __IO uint32_t BDCR1;           /*!< PWR Backup domain control register 1             Address offset: 0x024 */
+  __IO uint32_t BDCR2;           /*!< PWR Backup domain control register 2             Address offset: 0x028 */
+  __IO uint32_t DBPCR;           /*!< PWR Disable backup protection control register   Address offset: 0x02C */
+  __IO uint32_t CPUCR;           /*!< PWR CPU control register                         Address offset: 0x030 */
+  __IO uint32_t SVMCR1;          /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */
+  __IO uint32_t SVMCR2;          /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */
+  __IO uint32_t SVMCR3;          /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */
+       uint32_t RESERVED1[4];    /*!< Reserved                                         Address offset: 0x040-0x04C */
+  __IO uint32_t WKUPCR;          /*!< PWR Wakeup control register 1                    Address offset: 0x050 */
+  __IO uint32_t WKUPSR;          /*!< PWR Wakeup control register 2                    Address offset: 0x054 */
+  __IO uint32_t WKUPEPR;         /*!< PWR Wakeup control register 3                    Address offset: 0x058 */
+       uint32_t RESERVED2[5];    /*!< Reserved                                         Address offset: 0x05C-0x06C */
+  __IO uint32_t SECCFGR;         /*!< PWR Security configuration register              Address offset: 0x070 */
+  __IO uint32_t PRIVCFGR;        /*!< PWR Privilege configuration register             Address offset: 0x074 */
+} PWR_TypeDef;
+
+/**
+  * @brief PKA
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< PKA control register,             Address offset: 0x00 */
+  __IO uint32_t SR;            /*!< PKA status register,              Address offset: 0x04 */
+  __IO uint32_t CLRFR;         /*!< PKA clear flag register,          Address offset: 0x08 */
+  uint32_t Reserved[253];      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
+  __IO uint32_t RAM[1334];     /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
+} PKA_TypeDef;
+
+/**
+  * @brief RAMs configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control Register,                    Address offset: 0x00 */
+  __IO uint32_t IER;         /*!< Interrupt Enable Register,           Address offset: 0x04 */
+  __IO uint32_t ISR;         /*!< Interrupt Status Register,           Address offset: 0x08 */
+  __IO uint32_t ESEAR;       /*!< ECC Single Error Address Register,   Address offset: 0x0C */
+  __IO uint32_t EDEAR;       /*!< ECC Double Error Address Register,   Address offset: 0x10 */
+  __IO uint32_t ICR;         /*!< Interrupt Clear Register,            Address offset: 0x14 */
+  uint32_t      RESERVED[3]; /*!< Reserved,                       Address offset: 0x18-0x20 */
+  __IO uint32_t ECCKEYR;     /*!< RAM ECC Key Register,                Address offset: 0x24 */
+  __IO uint32_t ERKEYR;      /*!< RAM Erase Key Register,              Address offset: 0x28 */
+}RAMCFG_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< RCC control register                                           Address offset: 0x0000 */
+  __IO uint32_t SR;               /*!< RCC status register                                            Address offset: 0x0004 */
+  __IO uint32_t STOPCR;           /*!< RCC Stop mode control register                                 Address offset: 0x0008 */
+       uint32_t RESERVED0[5];     /*!< Reserved                                                       Address offset: 0x000C-0x001C */
+  __IO uint32_t CFGR1;            /*!< RCC configuration register 1                                   Address offset: 0x0020 */
+  __IO uint32_t CFGR2;            /*!< RCC configuration register 2                                   Address offset: 0x0024 */
+       uint32_t RESERVED1;        /*!< Reserved                                                       Address offset: 0x0028 */
+  __IO uint32_t BDCR;             /*!< RCC backup domain protection register                          Address offset: 0x002C */
+  __IO uint32_t HWRSR;            /*!< RCC reset status register for hardware                         Address offset: 0x0030 */
+  __IO uint32_t RSR;              /*!< RCC reset register                                             Address offset: 0x0034 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                                       Address offset: 0x0038-0x003C */
+  __IO uint32_t LSECFGR;          /*!< RCC LSE configuration register                                 Address offset: 0x0040 */
+  __IO uint32_t MSICFGR;          /*!< RCC MSI configuration register                                 Address offset: 0x0044 */
+  __IO uint32_t HSICFGR;          /*!< RCC HSI configuration register                                 Address offset: 0x0048 */
+  __IO uint32_t HSIMCR;           /*!< RCC HSI Monitor control register                               Address offset: 0x004C */
+  __IO uint32_t HSIMSR;           /*!< RCC HSI Monitor status register                                Address offset: 0x0050 */
+  __IO uint32_t HSECFGR;          /*!< RCC HSE configuration register                                 Address offset: 0x0054 */
+       uint32_t RESERVED3[10];    /*!< Reserved                                                       Address offset: 0x0058-0x007C */
+  __IO uint32_t PLL1CFGR1;        /*!< RCC PLL1 configuration register 1                              Address offset: 0x0080 */
+  __IO uint32_t PLL1CFGR2;        /*!< RCC PLL1 configuration register 2                              Address offset: 0x0084 */
+  __IO uint32_t PLL1CFGR3;        /*!< RCC PLL1 configuration register 3                              Address offset: 0x0088 */
+       uint32_t RESERVED4;        /*!< Reserved                                                       Address offset: 0x008C */
+  __IO uint32_t PLL2CFGR1;        /*!< RCC PLL2 configuration register 1                              Address offset: 0x0090 */
+  __IO uint32_t PLL2CFGR2;        /*!< RCC PLL2 configuration register 2                              Address offset: 0x0094 */
+  __IO uint32_t PLL2CFGR3;        /*!< RCC PLL2 configuration register 3                              Address offset: 0x0098 */
+       uint32_t RESERVED5;        /*!< Reserved                                                       Address offset: 0x009C */
+  __IO uint32_t PLL3CFGR1;        /*!< RCC PLL3 configuration register 1                              Address offset: 0x00A0 */
+  __IO uint32_t PLL3CFGR2;        /*!< RCC PLL3 configuration register 2                              Address offset: 0x00A4 */
+  __IO uint32_t PLL3CFGR3;        /*!< RCC PLL3 configuration register 3                              Address offset: 0x00A8 */
+       uint32_t RESERVED6;        /*!< Reserved                                                       Address offset: 0x00AC */
+  __IO uint32_t PLL4CFGR1;        /*!< RCC PLL4 configuration register 1                              Address offset: 0x00B0 */
+  __IO uint32_t PLL4CFGR2;        /*!< RCC PLL4 configuration register 2                              Address offset: 0x00B4 */
+  __IO uint32_t PLL4CFGR3;        /*!< RCC PLL4 configuration register 3                              Address offset: 0x00B8 */
+       uint32_t RESERVED7[2];     /*!< Reserved                                                       Address offset: 0x00BC-0x00C0 */
+  __IO uint32_t IC1CFGR;          /*!< RCC IC1 configuration register                                 Address offset: 0x00C4 */
+  __IO uint32_t IC2CFGR;          /*!< RCC IC2 configuration register                                 Address offset: 0x00C8 */
+  __IO uint32_t IC3CFGR;          /*!< RCC IC3 configuration register                                 Address offset: 0x00CC */
+  __IO uint32_t IC4CFGR;          /*!< RCC IC4 configuration register                                 Address offset: 0x00D0 */
+  __IO uint32_t IC5CFGR;          /*!< RCC IC5 configuration register                                 Address offset: 0x00D4 */
+  __IO uint32_t IC6CFGR;          /*!< RCC IC6 configuration register                                 Address offset: 0x00D8 */
+  __IO uint32_t IC7CFGR;          /*!< RCC IC7 configuration register                                 Address offset: 0x00DC */
+  __IO uint32_t IC8CFGR;          /*!< RCC IC8 configuration register                                 Address offset: 0x00E0 */
+  __IO uint32_t IC9CFGR;          /*!< RCC IC9 configuration register                                 Address offset: 0x00E4 */
+  __IO uint32_t IC10CFGR;         /*!< RCC IC10 configuration register                                Address offset: 0x00E8 */
+  __IO uint32_t IC11CFGR;         /*!< RCC IC11 configuration register                                Address offset: 0x00EC */
+  __IO uint32_t IC12CFGR;         /*!< RCC IC12 configuration register                                Address offset: 0x00F0 */
+  __IO uint32_t IC13CFGR;         /*!< RCC IC13 configuration register                                Address offset: 0x00F4 */
+  __IO uint32_t IC14CFGR;         /*!< RCC IC14 configuration register                                Address offset: 0x00F8 */
+  __IO uint32_t IC15CFGR;         /*!< RCC IC15 configuration register                                Address offset: 0x00FC */
+  __IO uint32_t IC16CFGR;         /*!< RCC IC16 configuration register                                Address offset: 0x0100 */
+  __IO uint32_t IC17CFGR;         /*!< RCC IC17 configuration register                                Address offset: 0x0104 */
+  __IO uint32_t IC18CFGR;         /*!< RCC IC18 configuration register                                Address offset: 0x0108 */
+  __IO uint32_t IC19CFGR;         /*!< RCC IC19 configuration register                                Address offset: 0x010C */
+  __IO uint32_t IC20CFGR;         /*!< RCC IC20 configuration register                                Address offset: 0x0110 */
+       uint32_t RESERVED8[4];     /*!< Reserved                                                       Address offset: 0x0114-0x0120 */
+  __IO uint32_t CIER;             /*!< RCC clock-source interrupt enable register                     Address offset: 0x0124 */
+  __IO uint32_t CIFR;             /*!< RCC clock-source interrupt flag register                       Address offset: 0x0128 */
+  __IO uint32_t CICR;             /*!< RCC clock-source interrupt clear register                      Address offset: 0x012C */
+       uint32_t RESERVED9[5];     /*!< Reserved                                                       Address offset: 0x0130-0x0140 */
+  __IO uint32_t CCIPR1;           /*!< RCC clock configuration for independent peripheral register 1  Address offset: 0x0144 */
+  __IO uint32_t CCIPR2;           /*!< RCC clock configuration for independent peripheral register 2  Address offset: 0x0148 */
+  __IO uint32_t CCIPR3;           /*!< RCC clock configuration for independent peripheral register 3  Address offset: 0x014C */
+  __IO uint32_t CCIPR4;           /*!< RCC clock configuration for independent peripheral register 4  Address offset: 0x0150 */
+  __IO uint32_t CCIPR5;           /*!< RCC clock configuration for independent peripheral register 5  Address offset: 0x0154 */
+  __IO uint32_t CCIPR6;           /*!< RCC clock configuration for independent peripheral register 6  Address offset: 0x0158 */
+  __IO uint32_t CCIPR7;           /*!< RCC clock configuration for independent peripheral register 7  Address offset: 0x015C */
+  __IO uint32_t CCIPR8;           /*!< RCC clock configuration for independent peripheral register 8  Address offset: 0x0160 */
+  __IO uint32_t CCIPR9;           /*!< RCC clock configuration for independent peripheral register 9  Address offset: 0x0164 */
+       uint32_t RESERVED10[2];    /*!< Reserved                                                       Address offset: 0x0168-0x016C */
+  __IO uint32_t CCIPR12;          /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */
+  __IO uint32_t CCIPR13;          /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */
+  __IO uint32_t CCIPR14;          /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */
+       uint32_t RESERVED11[35];   /*!< Reserved                                                       Address offset: 0x017C-0x0204 */
+  __IO uint32_t MISCRSTR;         /*!< RCC miscellaneous configurations reset register                Address offset: 0x0208 */
+  __IO uint32_t MEMRSTR;          /*!< RCC embedded memories reset register                           Address offset: 0x020C */
+  __IO uint32_t AHB1RSTR;         /*!< RCC AHB1 reset register                                        Address offset: 0x0210 */
+  __IO uint32_t AHB2RSTR;         /*!< RCC AHB2 reset register                                        Address offset: 0x0214 */
+  __IO uint32_t AHB3RSTR;         /*!< RCC AHB3 reset register                                        Address offset: 0x0218 */
+  __IO uint32_t AHB4RSTR;         /*!< RCC AHB4 reset register                                        Address offset: 0x021C */
+  __IO uint32_t AHB5RSTR;         /*!< RCC AHB5 reset register                                        Address offset: 0x0220 */
+  __IO uint32_t APB1RSTR1;        /*!< RCC APB1 reset register 1                                      Address offset: 0x0224 */
+  __IO uint32_t APB1RSTR2;        /*!< RCC APB1 reset register 2                                      Address offset: 0x0228 */
+  __IO uint32_t APB2RSTR;         /*!< RCC APB2 reset register                                        Address offset: 0x022C */
+       uint32_t RESERVED12;       /*!< Reserved                                                       Address offset: 0x0230 */
+  __IO uint32_t APB4RSTR1;        /*!< RCC APB4 reset register 1                                      Address offset: 0x0234 */
+  __IO uint32_t APB4RSTR2;        /*!< RCC APB4 reset register 2                                      Address offset: 0x0238 */
+  __IO uint32_t APB5RSTR;         /*!< RCC APB5 reset register                                        Address offset: 0x023C */
+  __IO uint32_t DIVENR;           /*!< RCC IC dividers enable register                                Address offset: 0x0240 */
+  __IO uint32_t BUSENR;           /*!< RCC embedded buses enable register                             Address offset: 0x0244 */
+  __IO uint32_t MISCENR;          /*!< RCC miscellaneous configurations enable register               Address offset: 0x0248 */
+  __IO uint32_t MEMENR;           /*!< RCC embedded memories enable register                          Address offset: 0x024C */
+  __IO uint32_t AHB1ENR;          /*!< RCC AHB1 enable register                                       Address offset: 0x0250 */
+  __IO uint32_t AHB2ENR;          /*!< RCC AHB2 enable register                                       Address offset: 0x0254 */
+  __IO uint32_t AHB3ENR;          /*!< RCC AHB3 enable register                                       Address offset: 0x0258 */
+  __IO uint32_t AHB4ENR;          /*!< RCC AHB4 enable register                                       Address offset: 0x025C */
+  __IO uint32_t AHB5ENR;          /*!< RCC AHB5 enable register                                       Address offset: 0x0260 */
+  __IO uint32_t APB1ENR1;         /*!< RCC APB1 enable register 1                                     Address offset: 0x0264 */
+  __IO uint32_t APB1ENR2;         /*!< RCC APB1 enable register 2                                     Address offset: 0x0268 */
+  __IO uint32_t APB2ENR;          /*!< RCC APB2 enable register                                       Address offset: 0x026C */
+  __IO uint32_t APB3ENR;          /*!< RCC APB3 enable register                                       Address offset: 0x0270 */
+  __IO uint32_t APB4ENR1;         /*!< RCC APB4 enable register 1                                     Address offset: 0x0274 */
+  __IO uint32_t APB4ENR2;         /*!< RCC APB4 enable register 2                                     Address offset: 0x0278 */
+  __IO uint32_t APB5ENR;          /*!< RCC APB5 enable register                                       Address offset: 0x027C */
+       uint32_t RESERVED13;       /*!< Reserved                                                       Address offset: 0x0280 */
+  __IO uint32_t BUSLPENR;         /*!< RCC embedded buses sleep enable register                       Address offset: 0x0284 */
+  __IO uint32_t MISCLPENR;        /*!< RCC miscellaneous configurations sleep enable register         Address offset: 0x0288 */
+  __IO uint32_t MEMLPENR;         /*!< RCC embedded memories sleep enable register                    Address offset: 0x028C */
+  __IO uint32_t AHB1LPENR;        /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0290 */
+  __IO uint32_t AHB2LPENR;        /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0294 */
+  __IO uint32_t AHB3LPENR;        /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0298 */
+  __IO uint32_t AHB4LPENR;        /*!< RCC AHB4 sleep enable register                                 Address offset: 0x029C */
+  __IO uint32_t AHB5LPENR;        /*!< RCC AHB5 sleep enable register                                 Address offset: 0x02A0 */
+  __IO uint32_t APB1LPENR1;       /*!< RCC APB1 sleep enable register 1                               Address offset: 0x02A4 */
+  __IO uint32_t APB1LPENR2;       /*!< RCC APB1 sleep enable register 2                               Address offset: 0x02A8 */
+  __IO uint32_t APB2LPENR;        /*!< RCC APB2 sleep enable register                                 Address offset: 0x02AC */
+  __IO uint32_t APB3LPENR;        /*!< RCC APB3 sleep enable register                                 Address offset: 0x02B0 */
+  __IO uint32_t APB4LPENR1;       /*!< RCC APB4 sleep enable register 1                               Address offset: 0x02B4 */
+  __IO uint32_t APB4LPENR2;       /*!< RCC APB4 sleep enable register 2                               Address offset: 0x02B8 */
+  __IO uint32_t APB5LPENR;        /*!< RCC APB5 sleep enable register                                 Address offset: 0x02BC */
+       uint32_t RESERVED14[99];   /*!< Reserved                                                       Address offset: 0x02C0-0x0448 */
+  __IO uint32_t RDCR;             /*!< RCC reset duration control register                            Address offset: 0x044C */
+       uint32_t RESERVED15[204];  /*!< Reserved                                                       Address offset: 0x0450-0x077C */
+  __IO uint32_t SECCFGR0;         /*!< RCC oscillator secure configuration register 0                 Address offset: 0x0780 */
+  __IO uint32_t PRIVCFGR0;        /*!< RCC oscillator privilege configuration register 0              Address offset: 0x0784 */
+  __IO uint32_t LOCKCFGR0;        /*!< RCC oscillator lock configuration register 0                   Address offset: 0x0788 */
+  __IO uint32_t PUBCFGR0;         /*!< RCC oscillator public configuration register 0                 Address offset: 0x078C */
+  __IO uint32_t SECCFGR1;         /*!< RCC PLL secure configuration register 1                        Address offset: 0x0790 */
+  __IO uint32_t PRIVCFGR1;        /*!< RCC PLL privilege configuration register 1                     Address offset: 0x0794 */
+  __IO uint32_t LOCKCFGR1;        /*!< RCC PLL lock configuration register 1                          Address offset: 0x0798 */
+  __IO uint32_t PUBCFGR1;         /*!< RCC PLL public configuration register 1                        Address offset: 0x079C */
+  __IO uint32_t SECCFGR2;         /*!< RCC divider secure configuration register 2                    Address offset: 0x07A0 */
+  __IO uint32_t PRIVCFGR2;        /*!< RCC divider privilege configuration register 2                 Address offset: 0x07A4 */
+  __IO uint32_t LOCKCFGR2;        /*!< RCC divider lock configuration register 2                      Address offset: 0x07A8 */
+  __IO uint32_t PUBCFGR2;         /*!< RCC divider public configuration register 2                    Address offset: 0x07AC */
+  __IO uint32_t SECCFGR3;         /*!< RCC system secure configuration register 3                     Address offset: 0x07B0 */
+  __IO uint32_t PRIVCFGR3;        /*!< RCC system privilege configuration register 3                  Address offset: 0x07B4 */
+  __IO uint32_t LOCKCFGR3;        /*!< RCC system lock configuration register 3                       Address offset: 0x07B8 */
+  __IO uint32_t PUBCFGR3;         /*!< RCC system public configuration register 3                     Address offset: 0x07BC */
+  __IO uint32_t SECCFGR4;         /*!< RCC bus secure configuration register 4                        Address offset: 0x07C0 */
+  __IO uint32_t PRIVCFGR4;        /*!< RCC bus privilege configuration register 4                     Address offset: 0x07C4 */
+  __IO uint32_t LOCKCFGR4;        /*!< RCC bus lock configuration register 4                          Address offset: 0x07C8 */
+  __IO uint32_t PUBCFGR4;         /*!< RCC bus public configuration register 4                        Address offset: 0x07CC */
+  __IO uint32_t PUBCFGR5;         /*!< RCC bus public configuration register 4                        Address offset: 0x07D0 */
+       uint32_t RESERVED16[11];   /*!< Reserved                                                       Address offset: 0x07D4-0x07FC */
+  __IO uint32_t CSR;              /*!< RCC control Set register                                       Address offset: 0x0800 */
+       uint32_t RESERVED17;       /*!< Reserved                                                       Address offset: 0x0804 */
+  __IO uint32_t STOPCSR;          /*!< RCC STOPCSR configuration register                             Address offset: 0x0808 */
+       uint32_t RESERVED18[127];  /*!< Reserved                                                       Address offset: 0x080C-0x0A00 */
+  __IO uint32_t MISCRSTSR;        /*!< RCC miscellaneous reset register                               Address offset: 0x0A08 */
+  __IO uint32_t MEMRSTSR;         /*!< RCC memory reset register                                      Address offset: 0x0A0C */
+  __IO uint32_t AHB1RSTSR;        /*!< RCC AHB1 reset register                                        Address offset: 0x0A10 */
+  __IO uint32_t AHB2RSTSR;        /*!< RCC AHB2 reset register                                        Address offset: 0x0A14 */
+  __IO uint32_t AHB3RSTSR;        /*!< RCC AHB3 reset register                                        Address offset: 0x0A18 */
+  __IO uint32_t AHB4RSTSR;        /*!< RCC AHB4 reset register                                        Address offset: 0x0A1C */
+  __IO uint32_t AHB5RSTSR;        /*!< RCC AHB5 reset register                                        Address offset: 0x0A20 */
+  __IO uint32_t APB1RSTSR1;       /*!< RCC APB1 reset register 1                                      Address offset: 0x0A24 */
+  __IO uint32_t APB1RSTSR2;       /*!< RCC APB1 reset register 2                                      Address offset: 0x0A28 */
+  __IO uint32_t APB2RSTSR;        /*!< RCC APB2 reset register                                        Address offset: 0x0A2C */
+       uint32_t RESERVED19;       /*!< Reserved                                                       Address offset: 0x0A30 */
+  __IO uint32_t APB4RSTSR1;       /*!< RCC APB4 reset register 1                                      Address offset: 0x0A34 */
+  __IO uint32_t APB4RSTSR2;       /*!< RCC APB4 reset register 2                                      Address offset: 0x0A38 */
+  __IO uint32_t APB5RSTSR;        /*!< RCC APB5 reset register                                        Address offset: 0x0A3C */
+  __IO uint32_t DIVENSR;          /*!< RCC divider enable register                                    Address offset: 0x0A40 */
+  __IO uint32_t BUSENSR;          /*!< RCC bus enable register                                        Address offset: 0x0A44 */
+  __IO uint32_t MISCENSR;         /*!< RCC miscellaneous enable register                              Address offset: 0x0A48 */
+  __IO uint32_t MEMENSR;          /*!< RCC memory enable register                                     Address offset: 0x0A4C */
+  __IO uint32_t AHB1ENSR;         /*!< RCC AHB1 enable register                                       Address offset: 0x0A50 */
+  __IO uint32_t AHB2ENSR;         /*!< RCC AHB2 enable register                                       Address offset: 0x0A54 */
+  __IO uint32_t AHB3ENSR;         /*!< RCC AHB3 enable register                                       Address offset: 0x0A58 */
+  __IO uint32_t AHB4ENSR;         /*!< RCC AHB4 enable register                                       Address offset: 0x0A5C */
+  __IO uint32_t AHB5ENSR;         /*!< RCC AHB5 enable register                                       Address offset: 0x0A60 */
+  __IO uint32_t APB1ENSR1;        /*!< RCC APB1 enable register 1                                     Address offset: 0x0A64 */
+  __IO uint32_t APB1ENSR2;        /*!< RCC APB1 enable register 2                                     Address offset: 0x0A68 */
+  __IO uint32_t APB2ENSR;         /*!< RCC APB2 enable register                                       Address offset: 0x0A6C */
+  __IO uint32_t APB3ENSR;         /*!< RCC APB3 enable register                                       Address offset: 0x0A70 */
+  __IO uint32_t APB4ENSR1;        /*!< RCC APB4 enable register 1                                     Address offset: 0x0A74 */
+  __IO uint32_t APB4ENSR2;        /*!< RCC APB4 enable register 2                                     Address offset: 0x0A78 */
+  __IO uint32_t APB5ENSR;         /*!< RCC APB5 enable register                                       Address offset: 0x0A7C */
+       uint32_t RESERVED20;       /*!< Reserved                                                       Address offset: 0x0A80 */
+  __IO uint32_t BUSLPENSR;        /*!< RCC bus sleep enable register                                  Address offset: 0x0A84 */
+  __IO uint32_t MISCLPENSR;       /*!< RCC miscellaneous sleep enable register                        Address offset: 0x0A88 */
+  __IO uint32_t MEMLPENSR;        /*!< RCC memory sleep enable register                               Address offset: 0x0A8C */
+  __IO uint32_t AHB1LPENSR;       /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0A90 */
+  __IO uint32_t AHB2LPENSR;       /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0A94 */
+  __IO uint32_t AHB3LPENSR;       /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0A98 */
+  __IO uint32_t AHB4LPENSR;       /*!< RCC AHB4 sleep enable register                                 Address offset: 0x0A9C */
+  __IO uint32_t AHB5LPENSR;       /*!< RCC AHB5 sleep enable register                                 Address offset: 0x0AA0 */
+  __IO uint32_t APB1LPENSR1;      /*!< RCC APB1 sleep enable register 1                               Address offset: 0x0AA4 */
+  __IO uint32_t APB1LPENSR2;      /*!< RCC APB1 sleep enable register 2                               Address offset: 0x0AA8 */
+  __IO uint32_t APB2LPENSR;       /*!< RCC APB2 sleep enable register                                 Address offset: 0x0AAC */
+  __IO uint32_t APB3LPENSR;       /*!< RCC APB3 sleep enable register                                 Address offset: 0x0AB0 */
+  __IO uint32_t APB4LPENSR1;      /*!< RCC APB4 sleep enable register 1                               Address offset: 0x0AB4 */
+  __IO uint32_t APB4LPENSR2;      /*!< RCC APB4 sleep enable register 2                               Address offset: 0x0AB8 */
+  __IO uint32_t APB5LPENSR;       /*!< RCC APB5 sleep enable register                                 Address offset: 0x0ABC */
+       uint32_t RESERVED21[305];  /*!< Reserved                                                       Address offset: 0x0AC0-0x0F80 */
+  __IO uint32_t PRIVCFGSR0;       /*!< RCC oscillator privilege configuration set register 0          Address offset: 0x0F84 */
+       uint32_t RESERVED22;       /*!< Reserved                                                       Address offset: 0x0F88 */
+  __IO uint32_t PUBCFGSR0;        /*!< RCC oscillator public configuration set register 0             Address offset: 0x0F8C */
+       uint32_t RESERVED23;       /*!< Reserved                                                       Address offset: 0x0F90 */
+  __IO uint32_t PRIVCFGSR1;       /*!< RCC PLL privilege configuration set register 1                 Address offset: 0x0F94 */
+       uint32_t RESERVED24;       /*!< Reserved                                                       Address offset: 0x0F98 */
+  __IO uint32_t PUBCFGSR1;        /*!< RCC PLL public configuration set register 1                    Address offset: 0x0F9C */
+       uint32_t RESERVED25;       /*!< Reserved                                                       Address offset: 0x0FA0 */
+  __IO uint32_t PRIVCFGSR2;       /*!< RCC divider privilege configuration set register 2             Address offset: 0x0FA4 */
+       uint32_t RESERVED26;       /*!< Reserved                                                       Address offset: 0x0FA8 */
+  __IO uint32_t PUBCFGSR2;        /*!< RCC divider public configuration set register 2                Address offset: 0x0FAC */
+       uint32_t RESERVED27;       /*!< Reserved                                                       Address offset: 0x0FB0 */
+  __IO uint32_t PRIVCFGSR3;       /*!< RCC system privilege configuration set register 3              Address offset: 0x0FB4 */
+       uint32_t RESERVED28;       /*!< Reserved                                                       Address offset: 0x0FB8 */
+  __IO uint32_t PUBCFGSR3;        /*!< RCC system public configuration set register 3                 Address offset: 0x0FBC */
+       uint32_t RESERVED29;       /*!< Reserved                                                       Address offset: 0x0FC0 */
+  __IO uint32_t PRIVCFGSR4;       /*!< RCC privilege configuration set register 4                     Address offset: 0x0FC4 */
+       uint32_t RESERVED30;       /*!< Reserved                                                       Address offset: 0x0FC8 */
+  __IO uint32_t PUBCFGSR4;        /*!< RCC public configuration set register 4                            Address offset: 0x0FCC */
+  __IO uint32_t PUBCFGSR5;        /*!< RCC public configuration set register 5                            Address offset: 0x0FD0 */
+       uint32_t RESERVED31[11];   /*!< Reserved                                                       Address offset: 0x0FD4-0x0FFC */
+  __IO uint32_t CCR;              /*!< RCC control clear register                                     Address offset: 0x1000 */
+       uint32_t RESERVED32;       /*!< Reserved                                                       Address offset: 0x1004 */
+  __IO uint32_t STOPCCR;          /*!< RCC Stop mode configuration clear register                     Address offset: 0x1008 */
+       uint32_t RESERVED33[127];  /*!< Reserved                                                       Address offset: 0x100C-0x1200 */
+  __IO uint32_t MISCRSTCR;        /*!< RCC miscellaneous reset clear register                         Address offset: 0x1208 */
+  __IO uint32_t MEMRSTCR;         /*!< RCC memory reset clear register                                Address offset: 0x120C */
+  __IO uint32_t AHB1RSTCR;        /*!< RCC AHB1 reset clear register                                  Address offset: 0x1210 */
+  __IO uint32_t AHB2RSTCR;        /*!< RCC AHB2 reset clear register                                  Address offset: 0x1214 */
+  __IO uint32_t AHB3RSTCR;        /*!< RCC AHB3 reset r clear register                                Address offset: 0x1218 */
+  __IO uint32_t AHB4RSTCR;        /*!< RCC AHB4 reset clear register                                  Address offset: 0x121C */
+  __IO uint32_t AHB5RSTCR;        /*!< RCC AHB5 reset clear register                                  Address offset: 0x1220 */
+  __IO uint32_t APB1RSTCR1;       /*!< RCC APB1 reset clear register 1                                Address offset: 0x1224 */
+  __IO uint32_t APB1RSTCR2;       /*!< RCC APB1 reset clear register 2                                Address offset: 0x1228 */
+  __IO uint32_t APB2RSTCR;        /*!< RCC APB2 reset clear register                                  Address offset: 0x122C */
+       uint32_t RESERVED34;       /*!< Reserved                                                       Address offset: 0x1230 */
+  __IO uint32_t APB4RSTCR1;       /*!< RCC APB4 reset clear register 1                                Address offset: 0x1234 */
+  __IO uint32_t APB4RSTCR2;       /*!< RCC APB4 reset clear register 2                                Address offset: 0x1238 */
+  __IO uint32_t APB5RSTCR;        /*!< RCC APB5 reset clear register                                  Address offset: 0x123C */
+  __IO uint32_t DIVENCR;          /*!< RCC divider enable clear register                              Address offset: 0x1240 */
+  __IO uint32_t BUSENCR;          /*!< RCC bus enable clear register                                  Address offset: 0x1244 */
+  __IO uint32_t MISCENCR;         /*!< RCC miscellaneous enable clear register                        Address offset: 0x1248 */
+  __IO uint32_t MEMENCR;          /*!< RCC memory enable clear register                               Address offset: 0x124C */
+  __IO uint32_t AHB1ENCR;         /*!< RCC AHB1 enable clear register                                 Address offset: 0x1250 */
+  __IO uint32_t AHB2ENCR;         /*!< RCC AHB2 enable clear register                                 Address offset: 0x1254 */
+  __IO uint32_t AHB3ENCR;         /*!< RCC AHB3 enable clear register                                 Address offset: 0x1258 */
+  __IO uint32_t AHB4ENCR;         /*!< RCC AHB4 enable clear register                                 Address offset: 0x125C */
+  __IO uint32_t AHB5ENCR;         /*!< RCC AHB5 enable clear register                                 Address offset: 0x1260 */
+  __IO uint32_t APB1ENCR1;        /*!< RCC APB1 enable clear register 1                               Address offset: 0x1264 */
+  __IO uint32_t APB1ENCR2;        /*!< RCC APB1 enable clear register 2                               Address offset: 0x1268 */
+  __IO uint32_t APB2ENCR;         /*!< RCC APB2 enable clear register                                 Address offset: 0x126C */
+  __IO uint32_t APB3ENCR;         /*!< RCC APB3 enable clear register                                 Address offset: 0x1270 */
+  __IO uint32_t APB4ENCR1;        /*!< RCC APB4 enable clear register 1                               Address offset: 0x1274 */
+  __IO uint32_t APB4ENCR2;        /*!< RCC APB4 enable clear register 2                               Address offset: 0x1278 */
+  __IO uint32_t APB5ENCR;         /*!< RCC APB5 enable clear register                                 Address offset: 0x127C */
+       uint32_t RESERVED35;       /*!< Reserved                                                       Address offset: 0x1280 */
+  __IO uint32_t BUSLPENCR;        /*!< RCC bus sleep enable clear register                            Address offset: 0x1284 */
+  __IO uint32_t MISCLPENCR;       /*!< RCC miscellaneous sleep enable clear register                  Address offset: 0x1288 */
+  __IO uint32_t MEMLPENCR;        /*!< RCC memory sleep enable clear register                         Address offset: 0x128C */
+  __IO uint32_t AHB1LPENCR;       /*!< RCC AHB1 sleep enable clear register                           Address offset: 0x1290 */
+  __IO uint32_t AHB2LPENCR;       /*!< RCC AHB2 sleep enable clear register                           Address offset: 0x1294 */
+  __IO uint32_t AHB3LPENCR;       /*!< RCC AHB3 sleep enable clear register                           Address offset: 0x1298 */
+  __IO uint32_t AHB4LPENCR;       /*!< RCC AHB4 sleep enable clear register                           Address offset: 0x129C */
+  __IO uint32_t AHB5LPENCR;       /*!< RCC AHB5 sleep enable clear register                           Address offset: 0x12A0 */
+  __IO uint32_t APB1LPENCR1;      /*!< RCC APB1 sleep enable clear register 1                         Address offset: 0x12A4 */
+  __IO uint32_t APB1LPENCR2;      /*!< RCC APB1 sleep enable clear register 2                         Address offset: 0x12A8 */
+  __IO uint32_t APB2LPENCR;       /*!< RCC APB2 sleep enable clear register                           Address offset: 0x12AC */
+  __IO uint32_t APB3LPENCR;       /*!< RCC APB3 sleep enable clear register                           Address offset: 0x12B0 */
+  __IO uint32_t APB4LPENCR1;      /*!< RCC APB4 sleep enable clear register 1                         Address offset: 0x12B4 */
+  __IO uint32_t APB4LPENCR2;      /*!< RCC APB4 sleep enable clear register 2                         Address offset: 0x12B8 */
+  __IO uint32_t APB5LPENCR;       /*!< RCC APB5 sleep enable clear register                           Address offset: 0x12BC */
+       uint32_t RESERVED36[305];  /*!< Reserved                                                       Address offset: 0x12C0-0x1780 */
+  __IO uint32_t PRIVCFGCR0;       /*!< RCC oscillator privilege configuration clear register 0        Address offset: 0x1784 */
+       uint32_t RESERVED37;       /*!< Reserved                                                       Address offset: 0x1788 */
+  __IO uint32_t PUBCFGCR0;        /*!< RCC oscillator public configuration clear register 0           Address offset: 0x178C */
+       uint32_t RESERVED38;       /*!< Reserved                                                       Address offset: 0x1790 */
+  __IO uint32_t PRIVCFGCR1;       /*!< RCC PLL privilege configuration clear register 1               Address offset: 0x1794 */
+       uint32_t RESERVED39;       /*!< Reserved                                                       Address offset: 0x1798 */
+  __IO uint32_t PUBCFGCR1;        /*!< RCC PLL public configuration clear register 1                  Address offset: 0x179C */
+       uint32_t RESERVED40;       /*!< Reserved                                                       Address offset: 0x17A0 */
+  __IO uint32_t PRIVCFGCR2;       /*!< RCC divider privilege configuration clear register 2           Address offset: 0x17A4 */
+       uint32_t RESERVED41;       /*!< Reserved                                                       Address offset: 0x17A8 */
+  __IO uint32_t PUBCFGCR2;        /*!< RCC divider public configuration clear register 2              Address offset: 0x17AC */
+       uint32_t RESERVED42;       /*!< Reserved                                                       Address offset: 0x17B0 */
+  __IO uint32_t PRIVCFGCR3;       /*!< RCC system privilege configuration clear register 3            Address offset: 0x17B4 */
+       uint32_t RESERVED43;       /*!< Reserved                                                       Address offset: 0x17B8 */
+  __IO uint32_t PUBCFGCR3;        /*!< RCC system public configuration clear register 3               Address offset: 0x17BC */
+       uint32_t RESERVED44;       /*!< Reserved                                                       Address offset: 0x17C0 */
+  __IO uint32_t PRIVCFGCR4;       /*!< RCC privilege configuration clear register 4                   Address offset: 0x17C4 */
+       uint32_t RESERVED45;       /*!< Reserved                                                       Address offset: 0x17C8 */
+  __IO uint32_t PUBCFGCR4;        /*!< RCC public configuration clear register 4                      Address offset: 0x17CC */
+  __IO uint32_t PUBCFGCR5;        /*!< RCC public configuration clear register 5                      Address offset: 0x17D0 */
+} RCC_TypeDef;
+
+/*
+ * @brief  RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1)
+ */
+typedef struct
+{
+  __IO uint32_t RISC_CR;            /*!< RIFSC RISC slave configuration register x               Address offset: 0x000 */
+       uint32_t RESERVED0[3];       /*!< Reserved                                                Address offset: 0x004-0x00C */
+  __IO uint32_t RISC_SECCFGRx[6];   /*!< RIFSC RISC slave security configuration register x      Address offset: 0x010-0x24 */
+       uint32_t RESERVED1[2];       /*!< Reserved                                                Address offset: 0x028-0x02C */
+  __IO uint32_t RISC_PRIVCFGRx[6];  /*!< RIFSC RISFC slave privileged register x                 Address offset: 0x030-0x44 */
+       uint32_t RESERVED2[2];       /*!< Reserved                                                Address offset: 0x048-0x04C */
+  __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */
+       uint32_t RESERVED3[742];     /*!< Reserved                                                Address offset: 0x068-0xBFC */
+  __IO uint32_t RIMC_CR;            /*!< RIFSC RIMC master configuration register                Address offset: 0xC00 */
+       uint32_t RESERVED4[3];       /*!< Reserved                                                Address offset: 0xC04-0xC0C */
+  __IO uint32_t RIMC_ATTRx[13];     /*!< RIFSC RIMC master attribute register x                  Address offset: 0xC10-0xC40 */
+       uint32_t RESERVED5[219];     /*!< Reserved                                                Address offset: 0xC40-0xFAC */
+  __IO uint32_t PPSRx[6];           /*!< RIFSC peripheral protection status register x           Address offset: 0xFB0-0xFC4 */
+       uint32_t RESERVED6[8];       /*!< Reserved                                                Address offset: 0xFC8-0xFE4 */
+} RIFSC_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version)
+  */
+typedef struct
+{
+  __IO uint32_t CFGR;          /*!< RISAF Region X configuration register             */
+  __IO uint32_t STARTR;        /*!< RISAF Region X start address register             */
+  __IO uint32_t ENDR;          /*!< RISAF Region X end address register               */
+  __IO uint32_t CIDCFGR;       /*!< RISAF Region X CID configuration register         */
+  __IO uint32_t ACFGR;         /*!< RISAF Region X subregion A configuration register */
+  __IO uint32_t ASTARTR;       /*!< RISAF Region X subregion A start address register */
+  __IO uint32_t AENDR;         /*!< RISAF Region X subregion A end address register   */
+  __IO uint32_t ANESTR;        /*!< RISAF Region X subregion A nested mode register   */
+  __IO uint32_t BCFGR;         /*!< RISAF Region X subregion B configuration register */
+  __IO uint32_t BSTARTR;       /*!< RISAF Region X subregion B start address register */
+  __IO uint32_t BENDR;         /*!< RISAF Region X subregion B end address register   */
+  __IO uint32_t BNESTR;        /*!< RISAF Region X subregion B nested mode register   */
+       uint32_t RESERVED0[4];  /*!< Reserved                                          */
+} RISAF_Region_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t IAESR;         /*!< RISAF Illegal access error status register */
+  __IO uint32_t IADDR;         /*!< RISAF Illegal address register,            */
+} RISAF_Illegal_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t              CR;            /*!< RISAF Configuration register,                            Address offset: 0x000 */
+  __IO uint32_t              RESERVED0;     /*!< Reserved,                                                Address offset: 0x004 */
+  __IO uint32_t              IASR;          /*!< RISAF Illegal access status register,                    Address offset: 0x008 */
+  __IO uint32_t              IACR;          /*!< RISAF Illegal access clear register,                     Address offset: 0x00C */
+       uint32_t              RESERVED1[4];  /*!< Reserved,                                                          0x010-0x01C */
+       RISAF_Illegal_TypeDef IAR[1];        /*!< RISAF Illegal access error status and address register,            0x020-0x024 */
+       uint32_t              RESERVED2[6];  /*!< Reserved,                                                          0x028-0x03C */
+       RISAF_Region_TypeDef  REG[15];       /*!< RISAF Region X configuration register,                             0x040-0x3FC */
+} RISAF_TypeDef;
+
+/**
+  * @brief RNG
+  */
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+  uint32_t RESERVED;
+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
+} RNG_TypeDef;
+
+/*
+* @brief RTC Specific device feature definitions
+*/
+#define RTC_BKP_NB         32U
+#define RTC_TAMP_NB        7U
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
+ __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
+ __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
+ __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
+ __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
+ __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
+ __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
+__IO uint32_t SECCFGR;      /*!< RTC secure mode control register,               Address offset: 0x20 */
+ __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
+ __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
+ __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
+ __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
+ __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
+ __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
+      uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
+ __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
+ __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
+ __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
+ __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
+ __IO uint32_t SMISR;       /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
+ __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
+      uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
+ __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
+ __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
+} RTC_TypeDef;
+
+/**
+  * @brief SAES Processor
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< SAES control register,                      Address offset: 0x000 */
+  __IO uint32_t SR;             /*!< SAES status register,                       Address offset: 0x004 */
+  __IO uint32_t DINR;           /*!< SAES data input register,                   Address offset: 0x008 */
+  __IO uint32_t DOUTR;          /*!< SAES data output register,                  Address offset: 0x00C */
+  __IO uint32_t KEYR0;          /*!< SAES key register 0,                        Address offset: 0x010 */
+  __IO uint32_t KEYR1;          /*!< SAES key register 1,                        Address offset: 0x014 */
+  __IO uint32_t KEYR2;          /*!< SAES key register 2,                        Address offset: 0x018 */
+  __IO uint32_t KEYR3;          /*!< SAES key register 3,                        Address offset: 0x01C */
+  __IO uint32_t IVR0;           /*!< SAES initialization vector register 0,      Address offset: 0x020 */
+  __IO uint32_t IVR1;           /*!< SAES initialization vector register 1,      Address offset: 0x024 */
+  __IO uint32_t IVR2;           /*!< SAES initialization vector register 2,      Address offset: 0x028 */
+  __IO uint32_t IVR3;           /*!< SAES initialization vector register 3,      Address offset: 0x02C */
+  __IO uint32_t KEYR4;          /*!< SAES key register 4,                        Address offset: 0x030 */
+  __IO uint32_t KEYR5;          /*!< SAES key register 5,                        Address offset: 0x034 */
+  __IO uint32_t KEYR6;          /*!< SAES key register 6,                        Address offset: 0x038 */
+  __IO uint32_t KEYR7;          /*!< SAES key register 7,                        Address offset: 0x03C */
+       uint32_t RESERVED1[48];  /*!< Reserved,                                   Address offset: 0x040 -- 0x0FC */
+  __IO uint32_t DPACFGR;        /*!< SAES DPA configuration register,            Address offset: 0x100 */
+       uint32_t RESERVED2[127]; /*!< Reserved,                                   Address offset: 0x104 -- 0x2FC */
+  __IO uint32_t IER;            /*!< SAES Interrupt Enable Register,             Address offset: 0x300 */
+  __IO uint32_t ISR;            /*!< SAES Interrupt Status Register,             Address offset: 0x304 */
+  __IO uint32_t ICR;            /*!< SAES Interrupt Clear Register,              Address offset: 0x308 */
+} SAES_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+typedef struct
+{
+  __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
+  uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
+  __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
+  __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,              Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,              Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                   Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                    Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,           Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                 Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                 Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                 Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                 Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                 Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,                Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,               Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,               Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,                     Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,            Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                       Address offset: 0x3C */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,      Address offset: 0x40 */
+  __IO uint32_t FIFOTHR;        /*!< SDMMC data FIFO threshold register,        Address offset: 0x44 */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x48 - 0x4C                                           */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,                Address offset: 0x50 */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,            Address offset: 0x54 */
+  __IO uint32_t IDMABASER;      /*!< SDMMC DMA buffer base address register,    Address offset: 0x58 */
+  uint32_t      RESERVED1[2];   /*!< Reserved, 0x5C - 0x60                                           */
+  __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,    Address offset: 0x64 */
+  __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
+  uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                  Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/**
+  * @brief SPI
+  */
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief UCPD
+  */
+typedef struct
+{
+  __IO uint32_t CFG1;        /*!< UCPD configuration register 1,            Address offset: 0x00 */
+  __IO uint32_t CFG2;        /*!< UCPD configuration register 2,            Address offset: 0x04 */
+  __IO uint32_t RESERVED0;   /*!< UCPD reserved register,                   Address offset: 0x08 */
+  __IO uint32_t CR;          /*!< UCPD control register,                    Address offset: 0x0C */
+  __IO uint32_t IMR;         /*!< UCPD interrupt mask register,             Address offset: 0x10 */
+  __IO uint32_t SR;          /*!< UCPD status register,                     Address offset: 0x14 */
+  __IO uint32_t ICR;         /*!< UCPD interrupt flag clear register        Address offset: 0x18 */
+  __IO uint32_t TX_ORDSET;   /*!< UCPD Tx ordered set type register,        Address offset: 0x1C */
+  __IO uint32_t TX_PAYSZ;    /*!< UCPD Tx payload size register,            Address offset: 0x20 */
+  __IO uint32_t TXDR;        /*!< UCPD Tx data register,                    Address offset: 0x24 */
+  __IO uint32_t RX_ORDSET;   /*!< UCPD Rx ordered set type register,        Address offset: 0x28 */
+  __IO uint32_t RX_PAYSZ;    /*!< UCPD Rx payload size register,            Address offset: 0x2C */
+  __IO uint32_t RXDR;        /*!< UCPD Rx data register,                    Address offset: 0x30 */
+  __IO uint32_t RX_ORDEXT1;  /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
+  __IO uint32_t RX_ORDEXT2;  /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
+} UCPD_TypeDef;
+
+/**
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;             /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t GOTGINT;             /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t GAHBCFG;             /*!< Core AHB Configuration Register,           Address offset: 008h */
+  __IO uint32_t GUSBCFG;             /*!< Core USB Configuration Register,           Address offset: 00Ch */
+  __IO uint32_t GRSTCTL;             /*!< Core Reset Register,                       Address offset: 010h */
+  __IO uint32_t GINTSTS;             /*!< Core Interrupt Register,                   Address offset: 014h */
+  __IO uint32_t GINTMSK;             /*!< Core Interrupt Mask Register,              Address offset: 018h */
+  __IO uint32_t GRXSTSR;             /*!< Receive Sts Q Read Register,               Address offset: 01Ch */
+  __IO uint32_t GRXSTSP;             /*!< Receive Sts Q Read & POP Register,         Address offset: 020h */
+  __IO uint32_t GRXFSIZ;             /*!< Receive FIFO Size Register,                Address offset: 024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;  /*!< EP0 / Non Periodic Tx FIFO Size Register,  Address offset: 028h */
+  __IO uint32_t HNPTXSTS;            /*!< Non Periodic Tx FIFO/Queue Sts reg,        Address offset: 02Ch */
+  __IO uint32_t Reserved30[2];       /*!< Reserved,                                  Address offset: 030h */
+  __IO uint32_t GCCFG;               /*!< General Purpose IO Register,               Address offset: 038h */
+  __IO uint32_t CID;                 /*!< User ID Register,                          Address offset: 03Ch */
+  __IO uint32_t GSNPSID;             /*!< USB_OTG core ID,                           Address offset: 040h */
+  __IO uint32_t GHWCFG1;             /*!< User HW config1,                           Address offset: 044h */
+  __IO uint32_t GHWCFG2;             /*!< User HW config2,                           Address offset: 048h */
+  __IO uint32_t GHWCFG3;             /*!< User HW config3,                           Address offset: 04Ch */
+  __IO uint32_t Reserved6;           /*!< Reserved,                                  Address offset: 050h */
+  __IO uint32_t GLPMCFG;             /*!< LPM Register,                              Address offset: 054h */
+  __IO uint32_t GPWRDN;              /*!< Power Down Register,                       Address offset: 058h */
+  __IO uint32_t GDFIFOCFG;           /*!< DFIFO Software Config Register,            Address offset: 05Ch */
+  __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register,    Address offset: 60Ch */
+  __IO uint32_t Reserved43[39];      /*!< Reserved,                                  Address offset: 058h */
+  __IO uint32_t HPTXFSIZ;            /*!< Host Periodic Tx FIFO Size Reg,            Address offset: 100h */
+  __IO uint32_t DIEPTXF[0x0F];       /*!< dev Periodic Transmit FIFO                 Address offset: 104h */
+} USB_OTG_GlobalTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;          /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;     /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;     /*!< Core AHB Configuration Register,           Address offset: 008h */
+} USB_PHY_GlobalTypeDef;
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;                /*!< dev Configuration Register,   Address offset: 800h */
+  __IO uint32_t DCTL;                /*!< dev Control Register,         Address offset: 804h */
+  __IO uint32_t DSTS;                /*!< dev Status Register (RO),     Address offset: 808h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                     Address offset: 80Ch */
+  __IO uint32_t DIEPMSK;             /*!< dev IN Endpoint Mask,         Address offset: 810h */
+  __IO uint32_t DOEPMSK;             /*!< dev OUT Endpoint Mask,        Address offset: 814h */
+  __IO uint32_t DAINT;               /*!< dev All Endpoints Itr Reg,    Address offset: 818h */
+  __IO uint32_t DAINTMSK;            /*!< dev All Endpoints Itr Mask,   Address offset: 81Ch */
+  __IO uint32_t Reserved20;          /*!< Reserved,                     Address offset: 820h */
+  __IO uint32_t Reserved9;           /*!< Reserved,                     Address offset: 824h */
+  __IO uint32_t DVBUSDIS;            /*!< dev VBUS discharge Register,  Address offset: 828h */
+  __IO uint32_t DVBUSPULSE;          /*!< dev VBUS Pulse Register,      Address offset: 82Ch */
+  __IO uint32_t DTHRCTL;             /*!< dev threshold,                Address offset: 830h */
+  __IO uint32_t DIEPEMPMSK;          /*!< dev empty msk,                Address offset: 834h */
+  __IO uint32_t DEACHINT;            /*!< dedicated EP interrupt,       Address offset: 838h */
+  __IO uint32_t DEACHMSK;            /*!< dedicated EP msk,             Address offset: 83Ch */
+  __IO uint32_t Reserved40;          /*!< dedicated EP mask,            Address offset: 840h */
+  __IO uint32_t DINEP1MSK;           /*!< dedicated EP mask,            Address offset: 844h */
+  __IO uint32_t Reserved44[15];      /*!< Reserved,                     Address offset: 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;          /*!< dedicated EP msk,             Address offset: 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;             /*!< dev IN Endpoint Control Register,          Address offset: 900h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;             /*!< dev IN Endpoint Itr Register,              Address offset: 900h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;            /*!< IN Endpoint Txfer Size Register,           Address offset: 900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;             /*!< IN Endpoint DMA Address Register,          Address offset: 900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;             /*!< IN Endpoint Tx FIFO Status Register,       Address offset: 900h + (ep_num * 20h) + 18h */
+  __IO uint32_t Reserved18;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;             /*!< dev OUT Endpoint Control Register,         Address offset: B00h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;             /*!< dev OUT Endpoint Itr Register,             Address offset: B00h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;            /*!< dev OUT Endpoint Txfer Size Register,      Address offset: B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;             /*!< dev OUT Endpoint DMA Address Register,     Address offset: B00h + (ep_num * 20h) + 14h */
+  __IO uint32_t Reserved18[2];       /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 18h */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;                 /*!< Host Configuration Register,              Address offset: 400h */
+  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register,             Address offset: 404h */
+  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining,           Address offset: 408h */
+  __IO uint32_t Reserved40C;          /*!< Reserved,                                 Address offset: 40Ch */
+  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status,      Address offset: 410h */
+  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register,     Address offset: 414h */
+  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask,         Address offset: 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;               /*!< Host Channel Characteristics Register,    Address offset: 500h */
+  __IO uint32_t HCSPLT;               /*!< Host Channel Split Control Register,      Address offset: 504h */
+  __IO uint32_t HCINT;                /*!< Host Channel Interrupt Register,          Address offset: 508h */
+  __IO uint32_t HCINTMSK;             /*!< Host Channel Interrupt Mask Register,     Address offset: 50Ch */
+  __IO uint32_t HCTSIZ;               /*!< Host Channel Transfer Size Register,      Address offset: 510h */
+  __IO uint32_t HCDMA;                /*!< Host Channel DMA Address Register,        Address offset: 514h */
+  uint32_t Reserved[2];               /*!< Reserved,                                 Address offset: 518h */
+} USB_OTG_HostChannelTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;           /*!< USB HS PHY Control Register,              Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;      /*!< USB HS PHY Trimming_1 Register,           Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;      /*!< USB HS PHY Trimming_2 Register,           Address offset: 008h */
+} USB_HS_PHYC_GlobalTypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t IMR;         /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t IFCR;        /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t DR;          /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t CSR;         /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t DIR;         /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t BOOTCR;         /*!< SYSCFG boot pin control register,                                            Address offset: 0x00 */
+  __IO uint32_t CM55CR;         /*!< SYSCFG Cortex-M55 control register,                                          Address offset: 0x04 */
+  __IO uint32_t CM55TCMCR;      /*!< SYSCFG Cortex-M55 TCM control register,                                      Address offset: 0x08 */
+  __IO uint32_t CM55RWMCR;      /*!< SYSCFG Cortex-M55 memory RW margin register,                                 Address offset: 0x0C */
+  __IO uint32_t INITSVTORCR;    /*!< SYSCFG Cortex-M55 SVTOR control register,                                    Address offset: 0x10 */
+  __IO uint32_t INITNSVTORCR;   /*!< Cortex-M55 NSVTOR control register,                                          Address offset: 0x14 */
+  __IO uint32_t CM55RSTCR;      /*!< SYSCFG Cortex-M55 reset type control register,                               Address offset: 0x18 */
+  __IO uint32_t CM55PAHBWPR;    /*!< SYSCFG Cortex-M55 P-AHB write posting control register,                      Address offset: 0x1C */
+  __IO uint32_t VENCRAMCR;      /*!< SYSCFG VENCRAM control register,                                             Address offset: 0x20 */
+  __IO uint32_t POTTAMPRSTCR;   /*!< SYSCFG potential tamper reset register,                                      Address offset: 0x24 */
+  uint32_t      RESERVED1[3];   /*!< Reserved,                                                                    Address offset: 0x28-0x30 */
+  __IO uint32_t ICNEWRCR;       /*!< SYSCFG AHB-AXI bridge early write response,                                  Address offset: 0x34 */
+  __IO uint32_t ICNCGCR;        /*!< SYSCFG ICN clock gating control register,                                    Address offset: 0x38 */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                                                    Address offset: 0x3C-0x40 */
+  __IO uint32_t VDDIO2CCCR;     /*!< SYSCFG VDDIO2 compensation cell control register,                            Address offset: 0x44 */
+  __IO uint32_t VDDIO2CCSR;     /*!< SYSCFG VDDIO2 compensation cell status register,                             Address offset: 0x48 */
+  __IO uint32_t VDDIO3CCCR;     /*!< SYSCFG VDDIO3 compensation cell control register,                            Address offset: 0x4C */
+  __IO uint32_t VDDIO3CCSR;     /*!< SYSCFG VDDIO3 compensation cell status register,                             Address offset: 0x50 */
+  __IO uint32_t VDDIO4CCCR;     /*!< SYSCFG VDDIO4 compensation cell control register,                            Address offset: 0x54 */
+  __IO uint32_t VDDIO4CCSR;     /*!< SYSCFG VDDIO4 compensation cell status register,                             Address offset: 0x58 */
+  __IO uint32_t VDDIO5CCCR;     /*!< SYSCFG VDDIO5 compensation cell control register,                            Address offset: 0x5C */
+  __IO uint32_t VDDIO5CCSR;     /*!< SYSCFG VDDIO5 compensation cell status register,                             Address offset: 0x60 */
+  __IO uint32_t VDDCCCR;        /*!< SYSCFG VDD compensation cell control register,                               Address offset: 0x64 */
+  __IO uint32_t VDDCCSR;        /*!< SYSCFG VDD compensation cell status register,                                Address offset: 0x68 */
+  __IO uint32_t CBR;            /*!< SYSCFG control timer break register,                                         Address offset: 0x6C */
+  __IO uint32_t SEC_AIDCR;      /*!< SYSCFG DMA CID secure control register,                                      Address offset: 0x70 */
+  __IO uint32_t FMC_RETIMECR;   /*!< SYSCFG FMC retiming logic control register,                                  Address offset: 0x74 */
+  uint32_t      RESERVED3[34];  /*!< Reserved,                                                                    Address offset: 0x78-0xFC */
+  __IO uint32_t BOOTSR;         /*!< SYSCFG boot pin status register,                                             Address offset: 0x100 */
+  __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register,                             Address offset: 0x104 */
+  uint32_t      RESERVED4[446]; /*!< Reserved,                                                                    Address offset: 0x108-0x3FC */
+  __IO uint32_t SECPRIV_AIDCR;  /*!< SYSCFG DMA CID non-secure control register,                                  Address offset: 0x800 */
+  uint32_t      RESERVED5[507]; /*!< Reserved,                                                                    Address offset: 0x804-0xFEC */
+  __IO uint32_t DEVICEID;       /*!< SYSCFG Device ID,                                                            Address offset: 0xFF0 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Tamper and backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1;           /*!< TAMP configuration register 1,                    Address offset: 0x00 */
+ __IO uint32_t CR2;           /*!< TAMP configuration register 2,                    Address offset: 0x04 */
+ __IO uint32_t CR3;           /*!< TAMP configuration register 3,                    Address offset: 0x08 */
+ __IO uint32_t FLTCR;         /*!< TAMP filter control register,                     Address offset: 0x0C */
+ __IO uint32_t ATCR1;         /*!< TAMP filter control register 1                    Address offset: 0x10 */
+ __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,                 Address offset: 0x14 */
+ __IO uint32_t ATOR;          /*!< TAMP active tamper output register,               Address offset: 0x18 */
+ __IO uint32_t ATCR2;         /*!< TAMP filter control register 2,                   Address offset: 0x1C */
+ __IO uint32_t SECCFGR;       /*!< TAMP secure mode control register,                Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR;      /*!< TAMP privilege mode control register,             Address offset: 0x24 */
+      uint32_t RESERVED2;     /*!< Reserved,                                         Address offset: 0x28 */
+ __IO uint32_t IER;           /*!< TAMP interrupt enable register,                   Address offset: 0x2C */
+ __IO uint32_t SR;            /*!< TAMP status register,                             Address offset: 0x30 */
+ __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,            Address offset: 0x34 */
+ __IO uint32_t SMISR;         /*!< TAMP secure masked interrupt status register,     Address offset: 0x38 */
+ __IO uint32_t SCR;           /*!< TAMP status clear register,                       Address offset: 0x3C */
+ __IO uint32_t COUNT1R;       /*!< TAMP monotonic counter register,                  Address offset: 0x40 */
+      uint32_t RESERVED4[3];  /*!< Reserved,                                         Address offset: 0x43 -- 0x4C */
+ __IO uint32_t OR;            /*!< TAMP option register,                             Address offset: 0x50 */
+ __IO uint32_t RPCFGR;        /*!< TAMP resources protection configuration register, Address offset: 0x54 */
+      uint32_t RESERVED5[42]; /*!< Reserved,                                         Address offset: 0x58 -- 0xFC */
+ __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                           Address offset: 0x100 */
+ __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                           Address offset: 0x104 */
+ __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                           Address offset: 0x108 */
+ __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                           Address offset: 0x10C */
+ __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                           Address offset: 0x110 */
+ __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                           Address offset: 0x114 */
+ __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                           Address offset: 0x118 */
+ __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                           Address offset: 0x11C */
+ __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                           Address offset: 0x120 */
+ __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                           Address offset: 0x124 */
+ __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                          Address offset: 0x128 */
+ __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                          Address offset: 0x12C */
+ __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                          Address offset: 0x130 */
+ __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                          Address offset: 0x134 */
+ __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                          Address offset: 0x138 */
+ __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                          Address offset: 0x13C */
+ __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                          Address offset: 0x140 */
+ __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                          Address offset: 0x144 */
+ __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                          Address offset: 0x148 */
+ __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                          Address offset: 0x14C */
+ __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                          Address offset: 0x150 */
+ __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                          Address offset: 0x154 */
+ __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                          Address offset: 0x158 */
+ __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                          Address offset: 0x15C */
+ __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                          Address offset: 0x160 */
+ __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                          Address offset: 0x164 */
+ __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                          Address offset: 0x168 */
+ __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                          Address offset: 0x16C */
+ __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                          Address offset: 0x170 */
+ __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                          Address offset: 0x174 */
+ __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                          Address offset: 0x178 */
+ __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                          Address offset: 0x17C */
+} TAMP_TypeDef;
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint32_t CR1;            /*!< TIM control register 1,                   Address offset:  0x00 */
+  __IO uint32_t CR2;            /*!< TIM control register 2,                   Address offset:  0x04 */
+  __IO uint32_t SMCR;           /*!< TIM slave mode control register,          Address offset:  0x08 */
+  __IO uint32_t DIER;           /*!< TIM DMA/interrupt enable register,        Address offset:  0x0C */
+  __IO uint32_t SR;             /*!< TIM status register,                      Address offset:  0x10 */
+  __IO uint32_t EGR;            /*!< TIM event generation register,            Address offset:  0x14 */
+  __IO uint32_t CCMR1;          /*!< TIM capture/compare mode register 1,      Address offset:  0x18 */
+  __IO uint32_t CCMR2;          /*!< TIM capture/compare mode register 2,      Address offset:  0x1C */
+  __IO uint32_t CCER;           /*!< TIM capture/compare enable register,      Address offset:  0x20 */
+  __IO uint32_t CNT;            /*!< TIM counter register,                     Address offset:  0x24 */
+  __IO uint32_t PSC;            /*!< TIM prescaler,                            Address offset:  0x28 */
+  __IO uint32_t ARR;            /*!< TIM auto-reload register,                 Address offset:  0x2C */
+  __IO uint32_t RCR;            /*!< TIM repetition counter register,          Address offset:  0x30 */
+  __IO uint32_t CCR1;           /*!< TIM capture/compare register 1,           Address offset:  0x34 */
+  __IO uint32_t CCR2;           /*!< TIM capture/compare register 2,           Address offset:  0x38 */
+  __IO uint32_t CCR3;           /*!< TIM capture/compare register 3,           Address offset:  0x3C */
+  __IO uint32_t CCR4;           /*!< TIM capture/compare register 4,           Address offset:  0x40 */
+  __IO uint32_t BDTR;           /*!< TIM break and dead-time register,         Address offset:  0x44 */
+  __IO uint32_t CCR5;           /*!< TIM capture/compare register 5,           Address offset:  0x48 */
+  __IO uint32_t CCR6;           /*!< TIM capture/compare register 6,           Address offset:  0x4C */
+  __IO uint32_t CCMR3;          /*!< TIM capture/compare mode register 3,      Address offset:  0x50 */
+  __IO uint32_t DTR2;           /*!< TIM deadtime register 2,                  Address offset:  0x54 */
+  __IO uint32_t ECR;            /*!< TIM encoder control register,             Address offset:  0x58 */
+  __IO uint32_t TISEL;          /*!< TIM Input Selection register,             Address offset:  0x5C */
+  __IO uint32_t AF1;            /*!< TIM alternate function option register 1, Address offset:  0x60 */
+  __IO uint32_t AF2;            /*!< TIM alternate function option register 2, Address offset:  0x64 */
+       uint32_t RESERVED1[221]; /*!< Reserved,                                            0x6C-0x3D8 */
+  __IO uint32_t DCR;            /*!< TIM DMA control register,                 Address offset: 0x3DC */
+  __IO uint32_t DMAR;           /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C */
+} USART_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief Window Watchdog
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,              Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,               Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief Extended-SPI Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI Control Register,                                Address offset: 0x000         */
+       uint32_t RESERVED1;      /*!< Reserved,                                             Address offset: 0x004         */
+  __IO uint32_t DCR1;           /*!< XSPI Device Configuration Register 1,                 Address offset: 0x008         */
+  __IO uint32_t DCR2;           /*!< XSPI Device Configuration Register 2,                 Address offset: 0x00C         */
+  __IO uint32_t DCR3;           /*!< XSPI Device Configuration Register 3,                 Address offset: 0x010         */
+  __IO uint32_t DCR4;           /*!< XSPI Device Configuration Register 4,                 Address offset: 0x014         */
+       uint32_t RESERVED2[2];   /*!< Reserved,                                             Address offset: 0x018 - 0x01C */
+  __IO uint32_t SR;             /*!< XSPI Status Register,                                 Address offset: 0x020         */
+  __IO uint32_t FCR;            /*!< XSPI Flag Clear Register,                             Address offset: 0x024         */
+       uint32_t RESERVED3[6];   /*!< Reserved,                                             Address offset: 0x028 - 0x03C */
+  __IO uint32_t DLR;            /*!< XSPI Data Length Register,                            Address offset: 0x040         */
+       uint32_t RESERVED4;      /*!< Reserved,                                             Address offset: 0x044         */
+  __IO uint32_t AR;             /*!< XSPI Address Register,                                Address offset: 0x048         */
+       uint32_t RESERVED5;      /*!< Reserved,                                             Address offset: 0x04C         */
+  __IO uint32_t DR;             /*!< XSPI Data Register,                                   Address offset: 0x050         */
+       uint32_t RESERVED6[11];  /*!< Reserved,                                             Address offset: 0x054 - 0x07C */
+  __IO uint32_t PSMKR;          /*!< XSPI Polling Status Mask Register,                    Address offset: 0x080         */
+       uint32_t RESERVED7;      /*!< Reserved,                                             Address offset: 0x084         */
+  __IO uint32_t PSMAR;          /*!< XSPI Polling Status Match Register,                   Address offset: 0x088         */
+       uint32_t RESERVED8;      /*!< Reserved,                                             Address offset: 0x08C         */
+  __IO uint32_t PIR;            /*!< XSPI Polling Interval Register,                       Address offset: 0x090         */
+       uint32_t RESERVED9[27];  /*!< Reserved,                                             Address offset: 0x094 - 0x0FC */
+  __IO uint32_t CCR;            /*!< XSPI Communication Configuration Register,            Address offset: 0x100         */
+       uint32_t RESERVED10;     /*!< Reserved,                                             Address offset: 0x104         */
+  __IO uint32_t TCR;            /*!< XSPI Timing Configuration Register,                   Address offset: 0x108         */
+       uint32_t RESERVED11;     /*!< Reserved,                                             Address offset: 0x10C         */
+  __IO uint32_t IR;             /*!< XSPI Instruction Register,                            Address offset: 0x110         */
+       uint32_t RESERVED12[3];  /*!< Reserved,                                             Address offset: 0x114 - 0x11C */
+  __IO uint32_t ABR;            /*!< XSPI Alternate Bytes Register,                        Address offset: 0x120         */
+       uint32_t RESERVED13[3];  /*!< Reserved,                                             Address offset: 0x124 - 0x12C */
+  __IO uint32_t LPTR;           /*!< XSPI Low-Power Timeout Register,                      Address offset: 0x130         */
+       uint32_t RESERVED14[3];  /*!< Reserved,                                             Address offset: 0x134 - 0x13C */
+  __IO uint32_t WPCCR;          /*!< XSPI Wrap Communication Configuration Register,       Address offset: 0x140         */
+       uint32_t RESERVED15;     /*!< Reserved,                                             Address offset: 0x144         */
+  __IO uint32_t WPTCR;          /*!< XSPI Wrap Timing Configuration Register,              Address offset: 0x148         */
+       uint32_t RESERVED16;     /*!< Reserved,                                             Address offset: 0x14C         */
+  __IO uint32_t WPIR;           /*!< XSPI Wrap Instruction Register,                       Address offset: 0x150         */
+       uint32_t RESERVED17[3];  /*!< Reserved,                                             Address offset: 0x154 - 0x15C */
+  __IO uint32_t WPABR;          /*!< XSPI Wrap Alternate Bytes Register,                   Address offset: 0x160         */
+       uint32_t RESERVED18[7];  /*!< Reserved,                                             Address offset: 0x164 - 0x17C */
+  __IO uint32_t WCCR;           /*!< XSPI Write Communication Configuration Register,      Address offset: 0x180         */
+       uint32_t RESERVED19;     /*!< Reserved,                                             Address offset: 0x184         */
+  __IO uint32_t WTCR;           /*!< XSPI Write Timing Configuration Register,             Address offset: 0x188         */
+       uint32_t RESERVED20;     /*!< Reserved,                                             Address offset: 0x18C         */
+  __IO uint32_t WIR;            /*!< XSPI Write Instruction Register,                      Address offset: 0x190         */
+       uint32_t RESERVED21[3];  /*!< Reserved,                                             Address offset: 0x194 - 0x19C */
+  __IO uint32_t WABR;           /*!< XSPI Write Alternate Bytes Register,                  Address offset: 0x1A0         */
+       uint32_t RESERVED22[23]; /*!< Reserved,                                             Address offset: 0x1A4 - 0x1FC */
+  __IO uint32_t HLCR;           /*!< XSPI HyperBus Latency Configuration Register,         Address offset: 0x200         */
+       uint32_t RESERVED23[3];  /*!< Reserved,                                             Address offset: 0x204 - 0x20C */
+  __IO uint32_t CALFCR;         /*!< XSPI Full-Cycle Calibration Configuration Register,   Address offset: 0x210         */
+       uint32_t RESERVED24;     /*!< Reserved,                                             Address offset: 0x214         */
+  __IO uint32_t CALMR;          /*!< XSPI DLL Master Calibration Configuration Register,   Address offset: 0x218         */
+       uint32_t RESERVED25;     /*!< Reserved,                                             Address offset: 0x21C         */
+  __IO uint32_t CALSOR;         /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220         */
+       uint32_t RESERVED26;     /*!< Reserved,                                             Address offset: 0x224         */
+  __IO uint32_t CALSIR;         /*!< XSPI Slave Input Calibration Configuration Register,  Address offset: 0x228         */
+} XSPI_TypeDef;
+
+/**
+  * @brief XSPI IO Manager
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI IO Manager Control Register,                     Address offset: 0x00        */
+} XSPIM_TypeDef;
+
+/** @} */ /* End of group STM32N6xx_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_peripheralAddr
+  * @{
+  */
+
+/* Internal RAMs sizes */
+#define SRAM1_AXI_SIZE                  0x100000UL   /*!< SRAM1_AXI = 1024 Kbytes */
+#define SRAM2_AXI_SIZE                  0x100000UL   /*!< SRAM2_AXI = 1024 Kbytes */
+#define FLEXRAM_SIZE                     0x64000UL   /*!< FLEXRAM <= 400 Kbytes   */
+#define SRAM3_AXI_SIZE                   0x70000UL   /*!< SRAM3_AXI = 448 Kbytes  */
+#define SRAM4_AXI_SIZE                   0x70000UL   /*!< SRAM4_AXI = 448 Kbytes  */
+#define SRAM5_AXI_SIZE                   0x70000UL   /*!< SRAM5_AXI = 448 Kbytes  */
+#define SRAM6_AXI_SIZE                   0x70000UL   /*!< SRAM6_AXI = 448 Kbytes  */
+#define SRAM1_AHB_SIZE                    0x4000UL   /*!< SRAM1_AHB = 16 Kbytes   */
+#define SRAM2_AHB_SIZE                    0x4000UL   /*!< SRAM2_AHB = 16 Kbytes   */
+#define VENC_RAM_SIZE                    0x20000UL   /*!< VENC RAM  = 128 Kbytes  */
+#define SRAM7_AXI_SIZE                   0x40000UL   /*!< SRAM7_AXI = 256 Kbytes  */
+#define BKPSRAM_SIZE                      0x2000UL   /*!< BKPSRAM  = 8 Kbytes     */
+
+
+#define FMC_BASE                        0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */
+#define FMC_BANK1                       FMC_BASE
+#define FMC_BANK1_1                     FMC_BANK1
+#define FMC_BANK1_2                     (FMC_BANK1 + 0x04000000UL)
+#define FMC_BANK1_3                     (FMC_BANK1 + 0x08000000UL)
+#define FMC_BANK1_4                     (FMC_BANK1 + 0x0C000000UL)
+#define FMC_BANK5                       0xC0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK5_1                     FMC_BANK5
+#define FMC_BANK5_2                     (FMC_BANK5 + 0x04000000UL)
+#define FMC_BANK5_3                     (FMC_BANK5 + 0x08000000UL)
+#define FMC_BANK5_4                     (FMC_BANK5 + 0x0C000000UL)
+#define FMC_BANK6                       0xD0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK6_1                     FMC_BANK6
+#define FMC_BANK6_2                     (FMC_BANK6 + 0x04000000UL)
+#define FMC_BANK6_3                     (FMC_BANK6 + 0x08000000UL)
+#define FMC_BANK6_4                     (FMC_BANK6 + 0x0C000000UL)
+#define XSPI1_BASE                      0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI    */
+#define XSPI2_BASE                      0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI    */
+#define XSPI3_BASE                      0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI    */
+
+/**************************************************************************/
+/*                                                                        */
+/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */
+/*                                                                        */
+/**************************************************************************/
+
+#define ITCM_BASE_NS                    0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_NS                 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_NS                    0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_NS               0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_NS               0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_NS               0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_NS               0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_NS               0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_NS               0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_NS                SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define SRAM7_AXI_BASE_NS               0x243C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */
+#define VENC_RAM_BASE_NS                0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS  0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS  0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS  0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS  0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_NS         0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_NS               0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_NS               0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_NS                SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */
+#define BKPSRAM_BASE_NS                 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge      */
+#define PERIPH_BASE_NS                  0x40000000UL /*!< Base address of : AHB/APB Peripherals                      */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_NS              PERIPH_BASE_NS
+#define AHB1PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00020000UL)
+#define APB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02000000UL)
+#define AHB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02020000UL)
+#define APB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04000000UL)
+#define AHB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04020000UL)
+#define APB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06000000UL)
+#define AHB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06020000UL)
+#define APB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08000000UL)
+#define AHB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0000UL)
+#define TIM3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0400UL)
+#define TIM4_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0800UL)
+#define TIM5_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0C00UL)
+#define TIM6_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1000UL)
+#define TIM7_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1400UL)
+#define TIM12_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1800UL)
+#define TIM13_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1C00UL)
+#define TIM14_BASE_NS                   (APB1PERIPH_BASE_NS + 0x2000UL)
+#define LPTIM1_BASE_NS                  (APB1PERIPH_BASE_NS + 0x2400UL)
+#define WWDG_BASE_NS                    (APB1PERIPH_BASE_NS + 0x2C00UL)
+#define TIM10_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3000UL)
+#define TIM11_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3400UL)
+#define SPI2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3800UL)
+#define SPI3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3C00UL)
+#define SPDIFRX_BASE_NS                 (APB1PERIPH_BASE_NS + 0x4000UL)
+#define USART2_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4400UL)
+#define USART3_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4800UL)
+#define UART4_BASE_NS                   (APB1PERIPH_BASE_NS + 0x4C00UL)
+#define UART5_BASE_NS                   (APB1PERIPH_BASE_NS + 0x5000UL)
+#define I2C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5400UL)
+#define I2C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5800UL)
+#define I2C3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5C00UL)
+#define I3C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6000UL)
+#define I3C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6400UL)
+#define UART7_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7800UL)
+#define UART8_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7C00UL)
+#define MDIOS_BASE_NS                   (APB1PERIPH_BASE_NS + 0x9400UL)
+#define FDCAN1_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA000UL)
+#define FDCAN_CONFIG_BASE_NS            (APB1PERIPH_BASE_NS + 0xA100UL)
+#define FDCAN2_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA400UL)
+#define FDCAN_CCU_BASE_NS               (APB1PERIPH_BASE_NS + 0xA800UL)
+#define SRAMCAN_BASE_NS                 (APB1PERIPH_BASE_NS + 0xC000UL)
+#define FDCAN3_BASE_NS                  (APB1PERIPH_BASE_NS + 0xE800UL)
+#define UCPD1_BASE_NS                   (APB1PERIPH_BASE_NS + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_NS                  (AHB1PERIPH_BASE_NS + 0x1000UL)
+#define GPDMA1_Channel0_BASE_NS         (GPDMA1_BASE_NS + 0x0050UL)
+#define GPDMA1_Channel1_BASE_NS         (GPDMA1_BASE_NS + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_NS         (GPDMA1_BASE_NS + 0x0150UL)
+#define GPDMA1_Channel3_BASE_NS         (GPDMA1_BASE_NS + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_NS         (GPDMA1_BASE_NS + 0x0250UL)
+#define GPDMA1_Channel5_BASE_NS         (GPDMA1_BASE_NS + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_NS         (GPDMA1_BASE_NS + 0x0350UL)
+#define GPDMA1_Channel7_BASE_NS         (GPDMA1_BASE_NS + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_NS         (GPDMA1_BASE_NS + 0x0450UL)
+#define GPDMA1_Channel9_BASE_NS         (GPDMA1_BASE_NS + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_NS        (GPDMA1_BASE_NS + 0x0550UL)
+#define GPDMA1_Channel11_BASE_NS        (GPDMA1_BASE_NS + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_NS        (GPDMA1_BASE_NS + 0x0650UL)
+#define GPDMA1_Channel13_BASE_NS        (GPDMA1_BASE_NS + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_NS        (GPDMA1_BASE_NS + 0x0750UL)
+#define GPDMA1_Channel15_BASE_NS        (GPDMA1_BASE_NS + 0x07D0UL)
+#define ADC1_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2000UL)
+#define ADC2_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2100UL)
+#define ADC12_COMMON_BASE_NS            (AHB1PERIPH_BASE_NS + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0000UL)
+#define TIM8_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0400UL)
+#define USART1_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1000UL)
+#define USART6_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1400UL)
+#define UART9_BASE_NS                   (APB2PERIPH_BASE_NS + 0x1800UL)
+#define USART10_BASE_NS                 (APB2PERIPH_BASE_NS + 0x1C00UL)
+#define SPI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3000UL)
+#define SPI4_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3400UL)
+#define TIM18_BASE_NS                   (APB2PERIPH_BASE_NS + 0x3C00UL)
+#define TIM15_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4000UL)
+#define TIM16_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4400UL)
+#define TIM17_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4800UL)
+#define TIM9_BASE_NS                    (APB2PERIPH_BASE_NS + 0x4C00UL)
+#define SPI5_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5000UL)
+#define SAI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5800UL)
+#define SAI1_Block_A_BASE_NS            (SAI1_BASE_NS + 0x0004UL)
+#define SAI1_Block_B_BASE_NS            (SAI1_BASE_NS + 0x0024UL)
+#define SAI2_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5C00UL)
+#define SAI2_Block_A_BASE_NS            (SAI2_BASE_NS + 0x0004UL)
+#define SAI2_Block_B_BASE_NS            (SAI2_BASE_NS + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_NS                  (AHB2PERIPH_BASE_NS + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_NS        (RAMCFG_BASE_NS)
+#define RAMCFG_SRAM2_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_NS         (RAMCFG_BASE_NS + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0500UL)
+#define MDF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x5000UL)
+#define MDF1_Filter0_BASE_NS            (MDF1_BASE_NS + 0x0080UL)
+#define MDF1_Filter1_BASE_NS            (MDF1_BASE_NS + 0x0100UL)
+#define MDF1_Filter2_BASE_NS            (MDF1_BASE_NS + 0x0180UL)
+#define MDF1_Filter3_BASE_NS            (MDF1_BASE_NS + 0x0200UL)
+#define MDF1_Filter4_BASE_NS            (MDF1_BASE_NS + 0x0280UL)
+#define MDF1_Filter5_BASE_NS            (MDF1_BASE_NS + 0x0300UL)
+#define ADF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x6000UL)
+#define ADF1_Filter0_BASE_NS            (ADF1_BASE_NS + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_NS                 (APB3PERIPH_BASE_NS + 0x0000UL)
+#define DBGMCU_BASE_NS                  (APB3PERIPH_BASE_NS + 0x1000UL)
+#define DFT_APB_BASE_NS                 (APB3PERIPH_BASE_NS + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x0000UL)
+#define HASH_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0400UL)
+#define HASH_DIGEST_BASE_NS             (AHB3PERIPH_BASE_NS + 0x0710UL)
+#define CRYP_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0800UL)
+#define SAES_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x1000UL)
+#define PKA_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x2000UL)
+#define RIFSC_BASE_NS                   (AHB3PERIPH_BASE_NS + 0x4000UL)
+#define RISAF1_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x6000UL)
+#define RISAF2_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x7000UL)
+#define RISAF3_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x8000UL)
+#define RISAF6_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xB000UL)
+#define RISAF7_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xC000UL)
+#define RISAF8_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xD000UL)
+#define RISAF9_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xE000UL)
+#define RISAF11_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x010000UL)
+#define RISAF12_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x011000UL)
+#define RISAF13_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x012000UL)
+#define RISAF14_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x013000UL)
+#define RISAF21_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x015000UL)
+#define RISAF22_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x016000UL)
+#define RISAF23_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_NS                     (APB4PERIPH_BASE_NS + 0x0800UL)
+#define LPUART1_BASE_NS                 (APB4PERIPH_BASE_NS + 0x0C00UL)
+#define SPI6_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1400UL)
+#define I2C4_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1C00UL)
+#define LPTIM2_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2400UL)
+#define LPTIM3_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2800UL)
+#define LPTIM4_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2C00UL)
+#define LPTIM5_BASE_NS                  (APB4PERIPH_BASE_NS + 0x3000UL)
+#define VREFBUF_BASE_NS                 (APB4PERIPH_BASE_NS + 0x3C00UL)
+#define RTC_BASE_NS                     (APB4PERIPH_BASE_NS + 0x4000UL)
+#define TAMP_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4400UL)
+#define IWDG_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4800UL)
+#define SERC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x7C00UL)
+#define SYSCFG_BASE_NS                  (APB4PERIPH_BASE_NS + 0x8000UL)
+#define BSEC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x9000UL)
+#define DTS_BASE_NS                     (APB4PERIPH_BASE_NS + 0xA000UL)
+#define DTS_Sensor0_BASE_NS             (DTS_BASE_NS + 0x0C0UL)
+#define DTS_Sensor1_BASE_NS             (DTS_BASE_NS + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0000UL)
+#define GPIOB_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0400UL)
+#define GPIOC_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0800UL)
+#define GPIOD_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0C00UL)
+#define GPIOE_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1000UL)
+#define GPIOF_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1400UL)
+#define GPIOG_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1800UL)
+#define GPIOH_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1C00UL)
+#define GPION_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3400UL)
+#define GPIOO_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3800UL)
+#define GPIOP_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3C00UL)
+#define GPIOQ_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x4000UL)
+#define PWR_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4800UL)
+#define CRC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4C00UL)
+#define EXTI_BASE_NS                    (AHB4PERIPH_BASE_NS + 0x5000UL)
+#define RCC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x1000UL)
+#define LTDC_Layer1_BASE_NS             (LTDC_BASE_NS + 0x0100UL)
+#define LTDC_Layer2_BASE_NS             (LTDC_BASE_NS + 0x0200UL)
+#define DCMIPP_BASE_NS                  (APB5PERIPH_BASE_NS + 0x2000UL)
+#define GFXTIM_BASE_NS                  (APB5PERIPH_BASE_NS + 0x4000UL)
+#define VENC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x5000UL)
+#define CSI_BASE_NS                     (APB5PERIPH_BASE_NS + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x0000UL)
+#define HPDMA1_Channel0_BASE_NS         (HPDMA1_BASE_NS + 0x0050UL)
+#define HPDMA1_Channel1_BASE_NS         (HPDMA1_BASE_NS + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_NS         (HPDMA1_BASE_NS + 0x0150UL)
+#define HPDMA1_Channel3_BASE_NS         (HPDMA1_BASE_NS + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_NS         (HPDMA1_BASE_NS + 0x0250UL)
+#define HPDMA1_Channel5_BASE_NS         (HPDMA1_BASE_NS + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_NS         (HPDMA1_BASE_NS + 0x0350UL)
+#define HPDMA1_Channel7_BASE_NS         (HPDMA1_BASE_NS + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_NS         (HPDMA1_BASE_NS + 0x0450UL)
+#define HPDMA1_Channel9_BASE_NS         (HPDMA1_BASE_NS + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_NS        (HPDMA1_BASE_NS + 0x0550UL)
+#define HPDMA1_Channel11_BASE_NS        (HPDMA1_BASE_NS + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_NS        (HPDMA1_BASE_NS + 0x0650UL)
+#define HPDMA1_Channel13_BASE_NS        (HPDMA1_BASE_NS + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_NS        (HPDMA1_BASE_NS + 0x0750UL)
+#define HPDMA1_Channel15_BASE_NS        (HPDMA1_BASE_NS + 0x07D0UL)
+#define DMA2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x1000UL)
+#define JPEG_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x3000UL)
+#define FMC_R_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x4000UL)
+#define FMC_Bank1_R_BASE_NS             (FMC_R_BASE_NS + 0x0000UL)
+#define FMC_Bank1E_R_BASE_NS            (FMC_R_BASE_NS + 0x0104UL)
+#define FMC_Bank3_R_BASE_NS             (FMC_R_BASE_NS + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_NS           (FMC_R_BASE_NS + 0x0140UL)
+#define FMC_Common_R_BASE_NS            (FMC_R_BASE_NS + 0x0020UL)
+#define XSPI1_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x5000UL)
+#define PSSI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x6400UL)
+#define SDMMC2_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x6800UL)
+#define DLYB_SDMMC2_BASE_NS             (AHB5PERIPH_BASE_NS + 0x6C00UL)
+#define SDMMC1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x7000UL)
+#define DLYB_SDMMC1_BASE_NS             (AHB5PERIPH_BASE_NS + 0x8000UL)
+#define DCMI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x8400UL)
+#define XSPI2_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xA000UL)
+#define XSPIM_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xB400UL)
+#define MCE1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xB800UL)
+#define MCE1_REGION1_BASE_NS            (MCE1_BASE_NS + 0x040UL)
+#define MCE1_REGION2_BASE_NS            (MCE1_BASE_NS + 0x050UL)
+#define MCE1_REGION3_BASE_NS            (MCE1_BASE_NS + 0x060UL)
+#define MCE1_REGION4_BASE_NS            (MCE1_BASE_NS + 0x070UL)
+#define MCE1_CONTEXT1_BASE_NS           (MCE1_BASE_NS + 0x240UL)
+#define MCE1_CONTEXT2_BASE_NS           (MCE1_BASE_NS + 0x270UL)
+#define MCE2_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xBC00UL)
+#define MCE2_REGION1_BASE_NS            (MCE2_BASE_NS + 0x040UL)
+#define MCE2_REGION2_BASE_NS            (MCE2_BASE_NS + 0x050UL)
+#define MCE2_REGION3_BASE_NS            (MCE2_BASE_NS + 0x060UL)
+#define MCE2_REGION4_BASE_NS            (MCE2_BASE_NS + 0x070UL)
+#define MCE2_CONTEXT1_BASE_NS           (MCE2_BASE_NS + 0x240UL)
+#define MCE2_CONTEXT2_BASE_NS           (MCE2_BASE_NS + 0x270UL)
+#define MCE3_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xC000UL)
+#define MCE3_REGION1_BASE_NS            (MCE3_BASE_NS + 0x040UL)
+#define MCE3_REGION2_BASE_NS            (MCE3_BASE_NS + 0x050UL)
+#define MCE3_REGION3_BASE_NS            (MCE3_BASE_NS + 0x060UL)
+#define MCE3_REGION4_BASE_NS            (MCE3_BASE_NS + 0x070UL)
+#define MCE3_CONTEXT1_BASE_NS           (MCE3_BASE_NS + 0x240UL)
+#define MCE3_CONTEXT2_BASE_NS           (MCE3_BASE_NS + 0x270UL)
+#define MCE4_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xE000UL)
+#define MCE4_REGION1_BASE_NS            (MCE4_BASE_NS + 0x040UL)
+#define MCE4_REGION2_BASE_NS            (MCE4_BASE_NS + 0x050UL)
+#define MCE4_REGION3_BASE_NS            (MCE4_BASE_NS + 0x060UL)
+#define MCE4_REGION4_BASE_NS            (MCE4_BASE_NS + 0x070UL)
+#define MCE4_CONTEXT1_BASE_NS           (MCE4_BASE_NS + 0x240UL)
+#define MCE4_CONTEXT2_BASE_NS           (MCE4_BASE_NS + 0x270UL)
+#define XSPI3_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xD000UL)
+#define GFXMMU_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x010000UL)
+#define GPU2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x014000UL)
+#define GPUCACHE_BASE_NS                (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ICACHE_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ETH1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x016000UL)
+#define ETH1_MAC_BASE_NS                (ETH1_BASE_NS)
+#define USB1_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x020000UL)
+#define USB2_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x060000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_NS                     (0x46009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_NS                   (BOOTROM_BASE_NS + 0x0047ECUL)
+
+
+#if defined (CPU_IN_SECURE_STATE)
+/*********************************************************************/
+/*                                                                   */
+/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */
+/*                                                                   */
+/*********************************************************************/
+#define ITCM_BASE_S                     0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_S                  0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_S                     0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_S                0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_S                0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_S                0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_S                0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_S                0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_S                0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_S                 SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define SRAM7_AXI_BASE_S                0x343C0000UL /*!< Base address of 256 KB system RAM 7 accessible over AXI */
+#define VENC_RAM_BASE_S                 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_S   0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_S   0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_S   0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_S   0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_S          0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_S                0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_S                0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_S                 SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge  */
+#define BKPSRAM_BASE_S                  0x3C000000UL   /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge    */
+#define PERIPH_BASE_S                   0x50000000UL   /*!< Base address of : AHB/APB Peripherals                    */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_S               PERIPH_BASE_S
+#define AHB1PERIPH_BASE_S               (PERIPH_BASE_S + 0x00020000UL)
+#define APB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02000000UL)
+#define AHB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02020000UL)
+#define APB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04000000UL)
+#define AHB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04020000UL)
+#define APB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06000000UL)
+#define AHB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06020000UL)
+#define APB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08000000UL)
+#define AHB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_S                     (APB1PERIPH_BASE_S + 0x0000UL)
+#define TIM3_BASE_S                     (APB1PERIPH_BASE_S + 0x0400UL)
+#define TIM4_BASE_S                     (APB1PERIPH_BASE_S + 0x0800UL)
+#define TIM5_BASE_S                     (APB1PERIPH_BASE_S + 0x0C00UL)
+#define TIM6_BASE_S                     (APB1PERIPH_BASE_S + 0x1000UL)
+#define TIM7_BASE_S                     (APB1PERIPH_BASE_S + 0x1400UL)
+#define TIM12_BASE_S                    (APB1PERIPH_BASE_S + 0x1800UL)
+#define TIM13_BASE_S                    (APB1PERIPH_BASE_S + 0x1C00UL)
+#define TIM14_BASE_S                    (APB1PERIPH_BASE_S + 0x2000UL)
+#define LPTIM1_BASE_S                   (APB1PERIPH_BASE_S + 0x2400UL)
+#define WWDG_BASE_S                     (APB1PERIPH_BASE_S + 0x2C00UL)
+#define TIM10_BASE_S                    (APB1PERIPH_BASE_S + 0x3000UL)
+#define TIM11_BASE_S                    (APB1PERIPH_BASE_S + 0x3400UL)
+#define SPI2_BASE_S                     (APB1PERIPH_BASE_S + 0x3800UL)
+#define SPI3_BASE_S                     (APB1PERIPH_BASE_S + 0x3C00UL)
+#define SPDIFRX_BASE_S                  (APB1PERIPH_BASE_S + 0x4000UL)
+#define USART2_BASE_S                   (APB1PERIPH_BASE_S + 0x4400UL)
+#define USART3_BASE_S                   (APB1PERIPH_BASE_S + 0x4800UL)
+#define UART4_BASE_S                    (APB1PERIPH_BASE_S + 0x4C00UL)
+#define UART5_BASE_S                    (APB1PERIPH_BASE_S + 0x5000UL)
+#define I2C1_BASE_S                     (APB1PERIPH_BASE_S + 0x5400UL)
+#define I2C2_BASE_S                     (APB1PERIPH_BASE_S + 0x5800UL)
+#define I2C3_BASE_S                     (APB1PERIPH_BASE_S + 0x5C00UL)
+#define I3C1_BASE_S                     (APB1PERIPH_BASE_S + 0x6000UL)
+#define I3C2_BASE_S                     (APB1PERIPH_BASE_S + 0x6400UL)
+#define UART7_BASE_S                    (APB1PERIPH_BASE_S + 0x7800UL)
+#define UART8_BASE_S                    (APB1PERIPH_BASE_S + 0x7C00UL)
+#define MDIOS_BASE_S                    (APB1PERIPH_BASE_S + 0x9400UL)
+#define FDCAN1_BASE_S                   (APB1PERIPH_BASE_S + 0xA000UL)
+#define FDCAN_CONFIG_BASE_S             (APB1PERIPH_BASE_S + 0xA100UL)
+#define FDCAN2_BASE_S                   (APB1PERIPH_BASE_S + 0xA400UL)
+#define FDCAN_CCU_BASE_S                (APB1PERIPH_BASE_S + 0xA800UL)
+#define SRAMCAN_BASE_S                  (APB1PERIPH_BASE_S + 0xC000UL)
+#define FDCAN3_BASE_S                   (APB1PERIPH_BASE_S + 0xE800UL)
+#define UCPD1_BASE_S                    (APB1PERIPH_BASE_S + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_S                   (AHB1PERIPH_BASE_S + 0x1000UL)
+#define GPDMA1_Channel0_BASE_S          (GPDMA1_BASE_S + 0x0050UL)
+#define GPDMA1_Channel1_BASE_S          (GPDMA1_BASE_S + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_S          (GPDMA1_BASE_S + 0x0150UL)
+#define GPDMA1_Channel3_BASE_S          (GPDMA1_BASE_S + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_S          (GPDMA1_BASE_S + 0x0250UL)
+#define GPDMA1_Channel5_BASE_S          (GPDMA1_BASE_S + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_S          (GPDMA1_BASE_S + 0x0350UL)
+#define GPDMA1_Channel7_BASE_S          (GPDMA1_BASE_S + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_S          (GPDMA1_BASE_S + 0x0450UL)
+#define GPDMA1_Channel9_BASE_S          (GPDMA1_BASE_S + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_S         (GPDMA1_BASE_S + 0x0550UL)
+#define GPDMA1_Channel11_BASE_S         (GPDMA1_BASE_S + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_S         (GPDMA1_BASE_S + 0x0650UL)
+#define GPDMA1_Channel13_BASE_S         (GPDMA1_BASE_S + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_S         (GPDMA1_BASE_S + 0x0750UL)
+#define GPDMA1_Channel15_BASE_S         (GPDMA1_BASE_S + 0x07D0UL)
+#define ADC1_BASE_S                     (AHB1PERIPH_BASE_S + 0x2000UL)
+#define ADC2_BASE_S                     (AHB1PERIPH_BASE_S + 0x2100UL)
+#define ADC12_COMMON_BASE_S             (AHB1PERIPH_BASE_S + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_S                     (APB2PERIPH_BASE_S + 0x0000UL)
+#define TIM8_BASE_S                     (APB2PERIPH_BASE_S + 0x0400UL)
+#define USART1_BASE_S                   (APB2PERIPH_BASE_S + 0x1000UL)
+#define USART6_BASE_S                   (APB2PERIPH_BASE_S + 0x1400UL)
+#define UART9_BASE_S                    (APB2PERIPH_BASE_S + 0x1800UL)
+#define USART10_BASE_S                  (APB2PERIPH_BASE_S + 0x1C00UL)
+#define SPI1_BASE_S                     (APB2PERIPH_BASE_S + 0x3000UL)
+#define SPI4_BASE_S                     (APB2PERIPH_BASE_S + 0x3400UL)
+#define TIM18_BASE_S                    (APB2PERIPH_BASE_S + 0x3C00UL)
+#define TIM15_BASE_S                    (APB2PERIPH_BASE_S + 0x4000UL)
+#define TIM16_BASE_S                    (APB2PERIPH_BASE_S + 0x4400UL)
+#define TIM17_BASE_S                    (APB2PERIPH_BASE_S + 0x4800UL)
+#define TIM9_BASE_S                     (APB2PERIPH_BASE_S + 0x4C00UL)
+#define SPI5_BASE_S                     (APB2PERIPH_BASE_S + 0x5000UL)
+#define SAI1_BASE_S                     (APB2PERIPH_BASE_S + 0x5800UL)
+#define SAI1_Block_A_BASE_S             (SAI1_BASE_S + 0x0004UL)
+#define SAI1_Block_B_BASE_S             (SAI1_BASE_S + 0x0024UL)
+#define SAI2_BASE_S                     (APB2PERIPH_BASE_S + 0x5C00UL)
+#define SAI2_Block_A_BASE_S             (SAI2_BASE_S + 0x0004UL)
+#define SAI2_Block_B_BASE_S             (SAI2_BASE_S + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_S                   (AHB2PERIPH_BASE_S + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_S         (RAMCFG_BASE_S)
+#define RAMCFG_SRAM2_AXI_BASE_S         (RAMCFG_BASE_S + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_S         (RAMCFG_BASE_S + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_S         (RAMCFG_BASE_S + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_S         (RAMCFG_BASE_S + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_S         (RAMCFG_BASE_S + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_S         (RAMCFG_BASE_S + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_S         (RAMCFG_BASE_S + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_S          (RAMCFG_BASE_S + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_S           (RAMCFG_BASE_S + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_S           (RAMCFG_BASE_S + 0x0500UL)
+#define MDF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x5000UL)
+#define MDF1_Filter0_BASE_S             (MDF1_BASE_S + 0x0080UL)
+#define MDF1_Filter1_BASE_S             (MDF1_BASE_S + 0x0100UL)
+#define MDF1_Filter2_BASE_S             (MDF1_BASE_S + 0x0180UL)
+#define MDF1_Filter3_BASE_S             (MDF1_BASE_S + 0x0200UL)
+#define MDF1_Filter4_BASE_S             (MDF1_BASE_S + 0x0280UL)
+#define MDF1_Filter5_BASE_S             (MDF1_BASE_S + 0x0300UL)
+#define ADF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x6000UL)
+#define ADF1_Filter0_BASE_S             (ADF1_BASE_S + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_S                  (APB3PERIPH_BASE_S + 0x0000UL)
+#define DBGMCU_BASE_S                   (APB3PERIPH_BASE_S + 0x1000UL)
+#define DFT_APB_BASE_S                  (APB3PERIPH_BASE_S + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_S                      (AHB3PERIPH_BASE_S + 0x0000UL)
+#define HASH_BASE_S                     (AHB3PERIPH_BASE_S + 0x0400UL)
+#define HASH_DIGEST_BASE_S              (AHB3PERIPH_BASE_S + 0x0710UL)
+#define CRYP_BASE_S                     (AHB3PERIPH_BASE_S + 0x0800UL)
+#define SAES_BASE_S                     (AHB3PERIPH_BASE_S + 0x1000UL)
+#define PKA_BASE_S                      (AHB3PERIPH_BASE_S + 0x2000UL)
+#define RIFSC_BASE_S                    (AHB3PERIPH_BASE_S + 0x4000UL)
+#define IAC_BASE_S                      (AHB3PERIPH_BASE_S + 0x5000UL)
+#define RISAF1_BASE_S                   (AHB3PERIPH_BASE_S + 0x6000UL)
+#define RISAF2_BASE_S                   (AHB3PERIPH_BASE_S + 0x7000UL)
+#define RISAF3_BASE_S                   (AHB3PERIPH_BASE_S + 0x8000UL)
+#define RISAF6_BASE_S                   (AHB3PERIPH_BASE_S + 0xB000UL)
+#define RISAF7_BASE_S                   (AHB3PERIPH_BASE_S + 0xC000UL)
+#define RISAF8_BASE_S                   (AHB3PERIPH_BASE_S + 0xD000UL)
+#define RISAF9_BASE_S                   (AHB3PERIPH_BASE_S + 0xE000UL)
+#define RISAF11_BASE_S                  (AHB3PERIPH_BASE_S + 0x010000UL)
+#define RISAF12_BASE_S                  (AHB3PERIPH_BASE_S + 0x011000UL)
+#define RISAF13_BASE_S                  (AHB3PERIPH_BASE_S + 0x012000UL)
+#define RISAF14_BASE_S                  (AHB3PERIPH_BASE_S + 0x013000UL)
+#define RISAF21_BASE_S                  (AHB3PERIPH_BASE_S + 0x015000UL)
+#define RISAF22_BASE_S                  (AHB3PERIPH_BASE_S + 0x016000UL)
+#define RISAF23_BASE_S                  (AHB3PERIPH_BASE_S + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_S                      (APB4PERIPH_BASE_S + 0x0800UL)
+#define LPUART1_BASE_S                  (APB4PERIPH_BASE_S + 0x0C00UL)
+#define SPI6_BASE_S                     (APB4PERIPH_BASE_S + 0x1400UL)
+#define I2C4_BASE_S                     (APB4PERIPH_BASE_S + 0x1C00UL)
+#define LPTIM2_BASE_S                   (APB4PERIPH_BASE_S + 0x2400UL)
+#define LPTIM3_BASE_S                   (APB4PERIPH_BASE_S + 0x2800UL)
+#define LPTIM4_BASE_S                   (APB4PERIPH_BASE_S + 0x2C00UL)
+#define LPTIM5_BASE_S                   (APB4PERIPH_BASE_S + 0x3000UL)
+#define VREFBUF_BASE_S                  (APB4PERIPH_BASE_S + 0x3C00UL)
+#define RTC_BASE_S                      (APB4PERIPH_BASE_S + 0x4000UL)
+#define TAMP_BASE_S                     (APB4PERIPH_BASE_S + 0x4400UL)
+#define IWDG_BASE_S                     (APB4PERIPH_BASE_S + 0x4800UL)
+
+#define SERC_BASE_S                     (APB4PERIPH_BASE_S + 0x7C00UL)
+#define SYSCFG_BASE_S                   (APB4PERIPH_BASE_S + 0x8000UL)
+#define BSEC_BASE_S                     (APB4PERIPH_BASE_S + 0x9000UL)
+#define DTS_BASE_S                      (APB4PERIPH_BASE_S + 0xA000UL)
+#define DTS_Sensor0_BASE_S              (DTS_BASE_S + 0x0C0UL)
+#define DTS_Sensor1_BASE_S              (DTS_BASE_S + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_S                    (AHB4PERIPH_BASE_S + 0x0000UL)
+#define GPIOB_BASE_S                    (AHB4PERIPH_BASE_S + 0x0400UL)
+#define GPIOC_BASE_S                    (AHB4PERIPH_BASE_S + 0x0800UL)
+#define GPIOD_BASE_S                    (AHB4PERIPH_BASE_S + 0x0C00UL)
+#define GPIOE_BASE_S                    (AHB4PERIPH_BASE_S + 0x1000UL)
+#define GPIOF_BASE_S                    (AHB4PERIPH_BASE_S + 0x1400UL)
+#define GPIOG_BASE_S                    (AHB4PERIPH_BASE_S + 0x1800UL)
+#define GPIOH_BASE_S                    (AHB4PERIPH_BASE_S + 0x1C00UL)
+#define GPION_BASE_S                    (AHB4PERIPH_BASE_S + 0x3400UL)
+#define GPIOO_BASE_S                    (AHB4PERIPH_BASE_S + 0x3800UL)
+#define GPIOP_BASE_S                    (AHB4PERIPH_BASE_S + 0x3C00UL)
+#define GPIOQ_BASE_S                    (AHB4PERIPH_BASE_S + 0x4000UL)
+#define PWR_BASE_S                      (AHB4PERIPH_BASE_S + 0x4800UL)
+#define CRC_BASE_S                      (AHB4PERIPH_BASE_S + 0x4C00UL)
+#define EXTI_BASE_S                     (AHB4PERIPH_BASE_S + 0x5000UL)
+#define RCC_BASE_S                      (AHB4PERIPH_BASE_S + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_S                     (APB5PERIPH_BASE_S + 0x1000UL)
+#define LTDC_Layer1_BASE_S              (LTDC_BASE_S + 0x0100UL)
+#define LTDC_Layer2_BASE_S              (LTDC_BASE_S + 0x0200UL)
+#define DCMIPP_BASE_S                   (APB5PERIPH_BASE_S + 0x2000UL)
+#define GFXTIM_BASE_S                   (APB5PERIPH_BASE_S + 0x4000UL)
+#define VENC_BASE_S                     (APB5PERIPH_BASE_S + 0x5000UL)
+#define CSI_BASE_S                      (APB5PERIPH_BASE_S + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_S                   (AHB5PERIPH_BASE_S + 0x0000UL)
+#define HPDMA1_Channel0_BASE_S          (HPDMA1_BASE_S + 0x0050UL)
+#define HPDMA1_Channel1_BASE_S          (HPDMA1_BASE_S + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_S          (HPDMA1_BASE_S + 0x0150UL)
+#define HPDMA1_Channel3_BASE_S          (HPDMA1_BASE_S + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_S          (HPDMA1_BASE_S + 0x0250UL)
+#define HPDMA1_Channel5_BASE_S          (HPDMA1_BASE_S + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_S          (HPDMA1_BASE_S + 0x0350UL)
+#define HPDMA1_Channel7_BASE_S          (HPDMA1_BASE_S + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_S          (HPDMA1_BASE_S + 0x0450UL)
+#define HPDMA1_Channel9_BASE_S          (HPDMA1_BASE_S + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_S         (HPDMA1_BASE_S + 0x0550UL)
+#define HPDMA1_Channel11_BASE_S         (HPDMA1_BASE_S + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_S         (HPDMA1_BASE_S + 0x0650UL)
+#define HPDMA1_Channel13_BASE_S         (HPDMA1_BASE_S + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_S         (HPDMA1_BASE_S + 0x0750UL)
+#define HPDMA1_Channel15_BASE_S         (HPDMA1_BASE_S + 0x07D0UL)
+#define DMA2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x1000UL)
+#define JPEG_BASE_S                     (AHB5PERIPH_BASE_S + 0x3000UL)
+#define FMC_R_BASE_S                    (AHB5PERIPH_BASE_S + 0x4000UL)
+#define FMC_Bank1_R_BASE_S              (FMC_R_BASE_S + 0x0000UL)
+#define FMC_Bank1E_R_BASE_S             (FMC_R_BASE_S + 0x0104UL)
+#define FMC_Bank3_R_BASE_S              (FMC_R_BASE_S + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_S            (FMC_R_BASE_S + 0x0140UL)
+#define FMC_Common_R_BASE_S             (FMC_R_BASE_S + 0x0020UL)
+#define XSPI1_BASE_S                    (AHB5PERIPH_BASE_S + 0x5000UL)
+#define PSSI_BASE_S                     (AHB5PERIPH_BASE_S + 0x6400UL)
+#define SDMMC2_BASE_S                   (AHB5PERIPH_BASE_S + 0x6800UL)
+#define DLYB_SDMMC2_BASE_S              (AHB5PERIPH_BASE_S + 0x6C00UL)
+#define SDMMC1_BASE_S                   (AHB5PERIPH_BASE_S + 0x7000UL)
+#define DLYB_SDMMC1_BASE_S              (AHB5PERIPH_BASE_S + 0x8000UL)
+#define DCMI_BASE_S                     (AHB5PERIPH_BASE_S + 0x8400UL)
+#define XSPI2_BASE_S                    (AHB5PERIPH_BASE_S + 0xA000UL)
+#define XSPIM_BASE_S                    (AHB5PERIPH_BASE_S + 0xB400UL)
+#define MCE1_BASE_S                     (AHB5PERIPH_BASE_S + 0xB800UL)
+#define MCE1_REGION1_BASE_S             (MCE1_BASE_S + 0x040UL)
+#define MCE1_REGION2_BASE_S             (MCE1_BASE_S + 0x050UL)
+#define MCE1_REGION3_BASE_S             (MCE1_BASE_S + 0x060UL)
+#define MCE1_REGION4_BASE_S             (MCE1_BASE_S + 0x070UL)
+#define MCE1_CONTEXT1_BASE_S            (MCE1_BASE_S + 0x240UL)
+#define MCE1_CONTEXT2_BASE_S            (MCE1_BASE_S + 0x270UL)
+#define MCE2_BASE_S                     (AHB5PERIPH_BASE_S + 0xBC00UL)
+#define MCE2_REGION1_BASE_S             (MCE2_BASE_S + 0x040UL)
+#define MCE2_REGION2_BASE_S             (MCE2_BASE_S + 0x050UL)
+#define MCE2_REGION3_BASE_S             (MCE2_BASE_S + 0x060UL)
+#define MCE2_REGION4_BASE_S             (MCE2_BASE_S + 0x070UL)
+#define MCE2_CONTEXT1_BASE_S            (MCE2_BASE_S + 0x240UL)
+#define MCE2_CONTEXT2_BASE_S            (MCE2_BASE_S + 0x270UL)
+#define MCE3_BASE_S                     (AHB5PERIPH_BASE_S + 0xC000UL)
+#define MCE3_REGION1_BASE_S             (MCE3_BASE_S + 0x040UL)
+#define MCE3_REGION2_BASE_S             (MCE3_BASE_S + 0x050UL)
+#define MCE3_REGION3_BASE_S             (MCE3_BASE_S + 0x060UL)
+#define MCE3_REGION4_BASE_S             (MCE3_BASE_S + 0x070UL)
+#define MCE3_CONTEXT1_BASE_S            (MCE3_BASE_S + 0x240UL)
+#define MCE3_CONTEXT2_BASE_S            (MCE3_BASE_S + 0x270UL)
+#define MCE4_BASE_S                     (AHB5PERIPH_BASE_S + 0xE000UL)
+#define MCE4_REGION1_BASE_S             (MCE4_BASE_S + 0x040UL)
+#define MCE4_REGION2_BASE_S             (MCE4_BASE_S + 0x050UL)
+#define MCE4_REGION3_BASE_S             (MCE4_BASE_S + 0x060UL)
+#define MCE4_REGION4_BASE_S             (MCE4_BASE_S + 0x070UL)
+#define MCE4_CONTEXT1_BASE_S            (MCE4_BASE_S + 0x240UL)
+#define MCE4_CONTEXT2_BASE_S            (MCE4_BASE_S + 0x270UL)
+#define XSPI3_BASE_S                    (AHB5PERIPH_BASE_S + 0xD000UL)
+#define GFXMMU_BASE_S                   (AHB5PERIPH_BASE_S + 0x010000UL)
+#define GPU2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x014000UL)
+#define GPUCACHE_BASE_S                 (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ICACHE_BASE_S                   (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ETH1_BASE_S                     (AHB5PERIPH_BASE_S + 0x016000UL)
+#define ETH1_MAC_BASE_S                 (ETH1_BASE_S)
+#define USB1_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x020000UL)
+#define USB2_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x060000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_S                      (0x56009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_S                    (BOOTROM_BASE_S + 0x0047ECUL)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_declaration
+  * @{
+  */
+#define ADC12_COMMON_NS           ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
+#define ADC1_NS                   ((ADC_TypeDef *) ADC1_BASE_NS)
+#define ADC2_NS                   ((ADC_TypeDef *) ADC2_BASE_NS)
+#define ADF1_NS                   ((MDF_TypeDef *) ADF1_BASE_NS)
+#define ADF1_Filter0_NS           ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS)
+#define BSEC_NS                   ((BSEC_TypeDef *) BSEC_BASE_NS)
+#define CRC_NS                    ((CRC_TypeDef *) CRC_BASE_NS)
+#define CRYP_NS                   ((CRYP_TypeDef *) CRYP_BASE_NS)
+#define CSI_NS                    ((CSI_TypeDef *) CSI_BASE_NS)
+#define DBGMCU_NS                 ((DBGMCU_TypeDef *) DBGMCU_BASE_NS)
+#define DCMI_NS                   ((DCMI_TypeDef *) DCMI_BASE_NS)
+#define DCMIPP_NS                 ((DCMIPP_TypeDef *) DCMIPP_BASE_NS)
+#define DLYB_SDMMC1_NS            ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
+#define DLYB_SDMMC2_NS            ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
+#define DMA2D_NS                  ((DMA2D_TypeDef *) DMA2D_BASE_NS)
+#define DTS_NS                    ((DTS_TypeDef *) DTS_BASE_NS)
+#define DTS_Sensor0_NS            ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS)
+#define DTS_Sensor1_NS            ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS)
+#define ETH1_NS                   ((ETH_TypeDef *) ETH1_BASE_NS)
+#define EXTI_NS                   ((EXTI_TypeDef *) EXTI_BASE_NS)
+#define FDCAN1_NS                 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
+#define FDCAN2_NS                 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS)
+#define FDCAN3_NS                 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS)
+#define FDCAN_CCU_NS              ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS)
+#define FDCAN_CONFIG_NS           ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
+#define FMC_Bank1E_R_NS           ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
+#define FMC_Bank1_R_NS            ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
+#define FMC_Bank3_R_NS            ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
+#define FMC_Bank5_6_R_NS          ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS)
+#define FMC_Common_R_NS           ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS)
+#define GFXMMU_NS                 ((GFXMMU_TypeDef *) GFXMMU_BASE_NS)
+#define GFXTIM_NS                 ((GFXTIM_TypeDef *) GFXTIM_BASE_NS)
+#define GPDMA1_NS                 ((DMA_TypeDef *) GPDMA1_BASE_NS)
+#define GPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
+#define GPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
+#define GPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
+#define GPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
+#define GPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
+#define GPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
+#define GPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
+#define GPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
+#define GPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
+#define GPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
+#define GPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
+#define GPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
+#define GPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
+#define GPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
+#define GPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
+#define GPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
+#define GPIOA_NS                  ((GPIO_TypeDef *) GPIOA_BASE_NS)
+#define GPIOB_NS                  ((GPIO_TypeDef *) GPIOB_BASE_NS)
+#define GPIOC_NS                  ((GPIO_TypeDef *) GPIOC_BASE_NS)
+#define GPIOD_NS                  ((GPIO_TypeDef *) GPIOD_BASE_NS)
+#define GPIOE_NS                  ((GPIO_TypeDef *) GPIOE_BASE_NS)
+#define GPIOF_NS                  ((GPIO_TypeDef *) GPIOF_BASE_NS)
+#define GPIOG_NS                  ((GPIO_TypeDef *) GPIOG_BASE_NS)
+#define GPIOH_NS                  ((GPIO_TypeDef *) GPIOH_BASE_NS)
+#define GPION_NS                  ((GPIO_TypeDef *) GPION_BASE_NS)
+#define GPIOO_NS                  ((GPIO_TypeDef *) GPIOO_BASE_NS)
+#define GPIOP_NS                  ((GPIO_TypeDef *) GPIOP_BASE_NS)
+#define GPIOQ_NS                  ((GPIO_TypeDef *) GPIOQ_BASE_NS)
+#define HASH_NS                   ((HASH_TypeDef *) HASH_BASE_NS)
+#define HASH_DIGEST_NS            ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
+#define HPDMA1_NS                 ((DMA_TypeDef *) HPDMA1_BASE_NS)
+#define HPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS)
+#define HPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS)
+#define HPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS)
+#define HPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS)
+#define HPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS)
+#define HPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS)
+#define HPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS)
+#define HPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS)
+#define HPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS)
+#define HPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS)
+#define HPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS)
+#define HPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS)
+#define HPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS)
+#define HPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS)
+#define HPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS)
+#define HPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS)
+#define I2C1_NS                   ((I2C_TypeDef *) I2C1_BASE_NS)
+#define I2C2_NS                   ((I2C_TypeDef *) I2C2_BASE_NS)
+#define I2C3_NS                   ((I2C_TypeDef *) I2C3_BASE_NS)
+#define I2C4_NS                   ((I2C_TypeDef *) I2C4_BASE_NS)
+#define I3C1_NS                   ((I3C_TypeDef *) I3C1_BASE_NS)
+#define I3C2_NS                   ((I3C_TypeDef *) I3C2_BASE_NS)
+#define ICACHE_NS                 ((ICACHE_TypeDef *) ICACHE_BASE_NS)
+#define IWDG_NS                   ((IWDG_TypeDef *) IWDG_BASE_NS)
+#define JPEG_NS                   ((JPEG_TypeDef *) JPEG_BASE_NS)
+#define LPTIM1_NS                 ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
+#define LPTIM2_NS                 ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
+#define LPTIM3_NS                 ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
+#define LPTIM4_NS                 ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
+#define LPTIM5_NS                 ((LPTIM_TypeDef *) LPTIM5_BASE_NS)
+#define LPUART1_NS                ((USART_TypeDef *) LPUART1_BASE_NS)
+#define LTDC_NS                   ((LTDC_TypeDef *)LTDC_BASE_NS)
+#define LTDC_Layer1_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS)
+#define LTDC_Layer2_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS)
+#define MCE1_NS                   ((MCE_TypeDef *) MCE1_BASE_NS)
+#define MCE1_REGION1_NS           ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS)
+#define MCE1_REGION2_NS           ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS)
+#define MCE1_REGION3_NS           ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS)
+#define MCE1_REGION4_NS           ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS)
+#define MCE1_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS)
+#define MCE1_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS)
+#define MCE2_NS                   ((MCE_TypeDef *) MCE2_BASE_NS)
+#define MCE2_REGION1_NS           ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS)
+#define MCE2_REGION2_NS           ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS)
+#define MCE2_REGION3_NS           ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS)
+#define MCE2_REGION4_NS           ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS)
+#define MCE2_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS)
+#define MCE2_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS)
+#define MCE3_NS                   ((MCE_TypeDef *) MCE3_BASE_NS)
+#define MCE3_REGION1_NS           ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS)
+#define MCE3_REGION2_NS           ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS)
+#define MCE3_REGION3_NS           ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS)
+#define MCE3_REGION4_NS           ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS)
+#define MCE3_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS)
+#define MCE3_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS)
+#define MCE4_NS                   ((MCE_TypeDef *) MCE4_BASE_NS)
+#define MCE4_REGION1_NS           ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS)
+#define MCE4_REGION2_NS           ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS)
+#define MCE4_REGION3_NS           ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS)
+#define MCE4_REGION4_NS           ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS)
+#define MCE4_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS)
+#define MCE4_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS)
+#define MDF1_NS                   ((MDF_TypeDef *) MDF1_BASE_NS)
+#define MDF1_Filter0_NS           ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS)
+#define MDF1_Filter1_NS           ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS)
+#define MDF1_Filter2_NS           ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS)
+#define MDF1_Filter3_NS           ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS)
+#define MDF1_Filter4_NS           ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS)
+#define MDF1_Filter5_NS           ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS)
+#define MDIOS_NS                  ((MDIOS_TypeDef *) MDIOS_BASE_NS)
+#define PKA_NS                    ((PKA_TypeDef *) PKA_BASE_NS)
+#define PSSI_NS                   ((PSSI_TypeDef *) PSSI_BASE_NS)
+#define PWR_NS                    ((PWR_TypeDef *) PWR_BASE_NS)
+#define RAMCFG_NS                 ((RAMCFG_TypeDef *) RAMCFG_BASE_NS)
+#define RAMCFG_SRAM1_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS)
+#define RAMCFG_SRAM2_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS)
+#define RAMCFG_SRAM3_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS)
+#define RAMCFG_SRAM4_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS)
+#define RAMCFG_SRAM5_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS)
+#define RAMCFG_SRAM6_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS)
+#define RAMCFG_SRAM1_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS)
+#define RAMCFG_SRAM2_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS)
+#define RAMCFG_VENC_RAM_NS        ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS)
+#define RAMCFG_FLEXRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS)
+#define RCC_NS                    ((RCC_TypeDef *) RCC_BASE_NS)
+#define RIFSC_NS                  ((RIFSC_TypeDef *) RIFSC_BASE_NS)
+#define RISAF1_NS                 ((RISAF_TypeDef *) RISAF1_BASE_NS)
+#define RISAF2_NS                 ((RISAF_TypeDef *) RISAF2_BASE_NS)
+#define RISAF3_NS                 ((RISAF_TypeDef *) RISAF3_BASE_NS)
+#define RISAF6_NS                 ((RISAF_TypeDef *) RISAF6_BASE_NS)
+#define RISAF7_NS                 ((RISAF_TypeDef *) RISAF7_BASE_NS)
+#define RISAF8_NS                 ((RISAF_TypeDef *) RISAF8_BASE_NS)
+#define RISAF9_NS                 ((RISAF_TypeDef *) RISAF9_BASE_NS)
+#define RISAF11_NS                ((RISAF_TypeDef *) RISAF11_BASE_NS)
+#define RISAF12_NS                ((RISAF_TypeDef *) RISAF12_BASE_NS)
+#define RISAF13_NS                ((RISAF_TypeDef *) RISAF13_BASE_NS)
+#define RISAF14_NS                ((RISAF_TypeDef *) RISAF14_BASE_NS)
+#define RISAF21_NS                ((RISAF_TypeDef *) RISAF21_BASE_NS)
+#define RISAF22_NS                ((RISAF_TypeDef *) RISAF22_BASE_NS)
+#define RISAF23_NS                ((RISAF_TypeDef *) RISAF23_BASE_NS)
+#define RNG_NS                    ((RNG_TypeDef *) RNG_BASE_NS)
+#define RTC_NS                    ((RTC_TypeDef *) RTC_BASE_NS)
+#define SAES_NS                   ((SAES_TypeDef *) SAES_BASE_NS)
+#define SAI1_NS                   ((SAI_TypeDef *) SAI1_BASE_NS)
+#define SAI1_Block_A_NS           ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS)
+#define SAI1_Block_B_NS           ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS)
+#define SAI2_NS                   ((SAI_TypeDef *) SAI2_BASE_NS)
+#define SAI2_Block_A_NS           ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS)
+#define SAI2_Block_B_NS           ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS)
+#define SDMMC1_NS                 ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
+#define SDMMC2_NS                 ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
+#define SPDIFRX_NS                ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS)
+#define SPI1_NS                   ((SPI_TypeDef *) SPI1_BASE_NS)
+#define SPI2_NS                   ((SPI_TypeDef *) SPI2_BASE_NS)
+#define SPI3_NS                   ((SPI_TypeDef *) SPI3_BASE_NS)
+#define SPI4_NS                   ((SPI_TypeDef *) SPI4_BASE_NS)
+#define SPI5_NS                   ((SPI_TypeDef *) SPI5_BASE_NS)
+#define SPI6_NS                   ((SPI_TypeDef *) SPI6_BASE_NS)
+#define SYSCFG_NS                 ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
+#define TAMP_NS                   ((TAMP_TypeDef *) TAMP_BASE_NS)
+#define TIM1_NS                   ((TIM_TypeDef *) TIM1_BASE_NS)
+#define TIM2_NS                   ((TIM_TypeDef *) TIM2_BASE_NS)
+#define TIM3_NS                   ((TIM_TypeDef *) TIM3_BASE_NS)
+#define TIM4_NS                   ((TIM_TypeDef *) TIM4_BASE_NS)
+#define TIM5_NS                   ((TIM_TypeDef *) TIM5_BASE_NS)
+#define TIM6_NS                   ((TIM_TypeDef *) TIM6_BASE_NS)
+#define TIM7_NS                   ((TIM_TypeDef *) TIM7_BASE_NS)
+#define TIM8_NS                   ((TIM_TypeDef *) TIM8_BASE_NS)
+#define TIM9_NS                   ((TIM_TypeDef *) TIM9_BASE_NS)
+#define TIM10_NS                  ((TIM_TypeDef *) TIM10_BASE_NS)
+#define TIM11_NS                  ((TIM_TypeDef *) TIM11_BASE_NS)
+#define TIM12_NS                  ((TIM_TypeDef *) TIM12_BASE_NS)
+#define TIM13_NS                  ((TIM_TypeDef *) TIM13_BASE_NS)
+#define TIM14_NS                  ((TIM_TypeDef *) TIM14_BASE_NS)
+#define TIM15_NS                  ((TIM_TypeDef *) TIM15_BASE_NS)
+#define TIM16_NS                  ((TIM_TypeDef *) TIM16_BASE_NS)
+#define TIM17_NS                  ((TIM_TypeDef *) TIM17_BASE_NS)
+#define TIM18_NS                  ((TIM_TypeDef *) TIM18_BASE_NS)
+#define UART4_NS                  ((USART_TypeDef *) UART4_BASE_NS)
+#define UART5_NS                  ((USART_TypeDef *) UART5_BASE_NS)
+#define UART7_NS                  ((USART_TypeDef *) UART7_BASE_NS)
+#define UART8_NS                  ((USART_TypeDef *) UART8_BASE_NS)
+#define UART9_NS                  ((USART_TypeDef *) UART9_BASE_NS)
+#define UCPD1_NS                  ((UCPD_TypeDef *) UCPD1_BASE_NS)
+#define USART1_NS                 ((USART_TypeDef *) USART1_BASE_NS)
+#define USART2_NS                 ((USART_TypeDef *) USART2_BASE_NS)
+#define USART3_NS                 ((USART_TypeDef *) USART3_BASE_NS)
+#define USART6_NS                 ((USART_TypeDef *) USART6_BASE_NS)
+#define USART10_NS                ((USART_TypeDef *) USART10_BASE_NS)
+#define USB1_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS)
+#define USB2_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS)
+#define USB1_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS)
+#define USB2_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS)
+#define VENC_NS                   ((VENC_TypeDef *) VENC_BASE_NS)
+#define VREFBUF_NS                ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
+#define WWDG_NS                   ((WWDG_TypeDef *) WWDG_BASE_NS)
+#define XSPI1_NS                  ((XSPI_TypeDef *) XSPI1_BASE_NS)
+#define XSPI2_NS                  ((XSPI_TypeDef *) XSPI2_BASE_NS)
+#define XSPI3_NS                  ((XSPI_TypeDef *) XSPI3_BASE_NS)
+#define XSPIM_NS                  ((XSPIM_TypeDef *) XSPIM_BASE_NS)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON_S            ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
+#define ADC1_S                    ((ADC_TypeDef *) ADC1_BASE_S)
+#define ADC2_S                    ((ADC_TypeDef *) ADC2_BASE_S)
+#define ADF1_S                    ((MDF_TypeDef *) ADF1_BASE_S)
+#define ADF1_Filter0_S            ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S)
+#define BSEC_S                    ((BSEC_TypeDef *) BSEC_BASE_S)
+#define CRC_S                     ((CRC_TypeDef *) CRC_BASE_S)
+#define CRYP_S                    ((CRYP_TypeDef *) CRYP_BASE_S)
+#define CSI_S                     ((CSI_TypeDef *) CSI_BASE_S)
+#define DBGMCU_S                  ((DBGMCU_TypeDef *) DBGMCU_BASE_S)
+#define DCMI_S                    ((DCMI_TypeDef *) DCMI_BASE_S)
+#define DCMIPP_S                  ((DCMIPP_TypeDef *) DCMIPP_BASE_S)
+#define DLYB_SDMMC1_S             ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
+#define DLYB_SDMMC2_S             ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
+#define DMA2D_S                   ((DMA2D_TypeDef *) DMA2D_BASE_S)
+#define DTS_S                     ((DTS_TypeDef *) DTS_BASE_S)
+#define DTS_Sensor0_S             ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S)
+#define DTS_Sensor1_S             ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S)
+#define ETH1_S                    ((ETH_TypeDef *) ETH1_BASE_S)
+#define EXTI_S                    ((EXTI_TypeDef *) EXTI_BASE_S)
+#define FDCAN1_S                  ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
+#define FDCAN2_S                  ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S)
+#define FDCAN3_S                  ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S)
+#define FDCAN_CCU_S               ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S)
+#define FDCAN_CONFIG_S            ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
+#define FMC_Bank1E_R_S            ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
+#define FMC_Bank1_R_S             ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
+#define FMC_Bank3_R_S             ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
+#define FMC_Bank5_6_R_S           ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S)
+#define FMC_Common_R_S            ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S)
+#define GFXMMU_S                  ((GFXMMU_TypeDef *) GFXMMU_BASE_S)
+#define GFXTIM_S                  ((GFXTIM_TypeDef *) GFXTIM_BASE_S)
+#define GPDMA1_S                  ((DMA_TypeDef *) GPDMA1_BASE_S)
+#define GPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
+#define GPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
+#define GPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
+#define GPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
+#define GPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
+#define GPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
+#define GPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
+#define GPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
+#define GPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
+#define GPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
+#define GPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
+#define GPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
+#define GPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
+#define GPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
+#define GPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
+#define GPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
+#define GPIOA_S                   ((GPIO_TypeDef *) GPIOA_BASE_S)
+#define GPIOB_S                   ((GPIO_TypeDef *) GPIOB_BASE_S)
+#define GPIOC_S                   ((GPIO_TypeDef *) GPIOC_BASE_S)
+#define GPIOD_S                   ((GPIO_TypeDef *) GPIOD_BASE_S)
+#define GPIOE_S                   ((GPIO_TypeDef *) GPIOE_BASE_S)
+#define GPIOF_S                   ((GPIO_TypeDef *) GPIOF_BASE_S)
+#define GPIOG_S                   ((GPIO_TypeDef *) GPIOG_BASE_S)
+#define GPIOH_S                   ((GPIO_TypeDef *) GPIOH_BASE_S)
+#define GPION_S                   ((GPIO_TypeDef *) GPION_BASE_S)
+#define GPIOO_S                   ((GPIO_TypeDef *) GPIOO_BASE_S)
+#define GPIOP_S                   ((GPIO_TypeDef *) GPIOP_BASE_S)
+#define GPIOQ_S                   ((GPIO_TypeDef *) GPIOQ_BASE_S)
+#define HASH_S                    ((HASH_TypeDef *) HASH_BASE_S)
+#define HASH_DIGEST_S             ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
+#define HPDMA1_S                  ((DMA_TypeDef *) HPDMA1_BASE_S)
+#define HPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S)
+#define HPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S)
+#define HPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S)
+#define HPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S)
+#define HPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S)
+#define HPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S)
+#define HPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S)
+#define HPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S)
+#define HPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S)
+#define HPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S)
+#define HPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S)
+#define HPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S)
+#define HPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S)
+#define HPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S)
+#define HPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S)
+#define HPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S)
+#define I2C1_S                    ((I2C_TypeDef *) I2C1_BASE_S)
+#define I2C2_S                    ((I2C_TypeDef *) I2C2_BASE_S)
+#define I2C3_S                    ((I2C_TypeDef *) I2C3_BASE_S)
+#define I2C4_S                    ((I2C_TypeDef *) I2C4_BASE_S)
+#define I3C1_S                    ((I3C_TypeDef *) I3C1_BASE_S)
+#define I3C2_S                    ((I3C_TypeDef *) I3C2_BASE_S)
+#define IAC_S                     ((IAC_TypeDef *) IAC_BASE_S)
+#define ICACHE_S                  ((ICACHE_TypeDef *) ICACHE_BASE_S)
+#define IWDG_S                    ((IWDG_TypeDef *) IWDG_BASE_S)
+#define JPEG_S                    ((JPEG_TypeDef *) JPEG_BASE_S)
+#define LPTIM1_S                  ((LPTIM_TypeDef *) LPTIM1_BASE_S)
+#define LPTIM2_S                  ((LPTIM_TypeDef *) LPTIM2_BASE_S)
+#define LPTIM3_S                  ((LPTIM_TypeDef *) LPTIM3_BASE_S)
+#define LPTIM4_S                  ((LPTIM_TypeDef *) LPTIM4_BASE_S)
+#define LPTIM5_S                  ((LPTIM_TypeDef *) LPTIM5_BASE_S)
+#define LPUART1_S                 ((USART_TypeDef *) LPUART1_BASE_S)
+#define LTDC_S                    ((LTDC_TypeDef *)LTDC_BASE_S)
+#define LTDC_Layer1_S             ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S)
+#define LTDC_Layer2_S             ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S)
+#define MCE1_S                    ((MCE_TypeDef *) MCE1_BASE_S)
+#define MCE1_REGION1_S            ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S)
+#define MCE1_REGION2_S            ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S)
+#define MCE1_REGION3_S            ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S)
+#define MCE1_REGION4_S            ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S)
+#define MCE1_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S)
+#define MCE1_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S)
+#define MCE2_S                    ((MCE_TypeDef *) MCE2_BASE_S)
+#define MCE2_REGION1_S            ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S)
+#define MCE2_REGION2_S            ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S)
+#define MCE2_REGION3_S            ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S)
+#define MCE2_REGION4_S            ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S)
+#define MCE2_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S)
+#define MCE2_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S)
+#define MCE3_S                    ((MCE_TypeDef *) MCE3_BASE_S)
+#define MCE3_REGION1_S            ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S)
+#define MCE3_REGION2_S            ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S)
+#define MCE3_REGION3_S            ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S)
+#define MCE3_REGION4_S            ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S)
+#define MCE3_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S)
+#define MCE3_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S)
+#define MCE4_S                    ((MCE_TypeDef *) MCE4_BASE_S)
+#define MCE4_REGION1_S            ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S)
+#define MCE4_REGION2_S            ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S)
+#define MCE4_REGION3_S            ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S)
+#define MCE4_REGION4_S            ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S)
+#define MCE4_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S)
+#define MCE4_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S)
+#define MDF1_S                    ((MDF_TypeDef *) MDF1_BASE_S)
+#define MDF1_Filter0_S            ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S)
+#define MDF1_Filter1_S            ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S)
+#define MDF1_Filter2_S            ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S)
+#define MDF1_Filter3_S            ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S)
+#define MDF1_Filter4_S            ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S)
+#define MDF1_Filter5_S            ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S)
+#define MDIOS_S                   ((MDIOS_TypeDef *) MDIOS_BASE_S)
+#define PKA_S                     ((PKA_TypeDef *) PKA_BASE_S)
+#define PSSI_S                    ((PSSI_TypeDef *) PSSI_BASE_S)
+#define PWR_S                     ((PWR_TypeDef *) PWR_BASE_S)
+#define RAMCFG_S                  ((RAMCFG_TypeDef *) RAMCFG_BASE_S)
+#define RAMCFG_SRAM1_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S)
+#define RAMCFG_SRAM2_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S)
+#define RAMCFG_SRAM3_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S)
+#define RAMCFG_SRAM4_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S)
+#define RAMCFG_SRAM5_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S)
+#define RAMCFG_SRAM6_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S)
+#define RAMCFG_SRAM1_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S)
+#define RAMCFG_SRAM2_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S)
+#define RAMCFG_VENC_RAM_S         ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_S          ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S)
+#define RAMCFG_FLEXRAM_S          ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S)
+#define RCC_S                     ((RCC_TypeDef *) RCC_BASE_S)
+#define RIFSC_S                   ((RIFSC_TypeDef *) RIFSC_BASE_S)
+#define RISAF1_S                  ((RISAF_TypeDef *) RISAF1_BASE_S)
+#define RISAF2_S                  ((RISAF_TypeDef *) RISAF2_BASE_S)
+#define RISAF3_S                  ((RISAF_TypeDef *) RISAF3_BASE_S)
+#define RISAF6_S                  ((RISAF_TypeDef *) RISAF6_BASE_S)
+#define RISAF7_S                  ((RISAF_TypeDef *) RISAF7_BASE_S)
+#define RISAF8_S                  ((RISAF_TypeDef *) RISAF8_BASE_S)
+#define RISAF9_S                  ((RISAF_TypeDef *) RISAF9_BASE_S)
+#define RISAF11_S                 ((RISAF_TypeDef *) RISAF11_BASE_S)
+#define RISAF12_S                 ((RISAF_TypeDef *) RISAF12_BASE_S)
+#define RISAF13_S                 ((RISAF_TypeDef *) RISAF13_BASE_S)
+#define RISAF14_S                 ((RISAF_TypeDef *) RISAF14_BASE_S)
+#define RISAF21_S                 ((RISAF_TypeDef *) RISAF21_BASE_S)
+#define RISAF22_S                 ((RISAF_TypeDef *) RISAF22_BASE_S)
+#define RISAF23_S                 ((RISAF_TypeDef *) RISAF23_BASE_S)
+#define RNG_S                     ((RNG_TypeDef *) RNG_BASE_S)
+#define RTC_S                     ((RTC_TypeDef *) RTC_BASE_S)
+#define SAES_S                    ((SAES_TypeDef *) SAES_BASE_S)
+#define SAI1_S                    ((SAI_TypeDef *) SAI1_BASE_S)
+#define SAI1_Block_A_S            ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S)
+#define SAI1_Block_B_S            ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S)
+#define SAI2_S                    ((SAI_TypeDef *) SAI2_BASE_S)
+#define SAI2_Block_A_S            ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S)
+#define SAI2_Block_B_S            ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S)
+#define SDMMC1_S                  ((SDMMC_TypeDef *) SDMMC1_BASE_S)
+#define SDMMC2_S                  ((SDMMC_TypeDef *) SDMMC2_BASE_S)
+#define SPDIFRX_S                 ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S)
+#define SPI1_S                    ((SPI_TypeDef *) SPI1_BASE_S)
+#define SPI2_S                    ((SPI_TypeDef *) SPI2_BASE_S)
+#define SPI3_S                    ((SPI_TypeDef *) SPI3_BASE_S)
+#define SPI4_S                    ((SPI_TypeDef *) SPI4_BASE_S)
+#define SPI5_S                    ((SPI_TypeDef *) SPI5_BASE_S)
+#define SPI6_S                    ((SPI_TypeDef *) SPI6_BASE_S)
+#define SYSCFG_S                  ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
+#define TAMP_S                    ((TAMP_TypeDef *) TAMP_BASE_S)
+#define TIM1_S                    ((TIM_TypeDef *) TIM1_BASE_S)
+#define TIM2_S                    ((TIM_TypeDef *) TIM2_BASE_S)
+#define TIM3_S                    ((TIM_TypeDef *) TIM3_BASE_S)
+#define TIM4_S                    ((TIM_TypeDef *) TIM4_BASE_S)
+#define TIM5_S                    ((TIM_TypeDef *) TIM5_BASE_S)
+#define TIM6_S                    ((TIM_TypeDef *) TIM6_BASE_S)
+#define TIM7_S                    ((TIM_TypeDef *) TIM7_BASE_S)
+#define TIM8_S                    ((TIM_TypeDef *) TIM8_BASE_S)
+#define TIM9_S                    ((TIM_TypeDef *) TIM9_BASE_S)
+#define TIM10_S                   ((TIM_TypeDef *) TIM10_BASE_S)
+#define TIM11_S                   ((TIM_TypeDef *) TIM11_BASE_S)
+#define TIM12_S                   ((TIM_TypeDef *) TIM12_BASE_S)
+#define TIM13_S                   ((TIM_TypeDef *) TIM13_BASE_S)
+#define TIM14_S                   ((TIM_TypeDef *) TIM14_BASE_S)
+#define TIM15_S                   ((TIM_TypeDef *) TIM15_BASE_S)
+#define TIM16_S                   ((TIM_TypeDef *) TIM16_BASE_S)
+#define TIM17_S                   ((TIM_TypeDef *) TIM17_BASE_S)
+#define TIM18_S                   ((TIM_TypeDef *) TIM18_BASE_S)
+#define UART4_S                   ((USART_TypeDef *) UART4_BASE_S)
+#define UART5_S                   ((USART_TypeDef *) UART5_BASE_S)
+#define UART7_S                   ((USART_TypeDef *) UART7_BASE_S)
+#define UART8_S                   ((USART_TypeDef *) UART8_BASE_S)
+#define UART9_S                   ((USART_TypeDef *) UART9_BASE_S)
+#define UCPD1_S                   ((UCPD_TypeDef *) UCPD1_BASE_S)
+#define USART1_S                  ((USART_TypeDef *) USART1_BASE_S)
+#define USART2_S                  ((USART_TypeDef *) USART2_BASE_S)
+#define USART3_S                  ((USART_TypeDef *) USART3_BASE_S)
+#define USART6_S                  ((USART_TypeDef *) USART6_BASE_S)
+#define USART10_S                 ((USART_TypeDef *) USART10_BASE_S)
+#define USB1_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S)
+#define USB2_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S)
+#define USB1_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S)
+#define USB2_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S)
+#define VENC_S                    ((VENC_TypeDef *) VENC_BASE_S)
+#define VREFBUF_S                 ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
+#define WWDG_S                    ((WWDG_TypeDef *) WWDG_BASE_S)
+#define XSPI1_S                   ((XSPI_TypeDef *) XSPI1_BASE_S)
+#define XSPI2_S                   ((XSPI_TypeDef *) XSPI2_BASE_S)
+#define XSPI3_S                   ((XSPI_TypeDef *) XSPI3_BASE_S)
+#define XSPIM_S                   ((XSPIM_TypeDef *) XSPIM_BASE_S)
+#endif
+
+/*!< Peripheral Instance aliases for Non-Secure/Secure execution  */
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON              ADC12_COMMON_S
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_S
+
+#define ADC1                      ADC1_S
+#define ADC1_BASE                 ADC1_BASE_S
+
+#define ADC2                      ADC2_S
+#define ADC2_BASE                 ADC2_BASE_S
+
+#define ADF1                      ADF1_S
+#define ADF1_BASE                 ADF1_BASE_S
+
+#define ADF1_Filter0              ADF1_Filter0_S
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_S
+
+#define BSEC                      BSEC_S
+#define BSEC_BASE                 BSEC_BASE_S
+
+#define CRC                       CRC_S
+#define CRC_BASE                  CRC_BASE_S
+
+#define CRYP                      CRYP_S
+#define CRYP_BASE                 CRYP_BASE_S
+
+#define CSI                       CSI_S
+#define CSI_BASE                  CSI_BASE_S
+
+#define DBGMCU                    DBGMCU_S
+#define DBGMCU_BASE               DBGMCU_BASE_S
+
+#define DCMI                      DCMI_S
+#define DCMI_BASE                 DCMI_BASE_S
+
+#define DCMIPP                    DCMIPP_S
+#define DCMIPP_BASE               DCMIPP_BASE_S
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_S
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_S
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_S
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_S
+
+#define DMA2D                     DMA2D_S
+#define DMA2D_BASE                DMA2D_BASE_S
+
+#define DTS                       DTS_S
+#define DTS_BASE                  DTS_BASE_S
+
+#define DTS_Sensor0               DTS_Sensor0_S
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_S
+
+#define DTS_Sensor1               DTS_Sensor1_S
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_S
+
+#define ETH1                      ETH1_S
+#define ETH1_BASE                 ETH1_BASE_S
+
+#define EXTI                      EXTI_S
+#define EXTI_BASE                 EXTI_BASE_S
+
+#define FDCAN1                    FDCAN1_S
+#define FDCAN1_BASE               FDCAN1_BASE_S
+
+#define FDCAN2                    FDCAN2_S
+#define FDCAN2_BASE               FDCAN2_BASE_S
+
+#define FDCAN3                    FDCAN3_S
+#define FDCAN3_BASE               FDCAN3_BASE_S
+
+#define FDCAN_CCU                 FDCAN_CCU_S
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_S
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_S
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_S
+
+#define FMC_R_BASE                FMC_R_BASE_S
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_S
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_S
+
+#define FMC_Bank1_R               FMC_Bank1_R_S
+#define FMC_Bank1_R_BASE          FMC_Bank1_R_BASE_S
+
+#define FMC_Bank3_R               FMC_Bank3_R_S
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_S
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_S
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_S
+
+#define FMC_Common_R              FMC_Common_R_S
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_S
+
+#define GFXMMU                       GFXMMU_S
+#define GFXMMU_BASE                  GFXMMU_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_S
+
+#define GFXTIM                    GFXTIM_S
+#define GFXTIM_BASE               GFXTIM_BASE_S
+
+#define GPDMA1                    GPDMA1_S
+#define GPDMA1_BASE               GPDMA1_BASE_S
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_S
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_S
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_S
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_S
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_S
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_S
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_S
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_S
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_S
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_S
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_S
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_S
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_S
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_S
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_S
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_S
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_S
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_S
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_S
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_S
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_S
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_S
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_S
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_S
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_S
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_S
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_S
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_S
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_S
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_S
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_S
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_S
+
+#define GPIOA                     GPIOA_S
+#define GPIOA_BASE                GPIOA_BASE_S
+
+#define GPIOB                     GPIOB_S
+#define GPIOB_BASE                GPIOB_BASE_S
+
+#define GPIOC                     GPIOC_S
+#define GPIOC_BASE                GPIOC_BASE_S
+
+#define GPIOD                     GPIOD_S
+#define GPIOD_BASE                GPIOD_BASE_S
+
+#define GPIOE                     GPIOE_S
+#define GPIOE_BASE                GPIOE_BASE_S
+
+#define GPIOF                     GPIOF_S
+#define GPIOF_BASE                GPIOF_BASE_S
+
+#define GPIOG                     GPIOG_S
+#define GPIOG_BASE                GPIOG_BASE_S
+
+#define GPIOH                     GPIOH_S
+#define GPIOH_BASE                GPIOH_BASE_S
+
+#define GPION                     GPION_S
+#define GPION_BASE                GPION_BASE_S
+
+#define GPIOO                     GPIOO_S
+#define GPIOO_BASE                GPIOO_BASE_S
+
+#define GPIOP                     GPIOP_S
+#define GPIOP_BASE                GPIOP_BASE_S
+
+#define GPIOQ                     GPIOQ_S
+#define GPIOQ_BASE                GPIOQ_BASE_S
+
+#define GPU2D                     GPU2D_BASE_S
+#define GPU2D_BASE                GPU2D_BASE_S
+
+#define HASH                      HASH_S
+#define HASH_BASE                 HASH_BASE_S
+
+#define HASH_DIGEST               HASH_DIGEST_S
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_S
+
+#define HPDMA1                    HPDMA1_S
+#define HPDMA1_BASE               HPDMA1_BASE_S
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_S
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_S
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_S
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_S
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_S
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_S
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_S
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_S
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_S
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_S
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_S
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_S
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_S
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_S
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_S
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_S
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_S
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_S
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_S
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_S
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_S
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_S
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_S
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_S
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_S
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_S
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_S
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_S
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_S
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_S
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_S
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_S
+
+#define I2C1                      I2C1_S
+#define I2C1_BASE                 I2C1_BASE_S
+
+#define I2C2                      I2C2_S
+#define I2C2_BASE                 I2C2_BASE_S
+
+#define I2C3                      I2C3_S
+#define I2C3_BASE                 I2C3_BASE_S
+
+#define I2C4                      I2C4_S
+#define I2C4_BASE                 I2C4_BASE_S
+
+#define I3C1                      I3C1_S
+#define I3C1_BASE                 I3C1_BASE_S
+
+#define I3C2                      I3C2_S
+#define I3C2_BASE                 I3C2_BASE_S
+
+#define IAC                       IAC_S
+#define IAC_BASE                  IAC_BASE_S
+
+#define ICACHE                    ICACHE_S
+#define ICACHE_BASE               ICACHE_BASE_S
+
+#define IWDG                      IWDG_S
+#define IWDG_BASE                 IWDG_BASE_S
+
+#define JPEG                      JPEG_S
+#define JPEG_BASE                 JPEG_BASE_S
+
+#define LPTIM1                    LPTIM1_S
+#define LPTIM1_BASE               LPTIM1_BASE_S
+
+#define LPTIM2                    LPTIM2_S
+#define LPTIM2_BASE               LPTIM2_BASE_S
+
+#define LPTIM3                    LPTIM3_S
+#define LPTIM3_BASE               LPTIM3_BASE_S
+
+#define LPTIM4                    LPTIM4_S
+#define LPTIM4_BASE               LPTIM4_BASE_S
+
+#define LPTIM5                    LPTIM5_S
+#define LPTIM5_BASE               LPTIM5_BASE_S
+
+#define LPUART1                   LPUART1_S
+#define LPUART1_BASE              LPUART1_BASE_S
+
+#define LTDC                      LTDC_S
+#define LTDC_BASE                 LTDC_BASE_S
+
+#define LTDC_Layer1               LTDC_Layer1_S
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_S
+
+#define LTDC_Layer2               LTDC_Layer2_S
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_S
+
+#define MCE1                      MCE1_S
+#define MCE1_BASE                 MCE1_BASE_S
+
+#define MCE1_REGION1              MCE1_REGION1_S
+#define MCE1_REGION1_BASE         MCE1_REGION1_BASE_S
+
+#define MCE1_REGION2              MCE1_REGION2_S
+#define MCE1_REGION2_BASE         MCE1_REGION2_BASE_S
+
+#define MCE1_REGION3              MCE1_REGION3_S
+#define MCE1_REGION3_BASE         MCE1_REGION3_BASE_S
+
+#define MCE1_REGION4              MCE1_REGION4_S
+#define MCE1_REGION4_BASE         MCE1_REGION4_BASE_S
+
+#define MCE1_CONTEXT1             MCE1_CONTEXT1_S
+#define MCE1_CONTEXT1_BASE        MCE1_CONTEXT1_BASE_S
+
+#define MCE1_CONTEXT2             MCE1_CONTEXT2_S
+#define MCE1_CONTEXT2_BASE        MCE1_CONTEXT2_BASE_S
+
+#define MCE2                      MCE2_S
+#define MCE2_BASE                 MCE2_BASE_S
+
+#define MCE2_REGION1              MCE2_REGION1_S
+#define MCE2_REGION1_BASE         MCE2_REGION1_BASE_S
+
+#define MCE2_REGION2              MCE2_REGION2_S
+#define MCE2_REGION2_BASE         MCE2_REGION2_BASE_S
+
+#define MCE2_REGION3              MCE2_REGION3_S
+#define MCE2_REGION3_BASE         MCE2_REGION3_BASE_S
+
+#define MCE2_REGION4              MCE2_REGION4_S
+#define MCE2_REGION4_BASE         MCE2_REGION4_BASE_S
+
+#define MCE2_CONTEXT1             MCE2_CONTEXT1_S
+#define MCE2_CONTEXT1_BASE        MCE2_CONTEXT1_BASE_S
+
+#define MCE2_CONTEXT2             MCE2_CONTEXT2_S
+#define MCE2_CONTEXT2_BASE        MCE2_CONTEXT2_BASE_S
+
+#define MCE3                      MCE3_S
+#define MCE3_BASE                 MCE3_BASE_S
+
+#define MCE3_REGION1              MCE3_REGION1_S
+#define MCE3_REGION1_BASE         MCE3_REGION1_BASE_S
+
+#define MCE3_REGION2              MCE3_REGION2_S
+#define MCE3_REGION2_BASE         MCE3_REGION2_BASE_S
+
+#define MCE3_REGION3              MCE3_REGION3_S
+#define MCE3_REGION3_BASE         MCE3_REGION3_BASE_S
+
+#define MCE3_REGION4              MCE3_REGION4_S
+#define MCE3_REGION4_BASE         MCE3_REGION4_BASE_S
+
+#define MCE3_CONTEXT1             MCE3_CONTEXT1_S
+#define MCE3_CONTEXT1_BASE        MCE3_CONTEXT1_BASE_S
+
+#define MCE3_CONTEXT2             MCE3_CONTEXT2_S
+#define MCE3_CONTEXT2_BASE        MCE3_CONTEXT2_BASE_S
+
+#define MCE4                      MCE4_S
+#define MCE4_BASE                 MCE4_BASE_S
+
+#define MCE4_REGION1              MCE4_REGION1_S
+#define MCE4_REGION1_BASE         MCE4_REGION1_BASE_S
+
+#define MCE4_REGION2              MCE4_REGION2_S
+#define MCE4_REGION2_BASE         MCE4_REGION2_BASE_S
+
+#define MCE4_REGION3              MCE4_REGION3_S
+#define MCE4_REGION3_BASE         MCE4_REGION3_BASE_S
+
+#define MCE4_REGION4              MCE4_REGION4_S
+#define MCE4_REGION4_BASE         MCE4_REGION4_BASE_S
+
+#define MCE4_CONTEXT1             MCE4_CONTEXT1_S
+#define MCE4_CONTEXT1_BASE        MCE4_CONTEXT1_BASE_S
+
+#define MCE4_CONTEXT2             MCE4_CONTEXT2_S
+#define MCE4_CONTEXT2_BASE        MCE4_CONTEXT2_BASE_S
+
+#define MDF1                      MDF1_S
+#define MDF1_BASE                 MDF1_BASE_S
+
+#define MDF1_Filter0              MDF1_Filter0_S
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_S
+
+#define MDF1_Filter1              MDF1_Filter1_S
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_S
+
+#define MDF1_Filter2              MDF1_Filter2_S
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_S
+
+#define MDF1_Filter3              MDF1_Filter3_S
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_S
+
+#define MDF1_Filter4              MDF1_Filter4_S
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_S
+
+#define MDF1_Filter5              MDF1_Filter5_S
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_S
+
+#define MDIOS                     MDIOS_S
+#define MDIOS_BASE                MDIOS_BASE_S
+
+#define PKA                       PKA_S
+#define PKA_BASE                  PKA_BASE_S
+
+#define PSSI                      PSSI_S
+#define PSSI_BASE                 PSSI_BASE_S
+
+#define PWR                       PWR_S
+#define PWR_BASE                  PWR_BASE_S
+
+#define RAMCFG                    RAMCFG_S
+#define RAMCFG_BASE               RAMCFG_BASE_S
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_S
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_S
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_S
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_S
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_S
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_S
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_S
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_S
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_S
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_S
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_S
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_S
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_S
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_S
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_S
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_S
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_S
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_S
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_S
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_S
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_S
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_S
+
+#define RCC                       RCC_S
+#define RCC_BASE                  RCC_BASE_S
+
+#define RIFSC                     RIFSC_S
+#define RIFSC_BASE                RIFSC_BASE_S
+
+#define RISAF1                    RISAF1_S
+#define RISAF1_BASE               RISAF1_BASE_S
+
+#define RISAF2                    RISAF2_S
+#define RISAF2_BASE               RISAF2_BASE_S
+
+#define RISAF3                    RISAF3_S
+#define RISAF3_BASE               RISAF3_BASE_S
+
+#define RISAF6                    RISAF6_S
+#define RISAF6_BASE               RISAF6_BASE_S
+
+#define RISAF7                    RISAF7_S
+#define RISAF7_BASE               RISAF7_BASE_S
+
+#define RISAF8                    RISAF8_S
+#define RISAF8_BASE               RISAF8_BASE_S
+
+#define RISAF9                    RISAF9_S
+#define RISAF9_BASE               RISAF9_BASE_S
+
+#define RISAF11                   RISAF11_S
+#define RISAF11_BASE              RISAF11_BASE_S
+
+#define RISAF12                   RISAF12_S
+#define RISAF12_BASE              RISAF12_BASE_S
+
+#define RISAF13                   RISAF13_S
+#define RISAF13_BASE              RISAF13_BASE_S
+
+#define RISAF14                   RISAF14_S
+#define RISAF14_BASE              RISAF14_BASE_S
+
+#define RISAF21                   RISAF21_S
+#define RISAF21_BASE              RISAF21_BASE_S
+
+#define RISAF22                   RISAF22_S
+#define RISAF22_BASE              RISAF22_BASE_S
+
+#define RISAF23                   RISAF23_S
+#define RISAF23_BASE              RISAF23_BASE_S
+
+#define RNG                       RNG_S
+#define RNG_BASE                  RNG_BASE_S
+
+#define RTC                       RTC_S
+#define RTC_BASE                  RTC_BASE_S
+
+#define SAES                      SAES_S
+#define SAES_BASE                 SAES_BASE_S
+
+#define SAI1                      SAI1_S
+#define SAI1_BASE                 SAI1_BASE_S
+
+#define SAI1_Block_A              SAI1_Block_A_S
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_S
+
+#define SAI1_Block_B              SAI1_Block_B_S
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_S
+
+#define SAI2                      SAI2_S
+#define SAI2_BASE                 SAI2_BASE_S
+
+#define SAI2_Block_A              SAI2_Block_A_S
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_S
+
+#define SAI2_Block_B              SAI2_Block_B_S
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_S
+
+#define SDMMC1                    SDMMC1_S
+#define SDMMC1_BASE               SDMMC1_BASE_S
+
+#define SDMMC2                    SDMMC2_S
+#define SDMMC2_BASE               SDMMC2_BASE_S
+
+#define SPDIFRX                   SPDIFRX_S
+#define SPDIFRX_BASE              SPDIFRX_BASE_S
+
+#define SPI1                      SPI1_S
+#define SPI1_BASE                 SPI1_BASE_S
+
+#define SPI2                      SPI2_S
+#define SPI2_BASE                 SPI2_BASE_S
+
+#define SPI3                      SPI3_S
+#define SPI3_BASE                 SPI3_BASE_S
+
+#define SPI4                      SPI4_S
+#define SPI4_BASE                 SPI4_BASE_S
+
+#define SPI5                      SPI5_S
+#define SPI5_BASE                 SPI5_BASE_S
+
+#define SPI6                      SPI6_S
+#define SPI6_BASE                 SPI6_BASE_S
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_S
+
+#define SYSCFG                    SYSCFG_S
+#define SYSCFG_BASE               SYSCFG_BASE_S
+
+#define TAMP                      TAMP_S
+#define TAMP_BASE                 TAMP_BASE_S
+
+#define TIM1                      TIM1_S
+#define TIM1_BASE                 TIM1_BASE_S
+
+#define TIM2                      TIM2_S
+#define TIM2_BASE                 TIM2_BASE_S
+
+#define TIM3                      TIM3_S
+#define TIM3_BASE                 TIM3_BASE_S
+
+#define TIM4                      TIM4_S
+#define TIM4_BASE                 TIM4_BASE_S
+
+#define TIM5                      TIM5_S
+#define TIM5_BASE                 TIM5_BASE_S
+
+#define TIM6                      TIM6_S
+#define TIM6_BASE                 TIM6_BASE_S
+
+#define TIM7                      TIM7_S
+#define TIM7_BASE                 TIM7_BASE_S
+
+#define TIM8                      TIM8_S
+#define TIM8_BASE                 TIM8_BASE_S
+
+#define TIM9                      TIM9_S
+#define TIM9_BASE                 TIM9_BASE_S
+
+#define TIM10                     TIM10_S
+#define TIM10_BASE                TIM10_BASE_S
+
+#define TIM11                     TIM11_S
+#define TIM11_BASE                TIM11_BASE_S
+
+#define TIM12                     TIM12_S
+#define TIM12_BASE                TIM12_BASE_S
+
+#define TIM13                     TIM13_S
+#define TIM13_BASE                TIM13_BASE_S
+
+#define TIM14                     TIM14_S
+#define TIM14_BASE                TIM14_BASE_S
+
+#define TIM15                     TIM15_S
+#define TIM15_BASE                TIM15_BASE_S
+
+#define TIM16                     TIM16_S
+#define TIM16_BASE                TIM16_BASE_S
+
+#define TIM17                     TIM17_S
+#define TIM17_BASE                TIM17_BASE_S
+
+#define TIM18                     TIM18_S
+#define TIM18_BASE                TIM18_BASE_S
+
+#define UART4                     UART4_S
+#define UART4_BASE                UART4_BASE_S
+
+#define UART5                     UART5_S
+#define UART5_BASE                UART5_BASE_S
+
+#define UART7                     UART7_S
+#define UART7_BASE                UART7_BASE_S
+
+#define UART8                     UART8_S
+#define UART8_BASE                UART8_BASE_S
+
+#define UART9                     UART9_S
+#define UART9_BASE                UART9_BASE_S
+
+#define UCPD1                     UCPD1_S
+#define UCPD1_BASE                UCPD1_BASE_S
+
+#define USART1                    USART1_S
+#define USART1_BASE               USART1_BASE_S
+
+#define USART2                    USART2_S
+#define USART2_BASE               USART2_BASE_S
+
+#define USART3                    USART3_S
+#define USART3_BASE               USART3_BASE_S
+
+#define USART6                    USART6_S
+#define USART6_BASE               USART6_BASE_S
+
+#define USART10                   USART10_S
+#define USART10_BASE              USART10_BASE_S
+
+#define USB1_OTG_HS               USB1_OTG_HS_S
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_S
+
+#define USB2_OTG_HS               USB2_OTG_HS_S
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_S
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_S
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_S
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_S
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_S
+
+#define VENC                      VENC_S
+#define VENC_BASE                 VENC_BASE_S
+
+#define VREFBUF                   VREFBUF_S
+#define VREFBUF_BASE              VREFBUF_BASE_S
+
+#define WWDG                      WWDG_S
+#define WWDG_BASE                 WWDG_BASE_S
+
+#define XSPI1                     XSPI1_S
+
+#define XSPI2                     XSPI2_S
+
+#define XSPI3                     XSPI3_S
+
+#define XSPIM                     XSPIM_S
+#define XSPIM_BASE                XSPIM_BASE_S
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_S
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_S
+
+#else
+
+#define ADC12_COMMON              ADC12_COMMON_NS
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_NS
+
+#define ADC1                      ADC1_NS
+#define ADC1_BASE                 ADC1_BASE_NS
+
+#define ADC2                      ADC2_NS
+#define ADC2_BASE                 ADC2_BASE_NS
+
+#define ADF1                      ADF1_NS
+#define ADF1_BASE                 ADF1_BASE_NS
+
+#define ADF1_Filter0              ADF1_Filter0_NS
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_NS
+
+#define BSEC                      BSEC_NS
+#define BSEC_BASE                 BSEC_BASE_NS
+
+#define CRC                       CRC_NS
+#define CRC_BASE                  CRC_BASE_NS
+
+#define CRYP                      CRYP_NS
+#define CRYP_BASE                 CRYP_BASE_NS
+
+#define CSI                       CSI_NS
+#define CSI_BASE                  CSI_BASE_NS
+
+#define DBGMCU                    DBGMCU_NS
+#define DBGMCU_BASE               DBGMCU_BASE_NS
+
+#define DCMI                      DCMI_NS
+#define DCMI_BASE                 DCMI_BASE_NS
+
+#define DCMIPP                    DCMIPP_NS
+#define DCMIPP_BASE               DCMIPP_BASE_NS
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_NS
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_NS
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_NS
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_NS
+
+#define DMA2D                     DMA2D_NS
+#define DMA2D_BASE                DMA2D_BASE_NS
+
+#define DTS                       DTS_NS
+#define DTS_BASE                  DTS_BASE_NS
+
+#define DTS_Sensor0               DTS_Sensor0_NS
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_NS
+
+#define DTS_Sensor1               DTS_Sensor1_NS
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_NS
+
+#define ETH1                      ETH1_NS
+#define ETH1_BASE                 ETH1_BASE_NS
+
+#define EXTI                      EXTI_NS
+#define EXTI_BASE                 EXTI_BASE_NS
+
+#define FDCAN1                    FDCAN1_NS
+#define FDCAN1_BASE               FDCAN1_BASE_NS
+
+#define FDCAN2                    FDCAN2_NS
+#define FDCAN2_BASE               FDCAN2_BASE_NS
+
+#define FDCAN3                    FDCAN3_NS
+#define FDCAN3_BASE               FDCAN3_BASE_NS
+
+#define FDCAN_CCU                 FDCAN_CCU_NS
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_NS
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_NS
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_NS
+
+#define FMC_R_BASE                FMC_R_BASE_NS
+#define FMC_R_BASE_BASE           FMC_R_BASE_BASE_NS
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_NS
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_NS
+
+#define FMC_Bank1_R               FMC_Bank1_R_NS
+#define FMC_Bank1_Rv              FMC_Bank1_R_BASE_NS
+
+#define FMC_Bank3_R               FMC_Bank3_R_NS
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_NS
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_NS
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_NS
+
+#define FMC_Common_R              FMC_Common_R_NS
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_NS
+
+#define GFXMMU                       GFXMMU_NS
+#define GFXMMU_BASE                  GFXMMU_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_NS
+
+#define GFXTIM                    GFXTIM_NS
+#define GFXTIM_BASE               GFXTIM_BASE_NS
+
+#define GPDMA1                    GPDMA1_NS
+#define GPDMA1_BASE               GPDMA1_BASE_NS
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_NS
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_NS
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_NS
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_NS
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_NS
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_NS
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_NS
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_NS
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_NS
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_NS
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_NS
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_NS
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_NS
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_NS
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_NS
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_NS
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_NS
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_NS
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_NS
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_NS
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_NS
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_NS
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_NS
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_NS
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_NS
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_NS
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_NS
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_NS
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_NS
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_NS
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_NS
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_NS
+
+#define GPIOA                     GPIOA_NS
+#define GPIOA_BASE                GPIOA_BASE_NS
+
+#define GPIOB                     GPIOB_NS
+#define GPIOB_BASE                GPIOB_BASE_NS
+
+#define GPIOC                     GPIOC_NS
+#define GPIOC_BASE                GPIOC_BASE_NS
+
+#define GPIOD                     GPIOD_NS
+#define GPIOD_BASE                GPIOD_BASE_NS
+
+#define GPIOE                     GPIOE_NS
+#define GPIOE_BASE                GPIOE_BASE_NS
+
+#define GPIOF                     GPIOF_NS
+#define GPIOF_BASE                GPIOF_BASE_NS
+
+#define GPIOG                     GPIOG_NS
+#define GPIOG_BASE                GPIOG_BASE_NS
+
+#define GPIOH                     GPIOH_NS
+#define GPIOH_BASE                GPIOH_BASE_NS
+
+#define GPION                     GPION_NS
+#define GPION_BASE                GPION_BASE_NS
+
+#define GPIOO                     GPIOO_NS
+#define GPIOO_BASE                GPIOO_BASE_NS
+
+#define GPIOP                     GPIOP_NS
+#define GPIOP_BASE                GPIOP_BASE_NS
+
+#define GPIOQ                     GPIOQ_NS
+#define GPIOQ_BASE                GPIOQ_BASE_NS
+
+#define GPU2D                     GPU2D_BASE_NS
+#define GPU2D_BASE                GPU2D_BASE_NS
+
+#define HASH                      HASH_NS
+#define HASH_BASE                 HASH_BASE_NS
+
+#define HASH_DIGEST               HASH_DIGEST_NS
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_NS
+
+#define HPDMA1                    HPDMA1_NS
+#define HPDMA1_BASE               HPDMA1_BASE_NS
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_NS
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_NS
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_NS
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_NS
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_NS
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_NS
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_NS
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_NS
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_NS
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_NS
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_NS
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_NS
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_NS
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_NS
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_NS
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_NS
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_NS
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_NS
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_NS
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_NS
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_NS
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_NS
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_NS
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_NS
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_NS
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_NS
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_NS
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_NS
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_NS
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_NS
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_NS
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_NS
+
+#define I2C1                      I2C1_NS
+#define I2C1_BASE                 I2C1_BASE_NS
+
+#define I2C2                      I2C2_NS
+#define I2C2_BASE                 I2C2_BASE_NS
+
+#define I2C3                      I2C3_NS
+#define I2C3_BASE                 I2C3_BASE_NS
+
+#define I2C4                      I2C4_NS
+#define I2C4_BASE                 I2C4_BASE_NS
+
+#define I3C1                      I3C1_NS
+#define I3C1_BASE                 I3C1_BASE_NS
+
+#define I3C2                      I3C2_NS
+#define I3C2_BASE                 I3C2_BASE_NS
+
+#define ICACHE                    ICACHE_NS
+#define ICACHE_BASE               ICACHE_BASE_NS
+
+#define IWDG                      IWDG_NS
+#define IWDG_BASE                 IWDG_BASE_NS
+
+#define JPEG                      JPEG_NS
+#define JPEG_BASE                 JPEG_BASE_NS
+
+#define LPTIM1                    LPTIM1_NS
+#define LPTIM1_BASE               LPTIM1_BASE_NS
+
+#define LPTIM2                    LPTIM2_NS
+#define LPTIM2_BASE               LPTIM2_BASE_NS
+
+#define LPTIM3                    LPTIM3_NS
+#define LPTIM3_BASE               LPTIM3_BASE_NS
+
+#define LPTIM4                    LPTIM4_NS
+#define LPTIM4_BASE               LPTIM4_BASE_NS
+
+#define LPTIM5                    LPTIM5_NS
+#define LPTIM5_BASE               LPTIM5_BASE_NS
+
+#define LPUART1                   LPUART1_NS
+#define LPUART1_BASE              LPUART1_BASE_NS
+
+#define LTDC                      LTDC_NS
+#define LTDC_BASE                 LTDC_BASE_NS
+
+#define LTDC_Layer1               LTDC_Layer1_NS
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_NS
+
+#define LTDC_Layer2               LTDC_Layer2_NS
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_NS
+
+#define MCE1                      MCE1_NS
+#define MCE1_BASE                 MCE1_BASE_NS
+
+#define MCE1_REGION1              MCE1_REGION1_NS
+#define MCE1_REGION1_BASE         MCE1_REGION1_BASE_NS
+
+#define MCE1_REGION2              MCE1_REGION2_NS
+#define MCE1_REGION2_BASE         MCE1_REGION2_BASE_NS
+
+#define MCE1_REGION3              MCE1_REGION3_NS
+#define MCE1_REGION3_BASE         MCE1_REGION3_BASE_NS
+
+#define MCE1_REGION4              MCE1_REGION4_NS
+#define MCE1_REGION4_BASE         MCE1_REGION4_BASE_NS
+
+#define MCE1_CONTEXT1             MCE1_CONTEXT1_NS
+#define MCE1_CONTEXT1_BASE        MCE1_CONTEXT1_BASE_NS
+
+#define MCE1_CONTEXT2             MCE1_CONTEXT2_NS
+#define MCE1_CONTEXT2_BASE        MCE1_CONTEXT2_BASE_NS
+
+#define MCE2                      MCE2_NS
+#define MCE2_BASE                 MCE2_BASE_NS
+
+#define MCE2_REGION1              MCE2_REGION1_NS
+#define MCE2_REGION1_BASE         MCE2_REGION1_BASE_NS
+
+#define MCE2_REGION2              MCE2_REGION2_NS
+#define MCE2_REGION2_BASE         MCE2_REGION2_BASE_NS
+
+#define MCE2_REGION3              MCE2_REGION3_NS
+#define MCE2_REGION3_BASE         MCE2_REGION3_BASE_NS
+
+#define MCE2_REGION4              MCE2_REGION4_NS
+#define MCE2_REGION4_BASE         MCE2_REGION4_BASE_NS
+
+#define MCE2_CONTEXT1             MCE2_CONTEXT1_NS
+#define MCE2_CONTEXT1_BASE        MCE2_CONTEXT1_BASE_NS
+
+#define MCE2_CONTEXT2             MCE2_CONTEXT2_NS
+#define MCE2_CONTEXT2_BASE        MCE2_CONTEXT2_BASE_NS
+
+#define MCE3                      MCE3_NS
+#define MCE3_BASE                 MCE3_BASE_NS
+
+#define MCE3_REGION1              MCE3_REGION1_NS
+#define MCE3_REGION1_BASE         MCE3_REGION1_BASE_NS
+
+#define MCE3_REGION2              MCE3_REGION2_NS
+#define MCE3_REGION2_BASE         MCE3_REGION2_BASE_NS
+
+#define MCE3_REGION3              MCE3_REGION3_NS
+#define MCE3_REGION3_BASE         MCE3_REGION3_BASE_NS
+
+#define MCE3_REGION4              MCE3_REGION4_NS
+#define MCE3_REGION4_BASE         MCE3_REGION4_BASE_NS
+
+#define MCE3_CONTEXT1             MCE3_CONTEXT1_NS
+#define MCE3_CONTEXT1_BASE        MCE3_CONTEXT1_BASE_NS
+
+#define MCE3_CONTEXT2             MCE3_CONTEXT2_NS
+#define MCE3_CONTEXT2_BASE        MCE3_CONTEXT2_BASE_NS
+
+#define MCE4                      MCE4_NS
+#define MCE4_BASE                 MCE4_BASE_NS
+
+#define MCE4_REGION1              MCE4_REGION1_NS
+#define MCE4_REGION1_BASE         MCE4_REGION1_BASE_NS
+
+#define MCE4_REGION2              MCE4_REGION2_NS
+#define MCE4_REGION2_BASE         MCE4_REGION2_BASE_NS
+
+#define MCE4_REGION3              MCE4_REGION3_NS
+#define MCE4_REGION3_BASE         MCE4_REGION3_BASE_NS
+
+#define MCE4_REGION4              MCE4_REGION4_NS
+#define MCE4_REGION4_BASE         MCE4_REGION4_BASE_NS
+
+#define MCE4_CONTEXT1             MCE4_CONTEXT1_NS
+#define MCE4_CONTEXT1_BASE        MCE4_CONTEXT1_BASE_NS
+
+#define MCE4_CONTEXT2             MCE4_CONTEXT2_NS
+#define MCE4_CONTEXT2_BASE        MCE4_CONTEXT2_BASE_NS
+
+#define MDF1                      MDF1_NS
+#define MDF1_BASE                 MDF1_BASE_NS
+
+#define MDF1_Filter0              MDF1_Filter0_NS
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_NS
+
+#define MDF1_Filter1              MDF1_Filter1_NS
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_NS
+
+#define MDF1_Filter2              MDF1_Filter2_NS
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_NS
+
+#define MDF1_Filter3              MDF1_Filter3_NS
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_NS
+
+#define MDF1_Filter4              MDF1_Filter4_NS
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_NS
+
+#define MDF1_Filter5              MDF1_Filter5_NS
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_NS
+
+#define MDIOS                     MDIOS_NS
+#define MDIOS_BASE                MDIOS_BASE_NS
+
+#define PKA                       PKA_NS
+#define PKA_BASE                  PKA_BASE_NS
+
+#define PSSI                      PSSI_NS
+#define PSSI_BASE                 PSSI_BASE_NS
+
+#define PWR                       PWR_NS
+#define PWR_BASE                  PWR_BASE_NS
+
+#define RAMCFG                    RAMCFG_NS
+#define RAMCFG_BASE               RAMCFG_BASE_NS
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_NS
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_NS
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_NS
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_NS
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_NS
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_NS
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_NS
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_NS
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_NS
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_NS
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_NS
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_NS
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_NS
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_NS
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_NS
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_NS
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_NS
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_NS
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_NS
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_NS
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_NS
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_NS
+
+#define RCC                       RCC_NS
+#define RCC_BASE                  RCC_BASE_NS
+
+#define RIFSC                     RIFSC_NS
+#define RIFSC_BASE                RIFSC_BASE_NS
+
+#define RISAF1                    RISAF1_NS
+#define RISAF1_BASE               RISAF1_BASE_NS
+
+#define RISAF2                    RISAF2_NS
+#define RISAF2_BASE               RISAF2_BASE_NS
+
+#define RISAF3                    RISAF3_NS
+#define RISAF3_BASE               RISAF3_BASE_NS
+
+#define RISAF6                    RISAF6_NS
+#define RISAF6_BASE               RISAF6_BASE_NS
+
+#define RISAF7                    RISAF7_NS
+#define RISAF7_BASE               RISAF7_BASE_NS
+
+#define RISAF8                    RISAF8_NS
+#define RISAF8_BASE               RISAF8_BASE_NS
+
+#define RISAF9                    RISAF9_NS
+#define RISAF9_BASE               RISAF9_BASE_NS
+
+#define RISAF11                   RISAF11_NS
+#define RISAF11_BASE              RISAF11_BASE_NS
+
+#define RISAF12                   RISAF12_NS
+#define RISAF12_BASE              RISAF12_BASE_NS
+
+#define RISAF13                   RISAF13_NS
+#define RISAF13_BASE              RISAF13_BASE_NS
+
+#define RISAF14                   RISAF14_NS
+#define RISAF14_BASE              RISAF14_BASE_NS
+
+#define RISAF21                   RISAF21_NS
+#define RISAF21_BASE              RISAF21_BASE_NS
+
+#define RISAF22                   RISAF22_NS
+#define RISAF22_BASE              RISAF22_BASE_NS
+
+#define RISAF23                   RISAF23_NS
+#define RISAF23_BASE              RISAF23_BASE_NS
+
+#define RNG                       RNG_NS
+#define RNG_BASE                  RNG_BASE_NS
+
+#define RTC                       RTC_NS
+#define RTC_BASE                  RTC_BASE_NS
+
+#define SAES                      SAES_NS
+#define SAES_BASE                 SAES_BASE_NS
+
+#define SAI1                      SAI1_NS
+#define SAI1_BASE                 SAI1_BASE_NS
+
+#define SAI1_Block_A              SAI1_Block_A_NS
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_NS
+
+#define SAI1_Block_B              SAI1_Block_B_NS
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_NS
+
+#define SAI2                      SAI2_NS
+#define SAI2_BASE                 SAI2_BASE_NS
+
+#define SAI2_Block_A              SAI2_Block_A_NS
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_NS
+
+#define SAI2_Block_B              SAI2_Block_B_NS
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_NS
+
+#define SDMMC1                    SDMMC1_NS
+#define SDMMC1_BASE               SDMMC1_BASE_NS
+
+#define SDMMC2                    SDMMC2_NS
+#define SDMMC2_BASE               SDMMC2_BASE_NS
+
+#define SPDIFRX                   SPDIFRX_NS
+#define SPDIFRX_BASE              SPDIFRX_BASE_NS
+
+#define SPI1                      SPI1_NS
+#define SPI1_BASE                 SPI1_BASE_NS
+
+#define SPI2                      SPI2_NS
+#define SPI2_BASE                 SPI2_BASE_NS
+
+#define SPI3                      SPI3_NS
+#define SPI3_BASE                 SPI3_BASE_NS
+
+#define SPI4                      SPI4_NS
+#define SPI4_BASE                 SPI4_BASE_NS
+
+#define SPI5                      SPI5_NS
+#define SPI5_BASE                 SPI5_BASE_NS
+
+#define SPI6                      SPI6_NS
+#define SPI6_BASE                 SPI6_BASE_NS
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_NS
+
+#define SYSCFG                    SYSCFG_NS
+#define SYSCFG_BASE               SYSCFG_BASE_NS
+
+#define TAMP                      TAMP_NS
+#define TAMP_BASE                 TAMP_BASE_NS
+
+#define TIM1                      TIM1_NS
+#define TIM1_BASE                 TIM1_BASE_NS
+
+#define TIM2                      TIM2_NS
+#define TIM2_BASE                 TIM2_BASE_NS
+
+#define TIM3                      TIM3_NS
+#define TIM3_BASE                 TIM3_BASE_NS
+
+#define TIM4                      TIM4_NS
+#define TIM4_BASE                 TIM4_BASE_NS
+
+#define TIM5                      TIM5_NS
+#define TIM5_BASE                 TIM5_BASE_NS
+
+#define TIM6                      TIM6_NS
+#define TIM6_BASE                 TIM6_BASE_NS
+
+#define TIM7                      TIM7_NS
+#define TIM7_BASE                 TIM7_BASE_NS
+
+#define TIM8                      TIM8_NS
+#define TIM8_BASE                 TIM8_BASE_NS
+
+#define TIM9                      TIM9_NS
+#define TIM9_BASE                 TIM9_BASE_NS
+
+#define TIM10                     TIM10_NS
+#define TIM10_BASE                TIM10_BASE_NS
+
+#define TIM11                     TIM11_NS
+#define TIM11_BASE                TIM11_BASE_NS
+
+#define TIM12                     TIM12_NS
+#define TIM12_BASE                TIM12_BASE_NS
+
+#define TIM13                     TIM13_NS
+#define TIM13_BASE                TIM13_BASE_NS
+
+#define TIM14                     TIM14_NS
+#define TIM14_BASE                TIM14_BASE_NS
+
+#define TIM15                     TIM15_NS
+#define TIM15_BASE                TIM15_BASE_NS
+
+#define TIM16                     TIM16_NS
+#define TIM16_BASE                TIM16_BASE_NS
+
+#define TIM17                     TIM17_NS
+#define TIM17_BASE                TIM17_BASE_NS
+
+#define TIM18                     TIM18_NS
+#define TIM18_BASE                TIM18_BASE_NS
+
+#define UART4                     UART4_NS
+#define UART4_BASE                UART4_BASE_NS
+
+#define UART5                     UART5_NS
+#define UART5_BASE                UART5_BASE_NS
+
+#define UART7                     UART7_NS
+#define UART7_BASE                UART7_BASE_NS
+
+#define UART8                     UART8_NS
+#define UART8_BASE                UART8_BASE_NS
+
+#define UART9                     UART9_NS
+#define UART9_BASE                UART9_BASE_NS
+
+#define UCPD1                     UCPD1_NS
+#define UCPD1_BASE                UCPD1_BASE_NS
+
+#define USART1                    USART1_NS
+#define USART1_BASE               USART1_BASE_NS
+
+#define USART2                    USART2_NS
+#define USART2_BASE               USART2_BASE_NS
+
+#define USART3                    USART3_NS
+#define USART3_BASE               USART3_BASE_NS
+
+#define USART6                    USART6_NS
+#define USART6_BASE               USART6_BASE_NS
+
+#define USART10                   USART10_NS
+#define USART10_BASE              USART10_BASE_NS
+
+#define USB1_OTG_HS               USB1_OTG_HS_NS
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_NS
+
+#define USB2_OTG_HS               USB2_OTG_HS_NS
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_NS
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_NS
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_NS
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_NS
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_NS
+
+#define VENC                      VENC_NS
+#define VENC_BASE                 VENC_BASE_NS
+
+#define VREFBUF                   VREFBUF_NS
+#define VREFBUF_BASE              VREFBUF_BASE_NS
+
+#define WWDG                      WWDG_NS
+#define WWDG_BASE                 WWDG_BASE_NS
+
+#define XSPI1                     XSPI1_NS
+
+#define XSPI2                     XSPI2_NS
+
+#define XSPI3                     XSPI3_NS
+
+#define XSPIM                     XSPIM_NS
+#define XSPIM_BASE                XSPIM_BASE_NS
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_NS
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_NS
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Timing_Definition
+  * @{
+  */
+
+#define LSI_STARTUP_TIME                16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter (ADC)                   */
+/*                                                                            */
+/******************************************************************************/
+
+/* Specific device feature definitions */
+#define ADC_MULTIMODE_SUPPORT         /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)
+#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)
+#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)
+#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)
+#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)
+#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)
+#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)
+#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)
+#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)
+#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)
+#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)
+#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)
+#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)
+#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)
+#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)
+#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)
+#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)
+#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)
+#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)
+#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)
+#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)
+#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)
+#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)
+#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)
+#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)
+#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)
+#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_DEEPPWD_Pos             (29U)
+#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)
+#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)
+#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR1 register  ******************/
+#define ADC_CFGR1_DMNGT_Pos            (0U)
+#define ADC_CFGR1_DMNGT_Msk            (0x3UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000003 */
+#define ADC_CFGR1_DMNGT                ADC_CFGR1_DMNGT_Msk                     /*!< ADC data management configuration */
+#define ADC_CFGR1_DMNGT_0              (0x1UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR1_DMNGT_1              (0x2UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000002 */
+
+#define ADC_CFGR1_RES_Pos              (2U)
+#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x0000000C */
+#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
+#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
+
+#define ADC_CFGR1_EXTSEL_Pos           (5U)
+#define ADC_CFGR1_EXTSEL_Msk           (0x1FUL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x000003E0 */
+#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
+#define ADC_CFGR1_EXTSEL_0             (0x01UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_CFGR1_EXTSEL_1             (0x02UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_2             (0x04UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_3             (0x08UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000100 */
+#define ADC_CFGR1_EXTSEL_4             (0x10UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000200 */
+
+#define ADC_CFGR1_EXTEN_Pos            (10U)
+#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
+
+#define ADC_CFGR1_OVRMOD_Pos           (12U)
+#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
+#define ADC_CFGR1_CONT_Pos             (13U)
+#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
+#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR1_AUTDLY_Pos           (14U)
+#define ADC_CFGR1_AUTDLY_Msk           (0x1UL << ADC_CFGR1_AUTDLY_Pos)         /*!< 0x00004000 */
+#define ADC_CFGR1_AUTDLY               ADC_CFGR1_AUTDLY_Msk                    /*!< ADC low power auto wait */
+
+#define ADC_CFGR1_DISCEN_Pos           (16U)
+#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR1_DISCNUM_Pos          (17U)
+#define ADC_CFGR1_DISCNUM_Msk          (0x7UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x000E0000 */
+#define ADC_CFGR1_DISCNUM              ADC_CFGR1_DISCNUM_Msk                   /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR1_DISCNUM_0            (0x1UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00020000 */
+#define ADC_CFGR1_DISCNUM_1            (0x2UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00040000 */
+#define ADC_CFGR1_DISCNUM_2            (0x4UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00080000 */
+
+#define ADC_CFGR1_JDISCEN_Pos          (20U)
+#define ADC_CFGR1_JDISCEN_Msk          (0x1UL << ADC_CFGR1_JDISCEN_Pos)        /*!< 0x00100000 */
+#define ADC_CFGR1_JDISCEN              ADC_CFGR1_JDISCEN_Msk                   /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CFGR1_AWD1SGL_Pos          (22U)
+#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
+#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR1_AWD1EN_Pos           (23U)
+#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
+#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR1_JAWD1EN_Pos          (24U)
+#define ADC_CFGR1_JAWD1EN_Msk          (0x1UL << ADC_CFGR1_JAWD1EN_Pos)        /*!< 0x01000000 */
+#define ADC_CFGR1_JAWD1EN              ADC_CFGR1_JAWD1EN_Msk                   /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR1_JAUTO_Pos            (25U)
+#define ADC_CFGR1_JAUTO_Msk            (0x1UL << ADC_CFGR1_JAUTO_Pos)          /*!< 0x02000000 */
+#define ADC_CFGR1_JAUTO                ADC_CFGR1_JAUTO_Msk                     /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR1_AWD1CH_Pos           (26U)
+#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
+#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
+#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
+#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
+#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
+#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)
+#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)
+#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)
+#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)
+#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)
+#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+#define ADC_CFGR2_BULB_Pos             (13U)
+#define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)            /*!< 0x00002000 */
+#define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                       /*!< ADC bulb sampling mode */
+
+#define ADC_CFGR2_SWTRIG_Pos           (14U)
+#define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)          /*!< 0x00004000 */
+#define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                     /*!< ADC software trigger bit for sampling time control trigger mode */
+
+#define ADC_CFGR2_SMPTRIG_Pos          (15U)
+#define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)         /*!< 0x00008000 */
+#define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                    /*!< ADC sampling time control trigger mode */
+
+#define ADC_CFGR2_OVSR_Pos             (16U)
+#define ADC_CFGR2_OVSR_Msk             (0x3FFUL << ADC_CFGR2_OVSR_Pos)          /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                       /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x001UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1               (0x002UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2               (0x004UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3               (0x008UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4               (0x010UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5               (0x020UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6               (0x040UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7               (0x080UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8               (0x100UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9               (0x200UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos           (28U)
+#define ADC_CFGR2_LSHIFT_Msk           (0xFUL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT               ADC_CFGR2_LSHIFT_Msk                     /*!< ADC left shift factor */
+#define ADC_CFGR2_LSHIFT_0             (0x1UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1             (0x2UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2             (0x4UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3             (0x8UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)
+#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)
+#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)
+#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)
+#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)
+#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)
+#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)
+#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)
+#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)
+#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)
+#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)
+#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)
+#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)
+#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)
+#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)
+#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)
+#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)
+#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)
+#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)
+#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos            (27U)
+#define ADC_SMPR2_SMP19_Msk            (0x7UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                ADC_SMPR2_SMP19_Msk                     /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0              (0x1UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1              (0x2UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2              (0x4UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  *****************/
+#define ADC_PCSEL_PCSEL_Pos            (0U)
+#define ADC_PCSEL_PCSEL_Msk            (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                ADC_PCSEL_PCSEL_Msk                   /*!< ADC channel preselection */
+#define ADC_PCSEL_PCSEL_0              (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1              (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2              (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3              (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4              (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5              (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6              (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7              (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8              (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9              (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10             (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11             (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12             (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13             (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14             (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15             (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16             (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17             (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18             (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19             (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)
+#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)
+#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)
+#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)
+#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)
+#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)
+#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)
+#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)
+#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)
+#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)
+#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)
+#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)
+#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)
+#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)
+#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)
+#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)
+#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)
+#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)
+#define ADC_DR_RDATA_Msk               (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)      /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x00000001UL << ADC_DR_RDATA_Pos)      /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x00000002UL << ADC_DR_RDATA_Pos)      /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x00000004UL << ADC_DR_RDATA_Pos)      /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x00000008UL << ADC_DR_RDATA_Pos)      /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x00000010UL << ADC_DR_RDATA_Pos)      /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x00000020UL << ADC_DR_RDATA_Pos)      /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x00000040UL << ADC_DR_RDATA_Pos)      /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x00000080UL << ADC_DR_RDATA_Pos)      /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x00000100UL << ADC_DR_RDATA_Pos)      /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x00000200UL << ADC_DR_RDATA_Pos)      /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x00000400UL << ADC_DR_RDATA_Pos)      /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x00000800UL << ADC_DR_RDATA_Pos)      /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x00001000UL << ADC_DR_RDATA_Pos)      /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x00002000UL << ADC_DR_RDATA_Pos)      /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x00004000UL << ADC_DR_RDATA_Pos)      /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x00008000UL << ADC_DR_RDATA_Pos)      /*!< 0x00008000 */
+#define ADC_DR_RDATA_16                (0x00010000UL << ADC_DR_RDATA_Pos)      /*!< 0x00010000 */
+#define ADC_DR_RDATA_17                (0x00020000UL << ADC_DR_RDATA_Pos)      /*!< 0x00020000 */
+#define ADC_DR_RDATA_18                (0x00040000UL << ADC_DR_RDATA_Pos)      /*!< 0x00040000 */
+#define ADC_DR_RDATA_19                (0x00080000UL << ADC_DR_RDATA_Pos)      /*!< 0x00080000 */
+#define ADC_DR_RDATA_20                (0x00100000UL << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
+#define ADC_DR_RDATA_21                (0x00200000UL << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
+#define ADC_DR_RDATA_22                (0x00400000UL << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
+#define ADC_DR_RDATA_23                (0x00800000UL << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
+#define ADC_DR_RDATA_24                (0x01000000UL << ADC_DR_RDATA_Pos)      /*!< 0x01000000 */
+#define ADC_DR_RDATA_25                (0x02000000UL << ADC_DR_RDATA_Pos)      /*!< 0x02000000 */
+#define ADC_DR_RDATA_26                (0x04000000UL << ADC_DR_RDATA_Pos)      /*!< 0x04000000 */
+#define ADC_DR_RDATA_27                (0x08000000UL << ADC_DR_RDATA_Pos)      /*!< 0x08000000 */
+#define ADC_DR_RDATA_28                (0x10000000UL << ADC_DR_RDATA_Pos)      /*!< 0x10000000 */
+#define ADC_DR_RDATA_29                (0x20000000UL << ADC_DR_RDATA_Pos)      /*!< 0x20000000 */
+#define ADC_DR_RDATA_30                (0x40000000UL << ADC_DR_RDATA_Pos)      /*!< 0x40000000 */
+#define ADC_DR_RDATA_31                (0x80000000UL << ADC_DR_RDATA_Pos)      /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)
+#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)
+#define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x01UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x02UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x04UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x08UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos            (7U)
+#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos              (9U)
+#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos              (15U)
+#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos              (21U)
+#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (27U)
+#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR1 register  ***************/
+#define ADC_OFCFGR1_POSOFF_Pos         (24U)
+#define ADC_OFCFGR1_POSOFF_Msk         (0x01UL << ADC_OFCFGR1_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR1_POSOFF             ADC_OFCFGR1_POSOFF_Msk                  /*!< ADC offset instance 1 positive offset enable */
+
+#define ADC_OFCFGR1_USAT_Pos           (25U)
+#define ADC_OFCFGR1_USAT_Msk           (0x01UL << ADC_OFCFGR1_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR1_USAT               ADC_OFCFGR1_USAT_Msk                    /*!< ADC offset instance 1  unsigned saturation value */
+
+#define ADC_OFCFGR1_SSAT_Pos           (26U)
+#define ADC_OFCFGR1_SSAT_Msk           (0x01UL << ADC_OFCFGR1_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR1_SSAT               ADC_OFCFGR1_SSAT_Msk                    /*!< ADC offset instance 1 signed satuaration enable */
+
+#define ADC_OFCFGR1_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR1_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR1_OFFSET_CH          ADC_OFCFGR1_OFFSET_CH_Msk               /*!< ADC offset instance 1 channel selection */
+#define ADC_OFCFGR1_OFFSET_CH_0        (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR1_OFFSET_CH_1        (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR1_OFFSET_CH_2        (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR1_OFFSET_CH_3        (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR1_OFFSET_CH_4        (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR2 register  ***************/
+#define ADC_OFCFGR2_POSOFF_Pos         (24U)
+#define ADC_OFCFGR2_POSOFF_Msk         (0x01UL << ADC_OFCFGR2_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR2_POSOFF             ADC_OFCFGR2_POSOFF_Msk                  /*!< ADC offset instance 2 positive offset enable */
+
+#define ADC_OFCFGR2_USAT_Pos           (25U)
+#define ADC_OFCFGR2_USAT_Msk           (0x01UL << ADC_OFCFGR2_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR2_USAT               ADC_OFCFGR2_USAT_Msk                    /*!< ADC offset instance 2 unsigned saturation value */
+
+#define ADC_OFCFGR2_SSAT_Pos           (26U)
+#define ADC_OFCFGR2_SSAT_Msk           (0x01UL << ADC_OFCFGR2_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR2_SSAT               ADC_OFCFGR2_SSAT_Msk                    /*!< ADC offset instance 2 signed satuaration enable */
+
+#define ADC_OFCFGR2_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR2_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR2_OFFSET_CH          ADC_OFCFGR2_OFFSET_CH_Msk               /*!< ADC offset instance 2 channel selection */
+#define ADC_OFCFGR2_OFFSET_CH_0        (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR2_OFFSET_CH_1        (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR2_OFFSET_CH_2        (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR2_OFFSET_CH_3        (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR2_OFFSET_CH_4        (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR3 register  ***************/
+#define ADC_OFCFGR3_POSOFF_Pos         (24U)
+#define ADC_OFCFGR3_POSOFF_Msk         (0x01UL << ADC_OFCFGR3_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR3_POSOFF             ADC_OFCFGR3_POSOFF_Msk                  /*!< ADC offset instance 3 positive offset enable */
+
+#define ADC_OFCFGR3_USAT_Pos           (25U)
+#define ADC_OFCFGR3_USAT_Msk           (0x01UL << ADC_OFCFGR3_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR3_USAT               ADC_OFCFGR3_USAT_Msk                    /*!< ADC offset instance 3 unsigned saturation value */
+
+#define ADC_OFCFGR3_SSAT_Pos           (26U)
+#define ADC_OFCFGR3_SSAT_Msk           (0x01UL << ADC_OFCFGR3_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR3_SSAT               ADC_OFCFGR3_SSAT_Msk                    /*!< ADC offset instance 3 signed satuaration enable */
+
+#define ADC_OFCFGR3_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR3_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR3_OFFSET_CH          ADC_OFCFGR3_OFFSET_CH_Msk               /*!< ADC offset instance 3 channel selection for the data offset */
+#define ADC_OFCFGR3_OFFSET_CH_0        (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR3_OFFSET_CH_1        (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR3_OFFSET_CH_2        (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR3_OFFSET_CH_3        (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR3_OFFSET_CH_4        (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR4 register  ***************/
+#define ADC_OFCFGR4_POSOFF_Pos         (24U)
+#define ADC_OFCFGR4_POSOFF_Msk         (0x01UL << ADC_OFCFGR4_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR4_POSOFF             ADC_OFCFGR4_POSOFF_Msk                  /*!< ADC offset instance 4 positive offset enable */
+
+#define ADC_OFCFGR4_USAT_Pos           (25U)
+#define ADC_OFCFGR4_USAT_Msk           (0x01UL << ADC_OFCFGR4_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR4_USAT               ADC_OFCFGR4_USAT_Msk                    /*!< ADC offset instance 4 unsigned saturation value */
+
+#define ADC_OFCFGR4_SSAT_Pos           (26U)
+#define ADC_OFCFGR4_SSAT_Msk           (0x01UL << ADC_OFCFGR4_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR4_SSAT               ADC_OFCFGR4_SSAT_Msk                    /*!< ADC offset instance 4 signed satuaration enable */
+
+#define ADC_OFCFGR4_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR4_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR4_OFFSET_CH          ADC_OFCFGR4_OFFSET_CH_Msk               /*!< ADC offset instance 4 channel selection for the data offset */
+#define ADC_OFCFGR4_OFFSET_CH_0        (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR4_OFFSET_CH_1        (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR4_OFFSET_CH_2        (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR4_OFFSET_CH_3        (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR4_OFFSET_CH_4        (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET_Pos            (0U)
+#define ADC_OFR1_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR1_OFFSET                ADC_OFR1_OFFSET_Msk                     /*!< ADC offset instance 1 offset level */
+#define ADC_OFR1_OFFSET_0              (0x0000001UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET_1              (0x0000002UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET_2              (0x0000004UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET_3              (0x0000008UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET_4              (0x0000010UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET_5              (0x0000020UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET_6              (0x0000040UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET_7              (0x0000080UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET_8              (0x0000100UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET_9              (0x0000200UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET_10             (0x0000400UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET_11             (0x0000800UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET_12             (0x0001000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET_13             (0x0002000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET_14             (0x0004000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET_15             (0x0008000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET_16             (0x0010000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET_17             (0x0020000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET_18             (0x0040000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET_19             (0x0080000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET_20             (0x0100000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET_21             (0x0200000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET_Pos            (0U)
+#define ADC_OFR2_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR2_OFFSET                ADC_OFR2_OFFSET_Msk                     /*!< ADC offset instance 2 offset level */
+#define ADC_OFR2_OFFSET_0              (0x0000001UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET_1              (0x0000002UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET_2              (0x0000004UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET_3              (0x0000008UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET_4              (0x0000010UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET_5              (0x0000020UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET_6              (0x0000040UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET_7              (0x0000080UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET_8              (0x0000100UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET_9              (0x0000200UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET_10             (0x0000400UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET_11             (0x0000800UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET_12             (0x0001000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET_13             (0x0002000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET_14             (0x0004000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET_15             (0x0008000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET_16             (0x0010000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET_17             (0x0020000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET_18             (0x0040000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET_19             (0x0080000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET_20             (0x0100000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET_21             (0x0200000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET_Pos            (0U)
+#define ADC_OFR3_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR3_OFFSET                ADC_OFR3_OFFSET_Msk                     /*!< ADC offset instance 3 offset level */
+#define ADC_OFR3_OFFSET_0              (0x0000001UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET_1              (0x0000002UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET_2              (0x0000004UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET_3              (0x0000008UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET_4              (0x0000010UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET_5              (0x0000020UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET_6              (0x0000040UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET_7              (0x0000080UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET_8              (0x0000100UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET_9              (0x0000200UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET_10             (0x0000400UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET_11             (0x0000800UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET_12             (0x0001000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET_13             (0x0002000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET_14             (0x0004000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET_15             (0x0008000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET_16             (0x0010000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET_17             (0x0020000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET_18             (0x0040000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET_19             (0x0080000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET_20             (0x0100000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET_21             (0x0200000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET_Pos            (0U)
+#define ADC_OFR4_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR4_OFFSET                ADC_OFR4_OFFSET_Msk                     /*!< ADC offset instance 4 offset level */
+#define ADC_OFR4_OFFSET_0              (0x0000001UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET_1              (0x0000002UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET_2              (0x0000004UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET_3              (0x0000008UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET_4              (0x0000010UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET_5              (0x0000020UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET_6              (0x0000040UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET_7              (0x0000080UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET_8              (0x0000100UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET_9              (0x0000200UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET_10             (0x0000400UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET_11             (0x0000800UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET_12             (0x0001000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET_13             (0x0002000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET_14             (0x0004000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET_15             (0x0008000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET_16             (0x0010000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET_17             (0x0020000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET_18             (0x0040000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET_19             (0x0080000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET_20             (0x0100000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET_21             (0x0200000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_GCOMP register  *****************/
+#define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
+#define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< Gain compensation coefficient */
+#define ADC_GCOMP_GCOMP_Pos            (31U)
+#define ADC_GCOMP_GCOMP_Msk            (0x1UL << ADC_GCOMP_GCOMP_Pos)          /*!< 0x80000000 */
+#define ADC_GCOMP_GCOMP                ADC_GCOMP_GCOMP_Msk                     /*!< Gain compensation mode */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)
+#define ADC_JDR1_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x00000001UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x00000002UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x00000004UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x00000008UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x00000010UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x00000020UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x00000040UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x00000080UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x00000100UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x00000200UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x00000400UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x00000800UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x00001000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x00002000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x00004000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x00008000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16              (0x00010000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17              (0x00020000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18              (0x00040000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19              (0x00080000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20              (0x00100000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21              (0x00200000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22              (0x00400000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23              (0x00800000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24              (0x01000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25              (0x02000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26              (0x04000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27              (0x08000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28              (0x10000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29              (0x20000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30              (0x40000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31              (0x80000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos             (0U)
+#define ADC_JDR2_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x00000001UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x00000002UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x00000004UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x00000008UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x00000010UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x00000020UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x00000040UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x00000080UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x00000100UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x00000200UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x00000400UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x00000800UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x00001000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x00002000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x00004000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x00008000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16              (0x00010000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17              (0x00020000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18              (0x00040000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19              (0x00080000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20              (0x00100000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21              (0x00200000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22              (0x00400000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23              (0x00800000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24              (0x01000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25              (0x02000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26              (0x04000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27              (0x08000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28              (0x10000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29              (0x20000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30              (0x40000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31              (0x80000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos             (0U)
+#define ADC_JDR3_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x00000001UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x00000002UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x00000004UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x00000008UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x00000010UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x00000020UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x00000040UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x00000080UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x00000100UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x00000200UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x00000400UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x00000800UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x00001000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x00002000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x00004000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x00008000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16              (0x00010000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17              (0x00020000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18              (0x00040000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19              (0x00080000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20              (0x00100000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21              (0x00200000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22              (0x00400000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23              (0x00800000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24              (0x01000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25              (0x02000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26              (0x04000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27              (0x08000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28              (0x10000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29              (0x20000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30              (0x40000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31              (0x80000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos             (0U)
+#define ADC_JDR4_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x00000001UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x00000002UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x00000004UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x00000008UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x00000010UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x00000020UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x00000040UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x00000080UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x00000100UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x00000200UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x00000400UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x00000800UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x00001000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x00002000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x00004000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x00008000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16              (0x00010000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17              (0x00020000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18              (0x00040000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19              (0x00080000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20              (0x00100000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21              (0x00200000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22              (0x00400000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23              (0x00800000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24              (0x01000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25              (0x02000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26              (0x04000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27              (0x08000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28              (0x10000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29              (0x20000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30              (0x40000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31              (0x80000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)
+#define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)
+#define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19           (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD1TR_LT register  *************/
+#define ADC_AWD1LTR_LTR_Pos            (0U)
+#define ADC_AWD1LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1LTR_LTR                ADC_AWD1LTR_LTR_Msk                    /*!< ADC analog watchdog 1 threshold low */
+#define ADC_AWD1LTR_LTR_0              (0x000001UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1LTR_LTR_1              (0x000002UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1LTR_LTR_2              (0x000004UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1LTR_LTR_3              (0x000008UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1LTR_LTR_4              (0x000010UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1LTR_LTR_5              (0x000020UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1LTR_LTR_6              (0x000040UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1LTR_LTR_7              (0x000080UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1LTR_LTR_8              (0x000100UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1LTR_LTR_9              (0x000200UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1LTR_LTR_10             (0x000400UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1LTR_LTR_11             (0x000800UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1LTR_LTR_12             (0x001000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1LTR_LTR_13             (0x002000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1LTR_LTR_14             (0x004000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1LTR_LTR_15             (0x008000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1LTR_LTR_16             (0x010000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1LTR_LTR_17             (0x020000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1LTR_LTR_18             (0x040000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1LTR_LTR_19             (0x080000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1LTR_LTR_20             (0x100000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1LTR_LTR_21             (0x200000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1LTR_LTR_22             (0x400000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD1TR_HT register  *******************/
+#define ADC_AWD1HTR_HTR_Pos            (0U)
+#define ADC_AWD1HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1HTR_HTR                ADC_AWD1HTR_HTR_Msk                    /*!< ADC analog watchdog 1 threshold high */
+#define ADC_AWD1HTR_HTR_0              (0x000001UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1HTR_HTR_1              (0x000002UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1HTR_HTR_2              (0x000004UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1HTR_HTR_3              (0x000008UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1HTR_HTR_4              (0x000010UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1HTR_HTR_5              (0x000020UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1HTR_HTR_6              (0x000040UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1HTR_HTR_7              (0x000080UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1HTR_HTR_8              (0x000100UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1HTR_HTR_9              (0x000200UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1HTR_HTR_10             (0x000400UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1HTR_HTR_11             (0x000800UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1HTR_HTR_12             (0x001000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1HTR_HTR_13             (0x002000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1HTR_HTR_14             (0x004000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1HTR_HTR_15             (0x008000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1HTR_HTR_16             (0x010000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1HTR_HTR_17             (0x020000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1HTR_HTR_18             (0x040000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1HTR_HTR_19             (0x080000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1HTR_HTR_20             (0x100000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1HTR_HTR_21             (0x200000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1HTR_HTR_22             (0x400000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00400000 */
+
+#define ADC_AWD1HTR_AWDFILT_Pos         (29U)
+#define ADC_AWD1HTR_AWDFILT_Msk         (0x7UL << ADC_AWD1HTR_AWDFILT_Pos)      /*!< 0x00000007 */
+#define ADC_AWD1HTR_AWDFILT             ADC_AWD1HTR_AWDFILT_Msk                 /*!< ADC analog watchdog 1 filtering */
+#define ADC_AWD1HTR_AWDFILT_0           (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */
+#define ADC_AWD1HTR_AWDFILT_1           (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */
+#define ADC_AWD1HTR_AWDFILT_2           (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */
+
+/********************  Bit definition for ADC_AWD2TR_LT register  *******************/
+#define ADC_AWD2LTR_LTR_Pos            (0U)
+#define ADC_AWD2LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2LTR_LTR                ADC_AWD2LTR_LTR_Msk                    /*!< ADC analog watchdog 2 threshold low */
+#define ADC_AWD2LTR_LTR_0              (0x000001UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2LTR_LTR_1              (0x000002UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2LTR_LTR_2              (0x000004UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2LTR_LTR_3              (0x000008UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2LTR_LTR_4              (0x000010UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2LTR_LTR_5              (0x000020UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2LTR_LTR_6              (0x000040UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2LTR_LTR_7              (0x000080UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2LTR_LTR_8              (0x000100UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2LTR_LTR_9              (0x000200UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2LTR_LTR_10             (0x000400UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2LTR_LTR_11             (0x000800UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2LTR_LTR_12             (0x001000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2LTR_LTR_13             (0x002000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2LTR_LTR_14             (0x004000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2LTR_LTR_15             (0x008000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2LTR_LTR_16             (0x010000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2LTR_LTR_17             (0x020000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2LTR_LTR_18             (0x040000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2LTR_LTR_19             (0x080000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2LTR_LTR_20             (0x100000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2LTR_LTR_21             (0x200000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2LTR_LTR_22             (0x400000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD2TR_HT register  *******************/
+#define ADC_AWD2HTR_HTR_Pos            (0U)
+#define ADC_AWD2HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2HTR_HTR                ADC_AWD2HTR_HTR_Msk                    /*!< ADC analog watchdog 2 threshold high */
+#define ADC_AWD2HTR_HTR_0              (0x000001UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2HTR_HTR_1              (0x000002UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2HTR_HTR_2              (0x000004UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2HTR_HTR_3              (0x000008UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2HTR_HTR_4              (0x000010UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2HTR_HTR_5              (0x000020UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2HTR_HTR_6              (0x000040UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2HTR_HTR_7              (0x000080UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2HTR_HTR_8              (0x000100UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2HTR_HTR_9              (0x000200UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2HTR_HTR_10             (0x000400UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2HTR_HTR_11             (0x000800UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2HTR_HTR_12             (0x001000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2HTR_HTR_13             (0x002000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2HTR_HTR_14             (0x004000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2HTR_HTR_15             (0x008000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2HTR_HTR_16             (0x010000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2HTR_HTR_17             (0x020000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2HTR_HTR_18             (0x040000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2HTR_HTR_19             (0x080000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2HTR_HTR_20             (0x100000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2HTR_HTR_21             (0x200000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2HTR_HTR_22             (0x400000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_LT register  *******************/
+#define ADC_AWD3LTR_LTR_Pos            (0U)
+#define ADC_AWD3LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3LTR_LTR                ADC_AWD3LTR_LTR_Msk                    /*!< ADC analog watchdog 3 threshold low */
+#define ADC_AWD3LTR_LTR_0              (0x000001UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3LTR_LTR_1              (0x000002UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3LTR_LTR_2              (0x000004UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3LTR_LTR_3              (0x000008UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3LTR_LTR_4              (0x000010UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3LTR_LTR_5              (0x000020UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3LTR_LTR_6              (0x000040UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3LTR_LTR_7              (0x000080UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3LTR_LTR_8              (0x000100UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3LTR_LTR_9              (0x000200UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3LTR_LTR_10             (0x000400UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3LTR_LTR_11             (0x000800UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3LTR_LTR_12             (0x001000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3LTR_LTR_13             (0x002000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3LTR_LTR_14             (0x004000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3LTR_LTR_15             (0x008000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3LTR_LTR_16             (0x010000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3LTR_LTR_17             (0x020000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3LTR_LTR_18             (0x040000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3LTR_LTR_19             (0x080000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3LTR_LTR_20             (0x100000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3LTR_LTR_21             (0x200000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3LTR_LTR_22             (0x400000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_HT register  *******************/
+#define ADC_AWD3HTR_HTR_Pos            (0U)
+#define ADC_AWD3HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3HTR_HTR                ADC_AWD3HTR_HTR_Msk                    /*!< ADC analog watchdog 3 threshold high */
+#define ADC_AWD3HTR_HTR_0              (0x000001UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3HTR_HTR_1              (0x000002UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3HTR_HTR_2              (0x000004UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3HTR_HTR_3              (0x000008UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3HTR_HTR_4              (0x000010UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3HTR_HTR_5              (0x000020UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3HTR_HTR_6              (0x000040UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3HTR_HTR_7              (0x000080UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3HTR_HTR_8              (0x000100UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3HTR_HTR_9              (0x000200UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3HTR_HTR_10             (0x000400UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3HTR_HTR_11             (0x000800UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3HTR_HTR_12             (0x001000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3HTR_HTR_13             (0x002000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3HTR_HTR_14             (0x004000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3HTR_HTR_15             (0x008000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3HTR_HTR_16             (0x010000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3HTR_HTR_17             (0x020000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3HTR_HTR_18             (0x040000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3HTR_HTR_19             (0x080000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3HTR_HTR_20             (0x100000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3HTR_HTR_21             (0x200000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3HTR_HTR_22             (0x400000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)
+#define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode selection */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)
+#define ADC_CALFACT_CALFACT_S_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos)  /*!< 0x000003FF */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7        (0x80UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8        (0x100UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9        (0x200UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000200 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)
+#define ADC_CALFACT_CALFACT_D_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos)  /*!< 0x03FF0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7        (0x80UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8        (0x100UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9        (0x200UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x02000000 */
+
+#define ADC_CALFACT_CALADDOS_Pos       (31U)
+#define ADC_CALFACT_CALADDOS_Msk       (0x01UL << ADC_CALFACT_CALADDOS_Pos)    /*!< 0x80000000 */
+#define ADC_CALFACT_CALADDOS           ADC_CALFACT_CALADDOS_Msk                /*!< ADC calibration additional offset mode */
+
+/********************  Bit definition for ADC_OR option register  ***************/
+#define ADC_OR_OP0_Pos                 (0U)
+#define ADC_OR_OP0_Msk                 (0x1UL << ADC_OR_OP0_Pos)               /*!< 0x00000001 */
+#define ADC_OR_OP0                     ADC_OR_OP0_Msk                          /*!< ADC internal reference voltage buffer */
+
+#define ADC_OR_OP1_Pos                 (1U)
+#define ADC_OR_OP1_Msk                 (0x1UL << ADC_OR_OP1_Pos)               /*!< 0x00000002 */
+#define ADC_OR_OP1                     ADC_OR_OP1_Msk                          /*!< ADC internal bandgap */
+
+#define ADC_OR_OP2_Pos                 (2U)
+#define ADC_OR_OP2_Msk                 (0x1UL << ADC_OR_OP2_Pos)               /*!< 0x00000004 */
+#define ADC_OR_OP2                     ADC_OR_OP2_Msk                          /*!< ADC internal path to VDDCORE */
+
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)
+#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)
+#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)
+#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)
+#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)
+#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)
+#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)
+#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)
+#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)
+#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)
+#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)
+#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)
+#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)
+#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)
+#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)
+#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)
+#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)
+#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)
+#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)
+#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)
+#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
+
+#define ADC_CCR_DAMDF_Pos              (14U)
+#define ADC_CCR_DAMDF_Msk              (0x3UL << ADC_CCR_DAMDF_Pos)            /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                  ADC_CCR_DAMDF_Msk                       /*!< ADC multimode data format */
+#define ADC_CCR_DAMDF_0                (0x1UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                (0x2UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00008000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)
+#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+
+#define ADC_CCR_VBATEN_Pos             (24U)
+#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos         (0U)
+#define ADC_CDR2_RDATA_ALT_Msk         (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT             ADC_CDR2_RDATA_ALT_Msk                   /*!< ADC multimode master or slave (alternated) group regular conversion data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       BSEC unit (Boot and Security)                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for BSEC_FVRw register  *******************/
+#define BSEC_FVRw_FV_Pos               (0U)
+#define BSEC_FVRw_FV_Msk               (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos)           /*!< 0xFFFFFFFF */
+#define BSEC_FVRw_FV                   BSEC_FVRw_FV_Msk                            /*!< Fuse value */
+
+/*****************  Bit definition for BSEC_SPLOCKx register  *****************/
+#define BSEC_SPLOCKx_SPLOCK0_Pos       (0U)
+#define BSEC_SPLOCKx_SPLOCK0_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SPLOCKx_SPLOCK0           BSEC_SPLOCKx_SPLOCK0_Msk                    /*!< Sticky programming lock for word (32*x) */
+#define BSEC_SPLOCKx_SPLOCK1_Pos       (1U)
+#define BSEC_SPLOCKx_SPLOCK1_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SPLOCKx_SPLOCK1           BSEC_SPLOCKx_SPLOCK1_Msk                    /*!< Sticky programming lock for word (1+32*x) */
+#define BSEC_SPLOCKx_SPLOCK2_Pos       (2U)
+#define BSEC_SPLOCKx_SPLOCK2_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SPLOCKx_SPLOCK2           BSEC_SPLOCKx_SPLOCK2_Msk                    /*!< Sticky programming lock for word (2+32*x) */
+#define BSEC_SPLOCKx_SPLOCK3_Pos       (3U)
+#define BSEC_SPLOCKx_SPLOCK3_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SPLOCKx_SPLOCK3           BSEC_SPLOCKx_SPLOCK3_Msk                    /*!< Sticky programming lock for word (3+32*x) */
+#define BSEC_SPLOCKx_SPLOCK4_Pos       (4U)
+#define BSEC_SPLOCKx_SPLOCK4_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SPLOCKx_SPLOCK4           BSEC_SPLOCKx_SPLOCK4_Msk                    /*!< Sticky programming lock for word (4+32*x) */
+#define BSEC_SPLOCKx_SPLOCK5_Pos       (5U)
+#define BSEC_SPLOCKx_SPLOCK5_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SPLOCKx_SPLOCK5           BSEC_SPLOCKx_SPLOCK5_Msk                    /*!< Sticky programming lock for word (5+32*x) */
+#define BSEC_SPLOCKx_SPLOCK6_Pos       (6U)
+#define BSEC_SPLOCKx_SPLOCK6_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SPLOCKx_SPLOCK6           BSEC_SPLOCKx_SPLOCK6_Msk                    /*!< Sticky programming lock for word (6+32*x) */
+#define BSEC_SPLOCKx_SPLOCK7_Pos       (7U)
+#define BSEC_SPLOCKx_SPLOCK7_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SPLOCKx_SPLOCK7           BSEC_SPLOCKx_SPLOCK7_Msk                    /*!< Sticky programming lock for word (7+32*x) */
+#define BSEC_SPLOCKx_SPLOCK8_Pos       (8U)
+#define BSEC_SPLOCKx_SPLOCK8_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SPLOCKx_SPLOCK8           BSEC_SPLOCKx_SPLOCK8_Msk                    /*!< Sticky programming lock for word (8+32*x) */
+#define BSEC_SPLOCKx_SPLOCK9_Pos       (9U)
+#define BSEC_SPLOCKx_SPLOCK9_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SPLOCKx_SPLOCK9           BSEC_SPLOCKx_SPLOCK9_Msk                    /*!< Sticky programming lock for word (9+32*x) */
+#define BSEC_SPLOCKx_SPLOCK10_Pos      (10U)
+#define BSEC_SPLOCKx_SPLOCK10_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SPLOCKx_SPLOCK10          BSEC_SPLOCKx_SPLOCK10_Msk                   /*!< Sticky programming lock for word (10+32*x) */
+#define BSEC_SPLOCKx_SPLOCK11_Pos      (11U)
+#define BSEC_SPLOCKx_SPLOCK11_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SPLOCKx_SPLOCK11          BSEC_SPLOCKx_SPLOCK11_Msk                   /*!< Sticky programming lock for word (11+32*x) */
+#define BSEC_SPLOCKx_SPLOCK12_Pos      (12U)
+#define BSEC_SPLOCKx_SPLOCK12_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SPLOCKx_SPLOCK12          BSEC_SPLOCKx_SPLOCK12_Msk                   /*!< Sticky programming lock for word (12+32*x) */
+#define BSEC_SPLOCKx_SPLOCK13_Pos      (13U)
+#define BSEC_SPLOCKx_SPLOCK13_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SPLOCKx_SPLOCK13          BSEC_SPLOCKx_SPLOCK13_Msk                   /*!< Sticky programming lock for word (13+32*x) */
+#define BSEC_SPLOCKx_SPLOCK14_Pos      (14U)
+#define BSEC_SPLOCKx_SPLOCK14_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SPLOCKx_SPLOCK14          BSEC_SPLOCKx_SPLOCK14_Msk                   /*!< Sticky programming lock for word (14+32*x) */
+#define BSEC_SPLOCKx_SPLOCK15_Pos      (15U)
+#define BSEC_SPLOCKx_SPLOCK15_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SPLOCKx_SPLOCK15          BSEC_SPLOCKx_SPLOCK15_Msk                   /*!< Sticky programming lock for word (15+32*x) */
+#define BSEC_SPLOCKx_SPLOCK16_Pos      (16U)
+#define BSEC_SPLOCKx_SPLOCK16_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SPLOCKx_SPLOCK16          BSEC_SPLOCKx_SPLOCK16_Msk                   /*!< Sticky programming lock for word (16+32*x) */
+#define BSEC_SPLOCKx_SPLOCK17_Pos      (17U)
+#define BSEC_SPLOCKx_SPLOCK17_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SPLOCKx_SPLOCK17          BSEC_SPLOCKx_SPLOCK17_Msk                   /*!< Sticky programming lock for word (17+32*x) */
+#define BSEC_SPLOCKx_SPLOCK18_Pos      (18U)
+#define BSEC_SPLOCKx_SPLOCK18_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SPLOCKx_SPLOCK18          BSEC_SPLOCKx_SPLOCK18_Msk                   /*!< Sticky programming lock for word (18+32*x) */
+#define BSEC_SPLOCKx_SPLOCK19_Pos      (19U)
+#define BSEC_SPLOCKx_SPLOCK19_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SPLOCKx_SPLOCK19          BSEC_SPLOCKx_SPLOCK19_Msk                   /*!< Sticky programming lock for word (19+32*x) */
+#define BSEC_SPLOCKx_SPLOCK20_Pos      (20U)
+#define BSEC_SPLOCKx_SPLOCK20_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SPLOCKx_SPLOCK20          BSEC_SPLOCKx_SPLOCK20_Msk                   /*!< Sticky programming lock for word (20+32*x) */
+#define BSEC_SPLOCKx_SPLOCK21_Pos      (21U)
+#define BSEC_SPLOCKx_SPLOCK21_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SPLOCKx_SPLOCK21          BSEC_SPLOCKx_SPLOCK21_Msk                   /*!< Sticky programming lock for word (21+32*x) */
+#define BSEC_SPLOCKx_SPLOCK22_Pos      (22U)
+#define BSEC_SPLOCKx_SPLOCK22_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SPLOCKx_SPLOCK22          BSEC_SPLOCKx_SPLOCK22_Msk                   /*!< Sticky programming lock for word (22+32*x) */
+#define BSEC_SPLOCKx_SPLOCK23_Pos      (23U)
+#define BSEC_SPLOCKx_SPLOCK23_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SPLOCKx_SPLOCK23          BSEC_SPLOCKx_SPLOCK23_Msk                   /*!< Sticky programming lock for word (23+32*x) */
+#define BSEC_SPLOCKx_SPLOCK24_Pos      (24U)
+#define BSEC_SPLOCKx_SPLOCK24_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SPLOCKx_SPLOCK24          BSEC_SPLOCKx_SPLOCK24_Msk                   /*!< Sticky programming lock for word (24+32*x) */
+#define BSEC_SPLOCKx_SPLOCK25_Pos      (25U)
+#define BSEC_SPLOCKx_SPLOCK25_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SPLOCKx_SPLOCK25          BSEC_SPLOCKx_SPLOCK25_Msk                   /*!< Sticky programming lock for word (25+32*x) */
+#define BSEC_SPLOCKx_SPLOCK26_Pos      (26U)
+#define BSEC_SPLOCKx_SPLOCK26_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SPLOCKx_SPLOCK26          BSEC_SPLOCKx_SPLOCK26_Msk                   /*!< Sticky programming lock for word (26+32*x) */
+#define BSEC_SPLOCKx_SPLOCK27_Pos      (27U)
+#define BSEC_SPLOCKx_SPLOCK27_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SPLOCKx_SPLOCK27          BSEC_SPLOCKx_SPLOCK27_Msk                   /*!< Sticky programming lock for word (27+32*x) */
+#define BSEC_SPLOCKx_SPLOCK28_Pos      (28U)
+#define BSEC_SPLOCKx_SPLOCK28_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SPLOCKx_SPLOCK28          BSEC_SPLOCKx_SPLOCK28_Msk                   /*!< Sticky programming lock for word (28+32*x) */
+#define BSEC_SPLOCKx_SPLOCK29_Pos      (29U)
+#define BSEC_SPLOCKx_SPLOCK29_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SPLOCKx_SPLOCK29          BSEC_SPLOCKx_SPLOCK29_Msk                   /*!< Sticky programming lock for word (29+32*x) */
+#define BSEC_SPLOCKx_SPLOCK30_Pos      (30U)
+#define BSEC_SPLOCKx_SPLOCK30_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SPLOCKx_SPLOCK30          BSEC_SPLOCKx_SPLOCK30_Msk                   /*!< Sticky programming lock for word (30+32*x) */
+#define BSEC_SPLOCKx_SPLOCK31_Pos      (31U)
+#define BSEC_SPLOCKx_SPLOCK31_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SPLOCKx_SPLOCK31          BSEC_SPLOCKx_SPLOCK31_Msk                   /*!< Sticky programming lock for word (31+32*x) */
+
+/*****************  Bit definition for BSEC_SWLOCKx register  *****************/
+#define BSEC_SWLOCKx_SWLOCK0_Pos       (0U)
+#define BSEC_SWLOCKx_SWLOCK0_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SWLOCKx_SWLOCK0           BSEC_SWLOCKx_SWLOCK0_Msk                    /*!< Sticky write lock for shadow register (32*x) */
+#define BSEC_SWLOCKx_SWLOCK1_Pos       (1U)
+#define BSEC_SWLOCKx_SWLOCK1_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SWLOCKx_SWLOCK1           BSEC_SWLOCKx_SWLOCK1_Msk                    /*!< Sticky write lock for shadow register (1+32*x) */
+#define BSEC_SWLOCKx_SWLOCK2_Pos       (2U)
+#define BSEC_SWLOCKx_SWLOCK2_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SWLOCKx_SWLOCK2           BSEC_SWLOCKx_SWLOCK2_Msk                    /*!< Sticky write lock for shadow register (2+32*x) */
+#define BSEC_SWLOCKx_SWLOCK3_Pos       (3U)
+#define BSEC_SWLOCKx_SWLOCK3_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SWLOCKx_SWLOCK3           BSEC_SWLOCKx_SWLOCK3_Msk                    /*!< Sticky write lock for shadow register (3+32*x) */
+#define BSEC_SWLOCKx_SWLOCK4_Pos       (4U)
+#define BSEC_SWLOCKx_SWLOCK4_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SWLOCKx_SWLOCK4           BSEC_SWLOCKx_SWLOCK4_Msk                    /*!< Sticky write lock for shadow register (4+32*x) */
+#define BSEC_SWLOCKx_SWLOCK5_Pos       (5U)
+#define BSEC_SWLOCKx_SWLOCK5_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SWLOCKx_SWLOCK5           BSEC_SWLOCKx_SWLOCK5_Msk                    /*!< Sticky write lock for shadow register (5+32*x) */
+#define BSEC_SWLOCKx_SWLOCK6_Pos       (6U)
+#define BSEC_SWLOCKx_SWLOCK6_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SWLOCKx_SWLOCK6           BSEC_SWLOCKx_SWLOCK6_Msk                    /*!< Sticky write lock for shadow register (6+32*x) */
+#define BSEC_SWLOCKx_SWLOCK7_Pos       (7U)
+#define BSEC_SWLOCKx_SWLOCK7_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SWLOCKx_SWLOCK7           BSEC_SWLOCKx_SWLOCK7_Msk                    /*!< Sticky write lock for shadow register (7+32*x) */
+#define BSEC_SWLOCKx_SWLOCK8_Pos       (8U)
+#define BSEC_SWLOCKx_SWLOCK8_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SWLOCKx_SWLOCK8           BSEC_SWLOCKx_SWLOCK8_Msk                    /*!< Sticky write lock for shadow register (8+32*x) */
+#define BSEC_SWLOCKx_SWLOCK9_Pos       (9U)
+#define BSEC_SWLOCKx_SWLOCK9_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SWLOCKx_SWLOCK9           BSEC_SWLOCKx_SWLOCK9_Msk                    /*!< Sticky write lock for shadow register (9+32*x) */
+#define BSEC_SWLOCKx_SWLOCK10_Pos      (10U)
+#define BSEC_SWLOCKx_SWLOCK10_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SWLOCKx_SWLOCK10          BSEC_SWLOCKx_SWLOCK10_Msk                   /*!< Sticky write lock for shadow register (10+32*x) */
+#define BSEC_SWLOCKx_SWLOCK11_Pos      (11U)
+#define BSEC_SWLOCKx_SWLOCK11_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SWLOCKx_SWLOCK11          BSEC_SWLOCKx_SWLOCK11_Msk                   /*!< Sticky write lock for shadow register (11+32*x) */
+#define BSEC_SWLOCKx_SWLOCK12_Pos      (12U)
+#define BSEC_SWLOCKx_SWLOCK12_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SWLOCKx_SWLOCK12          BSEC_SWLOCKx_SWLOCK12_Msk                   /*!< Sticky write lock for shadow register (12+32*x) */
+#define BSEC_SWLOCKx_SWLOCK13_Pos      (13U)
+#define BSEC_SWLOCKx_SWLOCK13_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SWLOCKx_SWLOCK13          BSEC_SWLOCKx_SWLOCK13_Msk                   /*!< Sticky write lock for shadow register (13+32*x) */
+#define BSEC_SWLOCKx_SWLOCK14_Pos      (14U)
+#define BSEC_SWLOCKx_SWLOCK14_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SWLOCKx_SWLOCK14          BSEC_SWLOCKx_SWLOCK14_Msk                   /*!< Sticky write lock for shadow register (14+32*x) */
+#define BSEC_SWLOCKx_SWLOCK15_Pos      (15U)
+#define BSEC_SWLOCKx_SWLOCK15_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SWLOCKx_SWLOCK15          BSEC_SWLOCKx_SWLOCK15_Msk                   /*!< Sticky write lock for shadow register (15+32*x) */
+#define BSEC_SWLOCKx_SWLOCK16_Pos      (16U)
+#define BSEC_SWLOCKx_SWLOCK16_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SWLOCKx_SWLOCK16          BSEC_SWLOCKx_SWLOCK16_Msk                   /*!< Sticky write lock for shadow register (16+32*x) */
+#define BSEC_SWLOCKx_SWLOCK17_Pos      (17U)
+#define BSEC_SWLOCKx_SWLOCK17_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SWLOCKx_SWLOCK17          BSEC_SWLOCKx_SWLOCK17_Msk                   /*!< Sticky write lock for shadow register (17+32*x) */
+#define BSEC_SWLOCKx_SWLOCK18_Pos      (18U)
+#define BSEC_SWLOCKx_SWLOCK18_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SWLOCKx_SWLOCK18          BSEC_SWLOCKx_SWLOCK18_Msk                   /*!< Sticky write lock for shadow register (18+32*x) */
+#define BSEC_SWLOCKx_SWLOCK19_Pos      (19U)
+#define BSEC_SWLOCKx_SWLOCK19_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SWLOCKx_SWLOCK19          BSEC_SWLOCKx_SWLOCK19_Msk                   /*!< Sticky write lock for shadow register (19+32*x) */
+#define BSEC_SWLOCKx_SWLOCK20_Pos      (20U)
+#define BSEC_SWLOCKx_SWLOCK20_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SWLOCKx_SWLOCK20          BSEC_SWLOCKx_SWLOCK20_Msk                   /*!< Sticky write lock for shadow register (20+32*x) */
+#define BSEC_SWLOCKx_SWLOCK21_Pos      (21U)
+#define BSEC_SWLOCKx_SWLOCK21_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SWLOCKx_SWLOCK21          BSEC_SWLOCKx_SWLOCK21_Msk                   /*!< Sticky write lock for shadow register (21+32*x) */
+#define BSEC_SWLOCKx_SWLOCK22_Pos      (22U)
+#define BSEC_SWLOCKx_SWLOCK22_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SWLOCKx_SWLOCK22          BSEC_SWLOCKx_SWLOCK22_Msk                   /*!< Sticky write lock for shadow register (22+32*x) */
+#define BSEC_SWLOCKx_SWLOCK23_Pos      (23U)
+#define BSEC_SWLOCKx_SWLOCK23_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SWLOCKx_SWLOCK23          BSEC_SWLOCKx_SWLOCK23_Msk                   /*!< Sticky write lock for shadow register (23+32*x) */
+#define BSEC_SWLOCKx_SWLOCK24_Pos      (24U)
+#define BSEC_SWLOCKx_SWLOCK24_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SWLOCKx_SWLOCK24          BSEC_SWLOCKx_SWLOCK24_Msk                   /*!< Sticky write lock for shadow register (24+32*x) */
+#define BSEC_SWLOCKx_SWLOCK25_Pos      (25U)
+#define BSEC_SWLOCKx_SWLOCK25_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SWLOCKx_SWLOCK25          BSEC_SWLOCKx_SWLOCK25_Msk                   /*!< Sticky write lock for shadow register (25+32*x) */
+#define BSEC_SWLOCKx_SWLOCK26_Pos      (26U)
+#define BSEC_SWLOCKx_SWLOCK26_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SWLOCKx_SWLOCK26          BSEC_SWLOCKx_SWLOCK26_Msk                   /*!< Sticky write lock for shadow register (26+32*x) */
+#define BSEC_SWLOCKx_SWLOCK27_Pos      (27U)
+#define BSEC_SWLOCKx_SWLOCK27_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SWLOCKx_SWLOCK27          BSEC_SWLOCKx_SWLOCK27_Msk                   /*!< Sticky write lock for shadow register (27+32*x) */
+#define BSEC_SWLOCKx_SWLOCK28_Pos      (28U)
+#define BSEC_SWLOCKx_SWLOCK28_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SWLOCKx_SWLOCK28          BSEC_SWLOCKx_SWLOCK28_Msk                   /*!< Sticky write lock for shadow register (28+32*x) */
+#define BSEC_SWLOCKx_SWLOCK29_Pos      (29U)
+#define BSEC_SWLOCKx_SWLOCK29_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SWLOCKx_SWLOCK29          BSEC_SWLOCKx_SWLOCK29_Msk                   /*!< Sticky write lock for shadow register (29+32*x) */
+#define BSEC_SWLOCKx_SWLOCK30_Pos      (30U)
+#define BSEC_SWLOCKx_SWLOCK30_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SWLOCKx_SWLOCK30          BSEC_SWLOCKx_SWLOCK30_Msk                   /*!< Sticky write lock for shadow register (30+32*x) */
+#define BSEC_SWLOCKx_SWLOCK31_Pos      (31U)
+#define BSEC_SWLOCKx_SWLOCK31_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SWLOCKx_SWLOCK31          BSEC_SWLOCKx_SWLOCK31_Msk                   /*!< Sticky write lock for shadow register (31+32*x) */
+
+/*****************  Bit definition for BSEC_SRLOCKx register  *****************/
+#define BSEC_SRLOCKx_SRLOCK0_Pos       (0U)
+#define BSEC_SRLOCKx_SRLOCK0_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SRLOCKx_SRLOCK0           BSEC_SRLOCKx_SRLOCK0_Msk                    /*!< Sticky reload lock for fuse word (32*x) */
+#define BSEC_SRLOCKx_SRLOCK1_Pos       (1U)
+#define BSEC_SRLOCKx_SRLOCK1_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SRLOCKx_SRLOCK1           BSEC_SRLOCKx_SRLOCK1_Msk                    /*!< Sticky reload lock for fuse word (1+32*x) */
+#define BSEC_SRLOCKx_SRLOCK2_Pos       (2U)
+#define BSEC_SRLOCKx_SRLOCK2_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SRLOCKx_SRLOCK2           BSEC_SRLOCKx_SRLOCK2_Msk                    /*!< Sticky reload lock for fuse word (2+32*x) */
+#define BSEC_SRLOCKx_SRLOCK3_Pos       (3U)
+#define BSEC_SRLOCKx_SRLOCK3_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SRLOCKx_SRLOCK3           BSEC_SRLOCKx_SRLOCK3_Msk                    /*!< Sticky reload lock for fuse word (3+32*x) */
+#define BSEC_SRLOCKx_SRLOCK4_Pos       (4U)
+#define BSEC_SRLOCKx_SRLOCK4_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SRLOCKx_SRLOCK4           BSEC_SRLOCKx_SRLOCK4_Msk                    /*!< Sticky reload lock for fuse word (4+32*x) */
+#define BSEC_SRLOCKx_SRLOCK5_Pos       (5U)
+#define BSEC_SRLOCKx_SRLOCK5_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SRLOCKx_SRLOCK5           BSEC_SRLOCKx_SRLOCK5_Msk                    /*!< Sticky reload lock for fuse word (5+32*x) */
+#define BSEC_SRLOCKx_SRLOCK6_Pos       (6U)
+#define BSEC_SRLOCKx_SRLOCK6_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SRLOCKx_SRLOCK6           BSEC_SRLOCKx_SRLOCK6_Msk                    /*!< Sticky reload lock for fuse word (6+32*x) */
+#define BSEC_SRLOCKx_SRLOCK7_Pos       (7U)
+#define BSEC_SRLOCKx_SRLOCK7_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SRLOCKx_SRLOCK7           BSEC_SRLOCKx_SRLOCK7_Msk                    /*!< Sticky reload lock for fuse word (7+32*x) */
+#define BSEC_SRLOCKx_SRLOCK8_Pos       (8U)
+#define BSEC_SRLOCKx_SRLOCK8_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SRLOCKx_SRLOCK8           BSEC_SRLOCKx_SRLOCK8_Msk                    /*!< Sticky reload lock for fuse word (8+32*x) */
+#define BSEC_SRLOCKx_SRLOCK9_Pos       (9U)
+#define BSEC_SRLOCKx_SRLOCK9_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SRLOCKx_SRLOCK9           BSEC_SRLOCKx_SRLOCK9_Msk                    /*!< Sticky reload lock for fuse word (9+32*x) */
+#define BSEC_SRLOCKx_SRLOCK10_Pos      (10U)
+#define BSEC_SRLOCKx_SRLOCK10_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SRLOCKx_SRLOCK10          BSEC_SRLOCKx_SRLOCK10_Msk                   /*!< Sticky reload lock for fuse word (10+2*x) */
+#define BSEC_SRLOCKx_SRLOCK11_Pos      (11U)
+#define BSEC_SRLOCKx_SRLOCK11_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SRLOCKx_SRLOCK11          BSEC_SRLOCKx_SRLOCK11_Msk                   /*!< Sticky reload lock for fuse word (11+32*x) */
+#define BSEC_SRLOCKx_SRLOCK12_Pos      (12U)
+#define BSEC_SRLOCKx_SRLOCK12_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SRLOCKx_SRLOCK12          BSEC_SRLOCKx_SRLOCK12_Msk                   /*!< Sticky reload lock for fuse word (12+32*x) */
+#define BSEC_SRLOCKx_SRLOCK13_Pos      (13U)
+#define BSEC_SRLOCKx_SRLOCK13_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SRLOCKx_SRLOCK13          BSEC_SRLOCKx_SRLOCK13_Msk                   /*!< Sticky reload lock for fuse word (13+32*x) */
+#define BSEC_SRLOCKx_SRLOCK14_Pos      (14U)
+#define BSEC_SRLOCKx_SRLOCK14_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SRLOCKx_SRLOCK14          BSEC_SRLOCKx_SRLOCK14_Msk                   /*!< Sticky reload lock for fuse word (14+32*x) */
+#define BSEC_SRLOCKx_SRLOCK15_Pos      (15U)
+#define BSEC_SRLOCKx_SRLOCK15_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SRLOCKx_SRLOCK15          BSEC_SRLOCKx_SRLOCK15_Msk                   /*!< Sticky reload lock for fuse word (15+32*x) */
+#define BSEC_SRLOCKx_SRLOCK16_Pos      (16U)
+#define BSEC_SRLOCKx_SRLOCK16_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SRLOCKx_SRLOCK16          BSEC_SRLOCKx_SRLOCK16_Msk                   /*!< Sticky reload lock for fuse word (16+32*x) */
+#define BSEC_SRLOCKx_SRLOCK17_Pos      (17U)
+#define BSEC_SRLOCKx_SRLOCK17_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SRLOCKx_SRLOCK17          BSEC_SRLOCKx_SRLOCK17_Msk                   /*!< Sticky reload lock for fuse word (17+32*x) */
+#define BSEC_SRLOCKx_SRLOCK18_Pos      (18U)
+#define BSEC_SRLOCKx_SRLOCK18_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SRLOCKx_SRLOCK18          BSEC_SRLOCKx_SRLOCK18_Msk                   /*!< Sticky reload lock for fuse word (18+32*x) */
+#define BSEC_SRLOCKx_SRLOCK19_Pos      (19U)
+#define BSEC_SRLOCKx_SRLOCK19_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SRLOCKx_SRLOCK19          BSEC_SRLOCKx_SRLOCK19_Msk                   /*!< Sticky reload lock for fuse word (19+32*x) */
+#define BSEC_SRLOCKx_SRLOCK20_Pos      (20U)
+#define BSEC_SRLOCKx_SRLOCK20_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SRLOCKx_SRLOCK20          BSEC_SRLOCKx_SRLOCK20_Msk                   /*!< Sticky reload lock for fuse word (20+32*x) */
+#define BSEC_SRLOCKx_SRLOCK21_Pos      (21U)
+#define BSEC_SRLOCKx_SRLOCK21_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SRLOCKx_SRLOCK21          BSEC_SRLOCKx_SRLOCK21_Msk                   /*!< Sticky reload lock for fuse word (21+32*x) */
+#define BSEC_SRLOCKx_SRLOCK22_Pos      (22U)
+#define BSEC_SRLOCKx_SRLOCK22_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SRLOCKx_SRLOCK22          BSEC_SRLOCKx_SRLOCK22_Msk                   /*!< Sticky reload lock for fuse word (22+32*x) */
+#define BSEC_SRLOCKx_SRLOCK23_Pos      (23U)
+#define BSEC_SRLOCKx_SRLOCK23_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SRLOCKx_SRLOCK23          BSEC_SRLOCKx_SRLOCK23_Msk                   /*!< Sticky reload lock for fuse word (23+32*x) */
+#define BSEC_SRLOCKx_SRLOCK24_Pos      (24U)
+#define BSEC_SRLOCKx_SRLOCK24_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SRLOCKx_SRLOCK24          BSEC_SRLOCKx_SRLOCK24_Msk                   /*!< Sticky reload lock for fuse word (24+32*x) */
+#define BSEC_SRLOCKx_SRLOCK25_Pos      (25U)
+#define BSEC_SRLOCKx_SRLOCK25_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SRLOCKx_SRLOCK25          BSEC_SRLOCKx_SRLOCK25_Msk                   /*!< Sticky reload lock for fuse word (25+32*x) */
+#define BSEC_SRLOCKx_SRLOCK26_Pos      (26U)
+#define BSEC_SRLOCKx_SRLOCK26_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SRLOCKx_SRLOCK26          BSEC_SRLOCKx_SRLOCK26_Msk                   /*!< Sticky reload lock for fuse word (26+32*x) */
+#define BSEC_SRLOCKx_SRLOCK27_Pos      (27U)
+#define BSEC_SRLOCKx_SRLOCK27_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SRLOCKx_SRLOCK27          BSEC_SRLOCKx_SRLOCK27_Msk                   /*!< Sticky reload lock for fuse word (27+32*x) */
+#define BSEC_SRLOCKx_SRLOCK28_Pos      (28U)
+#define BSEC_SRLOCKx_SRLOCK28_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SRLOCKx_SRLOCK28          BSEC_SRLOCKx_SRLOCK28_Msk                   /*!< Sticky reload lock for fuse word (28+32*x) */
+#define BSEC_SRLOCKx_SRLOCK29_Pos      (29U)
+#define BSEC_SRLOCKx_SRLOCK29_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SRLOCKx_SRLOCK29          BSEC_SRLOCKx_SRLOCK29_Msk                   /*!< Sticky reload lock for fuse word (29+32*x) */
+#define BSEC_SRLOCKx_SRLOCK30_Pos      (30U)
+#define BSEC_SRLOCKx_SRLOCK30_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SRLOCKx_SRLOCK30          BSEC_SRLOCKx_SRLOCK30_Msk                   /*!< Sticky reload lock for fuse word (30+32*x) */
+#define BSEC_SRLOCKx_SRLOCK31_Pos      (31U)
+#define BSEC_SRLOCKx_SRLOCK31_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SRLOCKx_SRLOCK31          BSEC_SRLOCKx_SRLOCK31_Msk                   /*!< Sticky reload lock for fuse word (31+32*x) */
+
+/****************  Bit definition for BSEC_OTPVLDRx register  *****************/
+#define BSEC_OTPVLDRx_VLDF0_Pos        (0U)
+#define BSEC_OTPVLDRx_VLDF0_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos)           /*!< 0x00000001 */
+#define BSEC_OTPVLDRx_VLDF0            BSEC_OTPVLDRx_VLDF0_Msk                     /*!< Valid flag for shadow register (32*x) */
+#define BSEC_OTPVLDRx_VLDF1_Pos        (1U)
+#define BSEC_OTPVLDRx_VLDF1_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos)           /*!< 0x00000002 */
+#define BSEC_OTPVLDRx_VLDF1            BSEC_OTPVLDRx_VLDF1_Msk                     /*!< Valid flag for shadow register (1+32*x) */
+#define BSEC_OTPVLDRx_VLDF2_Pos        (2U)
+#define BSEC_OTPVLDRx_VLDF2_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos)           /*!< 0x00000004 */
+#define BSEC_OTPVLDRx_VLDF2            BSEC_OTPVLDRx_VLDF2_Msk                     /*!< Valid flag for shadow register (2+32*x) */
+#define BSEC_OTPVLDRx_VLDF3_Pos        (3U)
+#define BSEC_OTPVLDRx_VLDF3_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos)           /*!< 0x00000008 */
+#define BSEC_OTPVLDRx_VLDF3            BSEC_OTPVLDRx_VLDF3_Msk                     /*!< Valid flag for shadow register (3+32*x) */
+#define BSEC_OTPVLDRx_VLDF4_Pos        (4U)
+#define BSEC_OTPVLDRx_VLDF4_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos)           /*!< 0x00000010 */
+#define BSEC_OTPVLDRx_VLDF4            BSEC_OTPVLDRx_VLDF4_Msk                     /*!< Valid flag for shadow register (4+32*x) */
+#define BSEC_OTPVLDRx_VLDF5_Pos        (5U)
+#define BSEC_OTPVLDRx_VLDF5_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos)           /*!< 0x00000020 */
+#define BSEC_OTPVLDRx_VLDF5            BSEC_OTPVLDRx_VLDF5_Msk                     /*!< Valid flag for shadow register (5+32*x) */
+#define BSEC_OTPVLDRx_VLDF6_Pos        (6U)
+#define BSEC_OTPVLDRx_VLDF6_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos)           /*!< 0x00000040 */
+#define BSEC_OTPVLDRx_VLDF6            BSEC_OTPVLDRx_VLDF6_Msk                     /*!< Valid flag for shadow register (6+32*x) */
+#define BSEC_OTPVLDRx_VLDF7_Pos        (7U)
+#define BSEC_OTPVLDRx_VLDF7_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos)           /*!< 0x00000080 */
+#define BSEC_OTPVLDRx_VLDF7            BSEC_OTPVLDRx_VLDF7_Msk                     /*!< Valid flag for shadow register (7+32*x) */
+#define BSEC_OTPVLDRx_VLDF8_Pos        (8U)
+#define BSEC_OTPVLDRx_VLDF8_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos)           /*!< 0x00000100 */
+#define BSEC_OTPVLDRx_VLDF8            BSEC_OTPVLDRx_VLDF8_Msk                     /*!< Valid flag for shadow register (8+32*x) */
+#define BSEC_OTPVLDRx_VLDF9_Pos        (9U)
+#define BSEC_OTPVLDRx_VLDF9_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos)           /*!< 0x00000200 */
+#define BSEC_OTPVLDRx_VLDF9            BSEC_OTPVLDRx_VLDF9_Msk                     /*!< Valid flag for shadow register (9+32*x) */
+#define BSEC_OTPVLDRx_VLDF10_Pos       (10U)
+#define BSEC_OTPVLDRx_VLDF10_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos)          /*!< 0x00000400 */
+#define BSEC_OTPVLDRx_VLDF10           BSEC_OTPVLDRx_VLDF10_Msk                    /*!< Valid flag for shadow register (10+32*x) */
+#define BSEC_OTPVLDRx_VLDF11_Pos       (11U)
+#define BSEC_OTPVLDRx_VLDF11_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos)          /*!< 0x00000800 */
+#define BSEC_OTPVLDRx_VLDF11           BSEC_OTPVLDRx_VLDF11_Msk                    /*!< Valid flag for shadow register (11+32*x) */
+#define BSEC_OTPVLDRx_VLDF12_Pos       (12U)
+#define BSEC_OTPVLDRx_VLDF12_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos)          /*!< 0x00001000 */
+#define BSEC_OTPVLDRx_VLDF12           BSEC_OTPVLDRx_VLDF12_Msk                    /*!< Valid flag for shadow register (12+32*x) */
+#define BSEC_OTPVLDRx_VLDF13_Pos       (13U)
+#define BSEC_OTPVLDRx_VLDF13_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos)          /*!< 0x00002000 */
+#define BSEC_OTPVLDRx_VLDF13           BSEC_OTPVLDRx_VLDF13_Msk                    /*!< Valid flag for shadow register (13+32*x) */
+#define BSEC_OTPVLDRx_VLDF14_Pos       (14U)
+#define BSEC_OTPVLDRx_VLDF14_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos)          /*!< 0x00004000 */
+#define BSEC_OTPVLDRx_VLDF14           BSEC_OTPVLDRx_VLDF14_Msk                    /*!< Valid flag for shadow register (14+32*x) */
+#define BSEC_OTPVLDRx_VLDF15_Pos       (15U)
+#define BSEC_OTPVLDRx_VLDF15_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos)          /*!< 0x00008000 */
+#define BSEC_OTPVLDRx_VLDF15           BSEC_OTPVLDRx_VLDF15_Msk                    /*!< Valid flag for shadow register (15+32*x) */
+#define BSEC_OTPVLDRx_VLDF16_Pos       (16U)
+#define BSEC_OTPVLDRx_VLDF16_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos)          /*!< 0x00010000 */
+#define BSEC_OTPVLDRx_VLDF16           BSEC_OTPVLDRx_VLDF16_Msk                    /*!< Valid flag for shadow register (16+32*x) */
+#define BSEC_OTPVLDRx_VLDF17_Pos       (17U)
+#define BSEC_OTPVLDRx_VLDF17_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos)          /*!< 0x00020000 */
+#define BSEC_OTPVLDRx_VLDF17           BSEC_OTPVLDRx_VLDF17_Msk                    /*!< Valid flag for shadow register (17+32*x) */
+#define BSEC_OTPVLDRx_VLDF18_Pos       (18U)
+#define BSEC_OTPVLDRx_VLDF18_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos)          /*!< 0x00040000 */
+#define BSEC_OTPVLDRx_VLDF18           BSEC_OTPVLDRx_VLDF18_Msk                    /*!< Valid flag for shadow register (18+32*x) */
+#define BSEC_OTPVLDRx_VLDF19_Pos       (19U)
+#define BSEC_OTPVLDRx_VLDF19_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos)          /*!< 0x00080000 */
+#define BSEC_OTPVLDRx_VLDF19           BSEC_OTPVLDRx_VLDF19_Msk                    /*!< Valid flag for shadow register (19+32*x) */
+#define BSEC_OTPVLDRx_VLDF20_Pos       (20U)
+#define BSEC_OTPVLDRx_VLDF20_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos)          /*!< 0x00100000 */
+#define BSEC_OTPVLDRx_VLDF20           BSEC_OTPVLDRx_VLDF20_Msk                    /*!< Valid flag for shadow register (20+32*x) */
+#define BSEC_OTPVLDRx_VLDF21_Pos       (21U)
+#define BSEC_OTPVLDRx_VLDF21_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos)          /*!< 0x00200000 */
+#define BSEC_OTPVLDRx_VLDF21           BSEC_OTPVLDRx_VLDF21_Msk                    /*!< Valid flag for shadow register (21+32*x) */
+#define BSEC_OTPVLDRx_VLDF22_Pos       (22U)
+#define BSEC_OTPVLDRx_VLDF22_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos)          /*!< 0x00400000 */
+#define BSEC_OTPVLDRx_VLDF22           BSEC_OTPVLDRx_VLDF22_Msk                    /*!< Valid flag for shadow register (22+32*x) */
+#define BSEC_OTPVLDRx_VLDF23_Pos       (23U)
+#define BSEC_OTPVLDRx_VLDF23_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos)          /*!< 0x00800000 */
+#define BSEC_OTPVLDRx_VLDF23           BSEC_OTPVLDRx_VLDF23_Msk                    /*!< Valid flag for shadow register (23+32*x) */
+#define BSEC_OTPVLDRx_VLDF24_Pos       (24U)
+#define BSEC_OTPVLDRx_VLDF24_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos)          /*!< 0x01000000 */
+#define BSEC_OTPVLDRx_VLDF24           BSEC_OTPVLDRx_VLDF24_Msk                    /*!< Valid flag for shadow register (24+32*x) */
+#define BSEC_OTPVLDRx_VLDF25_Pos       (25U)
+#define BSEC_OTPVLDRx_VLDF25_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos)          /*!< 0x02000000 */
+#define BSEC_OTPVLDRx_VLDF25           BSEC_OTPVLDRx_VLDF25_Msk                    /*!< Valid flag for shadow register (25+32*x) */
+#define BSEC_OTPVLDRx_VLDF26_Pos       (26U)
+#define BSEC_OTPVLDRx_VLDF26_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos)          /*!< 0x04000000 */
+#define BSEC_OTPVLDRx_VLDF26           BSEC_OTPVLDRx_VLDF26_Msk                    /*!< Valid flag for shadow register (26+32*x) */
+#define BSEC_OTPVLDRx_VLDF27_Pos       (27U)
+#define BSEC_OTPVLDRx_VLDF27_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos)          /*!< 0x08000000 */
+#define BSEC_OTPVLDRx_VLDF27           BSEC_OTPVLDRx_VLDF27_Msk                    /*!< Valid flag for shadow register (27+32*x) */
+#define BSEC_OTPVLDRx_VLDF28_Pos       (28U)
+#define BSEC_OTPVLDRx_VLDF28_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos)          /*!< 0x10000000 */
+#define BSEC_OTPVLDRx_VLDF28           BSEC_OTPVLDRx_VLDF28_Msk                    /*!< Valid flag for shadow register (28+32*x) */
+#define BSEC_OTPVLDRx_VLDF29_Pos       (29U)
+#define BSEC_OTPVLDRx_VLDF29_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos)          /*!< 0x20000000 */
+#define BSEC_OTPVLDRx_VLDF29           BSEC_OTPVLDRx_VLDF29_Msk                    /*!< Valid flag for shadow register (29+32*x) */
+#define BSEC_OTPVLDRx_VLDF30_Pos       (30U)
+#define BSEC_OTPVLDRx_VLDF30_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos)          /*!< 0x40000000 */
+#define BSEC_OTPVLDRx_VLDF30           BSEC_OTPVLDRx_VLDF30_Msk                    /*!< Valid flag for shadow register (30+32*x) */
+#define BSEC_OTPVLDRx_VLDF31_Pos       (31U)
+#define BSEC_OTPVLDRx_VLDF31_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos)          /*!< 0x80000000 */
+#define BSEC_OTPVLDRx_VLDF31           BSEC_OTPVLDRx_VLDF31_Msk                    /*!< Valid flag for shadow register (31+32*x) */
+
+/******************  Bit definition for BSEC_SFSRx register  ******************/
+#define BSEC_SFSRx_SFW0_Pos            (0U)
+#define BSEC_SFSRx_SFW0_Msk            (0x1UL << BSEC_SFSRx_SFW0_Pos)               /*!< 0x00000001 */
+#define BSEC_SFSRx_SFW0                BSEC_SFSRx_SFW0_Msk                         /*!< Shadowed fuse word (32*x) */
+#define BSEC_SFSRx_SFW1_Pos            (1U)
+#define BSEC_SFSRx_SFW1_Msk            (0x1UL << BSEC_SFSRx_SFW1_Pos)               /*!< 0x00000002 */
+#define BSEC_SFSRx_SFW1                BSEC_SFSRx_SFW1_Msk                         /*!< Shadowed fuse word (1+32*x) */
+#define BSEC_SFSRx_SFW2_Pos            (2U)
+#define BSEC_SFSRx_SFW2_Msk            (0x1UL << BSEC_SFSRx_SFW2_Pos)               /*!< 0x00000004 */
+#define BSEC_SFSRx_SFW2                BSEC_SFSRx_SFW2_Msk                         /*!< Shadowed fuse word (2+32*x) */
+#define BSEC_SFSRx_SFW3_Pos            (3U)
+#define BSEC_SFSRx_SFW3_Msk            (0x1UL << BSEC_SFSRx_SFW3_Pos)               /*!< 0x00000008 */
+#define BSEC_SFSRx_SFW3                BSEC_SFSRx_SFW3_Msk                         /*!< Shadowed fuse word (3+32*x) */
+#define BSEC_SFSRx_SFW4_Pos            (4U)
+#define BSEC_SFSRx_SFW4_Msk            (0x1UL << BSEC_SFSRx_SFW4_Pos)               /*!< 0x00000010 */
+#define BSEC_SFSRx_SFW4                BSEC_SFSRx_SFW4_Msk                         /*!< Shadowed fuse word (4+32*x) */
+#define BSEC_SFSRx_SFW5_Pos            (5U)
+#define BSEC_SFSRx_SFW5_Msk            (0x1UL << BSEC_SFSRx_SFW5_Pos)               /*!< 0x00000020 */
+#define BSEC_SFSRx_SFW5                BSEC_SFSRx_SFW5_Msk                         /*!< Shadowed fuse word (5+32*x) */
+#define BSEC_SFSRx_SFW6_Pos            (6U)
+#define BSEC_SFSRx_SFW6_Msk            (0x1UL << BSEC_SFSRx_SFW6_Pos)               /*!< 0x00000040 */
+#define BSEC_SFSRx_SFW6                BSEC_SFSRx_SFW6_Msk                         /*!< Shadowed fuse word (6+32*x) */
+#define BSEC_SFSRx_SFW7_Pos            (7U)
+#define BSEC_SFSRx_SFW7_Msk            (0x1UL << BSEC_SFSRx_SFW7_Pos)               /*!< 0x00000080 */
+#define BSEC_SFSRx_SFW7                BSEC_SFSRx_SFW7_Msk                         /*!< Shadowed fuse word (7+32*x) */
+#define BSEC_SFSRx_SFW8_Pos            (8U)
+#define BSEC_SFSRx_SFW8_Msk            (0x1UL << BSEC_SFSRx_SFW8_Pos)               /*!< 0x00000100 */
+#define BSEC_SFSRx_SFW8                BSEC_SFSRx_SFW8_Msk                         /*!< Shadowed fuse word (8+32*x) */
+#define BSEC_SFSRx_SFW9_Pos            (9U)
+#define BSEC_SFSRx_SFW9_Msk            (0x1UL << BSEC_SFSRx_SFW9_Pos)               /*!< 0x00000200 */
+#define BSEC_SFSRx_SFW9                BSEC_SFSRx_SFW9_Msk                         /*!< Shadowed fuse word (9+32*x) */
+#define BSEC_SFSRx_SFW10_Pos           (10U)
+#define BSEC_SFSRx_SFW10_Msk           (0x1UL << BSEC_SFSRx_SFW10_Pos)              /*!< 0x00000400 */
+#define BSEC_SFSRx_SFW10               BSEC_SFSRx_SFW10_Msk                        /*!< Shadowed fuse word (10+32*x) */
+#define BSEC_SFSRx_SFW11_Pos           (11U)
+#define BSEC_SFSRx_SFW11_Msk           (0x1UL << BSEC_SFSRx_SFW11_Pos)              /*!< 0x00000800 */
+#define BSEC_SFSRx_SFW11               BSEC_SFSRx_SFW11_Msk                        /*!< Shadowed fuse word (11+32*x) */
+#define BSEC_SFSRx_SFW12_Pos           (12U)
+#define BSEC_SFSRx_SFW12_Msk           (0x1UL << BSEC_SFSRx_SFW12_Pos)              /*!< 0x00001000 */
+#define BSEC_SFSRx_SFW12               BSEC_SFSRx_SFW12_Msk                        /*!< Shadowed fuse word (12+32*x) */
+#define BSEC_SFSRx_SFW13_Pos           (13U)
+#define BSEC_SFSRx_SFW13_Msk           (0x1UL << BSEC_SFSRx_SFW13_Pos)              /*!< 0x00002000 */
+#define BSEC_SFSRx_SFW13               BSEC_SFSRx_SFW13_Msk                        /*!< Shadowed fuse word (13+32*x) */
+#define BSEC_SFSRx_SFW14_Pos           (14U)
+#define BSEC_SFSRx_SFW14_Msk           (0x1UL << BSEC_SFSRx_SFW14_Pos)              /*!< 0x00004000 */
+#define BSEC_SFSRx_SFW14               BSEC_SFSRx_SFW14_Msk                        /*!< Shadowed fuse word (14+32*x) */
+#define BSEC_SFSRx_SFW15_Pos           (15U)
+#define BSEC_SFSRx_SFW15_Msk           (0x1UL << BSEC_SFSRx_SFW15_Pos)              /*!< 0x00008000 */
+#define BSEC_SFSRx_SFW15               BSEC_SFSRx_SFW15_Msk                        /*!< Shadowed fuse word (15+32*x) */
+#define BSEC_SFSRx_SFW16_Pos           (16U)
+#define BSEC_SFSRx_SFW16_Msk           (0x1UL << BSEC_SFSRx_SFW16_Pos)              /*!< 0x00010000 */
+#define BSEC_SFSRx_SFW16               BSEC_SFSRx_SFW16_Msk                        /*!< Shadowed fuse word (16+32*x) */
+#define BSEC_SFSRx_SFW17_Pos           (17U)
+#define BSEC_SFSRx_SFW17_Msk           (0x1UL << BSEC_SFSRx_SFW17_Pos)              /*!< 0x00020000 */
+#define BSEC_SFSRx_SFW17               BSEC_SFSRx_SFW17_Msk                        /*!< Shadowed fuse word (17+32*x) */
+#define BSEC_SFSRx_SFW18_Pos           (18U)
+#define BSEC_SFSRx_SFW18_Msk           (0x1UL << BSEC_SFSRx_SFW18_Pos)              /*!< 0x00040000 */
+#define BSEC_SFSRx_SFW18               BSEC_SFSRx_SFW18_Msk                        /*!< Shadowed fuse word (18+32*x) */
+#define BSEC_SFSRx_SFW19_Pos           (19U)
+#define BSEC_SFSRx_SFW19_Msk           (0x1UL << BSEC_SFSRx_SFW19_Pos)              /*!< 0x00080000 */
+#define BSEC_SFSRx_SFW19               BSEC_SFSRx_SFW19_Msk                        /*!< Shadowed fuse word (19+32*x) */
+#define BSEC_SFSRx_SFW20_Pos           (20U)
+#define BSEC_SFSRx_SFW20_Msk           (0x1UL << BSEC_SFSRx_SFW20_Pos)              /*!< 0x00100000 */
+#define BSEC_SFSRx_SFW20               BSEC_SFSRx_SFW20_Msk                        /*!< Shadowed fuse word (20+32*x) */
+#define BSEC_SFSRx_SFW21_Pos           (21U)
+#define BSEC_SFSRx_SFW21_Msk           (0x1UL << BSEC_SFSRx_SFW21_Pos)              /*!< 0x00200000 */
+#define BSEC_SFSRx_SFW21               BSEC_SFSRx_SFW21_Msk                        /*!< Shadowed fuse word (21+32*x) */
+#define BSEC_SFSRx_SFW22_Pos           (22U)
+#define BSEC_SFSRx_SFW22_Msk           (0x1UL << BSEC_SFSRx_SFW22_Pos)              /*!< 0x00400000 */
+#define BSEC_SFSRx_SFW22               BSEC_SFSRx_SFW22_Msk                        /*!< Shadowed fuse word (22+32*x) */
+#define BSEC_SFSRx_SFW23_Pos           (23U)
+#define BSEC_SFSRx_SFW23_Msk           (0x1UL << BSEC_SFSRx_SFW23_Pos)              /*!< 0x00800000 */
+#define BSEC_SFSRx_SFW23               BSEC_SFSRx_SFW23_Msk                        /*!< Shadowed fuse word (23+32*x) */
+#define BSEC_SFSRx_SFW24_Pos           (24U)
+#define BSEC_SFSRx_SFW24_Msk           (0x1UL << BSEC_SFSRx_SFW24_Pos)              /*!< 0x01000000 */
+#define BSEC_SFSRx_SFW24               BSEC_SFSRx_SFW24_Msk                        /*!< Shadowed fuse word (24+32*x) */
+#define BSEC_SFSRx_SFW25_Pos           (25U)
+#define BSEC_SFSRx_SFW25_Msk           (0x1UL << BSEC_SFSRx_SFW25_Pos)              /*!< 0x02000000 */
+#define BSEC_SFSRx_SFW25               BSEC_SFSRx_SFW25_Msk                        /*!< Shadowed fuse word (25+32*x) */
+#define BSEC_SFSRx_SFW26_Pos           (26U)
+#define BSEC_SFSRx_SFW26_Msk           (0x1UL << BSEC_SFSRx_SFW26_Pos)              /*!< 0x04000000 */
+#define BSEC_SFSRx_SFW26               BSEC_SFSRx_SFW26_Msk                        /*!< Shadowed fuse word (26+32*x) */
+#define BSEC_SFSRx_SFW27_Pos           (27U)
+#define BSEC_SFSRx_SFW27_Msk           (0x1UL << BSEC_SFSRx_SFW27_Pos)              /*!< 0x08000000 */
+#define BSEC_SFSRx_SFW27               BSEC_SFSRx_SFW27_Msk                        /*!< Shadowed fuse word (27+32*x) */
+#define BSEC_SFSRx_SFW28_Pos           (28U)
+#define BSEC_SFSRx_SFW28_Msk           (0x1UL << BSEC_SFSRx_SFW28_Pos)              /*!< 0x10000000 */
+#define BSEC_SFSRx_SFW28               BSEC_SFSRx_SFW28_Msk                        /*!< Shadowed fuse word (28+32*x) */
+#define BSEC_SFSRx_SFW29_Pos           (29U)
+#define BSEC_SFSRx_SFW29_Msk           (0x1UL << BSEC_SFSRx_SFW29_Pos)              /*!< 0x20000000 */
+#define BSEC_SFSRx_SFW29               BSEC_SFSRx_SFW29_Msk                        /*!< Shadowed fuse word (29+32*x) */
+#define BSEC_SFSRx_SFW30_Pos           (30U)
+#define BSEC_SFSRx_SFW30_Msk           (0x1UL << BSEC_SFSRx_SFW30_Pos)              /*!< 0x40000000 */
+#define BSEC_SFSRx_SFW30               BSEC_SFSRx_SFW30_Msk                        /*!< Shadowed fuse word (30+32*x) */
+#define BSEC_SFSRx_SFW31_Pos           (31U)
+#define BSEC_SFSRx_SFW31_Msk           (0x1UL << BSEC_SFSRx_SFW31_Pos)              /*!< 0x80000000 */
+#define BSEC_SFSRx_SFW31               BSEC_SFSRx_SFW31_Msk                        /*!< Shadowed fuse word (31+32*x) */
+
+/******************  Bit definition for BSEC_OTPCR register  ******************/
+#define BSEC_OTPCR_ADDR_Pos            (0U)
+#define BSEC_OTPCR_ADDR_Msk            (0x1FFUL << BSEC_OTPCR_ADDR_Pos)             /*!< 0x000001FF */
+#define BSEC_OTPCR_ADDR                BSEC_OTPCR_ADDR_Msk                         /*!< Fuse word address */
+#define BSEC_OTPCR_PROG_Pos            (13U)
+#define BSEC_OTPCR_PROG_Msk            (0x1UL << BSEC_OTPCR_PROG_Pos)               /*!< 0x00002000 */
+#define BSEC_OTPCR_PROG                BSEC_OTPCR_PROG_Msk                         /*!< Fuse word programming */
+#define BSEC_OTPCR_PPLOCK_Pos          (14U)
+#define BSEC_OTPCR_PPLOCK_Msk          (0x1UL << BSEC_OTPCR_PPLOCK_Pos)             /*!< 0x00004000 */
+#define BSEC_OTPCR_PPLOCK              BSEC_OTPCR_PPLOCK_Msk                       /*!< Permanent programming lock */
+#define BSEC_OTPCR_LASTCID_Pos         (19U)
+#define BSEC_OTPCR_LASTCID_Msk         (0x7UL << BSEC_OTPCR_LASTCID_Pos)            /*!< 0x00380000 */
+#define BSEC_OTPCR_LASTCID             BSEC_OTPCR_LASTCID_Msk                      /*!< Last CID */
+
+/*******************  Bit definition for BSEC_WDR register  *******************/
+#define BSEC_WDR_WRDATA_Pos            (0U)
+#define BSEC_WDR_WRDATA_Msk            (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos)        /*!< 0xFFFFFFFF */
+#define BSEC_WDR_WRDATA                BSEC_WDR_WRDATA_Msk                         /*!< OTP write data */
+
+/****************  Bit definition for BSEC_SCRATCHRx register  ****************/
+#define BSEC_SCRATCHRx_SDATA_Pos       (0U)
+#define BSEC_SCRATCHRx_SDATA_Msk       (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_SCRATCHRx_SDATA           BSEC_SCRATCHRx_SDATA_Msk                    /*!< Scratch data */
+
+/******************  Bit definition for BSEC_LOCKR register  ******************/
+#define BSEC_LOCKR_GWLOCK_Pos          (0U)
+#define BSEC_LOCKR_GWLOCK_Msk          (0x1UL << BSEC_LOCKR_GWLOCK_Pos)             /*!< 0x00000001 */
+#define BSEC_LOCKR_GWLOCK              BSEC_LOCKR_GWLOCK_Msk                       /*!< Global write lock */
+#define BSEC_LOCKR_HKLOCK_Pos          (2U)
+#define BSEC_LOCKR_HKLOCK_Msk          (0x1UL << BSEC_LOCKR_HKLOCK_Pos)             /*!< 0x00000004 */
+#define BSEC_LOCKR_HKLOCK              BSEC_LOCKR_HKLOCK_Msk                       /*!< Hardware key lock */
+
+/*****************  Bit definition for BSEC_JTAGINR register  *****************/
+#define BSEC_JTAGINR_JDATAIN_Pos       (0U)
+#define BSEC_JTAGINR_JDATAIN_Msk       (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_JTAGINR_JDATAIN           BSEC_JTAGINR_JDATAIN_Msk                    /*!< JTAG input data */
+
+/****************  Bit definition for BSEC_JTAGOUTR register  *****************/
+#define BSEC_JTAGOUTR_JDATAOUT_Pos     (0U)
+#define BSEC_JTAGOUTR_JDATAOUT_Msk     (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define BSEC_JTAGOUTR_JDATAOUT         BSEC_JTAGOUTR_JDATAOUT_Msk                  /*!< JTAG output data */
+
+/*****************  Bit definition for BSEC_UNMAPR register  ******************/
+#define BSEC_UNMAPR_UNMAP_Pos          (0U)
+#define BSEC_UNMAPR_UNMAP_Msk          (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos)      /*!< 0xFFFFFFFF */
+#define BSEC_UNMAPR_UNMAP              BSEC_UNMAPR_UNMAP_Msk                       /*!< Unmap key */
+
+/*******************  Bit definition for BSEC_SR register  ********************/
+#define BSEC_SR_HVALID_Pos             (1U)
+#define BSEC_SR_HVALID_Msk             (0x1UL << BSEC_SR_HVALID_Pos)                /*!< 0x00000002 */
+#define BSEC_SR_HVALID                 BSEC_SR_HVALID_Msk                          /*!< Hardware key valid */
+#define BSEC_SR_DBGREQ_Pos             (16U)
+#define BSEC_SR_DBGREQ_Msk             (0x1UL << BSEC_SR_DBGREQ_Pos)                /*!< 0x00010000 */
+#define BSEC_SR_DBGREQ                 BSEC_SR_DBGREQ_Msk                          /*!< Debug request */
+#define BSEC_SR_NVSTATE_Pos            (26U)
+#define BSEC_SR_NVSTATE_Msk            (0x3FUL << BSEC_SR_NVSTATE_Pos)              /*!< 0xFC000000 */
+#define BSEC_SR_NVSTATE                BSEC_SR_NVSTATE_Msk                         /*!< Non-volatile state */
+
+/******************  Bit definition for BSEC_OTPSR register  ******************/
+#define BSEC_OTPSR_BUSY_Pos            (0U)
+#define BSEC_OTPSR_BUSY_Msk            (0x1UL << BSEC_OTPSR_BUSY_Pos)               /*!< 0x00000001 */
+#define BSEC_OTPSR_BUSY                BSEC_OTPSR_BUSY_Msk                         /*!< Busy flag */
+#define BSEC_OTPSR_INIT_DONE_Pos       (1U)
+#define BSEC_OTPSR_INIT_DONE_Msk       (0x1UL << BSEC_OTPSR_INIT_DONE_Pos)          /*!< 0x00000002 */
+#define BSEC_OTPSR_INIT_DONE           BSEC_OTPSR_INIT_DONE_Msk                    /*!< Initialization done */
+#define BSEC_OTPSR_HIDEUP_Pos          (2U)
+#define BSEC_OTPSR_HIDEUP_Msk          (0x1UL << BSEC_OTPSR_HIDEUP_Pos)             /*!< 0x00000004 */
+#define BSEC_OTPSR_HIDEUP              BSEC_OTPSR_HIDEUP_Msk                       /*!< Hide upper fuse words */
+#define BSEC_OTPSR_OTPNVIR_Pos         (4U)
+#define BSEC_OTPSR_OTPNVIR_Msk         (0x1UL << BSEC_OTPSR_OTPNVIR_Pos)            /*!< 0x00000010 */
+#define BSEC_OTPSR_OTPNVIR             BSEC_OTPSR_OTPNVIR_Msk                      /*!< OTP not virgin */
+#define BSEC_OTPSR_OTPERR_Pos          (5U)
+#define BSEC_OTPSR_OTPERR_Msk          (0x1UL << BSEC_OTPSR_OTPERR_Pos)             /*!< 0x00000020 */
+#define BSEC_OTPSR_OTPERR              BSEC_OTPSR_OTPERR_Msk                       /*!< OTP with error */
+#define BSEC_OTPSR_OTPSEC_Pos          (6U)
+#define BSEC_OTPSR_OTPSEC_Msk          (0x1UL << BSEC_OTPSR_OTPSEC_Pos)             /*!< 0x00000040 */
+#define BSEC_OTPSR_OTPSEC              BSEC_OTPSR_OTPSEC_Msk                       /*!< OTP with single error correction */
+#define BSEC_OTPSR_PROGFAIL_Pos        (16U)
+#define BSEC_OTPSR_PROGFAIL_Msk        (0x1UL << BSEC_OTPSR_PROGFAIL_Pos)           /*!< 0x00010000 */
+#define BSEC_OTPSR_PROGFAIL            BSEC_OTPSR_PROGFAIL_Msk                     /*!< Programming failed */
+#define BSEC_OTPSR_DISTURBF_Pos        (17U)
+#define BSEC_OTPSR_DISTURBF_Msk        (0x1UL << BSEC_OTPSR_DISTURBF_Pos)           /*!< 0x00020000 */
+#define BSEC_OTPSR_DISTURBF            BSEC_OTPSR_DISTURBF_Msk                     /*!< Disturb flag */
+#define BSEC_OTPSR_DEDF_Pos            (18U)
+#define BSEC_OTPSR_DEDF_Msk            (0x1UL << BSEC_OTPSR_DEDF_Pos)               /*!< 0x00040000 */
+#define BSEC_OTPSR_DEDF                BSEC_OTPSR_DEDF_Msk                         /*!< Double error detection flag */
+#define BSEC_OTPSR_SECF_Pos            (19U)
+#define BSEC_OTPSR_SECF_Msk            (0x1UL << BSEC_OTPSR_SECF_Pos)               /*!< 0x00080000 */
+#define BSEC_OTPSR_SECF                BSEC_OTPSR_SECF_Msk                         /*!< Single error correction flag */
+#define BSEC_OTPSR_PPLF_Pos            (20U)
+#define BSEC_OTPSR_PPLF_Msk            (0x1UL << BSEC_OTPSR_PPLF_Pos)               /*!< 0x00100000 */
+#define BSEC_OTPSR_PPLF                BSEC_OTPSR_PPLF_Msk                         /*!< Permanent programming lock flag */
+#define BSEC_OTPSR_PPLMF_Pos           (21U)
+#define BSEC_OTPSR_PPLMF_Msk           (0x1UL << BSEC_OTPSR_PPLMF_Pos)              /*!< 0x00200000 */
+#define BSEC_OTPSR_PPLMF               BSEC_OTPSR_PPLMF_Msk                        /*!< Permanent programming lock mismatch flag */
+#define BSEC_OTPSR_AMEF_Pos            (22U)
+#define BSEC_OTPSR_AMEF_Msk            (0x1UL << BSEC_OTPSR_AMEF_Pos)               /*!< 0x00400000 */
+#define BSEC_OTPSR_AMEF                BSEC_OTPSR_AMEF_Msk                         /*!< Addresses mismatch error flag */
+
+/*****************  Bit definition for BSEC_EPOCHRx register  *****************/
+#define BSEC_EPOCHRx_EPOCH_Pos         (0U)
+#define BSEC_EPOCHRx_EPOCH_Msk         (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos)     /*!< 0xFFFFFFFF */
+#define BSEC_EPOCHRx_EPOCH             BSEC_EPOCHRx_EPOCH_Msk                      /*!< Epoch */
+
+/****************  Bit definition for BSEC_EPOCHSELR register  ****************/
+#define BSEC_EPOCHSELR_EPSEL_Pos       (0U)
+#define BSEC_EPOCHSELR_EPSEL_Msk       (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos)          /*!< 0x00000001 */
+#define BSEC_EPOCHSELR_EPSEL           BSEC_EPOCHSELR_EPSEL_Msk                    /*!< Epoch selection */
+
+/******************  Bit definition for BSEC_DBGCR register  ******************/
+#define BSEC_DBGCR_UNLOCK_Pos          (8U)
+#define BSEC_DBGCR_UNLOCK_Msk          (0xFFUL << BSEC_DBGCR_UNLOCK_Pos)            /*!< 0x0000FF00 */
+#define BSEC_DBGCR_UNLOCK              BSEC_DBGCR_UNLOCK_Msk                       /*!< Non-secure debug authorization */
+#define BSEC_DBGCR_AUTH_HDPL_Pos       (16U)
+#define BSEC_DBGCR_AUTH_HDPL_Msk       (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos)         /*!< 0x00FF0000 */
+#define BSEC_DBGCR_AUTH_HDPL           BSEC_DBGCR_AUTH_HDPL_Msk                    /*!< Level at which debug may be opened */
+#define BSEC_DBGCR_AUTH_SEC_Pos        (24U)
+#define BSEC_DBGCR_AUTH_SEC_Msk        (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos)          /*!< 0xFF000000 */
+#define BSEC_DBGCR_AUTH_SEC            BSEC_DBGCR_AUTH_SEC_Msk                     /*!< Secure debug authorization */
+
+/***************  Bit definition for BSEC_AP_UNLOCK register  *****************/
+#define BSEC_AP_UNLOCK_UNLOCK_Pos      (0U)
+#define BSEC_AP_UNLOCK_UNLOCK_Msk      (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos)        /*!< 0x000000FF */
+#define BSEC_AP_UNLOCK_UNLOCK          BSEC_AP_UNLOCK_UNLOCK_Msk                   /*!< Unlock DBG_MCU AP interface */
+
+/*****************  Bit definition for BSEC_HDPLSR register  ******************/
+#define BSEC_HDPLSR_HDPL_Pos           (0U)
+#define BSEC_HDPLSR_HDPL_Msk           (0xFFUL << BSEC_HDPLSR_HDPL_Pos)             /*!< 0x000000FF */
+#define BSEC_HDPLSR_HDPL               BSEC_HDPLSR_HDPL_Msk                        /*!< Current HDPL */
+
+/*****************  Bit definition for BSEC_HDPLCR register  ******************/
+#define BSEC_HDPLCR_INCR_HDPL_Pos      (0U)
+#define BSEC_HDPLCR_INCR_HDPL_Msk      (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos)  /*!< 0xFFFFFFFF */
+#define BSEC_HDPLCR_INCR_HDPL          BSEC_HDPLCR_INCR_HDPL_Msk                   /*!< Increment HDPL */
+
+/*****************  Bit definition for BSEC_NEXTLR register  ******************/
+#define BSEC_NEXTLR_INCR_Pos           (0U)
+#define BSEC_NEXTLR_INCR_Msk           (0x3UL << BSEC_NEXTLR_INCR_Pos)              /*!< 0x00000003 */
+#define BSEC_NEXTLR_INCR               BSEC_NEXTLR_INCR_Msk                        /*!< Increment */
+
+/*****************  Bit definition for BSEC_WOSCRx register  ******************/
+#define BSEC_WOSCRx_WOSDATA_Pos        (0U)
+#define BSEC_WOSCRx_WOSDATA_Msk        (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos)    /*!< 0xFFFFFFFF */
+#define BSEC_WOSCRx_WOSDATA            BSEC_WOSCRx_WOSDATA_Msk                     /*!< Write once scratch data */
+
+/******************  Bit definition for BSEC_HRCR register  *******************/
+#define BSEC_HRCR_HRC_Pos              (0U)
+#define BSEC_HRCR_HRC_Msk              (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_HRCR_HRC                  BSEC_HRCR_HRC_Msk                           /*!< Hot reset counter */
+
+/******************  Bit definition for BSEC_WRCR register  *******************/
+#define BSEC_WRCR_WRC_Pos              (0U)
+#define BSEC_WRCR_WRC_Msk              (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_WRCR_WRC                  BSEC_WRCR_WRC_Msk                           /*!< Warm reset counter */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos              (0U)
+#define CRC_DR_DR_Msk              (0xFFFFFFFFUL << CRC_DR_DR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                  CRC_DR_DR_Msk                               /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos            (0U)
+#define CRC_IDR_IDR_Msk            (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR                CRC_IDR_IDR_Msk                             /*!< General-purpose 32-bits data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos           (0U)
+#define CRC_CR_RESET_Msk           (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
+#define CRC_CR_RESET               CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos        (3U)
+#define CRC_CR_POLYSIZE_Msk        (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE            CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0          (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1          (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos          (5U)
+#define CRC_CR_REV_IN_Msk          (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
+#define CRC_CR_REV_IN              CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0            (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1            (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos         (7U)
+#define CRC_CR_REV_OUT_Msk         (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
+#define CRC_CR_REV_OUT             CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
+#define CRC_CR_REV_OUT_0           (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
+#define CRC_CR_REV_OUT_1           (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
+#define CRC_CR_RTYPE_IN_Pos        (9U)
+#define CRC_CR_RTYPE_IN_Msk        (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
+#define CRC_CR_RTYPE_IN            CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
+#define CRC_CR_RTYPE_OUT_Pos       (10U)
+#define CRC_CR_RTYPE_OUT_Msk       (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
+#define CRC_CR_RTYPE_OUT           CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos          (0U)
+#define CRC_INIT_INIT_Msk          (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)         /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT              CRC_INIT_INIT_Msk                           /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos            (0U)
+#define CRC_POL_POL_Msk            (0xFFFFFFFFUL << CRC_POL_POL_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_POL_POL                CRC_POL_POL_Msk                             /*!< Coefficients of the polynomial */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Cryp Processor                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register  ********************/
+#define CRYP_CR_ALGODIR_Pos              (2U)
+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)           /*!< 0x00000004 */
+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk                      /*!< Algorithm direction (Encrypt/Decrypt) */
+
+#define CRYP_CR_ALGOMODE_Pos             (3U)
+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080038 */
+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk                     /*!< Algorithm mode */
+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_3               (0x10000UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080000 */
+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)  /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)  /*!< 0x00000028 */
+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)  /*!< 0x00000030 */
+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)  /*!< 0x00000038 */
+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)
+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)  /*!< 0x00080000 */
+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk
+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)
+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk
+
+#define CRYP_CR_DATATYPE_Pos             (6U)
+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x000000C0 */
+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk                     /*!< Data Type selection */
+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000040 */
+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000080 */
+#define CRYP_CR_KEYSIZE_Pos              (8U)
+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000300 */
+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk                      /*!< Key Size selection */
+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000100 */
+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000200 */
+#define CRYP_CR_FFLUSH_Pos               (14U)
+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)            /*!< 0x00004000 */
+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk                       /*!< CRYP FIFO Flush */
+#define CRYP_CR_CRYPEN_Pos               (15U)
+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)            /*!< 0x00008000 */
+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk                       /*!< CRYP processor enable */
+
+#define CRYP_CR_GCM_CCMPH_Pos            (16U)
+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00030000 */
+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk                    /*!< GCM or CCM Phase selection */
+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00010000 */
+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00020000 */
+
+#define CRYP_CR_NPBLB_Pos                (20U)
+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)             /*!< 0x00F00000 */
+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk                        /*!< Number of Padding Bytes in Last Block of payload */
+
+#define CRYP_CR_KMOD_Pos                (24U)
+#define CRYP_CR_KMOD_Msk                (0x3UL << CRYP_CR_KMOD_Pos)               /*!< 0x03000000 */
+#define CRYP_CR_KMOD                    CRYP_CR_KMOD_Msk                          /*!< Key mode selection */
+#define CRYP_CR_KMOD_0                  (0x1UL << CRYP_CR_KMOD_Pos)               /*!< 0x01000000 */
+#define CRYP_CR_KMOD_1                  (0x2UL << CRYP_CR_KMOD_Pos)               /*!< 0x02000000 */
+
+#define CRYP_CR_IPRST_Pos               (31U)
+#define CRYP_CR_IPRST_Msk               (0x1UL << CRYP_CR_IPRST_Pos)              /*!< 0x80000000 */
+#define CRYP_CR_IPRST                   CRYP_CR_IPRST_Msk                         /*!< CRYP peripheral software reset */
+
+/****************** Bits definition for CRYP_SR register  *********************/
+#define CRYP_SR_IFEM_Pos                 (0U)
+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)              /*!< 0x00000001 */
+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk                         /*!< Input FIFO empty flag */
+#define CRYP_SR_IFNF_Pos                 (1U)
+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)              /*!< 0x00000002 */
+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk                         /*!< Input FIFO not full flag */
+#define CRYP_SR_OFNE_Pos                 (2U)
+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)              /*!< 0x00000004 */
+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk                         /*!< Output FIFO not empty flag */
+#define CRYP_SR_OFFU_Pos                 (3U)
+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)              /*!< 0x00000008 */
+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk                         /*!< Output FIFO full flag */
+#define CRYP_SR_BUSY_Pos                 (4U)
+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)              /*!< 0x00000010 */
+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk                         /*!< Busy bit */
+#define CRYP_SR_KERF_Pos                 (6U)
+#define CRYP_SR_KERF_Msk                 (0x1UL << CRYP_SR_KERF_Pos)              /*!< 0x00000040 */
+#define CRYP_SR_KERF                     CRYP_SR_KERF_Msk                         /*!< Key error flag */
+#define CRYP_SR_KEYVALID_Pos             (7U)
+#define CRYP_SR_KEYVALID_Msk             (0x1UL << CRYP_SR_KEYVALID_Pos)          /*!< 0x00000080 */
+#define CRYP_SR_KEYVALID                 CRYP_SR_KEYVALID_Msk                     /*!< Key valid flag */
+
+/*******************  Bit definition for CRYP_DIN register  *******************/
+#define CRYP_DIN_DATAIN_Pos              (0U)
+#define CRYP_DIN_DATAIN_Msk              (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos)    /*!< 0xFFFFFFFF */
+#define CRYP_DIN_DATAIN                  CRYP_DIN_DATAIN_Msk                      /*!< CRYP Data Input */
+
+/*******************  Bit definition for CRYP_DIN register  *******************/
+#define CRYP_DOUT_DATAOUT_Pos            (0U)
+#define CRYP_DOUT_DATAOUT_Msk            (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos)  /*!< 0xFFFFFFFF */
+#define CRYP_DOUT_DATAOUT                CRYP_DOUT_DATAOUT_Msk                    /*!< CRYP Data Output */
+
+/****************** Bits definition for CRYP_DMACR register  ******************/
+#define CRYP_DMACR_DIEN_Pos              (0U)
+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)           /*!< 0x00000001 */
+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk                      /*!< DMA Input Enable */
+#define CRYP_DMACR_DOEN_Pos              (1U)
+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)           /*!< 0x00000002 */
+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk                      /*!< DMA Output Enable */
+
+/*****************  Bits definition for CRYP_IMSCR register  ******************/
+#define CRYP_IMSCR_INIM_Pos              (0U)
+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)           /*!< 0x00000001 */
+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk                      /*!< Input FIFO service interrupt mask */
+#define CRYP_IMSCR_OUTIM_Pos             (1U)
+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)          /*!< 0x00000002 */
+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk                     /*!< Output FIFO service interrupt mask */
+
+/****************** Bits definition for CRYP_RISR register  *******************/
+#define CRYP_RISR_INRIS_Pos              (0U)
+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)           /*!< 0x00000001 */
+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk                      /*!< Input FIFO service raw interrupt status */
+#define CRYP_RISR_OUTRIS_Pos             (1U)
+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)          /*!< 0x00000002 */
+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk                     /*!< Output FIFO service raw interrupt mask */
+
+/****************** Bits definition for CRYP_MISR register  *******************/
+#define CRYP_MISR_INMIS_Pos              (0U)
+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)           /*!< 0x00000001 */
+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk                      /*!< Input FIFO service masked interrupt status */
+#define CRYP_MISR_OUTMIS_Pos             (1U)
+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)          /*!< 0x00000002 */
+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk                     /*!< Output FIFO service masked interrupt status */
+
+/*******************  Bit definition for CRYP_K0LR register  ******************/
+#define CRYP_K0LR_K_Pos                  (0U)
+#define CRYP_K0LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K0LR_K                      CRYP_K0LR_K_Msk                          /*!< AES key bit x (x= 224 to 255) */
+
+/*******************  Bit definition for CRYP_K0RR register  ******************/
+#define CRYP_K0RR_K_Pos                  (0U)
+#define CRYP_K0RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K0RR_K                      CRYP_K0RR_K_Msk                          /*!< AES key bit x (x= 192 to 223) */
+
+/*******************  Bit definition for CRYP_IV1LR register  ******************/
+#define CRYP_IV1LR_K_Pos                  (0U)
+#define CRYP_IV1LR_K_Msk                  (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_IV1LR_K                      CRYP_IV1LR_K_Msk                          /*!< AES key bit x (x= 160 to 291) */
+
+/*******************  Bit definition for CRYP_IV1RR register  ******************/
+#define CRYP_IV1RR_K_Pos                  (0U)
+#define CRYP_IV1RR_K_Msk                  (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_IV1RR_K                      CRYP_IV1RR_K_Msk                          /*!< AES key bit x (x= 128 to 159) */
+
+/*******************  Bit definition for CRYP_K2LR register  ******************/
+#define CRYP_K2LR_K_Pos                  (0U)
+#define CRYP_K2LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K2LR_K                      CRYP_K2LR_K_Msk                          /*!< AES key bit x (x= 96 to 127) */
+
+/*******************  Bit definition for CRYP_K2RR register  ******************/
+#define CRYP_K2RR_K_Pos                  (0U)
+#define CRYP_K2RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K2RR_K                      CRYP_K2RR_K_Msk                          /*!< AES key bit x (x= 64 to 95) */
+
+/*******************  Bit definition for CRYP_K3LR register  ******************/
+#define CRYP_K3LR_K_Pos                  (0U)
+#define CRYP_K3LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K3LR_K                      CRYP_K3LR_K_Msk                          /*!< AES key bit x (x= 32 to 63) */
+
+/*******************  Bit definition for CRYP_K3RR register  ******************/
+#define CRYP_K3RR_K_Pos                  (0U)
+#define CRYP_K3RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K3RR_K                      CRYP_K3RR_K_Msk                          /*!< AES key bit x (x= 0 to 31) */
+
+/*******************  Bit definition for CRYP_IV0LR register  ******************/
+#define CRYP_IV0LR_IV_Pos                (0U)
+#define CRYP_IV0LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV0LR_IV                    CRYP_IV0LR_IV_Msk                        /*!< Initialization vector bit x (x= 0 to 31) */
+
+/*******************  Bit definition for CRYP_IV0RR register  ******************/
+#define CRYP_IV0RR_IV_Pos                (0U)
+#define CRYP_IV0RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV0RR_IV                    CRYP_IV0RR_IV_Msk                        /*!< Initialization vector bit x (x= 32 to 63) */
+
+/*******************  Bit definition for CRYP_IV1LR register  ******************/
+#define CRYP_IV1LR_IV_Pos                (0U)
+#define CRYP_IV1LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV1LR_IV                    CRYP_IV1LR_IV_Msk                        /*!< Initialization vector bit x (x= 64 to 95) */
+
+/*******************  Bit definition for CRYP_IV1RR register  ******************/
+#define CRYP_IV1RR_IV_Pos                (0U)
+#define CRYP_IV1RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV1RR_IV                    CRYP_IV1RR_IV_Msk                        /*!< Initialization vector bit x (x= 96 to 127) */
+
+/*******************  Bit definition for CRYP_CSGCMCCM0R register  ******************/
+#define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos          (0U)
+#define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM0R_CSGCMCCM0              CRYP_CSGCMCCM0R_CSGCMCCM0_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM1R register  ******************/
+#define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos          (0U)
+#define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM1R_CSGCMCCM1              CRYP_CSGCMCCM1R_CSGCMCCM1_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM2R register  ******************/
+#define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos          (0U)
+#define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM2R_CSGCMCCM2              CRYP_CSGCMCCM2R_CSGCMCCM2_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM3R register  ******************/
+#define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos          (0U)
+#define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM3R_CSGCMCCM3              CRYP_CSGCMCCM3R_CSGCMCCM3_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM4R register  ******************/
+#define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos          (0U)
+#define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM4R_CSGCMCCM4              CRYP_CSGCMCCM4R_CSGCMCCM4_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM5R register  ******************/
+#define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos          (0U)
+#define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM5R_CSGCMCCM5              CRYP_CSGCMCCM5R_CSGCMCCM5_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM6R register  ******************/
+#define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos          (0U)
+#define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM6R_CSGCMCCM6              CRYP_CSGCMCCM6R_CSGCMCCM6_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM7R register  ******************/
+#define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos          (0U)
+#define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM7R_CSGCMCCM7              CRYP_CSGCMCCM7R_CSGCMCCM7_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCM0R register  ******************/
+#define CRYP_CSGCM0R_CSGCM0_Pos          (0U)
+#define CRYP_CSGCM0R_CSGCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM0R_CSGCM0              CRYP_CSGCM0R_CSGCM0_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM1R register  ******************/
+#define CRYP_CSGCM1R_CSGCM1_Pos          (0U)
+#define CRYP_CSGCM1R_CSGCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM1R_CSGCM1              CRYP_CSGCM1R_CSGCM1_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM2R register  ******************/
+#define CRYP_CSGCM2R_CSGCM2_Pos          (0U)
+#define CRYP_CSGCM2R_CSGCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM2R_CSGCM2              CRYP_CSGCM2R_CSGCM2_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM3R register  ******************/
+#define CRYP_CSGCM3R_CSGCM3_Pos          (0U)
+#define CRYP_CSGCM3R_CSGCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM3R_CSGCM3              CRYP_CSGCM3R_CSGCM3_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM4R register  ******************/
+#define CRYP_CSGCM4R_CSGCM4_Pos          (0U)
+#define CRYP_CSGCM4R_CSGCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM4R_CSGCM4              CRYP_CSGCM4R_CSGCM4_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM5R register  ******************/
+#define CRYP_CSGCM5R_CSGCM5_Pos          (0U)
+#define CRYP_CSGCM5R_CSGCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM5R_CSGCM5              CRYP_CSGCM5R_CSGCM5_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM6R register  ******************/
+#define CRYP_CSGCM6R_CSGCM6_Pos          (0U)
+#define CRYP_CSGCM6R_CSGCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM6R_CSGCM6              CRYP_CSGCM6R_CSGCM6_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM7R register  ******************/
+#define CRYP_CSGCM7R_CSGCM7_Pos          (0U)
+#define CRYP_CSGCM7R_CSGCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM7R_CSGCM7              CRYP_CSGCM7R_CSGCM7_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (CSI)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CSI_CR register  ********************/
+#define CSI_CR_CSIEN_Pos                (0U)
+#define CSI_CR_CSIEN_Msk                (0x1UL << CSI_CR_CSIEN_Pos)               /*!< 0x00000001 */
+#define CSI_CR_CSIEN                    CSI_CR_CSIEN_Msk                         /*!< CSI-2 enable */
+#define CSI_CR_VC0START_Pos             (2U)
+#define CSI_CR_VC0START_Msk             (0x1UL << CSI_CR_VC0START_Pos)            /*!< 0x00000004 */
+#define CSI_CR_VC0START                 CSI_CR_VC0START_Msk                      /*!< Virtual channel 0 start */
+#define CSI_CR_VC0STOP_Pos              (3U)
+#define CSI_CR_VC0STOP_Msk              (0x1UL << CSI_CR_VC0STOP_Pos)             /*!< 0x00000008 */
+#define CSI_CR_VC0STOP                  CSI_CR_VC0STOP_Msk                       /*!< Virtual channel 0 stop */
+#define CSI_CR_VC1START_Pos             (6U)
+#define CSI_CR_VC1START_Msk             (0x1UL << CSI_CR_VC1START_Pos)            /*!< 0x00000040 */
+#define CSI_CR_VC1START                 CSI_CR_VC1START_Msk                      /*!< Virtual channel 1 start */
+#define CSI_CR_VC1STOP_Pos              (7U)
+#define CSI_CR_VC1STOP_Msk              (0x1UL << CSI_CR_VC1STOP_Pos)             /*!< 0x00000080 */
+#define CSI_CR_VC1STOP                  CSI_CR_VC1STOP_Msk                       /*!< Virtual channel 1 stop */
+#define CSI_CR_VC2START_Pos             (10U)
+#define CSI_CR_VC2START_Msk             (0x1UL << CSI_CR_VC2START_Pos)            /*!< 0x00000400 */
+#define CSI_CR_VC2START                 CSI_CR_VC2START_Msk                      /*!< Virtual channel 2 start */
+#define CSI_CR_VC2STOP_Pos              (11U)
+#define CSI_CR_VC2STOP_Msk              (0x1UL << CSI_CR_VC2STOP_Pos)             /*!< 0x00000800 */
+#define CSI_CR_VC2STOP                  CSI_CR_VC2STOP_Msk                       /*!< Virtual channel 2 stop */
+#define CSI_CR_VC3START_Pos             (14U)
+#define CSI_CR_VC3START_Msk             (0x1UL << CSI_CR_VC3START_Pos)            /*!< 0x00004000 */
+#define CSI_CR_VC3START                 CSI_CR_VC3START_Msk                      /*!< Virtual channel 3 start */
+#define CSI_CR_VC3STOP_Pos              (15U)
+#define CSI_CR_VC3STOP_Msk              (0x1UL << CSI_CR_VC3STOP_Pos)             /*!< 0x00008000 */
+#define CSI_CR_VC3STOP                  CSI_CR_VC3STOP_Msk                       /*!< Virtual channel 3 stop */
+
+/*******************  Bit definition for CSI_PCR register  ********************/
+#define CSI_PCR_PWRDOWN_Pos             (0U)
+#define CSI_PCR_PWRDOWN_Msk             (0x1UL << CSI_PCR_PWRDOWN_Pos)            /*!< 0x00000001 */
+#define CSI_PCR_PWRDOWN                 CSI_PCR_PWRDOWN_Msk                      /*!< Virtual channel 3 start */
+#define CSI_PCR_CLEN_Pos                (1U)
+#define CSI_PCR_CLEN_Msk                (0x1UL << CSI_PCR_CLEN_Pos)               /*!< 0x00000002 */
+#define CSI_PCR_CLEN                    CSI_PCR_CLEN_Msk                         /*!< Clock lane enable */
+#define CSI_PCR_DL0EN_Pos               (2U)
+#define CSI_PCR_DL0EN_Msk               (0x1UL << CSI_PCR_DL0EN_Pos)              /*!< 0x00000004 */
+#define CSI_PCR_DL0EN                   CSI_PCR_DL0EN_Msk                        /*!< D-PHY_RX data lane 0 enable */
+#define CSI_PCR_DL1EN_Pos               (3U)
+#define CSI_PCR_DL1EN_Msk               (0x1UL << CSI_PCR_DL1EN_Pos)              /*!< 0x00000008 */
+#define CSI_PCR_DL1EN                   CSI_PCR_DL1EN_Msk                        /*!< D-PHY_RX data lane 1 enable */
+
+/*****************  Bit definition for CSI_VC0CFGR1 register  *****************/
+#define CSI_VC0CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC0CFGR1_ALLDT_Msk          (0x1UL << CSI_VC0CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC0CFGR1_ALLDT              CSI_VC0CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC0CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC0CFGR1_DT0EN_Msk          (0x1UL << CSI_VC0CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC0CFGR1_DT0EN              CSI_VC0CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC0CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC0CFGR1_DT1EN_Msk          (0x1UL << CSI_VC0CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC0CFGR1_DT1EN              CSI_VC0CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC0CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC0CFGR1_DT2EN_Msk          (0x1UL << CSI_VC0CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC0CFGR1_DT2EN              CSI_VC0CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC0CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC0CFGR1_DT3EN_Msk          (0x1UL << CSI_VC0CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC0CFGR1_DT3EN              CSI_VC0CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC0CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC0CFGR1_DT4EN_Msk          (0x1UL << CSI_VC0CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC0CFGR1_DT4EN              CSI_VC0CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC0CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC0CFGR1_DT5EN_Msk          (0x1UL << CSI_VC0CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC0CFGR1_DT5EN              CSI_VC0CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC0CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC0CFGR1_DT6EN_Msk          (0x1UL << CSI_VC0CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC0CFGR1_DT6EN              CSI_VC0CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC0CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC0CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR1_CDTFT              CSI_VC0CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC0CFGR1_DT0_Pos            (16U)
+#define CSI_VC0CFGR1_DT0_Msk            (0x3FUL << CSI_VC0CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR1_DT0                CSI_VC0CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC0CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC0CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR1_DT0FT              CSI_VC0CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC0CFGR2 register  *****************/
+#define CSI_VC0CFGR2_DT1_Pos            (0U)
+#define CSI_VC0CFGR2_DT1_Msk            (0x3FUL << CSI_VC0CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR2_DT1                CSI_VC0CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC0CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR2_DT1FT              CSI_VC0CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC0CFGR2_DT2_Pos            (16U)
+#define CSI_VC0CFGR2_DT2_Msk            (0x3FUL << CSI_VC0CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR2_DT2                CSI_VC0CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC0CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR2_DT2FT              CSI_VC0CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC0CFGR3 register  *****************/
+#define CSI_VC0CFGR3_DT3_Pos            (0U)
+#define CSI_VC0CFGR3_DT3_Msk            (0x3FUL << CSI_VC0CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR3_DT3                CSI_VC0CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC0CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR3_DT3FT              CSI_VC0CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC0CFGR3_DT4_Pos            (16U)
+#define CSI_VC0CFGR3_DT4_Msk            (0x3FUL << CSI_VC0CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR3_DT4                CSI_VC0CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC0CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR3_DT4FT              CSI_VC0CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC0CFGR4 register  *****************/
+#define CSI_VC0CFGR4_DT5_Pos            (0U)
+#define CSI_VC0CFGR4_DT5_Msk            (0x3FUL << CSI_VC0CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR4_DT5                CSI_VC0CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC0CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR4_DT5FT              CSI_VC0CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC0CFGR4_DT6_Pos            (16U)
+#define CSI_VC0CFGR4_DT6_Msk            (0x3FUL << CSI_VC0CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR4_DT6                CSI_VC0CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC0CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR4_DT6FT              CSI_VC0CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC1CFGR1 register  *****************/
+#define CSI_VC1CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC1CFGR1_ALLDT_Msk          (0x1UL << CSI_VC1CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC1CFGR1_ALLDT              CSI_VC1CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC1CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC1CFGR1_DT0EN_Msk          (0x1UL << CSI_VC1CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC1CFGR1_DT0EN              CSI_VC1CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC1CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC1CFGR1_DT1EN_Msk          (0x1UL << CSI_VC1CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC1CFGR1_DT1EN              CSI_VC1CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC1CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC1CFGR1_DT2EN_Msk          (0x1UL << CSI_VC1CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC1CFGR1_DT2EN              CSI_VC1CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC1CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC1CFGR1_DT3EN_Msk          (0x1UL << CSI_VC1CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC1CFGR1_DT3EN              CSI_VC1CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC1CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC1CFGR1_DT4EN_Msk          (0x1UL << CSI_VC1CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC1CFGR1_DT4EN              CSI_VC1CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC1CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC1CFGR1_DT5EN_Msk          (0x1UL << CSI_VC1CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC1CFGR1_DT5EN              CSI_VC1CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC1CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC1CFGR1_DT6EN_Msk          (0x1UL << CSI_VC1CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC1CFGR1_DT6EN              CSI_VC1CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC1CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC1CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR1_CDTFT              CSI_VC1CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC1CFGR1_DT0_Pos            (16U)
+#define CSI_VC1CFGR1_DT0_Msk            (0x3FUL << CSI_VC1CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR1_DT0                CSI_VC1CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC1CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC1CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR1_DT0FT              CSI_VC1CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC1CFGR2 register  *****************/
+#define CSI_VC1CFGR2_DT1_Pos            (0U)
+#define CSI_VC1CFGR2_DT1_Msk            (0x3FUL << CSI_VC1CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR2_DT1                CSI_VC1CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC1CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR2_DT1FT              CSI_VC1CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC1CFGR2_DT2_Pos            (16U)
+#define CSI_VC1CFGR2_DT2_Msk            (0x3FUL << CSI_VC1CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR2_DT2                CSI_VC1CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC1CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR2_DT2FT              CSI_VC1CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC1CFGR3 register  *****************/
+#define CSI_VC1CFGR3_DT3_Pos            (0U)
+#define CSI_VC1CFGR3_DT3_Msk            (0x3FUL << CSI_VC1CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR3_DT3                CSI_VC1CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC1CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR3_DT3FT              CSI_VC1CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC1CFGR3_DT4_Pos            (16U)
+#define CSI_VC1CFGR3_DT4_Msk            (0x3FUL << CSI_VC1CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR3_DT4                CSI_VC1CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC1CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR3_DT4FT              CSI_VC1CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC1CFGR4 register  *****************/
+#define CSI_VC1CFGR4_DT5_Pos            (0U)
+#define CSI_VC1CFGR4_DT5_Msk            (0x3FUL << CSI_VC1CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR4_DT5                CSI_VC1CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC1CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR4_DT5FT              CSI_VC1CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC1CFGR4_DT6_Pos            (16U)
+#define CSI_VC1CFGR4_DT6_Msk            (0x3FUL << CSI_VC1CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR4_DT6                CSI_VC1CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC1CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR4_DT6FT              CSI_VC1CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC2CFGR1 register  *****************/
+#define CSI_VC2CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC2CFGR1_ALLDT_Msk          (0x1UL << CSI_VC2CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC2CFGR1_ALLDT              CSI_VC2CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC2CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC2CFGR1_DT0EN_Msk          (0x1UL << CSI_VC2CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC2CFGR1_DT0EN              CSI_VC2CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC2CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC2CFGR1_DT1EN_Msk          (0x1UL << CSI_VC2CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC2CFGR1_DT1EN              CSI_VC2CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC2CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC2CFGR1_DT2EN_Msk          (0x1UL << CSI_VC2CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC2CFGR1_DT2EN              CSI_VC2CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC2CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC2CFGR1_DT3EN_Msk          (0x1UL << CSI_VC2CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC2CFGR1_DT3EN              CSI_VC2CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC2CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC2CFGR1_DT4EN_Msk          (0x1UL << CSI_VC2CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC2CFGR1_DT4EN              CSI_VC2CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC2CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC2CFGR1_DT5EN_Msk          (0x1UL << CSI_VC2CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC2CFGR1_DT5EN              CSI_VC2CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC2CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC2CFGR1_DT6EN_Msk          (0x1UL << CSI_VC2CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC2CFGR1_DT6EN              CSI_VC2CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC2CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC2CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR1_CDTFT              CSI_VC2CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC2CFGR1_DT0_Pos            (16U)
+#define CSI_VC2CFGR1_DT0_Msk            (0x3FUL << CSI_VC2CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR1_DT0                CSI_VC2CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC2CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC2CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR1_DT0FT              CSI_VC2CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC2CFGR2 register  *****************/
+#define CSI_VC2CFGR2_DT1_Pos            (0U)
+#define CSI_VC2CFGR2_DT1_Msk            (0x3FUL << CSI_VC2CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR2_DT1                CSI_VC2CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC2CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR2_DT1FT              CSI_VC2CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC2CFGR2_DT2_Pos            (16U)
+#define CSI_VC2CFGR2_DT2_Msk            (0x3FUL << CSI_VC2CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR2_DT2                CSI_VC2CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC2CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR2_DT2FT              CSI_VC2CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC2CFGR3 register  *****************/
+#define CSI_VC2CFGR3_DT3_Pos            (0U)
+#define CSI_VC2CFGR3_DT3_Msk            (0x3FUL << CSI_VC2CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR3_DT3                CSI_VC2CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC2CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR3_DT3FT              CSI_VC2CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC2CFGR3_DT4_Pos            (16U)
+#define CSI_VC2CFGR3_DT4_Msk            (0x3FUL << CSI_VC2CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR3_DT4                CSI_VC2CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC2CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR3_DT4FT              CSI_VC2CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC2CFGR4 register  *****************/
+#define CSI_VC2CFGR4_DT5_Pos            (0U)
+#define CSI_VC2CFGR4_DT5_Msk            (0x3FUL << CSI_VC2CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR4_DT5                CSI_VC2CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC2CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR4_DT5FT              CSI_VC2CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC2CFGR4_DT6_Pos            (16U)
+#define CSI_VC2CFGR4_DT6_Msk            (0x3FUL << CSI_VC2CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR4_DT6                CSI_VC2CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC2CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR4_DT6FT              CSI_VC2CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC3CFGR1 register  *****************/
+#define CSI_VC3CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC3CFGR1_ALLDT_Msk          (0x1UL << CSI_VC3CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC3CFGR1_ALLDT              CSI_VC3CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC3CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC3CFGR1_DT0EN_Msk          (0x1UL << CSI_VC3CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC3CFGR1_DT0EN              CSI_VC3CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC3CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC3CFGR1_DT1EN_Msk          (0x1UL << CSI_VC3CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC3CFGR1_DT1EN              CSI_VC3CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC3CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC3CFGR1_DT2EN_Msk          (0x1UL << CSI_VC3CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC3CFGR1_DT2EN              CSI_VC3CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC3CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC3CFGR1_DT3EN_Msk          (0x1UL << CSI_VC3CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC3CFGR1_DT3EN              CSI_VC3CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC3CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC3CFGR1_DT4EN_Msk          (0x1UL << CSI_VC3CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC3CFGR1_DT4EN              CSI_VC3CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC3CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC3CFGR1_DT5EN_Msk          (0x1UL << CSI_VC3CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC3CFGR1_DT5EN              CSI_VC3CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC3CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC3CFGR1_DT6EN_Msk          (0x1UL << CSI_VC3CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC3CFGR1_DT6EN              CSI_VC3CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC3CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC3CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR1_CDTFT              CSI_VC3CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC3CFGR1_DT0_Pos            (16U)
+#define CSI_VC3CFGR1_DT0_Msk            (0x3FUL << CSI_VC3CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR1_DT0                CSI_VC3CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC3CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC3CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR1_DT0FT              CSI_VC3CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC3CFGR2 register  *****************/
+#define CSI_VC3CFGR2_DT1_Pos            (0U)
+#define CSI_VC3CFGR2_DT1_Msk            (0x3FUL << CSI_VC3CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR2_DT1                CSI_VC3CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC3CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR2_DT1FT              CSI_VC3CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC3CFGR2_DT2_Pos            (16U)
+#define CSI_VC3CFGR2_DT2_Msk            (0x3FUL << CSI_VC3CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR2_DT2                CSI_VC3CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC3CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR2_DT2FT              CSI_VC3CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC3CFGR3 register  *****************/
+#define CSI_VC3CFGR3_DT3_Pos            (0U)
+#define CSI_VC3CFGR3_DT3_Msk            (0x3FUL << CSI_VC3CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR3_DT3                CSI_VC3CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC3CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR3_DT3FT              CSI_VC3CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC3CFGR3_DT4_Pos            (16U)
+#define CSI_VC3CFGR3_DT4_Msk            (0x3FUL << CSI_VC3CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR3_DT4                CSI_VC3CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC3CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR3_DT4FT              CSI_VC3CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC3CFGR4 register  *****************/
+#define CSI_VC3CFGR4_DT5_Pos            (0U)
+#define CSI_VC3CFGR4_DT5_Msk            (0x3FUL << CSI_VC3CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR4_DT5                CSI_VC3CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC3CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR4_DT5FT              CSI_VC3CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC3CFGR4_DT6_Pos            (16U)
+#define CSI_VC3CFGR4_DT6_Msk            (0x3FUL << CSI_VC3CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR4_DT6                CSI_VC3CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC3CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR4_DT6FT              CSI_VC3CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_LB0CFGR register  ******************/
+#define CSI_LB0CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB0CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB0CFGR_BYTECNT             CSI_LB0CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB0CFGR_LINECNT_Pos         (16U)
+#define CSI_LB0CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB0CFGR_LINECNT             CSI_LB0CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB1CFGR register  ******************/
+#define CSI_LB1CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB1CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB1CFGR_BYTECNT             CSI_LB1CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB1CFGR_LINECNT_Pos         (16U)
+#define CSI_LB1CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB1CFGR_LINECNT             CSI_LB1CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB2CFGR register  ******************/
+#define CSI_LB2CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB2CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB2CFGR_BYTECNT             CSI_LB2CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB2CFGR_LINECNT_Pos         (16U)
+#define CSI_LB2CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB2CFGR_LINECNT             CSI_LB2CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB3CFGR register  ******************/
+#define CSI_LB3CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB3CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB3CFGR_BYTECNT             CSI_LB3CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB3CFGR_LINECNT_Pos         (16U)
+#define CSI_LB3CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB3CFGR_LINECNT             CSI_LB3CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_TIM0CFGR register  *****************/
+#define CSI_TIM0CFGR_COUNT_Pos          (0U)
+#define CSI_TIM0CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM0CFGR_COUNT              CSI_TIM0CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM1CFGR register  *****************/
+#define CSI_TIM1CFGR_COUNT_Pos          (0U)
+#define CSI_TIM1CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM1CFGR_COUNT              CSI_TIM1CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM2CFGR register  *****************/
+#define CSI_TIM2CFGR_COUNT_Pos          (0U)
+#define CSI_TIM2CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM2CFGR_COUNT              CSI_TIM2CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM3CFGR register  *****************/
+#define CSI_TIM3CFGR_COUNT_Pos          (0U)
+#define CSI_TIM3CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM3CFGR_COUNT              CSI_TIM3CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/******************  Bit definition for CSI_LMCFGR register  ******************/
+#define CSI_LMCFGR_LANENB_Pos           (8U)
+#define CSI_LMCFGR_LANENB_Msk           (0x7UL << CSI_LMCFGR_LANENB_Pos)          /*!< 0x00000700 */
+#define CSI_LMCFGR_LANENB               CSI_LMCFGR_LANENB_Msk                    /*!< Number of lanes */
+#define CSI_LMCFGR_DL0MAP_Pos           (16U)
+#define CSI_LMCFGR_DL0MAP_Msk           (0x7UL << CSI_LMCFGR_DL0MAP_Pos)          /*!< 0x00070000 */
+#define CSI_LMCFGR_DL0MAP               CSI_LMCFGR_DL0MAP_Msk                    /*!< Physical mapping of logical data lane 0 */
+#define CSI_LMCFGR_DL1MAP_Pos           (20U)
+#define CSI_LMCFGR_DL1MAP_Msk           (0x7UL << CSI_LMCFGR_DL1MAP_Pos)          /*!< 0x00700000 */
+#define CSI_LMCFGR_DL1MAP               CSI_LMCFGR_DL1MAP_Msk                    /*!< Physical mapping of logical data lane 1 */
+
+/******************  Bit definition for CSI_PRGITR register  ******************/
+#define CSI_PRGITR_LB0VC_Pos            (0U)
+#define CSI_PRGITR_LB0VC_Msk            (0x3UL << CSI_PRGITR_LB0VC_Pos)           /*!< 0x00000003 */
+#define CSI_PRGITR_LB0VC                CSI_PRGITR_LB0VC_Msk                     /*!< Line/Byte counter 0 linked to a virtual channel */
+#define CSI_PRGITR_LB0EN_Pos            (3U)
+#define CSI_PRGITR_LB0EN_Msk            (0x1UL << CSI_PRGITR_LB0EN_Pos)           /*!< 0x00000008 */
+#define CSI_PRGITR_LB0EN                CSI_PRGITR_LB0EN_Msk                     /*!< Line/Byte 0counter enable */
+#define CSI_PRGITR_LB1VC_Pos            (4U)
+#define CSI_PRGITR_LB1VC_Msk            (0x3UL << CSI_PRGITR_LB1VC_Pos)           /*!< 0x00000030 */
+#define CSI_PRGITR_LB1VC                CSI_PRGITR_LB1VC_Msk                     /*!< Line/Byte counter 1 linked to a virtual channel */
+#define CSI_PRGITR_LB1EN_Pos            (7U)
+#define CSI_PRGITR_LB1EN_Msk            (0x1UL << CSI_PRGITR_LB1EN_Pos)           /*!< 0x00000080 */
+#define CSI_PRGITR_LB1EN                CSI_PRGITR_LB1EN_Msk                     /*!< Line/Byte 1 counter enable */
+#define CSI_PRGITR_LB2VC_Pos            (8U)
+#define CSI_PRGITR_LB2VC_Msk            (0x3UL << CSI_PRGITR_LB2VC_Pos)           /*!< 0x00000300 */
+#define CSI_PRGITR_LB2VC                CSI_PRGITR_LB2VC_Msk                     /*!< Line/Byte counter 2 linked to a virtual channel */
+#define CSI_PRGITR_LB2EN_Pos            (11U)
+#define CSI_PRGITR_LB2EN_Msk            (0x1UL << CSI_PRGITR_LB2EN_Pos)           /*!< 0x00000800 */
+#define CSI_PRGITR_LB2EN                CSI_PRGITR_LB2EN_Msk                     /*!< Line/Byte 2 counter enable */
+#define CSI_PRGITR_LB3VC_Pos            (12U)
+#define CSI_PRGITR_LB3VC_Msk            (0x3UL << CSI_PRGITR_LB3VC_Pos)           /*!< 0x00003000 */
+#define CSI_PRGITR_LB3VC                CSI_PRGITR_LB3VC_Msk                     /*!< Line/Byte counter 3 linked to a virtual channel */
+#define CSI_PRGITR_LB3EN_Pos            (15U)
+#define CSI_PRGITR_LB3EN_Msk            (0x1UL << CSI_PRGITR_LB3EN_Pos)           /*!< 0x00008000 */
+#define CSI_PRGITR_LB3EN                CSI_PRGITR_LB3EN_Msk                     /*!< Line/Byte 3 counter enable */
+#define CSI_PRGITR_TIM0VC_Pos           (16U)
+#define CSI_PRGITR_TIM0VC_Msk           (0x3UL << CSI_PRGITR_TIM0VC_Pos)          /*!< 0x00030000 */
+#define CSI_PRGITR_TIM0VC               CSI_PRGITR_TIM0VC_Msk                    /*!< TIM0 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM0EOF_Pos          (18U)
+#define CSI_PRGITR_TIM0EOF_Msk          (0x1UL << CSI_PRGITR_TIM0EOF_Pos)         /*!< 0x00040000 */
+#define CSI_PRGITR_TIM0EOF              CSI_PRGITR_TIM0EOF_Msk                   /*!< TIM0 base time starting from the end of frame */
+#define CSI_PRGITR_TIM0EN_Pos           (19U)
+#define CSI_PRGITR_TIM0EN_Msk           (0x1UL << CSI_PRGITR_TIM0EN_Pos)          /*!< 0x00080000 */
+#define CSI_PRGITR_TIM0EN               CSI_PRGITR_TIM0EN_Msk                    /*!< TIM0 base time enable */
+#define CSI_PRGITR_TIM1VC_Pos           (20U)
+#define CSI_PRGITR_TIM1VC_Msk           (0x3UL << CSI_PRGITR_TIM1VC_Pos)          /*!< 0x00300000 */
+#define CSI_PRGITR_TIM1VC               CSI_PRGITR_TIM1VC_Msk                    /*!< TIM1 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM1EOF_Pos          (22U)
+#define CSI_PRGITR_TIM1EOF_Msk          (0x1UL << CSI_PRGITR_TIM1EOF_Pos)         /*!< 0x00400000 */
+#define CSI_PRGITR_TIM1EOF              CSI_PRGITR_TIM1EOF_Msk                   /*!< TIM1 base time starting from the end of frame */
+#define CSI_PRGITR_TIM1EN_Pos           (23U)
+#define CSI_PRGITR_TIM1EN_Msk           (0x1UL << CSI_PRGITR_TIM1EN_Pos)          /*!< 0x00800000 */
+#define CSI_PRGITR_TIM1EN               CSI_PRGITR_TIM1EN_Msk                    /*!< TIM1 base time enable */
+#define CSI_PRGITR_TIM2VC_Pos           (24U)
+#define CSI_PRGITR_TIM2VC_Msk           (0x3UL << CSI_PRGITR_TIM2VC_Pos)          /*!< 0x03000000 */
+#define CSI_PRGITR_TIM2VC               CSI_PRGITR_TIM2VC_Msk                    /*!< TIM2 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM2EOF_Pos          (26U)
+#define CSI_PRGITR_TIM2EOF_Msk          (0x1UL << CSI_PRGITR_TIM2EOF_Pos)         /*!< 0x04000000 */
+#define CSI_PRGITR_TIM2EOF              CSI_PRGITR_TIM2EOF_Msk                   /*!< TIM2 base time starting from the end of frame */
+#define CSI_PRGITR_TIM2EN_Pos           (27U)
+#define CSI_PRGITR_TIM2EN_Msk           (0x1UL << CSI_PRGITR_TIM2EN_Pos)          /*!< 0x08000000 */
+#define CSI_PRGITR_TIM2EN               CSI_PRGITR_TIM2EN_Msk                    /*!< TIM2 base time enable */
+#define CSI_PRGITR_TIM3VC_Pos           (28U)
+#define CSI_PRGITR_TIM3VC_Msk           (0x3UL << CSI_PRGITR_TIM3VC_Pos)          /*!< 0x30000000 */
+#define CSI_PRGITR_TIM3VC               CSI_PRGITR_TIM3VC_Msk                    /*!< TIM3 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM3EOF_Pos          (30U)
+#define CSI_PRGITR_TIM3EOF_Msk          (0x1UL << CSI_PRGITR_TIM3EOF_Pos)         /*!< 0x40000000 */
+#define CSI_PRGITR_TIM3EOF              CSI_PRGITR_TIM3EOF_Msk                   /*!< TIM3 base time starting from the end of frame */
+#define CSI_PRGITR_TIM3EN_Pos           (31U)
+#define CSI_PRGITR_TIM3EN_Msk           (0x1UL << CSI_PRGITR_TIM3EN_Pos)          /*!< 0x80000000 */
+#define CSI_PRGITR_TIM3EN               CSI_PRGITR_TIM3EN_Msk                    /*!< TIM3 base time enable */
+
+/*******************  Bit definition for CSI_WDR register  ********************/
+#define CSI_WDR_CNT_Pos                 (0U)
+#define CSI_WDR_CNT_Msk                 (0xFFFFFFFFUL << CSI_WDR_CNT_Pos)         /*!< 0xFFFFFFFF */
+#define CSI_WDR_CNT                     CSI_WDR_CNT_Msk                          /*!< Watchdog counter */
+
+/*******************  Bit definition for CSI_IER0 register  *******************/
+#define CSI_IER0_LB0IE_Pos              (0U)
+#define CSI_IER0_LB0IE_Msk              (0x1UL << CSI_IER0_LB0IE_Pos)             /*!< 0x00000001 */
+#define CSI_IER0_LB0IE                  CSI_IER0_LB0IE_Msk                       /*!< Line byte counter 0 interrupt enable */
+#define CSI_IER0_LB1IE_Pos              (1U)
+#define CSI_IER0_LB1IE_Msk              (0x1UL << CSI_IER0_LB1IE_Pos)             /*!< 0x00000002 */
+#define CSI_IER0_LB1IE                  CSI_IER0_LB1IE_Msk                       /*!< Line byte counter 1 interrupt enable */
+#define CSI_IER0_LB2IE_Pos              (2U)
+#define CSI_IER0_LB2IE_Msk              (0x1UL << CSI_IER0_LB2IE_Pos)             /*!< 0x00000004 */
+#define CSI_IER0_LB2IE                  CSI_IER0_LB2IE_Msk                       /*!< Line byte counter 2 interrupt enable */
+#define CSI_IER0_LB3IE_Pos              (3U)
+#define CSI_IER0_LB3IE_Msk              (0x1UL << CSI_IER0_LB3IE_Pos)             /*!< 0x00000008 */
+#define CSI_IER0_LB3IE                  CSI_IER0_LB3IE_Msk                       /*!< Line byte counter 3 interrupt enable */
+#define CSI_IER0_TIM0IE_Pos             (4U)
+#define CSI_IER0_TIM0IE_Msk             (0x1UL << CSI_IER0_TIM0IE_Pos)            /*!< 0x00000010 */
+#define CSI_IER0_TIM0IE                 CSI_IER0_TIM0IE_Msk                      /*!< Timer 0 interrupt enable */
+#define CSI_IER0_TIM1IE_Pos             (5U)
+#define CSI_IER0_TIM1IE_Msk             (0x1UL << CSI_IER0_TIM1IE_Pos)            /*!< 0x00000020 */
+#define CSI_IER0_TIM1IE                 CSI_IER0_TIM1IE_Msk                      /*!< Timer 1 interrupt enable */
+#define CSI_IER0_TIM2IE_Pos             (6U)
+#define CSI_IER0_TIM2IE_Msk             (0x1UL << CSI_IER0_TIM2IE_Pos)            /*!< 0x00000040 */
+#define CSI_IER0_TIM2IE                 CSI_IER0_TIM2IE_Msk                      /*!< Timer 2 interrupt enable */
+#define CSI_IER0_TIM3IE_Pos             (7U)
+#define CSI_IER0_TIM3IE_Msk             (0x1UL << CSI_IER0_TIM3IE_Pos)            /*!< 0x00000080 */
+#define CSI_IER0_TIM3IE                 CSI_IER0_TIM3IE_Msk                      /*!< Timer 3 interrupt enable */
+#define CSI_IER0_SOF0IE_Pos             (8U)
+#define CSI_IER0_SOF0IE_Msk             (0x1UL << CSI_IER0_SOF0IE_Pos)            /*!< 0x00000100 */
+#define CSI_IER0_SOF0IE                 CSI_IER0_SOF0IE_Msk                      /*!< Start of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_SOF1IE_Pos             (9U)
+#define CSI_IER0_SOF1IE_Msk             (0x1UL << CSI_IER0_SOF1IE_Pos)            /*!< 0x00000200 */
+#define CSI_IER0_SOF1IE                 CSI_IER0_SOF1IE_Msk                      /*!< Start of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_SOF2IE_Pos             (10U)
+#define CSI_IER0_SOF2IE_Msk             (0x1UL << CSI_IER0_SOF2IE_Pos)            /*!< 0x00000400 */
+#define CSI_IER0_SOF2IE                 CSI_IER0_SOF2IE_Msk                      /*!< Start of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_SOF3IE_Pos             (11U)
+#define CSI_IER0_SOF3IE_Msk             (0x1UL << CSI_IER0_SOF3IE_Pos)            /*!< 0x00000800 */
+#define CSI_IER0_SOF3IE                 CSI_IER0_SOF3IE_Msk                      /*!< Start of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_EOF0IE_Pos             (12U)
+#define CSI_IER0_EOF0IE_Msk             (0x1UL << CSI_IER0_EOF0IE_Pos)            /*!< 0x00001000 */
+#define CSI_IER0_EOF0IE                 CSI_IER0_EOF0IE_Msk                      /*!< End of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_EOF1IE_Pos             (13U)
+#define CSI_IER0_EOF1IE_Msk             (0x1UL << CSI_IER0_EOF1IE_Pos)            /*!< 0x00002000 */
+#define CSI_IER0_EOF1IE                 CSI_IER0_EOF1IE_Msk                      /*!< End of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_EOF2IE_Pos             (14U)
+#define CSI_IER0_EOF2IE_Msk             (0x1UL << CSI_IER0_EOF2IE_Pos)            /*!< 0x00004000 */
+#define CSI_IER0_EOF2IE                 CSI_IER0_EOF2IE_Msk                      /*!< End of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_EOF3IE_Pos             (15U)
+#define CSI_IER0_EOF3IE_Msk             (0x1UL << CSI_IER0_EOF3IE_Pos)            /*!< 0x00008000 */
+#define CSI_IER0_EOF3IE                 CSI_IER0_EOF3IE_Msk                      /*!< End of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_SPKTIE_Pos             (16U)
+#define CSI_IER0_SPKTIE_Msk             (0x1UL << CSI_IER0_SPKTIE_Pos)            /*!< 0x00010000 */
+#define CSI_IER0_SPKTIE                 CSI_IER0_SPKTIE_Msk                      /*!< Short packet interrupt enable */
+#define CSI_IER0_CCFIFOFIE_Pos          (21U)
+#define CSI_IER0_CCFIFOFIE_Msk          (0x1UL << CSI_IER0_CCFIFOFIE_Pos)         /*!< 0x00200000 */
+#define CSI_IER0_CCFIFOFIE              CSI_IER0_CCFIFOFIE_Msk                   /*!< Clock changer FIFO full interrupt enable */
+#define CSI_IER0_CRCERRIE_Pos           (24U)
+#define CSI_IER0_CRCERRIE_Msk           (0x1UL << CSI_IER0_CRCERRIE_Pos)          /*!< 0x01000000 */
+#define CSI_IER0_CRCERRIE               CSI_IER0_CRCERRIE_Msk                    /*!< CRC error interrupt enable */
+#define CSI_IER0_ECCERRIE_Pos           (25U)
+#define CSI_IER0_ECCERRIE_Msk           (0x1UL << CSI_IER0_ECCERRIE_Pos)          /*!< 0x02000000 */
+#define CSI_IER0_ECCERRIE               CSI_IER0_ECCERRIE_Msk                    /*!< ECC error interrupt enable */
+#define CSI_IER0_CECCERRIE_Pos          (26U)
+#define CSI_IER0_CECCERRIE_Msk          (0x1UL << CSI_IER0_CECCERRIE_Pos)         /*!< 0x04000000 */
+#define CSI_IER0_CECCERRIE              CSI_IER0_CECCERRIE_Msk                   /*!< Corrected ECC error interrupt enable */
+#define CSI_IER0_IDERRIE_Pos            (27U)
+#define CSI_IER0_IDERRIE_Msk            (0x1UL << CSI_IER0_IDERRIE_Pos)           /*!< 0x08000000 */
+#define CSI_IER0_IDERRIE                CSI_IER0_IDERRIE_Msk                     /*!< Data type ID error interrupt enable */
+#define CSI_IER0_SPKTERRIE_Pos          (28U)
+#define CSI_IER0_SPKTERRIE_Msk          (0x1UL << CSI_IER0_SPKTERRIE_Pos)         /*!< 0x10000000 */
+#define CSI_IER0_SPKTERRIE              CSI_IER0_SPKTERRIE_Msk                   /*!< Short packet error interrupt enable */
+#define CSI_IER0_WDERRIE_Pos            (29U)
+#define CSI_IER0_WDERRIE_Msk            (0x1UL << CSI_IER0_WDERRIE_Pos)           /*!< 0x20000000 */
+#define CSI_IER0_WDERRIE                CSI_IER0_WDERRIE_Msk                     /*!< Watchdog error interrupt enable */
+#define CSI_IER0_SYNCERRIE_Pos          (30U)
+#define CSI_IER0_SYNCERRIE_Msk          (0x1UL << CSI_IER0_SYNCERRIE_Pos)         /*!< 0x40000000 */
+#define CSI_IER0_SYNCERRIE              CSI_IER0_SYNCERRIE_Msk                   /*!< Invalid synchronization error interrupt enable */
+
+/*******************  Bit definition for CSI_IER1 register  *******************/
+#define CSI_IER1_ESOTDL0IE_Pos          (0U)
+#define CSI_IER1_ESOTDL0IE_Msk          (0x1UL << CSI_IER1_ESOTDL0IE_Pos)         /*!< 0x00000001 */
+#define CSI_IER1_ESOTDL0IE              CSI_IER1_ESOTDL0IE_Msk                   /*!< Start of transmission error interrupt enable on lane 0 */
+#define CSI_IER1_ESOTSYNCDL0IE_Pos      (1U)
+#define CSI_IER1_ESOTSYNCDL0IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos)     /*!< 0x00000002 */
+#define CSI_IER1_ESOTSYNCDL0IE          CSI_IER1_ESOTSYNCDL0IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 0 */
+#define CSI_IER1_EESCDL0IE_Pos          (2U)
+#define CSI_IER1_EESCDL0IE_Msk          (0x1UL << CSI_IER1_EESCDL0IE_Pos)         /*!< 0x00000004 */
+#define CSI_IER1_EESCDL0IE              CSI_IER1_EESCDL0IE_Msk                   /*!< D-PHY_RX lane 0 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL0IE_Pos      (3U)
+#define CSI_IER1_ESYNCESCDL0IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos)     /*!< 0x00000008 */
+#define CSI_IER1_ESYNCESCDL0IE          CSI_IER1_ESYNCESCDL0IE_Msk               /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL0IE_Pos         (4U)
+#define CSI_IER1_ECTRLDL0IE_Msk         (0x1UL << CSI_IER1_ECTRLDL0IE_Pos)        /*!< 0x00000010 */
+#define CSI_IER1_ECTRLDL0IE             CSI_IER1_ECTRLDL0IE_Msk                  /*!< D-PHY_RX lane 0 control error interrupt enable */
+#define CSI_IER1_ESOTDL1IE_Pos          (8U)
+#define CSI_IER1_ESOTDL1IE_Msk          (0x1UL << CSI_IER1_ESOTDL1IE_Pos)         /*!< 0x00000100 */
+#define CSI_IER1_ESOTDL1IE              CSI_IER1_ESOTDL1IE_Msk                   /*!< Start of transmission error interrupt enable on lane 1 */
+#define CSI_IER1_ESOTSYNCDL1IE_Pos      (9U)
+#define CSI_IER1_ESOTSYNCDL1IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos)     /*!< 0x00000200 */
+#define CSI_IER1_ESOTSYNCDL1IE          CSI_IER1_ESOTSYNCDL1IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 1 */
+#define CSI_IER1_EESCDL1IE_Pos          (10U)
+#define CSI_IER1_EESCDL1IE_Msk          (0x1UL << CSI_IER1_EESCDL1IE_Pos)         /*!< 0x00000400 */
+#define CSI_IER1_EESCDL1IE              CSI_IER1_EESCDL1IE_Msk                   /*!< D-PHY_RX lane 1 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL1IE_Pos      (11U)
+#define CSI_IER1_ESYNCESCDL1IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos)     /*!< 0x00000800 */
+#define CSI_IER1_ESYNCESCDL1IE          CSI_IER1_ESYNCESCDL1IE_Msk               /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL1IE_Pos         (12U)
+#define CSI_IER1_ECTRLDL1IE_Msk         (0x1UL << CSI_IER1_ECTRLDL1IE_Pos)        /*!< 0x00001000 */
+#define CSI_IER1_ECTRLDL1IE             CSI_IER1_ECTRLDL1IE_Msk                  /*!< D-PHY_RX lane 1 control error interrupt enable */
+
+/*******************  Bit definition for CSI_SR0 register  ********************/
+#define CSI_SR0_LB0F_Pos                (0U)
+#define CSI_SR0_LB0F_Msk                (0x1UL << CSI_SR0_LB0F_Pos)               /*!< 0x00000001 */
+#define CSI_SR0_LB0F                    CSI_SR0_LB0F_Msk                         /*!< Line byte counter 0 flag */
+#define CSI_SR0_LB1F_Pos                (1U)
+#define CSI_SR0_LB1F_Msk                (0x1UL << CSI_SR0_LB1F_Pos)               /*!< 0x00000002 */
+#define CSI_SR0_LB1F                    CSI_SR0_LB1F_Msk                         /*!< Line byte counter 1 flag */
+#define CSI_SR0_LB2F_Pos                (2U)
+#define CSI_SR0_LB2F_Msk                (0x1UL << CSI_SR0_LB2F_Pos)               /*!< 0x00000004 */
+#define CSI_SR0_LB2F                    CSI_SR0_LB2F_Msk                         /*!< Line byte counter 2 flag */
+#define CSI_SR0_LB3F_Pos                (3U)
+#define CSI_SR0_LB3F_Msk                (0x1UL << CSI_SR0_LB3F_Pos)               /*!< 0x00000008 */
+#define CSI_SR0_LB3F                    CSI_SR0_LB3F_Msk                         /*!< Line byte counter 3 flag */
+#define CSI_SR0_TIM0F_Pos               (4U)
+#define CSI_SR0_TIM0F_Msk               (0x1UL << CSI_SR0_TIM0F_Pos)              /*!< 0x00000010 */
+#define CSI_SR0_TIM0F                   CSI_SR0_TIM0F_Msk                        /*!< Timer 0 flag */
+#define CSI_SR0_TIM1F_Pos               (5U)
+#define CSI_SR0_TIM1F_Msk               (0x1UL << CSI_SR0_TIM1F_Pos)              /*!< 0x00000020 */
+#define CSI_SR0_TIM1F                   CSI_SR0_TIM1F_Msk                        /*!< Timer 1 flag */
+#define CSI_SR0_TIM2F_Pos               (6U)
+#define CSI_SR0_TIM2F_Msk               (0x1UL << CSI_SR0_TIM2F_Pos)              /*!< 0x00000040 */
+#define CSI_SR0_TIM2F                   CSI_SR0_TIM2F_Msk                        /*!< Timer 2 flag */
+#define CSI_SR0_TIM3F_Pos               (7U)
+#define CSI_SR0_TIM3F_Msk               (0x1UL << CSI_SR0_TIM3F_Pos)              /*!< 0x00000080 */
+#define CSI_SR0_TIM3F                   CSI_SR0_TIM3F_Msk                        /*!< Timer 3 flag */
+#define CSI_SR0_SOF0F_Pos               (8U)
+#define CSI_SR0_SOF0F_Msk               (0x1UL << CSI_SR0_SOF0F_Pos)              /*!< 0x00000100 */
+#define CSI_SR0_SOF0F                   CSI_SR0_SOF0F_Msk                        /*!< Start of frame flag for virtual channel 0 */
+#define CSI_SR0_SOF1F_Pos               (9U)
+#define CSI_SR0_SOF1F_Msk               (0x1UL << CSI_SR0_SOF1F_Pos)              /*!< 0x00000200 */
+#define CSI_SR0_SOF1F                   CSI_SR0_SOF1F_Msk                        /*!< Start of frame flag for virtual channel 1 */
+#define CSI_SR0_SOF2F_Pos               (10U)
+#define CSI_SR0_SOF2F_Msk               (0x1UL << CSI_SR0_SOF2F_Pos)              /*!< 0x00000400 */
+#define CSI_SR0_SOF2F                   CSI_SR0_SOF2F_Msk                        /*!< Start of frame flag for virtual channel 2 */
+#define CSI_SR0_SOF3F_Pos               (11U)
+#define CSI_SR0_SOF3F_Msk               (0x1UL << CSI_SR0_SOF3F_Pos)              /*!< 0x00000800 */
+#define CSI_SR0_SOF3F                   CSI_SR0_SOF3F_Msk                        /*!< Start of frame flag for virtual channel 3 */
+#define CSI_SR0_EOF0F_Pos               (12U)
+#define CSI_SR0_EOF0F_Msk               (0x1UL << CSI_SR0_EOF0F_Pos)              /*!< 0x00001000 */
+#define CSI_SR0_EOF0F                   CSI_SR0_EOF0F_Msk                        /*!< End of frame flag for virtual channel 0 */
+#define CSI_SR0_EOF1F_Pos               (13U)
+#define CSI_SR0_EOF1F_Msk               (0x1UL << CSI_SR0_EOF1F_Pos)              /*!< 0x00002000 */
+#define CSI_SR0_EOF1F                   CSI_SR0_EOF1F_Msk                        /*!< End of frame flag for virtual channel 1 */
+#define CSI_SR0_EOF2F_Pos               (14U)
+#define CSI_SR0_EOF2F_Msk               (0x1UL << CSI_SR0_EOF2F_Pos)              /*!< 0x00004000 */
+#define CSI_SR0_EOF2F                   CSI_SR0_EOF2F_Msk                        /*!< End of frame flag for virtual channel 2 */
+#define CSI_SR0_EOF3F_Pos               (15U)
+#define CSI_SR0_EOF3F_Msk               (0x1UL << CSI_SR0_EOF3F_Pos)              /*!< 0x00008000 */
+#define CSI_SR0_EOF3F                   CSI_SR0_EOF3F_Msk                        /*!< End of frame flag for virtual channel 3 */
+#define CSI_SR0_SPKTF_Pos               (16U)
+#define CSI_SR0_SPKTF_Msk               (0x1UL << CSI_SR0_SPKTF_Pos)              /*!< 0x00010000 */
+#define CSI_SR0_SPKTF                   CSI_SR0_SPKTF_Msk                        /*!< Short packet flag */
+#define CSI_SR0_VC0STATEF_Pos           (17U)
+#define CSI_SR0_VC0STATEF_Msk           (0x1UL << CSI_SR0_VC0STATEF_Pos)          /*!< 0x00020000 */
+#define CSI_SR0_VC0STATEF               CSI_SR0_VC0STATEF_Msk                    /*!< Virtual channel 0 state flag */
+#define CSI_SR0_VC1STATEF_Pos           (18U)
+#define CSI_SR0_VC1STATEF_Msk           (0x1UL << CSI_SR0_VC1STATEF_Pos)          /*!< 0x00040000 */
+#define CSI_SR0_VC1STATEF               CSI_SR0_VC1STATEF_Msk                    /*!< Virtual channel 1 state flag */
+#define CSI_SR0_VC2STATEF_Pos           (19U)
+#define CSI_SR0_VC2STATEF_Msk           (0x1UL << CSI_SR0_VC2STATEF_Pos)          /*!< 0x00080000 */
+#define CSI_SR0_VC2STATEF               CSI_SR0_VC2STATEF_Msk                    /*!< Virtual channel 2 state flag */
+#define CSI_SR0_VC3STATEF_Pos           (20U)
+#define CSI_SR0_VC3STATEF_Msk           (0x1UL << CSI_SR0_VC3STATEF_Pos)          /*!< 0x00100000 */
+#define CSI_SR0_VC3STATEF               CSI_SR0_VC3STATEF_Msk                    /*!< Virtual channel 3 state flag */
+#define CSI_SR0_CCFIFOFF_Pos            (21U)
+#define CSI_SR0_CCFIFOFF_Msk            (0x1UL << CSI_SR0_CCFIFOFF_Pos)           /*!< 0x00200000 */
+#define CSI_SR0_CCFIFOFF                CSI_SR0_CCFIFOFF_Msk                     /*!< Clock changer FIFO full flag */
+#define CSI_SR0_CRCERRF_Pos             (24U)
+#define CSI_SR0_CRCERRF_Msk             (0x1UL << CSI_SR0_CRCERRF_Pos)            /*!< 0x01000000 */
+#define CSI_SR0_CRCERRF                 CSI_SR0_CRCERRF_Msk                      /*!< CRC error flag */
+#define CSI_SR0_ECCERRF_Pos             (25U)
+#define CSI_SR0_ECCERRF_Msk             (0x1UL << CSI_SR0_ECCERRF_Pos)            /*!< 0x02000000 */
+#define CSI_SR0_ECCERRF                 CSI_SR0_ECCERRF_Msk                      /*!< ECC error flag */
+#define CSI_SR0_CECCERRF_Pos            (26U)
+#define CSI_SR0_CECCERRF_Msk            (0x1UL << CSI_SR0_CECCERRF_Pos)           /*!< 0x04000000 */
+#define CSI_SR0_CECCERRF                CSI_SR0_CECCERRF_Msk                     /*!< Corrected ECC error flag */
+#define CSI_SR0_IDERRF_Pos              (27U)
+#define CSI_SR0_IDERRF_Msk              (0x1UL << CSI_SR0_IDERRF_Pos)             /*!< 0x08000000 */
+#define CSI_SR0_IDERRF                  CSI_SR0_IDERRF_Msk                       /*!< Data type ID error flag */
+#define CSI_SR0_SPKTERRF_Pos            (28U)
+#define CSI_SR0_SPKTERRF_Msk            (0x1UL << CSI_SR0_SPKTERRF_Pos)           /*!< 0x10000000 */
+#define CSI_SR0_SPKTERRF                CSI_SR0_SPKTERRF_Msk                     /*!< Short packet error flag */
+#define CSI_SR0_WDERRF_Pos              (29U)
+#define CSI_SR0_WDERRF_Msk              (0x1UL << CSI_SR0_WDERRF_Pos)             /*!< 0x20000000 */
+#define CSI_SR0_WDERRF                  CSI_SR0_WDERRF_Msk                       /*!< Watchdog error flag */
+#define CSI_SR0_SYNCERRF_Pos            (30U)
+#define CSI_SR0_SYNCERRF_Msk            (0x1UL << CSI_SR0_SYNCERRF_Pos)           /*!< 0x40000000 */
+#define CSI_SR0_SYNCERRF                CSI_SR0_SYNCERRF_Msk                     /*!< Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_SR1 register  ********************/
+#define CSI_SR1_ESOTDL0F_Pos            (0U)
+#define CSI_SR1_ESOTDL0F_Msk            (0x1UL << CSI_SR1_ESOTDL0F_Pos)           /*!< 0x00000001 */
+#define CSI_SR1_ESOTDL0F                CSI_SR1_ESOTDL0F_Msk                     /*!< Start of transmission error flag on lane 0 */
+#define CSI_SR1_ESOTSYNCDL0F_Pos        (1U)
+#define CSI_SR1_ESOTSYNCDL0F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos)       /*!< 0x00000002 */
+#define CSI_SR1_ESOTSYNCDL0F            CSI_SR1_ESOTSYNCDL0F_Msk                 /*!< Start of transmission synchronization error flag on lane 0 */
+#define CSI_SR1_EESCDL0F_Pos            (2U)
+#define CSI_SR1_EESCDL0F_Msk            (0x1UL << CSI_SR1_EESCDL0F_Pos)           /*!< 0x00000004 */
+#define CSI_SR1_EESCDL0F                CSI_SR1_EESCDL0F_Msk                     /*!< D-PHY_RX lane 0 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL0F_Pos        (3U)
+#define CSI_SR1_ESYNCESCDL0F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos)       /*!< 0x00000008 */
+#define CSI_SR1_ESYNCESCDL0F            CSI_SR1_ESYNCESCDL0F_Msk                 /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL0F_Pos           (4U)
+#define CSI_SR1_ECTRLDL0F_Msk           (0x1UL << CSI_SR1_ECTRLDL0F_Pos)          /*!< 0x00000010 */
+#define CSI_SR1_ECTRLDL0F               CSI_SR1_ECTRLDL0F_Msk                    /*!< D-PHY_RX lane 0 control error flag */
+#define CSI_SR1_ESOTDL1F_Pos            (8U)
+#define CSI_SR1_ESOTDL1F_Msk            (0x1UL << CSI_SR1_ESOTDL1F_Pos)           /*!< 0x00000100 */
+#define CSI_SR1_ESOTDL1F                CSI_SR1_ESOTDL1F_Msk                     /*!< Start of transmission error flag on lane 1 */
+#define CSI_SR1_ESOTSYNCDL1F_Pos        (9U)
+#define CSI_SR1_ESOTSYNCDL1F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos)       /*!< 0x00000200 */
+#define CSI_SR1_ESOTSYNCDL1F            CSI_SR1_ESOTSYNCDL1F_Msk                 /*!< Start of transmission synchronization error flag on lane 1 */
+#define CSI_SR1_EESCDL1F_Pos            (10U)
+#define CSI_SR1_EESCDL1F_Msk            (0x1UL << CSI_SR1_EESCDL1F_Pos)           /*!< 0x00000400 */
+#define CSI_SR1_EESCDL1F                CSI_SR1_EESCDL1F_Msk                     /*!< D-PHY_RX lane 1 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL1F_Pos        (11U)
+#define CSI_SR1_ESYNCESCDL1F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos)       /*!< 0x00000800 */
+#define CSI_SR1_ESYNCESCDL1F            CSI_SR1_ESYNCESCDL1F_Msk                 /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL1F_Pos           (12U)
+#define CSI_SR1_ECTRLDL1F_Msk           (0x1UL << CSI_SR1_ECTRLDL1F_Pos)          /*!< 0x00001000 */
+#define CSI_SR1_ECTRLDL1F               CSI_SR1_ECTRLDL1F_Msk                    /*!< D-PHY_RX lane 1 control error flag */
+#define CSI_SR1_ACTDL0F_Pos             (16U)
+#define CSI_SR1_ACTDL0F_Msk             (0x1UL << CSI_SR1_ACTDL0F_Pos)            /*!< 0x00010000 */
+#define CSI_SR1_ACTDL0F                 CSI_SR1_ACTDL0F_Msk                      /*!< D-PHY_RX lane 0 High speed reception active */
+#define CSI_SR1_SYNCDL0F_Pos            (17U)
+#define CSI_SR1_SYNCDL0F_Msk            (0x1UL << CSI_SR1_SYNCDL0F_Pos)           /*!< 0x00020000 */
+#define CSI_SR1_SYNCDL0F                CSI_SR1_SYNCDL0F_Msk                     /*!< D-PHY_RX lane 0 receiver synchronization observed */
+#define CSI_SR1_SKCALDL0F_Pos           (18U)
+#define CSI_SR1_SKCALDL0F_Msk           (0x1UL << CSI_SR1_SKCALDL0F_Pos)          /*!< 0x00040000 */
+#define CSI_SR1_SKCALDL0F               CSI_SR1_SKCALDL0F_Msk                    /*!< D-PHY_RX lane 0 High speed skew calibration */
+#define CSI_SR1_STOPDL0F_Pos            (19U)
+#define CSI_SR1_STOPDL0F_Msk            (0x1UL << CSI_SR1_STOPDL0F_Pos)           /*!< 0x00080000 */
+#define CSI_SR1_STOPDL0F                CSI_SR1_STOPDL0F_Msk                     /*!< D-PHY_RX receiver data lane 0 in stop state */
+#define CSI_SR1_ULPNDL0F_Pos            (20U)
+#define CSI_SR1_ULPNDL0F_Msk            (0x1UL << CSI_SR1_ULPNDL0F_Pos)           /*!< 0x00100000 */
+#define CSI_SR1_ULPNDL0F                CSI_SR1_ULPNDL0F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */
+#define CSI_SR1_ACTDL1F_Pos             (22U)
+#define CSI_SR1_ACTDL1F_Msk             (0x1UL << CSI_SR1_ACTDL1F_Pos)            /*!< 0x00400000 */
+#define CSI_SR1_ACTDL1F                 CSI_SR1_ACTDL1F_Msk                      /*!< D-PHY_RX lane 1 High speed reception active */
+#define CSI_SR1_SYNCDL1F_Pos            (23U)
+#define CSI_SR1_SYNCDL1F_Msk            (0x1UL << CSI_SR1_SYNCDL1F_Pos)           /*!< 0x00800000 */
+#define CSI_SR1_SYNCDL1F                CSI_SR1_SYNCDL1F_Msk                     /*!< D-PHY_RX lane 1 receiver synchronization observed */
+#define CSI_SR1_SKCALDL1F_Pos           (24U)
+#define CSI_SR1_SKCALDL1F_Msk           (0x1UL << CSI_SR1_SKCALDL1F_Pos)          /*!< 0x01000000 */
+#define CSI_SR1_SKCALDL1F               CSI_SR1_SKCALDL1F_Msk                    /*!< D-PHY_RX lane 1 High speed skew calibration */
+#define CSI_SR1_STOPDL1F_Pos            (25U)
+#define CSI_SR1_STOPDL1F_Msk            (0x1UL << CSI_SR1_STOPDL1F_Pos)           /*!< 0x02000000 */
+#define CSI_SR1_STOPDL1F                CSI_SR1_STOPDL1F_Msk                     /*!< D-PHY_RX receiver data lane 1 in stop state */
+#define CSI_SR1_ULPNDL1F_Pos            (26U)
+#define CSI_SR1_ULPNDL1F_Msk            (0x1UL << CSI_SR1_ULPNDL1F_Pos)           /*!< 0x04000000 */
+#define CSI_SR1_ULPNDL1F                CSI_SR1_ULPNDL1F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */
+#define CSI_SR1_STOPCLF_Pos             (28U)
+#define CSI_SR1_STOPCLF_Msk             (0x1UL << CSI_SR1_STOPCLF_Pos)            /*!< 0x10000000 */
+#define CSI_SR1_STOPCLF                 CSI_SR1_STOPCLF_Msk                      /*!< D-PHY_RX receiver in stop state for the clock lane */
+#define CSI_SR1_ULPNACTF_Pos            (29U)
+#define CSI_SR1_ULPNACTF_Msk            (0x1UL << CSI_SR1_ULPNACTF_Pos)           /*!< 0x20000000 */
+#define CSI_SR1_ULPNACTF                CSI_SR1_ULPNACTF_Msk                     /*!< D-PHY_RX receiver ULP state (not) active */
+#define CSI_SR1_ULPNCLF_Pos             (30U)
+#define CSI_SR1_ULPNCLF_Msk             (0x1UL << CSI_SR1_ULPNCLF_Pos)            /*!< 0x40000000 */
+#define CSI_SR1_ULPNCLF                 CSI_SR1_ULPNCLF_Msk                      /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */
+#define CSI_SR1_ACTCLF_Pos              (31U)
+#define CSI_SR1_ACTCLF_Msk              (0x1UL << CSI_SR1_ACTCLF_Pos)             /*!< 0x80000000 */
+#define CSI_SR1_ACTCLF                  CSI_SR1_ACTCLF_Msk                       /*!< D-PHY_RX receiver clock active flag */
+
+/*******************  Bit definition for CSI_FCR0 register  *******************/
+#define CSI_FCR0_CLB0F_Pos              (0U)
+#define CSI_FCR0_CLB0F_Msk              (0x1UL << CSI_FCR0_CLB0F_Pos)             /*!< 0x00000001 */
+#define CSI_FCR0_CLB0F                  CSI_FCR0_CLB0F_Msk                       /*!< Clear Line byte counter 0 flag */
+#define CSI_FCR0_CLB1F_Pos              (1U)
+#define CSI_FCR0_CLB1F_Msk              (0x1UL << CSI_FCR0_CLB1F_Pos)             /*!< 0x00000002 */
+#define CSI_FCR0_CLB1F                  CSI_FCR0_CLB1F_Msk                       /*!< Clear Line byte counter 1 flag */
+#define CSI_FCR0_CLB2F_Pos              (2U)
+#define CSI_FCR0_CLB2F_Msk              (0x1UL << CSI_FCR0_CLB2F_Pos)             /*!< 0x00000004 */
+#define CSI_FCR0_CLB2F                  CSI_FCR0_CLB2F_Msk                       /*!< Clear Line byte counter 2 flag */
+#define CSI_FCR0_CLB3F_Pos              (3U)
+#define CSI_FCR0_CLB3F_Msk              (0x1UL << CSI_FCR0_CLB3F_Pos)             /*!< 0x00000008 */
+#define CSI_FCR0_CLB3F                  CSI_FCR0_CLB3F_Msk                       /*!< Clear Line byte counter 3 flag */
+#define CSI_FCR0_CTIM0F_Pos             (4U)
+#define CSI_FCR0_CTIM0F_Msk             (0x1UL << CSI_FCR0_CTIM0F_Pos)            /*!< 0x00000010 */
+#define CSI_FCR0_CTIM0F                 CSI_FCR0_CTIM0F_Msk                      /*!< Clear Timer 0 flag */
+#define CSI_FCR0_CTIM1F_Pos             (5U)
+#define CSI_FCR0_CTIM1F_Msk             (0x1UL << CSI_FCR0_CTIM1F_Pos)            /*!< 0x00000020 */
+#define CSI_FCR0_CTIM1F                 CSI_FCR0_CTIM1F_Msk                      /*!< Clear Timer 1 flag */
+#define CSI_FCR0_CTIM2F_Pos             (6U)
+#define CSI_FCR0_CTIM2F_Msk             (0x1UL << CSI_FCR0_CTIM2F_Pos)            /*!< 0x00000040 */
+#define CSI_FCR0_CTIM2F                 CSI_FCR0_CTIM2F_Msk                      /*!< Clear Timer 2 flag */
+#define CSI_FCR0_CTIM3F_Pos             (7U)
+#define CSI_FCR0_CTIM3F_Msk             (0x1UL << CSI_FCR0_CTIM3F_Pos)            /*!< 0x00000080 */
+#define CSI_FCR0_CTIM3F                 CSI_FCR0_CTIM3F_Msk                      /*!< Clear Timer 3 flag */
+#define CSI_FCR0_CSOF0F_Pos             (8U)
+#define CSI_FCR0_CSOF0F_Msk             (0x1UL << CSI_FCR0_CSOF0F_Pos)            /*!< 0x00000100 */
+#define CSI_FCR0_CSOF0F                 CSI_FCR0_CSOF0F_Msk                      /*!< Clear Start of frame flag for virtual channel 0 */
+#define CSI_FCR0_CSOF1F_Pos             (9U)
+#define CSI_FCR0_CSOF1F_Msk             (0x1UL << CSI_FCR0_CSOF1F_Pos)            /*!< 0x00000200 */
+#define CSI_FCR0_CSOF1F                 CSI_FCR0_CSOF1F_Msk                      /*!< Clear Start of frame flag for virtual channel 1 */
+#define CSI_FCR0_CSOF2F_Pos             (10U)
+#define CSI_FCR0_CSOF2F_Msk             (0x1UL << CSI_FCR0_CSOF2F_Pos)            /*!< 0x00000400 */
+#define CSI_FCR0_CSOF2F                 CSI_FCR0_CSOF2F_Msk                      /*!< Clear Start of frame flag for virtual channel 2 */
+#define CSI_FCR0_CSOF3F_Pos             (11U)
+#define CSI_FCR0_CSOF3F_Msk             (0x1UL << CSI_FCR0_CSOF3F_Pos)            /*!< 0x00000800 */
+#define CSI_FCR0_CSOF3F                 CSI_FCR0_CSOF3F_Msk                      /*!< Clear Start of frame flag for virtual channel 3 */
+#define CSI_FCR0_CEOF0F_Pos             (12U)
+#define CSI_FCR0_CEOF0F_Msk             (0x1UL << CSI_FCR0_CEOF0F_Pos)            /*!< 0x00001000 */
+#define CSI_FCR0_CEOF0F                 CSI_FCR0_CEOF0F_Msk                      /*!< Clear End of frame flag for virtual channel 0 */
+#define CSI_FCR0_CEOF1F_Pos             (13U)
+#define CSI_FCR0_CEOF1F_Msk             (0x1UL << CSI_FCR0_CEOF1F_Pos)            /*!< 0x00002000 */
+#define CSI_FCR0_CEOF1F                 CSI_FCR0_CEOF1F_Msk                      /*!< Clear End of frame flag for virtual channel 1 */
+#define CSI_FCR0_CEOF2F_Pos             (14U)
+#define CSI_FCR0_CEOF2F_Msk             (0x1UL << CSI_FCR0_CEOF2F_Pos)            /*!< 0x00004000 */
+#define CSI_FCR0_CEOF2F                 CSI_FCR0_CEOF2F_Msk                      /*!< Clear End of frame flag for virtual channel 2 */
+#define CSI_FCR0_CEOF3F_Pos             (15U)
+#define CSI_FCR0_CEOF3F_Msk             (0x1UL << CSI_FCR0_CEOF3F_Pos)            /*!< 0x00008000 */
+#define CSI_FCR0_CEOF3F                 CSI_FCR0_CEOF3F_Msk                      /*!< Clear End of frame flag for virtual channel 3 */
+#define CSI_FCR0_CSPKTF_Pos             (16U)
+#define CSI_FCR0_CSPKTF_Msk             (0x1UL << CSI_FCR0_CSPKTF_Pos)            /*!< 0x00010000 */
+#define CSI_FCR0_CSPKTF                 CSI_FCR0_CSPKTF_Msk                      /*!< Clear Short packet flag */
+#define CSI_FCR0_CCCFIFOFF_Pos          (21U)
+#define CSI_FCR0_CCCFIFOFF_Msk          (0x1UL << CSI_FCR0_CCCFIFOFF_Pos)         /*!< 0x00200000 */
+#define CSI_FCR0_CCCFIFOFF              CSI_FCR0_CCCFIFOFF_Msk                   /*!< Clear Clock changer FIFO full flag */
+#define CSI_FCR0_CCRCERRF_Pos           (24U)
+#define CSI_FCR0_CCRCERRF_Msk           (0x1UL << CSI_FCR0_CCRCERRF_Pos)          /*!< 0x01000000 */
+#define CSI_FCR0_CCRCERRF               CSI_FCR0_CCRCERRF_Msk                    /*!< Clear CRC error flag */
+#define CSI_FCR0_CECCERRF_Pos           (25U)
+#define CSI_FCR0_CECCERRF_Msk           (0x1UL << CSI_FCR0_CECCERRF_Pos)          /*!< 0x02000000 */
+#define CSI_FCR0_CECCERRF               CSI_FCR0_CECCERRF_Msk                    /*!< Clear ECC error flag */
+#define CSI_FCR0_CCECCERRF_Pos          (26U)
+#define CSI_FCR0_CCECCERRF_Msk          (0x1UL << CSI_FCR0_CCECCERRF_Pos)         /*!< 0x04000000 */
+#define CSI_FCR0_CCECCERRF              CSI_FCR0_CCECCERRF_Msk                   /*!< Clear Corrected ECC error flag */
+#define CSI_FCR0_CIDERRF_Pos            (27U)
+#define CSI_FCR0_CIDERRF_Msk            (0x1UL << CSI_FCR0_CIDERRF_Pos)           /*!< 0x08000000 */
+#define CSI_FCR0_CIDERRF                CSI_FCR0_CIDERRF_Msk                     /*!< Clear Data type ID error flag */
+#define CSI_FCR0_CSPKTERRF_Pos          (28U)
+#define CSI_FCR0_CSPKTERRF_Msk          (0x1UL << CSI_FCR0_CSPKTERRF_Pos)         /*!< 0x10000000 */
+#define CSI_FCR0_CSPKTERRF              CSI_FCR0_CSPKTERRF_Msk                   /*!< Clear Short packet error flag */
+#define CSI_FCR0_CWDERRF_Pos            (29U)
+#define CSI_FCR0_CWDERRF_Msk            (0x1UL << CSI_FCR0_CWDERRF_Pos)           /*!< 0x20000000 */
+#define CSI_FCR0_CWDERRF                CSI_FCR0_CWDERRF_Msk                     /*!< Clear Watchdog error flag */
+#define CSI_FCR0_CSYNCERRF_Pos          (30U)
+#define CSI_FCR0_CSYNCERRF_Msk          (0x1UL << CSI_FCR0_CSYNCERRF_Pos)         /*!< 0x40000000 */
+#define CSI_FCR0_CSYNCERRF              CSI_FCR0_CSYNCERRF_Msk                   /*!< Clear Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_FCR1 register  *******************/
+#define CSI_FCR1_CESOTDL0F_Pos          (0U)
+#define CSI_FCR1_CESOTDL0F_Msk          (0x1UL << CSI_FCR1_CESOTDL0F_Pos)         /*!< 0x00000001 */
+#define CSI_FCR1_CESOTDL0F              CSI_FCR1_CESOTDL0F_Msk                   /*!< Clear Start of transmission error flag on lane 0 */
+#define CSI_FCR1_CESOTSYNCDL0F_Pos      (1U)
+#define CSI_FCR1_CESOTSYNCDL0F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos)     /*!< 0x00000002 */
+#define CSI_FCR1_CESOTSYNCDL0F          CSI_FCR1_CESOTSYNCDL0F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 0 */
+#define CSI_FCR1_CEESCDL0F_Pos          (2U)
+#define CSI_FCR1_CEESCDL0F_Msk          (0x1UL << CSI_FCR1_CEESCDL0F_Pos)         /*!< 0x00000004 */
+#define CSI_FCR1_CEESCDL0F              CSI_FCR1_CEESCDL0F_Msk                   /*!< Clear D-PHY_RX lane 0 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL0F_Pos      (3U)
+#define CSI_FCR1_CESYNCESCDL0F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos)     /*!< 0x00000008 */
+#define CSI_FCR1_CESYNCESCDL0F          CSI_FCR1_CESYNCESCDL0F_Msk               /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL0F_Pos         (4U)
+#define CSI_FCR1_CECTRLDL0F_Msk         (0x1UL << CSI_FCR1_CECTRLDL0F_Pos)        /*!< 0x00000010 */
+#define CSI_FCR1_CECTRLDL0F             CSI_FCR1_CECTRLDL0F_Msk                  /*!< Clear D-PHY_RX lane 0 control error flag */
+#define CSI_FCR1_CESOTDL1F_Pos          (8U)
+#define CSI_FCR1_CESOTDL1F_Msk          (0x1UL << CSI_FCR1_CESOTDL1F_Pos)         /*!< 0x00000100 */
+#define CSI_FCR1_CESOTDL1F              CSI_FCR1_CESOTDL1F_Msk                   /*!< Clear Start of transmission error flag on lane 1 */
+#define CSI_FCR1_CESOTSYNCDL1F_Pos      (9U)
+#define CSI_FCR1_CESOTSYNCDL1F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos)     /*!< 0x00000200 */
+#define CSI_FCR1_CESOTSYNCDL1F          CSI_FCR1_CESOTSYNCDL1F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 1 */
+#define CSI_FCR1_CEESCDL1F_Pos          (10U)
+#define CSI_FCR1_CEESCDL1F_Msk          (0x1UL << CSI_FCR1_CEESCDL1F_Pos)         /*!< 0x00000400 */
+#define CSI_FCR1_CEESCDL1F              CSI_FCR1_CEESCDL1F_Msk                   /*!< Clear D-PHY_RX lane 1 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL1F_Pos      (11U)
+#define CSI_FCR1_CESYNCESCDL1F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos)     /*!< 0x00000800 */
+#define CSI_FCR1_CESYNCESCDL1F          CSI_FCR1_CESYNCESCDL1F_Msk               /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL1F_Pos         (12U)
+#define CSI_FCR1_CECTRLDL1F_Msk         (0x1UL << CSI_FCR1_CECTRLDL1F_Pos)        /*!< 0x00001000 */
+#define CSI_FCR1_CECTRLDL1F             CSI_FCR1_CECTRLDL1F_Msk                  /*!< Clear D-PHY_RX lane 1 control error flag */
+
+/******************  Bit definition for CSI_SPDFR register  *******************/
+#define CSI_SPDFR_DATAFIELD_Pos         (0U)
+#define CSI_SPDFR_DATAFIELD_Msk         (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos)     /*!< 0x0000FFFF */
+#define CSI_SPDFR_DATAFIELD             CSI_SPDFR_DATAFIELD_Msk                  /*!< Data field */
+#define CSI_SPDFR_DATATYPE_Pos          (16U)
+#define CSI_SPDFR_DATATYPE_Msk          (0x3FUL << CSI_SPDFR_DATATYPE_Pos)        /*!< 0x003F0000 */
+#define CSI_SPDFR_DATATYPE              CSI_SPDFR_DATATYPE_Msk                   /*!< Data type class */
+#define CSI_SPDFR_VCHANNEL_Pos          (22U)
+#define CSI_SPDFR_VCHANNEL_Msk          (0x3UL << CSI_SPDFR_VCHANNEL_Pos)         /*!< 0x00C00000 */
+#define CSI_SPDFR_VCHANNEL              CSI_SPDFR_VCHANNEL_Msk                   /*!< Virtual channel */
+
+/*******************  Bit definition for CSI_ERR1 register  *******************/
+#define CSI_ERR1_CRCDTERR_Pos           (0U)
+#define CSI_ERR1_CRCDTERR_Msk           (0x3FUL << CSI_ERR1_CRCDTERR_Pos)         /*!< 0x0000003F */
+#define CSI_ERR1_CRCDTERR               CSI_ERR1_CRCDTERR_Msk                    /*!< Data type having a CRC error */
+#define CSI_ERR1_CRCVCERR_Pos           (6U)
+#define CSI_ERR1_CRCVCERR_Msk           (0x3UL << CSI_ERR1_CRCVCERR_Pos)          /*!< 0x000000C0 */
+#define CSI_ERR1_CRCVCERR               CSI_ERR1_CRCVCERR_Msk                    /*!< Virtual channel having a CRC error */
+#define CSI_ERR1_CECCDTERR_Pos          (8U)
+#define CSI_ERR1_CECCDTERR_Msk          (0x3FUL << CSI_ERR1_CECCDTERR_Pos)        /*!< 0x00003F00 */
+#define CSI_ERR1_CECCDTERR              CSI_ERR1_CECCDTERR_Msk                   /*!< Data type having a corrected ECC error */
+#define CSI_ERR1_CECCVCERR_Pos          (14U)
+#define CSI_ERR1_CECCVCERR_Msk          (0x3UL << CSI_ERR1_CECCVCERR_Pos)         /*!< 0x0000C000 */
+#define CSI_ERR1_CECCVCERR              CSI_ERR1_CECCVCERR_Msk                   /*!< Virtual channel having a corrected ECC error */
+#define CSI_ERR1_IDDTERR_Pos            (16U)
+#define CSI_ERR1_IDDTERR_Msk            (0x3FUL << CSI_ERR1_IDDTERR_Pos)          /*!< 0x003F0000 */
+#define CSI_ERR1_IDDTERR                CSI_ERR1_IDDTERR_Msk                     /*!< Data type in error */
+#define CSI_ERR1_IDVCERR_Pos            (22U)
+#define CSI_ERR1_IDVCERR_Msk            (0x3UL << CSI_ERR1_IDVCERR_Pos)           /*!< 0x00C00000 */
+#define CSI_ERR1_IDVCERR                CSI_ERR1_IDVCERR_Msk                     /*!< Virtual channel having ID error */
+
+/*******************  Bit definition for CSI_ERR2 register  *******************/
+#define CSI_ERR2_SPKTDTERR_Pos          (0U)
+#define CSI_ERR2_SPKTDTERR_Msk          (0x3FUL << CSI_ERR2_SPKTDTERR_Pos)        /*!< 0x0000003F */
+#define CSI_ERR2_SPKTDTERR              CSI_ERR2_SPKTDTERR_Msk                   /*!< Data type having a short packet error */
+#define CSI_ERR2_SPKTVCERR_Pos          (6U)
+#define CSI_ERR2_SPKTVCERR_Msk          (0x3UL << CSI_ERR2_SPKTVCERR_Pos)         /*!< 0x000000C0 */
+#define CSI_ERR2_SPKTVCERR              CSI_ERR2_SPKTVCERR_Msk                   /*!< Virtual channel having a short packet error */
+#define CSI_ERR2_WDVCERR_Pos            (16U)
+#define CSI_ERR2_WDVCERR_Msk            (0x3UL << CSI_ERR2_WDVCERR_Pos)           /*!< 0x00030000 */
+#define CSI_ERR2_WDVCERR                CSI_ERR2_WDVCERR_Msk                     /*!< Virtual channel having a watchdog error */
+#define CSI_ERR2_SYNCVCERR_Pos          (18U)
+#define CSI_ERR2_SYNCVCERR_Msk          (0x3UL << CSI_ERR2_SYNCVCERR_Pos)         /*!< 0x000C0000 */
+#define CSI_ERR2_SYNCVCERR              CSI_ERR2_SYNCVCERR_Msk                   /*!< Virtual channel having synchronization error */
+
+/*******************  Bit definition for CSI_PRCR register  *******************/
+#define CSI_PRCR_PEN_Pos                (1U)
+#define CSI_PRCR_PEN_Msk                (0x1UL << CSI_PRCR_PEN_Pos)               /*!< 0x00000002 */
+#define CSI_PRCR_PEN                    CSI_PRCR_PEN_Msk                         /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */
+
+/*******************  Bit definition for CSI_PMCR register  *******************/
+#define CSI_PMCR_FRXMDL0_Pos            (0U)
+#define CSI_PMCR_FRXMDL0_Msk            (0x1UL << CSI_PMCR_FRXMDL0_Pos)           /*!< 0x00000001 */
+#define CSI_PMCR_FRXMDL0                CSI_PMCR_FRXMDL0_Msk                     /*!< Force to Rx Mode the Data Lane 0 */
+#define CSI_PMCR_FRXMDL1_Pos            (1U)
+#define CSI_PMCR_FRXMDL1_Msk            (0x1UL << CSI_PMCR_FRXMDL1_Pos)           /*!< 0x00000002 */
+#define CSI_PMCR_FRXMDL1                CSI_PMCR_FRXMDL1_Msk                     /*!< Force to Rx Mode the Data Lane 1 */
+#define CSI_PMCR_FTXSMDL0_Pos           (2U)
+#define CSI_PMCR_FTXSMDL0_Msk           (0x1UL << CSI_PMCR_FTXSMDL0_Pos)          /*!< 0x00000004 */
+#define CSI_PMCR_FTXSMDL0               CSI_PMCR_FTXSMDL0_Msk                    /*!< Force to Tx Stop Mode the Data Lane 0 */
+#define CSI_PMCR_DTDL_Pos               (4U)
+#define CSI_PMCR_DTDL_Msk               (0x1UL << CSI_PMCR_DTDL_Pos)              /*!< 0x00000010 */
+#define CSI_PMCR_DTDL                   CSI_PMCR_DTDL_Msk                        /*!< Disable Turn-around Data Lane 0 */
+#define CSI_PMCR_RTDL0_Pos              (8U)
+#define CSI_PMCR_RTDL0_Msk              (0x1UL << CSI_PMCR_RTDL0_Pos)             /*!< 0x00000100 */
+#define CSI_PMCR_RTDL0                  CSI_PMCR_RTDL0_Msk                       /*!< Turn-around Request Data Lane 0 */
+#define CSI_PMCR_TUESDL0_Pos            (12U)
+#define CSI_PMCR_TUESDL0_Msk            (0x1UL << CSI_PMCR_TUESDL0_Pos)           /*!< 0x00001000 */
+#define CSI_PMCR_TUESDL0                CSI_PMCR_TUESDL0_Msk                     /*!< Tx ULP Escape-mode Data Lane 0 */
+#define CSI_PMCR_TUEXDL0_Pos            (16U)
+#define CSI_PMCR_TUEXDL0_Msk            (0x1UL << CSI_PMCR_TUEXDL0_Pos)           /*!< 0x00010000 */
+#define CSI_PMCR_TUEXDL0                CSI_PMCR_TUEXDL0_Msk                     /*!< Tx ULP Exit-sequence Data Lane 0 */
+
+/*******************  Bit definition for CSI_PFCR register  *******************/
+#define CSI_PFCR_CCFR_Pos               (0U)
+#define CSI_PFCR_CCFR_Msk               (0x3FUL << CSI_PFCR_CCFR_Pos)             /*!< 0x0000003F */
+#define CSI_PFCR_CCFR                   CSI_PFCR_CCFR_Msk                        /*!< Configuration Clock Frequency Range selection */
+#define CSI_PFCR_HSFR_Pos               (8U)
+#define CSI_PFCR_HSFR_Msk               (0x7FUL << CSI_PFCR_HSFR_Pos)             /*!< 0x00007F00 */
+#define CSI_PFCR_HSFR                   CSI_PFCR_HSFR_Msk                        /*!< PHY-high-speed Frequency Range selection */
+#define CSI_PFCR_DLD_Pos                (16U)
+#define CSI_PFCR_DLD_Msk                (0x1UL << CSI_PFCR_DLD_Pos)               /*!< 0x00010000 */
+#define CSI_PFCR_DLD                    CSI_PFCR_DLD_Msk                         /*!< Data Lane Direction of lane0 */
+
+/******************  Bit definition for CSI_PTCR0 register  *******************/
+#define CSI_PTCR0_TCKEN_Pos             (0U)
+#define CSI_PTCR0_TCKEN_Msk             (0x1UL << CSI_PTCR0_TCKEN_Pos)            /*!< 0x00000001 */
+#define CSI_PTCR0_TCKEN                 CSI_PTCR0_TCKEN_Msk                      /*!< Test-interface Clock Enable for the TDI bus into the PHY */
+#define CSI_PTCR0_TRSEN_Pos             (1U)
+#define CSI_PTCR0_TRSEN_Msk             (0x1UL << CSI_PTCR0_TRSEN_Pos)            /*!< 0x00000002 */
+#define CSI_PTCR0_TRSEN                 CSI_PTCR0_TRSEN_Msk                      /*!< Test-interface Reset Enable for the TDI bus into the PHY */
+
+/******************  Bit definition for CSI_PTCR1 register  *******************/
+#define CSI_PTCR1_TDI_Pos               (0U)
+#define CSI_PTCR1_TDI_Msk               (0xFFUL << CSI_PTCR1_TDI_Pos)             /*!< 0x000000FF */
+#define CSI_PTCR1_TDI                   CSI_PTCR1_TDI_Msk                        /*!< Test-interface Data In */
+#define CSI_PTCR1_TWM_Pos               (16U)
+#define CSI_PTCR1_TWM_Msk               (0x1UL << CSI_PTCR1_TWM_Pos)              /*!< 0x00010000 */
+#define CSI_PTCR1_TWM                   CSI_PTCR1_TWM_Msk                        /*!< Test-interface Write Mode selector */
+
+/*******************  Bit definition for CSI_PTSR register  *******************/
+#define CSI_PTSR_TDO_Pos                (0U)
+#define CSI_PTSR_TDO_Msk                (0xFFUL << CSI_PTSR_TDO_Pos)              /*!< 0x000000FF */
+#define CSI_PTSR_TDO                    CSI_PTSR_TDO_Msk                         /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                DBGMCU                                         */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  ****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos             (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk             (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)          /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                 DBGMCU_IDCODE_DEV_ID_Msk                       /*!< Device ID */
+#define DBGMCU_IDCODE_REV_ID_Pos             (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk             (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)         /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                 DBGMCU_IDCODE_REV_ID_Msk                       /*!< Revision ID */
+
+/********************  Bit definition for DBGMCU_CR register  ********************/
+#define DBGMCU_CR_DBG_SLEEP_Pos              (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk              (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)             /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                  DBGMCU_CR_DBG_SLEEP_Msk                        /*!< Allow debug in Sleep mode */
+#define DBGMCU_CR_DBG_STOP_Pos               (1U)
+#define DBGMCU_CR_DBG_STOP_Msk               (0x1UL << DBGMCU_CR_DBG_STOP_Pos)              /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                   DBGMCU_CR_DBG_STOP_Msk                         /*!< Allow debug in Stop mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos            (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk            (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)           /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                DBGMCU_CR_DBG_STANDBY_Msk                      /*!< Allow debug in Standby mode */
+#define DBGMCU_CR_DBGCLKEN_Pos               (20U)
+#define DBGMCU_CR_DBGCLKEN_Msk               (0x1UL << DBGMCU_CR_DBGCLKEN_Pos)              /*!< 0x00100000 */
+#define DBGMCU_CR_DBGCLKEN                   DBGMCU_CR_DBGCLKEN_Msk                         /*!< Debug clock enable through software */
+#define DBGMCU_CR_TRACECLKEN_Pos             (21U)
+#define DBGMCU_CR_TRACECLKEN_Msk             (0x1UL << DBGMCU_CR_TRACECLKEN_Pos)            /*!< 0x00200000 */
+#define DBGMCU_CR_TRACECLKEN                 DBGMCU_CR_TRACECLKEN_Msk                       /*!< TPIU export clock enable through software */
+#define DBGMCU_CR_DBTRGOEN_Pos               (28U)
+#define DBGMCU_CR_DBTRGOEN_Msk               (0x1UL << DBGMCU_CR_DBTRGOEN_Pos)              /*!< 0x10000000 */
+#define DBGMCU_CR_DBTRGOEN                   DBGMCU_CR_DBTRGOEN_Msk                         /*!< DBTRGIO connection control */
+#define DBGMCU_CR_HLT_TSGEN_EN_Pos           (31U)
+#define DBGMCU_CR_HLT_TSGEN_EN_Msk           (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos)          /*!< 0x80000000 */
+#define DBGMCU_CR_HLT_TSGEN_EN               DBGMCU_CR_HLT_TSGEN_EN_Msk                     /*!< TSGEN halt enable */
+
+/********************  Bit definition for DBGMCU_APB1LFZ1 register  ***************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos    (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP        DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk              /*!< TIM2 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos    (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP        DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk              /*!< TIM3 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos    (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP        DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk              /*!< TIM4 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos    (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP        DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk              /*!< TIM5 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos    (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP        DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk              /*!< TIM6 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos    (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos)  /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP        DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk             /*!< TIM7 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos   (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos)  /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP       DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk             /*!< TIM12 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos   (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos)  /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP       DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk             /*!< TIM13 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos   (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP       DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk             /*!< TIM14 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos  (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP      DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk            /*!< LPTIM1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos   (11U)
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP       DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk             /*!< WWDG1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos   (12U)
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP       DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk             /*!< TIM10 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos   (13U)
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP       DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk             /*!< TIM11 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos    (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos)   /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP        DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk              /*!< I2C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos    (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos)   /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP        DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk              /*!< I2C2 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos    (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos)   /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP        DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk              /*!< I2C3 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos    (24U)
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos)   /*!< 0x01000000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP        DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk              /*!< I3C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos    (25U)
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP        DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk              /*!< I3C2 SMBUS timeout stop in debug */
+
+/********************  Bit definition for DBGMCU_APB1HFZ1 register  ***************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos   (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk   (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP       DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk             /*!< FDCAN stop in debug */
+
+/********************  Bit definition for DBGMCU_APB2FZ1 register  ***************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos     (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos)    /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP         DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk               /*!< TIM1 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos     (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos)    /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP         DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk               /*!< TIM8 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos    (15U)
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP        DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk              /*!< TIM18 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos    (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos)   /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP        DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk              /*!< TIM15 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos    (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos)   /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP        DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk              /*!< TIM16 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos    (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos)   /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP        DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk              /*!< TIM17 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos     (19U)
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos)    /*!< 0x00080000 */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP         DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk               /*!< TIM9 stop in debug */
+
+/********************  Bit definition for DBGMCU_APB4FZ1 register  ***************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos     (8U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos)    /*!< 0x00000100 */
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP         DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk               /*!< I2C4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos   (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos)  /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP       DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk             /*!< LPTIM2 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos   (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP       DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk             /*!< LPTIM3 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos   (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP       DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk             /*!< LPTIM4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos   (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP       DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk             /*!< LPTIM5 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos      (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos)     /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP          DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk                /*!< RTC stop in debug */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos     (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos)    /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP         DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk               /*!< IWDG stop in debug */
+
+/********************  Bit definition for DBGMCU_APB5FZ1 register  ***************/
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos   (4U)
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk   (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos)  /*!< 0x00000010 */
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP       DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk             /*!< GFXTIM stop in debug */
+
+/********************  Bit definition for DBGMCU_AHB1FZ1 register  ***************/
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk              /*!< GPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk              /*!< GPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk              /*!< GPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk              /*!< GPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk              /*!< GPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk              /*!< GPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk              /*!< GPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk              /*!< GPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk              /*!< GPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk              /*!< GPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk             /*!< GPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk             /*!< GPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk             /*!< GPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk             /*!< GPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk             /*!< GPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk             /*!< GPDMA1_CH15 suspend in debug */
+
+/********************  Bit definition for DBGMCU_AHB5FZ1 register  ***************/
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk              /*!< HPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk              /*!< HPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk              /*!< HPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk              /*!< HPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk              /*!< HPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk              /*!< HPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk              /*!< HPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk              /*!< HPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk              /*!< HPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk              /*!< HPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk             /*!< HPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk             /*!< HPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk             /*!< HPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk             /*!< HPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk             /*!< HPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk             /*!< HPDMA1_CH15 suspend in debug */
+
+/********************  Bit definition for DBGMCU_SR register  ***************/
+#define DBGMCU_SR_AP0_PRESENT_Pos            (0U)
+#define DBGMCU_SR_AP0_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos)           /*!< 0x00000001 */
+#define DBGMCU_SR_AP0_PRESENT                DBGMCU_SR_AP0_PRESENT_Msk                      /*!< Access point 0 presence */
+#define DBGMCU_SR_AP1_PRESENT_Pos            (1U)
+#define DBGMCU_SR_AP1_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos)           /*!< 0x00000002 */
+#define DBGMCU_SR_AP1_PRESENT                DBGMCU_SR_AP1_PRESENT_Msk                      /*!< Access point 1 presence */
+#define DBGMCU_SR_AP0_ENABLE_Pos             (16U)
+#define DBGMCU_SR_AP0_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos)            /*!< 0x00010000 */
+#define DBGMCU_SR_AP0_ENABLE                 DBGMCU_SR_AP0_ENABLE_Msk                       /*!< Access point 0 enable */
+#define DBGMCU_SR_AP1_ENABLE_Pos             (17U)
+#define DBGMCU_SR_AP1_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos)            /*!< 0x00020000 */
+#define DBGMCU_SR_AP1_ENABLE                 DBGMCU_SR_AP1_ENABLE_Msk                       /*!< Access point 1 enable */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_HOST register  **********************/
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos     (0U)
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk     (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE         DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk                   /*!< Message[31:0] */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos      (0U)
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk      (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE          DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk                    /*!< Message[31:0] */
+
+/********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***************/
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos     (0U)
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk     (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos)    /*!< 0x00000001 */
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK         DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk               /*!< Access status to DBG_AUTH_HOST register */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos   (1U)
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk   (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos)  /*!< 0x00000002 */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK       DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk             /*!< Access status to DBG_AUTH_DEV register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos                 (0U)
+#define DCMI_CR_CAPTURE_Msk                 (0x1UL << DCMI_CR_CAPTURE_Pos)          /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE                     DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos                      (1U)
+#define DCMI_CR_CM_Msk                      (0x1UL << DCMI_CR_CM_Pos)               /*!< 0x00000002 */
+#define DCMI_CR_CM                          DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos                    (2U)
+#define DCMI_CR_CROP_Msk                    (0x1UL << DCMI_CR_CROP_Pos)             /*!< 0x00000004 */
+#define DCMI_CR_CROP                        DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos                    (3U)
+#define DCMI_CR_JPEG_Msk                    (0x1UL << DCMI_CR_JPEG_Pos)             /*!< 0x00000008 */
+#define DCMI_CR_JPEG                        DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos                     (4U)
+#define DCMI_CR_ESS_Msk                     (0x1UL << DCMI_CR_ESS_Pos)              /*!< 0x00000010 */
+#define DCMI_CR_ESS                         DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos                  (5U)
+#define DCMI_CR_PCKPOL_Msk                  (0x1UL << DCMI_CR_PCKPOL_Pos)           /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL                      DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos                   (6U)
+#define DCMI_CR_HSPOL_Msk                   (0x1UL << DCMI_CR_HSPOL_Pos)            /*!< 0x00000040 */
+#define DCMI_CR_HSPOL                       DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos                   (7U)
+#define DCMI_CR_VSPOL_Msk                   (0x1UL << DCMI_CR_VSPOL_Pos)            /*!< 0x00000080 */
+#define DCMI_CR_VSPOL                       DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_Pos                    (8U)
+#define DCMI_CR_FCRC_Msk                    (0x3UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000300 */
+#define DCMI_CR_FCRC                        DCMI_CR_FCRC_Msk                        /*!< DCMI Frame capture rate control FCRC[1:0] */
+#define DCMI_CR_FCRC_0                      (0x1UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000100 */
+#define DCMI_CR_FCRC_1                      (0x2UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000200 */
+#define DCMI_CR_EDM_Pos                     (10U)
+#define DCMI_CR_EDM_Msk                     (0x3UL << DCMI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define DCMI_CR_EDM                         DCMI_CR_EDM_Msk                         /*!< DCMI Extended data mode EDM[1:0] */
+#define DCMI_CR_EDM_0                       (0x1UL << DCMI_CR_EDM_Pos)              /*!< 0x00000400 */
+#define DCMI_CR_EDM_1                       (0x2UL << DCMI_CR_EDM_Pos)              /*!< 0x00000800 */
+#define DCMI_CR_ENABLE_Pos                  (14U)
+#define DCMI_CR_ENABLE_Msk                  (0x1UL << DCMI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define DCMI_CR_ENABLE                      DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos                     (16U)
+#define DCMI_CR_BSM_Msk                     (0x3UL << DCMI_CR_BSM_Pos)              /*!< 0x00030000 */
+#define DCMI_CR_BSM                         DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0                       (0x1UL << DCMI_CR_BSM_Pos)              /*!< 0x00010000 */
+#define DCMI_CR_BSM_1                       (0x2UL << DCMI_CR_BSM_Pos)              /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos                    (18U)
+#define DCMI_CR_OEBS_Msk                    (0x1UL << DCMI_CR_OEBS_Pos)             /*!< 0x00040000 */
+#define DCMI_CR_OEBS                        DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos                     (19U)
+#define DCMI_CR_LSM_Msk                     (0x1UL << DCMI_CR_LSM_Pos)              /*!< 0x00080000 */
+#define DCMI_CR_LSM                         DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos                    (20U)
+#define DCMI_CR_OELS_Msk                    (0x1UL << DCMI_CR_OELS_Pos)             /*!< 0x00100000 */
+#define DCMI_CR_OELS                        DCMI_CR_OELS_Msk
+#define DCMI_CR_PSDM_Pos                    (31U)
+#define DCMI_CR_PSDM_Msk                    (0x0UL << DCMI_CR_PSDM_Pos)             /*!< 0x00000000 */
+#define DCMI_CR_PSDM                        DCMI_CR_PSDM_Msk                        /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos                   (0U)
+#define DCMI_SR_HSYNC_Msk                   (0x1UL << DCMI_SR_HSYNC_Pos)            /*!< 0x00000001 */
+#define DCMI_SR_HSYNC                       DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos                   (1U)
+#define DCMI_SR_VSYNC_Msk                   (0x1UL << DCMI_SR_VSYNC_Pos)            /*!< 0x00000002 */
+#define DCMI_SR_VSYNC                       DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos                     (2U)
+#define DCMI_SR_FNE_Msk                     (0x1UL << DCMI_SR_FNE_Pos)              /*!< 0x00000004 */
+#define DCMI_SR_FNE                         DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos              (0U)
+#define DCMI_RIS_FRAME_RIS_Msk              (0x1UL << DCMI_RIS_FRAME_RIS_Pos)       /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS                  DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos                (1U)
+#define DCMI_RIS_OVR_RIS_Msk                (0x1UL << DCMI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS                    DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos                (2U)
+#define DCMI_RIS_ERR_RIS_Msk                (0x1UL << DCMI_RIS_ERR_RIS_Pos)         /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS                    DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos              (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk              (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)       /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos               (4U)
+#define DCMI_RIS_LINE_RIS_Msk               (0x1UL << DCMI_RIS_LINE_RIS_Pos)        /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS                   DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos               (0U)
+#define DCMI_IER_FRAME_IE_Msk               (0x1UL << DCMI_IER_FRAME_IE_Pos)        /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE                   DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos                 (1U)
+#define DCMI_IER_OVR_IE_Msk                 (0x1UL << DCMI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE                     DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos                 (2U)
+#define DCMI_IER_ERR_IE_Msk                 (0x1UL << DCMI_IER_ERR_IE_Pos)          /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE                     DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos               (3U)
+#define DCMI_IER_VSYNC_IE_Msk               (0x1UL << DCMI_IER_VSYNC_IE_Pos)        /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE                   DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos                (4U)
+#define DCMI_IER_LINE_IE_Msk                (0x1UL << DCMI_IER_LINE_IE_Pos)         /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE                    DCMI_IER_LINE_IE_Msk
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos              (0U)
+#define DCMI_MIS_FRAME_MIS_Msk              (0x1UL << DCMI_MIS_FRAME_MIS_Pos)       /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS                  DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos                (1U)
+#define DCMI_MIS_OVR_MIS_Msk                (0x1UL << DCMI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS                    DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos                (2U)
+#define DCMI_MIS_ERR_MIS_Msk                (0x1UL << DCMI_MIS_ERR_MIS_Pos)         /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS                    DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos              (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk              (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)       /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos               (4U)
+#define DCMI_MIS_LINE_MIS_Msk               (0x1UL << DCMI_MIS_LINE_MIS_Pos)        /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS                   DCMI_MIS_LINE_MIS_Msk
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos              (0U)
+#define DCMI_ICR_FRAME_ISC_Msk              (0x1UL << DCMI_ICR_FRAME_ISC_Pos)       /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC                  DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos                (1U)
+#define DCMI_ICR_OVR_ISC_Msk                (0x1UL << DCMI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC                    DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos                (2U)
+#define DCMI_ICR_ERR_ISC_Msk                (0x1UL << DCMI_ICR_ERR_ISC_Pos)         /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC                    DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos              (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk              (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)       /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC                  DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos               (4U)
+#define DCMI_ICR_LINE_ISC_Msk               (0x1UL << DCMI_ICR_LINE_ISC_Pos)        /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC                   DCMI_ICR_LINE_ISC_Msk
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos                   (0U)
+#define DCMI_ESCR_FSC_Msk                   (0xFFUL << DCMI_ESCR_FSC_Pos)           /*!< 0x000000FF */
+#define DCMI_ESCR_FSC                       DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos                   (8U)
+#define DCMI_ESCR_LSC_Msk                   (0xFFUL << DCMI_ESCR_LSC_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC                       DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos                   (16U)
+#define DCMI_ESCR_LEC_Msk                   (0xFFUL << DCMI_ESCR_LEC_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC                       DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos                   (24U)
+#define DCMI_ESCR_FEC_Msk                   (0xFFUL << DCMI_ESCR_FEC_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC                       DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos                   (0U)
+#define DCMI_ESUR_FSU_Msk                   (0xFFUL << DCMI_ESUR_FSU_Pos)           /*!< 0x000000FF */
+#define DCMI_ESUR_FSU                       DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos                   (8U)
+#define DCMI_ESUR_LSU_Msk                   (0xFFUL << DCMI_ESUR_LSU_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU                       DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos                   (16U)
+#define DCMI_ESUR_LEU_Msk                   (0xFFUL << DCMI_ESUR_LEU_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU                       DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos                   (24U)
+#define DCMI_ESUR_FEU_Msk                   (0xFFUL << DCMI_ESUR_FEU_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU                       DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos             (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk             (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)   /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT                 DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos                 (16U)
+#define DCMI_CWSTRT_VST_Msk                 (0x1FFFUL << DCMI_CWSTRT_VST_Pos)       /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST                     DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos              (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk              (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)    /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT                  DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos               (16U)
+#define DCMI_CWSIZE_VLINE_Msk               (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)     /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE                   DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos                   (0U)
+#define DCMI_DR_BYTE0_Msk                   (0xFFUL << DCMI_DR_BYTE0_Pos)           /*!< 0x000000FF */
+#define DCMI_DR_BYTE0                       DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos                   (8U)
+#define DCMI_DR_BYTE1_Msk                   (0xFFUL << DCMI_DR_BYTE1_Pos)           /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1                       DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos                   (16U)
+#define DCMI_DR_BYTE2_Msk                   (0xFFUL << DCMI_DR_BYTE2_Pos)           /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2                       DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos                   (24U)
+#define DCMI_DR_BYTE3_Msk                   (0xFFUL << DCMI_DR_BYTE3_Pos)           /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3                       DCMI_DR_BYTE3_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   DCMIPP                                   */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for DCMIPP_IPGR1 register  *****************/
+#define DCMIPP_IPGR1_MEMORYPAGE_Pos         (0U)
+#define DCMIPP_IPGR1_MEMORYPAGE_Msk         (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos)           /*!< 0x00000007 */
+#define DCMIPP_IPGR1_MEMORYPAGE             DCMIPP_IPGR1_MEMORYPAGE_Msk                     /*!< Memory page size, as power of 2 of 64-byte units: */
+#define DCMIPP_IPGR1_QOS_MODE_Pos           (24U)
+#define DCMIPP_IPGR1_QOS_MODE_Msk           (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_IPGR1_QOS_MODE               DCMIPP_IPGR1_QOS_MODE_Msk                       /*!< Quality of service */
+
+/*****************  Bit definition for DCMIPP_IPGR2 register  *****************/
+#define DCMIPP_IPGR2_PSTART_Pos             (0U)
+#define DCMIPP_IPGR2_PSTART_Msk             (0x1UL << DCMIPP_IPGR2_PSTART_Pos)               /*!< 0x00000001 */
+#define DCMIPP_IPGR2_PSTART                 DCMIPP_IPGR2_PSTART_Msk                         /*!< Request to lock the IP-Plug, to allow reconfiguration */
+
+/*****************  Bit definition for DCMIPP_IPGR3 register  *****************/
+#define DCMIPP_IPGR3_IDLE_Pos               (0U)
+#define DCMIPP_IPGR3_IDLE_Msk               (0x1UL << DCMIPP_IPGR3_IDLE_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_IPGR3_IDLE                   DCMIPP_IPGR3_IDLE_Msk                           /*!< Status of IP-Plug */
+
+/*****************  Bit definition for DCMIPP_IPGR8 register  *****************/
+#define DCMIPP_IPGR8_DID_Pos                (0U)
+#define DCMIPP_IPGR8_DID_Msk                (0x3FUL << DCMIPP_IPGR8_DID_Pos)                 /*!< 0x0000003F */
+#define DCMIPP_IPGR8_DID                    DCMIPP_IPGR8_DID_Msk                            /*!< Division identifier (0x14) */
+#define DCMIPP_IPGR8_REVID_Pos              (8U)
+#define DCMIPP_IPGR8_REVID_Msk              (0x1FUL << DCMIPP_IPGR8_REVID_Pos)               /*!< 0x00001F00 */
+#define DCMIPP_IPGR8_REVID                  DCMIPP_IPGR8_REVID_Msk                          /*!< Revision identifier (0x03) */
+#define DCMIPP_IPGR8_ARCHIID_Pos            (16U)
+#define DCMIPP_IPGR8_ARCHIID_Msk            (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos)             /*!< 0x001F0000 */
+#define DCMIPP_IPGR8_ARCHIID                DCMIPP_IPGR8_ARCHIID_Msk                        /*!< Architecture identifier (0x04) */
+#define DCMIPP_IPGR8_IPPID_Pos              (24U)
+#define DCMIPP_IPGR8_IPPID_Msk              (0xFFUL << DCMIPP_IPGR8_IPPID_Pos)               /*!< 0xFF000000 */
+#define DCMIPP_IPGR8_IPPID                  DCMIPP_IPGR8_IPPID_Msk                          /*!< IP identifier (0xAA) */
+
+/****************  Bit definition for DCMIPP_IPC1R1 register  *****************/
+#define DCMIPP_IPC1R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC1R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC1R1_TRAFFIC               DCMIPP_IPC1R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC1R1_OTR_Pos               (8U)
+#define DCMIPP_IPC1R1_OTR_Msk               (0xFUL << DCMIPP_IPC1R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC1R1_OTR                   DCMIPP_IPC1R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC1R2 register  *****************/
+#define DCMIPP_IPC1R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC1R2_WLRU_Msk              (0xFUL << DCMIPP_IPC1R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC1R2_WLRU                  DCMIPP_IPC1R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC1R3 register  *****************/
+#define DCMIPP_IPC1R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC1R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC1R3_DPREGSTART            DCMIPP_IPC1R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC1R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC1R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC1R3_DPREGEND              DCMIPP_IPC1R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC2R1 register  *****************/
+#define DCMIPP_IPC2R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC2R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC2R1_TRAFFIC               DCMIPP_IPC2R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC2R1_OTR_Pos               (8U)
+#define DCMIPP_IPC2R1_OTR_Msk               (0xFUL << DCMIPP_IPC2R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC2R1_OTR                   DCMIPP_IPC2R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC2R2 register  *****************/
+#define DCMIPP_IPC2R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC2R2_WLRU_Msk              (0xFUL << DCMIPP_IPC2R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC2R2_WLRU                  DCMIPP_IPC2R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC2R3 register  *****************/
+#define DCMIPP_IPC2R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC2R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC2R3_DPREGSTART            DCMIPP_IPC2R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC2R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC2R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC2R3_DPREGEND              DCMIPP_IPC2R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC3R1 register  *****************/
+#define DCMIPP_IPC3R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC3R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC3R1_TRAFFIC               DCMIPP_IPC3R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC3R1_OTR_Pos               (8U)
+#define DCMIPP_IPC3R1_OTR_Msk               (0xFUL << DCMIPP_IPC3R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC3R1_OTR                   DCMIPP_IPC3R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC3R2 register  *****************/
+#define DCMIPP_IPC3R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC3R2_WLRU_Msk              (0xFUL << DCMIPP_IPC3R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC3R2_WLRU                  DCMIPP_IPC3R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC3R3 register  *****************/
+#define DCMIPP_IPC3R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC3R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC3R3_DPREGSTART            DCMIPP_IPC3R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC3R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC3R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC3R3_DPREGEND              DCMIPP_IPC3R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC4R1 register  *****************/
+#define DCMIPP_IPC4R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC4R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC4R1_TRAFFIC               DCMIPP_IPC4R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC4R1_OTR_Pos               (8U)
+#define DCMIPP_IPC4R1_OTR_Msk               (0xFUL << DCMIPP_IPC4R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC4R1_OTR                   DCMIPP_IPC4R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC4R2 register  *****************/
+#define DCMIPP_IPC4R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC4R2_WLRU_Msk              (0xFUL << DCMIPP_IPC4R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC4R2_WLRU                  DCMIPP_IPC4R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC4R3 register  *****************/
+#define DCMIPP_IPC4R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC4R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC4R3_DPREGSTART            DCMIPP_IPC4R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC4R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC4R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC4R3_DPREGEND              DCMIPP_IPC4R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC5R1 register  *****************/
+#define DCMIPP_IPC5R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC5R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC5R1_TRAFFIC               DCMIPP_IPC5R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC5R1_OTR_Pos               (8U)
+#define DCMIPP_IPC5R1_OTR_Msk               (0xFUL << DCMIPP_IPC5R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC5R1_OTR                   DCMIPP_IPC5R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC5R2 register  *****************/
+#define DCMIPP_IPC5R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC5R2_WLRU_Msk              (0xFUL << DCMIPP_IPC5R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC5R2_WLRU                  DCMIPP_IPC5R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC5R3 register  *****************/
+#define DCMIPP_IPC5R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC5R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC5R3_DPREGSTART            DCMIPP_IPC5R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC5R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC5R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC5R3_DPREGEND              DCMIPP_IPC5R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/***************  Bit definition for DCMIPP_PRHWCFGR register  ****************/
+
+/*****************  Bit definition for DCMIPP_PRCR register  ******************/
+#define DCMIPP_PRCR_ESS_Pos                 (4U)
+#define DCMIPP_PRCR_ESS_Msk                 (0x1UL << DCMIPP_PRCR_ESS_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_PRCR_ESS                     DCMIPP_PRCR_ESS_Msk                             /*!< Embedded synchronization select */
+#define DCMIPP_PRCR_PCKPOL_Pos              (5U)
+#define DCMIPP_PRCR_PCKPOL_Msk              (0x1UL << DCMIPP_PRCR_PCKPOL_Pos)                /*!< 0x00000020 */
+#define DCMIPP_PRCR_PCKPOL                  DCMIPP_PRCR_PCKPOL_Msk                          /*!< Pixel clock polarity */
+#define DCMIPP_PRCR_HSPOL_Pos               (6U)
+#define DCMIPP_PRCR_HSPOL_Msk               (0x1UL << DCMIPP_PRCR_HSPOL_Pos)                 /*!< 0x00000040 */
+#define DCMIPP_PRCR_HSPOL                   DCMIPP_PRCR_HSPOL_Msk                           /*!< Horizontal synchronization polarity */
+#define DCMIPP_PRCR_VSPOL_Pos               (7U)
+#define DCMIPP_PRCR_VSPOL_Msk               (0x1UL << DCMIPP_PRCR_VSPOL_Pos)                 /*!< 0x00000080 */
+#define DCMIPP_PRCR_VSPOL                   DCMIPP_PRCR_VSPOL_Msk                           /*!< Vertical synchronization polarity */
+#define DCMIPP_PRCR_EDM_Pos                 (10U)
+#define DCMIPP_PRCR_EDM_Msk                 (0x7UL << DCMIPP_PRCR_EDM_Pos)                   /*!< 0x00001C00 */
+#define DCMIPP_PRCR_EDM                     DCMIPP_PRCR_EDM_Msk                             /*!< Extended data mode */
+#define DCMIPP_PRCR_ENABLE_Pos              (14U)
+#define DCMIPP_PRCR_ENABLE_Msk              (0x1UL << DCMIPP_PRCR_ENABLE_Pos)                /*!< 0x00004000 */
+#define DCMIPP_PRCR_ENABLE                  DCMIPP_PRCR_ENABLE_Msk                          /*!< Parallel interface enable */
+#define DCMIPP_PRCR_FORMAT_Pos              (16U)
+#define DCMIPP_PRCR_FORMAT_Msk              (0xFFUL << DCMIPP_PRCR_FORMAT_Pos)               /*!< 0x00FF0000 */
+#define DCMIPP_PRCR_FORMAT                  DCMIPP_PRCR_FORMAT_Msk                          /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */
+#define DCMIPP_PRCR_SWAPCYCLES_Pos          (25U)
+#define DCMIPP_PRCR_SWAPCYCLES_Msk          (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos)            /*!< 0x02000000 */
+#define DCMIPP_PRCR_SWAPCYCLES              DCMIPP_PRCR_SWAPCYCLES_Msk                      /*!< Swap data from cycle 0 vs */
+#define DCMIPP_PRCR_SWAPBITS_Pos            (26U)
+#define DCMIPP_PRCR_SWAPBITS_Msk            (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos)              /*!< 0x04000000 */
+#define DCMIPP_PRCR_SWAPBITS                DCMIPP_PRCR_SWAPBITS_Msk                        /*!< Swap LSB vs */
+
+/****************  Bit definition for DCMIPP_PRESCR register  *****************/
+#define DCMIPP_PRESCR_FSC_Pos               (0U)
+#define DCMIPP_PRESCR_FSC_Msk               (0xFFUL << DCMIPP_PRESCR_FSC_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESCR_FSC                   DCMIPP_PRESCR_FSC_Msk                           /*!< Frame start delimiter code */
+#define DCMIPP_PRESCR_LSC_Pos               (8U)
+#define DCMIPP_PRESCR_LSC_Msk               (0xFFUL << DCMIPP_PRESCR_LSC_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESCR_LSC                   DCMIPP_PRESCR_LSC_Msk                           /*!< Line start delimiter code */
+#define DCMIPP_PRESCR_LEC_Pos               (16U)
+#define DCMIPP_PRESCR_LEC_Msk               (0xFFUL << DCMIPP_PRESCR_LEC_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESCR_LEC                   DCMIPP_PRESCR_LEC_Msk                           /*!< Line end delimiter code */
+#define DCMIPP_PRESCR_FEC_Pos               (24U)
+#define DCMIPP_PRESCR_FEC_Msk               (0xFFUL << DCMIPP_PRESCR_FEC_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESCR_FEC                   DCMIPP_PRESCR_FEC_Msk                           /*!< Frame end delimiter code */
+
+/****************  Bit definition for DCMIPP_PRESUR register  *****************/
+#define DCMIPP_PRESUR_FSU_Pos               (0U)
+#define DCMIPP_PRESUR_FSU_Msk               (0xFFUL << DCMIPP_PRESUR_FSU_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESUR_FSU                   DCMIPP_PRESUR_FSU_Msk                           /*!< Frame start delimiter unmask */
+#define DCMIPP_PRESUR_LSU_Pos               (8U)
+#define DCMIPP_PRESUR_LSU_Msk               (0xFFUL << DCMIPP_PRESUR_LSU_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESUR_LSU                   DCMIPP_PRESUR_LSU_Msk                           /*!< Line start delimiter unmask */
+#define DCMIPP_PRESUR_LEU_Pos               (16U)
+#define DCMIPP_PRESUR_LEU_Msk               (0xFFUL << DCMIPP_PRESUR_LEU_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESUR_LEU                   DCMIPP_PRESUR_LEU_Msk                           /*!< Line end delimiter unmask */
+#define DCMIPP_PRESUR_FEU_Pos               (24U)
+#define DCMIPP_PRESUR_FEU_Msk               (0xFFUL << DCMIPP_PRESUR_FEU_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESUR_FEU                   DCMIPP_PRESUR_FEU_Msk                           /*!< Frame end delimiter unmask */
+
+/*****************  Bit definition for DCMIPP_PRIER register  *****************/
+#define DCMIPP_PRIER_ERRIE_Pos              (6U)
+#define DCMIPP_PRIER_ERRIE_Msk              (0x1UL << DCMIPP_PRIER_ERRIE_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRIER_ERRIE                  DCMIPP_PRIER_ERRIE_Msk                          /*!< Synchronization error interrupt enable */
+
+/*****************  Bit definition for DCMIPP_PRSR register  ******************/
+#define DCMIPP_PRSR_ERRF_Pos                (6U)
+#define DCMIPP_PRSR_ERRF_Msk                (0x1UL << DCMIPP_PRSR_ERRF_Pos)                  /*!< 0x00000040 */
+#define DCMIPP_PRSR_ERRF                    DCMIPP_PRSR_ERRF_Msk                            /*!< Synchronization error raw interrupt status */
+#define DCMIPP_PRSR_HSYNC_Pos               (16U)
+#define DCMIPP_PRSR_HSYNC_Msk               (0x1UL << DCMIPP_PRSR_HSYNC_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_PRSR_HSYNC                   DCMIPP_PRSR_HSYNC_Msk                           /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */
+#define DCMIPP_PRSR_VSYNC_Pos               (17U)
+#define DCMIPP_PRSR_VSYNC_Msk               (0x1UL << DCMIPP_PRSR_VSYNC_Pos)                 /*!< 0x00020000 */
+#define DCMIPP_PRSR_VSYNC                   DCMIPP_PRSR_VSYNC_Msk                           /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */
+
+/*****************  Bit definition for DCMIPP_PRFCR register  *****************/
+#define DCMIPP_PRFCR_CERRF_Pos              (6U)
+#define DCMIPP_PRFCR_CERRF_Msk              (0x1UL << DCMIPP_PRFCR_CERRF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRFCR_CERRF                  DCMIPP_PRFCR_CERRF_Msk                          /*!< Synchronization error interrupt status clear */
+
+/*****************  Bit definition for DCMIPP_CMCR register  ******************/
+#define DCMIPP_CMCR_INSEL_Pos               (0U)
+#define DCMIPP_CMCR_INSEL_Msk               (0x1UL << DCMIPP_CMCR_INSEL_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_CMCR_INSEL                   DCMIPP_CMCR_INSEL_Msk                           /*!< input selection */
+#define DCMIPP_CMCR_PSFC_Pos                (1U)
+#define DCMIPP_CMCR_PSFC_Msk                (0x3UL << DCMIPP_CMCR_PSFC_Pos)                  /*!< 0x00000006 */
+#define DCMIPP_CMCR_PSFC                    DCMIPP_CMCR_PSFC_Msk                            /*!< Pipe selection for the frame counter */
+#define DCMIPP_CMCR_CFC_Pos                 (4U)
+#define DCMIPP_CMCR_CFC_Msk                 (0x1UL << DCMIPP_CMCR_CFC_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_CMCR_CFC                     DCMIPP_CMCR_CFC_Msk                             /*!< Clear frame counter */
+#define DCMIPP_CMCR_SWAPRB_Pos              (7U)
+#define DCMIPP_CMCR_SWAPRB_Msk              (0x1UL << DCMIPP_CMCR_SWAPRB_Pos)                /*!< 0x00000080 */
+#define DCMIPP_CMCR_SWAPRB                  DCMIPP_CMCR_SWAPRB_Msk                          /*!< Swap R/U and B/V */
+
+/****************  Bit definition for DCMIPP_CMFRCR register  *****************/
+#define DCMIPP_CMFRCR_FRMCNT_Pos            (0U)
+#define DCMIPP_CMFRCR_FRMCNT_Msk            (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_CMFRCR_FRMCNT                DCMIPP_CMFRCR_FRMCNT_Msk                        /*!< Frame counter, read-only, loops around */
+
+/*****************  Bit definition for DCMIPP_CMIER register  *****************/
+#define DCMIPP_CMIER_ATXERRIE_Pos           (5U)
+#define DCMIPP_CMIER_ATXERRIE_Msk           (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMIER_ATXERRIE               DCMIPP_CMIER_ATXERRIE_Msk                       /*!< AXI Transfer error interrupt enable for IPPLUG */
+#define DCMIPP_CMIER_PRERRIE_Pos            (6U)
+#define DCMIPP_CMIER_PRERRIE_Msk            (0x1UL << DCMIPP_CMIER_PRERRIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMIER_PRERRIE                DCMIPP_CMIER_PRERRIE_Msk                        /*!< limit interrupt enable for the Parallel Interface */
+#define DCMIPP_CMIER_P0LINEIE_Pos           (8U)
+#define DCMIPP_CMIER_P0LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMIER_P0LINEIE               DCMIPP_CMIER_P0LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0FRAMEIE_Pos          (9U)
+#define DCMIPP_CMIER_P0FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMIER_P0FRAMEIE              DCMIPP_CMIER_P0FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0VSYNCIE_Pos          (10U)
+#define DCMIPP_CMIER_P0VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMIER_P0VSYNCIE              DCMIPP_CMIER_P0VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0LIMITIE_Pos          (14U)
+#define DCMIPP_CMIER_P0LIMITIE_Msk          (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMIER_P0LIMITIE              DCMIPP_CMIER_P0LIMITIE_Msk                      /*!< limit interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0OVRIE_Pos            (15U)
+#define DCMIPP_CMIER_P0OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMIER_P0OVRIE                DCMIPP_CMIER_P0OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P1LINEIE_Pos           (16U)
+#define DCMIPP_CMIER_P1LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMIER_P1LINEIE               DCMIPP_CMIER_P1LINEIE_Msk                       /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */
+#define DCMIPP_CMIER_P1FRAMEIE_Pos          (17U)
+#define DCMIPP_CMIER_P1FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMIER_P1FRAMEIE              DCMIPP_CMIER_P1FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1VSYNCIE_Pos          (18U)
+#define DCMIPP_CMIER_P1VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMIER_P1VSYNCIE              DCMIPP_CMIER_P1VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1OVRIE_Pos            (23U)
+#define DCMIPP_CMIER_P1OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMIER_P1OVRIE                DCMIPP_CMIER_P1OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P2LINEIE_Pos           (24U)
+#define DCMIPP_CMIER_P2LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMIER_P2LINEIE               DCMIPP_CMIER_P2LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2FRAMEIE_Pos          (25U)
+#define DCMIPP_CMIER_P2FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMIER_P2FRAMEIE              DCMIPP_CMIER_P2FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2VSYNCIE_Pos          (26U)
+#define DCMIPP_CMIER_P2VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMIER_P2VSYNCIE              DCMIPP_CMIER_P2VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2OVRIE_Pos            (31U)
+#define DCMIPP_CMIER_P2OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMIER_P2OVRIE                DCMIPP_CMIER_P2OVRIE_Msk                        /*!< Overrun interrupt status enable for the Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR1 register  *****************/
+#define DCMIPP_CMSR1_PRHSYNC_Pos            (0U)
+#define DCMIPP_CMSR1_PRHSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos)              /*!< 0x00000001 */
+#define DCMIPP_CMSR1_PRHSYNC                DCMIPP_CMSR1_PRHSYNC_Msk                        /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_PRVSYNC_Pos            (1U)
+#define DCMIPP_CMSR1_PRVSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos)              /*!< 0x00000002 */
+#define DCMIPP_CMSR1_PRVSYNC                DCMIPP_CMSR1_PRVSYNC_Msk                        /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_P0LSTLINE_Pos          (8U)
+#define DCMIPP_CMSR1_P0LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos)            /*!< 0x00000100 */
+#define DCMIPP_CMSR1_P0LSTLINE              DCMIPP_CMSR1_P0LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0LSTFRM_Pos           (9U)
+#define DCMIPP_CMSR1_P0LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR1_P0LSTFRM               DCMIPP_CMSR1_P0LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0CPTACT_Pos           (15U)
+#define DCMIPP_CMSR1_P0CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos)             /*!< 0x00008000 */
+#define DCMIPP_CMSR1_P0CPTACT               DCMIPP_CMSR1_P0CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */
+#define DCMIPP_CMSR1_P1LSTLINE_Pos          (16U)
+#define DCMIPP_CMSR1_P1LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos)            /*!< 0x00010000 */
+#define DCMIPP_CMSR1_P1LSTLINE              DCMIPP_CMSR1_P1LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1LSTFRM_Pos           (17U)
+#define DCMIPP_CMSR1_P1LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR1_P1LSTFRM               DCMIPP_CMSR1_P1LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1CPTACT_Pos           (23U)
+#define DCMIPP_CMSR1_P1CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos)             /*!< 0x00800000 */
+#define DCMIPP_CMSR1_P1CPTACT               DCMIPP_CMSR1_P1CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */
+#define DCMIPP_CMSR1_P2LSTLINE_Pos          (24U)
+#define DCMIPP_CMSR1_P2LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos)            /*!< 0x01000000 */
+#define DCMIPP_CMSR1_P2LSTLINE              DCMIPP_CMSR1_P2LSTLINE_Msk                      /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2LSTFRM_Pos           (25U)
+#define DCMIPP_CMSR1_P2LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR1_P2LSTFRM               DCMIPP_CMSR1_P2LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2CPTACT_Pos           (31U)
+#define DCMIPP_CMSR1_P2CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos)             /*!< 0x80000000 */
+#define DCMIPP_CMSR1_P2CPTACT               DCMIPP_CMSR1_P2CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR2 register  *****************/
+#define DCMIPP_CMSR2_ATXERRF_Pos            (5U)
+#define DCMIPP_CMSR2_ATXERRF_Msk            (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos)              /*!< 0x00000020 */
+#define DCMIPP_CMSR2_ATXERRF                DCMIPP_CMSR2_ATXERRF_Msk                        /*!< AXI transfer error interrupt status flag for the IPPLUG */
+#define DCMIPP_CMSR2_PRERRF_Pos             (6U)
+#define DCMIPP_CMSR2_PRERRF_Msk             (0x1UL << DCMIPP_CMSR2_PRERRF_Pos)               /*!< 0x00000040 */
+#define DCMIPP_CMSR2_PRERRF                 DCMIPP_CMSR2_PRERRF_Msk                         /*!< Synchronization error raw interrupt status for the parallel interface */
+#define DCMIPP_CMSR2_P0LINEF_Pos            (8U)
+#define DCMIPP_CMSR2_P0LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos)              /*!< 0x00000100 */
+#define DCMIPP_CMSR2_P0LINEF                DCMIPP_CMSR2_P0LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0FRAMEF_Pos           (9U)
+#define DCMIPP_CMSR2_P0FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR2_P0FRAMEF               DCMIPP_CMSR2_P0FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0VSYNCF_Pos           (10U)
+#define DCMIPP_CMSR2_P0VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos)             /*!< 0x00000400 */
+#define DCMIPP_CMSR2_P0VSYNCF               DCMIPP_CMSR2_P0VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0LIMITF_Pos           (14U)
+#define DCMIPP_CMSR2_P0LIMITF_Msk           (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos)             /*!< 0x00004000 */
+#define DCMIPP_CMSR2_P0LIMITF               DCMIPP_CMSR2_P0LIMITF_Msk                       /*!< Limit raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0OVRF_Pos             (15U)
+#define DCMIPP_CMSR2_P0OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos)               /*!< 0x00008000 */
+#define DCMIPP_CMSR2_P0OVRF                 DCMIPP_CMSR2_P0OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P1LINEF_Pos            (16U)
+#define DCMIPP_CMSR2_P1LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos)              /*!< 0x00010000 */
+#define DCMIPP_CMSR2_P1LINEF                DCMIPP_CMSR2_P1LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1FRAMEF_Pos           (17U)
+#define DCMIPP_CMSR2_P1FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR2_P1FRAMEF               DCMIPP_CMSR2_P1FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1VSYNCF_Pos           (18U)
+#define DCMIPP_CMSR2_P1VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos)             /*!< 0x00040000 */
+#define DCMIPP_CMSR2_P1VSYNCF               DCMIPP_CMSR2_P1VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1OVRF_Pos             (23U)
+#define DCMIPP_CMSR2_P1OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos)               /*!< 0x00800000 */
+#define DCMIPP_CMSR2_P1OVRF                 DCMIPP_CMSR2_P1OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P2LINEF_Pos            (24U)
+#define DCMIPP_CMSR2_P2LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos)              /*!< 0x01000000 */
+#define DCMIPP_CMSR2_P2LINEF                DCMIPP_CMSR2_P2LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2FRAMEF_Pos           (25U)
+#define DCMIPP_CMSR2_P2FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR2_P2FRAMEF               DCMIPP_CMSR2_P2FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2VSYNCF_Pos           (26U)
+#define DCMIPP_CMSR2_P2VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos)             /*!< 0x04000000 */
+#define DCMIPP_CMSR2_P2VSYNCF               DCMIPP_CMSR2_P2VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2OVRF_Pos             (31U)
+#define DCMIPP_CMSR2_P2OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos)               /*!< 0x80000000 */
+#define DCMIPP_CMSR2_P2OVRF                 DCMIPP_CMSR2_P2OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMFCR register  *****************/
+#define DCMIPP_CMFCR_CATXERRF_Pos           (5U)
+#define DCMIPP_CMFCR_CATXERRF_Msk           (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMFCR_CATXERRF               DCMIPP_CMFCR_CATXERRF_Msk                       /*!< AXI Transfer error interrupt status clear */
+#define DCMIPP_CMFCR_CPRERRF_Pos            (6U)
+#define DCMIPP_CMFCR_CPRERRF_Msk            (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMFCR_CPRERRF                DCMIPP_CMFCR_CPRERRF_Msk                        /*!< Synchronization error interrupt status clear */
+#define DCMIPP_CMFCR_CP0LINEF_Pos           (8U)
+#define DCMIPP_CMFCR_CP0LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMFCR_CP0LINEF               DCMIPP_CMFCR_CP0LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0FRAMEF_Pos          (9U)
+#define DCMIPP_CMFCR_CP0FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMFCR_CP0FRAMEF              DCMIPP_CMFCR_CP0FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0VSYNCF_Pos          (10U)
+#define DCMIPP_CMFCR_CP0VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMFCR_CP0VSYNCF              DCMIPP_CMFCR_CP0VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP0LIMITF_Pos          (14U)
+#define DCMIPP_CMFCR_CP0LIMITF_Msk          (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMFCR_CP0LIMITF              DCMIPP_CMFCR_CP0LIMITF_Msk                      /*!< limit interrupt status clear */
+#define DCMIPP_CMFCR_CP0OVRF_Pos            (15U)
+#define DCMIPP_CMFCR_CP0OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMFCR_CP0OVRF                DCMIPP_CMFCR_CP0OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP1LINEF_Pos           (16U)
+#define DCMIPP_CMFCR_CP1LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMFCR_CP1LINEF               DCMIPP_CMFCR_CP1LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1FRAMEF_Pos          (17U)
+#define DCMIPP_CMFCR_CP1FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMFCR_CP1FRAMEF              DCMIPP_CMFCR_CP1FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1VSYNCF_Pos          (18U)
+#define DCMIPP_CMFCR_CP1VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMFCR_CP1VSYNCF              DCMIPP_CMFCR_CP1VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP1OVRF_Pos            (23U)
+#define DCMIPP_CMFCR_CP1OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMFCR_CP1OVRF                DCMIPP_CMFCR_CP1OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP2LINEF_Pos           (24U)
+#define DCMIPP_CMFCR_CP2LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMFCR_CP2LINEF               DCMIPP_CMFCR_CP2LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2FRAMEF_Pos          (25U)
+#define DCMIPP_CMFCR_CP2FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMFCR_CP2FRAMEF              DCMIPP_CMFCR_CP2FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2VSYNCF_Pos          (26U)
+#define DCMIPP_CMFCR_CP2VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMFCR_CP2VSYNCF              DCMIPP_CMFCR_CP2VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP2OVRF_Pos            (31U)
+#define DCMIPP_CMFCR_CP2OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMFCR_CP2OVRF                DCMIPP_CMFCR_CP2OVRF_Msk                        /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0FSCR register  *****************/
+#define DCMIPP_P0FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P0FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P0FSCR_DTIDA                 DCMIPP_P0FSCR_DTIDA_Msk                         /*!< Data type selection ID A */
+#define DCMIPP_P0FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P0FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P0FSCR_DTIDB                 DCMIPP_P0FSCR_DTIDB_Msk                         /*!< Data type selection ID B */
+#define DCMIPP_P0FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P0FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P0FSCR_DTMODE                DCMIPP_P0FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_VC_Pos                (19U)
+#define DCMIPP_P0FSCR_VC_Msk                (0x3UL << DCMIPP_P0FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P0FSCR_VC                    DCMIPP_P0FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P0FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P0FSCR_PIPEN                 DCMIPP_P0FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P0FCTCR register  ****************/
+#define DCMIPP_P0FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P0FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P0FCTCR_FRATE                DCMIPP_P0FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P0FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P0FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P0FCTCR_CPTMODE              DCMIPP_P0FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P0FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P0FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P0FCTCR_CPTREQ               DCMIPP_P0FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P0SCSTR register  ****************/
+#define DCMIPP_P0SCSTR_HSTART_Pos           (0U)
+#define DCMIPP_P0SCSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0SCSTR_HSTART               DCMIPP_P0SCSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0SCSTR_VSTART_Pos           (16U)
+#define DCMIPP_P0SCSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSTR_VSTART               DCMIPP_P0SCSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P0SCSZR register  ****************/
+#define DCMIPP_P0SCSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P0SCSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P0SCSZR_HSIZE                DCMIPP_P0SCSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0SCSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P0SCSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSZR_VSIZE                DCMIPP_P0SCSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0SCSZR_POSNEG_Pos           (30U)
+#define DCMIPP_P0SCSZR_POSNEG_Msk           (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P0SCSZR_POSNEG               DCMIPP_P0SCSZR_POSNEG_Msk                       /*!< This bit is set and cleared by software */
+#define DCMIPP_P0SCSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P0SCSZR_ENABLE_Msk           (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P0SCSZR_ENABLE               DCMIPP_P0SCSZR_ENABLE_Msk                       /*!< This bit is set and cleared by software */
+
+/***************  Bit definition for DCMIPP_P0DCCNTR register  ****************/
+#define DCMIPP_P0DCCNTR_CNT_Pos             (0U)
+#define DCMIPP_P0DCCNTR_CNT_Msk             (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos)         /*!< 0x03FFFFFF */
+#define DCMIPP_P0DCCNTR_CNT                 DCMIPP_P0DCCNTR_CNT_Msk                         /*!< Number of data dumped during the frame */
+
+/***************  Bit definition for DCMIPP_P0DCLMTR register  ****************/
+#define DCMIPP_P0DCLMTR_LIMIT_Pos           (0U)
+#define DCMIPP_P0DCLMTR_LIMIT_Msk           (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos)        /*!< 0x00FFFFFF */
+#define DCMIPP_P0DCLMTR_LIMIT               DCMIPP_P0DCLMTR_LIMIT_Msk                       /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */
+#define DCMIPP_P0DCLMTR_ENABLE_Pos          (31U)
+#define DCMIPP_P0DCLMTR_ENABLE_Msk          (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0DCLMTR_ENABLE              DCMIPP_P0DCLMTR_ENABLE_Msk                      /*!<  */
+
+/****************  Bit definition for DCMIPP_P0PPCR register  *****************/
+#define DCMIPP_P0PPCR_SWAPYUV_Pos           (0U)
+#define DCMIPP_P0PPCR_SWAPYUV_Msk           (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P0PPCR_SWAPYUV               DCMIPP_P0PPCR_SWAPYUV_Msk                       /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0PPCR_PAD_Pos               (5U)
+#define DCMIPP_P0PPCR_PAD_Msk               (0x1UL << DCMIPP_P0PPCR_PAD_Pos)                 /*!< 0x00000020 */
+#define DCMIPP_P0PPCR_PAD                   DCMIPP_P0PPCR_PAD_Msk                           /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0PPCR_HEADEREN_Pos          (6U)
+#define DCMIPP_P0PPCR_HEADEREN_Msk          (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos)            /*!< 0x00000040 */
+#define DCMIPP_P0PPCR_HEADEREN              DCMIPP_P0PPCR_HEADEREN_Msk                      /*!< CSI header dump enable */
+#define DCMIPP_P0PPCR_BSM_Pos               (7U)
+#define DCMIPP_P0PPCR_BSM_Msk               (0x3UL << DCMIPP_P0PPCR_BSM_Pos)                 /*!< 0x00000180 */
+#define DCMIPP_P0PPCR_BSM                   DCMIPP_P0PPCR_BSM_Msk                           /*!< Byte select mode */
+#define DCMIPP_P0PPCR_OEBS_Pos              (9U)
+#define DCMIPP_P0PPCR_OEBS_Msk              (0x1UL << DCMIPP_P0PPCR_OEBS_Pos)                /*!< 0x00000200 */
+#define DCMIPP_P0PPCR_OEBS                  DCMIPP_P0PPCR_OEBS_Msk                          /*!< Odd/even byte select (byte select start) */
+#define DCMIPP_P0PPCR_LSM_Pos               (10U)
+#define DCMIPP_P0PPCR_LSM_Msk               (0x1UL << DCMIPP_P0PPCR_LSM_Pos)                 /*!< 0x00000400 */
+#define DCMIPP_P0PPCR_LSM                   DCMIPP_P0PPCR_LSM_Msk                           /*!< Line select mode */
+#define DCMIPP_P0PPCR_OELS_Pos              (11U)
+#define DCMIPP_P0PPCR_OELS_Msk              (0x1UL << DCMIPP_P0PPCR_OELS_Pos)                /*!< 0x00000800 */
+#define DCMIPP_P0PPCR_OELS                  DCMIPP_P0PPCR_OELS_Msk                          /*!< Odd/even line select (line select start) */
+#define DCMIPP_P0PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P0PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P0PPCR_LINEMULT              DCMIPP_P0PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0PPCR_DBM_Pos               (16U)
+#define DCMIPP_P0PPCR_DBM_Msk               (0x1UL << DCMIPP_P0PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P0PPCR_DBM                   DCMIPP_P0PPCR_DBM_Msk                           /*!< Double buffer mode */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR1 register  ***************/
+#define DCMIPP_P0PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR1_M0A                DCMIPP_P0PPM0AR1_M0A_Msk                        /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR2 register  ***************/
+#define DCMIPP_P0PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR2_M0A                DCMIPP_P0PPM0AR2_M0A_Msk                        /*!< Memory0 address */
+
+/*****************  Bit definition for DCMIPP_P0IER register  *****************/
+#define DCMIPP_P0IER_LINEIE_Pos             (0U)
+#define DCMIPP_P0IER_LINEIE_Msk             (0x1UL << DCMIPP_P0IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0IER_LINEIE                 DCMIPP_P0IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P0IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P0IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0IER_FRAMEIE                DCMIPP_P0IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P0IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P0IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0IER_VSYNCIE                DCMIPP_P0IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P0IER_LIMITIE_Pos            (6U)
+#define DCMIPP_P0IER_LIMITIE_Msk            (0x1UL << DCMIPP_P0IER_LIMITIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0IER_LIMITIE                DCMIPP_P0IER_LIMITIE_Msk                        /*!< Limit interrupt enable */
+#define DCMIPP_P0IER_OVRIE_Pos              (7U)
+#define DCMIPP_P0IER_OVRIE_Msk              (0x1UL << DCMIPP_P0IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0IER_OVRIE                  DCMIPP_P0IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P0SR register  ******************/
+#define DCMIPP_P0SR_LINEF_Pos               (0U)
+#define DCMIPP_P0SR_LINEF_Msk               (0x1UL << DCMIPP_P0SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P0SR_LINEF                   DCMIPP_P0SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P0SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P0SR_FRAMEF_Msk              (0x1UL << DCMIPP_P0SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P0SR_FRAMEF                  DCMIPP_P0SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P0SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P0SR_VSYNCF_Msk              (0x1UL << DCMIPP_P0SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P0SR_VSYNCF                  DCMIPP_P0SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P0SR_LIMITF_Pos              (6U)
+#define DCMIPP_P0SR_LIMITF_Msk              (0x1UL << DCMIPP_P0SR_LIMITF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_P0SR_LIMITF                  DCMIPP_P0SR_LIMITF_Msk                          /*!< Limit raw interrupt status */
+#define DCMIPP_P0SR_OVRF_Pos                (7U)
+#define DCMIPP_P0SR_OVRF_Msk                (0x1UL << DCMIPP_P0SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P0SR_OVRF                    DCMIPP_P0SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P0SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P0SR_LSTLINE_Msk             (0x1UL << DCMIPP_P0SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P0SR_LSTLINE                 DCMIPP_P0SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P0SR_LSTFRM_Msk              (0x1UL << DCMIPP_P0SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P0SR_LSTFRM                  DCMIPP_P0SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_CPTACT_Pos              (23U)
+#define DCMIPP_P0SR_CPTACT_Msk              (0x1UL << DCMIPP_P0SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P0SR_CPTACT                  DCMIPP_P0SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P0FCR register  *****************/
+#define DCMIPP_P0FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P0FCR_CLINEF_Msk             (0x1UL << DCMIPP_P0FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0FCR_CLINEF                 DCMIPP_P0FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P0FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0FCR_CFRAMEF                DCMIPP_P0FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P0FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0FCR_CVSYNCF                DCMIPP_P0FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P0FCR_CLIMITF_Pos            (6U)
+#define DCMIPP_P0FCR_CLIMITF_Msk            (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0FCR_CLIMITF                DCMIPP_P0FCR_CLIMITF_Msk                        /*!< limit interrupt status clear */
+#define DCMIPP_P0FCR_COVRF_Pos              (7U)
+#define DCMIPP_P0FCR_COVRF_Msk              (0x1UL << DCMIPP_P0FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0FCR_COVRF                  DCMIPP_P0FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0CFSCR register  ****************/
+#define DCMIPP_P0CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P0CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P0CFSCR_DTIDA                DCMIPP_P0CFSCR_DTIDA_Msk                        /*!< Current Data type selection ID A */
+#define DCMIPP_P0CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P0CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P0CFSCR_DTIDB                DCMIPP_P0CFSCR_DTIDB_Msk                        /*!< Current Data type selection ID B */
+#define DCMIPP_P0CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P0CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P0CFSCR_DTMODE               DCMIPP_P0CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P0CFSCR_VC_Pos               (19U)
+#define DCMIPP_P0CFSCR_VC_Msk               (0x3UL << DCMIPP_P0CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P0CFSCR_VC                   DCMIPP_P0CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P0CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P0CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P0CFSCR_PIPEN                DCMIPP_P0CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P0CFCTCR register  ****************/
+#define DCMIPP_P0CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P0CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P0CFCTCR_FRATE               DCMIPP_P0CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P0CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P0CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P0CFCTCR_CPTMODE             DCMIPP_P0CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P0CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P0CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P0CFCTCR_CPTREQ              DCMIPP_P0CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P0CSCSTR register  ****************/
+#define DCMIPP_P0CSCSTR_HSTART_Pos          (0U)
+#define DCMIPP_P0CSCSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSTR_HSTART              DCMIPP_P0CSCSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0CSCSTR_VSTART_Pos          (16U)
+#define DCMIPP_P0CSCSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSTR_VSTART              DCMIPP_P0CSCSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P0CSCSZR register  ****************/
+#define DCMIPP_P0CSCSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P0CSCSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSZR_HSIZE               DCMIPP_P0CSCSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0CSCSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P0CSCSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSZR_VSIZE               DCMIPP_P0CSCSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0CSCSZR_POSNEG_Pos          (30U)
+#define DCMIPP_P0CSCSZR_POSNEG_Msk          (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos)            /*!< 0x40000000 */
+#define DCMIPP_P0CSCSZR_POSNEG              DCMIPP_P0CSCSZR_POSNEG_Msk                      /*!< Current value of the POSNEG bit */
+#define DCMIPP_P0CSCSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P0CSCSZR_ENABLE_Msk          (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0CSCSZR_ENABLE              DCMIPP_P0CSCSZR_ENABLE_Msk                      /*!< Current value of the ENABLE bit */
+
+/****************  Bit definition for DCMIPP_P0CPPCR register  ****************/
+#define DCMIPP_P0CPPCR_SWAPYUV_Pos          (0U)
+#define DCMIPP_P0CPPCR_SWAPYUV_Msk          (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P0CPPCR_SWAPYUV              DCMIPP_P0CPPCR_SWAPYUV_Msk                      /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0CPPCR_PAD_Pos              (5U)
+#define DCMIPP_P0CPPCR_PAD_Msk              (0x1UL << DCMIPP_P0CPPCR_PAD_Pos)                /*!< 0x00000020 */
+#define DCMIPP_P0CPPCR_PAD                  DCMIPP_P0CPPCR_PAD_Msk                          /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0CPPCR_HEADEREN_Pos         (6U)
+#define DCMIPP_P0CPPCR_HEADEREN_Msk         (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos)           /*!< 0x00000040 */
+#define DCMIPP_P0CPPCR_HEADEREN             DCMIPP_P0CPPCR_HEADEREN_Msk                     /*!< Current CSI header dump enable */
+#define DCMIPP_P0CPPCR_BSM_Pos              (7U)
+#define DCMIPP_P0CPPCR_BSM_Msk              (0x3UL << DCMIPP_P0CPPCR_BSM_Pos)                /*!< 0x00000180 */
+#define DCMIPP_P0CPPCR_BSM                  DCMIPP_P0CPPCR_BSM_Msk                          /*!< Current Byte select mode */
+#define DCMIPP_P0CPPCR_OEBS_Pos             (9U)
+#define DCMIPP_P0CPPCR_OEBS_Msk             (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos)               /*!< 0x00000200 */
+#define DCMIPP_P0CPPCR_OEBS                 DCMIPP_P0CPPCR_OEBS_Msk                         /*!< Current odd/even byte select (Byte select start) */
+#define DCMIPP_P0CPPCR_LSM_Pos              (10U)
+#define DCMIPP_P0CPPCR_LSM_Msk              (0x1UL << DCMIPP_P0CPPCR_LSM_Pos)                /*!< 0x00000400 */
+#define DCMIPP_P0CPPCR_LSM                  DCMIPP_P0CPPCR_LSM_Msk                          /*!< Current Line select mode */
+#define DCMIPP_P0CPPCR_OELS_Pos             (11U)
+#define DCMIPP_P0CPPCR_OELS_Msk             (0x1UL << DCMIPP_P0CPPCR_OELS_Pos)               /*!< 0x00000800 */
+#define DCMIPP_P0CPPCR_OELS                 DCMIPP_P0CPPCR_OELS_Msk                         /*!< Current odd/even line select (Line select start) */
+#define DCMIPP_P0CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P0CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P0CPPCR_LINEMULT             DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Current amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P0CPPCR_DBM_Msk              (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P0CPPCR_DBM                  DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Double buffer mode */
+
+/**************  Bit definition for DCMIPP_P0CPPM0AR1 register  ***************/
+#define DCMIPP_P0CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P0CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P0CPPM0AR1_M0A               DCMIPP_P0CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/****************  Bit definition for DCMIPP_P1FSCR register  *****************/
+#define DCMIPP_P1FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P1FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P1FSCR_DTIDA                 DCMIPP_P1FSCR_DTIDA_Msk                         /*!< Data type ID A */
+#define DCMIPP_P1FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P1FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P1FSCR_DTIDB                 DCMIPP_P1FSCR_DTIDB_Msk                         /*!< Data type ID B */
+#define DCMIPP_P1FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P1FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P1FSCR_DTMODE                DCMIPP_P1FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_PIPEDIFF_Pos          (18U)
+#define DCMIPP_P1FSCR_PIPEDIFF_Msk          (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_P1FSCR_PIPEDIFF              DCMIPP_P1FSCR_PIPEDIFF_Msk                      /*!< Differentiates Pipe2 vs */
+#define DCMIPP_P1FSCR_VC_Pos                (19U)
+#define DCMIPP_P1FSCR_VC_Msk                (0x3UL << DCMIPP_P1FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P1FSCR_VC                    DCMIPP_P1FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P1FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P1FSCR_FDTF                  DCMIPP_P1FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P1FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P1FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P1FSCR_FDTFEN                DCMIPP_P1FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P1FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P1FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P1FSCR_PIPEN                 DCMIPP_P1FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P1SRCR register  *****************/
+#define DCMIPP_P1SRCR_LASTLINE_Pos          (0U)
+#define DCMIPP_P1SRCR_LASTLINE_Msk          (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1SRCR_LASTLINE              DCMIPP_P1SRCR_LASTLINE_Msk                      /*!< Number of the last line to be kept when CROPEN = 1 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos      (12U)
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk      (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos)        /*!< 0x00007000 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL          DCMIPP_P1SRCR_FIRSTLINEDEL_Msk                  /*!< Number of lines to be deleted when CROPEN = 1 */
+#define DCMIPP_P1SRCR_CROPEN_Pos            (15U)
+#define DCMIPP_P1SRCR_CROPEN_Msk            (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos)              /*!< 0x00008000 */
+#define DCMIPP_P1SRCR_CROPEN                DCMIPP_P1SRCR_CROPEN_Msk                        /*!< Crop line enable */
+
+/****************  Bit definition for DCMIPP_P1BPRCR register  ****************/
+#define DCMIPP_P1BPRCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BPRCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BPRCR_ENABLE               DCMIPP_P1BPRCR_ENABLE_Msk                       /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */
+#define DCMIPP_P1BPRCR_STRENGTH_Pos         (1U)
+#define DCMIPP_P1BPRCR_STRENGTH_Msk         (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos)           /*!< 0x0000000E */
+#define DCMIPP_P1BPRCR_STRENGTH             DCMIPP_P1BPRCR_STRENGTH_Msk                     /*!< Strength (aggressivity) of the bad pixel detection: */
+
+/****************  Bit definition for DCMIPP_P1BPRSR register  ****************/
+#define DCMIPP_P1BPRSR_BADCNT_Pos           (0U)
+#define DCMIPP_P1BPRSR_BADCNT_Msk           (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1BPRSR_BADCNT               DCMIPP_P1BPRSR_BADCNT_Msk                       /*!< Amount of detected bad pixels */
+
+/****************  Bit definition for DCMIPP_P1DECR register  *****************/
+#define DCMIPP_P1DECR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DECR_ENABLE_Msk            (0x1UL << DCMIPP_P1DECR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DECR_ENABLE                DCMIPP_P1DECR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DECR_HDEC_Pos              (1U)
+#define DCMIPP_P1DECR_HDEC_Msk              (0x3UL << DCMIPP_P1DECR_HDEC_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DECR_HDEC                  DCMIPP_P1DECR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DECR_VDEC_Pos              (3U)
+#define DCMIPP_P1DECR_VDEC_Msk              (0x3UL << DCMIPP_P1DECR_VDEC_Pos)                /*!< 0x00000018 */
+#define DCMIPP_P1DECR_VDEC                  DCMIPP_P1DECR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1BLCCR register  ****************/
+#define DCMIPP_P1BLCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BLCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BLCCR_ENABLE               DCMIPP_P1BLCCR_ENABLE_Msk                       /*!< Black level calibration */
+#define DCMIPP_P1BLCCR_BLCB_Pos             (8U)
+#define DCMIPP_P1BLCCR_BLCB_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos)              /*!< 0x0000FF00 */
+#define DCMIPP_P1BLCCR_BLCB                 DCMIPP_P1BLCCR_BLCB_Msk                         /*!< Black level calibration - Blue */
+#define DCMIPP_P1BLCCR_BLCG_Pos             (16U)
+#define DCMIPP_P1BLCCR_BLCG_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos)              /*!< 0x00FF0000 */
+#define DCMIPP_P1BLCCR_BLCG                 DCMIPP_P1BLCCR_BLCG_Msk                         /*!< Black level calibration - Green */
+#define DCMIPP_P1BLCCR_BLCR_Pos             (24U)
+#define DCMIPP_P1BLCCR_BLCR_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos)              /*!< 0xFF000000 */
+#define DCMIPP_P1BLCCR_BLCR                 DCMIPP_P1BLCCR_BLCR_Msk                         /*!< Black level calibration - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR1 register  ****************/
+#define DCMIPP_P1EXCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1EXCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1EXCR1_ENABLE               DCMIPP_P1EXCR1_ENABLE_Msk                       /*!< Exposure control (multiplication and shift) of all red, green and blue */
+#define DCMIPP_P1EXCR1_MULTR_Pos            (20U)
+#define DCMIPP_P1EXCR1_MULTR_Msk            (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR1_MULTR                DCMIPP_P1EXCR1_MULTR_Msk                        /*!< Exposure multiplier - Red */
+#define DCMIPP_P1EXCR1_SHFR_Pos             (28U)
+#define DCMIPP_P1EXCR1_SHFR_Msk             (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR1_SHFR                 DCMIPP_P1EXCR1_SHFR_Msk                         /*!< Exposure shift - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR2 register  ****************/
+#define DCMIPP_P1EXCR2_MULTB_Pos            (4U)
+#define DCMIPP_P1EXCR2_MULTB_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos)             /*!< 0x00000FF0 */
+#define DCMIPP_P1EXCR2_MULTB                DCMIPP_P1EXCR2_MULTB_Msk                        /*!< Exposure multiplier - Blue */
+#define DCMIPP_P1EXCR2_SHFB_Pos             (12U)
+#define DCMIPP_P1EXCR2_SHFB_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos)               /*!< 0x00007000 */
+#define DCMIPP_P1EXCR2_SHFB                 DCMIPP_P1EXCR2_SHFB_Msk                         /*!< Exposure shift - Blue */
+#define DCMIPP_P1EXCR2_MULTG_Pos            (20U)
+#define DCMIPP_P1EXCR2_MULTG_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR2_MULTG                DCMIPP_P1EXCR2_MULTG_Msk                        /*!< Exposure multiplier - Green */
+#define DCMIPP_P1EXCR2_SHFG_Pos             (28U)
+#define DCMIPP_P1EXCR2_SHFG_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR2_SHFG                 DCMIPP_P1EXCR2_SHFG_Msk                         /*!< Exposure shift - Green */
+
+/****************  Bit definition for DCMIPP_P1ST1CR register  ****************/
+#define DCMIPP_P1ST1CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST1CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST1CR_ENABLE               DCMIPP_P1ST1CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST1CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST1CR_BINS_Msk             (0x3UL << DCMIPP_P1ST1CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST1CR_BINS                 DCMIPP_P1ST1CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST1CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST1CR_SRC_Msk              (0x7UL << DCMIPP_P1ST1CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST1CR_SRC                  DCMIPP_P1ST1CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST1CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST1CR_MODE_Msk             (0x1UL << DCMIPP_P1ST1CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST1CR_MODE                 DCMIPP_P1ST1CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST2CR register  ****************/
+#define DCMIPP_P1ST2CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST2CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST2CR_ENABLE               DCMIPP_P1ST2CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST2CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST2CR_BINS_Msk             (0x3UL << DCMIPP_P1ST2CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST2CR_BINS                 DCMIPP_P1ST2CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST2CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST2CR_SRC_Msk              (0x7UL << DCMIPP_P1ST2CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST2CR_SRC                  DCMIPP_P1ST2CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST2CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST2CR_MODE_Msk             (0x1UL << DCMIPP_P1ST2CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST2CR_MODE                 DCMIPP_P1ST2CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST3CR register  ****************/
+#define DCMIPP_P1ST3CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST3CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST3CR_ENABLE               DCMIPP_P1ST3CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST3CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST3CR_BINS_Msk             (0x3UL << DCMIPP_P1ST3CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST3CR_BINS                 DCMIPP_P1ST3CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST3CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST3CR_SRC_Msk              (0x7UL << DCMIPP_P1ST3CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST3CR_SRC                  DCMIPP_P1ST3CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST3CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST3CR_MODE_Msk             (0x1UL << DCMIPP_P1ST3CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST3CR_MODE                 DCMIPP_P1ST3CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1STSTR register  ****************/
+#define DCMIPP_P1STSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1STSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1STSTR_HSTART               DCMIPP_P1STSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1STSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSTR_VSTART               DCMIPP_P1STSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1STSZR register  ****************/
+#define DCMIPP_P1STSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1STSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1STSZR_HSIZE                DCMIPP_P1STSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1STSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSZR_VSIZE                DCMIPP_P1STSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1STSZR_CROPEN_Pos           (31U)
+#define DCMIPP_P1STSZR_CROPEN_Msk           (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1STSZR_CROPEN               DCMIPP_P1STSZR_CROPEN_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1ST1SR register  ****************/
+#define DCMIPP_P1ST1SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST1SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST1SR_ACCU                 DCMIPP_P1ST1SR_ACCU_Msk                         /*!< Accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST2SR register  ****************/
+#define DCMIPP_P1ST2SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST2SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST2SR_ACCU                 DCMIPP_P1ST2SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST3SR register  ****************/
+#define DCMIPP_P1ST3SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST3SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST3SR_ACCU                 DCMIPP_P1ST3SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1DMCR register  *****************/
+#define DCMIPP_P1DMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DMCR_ENABLE                DCMIPP_P1DMCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DMCR_TYPE_Pos              (1U)
+#define DCMIPP_P1DMCR_TYPE_Msk              (0x3UL << DCMIPP_P1DMCR_TYPE_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DMCR_TYPE                  DCMIPP_P1DMCR_TYPE_Msk                          /*!< Raw Bayer type */
+#define DCMIPP_P1DMCR_PEAK_Pos              (16U)
+#define DCMIPP_P1DMCR_PEAK_Msk              (0x7UL << DCMIPP_P1DMCR_PEAK_Pos)                /*!< 0x00070000 */
+#define DCMIPP_P1DMCR_PEAK                  DCMIPP_P1DMCR_PEAK_Msk                          /*!< Strength of the peak detection */
+#define DCMIPP_P1DMCR_LINEV_Pos             (20U)
+#define DCMIPP_P1DMCR_LINEV_Msk             (0x7UL << DCMIPP_P1DMCR_LINEV_Pos)               /*!< 0x00700000 */
+#define DCMIPP_P1DMCR_LINEV                 DCMIPP_P1DMCR_LINEV_Msk                         /*!< Strength of the vertical line detection */
+#define DCMIPP_P1DMCR_LINEH_Pos             (24U)
+#define DCMIPP_P1DMCR_LINEH_Msk             (0x7UL << DCMIPP_P1DMCR_LINEH_Pos)               /*!< 0x07000000 */
+#define DCMIPP_P1DMCR_LINEH                 DCMIPP_P1DMCR_LINEH_Msk                         /*!< Strength of the horizontal line detection */
+#define DCMIPP_P1DMCR_EDGE_Pos              (28U)
+#define DCMIPP_P1DMCR_EDGE_Msk              (0x7UL << DCMIPP_P1DMCR_EDGE_Pos)                /*!< 0x70000000 */
+#define DCMIPP_P1DMCR_EDGE                  DCMIPP_P1DMCR_EDGE_Msk                          /*!< Strength of the edge detection */
+
+/****************  Bit definition for DCMIPP_P1CCCR register  *****************/
+#define DCMIPP_P1CCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1CCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1CCCR_ENABLE                DCMIPP_P1CCCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1CCCR_TYPE_Pos              (1U)
+#define DCMIPP_P1CCCR_TYPE_Msk              (0x1UL << DCMIPP_P1CCCR_TYPE_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1CCCR_TYPE                  DCMIPP_P1CCCR_TYPE_Msk                          /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCR_CLAMP_Pos             (2U)
+#define DCMIPP_P1CCCR_CLAMP_Msk             (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos)               /*!< 0x00000004 */
+#define DCMIPP_P1CCCR_CLAMP                 DCMIPP_P1CCCR_CLAMP_Msk                         /*!< Clamp the output samples */
+
+/****************  Bit definition for DCMIPP_P1CCRR1 register  ****************/
+#define DCMIPP_P1CCRR1_RR_Pos               (0U)
+#define DCMIPP_P1CCRR1_RR_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR1_RR                   DCMIPP_P1CCRR1_RR_Msk                           /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCRR1_RG_Pos               (16U)
+#define DCMIPP_P1CCRR1_RG_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCRR1_RG                   DCMIPP_P1CCRR1_RG_Msk                           /*!< Coefficient row 1 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCRR2 register  ****************/
+#define DCMIPP_P1CCRR2_RB_Pos               (0U)
+#define DCMIPP_P1CCRR2_RB_Msk               (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR2_RB                   DCMIPP_P1CCRR2_RB_Msk                           /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCRR2_RA_Pos               (16U)
+#define DCMIPP_P1CCRR2_RA_Msk               (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCRR2_RA                   DCMIPP_P1CCRR2_RA_Msk                           /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCGR1 register  ****************/
+#define DCMIPP_P1CCGR1_GR_Pos               (0U)
+#define DCMIPP_P1CCGR1_GR_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR1_GR                   DCMIPP_P1CCGR1_GR_Msk                           /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCGR1_GG_Pos               (16U)
+#define DCMIPP_P1CCGR1_GG_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCGR1_GG                   DCMIPP_P1CCGR1_GG_Msk                           /*!< Coefficient row 2 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCGR2 register  ****************/
+#define DCMIPP_P1CCGR2_GB_Pos               (0U)
+#define DCMIPP_P1CCGR2_GB_Msk               (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR2_GB                   DCMIPP_P1CCGR2_GB_Msk                           /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCGR2_GA_Pos               (16U)
+#define DCMIPP_P1CCGR2_GA_Msk               (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCGR2_GA                   DCMIPP_P1CCGR2_GA_Msk                           /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCBR1 register  ****************/
+#define DCMIPP_P1CCBR1_BR_Pos               (0U)
+#define DCMIPP_P1CCBR1_BR_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR1_BR                   DCMIPP_P1CCBR1_BR_Msk                           /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCBR1_BG_Pos               (16U)
+#define DCMIPP_P1CCBR1_BG_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCBR1_BG                   DCMIPP_P1CCBR1_BG_Msk                           /*!< Coefficient row 3 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCBR2 register  ****************/
+#define DCMIPP_P1CCBR2_BB_Pos               (0U)
+#define DCMIPP_P1CCBR2_BB_Msk               (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR2_BB                   DCMIPP_P1CCBR2_BB_Msk                           /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCBR2_BA_Pos               (16U)
+#define DCMIPP_P1CCBR2_BA_Msk               (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCBR2_BA                   DCMIPP_P1CCBR2_BA_Msk                           /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CTCR1 register  ****************/
+#define DCMIPP_P1CTCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1CTCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CTCR1_ENABLE               DCMIPP_P1CTCR1_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1CTCR1_LUM0_Pos             (9U)
+#define DCMIPP_P1CTCR1_LUM0_Msk             (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR1_LUM0                 DCMIPP_P1CTCR1_LUM0_Msk                         /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR2 register  ****************/
+#define DCMIPP_P1CTCR2_LUM4_Pos             (1U)
+#define DCMIPP_P1CTCR2_LUM4_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR2_LUM4                 DCMIPP_P1CTCR2_LUM4_Msk                         /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM3_Pos             (9U)
+#define DCMIPP_P1CTCR2_LUM3_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR2_LUM3                 DCMIPP_P1CTCR2_LUM3_Msk                         /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM2_Pos             (17U)
+#define DCMIPP_P1CTCR2_LUM2_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR2_LUM2                 DCMIPP_P1CTCR2_LUM2_Msk                         /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM1_Pos             (25U)
+#define DCMIPP_P1CTCR2_LUM1_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR2_LUM1                 DCMIPP_P1CTCR2_LUM1_Msk                         /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR3 register  ****************/
+#define DCMIPP_P1CTCR3_LUM8_Pos             (1U)
+#define DCMIPP_P1CTCR3_LUM8_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR3_LUM8                 DCMIPP_P1CTCR3_LUM8_Msk                         /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM7_Pos             (9U)
+#define DCMIPP_P1CTCR3_LUM7_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR3_LUM7                 DCMIPP_P1CTCR3_LUM7_Msk                         /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM6_Pos             (17U)
+#define DCMIPP_P1CTCR3_LUM6_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR3_LUM6                 DCMIPP_P1CTCR3_LUM6_Msk                         /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM5_Pos             (25U)
+#define DCMIPP_P1CTCR3_LUM5_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR3_LUM5                 DCMIPP_P1CTCR3_LUM5_Msk                         /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1FCTCR register  ****************/
+#define DCMIPP_P1FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P1FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P1FCTCR_FRATE                DCMIPP_P1FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P1FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P1FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P1FCTCR_CPTMODE              DCMIPP_P1FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P1FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P1FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P1FCTCR_CPTREQ               DCMIPP_P1FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P1CRSTR register  ****************/
+#define DCMIPP_P1CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CRSTR_HSTART               DCMIPP_P1CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSTR_VSTART               DCMIPP_P1CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CRSZR register  ****************/
+#define DCMIPP_P1CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1CRSZR_HSIZE                DCMIPP_P1CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSZR_VSIZE                DCMIPP_P1CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CRSZR_ENABLE               DCMIPP_P1CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1DCCR register  *****************/
+#define DCMIPP_P1DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1DCCR_ENABLE                DCMIPP_P1DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P1DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P1DCCR_HDEC_Msk              (0x3UL << DCMIPP_P1DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1DCCR_HDEC                  DCMIPP_P1DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P1DCCR_VDEC_Msk              (0x3UL << DCMIPP_P1DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1DCCR_VDEC                  DCMIPP_P1DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1DSCR register  *****************/
+#define DCMIPP_P1DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P1DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P1DSCR_HDIV                  DCMIPP_P1DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P1DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1DSCR_VDIV                  DCMIPP_P1DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P1DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1DSCR_ENABLE                DCMIPP_P1DSCR_ENABLE_Msk                        /*!<  Downscaler Enable */
+
+/***************  Bit definition for DCMIPP_P1DSRTIOR register  ***************/
+#define DCMIPP_P1DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P1DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P1DSRTIOR_HRATIO             DCMIPP_P1DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P1DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P1DSRTIOR_VRATIO             DCMIPP_P1DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P1DSSZR register  ****************/
+#define DCMIPP_P1DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1DSSZR_HSIZE                DCMIPP_P1DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1DSSZR_VSIZE                DCMIPP_P1DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CMRICR register  ***************/
+#define DCMIPP_P1CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P1CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P1CMRICR_ROILSZ              DCMIPP_P1CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P1CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P1CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P1CMRICR_ROI1EN              DCMIPP_P1CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P1CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P1CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P1CMRICR_ROI2EN              DCMIPP_P1CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P1CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P1CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CMRICR_ROI3EN              DCMIPP_P1CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P1CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P1CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P1CMRICR_ROI4EN              DCMIPP_P1CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P1CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P1CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P1CMRICR_ROI5EN              DCMIPP_P1CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P1CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P1CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P1CMRICR_ROI6EN              DCMIPP_P1CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P1CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P1CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P1CMRICR_ROI7EN              DCMIPP_P1CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P1CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P1CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P1CMRICR_ROI8EN              DCMIPP_P1CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P1RIxCR1 register  ***************/
+#define DCMIPP_P1RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P1RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P1RIxCR1_HSTART              DCMIPP_P1RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P1RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P1RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P1RIxCR1_CLB                 DCMIPP_P1RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P1RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P1RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P1RIxCR1_CLG                 DCMIPP_P1RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P1RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P1RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P1RIxCR1_VSTART              DCMIPP_P1RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P1RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P1RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P1RIxCR1_CLR                 DCMIPP_P1RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P1RIxCR2 register  ***************/
+#define DCMIPP_P1RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P1RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P1RIxCR2_VSIZE               DCMIPP_P1RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P1RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P1RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P1RIxCR2_HSIZE               DCMIPP_P1RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P1GMCR register  *****************/
+#define DCMIPP_P1GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos)              /*!< 0x00000001   */
+#define DCMIPP_P1GMCR_ENABLE                DCMIPP_P1GMCR_ENABLE_Msk                        /*!<  Gamma  enable*/
+
+/****************  Bit definition for DCMIPP_P1YUVCR register  ****************/
+#define DCMIPP_P1YUVCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1YUVCR_ENABLE_Msk           (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1YUVCR_ENABLE               DCMIPP_P1YUVCR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1YUVCR_TYPE_Pos             (1U)
+#define DCMIPP_P1YUVCR_TYPE_Msk             (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1YUVCR_TYPE                 DCMIPP_P1YUVCR_TYPE_Msk                         /*!< Output samples type used while CLAMP is activated */
+#define DCMIPP_P1YUVCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1YUVCR_CLAMP_Msk            (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1YUVCR_CLAMP                DCMIPP_P1YUVCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1YUVRR1 register  ****************/
+#define DCMIPP_P1YUVRR1_RR_Pos              (0U)
+#define DCMIPP_P1YUVRR1_RR_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR1_RR                  DCMIPP_P1YUVRR1_RR_Msk                          /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1YUVRR1_RG_Pos              (16U)
+#define DCMIPP_P1YUVRR1_RG_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVRR1_RG                  DCMIPP_P1YUVRR1_RG_Msk                          /*!< Coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVRR2 register  ****************/
+#define DCMIPP_P1YUVRR2_RB_Pos              (0U)
+#define DCMIPP_P1YUVRR2_RB_Msk              (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR2_RB                  DCMIPP_P1YUVRR2_RB_Msk                          /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1YUVRR2_RA_Pos              (16U)
+#define DCMIPP_P1YUVRR2_RA_Msk              (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVRR2_RA                  DCMIPP_P1YUVRR2_RA_Msk                          /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVGR1 register  ****************/
+#define DCMIPP_P1YUVGR1_GR_Pos              (0U)
+#define DCMIPP_P1YUVGR1_GR_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR1_GR                  DCMIPP_P1YUVGR1_GR_Msk                          /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1YUVGR1_GG_Pos              (16U)
+#define DCMIPP_P1YUVGR1_GG_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVGR1_GG                  DCMIPP_P1YUVGR1_GG_Msk                          /*!< Coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVGR2 register  ****************/
+#define DCMIPP_P1YUVGR2_GB_Pos              (0U)
+#define DCMIPP_P1YUVGR2_GB_Msk              (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR2_GB                  DCMIPP_P1YUVGR2_GB_Msk                          /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1YUVGR2_GA_Pos              (16U)
+#define DCMIPP_P1YUVGR2_GA_Msk              (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVGR2_GA                  DCMIPP_P1YUVGR2_GA_Msk                          /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVBR1 register  ****************/
+#define DCMIPP_P1YUVBR1_BR_Pos              (0U)
+#define DCMIPP_P1YUVBR1_BR_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR1_BR                  DCMIPP_P1YUVBR1_BR_Msk                          /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1YUVBR1_BG_Pos              (16U)
+#define DCMIPP_P1YUVBR1_BG_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVBR1_BG                  DCMIPP_P1YUVBR1_BG_Msk                          /*!< Coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVBR2 register  ****************/
+#define DCMIPP_P1YUVBR2_BB_Pos              (0U)
+#define DCMIPP_P1YUVBR2_BB_Msk              (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR2_BB                  DCMIPP_P1YUVBR2_BB_Msk                          /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1YUVBR2_BA_Pos              (16U)
+#define DCMIPP_P1YUVBR2_BA_Msk              (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVBR2_BA                  DCMIPP_P1YUVBR2_BA_Msk                          /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1PPCR register  *****************/
+#define DCMIPP_P1PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P1PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P1PPCR_FORMAT                DCMIPP_P1PPCR_FORMAT_Msk                        /*!< Memory format */
+#define DCMIPP_P1PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P1PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P1PPCR_SWAPRB                DCMIPP_P1PPCR_SWAPRB_Msk                        /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P1PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P1PPCR_LINEMULT              DCMIPP_P1PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P1PPCR_DBM_Pos               (16U)
+#define DCMIPP_P1PPCR_DBM_Msk               (0x1UL << DCMIPP_P1PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P1PPCR_DBM                   DCMIPP_P1PPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P1PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P1PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos)                /*!< 0x000E0000 */
+#define DCMIPP_P1PPCR_LMAWM                 DCMIPP_P1PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P1PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P1PPCR_LMAWE_Msk             (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos)                /*!< 0x00100000 */
+#define DCMIPP_P1PPCR_LMAWE                 DCMIPP_P1PPCR_LMAWE_Msk                           /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P1PPM0AR1 register  ***************/
+#define DCMIPP_P1PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR1_M0A                DCMIPP_P1PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM0AR2 register  ***************/
+#define DCMIPP_P1PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR2_M0A                DCMIPP_P1PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1PPM0PR register  ****************/
+#define DCMIPP_P1PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM0PR_PITCH               DCMIPP_P1PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR1 register  ***************/
+#define DCMIPP_P1PPM1AR1_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR1_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR1_M1A                DCMIPP_P1PPM1AR1_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR2 register  ***************/
+#define DCMIPP_P1PPM1AR2_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR2_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR2_M1A                DCMIPP_P1PPM1AR2_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1PR register  ****************/
+#define DCMIPP_P1PPM1PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM1PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM1PR_PITCH               DCMIPP_P1PPM1PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1STM1AR register  ****************/
+#define DCMIPP_P1STM1AR_M1A_Pos             (0U)
+#define DCMIPP_P1STM1AR_M1A_Msk             (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM1AR_M1A                 DCMIPP_P1STM1AR_M1A_Msk                         /*!< status Memory1 address register */
+
+/***************  Bit definition for DCMIPP_P1PPM2AR1 register  ***************/
+#define DCMIPP_P1PPM2AR1_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR1_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR1_M2A                DCMIPP_P1PPM2AR1_M2A_Msk                        /*!< Memory2 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM2AR2 register  ***************/
+#define DCMIPP_P1PPM2AR2_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR2_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR2_M2A                DCMIPP_P1PPM2AR2_M2A_Msk                        /*!< Memory2 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1STM2AR register  ****************/
+#define DCMIPP_P1STM2AR_M2A_Pos             (0U)
+#define DCMIPP_P1STM2AR_M2A_Msk             (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM2AR_M2A                 DCMIPP_P1STM2AR_M2A_Msk                         /*!< status Memory2 address register */
+
+/*****************  Bit definition for DCMIPP_P1IER register  *****************/
+#define DCMIPP_P1IER_LINEIE_Pos             (0U)
+#define DCMIPP_P1IER_LINEIE_Msk             (0x1UL << DCMIPP_P1IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1IER_LINEIE                 DCMIPP_P1IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P1IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P1IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1IER_FRAMEIE                DCMIPP_P1IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P1IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P1IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1IER_VSYNCIE                DCMIPP_P1IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P1IER_OVRIE_Pos              (7U)
+#define DCMIPP_P1IER_OVRIE_Msk              (0x1UL << DCMIPP_P1IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1IER_OVRIE                  DCMIPP_P1IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P1SR register  ******************/
+#define DCMIPP_P1SR_LINEF_Pos               (0U)
+#define DCMIPP_P1SR_LINEF_Msk               (0x1UL << DCMIPP_P1SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P1SR_LINEF                   DCMIPP_P1SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P1SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P1SR_FRAMEF_Msk              (0x1UL << DCMIPP_P1SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1SR_FRAMEF                  DCMIPP_P1SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P1SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P1SR_VSYNCF_Msk              (0x1UL << DCMIPP_P1SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P1SR_VSYNCF                  DCMIPP_P1SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P1SR_OVRF_Pos                (7U)
+#define DCMIPP_P1SR_OVRF_Msk                (0x1UL << DCMIPP_P1SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P1SR_OVRF                    DCMIPP_P1SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P1SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P1SR_LSTLINE_Msk             (0x1UL << DCMIPP_P1SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P1SR_LSTLINE                 DCMIPP_P1SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P1SR_LSTFRM_Msk              (0x1UL << DCMIPP_P1SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P1SR_LSTFRM                  DCMIPP_P1SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_CPTACT_Pos              (23U)
+#define DCMIPP_P1SR_CPTACT_Msk              (0x1UL << DCMIPP_P1SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P1SR_CPTACT                  DCMIPP_P1SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P1FCR register  *****************/
+#define DCMIPP_P1FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P1FCR_CLINEF_Msk             (0x1UL << DCMIPP_P1FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1FCR_CLINEF                 DCMIPP_P1FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P1FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1FCR_CFRAMEF                DCMIPP_P1FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P1FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1FCR_CVSYNCF                DCMIPP_P1FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P1FCR_COVRF_Pos              (7U)
+#define DCMIPP_P1FCR_COVRF_Msk              (0x1UL << DCMIPP_P1FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1FCR_COVRF                  DCMIPP_P1FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P1CFSCR register  ****************/
+#define DCMIPP_P1CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P1CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P1CFSCR_DTIDA                DCMIPP_P1CFSCR_DTIDA_Msk                        /*!< Current Data type ID A */
+#define DCMIPP_P1CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P1CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P1CFSCR_DTIDB                DCMIPP_P1CFSCR_DTIDB_Msk                        /*!< Current Data type ID B */
+#define DCMIPP_P1CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P1CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P1CFSCR_DTMODE               DCMIPP_P1CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P1CFSCR_PIPEDIFF_Pos         (18U)
+#define DCMIPP_P1CFSCR_PIPEDIFF_Msk         (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CFSCR_PIPEDIFF             DCMIPP_P1CFSCR_PIPEDIFF_Msk                     /*!< Current differentiates Pipe2 vs */
+#define DCMIPP_P1CFSCR_VC_Pos               (19U)
+#define DCMIPP_P1CFSCR_VC_Msk               (0x3UL << DCMIPP_P1CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P1CFSCR_VC                   DCMIPP_P1CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P1CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P1CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P1CFSCR_FDTF                 DCMIPP_P1CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P1CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P1CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P1CFSCR_FDTFEN               DCMIPP_P1CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P1CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P1CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1CFSCR_PIPEN                DCMIPP_P1CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P1CBPRCR register  ****************/
+#define DCMIPP_P1CBPRCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBPRCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBPRCR_ENABLE              DCMIPP_P1CBPRCR_ENABLE_Msk                      /*!< Current status of enable bit */
+#define DCMIPP_P1CBPRCR_STRENGTH_Pos        (1U)
+#define DCMIPP_P1CBPRCR_STRENGTH_Msk        (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos)          /*!< 0x0000000E */
+#define DCMIPP_P1CBPRCR_STRENGTH            DCMIPP_P1CBPRCR_STRENGTH_Msk                    /*!< Current strength (aggressivity) of the bad pixel detection: */
+
+/***************  Bit definition for DCMIPP_P1CBLCCR register  ****************/
+#define DCMIPP_P1CBLCCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBLCCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBLCCR_ENABLE              DCMIPP_P1CBLCCR_ENABLE_Msk                      /*!< For current black level calibration */
+#define DCMIPP_P1CBLCCR_BLCB_Pos            (8U)
+#define DCMIPP_P1CBLCCR_BLCB_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos)             /*!< 0x0000FF00 */
+#define DCMIPP_P1CBLCCR_BLCB                DCMIPP_P1CBLCCR_BLCB_Msk                        /*!< Current black level calibration - Blue */
+#define DCMIPP_P1CBLCCR_BLCG_Pos            (16U)
+#define DCMIPP_P1CBLCCR_BLCG_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos)             /*!< 0x00FF0000 */
+#define DCMIPP_P1CBLCCR_BLCG                DCMIPP_P1CBLCCR_BLCG_Msk                        /*!< Current black level calibration - Green */
+#define DCMIPP_P1CBLCCR_BLCR_Pos            (24U)
+#define DCMIPP_P1CBLCCR_BLCR_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos)             /*!< 0xFF000000 */
+#define DCMIPP_P1CBLCCR_BLCR                DCMIPP_P1CBLCCR_BLCR_Msk                        /*!< Current black level calibration - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR1 register  ****************/
+#define DCMIPP_P1CEXCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CEXCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CEXCR1_ENABLE              DCMIPP_P1CEXCR1_ENABLE_Msk                      /*!< for exposure control (multiplication and shift) */
+#define DCMIPP_P1CEXCR1_MULTR_Pos           (20U)
+#define DCMIPP_P1CEXCR1_MULTR_Msk           (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR1_MULTR               DCMIPP_P1CEXCR1_MULTR_Msk                       /*!< Current exposure multiplier - Red */
+#define DCMIPP_P1CEXCR1_SHFR_Pos            (28U)
+#define DCMIPP_P1CEXCR1_SHFR_Msk            (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR1_SHFR                DCMIPP_P1CEXCR1_SHFR_Msk                        /*!< Current exposure shift - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR2 register  ****************/
+#define DCMIPP_P1CEXCR2_MULTB_Pos           (4U)
+#define DCMIPP_P1CEXCR2_MULTB_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos)            /*!< 0x00000FF0 */
+#define DCMIPP_P1CEXCR2_MULTB               DCMIPP_P1CEXCR2_MULTB_Msk                       /*!< Current exposure multiplier - Blue */
+#define DCMIPP_P1CEXCR2_SHFB_Pos            (12U)
+#define DCMIPP_P1CEXCR2_SHFB_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos)              /*!< 0x00007000 */
+#define DCMIPP_P1CEXCR2_SHFB                DCMIPP_P1CEXCR2_SHFB_Msk                        /*!< Current exposure shift - Blue */
+#define DCMIPP_P1CEXCR2_MULTG_Pos           (20U)
+#define DCMIPP_P1CEXCR2_MULTG_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR2_MULTG               DCMIPP_P1CEXCR2_MULTG_Msk                       /*!< Current exposure multiplier - Green */
+#define DCMIPP_P1CEXCR2_SHFG_Pos            (28U)
+#define DCMIPP_P1CEXCR2_SHFG_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR2_SHFG                DCMIPP_P1CEXCR2_SHFG_Msk                        /*!< Current exposure shift - Green */
+
+/***************  Bit definition for DCMIPP_P1CST1CR register  ****************/
+#define DCMIPP_P1CST1CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST1CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST1CR_ENABLE              DCMIPP_P1CST1CR_ENABLE_Msk                      /*!< Current enable bit value */
+#define DCMIPP_P1CST1CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST1CR_BINS_Msk            (0x3UL << DCMIPP_P1CST1CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST1CR_BINS                DCMIPP_P1CST1CR_BINS_Msk                        /*!< Current bin definition */
+#define DCMIPP_P1CST1CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST1CR_SRC_Msk             (0x7UL << DCMIPP_P1CST1CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST1CR_SRC                 DCMIPP_P1CST1CR_SRC_Msk                         /*!< Current source of statistics */
+#define DCMIPP_P1CST1CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST1CR_MODE_Msk            (0x1UL << DCMIPP_P1CST1CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST1CR_MODE                DCMIPP_P1CST1CR_MODE_Msk                        /*!< Current statistics mode */
+#define DCMIPP_P1CST1CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST1CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST1CR_ACCU                DCMIPP_P1CST1CR_ACCU_Msk                        /*!< Current accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST2CR register  ****************/
+#define DCMIPP_P1CST2CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST2CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST2CR_ENABLE              DCMIPP_P1CST2CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST2CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST2CR_BINS_Msk            (0x3UL << DCMIPP_P1CST2CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST2CR_BINS                DCMIPP_P1CST2CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST2CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST2CR_SRC_Msk             (0x7UL << DCMIPP_P1CST2CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST2CR_SRC                 DCMIPP_P1CST2CR_SRC_Msk                         /*!< source of stat */
+#define DCMIPP_P1CST2CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST2CR_MODE_Msk            (0x1UL << DCMIPP_P1CST2CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST2CR_MODE                DCMIPP_P1CST2CR_MODE_Msk                        /*!< statistics mode */
+#define DCMIPP_P1CST2CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST2CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST2CR_ACCU                DCMIPP_P1CST2CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST3CR register  ****************/
+#define DCMIPP_P1CST3CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST3CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST3CR_ENABLE              DCMIPP_P1CST3CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST3CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST3CR_BINS_Msk            (0x3UL << DCMIPP_P1CST3CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST3CR_BINS                DCMIPP_P1CST3CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST3CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST3CR_SRC_Msk             (0x7UL << DCMIPP_P1CST3CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST3CR_SRC                 DCMIPP_P1CST3CR_SRC_Msk                         /*!< Statistics source */
+#define DCMIPP_P1CST3CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST3CR_MODE_Msk            (0x1UL << DCMIPP_P1CST3CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST3CR_MODE                DCMIPP_P1CST3CR_MODE_Msk                        /*!< Statistics mode */
+#define DCMIPP_P1CST3CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST3CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST3CR_ACCU                DCMIPP_P1CST3CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CSTSTR register  ****************/
+#define DCMIPP_P1CSTSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CSTSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSTR_HSTART              DCMIPP_P1CSTSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CSTSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSTR_VSTART              DCMIPP_P1CSTSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CSTSZR register  ****************/
+#define DCMIPP_P1CSTSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CSTSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSZR_HSIZE               DCMIPP_P1CSTSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CSTSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSZR_VSIZE               DCMIPP_P1CSTSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CSTSZR_CROPEN_Pos          (31U)
+#define DCMIPP_P1CSTSZR_CROPEN_Msk          (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CSTSZR_CROPEN              DCMIPP_P1CSTSZR_CROPEN_Msk                      /*!< Current CROPEN bit value */
+
+/****************  Bit definition for DCMIPP_P1CCCCR register  ****************/
+#define DCMIPP_P1CCCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CCCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CCCCR_ENABLE               DCMIPP_P1CCCCR_ENABLE_Msk                       /*!< This bit indicates the current value applied */
+#define DCMIPP_P1CCCCR_TYPE_Pos             (1U)
+#define DCMIPP_P1CCCCR_TYPE_Msk             (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1CCCCR_TYPE                 DCMIPP_P1CCCCR_TYPE_Msk                         /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1CCCCR_CLAMP_Msk            (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1CCCCR_CLAMP                DCMIPP_P1CCCCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1CCCRR1 register  ****************/
+#define DCMIPP_P1CCCRR1_RR_Pos              (0U)
+#define DCMIPP_P1CCCRR1_RR_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR1_RR                  DCMIPP_P1CCCRR1_RR_Msk                          /*!< Current coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCCRR1_RG_Pos              (16U)
+#define DCMIPP_P1CCCRR1_RG_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCRR1_RG                  DCMIPP_P1CCCRR1_RG_Msk                          /*!< Current coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCRR2 register  ****************/
+#define DCMIPP_P1CCCRR2_RB_Pos              (0U)
+#define DCMIPP_P1CCCRR2_RB_Msk              (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR2_RB                  DCMIPP_P1CCCRR2_RB_Msk                          /*!< Current coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCCRR2_RA_Pos              (16U)
+#define DCMIPP_P1CCCRR2_RA_Msk              (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCRR2_RA                  DCMIPP_P1CCCRR2_RA_Msk                          /*!< Current coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCGR1 register  ****************/
+#define DCMIPP_P1CCCGR1_GR_Pos              (0U)
+#define DCMIPP_P1CCCGR1_GR_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR1_GR                  DCMIPP_P1CCCGR1_GR_Msk                          /*!< Current coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCCGR1_GG_Pos              (16U)
+#define DCMIPP_P1CCCGR1_GG_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCGR1_GG                  DCMIPP_P1CCCGR1_GG_Msk                          /*!< Current coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCGR2 register  ****************/
+#define DCMIPP_P1CCCGR2_GB_Pos              (0U)
+#define DCMIPP_P1CCCGR2_GB_Msk              (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR2_GB                  DCMIPP_P1CCCGR2_GB_Msk                          /*!< Current coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCCGR2_GA_Pos              (16U)
+#define DCMIPP_P1CCCGR2_GA_Msk              (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCGR2_GA                  DCMIPP_P1CCCGR2_GA_Msk                          /*!< Current coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCBR1 register  ****************/
+#define DCMIPP_P1CCCBR1_BR_Pos              (0U)
+#define DCMIPP_P1CCCBR1_BR_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR1_BR                  DCMIPP_P1CCCBR1_BR_Msk                          /*!< Current coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCCBR1_BG_Pos              (16U)
+#define DCMIPP_P1CCCBR1_BG_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCBR1_BG                  DCMIPP_P1CCCBR1_BG_Msk                          /*!< Current coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCBR2 register  ****************/
+#define DCMIPP_P1CCCBR2_BB_Pos              (0U)
+#define DCMIPP_P1CCCBR2_BB_Msk              (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR2_BB                  DCMIPP_P1CCCBR2_BB_Msk                          /*!< Current coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCCBR2_BA_Pos              (16U)
+#define DCMIPP_P1CCCBR2_BA_Msk              (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCBR2_BA                  DCMIPP_P1CCCBR2_BA_Msk                          /*!< Current coefficient row 3 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR1 register  ****************/
+#define DCMIPP_P1CCTCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CCTCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CCTCR1_ENABLE              DCMIPP_P1CCTCR1_ENABLE_Msk                      /*!< Current ENABLE bit value */
+#define DCMIPP_P1CCTCR1_LUM0_Pos            (9U)
+#define DCMIPP_P1CCTCR1_LUM0_Msk            (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR1_LUM0                DCMIPP_P1CCTCR1_LUM0_Msk                        /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR2 register  ****************/
+#define DCMIPP_P1CCTCR2_LUM4_Pos            (1U)
+#define DCMIPP_P1CCTCR2_LUM4_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR2_LUM4                DCMIPP_P1CCTCR2_LUM4_Msk                        /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM3_Pos            (9U)
+#define DCMIPP_P1CCTCR2_LUM3_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR2_LUM3                DCMIPP_P1CCTCR2_LUM3_Msk                        /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM2_Pos            (17U)
+#define DCMIPP_P1CCTCR2_LUM2_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR2_LUM2                DCMIPP_P1CCTCR2_LUM2_Msk                        /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM1_Pos            (25U)
+#define DCMIPP_P1CCTCR2_LUM1_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR2_LUM1                DCMIPP_P1CCTCR2_LUM1_Msk                        /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR3 register  ****************/
+#define DCMIPP_P1CCTCR3_LUM8_Pos            (1U)
+#define DCMIPP_P1CCTCR3_LUM8_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR3_LUM8                DCMIPP_P1CCTCR3_LUM8_Msk                        /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM7_Pos            (9U)
+#define DCMIPP_P1CCTCR3_LUM7_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR3_LUM7                DCMIPP_P1CCTCR3_LUM7_Msk                        /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM6_Pos            (17U)
+#define DCMIPP_P1CCTCR3_LUM6_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR3_LUM6                DCMIPP_P1CCTCR3_LUM6_Msk                        /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM5_Pos            (25U)
+#define DCMIPP_P1CCTCR3_LUM5_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR3_LUM5                DCMIPP_P1CCTCR3_LUM5_Msk                        /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CFCTCR register  ****************/
+#define DCMIPP_P1CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P1CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P1CFCTCR_FRATE               DCMIPP_P1CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P1CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P1CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P1CFCTCR_CPTMODE             DCMIPP_P1CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P1CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P1CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P1CFCTCR_CPTREQ              DCMIPP_P1CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P1CCRSTR register  ****************/
+#define DCMIPP_P1CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSTR_HSTART              DCMIPP_P1CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSTR_VSTART              DCMIPP_P1CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CCRSZR register  ****************/
+#define DCMIPP_P1CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSZR_HSIZE               DCMIPP_P1CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSZR_VSIZE               DCMIPP_P1CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P1CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CCRSZR_ENABLE              DCMIPP_P1CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P1CDCCR register  *****************/
+#define DCMIPP_P1CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CDCCR_ENABLE               DCMIPP_P1CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P1CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P1CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1CDCCR_HDEC                 DCMIPP_P1CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P1CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P1CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1CDCCR_VDEC                 DCMIPP_P1CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1CDSCR register  ****************/
+#define DCMIPP_P1CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P1CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P1CDSCR_HDIV                 DCMIPP_P1CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P1CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P1CDSCR_VDIV                 DCMIPP_P1CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CDSCR_ENABLE               DCMIPP_P1CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P1CDSRTIOR register  ***************/
+#define DCMIPP_P1CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P1CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P1CDSRTIOR_HRATIO            DCMIPP_P1CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P1CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P1CDSRTIOR_VRATIO            DCMIPP_P1CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P1CDSSZR register  ****************/
+#define DCMIPP_P1CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CDSSZR_HSIZE               DCMIPP_P1CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CDSSZR_VSIZE               DCMIPP_P1CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CPPCR register  ****************/
+#define DCMIPP_P1CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P1CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P1CPPCR_FORMAT               DCMIPP_P1CPPCR_FORMAT_Msk                       /*!< Memory format */
+#define DCMIPP_P1CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P1CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P1CPPCR_SWAPRB               DCMIPP_P1CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P1CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P1CPPCR_LINEMULT             DCMIPP_P1CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+
+/**************  Bit definition for DCMIPP_P1CPPM0AR1 register  ***************/
+#define DCMIPP_P1CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P1CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM0AR1_M0A               DCMIPP_P1CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM0PR register  ***************/
+#define DCMIPP_P1CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM0PR_PITCH              DCMIPP_P1CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM1AR1 register  ***************/
+#define DCMIPP_P1CPPM1AR1_M1A_Pos           (0U)
+#define DCMIPP_P1CPPM1AR1_M1A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM1AR1_M1A               DCMIPP_P1CPPM1AR1_M1A_Msk                       /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM1PR register  ***************/
+#define DCMIPP_P1CPPM1PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM1PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM1PR_PITCH              DCMIPP_P1CPPM1PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM2AR1 register  ***************/
+#define DCMIPP_P1CPPM2AR1_M2A_Pos           (0U)
+#define DCMIPP_P1CPPM2AR1_M2A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM2AR1_M2A               DCMIPP_P1CPPM2AR1_M2A_Msk                       /*!< Memory 2 address */
+
+/****************  Bit definition for DCMIPP_P2FSCR register  *****************/
+#define DCMIPP_P2FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P2FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2FSCR_DTIDA                 DCMIPP_P2FSCR_DTIDA_Msk                         /*!< Data type ID */
+#define DCMIPP_P2FSCR_VC_Pos                (19U)
+#define DCMIPP_P2FSCR_VC_Msk                (0x3UL << DCMIPP_P2FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P2FSCR_VC                    DCMIPP_P2FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P2FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P2FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P2FSCR_FDTF                  DCMIPP_P2FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P2FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P2FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P2FSCR_FDTFEN                DCMIPP_P2FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P2FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P2FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P2FSCR_PIPEN                 DCMIPP_P2FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P2FCTCR register  ****************/
+#define DCMIPP_P2FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P2FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P2FCTCR_FRATE                DCMIPP_P2FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P2FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P2FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P2FCTCR_CPTMODE              DCMIPP_P2FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P2FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P2FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P2FCTCR_CPTREQ               DCMIPP_P2FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P2CRSTR register  ****************/
+#define DCMIPP_P2CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P2CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CRSTR_HSTART               DCMIPP_P2CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P2CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSTR_VSTART               DCMIPP_P2CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CRSZR register  ****************/
+#define DCMIPP_P2CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2CRSZR_HSIZE                DCMIPP_P2CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSZR_VSIZE                DCMIPP_P2CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CRSZR_ENABLE               DCMIPP_P2CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P2DCCR register  *****************/
+#define DCMIPP_P2DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P2DCCR_ENABLE                DCMIPP_P2DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P2DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P2DCCR_HDEC_Msk              (0x3UL << DCMIPP_P2DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P2DCCR_HDEC                  DCMIPP_P2DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P2DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P2DCCR_VDEC_Msk              (0x3UL << DCMIPP_P2DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P2DCCR_VDEC                  DCMIPP_P2DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2DSCR register  *****************/
+#define DCMIPP_P2DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P2DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P2DSCR_HDIV                  DCMIPP_P2DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P2DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P2DSCR_VDIV                  DCMIPP_P2DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P2DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2DSCR_ENABLE                DCMIPP_P2DSCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2DSRTIOR register  ***************/
+#define DCMIPP_P2DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P2DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P2DSRTIOR_HRATIO             DCMIPP_P2DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P2DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P2DSRTIOR_VRATIO             DCMIPP_P2DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P2DSSZR register  ****************/
+#define DCMIPP_P2DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2DSSZR_HSIZE                DCMIPP_P2DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2DSSZR_VSIZE                DCMIPP_P2DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2GMCR register  *****************/
+#define DCMIPP_P2GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P2GMCR_ENABLE                DCMIPP_P2GMCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2CMRICR register  ***************/
+#define DCMIPP_P2CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P2CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P2CMRICR_ROILSZ              DCMIPP_P2CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P2CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P2CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P2CMRICR_ROI1EN              DCMIPP_P2CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P2CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P2CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P2CMRICR_ROI2EN              DCMIPP_P2CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P2CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P2CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P2CMRICR_ROI3EN              DCMIPP_P2CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P2CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P2CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P2CMRICR_ROI4EN              DCMIPP_P2CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P2CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P2CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P2CMRICR_ROI5EN              DCMIPP_P2CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P2CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P2CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P2CMRICR_ROI6EN              DCMIPP_P2CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P2CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P2CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P2CMRICR_ROI7EN              DCMIPP_P2CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P2CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P2CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P2CMRICR_ROI8EN              DCMIPP_P2CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P2RIxCR1 register  ***************/
+#define DCMIPP_P2RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P2RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P2RIxCR1_HSTART              DCMIPP_P2RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P2RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P2RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P2RIxCR1_CLB                 DCMIPP_P2RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P2RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P2RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P2RIxCR1_CLG                 DCMIPP_P2RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P2RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P2RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P2RIxCR1_VSTART              DCMIPP_P2RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P2RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P2RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P2RIxCR1_CLR                 DCMIPP_P2RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P2RIxCR2 register  ***************/
+#define DCMIPP_P2RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P2RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P2RIxCR2_VSIZE               DCMIPP_P2RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P2RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P2RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P2RIxCR2_HSIZE               DCMIPP_P2RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P2PPCR register  *****************/
+#define DCMIPP_P2PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P2PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P2PPCR_FORMAT                DCMIPP_P2PPCR_FORMAT_Msk                         /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P2PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P2PPCR_SWAPRB                DCMIPP_P2PPCR_SWAPRB_Msk                         /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P2PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P2PPCR_LINEMULT              DCMIPP_P2PPCR_LINEMULT_Msk                       /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2PPCR_DBM_Pos               (16U)
+#define DCMIPP_P2PPCR_DBM_Msk               (0x1UL << DCMIPP_P2PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P2PPCR_DBM                   DCMIPP_P2PPCR_DBM_Msk                            /*!< Double buffer mode */
+#define DCMIPP_P2PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P2PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos)               /*!< 0x000E0000 */
+#define DCMIPP_P2PPCR_LMAWM                 DCMIPP_P2PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P2PPCR_LMAWE_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos)               /*!< 0x00100000 */
+#define DCMIPP_P2PPCR_LMAWE                 DCMIPP_P2PPCR_LMAWE_Msk                          /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR1 register  ***************/
+#define DCMIPP_P2PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR1_M0A                DCMIPP_P2PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1 */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR2 register  ***************/
+#define DCMIPP_P2PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR2_M0A                DCMIPP_P2PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2*/
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P2PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P2PPM0PR_PITCH               DCMIPP_P2PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2STM0AR_Pos                 (0U)
+#define DCMIPP_P2STM0AR_Msk                 (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P2STM0AR                     DCMIPP_P2STM0AR_Msk                             /*!< Pipe2 status Memory0 address register */
+
+/*****************  Bit definition for DCMIPP_P2IER register  *****************/
+#define DCMIPP_P2IER_LINEIE_Pos             (0U)
+#define DCMIPP_P2IER_LINEIE_Msk             (0x1UL << DCMIPP_P2IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2IER_LINEIE                 DCMIPP_P2IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P2IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P2IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2IER_FRAMEIE                DCMIPP_P2IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P2IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P2IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2IER_VSYNCIE                DCMIPP_P2IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P2IER_OVRIE_Pos              (7U)
+#define DCMIPP_P2IER_OVRIE_Msk              (0x1UL << DCMIPP_P2IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2IER_OVRIE                  DCMIPP_P2IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P2SR register  ******************/
+#define DCMIPP_P2SR_LINEF_Pos               (0U)
+#define DCMIPP_P2SR_LINEF_Msk               (0x1UL << DCMIPP_P2SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P2SR_LINEF                   DCMIPP_P2SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P2SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P2SR_FRAMEF_Msk              (0x1UL << DCMIPP_P2SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P2SR_FRAMEF                  DCMIPP_P2SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P2SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P2SR_VSYNCF_Msk              (0x1UL << DCMIPP_P2SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P2SR_VSYNCF                  DCMIPP_P2SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P2SR_OVRF_Pos                (7U)
+#define DCMIPP_P2SR_OVRF_Msk                (0x1UL << DCMIPP_P2SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P2SR_OVRF                    DCMIPP_P2SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P2SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P2SR_LSTLINE_Msk             (0x1UL << DCMIPP_P2SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P2SR_LSTLINE                 DCMIPP_P2SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P2SR_LSTFRM_Msk              (0x1UL << DCMIPP_P2SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P2SR_LSTFRM                  DCMIPP_P2SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_CPTACT_Pos              (23U)
+#define DCMIPP_P2SR_CPTACT_Msk              (0x1UL << DCMIPP_P2SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P2SR_CPTACT                  DCMIPP_P2SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P2FCR register  *****************/
+#define DCMIPP_P2FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P2FCR_CLINEF_Msk             (0x1UL << DCMIPP_P2FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2FCR_CLINEF                 DCMIPP_P2FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P2FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2FCR_CFRAMEF                DCMIPP_P2FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P2FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2FCR_CVSYNCF                DCMIPP_P2FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P2FCR_COVRF_Pos              (7U)
+#define DCMIPP_P2FCR_COVRF_Msk              (0x1UL << DCMIPP_P2FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2FCR_COVRF                  DCMIPP_P2FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P2CFSCR register  ****************/
+#define DCMIPP_P2CFSCR_DTID_Pos             (0U)
+#define DCMIPP_P2CFSCR_DTID_Msk             (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2CFSCR_DTID                 DCMIPP_P2CFSCR_DTID_Msk                         /*!< Current Data type ID */
+#define DCMIPP_P2CFSCR_VC_Pos               (19U)
+#define DCMIPP_P2CFSCR_VC_Msk               (0x3UL << DCMIPP_P2CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P2CFSCR_VC                   DCMIPP_P2CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P2CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P2CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P2CFSCR_FDTF                 DCMIPP_P2CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P2CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P2CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P2CFSCR_FDTFEN               DCMIPP_P2CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P2CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P2CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2CFSCR_PIPEN                DCMIPP_P2CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P2CFCTCR register  ****************/
+#define DCMIPP_P2CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P2CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P2CFCTCR_FRATE               DCMIPP_P2CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P2CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P2CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P2CFCTCR_CPTMODE             DCMIPP_P2CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P2CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P2CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P2CFCTCR_CPTREQ              DCMIPP_P2CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P2CCRSTR register  ****************/
+#define DCMIPP_P2CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P2CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSTR_HSTART              DCMIPP_P2CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P2CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSTR_VSTART              DCMIPP_P2CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P2CCRSZR register  ****************/
+#define DCMIPP_P2CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSZR_HSIZE               DCMIPP_P2CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSZR_VSIZE               DCMIPP_P2CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P2CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P2CCRSZR_ENABLE              DCMIPP_P2CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P2CDCCR register  *****************/
+#define DCMIPP_P2CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P2CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P2CDCCR_ENABLE               DCMIPP_P2CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P2CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P2CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos)              /*!< 0x00000006 */
+#define DCMIPP_P2CDCCR_HDEC                 DCMIPP_P2CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P2CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P2CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos)              /*!< 0x00000018 */
+#define DCMIPP_P2CDCCR_VDEC                 DCMIPP_P2CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2CDSCR register  ****************/
+#define DCMIPP_P2CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P2CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P2CDSCR_HDIV                 DCMIPP_P2CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P2CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P2CDSCR_VDIV                 DCMIPP_P2CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CDSCR_ENABLE               DCMIPP_P2CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P2CDSRTIOR register  ***************/
+#define DCMIPP_P2CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P2CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P2CDSRTIOR_HRATIO            DCMIPP_P2CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P2CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P2CDSRTIOR_VRATIO            DCMIPP_P2CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P2CDSSZR register  ****************/
+#define DCMIPP_P2CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CDSSZR_HSIZE               DCMIPP_P2CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CDSSZR_VSIZE               DCMIPP_P2CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CPPCR register  ****************/
+#define DCMIPP_P2CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P2CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P2CPPCR_FORMAT               DCMIPP_P2CPPCR_FORMAT_Msk                       /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P2CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P2CPPCR_SWAPRB               DCMIPP_P2CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P2CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P2CPPCR_LINEMULT             DCMIPP_P2CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P2CPPCR_DBM_Msk              (0x1UL << DCMIPP_P2CPPCR_DBM_Pos)                /*!< 0x00010000 */
+#define DCMIPP_P2CPPCR_DBM                  DCMIPP_P2CPPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P2CPPCR_LMAWM_Pos            (17U)
+#define DCMIPP_P2CPPCR_LMAWM_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos)              /*!< 0x000E0000 */
+#define DCMIPP_P2CPPCR_LMAWM                DCMIPP_P2CPPCR_LMAWM_Msk                         /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2CPPCR_LMAWE_Pos            (20U)
+#define DCMIPP_P2CPPCR_LMAWE_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos)              /*!< 0x00100000 */
+#define DCMIPP_P2CPPCR_LMAWE                DCMIPP_P2CPPCR_LMAWE_Msk                         /*!< Line multi address wrapping enable */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR1 register  ***************/
+#define DCMIPP_P2CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR1_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR2 register  ***************/
+#define DCMIPP_P2CPPM0AR2_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR2_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR2_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address Register 2 */
+
+/***************  Bit definition for DCMIPP_P2CPPM0PR register  ***************/
+#define DCMIPP_P2CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P2CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P2CPPM0PR_PITCH              DCMIPP_P2CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/****************  Bit definition for DCMIPP_HWCFGR2 register  ****************/
+#define DCMIPP_HWCFGR2_VPFT_Pos             (0U)
+#define DCMIPP_HWCFGR2_VPFT_Msk             (0x7U << DCMIPP_HWCFGR2_VPFT_Pos)               /*!< 0x00000007 */
+#define DCMIPP_HWCFGR2_VPFT                 DCMIPP_HWCFGR2_VPFT_Msk                         /*!< Virtual pipe function */
+#define DCMIPP_HWCFGR2_DBMFT_Pos            (4U)
+#define DCMIPP_HWCFGR2_DBMFT_Msk            (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos)              /*!< 0x00000010 */
+#define DCMIPP_HWCFGR2_DBMFT                DCMIPP_HWCFGR2_DBMFT_Msk                        /*!< Double buffer mode featured */
+#define DCMIPP_HWCFGR2_PROCCLK_Pos          (8U)
+#define DCMIPP_HWCFGR2_PROCCLK_Msk          (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos)            /*!< 0x00000100 */
+#define DCMIPP_HWCFGR2_PROCCLK              DCMIPP_HWCFGR2_PROCCLK_Msk                      /*!< Processing clock linked to AXI clock featured */
+#define DCMIPP_HWCFGR2_ADDMOD_Pos           (12U)
+#define DCMIPP_HWCFGR2_ADDMOD_Msk           (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR2_ADDMOD               DCMIPP_HWCFGR2_ADDMOD_Msk                       /*!< Address modulo computation to access a small buffer in streaming featured */
+#define DCMIPP_HWCFGR2_DEC1_Pos             (16U)
+#define DCMIPP_HWCFGR2_DEC1_Msk             (0x1U << DCMIPP_HWCFGR2_DEC1_Pos)               /*!< 0x00010000 */
+#define DCMIPP_HWCFGR2_DEC1                 DCMIPP_HWCFGR2_DEC1_Msk                         /*!< Decimation on Pipe1 before downsize */
+#define DCMIPP_HWCFGR2_DEC2_Pos             (17U)
+#define DCMIPP_HWCFGR2_DEC2_Msk             (0x1U << DCMIPP_HWCFGR2_DEC2_Pos)               /*!< 0x00020000 */
+#define DCMIPP_HWCFGR2_DEC2                 DCMIPP_HWCFGR2_DEC2_Msk                         /*!< Decimation on Pipe2 before downsize */
+#define DCMIPP_HWCFGR2_MCU_Pos              (20U)
+#define DCMIPP_HWCFGR2_MCU_Msk              (0x1U << DCMIPP_HWCFGR2_MCU_Pos)                /*!< 0x00100000 */
+#define DCMIPP_HWCFGR2_MCU                  DCMIPP_HWCFGR2_MCU_Msk                          /*!< Macroblock unit as pixel format  */
+#define DCMIPP_HWCFGR2_TPG_Pos              (24U)
+#define DCMIPP_HWCFGR2_TPG_Msk              (0x1U << DCMIPP_HWCFGR2_TPG_Pos)                /*!< 0x01000000 */
+#define DCMIPP_HWCFGR2_TPG                  DCMIPP_HWCFGR2_TPG_Msk                          /*!< Test Pattern Generator */
+#define DCMIPP_HWCFGR2_STV_Pos              (28U)
+#define DCMIPP_HWCFGR2_STV_Msk              (0x1U << DCMIPP_HWCFGR2_STV_Pos)                /*!< 0x10000000 */
+#define DCMIPP_HWCFGR2_STV                  DCMIPP_HWCFGR2_STV_Msk                          /*!< Statistic Version */
+
+/****************  Bit definition for DCMIPP_HWCFGR1 register  ****************/
+#define DCMIPP_HWCFGR1_CSIFT_Pos            (0U)
+#define DCMIPP_HWCFGR1_CSIFT_Msk            (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos)              /*!< 0x00000001 */
+#define DCMIPP_HWCFGR1_CSIFT                DCMIPP_HWCFGR1_CSIFT_Msk                        /*!< CSI2 host protocol compliant */
+#define DCMIPP_HWCFGR1_PIPENB_Pos           (4U)
+#define DCMIPP_HWCFGR1_PIPENB_Msk           (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos)             /*!< 0x00000030 */
+#define DCMIPP_HWCFGR1_PIPENB               DCMIPP_HWCFGR1_PIPENB_Msk                       /*!< Number of pipes */
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos        (8U)
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk        (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos)          /*!< 0x00000100 */
+#define DCMIPP_HWCFGR1_IPPLUGCFG            DCMIPP_HWCFGR1_IPPLUGCFG_Msk                    /*!< IP-Plug configuration */
+#define DCMIPP_HWCFGR1_DSP1FT_Pos           (12U)
+#define DCMIPP_HWCFGR1_DSP1FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR1_DSP1FT               DCMIPP_HWCFGR1_DSP1FT_Msk                       /*!< Down-sampling feature for the pixel Pipe1 */
+#define DCMIPP_HWCFGR1_DSP2FT_Pos           (13U)
+#define DCMIPP_HWCFGR1_DSP2FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos)             /*!< 0x00002000 */
+#define DCMIPP_HWCFGR1_DSP2FT               DCMIPP_HWCFGR1_DSP2FT_Msk                       /*!< Down-sampling feature for the pixel Pipe2 */
+#define DCMIPP_HWCFGR1_RB2RGB_Pos           (16U)
+#define DCMIPP_HWCFGR1_RB2RGB_Msk           (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos)             /*!< 0x00010000 */
+#define DCMIPP_HWCFGR1_RB2RGB               DCMIPP_HWCFGR1_RB2RGB_Msk                       /*!< Raw Bayer to RGB feature (demosaicer) */
+#define DCMIPP_HWCFGR1_PLANARFT_Pos         (20U)
+#define DCMIPP_HWCFGR1_PLANARFT_Msk         (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos)           /*!< 0x00300000 */
+#define DCMIPP_HWCFGR1_PLANARFT             DCMIPP_HWCFGR1_PLANARFT_Msk                     /*!< Buffer features for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI1NB_Pos           (24U)
+#define DCMIPP_HWCFGR1_ROI1NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos)             /*!< 0x0F000000 */
+#define DCMIPP_HWCFGR1_ROI1NB               DCMIPP_HWCFGR1_ROI1NB_Msk                       /*!< Number of ROIs for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI2NB_Pos           (28U)
+#define DCMIPP_HWCFGR1_ROI2NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos)             /*!< 0xF0000000 */
+#define DCMIPP_HWCFGR1_ROI2NB               DCMIPP_HWCFGR1_ROI2NB_Msk                       /*!< Number of ROIs for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_VERR register  ******************/
+#define DCMIPP_VERR_MINREV_Pos              (0U)
+#define DCMIPP_VERR_MINREV_Msk              (0xFU << DCMIPP_VERR_MINREV_Pos)                /*!< 0x0000000F */
+#define DCMIPP_VERR_MINREV                  DCMIPP_VERR_MINREV_Msk                          /*!< DCMIPP minor revision */
+#define DCMIPP_VERR_MAJREV_Pos              (4U)
+#define DCMIPP_VERR_MAJREV_Msk              (0xFU << DCMIPP_VERR_MAJREV_Pos)                /*!< 0x000000F0 */
+#define DCMIPP_VERR_MAJREV                  DCMIPP_VERR_MAJREV_Msk                          /*!< DCMIPP major revision */
+
+/*****************  Bit definition for DCMIPP_IPIDR register  *****************/
+#define DCMIPP_IPIDR_IDR_Pos                (0U)
+#define DCMIPP_IPIDR_IDR_Msk                (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_IPIDR_IDR                    DCMIPP_IPIDR_IDR_Msk                            /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */
+
+/*****************  Bit definition for DCMIPP_SIDR register  ******************/
+#define DCMIPP_SIDR_SID_Pos                 (0U)
+#define DCMIPP_SIDR_SID_Msk                 (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos)            /*!< 0xFFFFFFFF */
+#define DCMIPP_SIDR_SID                     DCMIPP_SIDR_SID_Msk                             /*!< 4-Kbyte decoding space */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos                     (0U)
+#define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
+#define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos                     (1U)
+#define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
+#define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos                   (0U)
+#define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
+#define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos                  (8U)
+#define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos                   (16U)
+#define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos                  (31U)
+#define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_SECCFGR register  ****************/
+#define DMA_SECCFGR_SEC0_Pos     (0U)
+#define DMA_SECCFGR_SEC0_Msk     (0x1UL << DMA_SECCFGR_SEC0_Pos)                /*!< 0x00000001 */
+#define DMA_SECCFGR_SEC0         DMA_SECCFGR_SEC0_Msk                          /*!< Secure State of Channel 0 */
+#define DMA_SECCFGR_SEC1_Pos     (1U)
+#define DMA_SECCFGR_SEC1_Msk     (0x1UL << DMA_SECCFGR_SEC1_Pos)                /*!< 0x00000002 */
+#define DMA_SECCFGR_SEC1         DMA_SECCFGR_SEC1_Msk                          /*!< Secure State of Channel 1 */
+#define DMA_SECCFGR_SEC2_Pos     (2U)
+#define DMA_SECCFGR_SEC2_Msk     (0x1UL << DMA_SECCFGR_SEC2_Pos)                /*!< 0x00000004 */
+#define DMA_SECCFGR_SEC2         DMA_SECCFGR_SEC2_Msk                          /*!< Secure State of Channel 2 */
+#define DMA_SECCFGR_SEC3_Pos     (3U)
+#define DMA_SECCFGR_SEC3_Msk     (0x1UL << DMA_SECCFGR_SEC3_Pos)                /*!< 0x00000008 */
+#define DMA_SECCFGR_SEC3         DMA_SECCFGR_SEC3_Msk                          /*!< Secure State of Channel 3 */
+#define DMA_SECCFGR_SEC4_Pos     (4U)
+#define DMA_SECCFGR_SEC4_Msk     (0x1UL << DMA_SECCFGR_SEC4_Pos)                /*!< 0x00000010 */
+#define DMA_SECCFGR_SEC4         DMA_SECCFGR_SEC4_Msk                          /*!< Secure State of Channel 4 */
+#define DMA_SECCFGR_SEC5_Pos     (5U)
+#define DMA_SECCFGR_SEC5_Msk     (0x1UL << DMA_SECCFGR_SEC5_Pos)                /*!< 0x00000020 */
+#define DMA_SECCFGR_SEC5         DMA_SECCFGR_SEC5_Msk                          /*!< Secure State of Channel 5 */
+#define DMA_SECCFGR_SEC6_Pos     (6U)
+#define DMA_SECCFGR_SEC6_Msk     (0x1UL << DMA_SECCFGR_SEC6_Pos)                /*!< 0x00000040 */
+#define DMA_SECCFGR_SEC6         DMA_SECCFGR_SEC6_Msk                          /*!< Secure State of Channel 6 */
+#define DMA_SECCFGR_SEC7_Pos     (7U)
+#define DMA_SECCFGR_SEC7_Msk     (0x1UL << DMA_SECCFGR_SEC7_Pos)                /*!< 0x00000080 */
+#define DMA_SECCFGR_SEC7         DMA_SECCFGR_SEC7_Msk                          /*!< Secure State of Channel 7 */
+#define DMA_SECCFGR_SEC8_Pos     (8U)
+#define DMA_SECCFGR_SEC8_Msk     (0x1UL << DMA_SECCFGR_SEC8_Pos)                /*!< 0x00000100 */
+#define DMA_SECCFGR_SEC8         DMA_SECCFGR_SEC8_Msk                          /*!< Secure State of Channel 8 */
+#define DMA_SECCFGR_SEC9_Pos     (9U)
+#define DMA_SECCFGR_SEC9_Msk     (0x1UL << DMA_SECCFGR_SEC9_Pos)                /*!< 0x00000200 */
+#define DMA_SECCFGR_SEC9         DMA_SECCFGR_SEC9_Msk                          /*!< Secure State of Channel 9 */
+#define DMA_SECCFGR_SEC10_Pos    (10U)
+#define DMA_SECCFGR_SEC10_Msk    (0x1UL << DMA_SECCFGR_SEC10_Pos)               /*!< 0x00000400 */
+#define DMA_SECCFGR_SEC10        DMA_SECCFGR_SEC10_Msk                         /*!< Secure State of Channel 10 */
+#define DMA_SECCFGR_SEC11_Pos    (11U)
+#define DMA_SECCFGR_SEC11_Msk    (0x1UL << DMA_SECCFGR_SEC11_Pos)               /*!< 0x00000800 */
+#define DMA_SECCFGR_SEC11        DMA_SECCFGR_SEC11_Msk                         /*!< Secure State of Channel 11 */
+#define DMA_SECCFGR_SEC12_Pos    (12U)
+#define DMA_SECCFGR_SEC12_Msk    (0x1UL << DMA_SECCFGR_SEC12_Pos)               /*!< 0x00001000 */
+#define DMA_SECCFGR_SEC12        DMA_SECCFGR_SEC12_Msk                         /*!< Secure State of Channel 12 */
+#define DMA_SECCFGR_SEC13_Pos    (13U)
+#define DMA_SECCFGR_SEC13_Msk    (0x1UL << DMA_SECCFGR_SEC13_Pos)               /*!< 0x00002000 */
+#define DMA_SECCFGR_SEC13        DMA_SECCFGR_SEC13_Msk                         /*!< Secure State of Channel 13 */
+#define DMA_SECCFGR_SEC14_Pos    (14U)
+#define DMA_SECCFGR_SEC14_Msk    (0x1UL << DMA_SECCFGR_SEC14_Pos)               /*!< 0x00004000 */
+#define DMA_SECCFGR_SEC14        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 14 */
+#define DMA_SECCFGR_SEC15_Pos    (15U)
+#define DMA_SECCFGR_SEC15_Msk    (0x1UL << DMA_SECCFGR_SEC15_Pos)               /*!< 0x00008000 */
+#define DMA_SECCFGR_SEC15        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 15 */
+
+/*******************  Bit definition for DMA_PRIVCFGR register  ****************/
+#define DMA_PRIVCFGR_PRIV0_Pos              (0U)
+#define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0 */
+#define DMA_PRIVCFGR_PRIV1_Pos              (1U)
+#define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1 */
+#define DMA_PRIVCFGR_PRIV2_Pos              (2U)
+#define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2 */
+#define DMA_PRIVCFGR_PRIV3_Pos              (3U)
+#define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3 */
+#define DMA_PRIVCFGR_PRIV4_Pos              (4U)
+#define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4 */
+#define DMA_PRIVCFGR_PRIV5_Pos              (5U)
+#define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5 */
+#define DMA_PRIVCFGR_PRIV6_Pos              (6U)
+#define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6 */
+#define DMA_PRIVCFGR_PRIV7_Pos              (7U)
+#define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7 */
+#define DMA_PRIVCFGR_PRIV8_Pos              (8U)
+#define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
+#define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8 */
+#define DMA_PRIVCFGR_PRIV9_Pos              (9U)
+#define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
+#define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9 */
+#define DMA_PRIVCFGR_PRIV10_Pos             (10U)
+#define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
+#define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
+#define DMA_PRIVCFGR_PRIV11_Pos             (11U)
+#define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
+#define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */
+#define DMA_PRIVCFGR_PRIV12_Pos             (12U)
+#define DMA_PRIVCFGR_PRIV12_Msk             (0x1UL << DMA_PRIVCFGR_PRIV12_Pos)      /*!< 0x00001000 */
+#define DMA_PRIVCFGR_PRIV12                 DMA_PRIVCFGR_PRIV12_Msk                 /*!< Privileged State of Channel 12 */
+#define DMA_PRIVCFGR_PRIV13_Pos             (13U)
+#define DMA_PRIVCFGR_PRIV13_Msk             (0x1UL << DMA_PRIVCFGR_PRIV13_Pos)      /*!< 0x00002000 */
+#define DMA_PRIVCFGR_PRIV13                 DMA_PRIVCFGR_PRIV13_Msk                 /*!< Privileged State of Channel 13 */
+#define DMA_PRIVCFGR_PRIV14_Pos             (14U)
+#define DMA_PRIVCFGR_PRIV14_Msk             (0x1UL << DMA_PRIVCFGR_PRIV14_Pos)      /*!< 0x00004000 */
+#define DMA_PRIVCFGR_PRIV14                 DMA_PRIVCFGR_PRIV14_Msk                 /*!< Privileged State of Channel 14 */
+#define DMA_PRIVCFGR_PRIV15_Pos             (15U)
+#define DMA_PRIVCFGR_PRIV15_Msk             (0x1UL << DMA_PRIVCFGR_PRIV15_Pos)      /*!< 0x00008000 */
+#define DMA_PRIVCFGR_PRIV15                 DMA_PRIVCFGR_PRIV15_Msk                 /*!< Privileged State of Channel 15 */
+
+/*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
+#define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
+#define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
+#define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
+#define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
+#define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
+#define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
+#define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
+#define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
+#define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
+#define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
+#define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
+#define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
+#define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
+#define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
+#define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
+#define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
+#define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
+#define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
+#define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
+#define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
+#define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
+#define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
+#define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
+#define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
+#define DMA_RCFGLOCKR_LOCK8_Pos              (8U)
+#define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
+#define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
+#define DMA_RCFGLOCKR_LOCK9_Pos              (9U)
+#define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
+#define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
+#define DMA_RCFGLOCKR_LOCK10_Pos             (10U)
+#define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
+#define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
+#define DMA_RCFGLOCKR_LOCK11_Pos             (11U)
+#define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
+#define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */
+#define DMA_RCFGLOCKR_LOCK12_Pos             (12U)
+#define DMA_RCFGLOCKR_LOCK12_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos)      /*!< 0x00001000 */
+#define DMA_RCFGLOCKR_LOCK12                 DMA_RCFGLOCKR_LOCK12_Msk                 /*!< Lock the configuration of Channel 12 */
+#define DMA_RCFGLOCKR_LOCK13_Pos             (13U)
+#define DMA_RCFGLOCKR_LOCK13_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos)      /*!< 0x00002000 */
+#define DMA_RCFGLOCKR_LOCK13                 DMA_RCFGLOCKR_LOCK13_Msk                 /*!< Lock the configuration of Channel 13 */
+#define DMA_RCFGLOCKR_LOCK14_Pos             (14U)
+#define DMA_RCFGLOCKR_LOCK14_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos)      /*!< 0x00004000 */
+#define DMA_RCFGLOCKR_LOCK14                 DMA_RCFGLOCKR_LOCK14_Msk                 /*!< Lock the configuration of Channel 14 */
+#define DMA_RCFGLOCKR_LOCK15_Pos             (15U)
+#define DMA_RCFGLOCKR_LOCK15_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos)      /*!< 0x00008000 */
+#define DMA_RCFGLOCKR_LOCK15                 DMA_RCFGLOCKR_LOCK15_Msk                 /*!< Lock the configuration of Channel 15 */
+
+/*******************  Bit definition for DMA_MISR register  ****************/
+#define DMA_MISR_MIS0_Pos                   (0U)
+#define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
+#define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0 */
+#define DMA_MISR_MIS1_Pos                   (1U)
+#define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
+#define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1 */
+#define DMA_MISR_MIS2_Pos                   (2U)
+#define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
+#define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2 */
+#define DMA_MISR_MIS3_Pos                   (3U)
+#define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
+#define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3 */
+#define DMA_MISR_MIS4_Pos                   (4U)
+#define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
+#define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4 */
+#define DMA_MISR_MIS5_Pos                   (5U)
+#define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
+#define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5 */
+#define DMA_MISR_MIS6_Pos                   (6U)
+#define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
+#define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6 */
+#define DMA_MISR_MIS7_Pos                   (7U)
+#define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
+#define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7 */
+#define DMA_MISR_MIS8_Pos                   (8U)
+#define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
+#define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 8 */
+#define DMA_MISR_MIS9_Pos                   (9U)
+#define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
+#define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 9 */
+#define DMA_MISR_MIS10_Pos                  (10U)
+#define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
+#define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 10 */
+#define DMA_MISR_MIS11_Pos                  (11U)
+#define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
+#define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 11 */
+#define DMA_MISR_MIS12_Pos                  (12U)
+#define DMA_MISR_MIS12_Msk                  (0x1UL << DMA_MISR_MIS12_Pos)           /*!< 0x00001000 */
+#define DMA_MISR_MIS12                      DMA_MISR_MIS12_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 12 */
+#define DMA_MISR_MIS13_Pos                  (13U)
+#define DMA_MISR_MIS13_Msk                  (0x1UL << DMA_MISR_MIS13_Pos)           /*!< 0x00002000 */
+#define DMA_MISR_MIS13                      DMA_MISR_MIS13_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 13 */
+#define DMA_MISR_MIS14_Pos                  (14U)
+#define DMA_MISR_MIS14_Msk                  (0x1UL << DMA_MISR_MIS14_Pos)           /*!< 0x00004000 */
+#define DMA_MISR_MIS14                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 14 */
+#define DMA_MISR_MIS15_Pos                  (15U)
+#define DMA_MISR_MIS15_Msk                  (0x1UL << DMA_MISR_MIS15_Pos)           /*!< 0x00008000 */
+#define DMA_MISR_MIS15                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 15 */
+
+/*******************  Bit definition for DMA_SMISR register  ****************/
+#define DMA_SMISR_MIS0_Pos       (0U)
+#define DMA_SMISR_MIS0_Msk       (0x1UL << DMA_SMISR_MIS0_Pos)                  /*!< 0x00000001 */
+#define DMA_SMISR_MIS0           DMA_SMISR_MIS0_Msk                            /*!< Masked Interrupt State of Secure Channel 0 */
+#define DMA_SMISR_MIS1_Pos       (1U)
+#define DMA_SMISR_MIS1_Msk       (0x1UL << DMA_SMISR_MIS1_Pos)                  /*!< 0x00000002 */
+#define DMA_SMISR_MIS1           DMA_SMISR_MIS1_Msk                            /*!< Masked Interrupt State of Secure Channel 1 */
+#define DMA_SMISR_MIS2_Pos       (2U)
+#define DMA_SMISR_MIS2_Msk       (0x1UL << DMA_SMISR_MIS2_Pos)                  /*!< 0x00000004 */
+#define DMA_SMISR_MIS2           DMA_SMISR_MIS2_Msk                            /*!< Masked Interrupt State of Secure Channel 2 */
+#define DMA_SMISR_MIS3_Pos       (3U)
+#define DMA_SMISR_MIS3_Msk       (0x1UL << DMA_SMISR_MIS3_Pos)                  /*!< 0x00000008 */
+#define DMA_SMISR_MIS3           DMA_SMISR_MIS3_Msk                            /*!< Masked Interrupt State of Secure Channel 3 */
+#define DMA_SMISR_MIS4_Pos       (4U)
+#define DMA_SMISR_MIS4_Msk       (0x1UL << DMA_SMISR_MIS4_Pos)                  /*!< 0x00000010 */
+#define DMA_SMISR_MIS4           DMA_SMISR_MIS4_Msk                            /*!< Masked Interrupt State of Secure Channel 4 */
+#define DMA_SMISR_MIS5_Pos       (5U)
+#define DMA_SMISR_MIS5_Msk       (0x1UL << DMA_SMISR_MIS5_Pos)                  /*!< 0x00000020 */
+#define DMA_SMISR_MIS5           DMA_SMISR_MIS5_Msk                            /*!< Masked Interrupt State of Secure Channel 5 */
+#define DMA_SMISR_MIS6_Pos       (6U)
+#define DMA_SMISR_MIS6_Msk       (0x1UL << DMA_SMISR_MIS6_Pos)                  /*!< 0x00000040 */
+#define DMA_SMISR_MIS6           DMA_SMISR_MIS6_Msk                            /*!< Masked Interrupt State of Secure Channel 6 */
+#define DMA_SMISR_MIS7_Pos       (7U)
+#define DMA_SMISR_MIS7_Msk       (0x1UL << DMA_SMISR_MIS7_Pos)                  /*!< 0x00000080 */
+#define DMA_SMISR_MIS7           DMA_SMISR_MIS7_Msk                            /*!< Masked Interrupt State of Secure Channel 7 */
+#define DMA_SMISR_MIS8_Pos       (8U)
+#define DMA_SMISR_MIS8_Msk       (0x1UL << DMA_SMISR_MIS8_Pos)                  /*!< 0x00000100 */
+#define DMA_SMISR_MIS8           DMA_SMISR_MIS8_Msk                            /*!< Masked Interrupt State of Secure Channel 8 */
+#define DMA_SMISR_MIS9_Pos       (9U)
+#define DMA_SMISR_MIS9_Msk       (0x1UL << DMA_SMISR_MIS9_Pos)                  /*!< 0x00000200 */
+#define DMA_SMISR_MIS9           DMA_SMISR_MIS9_Msk                            /*!< Masked Interrupt State of Secure Channel 9 */
+#define DMA_SMISR_MIS10_Pos      (10U)
+#define DMA_SMISR_MIS10_Msk      (0x1UL << DMA_SMISR_MIS10_Pos)                 /*!< 0x00000400 */
+#define DMA_SMISR_MIS10          DMA_SMISR_MIS10_Msk                           /*!< Masked Interrupt State of Secure Channel 10 */
+#define DMA_SMISR_MIS11_Pos      (11U)
+#define DMA_SMISR_MIS11_Msk      (0x1UL << DMA_SMISR_MIS11_Pos)                 /*!< 0x00000800 */
+#define DMA_SMISR_MIS11          DMA_SMISR_MIS11_Msk                           /*!< Masked Interrupt State of Secure Channel 11 */
+#define DMA_SMISR_MIS12_Pos      (12U)
+#define DMA_SMISR_MIS12_Msk      (0x1UL << DMA_SMISR_MIS12_Pos)                 /*!< 0x00001000 */
+#define DMA_SMISR_MIS12          DMA_SMISR_MIS12_Msk                           /*!< Masked Interrupt State of Secure Channel 12 */
+#define DMA_SMISR_MIS13_Pos      (13U)
+#define DMA_SMISR_MIS13_Msk      (0x1UL << DMA_SMISR_MIS13_Pos)                 /*!< 0x00002000 */
+#define DMA_SMISR_MIS13          DMA_SMISR_MIS13_Msk                           /*!< Masked Interrupt State of Secure Channel 13 */
+#define DMA_SMISR_MIS14_Pos      (14U)
+#define DMA_SMISR_MIS14_Msk      (0x1UL << DMA_SMISR_MIS14_Pos)                 /*!< 0x00004000 */
+#define DMA_SMISR_MIS14          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 14 */
+#define DMA_SMISR_MIS15_Pos      (15U)
+#define DMA_SMISR_MIS15_Msk      (0x1UL << DMA_SMISR_MIS15_Pos)                 /*!< 0x00008000 */
+#define DMA_SMISR_MIS15          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 15 */
+
+/*******************  Bit definition for DMA_CLBAR register  ****************/
+#define DMA_CLBAR_LBA_Pos                   (16U)
+#define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
+#define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
+
+/*******************  Bit definition for DMA_CCIDCFGR register  *******************/
+#define DMA_CCIDCFGR_CFEN_Pos           (0U)
+#define DMA_CCIDCFGR_CFEN_Msk           (0x1UL << DMA_CCIDCFGR_CFEN_Pos)         /*!< 0x00000001 */
+#define DMA_CCIDCFGR_CFEN               DMA_CCIDCFGR_CFEN_Msk                   /*!< CID filtering enable of the channel x */
+#define DMA_CCIDCFGR_SCID_Pos           (4U)
+#define DMA_CCIDCFGR_SCID_Msk           (0x7UL << DMA_CCIDCFGR_SCID_Pos)         /*!< 0x00000070 */
+#define DMA_CCIDCFGR_SCID               DMA_CCIDCFGR_SCID_Msk                   /*!< select a static CID to the channel x */
+
+/*******************  Bit definition for DMA_CFCR register  *******************/
+#define DMA_CFCR_TCF_Pos                    (8U)
+#define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
+#define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear */
+#define DMA_CFCR_HTF_Pos                    (9U)
+#define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
+#define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear */
+#define DMA_CFCR_DTEF_Pos                   (10U)
+#define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
+#define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear */
+#define DMA_CFCR_ULEF_Pos                   (11U)
+#define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
+#define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
+#define DMA_CFCR_USEF_Pos                   (12U)
+#define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
+#define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear */
+#define DMA_CFCR_SUSPF_Pos                  (13U)
+#define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
+#define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear */
+#define DMA_CFCR_TOF_Pos                    (14U)
+#define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
+#define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun clear flag */
+
+/*******************  Bit definition for DMA_CSR register  *******************/
+#define DMA_CSR_IDLEF_Pos                   (0U)
+#define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
+#define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag */
+#define DMA_CSR_TCF_Pos                     (8U)
+#define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
+#define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag */
+#define DMA_CSR_HTF_Pos                     (9U)
+#define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
+#define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag */
+#define DMA_CSR_DTEF_Pos                    (10U)
+#define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
+#define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag */
+#define DMA_CSR_ULEF_Pos                    (11U)
+#define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
+#define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
+#define DMA_CSR_USEF_Pos                    (12U)
+#define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
+#define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag */
+#define DMA_CSR_SUSPF_Pos                   (13U)
+#define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
+#define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag */
+#define DMA_CSR_TOF_Pos                     (14U)
+#define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
+#define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag */
+#define DMA_CSR_FIFOL_Pos                   (16U)
+#define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
+#define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos                      (0U)
+#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable */
+#define DMA_CCR_RESET_Pos                   (1U)
+#define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
+#define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset */
+#define DMA_CCR_SUSP_Pos                    (2U)
+#define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
+#define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend */
+#define DMA_CCR_TCIE_Pos                    (8U)
+#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
+#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos                    (9U)
+#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
+#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable */
+#define DMA_CCR_DTEIE_Pos                   (10U)
+#define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
+#define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable */
+#define DMA_CCR_ULEIE_Pos                   (11U)
+#define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
+#define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
+#define DMA_CCR_USEIE_Pos                   (12U)
+#define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
+#define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable */
+#define DMA_CCR_SUSPIE_Pos                  (13U)
+#define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
+#define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable */
+#define DMA_CCR_TOIE_Pos                    (14U)
+#define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
+#define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable */
+#define DMA_CCR_LSM_Pos                     (16U)
+#define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
+#define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode */
+#define DMA_CCR_LAP_Pos                     (17U)
+#define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
+#define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port */
+#define DMA_CCR_PRIO_Pos                    (22U)
+#define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
+#define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level */
+#define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
+#define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
+
+/*******************  Bit definition for DMA_CTR1 register  *******************/
+#define DMA_CTR1_SDW_LOG2_Pos               (0U)
+#define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
+#define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst */
+#define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_SINC_Pos                   (3U)
+#define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
+#define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst */
+#define DMA_CTR1_SBL_1_Pos                  (4U)
+#define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
+#define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1 */
+#define DMA_CTR1_PAM_Pos                    (11U)
+#define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
+#define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode */
+#define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
+#define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
+#define DMA_CTR1_SBX_Pos                    (13U)
+#define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
+#define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
+#define DMA_CTR1_SAP_Pos                    (14U)
+#define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
+#define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port */
+#define DMA_CTR1_SSEC_Pos                   (15U)
+#define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
+#define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source */
+#define DMA_CTR1_DDW_LOG2_Pos               (16U)
+#define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
+#define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst */
+#define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_DINC_Pos                   (19U)
+#define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
+#define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst */
+#define DMA_CTR1_DBL_1_Pos                  (20U)
+#define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
+#define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1 */
+#define DMA_CTR1_DBX_Pos                    (26U)
+#define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
+#define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange */
+#define DMA_CTR1_DHX_Pos                    (27U)
+#define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
+#define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange */
+#define DMA_CTR1_DWX_Pos                    (28U)
+#define DMA_CTR1_DWX_Msk                    (0x1UL << DMA_CTR1_DWX_Pos)             /*!< 0x10000000 */
+#define DMA_CTR1_DWX                        DMA_CTR1_DWX_Msk                        /*!< Destination word-word exchange */
+#define DMA_CTR1_DAP_Pos                    (30U)
+#define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
+#define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port */
+#define DMA_CTR1_DSEC_Pos                   (31U)
+#define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
+#define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination */
+
+/******************  Bit definition for DMA_CTR2 register  *******************/
+#define DMA_CTR2_REQSEL_Pos                 (0U)
+#define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
+#define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
+#define DMA_CTR2_SWREQ_Pos                  (9U)
+#define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
+#define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request */
+#define DMA_CTR2_DREQ_Pos                   (10U)
+#define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
+#define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request */
+#define DMA_CTR2_BREQ_Pos                   (11U)
+#define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
+#define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request */
+#define DMA_CTR2_PFREQ_Pos                  (12U)
+#define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)           /*!< 0x00001000 */
+#define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Hardware request in peripheral flow control mode */
+#define DMA_CTR2_TRIGM_Pos                  (14U)
+#define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
+#define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode */
+#define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
+#define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
+#define DMA_CTR2_TRIGSEL_Pos                (16U)
+#define DMA_CTR2_TRIGSEL_Msk                (0x7FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x007F0000 */
+#define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection */
+#define DMA_CTR2_TRIGPOL_Pos                (24U)
+#define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
+#define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity */
+#define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
+#define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
+#define DMA_CTR2_TCEM_Pos                   (30U)
+#define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
+#define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode */
+#define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
+#define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
+
+/******************  Bit definition for DMA_CBR1 register  *******************/
+#define DMA_CBR1_BNDT_Pos                   (0U)
+#define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
+#define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
+#define DMA_CBR1_BRC_Pos                    (16U)
+#define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
+#define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter */
+#define DMA_CBR1_SDEC_Pos                   (28U)
+#define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
+#define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement */
+#define DMA_CBR1_DDEC_Pos                   (29U)
+#define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
+#define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement */
+#define DMA_CBR1_BRSDEC_Pos                 (30U)
+#define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
+#define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement */
+#define DMA_CBR1_BRDDEC_Pos                 (31U)
+#define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
+#define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement */
+
+/******************  Bit definition for DMA_CSAR register  ********************/
+#define DMA_CSAR_SA_Pos                     (0U)
+#define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
+
+/******************  Bit definition for DMA_CDAR register  *******************/
+#define DMA_CDAR_DA_Pos                     (0U)
+#define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
+
+/******************  Bit definition for DMA_CTR3 register  *******************/
+#define DMA_CTR3_SAO_Pos                    (0U)
+#define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
+#define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment */
+#define DMA_CTR3_DAO_Pos                    (16U)
+#define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
+#define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
+
+/******************  Bit definition for DMA_CBR2 register  *******************/
+#define DMA_CBR2_BRSAO_Pos                  (0U)
+#define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
+#define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset */
+#define DMA_CBR2_BRDAO_Pos                  (16U)
+#define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
+#define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
+
+/******************  Bit definition for DMA_CLLR register  *******************/
+#define DMA_CLLR_LA_Pos                     (2U)
+#define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
+#define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
+#define DMA_CLLR_ULL_Pos                    (16U)
+#define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
+#define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory */
+#define DMA_CLLR_UB2_Pos                    (25U)
+#define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
+#define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory */
+#define DMA_CLLR_UT3_Pos                    (26U)
+#define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
+#define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM */
+#define DMA_CLLR_UDA_Pos                    (27U)
+#define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
+#define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM */
+#define DMA_CLLR_USA_Pos                    (28U)
+#define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
+#define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM */
+#define DMA_CLLR_UB1_Pos                    (29U)
+#define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
+#define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM */
+#define DMA_CLLR_UT2_Pos                    (30U)
+#define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
+#define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM */
+#define DMA_CLLR_UT1_Pos                    (31U)
+#define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
+#define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          DMA2D Controller (DMA2D)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DMA2D_CR register  ******************/
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0] */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /*!< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+/*!<Mode_ARGB8888/RGB888 */
+#define DMA2D_OCOLR_BLUE_1         (0x000000FFUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_1        (0x0000FF00UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_1          (0x00FF0000UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1        (0xFF000000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_2        (0x000007E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_2          (0x0000F800UL)                              /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_3        (0x000003E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_3          (0x00007C00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3        (0x00008000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4         (0x0000000FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_4        (0x000000F0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_4          (0x00000F00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4        (0x0000F000UL)                              /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital Temperature Sensor                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DTS_PVTREG_LOCKR register  *****************/
+#define DTS_PVTREG_LOCKR_LOCK_Pos                 (0U)
+#define DTS_PVTREG_LOCKR_LOCK_Msk                 (0xFFFFFFFFUL << DTS_PVTREG_LOCKR_LOCK_Pos)         /*!< 0xFFFFFFFF */
+#define DTS_PVTREG_LOCKR_LOCK                     DTS_PVTREG_LOCKR_LOCK_Msk                           /*!< PVT software lock */
+
+/*******************  Bit definition for DTS_PVTLOCK_SR register  *****************/
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos         (0U)
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos)        /*!< 0x00000001 */
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS             DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk                   /*!< Software lock status */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos         (1U)
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos)        /*!< 0x00000002 */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS             DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk                   /*!< Hardware lock status */
+
+/*******************  Bit definition for DTS_PVTTMR_CR register  *****************/
+#define DTS_PVTTMR_CR_TMR_DELAY_Pos               (0U)
+#define DTS_PVTTMR_CR_TMR_DELAY_Msk               (0xFFFFUL << DTS_PVTTMR_CR_TMR_DELAY_Pos)           /*!< 0x0000FFFF */
+#define DTS_PVTTMR_CR_TMR_DELAY                   DTS_PVTTMR_CR_TMR_DELAY_Msk                         /*!< Timer delay */
+#define DTS_PVTTMR_CR_TMR_RUN_Pos                 (16U)
+#define DTS_PVTTMR_CR_TMR_RUN_Msk                 (0x1UL << DTS_PVTTMR_CR_TMR_RUN_Pos)                /*!< 0x00010000 */
+#define DTS_PVTTMR_CR_TMR_RUN                     DTS_PVTTMR_CR_TMR_RUN_Msk                           /*!< Enable */
+
+/*******************  Bit definition for DTS_PVTTMR_SR register  *****************/
+#define DTS_PVTTMR_SR_TMR_BUSY_Pos                (0U)
+#define DTS_PVTTMR_SR_TMR_BUSY_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_BUSY_Pos)               /*!< 0x00000001 */
+#define DTS_PVTTMR_SR_TMR_BUSY                    DTS_PVTTMR_SR_TMR_BUSY_Msk                          /*!< Counter busy flag */
+#define DTS_PVTTMR_SR_TMR_DONE_Pos                (1U)
+#define DTS_PVTTMR_SR_TMR_DONE_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_PVTTMR_SR_TMR_DONE                    DTS_PVTTMR_SR_TMR_DONE_Msk                          /*!< Cnt delay timeout */
+
+/*******************  Bit definition for DTS_PVT_IER register  *****************/
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Pos            (0U)
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Msk            (0x1UL << DTS_PVT_IER_TMR_IRQ_ENABLE_Pos)           /*!< 0x00000001 */
+#define DTS_PVT_IER_TMR_IRQ_ENABLE                DTS_PVT_IER_TMR_IRQ_ENABLE_Msk                      /*!< Timer IRQ enable */
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Pos             (1U)
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Msk             (0x1UL << DTS_PVT_IER_TS_IRQ_ENABLE_Pos)            /*!< 0x00000002 */
+#define DTS_PVT_IER_TS_IRQ_ENABLE                 DTS_PVT_IER_TS_IRQ_ENABLE_Msk                       /*!< TS IRQ enable */
+
+/*******************  Bit definition for DTS_PVTIRQTRMASKR register  *****************/
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos        (0U)
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk        (0x1UL << DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos)       /*!< 0x00000001 */
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK            DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk                  /*!< Timer IRQ mask */
+
+/*******************  Bit definition for DTS_TS_MR register  *****************/
+#define DTS_TS_MR_TS0_IRQ_MASK_Pos                (0U)
+#define DTS_TS_MR_TS0_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS0_IRQ_MASK_Pos)               /*!< 0x00000001 */
+#define DTS_TS_MR_TS0_IRQ_MASK                    DTS_TS_MR_TS0_IRQ_MASK_Msk                          /*!< TS0 IRQ mask */
+#define DTS_TS_MR_TS1_IRQ_MASK_Pos                (1U)
+#define DTS_TS_MR_TS1_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS1_IRQ_MASK_Pos)               /*!< 0x00000002 */
+#define DTS_TS_MR_TS1_IRQ_MASK                    DTS_TS_MR_TS1_IRQ_MASK_Msk                          /*!< TS1 IRQ mask */
+
+/*******************  Bit definition for DTS_PVTTR_SR register  *****************/
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos           (0U)
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk           (0x1UL << DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos)          /*!< 0x00000001 */
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS               DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk                     /*!< Timer IRQ status after masking */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Pos             (0U)
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS0_IRQ_STATUS_Pos)            /*!< 0x00000001 */
+#define DTS_TS_ISR_TS0_IRQ_STATUS                 DTS_TS_ISR_TS0_IRQ_STATUS_Msk                       /*!< TS0 IRQ status after masking */
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Pos             (1U)
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS1_IRQ_STATUS_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ISR_TS1_IRQ_STATUS                 DTS_TS_ISR_TS1_IRQ_STATUS_Msk                       /*!< TS1 IRQ status after masking */
+
+/*******************  Bit definition for DTS_PVTTMRRAW_ISR register  *****************/
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos  (0U)
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk  (0x1UL << DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos) /*!< 0x00000001 */
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS      DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk            /*!< Timer IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSRAW_ISR register  *****************/
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos      (0U)
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos)     /*!< 0x00000001 */
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS0_RAW_IRQ_STATUS_Msk                /*!< TS0 IRQ status before masking */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos      (1U)
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos)     /*!< 0x00000002 */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk                /*!< TS1 IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSCCLKSYNTHR register  *****************/
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos         (0U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos)       /*!< 0x000000FF */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO             DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk                   /*!< Synthesized clk_ts low period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos         (8U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos)       /*!< 0x0000FF00 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI             DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk                   /*!< Synthesized clk_ts ghigh period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos       (16U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk       (0xFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos)      /*!< 0x000F0000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD           DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk                 /*!< Hold input or output delay */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos         (24U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk         (0x1UL << DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos)        /*!< 0x01000000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN             DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk                   /*!< Synthesized enable */
+
+/*******************  Bit definition for DTS_TSCSDIFDISABLER register  *****************/
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos  (0U)
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk            /*!< TS0 SDIF disable */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos  (1U)
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos) /*!< 0x00000002 */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk            /*!< TS1 SDIF disable */
+
+/*******************  Bit definition for DTS_TSCSDIF_SR register  *****************/
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Pos              (0U)
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_BUSY_Pos)             /*!< 0x00000001 */
+#define DTS_TSCSDIF_SR_SDIF_BUSY                  DTS_TSCSDIF_SR_SDIF_BUSY_Msk                        /*!< SDIF busy flag */
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Pos              (1U)
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_LOCK_Pos)             /*!< 0x00000002 */
+#define DTS_TSCSDIF_SR_SDIF_LOCK                  DTS_TSCSDIF_SR_SDIF_LOCK_Msk                        /*!< SDIF locked flag */
+
+/*******************  Bit definition for DTS_TSCSDIF_CR register  *****************/
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Pos             (0U)
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Msk             (0xFFFFFFUL << DTS_TSCSDIF_CR_SDIF_WDATA_Pos)       /*!< 0x00FFFFFF */
+#define DTS_TSCSDIF_CR_SDIF_WDATA                 DTS_TSCSDIF_CR_SDIF_WDATA_Msk                       /*!< SDIF write data */
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Pos              (24U)
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Msk              (0x7UL << DTS_TSCSDIF_CR_SDIF_ADDR_Pos)             /*!< 0x07000000 */
+#define DTS_TSCSDIF_CR_SDIF_ADDR                  DTS_TSCSDIF_CR_SDIF_ADDR_Msk                        /*!< SDIF register address */
+#define DTS_TSCSDIF_CR_SDIF_WRN_Pos               (27U)
+#define DTS_TSCSDIF_CR_SDIF_WRN_Msk               (0x1UL << DTS_TSCSDIF_CR_SDIF_WRN_Pos)              /*!< 0x08000000 */
+#define DTS_TSCSDIF_CR_SDIF_WRN                   DTS_TSCSDIF_CR_SDIF_WRN_Msk                         /*!< SDIF write no read control */
+#define DTS_TSCSDIF_CR_SDIF_PROG_Pos              (31U)
+#define DTS_TSCSDIF_CR_SDIF_PROG_Msk              (0x1UL << DTS_TSCSDIF_CR_SDIF_PROG_Pos)             /*!< 0x80000000 */
+#define DTS_TSCSDIF_CR_SDIF_PROG                  DTS_TSCSDIF_CR_SDIF_PROG_Msk                        /*!< SDIF program request */
+
+/*******************  Bit definition for DTS_TSCSDIFHALTR register  *****************/
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Pos            (0U)
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Msk            (0x1UL << DTS_TSCSDIFHALTR_SDIF_STOP_Pos)           /*!< 0x00000001 */
+#define DTS_TSCSDIFHALTR_SDIF_STOP                DTS_TSCSDIFHALTR_SDIF_STOP_Msk                      /*!< SDIF stop */
+
+/*******************  Bit definition for DTS_TSCSDIF_CFGR register  *****************/
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos         (0U)
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk         (0x3UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000003 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT             DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk                   /*!< SDIF programming inhibit */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_0           (0x1UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000001 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_1           (0x2UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000002 */
+
+/*******************  Bit definition for DTS_TSCSMPL_CR register  *****************/
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos       (0U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk       (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos)      /*!< 0x00000001 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE           DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk                 /*!< Sample counter disable */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos          (1U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk          (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos)         /*!< 0x00000002 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD              DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk                    /*!< Sample counter hold */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Pos           (2U)
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Msk           (0x1UL << DTS_TSCSMPL_CR_SMPL_DISCARD_Pos)          /*!< 0x00000004 */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD               DTS_TSCSMPL_CR_SMPL_DISCARD_Msk                     /*!< Sample discard */
+
+/*******************  Bit definition for DTS_TSCSDIFSMPLCLRR register  *****************/
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos  (0U)
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk  (0x1UL << DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR      DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk            /*!< Sample counter clear */
+
+/*******************  Bit definition for DTS_TSCSMPLCNTR register  *****************/
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Pos            (0U)
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Msk            (0xFFFFUL << DTS_TSCSMPLCNTR_SMPL_COUNT_Pos)        /*!< 0x0000FFFF */
+#define DTS_TSCSMPLCNTR_SMPL_COUNT                DTS_TSCSMPLCNTR_SMPL_COUNT_Msk                      /*!< Sample counter  */
+
+/*******************  Bit definition for DTS_TS_IER register  *****************/
+#define DTS_TS_IER_IRQ_EN_FAULT_Pos               (0U)
+#define DTS_TS_IER_IRQ_EN_FAULT_Msk               (0x1UL << DTS_TS_IER_IRQ_EN_FAULT_Pos)              /*!< 0x00000001 */
+#define DTS_TS_IER_IRQ_EN_FAULT                   DTS_TS_IER_IRQ_EN_FAULT_Msk                         /*!< TS Fault IRQ enable */
+#define DTS_TS_IER_IRQ_EN_DONE_Pos                (1U)
+#define DTS_TS_IER_IRQ_EN_DONE_Msk                (0x1UL << DTS_TS_IER_IRQ_EN_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_TS_IER_IRQ_EN_DONE                    DTS_TS_IER_IRQ_EN_DONE_Msk                          /*!< TS Sample done IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMA_Pos              (3U)
+#define DTS_TS_IER_IRQ_EN_ALARMA_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMA_Pos)             /*!< 0x00000008 */
+#define DTS_TS_IER_IRQ_EN_ALARMA                  DTS_TS_IER_IRQ_EN_ALARMA_Msk                        /*!< TS Alarm A IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMB_Pos              (4U)
+#define DTS_TS_IER_IRQ_EN_ALARMB_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMB_Pos)             /*!< 0x00000010 */
+#define DTS_TS_IER_IRQ_EN_ALARMB                  DTS_TS_IER_IRQ_EN_ALARMB_Msk                        /*!< TS Alarm B IRQ enable */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Pos           (0U)
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Msk           (0x1UL << DTS_TS_ISR_IRQ_STATUS_FAULT_Pos)          /*!< 0x00000001 */
+#define DTS_TS_ISR_IRQ_STATUS_FAULT               DTS_TS_ISR_IRQ_STATUS_FAULT_Msk                     /*!< TS Fault IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Pos            (1U)
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Msk            (0x1UL << DTS_TS_ISR_IRQ_STATUS_DONE_Pos)           /*!< 0x00000002 */
+#define DTS_TS_ISR_IRQ_STATUS_DONE                DTS_TS_ISR_IRQ_STATUS_DONE_Msk                      /*!< TS Sample done IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos          (3U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos)         /*!< 0x00000008 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA              DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk                    /*!< TS Alarm A IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos          (4U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos)         /*!< 0x00000010 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB              DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk                    /*!< TS Alarm B IRQ status */
+
+/*******************  Bit definition for DTS_TS_ICR register  *****************/
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos            (0U)
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk            (0x1UL << DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos)           /*!< 0x00000001 */
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT                DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk                      /*!< TS Fault IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Pos             (1U)
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Msk             (0x1UL << DTS_TS_ICR_IRQ_CLEAR_DONE_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE                 DTS_TS_ICR_IRQ_CLEAR_DONE_Msk                       /*!< TS Sample done IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos           (3U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos)          /*!< 0x00000008 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA               DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk                     /*!< TS Alarm A IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos           (4U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos)          /*!< 0x00000010 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB               DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk                     /*!< TS Alarm B IRQ clear */
+
+/*******************  Bit definition for DTS_TSIRQTESTR register  *****************/
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos         (0U)
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk         (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos)        /*!< 0x00000001 */
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT             DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk                   /*!< TS Fault IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos          (1U)
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk          (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos)         /*!< 0x00000002 */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE              DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk                    /*!< TS Sample done IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos        (3U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos)       /*!< 0x00000008 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA            DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk                  /*!< TS Alarm A IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos        (4U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos)       /*!< 0x00000010 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB            DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk                  /*!< TS Alarm B IRQ test */
+
+/*******************  Bit definition for DTS_TSSDIFRDATAR register  *****************/
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Pos           (0U)
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Msk           (0xFFFFFFUL << DTS_TSSDIFRDATAR_SDIF_RDATA_Pos)     /*!< 0x00FFFFFF */
+#define DTS_TSSDIFRDATAR_SDIF_RDATA               DTS_TSSDIFRDATAR_SDIF_RDATA_Msk                     /*!< TS SDIF read data */
+
+/*******************  Bit definition for DTS_TSSDIFDONER register  *****************/
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos        (0U)
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk        (0x1UL << DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos)       /*!< 0x00000001 */
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE            DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk                  /*!< TS Sample done flag */
+
+/*******************  Bit definition for DTS_TSSDIFDATAR register  *****************/
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Pos           (0U)
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Msk           (0xFFFFUL << DTS_TSSDIFDATAR_SAMPLE_DATA_Pos)       /*!< 0x0000FFFF */
+#define DTS_TSSDIFDATAR_SAMPLE_DATA               DTS_TSSDIFDATAR_SAMPLE_DATA_Msk                     /*!< TS Sample data */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos           (16U)
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk           (0x1UL << DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos)          /*!< 0x00010000 */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE               DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk                     /*!< TS Sample type */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos          (17U)
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk          (0x1UL << DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos)         /*!< 0x00020000 */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT              DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk                    /*!< TS Sample fault */
+
+/*******************  Bit definition for DTS_TSALARMA_CFGR register  *****************/
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos        (0U)
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk        (0xFFFFUL << DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH            DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk                  /*!< TS Alarm A hysteresis threshold */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos       (16U)
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk       (0xFFFFUL << DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH           DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk                 /*!< TS Alarm A threshold */
+
+/*******************  Bit definition for DTS_TSALARMB_CFGR register  *****************/
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos        (0U)
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk        (0xFFFFUL << DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH            DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk                  /*!< TS Alarm B hysteresis threshold */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos       (16U)
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk       (0xFFFFUL << DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH           DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk                 /*!< TS Alarm B threshold */
+
+/*******************  Bit definition for DTS_TSHLSAMPLER register  *****************/
+#define DTS_TSHLSAMPLER_SMPL_LO_Pos               (0U)
+#define DTS_TSHLSAMPLER_SMPL_LO_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_LO_Pos)           /*!< 0x0000FFFF */
+#define DTS_TSHLSAMPLER_SMPL_LO                   DTS_TSHLSAMPLER_SMPL_LO_Msk                         /*!< TS Lowest valid data sample value received */
+#define DTS_TSHLSAMPLER_SMPL_HI_Pos               (16U)
+#define DTS_TSHLSAMPLER_SMPL_HI_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_HI_Pos)           /*!< 0xFFFF0000 */
+#define DTS_TSHLSAMPLER_SMPL_HI                   DTS_TSHLSAMPLER_SMPL_HI_Msk                         /*!< TS Highest valid data sample value received */
+
+/*******************  Bit definition for DTS_TSHILORESETR register  *****************/
+#define DTS_TSHILORESETR_SMPL_LO_SET_Pos          (0U)
+#define DTS_TSHILORESETR_SMPL_LO_SET_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_LO_SET_Pos)         /*!< 0x00000001 */
+#define DTS_TSHILORESETR_SMPL_LO_SET              DTS_TSHILORESETR_SMPL_LO_SET_Msk                    /*!< TS Sample Low Set */
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Pos          (1U)
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_HI_CLR_Pos)         /*!< 0x00000002 */
+#define DTS_TSHILORESETR_SMPL_HI_CLR              DTS_TSHILORESETR_SMPL_HI_CLR_Msk                    /*!< TS Sample high clear 0 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              Ethernet MAC                                  */
+/*                                                                            */
+/******************************************************************************/
+/******  Bit definition for Ethernet MAC Configuration Register  **************/
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_PB_Pos                              (18U)
+#define ETH_MACCR_PB_Msk                              (0x1UL << ETH_MACCR_PB_Pos) /*!< 0x00040000 */
+#define ETH_MACCR_PB                                  ETH_MACCR_PB_Msk         /* Packet Burst Enable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_PS_Pos                              (15U)
+#define ETH_MACCR_PS_Msk                              (0x1UL << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
+#define ETH_MACCR_PS                                  ETH_MACCR_PS_Msk         /* Port Select */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* MAC speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/******  Bit definition for Ethernet MAC Extended Configuration Register  ***********/
+#define ETH_MACECR_APDIM_Pos                          (30U)
+#define ETH_MACECR_APDIM_Msk                          (0x1FUL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */
+#define ETH_MACECR_APDIM                              ETH_MACECR_APDIM_Msk      /* ARP Packet Drop if IP Address Mismatch */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/************  Bit definition for Ethernet MAC Packet Filter Register  ***************/
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/************  Bit definition for Ethernet MAC Watchdog Timeout Register  ***************/
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/************  Bit definition for Ethernet MAC Hash Table 0 register  ***************/
+#define ETH_MACHT0R_HTH_Pos                           (0U)
+#define ETH_MACHT0R_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT0R_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/************  Bit definition for Ethernet MAC Hash Table 1 register  ***************/
+#define ETH_MACHT1R_HTL_Pos                           (0U)
+#define ETH_MACHT1R_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT1R_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/************  Bit definition for Ethernet MAC VLAN tag Control register  ***************/
+#define ETH_MACVTCR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTCR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTCR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTCR_EIVLRXS                            ETH_MACVTCR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTCR_EIVLS_Pos                          (28U)
+#define ETH_MACVTCR_EIVLS_Msk                          (0x3UL << ETH_MACVTCR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS                              ETH_MACVTCR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS                  ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS                 ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP                  ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTCR_ERIVLT_Msk                         (0x1UL << ETH_MACVTCR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTCR_ERIVLT                             ETH_MACVTCR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTCR_EDVLP_Pos                          (26U)
+#define ETH_MACVTCR_EDVLP_Msk                          (0x1UL << ETH_MACVTCR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTCR_EDVLP                              ETH_MACVTCR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTCR_VTHM_Pos                           (25U)
+#define ETH_MACVTCR_VTHM_Msk                           (0x1UL << ETH_MACVTCR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTCR_VTHM                               ETH_MACVTCR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTCR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTCR_EVLRXS_Msk                         (0x1UL << ETH_MACVTCR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTCR_EVLRXS                             ETH_MACVTCR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTCR_EVLS_Pos                           (21U)
+#define ETH_MACVTCR_EVLS_Msk                           (0x3UL << ETH_MACVTCR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS                               ETH_MACVTCR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTCR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS                   ETH_MACVTCR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS                  ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP                   ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTCR_DOVLTC_Msk                         (0x1UL << ETH_MACVTCR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTCR_DOVLTC                             ETH_MACVTCR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTCR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTCR_ERSVLM_Msk                         (0x1UL << ETH_MACVTCR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTCR_ERSVLM                             ETH_MACVTCR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTCR_ESVL_Pos                           (18U)
+#define ETH_MACVTCR_ESVL_Msk                           (0x1UL << ETH_MACVTCR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTCR_ESVL                               ETH_MACVTCR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTCR_VTIM_Pos                           (17U)
+#define ETH_MACVTCR_VTIM_Msk                           (0x1UL << ETH_MACVTCR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTCR_VTIM                               ETH_MACVTCR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTCR_ETV_Pos                            (16U)
+#define ETH_MACVTCR_ETV_Msk                            (0x1UL << ETH_MACVTCR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTCR_ETV                                ETH_MACVTCR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTCR_OFS_Pos                            (2U)
+#define ETH_MACVTCR_OFS_Msk                            (0x3UL << ETH_MACVTCR_OFS_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS                                ETH_MACVTCR_EVLS_Msk      /* Offset */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER0             ((uint32_t)0x00000000)   /* holds MAC VLAN Tag Filter0 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos) /*!< 0x00000004 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk /* holds MAC VLAN Tag Filter1 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos         (3U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos) /*!< 0x00000008 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk /* holds MAC VLAN Tag Filter2 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk         (0x3UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk /* holds MAC VLAN Tag Filter3 content */
+#define ETH_MACVTCR_CT_Pos                             (1U)
+#define ETH_MACVTCR_CT_Msk                             (0x1UL << ETH_MACVTCR_CT_Pos) /*!< 0x00000002 */
+#define ETH_MACVTCR_CT                                 ETH_MACVTCR_CT_Msk       /* Command Type */
+#define ETH_MACVTCR_OB_Pos                             (0U)
+#define ETH_MACVTCR_OB_Msk                             (0x1UL << ETH_MACVTCR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACVTCR_OB                                 ETH_MACVTCR_OB_Msk       /* Operation Busy */
+
+/************  Bit definition for Ethernet MAC VLAN tag data register  ***************/
+#define ETH_MACVTDR_DMACHN_Pos                        (25U)
+#define ETH_MACVTDR_DMACHN_Msk                        (0x1UL << ETH_MACVTDR_DMACHN_Pos) /*!< 0x02000000 */
+#define ETH_MACVTDR_DMACHN                            ETH_MACVTDR_DMACHN_Msk   /* DMA Channel Number */
+#define ETH_MACVTDR_DMACHEN_Pos                       (24U)
+#define ETH_MACVTDR_DMACHEN_Msk                       (0x1UL << ETH_MACVTDR_DMACHEN_Pos) /*!< 0x01000000 */
+#define ETH_MACVTDR_DMACHEN                           ETH_MACVTDR_DMACHEN_Msk   /* DMA Channel Number Enable */
+#define ETH_MACVTDR_ERIVLT_Pos                        (20U)
+#define ETH_MACVTDR_ERIVLT_Msk                        (0x1UL << ETH_MACVTDR_ERIVLT_Pos) /*!< 0x00100000 */
+#define ETH_MACVTDR_ERIVLT                            ETH_MACVTDR_ERIVLT_Msk   /* Enable Inner VLAN Tag Comparison */
+#define ETH_MACVTDR_ERSVLM_Pos                        (19U)
+#define ETH_MACVTDR_ERSVLM_Msk                        (0x1UL << ETH_MACVTDR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_ERSVLM                            ETH_MACVTDR_ERSVLM_Msk   /* Enable S-VLAN Match for received Frames */
+#define ETH_MACVTDR_DOVLTC_Pos                        (18U)
+#define ETH_MACVTDR_DOVLTC_Msk                        (0x1UL << ETH_MACVTDR_DOVLTC_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_DOVLTC                            ETH_MACVTDR_DOVLTC_Msk   /* Disable VLAN Type Comparison */
+#define ETH_MACVTDR_ETV_Pos                           (17U)
+#define ETH_MACVTDR_ETV_Msk                           (0x1UL << ETH_MACVTDR_ETV_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV                               ETH_MACVTDR_ETV_Msk   /* 12-bit or 16-bit VLAN comparison */
+#define ETH_MACVTDR_ETV_VLAN16B                       ((uint32_t)0x00000000)   /* 16-bit VLAN */
+#define ETH_MACVTDR_ETV_VLAN12B_Pos                   (17U)
+#define ETH_MACVTDR_ETV_VLAN12B_Msk                   (0x1UL << ETH_MACVTDR_ETV_VLAN12B_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV_VLAN12B                       ETH_MACVTDR_ETV_VLAN12B_Msk   /* 12-bit VLAN */
+#define ETH_MACVTDR_VEN_Pos                           (16U)
+#define ETH_MACVTDR_VEN_Msk                           (0x1UL << ETH_MACVTDR_VEN_Pos) /*!< 0x00010000 */
+#define ETH_MACVTDR_VEN                               ETH_MACVTDR_VEN_Msk   /* VLAN Tag Enable */
+#define ETH_MACVTDR_VID_Pos                           (0U)
+#define ETH_MACVTDR_VID_Msk                           (0xFFFFUL << ETH_MACVTDR_VID_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID                               ETH_MACVTDR_VID_Msk        /* VLAN Tag ID */
+#define ETH_MACVTDR_VID_12BIT_Msk                     (0xFFFU << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000FFF */
+#define ETH_MACVTDR_VID_12BIT                         ETH_MACVTDR_VID_12BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 12bit */
+#define ETH_MACVTDR_VID_16BIT_Msk                     (0xFFFFU << ETH_MACVTDR_VID_Pos)                    /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID_16BIT                         ETH_MACVTDR_VID_16BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 16bit */
+#define ETH_MACVTDR_VID_0                             (0x1U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000001 */
+#define ETH_MACVTDR_VID_1                             (0x2U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000002 */
+#define ETH_MACVTDR_VID_2                             (0x4U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000004 */
+#define ETH_MACVTDR_VID_3                             (0x8U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000008 */
+#define ETH_MACVTDR_VID_4                             (0x10U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000010 */
+#define ETH_MACVTDR_VID_5                             (0x20U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000020 */
+#define ETH_MACVTDR_VID_6                             (0x40U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000040 */
+#define ETH_MACVTDR_VID_7                             (0x80U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000080 */
+#define ETH_MACVTDR_VID_8                             (0x100U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000100 */
+#define ETH_MACVTDR_VID_9                             (0x200U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000200 */
+#define ETH_MACVTDR_VID_10                            (0x400U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000400 */
+#define ETH_MACVTDR_VID_11                            (0x800U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000800 */
+#define ETH_MACVTDR_VID_12                            (0x1000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00001000 */
+#define ETH_MACVTDR_VID_13                            (0x2000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00002000 */
+#define ETH_MACVTDR_VID_14                            (0x4000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00004000 */
+#define ETH_MACVTDR_VID_15                            (0x8000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00008000 */
+
+/************  Bit definition for Ethernet MAC VLAN Hash Table Register  ***************/
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/************  Bit definition for Ethernet MAC VLAN inclusion Register  ***************/
+#define ETH_MACVIR_BUSY_Pos                           (31U)
+#define ETH_MACVIR_BUSY_Msk                           (0x1UL << ETH_MACVIR_BUSY_Pos) /*!< 0x80000000 */
+#define ETH_MACVIR_BUSY                               ETH_MACVIR_BUSY_Msk      /* Busy */
+#define ETH_MACVIR_RDWR_Pos                           (30U)
+#define ETH_MACVIR_RDWR_Msk                           (0x1UL << ETH_MACVIR_RDWR_Pos) /*!< 0x40000000 */
+#define ETH_MACVIR_RDWR                               ETH_MACVIR_RDWR_Msk      /* Read write control */
+#define ETH_MACVIR_ADDR_Pos                           (24U)
+#define ETH_MACVIR_ADDR_Msk                           (0x1UL << ETH_MACVIR_ADDR_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR                               ETH_MACVIR_ADDR_Msk      /* Address */
+#define ETH_MACVIR_ADDR_VLANINSTXQ0                   ((uint32_t)0x00000000)   /* VLAN tag for insertion in the Transmit packets from Tx Queue 0 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Pos               (24U)
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Msk               (0x1UL << ETH_MACVIR_ADDR_VLANINSTXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1                   ETH_MACVIR_ADDR_VLANINSTXQ1_Msk   /* VLAN tag for insertion in the Transmit packets from Tx Queue 1 */
+#define ETH_MACVIR_CBTI_Pos                           (21U)
+#define ETH_MACVIR_CBTI_Msk                           (0x1UL << ETH_MACVIR_CBTI_Pos) /*!< 0x00200000 */
+#define ETH_MACVIR_CBTI                               ETH_MACVIR_CBTI_Msk      /* Channel based tag insertion */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Inner_VLAN Incl Register   ***************/
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Tx Queue 0 flow control Register   ***************/
+#define ETH_MACQ0TXFCR_PT_Pos                         (16U)
+#define ETH_MACQ0TXFCR_PT_Msk                         (0xFFFFUL << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACQ0TXFCR_PT                             ETH_MACQ0TXFCR_PT_Msk       /* Pause Time */
+#define ETH_MACQ0TXFCR_DZPQ_Pos                       (7U)
+#define ETH_MACQ0TXFCR_DZPQ_Msk                       (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACQ0TXFCR_DZPQ                           ETH_MACQ0TXFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACQ0TXFCR_PLT_Pos                        (4U)
+#define ETH_MACQ0TXFCR_PLT_Msk                        (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACQ0TXFCR_PLT                            ETH_MACQ0TXFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACQ0TXFCR_PLT_MINUS4                     ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Pos                (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACQ0TXFCR_PLT_MINUS28                    ETH_MACQ0TXFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Pos                (5U)
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACQ0TXFCR_PLT_MINUS36                    ETH_MACQ0TXFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Msk               (0x3UL << ETH_MACQ0TXFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACQ0TXFCR_PLT_MINUS144                   ETH_MACQ0TXFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Pos               (6U)
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Msk               (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACQ0TXFCR_PLT_MINUS256                   ETH_MACQ0TXFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Msk               (0x5UL << ETH_MACQ0TXFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACQ0TXFCR_PLT_MINUS512                   ETH_MACQ0TXFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACQ0TXFCR_TFE_Pos                        (1U)
+#define ETH_MACQ0TXFCR_TFE_Msk                        (0x1UL << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACQ0TXFCR_TFE                            ETH_MACQ0TXFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACQ0TXFCR_FCB_Pos                        (0U)
+#define ETH_MACQ0TXFCR_FCB_Msk                        (0x1UL << ETH_MACQ0TXFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACQ0TXFCR_FCB                            ETH_MACQ0TXFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/************ Bit definition for Ethernet MAC Rx flow control Register   ***************/
+#define ETH_MACRXFCR_UP_Pos                            (1U)
+#define ETH_MACRXFCR_UP_Msk                            (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRXFCR_UP                                ETH_MACRXFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRXFCR_RFE_Pos                           (0U)
+#define ETH_MACRXFCR_RFE_Msk                           (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXFCR_RFE                               ETH_MACRXFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/************ Bit definition for Ethernet MAC Rx Queue control Register  ***************/
+#define ETH_MACRXQCR_VFFQ_Pos                         (17U)
+#define ETH_MACRXQCR_VFFQ_Msk                         (0x1UL << ETH_MACRXQCR_VFFQ_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ                             ETH_MACRXQCR_VFFQ_Msk       /* VLAN Tag Filter Fail Packets Queue */
+#define ETH_MACRXQCR_VFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_VFFQ_Q1_Pos                      (17U)
+#define ETH_MACRXQCR_VFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_VFFQ_Q1_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ_Q1                          ETH_MACRXQCR_VFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_VFFQE_Pos                        (16U)
+#define ETH_MACRXQCR_VFFQE_Msk                        (0x1UL << ETH_MACRXQCR_VFFQE_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQCR_VFFQE                            ETH_MACRXQCR_VFFQE_Msk       /* VLAN Tag Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_MFFQ_Pos                         (9U)
+#define ETH_MACRXQCR_MFFQ_Msk                         (0x1UL << ETH_MACRXQCR_MFFQ_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ                             ETH_MACRXQCR_MFFQ_Msk       /* Multicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_MFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_MFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_MFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_MFFQ_Q1_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ_Q1                          ETH_MACRXQCR_MFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_MFFQE_Pos                        (8U)
+#define ETH_MACRXQCR_MFFQE_Msk                        (0x1UL << ETH_MACRXQCR_MFFQE_Pos) /*!< 0x00000100 */
+#define ETH_MACRXQCR_MFFQE                            ETH_MACRXQCR_MFFQE_Msk       /* Multicast Address Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_UFFQ_Pos                         (1U)
+#define ETH_MACRXQCR_UFFQ_Msk                         (0x1UL << ETH_MACRXQCR_UFFQ_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ                             ETH_MACRXQCR_UFFQ_Msk       /* Unicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_UFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_UFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_UFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_UFFQ_Q1_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ_Q1                          ETH_MACRXQCR_UFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_UFFQE_Pos                        (0U)
+#define ETH_MACRXQCR_UFFQE_Msk                        (0x1UL << ETH_MACRXQCR_UFFQE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQCR_UFFQE                            ETH_MACRXQCR_UFFQE_Msk       /* Unicast Address Filter Fail Packets Queuing Enable */
+
+/************ Bit definition for Ethernet MAC Rx queue control 0 Register   ***************/
+#define ETH_MACRXQC0R_RXQ1EN_Pos                      (2U)
+#define ETH_MACRXQC0R_RXQ1EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
+#define ETH_MACRXQC0R_RXQ1EN                          ETH_MACRXQC0R_RXQ1EN_Msk       /* Receive Queue 1 Enable */
+#define ETH_MACRXQC0R_RXQ1EN_NOT                      ((uint32_t)0x00000000)        /* Queue 1 Not enabled */
+#define ETH_MACRXQC0R_RXQ1EN_AV_Pos                   (2U)
+#define ETH_MACRXQC0R_RXQ1EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_AV_Pos) /*!< 0x00000004 */
+#define ETH_MACRXQC0R_RXQ1EN_AV                       ETH_MACRXQC0R_RXQ1EN_AV_Msk   /* Queue 1 enabled for AV */
+#define ETH_MACRXQC0R_RXQ1EN_GT_Pos                   (3U)
+#define ETH_MACRXQC0R_RXQ1EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_GT_Pos) /*!< 0x00000008 */
+#define ETH_MACRXQC0R_RXQ1EN_GT                       ETH_MACRXQC0R_RXQ1EN_GT_Msk   /* Queue 1 enabled for Generic traffic */
+#define ETH_MACRXQC0R_RXQ0EN_Pos                      (0U)
+#define ETH_MACRXQC0R_RXQ0EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
+#define ETH_MACRXQC0R_RXQ0EN                          ETH_MACRXQC0R_RXQ0EN_Msk       /* Receive Queue 0 Enable */
+#define ETH_MACRXQC0R_RXQ0EN_NOT                      ((uint32_t)0x00000000)        /* Queue 0 Not enabled */
+#define ETH_MACRXQC0R_RXQ0EN_AV_Pos                   (0U)
+#define ETH_MACRXQC0R_RXQ0EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_AV_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC0R_RXQ0EN_AV                       ETH_MACRXQC0R_RXQ0EN_AV_Msk   /* Queue 0 enabled for AV */
+#define ETH_MACRXQC0R_RXQ0EN_GT_Pos                   (1U)
+#define ETH_MACRXQC0R_RXQ0EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_GT_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQC0R_RXQ0EN_GT                       ETH_MACRXQC0R_RXQ0EN_GT_Msk   /* Queue 0 enabled for Generic traffic */
+
+/************ Bit definition for Ethernet MAC Rx queue control 1 Register   ***************/
+#define ETH_MACRXQC1R_TBRQE_Pos                       (29U)
+#define ETH_MACRXQC1R_TBRQE_Msk                       (0x1UL << ETH_MACRXQC1R_TBRQE_Pos) /*!< 0x20000000 */
+#define ETH_MACRXQC1R_TBRQE                           ETH_MACRXQC1R_TBRQE_Msk       /* Type Field Based Rx Queuing Enable */
+#define ETH_MACRXQC1R_OMCBCQ_Pos                      (28U)
+#define ETH_MACRXQC1R_OMCBCQ_Msk                      (0x1UL << ETH_MACRXQC1R_OMCBCQ_Pos) /*!< 0x10000000 */
+#define ETH_MACRXQC1R_OMCBCQ                          ETH_MACRXQC1R_OMCBCQ_Msk       /* Overriding MC-BC queue priority select */
+#define ETH_MACRXQC1R_FPRQ_Pos                        (24U)
+#define ETH_MACRXQC1R_FPRQ_Msk                        (0x7UL << ETH_MACRXQC1R_FPRQ_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_FPRQ                            ETH_MACRXQC1R_FPRQ_Msk       /* Frame Preemption Residue Queue */
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Pos                   (24U)
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_FPRQ_RXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACRXQC1R_FPRQ_RXQ1                       ETH_MACRXQC1R_FPRQ_RXQ1_Msk       /* Rx queue 1 */
+#define ETH_MACRXQC1R_TPQC_Pos                        (22U)
+#define ETH_MACRXQC1R_TPQC_Msk                        (0x3UL << ETH_MACRXQC1R_TPQC_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_TPQC                            ETH_MACRXQC1R_TPQC_Msk   /* Tagged PTP over Ethernet Packets Queuing Control */
+#define ETH_MACRXQC1R_TPQC_PTPGENVLANTAG              ((uint32_t)0x00000000)   /* VLAN tagged PTPoE packets are routed as generic VLAN tagged packet */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos             (22U)
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk             (0x1UL << ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos) /*!< 0x000400000 */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ                 ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk /* VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos           (23U)
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk           (0x1UL << ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos) /*!< 0x00080000 */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ               ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk /* VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ */
+#define ETH_MACRXQC1R_TACPQE_Pos                      (21U)
+#define ETH_MACRXQC1R_TACPQE_Msk                      (0x1UL << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
+#define ETH_MACRXQC1R_TACPQE                          ETH_MACRXQC1R_TACPQE_Msk       /* Tagged AV Control Packets Queuing Enable */
+#define ETH_MACRXQC1R_MCBCQEN_Pos                     (20U)
+#define ETH_MACRXQC1R_MCBCQEN_Msk                     (0x1UL << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
+#define ETH_MACRXQC1R_MCBCQEN                         ETH_MACRXQC1R_MCBCQEN_Msk     /* Multicast and Broadcast Queue Enable */
+#define ETH_MACRXQC1R_MCBCQ_Pos                       (16U)
+#define ETH_MACRXQC1R_MCBCQ_Msk                       (0x7UL << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
+#define ETH_MACRXQC1R_MCBCQ                           ETH_MACRXQC1R_MCBCQ_Msk       /* Multicast and Broadcast Queue */
+#define ETH_MACRXQC1R_MCBCQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Pos                  (16U)
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_MCBCQ_RXQ1_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1                      ETH_MACRXQC1R_MCBCQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_UPQ_Pos                         (12U)
+#define ETH_MACRXQC1R_UPQ_Msk                         (0x7UL << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
+#define ETH_MACRXQC1R_UPQ                             ETH_MACRXQC1R_UPQ_Msk       /* Untagged Packet Queue */
+#define ETH_MACRXQC1R_UPQ_RXQ0                        ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_UPQ_RXQ1_Pos                    (12U)
+#define ETH_MACRXQC1R_UPQ_RXQ1_Msk                    (0x1UL << ETH_MACRXQC1R_UPQ_RXQ1_Pos) /*!< 0x00001000 */
+#define ETH_MACRXQC1R_UPQ_RXQ1                        ETH_MACRXQC1R_UPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_PTPQ_Pos                        (4U)
+#define ETH_MACRXQC1R_PTPQ_Msk                        (0x7UL << ETH_MACRXQC1R_PTPQ_Pos) /*!< 0x00000070 */
+#define ETH_MACRXQC1R_PTPQ                            ETH_MACRXQC1R_PTPQ_Msk       /* PTP Packets Queue */
+#define ETH_MACRXQC1R_PTPQ_RXQ0                       ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Pos                   (4U)
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_PTPQ_RXQ1_Pos) /*!< 0x00000010 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1                       ETH_MACRXQC1R_PTPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_AVCPQ_Pos                       (0U)
+#define ETH_MACRXQC1R_AVCPQ_Msk                       (0x7UL << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
+#define ETH_MACRXQC1R_AVCPQ                           ETH_MACRXQC1R_AVCPQ_Msk       /* AV Untagged Control Packets Queue */
+#define ETH_MACRXQC1R_AVCPQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Pos                  (0U)
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_AVCPQ_RXQ1_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1                      ETH_MACRXQC1R_AVCPQ_RXQ1_Msk  /* Rx queue 1 */
+
+/************ Bit definition for Ethernet MAC Rx queue control 2 Register   ***************/
+#define ETH_MACRXQC2R_PSRQ1_Pos                       (8U)
+#define ETH_MACRXQC2R_PSRQ1_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
+#define ETH_MACRXQC2R_PSRQ1                           ETH_MACRXQC2R_PSRQ1_Msk       /* Priorities Selected in the Receive Queue 1 */
+#define ETH_MACRXQC2R_PSRQ0_Pos                       (0U)
+#define ETH_MACRXQC2R_PSRQ0_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
+#define ETH_MACRXQC2R_PSRQ0                           ETH_MACRXQC2R_PSRQ0_Msk       /* Priorities Selected in the Receive Queue 0 */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MFRIS_Pos                          (20U)
+#define ETH_MACISR_MFRIS_Msk                          (0x1UL << ETH_MACISR_MFRIS_Pos) /*!< 0x00100000 */
+#define ETH_MACISR_MFRIS                              ETH_MACISR_MFRIS_Msk   /* MMC FPE Receive Interrupt Status */
+#define ETH_MACISR_MFTIS_Pos                          (19U)
+#define ETH_MACISR_MFTIS_Msk                          (0x1UL << ETH_MACISR_MFTIS_Pos) /*!< 0x00080000 */
+#define ETH_MACISR_MFTIS                              ETH_MACISR_MFTIS_Msk   /* MMC FPE Transmit Interrupt Status */
+#define ETH_MACISR_MDIOIS_Pos                         (18U)
+#define ETH_MACISR_MDIOIS_Msk                         (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIS                             ETH_MACISR_MDIOIS_Msk   /* MDIO Interrupt Status*/
+#define ETH_MACISR_FPEIS_Pos                          (17U)
+#define ETH_MACISR_FPEIS_Msk                          (0x1UL << ETH_MACISR_FPEIS_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIS                              ETH_MACISR_FPEIS_Msk   /* Frame Preemption Interrupt Status */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+#define ETH_MACISR_RGSMIIIS_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIS_Msk                       (0x1UL << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIS                           ETH_MACISR_RGSMIIIS_Msk     /* RGMII Interrupt Status */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MDIOIE_Pos                         (18U)
+#define ETH_MACISR_MDIOIE_Msk                         (0x1UL << ETH_MACISR_MDIOIE_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIE                             ETH_MACISR_MDIOIE_Msk   /* Receive Interrupt Enable*/
+#define ETH_MACISR_FPEIE_Pos                          (17U)
+#define ETH_MACISR_FPEIE_Msk                          (0x1UL << ETH_MACISR_FPEIE_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIE                              ETH_MACISR_FPEIE_Msk   /* Frame Preemption Interrupt Enable */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+#define ETH_MACISR_RGSMIIIE_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIE_Msk                       (0x1UL << ETH_MACISR_RGSMIIIE_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIE                           ETH_MACISR_RGSMIIIE_Msk     /* RGMII Interrupt Enable */
+
+/************ Bit definition for Ethernet MAC Rx Tx Status Register   ***************/
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/************ Bit definition for Ethernet MAC PMT Control Status Register   ***************/
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/************ Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register   ***************/
+#define ETH_MACRWKPFR_MACRWKPFR_Pos                   (0U)
+#define ETH_MACRWKPFR_MACRWKPFR_Msk                   (0xFFFFFFFFUL << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWKPFR_MACRWKPFR                       ETH_MACRWKPFR_MACRWKPFR_Msk  /* Wake-up Packet filter register data */
+
+/************ Bit definition for Ethernet MAC LPI Control Status Register   ***************/
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLSEN_Pos                         (18U)
+#define ETH_MACLCSR_PLSEN_Msk                         (0x1UL << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
+#define ETH_MACLCSR_PLSEN                             ETH_MACLCSR_PLSEN_Msk      /* PHY Link Status Enable */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/************ Bit definition for Ethernet MAC LPI Timers Control Register   ***************/
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/************ Bit definition for Ethernet MAC LPI Entry Timer Register   ***************/
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/************ Bit definition for Ethernet MAC 1US Tic Counter Register   ***************/
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/************ Bit definition for Ethernet MAC PHYIF control status Register   ***************/
+#define ETH_MACPHYCSR_LNKSTS_Pos                      (19U)
+#define ETH_MACPHYCSR_LNKSTS_Msk                      (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS                          ETH_MACPHYCSR_LNKSTS_Msk  /* Link Status */
+#define ETH_MACPHYCSR_LNKSTS_LD                       ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LNKSTS_LU_Pos                   (19U)
+#define ETH_MACPHYCSR_LNKSTS_LU_Msk                   (0x1UL << ETH_MACPHYCSR_LNKSTS_LU_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS_LU                       ETH_MACPHYCSR_LNKSTS_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_LNKSPEED_Pos                    (17U)
+#define ETH_MACPHYCSR_LNKSPEED_Msk                    (0x3UL << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
+#define ETH_MACPHYCSR_LNKSPEED                        ETH_MACPHYCSR_LNKSPEED_Msk  /* Link Speed */
+#define ETH_MACPHYCSR_LNKSPEED_2_5MHZ                 ((uint32_t)0x00000000)    /* 2.5 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos              (17U)
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk              (0x1UL << ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos) /*!< 0x00020000 */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ                  ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk   /* 25 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos             (18U)
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk             (0x1UL << ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos) /*!< 0x00040000 */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ                 ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk  /* 125 MHz */
+#define ETH_MACPHYCSR_LNKMOD_Pos                      (16U)
+#define ETH_MACPHYCSR_LNKMOD_Msk                      (0x1UL << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKMOD                          ETH_MACPHYCSR_LNKMOD_Msk  /* Link Mode */
+#define ETH_MACPHYCSR_LNKMOD_HD                       ((uint32_t)0x00000000)    /* Half-duplex mode */
+#define ETH_MACPHYCSR_LNKMOD_FD_Pos                   (16U)
+#define ETH_MACPHYCSR_LNKMOD_FD_Msk                   (0x1UL << ETH_MACPHYCSR_LNKMOD_FD_Pos) /*!< 0x00010000 */
+#define ETH_MACPHYCSR_LNKMOD_FD                       ETH_MACPHYCSR_LNKMOD_FD_Msk  /* Full-duplex mode */
+#define ETH_MACPHYCSR_LUD_Pos                         (1U)
+#define ETH_MACPHYCSR_LUD_Msk                         (0x1UL << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD                             ETH_MACPHYCSR_LUD_Msk  /* Link Up or Down */
+#define ETH_MACPHYCSR_LUD_LD                          ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LUD_LU_Pos                      (1U)
+#define ETH_MACPHYCSR_LUD_LU_Msk                      (0x1UL << ETH_MACPHYCSR_LUD_LU_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD_LU                          ETH_MACPHYCSR_LUD_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_TC_Pos                          (0U)
+#define ETH_MACPHYCSR_TC_Msk                          (0x1UL << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
+#define ETH_MACPHYCSR_TC                              ETH_MACPHYCSR_TC_Msk  /* Transmit Configuration in RGMII */
+
+/************ Bit definition for Ethernet MAC Version Register   ***************/
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/************ Bit definition for Ethernet MAC Debug Register   ***************/
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/************ Bit definition for Ethernet MAC HW Feature 0 Register   ***************/
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos              (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII                  ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk /* RGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos              (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII                  ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Pos                (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Msk                (0x3UL << ETH_MACHWF0R_ACTPHYSEL_TBI_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI                    ETH_MACHWF0R_ACTPHYSEL_TBI_Msk /* TBI */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos               (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk               (0x5UL << ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos) /*!< 0x50000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI                   ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk /* RTBI */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Pos               (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Msk               (0x3UL << ETH_MACHWF0R_ACTPHYSEL_SMII_Pos) /*!< 0x60000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII                   ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/************ Bit definition for Ethernet MAC HW Feature 1 Register   ***************/
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_HASHTBLSZ_NOHASH                 ((uint32_t)0x00000000)   /* No Hash table */
+#define ETH_MACHWF1R_HASHTBLSZ_64_Pos                 (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_64_Msk                 (0x1UL << ETH_MACHWF1R_HASHTBLSZ_64_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_64                     ETH_MACHWF1R_HASHTBLSZ_64_Msk /* 64 */
+#define ETH_MACHWF1R_HASHTBLSZ_128_Pos                (25U)
+#define ETH_MACHWF1R_HASHTBLSZ_128_Msk                (0x1UL << ETH_MACHWF1R_HASHTBLSZ_128_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_128                    ETH_MACHWF1R_HASHTBLSZ_128_Msk /* 128 */
+#define ETH_MACHWF1R_HASHTBLSZ_256_Pos                (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_256_Msk                (0x3UL << ETH_MACHWF1R_HASHTBLSZ_256_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_256                    ETH_MACHWF1R_HASHTBLSZ_256_Msk /* 256 */
+#define ETH_MACHWF1R_POUOST_Pos                       (23U)
+#define ETH_MACHWF1R_POUOST_Msk                       (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_POUOST                           ETH_MACHWF1R_POUOST_Msk   /* One Step for PTP over UDP/IP Feature Enable */
+#define ETH_MACHWF1R_RAVSEL_Pos                       (21U)
+#define ETH_MACHWF1R_RAVSEL_Msk                       (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_RAVSEL                           ETH_MACHWF1R_RAVSEL_Msk   /* Rx Side Only AV Feature Enable */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_SPRAM_Pos                        (5U)
+#define ETH_MACHWF1R_SPRAM_Msk                        (0x1FUL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF1R_SPRAM                            ETH_MACHWF1R_SPRAM_Msk /* MTL Receive FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/************ Bit definition for Ethernet MAC HW Feature 2 Register   ***************/
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TDCSZ_Pos                        (22U)
+#define ETH_MACHWF2R_TDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_TDCSZ                            ETH_MACHWF2R_TDCSZ_Msk /* Tx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_TXCHCNT_1DMATXCH                 ((uint32_t)0x00000000) /* 1 DMA Tx Channel */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos             (18U)
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk             (0x1UL << ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH                 ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk  /* 2 DMA Tx Channels */
+#define ETH_MACHWF2R_RDCSZ_Pos                        (16U)
+#define ETH_MACHWF2R_RDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_RDCSZ                            ETH_MACHWF2R_RDCSZ_Msk /* Rx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (12U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_RXCHCNT_1DMARXCH                 ((uint32_t)0x00000000) /* 1 DMA Rx Channel */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos             (12U)
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk             (0x1UL << ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH                 ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk  /* 2 DMA Rx Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_TXQCNT_1MTLTXQ                   ((uint32_t)0x00000000) /* 1 MTL Tx queue */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos               (6U)
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk               (0x1UL << ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ                   ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk  /* 2 MTL Tx queue */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+#define ETH_MACHWF2R_RXQCNT_1MTLRXQ                   ((uint32_t)0x00000000) /* 1 MTL Rx queue */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos               (0U)
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk               (0x1UL << ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ                   ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk  /* 2 MTL Rx queue */
+
+/************ Bit definition for Ethernet MAC HW Feature 3 Register    ***************/
+#define ETH_MACHWF3R_ASP_Pos                          (28U)
+#define ETH_MACHWF3R_ASP_Msk                          (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP                              ETH_MACHWF3R_ASP_Msk /* Automotive Safety Package */
+#define ETH_MACHWF3R_ASP_NONE                         ((uint32_t)0x00000000) /* None */
+#define ETH_MACHWF3R_ASP_ECC_Pos                      (28U)
+#define ETH_MACHWF3R_ASP_ECC_Msk                      (0x1UL << ETH_MACHWF3R_ASP_ECC_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF3R_ASP_ECC                          ETH_MACHWF3R_ASP_ECC_Msk  /* ECC only */
+#define ETH_MACHWF3R_ASP_ASNPPE_Pos                   (29U)
+#define ETH_MACHWF3R_ASP_ASNPPE_Msk                   (0x1UL << ETH_MACHWF3R_ASP_ASNPPE_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF3R_ASP_ASNPPE                       ETH_MACHWF3R_ASP_ASNPPE_Msk  /* AS_NPPE */
+#define ETH_MACHWF3R_ASP_ASPPE_Pos                    (28U)
+#define ETH_MACHWF3R_ASP_ASPPE_Msk                    (0x3UL << ETH_MACHWF3R_ASP_ASPPE_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP_ASPPE                        ETH_MACHWF3R_ASP_ASPPE_Msk  /* AS_PPE */
+#define ETH_MACHWF3R_TBSSEL_Pos                       (27U)
+#define ETH_MACHWF3R_TBSSEL_Msk                       (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF3R_TBSSEL                           ETH_MACHWF3R_TBSSEL_Msk /* Time-based scheduling Enable */
+#define ETH_MACHWF3R_FPESEL_Pos                       (26U)
+#define ETH_MACHWF3R_FPESEL_Msk                       (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF3R_FPESEL                           ETH_MACHWF3R_FPESEL_Msk /* Frame Preemption Enable */
+#define ETH_MACHWF3R_ESTWID_Pos                       (20U)
+#define ETH_MACHWF3R_ESTWID_Msk                       (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID                           ETH_MACHWF3R_ESTWID_Msk /* Width of the Time Interval field in the Gate Control List */
+#define ETH_MACHWF3R_ESTWID_NOWIDTH                   ((uint32_t)0x00000000) /* No Width */
+#define ETH_MACHWF3R_ESTWID_16_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_16_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_16_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF3R_ESTWID_16                        ETH_MACHWF3R_ESTWID_16_Msk  /* 16 Width */
+#define ETH_MACHWF3R_ESTWID_20_Pos                    (21U)
+#define ETH_MACHWF3R_ESTWID_20_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_20_Pos) /*!< 0x00200000 */
+#define ETH_MACHWF3R_ESTWID_20                        ETH_MACHWF3R_ESTWID_20_Msk  /* 20 Width */
+#define ETH_MACHWF3R_ESTWID_24_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_24_Msk                    (0x3UL << ETH_MACHWF3R_ESTWID_24_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID_24                        ETH_MACHWF3R_ESTWID_24_Msk  /* 24 Width */
+#define ETH_MACHWF3R_ESTDEP_Pos                       (17U)
+#define ETH_MACHWF3R_ESTDEP_Msk                       (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */
+#define ETH_MACHWF3R_ESTDEP                           ETH_MACHWF3R_ESTDEP_Msk /* Depth of the Gate Control List */
+#define ETH_MACHWF3R_ESTDEP_NODEPTH                   ((uint32_t)0x00000000) /* No depth */
+#define ETH_MACHWF3R_ESTDEP_64_Pos                    (17U)
+#define ETH_MACHWF3R_ESTDEP_64_Msk                    (0x1UL << ETH_MACHWF3R_ESTDEP_64_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF3R_ESTDEP_64                        ETH_MACHWF3R_ESTDEP_64_Msk  /* 64 depth */
+#define ETH_MACHWF3R_ESTDEP_128_Pos                   (18U)
+#define ETH_MACHWF3R_ESTDEP_128_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_128_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF3R_ESTDEP_128                       ETH_MACHWF3R_ESTDEP_128_Msk  /* 128 depth */
+#define ETH_MACHWF3R_ESTDEP_256_Pos                   (17U)
+#define ETH_MACHWF3R_ESTDEP_256_Msk                   (0x3UL << ETH_MACHWF3R_ESTDEP_256_Pos) /*!< 0x00060000 */
+#define ETH_MACHWF3R_ESTDEP_256                       ETH_MACHWF3R_ESTDEP_256_Msk  /* 256 depth */
+#define ETH_MACHWF3R_ESTDEP_512_Pos                   (19U)
+#define ETH_MACHWF3R_ESTDEP_512_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_512_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF3R_ESTDEP_512                       ETH_MACHWF3R_ESTDEP_512_Msk  /* 512 depth */
+#define ETH_MACHWF3R_ESTDEP_1024_Pos                  (17U)
+#define ETH_MACHWF3R_ESTDEP_1024_Msk                  (0x5UL << ETH_MACHWF3R_ESTDEP_1024_Pos) /*!< 0x000A0000 */
+#define ETH_MACHWF3R_ESTDEP_1024                      ETH_MACHWF3R_ESTDEP_1024_Msk  /* 1024 depth */
+#define ETH_MACHWF3R_ESTSEL_Pos                       (16U)
+#define ETH_MACHWF3R_ESTSEL_Msk                       (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF3R_ESTSEL                           ETH_MACHWF3R_ESTSEL_Msk  /* Enhancements to Scheduled Traffic Enable */
+#define ETH_MACHWF3R_FRPES_Pos                        (13U)
+#define ETH_MACHWF3R_FRPES_Msk                        (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */
+#define ETH_MACHWF3R_FRPES                            ETH_MACHWF3R_FRPES_Msk  /* Flexible Receive Parser Table Entries size */
+#define ETH_MACHWF3R_FRPES_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPES_128_Pos                    (13U)
+#define ETH_MACHWF3R_FRPES_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_128_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF3R_FRPES_128                        ETH_MACHWF3R_FRPES_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPES_256_Pos                    (14U)
+#define ETH_MACHWF3R_FRPES_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_256_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF3R_FRPES_256                        ETH_MACHWF3R_FRPES_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPBS_Pos                        (11U)
+#define ETH_MACHWF3R_FRPBS_Msk                        (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */
+#define ETH_MACHWF3R_FRPBS                            ETH_MACHWF3R_FRPBS_Msk  /* Flexible Receive Parser Buffer size */
+#define ETH_MACHWF3R_FRPBS_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPBS_128_Pos                    (11U)
+#define ETH_MACHWF3R_FRPBS_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_128_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF3R_FRPBS_128                        ETH_MACHWF3R_FRPBS_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPBS_256_Pos                    (12U)
+#define ETH_MACHWF3R_FRPBS_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_256_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF3R_FRPBS_256                        ETH_MACHWF3R_FRPBS_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPSEL_Pos                       (10U)
+#define ETH_MACHWF3R_FRPSEL_Msk                       (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */
+#define ETH_MACHWF3R_FRPSEL                           ETH_MACHWF3R_FRPSEL_Msk  /* Flexible Receive Parser Selected */
+#define ETH_MACHWF3R_PDUPSEL_Pos                      (9U)
+#define ETH_MACHWF3R_PDUPSEL_Msk                      (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF3R_PDUPSEL                          ETH_MACHWF3R_PDUPSEL_Msk  /* Broadcast/Multicast Packet Duplication */
+#define ETH_MACHWF3R_DVLAN_Pos                        (5U)
+#define ETH_MACHWF3R_DVLAN_Msk                        (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF3R_DVLAN                            ETH_MACHWF3R_DVLAN_Msk  /* Double VLAN processing enable */
+#define ETH_MACHWF3R_CBTISEL_Pos                      (4U)
+#define ETH_MACHWF3R_CBTISEL_Msk                      (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF3R_CBTISEL                          ETH_MACHWF3R_CBTISEL_Msk  /* Queue/Channel based VLAN tag insertion on Tx enable */
+#define ETH_MACHWF3R_NRVF_Pos                         (0U)
+#define ETH_MACHWF3R_NRVF_Msk                         (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */
+#define ETH_MACHWF3R_NRVF                             ETH_MACHWF3R_NRVF_Msk  /* Number of Extended VLAN Tag Filters Enabled */
+#define ETH_MACHWF3R_NRVF_NOEXRXVLANFLTR              ((uint32_t)0x00000000) /* No Extended Rx VLAN Filters */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos           (0U)
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR               ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos           (1U)
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR               ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk          (0x3UL << ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos) /*!< 0x00000003 */
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR              ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos          (2U)
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk          (0x1UL << ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR              ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk          (0x5UL << ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos) /*!< 0x00000005 */
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR              ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk
+
+/************ Bit definition for Ethernet MAC MDIO Address Register   ***************/
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV204_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV204_Msk                   (0x3UL << ETH_MACMDIOAR_CR_DIV204_Pos) /*!< 0x00000600 */
+#define ETH_MACMDIOAR_CR_DIV204                       ETH_MACMDIOAR_CR_DIV204_Msk /* CSR clock/204 */
+#define ETH_MACMDIOAR_CR_DIV324_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV324_Msk                   (0x7UL << ETH_MACMDIOAR_CR_DIV324_Pos) /*!< 0x00000700 */
+#define ETH_MACMDIOAR_CR_DIV324                       ETH_MACMDIOAR_CR_DIV324_Msk /* CSR clock/304 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_GOC_Pos                         (2U)
+#define ETH_MACMDIOAR_GOC_Msk                         (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_GOC_0                           (0x1U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000004 */
+#define ETH_MACMDIOAR_GOC_1                           (0x2U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000008 */
+#define ETH_MACMDIOAR_GOC                             ETH_MACMDIOAR_GOC_Msk    /* GMII Operation Command */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_GB_Pos                          (0U)
+#define ETH_MACMDIOAR_GB_Msk                          (0x1UL << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_GB                              ETH_MACMDIOAR_GB_Msk     /* GMII Busy */
+
+/************ Bit definition for Ethernet MAC MDIO Data Register   ***************/
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_GD_Pos                          (0U)
+#define ETH_MACMDIODR_GD_Msk                          (0xFFFFUL << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_GD                              ETH_MACMDIODR_GD_Msk     /* GMII Data */
+
+/************ Bit definition for Ethernet ARP Address Register    ***************/
+#define ETH_MACARPAR_ARPPA_Pos                        (0U)
+#define ETH_MACARPAR_ARPPA_Msk                        (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                            ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/************ Bit definition for Ethernet MAC CSR software control Register   ***************/
+#define ETH_MACCSRSWCR_SEEN_Pos                       (8U)
+#define ETH_MACCSRSWCR_SEEN_Msk                       (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */
+#define ETH_MACCSRSWCR_SEEN                           ETH_MACCSRSWCR_SEEN_Msk /* Slave Error Response Enable */
+#define ETH_MACCSRSWCR_RCWE_Pos                       (0U)
+#define ETH_MACCSRSWCR_RCWE_Msk                       (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */
+#define ETH_MACCSRSWCR_RCWE                           ETH_MACCSRSWCR_RCWE_Msk /* Register Clear on Write 1 Enable */
+
+/************ Bit definition for Ethernet MAC FPE control and status Register   ***************/
+#define ETH_MACFPECSR_TRSP_Pos                        (19U)
+#define ETH_MACFPECSR_TRSP_Msk                        (0x1UL << ETH_MACFPECSR_TRSP_Pos) /*!< 0x00080000 */
+#define ETH_MACFPECSR_TRSP                            ETH_MACFPECSR_TRSP_Msk /* Transmitted Respond Frame */
+#define ETH_MACFPECSR_TVER_Pos                        (18U)
+#define ETH_MACFPECSR_TVER_Msk                        (0x1UL << ETH_MACFPECSR_TVER_Pos) /*!< 0x00040000 */
+#define ETH_MACFPECSR_TVER                            ETH_MACFPECSR_TVER_Msk /* Transmitted Verify Frame */
+#define ETH_MACFPECSR_RRSP_Pos                        (17U)
+#define ETH_MACFPECSR_RRSP_Msk                        (0x1UL << ETH_MACFPECSR_RRSP_Pos) /*!< 0x00020000 */
+#define ETH_MACFPECSR_RRSP                            ETH_MACFPECSR_RRSP_Msk /* Received Respond Frame */
+#define ETH_MACFPECSR_RVER_Pos                        (16U)
+#define ETH_MACFPECSR_RVER_Msk                        (0x1UL << ETH_MACFPECSR_RVER_Pos) /*!< 0x00010000 */
+#define ETH_MACFPECSR_RVER                            ETH_MACFPECSR_RVER_Msk /* Received Verify Frame */
+#define ETH_MACFPECSR_SRSP_Pos                        (2U)
+#define ETH_MACFPECSR_SRSP_Msk                        (0x1UL << ETH_MACFPECSR_SRSP_Pos) /*!< 0x00000004 */
+#define ETH_MACFPECSR_SRSP                            ETH_MACFPECSR_SRSP_Msk /* Send Respond mPacket */
+#define ETH_MACFPECSR_SVER_Pos                        (1U)
+#define ETH_MACFPECSR_SVER_Msk                        (0x1UL << ETH_MACFPECSR_SVER_Pos) /*!< 0x00000002 */
+#define ETH_MACFPECSR_SVER                            ETH_MACFPECSR_SVER_Msk /* Send Verify mPacket */
+#define ETH_MACFPECSR_EFPE_Pos                        (0U)
+#define ETH_MACFPECSR_EFPE_Msk                        (0x1UL << ETH_MACFPECSR_EFPE_Pos) /*!< 0x00000001 */
+#define ETH_MACFPECSR_EFPE                            ETH_MACFPECSR_EFPE_Msk /* Enable Tx Frame Preemption */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMR_MPTN_Pos                        (0U)
+#define ETH_MACPRSTIMR_MPTN_Msk                        (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMR_MPTN                            ETH_MACPRSTIMR_MPTN_Msk /* MAC 1722 Presentation Time in ns */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMUR_MPTU_Pos                       (0U)
+#define ETH_MACPRSTIMUR_MPTU_Msk                       (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMUR_MPTU                           ETH_MACPRSTIMUR_MPTU_Msk /* MAC 1722 Presentation Time Update */
+
+/************ Bit definition for Ethernet MAC Address 0 High Register   ***************/
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_DCS_Pos                           (16U)
+#define ETH_MACA0HR_DCS_Msk                           (0x1UL << ETH_MACA0HR_DCS_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_DCS                               ETH_MACA0HR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/************ Bit definition for Ethernet MAC Address x Low Register   ***************/
+#define ETH_MACAxLR_ADDRLO_Pos                        (0U)
+#define ETH_MACAxLR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACAxLR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACAxLR_ADDRLO                            ETH_MACAxLR_ADDRLO_Msk   /* MAC Address x*/
+
+/************ Bit definition for Ethernet MAC Address x High Register  ***************/
+#define ETH_MACAxHR_AE_Pos                            (31U)
+#define ETH_MACAxHR_AE_Msk                            (0x1UL << ETH_MACAxHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAxHR_AE                                ETH_MACAxHR_AE_Msk /* Address Enable*/
+#define ETH_MACAxHR_SA_Pos                            (30U)
+#define ETH_MACAxHR_SA_Msk                            (0x1UL << ETH_MACAxHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAxHR_SA                                ETH_MACAxHR_SA_Msk /* Source Address */
+#define ETH_MACAxHR_MBC_Pos                           (24U)
+#define ETH_MACAxHR_MBC_Msk                           (0x3FUL << ETH_MACAxHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAxHR_MBC                               ETH_MACAxHR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACAxHR_DCS_Pos                           (16U)
+#define ETH_MACAxHR_DCS_Msk                           (0x1UL << ETH_MACAxHR_DCS_Pos) /*!< 0x00010000 */
+#define ETH_MACAxHR_DCS                               ETH_MACAxHR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACAxHR_ADDRHI_Pos                        (0U)
+#define ETH_MACAxHR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACAxHR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAxHR_ADDRHI                            ETH_MACAxHR_ADDRHI_Msk   /* MAC Address 1*/
+
+/************ Bit definition for Ethernet MMC Control Register   ***************/
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/************ Bit definition for Ethernet MMC Rx Interrupt Register  ***************/
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Register   ***************/
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Rx interrupt Mask Register   ***************/
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Mask Register   ***************/
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Single Collision Good Packets Register   ***************/
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register   ***************/
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Packet Count Good Register  ***************/
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/************ Bit definition for Ethernet MMC Rx CRC Error Packets Register  ***************/
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx alignment error packets Register   ***************/
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx Unicast Packets Good Register   ***************/
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/************ Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register   ***************/
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Tx LPI Transition Counter Register   ***************/
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register   ***************/
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Transition Counter Register   ***************/
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt status Register   ***************/
+#define ETH_MMCFPETISR_HRCIS_Pos                      (1U)
+#define ETH_MMCFPETISR_HRCIS_msk                      (0x1UL <<  ETH_MMCFPETISR_HRCIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETISR_HRCIS                          ETH_MMCFPETISR_HRCIS_msk /* MMC Tx Hold Request Counter Interrupt Status */
+#define ETH_MMCFPETISR_FCIS_Pos                       (0U)
+#define ETH_MMCFPETISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPETISR_FCIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETISR_FCIS                           ETH_MMCFPETISR_FCIS_msk /* MMC Tx FPE Fragment Counter Interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt mask Register   ***************/
+#define ETH_MMCFPETIMR_HRCIM_Pos                      (1U)
+#define ETH_MMCFPETIMR_HRCIM_msk                      (0x1UL <<  ETH_MMCFPETIMR_HRCIM_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETIMR_HRCIM                          ETH_MMCFPETIMR_HRCIM_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+#define ETH_MMCFPETIMR_FCIM_Pos                       (0U)
+#define ETH_MMCFPETIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPETIMR_FCIM_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETIMR_FCIM                           ETH_MMCFPETIMR_FCIM_msk /* MMC Transmit Fragment Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC FPE Tx fragment counter Register   ***************/
+#define ETH_MMCFPETFCR_TXFFC_Pos                      (0U)
+#define ETH_MMCFPETFCR_TXFFC_msk                      (0xFFFFFFFFUL <<  ETH_MMCFPETFCR_TXFFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPETFCR_TXFFC                          ETH_MMCFPETFCR_TXFFC_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx hold request counter Register   ***************/
+#define ETH_MMCTHRCR_TXHRC_Pos                        (0U)
+#define ETH_MMCTHRCR_TXHRC_msk                        (0xFFFFFFFFUL <<  ETH_MMCTHRCR_TXHRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTHRCR_TXHRC                            ETH_MMCTHRCR_TXHRC_msk /* Tx hold request counter */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt status Register   ***************/
+#define ETH_MMCFPERISR_FCIS_Pos                       (3U)
+#define ETH_MMCFPERISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPERISR_FCIS_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERISR_FCIS                           ETH_MMCFPERISR_FCIS_msk /* MMC Rx FPE Fragment Counter Interrupt Status */
+#define ETH_MMCFPERISR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERISR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERISR_PAOCIS                         ETH_MMCFPERISR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt status */
+#define ETH_MMCFPERISR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERISR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERISR_PSECIS                         ETH_MMCFPERISR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt status */
+#define ETH_MMCFPERISR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERISR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERISR_PAECIS                         ETH_MMCFPERISR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt mask Register   ***************/
+#define ETH_MMCFPERIMR_FCIM_Pos                       (3U)
+#define ETH_MMCFPERIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPERIMR_FCIM_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERIMR_FCIM                           ETH_MMCFPERIMR_FCIM_msk /* MMC Rx FPE Fragment Counter Interrupt Mask */
+#define ETH_MMCFPERIMR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERIMR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERIMR_PAOCIS                         ETH_MMCFPERIMR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt Mask */
+#define ETH_MMCFPERIMR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERIMR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERIMR_PSECIS                         ETH_MMCFPERIMR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt Mask */
+#define ETH_MMCFPERIMR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERIMR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERIMR_PAECIS                         ETH_MMCFPERIMR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly error Register   ***************/
+#define ETH_MMCRPAER_PAEC_Pos                         (0U)
+#define ETH_MMCRPAER_PAEC_msk                         (0xFFFFFFFFUL <<  ETH_MMCRPAER_PAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAER_PAEC                             ETH_MMCRPAER_PAEC_msk /* Rx Packet Assembly Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet SMD error Register   ***************/
+#define ETH_MMCRPSMDER_PSEC_Pos                       (0U)
+#define ETH_MMCRPSMDER_PSEC_msk                       (0xFFFFFFFFUL <<  ETH_MMCRPSMDER_PSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPSMDER_PSEC                           ETH_MMCRPSMDER_PSEC_msk /* Rx Packet SMD Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly OK Register   ***************/
+#define ETH_MMCRPAOKR_PAOC_Pos                        (0U)
+#define ETH_MMCRPAOKR_PAOC_msk                        (0xFFFFFFFFUL <<  ETH_MMCRPAOKR_PAOC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAOKR_PAOC                            ETH_MMCRPAOKR_PAOC_msk /* Rx Packet Assembly OK Counter */
+
+/************ Bit definition for Ethernet MMC Rx FPE fragments counter Register   ***************/
+#define ETH_MMCFPERFCR_FFC_Pos                        (0U)
+#define ETH_MMCFPERFCR_FFC_msk                        (0xFFFFFFFFUL <<  ETH_MMCFPERFCR_FFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPERFCR_FFC                            ETH_MMCFPERFCR_FFC_msk /* Rx FPE Fragment Counter */
+
+/************ Bit definition for Ethernet MAC L3 and L4 control 0 Register   ***************/
+#define ETH_MACL3L4C0R_DMCHEN0_Pos                     (28U)
+#define ETH_MACL3L4C0R_DMCHEN0_Msk                     (0x1UL << ETH_MACL3L4C0R_DMCHEN0_Pos) /*!< 0x10000000 */
+#define ETH_MACL3L4C0R_DMCHEN0                         ETH_MACL3L4C0R_DMCHEN0_Msk /* DMA Channel Select Enable */
+#define ETH_MACL3L4C0R_DMCHN0_Pos                      (24U)
+#define ETH_MACL3L4C0R_DMCHN0_Msk                      (0x1UL << ETH_MACL3L4C0R_DMCHN0_Pos) /*!< 0x01000000 */
+#define ETH_MACL3L4C0R_DMCHN0                          ETH_MACL3L4C0R_DMCHN0_Msk /* DMA Channel Number */
+#define ETH_MACL3L4C0R_L4DPIM0_Pos                     (21U)
+#define ETH_MACL3L4C0R_L4DPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4C0R_L4DPIM0                         ETH_MACL3L4C0R_L4DPIM0_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4DPM0_Pos                      (20U)
+#define ETH_MACL3L4C0R_L4DPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4C0R_L4DPM0                          ETH_MACL3L4C0R_L4DPM0_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4C0R_L4SPIM0_Pos                     (19U)
+#define ETH_MACL3L4C0R_L4SPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4C0R_L4SPIM0                         ETH_MACL3L4C0R_L4SPIM0_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4SPM0_Pos                      (18U)
+#define ETH_MACL3L4C0R_L4SPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4C0R_L4SPM0                          ETH_MACL3L4C0R_L4SPM0_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4C0R_L4PEN0_Pos                      (16U)
+#define ETH_MACL3L4C0R_L4PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4C0R_L4PEN0                          ETH_MACL3L4C0R_L4PEN0_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4C0R_L3HDBM0_Pos                     (11U)
+#define ETH_MACL3L4C0R_L3HDBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4C0R_L3HDBM0                         ETH_MACL3L4C0R_L3HDBM0_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3HSBM0_Pos                     (6U)
+#define ETH_MACL3L4C0R_L3HSBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4C0R_L3HSBM0                         ETH_MACL3L4C0R_L3HSBM0_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3DAIM0_Pos                     (5U)
+#define ETH_MACL3L4C0R_L3DAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4C0R_L3DAIM0                         ETH_MACL3L4C0R_L3DAIM0_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3DAM0_Pos                      (4U)
+#define ETH_MACL3L4C0R_L3DAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4C0R_L3DAM0                          ETH_MACL3L4C0R_L3DAM0_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4C0R_L3SAIM0_Pos                     (3U)
+#define ETH_MACL3L4C0R_L3SAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4C0R_L3SAIM0                         ETH_MACL3L4C0R_L3SAIM0_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3SAM0_Pos                      (2U)
+#define ETH_MACL3L4C0R_L3SAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4C0R_L3SAM0                          ETH_MACL3L4C0R_L3SAM0_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4C0R_L3PEN0_Pos                      (0U)
+#define ETH_MACL3L4C0R_L3PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4C0R_L3PEN0                          ETH_MACL3L4C0R_L3PEN0_Msk  /* Layer 3 Protocol Enable */
+
+/************ Bit definition for Ethernet MAC Layer4 Address filter Register   ***************/
+#define ETH_MACL4A0R_L4DP0_Pos                        (16U)
+#define ETH_MACL4A0R_L4DP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4A0R_L4DP0                            ETH_MACL4A0R_L4DP0_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4A0R_L4SP0_Pos                        (0U)
+#define ETH_MACL4A0R_L4SP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4A0R_L4SP0                            ETH_MACL4A0R_L4SP0_Msk     /* Layer 4 Source Port Number Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 0 Register   ***************/
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 1 Register   ***************/
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 2 Register   ***************/
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 3 Register   ***************/
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/************ Bit definition for Ethernet MAC Indirect Access Control Register   ***************/
+#define ETH_MACIACR_MSEL_Pos                           (16U)
+#define ETH_MACIACR_MSEL_Msk                           (0xFUL << ETH_MACIACR_MSEL_Pos) /*!< 0x000F0000 */
+#define ETH_MACIACR_MSEL                               ETH_MACIACR_MSEL_Msk    /* Mode Select */
+#define ETH_MACIACR_MSEL_RXQ                           ((uint32_t)0x00000000)   /* Type-based RXQ mapping */
+#define ETH_MACIACR_AOFF_Pos                           (8U)
+#define ETH_MACIACR_AOFF_Msk                           (0xFFUL << ETH_MACIACR_AOFF_Pos) /*!< 0x0000FF00 */
+#define ETH_MACIACR_AOFF                               ETH_MACIACR_AOFF_Msk    /* Address Offset */
+#define ETH_MACIACR_AOFF_IndReg0                       ((uint32_t)0x00000000)   /* Indirect register 0 */
+#define ETH_MACIACR_AOFF_IndReg1_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg1_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg1_Pos) /*!< 0x00000100 */
+#define ETH_MACIACR_AOFF_IndReg1                       ETH_MACIACR_AOFF_IndReg1_Msk  /* Indirect register 1 */
+#define ETH_MACIACR_AOFF_IndReg2_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg2_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg2_Pos) /*!< 0x00000200 */
+#define ETH_MACIACR_AOFF_IndReg2                       ETH_MACIACR_AOFF_IndReg2_Msk  /* Indirect register 2 */
+#define ETH_MACIACR_AOFF_IndReg3_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg3_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg3_Pos) /*!< 0x00000300 */
+#define ETH_MACIACR_AOFF_IndReg3                       ETH_MACIACR_AOFF_IndReg3_Msk  /* Indirect register 3 */
+#define ETH_MACIACR_AOFF_IndReg4_Pos                   (10U)
+#define ETH_MACIACR_AOFF_IndReg4_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg4_Pos) /*!< 0x00000400 */
+#define ETH_MACIACR_AOFF_IndReg4                       ETH_MACIACR_AOFF_IndReg4_Msk  /* Indirect register 4 */
+#define ETH_MACIACR_AOFF_IndReg5_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg5_Msk                   (0x5UL << ETH_MACIACR_AOFF_IndReg5_Pos) /*!< 0x00000500 */
+#define ETH_MACIACR_AOFF_IndReg5                       ETH_MACIACR_AOFF_IndReg5_Msk  /* Indirect register 5 */
+#define ETH_MACIACR_AOFF_IndReg6_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg6_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg6_Pos) /*!< 0x00000600 */
+#define ETH_MACIACR_AOFF_IndReg6                       ETH_MACIACR_AOFF_IndReg6_Msk  /* Indirect register 6 */
+#define ETH_MACIACR_AOFF_IndReg7_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg7_Msk                   (0x7UL << ETH_MACIACR_AOFF_IndReg7_Pos) /*!< 0x00000700 */
+#define ETH_MACIACR_AOFF_IndReg7                       ETH_MACIACR_AOFF_IndReg7_Msk  /* Indirect register 7 */
+#define ETH_MACIACR_AUTO_Pos                           (5U)
+#define ETH_MACIACR_AUTO_Msk                           (0x1UL << ETH_MACIACR_AUTO_Pos) /*!< 0x00000020 */
+#define ETH_MACIACR_AUTO                               ETH_MACIACR_AUTO_Msk    /* Auto-increment */
+#define ETH_MACIACR_COM_Pos                            (1U)
+#define ETH_MACIACR_COM_Msk                            (0x1UL << ETH_MACIACR_COM_Pos) /*!< 0x00000002 */
+#define ETH_MACIACR_COM                                ETH_MACIACR_COM_Msk    /* Command type: 1: read operation / 0: write operation */
+#define ETH_MACIACR_OB_Pos                             (0U)
+#define ETH_MACIACR_OB_Msk                             (0x1UL << ETH_MACIACR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACIACR_OB                                 ETH_MACIACR_OB_Msk    /* Operation Busy */
+
+/************ Bit definition for Ethernet MAC type-based Rx Queue mapping Register   ***************/
+#define ETH_MACTMRQR_PFEX_Pos                          (20U)
+#define ETH_MACTMRQR_PFEX_Msk                          (0x1UL << ETH_MACTMRQR_PFEX_Pos) /*!< 0x00100000 */
+#define ETH_MACTMRQR_PFEX                              ETH_MACTMRQR_PFEX_Msk    /* Preemption or Express Packet */
+#define ETH_MACTMRQR_TMRQ_Pos                          (16U)
+#define ETH_MACTMRQR_TMRQ_Msk                          (0x7UL << ETH_MACTMRQR_TMRQ_Pos) /*!< 0x00070000 */
+#define ETH_MACTMRQR_TMRQ                              ETH_MACTMRQR_TMRQ_Msk    /* Type Match Rx Queue Number */
+#define ETH_MACTMRQR_TYP_Pos                           (0U)
+#define ETH_MACTMRQR_TYP_Msk                           (0xFFFFUL << ETH_MACTMRQR_TYP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACTMRQR_TYP                               ETH_MACTMRQR_TYP_Msk    /* Type field Value */
+
+/************ Bit definition for Ethernet MAC Timestamp Control Register   ***************/
+#define ETH_MACTSCR_AV8021ASMEN_Pos                   (28U)
+#define ETH_MACTSCR_AV8021ASMEN_Msk                   (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
+#define ETH_MACTSCR_AV8021ASMEN                       ETH_MACTSCR_AV8021ASMEN_Msk  /* AV 802.1AS Mode Enable */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_ESTI_Pos                          (20U)
+#define ETH_MACTSCR_ESTI_Msk                          (0x1UL << ETH_MACTSCR_ESTI_Pos) /*!< 0x00100000 */
+#define ETH_MACTSCR_ESTI                              ETH_MACTSCR_ESTI_Msk  /* External System Time Input */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_PTGE_Pos                          (6U)
+#define ETH_MACTSCR_PTGE_Msk                          (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */
+#define ETH_MACTSCR_PTGE                              ETH_MACTSCR_PTGE_Msk  /* Presentation Time Generation Enable */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/************ Bit definition for Ethernet MAC Sub-second Increment Register   ***************/
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Register   ***************/
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Register   ***************/
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Update Register   ***************/
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Update Register   ***************/
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Addend Register   ***************/
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/************ Bit definition for Ethernet MAC Timestamp Status Register   ***************/
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR1_Pos                    (5U)
+#define ETH_MACTSSR_TSTRGTERR1_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR1_Pos) /*!< 0x00000020 */
+#define ETH_MACTSSR_TSTRGTERR1                        ETH_MACTSSR_TSTRGTERR1_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_TSTARGT1_Pos                      (4U)
+#define ETH_MACTSSR_TSTARGT1_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT1_Pos) /*!< 0x00000010 */
+#define ETH_MACTSSR_TSTARGT1                          ETH_MACTSSR_TSTARGT1_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register   ***************/
+#define ETH_MACTXTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTXTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTXTSSNR_TXTSSMIS                        ETH_MACTXTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTXTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTXTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTXTSSNR_TXTSSLO                         ETH_MACTXTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register   ***************/
+#define ETH_MACTXTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTXTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTXTSSSR_TXTSSHI                         ETH_MACTXTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/************ Bit definition for Ethernet MAC Auxiliary Control Register   ***************/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register   ***************/
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register   ***************/
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register   ***************/
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction  ***************/
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond   ***************/
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond   ***************/
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Latency   ***************/
+#define ETH_MACTSILR_ITLNS_Pos                        (16U)
+#define ETH_MACTSILR_ITLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSILR_ITLNS                            ETH_MACTSILR_ITLNS_Msk  /* Ingress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSILR_ITLSNS_Pos                       (8U)
+#define ETH_MACTSILR_ITLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSILR_ITLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Ingress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Latency Register   ***************/
+#define ETH_MACTSELR_ETLNS_Pos                        (16U)
+#define ETH_MACTSELR_ETLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSELR_ETLNS                            ETH_MACTSILR_ITLNS_Msk  /* Egress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSELR_ETLSNS_Pos                       (8U)
+#define ETH_MACTSELR_ETLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSELR_ETLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Egress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC PPS Control Register   ***************/
+#define ETH_MACPPSCR_TIMESEL_Pos                      (28U)
+#define ETH_MACPPSCR_TIMESEL_Msk                      (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSCR_TIMESEL                          ETH_MACPPSCR_TIMESEL_Msk  /* Time Select */
+#define ETH_MACPPSCR_MCGREN0_Pos                      (7U)
+#define ETH_MACPPSCR_MCGREN0_Msk                      (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0                          ETH_MACPPSCR_MCGREN0_Msk  /* MCGR Mode Enable for PPS0 Output */
+#define ETH_MACPPSCR_MCGREN0_PPS                      ((uint32_t)0x00000000)   /* PPS mode */
+#define ETH_MACPPSCR_MCGREN0_MCGR_Pos                 (7U)
+#define ETH_MACPPSCR_MCGREN0_MCGR_Msk                 (0x1UL << ETH_MACPPSCR_MCGREN0_MCGR_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0_MCGR                     ETH_MACPPSCR_MCGREN0_MCGR_Msk  /* MCGR mode */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/************ Bit definition for Ethernet MAC PPS x target time seconds Register   ***************/
+#define ETH_MACPPSTTSxR_TSTRH0_Pos                    (0U)
+#define ETH_MACPPSTTSxR_TSTRH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSTTSxR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSxR_TSTRH0                        ETH_MACPPSTTSxR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/************ Bit definition for Ethernet MAC PPS x target time nanoseconds Register   ***************/
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Pos                 (31U)
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Msk                 (0x1UL << ETH_MACPPSTTNxR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNxR_TRGTBUSY0                     ETH_MACPPSTTNxR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNxR_TTSL0_Pos                     (0U)
+#define ETH_MACPPSTTNxR_TTSL0_Msk                     (0x7FFFFFFFUL << ETH_MACPPSTTNxR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNxR_TTSL0                         ETH_MACPPSTTNxR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/************ Bit definition for Ethernet MAC PPS x Interval Register   ***************/
+#define ETH_MACPPSIxR_PPSINT0_Pos                     (0U)
+#define ETH_MACPPSIxR_PPSINT0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSIxR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIxR_PPSINT0                         ETH_MACPPSIxR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/************ Bit definition for Ethernet MAC PPS x Width Register   ***************/
+#define ETH_MACPPSWxR_PPSWIDTH0_Pos                   (0U)
+#define ETH_MACPPSWxR_PPSWIDTH0_Msk                   (0xFFFFFFFFUL << ETH_MACPPSWxR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWxR_PPSWIDTH0                       ETH_MACPPSWxR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/************ Bit definition for Ethernet MAC PTP Offload Control Register   ***************/
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_PDRDIS_Pos                        (7U)
+#define ETH_MACPOCR_PDRDIS_Msk                        (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */
+#define ETH_MACPOCR_PDRDIS                            ETH_MACPOCR_PDRDIS_Msk  /* Disable Peer Delay Response response generation */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 0 Register   ***************/
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 1 Register   ***************/
+#define ETH_MACSPI1R_SPI1_Pos                        (0U)
+#define ETH_MACSPI1R_SPI1_Msk                        (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                            ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 2 Register   ***************/
+#define ETH_MACSPI2R_SPI2_Pos                        (0U)
+#define ETH_MACSPI2R_SPI2_Msk                        (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                            ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/************ Bit definition for Ethernet MAC Log Message Interval Register   ***************/
+#define ETH_MACLMIR_LMPDRI_Pos                       (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                       (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                            ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                      (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                      (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                          ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                          (0U)
+#define ETH_MACLMIR_LSI_Msk                          (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                              ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/************ Bit definition for Ethernet MTL Operation Mode Register   ***************/
+#define ETH_MTLOMR_CNTCLR_Pos                        (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                        (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                            ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                       (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                       (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                           ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_SCHALG_Pos                        (5U)
+#define ETH_MTLOMR_SCHALG_Msk                        (0x3UL << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG                            ETH_MTLOMR_SCHALG_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_SCHALG_WRR                        ((uint32_t)0x00000000)   /* Weighted round robin (WRR) algorithm */
+#define ETH_MTLOMR_SCHALG_SP_Pos                     (5U)
+#define ETH_MTLOMR_SCHALG_SP_Msk                     (0x3UL << ETH_MTLOMR_SCHALG_SP_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG_SP                         ETH_MTLOMR_SCHALG_SP_Msk  /* Strict priority (SP) algorithm */
+#define ETH_MTLOMR_RAA_Pos                           (2U)
+#define ETH_MTLOMR_RAA_Msk                           (0x1UL << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA                               ETH_MTLOMR_RAA_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_RAA_SP                            ((uint32_t)0x00000000)   /* Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest */
+#define ETH_MTLOMR_RAA_WSP_Pos                       (2U)
+#define ETH_MTLOMR_RAA_WSP_Msk                       (0x1UL << ETH_MTLOMR_RAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA_WSP                           ETH_MTLOMR_RAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_MTLOMR_DTXSTS_Pos                        (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                        (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                            ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/************ Bit definition for Ethernet MTL Interrupt Status Register   ***************/
+#define ETH_MTLISR_ESTIS_Pos                          (18U)
+#define ETH_MTLISR_ESTIS_Msk                          (0x1UL << ETH_MTLISR_ESTIS_Pos) /*!< 0x00040000 */
+#define ETH_MTLISR_ESTIS                              ETH_MTLISR_ESTIS_Msk     /* EST (TAS- 802.1Qbv) Interrupt Status */
+#define ETH_MTLISR_Q1IS_Pos                           (1U)
+#define ETH_MTLISR_Q1IS_Msk                           (0x1UL << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
+#define ETH_MTLISR_Q1IS                               ETH_MTLISR_Q1IS_Msk       /* Queue 1 Interrupt status */
+#define ETH_MTLISR_Q0IS_Pos                           (0U)
+#define ETH_MTLISR_Q0IS_Msk                           (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_Q0IS                               ETH_MTLISR_Q0IS_Msk       /* Queue 0 Interrupt status */
+
+/************ Bit definition for Ethernet MTL Rx Queue and DMA Channel Mapping   ***************/
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Pos                 (12U)
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1DDMACH_Pos) /*!< 0x00001000 */
+#define ETH_MTLRXQDMAMR_Q1DDMACH                     ETH_MTLRXQDMAMR_Q1DDMACH_Msk /* Queue 1 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Pos                 (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH                     ETH_MTLRXQDMAMR_Q1MDMACH_Msk /* Queue 1 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos          (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk /* DMA Channel 1 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Pos                 (4U)
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0DDMACH_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH                     ETH_MTLRXQDMAMR_Q0DDMACH_Msk /* Queue 0 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Pos                 (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH                     ETH_MTLRXQDMAMR_Q0MDMACH_Msk /* Queue 0 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos          (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk /* DMA Channel 1 */
+
+/************ Bit definition for Ethernet MTL TBS control Register   ***************/
+#define ETH_MTLTBSCR_LEOS_Pos                       (8U)
+#define ETH_MTLTBSCR_LEOS_Msk                       (0xFFFFFFUL << ETH_MTLTBSCR_LEOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEOS                           ETH_MTLTBSCR_LEOS_Msk /* Launch Expiry Offset */
+#define ETH_MTLTBSCR_LEGOS_Pos                      (4U)
+#define ETH_MTLTBSCR_LEGOS_Msk                      (0x7UL << ETH_MTLTBSCR_LEGOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEGOS                          ETH_MTLTBSCR_LEGOS_Msk /* Launch Expiry GSN Offset */
+#define ETH_MTLTBSCR_LEOV_Pos                       (1U)
+#define ETH_MTLTBSCR_LEOV_Msk                       (0x1UL << ETH_MTLTBSCR_LEOV_Pos) /*!< 0x00000002 */
+#define ETH_MTLTBSCR_LEOV                           ETH_MTLTBSCR_LEOV_Msk /* Launch expiry offset valid */
+#define ETH_MTLTBSCR_ESTM_Pos                       (0U)
+#define ETH_MTLTBSCR_ESTM_Msk                       (0x1UL << ETH_MTLTBSCR_ESTM_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM                           ETH_MTLTBSCR_ESTM_Msk /* EST offset mode */
+#define ETH_MTLTBSCR_ESTM_ESTOFFDIS                 ((uint32_t)0x00000000)   /* EST offset mode disabled */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos              (0U)
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk              (0x1UL << ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN                   ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk  /* EST offset mode enabled */
+
+/************ Bit definition for Ethernet MTL EST Control Register   ***************/
+#define ETH_MTLESTCR_PTOV_Pos                       (24U)
+#define ETH_MTLESTCR_PTOV_Msk                       (0xFFFFFFUL << ETH_MTLESTCR_PTOV_Pos) /*!< 0xFF000000 */
+#define ETH_MTLESTCR_PTOV                           ETH_MTLESTCR_PTOV_Msk /* PTP Time Offset Value */
+#define ETH_MTLESTCR_CTOV_Pos                       (12U)
+#define ETH_MTLESTCR_CTOV_Msk                       (0xFFFUL << ETH_MTLESTCR_CTOV_Pos) /*!< 0x00FFF000 */
+#define ETH_MTLESTCR_CTOV                           ETH_MTLESTCR_CTOV_Msk /* Current Time Offset Value */
+#define ETH_MTLESTCR_TILS_Pos                       (8U)
+#define ETH_MTLESTCR_TILS_Msk                       (0x7UL << ETH_MTLESTCR_TILS_Pos) /*!< 0x00000700 */
+#define ETH_MTLESTCR_TILS                           ETH_MTLESTCR_TILS_Msk /* Time Interval Left Shift Amount */
+#define ETH_MTLESTCR_LCSE_Pos                       (6U)
+#define ETH_MTLESTCR_LCSE_Msk                       (0x3UL << ETH_MTLESTCR_LCSE_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE                           ETH_MTLESTCR_LCSE_Msk /* Loop Count to report Scheduling Error */
+#define ETH_MTLESTCR_LCSE_4IT                       ((uint32_t)0x00000000)   /* 4 iterations */
+#define ETH_MTLESTCR_LCSE_8IT_Pos                   (6U)
+#define ETH_MTLESTCR_LCSE_8IT_Msk                   (0x1UL << ETH_MTLESTCR_LCSE_8IT_Pos) /*!< 0x00000040 */
+#define ETH_MTLESTCR_LCSE_8IT                       ETH_MTLESTCR_LCSE_8IT_Msk   /* 8 iterations */
+#define ETH_MTLESTCR_LCSE_16IT_Pos                  (7U)
+#define ETH_MTLESTCR_LCSE_16IT_Msk                  (0x1UL << ETH_MTLESTCR_LCSE_16IT_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTCR_LCSE_16IT                      ETH_MTLESTCR_LCSE_16IT_Msk  /* 16 iterations */
+#define ETH_MTLESTCR_LCSE_32IT_Pos                  (6U)
+#define ETH_MTLESTCR_LCSE_32IT_Msk                  (0x3UL << ETH_MTLESTCR_LCSE_32IT_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE_32IT                      ETH_MTLESTCR_LCSE_32IT_Msk  /* 32 iterations */
+#define ETH_MTLESTCR_DFBS_Pos                       (5U)
+#define ETH_MTLESTCR_DFBS_Msk                       (0x1UL << ETH_MTLESTCR_DFBS_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTCR_DFBS                           ETH_MTLESTCR_DFBS_Msk /* Drop Frames causing Scheduling Error */
+#define ETH_MTLESTCR_DDBF_Pos                       (4U)
+#define ETH_MTLESTCR_DDBF_Msk                       (0x1UL << ETH_MTLESTCR_DDBF_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTCR_DDBF                           ETH_MTLESTCR_DDBF_Msk /* Do not Drop frames during Frame Size Error */
+#define ETH_MTLESTCR_SSWL_Pos                       (1U)
+#define ETH_MTLESTCR_SSWL_Msk                       (0x1UL << ETH_MTLESTCR_SSWL_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTCR_SSWL                           ETH_MTLESTCR_SSWL_Msk /* Switch to S/W owned list */
+#define ETH_MTLESTCR_EEST_Pos                       (0U)
+#define ETH_MTLESTCR_EEST_Msk                       (0x1UL << ETH_MTLESTCR_EEST_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTCR_EEST                           ETH_MTLESTCR_EEST_Msk /* Enable EST */
+
+/************ Bit definition for Ethernet MTL EST Extended Control Register   ***************/
+/* Bit definition for Ethernet MTL EST Extended Control Register */
+#define ETH_MTLESTECR_OVHD_Pos                       (0U)
+#define ETH_MTLESTECR_OVHD_Msk                       (0x3FUL << ETH_MTLESTECR_OVHD_Pos) /*!< 0x0000003F */
+#define ETH_MTLESTECR_OVHD                           ETH_MTLESTECR_OVHD_Msk /* Overhead Bytes Value */
+
+/************ Bit definition for Ethernet MTL EST Status Register   ***************/
+#define ETH_MTLESTSR_CGSN_Pos                       (16U)
+#define ETH_MTLESTSR_CGSN_Msk                       (0xFUL << ETH_MTLESTSR_CGSN_Pos) /*!< 0x000F0000 */
+#define ETH_MTLESTSR_CGSN                           ETH_MTLESTSR_CGSN_Msk /* Current GCL slot number */
+#define ETH_MTLESTSR_BTRL_Pos                       (8U)
+#define ETH_MTLESTSR_BTRL_Msk                       (0xFFUL << ETH_MTLESTSR_BTRL_Pos) /*!< 0x00000F00 */
+#define ETH_MTLESTSR_BTRL                           ETH_MTLESTSR_CGSN_Msk /* BTR Error Loop Count */
+#define ETH_MTLESTSR_SWOL_Pos                       (7U)
+#define ETH_MTLESTSR_SWOL_Msk                       (0x1UL << ETH_MTLESTSR_SWOL_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTSR_SWOL                           ETH_MTLESTSR_SWOL_Msk /* S/W owned list */
+#define ETH_MTLESTSR_CGCE_Pos                       (4U)
+#define ETH_MTLESTSR_CGCE_Msk                       (0x1UL << ETH_MTLESTSR_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTSR_CGCE                           ETH_MTLESTSR_CGCE_Msk /* Constant Gate Control Error */
+#define ETH_MTLESTSR_HLBS_Pos                       (3U)
+#define ETH_MTLESTSR_HLBS_Msk                       (0x1UL << ETH_MTLESTSR_HLBS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTSR_HLBS                           ETH_MTLESTSR_HLBS_Msk /* Head-Of-Line Blocking due to Scheduling */
+#define ETH_MTLESTSR_HLBF_Pos                       (2U)
+#define ETH_MTLESTSR_HLBF_Msk                       (0x1UL << ETH_MTLESTSR_HLBF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTSR_HLBF                           ETH_MTLESTSR_HLBF_Msk /* Head-Of-Line Blocking due to Frame Size */
+#define ETH_MTLESTSR_BTRE_Pos                       (1U)
+#define ETH_MTLESTSR_BTRE_Msk                       (0x1UL << ETH_MTLESTSR_BTRE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTSR_BTRE                           ETH_MTLESTSR_BTRE_Msk /* BTR Error */
+#define ETH_MTLESTSR_SWLC_Pos                       (0U)
+#define ETH_MTLESTSR_SWLC_Msk                       (0x1UL << ETH_MTLESTSR_SWLC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTSR_SWLC                           ETH_MTLESTSR_SWLC_Msk /* Switch to S/W owned list Complete */
+
+/************ Bit definition for Ethernet MTL EST Schedule Error Register   ***************/
+/* Bit definition for Ethernet MTL EST Schedule Error Register */
+#define ETH_MTLESTSCHER_SEQN_Pos                       (0U)
+#define ETH_MTLESTSCHER_SEQN_Msk                       (0x3UL << ETH_MTLESTSCHER_SEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTSCHER_SEQN                           ETH_MTLESTSCHER_SEQN_Msk /* Schedule Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Error Register   ***************/
+#define ETH_MTLESTFSER_FEQN_Pos                       (0U)
+#define ETH_MTLESTFSER_FEQN_Msk                       (0x3UL << ETH_MTLESTFSER_FEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTFSER_FEQN                           ETH_MTLESTFSER_FEQN_Msk /* Frame Size Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Capture Register   ***************/
+#define ETH_MTLESTFSCR_HBFQ_Pos                       (16U)
+#define ETH_MTLESTFSCR_HBFQ_Msk                       (0x1UL << ETH_MTLESTFSCR_HBFQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLESTFSCR_HBFQ                           ETH_MTLESTFSCR_HBFQ_Msk /* Queue Number of HLBF */
+#define ETH_MTLESTFSCR_HBFS_Pos                       (0U)
+#define ETH_MTLESTFSCR_HBFS_Msk                       (0x7FFFUL << ETH_MTLESTFSCR_HBFS_Pos) /*!< 0x00007FFF */
+#define ETH_MTLESTFSCR_HBFS                           ETH_MTLESTFSCR_HBFS_Msk /* Frame Size of HLBF */
+
+/************ Bit definition for Ethernet MTL EST Interrupt Enable Register   ***************/
+/* Bit definition for Ethernet MTL EST Interrupt Enable Register */
+#define ETH_MTLESTIER_CGCE_Pos                       (4U)
+#define ETH_MTLESTIER_CGCE_Msk                       (0x1UL << ETH_MTLESTIER_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTIER_CGCE                           ETH_MTLESTIER_CGCE_Msk /* Interrupt Enable for CGCE */
+#define ETH_MTLESTIER_IEHS_Pos                       (3U)
+#define ETH_MTLESTIER_IEHS_Msk                       (0x1UL << ETH_MTLESTIER_IEHS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTIER_IEHS                           ETH_MTLESTIER_IEHS_Msk /* Interrupt Enable for HLBS */
+#define ETH_MTLESTIER_IEHF_Pos                       (2U)
+#define ETH_MTLESTIER_IEHF_Msk                       (0x1UL << ETH_MTLESTIER_IEHF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTIER_IEHF                           ETH_MTLESTIER_IEHF_Msk /* Interrupt Enable for HLBF */
+#define ETH_MTLESTIER_IEBE_Pos                       (1U)
+#define ETH_MTLESTIER_IEBE_Msk                       (0x1UL << ETH_MTLESTIER_IEBE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTIER_IEBE                           ETH_MTLESTIER_IEBE_Msk /* Interrupt Enable for BTR Error */
+#define ETH_MTLESTIER_IECC_Pos                       (0U)
+#define ETH_MTLESTIER_IECC_Msk                       (0x1UL << ETH_MTLESTIER_IECC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTIER_IECC                           ETH_MTLESTIER_IECC_Msk /* Interrupt Enable for Switch List */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Register   ***************/
+#define ETH_MTLESTGCLCR_ADDR_Pos                       (8U)
+#define ETH_MTLESTGCLCR_ADDR_Msk                       (0x3FUL << ETH_MTLESTGCLCR_ADDR_Pos) /*!< 0x00003F00 */
+#define ETH_MTLESTGCLCR_ADDR                           ETH_MTLESTGCLCR_ADDR_Msk /* Gate Control List Address */
+#define ETH_MTLESTGCLCR_ADDR_BTRLOW                    ((uint32_t)0x00000000)   /* BTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk               (0x1UL << ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos) /*!< 0x00000100 */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH                   ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk /* BTR High (63:31) */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos                (9U)
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk                (0x1UL << ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos) /*!< 0x00000200 */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW                    ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk /* CTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk               (0x3UL << ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos) /*!< 0x00000300 */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH                   ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk /* CTR High (39:32) */
+#define ETH_MTLESTGCLCR_ADDR_TER_Pos                   (10U)
+#define ETH_MTLESTGCLCR_ADDR_TER_Msk                   (0x1UL << ETH_MTLESTGCLCR_ADDR_TER_Pos) /*!< 0x00000400 */
+#define ETH_MTLESTGCLCR_ADDR_TER                       ETH_MTLESTGCLCR_ADDR_TER_Msk /* TER (30:0) */
+#define ETH_MTLESTGCLCR_ADDR_LLR_Pos                   (8U)
+#define ETH_MTLESTGCLCR_ADDR_LLR_Msk                   (0x5UL << ETH_MTLESTGCLCR_ADDR_LLR_Pos) /*!< 0x00000500 */
+#define ETH_MTLESTGCLCR_ADDR_LLR                       ETH_MTLESTGCLCR_ADDR_LLR_Msk /* LLR (6:0) */
+#define ETH_MTLESTGCLCR_DBGB_Pos                       (5U)
+#define ETH_MTLESTGCLCR_DBGB_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGB_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTGCLCR_DBGB                           ETH_MTLESTGCLCR_DBGB_Msk /* Debug Mode Bank Select */
+#define ETH_MTLESTGCLCR_DBGM_Pos                       (4U)
+#define ETH_MTLESTGCLCR_DBGM_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGM_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTGCLCR_DBGM                           ETH_MTLESTGCLCR_DBGM_Msk /* Debug Mode */
+#define ETH_MTLESTGCLCR_GCRR_Pos                       (2U)
+#define ETH_MTLESTGCLCR_GCRR_Msk                       (0x1UL << ETH_MTLESTGCLCR_GCRR_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTGCLCR_GCRR                           ETH_MTLESTGCLCR_GCRR_Msk /* Gate Control Related Registers */
+#define ETH_MTLESTGCLCR_R1W0_Pos                       (1U)
+#define ETH_MTLESTGCLCR_R1W0_Msk                       (0x1UL << ETH_MTLESTGCLCR_R1W0_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTGCLCR_R1W0                           ETH_MTLESTGCLCR_R1W0_Msk /* Read 1, Write 0 */
+#define ETH_MTLESTGCLCR_SRWO_Pos                       (0U)
+#define ETH_MTLESTGCLCR_SRWO_Msk                       (0x1UL << ETH_MTLESTGCLCR_SRWO_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTGCLCR_SRWO                           ETH_MTLESTGCLCR_SRWO_Msk /* Start Read/Write Operation */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Data Register   ***************/
+#define ETH_MTLESTGCLDR_GCD_Pos                        (0U)
+#define ETH_MTLESTGCLDR_GCD_Msk                        (0xFFFFFFFFUL << ETH_MTLESTGCLDR_GCD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MTLESTGCLDR_GCD                            ETH_MTLESTGCLDR_GCD_Msk /* Gate Control Data */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Control Status Register   ***************/
+#define ETH_MTLFPECSR_HRS_Pos                          (28U)
+#define ETH_MTLFPECSR_HRS_Msk                          (0x1UL << ETH_MTLFPECSR_HRS_Pos) /*!< 0x10000000 */
+#define ETH_MTLFPECSR_HRS                              ETH_MTLFPECSR_HRS_Msk /* Hold/Release Status */
+#define ETH_MTLFPECSR_PEC_Pos                          (8U)
+#define ETH_MTLFPECSR_PEC_Msk                          (0x3UL << ETH_MTLFPECSR_PEC_Pos) /*!< 0x00000300 */
+#define ETH_MTLFPECSR_PEC                              ETH_MTLFPECSR_PEC_Msk /* Preemption Classification */
+#define ETH_MTLFPECSR_AFSZ_Pos                         (0U)
+#define ETH_MTLFPECSR_AFSZ_Msk                         (0x3UL << ETH_MTLFPECSR_AFSZ_Pos) /*!< 0x00000003 */
+#define ETH_MTLFPECSR_AFSZ                             ETH_MTLFPECSR_AFSZ_Msk /* Additional Fragment Size */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Advance Register   ***************/
+#define ETH_MTLFPEAR_RADV_Pos                          (16U)
+#define ETH_MTLFPEAR_RADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_RADV_Pos) /*!< 0xFFFF0000 */
+#define ETH_MTLFPEAR_RADV                              ETH_MTLFPEAR_RADV_Msk /* Release Advance */
+#define ETH_MTLFPEAR_HADV_Pos                          (0U)
+#define ETH_MTLFPEAR_HADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_HADV_Pos) /*!< 0x0000FFFF */
+#define ETH_MTLFPEAR_HADV                              ETH_MTLFPEAR_HADV_Msk /* Hold Advance */
+
+/************ Bit definition for Ethernet MTL Tx queue x operating mode Register   ***************/
+#define ETH_MTLTXQxOMR_TQS_Pos                          (16U)
+#define ETH_MTLTXQxOMR_TQS_Msk                          (0xFUL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x000F0000 */
+#define ETH_MTLTXQxOMR_TQS                              ETH_MTLTXQxOMR_TQS_Msk     /* Transmit queue size */
+#define ETH_MTLTXQxOMR_TQS_0                            (0x1UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00010000 */
+#define ETH_MTLTXQxOMR_TQS_1                            (0x2UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00020000 */
+#define ETH_MTLTXQxOMR_TQS_2                            (0x4UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00040000 */
+#define ETH_MTLTXQxOMR_TQS_3                            (0x8UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00080000 */
+#define ETH_MTLTXQxOMR_TTC_Pos                          (4U)
+#define ETH_MTLTXQxOMR_TTC_Msk                          (0x7UL << ETH_MTLTXQxOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQxOMR_TTC                              ETH_MTLTXQxOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTXQxOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTXQxOMR_TXQEN_Pos                        (2U)
+#define ETH_MTLTXQxOMR_TXQEN_Msk                        (0x3UL << ETH_MTLTXQxOMR_TXQEN_Pos) /*!< 0x0000000C */
+#define ETH_MTLTXQxOMR_TXQEN                            ETH_MTLTXQxOMR_TXQEN_Msk     /* Transmit Queue Enable */
+#define ETH_MTLTXQxOMR_TXQEN_NOT                        ((uint32_t)0x00000000)   /* Not enabled */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos                 (2U)
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk                 (0x1UL << ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE                     ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk     /* Enable in AV mode */
+#define ETH_MTLTXQxOMR_TXQEN_EN_Pos                     (3U)
+#define ETH_MTLTXQxOMR_TXQEN_EN_Msk                     (0x1UL << ETH_MTLTXQxOMR_TXQEN_EN_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxOMR_TXQEN_EN                         ETH_MTLTXQxOMR_TXQEN_EN_Msk     /* Enabled */
+#define ETH_MTLTXQxOMR_TSF_Pos                          (1U)
+#define ETH_MTLTXQxOMR_TSF_Msk                          (0x1UL << ETH_MTLTXQxOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQxOMR_TSF                              ETH_MTLTXQxOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTXQxOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTXQxOMR_FTQ_Msk                          (0x1UL << ETH_MTLTXQxOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxOMR_FTQ                              ETH_MTLTXQxOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Underflow Register   ***************/
+#define ETH_MTLTXQxUR_UFCNTOVF_Pos                     (11U)
+#define ETH_MTLTXQxUR_UFCNTOVF_Msk                     (0x1UL << ETH_MTLTXQxUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQxUR_UFCNTOVF                         ETH_MTLTXQxUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTXQxUR_UFPKTCNT_Pos                     (0U)
+#define ETH_MTLTXQxUR_UFPKTCNT_Msk                     (0x7FFUL << ETH_MTLTXQxUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTXQxUR_UFPKTCNT                         ETH_MTLTXQxUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Debug Register   ***************/
+#define ETH_MTLTXQxDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTXQxDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTXQxDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTXQxDR_STXSTSF                           ETH_MTLTXQxDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTXQxDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTXQxDR_PTXQ_Msk                          (0x7UL << ETH_MTLTXQxDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTXQxDR_PTXQ                              ETH_MTLTXQxDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTXQxDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTXQxDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTXQxDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQxDR_TXSTSFSTS                         ETH_MTLTXQxDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTXQxDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTXQxDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQxDR_TXQSTS                            ETH_MTLTXQxDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTXQxDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTXQxDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxDR_TWCSTS                            ETH_MTLTXQxDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTXQxDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTXQxDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTXQxDR_TRCSTS                            ETH_MTLTXQ0DR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTXQxDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTXQxDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTXQxDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTXQxDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTXQxDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTXQxDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxDR_TXQPAUSED                         ETH_MTLTXQxDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/************ Bit definition for Ethernet MTL Tx queue x ETS status Register   ***************/
+#define ETH_MTLTXQxESR_ABS_Pos                       (0U)
+#define ETH_MTLTXQxESR_ABS_Msk                       (0xFFFFFFUL << ETH_MTLTXQxESR_ABS_Pos) /*!< 0x00FFFFFF */
+#define ETH_MTLTXQxESR_ABS                           ETH_MTLTXQxESR_ABS_Msk  /* Average Bits per Slot */
+
+/************ Bit definition for Ethernet MTL Tx queue 0 quantum weight Register   ***************/
+#define ETH_MTLTXQ0QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ0QWR_ISCQW_Msk                       (0x7FUL << ETH_MTLTXQ0QWR_ISCQW_Pos) /*!< 0x0000007F */
+#define ETH_MTLTXQ0QWR_ISCQW                           ETH_MTLTXQ0QWR_ISCQW_Msk  /* Weights */
+
+/************ Bit definition for Ethernet MTL Queue x Interrupt Control Status Register   ***************/
+#define ETH_MTLQxICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQxICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQxICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQxICSR_RXOIE                            ETH_MTLQxICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQxICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQxICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQxICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQxICSR_RXOVFIS                          ETH_MTLQxICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQxICSR_ABPSIE_Pos                       (9U)
+#define ETH_MTLQxICSR_ABPSIE_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIE_Pos) /*!< 0x00000200 */
+#define ETH_MTLQxICSR_ABPSIE                           ETH_MTLQxICSR_ABPSIE_Msk   /* Average Bits Per Slot Interrupt Enable */
+#define ETH_MTLQxICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQxICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQxICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQxICSR_TXUIE                            ETH_MTLQxICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQxICSR_ABPSIS_Pos                       (1U)
+#define ETH_MTLQxICSR_ABPSIS_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIS_Pos) /*!< 0x00000002 */
+#define ETH_MTLQxICSR_ABPSIS                           ETH_MTLQxICSR_ABPSIS_Msk /* Average Bits Per Slot Interrupt Status */
+#define ETH_MTLQxICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQxICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQxICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQxICSR_TXUNFIS                          ETH_MTLQxICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Operation Mode Register   ***************/
+#define ETH_MTLRXQxOMR_RQS_Pos                          (20U)
+#define ETH_MTLRXQxOMR_RQS_Msk                          (0xFUL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00F00000 */
+#define ETH_MTLRXQxOMR_RQS                              ETH_MTLRXQxOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRXQxOMR_RQS_0                            (0x1UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00100000 */
+#define ETH_MTLRXQxOMR_RQS_1                            (0x2UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00200000 */
+#define ETH_MTLRXQxOMR_RQS_2                            (0x4UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00400000 */
+#define ETH_MTLRXQxOMR_RQS_3                            (0x8UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00800000 */
+#define ETH_MTLRXQxOMR_RFD_Pos                          (14U)
+#define ETH_MTLRXQxOMR_RFD_Msk                          (0x7UL << ETH_MTLRXQxOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRXQxOMR_RFD                              ETH_MTLRXQxOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRXQxOMR_RFA_Pos                          (8U)
+#define ETH_MTLRXQxOMR_RFA_Msk                          (0x7UL << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRXQxOMR_RFA                              ETH_MTLRXQxOMR_RFA_Pos /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRXQxOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRXQxOMR_EHFC_Msk                         (0x1UL << ETH_MTLRXQxOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQxOMR_EHFC                             ETH_MTLRXQxOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRXQxOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRXQxOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRXQxOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQxOMR_DISTCPEF                         ETH_MTLRXQxOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRXQxOMR_RSF_Pos                          (5U)
+#define ETH_MTLRXQxOMR_RSF_Msk                          (0x1UL << ETH_MTLRXQxOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxOMR_RSF                              ETH_MTLRXQxOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRXQxOMR_FEP_Pos                          (4U)
+#define ETH_MTLRXQxOMR_FEP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxOMR_FEP                              ETH_MTLRXQxOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRXQxOMR_FUP_Pos                          (3U)
+#define ETH_MTLRXQxOMR_FUP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxOMR_FUP                              ETH_MTLRXQxOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRXQxOMR_RTC_Pos                          (0U)
+#define ETH_MTLRXQxOMR_RTC_Msk                          (0x3UL << ETH_MTLRXQxOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRXQxOMR_RTC                              ETH_MTLRXQxOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRXQxOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Missed Packet Overflow Cnt Register   ***************/
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQxMPOCR_MISCNTOVF                      ETH_MTLRXQxMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT                      ETH_MTLRXQxMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF                      ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT                      ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Debug Register   ***************/
+#define ETH_MTLRXQxDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRXQxDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRXQxDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRXQxDR_PRXQ                              ETH_MTLRXQxDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRXQxDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRXQxDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS                            ETH_MTLRXQxDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRXQxDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRXQxDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS_FULL                       ETH_MTLRXQxDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRXQxDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRXQxDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS                            ETH_MTLRXQxDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRXQxDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS              ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING                   ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRXQxDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRXQxDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRXQxDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQxDR_RWCSTS                            ETH_MTLRXQxDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Control Register   ***************/
+#define ETH_MTLRXQxCR_RQPA_Pos                          (3U)
+#define ETH_MTLRXQxCR_RQPA_Msk                          (0x1UL << ETH_MTLRXQxCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxCR_RQPA                              ETH_MTLRXQxCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRXQxCR_RQW_Pos                           (0U)
+#define ETH_MTLRXQxCR_RQW_Msk                           (0x7UL << ETH_MTLRXQxCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRXQxCR_RQW                               ETH_MTLRXQxCR_RQW_Msk      /* Receive Queue Weight */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 ETS control Register   ***************/
+#define ETH_MTLTXQ1ECR_SLC_Pos                         (4U)
+#define ETH_MTLTXQ1ECR_SLC_Msk                         (0x7UL << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQ1ECR_SLC                             ETH_MTLTXQ1ECR_SLC_Msk     /* Slot Count */
+#define ETH_MTLTXQ1ECR_SLC_1SLOT                       ((uint32_t)0x00000000)   /* 1 Slot */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_2SLOT_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT                       ETH_MTLTXQ1ECR_SLC_2SLOT_Msk     /* 2 Slots */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Pos                   (5U)
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_4SLOT_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT                       ETH_MTLTXQ1ECR_SLC_4SLOT_Msk     /* 4 Slots */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Msk                   (0x3UL << ETH_MTLTXQ1ECR_SLC_8SLOT_Pos) /*!< 0x00000030 */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT                       ETH_MTLTXQ1ECR_SLC_8SLOT_Msk     /* 8 Slots */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Pos                  (6U)
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Msk                  (0x1UL << ETH_MTLTXQ1ECR_SLC_16SLOT_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT                      ETH_MTLTXQ1ECR_SLC_16SLOT_Msk     /* 16 Slots */
+#define ETH_MTLTXQ1ECR_CC_Pos                          (3U)
+#define ETH_MTLTXQ1ECR_CC_Msk                          (0x1UL << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1ECR_CC                              ETH_MTLTXQ1ECR_CC_Msk     /* Credit Control */
+#define ETH_MTLTXQ1ECR_AVALG_Pos                       (2U)
+#define ETH_MTLTXQ1ECR_AVALG_Msk                       (0x1UL << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1ECR_AVALG                           ETH_MTLTXQ1ECR_AVALG_Msk     /* Credit Control */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 quantum weight Register   ***************/
+#define ETH_MTLTXQ1QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ1QWR_ISCQW_Msk                       (0x3FFFUL << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1QWR_ISCQW                           ETH_MTLTXQ1QWR_ISCQW_Msk     /* IdleSlopeCredit or Weights */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 send slope credit Register   ***************/
+#define ETH_MTLTXQ1SSCR_SSC_Pos                        (0U)
+#define ETH_MTLTXQ1SSCR_SSC_Msk                        (0x3FFFUL << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1SSCR_SSC                            ETH_MTLTXQ1SSCR_SSC_Msk     /* sendSlopeCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx Queue 1 hiCredit Register   ***************/
+#define ETH_MTLTXQ1HCR_HC_Pos                          (0U)
+#define ETH_MTLTXQ1HCR_HC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1HCR_HC                              ETH_MTLTXQ1HCR_HC_Msk     /* hiCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 loCredit Register   ***************/
+#define ETH_MTLTXQ1LCR_LC_Pos                          (0U)
+#define ETH_MTLTXQ1LCR_LC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1LCR_LC                              ETH_MTLTXQ1LCR_LC_Msk     /* loCredit Value */
+
+/************ Bit definition for Ethernet DMA Mode Register   ***************/
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk         /* Transmit priority */
+#define ETH_DMAMR_DSPW_Pos                            (8U)
+#define ETH_DMAMR_DSPW_Msk                            (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */
+#define ETH_DMAMR_DSPW                                ETH_DMAMR_DSPW_Msk         /* Descriptor Posted Write */
+#define ETH_DMAMR_TAA_Pos                             (2U)
+#define ETH_DMAMR_TAA_Msk                             (0x7UL << ETH_DMAMR_TAA_Pos) /*!< 0x000001C0 */
+#define ETH_DMAMR_TAA                                 ETH_DMAMR_TAA_Msk         /* Transmit Arbitration Algorithm */
+#define ETH_DMAMR_TAA_FP                              ((uint32_t)0x00000000)    /* Fixed priority */
+#define ETH_DMAMR_TAA_WSP_Pos                         (2U)
+#define ETH_DMAMR_TAA_WSP_Msk                         (0x1UL << ETH_DMAMR_TAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_DMAMR_TAA_WSP                             ETH_DMAMR_TAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_DMAMR_TAA_WRR_Pos                         (3U)
+#define ETH_DMAMR_TAA_WRR_Msk                         (0x1UL << ETH_DMAMR_TAA_WRR_Pos) /*!< 0x00000008 */
+#define ETH_DMAMR_TAA_WRR                             ETH_DMAMR_TAA_WRR_Msk  /* Weighted Round-Robin (WRR) */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk  /* Software Reset */
+
+/************ Bit definition for Ethernet DMA System bus mode Register   ***************/
+#define ETH_DMASBMR_ENLPI_Pos                         (31U)
+#define ETH_DMASBMR_ENLPI_Msk                         (0x1UL << ETH_DMASBMR_ENLPI_Pos) /*!< 0x80000000 */
+#define ETH_DMASBMR_ENLPI                             ETH_DMASBMR_ENLPI_Msk       /* Enable Low Power Interface (LPI) */
+#define ETH_DMASBMR_LPIXPKT_Pos                       (30U)
+#define ETH_DMASBMR_LPIXPKT_Msk                       (0x1UL << ETH_DMASBMR_LPIXPKT_Pos) /*!< 0x40000000 */
+#define ETH_DMASBMR_LPIXPKT                           ETH_DMASBMR_LPIXPKT_Msk       /* Unlock on Magic Packet or Remote wakeup Packet */
+#define ETH_DMASBMR_WR_OSR_LMT_Pos                    (24U)
+#define ETH_DMASBMR_WR_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
+#define ETH_DMASBMR_WR_OSR_LMT                        ETH_DMASBMR_WR_OSR_LMT_Msk            /*!< AXI Maximum Write Outstanding Request Limit */
+#define ETH_DMASBMR_WR_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
+#define ETH_DMASBMR_WR_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
+#define ETH_DMASBMR_RD_OSR_LMT_Pos                    (16U)
+#define ETH_DMASBMR_RD_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
+#define ETH_DMASBMR_RD_OSR_LMT                        ETH_DMASBMR_RD_OSR_LMT_Msk            /*!< AXI Maximum Read Outstanding Request Limit */
+#define ETH_DMASBMR_RD_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
+#define ETH_DMASBMR_RD_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
+#define ETH_DMASBMR_ONEKBBE_Pos                       (13U)
+#define ETH_DMASBMR_ONEKBBE_Msk                       (0x1UL << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
+#define ETH_DMASBMR_ONEKBBE                           ETH_DMASBMR_ONEKBBE_Msk       /* 1 Kbyte Boundary Crossing Enable for the AXI Master */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_AALE_Pos                          (10U)
+#define ETH_DMASBMR_AALE_Msk                          (0x1UL << ETH_DMASBMR_AALE_Pos) /*!< 0x00000400 */
+#define ETH_DMASBMR_AALE                              ETH_DMASBMR_AALE_Msk       /* Automatic AXI LPI enable */
+#define ETH_DMASBMR_BLEN256_Pos                       (7U)
+#define ETH_DMASBMR_BLEN256_Msk                       (0x1UL << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
+#define ETH_DMASBMR_BLEN256                           ETH_DMASBMR_BLEN256_Msk       /* AXI Burst Length 256 */
+#define ETH_DMASBMR_BLEN128_Pos                       (6U)
+#define ETH_DMASBMR_BLEN128_Msk                       (0x1UL << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
+#define ETH_DMASBMR_BLEN128                           ETH_DMASBMR_BLEN128_Msk       /* AXI Burst Length 128 */
+#define ETH_DMASBMR_BLEN64_Pos                        (5U)
+#define ETH_DMASBMR_BLEN64_Msk                        (0x1UL << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
+#define ETH_DMASBMR_BLEN64                            ETH_DMASBMR_BLEN64_Msk       /* AXI Burst Length 64 */
+#define ETH_DMASBMR_BLEN32_Pos                        (4U)
+#define ETH_DMASBMR_BLEN32_Msk                        (0x1UL << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
+#define ETH_DMASBMR_BLEN32                            ETH_DMASBMR_BLEN32_Msk       /* AXI Burst Length 32 */
+#define ETH_DMASBMR_BLEN16_Pos                        (3U)
+#define ETH_DMASBMR_BLEN16_Msk                        (0x1UL << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
+#define ETH_DMASBMR_BLEN16                            ETH_DMASBMR_BLEN16_Msk       /* AXI Burst Length 16 */
+#define ETH_DMASBMR_BLEN8_Pos                         (2U)
+#define ETH_DMASBMR_BLEN8_Msk                         (0x1UL << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
+#define ETH_DMASBMR_BLEN8                             ETH_DMASBMR_BLEN8_Msk       /* AXI Burst Length 8 */
+#define ETH_DMASBMR_BLEN4_Pos                         (1U)
+#define ETH_DMASBMR_BLEN4_Msk                         (0x1UL << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
+#define ETH_DMASBMR_BLEN4                             ETH_DMASBMR_BLEN4_Msk       /* AXI Burst Length 4 */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/************ Bit definition for Ethernet DMA Interrupt Status Register   ***************/
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMAC1IS_Pos                        (1U)
+#define ETH_DMAISR_DMAC1IS_Msk                        (0x1UL << ETH_DMAISR_DMAC1IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC1IS                            ETH_DMAISR_DMAC1IS_Msk    /* DMA Channel 1 Interrupt Status */
+#define ETH_DMAISR_DMAC0IS_Pos                        (0U)
+#define ETH_DMAISR_DMAC0IS_Msk                        (0x1UL << ETH_DMAISR_DMAC0IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC0IS                            ETH_DMAISR_DMAC0IS_Msk    /* DMA Channel 0 Interrupt Status */
+
+/************ Bit definition for Ethernet DMA Debug Status Register   ***************/
+#define ETH_DMADSR_TPS1_Pos                            (20U)
+#define ETH_DMADSR_TPS1_Msk                            (0xFUL << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
+#define ETH_DMADSR_TPS1                                ETH_DMADSR_TPS1_Msk       /* DMA Channel 1 Transmit Process State */
+#define ETH_DMADSR_TPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS1_FETCHING_Pos                   (20U)
+#define ETH_DMADSR_TPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS1_FETCHING_Pos) /*!< 0x00100000 */
+#define ETH_DMADSR_TPS1_FETCHING                       ETH_DMADSR_TPS1_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS1_WAITING_Pos                    (21U)
+#define ETH_DMADSR_TPS1_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS1_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_DMADSR_TPS1_WAITING                        ETH_DMADSR_TPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS1_READING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_READING_Msk                    (0x3UL << ETH_DMADSR_TPS1_READING_Pos) /*!< 0x00300000 */
+#define ETH_DMADSR_TPS1_READING                        ETH_DMADSR_TPS1_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos               (22U)
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos) /*!< 0x00400000 */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR                   ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS1_SUSPENDED_Pos                  (21U)
+#define ETH_DMADSR_TPS1_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS1_SUSPENDED_Pos) /*!< 0x00600000 */
+#define ETH_DMADSR_TPS1_SUSPENDED                      ETH_DMADSR_TPS1_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS1_CLOSING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS1_CLOSING_Pos) /*!< 0x00700000 */
+#define ETH_DMADSR_TPS1_CLOSING                        ETH_DMADSR_TPS1_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS1_Pos                            (16U)
+#define ETH_DMADSR_RPS1_Msk                            (0xFUL << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
+#define ETH_DMADSR_RPS1                                ETH_DMADSR_RPS1_Msk       /* DMA Channel 1 Receive Process State */
+#define ETH_DMADSR_RPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS1_FETCHING_Pos                   (16U)
+#define ETH_DMADSR_RPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS1_FETCHING_Pos) /*!< 0x00010000 */
+#define ETH_DMADSR_RPS1_FETCHING                       ETH_DMADSR_RPS1_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS1_WAITING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS1_WAITING_Pos) /*!< 0x00030000 */
+#define ETH_DMADSR_RPS1_WAITING                        ETH_DMADSR_RPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS1_SUSPENDED_Pos                  (18U)
+#define ETH_DMADSR_RPS1_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS1_SUSPENDED_Pos) /*!< 0x00040000 */
+#define ETH_DMADSR_RPS1_SUSPENDED                      ETH_DMADSR_RPS1_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS1_CLOSING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS1_CLOSING_Pos) /*!< 0x00050000 */
+#define ETH_DMADSR_RPS1_CLOSING                        ETH_DMADSR_RPS1_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos               (17U)
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos) /*!< 0x00060000 */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR                   ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS1_TRANSFERRING_Pos               (16U)
+#define ETH_DMADSR_RPS1_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS1_TRANSFERRING_Pos) /*!< 0x00070000 */
+#define ETH_DMADSR_RPS1_TRANSFERRING                   ETH_DMADSR_RPS1_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_TPS0_Pos                            (12U)
+#define ETH_DMADSR_TPS0_Msk                            (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS0                                ETH_DMADSR_TPS0_Msk       /* DMA Channel 0 Transmit Process State */
+#define ETH_DMADSR_TPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS0_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS0_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS0_FETCHING                       ETH_DMADSR_TPS0_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS0_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS0_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS0_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS0_WAITING                        ETH_DMADSR_TPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS0_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_READING_Msk                    (0x3UL << ETH_DMADSR_TPS0_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS0_READING                        ETH_DMADSR_TPS0_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR                   ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS0_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS0_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS0_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS0_SUSPENDED                      ETH_DMADSR_TPS0_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS0_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS0_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS0_CLOSING                        ETH_DMADSR_TPS0_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS0_Pos                            (8U)
+#define ETH_DMADSR_RPS0_Msk                            (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS0                                ETH_DMADSR_RPS0_Msk       /* DMA Channel 0 Receive Process State */
+#define ETH_DMADSR_RPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS0_FETCHING_Pos                   (8U)
+#define ETH_DMADSR_RPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS0_FETCHING_Pos) /*!< 0x00000100 */
+#define ETH_DMADSR_RPS0_FETCHING                       ETH_DMADSR_RPS0_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS0_WAITING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS0_WAITING_Pos) /*!< 0x00000300 */
+#define ETH_DMADSR_RPS0_WAITING                        ETH_DMADSR_RPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS0_SUSPENDED_Pos                  (10U)
+#define ETH_DMADSR_RPS0_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS0_SUSPENDED_Pos) /*!< 0x00000400 */
+#define ETH_DMADSR_RPS0_SUSPENDED                      ETH_DMADSR_RPS0_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS0_CLOSING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS0_CLOSING_Pos) /*!< 0x00000500 */
+#define ETH_DMADSR_RPS0_CLOSING                        ETH_DMADSR_RPS0_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos               (9U)
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos) /*!< 0x00000600 */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR                   ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS0_TRANSFERRING_Pos               (8U)
+#define ETH_DMADSR_RPS0_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS0_TRANSFERRING_Pos) /*!< 0x00000700 */
+#define ETH_DMADSR_RPS0_TRANSFERRING                   ETH_DMADSR_RPS0_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_AXRHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXRHSTS_Msk                         (0x1UL << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
+#define ETH_DMADSR_AXRHSTS                             ETH_DMADSR_AXRHSTS_Msk /* AXI Master Read Channel Status */
+#define ETH_DMADSR_AXWHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXWHSTS_Msk                         (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
+#define ETH_DMADSR_AXWHSTS                             ETH_DMADSR_AXWHSTS_Msk /* AXI Master Write Channel */
+
+/************ Bit definition for Ethernet DMA AXI4 transmit channel ACE control Register   ***************/
+#define ETH_DMAA4TXACR_THC_Pos                         (16U)
+#define ETH_DMAA4TXACR_THC_Msk                         (0xFUL << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4TXACR_THC                             ETH_DMAA4TXACR_THC_Msk       /* Transmit DMA First Packet Buffer or TSO Header Cache Control */
+#define ETH_DMAA4TXACR_TEC_Pos                         (8U)
+#define ETH_DMAA4TXACR_TEC_Msk                         (0xFUL << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4TXACR_TEC                             ETH_DMAA4TXACR_TEC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+#define ETH_DMAA4TXACR_TDRC_Pos                        (0U)
+#define ETH_DMAA4TXACR_TDRC_Msk                        (0xFUL << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4TXACR_TDRC                            ETH_DMAA4TXACR_TDRC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 receive channel ACE control Register   ***************/
+#define ETH_DMAA4RXACR_RDC_Pos                         (24U)
+#define ETH_DMAA4RXACR_RDC_Msk                         (0xFUL << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
+#define ETH_DMAA4RXACR_RDC                             ETH_DMAA4RXACR_RDC_Msk       /* Receive DMA Buffer Cache Control */
+#define ETH_DMAA4RXACR_RHC_Pos                         (16U)
+#define ETH_DMAA4RXACR_RHC_Msk                         (0xFUL << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4RXACR_RHC                             ETH_DMAA4RXACR_RHC_Msk       /* Receive DMA Header Cache Control */
+#define ETH_DMAA4RXACR_RPC_Pos                         (8U)
+#define ETH_DMAA4RXACR_RPC_Msk                         (0xFUL << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4RXACR_RPC                             ETH_DMAA4RXACR_RPC_Msk       /* Receive DMA Payload Cache Control */
+#define ETH_DMAA4RXACR_RDWC_Pos                        (0U)
+#define ETH_DMAA4RXACR_RDWC_Msk                        (0xFUL << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4RXACR_RDWC                            ETH_DMAA4RXACR_RDWC_Msk   /* Receive DMA Write Descriptor Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 descriptor ACE control Register   ***************/
+#define ETH_DMAA4DACR_RDRC_Pos                         (8U)
+#define ETH_DMAA4DACR_RDRC_Msk                         (0xFUL << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4DACR_RDRC                             ETH_DMAA4DACR_RDRC_Msk       /* Receive DMA Read Descriptor Cache control */
+#define ETH_DMAA4DACR_TDWD_Pos                         (4U)
+#define ETH_DMAA4DACR_TDWD_Msk                         (0xFUL << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
+#define ETH_DMAA4DACR_TDWD                             ETH_DMAA4DACR_TDWD_Msk       /* Transmit DMA Write Descriptor Domain control */
+#define ETH_DMAA4DACR_TDWC_Pos                         (0U)
+#define ETH_DMAA4DACR_TDWC_Msk                         (0xFUL << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4DACR_TDWC                             ETH_DMAA4DACR_TDWC_Msk       /* Transmit DMA Write Descriptor Cache control */
+
+/************ Bit definition for Ethernet DMA AXI4 LPI Entry Interval Register   ***************/
+/* Bit definition for Ethernet DMA AXI4 LPI Entry Interval register */
+#define ETH_DMALPIEI_LPIEI_Pos                         (0U)
+#define ETH_DMALPIEI_LPIEI_Msk                         (0xFUL << ETH_DMALPIEI_LPIEI_Pos) /*!< 0x0000000F */
+#define ETH_DMALPIEI_LPIEI                             ETH_DMALPIEI_LPIEI_Msk   /* LPI Entry Interval */
+
+/************ Bit definition for Ethernet DMA TBS control Register   ***************/
+#define ETH_DMATBSCTRL0R_FTOS_Pos                      (8U)
+#define ETH_DMATBSCTRL0R_FTOS_Msk                      (0xFFFFFFUL << ETH_DMATBSCTRL0R_FTOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_DMATBSCTRL0R_FTOS                          ETH_DMATBSCTRL0R_FTOS_Msk   /* Fetch time offset */
+#define ETH_DMATBSCTRL0R_FGOS_Pos                      (4U)
+#define ETH_DMATBSCTRL0R_FGOS_Msk                      (0x7UL << ETH_DMATBSCTRL0R_FGOS_Pos) /*!< 0x00000070 */
+#define ETH_DMATBSCTRL0R_FGOS                          ETH_DMATBSCTRL0R_FGOS_Msk   /* Fetch GSN offset */
+#define ETH_DMATBSCTRL0R_FTOV_Pos                      (0U)
+#define ETH_DMATBSCTRL0R_FTOV_Msk                      (0x1UL << ETH_DMATBSCTRL0R_FTOV_Pos) /*!< 0x00000001 */
+#define ETH_DMATBSCTRL0R_FTOV                          ETH_DMATBSCTRL0R_FTOV_Msk   /* Fetch time offset valid */
+
+/************ Bit definition for Ethernet DMA Channel x Control Register   ***************/
+#define ETH_DMACxCR_DSL_Pos                            (18U)
+#define ETH_DMACxCR_DSL_Msk                            (0x7UL << ETH_DMACxCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACxCR_DSL                                ETH_DMACxCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACxCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACxCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACxCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACxCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACxCR_PBLX8_Pos                          (16U)
+#define ETH_DMACxCR_PBLX8_Msk                          (0x1UL << ETH_DMACxCR_PBLX8_Pos) /*!< 0x00010000 */
+#define ETH_DMACxCR_PBLX8                              ETH_DMACxCR_PBLX8_Msk  /* 8xPBL mode */
+#define ETH_DMACxCR_MSS_Pos                            (0U)
+#define ETH_DMACxCR_MSS_Msk                            (0x3FFFUL << ETH_DMACxCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACxCR_MSS                                ETH_DMACxCR_MSS_Msk       /* Maximum Segment Size */
+
+/************ Bit definition for Ethernet DMA Channel x transmit control Register   ***************/
+#define ETH_DMACxTXCR_EDSE_Pos                         (28U)
+#define ETH_DMACxTXCR_EDSE_Msk                         (0x1UL << ETH_DMACxTXCR_EDSE_Pos) /*!< 0x10000000 */
+#define ETH_DMACxTXCR_EDSE                             ETH_DMACxTXCR_EDSE_Msk       /* Enhanced Descriptor Enable */
+#define ETH_DMACxTXCR_TQOS_Pos                         (24U)
+#define ETH_DMACxTXCR_TQOS_Msk                         (0xFUL << ETH_DMACxTXCR_TQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxTXCR_TQOS                             ETH_DMACxTXCR_TQOS_Msk       /* Transmit QOS */
+#define ETH_DMACxTXCR_TXPBL_Pos                        (16U)
+#define ETH_DMACxTXCR_TXPBL_Msk                        (0x3FUL << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxTXCR_TXPBL                            ETH_DMACxTXCR_TXPBL_Msk       /* Transmit Programmable Burst Length */
+#define ETH_DMACxTXCR_TXPBL_1PBL                       (0x1U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00010000 */
+#define ETH_DMACxTXCR_TXPBL_2PBL                       (0x2U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00020000 */
+#define ETH_DMACxTXCR_TXPBL_4PBL                       (0x4U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00040000 */
+#define ETH_DMACxTXCR_TXPBL_8PBL                       (0x8U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00080000 */
+#define ETH_DMACxTXCR_TXPBL_16PBL                      (0x10U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00100000 */
+#define ETH_DMACxTXCR_TXPBL_32PBL                      (0x20U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00200000 */
+#define ETH_DMACxTXCR_IPBL_Pos                         (15U)
+#define ETH_DMACxTXCR_IPBL_Msk                         (0x1UL << ETH_DMACxTXCR_IPBL_Pos) /*!< 0x00008000 */
+#define ETH_DMACxTXCR_IPBL                             ETH_DMACxTXCR_IPBL_Msk       /* Ignore PBL Requirement */
+#define ETH_DMACxTXCR_TSE_Pos                          (12U)
+#define ETH_DMACxTXCR_TSE_Msk                          (0x1UL << ETH_DMACxTXCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxTXCR_TSE                              ETH_DMACxTXCR_TSE_Msk       /* TCP Segmentation Enabled */
+#define ETH_DMACxTXCR_OSF_Pos                          (4U)
+#define ETH_DMACxTXCR_OSF_Msk                          (0x1UL << ETH_DMACxTXCR_OSF_Pos) /*!< 0x00000010 */
+#define ETH_DMACxTXCR_OSF                              ETH_DMACxTXCR_OSF_Msk       /* Operate on Second Packet */
+#define ETH_DMACxTXCR_TCW_Pos                          (1U)
+#define ETH_DMACxTXCR_TCW_Msk                          (0x7UL << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000E */
+#define ETH_DMACxTXCR_TCW                              ETH_DMACxTXCR_TCW_Msk       /* Transmit Channel Weight */
+#define ETH_DMACxTXCR_TCW_1                            (0x1U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000002 */
+#define ETH_DMACxTXCR_TCW_2                            (0x2U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000004 */
+#define ETH_DMACxTXCR_TCW_3                            (0x3U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000006 */
+#define ETH_DMACxTXCR_TCW_4                            (0x4U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000008 */
+#define ETH_DMACxTXCR_TCW_5                            (0x5U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000A */
+#define ETH_DMACxTXCR_TCW_6                            (0x6U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000C */
+#define ETH_DMACxTXCR_TCW_7                            (0x7U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000E */
+#define ETH_DMACxTXCR_ST_Pos                           (0U)
+#define ETH_DMACxTXCR_ST_Msk                           (0x1UL << ETH_DMACxTXCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACxTXCR_ST                               ETH_DMACxTXCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/************ Bit definition for Ethernet DMA Channel x receive control Register   ***************/
+#define ETH_DMACxRXCR_RPF_Pos                         (31U)
+#define ETH_DMACxRXCR_RPF_Msk                         (0x1UL << ETH_DMACxRXCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACxRXCR_RPF                             ETH_DMACxRXCR_RPF_Msk       /* DMA Rx Channel Packet Flush */
+#define ETH_DMACxRXCR_RQOS_Pos                        (24U)
+#define ETH_DMACxRXCR_RQOS_Msk                        (0xFUL << ETH_DMACxRXCR_RQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxRXCR_RQOS                            ETH_DMACxRXCR_RQOS_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_Pos                       (16U)
+#define ETH_DMACxRXCR_RXPBL_Msk                       (0x3FUL << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxRXCR_RXPBL                           ETH_DMACxRXCR_RXPBL_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_1PBL                      (0x1U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00010000 */
+#define ETH_DMACxRXCR_RXPBL_2PBL                      (0x2U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00020000 */
+#define ETH_DMACxRXCR_RXPBL_4PBL                      (0x4U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00040000 */
+#define ETH_DMACxRXCR_RXPBL_8PBL                      (0x8U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00080000 */
+#define ETH_DMACxRXCR_RXPBL_16PBL                     (0x10U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00100000 */
+#define ETH_DMACxRXCR_RXPBL_32PBL                     (0x20U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00200000 */
+#define ETH_DMACxRXCR_RBSZ_Pos                        (1U)
+#define ETH_DMACxRXCR_RBSZ_Msk                        (0x1FFFUL << ETH_DMACxRXCR_RBSZ_Pos) /*!< 0x00003FFE */
+#define ETH_DMACxRXCR_RBSZ                            ETH_DMACxRXCR_RBSZ_Msk       /* Receive Buffer size */
+#define ETH_DMACxRXCR_SR_Pos                          (0U)
+#define ETH_DMACxRXCR_SR_Msk                          (0x1UL << ETH_DMACxRXCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACxRXCR_SR                              ETH_DMACxRXCR_SR_Msk       /* Start or Stop Receive */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor list address Register   ***************/
+#define ETH_DMACxTXDLAR_TDESLA_Pos                    (0U)
+#define ETH_DMACxTXDLAR_TDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDLAR_TDESLA                        ETH_DMACxTXDLAR_TDESLA_Msk   /* Start of Transmit List */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor list address Register   ***************/
+#define ETH_DMACxRXDLAR_RDESLA_Pos                    (0U)
+#define ETH_DMACxRXDLAR_RDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDLAR_RDESLA                        ETH_DMACxRXDLAR_RDESLA_Msk   /* Start of Receive List */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor tail pointer Register   ***************/
+#define ETH_DMACxTXDTPR_TDT_Pos                       (0U)
+#define ETH_DMACxTXDTPR_TDT_Msk                       (0xFFFFFFFFUL << ETH_DMACxTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDTPR_TDT                           ETH_DMACxTXDTPR_TDT_Msk   /* Transmit Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor tail pointer Register   ***************/
+#define ETH_DMACxRXDTPR_TDT_Pos                      (0U)
+#define ETH_DMACxRXDTPR_TDT_Msk                      (0xFFFFFFFFUL << ETH_DMACxRXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDTPR_TDT                          ETH_DMACxRXDTPR_TDT_Msk   /* Receive Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor ring length Register   ***************/
+#define ETH_DMACxTXRLR_TDRL_Pos                       (0U)
+#define ETH_DMACxTXRLR_TDRL_Msk                       (0x3FFUL << ETH_DMACxTXRLR_TDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxTXRLR_TDRL                           ETH_DMACxTXRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor ring length Register   ***************/
+#define ETH_DMACxRXRLR_ARBS_Pos                       (17U)
+#define ETH_DMACxRXRLR_ARBS_Msk                       (0x7FUL << ETH_DMACxRXRLR_ARBS_Pos) /*!< 0x000FE0000 */
+#define ETH_DMACxRXRLR_ARBS                           ETH_DMACxRXRLR_ARBS_Msk   /* Alternate Receive Buffer Size */
+#define ETH_DMACxRXRLR_RDRL_Pos                       (0U)
+#define ETH_DMACxRXRLR_RDRL_Msk                       (0x3FFUL << ETH_DMACxRXRLR_RDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxRXRLR_RDRL                           ETH_DMACxRXRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Interrupt Enable Register   ***************/
+#define ETH_DMACxIER_NIE_Pos                           (15U)
+#define ETH_DMACxIER_NIE_Msk                           (0x1UL << ETH_DMACxIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACxIER_NIE                               ETH_DMACxIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACxIER_AIE_Pos                           (14U)
+#define ETH_DMACxIER_AIE_Msk                           (0x1UL << ETH_DMACxIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACxIER_AIE                               ETH_DMACxIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACxIER_CDEE_Pos                          (13U)
+#define ETH_DMACxIER_CDEE_Msk                          (0x1UL << ETH_DMACxIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxIER_CDEE                              ETH_DMACxIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACxIER_FBEE_Pos                          (12U)
+#define ETH_DMACxIER_FBEE_Msk                          (0x1UL << ETH_DMACxIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxIER_FBEE                              ETH_DMACxIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACxIER_ERIE_Pos                          (11U)
+#define ETH_DMACxIER_ERIE_Msk                          (0x1UL << ETH_DMACxIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACxIER_ERIE                              ETH_DMACxIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACxIER_ETIE_Pos                          (10U)
+#define ETH_DMACxIER_ETIE_Msk                          (0x1UL << ETH_DMACxIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACxIER_ETIE                              ETH_DMACxIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACxIER_RWTE_Pos                          (9U)
+#define ETH_DMACxIER_RWTE_Msk                          (0x1UL << ETH_DMACxIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACxIER_RWTE                              ETH_DMACxIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACxIER_RSE_Pos                           (8U)
+#define ETH_DMACxIER_RSE_Msk                           (0x1UL << ETH_DMACxIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACxIER_RSE                               ETH_DMACxIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACxIER_RBUE_Pos                          (7U)
+#define ETH_DMACxIER_RBUE_Msk                          (0x1UL << ETH_DMACxIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACxIER_RBUE                              ETH_DMACxIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACxIER_RIE_Pos                           (6U)
+#define ETH_DMACxIER_RIE_Msk                           (0x1UL << ETH_DMACxIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACxIER_RIE                               ETH_DMACxIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACxIER_TBUE_Pos                          (2U)
+#define ETH_DMACxIER_TBUE_Msk                          (0x1UL << ETH_DMACxIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACxIER_TBUE                              ETH_DMACxIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACxIER_TXSE_Pos                          (1U)
+#define ETH_DMACxIER_TXSE_Msk                          (0x1UL << ETH_DMACxIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACxIER_TXSE                              ETH_DMACxIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACxIER_TIE_Pos                           (0U)
+#define ETH_DMACxIER_TIE_Msk                           (0x1UL << ETH_DMACxIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACxIER_TIE                               ETH_DMACxIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/************ Bit definition for Ethernet DMA Channel x Rx Interrupt Watchdog Timer Register   ***************/
+#define ETH_DMACxRXIWTR_RWTU_Pos                        (16U)
+#define ETH_DMACxRXIWTR_RWTU_Msk                        (0x3UL << ETH_DMACxRXIWTR_RWTU_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU                            ETH_DMACxRXIWTR_RWTU_Msk    /* Receive Interrupt Watchdog Timer Count Units */
+#define ETH_DMACxRXIWTR_RWTU_256                        ((uint32_t)0x00000000)   /* 256 */
+#define ETH_DMACxRXIWTR_RWTU_512_Pos                    (16U)
+#define ETH_DMACxRXIWTR_RWTU_512_Msk                    (0x1UL << ETH_DMACxRXIWTR_RWTU_512_Pos) /*!< 0x00010000 */
+#define ETH_DMACxRXIWTR_RWTU_512                        ETH_DMACxRXIWTR_RWTU_512_Msk    /* 512 */
+#define ETH_DMACxRXIWTR_RWTU_1024_Pos                   (17U)
+#define ETH_DMACxRXIWTR_RWTU_1024_Msk                   (0x1UL << ETH_DMACxRXIWTR_RWTU_1024_Pos) /*!< 0x00020000 */
+#define ETH_DMACxRXIWTR_RWTU_1024                       ETH_DMACxRXIWTR_RWTU_1024_Msk    /* 1024 */
+#define ETH_DMACxRXIWTR_RWTU_2048_Pos                   (16U)
+#define ETH_DMACxRXIWTR_RWTU_2048_Msk                   (0x3UL << ETH_DMACxRXIWTR_RWTU_2048_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU_2048                       ETH_DMACxRXIWTR_RWTU_2048_Msk    /* 2048 */
+#define ETH_DMACxRXIWTR_RWT_Pos                         (0U)
+#define ETH_DMACxRXIWTR_RWT_Msk                         (0xFFUL << ETH_DMACxRXIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACxRXIWTR_RWT                             ETH_DMACxRXIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/************ Bit definition for Ethernet DMA Channel x slot function control status Register   ***************/
+#define ETH_DMACxSFCSR_RSN_Pos                        (16U)
+#define ETH_DMACxSFCSR_RSN_Msk                        (0xFUL << ETH_DMACxSFCSR_RSN_Pos) /*!< 0x000F0000 */
+#define ETH_DMACxSFCSR_RSN                            ETH_DMACxSFCSR_RSN_Msk    /* Reference Slot Number */
+#define ETH_DMACxSFCSR_SIV_Pos                        (4U)
+#define ETH_DMACxSFCSR_SIV_Msk                        (0xFFFUL << ETH_DMACxSFCSR_SIV_Pos) /*!< 0x0000FFF0 */
+#define ETH_DMACxSFCSR_SIV                            ETH_DMACxSFCSR_SIV_Msk    /* Slot Interval Value */
+#define ETH_DMACxSFCSR_ASC_Pos                        (1U)
+#define ETH_DMACxSFCSR_ASC_Msk                        (0x1UL << ETH_DMACxSFCSR_ASC_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSFCSR_ASC                            ETH_DMACxSFCSR_ASC_Msk    /* Advance Slot Check */
+#define ETH_DMACxSFCSR_ESC_Pos                        (0U)
+#define ETH_DMACxSFCSR_ESC_Msk                        (0x1UL << ETH_DMACxSFCSR_ESC_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSFCSR_ESC                            ETH_DMACxSFCSR_ESC_Msk    /* Enable Slot Comparison */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Desc Register   ***************/
+#define ETH_DMACxCATXDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACxCATXDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXDR_CURTDESAPTR                     ETH_DMACxCATXDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Desc Register   ***************/
+#define ETH_DMACxCARXDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACxCARXDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXDR_CURRDESAPTR                     ETH_DMACxCARXDR_CURRDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Buffer Register   ***************/
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXBR_CURTBUFAPTR                     ETH_DMACxCATXBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Buffer Register   ***************/
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXBR_CURRBUFAPTR                     ETH_DMACxCARXBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Status Register   ***************/
+#define ETH_DMACxSR_REB_Pos                            (19U)
+#define ETH_DMACxSR_REB_Msk                            (0x7UL << ETH_DMACxSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACxSR_REB                                ETH_DMACxSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACxSR_TEB_Pos                            (16U)
+#define ETH_DMACxSR_TEB_Msk                            (0x7UL << ETH_DMACxSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACxSR_TEB                                ETH_DMACxSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACxSR_NIS_Pos                            (15U)
+#define ETH_DMACxSR_NIS_Msk                            (0x1UL << ETH_DMACxSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACxSR_NIS                                ETH_DMACxSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACxSR_AIS_Pos                            (14U)
+#define ETH_DMACxSR_AIS_Msk                            (0x1UL << ETH_DMACxSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACxSR_AIS                                ETH_DMACxSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACxSR_CDE_Pos                            (13U)
+#define ETH_DMACxSR_CDE_Msk                            (0x1UL << ETH_DMACxSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxSR_CDE                                ETH_DMACxSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACxSR_FBE_Pos                            (12U)
+#define ETH_DMACxSR_FBE_Msk                            (0x1UL << ETH_DMACxSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxSR_FBE                                ETH_DMACxSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACxSR_ERI_Pos                            (11U)
+#define ETH_DMACxSR_ERI_Msk                            (0x1UL << ETH_DMACxSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACxSR_ERI                                ETH_DMACxSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACxSR_ETI_Pos                            (10U)
+#define ETH_DMACxSR_ETI_Msk                            (0x1UL << ETH_DMACxSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACxSR_ETI                                ETH_DMACxSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACxSR_RWT_Pos                            (9U)
+#define ETH_DMACxSR_RWT_Msk                            (0x1UL << ETH_DMACxSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACxSR_RWT                                ETH_DMACxSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACxSR_RPS_Pos                            (8U)
+#define ETH_DMACxSR_RPS_Msk                            (0x1UL << ETH_DMACxSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACxSR_RPS                                ETH_DMACxSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACxSR_RBU_Pos                            (7U)
+#define ETH_DMACxSR_RBU_Msk                            (0x1UL << ETH_DMACxSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACxSR_RBU                                ETH_DMACxSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACxSR_RI_Pos                             (6U)
+#define ETH_DMACxSR_RI_Msk                             (0x1UL << ETH_DMACxSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACxSR_RI                                 ETH_DMACxSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACxSR_TBU_Pos                            (2U)
+#define ETH_DMACxSR_TBU_Msk                            (0x1UL << ETH_DMACxSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACxSR_TBU                                ETH_DMACxSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACxSR_TPS_Pos                            (1U)
+#define ETH_DMACxSR_TPS_Msk                            (0x1UL << ETH_DMACxSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSR_TPS                                ETH_DMACxSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACxSR_TI_Pos                             (0U)
+#define ETH_DMACxSR_TI_Msk                             (0x1UL << ETH_DMACxSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSR_TI                                 ETH_DMACxSR_TI_Msk        /* Transmit Interrupt */
+
+/************ Bit definition for Ethernet DMA Channel x missed frame count Register   ***************/
+#define ETH_DMACxMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACxMFCR_MFCO_Msk                         (0x1UL << ETH_DMACxMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACxMFCR_MFCO                             ETH_DMACxMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACxMFCR_MFC_Pos                          (0U)
+#define ETH_DMACxMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACxMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACxMFCR_MFC                              ETH_DMACxMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_RTSR1 register  *****************/
+#define EXTI_RTSR1_RT0_Pos           (0U)
+#define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
+#define EXTI_RTSR1_RT1_Pos           (1U)
+#define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
+#define EXTI_RTSR1_RT2_Pos           (2U)
+#define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
+#define EXTI_RTSR1_RT3_Pos           (3U)
+#define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
+#define EXTI_RTSR1_RT4_Pos           (4U)
+#define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
+#define EXTI_RTSR1_RT5_Pos           (5U)
+#define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
+#define EXTI_RTSR1_RT6_Pos           (6U)
+#define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
+#define EXTI_RTSR1_RT7_Pos           (7U)
+#define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
+#define EXTI_RTSR1_RT8_Pos           (8U)
+#define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
+#define EXTI_RTSR1_RT9_Pos           (9U)
+#define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
+#define EXTI_RTSR1_RT10_Pos          (10U)
+#define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
+#define EXTI_RTSR1_RT11_Pos          (11U)
+#define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
+#define EXTI_RTSR1_RT12_Pos          (12U)
+#define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
+#define EXTI_RTSR1_RT13_Pos          (13U)
+#define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
+#define EXTI_RTSR1_RT14_Pos          (14U)
+#define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
+#define EXTI_RTSR1_RT15_Pos          (15U)
+#define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
+#define EXTI_RTSR1_RT20_Pos          (20U)
+#define EXTI_RTSR1_RT20_Msk          (0x1UL << EXTI_RTSR1_RT20_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20              EXTI_RTSR1_RT20_Msk                       /*!< Rising trigger configuration for input line 20 */
+#define EXTI_RTSR1_RT21_Pos          (21U)
+#define EXTI_RTSR1_RT21_Msk          (0x1UL << EXTI_RTSR1_RT21_Pos)            /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21              EXTI_RTSR1_RT21_Msk                       /*!< Rising trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_FTSR1 register  *****************/
+#define EXTI_FTSR1_FT0_Pos           (0U)
+#define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
+#define EXTI_FTSR1_FT1_Pos           (1U)
+#define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
+#define EXTI_FTSR1_FT2_Pos           (2U)
+#define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
+#define EXTI_FTSR1_FT3_Pos           (3U)
+#define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
+#define EXTI_FTSR1_FT4_Pos           (4U)
+#define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
+#define EXTI_FTSR1_FT5_Pos           (5U)
+#define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
+#define EXTI_FTSR1_FT6_Pos           (6U)
+#define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
+#define EXTI_FTSR1_FT7_Pos           (7U)
+#define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
+#define EXTI_FTSR1_FT8_Pos           (8U)
+#define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
+#define EXTI_FTSR1_FT9_Pos           (9U)
+#define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
+#define EXTI_FTSR1_FT10_Pos          (10U)
+#define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
+#define EXTI_FTSR1_FT11_Pos          (11U)
+#define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
+#define EXTI_FTSR1_FT12_Pos          (12U)
+#define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
+#define EXTI_FTSR1_FT13_Pos          (13U)
+#define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
+#define EXTI_FTSR1_FT14_Pos          (14U)
+#define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
+#define EXTI_FTSR1_FT15_Pos          (15U)
+#define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
+#define EXTI_FTSR1_FT20_Pos          (20U)
+#define EXTI_FTSR1_FT20_Msk          (0x1UL << EXTI_FTSR1_FT20_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20              EXTI_FTSR1_FT20_Msk                       /*!< Falling trigger configuration for input line 20 */
+#define EXTI_FTSR1_FT21_Pos          (21U)
+#define EXTI_FTSR1_FT21_Msk          (0x1UL << EXTI_FTSR1_FT21_Pos)            /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21              EXTI_FTSR1_FT21_Msk                       /*!< Falling trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_SWIER1 register  ****************/
+#define EXTI_SWIER1_SWI0_Pos         (0U)
+#define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos         (1U)
+#define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos         (2U)
+#define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos         (3U)
+#define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos         (4U)
+#define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos         (5U)
+#define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos         (6U)
+#define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos         (7U)
+#define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos         (8U)
+#define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos         (9U)
+#define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos        (10U)
+#define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos        (11U)
+#define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos        (12U)
+#define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos        (13U)
+#define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos        (14U)
+#define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos        (15U)
+#define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI20_Pos        (20U)
+#define EXTI_SWIER1_SWI20_Msk        (0x1UL << EXTI_SWIER1_SWI20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20            EXTI_SWIER1_SWI20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos        (21U)
+#define EXTI_SWIER1_SWI21_Msk        (0x1UL << EXTI_SWIER1_SWI21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21            EXTI_SWIER1_SWI21_Msk                     /*!< Software Interrupt on line 21 */
+
+/*******************  Bit definition for EXTI_RPR1 register  ******************/
+#define EXTI_RPR1_RPIF0_Pos          (0U)
+#define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
+#define EXTI_RPR1_RPIF1_Pos          (1U)
+#define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
+#define EXTI_RPR1_RPIF2_Pos          (2U)
+#define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
+#define EXTI_RPR1_RPIF3_Pos          (3U)
+#define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
+#define EXTI_RPR1_RPIF4_Pos          (4U)
+#define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
+#define EXTI_RPR1_RPIF5_Pos          (5U)
+#define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
+#define EXTI_RPR1_RPIF6_Pos          (6U)
+#define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
+#define EXTI_RPR1_RPIF7_Pos          (7U)
+#define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
+#define EXTI_RPR1_RPIF8_Pos          (8U)
+#define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
+#define EXTI_RPR1_RPIF9_Pos          (9U)
+#define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
+#define EXTI_RPR1_RPIF10_Pos         (10U)
+#define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
+#define EXTI_RPR1_RPIF11_Pos         (11U)
+#define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
+#define EXTI_RPR1_RPIF12_Pos         (12U)
+#define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
+#define EXTI_RPR1_RPIF13_Pos         (13U)
+#define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
+#define EXTI_RPR1_RPIF14_Pos         (14U)
+#define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
+#define EXTI_RPR1_RPIF15_Pos         (15U)
+#define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
+#define EXTI_RPR1_RPIF20_Pos         (20U)
+#define EXTI_RPR1_RPIF20_Msk         (0x1UL << EXTI_RPR1_RPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_RPR1_RPIF20             EXTI_RPR1_RPIF20_Msk                      /*!< Rising Pending Interrupt Flag on line 20 */
+#define EXTI_RPR1_RPIF21_Pos         (21U)
+#define EXTI_RPR1_RPIF21_Msk         (0x1UL << EXTI_RPR1_RPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_RPR1_RPIF21             EXTI_RPR1_RPIF21_Msk                      /*!< Rising Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_FPR1 register  ******************/
+#define EXTI_FPR1_FPIF0_Pos          (0U)
+#define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
+#define EXTI_FPR1_FPIF1_Pos          (1U)
+#define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
+#define EXTI_FPR1_FPIF2_Pos          (2U)
+#define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
+#define EXTI_FPR1_FPIF3_Pos          (3U)
+#define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
+#define EXTI_FPR1_FPIF4_Pos          (4U)
+#define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
+#define EXTI_FPR1_FPIF5_Pos          (5U)
+#define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
+#define EXTI_FPR1_FPIF6_Pos          (6U)
+#define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
+#define EXTI_FPR1_FPIF7_Pos          (7U)
+#define EXTI_FPR1_FPIF7_Msk           (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
+#define EXTI_FPR1_FPIF8_Pos          (8U)
+#define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
+#define EXTI_FPR1_FPIF9_Pos          (9U)
+#define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
+#define EXTI_FPR1_FPIF10_Pos         (10U)
+#define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
+#define EXTI_FPR1_FPIF11_Pos         (11U)
+#define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
+#define EXTI_FPR1_FPIF12_Pos         (12U)
+#define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
+#define EXTI_FPR1_FPIF13_Pos         (13U)
+#define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
+#define EXTI_FPR1_FPIF14_Pos         (14U)
+#define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
+#define EXTI_FPR1_FPIF15_Pos         (15U)
+#define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
+#define EXTI_FPR1_FPIF20_Pos         (20U)
+#define EXTI_FPR1_FPIF20_Msk         (0x1UL << EXTI_FPR1_FPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_FPR1_FPIF20             EXTI_FPR1_FPIF20_Msk                      /*!< Falling Pending Interrupt Flag on line 20 */
+#define EXTI_FPR1_FPIF21_Pos         (21U)
+#define EXTI_FPR1_FPIF21_Msk         (0x1UL << EXTI_FPR1_FPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_FPR1_FPIF21             EXTI_FPR1_FPIF21_Msk                      /*!< Falling Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_SECCFGR1 register  ******************/
+#define EXTI_SECCFGR1_SEC0_Pos       (0U)
+#define EXTI_SECCFGR1_SEC0_Msk       (0x1UL << EXTI_SECCFGR1_SEC0_Pos)         /*!< 0x00000001 */
+#define EXTI_SECCFGR1_SEC0           EXTI_SECCFGR1_SEC0_Msk                    /*!< Security enable on line 0 */
+#define EXTI_SECCFGR1_SEC1_Pos       (1U)
+#define EXTI_SECCFGR1_SEC1_Msk       (0x1UL << EXTI_SECCFGR1_SEC1_Pos)         /*!< 0x00000002 */
+#define EXTI_SECCFGR1_SEC1           EXTI_SECCFGR1_SEC1_Msk                    /*!< Security enable on line 1 */
+#define EXTI_SECCFGR1_SEC2_Pos       (2U)
+#define EXTI_SECCFGR1_SEC2_Msk       (0x1UL << EXTI_SECCFGR1_SEC2_Pos)         /*!< 0x00000004 */
+#define EXTI_SECCFGR1_SEC2           EXTI_SECCFGR1_SEC2_Msk                    /*!< Security enable on line 2 */
+#define EXTI_SECCFGR1_SEC3_Pos       (3U)
+#define EXTI_SECCFGR1_SEC3_Msk       (0x1UL << EXTI_SECCFGR1_SEC3_Pos)         /*!< 0x00000008 */
+#define EXTI_SECCFGR1_SEC3           EXTI_SECCFGR1_SEC3_Msk                    /*!< Security enable on line 3 */
+#define EXTI_SECCFGR1_SEC4_Pos       (4U)
+#define EXTI_SECCFGR1_SEC4_Msk       (0x1UL << EXTI_SECCFGR1_SEC4_Pos)         /*!< 0x00000010 */
+#define EXTI_SECCFGR1_SEC4           EXTI_SECCFGR1_SEC4_Msk                    /*!< Security enable on line 4 */
+#define EXTI_SECCFGR1_SEC5_Pos       (5U)
+#define EXTI_SECCFGR1_SEC5_Msk       (0x1UL << EXTI_SECCFGR1_SEC5_Pos)         /*!< 0x00000020 */
+#define EXTI_SECCFGR1_SEC5           EXTI_SECCFGR1_SEC5_Msk                    /*!< Security enable on line 5 */
+#define EXTI_SECCFGR1_SEC6_Pos       (6U)
+#define EXTI_SECCFGR1_SEC6_Msk       (0x1UL << EXTI_SECCFGR1_SEC6_Pos)         /*!< 0x00000040 */
+#define EXTI_SECCFGR1_SEC6           EXTI_SECCFGR1_SEC6_Msk                    /*!< Security enable on line 6 */
+#define EXTI_SECCFGR1_SEC7_Pos       (7U)
+#define EXTI_SECCFGR1_SEC7_Msk       (0x1UL << EXTI_SECCFGR1_SEC7_Pos)         /*!< 0x00000080 */
+#define EXTI_SECCFGR1_SEC7           EXTI_SECCFGR1_SEC7_Msk                    /*!< Security enable on line 7 */
+#define EXTI_SECCFGR1_SEC8_Pos       (8U)
+#define EXTI_SECCFGR1_SEC8_Msk       (0x1UL << EXTI_SECCFGR1_SEC8_Pos)         /*!< 0x00000100 */
+#define EXTI_SECCFGR1_SEC8           EXTI_SECCFGR1_SEC8_Msk                    /*!< Security enable on line 8 */
+#define EXTI_SECCFGR1_SEC9_Pos       (9U)
+#define EXTI_SECCFGR1_SEC9_Msk       (0x1UL << EXTI_SECCFGR1_SEC9_Pos)         /*!< 0x00000200 */
+#define EXTI_SECCFGR1_SEC9           EXTI_SECCFGR1_SEC9_Msk                    /*!< Security enable on line 9 */
+#define EXTI_SECCFGR1_SEC10_Pos      (10U)
+#define EXTI_SECCFGR1_SEC10_Msk      (0x1UL << EXTI_SECCFGR1_SEC10_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR1_SEC10          EXTI_SECCFGR1_SEC10_Msk                   /*!< Security enable on line 10 */
+#define EXTI_SECCFGR1_SEC11_Pos      (11U)
+#define EXTI_SECCFGR1_SEC11_Msk      (0x1UL << EXTI_SECCFGR1_SEC11_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR1_SEC11          EXTI_SECCFGR1_SEC11_Msk                   /*!< Security enable on line 11 */
+#define EXTI_SECCFGR1_SEC12_Pos      (12U)
+#define EXTI_SECCFGR1_SEC12_Msk      (0x1UL << EXTI_SECCFGR1_SEC12_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR1_SEC12          EXTI_SECCFGR1_SEC12_Msk                   /*!< Security enable on line 12 */
+#define EXTI_SECCFGR1_SEC13_Pos      (13U)
+#define EXTI_SECCFGR1_SEC13_Msk      (0x1UL << EXTI_SECCFGR1_SEC13_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR1_SEC13          EXTI_SECCFGR1_SEC13_Msk                   /*!< Security enable on line 13 */
+#define EXTI_SECCFGR1_SEC14_Pos      (14U)
+#define EXTI_SECCFGR1_SEC14_Msk      (0x1UL << EXTI_SECCFGR1_SEC14_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR1_SEC14          EXTI_SECCFGR1_SEC14_Msk                   /*!< Security enable on line 14 */
+#define EXTI_SECCFGR1_SEC15_Pos      (15U)
+#define EXTI_SECCFGR1_SEC15_Msk      (0x1UL << EXTI_SECCFGR1_SEC15_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR1_SEC15          EXTI_SECCFGR1_SEC15_Msk                   /*!< Security enable on line 15 */
+#define EXTI_SECCFGR1_SEC17_Pos      (17U)
+#define EXTI_SECCFGR1_SEC17_Msk      (0x1UL << EXTI_SECCFGR1_SEC17_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR1_SEC17          EXTI_SECCFGR1_SEC17_Msk                   /*!< Security enable on line 17 */
+#define EXTI_SECCFGR1_SEC18_Pos      (18U)
+#define EXTI_SECCFGR1_SEC18_Msk      (0x1UL << EXTI_SECCFGR1_SEC18_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR1_SEC18          EXTI_SECCFGR1_SEC18_Msk                   /*!< Security enable on line 18 */
+#define EXTI_SECCFGR1_SEC19_Pos      (19U)
+#define EXTI_SECCFGR1_SEC19_Msk      (0x1UL << EXTI_SECCFGR1_SEC19_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR1_SEC19          EXTI_SECCFGR1_SEC19_Msk                   /*!< Security enable on line 19 */
+#define EXTI_SECCFGR1_SEC20_Pos      (20U)
+#define EXTI_SECCFGR1_SEC20_Msk      (0x1UL << EXTI_SECCFGR1_SEC20_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR1_SEC20          EXTI_SECCFGR1_SEC20_Msk                   /*!< Security enable on line 20 */
+#define EXTI_SECCFGR1_SEC21_Pos      (21U)
+#define EXTI_SECCFGR1_SEC21_Msk      (0x1UL << EXTI_SECCFGR1_SEC21_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR1_SEC21          EXTI_SECCFGR1_SEC21_Msk                   /*!< Security enable on line 21 */
+#define EXTI_SECCFGR1_SEC22_Pos      (22U)
+#define EXTI_SECCFGR1_SEC22_Msk      (0x1UL << EXTI_SECCFGR1_SEC22_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR1_SEC22          EXTI_SECCFGR1_SEC22_Msk                   /*!< Security enable on line 22 */
+#define EXTI_SECCFGR1_SEC23_Pos      (23U)
+#define EXTI_SECCFGR1_SEC23_Msk      (0x1UL << EXTI_SECCFGR1_SEC23_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR1_SEC23          EXTI_SECCFGR1_SEC23_Msk                   /*!< Security enable on line 23 */
+#define EXTI_SECCFGR1_SEC24_Pos      (24U)
+#define EXTI_SECCFGR1_SEC24_Msk      (0x1UL << EXTI_SECCFGR1_SEC24_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR1_SEC24          EXTI_SECCFGR1_SEC24_Msk                   /*!< Security enable on line 24 */
+#define EXTI_SECCFGR1_SEC25_Pos      (25U)
+#define EXTI_SECCFGR1_SEC25_Msk      (0x1UL << EXTI_SECCFGR1_SEC25_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR1_SEC25          EXTI_SECCFGR1_SEC25_Msk                   /*!< Security enable on line 25 */
+#define EXTI_SECCFGR1_SEC26_Pos      (26U)
+#define EXTI_SECCFGR1_SEC26_Msk      (0x1UL << EXTI_SECCFGR1_SEC26_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR1_SEC26          EXTI_SECCFGR1_SEC26_Msk                   /*!< Security enable on line 26 */
+#define EXTI_SECCFGR1_SEC27_Pos      (27U)
+#define EXTI_SECCFGR1_SEC27_Msk      (0x1UL << EXTI_SECCFGR1_SEC27_Pos)        /*!< 0x08000000 */
+#define EXTI_SECCFGR1_SEC27          EXTI_SECCFGR1_SEC27_Msk                   /*!< Security enable on line 27 */
+#define EXTI_SECCFGR1_SEC28_Pos      (28U)
+#define EXTI_SECCFGR1_SEC28_Msk      (0x1UL << EXTI_SECCFGR1_SEC28_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR1_SEC28          EXTI_SECCFGR1_SEC28_Msk                   /*!< Security enable on line 28 */
+#define EXTI_SECCFGR1_SEC29_Pos      (29U)
+#define EXTI_SECCFGR1_SEC29_Msk      (0x1UL << EXTI_SECCFGR1_SEC29_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR1_SEC29          EXTI_SECCFGR1_SEC29_Msk                   /*!< Security enable on line 29 */
+#define EXTI_SECCFGR1_SEC30_Pos      (30U)
+#define EXTI_SECCFGR1_SEC30_Msk      (0x1UL << EXTI_SECCFGR1_SEC30_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR1_SEC30          EXTI_SECCFGR1_SEC30_Msk                   /*!< Security enable on line 30 */
+#define EXTI_SECCFGR1_SEC31_Pos      (31U)
+#define EXTI_SECCFGR1_SEC31_Msk      (0x1UL << EXTI_SECCFGR1_SEC31_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR1_SEC31          EXTI_SECCFGR1_SEC31_Msk                   /*!< Security enable on line 31 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR1 register  ******************/
+#define EXTI_PRIVCFGR1_PRIV0_Pos     (0U)
+#define EXTI_PRIVCFGR1_PRIV0_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos)       /*!< 0x00000001 */
+#define EXTI_PRIVCFGR1_PRIV0         EXTI_PRIVCFGR1_PRIV0_Msk                  /*!< Privilege enable on line 0 */
+#define EXTI_PRIVCFGR1_PRIV1_Pos     (1U)
+#define EXTI_PRIVCFGR1_PRIV1_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos)       /*!< 0x00000002 */
+#define EXTI_PRIVCFGR1_PRIV1         EXTI_PRIVCFGR1_PRIV1_Msk                  /*!< Privilege enable on line 1 */
+#define EXTI_PRIVCFGR1_PRIV2_Pos     (2U)
+#define EXTI_PRIVCFGR1_PRIV2_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos)       /*!< 0x00000004 */
+#define EXTI_PRIVCFGR1_PRIV2         EXTI_PRIVCFGR1_PRIV2_Msk                  /*!< Privilege enable on line 2 */
+#define EXTI_PRIVCFGR1_PRIV3_Pos     (3U)
+#define EXTI_PRIVCFGR1_PRIV3_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos)       /*!< 0x00000008 */
+#define EXTI_PRIVCFGR1_PRIV3         EXTI_PRIVCFGR1_PRIV3_Msk                  /*!< Privilege enable on line 3 */
+#define EXTI_PRIVCFGR1_PRIV4_Pos     (4U)
+#define EXTI_PRIVCFGR1_PRIV4_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos)       /*!< 0x00000010 */
+#define EXTI_PRIVCFGR1_PRIV4         EXTI_PRIVCFGR1_PRIV4_Msk                  /*!< Privilege enable on line 4 */
+#define EXTI_PRIVCFGR1_PRIV5_Pos     (5U)
+#define EXTI_PRIVCFGR1_PRIV5_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos)       /*!< 0x00000020 */
+#define EXTI_PRIVCFGR1_PRIV5         EXTI_PRIVCFGR1_PRIV5_Msk                  /*!< Privilege enable on line 5 */
+#define EXTI_PRIVCFGR1_PRIV6_Pos     (6U)
+#define EXTI_PRIVCFGR1_PRIV6_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos)       /*!< 0x00000040 */
+#define EXTI_PRIVCFGR1_PRIV6         EXTI_PRIVCFGR1_PRIV6_Msk                  /*!< Privilege enable on line 6 */
+#define EXTI_PRIVCFGR1_PRIV7_Pos     (7U)
+#define EXTI_PRIVCFGR1_PRIV7_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos)       /*!< 0x00000080 */
+#define EXTI_PRIVCFGR1_PRIV7         EXTI_PRIVCFGR1_PRIV7_Msk                  /*!< Privilege enable on line 7 */
+#define EXTI_PRIVCFGR1_PRIV8_Pos     (8U)
+#define EXTI_PRIVCFGR1_PRIV8_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos)       /*!< 0x00000100 */
+#define EXTI_PRIVCFGR1_PRIV8         EXTI_PRIVCFGR1_PRIV8_Msk                  /*!< Privilege enable on line 8 */
+#define EXTI_PRIVCFGR1_PRIV9_Pos     (9U)
+#define EXTI_PRIVCFGR1_PRIV9_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos)       /*!< 0x00000200 */
+#define EXTI_PRIVCFGR1_PRIV9         EXTI_PRIVCFGR1_PRIV9_Msk                  /*!< Privilege enable on line 9 */
+#define EXTI_PRIVCFGR1_PRIV10_Pos    (10U)
+#define EXTI_PRIVCFGR1_PRIV10_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR1_PRIV10        EXTI_PRIVCFGR1_PRIV10_Msk                 /*!< Privilege enable on line 10 */
+#define EXTI_PRIVCFGR1_PRIV11_Pos    (11U)
+#define EXTI_PRIVCFGR1_PRIV11_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR1_PRIV11        EXTI_PRIVCFGR1_PRIV11_Msk                 /*!< Privilege enable on line 11 */
+#define EXTI_PRIVCFGR1_PRIV12_Pos    (12U)
+#define EXTI_PRIVCFGR1_PRIV12_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR1_PRIV12        EXTI_PRIVCFGR1_PRIV12_Msk                 /*!< Privilege enable on line 12 */
+#define EXTI_PRIVCFGR1_PRIV13_Pos    (13U)
+#define EXTI_PRIVCFGR1_PRIV13_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR1_PRIV13        EXTI_PRIVCFGR1_PRIV13_Msk                 /*!< Privilege enable on line 13 */
+#define EXTI_PRIVCFGR1_PRIV14_Pos    (14U)
+#define EXTI_PRIVCFGR1_PRIV14_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR1_PRIV14        EXTI_PRIVCFGR1_PRIV14_Msk                 /*!< Privilege enable on line 14 */
+#define EXTI_PRIVCFGR1_PRIV15_Pos    (15U)
+#define EXTI_PRIVCFGR1_PRIV15_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR1_PRIV15        EXTI_PRIVCFGR1_PRIV15_Msk                 /*!< Privilege enable on line 15 */
+#define EXTI_PRIVCFGR1_PRIV17_Pos    (17U)
+#define EXTI_PRIVCFGR1_PRIV17_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR1_PRIV17        EXTI_PRIVCFGR1_PRIV17_Msk                 /*!< Privilege enable on line 17 */
+#define EXTI_PRIVCFGR1_PRIV18_Pos    (18U)
+#define EXTI_PRIVCFGR1_PRIV18_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR1_PRIV18        EXTI_PRIVCFGR1_PRIV18_Msk                 /*!< Privilege enable on line 18 */
+#define EXTI_PRIVCFGR1_PRIV19_Pos    (19U)
+#define EXTI_PRIVCFGR1_PRIV19_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR1_PRIV19        EXTI_PRIVCFGR1_PRIV19_Msk                 /*!< Privilege enable on line 19 */
+#define EXTI_PRIVCFGR1_PRIV20_Pos    (20U)
+#define EXTI_PRIVCFGR1_PRIV20_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR1_PRIV20        EXTI_PRIVCFGR1_PRIV20_Msk                 /*!< Privilege enable on line 20 */
+#define EXTI_PRIVCFGR1_PRIV21_Pos    (21U)
+#define EXTI_PRIVCFGR1_PRIV21_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR1_PRIV21        EXTI_PRIVCFGR1_PRIV21_Msk                 /*!< Privilege enable on line 21 */
+#define EXTI_PRIVCFGR1_PRIV22_Pos    (22U)
+#define EXTI_PRIVCFGR1_PRIV22_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR1_PRIV22        EXTI_PRIVCFGR1_PRIV22_Msk                 /*!< Privilege enable on line 22 */
+#define EXTI_PRIVCFGR1_PRIV23_Pos    (23U)
+#define EXTI_PRIVCFGR1_PRIV23_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR1_PRIV23        EXTI_PRIVCFGR1_PRIV23_Msk                 /*!< Privilege enable on line 23 */
+#define EXTI_PRIVCFGR1_PRIV24_Pos    (24U)
+#define EXTI_PRIVCFGR1_PRIV24_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR1_PRIV24        EXTI_PRIVCFGR1_PRIV24_Msk                 /*!< Privilege enable on line 24 */
+#define EXTI_PRIVCFGR1_PRIV25_Pos    (25U)
+#define EXTI_PRIVCFGR1_PRIV25_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR1_PRIV25        EXTI_PRIVCFGR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
+#define EXTI_PRIVCFGR1_PRIV26_Pos    (26U)
+#define EXTI_PRIVCFGR1_PRIV26_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR1_PRIV26        EXTI_PRIVCFGR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
+#define EXTI_PRIVCFGR1_PRIV27_Pos    (27U)
+#define EXTI_PRIVCFGR1_PRIV27_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos)      /*!< 0x08000000 */
+#define EXTI_PRIVCFGR1_PRIV27        EXTI_PRIVCFGR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
+#define EXTI_PRIVCFGR1_PRIV28_Pos    (28U)
+#define EXTI_PRIVCFGR1_PRIV28_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR1_PRIV28        EXTI_PRIVCFGR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
+#define EXTI_PRIVCFGR1_PRIV29_Pos    (29U)
+#define EXTI_PRIVCFGR1_PRIV29_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR1_PRIV29        EXTI_PRIVCFGR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
+#define EXTI_PRIVCFGR1_PRIV30_Pos    (30U)
+#define EXTI_PRIVCFGR1_PRIV30_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR1_PRIV30        EXTI_PRIVCFGR1_PRIV30_Msk                 /*!< Privilege enable on line 30 */
+#define EXTI_PRIVCFGR1_PRIV31_Pos    (31U)
+#define EXTI_PRIVCFGR1_PRIV31_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR1_PRIV31        EXTI_PRIVCFGR1_PRIV31_Msk                 /*!< Privilege enable on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR2 register  *****************/
+#define EXTI_RTSR2_RT39_Pos          (7U)
+#define EXTI_RTSR2_RT39_Msk          (0x1UL << EXTI_RTSR2_RT39_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR2_RT39              EXTI_RTSR2_RT39_Msk                       /*!< Rising trigger configuration for input line 39 */
+#define EXTI_RTSR2_RT40_Pos          (8U)
+#define EXTI_RTSR2_RT40_Msk          (0x1UL << EXTI_RTSR2_RT40_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR2_RT40              EXTI_RTSR2_RT40_Msk                       /*!< Rising trigger configuration for input line 40 */
+#define EXTI_RTSR2_RT51_Pos          (19U)
+#define EXTI_RTSR2_RT51_Msk          (0x1UL << EXTI_RTSR2_RT51_Pos)            /*!< 0x00080000 */
+#define EXTI_RTSR2_RT51              EXTI_RTSR2_RT51_Msk                       /*!< Rising trigger configuration for input line 51 */
+#define EXTI_RTSR2_RT54_Pos          (22U)
+#define EXTI_RTSR2_RT54_Msk          (0x1UL << EXTI_RTSR2_RT54_Pos)            /*!< 0x00400000 */
+#define EXTI_RTSR2_RT54              EXTI_RTSR2_RT54_Msk                       /*!< Rising trigger configuration for input line 54 */
+#define EXTI_RTSR2_RT56_Pos          (24U)
+#define EXTI_RTSR2_RT56_Msk          (0x1UL << EXTI_RTSR2_RT56_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR2_RT56              EXTI_RTSR2_RT56_Msk                       /*!< Rising trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_FTSR2 register  *****************/
+#define EXTI_FTSR2_FT39_Pos          (7U)
+#define EXTI_FTSR2_FT39_Msk          (0x1UL << EXTI_FTSR2_FT39_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR2_FT39              EXTI_FTSR2_FT39_Msk                       /*!< Falling trigger configuration for input line 39 */
+#define EXTI_FTSR2_FT40_Pos          (8U)
+#define EXTI_FTSR2_FT40_Msk          (0x1UL << EXTI_FTSR2_FT40_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR2_FT40              EXTI_FTSR2_FT40_Msk                       /*!< Falling trigger configuration for input line 40 */
+#define EXTI_FTSR2_FT51_Pos          (19U)
+#define EXTI_FTSR2_FT51_Msk          (0x1UL << EXTI_FTSR2_FT51_Pos)            /*!< 0x00080000 */
+#define EXTI_FTSR2_FT51              EXTI_FTSR2_FT51_Msk                       /*!< Falling trigger configuration for input line 51 */
+#define EXTI_FTSR2_FT54_Pos          (22U)
+#define EXTI_FTSR2_FT54_Msk          (0x1UL << EXTI_FTSR2_FT54_Pos)            /*!< 0x00400000 */
+#define EXTI_FTSR2_FT54              EXTI_FTSR2_FT54_Msk                       /*!< Falling trigger configuration for input line 54 */
+#define EXTI_FTSR2_FT56_Pos          (24U)
+#define EXTI_FTSR2_FT56_Msk          (0x1UL << EXTI_FTSR2_FT56_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR2_FT56              EXTI_FTSR2_FT56_Msk                       /*!< Falling trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_SWIER2 register  ****************/
+#define EXTI_SWIER2_SWI39_Pos        (7U)
+#define EXTI_SWIER2_SWI39_Msk        (0x1UL << EXTI_SWIER2_SWI39_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER2_SWI39            EXTI_SWIER2_SWI39_Msk                     /*!< Software Interrupt on line 39 */
+#define EXTI_SWIER2_SWI40_Pos        (8U)
+#define EXTI_SWIER2_SWI40_Msk        (0x1UL << EXTI_SWIER2_SWI40_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER2_SWI40            EXTI_SWIER2_SWI40_Msk                     /*!< Software Interrupt on line 40 */
+#define EXTI_SWIER2_SWI51_Pos        (19U)
+#define EXTI_SWIER2_SWI51_Msk        (0x1UL << EXTI_SWIER2_SWI51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWI51            EXTI_SWIER2_SWI51_Msk                     /*!< Software Interrupt on line 51 */
+#define EXTI_SWIER2_SWI54_Pos        (22U)
+#define EXTI_SWIER2_SWI54_Msk        (0x1UL << EXTI_SWIER2_SWI54_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER2_SWI54            EXTI_SWIER2_SWI54_Msk                     /*!< Software Interrupt on line 54 */
+#define EXTI_SWIER2_SWI56_Pos        (24U)
+#define EXTI_SWIER2_SWI56_Msk        (0x1UL << EXTI_SWIER2_SWI56_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER2_SWI56            EXTI_SWIER2_SWI56_Msk                     /*!< Software Interrupt on line 56 */
+
+/*******************  Bit definition for EXTI_RPR2 register  ******************/
+#define EXTI_RPR2_RPIF39_Pos         (7U)
+#define EXTI_RPR2_RPIF39_Msk         (0x1UL << EXTI_RPR2_RPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR2_RPIF39             EXTI_RPR2_RPIF39_Msk                      /*!< Rising Pending Interrupt Flag on line 39 */
+#define EXTI_RPR2_RPIF40_Pos         (8U)
+#define EXTI_RPR2_RPIF40_Msk         (0x1UL << EXTI_RPR2_RPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR2_RPIF40             EXTI_RPR2_RPIF40_Msk                      /*!< Rising Pending Interrupt Flag on line 40 */
+#define EXTI_RPR2_RPIF51_Pos         (19U)
+#define EXTI_RPR2_RPIF51_Msk         (0x1UL << EXTI_RPR2_RPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_RPR2_RPIF51             EXTI_RPR2_RPIF51_Msk                      /*!< Rising Pending Interrupt Flag on line 51 */
+#define EXTI_RPR2_RPIF54_Pos         (22U)
+#define EXTI_RPR2_RPIF54_Msk         (0x1UL << EXTI_RPR2_RPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_RPR2_RPIF54             EXTI_RPR2_RPIF54_Msk                      /*!< Rising Pending Interrupt Flag on line 54 */
+#define EXTI_RPR2_RPIF56_Pos         (24U)
+#define EXTI_RPR2_RPIF56_Msk         (0x1UL << EXTI_RPR2_RPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_RPR2_RPIF56             EXTI_RPR2_RPIF56_Msk                      /*!< Rising Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_FPR2 register  ******************/
+#define EXTI_FPR2_FPIF39_Pos         (7U)
+#define EXTI_FPR2_FPIF39_Msk         (0x1UL << EXTI_FPR2_FPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR2_FPIF39             EXTI_FPR2_FPIF39_Msk                      /*!< Falling Pending Interrupt Flag on line 39 */
+#define EXTI_FPR2_FPIF40_Pos         (8U)
+#define EXTI_FPR2_FPIF40_Msk         (0x1UL << EXTI_FPR2_FPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR2_FPIF40             EXTI_FPR2_FPIF40_Msk                      /*!< Falling Pending Interrupt Flag on line 40 */
+#define EXTI_FPR2_FPIF51_Pos         (19U)
+#define EXTI_FPR2_FPIF51_Msk         (0x1UL << EXTI_FPR2_FPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_FPR2_FPIF51             EXTI_FPR2_FPIF51_Msk                      /*!< Falling Pending Interrupt Flag on line 51 */
+#define EXTI_FPR2_FPIF54_Pos         (22U)
+#define EXTI_FPR2_FPIF54_Msk         (0x1UL << EXTI_FPR2_FPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_FPR2_FPIF54             EXTI_FPR2_FPIF54_Msk                      /*!< Falling Pending Interrupt Flag on line 54 */
+#define EXTI_FPR2_FPIF56_Pos         (24U)
+#define EXTI_FPR2_FPIF56_Msk         (0x1UL << EXTI_FPR2_FPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_FPR2_FPIF56             EXTI_FPR2_FPIF56_Msk                      /*!< Falling Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_SECCFGR2 register  ******************/
+#define EXTI_SECCFGR2_SEC32_Pos      (0U)
+#define EXTI_SECCFGR2_SEC32_Msk      (0x1UL << EXTI_SECCFGR2_SEC32_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR2_SEC32          EXTI_SECCFGR2_SEC32_Msk                   /*!< Security enable on line 32 */
+#define EXTI_SECCFGR2_SEC33_Pos      (1U)
+#define EXTI_SECCFGR2_SEC33_Msk      (0x1UL << EXTI_SECCFGR2_SEC33_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR2_SEC33          EXTI_SECCFGR2_SEC33_Msk                   /*!< Security enable on line 33 */
+#define EXTI_SECCFGR2_SEC34_Pos      (2U)
+#define EXTI_SECCFGR2_SEC34_Msk      (0x1UL << EXTI_SECCFGR2_SEC34_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR2_SEC34          EXTI_SECCFGR2_SEC34_Msk                   /*!< Security enable on line 34 */
+#define EXTI_SECCFGR2_SEC35_Pos      (3U)
+#define EXTI_SECCFGR2_SEC35_Msk      (0x1UL << EXTI_SECCFGR2_SEC35_Pos)        /*!< 0x00000008 */
+#define EXTI_SECCFGR2_SEC35          EXTI_SECCFGR2_SEC35_Msk                   /*!< Security enable on line 35 */
+#define EXTI_SECCFGR2_SEC36_Pos      (4U)
+#define EXTI_SECCFGR2_SEC36_Msk      (0x1UL << EXTI_SECCFGR2_SEC36_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR2_SEC36          EXTI_SECCFGR2_SEC36_Msk                   /*!< Security enable on line 36 */
+#define EXTI_SECCFGR2_SEC37_Pos      (5U)
+#define EXTI_SECCFGR2_SEC37_Msk      (0x1UL << EXTI_SECCFGR2_SEC37_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR2_SEC37          EXTI_SECCFGR2_SEC37_Msk                   /*!< Security enable on line 37 */
+#define EXTI_SECCFGR2_SEC38_Pos      (6U)
+#define EXTI_SECCFGR2_SEC38_Msk      (0x1UL << EXTI_SECCFGR2_SEC38_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR2_SEC38          EXTI_SECCFGR2_SEC38_Msk                   /*!< Security enable on line 38 */
+#define EXTI_SECCFGR2_SEC39_Pos      (7U)
+#define EXTI_SECCFGR2_SEC39_Msk      (0x1UL << EXTI_SECCFGR2_SEC39_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR2_SEC39          EXTI_SECCFGR2_SEC39_Msk                   /*!< Security enable on line 39 */
+#define EXTI_SECCFGR2_SEC40_Pos      (8U)
+#define EXTI_SECCFGR2_SEC40_Msk      (0x1UL << EXTI_SECCFGR2_SEC40_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR2_SEC40          EXTI_SECCFGR2_SEC40_Msk                   /*!< Security enable on line 40 */
+#define EXTI_SECCFGR2_SEC41_Pos      (9U)
+#define EXTI_SECCFGR2_SEC41_Msk      (0x1UL << EXTI_SECCFGR2_SEC41_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR2_SEC41          EXTI_SECCFGR2_SEC41_Msk                   /*!< Security enable on line 41 */
+#define EXTI_SECCFGR2_SEC42_Pos      (10U)
+#define EXTI_SECCFGR2_SEC42_Msk      (0x1UL << EXTI_SECCFGR2_SEC42_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR2_SEC42          EXTI_SECCFGR2_SEC42_Msk                   /*!< Security enable on line 42 */
+#define EXTI_SECCFGR2_SEC43_Pos      (11U)
+#define EXTI_SECCFGR2_SEC43_Msk      (0x1UL << EXTI_SECCFGR2_SEC43_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR2_SEC43          EXTI_SECCFGR2_SEC43_Msk                   /*!< Security enable on line 43 */
+#define EXTI_SECCFGR2_SEC44_Pos      (12U)
+#define EXTI_SECCFGR2_SEC44_Msk      (0x1UL << EXTI_SECCFGR2_SEC44_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR2_SEC44          EXTI_SECCFGR2_SEC44_Msk                   /*!< Security enable on line 44 */
+#define EXTI_SECCFGR2_SEC45_Pos      (13U)
+#define EXTI_SECCFGR2_SEC45_Msk      (0x1UL << EXTI_SECCFGR2_SEC45_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR2_SEC45          EXTI_SECCFGR2_SEC45                       /*!< Security enable on line 45 */
+#define EXTI_SECCFGR2_SEC46_Pos      (14U)
+#define EXTI_SECCFGR2_SEC46_Msk      (0x1UL << EXTI_SECCFGR2_SEC46_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR2_SEC46          EXTI_SECCFGR2_SEC46_Msk                   /*!< Security enable on line 46 */
+#define EXTI_SECCFGR2_SEC47_Pos      (15U)
+#define EXTI_SECCFGR2_SEC47_Msk      (0x1UL << EXTI_SECCFGR2_SEC47_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR2_SEC47          EXTI_SECCFGR2_SEC47_Msk                   /*!< Security enable on line 47 */
+#define EXTI_SECCFGR2_SEC48_Pos      (16U)
+#define EXTI_SECCFGR2_SEC48_Msk      (0x1UL << EXTI_SECCFGR2_SEC48_Pos)        /*!< 0x00010000 */
+#define EXTI_SECCFGR2_SEC48          EXTI_SECCFGR2_SEC48_Msk                   /*!< Security enable on line 48 */
+#define EXTI_SECCFGR2_SEC49_Pos      (17U)
+#define EXTI_SECCFGR2_SEC49_Msk      (0x1UL << EXTI_SECCFGR2_SEC49_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR2_SEC49          EXTI_SECCFGR2_SEC49_Msk                   /*!< Security enable on line 49 */
+#define EXTI_SECCFGR2_SEC50_Pos      (18U)
+#define EXTI_SECCFGR2_SEC50_Msk      (0x1UL << EXTI_SECCFGR2_SEC50_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR2_SEC50          EXTI_SECCFGR2_SEC50_Msk                   /*!< Security enable on line 50 */
+#define EXTI_SECCFGR2_SEC51_Pos      (19U)
+#define EXTI_SECCFGR2_SEC51_Msk      (0x1UL << EXTI_SECCFGR2_SEC51_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR2_SEC51          EXTI_SECCFGR2_SEC51_Msk                   /*!< Security enable on line 51 */
+#define EXTI_SECCFGR2_SEC52_Pos      (20U)
+#define EXTI_SECCFGR2_SEC52_Msk      (0x1UL << EXTI_SECCFGR2_SEC52_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR2_SEC52          EXTI_SECCFGR2_SEC52_Msk                   /*!< Security enable on line 52 */
+#define EXTI_SECCFGR2_SEC53_Pos      (21U)
+#define EXTI_SECCFGR2_SEC53_Msk      (0x1UL << EXTI_SECCFGR2_SEC53_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR2_SEC53          EXTI_SECCFGR2_SEC53_Msk                   /*!< Security enable on line 53 */
+#define EXTI_SECCFGR2_SEC54_Pos      (22U)
+#define EXTI_SECCFGR2_SEC54_Msk      (0x1UL << EXTI_SECCFGR2_SEC54_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR2_SEC54          EXTI_SECCFGR2_SEC54_Msk                   /*!< Security enable on line 54 */
+#define EXTI_SECCFGR2_SEC55_Pos      (23U)
+#define EXTI_SECCFGR2_SEC55_Msk      (0x1UL << EXTI_SECCFGR2_SEC55_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR2_SEC55          EXTI_SECCFGR2_SEC55_Msk                   /*!< Security enable on line 55 */
+#define EXTI_SECCFGR2_SEC56_Pos      (24U)
+#define EXTI_SECCFGR2_SEC56_Msk      (0x1UL << EXTI_SECCFGR2_SEC56_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR2_SEC56          EXTI_SECCFGR2_SEC56_Msk                   /*!< Security enable on line 56 */
+#define EXTI_SECCFGR2_SEC57_Pos      (25U)
+#define EXTI_SECCFGR2_SEC57_Msk      (0x1UL << EXTI_SECCFGR2_SEC57_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR2_SEC57          EXTI_SECCFGR2_SEC57_Msk                   /*!< Security enable on line 57 */
+#define EXTI_SECCFGR2_SEC58_Pos      (26U)
+#define EXTI_SECCFGR2_SEC58_Msk      (0x1UL << EXTI_SECCFGR2_SEC58_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR2_SEC58          EXTI_SECCFGR2_SEC58_Msk                   /*!< Security enable on line 58 */
+#define EXTI_SECCFGR2_SEC60_Pos      (28U)
+#define EXTI_SECCFGR2_SEC60_Msk      (0x1UL << EXTI_SECCFGR2_SEC60_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR2_SEC60          EXTI_SECCFGR2_SEC60_Msk                   /*!< Security enable on line 60 */
+#define EXTI_SECCFGR2_SEC61_Pos      (29U)
+#define EXTI_SECCFGR2_SEC61_Msk      (0x1UL << EXTI_SECCFGR2_SEC61_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR2_SEC61          EXTI_SECCFGR2_SEC61_Msk                   /*!< Security enable on line 61 */
+#define EXTI_SECCFGR2_SEC62_Pos      (30U)
+#define EXTI_SECCFGR2_SEC62_Msk      (0x1UL << EXTI_SECCFGR2_SEC62_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR2_SEC62          EXTI_SECCFGR2_SEC62_Msk                   /*!< Security enable on line 62 */
+#define EXTI_SECCFGR2_SEC63_Pos      (31U)
+#define EXTI_SECCFGR2_SEC63_Msk      (0x1UL << EXTI_SECCFGR2_SEC63_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR2_SEC63          EXTI_SECCFGR2_SEC63_Msk                   /*!< Security enable on line 63 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR2 register  ******************/
+#define EXTI_PRIVCFGR2_PRIV32_Pos    (0U)
+#define EXTI_PRIVCFGR2_PRIV32_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR2_PRIV32        EXTI_PRIVCFGR2_PRIV32_Msk                 /*!< Privilege enable on line 32 */
+#define EXTI_PRIVCFGR2_PRIV33_Pos    (1U)
+#define EXTI_PRIVCFGR2_PRIV33_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR2_PRIV33        EXTI_PRIVCFGR2_PRIV33_Msk                 /*!< Privilege enable on line 33 */
+#define EXTI_PRIVCFGR2_PRIV34_Pos    (2U)
+#define EXTI_PRIVCFGR2_PRIV34_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR2_PRIV34        EXTI_PRIVCFGR2_PRIV34_Msk                 /*!< Privilege enable on line 34 */
+#define EXTI_PRIVCFGR2_PRIV35_Pos    (3U)
+#define EXTI_PRIVCFGR2_PRIV35_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos)      /*!< 0x00000008 */
+#define EXTI_PRIVCFGR2_PRIV35        EXTI_PRIVCFGR2_PRIV35_Msk                 /*!< Privilege enable on line 35 */
+#define EXTI_PRIVCFGR2_PRIV36_Pos    (4U)
+#define EXTI_PRIVCFGR2_PRIV36_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR2_PRIV36        EXTI_PRIVCFGR2_PRIV36_Msk                 /*!< Privilege enable on line 36 */
+#define EXTI_PRIVCFGR2_PRIV37_Pos    (5U)
+#define EXTI_PRIVCFGR2_PRIV37_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR2_PRIV37        EXTI_PRIVCFGR2_PRIV37_Msk                 /*!< Privilege enable on line 37 */
+#define EXTI_PRIVCFGR2_PRIV38_Pos    (6U)
+#define EXTI_PRIVCFGR2_PRIV38_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR2_PRIV38        EXTI_PRIVCFGR2_PRIV38_Msk                 /*!< Privilege enable on line 38 */
+#define EXTI_PRIVCFGR2_PRIV39_Pos    (7U)
+#define EXTI_PRIVCFGR2_PRIV39_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR2_PRIV39        EXTI_PRIVCFGR2_PRIV39_Msk                 /*!< Privilege enable on line 39 */
+#define EXTI_PRIVCFGR2_PRIV40_Pos    (8U)
+#define EXTI_PRIVCFGR2_PRIV40_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV40_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR2_PRIV40        EXTI_PRIVCFGR2_PRIV40_Msk                 /*!< Privilege enable on line 40 */
+#define EXTI_PRIVCFGR2_PRIV41_Pos    (9U)
+#define EXTI_PRIVCFGR2_PRIV41_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV41_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR2_PRIV41        EXTI_PRIVCFGR2_PRIV41_Msk                 /*!< Privilege enable on line 41 */
+#define EXTI_PRIVCFGR2_PRIV42_Pos    (10U)
+#define EXTI_PRIVCFGR2_PRIV42_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV42_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR2_PRIV42        EXTI_PRIVCFGR2_PRIV42_Msk                 /*!< Privilege enable on line 42 */
+#define EXTI_PRIVCFGR2_PRIV43_Pos    (11U)
+#define EXTI_PRIVCFGR2_PRIV43_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV43_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR2_PRIV43        EXTI_PRIVCFGR2_PRIV43_Msk                 /*!< Privilege enable on line 43 */
+#define EXTI_PRIVCFGR2_PRIV44_Pos    (12U)
+#define EXTI_PRIVCFGR2_PRIV44_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV44_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR2_PRIV44        EXTI_PRIVCFGR2_PRIV44_Msk                 /*!< Privilege enable on line 44 */
+#define EXTI_PRIVCFGR2_PRIV45_Pos    (13U)
+#define EXTI_PRIVCFGR2_PRIV45_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV45_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR2_PRIV45        EXTI_PRIVCFGR2_PRIV45                     /*!< Privilege enable on line 45 */
+#define EXTI_PRIVCFGR2_PRIV46_Pos    (14U)
+#define EXTI_PRIVCFGR2_PRIV46_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV46_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR2_PRIV46        EXTI_PRIVCFGR2_PRIV46_Msk                 /*!< Privilege enable on line 46 */
+#define EXTI_PRIVCFGR2_PRIV47_Pos    (15U)
+#define EXTI_PRIVCFGR2_PRIV47_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV47_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR2_PRIV47        EXTI_PRIVCFGR2_PRIV47_Msk                 /*!< Privilege enable on line 47 */
+#define EXTI_PRIVCFGR2_PRIV48_Pos    (16U)
+#define EXTI_PRIVCFGR2_PRIV48_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV48_Pos)      /*!< 0x00010000 */
+#define EXTI_PRIVCFGR2_PRIV48        EXTI_PRIVCFGR2_PRIV48_Msk                 /*!< Privilege enable on line 48 */
+#define EXTI_PRIVCFGR2_PRIV49_Pos    (17U)
+#define EXTI_PRIVCFGR2_PRIV49_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV49_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR2_PRIV49        EXTI_PRIVCFGR2_PRIV49_Msk                 /*!< Privilege enable on line 49 */
+#define EXTI_PRIVCFGR2_PRIV50_Pos    (18U)
+#define EXTI_PRIVCFGR2_PRIV50_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV50_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR2_PRIV50        EXTI_PRIVCFGR2_PRIV50_Msk                 /*!< Privilege enable on line 50 */
+#define EXTI_PRIVCFGR2_PRIV51_Pos    (19U)
+#define EXTI_PRIVCFGR2_PRIV51_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV51_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR2_PRIV51        EXTI_PRIVCFGR2_PRIV51_Msk                 /*!< Privilege enable on line 51 */
+#define EXTI_PRIVCFGR2_PRIV52_Pos    (20U)
+#define EXTI_PRIVCFGR2_PRIV52_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV52_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR2_PRIV52        EXTI_PRIVCFGR2_PRIV52_Msk                 /*!< Privilege enable on line 52 */
+#define EXTI_PRIVCFGR2_PRIV53_Pos    (21U)
+#define EXTI_PRIVCFGR2_PRIV53_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV53_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR2_PRIV53        EXTI_PRIVCFGR2_PRIV53_Msk                 /*!< Privilege enable on line 53 */
+#define EXTI_PRIVCFGR2_PRIV54_Pos    (22U)
+#define EXTI_PRIVCFGR2_PRIV54_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV54_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR2_PRIV54        EXTI_PRIVCFGR2_PRIV54_Msk                 /*!< Privilege enable on line 54 */
+#define EXTI_PRIVCFGR2_PRIV55_Pos    (23U)
+#define EXTI_PRIVCFGR2_PRIV55_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV55_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR2_PRIV55        EXTI_PRIVCFGR2_PRIV55_Msk                 /*!< Privilege enable on line 55 */
+#define EXTI_PRIVCFGR2_PRIV56_Pos    (24U)
+#define EXTI_PRIVCFGR2_PRIV56_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV56_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR2_PRIV56        EXTI_PRIVCFGR2_PRIV56_Msk                 /*!< Privilege enable on line 56 */
+#define EXTI_PRIVCFGR2_PRIV57_Pos    (25U)
+#define EXTI_PRIVCFGR2_PRIV57_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV57_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR2_PRIV57        EXTI_PRIVCFGR2_PRIV57_Msk                 /*!< Privilege enable on line 57 */
+#define EXTI_PRIVCFGR2_PRIV58_Pos    (26U)
+#define EXTI_PRIVCFGR2_PRIV58_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV58_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR2_PRIV58        EXTI_PRIVCFGR2_PRIV58_Msk                 /*!< Privilege enable on line 58 */
+#define EXTI_PRIVCFGR2_PRIV60_Pos    (28U)
+#define EXTI_PRIVCFGR2_PRIV60_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV60_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR2_PRIV60        EXTI_PRIVCFGR2_PRIV60_Msk                 /*!< Privilege enable on line 60 */
+#define EXTI_PRIVCFGR2_PRIV61_Pos    (29U)
+#define EXTI_PRIVCFGR2_PRIV61_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV61_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR2_PRIV61        EXTI_PRIVCFGR2_PRIV61_Msk                 /*!< Privilege enable on line 61 */
+#define EXTI_PRIVCFGR2_PRIV62_Pos    (30U)
+#define EXTI_PRIVCFGR2_PRIV62_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV62_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR2_PRIV62        EXTI_PRIVCFGR2_PRIV62_Msk                 /*!< Privilege enable on line 62 */
+#define EXTI_PRIVCFGR2_PRIV63_Pos    (31U)
+#define EXTI_PRIVCFGR2_PRIV63_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV63_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR2_PRIV63        EXTI_PRIVCFGR2_PRIV63_Msk                 /*!< Privilege enable on line 63 */
+
+/*******************  Bit definition for EXTI_RTSR3 register  *****************/
+#define EXTI_RTSR3_RT66_Pos          (2U)
+#define EXTI_RTSR3_RT66_Msk          (0x1UL << EXTI_RTSR3_RT66_Pos)            /*!< 0x00000004 */
+#define EXTI_RTSR3_RT66              EXTI_RTSR3_RT66_Msk                       /*!< Rising trigger configuration for input line 66 */
+#define EXTI_RTSR3_RT68_Pos          (4U)
+#define EXTI_RTSR3_RT68_Msk          (0x1UL << EXTI_RTSR3_RT68_Pos)            /*!< 0x00000010 */
+#define EXTI_RTSR3_RT68              EXTI_RTSR3_RT68_Msk                       /*!< Rising trigger configuration for input line 68 */
+#define EXTI_RTSR3_RT69_Pos          (5U)
+#define EXTI_RTSR3_RT69_Msk          (0x1UL << EXTI_RTSR3_RT69_Pos)            /*!< 0x00000020 */
+#define EXTI_RTSR3_RT69              EXTI_RTSR3_RT69_Msk                       /*!< Rising trigger configuration for input line 69 */
+#define EXTI_RTSR3_RT70_Pos          (6U)
+#define EXTI_RTSR3_RT70_Msk          (0x1UL << EXTI_RTSR3_RT70_Pos)            /*!< 0x00000040 */
+#define EXTI_RTSR3_RT70              EXTI_RTSR3_RT70_Msk                       /*!< Rising trigger configuration for input line 70 */
+#define EXTI_RTSR3_RT71_Pos          (7U)
+#define EXTI_RTSR3_RT71_Msk          (0x1UL << EXTI_RTSR3_RT71_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR3_RT71              EXTI_RTSR3_RT71_Msk                       /*!< Rising trigger configuration for input line 71 */
+#define EXTI_RTSR3_RT72_Pos          (8U)
+#define EXTI_RTSR3_RT72_Msk          (0x1UL << EXTI_RTSR3_RT72_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR3_RT72              EXTI_RTSR3_RT72_Msk                       /*!< Rising trigger configuration for input line 72 */
+#define EXTI_RTSR3_RT73_Pos          (9U)
+#define EXTI_RTSR3_RT73_Msk          (0x1UL << EXTI_RTSR3_RT73_Pos)            /*!< 0x00000200 */
+#define EXTI_RTSR3_RT73              EXTI_RTSR3_RT73_Msk                       /*!< Rising trigger configuration for input line 73 */
+#define EXTI_RTSR3_RT74_Pos          (10U)
+#define EXTI_RTSR3_RT74_Msk          (0x1UL << EXTI_RTSR3_RT74_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR3_RT74              EXTI_RTSR3_RT74_Msk                       /*!< Rising trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_FTSR3 register  *****************/
+#define EXTI_FTSR3_FT66_Pos          (2U)
+#define EXTI_FTSR3_FT66_Msk          (0x1UL << EXTI_FTSR3_FT66_Pos)            /*!< 0x00000004 */
+#define EXTI_FTSR3_FT66              EXTI_FTSR3_FT66_Msk                       /*!< Falling trigger configuration for input line 66 */
+#define EXTI_FTSR3_FT68_Pos          (4U)
+#define EXTI_FTSR3_FT68_Msk          (0x1UL << EXTI_FTSR3_FT68_Pos)            /*!< 0x00000010 */
+#define EXTI_FTSR3_FT68              EXTI_FTSR3_FT68_Msk                       /*!< Falling trigger configuration for input line 68 */
+#define EXTI_FTSR3_FT69_Pos          (5U)
+#define EXTI_FTSR3_FT69_Msk          (0x1UL << EXTI_FTSR3_FT69_Pos)            /*!< 0x00000020 */
+#define EXTI_FTSR3_FT69              EXTI_FTSR3_FT69_Msk                       /*!< Falling trigger configuration for input line 69 */
+#define EXTI_FTSR3_FT70_Pos          (6U)
+#define EXTI_FTSR3_FT70_Msk          (0x1UL << EXTI_FTSR3_FT70_Pos)            /*!< 0x00000040 */
+#define EXTI_FTSR3_FT70              EXTI_FTSR3_FT70_Msk                       /*!< Falling trigger configuration for input line 70 */
+#define EXTI_FTSR3_FT71_Pos          (7U)
+#define EXTI_FTSR3_FT71_Msk          (0x1UL << EXTI_FTSR3_FT71_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR3_FT71              EXTI_FTSR3_FT71_Msk                       /*!< Falling trigger configuration for input line 71 */
+#define EXTI_FTSR3_FT72_Pos          (8U)
+#define EXTI_FTSR3_FT72_Msk          (0x1UL << EXTI_FTSR3_FT72_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR3_FT72              EXTI_FTSR3_FT72_Msk                       /*!< Falling trigger configuration for input line 72 */
+#define EXTI_FTSR3_FT73_Pos          (9U)
+#define EXTI_FTSR3_FT73_Msk          (0x1UL << EXTI_FTSR3_FT73_Pos)            /*!< 0x00000200 */
+#define EXTI_FTSR3_FT73              EXTI_FTSR3_FT73_Msk                       /*!< Falling trigger configuration for input line 73 */
+#define EXTI_FTSR3_FT74_Pos          (10U)
+#define EXTI_FTSR3_FT74_Msk          (0x1UL << EXTI_FTSR3_FT74_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR3_FT74              EXTI_FTSR3_FT74_Msk                       /*!< Falling trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_SWIER3 register  ****************/
+#define EXTI_SWIER3_SWI66_Pos        (2U)
+#define EXTI_SWIER3_SWI66_Msk        (0x1UL << EXTI_SWIER3_SWI66_Pos)          /*!< 0x00000004 */
+#define EXTI_SWIER3_SWI66            EXTI_SWIER3_SWI66_Msk                     /*!< Software Interrupt on line 66 */
+#define EXTI_SWIER3_SWI68_Pos        (4U)
+#define EXTI_SWIER3_SWI68_Msk        (0x1UL << EXTI_SWIER3_SWI68_Pos)          /*!< 0x00000010 */
+#define EXTI_SWIER3_SWI68            EXTI_SWIER3_SWI68_Msk                     /*!< Software Interrupt on line 68 */
+#define EXTI_SWIER3_SWI69_Pos        (5U)
+#define EXTI_SWIER3_SWI69_Msk        (0x1UL << EXTI_SWIER3_SWI69_Pos)          /*!< 0x00000020 */
+#define EXTI_SWIER3_SWI69            EXTI_SWIER3_SWI69_Msk                     /*!< Software Interrupt on line 69 */
+#define EXTI_SWIER3_SWI70_Pos        (6U)
+#define EXTI_SWIER3_SWI70_Msk        (0x1UL << EXTI_SWIER3_SWI70_Pos)          /*!< 0x00000040 */
+#define EXTI_SWIER3_SWI70            EXTI_SWIER3_SWI70_Msk                     /*!< Software Interrupt on line 70 */
+#define EXTI_SWIER3_SWI71_Pos        (7U)
+#define EXTI_SWIER3_SWI71_Msk        (0x1UL << EXTI_SWIER3_SWI71_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER3_SWI71            EXTI_SWIER3_SWI71_Msk                     /*!< Software Interrupt on line 71 */
+#define EXTI_SWIER3_SWI72_Pos        (8U)
+#define EXTI_SWIER3_SWI72_Msk        (0x1UL << EXTI_SWIER3_SWI72_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER3_SWI72            EXTI_SWIER3_SWI72_Msk                     /*!< Software Interrupt on line 72 */
+#define EXTI_SWIER3_SWI73_Pos        (9U)
+#define EXTI_SWIER3_SWI73_Msk        (0x1UL << EXTI_SWIER3_SWI73_Pos)          /*!< 0x00000200 */
+#define EXTI_SWIER3_SWI73            EXTI_SWIER3_SWI73_Msk                     /*!< Software Interrupt on line 73 */
+#define EXTI_SWIER3_SWI74_Pos        (10U)
+#define EXTI_SWIER3_SWI74_Msk        (0x1UL << EXTI_SWIER3_SWI74_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER3_SWI74            EXTI_SWIER3_SWI74_Msk                     /*!< Software Interrupt on line 74 */
+
+/*******************  Bit definition for EXTI_RPR3 register  ******************/
+#define EXTI_RPR3_RPIF66_Pos         (2U)
+#define EXTI_RPR3_RPIF66_Msk         (0x1UL << EXTI_RPR3_RPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_RPR3_RPIF66             EXTI_RPR3_RPIF66_Msk                      /*!< Rising Pending Interrupt Flag on line 66 */
+#define EXTI_RPR3_RPIF68_Pos         (4U)
+#define EXTI_RPR3_RPIF68_Msk         (0x1UL << EXTI_RPR3_RPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_RPR3_RPIF68             EXTI_RPR3_RPIF68_Msk                      /*!< Rising Pending Interrupt Flag on line 68 */
+#define EXTI_RPR3_RPIF69_Pos         (5U)
+#define EXTI_RPR3_RPIF69_Msk         (0x1UL << EXTI_RPR3_RPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_RPR3_RPIF69             EXTI_RPR3_RPIF69_Msk                      /*!< Rising Pending Interrupt Flag on line 69 */
+#define EXTI_RPR3_RPIF70_Pos         (6U)
+#define EXTI_RPR3_RPIF70_Msk         (0x1UL << EXTI_RPR3_RPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_RPR3_RPIF70             EXTI_RPR3_RPIF70_Msk                      /*!< Rising Pending Interrupt Flag on line 70 */
+#define EXTI_RPR3_RPIF71_Pos         (7U)
+#define EXTI_RPR3_RPIF71_Msk         (0x1UL << EXTI_RPR3_RPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR3_RPIF71             EXTI_RPR3_RPIF71_Msk                      /*!< Rising Pending Interrupt Flag on line 71 */
+#define EXTI_RPR3_RPIF72_Pos         (8U)
+#define EXTI_RPR3_RPIF72_Msk         (0x1UL << EXTI_RPR3_RPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR3_RPIF72             EXTI_RPR3_RPIF72_Msk                      /*!< Rising Pending Interrupt Flag on line 72 */
+#define EXTI_RPR3_RPIF73_Pos         (9U)
+#define EXTI_RPR3_RPIF73_Msk         (0x1UL << EXTI_RPR3_RPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_RPR3_RPIF73             EXTI_RPR3_RPIF73_Msk                      /*!< Rising Pending Interrupt Flag on line 73 */
+#define EXTI_RPR3_RPIF74_Pos         (10U)
+#define EXTI_RPR3_RPIF74_Msk         (0x1UL << EXTI_RPR3_RPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR3_RPIF74             EXTI_RPR3_RPIF74_Msk                      /*!< Rising Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_FPR3 register  ******************/
+#define EXTI_FPR3_FPIF66_Pos         (2U)
+#define EXTI_FPR3_FPIF66_Msk         (0x1UL << EXTI_FPR3_FPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_FPR3_FPIF66             EXTI_FPR3_FPIF66_Msk                      /*!< Falling Pending Interrupt Flag on line 66 */
+#define EXTI_FPR3_FPIF68_Pos         (4U)
+#define EXTI_FPR3_FPIF68_Msk         (0x1UL << EXTI_FPR3_FPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_FPR3_FPIF68             EXTI_FPR3_FPIF68_Msk                      /*!< Falling Pending Interrupt Flag on line 68 */
+#define EXTI_FPR3_FPIF69_Pos         (5U)
+#define EXTI_FPR3_FPIF69_Msk         (0x1UL << EXTI_FPR3_FPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_FPR3_FPIF69             EXTI_FPR3_FPIF69_Msk                      /*!< Falling Pending Interrupt Flag online  69 */
+#define EXTI_FPR3_FPIF70_Pos         (6U)
+#define EXTI_FPR3_FPIF70_Msk         (0x1UL << EXTI_FPR3_FPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_FPR3_FPIF70             EXTI_FPR3_FPIF70_Msk                      /*!< Falling Pending Interrupt Flag on line 70 */
+#define EXTI_FPR3_FPIF71_Pos         (7U)
+#define EXTI_FPR3_FPIF71_Msk         (0x1UL << EXTI_FPR3_FPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR3_FPIF71             EXTI_FPR3_FPIF71_Msk                      /*!< Falling Pending Interrupt Flag on line 71 */
+#define EXTI_FPR3_FPIF72_Pos         (8U)
+#define EXTI_FPR3_FPIF72_Msk         (0x1UL << EXTI_FPR3_FPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR3_FPIF72             EXTI_FPR3_FPIF72_Msk                      /*!< Falling Pending Interrupt Flag on line 72 */
+#define EXTI_FPR3_FPIF73_Pos         (9U)
+#define EXTI_FPR3_FPIF73_Msk         (0x1UL << EXTI_FPR3_FPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_FPR3_FPIF73             EXTI_FPR3_FPIF73_Msk                      /*!< Falling Pending Interrupt Flag on line 73 */
+#define EXTI_FPR3_FPIF74_Pos         (10U)
+#define EXTI_FPR3_FPIF74_Msk         (0x1UL << EXTI_FPR3_FPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR3_FPIF74             EXTI_FPR3_FPIF74_Msk                      /*!< Falling Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_SECCFGR3 register  ******************/
+#define EXTI_SECCFGR3_SEC64_Pos      (0U)
+#define EXTI_SECCFGR3_SEC64_Msk      (0x1UL << EXTI_SECCFGR3_SEC64_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR3_SEC64          EXTI_SECCFGR3_SEC64_Msk                   /*!< Security enable on line 64 */
+#define EXTI_SECCFGR3_SEC65_Pos      (1U)
+#define EXTI_SECCFGR3_SEC65_Msk      (0x1UL << EXTI_SECCFGR3_SEC65_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR3_SEC65          EXTI_SECCFGR3_SEC65_Msk                   /*!< Security enable on line 65 */
+#define EXTI_SECCFGR3_SEC66_Pos      (2U)
+#define EXTI_SECCFGR3_SEC66_Msk      (0x1UL << EXTI_SECCFGR3_SEC66_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR3_SEC66          EXTI_SECCFGR3_SEC66_Msk                   /*!< Security enable on line 66  */
+#define EXTI_SECCFGR3_SEC68_Pos      (4U)
+#define EXTI_SECCFGR3_SEC68_Msk      (0x1UL << EXTI_SECCFGR3_SEC68_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR3_SEC68          EXTI_SECCFGR3_SEC68_Msk                   /*!< Security enable on line 68 */
+#define EXTI_SECCFGR3_SEC69_Pos      (5U)
+#define EXTI_SECCFGR3_SEC69_Msk      (0x1UL << EXTI_SECCFGR3_SEC69_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR3_SEC69          EXTI_SECCFGR3_SEC69_Msk                   /*!< Security enable on line 69 */
+#define EXTI_SECCFGR3_SEC70_Pos      (6U)
+#define EXTI_SECCFGR3_SEC70_Msk      (0x1UL << EXTI_SECCFGR3_SEC70_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR3_SEC70          EXTI_SECCFGR3_SEC70_Msk                   /*!< Security enable on line 70 */
+#define EXTI_SECCFGR3_SEC71_Pos      (7U)
+#define EXTI_SECCFGR3_SEC71_Msk      (0x1UL << EXTI_SECCFGR3_SEC71_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR3_SEC71          EXTI_SECCFGR3_SEC71_Msk                   /*!< Security enable on line 71 */
+#define EXTI_SECCFGR3_SEC72_Pos      (8U)
+#define EXTI_SECCFGR3_SEC72_Msk      (0x1UL << EXTI_SECCFGR3_SEC72_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR3_SEC72          EXTI_SECCFGR3_SEC72_Msk                   /*!< Security enable on line 72 */
+#define EXTI_SECCFGR3_SEC73_Pos      (9U)
+#define EXTI_SECCFGR3_SEC73_Msk      (0x1UL << EXTI_SECCFGR3_SEC73_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR3_SEC73          EXTI_SECCFGR3_SEC73_Msk                   /*!< Security enable on line 73 */
+#define EXTI_SECCFGR3_SEC74_Pos      (10U)
+#define EXTI_SECCFGR3_SEC74_Msk      (0x1UL << EXTI_SECCFGR3_SEC74_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR3_SEC74          EXTI_SECCFGR3_SEC74_Msk                   /*!< Security enable on line 74 */
+#define EXTI_SECCFGR3_SEC77_Pos      (13U)
+#define EXTI_SECCFGR3_SEC77_Msk      (0x1UL << EXTI_SECCFGR3_SEC77_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR3_SEC77          EXTI_SECCFGR3_SEC77_Msk                   /*!< Security enable on line 77 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR3 register  ******************/
+#define EXTI_PRIVCFGR3_PRIV64_Pos    (0U)
+#define EXTI_PRIVCFGR3_PRIV64_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV64_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR3_PRIV64        EXTI_PRIVCFGR3_PRIV64_Msk                 /*!< Privilege enable on line 64 */
+#define EXTI_PRIVCFGR3_PRIV65_Pos    (1U)
+#define EXTI_PRIVCFGR3_PRIV65_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV65_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR3_PRIV65        EXTI_PRIVCFGR3_PRIV65_Msk                 /*!< Privilege enable on line 65 */
+#define EXTI_PRIVCFGR3_PRIV66_Pos    (2U)
+#define EXTI_PRIVCFGR3_PRIV66_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV66_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR3_PRIV66        EXTI_PRIVCFGR3_PRIV66_Msk                 /*!< Privilege enable on line 66  */
+#define EXTI_PRIVCFGR3_PRIV68_Pos    (4U)
+#define EXTI_PRIVCFGR3_PRIV68_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV68_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR3_PRIV68        EXTI_PRIVCFGR3_PRIV68_Msk                 /*!< Privilege enable on line 68 */
+#define EXTI_PRIVCFGR3_PRIV69_Pos    (5U)
+#define EXTI_PRIVCFGR3_PRIV69_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV69_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR3_PRIV69        EXTI_PRIVCFGR3_PRIV69_Msk                 /*!< Privilege enable on line 69 */
+#define EXTI_PRIVCFGR3_PRIV70_Pos    (6U)
+#define EXTI_PRIVCFGR3_PRIV70_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV70_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR3_PRIV70        EXTI_PRIVCFGR3_PRIV70_Msk                 /*!< Privilege enable on line 70 */
+#define EXTI_PRIVCFGR3_PRIV71_Pos    (7U)
+#define EXTI_PRIVCFGR3_PRIV71_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV71_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR3_PRIV71        EXTI_PRIVCFGR3_PRIV71_Msk                 /*!< Privilege enable on line 71 */
+#define EXTI_PRIVCFGR3_PRIV72_Pos    (8U)
+#define EXTI_PRIVCFGR3_PRIV72_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV72_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR3_PRIV72        EXTI_PRIVCFGR3_PRIV72_Msk                 /*!< Privilege enable on line 72 */
+#define EXTI_PRIVCFGR3_PRIV73_Pos    (9U)
+#define EXTI_PRIVCFGR3_PRIV73_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV73_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR3_PRIV73        EXTI_PRIVCFGR3_PRIV73_Msk                 /*!< Privilege enable on line 73 */
+#define EXTI_PRIVCFGR3_PRIV74_Pos    (10U)
+#define EXTI_PRIVCFGR3_PRIV74_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV74_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR3_PRIV74        EXTI_PRIVCFGR3_PRIV74_Msk                 /*!< Privilege enable on line 74 */
+#define EXTI_PRIVCFGR3_PRIV77_Pos    (13U)
+#define EXTI_PRIVCFGR3_PRIV77_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV77_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR3_PRIV77        EXTI_PRIVCFGR3_PRIV77_Msk                 /*!< Privilege enable on line 77 */
+
+/*****************  Bit definition for EXTI_EXTICR1 register  **************/
+#define EXTI_EXTICR1_EXTI0_Pos       (0U)
+#define EXTI_EXTICR1_EXTI0_Msk       (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
+#define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR1_EXTI0_3         (0x8UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR1_EXTI0_4         (0x10UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR1_EXTI0_5         (0x20UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR1_EXTI0_6         (0x40UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR1_EXTI0_7         (0x80UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR1_EXTI1_Pos       (8U)
+#define EXTI_EXTICR1_EXTI1_Msk       (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
+#define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR1_EXTI1_3         (0x8UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR1_EXTI1_4         (0x10UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR1_EXTI1_5         (0x20UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR1_EXTI1_6         (0x40UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR1_EXTI1_7         (0x80UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR1_EXTI2_Pos       (16U)
+#define EXTI_EXTICR1_EXTI2_Msk       (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
+#define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR1_EXTI2_3         (0x8UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR1_EXTI2_4         (0x10UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR1_EXTI2_5         (0x20UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR1_EXTI2_6         (0x40UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR1_EXTI2_7         (0x80UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR1_EXTI3_Pos       (24U)
+#define EXTI_EXTICR1_EXTI3_Msk       (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
+#define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR1_EXTI3_3         (0x8UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR1_EXTI3_4         (0x10UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR1_EXTI3_5         (0x20UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR1_EXTI3_6         (0x40UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR1_EXTI3_7         (0x80UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR2 register  **************/
+#define EXTI_EXTICR2_EXTI4_Pos       (0U)
+#define EXTI_EXTICR2_EXTI4_Msk       (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
+#define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR2_EXTI4_3         (0x8UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR2_EXTI4_4         (0x10UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR2_EXTI4_5         (0x20UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR2_EXTI4_6         (0x40UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR2_EXTI4_7         (0x80UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR2_EXTI5_Pos       (8U)
+#define EXTI_EXTICR2_EXTI5_Msk       (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
+#define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR2_EXTI5_3         (0x8UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR2_EXTI5_4         (0x10UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR2_EXTI5_5         (0x20UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR2_EXTI5_6         (0x40UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR2_EXTI5_7         (0x80UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR2_EXTI6_Pos       (16U)
+#define EXTI_EXTICR2_EXTI6_Msk       (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
+#define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR2_EXTI6_3         (0x8UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR2_EXTI6_4         (0x10UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR2_EXTI6_5         (0x20UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR2_EXTI6_6         (0x40UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR2_EXTI6_7         (0x80UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR2_EXTI7_Pos       (24U)
+#define EXTI_EXTICR2_EXTI7_Msk       (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
+#define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR2_EXTI7_3         (0x8UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR2_EXTI7_4         (0x10UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR2_EXTI7_5         (0x20UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR2_EXTI7_6         (0x40UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR2_EXTI7_7         (0x80UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR3 register  **************/
+#define EXTI_EXTICR3_EXTI8_Pos       (0U)
+#define EXTI_EXTICR3_EXTI8_Msk       (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
+#define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR3_EXTI8_3         (0x8UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR3_EXTI8_4         (0x10UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR3_EXTI8_5         (0x20UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR3_EXTI8_6         (0x40UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR3_EXTI8_7         (0x80UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR3_EXTI9_Pos       (8U)
+#define EXTI_EXTICR3_EXTI9_Msk       (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
+#define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR3_EXTI9_3         (0x8UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR3_EXTI9_4         (0x10UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR3_EXTI9_5         (0x20UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR3_EXTI9_6         (0x40UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR3_EXTI9_7         (0x80UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR3_EXTI10_Pos      (16U)
+#define EXTI_EXTICR3_EXTI10_Msk      (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
+#define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR3_EXTI10_3        (0x8UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR3_EXTI10_4        (0x10UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR3_EXTI10_5        (0x20UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR3_EXTI10_6        (0x40UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR3_EXTI10_7        (0x80UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR3_EXTI11_Pos      (24U)
+#define EXTI_EXTICR3_EXTI11_Msk      (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
+#define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR3_EXTI11_3        (0x8UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR3_EXTI11_4        (0x10UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR3_EXTI11_5        (0x20UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR3_EXTI11_6        (0x40UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR3_EXTI11_7        (0x80UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR4 register  **************/
+#define EXTI_EXTICR4_EXTI12_Pos      (0U)
+#define EXTI_EXTICR4_EXTI12_Msk      (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x000000FF */
+#define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
+#define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
+#define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
+#define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
+#define EXTI_EXTICR4_EXTI12_3        (0x8UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000008 */
+#define EXTI_EXTICR4_EXTI12_4        (0x10UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000010 */
+#define EXTI_EXTICR4_EXTI12_5        (0x20UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000020 */
+#define EXTI_EXTICR4_EXTI12_6        (0x40UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000040 */
+#define EXTI_EXTICR4_EXTI12_7        (0x80UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000080 */
+#define EXTI_EXTICR4_EXTI13_Pos      (8U)
+#define EXTI_EXTICR4_EXTI13_Msk      (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x0000FF00 */
+#define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
+#define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
+#define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000200 */
+#define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000400 */
+#define EXTI_EXTICR4_EXTI13_3        (0x8UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000800 */
+#define EXTI_EXTICR4_EXTI13_4        (0x10UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00001000 */
+#define EXTI_EXTICR4_EXTI13_5        (0x20UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00002000 */
+#define EXTI_EXTICR4_EXTI13_6        (0x40UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00004000 */
+#define EXTI_EXTICR4_EXTI13_7        (0x80UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00008000 */
+#define EXTI_EXTICR4_EXTI14_Pos      (16U)
+#define EXTI_EXTICR4_EXTI14_Msk      (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
+#define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR4_EXTI14_3        (0x8UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR4_EXTI14_4        (0x10UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR4_EXTI14_5        (0x20UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR4_EXTI14_6        (0x40UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR4_EXTI14_7        (0x80UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR4_EXTI15_Pos      (24U)
+#define EXTI_EXTICR4_EXTI15_Msk      (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
+#define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR4_EXTI15_3        (0x8UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR4_EXTI15_4        (0x10UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR4_EXTI15_5        (0x20UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR4_EXTI15_6        (0x40UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR4_EXTI15_7        (0x80UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x80000000 */
+
+/*******************  Bit definition I_LOCKR register  ******************/
+#define EXTI_LOCKR_LOCK_Pos          (0U)
+#define EXTI_LOCKR_LOCK_Msk          (0x1UL << EXTI_LOCKR_LOCK_Pos)            /*!< 0x00000001 */
+#define EXTI_LOCKR_LOCK              EXTI_LOCKR_LOCK_Msk                       /*!< Security and privilege configuration lock */
+
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos            (0U)
+#define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
+#define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos            (1U)
+#define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
+#define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos            (2U)
+#define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
+#define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos            (3U)
+#define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
+#define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos            (4U)
+#define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
+#define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos            (5U)
+#define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
+#define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos            (6U)
+#define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
+#define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos            (7U)
+#define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
+#define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos            (8U)
+#define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
+#define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos            (9U)
+#define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
+#define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos           (10U)
+#define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos           (11U)
+#define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos           (12U)
+#define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos           (13U)
+#define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos           (14U)
+#define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos           (15U)
+#define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM17_Pos           (17U)
+#define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos           (18U)
+#define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos           (19U)
+#define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos           (20U)
+#define EXTI_IMR1_IM20_Msk           (0x1UL << EXTI_IMR1_IM20_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR1_IM20               EXTI_IMR1_IM20_Msk                        /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos           (21U)
+#define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos           (22U)
+#define EXTI_IMR1_IM22_Msk           (0x1UL << EXTI_IMR1_IM22_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR1_IM22               EXTI_IMR1_IM22_Msk                        /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos           (23U)
+#define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos           (24U)
+#define EXTI_IMR1_IM24_Msk           (0x1UL << EXTI_IMR1_IM24_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR1_IM24               EXTI_IMR1_IM24_Msk                        /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos           (25U)
+#define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos           (26U)
+#define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos           (27U)
+#define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */
+#define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos           (28U)
+#define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos           (29U)
+#define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos           (30U)
+#define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos           (31U)
+#define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos             (0U)
+#define EXTI_IMR1_IM_Msk             (0xFFFEFFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos            (0U)
+#define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
+#define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos            (1U)
+#define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
+#define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos            (2U)
+#define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
+#define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos            (3U)
+#define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
+#define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos            (4U)
+#define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
+#define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos            (5U)
+#define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
+#define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos            (6U)
+#define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
+#define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos            (7U)
+#define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
+#define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos            (8U)
+#define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
+#define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos            (9U)
+#define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
+#define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos           (10U)
+#define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos           (11U)
+#define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos           (12U)
+#define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos           (13U)
+#define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos           (14U)
+#define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos           (15U)
+#define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM17_Pos           (17U)
+#define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos           (18U)
+#define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos           (19U)
+#define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos           (20U)
+#define EXTI_EMR1_EM20_Msk           (0x1UL << EXTI_EMR1_EM20_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR1_EM20               EXTI_EMR1_EM20_Msk                        /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos           (21U)
+#define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos           (22U)
+#define EXTI_EMR1_EM22_Msk           (0x1UL << EXTI_EMR1_EM22_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR1_EM22               EXTI_EMR1_EM22_Msk                        /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos           (23U)
+#define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos           (24U)
+#define EXTI_EMR1_EM24_Msk           (0x1UL << EXTI_EMR1_EM24_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR1_EM24               EXTI_EMR1_EM24_Msk                        /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos           (25U)
+#define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos           (26U)
+#define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos           (27U)
+#define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */
+#define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos           (28U)
+#define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos           (29U)
+#define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos           (30U)
+#define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos           (31U)
+#define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */
+#define EXTI_EMR1_EM_Pos             (0U)
+#define EXTI_EMR1_EM_Msk             (0xFFFEFFFFUL << EXTI_EMR1_EM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_EMR1_EM                 EXTI_EMR1_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos           (0U)
+#define EXTI_IMR2_IM32_Msk           (0x1UL << EXTI_IMR2_IM32_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR2_IM32               EXTI_IMR2_IM32_Msk                        /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos           (1U)
+#define EXTI_IMR2_IM33_Msk           (0x1UL << EXTI_IMR2_IM33_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR2_IM33               EXTI_IMR2_IM33_Msk                        /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos           (2U)
+#define EXTI_IMR2_IM34_Msk           (0x1UL << EXTI_IMR2_IM34_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR2_IM34               EXTI_IMR2_IM34_Msk                        /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos           (3U)
+#define EXTI_IMR2_IM35_Msk           (0x1UL << EXTI_IMR2_IM35_Pos)             /*!< 0x00000008 */
+#define EXTI_IMR2_IM35               EXTI_IMR2_IM35_Msk                        /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos           (4U)
+#define EXTI_IMR2_IM36_Msk           (0x1UL << EXTI_IMR2_IM36_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR2_IM36               EXTI_IMR2_IM36_Msk                        /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos           (5U)
+#define EXTI_IMR2_IM37_Msk           (0x1UL << EXTI_IMR2_IM37_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR2_IM37               EXTI_IMR2_IM37_Msk                        /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos           (6U)
+#define EXTI_IMR2_IM38_Msk           (0x1UL << EXTI_IMR2_IM38_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR2_IM38               EXTI_IMR2_IM38_Msk                        /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos           (7U)
+#define EXTI_IMR2_IM39_Msk           (0x1UL << EXTI_IMR2_IM39_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR2_IM39               EXTI_IMR2_IM39_Msk                        /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos           (8U)
+#define EXTI_IMR2_IM40_Msk           (0x1UL << EXTI_IMR2_IM40_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR2_IM40               EXTI_IMR2_IM40_Msk                        /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos           (9U)
+#define EXTI_IMR2_IM41_Msk           (0x1UL << EXTI_IMR2_IM41_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR2_IM41               EXTI_IMR2_IM41_Msk                        /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos           (10U)
+#define EXTI_IMR2_IM42_Msk           (0x1UL << EXTI_IMR2_IM42_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR2_IM42               EXTI_IMR2_IM42_Msk                        /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos           (11U)
+#define EXTI_IMR2_IM43_Msk           (0x1UL << EXTI_IMR2_IM43_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR2_IM43               EXTI_IMR2_IM43_Msk                        /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos           (12U)
+#define EXTI_IMR2_IM44_Msk           (0x1UL << EXTI_IMR2_IM44_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR2_IM44               EXTI_IMR2_IM44_Msk                        /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM45_Pos           (13U)
+#define EXTI_IMR2_IM45_Msk           (0x1UL << EXTI_IMR2_IM45_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR2_IM45               EXTI_IMR2_IM45_Msk                        /*!< Interrupt Mask on line 45 */
+#define EXTI_IMR2_IM46_Pos           (14U)
+#define EXTI_IMR2_IM46_Msk           (0x1UL << EXTI_IMR2_IM46_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR2_IM46               EXTI_IMR2_IM46_Msk                        /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos           (15U)
+#define EXTI_IMR2_IM47_Msk           (0x1UL << EXTI_IMR2_IM47_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR2_IM47               EXTI_IMR2_IM47_Msk                        /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos           (16U)
+#define EXTI_IMR2_IM48_Msk           (0x1UL << EXTI_IMR2_IM48_Pos)             /*!< 0x00010000 */
+#define EXTI_IMR2_IM48               EXTI_IMR2_IM48_Msk                        /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos           (17U)
+#define EXTI_IMR2_IM49_Msk           (0x1UL << EXTI_IMR2_IM49_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR2_IM49               EXTI_IMR2_IM49_Msk                        /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos           (18U)
+#define EXTI_IMR2_IM50_Msk           (0x1UL << EXTI_IMR2_IM50_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR2_IM50               EXTI_IMR2_IM50_Msk                        /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos           (19U)
+#define EXTI_IMR2_IM51_Msk           (0x1UL << EXTI_IMR2_IM51_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR2_IM51               EXTI_IMR2_IM51_Msk                        /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos           (20U)
+#define EXTI_IMR2_IM52_Msk           (0x1UL << EXTI_IMR2_IM52_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR2_IM52               EXTI_IMR2_IM52_Msk                        /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos           (21U)
+#define EXTI_IMR2_IM53_Msk           (0x1UL << EXTI_IMR2_IM53_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR2_IM53               EXTI_IMR2_IM53_Msk                        /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos           (22U)
+#define EXTI_IMR2_IM54_Msk           (0x1UL << EXTI_IMR2_IM54_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR2_IM54               EXTI_IMR2_IM54_Msk                        /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos           (23U)
+#define EXTI_IMR2_IM55_Msk           (0x1UL << EXTI_IMR2_IM55_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR2_IM55               EXTI_IMR2_IM55_Msk                        /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos           (24U)
+#define EXTI_IMR2_IM56_Msk           (0x1UL << EXTI_IMR2_IM56_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR2_IM56               EXTI_IMR2_IM56_Msk                        /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos           (25U)
+#define EXTI_IMR2_IM57_Msk           (0x1UL << EXTI_IMR2_IM57_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR2_IM57               EXTI_IMR2_IM57_Msk                        /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos           (26U)
+#define EXTI_IMR2_IM58_Msk           (0x1UL << EXTI_IMR2_IM58_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR2_IM58               EXTI_IMR2_IM58_Msk                        /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM60_Pos           (28U)
+#define EXTI_IMR2_IM60_Msk           (0x1UL << EXTI_IMR2_IM60_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR2_IM60               EXTI_IMR2_IM60_Msk                        /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos           (29U)
+#define EXTI_IMR2_IM61_Msk           (0x1UL << EXTI_IMR2_IM61_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR2_IM61               EXTI_IMR2_IM61_Msk                        /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos           (30U)
+#define EXTI_IMR2_IM62_Msk           (0x1UL << EXTI_IMR2_IM62_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR2_IM62               EXTI_IMR2_IM62_Msk                        /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos           (31U)
+#define EXTI_IMR2_IM63_Msk           (0x1UL << EXTI_IMR2_IM63_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR2_IM63               EXTI_IMR2_IM63_Msk                        /*!< Interrupt Mask on line 63 */
+#define EXTI_IMR2_IM_Pos             (0U)
+#define EXTI_IMR2_IM_Msk             (0xF7FFFFFFUL << EXTI_IMR2_IM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_IMR2_IM                 EXTI_IMR2_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos           (0U)
+#define EXTI_EMR2_EM32_Msk           (0x1UL << EXTI_EMR2_EM32_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR2_EM32               EXTI_EMR2_EM32_Msk                        /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos           (1U)
+#define EXTI_EMR2_EM33_Msk           (0x1UL << EXTI_EMR2_EM33_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR2_EM33               EXTI_EMR2_EM33_Msk                        /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos           (2U)
+#define EXTI_EMR2_EM34_Msk           (0x1UL << EXTI_EMR2_EM34_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR2_EM34               EXTI_EMR2_EM34_Msk                        /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos           (3U)
+#define EXTI_EMR2_EM35_Msk           (0x1UL << EXTI_EMR2_EM35_Pos)             /*!< 0x00000008 */
+#define EXTI_EMR2_EM35               EXTI_EMR2_EM35_Msk                        /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos           (4U)
+#define EXTI_EMR2_EM36_Msk           (0x1UL << EXTI_EMR2_EM36_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR2_EM36               EXTI_EMR2_EM36_Msk                        /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos           (5U)
+#define EXTI_EMR2_EM37_Msk           (0x1UL << EXTI_EMR2_EM37_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR2_EM37               EXTI_EMR2_EM37_Msk                        /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos           (6U)
+#define EXTI_EMR2_EM38_Msk           (0x1UL << EXTI_EMR2_EM38_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR2_EM38               EXTI_EMR2_EM38_Msk                        /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos           (7U)
+#define EXTI_EMR2_EM39_Msk           (0x1UL << EXTI_EMR2_EM39_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR2_EM39               EXTI_EMR2_EM39_Msk                        /*!< Event Mask on line 39 */
+#define EXTI_EMR2_EM40_Pos           (8U)
+#define EXTI_EMR2_EM40_Msk           (0x1UL << EXTI_EMR2_EM40_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR2_EM40               EXTI_EMR2_EM40_Msk                        /*!< Event Mask on line 40 */
+#define EXTI_EMR2_EM41_Pos           (9U)
+#define EXTI_EMR2_EM41_Msk           (0x1UL << EXTI_EMR2_EM41_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR2_EM41               EXTI_EMR2_EM41_Msk                        /*!< Event Mask on line 41 */
+#define EXTI_EMR2_EM42_Pos           (10U)
+#define EXTI_EMR2_EM42_Msk           (0x1UL << EXTI_EMR2_EM42_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR2_EM42               EXTI_EMR2_EM42_Msk                        /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos           (11U)
+#define EXTI_EMR2_EM43_Msk           (0x1UL << EXTI_EMR2_EM43_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR2_EM43               EXTI_EMR2_EM43_Msk                        /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos           (12U)
+#define EXTI_EMR2_EM44_Msk           (0x1UL << EXTI_EMR2_EM44_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR2_EM44               EXTI_EMR2_EM44_Msk                        /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM45_Pos           (13U)
+#define EXTI_EMR2_EM45_Msk           (0x1UL << EXTI_EMR2_EM45_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR2_EM45               EXTI_EMR2_EM45_Msk                        /*!< Event Mask on line 45 */
+#define EXTI_EMR2_EM46_Pos           (14U)
+#define EXTI_EMR2_EM46_Msk           (0x1UL << EXTI_EMR2_EM46_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR2_EM46               EXTI_EMR2_EM46_Msk                        /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos           (15U)
+#define EXTI_EMR2_EM47_Msk           (0x1UL << EXTI_EMR2_EM47_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR2_EM47               EXTI_EMR2_EM47_Msk                        /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos           (16U)
+#define EXTI_EMR2_EM48_Msk           (0x1UL << EXTI_EMR2_EM48_Pos)             /*!< 0x00010000 */
+#define EXTI_EMR2_EM48               EXTI_EMR2_EM48_Msk                        /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos           (17U)
+#define EXTI_EMR2_EM49_Msk           (0x1UL << EXTI_EMR2_EM49_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR2_EM49               EXTI_EMR2_EM49_Msk                        /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos           (18U)
+#define EXTI_EMR2_EM50_Msk           (0x1UL << EXTI_EMR2_EM50_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR2_EM50               EXTI_EMR2_EM50_Msk                        /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos           (19U)
+#define EXTI_EMR2_EM51_Msk           (0x1UL << EXTI_EMR2_EM51_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR2_EM51               EXTI_EMR2_EM51_Msk                        /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos           (20U)
+#define EXTI_EMR2_EM52_Msk           (0x1UL << EXTI_EMR2_EM52_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR2_EM52               EXTI_EMR2_EM52_Msk                        /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos           (21U)
+#define EXTI_EMR2_EM53_Msk           (0x1UL << EXTI_EMR2_EM53_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR2_EM53               EXTI_EMR2_EM53_Msk                        /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos           (22U)
+#define EXTI_EMR2_EM54_Msk           (0x1UL << EXTI_EMR2_EM54_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR2_EM54               EXTI_EMR2_EM54_Msk                        /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos           (23U)
+#define EXTI_EMR2_EM55_Msk           (0x1UL << EXTI_EMR2_EM55_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR2_EM55               EXTI_EMR2_EM55_Msk                        /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos           (24U)
+#define EXTI_EMR2_EM56_Msk           (0x1UL << EXTI_EMR2_EM56_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR2_EM56               EXTI_EMR2_EM56_Msk                        /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos           (25U)
+#define EXTI_EMR2_EM57_Msk           (0x1UL << EXTI_EMR2_EM57_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR2_EM57               EXTI_EMR2_EM57_Msk                        /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos           (26U)
+#define EXTI_EMR2_EM58_Msk           (0x1UL << EXTI_EMR2_EM58_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR2_EM58               EXTI_EMR2_EM58_Msk                        /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM60_Pos           (28U)
+#define EXTI_EMR2_EM60_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR2_EM60               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos           (29U)
+#define EXTI_EMR2_EM61_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR2_EM61               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos           (30U)
+#define EXTI_EMR2_EM62_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR2_EM62               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos           (31U)
+#define EXTI_EMR2_EM63_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR2_EM63               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 63 */
+#define EXTI_EMR2_EM_Pos             (0U)
+#define EXTI_EMR2_EM_Msk             (0xF7FFFFFFUL << EXTI_EMR2_EM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_EMR2_EM                 EXTI_EMR2_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR3 register  ******************/
+#define EXTI_IMR3_IM64_Pos           (0U)
+#define EXTI_IMR3_IM64_Msk           (0x1UL << EXTI_IMR3_IM64_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR3_IM64               EXTI_IMR3_IM64_Msk                        /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos           (1U)
+#define EXTI_IMR3_IM65_Msk           (0x1UL << EXTI_IMR3_IM65_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR3_IM65               EXTI_IMR3_IM65_Msk                        /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos           (2U)
+#define EXTI_IMR3_IM66_Msk           (0x1UL << EXTI_IMR3_IM66_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR3_IM66               EXTI_IMR3_IM66_Msk                        /*!< Interrupt Mask on line 66  */
+#define EXTI_IMR3_IM68_Pos           (4U)
+#define EXTI_IMR3_IM68_Msk           (0x1UL << EXTI_IMR3_IM68_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR3_IM68               EXTI_IMR3_IM68_Msk                        /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos           (5U)
+#define EXTI_IMR3_IM69_Msk           (0x1UL << EXTI_IMR3_IM69_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR3_IM69               EXTI_IMR3_IM69_Msk                        /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos           (6U)
+#define EXTI_IMR3_IM70_Msk           (0x1UL << EXTI_IMR3_IM70_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR3_IM70               EXTI_IMR3_IM70_Msk                        /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos           (7U)
+#define EXTI_IMR3_IM71_Msk           (0x1UL << EXTI_IMR3_IM71_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR3_IM71               EXTI_IMR3_IM71_Msk                        /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos           (8U)
+#define EXTI_IMR3_IM72_Msk           (0x1UL << EXTI_IMR3_IM72_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR3_IM72               EXTI_IMR3_IM72_Msk                        /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos           (9U)
+#define EXTI_IMR3_IM73_Msk           (0x1UL << EXTI_IMR3_IM73_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR3_IM73               EXTI_IMR3_IM73_Msk                        /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos           (10U)
+#define EXTI_IMR3_IM74_Msk           (0x1UL << EXTI_IMR3_IM74_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR3_IM74               EXTI_IMR3_IM74_Msk                        /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM77_Pos           (13U)
+#define EXTI_IMR3_IM77_Msk           (0x1UL << EXTI_IMR3_IM77_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR3_IM77               EXTI_IMR3_IM77_Msk                        /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM_Pos             (0U)
+#define EXTI_IMR3_IM_Msk             (0x27F7UL << EXTI_IMR3_IM_Pos)             /*!< 0x000027F7 */
+#define EXTI_IMR3_IM                 EXTI_IMR3_IM_Msk                           /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR3 register  ******************/
+#define EXTI_EMR3_EM64_Pos           (0U)
+#define EXTI_EMR3_EM64_Msk           (0x1UL << EXTI_EMR3_EM64_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR3_EM64               EXTI_EMR3_EM64_Msk                        /*!< Event Mask on line 64 */
+#define EXTI_EMR3_EM65_Pos           (1U)
+#define EXTI_EMR3_EM65_Msk           (0x1UL << EXTI_EMR3_EM65_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR3_EM65               EXTI_EMR3_EM65_Msk                        /*!< Event Mask on line 65 */
+#define EXTI_EMR3_EM66_Pos           (2U)
+#define EXTI_EMR3_EM66_Msk           (0x1UL << EXTI_EMR3_EM66_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR3_EM66               EXTI_EMR3_EM66_Msk                        /*!< Event Mask on line 66  */
+#define EXTI_EMR3_EM68_Pos           (4U)
+#define EXTI_EMR3_EM68_Msk           (0x1UL << EXTI_EMR3_EM68_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR3_EM68               EXTI_EMR3_EM68_Msk                        /*!< Event Mask on line 68 */
+#define EXTI_EMR3_EM69_Pos           (5U)
+#define EXTI_EMR3_EM69_Msk           (0x1UL << EXTI_EMR3_EM69_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR3_EM69               EXTI_EMR3_EM69_Msk                        /*!< Event Mask on line 69 */
+#define EXTI_EMR3_EM70_Pos           (6U)
+#define EXTI_EMR3_EM70_Msk           (0x1UL << EXTI_EMR3_EM70_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR3_EM70               EXTI_EMR3_EM70_Msk                        /*!< Event Mask on line 70 */
+#define EXTI_EMR3_EM71_Pos           (7U)
+#define EXTI_EMR3_EM71_Msk           (0x1UL << EXTI_EMR3_EM71_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR3_EM71               EXTI_EMR3_EM71_Msk                        /*!< Event Mask on line 71 */
+#define EXTI_EMR3_EM72_Pos           (8U)
+#define EXTI_EMR3_EM72_Msk           (0x1UL << EXTI_EMR3_EM72_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR3_EM72               EXTI_EMR3_EM72_Msk                        /*!< Event Mask on line 72 */
+#define EXTI_EMR3_EM73_Pos           (9U)
+#define EXTI_EMR3_EM73_Msk           (0x1UL << EXTI_EMR3_EM73_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR3_EM73               EXTI_EMR3_EM73_Msk                        /*!< Event Mask on line 73 */
+#define EXTI_EMR3_EM74_Pos           (10U)
+#define EXTI_EMR3_EM74_Msk           (0x1UL << EXTI_EMR3_EM74_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR3_EM74               EXTI_EMR3_EM74_Msk                        /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM77_Pos           (13U)
+#define EXTI_EMR3_EM77_Msk           (0x1UL << EXTI_EMR3_EM77_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR3_EM77               EXTI_EMR3_EM77_Msk                        /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM_Pos             (0U)
+#define EXTI_EMR3_EM_Msk             (0x27F7UL << EXTI_EMR3_EM_Pos)             /*!< 0x000027F7 */
+#define EXTI_EMR3_EM                 EXTI_EMR3_EM_Msk                           /*!< Event Mask All */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos           (0U)
+#define FDCAN_CREL_DAY_Msk           (0xFFUL << FDCAN_CREL_DAY_Pos)            /*!< 0x000000FF */
+#define FDCAN_CREL_DAY               FDCAN_CREL_DAY_Msk                        /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos           (8U)
+#define FDCAN_CREL_MON_Msk           (0xFFUL << FDCAN_CREL_MON_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON               FDCAN_CREL_MON_Msk                        /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos          (16U)
+#define FDCAN_CREL_YEAR_Msk          (0xFUL << FDCAN_CREL_YEAR_Pos)            /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR              FDCAN_CREL_YEAR_Msk                       /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos       (20U)
+#define FDCAN_CREL_SUBSTEP_Msk       (0xFUL << FDCAN_CREL_SUBSTEP_Pos)         /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP           FDCAN_CREL_SUBSTEP_Msk                    /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos          (24U)
+#define FDCAN_CREL_STEP_Msk          (0xFUL << FDCAN_CREL_STEP_Pos)            /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP              FDCAN_CREL_STEP_Msk                       /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos           (28U)
+#define FDCAN_CREL_REL_Msk           (0xFUL << FDCAN_CREL_REL_Pos)             /*!< 0xF0000000 */
+#define FDCAN_CREL_REL               FDCAN_CREL_REL_Msk                        /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos           (0U)
+#define FDCAN_ENDN_ETV_Msk           (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV               FDCAN_ENDN_ETV_Msk                        /*!<Endianness Test Value                   */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos          (0U)
+#define FDCAN_DBTP_DSJW_Msk          (0xFUL << FDCAN_DBTP_DSJW_Pos)            /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW              FDCAN_DBTP_DSJW_Msk                       /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos        (4U)
+#define FDCAN_DBTP_DTSEG2_Msk        (0xFUL << FDCAN_DBTP_DTSEG2_Pos)          /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2            FDCAN_DBTP_DTSEG2_Msk                     /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos        (8U)
+#define FDCAN_DBTP_DTSEG1_Msk        (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)         /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1            FDCAN_DBTP_DTSEG1_Msk                     /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos          (16U)
+#define FDCAN_DBTP_DBRP_Msk          (0x1FUL << FDCAN_DBTP_DBRP_Pos)           /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP              FDCAN_DBTP_DBRP_Msk                       /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos           (23U)
+#define FDCAN_DBTP_TDC_Msk           (0x1UL << FDCAN_DBTP_TDC_Pos)             /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC               FDCAN_DBTP_TDC_Msk                        /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos          (4U)
+#define FDCAN_TEST_LBCK_Msk          (0x1UL << FDCAN_TEST_LBCK_Pos)            /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK              FDCAN_TEST_LBCK_Msk                       /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos            (5U)
+#define FDCAN_TEST_TX_Msk            (0x3UL << FDCAN_TEST_TX_Pos)              /*!< 0x00000060 */
+#define FDCAN_TEST_TX                FDCAN_TEST_TX_Msk                         /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos            (7U)
+#define FDCAN_TEST_RX_Msk            (0x1UL << FDCAN_TEST_RX_Pos)              /*!< 0x00000080 */
+#define FDCAN_TEST_RX                FDCAN_TEST_RX_Msk                         /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos            (0U)
+#define FDCAN_RWD_WDC_Msk            (0xFFUL << FDCAN_RWD_WDC_Pos)             /*!< 0x000000FF */
+#define FDCAN_RWD_WDC                FDCAN_RWD_WDC_Msk                         /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos            (8U)
+#define FDCAN_RWD_WDV_Msk            (0xFFUL << FDCAN_RWD_WDV_Pos)             /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV                FDCAN_RWD_WDV_Msk                         /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  *******************/
+#define FDCAN_CCCR_INIT_Pos          (0U)
+#define FDCAN_CCCR_INIT_Msk          (0x1UL << FDCAN_CCCR_INIT_Pos)            /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT              FDCAN_CCCR_INIT_Msk                       /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos           (1U)
+#define FDCAN_CCCR_CCE_Msk           (0x1UL << FDCAN_CCCR_CCE_Pos)             /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE               FDCAN_CCCR_CCE_Msk                        /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos           (2U)
+#define FDCAN_CCCR_ASM_Msk           (0x1UL << FDCAN_CCCR_ASM_Pos)             /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM               FDCAN_CCCR_ASM_Msk                        /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos           (3U)
+#define FDCAN_CCCR_CSA_Msk           (0x1UL << FDCAN_CCCR_CSA_Pos)             /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA               FDCAN_CCCR_CSA_Msk                        /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos           (4U)
+#define FDCAN_CCCR_CSR_Msk           (0x1UL << FDCAN_CCCR_CSR_Pos)             /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR               FDCAN_CCCR_CSR_Msk                        /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos           (5U)
+#define FDCAN_CCCR_MON_Msk           (0x1UL << FDCAN_CCCR_MON_Pos)             /*!< 0x00000020 */
+#define FDCAN_CCCR_MON               FDCAN_CCCR_MON_Msk                        /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos           (6U)
+#define FDCAN_CCCR_DAR_Msk           (0x1UL << FDCAN_CCCR_DAR_Pos)             /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR               FDCAN_CCCR_DAR_Msk                        /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos          (7U)
+#define FDCAN_CCCR_TEST_Msk          (0x1UL << FDCAN_CCCR_TEST_Pos)            /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST              FDCAN_CCCR_TEST_Msk                       /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos          (8U)
+#define FDCAN_CCCR_FDOE_Msk          (0x1UL << FDCAN_CCCR_FDOE_Pos)            /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE              FDCAN_CCCR_FDOE_Msk                       /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos          (9U)
+#define FDCAN_CCCR_BRSE_Msk          (0x1UL << FDCAN_CCCR_BRSE_Pos)            /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE              FDCAN_CCCR_BRSE_Msk                       /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos          (12U)
+#define FDCAN_CCCR_PXHD_Msk          (0x1UL << FDCAN_CCCR_PXHD_Pos)            /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD              FDCAN_CCCR_PXHD_Msk                       /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos          (13U)
+#define FDCAN_CCCR_EFBI_Msk          (0x1UL << FDCAN_CCCR_EFBI_Pos)            /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI              FDCAN_CCCR_EFBI_Msk                       /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos           (14U)
+#define FDCAN_CCCR_TXP_Msk           (0x1UL << FDCAN_CCCR_TXP_Pos)             /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP               FDCAN_CCCR_TXP_Msk                        /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos          (15U)
+#define FDCAN_CCCR_NISO_Msk          (0x1UL << FDCAN_CCCR_NISO_Pos)            /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO              FDCAN_CCCR_NISO_Msk                       /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  *******************/
+#define FDCAN_NBTP_NTSEG2_Pos        (0U)
+#define FDCAN_NBTP_NTSEG2_Msk        (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)         /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2            FDCAN_NBTP_NTSEG2_Msk                     /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos        (8U)
+#define FDCAN_NBTP_NTSEG1_Msk        (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)         /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1            FDCAN_NBTP_NTSEG1_Msk                     /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos          (16U)
+#define FDCAN_NBTP_NBRP_Msk          (0x1FFUL << FDCAN_NBTP_NBRP_Pos)          /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP              FDCAN_NBTP_NBRP_Msk                       /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos          (25U)
+#define FDCAN_NBTP_NSJW_Msk          (0x7FUL << FDCAN_NBTP_NSJW_Pos)           /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW              FDCAN_NBTP_NSJW_Msk                       /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  *******************/
+#define FDCAN_TSCC_TSS_Pos           (0U)
+#define FDCAN_TSCC_TSS_Msk           (0x3UL << FDCAN_TSCC_TSS_Pos)             /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS               FDCAN_TSCC_TSS_Msk                        /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos           (16U)
+#define FDCAN_TSCC_TCP_Msk           (0xFUL << FDCAN_TSCC_TCP_Pos)             /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP               FDCAN_TSCC_TCP_Msk                        /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  *******************/
+#define FDCAN_TSCV_TSC_Pos           (0U)
+#define FDCAN_TSCV_TSC_Msk           (0xFFFFUL << FDCAN_TSCV_TSC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC               FDCAN_TSCV_TSC_Msk                        /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  *******************/
+#define FDCAN_TOCC_ETOC_Pos          (0U)
+#define FDCAN_TOCC_ETOC_Msk          (0x1UL << FDCAN_TOCC_ETOC_Pos)            /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC              FDCAN_TOCC_ETOC_Msk                       /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos           (1U)
+#define FDCAN_TOCC_TOS_Msk           (0x3UL << FDCAN_TOCC_TOS_Pos)             /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS               FDCAN_TOCC_TOS_Msk                        /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos           (16U)
+#define FDCAN_TOCC_TOP_Msk           (0xFFFFUL << FDCAN_TOCC_TOP_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP               FDCAN_TOCC_TOP_Msk                        /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  *******************/
+#define FDCAN_TOCV_TOC_Pos           (0U)
+#define FDCAN_TOCV_TOC_Msk           (0xFFFFUL << FDCAN_TOCV_TOC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC               FDCAN_TOCV_TOC_Msk                        /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  ********************/
+#define FDCAN_ECR_TEC_Pos            (0U)
+#define FDCAN_ECR_TEC_Msk            (0xFFUL << FDCAN_ECR_TEC_Pos)             /*!< 0x000000FF */
+#define FDCAN_ECR_TEC                FDCAN_ECR_TEC_Msk                         /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos            (8U)
+#define FDCAN_ECR_REC_Msk            (0x7FUL << FDCAN_ECR_REC_Pos)             /*!< 0x00007F00 */
+#define FDCAN_ECR_REC                FDCAN_ECR_REC_Msk                         /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos             (15U)
+#define FDCAN_ECR_RP_Msk             (0x1UL << FDCAN_ECR_RP_Pos)               /*!< 0x00008000 */
+#define FDCAN_ECR_RP                 FDCAN_ECR_RP_Msk                          /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos            (16U)
+#define FDCAN_ECR_CEL_Msk            (0xFFUL << FDCAN_ECR_CEL_Pos)             /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL                FDCAN_ECR_CEL_Msk                         /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  ********************/
+#define FDCAN_PSR_LEC_Pos            (0U)
+#define FDCAN_PSR_LEC_Msk            (0x7UL << FDCAN_PSR_LEC_Pos)              /*!< 0x00000007 */
+#define FDCAN_PSR_LEC                FDCAN_PSR_LEC_Msk                         /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos            (3U)
+#define FDCAN_PSR_ACT_Msk            (0x3UL << FDCAN_PSR_ACT_Pos)              /*!< 0x00000018 */
+#define FDCAN_PSR_ACT                FDCAN_PSR_ACT_Msk                         /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos             (5U)
+#define FDCAN_PSR_EP_Msk             (0x1UL << FDCAN_PSR_EP_Pos)               /*!< 0x00000020 */
+#define FDCAN_PSR_EP                 FDCAN_PSR_EP_Msk                          /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos             (6U)
+#define FDCAN_PSR_EW_Msk             (0x1UL << FDCAN_PSR_EW_Pos)               /*!< 0x00000040 */
+#define FDCAN_PSR_EW                 FDCAN_PSR_EW_Msk                          /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos             (7U)
+#define FDCAN_PSR_BO_Msk             (0x1UL << FDCAN_PSR_BO_Pos)               /*!< 0x00000080 */
+#define FDCAN_PSR_BO                 FDCAN_PSR_BO_Msk                          /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos           (8U)
+#define FDCAN_PSR_DLEC_Msk           (0x7UL << FDCAN_PSR_DLEC_Pos)             /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC               FDCAN_PSR_DLEC_Msk                        /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos           (11U)
+#define FDCAN_PSR_RESI_Msk           (0x1UL << FDCAN_PSR_RESI_Pos)             /*!< 0x00000800 */
+#define FDCAN_PSR_RESI               FDCAN_PSR_RESI_Msk                        /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos           (12U)
+#define FDCAN_PSR_RBRS_Msk           (0x1UL << FDCAN_PSR_RBRS_Pos)             /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS               FDCAN_PSR_RBRS_Msk                        /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos           (13U)
+#define FDCAN_PSR_REDL_Msk           (0x1UL << FDCAN_PSR_REDL_Pos)             /*!< 0x00002000 */
+#define FDCAN_PSR_REDL               FDCAN_PSR_REDL_Msk                        /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos            (14U)
+#define FDCAN_PSR_PXE_Msk            (0x1UL << FDCAN_PSR_PXE_Pos)              /*!< 0x00004000 */
+#define FDCAN_PSR_PXE                FDCAN_PSR_PXE_Msk                         /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos           (16U)
+#define FDCAN_PSR_TDCV_Msk           (0x7FUL << FDCAN_PSR_TDCV_Pos)            /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV               FDCAN_PSR_TDCV_Msk                        /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  *******************/
+#define FDCAN_TDCR_TDCF_Pos          (0U)
+#define FDCAN_TDCR_TDCF_Msk          (0x7FUL << FDCAN_TDCR_TDCF_Pos)           /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF              FDCAN_TDCR_TDCF_Msk                       /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos          (8U)
+#define FDCAN_TDCR_TDCO_Msk          (0x7FUL << FDCAN_TDCR_TDCO_Pos)           /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO              FDCAN_TDCR_TDCO_Msk                       /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  *********************/
+#define FDCAN_IR_RF0N_Pos            (0U)
+#define FDCAN_IR_RF0N_Msk            (0x1UL << FDCAN_IR_RF0N_Pos)              /*!< 0x00000001 */
+#define FDCAN_IR_RF0N                FDCAN_IR_RF0N_Msk                         /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos            (1U)
+#define FDCAN_IR_RF0W_Msk            (0x1UL << FDCAN_IR_RF0W_Pos)              /*!< 0x00000002 */
+#define FDCAN_IR_RF0W                FDCAN_IR_RF0W_Msk                         /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos            (2U)
+#define FDCAN_IR_RF0F_Msk            (0x1UL << FDCAN_IR_RF0F_Pos)              /*!< 0x00000004 */
+#define FDCAN_IR_RF0F                FDCAN_IR_RF0F_Msk                         /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos            (3U)
+#define FDCAN_IR_RF0L_Msk            (0x1UL << FDCAN_IR_RF0L_Pos)              /*!< 0x00000008 */
+#define FDCAN_IR_RF0L                FDCAN_IR_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos            (4U)
+#define FDCAN_IR_RF1N_Msk            (0x1UL << FDCAN_IR_RF1N_Pos)              /*!< 0x00000010 */
+#define FDCAN_IR_RF1N                FDCAN_IR_RF1N_Msk                         /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos            (5U)
+#define FDCAN_IR_RF1W_Msk            (0x1UL << FDCAN_IR_RF1W_Pos)              /*!< 0x00000020 */
+#define FDCAN_IR_RF1W                FDCAN_IR_RF1W_Msk                         /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos            (6U)
+#define FDCAN_IR_RF1F_Msk            (0x1UL << FDCAN_IR_RF1F_Pos)              /*!< 0x00000040 */
+#define FDCAN_IR_RF1F                FDCAN_IR_RF1F_Msk                         /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos            (7U)
+#define FDCAN_IR_RF1L_Msk            (0x1UL << FDCAN_IR_RF1L_Pos)              /*!< 0x00000080 */
+#define FDCAN_IR_RF1L                FDCAN_IR_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos             (8U)
+#define FDCAN_IR_HPM_Msk             (0x1UL << FDCAN_IR_HPM_Pos)               /*!< 0x00000100 */
+#define FDCAN_IR_HPM                 FDCAN_IR_HPM_Msk                          /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos              (9U)
+#define FDCAN_IR_TC_Msk              (0x1UL << FDCAN_IR_TC_Pos)                /*!< 0x00000200 */
+#define FDCAN_IR_TC                  FDCAN_IR_TC_Msk                           /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos             (10U)
+#define FDCAN_IR_TCF_Msk             (0x1UL << FDCAN_IR_TCF_Pos)               /*!< 0x00000400 */
+#define FDCAN_IR_TCF                 FDCAN_IR_TCF_Msk                          /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos             (11U)
+#define FDCAN_IR_TFE_Msk             (0x1UL << FDCAN_IR_TFE_Pos)               /*!< 0x00000800 */
+#define FDCAN_IR_TFE                 FDCAN_IR_TFE_Msk                          /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos            (12U)
+#define FDCAN_IR_TEFN_Msk            (0x1UL << FDCAN_IR_TEFN_Pos)              /*!< 0x00001000 */
+#define FDCAN_IR_TEFN                FDCAN_IR_TEFN_Msk                         /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos            (13U)
+#define FDCAN_IR_TEFW_Msk            (0x1UL << FDCAN_IR_TEFW_Pos)              /*!< 0x00002000 */
+#define FDCAN_IR_TEFW                FDCAN_IR_TEFW_Msk                         /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos            (14U)
+#define FDCAN_IR_TEFF_Msk            (0x1UL << FDCAN_IR_TEFF_Pos)              /*!< 0x00004000 */
+#define FDCAN_IR_TEFF                FDCAN_IR_TEFF_Msk                         /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos            (15U)
+#define FDCAN_IR_TEFL_Msk            (0x1UL << FDCAN_IR_TEFL_Pos)              /*!< 0x00008000 */
+#define FDCAN_IR_TEFL                FDCAN_IR_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos             (16U)
+#define FDCAN_IR_TSW_Msk             (0x1UL << FDCAN_IR_TSW_Pos)               /*!< 0x00010000 */
+#define FDCAN_IR_TSW                 FDCAN_IR_TSW_Msk                          /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos            (17U)
+#define FDCAN_IR_MRAF_Msk            (0x1UL << FDCAN_IR_MRAF_Pos)              /*!< 0x00020000 */
+#define FDCAN_IR_MRAF                FDCAN_IR_MRAF_Msk                         /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos             (18U)
+#define FDCAN_IR_TOO_Msk             (0x1UL << FDCAN_IR_TOO_Pos)               /*!< 0x00040000 */
+#define FDCAN_IR_TOO                 FDCAN_IR_TOO_Msk                          /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos             (19U)
+#define FDCAN_IR_DRX_Msk             (0x1UL << FDCAN_IR_DRX_Pos)               /*!< 0x00080000 */
+#define FDCAN_IR_DRX                 FDCAN_IR_DRX_Msk                          /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos             (22U)
+#define FDCAN_IR_ELO_Msk             (0x1UL << FDCAN_IR_ELO_Pos)               /*!< 0x00400000 */
+#define FDCAN_IR_ELO                 FDCAN_IR_ELO_Msk                          /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos              (23U)
+#define FDCAN_IR_EP_Msk              (0x1UL << FDCAN_IR_EP_Pos)                /*!< 0x00800000 */
+#define FDCAN_IR_EP                  FDCAN_IR_EP_Msk                           /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos              (24U)
+#define FDCAN_IR_EW_Msk              (0x1UL << FDCAN_IR_EW_Pos)                /*!< 0x01000000 */
+#define FDCAN_IR_EW                  FDCAN_IR_EW_Msk                           /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos              (25U)
+#define FDCAN_IR_BO_Msk              (0x1UL << FDCAN_IR_BO_Pos)                /*!< 0x02000000 */
+#define FDCAN_IR_BO                  FDCAN_IR_BO_Msk                           /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos             (26U)
+#define FDCAN_IR_WDI_Msk             (0x1UL << FDCAN_IR_WDI_Pos)               /*!< 0x04000000 */
+#define FDCAN_IR_WDI                 FDCAN_IR_WDI_Msk                          /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos             (27U)
+#define FDCAN_IR_PEA_Msk             (0x1UL << FDCAN_IR_PEA_Pos)               /*!< 0x08000000 */
+#define FDCAN_IR_PEA                 FDCAN_IR_PEA_Msk                          /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos             (28U)
+#define FDCAN_IR_PED_Msk             (0x1UL << FDCAN_IR_PED_Pos)               /*!< 0x10000000 */
+#define FDCAN_IR_PED                 FDCAN_IR_PED_Msk                          /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos             (29U)
+#define FDCAN_IR_ARA_Msk             (0x1UL << FDCAN_IR_ARA_Pos)               /*!< 0x20000000 */
+#define FDCAN_IR_ARA                 FDCAN_IR_ARA_Msk                          /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  *********************/
+#define FDCAN_IE_RF0NE_Pos           (0U)
+#define FDCAN_IE_RF0NE_Msk           (0x1UL << FDCAN_IE_RF0NE_Pos)             /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE               FDCAN_IE_RF0NE_Msk                        /*!<Rx FIFO 0 New Message Enable             */
+#define FDCAN_IE_RF0WE_Pos           (1U)
+#define FDCAN_IE_RF0WE_Msk           (0x1UL << FDCAN_IE_RF0WE_Pos)             /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE               FDCAN_IE_RF0WE_Msk                        /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos           (2U)
+#define FDCAN_IE_RF0FE_Msk           (0x1UL << FDCAN_IE_RF0FE_Pos)             /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE               FDCAN_IE_RF0FE_Msk                        /*!<Rx FIFO 0 Full Enable                    */
+#define FDCAN_IE_RF0LE_Pos           (3U)
+#define FDCAN_IE_RF0LE_Msk           (0x1UL << FDCAN_IE_RF0LE_Pos)             /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE               FDCAN_IE_RF0LE_Msk                        /*!<Rx FIFO 0 Message Lost Enable            */
+#define FDCAN_IE_RF1NE_Pos           (4U)
+#define FDCAN_IE_RF1NE_Msk           (0x1UL << FDCAN_IE_RF1NE_Pos)             /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE               FDCAN_IE_RF1NE_Msk                        /*!<Rx FIFO 1 New Message Enable             */
+#define FDCAN_IE_RF1WE_Pos           (5U)
+#define FDCAN_IE_RF1WE_Msk           (0x1UL << FDCAN_IE_RF1WE_Pos)             /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE               FDCAN_IE_RF1WE_Msk                        /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos           (6U)
+#define FDCAN_IE_RF1FE_Msk           (0x1UL << FDCAN_IE_RF1FE_Pos)             /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE               FDCAN_IE_RF1FE_Msk                        /*!<Rx FIFO 1 Full Enable                    */
+#define FDCAN_IE_RF1LE_Pos           (7U)
+#define FDCAN_IE_RF1LE_Msk           (0x1UL << FDCAN_IE_RF1LE_Pos)             /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE               FDCAN_IE_RF1LE_Msk                        /*!<Rx FIFO 1 Message Lost Enable            */
+#define FDCAN_IE_HPME_Pos            (8U)
+#define FDCAN_IE_HPME_Msk            (0x1UL << FDCAN_IE_HPME_Pos)              /*!< 0x00000100 */
+#define FDCAN_IE_HPME                FDCAN_IE_HPME_Msk                         /*!<High Priority Message Enable             */
+#define FDCAN_IE_TCE_Pos             (9U)
+#define FDCAN_IE_TCE_Msk             (0x1UL << FDCAN_IE_TCE_Pos)               /*!< 0x00000200 */
+#define FDCAN_IE_TCE                 FDCAN_IE_TCE_Msk                          /*!<Transmission Completed Enable            */
+#define FDCAN_IE_TCFE_Pos            (10U)
+#define FDCAN_IE_TCFE_Msk            (0x1UL << FDCAN_IE_TCFE_Pos)              /*!< 0x00000400 */
+#define FDCAN_IE_TCFE                FDCAN_IE_TCFE_Msk                         /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos            (11U)
+#define FDCAN_IE_TFEE_Msk            (0x1UL << FDCAN_IE_TFEE_Pos)              /*!< 0x00000800 */
+#define FDCAN_IE_TFEE                FDCAN_IE_TFEE_Msk                         /*!<Tx FIFO Empty Enable                     */
+#define FDCAN_IE_TEFNE_Pos           (12U)
+#define FDCAN_IE_TEFNE_Msk           (0x1UL << FDCAN_IE_TEFNE_Pos)             /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE               FDCAN_IE_TEFNE_Msk                        /*!<Tx Event FIFO New Entry Enable           */
+#define FDCAN_IE_TEFWE_Pos           (13U)
+#define FDCAN_IE_TEFWE_Msk           (0x1UL << FDCAN_IE_TEFWE_Pos)             /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE               FDCAN_IE_TEFWE_Msk                        /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos           (14U)
+#define FDCAN_IE_TEFFE_Msk           (0x1UL << FDCAN_IE_TEFFE_Pos)             /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE               FDCAN_IE_TEFFE_Msk                        /*!<Tx Event FIFO Full Enable                */
+#define FDCAN_IE_TEFLE_Pos           (15U)
+#define FDCAN_IE_TEFLE_Msk           (0x1UL << FDCAN_IE_TEFLE_Pos)             /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE               FDCAN_IE_TEFLE_Msk                        /*!<Tx Event FIFO Element Lost Enable        */
+#define FDCAN_IE_TSWE_Pos            (16U)
+#define FDCAN_IE_TSWE_Msk            (0x1UL << FDCAN_IE_TSWE_Pos)              /*!< 0x00010000 */
+#define FDCAN_IE_TSWE                FDCAN_IE_TSWE_Msk                         /*!<Timestamp Wraparound Enable              */
+#define FDCAN_IE_MRAFE_Pos           (17U)
+#define FDCAN_IE_MRAFE_Msk           (0x1UL << FDCAN_IE_MRAFE_Pos)             /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE               FDCAN_IE_MRAFE_Msk                        /*!<Message RAM Access Failure Enable        */
+#define FDCAN_IE_TOOE_Pos            (18U)
+#define FDCAN_IE_TOOE_Msk            (0x1UL << FDCAN_IE_TOOE_Pos)              /*!< 0x00040000 */
+#define FDCAN_IE_TOOE                FDCAN_IE_TOOE_Msk                         /*!<Timeout Occurred Enable                  */
+#define FDCAN_IE_DRXE_Pos            (19U)
+#define FDCAN_IE_DRXE_Msk            (0x1UL << FDCAN_IE_DRXE_Pos)              /*!< 0x00080000 */
+#define FDCAN_IE_DRXE                FDCAN_IE_DRXE_Msk                         /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos            (20U)
+#define FDCAN_IE_BECE_Msk            (0x1UL << FDCAN_IE_BECE_Pos)              /*!< 0x00100000 */
+#define FDCAN_IE_BECE                FDCAN_IE_BECE_Msk                         /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos            (21U)
+#define FDCAN_IE_BEUE_Msk            (0x1UL << FDCAN_IE_BEUE_Pos)              /*!< 0x00200000 */
+#define FDCAN_IE_BEUE                FDCAN_IE_BEUE_Msk                         /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos            (22U)
+#define FDCAN_IE_ELOE_Msk            (0x1UL << FDCAN_IE_ELOE_Pos)              /*!< 0x00400000 */
+#define FDCAN_IE_ELOE                FDCAN_IE_ELOE_Msk                         /*!<Error Logging Overflow Enable            */
+#define FDCAN_IE_EPE_Pos             (23U)
+#define FDCAN_IE_EPE_Msk             (0x1UL << FDCAN_IE_EPE_Pos)               /*!< 0x00800000 */
+#define FDCAN_IE_EPE                 FDCAN_IE_EPE_Msk                          /*!<Error Passive Enable                     */
+#define FDCAN_IE_EWE_Pos             (24U)
+#define FDCAN_IE_EWE_Msk             (0x1UL << FDCAN_IE_EWE_Pos)               /*!< 0x01000000 */
+#define FDCAN_IE_EWE                 FDCAN_IE_EWE_Msk                          /*!<Warning Status Enable                    */
+#define FDCAN_IE_BOE_Pos             (25U)
+#define FDCAN_IE_BOE_Msk             (0x1UL << FDCAN_IE_BOE_Pos)               /*!< 0x02000000 */
+#define FDCAN_IE_BOE                 FDCAN_IE_BOE_Msk                          /*!<Bus_Off Status Enable                    */
+#define FDCAN_IE_WDIE_Pos            (26U)
+#define FDCAN_IE_WDIE_Msk            (0x1UL << FDCAN_IE_WDIE_Pos)              /*!< 0x04000000 */
+#define FDCAN_IE_WDIE                FDCAN_IE_WDIE_Msk                         /*!<Watchdog Interrupt Enable                */
+#define FDCAN_IE_PEAE_Pos            (27U)
+#define FDCAN_IE_PEAE_Msk            (0x1UL << FDCAN_IE_PEAE_Pos)              /*!< 0x08000000 */
+#define FDCAN_IE_PEAE                FDCAN_IE_PEAE_Msk                         /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos            (28U)
+#define FDCAN_IE_PEDE_Msk            (0x1UL << FDCAN_IE_PEDE_Pos)              /*!< 0x10000000 */
+#define FDCAN_IE_PEDE                FDCAN_IE_PEDE_Msk                         /*!<Protocol Error in Data Phase Enable      */
+#define FDCAN_IE_ARAE_Pos            (29U)
+#define FDCAN_IE_ARAE_Msk            (0x1UL << FDCAN_IE_ARAE_Pos)              /*!< 0x20000000 */
+#define FDCAN_IE_ARAE                FDCAN_IE_ARAE_Msk                         /*!<Access to Reserved Address Enable        */
+
+/*****************  Bit definition for FDCAN_ILS register  ********************/
+#define FDCAN_ILS_RF0NL_Pos          (0U)
+#define FDCAN_ILS_RF0NL_Msk          (0x1UL << FDCAN_ILS_RF0NL_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL              FDCAN_ILS_RF0NL_Msk                       /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos          (1U)
+#define FDCAN_ILS_RF0WL_Msk          (0x1UL << FDCAN_ILS_RF0WL_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL              FDCAN_ILS_RF0WL_Msk                       /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos          (2U)
+#define FDCAN_ILS_RF0FL_Msk          (0x1UL << FDCAN_ILS_RF0FL_Pos)            /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL              FDCAN_ILS_RF0FL_Msk                       /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos          (3U)
+#define FDCAN_ILS_RF0LL_Msk          (0x1UL << FDCAN_ILS_RF0LL_Pos)            /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL              FDCAN_ILS_RF0LL_Msk                       /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos          (4U)
+#define FDCAN_ILS_RF1NL_Msk          (0x1UL << FDCAN_ILS_RF1NL_Pos)            /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL              FDCAN_ILS_RF1NL_Msk                       /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos          (5U)
+#define FDCAN_ILS_RF1WL_Msk          (0x1UL << FDCAN_ILS_RF1WL_Pos)            /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL              FDCAN_ILS_RF1WL_Msk                       /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos          (6U)
+#define FDCAN_ILS_RF1FL_Msk          (0x1UL << FDCAN_ILS_RF1FL_Pos)            /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL              FDCAN_ILS_RF1FL_Msk                       /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos          (7U)
+#define FDCAN_ILS_RF1LL_Msk          (0x1UL << FDCAN_ILS_RF1LL_Pos)            /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL              FDCAN_ILS_RF1LL_Msk                       /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos           (8U)
+#define FDCAN_ILS_HPML_Msk           (0x1UL << FDCAN_ILS_HPML_Pos)             /*!< 0x00000100 */
+#define FDCAN_ILS_HPML               FDCAN_ILS_HPML_Msk                        /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos            (9U)
+#define FDCAN_ILS_TCL_Msk            (0x1UL << FDCAN_ILS_TCL_Pos)              /*!< 0x00000200 */
+#define FDCAN_ILS_TCL                FDCAN_ILS_TCL_Msk                         /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos           (10U)
+#define FDCAN_ILS_TCFL_Msk           (0x1UL << FDCAN_ILS_TCFL_Pos)             /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL               FDCAN_ILS_TCFL_Msk                        /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos           (11U)
+#define FDCAN_ILS_TFEL_Msk           (0x1UL << FDCAN_ILS_TFEL_Pos)             /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL               FDCAN_ILS_TFEL_Msk                        /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos          (12U)
+#define FDCAN_ILS_TEFNL_Msk          (0x1UL << FDCAN_ILS_TEFNL_Pos)            /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL              FDCAN_ILS_TEFNL_Msk                       /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos          (13U)
+#define FDCAN_ILS_TEFWL_Msk          (0x1UL << FDCAN_ILS_TEFWL_Pos)            /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL              FDCAN_ILS_TEFWL_Msk                       /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos          (14U)
+#define FDCAN_ILS_TEFFL_Msk          (0x1UL << FDCAN_ILS_TEFFL_Pos)            /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL              FDCAN_ILS_TEFFL_Msk                       /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos          (15U)
+#define FDCAN_ILS_TEFLL_Msk          (0x1UL << FDCAN_ILS_TEFLL_Pos)            /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL              FDCAN_ILS_TEFLL_Msk                       /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos           (16U)
+#define FDCAN_ILS_TSWL_Msk           (0x1UL << FDCAN_ILS_TSWL_Pos)             /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL               FDCAN_ILS_TSWL_Msk                        /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFL_Pos          (17U)
+#define FDCAN_ILS_MRAFL_Msk          (0x1UL << FDCAN_ILS_MRAFL_Pos)            /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFL              FDCAN_ILS_MRAFL_Msk                       /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOL_Pos           (18U)
+#define FDCAN_ILS_TOOL_Msk           (0x1UL << FDCAN_ILS_TOOL_Pos)             /*!< 0x00040000 */
+#define FDCAN_ILS_TOOL               FDCAN_ILS_TOOL_Msk                        /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXL_Pos           (19U)
+#define FDCAN_ILS_DRXL_Msk           (0x1UL << FDCAN_ILS_DRXL_Pos)             /*!< 0x00080000 */
+#define FDCAN_ILS_DRXL               FDCAN_ILS_DRXL_Msk                        /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_ELOL_Pos           (22U)
+#define FDCAN_ILS_ELOL_Msk           (0x1UL << FDCAN_ILS_ELOL_Pos)             /*!< 0x00400000 */
+#define FDCAN_ILS_ELOL               FDCAN_ILS_ELOL_Msk                        /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPL_Pos            (23U)
+#define FDCAN_ILS_EPL_Msk            (0x1UL << FDCAN_ILS_EPL_Pos)              /*!< 0x00800000 */
+#define FDCAN_ILS_EPL                FDCAN_ILS_EPL_Msk                         /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWL_Pos            (24U)
+#define FDCAN_ILS_EWL_Msk            (0x1UL << FDCAN_ILS_EWL_Pos)              /*!< 0x01000000 */
+#define FDCAN_ILS_EWL                FDCAN_ILS_EWL_Msk                         /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOL_Pos            (25U)
+#define FDCAN_ILS_BOL_Msk            (0x1UL << FDCAN_ILS_BOL_Pos)              /*!< 0x02000000 */
+#define FDCAN_ILS_BOL                FDCAN_ILS_BOL_Msk                         /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIL_Pos           (26U)
+#define FDCAN_ILS_WDIL_Msk           (0x1UL << FDCAN_ILS_WDIL_Pos)             /*!< 0x04000000 */
+#define FDCAN_ILS_WDIL               FDCAN_ILS_WDIL_Msk                        /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAL_Pos           (27U)
+#define FDCAN_ILS_PEAL_Msk           (0x1UL << FDCAN_ILS_PEAL_Pos)             /*!< 0x08000000 */
+#define FDCAN_ILS_PEAL               FDCAN_ILS_PEAL_Msk                        /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDL_Pos           (28U)
+#define FDCAN_ILS_PEDL_Msk           (0x1UL << FDCAN_ILS_PEDL_Pos)             /*!< 0x10000000 */
+#define FDCAN_ILS_PEDL               FDCAN_ILS_PEDL_Msk                        /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAL_Pos           (29U)
+#define FDCAN_ILS_ARAL_Msk           (0x1UL << FDCAN_ILS_ARAL_Pos)             /*!< 0x20000000 */
+#define FDCAN_ILS_ARAL               FDCAN_ILS_ARAL_Msk                        /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  ********************/
+#define FDCAN_ILE_EINT0_Pos          (0U)
+#define FDCAN_ILE_EINT0_Msk          (0x1UL << FDCAN_ILE_EINT0_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0              FDCAN_ILE_EINT0_Msk                       /*!<Enable Interrupt Line 0                  */
+#define FDCAN_ILE_EINT1_Pos          (1U)
+#define FDCAN_ILE_EINT1_Msk          (0x1UL << FDCAN_ILE_EINT1_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1              FDCAN_ILE_EINT1_Msk                       /*!<Enable Interrupt Line 1                  */
+
+/*****************  Bit definition for FDCAN_GFC register  ******************/
+#define FDCAN_GFC_RRFE_Pos           (0U)
+#define FDCAN_GFC_RRFE_Msk           (0x1UL << FDCAN_GFC_RRFE_Pos)             /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE               FDCAN_GFC_RRFE_Msk                        /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos           (1U)
+#define FDCAN_GFC_RRFS_Msk           (0x1UL << FDCAN_GFC_RRFS_Pos)             /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS               FDCAN_GFC_RRFS_Msk                        /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos           (2U)
+#define FDCAN_GFC_ANFE_Msk           (0x3UL << FDCAN_GFC_ANFE_Pos)             /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE               FDCAN_GFC_ANFE_Msk                        /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos           (4U)
+#define FDCAN_GFC_ANFS_Msk           (0x3UL << FDCAN_GFC_ANFS_Pos)             /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS               FDCAN_GFC_ANFS_Msk                        /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos        (2U)
+#define FDCAN_SIDFC_FLSSA_Msk        (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA            FDCAN_SIDFC_FLSSA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos          (16U)
+#define FDCAN_SIDFC_LSS_Msk          (0xFFUL << FDCAN_SIDFC_LSS_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS              FDCAN_SIDFC_LSS_Msk                       /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos        (2U)
+#define FDCAN_XIDFC_FLESA_Msk        (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA            FDCAN_XIDFC_FLESA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos          (16U)
+#define FDCAN_XIDFC_LSE_Msk          (0x7FUL << FDCAN_XIDFC_LSE_Pos)           /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE              FDCAN_XIDFC_LSE_Msk                       /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ******************/
+#define FDCAN_XIDAM_EIDM_Pos         (0U)
+#define FDCAN_XIDAM_EIDM_Msk         (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)    /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM             FDCAN_XIDAM_EIDM_Msk                      /*!<Extended ID Mask                         */
+
+/*****************  Bit definition for FDCAN_HPMS register  *******************/
+#define FDCAN_HPMS_BIDX_Pos          (0U)
+#define FDCAN_HPMS_BIDX_Msk          (0x3FUL << FDCAN_HPMS_BIDX_Pos)           /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX              FDCAN_HPMS_BIDX_Msk                       /*!<Buffer Index                             */
+#define FDCAN_HPMS_MSI_Pos           (6U)
+#define FDCAN_HPMS_MSI_Msk           (0x3UL << FDCAN_HPMS_MSI_Pos)             /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI               FDCAN_HPMS_MSI_Msk                        /*!<Message Storage Indicator                */
+#define FDCAN_HPMS_FIDX_Pos          (8U)
+#define FDCAN_HPMS_FIDX_Msk          (0x7FUL << FDCAN_HPMS_FIDX_Pos)           /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX              FDCAN_HPMS_FIDX_Msk                       /*!<Filter Index                             */
+#define FDCAN_HPMS_FLST_Pos          (15U)
+#define FDCAN_HPMS_FLST_Msk          (0x1UL << FDCAN_HPMS_FLST_Pos)            /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST              FDCAN_HPMS_FLST_Msk                       /*!<Filter List                              */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos          (0U)
+#define FDCAN_NDAT1_ND0_Msk          (0x1UL << FDCAN_NDAT1_ND0_Pos)            /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0              FDCAN_NDAT1_ND0_Msk                       /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos          (1U)
+#define FDCAN_NDAT1_ND1_Msk          (0x1UL << FDCAN_NDAT1_ND1_Pos)            /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1              FDCAN_NDAT1_ND1_Msk                       /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos          (2U)
+#define FDCAN_NDAT1_ND2_Msk          (0x1UL << FDCAN_NDAT1_ND2_Pos)            /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2              FDCAN_NDAT1_ND2_Msk                       /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos          (3U)
+#define FDCAN_NDAT1_ND3_Msk          (0x1UL << FDCAN_NDAT1_ND3_Pos)            /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3              FDCAN_NDAT1_ND3_Msk                       /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos          (4U)
+#define FDCAN_NDAT1_ND4_Msk          (0x1UL << FDCAN_NDAT1_ND4_Pos)            /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4              FDCAN_NDAT1_ND4_Msk                       /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos          (5U)
+#define FDCAN_NDAT1_ND5_Msk          (0x1UL << FDCAN_NDAT1_ND5_Pos)            /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5              FDCAN_NDAT1_ND5_Msk                       /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos          (6U)
+#define FDCAN_NDAT1_ND6_Msk          (0x1UL << FDCAN_NDAT1_ND6_Pos)            /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6              FDCAN_NDAT1_ND6_Msk                       /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos          (7U)
+#define FDCAN_NDAT1_ND7_Msk          (0x1UL << FDCAN_NDAT1_ND7_Pos)            /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7              FDCAN_NDAT1_ND7_Msk                       /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos          (8U)
+#define FDCAN_NDAT1_ND8_Msk          (0x1UL << FDCAN_NDAT1_ND8_Pos)            /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8              FDCAN_NDAT1_ND8_Msk                       /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos              (9U)
+#define FDCAN_NDAT1_ND9_Msk          (0x1UL << FDCAN_NDAT1_ND9_Pos)            /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9              FDCAN_NDAT1_ND9_Msk                       /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos            (10U)
+#define FDCAN_NDAT1_ND10_Msk         (0x1UL << FDCAN_NDAT1_ND10_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10             FDCAN_NDAT1_ND10_Msk                      /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos         (11U)
+#define FDCAN_NDAT1_ND11_Msk         (0x1UL << FDCAN_NDAT1_ND11_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11             FDCAN_NDAT1_ND11_Msk                      /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos         (12U)
+#define FDCAN_NDAT1_ND12_Msk         (0x1UL << FDCAN_NDAT1_ND12_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12             FDCAN_NDAT1_ND12_Msk                      /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos         (13U)
+#define FDCAN_NDAT1_ND13_Msk         (0x1UL << FDCAN_NDAT1_ND13_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13             FDCAN_NDAT1_ND13_Msk                      /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos         (14U)
+#define FDCAN_NDAT1_ND14_Msk         (0x1UL << FDCAN_NDAT1_ND14_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14             FDCAN_NDAT1_ND14_Msk                      /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos         (15U)
+#define FDCAN_NDAT1_ND15_Msk         (0x1UL << FDCAN_NDAT1_ND15_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15             FDCAN_NDAT1_ND15_Msk                      /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos         (16U)
+#define FDCAN_NDAT1_ND16_Msk         (0x1UL << FDCAN_NDAT1_ND16_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16             FDCAN_NDAT1_ND16_Msk                      /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos         (17U)
+#define FDCAN_NDAT1_ND17_Msk         (0x1UL << FDCAN_NDAT1_ND17_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17             FDCAN_NDAT1_ND17_Msk                      /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos         (18U)
+#define FDCAN_NDAT1_ND18_Msk         (0x1UL << FDCAN_NDAT1_ND18_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18             FDCAN_NDAT1_ND18_Msk                      /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos         (19U)
+#define FDCAN_NDAT1_ND19_Msk         (0x1UL << FDCAN_NDAT1_ND19_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19             FDCAN_NDAT1_ND19_Msk                      /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos         (20U)
+#define FDCAN_NDAT1_ND20_Msk         (0x1UL << FDCAN_NDAT1_ND20_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20             FDCAN_NDAT1_ND20_Msk                      /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos         (21U)
+#define FDCAN_NDAT1_ND21_Msk         (0x1UL << FDCAN_NDAT1_ND21_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21             FDCAN_NDAT1_ND21_Msk                      /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos         (22U)
+#define FDCAN_NDAT1_ND22_Msk         (0x1UL << FDCAN_NDAT1_ND22_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22             FDCAN_NDAT1_ND22_Msk                      /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos         (23U)
+#define FDCAN_NDAT1_ND23_Msk         (0x1UL << FDCAN_NDAT1_ND23_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23             FDCAN_NDAT1_ND23_Msk                      /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos         (24U)
+#define FDCAN_NDAT1_ND24_Msk         (0x1UL << FDCAN_NDAT1_ND24_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24             FDCAN_NDAT1_ND24_Msk                      /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos         (25U)
+#define FDCAN_NDAT1_ND25_Msk         (0x1UL << FDCAN_NDAT1_ND25_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25             FDCAN_NDAT1_ND25_Msk                      /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos         (26U)
+#define FDCAN_NDAT1_ND26_Msk         (0x1UL << FDCAN_NDAT1_ND26_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26             FDCAN_NDAT1_ND26_Msk                      /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos         (27U)
+#define FDCAN_NDAT1_ND27_Msk         (0x1UL << FDCAN_NDAT1_ND27_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27             FDCAN_NDAT1_ND27_Msk                      /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos         (28U)
+#define FDCAN_NDAT1_ND28_Msk         (0x1UL << FDCAN_NDAT1_ND28_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28             FDCAN_NDAT1_ND28_Msk                      /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos         (29U)
+#define FDCAN_NDAT1_ND29_Msk         (0x1UL << FDCAN_NDAT1_ND29_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29             FDCAN_NDAT1_ND29_Msk                      /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos         (30U)
+#define FDCAN_NDAT1_ND30_Msk         (0x1UL << FDCAN_NDAT1_ND30_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30             FDCAN_NDAT1_ND30_Msk                      /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos         (31U)
+#define FDCAN_NDAT1_ND31_Msk         (0x1UL << FDCAN_NDAT1_ND31_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31             FDCAN_NDAT1_ND31_Msk                      /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos         (0U)
+#define FDCAN_NDAT2_ND32_Msk         (0x1UL << FDCAN_NDAT2_ND32_Pos)           /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32             FDCAN_NDAT2_ND32_Msk                      /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos         (1U)
+#define FDCAN_NDAT2_ND33_Msk         (0x1UL << FDCAN_NDAT2_ND33_Pos)           /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33             FDCAN_NDAT2_ND33_Msk                      /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos         (2U)
+#define FDCAN_NDAT2_ND34_Msk         (0x1UL << FDCAN_NDAT2_ND34_Pos)           /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34             FDCAN_NDAT2_ND34_Msk                      /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos         (3U)
+#define FDCAN_NDAT2_ND35_Msk         (0x1UL << FDCAN_NDAT2_ND35_Pos)           /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35             FDCAN_NDAT2_ND35_Msk                      /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos         (4U)
+#define FDCAN_NDAT2_ND36_Msk         (0x1UL << FDCAN_NDAT2_ND36_Pos)           /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36             FDCAN_NDAT2_ND36_Msk                      /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos         (5U)
+#define FDCAN_NDAT2_ND37_Msk         (0x1UL << FDCAN_NDAT2_ND37_Pos)           /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37             FDCAN_NDAT2_ND37_Msk                      /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos         (6U)
+#define FDCAN_NDAT2_ND38_Msk         (0x1UL << FDCAN_NDAT2_ND38_Pos)           /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38             FDCAN_NDAT2_ND38_Msk                      /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos         (7U)
+#define FDCAN_NDAT2_ND39_Msk         (0x1UL << FDCAN_NDAT2_ND39_Pos)           /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39             FDCAN_NDAT2_ND39_Msk                      /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos         (8U)
+#define FDCAN_NDAT2_ND40_Msk         (0x1UL << FDCAN_NDAT2_ND40_Pos)           /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40             FDCAN_NDAT2_ND40_Msk                      /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos         (9U)
+#define FDCAN_NDAT2_ND41_Msk         (0x1UL << FDCAN_NDAT2_ND41_Pos)           /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41             FDCAN_NDAT2_ND41_Msk                      /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos         (10U)
+#define FDCAN_NDAT2_ND42_Msk         (0x1UL << FDCAN_NDAT2_ND42_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42             FDCAN_NDAT2_ND42_Msk                      /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos         (11U)
+#define FDCAN_NDAT2_ND43_Msk         (0x1UL << FDCAN_NDAT2_ND43_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43             FDCAN_NDAT2_ND43_Msk                      /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos         (12U)
+#define FDCAN_NDAT2_ND44_Msk         (0x1UL << FDCAN_NDAT2_ND44_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44             FDCAN_NDAT2_ND44_Msk                      /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos         (13U)
+#define FDCAN_NDAT2_ND45_Msk         (0x1UL << FDCAN_NDAT2_ND45_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45             FDCAN_NDAT2_ND45_Msk                      /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos         (14U)
+#define FDCAN_NDAT2_ND46_Msk         (0x1UL << FDCAN_NDAT2_ND46_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46             FDCAN_NDAT2_ND46_Msk                      /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos         (15U)
+#define FDCAN_NDAT2_ND47_Msk         (0x1UL << FDCAN_NDAT2_ND47_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47             FDCAN_NDAT2_ND47_Msk                      /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos         (16U)
+#define FDCAN_NDAT2_ND48_Msk         (0x1UL << FDCAN_NDAT2_ND48_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48             FDCAN_NDAT2_ND48_Msk                      /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos         (17U)
+#define FDCAN_NDAT2_ND49_Msk         (0x1UL << FDCAN_NDAT2_ND49_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49             FDCAN_NDAT2_ND49_Msk                      /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos         (18U)
+#define FDCAN_NDAT2_ND50_Msk         (0x1UL << FDCAN_NDAT2_ND50_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50             FDCAN_NDAT2_ND50_Msk                      /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos         (19U)
+#define FDCAN_NDAT2_ND51_Msk         (0x1UL << FDCAN_NDAT2_ND51_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51             FDCAN_NDAT2_ND51_Msk                      /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos         (20U)
+#define FDCAN_NDAT2_ND52_Msk         (0x1UL << FDCAN_NDAT2_ND52_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52             FDCAN_NDAT2_ND52_Msk                      /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos         (21U)
+#define FDCAN_NDAT2_ND53_Msk         (0x1UL << FDCAN_NDAT2_ND53_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53             FDCAN_NDAT2_ND53_Msk                      /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos         (22U)
+#define FDCAN_NDAT2_ND54_Msk         (0x1UL << FDCAN_NDAT2_ND54_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54             FDCAN_NDAT2_ND54_Msk                      /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos         (23U)
+#define FDCAN_NDAT2_ND55_Msk         (0x1UL << FDCAN_NDAT2_ND55_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55             FDCAN_NDAT2_ND55_Msk                      /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos         (24U)
+#define FDCAN_NDAT2_ND56_Msk         (0x1UL << FDCAN_NDAT2_ND56_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56             FDCAN_NDAT2_ND56_Msk                      /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos         (25U)
+#define FDCAN_NDAT2_ND57_Msk         (0x1UL << FDCAN_NDAT2_ND57_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57             FDCAN_NDAT2_ND57_Msk                      /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos         (26U)
+#define FDCAN_NDAT2_ND58_Msk         (0x1UL << FDCAN_NDAT2_ND58_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58             FDCAN_NDAT2_ND58_Msk                      /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos         (27U)
+#define FDCAN_NDAT2_ND59_Msk         (0x1UL << FDCAN_NDAT2_ND59_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59             FDCAN_NDAT2_ND59_Msk                      /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos         (28U)
+#define FDCAN_NDAT2_ND60_Msk         (0x1UL << FDCAN_NDAT2_ND60_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60             FDCAN_NDAT2_ND60_Msk                      /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos         (29U)
+#define FDCAN_NDAT2_ND61_Msk         (0x1UL << FDCAN_NDAT2_ND61_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61             FDCAN_NDAT2_ND61_Msk                      /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos         (30U)
+#define FDCAN_NDAT2_ND62_Msk         (0x1UL << FDCAN_NDAT2_ND62_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62             FDCAN_NDAT2_ND62_Msk                      /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos         (31U)
+#define FDCAN_NDAT2_ND63_Msk         (0x1UL << FDCAN_NDAT2_ND63_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63             FDCAN_NDAT2_ND63_Msk                      /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos         (2U)
+#define FDCAN_RXF0C_F0SA_Msk         (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA             FDCAN_RXF0C_F0SA_Msk                      /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos          (16U)
+#define FDCAN_RXF0C_F0S_Msk          (0x7FUL << FDCAN_RXF0C_F0S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S              FDCAN_RXF0C_F0S_Msk                       /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos         (24U)
+#define FDCAN_RXF0C_F0WM_Msk         (0x7FUL << FDCAN_RXF0C_F0WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM             FDCAN_RXF0C_F0WM_Msk                      /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos         (31U)
+#define FDCAN_RXF0C_F0OM_Msk         (0x1UL << FDCAN_RXF0C_F0OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM             FDCAN_RXF0C_F0OM_Msk                      /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ******************/
+#define FDCAN_RXF0S_F0FL_Pos         (0U)
+#define FDCAN_RXF0S_F0FL_Msk         (0x7FUL << FDCAN_RXF0S_F0FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL             FDCAN_RXF0S_F0FL_Msk                      /*!<Rx FIFO 0 Fill Level                     */
+#define FDCAN_RXF0S_F0GI_Pos         (8U)
+#define FDCAN_RXF0S_F0GI_Msk         (0x3FUL << FDCAN_RXF0S_F0GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI             FDCAN_RXF0S_F0GI_Msk                      /*!<Rx FIFO 0 Get Index                      */
+#define FDCAN_RXF0S_F0PI_Pos         (16U)
+#define FDCAN_RXF0S_F0PI_Msk         (0x3FUL << FDCAN_RXF0S_F0PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI             FDCAN_RXF0S_F0PI_Msk                      /*!<Rx FIFO 0 Put Index                      */
+#define FDCAN_RXF0S_F0F_Pos          (24U)
+#define FDCAN_RXF0S_F0F_Msk          (0x1UL << FDCAN_RXF0S_F0F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F              FDCAN_RXF0S_F0F_Msk                       /*!<Rx FIFO 0 Full                           */
+#define FDCAN_RXF0S_RF0L_Pos         (25U)
+#define FDCAN_RXF0S_RF0L_Msk         (0x1UL << FDCAN_RXF0S_RF0L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L             FDCAN_RXF0S_RF0L_Msk                      /*!<Rx FIFO 0 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ******************/
+#define FDCAN_RXF0A_F0AI_Pos         (0U)
+#define FDCAN_RXF0A_F0AI_Msk         (0x3FUL << FDCAN_RXF0A_F0AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI             FDCAN_RXF0A_F0AI_Msk                      /*!<Rx FIFO 0 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos          (2U)
+#define FDCAN_RXBC_RBSA_Msk          (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA              FDCAN_RXBC_RBSA_Msk                       /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ******************/
+#define FDCAN_RXF1C_F1SA_Pos         (2U)
+#define FDCAN_RXF1C_F1SA_Msk         (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA             FDCAN_RXF1C_F1SA_Msk                      /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos          (16U)
+#define FDCAN_RXF1C_F1S_Msk          (0x7FUL << FDCAN_RXF1C_F1S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S              FDCAN_RXF1C_F1S_Msk                       /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos         (24U)
+#define FDCAN_RXF1C_F1WM_Msk         (0x7FUL << FDCAN_RXF1C_F1WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM             FDCAN_RXF1C_F1WM_Msk                      /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos         (31U)
+#define FDCAN_RXF1C_F1OM_Msk         (0x1UL << FDCAN_RXF1C_F1OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM             FDCAN_RXF1C_F1OM_Msk                      /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ******************/
+#define FDCAN_RXF1S_F1FL_Pos         (0U)
+#define FDCAN_RXF1S_F1FL_Msk         (0x7FUL << FDCAN_RXF1S_F1FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL             FDCAN_RXF1S_F1FL_Msk                      /*!<Rx FIFO 1 Fill Level                     */
+#define FDCAN_RXF1S_F1GI_Pos         (8U)
+#define FDCAN_RXF1S_F1GI_Msk         (0x3FUL << FDCAN_RXF1S_F1GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI             FDCAN_RXF1S_F1GI_Msk                      /*!<Rx FIFO 1 Get Index                      */
+#define FDCAN_RXF1S_F1PI_Pos         (16U)
+#define FDCAN_RXF1S_F1PI_Msk         (0x3FUL << FDCAN_RXF1S_F1PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI             FDCAN_RXF1S_F1PI_Msk                      /*!<Rx FIFO 1 Put Index                      */
+#define FDCAN_RXF1S_F1F_Pos          (24U)
+#define FDCAN_RXF1S_F1F_Msk          (0x1UL << FDCAN_RXF1S_F1F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F              FDCAN_RXF1S_F1F_Msk                       /*!<Rx FIFO 1 Full                           */
+#define FDCAN_RXF1S_RF1L_Pos         (25U)
+#define FDCAN_RXF1S_RF1L_Msk         (0x1UL << FDCAN_RXF1S_RF1L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L             FDCAN_RXF1S_RF1L_Msk                      /*!<Rx FIFO 1 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ******************/
+#define FDCAN_RXF1A_F1AI_Pos         (0U)
+#define FDCAN_RXF1A_F1AI_Msk         (0x3FUL << FDCAN_RXF1A_F1AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI             FDCAN_RXF1A_F1AI_Msk                      /*!<Rx FIFO 1 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXESC register  ******************/
+#define FDCAN_RXESC_F0DS_Pos         (0U)
+#define FDCAN_RXESC_F0DS_Msk         (0x7UL << FDCAN_RXESC_F0DS_Pos)           /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS             FDCAN_RXESC_F0DS_Msk                      /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos         (4U)
+#define FDCAN_RXESC_F1DS_Msk         (0x7UL << FDCAN_RXESC_F1DS_Pos)           /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS             FDCAN_RXESC_F1DS_Msk                      /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos         (8U)
+#define FDCAN_RXESC_RBDS_Msk         (0x7UL << FDCAN_RXESC_RBDS_Pos)           /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS             FDCAN_RXESC_RBDS_Msk                      /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *******************/
+#define FDCAN_TXBC_TBSA_Pos          (2U)
+#define FDCAN_TXBC_TBSA_Msk          (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA              FDCAN_TXBC_TBSA_Msk                       /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos          (16U)
+#define FDCAN_TXBC_NDTB_Msk          (0x3FUL << FDCAN_TXBC_NDTB_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB              FDCAN_TXBC_NDTB_Msk                       /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos          (24U)
+#define FDCAN_TXBC_TFQS_Msk          (0x3FUL << FDCAN_TXBC_TFQS_Pos)           /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS              FDCAN_TXBC_TFQS_Msk                       /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos          (30U)
+#define FDCAN_TXBC_TFQM_Msk          (0x1UL << FDCAN_TXBC_TFQM_Pos)            /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM              FDCAN_TXBC_TFQM_Msk                       /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  ******************/
+#define FDCAN_TXFQS_TFFL_Pos         (0U)
+#define FDCAN_TXFQS_TFFL_Msk         (0x3FUL << FDCAN_TXFQS_TFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL             FDCAN_TXFQS_TFFL_Msk                      /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos         (8U)
+#define FDCAN_TXFQS_TFGI_Msk         (0x1FUL << FDCAN_TXFQS_TFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI             FDCAN_TXFQS_TFGI_Msk                      /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos        (16U)
+#define FDCAN_TXFQS_TFQPI_Msk        (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)         /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI            FDCAN_TXFQS_TFQPI_Msk                     /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos         (21U)
+#define FDCAN_TXFQS_TFQF_Msk         (0x1UL << FDCAN_TXFQS_TFQF_Pos)           /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF             FDCAN_TXFQS_TFQF_Msk                      /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  ******************/
+#define FDCAN_TXESC_TBDS_Pos         (0U)
+#define FDCAN_TXESC_TBDS_Msk         (0x7UL << FDCAN_TXESC_TBDS_Pos)           /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS             FDCAN_TXESC_TBDS_Msk                      /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  ******************/
+#define FDCAN_TXBRP_TRP_Pos          (0U)
+#define FDCAN_TXBRP_TRP_Msk          (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)     /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP              FDCAN_TXBRP_TRP_Msk                       /*!<Transmission Request Pending             */
+
+/*****************  Bit definition for FDCAN_TXBAR register  ******************/
+#define FDCAN_TXBAR_AR_Pos           (0U)
+#define FDCAN_TXBAR_AR_Msk           (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR               FDCAN_TXBAR_AR_Msk                        /*!<Add Request                              */
+
+/*****************  Bit definition for FDCAN_TXBCR register  ******************/
+#define FDCAN_TXBCR_CR_Pos           (0U)
+#define FDCAN_TXBCR_CR_Msk           (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR               FDCAN_TXBCR_CR_Msk                        /*!<Cancellation Request                     */
+
+/*****************  Bit definition for FDCAN_TXBTO register  ******************/
+#define FDCAN_TXBTO_TO_Pos           (0U)
+#define FDCAN_TXBTO_TO_Msk           (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO               FDCAN_TXBTO_TO_Msk                        /*!<Transmission Occurred                    */
+
+/*****************  Bit definition for FDCAN_TXBCF register  ******************/
+#define FDCAN_TXBCF_CF_Pos           (0U)
+#define FDCAN_TXBCF_CF_Msk           (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF               FDCAN_TXBCF_CF_Msk                        /*!<Cancellation Finished                    */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  *****************/
+#define FDCAN_TXBTIE_TIE_Pos         (0U)
+#define FDCAN_TXBTIE_TIE_Msk         (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)    /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE             FDCAN_TXBTIE_TIE_Msk                      /*!<Transmission Interrupt Enable            */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  ****************/
+#define FDCAN_TXBCIE_CFIE_Pos        (0U)
+#define FDCAN_TXBCIE_CFIE_Msk        (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)   /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE            FDCAN_TXBCIE_CFIE_Msk                     /*!<Cancellation Finished Interrupt Enable   */
+
+/*****************  Bit definition for FDCAN_TXEFC register  ******************/
+#define FDCAN_TXEFC_EFSA_Pos         (2U)
+#define FDCAN_TXEFC_EFSA_Msk         (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA             FDCAN_TXEFC_EFSA_Msk                      /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos          (16U)
+#define FDCAN_TXEFC_EFS_Msk          (0x3FUL << FDCAN_TXEFC_EFS_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS              FDCAN_TXEFC_EFS_Msk                       /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos         (24U)
+#define FDCAN_TXEFC_EFWM_Msk         (0x3FUL << FDCAN_TXEFC_EFWM_Pos)          /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM             FDCAN_TXEFC_EFWM_Msk                      /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  ******************/
+#define FDCAN_TXEFS_EFFL_Pos         (0U)
+#define FDCAN_TXEFS_EFFL_Msk         (0x3FUL << FDCAN_TXEFS_EFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL             FDCAN_TXEFS_EFFL_Msk                      /*!<Event FIFO Fill Level                    */
+#define FDCAN_TXEFS_EFGI_Pos         (8U)
+#define FDCAN_TXEFS_EFGI_Msk         (0x1FUL << FDCAN_TXEFS_EFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI             FDCAN_TXEFS_EFGI_Msk                      /*!<Event FIFO Get Index                     */
+#define FDCAN_TXEFS_EFPI_Pos         (16U)
+#define FDCAN_TXEFS_EFPI_Msk         (0x1FUL << FDCAN_TXEFS_EFPI_Pos)          /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI             FDCAN_TXEFS_EFPI_Msk                      /*!<Event FIFO Put Index                     */
+#define FDCAN_TXEFS_EFF_Pos          (24U)
+#define FDCAN_TXEFS_EFF_Msk          (0x1UL << FDCAN_TXEFS_EFF_Pos)            /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF              FDCAN_TXEFS_EFF_Msk                       /*!<Event FIFO Full                          */
+#define FDCAN_TXEFS_TEFL_Pos         (25U)
+#define FDCAN_TXEFS_TEFL_Msk         (0x1UL << FDCAN_TXEFS_TEFL_Pos)           /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL             FDCAN_TXEFS_TEFL_Msk                      /*!<Tx Event FIFO Element Lost               */
+
+/*****************  Bit definition for FDCAN_TXEFA register  ******************/
+#define FDCAN_TXEFA_EFAI_Pos         (0U)
+#define FDCAN_TXEFA_EFAI_Msk         (0x1FUL << FDCAN_TXEFA_EFAI_Pos)          /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI             FDCAN_TXEFA_EFAI_Msk                      /*!<Event FIFO Acknowledge Index             */
+
+/*****************  Bit definition for FDCAN_TTTMC register  ******************/
+#define FDCAN_TTTMC_TMSA_Pos         (2U)
+#define FDCAN_TTTMC_TMSA_Msk         (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA             FDCAN_TTTMC_TMSA_Msk                      /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos          (16U)
+#define FDCAN_TTTMC_TME_Msk          (0x7FUL << FDCAN_TTTMC_TME_Pos)           /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME              FDCAN_TTTMC_TME_Msk                       /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  ******************/
+#define FDCAN_TTRMC_RID_Pos          (0U)
+#define FDCAN_TTRMC_RID_Msk          (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)     /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID              FDCAN_TTRMC_RID_Msk                       /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos          (30U)
+#define FDCAN_TTRMC_XTD_Msk          (0x1UL << FDCAN_TTRMC_XTD_Pos)            /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD              FDCAN_TTRMC_XTD_Msk                       /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos         (31U)
+#define FDCAN_TTRMC_RMPS_Msk         (0x1UL << FDCAN_TTRMC_RMPS_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS             FDCAN_TTRMC_RMPS_Msk                      /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  ******************/
+#define FDCAN_TTOCF_OM_Pos           (0U)
+#define FDCAN_TTOCF_OM_Msk           (0x3UL << FDCAN_TTOCF_OM_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM               FDCAN_TTOCF_OM_Msk                        /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos          (3U)
+#define FDCAN_TTOCF_GEN_Msk          (0x1UL << FDCAN_TTOCF_GEN_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN              FDCAN_TTOCF_GEN_Msk                       /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos           (4U)
+#define FDCAN_TTOCF_TM_Msk           (0x1UL << FDCAN_TTOCF_TM_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM               FDCAN_TTOCF_TM_Msk                        /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos        (5U)
+#define FDCAN_TTOCF_LDSDL_Msk        (0x7UL << FDCAN_TTOCF_LDSDL_Pos)          /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL            FDCAN_TTOCF_LDSDL_Msk                     /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos         (8U)
+#define FDCAN_TTOCF_IRTO_Msk         (0x7FUL << FDCAN_TTOCF_IRTO_Pos)          /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO             FDCAN_TTOCF_IRTO_Msk                      /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos         (15U)
+#define FDCAN_TTOCF_EECS_Msk         (0x1UL << FDCAN_TTOCF_EECS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS             FDCAN_TTOCF_EECS_Msk                      /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos          (16U)
+#define FDCAN_TTOCF_AWL_Msk          (0xFFUL << FDCAN_TTOCF_AWL_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL              FDCAN_TTOCF_AWL_Msk                       /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos         (24U)
+#define FDCAN_TTOCF_EGTF_Msk         (0x1UL << FDCAN_TTOCF_EGTF_Pos)           /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF             FDCAN_TTOCF_EGTF_Msk                      /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos          (25U)
+#define FDCAN_TTOCF_ECC_Msk          (0x1UL << FDCAN_TTOCF_ECC_Pos)            /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC              FDCAN_TTOCF_ECC_Msk                       /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos         (26U)
+#define FDCAN_TTOCF_EVTP_Msk         (0x1UL << FDCAN_TTOCF_EVTP_Pos)           /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP             FDCAN_TTOCF_EVTP_Msk                      /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  ******************/
+#define FDCAN_TTMLM_CCM_Pos          (0U)
+#define FDCAN_TTMLM_CCM_Msk          (0x3FUL << FDCAN_TTMLM_CCM_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM              FDCAN_TTMLM_CCM_Msk                       /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos          (6U)
+#define FDCAN_TTMLM_CSS_Msk          (0x3UL << FDCAN_TTMLM_CSS_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS              FDCAN_TTMLM_CSS_Msk                       /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos         (8U)
+#define FDCAN_TTMLM_TXEW_Msk         (0xFUL << FDCAN_TTMLM_TXEW_Pos)           /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW             FDCAN_TTMLM_TXEW_Msk                      /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos         (16U)
+#define FDCAN_TTMLM_ENTT_Msk         (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)         /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT             FDCAN_TTMLM_ENTT_Msk                      /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  ******************/
+#define FDCAN_TURCF_NCL_Pos          (0U)
+#define FDCAN_TURCF_NCL_Msk          (0xFFFFUL << FDCAN_TURCF_NCL_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL              FDCAN_TURCF_NCL_Msk                       /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos           (16U)
+#define FDCAN_TURCF_DC_Msk           (0x3FFFUL << FDCAN_TURCF_DC_Pos)          /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC               FDCAN_TURCF_DC_Msk                        /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos          (31U)
+#define FDCAN_TURCF_ELT_Msk          (0x1UL << FDCAN_TURCF_ELT_Pos)            /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT              FDCAN_TURCF_ELT_Msk                       /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ******************/
+#define FDCAN_TTOCN_SGT_Pos          (0U)
+#define FDCAN_TTOCN_SGT_Msk          (0x1UL << FDCAN_TTOCN_SGT_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT              FDCAN_TTOCN_SGT_Msk                       /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos          (1U)
+#define FDCAN_TTOCN_ECS_Msk          (0x1UL << FDCAN_TTOCN_ECS_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS              FDCAN_TTOCN_ECS_Msk                       /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos          (2U)
+#define FDCAN_TTOCN_SWP_Msk          (0x1UL << FDCAN_TTOCN_SWP_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP              FDCAN_TTOCN_SWP_Msk                       /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos          (3U)
+#define FDCAN_TTOCN_SWS_Msk          (0x3UL << FDCAN_TTOCN_SWS_Pos)            /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS              FDCAN_TTOCN_SWS_Msk                       /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos         (5U)
+#define FDCAN_TTOCN_RTIE_Msk         (0x1UL << FDCAN_TTOCN_RTIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE             FDCAN_TTOCN_RTIE_Msk                      /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos          (6U)
+#define FDCAN_TTOCN_TMC_Msk          (0x3UL << FDCAN_TTOCN_TMC_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC              FDCAN_TTOCN_TMC_Msk                       /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos         (8U)
+#define FDCAN_TTOCN_TTIE_Msk         (0x1UL << FDCAN_TTOCN_TTIE_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE             FDCAN_TTOCN_TTIE_Msk                      /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos          (9U)
+#define FDCAN_TTOCN_GCS_Msk          (0x1UL << FDCAN_TTOCN_GCS_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS              FDCAN_TTOCN_GCS_Msk                       /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos          (10U)
+#define FDCAN_TTOCN_FGP_Msk          (0x1UL << FDCAN_TTOCN_FGP_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP              FDCAN_TTOCN_FGP_Msk                       /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos          (11U)
+#define FDCAN_TTOCN_TMG_Msk          (0x1UL << FDCAN_TTOCN_TMG_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG              FDCAN_TTOCN_TMG_Msk                       /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos          (12U)
+#define FDCAN_TTOCN_NIG_Msk          (0x1UL << FDCAN_TTOCN_NIG_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG              FDCAN_TTOCN_NIG_Msk                       /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos         (13U)
+#define FDCAN_TTOCN_ESCN_Msk         (0x1UL << FDCAN_TTOCN_ESCN_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN             FDCAN_TTOCN_ESCN_Msk                      /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos         (15U)
+#define FDCAN_TTOCN_LCKC_Msk         (0x1UL << FDCAN_TTOCN_LCKC_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC             FDCAN_TTOCN_LCKC_Msk                      /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ******************/
+#define FDCAN_TTGTP_TP_Pos           (0U)
+#define FDCAN_TTGTP_TP_Msk           (0xFFFFUL << FDCAN_TTGTP_TP_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP               FDCAN_TTGTP_TP_Msk                        /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos          (16U)
+#define FDCAN_TTGTP_CTP_Msk          (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP              FDCAN_TTGTP_CTP_Msk                       /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ******************/
+#define FDCAN_TTTMK_TM_Pos           (0U)
+#define FDCAN_TTTMK_TM_Msk           (0xFFFFUL << FDCAN_TTTMK_TM_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM               FDCAN_TTTMK_TM_Msk                        /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos         (16U)
+#define FDCAN_TTTMK_TICC_Msk         (0x7FUL << FDCAN_TTTMK_TICC_Pos)          /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC             FDCAN_TTTMK_TICC_Msk                      /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos         (31U)
+#define FDCAN_TTTMK_LCKM_Msk         (0x1UL << FDCAN_TTTMK_LCKM_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM             FDCAN_TTTMK_LCKM_Msk                      /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  *******************/
+#define FDCAN_TTIR_SBC_Pos           (0U)
+#define FDCAN_TTIR_SBC_Msk           (0x1UL << FDCAN_TTIR_SBC_Pos)             /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC               FDCAN_TTIR_SBC_Msk                        /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos           (1U)
+#define FDCAN_TTIR_SMC_Msk           (0x1UL << FDCAN_TTIR_SMC_Pos)             /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC               FDCAN_TTIR_SMC_Msk                        /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos           (2U)
+#define FDCAN_TTIR_CSM_Msk           (0x1UL << FDCAN_TTIR_CSM_Pos)             /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM               FDCAN_TTIR_CSM_Msk                        /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos           (3U)
+#define FDCAN_TTIR_SOG_Msk           (0x1UL << FDCAN_TTIR_SOG_Pos)             /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG               FDCAN_TTIR_SOG_Msk                        /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos          (4U)
+#define FDCAN_TTIR_RTMI_Msk          (0x1UL << FDCAN_TTIR_RTMI_Pos)            /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI              FDCAN_TTIR_RTMI_Msk                       /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos          (5U)
+#define FDCAN_TTIR_TTMI_Msk          (0x1UL << FDCAN_TTIR_TTMI_Pos)            /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI              FDCAN_TTIR_TTMI_Msk                       /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos           (6U)
+#define FDCAN_TTIR_SWE_Msk           (0x1UL << FDCAN_TTIR_SWE_Pos)             /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE               FDCAN_TTIR_SWE_Msk                        /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos           (7U)
+#define FDCAN_TTIR_GTW_Msk           (0x1UL << FDCAN_TTIR_GTW_Pos)             /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW               FDCAN_TTIR_GTW_Msk                        /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos           (8U)
+#define FDCAN_TTIR_GTD_Msk           (0x1UL << FDCAN_TTIR_GTD_Pos)             /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD               FDCAN_TTIR_GTD_Msk                        /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos           (9U)
+#define FDCAN_TTIR_GTE_Msk           (0x1UL << FDCAN_TTIR_GTE_Pos)             /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE               FDCAN_TTIR_GTE_Msk                        /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos           (10U)
+#define FDCAN_TTIR_TXU_Msk           (0x1UL << FDCAN_TTIR_TXU_Pos)             /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU               FDCAN_TTIR_TXU_Msk                        /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos           (11U)
+#define FDCAN_TTIR_TXO_Msk           (0x1UL << FDCAN_TTIR_TXO_Pos)             /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO               FDCAN_TTIR_TXO_Msk                        /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos           (12U)
+#define FDCAN_TTIR_SE1_Msk           (0x1UL << FDCAN_TTIR_SE1_Pos)             /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1               FDCAN_TTIR_SE1_Msk                        /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos           (13U)
+#define FDCAN_TTIR_SE2_Msk           (0x1UL << FDCAN_TTIR_SE2_Pos)             /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2               FDCAN_TTIR_SE2_Msk                        /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos           (14U)
+#define FDCAN_TTIR_ELC_Msk           (0x1UL << FDCAN_TTIR_ELC_Pos)             /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC               FDCAN_TTIR_ELC_Msk                        /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos           (15U)
+#define FDCAN_TTIR_IWT_Msk           (0x1UL << FDCAN_TTIR_IWT_Pos)             /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT               FDCAN_TTIR_IWT_Msk                        /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos            (16U)
+#define FDCAN_TTIR_WT_Msk            (0x1UL << FDCAN_TTIR_WT_Pos)              /*!< 0x00010000 */
+#define FDCAN_TTIR_WT                FDCAN_TTIR_WT_Msk                         /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos            (17U)
+#define FDCAN_TTIR_AW_Msk            (0x1UL << FDCAN_TTIR_AW_Pos)              /*!< 0x00020000 */
+#define FDCAN_TTIR_AW                FDCAN_TTIR_AW_Msk                         /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos           (18U)
+#define FDCAN_TTIR_CER_Msk           (0x1UL << FDCAN_TTIR_CER_Pos)             /*!< 0x00040000 */
+#define FDCAN_TTIR_CER               FDCAN_TTIR_CER_Msk                        /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  *******************/
+#define FDCAN_TTIE_SBCE_Pos          (0U)
+#define FDCAN_TTIE_SBCE_Msk          (0x1UL << FDCAN_TTIE_SBCE_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE              FDCAN_TTIE_SBCE_Msk                       /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos          (1U)
+#define FDCAN_TTIE_SMCE_Msk          (0x1UL << FDCAN_TTIE_SMCE_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE              FDCAN_TTIE_SMCE_Msk                       /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos          (2U)
+#define FDCAN_TTIE_CSME_Msk          (0x1UL << FDCAN_TTIE_CSME_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME              FDCAN_TTIE_CSME_Msk                       /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos          (3U)
+#define FDCAN_TTIE_SOGE_Msk          (0x1UL << FDCAN_TTIE_SOGE_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE              FDCAN_TTIE_SOGE_Msk                       /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos         (4U)
+#define FDCAN_TTIE_RTMIE_Msk         (0x1UL << FDCAN_TTIE_RTMIE_Pos)           /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE             FDCAN_TTIE_RTMIE_Msk                      /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos         (5U)
+#define FDCAN_TTIE_TTMIE_Msk         (0x1UL << FDCAN_TTIE_TTMIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE             FDCAN_TTIE_TTMIE_Msk                      /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos          (6U)
+#define FDCAN_TTIE_SWEE_Msk          (0x1UL << FDCAN_TTIE_SWEE_Pos)            /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE              FDCAN_TTIE_SWEE_Msk                       /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos          (7U)
+#define FDCAN_TTIE_GTWE_Msk          (0x1UL << FDCAN_TTIE_GTWE_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE              FDCAN_TTIE_GTWE_Msk                       /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos          (8U)
+#define FDCAN_TTIE_GTDE_Msk          (0x1UL << FDCAN_TTIE_GTDE_Pos)            /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE              FDCAN_TTIE_GTDE_Msk                       /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos          (9U)
+#define FDCAN_TTIE_GTEE_Msk          (0x1UL << FDCAN_TTIE_GTEE_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE              FDCAN_TTIE_GTEE_Msk                       /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos          (10U)
+#define FDCAN_TTIE_TXUE_Msk          (0x1UL << FDCAN_TTIE_TXUE_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE              FDCAN_TTIE_TXUE_Msk                       /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos          (11U)
+#define FDCAN_TTIE_TXOE_Msk          (0x1UL << FDCAN_TTIE_TXOE_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE              FDCAN_TTIE_TXOE_Msk                       /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos          (12U)
+#define FDCAN_TTIE_SE1E_Msk          (0x1UL << FDCAN_TTIE_SE1E_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E              FDCAN_TTIE_SE1E_Msk                       /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos          (13U)
+#define FDCAN_TTIE_SE2E_Msk          (0x1UL << FDCAN_TTIE_SE2E_Pos)            /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E              FDCAN_TTIE_SE2E_Msk                       /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos          (14U)
+#define FDCAN_TTIE_ELCE_Msk          (0x1UL << FDCAN_TTIE_ELCE_Pos)            /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE              FDCAN_TTIE_ELCE_Msk                       /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos          (15U)
+#define FDCAN_TTIE_IWTE_Msk          (0x1UL << FDCAN_TTIE_IWTE_Pos)            /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE              FDCAN_TTIE_IWTE_Msk                       /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos           (16U)
+#define FDCAN_TTIE_WTE_Msk           (0x1UL << FDCAN_TTIE_WTE_Pos)             /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE               FDCAN_TTIE_WTE_Msk                        /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos           (17U)
+#define FDCAN_TTIE_AWE_Msk           (0x1UL << FDCAN_TTIE_AWE_Pos)             /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE               FDCAN_TTIE_AWE_Msk                        /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos          (18U)
+#define FDCAN_TTIE_CERE_Msk          (0x1UL << FDCAN_TTIE_CERE_Pos)            /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE              FDCAN_TTIE_CERE_Msk                       /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ******************/
+#define FDCAN_TTILS_SBCS_Pos         (0U)
+#define FDCAN_TTILS_SBCS_Msk         (0x1UL << FDCAN_TTILS_SBCS_Pos)           /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS             FDCAN_TTILS_SBCS_Msk                      /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos         (1U)
+#define FDCAN_TTILS_SMCS_Msk         (0x1UL << FDCAN_TTILS_SMCS_Pos)           /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS             FDCAN_TTILS_SMCS_Msk                      /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos         (2U)
+#define FDCAN_TTILS_CSMS_Msk         (0x1UL << FDCAN_TTILS_CSMS_Pos)           /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS             FDCAN_TTILS_CSMS_Msk                      /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos         (3U)
+#define FDCAN_TTILS_SOGS_Msk         (0x1UL << FDCAN_TTILS_SOGS_Pos)           /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS             FDCAN_TTILS_SOGS_Msk                      /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos        (4U)
+#define FDCAN_TTILS_RTMIS_Msk        (0x1UL << FDCAN_TTILS_RTMIS_Pos)          /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS            FDCAN_TTILS_RTMIS_Msk                     /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos        (5U)
+#define FDCAN_TTILS_TTMIS_Msk        (0x1UL << FDCAN_TTILS_TTMIS_Pos)          /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS            FDCAN_TTILS_TTMIS_Msk                     /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos         (6U)
+#define FDCAN_TTILS_SWES_Msk         (0x1UL << FDCAN_TTILS_SWES_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES             FDCAN_TTILS_SWES_Msk                      /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos         (7U)
+#define FDCAN_TTILS_GTWS_Msk         (0x1UL << FDCAN_TTILS_GTWS_Pos)           /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS             FDCAN_TTILS_GTWS_Msk                      /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos         (8U)
+#define FDCAN_TTILS_GTDS_Msk         (0x1UL << FDCAN_TTILS_GTDS_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS             FDCAN_TTILS_GTDS_Msk                      /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos         (9U)
+#define FDCAN_TTILS_GTES_Msk         (0x1UL << FDCAN_TTILS_GTES_Pos)           /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES             FDCAN_TTILS_GTES_Msk                      /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos         (10U)
+#define FDCAN_TTILS_TXUS_Msk         (0x1UL << FDCAN_TTILS_TXUS_Pos)           /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS             FDCAN_TTILS_TXUS_Msk                      /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos         (11U)
+#define FDCAN_TTILS_TXOS_Msk         (0x1UL << FDCAN_TTILS_TXOS_Pos)           /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS             FDCAN_TTILS_TXOS_Msk                      /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos         (12U)
+#define FDCAN_TTILS_SE1S_Msk         (0x1UL << FDCAN_TTILS_SE1S_Pos)           /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S             FDCAN_TTILS_SE1S_Msk                      /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos         (13U)
+#define FDCAN_TTILS_SE2S_Msk         (0x1UL << FDCAN_TTILS_SE2S_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S             FDCAN_TTILS_SE2S_Msk                      /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos         (14U)
+#define FDCAN_TTILS_ELCS_Msk         (0x1UL << FDCAN_TTILS_ELCS_Pos)           /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS             FDCAN_TTILS_ELCS_Msk                      /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos         (15U)
+#define FDCAN_TTILS_IWTS_Msk         (0x1UL << FDCAN_TTILS_IWTS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS             FDCAN_TTILS_IWTS_Msk                      /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos          (16U)
+#define FDCAN_TTILS_WTS_Msk          (0x1UL << FDCAN_TTILS_WTS_Pos)            /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS              FDCAN_TTILS_WTS_Msk                       /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos          (17U)
+#define FDCAN_TTILS_AWS_Msk          (0x1UL << FDCAN_TTILS_AWS_Pos)            /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS              FDCAN_TTILS_AWS_Msk                       /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos         (18U)
+#define FDCAN_TTILS_CERS_Msk         (0x1UL << FDCAN_TTILS_CERS_Pos)           /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS             FDCAN_TTILS_CERS_Msk                      /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ******************/
+#define FDCAN_TTOST_EL_Pos           (0U)
+#define FDCAN_TTOST_EL_Msk           (0x3UL << FDCAN_TTOST_EL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOST_EL               FDCAN_TTOST_EL_Msk                        /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos           (2U)
+#define FDCAN_TTOST_MS_Msk           (0x3UL << FDCAN_TTOST_MS_Pos)             /*!< 0x0000000C */
+#define FDCAN_TTOST_MS               FDCAN_TTOST_MS_Msk                        /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos          (4U)
+#define FDCAN_TTOST_SYS_Msk          (0x3UL << FDCAN_TTOST_SYS_Pos)            /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS              FDCAN_TTOST_SYS_Msk                       /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos         (6U)
+#define FDCAN_TTOST_QGTP_Msk         (0x1UL << FDCAN_TTOST_QGTP_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP             FDCAN_TTOST_QGTP_Msk                      /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos          (7U)
+#define FDCAN_TTOST_QCS_Msk          (0x1UL << FDCAN_TTOST_QCS_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS              FDCAN_TTOST_QCS_Msk                       /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos          (8U)
+#define FDCAN_TTOST_RTO_Msk          (0xFFUL << FDCAN_TTOST_RTO_Pos)           /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO              FDCAN_TTOST_RTO_Msk                       /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos         (22U)
+#define FDCAN_TTOST_WGTD_Msk         (0x1UL << FDCAN_TTOST_WGTD_Pos)           /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD             FDCAN_TTOST_WGTD_Msk                      /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos          (23U)
+#define FDCAN_TTOST_GFI_Msk          (0x1UL << FDCAN_TTOST_GFI_Pos)            /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI              FDCAN_TTOST_GFI_Msk                       /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos          (24U)
+#define FDCAN_TTOST_TMP_Msk          (0x7UL << FDCAN_TTOST_TMP_Pos)            /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP              FDCAN_TTOST_TMP_Msk                       /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos          (27U)
+#define FDCAN_TTOST_GSI_Msk          (0x1UL << FDCAN_TTOST_GSI_Pos)            /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI              FDCAN_TTOST_GSI_Msk                       /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos          (28U)
+#define FDCAN_TTOST_WFE_Msk          (0x1UL << FDCAN_TTOST_WFE_Pos)            /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE              FDCAN_TTOST_WFE_Msk                       /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos          (29U)
+#define FDCAN_TTOST_AWE_Msk          (0x1UL << FDCAN_TTOST_AWE_Pos)            /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE              FDCAN_TTOST_AWE_Msk                       /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos         (30U)
+#define FDCAN_TTOST_WECS_Msk         (0x1UL << FDCAN_TTOST_WECS_Pos)           /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS             FDCAN_TTOST_WECS_Msk                      /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos          (31U)
+#define FDCAN_TTOST_SPL_Msk          (0x1UL << FDCAN_TTOST_SPL_Pos)            /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL              FDCAN_TTOST_SPL_Msk                       /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ******************/
+#define FDCAN_TURNA_NAV_Pos          (0U)
+#define FDCAN_TURNA_NAV_Msk          (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)        /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV              FDCAN_TURNA_NAV_Msk                       /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ******************/
+#define FDCAN_TTLGT_LT_Pos           (0U)
+#define FDCAN_TTLGT_LT_Msk           (0xFFFFUL << FDCAN_TTLGT_LT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT               FDCAN_TTLGT_LT_Msk                        /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos           (16U)
+#define FDCAN_TTLGT_GT_Msk           (0xFFFFUL << FDCAN_TTLGT_GT_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT               FDCAN_TTLGT_GT_Msk                        /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ******************/
+#define FDCAN_TTCTC_CT_Pos           (0U)
+#define FDCAN_TTCTC_CT_Msk           (0xFFFFUL << FDCAN_TTCTC_CT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT               FDCAN_TTCTC_CT_Msk                        /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos           (16U)
+#define FDCAN_TTCTC_CC_Msk           (0x3FUL << FDCAN_TTCTC_CC_Pos)            /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC               FDCAN_TTCTC_CC_Msk                        /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ******************/
+#define FDCAN_TTCPT_CCV_Pos          (0U)
+#define FDCAN_TTCPT_CCV_Msk          (0x3FUL << FDCAN_TTCPT_CCV_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV              FDCAN_TTCPT_CCV_Msk                       /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos          (16U)
+#define FDCAN_TTCPT_SWV_Msk          (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV              FDCAN_TTCPT_SWV_Msk                       /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ******************/
+#define FDCAN_TTCSM_CSM_Pos          (0U)
+#define FDCAN_TTCSM_CSM_Msk          (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM              FDCAN_TTCSM_CSM_Msk                       /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *******************/
+#define FDCAN_TTTS_SWTSEL_Pos        (0U)
+#define FDCAN_TTTS_SWTSEL_Msk        (0x3UL << FDCAN_TTTS_SWTSEL_Pos)          /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL            FDCAN_TTTS_SWTSEL_Msk                     /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos        (4U)
+#define FDCAN_TTTS_EVTSEL_Msk        (0x3UL << FDCAN_TTTS_EVTSEL_Pos)          /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL            FDCAN_TTTS_EVTSEL_Msk                     /*!<Event trigger input selection            */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FDCANCCU (Clock Calibration unit)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ****************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ****************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  ***************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ****************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *****************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *****************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  **********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!< Memory bank enable bit */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!< Address/data multiplexing enable bit */
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!< Memory type */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!< Memory data bus width */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!< Flash access enable */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!< Burst enable bit */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!< Wait signal polarity bit */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!< Wait timing configuration */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!< Write enable bit */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!< Wait enable bit */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!< Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!< Wait signal during asynchronous transfers */
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!< CRAM page size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!< Write burst enable */
+#define FMC_BCRx_CSCOUNT_Pos       (20U)
+#define FMC_BCRx_CSCOUNT_Msk       (0x3UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00300000 */
+#define FMC_BCRx_CSCOUNT           FMC_BCRx_CSCOUNT_Msk                        /*!< Chip Select (CS) counter */
+#define FMC_BCRx_CSCOUNT_0         (0x1UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00100000 */
+#define FMC_BCRx_CSCOUNT_1         (0x2UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00200000 */
+#define FMC_BCRx_NBLSET_Pos        (22U)
+#define FMC_BCRx_NBLSET_Msk        (0x3UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00C00000 */
+#define FMC_BCRx_NBLSET            FMC_BCRx_NBLSET_Msk                         /*!< Byte lane (NBL) setup */
+#define FMC_BCRx_NBLSET_0          (0x1UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00400000 */
+#define FMC_BCRx_NBLSET_1          (0x2UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00800000 */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  **********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!< Address setup phase duration */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!< Address-hold phase duration */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!< Data-phase duration */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!< Bus turnaround phase duration */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!< Clock divide ratio */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!< Data latency for synchronous memory */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!< Access mode */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+#define FMC_BTRx_DATAHLD_Pos       (30U)
+#define FMC_BTRx_DATAHLD_Msk       (0x3UL << FMC_BTRx_DATAHLD_Pos)              /*!< 0xC0000000 */
+#define FMC_BTRx_DATAHLD           FMC_BTRx_DATAHLD_Msk                        /*!< Data Hold phase duration */
+#define FMC_BTRx_DATAHLD_0         (0x1UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x40000000 */
+#define FMC_BTRx_DATAHLD_1         (0x2UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_CFGR register  *****************/
+#define FMC_CFGR_CLKDIV_Pos        (16U)
+#define FMC_CFGR_CLKDIV_Msk        (0xFUL << FMC_CFGR_CLKDIV_Pos)               /*!< 0x000F0000 */
+#define FMC_CFGR_CLKDIV            FMC_CFGR_CLKDIV_Msk                         /*!< Clock divide ratio (for FMC_CLK signal) */
+#define FMC_CFGR_CLKDIV_0          (0x1UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00010000 */
+#define FMC_CFGR_CLKDIV_1          (0x2UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00020000 */
+#define FMC_CFGR_CLKDIV_2          (0x4UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00040000 */
+#define FMC_CFGR_CLKDIV_3          (0x8UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00080000 */
+#define FMC_CFGR_CCLKEN_Pos        (20U)
+#define FMC_CFGR_CCLKEN_Msk        (0x1UL << FMC_CFGR_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_CFGR_CCLKEN            FMC_CFGR_CCLKEN_Msk                         /*!< Continuous clock enable */
+#define FMC_CFGR_BMAP_Pos          (24U)
+#define FMC_CFGR_BMAP_Msk          (0x3UL << FMC_CFGR_BMAP_Pos)                 /*!< 0x03000000 */
+#define FMC_CFGR_BMAP              FMC_CFGR_BMAP_Msk                           /*!< FMC memory region mapping */
+#define FMC_CFGR_BMAP_0            (0x1UL << FMC_CFGR_BMAP_Pos)                /*!< 0x01000000 */
+#define FMC_CFGR_BMAP_1            (0x2UL << FMC_CFGR_BMAP_Pos)                /*!< 0x02000000 */
+#define FMC_CFGR_FMCEN_Pos         (31U)
+#define FMC_CFGR_FMCEN_Msk         (0x1UL << FMC_CFGR_FMCEN_Pos)                /*!< 0x80000000 */
+#define FMC_CFGR_FMCEN             FMC_CFGR_FMCEN_Msk                          /*!< FMC controller enable */
+
+/******************  Bit definition for FMC_PCR register  *********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!< Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!< NAND Flash memory bank enable bit */
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!< Data bus width */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!< ECC computation logic enable bit */
+#define FMC_PCR_ECCALG_Pos         (8U)
+#define FMC_PCR_ECCALG_Msk         (0x1UL << FMC_PCR_ECCALG_Pos)               /*!< 0x00000100 */
+#define FMC_PCR_ECCALG             FMC_PCR_ECCALG_Msk                          /*!< ECC algorithm */
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!< CLE to RE delay */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!< ALE to RE delay */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
+#define FMC_PCR_ECCSS_Pos          (17U)
+#define FMC_PCR_ECCSS_Msk          (0x7UL << FMC_PCR_ECCSS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCSS              FMC_PCR_ECCSS_Msk                           /*!< ECC page size */
+#define FMC_PCR_ECCSS_0            (0x1UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00020000 */
+#define FMC_PCR_ECCSS_1            (0x2UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00040000 */
+#define FMC_PCR_ECCSS_2            (0x4UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00080000 */
+#define FMC_PCR_BCHECC_Pos         (24U)
+#define FMC_PCR_BCHECC_Msk         (0x1UL << FMC_PCR_BCHECC_Pos)                /*!< 0x01000000 */
+#define FMC_PCR_BCHECC             FMC_PCR_BCHECC_Msk                          /*!< BCH error correction capability */
+#define FMC_PCR_WEN_Pos            (25U)
+#define FMC_PCR_WEN_Msk            (0x1UL << FMC_PCR_WEN_Pos)                   /*!< 0x02000000 */
+#define FMC_PCR_WEN                FMC_PCR_WEN_Msk                             /*!< Write enable */
+
+/******************  Bit definition for FMC_SR register  ******************/
+#define FMC_SR_ISOST_Pos           (0U)
+#define FMC_SR_ISOST_Msk           (0x3UL << FMC_SR_ISOST_Pos)                  /*!< 0x00000003 */
+#define FMC_SR_ISOST               FMC_SR_ISOST_Msk                            /*!< FMC isolation state with respect to the AXI interface */
+#define FMC_SR_PEF_Pos             (4U)
+#define FMC_SR_PEF_Msk             (0x1UL << FMC_SR_PEF_Pos)                    /*!< 0x00000010 */
+#define FMC_SR_PEF                 FMC_SR_PEF_Msk                              /*!< Pipe Empty Flag */
+#define FMC_SR_NWRF_Pos            (6U)
+#define FMC_SR_NWRF_Msk            (0x1UL << FMC_SR_NWRF_Pos)                   /*!< 0x00000040 */
+#define FMC_SR_NWRF                FMC_SR_NWRF_Msk                             /*!< NAND write request flag */
+
+/******************  Bit definition for FMC_PMEM register  ********************/
+#define FMC_PMEM_MEMSET_Pos        (0U)
+#define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!< Common memory setup time */
+#define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+#define FMC_PMEM_MEMWAIT_Pos       (8U)
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!< Common memory wait time */
+#define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PMEM_MEMHOLD_Pos       (16U)
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!< Common memory hold time */
+#define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PMEM_MEMHIZ_Pos        (24U)
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!< Common memory databus Hi-Z time */
+#define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ********************/
+#define FMC_PATT_ATTSET_Pos        (0U)
+#define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!< Attribute memory setup time */
+#define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+#define FMC_PATT_ATTWAIT_Pos       (8U)
+#define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!< Attribute memory wait time */
+#define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PATT_ATTHOLD_Pos       (16U)
+#define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!< Attribute memory hold time */
+#define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PATT_ATTHIZ_Pos        (24U)
+#define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!< Attribute memory data bus Hi-Z time */
+#define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_HPR register  ******************/
+#define FMC_HPR_HPR_Pos            (0U)
+#define FMC_HPR_HPR_Msk            (0xFFFFFFFFUL << FMC_HPR_HPR_Pos)            /*!< 0xFFFFFFFF */
+#define FMC_HPR_HPR                FMC_HPR_HPR_Msk                             /*!< Hamming parity result */
+
+/****************  Bit definition for FMC_HECCR register  *****************/
+#define FMC_HECCR_HECC_Pos         (0U)
+#define FMC_HECCR_HECC_Msk         (0xFFFFFFFFUL << FMC_HECCR_HECC_Pos)         /*!< 0xFFFFFFFF */
+#define FMC_HECCR_HECC             FMC_HECCR_HECC_Msk                          /*!< ECC result */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!< Address setup phase duration */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!< Address-hold phase duration */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!< Data-phase duration */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!< Bus turnaround phase duration */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!< Access mode */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
+#define FMC_BWTRx_DATAHLD_Pos      (30U)
+#define FMC_BWTRx_DATAHLD_Msk      (0x3UL << FMC_BWTRx_DATAHLD_Pos)             /*!< 0xC0000000 */
+#define FMC_BWTRx_DATAHLD          FMC_BWTRx_DATAHLD_Msk                       /*!< Data Hold phase duration */
+#define FMC_BWTRx_DATAHLD_0        (0x1UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x40000000 */
+#define FMC_BWTRx_DATAHLD_1        (0x2UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!< Number of column address bits */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000002 */
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!< Number of row address bits */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000008 */
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!< Memory data bus width */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000020 */
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!< Number of internal banks */
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!< CAS latency */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!< Write protection */
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!< SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000800 */
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!< Read pipe */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00004000 */
+#define FMC_SDCRx_SDEN_Pos         (16U)
+#define FMC_SDCRx_SDEN_Msk         (0x1UL << FMC_SDCRx_SDEN_Pos)               /*!< 0x00010000 */
+#define FMC_SDCRx_SDEN             FMC_SDCRx_SDEN_Msk                          /*!< SDRAM device enable */
+#define FMC_SDCRx_SDINIT_Pos       (17U)
+#define FMC_SDCRx_SDINIT_Msk       (0x1UL << FMC_SDCRx_SDINIT_Pos)             /*!< 0x00020000 */
+#define FMC_SDCRx_SDINIT           FMC_SDCRx_SDINIT_Msk                        /*!< SDRAM device initialization */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  **************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!< Load mode register to active */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000008 */
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<Exit self-refresh delay */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000080 */
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!< Self refresh time */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000800 */
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!< Row cycle delay */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00004000 */
+#define FMC_SDTRx_TRC_3            (0x8UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00008000 */
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!< Recovery delay */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00040000 */
+#define FMC_SDTRx_TWR_3            (0x8UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00080000 */
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!< Row precharge delay */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00400000 */
+#define FMC_SDTRx_TRP_3            (0x8UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00800000 */
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!< Row to column delay */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x04000000 */
+#define FMC_SDTRx_TRCD_3           (0x8UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x08000000 */
+
+/******************  Bit definition for FMC_SDCMR register  *******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!< Command mode */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
+#define FMC_SDCMR_DS2_Pos          (3U)
+#define FMC_SDCMR_DS2_Msk          (0x1UL << FMC_SDCMR_DS2_Pos)                /*!< 0x00000008 */
+#define FMC_SDCMR_DS2              FMC_SDCMR_DS2_Msk                           /*!< Command targeting SDRAM device 2 */
+#define FMC_SDCMR_DS1_Pos          (4U)
+#define FMC_SDCMR_DS1_Msk          (0x1UL << FMC_SDCMR_DS1_Pos)                /*!< 0x00000010 */
+#define FMC_SDCMR_DS1              FMC_SDCMR_DS1_Msk                           /*!< Command targeting SDRAM device 1 */
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!< Number of auto-refresh */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x3FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x007FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!< Mode register definition */
+
+/******************  Bit definition for FMC_SDRTR register  *******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!< Clear refresh error flag */
+#define FMC_SDRTR_RFSCNT_Pos       (1U)
+#define FMC_SDRTR_RFSCNT_Msk       (0x1FFFUL << FMC_SDRTR_RFSCNT_Pos)          /*!< 0x00003FFE */
+#define FMC_SDRTR_RFSCNT           FMC_SDRTR_RFSCNT_Msk                        /*!< Refresh timer count */
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!< RES interrupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ********************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!< Refresh error flag */
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!< Status mode for bank 1 */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!< Status mode for bank 2 */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
+#define FMC_SDSR_CMDOK_Pos         (15U)
+#define FMC_SDSR_CMDOK_Msk         (0x1UL << FMC_SDSR_CMDOK_Pos)               /*!< 0x00004000 */
+#define FMC_SDSR_CMDOK             FMC_SDSR_CMDOK_Msk                          /*!< Previous command status */
+
+/*******************  Bit definition for FMC_IER register  ********************/
+#define FMC_IER_IREE_Pos              (0U)
+#define FMC_IER_IREE_Msk              (0x1UL << FMC_IER_IREE_Pos)               /*!< 0x00000001 */
+#define FMC_IER_IREE                  FMC_IER_IREE_Msk                         /*!< Interrupt rising edge detection enable bit */
+#define FMC_IER_IHLE_Pos              (1U)
+#define FMC_IER_IHLE_Msk              (0x1UL << FMC_IER_IHLE_Pos)               /*!< 0x00000002 */
+#define FMC_IER_IHLE                  FMC_IER_IHLE_Msk                         /*!< Interrupt high-level detection enable bit */
+#define FMC_IER_IFEE_Pos              (2U)
+#define FMC_IER_IFEE_Msk              (0x1UL << FMC_IER_IFEE_Pos)               /*!< 0x00000004 */
+#define FMC_IER_IFEE                  FMC_IER_IFEE_Msk                         /*!< Interrupt falling edge detection enable bit */
+
+/*******************  Bit definition for FMC_ISR register  ********************/
+#define FMC_ISR_IREF_Pos              (0U)
+#define FMC_ISR_IREF_Msk              (0x1UL << FMC_ISR_IREF_Pos)               /*!< 0x00000001 */
+#define FMC_ISR_IREF                  FMC_ISR_IREF_Msk                         /*!< Interrupt rising edge flag */
+#define FMC_ISR_IHLF_Pos              (1U)
+#define FMC_ISR_IHLF_Msk              (0x1UL << FMC_ISR_IHLF_Pos)               /*!< 0x00000002 */
+#define FMC_ISR_IHLF                  FMC_ISR_IHLF_Msk                         /*!< Interrupt high-level flag */
+#define FMC_ISR_IFEF_Pos              (2U)
+#define FMC_ISR_IFEF_Msk              (0x1UL << FMC_ISR_IFEF_Pos)               /*!< 0x00000004 */
+#define FMC_ISR_IFEF                  FMC_ISR_IFEF_Msk                         /*!< Interrupt falling edge flag */
+
+/*******************  Bit definition for FMC_ICR register  ********************/
+#define FMC_ICR_CIREF_Pos             (0U)
+#define FMC_ICR_CIREF_Msk             (0x1UL << FMC_ICR_CIREF_Pos)              /*!< 0x00000001 */
+#define FMC_ICR_CIREF                 FMC_ICR_CIREF_Msk                        /*!< Clear Interrupt rising edge flag */
+#define FMC_ICR_CIHLF_Pos             (1U)
+#define FMC_ICR_CIHLF_Msk             (0x1UL << FMC_ICR_CIHLF_Pos)              /*!< 0x00000002 */
+#define FMC_ICR_CIHLF                 FMC_ICR_CIHLF_Msk                        /*!< Clear Interrupt high-level flag */
+#define FMC_ICR_CIFEF_Pos             (2U)
+#define FMC_ICR_CIFEF_Msk             (0x1UL << FMC_ICR_CIFEF_Pos)              /*!< 0x00000004 */
+#define FMC_ICR_CIFEF                 FMC_ICR_CIFEF_Msk                        /*!< Clear Interrupt falling edge flag */
+
+/****************  Bit definition for FMC_CSQCR register  *****************/
+#define FMC_CSQCR_CSQSTART_Pos        (0U)
+#define FMC_CSQCR_CSQSTART_Msk        (0x1UL << FMC_CSQCR_CSQSTART_Pos)         /*!< 0x00000001 */
+#define FMC_CSQCR_CSQSTART            FMC_CSQCR_CSQSTART_Msk                   /*!< Command Sequencer Enable */
+
+/***************  Bit definition for FMC_CSQCFGR1 register  ***************/
+#define FMC_CSQCFGR1_CMD2EN_Pos       (1U)
+#define FMC_CSQCFGR1_CMD2EN_Msk       (0x1UL << FMC_CSQCFGR1_CMD2EN_Pos)        /*!< 0x00000002 */
+#define FMC_CSQCFGR1_CMD2EN           FMC_CSQCFGR1_CMD2EN_Msk                  /*!< Command cycle 2 Enable */
+#define FMC_CSQCFGR1_DMADEN_Pos       (2U)
+#define FMC_CSQCFGR1_DMADEN_Msk       (0x1UL << FMC_CSQCFGR1_DMADEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR1_DMADEN           FMC_CSQCFGR1_DMADEN_Msk                  /*!< Command sequencer DMA request data enable */
+#define FMC_CSQCFGR1_ACYNBR_Pos       (4U)
+#define FMC_CSQCFGR1_ACYNBR_Msk       (0x7UL << FMC_CSQCFGR1_ACYNBR_Pos)        /*!< 0x00000070 */
+#define FMC_CSQCFGR1_ACYNBR           FMC_CSQCFGR1_ACYNBR_Msk                  /*!< Address Cycle number */
+#define FMC_CSQCFGR1_CMD1_Pos         (8U)
+#define FMC_CSQCFGR1_CMD1_Msk         (0xFFUL << FMC_CSQCFGR1_CMD1_Pos)         /*!< 0x0000FF00 */
+#define FMC_CSQCFGR1_CMD1             FMC_CSQCFGR1_CMD1_Msk                    /*!< Command 1 sequencer */
+#define FMC_CSQCFGR1_CMD2_Pos         (16U)
+#define FMC_CSQCFGR1_CMD2_Msk         (0xFFUL << FMC_CSQCFGR1_CMD2_Pos)         /*!< 0x00FF0000 */
+#define FMC_CSQCFGR1_CMD2             FMC_CSQCFGR1_CMD2_Msk                    /*!< Command 2 sequencer */
+#define FMC_CSQCFGR1_CMD1T_Pos        (24U)
+#define FMC_CSQCFGR1_CMD1T_Msk        (0x1UL << FMC_CSQCFGR1_CMD1T_Pos)         /*!< 0x01000000 */
+#define FMC_CSQCFGR1_CMD1T            FMC_CSQCFGR1_CMD1T_Msk                   /*!< Command 1 Sequencer timings */
+#define FMC_CSQCFGR1_CMD2T_Pos        (25U)
+#define FMC_CSQCFGR1_CMD2T_Msk        (0x1UL << FMC_CSQCFGR1_CMD2T_Pos)         /*!< 0x02000000 */
+#define FMC_CSQCFGR1_CMD2T            FMC_CSQCFGR1_CMD2T_Msk                   /*!< Command 2 Sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR2 register  ***************/
+#define FMC_CSQCFGR2_SQSDTEN_Pos      (0U)
+#define FMC_CSQCFGR2_SQSDTEN_Msk      (0x1UL << FMC_CSQCFGR2_SQSDTEN_Pos)       /*!< 0x00000001 */
+#define FMC_CSQCFGR2_SQSDTEN          FMC_CSQCFGR2_SQSDTEN_Msk                 /*!< Sequencer spare data transfer enable */
+#define FMC_CSQCFGR2_RCMD2EN_Pos      (1U)
+#define FMC_CSQCFGR2_RCMD2EN_Msk      (0x1UL << FMC_CSQCFGR2_RCMD2EN_Pos)       /*!< 0x00000002 */
+#define FMC_CSQCFGR2_RCMD2EN          FMC_CSQCFGR2_RCMD2EN_Msk                 /*!< Random Command 2 sequencer enable */
+#define FMC_CSQCFGR2_DMASEN_Pos       (2U)
+#define FMC_CSQCFGR2_DMASEN_Msk       (0x1UL << FMC_CSQCFGR2_DMASEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR2_DMASEN           FMC_CSQCFGR2_DMASEN_Msk                  /*!< Command sequencer DMA request decoding status enable */
+#define FMC_CSQCFGR2_RCMD1_Pos        (8U)
+#define FMC_CSQCFGR2_RCMD1_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD1_Pos)        /*!< 0x0000FF00 */
+#define FMC_CSQCFGR2_RCMD1            FMC_CSQCFGR2_RCMD1_Msk                   /*!< Random Command 1 sequencer */
+#define FMC_CSQCFGR2_RCMD2_Pos        (16U)
+#define FMC_CSQCFGR2_RCMD2_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD2_Pos)        /*!< 0x00FF0000 */
+#define FMC_CSQCFGR2_RCMD2            FMC_CSQCFGR2_RCMD2_Msk                   /*!< Random Command 2 sequencer */
+#define FMC_CSQCFGR2_RCMD1T_Pos       (24U)
+#define FMC_CSQCFGR2_RCMD1T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD1T_Pos)        /*!< 0x01000000 */
+#define FMC_CSQCFGR2_RCMD1T           FMC_CSQCFGR2_RCMD1T_Msk                  /*!< Command 1 sequencer timings */
+#define FMC_CSQCFGR2_RCMD2T_Pos       (25U)
+#define FMC_CSQCFGR2_RCMD2T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD2T_Pos)        /*!< 0x02000000 */
+#define FMC_CSQCFGR2_RCMD2T           FMC_CSQCFGR2_RCMD2T_Msk                  /*!< Command 1 sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR3 register  ***************/
+#define FMC_CSQCFGR3_SNBR_Pos         (8U)
+#define FMC_CSQCFGR3_SNBR_Msk         (0x3FUL << FMC_CSQCFGR3_SNBR_Pos)         /*!< 0x00003F00 */
+#define FMC_CSQCFGR3_SNBR             FMC_CSQCFGR3_SNBR_Msk                    /*!< Number of sectors to be read/written */
+#define FMC_CSQCFGR3_AC1T_Pos         (16U)
+#define FMC_CSQCFGR3_AC1T_Msk         (0x1UL << FMC_CSQCFGR3_AC1T_Pos)          /*!< 0x00010000 */
+#define FMC_CSQCFGR3_AC1T             FMC_CSQCFGR3_AC1T_Msk                    /*!< Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_AC2T_Pos         (17U)
+#define FMC_CSQCFGR3_AC2T_Msk         (0x1UL << FMC_CSQCFGR3_AC2T_Pos)          /*!< 0x00020000 */
+#define FMC_CSQCFGR3_AC2T             FMC_CSQCFGR3_AC2T_Msk                    /*!< Address cycle 2 sequencer timings */
+#define FMC_CSQCFGR3_AC3T_Pos         (18U)
+#define FMC_CSQCFGR3_AC3T_Msk         (0x1UL << FMC_CSQCFGR3_AC3T_Pos)          /*!< 0x00040000 */
+#define FMC_CSQCFGR3_AC3T             FMC_CSQCFGR3_AC3T_Msk                    /*!< Address cycle 3 sequencer timings */
+#define FMC_CSQCFGR3_AC4T_Pos         (19U)
+#define FMC_CSQCFGR3_AC4T_Msk         (0x1UL << FMC_CSQCFGR3_AC4T_Pos)          /*!< 0x00080000 */
+#define FMC_CSQCFGR3_AC4T             FMC_CSQCFGR3_AC4T_Msk                    /*!< Address cycle 4sequencer timings */
+#define FMC_CSQCFGR3_AC5T_Pos         (20U)
+#define FMC_CSQCFGR3_AC5T_Msk         (0x1UL << FMC_CSQCFGR3_AC5T_Pos)          /*!< 0x00100000 */
+#define FMC_CSQCFGR3_AC5T             FMC_CSQCFGR3_AC5T_Msk                    /*!< Address cycle 5 sequencer timings */
+#define FMC_CSQCFGR3_SDT_Pos          (21U)
+#define FMC_CSQCFGR3_SDT_Msk          (0x1UL << FMC_CSQCFGR3_SDT_Pos)           /*!< 0x00200000 */
+#define FMC_CSQCFGR3_SDT              FMC_CSQCFGR3_SDT_Msk                     /*!< Spare data transfer sequencer timings */
+#define FMC_CSQCFGR3_RAC1T_Pos        (22U)
+#define FMC_CSQCFGR3_RAC1T_Msk        (0x1UL << FMC_CSQCFGR3_RAC1T_Pos)         /*!< 0x00400000 */
+#define FMC_CSQCFGR3_RAC1T            FMC_CSQCFGR3_RAC1T_Msk                   /*!< Random Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_RAC2T_Pos        (23U)
+#define FMC_CSQCFGR3_RAC2T_Msk        (0x1UL << FMC_CSQCFGR3_RAC2T_Pos)         /*!< 0x00800000 */
+#define FMC_CSQCFGR3_RAC2T            FMC_CSQCFGR3_RAC2T_Msk                   /*!< Random Address cycle 2 sequencer timings */
+
+/****************  Bit definition for FMC_CSQAR1 register  ****************/
+#define FMC_CSQAR1_ADDC1_Pos          (0U)
+#define FMC_CSQAR1_ADDC1_Msk          (0xFFUL << FMC_CSQAR1_ADDC1_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR1_ADDC1              FMC_CSQAR1_ADDC1_Msk                     /*!< Address Cycle 1 */
+#define FMC_CSQAR1_ADDC2_Pos          (8U)
+#define FMC_CSQAR1_ADDC2_Msk          (0xFFUL << FMC_CSQAR1_ADDC2_Pos)          /*!< 0x0000FF00 */
+#define FMC_CSQAR1_ADDC2              FMC_CSQAR1_ADDC2_Msk                     /*!< Address Cycle 2 */
+#define FMC_CSQAR1_ADDC3_Pos          (16U)
+#define FMC_CSQAR1_ADDC3_Msk          (0xFFUL << FMC_CSQAR1_ADDC3_Pos)          /*!< 0x00FF0000 */
+#define FMC_CSQAR1_ADDC3              FMC_CSQAR1_ADDC3_Msk                     /*!< Address Cycle 3 */
+#define FMC_CSQAR1_ADDC4_Pos          (24U)
+#define FMC_CSQAR1_ADDC4_Msk          (0xFFUL << FMC_CSQAR1_ADDC4_Pos)          /*!< 0xFF000000 */
+#define FMC_CSQAR1_ADDC4              FMC_CSQAR1_ADDC4_Msk                     /*!< Address Cycle 4 */
+
+/****************  Bit definition for FMC_CSQAR2 register  ****************/
+#define FMC_CSQAR2_ADDC5_Pos          (0U)
+#define FMC_CSQAR2_ADDC5_Msk          (0xFFUL << FMC_CSQAR2_ADDC5_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR2_ADDC5              FMC_CSQAR2_ADDC5_Msk                     /*!< Address Cycle 5 */
+#define FMC_CSQAR2_SAO_Pos            (16U)
+#define FMC_CSQAR2_SAO_Msk            (0xFFFFUL << FMC_CSQAR2_SAO_Pos)          /*!< 0xFFFF0000 */
+#define FMC_CSQAR2_SAO                FMC_CSQAR2_SAO_Msk                       /*!< Spare Area Address Offset. */
+
+/****************  Bit definition for FMC_CSQIER register  ****************/
+#define FMC_CSQIER_TCIE_Pos           (0U)
+#define FMC_CSQIER_TCIE_Msk           (0x1UL << FMC_CSQIER_TCIE_Pos)            /*!< 0x00000001 */
+#define FMC_CSQIER_TCIE               FMC_CSQIER_TCIE_Msk                      /*!< Transfer Complete Interrupt enable */
+#define FMC_CSQIER_SCIE_Pos           (1U)
+#define FMC_CSQIER_SCIE_Msk           (0x1UL << FMC_CSQIER_SCIE_Pos)            /*!< 0x00000002 */
+#define FMC_CSQIER_SCIE               FMC_CSQIER_SCIE_Msk                      /*!< Sector Complete interrupt enable */
+#define FMC_CSQIER_SEIE_Pos           (2U)
+#define FMC_CSQIER_SEIE_Msk           (0x1UL << FMC_CSQIER_SEIE_Pos)            /*!< 0x00000004 */
+#define FMC_CSQIER_SEIE               FMC_CSQIER_SEIE_Msk                      /*!< Sector Error interrupt enable */
+#define FMC_CSQIER_SUEIE_Pos          (3U)
+#define FMC_CSQIER_SUEIE_Msk          (0x1UL << FMC_CSQIER_SUEIE_Pos)           /*!< 0x00000008 */
+#define FMC_CSQIER_SUEIE              FMC_CSQIER_SUEIE_Msk                     /*!< Sector Uncorrectable Error interrupt enable */
+#define FMC_CSQIER_CMDTCIE_Pos        (4U)
+#define FMC_CSQIER_CMDTCIE_Msk        (0x1UL << FMC_CSQIER_CMDTCIE_Pos)         /*!< 0x00000010 */
+#define FMC_CSQIER_CMDTCIE            FMC_CSQIER_CMDTCIE_Msk                   /*!< Command Transfer Complete interrupt enable */
+
+/****************  Bit definition for FMC_CSQISR register  ****************/
+#define FMC_CSQISR_TCF_Pos            (0U)
+#define FMC_CSQISR_TCF_Msk            (0x1UL << FMC_CSQISR_TCF_Pos)             /*!< 0x00000001 */
+#define FMC_CSQISR_TCF                FMC_CSQISR_TCF_Msk                       /*!< Transfer Complete flag */
+#define FMC_CSQISR_SCF_Pos            (1U)
+#define FMC_CSQISR_SCF_Msk            (0x1UL << FMC_CSQISR_SCF_Pos)             /*!< 0x00000002 */
+#define FMC_CSQISR_SCF                FMC_CSQISR_SCF_Msk                       /*!< Sector Complete flag */
+#define FMC_CSQISR_SEF_Pos            (2U)
+#define FMC_CSQISR_SEF_Msk            (0x1UL << FMC_CSQISR_SEF_Pos)             /*!< 0x00000004 */
+#define FMC_CSQISR_SEF                FMC_CSQISR_SEF_Msk                       /*!< Sector Error flag */
+#define FMC_CSQISR_SUEF_Pos           (3U)
+#define FMC_CSQISR_SUEF_Msk           (0x1UL << FMC_CSQISR_SUEF_Pos)            /*!< 0x00000008 */
+#define FMC_CSQISR_SUEF               FMC_CSQISR_SUEF_Msk                      /*!< Sector Uncorrectable Error flag */
+#define FMC_CSQISR_CMDTCF_Pos         (4U)
+#define FMC_CSQISR_CMDTCF_Msk         (0x1UL << FMC_CSQISR_CMDTCF_Pos)          /*!< 0x00000010 */
+#define FMC_CSQISR_CMDTCF             FMC_CSQISR_CMDTCF_Msk                    /*!< Command Transfer Complete flag */
+
+/****************  Bit definition for FMC_CSQICR register  ****************/
+#define FMC_CSQICR_CTCF_Pos           (0U)
+#define FMC_CSQICR_CTCF_Msk           (0x1UL << FMC_CSQICR_CTCF_Pos)            /*!< 0x00000001 */
+#define FMC_CSQICR_CTCF               FMC_CSQICR_CTCF_Msk                      /*!< Clear Transfer Complete flag */
+#define FMC_CSQICR_CSCF_Pos           (1U)
+#define FMC_CSQICR_CSCF_Msk           (0x1UL << FMC_CSQICR_CSCF_Pos)            /*!< 0x00000002 */
+#define FMC_CSQICR_CSCF               FMC_CSQICR_CSCF_Msk                      /*!< Clear Sector Complete flag */
+#define FMC_CSQICR_CSEF_Pos           (2U)
+#define FMC_CSQICR_CSEF_Msk           (0x1UL << FMC_CSQICR_CSEF_Pos)            /*!< 0x00000004 */
+#define FMC_CSQICR_CSEF               FMC_CSQICR_CSEF_Msk                      /*!< Clear Sector Error flag */
+#define FMC_CSQICR_CSUEF_Pos          (3U)
+#define FMC_CSQICR_CSUEF_Msk          (0x1UL << FMC_CSQICR_CSUEF_Pos)           /*!< 0x00000008 */
+#define FMC_CSQICR_CSUEF              FMC_CSQICR_CSUEF_Msk                     /*!< Clear Sector uncorrectable Error flag */
+#define FMC_CSQICR_CCMDTCF_Pos        (4U)
+#define FMC_CSQICR_CCMDTCF_Msk        (0x1UL << FMC_CSQICR_CCMDTCF_Pos)         /*!< 0x00000010 */
+#define FMC_CSQICR_CCMDTCF            FMC_CSQICR_CCMDTCF_Msk                   /*!< Clear Command Transfer Complete flag */
+
+/***************  Bit definition for FMC_CSQEMSR register  ****************/
+#define FMC_CSQEMSR_SEM_Pos           (0U)
+#define FMC_CSQEMSR_SEM_Msk           (0xFFFFUL << FMC_CSQEMSR_SEM_Pos)         /*!< 0x0000FFFF */
+#define FMC_CSQEMSR_SEM               FMC_CSQEMSR_SEM_Msk                      /*!< Sector Error mapping */
+
+/****************  Bit definition for FMC_BCHIER register  ****************/
+#define FMC_BCHIER_DUEIE_Pos          (0U)
+#define FMC_BCHIER_DUEIE_Msk          (0x1UL << FMC_BCHIER_DUEIE_Pos)           /*!< 0x00000001 */
+#define FMC_BCHIER_DUEIE              FMC_BCHIER_DUEIE_Msk                     /*!< Decoder Uncorrectable Errors Interrupt enable */
+#define FMC_BCHIER_DERIE_Pos          (1U)
+#define FMC_BCHIER_DERIE_Msk          (0x1UL << FMC_BCHIER_DERIE_Pos)           /*!< 0x00000002 */
+#define FMC_BCHIER_DERIE              FMC_BCHIER_DERIE_Msk                     /*!< Decoder Error Ready Interrupt enable */
+#define FMC_BCHIER_DEFIE_Pos          (2U)
+#define FMC_BCHIER_DEFIE_Msk          (0x1UL << FMC_BCHIER_DEFIE_Pos)           /*!< 0x00000004 */
+#define FMC_BCHIER_DEFIE              FMC_BCHIER_DEFIE_Msk                     /*!< Decoder Error Found Interrupt enable */
+#define FMC_BCHIER_DSRIE_Pos          (3U)
+#define FMC_BCHIER_DSRIE_Msk          (0x1UL << FMC_BCHIER_DSRIE_Pos)           /*!< 0x00000008 */
+#define FMC_BCHIER_DSRIE              FMC_BCHIER_DSRIE_Msk                     /*!< Decoder Syndrome Ready Interrupt enable */
+#define FMC_BCHIER_EPBRIE_Pos         (4U)
+#define FMC_BCHIER_EPBRIE_Msk         (0x1UL << FMC_BCHIER_EPBRIE_Pos)          /*!< 0x00000010 */
+#define FMC_BCHIER_EPBRIE             FMC_BCHIER_EPBRIE_Msk                    /*!< Decoder Parity Bits Ready Interrupt enable */
+
+/****************  Bit definition for FMC_BCHISR register  ****************/
+#define FMC_BCHISR_DUEF_Pos           (0U)
+#define FMC_BCHISR_DUEF_Msk           (0x1UL << FMC_BCHISR_DUEF_Pos)            /*!< 0x00000001 */
+#define FMC_BCHISR_DUEF               FMC_BCHISR_DUEF_Msk                      /*!< Decoder Uncorrectable Errors flag */
+#define FMC_BCHISR_DERF_Pos           (1U)
+#define FMC_BCHISR_DERF_Msk           (0x1UL << FMC_BCHISR_DERF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHISR_DERF               FMC_BCHISR_DERF_Msk                      /*!< Decoder Error Ready flag */
+#define FMC_BCHISR_DEFF_Pos           (2U)
+#define FMC_BCHISR_DEFF_Msk           (0x1UL << FMC_BCHISR_DEFF_Pos)            /*!< 0x00000004 */
+#define FMC_BCHISR_DEFF               FMC_BCHISR_DEFF_Msk                      /*!< Decoder Error Found flag */
+#define FMC_BCHISR_DSRF_Pos           (3U)
+#define FMC_BCHISR_DSRF_Msk           (0x1UL << FMC_BCHISR_DSRF_Pos)            /*!< 0x00000008 */
+#define FMC_BCHISR_DSRF               FMC_BCHISR_DSRF_Msk                      /*!< Decoder Syndrome Ready flag */
+#define FMC_BCHISR_EPBRF_Pos          (4U)
+#define FMC_BCHISR_EPBRF_Msk          (0x1UL << FMC_BCHISR_EPBRF_Pos)           /*!< 0x00000010 */
+#define FMC_BCHISR_EPBRF              FMC_BCHISR_EPBRF_Msk                     /*!< Encoder Parity Bits Ready flag */
+
+/****************  Bit definition for FMC_BCHICR register  ****************/
+#define FMC_BCHICR_CDUEF_Pos          (0U)
+#define FMC_BCHICR_CDUEF_Msk          (0x1UL << FMC_BCHICR_CDUEF_Pos)           /*!< 0x00000001 */
+#define FMC_BCHICR_CDUEF              FMC_BCHICR_CDUEF_Msk                     /*!< Clear Decoder Uncorrectable Error flag */
+#define FMC_BCHICR_CDERF_Pos          (1U)
+#define FMC_BCHICR_CDERF_Msk          (0x1UL << FMC_BCHICR_CDERF_Pos)           /*!< 0x00000002 */
+#define FMC_BCHICR_CDERF              FMC_BCHICR_CDERF_Msk                     /*!< Clear Decoder Error ready flag */
+#define FMC_BCHICR_CDEFF_Pos          (2U)
+#define FMC_BCHICR_CDEFF_Msk          (0x1UL << FMC_BCHICR_CDEFF_Pos)           /*!< 0x00000004 */
+#define FMC_BCHICR_CDEFF              FMC_BCHICR_CDEFF_Msk                     /*!< Clear Decoder Error Found flag */
+#define FMC_BCHICR_CDSRF_Pos          (3U)
+#define FMC_BCHICR_CDSRF_Msk          (0x1UL << FMC_BCHICR_CDSRF_Pos)           /*!< 0x00000008 */
+#define FMC_BCHICR_CDSRF              FMC_BCHICR_CDSRF_Msk                     /*!< Clear Decoder Syndrome Ready flag */
+#define FMC_BCHICR_CEPBRF_Pos         (4U)
+#define FMC_BCHICR_CEPBRF_Msk         (0x1UL << FMC_BCHICR_CEPBRF_Pos)          /*!< 0x00000010 */
+#define FMC_BCHICR_CEPBRF             FMC_BCHICR_CEPBRF_Msk                    /*!< Clear Encoder Parity Bits Ready flag */
+
+/***************  Bit definition for FMC_BCHPBR1 register  ****************/
+#define FMC_BCHPBR1_BCHPB_Pos         (0U)
+#define FMC_BCHPBR1_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR1_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR1_BCHPB             FMC_BCHPBR1_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR2 register  ****************/
+#define FMC_BCHPBR2_BCHPB_Pos         (0U)
+#define FMC_BCHPBR2_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR2_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR2_BCHPB             FMC_BCHPBR2_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR3 register  ****************/
+#define FMC_BCHPBR3_BCHPB_Pos         (0U)
+#define FMC_BCHPBR3_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR3_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR3_BCHPB             FMC_BCHPBR3_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR4 register  ****************/
+#define FMC_BCHPBR4_BCHPB_Pos         (0U)
+#define FMC_BCHPBR4_BCHPB_Msk         (0xFFUL << FMC_BCHPBR4_BCHPB_Pos)         /*!< 0x000000FF */
+#define FMC_BCHPBR4_BCHPB             FMC_BCHPBR4_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHDSR0 register  ****************/
+#define FMC_BCHDSR0_DUE_Pos           (0U)
+#define FMC_BCHDSR0_DUE_Msk           (0x1UL << FMC_BCHDSR0_DUE_Pos)            /*!< 0x00000001 */
+#define FMC_BCHDSR0_DUE               FMC_BCHDSR0_DUE_Msk                      /*!< Decoder uncorrectable error */
+#define FMC_BCHDSR0_DEF_Pos           (1U)
+#define FMC_BCHDSR0_DEF_Msk           (0x1UL << FMC_BCHDSR0_DEF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHDSR0_DEF               FMC_BCHDSR0_DEF_Msk                      /*!< Decoder error found */
+#define FMC_BCHDSR0_DEN_Pos           (4U)
+#define FMC_BCHDSR0_DEN_Msk           (0xFUL << FMC_BCHDSR0_DEN_Pos)            /*!< 0x000000F0 */
+#define FMC_BCHDSR0_DEN               FMC_BCHDSR0_DEN_Msk                      /*!< Decoder error number */
+
+/***************  Bit definition for FMC_BCHDSR1 register  ****************/
+#define FMC_BCHDSR1_EBP1_Pos          (0U)
+#define FMC_BCHDSR1_EBP1_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP1_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR1_EBP1              FMC_BCHDSR1_EBP1_Msk                     /*!< Error bit position for error number 1 */
+#define FMC_BCHDSR1_EBP2_Pos          (16U)
+#define FMC_BCHDSR1_EBP2_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP2_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR1_EBP2              FMC_BCHDSR1_EBP2_Msk                     /*!< Error bit position for error number 2 */
+
+/***************  Bit definition for FMC_BCHDSR2 register  ****************/
+#define FMC_BCHDSR2_EBP3_Pos          (0U)
+#define FMC_BCHDSR2_EBP3_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP3_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR2_EBP3              FMC_BCHDSR2_EBP3_Msk                     /*!< Error bit position for error number 3 */
+#define FMC_BCHDSR2_EBP4_Pos          (16U)
+#define FMC_BCHDSR2_EBP4_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP4_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR2_EBP4              FMC_BCHDSR2_EBP4_Msk                     /*!< Error bit position for error number 4 */
+
+/***************  Bit definition for FMC_BCHDSR3 register  ****************/
+#define FMC_BCHDSR3_EBP5_Pos          (0U)
+#define FMC_BCHDSR3_EBP5_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP5_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR3_EBP5              FMC_BCHDSR3_EBP5_Msk                     /*!< Error bit position for error number 5 */
+#define FMC_BCHDSR3_EBP6_Pos          (16U)
+#define FMC_BCHDSR3_EBP6_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP6_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR3_EBP6              FMC_BCHDSR3_EBP6_Msk                     /*!< Error bit position for error number 6 */
+
+/***************  Bit definition for FMC_BCHDSR4 register  ****************/
+#define FMC_BCHDSR4_EBP7_Pos          (0U)
+#define FMC_BCHDSR4_EBP7_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP7_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR4_EBP7              FMC_BCHDSR4_EBP7_Msk                     /*!< Error bit position for error number 7 */
+#define FMC_BCHDSR4_EBP8_Pos          (16U)
+#define FMC_BCHDSR4_EBP8_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP8_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR4_EBP8              FMC_BCHDSR4_EBP8_Msk                     /*!< Error bit position for error number 8 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic MMU (GFXMMU)                                 */
+/*                                                                            */
+/******************************************************************************/
+/****************** Bits definition for GFXMMU_CR register ********************/
+#define GFXMMU_CR_B0OIE_Pos                (0U)
+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)      /*!< 0x00000001 */
+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */
+#define GFXMMU_CR_B1OIE_Pos                (1U)
+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)      /*!< 0x00000002 */
+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */
+#define GFXMMU_CR_B2OIE_Pos                (2U)
+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)      /*!< 0x00000004 */
+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */
+#define GFXMMU_CR_B3OIE_Pos                (3U)
+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)      /*!< 0x00000008 */
+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */
+#define GFXMMU_CR_AMEIE_Pos                (4U)
+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)      /*!< 0x00000010 */
+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */
+#define GFXMMU_CR_BS_Pos                   (6U)
+#define GFXMMU_CR_BS_Msk                   (0x1UL << GFXMMU_CR_BS_Pos)         /*!< 0x00000040 */
+#define GFXMMU_CR_BS                       GFXMMU_CR_BS_Msk                    /*!< Block size */
+#define GFXMMU_CR_ATE_Pos                  (15U)
+#define GFXMMU_CR_ATE_Msk                  (0x1UL << GFXMMU_CR_ATE_Pos)        /*!< 0x00008000 */
+#define GFXMMU_CR_ATE                      GFXMMU_CR_ATE_Msk                   /*!< Address translation enable */
+#define GFXMMU_CR_B0PE_Pos                 (24U)
+#define GFXMMU_CR_B0PE_Msk                 (0x1UL << GFXMMU_CR_B0PE_Pos)       /*!< 0x01000000 */
+#define GFXMMU_CR_B0PE                     GFXMMU_CR_B0PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B0PM_Pos                 (25U)
+#define GFXMMU_CR_B0PM_Msk                 (0x1UL << GFXMMU_CR_B0PM_Pos)       /*!< 0x02000000 */
+#define GFXMMU_CR_B0PM                     GFXMMU_CR_B0PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B1PE_Pos                 (26U)
+#define GFXMMU_CR_B1PE_Msk                 (0x1UL << GFXMMU_CR_B1PE_Pos)       /*!< 0x04000000 */
+#define GFXMMU_CR_B1PE                     GFXMMU_CR_B1PE_Msk                  /*!< Buffer 1 packing enable */
+#define GFXMMU_CR_B1PM_Pos                 (27U)
+#define GFXMMU_CR_B1PM_Msk                 (0x1UL << GFXMMU_CR_B1PM_Pos)       /*!< 0x08000000 */
+#define GFXMMU_CR_B1PM                     GFXMMU_CR_B1PM_Msk                  /*!< Buffer 1 packing mode */
+#define GFXMMU_CR_B2PE_Pos                 (28U)
+#define GFXMMU_CR_B2PE_Msk                 (0x1UL << GFXMMU_CR_B2PE_Pos)       /*!< 0x10000000 */
+#define GFXMMU_CR_B2PE                     GFXMMU_CR_B2PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B2PM_Pos                 (29U)
+#define GFXMMU_CR_B2PM_Msk                 (0x1UL << GFXMMU_CR_B2PM_Pos)       /*!< 0x20000000 */
+#define GFXMMU_CR_B2PM                     GFXMMU_CR_B2PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B3PE_Pos                 (30U)
+#define GFXMMU_CR_B3PE_Msk                 (0x1UL << GFXMMU_CR_B3PE_Pos)       /*!< 0x40000000 */
+#define GFXMMU_CR_B3PE                     GFXMMU_CR_B3PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B3PM_Pos                 (31U)
+#define GFXMMU_CR_B3PM_Msk                 (0x1UL << GFXMMU_CR_B3PM_Pos)       /*!< 0x80000000 */
+#define GFXMMU_CR_B3PM                     GFXMMU_CR_B3PM_Msk                  /*!< Buffer 0 packing mode */
+
+/****************** Bits definition for GFXMMU_SR register ********************/
+#define GFXMMU_SR_B0OF_Pos                 (0U)
+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)       /*!< 0x00000001 */
+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */
+#define GFXMMU_SR_B1OF_Pos                 (1U)
+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)       /*!< 0x00000002 */
+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */
+#define GFXMMU_SR_B2OF_Pos                 (2U)
+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)       /*!< 0x00000004 */
+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */
+#define GFXMMU_SR_B3OF_Pos                 (3U)
+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)       /*!< 0x00000008 */
+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */
+#define GFXMMU_SR_AMEF_Pos                 (4U)
+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)       /*!< 0x00000010 */
+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AXI master error flag */
+
+/****************** Bits definition for GFXMMU_FCR register *******************/
+#define GFXMMU_FCR_CB0OF_Pos               (0U)
+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)     /*!< 0x00000001 */
+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */
+#define GFXMMU_FCR_CB1OF_Pos               (1U)
+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)     /*!< 0x00000002 */
+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */
+#define GFXMMU_FCR_CB2OF_Pos               (2U)
+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)     /*!< 0x00000004 */
+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */
+#define GFXMMU_FCR_CB3OF_Pos               (3U)
+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)     /*!< 0x00000008 */
+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */
+#define GFXMMU_FCR_CAMEF_Pos               (4U)
+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)     /*!< 0x00000010 */
+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */
+
+/****************** Bits definition for GFXMMU_DVR register *******************/
+#define GFXMMU_DVR_DV_Pos                  (0U)
+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */
+
+/****************** Bits definition for GFXMMU_DAR register *******************/
+#define GFXMMU_DAR_DA_Pos                  (0U)
+#define GFXMMU_DAR_DA_Msk                  (0xFFUL << GFXMMU_DVR_DA_Pos)       /*!< 0x000000FF */
+#define GFXMMU_DAR_DA                      GFXMMU_DVR_DA_Msk                   /*!< DA[7:0] bits (Default alpha) */
+
+/****************** Bits definition for GFXMMU_B0CR register ******************/
+#define GFXMMU_B0CR_PBO_Pos                (4U)
+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B0CR_PBBA_Pos               (23U)
+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B1CR register ******************/
+#define GFXMMU_B1CR_PBO_Pos                (4U)
+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B1CR_PBBA_Pos               (23U)
+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B2CR register ******************/
+#define GFXMMU_B2CR_PBO_Pos                (4U)
+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B2CR_PBBA_Pos               (23U)
+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B3CR register ******************/
+#define GFXMMU_B3CR_PBO_Pos                (4U)
+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B3CR_PBBA_Pos               (23U)
+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_LUTxL register *****************/
+#define GFXMMU_LUTxL_EN_Pos                (0U)
+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)      /*!< 0x00000001 */
+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */
+#define GFXMMU_LUTxL_FVB_Pos               (8U)
+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)    /*!< 0x0000FF00 */
+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */
+#define GFXMMU_LUTxL_LVB_Pos               (16U)
+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)    /*!< 0x00FF0000 */
+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */
+
+/****************** Bits definition for GFXMMU_LUTxH register *****************/
+#define GFXMMU_LUTxH_LO_Pos                (0U)
+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)  /*!< 0x0003FFFF */
+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[17:0] bits (Line offset) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic Timer (GFXTIM)                               */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CR_TES_Pos              (0U)
+#define GFXTIM_CR_TES_Msk              (0x3UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000003 */
+#define GFXTIM_CR_TES                  GFXTIM_CR_TES_Msk
+#define GFXTIM_CR_TES_0                (0x1UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000001 */
+#define GFXTIM_CR_TES_1                (0x2UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000002 */
+
+#define GFXTIM_CR_TEPOL_Pos            (4U)
+#define GFXTIM_CR_TEPOL_Msk            (0x1UL << GFXTIM_CR_TEPOL_Pos)          /*!< 0x00000010 */
+#define GFXTIM_CR_TEPOL                GFXTIM_CR_TEPOL_Msk
+
+#define GFXTIM_CR_SYNCS_Pos            (8U)
+#define GFXTIM_CR_SYNCS_Msk            (0x3UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000300 */
+#define GFXTIM_CR_SYNCS                GFXTIM_CR_SYNCS_Msk
+#define GFXTIM_CR_SYNCS_0              (0x1UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000100 */
+#define GFXTIM_CR_SYNCS_1              (0x2UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000200 */
+
+#define GFXTIM_CR_FCCOE_Pos            (16U)
+#define GFXTIM_CR_FCCOE_Msk            (0x1UL << GFXTIM_CR_FCCOE_Pos)          /*!< 0x00010000 */
+#define GFXTIM_CR_FCCOE                GFXTIM_CR_FCCOE_Msk
+
+#define GFXTIM_CR_LCCOE_Pos            (17U)
+#define GFXTIM_CR_LCCOE_Msk            (0x1UL << GFXTIM_CR_LCCOE_Pos)          /*!< 0x00020000 */
+#define GFXTIM_CR_LCCOE                GFXTIM_CR_LCCOE_Msk
+
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CGCR_LCS_Pos           (0U)
+#define GFXTIM_CGCR_LCS_Msk           (0x7UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_LCS               GFXTIM_CGCR_LCS_Msk
+#define GFXTIM_CGCR_LCS_0             (0x1UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000001 */
+#define GFXTIM_CGCR_LCS_1             (0x2UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000002 */
+#define GFXTIM_CGCR_LCS_2             (0x4UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000004 */
+
+#define GFXTIM_CGCR_LCCCS_Pos         (4U)
+#define GFXTIM_CGCR_LCCCS_Msk         (0x1UL << GFXTIM_CGCR_LCCCS_Pos)         /*!< 0x00000010 */
+#define GFXTIM_CGCR_LCCCS             GFXTIM_CGCR_LCCCS_Msk
+
+#define GFXTIM_CGCR_LCCFR_Pos         (8U)
+#define GFXTIM_CGCR_LCCFR_Msk         (0x1UL << GFXTIM_CGCR_LCCFR_Pos)         /*!< 0x00000100 */
+#define GFXTIM_CGCR_LCCFR             GFXTIM_CGCR_LCCFR_Msk
+
+#define GFXTIM_CGCR_LCCHRS_Pos        (12U)
+#define GFXTIM_CGCR_LCCHRS_Msk        (0x7UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00007000 */
+#define GFXTIM_CGCR_LCCHRS            GFXTIM_CGCR_LCCHRS_Msk
+#define GFXTIM_CGCR_LCCHRS_0          (0x1UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00001000 */
+#define GFXTIM_CGCR_LCCHRS_1          (0x2UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00002000 */
+#define GFXTIM_CGCR_LCCHRS_2          (0x4UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCS_Pos           (16U)
+#define GFXTIM_CGCR_FCS_Msk           (0x7UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_FCS               GFXTIM_CGCR_FCS_Msk
+#define GFXTIM_CGCR_FCS_0             (0x1UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00001000 */
+#define GFXTIM_CGCR_FCS_1             (0x2UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00002000 */
+#define GFXTIM_CGCR_FCS_2             (0x4UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCCCS_Pos         (20U)
+#define GFXTIM_CGCR_FCCCS_Msk         (0x7UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00070000 */
+#define GFXTIM_CGCR_FCCCS             GFXTIM_CGCR_FCCCS_Msk
+#define GFXTIM_CGCR_FCCCS_0           (0x1UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00010000 */
+#define GFXTIM_CGCR_FCCCS_1           (0x2UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00020000 */
+#define GFXTIM_CGCR_FCCCS_2           (0x4UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_CGCR_FCCFR_Pos         (24U)
+#define GFXTIM_CGCR_FCCFR_Msk         (0x1UL << GFXTIM_CGCR_FCCFR_Pos)         /*!< 0x00100000 */
+#define GFXTIM_CGCR_FCCFR             GFXTIM_CGCR_FCCFR_Msk
+
+#define GFXTIM_CGCR_FCCHRS_Pos        (28U)
+#define GFXTIM_CGCR_FCCHRS_Msk        (0x7UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x70000000 */
+#define GFXTIM_CGCR_FCCHRS            GFXTIM_CGCR_FCCHRS_Msk
+#define GFXTIM_CGCR_FCCHRS_0          (0x1UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x10000000 */
+#define GFXTIM_CGCR_FCCHRS_1          (0x2UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x20000000 */
+#define GFXTIM_CGCR_FCCHRS_2          (0x4UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_TCR register  *****************/
+#define GFXTIM_TCR_AFCEN_Pos           (0U)
+#define GFXTIM_TCR_AFCEN_Msk           (0x1UL << GFXTIM_TCR_AFCEN_Pos)         /*!< 0x00000001 */
+#define GFXTIM_TCR_AFCEN               GFXTIM_TCR_AFCEN_Msk
+
+#define GFXTIM_TCR_FAFCR_Pos           (1U)
+#define GFXTIM_TCR_FAFCR_Msk           (0x1UL << GFXTIM_TCR_FAFCR_Pos)         /*!< 0x00000002 */
+#define GFXTIM_TCR_FAFCR               GFXTIM_TCR_FAFCR_Msk
+
+#define GFXTIM_TCR_ALCEN_Pos           (4U)
+#define GFXTIM_TCR_ALCEN_Msk           (0x1UL << GFXTIM_TCR_ALCEN_Pos)         /*!< 0x00000010 */
+#define GFXTIM_TCR_ALCEN               GFXTIM_TCR_ALCEN_Msk
+
+#define GFXTIM_TCR_FALCR_Pos           (5U)
+#define GFXTIM_TCR_FALCR_Msk           (0x1UL << GFXTIM_TCR_FALCR_Pos)         /*!< 0x00000020 */
+#define GFXTIM_TCR_FALCR               GFXTIM_TCR_FALCR_Msk
+
+#define GFXTIM_TCR_RFC1EN_Pos          (16U)
+#define GFXTIM_TCR_RFC1EN_Msk          (0x1UL << GFXTIM_TCR_RFC1EN_Pos)        /*!< 0x00010000 */
+#define GFXTIM_TCR_RFC1EN              GFXTIM_TCR_RFC1EN_Msk
+
+#define GFXTIM_TCR_RFC1CM_Pos          (17U)
+#define GFXTIM_TCR_RFC1CM_Msk          (0x1UL << GFXTIM_TCR_RFC1CM_Pos)        /*!< 0x00020000 */
+#define GFXTIM_TCR_RFC1CM              GFXTIM_TCR_RFC1CM_Msk
+
+#define GFXTIM_TCR_FRFC1R_Pos          (18U)
+#define GFXTIM_TCR_FRFC1R_Msk          (0x1UL << GFXTIM_TCR_FRFC1R_Pos)        /*!< 0x00040000 */
+#define GFXTIM_TCR_FRFC1R              GFXTIM_TCR_FRFC1R_Msk
+
+#define GFXTIM_TCR_RFC2EN_Pos          (20U)
+#define GFXTIM_TCR_RFC2EN_Msk          (0x1UL << GFXTIM_TCR_RFC2EN_Pos)        /*!< 0x00100000 */
+#define GFXTIM_TCR_RFC2EN              GFXTIM_TCR_RFC2EN_Msk
+
+#define GFXTIM_TCR_RFC2CM_Pos          (21U)
+#define GFXTIM_TCR_RFC2CM_Msk          (0x1UL << GFXTIM_TCR_RFC2CM_Pos)        /*!< 0x00200000 */
+#define GFXTIM_TCR_RFC2CM              GFXTIM_TCR_RFC2CM_Msk
+
+#define GFXTIM_TCR_FRFC2R_Pos          (22U)
+#define GFXTIM_TCR_FRFC2R_Msk          (0x1UL << GFXTIM_TCR_FRFC2R_Pos)        /*!< 0x00400000 */
+#define GFXTIM_TCR_FRFC2R              GFXTIM_TCR_FRFC2R_Msk
+
+/******************  Bits definition for GFXTIM_TDR register  *****************/
+#define GFXTIM_TDR_AFCDIS_Pos          (0U)
+#define GFXTIM_TDR_AFCDIS_Msk          (0x1UL << GFXTIM_TDR_AFCDIS_Pos)        /*!< 0x00000001 */
+#define GFXTIM_TDR_AFCDIS              GFXTIM_TDR_AFCDIS_Msk
+
+#define GFXTIM_TDR_ALCDIS_Pos          (4U)
+#define GFXTIM_TDR_ALCDIS_Msk          (0x1UL << GFXTIM_TDR_ALCDIS_Pos)        /*!< 0x00000010 */
+#define GFXTIM_TDR_ALCDIS              GFXTIM_TDR_ALCDIS_Msk
+
+#define GFXTIM_TDR_RFC1DIS_Pos         (16U)
+#define GFXTIM_TDR_RFC1DIS_Msk         (0x1UL << GFXTIM_TDR_RFC1DIS_Pos)       /*!< 0x00010000 */
+#define GFXTIM_TDR_RFC1DIS             GFXTIM_TDR_RFC1DIS_Msk
+
+#define GFXTIM_TDR_RFC2DIS_Pos         (20U)
+#define GFXTIM_TDR_RFC2DIS_Msk         (0x1UL << GFXTIM_TDR_RFC2DIS_Pos)       /*!< 0x00100000 */
+#define GFXTIM_TDR_RFC2DIS             GFXTIM_TDR_RFC2DIS_Msk
+
+/******************  Bits definition for GFXTIM_EVCR register  ****************/
+#define GFXTIM_EVCR_EV1EN_Pos          (0U)
+#define GFXTIM_EVCR_EV1EN_Msk          (0x1UL << GFXTIM_EVCR_EV1EN_Pos)        /*!< 0x00000001 */
+#define GFXTIM_EVCR_EV1EN              GFXTIM_EVCR_EV1EN_Msk
+
+#define GFXTIM_EVCR_EV2EN_Pos          (1U)
+#define GFXTIM_EVCR_EV2EN_Msk          (0x1UL << GFXTIM_EVCR_EV2EN_Pos)        /*!< 0x00000002 */
+#define GFXTIM_EVCR_EV2EN              GFXTIM_EVCR_EV2EN_Msk
+
+#define GFXTIM_EVCR_EV3EN_Pos          (2U)
+#define GFXTIM_EVCR_EV3EN_Msk          (0x1UL << GFXTIM_EVCR_EV3EN_Pos)        /*!< 0x00000004 */
+#define GFXTIM_EVCR_EV3EN              GFXTIM_EVCR_EV3EN_Msk
+
+#define GFXTIM_EVCR_EV4EN_Pos          (3U)
+#define GFXTIM_EVCR_EV4EN_Msk          (0x1UL << GFXTIM_EVCR_EV4EN_Pos)        /*!< 0x00000008 */
+#define GFXTIM_EVCR_EV4EN              GFXTIM_EVCR_EV4EN_Msk
+
+/******************  Bits definition for GFXTIM_EVSR register  ****************/
+#define GFXTIM_EVSR_LES1_Pos           (0U)
+#define GFXTIM_EVSR_LES1_Msk           (0x7UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000007 */
+#define GFXTIM_EVSR_LES1               GFXTIM_EVSR_LES1_Msk
+#define GFXTIM_EVSR_LES1_0             (0x1UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000001 */
+#define GFXTIM_EVSR_LES1_1             (0x2UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000002 */
+#define GFXTIM_EVSR_LES1_2             (0x4UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000004 */
+
+#define GFXTIM_EVSR_FES1_Pos           (4U)
+#define GFXTIM_EVSR_FES1_Msk           (0x7UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000070 */
+#define GFXTIM_EVSR_FES1               GFXTIM_EVSR_FES1_Msk
+#define GFXTIM_EVSR_FES1_0             (0x1UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000010 */
+#define GFXTIM_EVSR_FES1_1             (0x2UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000020 */
+#define GFXTIM_EVSR_FES1_2             (0x4UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000040 */
+
+#define GFXTIM_EVSR_LES2_Pos           (8U)
+#define GFXTIM_EVSR_LES2_Msk           (0x7UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000700 */
+#define GFXTIM_EVSR_LES2               GFXTIM_EVSR_LES2_Msk
+#define GFXTIM_EVSR_LES2_0             (0x1UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000100 */
+#define GFXTIM_EVSR_LES2_1             (0x2UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000200 */
+#define GFXTIM_EVSR_LES2_2             (0x4UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000400 */
+
+#define GFXTIM_EVSR_FES2_Pos           (12U)
+#define GFXTIM_EVSR_FES2_Msk           (0x7UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00007000 */
+#define GFXTIM_EVSR_FES2               GFXTIM_EVSR_FES2_Msk
+#define GFXTIM_EVSR_FES2_0             (0x1UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00001000 */
+#define GFXTIM_EVSR_FES2_1             (0x2UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00002000 */
+#define GFXTIM_EVSR_FES2_2             (0x4UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00004000 */
+
+#define GFXTIM_EVSR_LES3_Pos           (16U)
+#define GFXTIM_EVSR_LES3_Msk           (0x7UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00070000 */
+#define GFXTIM_EVSR_LES3               GFXTIM_EVSR_LES3_Msk
+#define GFXTIM_EVSR_LES3_0             (0x1UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00010000 */
+#define GFXTIM_EVSR_LES3_1             (0x2UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00020000 */
+#define GFXTIM_EVSR_LES3_2             (0x4UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_EVSR_FES3_Pos           (20U)
+#define GFXTIM_EVSR_FES3_Msk           (0x7UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00700000 */
+#define GFXTIM_EVSR_FES3               GFXTIM_EVSR_FES3_Msk
+#define GFXTIM_EVSR_FES3_0             (0x1UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00100000 */
+#define GFXTIM_EVSR_FES3_1             (0x2UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00200000 */
+#define GFXTIM_EVSR_FES3_2             (0x4UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00400000 */
+
+#define GFXTIM_EVSR_LES4_Pos           (24U)
+#define GFXTIM_EVSR_LES4_Msk           (0x7UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x07000000 */
+#define GFXTIM_EVSR_LES4               GFXTIM_EVSR_LES4_Msk
+#define GFXTIM_EVSR_LES4_0             (0x1UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x01000000 */
+#define GFXTIM_EVSR_LES4_1             (0x2UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x02000000 */
+#define GFXTIM_EVSR_LES4_2             (0x4UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x04000000 */
+
+#define GFXTIM_EVSR_FES4_Pos           (28U)
+#define GFXTIM_EVSR_FES4_Msk           (0x7UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x70000000 */
+#define GFXTIM_EVSR_FES4               GFXTIM_EVSR_FES4_Msk
+#define GFXTIM_EVSR_FES4_0             (0x1UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x10000000 */
+#define GFXTIM_EVSR_FES4_1             (0x2UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x20000000 */
+#define GFXTIM_EVSR_FES4_2             (0x4UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_WDGTCR register  **************/
+#define GFXTIM_WDGTCR_WDGEN_Pos        (0U)
+#define GFXTIM_WDGTCR_WDGEN_Msk        (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos)      /*!< 0x00000001 */
+#define GFXTIM_WDGTCR_WDGEN            GFXTIM_WDGTCR_WDGEN_Msk
+
+#define GFXTIM_WDGTCR_WDGDIS_Pos       (1U)
+#define GFXTIM_WDGTCR_WDGDIS_Msk       (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos)     /*!< 0x00000002 */
+#define GFXTIM_WDGTCR_WDGDIS           GFXTIM_WDGTCR_WDGDIS_Msk
+
+#define GFXTIM_WDGTCR_WDGS_Pos         (2U)
+#define GFXTIM_WDGTCR_WDGS_Msk         (0x1UL << GFXTIM_WDGTCR_WDGS_Pos)       /*!< 0x00000004 */
+#define GFXTIM_WDGTCR_WDGS             GFXTIM_WDGTCR_WDGS_Msk
+
+#define GFXTIM_WDGTCR_WDGHRC_Pos       (4U)
+#define GFXTIM_WDGTCR_WDGHRC_Msk       (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000030 */
+#define GFXTIM_WDGTCR_WDGHRC           GFXTIM_WDGTCR_WDGHRC_Msk
+#define GFXTIM_WDGTCR_WDGHRC_0         (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000010 */
+#define GFXTIM_WDGTCR_WDGHRC_1         (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000020 */
+
+#define GFXTIM_WDGTCR_WDGCS_Pos        (8U)
+#define GFXTIM_WDGTCR_WDGCS_Msk        (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000700 */
+#define GFXTIM_WDGTCR_WDGCS            GFXTIM_WDGTCR_WDGCS_Msk
+#define GFXTIM_WDGTCR_WDGCS_0          (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000100 */
+#define GFXTIM_WDGTCR_WDGCS_1          (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000200 */
+#define GFXTIM_WDGTCR_WDGCS_2          (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000400 */
+#define GFXTIM_WDGTCR_WDGCS_3          (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000800 */
+
+#define GFXTIM_WDGTCR_FWDGR_Pos        (16U)
+#define GFXTIM_WDGTCR_FWDGR_Msk        (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos)      /*!< 0x00010000 */
+#define GFXTIM_WDGTCR_FWDGR            GFXTIM_WDGTCR_FWDGR_Msk
+
+/******************  Bits definition for GFXTIM_ISR register  *****************/
+#define GFXTIM_ISR_AFCOF_Pos           (0U)
+#define GFXTIM_ISR_AFCOF_Msk           (0x1UL << GFXTIM_ISR_AFCOF_Pos)         /*!< 0x00000001 */
+#define GFXTIM_ISR_AFCOF               GFXTIM_ISR_AFCOF_Msk
+
+#define GFXTIM_ISR_ALCOF_Pos           (1U)
+#define GFXTIM_ISR_ALCOF_Msk           (0x1UL << GFXTIM_ISR_ALCOF_Pos)         /*!< 0x00000002 */
+#define GFXTIM_ISR_ALCOF               GFXTIM_ISR_ALCOF_Msk
+
+#define GFXTIM_ISR_TEF_Pos             (2U)
+#define GFXTIM_ISR_TEF_Msk             (0x1UL << GFXTIM_ISR_TEF_Pos)           /*!< 0x00000004 */
+#define GFXTIM_ISR_TEF                 GFXTIM_ISR_TEF_Msk
+
+#define GFXTIM_ISR_AFCC1F_Pos          (4U)
+#define GFXTIM_ISR_AFCC1F_Msk          (0x1UL << GFXTIM_ISR_AFCC1F_Pos)        /*!< 0x00000010 */
+#define GFXTIM_ISR_AFCC1F              GFXTIM_ISR_AFCC1F_Msk
+
+#define GFXTIM_ISR_ALCC1F_Pos          (8U)
+#define GFXTIM_ISR_ALCC1F_Msk          (0x1UL << GFXTIM_ISR_ALCC1F_Pos)        /*!< 0x00000100 */
+#define GFXTIM_ISR_ALCC1F              GFXTIM_ISR_ALCC1F_Msk
+
+#define GFXTIM_ISR_ALCC2F_Pos          (9U)
+#define GFXTIM_ISR_ALCC2F_Msk          (0x1UL << GFXTIM_ISR_ALCC2F_Pos)        /*!< 0x00000200 */
+#define GFXTIM_ISR_ALCC2F              GFXTIM_ISR_ALCC2F_Msk
+
+#define GFXTIM_ISR_RFC1RF_Pos          (12U)
+#define GFXTIM_ISR_RFC1RF_Msk          (0x1UL << GFXTIM_ISR_RFC1RF_Pos)        /*!< 0x00001000 */
+#define GFXTIM_ISR_RFC1RF              GFXTIM_ISR_RFC1RF_Msk
+
+#define GFXTIM_ISR_RFC2RF_Pos          (13U)
+#define GFXTIM_ISR_RFC2RF_Msk          (0x1UL << GFXTIM_ISR_RFC2RF_Pos)        /*!< 0x00002000 */
+#define GFXTIM_ISR_RFC2RF              GFXTIM_ISR_RFC2RF_Msk
+
+#define GFXTIM_ISR_EV1F_Pos            (16U)
+#define GFXTIM_ISR_EV1F_Msk            (0x1UL << GFXTIM_ISR_EV1F_Pos)          /*!< 0x00010000 */
+#define GFXTIM_ISR_EV1F                GFXTIM_ISR_EV1F_Msk
+
+#define GFXTIM_ISR_EV2F_Pos            (17U)
+#define GFXTIM_ISR_EV2F_Msk            (0x1UL << GFXTIM_ISR_EV2F_Pos)          /*!< 0x00020000 */
+#define GFXTIM_ISR_EV2F                GFXTIM_ISR_EV2F_Msk
+
+#define GFXTIM_ISR_EV3F_Pos            (18U)
+#define GFXTIM_ISR_EV3F_Msk            (0x1UL << GFXTIM_ISR_EV3F_Pos)          /*!< 0x00040000 */
+#define GFXTIM_ISR_EV3F                GFXTIM_ISR_EV3F_Msk
+
+#define GFXTIM_ISR_EV4F_Pos            (19U)
+#define GFXTIM_ISR_EV4F_Msk            (0x1UL << GFXTIM_ISR_EV4F_Pos)          /*!< 0x00080000 */
+#define GFXTIM_ISR_EV4F                GFXTIM_ISR_EV4F_Msk
+
+#define GFXTIM_ISR_WDGAF_Pos           (24U)
+#define GFXTIM_ISR_WDGAF_Msk           (0x1UL << GFXTIM_ISR_WDGAF_Pos)         /*!< 0x01000000 */
+#define GFXTIM_ISR_WDGAF               GFXTIM_ISR_WDGAF_Msk
+
+#define GFXTIM_ISR_WDGPF_Pos           (25U)
+#define GFXTIM_ISR_WDGPF_Msk           (0x1UL << GFXTIM_ISR_WDGPF_Pos)         /*!< 0x02000000 */
+#define GFXTIM_ISR_WDGPF               GFXTIM_ISR_WDGPF_Msk
+
+/******************  Bits definition for GFXTIM_ICR register  *****************/
+#define GFXTIM_ICR_CAFCOF_Pos          (0U)
+#define GFXTIM_ICR_CAFCOF_Msk          (0x1UL << GFXTIM_ICR_CAFCOF_Pos)        /*!< 0x00000001 */
+#define GFXTIM_ICR_CAFCOF              GFXTIM_ICR_CAFCOF_Msk
+
+#define GFXTIM_ICR_CALCOF_Pos          (1U)
+#define GFXTIM_ICR_CALCOF_Msk          (0x1UL << GFXTIM_ICR_CALCOF_Pos)        /*!< 0x00000002 */
+#define GFXTIM_ICR_CALCOF              GFXTIM_ICR_CALCOF_Msk
+
+#define GFXTIM_ICR_CTEF_Pos            (2U)
+#define GFXTIM_ICR_CTEF_Msk            (0x1UL << GFXTIM_ICR_CTEF_Pos)          /*!< 0x00000004 */
+#define GFXTIM_ICR_CTEF                GFXTIM_ICR_CTEF_Msk
+
+#define GFXTIM_ICR_CAFCC1F_Pos         (4U)
+#define GFXTIM_ICR_CAFCC1F_Msk         (0x1UL << GFXTIM_ICR_CAFCC1F_Pos)       /*!< 0x00000010 */
+#define GFXTIM_ICR_CAFCC1F             GFXTIM_ICR_CAFCC1F_Msk
+
+#define GFXTIM_ICR_CALCC1F_Pos         (8U)
+#define GFXTIM_ICR_CALCC1F_Msk         (0x1UL << GFXTIM_ICR_CALCC1F_Pos)       /*!< 0x00000100 */
+#define GFXTIM_ICR_CALCC1F             GFXTIM_ICR_CALCC1F_Msk
+
+#define GFXTIM_ICR_CALCC2F_Pos         (9U)
+#define GFXTIM_ICR_CALCC2F_Msk         (0x1UL << GFXTIM_ICR_CALCC2F_Pos)       /*!< 0x00000200 */
+#define GFXTIM_ICR_CALCC2F             GFXTIM_ICR_CALCC2F_Msk
+
+#define GFXTIM_ICR_CRFC1RF_Pos         (12U)
+#define GFXTIM_ICR_CRFC1RF_Msk         (0x1UL << GFXTIM_ICR_CRFC1RF_Pos)       /*!< 0x00001000 */
+#define GFXTIM_ICR_CRFC1RF             GFXTIM_ICR_CRFC1RF_Msk
+
+#define GFXTIM_ICR_CRFC2RF_Pos         (13U)
+#define GFXTIM_ICR_CRFC2RF_Msk         (0x1UL << GFXTIM_ICR_CRFC2RF_Pos)       /*!< 0x00002000 */
+#define GFXTIM_ICR_CRFC2RF             GFXTIM_ICR_CRFC2RF_Msk
+
+#define GFXTIM_ICR_CEV1F_Pos           (16U)
+#define GFXTIM_ICR_CEV1F_Msk           (0x1UL << GFXTIM_ICR_CEV1F_Pos)         /*!< 0x00010000 */
+#define GFXTIM_ICR_CEV1F               GFXTIM_ICR_CEV1F_Msk
+
+#define GFXTIM_ICR_CEV2F_Pos           (17U)
+#define GFXTIM_ICR_CEV2F_Msk           (0x1UL << GFXTIM_ICR_CEV2F_Pos)         /*!< 0x00020000 */
+#define GFXTIM_ICR_CEV2F               GFXTIM_ICR_CEV2F_Msk
+
+#define GFXTIM_ICR_CEV3F_Pos           (18U)
+#define GFXTIM_ICR_CEV3F_Msk           (0x1UL << GFXTIM_ICR_CEV3F_Pos)         /*!< 0x00040000 */
+#define GFXTIM_ICR_CEV3F               GFXTIM_ICR_CEV3F_Msk
+
+#define GFXTIM_ICR_CEV4F_Pos           (19U)
+#define GFXTIM_ICR_CEV4F_Msk           (0x1UL << GFXTIM_ICR_CEV4F_Pos)         /*!< 0x00080000 */
+#define GFXTIM_ICR_CEV4F               GFXTIM_ICR_CEV4F_Msk
+
+#define GFXTIM_ICR_CWDGAF_Pos          (24U)
+#define GFXTIM_ICR_CWDGAF_Msk          (0x1UL << GFXTIM_ICR_CWDGAF_Pos)        /*!< 0x01000000 */
+#define GFXTIM_ICR_CWDGAF              GFXTIM_ICR_CWDGAF_Msk
+
+#define GFXTIM_ICR_CWDGPF_Pos          (25U)
+#define GFXTIM_ICR_CWDGPF_Msk          (0x1UL << GFXTIM_ICR_CWDGPF_Pos)        /*!< 0x02000000 */
+#define GFXTIM_ICR_CWDGPF              GFXTIM_ICR_CWDGPF_Msk
+
+/******************  Bits definition for GFXTIM_IER register  *****************/
+#define GFXTIM_IER_AFCOIE_Pos          (0U)
+#define GFXTIM_IER_AFCOIE_Msk          (0x1UL << GFXTIM_IER_AFCOIE_Pos)        /*!< 0x00000001 */
+#define GFXTIM_IER_AFCOIE              GFXTIM_IER_AFCOIE_Msk
+
+#define GFXTIM_IER_ALCOIE_Pos          (1U)
+#define GFXTIM_IER_ALCOIE_Msk          (0x1UL << GFXTIM_IER_ALCOIE_Pos)        /*!< 0x00000002 */
+#define GFXTIM_IER_ALCOIE              GFXTIM_IER_ALCOIE_Msk
+
+#define GFXTIM_IER_TEIE_Pos            (2U)
+#define GFXTIM_IER_TEIE_Msk            (0x1UL << GFXTIM_IER_TEIE_Pos)          /*!< 0x00000004 */
+#define GFXTIM_IER_TEIE                GFXTIM_IER_TEIE_Msk
+
+#define GFXTIM_IER_AFCC1IE_Pos         (4U)
+#define GFXTIM_IER_AFCC1IE_Msk         (0x1UL << GFXTIM_IER_AFCC1IE_Pos)       /*!< 0x00000010 */
+#define GFXTIM_IER_AFCC1IE             GFXTIM_IER_AFCC1IE_Msk
+
+#define GFXTIM_IER_ALCC1IE_Pos         (8U)
+#define GFXTIM_IER_ALCC1IE_Msk         (0x1UL << GFXTIM_IER_ALCC1IE_Pos)       /*!< 0x00000100 */
+#define GFXTIM_IER_ALCC1IE             GFXTIM_IER_ALCC1IE_Msk
+
+#define GFXTIM_IER_ALCC2IE_Pos         (9U)
+#define GFXTIM_IER_ALCC2IE_Msk         (0x1UL << GFXTIM_IER_ALCC2IE_Pos)       /*!< 0x00000200 */
+#define GFXTIM_IER_ALCC2IE             GFXTIM_IER_ALCC2IE_Msk
+
+#define GFXTIM_IER_RFC1RIE_Pos         (12U)
+#define GFXTIM_IER_RFC1RIE_Msk         (0x1UL << GFXTIM_IER_RFC1RIE_Pos)       /*!< 0x00001000 */
+#define GFXTIM_IER_RFC1RIE             GFXTIM_IER_RFC1RIE_Msk
+
+#define GFXTIM_IER_RFC2RIE_Pos         (13U)
+#define GFXTIM_IER_RFC2RIE_Msk         (0x1UL << GFXTIM_IER_RFC2RIE_Pos)       /*!< 0x00002000 */
+#define GFXTIM_IER_RFC2RIE             GFXTIM_IER_RFC2RIE_Msk
+
+#define GFXTIM_IER_EV1IE_Pos           (16U)
+#define GFXTIM_IER_EV1IE_Msk           (0x1UL << GFXTIM_IER_EV1IE_Pos)         /*!< 0x00010000 */
+#define GFXTIM_IER_EV1IE               GFXTIM_IER_EV1IE_Msk
+
+#define GFXTIM_IER_EV2IE_Pos           (17U)
+#define GFXTIM_IER_EV2IE_Msk           (0x1UL << GFXTIM_IER_EV2IE_Pos)         /*!< 0x00020000 */
+#define GFXTIM_IER_EV2IE               GFXTIM_IER_EV2IE_Msk
+
+#define GFXTIM_IER_EV3IE_Pos           (18U)
+#define GFXTIM_IER_EV3IE_Msk           (0x1UL << GFXTIM_IER_EV3IE_Pos)         /*!< 0x00040000 */
+#define GFXTIM_IER_EV3IE               GFXTIM_IER_EV3IE_Msk
+
+#define GFXTIM_IER_EV4IE_Pos           (19U)
+#define GFXTIM_IER_EV4IE_Msk           (0x1UL << GFXTIM_IER_EV4IE_Pos)         /*!< 0x00080000 */
+#define GFXTIM_IER_EV4IE               GFXTIM_IER_EV4IE_Msk
+
+#define GFXTIM_IER_WDGAIE_Pos          (24U)
+#define GFXTIM_IER_WDGAIE_Msk          (0x1UL << GFXTIM_IER_WDGAIE_Pos)        /*!< 0x01000000 */
+#define GFXTIM_IER_WDGAIE              GFXTIM_IER_WDGAIE_Msk
+
+#define GFXTIM_IER_WDGPIE_Pos          (25U)
+#define GFXTIM_IER_WDGPIE_Msk          (0x1UL << GFXTIM_IER_WDGPIE_Pos)        /*!< 0x02000000 */
+#define GFXTIM_IER_WDGPIE              GFXTIM_IER_WDGPIE_Msk
+
+/******************  Bits definition for GFXTIM_TSR register  *****************/
+#define GFXTIM_TSR_AFCS_Pos            (0U)
+#define GFXTIM_TSR_AFCS_Msk            (0x1UL << GFXTIM_TSR_AFCS_Pos)          /*!< 0x00000001 */
+#define GFXTIM_TSR_AFCS                GFXTIM_TSR_AFCS_Msk
+
+#define GFXTIM_TSR_ALCS_Pos            (4U)
+#define GFXTIM_TSR_ALCS_Msk            (0x1UL << GFXTIM_TSR_ALCS_Pos)          /*!< 0x00000010 */
+#define GFXTIM_TSR_ALCS                GFXTIM_TSR_ALCS_Msk
+
+#define GFXTIM_TSR_RFC1S_Pos           (16U)
+#define GFXTIM_TSR_RFC1S_Msk           (0x1UL << GFXTIM_TSR_RFC1S_Pos)         /*!< 0x00010000 */
+#define GFXTIM_TSR_RFC1S               GFXTIM_TSR_RFC1S_Msk
+
+#define GFXTIM_TSR_RFC2S_Pos           (20U)
+#define GFXTIM_TSR_RFC2S_Msk           (0x1UL << GFXTIM_TSR_RFC2S_Pos)         /*!< 0x00100000 */
+#define GFXTIM_TSR_RFC2S               GFXTIM_TSR_RFC2S_Msk
+
+/******************  Bits definition for GFXTIM_LCCRR register  ***************/
+#define GFXTIM_LCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_LCCRR_RELOAD_Msk        (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
+#define GFXTIM_LCCRR_RELOAD            GFXTIM_LCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_FCCRR register  ***************/
+#define GFXTIM_FCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_FCCRR_RELOAD_Msk        (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_FCCRR_RELOAD            GFXTIM_FCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_ATR register  *****************/
+#define GFXTIM_ATR_LINE_Pos            (0U)
+#define GFXTIM_ATR_LINE_Msk            (0xFFFUL << GFXTIM_ATR_LINE_Pos)        /*!< 0x00000FFF */
+#define GFXTIM_ATR_LINE                GFXTIM_ATR_LINE_Msk
+
+#define GFXTIM_ATR_FRAME_Pos           (12U)
+#define GFXTIM_ATR_FRAME_Msk           (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos)     /*!< 0xFFFFF000 */
+#define GFXTIM_ATR_FRAME               GFXTIM_ATR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_AFCR register  ****************/
+#define GFXTIM_AFCR_FRAME_Pos          (0U)
+#define GFXTIM_AFCR_FRAME_Msk          (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos)    /*!< 0x000FFFFF */
+#define GFXTIM_AFCR_FRAME              GFXTIM_AFCR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCR register  ****************/
+#define GFXTIM_ALCR_LINE_Pos           (0U)
+#define GFXTIM_ALCR_LINE_Msk           (0xFFFUL << GFXTIM_ALCR_LINE_Pos)       /*!< 0x00000FFF */
+#define GFXTIM_ALCR_LINE               GFXTIM_ALCR_LINE_Msk
+
+/******************  Bits definition for GFXTIM_AFCC1R register  **************/
+#define GFXTIM_AFCC1R_FRAME_Pos        (0U)
+#define GFXTIM_AFCC1R_FRAME_Msk        (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos)  /*!< 0x000FFFFF */
+#define GFXTIM_AFCC1R_FRAME            GFXTIM_AFCC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCC1R register  **************/
+#define GFXTIM_ALCC1R_LINE_Pos         (0U)
+#define GFXTIM_ALCC1R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC1R_LINE             GFXTIM_ALCC1R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_ALCC2R register  **************/
+#define GFXTIM_ALCC2R_LINE_Pos         (0U)
+#define GFXTIM_ALCC2R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC2R_LINE             GFXTIM_ALCC2R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_RFC1R register  ***************/
+#define GFXTIM_RFC1R_FRAME_Pos         (0U)
+#define GFXTIM_RFC1R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC1R_FRAME             GFXTIM_RFC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC1RR register  **************/
+#define GFXTIM_RFC1RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC1RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC1RR_FRAME            GFXTIM_RFC1RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2R register  ***************/
+#define GFXTIM_RFC2R_FRAME_Pos         (0U)
+#define GFXTIM_RFC2R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC2R_FRAME             GFXTIM_RFC2R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2RR register  **************/
+#define GFXTIM_RFC2RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC2RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC2RR_FRAME            GFXTIM_RFC2RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_WDGCR register  ***************/
+#define GFXTIM_WDGCR_VALUE_Pos         (0U)
+#define GFXTIM_WDGCR_VALUE_Msk         (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos)    /*!< 0x0000FFFF */
+#define GFXTIM_WDGCR_VALUE             GFXTIM_WDGCR_VALUE_Msk
+
+/******************  Bits definition for GFXTIM_WDGRR register  ***************/
+#define GFXTIM_WDGRR_RELOAD_Pos        (0U)
+#define GFXTIM_WDGRR_RELOAD_Msk        (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos)   /*!< 0x0000FFFF */
+#define GFXTIM_WDGRR_RELOAD            GFXTIM_WDGRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_WDGPAR register  **************/
+#define GFXTIM_WDGPAR_PREALARM_Pos      (0U)
+#define GFXTIM_WDGPAR_PREALARM_Msk     (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
+#define GFXTIM_WDGPAR_PREALARM          GFXTIM_WDGPAR_PREALARM_Msk
+
+/******************  Bits definition for GFXTIM_HWCFGR register  **************/
+
+/******************  Bits definition for GFXTIM_VERR register  ****************/
+#define GFXTIM_VERR_MINREV_Pos         (0U)
+#define GFXTIM_VERR_MINREV_Msk         (0xFUL << GFXTIM_VERR_MINREV_Pos)       /*!< 0x0000000F */
+#define GFXTIM_VERR_MINREV             GFXTIM_VERR_MINREV_Msk
+
+#define GFXTIM_VERR_MAJREV_Pos         (4U)
+#define GFXTIM_VERR_MAJREV_Msk         (0xFUL << GFXTIM_VERR_MAJREV_Pos)       /*!< 0x000000F0 */
+#define GFXTIM_VERR_MAJREV             GFXTIM_VERR_MAJREV_Msk
+
+/******************  Bits definition for GFXTIM_IPIDR register  ***************/
+#define GFXTIM_IPIDR_ID_Pos            (0U)
+#define GFXTIM_IPIDR_ID_Msk            (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_IPIDR_ID                GFXTIM_IPIDR_ID_Msk
+
+/******************  Bits definition for GFXTIM_SIDR register  ****************/
+#define GFXTIM_SIDR_SID_Pos            (0U)
+#define GFXTIM_SIDR_SID_Msk            (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_SIDR_SID                GFXTIM_SIDR_SID_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)
+#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos               (1U)
+#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos               (2U)
+#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos               (3U)
+#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos               (4U)
+#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos               (5U)
+#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos               (6U)
+#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos               (7U)
+#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos               (8U)
+#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos               (9U)
+#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos              (10U)
+#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos              (11U)
+#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos              (12U)
+#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos              (13U)
+#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos              (14U)
+#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos              (15U)
+#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
+
+/******************  Bits definition for GPIO_SECCFGR register  ******************/
+#define GPIO_SECCFGR_SEC0_Pos          (0U)
+#define GPIO_SECCFGR_SEC0_Msk          (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
+#define GPIO_SECCFGR_SEC0              GPIO_SECCFGR_SEC0_Msk
+#define GPIO_SECCFGR_SEC1_Pos          (1U)
+#define GPIO_SECCFGR_SEC1_Msk          (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
+#define GPIO_SECCFGR_SEC1              GPIO_SECCFGR_SEC1_Msk
+#define GPIO_SECCFGR_SEC2_Pos          (2U)
+#define GPIO_SECCFGR_SEC2_Msk          (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
+#define GPIO_SECCFGR_SEC2              GPIO_SECCFGR_SEC2_Msk
+#define GPIO_SECCFGR_SEC3_Pos          (3U)
+#define GPIO_SECCFGR_SEC3_Msk          (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
+#define GPIO_SECCFGR_SEC3              GPIO_SECCFGR_SEC3_Msk
+#define GPIO_SECCFGR_SEC4_Pos          (4U)
+#define GPIO_SECCFGR_SEC4_Msk          (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
+#define GPIO_SECCFGR_SEC4              GPIO_SECCFGR_SEC4_Msk
+#define GPIO_SECCFGR_SEC5_Pos          (5U)
+#define GPIO_SECCFGR_SEC5_Msk          (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
+#define GPIO_SECCFGR_SEC5              GPIO_SECCFGR_SEC5_Msk
+#define GPIO_SECCFGR_SEC6_Pos          (6U)
+#define GPIO_SECCFGR_SEC6_Msk          (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
+#define GPIO_SECCFGR_SEC6              GPIO_SECCFGR_SEC6_Msk
+#define GPIO_SECCFGR_SEC7_Pos          (7U)
+#define GPIO_SECCFGR_SEC7_Msk          (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
+#define GPIO_SECCFGR_SEC7              GPIO_SECCFGR_SEC7_Msk
+#define GPIO_SECCFGR_SEC8_Pos          (8U)
+#define GPIO_SECCFGR_SEC8_Msk          (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
+#define GPIO_SECCFGR_SEC8              GPIO_SECCFGR_SEC8_Msk
+#define GPIO_SECCFGR_SEC9_Pos          (9U)
+#define GPIO_SECCFGR_SEC9_Msk          (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
+#define GPIO_SECCFGR_SEC9              GPIO_SECCFGR_SEC9_Msk
+#define GPIO_SECCFGR_SEC10_Pos         (10U)
+#define GPIO_SECCFGR_SEC10_Msk         (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
+#define GPIO_SECCFGR_SEC10             GPIO_SECCFGR_SEC10_Msk
+#define GPIO_SECCFGR_SEC11_Pos         (11U)
+#define GPIO_SECCFGR_SEC11_Msk         (0x1UL << GPIO_SECCFGR_SEC11_Pos)       /*!< 0x00000800 */
+#define GPIO_SECCFGR_SEC11             GPIO_SECCFGR_SEC11_Msk
+#define GPIO_SECCFGR_SEC12_Pos         (12U)
+#define GPIO_SECCFGR_SEC12_Msk         (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
+#define GPIO_SECCFGR_SEC12             GPIO_SECCFGR_SEC12_Msk
+#define GPIO_SECCFGR_SEC13_Pos         (13U)
+#define GPIO_SECCFGR_SEC13_Msk         (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
+#define GPIO_SECCFGR_SEC13             GPIO_SECCFGR_SEC13_Msk
+#define GPIO_SECCFGR_SEC14_Pos         (14U)
+#define GPIO_SECCFGR_SEC14_Msk         (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
+#define GPIO_SECCFGR_SEC14             GPIO_SECCFGR_SEC14_Msk
+#define GPIO_SECCFGR_SEC15_Pos         (15U)
+#define GPIO_SECCFGR_SEC15_Msk         (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
+#define GPIO_SECCFGR_SEC15             GPIO_SECCFGR_SEC15_Msk
+
+/******************  Bits definition for GPIO_PRIVCFGR register  ******************/
+#define GPIO_PRIVCFGR_PRIV0_Pos        (0U)
+#define GPIO_PRIVCFGR_PRIV0_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV0_Pos)      /*!< 0x00000001 */
+#define GPIO_PRIVCFGR_PRIV0            GPIO_PRIVCFGR_PRIV0_Msk
+#define GPIO_PRIVCFGR_PRIV1_Pos        (1U)
+#define GPIO_PRIVCFGR_PRIV1_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV1_Pos)      /*!< 0x00000002 */
+#define GPIO_PRIVCFGR_PRIV1            GPIO_PRIVCFGR_PRIV1_Msk
+#define GPIO_PRIVCFGR_PRIV2_Pos        (2U)
+#define GPIO_PRIVCFGR_PRIV2_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV2_Pos)      /*!< 0x00000004 */
+#define GPIO_PRIVCFGR_PRIV2            GPIO_PRIVCFGR_PRIV2_Msk
+#define GPIO_PRIVCFGR_PRIV3_Pos        (3U)
+#define GPIO_PRIVCFGR_PRIV3_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV3_Pos)      /*!< 0x00000008 */
+#define GPIO_PRIVCFGR_PRIV3            GPIO_PRIVCFGR_PRIV3_Msk
+#define GPIO_PRIVCFGR_PRIV4_Pos        (4U)
+#define GPIO_PRIVCFGR_PRIV4_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV4_Pos)      /*!< 0x00000010 */
+#define GPIO_PRIVCFGR_PRIV4            GPIO_PRIVCFGR_PRIV4_Msk
+#define GPIO_PRIVCFGR_PRIV5_Pos        (5U)
+#define GPIO_PRIVCFGR_PRIV5_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV5_Pos)      /*!< 0x00000020 */
+#define GPIO_PRIVCFGR_PRIV5            GPIO_PRIVCFGR_PRIV5_Msk
+#define GPIO_PRIVCFGR_PRIV6_Pos        (6U)
+#define GPIO_PRIVCFGR_PRIV6_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV6_Pos)      /*!< 0x00000040 */
+#define GPIO_PRIVCFGR_PRIV6            GPIO_PRIVCFGR_PRIV6_Msk
+#define GPIO_PRIVCFGR_PRIV7_Pos        (7U)
+#define GPIO_PRIVCFGR_PRIV7_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV7_Pos)      /*!< 0x00000080 */
+#define GPIO_PRIVCFGR_PRIV7            GPIO_PRIVCFGR_PRIV7_Msk
+#define GPIO_PRIVCFGR_PRIV8_Pos        (8U)
+#define GPIO_PRIVCFGR_PRIV8_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV8_Pos)      /*!< 0x00000100 */
+#define GPIO_PRIVCFGR_PRIV8            GPIO_PRIVCFGR_PRIV8_Msk
+#define GPIO_PRIVCFGR_PRIV9_Pos        (9U)
+#define GPIO_PRIVCFGR_PRIV9_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV9_Pos)      /*!< 0x00000200 */
+#define GPIO_PRIVCFGR_PRIV9            GPIO_PRIVCFGR_PRIV9_Msk
+#define GPIO_PRIVCFGR_PRIV10_Pos       (10U)
+#define GPIO_PRIVCFGR_PRIV10_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV10_Pos)     /*!< 0x00000400 */
+#define GPIO_PRIVCFGR_PRIV10           GPIO_PRIVCFGR_PRIV10_Msk
+#define GPIO_PRIVCFGR_PRIV11_Pos       (11U)
+#define GPIO_PRIVCFGR_PRIV11_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV11_Pos)     /*!< 0x00000800 */
+#define GPIO_PRIVCFGR_PRIV11           GPIO_PRIVCFGR_PRIV11_Msk
+#define GPIO_PRIVCFGR_PRIV12_Pos       (12U)
+#define GPIO_PRIVCFGR_PRIV12_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV12_Pos)     /*!< 0x00001000 */
+#define GPIO_PRIVCFGR_PRIV12           GPIO_PRIVCFGR_PRIV12_Msk
+#define GPIO_PRIVCFGR_PRIV13_Pos       (13U)
+#define GPIO_PRIVCFGR_PRIV13_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV13_Pos)     /*!< 0x00002000 */
+#define GPIO_PRIVCFGR_PRIV13           GPIO_PRIVCFGR_PRIV13_Msk
+#define GPIO_PRIVCFGR_PRIV14_Pos       (14U)
+#define GPIO_PRIVCFGR_PRIV14_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV14_Pos)     /*!< 0x00004000 */
+#define GPIO_PRIVCFGR_PRIV14           GPIO_PRIVCFGR_PRIV14_Msk
+#define GPIO_PRIVCFGR_PRIV15_Pos       (15U)
+#define GPIO_PRIVCFGR_PRIV15_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV15_Pos)     /*!< 0x00008000 */
+#define GPIO_PRIVCFGR_PRIV15           GPIO_PRIVCFGR_PRIV15_Msk
+
+/******************  Bits definition for GPIO_RCFGLOCKR register  ******************/
+#define GPIO_RCFGLOCKR_RLOCK0_Pos      (0U)
+#define GPIO_RCFGLOCKR_RLOCK0_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK0_Pos)    /*!< 0x00000001 */
+#define GPIO_RCFGLOCKR_RLOCK0          GPIO_RCFGLOCKR_RLOCK0_Msk
+#define GPIO_RCFGLOCKR_RLOCK1_Pos      (1U)
+#define GPIO_RCFGLOCKR_RLOCK1_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK1_Pos)    /*!< 0x00000002 */
+#define GPIO_RCFGLOCKR_RLOCK1          GPIO_RCFGLOCKR_RLOCK1_Msk
+#define GPIO_RCFGLOCKR_RLOCK2_Pos      (2U)
+#define GPIO_RCFGLOCKR_RLOCK2_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK2_Pos)    /*!< 0x00000004 */
+#define GPIO_RCFGLOCKR_RLOCK2          GPIO_RCFGLOCKR_RLOCK2_Msk
+#define GPIO_RCFGLOCKR_RLOCK3_Pos      (3U)
+#define GPIO_RCFGLOCKR_RLOCK3_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK3_Pos)    /*!< 0x00000008 */
+#define GPIO_RCFGLOCKR_RLOCK3          GPIO_RCFGLOCKR_RLOCK3_Msk
+#define GPIO_RCFGLOCKR_RLOCK4_Pos      (4U)
+#define GPIO_RCFGLOCKR_RLOCK4_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK4_Pos)    /*!< 0x00000010 */
+#define GPIO_RCFGLOCKR_RLOCK4          GPIO_RCFGLOCKR_RLOCK4_Msk
+#define GPIO_RCFGLOCKR_RLOCK5_Pos      (5U)
+#define GPIO_RCFGLOCKR_RLOCK5_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK5_Pos)    /*!< 0x00000020 */
+#define GPIO_RCFGLOCKR_RLOCK5          GPIO_RCFGLOCKR_RLOCK5_Msk
+#define GPIO_RCFGLOCKR_RLOCK6_Pos      (6U)
+#define GPIO_RCFGLOCKR_RLOCK6_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK6_Pos)    /*!< 0x00000040 */
+#define GPIO_RCFGLOCKR_RLOCK6          GPIO_RCFGLOCKR_RLOCK6_Msk
+#define GPIO_RCFGLOCKR_RLOCK7_Pos      (7U)
+#define GPIO_RCFGLOCKR_RLOCK7_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK7_Pos)    /*!< 0x00000080 */
+#define GPIO_RCFGLOCKR_RLOCK7          GPIO_RCFGLOCKR_RLOCK7_Msk
+#define GPIO_RCFGLOCKR_RLOCK8_Pos      (8U)
+#define GPIO_RCFGLOCKR_RLOCK8_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK8_Pos)    /*!< 0x00000100 */
+#define GPIO_RCFGLOCKR_RLOCK8          GPIO_RCFGLOCKR_RLOCK8_Msk
+#define GPIO_RCFGLOCKR_RLOCK9_Pos      (9U)
+#define GPIO_RCFGLOCKR_RLOCK9_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK9_Pos)    /*!< 0x00000200 */
+#define GPIO_RCFGLOCKR_RLOCK9          GPIO_RCFGLOCKR_RLOCK9_Msk
+#define GPIO_RCFGLOCKR_RLOCK10_Pos     (10U)
+#define GPIO_RCFGLOCKR_RLOCK10_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK10_Pos)   /*!< 0x00000400 */
+#define GPIO_RCFGLOCKR_RLOCK10         GPIO_RCFGLOCKR_RLOCK10_Msk
+#define GPIO_RCFGLOCKR_RLOCK11_Pos     (11U)
+#define GPIO_RCFGLOCKR_RLOCK11_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK11_Pos)   /*!< 0x00000800 */
+#define GPIO_RCFGLOCKR_RLOCK11         GPIO_RCFGLOCKR_RLOCK11_Msk
+#define GPIO_RCFGLOCKR_RLOCK12_Pos     (12U)
+#define GPIO_RCFGLOCKR_RLOCK12_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK12_Pos)   /*!< 0x00001000 */
+#define GPIO_RCFGLOCKR_RLOCK12         GPIO_RCFGLOCKR_RLOCK12_Msk
+#define GPIO_RCFGLOCKR_RLOCK13_Pos     (13U)
+#define GPIO_RCFGLOCKR_RLOCK13_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK13_Pos)   /*!< 0x00002000 */
+#define GPIO_RCFGLOCKR_RLOCK13         GPIO_RCFGLOCKR_RLOCK13_Msk
+#define GPIO_RCFGLOCKR_RLOCK14_Pos     (14U)
+#define GPIO_RCFGLOCKR_RLOCK14_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK14_Pos)   /*!< 0x00004000 */
+#define GPIO_RCFGLOCKR_RLOCK14         GPIO_RCFGLOCKR_RLOCK14_Msk
+#define GPIO_RCFGLOCKR_RLOCK15_Pos     (15U)
+#define GPIO_RCFGLOCKR_RLOCK15_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK15_Pos)   /*!< 0x00008000 */
+#define GPIO_RCFGLOCKR_RLOCK15         GPIO_RCFGLOCKR_RLOCK15_Msk
+
+/****************** Bit definition for GPIO_DELAYRL register *********************/
+#define GPIO_DELAYRL_DLY0_Pos        (0U)
+#define GPIO_DELAYRL_DLY0_Msk        (0xFUL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRL_DLY0            GPIO_DELAYRL_DLY0_Msk
+#define GPIO_DELAYRL_DLY0_0          (0x1UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRL_DLY0_1          (0x2UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRL_DLY0_2          (0x4UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRL_DLY0_3          (0x8UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRL_DLY1_Pos        (4U)
+#define GPIO_DELAYRL_DLY1_Msk        (0xFUL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRL_DLY1            GPIO_DELAYRL_DLY1_Msk
+#define GPIO_DELAYRL_DLY1_0          (0x1UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRL_DLY1_1          (0x2UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRL_DLY1_2          (0x4UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRL_DLY1_3          (0x8UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRL_DLY2_Pos        (8U)
+#define GPIO_DELAYRL_DLY2_Msk        (0xFUL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000F00 */
+#define GPIO_DELAYRL_DLY2            GPIO_DELAYRL_DLY2_Msk
+#define GPIO_DELAYRL_DLY2_0          (0x1UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000100 */
+#define GPIO_DELAYRL_DLY2_1          (0x2UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000200 */
+#define GPIO_DELAYRL_DLY2_2          (0x4UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000400 */
+#define GPIO_DELAYRL_DLY2_3          (0x8UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000800 */
+#define GPIO_DELAYRL_DLY3_Pos        (12U)
+#define GPIO_DELAYRL_DLY3_Msk        (0xFUL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x0000F000 */
+#define GPIO_DELAYRL_DLY3            GPIO_DELAYRL_DLY3_Msk
+#define GPIO_DELAYRL_DLY3_0          (0x1UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00001000 */
+#define GPIO_DELAYRL_DLY3_1          (0x2UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00002000 */
+#define GPIO_DELAYRL_DLY3_2          (0x4UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00004000 */
+#define GPIO_DELAYRL_DLY3_3          (0x8UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00008000 */
+#define GPIO_DELAYRL_DLY4_Pos        (16U)
+#define GPIO_DELAYRL_DLY4_Msk        (0xFUL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x000F0000 */
+#define GPIO_DELAYRL_DLY4            GPIO_DELAYRL_DLY4_Msk
+#define GPIO_DELAYRL_DLY4_0          (0x1UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00010000 */
+#define GPIO_DELAYRL_DLY4_1          (0x2UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00020000 */
+#define GPIO_DELAYRL_DLY4_2          (0x4UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00040000 */
+#define GPIO_DELAYRL_DLY4_3          (0x8UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00080000 */
+#define GPIO_DELAYRL_DLY5_Pos        (20U)
+#define GPIO_DELAYRL_DLY5_Msk        (0xFUL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00F00000 */
+#define GPIO_DELAYRL_DLY5            GPIO_DELAYRL_DLY5_Msk
+#define GPIO_DELAYRL_DLY5_0          (0x1UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00100000 */
+#define GPIO_DELAYRL_DLY5_1          (0x2UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00200000 */
+#define GPIO_DELAYRL_DLY5_2          (0x4UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00400000 */
+#define GPIO_DELAYRL_DLY5_3          (0x8UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00800000 */
+#define GPIO_DELAYRL_DLY6_Pos        (24U)
+#define GPIO_DELAYRL_DLY6_Msk        (0xFUL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x0F000000 */
+#define GPIO_DELAYRL_DLY6            GPIO_DELAYRL_DLY6_Msk
+#define GPIO_DELAYRL_DLY6_0          (0x1UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x01000000 */
+#define GPIO_DELAYRL_DLY6_1          (0x2UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x02000000 */
+#define GPIO_DELAYRL_DLY6_2          (0x4UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x04000000 */
+#define GPIO_DELAYRL_DLY6_3          (0x8UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x08000000 */
+#define GPIO_DELAYRL_DLY7_Pos        (28U)
+#define GPIO_DELAYRL_DLY7_Msk        (0xFUL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0xF0000000 */
+#define GPIO_DELAYRL_DLY7            GPIO_DELAYRL_DLY7_Msk
+#define GPIO_DELAYRL_DLY7_0          (0x1UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x10000000 */
+#define GPIO_DELAYRL_DLY7_1          (0x2UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x20000000 */
+#define GPIO_DELAYRL_DLY7_2          (0x4UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x40000000 */
+#define GPIO_DELAYRL_DLY7_3          (0x8UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_DELAYRH register *********************/
+#define GPIO_DELAYRH_DLY8_Pos        (0U)
+#define GPIO_DELAYRH_DLY8_Msk        (0xFUL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRH_DLY8            GPIO_DELAYRH_DLY8_Msk
+#define GPIO_DELAYRH_DLY8_0          (0x1UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRH_DLY8_1          (0x2UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRH_DLY8_2          (0x4UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRH_DLY8_3          (0x8UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRH_DLY9_Pos        (4U)
+#define GPIO_DELAYRH_DLY9_Msk        (0xFUL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRH_DLY9            GPIO_DELAYRH_DLY9_Msk
+#define GPIO_DELAYRH_DLY9_0          (0x1UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRH_DLY9_1          (0x2UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRH_DLY9_2          (0x4UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRH_DLY9_3          (0x8UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRH_DLY10_Pos       (8U)
+#define GPIO_DELAYRH_DLY10_Msk       (0xFUL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000F00 */
+#define GPIO_DELAYRH_DLY10           GPIO_DELAYRH_DLY10_Msk
+#define GPIO_DELAYRH_DLY10_0         (0x1UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000100 */
+#define GPIO_DELAYRH_DLY10_1         (0x2UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000200 */
+#define GPIO_DELAYRH_DLY10_2         (0x4UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000400 */
+#define GPIO_DELAYRH_DLY10_3         (0x8UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000800 */
+#define GPIO_DELAYRH_DLY11_Pos       (12U)
+#define GPIO_DELAYRH_DLY11_Msk       (0xFUL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x0000F000 */
+#define GPIO_DELAYRH_DLY11           GPIO_DELAYRH_DLY11_Msk
+#define GPIO_DELAYRH_DLY11_0         (0x1UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00001000 */
+#define GPIO_DELAYRH_DLY11_1         (0x2UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00002000 */
+#define GPIO_DELAYRH_DLY11_2         (0x4UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00004000 */
+#define GPIO_DELAYRH_DLY11_3         (0x8UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00008000 */
+#define GPIO_DELAYRH_DLY12_Pos       (16U)
+#define GPIO_DELAYRH_DLY12_Msk       (0xFUL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x000F0000 */
+#define GPIO_DELAYRH_DLY12           GPIO_DELAYRH_DLY12_Msk
+#define GPIO_DELAYRH_DLY12_0         (0x1UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00010000 */
+#define GPIO_DELAYRH_DLY12_1         (0x2UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00020000 */
+#define GPIO_DELAYRH_DLY12_2         (0x4UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00040000 */
+#define GPIO_DELAYRH_DLY12_3         (0x8UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00080000 */
+#define GPIO_DELAYRH_DLY13_Pos       (20U)
+#define GPIO_DELAYRH_DLY13_Msk       (0xFUL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00F00000 */
+#define GPIO_DELAYRH_DLY13           GPIO_DELAYRH_DLY13_Msk
+#define GPIO_DELAYRH_DLY13_0         (0x1UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00100000 */
+#define GPIO_DELAYRH_DLY13_1         (0x2UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00200000 */
+#define GPIO_DELAYRH_DLY13_2         (0x4UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00400000 */
+#define GPIO_DELAYRH_DLY13_3         (0x8UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00800000 */
+#define GPIO_DELAYRH_DLY14_Pos       (24U)
+#define GPIO_DELAYRH_DLY14_Msk       (0xFUL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x0F000000 */
+#define GPIO_DELAYRH_DLY14           GPIO_DELAYRH_DLY14_Msk
+#define GPIO_DELAYRH_DLY14_0         (0x1UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x01000000 */
+#define GPIO_DELAYRH_DLY14_1         (0x2UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x02000000 */
+#define GPIO_DELAYRH_DLY14_2         (0x4UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x04000000 */
+#define GPIO_DELAYRH_DLY14_3         (0x8UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x08000000 */
+#define GPIO_DELAYRH_DLY15_Pos       (28U)
+#define GPIO_DELAYRH_DLY15_Msk       (0xFUL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0xF0000000 */
+#define GPIO_DELAYRH_DLY15           GPIO_DELAYRH_DLY15_Msk
+#define GPIO_DELAYRH_DLY15_0         (0x1UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x10000000 */
+#define GPIO_DELAYRH_DLY15_1         (0x2UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x20000000 */
+#define GPIO_DELAYRH_DLY15_2         (0x4UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x40000000 */
+#define GPIO_DELAYRH_DLY15_3         (0x8UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRL register *********************/
+#define GPIO_ADVCFGRL_0_Pos            (0U)
+#define GPIO_ADVCFGRL_0_Msk            (0xFUL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRL_0                GPIO_ADVCFGRL_0_Msk
+#define GPIO_ADVCFGRL_DLYPATH0         (0x1UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRL_DE0              (0x2UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRL_INVCLK0          (0x4UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRL_RET0             (0x8UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRL_1_Pos            (4U)
+#define GPIO_ADVCFGRL_1_Msk            (0xFUL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRL_1                GPIO_ADVCFGRL_1_Msk
+#define GPIO_ADVCFGRL_DLYPATH1         (0x1UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRL_DE1              (0x2UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRL_INVCLK1          (0x4UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRL_RET1             (0x8UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRL_2_Pos            (8U)
+#define GPIO_ADVCFGRL_2_Msk            (0xFUL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000F00 */
+#define GPIO_ADVCFGRL_2                GPIO_ADVCFGRL_2_Msk
+#define GPIO_ADVCFGRL_DLYPATH2         (0x1UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000100 */
+#define GPIO_ADVCFGRL_DE2              (0x2UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000200 */
+#define GPIO_ADVCFGRL_INVCLK2          (0x4UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000400 */
+#define GPIO_ADVCFGRL_RET2             (0x8UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000800 */
+#define GPIO_ADVCFGRL_3_Pos            (12U)
+#define GPIO_ADVCFGRL_3_Msk            (0xFUL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x0000F000 */
+#define GPIO_ADVCFGRL_3                GPIO_ADVCFGRL_3_Msk
+#define GPIO_ADVCFGRL_DLYPATH3         (0x1UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00001000 */
+#define GPIO_ADVCFGRL_DE3              (0x2UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00002000 */
+#define GPIO_ADVCFGRL_INVCLK3          (0x4UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00004000 */
+#define GPIO_ADVCFGRL_RET3             (0x8UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00008000 */
+#define GPIO_ADVCFGRL_4_Pos            (16U)
+#define GPIO_ADVCFGRL_4_Msk            (0xFUL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x000F0000 */
+#define GPIO_ADVCFGRL_4                GPIO_ADVCFGRL_4_Msk
+#define GPIO_ADVCFGRL_DLYPATH4         (0x1UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00010000 */
+#define GPIO_ADVCFGRL_DE4              (0x2UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00020000 */
+#define GPIO_ADVCFGRL_INVCLK4          (0x4UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00040000 */
+#define GPIO_ADVCFGRL_RET4             (0x8UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00080000 */
+#define GPIO_ADVCFGRL_5_Pos            (20U)
+#define GPIO_ADVCFGRL_5_Msk            (0xFUL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00F00000 */
+#define GPIO_ADVCFGRL_5                GPIO_ADVCFGRL_5_Msk
+#define GPIO_ADVCFGRL_DLYPATH5         (0x1UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00100000 */
+#define GPIO_ADVCFGRL_DE5              (0x2UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00200000 */
+#define GPIO_ADVCFGRL_INVCLK5          (0x4UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00400000 */
+#define GPIO_ADVCFGRL_RET5             (0x8UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00800000 */
+#define GPIO_ADVCFGRL_6_Pos            (24U)
+#define GPIO_ADVCFGRL_6_Msk            (0xFUL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x0F000000 */
+#define GPIO_ADVCFGRL_6                GPIO_ADVCFGRL_6_Msk
+#define GPIO_ADVCFGRL_DLYPATH6         (0x1UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x01000000 */
+#define GPIO_ADVCFGRL_DE6              (0x2UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x02000000 */
+#define GPIO_ADVCFGRL_INVCLK6          (0x4UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x04000000 */
+#define GPIO_ADVCFGRL_RET6             (0x8UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x08000000 */
+#define GPIO_ADVCFGRL_7_Pos            (28U)
+#define GPIO_ADVCFGRL_7_Msk            (0xFUL << GPIO_ADVCFGRL_7_Pos)          /*!< 0xF0000000 */
+#define GPIO_ADVCFGRL_7                GPIO_ADVCFGRL_7_Msk
+#define GPIO_ADVCFGRL_DLYPATH7         (0x1UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x10000000 */
+#define GPIO_ADVCFGRL_DE7              (0x2UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x20000000 */
+#define GPIO_ADVCFGRL_INVCLK7          (0x4UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x40000000 */
+#define GPIO_ADVCFGRL_RET7             (0x8UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRH register *********************/
+#define GPIO_ADVCFGRH_8_Pos            (0U)
+#define GPIO_ADVCFGRH_8_Msk            (0xFUL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRH_8                GPIO_ADVCFGRH_8_Msk
+#define GPIO_ADVCFGRH_DLYPATH8         (0x1UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRH_DE8              (0x2UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRH_INVCLK8          (0x4UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRH_RET8             (0x8UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRH_9_Pos            (4U)
+#define GPIO_ADVCFGRH_9_Msk            (0xFUL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRH_9                GPIO_ADVCFGRH_9_Msk
+#define GPIO_ADVCFGRH_DLYPATH9         (0x1UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRH_DE9              (0x2UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRH_INVCLK9          (0x4UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRH_RET9             (0x8UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRH_10_Pos           (8U)
+#define GPIO_ADVCFGRH_10_Msk           (0xFUL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000F00 */
+#define GPIO_ADVCFGRH_10               GPIO_ADVCFGRH_10_Msk
+#define GPIO_ADVCFGRH_DLYPATH10        (0x1UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000100 */
+#define GPIO_ADVCFGRH_DE10             (0x2UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000200 */
+#define GPIO_ADVCFGRH_INVCLK10         (0x4UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000400 */
+#define GPIO_ADVCFGRH_RET10            (0x8UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000800 */
+#define GPIO_ADVCFGRH_11_Pos           (12U)
+#define GPIO_ADVCFGRH_11_Msk           (0xFUL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x0000F000 */
+#define GPIO_ADVCFGRH_11               GPIO_ADVCFGRH_11_Msk
+#define GPIO_ADVCFGRH_DLYPATH11        (0x1UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00001000 */
+#define GPIO_ADVCFGRH_DE11             (0x2UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00002000 */
+#define GPIO_ADVCFGRH_INVCLK11         (0x4UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00004000 */
+#define GPIO_ADVCFGRH_RET11            (0x8UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00008000 */
+#define GPIO_ADVCFGRH_12_Pos           (16U)
+#define GPIO_ADVCFGRH_12_Msk           (0xFUL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x000F0000 */
+#define GPIO_ADVCFGRH_12               GPIO_ADVCFGRH_12_Msk
+#define GPIO_ADVCFGRH_DLYPATH12        (0x1UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00010000 */
+#define GPIO_ADVCFGRH_DE12             (0x2UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00020000 */
+#define GPIO_ADVCFGRH_INVCLK12         (0x4UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00040000 */
+#define GPIO_ADVCFGRH_RET12            (0x8UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00080000 */
+#define GPIO_ADVCFGRH_13_Pos           (20U)
+#define GPIO_ADVCFGRH_13_Msk           (0xFUL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00F00000 */
+#define GPIO_ADVCFGRH_13               GPIO_ADVCFGRH_13_Msk
+#define GPIO_ADVCFGRH_DLYPATH13        (0x1UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00100000 */
+#define GPIO_ADVCFGRH_DE13             (0x2UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00200000 */
+#define GPIO_ADVCFGRH_INVCLK13         (0x4UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00400000 */
+#define GPIO_ADVCFGRH_RET13            (0x8UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00800000 */
+#define GPIO_ADVCFGRH_14_Pos           (24U)
+#define GPIO_ADVCFGRH_14_Msk           (0xFUL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x0F000000 */
+#define GPIO_ADVCFGRH_14               GPIO_ADVCFGRH_14_Msk
+#define GPIO_ADVCFGRH_DLYPATH14        (0x1UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x01000000 */
+#define GPIO_ADVCFGRH_DE14             (0x2UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x02000000 */
+#define GPIO_ADVCFGRH_INVCLK14         (0x4UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x04000000 */
+#define GPIO_ADVCFGRH_RET14            (0x8UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x08000000 */
+#define GPIO_ADVCFGRH_15_Pos           (28U)
+#define GPIO_ADVCFGRH_15_Msk           (0xFUL << GPIO_ADVCFGRH_15_Pos)         /*!< 0xF0000000 */
+#define GPIO_ADVCFGRH_15               GPIO_ADVCFGRH_15_Msk
+#define GPIO_ADVCFGRH_DLYPATH15        (0x1UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x10000000 */
+#define GPIO_ADVCFGRH_DE15             (0x2UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x20000000 */
+#define GPIO_ADVCFGRH_INVCLK15         (0x4UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x40000000 */
+#define GPIO_ADVCFGRH_RET15            (0x8UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x80000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT_Pos                    (2U)
+#define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
+#define HASH_CR_INIT                        HASH_CR_INIT_Msk
+#define HASH_CR_DMAE_Pos                    (3U)
+#define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
+#define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
+#define HASH_CR_DATATYPE_Pos                (4U)
+#define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
+#define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
+#define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos                    (6U)
+#define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
+#define HASH_CR_MODE                        HASH_CR_MODE_Msk
+#define HASH_CR_NBW_Pos                     (8U)
+#define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
+#define HASH_CR_NBW                         HASH_CR_NBW_Msk
+#define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
+#define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
+#define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
+#define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos                   (12U)
+#define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
+#define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
+#define HASH_CR_MDMAT_Pos                   (13U)
+#define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
+#define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
+#define HASH_CR_LKEY_Pos                    (16U)
+#define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
+#define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
+#define HASH_CR_ALGO_Pos                    (17U)
+#define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
+#define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
+#define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
+#define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
+#define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
+#define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBLW_Pos                   (0U)
+#define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
+#define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
+#define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
+#define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
+#define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
+#define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
+#define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos                   (8U)
+#define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
+#define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIE_Pos                  (0U)
+#define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
+#define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
+#define HASH_IMR_DCIE_Pos                   (1U)
+#define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
+#define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS_Pos                   (0U)
+#define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
+#define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
+#define HASH_SR_DCIS_Pos                    (1U)
+#define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
+#define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
+#define HASH_SR_DMAS_Pos                    (2U)
+#define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
+#define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
+#define HASH_SR_BUSY_Pos                    (3U)
+#define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
+#define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
+#define HASH_SR_NBWE_Pos                    (16U)
+#define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
+#define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
+#define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
+#define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
+#define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
+#define HASH_SR_DINNE_Pos                   (15U)
+#define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
+#define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
+#define HASH_SR_NBWP_Pos                    (9U)
+#define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
+#define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
+#define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
+#define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
+#define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos                      (0U)
+#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
+#define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos                    (1U)
+#define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
+#define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos                    (2U)
+#define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
+#define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos                  (3U)
+#define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos                  (4U)
+#define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
+#define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos                  (5U)
+#define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
+#define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos                    (6U)
+#define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos                   (7U)
+#define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos                     (8U)
+#define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
+#define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos                  (12U)
+#define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos                   (13U)
+#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
+#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos                 (14U)
+#define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos                 (15U)
+#define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos                     (16U)
+#define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
+#define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos               (17U)
+#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos                   (18U)
+#define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos                    (19U)
+#define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
+#define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos                  (20U)
+#define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos                  (21U)
+#define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos                 (22U)
+#define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos                   (23U)
+#define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
+#define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
+#define I2C_CR1_FMP_Pos                     (24U)
+#define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
+#define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
+#define I2C_CR1_ADDRACLR_Pos                (30U)
+#define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
+#define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
+#define I2C_CR1_STOPFACLR_Pos               (31U)
+#define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
+#define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos                    (0U)
+#define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
+#define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos                  (10U)
+#define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos                   (11U)
+#define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
+#define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos                 (12U)
+#define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos                   (13U)
+#define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
+#define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
+#define I2C_CR2_STOP_Pos                    (14U)
+#define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
+#define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos                    (15U)
+#define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
+#define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos                  (16U)
+#define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos                  (24U)
+#define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
+#define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos                 (25U)
+#define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos                 (26U)
+#define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos                    (0U)
+#define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
+#define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos                (10U)
+#define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos                  (15U)
+#define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos                    (1U)
+#define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
+#define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos                 (8U)
+#define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos              (8U)
+#define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos              (9U)
+#define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos              (8U)
+#define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos              (10U)
+#define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos              (8U)
+#define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos              (9U)
+#define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos              (8U)
+#define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos                  (15U)
+#define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos                (0U)
+#define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos                (8U)
+#define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos              (16U)
+#define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos              (20U)
+#define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos               (28U)
+#define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos              (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos                     (0U)
+#define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
+#define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos                    (1U)
+#define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
+#define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos                    (2U)
+#define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
+#define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos                    (3U)
+#define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
+#define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos                   (4U)
+#define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
+#define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos                   (5U)
+#define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
+#define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos                      (6U)
+#define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
+#define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos                     (7U)
+#define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
+#define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos                    (8U)
+#define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
+#define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
+#define I2C_ISR_ARLO_Pos                    (9U)
+#define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
+#define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos                     (10U)
+#define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
+#define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos                  (11U)
+#define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
+#define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos                 (12U)
+#define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos                   (13U)
+#define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
+#define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos                    (15U)
+#define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
+#define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
+#define I2C_ISR_DIR_Pos                     (16U)
+#define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
+#define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos                 (17U)
+#define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos                  (3U)
+#define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos                  (4U)
+#define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
+#define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos                  (5U)
+#define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
+#define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos                  (8U)
+#define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
+#define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos                  (9U)
+#define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos                   (10U)
+#define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos                   (11U)
+#define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
+#define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos                (12U)
+#define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos                 (13U)
+#define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos                    (0U)
+#define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
+#define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos                 (0U)
+#define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos                 (0U)
+#define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Improved Inter-integrated Circuit Interface (I3C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I3C_CR register  *********************/
+#define I3C_CR_DCNT_Pos                     (0U)
+#define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
+#define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
+#define I3C_CR_RNW_Pos                      (16U)
+#define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
+#define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
+#define I3C_CR_CCC_Pos                      (16U)
+#define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
+#define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
+#define I3C_CR_ADD_Pos                      (17U)
+#define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
+#define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
+#define I3C_CR_MTYPE_Pos                    (27U)
+#define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
+#define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
+#define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
+#define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
+#define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
+#define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
+#define I3C_CR_MEND_Pos                     (31U)
+#define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
+#define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
+
+/*******************  Bit definition for I3C_CFGR register  *******************/
+#define I3C_CFGR_EN_Pos                     (0U)
+#define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
+#define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
+#define I3C_CFGR_CRINIT_Pos                 (1U)
+#define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
+#define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
+#define I3C_CFGR_NOARBH_Pos                 (2U)
+#define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
+#define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
+#define I3C_CFGR_RSTPTRN_Pos                (3U)
+#define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
+#define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
+#define I3C_CFGR_EXITPTRN_Pos               (4U)
+#define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
+#define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
+#define I3C_CFGR_HKSDAEN_Pos                (5U)
+#define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
+#define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
+#define I3C_CFGR_HJACK_Pos                  (7U)
+#define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
+#define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
+#define I3C_CFGR_RXDMAEN_Pos                (8U)
+#define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
+#define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
+#define I3C_CFGR_RXFLUSH_Pos                (9U)
+#define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
+#define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
+#define I3C_CFGR_RXTHRES_Pos                (10U)
+#define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
+#define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
+#define I3C_CFGR_TXDMAEN_Pos                (12U)
+#define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
+#define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
+#define I3C_CFGR_TXFLUSH_Pos                (13U)
+#define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
+#define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
+#define I3C_CFGR_TXTHRES_Pos                (14U)
+#define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
+#define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
+#define I3C_CFGR_SDMAEN_Pos                 (16U)
+#define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
+#define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
+#define I3C_CFGR_SFLUSH_Pos                 (17U)
+#define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
+#define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
+#define I3C_CFGR_SMODE_Pos                  (18U)
+#define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
+#define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
+#define I3C_CFGR_TMODE_Pos                  (19U)
+#define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
+#define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
+#define I3C_CFGR_CDMAEN_Pos                 (20U)
+#define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
+#define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
+#define I3C_CFGR_CFLUSH_Pos                 (21U)
+#define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
+#define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
+#define I3C_CFGR_TSFSET_Pos                 (30U)
+#define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
+#define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
+
+/*******************  Bit definition for I3C_RDR register  ********************/
+#define I3C_RDR_RDB0_Pos                    (0U)
+#define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
+#define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
+
+/******************  Bit definition for I3C_RDWR register  ********************/
+#define I3C_RDWR_RDBx_Pos                   (0U)
+#define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
+#define I3C_RDWR_RDB0_Pos                   (0U)
+#define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
+#define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
+#define I3C_RDWR_RDB1_Pos                   (8U)
+#define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
+#define I3C_RDWR_RDB2_Pos                   (16U)
+#define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
+#define I3C_RDWR_RDB3_Pos                   (24U)
+#define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
+
+/*******************  Bit definition for I3C_TDR register  ********************/
+#define I3C_TDR_TDB0_Pos                    (0U)
+#define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
+#define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
+
+/******************  Bit definition for I3C_TDWR register  ********************/
+#define I3C_TDWR_TDBx_Pos                   (0U)
+#define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
+#define I3C_TDWR_TDB0_Pos                   (0U)
+#define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
+#define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
+#define I3C_TDWR_TDB1_Pos                   (8U)
+#define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
+#define I3C_TDWR_TDB2_Pos                   (16U)
+#define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
+#define I3C_TDWR_TDB3_Pos                   (24U)
+#define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
+
+/*******************  Bit definition for I3C_IBIDR register  ******************/
+#define I3C_IBIDR_IBIDBx_Pos                (0U)
+#define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
+#define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
+#define I3C_IBIDR_IBIDB0_Pos                (0U)
+#define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
+#define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
+#define I3C_IBIDR_IBIDB1_Pos                (8U)
+#define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
+#define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
+#define I3C_IBIDR_IBIDB2_Pos                (16U)
+#define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
+#define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
+#define I3C_IBIDR_IBIDB3_Pos                (24U)
+#define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
+#define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
+
+/******************  Bit definition for I3C_TGTTDR register  ******************/
+#define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
+#define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
+#define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
+#define I3C_TGTTDR_PRELOAD_Pos              (16U)
+#define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
+#define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
+
+/*******************  Bit definition for I3C_SR register  *********************/
+#define I3C_SR_XDCNT_Pos                    (0U)
+#define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
+#define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
+#define I3C_SR_ABT_Pos                      (17U)
+#define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
+#define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
+#define I3C_SR_DIR_Pos                      (18U)
+#define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
+#define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
+#define I3C_SR_MID_Pos                      (24U)
+#define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
+#define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
+
+/*******************  Bit definition for I3C_SER register  ********************/
+#define I3C_SER_CODERR_Pos                  (0U)
+#define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
+#define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
+#define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
+#define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
+#define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
+#define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
+#define I3C_SER_PERR_Pos                    (4U)
+#define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
+#define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
+#define I3C_SER_STALL_Pos                   (5U)
+#define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
+#define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
+#define I3C_SER_DOVR_Pos                    (6U)
+#define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
+#define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
+#define I3C_SER_COVR_Pos                    (7U)
+#define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
+#define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
+#define I3C_SER_ANACK_Pos                   (8U)
+#define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
+#define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
+#define I3C_SER_DNACK_Pos                   (9U)
+#define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
+#define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
+#define I3C_SER_DERR_Pos                    (10U)
+#define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
+#define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
+
+/*******************  Bit definition for I3C_RMR register  ********************/
+#define I3C_RMR_IBIRDCNT_Pos                (0U)
+#define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
+#define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
+#define I3C_RMR_RCODE_Pos                   (8U)
+#define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
+#define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
+#define I3C_RMR_RADD_Pos                    (17U)
+#define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
+#define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
+
+/*******************  Bit definition for I3C_EVR register  ********************/
+#define I3C_EVR_CFEF_Pos                    (0U)
+#define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
+#define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
+#define I3C_EVR_TXFEF_Pos                   (1U)
+#define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
+#define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
+#define I3C_EVR_CFNFF_Pos                   (2U)
+#define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
+#define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
+#define I3C_EVR_SFNEF_Pos                   (3U)
+#define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
+#define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
+#define I3C_EVR_TXFNFF_Pos                  (4U)
+#define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
+#define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
+#define I3C_EVR_RXFNEF_Pos                  (5U)
+#define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
+#define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
+#define I3C_EVR_TXLASTF_Pos                 (6U)
+#define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
+#define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
+#define I3C_EVR_RXLASTF_Pos                 (7U)
+#define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
+#define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
+#define I3C_EVR_FCF_Pos                     (9U)
+#define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
+#define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
+#define I3C_EVR_RXTGTENDF_Pos               (10U)
+#define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
+#define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
+#define I3C_EVR_ERRF_Pos                    (11U)
+#define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
+#define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
+#define I3C_EVR_IBIF_Pos                    (15U)
+#define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
+#define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
+#define I3C_EVR_IBIENDF_Pos                 (16U)
+#define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
+#define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
+#define I3C_EVR_CRF_Pos                     (17U)
+#define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
+#define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
+#define I3C_EVR_CRUPDF_Pos                  (18U)
+#define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
+#define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
+#define I3C_EVR_HJF_Pos                     (19U)
+#define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
+#define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
+#define I3C_EVR_WKPF_Pos                    (21U)
+#define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
+#define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
+#define I3C_EVR_GETF_Pos                    (22U)
+#define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
+#define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
+#define I3C_EVR_STAF_Pos                    (23U)
+#define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
+#define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
+#define I3C_EVR_DAUPDF_Pos                  (24U)
+#define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
+#define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
+#define I3C_EVR_MWLUPDF_Pos                 (25U)
+#define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
+#define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
+#define I3C_EVR_MRLUPDF_Pos                 (26U)
+#define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
+#define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
+#define I3C_EVR_RSTF_Pos                    (27U)
+#define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
+#define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
+#define I3C_EVR_ASUPDF_Pos                  (28U)
+#define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
+#define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
+#define I3C_EVR_INTUPDF_Pos                 (29U)
+#define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
+#define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
+#define I3C_EVR_DEFF_Pos                    (30U)
+#define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
+#define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
+#define I3C_EVR_GRPF_Pos                    (31U)
+#define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
+#define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
+
+/*******************  Bit definition for I3C_IER register  ********************/
+#define I3C_IER_CFNFIE_Pos                  (2U)
+#define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
+#define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
+#define I3C_IER_SFNEIE_Pos                  (3U)
+#define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
+#define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
+#define I3C_IER_TXFNFIE_Pos                 (4U)
+#define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
+#define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
+#define I3C_IER_RXFNEIE_Pos                 (5U)
+#define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
+#define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
+#define I3C_IER_FCIE_Pos                    (9U)
+#define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
+#define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
+#define I3C_IER_RXTGTENDIE_Pos              (10U)
+#define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
+#define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
+#define I3C_IER_ERRIE_Pos                   (11U)
+#define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
+#define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
+#define I3C_IER_IBIIE_Pos                   (15U)
+#define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
+#define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
+#define I3C_IER_IBIENDIE_Pos                (16U)
+#define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
+#define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
+#define I3C_IER_CRIE_Pos                    (17U)
+#define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
+#define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
+#define I3C_IER_CRUPDIE_Pos                 (18U)
+#define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
+#define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
+#define I3C_IER_HJIE_Pos                    (19U)
+#define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
+#define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
+#define I3C_IER_WKPIE_Pos                   (21U)
+#define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
+#define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
+#define I3C_IER_GETIE_Pos                   (22U)
+#define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
+#define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
+#define I3C_IER_STAIE_Pos                   (23U)
+#define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
+#define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
+#define I3C_IER_DAUPDIE_Pos                 (24U)
+#define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
+#define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
+#define I3C_IER_MWLUPDIE_Pos                (25U)
+#define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
+#define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
+#define I3C_IER_MRLUPDIE_Pos                (26U)
+#define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
+#define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
+#define I3C_IER_RSTIE_Pos                   (27U)
+#define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
+#define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
+#define I3C_IER_ASUPDIE_Pos                 (28U)
+#define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
+#define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
+#define I3C_IER_INTUPDIE_Pos                (29U)
+#define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
+#define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
+#define I3C_IER_DEFIE_Pos                   (30U)
+#define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
+#define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
+#define I3C_IER_GRPIE_Pos                   (31U)
+#define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
+#define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
+
+/*******************  Bit definition for I3C_CEVR register  *******************/
+#define I3C_CEVR_CFCF_Pos                   (9U)
+#define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
+#define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
+#define I3C_CEVR_CRXTGTENDF_Pos             (10U)
+#define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
+#define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
+#define I3C_CEVR_CERRF_Pos                  (11U)
+#define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
+#define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
+#define I3C_CEVR_CIBIF_Pos                  (15U)
+#define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
+#define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
+#define I3C_CEVR_CIBIENDF_Pos               (16U)
+#define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
+#define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
+#define I3C_CEVR_CCRF_Pos                   (17U)
+#define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
+#define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
+#define I3C_CEVR_CCRUPDF_Pos                (18U)
+#define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
+#define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
+#define I3C_CEVR_CHJF_Pos                   (19U)
+#define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
+#define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
+#define I3C_CEVR_CWKPF_Pos                  (21U)
+#define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
+#define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
+#define I3C_CEVR_CGETF_Pos                  (22U)
+#define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
+#define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
+#define I3C_CEVR_CSTAF_Pos                  (23U)
+#define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
+#define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
+#define I3C_CEVR_CDAUPDF_Pos                (24U)
+#define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
+#define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
+#define I3C_CEVR_CMWLUPDF_Pos               (25U)
+#define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
+#define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
+#define I3C_CEVR_CMRLUPDF_Pos               (26U)
+#define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
+#define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
+#define I3C_CEVR_CRSTF_Pos                  (27U)
+#define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
+#define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
+#define I3C_CEVR_CASUPDF_Pos                (28U)
+#define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
+#define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
+#define I3C_CEVR_CINTUPDF_Pos               (29U)
+#define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
+#define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
+#define I3C_CEVR_CDEFF_Pos                  (30U)
+#define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
+#define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
+#define I3C_CEVR_CGRPF_Pos                  (31U)
+#define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
+#define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
+
+/******************  Bit definition for I3C_DEVR0 register  *******************/
+#define I3C_DEVR0_DAVAL_Pos                 (0U)
+#define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
+#define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
+#define I3C_DEVR0_DA_Pos                    (1U)
+#define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
+#define I3C_DEVR0_IBIEN_Pos                 (16U)
+#define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
+#define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
+#define I3C_DEVR0_CREN_Pos                  (17U)
+#define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
+#define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
+#define I3C_DEVR0_HJEN_Pos                  (19U)
+#define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
+#define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
+#define I3C_DEVR0_AS_Pos                    (20U)
+#define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
+#define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
+#define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
+#define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
+#define I3C_DEVR0_RSTACT_Pos                (22U)
+#define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
+#define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
+#define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
+#define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
+#define I3C_DEVR0_RSTVAL_Pos                (24U)
+#define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
+#define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
+
+/******************  Bit definition for I3C_DEVRX register  *******************/
+#define I3C_DEVRX_DA_Pos                    (1U)
+#define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
+#define I3C_DEVRX_IBIACK_Pos                (16U)
+#define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
+#define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
+#define I3C_DEVRX_CRACK_Pos                 (17U)
+#define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
+#define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
+#define I3C_DEVRX_IBIDEN_Pos                (18U)
+#define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
+#define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
+#define I3C_DEVRX_SUSP_Pos                  (19U)
+#define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
+#define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
+#define I3C_DEVRX_DIS_Pos                   (31U)
+#define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
+#define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
+
+/******************  Bit definition for I3C_MAXRLR register  ******************/
+#define I3C_MAXRLR_MRL_Pos                  (0U)
+#define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
+#define I3C_MAXRLR_IBIP_Pos                 (16U)
+#define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
+#define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
+#define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
+#define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
+#define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
+
+/******************  Bit definition for I3C_MAXWLR register  ******************/
+#define I3C_MAXWLR_MWL_Pos                  (0U)
+#define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
+
+/****************  Bit definition for I3C_TIMINGR0 register  ******************/
+#define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
+#define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
+#define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
+#define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
+#define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
+#define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
+#define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
+#define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
+#define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
+#define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
+#define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
+#define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
+
+/****************  Bit definition for I3C_TIMINGR1 register  ******************/
+#define I3C_TIMINGR1_AVAL_Pos               (0U)
+#define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
+#define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
+#define I3C_TIMINGR1_ASNCR_Pos              (8U)
+#define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
+#define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
+#define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
+#define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
+#define I3C_TIMINGR1_FREE_Pos               (16U)
+#define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
+#define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
+#define I3C_TIMINGR1_SDA_HD_Pos             (28U)
+#define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
+#define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
+
+/****************  Bit definition for I3C_TIMINGR2 register  ******************/
+#define I3C_TIMINGR2_STALLT_Pos             (0U)
+#define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x0000001 */
+#define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
+#define I3C_TIMINGR2_STALLD_Pos             (1U)
+#define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x0000002 */
+#define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
+#define I3C_TIMINGR2_STALLC_Pos             (2U)
+#define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x0000004 */
+#define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
+#define I3C_TIMINGR2_STALLA_Pos             (3U)
+#define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x0000008 */
+#define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
+#define I3C_TIMINGR2_STALL_Pos              (8U)
+#define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x000FF00 */
+#define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
+
+/*******************  Bit definition for I3C_BCR register  ********************/
+#define I3C_BCR_BCR_Pos                     (0U)
+#define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
+#define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
+#define I3C_BCR_BCR0_Pos                    (0U)
+#define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
+#define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
+#define I3C_BCR_BCR1_Pos                    (1U)
+#define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
+#define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
+#define I3C_BCR_BCR2_Pos                    (2U)
+#define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
+#define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
+#define I3C_BCR_BCR3_Pos                    (3U)
+#define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
+#define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
+#define I3C_BCR_BCR4_Pos                    (4U)
+#define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
+#define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
+#define I3C_BCR_BCR5_Pos                    (5U)
+#define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
+#define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
+#define I3C_BCR_BCR6_Pos                    (6U)
+#define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
+#define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
+
+/*******************  Bit definition for I3C_DCR register  ********************/
+#define I3C_DCR_DCR_Pos                     (0U)
+#define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x00000FF */
+#define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
+
+/*****************  Bit definition for I3C_GETCAPR register  ******************/
+#define I3C_GETCAPR_CAPPEND_Pos             (14U)
+#define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
+#define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
+
+/*****************  Bit definition for I3C_CRCAPR register  *******************/
+#define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
+#define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
+#define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
+#define I3C_CRCAPR_CAPGRP_Pos               (9U)
+#define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
+#define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
+
+/****************  Bit definition for I3C_GETMXDSR register  ******************/
+#define I3C_GETMXDSR_HOFFAS_Pos             (0U)
+#define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
+#define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
+#define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
+#define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
+#define I3C_GETMXDSR_FMT_Pos                (8U)
+#define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
+#define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
+#define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
+#define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
+#define I3C_GETMXDSR_RDTURN_Pos             (16U)
+#define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
+#define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
+#define I3C_GETMXDSR_TSCO_Pos               (24U)
+#define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
+#define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
+
+/******************  Bit definition for I3C_EPIDR register  *******************/
+#define I3C_EPIDR_MIPIID_Pos                (12U)
+#define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
+#define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
+#define I3C_EPIDR_IDTSEL_Pos                (16U)
+#define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
+#define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
+#define I3C_EPIDR_MIPIMID_Pos               (17U)
+#define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
+#define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Illegal Access Controller (IAC)                                */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for IAC_IER0 register *******************/
+#define IAC_IER0_IAIE0_Pos            (0U)
+#define IAC_IER0_IAIE0_Msk            (0x1UL << IAC_IER0_IAIE0_Pos)              /*!< 0x00000001 */
+#define IAC_IER0_IAIE0                IAC_IER0_IAIE0_Msk
+#define IAC_IER0_IAIE1_Pos            (1U)
+#define IAC_IER0_IAIE1_Msk            (0x1UL << IAC_IER0_IAIE1_Pos)              /*!< 0x00000002 */
+#define IAC_IER0_IAIE1                IAC_IER0_IAIE1_Msk
+#define IAC_IER0_IAIE2_Pos            (2U)
+#define IAC_IER0_IAIE2_Msk            (0x1UL << IAC_IER0_IAIE2_Pos)              /*!< 0x00000004 */
+#define IAC_IER0_IAIE2                IAC_IER0_IAIE2_Msk
+#define IAC_IER0_IAIE3_Pos            (3U)
+#define IAC_IER0_IAIE3_Msk            (0x1UL << IAC_IER0_IAIE3_Pos)              /*!< 0x00000008 */
+#define IAC_IER0_IAIE3                IAC_IER0_IAIE3_Msk
+#define IAC_IER0_IAIE4_Pos            (4U)
+#define IAC_IER0_IAIE4_Msk            (0x1UL << IAC_IER0_IAIE4_Pos)              /*!< 0x00000010 */
+#define IAC_IER0_IAIE4                IAC_IER0_IAIE4_Msk
+#define IAC_IER0_IAIE5_Pos            (5U)
+#define IAC_IER0_IAIE5_Msk            (0x1UL << IAC_IER0_IAIE5_Pos)              /*!< 0x00000020 */
+#define IAC_IER0_IAIE5                IAC_IER0_IAIE5_Msk
+#define IAC_IER0_IAIE6_Pos            (6U)
+#define IAC_IER0_IAIE6_Msk            (0x1UL << IAC_IER0_IAIE6_Pos)              /*!< 0x00000040 */
+#define IAC_IER0_IAIE6                IAC_IER0_IAIE6_Msk
+#define IAC_IER0_IAIE8_Pos            (8U)
+#define IAC_IER0_IAIE8_Msk            (0x1UL << IAC_IER0_IAIE8_Pos)              /*!< 0x00000100 */
+#define IAC_IER0_IAIE8                IAC_IER0_IAIE8_Msk
+#define IAC_IER0_IAIE9_Pos            (9U)
+#define IAC_IER0_IAIE9_Msk            (0x1UL << IAC_IER0_IAIE9_Pos)              /*!< 0x00000200 */
+#define IAC_IER0_IAIE9                IAC_IER0_IAIE9_Msk
+#define IAC_IER0_IAIE10_Pos           (10U)
+#define IAC_IER0_IAIE10_Msk           (0x1UL << IAC_IER0_IAIE10_Pos)             /*!< 0x00000400 */
+#define IAC_IER0_IAIE10               IAC_IER0_IAIE10_Msk
+#define IAC_IER0_IAIE11_Pos           (11U)
+#define IAC_IER0_IAIE11_Msk           (0x1UL << IAC_IER0_IAIE11_Pos)             /*!< 0x00000800 */
+#define IAC_IER0_IAIE11               IAC_IER0_IAIE11_Msk
+#define IAC_IER0_IAIE12_Pos           (12U)
+#define IAC_IER0_IAIE12_Msk           (0x1UL << IAC_IER0_IAIE12_Pos)             /*!< 0x00001000 */
+#define IAC_IER0_IAIE12               IAC_IER0_IAIE12_Msk
+#define IAC_IER0_IAIE13_Pos           (13U)
+#define IAC_IER0_IAIE13_Msk           (0x1UL << IAC_IER0_IAIE13_Pos)             /*!< 0x00002000 */
+#define IAC_IER0_IAIE13               IAC_IER0_IAIE13_Msk
+#define IAC_IER0_IAIE14_Pos           (14U)
+#define IAC_IER0_IAIE14_Msk           (0x1UL << IAC_IER0_IAIE14_Pos)             /*!< 0x00004000 */
+#define IAC_IER0_IAIE14               IAC_IER0_IAIE14_Msk
+#define IAC_IER0_IAIE15_Pos           (15U)
+#define IAC_IER0_IAIE15_Msk           (0x1UL << IAC_IER0_IAIE15_Pos)             /*!< 0x00008000 */
+#define IAC_IER0_IAIE15               IAC_IER0_IAIE15_Msk
+#define IAC_IER0_IAIE16_Pos           (16U)
+#define IAC_IER0_IAIE16_Msk           (0x1UL << IAC_IER0_IAIE16_Pos)             /*!< 0x00010000 */
+#define IAC_IER0_IAIE16               IAC_IER0_IAIE16_Msk
+#define IAC_IER0_IAIE17_Pos           (17U)
+#define IAC_IER0_IAIE17_Msk           (0x1UL << IAC_IER0_IAIE17_Pos)             /*!< 0x00020000 */
+#define IAC_IER0_IAIE17               IAC_IER0_IAIE17_Msk
+#define IAC_IER0_IAIE18_Pos           (18U)
+#define IAC_IER0_IAIE18_Msk           (0x1UL << IAC_IER0_IAIE18_Pos)             /*!< 0x00040000 */
+#define IAC_IER0_IAIE18               IAC_IER0_IAIE18_Msk
+#define IAC_IER0_IAIE19_Pos           (19U)
+#define IAC_IER0_IAIE19_Msk           (0x1UL << IAC_IER0_IAIE19_Pos)             /*!< 0x00080000 */
+#define IAC_IER0_IAIE19               IAC_IER0_IAIE19_Msk
+#define IAC_IER0_IAIE20_Pos           (20U)
+#define IAC_IER0_IAIE20_Msk           (0x1UL << IAC_IER0_IAIE20_Pos)             /*!< 0x00100000 */
+#define IAC_IER0_IAIE20               IAC_IER0_IAIE20_Msk
+#define IAC_IER0_IAIE21_Pos           (21U)
+#define IAC_IER0_IAIE21_Msk           (0x1UL << IAC_IER0_IAIE21_Pos)             /*!< 0x00200000 */
+#define IAC_IER0_IAIE21               IAC_IER0_IAIE21_Msk
+#define IAC_IER0_IAIE22_Pos           (22U)
+#define IAC_IER0_IAIE22_Msk           (0x1UL << IAC_IER0_IAIE22_Pos)             /*!< 0x00400000 */
+#define IAC_IER0_IAIE22               IAC_IER0_IAIE22_Msk
+#define IAC_IER0_IAIE23_Pos           (23U)
+#define IAC_IER0_IAIE23_Msk           (0x1UL << IAC_IER0_IAIE23_Pos)             /*!< 0x00800000 */
+#define IAC_IER0_IAIE23               IAC_IER0_IAIE23_Msk
+#define IAC_IER0_IAIE24_Pos           (24U)
+#define IAC_IER0_IAIE24_Msk           (0x1UL << IAC_IER0_IAIE24_Pos)             /*!< 0x01000000 */
+#define IAC_IER0_IAIE24               IAC_IER0_IAIE24_Msk
+#define IAC_IER0_IAIE25_Pos           (25U)
+#define IAC_IER0_IAIE25_Msk           (0x1UL << IAC_IER0_IAIE25_Pos)             /*!< 0x02000000 */
+#define IAC_IER0_IAIE25               IAC_IER0_IAIE25_Msk
+#define IAC_IER0_IAIE26_Pos           (26U)
+#define IAC_IER0_IAIE26_Msk           (0x1UL << IAC_IER0_IAIE26_Pos)             /*!< 0x04000000 */
+#define IAC_IER0_IAIE26               IAC_IER0_IAIE26_Msk
+#define IAC_IER0_IAIE27_Pos           (27U)
+#define IAC_IER0_IAIE27_Msk           (0x1UL << IAC_IER0_IAIE27_Pos)             /*!< 0x08000000 */
+#define IAC_IER0_IAIE27               IAC_IER0_IAIE27_Msk
+#define IAC_IER0_IAIE28_Pos           (28U)
+#define IAC_IER0_IAIE28_Msk           (0x1UL << IAC_IER0_IAIE28_Pos)             /*!< 0x10000000 */
+#define IAC_IER0_IAIE28               IAC_IER0_IAIE28_Msk
+#define IAC_IER0_IAIE29_Pos           (29U)
+#define IAC_IER0_IAIE29_Msk           (0x1UL << IAC_IER0_IAIE29_Pos)             /*!< 0x20000000 */
+#define IAC_IER0_IAIE29               IAC_IER0_IAIE29_Msk
+#define IAC_IER0_IAIE30_Pos           (30U)
+#define IAC_IER0_IAIE30_Msk           (0x1UL << IAC_IER0_IAIE30_Pos)             /*!< 0x40000000 */
+#define IAC_IER0_IAIE30               IAC_IER0_IAIE30_Msk
+#define IAC_IER0_IAIE31_Pos           (31U)
+#define IAC_IER0_IAIE31_Msk           (0x1UL << IAC_IER0_IAIE31_Pos)             /*!< 0x80000000 */
+#define IAC_IER0_IAIE31               IAC_IER0_IAIE31_Msk
+
+/*******************  Bits definition for IAC_IER1 register *******************/
+#define IAC_IER1_IAIE32_Pos           (0U)
+#define IAC_IER1_IAIE32_Msk           (0x1UL << IAC_IER1_IAIE32_Pos)             /*!< 0x00000001 */
+#define IAC_IER1_IAIE32               IAC_IER1_IAIE32_Msk
+#define IAC_IER1_IAIE33_Pos           (1U)
+#define IAC_IER1_IAIE33_Msk           (0x1UL << IAC_IER1_IAIE33_Pos)             /*!< 0x00000002 */
+#define IAC_IER1_IAIE33               IAC_IER1_IAIE33_Msk
+#define IAC_IER1_IAIE34_Pos           (2U)
+#define IAC_IER1_IAIE34_Msk           (0x1UL << IAC_IER1_IAIE34_Pos)             /*!< 0x00000004 */
+#define IAC_IER1_IAIE34               IAC_IER1_IAIE34_Msk
+#define IAC_IER1_IAIE35_Pos           (3U)
+#define IAC_IER1_IAIE35_Msk           (0x1UL << IAC_IER1_IAIE35_Pos)             /*!< 0x00000008 */
+#define IAC_IER1_IAIE35               IAC_IER1_IAIE35_Msk
+#define IAC_IER1_IAIE36_Pos           (4U)
+#define IAC_IER1_IAIE36_Msk           (0x1UL << IAC_IER1_IAIE36_Pos)             /*!< 0x00000010 */
+#define IAC_IER1_IAIE36               IAC_IER1_IAIE36_Msk
+#define IAC_IER1_IAIE37_Pos           (5U)
+#define IAC_IER1_IAIE37_Msk           (0x1UL << IAC_IER1_IAIE37_Pos)             /*!< 0x00000020 */
+#define IAC_IER1_IAIE37               IAC_IER1_IAIE37_Msk
+#define IAC_IER1_IAIE38_Pos           (6U)
+#define IAC_IER1_IAIE38_Msk           (0x1UL << IAC_IER1_IAIE38_Pos)             /*!< 0x00000040 */
+#define IAC_IER1_IAIE38               IAC_IER1_IAIE38_Msk
+#define IAC_IER1_IAIE39_Pos           (7U)
+#define IAC_IER1_IAIE39_Msk           (0x1UL << IAC_IER1_IAIE39_Pos)             /*!< 0x00000080 */
+#define IAC_IER1_IAIE39               IAC_IER1_IAIE39_Msk
+#define IAC_IER1_IAIE40_Pos           (8U)
+#define IAC_IER1_IAIE40_Msk           (0x1UL << IAC_IER1_IAIE40_Pos)             /*!< 0x00000100 */
+#define IAC_IER1_IAIE40               IAC_IER1_IAIE40_Msk
+#define IAC_IER1_IAIE41_Pos           (9U)
+#define IAC_IER1_IAIE41_Msk           (0x1UL << IAC_IER1_IAIE41_Pos)             /*!< 0x00000200 */
+#define IAC_IER1_IAIE41               IAC_IER1_IAIE41_Msk
+#define IAC_IER1_IAIE42_Pos           (10U)
+#define IAC_IER1_IAIE42_Msk           (0x1UL << IAC_IER1_IAIE42_Pos)             /*!< 0x00000400 */
+#define IAC_IER1_IAIE42               IAC_IER1_IAIE42_Msk
+#define IAC_IER1_IAIE43_Pos           (11U)
+#define IAC_IER1_IAIE43_Msk           (0x1UL << IAC_IER1_IAIE43_Pos)             /*!< 0x00000800 */
+#define IAC_IER1_IAIE43               IAC_IER1_IAIE43_Msk
+#define IAC_IER1_IAIE44_Pos           (12U)
+#define IAC_IER1_IAIE44_Msk           (0x1UL << IAC_IER1_IAIE44_Pos)             /*!< 0x00001000 */
+#define IAC_IER1_IAIE44               IAC_IER1_IAIE44_Msk
+#define IAC_IER1_IAIE45_Pos           (13U)
+#define IAC_IER1_IAIE45_Msk           (0x1UL << IAC_IER1_IAIE45_Pos)             /*!< 0x00002000 */
+#define IAC_IER1_IAIE45               IAC_IER1_IAIE45_Msk
+#define IAC_IER1_IAIE46_Pos           (14U)
+#define IAC_IER1_IAIE46_Msk           (0x1UL << IAC_IER1_IAIE46_Pos)             /*!< 0x00004000 */
+#define IAC_IER1_IAIE46               IAC_IER1_IAIE46_Msk
+#define IAC_IER1_IAIE47_Pos           (15U)
+#define IAC_IER1_IAIE47_Msk           (0x1UL << IAC_IER1_IAIE47_Pos)             /*!< 0x00008000 */
+#define IAC_IER1_IAIE47               IAC_IER1_IAIE47_Msk
+#define IAC_IER1_IAIE48_Pos           (16U)
+#define IAC_IER1_IAIE48_Msk           (0x1UL << IAC_IER1_IAIE48_Pos)             /*!< 0x00010000 */
+#define IAC_IER1_IAIE48               IAC_IER1_IAIE48_Msk
+#define IAC_IER1_IAIE49_Pos           (17U)
+#define IAC_IER1_IAIE49_Msk           (0x1UL << IAC_IER1_IAIE49_Pos)             /*!< 0x00020000 */
+#define IAC_IER1_IAIE49               IAC_IER1_IAIE49_Msk
+#define IAC_IER1_IAIE50_Pos           (18U)
+#define IAC_IER1_IAIE50_Msk           (0x1UL << IAC_IER1_IAIE50_Pos)             /*!< 0x00040000 */
+#define IAC_IER1_IAIE50               IAC_IER1_IAIE50_Msk
+#define IAC_IER1_IAIE51_Pos           (19U)
+#define IAC_IER1_IAIE51_Msk           (0x1UL << IAC_IER1_IAIE51_Pos)             /*!< 0x00080000 */
+#define IAC_IER1_IAIE51               IAC_IER1_IAIE51_Msk
+#define IAC_IER1_IAIE52_Pos           (20U)
+#define IAC_IER1_IAIE52_Msk           (0x1UL << IAC_IER1_IAIE52_Pos)             /*!< 0x00100000 */
+#define IAC_IER1_IAIE52               IAC_IER1_IAIE52_Msk
+#define IAC_IER1_IAIE53_Pos           (21U)
+#define IAC_IER1_IAIE53_Msk           (0x1UL << IAC_IER1_IAIE53_Pos)             /*!< 0x00200000 */
+#define IAC_IER1_IAIE53               IAC_IER1_IAIE53_Msk
+#define IAC_IER1_IAIE54_Pos           (22U)
+#define IAC_IER1_IAIE54_Msk           (0x1UL << IAC_IER1_IAIE54_Pos)             /*!< 0x00400000 */
+#define IAC_IER1_IAIE54               IAC_IER1_IAIE54_Msk
+#define IAC_IER1_IAIE55_Pos           (23U)
+#define IAC_IER1_IAIE55_Msk           (0x1UL << IAC_IER1_IAIE55_Pos)             /*!< 0x00800000 */
+#define IAC_IER1_IAIE55               IAC_IER1_IAIE55_Msk
+#define IAC_IER1_IAIE56_Pos           (24U)
+#define IAC_IER1_IAIE56_Msk           (0x1UL << IAC_IER1_IAIE56_Pos)             /*!< 0x01000000 */
+#define IAC_IER1_IAIE56               IAC_IER1_IAIE56_Msk
+#define IAC_IER1_IAIE57_Pos           (25U)
+#define IAC_IER1_IAIE57_Msk           (0x1UL << IAC_IER1_IAIE57_Pos)             /*!< 0x02000000 */
+#define IAC_IER1_IAIE57               IAC_IER1_IAIE57_Msk
+#define IAC_IER1_IAIE58_Pos           (26U)
+#define IAC_IER1_IAIE58_Msk           (0x1UL << IAC_IER1_IAIE58_Pos)             /*!< 0x04000000 */
+#define IAC_IER1_IAIE58               IAC_IER1_IAIE58_Msk
+#define IAC_IER1_IAIE60_Pos           (28U)
+#define IAC_IER1_IAIE60_Msk           (0x1UL << IAC_IER1_IAIE60_Pos)             /*!< 0x10000000 */
+#define IAC_IER1_IAIE60               IAC_IER1_IAIE60_Msk
+#define IAC_IER1_IAIE61_Pos           (29U)
+#define IAC_IER1_IAIE61_Msk           (0x1UL << IAC_IER1_IAIE61_Pos)             /*!< 0x20000000 */
+#define IAC_IER1_IAIE61               IAC_IER1_IAIE61_Msk
+#define IAC_IER1_IAIE62_Pos           (30U)
+#define IAC_IER1_IAIE62_Msk           (0x1UL << IAC_IER1_IAIE62_Pos)             /*!< 0x40000000 */
+#define IAC_IER1_IAIE62               IAC_IER1_IAIE62_Msk
+
+/*******************  Bits definition for IAC_IER2 register *******************/
+#define IAC_IER2_IAIE64_Pos           (0U)
+#define IAC_IER2_IAIE64_Msk           (0x1UL << IAC_IER2_IAIE64_Pos)             /*!< 0x00000001 */
+#define IAC_IER2_IAIE64               IAC_IER2_IAIE64_Msk
+#define IAC_IER2_IAIE65_Pos           (1U)
+#define IAC_IER2_IAIE65_Msk           (0x1UL << IAC_IER2_IAIE65_Pos)             /*!< 0x00000002 */
+#define IAC_IER2_IAIE65               IAC_IER2_IAIE65_Msk
+#define IAC_IER2_IAIE67_Pos           (3U)
+#define IAC_IER2_IAIE67_Msk           (0x1UL << IAC_IER2_IAIE67_Pos)             /*!< 0x00000008 */
+#define IAC_IER2_IAIE67               IAC_IER2_IAIE67_Msk
+#define IAC_IER2_IAIE68_Pos           (4U)
+#define IAC_IER2_IAIE68_Msk           (0x1UL << IAC_IER2_IAIE68_Pos)             /*!< 0x00000010 */
+#define IAC_IER2_IAIE68               IAC_IER2_IAIE68_Msk
+#define IAC_IER2_IAIE69_Pos           (5U)
+#define IAC_IER2_IAIE69_Msk           (0x1UL << IAC_IER2_IAIE69_Pos)             /*!< 0x00000020 */
+#define IAC_IER2_IAIE69               IAC_IER2_IAIE69_Msk
+#define IAC_IER2_IAIE76_Pos           (12U)
+#define IAC_IER2_IAIE76_Msk           (0x1UL << IAC_IER2_IAIE76_Pos)             /*!< 0x00001000 */
+#define IAC_IER2_IAIE76               IAC_IER2_IAIE76_Msk
+#define IAC_IER2_IAIE77_Pos           (13U)
+#define IAC_IER2_IAIE77_Msk           (0x1UL << IAC_IER2_IAIE77_Pos)             /*!< 0x00002000 */
+#define IAC_IER2_IAIE77               IAC_IER2_IAIE77_Msk
+#define IAC_IER2_IAIE78_Pos           (14U)
+#define IAC_IER2_IAIE78_Msk           (0x1UL << IAC_IER2_IAIE78_Pos)             /*!< 0x00004000 */
+#define IAC_IER2_IAIE78               IAC_IER2_IAIE78_Msk
+#define IAC_IER2_IAIE79_Pos           (15U)
+#define IAC_IER2_IAIE79_Msk           (0x1UL << IAC_IER2_IAIE79_Pos)             /*!< 0x00008000 */
+#define IAC_IER2_IAIE79               IAC_IER2_IAIE79_Msk
+#define IAC_IER2_IAIE80_Pos           (16U)
+#define IAC_IER2_IAIE80_Msk           (0x1UL << IAC_IER2_IAIE80_Pos)             /*!< 0x00010000 */
+#define IAC_IER2_IAIE80               IAC_IER2_IAIE80_Msk
+#define IAC_IER2_IAIE81_Pos           (17U)
+#define IAC_IER2_IAIE81_Msk           (0x1UL << IAC_IER2_IAIE81_Pos)             /*!< 0x00020000 */
+#define IAC_IER2_IAIE81               IAC_IER2_IAIE81_Msk
+#define IAC_IER2_IAIE82_Pos           (18U)
+#define IAC_IER2_IAIE82_Msk           (0x1UL << IAC_IER2_IAIE82_Pos)             /*!< 0x00040000 */
+#define IAC_IER2_IAIE82               IAC_IER2_IAIE82_Msk
+#define IAC_IER2_IAIE83_Pos           (19U)
+#define IAC_IER2_IAIE83_Msk           (0x1UL << IAC_IER2_IAIE83_Pos)             /*!< 0x00080000 */
+#define IAC_IER2_IAIE83               IAC_IER2_IAIE83_Msk
+#define IAC_IER2_IAIE84_Pos           (20U)
+#define IAC_IER2_IAIE84_Msk           (0x1UL << IAC_IER2_IAIE84_Pos)             /*!< 0x00100000 */
+#define IAC_IER2_IAIE84               IAC_IER2_IAIE84_Msk
+#define IAC_IER2_IAIE86_Pos           (22U)
+#define IAC_IER2_IAIE86_Msk           (0x1UL << IAC_IER2_IAIE86_Pos)             /*!< 0x00400000 */
+#define IAC_IER2_IAIE86               IAC_IER2_IAIE86_Msk
+#define IAC_IER2_IAIE87_Pos           (23U)
+#define IAC_IER2_IAIE87_Msk           (0x1UL << IAC_IER2_IAIE87_Pos)             /*!< 0x00800000 */
+#define IAC_IER2_IAIE87               IAC_IER2_IAIE87_Msk
+#define IAC_IER2_IAIE88_Pos           (24U)
+#define IAC_IER2_IAIE88_Msk           (0x1UL << IAC_IER2_IAIE88_Pos)             /*!< 0x01000000 */
+#define IAC_IER2_IAIE88               IAC_IER2_IAIE88_Msk
+#define IAC_IER2_IAIE89_Pos           (25U)
+#define IAC_IER2_IAIE89_Msk           (0x1UL << IAC_IER2_IAIE89_Pos)             /*!< 0x02000000 */
+#define IAC_IER2_IAIE89               IAC_IER2_IAIE89_Msk
+#define IAC_IER2_IAIE90_Pos           (26U)
+#define IAC_IER2_IAIE90_Msk           (0x1UL << IAC_IER2_IAIE90_Pos)             /*!< 0x04000000 */
+#define IAC_IER2_IAIE90               IAC_IER2_IAIE90_Msk
+#define IAC_IER2_IAIE92_Pos           (28U)
+#define IAC_IER2_IAIE92_Msk           (0x1UL << IAC_IER2_IAIE92_Pos)             /*!< 0x10000000 */
+#define IAC_IER2_IAIE92               IAC_IER2_IAIE92_Msk
+#define IAC_IER2_IAIE93_Pos           (29U)
+#define IAC_IER2_IAIE93_Msk           (0x1UL << IAC_IER2_IAIE93_Pos)             /*!< 0x20000000 */
+#define IAC_IER2_IAIE93               IAC_IER2_IAIE93_Msk
+#define IAC_IER2_IAIE94_Pos           (30U)
+#define IAC_IER2_IAIE94_Msk           (0x1UL << IAC_IER2_IAIE94_Pos)             /*!< 0x40000000 */
+#define IAC_IER2_IAIE94               IAC_IER2_IAIE94_Msk
+#define IAC_IER2_IAIE95_Pos           (31U)
+#define IAC_IER2_IAIE95_Msk           (0x1UL << IAC_IER2_IAIE95_Pos)             /*!< 0x80000000 */
+#define IAC_IER2_IAIE95               IAC_IER2_IAIE95_Msk
+
+/*******************  Bits definition for IAC_IER3 register *******************/
+#define IAC_IER3_IAIE96_Pos           (0U)
+#define IAC_IER3_IAIE96_Msk           (0x1UL << IAC_IER3_IAIE96_Pos)             /*!< 0x00000001 */
+#define IAC_IER3_IAIE96               IAC_IER3_IAIE96_Msk
+#define IAC_IER3_IAIE97_Pos           (1U)
+#define IAC_IER3_IAIE97_Msk           (0x1UL << IAC_IER3_IAIE97_Pos)             /*!< 0x00000002 */
+#define IAC_IER3_IAIE97               IAC_IER3_IAIE97_Msk
+#define IAC_IER3_IAIE98_Pos           (2U)
+#define IAC_IER3_IAIE98_Msk           (0x1UL << IAC_IER3_IAIE98_Pos)             /*!< 0x00000004 */
+#define IAC_IER3_IAIE98               IAC_IER3_IAIE98_Msk
+#define IAC_IER3_IAIE99_Pos           (3U)
+#define IAC_IER3_IAIE99_Msk           (0x1UL << IAC_IER3_IAIE99_Pos)             /*!< 0x00000008 */
+#define IAC_IER3_IAIE99               IAC_IER3_IAIE99_Msk
+#define IAC_IER3_IAIE100_Pos          (4U)
+#define IAC_IER3_IAIE100_Msk          (0x1UL << IAC_IER3_IAIE100_Pos)            /*!< 0x00000010 */
+#define IAC_IER3_IAIE100              IAC_IER3_IAIE100_Msk
+#define IAC_IER3_IAIE101_Pos          (5U)
+#define IAC_IER3_IAIE101_Msk          (0x1UL << IAC_IER3_IAIE101_Pos)            /*!< 0x00000020 */
+#define IAC_IER3_IAIE101              IAC_IER3_IAIE101_Msk
+#define IAC_IER3_IAIE102_Pos          (6U)
+#define IAC_IER3_IAIE102_Msk          (0x1UL << IAC_IER3_IAIE102_Pos)            /*!< 0x00000040 */
+#define IAC_IER3_IAIE102              IAC_IER3_IAIE102_Msk
+#define IAC_IER3_IAIE103_Pos          (7U)
+#define IAC_IER3_IAIE103_Msk          (0x1UL << IAC_IER3_IAIE103_Pos)            /*!< 0x00000080 */
+#define IAC_IER3_IAIE103              IAC_IER3_IAIE103_Msk
+#define IAC_IER3_IAIE104_Pos          (8U)
+#define IAC_IER3_IAIE104_Msk          (0x1UL << IAC_IER3_IAIE104_Pos)            /*!< 0x00000100 */
+#define IAC_IER3_IAIE104              IAC_IER3_IAIE104_Msk
+#define IAC_IER3_IAIE106_Pos          (10U)
+#define IAC_IER3_IAIE106_Msk          (0x1UL << IAC_IER3_IAIE106_Pos)            /*!< 0x00000400 */
+#define IAC_IER3_IAIE106              IAC_IER3_IAIE106_Msk
+
+/*******************  Bits definition for IAC_IER4 register *******************/
+#define IAC_IER4_IAIE128_Pos          (0U)
+#define IAC_IER4_IAIE128_Msk          (0x1UL << IAC_IER4_IAIE128_Pos)            /*!< 0x00000001 */
+#define IAC_IER4_IAIE128              IAC_IER4_IAIE128_Msk
+#define IAC_IER4_IAIE129_Pos          (1U)
+#define IAC_IER4_IAIE129_Msk          (0x1UL << IAC_IER4_IAIE129_Pos)            /*!< 0x00000002 */
+#define IAC_IER4_IAIE129              IAC_IER4_IAIE129_Msk
+#define IAC_IER4_IAIE130_Pos          (2U)
+#define IAC_IER4_IAIE130_Msk          (0x1UL << IAC_IER4_IAIE130_Pos)            /*!< 0x00000004 */
+#define IAC_IER4_IAIE130              IAC_IER4_IAIE130_Msk
+#define IAC_IER4_IAIE131_Pos          (3U)
+#define IAC_IER4_IAIE131_Msk          (0x1UL << IAC_IER4_IAIE131_Pos)            /*!< 0x00000008 */
+#define IAC_IER4_IAIE131              IAC_IER4_IAIE131_Msk
+#define IAC_IER4_IAIE133_Pos          (5U)
+#define IAC_IER4_IAIE133_Msk          (0x1UL << IAC_IER4_IAIE133_Pos)            /*!< 0x00000020 */
+#define IAC_IER4_IAIE133              IAC_IER4_IAIE133_Msk
+#define IAC_IER4_IAIE134_Pos          (6U)
+#define IAC_IER4_IAIE134_Msk          (0x1UL << IAC_IER4_IAIE134_Pos)            /*!< 0x00000040 */
+#define IAC_IER4_IAIE134              IAC_IER4_IAIE134_Msk
+#define IAC_IER4_IAIE135_Pos          (7U)
+#define IAC_IER4_IAIE135_Msk          (0x1UL << IAC_IER4_IAIE135_Pos)            /*!< 0x00000080 */
+#define IAC_IER4_IAIE135              IAC_IER4_IAIE135_Msk
+#define IAC_IER4_IAIE136_Pos          (8U)
+#define IAC_IER4_IAIE136_Msk          (0x1UL << IAC_IER4_IAIE136_Pos)            /*!< 0x00000100 */
+#define IAC_IER4_IAIE136              IAC_IER4_IAIE136_Msk
+#define IAC_IER4_IAIE137_Pos          (9U)
+#define IAC_IER4_IAIE137_Msk          (0x1UL << IAC_IER4_IAIE137_Pos)            /*!< 0x00000200 */
+#define IAC_IER4_IAIE137              IAC_IER4_IAIE137_Msk
+#define IAC_IER4_IAIE138_Pos          (10U)
+#define IAC_IER4_IAIE138_Msk          (0x1UL << IAC_IER4_IAIE138_Pos)            /*!< 0x00000400 */
+#define IAC_IER4_IAIE138              IAC_IER4_IAIE138_Msk
+#define IAC_IER4_IAIE139_Pos          (11U)
+#define IAC_IER4_IAIE139_Msk          (0x1UL << IAC_IER4_IAIE139_Pos)            /*!< 0x00000800 */
+#define IAC_IER4_IAIE139              IAC_IER4_IAIE139_Msk
+#define IAC_IER4_IAIE140_Pos          (12U)
+#define IAC_IER4_IAIE140_Msk          (0x1UL << IAC_IER4_IAIE140_Pos)            /*!< 0x00001000 */
+#define IAC_IER4_IAIE140              IAC_IER4_IAIE140_Msk
+#define IAC_IER4_IAIE141_Pos          (13U)
+#define IAC_IER4_IAIE141_Msk          (0x1UL << IAC_IER4_IAIE141_Pos)            /*!< 0x00002000 */
+#define IAC_IER4_IAIE141              IAC_IER4_IAIE141_Msk
+#define IAC_IER4_IAIE142_Pos          (14U)
+#define IAC_IER4_IAIE142_Msk          (0x1UL << IAC_IER4_IAIE142_Pos)            /*!< 0x00004000 */
+#define IAC_IER4_IAIE142              IAC_IER4_IAIE142_Msk
+#define IAC_IER4_IAIE143_Pos          (15U)
+#define IAC_IER4_IAIE143_Msk          (0x1UL << IAC_IER4_IAIE143_Pos)            /*!< 0x00008000 */
+#define IAC_IER4_IAIE143              IAC_IER4_IAIE143_Msk
+#define IAC_IER4_IAIE144_Pos          (16U)
+#define IAC_IER4_IAIE144_Msk          (0x1UL << IAC_IER4_IAIE144_Pos)            /*!< 0x00010000 */
+#define IAC_IER4_IAIE144              IAC_IER4_IAIE144_Msk
+#define IAC_IER4_IAIE145_Pos          (17U)
+#define IAC_IER4_IAIE145_Msk          (0x1UL << IAC_IER4_IAIE145_Pos)            /*!< 0x00020000 */
+#define IAC_IER4_IAIE145              IAC_IER4_IAIE145_Msk
+#define IAC_IER4_IAIE146_Pos          (18U)
+#define IAC_IER4_IAIE146_Msk          (0x1UL << IAC_IER4_IAIE146_Pos)            /*!< 0x00040000 */
+#define IAC_IER4_IAIE146              IAC_IER4_IAIE146_Msk
+#define IAC_IER4_IAIE147_Pos          (19U)
+#define IAC_IER4_IAIE147_Msk          (0x1UL << IAC_IER4_IAIE147_Pos)            /*!< 0x00080000 */
+#define IAC_IER4_IAIE147              IAC_IER4_IAIE147_Msk
+#define IAC_IER4_IAIE149_Pos          (21U)
+#define IAC_IER4_IAIE149_Msk          (0x1UL << IAC_IER4_IAIE149_Pos)            /*!< 0x00200000 */
+#define IAC_IER4_IAIE149              IAC_IER4_IAIE149_Msk
+#define IAC_IER4_IAIE150_Pos          (22U)
+#define IAC_IER4_IAIE150_Msk          (0x1UL << IAC_IER4_IAIE150_Pos)            /*!< 0x00400000 */
+#define IAC_IER4_IAIE150              IAC_IER4_IAIE150_Msk
+#define IAC_IER4_IAIE151_Pos          (23U)
+#define IAC_IER4_IAIE151_Msk          (0x1UL << IAC_IER4_IAIE151_Pos)            /*!< 0x00800000 */
+#define IAC_IER4_IAIE151              IAC_IER4_IAIE151_Msk
+#define IAC_IER4_IAIE152_Pos          (24U)
+#define IAC_IER4_IAIE152_Msk          (0x1UL << IAC_IER4_IAIE152_Pos)            /*!< 0x01000000 */
+#define IAC_IER4_IAIE152              IAC_IER4_IAIE152_Msk
+#define IAC_IER4_IAIE153_Pos          (25U)
+#define IAC_IER4_IAIE153_Msk          (0x1UL << IAC_IER4_IAIE153_Pos)            /*!< 0x02000000 */
+#define IAC_IER4_IAIE153              IAC_IER4_IAIE153_Msk
+#define IAC_IER4_IAIE155_Pos          (27U)
+#define IAC_IER4_IAIE155_Msk          (0x1UL << IAC_IER4_IAIE155_Pos)            /*!< 0x08000000 */
+#define IAC_IER4_IAIE155              IAC_IER4_IAIE155_Msk
+#define IAC_IER4_IAIE156_Pos          (28U)
+#define IAC_IER4_IAIE156_Msk          (0x1UL << IAC_IER4_IAIE156_Pos)            /*!< 0x10000000 */
+#define IAC_IER4_IAIE156              IAC_IER4_IAIE156_Msk
+#define IAC_IER4_IAIE157_Pos          (29U)
+#define IAC_IER4_IAIE157_Msk          (0x1UL << IAC_IER4_IAIE157_Pos)            /*!< 0x20000000 */
+#define IAC_IER4_IAIE157              IAC_IER4_IAIE157_Msk
+
+/*******************  Bits definition for IAC_ISR0 register *******************/
+#define IAC_ISR0_IAF0_Pos             (0U)
+#define IAC_ISR0_IAF0_Msk             (0x1UL << IAC_ISR0_IAF0_Pos)               /*!< 0x00000001 */
+#define IAC_ISR0_IAF0                 IAC_ISR0_IAF0_Msk
+#define IAC_ISR0_IAF1_Pos             (1U)
+#define IAC_ISR0_IAF1_Msk             (0x1UL << IAC_ISR0_IAF1_Pos)               /*!< 0x00000002 */
+#define IAC_ISR0_IAF1                 IAC_ISR0_IAF1_Msk
+#define IAC_ISR0_IAF2_Pos             (2U)
+#define IAC_ISR0_IAF2_Msk             (0x1UL << IAC_ISR0_IAF2_Pos)               /*!< 0x00000004 */
+#define IAC_ISR0_IAF2                 IAC_ISR0_IAF2_Msk
+#define IAC_ISR0_IAF3_Pos             (3U)
+#define IAC_ISR0_IAF3_Msk             (0x1UL << IAC_ISR0_IAF3_Pos)               /*!< 0x00000008 */
+#define IAC_ISR0_IAF3                 IAC_ISR0_IAF3_Msk
+#define IAC_ISR0_IAF4_Pos             (4U)
+#define IAC_ISR0_IAF4_Msk             (0x1UL << IAC_ISR0_IAF4_Pos)               /*!< 0x00000010 */
+#define IAC_ISR0_IAF4                 IAC_ISR0_IAF4_Msk
+#define IAC_ISR0_IAF5_Pos             (5U)
+#define IAC_ISR0_IAF5_Msk             (0x1UL << IAC_ISR0_IAF5_Pos)               /*!< 0x00000020 */
+#define IAC_ISR0_IAF5                 IAC_ISR0_IAF5_Msk
+#define IAC_ISR0_IAF6_Pos             (6U)
+#define IAC_ISR0_IAF6_Msk             (0x1UL << IAC_ISR0_IAF6_Pos)               /*!< 0x00000040 */
+#define IAC_ISR0_IAF6                 IAC_ISR0_IAF6_Msk
+#define IAC_ISR0_IAF8_Pos             (8U)
+#define IAC_ISR0_IAF8_Msk             (0x1UL << IAC_ISR0_IAF8_Pos)               /*!< 0x00000100 */
+#define IAC_ISR0_IAF8                 IAC_ISR0_IAF8_Msk
+#define IAC_ISR0_IAF9_Pos             (9U)
+#define IAC_ISR0_IAF9_Msk             (0x1UL << IAC_ISR0_IAF9_Pos)               /*!< 0x00000200 */
+#define IAC_ISR0_IAF9                 IAC_ISR0_IAF9_Msk
+#define IAC_ISR0_IAF10_Pos            (10U)
+#define IAC_ISR0_IAF10_Msk            (0x1UL << IAC_ISR0_IAF10_Pos)              /*!< 0x00000400 */
+#define IAC_ISR0_IAF10                IAC_ISR0_IAF10_Msk
+#define IAC_ISR0_IAF11_Pos            (11U)
+#define IAC_ISR0_IAF11_Msk            (0x1UL << IAC_ISR0_IAF11_Pos)              /*!< 0x00000800 */
+#define IAC_ISR0_IAF11                IAC_ISR0_IAF11_Msk
+#define IAC_ISR0_IAF12_Pos            (12U)
+#define IAC_ISR0_IAF12_Msk            (0x1UL << IAC_ISR0_IAF12_Pos)              /*!< 0x00001000 */
+#define IAC_ISR0_IAF12                IAC_ISR0_IAF12_Msk
+#define IAC_ISR0_IAF13_Pos            (13U)
+#define IAC_ISR0_IAF13_Msk            (0x1UL << IAC_ISR0_IAF13_Pos)              /*!< 0x00002000 */
+#define IAC_ISR0_IAF13                IAC_ISR0_IAF13_Msk
+#define IAC_ISR0_IAF14_Pos            (14U)
+#define IAC_ISR0_IAF14_Msk            (0x1UL << IAC_ISR0_IAF14_Pos)              /*!< 0x00004000 */
+#define IAC_ISR0_IAF14                IAC_ISR0_IAF14_Msk
+#define IAC_ISR0_IAF15_Pos            (15U)
+#define IAC_ISR0_IAF15_Msk            (0x1UL << IAC_ISR0_IAF15_Pos)              /*!< 0x00008000 */
+#define IAC_ISR0_IAF15                IAC_ISR0_IAF15_Msk
+#define IAC_ISR0_IAF16_Pos            (16U)
+#define IAC_ISR0_IAF16_Msk            (0x1UL << IAC_ISR0_IAF16_Pos)              /*!< 0x00010000 */
+#define IAC_ISR0_IAF16                IAC_ISR0_IAF16_Msk
+#define IAC_ISR0_IAF17_Pos            (17U)
+#define IAC_ISR0_IAF17_Msk            (0x1UL << IAC_ISR0_IAF17_Pos)              /*!< 0x00020000 */
+#define IAC_ISR0_IAF17                IAC_ISR0_IAF17_Msk
+#define IAC_ISR0_IAF18_Pos            (18U)
+#define IAC_ISR0_IAF18_Msk            (0x1UL << IAC_ISR0_IAF18_Pos)              /*!< 0x00040000 */
+#define IAC_ISR0_IAF18                IAC_ISR0_IAF18_Msk
+#define IAC_ISR0_IAF19_Pos            (19U)
+#define IAC_ISR0_IAF19_Msk            (0x1UL << IAC_ISR0_IAF19_Pos)              /*!< 0x00080000 */
+#define IAC_ISR0_IAF19                IAC_ISR0_IAF19_Msk
+#define IAC_ISR0_IAF20_Pos            (20U)
+#define IAC_ISR0_IAF20_Msk            (0x1UL << IAC_ISR0_IAF20_Pos)              /*!< 0x00100000 */
+#define IAC_ISR0_IAF20                IAC_ISR0_IAF20_Msk
+#define IAC_ISR0_IAF21_Pos            (21U)
+#define IAC_ISR0_IAF21_Msk            (0x1UL << IAC_ISR0_IAF21_Pos)              /*!< 0x00200000 */
+#define IAC_ISR0_IAF21                IAC_ISR0_IAF21_Msk
+#define IAC_ISR0_IAF22_Pos            (22U)
+#define IAC_ISR0_IAF22_Msk            (0x1UL << IAC_ISR0_IAF22_Pos)              /*!< 0x00400000 */
+#define IAC_ISR0_IAF22                IAC_ISR0_IAF22_Msk
+#define IAC_ISR0_IAF23_Pos            (23U)
+#define IAC_ISR0_IAF23_Msk            (0x1UL << IAC_ISR0_IAF23_Pos)              /*!< 0x00800000 */
+#define IAC_ISR0_IAF23                IAC_ISR0_IAF23_Msk
+#define IAC_ISR0_IAF24_Pos            (24U)
+#define IAC_ISR0_IAF24_Msk            (0x1UL << IAC_ISR0_IAF24_Pos)              /*!< 0x01000000 */
+#define IAC_ISR0_IAF24                IAC_ISR0_IAF24_Msk
+#define IAC_ISR0_IAF25_Pos            (25U)
+#define IAC_ISR0_IAF25_Msk            (0x1UL << IAC_ISR0_IAF25_Pos)              /*!< 0x02000000 */
+#define IAC_ISR0_IAF25                IAC_ISR0_IAF25_Msk
+#define IAC_ISR0_IAF26_Pos            (26U)
+#define IAC_ISR0_IAF26_Msk            (0x1UL << IAC_ISR0_IAF26_Pos)              /*!< 0x04000000 */
+#define IAC_ISR0_IAF26                IAC_ISR0_IAF26_Msk
+#define IAC_ISR0_IAF27_Pos            (27U)
+#define IAC_ISR0_IAF27_Msk            (0x1UL << IAC_ISR0_IAF27_Pos)              /*!< 0x08000000 */
+#define IAC_ISR0_IAF27                IAC_ISR0_IAF27_Msk
+#define IAC_ISR0_IAF28_Pos            (28U)
+#define IAC_ISR0_IAF28_Msk            (0x1UL << IAC_ISR0_IAF28_Pos)              /*!< 0x10000000 */
+#define IAC_ISR0_IAF28                IAC_ISR0_IAF28_Msk
+#define IAC_ISR0_IAF29_Pos            (29U)
+#define IAC_ISR0_IAF29_Msk            (0x1UL << IAC_ISR0_IAF29_Pos)              /*!< 0x20000000 */
+#define IAC_ISR0_IAF29                IAC_ISR0_IAF29_Msk
+#define IAC_ISR0_IAF30_Pos            (30U)
+#define IAC_ISR0_IAF30_Msk            (0x1UL << IAC_ISR0_IAF30_Pos)              /*!< 0x40000000 */
+#define IAC_ISR0_IAF30                IAC_ISR0_IAF30_Msk
+#define IAC_ISR0_IAF31_Pos            (31U)
+#define IAC_ISR0_IAF31_Msk            (0x1UL << IAC_ISR0_IAF31_Pos)              /*!< 0x80000000 */
+#define IAC_ISR0_IAF31                IAC_ISR0_IAF31_Msk
+
+/*******************  Bits definition for IAC_ISR1 register *******************/
+#define IAC_ISR1_IAF32_Pos            (0U)
+#define IAC_ISR1_IAF32_Msk            (0x1UL << IAC_ISR1_IAF32_Pos)              /*!< 0x00000001 */
+#define IAC_ISR1_IAF32                IAC_ISR1_IAF32_Msk
+#define IAC_ISR1_IAF33_Pos            (1U)
+#define IAC_ISR1_IAF33_Msk            (0x1UL << IAC_ISR1_IAF33_Pos)              /*!< 0x00000002 */
+#define IAC_ISR1_IAF33                IAC_ISR1_IAF33_Msk
+#define IAC_ISR1_IAF34_Pos            (2U)
+#define IAC_ISR1_IAF34_Msk            (0x1UL << IAC_ISR1_IAF34_Pos)              /*!< 0x00000004 */
+#define IAC_ISR1_IAF34                IAC_ISR1_IAF34_Msk
+#define IAC_ISR1_IAF35_Pos            (3U)
+#define IAC_ISR1_IAF35_Msk            (0x1UL << IAC_ISR1_IAF35_Pos)              /*!< 0x00000008 */
+#define IAC_ISR1_IAF35                IAC_ISR1_IAF35_Msk
+#define IAC_ISR1_IAF36_Pos            (4U)
+#define IAC_ISR1_IAF36_Msk            (0x1UL << IAC_ISR1_IAF36_Pos)              /*!< 0x00000010 */
+#define IAC_ISR1_IAF36                IAC_ISR1_IAF36_Msk
+#define IAC_ISR1_IAF37_Pos            (5U)
+#define IAC_ISR1_IAF37_Msk            (0x1UL << IAC_ISR1_IAF37_Pos)              /*!< 0x00000020 */
+#define IAC_ISR1_IAF37                IAC_ISR1_IAF37_Msk
+#define IAC_ISR1_IAF38_Pos            (6U)
+#define IAC_ISR1_IAF38_Msk            (0x1UL << IAC_ISR1_IAF38_Pos)              /*!< 0x00000040 */
+#define IAC_ISR1_IAF38                IAC_ISR1_IAF38_Msk
+#define IAC_ISR1_IAF39_Pos            (7U)
+#define IAC_ISR1_IAF39_Msk            (0x1UL << IAC_ISR1_IAF39_Pos)              /*!< 0x00000080 */
+#define IAC_ISR1_IAF39                IAC_ISR1_IAF39_Msk
+#define IAC_ISR1_IAF40_Pos            (8U)
+#define IAC_ISR1_IAF40_Msk            (0x1UL << IAC_ISR1_IAF40_Pos)              /*!< 0x00000100 */
+#define IAC_ISR1_IAF40                IAC_ISR1_IAF40_Msk
+#define IAC_ISR1_IAF41_Pos            (9U)
+#define IAC_ISR1_IAF41_Msk            (0x1UL << IAC_ISR1_IAF41_Pos)              /*!< 0x00000200 */
+#define IAC_ISR1_IAF41                IAC_ISR1_IAF41_Msk
+#define IAC_ISR1_IAF42_Pos            (10U)
+#define IAC_ISR1_IAF42_Msk            (0x1UL << IAC_ISR1_IAF42_Pos)              /*!< 0x00000400 */
+#define IAC_ISR1_IAF42                IAC_ISR1_IAF42_Msk
+#define IAC_ISR1_IAF43_Pos            (11U)
+#define IAC_ISR1_IAF43_Msk            (0x1UL << IAC_ISR1_IAF43_Pos)              /*!< 0x00000800 */
+#define IAC_ISR1_IAF43                IAC_ISR1_IAF43_Msk
+#define IAC_ISR1_IAF44_Pos            (12U)
+#define IAC_ISR1_IAF44_Msk            (0x1UL << IAC_ISR1_IAF44_Pos)              /*!< 0x00001000 */
+#define IAC_ISR1_IAF44                IAC_ISR1_IAF44_Msk
+#define IAC_ISR1_IAF45_Pos            (13U)
+#define IAC_ISR1_IAF45_Msk            (0x1UL << IAC_ISR1_IAF45_Pos)              /*!< 0x00002000 */
+#define IAC_ISR1_IAF45                IAC_ISR1_IAF45_Msk
+#define IAC_ISR1_IAF46_Pos            (14U)
+#define IAC_ISR1_IAF46_Msk            (0x1UL << IAC_ISR1_IAF46_Pos)              /*!< 0x00004000 */
+#define IAC_ISR1_IAF46                IAC_ISR1_IAF46_Msk
+#define IAC_ISR1_IAF47_Pos            (15U)
+#define IAC_ISR1_IAF47_Msk            (0x1UL << IAC_ISR1_IAF47_Pos)              /*!< 0x00008000 */
+#define IAC_ISR1_IAF47                IAC_ISR1_IAF47_Msk
+#define IAC_ISR1_IAF48_Pos            (16U)
+#define IAC_ISR1_IAF48_Msk            (0x1UL << IAC_ISR1_IAF48_Pos)              /*!< 0x00010000 */
+#define IAC_ISR1_IAF48                IAC_ISR1_IAF48_Msk
+#define IAC_ISR1_IAF49_Pos            (17U)
+#define IAC_ISR1_IAF49_Msk            (0x1UL << IAC_ISR1_IAF49_Pos)              /*!< 0x00020000 */
+#define IAC_ISR1_IAF49                IAC_ISR1_IAF49_Msk
+#define IAC_ISR1_IAF50_Pos            (18U)
+#define IAC_ISR1_IAF50_Msk            (0x1UL << IAC_ISR1_IAF50_Pos)              /*!< 0x00040000 */
+#define IAC_ISR1_IAF50                IAC_ISR1_IAF50_Msk
+#define IAC_ISR1_IAF51_Pos            (19U)
+#define IAC_ISR1_IAF51_Msk            (0x1UL << IAC_ISR1_IAF51_Pos)              /*!< 0x00080000 */
+#define IAC_ISR1_IAF51                IAC_ISR1_IAF51_Msk
+#define IAC_ISR1_IAF52_Pos            (20U)
+#define IAC_ISR1_IAF52_Msk            (0x1UL << IAC_ISR1_IAF52_Pos)              /*!< 0x00100000 */
+#define IAC_ISR1_IAF52                IAC_ISR1_IAF52_Msk
+#define IAC_ISR1_IAF53_Pos            (21U)
+#define IAC_ISR1_IAF53_Msk            (0x1UL << IAC_ISR1_IAF53_Pos)              /*!< 0x00200000 */
+#define IAC_ISR1_IAF53                IAC_ISR1_IAF53_Msk
+#define IAC_ISR1_IAF54_Pos            (22U)
+#define IAC_ISR1_IAF54_Msk            (0x1UL << IAC_ISR1_IAF54_Pos)              /*!< 0x00400000 */
+#define IAC_ISR1_IAF54                IAC_ISR1_IAF54_Msk
+#define IAC_ISR1_IAF55_Pos            (23U)
+#define IAC_ISR1_IAF55_Msk            (0x1UL << IAC_ISR1_IAF55_Pos)              /*!< 0x00800000 */
+#define IAC_ISR1_IAF55                IAC_ISR1_IAF55_Msk
+#define IAC_ISR1_IAF56_Pos            (24U)
+#define IAC_ISR1_IAF56_Msk            (0x1UL << IAC_ISR1_IAF56_Pos)              /*!< 0x01000000 */
+#define IAC_ISR1_IAF56                IAC_ISR1_IAF56_Msk
+#define IAC_ISR1_IAF57_Pos            (25U)
+#define IAC_ISR1_IAF57_Msk            (0x1UL << IAC_ISR1_IAF57_Pos)              /*!< 0x02000000 */
+#define IAC_ISR1_IAF57                IAC_ISR1_IAF57_Msk
+#define IAC_ISR1_IAF58_Pos            (26U)
+#define IAC_ISR1_IAF58_Msk            (0x1UL << IAC_ISR1_IAF58_Pos)              /*!< 0x04000000 */
+#define IAC_ISR1_IAF58                IAC_ISR1_IAF58_Msk
+#define IAC_ISR1_IAF60_Pos            (28U)
+#define IAC_ISR1_IAF60_Msk            (0x1UL << IAC_ISR1_IAF60_Pos)              /*!< 0x10000000 */
+#define IAC_ISR1_IAF60                IAC_ISR1_IAF60_Msk
+#define IAC_ISR1_IAF61_Pos            (29U)
+#define IAC_ISR1_IAF61_Msk            (0x1UL << IAC_ISR1_IAF61_Pos)              /*!< 0x20000000 */
+#define IAC_ISR1_IAF61                IAC_ISR1_IAF61_Msk
+#define IAC_ISR1_IAF62_Pos            (30U)
+#define IAC_ISR1_IAF62_Msk            (0x1UL << IAC_ISR1_IAF62_Pos)              /*!< 0x40000000 */
+#define IAC_ISR1_IAF62                IAC_ISR1_IAF62_Msk
+
+/*******************  Bits definition for IAC_ISR2 register *******************/
+#define IAC_ISR2_IAF64_Pos            (0U)
+#define IAC_ISR2_IAF64_Msk            (0x1UL << IAC_ISR2_IAF64_Pos)              /*!< 0x00000001 */
+#define IAC_ISR2_IAF64                IAC_ISR2_IAF64_Msk
+#define IAC_ISR2_IAF65_Pos            (1U)
+#define IAC_ISR2_IAF65_Msk            (0x1UL << IAC_ISR2_IAF65_Pos)              /*!< 0x00000002 */
+#define IAC_ISR2_IAF65                IAC_ISR2_IAF65_Msk
+#define IAC_ISR2_IAF67_Pos            (3U)
+#define IAC_ISR2_IAF67_Msk            (0x1UL << IAC_ISR2_IAF67_Pos)              /*!< 0x00000008 */
+#define IAC_ISR2_IAF67                IAC_ISR2_IAF67_Msk
+#define IAC_ISR2_IAF68_Pos            (4U)
+#define IAC_ISR2_IAF68_Msk            (0x1UL << IAC_ISR2_IAF68_Pos)              /*!< 0x00000010 */
+#define IAC_ISR2_IAF68                IAC_ISR2_IAF68_Msk
+#define IAC_ISR2_IAF69_Pos            (5U)
+#define IAC_ISR2_IAF69_Msk            (0x1UL << IAC_ISR2_IAF69_Pos)              /*!< 0x00000020 */
+#define IAC_ISR2_IAF69                IAC_ISR2_IAF69_Msk
+#define IAC_ISR2_IAF76_Pos            (12U)
+#define IAC_ISR2_IAF76_Msk            (0x1UL << IAC_ISR2_IAF76_Pos)              /*!< 0x00001000 */
+#define IAC_ISR2_IAF76                IAC_ISR2_IAF76_Msk
+#define IAC_ISR2_IAF77_Pos            (13U)
+#define IAC_ISR2_IAF77_Msk            (0x1UL << IAC_ISR2_IAF77_Pos)              /*!< 0x00002000 */
+#define IAC_ISR2_IAF77                IAC_ISR2_IAF77_Msk
+#define IAC_ISR2_IAF78_Pos            (14U)
+#define IAC_ISR2_IAF78_Msk            (0x1UL << IAC_ISR2_IAF78_Pos)              /*!< 0x00004000 */
+#define IAC_ISR2_IAF78                IAC_ISR2_IAF78_Msk
+#define IAC_ISR2_IAF79_Pos            (15U)
+#define IAC_ISR2_IAF79_Msk            (0x1UL << IAC_ISR2_IAF79_Pos)              /*!< 0x00008000 */
+#define IAC_ISR2_IAF79                IAC_ISR2_IAF79_Msk
+#define IAC_ISR2_IAF80_Pos            (16U)
+#define IAC_ISR2_IAF80_Msk            (0x1UL << IAC_ISR2_IAF80_Pos)              /*!< 0x00010000 */
+#define IAC_ISR2_IAF80                IAC_ISR2_IAF80_Msk
+#define IAC_ISR2_IAF81_Pos            (17U)
+#define IAC_ISR2_IAF81_Msk            (0x1UL << IAC_ISR2_IAF81_Pos)              /*!< 0x00020000 */
+#define IAC_ISR2_IAF81                IAC_ISR2_IAF81_Msk
+#define IAC_ISR2_IAF82_Pos            (18U)
+#define IAC_ISR2_IAF82_Msk            (0x1UL << IAC_ISR2_IAF82_Pos)              /*!< 0x00040000 */
+#define IAC_ISR2_IAF82                IAC_ISR2_IAF82_Msk
+#define IAC_ISR2_IAF83_Pos            (19U)
+#define IAC_ISR2_IAF83_Msk            (0x1UL << IAC_ISR2_IAF83_Pos)              /*!< 0x00080000 */
+#define IAC_ISR2_IAF83                IAC_ISR2_IAF83_Msk
+#define IAC_ISR2_IAF84_Pos            (20U)
+#define IAC_ISR2_IAF84_Msk            (0x1UL << IAC_ISR2_IAF84_Pos)              /*!< 0x00100000 */
+#define IAC_ISR2_IAF84                IAC_ISR2_IAF84_Msk
+#define IAC_ISR2_IAF86_Pos            (22U)
+#define IAC_ISR2_IAF86_Msk            (0x1UL << IAC_ISR2_IAF86_Pos)              /*!< 0x00400000 */
+#define IAC_ISR2_IAF86                IAC_ISR2_IAF86_Msk
+#define IAC_ISR2_IAF87_Pos            (23U)
+#define IAC_ISR2_IAF87_Msk            (0x1UL << IAC_ISR2_IAF87_Pos)              /*!< 0x00800000 */
+#define IAC_ISR2_IAF87                IAC_ISR2_IAF87_Msk
+#define IAC_ISR2_IAF88_Pos            (24U)
+#define IAC_ISR2_IAF88_Msk            (0x1UL << IAC_ISR2_IAF88_Pos)              /*!< 0x01000000 */
+#define IAC_ISR2_IAF88                IAC_ISR2_IAF88_Msk
+#define IAC_ISR2_IAF89_Pos            (25U)
+#define IAC_ISR2_IAF89_Msk            (0x1UL << IAC_ISR2_IAF89_Pos)              /*!< 0x02000000 */
+#define IAC_ISR2_IAF89                IAC_ISR2_IAF89_Msk
+#define IAC_ISR2_IAF90_Pos            (26U)
+#define IAC_ISR2_IAF90_Msk            (0x1UL << IAC_ISR2_IAF90_Pos)              /*!< 0x04000000 */
+#define IAC_ISR2_IAF90                IAC_ISR2_IAF90_Msk
+#define IAC_ISR2_IAF92_Pos            (28U)
+#define IAC_ISR2_IAF92_Msk            (0x1UL << IAC_ISR2_IAF92_Pos)              /*!< 0x10000000 */
+#define IAC_ISR2_IAF92                IAC_ISR2_IAF92_Msk
+#define IAC_ISR2_IAF93_Pos            (29U)
+#define IAC_ISR2_IAF93_Msk            (0x1UL << IAC_ISR2_IAF93_Pos)              /*!< 0x20000000 */
+#define IAC_ISR2_IAF93                IAC_ISR2_IAF93_Msk
+#define IAC_ISR2_IAF94_Pos            (30U)
+#define IAC_ISR2_IAF94_Msk            (0x1UL << IAC_ISR2_IAF94_Pos)              /*!< 0x40000000 */
+#define IAC_ISR2_IAF94                IAC_ISR2_IAF94_Msk
+#define IAC_ISR2_IAF95_Pos            (31U)
+#define IAC_ISR2_IAF95_Msk            (0x1UL << IAC_ISR2_IAF95_Pos)              /*!< 0x80000000 */
+#define IAC_ISR2_IAF95                IAC_ISR2_IAF95_Msk
+
+/*******************  Bits definition for IAC_ISR3 register *******************/
+#define IAC_ISR3_IAF96_Pos            (0U)
+#define IAC_ISR3_IAF96_Msk            (0x1UL << IAC_ISR3_IAF96_Pos)              /*!< 0x00000001 */
+#define IAC_ISR3_IAF96                IAC_ISR3_IAF96_Msk
+#define IAC_ISR3_IAF97_Pos            (1U)
+#define IAC_ISR3_IAF97_Msk            (0x1UL << IAC_ISR3_IAF97_Pos)              /*!< 0x00000002 */
+#define IAC_ISR3_IAF97                IAC_ISR3_IAF97_Msk
+#define IAC_ISR3_IAF98_Pos            (2U)
+#define IAC_ISR3_IAF98_Msk            (0x1UL << IAC_ISR3_IAF98_Pos)              /*!< 0x00000004 */
+#define IAC_ISR3_IAF98                IAC_ISR3_IAF98_Msk
+#define IAC_ISR3_IAF99_Pos            (3U)
+#define IAC_ISR3_IAF99_Msk            (0x1UL << IAC_ISR3_IAF99_Pos)              /*!< 0x00000008 */
+#define IAC_ISR3_IAF99                IAC_ISR3_IAF99_Msk
+#define IAC_ISR3_IAF100_Pos           (4U)
+#define IAC_ISR3_IAF100_Msk           (0x1UL << IAC_ISR3_IAF100_Pos)             /*!< 0x00000010 */
+#define IAC_ISR3_IAF100               IAC_ISR3_IAF100_Msk
+#define IAC_ISR3_IAF101_Pos           (5U)
+#define IAC_ISR3_IAF101_Msk           (0x1UL << IAC_ISR3_IAF101_Pos)             /*!< 0x00000020 */
+#define IAC_ISR3_IAF101               IAC_ISR3_IAF101_Msk
+#define IAC_ISR3_IAF102_Pos           (6U)
+#define IAC_ISR3_IAF102_Msk           (0x1UL << IAC_ISR3_IAF102_Pos)             /*!< 0x00000040 */
+#define IAC_ISR3_IAF102               IAC_ISR3_IAF102_Msk
+#define IAC_ISR3_IAF103_Pos           (7U)
+#define IAC_ISR3_IAF103_Msk           (0x1UL << IAC_ISR3_IAF103_Pos)             /*!< 0x00000080 */
+#define IAC_ISR3_IAF103               IAC_ISR3_IAF103_Msk
+#define IAC_ISR3_IAF104_Pos           (8U)
+#define IAC_ISR3_IAF104_Msk           (0x1UL << IAC_ISR3_IAF104_Pos)             /*!< 0x00000100 */
+#define IAC_ISR3_IAF104               IAC_ISR3_IAF104_Msk
+#define IAC_ISR3_IAF106_Pos           (10U)
+#define IAC_ISR3_IAF106_Msk           (0x1UL << IAC_ISR3_IAF106_Pos)             /*!< 0x00000400 */
+#define IAC_ISR3_IAF106               IAC_ISR3_IAF106_Msk
+
+/*******************  Bits definition for IAC_ISR4 register *******************/
+#define IAC_ISR4_IAF128_Pos           (0U)
+#define IAC_ISR4_IAF128_Msk           (0x1UL << IAC_ISR4_IAF128_Pos)             /*!< 0x00000001 */
+#define IAC_ISR4_IAF128               IAC_ISR4_IAF128_Msk
+#define IAC_ISR4_IAF129_Pos           (1U)
+#define IAC_ISR4_IAF129_Msk           (0x1UL << IAC_ISR4_IAF129_Pos)             /*!< 0x00000002 */
+#define IAC_ISR4_IAF129               IAC_ISR4_IAF129_Msk
+#define IAC_ISR4_IAF130_Pos           (2U)
+#define IAC_ISR4_IAF130_Msk           (0x1UL << IAC_ISR4_IAF130_Pos)             /*!< 0x00000004 */
+#define IAC_ISR4_IAF130               IAC_ISR4_IAF130_Msk
+#define IAC_ISR4_IAF131_Pos           (3U)
+#define IAC_ISR4_IAF131_Msk           (0x1UL << IAC_ISR4_IAF131_Pos)             /*!< 0x00000008 */
+#define IAC_ISR4_IAF131               IAC_ISR4_IAF131_Msk
+#define IAC_ISR4_IAF133_Pos           (5U)
+#define IAC_ISR4_IAF133_Msk           (0x1UL << IAC_ISR4_IAF133_Pos)             /*!< 0x00000020 */
+#define IAC_ISR4_IAF133               IAC_ISR4_IAF133_Msk
+#define IAC_ISR4_IAF134_Pos           (6U)
+#define IAC_ISR4_IAF134_Msk           (0x1UL << IAC_ISR4_IAF134_Pos)             /*!< 0x00000040 */
+#define IAC_ISR4_IAF134               IAC_ISR4_IAF134_Msk
+#define IAC_ISR4_IAF135_Pos           (7U)
+#define IAC_ISR4_IAF135_Msk           (0x1UL << IAC_ISR4_IAF135_Pos)             /*!< 0x00000080 */
+#define IAC_ISR4_IAF135               IAC_ISR4_IAF135_Msk
+#define IAC_ISR4_IAF136_Pos           (8U)
+#define IAC_ISR4_IAF136_Msk           (0x1UL << IAC_ISR4_IAF136_Pos)             /*!< 0x00000100 */
+#define IAC_ISR4_IAF136               IAC_ISR4_IAF136_Msk
+#define IAC_ISR4_IAF137_Pos           (9U)
+#define IAC_ISR4_IAF137_Msk           (0x1UL << IAC_ISR4_IAF137_Pos)             /*!< 0x00000200 */
+#define IAC_ISR4_IAF137               IAC_ISR4_IAF137_Msk
+#define IAC_ISR4_IAF138_Pos           (10U)
+#define IAC_ISR4_IAF138_Msk           (0x1UL << IAC_ISR4_IAF138_Pos)             /*!< 0x00000400 */
+#define IAC_ISR4_IAF138               IAC_ISR4_IAF138_Msk
+#define IAC_ISR4_IAF139_Pos           (11U)
+#define IAC_ISR4_IAF139_Msk           (0x1UL << IAC_ISR4_IAF139_Pos)             /*!< 0x00000800 */
+#define IAC_ISR4_IAF139               IAC_ISR4_IAF139_Msk
+#define IAC_ISR4_IAF140_Pos           (12U)
+#define IAC_ISR4_IAF140_Msk           (0x1UL << IAC_ISR4_IAF140_Pos)             /*!< 0x00001000 */
+#define IAC_ISR4_IAF140               IAC_ISR4_IAF140_Msk
+#define IAC_ISR4_IAF141_Pos           (13U)
+#define IAC_ISR4_IAF141_Msk           (0x1UL << IAC_ISR4_IAF141_Pos)             /*!< 0x00002000 */
+#define IAC_ISR4_IAF141               IAC_ISR4_IAF141_Msk
+#define IAC_ISR4_IAF142_Pos           (14U)
+#define IAC_ISR4_IAF142_Msk           (0x1UL << IAC_ISR4_IAF142_Pos)             /*!< 0x00004000 */
+#define IAC_ISR4_IAF142               IAC_ISR4_IAF142_Msk
+#define IAC_ISR4_IAF143_Pos           (15U)
+#define IAC_ISR4_IAF143_Msk           (0x1UL << IAC_ISR4_IAF143_Pos)             /*!< 0x00008000 */
+#define IAC_ISR4_IAF143               IAC_ISR4_IAF143_Msk
+#define IAC_ISR4_IAF144_Pos           (16U)
+#define IAC_ISR4_IAF144_Msk           (0x1UL << IAC_ISR4_IAF144_Pos)             /*!< 0x00010000 */
+#define IAC_ISR4_IAF144               IAC_ISR4_IAF144_Msk
+#define IAC_ISR4_IAF145_Pos           (17U)
+#define IAC_ISR4_IAF145_Msk           (0x1UL << IAC_ISR4_IAF145_Pos)             /*!< 0x00020000 */
+#define IAC_ISR4_IAF145               IAC_ISR4_IAF145_Msk
+#define IAC_ISR4_IAF146_Pos           (18U)
+#define IAC_ISR4_IAF146_Msk           (0x1UL << IAC_ISR4_IAF146_Pos)             /*!< 0x00040000 */
+#define IAC_ISR4_IAF146               IAC_ISR4_IAF146_Msk
+#define IAC_ISR4_IAF147_Pos           (19U)
+#define IAC_ISR4_IAF147_Msk           (0x1UL << IAC_ISR4_IAF147_Pos)             /*!< 0x00080000 */
+#define IAC_ISR4_IAF147               IAC_ISR4_IAF147_Msk
+#define IAC_ISR4_IAF149_Pos           (21U)
+#define IAC_ISR4_IAF149_Msk           (0x1UL << IAC_ISR4_IAF149_Pos)             /*!< 0x00200000 */
+#define IAC_ISR4_IAF149               IAC_ISR4_IAF149_Msk
+#define IAC_ISR4_IAF150_Pos           (22U)
+#define IAC_ISR4_IAF150_Msk           (0x1UL << IAC_ISR4_IAF150_Pos)             /*!< 0x00400000 */
+#define IAC_ISR4_IAF150               IAC_ISR4_IAF150_Msk
+#define IAC_ISR4_IAF151_Pos           (23U)
+#define IAC_ISR4_IAF151_Msk           (0x1UL << IAC_ISR4_IAF151_Pos)             /*!< 0x00800000 */
+#define IAC_ISR4_IAF151               IAC_ISR4_IAF151_Msk
+#define IAC_ISR4_IAF152_Pos           (24U)
+#define IAC_ISR4_IAF152_Msk           (0x1UL << IAC_ISR4_IAF152_Pos)             /*!< 0x01000000 */
+#define IAC_ISR4_IAF152               IAC_ISR4_IAF152_Msk
+#define IAC_ISR4_IAF153_Pos           (25U)
+#define IAC_ISR4_IAF153_Msk           (0x1UL << IAC_ISR4_IAF153_Pos)             /*!< 0x02000000 */
+#define IAC_ISR4_IAF153               IAC_ISR4_IAF153_Msk
+#define IAC_ISR4_IAF155_Pos           (27U)
+#define IAC_ISR4_IAF155_Msk           (0x1UL << IAC_ISR4_IAF155_Pos)             /*!< 0x08000000 */
+#define IAC_ISR4_IAF155               IAC_ISR4_IAF155_Msk
+#define IAC_ISR4_IAF156_Pos           (28U)
+#define IAC_ISR4_IAF156_Msk           (0x1UL << IAC_ISR4_IAF156_Pos)             /*!< 0x10000000 */
+#define IAC_ISR4_IAF156               IAC_ISR4_IAF156_Msk
+#define IAC_ISR4_IAF157_Pos           (29U)
+#define IAC_ISR4_IAF157_Msk           (0x1UL << IAC_ISR4_IAF157_Pos)             /*!< 0x20000000 */
+#define IAC_ISR4_IAF157               IAC_ISR4_IAF157_Msk
+
+/*******************  Bits definition for IAC_ICR0 register *******************/
+#define IAC_ICR0_IACF0_Pos            (0U)
+#define IAC_ICR0_IACF0_Msk            (0x1UL << IAC_ICR0_IACF0_Pos)               /*!< 0x00000001 */
+#define IAC_ICR0_IACF0                IAC_ICR0_IACF0_Msk
+#define IAC_ICR0_IACF1_Pos            (1U)
+#define IAC_ICR0_IACF1_Msk            (0x1UL << IAC_ICR0_IACF1_Pos)               /*!< 0x00000002 */
+#define IAC_ICR0_IACF1                IAC_ICR0_IACF1_Msk
+#define IAC_ICR0_IACF2_Pos            (2U)
+#define IAC_ICR0_IACF2_Msk            (0x1UL << IAC_ICR0_IACF2_Pos)               /*!< 0x00000004 */
+#define IAC_ICR0_IACF2                IAC_ICR0_IACF2_Msk
+#define IAC_ICR0_IACF3_Pos            (3U)
+#define IAC_ICR0_IACF3_Msk            (0x1UL << IAC_ICR0_IACF3_Pos)               /*!< 0x00000008 */
+#define IAC_ICR0_IACF3                IAC_ICR0_IACF3_Msk
+#define IAC_ICR0_IACF4_Pos            (4U)
+#define IAC_ICR0_IACF4_Msk            (0x1UL << IAC_ICR0_IACF4_Pos)               /*!< 0x00000010 */
+#define IAC_ICR0_IACF4                IAC_ICR0_IACF4_Msk
+#define IAC_ICR0_IACF5_Pos            (5U)
+#define IAC_ICR0_IACF5_Msk            (0x1UL << IAC_ICR0_IACF5_Pos)               /*!< 0x00000020 */
+#define IAC_ICR0_IACF5                IAC_ICR0_IACF5_Msk
+#define IAC_ICR0_IACF6_Pos            (6U)
+#define IAC_ICR0_IACF6_Msk            (0x1UL << IAC_ICR0_IACF6_Pos)               /*!< 0x00000040 */
+#define IAC_ICR0_IACF6                IAC_ICR0_IACF6_Msk
+#define IAC_ICR0_IACF8_Pos            (8U)
+#define IAC_ICR0_IACF8_Msk            (0x1UL << IAC_ICR0_IACF8_Pos)               /*!< 0x00000100 */
+#define IAC_ICR0_IACF8                IAC_ICR0_IACF8_Msk
+#define IAC_ICR0_IACF9_Pos            (9U)
+#define IAC_ICR0_IACF9_Msk            (0x1UL << IAC_ICR0_IACF9_Pos)               /*!< 0x00000200 */
+#define IAC_ICR0_IACF9                IAC_ICR0_IACF9_Msk
+#define IAC_ICR0_IACF10_Pos           (10U)
+#define IAC_ICR0_IACF10_Msk           (0x1UL << IAC_ICR0_IACF10_Pos)              /*!< 0x00000400 */
+#define IAC_ICR0_IACF10               IAC_ICR0_IACF10_Msk
+#define IAC_ICR0_IACF11_Pos           (11U)
+#define IAC_ICR0_IACF11_Msk           (0x1UL << IAC_ICR0_IACF11_Pos)              /*!< 0x00000800 */
+#define IAC_ICR0_IACF11               IAC_ICR0_IACF11_Msk
+#define IAC_ICR0_IACF12_Pos           (12U)
+#define IAC_ICR0_IACF12_Msk           (0x1UL << IAC_ICR0_IACF12_Pos)              /*!< 0x00001000 */
+#define IAC_ICR0_IACF12               IAC_ICR0_IACF12_Msk
+#define IAC_ICR0_IACF13_Pos           (13U)
+#define IAC_ICR0_IACF13_Msk           (0x1UL << IAC_ICR0_IACF13_Pos)              /*!< 0x00002000 */
+#define IAC_ICR0_IACF13               IAC_ICR0_IACF13_Msk
+#define IAC_ICR0_IACF14_Pos           (14U)
+#define IAC_ICR0_IACF14_Msk           (0x1UL << IAC_ICR0_IACF14_Pos)              /*!< 0x00004000 */
+#define IAC_ICR0_IACF14               IAC_ICR0_IACF14_Msk
+#define IAC_ICR0_IACF15_Pos           (15U)
+#define IAC_ICR0_IACF15_Msk           (0x1UL << IAC_ICR0_IACF15_Pos)              /*!< 0x00008000 */
+#define IAC_ICR0_IACF15               IAC_ICR0_IACF15_Msk
+#define IAC_ICR0_IACF16_Pos           (16U)
+#define IAC_ICR0_IACF16_Msk           (0x1UL << IAC_ICR0_IACF16_Pos)              /*!< 0x00010000 */
+#define IAC_ICR0_IACF16               IAC_ICR0_IACF16_Msk
+#define IAC_ICR0_IACF17_Pos           (17U)
+#define IAC_ICR0_IACF17_Msk           (0x1UL << IAC_ICR0_IACF17_Pos)              /*!< 0x00020000 */
+#define IAC_ICR0_IACF17               IAC_ICR0_IACF17_Msk
+#define IAC_ICR0_IACF18_Pos           (18U)
+#define IAC_ICR0_IACF18_Msk           (0x1UL << IAC_ICR0_IACF18_Pos)              /*!< 0x00040000 */
+#define IAC_ICR0_IACF18               IAC_ICR0_IACF18_Msk
+#define IAC_ICR0_IACF19_Pos           (19U)
+#define IAC_ICR0_IACF19_Msk           (0x1UL << IAC_ICR0_IACF19_Pos)              /*!< 0x00080000 */
+#define IAC_ICR0_IACF19               IAC_ICR0_IACF19_Msk
+#define IAC_ICR0_IACF20_Pos           (20U)
+#define IAC_ICR0_IACF20_Msk           (0x1UL << IAC_ICR0_IACF20_Pos)              /*!< 0x00100000 */
+#define IAC_ICR0_IACF20               IAC_ICR0_IACF20_Msk
+#define IAC_ICR0_IACF21_Pos           (21U)
+#define IAC_ICR0_IACF21_Msk           (0x1UL << IAC_ICR0_IACF21_Pos)              /*!< 0x00200000 */
+#define IAC_ICR0_IACF21               IAC_ICR0_IACF21_Msk
+#define IAC_ICR0_IACF22_Pos           (22U)
+#define IAC_ICR0_IACF22_Msk           (0x1UL << IAC_ICR0_IACF22_Pos)              /*!< 0x00400000 */
+#define IAC_ICR0_IACF22               IAC_ICR0_IACF22_Msk
+#define IAC_ICR0_IACF23_Pos           (23U)
+#define IAC_ICR0_IACF23_Msk           (0x1UL << IAC_ICR0_IACF23_Pos)              /*!< 0x00800000 */
+#define IAC_ICR0_IACF23               IAC_ICR0_IACF23_Msk
+#define IAC_ICR0_IACF24_Pos           (24U)
+#define IAC_ICR0_IACF24_Msk           (0x1UL << IAC_ICR0_IACF24_Pos)              /*!< 0x01000000 */
+#define IAC_ICR0_IACF24               IAC_ICR0_IACF24_Msk
+#define IAC_ICR0_IACF25_Pos           (25U)
+#define IAC_ICR0_IACF25_Msk           (0x1UL << IAC_ICR0_IACF25_Pos)              /*!< 0x02000000 */
+#define IAC_ICR0_IACF25               IAC_ICR0_IACF25_Msk
+#define IAC_ICR0_IACF26_Pos           (26U)
+#define IAC_ICR0_IACF26_Msk           (0x1UL << IAC_ICR0_IACF26_Pos)              /*!< 0x04000000 */
+#define IAC_ICR0_IACF26               IAC_ICR0_IACF26_Msk
+#define IAC_ICR0_IACF27_Pos           (27U)
+#define IAC_ICR0_IACF27_Msk           (0x1UL << IAC_ICR0_IACF27_Pos)              /*!< 0x08000000 */
+#define IAC_ICR0_IACF27               IAC_ICR0_IACF27_Msk
+#define IAC_ICR0_IACF28_Pos           (28U)
+#define IAC_ICR0_IACF28_Msk           (0x1UL << IAC_ICR0_IACF28_Pos)              /*!< 0x10000000 */
+#define IAC_ICR0_IACF28               IAC_ICR0_IACF28_Msk
+#define IAC_ICR0_IACF29_Pos           (29U)
+#define IAC_ICR0_IACF29_Msk           (0x1UL << IAC_ICR0_IACF29_Pos)              /*!< 0x20000000 */
+#define IAC_ICR0_IACF29               IAC_ICR0_IACF29_Msk
+#define IAC_ICR0_IACF30_Pos           (30U)
+#define IAC_ICR0_IACF30_Msk           (0x1UL << IAC_ICR0_IACF30_Pos)              /*!< 0x40000000 */
+#define IAC_ICR0_IACF30               IAC_ICR0_IACF30_Msk
+#define IAC_ICR0_IACF31_Pos           (31U)
+#define IAC_ICR0_IACF31_Msk           (0x1UL << IAC_ICR0_IACF31_Pos)              /*!< 0x80000000 */
+#define IAC_ICR0_IACF31               IAC_ICR0_IACF31_Msk
+
+/*******************  Bits definition for IAC_ICR1 register *******************/
+#define IAC_ICR1_IACF32_Pos           (0U)
+#define IAC_ICR1_IACF32_Msk           (0x1UL << IAC_ICR1_IACF32_Pos)              /*!< 0x00000001 */
+#define IAC_ICR1_IACF32               IAC_ICR1_IACF32_Msk
+#define IAC_ICR1_IACF33_Pos           (1U)
+#define IAC_ICR1_IACF33_Msk           (0x1UL << IAC_ICR1_IACF33_Pos)              /*!< 0x00000002 */
+#define IAC_ICR1_IACF33               IAC_ICR1_IACF33_Msk
+#define IAC_ICR1_IACF34_Pos           (2U)
+#define IAC_ICR1_IACF34_Msk           (0x1UL << IAC_ICR1_IACF34_Pos)              /*!< 0x00000004 */
+#define IAC_ICR1_IACF34               IAC_ICR1_IACF34_Msk
+#define IAC_ICR1_IACF35_Pos           (3U)
+#define IAC_ICR1_IACF35_Msk           (0x1UL << IAC_ICR1_IACF35_Pos)              /*!< 0x00000008 */
+#define IAC_ICR1_IACF35               IAC_ICR1_IACF35_Msk
+#define IAC_ICR1_IACF36_Pos           (4U)
+#define IAC_ICR1_IACF36_Msk           (0x1UL << IAC_ICR1_IACF36_Pos)              /*!< 0x00000010 */
+#define IAC_ICR1_IACF36               IAC_ICR1_IACF36_Msk
+#define IAC_ICR1_IACF37_Pos           (5U)
+#define IAC_ICR1_IACF37_Msk           (0x1UL << IAC_ICR1_IACF37_Pos)              /*!< 0x00000020 */
+#define IAC_ICR1_IACF37               IAC_ICR1_IACF37_Msk
+#define IAC_ICR1_IACF38_Pos           (6U)
+#define IAC_ICR1_IACF38_Msk           (0x1UL << IAC_ICR1_IACF38_Pos)              /*!< 0x00000040 */
+#define IAC_ICR1_IACF38               IAC_ICR1_IACF38_Msk
+#define IAC_ICR1_IACF39_Pos           (7U)
+#define IAC_ICR1_IACF39_Msk           (0x1UL << IAC_ICR1_IACF39_Pos)              /*!< 0x00000080 */
+#define IAC_ICR1_IACF39               IAC_ICR1_IACF39_Msk
+#define IAC_ICR1_IACF40_Pos           (8U)
+#define IAC_ICR1_IACF40_Msk           (0x1UL << IAC_ICR1_IACF40_Pos)              /*!< 0x00000100 */
+#define IAC_ICR1_IACF40               IAC_ICR1_IACF40_Msk
+#define IAC_ICR1_IACF41_Pos           (9U)
+#define IAC_ICR1_IACF41_Msk           (0x1UL << IAC_ICR1_IACF41_Pos)              /*!< 0x00000200 */
+#define IAC_ICR1_IACF41               IAC_ICR1_IACF41_Msk
+#define IAC_ICR1_IACF42_Pos           (10U)
+#define IAC_ICR1_IACF42_Msk           (0x1UL << IAC_ICR1_IACF42_Pos)              /*!< 0x00000400 */
+#define IAC_ICR1_IACF42               IAC_ICR1_IACF42_Msk
+#define IAC_ICR1_IACF43_Pos           (11U)
+#define IAC_ICR1_IACF43_Msk           (0x1UL << IAC_ICR1_IACF43_Pos)              /*!< 0x00000800 */
+#define IAC_ICR1_IACF43               IAC_ICR1_IACF43_Msk
+#define IAC_ICR1_IACF44_Pos           (12U)
+#define IAC_ICR1_IACF44_Msk           (0x1UL << IAC_ICR1_IACF44_Pos)              /*!< 0x00001000 */
+#define IAC_ICR1_IACF44               IAC_ICR1_IACF44_Msk
+#define IAC_ICR1_IACF45_Pos           (13U)
+#define IAC_ICR1_IACF45_Msk           (0x1UL << IAC_ICR1_IACF45_Pos)              /*!< 0x00002000 */
+#define IAC_ICR1_IACF45               IAC_ICR1_IACF45_Msk
+#define IAC_ICR1_IACF46_Pos           (14U)
+#define IAC_ICR1_IACF46_Msk           (0x1UL << IAC_ICR1_IACF46_Pos)              /*!< 0x00004000 */
+#define IAC_ICR1_IACF46               IAC_ICR1_IACF46_Msk
+#define IAC_ICR1_IACF47_Pos           (15U)
+#define IAC_ICR1_IACF47_Msk           (0x1UL << IAC_ICR1_IACF47_Pos)              /*!< 0x00008000 */
+#define IAC_ICR1_IACF47               IAC_ICR1_IACF47_Msk
+#define IAC_ICR1_IACF48_Pos           (16U)
+#define IAC_ICR1_IACF48_Msk           (0x1UL << IAC_ICR1_IACF48_Pos)              /*!< 0x00010000 */
+#define IAC_ICR1_IACF48               IAC_ICR1_IACF48_Msk
+#define IAC_ICR1_IACF49_Pos           (17U)
+#define IAC_ICR1_IACF49_Msk           (0x1UL << IAC_ICR1_IACF49_Pos)              /*!< 0x00020000 */
+#define IAC_ICR1_IACF49               IAC_ICR1_IACF49_Msk
+#define IAC_ICR1_IACF50_Pos           (18U)
+#define IAC_ICR1_IACF50_Msk           (0x1UL << IAC_ICR1_IACF50_Pos)              /*!< 0x00040000 */
+#define IAC_ICR1_IACF50               IAC_ICR1_IACF50_Msk
+#define IAC_ICR1_IACF51_Pos           (19U)
+#define IAC_ICR1_IACF51_Msk           (0x1UL << IAC_ICR1_IACF51_Pos)              /*!< 0x00080000 */
+#define IAC_ICR1_IACF51               IAC_ICR1_IACF51_Msk
+#define IAC_ICR1_IACF52_Pos           (20U)
+#define IAC_ICR1_IACF52_Msk           (0x1UL << IAC_ICR1_IACF52_Pos)              /*!< 0x00100000 */
+#define IAC_ICR1_IACF52               IAC_ICR1_IACF52_Msk
+#define IAC_ICR1_IACF53_Pos           (21U)
+#define IAC_ICR1_IACF53_Msk           (0x1UL << IAC_ICR1_IACF53_Pos)              /*!< 0x00200000 */
+#define IAC_ICR1_IACF53               IAC_ICR1_IACF53_Msk
+#define IAC_ICR1_IACF54_Pos           (22U)
+#define IAC_ICR1_IACF54_Msk           (0x1UL << IAC_ICR1_IACF54_Pos)              /*!< 0x00400000 */
+#define IAC_ICR1_IACF54               IAC_ICR1_IACF54_Msk
+#define IAC_ICR1_IACF55_Pos           (23U)
+#define IAC_ICR1_IACF55_Msk           (0x1UL << IAC_ICR1_IACF55_Pos)              /*!< 0x00800000 */
+#define IAC_ICR1_IACF55               IAC_ICR1_IACF55_Msk
+#define IAC_ICR1_IACF56_Pos           (24U)
+#define IAC_ICR1_IACF56_Msk           (0x1UL << IAC_ICR1_IACF56_Pos)              /*!< 0x01000000 */
+#define IAC_ICR1_IACF56               IAC_ICR1_IACF56_Msk
+#define IAC_ICR1_IACF57_Pos           (25U)
+#define IAC_ICR1_IACF57_Msk           (0x1UL << IAC_ICR1_IACF57_Pos)              /*!< 0x02000000 */
+#define IAC_ICR1_IACF57               IAC_ICR1_IACF57_Msk
+#define IAC_ICR1_IACF58_Pos           (26U)
+#define IAC_ICR1_IACF58_Msk           (0x1UL << IAC_ICR1_IACF58_Pos)              /*!< 0x04000000 */
+#define IAC_ICR1_IACF58               IAC_ICR1_IACF58_Msk
+#define IAC_ICR1_IACF60_Pos           (28U)
+#define IAC_ICR1_IACF60_Msk           (0x1UL << IAC_ICR1_IACF60_Pos)              /*!< 0x10000000 */
+#define IAC_ICR1_IACF60               IAC_ICR1_IACF60_Msk
+#define IAC_ICR1_IACF61_Pos           (29U)
+#define IAC_ICR1_IACF61_Msk           (0x1UL << IAC_ICR1_IACF61_Pos)              /*!< 0x20000000 */
+#define IAC_ICR1_IACF61               IAC_ICR1_IACF61_Msk
+#define IAC_ICR1_IACF62_Pos           (30U)
+#define IAC_ICR1_IACF62_Msk           (0x1UL << IAC_ICR1_IACF62_Pos)              /*!< 0x40000000 */
+#define IAC_ICR1_IACF62               IAC_ICR1_IACF62_Msk
+
+/*******************  Bits definition for IAC_ICR2 register *******************/
+#define IAC_ICR2_IACF64_Pos           (0U)
+#define IAC_ICR2_IACF64_Msk           (0x1UL << IAC_ICR2_IACF64_Pos)              /*!< 0x00000001 */
+#define IAC_ICR2_IACF64               IAC_ICR2_IACF64_Msk
+#define IAC_ICR2_IACF65_Pos           (1U)
+#define IAC_ICR2_IACF65_Msk           (0x1UL << IAC_ICR2_IACF65_Pos)              /*!< 0x00000002 */
+#define IAC_ICR2_IACF65               IAC_ICR2_IACF65_Msk
+#define IAC_ICR2_IACF67_Pos           (3U)
+#define IAC_ICR2_IACF67_Msk           (0x1UL << IAC_ICR2_IACF67_Pos)              /*!< 0x00000008 */
+#define IAC_ICR2_IACF67               IAC_ICR2_IACF67_Msk
+#define IAC_ICR2_IACF68_Pos           (4U)
+#define IAC_ICR2_IACF68_Msk           (0x1UL << IAC_ICR2_IACF68_Pos)              /*!< 0x00000010 */
+#define IAC_ICR2_IACF68               IAC_ICR2_IACF68_Msk
+#define IAC_ICR2_IACF69_Pos           (5U)
+#define IAC_ICR2_IACF69_Msk           (0x1UL << IAC_ICR2_IACF69_Pos)              /*!< 0x00000020 */
+#define IAC_ICR2_IACF69               IAC_ICR2_IACF69_Msk
+#define IAC_ICR2_IACF76_Pos           (12U)
+#define IAC_ICR2_IACF76_Msk           (0x1UL << IAC_ICR2_IACF76_Pos)              /*!< 0x00001000 */
+#define IAC_ICR2_IACF76               IAC_ICR2_IACF76_Msk
+#define IAC_ICR2_IACF77_Pos           (13U)
+#define IAC_ICR2_IACF77_Msk           (0x1UL << IAC_ICR2_IACF77_Pos)              /*!< 0x00002000 */
+#define IAC_ICR2_IACF77               IAC_ICR2_IACF77_Msk
+#define IAC_ICR2_IACF78_Pos           (14U)
+#define IAC_ICR2_IACF78_Msk           (0x1UL << IAC_ICR2_IACF78_Pos)              /*!< 0x00004000 */
+#define IAC_ICR2_IACF78               IAC_ICR2_IACF78_Msk
+#define IAC_ICR2_IACF79_Pos           (15U)
+#define IAC_ICR2_IACF79_Msk           (0x1UL << IAC_ICR2_IACF79_Pos)              /*!< 0x00008000 */
+#define IAC_ICR2_IACF79               IAC_ICR2_IACF79_Msk
+#define IAC_ICR2_IACF80_Pos           (16U)
+#define IAC_ICR2_IACF80_Msk           (0x1UL << IAC_ICR2_IACF80_Pos)              /*!< 0x00010000 */
+#define IAC_ICR2_IACF80               IAC_ICR2_IACF80_Msk
+#define IAC_ICR2_IACF81_Pos           (17U)
+#define IAC_ICR2_IACF81_Msk           (0x1UL << IAC_ICR2_IACF81_Pos)              /*!< 0x00020000 */
+#define IAC_ICR2_IACF81               IAC_ICR2_IACF81_Msk
+#define IAC_ICR2_IACF82_Pos           (18U)
+#define IAC_ICR2_IACF82_Msk           (0x1UL << IAC_ICR2_IACF82_Pos)              /*!< 0x00040000 */
+#define IAC_ICR2_IACF82               IAC_ICR2_IACF82_Msk
+#define IAC_ICR2_IACF83_Pos           (19U)
+#define IAC_ICR2_IACF83_Msk           (0x1UL << IAC_ICR2_IACF83_Pos)              /*!< 0x00080000 */
+#define IAC_ICR2_IACF83               IAC_ICR2_IACF83_Msk
+#define IAC_ICR2_IACF84_Pos           (20U)
+#define IAC_ICR2_IACF84_Msk           (0x1UL << IAC_ICR2_IACF84_Pos)              /*!< 0x00100000 */
+#define IAC_ICR2_IACF84               IAC_ICR2_IACF84_Msk
+#define IAC_ICR2_IACF86_Pos           (22U)
+#define IAC_ICR2_IACF86_Msk           (0x1UL << IAC_ICR2_IACF86_Pos)              /*!< 0x00400000 */
+#define IAC_ICR2_IACF86               IAC_ICR2_IACF86_Msk
+#define IAC_ICR2_IACF87_Pos           (23U)
+#define IAC_ICR2_IACF87_Msk           (0x1UL << IAC_ICR2_IACF87_Pos)              /*!< 0x00800000 */
+#define IAC_ICR2_IACF87               IAC_ICR2_IACF87_Msk
+#define IAC_ICR2_IACF88_Pos           (24U)
+#define IAC_ICR2_IACF88_Msk           (0x1UL << IAC_ICR2_IACF88_Pos)              /*!< 0x01000000 */
+#define IAC_ICR2_IACF88               IAC_ICR2_IACF88_Msk
+#define IAC_ICR2_IACF89_Pos           (25U)
+#define IAC_ICR2_IACF89_Msk           (0x1UL << IAC_ICR2_IACF89_Pos)              /*!< 0x02000000 */
+#define IAC_ICR2_IACF89               IAC_ICR2_IACF89_Msk
+#define IAC_ICR2_IACF90_Pos           (26U)
+#define IAC_ICR2_IACF90_Msk           (0x1UL << IAC_ICR2_IACF90_Pos)              /*!< 0x04000000 */
+#define IAC_ICR2_IACF90               IAC_ICR2_IACF90_Msk
+#define IAC_ICR2_IACF92_Pos           (28U)
+#define IAC_ICR2_IACF92_Msk           (0x1UL << IAC_ICR2_IACF92_Pos)              /*!< 0x10000000 */
+#define IAC_ICR2_IACF92               IAC_ICR2_IACF92_Msk
+#define IAC_ICR2_IACF93_Pos           (29U)
+#define IAC_ICR2_IACF93_Msk           (0x1UL << IAC_ICR2_IACF93_Pos)              /*!< 0x20000000 */
+#define IAC_ICR2_IACF93               IAC_ICR2_IACF93_Msk
+#define IAC_ICR2_IACF94_Pos           (30U)
+#define IAC_ICR2_IACF94_Msk           (0x1UL << IAC_ICR2_IACF94_Pos)              /*!< 0x40000000 */
+#define IAC_ICR2_IACF94               IAC_ICR2_IACF94_Msk
+#define IAC_ICR2_IACF95_Pos           (31U)
+#define IAC_ICR2_IACF95_Msk           (0x1UL << IAC_ICR2_IACF95_Pos)              /*!< 0x80000000 */
+#define IAC_ICR2_IACF95               IAC_ICR2_IACF95_Msk
+
+/*******************  Bits definition for IAC_ICR3 register *******************/
+#define IAC_ICR3_IACF96_Pos           (0U)
+#define IAC_ICR3_IACF96_Msk           (0x1UL << IAC_ICR3_IACF96_Pos)              /*!< 0x00000001 */
+#define IAC_ICR3_IACF96               IAC_ICR3_IACF96_Msk
+#define IAC_ICR3_IACF97_Pos           (1U)
+#define IAC_ICR3_IACF97_Msk           (0x1UL << IAC_ICR3_IACF97_Pos)              /*!< 0x00000002 */
+#define IAC_ICR3_IACF97               IAC_ICR3_IACF97_Msk
+#define IAC_ICR3_IACF98_Pos           (2U)
+#define IAC_ICR3_IACF98_Msk           (0x1UL << IAC_ICR3_IACF98_Pos)              /*!< 0x00000004 */
+#define IAC_ICR3_IACF98               IAC_ICR3_IACF98_Msk
+#define IAC_ICR3_IACF99_Pos           (3U)
+#define IAC_ICR3_IACF99_Msk           (0x1UL << IAC_ICR3_IACF99_Pos)              /*!< 0x00000008 */
+#define IAC_ICR3_IACF99               IAC_ICR3_IACF99_Msk
+#define IAC_ICR3_IACF100_Pos          (4U)
+#define IAC_ICR3_IACF100_Msk          (0x1UL << IAC_ICR3_IACF100_Pos)             /*!< 0x00000010 */
+#define IAC_ICR3_IACF100              IAC_ICR3_IACF100_Msk
+#define IAC_ICR3_IACF101_Pos          (5U)
+#define IAC_ICR3_IACF101_Msk          (0x1UL << IAC_ICR3_IACF101_Pos)             /*!< 0x00000020 */
+#define IAC_ICR3_IACF101              IAC_ICR3_IACF101_Msk
+#define IAC_ICR3_IACF102_Pos          (6U)
+#define IAC_ICR3_IACF102_Msk          (0x1UL << IAC_ICR3_IACF102_Pos)             /*!< 0x00000040 */
+#define IAC_ICR3_IACF102              IAC_ICR3_IACF102_Msk
+#define IAC_ICR3_IACF103_Pos          (7U)
+#define IAC_ICR3_IACF103_Msk          (0x1UL << IAC_ICR3_IACF103_Pos)             /*!< 0x00000080 */
+#define IAC_ICR3_IACF103              IAC_ICR3_IACF103_Msk
+#define IAC_ICR3_IACF104_Pos          (8U)
+#define IAC_ICR3_IACF104_Msk          (0x1UL << IAC_ICR3_IACF104_Pos)             /*!< 0x00000100 */
+#define IAC_ICR3_IACF104              IAC_ICR3_IACF104_Msk
+#define IAC_ICR3_IACF106_Pos          (10U)
+#define IAC_ICR3_IACF106_Msk          (0x1UL << IAC_ICR3_IACF106_Pos)             /*!< 0x00000400 */
+#define IAC_ICR3_IACF106              IAC_ICR3_IACF106_Msk
+
+/*******************  Bits definition for IAC_ICR4 register *******************/
+#define IAC_ICR4_IACF128_Pos          (0U)
+#define IAC_ICR4_IACF128_Msk          (0x1UL << IAC_ICR4_IACF128_Pos)             /*!< 0x00000001 */
+#define IAC_ICR4_IACF128              IAC_ICR4_IACF128_Msk
+#define IAC_ICR4_IACF129_Pos          (1U)
+#define IAC_ICR4_IACF129_Msk          (0x1UL << IAC_ICR4_IACF129_Pos)             /*!< 0x00000002 */
+#define IAC_ICR4_IACF129              IAC_ICR4_IACF129_Msk
+#define IAC_ICR4_IACF130_Pos          (2U)
+#define IAC_ICR4_IACF130_Msk          (0x1UL << IAC_ICR4_IACF130_Pos)             /*!< 0x00000004 */
+#define IAC_ICR4_IACF130              IAC_ICR4_IACF130_Msk
+#define IAC_ICR4_IACF131_Pos          (3U)
+#define IAC_ICR4_IACF131_Msk          (0x1UL << IAC_ICR4_IACF131_Pos)             /*!< 0x00000008 */
+#define IAC_ICR4_IACF131              IAC_ICR4_IACF131_Msk
+#define IAC_ICR4_IACF133_Pos          (5U)
+#define IAC_ICR4_IACF133_Msk          (0x1UL << IAC_ICR4_IACF133_Pos)             /*!< 0x00000020 */
+#define IAC_ICR4_IACF133              IAC_ICR4_IACF133_Msk
+#define IAC_ICR4_IACF134_Pos          (6U)
+#define IAC_ICR4_IACF134_Msk          (0x1UL << IAC_ICR4_IACF134_Pos)             /*!< 0x00000040 */
+#define IAC_ICR4_IACF134              IAC_ICR4_IACF134_Msk
+#define IAC_ICR4_IACF135_Pos          (7U)
+#define IAC_ICR4_IACF135_Msk          (0x1UL << IAC_ICR4_IACF135_Pos)             /*!< 0x00000080 */
+#define IAC_ICR4_IACF135              IAC_ICR4_IACF135_Msk
+#define IAC_ICR4_IACF136_Pos          (8U)
+#define IAC_ICR4_IACF136_Msk          (0x1UL << IAC_ICR4_IACF136_Pos)             /*!< 0x00000100 */
+#define IAC_ICR4_IACF136              IAC_ICR4_IACF136_Msk
+#define IAC_ICR4_IACF137_Pos          (9U)
+#define IAC_ICR4_IACF137_Msk          (0x1UL << IAC_ICR4_IACF137_Pos)             /*!< 0x00000200 */
+#define IAC_ICR4_IACF137              IAC_ICR4_IACF137_Msk
+#define IAC_ICR4_IACF138_Pos          (10U)
+#define IAC_ICR4_IACF138_Msk          (0x1UL << IAC_ICR4_IACF138_Pos)             /*!< 0x00000400 */
+#define IAC_ICR4_IACF138              IAC_ICR4_IACF138_Msk
+#define IAC_ICR4_IACF139_Pos          (11U)
+#define IAC_ICR4_IACF139_Msk          (0x1UL << IAC_ICR4_IACF139_Pos)             /*!< 0x00000800 */
+#define IAC_ICR4_IACF139              IAC_ICR4_IACF139_Msk
+#define IAC_ICR4_IACF140_Pos          (12U)
+#define IAC_ICR4_IACF140_Msk          (0x1UL << IAC_ICR4_IACF140_Pos)             /*!< 0x00001000 */
+#define IAC_ICR4_IACF140              IAC_ICR4_IACF140_Msk
+#define IAC_ICR4_IACF141_Pos          (13U)
+#define IAC_ICR4_IACF141_Msk          (0x1UL << IAC_ICR4_IACF141_Pos)             /*!< 0x00002000 */
+#define IAC_ICR4_IACF141              IAC_ICR4_IACF141_Msk
+#define IAC_ICR4_IACF142_Pos          (14U)
+#define IAC_ICR4_IACF142_Msk          (0x1UL << IAC_ICR4_IACF142_Pos)             /*!< 0x00004000 */
+#define IAC_ICR4_IACF142              IAC_ICR4_IACF142_Msk
+#define IAC_ICR4_IACF143_Pos          (15U)
+#define IAC_ICR4_IACF143_Msk          (0x1UL << IAC_ICR4_IACF143_Pos)             /*!< 0x00008000 */
+#define IAC_ICR4_IACF143              IAC_ICR4_IACF143_Msk
+#define IAC_ICR4_IACF144_Pos          (16U)
+#define IAC_ICR4_IACF144_Msk          (0x1UL << IAC_ICR4_IACF144_Pos)             /*!< 0x00010000 */
+#define IAC_ICR4_IACF144              IAC_ICR4_IACF144_Msk
+#define IAC_ICR4_IACF145_Pos          (17U)
+#define IAC_ICR4_IACF145_Msk          (0x1UL << IAC_ICR4_IACF145_Pos)             /*!< 0x00020000 */
+#define IAC_ICR4_IACF145              IAC_ICR4_IACF145_Msk
+#define IAC_ICR4_IACF146_Pos          (18U)
+#define IAC_ICR4_IACF146_Msk          (0x1UL << IAC_ICR4_IACF146_Pos)             /*!< 0x00040000 */
+#define IAC_ICR4_IACF146              IAC_ICR4_IACF146_Msk
+#define IAC_ICR4_IACF147_Pos          (19U)
+#define IAC_ICR4_IACF147_Msk          (0x1UL << IAC_ICR4_IACF147_Pos)             /*!< 0x00080000 */
+#define IAC_ICR4_IACF147              IAC_ICR4_IACF147_Msk
+#define IAC_ICR4_IACF149_Pos          (21U)
+#define IAC_ICR4_IACF149_Msk          (0x1UL << IAC_ICR4_IACF149_Pos)             /*!< 0x00200000 */
+#define IAC_ICR4_IACF149              IAC_ICR4_IACF149_Msk
+#define IAC_ICR4_IACF150_Pos          (22U)
+#define IAC_ICR4_IACF150_Msk          (0x1UL << IAC_ICR4_IACF150_Pos)             /*!< 0x00400000 */
+#define IAC_ICR4_IACF150              IAC_ICR4_IACF150_Msk
+#define IAC_ICR4_IACF151_Pos          (23U)
+#define IAC_ICR4_IACF151_Msk          (0x1UL << IAC_ICR4_IACF151_Pos)             /*!< 0x00800000 */
+#define IAC_ICR4_IACF151              IAC_ICR4_IACF151_Msk
+#define IAC_ICR4_IACF152_Pos          (24U)
+#define IAC_ICR4_IACF152_Msk          (0x1UL << IAC_ICR4_IACF152_Pos)             /*!< 0x01000000 */
+#define IAC_ICR4_IACF152              IAC_ICR4_IACF152_Msk
+#define IAC_ICR4_IACF153_Pos          (25U)
+#define IAC_ICR4_IACF153_Msk          (0x1UL << IAC_ICR4_IACF153_Pos)             /*!< 0x02000000 */
+#define IAC_ICR4_IACF153              IAC_ICR4_IACF153_Msk
+#define IAC_ICR4_IACF155_Pos          (27U)
+#define IAC_ICR4_IACF155_Msk          (0x1UL << IAC_ICR4_IACF155_Pos)             /*!< 0x08000000 */
+#define IAC_ICR4_IACF155              IAC_ICR4_IACF155_Msk
+#define IAC_ICR4_IACF156_Pos          (28U)
+#define IAC_ICR4_IACF156_Msk          (0x1UL << IAC_ICR4_IACF156_Pos)             /*!< 0x10000000 */
+#define IAC_ICR4_IACF156              IAC_ICR4_IACF156_Msk
+#define IAC_ICR4_IACF157_Pos          (29U)
+#define IAC_ICR4_IACF157_Msk          (0x1UL << IAC_ICR4_IACF157_Pos)             /*!< 0x20000000 */
+#define IAC_ICR4_IACF157              IAC_ICR4_IACF157_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 ICACHE                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for ICACHE_CR register  *******************/
+#define ICACHE_CR_EN_Pos               (0U)
+#define ICACHE_CR_EN_Msk               (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
+#define ICACHE_CR_EN                   ICACHE_CR_EN_Msk                        /*!< Enable */
+#define ICACHE_CR_CACHEINV_Pos         (1U)
+#define ICACHE_CR_CACHEINV_Msk         (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
+#define ICACHE_CR_CACHEINV             ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
+#define ICACHE_CR_WAYSEL_Pos           (2U)
+#define ICACHE_CR_WAYSEL_Msk           (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
+#define ICACHE_CR_WAYSEL               ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
+#define ICACHE_CR_HITMEN_Pos           (16U)
+#define ICACHE_CR_HITMEN_Msk           (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
+#define ICACHE_CR_HITMEN               ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
+#define ICACHE_CR_MISSMEN_Pos          (17U)
+#define ICACHE_CR_MISSMEN_Msk          (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
+#define ICACHE_CR_MISSMEN              ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
+#define ICACHE_CR_HITMRST_Pos          (18U)
+#define ICACHE_CR_HITMRST_Msk          (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
+#define ICACHE_CR_HITMRST              ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
+#define ICACHE_CR_MISSMRST_Pos         (19U)
+#define ICACHE_CR_MISSMRST_Msk         (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
+#define ICACHE_CR_MISSMRST             ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
+
+/******************  Bit definition for ICACHE_SR register  *******************/
+#define ICACHE_SR_BUSYF_Pos            (0U)
+#define ICACHE_SR_BUSYF_Msk            (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
+#define ICACHE_SR_BUSYF                ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
+#define ICACHE_SR_BSYENDF_Pos          (1U)
+#define ICACHE_SR_BSYENDF_Msk          (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
+#define ICACHE_SR_BSYENDF              ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
+#define ICACHE_SR_ERRF_Pos             (2U)
+#define ICACHE_SR_ERRF_Msk             (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
+#define ICACHE_SR_ERRF                 ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
+
+/******************  Bit definition for ICACHE_IER register  ******************/
+#define ICACHE_IER_BSYENDIE_Pos        (1U)
+#define ICACHE_IER_BSYENDIE_Msk        (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
+#define ICACHE_IER_BSYENDIE            ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
+#define ICACHE_IER_ERRIE_Pos           (2U)
+#define ICACHE_IER_ERRIE_Msk           (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
+#define ICACHE_IER_ERRIE               ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
+
+/******************  Bit definition for ICACHE_FCR register  ******************/
+#define ICACHE_FCR_CBSYENDF_Pos        (1U)
+#define ICACHE_FCR_CBSYENDF_Msk        (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
+#define ICACHE_FCR_CBSYENDF            ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
+#define ICACHE_FCR_CERRF_Pos           (2U)
+#define ICACHE_FCR_CERRF_Msk           (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
+#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
+
+/******************  Bit definition for ICACHE_HMONR register  ****************/
+#define ICACHE_HMONR_HITMON_Pos         (0U)
+#define ICACHE_HMONR_HITMON_Msk         (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)/*!< 0xFFFFFFFF */
+#define ICACHE_HMONR_HITMON             ICACHE_HMONR_HITMON_Msk                /*!< Cache hit monitor register */
+
+/******************  Bit definition for ICACHE_MMONR register  ****************/
+#define ICACHE_MMONR_MISSMON_Pos        (0U)
+#define ICACHE_MMONR_MISSMON_Msk        (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
+#define ICACHE_MMONR_MISSMON            ICACHE_MMONR_MISSMON_Msk               /*!< Cache miss monitor register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent Watchdog (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos             (0U)
+#define IWDG_KR_KEY_Msk             (0xFFFFUL << IWDG_KR_KEY_Pos)          /*!< 0x0000FFFF */
+#define IWDG_KR_KEY                 IWDG_KR_KEY_Msk                       /*!< Key value (write only, read 0x0000) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos              (0U)
+#define IWDG_PR_PR_Msk              (0xFUL << IWDG_PR_PR_Pos)              /*!< 0x0000000F */
+#define IWDG_PR_PR                  IWDG_PR_PR_Msk                        /*!< Prescaler divider */
+#define IWDG_PR_PR_0                (0x1UL << IWDG_PR_PR_Pos)              /*!< 0x00000001 */
+#define IWDG_PR_PR_1                (0x2UL << IWDG_PR_PR_Pos)              /*!< 0x00000002 */
+#define IWDG_PR_PR_2                (0x4UL << IWDG_PR_PR_Pos)              /*!< 0x00000004 */
+#define IWDG_PR_PR_3                (0x8UL << IWDG_PR_PR_Pos)              /*!< 0x00000008 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos             (0U)
+#define IWDG_RLR_RL_Msk             (0xFFFUL << IWDG_RLR_RL_Pos)           /*!< 0x00000FFF */
+#define IWDG_RLR_RL                 IWDG_RLR_RL_Msk                       /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos             (0U)
+#define IWDG_SR_PVU_Msk             (0x1UL << IWDG_SR_PVU_Pos)             /*!< 0x00000001 */
+#define IWDG_SR_PVU                 IWDG_SR_PVU_Msk                       /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos             (1U)
+#define IWDG_SR_RVU_Msk             (0x1UL << IWDG_SR_RVU_Pos)             /*!< 0x00000002 */
+#define IWDG_SR_RVU                 IWDG_SR_RVU_Msk                       /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos             (2U)
+#define IWDG_SR_WVU_Msk             (0x1UL << IWDG_SR_WVU_Pos)             /*!< 0x00000004 */
+#define IWDG_SR_WVU                 IWDG_SR_WVU_Msk                       /*!< Watchdog counter window value update */
+#define IWDG_SR_EWU_Pos             (3U)
+#define IWDG_SR_EWU_Msk             (0x1UL << IWDG_SR_EWU_Pos)             /*!< 0x00000008 */
+#define IWDG_SR_EWU                 IWDG_SR_EWU_Msk                       /*!< Watchdog interrupt comparator value update */
+#define IWDG_SR_ONF_Pos             (8U)
+#define IWDG_SR_ONF_Msk             (0x1UL << IWDG_SR_ONF_Pos)             /*!< 0x00000100 */
+#define IWDG_SR_ONF                 IWDG_SR_ONF_Msk                       /*!< Watchdog Enable status bit */
+#define IWDG_SR_EWIF_Pos            (15U)
+#define IWDG_SR_EWIF_Msk            (0x1UL << IWDG_SR_EWIF_Pos)            /*!< 0x00008000 */
+#define IWDG_SR_EWIF                IWDG_SR_EWIF_Msk                      /*!< Watchdog Early Interrupt flag */
+
+/******************  Bit definition for IWDG_WINR register  *******************/
+#define IWDG_WINR_WIN_Pos           (0U)
+#define IWDG_WINR_WIN_Msk           (0xFFFUL << IWDG_WINR_WIN_Pos)         /*!< 0x00000FFF */
+#define IWDG_WINR_WIN               IWDG_WINR_WIN_Msk                     /*!< Watchdog counter window value */
+
+/******************  Bit definition for IWDG_EWCR register  *******************/
+#define IWDG_EWCR_EWIT_Pos          (0U)
+#define IWDG_EWCR_EWIT_Msk          (0xFFFUL << IWDG_EWCR_EWIT_Pos)        /*!< 0x00000FFF */
+#define IWDG_EWCR_EWIT              IWDG_EWCR_EWIT_Msk                    /*!< Watchdog counter window value */
+#define IWDG_EWCR_EWIE_Pos          (15U)
+#define IWDG_EWCR_EWIE_Msk          (0x1UL << IWDG_EWCR_EWIE_Pos)          /*!< 0x00008000 */
+#define IWDG_EWCR_EWIE              IWDG_EWCR_EWIE_Msk                    /*!< Watchdog early interrupt enable */
+
+/*******************  Bit definition for IWDG_ICR register  *******************/
+#define IWDG_ICR_EWIC_Pos           (15U)
+#define IWDG_ICR_EWIC_Msk           (0x1UL << IWDG_ICR_EWIC_Pos)           /*!< 0x00008000 */
+#define IWDG_ICR_EWIC               IWDG_ICR_EWIC_Msk                     /*!< Watchdog early interrupt acknowledge */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)         /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                    /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                       /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                       /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk               /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)            /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                       /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                      /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                    /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)    /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                     /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                    /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                      /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                      /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)              /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                         /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)             /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                        /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)            /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                       /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)             /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                        /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)            /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                       /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)             /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                        /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)             /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                        /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IDMAEN_Pos              (11U)
+#define JPEG_CR_IDMAEN_Msk              (0x1UL << JPEG_CR_IDMAEN_Pos)            /*!< 0x00000800 */
+#define JPEG_CR_IDMAEN                  JPEG_CR_IDMAEN_Msk                       /*!<Input DMA enable */
+#define JPEG_CR_ODMAEN_Pos              (12U)
+#define JPEG_CR_ODMAEN_Msk              (0x1UL << JPEG_CR_ODMAEN_Pos)            /*!< 0x00001000 */
+#define JPEG_CR_ODMAEN                  JPEG_CR_ODMAEN_Msk                       /*!<Output DMA enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)               /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                          /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)               /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                          /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)              /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                         /*!<Input FIFO is not full and is below its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)             /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                        /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)              /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                         /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)             /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                        /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)              /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                         /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)              /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                         /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)               /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                          /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (5U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                       /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (6U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                       /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)    /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                      /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)   /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                     /*!<Data Output FIFO */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                            */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CC1IF_Pos         (0U)
+#define LPTIM_ISR_CC1IF_Msk         (0x1UL << LPTIM_ISR_CC1IF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ISR_CC1IF             LPTIM_ISR_CC1IF_Msk                        /*!< Capture/Compare 1 interrupt flag */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMP1OK_Pos        (3U)
+#define LPTIM_ISR_CMP1OK_Msk        (0x1UL << LPTIM_ISR_CMP1OK_Pos)            /*!< 0x00000008 */
+#define LPTIM_ISR_CMP1OK            LPTIM_ISR_CMP1OK_Msk                       /*!< Compare register 1 update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+#define LPTIM_ISR_UE_Pos            (7U)
+#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
+#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
+#define LPTIM_ISR_REPOK_Pos         (8U)
+#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
+#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
+#define LPTIM_ISR_CC2IF_Pos         (9U)
+#define LPTIM_ISR_CC2IF_Msk         (0x1UL << LPTIM_ISR_CC2IF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ISR_CC2IF             LPTIM_ISR_CC2IF_Msk                        /*!< Capture/Compare 2 interrupt flag */
+#define LPTIM_ISR_CC1OF_Pos         (12U)
+#define LPTIM_ISR_CC1OF_Msk         (0x1UL << LPTIM_ISR_CC1OF_Pos)             /*!< 0x00001000 */
+#define LPTIM_ISR_CC1OF             LPTIM_ISR_CC1OF_Msk                        /*!< Capture/Compare 1 over-capture flag */
+#define LPTIM_ISR_CC2OF_Pos         (13U)
+#define LPTIM_ISR_CC2OF_Msk         (0x1UL << LPTIM_ISR_CC2OF_Pos)             /*!< 0x00002000 */
+#define LPTIM_ISR_CC2OF             LPTIM_ISR_CC2OF_Msk                        /*!< Capture/Compare 2 over-capture flag */
+#define LPTIM_ISR_CMP2OK_Pos        (19U)
+#define LPTIM_ISR_CMP2OK_Msk        (0x1UL << LPTIM_ISR_CMP2OK_Pos)            /*!< 0x00080000 */
+#define LPTIM_ISR_CMP2OK            LPTIM_ISR_CMP2OK_Msk                       /*!< Compare register 2 update OK */
+#define LPTIM_ISR_DIEROK_Pos        (24U)
+#define LPTIM_ISR_DIEROK_Msk        (0x1UL << LPTIM_ISR_DIEROK_Pos)            /*!< 0x01000000 */
+#define LPTIM_ISR_DIEROK            LPTIM_ISR_DIEROK_Msk                       /*!< Interrupt enable register update OK */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CC1CF_Pos         (0U)
+#define LPTIM_ICR_CC1CF_Msk         (0x1UL << LPTIM_ICR_CC1CF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CC1CF              LPTIM_ICR_CC1CF_Msk                       /*!< Capture/Compare 1 clear flag  */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMP1OKCF_Pos      (3U)
+#define LPTIM_ICR_CMP1OKCF_Msk      (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)          /*!< 0x00000008 */
+#define LPTIM_ICR_CMP1OKCF          LPTIM_ICR_CMP1OKCF_Msk                     /*!< Compare register 1 update OK clear flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+#define LPTIM_ICR_UECF_Pos          (7U)
+#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
+#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
+#define LPTIM_ICR_REPOKCF_Pos       (8U)
+#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
+#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
+#define LPTIM_ICR_CC2CF_Pos         (9U)
+#define LPTIM_ICR_CC2CF_Msk         (0x1UL << LPTIM_ICR_CC2CF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ICR_CC2CF             LPTIM_ICR_CC2CF_Msk                        /*!< Capture/Compare 2 clear flag  */
+#define LPTIM_ICR_CC1OCF_Pos        (12U)
+#define LPTIM_ICR_CC1OCF_Msk        (0x1UL << LPTIM_ICR_CC1OCF_Pos)            /*!< 0x00001000 */
+#define LPTIM_ICR_CC1OCF            LPTIM_ICR_CC1OCF_Msk                       /*!< Capture/Compare 1 over-capture clear flag */
+#define LPTIM_ICR_CC2OCF_Pos        (13U)
+#define LPTIM_ICR_CC2OCF_Msk        (0x1UL << LPTIM_ICR_CC2OCF_Pos)            /*!< 0x00002000 */
+#define LPTIM_ICR_CC2OCF            LPTIM_ICR_CC2OCF_Msk                       /*!< Capture/Compare 2 over-capture clear flag */
+#define LPTIM_ICR_CMP2OKCF_Pos      (19U)
+#define LPTIM_ICR_CMP2OKCF_Msk      (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)          /*!< 0x00080000 */
+#define LPTIM_ICR_CMP2OKCF          LPTIM_ICR_CMP2OKCF_Msk                     /*!< Compare register 2 update OK clear flag */
+#define LPTIM_ICR_DIEROKCF_Pos      (24U)
+#define LPTIM_ICR_DIEROKCF_Msk      (0x1UL << LPTIM_ICR_DIEROKCF_Pos)          /*!< 0x01000000 */
+#define LPTIM_ICR_DIEROKCF          LPTIM_ICR_DIEROKCF_Msk                     /*!< Interrupt enable register update OK clear flag */
+
+/******************  Bit definition for LPTIM_DIER register *******************/
+#define LPTIM_DIER_CC1IE_Pos        (0U)
+#define LPTIM_DIER_CC1IE_Msk        (0x1UL << LPTIM_DIER_CC1IE_Pos)            /*!< 0x00000001 */
+#define LPTIM_DIER_CC1IE            LPTIM_DIER_CC1IE_Msk                       /*!< Compare/Compare interrupt enable */
+#define LPTIM_DIER_ARRMIE_Pos        (1U)
+#define LPTIM_DIER_ARRMIE_Msk       (0x1UL << LPTIM_DIER_ARRMIE_Pos)           /*!< 0x00000002 */
+#define LPTIM_DIER_ARRMIE           LPTIM_DIER_ARRMIE_Msk                      /*!< Autoreload match Interrupt Enable */
+#define LPTIM_DIER_EXTTRIGIE_Pos    (2U)
+#define LPTIM_DIER_EXTTRIGIE_Msk    (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)        /*!< 0x00000004 */
+#define LPTIM_DIER_EXTTRIGIE        LPTIM_DIER_EXTTRIGIE_Msk                   /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_DIER_CMP1OKIE_Pos     (3U)
+#define LPTIM_DIER_CMP1OKIE_Msk     (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)         /*!< 0x00000008 */
+#define LPTIM_DIER_CMP1OKIE         LPTIM_DIER_CMP1OKIE_Msk                    /*!< Compare register 1 update OK interrupt enable */
+#define LPTIM_DIER_ARROKIE_Pos      (4U)
+#define LPTIM_DIER_ARROKIE_Msk      (0x1UL << LPTIM_DIER_ARROKIE_Pos)          /*!< 0x00000010 */
+#define LPTIM_DIER_ARROKIE          LPTIM_DIER_ARROKIE_Msk                     /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_DIER_UPIE_Pos         (5U)
+#define LPTIM_DIER_UPIE_Msk         (0x1UL << LPTIM_DIER_UPIE_Pos)             /*!< 0x00000020 */
+#define LPTIM_DIER_UPIE             LPTIM_DIER_UPIE_Msk                        /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_DIER_DOWNIE_Pos       (6U)
+#define LPTIM_DIER_DOWNIE_Msk       (0x1UL << LPTIM_DIER_DOWNIE_Pos)           /*!< 0x00000040 */
+#define LPTIM_DIER_DOWNIE           LPTIM_DIER_DOWNIE_Msk                      /*!< Counter direction change up to down Interrupt Enable */
+#define LPTIM_DIER_UEIE_Pos         (7U)
+#define LPTIM_DIER_UEIE_Msk         (0x1UL << LPTIM_DIER_UEIE_Pos)             /*!< 0x00000080 */
+#define LPTIM_DIER_UEIE             LPTIM_DIER_UEIE_Msk                        /*!< Update event Interrupt Enable */
+#define LPTIM_DIER_REPOKIE_Pos      (8U)
+#define LPTIM_DIER_REPOKIE_Msk      (0x1UL << LPTIM_DIER_REPOKIE_Pos)          /*!< 0x00000100 */
+#define LPTIM_DIER_REPOKIE          LPTIM_DIER_REPOKIE_Msk                     /*!< Repetition register update OK Interrupt Enable */
+#define LPTIM_DIER_CC2IE_Pos        (9U)
+#define LPTIM_DIER_CC2IE_Msk        (0x1UL << LPTIM_DIER_CC2IE_Pos)            /*!< 0x00000200 */
+#define LPTIM_DIER_CC2IE            LPTIM_DIER_CC2IE_Msk                       /*!< Capture/Compare 2 interrupt interrupt enable */
+#define LPTIM_DIER_CC1OIE_Pos       (12U)
+#define LPTIM_DIER_CC1OIE_Msk       (0x1UL << LPTIM_DIER_CC1OIE_Pos)           /*!< 0x00001000 */
+#define LPTIM_DIER_CC1OIE           LPTIM_DIER_CC1OIE_Msk                      /*!< Capture/Compare 1 over-capture interrupt enable */
+#define LPTIM_DIER_CC2OIE_Pos       (13U)
+#define LPTIM_DIER_CC2OIE_Msk       (0x1UL << LPTIM_DIER_CC2OIE_Pos)           /*!< 0x00002000 */
+#define LPTIM_DIER_CC2OIE           LPTIM_DIER_CC2OIE_Msk                      /*!< Capture/Compare 2 over-capture interrupt enable */
+#define LPTIM_DIER_CC1DE_Pos        (16U)
+#define LPTIM_DIER_CC1DE_Msk        (0x1UL << LPTIM_DIER_CC1DE_Pos)            /*!< 0x00010000 */
+#define LPTIM_DIER_CC1DE            LPTIM_DIER_CC1DE_Msk                       /*!< Capture/Compare 1 DMA request enable */
+#define LPTIM_DIER_CMP2OKIE_Pos     (19U)
+#define LPTIM_DIER_CMP2OKIE_Msk     (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)         /*!< 0x00080000 */
+#define LPTIM_DIER_CMP2OKIE         LPTIM_DIER_CMP2OKIE_Msk                    /*!< Compare register 2 update OK interrupt enable */
+#define LPTIM_DIER_UEDE_Pos         (23U)
+#define LPTIM_DIER_UEDE_Msk         (0x1UL << LPTIM_DIER_UEDE_Pos)             /*!< 0x00800000 */
+#define LPTIM_DIER_UEDE             LPTIM_DIER_UEDE_Msk                        /*!< Update event DMA request enable */
+#define LPTIM_DIER_CC2DE_Pos        (25U)
+#define LPTIM_DIER_CC2DE_Msk        (0x1UL << LPTIM_DIER_CC2DE_Pos)            /*!< 0x02000000 */
+#define LPTIM_DIER_CC2DE            LPTIM_DIER_CC2DE_Msk                       /*!< Capture/Compare 2 DMA request enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CCR1_CCR1_Pos           (0U)
+#define LPTIM_CCR1_CCR1_Msk           (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)        /*!< 0x0000FFFF */
+#define LPTIM_CCR1_CCR1               LPTIM_CCR1_CCR1_Msk                      /*!< Compare register 1 */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000020 */
+#define LPTIM_CFGR2_IC1SEL_Pos      (16U)
+#define LPTIM_CFGR2_IC1SEL_Msk      (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IC1SEL          LPTIM_CFGR2_IC1SEL_Msk                     /*!< IC1SEL[17:16] bits */
+#define LPTIM_CFGR2_IC1SEL_0        (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CFGR2_IC1SEL_1        (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00020000 */
+#define LPTIM_CFGR2_IC2SEL_Pos      (20U)
+#define LPTIM_CFGR2_IC2SEL_Msk      (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IC2SEL          LPTIM_CFGR2_IC2SEL_Msk                     /*!< IC2SEL[21:20] bits */
+#define LPTIM_CFGR2_IC2SEL_0        (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00100000 */
+#define LPTIM_CFGR2_IC2SEL_1        (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00200000 */
+
+/******************  Bit definition for LPTIM_RCR register  *******************/
+#define LPTIM_RCR_REP_Pos           (0U)
+#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
+#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!< Repetition Counter Value */
+
+/*****************  Bit definition for LPTIM_CCMR1 register  ******************/
+#define LPTIM_CCMR1_CC1SEL_Pos      (0U)
+#define LPTIM_CCMR1_CC1SEL_Msk      (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CCMR1_CC1SEL          LPTIM_CCMR1_CC1SEL_Msk                     /*!< Capture/Compare 1 selection */
+#define LPTIM_CCMR1_CC1E_Pos        (1U)
+#define LPTIM_CCMR1_CC1E_Msk        (0x1UL << LPTIM_CCMR1_CC1E_Pos)            /*!< 0x00000002 */
+#define LPTIM_CCMR1_CC1E            LPTIM_CCMR1_CC1E_Msk                       /*!< Capture/Compare 1 output enable */
+#define LPTIM_CCMR1_CC1P_Pos        (2U)
+#define LPTIM_CCMR1_CC1P_Msk        (0x3UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x0000000C */
+#define LPTIM_CCMR1_CC1P            LPTIM_CCMR1_CC1P_Msk                       /*!< Capture/Compare 1 output polarity */
+#define LPTIM_CCMR1_CC1P_0          (0x1UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000004 */
+#define LPTIM_CCMR1_CC1P_1          (0x2UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000008 */
+#define LPTIM_CCMR1_IC1PSC_Pos      (8U)
+#define LPTIM_CCMR1_IC1PSC_Msk      (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000300 */
+#define LPTIM_CCMR1_IC1PSC          LPTIM_CCMR1_IC1PSC_Msk                     /*!< Input capture 1 prescaler */
+#define LPTIM_CCMR1_IC1PSC_0        (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000100 */
+#define LPTIM_CCMR1_IC1PSC_1        (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000200 */
+#define LPTIM_CCMR1_IC1F_Pos        (12U)
+#define LPTIM_CCMR1_IC1F_Msk        (0x3UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00003000 */
+#define LPTIM_CCMR1_IC1F            LPTIM_CCMR1_IC1F_Msk                       /*!< Input capture 1 filter */
+#define LPTIM_CCMR1_IC1F_0          (0x1UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00001000 */
+#define LPTIM_CCMR1_IC1F_1          (0x2UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00002000 */
+#define LPTIM_CCMR1_CC2SEL_Pos      (16U)
+#define LPTIM_CCMR1_CC2SEL_Msk      (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CCMR1_CC2SEL          LPTIM_CCMR1_CC2SEL_Msk                     /*!< Capture/Compare 2 selection */
+#define LPTIM_CCMR1_CC2E_Pos        (17U)
+#define LPTIM_CCMR1_CC2E_Msk        (0x1UL << LPTIM_CCMR1_CC2E_Pos)            /*!< 0x00020000 */
+#define LPTIM_CCMR1_CC2E            LPTIM_CCMR1_CC2E_Msk                       /*!< Capture/Compare 2 output enable */
+#define LPTIM_CCMR1_CC2P_Pos        (18U)
+#define LPTIM_CCMR1_CC2P_Msk        (0x3UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x000C0000 */
+#define LPTIM_CCMR1_CC2P            LPTIM_CCMR1_CC2P_Msk                       /*!< Capture/Compare 2 output polarity */
+#define LPTIM_CCMR1_CC2P_0          (0x1UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00040000 */
+#define LPTIM_CCMR1_CC2P_1          (0x2UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00080000 */
+#define LPTIM_CCMR1_IC2PSC_Pos      (24U)
+#define LPTIM_CCMR1_IC2PSC_Msk      (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x03000000 */
+#define LPTIM_CCMR1_IC2PSC          LPTIM_CCMR1_IC2PSC_Msk                     /*!< Input capture 2 prescaler */
+#define LPTIM_CCMR1_IC2PSC_0        (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x01000000 */
+#define LPTIM_CCMR1_IC2PSC_1        (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x02000000 */
+#define LPTIM_CCMR1_IC2F_Pos        (28U)
+#define LPTIM_CCMR1_IC2F_Msk        (0x3UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x30000000 */
+#define LPTIM_CCMR1_IC2F            LPTIM_CCMR1_IC2F_Msk                       /*!< Input capture 2 filter */
+#define LPTIM_CCMR1_IC2F_0          (0x1UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x10000000 */
+#define LPTIM_CCMR1_IC2F_1          (0x2UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x20000000 */
+
+/******************  Bit definition for LPTIM_CCR2 register  ******************/
+#define LPTIM_CCR2_CCR2_Pos         (0U)
+#define LPTIM_CCR2_CCR2_Msk         (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)           /*!< 0x0000FFFF */
+#define LPTIM_CCR2_CCR2             LPTIM_CCR2_CCR2_Msk                         /*!< Compare register 2 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/* Bit fields for LTDC_SSCR register */
+#define LTDC_SSCR_VSH_Pos                (0U)
+#define LTDC_SSCR_VSH_Msk                (0xfffUL << LTDC_SSCR_VSH_Pos)
+#define LTDC_SSCR_VSH                    LTDC_SSCR_VSH_Msk  /*!< vertical synchronization height (in units of horizontal scan line)These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. */
+#define LTDC_SSCR_HSW_Pos                (16U)
+#define LTDC_SSCR_HSW_Msk                (0xfffUL << LTDC_SSCR_HSW_Pos)
+#define LTDC_SSCR_HSW                    LTDC_SSCR_HSW_Msk  /*!< horizontal synchronization width (in units of pixel clock period)These bits define the number of Horizontal Synchronization pixel minus 1. */
+
+/* Bit fields for LTDC_BPCR register */
+#define LTDC_BPCR_AVBP_Pos               (0U)
+#define LTDC_BPCR_AVBP_Msk               (0xfffUL << LTDC_BPCR_AVBP_Pos)
+#define LTDC_BPCR_AVBP                   LTDC_BPCR_AVBP_Msk  /*!< accumulated Vertical back porch (in units of horizontal scan line)These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1.The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. */
+#define LTDC_BPCR_AHBP_Pos               (16U)
+#define LTDC_BPCR_AHBP_Msk               (0xfffUL << LTDC_BPCR_AHBP_Pos)
+#define LTDC_BPCR_AHBP                   LTDC_BPCR_AHBP_Msk  /*!< accumulated horizontal back porch (in units of pixel clock period)These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1.The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. */
+
+/* Bit fields for LTDC_AWCR register */
+#define LTDC_AWCR_AAH_Pos                (0U)
+#define LTDC_AWCR_AAH_Msk                (0xfffUL << LTDC_AWCR_AAH_Pos)
+#define LTDC_AWCR_AAH                    LTDC_AWCR_AAH_Msk  /*!< accumulated active height (in units of horizontal scan line)These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel.Refer to device datasheet for maximum active height supported following maximum pixel clock. */
+#define LTDC_AWCR_AAW_Pos                (16U)
+#define LTDC_AWCR_AAW_Msk                (0xfffUL << LTDC_AWCR_AAW_Pos)
+#define LTDC_AWCR_AAW                    LTDC_AWCR_AAW_Msk  /*!< accumulated active width (in units of pixel clock period)These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1.The active width is the number of pixels in active display area of the panel scan line.Refer to device datasheet for maximum active width supported following maximum pixel clock. */
+
+/* Bit fields for LTDC_TWCR register */
+#define LTDC_TWCR_TOTALH_Pos             (0U)
+#define LTDC_TWCR_TOTALH_Msk             (0xfffUL << LTDC_TWCR_TOTALH_Pos)
+#define LTDC_TWCR_TOTALH                 LTDC_TWCR_TOTALH_Msk  /*!< total height (in units of horizontal scan line)These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. */
+#define LTDC_TWCR_TOTALW_Pos             (16U)
+#define LTDC_TWCR_TOTALW_Msk             (0xfffUL << LTDC_TWCR_TOTALW_Pos)
+#define LTDC_TWCR_TOTALW                 LTDC_TWCR_TOTALW_Msk  /*!< total width (in units of pixel clock period)These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. */
+
+/* Bit fields for LTDC_GCR register */
+#define LTDC_GCR_LTDCEN_Pos              (0U)
+#define LTDC_GCR_LTDCEN_Msk              (0x1UL << LTDC_GCR_LTDCEN_Pos)
+#define LTDC_GCR_LTDCEN                  LTDC_GCR_LTDCEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: LTDC disable- 1: LTDC enable */
+#define LTDC_GCR_GAMEN_Pos               (1U)
+#define LTDC_GCR_GAMEN_Msk               (0x1UL << LTDC_GCR_GAMEN_Pos)
+#define LTDC_GCR_GAMEN                   LTDC_GCR_GAMEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: GammaCorrection disable (pixels bypass the gamma operator)- 1: Gamma Correction enable */
+#define LTDC_GCR_ROTEN_Pos               (2U)
+#define LTDC_GCR_ROTEN_Msk               (0x1UL << LTDC_GCR_ROTEN_Pos)
+#define LTDC_GCR_ROTEN                   LTDC_GCR_ROTEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: Rotation disable- 1: Rotation enable (for a pure visual rotation, the mirroring has to be activated) */
+#define LTDC_GCR_DBW_Pos                 (4U)
+#define LTDC_GCR_DBW_Msk                 (0x7UL << LTDC_GCR_DBW_Pos)
+#define LTDC_GCR_DBW                     LTDC_GCR_DBW_Msk  /*!< dither blue widthThese bits return the dither blue bits. */
+#define LTDC_GCR_DGW_Pos                 (8U)
+#define LTDC_GCR_DGW_Msk                 (0x7UL << LTDC_GCR_DGW_Pos)
+#define LTDC_GCR_DGW                     LTDC_GCR_DGW_Msk  /*!< dither green widthThese bits return the dither green bits. */
+#define LTDC_GCR_DRW_Pos                 (12U)
+#define LTDC_GCR_DRW_Msk                 (0x7UL << LTDC_GCR_DRW_Pos)
+#define LTDC_GCR_DRW                     LTDC_GCR_DRW_Msk  /*!< dither red widthThese bits return the Dither Red Bits. */
+#define LTDC_GCR_DEN_Pos                 (16U)
+#define LTDC_GCR_DEN_Msk                 (0x1UL << LTDC_GCR_DEN_Pos)
+#define LTDC_GCR_DEN                     LTDC_GCR_DEN_Msk  /*!< dither enableThis bit is set and cleared by software.- 0: dither disable- 1: dither enable */
+#define LTDC_GCR_BCKEN_Pos               (17U)
+#define LTDC_GCR_BCKEN_Msk               (0x1UL << LTDC_GCR_BCKEN_Pos)
+#define LTDC_GCR_BCKEN                   LTDC_GCR_BCKEN_Msk  /*!< backgroundlayer enableThis bit is set and cleared by software.- 0: backgrounddisable- 1: background enable */
+#define LTDC_GCR_CRCEN_Pos               (19U)
+#define LTDC_GCR_CRCEN_Msk               (0x1UL << LTDC_GCR_CRCEN_Pos)
+#define LTDC_GCR_CRCEN                   LTDC_GCR_CRCEN_Msk  /*!< CRC enableThis bit is set and cleared by software.- 0: CRC disable- 1: CRC enable */
+#define LTDC_GCR_SFEN_Pos                (24U)
+#define LTDC_GCR_SFEN_Msk                (0x1UL << LTDC_GCR_SFEN_Pos)
+#define LTDC_GCR_SFEN                    LTDC_GCR_SFEN_Msk  /*!< single-frame mode: mode enableThis bit is set and cleared by software.- 0: single-frame disable:a trigger (on SFSW or External) will generate a continuous flow.- 1: single-frame enable: a trigger (on SFSW or External) will generate a single frame. */
+#define LTDC_GCR_SFSWTR_Pos              (25U)
+#define LTDC_GCR_SFSWTR_Msk              (0x1UL << LTDC_GCR_SFSWTR_Pos)
+#define LTDC_GCR_SFSWTR                  LTDC_GCR_SFSWTR_Msk  /*!< single-frame mode: software triggerThis bit is set by software and cleared by hardware.- 0: no action- 1: triggers one frame */
+#define LTDC_GCR_SFEXEN_Pos              (26U)
+#define LTDC_GCR_SFEXEN_Msk              (0x1UL << LTDC_GCR_SFEXEN_Pos)
+#define LTDC_GCR_SFEXEN                  LTDC_GCR_SFEXEN_Msk  /*!< single-frame mode: external trigger enableThis bit is set and cleared by software.- 0: external trigger disable- 1: external trigger enable: a trigger on the external trigger will generate one single frame. */
+#define LTDC_GCR_PCPOL_Pos               (28U)
+#define LTDC_GCR_PCPOL_Msk               (0x1UL << LTDC_GCR_PCPOL_Pos)
+#define LTDC_GCR_PCPOL                   LTDC_GCR_PCPOL_Msk  /*!< pixel clock polarityThis bit is set and cleared by software.- 0: pixel clock polarity is active low.- 1: pixel clock is active high. */
+#define LTDC_GCR_DEPOL_Pos               (29U)
+#define LTDC_GCR_DEPOL_Msk               (0x1UL << LTDC_GCR_DEPOL_Pos)
+#define LTDC_GCR_DEPOL                   LTDC_GCR_DEPOL_Msk  /*!< blanking (=no data/pixel) polarityThis bit is set and cleared by software.- 0: blanking (no data/pixel) polarity is active low.- 1: blanking (no data/pixel) polarity is active high. */
+#define LTDC_GCR_VSPOL_Pos               (30U)
+#define LTDC_GCR_VSPOL_Msk               (0x1UL << LTDC_GCR_VSPOL_Pos)
+#define LTDC_GCR_VSPOL                   LTDC_GCR_VSPOL_Msk  /*!< vertical synchronization polarityThis bit is set and cleared by software.- 0: vertical synchronization is active low.- 1: vertical synchronization is active high. */
+#define LTDC_GCR_HSPOL_Pos               (31U)
+#define LTDC_GCR_HSPOL_Msk               (0x1UL << LTDC_GCR_HSPOL_Pos)
+#define LTDC_GCR_HSPOL                   LTDC_GCR_HSPOL_Msk  /*!< horizontal synchronization polarityThis bit is set and cleared by software.- 0: horizontal synchronization polarity is active low.- 1: horizontal synchronization polarity is active high. */
+
+/* Bit fields for LTDC_SRCR register */
+#define LTDC_SRCR_IMR_Pos                (0U)
+#define LTDC_SRCR_IMR_Msk                (0x1UL << LTDC_SRCR_IMR_Pos)
+#define LTDC_SRCR_IMR                    LTDC_SRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_SRCR_VBR_Pos                (1U)
+#define LTDC_SRCR_VBR_Msk                (0x1UL << LTDC_SRCR_VBR_Pos)
+#define LTDC_SRCR_VBR                    LTDC_SRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+
+/* Bit fields for LTDC_GCCR register */
+#define LTDC_GCCR_ADDR_Pos               (0U)
+#define LTDC_GCCR_ADDR_Msk               (0xffUL << LTDC_GCCR_ADDR_Pos)
+#define LTDC_GCCR_ADDR                   LTDC_GCCR_ADDR_Msk  /*!< address of the R,G,B table where the COMP component is written.When LTDC_GC1R.GCT=2, the gamma is implemented with 8 interpolated segment. In that case, the valid ADDR addresses are: 0, 32, 64, 96, 128, 160, 192, 224, 255.Note that for ADDR=255, the gamma interpolation hardware considers that the address is 256. */
+#define LTDC_GCCR_COMP_Pos               (8U)
+#define LTDC_GCCR_COMP_Msk               (0xffUL << LTDC_GCCR_COMP_Pos)
+#define LTDC_GCCR_COMP                   LTDC_GCCR_COMP_Msk  /*!< color component to be written, in either (or all) the R,G,B tables.. */
+#define LTDC_GCCR_BEN_Pos                (16U)
+#define LTDC_GCCR_BEN_Msk                (0x1UL << LTDC_GCCR_BEN_Pos)
+#define LTDC_GCCR_BEN                    LTDC_GCCR_BEN_Msk  /*!< write trigger to the blue table- 0: no action done- 1: COMP is written at ADDR in the Blue table. */
+#define LTDC_GCCR_GEN_Pos                (17U)
+#define LTDC_GCCR_GEN_Msk                (0x1UL << LTDC_GCCR_GEN_Pos)
+#define LTDC_GCCR_GEN                    LTDC_GCCR_GEN_Msk  /*!< write trigger to the green table- 0: no action done- 1: COMP is written at ADDR in the Green table. */
+#define LTDC_GCCR_REN_Pos                (18U)
+#define LTDC_GCCR_REN_Msk                (0x1UL << LTDC_GCCR_REN_Pos)
+#define LTDC_GCCR_REN                    LTDC_GCCR_REN_Msk  /*!< write trigger to the red table- 0: no action done- 1: COMP is written at ADDR in the Red table. */
+
+/* Bit fields for LTDC_BCCR register */
+#define LTDC_BCCR_BCBLUE_Pos             (0U)
+#define LTDC_BCCR_BCBLUE_Msk             (0xffUL << LTDC_BCCR_BCBLUE_Pos)
+#define LTDC_BCCR_BCBLUE                 LTDC_BCCR_BCBLUE_Msk  /*!< background color blue valueThese bits configure the background blue value. */
+#define LTDC_BCCR_BCGREEN_Pos            (8U)
+#define LTDC_BCCR_BCGREEN_Msk            (0xffUL << LTDC_BCCR_BCGREEN_Pos)
+#define LTDC_BCCR_BCGREEN                LTDC_BCCR_BCGREEN_Msk  /*!< background color green valueThese bits configure the background green value. */
+#define LTDC_BCCR_BCRED_Pos              (16U)
+#define LTDC_BCCR_BCRED_Msk              (0xffUL << LTDC_BCCR_BCRED_Pos)
+#define LTDC_BCCR_BCRED                  LTDC_BCCR_BCRED_Msk  /*!< background color red valueThese bits configure the background red value. */
+
+/* Bit fields for LTDC_IER register */
+#define LTDC_IER_LIE_Pos                 (0U)
+#define LTDC_IER_LIE_Msk                 (0x1UL << LTDC_IER_LIE_Pos)
+#define LTDC_IER_LIE                     LTDC_IER_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER_FUWIE_Pos               (1U)
+#define LTDC_IER_FUWIE_Msk               (0x1UL << LTDC_IER_FUWIE_Pos)
+#define LTDC_IER_FUWIE                   LTDC_IER_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER_TERRIE_Pos              (2U)
+#define LTDC_IER_TERRIE_Msk              (0x1UL << LTDC_IER_TERRIE_Pos)
+#define LTDC_IER_TERRIE                  LTDC_IER_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER_RRIE_Pos                (3U)
+#define LTDC_IER_RRIE_Msk                (0x1UL << LTDC_IER_RRIE_Pos)
+#define LTDC_IER_RRIE                    LTDC_IER_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER_FUIE_Pos                (6U)
+#define LTDC_IER_FUIE_Msk                (0x1UL << LTDC_IER_FUIE_Pos)
+#define LTDC_IER_FUIE                    LTDC_IER_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER_CRCIE_Pos               (7U)
+#define LTDC_IER_CRCIE_Msk               (0x1UL << LTDC_IER_CRCIE_Pos)
+#define LTDC_IER_CRCIE                   LTDC_IER_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+#define LTDC_IER_FURIE_Pos               (8U)
+#define LTDC_IER_FURIE_Msk               (0x1UL << LTDC_IER_FURIE_Pos)
+#define LTDC_IER_FURIE                   LTDC_IER_FURIE_Msk  /*!< FIFOunderrun at rotation interrupt enableThis bit is set and cleared by software.- 0: FIFOunderrun at rotation interrupt disable- 1: FIFO underrunat rotation interrupt enable */
+
+/* Bit fields for LTDC_ISR register */
+#define LTDC_ISR_LIF_Pos                 (0U)
+#define LTDC_ISR_LIF_Msk                 (0x1UL << LTDC_ISR_LIF_Pos)
+#define LTDC_ISR_LIF                     LTDC_ISR_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR_FUWIF_Pos               (1U)
+#define LTDC_ISR_FUWIF_Msk               (0x1UL << LTDC_ISR_FUWIF_Pos)
+#define LTDC_ISR_FUWIF                   LTDC_ISR_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR_TERRIF_Pos              (2U)
+#define LTDC_ISR_TERRIF_Msk              (0x1UL << LTDC_ISR_TERRIF_Pos)
+#define LTDC_ISR_TERRIF                  LTDC_ISR_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR_RRIF_Pos                (3U)
+#define LTDC_ISR_RRIF_Msk                (0x1UL << LTDC_ISR_RRIF_Pos)
+#define LTDC_ISR_RRIF                    LTDC_ISR_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR_FUIF_Pos                (6U)
+#define LTDC_ISR_FUIF_Msk                (0x1UL << LTDC_ISR_FUIF_Pos)
+#define LTDC_ISR_FUIF                    LTDC_ISR_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data is read from the FIFO */
+#define LTDC_ISR_CRCIF_Pos               (7U)
+#define LTDC_ISR_CRCIF_Msk               (0x1UL << LTDC_ISR_CRCIF_Pos)
+#define LTDC_ISR_CRCIF                   LTDC_ISR_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when the computed CRC is different from the expected CRC. */
+#define LTDC_ISR_FURIF_Pos               (8U)
+#define LTDC_ISR_FURIF_Msk               (0x1UL << LTDC_ISR_FURIF_Pos)
+#define LTDC_ISR_FURIF                   LTDC_ISR_FURIF_Msk  /*!< FIFO underrun at rotation interrupt flag- 0: no FIFO underrun at rotation interrupt generated- 1: FIFO underrun at rotation interrupt generated */
+
+/* Bit fields for LTDC_ICR register */
+#define LTDC_ICR_CLIF_Pos                (0U)
+#define LTDC_ICR_CLIF_Msk                (0x1UL << LTDC_ICR_CLIF_Pos)
+#define LTDC_ICR_CLIF                    LTDC_ICR_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFUWIF_Pos              (1U)
+#define LTDC_ICR_CFUWIF_Msk              (0x1UL << LTDC_ICR_CFUWIF_Pos)
+#define LTDC_ICR_CFUWIF                  LTDC_ICR_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CTERRIF_Pos             (2U)
+#define LTDC_ICR_CTERRIF_Msk             (0x1UL << LTDC_ICR_CTERRIF_Pos)
+#define LTDC_ICR_CTERRIF                 LTDC_ICR_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CRRIF_Pos               (3U)
+#define LTDC_ICR_CRRIF_Msk               (0x1UL << LTDC_ICR_CRRIF_Pos)
+#define LTDC_ICR_CRRIF                   LTDC_ICR_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR_CFUIF_Pos               (6U)
+#define LTDC_ICR_CFUIF_Msk               (0x1UL << LTDC_ICR_CFUIF_Pos)
+#define LTDC_ICR_CFUIF                   LTDC_ICR_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CCRCIF_Pos              (7U)
+#define LTDC_ICR_CCRCIF_Msk              (0x1UL << LTDC_ICR_CCRCIF_Pos)
+#define LTDC_ICR_CCRCIF                  LTDC_ICR_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFURIF_Pos              (8U)
+#define LTDC_ICR_CFURIF_Msk              (0x1UL << LTDC_ICR_CFURIF_Pos)
+#define LTDC_ICR_CFURIF                  LTDC_ICR_CFURIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the FURIF flag in the LTDC_ISR register */
+
+/* Bit fields for LTDC_LIPCR register */
+#define LTDC_LIPCR_LIPOS_Pos             (0U)
+#define LTDC_LIPCR_LIPOS_Msk             (0xfffUL << LTDC_LIPCR_LIPOS_Pos)
+#define LTDC_LIPCR_LIPOS                 LTDC_LIPCR_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR register */
+#define LTDC_CPSR_CYPOS_Pos              (0U)
+#define LTDC_CPSR_CYPOS_Msk              (0xfffUL << LTDC_CPSR_CYPOS_Pos)
+#define LTDC_CPSR_CYPOS                  LTDC_CPSR_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR_CXPOS_Pos              (16U)
+#define LTDC_CPSR_CXPOS_Msk              (0xfffUL << LTDC_CPSR_CXPOS_Pos)
+#define LTDC_CPSR_CXPOS                  LTDC_CPSR_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_CDSR register */
+#define LTDC_CDSR_VDES_Pos               (0U)
+#define LTDC_CDSR_VDES_Msk               (0x1UL << LTDC_CDSR_VDES_Pos)
+#define LTDC_CDSR_VDES                   LTDC_CDSR_VDES_Msk  /*!< vertical data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HDES_Pos               (1U)
+#define LTDC_CDSR_HDES_Msk               (0x1UL << LTDC_CDSR_HDES_Pos)
+#define LTDC_CDSR_HDES                   LTDC_CDSR_HDES_Msk  /*!< horizontal data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_VSYNCS_Pos             (2U)
+#define LTDC_CDSR_VSYNCS_Msk             (0x1UL << LTDC_CDSR_VSYNCS_Pos)
+#define LTDC_CDSR_VSYNCS                 LTDC_CDSR_VSYNCS_Msk  /*!< vertical synchronization display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HSYNCS_Pos             (3U)
+#define LTDC_CDSR_HSYNCS_Msk             (0x1UL << LTDC_CDSR_HSYNCS_Pos)
+#define LTDC_CDSR_HSYNCS                 LTDC_CDSR_HSYNCS_Msk  /*!< horizontal synchronization display status- 0: active low- 1: active high */
+
+/* Bit fields for LTDC_EDCR register */
+#define LTDC_EDCR_OCYEN_Pos              (25U)
+#define LTDC_EDCR_OCYEN_Msk              (0x1UL << LTDC_EDCR_OCYEN_Pos)
+#define LTDC_EDCR_OCYEN                  LTDC_EDCR_OCYEN_Msk  /*!< output conversion to YCbCr 422: Enable- 0: conversion is disabled- 1: conversion is enabled */
+#define LTDC_EDCR_OCYSEL_Pos             (26U)
+#define LTDC_EDCR_OCYSEL_Msk             (0x1UL << LTDC_EDCR_OCYSEL_Pos)
+#define LTDC_EDCR_OCYSEL                 LTDC_EDCR_OCYSEL_Msk  /*!< output conversion to YCbCr 422: selection of the CCIR hard-wired coefficients:- 0: use CCIR-BT601 set (for typically SDTV analog-like displays)- 1: use CCIR-BT709 set (for typically HDTV digital-like displays) */
+#define LTDC_EDCR_OCYCO_Pos              (27U)
+#define LTDC_EDCR_OCYCO_Msk              (0x1UL << LTDC_EDCR_OCYCO_Pos)
+#define LTDC_EDCR_OCYCO                  LTDC_EDCR_OCYCO_Msk  /*!< output conversion to YCbCr 422: chrominance order.- 0: Cb is output first (so: Y0Cb, then Y1Cr, Y2Cb, etc .. ).- 1: Cr is output first (so: Y0Cr, then Y1Cb, Y2Cr, etc ..). */
+
+/* Bit fields for LTDC_IER2 register */
+#define LTDC_IER2_LIE_Pos                (0U)
+#define LTDC_IER2_LIE_Msk                (0x1UL << LTDC_IER2_LIE_Pos)
+#define LTDC_IER2_LIE                    LTDC_IER2_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER2_FUWIE_Pos              (1U)
+#define LTDC_IER2_FUWIE_Msk              (0x1UL << LTDC_IER2_FUWIE_Pos)
+#define LTDC_IER2_FUWIE                  LTDC_IER2_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER2_TERRIE_Pos             (2U)
+#define LTDC_IER2_TERRIE_Msk             (0x1UL << LTDC_IER2_TERRIE_Pos)
+#define LTDC_IER2_TERRIE                 LTDC_IER2_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER2_RRIE_Pos               (3U)
+#define LTDC_IER2_RRIE_Msk               (0x1UL << LTDC_IER2_RRIE_Pos)
+#define LTDC_IER2_RRIE                   LTDC_IER2_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER2_FUIE_Pos               (6U)
+#define LTDC_IER2_FUIE_Msk               (0x1UL << LTDC_IER2_FUIE_Pos)
+#define LTDC_IER2_FUIE                   LTDC_IER2_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER2_CRCIE_Pos              (7U)
+#define LTDC_IER2_CRCIE_Msk              (0x1UL << LTDC_IER2_CRCIE_Pos)
+#define LTDC_IER2_CRCIE                  LTDC_IER2_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+
+/* Bit fields for LTDC_ISR2 register */
+#define LTDC_ISR2_LIF_Pos                (0U)
+#define LTDC_ISR2_LIF_Msk                (0x1UL << LTDC_ISR2_LIF_Pos)
+#define LTDC_ISR2_LIF                    LTDC_ISR2_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR2_FUWIF_Pos              (1U)
+#define LTDC_ISR2_FUWIF_Msk              (0x1UL << LTDC_ISR2_FUWIF_Pos)
+#define LTDC_ISR2_FUWIF                  LTDC_ISR2_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR2_TERRIF_Pos             (2U)
+#define LTDC_ISR2_TERRIF_Msk             (0x1UL << LTDC_ISR2_TERRIF_Pos)
+#define LTDC_ISR2_TERRIF                 LTDC_ISR2_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR2_RRIF_Pos               (3U)
+#define LTDC_ISR2_RRIF_Msk               (0x1UL << LTDC_ISR2_RRIF_Pos)
+#define LTDC_ISR2_RRIF                   LTDC_ISR2_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR2_FUIF_Pos               (6U)
+#define LTDC_ISR2_FUIF_Msk               (0x1UL << LTDC_ISR2_FUIF_Pos)
+#define LTDC_ISR2_FUIF                   LTDC_ISR2_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO */
+#define LTDC_ISR2_CRCIF_Pos              (7U)
+#define LTDC_ISR2_CRCIF_Msk              (0x1UL << LTDC_ISR2_CRCIF_Pos)
+#define LTDC_ISR2_CRCIF                  LTDC_ISR2_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when a bus error occurs */
+
+/* Bit fields for LTDC_ICR2 register */
+#define LTDC_ICR2_CLIF_Pos               (0U)
+#define LTDC_ICR2_CLIF_Msk               (0x1UL << LTDC_ICR2_CLIF_Pos)
+#define LTDC_ICR2_CLIF                   LTDC_ICR2_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CFUWIF_Pos             (1U)
+#define LTDC_ICR2_CFUWIF_Msk             (0x1UL << LTDC_ICR2_CFUWIF_Pos)
+#define LTDC_ICR2_CFUWIF                 LTDC_ICR2_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CTERRIF_Pos            (2U)
+#define LTDC_ICR2_CTERRIF_Msk            (0x1UL << LTDC_ICR2_CTERRIF_Pos)
+#define LTDC_ICR2_CTERRIF                LTDC_ICR2_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CRRIF_Pos              (3U)
+#define LTDC_ICR2_CRRIF_Msk              (0x1UL << LTDC_ICR2_CRRIF_Pos)
+#define LTDC_ICR2_CRRIF                  LTDC_ICR2_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR2_CFUIF_Pos              (6U)
+#define LTDC_ICR2_CFUIF_Msk              (0x1UL << LTDC_ICR2_CFUIF_Pos)
+#define LTDC_ICR2_CFUIF                  LTDC_ICR2_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CCRCIF_Pos             (7U)
+#define LTDC_ICR2_CCRCIF_Msk             (0x1UL << LTDC_ICR2_CCRCIF_Pos)
+#define LTDC_ICR2_CCRCIF                 LTDC_ICR2_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+
+/* Bit fields for LTDC_LIPCR2 register */
+#define LTDC_LIPCR2_LIPOS_Pos             (0U)
+#define LTDC_LIPCR2_LIPOS_Msk             (0xffffUL << LTDC_LIPCR2_LIPOS_Pos)
+#define LTDC_LIPCR2_LIPOS                 LTDC_LIPCR2_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR2 register */
+#define LTDC_CPSR2_CYPOS_Pos             (0U)
+#define LTDC_CPSR2_CYPOS_Msk             (0xffffUL << LTDC_CPSR2_CYPOS_Pos)
+#define LTDC_CPSR2_CYPOS                 LTDC_CPSR2_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR2_CXPOS_Pos             (16U)
+#define LTDC_CPSR2_CXPOS_Msk             (0xffffUL << LTDC_CPSR2_CXPOS_Pos)
+#define LTDC_CPSR2_CXPOS                 LTDC_CPSR2_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_ECRCR register */
+#define LTDC_ECRCR_ECRC_Pos              (0U)
+#define LTDC_ECRCR_ECRC_Msk              (0xffffUL << LTDC_ECRCR_ECRC_Pos)
+#define LTDC_ECRCR_ECRC                  LTDC_ECRCR_ECRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_CCRCR register */
+#define LTDC_CCRCR_CCRC_Pos              (0U)
+#define LTDC_CCRCR_CCRC_Msk              (0xffffUL << LTDC_CCRCR_CCRC_Pos)
+#define LTDC_CCRCR_CCRC                  LTDC_CCRCR_CCRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_FUTR register */
+#define LTDC_FUTR_THRE_Pos               (0U)
+#define LTDC_FUTR_THRE_Msk               (0xffffUL << LTDC_FUTR_THRE_Pos)
+#define LTDC_FUTR_THRE                   LTDC_FUTR_THRE_Msk  /*!< threshold to trigger a FIFO underrun killing interrupt (unit is per fifo word, 64bit) */
+
+/* Bit fields for LTDC_LxC0R register */
+#define LTDC_LxC0R_CKTA_Pos              (0U)
+#define LTDC_LxC0R_CKTA_Msk              (0x1UL << LTDC_LxC0R_CKTA_Pos)
+#define LTDC_LxC0R_CKTA                  LTDC_LxC0R_CKTA_Msk  /*!< color key transparency Ability */
+#define LTDC_LxC0R_CFBDA_Pos             (1U)
+#define LTDC_LxC0R_CFBDA_Msk             (0x1UL << LTDC_LxC0R_CFBDA_Pos)
+#define LTDC_LxC0R_CFBDA                 LTDC_LxC0R_CFBDA_Msk  /*!< color frame buffer duplication ability */
+#define LTDC_LxC0R_CFBPA_Pos             (2U)
+#define LTDC_LxC0R_CFBPA_Msk             (0x1UL << LTDC_LxC0R_CFBPA_Pos)
+#define LTDC_LxC0R_CFBPA                 LTDC_LxC0R_CFBPA_Msk  /*!< color frame buffer pitch ability */
+#define LTDC_LxC0R_APA_Pos               (3U)
+#define LTDC_LxC0R_APA_Msk               (0x1UL << LTDC_LxC0R_APA_Pos)
+#define LTDC_LxC0R_APA                   LTDC_LxC0R_APA_Msk  /*!< alpha plane ability */
+#define LTDC_LxC0R_DCP_Pos               (4U)
+#define LTDC_LxC0R_DCP_Msk               (0x1UL << LTDC_LxC0R_DCP_Pos)
+#define LTDC_LxC0R_DCP                   LTDC_LxC0R_DCP_Msk  /*!< default color programmability */
+#define LTDC_LxC0R_WINA_Pos              (5U)
+#define LTDC_LxC0R_WINA_Msk              (0x1UL << LTDC_LxC0R_WINA_Pos)
+#define LTDC_LxC0R_WINA                  LTDC_LxC0R_WINA_Msk  /*!< windowing ability */
+#define LTDC_LxC0R_CLUTA_Pos             (6U)
+#define LTDC_LxC0R_CLUTA_Msk             (0x1UL << LTDC_LxC0R_CLUTA_Pos)
+#define LTDC_LxC0R_CLUTA                 LTDC_LxC0R_CLUTA_Msk  /*!< CLUT ability */
+#define LTDC_LxC0R_CKRA_Pos              (7U)
+#define LTDC_LxC0R_CKRA_Msk              (0x1UL << LTDC_LxC0R_CKRA_Pos)
+#define LTDC_LxC0R_CKRA                  LTDC_LxC0R_CKRA_Msk  /*!< color key replace ability */
+#define LTDC_LxC0R_F21_Pos               (8U)
+#define LTDC_LxC0R_F21_Msk               (0x1UL << LTDC_LxC0R_F21_Pos)
+#define LTDC_LxC0R_F21                   LTDC_LxC0R_F21_Msk  /*!< blending factor 2, ability for: 1.0 */
+#define LTDC_LxC0R_F20_Pos               (9U)
+#define LTDC_LxC0R_F20_Msk               (0x1UL << LTDC_LxC0R_F20_Pos)
+#define LTDC_LxC0R_F20                   LTDC_LxC0R_F20_Msk  /*!< blending factor 2, ability for: 0.0 */
+#define LTDC_LxC0R_F2P_Pos               (10U)
+#define LTDC_LxC0R_F2P_Msk               (0x1UL << LTDC_LxC0R_F2P_Pos)
+#define LTDC_LxC0R_F2P                   LTDC_LxC0R_F2P_Msk  /*!< blending factor 2, ability for: pixel_alpha */
+#define LTDC_LxC0R_F21P_Pos              (11U)
+#define LTDC_LxC0R_F21P_Msk              (0x1UL << LTDC_LxC0R_F21P_Pos)
+#define LTDC_LxC0R_F21P                  LTDC_LxC0R_F21P_Msk  /*!< blending factor 2, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F2C_Pos               (12U)
+#define LTDC_LxC0R_F2C_Msk               (0x1UL << LTDC_LxC0R_F2C_Pos)
+#define LTDC_LxC0R_F2C                   LTDC_LxC0R_F2C_Msk  /*!< blending factor 2, ability for: constant_alpha */
+#define LTDC_LxC0R_F21C_Pos              (13U)
+#define LTDC_LxC0R_F21C_Msk              (0x1UL << LTDC_LxC0R_F21C_Pos)
+#define LTDC_LxC0R_F21C                  LTDC_LxC0R_F21C_Msk  /*!< blending factor 2, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F2PC_Pos              (14U)
+#define LTDC_LxC0R_F2PC_Msk              (0x1UL << LTDC_LxC0R_F2PC_Pos)
+#define LTDC_LxC0R_F2PC                  LTDC_LxC0R_F2PC_Msk  /*!< blending factor 2, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F21PC_Pos             (15U)
+#define LTDC_LxC0R_F21PC_Msk             (0x1UL << LTDC_LxC0R_F21PC_Pos)
+#define LTDC_LxC0R_F21PC                 LTDC_LxC0R_F21PC_Msk  /*!< blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_F11_Pos               (16U)
+#define LTDC_LxC0R_F11_Msk               (0x1UL << LTDC_LxC0R_F11_Pos)
+#define LTDC_LxC0R_F11                   LTDC_LxC0R_F11_Msk  /*!< blending factor 1, ability for: 1.0 */
+#define LTDC_LxC0R_F10_Pos               (17U)
+#define LTDC_LxC0R_F10_Msk               (0x1UL << LTDC_LxC0R_F10_Pos)
+#define LTDC_LxC0R_F10                   LTDC_LxC0R_F10_Msk  /*!< blending factor 1,ability for: 0.0 */
+#define LTDC_LxC0R_F1P_Pos               (18U)
+#define LTDC_LxC0R_F1P_Msk               (0x1UL << LTDC_LxC0R_F1P_Pos)
+#define LTDC_LxC0R_F1P                   LTDC_LxC0R_F1P_Msk  /*!< blending factor 1, ability for: pixel_alpha */
+#define LTDC_LxC0R_F11P_Pos              (19U)
+#define LTDC_LxC0R_F11P_Msk              (0x1UL << LTDC_LxC0R_F11P_Pos)
+#define LTDC_LxC0R_F11P                  LTDC_LxC0R_F11P_Msk  /*!< blending factor 1, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F1C_Pos               (20U)
+#define LTDC_LxC0R_F1C_Msk               (0x1UL << LTDC_LxC0R_F1C_Pos)
+#define LTDC_LxC0R_F1C                   LTDC_LxC0R_F1C_Msk  /*!< blending factor 1, ability for: constant_alpha */
+#define LTDC_LxC0R_F11C_Pos              (21U)
+#define LTDC_LxC0R_F11C_Msk              (0x1UL << LTDC_LxC0R_F11C_Pos)
+#define LTDC_LxC0R_F11C                  LTDC_LxC0R_F11C_Msk  /*!< blending factor 1, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F1PC_Pos              (22U)
+#define LTDC_LxC0R_F1PC_Msk              (0x1UL << LTDC_LxC0R_F1PC_Pos)
+#define LTDC_LxC0R_F1PC                  LTDC_LxC0R_F1PC_Msk  /*!< blending factor 1, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F11PC_Pos             (23U)
+#define LTDC_LxC0R_F11PC_Msk             (0x1UL << LTDC_LxC0R_F11PC_Pos)
+#define LTDC_LxC0R_F11PC                 LTDC_LxC0R_F11PC_Msk  /*!< blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_P88_Pos               (24U)
+#define LTDC_LxC0R_P88_Msk               (0x1UL << LTDC_LxC0R_P88_Pos)
+#define LTDC_LxC0R_P88                   LTDC_LxC0R_P88_Msk  /*!< pixel format, ability for: AL88. */
+#define LTDC_LxC0R_P44_Pos               (25U)
+#define LTDC_LxC0R_P44_Msk               (0x1UL << LTDC_LxC0R_P44_Pos)
+#define LTDC_LxC0R_P44                   LTDC_LxC0R_P44_Msk  /*!< pixel format, ability for: AL44. */
+#define LTDC_LxC0R_P8_Pos                (26U)
+#define LTDC_LxC0R_P8_Msk                (0x1UL << LTDC_LxC0R_P8_Pos)
+#define LTDC_LxC0R_P8                    LTDC_LxC0R_P8_Msk  /*!< pixel format, ability for: L8. */
+#define LTDC_LxC0R_P4444_Pos             (27U)
+#define LTDC_LxC0R_P4444_Msk             (0x1UL << LTDC_LxC0R_P4444_Pos)
+#define LTDC_LxC0R_P4444                 LTDC_LxC0R_P4444_Msk  /*!< pixel format, ability for: ARGB4444. */
+#define LTDC_LxC0R_P1555_Pos             (28U)
+#define LTDC_LxC0R_P1555_Msk             (0x1UL << LTDC_LxC0R_P1555_Pos)
+#define LTDC_LxC0R_P1555                 LTDC_LxC0R_P1555_Msk  /*!< pixel format, ability for: ARGB1555. */
+#define LTDC_LxC0R_P565_Pos              (29U)
+#define LTDC_LxC0R_P565_Msk              (0x1UL << LTDC_LxC0R_P565_Pos)
+#define LTDC_LxC0R_P565                  LTDC_LxC0R_P565_Msk  /*!< pixel format, ability for: RGB565. */
+#define LTDC_LxC0R_P888_Pos              (30U)
+#define LTDC_LxC0R_P888_Msk              (0x1UL << LTDC_LxC0R_P888_Pos)
+#define LTDC_LxC0R_P888                  LTDC_LxC0R_P888_Msk  /*!< pixel format, ability for: RGB888. */
+#define LTDC_LxC0R_P8888_Pos             (31U)
+#define LTDC_LxC0R_P8888_Msk             (0x1UL << LTDC_LxC0R_P8888_Pos)
+#define LTDC_LxC0R_P8888                 LTDC_LxC0R_P8888_Msk  /*!< pixel format, ability for: ARGB8888. */
+
+/* Bit fields for LTDC_LxC1R register */
+#define LTDC_LxC1R_YIA_Pos               (0U)
+#define LTDC_LxC1R_YIA_Msk               (0x1UL << LTDC_LxC1R_YIA_Pos)
+#define LTDC_LxC1R_YIA                   LTDC_LxC1R_YIA_Msk  /*!< YCbCr 422 interleaved ability for that layer.- 0: interleaved not available- 1: interleaved available */
+#define LTDC_LxC1R_YSPA_Pos              (1U)
+#define LTDC_LxC1R_YSPA_Msk              (0x1UL << LTDC_LxC1R_YSPA_Pos)
+#define LTDC_LxC1R_YSPA                  LTDC_LxC1R_YSPA_Msk  /*!< YCbCr 420 semi-planar ability for that layer.- 0: semiplanar not available- 1: semi-planar available */
+#define LTDC_LxC1R_YFPA_Pos              (2U)
+#define LTDC_LxC1R_YFPA_Msk              (0x1UL << LTDC_LxC1R_YFPA_Pos)
+#define LTDC_LxC1R_YFPA                  LTDC_LxC1R_YFPA_Msk  /*!< YCbCr 420 full-planar ability for that layer.- 0: full planar not available- 1: full planar available */
+#define LTDC_LxC1R_SCA_Pos               (31U)
+#define LTDC_LxC1R_SCA_Msk               (0x1UL << LTDC_LxC1R_SCA_Pos)
+#define LTDC_LxC1R_SCA                   LTDC_LxC1R_SCA_Msk  /*!< scaling ability for that layer.- 0: scaling not available- 1: scaling available */
+
+/* Bit fields for LTDC_LxRCR register */
+#define LTDC_LxRCR_IMR_Pos               (0U)
+#define LTDC_LxRCR_IMR_Msk               (0x1UL << LTDC_LxRCR_IMR_Pos)
+#define LTDC_LxRCR_IMR                   LTDC_LxRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_LxRCR_VBR_Pos               (1U)
+#define LTDC_LxRCR_VBR_Msk               (0x1UL << LTDC_LxRCR_VBR_Pos)
+#define LTDC_LxRCR_VBR                   LTDC_LxRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+#define LTDC_LxRCR_GRMSK_Pos             (2U)
+#define LTDC_LxRCR_GRMSK_Msk             (0x1UL << LTDC_LxRCR_GRMSK_Pos)
+#define LTDC_LxRCR_GRMSK                 LTDC_LxRCR_GRMSK_Msk  /*!< shadow reload control: global (centralized) reload maskedThis bit is set and cleared by software.- 0: global reload active (the control from the LTDC_SRCR are enabled)- 1: global reload is masked (the control from the LTDC_SRCR are disabled) */
+
+/* Bit fields for LTDC_LxCR register */
+#define LTDC_LxCR_LEN_Pos                (0U)
+#define LTDC_LxCR_LEN_Msk                (0x1UL << LTDC_LxCR_LEN_Pos)
+#define LTDC_LxCR_LEN                    LTDC_LxCR_LEN_Msk  /*!< layer enable: the bit is used to enable/disable the presence of this whole layer.This bit is set and cleared by software.- 0: layer disabled- 1: layer enabled */
+#define LTDC_LxCR_CKEN_Pos               (1U)
+#define LTDC_LxCR_CKEN_Msk               (0x1UL << LTDC_LxCR_CKEN_Pos)
+#define LTDC_LxCR_CKEN                   LTDC_LxCR_CKEN_Msk  /*!< color keying enableThis bit is set and cleared by software.- 0: color keying disabled- 1: color keying enabled: if RGB matches, then the ARGB are set to 0. */
+#define LTDC_LxCR_VPDEN_Pos              (2U)
+#define LTDC_LxCR_VPDEN_Msk              (0x1UL << LTDC_LxCR_VPDEN_Pos)
+#define LTDC_LxCR_VPDEN                  LTDC_LxCR_VPDEN_Msk  /*!< vertical pixel duplication enableThis bit is set and cleared by software.- 0: duplication disabled- 1: duplication enabled */
+#define LTDC_LxCR_CLUTEN_Pos             (4U)
+#define LTDC_LxCR_CLUTEN_Msk             (0x1UL << LTDC_LxCR_CLUTEN_Pos)
+#define LTDC_LxCR_CLUTEN                 LTDC_LxCR_CLUTEN_Msk  /*!< color look-up table enableThis bit is set and cleared by software.- 0: color look-up table disabled- 1: color look-up table enabledThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up table (CLUT) */
+#define LTDC_LxCR_HMEN_Pos               (8U)
+#define LTDC_LxCR_HMEN_Msk               (0x1UL << LTDC_LxCR_HMEN_Pos)
+#define LTDC_LxCR_HMEN                   LTDC_LxCR_HMEN_Msk  /*!< horizontal mirroring enableThis bit is set and cleared by software.- 0: mirror disabled- 1: mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instannce: if line is 100 pixels, 24bpp, then address is set to 299) */
+#define LTDC_LxCR_DCBEN_Pos              (9U)
+#define LTDC_LxCR_DCBEN_Msk              (0x1UL << LTDC_LxCR_DCBEN_Pos)
+#define LTDC_LxCR_DCBEN                  LTDC_LxCR_DCBEN_Msk  /*!< default color blending enableThis bit is set and cleared by software.- 0: blending disabled- 1: blending enabled */
+
+/* Bit fields for LTDC_LxWHPCR register */
+#define LTDC_LxWHPCR_WHSTPOS_Pos         (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSTPOS_Pos)
+#define LTDC_LxWHPCR_WHSTPOS             LTDC_LxWHPCR_WHSTPOS_Msk  /*!< window horizontal start positionThese bits configure the first visible pixel of a line of the layer window.WHSTPOS[15:0] must be >= AAW[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWHPCR_WHSPPOS_Pos         (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos)
+#define LTDC_LxWHPCR_WHSPPOS             LTDC_LxWHPCR_WHSPPOS_Msk  /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxWVPCR register */
+#define LTDC_LxWVPCR_WVSTPOS_Pos         (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos)
+#define LTDC_LxWVPCR_WVSTPOS             LTDC_LxWVPCR_WVSTPOS_Msk  /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWVPCR_WVSPPOS_Pos         (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos)
+#define LTDC_LxWVPCR_WVSPPOS             LTDC_LxWVPCR_WVSPPOS_Msk  /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxCKCR register */
+#define LTDC_LxCKCR_CKBLUE_Pos           (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk           (0xffUL << LTDC_LxCKCR_CKBLUE_Pos)
+#define LTDC_LxCKCR_CKBLUE               LTDC_LxCKCR_CKBLUE_Msk  /*!< color key blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos          (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk          (0xffUL << LTDC_LxCKCR_CKGREEN_Pos)
+#define LTDC_LxCKCR_CKGREEN              LTDC_LxCKCR_CKGREEN_Msk  /*!< color key green value */
+#define LTDC_LxCKCR_CKRED_Pos            (16U)
+#define LTDC_LxCKCR_CKRED_Msk            (0xffUL << LTDC_LxCKCR_CKRED_Pos)
+#define LTDC_LxCKCR_CKRED                LTDC_LxCKCR_CKRED_Msk  /*!< color key red value */
+
+/* Bit fields for LTDC_LxPFCR register */
+#define LTDC_LxPFCR_PF_Pos               (0U)
+#define LTDC_LxPFCR_PF_Msk               (0x7UL << LTDC_LxPFCR_PF_Pos)
+#define LTDC_LxPFCR_PF                   LTDC_LxPFCR_PF_Msk  /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */
+
+/* Bit fields for LTDC_LxCACR register */
+#define LTDC_LxCACR_CONSTA_Pos           (0U)
+#define LTDC_LxCACR_CONSTA_Msk           (0xffUL << LTDC_LxCACR_CONSTA_Pos)
+#define LTDC_LxCACR_CONSTA               LTDC_LxCACR_CONSTA_Msk  /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */
+
+/* Bit fields for LTDC_LxDCCR register */
+#define LTDC_LxDCCR_DCBLUE_Pos           (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk           (0xffUL << LTDC_LxDCCR_DCBLUE_Pos)
+#define LTDC_LxDCCR_DCBLUE               LTDC_LxDCCR_DCBLUE_Msk  /*!< default color blueThese bits configure the default blue value. */
+#define LTDC_LxDCCR_DCGREEN_Pos          (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk          (0xffUL << LTDC_LxDCCR_DCGREEN_Pos)
+#define LTDC_LxDCCR_DCGREEN              LTDC_LxDCCR_DCGREEN_Msk  /*!< default color greenThese bits configure the default green value. */
+#define LTDC_LxDCCR_DCRED_Pos            (16U)
+#define LTDC_LxDCCR_DCRED_Msk            (0xffUL << LTDC_LxDCCR_DCRED_Pos)
+#define LTDC_LxDCCR_DCRED                LTDC_LxDCCR_DCRED_Msk  /*!< default color redThese bits configure the default red value. */
+#define LTDC_LxDCCR_DCALPHA_Pos          (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk          (0xffUL << LTDC_LxDCCR_DCALPHA_Pos)
+#define LTDC_LxDCCR_DCALPHA              LTDC_LxDCCR_DCALPHA_Msk  /*!< default color alphaThese bits configure the default alpha value. */
+
+/* Bit fields for LTDC_LxBFCR register */
+#define LTDC_LxBFCR_BF2_Pos              (0U)
+#define LTDC_LxBFCR_BF2_Msk              (0x7UL << LTDC_LxBFCR_BF2_Pos)
+#define LTDC_LxBFCR_BF2                  LTDC_LxBFCR_BF2_Msk  /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */
+#define LTDC_LxBFCR_BF1_Pos              (8U)
+#define LTDC_LxBFCR_BF1_Msk              (0x7UL << LTDC_LxBFCR_BF1_Pos)
+#define LTDC_LxBFCR_BF1                  LTDC_LxBFCR_BF1_Msk  /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */
+#define LTDC_LxBFCR_BOR_Pos              (16U)
+#define LTDC_LxBFCR_BOR_Msk              (0x1UL << LTDC_LxBFCR_BOR_Pos)
+#define LTDC_LxBFCR_BOR                  LTDC_LxBFCR_BOR_Msk  /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */
+
+/* Bit fields for LTDC_LxBLCR register */
+#define LTDC_LxBLCR_BL_Pos               (0U)
+#define LTDC_LxBLCR_BL_Msk               (0x1fUL << LTDC_LxBLCR_BL_Pos)
+#define LTDC_LxBLCR_BL                   LTDC_LxBLCR_BL_Msk  /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */
+
+/* Bit fields for LTDC_LxPCR register */
+#define LTDC_LxPCR_YCEN_Pos              (3U)
+#define LTDC_LxPCR_YCEN_Msk              (0x1UL << LTDC_LxPCR_YCEN_Pos)
+#define LTDC_LxPCR_YCEN                  LTDC_LxPCR_YCEN_Msk  /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */
+#define LTDC_LxPCR_YCM_Pos               (4U)
+#define LTDC_LxPCR_YCM_Msk               (0x3UL << LTDC_LxPCR_YCM_Pos)
+#define LTDC_LxPCR_YCM                   LTDC_LxPCR_YCM_Msk  /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */
+#define LTDC_LxPCR_YF_Pos                (6U)
+#define LTDC_LxPCR_YF_Msk                (0x1UL << LTDC_LxPCR_YF_Pos)
+#define LTDC_LxPCR_YF                    LTDC_LxPCR_YF_Msk  /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */
+#define LTDC_LxPCR_CBF_Pos               (7U)
+#define LTDC_LxPCR_CBF_Msk               (0x1UL << LTDC_LxPCR_CBF_Pos)
+#define LTDC_LxPCR_CBF                   LTDC_LxPCR_CBF_Msk  /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */
+#define LTDC_LxPCR_OF_Pos                (8U)
+#define LTDC_LxPCR_OF_Msk                (0x1UL << LTDC_LxPCR_OF_Pos)
+#define LTDC_LxPCR_OF                    LTDC_LxPCR_OF_Msk  /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */
+#define LTDC_LxPCR_YREN_Pos              (9U)
+#define LTDC_LxPCR_YREN_Msk              (0x1UL << LTDC_LxPCR_YREN_Pos)
+#define LTDC_LxPCR_YREN                  LTDC_LxPCR_YREN_Msk  /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */
+
+/* Bit fields for LTDC_LxCFBAR register */
+#define LTDC_LxCFBAR_CFBADD_Pos          (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk          (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos)
+#define LTDC_LxCFBAR_CFBADD              LTDC_LxCFBAR_CFBADD_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxCFBLR register */
+#define LTDC_LxCFBLR_CFBLL_Pos           (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk           (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos)
+#define LTDC_LxCFBLR_CFBLL               LTDC_LxCFBLR_CFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_LxCFBLR_CFBP_Pos            (16U)
+#define LTDC_LxCFBLR_CFBP_Msk            (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos)
+#define LTDC_LxCFBLR_CFBP                LTDC_LxCFBLR_CFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxCFBLNR register */
+#define LTDC_LxCFBLNR_CFBLNBR_Pos        (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk        (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
+#define LTDC_LxCFBLNR_CFBLNBR            LTDC_LxCFBLNR_CFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_L1AFBA0R register */
+#define LTDC_L1AFBA0R_AFBADD0_Pos        (0U)
+#define LTDC_L1AFBA0R_AFBADD0_Msk        (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos)
+#define LTDC_L1AFBA0R_AFBADD0            LTDC_L1AFBA0R_AFBADD0_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBA1R register */
+#define LTDC_L1AFBA1R_AFBADD1_Pos        (0U)
+#define LTDC_L1AFBA1R_AFBADD1_Msk        (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos)
+#define LTDC_L1AFBA1R_AFBADD1            LTDC_L1AFBA1R_AFBADD1_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBLR register */
+#define LTDC_L1AFBLR_AFBLL_Pos           (0U)
+#define LTDC_L1AFBLR_AFBLL_Msk           (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos)
+#define LTDC_L1AFBLR_AFBLL               LTDC_L1AFBLR_AFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_L1AFBLR_AFBP_Pos            (16U)
+#define LTDC_L1AFBLR_AFBP_Msk            (0xffffUL << LTDC_L1AFBLR_AFBP_Pos)
+#define LTDC_L1AFBLR_AFBP                LTDC_L1AFBLR_AFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxAFBLNR register */
+#define LTDC_L1AFBLNR_AFBLNBR_Pos        (0U)
+#define LTDC_L1AFBLNR_AFBLNBR_Msk        (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos)
+#define LTDC_L1AFBLNR_AFBLNBR            LTDC_L1AFBLNR_AFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_LxCLUTWR register */
+#define LTDC_LxCLUTWR_BLUE_Pos           (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk           (0xffUL << LTDC_LxCLUTWR_BLUE_Pos)
+#define LTDC_LxCLUTWR_BLUE               LTDC_LxCLUTWR_BLUE_Msk  /*!< blue valueThese bits configure the blue value. */
+#define LTDC_LxCLUTWR_GREEN_Pos          (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk          (0xffUL << LTDC_LxCLUTWR_GREEN_Pos)
+#define LTDC_LxCLUTWR_GREEN              LTDC_LxCLUTWR_GREEN_Msk  /*!< green valueThese bits configure the green value. */
+#define LTDC_LxCLUTWR_RED_Pos            (16U)
+#define LTDC_LxCLUTWR_RED_Msk            (0xffUL << LTDC_LxCLUTWR_RED_Pos)
+#define LTDC_LxCLUTWR_RED                LTDC_LxCLUTWR_RED_Msk  /*!< red valueThese bits configure the red value. */
+#define LTDC_LxCLUTWR_CLUTADD_Pos        (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk        (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos)
+#define LTDC_LxCLUTWR_CLUTADD            LTDC_LxCLUTWR_CLUTADD_Msk  /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */
+
+/* Bit fields for LTDC_LxCYR0R register */
+#define LTDC_LxCYR0R_CR2R_Pos            (0U)
+#define LTDC_LxCYR0R_CR2R_Msk            (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos)
+#define LTDC_LxCYR0R_CR2R                LTDC_LxCYR0R_CR2R_Msk  /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR0R_CB2B_Pos            (16U)
+#define LTDC_LxCYR0R_CB2B_Msk            (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos)
+#define LTDC_LxCYR0R_CB2B                LTDC_LxCYR0R_CB2B_Msk  /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxCYR1R register */
+#define LTDC_LxCYR1R_CR2G_Pos            (0U)
+#define LTDC_LxCYR1R_CR2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos)
+#define LTDC_LxCYR1R_CR2G                LTDC_LxCYR1R_CR2G_Msk  /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR1R_CB2G_Pos            (16U)
+#define LTDC_LxCYR1R_CB2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos)
+#define LTDC_LxCYR1R_CB2G                LTDC_LxCYR1R_CB2G_Msk  /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxFPF0R register */
+#define LTDC_LxFPF0R_APOS_Pos            (0U)
+#define LTDC_LxFPF0R_APOS_Msk            (0x1fUL << LTDC_LxFPF0R_APOS_Pos)
+#define LTDC_LxFPF0R_APOS                LTDC_LxFPF0R_APOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_ALEN_Pos            (5U)
+#define LTDC_LxFPF0R_ALEN_Msk            (0xfUL << LTDC_LxFPF0R_ALEN_Pos)
+#define LTDC_LxFPF0R_ALEN                LTDC_LxFPF0R_ALEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF0R_RPOS_Pos            (9U)
+#define LTDC_LxFPF0R_RPOS_Msk            (0x1fUL << LTDC_LxFPF0R_RPOS_Pos)
+#define LTDC_LxFPF0R_RPOS                LTDC_LxFPF0R_RPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_RLEN_Pos            (14U)
+#define LTDC_LxFPF0R_RLEN_Msk            (0xfUL << LTDC_LxFPF0R_RLEN_Pos)
+#define LTDC_LxFPF0R_RLEN                LTDC_LxFPF0R_RLEN_Msk  /*!< Width of the red component (in bits). */
+
+/* Bit fields for LTDC_LxFPF1R register */
+#define LTDC_LxFPF1R_GPOS_Pos            (0U)
+#define LTDC_LxFPF1R_GPOS_Msk            (0x1fUL << LTDC_LxFPF1R_GPOS_Pos)
+#define LTDC_LxFPF1R_GPOS                LTDC_LxFPF1R_GPOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_GLEN_Pos            (5U)
+#define LTDC_LxFPF1R_GLEN_Msk            (0xfUL << LTDC_LxFPF1R_GLEN_Pos)
+#define LTDC_LxFPF1R_GLEN                LTDC_LxFPF1R_GLEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF1R_BPOS_Pos            (9U)
+#define LTDC_LxFPF1R_BPOS_Msk            (0x1fUL << LTDC_LxFPF1R_BPOS_Pos)
+#define LTDC_LxFPF1R_BPOS                LTDC_LxFPF1R_BPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_BLEN_Pos            (14U)
+#define LTDC_LxFPF1R_BLEN_Msk            (0xfUL << LTDC_LxFPF1R_BLEN_Pos)
+#define LTDC_LxFPF1R_BLEN                LTDC_LxFPF1R_BLEN_Msk  /*!< Width of the red component (in bits). */
+
+#define LTDC_LxFPF1R_PSIZE_Pos            (18U)
+#define LTDC_LxFPF1R_PSIZE_Msk            (0x7UL << LTDC_LxFPF1R_PSIZE_Pos)
+#define LTDC_LxFPF1R_PSIZE                LTDC_LxFPF1R_PSIZE_Msk  /*!< Width of the red component (in bits). */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Memory Cipher Engine (MCE)                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MCE_CR register  ********************/
+#define MCE_CR_GLOCK_Pos               (0U)
+#define MCE_CR_GLOCK_Msk               (0x1UL << MCE_CR_GLOCK_Pos)             /*!< 0x00000001 */
+#define MCE_CR_GLOCK                   MCE_CR_GLOCK_Msk                        /*!< MCE global lock */
+#define MCE_CR_MKLOCK_Pos              (1U)
+#define MCE_CR_MKLOCK_Msk              (0x1UL << MCE_CR_MKLOCK_Pos)            /*!< 0x00000002 */
+#define MCE_CR_MKLOCK                  MCE_CR_MKLOCK_Msk                       /*!< MCE master and fast master keys lock */
+#define MCE_CR_CIPHERSEL_Pos           (4U)
+#define MCE_CR_CIPHERSEL_Msk           (0x3UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000030 */
+#define MCE_CR_CIPHERSEL               MCE_CR_CIPHERSEL_Msk                    /*!< MCE Cipher selection */
+#define MCE_CR_CIPHERSEL_0             (0x1UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000010 */
+#define MCE_CR_CIPHERSEL_1             (0x2UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000020 */
+
+/********************  Bit definition for MCE_SR register  ********************/
+#define MCE_SR_MKVALID_Pos             (0U)
+#define MCE_SR_MKVALID_Msk             (0x1UL << MCE_SR_MKVALID_Pos)           /*!< 0x00000001 */
+#define MCE_SR_MKVALID                 MCE_SR_MKVALID_Msk                      /*!< MCE master key valid flag */
+#define MCE_SR_FMKVALID_Pos            (2U)
+#define MCE_SR_FMKVALID_Msk            (0x1UL << MCE_SR_FMKVALID_Pos)          /*!< 0x00000004 */
+#define MCE_SR_FMKVALID                 MCE_SR_FMKVALID_Msk                    /*!< MCE fast master key valid flag */
+#define MCE_SR_ENCDIS_Pos              (4U)
+#define MCE_SR_ENCDIS_Msk              (0x1UL << MCE_SR_ENCDIS_Pos)            /*!< 0x00000010 */
+#define MCE_SR_ENCDIS                  MCE_SR_ENCDIS_Msk                       /*!< MCE encryption disabled flag */
+
+/********************  Bit definition for MCE_IASR register  ******************/
+#define MCE_IASR_IAEF_Pos              (1U)
+#define MCE_IASR_IAEF_Msk              (0x1UL << MCE_IASR_IAEF_Pos)             /*!< 0x00000002 */
+#define MCE_IASR_IAEF                  MCE_IASR_IAEF_Msk                        /*!< MCE illegal access error flag */
+
+/********************  Bit definition for MCE_IACR register  ******************/
+#define MCE_IACR_IAEF_Pos              (1U)
+#define MCE_IACR_IAEF_Msk              (0x1UL << MCE_IACR_IAEF_Pos)             /*!< 0x00000002 */
+#define MCE_IACR_IAEF                  MCE_IACR_IAEF_Msk                        /*!< MCE illegal access error clear bit */
+
+/********************  Bit definition for MCE_IAIER register  *****************/
+#define MCE_IAIER_IAEIE_Pos            (1U)
+#define MCE_IAIER_IAEIE_Msk            (0x1UL << MCE_IAIER_IAEIE_Pos)           /*!< 0x00000002 */
+#define MCE_IAIER_IAEIE                MCE_IAIER_IAEIE_Msk                      /*!< MCE illegal access error interrupt enable */
+
+/********************  Bit definition for MCE_IADDR register  *****************/
+#define MCE_IADDR_IADD_Pos             (0U)
+#define MCE_IADDR_IADD_Msk             (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_IADDR_IADD                 MCE_IADDR_IADD_Msk                      /*!< MCE illegal access */
+
+/********************  Bit definition for MCE_REGCR register  *****************/
+#define MCE_REGCR_BREN_Pos             (0U)
+#define MCE_REGCR_BREN_Msk             (0x1UL << MCE_REGCR_BREN_Pos)            /*!< 0x00000001 */
+#define MCE_REGCR_BREN                 MCE_REGCR_BREN_Msk                       /*!< MCE base region enable */
+#define MCE_REGCR_CTXID_Pos            (9U)
+#define MCE_REGCR_CTXID_Msk            (0x3UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000600 */
+#define MCE_REGCR_CTXID                MCE_REGCR_CTXID_Msk                      /*!< MCE context ID */
+#define MCE_REGCR_CTXID_0              (0x1UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000200 */
+#define MCE_REGCR_CTXID_1              (0x2UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000400 */
+#define MCE_REGCR_ENC_Pos              (14U)
+#define MCE_REGCR_ENC_Msk              (0x3UL << MCE_REGCR_ENC_Pos)             /*!< 0x0000C000 */
+#define MCE_REGCR_ENC                  MCE_REGCR_ENC_Msk                        /*!< MCE encrypted region */
+#define MCE_REGCR_ENC_0                (0x1UL << MCE_REGCR_ENC_Pos)             /*!< 0x00004000 */
+#define MCE_REGCR_ENC_1                (0x2UL << MCE_REGCR_ENC_Pos)             /*!< 0x00008000 */
+
+/********************  Bit definition for MCE_SADDR register  *****************/
+#define MCE_SADDR_BADDSTART_Pos        (12U)
+#define MCE_SADDR_BADDSTART_Msk        (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos)   /*!< 0xFFFFF000 */
+#define MCE_SADDR_BADDSTART            MCE_SADDR_BADDSTART_Msk                  /*!< MCE region address start */
+
+/********************  Bit definition for MCE_EADDR register  *****************/
+#define MCE_EADDR_BADDEND_Pos          (12U)
+#define MCE_EADDR_BADDEND_Msk          (0xFFFFFUL << MCE_EADDR_BADDEND_Pos)     /*!< 0xFFFFF000 */
+#define MCE_EADDR_BADDEND              MCE_EADDR_BADDEND_Msk                    /*!< MCE region address end */
+
+/********************  Bit definition for MCE_MKEYR0 register  ****************/
+#define MCE_MKEYR0_MKEY_Pos            (0U)
+#define MCE_MKEYR0_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR0_MKEY                MCE_MKEYR0_MKEY_Msk                      /*!< MCE master key, bits [31:0] */
+
+/********************  Bit definition for MCE_MKEYR1 register  ****************/
+#define MCE_MKEYR1_MKEY_Pos            (0U)
+#define MCE_MKEYR1_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR1_MKEY                MCE_MKEYR1_MKEY_Msk                      /*!< MCE master key, bits [63:32] */
+
+/********************  Bit definition for MCE_MKEYR2 register  ****************/
+#define MCE_MKEYR2_MKEY_Pos            (0U)
+#define MCE_MKEYR2_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR2_MKEY                MCE_MKEYR2_MKEY_Msk                      /*!< MCE master key, bits [95:64] */
+
+/********************  Bit definition for MCE_MKEYR3 register  ****************/
+#define MCE_MKEYR3_MKEY_Pos            (0U)
+#define MCE_MKEYR3_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR3_MKEY                MCE_MKEYR3_MKEY_Msk                      /*!< MCE master key, bits [127:96] */
+
+/********************  Bit definition for MCE_MKEYR4 register  ****************/
+#define MCE_MKEYR4_MKEY_Pos            (0U)
+#define MCE_MKEYR4_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR4_MKEY                MCE_MKEYR4_MKEY_Msk                      /*!< MCE master key, bits [159:128] */
+
+/********************  Bit definition for MCE_MKEYR5 register  ****************/
+#define MCE_MKEYR5_MKEY_Pos            (0U)
+#define MCE_MKEYR5_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR5_MKEY                MCE_MKEYR5_MKEY_Msk                      /*!< MCE master key, bits [191:160] */
+
+/********************  Bit definition for MCE_MKEYR6 register  ****************/
+#define MCE_MKEYR6_MKEY_Pos            (0U)
+#define MCE_MKEYR6_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR6_MKEY                MCE_MKEYR6_MKEY_Msk                      /*!< MCE master key, bits [223:192] */
+
+/********************  Bit definition for MCE_MKEYR7 register  ****************/
+#define MCE_MKEYR7_MKEY_Pos            (0U)
+#define MCE_MKEYR7_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR7_MKEY                MCE_MKEYR7_MKEY_Msk                      /*!< MCE master key, bits [255:224] */
+
+/********************  Bit definition for MCE_FMKEYR0 register  ***************/
+#define MCE_FMKEYR0_FMKEY_Pos          (0U)
+#define MCE_FMKEYR0_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR0_FMKEY              MCE_FMKEYR0_FMKEY_Msk                    /*!< MCE fast master key, bits [31:0] */
+
+/********************  Bit definition for MCE_FMKEYR1 register  ***************/
+#define MCE_FMKEYR1_FMKEY_Pos          (0U)
+#define MCE_FMKEYR1_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR1_FMKEY              MCE_FMKEYR1_FMKEY_Msk                    /*!< MCE fast master key, bits [63:32] */
+
+/********************  Bit definition for MCE_FMKEYR2 register  ***************/
+#define MCE_FMKEYR2_FMKEY_Pos          (0U)
+#define MCE_FMKEYR2_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR2_FMKEY              MCE_FMKEYR2_FMKEY_Msk                    /*!< MCE fast master key, bits [95:64] */
+
+/********************  Bit definition for MCE_FMKEYR3 register  ***************/
+#define MCE_FMKEYR3_FMKEY_Pos          (0U)
+#define MCE_FMKEYR3_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR3_FMKEY              MCE_FMKEYR3_FMKEY_Msk                    /*!< MCE fast master key, bits [127:96] */
+
+/********************  Bit definition for MCE_FMKEYR4 register  ****************/
+#define MCE_FMKEYR4_FMKEY_Pos          (0U)
+#define MCE_FMKEYR4_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR4_FMKEY              MCE_FMKEYR4_FMKEY_Msk                    /*!< MCE fast master key, bits [159:128] */
+
+/********************  Bit definition for MCE_FMKEYR5 register  ****************/
+#define MCE_FMKEYR5_FMKEY_Pos          (0U)
+#define MCE_FMKEYR5_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR5_FMKEY              MCE_FMKEYR5_FMKEY_Msk                    /*!< MCE fast master key, bits [191:160] */
+
+/********************  Bit definition for MCE_FMKEYR6 register  ****************/
+#define MCE_FMKEYR6_FMKEY_Pos          (0U)
+#define MCE_FMKEYR6_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR6_FMKEY              MCE_FMKEYR6_FMKEY_Msk                    /*!< MCE fast master key, bits [223:192] */
+
+/********************  Bit definition for MCE_FMKEYR7 register  ****************/
+#define MCE_FMKEYR7_FMKEY_Pos          (0U)
+#define MCE_FMKEYR7_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR7_FMKEY              MCE_FMKEYR7_FMKEY_Msk                    /*!< MCE fast master key, bits [255:224] */
+
+/********************  Bit definition for MCE_CCCFGR register  ****************/
+#define MCE_CCCFGR_CCEN_Pos             (0U)
+#define MCE_CCCFGR_CCEN_Msk             (0x1UL << MCE_CCCFGR_CCEN_Pos)          /*!< 0x00000001 */
+#define MCE_CCCFGR_CCEN                 MCE_CCCFGR_CCEN_Msk                     /*!< MCE cipher context enable */
+#define MCE_CCCFGR_CCLOCK_Pos           (1U)
+#define MCE_CCCFGR_CCLOCK_Msk           (0x1UL << MCE_CCCFGR_CCLOCK_Pos)        /*!< 0x00000002 */
+#define MCE_CCCFGR_CCLOCK               MCE_CCCFGR_CCLOCK_Msk                   /*!< MCE cipher context lock */
+#define MCE_CCCFGR_KEYLOCK_Pos          (2U)
+#define MCE_CCCFGR_KEYLOCK_Msk          (0x1UL << MCE_CCCFGR_KEYLOCK_Pos)       /*!< 0x00000004 */
+#define MCE_CCCFGR_KEYLOCK              MCE_CCCFGR_KEYLOCK_Msk                  /*!< MCE cipher context key lock */
+#define MCE_CCCFGR_MODE_Pos             (4U)
+#define MCE_CCCFGR_MODE_Msk             (0x3UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000030 */
+#define MCE_CCCFGR_MODE                 MCE_CCCFGR_MODE_Msk                     /*!< MCE authorized cipher mode */
+#define MCE_CCCFGR_MODE_0               (0x1UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000010 */
+#define MCE_CCCFGR_MODE_1               (0x2UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000020 */
+#define MCE_CCCFGR_KEYCRC_Pos           (8U)
+#define MCE_CCCFGR_KEYCRC_Msk           (0xFFUL << MCE_CCCFGR_KEYCRC_Pos)       /*!< 0x0000FF00 */
+#define MCE_CCCFGR_KEYCRC               MCE_CCCFGR_KEYCRC_Msk                   /*!< MCE cipher context key CRC */
+#define MCE_CCCFGR_VERSION_Pos          (16U)
+#define MCE_CCCFGR_VERSION_Msk          (0xFFFFUL << MCE_CCCFGR_VERSION_Pos)    /*!< 0xFFFF0000 */
+#define MCE_CCCFGR_VERSION              MCE_CCCFGR_VERSION_Msk                  /*!< MCE cipher context version */
+
+/********************  Bit definition for MCE_CCNR0 register  *****************/
+#define MCE_CCNR0_SCNONCE_Pos          (0U)
+#define MCE_CCNR0_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_CCNR0_SCNONCE              MCE_CCNR0_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [31:0] */
+
+/********************  Bit definition for MCE_CCNR1 register  ****************/
+#define MCE_CCNR1_SCNONCE_Pos          (0U)
+#define MCE_CCNR1_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_CCNR1_SCNONCE              MCE_CCNR1_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [63:32] */
+
+/********************  Bit definition for MCE_CCKEYR0 register  ***************/
+#define MCE_CCKEYR0_KEY_Pos            (0U)
+#define MCE_CCKEYR0_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR0_KEY                MCE_CCKEYR0_KEY_Msk                      /*!< MCE cipher context key, bits [31:0] */
+
+/********************  Bit definition for MCE_CCKEYR1 register  ***************/
+#define MCE_CCKEYR1_KEY_Pos            (0U)
+#define MCE_CCKEYR1_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR1_KEY                MCE_CCKEYR1_KEY_Msk                      /*!< MCE fast master key, bits [63:32] */
+
+/********************  Bit definition for MCE_CCKEYR2 register  ***************/
+#define MCE_CCKEYR2_KEY_Pos            (0U)
+#define MCE_CCKEYR2_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR2_KEY                MCE_CCKEYR2_KEY_Msk                      /*!< MCE fast master key, bits [95:64] */
+
+/********************  Bit definition for MCE_CCKEYR3 register  ***************/
+#define MCE_CCKEYR3_KEY_Pos            (0U)
+#define MCE_CCKEYR3_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR3_KEY                MCE_CCKEYR3_KEY_Msk                      /*!< MCE fast master key, bits [127:96] */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDF/ADF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for MDF/ADF_GCR register  ****************/
+#define MDF_GCR_TRGO_Pos                    (0U)
+#define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
+#define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!< Trigger output control */
+#define MDF_GCR_ILVNB_Pos                   (4U)
+#define MDF_GCR_ILVNB_Msk                   (0xFUL << MDF_GCR_ILVNB_Pos)            /*!< 0x000000F0 */
+#define MDF_GCR_ILVNB                       MDF_GCR_ILVNB_Msk                       /*!< Interleaved Number */
+
+/*******************  Bit definition for MDF/ADF_CKGCR register  ********************/
+#define MDF_CKGCR_CKDEN_Pos                 (0U)
+#define MDF_CKGCR_CKDEN_Msk                 (0x1UL << MDF_CKGCR_CKDEN_Pos)          /*!< 0x00000001 */
+#define MDF_CKGCR_CKDEN                     MDF_CKGCR_CKDEN_Msk                     /*!<CKGEN diveders enable */
+#define MDF_CKGCR_CCK0EN_Pos                (1U)
+#define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
+#define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!<CCK0 clock enable */
+#define MDF_CKGCR_CCK1EN_Pos                (2U)
+#define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
+#define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!<CCK1 clock enable */
+#define MDF_CKGCR_CKGMOD_Pos                (4U)
+#define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
+#define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!<Clock genartor mode */
+#define MDF_CKGCR_CCK0DIR_Pos               (5U)
+#define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
+#define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!<CCK0 clock direction */
+#define MDF_CKGCR_CCK1DIR_Pos               (6U)
+#define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
+#define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!<CCK1 clock direction */
+#define MDF_CKGCR_TRGSENS_Pos               (8U)
+#define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
+#define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!<CKGEN trigger sensitivity selection */
+#define MDF_CKGCR_TRGSRC_Pos                (12U)
+#define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
+#define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!<Digital Filter trigger signal selection */
+#define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
+#define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
+#define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
+#define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
+#define MDF_CKGCR_CCKDIV_Pos                (16U)
+#define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
+#define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!<Divider to control the MDF_CCK clock */
+#define MDF_CKGCR_PROCDIV_Pos               (24U)
+#define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
+#define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!<Divider to control the serial interface clock */
+#define MDF_CKGCR_CCKACTIVE_Pos             (31U)
+#define MDF_CKGCR_CCKACTIVE_Msk             (0x1UL << MDF_CKGCR_CCKACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_CKGCR_CCKACTIVE                 MDF_CKGCR_CCKACTIVE_Msk                 /*!<Clock generator active flag */
+
+/*******************  Bit definition for MDF/ADF_OR register  ********************/
+#define MDF_OR_OPTION_Pos                   (0U)
+#define MDF_OR_OPTION_Msk                   (0xFFFFFFFFUL << MDF_OR_OPTION_Pos)     /*!< 0xFFFFFFFF */
+#define MDF_OR_OPTION                       MDF_OR_OPTION_Msk                       /*!<Option Control Bits */
+
+/*******************  Bit definition for MDF/ADF_SITFxCR register  ********************/
+#define MDF_SITFCR_SITFEN_Pos               (0U)
+#define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
+#define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!<Serial interface enable */
+#define MDF_SITFCR_SCKSRC_Pos               (1U)
+#define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
+#define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!<Serial clock source */
+#define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SITFMOD_Pos              (4U)
+#define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
+#define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!<Serial interface type */
+#define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
+#define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
+#define MDF_SITFCR_STH_Pos                  (8U)
+#define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
+#define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!<Manchester Symbol threshold / SPI threshold */
+#define MDF_SITFCR_SITFACTIVE_Pos           (31U)
+#define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
+#define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!<Serial interface active flag */
+
+/*******************  Bit definition for MDF/ADF_BSMXxCR register  ********************/
+#define MDF_BSMXCR_BSSEL_Pos                (0U)
+#define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
+#define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!<Bit Streal selection */
+#define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
+#define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
+#define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
+#define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
+#define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
+#define MDF_BSMXCR_BSMXACTIVATE_Pos         (31U)
+#define MDF_BSMXCR_BSMXACTIVATE_Msk         (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos)  /*!< 0x80000000 */
+#define MDF_BSMXCR_BSMXACTIVATE             MDF_BSMXCR_BSMXACTIVATE_Msk             /*!<Bit Streal activation flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCR register  ********************/
+#define MDF_DFLTCR_DFLTEN_Pos               (0U)
+#define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!<Digital filter enable */
+#define MDF_DFLTCR_DMAEN_Pos                (1U)
+#define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
+#define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!<DMA request enable */
+#define MDF_DFLTCR_FTH_Pos                  (2U)
+#define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
+#define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!<RXFIFO Threshold selection */
+#define MDF_DFLTCR_ACQMOD_Pos               (4U)
+#define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!<Digital filter trigger mode */
+#define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
+#define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
+#define MDF_DFLTCR_TRGSENS_Pos              (8U)
+#define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!<Digital filter trigger sensitivity selection */
+#define MDF_DFLTCR_TRGSRC_Pos               (12U)
+#define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!<Digital filter trigger signal selection */
+#define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
+#define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
+#define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
+#define MDF_DFLTCR_SNPSFMT_Pos              (16U)
+#define MDF_DFLTCR_SNPSFMT_Msk              (0x1UL << MDF_DFLTCR_SNPSFMT_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_SNPSFMT                  MDF_DFLTCR_SNPSFMT_Msk                  /*!<SnapShot Data format */
+#define MDF_DFLTCR_NBDIS_Pos                (20U)
+#define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!<Number of samples to be discard */
+#define MDF_DFLTCR_DFLTRUN_Pos              (30U)
+#define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!<Digital filter run status flag */
+#define MDF_DFLTCR_DFLTACTIVE_Pos           (31U)
+#define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!<Digital filter active flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCICR register  ********************/
+#define MDF_DFLTCICR_DATSRC_Pos             (0U)
+#define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!<Source Data for the digital filter */
+#define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTCICR_CICMOD_Pos             (4U)
+#define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
+#define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!<Select the CIC Mode*/
+#define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
+#define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
+#define MDF_DFLTCICR_MCICD_Pos              (8U)
+#define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
+#define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!<CIC decimation ratio selection*/
+#define MDF_DFLTCICR_SCALE_Pos              (20U)
+#define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
+#define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!<Scaling factor selection*/
+
+/*******************  Bit definition for MDF/ADF_DFLTxRSFR register  ********************/
+#define MDF_DFLTRSFR_RSFLTBYP_Pos           (0U)
+#define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
+#define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!<Reshape filter bypass*/
+#define MDF_DFLTRSFR_RSFLTD_Pos             (4U)
+#define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!<Reshape filter decimation ratio*/
+#define MDF_DFLTRSFR_HPFBYP_Pos             (7U)
+#define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!<High-pass filter bypass*/
+#define MDF_DFLTRSFR_HPFC_Pos               (8U)
+#define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!<High-pass filter cut-off frequency*/
+#define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
+#define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)
+
+/*******************  Bit definition for MDF/ADF_DFLTxINTR register  ********************/
+#define MDF_DFLTINTR_INTDIV_Pos             (0U)
+#define MDF_DFLTINTR_INTDIV_Msk             (0x3UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTINTR_INTDIV                 MDF_DFLTINTR_INTDIV_Msk                 /*!<Integrator output dividion*/
+#define MDF_DFLTINTR_INTDIV_0               (0x1UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTINTR_INTDIV_1               (0x2UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTINTR_INTVAL_Pos             (4U)
+#define MDF_DFLTINTR_INTVAL_Msk             (0x7FUL << MDF_DFLTINTR_INTVAL_Pos)     /*!< 0x000007F0 */
+#define MDF_DFLTINTR_INTVAL                 MDF_DFLTINTR_INTVAL_Msk                 /*!<Integrator value selection*/
+
+/*******************  Bit definition for MDF/ADF_OLDxCR register  ********************/
+#define MDF_OLDCR_OLDEN_Pos                 (0U)
+#define MDF_OLDCR_OLDEN_Msk                 (0x1UL << MDF_OLDCR_OLDEN_Pos)          /*!< 0x00000001 */
+#define MDF_OLDCR_OLDEN                     MDF_OLDCR_OLDEN_Msk                     /*!<OLD enable*/
+#define MDF_OLDCR_THINB_Pos                 (1U)
+#define MDF_OLDCR_THINB_Msk                 (0x1UL << MDF_OLDCR_THINB_Pos)          /*!< 0x00000002 */
+#define MDF_OLDCR_THINB                     MDF_OLDCR_THINB_Msk                     /*!<OLD threshold in band*/
+#define MDF_OLDCR_BKOLD_Pos                 (4U)
+#define MDF_OLDCR_BKOLD_Msk                 (0xFUL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x000000F0 */
+#define MDF_OLDCR_BKOLD                     MDF_OLDCR_BKOLD_Msk                     /*!<Bteak signal assignment for OLD*/
+#define MDF_OLDCR_BKOLD_0                   (0x1UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000010 */
+#define MDF_OLDCR_BKOLD_1                   (0x2UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000020 */
+#define MDF_OLDCR_BKOLD_2                   (0x4UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000040 */
+#define MDF_OLDCR_BKOLD_3                   (0x8UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000080 */
+#define MDF_OLDCR_ACICN_Pos                 (12U)
+#define MDF_OLDCR_ACICN_Msk                 (0x3UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00003000 */
+#define MDF_OLDCR_ACICN                     MDF_OLDCR_ACICN_Msk                     /*!<OLD CIC order selection*/
+#define MDF_OLDCR_ACICN_0                   (0x1UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00001000 */
+#define MDF_OLDCR_ACICN_1                   (0x2UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00002000 */
+#define MDF_OLDCR_ACICD_Pos                 (17U)
+#define MDF_OLDCR_ACICD_Msk                 (0x1FUL << MDF_OLDCR_ACICD_Pos)         /*!< 0x003E0000 */
+#define MDF_OLDCR_ACICD                     MDF_OLDCR_ACICD_Msk                     /*!<OLD CIC decimation ratio selection*/
+#define MDF_OLDCR_OLDACTIVE_Pos             (31U)
+#define MDF_OLDCR_OLDACTIVE_Msk             (0x1UL << MDF_OLDCR_OLDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_OLDCR_OLDACTIVE                 MDF_OLDCR_OLDACTIVE_Msk                 /*!<OLD active flag*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHLR register  ********************/
+#define MDF_OLDTHLR_OLDTHL_Pos              (0U)
+#define MDF_OLDTHLR_OLDTHL_Msk              (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHLR_OLDTHL                  MDF_OLDTHLR_OLDTHL_Msk                  /*!<OLD Low threshold value*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHHR register  ********************/
+#define MDF_OLDTHHR_OLDTHH_Pos              (0U)
+#define MDF_OLDTHHR_OLDTHH_Msk              (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHHR_OLDTHH                  MDF_OLDTHHR_OLDTHH_Msk                  /*!<OLD High threshold value*/
+
+/*******************  Bit definition for MDF/ADF_DLYxCR register  ********************/
+#define MDF_DLYCR_SKPDLY_Pos                (0U)
+#define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
+#define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!<Delay to apply to a bitstream*/
+#define MDF_DLYCR_SKPBF_Pos                 (31U)
+#define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
+#define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!<DSkip Busy Flag*/
+
+/*******************  Bit definition for MDF/ADF_SCDxCR register  ********************/
+#define MDF_SCDCR_SCDEN_Pos                 (0U)
+#define MDF_SCDCR_SCDEN_Msk                 (0x1UL << MDF_SCDCR_SCDEN_Pos)          /*!< 0x00000001 */
+#define MDF_SCDCR_SCDEN                     MDF_SCDCR_SCDEN_Msk                     /*!<Short circuit detector enable*/
+#define MDF_SCDCR_BKSCD_Pos                 (4U)
+#define MDF_SCDCR_BKSCD_Msk                 (0xFUL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x000000F0 */
+#define MDF_SCDCR_BKSCD                     MDF_SCDCR_BKSCD_Msk                     /*!<Break signal assignment to short circuit detector */
+#define MDF_SCDCR_BKSCD_0                   (0x1UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000010 */
+#define MDF_SCDCR_BKSCD_1                   (0x2UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000020 */
+#define MDF_SCDCR_BKSCD_2                   (0x4UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000040 */
+#define MDF_SCDCR_BKSCD_3                   (0x8UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000080 */
+#define MDF_SCDCR_SCDT_Pos                  (12U)
+#define MDF_SCDCR_SCDT_Msk                  (0xFFUL << MDF_SCDCR_SCDT_Pos)          /*!< 0x00000FF00 */
+#define MDF_SCDCR_SCDT                      MDF_SCDCR_SCDT_Msk                      /*!<Short circuit detector threshold*/
+#define MDF_SCDCR_SCDACTIVE_Pos             (31U)
+#define MDF_SCDCR_SCDACTIVE_Msk             (0x1UL << MDF_SCDCR_SCDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SCDCR_SCDACTIVE                 MDF_SCDCR_SCDACTIVE_Msk                 /*!<Short circuit detector active flag*/
+
+/*******************  Bit definition for MDF/ADF_DFLTIER register  ********************/
+#define MDF_DFLTIER_FTHIE_Pos               (0U)
+#define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!<RXFIFO threshold interrupt enable*/
+#define MDF_DFLTIER_DOVRIE_Pos              (1U)
+#define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
+#define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!<Data overflow interrupt enable*/
+#define MDF_DFLTIER_SSDRIE_Pos              (2U)
+#define MDF_DFLTIER_SSDRIE_Msk              (0x1UL << MDF_DFLTIER_SSDRIE_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTIER_SSDRIE                  MDF_DFLTIER_SSDRIE_Msk                  /*!<Snapshot data ready interrupt enable*/
+#define MDF_DFLTIER_OLDIE_Pos               (4U)
+#define MDF_DFLTIER_OLDIE_Msk               (0x1UL << MDF_DFLTIER_OLDIE_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTIER_OLDIE                   MDF_DFLTIER_OLDIE_Msk                   /*!<OLD interrupt enable*/
+#define MDF_DFLTIER_SSOVRIE_Pos             (7U)
+#define MDF_DFLTIER_SSOVRIE_Msk             (0x1UL << MDF_DFLTIER_SSOVRIE_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTIER_SSOVRIE                 MDF_DFLTIER_SSOVRIE_Msk                 /*!<Snapshot overrun interrupt enable*/
+#define MDF_DFLTIER_SCDIE_Pos               (8U)
+#define MDF_DFLTIER_SCDIE_Msk               (0x1UL << MDF_DFLTIER_SCDIE_Pos)        /*!< 0x00000100 */
+#define MDF_DFLTIER_SCDIE                   MDF_DFLTIER_SCDIE_Msk                   /*!<Short circuit dtector interrupt enable*/
+#define MDF_DFLTIER_SATIE_Pos               (9U)
+#define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
+#define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!<Saturation detection interrupt enable*/
+#define MDF_DFLTIER_CKABIE_Pos              (10U)
+#define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
+#define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!<Clock absence detection interrupt enable*/
+#define MDF_DFLTIER_RFOVRIE_Pos             (11U)
+#define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
+#define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!<reshape filter overrun interrupt enable*/
+#define MDF_DFLTIER_SDDETIE_Pos             (12U)
+#define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
+#define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!<SAD interrupt enable*/
+#define MDF_DFLTIER_SDLVLIE_Pos             (13U)
+#define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
+#define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!<Sound level value ready interrupt enable*/
+
+/*******************  Bit definition for MDF/ADF_DFLTISR register  ********************/
+#define MDF_DFLTISR_FTHF_Pos                (0U)
+#define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
+#define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!<RXFIFO threshold interrupt flag*/
+#define MDF_DFLTISR_DOVRF_Pos               (1U)
+#define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
+#define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!<Data overflow interrupt flag*/
+#define MDF_DFLTISR_SSDRF_Pos               (2U)
+#define MDF_DFLTISR_SSDRF_Msk               (0x1UL << MDF_DFLTISR_SSDRF_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTISR_SSDRF                   MDF_DFLTISR_SSDRF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_RXNEF_Pos               (3U)
+#define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
+#define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_OLDF_Pos                (4U)
+#define MDF_DFLTISR_OLDF_Msk                (0x1UL << MDF_DFLTISR_OLDF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_OLDF                    MDF_DFLTISR_OLDF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THLF_Pos                (5U)
+#define MDF_DFLTISR_THLF_Msk                (0x1UL << MDF_DFLTISR_THLF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THLF                    MDF_DFLTISR_THLF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THHF_Pos                (6U)
+#define MDF_DFLTISR_THHF_Msk                (0x1UL << MDF_DFLTISR_THHF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THHF                    MDF_DFLTISR_THHF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_SSOVRF_Pos              (7U)
+#define MDF_DFLTISR_SSOVRF_Msk              (0x1UL << MDF_DFLTISR_SSOVRF_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTISR_SSOVRF                  MDF_DFLTISR_SSOVRF_Msk                  /*!<Snapshot overrun interrupt flag*/
+#define MDF_DFLTISR_SCDF_Pos                (8U)
+#define MDF_DFLTISR_SCDF_Msk                (0x1UL << MDF_DFLTISR_SCDF_Pos)         /*!< 0x00000100 */
+#define MDF_DFLTISR_SCDF                    MDF_DFLTISR_SCDF_Msk                    /*!<Short circuit dtector interrupt flag*/
+#define MDF_DFLTISR_SATF_Pos                (9U)
+#define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
+#define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!<Saturation detection interrupt flag*/
+#define MDF_DFLTISR_CKABF_Pos               (10U)
+#define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
+#define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!<Clock absence detection interrupt flag*/
+#define MDF_DFLTISR_RFOVRF_Pos              (11U)
+#define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
+#define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!<reshape filter overrun interrupt flag*/
+#define MDF_DFLTISR_SDDETF_Pos              (12U)
+#define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!<SAD interrupt flag*/
+#define MDF_DFLTISR_SDLVLF_Pos              (13U)
+#define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
+#define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!<Sound level value ready interrupt flag*/
+
+/*******************  Bit definition for MDF/ADF_OECCR register  ********************/
+#define MDF_OECCR_OFFSET_Pos                (0U)
+#define MDF_OECCR_OFFSET_Msk                (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos)   /*!< 0x03FFFFFF */
+#define MDF_OECCR_OFFSET                    MDF_OECCR_OFFSET_Msk                    /*!<Short circuit detector enable*/
+
+/*******************  Bit definition for MDF/ADF_SADCR register  ********************/
+#define MDF_SADCR_SADEN_Pos                 (0U)
+#define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
+#define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!<SAD enable*/
+#define MDF_SADCR_DATCAP_Pos                (1U)
+#define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
+#define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!<SAD data capture mode*/
+#define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
+#define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
+#define MDF_SADCR_DETCFG_Pos                (3U)
+#define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
+#define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!<SAD trigger event configuration*/
+#define MDF_SADCR_SADST_Pos                 (4U)
+#define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
+#define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!<SAD state*/
+#define MDF_SADCR_HYSTEN_Pos                (7U)
+#define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
+#define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!<Hysteresis enable*/
+#define MDF_SADCR_FRSIZE_Pos                (8U)
+#define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
+#define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!<Frame size*/
+#define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
+#define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
+#define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
+#define MDF_SADCR_SADMOD_Pos                (12U)
+#define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
+#define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!<SAD working mode*/
+#define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
+#define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
+#define MDF_SADCR_SADACTIVE_Pos             (31U)
+#define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!<SAD active flag*/
+
+/*******************  Bit definition for MDF/ADF_SADCFGR register  ********************/
+#define MDF_SADCFGR_SNTHR_Pos               (0U)
+#define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
+#define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!<Signal to noise threshold*/
+#define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
+#define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
+#define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
+#define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
+#define MDF_SADCFGR_ANSLP_Pos               (4U)
+#define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
+#define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!<Ambiant noise slope control*/
+#define MDF_SADCFGR_LFRNB_Pos               (8U)
+#define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
+#define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!<Number of learning frames*/
+#define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
+#define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
+#define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
+#define MDF_SADCFGR_HGOVR_Pos               (12U)
+#define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
+#define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!<Hangover time window*/
+#define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
+#define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
+#define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
+#define MDF_SADCFGR_ANMIN_Pos               (16U)
+#define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
+#define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!<Hangover time window*/
+
+/*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
+#define MDF_SADSDLVR_SDLVL_Pos              (0U)
+#define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!<Short term sound level*/
+
+/*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
+#define MDF_SADANLVR_ANLVL_Pos              (0U)
+#define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!<Ambiant noise level estimation*/
+
+/*******************  Bit definition for MDF/ADF_SNPSDR register  ********************/
+#define MDF_SNPSDR_MCICDC_Pos               (0U)
+#define MDF_SNPSDR_MCICDC_Msk               (0x1FFUL << MDF_SNPSDR_MCICDC_Pos)      /*!< 0x000001FF */
+#define MDF_SNPSDR_MCICDC                   MDF_SNPSDR_MCICDC_Msk                   /*!<MCIC decimation counter*/
+#define MDF_SNPSDR_EXTSDR_Pos               (9U)
+#define MDF_SNPSDR_EXTSDR_Msk               (0x7FUL << MDF_SNPSDR_EXTSDR_Pos)       /*!< 0x0000FE00 */
+#define MDF_SNPSDR_EXTSDR                   MDF_SNPSDR_EXTSDR_Msk                   /*!<Extended data size*/
+#define MDF_SNPSDR_SDR_Pos                  (16U)
+#define MDF_SNPSDR_SDR_Msk                  (0xFFFFUL << MDF_SNPSDR_SDR_Pos)        /*!< 0xFFFF0000 */
+#define MDF_SNPSDR_SDR                      MDF_SNPSDR_SDR_Msk                      /*!<Extended data size*/
+
+/*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
+#define MDF_DFLTDR_DR_Pos                   (8U)
+#define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
+#define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!<MCIC decimation counter*/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDIOS                                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Public Key Accelerator (PKA)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PKA_CR register  *********************/
+#define PKA_CR_EN_Pos                       (0U)
+#define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
+#define PKA_CR_EN                           PKA_CR_EN_Msk                           /*!< PKA enable */
+#define PKA_CR_START_Pos                    (1U)
+#define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
+#define PKA_CR_START                        PKA_CR_START_Msk                        /*!< Start operation */
+#define PKA_CR_MODE_Pos                     (8U)
+#define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
+#define PKA_CR_MODE                         PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
+#define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
+#define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
+#define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
+#define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
+#define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
+#define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
+#define PKA_CR_PROCENDIE_Pos                (17U)
+#define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
+#define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
+#define PKA_CR_RAMERRIE_Pos                 (19U)
+#define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
+#define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
+#define PKA_CR_ADDRERRIE_Pos                (20U)
+#define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
+#define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                    /*!< Address error interrupt enable */
+#define PKA_CR_OPERRIE_Pos                  (21U)
+#define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)           /*!< 0x00200000 */
+#define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                      /*!< Operation Error interrupt enable */
+
+/*******************  Bit definition for PKA_SR register  *********************/
+#define PKA_SR_INITOK_Pos                   (0U)
+#define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)            /*!< 0x00000001 */
+#define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                       /*!< PKA initialisation flag */
+#define PKA_SR_BUSY_Pos                     (16U)
+#define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
+#define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
+#define PKA_SR_PROCENDF_Pos                 (17U)
+#define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
+#define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
+#define PKA_SR_RAMERRF_Pos                  (19U)
+#define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
+#define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
+#define PKA_SR_ADDRERRF_Pos                 (20U)
+#define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
+#define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
+#define PKA_SR_OPERRF_Pos                   (21U)
+#define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)            /*!< 0x00200000 */
+#define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                       /*!< PKA operation Error flag*/
+
+/*******************  Bit definition for PKA_CLRFR register  ******************/
+#define PKA_CLRFR_PROCENDFC_Pos             (17U)
+#define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
+#define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
+#define PKA_CLRFR_RAMERRFC_Pos              (19U)
+#define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
+#define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
+#define PKA_CLRFR_ADDRERRFC_Pos             (20U)
+#define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
+#define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
+#define PKA_CLRFR_OPERRFC_Pos               (21U)
+#define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)        /*!< 0x00200000 */
+#define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                   /*!< Clear PKA operation Error flag*/
+
+/*******************  Bits definition for PKA RAM  *************************/
+#define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */
+
+/* Compute Montgomery parameter input data */
+#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Compute Montgomery parameter output data */
+#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */
+
+/* Compute modular exponentiation input data */
+#define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
+#define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+#define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
+#define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
+#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */
+
+/* Compute modular exponentiation output data */
+#define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */
+
+/* Compute ECC scalar multiplication input data */
+#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */
+
+/* Compute ECC scalar multiplication output data */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
+
+/* Point check input data */
+#define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+
+/* Point check output data */
+#define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+
+/* ECDSA signature input data */
+#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
+#define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA signature output data */
+#define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */
+
+
+/* ECDSA verification input data */
+#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
+#define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA verification output data */
+#define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* RSA CRT exponentiation input data */
+#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
+#define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
+#define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
+#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+
+/* RSA CRT exponentiation output data */
+#define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular reduction input data */
+#define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
+#define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
+#define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
+#define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Modular reduction output data */
+#define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic addition input data */
+#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic addition output data */
+#define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic subtraction input data */
+#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic subtraction output data */
+#define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic multiplication input data */
+#define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic multiplication output data */
+#define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Comparison input data */
+#define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Comparison output data */
+#define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular addition input data */
+#define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
+
+/* Modular addition output data */
+#define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular inversion input data */
+#define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
+
+/* Modular inversion output data */
+#define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular subtraction input data */
+#define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
+
+/* Modular subtraction output data */
+#define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Montgomery multiplication input data */
+#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
+
+/* Montgomery multiplication output data */
+#define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Generic Arithmetic input data */
+#define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
+
+/* Generic Arithmetic output data */
+#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)   /*!< Output result for arithmetic operations */
+
+/* Compute ECC complete addition input data */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)   /*!< Input Modulus number of bits */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Z coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC complete addition output data */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Z coordinate */
+
+/* Compute ECC double base ladder input data */
+#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS  ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN         ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF              ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER            ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X             ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y             ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z             ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X             ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y             ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z             ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC double base ladder output data */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)      /*!< Output result X coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y          ((0x05D0UL - PKA_RAM_OFFSET)>>2)      /*!< Output result Y coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR             ((0x0520UL - PKA_RAM_OFFSET)>>2)      /*!< Output result error */
+
+/* Compute ECC projective to affine conversion input data */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)  /*!< Input Modulus number of bits */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)  /*!< Input modulus GF(p) */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X               ((0x0D60UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P X coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y               ((0x0DB8UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Y coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z               ((0x0E10UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Z coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2   ((0x04C8UL - PKA_RAM_OFFSET)>>2)  /*!< Input storage area for Montgomery parameter */
+
+/* Compute ECC projective to affine conversion output data */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X      ((0x0578UL - PKA_RAM_OFFSET)>>2)         /*!< Output result x affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y      ((0x05D0UL - PKA_RAM_OFFSET)>>2)         /*!< Output result y affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR         ((0x0680UL - PKA_RAM_OFFSET)>>2)         /*!< Output result error */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                Parallel Synchronous Slave Interface (PSSI )                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PSSI_CR register  *******************/
+#define PSSI_CR_CKPOL_Pos                   (5U)
+#define PSSI_CR_CKPOL_Msk                   (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
+#define PSSI_CR_CKPOL                       PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
+#define PSSI_CR_DEPOL_Pos                   (6U)
+#define PSSI_CR_DEPOL_Msk                   (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
+#define PSSI_CR_DEPOL                       PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
+#define PSSI_CR_RDYPOL_Pos                  (8U)
+#define PSSI_CR_RDYPOL_Msk                  (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
+#define PSSI_CR_RDYPOL                      PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
+#define PSSI_CR_EDM_Pos                     (10U)
+#define PSSI_CR_EDM_Msk                     (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define PSSI_CR_EDM                         PSSI_CR_EDM_Msk                         /*!< Extended data mode */
+#define PSSI_CR_ENABLE_Pos                  (14U)
+#define PSSI_CR_ENABLE_Msk                  (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define PSSI_CR_ENABLE                      PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
+#define PSSI_CR_DERDYCFG_Pos                (18U)
+#define PSSI_CR_DERDYCFG_Msk                (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
+#define PSSI_CR_DERDYCFG                    PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
+#define PSSI_CR_CKSRC_Pos                   (29U)
+#define PSSI_CR_CKSRC_Msk                   (0x1UL << PSSI_CR_CKSRC_Pos)            /*!< 0x20000000 */
+#define PSSI_CR_CKSRC                       PSSI_CR_CKSRC_Msk                       /*!< Clock source */
+#define PSSI_CR_DMAEN_Pos                   (30U)
+#define PSSI_CR_DMAEN_Msk                   (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
+#define PSSI_CR_DMAEN                       PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
+#define PSSI_CR_OUTEN_Pos                   (31U)
+#define PSSI_CR_OUTEN_Msk                   (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
+#define PSSI_CR_OUTEN                       PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */
+
+/********************  Bit definition for PSSI_SR register  *******************/
+#define PSSI_SR_RTT4B_Pos                   (2U)
+#define PSSI_SR_RTT4B_Msk                   (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
+#define PSSI_SR_RTT4B                       PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
+#define PSSI_SR_RTT1B_Pos                   (3U)
+#define PSSI_SR_RTT1B_Msk                   (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
+#define PSSI_SR_RTT1B                       PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */
+
+/********************  Bit definition for PSSI_RIS register  *******************/
+#define PSSI_RIS_OVR_RIS_Pos                (1U)
+#define PSSI_RIS_OVR_RIS_Msk                (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define PSSI_RIS_OVR_RIS                    PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */
+
+/********************  Bit definition for PSSI_IER register  *******************/
+#define PSSI_IER_OVR_IE_Pos                 (1U)
+#define PSSI_IER_OVR_IE_Msk                 (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define PSSI_IER_OVR_IE                     PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */
+
+/********************  Bit definition for PSSI_MIS register  *******************/
+#define PSSI_MIS_OVR_MIS_Pos                (1U)
+#define PSSI_MIS_OVR_MIS_Msk                (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define PSSI_MIS_OVR_MIS                    PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */
+
+/********************  Bit definition for PSSI_ICR register  *******************/
+#define PSSI_ICR_OVR_ISC_Pos                (1U)
+#define PSSI_ICR_OVR_ISC_Msk                (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define PSSI_ICR_OVR_ISC                    PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */
+
+/********************  Bit definition for PSSI_DR register  *******************/
+#define PSSI_DR_DR_Pos                      (0U)
+#define PSSI_DR_DR_Msk                      (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
+#define PSSI_DR_DR                          PSSI_DR_DR_Msk                          /*!< Data register  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PWR_CR1 register  ********************/
+#define PWR_CR1_SDEN_Pos                (2U)
+#define PWR_CR1_SDEN_Msk                (0x1UL << PWR_CR1_SDEN_Pos)             /*!< 0x00000004 */
+#define PWR_CR1_SDEN                    PWR_CR1_SDEN_Msk                        /*!< SMPS step-down converter enable */
+#define PWR_CR1_MODE_PDN_Pos            (4U)
+#define PWR_CR1_MODE_PDN_Msk            (0x1UL << PWR_CR1_MODE_PDN_Pos)         /*!< 0x00000010 */
+#define PWR_CR1_MODE_PDN                PWR_CR1_MODE_PDN_Msk                    /*!< Pull down on output voltage during power down mode */
+#define PWR_CR1_LPDS08V_Pos             (5U)
+#define PWR_CR1_LPDS08V_Msk             (0x1UL << PWR_CR1_LPDS08V_Pos)          /*!< 0x00000020 */
+#define PWR_CR1_LPDS08V                 PWR_CR1_LPDS08V_Msk                     /*!< SMPS Low power mode enable (SVOS high only) */
+#define PWR_CR1_VDD18SMPSVMEN_Pos       (8U)
+#define PWR_CR1_VDD18SMPSVMEN_Msk       (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos)    /*!< 0x00000100 */
+#define PWR_CR1_VDD18SMPSVMEN           PWR_CR1_VDD18SMPSVMEN_Msk               /*!< VDD18SMPS voltage monitor enable */
+#define PWR_CR1_VDD18SMPSRDY_Pos        (15U)
+#define PWR_CR1_VDD18SMPSRDY_Msk        (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos)     /*!< 0x00008000 */
+#define PWR_CR1_VDD18SMPSRDY            PWR_CR1_VDD18SMPSRDY_Msk                /*!< VDD18SMPS ready */
+#define PWR_CR1_POPL_Pos                (16U)
+#define PWR_CR1_POPL_Msk                (0x1FUL << PWR_CR1_POPL_Pos)            /*!< 0x001F0000 */
+#define PWR_CR1_POPL                    PWR_CR1_POPL_Msk                        /*!< pwr_on pulse low configuration */
+#define PWR_CR1_POPL_0                  (0x1UL << PWR_CR1_POPL_Pos)             /*!< 0x00010000 */
+#define PWR_CR1_POPL_1                  (0x2UL << PWR_CR1_POPL_Pos)             /*!< 0x00020000 */
+#define PWR_CR1_POPL_2                  (0x4UL << PWR_CR1_POPL_Pos)             /*!< 0x00040000 */
+#define PWR_CR1_POPL_3                  (0x8UL << PWR_CR1_POPL_Pos)             /*!< 0x00080000 */
+#define PWR_CR1_POPL_4                  (0x10UL << PWR_CR1_POPL_Pos)            /*!< 0x00100000 */
+
+/*******************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_PVDEN_Pos               (0U)
+#define PWR_CR2_PVDEN_Msk               (0x1UL << PWR_CR2_PVDEN_Pos)            /*!< 0x00000001 */
+#define PWR_CR2_PVDEN                   PWR_CR2_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR2_PVDO_Pos                (8U)
+#define PWR_CR2_PVDO_Msk                (0x1UL << PWR_CR2_PVDO_Pos)             /*!< 0x00000100 */
+#define PWR_CR2_PVDO                    PWR_CR2_PVDO_Msk                        /*!< Programmable Voltage Detect Output */
+
+/*******************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_VCOREMONEN_Pos          (0U)
+#define PWR_CR3_VCOREMONEN_Msk          (0x1UL << PWR_CR3_VCOREMONEN_Pos)       /*!< 0x00000001 */
+#define PWR_CR3_VCOREMONEN              PWR_CR3_VCOREMONEN_Msk                  /*!< VDDCORE monitoring enable */
+#define PWR_CR3_VCORELLS_Pos            (4U)
+#define PWR_CR3_VCORELLS_Msk            (0x1UL << PWR_CR3_VCORELLS_Pos)         /*!< 0x00000010 */
+#define PWR_CR3_VCORELLS                PWR_CR3_VCORELLS_Msk                    /*!< VDDCORE Voltage Detector low level selection */
+#define PWR_CR3_VCOREL_Pos              (8U)
+#define PWR_CR3_VCOREL_Msk              (0x1UL << PWR_CR3_VCOREL_Pos)           /*!< 0x00000100 */
+#define PWR_CR3_VCOREL                  PWR_CR3_VCOREL_Msk                      /*!< Monitored VDDCORE level above low threshold */
+#define PWR_CR3_VCOREH_Pos              (9U)
+#define PWR_CR3_VCOREH_Msk              (0x1UL << PWR_CR3_VCOREH_Pos)           /*!< 0x00000200 */
+#define PWR_CR3_VCOREH                  PWR_CR3_VCOREH_Msk                      /*!< Monitored VDDCORE level above high threshold */
+
+/*******************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_TCMRBSEN_Pos            (0U)
+#define PWR_CR4_TCMRBSEN_Msk            (0x1UL << PWR_CR4_TCMRBSEN_Pos)         /*!< 0x00000001 */
+#define PWR_CR4_TCMRBSEN                PWR_CR4_TCMRBSEN_Msk                    /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */
+#define PWR_CR4_TCMFLXRBSEN_Pos         (4U)
+#define PWR_CR4_TCMFLXRBSEN_Msk         (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos)      /*!< 0x00000010 */
+#define PWR_CR4_TCMFLXRBSEN             PWR_CR4_TCMFLXRBSEN_Msk                 /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */
+
+/******************  Bit definition for PWR_VOSCR register  *******************/
+#define PWR_VOSCR_VOS_Pos               (0U)
+#define PWR_VOSCR_VOS_Msk               (0x1UL << PWR_VOSCR_VOS_Pos)            /*!< 0x00000001 */
+#define PWR_VOSCR_VOS                   PWR_VOSCR_VOS_Msk                       /*!< Voltage scaling selection according to performance */
+#define PWR_VOSCR_VOSRDY_Pos            (1U)
+#define PWR_VOSCR_VOSRDY_Msk            (0x1UL << PWR_VOSCR_VOSRDY_Pos)         /*!< 0x00000002 */
+#define PWR_VOSCR_VOSRDY                PWR_VOSCR_VOSRDY_Msk                    /*!< VOS Ready bit for VCORE voltage scaling output selection */
+#define PWR_VOSCR_ACTVOS_Pos            (16U)
+#define PWR_VOSCR_ACTVOS_Msk            (0x1UL << PWR_VOSCR_ACTVOS_Pos)         /*!< 0x00010000 */
+#define PWR_VOSCR_ACTVOS                PWR_VOSCR_ACTVOS_Msk                    /*!< VOS currently applied for VCORE voltage scaling selection */
+#define PWR_VOSCR_ACTVOSRDY_Pos         (17U)
+#define PWR_VOSCR_ACTVOSRDY_Msk         (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos)      /*!< 0x00020000 */
+#define PWR_VOSCR_ACTVOSRDY             PWR_VOSCR_ACTVOSRDY_Msk                 /*!< Voltage levels ready bit for currently used ACTVOS */
+
+/******************  Bit definition for PWR_BDCR1 register  *******************/
+#define PWR_BDCR1_MONEN_Pos             (0U)
+#define PWR_BDCR1_MONEN_Msk             (0x1UL << PWR_BDCR1_MONEN_Pos)          /*!< 0x00000001 */
+#define PWR_BDCR1_MONEN                 PWR_BDCR1_MONEN_Msk                     /*!< VBAT and temperature monitoring enable */
+#define PWR_BDCR1_VBATL_Pos             (16U)
+#define PWR_BDCR1_VBATL_Msk             (0x1UL << PWR_BDCR1_VBATL_Pos)          /*!< 0x00010000 */
+#define PWR_BDCR1_VBATL                 PWR_BDCR1_VBATL_Msk                     /*!< VBAT level monitoring versus low threshold */
+#define PWR_BDCR1_VBATH_Pos             (17U)
+#define PWR_BDCR1_VBATH_Msk             (0x1UL << PWR_BDCR1_VBATH_Pos)          /*!< 0x00020000 */
+#define PWR_BDCR1_VBATH                 PWR_BDCR1_VBATH_Msk                     /*!< VBAT level monitoring versus high threshold */
+#define PWR_BDCR1_TEMPL_Pos             (18U)
+#define PWR_BDCR1_TEMPL_Msk             (0x1UL << PWR_BDCR1_TEMPL_Pos)          /*!< 0x00040000 */
+#define PWR_BDCR1_TEMPL                 PWR_BDCR1_TEMPL_Msk                     /*!< Temperature level monitoring versus low threshold */
+#define PWR_BDCR1_TEMPH_Pos             (19U)
+#define PWR_BDCR1_TEMPH_Msk             (0x1UL << PWR_BDCR1_TEMPH_Pos)          /*!< 0x00080000 */
+#define PWR_BDCR1_TEMPH                 PWR_BDCR1_TEMPH_Msk                     /*!< Temperature level monitoring versus high threshold */
+
+/******************  Bit definition for PWR_BDCR2 register  *******************/
+#define PWR_BDCR2_BKPRBSEN_Pos          (0U)
+#define PWR_BDCR2_BKPRBSEN_Msk          (0x1UL << PWR_BDCR2_BKPRBSEN_Pos)       /*!< 0x00000001 */
+#define PWR_BDCR2_BKPRBSEN              PWR_BDCR2_BKPRBSEN_Msk                  /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */
+
+/******************  Bit definition for PWR_DBPCR register  *******************/
+#define PWR_DBPCR_DBP_Pos               (0U)
+#define PWR_DBPCR_DBP_Msk               (0x1UL << PWR_DBPCR_DBP_Pos)            /*!< 0x00000001 */
+#define PWR_DBPCR_DBP                   PWR_DBPCR_DBP_Msk                       /*!< Disable backup domain write protection */
+
+/******************  Bit definition for PWR_CPUCR register  *******************/
+#define PWR_CPUCR_PDDS_Pos              (0U)
+#define PWR_CPUCR_PDDS_Msk              (0x1UL << PWR_CPUCR_PDDS_Pos)           /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS                  PWR_CPUCR_PDDS_Msk                      /*!< Power Down Deepsleep selection */
+#define PWR_CPUCR_CSSF_Pos              (1U)
+#define PWR_CPUCR_CSSF_Msk              (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000002 */
+#define PWR_CPUCR_CSSF                  PWR_CPUCR_CSSF_Msk                      /*!< Clear Standby and Stop flags (always read as 0) */
+#define PWR_CPUCR_STOPF_Pos             (8U)
+#define PWR_CPUCR_STOPF_Msk             (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000100 */
+#define PWR_CPUCR_STOPF                 PWR_CPUCR_STOPF_Msk                     /*!< STOP flag */
+#define PWR_CPUCR_SBF_Pos               (9U)
+#define PWR_CPUCR_SBF_Msk               (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000200 */
+#define PWR_CPUCR_SBF                   PWR_CPUCR_SBF_Msk                       /*!< System Standby flag */
+#define PWR_CPUCR_SVOS_Pos              (16U)
+#define PWR_CPUCR_SVOS_Msk              (0x1UL << PWR_CPUCR_SVOS_Pos)           /*!< 0x00010000 */
+#define PWR_CPUCR_SVOS                  PWR_CPUCR_SVOS_Msk                      /*!< System Stop mode voltage scaling selection */
+
+/******************  Bit definition for PWR_SVMCR1 register  ******************/
+#define PWR_SVMCR1_VDDIO4VMEN_Pos       (0U)
+#define PWR_SVMCR1_VDDIO4VMEN_Msk       (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR1_VDDIO4VMEN           PWR_SVMCR1_VDDIO4VMEN_Msk               /*!< VDDOI4 Independent I/Os voltage monitor enable */
+#define PWR_SVMCR1_VDDIO4SV_Pos         (8U)
+#define PWR_SVMCR1_VDDIO4SV_Msk         (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR1_VDDIO4SV             PWR_SVMCR1_VDDIO4SV_Msk                 /*!< VDDIO4 Independent I/Os supply valid */
+#define PWR_SVMCR1_VDDIO4RDY_Pos        (16U)
+#define PWR_SVMCR1_VDDIO4RDY_Msk        (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR1_VDDIO4RDY            PWR_SVMCR1_VDDIO4RDY_Msk                /*!< VDDIO4 ready */
+#define PWR_SVMCR1_VDDIO4VRSEL_Pos      (24U)
+#define PWR_SVMCR1_VDDIO4VRSEL_Msk      (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR1_VDDIO4VRSEL          PWR_SVMCR1_VDDIO4VRSEL_Msk              /*!< VDDIO4 IO voltage range selection */
+#define PWR_SVMCR1_VDDIO4VRSTBY_Pos     (25U)
+#define PWR_SVMCR1_VDDIO4VRSTBY_Msk     (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos)  /*!< 0x04000000 */
+#define PWR_SVMCR1_VDDIO4VRSTBY         PWR_SVMCR1_VDDIO4VRSTBY_Msk             /*!< VDDIO4 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR2 register  ******************/
+#define PWR_SVMCR2_VDDIO5VMEN_Pos       (0U)
+#define PWR_SVMCR2_VDDIO5VMEN_Msk       (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR2_VDDIO5VMEN           PWR_SVMCR2_VDDIO5VMEN_Msk               /*!< VDDIO5 Independent voltage monitor enable */
+#define PWR_SVMCR2_VDDIO5SV_Pos         (8U)
+#define PWR_SVMCR2_VDDIO5SV_Msk         (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR2_VDDIO5SV             PWR_SVMCR2_VDDIO5SV_Msk                 /*!< VDDIO5 Independent supply valid */
+#define PWR_SVMCR2_VDDIO5RDY_Pos        (16U)
+#define PWR_SVMCR2_VDDIO5RDY_Msk        (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR2_VDDIO5RDY            PWR_SVMCR2_VDDIO5RDY_Msk                /*!< VDDIO5 ready */
+#define PWR_SVMCR2_VDDIO5VRSEL_Pos      (24U)
+#define PWR_SVMCR2_VDDIO5VRSEL_Msk      (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR2_VDDIO5VRSEL          PWR_SVMCR2_VDDIO5VRSEL_Msk              /*!< VDDIO5 IO voltage range selection */
+#define PWR_SVMCR2_VDDIO5VRSTBY_Pos     (25U)
+#define PWR_SVMCR2_VDDIO5VRSTBY_Msk     (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos)  /*!< 0x02000000 */
+#define PWR_SVMCR2_VDDIO5VRSTBY         PWR_SVMCR2_VDDIO5VRSTBY_Msk             /*!< VDDIO5 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR3 register  ******************/
+#define PWR_SVMCR3_VDDIO2VMEN_Pos       (0U)
+#define PWR_SVMCR3_VDDIO2VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR3_VDDIO2VMEN           PWR_SVMCR3_VDDIO2VMEN_Msk               /*!< VDDIO2 Independent voltage monitor enable */
+#define PWR_SVMCR3_VDDIO3VMEN_Pos       (1U)
+#define PWR_SVMCR3_VDDIO3VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos)    /*!< 0x00000002 */
+#define PWR_SVMCR3_VDDIO3VMEN           PWR_SVMCR3_VDDIO3VMEN_Msk               /*!< VDDIO3 Independent voltage monitor enable */
+#define PWR_SVMCR3_USB33VMEN_Pos        (2U)
+#define PWR_SVMCR3_USB33VMEN_Msk        (0x1UL << PWR_SVMCR3_USB33VMEN_Pos)     /*!< 0x00000004 */
+#define PWR_SVMCR3_USB33VMEN            PWR_SVMCR3_USB33VMEN_Msk                /*!< VDD33USB Independent USB 33 voltage monitor enable */
+#define PWR_SVMCR3_AVMEN_Pos            (4U)
+#define PWR_SVMCR3_AVMEN_Msk            (0x1UL << PWR_SVMCR3_AVMEN_Pos)         /*!< 0x00000010 */
+#define PWR_SVMCR3_AVMEN                PWR_SVMCR3_AVMEN_Msk                    /*!< VDDA18ADC Independent ADC voltage monitor enable */
+#define PWR_SVMCR3_VDDIO2SV_Pos         (8U)
+#define PWR_SVMCR3_VDDIO2SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR3_VDDIO2SV             PWR_SVMCR3_VDDIO2SV_Msk                 /*!< VDDIO2 Independent supply valid */
+#define PWR_SVMCR3_VDDIO3SV_Pos         (9U)
+#define PWR_SVMCR3_VDDIO3SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos)      /*!< 0x00000200 */
+#define PWR_SVMCR3_VDDIO3SV             PWR_SVMCR3_VDDIO3SV_Msk                 /*!< VDDIO3 Independent supply valid */
+#define PWR_SVMCR3_USB33SV_Pos          (10U)
+#define PWR_SVMCR3_USB33SV_Msk          (0x1UL << PWR_SVMCR3_USB33SV_Pos)       /*!< 0x00000400 */
+#define PWR_SVMCR3_USB33SV              PWR_SVMCR3_USB33SV_Msk                  /*!< VDD33USB Independent supply valid */
+#define PWR_SVMCR3_ASV_Pos              (12U)
+#define PWR_SVMCR3_ASV_Msk              (0x1UL << PWR_SVMCR3_ASV_Pos)           /*!< 0x00001000 */
+#define PWR_SVMCR3_ASV                  PWR_SVMCR3_ASV_Msk                      /*!< VDDA18ADC Independent supply valid */
+#define PWR_SVMCR3_VDDIO2RDY_Pos        (16U)
+#define PWR_SVMCR3_VDDIO2RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR3_VDDIO2RDY            PWR_SVMCR3_VDDIO2RDY_Msk                /*!< VDDIO2 ready */
+#define PWR_SVMCR3_VDDIO3RDY_Pos        (17U)
+#define PWR_SVMCR3_VDDIO3RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos)     /*!< 0x00020000 */
+#define PWR_SVMCR3_VDDIO3RDY            PWR_SVMCR3_VDDIO3RDY_Msk                /*!< VDDIO3 ready */
+#define PWR_SVMCR3_USB33RDY_Pos         (18U)
+#define PWR_SVMCR3_USB33RDY_Msk         (0x1UL << PWR_SVMCR3_USB33RDY_Pos)      /*!< 0x00040000 */
+#define PWR_SVMCR3_USB33RDY             PWR_SVMCR3_USB33RDY_Msk                 /*!< VDD33USB ready */
+#define PWR_SVMCR3_ARDY_Pos             (20U)
+#define PWR_SVMCR3_ARDY_Msk             (0x1UL << PWR_SVMCR3_ARDY_Pos)          /*!< 0x00100000 */
+#define PWR_SVMCR3_ARDY                 PWR_SVMCR3_ARDY_Msk                     /*!< VDDA18ADC ready */
+#define PWR_SVMCR3_VDDIOVRSEL_Pos       (24U)
+#define PWR_SVMCR3_VDDIOVRSEL_Msk       (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos)    /*!< 0x01000000 */
+#define PWR_SVMCR3_VDDIOVRSEL           PWR_SVMCR3_VDDIOVRSEL_Msk               /*!< VDD IO voltage range selection */
+#define PWR_SVMCR3_VDDIO2VRSEL_Pos      (25U)
+#define PWR_SVMCR3_VDDIO2VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos)   /*!< 0x02000000 */
+#define PWR_SVMCR3_VDDIO2VRSEL          PWR_SVMCR3_VDDIO2VRSEL_Msk              /*!< VDDIO2 IO voltage range selection */
+#define PWR_SVMCR3_VDDIO3VRSEL_Pos      (26U)
+#define PWR_SVMCR3_VDDIO3VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos)   /*!< 0x04000000 */
+#define PWR_SVMCR3_VDDIO3VRSEL          PWR_SVMCR3_VDDIO3VRSEL_Msk              /*!< VDDIO3 IO voltage range selection */
+
+/*****************  Bit definition for PWR_WKUPCR register  *******************/
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                    /*!< Clear Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                    /*!< Clear Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                    /*!< Clear Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                    /*!< Clear Wakeup Flag for WKUP4 pin */
+#define PWR_WKUPCR_WKUPC_Pos           (0U)
+#define PWR_WKUPCR_WKUPC_Msk           (0xFUL << PWR_WKUPCR_WKUPC_Pos)         /*!< 0x0000000F */
+#define PWR_WKUPCR_WKUPC               PWR_WKUPCR_WKUPC_Msk                    /*!< Clear Wakeup Flag 1 to 4 */
+
+/*****************  Bit definition for PWR_WKUPSR register  *******************/
+#define PWR_WKUPSR_WKUPF1_Pos          (0U)
+#define PWR_WKUPSR_WKUPF1_Msk          (0x1UL << PWR_WKUPSR_WKUPF1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPSR_WKUPF1              PWR_WKUPSR_WKUPF1_Msk                    /*!< Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPSR_WKUPF2_Pos          (1U)
+#define PWR_WKUPSR_WKUPF2_Msk          (0x1UL << PWR_WKUPSR_WKUPF2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPSR_WKUPF2              PWR_WKUPSR_WKUPF2_Msk                    /*!< Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPSR_WKUPF3_Pos          (2U)
+#define PWR_WKUPSR_WKUPF3_Msk          (0x1UL << PWR_WKUPSR_WKUPF3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPSR_WKUPF3              PWR_WKUPSR_WKUPF3_Msk                    /*!< Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPSR_WKUPF4_Pos          (3U)
+#define PWR_WKUPSR_WKUPF4_Msk          (0x1UL << PWR_WKUPSR_WKUPF4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPSR_WKUPF4              PWR_WKUPSR_WKUPF4_Msk                    /*!< Wakeup Flag for WKUP4 pin */
+
+/*****************  Bit definition for PWR_WKUPEPR register  *******************/
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)       /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                  /*!< Enable Wakeup pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)       /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                  /*!< Enable Wakeup pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)       /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                  /*!< Enable Wakeup pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)       /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                  /*!< Enable Wakeup pin WKUP4 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)        /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                   /*!< Wakeup Polarity bit for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)        /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                   /*!< Wakeup Polarity bit for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)        /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                   /*!< Wakeup Polarity bit for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)        /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                   /*!< Wakeup Polarity bit for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPP_Pos          (8U)
+#define PWR_WKUPEPR_WKUPP_Msk          (0x0FUL << PWR_WKUPEPR_WKUPP_Pos)        /*!< 0x0000300F */
+#define PWR_WKUPEPR_WKUPP              PWR_WKUPEPR_WKUPP_Msk                    /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk                /*!< Wakeup pull configuration for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk                /*!< Wakeup pull configuration for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk                /*!< Wakeup pull configuration for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk                /*!< Wakeup pull configuration for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos)       /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                   /*!< Enable all Wakeup Pin */
+
+/*****************  Bit definition for PWR_SECCFGR register  ******************/
+#define PWR_SECCFGR_SEC0_Pos            (0U)
+#define PWR_SECCFGR_SEC0_Msk            (0x1UL << PWR_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
+#define PWR_SECCFGR_SEC0                PWR_SECCFGR_SEC0_Msk                    /*!< System supply configuration secure protection */
+#define PWR_SECCFGR_SEC1_Pos            (1U)
+#define PWR_SECCFGR_SEC1_Msk            (0x1UL << PWR_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
+#define PWR_SECCFGR_SEC1                PWR_SECCFGR_SEC1_Msk                    /*!< Programmable voltage detector secure protection */
+#define PWR_SECCFGR_SEC2_Pos            (2U)
+#define PWR_SECCFGR_SEC2_Msk            (0x1UL << PWR_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
+#define PWR_SECCFGR_SEC2                PWR_SECCFGR_SEC2_Msk                    /*!< VDDCORE monitor secure protection */
+#define PWR_SECCFGR_SEC3_Pos            (3U)
+#define PWR_SECCFGR_SEC3_Msk            (0x1UL << PWR_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
+#define PWR_SECCFGR_SEC3                PWR_SECCFGR_SEC3_Msk                    /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */
+#define PWR_SECCFGR_SEC4_Pos            (4U)
+#define PWR_SECCFGR_SEC4_Msk            (0x1UL << PWR_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
+#define PWR_SECCFGR_SEC4                PWR_SECCFGR_SEC4_Msk                    /*!< Voltage scaling selection secure protection */
+#define PWR_SECCFGR_SEC5_Pos            (5U)
+#define PWR_SECCFGR_SEC5_Msk            (0x1UL << PWR_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
+#define PWR_SECCFGR_SEC5                PWR_SECCFGR_SEC5_Msk                    /*!< Backup domain secure protection */
+#define PWR_SECCFGR_SEC6_Pos            (6U)
+#define PWR_SECCFGR_SEC6_Msk            (0x1UL << PWR_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
+#define PWR_SECCFGR_SEC6                PWR_SECCFGR_SEC6_Msk                    /*!< CPU power control secure protection */
+#define PWR_SECCFGR_SEC7_Pos            (7U)
+#define PWR_SECCFGR_SEC7_Msk            (0x1UL << PWR_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
+#define PWR_SECCFGR_SEC7                PWR_SECCFGR_SEC7_Msk                    /*!< Peripheral voltage monitor secure protection */
+#define PWR_SECCFGR_WKUPSEC1_Pos        (16U)
+#define PWR_SECCFGR_WKUPSEC1_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos)     /*!< 0x00010000 */
+#define PWR_SECCFGR_WKUPSEC1            PWR_SECCFGR_WKUPSEC1_Msk                /*!< WKUP1 secure protection */
+#define PWR_SECCFGR_WKUPSEC2_Pos        (17U)
+#define PWR_SECCFGR_WKUPSEC2_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos)     /*!< 0x00020000 */
+#define PWR_SECCFGR_WKUPSEC2            PWR_SECCFGR_WKUPSEC2_Msk                /*!< WKUP2 secure protection */
+#define PWR_SECCFGR_WKUPSEC3_Pos        (18U)
+#define PWR_SECCFGR_WKUPSEC3_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos)     /*!< 0x00040000 */
+#define PWR_SECCFGR_WKUPSEC3            PWR_SECCFGR_WKUPSEC3_Msk                /*!< WKUP3 secure protection */
+#define PWR_SECCFGR_WKUPSEC4_Pos        (19U)
+#define PWR_SECCFGR_WKUPSEC4_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos)     /*!< 0x00080000 */
+#define PWR_SECCFGR_WKUPSEC4            PWR_SECCFGR_WKUPSEC4_Msk                /*!< WKUP4 secure protection */
+
+/*****************  Bit definition for PWR_PRIVCFGR register  *****************/
+#define PWR_PRIVCFGR_PRIV0_Pos          (0U)
+#define PWR_PRIVCFGR_PRIV0_Msk          (0x1UL << PWR_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define PWR_PRIVCFGR_PRIV0              PWR_PRIVCFGR_PRIV0_Msk                  /*!< System supply configuration privileged protection */
+#define PWR_PRIVCFGR_PRIV1_Pos          (1U)
+#define PWR_PRIVCFGR_PRIV1_Msk          (0x1UL << PWR_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define PWR_PRIVCFGR_PRIV1              PWR_PRIVCFGR_PRIV1_Msk                  /*!< Programmable voltage detector privileged protection */
+#define PWR_PRIVCFGR_PRIV2_Pos          (2U)
+#define PWR_PRIVCFGR_PRIV2_Msk          (0x1UL << PWR_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define PWR_PRIVCFGR_PRIV2              PWR_PRIVCFGR_PRIV2_Msk                  /*!< VDDCORE monitor privileged protection */
+#define PWR_PRIVCFGR_PRIV3_Pos          (3U)
+#define PWR_PRIVCFGR_PRIV3_Msk          (0x1UL << PWR_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define PWR_PRIVCFGR_PRIV3              PWR_PRIVCFGR_PRIV3_Msk                  /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */
+#define PWR_PRIVCFGR_PRIV4_Pos          (4U)
+#define PWR_PRIVCFGR_PRIV4_Msk          (0x1UL << PWR_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define PWR_PRIVCFGR_PRIV4              PWR_PRIVCFGR_PRIV4_Msk                  /*!< Voltage scaling selection privileged protection */
+#define PWR_PRIVCFGR_PRIV5_Pos          (5U)
+#define PWR_PRIVCFGR_PRIV5_Msk          (0x1UL << PWR_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define PWR_PRIVCFGR_PRIV5              PWR_PRIVCFGR_PRIV5_Msk                  /*!< Backup domain privileged protection */
+#define PWR_PRIVCFGR_PRIV6_Pos          (6U)
+#define PWR_PRIVCFGR_PRIV6_Msk          (0x1UL << PWR_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define PWR_PRIVCFGR_PRIV6              PWR_PRIVCFGR_PRIV6_Msk                  /*!< CPU power control privileged protection */
+#define PWR_PRIVCFGR_PRIV7_Pos          (7U)
+#define PWR_PRIVCFGR_PRIV7_Msk          (0x1UL << PWR_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define PWR_PRIVCFGR_PRIV7              PWR_PRIVCFGR_PRIV7_Msk                  /*!< Peripheral voltage monitor privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV1_Pos      (16U)
+#define PWR_PRIVCFGR_WKUPPRIV1_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos)   /*!< 0x00010000 */
+#define PWR_PRIVCFGR_WKUPPRIV1          PWR_PRIVCFGR_WKUPPRIV1_Msk              /*!< WKUP1 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV2_Pos      (17U)
+#define PWR_PRIVCFGR_WKUPPRIV2_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos)   /*!< 0x00020000 */
+#define PWR_PRIVCFGR_WKUPPRIV2          PWR_PRIVCFGR_WKUPPRIV2_Msk              /*!< WKUP2 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV3_Pos      (18U)
+#define PWR_PRIVCFGR_WKUPPRIV3_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos)   /*!< 0x00040000 */
+#define PWR_PRIVCFGR_WKUPPRIV3          PWR_PRIVCFGR_WKUPPRIV3_Msk              /*!< WKUP3 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV4_Pos      (19U)
+#define PWR_PRIVCFGR_WKUPPRIV4_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos)   /*!< 0x00080000 */
+#define PWR_PRIVCFGR_WKUPPRIV4          PWR_PRIVCFGR_WKUPPRIV4_Msk              /*!< WKUP4 privileged protection */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       RAMs configuration controller                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RAMCFG_CR register  ******************/
+#define RAMCFG_CR_ECCE_Pos              (0U)
+#define RAMCFG_CR_ECCE_Msk              (0x1UL << RAMCFG_CR_ECCE_Pos)          /*!< 0x00000001 */
+#define RAMCFG_CR_ECCE                  RAMCFG_CR_ECCE_Msk                     /*!< ECC Enable */
+#define RAMCFG_CR_ALE_Pos               (4U)
+#define RAMCFG_CR_ALE_Msk               (0x1UL << RAMCFG_CR_ALE_Pos)           /*!< 0x00000010 */
+#define RAMCFG_CR_ALE                   RAMCFG_CR_ALE_Msk                      /*!< Address Latching Enable */
+#define RAMCFG_CR_SRAMER_Pos            (8U)
+#define RAMCFG_CR_SRAMER_Msk            (0x1UL << RAMCFG_CR_SRAMER_Pos)        /*!< 0x00000100 */
+#define RAMCFG_CR_SRAMER                RAMCFG_CR_SRAMER_Msk                   /*!< Start Erase */
+#define RAMCFG_CR_SRAMHWERDIS_Pos       (12U)
+#define RAMCFG_CR_SRAMHWERDIS_Msk       (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos)   /*!< 0x00001000 */
+#define RAMCFG_CR_SRAMHWERDIS           RAMCFG_CR_SRAMHWERDIS_Msk              /*!< SRAM hardware erase disable */
+#define RAMCFG_CR_ITCMCFG_Pos           (16U)
+#define RAMCFG_CR_ITCMCFG_Msk           (0x3UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00030000 */
+#define RAMCFG_CR_ITCMCFG               RAMCFG_CR_ITCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+#define RAMCFG_CR_ITCMCFG_0             (0x1UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00010000 */
+#define RAMCFG_CR_ITCMCFG_1             (0x2UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00020000 */
+#define RAMCFG_CR_SRAMSD_Pos            (20U)
+#define RAMCFG_CR_SRAMSD_Msk            (0x1UL << RAMCFG_CR_SRAMSD_Pos)        /*!< 0x00100000 */
+#define RAMCFG_CR_SRAMSD                RAMCFG_CR_SRAMSD_Msk                   /*!< Shutdown AXISRAMx */
+#define RAMCFG_CR_DTCMCFG_Pos           (24U)
+#define RAMCFG_CR_DTCMCFG_Msk           (0x1UL << RAMCFG_CR_DTCMCFG_Pos)       /*!< 0x01000000 */
+#define RAMCFG_CR_DTCMCFG               RAMCFG_CR_DTCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+
+/*******************  Bit definition for RAMCFG_IER register  *****************/
+#define RAMCFG_IER_SEIE_Pos             (0U)
+#define RAMCFG_IER_SEIE_Msk             (0x1UL << RAMCFG_IER_SEIE_Pos)         /*!< 0x00000001 */
+#define RAMCFG_IER_SEIE                 RAMCFG_IER_SEIE_Msk                    /*!< Single Error Interrupt Enable */
+#define RAMCFG_IER_DEIE_Pos             (1U)
+#define RAMCFG_IER_DEIE_Msk             (0x1UL << RAMCFG_IER_DEIE_Pos)         /*!< 0x00000002 */
+#define RAMCFG_IER_DEIE                 RAMCFG_IER_DEIE_Msk                    /*!< Double Error Interrupt Enable */
+
+/*******************  Bit definition for RAMCFG_ISR register  *****************/
+#define RAMCFG_ISR_SEDC_Pos             (0U)
+#define RAMCFG_ISR_SEDC_Msk             (0x1UL << RAMCFG_ISR_SEDC_Pos)         /*!< 0x00000001 */
+#define RAMCFG_ISR_SEDC                 RAMCFG_ISR_SEDC_Msk                    /*!< Single Error Detected and Corrected flag */
+#define RAMCFG_ISR_DED_Pos              (1U)
+#define RAMCFG_ISR_DED_Msk              (0x1UL << RAMCFG_ISR_DED_Pos)          /*!< 0x00000002 */
+#define RAMCFG_ISR_DED                  RAMCFG_ISR_DED_Msk                     /*!< Double Error Detected flag */
+#define RAMCFG_ISR_SRAMBUSY_Pos         (8U)
+#define RAMCFG_ISR_SRAMBUSY_Msk         (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)     /*!< 0x00000100 */
+#define RAMCFG_ISR_SRAMBUSY             RAMCFG_ISR_SRAMBUSY_Msk                /*!< SRAM busy flag */
+
+/*******************  Bit definition for RAMCFG_ESEAR register  ****************/
+#define RAMCFG_ESEAR_ESEA_Pos           (0U)
+#define RAMCFG_ESEAR_ESEA_Msk           (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_ESEAR_ESEA               RAMCFG_ESEAR_ESEA_Msk                  /*!< ECC Single Error Address */
+
+/*******************  Bit definition for RAMCFG_EDEAR register  ****************/
+#define RAMCFG_EDEAR_EDEA_Pos           (0U)
+#define RAMCFG_EDEAR_EDEA_Msk           (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_EDEAR_EDEA               RAMCFG_EDEAR_EDEA_Msk                  /*!< ECC Double Error Address */
+
+/*******************  Bit definition for RAMCFG_ICR register  *****************/
+#define RAMCFG_ICR_CSEDC_Pos            (0U)
+#define RAMCFG_ICR_CSEDC_Msk            (0x1UL << RAMCFG_ICR_CSEDC_Pos)        /*!< 0x00000001 */
+#define RAMCFG_ICR_CSEDC                RAMCFG_ICR_CSEDC_Msk                   /*!< Clear ECC Single Error Detected and Corrected Flag */
+#define RAMCFG_ICR_CDED_Pos             (1U)
+#define RAMCFG_ICR_CDED_Msk             (0x1UL << RAMCFG_ICR_CDED_Pos)         /*!< 0x00000002 */
+#define RAMCFG_ICR_CDED                 RAMCFG_ICR_CDED_Msk                    /*!< Clear ECC Double Error Detected Flag*/
+
+/*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
+#define RAMCFG_ECCKEYR_ECCKEY_Pos       (0U)
+#define RAMCFG_ECCKEYR_ECCKEY_Msk       (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)  /*!< 0x000000FF */
+#define RAMCFG_ECCKEYR_ECCKEY           RAMCFG_ECCKEYR_ECCKEY_Msk              /*!< ECC Write Protection Key */
+
+/*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
+#define RAMCFG_ERKEYR_ERASEKEY_Pos      (0U)
+#define RAMCFG_ERKEYR_ERASEKEY_Msk      (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */
+#define RAMCFG_ERKEYR_ERASEKEY          RAMCFG_ERKEYR_ERASEKEY_Msk             /*!< Erase Write Protection Key */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (RCC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_LSION_Pos                        (0U)
+#define RCC_CR_LSION_Msk                        (0x1UL << RCC_CR_LSION_Pos)           /*!< 0x00000001 */
+#define RCC_CR_LSION                            RCC_CR_LSION_Msk                     /*!< LSI oscillator enable */
+#define RCC_CR_LSEON_Pos                        (1U)
+#define RCC_CR_LSEON_Msk                        (0x1UL << RCC_CR_LSEON_Pos)           /*!< 0x00000002 */
+#define RCC_CR_LSEON                            RCC_CR_LSEON_Msk                     /*!< LSE oscillator enable */
+#define RCC_CR_MSION_Pos                        (2U)
+#define RCC_CR_MSION_Msk                        (0x1UL << RCC_CR_MSION_Pos)           /*!< 0x00000004 */
+#define RCC_CR_MSION                            RCC_CR_MSION_Msk                     /*!< MSI oscillator enable */
+#define RCC_CR_HSION_Pos                        (3U)
+#define RCC_CR_HSION_Msk                        (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000008 */
+#define RCC_CR_HSION                            RCC_CR_HSION_Msk                     /*!< HSI oscillator enable */
+#define RCC_CR_HSEON_Pos                        (4U)
+#define RCC_CR_HSEON_Msk                        (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00000010 */
+#define RCC_CR_HSEON                            RCC_CR_HSEON_Msk                     /*!< HSE oscillator enable */
+#define RCC_CR_PLL1ON_Pos                       (8U)
+#define RCC_CR_PLL1ON_Msk                       (0x1UL << RCC_CR_PLL1ON_Pos)          /*!< 0x00000100 */
+#define RCC_CR_PLL1ON                           RCC_CR_PLL1ON_Msk                    /*!< PLL1 enable */
+#define RCC_CR_PLL2ON_Pos                       (9U)
+#define RCC_CR_PLL2ON_Msk                       (0x1UL << RCC_CR_PLL2ON_Pos)          /*!< 0x00000200 */
+#define RCC_CR_PLL2ON                           RCC_CR_PLL2ON_Msk                    /*!< PLL2 enable */
+#define RCC_CR_PLL3ON_Pos                       (10U)
+#define RCC_CR_PLL3ON_Msk                       (0x1UL << RCC_CR_PLL3ON_Pos)          /*!< 0x00000400 */
+#define RCC_CR_PLL3ON                           RCC_CR_PLL3ON_Msk                    /*!< PLL3 enable */
+#define RCC_CR_PLL4ON_Pos                       (11U)
+#define RCC_CR_PLL4ON_Msk                       (0x1UL << RCC_CR_PLL4ON_Pos)          /*!< 0x00000800 */
+#define RCC_CR_PLL4ON                           RCC_CR_PLL4ON_Msk                    /*!< PLL4 enable */
+
+/********************  Bit definition for RCC_SR register  ********************/
+#define RCC_SR_LSIRDY_Pos                       (0U)
+#define RCC_SR_LSIRDY_Msk                       (0x1UL << RCC_SR_LSIRDY_Pos)          /*!< 0x00000001 */
+#define RCC_SR_LSIRDY                           RCC_SR_LSIRDY_Msk                    /*!< LSI clock ready flag */
+#define RCC_SR_LSERDY_Pos                       (1U)
+#define RCC_SR_LSERDY_Msk                       (0x1UL << RCC_SR_LSERDY_Pos)          /*!< 0x00000002 */
+#define RCC_SR_LSERDY                           RCC_SR_LSERDY_Msk                    /*!< LSE clock ready flag */
+#define RCC_SR_MSIRDY_Pos                       (2U)
+#define RCC_SR_MSIRDY_Msk                       (0x1UL << RCC_SR_MSIRDY_Pos)          /*!< 0x00000004 */
+#define RCC_SR_MSIRDY                           RCC_SR_MSIRDY_Msk                    /*!< MSI clock ready flag */
+#define RCC_SR_HSIRDY_Pos                       (3U)
+#define RCC_SR_HSIRDY_Msk                       (0x1UL << RCC_SR_HSIRDY_Pos)          /*!< 0x00000008 */
+#define RCC_SR_HSIRDY                           RCC_SR_HSIRDY_Msk                    /*!< HSI clock ready flag */
+#define RCC_SR_HSERDY_Pos                       (4U)
+#define RCC_SR_HSERDY_Msk                       (0x1UL << RCC_SR_HSERDY_Pos)          /*!< 0x00000010 */
+#define RCC_SR_HSERDY                           RCC_SR_HSERDY_Msk                    /*!< HSE clock ready flag */
+#define RCC_SR_PLL1RDY_Pos                      (8U)
+#define RCC_SR_PLL1RDY_Msk                      (0x1UL << RCC_SR_PLL1RDY_Pos)         /*!< 0x00000100 */
+#define RCC_SR_PLL1RDY                          RCC_SR_PLL1RDY_Msk                   /*!< PLL1 clock ready flag */
+#define RCC_SR_PLL2RDY_Pos                      (9U)
+#define RCC_SR_PLL2RDY_Msk                      (0x1UL << RCC_SR_PLL2RDY_Pos)         /*!< 0x00000200 */
+#define RCC_SR_PLL2RDY                          RCC_SR_PLL2RDY_Msk                   /*!< PLL2 clock ready flag */
+#define RCC_SR_PLL3RDY_Pos                      (10U)
+#define RCC_SR_PLL3RDY_Msk                      (0x1UL << RCC_SR_PLL3RDY_Pos)         /*!< 0x00000400 */
+#define RCC_SR_PLL3RDY                          RCC_SR_PLL3RDY_Msk                   /*!< PLL3 clock ready flag */
+#define RCC_SR_PLL4RDY_Pos                      (11U)
+#define RCC_SR_PLL4RDY_Msk                      (0x1UL << RCC_SR_PLL4RDY_Pos)         /*!< 0x00000800 */
+#define RCC_SR_PLL4RDY                          RCC_SR_PLL4RDY_Msk                   /*!< PLL4 clock ready flag */
+
+/******************  Bit definition for RCC_STOPCR register  ******************/
+#define RCC_STOPCR_MSISTOPEN_Pos                (0U)
+#define RCC_STOPCR_MSISTOPEN_Msk                (0x1UL << RCC_STOPCR_MSISTOPEN_Pos)   /*!< 0x00000001 */
+#define RCC_STOPCR_MSISTOPEN                    RCC_STOPCR_MSISTOPEN_Msk             /*!< MSI oscillator enable */
+#define RCC_STOPCR_HSISTOPEN_Pos                (1U)
+#define RCC_STOPCR_HSISTOPEN_Msk                (0x1UL << RCC_STOPCR_HSISTOPEN_Pos)   /*!< 0x00000002 */
+#define RCC_STOPCR_HSISTOPEN                    RCC_STOPCR_HSISTOPEN_Msk             /*!< HSI oscillator enable */
+
+/******************  Bit definition for RCC_CFGR1 register  *******************/
+#define RCC_CFGR1_STOPWUCK_Pos                  (0U)
+#define RCC_CFGR1_STOPWUCK_Msk                  (0x1UL << RCC_CFGR1_STOPWUCK_Pos)     /*!< 0x00000001 */
+#define RCC_CFGR1_STOPWUCK                      RCC_CFGR1_STOPWUCK_Msk               /*!< System clock selection after a wake up from system stop */
+#define RCC_CFGR1_CPUSW_Pos                     (16U)
+#define RCC_CFGR1_CPUSW_Msk                     (0x3UL << RCC_CFGR1_CPUSW_Pos)        /*!< 0x00030000 */
+#define RCC_CFGR1_CPUSW                         RCC_CFGR1_CPUSW_Msk                  /*!< CPU clock switch selection */
+#define RCC_CFGR1_CPUSW_0                       (0x1UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR1_CPUSW_1                       (0x2UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR1_CPUSWS_Pos                    (20U)
+#define RCC_CFGR1_CPUSWS_Msk                    (0x3UL << RCC_CFGR1_CPUSWS_Pos)       /*!< 0x00300000 */
+#define RCC_CFGR1_CPUSWS                        RCC_CFGR1_CPUSWS_Msk                 /*!< CPU clock switch status */
+#define RCC_CFGR1_CPUSWS_0                      (0x1UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00100000 */
+#define RCC_CFGR1_CPUSWS_1                      (0x2UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00200000 */
+#define RCC_CFGR1_SYSSW_Pos                     (24U)
+#define RCC_CFGR1_SYSSW_Msk                     (0x3UL << RCC_CFGR1_SYSSW_Pos)        /*!< 0x03000000 */
+#define RCC_CFGR1_SYSSW                         RCC_CFGR1_SYSSW_Msk                  /*!< System clock switch selection */
+#define RCC_CFGR1_SYSSW_0                       (0x1UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x01000000 */
+#define RCC_CFGR1_SYSSW_1                       (0x2UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x02000000 */
+#define RCC_CFGR1_SYSSWS_Pos                    (28U)
+#define RCC_CFGR1_SYSSWS_Msk                    (0x3UL << RCC_CFGR1_SYSSWS_Pos)       /*!< 0x30000000 */
+#define RCC_CFGR1_SYSSWS                        RCC_CFGR1_SYSSWS_Msk                 /*!< System clock switch status */
+#define RCC_CFGR1_SYSSWS_0                      (0x1UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR1_SYSSWS_1                      (0x2UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x20000000 */
+
+/******************  Bit definition for RCC_CFGR2 register  *******************/
+#define RCC_CFGR2_PPRE1_Pos                     (0U)
+#define RCC_CFGR2_PPRE1_Msk                     (0x7UL << RCC_CFGR2_PPRE1_Pos)        /*!< 0x00000007 */
+#define RCC_CFGR2_PPRE1                         RCC_CFGR2_PPRE1_Msk                  /*!< CPU domain APB1 prescaler */
+#define RCC_CFGR2_PPRE1_0                       (0x1UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000001 */
+#define RCC_CFGR2_PPRE1_1                       (0x2UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000002 */
+#define RCC_CFGR2_PPRE1_2                       (0x4UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000004 */
+#define RCC_CFGR2_PPRE2_Pos                     (4U)
+#define RCC_CFGR2_PPRE2_Msk                     (0x7UL << RCC_CFGR2_PPRE2_Pos)        /*!< 0x00000070 */
+#define RCC_CFGR2_PPRE2                         RCC_CFGR2_PPRE2_Msk                  /*!< CPU domain APB2 prescaler */
+#define RCC_CFGR2_PPRE2_0                       (0x1UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR2_PPRE2_1                       (0x2UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR2_PPRE2_2                       (0x4UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR2_PPRE4_Pos                     (12U)
+#define RCC_CFGR2_PPRE4_Msk                     (0x7UL << RCC_CFGR2_PPRE4_Pos)        /*!< 0x00007000 */
+#define RCC_CFGR2_PPRE4                         RCC_CFGR2_PPRE4_Msk                  /*!< CPU domain APB4 prescaler */
+#define RCC_CFGR2_PPRE4_0                       (0x1UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR2_PPRE4_1                       (0x2UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00002000 */
+#define RCC_CFGR2_PPRE4_2                       (0x4UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00004000 */
+#define RCC_CFGR2_PPRE5_Pos                     (16U)
+#define RCC_CFGR2_PPRE5_Msk                     (0x7UL << RCC_CFGR2_PPRE5_Pos)        /*!< 0x00070000 */
+#define RCC_CFGR2_PPRE5                         RCC_CFGR2_PPRE5_Msk                  /*!< CPU domain APB5 prescaler */
+#define RCC_CFGR2_PPRE5_0                       (0x1UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR2_PPRE5_1                       (0x2UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR2_PPRE5_2                       (0x4UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00040000 */
+#define RCC_CFGR2_HPRE_Pos                      (20U)
+#define RCC_CFGR2_HPRE_Msk                      (0x7UL << RCC_CFGR2_HPRE_Pos)         /*!< 0x00700000 */
+#define RCC_CFGR2_HPRE                          RCC_CFGR2_HPRE_Msk                   /*!< AHB clock prescaler */
+#define RCC_CFGR2_HPRE_0                        (0x1UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00100000 */
+#define RCC_CFGR2_HPRE_1                        (0x2UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00200000 */
+#define RCC_CFGR2_HPRE_2                        (0x4UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00400000 */
+#define RCC_CFGR2_TIMPRE_Pos                    (24U)
+#define RCC_CFGR2_TIMPRE_Msk                    (0x3UL << RCC_CFGR2_TIMPRE_Pos)       /*!< 0x03000000 */
+#define RCC_CFGR2_TIMPRE                        RCC_CFGR2_TIMPRE_Msk                 /*!< Timer clock prescaler selection */
+#define RCC_CFGR2_TIMPRE_0                      (0x1UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR2_TIMPRE_1                      (0x2UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x02000000 */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define RCC_BDCR_VSWRST_Pos                     (31U)
+#define RCC_BDCR_VSWRST_Msk                     (0x1UL << RCC_BDCR_VSWRST_Pos)       /*!< 0x80000000 */
+#define RCC_BDCR_VSWRST                         RCC_BDCR_VSWRST_Msk                  /*!< Vswitch (VSW) domain software reset */
+
+/******************  Bit definition for RCC_HWRSR register  *******************/
+#define RCC_HWRSR_RMVF_Pos                      (16U)
+#define RCC_HWRSR_RMVF_Msk                      (0x1UL << RCC_HWRSR_RMVF_Pos)         /*!< 0x00010000 */
+#define RCC_HWRSR_RMVF                          RCC_HWRSR_RMVF_Msk                   /*!< Remove reset flag */
+#define RCC_HWRSR_LCKRSTF_Pos                   (17U)
+#define RCC_HWRSR_LCKRSTF_Msk                   (0x1UL << RCC_HWRSR_LCKRSTF_Pos)      /*!< 0x00020000 */
+#define RCC_HWRSR_LCKRSTF                       RCC_HWRSR_LCKRSTF_Msk                /*!< CPU lockup reset flag */
+#define RCC_HWRSR_BORRSTF_Pos                   (21U)
+#define RCC_HWRSR_BORRSTF_Msk                   (0x1UL << RCC_HWRSR_BORRSTF_Pos)      /*!< 0x00200000 */
+#define RCC_HWRSR_BORRSTF                       RCC_HWRSR_BORRSTF_Msk                /*!< BOR reset flag */
+#define RCC_HWRSR_PINRSTF_Pos                   (22U)
+#define RCC_HWRSR_PINRSTF_Msk                   (0x1UL << RCC_HWRSR_PINRSTF_Pos)      /*!< 0x00400000 */
+#define RCC_HWRSR_PINRSTF                       RCC_HWRSR_PINRSTF_Msk                /*!< Pin reset flag (NRST)  */
+#define RCC_HWRSR_PORRSTF_Pos                   (23U)
+#define RCC_HWRSR_PORRSTF_Msk                   (0x1UL << RCC_HWRSR_PORRSTF_Pos)      /*!< 0x00800000 */
+#define RCC_HWRSR_PORRSTF                       RCC_HWRSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
+#define RCC_HWRSR_SFTRSTF_Pos                   (24U)
+#define RCC_HWRSR_SFTRSTF_Msk                   (0x1UL << RCC_HWRSR_SFTRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_HWRSR_SFTRSTF                       RCC_HWRSR_SFTRSTF_Msk                /*!< Software system reset flag  */
+#define RCC_HWRSR_IWDGRSTF_Pos                  (26U)
+#define RCC_HWRSR_IWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_IWDGRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_HWRSR_IWDGRSTF                      RCC_HWRSR_IWDGRSTF_Msk               /*!< Independent watchdog reset flag */
+#define RCC_HWRSR_WWDGRSTF_Pos                  (28U)
+#define RCC_HWRSR_WWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_WWDGRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_HWRSR_WWDGRSTF                      RCC_HWRSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
+#define RCC_HWRSR_LPWRRSTF_Pos                  (30U)
+#define RCC_HWRSR_LPWRRSTF_Msk                  (0x1UL << RCC_HWRSR_LPWRRSTF_Pos)     /*!< 0x40000000 */
+#define RCC_HWRSR_LPWRRSTF                      RCC_HWRSR_LPWRRSTF_Msk               /*!< Illegal Stop or Standby flag */
+
+/*******************  Bit definition for RCC_RSR register  ********************/
+#define RCC_RSR_RMVF_Pos                        (16U)
+#define RCC_RSR_RMVF_Msk                        (0x1UL << RCC_RSR_RMVF_Pos)           /*!< 0x00010000 */
+#define RCC_RSR_RMVF                            RCC_RSR_RMVF_Msk                     /*!< Remove reset flag */
+#define RCC_RSR_LCKRSTF_Pos                     (17U)
+#define RCC_RSR_LCKRSTF_Msk                     (0x1UL << RCC_RSR_LCKRSTF_Pos)        /*!< 0x00020000 */
+#define RCC_RSR_LCKRSTF                         RCC_RSR_LCKRSTF_Msk                  /*!< CPU lockup reset flag */
+#define RCC_RSR_BORRSTF_Pos                     (21U)
+#define RCC_RSR_BORRSTF_Msk                     (0x1UL << RCC_RSR_BORRSTF_Pos)        /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                         RCC_RSR_BORRSTF_Msk                  /*!< BOR reset flag */
+#define RCC_RSR_PINRSTF_Pos                     (22U)
+#define RCC_RSR_PINRSTF_Msk                     (0x1UL << RCC_RSR_PINRSTF_Pos)        /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                         RCC_RSR_PINRSTF_Msk                  /*!< Pin reset flag (NRST)  */
+#define RCC_RSR_PORRSTF_Pos                     (23U)
+#define RCC_RSR_PORRSTF_Msk                     (0x1UL << RCC_RSR_PORRSTF_Pos)        /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                         RCC_RSR_PORRSTF_Msk                  /*!< POR/PDR reset flag */
+#define RCC_RSR_SFTRSTF_Pos                     (24U)
+#define RCC_RSR_SFTRSTF_Msk                     (0x1UL << RCC_RSR_SFTRSTF_Pos)        /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                         RCC_RSR_SFTRSTF_Msk                  /*!< Software system reset flag  */
+#define RCC_RSR_IWDGRSTF_Pos                    (26U)
+#define RCC_RSR_IWDGRSTF_Msk                    (0x1UL << RCC_RSR_IWDGRSTF_Pos)       /*!< 0x04000000 */
+#define RCC_RSR_IWDGRSTF                        RCC_RSR_IWDGRSTF_Msk                 /*!< Independent watchdog reset flag */
+#define RCC_RSR_WWDGRSTF_Pos                    (28U)
+#define RCC_RSR_WWDGRSTF_Msk                    (0x1UL << RCC_RSR_WWDGRSTF_Pos)       /*!< 0x10000000 */
+#define RCC_RSR_WWDGRSTF                        RCC_RSR_WWDGRSTF_Msk                 /*!< Window watchdog reset flag */
+#define RCC_RSR_LPWRRSTF_Pos                    (30U)
+#define RCC_RSR_LPWRRSTF_Msk                    (0x1UL << RCC_RSR_LPWRRSTF_Pos)       /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                        RCC_RSR_LPWRRSTF_Msk                 /*!< Illegal Stop or Standby flag */
+
+/*****************  Bit definition for RCC_LSECFGR register  ******************/
+#define RCC_LSECFGR_LSECSSON_Pos                (7U)
+#define RCC_LSECFGR_LSECSSON_Msk                (0x1UL << RCC_LSECFGR_LSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_LSECFGR_LSECSSON                    RCC_LSECFGR_LSECSSON_Msk             /*!< LSE clock security system (CSS) enable */
+#define RCC_LSECFGR_LSECSSRA_Pos                (8U)
+#define RCC_LSECFGR_LSECSSRA_Msk                (0x1UL << RCC_LSECFGR_LSECSSRA_Pos)   /*!< 0x00000100 */
+#define RCC_LSECFGR_LSECSSRA                    RCC_LSECFGR_LSECSSRA_Msk             /*!< LSE clock security system (CSS) rearm function */
+#define RCC_LSECFGR_LSECSSD_Pos                 (9U)
+#define RCC_LSECFGR_LSECSSD_Msk                 (0x1UL << RCC_LSECFGR_LSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_LSECFGR_LSECSSD                     RCC_LSECFGR_LSECSSD_Msk              /*!< LSE clock security system (CSS) failure detection */
+#define RCC_LSECFGR_LSEBYP_Pos                  (15U)
+#define RCC_LSECFGR_LSEBYP_Msk                  (0x1UL << RCC_LSECFGR_LSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_LSECFGR_LSEBYP                      RCC_LSECFGR_LSEBYP_Msk               /*!< LSE clock bypass */
+#define RCC_LSECFGR_LSEEXT_Pos                  (16U)
+#define RCC_LSECFGR_LSEEXT_Msk                  (0x1UL << RCC_LSECFGR_LSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_LSECFGR_LSEEXT                      RCC_LSECFGR_LSEEXT_Msk               /*!< LSE clock type in bypass mode */
+#define RCC_LSECFGR_LSEGFON_Pos                 (17U)
+#define RCC_LSECFGR_LSEGFON_Msk                 (0x1UL << RCC_LSECFGR_LSEGFON_Pos)    /*!< 0x00020000 */
+#define RCC_LSECFGR_LSEGFON                     RCC_LSECFGR_LSEGFON_Msk              /*!< LSE clock glitch filter enable */
+#define RCC_LSECFGR_LSEDRV_Pos                  (18U)
+#define RCC_LSECFGR_LSEDRV_Msk                  (0x3UL << RCC_LSECFGR_LSEDRV_Pos)     /*!< 0x000C0000 */
+#define RCC_LSECFGR_LSEDRV                      RCC_LSECFGR_LSEDRV_Msk               /*!< LSE oscillator driving capability */
+#define RCC_LSECFGR_LSEDRV_0                    (0x1UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00040000 */
+#define RCC_LSECFGR_LSEDRV_1                    (0x2UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for RCC_MSICFGR register  ******************/
+#define RCC_MSICFGR_MSIFREQSEL_Pos              (9U)
+#define RCC_MSICFGR_MSIFREQSEL_Msk              (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */
+#define RCC_MSICFGR_MSIFREQSEL                  RCC_MSICFGR_MSIFREQSEL_Msk           /*!< MSI oscillator frequency selection */
+#define RCC_MSICFGR_MSITRIM_Pos                 (16U)
+#define RCC_MSICFGR_MSITRIM_Msk                 (0x1FUL << RCC_MSICFGR_MSITRIM_Pos)   /*!< 0x001F0000 */
+#define RCC_MSICFGR_MSITRIM                     RCC_MSICFGR_MSITRIM_Msk              /*!< MSI clock trimming */
+#define RCC_MSICFGR_MSICAL_Pos                  (23U)
+#define RCC_MSICFGR_MSICAL_Msk                  (0xFFUL << RCC_MSICFGR_MSICAL_Pos)    /*!< 0x7F800000 */
+#define RCC_MSICFGR_MSICAL                      RCC_MSICFGR_MSICAL_Msk               /*!< MSI clock calibration */
+
+/*****************  Bit definition for RCC_HSICFGR register  ******************/
+#define RCC_HSICFGR_HSIDIV_Pos                  (7U)
+#define RCC_HSICFGR_HSIDIV_Msk                  (0x3UL << RCC_HSICFGR_HSIDIV_Pos)     /*!< 0x00000180 */
+#define RCC_HSICFGR_HSIDIV                      RCC_HSICFGR_HSIDIV_Msk               /*!< HSI clock divider */
+#define RCC_HSICFGR_HSIDIV_0                    (0x1UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000080 */
+#define RCC_HSICFGR_HSIDIV_1                    (0x2UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000100 */
+#define RCC_HSICFGR_HSITRIM_Pos                 (16U)
+#define RCC_HSICFGR_HSITRIM_Msk                 (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)   /*!< 0x007F0000 */
+#define RCC_HSICFGR_HSITRIM                     RCC_HSICFGR_HSITRIM_Msk              /*!< HSI clock trimming */
+#define RCC_HSICFGR_HSICAL_Pos                  (23U)
+#define RCC_HSICFGR_HSICAL_Msk                  (0x1FFUL << RCC_HSICFGR_HSICAL_Pos)   /*!< 0xFF800000 */
+#define RCC_HSICFGR_HSICAL                      RCC_HSICFGR_HSICAL_Msk               /*!< HSI clock calibration */
+
+/******************  Bit definition for RCC_HSIMCR register  ******************/
+#define RCC_HSIMCR_HSIREF_Pos                   (0U)
+#define RCC_HSIMCR_HSIREF_Msk                   (0x7FFUL << RCC_HSIMCR_HSIREF_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMCR_HSIREF                       RCC_HSIMCR_HSIREF_Msk                /*!< HSI clock-cycle counter reference value */
+#define RCC_HSIMCR_HSIDEV_Pos                   (16U)
+#define RCC_HSIMCR_HSIDEV_Msk                   (0x3FUL << RCC_HSIMCR_HSIDEV_Pos)     /*!< 0x003F0000 */
+#define RCC_HSIMCR_HSIDEV                       RCC_HSIMCR_HSIDEV_Msk                /*!< HSI clock count deviation value */
+#define RCC_HSIMCR_HSIMONEN_Pos                 (31U)
+#define RCC_HSIMCR_HSIMONEN_Msk                 (0x1UL << RCC_HSIMCR_HSIMONEN_Pos)    /*!< 0x80000000 */
+#define RCC_HSIMCR_HSIMONEN                     RCC_HSIMCR_HSIMONEN_Msk              /*!< HSI clock period monitor enable */
+
+/******************  Bit definition for RCC_HSIMSR register  ******************/
+#define RCC_HSIMSR_HSIVAL_Pos                   (0U)
+#define RCC_HSIMSR_HSIVAL_Msk                   (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMSR_HSIVAL                       RCC_HSIMSR_HSIVAL_Msk                /*!< HSI clock-cycle counter measured value */
+
+/*****************  Bit definition for RCC_HSECFGR register  ******************/
+#define RCC_HSECFGR_HSEDIV2SEL_Pos              (6U)
+#define RCC_HSECFGR_HSEDIV2SEL_Msk              (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */
+#define RCC_HSECFGR_HSEDIV2SEL                  RCC_HSECFGR_HSEDIV2SEL_Msk           /*!< HSE div2 clock source select */
+#define RCC_HSECFGR_HSECSSON_Pos                (7U)
+#define RCC_HSECFGR_HSECSSON_Msk                (0x1UL << RCC_HSECFGR_HSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_HSECFGR_HSECSSON                    RCC_HSECFGR_HSECSSON_Msk             /*!< HSE CSS enable */
+#define RCC_HSECFGR_HSECSSD_Pos                 (9U)
+#define RCC_HSECFGR_HSECSSD_Msk                 (0x1UL << RCC_HSECFGR_HSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_HSECFGR_HSECSSD                     RCC_HSECFGR_HSECSSD_Msk              /*!< HSE CSS failure detection */
+#define RCC_HSECFGR_HSECSSBYP_Pos               (10U)
+#define RCC_HSECFGR_HSECSSBYP_Msk               (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos)  /*!< 0x00000400 */
+#define RCC_HSECFGR_HSECSSBYP                   RCC_HSECFGR_HSECSSBYP_Msk            /*!< HSE CSS bypass enable */
+#define RCC_HSECFGR_HSECSSBPRE_Pos              (11U)
+#define RCC_HSECFGR_HSECSSBPRE_Msk              (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */
+#define RCC_HSECFGR_HSECSSBPRE                  RCC_HSECFGR_HSECSSBPRE_Msk           /*!< HSE CSS bypass divider */
+#define RCC_HSECFGR_HSECSSBPRE_0                (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */
+#define RCC_HSECFGR_HSECSSBPRE_1                (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */
+#define RCC_HSECFGR_HSECSSBPRE_2                (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */
+#define RCC_HSECFGR_HSECSSBPRE_3                (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */
+#define RCC_HSECFGR_HSEBYP_Pos                  (15U)
+#define RCC_HSECFGR_HSEBYP_Msk                  (0x1UL << RCC_HSECFGR_HSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_HSECFGR_HSEBYP                      RCC_HSECFGR_HSEBYP_Msk               /*!< HSE clock bypass */
+#define RCC_HSECFGR_HSEEXT_Pos                  (16U)
+#define RCC_HSECFGR_HSEEXT_Msk                  (0x1UL << RCC_HSECFGR_HSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_HSECFGR_HSEEXT                      RCC_HSECFGR_HSEEXT_Msk               /*!< HSE clock type in bypass mode */
+
+/****************  Bit definition for RCC_PLL1CFGR1 register  *****************/
+#define RCC_PLL1CFGR1_PLL1DIVN_Pos              (8U)
+#define RCC_PLL1CFGR1_PLL1DIVN_Msk              (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL1CFGR1_PLL1DIVN                  RCC_PLL1CFGR1_PLL1DIVN_Msk           /*!< PLL1 integer part for the VCO multiplication factor */
+#define RCC_PLL1CFGR1_PLL1DIVM_Pos              (20U)
+#define RCC_PLL1CFGR1_PLL1DIVM_Msk              (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL1CFGR1_PLL1DIVM                  RCC_PLL1CFGR1_PLL1DIVM_Msk           /*!< PLL1 reference input clock divide frequency ratio */
+#define RCC_PLL1CFGR1_PLL1BYP_Pos               (27U)
+#define RCC_PLL1CFGR1_PLL1BYP_Msk               (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL1CFGR1_PLL1BYP                   RCC_PLL1CFGR1_PLL1BYP_Msk            /*!< PLL1 bypass */
+#define RCC_PLL1CFGR1_PLL1SEL_Pos               (28U)
+#define RCC_PLL1CFGR1_PLL1SEL_Msk               (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL1CFGR1_PLL1SEL                   RCC_PLL1CFGR1_PLL1SEL_Msk            /*!< PLL1 source selection of the reference clock */
+#define RCC_PLL1CFGR1_PLL1SEL_0                 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_1                 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_2                 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL1CFGR2 register  *****************/
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos          (0U)
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC              RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk       /*!< PLL1 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL1CFGR3 register  *****************/
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos          (0U)
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL1CFGR3_PLL1MODSSRST              RCC_PLL1CFGR3_PLL1MODSSRST_Msk       /*!< PLL1 modulation spread spectrum reset */
+#define RCC_PLL1CFGR3_PLL1DACEN_Pos             (1U)
+#define RCC_PLL1CFGR3_PLL1DACEN_Msk             (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL1CFGR3_PLL1DACEN                 RCC_PLL1CFGR3_PLL1DACEN_Msk          /*!< PLL1 noise canceling DAC enable in fractional mode */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos          (2U)
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS              RCC_PLL1CFGR3_PLL1MODSSDIS_Msk       /*!< PLL1 modulation spread spectrum disable  */
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos           (3U)
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk           (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL1CFGR3_PLL1MODDSEN               RCC_PLL1CFGR3_PLL1MODDSEN_Msk        /*!< PLL1 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos          (4U)
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW              RCC_PLL1CFGR3_PLL1MODSPRDW_Msk       /*!< PLL1 modulation spread spectrum down */
+#define RCC_PLL1CFGR3_PLL1MODDIV_Pos            (8U)
+#define RCC_PLL1CFGR3_PLL1MODDIV_Msk            (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL1CFGR3_PLL1MODDIV                RCC_PLL1CFGR3_PLL1MODDIV_Msk         /*!< PLL1 modulation division frequency adjustment  */
+#define RCC_PLL1CFGR3_PLL1MODSPR_Pos            (16U)
+#define RCC_PLL1CFGR3_PLL1MODSPR_Msk            (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL1CFGR3_PLL1MODSPR                RCC_PLL1CFGR3_PLL1MODSPR_Msk         /*!< PLL1 modulation spread depth adjustment */
+#define RCC_PLL1CFGR3_PLL1PDIV2_Pos             (24U)
+#define RCC_PLL1CFGR3_PLL1PDIV2_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV2                 RCC_PLL1CFGR3_PLL1PDIV2_Msk          /*!< PLL1 VCO frequency divider level 2 */
+#define RCC_PLL1CFGR3_PLL1PDIV1_Pos             (27U)
+#define RCC_PLL1CFGR3_PLL1PDIV1_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV1                 RCC_PLL1CFGR3_PLL1PDIV1_Msk          /*!< PLL1 VCO frequency divider level 1 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos            (30U)
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk            (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN                RCC_PLL1CFGR3_PLL1PDIVEN_Msk         /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL2CFGR1 register  *****************/
+#define RCC_PLL2CFGR1_PLL2DIVN_Pos              (8U)
+#define RCC_PLL2CFGR1_PLL2DIVN_Msk              (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL2CFGR1_PLL2DIVN                  RCC_PLL2CFGR1_PLL2DIVN_Msk           /*!< PLL2 integer part for the VCO multiplication factor */
+#define RCC_PLL2CFGR1_PLL2DIVM_Pos              (20U)
+#define RCC_PLL2CFGR1_PLL2DIVM_Msk              (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL2CFGR1_PLL2DIVM                  RCC_PLL2CFGR1_PLL2DIVM_Msk           /*!< PLL2 reference input clock divide frequency ratio */
+#define RCC_PLL2CFGR1_PLL2BYP_Pos               (27U)
+#define RCC_PLL2CFGR1_PLL2BYP_Msk               (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL2CFGR1_PLL2BYP                   RCC_PLL2CFGR1_PLL2BYP_Msk            /*!< PLL2 bypass */
+#define RCC_PLL2CFGR1_PLL2SEL_Pos               (28U)
+#define RCC_PLL2CFGR1_PLL2SEL_Msk               (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL2CFGR1_PLL2SEL                   RCC_PLL2CFGR1_PLL2SEL_Msk            /*!< PLL2 source selection of the reference clock */
+#define RCC_PLL2CFGR1_PLL2SEL_0                 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_1                 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_2                 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL2CFGR2 register  *****************/
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos          (0U)
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC              RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk       /*!< PLL2 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL2CFGR3 register  *****************/
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos          (0U)
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL2CFGR3_PLL2MODSSRST              RCC_PLL2CFGR3_PLL2MODSSRST_Msk       /*!< PLL2 modulation spread spectrum reset */
+#define RCC_PLL2CFGR3_PLL2DACEN_Pos             (1U)
+#define RCC_PLL2CFGR3_PLL2DACEN_Msk             (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL2CFGR3_PLL2DACEN                 RCC_PLL2CFGR3_PLL2DACEN_Msk          /*!< PLL2 noise canceling DAC enable in fractional mode */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos          (2U)
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS              RCC_PLL2CFGR3_PLL2MODSSDIS_Msk       /*!< PLL2 modulation spread spectrum disable  */
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos           (3U)
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk           (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL2CFGR3_PLL2MODDSEN               RCC_PLL2CFGR3_PLL2MODDSEN_Msk        /*!< PLL2 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos          (4U)
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW              RCC_PLL2CFGR3_PLL2MODSPRDW_Msk       /*!< PLL2 modulation down spread */
+#define RCC_PLL2CFGR3_PLL2MODDIV_Pos            (8U)
+#define RCC_PLL2CFGR3_PLL2MODDIV_Msk            (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL2CFGR3_PLL2MODDIV                RCC_PLL2CFGR3_PLL2MODDIV_Msk         /*!< PLL2 modulation division frequency adjustment  */
+#define RCC_PLL2CFGR3_PLL2MODSPR_Pos            (16U)
+#define RCC_PLL2CFGR3_PLL2MODSPR_Msk            (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL2CFGR3_PLL2MODSPR                RCC_PLL2CFGR3_PLL2MODSPR_Msk         /*!< PLL2 modulation spread depth adjustment */
+#define RCC_PLL2CFGR3_PLL2PDIV2_Pos             (24U)
+#define RCC_PLL2CFGR3_PLL2PDIV2_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV2                 RCC_PLL2CFGR3_PLL2PDIV2_Msk          /*!< PLL2 VCO frequency divider level 2 */
+#define RCC_PLL2CFGR3_PLL2PDIV1_Pos             (27U)
+#define RCC_PLL2CFGR3_PLL2PDIV1_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV1                 RCC_PLL2CFGR3_PLL2PDIV1_Msk          /*!< PLL2 VCO frequency divider level 1 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos            (30U)
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk            (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN                RCC_PLL2CFGR3_PLL2PDIVEN_Msk         /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL3CFGR1 register  *****************/
+#define RCC_PLL3CFGR1_PLL3DIVN_Pos              (8U)
+#define RCC_PLL3CFGR1_PLL3DIVN_Msk              (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL3CFGR1_PLL3DIVN                  RCC_PLL3CFGR1_PLL3DIVN_Msk           /*!< PLL3 Integer part for the VCO multiplication factor */
+#define RCC_PLL3CFGR1_PLL3DIVM_Pos              (20U)
+#define RCC_PLL3CFGR1_PLL3DIVM_Msk              (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL3CFGR1_PLL3DIVM                  RCC_PLL3CFGR1_PLL3DIVM_Msk           /*!< PLL3 reference input clock divide frequency ratio */
+#define RCC_PLL3CFGR1_PLL3BYP_Pos               (27U)
+#define RCC_PLL3CFGR1_PLL3BYP_Msk               (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL3CFGR1_PLL3BYP                   RCC_PLL3CFGR1_PLL3BYP_Msk            /*!< PLL3 bypass */
+#define RCC_PLL3CFGR1_PLL3SEL_Pos               (28U)
+#define RCC_PLL3CFGR1_PLL3SEL_Msk               (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL3CFGR1_PLL3SEL                   RCC_PLL3CFGR1_PLL3SEL_Msk            /*!< PLL3 source selection of the reference clock */
+#define RCC_PLL3CFGR1_PLL3SEL_0                 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_1                 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_2                 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL3CFGR2 register  *****************/
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos          (0U)
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC              RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk       /*!< PLL3 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL3CFGR3 register  *****************/
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos          (0U)
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL3CFGR3_PLL3MODSSRST              RCC_PLL3CFGR3_PLL3MODSSRST_Msk       /*!< PLL3 modulation spread spectrum reset */
+#define RCC_PLL3CFGR3_PLL3DACEN_Pos             (1U)
+#define RCC_PLL3CFGR3_PLL3DACEN_Msk             (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL3CFGR3_PLL3DACEN                 RCC_PLL3CFGR3_PLL3DACEN_Msk          /*!< PLL3 noise canceling DAC enable in fractional mode */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos          (2U)
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS              RCC_PLL3CFGR3_PLL3MODSSDIS_Msk       /*!< PLL3 modulation spread spectrum disable  */
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos           (3U)
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk           (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL3CFGR3_PLL3MODDSEN               RCC_PLL3CFGR3_PLL3MODDSEN_Msk        /*!< PLL3 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos          (4U)
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW              RCC_PLL3CFGR3_PLL3MODSPRDW_Msk       /*!< PLL3 modulation down spread */
+#define RCC_PLL3CFGR3_PLL3MODDIV_Pos            (8U)
+#define RCC_PLL3CFGR3_PLL3MODDIV_Msk            (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL3CFGR3_PLL3MODDIV                RCC_PLL3CFGR3_PLL3MODDIV_Msk         /*!< PLL3 modulation division frequency adjustment  */
+#define RCC_PLL3CFGR3_PLL3MODSPR_Pos            (16U)
+#define RCC_PLL3CFGR3_PLL3MODSPR_Msk            (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL3CFGR3_PLL3MODSPR                RCC_PLL3CFGR3_PLL3MODSPR_Msk         /*!< PLL3 modulation spread depth adjustment */
+#define RCC_PLL3CFGR3_PLL3PDIV2_Pos             (24U)
+#define RCC_PLL3CFGR3_PLL3PDIV2_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV2                 RCC_PLL3CFGR3_PLL3PDIV2_Msk          /*!< PLL3 VCO frequency divider level 2 */
+#define RCC_PLL3CFGR3_PLL3PDIV1_Pos             (27U)
+#define RCC_PLL3CFGR3_PLL3PDIV1_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV1                 RCC_PLL3CFGR3_PLL3PDIV1_Msk          /*!< PLL3 VCO frequency divider level 1 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos            (30U)
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk            (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN                RCC_PLL3CFGR3_PLL3PDIVEN_Msk         /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL4CFGR1 register  *****************/
+#define RCC_PLL4CFGR1_PLL4DIVN_Pos              (8U)
+#define RCC_PLL4CFGR1_PLL4DIVN_Msk              (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL4CFGR1_PLL4DIVN                  RCC_PLL4CFGR1_PLL4DIVN_Msk           /*!< PLL4 integer part for the VCO multiplication factor */
+#define RCC_PLL4CFGR1_PLL4DIVM_Pos              (20U)
+#define RCC_PLL4CFGR1_PLL4DIVM_Msk              (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL4CFGR1_PLL4DIVM                  RCC_PLL4CFGR1_PLL4DIVM_Msk           /*!< PLL4 reference input clock divide frequency ratio */
+#define RCC_PLL4CFGR1_PLL4BYP_Pos               (27U)
+#define RCC_PLL4CFGR1_PLL4BYP_Msk               (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL4CFGR1_PLL4BYP                   RCC_PLL4CFGR1_PLL4BYP_Msk            /*!< PLL4 bypass */
+#define RCC_PLL4CFGR1_PLL4SEL_Pos               (28U)
+#define RCC_PLL4CFGR1_PLL4SEL_Msk               (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL4CFGR1_PLL4SEL                   RCC_PLL4CFGR1_PLL4SEL_Msk            /*!< PLL4 source selection of the reference clock */
+#define RCC_PLL4CFGR1_PLL4SEL_0                 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_1                 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_2                 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL4CFGR2 register  *****************/
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos          (0U)
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC              RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk       /*!< PLL4 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL4CFGR3 register  *****************/
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos          (0U)
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL4CFGR3_PLL4MODSSRST              RCC_PLL4CFGR3_PLL4MODSSRST_Msk       /*!< PLL4 modulation spread spectrum reset */
+#define RCC_PLL4CFGR3_PLL4DACEN_Pos             (1U)
+#define RCC_PLL4CFGR3_PLL4DACEN_Msk             (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL4CFGR3_PLL4DACEN                 RCC_PLL4CFGR3_PLL4DACEN_Msk          /*!< PLL4 noise canceling DAC enable in fractional mode */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos          (2U)
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS              RCC_PLL4CFGR3_PLL4MODSSDIS_Msk       /*!< PLL4 modulation spread spectrum disable  */
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos           (3U)
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk           (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL4CFGR3_PLL4MODDSEN               RCC_PLL4CFGR3_PLL4MODDSEN_Msk        /*!< PLL4 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos          (4U)
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW              RCC_PLL4CFGR3_PLL4MODSPRDW_Msk       /*!< PLL4 modulation down spread */
+#define RCC_PLL4CFGR3_PLL4MODDIV_Pos            (8U)
+#define RCC_PLL4CFGR3_PLL4MODDIV_Msk            (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL4CFGR3_PLL4MODDIV                RCC_PLL4CFGR3_PLL4MODDIV_Msk         /*!< PLL4 modulation division frequency adjustment  */
+#define RCC_PLL4CFGR3_PLL4MODSPR_Pos            (16U)
+#define RCC_PLL4CFGR3_PLL4MODSPR_Msk            (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL4CFGR3_PLL4MODSPR                RCC_PLL4CFGR3_PLL4MODSPR_Msk         /*!< PLL4 modulation spread depth adjustment */
+#define RCC_PLL4CFGR3_PLL4PDIV2_Pos             (24U)
+#define RCC_PLL4CFGR3_PLL4PDIV2_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV2                 RCC_PLL4CFGR3_PLL4PDIV2_Msk          /*!< PLL4 VCO frequency divider level 2 */
+#define RCC_PLL4CFGR3_PLL4PDIV1_Pos             (27U)
+#define RCC_PLL4CFGR3_PLL4PDIV1_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV1                 RCC_PLL4CFGR3_PLL4PDIV1_Msk          /*!< PLL4 VCO frequency divider level 1 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos            (30U)
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk            (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN                RCC_PLL4CFGR3_PLL4PDIVEN_Msk         /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/*****************  Bit definition for RCC_IC1CFGR register  ******************/
+#define RCC_IC1CFGR_IC1INT_Pos                  (16U)
+#define RCC_IC1CFGR_IC1INT_Msk                  (0xFFUL << RCC_IC1CFGR_IC1INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC1CFGR_IC1INT                      RCC_IC1CFGR_IC1INT_Msk               /*!< Divider IC1 integer division factor */
+#define RCC_IC1CFGR_IC1SEL_Pos                  (28U)
+#define RCC_IC1CFGR_IC1SEL_Msk                  (0x3UL << RCC_IC1CFGR_IC1SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC1CFGR_IC1SEL                      RCC_IC1CFGR_IC1SEL_Msk               /*!< Divider IC1 source selection */
+#define RCC_IC1CFGR_IC1SEL_0                    (0x1UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC1CFGR_IC1SEL_1                    (0x2UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC2CFGR register  ******************/
+#define RCC_IC2CFGR_IC2INT_Pos                  (16U)
+#define RCC_IC2CFGR_IC2INT_Msk                  (0xFFUL << RCC_IC2CFGR_IC2INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC2CFGR_IC2INT                      RCC_IC2CFGR_IC2INT_Msk               /*!< Divider IC2 integer division factor */
+#define RCC_IC2CFGR_IC2SEL_Pos                  (28U)
+#define RCC_IC2CFGR_IC2SEL_Msk                  (0x3UL << RCC_IC2CFGR_IC2SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC2CFGR_IC2SEL                      RCC_IC2CFGR_IC2SEL_Msk               /*!< Divider IC2 source selection */
+#define RCC_IC2CFGR_IC2SEL_0                    (0x1UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC2CFGR_IC2SEL_1                    (0x2UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC3CFGR register  ******************/
+#define RCC_IC3CFGR_IC3INT_Pos                  (16U)
+#define RCC_IC3CFGR_IC3INT_Msk                  (0xFFUL << RCC_IC3CFGR_IC3INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC3CFGR_IC3INT                      RCC_IC3CFGR_IC3INT_Msk               /*!< Divider IC3 integer division factor */
+#define RCC_IC3CFGR_IC3SEL_Pos                  (28U)
+#define RCC_IC3CFGR_IC3SEL_Msk                  (0x3UL << RCC_IC3CFGR_IC3SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC3CFGR_IC3SEL                      RCC_IC3CFGR_IC3SEL_Msk               /*!< Divider IC3 source selection */
+#define RCC_IC3CFGR_IC3SEL_0                    (0x1UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC3CFGR_IC3SEL_1                    (0x2UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC4CFGR register  ******************/
+#define RCC_IC4CFGR_IC4INT_Pos                  (16U)
+#define RCC_IC4CFGR_IC4INT_Msk                  (0xFFUL << RCC_IC4CFGR_IC4INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC4CFGR_IC4INT                      RCC_IC4CFGR_IC4INT_Msk               /*!< Divider IC4 integer division factor */
+#define RCC_IC4CFGR_IC4SEL_Pos                  (28U)
+#define RCC_IC4CFGR_IC4SEL_Msk                  (0x3UL << RCC_IC4CFGR_IC4SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC4CFGR_IC4SEL                      RCC_IC4CFGR_IC4SEL_Msk               /*!< Divider IC4 source selection */
+#define RCC_IC4CFGR_IC4SEL_0                    (0x1UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC4CFGR_IC4SEL_1                    (0x2UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC5CFGR register  ******************/
+#define RCC_IC5CFGR_IC5INT_Pos                  (16U)
+#define RCC_IC5CFGR_IC5INT_Msk                  (0xFFUL << RCC_IC5CFGR_IC5INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC5CFGR_IC5INT                      RCC_IC5CFGR_IC5INT_Msk               /*!< Divider IC5 integer division factor */
+#define RCC_IC5CFGR_IC5SEL_Pos                  (28U)
+#define RCC_IC5CFGR_IC5SEL_Msk                  (0x3UL << RCC_IC5CFGR_IC5SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC5CFGR_IC5SEL                      RCC_IC5CFGR_IC5SEL_Msk               /*!< Divider IC5 source selection */
+#define RCC_IC5CFGR_IC5SEL_0                    (0x1UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC5CFGR_IC5SEL_1                    (0x2UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC6CFGR register  ******************/
+#define RCC_IC6CFGR_IC6INT_Pos                  (16U)
+#define RCC_IC6CFGR_IC6INT_Msk                  (0xFFUL << RCC_IC6CFGR_IC6INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC6CFGR_IC6INT                      RCC_IC6CFGR_IC6INT_Msk               /*!< Divider IC6 integer division factor */
+#define RCC_IC6CFGR_IC6SEL_Pos                  (28U)
+#define RCC_IC6CFGR_IC6SEL_Msk                  (0x3UL << RCC_IC6CFGR_IC6SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC6CFGR_IC6SEL                      RCC_IC6CFGR_IC6SEL_Msk               /*!< Divider IC6 source selection */
+#define RCC_IC6CFGR_IC6SEL_0                    (0x1UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC6CFGR_IC6SEL_1                    (0x2UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC7CFGR register  ******************/
+#define RCC_IC7CFGR_IC7INT_Pos                  (16U)
+#define RCC_IC7CFGR_IC7INT_Msk                  (0xFFUL << RCC_IC7CFGR_IC7INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC7CFGR_IC7INT                      RCC_IC7CFGR_IC7INT_Msk               /*!< Divider IC7 integer division factor */
+#define RCC_IC7CFGR_IC7SEL_Pos                  (28U)
+#define RCC_IC7CFGR_IC7SEL_Msk                  (0x3UL << RCC_IC7CFGR_IC7SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC7CFGR_IC7SEL                      RCC_IC7CFGR_IC7SEL_Msk               /*!< Divider IC7 source selection */
+#define RCC_IC7CFGR_IC7SEL_0                    (0x1UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC7CFGR_IC7SEL_1                    (0x2UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC8CFGR register  ******************/
+#define RCC_IC8CFGR_IC8INT_Pos                  (16U)
+#define RCC_IC8CFGR_IC8INT_Msk                  (0xFFUL << RCC_IC8CFGR_IC8INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC8CFGR_IC8INT                      RCC_IC8CFGR_IC8INT_Msk               /*!< Divider IC8 integer division factor */
+#define RCC_IC8CFGR_IC8SEL_Pos                  (28U)
+#define RCC_IC8CFGR_IC8SEL_Msk                  (0x3UL << RCC_IC8CFGR_IC8SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC8CFGR_IC8SEL                      RCC_IC8CFGR_IC8SEL_Msk               /*!< Divider IC8 source selection */
+#define RCC_IC8CFGR_IC8SEL_0                    (0x1UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC8CFGR_IC8SEL_1                    (0x2UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC9CFGR register  ******************/
+#define RCC_IC9CFGR_IC9INT_Pos                  (16U)
+#define RCC_IC9CFGR_IC9INT_Msk                  (0xFFUL << RCC_IC9CFGR_IC9INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC9CFGR_IC9INT                      RCC_IC9CFGR_IC9INT_Msk               /*!< Divider IC9 integer division factor */
+#define RCC_IC9CFGR_IC9SEL_Pos                  (28U)
+#define RCC_IC9CFGR_IC9SEL_Msk                  (0x3UL << RCC_IC9CFGR_IC9SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC9CFGR_IC9SEL                      RCC_IC9CFGR_IC9SEL_Msk               /*!< Divider IC9 source selection */
+#define RCC_IC9CFGR_IC9SEL_0                    (0x1UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC9CFGR_IC9SEL_1                    (0x2UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC10CFGR register  *****************/
+#define RCC_IC10CFGR_IC10INT_Pos                (16U)
+#define RCC_IC10CFGR_IC10INT_Msk                (0xFFUL << RCC_IC10CFGR_IC10INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC10CFGR_IC10INT                    RCC_IC10CFGR_IC10INT_Msk             /*!< Divider IC10 integer division factor */
+#define RCC_IC10CFGR_IC10SEL_Pos                (28U)
+#define RCC_IC10CFGR_IC10SEL_Msk                (0x3UL << RCC_IC10CFGR_IC10SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC10CFGR_IC10SEL                    RCC_IC10CFGR_IC10SEL_Msk             /*!< Divider IC10 source selection */
+#define RCC_IC10CFGR_IC10SEL_0                  (0x1UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC10CFGR_IC10SEL_1                  (0x2UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC11CFGR register  *****************/
+#define RCC_IC11CFGR_IC11INT_Pos                (16U)
+#define RCC_IC11CFGR_IC11INT_Msk                (0xFFUL << RCC_IC11CFGR_IC11INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC11CFGR_IC11INT                    RCC_IC11CFGR_IC11INT_Msk             /*!< Divider IC11 integer division factor */
+#define RCC_IC11CFGR_IC11SEL_Pos                (28U)
+#define RCC_IC11CFGR_IC11SEL_Msk                (0x3UL << RCC_IC11CFGR_IC11SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC11CFGR_IC11SEL                    RCC_IC11CFGR_IC11SEL_Msk             /*!< Divider IC11 source selection */
+#define RCC_IC11CFGR_IC11SEL_0                  (0x1UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC11CFGR_IC11SEL_1                  (0x2UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC12CFGR register  *****************/
+#define RCC_IC12CFGR_IC12INT_Pos                (16U)
+#define RCC_IC12CFGR_IC12INT_Msk                (0xFFUL << RCC_IC12CFGR_IC12INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC12CFGR_IC12INT                    RCC_IC12CFGR_IC12INT_Msk             /*!< Divider IC12 integer division factor */
+#define RCC_IC12CFGR_IC12SEL_Pos                (28U)
+#define RCC_IC12CFGR_IC12SEL_Msk                (0x3UL << RCC_IC12CFGR_IC12SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC12CFGR_IC12SEL                    RCC_IC12CFGR_IC12SEL_Msk             /*!< Divider IC12 source selection */
+#define RCC_IC12CFGR_IC12SEL_0                  (0x1UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC12CFGR_IC12SEL_1                  (0x2UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC13CFGR register  *****************/
+#define RCC_IC13CFGR_IC13INT_Pos                (16U)
+#define RCC_IC13CFGR_IC13INT_Msk                (0xFFUL << RCC_IC13CFGR_IC13INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC13CFGR_IC13INT                    RCC_IC13CFGR_IC13INT_Msk             /*!< Divider IC13 integer division factor */
+#define RCC_IC13CFGR_IC13SEL_Pos                (28U)
+#define RCC_IC13CFGR_IC13SEL_Msk                (0x3UL << RCC_IC13CFGR_IC13SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC13CFGR_IC13SEL                    RCC_IC13CFGR_IC13SEL_Msk             /*!< Divider IC13 source selection */
+#define RCC_IC13CFGR_IC13SEL_0                  (0x1UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC13CFGR_IC13SEL_1                  (0x2UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC14CFGR register  *****************/
+#define RCC_IC14CFGR_IC14INT_Pos                (16U)
+#define RCC_IC14CFGR_IC14INT_Msk                (0xFFUL << RCC_IC14CFGR_IC14INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC14CFGR_IC14INT                    RCC_IC14CFGR_IC14INT_Msk             /*!< Divider IC14 integer division factor */
+#define RCC_IC14CFGR_IC14SEL_Pos                (28U)
+#define RCC_IC14CFGR_IC14SEL_Msk                (0x3UL << RCC_IC14CFGR_IC14SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC14CFGR_IC14SEL                    RCC_IC14CFGR_IC14SEL_Msk             /*!< Divider IC14 source selection */
+#define RCC_IC14CFGR_IC14SEL_0                  (0x1UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC14CFGR_IC14SEL_1                  (0x2UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC15CFGR register  *****************/
+#define RCC_IC15CFGR_IC15INT_Pos                (16U)
+#define RCC_IC15CFGR_IC15INT_Msk                (0xFFUL << RCC_IC15CFGR_IC15INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC15CFGR_IC15INT                    RCC_IC15CFGR_IC15INT_Msk             /*!< Divider IC15 integer division factor */
+#define RCC_IC15CFGR_IC15SEL_Pos                (28U)
+#define RCC_IC15CFGR_IC15SEL_Msk                (0x3UL << RCC_IC15CFGR_IC15SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC15CFGR_IC15SEL                    RCC_IC15CFGR_IC15SEL_Msk             /*!< Divider IC15 source selection */
+#define RCC_IC15CFGR_IC15SEL_0                  (0x1UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC15CFGR_IC15SEL_1                  (0x2UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC16CFGR register  *****************/
+#define RCC_IC16CFGR_IC16INT_Pos                (16U)
+#define RCC_IC16CFGR_IC16INT_Msk                (0xFFUL << RCC_IC16CFGR_IC16INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC16CFGR_IC16INT                    RCC_IC16CFGR_IC16INT_Msk             /*!< Divider IC16 integer division factor */
+#define RCC_IC16CFGR_IC16SEL_Pos                (28U)
+#define RCC_IC16CFGR_IC16SEL_Msk                (0x3UL << RCC_IC16CFGR_IC16SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC16CFGR_IC16SEL                    RCC_IC16CFGR_IC16SEL_Msk             /*!< Divider IC16 source selection */
+#define RCC_IC16CFGR_IC16SEL_0                  (0x1UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC16CFGR_IC16SEL_1                  (0x2UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC17CFGR register  *****************/
+#define RCC_IC17CFGR_IC17INT_Pos                (16U)
+#define RCC_IC17CFGR_IC17INT_Msk                (0xFFUL << RCC_IC17CFGR_IC17INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC17CFGR_IC17INT                    RCC_IC17CFGR_IC17INT_Msk             /*!< Divider IC17 integer division factor */
+#define RCC_IC17CFGR_IC17SEL_Pos                (28U)
+#define RCC_IC17CFGR_IC17SEL_Msk                (0x3UL << RCC_IC17CFGR_IC17SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC17CFGR_IC17SEL                    RCC_IC17CFGR_IC17SEL_Msk             /*!< Divider IC17 source selection */
+#define RCC_IC17CFGR_IC17SEL_0                  (0x1UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC17CFGR_IC17SEL_1                  (0x2UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC18CFGR register  *****************/
+#define RCC_IC18CFGR_IC18INT_Pos                (16U)
+#define RCC_IC18CFGR_IC18INT_Msk                (0xFFUL << RCC_IC18CFGR_IC18INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC18CFGR_IC18INT                    RCC_IC18CFGR_IC18INT_Msk             /*!< Divider IC18 integer division factor */
+#define RCC_IC18CFGR_IC18SEL_Pos                (28U)
+#define RCC_IC18CFGR_IC18SEL_Msk                (0x3UL << RCC_IC18CFGR_IC18SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC18CFGR_IC18SEL                    RCC_IC18CFGR_IC18SEL_Msk             /*!< Divider IC18 source selection */
+#define RCC_IC18CFGR_IC18SEL_0                  (0x1UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC18CFGR_IC18SEL_1                  (0x2UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC19CFGR register  *****************/
+#define RCC_IC19CFGR_IC19INT_Pos                (16U)
+#define RCC_IC19CFGR_IC19INT_Msk                (0xFFUL << RCC_IC19CFGR_IC19INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC19CFGR_IC19INT                    RCC_IC19CFGR_IC19INT_Msk             /*!< Divider IC19 integer division factor */
+#define RCC_IC19CFGR_IC19SEL_Pos                (28U)
+#define RCC_IC19CFGR_IC19SEL_Msk                (0x3UL << RCC_IC19CFGR_IC19SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC19CFGR_IC19SEL                    RCC_IC19CFGR_IC19SEL_Msk             /*!< Divider IC19 source selection */
+#define RCC_IC19CFGR_IC19SEL_0                  (0x1UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC19CFGR_IC19SEL_1                  (0x2UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC20CFGR register  *****************/
+#define RCC_IC20CFGR_IC20INT_Pos                (16U)
+#define RCC_IC20CFGR_IC20INT_Msk                (0xFFUL << RCC_IC20CFGR_IC20INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC20CFGR_IC20INT                    RCC_IC20CFGR_IC20INT_Msk             /*!< Divider IC20 integer division factor */
+#define RCC_IC20CFGR_IC20SEL_Pos                (28U)
+#define RCC_IC20CFGR_IC20SEL_Msk                (0x3UL << RCC_IC20CFGR_IC20SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC20CFGR_IC20SEL                    RCC_IC20CFGR_IC20SEL_Msk             /*!< Divider IC20 source selection */
+#define RCC_IC20CFGR_IC20SEL_0                  (0x1UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC20CFGR_IC20SEL_1                  (0x2UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x20000000 */
+
+/*******************  Bit definition for RCC_CIER register  *******************/
+#define RCC_CIER_LSIRDYIE_Pos                   (0U)
+#define RCC_CIER_LSIRDYIE_Msk                   (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                       RCC_CIER_LSIRDYIE_Msk                /*!< LSI ready interrupt enable */
+#define RCC_CIER_LSERDYIE_Pos                   (1U)
+#define RCC_CIER_LSERDYIE_Msk                   (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                       RCC_CIER_LSERDYIE_Msk                /*!< LSE ready interrupt enable */
+#define RCC_CIER_MSIRDYIE_Pos                   (2U)
+#define RCC_CIER_MSIRDYIE_Msk                   (0x1UL << RCC_CIER_MSIRDYIE_Pos)      /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                       RCC_CIER_MSIRDYIE_Msk                /*!< MSI ready interrupt enable */
+#define RCC_CIER_HSIRDYIE_Pos                   (3U)
+#define RCC_CIER_HSIRDYIE_Msk                   (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                       RCC_CIER_HSIRDYIE_Msk                /*!< HSI ready interrupt enable */
+#define RCC_CIER_HSERDYIE_Pos                   (4U)
+#define RCC_CIER_HSERDYIE_Msk                   (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                       RCC_CIER_HSERDYIE_Msk                /*!< HSE ready interrupt enable */
+#define RCC_CIER_PLL1RDYIE_Pos                  (8U)
+#define RCC_CIER_PLL1RDYIE_Msk                  (0x1UL << RCC_CIER_PLL1RDYIE_Pos)     /*!< 0x00000100 */
+#define RCC_CIER_PLL1RDYIE                      RCC_CIER_PLL1RDYIE_Msk               /*!< PLL1 ready interrupt enable */
+#define RCC_CIER_PLL2RDYIE_Pos                  (9U)
+#define RCC_CIER_PLL2RDYIE_Msk                  (0x1UL << RCC_CIER_PLL2RDYIE_Pos)     /*!< 0x00000200 */
+#define RCC_CIER_PLL2RDYIE                      RCC_CIER_PLL2RDYIE_Msk               /*!< PLL2 ready interrupt enable */
+#define RCC_CIER_PLL3RDYIE_Pos                  (10U)
+#define RCC_CIER_PLL3RDYIE_Msk                  (0x1UL << RCC_CIER_PLL3RDYIE_Pos)     /*!< 0x00000400 */
+#define RCC_CIER_PLL3RDYIE                      RCC_CIER_PLL3RDYIE_Msk               /*!< PLL3 ready interrupt enable */
+#define RCC_CIER_PLL4RDYIE_Pos                  (11U)
+#define RCC_CIER_PLL4RDYIE_Msk                  (0x1UL << RCC_CIER_PLL4RDYIE_Pos)     /*!< 0x00000800 */
+#define RCC_CIER_PLL4RDYIE                      RCC_CIER_PLL4RDYIE_Msk               /*!< PLL4 ready interrupt enable */
+#define RCC_CIER_LSECSSIE_Pos                   (16U)
+#define RCC_CIER_LSECSSIE_Msk                   (0x1UL << RCC_CIER_LSECSSIE_Pos)      /*!< 0x00010000 */
+#define RCC_CIER_LSECSSIE                       RCC_CIER_LSECSSIE_Msk                /*!< LSE CSS interrupt enable */
+#define RCC_CIER_HSECSSIE_Pos                   (17U)
+#define RCC_CIER_HSECSSIE_Msk                   (0x1UL << RCC_CIER_HSECSSIE_Pos)      /*!< 0x00020000 */
+#define RCC_CIER_HSECSSIE                       RCC_CIER_HSECSSIE_Msk                /*!< HSE CSS interrupt enable */
+#define RCC_CIER_WKUPIE_Pos                     (24U)
+#define RCC_CIER_WKUPIE_Msk                     (0x1UL << RCC_CIER_WKUPIE_Pos)        /*!< 0x01000000 */
+#define RCC_CIER_WKUPIE                         RCC_CIER_WKUPIE_Msk                  /*!< CPU wake-up from Stop interrupt enable */
+
+/*******************  Bit definition for RCC_CIFR register  *******************/
+#define RCC_CIFR_LSIRDYF_Pos                    (0U)
+#define RCC_CIFR_LSIRDYF_Msk                    (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                        RCC_CIFR_LSIRDYF_Msk                 /*!< LSI ready interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos                    (1U)
+#define RCC_CIFR_LSERDYF_Msk                    (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                        RCC_CIFR_LSERDYF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos                    (2U)
+#define RCC_CIFR_MSIRDYF_Msk                    (0x1UL << RCC_CIFR_MSIRDYF_Pos)       /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                        RCC_CIFR_MSIRDYF_Msk                 /*!< MSI ready interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos                    (3U)
+#define RCC_CIFR_HSIRDYF_Msk                    (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                        RCC_CIFR_HSIRDYF_Msk                 /*!< HSI ready interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos                    (4U)
+#define RCC_CIFR_HSERDYF_Msk                    (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                        RCC_CIFR_HSERDYF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_PLL1RDYF_Pos                   (8U)
+#define RCC_CIFR_PLL1RDYF_Msk                   (0x1UL << RCC_CIFR_PLL1RDYF_Pos)      /*!< 0x00000100 */
+#define RCC_CIFR_PLL1RDYF                       RCC_CIFR_PLL1RDYF_Msk                /*!< PLL1 ready interrupt flag */
+#define RCC_CIFR_PLL2RDYF_Pos                   (9U)
+#define RCC_CIFR_PLL2RDYF_Msk                   (0x1UL << RCC_CIFR_PLL2RDYF_Pos)      /*!< 0x00000200 */
+#define RCC_CIFR_PLL2RDYF                       RCC_CIFR_PLL2RDYF_Msk                /*!< PLL2 ready interrupt flag */
+#define RCC_CIFR_PLL3RDYF_Pos                   (10U)
+#define RCC_CIFR_PLL3RDYF_Msk                   (0x1UL << RCC_CIFR_PLL3RDYF_Pos)      /*!< 0x00000400 */
+#define RCC_CIFR_PLL3RDYF                       RCC_CIFR_PLL3RDYF_Msk                /*!< PLL3 ready interrupt flag */
+#define RCC_CIFR_PLL4RDYF_Pos                   (11U)
+#define RCC_CIFR_PLL4RDYF_Msk                   (0x1UL << RCC_CIFR_PLL4RDYF_Pos)      /*!< 0x00000800 */
+#define RCC_CIFR_PLL4RDYF                       RCC_CIFR_PLL4RDYF_Msk                /*!< PLL4 ready interrupt flag */
+#define RCC_CIFR_LSECSSF_Pos                    (16U)
+#define RCC_CIFR_LSECSSF_Msk                    (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00010000 */
+#define RCC_CIFR_LSECSSF                        RCC_CIFR_LSECSSF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_HSECSSF_Pos                    (17U)
+#define RCC_CIFR_HSECSSF_Msk                    (0x1UL << RCC_CIFR_HSECSSF_Pos)       /*!< 0x00020000 */
+#define RCC_CIFR_HSECSSF                        RCC_CIFR_HSECSSF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_WKUPF_Pos                      (24U)
+#define RCC_CIFR_WKUPF_Msk                      (0x1UL << RCC_CIFR_WKUPF_Pos)         /*!< 0x01000000 */
+#define RCC_CIFR_WKUPF                          RCC_CIFR_WKUPF_Msk                   /*!< CPU wake-up from Stop interrupt flag */
+
+/*******************  Bit definition for RCC_CICR register  *******************/
+#define RCC_CICR_LSIRDYC_Pos                    (0U)
+#define RCC_CICR_LSIRDYC_Msk                    (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                        RCC_CICR_LSIRDYC_Msk                 /*!< LSI ready interrupt clear */
+#define RCC_CICR_LSERDYC_Pos                    (1U)
+#define RCC_CICR_LSERDYC_Msk                    (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                        RCC_CICR_LSERDYC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_MSIRDYC_Pos                    (2U)
+#define RCC_CICR_MSIRDYC_Msk                    (0x1UL << RCC_CICR_MSIRDYC_Pos)       /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                        RCC_CICR_MSIRDYC_Msk                 /*!< MSI ready interrupt clear */
+#define RCC_CICR_HSIRDYC_Pos                    (3U)
+#define RCC_CICR_HSIRDYC_Msk                    (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                        RCC_CICR_HSIRDYC_Msk                 /*!< HSI ready interrupt clear */
+#define RCC_CICR_HSERDYC_Pos                    (4U)
+#define RCC_CICR_HSERDYC_Msk                    (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                        RCC_CICR_HSERDYC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_PLL1RDYC_Pos                   (8U)
+#define RCC_CICR_PLL1RDYC_Msk                   (0x1UL << RCC_CICR_PLL1RDYC_Pos)      /*!< 0x00000100 */
+#define RCC_CICR_PLL1RDYC                       RCC_CICR_PLL1RDYC_Msk                /*!< PLL1 ready interrupt clear */
+#define RCC_CICR_PLL2RDYC_Pos                   (9U)
+#define RCC_CICR_PLL2RDYC_Msk                   (0x1UL << RCC_CICR_PLL2RDYC_Pos)      /*!< 0x00000200 */
+#define RCC_CICR_PLL2RDYC                       RCC_CICR_PLL2RDYC_Msk                /*!< PLL2 ready interrupt clear */
+#define RCC_CICR_PLL3RDYC_Pos                   (10U)
+#define RCC_CICR_PLL3RDYC_Msk                   (0x1UL << RCC_CICR_PLL3RDYC_Pos)      /*!< 0x00000400 */
+#define RCC_CICR_PLL3RDYC                       RCC_CICR_PLL3RDYC_Msk                /*!< PLL3 ready interrupt clear */
+#define RCC_CICR_PLL4RDYC_Pos                   (11U)
+#define RCC_CICR_PLL4RDYC_Msk                   (0x1UL << RCC_CICR_PLL4RDYC_Pos)      /*!< 0x00000800 */
+#define RCC_CICR_PLL4RDYC                       RCC_CICR_PLL4RDYC_Msk                /*!< PLL4 ready interrupt clear */
+#define RCC_CICR_LSECSSC_Pos                    (16U)
+#define RCC_CICR_LSECSSC_Msk                    (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00010000 */
+#define RCC_CICR_LSECSSC                        RCC_CICR_LSECSSC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_HSECSSC_Pos                    (17U)
+#define RCC_CICR_HSECSSC_Msk                    (0x1UL << RCC_CICR_HSECSSC_Pos)       /*!< 0x00020000 */
+#define RCC_CICR_HSECSSC                        RCC_CICR_HSECSSC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_WKUPFC_Pos                     (24U)
+#define RCC_CICR_WKUPFC_Msk                     (0x1UL << RCC_CICR_WKUPFC_Pos)        /*!< 0x01000000 */
+#define RCC_CICR_WKUPFC                         RCC_CICR_WKUPFC_Msk                  /*!< CPU wake-up ready interrupt clear */
+
+/******************  Bit definition for RCC_CCIPR1 register  ******************/
+#define RCC_CCIPR1_ADF1SEL_Pos                  (0U)
+#define RCC_CCIPR1_ADF1SEL_Msk                  (0x7UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR1_ADF1SEL                      RCC_CCIPR1_ADF1SEL_Msk                            /*!< Source selection for the ADF1 kernel clock */
+#define RCC_CCIPR1_ADF1SEL_0                    (0x1UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR1_ADF1SEL_1                    (0x2UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR1_ADF1SEL_2                    (0x4UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR1_ADC12SEL_Pos                 (4U)
+#define RCC_CCIPR1_ADC12SEL_Msk                 (0x7UL << RCC_CCIPR1_ADC12SEL_Pos)                 /*!< 0x00000070 */
+#define RCC_CCIPR1_ADC12SEL                     RCC_CCIPR1_ADC12SEL_Msk                           /*!< Source selection for the ADC12 kernel clock */
+#define RCC_CCIPR1_ADC12SEL_0                   (0x1UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR1_ADC12SEL_1                   (0x2UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR1_ADC12SEL_2                   (0x4UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000040 */
+#define RCC_CCIPR1_ADCPRE_Pos                   (8U)
+#define RCC_CCIPR1_ADCPRE_Msk                   (0xFFUL << RCC_CCIPR1_ADCPRE_Pos)                  /*!< 0x0000FF00 */
+#define RCC_CCIPR1_ADCPRE                       RCC_CCIPR1_ADCPRE_Msk                             /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */
+#define RCC_CCIPR1_ADCPRE_0                     (0x1UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR1_ADCPRE_1                     (0x2UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR1_ADCPRE_2                     (0x4UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000400 */
+#define RCC_CCIPR1_ADCPRE_3                     (0x8UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000800 */
+#define RCC_CCIPR1_ADCPRE_4                     (0x10UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR1_ADCPRE_5                     (0x20UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR1_ADCPRE_6                     (0x40UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR1_ADCPRE_7                     (0x80UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR1_DCMIPPSEL_Pos                (20U)
+#define RCC_CCIPR1_DCMIPPSEL_Msk                (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos)                /*!< 0x00300000 */
+#define RCC_CCIPR1_DCMIPPSEL                    RCC_CCIPR1_DCMIPPSEL_Msk                          /*!< Source selection for the DCMIPP kernel clock */
+#define RCC_CCIPR1_DCMIPPSEL_0                  (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00100000 */
+#define RCC_CCIPR1_DCMIPPSEL_1                  (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00200000 */
+
+/******************  Bit definition for RCC_CCIPR2 register  ******************/
+#define RCC_CCIPR2_ETH1PTPSEL_Pos               (0U)
+#define RCC_CCIPR2_ETH1PTPSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000003 */
+#define RCC_CCIPR2_ETH1PTPSEL                   RCC_CCIPR2_ETH1PTPSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1PTPSEL_0                 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR2_ETH1PTPSEL_1                 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR2_ETH1PTPDIV_Pos               (4U)
+#define RCC_CCIPR2_ETH1PTPDIV_Msk               (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos)               /*!< 0x000000F0 */
+#define RCC_CCIPR2_ETH1PTPDIV                   RCC_CCIPR2_ETH1PTPDIV_Msk                         /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */
+#define RCC_CCIPR2_ETH1PTPDIV_0                 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR2_ETH1PTPDIV_1                 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR2_ETH1PTPDIV_2                 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR2_ETH1PTPDIV_3                 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000080 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos           (8U)
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk           (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos)           /*!< 0x00000100 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK               RCC_CCIPR2_ETH1PWRDOWNACK_Msk                     /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1CLKSEL_Pos               (12U)
+#define RCC_CCIPR2_ETH1CLKSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR2_ETH1CLKSEL                   RCC_CCIPR2_ETH1CLKSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1CLKSEL_0                 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR2_ETH1CLKSEL_1                 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR2_ETH1SEL_Pos                  (16U)
+#define RCC_CCIPR2_ETH1SEL_Msk                  (0x7UL << RCC_CCIPR2_ETH1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR2_ETH1SEL                      RCC_CCIPR2_ETH1SEL_Msk                            /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1SEL_0                    (0x1UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR2_ETH1SEL_1                    (0x2UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR2_ETH1SEL_2                    (0x4UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL_Pos            (20U)
+#define RCC_CCIPR2_ETH1REFCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos)            /*!< 0x00100000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL                RCC_CCIPR2_ETH1REFCLKSEL_Msk                      /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos            (24U)
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR2_ETH1GTXCLKSEL                RCC_CCIPR2_ETH1GTXCLKSEL_Msk                      /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR3 register  ******************/
+#define RCC_CCIPR3_FDCANSEL_Pos                 (0U)
+#define RCC_CCIPR3_FDCANSEL_Msk                 (0x3UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR3_FDCANSEL                     RCC_CCIPR3_FDCANSEL_Msk                           /*!< Source selection for the FDCAN kernel clock */
+#define RCC_CCIPR3_FDCANSEL_0                   (0x1UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR3_FDCANSEL_1                   (0x2UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR3_FMCSEL_Pos                   (4U)
+#define RCC_CCIPR3_FMCSEL_Msk                   (0x3UL << RCC_CCIPR3_FMCSEL_Pos)                   /*!< 0x00000030 */
+#define RCC_CCIPR3_FMCSEL                       RCC_CCIPR3_FMCSEL_Msk                             /*!< Source selection for the FMC kernel clock */
+#define RCC_CCIPR3_FMCSEL_0                     (0x1UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000010 */
+#define RCC_CCIPR3_FMCSEL_1                     (0x2UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000020 */
+#define RCC_CCIPR3_DFTSEL_Pos                   (8U)
+#define RCC_CCIPR3_DFTSEL_Msk                   (0x1UL << RCC_CCIPR3_DFTSEL_Pos)                   /*!< 0x00000100 */
+#define RCC_CCIPR3_DFTSEL                       RCC_CCIPR3_DFTSEL_Msk                             /*!< Source selection for the DFT kernel clock */
+
+/******************  Bit definition for RCC_CCIPR4 register  ******************/
+#define RCC_CCIPR4_I2C1SEL_Pos                  (0U)
+#define RCC_CCIPR4_I2C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR4_I2C1SEL                      RCC_CCIPR4_I2C1SEL_Msk                            /*!< Source selection for the I2C1 kernel clock */
+#define RCC_CCIPR4_I2C1SEL_0                    (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR4_I2C1SEL_1                    (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR4_I2C1SEL_2                    (0x4UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR4_I2C2SEL_Pos                  (4U)
+#define RCC_CCIPR4_I2C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C2SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR4_I2C2SEL                      RCC_CCIPR4_I2C2SEL_Msk                            /*!< Source selection for the I2C2 kernel clock */
+#define RCC_CCIPR4_I2C2SEL_0                    (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR4_I2C2SEL_1                    (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR4_I2C2SEL_2                    (0x4UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR4_I2C3SEL_Pos                  (8U)
+#define RCC_CCIPR4_I2C3SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C3SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR4_I2C3SEL                      RCC_CCIPR4_I2C3SEL_Msk                            /*!< Source selection for the I2C3 kernel clock */
+#define RCC_CCIPR4_I2C3SEL_0                    (0x1UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR4_I2C3SEL_1                    (0x2UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR4_I2C3SEL_2                    (0x4UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR4_I2C4SEL_Pos                  (12U)
+#define RCC_CCIPR4_I2C4SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C4SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR4_I2C4SEL                      RCC_CCIPR4_I2C4SEL_Msk                            /*!< Source selection for the I2C4 kernel clock */
+#define RCC_CCIPR4_I2C4SEL_0                    (0x1UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR4_I2C4SEL_1                    (0x2UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR4_I2C4SEL_2                    (0x4UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR4_I3C1SEL_Pos                  (16U)
+#define RCC_CCIPR4_I3C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR4_I3C1SEL                      RCC_CCIPR4_I3C1SEL_Msk                            /*!< Source selection for the I3C1 kernel clock */
+#define RCC_CCIPR4_I3C1SEL_0                    (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR4_I3C1SEL_1                    (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR4_I3C1SEL_2                    (0x4UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR4_I3C2SEL_Pos                  (20U)
+#define RCC_CCIPR4_I3C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C2SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR4_I3C2SEL                      RCC_CCIPR4_I3C2SEL_Msk                            /*!< Source selection for the I3C2 kernel clock */
+#define RCC_CCIPR4_I3C2SEL_0                    (0x1UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR4_I3C2SEL_1                    (0x2UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR4_I3C2SEL_2                    (0x4UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR4_LTDCSEL_Pos                  (24U)
+#define RCC_CCIPR4_LTDCSEL_Msk                  (0x3UL << RCC_CCIPR4_LTDCSEL_Pos)                  /*!< 0x03000000 */
+#define RCC_CCIPR4_LTDCSEL                      RCC_CCIPR4_LTDCSEL_Msk                            /*!< Source selection for the LTDC kernel clock */
+#define RCC_CCIPR4_LTDCSEL_0                    (0x1UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR4_LTDCSEL_1                    (0x2UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x02000000 */
+
+/******************  Bit definition for RCC_CCIPR5 register  ******************/
+#define RCC_CCIPR5_MCO1SEL_Pos                  (0U)
+#define RCC_CCIPR5_MCO1SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR5_MCO1SEL                      RCC_CCIPR5_MCO1SEL_Msk                            /*!< Source selection for the MCO1 kernel clock */
+#define RCC_CCIPR5_MCO1SEL_0                    (0x1UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR5_MCO1SEL_1                    (0x2UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR5_MCO1SEL_2                    (0x4UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR5_MCO1PRE_Pos                  (4U)
+#define RCC_CCIPR5_MCO1PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO1PRE_Pos)                  /*!< 0x000000F0 */
+#define RCC_CCIPR5_MCO1PRE                      RCC_CCIPR5_MCO1PRE_Msk                            /*!< MCO1 Kernel clock divider selection (for clock MCO1) */
+#define RCC_CCIPR5_MCO1PRE_0                    (0x1UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR5_MCO1PRE_1                    (0x2UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR5_MCO1PRE_2                    (0x4UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR5_MCO1PRE_3                    (0x8UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000080 */
+#define RCC_CCIPR5_MCO2SEL_Pos                  (8U)
+#define RCC_CCIPR5_MCO2SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR5_MCO2SEL                      RCC_CCIPR5_MCO2SEL_Msk                            /*!< Source selection for the MCO2 kernel clock */
+#define RCC_CCIPR5_MCO2SEL_0                    (0x1UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR5_MCO2SEL_1                    (0x2UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR5_MCO2SEL_2                    (0x4UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR5_MCO2PRE_Pos                  (12U)
+#define RCC_CCIPR5_MCO2PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO2PRE_Pos)                  /*!< 0x0000F000 */
+#define RCC_CCIPR5_MCO2PRE                      RCC_CCIPR5_MCO2PRE_Msk                            /*!< MCO2 Kernel clock divider selection (for clock MCO2) */
+#define RCC_CCIPR5_MCO2PRE_0                    (0x1UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR5_MCO2PRE_1                    (0x2UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR5_MCO2PRE_2                    (0x4UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR5_MCO2PRE_3                    (0x8UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00008000 */
+#define RCC_CCIPR5_MDF1SEL_Pos                  (16U)
+#define RCC_CCIPR5_MDF1SEL_Msk                  (0x7UL << RCC_CCIPR5_MDF1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR5_MDF1SEL                      RCC_CCIPR5_MDF1SEL_Msk                            /*!< Source selection for the MDF1 kernel clock */
+#define RCC_CCIPR5_MDF1SEL_0                    (0x1UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR5_MDF1SEL_1                    (0x2UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR5_MDF1SEL_2                    (0x4UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00040000 */
+
+/******************  Bit definition for RCC_CCIPR6 register  ******************/
+#define RCC_CCIPR6_XSPI1SEL_Pos                 (0U)
+#define RCC_CCIPR6_XSPI1SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR6_XSPI1SEL                     RCC_CCIPR6_XSPI1SEL_Msk                           /*!< Source selection for the XSPI1 kernel clock */
+#define RCC_CCIPR6_XSPI1SEL_0                   (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR6_XSPI1SEL_1                   (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR6_XSPI2SEL_Pos                 (4U)
+#define RCC_CCIPR6_XSPI2SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos)                 /*!< 0x00000030 */
+#define RCC_CCIPR6_XSPI2SEL                     RCC_CCIPR6_XSPI2SEL_Msk                           /*!< Source selection for the XSPI2 kernel clock */
+#define RCC_CCIPR6_XSPI2SEL_0                   (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR6_XSPI2SEL_1                   (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR6_XSPI3SEL_Pos                 (8U)
+#define RCC_CCIPR6_XSPI3SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos)                 /*!< 0x00000300 */
+#define RCC_CCIPR6_XSPI3SEL                     RCC_CCIPR6_XSPI3SEL_Msk                           /*!< Source selection for the XSPI3 kernel clock */
+#define RCC_CCIPR6_XSPI3SEL_0                   (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000100 */
+#define RCC_CCIPR6_XSPI3SEL_1                   (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000200 */
+#define RCC_CCIPR6_OTGPHY1SEL_Pos               (12U)
+#define RCC_CCIPR6_OTGPHY1SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR6_OTGPHY1SEL                   RCC_CCIPR6_OTGPHY1SEL_Msk                         /*!< Source selection for the OTGPHY1 kernel clock */
+#define RCC_CCIPR6_OTGPHY1SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR6_OTGPHY1SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos          (16U)
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos)          /*!< 0x00010000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL              RCC_CCIPR6_OTGPHY1CKREFSEL_Msk                    /*!< Set and reset by software */
+#define RCC_CCIPR6_OTGPHY2SEL_Pos               (20U)
+#define RCC_CCIPR6_OTGPHY2SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos)               /*!< 0x00300000 */
+#define RCC_CCIPR6_OTGPHY2SEL                   RCC_CCIPR6_OTGPHY2SEL_Msk                         /*!< Source selection for the OTGPHY2 kernel clock */
+#define RCC_CCIPR6_OTGPHY2SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR6_OTGPHY2SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos          (24U)
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL              RCC_CCIPR6_OTGPHY2CKREFSEL_Msk                    /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR7 register  ******************/
+#define RCC_CCIPR7_PERSEL_Pos                   (0U)
+#define RCC_CCIPR7_PERSEL_Msk                   (0x7UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000007 */
+#define RCC_CCIPR7_PERSEL                       RCC_CCIPR7_PERSEL_Msk                             /*!< Source selection for the PER kernel clock */
+#define RCC_CCIPR7_PERSEL_0                     (0x1UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000001 */
+#define RCC_CCIPR7_PERSEL_1                     (0x2UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000002 */
+#define RCC_CCIPR7_PERSEL_2                     (0x4UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000004 */
+#define RCC_CCIPR7_PSSISEL_Pos                  (4U)
+#define RCC_CCIPR7_PSSISEL_Msk                  (0x3UL << RCC_CCIPR7_PSSISEL_Pos)                  /*!< 0x00000030 */
+#define RCC_CCIPR7_PSSISEL                      RCC_CCIPR7_PSSISEL_Msk                            /*!< Source selection for the PSSI kernel clock */
+#define RCC_CCIPR7_PSSISEL_0                    (0x1UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR7_PSSISEL_1                    (0x2UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR7_RTCSEL_Pos                   (8U)
+#define RCC_CCIPR7_RTCSEL_Msk                   (0x3UL << RCC_CCIPR7_RTCSEL_Pos)                   /*!< 0x00000300 */
+#define RCC_CCIPR7_RTCSEL                       RCC_CCIPR7_RTCSEL_Msk                             /*!< Source selection for the RTC kernel clock */
+#define RCC_CCIPR7_RTCSEL_0                     (0x1UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR7_RTCSEL_1                     (0x2UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR7_RTCPRE_Pos                   (12U)
+#define RCC_CCIPR7_RTCPRE_Msk                   (0x3FUL << RCC_CCIPR7_RTCPRE_Pos)                  /*!< 0x0003F000 */
+#define RCC_CCIPR7_RTCPRE                       RCC_CCIPR7_RTCPRE_Msk                             /*!< RTC OSC clock divider selection (for clock hse_ck) */
+#define RCC_CCIPR7_RTCPRE_0                     (0x1UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR7_RTCPRE_1                     (0x2UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR7_RTCPRE_2                     (0x4UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR7_RTCPRE_3                     (0x8UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR7_RTCPRE_4                     (0x10UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00010000 */
+#define RCC_CCIPR7_RTCPRE_5                     (0x20UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00020000 */
+#define RCC_CCIPR7_SAI1SEL_Pos                  (20U)
+#define RCC_CCIPR7_SAI1SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI1SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR7_SAI1SEL                      RCC_CCIPR7_SAI1SEL_Msk                            /*!< Source selection for the SAI1 kernel clock */
+#define RCC_CCIPR7_SAI1SEL_0                    (0x1UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR7_SAI1SEL_1                    (0x2UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR7_SAI1SEL_2                    (0x4UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR7_SAI2SEL_Pos                  (24U)
+#define RCC_CCIPR7_SAI2SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI2SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR7_SAI2SEL                      RCC_CCIPR7_SAI2SEL_Msk                            /*!< Source selection for the SAI2 kernel clock */
+#define RCC_CCIPR7_SAI2SEL_0                    (0x1UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR7_SAI2SEL_1                    (0x2UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR7_SAI2SEL_2                    (0x4UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x04000000 */
+
+/******************  Bit definition for RCC_CCIPR8 register  ******************/
+#define RCC_CCIPR8_SDMMC1SEL_Pos                (0U)
+#define RCC_CCIPR8_SDMMC1SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000003 */
+#define RCC_CCIPR8_SDMMC1SEL                    RCC_CCIPR8_SDMMC1SEL_Msk                          /*!< Source selection for the SDMMC1 kernel clock */
+#define RCC_CCIPR8_SDMMC1SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR8_SDMMC1SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR8_SDMMC2SEL_Pos                (4U)
+#define RCC_CCIPR8_SDMMC2SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos)                /*!< 0x00000030 */
+#define RCC_CCIPR8_SDMMC2SEL                    RCC_CCIPR8_SDMMC2SEL_Msk                          /*!< Source selection for the SDMMC2 kernel clock */
+#define RCC_CCIPR8_SDMMC2SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000010 */
+#define RCC_CCIPR8_SDMMC2SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000020 */
+
+/******************  Bit definition for RCC_CCIPR9 register  ******************/
+#define RCC_CCIPR9_SPDIFRX1SEL_Pos              (0U)
+#define RCC_CCIPR9_SPDIFRX1SEL_Msk              (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000007 */
+#define RCC_CCIPR9_SPDIFRX1SEL                  RCC_CCIPR9_SPDIFRX1SEL_Msk                        /*!< Source selection for the SPDIFRX1 kernel clock */
+#define RCC_CCIPR9_SPDIFRX1SEL_0                (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000001 */
+#define RCC_CCIPR9_SPDIFRX1SEL_1                (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000002 */
+#define RCC_CCIPR9_SPDIFRX1SEL_2                (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000004 */
+#define RCC_CCIPR9_SPI1SEL_Pos                  (4U)
+#define RCC_CCIPR9_SPI1SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI1SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR9_SPI1SEL                      RCC_CCIPR9_SPI1SEL_Msk                            /*!< Source selection for the SPI1 kernel clock */
+#define RCC_CCIPR9_SPI1SEL_0                    (0x1UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR9_SPI1SEL_1                    (0x2UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR9_SPI1SEL_2                    (0x4UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR9_SPI2SEL_Pos                  (8U)
+#define RCC_CCIPR9_SPI2SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR9_SPI2SEL                      RCC_CCIPR9_SPI2SEL_Msk                            /*!< Source selection for the SPI2 kernel clock */
+#define RCC_CCIPR9_SPI2SEL_0                    (0x1UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR9_SPI2SEL_1                    (0x2UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR9_SPI2SEL_2                    (0x4UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR9_SPI3SEL_Pos                  (12U)
+#define RCC_CCIPR9_SPI3SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI3SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR9_SPI3SEL                      RCC_CCIPR9_SPI3SEL_Msk                            /*!< Source selection for the SPI3 kernel clock */
+#define RCC_CCIPR9_SPI3SEL_0                    (0x1UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR9_SPI3SEL_1                    (0x2UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR9_SPI3SEL_2                    (0x4UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR9_SPI4SEL_Pos                  (16U)
+#define RCC_CCIPR9_SPI4SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI4SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR9_SPI4SEL                      RCC_CCIPR9_SPI4SEL_Msk                            /*!< Source selection for the SPI4 kernel clock */
+#define RCC_CCIPR9_SPI4SEL_0                    (0x1UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR9_SPI4SEL_1                    (0x2UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR9_SPI4SEL_2                    (0x4UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR9_SPI5SEL_Pos                  (20U)
+#define RCC_CCIPR9_SPI5SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI5SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR9_SPI5SEL                      RCC_CCIPR9_SPI5SEL_Msk                            /*!< Source selection for the SPI5 kernel clock */
+#define RCC_CCIPR9_SPI5SEL_0                    (0x1UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR9_SPI5SEL_1                    (0x2UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR9_SPI5SEL_2                    (0x4UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR9_SPI6SEL_Pos                  (24U)
+#define RCC_CCIPR9_SPI6SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI6SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR9_SPI6SEL                      RCC_CCIPR9_SPI6SEL_Msk                            /*!< Source selection for the SPI6 kernel clock */
+#define RCC_CCIPR9_SPI6SEL_0                    (0x1UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR9_SPI6SEL_1                    (0x2UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR9_SPI6SEL_2                    (0x4UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR12 register  ******************/
+#define RCC_CCIPR12_LPTIM1SEL_Pos               (8U)
+#define RCC_CCIPR12_LPTIM1SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR12_LPTIM1SEL                   RCC_CCIPR12_LPTIM1SEL_Msk                         /*!< Source selection for the LPTIM1 kernel clock */
+#define RCC_CCIPR12_LPTIM1SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR12_LPTIM1SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR12_LPTIM1SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR12_LPTIM2SEL_Pos               (12U)
+#define RCC_CCIPR12_LPTIM2SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos)               /*!< 0x00007000 */
+#define RCC_CCIPR12_LPTIM2SEL                   RCC_CCIPR12_LPTIM2SEL_Msk                         /*!< Source selection for the LPTIM2 kernel clock */
+#define RCC_CCIPR12_LPTIM2SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR12_LPTIM2SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR12_LPTIM2SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00004000 */
+#define RCC_CCIPR12_LPTIM3SEL_Pos               (16U)
+#define RCC_CCIPR12_LPTIM3SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos)               /*!< 0x00070000 */
+#define RCC_CCIPR12_LPTIM3SEL                   RCC_CCIPR12_LPTIM3SEL_Msk                         /*!< Source selection for the LPTIM3 kernel clock */
+#define RCC_CCIPR12_LPTIM3SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00010000 */
+#define RCC_CCIPR12_LPTIM3SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00020000 */
+#define RCC_CCIPR12_LPTIM3SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00040000 */
+#define RCC_CCIPR12_LPTIM4SEL_Pos               (20U)
+#define RCC_CCIPR12_LPTIM4SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR12_LPTIM4SEL                   RCC_CCIPR12_LPTIM4SEL_Msk                         /*!< Source selection for the LPTIM4 kernel clock */
+#define RCC_CCIPR12_LPTIM4SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR12_LPTIM4SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR12_LPTIM4SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR12_LPTIM5SEL_Pos               (24U)
+#define RCC_CCIPR12_LPTIM5SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos)               /*!< 0x07000000 */
+#define RCC_CCIPR12_LPTIM5SEL                   RCC_CCIPR12_LPTIM5SEL_Msk                         /*!< Source selection for the LPTIM5 kernel clock */
+#define RCC_CCIPR12_LPTIM5SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x01000000 */
+#define RCC_CCIPR12_LPTIM5SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x02000000 */
+#define RCC_CCIPR12_LPTIM5SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR13 register  ******************/
+#define RCC_CCIPR13_USART1SEL_Pos               (0U)
+#define RCC_CCIPR13_USART1SEL_Msk               (0x7UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000007 */
+#define RCC_CCIPR13_USART1SEL                   RCC_CCIPR13_USART1SEL_Msk                         /*!< Source selection for the USART1 kernel clock */
+#define RCC_CCIPR13_USART1SEL_0                 (0x1UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR13_USART1SEL_1                 (0x2UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR13_USART1SEL_2                 (0x4UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000004 */
+#define RCC_CCIPR13_USART2SEL_Pos               (4U)
+#define RCC_CCIPR13_USART2SEL_Msk               (0x7UL << RCC_CCIPR13_USART2SEL_Pos)               /*!< 0x00000070 */
+#define RCC_CCIPR13_USART2SEL                   RCC_CCIPR13_USART2SEL_Msk                         /*!< Source selection for the USART2 kernel clock */
+#define RCC_CCIPR13_USART2SEL_0                 (0x1UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR13_USART2SEL_1                 (0x2UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR13_USART2SEL_2                 (0x4UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR13_USART3SEL_Pos               (8U)
+#define RCC_CCIPR13_USART3SEL_Msk               (0x7UL << RCC_CCIPR13_USART3SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR13_USART3SEL                   RCC_CCIPR13_USART3SEL_Msk                         /*!< Source selection for the USART3 kernel clock */
+#define RCC_CCIPR13_USART3SEL_0                 (0x1UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR13_USART3SEL_1                 (0x2UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR13_USART3SEL_2                 (0x4UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR13_UART4SEL_Pos                (12U)
+#define RCC_CCIPR13_UART4SEL_Msk                (0x7UL << RCC_CCIPR13_UART4SEL_Pos)                /*!< 0x00007000 */
+#define RCC_CCIPR13_UART4SEL                    RCC_CCIPR13_UART4SEL_Msk                          /*!< Source selection for the UART4 kernel clock */
+#define RCC_CCIPR13_UART4SEL_0                  (0x1UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00001000 */
+#define RCC_CCIPR13_UART4SEL_1                  (0x2UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00002000 */
+#define RCC_CCIPR13_UART4SEL_2                  (0x4UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00004000 */
+#define RCC_CCIPR13_UART5SEL_Pos                (16U)
+#define RCC_CCIPR13_UART5SEL_Msk                (0x7UL << RCC_CCIPR13_UART5SEL_Pos)                /*!< 0x00070000 */
+#define RCC_CCIPR13_UART5SEL                    RCC_CCIPR13_UART5SEL_Msk                          /*!< Source selection for the UART5 kernel clock */
+#define RCC_CCIPR13_UART5SEL_0                  (0x1UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00010000 */
+#define RCC_CCIPR13_UART5SEL_1                  (0x2UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00020000 */
+#define RCC_CCIPR13_UART5SEL_2                  (0x4UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00040000 */
+#define RCC_CCIPR13_USART6SEL_Pos               (20U)
+#define RCC_CCIPR13_USART6SEL_Msk               (0x7UL << RCC_CCIPR13_USART6SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR13_USART6SEL                   RCC_CCIPR13_USART6SEL_Msk                         /*!< Source selection for the USART6 kernel clock */
+#define RCC_CCIPR13_USART6SEL_0                 (0x1UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR13_USART6SEL_1                 (0x2UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR13_USART6SEL_2                 (0x4UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR13_UART7SEL_Pos                (24U)
+#define RCC_CCIPR13_UART7SEL_Msk                (0x7UL << RCC_CCIPR13_UART7SEL_Pos)                /*!< 0x07000000 */
+#define RCC_CCIPR13_UART7SEL                    RCC_CCIPR13_UART7SEL_Msk                          /*!< Source selection for the UART7 kernel clock */
+#define RCC_CCIPR13_UART7SEL_0                  (0x1UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR13_UART7SEL_1                  (0x2UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x02000000 */
+#define RCC_CCIPR13_UART7SEL_2                  (0x4UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x04000000 */
+#define RCC_CCIPR13_UART8SEL_Pos                (28U)
+#define RCC_CCIPR13_UART8SEL_Msk                (0x7UL << RCC_CCIPR13_UART8SEL_Pos)                /*!< 0x70000000 */
+#define RCC_CCIPR13_UART8SEL                    RCC_CCIPR13_UART8SEL_Msk                          /*!< Source selection for the UART8 kernel clock */
+#define RCC_CCIPR13_UART8SEL_0                  (0x1UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x10000000 */
+#define RCC_CCIPR13_UART8SEL_1                  (0x2UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x20000000 */
+#define RCC_CCIPR13_UART8SEL_2                  (0x4UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x40000000 */
+
+/*****************  Bit definition for RCC_CCIPR14 register  ******************/
+#define RCC_CCIPR14_UART9SEL_Pos                (0U)
+#define RCC_CCIPR14_UART9SEL_Msk                (0x7UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000007 */
+#define RCC_CCIPR14_UART9SEL                    RCC_CCIPR14_UART9SEL_Msk                          /*!< Source selection for the UART9 kernel clock */
+#define RCC_CCIPR14_UART9SEL_0                  (0x1UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR14_UART9SEL_1                  (0x2UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR14_UART9SEL_2                  (0x4UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000004 */
+#define RCC_CCIPR14_USART10SEL_Pos              (4U)
+#define RCC_CCIPR14_USART10SEL_Msk              (0x7UL << RCC_CCIPR14_USART10SEL_Pos)              /*!< 0x00000070 */
+#define RCC_CCIPR14_USART10SEL                  RCC_CCIPR14_USART10SEL_Msk                        /*!< Source selection for the USART10 kernel clock */
+#define RCC_CCIPR14_USART10SEL_0                (0x1UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000010 */
+#define RCC_CCIPR14_USART10SEL_1                (0x2UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000020 */
+#define RCC_CCIPR14_USART10SEL_2                (0x4UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000040 */
+#define RCC_CCIPR14_LPUART1SEL_Pos              (8U)
+#define RCC_CCIPR14_LPUART1SEL_Msk              (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos)              /*!< 0x00000700 */
+#define RCC_CCIPR14_LPUART1SEL                  RCC_CCIPR14_LPUART1SEL_Msk                        /*!< Source selection for the LPUART1 kernel clock */
+#define RCC_CCIPR14_LPUART1SEL_0                (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000100 */
+#define RCC_CCIPR14_LPUART1SEL_1                (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000200 */
+#define RCC_CCIPR14_LPUART1SEL_2                (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000400 */
+
+/*****************  Bit definition for RCC_MISCRSTR register  *****************/
+#define RCC_MISCRSTR_DBGRST_Pos                 (0U)
+#define RCC_MISCRSTR_DBGRST_Msk                 (0x1UL << RCC_MISCRSTR_DBGRST_Pos)    /*!< 0x00000001 */
+#define RCC_MISCRSTR_DBGRST                     RCC_MISCRSTR_DBGRST_Msk              /*!< DBG reset */
+#define RCC_MISCRSTR_XSPIPHY1RST_Pos            (4U)
+#define RCC_MISCRSTR_XSPIPHY1RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */
+#define RCC_MISCRSTR_XSPIPHY1RST                RCC_MISCRSTR_XSPIPHY1RST_Msk         /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTR_XSPIPHY2RST_Pos            (5U)
+#define RCC_MISCRSTR_XSPIPHY2RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */
+#define RCC_MISCRSTR_XSPIPHY2RST                RCC_MISCRSTR_XSPIPHY2RST_Msk         /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTR_SDMMC1DLLRST_Pos           (7U)
+#define RCC_MISCRSTR_SDMMC1DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos)  /*!< 0x00000080 */
+#define RCC_MISCRSTR_SDMMC1DLLRST               RCC_MISCRSTR_SDMMC1DLLRST_Msk        /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTR_SDMMC2DLLRST_Pos           (8U)
+#define RCC_MISCRSTR_SDMMC2DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos)  /*!< 0x00000100 */
+#define RCC_MISCRSTR_SDMMC2DLLRST               RCC_MISCRSTR_SDMMC2DLLRST_Msk        /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTR register  ******************/
+#define RCC_MEMRSTR_AXISRAM3RST_Pos             (0U)
+#define RCC_MEMRSTR_AXISRAM3RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */
+#define RCC_MEMRSTR_AXISRAM3RST                 RCC_MEMRSTR_AXISRAM3RST_Msk          /*!< AXISRAM3 reset */
+#define RCC_MEMRSTR_AXISRAM4RST_Pos             (1U)
+#define RCC_MEMRSTR_AXISRAM4RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */
+#define RCC_MEMRSTR_AXISRAM4RST                 RCC_MEMRSTR_AXISRAM4RST_Msk          /*!< AXISRAM4 reset */
+#define RCC_MEMRSTR_AXISRAM5RST_Pos             (2U)
+#define RCC_MEMRSTR_AXISRAM5RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */
+#define RCC_MEMRSTR_AXISRAM5RST                 RCC_MEMRSTR_AXISRAM5RST_Msk          /*!< AXISRAM5 reset */
+#define RCC_MEMRSTR_AXISRAM6RST_Pos             (3U)
+#define RCC_MEMRSTR_AXISRAM6RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */
+#define RCC_MEMRSTR_AXISRAM6RST                 RCC_MEMRSTR_AXISRAM6RST_Msk          /*!< AXISRAM6 reset */
+#define RCC_MEMRSTR_AHBSRAM1RST_Pos             (4U)
+#define RCC_MEMRSTR_AHBSRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */
+#define RCC_MEMRSTR_AHBSRAM1RST                 RCC_MEMRSTR_AHBSRAM1RST_Msk          /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTR_AHBSRAM2RST_Pos             (5U)
+#define RCC_MEMRSTR_AHBSRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */
+#define RCC_MEMRSTR_AHBSRAM2RST                 RCC_MEMRSTR_AHBSRAM2RST_Msk          /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTR_AXISRAM1RST_Pos             (7U)
+#define RCC_MEMRSTR_AXISRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */
+#define RCC_MEMRSTR_AXISRAM1RST                 RCC_MEMRSTR_AXISRAM1RST_Msk          /*!< AXISRAM1 reset */
+#define RCC_MEMRSTR_AXISRAM2RST_Pos             (8U)
+#define RCC_MEMRSTR_AXISRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */
+#define RCC_MEMRSTR_AXISRAM2RST                 RCC_MEMRSTR_AXISRAM2RST_Msk          /*!< AXISRAM2 reset */
+#define RCC_MEMRSTR_FLEXRAMRST_Pos              (9U)
+#define RCC_MEMRSTR_FLEXRAMRST_Msk              (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTR_FLEXRAMRST                  RCC_MEMRSTR_FLEXRAMRST_Msk           /*!< FLEXRAM reset */
+#define RCC_MEMRSTR_VENCRAMRST_Pos              (11U)
+#define RCC_MEMRSTR_VENCRAMRST_Msk              (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTR_VENCRAMRST                  RCC_MEMRSTR_VENCRAMRST_Msk           /*!< VENCRAM reset */
+#define RCC_MEMRSTR_BOOTROMRST_Pos              (12U)
+#define RCC_MEMRSTR_BOOTROMRST_Msk              (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTR_BOOTROMRST                  RCC_MEMRSTR_BOOTROMRST_Msk           /*!< Boot ROM reset */
+
+/*****************  Bit definition for RCC_AHB1RSTR register  *****************/
+#define RCC_AHB1RSTR_GPDMA1RST_Pos              (4U)
+#define RCC_AHB1RSTR_GPDMA1RST_Msk              (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPDMA1RST                  RCC_AHB1RSTR_GPDMA1RST_Msk           /*!< GPDMA1 reset */
+#define RCC_AHB1RSTR_ADC12RST_Pos               (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk               (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                   RCC_AHB1RSTR_ADC12RST_Msk            /*!< ADC12 reset */
+
+/*****************  Bit definition for RCC_AHB2RSTR register  *****************/
+#define RCC_AHB2RSTR_RAMCFGRST_Pos              (12U)
+#define RCC_AHB2RSTR_RAMCFGRST_Msk              (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_RAMCFGRST                  RCC_AHB2RSTR_RAMCFGRST_Msk           /*!< RAMCFG reset */
+#define RCC_AHB2RSTR_MDF1RST_Pos                (16U)
+#define RCC_AHB2RSTR_MDF1RST_Msk                (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2RSTR_MDF1RST                    RCC_AHB2RSTR_MDF1RST_Msk             /*!< MDF1 reset */
+#define RCC_AHB2RSTR_ADF1RST_Pos                (17U)
+#define RCC_AHB2RSTR_ADF1RST_Msk                (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2RSTR_ADF1RST                    RCC_AHB2RSTR_ADF1RST_Msk             /*!< ADF1 reset */
+
+/*****************  Bit definition for RCC_AHB3RSTR register  *****************/
+#define RCC_AHB3RSTR_RNGRST_Pos                 (0U)
+#define RCC_AHB3RSTR_RNGRST_Msk                 (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3RSTR_RNGRST                     RCC_AHB3RSTR_RNGRST_Msk              /*!< RNG reset */
+#define RCC_AHB3RSTR_HASHRST_Pos                (1U)
+#define RCC_AHB3RSTR_HASHRST_Msk                (0x1UL << RCC_AHB3RSTR_HASHRST_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3RSTR_HASHRST                    RCC_AHB3RSTR_HASHRST_Msk             /*!< HASH reset */
+#define RCC_AHB3RSTR_CRYPRST_Pos                (2U)
+#define RCC_AHB3RSTR_CRYPRST_Msk                (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos)   /*!< 0x00000004 */
+#define RCC_AHB3RSTR_CRYPRST                    RCC_AHB3RSTR_CRYPRST_Msk             /*!< CRYP reset */
+#define RCC_AHB3RSTR_SAESRST_Pos                (4U)
+#define RCC_AHB3RSTR_SAESRST_Msk                (0x1UL << RCC_AHB3RSTR_SAESRST_Pos)   /*!< 0x00000010 */
+#define RCC_AHB3RSTR_SAESRST                    RCC_AHB3RSTR_SAESRST_Msk             /*!< SAES reset */
+#define RCC_AHB3RSTR_PKARST_Pos                 (8U)
+#define RCC_AHB3RSTR_PKARST_Msk                 (0x1UL << RCC_AHB3RSTR_PKARST_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3RSTR_PKARST                     RCC_AHB3RSTR_PKARST_Msk              /*!< PKA reset */
+#define RCC_AHB3RSTR_IACRST_Pos                 (10U)
+#define RCC_AHB3RSTR_IACRST_Msk                 (0x1UL << RCC_AHB3RSTR_IACRST_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3RSTR_IACRST                     RCC_AHB3RSTR_IACRST_Msk              /*!< IAC reset */
+
+/*****************  Bit definition for RCC_AHB4RSTR register  *****************/
+#define RCC_AHB4RSTR_GPIOARST_Pos               (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                   RCC_AHB4RSTR_GPIOARST_Msk            /*!< GPIO A reset */
+#define RCC_AHB4RSTR_GPIOBRST_Pos               (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                   RCC_AHB4RSTR_GPIOBRST_Msk            /*!< GPIO B reset */
+#define RCC_AHB4RSTR_GPIOCRST_Pos               (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                   RCC_AHB4RSTR_GPIOCRST_Msk            /*!< GPIO C reset */
+#define RCC_AHB4RSTR_GPIODRST_Pos               (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                   RCC_AHB4RSTR_GPIODRST_Msk            /*!< GPIO D reset */
+#define RCC_AHB4RSTR_GPIOERST_Pos               (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                   RCC_AHB4RSTR_GPIOERST_Msk            /*!< GPIO E reset */
+#define RCC_AHB4RSTR_GPIOFRST_Pos               (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                   RCC_AHB4RSTR_GPIOFRST_Msk            /*!< GPIO F reset */
+#define RCC_AHB4RSTR_GPIOGRST_Pos               (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                   RCC_AHB4RSTR_GPIOGRST_Msk            /*!< GPIO G reset */
+#define RCC_AHB4RSTR_GPIOHRST_Pos               (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                   RCC_AHB4RSTR_GPIOHRST_Msk            /*!< GPIO H reset */
+#define RCC_AHB4RSTR_GPIONRST_Pos               (13U)
+#define RCC_AHB4RSTR_GPIONRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4RSTR_GPIONRST                   RCC_AHB4RSTR_GPIONRST_Msk            /*!< GPIO N reset */
+#define RCC_AHB4RSTR_GPIOORST_Pos               (14U)
+#define RCC_AHB4RSTR_GPIOORST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4RSTR_GPIOORST                   RCC_AHB4RSTR_GPIOORST_Msk            /*!< GPIO O reset */
+#define RCC_AHB4RSTR_GPIOPRST_Pos               (15U)
+#define RCC_AHB4RSTR_GPIOPRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4RSTR_GPIOPRST                   RCC_AHB4RSTR_GPIOPRST_Msk            /*!< GPIO P reset */
+#define RCC_AHB4RSTR_GPIOQRST_Pos               (16U)
+#define RCC_AHB4RSTR_GPIOQRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4RSTR_GPIOQRST                   RCC_AHB4RSTR_GPIOQRST_Msk            /*!< GPIO Q reset */
+#define RCC_AHB4RSTR_PWRRST_Pos                 (18U)
+#define RCC_AHB4RSTR_PWRRST_Msk                 (0x1UL << RCC_AHB4RSTR_PWRRST_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4RSTR_PWRRST                     RCC_AHB4RSTR_PWRRST_Msk              /*!< PWR reset */
+#define RCC_AHB4RSTR_CRCRST_Pos                 (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                 (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                     RCC_AHB4RSTR_CRCRST_Msk              /*!< CRC reset */
+
+/*****************  Bit definition for RCC_AHB5RSTR register  *****************/
+#define RCC_AHB5RSTR_HPDMA1RST_Pos              (0U)
+#define RCC_AHB5RSTR_HPDMA1RST_Msk              (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTR_HPDMA1RST                  RCC_AHB5RSTR_HPDMA1RST_Msk           /*!< HPDMA1 reset */
+#define RCC_AHB5RSTR_DMA2DRST_Pos               (1U)
+#define RCC_AHB5RSTR_DMA2DRST_Msk               (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5RSTR_DMA2DRST                   RCC_AHB5RSTR_DMA2DRST_Msk            /*!< DMA2D reset */
+#define RCC_AHB5RSTR_JPEGRST_Pos                (3U)
+#define RCC_AHB5RSTR_JPEGRST_Msk                (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5RSTR_JPEGRST                    RCC_AHB5RSTR_JPEGRST_Msk             /*!< JPEG reset */
+#define RCC_AHB5RSTR_FMCRST_Pos                 (4U)
+#define RCC_AHB5RSTR_FMCRST_Msk                 (0x1UL << RCC_AHB5RSTR_FMCRST_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5RSTR_FMCRST                     RCC_AHB5RSTR_FMCRST_Msk              /*!< FMC reset */
+#define RCC_AHB5RSTR_XSPI1RST_Pos               (5U)
+#define RCC_AHB5RSTR_XSPI1RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5RSTR_XSPI1RST                   RCC_AHB5RSTR_XSPI1RST_Msk            /*!< XSPI1 reset */
+#define RCC_AHB5RSTR_PSSIRST_Pos                (6U)
+#define RCC_AHB5RSTR_PSSIRST_Msk                (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5RSTR_PSSIRST                    RCC_AHB5RSTR_PSSIRST_Msk             /*!< PSSI reset */
+#define RCC_AHB5RSTR_SDMMC2RST_Pos              (7U)
+#define RCC_AHB5RSTR_SDMMC2RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTR_SDMMC2RST                  RCC_AHB5RSTR_SDMMC2RST_Msk           /*!< SDMMC2 reset */
+#define RCC_AHB5RSTR_SDMMC1RST_Pos              (8U)
+#define RCC_AHB5RSTR_SDMMC1RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTR_SDMMC1RST                  RCC_AHB5RSTR_SDMMC1RST_Msk           /*!< SDMMC1 reset */
+#define RCC_AHB5RSTR_XSPI2RST_Pos               (12U)
+#define RCC_AHB5RSTR_XSPI2RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5RSTR_XSPI2RST                   RCC_AHB5RSTR_XSPI2RST_Msk            /*!< XSPI2 reset */
+#define RCC_AHB5RSTR_XSPIMRST_Pos               (13U)
+#define RCC_AHB5RSTR_XSPIMRST_Msk               (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5RSTR_XSPIMRST                   RCC_AHB5RSTR_XSPIMRST_Msk            /*!< XSPIM reset */
+#define RCC_AHB5RSTR_XSPI3RST_Pos               (17U)
+#define RCC_AHB5RSTR_XSPI3RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5RSTR_XSPI3RST                   RCC_AHB5RSTR_XSPI3RST_Msk            /*!< XSPI3 reset */
+#define RCC_AHB5RSTR_GFXMMURST_Pos              (19U)
+#define RCC_AHB5RSTR_GFXMMURST_Msk              (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTR_GFXMMURST                  RCC_AHB5RSTR_GFXMMURST_Msk           /*!< GFXMMU reset */
+#define RCC_AHB5RSTR_GPU2DRST_Pos               (20U)
+#define RCC_AHB5RSTR_GPU2DRST_Msk               (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5RSTR_GPU2DRST                   RCC_AHB5RSTR_GPU2DRST_Msk            /*!< GPU2D reset */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos          (23U)
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST              RCC_AHB5RSTR_OTG1PHYCTLRST_Msk       /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos          (24U)
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST              RCC_AHB5RSTR_OTG2PHYCTLRST_Msk       /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTR_ETH1RST_Pos                (25U)
+#define RCC_AHB5RSTR_ETH1RST_Msk                (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5RSTR_ETH1RST                    RCC_AHB5RSTR_ETH1RST_Msk             /*!< ETH1 reset */
+#define RCC_AHB5RSTR_OTG1RST_Pos                (26U)
+#define RCC_AHB5RSTR_OTG1RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5RSTR_OTG1RST                    RCC_AHB5RSTR_OTG1RST_Msk             /*!< OTG1 reset */
+#define RCC_AHB5RSTR_OTGPHY1RST_Pos             (27U)
+#define RCC_AHB5RSTR_OTGPHY1RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */
+#define RCC_AHB5RSTR_OTGPHY1RST                 RCC_AHB5RSTR_OTGPHY1RST_Msk          /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTR_OTGPHY2RST_Pos             (28U)
+#define RCC_AHB5RSTR_OTGPHY2RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */
+#define RCC_AHB5RSTR_OTGPHY2RST                 RCC_AHB5RSTR_OTGPHY2RST_Msk          /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTR_OTG2RST_Pos                (29U)
+#define RCC_AHB5RSTR_OTG2RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5RSTR_OTG2RST                    RCC_AHB5RSTR_OTG2RST_Msk             /*!< OTG2 reset */
+
+/****************  Bit definition for RCC_APB1RSTR1 register  *****************/
+#define RCC_APB1RSTR1_TIM2RST_Pos               (0U)
+#define RCC_APB1RSTR1_TIM2RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                   RCC_APB1RSTR1_TIM2RST_Msk            /*!< TIM2 reset */
+#define RCC_APB1RSTR1_TIM3RST_Pos               (1U)
+#define RCC_APB1RSTR1_TIM3RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                   RCC_APB1RSTR1_TIM3RST_Msk            /*!< TIM3 reset */
+#define RCC_APB1RSTR1_TIM4RST_Pos               (2U)
+#define RCC_APB1RSTR1_TIM4RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)  /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                   RCC_APB1RSTR1_TIM4RST_Msk            /*!< TIM4 reset */
+#define RCC_APB1RSTR1_TIM5RST_Pos               (3U)
+#define RCC_APB1RSTR1_TIM5RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)  /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                   RCC_APB1RSTR1_TIM5RST_Msk            /*!< TIM5 reset */
+#define RCC_APB1RSTR1_TIM6RST_Pos               (4U)
+#define RCC_APB1RSTR1_TIM6RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)  /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                   RCC_APB1RSTR1_TIM6RST_Msk            /*!< TIM6 reset */
+#define RCC_APB1RSTR1_TIM7RST_Pos               (5U)
+#define RCC_APB1RSTR1_TIM7RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                   RCC_APB1RSTR1_TIM7RST_Msk            /*!< TIM7 reset */
+#define RCC_APB1RSTR1_TIM12RST_Pos              (6U)
+#define RCC_APB1RSTR1_TIM12RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR1_TIM12RST                  RCC_APB1RSTR1_TIM12RST_Msk           /*!< TIM12 reset */
+#define RCC_APB1RSTR1_TIM13RST_Pos              (7U)
+#define RCC_APB1RSTR1_TIM13RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR1_TIM13RST                  RCC_APB1RSTR1_TIM13RST_Msk           /*!< TIM13 reset */
+#define RCC_APB1RSTR1_TIM14RST_Pos              (8U)
+#define RCC_APB1RSTR1_TIM14RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR1_TIM14RST                  RCC_APB1RSTR1_TIM14RST_Msk           /*!< TIM14 reset */
+#define RCC_APB1RSTR1_LPTIM1RST_Pos             (9U)
+#define RCC_APB1RSTR1_LPTIM1RST_Msk             (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */
+#define RCC_APB1RSTR1_LPTIM1RST                 RCC_APB1RSTR1_LPTIM1RST_Msk          /*!< LPTIM1 reset */
+#define RCC_APB1RSTR1_WWDGRST_Pos               (11U)
+#define RCC_APB1RSTR1_WWDGRST_Msk               (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos)  /*!< 0x00000800 */
+#define RCC_APB1RSTR1_WWDGRST                   RCC_APB1RSTR1_WWDGRST_Msk            /*!< WWDG reset */
+#define RCC_APB1RSTR1_TIM10RST_Pos              (12U)
+#define RCC_APB1RSTR1_TIM10RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTR1_TIM10RST                  RCC_APB1RSTR1_TIM10RST_Msk           /*!< TIM10 reset */
+#define RCC_APB1RSTR1_TIM11RST_Pos              (13U)
+#define RCC_APB1RSTR1_TIM11RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTR1_TIM11RST                  RCC_APB1RSTR1_TIM11RST_Msk           /*!< TIM11 reset */
+#define RCC_APB1RSTR1_SPI2RST_Pos               (14U)
+#define RCC_APB1RSTR1_SPI2RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                   RCC_APB1RSTR1_SPI2RST_Msk            /*!< SPI2 reset */
+#define RCC_APB1RSTR1_SPI3RST_Pos               (15U)
+#define RCC_APB1RSTR1_SPI3RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                   RCC_APB1RSTR1_SPI3RST_Msk            /*!< SPI3 reset */
+#define RCC_APB1RSTR1_SPDIFRX1RST_Pos           (16U)
+#define RCC_APB1RSTR1_SPDIFRX1RST_Msk           (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB1RSTR1_SPDIFRX1RST               RCC_APB1RSTR1_SPDIFRX1RST_Msk        /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTR1_USART2RST_Pos             (17U)
+#define RCC_APB1RSTR1_USART2RST_Msk             (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST                 RCC_APB1RSTR1_USART2RST_Msk          /*!< USART2 reset */
+#define RCC_APB1RSTR1_USART3RST_Pos             (18U)
+#define RCC_APB1RSTR1_USART3RST_Msk             (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST                 RCC_APB1RSTR1_USART3RST_Msk          /*!< USART3 reset */
+#define RCC_APB1RSTR1_UART4RST_Pos              (19U)
+#define RCC_APB1RSTR1_UART4RST_Msk              (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST                  RCC_APB1RSTR1_UART4RST_Msk           /*!< UART4 reset */
+#define RCC_APB1RSTR1_UART5RST_Pos              (20U)
+#define RCC_APB1RSTR1_UART5RST_Msk              (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST                  RCC_APB1RSTR1_UART5RST_Msk           /*!< UART5 reset */
+#define RCC_APB1RSTR1_I2C1RST_Pos               (21U)
+#define RCC_APB1RSTR1_I2C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                   RCC_APB1RSTR1_I2C1RST_Msk            /*!< I2C1 reset */
+#define RCC_APB1RSTR1_I2C2RST_Pos               (22U)
+#define RCC_APB1RSTR1_I2C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                   RCC_APB1RSTR1_I2C2RST_Msk            /*!< I2C2 reset */
+#define RCC_APB1RSTR1_I2C3RST_Pos               (23U)
+#define RCC_APB1RSTR1_I2C3RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                   RCC_APB1RSTR1_I2C3RST_Msk            /*!< I2C3 reset */
+#define RCC_APB1RSTR1_I3C1RST_Pos               (24U)
+#define RCC_APB1RSTR1_I3C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos)  /*!< 0x01000000 */
+#define RCC_APB1RSTR1_I3C1RST                   RCC_APB1RSTR1_I3C1RST_Msk            /*!< I3C1 reset */
+#define RCC_APB1RSTR1_I3C2RST_Pos               (25U)
+#define RCC_APB1RSTR1_I3C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos)  /*!< 0x02000000 */
+#define RCC_APB1RSTR1_I3C2RST                   RCC_APB1RSTR1_I3C2RST_Msk            /*!< I3C2 reset */
+#define RCC_APB1RSTR1_UART7RST_Pos              (30U)
+#define RCC_APB1RSTR1_UART7RST_Msk              (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_UART7RST                  RCC_APB1RSTR1_UART7RST_Msk           /*!< UART7 reset */
+#define RCC_APB1RSTR1_UART8RST_Pos              (31U)
+#define RCC_APB1RSTR1_UART8RST_Msk              (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_UART8RST                  RCC_APB1RSTR1_UART8RST_Msk           /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTR2 register  *****************/
+#define RCC_APB1RSTR2_MDIOSRST_Pos              (5U)
+#define RCC_APB1RSTR2_MDIOSRST_Msk              (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_MDIOSRST                  RCC_APB1RSTR2_MDIOSRST_Msk            /*!< MDIOS reset */
+#define RCC_APB1RSTR2_FDCANRST_Pos              (8U)
+#define RCC_APB1RSTR2_FDCANRST_Msk              (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR2_FDCANRST                  RCC_APB1RSTR2_FDCANRST_Msk            /*!< FDCAN reset */
+#define RCC_APB1RSTR2_UCPD1RST_Pos              (18U)
+#define RCC_APB1RSTR2_UCPD1RST_Msk              (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR2_UCPD1RST                  RCC_APB1RSTR2_UCPD1RST_Msk            /*!< UCPD1 reset */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define RCC_APB2RSTR_TIM1RST_Pos                (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk                (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)   /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                    RCC_APB2RSTR_TIM1RST_Msk             /*!< TIM1 reset */
+#define RCC_APB2RSTR_TIM8RST_Pos                (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk                (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)   /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                    RCC_APB2RSTR_TIM8RST_Msk             /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST_Pos              (4U)
+#define RCC_APB2RSTR_USART1RST_Msk              (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                  RCC_APB2RSTR_USART1RST_Msk           /*!< USART1 reset */
+#define RCC_APB2RSTR_USART6RST_Pos              (5U)
+#define RCC_APB2RSTR_USART6RST_Msk              (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                  RCC_APB2RSTR_USART6RST_Msk           /*!< USART6 reset */
+#define RCC_APB2RSTR_UART9RST_Pos               (6U)
+#define RCC_APB2RSTR_UART9RST_Msk               (0x1UL << RCC_APB2RSTR_UART9RST_Pos)  /*!< 0x00000040 */
+#define RCC_APB2RSTR_UART9RST                   RCC_APB2RSTR_UART9RST_Msk            /*!< UART9 reset */
+#define RCC_APB2RSTR_USART10RST_Pos             (7U)
+#define RCC_APB2RSTR_USART10RST_Msk             (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */
+#define RCC_APB2RSTR_USART10RST                 RCC_APB2RSTR_USART10RST_Msk          /*!< USART10 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos                (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk                (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)   /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                    RCC_APB2RSTR_SPI1RST_Msk             /*!< SPI1 reset */
+#define RCC_APB2RSTR_SPI4RST_Pos                (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk                (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)   /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                    RCC_APB2RSTR_SPI4RST_Msk             /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM18RST_Pos               (15U)
+#define RCC_APB2RSTR_TIM18RST_Msk               (0x1UL << RCC_APB2RSTR_TIM18RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB2RSTR_TIM18RST                   RCC_APB2RSTR_TIM18RST_Msk            /*!< TIM18 reset */
+#define RCC_APB2RSTR_TIM15RST_Pos               (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk               (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                   RCC_APB2RSTR_TIM15RST_Msk            /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST_Pos               (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk               (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)  /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                   RCC_APB2RSTR_TIM16RST_Msk            /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST_Pos               (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk               (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)  /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                   RCC_APB2RSTR_TIM17RST_Msk            /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM9RST_Pos                (19U)
+#define RCC_APB2RSTR_TIM9RST_Msk                (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)   /*!< 0x00080000 */
+#define RCC_APB2RSTR_TIM9RST                    RCC_APB2RSTR_TIM9RST_Msk             /*!< TIM9 reset */
+#define RCC_APB2RSTR_SPI5RST_Pos                (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk                (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)   /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                    RCC_APB2RSTR_SPI5RST_Msk             /*!< SPI5 reset */
+#define RCC_APB2RSTR_SAI1RST_Pos                (21U)
+#define RCC_APB2RSTR_SAI1RST_Msk                (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)   /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                    RCC_APB2RSTR_SAI1RST_Msk             /*!< SAI1 reset */
+#define RCC_APB2RSTR_SAI2RST_Pos                (22U)
+#define RCC_APB2RSTR_SAI2RST_Msk                (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)   /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                    RCC_APB2RSTR_SAI2RST_Msk             /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTR1 register  *****************/
+#define RCC_APB4RSTR1_HDPRST_Pos                (2U)
+#define RCC_APB4RSTR1_HDPRST_Msk                (0x1UL << RCC_APB4RSTR1_HDPRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR1_HDPRST                    RCC_APB4RSTR1_HDPRST_Msk             /*!< HDP reset */
+#define RCC_APB4RSTR1_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR1_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR1_LPUART1RST                RCC_APB4RSTR1_LPUART1RST_Msk         /*!< LPUART1 reset */
+#define RCC_APB4RSTR1_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR1_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB4RSTR1_SPI6RST                   RCC_APB4RSTR1_SPI6RST_Msk            /*!< SPI6 reset */
+#define RCC_APB4RSTR1_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR1_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos)  /*!< 0x00000080 */
+#define RCC_APB4RSTR1_I2C4RST                   RCC_APB4RSTR1_I2C4RST_Msk            /*!< I2C4 reset */
+#define RCC_APB4RSTR1_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR1_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */
+#define RCC_APB4RSTR1_LPTIM2RST                 RCC_APB4RSTR1_LPTIM2RST_Msk          /*!< LPTIM2 reset */
+#define RCC_APB4RSTR1_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR1_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */
+#define RCC_APB4RSTR1_LPTIM3RST                 RCC_APB4RSTR1_LPTIM3RST_Msk          /*!< LPTIM3 reset */
+#define RCC_APB4RSTR1_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR1_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */
+#define RCC_APB4RSTR1_LPTIM4RST                 RCC_APB4RSTR1_LPTIM4RST_Msk          /*!< LPTIM4 reset */
+#define RCC_APB4RSTR1_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR1_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */
+#define RCC_APB4RSTR1_LPTIM5RST                 RCC_APB4RSTR1_LPTIM5RST_Msk          /*!< LPTIM5 reset */
+#define RCC_APB4RSTR1_VREFBUFRST_Pos            (15U)
+#define RCC_APB4RSTR1_VREFBUFRST_Msk            (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR1_VREFBUFRST                RCC_APB4RSTR1_VREFBUFRST_Msk         /*!< VREFBUF reset */
+#define RCC_APB4RSTR1_RTCRST_Pos                (16U)
+#define RCC_APB4RSTR1_RTCRST_Msk                (0x1UL << RCC_APB4RSTR1_RTCRST_Pos)   /*!< 0x00010000 */
+#define RCC_APB4RSTR1_RTCRST                    RCC_APB4RSTR1_RTCRST_Msk             /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTR2 register  *****************/
+#define RCC_APB4RSTR2_SYSCFGRST_Pos             (0U)
+#define RCC_APB4RSTR2_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */
+#define RCC_APB4RSTR2_SYSCFGRST                 RCC_APB4RSTR2_SYSCFGRST_Msk          /*!< SYSCFG reset */
+#define RCC_APB4RSTR2_DTSRST_Pos                (2U)
+#define RCC_APB4RSTR2_DTSRST_Msk                (0x1UL << RCC_APB4RSTR2_DTSRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR2_DTSRST                    RCC_APB4RSTR2_DTSRST_Msk             /*!< DTS reset */
+
+/*****************  Bit definition for RCC_APB5RSTR register  *****************/
+#define RCC_APB5RSTR_LTDCRST_Pos                (1U)
+#define RCC_APB5RSTR_LTDCRST_Msk                (0x1UL << RCC_APB5RSTR_LTDCRST_Pos)   /*!< 0x00000002 */
+#define RCC_APB5RSTR_LTDCRST                    RCC_APB5RSTR_LTDCRST_Msk             /*!< LTDC reset */
+#define RCC_APB5RSTR_DCMIPPRST_Pos              (2U)
+#define RCC_APB5RSTR_DCMIPPRST_Msk              (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTR_DCMIPPRST                  RCC_APB5RSTR_DCMIPPRST_Msk           /*!< DCMIPP reset */
+#define RCC_APB5RSTR_GFXTIMRST_Pos              (4U)
+#define RCC_APB5RSTR_GFXTIMRST_Msk              (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTR_GFXTIMRST                  RCC_APB5RSTR_GFXTIMRST_Msk           /*!< GFXTIM reset */
+#define RCC_APB5RSTR_VENCRST_Pos                (5U)
+#define RCC_APB5RSTR_VENCRST_Msk                (0x1UL << RCC_APB5RSTR_VENCRST_Pos)   /*!< 0x00000020 */
+#define RCC_APB5RSTR_VENCRST                    RCC_APB5RSTR_VENCRST_Msk             /*!< VENC reset */
+#define RCC_APB5RSTR_CSIRST_Pos                 (6U)
+#define RCC_APB5RSTR_CSIRST_Msk                 (0x1UL << RCC_APB5RSTR_CSIRST_Pos)    /*!< 0x00000040 */
+#define RCC_APB5RSTR_CSIRST                     RCC_APB5RSTR_CSIRST_Msk              /*!< CSI reset */
+
+/******************  Bit definition for RCC_DIVENR register  ******************/
+#define RCC_DIVENR_IC1EN_Pos                    (0U)
+#define RCC_DIVENR_IC1EN_Msk                    (0x1UL << RCC_DIVENR_IC1EN_Pos)       /*!< 0x00000001 */
+#define RCC_DIVENR_IC1EN                        RCC_DIVENR_IC1EN_Msk                 /*!< IC1 enable */
+#define RCC_DIVENR_IC2EN_Pos                    (1U)
+#define RCC_DIVENR_IC2EN_Msk                    (0x1UL << RCC_DIVENR_IC2EN_Pos)       /*!< 0x00000002 */
+#define RCC_DIVENR_IC2EN                        RCC_DIVENR_IC2EN_Msk                 /*!< IC2 enable */
+#define RCC_DIVENR_IC3EN_Pos                    (2U)
+#define RCC_DIVENR_IC3EN_Msk                    (0x1UL << RCC_DIVENR_IC3EN_Pos)       /*!< 0x00000004 */
+#define RCC_DIVENR_IC3EN                        RCC_DIVENR_IC3EN_Msk                 /*!< IC3 enable */
+#define RCC_DIVENR_IC4EN_Pos                    (3U)
+#define RCC_DIVENR_IC4EN_Msk                    (0x1UL << RCC_DIVENR_IC4EN_Pos)       /*!< 0x00000008 */
+#define RCC_DIVENR_IC4EN                        RCC_DIVENR_IC4EN_Msk                 /*!< IC4 enable */
+#define RCC_DIVENR_IC5EN_Pos                    (4U)
+#define RCC_DIVENR_IC5EN_Msk                    (0x1UL << RCC_DIVENR_IC5EN_Pos)       /*!< 0x00000010 */
+#define RCC_DIVENR_IC5EN                        RCC_DIVENR_IC5EN_Msk                 /*!< IC5 enable */
+#define RCC_DIVENR_IC6EN_Pos                    (5U)
+#define RCC_DIVENR_IC6EN_Msk                    (0x1UL << RCC_DIVENR_IC6EN_Pos)       /*!< 0x00000020 */
+#define RCC_DIVENR_IC6EN                        RCC_DIVENR_IC6EN_Msk                 /*!< IC6 enable */
+#define RCC_DIVENR_IC7EN_Pos                    (6U)
+#define RCC_DIVENR_IC7EN_Msk                    (0x1UL << RCC_DIVENR_IC7EN_Pos)       /*!< 0x00000040 */
+#define RCC_DIVENR_IC7EN                        RCC_DIVENR_IC7EN_Msk                 /*!< IC7 enable */
+#define RCC_DIVENR_IC8EN_Pos                    (7U)
+#define RCC_DIVENR_IC8EN_Msk                    (0x1UL << RCC_DIVENR_IC8EN_Pos)       /*!< 0x00000080 */
+#define RCC_DIVENR_IC8EN                        RCC_DIVENR_IC8EN_Msk                 /*!< IC8 enable */
+#define RCC_DIVENR_IC9EN_Pos                    (8U)
+#define RCC_DIVENR_IC9EN_Msk                    (0x1UL << RCC_DIVENR_IC9EN_Pos)       /*!< 0x00000100 */
+#define RCC_DIVENR_IC9EN                        RCC_DIVENR_IC9EN_Msk                 /*!< IC9 enable */
+#define RCC_DIVENR_IC10EN_Pos                   (9U)
+#define RCC_DIVENR_IC10EN_Msk                   (0x1UL << RCC_DIVENR_IC10EN_Pos)      /*!< 0x00000200 */
+#define RCC_DIVENR_IC10EN                       RCC_DIVENR_IC10EN_Msk                /*!< IC10 enable */
+#define RCC_DIVENR_IC11EN_Pos                   (10U)
+#define RCC_DIVENR_IC11EN_Msk                   (0x1UL << RCC_DIVENR_IC11EN_Pos)      /*!< 0x00000400 */
+#define RCC_DIVENR_IC11EN                       RCC_DIVENR_IC11EN_Msk                /*!< IC11 enable */
+#define RCC_DIVENR_IC12EN_Pos                   (11U)
+#define RCC_DIVENR_IC12EN_Msk                   (0x1UL << RCC_DIVENR_IC12EN_Pos)      /*!< 0x00000800 */
+#define RCC_DIVENR_IC12EN                       RCC_DIVENR_IC12EN_Msk                /*!< IC12 enable */
+#define RCC_DIVENR_IC13EN_Pos                   (12U)
+#define RCC_DIVENR_IC13EN_Msk                   (0x1UL << RCC_DIVENR_IC13EN_Pos)      /*!< 0x00001000 */
+#define RCC_DIVENR_IC13EN                       RCC_DIVENR_IC13EN_Msk                /*!< IC13 enable */
+#define RCC_DIVENR_IC14EN_Pos                   (13U)
+#define RCC_DIVENR_IC14EN_Msk                   (0x1UL << RCC_DIVENR_IC14EN_Pos)      /*!< 0x00002000 */
+#define RCC_DIVENR_IC14EN                       RCC_DIVENR_IC14EN_Msk                /*!< IC14 enable */
+#define RCC_DIVENR_IC15EN_Pos                   (14U)
+#define RCC_DIVENR_IC15EN_Msk                   (0x1UL << RCC_DIVENR_IC15EN_Pos)      /*!< 0x00004000 */
+#define RCC_DIVENR_IC15EN                       RCC_DIVENR_IC15EN_Msk                /*!< IC15 enable */
+#define RCC_DIVENR_IC16EN_Pos                   (15U)
+#define RCC_DIVENR_IC16EN_Msk                   (0x1UL << RCC_DIVENR_IC16EN_Pos)      /*!< 0x00008000 */
+#define RCC_DIVENR_IC16EN                       RCC_DIVENR_IC16EN_Msk                /*!< IC16 enable */
+#define RCC_DIVENR_IC17EN_Pos                   (16U)
+#define RCC_DIVENR_IC17EN_Msk                   (0x1UL << RCC_DIVENR_IC17EN_Pos)      /*!< 0x00010000 */
+#define RCC_DIVENR_IC17EN                       RCC_DIVENR_IC17EN_Msk                /*!< IC17 enable */
+#define RCC_DIVENR_IC18EN_Pos                   (17U)
+#define RCC_DIVENR_IC18EN_Msk                   (0x1UL << RCC_DIVENR_IC18EN_Pos)      /*!< 0x00020000 */
+#define RCC_DIVENR_IC18EN                       RCC_DIVENR_IC18EN_Msk                /*!< IC18 enable */
+#define RCC_DIVENR_IC19EN_Pos                   (18U)
+#define RCC_DIVENR_IC19EN_Msk                   (0x1UL << RCC_DIVENR_IC19EN_Pos)      /*!< 0x00040000 */
+#define RCC_DIVENR_IC19EN                       RCC_DIVENR_IC19EN_Msk                /*!< IC19 enable */
+#define RCC_DIVENR_IC20EN_Pos                   (19U)
+#define RCC_DIVENR_IC20EN_Msk                   (0x1UL << RCC_DIVENR_IC20EN_Pos)      /*!< 0x00080000 */
+#define RCC_DIVENR_IC20EN                       RCC_DIVENR_IC20EN_Msk                /*!< IC20 enable */
+
+/******************  Bit definition for RCC_BUSENR register  ******************/
+#define RCC_BUSENR_ACLKNEN_Pos                  (0U)
+#define RCC_BUSENR_ACLKNEN_Msk                  (0x1UL << RCC_BUSENR_ACLKNEN_Pos)     /*!< 0x00000001 */
+#define RCC_BUSENR_ACLKNEN                      RCC_BUSENR_ACLKNEN_Msk               /*!< ACLKN enable */
+#define RCC_BUSENR_ACLKNCEN_Pos                 (1U)
+#define RCC_BUSENR_ACLKNCEN_Msk                 (0x1UL << RCC_BUSENR_ACLKNCEN_Pos)    /*!< 0x00000002 */
+#define RCC_BUSENR_ACLKNCEN                     RCC_BUSENR_ACLKNCEN_Msk              /*!< ACLKNC enable */
+#define RCC_BUSENR_AHBMEN_Pos                   (2U)
+#define RCC_BUSENR_AHBMEN_Msk                   (0x1UL << RCC_BUSENR_AHBMEN_Pos)      /*!< 0x00000004 */
+#define RCC_BUSENR_AHBMEN                       RCC_BUSENR_AHBMEN_Msk                /*!< AHBM enable */
+#define RCC_BUSENR_AHB1EN_Pos                   (3U)
+#define RCC_BUSENR_AHB1EN_Msk                   (0x1UL << RCC_BUSENR_AHB1EN_Pos)      /*!< 0x00000008 */
+#define RCC_BUSENR_AHB1EN                       RCC_BUSENR_AHB1EN_Msk                /*!< AHB1 enable */
+#define RCC_BUSENR_AHB2EN_Pos                   (4U)
+#define RCC_BUSENR_AHB2EN_Msk                   (0x1UL << RCC_BUSENR_AHB2EN_Pos)      /*!< 0x00000010 */
+#define RCC_BUSENR_AHB2EN                       RCC_BUSENR_AHB2EN_Msk                /*!< AHB2 enable */
+#define RCC_BUSENR_AHB3EN_Pos                   (5U)
+#define RCC_BUSENR_AHB3EN_Msk                   (0x1UL << RCC_BUSENR_AHB3EN_Pos)      /*!< 0x00000020 */
+#define RCC_BUSENR_AHB3EN                       RCC_BUSENR_AHB3EN_Msk                /*!< AHB3 enable */
+#define RCC_BUSENR_AHB4EN_Pos                   (6U)
+#define RCC_BUSENR_AHB4EN_Msk                   (0x1UL << RCC_BUSENR_AHB4EN_Pos)      /*!< 0x00000040 */
+#define RCC_BUSENR_AHB4EN                       RCC_BUSENR_AHB4EN_Msk                /*!< AHB4 enable */
+#define RCC_BUSENR_AHB5EN_Pos                   (7U)
+#define RCC_BUSENR_AHB5EN_Msk                   (0x1UL << RCC_BUSENR_AHB5EN_Pos)      /*!< 0x00000080 */
+#define RCC_BUSENR_AHB5EN                       RCC_BUSENR_AHB5EN_Msk                /*!< AHB5 enable */
+#define RCC_BUSENR_APB1EN_Pos                   (8U)
+#define RCC_BUSENR_APB1EN_Msk                   (0x1UL << RCC_BUSENR_APB1EN_Pos)      /*!< 0x00000100 */
+#define RCC_BUSENR_APB1EN                       RCC_BUSENR_APB1EN_Msk                /*!< APB1 enable */
+#define RCC_BUSENR_APB2EN_Pos                   (9U)
+#define RCC_BUSENR_APB2EN_Msk                   (0x1UL << RCC_BUSENR_APB2EN_Pos)      /*!< 0x00000200 */
+#define RCC_BUSENR_APB2EN                       RCC_BUSENR_APB2EN_Msk                /*!< APB2 enable */
+#define RCC_BUSENR_APB3EN_Pos                   (10U)
+#define RCC_BUSENR_APB3EN_Msk                   (0x1UL << RCC_BUSENR_APB3EN_Pos)      /*!< 0x00000400 */
+#define RCC_BUSENR_APB3EN                       RCC_BUSENR_APB3EN_Msk                /*!< APB3 enable */
+#define RCC_BUSENR_APB4EN_Pos                   (11U)
+#define RCC_BUSENR_APB4EN_Msk                   (0x1UL << RCC_BUSENR_APB4EN_Pos)      /*!< 0x00000800 */
+#define RCC_BUSENR_APB4EN                       RCC_BUSENR_APB4EN_Msk                /*!< APB4 enable */
+#define RCC_BUSENR_APB5EN_Pos                   (12U)
+#define RCC_BUSENR_APB5EN_Msk                   (0x1UL << RCC_BUSENR_APB5EN_Pos)      /*!< 0x00001000 */
+#define RCC_BUSENR_APB5EN                       RCC_BUSENR_APB5EN_Msk                /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENR register  ******************/
+#define RCC_MISCENR_DBGEN_Pos                   (0U)
+#define RCC_MISCENR_DBGEN_Msk                   (0x1UL << RCC_MISCENR_DBGEN_Pos)      /*!< 0x00000001 */
+#define RCC_MISCENR_DBGEN                       RCC_MISCENR_DBGEN_Msk                /*!< DBG enable */
+#define RCC_MISCENR_MCO1EN_Pos                  (1U)
+#define RCC_MISCENR_MCO1EN_Msk                  (0x1UL << RCC_MISCENR_MCO1EN_Pos)     /*!< 0x00000002 */
+#define RCC_MISCENR_MCO1EN                      RCC_MISCENR_MCO1EN_Msk               /*!< MCO1 enable */
+#define RCC_MISCENR_MCO2EN_Pos                  (2U)
+#define RCC_MISCENR_MCO2EN_Msk                  (0x1UL << RCC_MISCENR_MCO2EN_Pos)     /*!< 0x00000004 */
+#define RCC_MISCENR_MCO2EN                      RCC_MISCENR_MCO2EN_Msk               /*!< MCO2 enable */
+#define RCC_MISCENR_XSPIPHYCOMPEN_Pos           (3U)
+#define RCC_MISCENR_XSPIPHYCOMPEN_Msk           (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MISCENR_XSPIPHYCOMPEN               RCC_MISCENR_XSPIPHYCOMPEN_Msk        /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENR_PEREN_Pos                   (6U)
+#define RCC_MISCENR_PEREN_Msk                   (0x1UL << RCC_MISCENR_PEREN_Pos)      /*!< 0x00000040 */
+#define RCC_MISCENR_PEREN                       RCC_MISCENR_PEREN_Msk                /*!< PER enable */
+
+/******************  Bit definition for RCC_MEMENR register  ******************/
+#define RCC_MEMENR_AXISRAM3EN_Pos               (0U)
+#define RCC_MEMENR_AXISRAM3EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMENR_AXISRAM3EN                   RCC_MEMENR_AXISRAM3EN_Msk            /*!< AXISRAM3 enable */
+#define RCC_MEMENR_AXISRAM4EN_Pos               (1U)
+#define RCC_MEMENR_AXISRAM4EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMENR_AXISRAM4EN                   RCC_MEMENR_AXISRAM4EN_Msk            /*!< AXISRAM4 enable */
+#define RCC_MEMENR_AXISRAM5EN_Pos               (2U)
+#define RCC_MEMENR_AXISRAM5EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMENR_AXISRAM5EN                   RCC_MEMENR_AXISRAM5EN_Msk            /*!< AXISRAM5 enable */
+#define RCC_MEMENR_AXISRAM6EN_Pos               (3U)
+#define RCC_MEMENR_AXISRAM6EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMENR_AXISRAM6EN                   RCC_MEMENR_AXISRAM6EN_Msk            /*!< AXISRAM6 enable */
+#define RCC_MEMENR_AHBSRAM1EN_Pos               (4U)
+#define RCC_MEMENR_AHBSRAM1EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMENR_AHBSRAM1EN                   RCC_MEMENR_AHBSRAM1EN_Msk            /*!< AHBSRAM1 enable */
+#define RCC_MEMENR_AHBSRAM2EN_Pos               (5U)
+#define RCC_MEMENR_AHBSRAM2EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMENR_AHBSRAM2EN                   RCC_MEMENR_AHBSRAM2EN_Msk            /*!< AHBSRAM2 enable */
+#define RCC_MEMENR_BKPSRAMEN_Pos                (6U)
+#define RCC_MEMENR_BKPSRAMEN_Msk                (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos)   /*!< 0x00000040 */
+#define RCC_MEMENR_BKPSRAMEN                    RCC_MEMENR_BKPSRAMEN_Msk             /*!< BKPSRAM enable */
+#define RCC_MEMENR_AXISRAM1EN_Pos               (7U)
+#define RCC_MEMENR_AXISRAM1EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMENR_AXISRAM1EN                   RCC_MEMENR_AXISRAM1EN_Msk            /*!< AXISRAM1 enable */
+#define RCC_MEMENR_AXISRAM2EN_Pos               (8U)
+#define RCC_MEMENR_AXISRAM2EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMENR_AXISRAM2EN                   RCC_MEMENR_AXISRAM2EN_Msk            /*!< AXISRAM2 enable */
+#define RCC_MEMENR_FLEXRAMEN_Pos                (9U)
+#define RCC_MEMENR_FLEXRAMEN_Msk                (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos)   /*!< 0x00000200 */
+#define RCC_MEMENR_FLEXRAMEN                    RCC_MEMENR_FLEXRAMEN_Msk             /*!< FLEXRAM enable */
+#define RCC_MEMENR_VENCRAMEN_Pos                (11U)
+#define RCC_MEMENR_VENCRAMEN_Msk                (0x1UL << RCC_MEMENR_VENCRAMEN_Pos)   /*!< 0x00000800 */
+#define RCC_MEMENR_VENCRAMEN                    RCC_MEMENR_VENCRAMEN_Msk             /*!< VENCRAM enable */
+#define RCC_MEMENR_BOOTROMEN_Pos                (12U)
+#define RCC_MEMENR_BOOTROMEN_Msk                (0x1UL << RCC_MEMENR_BOOTROMEN_Pos)   /*!< 0x00001000 */
+#define RCC_MEMENR_BOOTROMEN                    RCC_MEMENR_BOOTROMEN_Msk             /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENR register  ******************/
+#define RCC_AHB1ENR_GPDMA1EN_Pos                (4U)
+#define RCC_AHB1ENR_GPDMA1EN_Msk                (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPDMA1EN                    RCC_AHB1ENR_GPDMA1EN_Msk             /*!< GPDMA1 enable */
+#define RCC_AHB1ENR_ADC12EN_Pos                 (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                 (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                     RCC_AHB1ENR_ADC12EN_Msk              /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENR register  ******************/
+#define RCC_AHB2ENR_RAMCFGEN_Pos                (12U)
+#define RCC_AHB2ENR_RAMCFGEN_Msk                (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2ENR_RAMCFGEN                    RCC_AHB2ENR_RAMCFGEN_Msk             /*!< RAMCFG enable */
+#define RCC_AHB2ENR_MDF1EN_Pos                  (16U)
+#define RCC_AHB2ENR_MDF1EN_Msk                  (0x1UL << RCC_AHB2ENR_MDF1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB2ENR_MDF1EN                      RCC_AHB2ENR_MDF1EN_Msk               /*!< MDF1 enable */
+#define RCC_AHB2ENR_ADF1EN_Pos                  (17U)
+#define RCC_AHB2ENR_ADF1EN_Msk                  (0x1UL << RCC_AHB2ENR_ADF1EN_Pos)     /*!< 0x00020000 */
+#define RCC_AHB2ENR_ADF1EN                      RCC_AHB2ENR_ADF1EN_Msk               /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENR register  ******************/
+#define RCC_AHB3ENR_RNGEN_Pos                   (0U)
+#define RCC_AHB3ENR_RNGEN_Msk                   (0x1UL << RCC_AHB3ENR_RNGEN_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3ENR_RNGEN                       RCC_AHB3ENR_RNGEN_Msk                /*!< RNG enable */
+#define RCC_AHB3ENR_HASHEN_Pos                  (1U)
+#define RCC_AHB3ENR_HASHEN_Msk                  (0x1UL << RCC_AHB3ENR_HASHEN_Pos)     /*!< 0x00000002 */
+#define RCC_AHB3ENR_HASHEN                      RCC_AHB3ENR_HASHEN_Msk               /*!< HASH enable */
+#define RCC_AHB3ENR_CRYPEN_Pos                  (2U)
+#define RCC_AHB3ENR_CRYPEN_Msk                  (0x1UL << RCC_AHB3ENR_CRYPEN_Pos)     /*!< 0x00000004 */
+#define RCC_AHB3ENR_CRYPEN                      RCC_AHB3ENR_CRYPEN_Msk               /*!< CRYP enable */
+#define RCC_AHB3ENR_SAESEN_Pos                  (4U)
+#define RCC_AHB3ENR_SAESEN_Msk                  (0x1UL << RCC_AHB3ENR_SAESEN_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3ENR_SAESEN                      RCC_AHB3ENR_SAESEN_Msk               /*!< SAES enable */
+#define RCC_AHB3ENR_PKAEN_Pos                   (8U)
+#define RCC_AHB3ENR_PKAEN_Msk                   (0x1UL << RCC_AHB3ENR_PKAEN_Pos)      /*!< 0x00000100 */
+#define RCC_AHB3ENR_PKAEN                       RCC_AHB3ENR_PKAEN_Msk                /*!< PKA enable */
+#define RCC_AHB3ENR_RIFSCEN_Pos                 (9U)
+#define RCC_AHB3ENR_RIFSCEN_Msk                 (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos)    /*!< 0x00000200 */
+#define RCC_AHB3ENR_RIFSCEN                     RCC_AHB3ENR_RIFSCEN_Msk              /*!< RIFSC enable */
+#define RCC_AHB3ENR_IACEN_Pos                   (10U)
+#define RCC_AHB3ENR_IACEN_Msk                   (0x1UL << RCC_AHB3ENR_IACEN_Pos)      /*!< 0x00000400 */
+#define RCC_AHB3ENR_IACEN                       RCC_AHB3ENR_IACEN_Msk                /*!< IAC enable */
+#define RCC_AHB3ENR_RISAFEN_Pos                 (14U)
+#define RCC_AHB3ENR_RISAFEN_Msk                 (0x1UL << RCC_AHB3ENR_RISAFEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB3ENR_RISAFEN                     RCC_AHB3ENR_RISAFEN_Msk              /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                 (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                     RCC_AHB4ENR_GPIOAEN_Msk              /*!< GPIO A enable */
+#define RCC_AHB4ENR_GPIOBEN_Pos                 (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                     RCC_AHB4ENR_GPIOBEN_Msk              /*!< GPIO B enable */
+#define RCC_AHB4ENR_GPIOCEN_Pos                 (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)    /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                     RCC_AHB4ENR_GPIOCEN_Msk              /*!< GPIO C enable */
+#define RCC_AHB4ENR_GPIODEN_Pos                 (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)    /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                     RCC_AHB4ENR_GPIODEN_Msk              /*!< GPIO D enable */
+#define RCC_AHB4ENR_GPIOEEN_Pos                 (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)    /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                     RCC_AHB4ENR_GPIOEEN_Msk              /*!< GPIO E enable */
+#define RCC_AHB4ENR_GPIOFEN_Pos                 (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                     RCC_AHB4ENR_GPIOFEN_Msk              /*!< GPIO F enable */
+#define RCC_AHB4ENR_GPIOGEN_Pos                 (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)    /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                     RCC_AHB4ENR_GPIOGEN_Msk              /*!< GPIO G enable */
+#define RCC_AHB4ENR_GPIOHEN_Pos                 (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)    /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                     RCC_AHB4ENR_GPIOHEN_Msk              /*!< GPIO H enable */
+#define RCC_AHB4ENR_GPIONEN_Pos                 (13U)
+#define RCC_AHB4ENR_GPIONEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIONEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB4ENR_GPIONEN                     RCC_AHB4ENR_GPIONEN_Msk              /*!< GPIO N enable */
+#define RCC_AHB4ENR_GPIOOEN_Pos                 (14U)
+#define RCC_AHB4ENR_GPIOOEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB4ENR_GPIOOEN                     RCC_AHB4ENR_GPIOOEN_Msk              /*!< GPIO O enable */
+#define RCC_AHB4ENR_GPIOPEN_Pos                 (15U)
+#define RCC_AHB4ENR_GPIOPEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos)    /*!< 0x00008000 */
+#define RCC_AHB4ENR_GPIOPEN                     RCC_AHB4ENR_GPIOPEN_Msk              /*!< GPIO P enable */
+#define RCC_AHB4ENR_GPIOQEN_Pos                 (16U)
+#define RCC_AHB4ENR_GPIOQEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos)    /*!< 0x00010000 */
+#define RCC_AHB4ENR_GPIOQEN                     RCC_AHB4ENR_GPIOQEN_Msk              /*!< GPIO Q enable */
+#define RCC_AHB4ENR_PWREN_Pos                   (18U)
+#define RCC_AHB4ENR_PWREN_Msk                   (0x1UL << RCC_AHB4ENR_PWREN_Pos)      /*!< 0x00040000 */
+#define RCC_AHB4ENR_PWREN                       RCC_AHB4ENR_PWREN_Msk                /*!< PWR enable */
+#define RCC_AHB4ENR_CRCEN_Pos                   (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                   (0x1UL << RCC_AHB4ENR_CRCEN_Pos)      /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                       RCC_AHB4ENR_CRCEN_Msk                /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENR register  ******************/
+#define RCC_AHB5ENR_HPDMA1EN_Pos                (0U)
+#define RCC_AHB5ENR_HPDMA1EN_Msk                (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5ENR_HPDMA1EN                    RCC_AHB5ENR_HPDMA1EN_Msk             /*!< HPDMA1 enable */
+#define RCC_AHB5ENR_DMA2DEN_Pos                 (1U)
+#define RCC_AHB5ENR_DMA2DEN_Msk                 (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB5ENR_DMA2DEN                     RCC_AHB5ENR_DMA2DEN_Msk              /*!< DMA2D enable */
+#define RCC_AHB5ENR_JPEGEN_Pos                  (3U)
+#define RCC_AHB5ENR_JPEGEN_Msk                  (0x1UL << RCC_AHB5ENR_JPEGEN_Pos)     /*!< 0x00000008 */
+#define RCC_AHB5ENR_JPEGEN                      RCC_AHB5ENR_JPEGEN_Msk               /*!< JPEG enable */
+#define RCC_AHB5ENR_FMCEN_Pos                   (4U)
+#define RCC_AHB5ENR_FMCEN_Msk                   (0x1UL << RCC_AHB5ENR_FMCEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB5ENR_FMCEN                       RCC_AHB5ENR_FMCEN_Msk                /*!< FMC enable */
+#define RCC_AHB5ENR_XSPI1EN_Pos                 (5U)
+#define RCC_AHB5ENR_XSPI1EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB5ENR_XSPI1EN                     RCC_AHB5ENR_XSPI1EN_Msk              /*!< XSPI1 enable */
+#define RCC_AHB5ENR_PSSIEN_Pos                  (6U)
+#define RCC_AHB5ENR_PSSIEN_Msk                  (0x1UL << RCC_AHB5ENR_PSSIEN_Pos)     /*!< 0x00000040 */
+#define RCC_AHB5ENR_PSSIEN                      RCC_AHB5ENR_PSSIEN_Msk               /*!< PSSI enable */
+#define RCC_AHB5ENR_SDMMC2EN_Pos                (7U)
+#define RCC_AHB5ENR_SDMMC2EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5ENR_SDMMC2EN                    RCC_AHB5ENR_SDMMC2EN_Msk             /*!< SDMMC2 enable */
+#define RCC_AHB5ENR_SDMMC1EN_Pos                (8U)
+#define RCC_AHB5ENR_SDMMC1EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5ENR_SDMMC1EN                    RCC_AHB5ENR_SDMMC1EN_Msk             /*!< SDMMC1 enable */
+#define RCC_AHB5ENR_XSPI2EN_Pos                 (12U)
+#define RCC_AHB5ENR_XSPI2EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos)    /*!< 0x00001000 */
+#define RCC_AHB5ENR_XSPI2EN                     RCC_AHB5ENR_XSPI2EN_Msk              /*!< XSPI2 enable */
+#define RCC_AHB5ENR_XSPIMEN_Pos                 (13U)
+#define RCC_AHB5ENR_XSPIMEN_Msk                 (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB5ENR_XSPIMEN                     RCC_AHB5ENR_XSPIMEN_Msk              /*!< XSPIM enable */
+#define RCC_AHB5ENR_MCE1EN_Pos                  (14U)
+#define RCC_AHB5ENR_MCE1EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE1EN_Pos)     /*!< 0x00004000 */
+#define RCC_AHB5ENR_MCE1EN                      RCC_AHB5ENR_MCE1EN_Msk               /*!< MCE1 enable */
+#define RCC_AHB5ENR_MCE2EN_Pos                  (15U)
+#define RCC_AHB5ENR_MCE2EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE2EN_Pos)     /*!< 0x00008000 */
+#define RCC_AHB5ENR_MCE2EN                      RCC_AHB5ENR_MCE2EN_Msk               /*!< MCE2 enable */
+#define RCC_AHB5ENR_MCE3EN_Pos                  (16U)
+#define RCC_AHB5ENR_MCE3EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE3EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB5ENR_MCE3EN                      RCC_AHB5ENR_MCE3EN_Msk               /*!< MCE3 enable */
+#define RCC_AHB5ENR_XSPI3EN_Pos                 (17U)
+#define RCC_AHB5ENR_XSPI3EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos)    /*!< 0x00020000 */
+#define RCC_AHB5ENR_XSPI3EN                     RCC_AHB5ENR_XSPI3EN_Msk              /*!< XSPI3 enable */
+#define RCC_AHB5ENR_MCE4EN_Pos                  (18U)
+#define RCC_AHB5ENR_MCE4EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE4EN_Pos)     /*!< 0x00040000 */
+#define RCC_AHB5ENR_MCE4EN                      RCC_AHB5ENR_MCE4EN_Msk               /*!< MCE4 enable */
+#define RCC_AHB5ENR_GFXMMUEN_Pos                (19U)
+#define RCC_AHB5ENR_GFXMMUEN_Msk                (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5ENR_GFXMMUEN                    RCC_AHB5ENR_GFXMMUEN_Msk             /*!< GFXMMU enable */
+#define RCC_AHB5ENR_GPU2DEN_Pos                 (20U)
+#define RCC_AHB5ENR_GPU2DEN_Msk                 (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos)    /*!< 0x00100000 */
+#define RCC_AHB5ENR_GPU2DEN                     RCC_AHB5ENR_GPU2DEN_Msk              /*!< GPU2D enable */
+#define RCC_AHB5ENR_ETH1MACEN_Pos               (22U)
+#define RCC_AHB5ENR_ETH1MACEN_Msk               (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5ENR_ETH1MACEN                   RCC_AHB5ENR_ETH1MACEN_Msk            /*!< ETH1MAC enable */
+#define RCC_AHB5ENR_ETH1TXEN_Pos                (23U)
+#define RCC_AHB5ENR_ETH1TXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5ENR_ETH1TXEN                    RCC_AHB5ENR_ETH1TXEN_Msk             /*!< ETH1TX enable */
+#define RCC_AHB5ENR_ETH1RXEN_Pos                (24U)
+#define RCC_AHB5ENR_ETH1RXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5ENR_ETH1RXEN                    RCC_AHB5ENR_ETH1RXEN_Msk             /*!< ETH1RX enable */
+#define RCC_AHB5ENR_ETH1EN_Pos                  (25U)
+#define RCC_AHB5ENR_ETH1EN_Msk                  (0x1UL << RCC_AHB5ENR_ETH1EN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB5ENR_ETH1EN                      RCC_AHB5ENR_ETH1EN_Msk               /*!< ETH1 enable */
+#define RCC_AHB5ENR_OTG1EN_Pos                  (26U)
+#define RCC_AHB5ENR_OTG1EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG1EN_Pos)     /*!< 0x04000000 */
+#define RCC_AHB5ENR_OTG1EN                      RCC_AHB5ENR_OTG1EN_Msk               /*!< OTG1 enable */
+#define RCC_AHB5ENR_OTGPHY1EN_Pos               (27U)
+#define RCC_AHB5ENR_OTGPHY1EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5ENR_OTGPHY1EN                   RCC_AHB5ENR_OTGPHY1EN_Msk            /*!< OTGPHY1 enable */
+#define RCC_AHB5ENR_OTGPHY2EN_Pos               (28U)
+#define RCC_AHB5ENR_OTGPHY2EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5ENR_OTGPHY2EN                   RCC_AHB5ENR_OTGPHY2EN_Msk            /*!< OTGPHY2 enable */
+#define RCC_AHB5ENR_OTG2EN_Pos                  (29U)
+#define RCC_AHB5ENR_OTG2EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG2EN_Pos)     /*!< 0x20000000 */
+#define RCC_AHB5ENR_OTG2EN                      RCC_AHB5ENR_OTG2EN_Msk               /*!< OTG2 enable */
+
+/*****************  Bit definition for RCC_APB1ENR1 register  *****************/
+#define RCC_APB1ENR1_TIM2EN_Pos                 (0U)
+#define RCC_APB1ENR1_TIM2EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                     RCC_APB1ENR1_TIM2EN_Msk              /*!< TIM2 enable */
+#define RCC_APB1ENR1_TIM3EN_Pos                 (1U)
+#define RCC_APB1ENR1_TIM3EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                     RCC_APB1ENR1_TIM3EN_Msk              /*!< TIM3 enable */
+#define RCC_APB1ENR1_TIM4EN_Pos                 (2U)
+#define RCC_APB1ENR1_TIM4EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)    /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                     RCC_APB1ENR1_TIM4EN_Msk              /*!< TIM4 enable */
+#define RCC_APB1ENR1_TIM5EN_Pos                 (3U)
+#define RCC_APB1ENR1_TIM5EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)    /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                     RCC_APB1ENR1_TIM5EN_Msk              /*!< TIM5 enable */
+#define RCC_APB1ENR1_TIM6EN_Pos                 (4U)
+#define RCC_APB1ENR1_TIM6EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)    /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                     RCC_APB1ENR1_TIM6EN_Msk              /*!< TIM6 enable */
+#define RCC_APB1ENR1_TIM7EN_Pos                 (5U)
+#define RCC_APB1ENR1_TIM7EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                     RCC_APB1ENR1_TIM7EN_Msk              /*!< TIM7 enable */
+#define RCC_APB1ENR1_TIM12EN_Pos                (6U)
+#define RCC_APB1ENR1_TIM12EN_Msk                (0x1UL << RCC_APB1ENR1_TIM12EN_Pos)   /*!< 0x00000040 */
+#define RCC_APB1ENR1_TIM12EN                    RCC_APB1ENR1_TIM12EN_Msk             /*!< TIM12 enable */
+#define RCC_APB1ENR1_TIM13EN_Pos                (7U)
+#define RCC_APB1ENR1_TIM13EN_Msk                (0x1UL << RCC_APB1ENR1_TIM13EN_Pos)   /*!< 0x00000080 */
+#define RCC_APB1ENR1_TIM13EN                    RCC_APB1ENR1_TIM13EN_Msk             /*!< TIM13 enable */
+#define RCC_APB1ENR1_TIM14EN_Pos                (8U)
+#define RCC_APB1ENR1_TIM14EN_Msk                (0x1UL << RCC_APB1ENR1_TIM14EN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR1_TIM14EN                    RCC_APB1ENR1_TIM14EN_Msk             /*!< TIM14 enable */
+#define RCC_APB1ENR1_LPTIM1EN_Pos               (9U)
+#define RCC_APB1ENR1_LPTIM1EN_Msk               (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LPTIM1EN                   RCC_APB1ENR1_LPTIM1EN_Msk            /*!< LPTIM1 enable */
+#define RCC_APB1ENR1_WWDGEN_Pos                 (11U)
+#define RCC_APB1ENR1_WWDGEN_Msk                 (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                     RCC_APB1ENR1_WWDGEN_Msk              /*!< WWDG enable */
+#define RCC_APB1ENR1_TIM10EN_Pos                (12U)
+#define RCC_APB1ENR1_TIM10EN_Msk                (0x1UL << RCC_APB1ENR1_TIM10EN_Pos)   /*!< 0x00001000 */
+#define RCC_APB1ENR1_TIM10EN                    RCC_APB1ENR1_TIM10EN_Msk             /*!< TIM10 enable */
+#define RCC_APB1ENR1_TIM11EN_Pos                (13U)
+#define RCC_APB1ENR1_TIM11EN_Msk                (0x1UL << RCC_APB1ENR1_TIM11EN_Pos)   /*!< 0x00002000 */
+#define RCC_APB1ENR1_TIM11EN                    RCC_APB1ENR1_TIM11EN_Msk             /*!< TIM11 enable */
+#define RCC_APB1ENR1_SPI2EN_Pos                 (14U)
+#define RCC_APB1ENR1_SPI2EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                     RCC_APB1ENR1_SPI2EN_Msk              /*!< SPI2 enable */
+#define RCC_APB1ENR1_SPI3EN_Pos                 (15U)
+#define RCC_APB1ENR1_SPI3EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                     RCC_APB1ENR1_SPI3EN_Msk              /*!< SPI3 enable */
+#define RCC_APB1ENR1_SPDIFRX1EN_Pos             (16U)
+#define RCC_APB1ENR1_SPDIFRX1EN_Msk             (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */
+#define RCC_APB1ENR1_SPDIFRX1EN                 RCC_APB1ENR1_SPDIFRX1EN_Msk          /*!< SPDIFRX1 enable */
+#define RCC_APB1ENR1_USART2EN_Pos               (17U)
+#define RCC_APB1ENR1_USART2EN_Msk               (0x1UL << RCC_APB1ENR1_USART2EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                   RCC_APB1ENR1_USART2EN_Msk            /*!< USART2 enable */
+#define RCC_APB1ENR1_USART3EN_Pos               (18U)
+#define RCC_APB1ENR1_USART3EN_Msk               (0x1UL << RCC_APB1ENR1_USART3EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                   RCC_APB1ENR1_USART3EN_Msk            /*!< USART3 enable */
+#define RCC_APB1ENR1_UART4EN_Pos                (19U)
+#define RCC_APB1ENR1_UART4EN_Msk                (0x1UL << RCC_APB1ENR1_UART4EN_Pos)   /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                    RCC_APB1ENR1_UART4EN_Msk             /*!< UART4 enable */
+#define RCC_APB1ENR1_UART5EN_Pos                (20U)
+#define RCC_APB1ENR1_UART5EN_Msk                (0x1UL << RCC_APB1ENR1_UART5EN_Pos)   /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                    RCC_APB1ENR1_UART5EN_Msk             /*!< UART5 enable */
+#define RCC_APB1ENR1_I2C1EN_Pos                 (21U)
+#define RCC_APB1ENR1_I2C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                     RCC_APB1ENR1_I2C1EN_Msk              /*!< I2C1 enable */
+#define RCC_APB1ENR1_I2C2EN_Pos                 (22U)
+#define RCC_APB1ENR1_I2C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                     RCC_APB1ENR1_I2C2EN_Msk              /*!< I2C2 enable */
+#define RCC_APB1ENR1_I2C3EN_Pos                 (23U)
+#define RCC_APB1ENR1_I2C3EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                     RCC_APB1ENR1_I2C3EN_Msk              /*!< I2C3 enable */
+#define RCC_APB1ENR1_I3C1EN_Pos                 (24U)
+#define RCC_APB1ENR1_I3C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C1EN_Pos)    /*!< 0x01000000 */
+#define RCC_APB1ENR1_I3C1EN                     RCC_APB1ENR1_I3C1EN_Msk              /*!< I3C1 enable */
+#define RCC_APB1ENR1_I3C2EN_Pos                 (25U)
+#define RCC_APB1ENR1_I3C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C2EN_Pos)    /*!< 0x02000000 */
+#define RCC_APB1ENR1_I3C2EN                     RCC_APB1ENR1_I3C2EN_Msk              /*!< I3C2 enable */
+#define RCC_APB1ENR1_UART7EN_Pos                (30U)
+#define RCC_APB1ENR1_UART7EN_Msk                (0x1UL << RCC_APB1ENR1_UART7EN_Pos)   /*!< 0x40000000 */
+#define RCC_APB1ENR1_UART7EN                    RCC_APB1ENR1_UART7EN_Msk             /*!< UART7 enable */
+#define RCC_APB1ENR1_UART8EN_Pos                (31U)
+#define RCC_APB1ENR1_UART8EN_Msk                (0x1UL << RCC_APB1ENR1_UART8EN_Pos)   /*!< 0x80000000 */
+#define RCC_APB1ENR1_UART8EN                    RCC_APB1ENR1_UART8EN_Msk             /*!< UART8 enable */
+
+/*****************  Bit definition for RCC_APB1ENR2 register  *****************/
+#define RCC_APB1ENR2_MDIOSEN_Pos                (5U)
+#define RCC_APB1ENR2_MDIOSEN_Msk                (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos)   /*!< 0x00000020 */
+#define RCC_APB1ENR2_MDIOSEN                    RCC_APB1ENR2_MDIOSEN_Msk             /*!< MDIOS enable */
+#define RCC_APB1ENR2_FDCANEN_Pos                (8U)
+#define RCC_APB1ENR2_FDCANEN_Msk                (0x1UL << RCC_APB1ENR2_FDCANEN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR2_FDCANEN                    RCC_APB1ENR2_FDCANEN_Msk             /*!< FDCAN enable */
+#define RCC_APB1ENR2_UCPD1EN_Pos                (18U)
+#define RCC_APB1ENR2_UCPD1EN_Msk                (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB1ENR2_UCPD1EN                    RCC_APB1ENR2_UCPD1EN_Msk             /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                  (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                  (0x1UL << RCC_APB2ENR_TIM1EN_Pos)     /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                      RCC_APB2ENR_TIM1EN_Msk               /*!< TIM1 enable */
+#define RCC_APB2ENR_TIM8EN_Pos                  (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                  (0x1UL << RCC_APB2ENR_TIM8EN_Pos)     /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                      RCC_APB2ENR_TIM8EN_Msk               /*!< TIM8 enable */
+#define RCC_APB2ENR_USART1EN_Pos                (4U)
+#define RCC_APB2ENR_USART1EN_Msk                (0x1UL << RCC_APB2ENR_USART1EN_Pos)   /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                    RCC_APB2ENR_USART1EN_Msk             /*!< USART1 enable */
+#define RCC_APB2ENR_USART6EN_Pos                (5U)
+#define RCC_APB2ENR_USART6EN_Msk                (0x1UL << RCC_APB2ENR_USART6EN_Pos)   /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                    RCC_APB2ENR_USART6EN_Msk             /*!< USART6 enable */
+#define RCC_APB2ENR_UART9EN_Pos                 (6U)
+#define RCC_APB2ENR_UART9EN_Msk                 (0x1UL << RCC_APB2ENR_UART9EN_Pos)    /*!< 0x00000040 */
+#define RCC_APB2ENR_UART9EN                     RCC_APB2ENR_UART9EN_Msk              /*!< UART9 enable */
+#define RCC_APB2ENR_USART10EN_Pos               (7U)
+#define RCC_APB2ENR_USART10EN_Msk               (0x1UL << RCC_APB2ENR_USART10EN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk            /*!< USART10 enable */
+#define RCC_APB2ENR_SPI1EN_Pos                  (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                  (0x1UL << RCC_APB2ENR_SPI1EN_Pos)     /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                      RCC_APB2ENR_SPI1EN_Msk               /*!< SPI1 enable */
+#define RCC_APB2ENR_SPI4EN_Pos                  (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                  (0x1UL << RCC_APB2ENR_SPI4EN_Pos)     /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                      RCC_APB2ENR_SPI4EN_Msk               /*!< SPI4 enable */
+#define RCC_APB2ENR_TIM18EN_Pos                 (15U)
+#define RCC_APB2ENR_TIM18EN_Msk                 (0x1UL << RCC_APB2ENR_TIM18EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB2ENR_TIM18EN                     RCC_APB2ENR_TIM18EN_Msk              /*!< TIM18 enable */
+#define RCC_APB2ENR_TIM15EN_Pos                 (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                 (0x1UL << RCC_APB2ENR_TIM15EN_Pos)    /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                     RCC_APB2ENR_TIM15EN_Msk              /*!< TIM15 enable */
+#define RCC_APB2ENR_TIM16EN_Pos                 (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                 (0x1UL << RCC_APB2ENR_TIM16EN_Pos)    /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                     RCC_APB2ENR_TIM16EN_Msk              /*!< TIM16 enable */
+#define RCC_APB2ENR_TIM17EN_Pos                 (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                 (0x1UL << RCC_APB2ENR_TIM17EN_Pos)    /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                     RCC_APB2ENR_TIM17EN_Msk              /*!< TIM17 enable */
+#define RCC_APB2ENR_TIM9EN_Pos                  (19U)
+#define RCC_APB2ENR_TIM9EN_Msk                  (0x1UL << RCC_APB2ENR_TIM9EN_Pos)     /*!< 0x00080000 */
+#define RCC_APB2ENR_TIM9EN                      RCC_APB2ENR_TIM9EN_Msk               /*!< TIM9 enable */
+#define RCC_APB2ENR_SPI5EN_Pos                  (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                  (0x1UL << RCC_APB2ENR_SPI5EN_Pos)     /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                      RCC_APB2ENR_SPI5EN_Msk               /*!< SPI5 enable */
+#define RCC_APB2ENR_SAI1EN_Pos                  (21U)
+#define RCC_APB2ENR_SAI1EN_Msk                  (0x1UL << RCC_APB2ENR_SAI1EN_Pos)     /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                      RCC_APB2ENR_SAI1EN_Msk               /*!< SAI1 enable */
+#define RCC_APB2ENR_SAI2EN_Pos                  (22U)
+#define RCC_APB2ENR_SAI2EN_Msk                  (0x1UL << RCC_APB2ENR_SAI2EN_Pos)     /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                      RCC_APB2ENR_SAI2EN_Msk               /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_DFTEN_Pos                   (2U)
+#define RCC_APB3ENR_DFTEN_Msk                   (0x1UL << RCC_APB3ENR_DFTEN_Pos)      /*!< 0x00000004 */
+#define RCC_APB3ENR_DFTEN                       RCC_APB3ENR_DFTEN_Msk                /*!< DFT enable */
+
+/*****************  Bit definition for RCC_APB4ENR1 register  *****************/
+#define RCC_APB4ENR1_HDPEN_Pos                  (2U)
+#define RCC_APB4ENR1_HDPEN_Msk                  (0x1UL << RCC_APB4ENR1_HDPEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR1_HDPEN                      RCC_APB4ENR1_HDPEN_Msk               /*!< HDP enable */
+#define RCC_APB4ENR1_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR1_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR1_LPUART1EN                  RCC_APB4ENR1_LPUART1EN_Msk           /*!< LPUART1 enable */
+#define RCC_APB4ENR1_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR1_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR1_SPI6EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB4ENR1_SPI6EN                     RCC_APB4ENR1_SPI6EN_Msk              /*!< SPI6 enable */
+#define RCC_APB4ENR1_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR1_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR1_I2C4EN_Pos)    /*!< 0x00000080 */
+#define RCC_APB4ENR1_I2C4EN                     RCC_APB4ENR1_I2C4EN_Msk              /*!< I2C4 enable */
+#define RCC_APB4ENR1_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR1_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4ENR1_LPTIM2EN                   RCC_APB4ENR1_LPTIM2EN_Msk            /*!< LPTIM2 enable */
+#define RCC_APB4ENR1_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR1_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4ENR1_LPTIM3EN                   RCC_APB4ENR1_LPTIM3EN_Msk            /*!< LPTIM3 enable */
+#define RCC_APB4ENR1_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR1_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4ENR1_LPTIM4EN                   RCC_APB4ENR1_LPTIM4EN_Msk            /*!< LPTIM4 enable */
+#define RCC_APB4ENR1_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR1_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4ENR1_LPTIM5EN                   RCC_APB4ENR1_LPTIM5EN_Msk            /*!< LPTIM5 enable */
+#define RCC_APB4ENR1_VREFBUFEN_Pos              (15U)
+#define RCC_APB4ENR1_VREFBUFEN_Msk              (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR1_VREFBUFEN                  RCC_APB4ENR1_VREFBUFEN_Msk           /*!< VREFBUF enable */
+#define RCC_APB4ENR1_RTCEN_Pos                  (16U)
+#define RCC_APB4ENR1_RTCEN_Msk                  (0x1UL << RCC_APB4ENR1_RTCEN_Pos)     /*!< 0x00010000 */
+#define RCC_APB4ENR1_RTCEN                      RCC_APB4ENR1_RTCEN_Msk               /*!< RTC enable */
+#define RCC_APB4ENR1_RTCAPBEN_Pos               (17U)
+#define RCC_APB4ENR1_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4ENR1_RTCAPBEN                   RCC_APB4ENR1_RTCAPBEN_Msk            /*!< RTCAPB enable */
+
+/*****************  Bit definition for RCC_APB4ENR2 register  *****************/
+#define RCC_APB4ENR2_SYSCFGEN_Pos               (0U)
+#define RCC_APB4ENR2_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4ENR2_SYSCFGEN                   RCC_APB4ENR2_SYSCFGEN_Msk            /*!< SYSCFG enable */
+#define RCC_APB4ENR2_BSECEN_Pos                 (1U)
+#define RCC_APB4ENR2_BSECEN_Msk                 (0x1UL << RCC_APB4ENR2_BSECEN_Pos)    /*!< 0x00000002 */
+#define RCC_APB4ENR2_BSECEN                     RCC_APB4ENR2_BSECEN_Msk              /*!< BSEC enable */
+#define RCC_APB4ENR2_DTSEN_Pos                  (2U)
+#define RCC_APB4ENR2_DTSEN_Msk                  (0x1UL << RCC_APB4ENR2_DTSEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR2_DTSEN                      RCC_APB4ENR2_DTSEN_Msk               /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENR register  ******************/
+#define RCC_APB5ENR_LTDCEN_Pos                  (1U)
+#define RCC_APB5ENR_LTDCEN_Msk                  (0x1UL << RCC_APB5ENR_LTDCEN_Pos)     /*!< 0x00000002 */
+#define RCC_APB5ENR_LTDCEN                      RCC_APB5ENR_LTDCEN_Msk               /*!< LTDC enable */
+#define RCC_APB5ENR_DCMIPPEN_Pos                (2U)
+#define RCC_APB5ENR_DCMIPPEN_Msk                (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos)   /*!< 0x00000004 */
+#define RCC_APB5ENR_DCMIPPEN                    RCC_APB5ENR_DCMIPPEN_Msk             /*!< DCMIPP enable */
+#define RCC_APB5ENR_GFXTIMEN_Pos                (4U)
+#define RCC_APB5ENR_GFXTIMEN_Msk                (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos)   /*!< 0x00000010 */
+#define RCC_APB5ENR_GFXTIMEN                    RCC_APB5ENR_GFXTIMEN_Msk             /*!< GFXTIM enable */
+#define RCC_APB5ENR_VENCEN_Pos                  (5U)
+#define RCC_APB5ENR_VENCEN_Msk                  (0x1UL << RCC_APB5ENR_VENCEN_Pos)     /*!< 0x00000020 */
+#define RCC_APB5ENR_VENCEN                      RCC_APB5ENR_VENCEN_Msk               /*!< VENC enable */
+#define RCC_APB5ENR_CSIEN_Pos                   (6U)
+#define RCC_APB5ENR_CSIEN_Msk                   (0x1UL << RCC_APB5ENR_CSIEN_Pos)      /*!< 0x00000040 */
+#define RCC_APB5ENR_CSIEN                       RCC_APB5ENR_CSIEN_Msk                /*!< CSI enable */
+
+/*****************  Bit definition for RCC_BUSLPENR register  *****************/
+#define RCC_BUSLPENR_ACLKNLPEN_Pos              (0U)
+#define RCC_BUSLPENR_ACLKNLPEN_Msk              (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENR_ACLKNLPEN                  RCC_BUSLPENR_ACLKNLPEN_Msk           /*!< ACLKN enable  */
+#define RCC_BUSLPENR_ACLKNCLPEN_Pos             (1U)
+#define RCC_BUSLPENR_ACLKNCLPEN_Msk             (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */
+#define RCC_BUSLPENR_ACLKNCLPEN                 RCC_BUSLPENR_ACLKNCLPEN_Msk          /*!< ACLKNC enable */
+
+/****************  Bit definition for RCC_MISCLPENR register  *****************/
+#define RCC_MISCLPENR_DBGLPEN_Pos               (0U)
+#define RCC_MISCLPENR_DBGLPEN_Msk               (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MISCLPENR_DBGLPEN                   RCC_MISCLPENR_DBGLPEN_Msk            /*!< DBG enable  */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos       (3U)
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk       (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos)      /*!< 0x00000008 */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN           RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk    /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENR_PERLPEN_Pos               (6U)
+#define RCC_MISCLPENR_PERLPEN_Msk               (0x1UL << RCC_MISCLPENR_PERLPEN_Pos)  /*!< 0x00000040 */
+#define RCC_MISCLPENR_PERLPEN                   RCC_MISCLPENR_PERLPEN_Msk            /*!< PER enable  */
+
+/*****************  Bit definition for RCC_MEMLPENR register  *****************/
+#define RCC_MEMLPENR_AXISRAM3LPEN_Pos           (0U)
+#define RCC_MEMLPENR_AXISRAM3LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMLPENR_AXISRAM3LPEN               RCC_MEMLPENR_AXISRAM3LPEN_Msk        /*!< AXISRAM3 enable */
+#define RCC_MEMLPENR_AXISRAM4LPEN_Pos           (1U)
+#define RCC_MEMLPENR_AXISRAM4LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMLPENR_AXISRAM4LPEN               RCC_MEMLPENR_AXISRAM4LPEN_Msk        /*!< AXISRAM4 enable */
+#define RCC_MEMLPENR_AXISRAM5LPEN_Pos           (2U)
+#define RCC_MEMLPENR_AXISRAM5LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMLPENR_AXISRAM5LPEN               RCC_MEMLPENR_AXISRAM5LPEN_Msk        /*!< AXISRAM5 enable */
+#define RCC_MEMLPENR_AXISRAM6LPEN_Pos           (3U)
+#define RCC_MEMLPENR_AXISRAM6LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMLPENR_AXISRAM6LPEN               RCC_MEMLPENR_AXISRAM6LPEN_Msk        /*!< AXISRAM6 enable */
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos           (4U)
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMLPENR_AHBSRAM1LPEN               RCC_MEMLPENR_AHBSRAM1LPEN_Msk        /*!< AHBSRAM1 enable */
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos           (5U)
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMLPENR_AHBSRAM2LPEN               RCC_MEMLPENR_AHBSRAM2LPEN_Msk        /*!< AHBSRAM2 enable */
+#define RCC_MEMLPENR_BKPSRAMLPEN_Pos            (6U)
+#define RCC_MEMLPENR_BKPSRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MEMLPENR_BKPSRAMLPEN                RCC_MEMLPENR_BKPSRAMLPEN_Msk         /*!< BKPSRAM enable */
+#define RCC_MEMLPENR_AXISRAM1LPEN_Pos           (7U)
+#define RCC_MEMLPENR_AXISRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMLPENR_AXISRAM1LPEN               RCC_MEMLPENR_AXISRAM1LPEN_Msk        /*!< AXISRAM1 enable */
+#define RCC_MEMLPENR_AXISRAM2LPEN_Pos           (8U)
+#define RCC_MEMLPENR_AXISRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMLPENR_AXISRAM2LPEN               RCC_MEMLPENR_AXISRAM2LPEN_Msk        /*!< AXISRAM2 enable */
+#define RCC_MEMLPENR_FLEXRAMLPEN_Pos            (9U)
+#define RCC_MEMLPENR_FLEXRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MEMLPENR_FLEXRAMLPEN                RCC_MEMLPENR_FLEXRAMLPEN_Msk         /*!< FLEXRAM enable */
+#define RCC_MEMLPENR_VENCRAMLPEN_Pos            (11U)
+#define RCC_MEMLPENR_VENCRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MEMLPENR_VENCRAMLPEN                RCC_MEMLPENR_VENCRAMLPEN_Msk         /*!< VENCRAM enable */
+#define RCC_MEMLPENR_BOOTROMLPEN_Pos            (12U)
+#define RCC_MEMLPENR_BOOTROMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MEMLPENR_BOOTROMLPEN                RCC_MEMLPENR_BOOTROMLPEN_Msk         /*!< Boot ROM enable */
+
+/****************  Bit definition for RCC_AHB1LPENR register  *****************/
+#define RCC_AHB1LPENR_GPDMA1LPEN_Pos            (4U)
+#define RCC_AHB1LPENR_GPDMA1LPEN_Msk            (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPDMA1LPEN                RCC_AHB1LPENR_GPDMA1LPEN_Msk         /*!< GPDMA1 enable */
+#define RCC_AHB1LPENR_ADC12LPEN_Pos             (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk             (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                 RCC_AHB1LPENR_ADC12LPEN_Msk          /*!< ADC12 enable */
+
+/****************  Bit definition for RCC_AHB2LPENR register  *****************/
+#define RCC_AHB2LPENR_RAMCFGLPEN_Pos            (12U)
+#define RCC_AHB2LPENR_RAMCFGLPEN_Msk            (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2LPENR_RAMCFGLPEN                RCC_AHB2LPENR_RAMCFGLPEN_Msk         /*!< RAMCFG enable */
+#define RCC_AHB2LPENR_MDF1LPEN_Pos              (16U)
+#define RCC_AHB2LPENR_MDF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENR_MDF1LPEN                  RCC_AHB2LPENR_MDF1LPEN_Msk           /*!< MDF1 enable */
+#define RCC_AHB2LPENR_ADF1LPEN_Pos              (17U)
+#define RCC_AHB2LPENR_ADF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENR_ADF1LPEN                  RCC_AHB2LPENR_ADF1LPEN_Msk           /*!< ADF1 enable */
+
+/****************  Bit definition for RCC_AHB3LPENR register  *****************/
+#define RCC_AHB3LPENR_RNGLPEN_Pos               (0U)
+#define RCC_AHB3LPENR_RNGLPEN_Msk               (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3LPENR_RNGLPEN                   RCC_AHB3LPENR_RNGLPEN_Msk            /*!< RNG enable */
+#define RCC_AHB3LPENR_HASHLPEN_Pos              (1U)
+#define RCC_AHB3LPENR_HASHLPEN_Msk              (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_HASHLPEN                  RCC_AHB3LPENR_HASHLPEN_Msk           /*!< HASH enable */
+#define RCC_AHB3LPENR_CRYPLPEN_Pos              (2U)
+#define RCC_AHB3LPENR_CRYPLPEN_Msk              (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB3LPENR_CRYPLPEN                  RCC_AHB3LPENR_CRYPLPEN_Msk           /*!< CRYP enable */
+#define RCC_AHB3LPENR_SAESLPEN_Pos              (4U)
+#define RCC_AHB3LPENR_SAESLPEN_Msk              (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB3LPENR_SAESLPEN                  RCC_AHB3LPENR_SAESLPEN_Msk           /*!< SAES enable */
+#define RCC_AHB3LPENR_PKALPEN_Pos               (8U)
+#define RCC_AHB3LPENR_PKALPEN_Msk               (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3LPENR_PKALPEN                   RCC_AHB3LPENR_PKALPEN_Msk            /*!< PKA enable */
+#define RCC_AHB3LPENR_RIFSCLPEN_Pos             (9U)
+#define RCC_AHB3LPENR_RIFSCLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */
+#define RCC_AHB3LPENR_RIFSCLPEN                 RCC_AHB3LPENR_RIFSCLPEN_Msk          /*!< RIFSC enable */
+#define RCC_AHB3LPENR_IACLPEN_Pos               (10U)
+#define RCC_AHB3LPENR_IACLPEN_Msk               (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3LPENR_IACLPEN                   RCC_AHB3LPENR_IACLPEN_Msk            /*!< IAC enable */
+#define RCC_AHB3LPENR_RISAFLPEN_Pos             (14U)
+#define RCC_AHB3LPENR_RISAFLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB3LPENR_RISAFLPEN                 RCC_AHB3LPENR_RISAFLPEN_Msk          /*!< RISAF enable */
+
+/****************  Bit definition for RCC_AHB4LPENR register  *****************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos             (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                 RCC_AHB4LPENR_GPIOALPEN_Msk          /*!< GPIO A enable */
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos             (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                 RCC_AHB4LPENR_GPIOBLPEN_Msk          /*!< GPIO B enable */
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos             (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                 RCC_AHB4LPENR_GPIOCLPEN_Msk          /*!< GPIO C enable */
+#define RCC_AHB4LPENR_GPIODLPEN_Pos             (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                 RCC_AHB4LPENR_GPIODLPEN_Msk          /*!< GPIO D enable */
+#define RCC_AHB4LPENR_GPIOELPEN_Pos             (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                 RCC_AHB4LPENR_GPIOELPEN_Msk          /*!< GPIO E enable */
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos             (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                 RCC_AHB4LPENR_GPIOFLPEN_Msk          /*!< GPIO F enable */
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos             (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                 RCC_AHB4LPENR_GPIOGLPEN_Msk          /*!< GPIO G enable */
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos             (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                 RCC_AHB4LPENR_GPIOHLPEN_Msk          /*!< GPIO H enable */
+#define RCC_AHB4LPENR_GPIONLPEN_Pos             (13U)
+#define RCC_AHB4LPENR_GPIONLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB4LPENR_GPIONLPEN                 RCC_AHB4LPENR_GPIONLPEN_Msk          /*!< GPIO N enable */
+#define RCC_AHB4LPENR_GPIOOLPEN_Pos             (14U)
+#define RCC_AHB4LPENR_GPIOOLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB4LPENR_GPIOOLPEN                 RCC_AHB4LPENR_GPIOOLPEN_Msk          /*!< GPIO O enable */
+#define RCC_AHB4LPENR_GPIOPLPEN_Pos             (15U)
+#define RCC_AHB4LPENR_GPIOPLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */
+#define RCC_AHB4LPENR_GPIOPLPEN                 RCC_AHB4LPENR_GPIOPLPEN_Msk          /*!< GPIO P enable */
+#define RCC_AHB4LPENR_GPIOQLPEN_Pos             (16U)
+#define RCC_AHB4LPENR_GPIOQLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */
+#define RCC_AHB4LPENR_GPIOQLPEN                 RCC_AHB4LPENR_GPIOQLPEN_Msk          /*!< GPIO Q enable */
+#define RCC_AHB4LPENR_PWRLPEN_Pos               (18U)
+#define RCC_AHB4LPENR_PWRLPEN_Msk               (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4LPENR_PWRLPEN                   RCC_AHB4LPENR_PWRLPEN_Msk            /*!< PWR enable */
+#define RCC_AHB4LPENR_CRCLPEN_Pos               (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk               (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                   RCC_AHB4LPENR_CRCLPEN_Msk            /*!< CRC enable */
+
+/****************  Bit definition for RCC_AHB5LPENR register  *****************/
+#define RCC_AHB5LPENR_HPDMA1LPEN_Pos            (0U)
+#define RCC_AHB5LPENR_HPDMA1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB5LPENR_HPDMA1LPEN                RCC_AHB5LPENR_HPDMA1LPEN_Msk         /*!< HPDMA1 enable */
+#define RCC_AHB5LPENR_DMA2DLPEN_Pos             (1U)
+#define RCC_AHB5LPENR_DMA2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB5LPENR_DMA2DLPEN                 RCC_AHB5LPENR_DMA2DLPEN_Msk          /*!< DMA2D enable */
+#define RCC_AHB5LPENR_JPEGLPEN_Pos              (3U)
+#define RCC_AHB5LPENR_JPEGLPEN_Msk              (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENR_JPEGLPEN                  RCC_AHB5LPENR_JPEGLPEN_Msk           /*!< JPEG enable */
+#define RCC_AHB5LPENR_FMCLPEN_Pos               (4U)
+#define RCC_AHB5LPENR_FMCLPEN_Msk               (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5LPENR_FMCLPEN                   RCC_AHB5LPENR_FMCLPEN_Msk            /*!< FMC enable */
+#define RCC_AHB5LPENR_XSPI1LPEN_Pos             (5U)
+#define RCC_AHB5LPENR_XSPI1LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB5LPENR_XSPI1LPEN                 RCC_AHB5LPENR_XSPI1LPEN_Msk          /*!< XSPI1 enable */
+#define RCC_AHB5LPENR_PSSILPEN_Pos              (6U)
+#define RCC_AHB5LPENR_PSSILPEN_Msk              (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENR_PSSILPEN                  RCC_AHB5LPENR_PSSILPEN_Msk           /*!< PSSI enable */
+#define RCC_AHB5LPENR_SDMMC2LPEN_Pos            (7U)
+#define RCC_AHB5LPENR_SDMMC2LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB5LPENR_SDMMC2LPEN                RCC_AHB5LPENR_SDMMC2LPEN_Msk         /*!< SDMMC2 enable */
+#define RCC_AHB5LPENR_SDMMC1LPEN_Pos            (8U)
+#define RCC_AHB5LPENR_SDMMC1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB5LPENR_SDMMC1LPEN                RCC_AHB5LPENR_SDMMC1LPEN_Msk         /*!< SDMMC1 enable */
+#define RCC_AHB5LPENR_XSPI2LPEN_Pos             (12U)
+#define RCC_AHB5LPENR_XSPI2LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */
+#define RCC_AHB5LPENR_XSPI2LPEN                 RCC_AHB5LPENR_XSPI2LPEN_Msk          /*!< XSPI2 enable */
+#define RCC_AHB5LPENR_XSPIMLPEN_Pos             (13U)
+#define RCC_AHB5LPENR_XSPIMLPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB5LPENR_XSPIMLPEN                 RCC_AHB5LPENR_XSPIMLPEN_Msk          /*!< XSPIM enable */
+#define RCC_AHB5LPENR_MCE1LPEN_Pos              (14U)
+#define RCC_AHB5LPENR_MCE1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB5LPENR_MCE1LPEN                  RCC_AHB5LPENR_MCE1LPEN_Msk           /*!< MCE1 enable */
+#define RCC_AHB5LPENR_MCE2LPEN_Pos              (15U)
+#define RCC_AHB5LPENR_MCE2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB5LPENR_MCE2LPEN                  RCC_AHB5LPENR_MCE2LPEN_Msk           /*!< MCE2 enable */
+#define RCC_AHB5LPENR_MCE3LPEN_Pos              (16U)
+#define RCC_AHB5LPENR_MCE3LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB5LPENR_MCE3LPEN                  RCC_AHB5LPENR_MCE3LPEN_Msk           /*!< MCE3 enable */
+#define RCC_AHB5LPENR_XSPI3LPEN_Pos             (17U)
+#define RCC_AHB5LPENR_XSPI3LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */
+#define RCC_AHB5LPENR_XSPI3LPEN                 RCC_AHB5LPENR_XSPI3LPEN_Msk          /*!< XSPI3 enable */
+#define RCC_AHB5LPENR_MCE4LPEN_Pos              (18U)
+#define RCC_AHB5LPENR_MCE4LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB5LPENR_MCE4LPEN                  RCC_AHB5LPENR_MCE4LPEN_Msk           /*!< MCE4 enable */
+#define RCC_AHB5LPENR_GFXMMULPEN_Pos            (19U)
+#define RCC_AHB5LPENR_GFXMMULPEN_Msk            (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB5LPENR_GFXMMULPEN                RCC_AHB5LPENR_GFXMMULPEN_Msk         /*!< GFXMMU enable */
+#define RCC_AHB5LPENR_GPU2DLPEN_Pos             (20U)
+#define RCC_AHB5LPENR_GPU2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */
+#define RCC_AHB5LPENR_GPU2DLPEN                 RCC_AHB5LPENR_GPU2DLPEN_Msk          /*!< GPU2D enable */
+#define RCC_AHB5LPENR_ETH1MACLPEN_Pos           (22U)
+#define RCC_AHB5LPENR_ETH1MACLPEN_Msk           (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5LPENR_ETH1MACLPEN               RCC_AHB5LPENR_ETH1MACLPEN_Msk        /*!< ETH1MAC enable */
+#define RCC_AHB5LPENR_ETH1TXLPEN_Pos            (23U)
+#define RCC_AHB5LPENR_ETH1TXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB5LPENR_ETH1TXLPEN                RCC_AHB5LPENR_ETH1TXLPEN_Msk         /*!< ETH1TX enable */
+#define RCC_AHB5LPENR_ETH1RXLPEN_Pos            (24U)
+#define RCC_AHB5LPENR_ETH1RXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB5LPENR_ETH1RXLPEN                RCC_AHB5LPENR_ETH1RXLPEN_Msk         /*!< ETH1RX enable */
+#define RCC_AHB5LPENR_ETH1LPEN_Pos              (25U)
+#define RCC_AHB5LPENR_ETH1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENR_ETH1LPEN                  RCC_AHB5LPENR_ETH1LPEN_Msk           /*!< ETH1 enable */
+#define RCC_AHB5LPENR_OTG1LPEN_Pos              (26U)
+#define RCC_AHB5LPENR_OTG1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENR_OTG1LPEN                  RCC_AHB5LPENR_OTG1LPEN_Msk           /*!< OTG1 enable */
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos           (27U)
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5LPENR_OTGPHY1LPEN               RCC_AHB5LPENR_OTGPHY1LPEN_Msk        /*!< OTGPHY1 enable */
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos           (28U)
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5LPENR_OTGPHY2LPEN               RCC_AHB5LPENR_OTGPHY2LPEN_Msk        /*!< OTGPHY2 enable */
+#define RCC_AHB5LPENR_OTG2LPEN_Pos              (29U)
+#define RCC_AHB5LPENR_OTG2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENR_OTG2LPEN                  RCC_AHB5LPENR_OTG2LPEN_Msk           /*!< OTG2 enable */
+
+/****************  Bit definition for RCC_APB1LPENR1 register  ****************/
+#define RCC_APB1LPENR1_TIM2LPEN_Pos             (0U)
+#define RCC_APB1LPENR1_TIM2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */
+#define RCC_APB1LPENR1_TIM2LPEN                 RCC_APB1LPENR1_TIM2LPEN_Msk          /*!< TIM2 enable */
+#define RCC_APB1LPENR1_TIM3LPEN_Pos             (1U)
+#define RCC_APB1LPENR1_TIM3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB1LPENR1_TIM3LPEN                 RCC_APB1LPENR1_TIM3LPEN_Msk          /*!< TIM3 enable */
+#define RCC_APB1LPENR1_TIM4LPEN_Pos             (2U)
+#define RCC_APB1LPENR1_TIM4LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */
+#define RCC_APB1LPENR1_TIM4LPEN                 RCC_APB1LPENR1_TIM4LPEN_Msk          /*!< TIM4 enable */
+#define RCC_APB1LPENR1_TIM5LPEN_Pos             (3U)
+#define RCC_APB1LPENR1_TIM5LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */
+#define RCC_APB1LPENR1_TIM5LPEN                 RCC_APB1LPENR1_TIM5LPEN_Msk          /*!< TIM5 enable */
+#define RCC_APB1LPENR1_TIM6LPEN_Pos             (4U)
+#define RCC_APB1LPENR1_TIM6LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */
+#define RCC_APB1LPENR1_TIM6LPEN                 RCC_APB1LPENR1_TIM6LPEN_Msk          /*!< TIM6 enable */
+#define RCC_APB1LPENR1_TIM7LPEN_Pos             (5U)
+#define RCC_APB1LPENR1_TIM7LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB1LPENR1_TIM7LPEN                 RCC_APB1LPENR1_TIM7LPEN_Msk          /*!< TIM7 enable */
+#define RCC_APB1LPENR1_TIM12LPEN_Pos            (6U)
+#define RCC_APB1LPENR1_TIM12LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR1_TIM12LPEN                RCC_APB1LPENR1_TIM12LPEN_Msk         /*!< TIM12 enable */
+#define RCC_APB1LPENR1_TIM13LPEN_Pos            (7U)
+#define RCC_APB1LPENR1_TIM13LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR1_TIM13LPEN                RCC_APB1LPENR1_TIM13LPEN_Msk         /*!< TIM13 enable */
+#define RCC_APB1LPENR1_TIM14LPEN_Pos            (8U)
+#define RCC_APB1LPENR1_TIM14LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR1_TIM14LPEN                RCC_APB1LPENR1_TIM14LPEN_Msk         /*!< TIM14 enable */
+#define RCC_APB1LPENR1_LPTIM1LPEN_Pos           (9U)
+#define RCC_APB1LPENR1_LPTIM1LPEN_Msk           (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1LPENR1_LPTIM1LPEN               RCC_APB1LPENR1_LPTIM1LPEN_Msk        /*!< LPTIM1 enable */
+#define RCC_APB1LPENR1_WWDGLPEN_Pos             (11U)
+#define RCC_APB1LPENR1_WWDGLPEN_Msk             (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */
+#define RCC_APB1LPENR1_WWDGLPEN                 RCC_APB1LPENR1_WWDGLPEN_Msk          /*!< WWDG enable */
+#define RCC_APB1LPENR1_TIM10LPEN_Pos            (12U)
+#define RCC_APB1LPENR1_TIM10LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB1LPENR1_TIM10LPEN                RCC_APB1LPENR1_TIM10LPEN_Msk         /*!< TIM10 enable */
+#define RCC_APB1LPENR1_TIM11LPEN_Pos            (13U)
+#define RCC_APB1LPENR1_TIM11LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB1LPENR1_TIM11LPEN                RCC_APB1LPENR1_TIM11LPEN_Msk         /*!< TIM11 enable */
+#define RCC_APB1LPENR1_SPI2LPEN_Pos             (14U)
+#define RCC_APB1LPENR1_SPI2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */
+#define RCC_APB1LPENR1_SPI2LPEN                 RCC_APB1LPENR1_SPI2LPEN_Msk          /*!< SPI2 enable */
+#define RCC_APB1LPENR1_SPI3LPEN_Pos             (15U)
+#define RCC_APB1LPENR1_SPI3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB1LPENR1_SPI3LPEN                 RCC_APB1LPENR1_SPI3LPEN_Msk          /*!< SPI3 enable */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos         (16U)
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk         (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos)    /*!< 0x00010000 */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN             RCC_APB1LPENR1_SPDIFRX1LPEN_Msk      /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENR1_USART2LPEN_Pos           (17U)
+#define RCC_APB1LPENR1_USART2LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1LPENR1_USART2LPEN               RCC_APB1LPENR1_USART2LPEN_Msk        /*!< USART2 enable */
+#define RCC_APB1LPENR1_USART3LPEN_Pos           (18U)
+#define RCC_APB1LPENR1_USART3LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1LPENR1_USART3LPEN               RCC_APB1LPENR1_USART3LPEN_Msk        /*!< USART3 enable */
+#define RCC_APB1LPENR1_UART4LPEN_Pos            (19U)
+#define RCC_APB1LPENR1_UART4LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR1_UART4LPEN                RCC_APB1LPENR1_UART4LPEN_Msk         /*!< UART4 enable */
+#define RCC_APB1LPENR1_UART5LPEN_Pos            (20U)
+#define RCC_APB1LPENR1_UART5LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR1_UART5LPEN                RCC_APB1LPENR1_UART5LPEN_Msk         /*!< UART5 enable */
+#define RCC_APB1LPENR1_I2C1LPEN_Pos             (21U)
+#define RCC_APB1LPENR1_I2C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */
+#define RCC_APB1LPENR1_I2C1LPEN                 RCC_APB1LPENR1_I2C1LPEN_Msk          /*!< I2C1 enable */
+#define RCC_APB1LPENR1_I2C2LPEN_Pos             (22U)
+#define RCC_APB1LPENR1_I2C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */
+#define RCC_APB1LPENR1_I2C2LPEN                 RCC_APB1LPENR1_I2C2LPEN_Msk          /*!< I2C2 enable */
+#define RCC_APB1LPENR1_I2C3LPEN_Pos             (23U)
+#define RCC_APB1LPENR1_I2C3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */
+#define RCC_APB1LPENR1_I2C3LPEN                 RCC_APB1LPENR1_I2C3LPEN_Msk          /*!< I2C3 enable */
+#define RCC_APB1LPENR1_I3C1LPEN_Pos             (24U)
+#define RCC_APB1LPENR1_I3C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */
+#define RCC_APB1LPENR1_I3C1LPEN                 RCC_APB1LPENR1_I3C1LPEN_Msk          /*!< I3C1 enable */
+#define RCC_APB1LPENR1_I3C2LPEN_Pos             (25U)
+#define RCC_APB1LPENR1_I3C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */
+#define RCC_APB1LPENR1_I3C2LPEN                 RCC_APB1LPENR1_I3C2LPEN_Msk          /*!< I3C2 enable */
+#define RCC_APB1LPENR1_UART7LPEN_Pos            (30U)
+#define RCC_APB1LPENR1_UART7LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR1_UART7LPEN                RCC_APB1LPENR1_UART7LPEN_Msk         /*!< UART7 enable */
+#define RCC_APB1LPENR1_UART8LPEN_Pos            (31U)
+#define RCC_APB1LPENR1_UART8LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR1_UART8LPEN                RCC_APB1LPENR1_UART8LPEN_Msk         /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1LPENR2 register  ****************/
+#define RCC_APB1LPENR2_MDIOSLPEN_Pos            (5U)
+#define RCC_APB1LPENR2_MDIOSLPEN_Msk            (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR2_MDIOSLPEN                RCC_APB1LPENR2_MDIOSLPEN_Msk         /*!< MDIOS enable in Sleep mode */
+#define RCC_APB1LPENR2_FDCANLPEN_Pos            (8U)
+#define RCC_APB1LPENR2_FDCANLPEN_Msk            (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR2_FDCANLPEN                RCC_APB1LPENR2_FDCANLPEN_Msk         /*!< FDCAN enablein Sleep mode */
+#define RCC_APB1LPENR2_UCPD1LPEN_Pos            (18U)
+#define RCC_APB1LPENR2_UCPD1LPEN_Msk            (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR2_UCPD1LPEN                RCC_APB1LPENR2_UCPD1LPEN_Msk         /*!< UCPD1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_APB2LPENR register  *****************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos              (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                  RCC_APB2LPENR_TIM1LPEN_Msk           /*!< TIM1 enable */
+#define RCC_APB2LPENR_TIM8LPEN_Pos              (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                  RCC_APB2LPENR_TIM8LPEN_Msk           /*!< TIM8 enable */
+#define RCC_APB2LPENR_USART1LPEN_Pos            (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN                RCC_APB2LPENR_USART1LPEN_Msk         /*!< USART1 enable */
+#define RCC_APB2LPENR_USART6LPEN_Pos            (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN                RCC_APB2LPENR_USART6LPEN_Msk         /*!< USART6 enable */
+#define RCC_APB2LPENR_UART9LPEN_Pos             (6U)
+#define RCC_APB2LPENR_UART9LPEN_Msk             (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */
+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk          /*!< UART9 enable */
+#define RCC_APB2LPENR_USART10LPEN_Pos           (7U)
+#define RCC_APB2LPENR_USART10LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk        /*!< USART10 enable */
+#define RCC_APB2LPENR_SPI1LPEN_Pos              (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                  RCC_APB2LPENR_SPI1LPEN_Msk           /*!< SPI1 enable */
+#define RCC_APB2LPENR_SPI4LPEN_Pos              (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                  RCC_APB2LPENR_SPI4LPEN_Msk           /*!< SPI4 enable */
+#define RCC_APB2LPENR_TIM18LPEN_Pos             (15U)
+#define RCC_APB2LPENR_TIM18LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB2LPENR_TIM18LPEN                 RCC_APB2LPENR_TIM18LPEN_Msk          /*!< TIM18 enable */
+#define RCC_APB2LPENR_TIM15LPEN_Pos             (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                 RCC_APB2LPENR_TIM15LPEN_Msk          /*!< TIM15 enable */
+#define RCC_APB2LPENR_TIM16LPEN_Pos             (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                 RCC_APB2LPENR_TIM16LPEN_Msk          /*!< TIM16 enable */
+#define RCC_APB2LPENR_TIM17LPEN_Pos             (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                 RCC_APB2LPENR_TIM17LPEN_Msk          /*!< TIM17 enable */
+#define RCC_APB2LPENR_TIM9LPEN_Pos              (19U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENR_TIM9LPEN                  RCC_APB2LPENR_TIM9LPEN_Msk           /*!< TIM9 enable */
+#define RCC_APB2LPENR_SPI5LPEN_Pos              (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                  RCC_APB2LPENR_SPI5LPEN_Msk           /*!< SPI5 enable */
+#define RCC_APB2LPENR_SAI1LPEN_Pos              (21U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SAI1LPEN                  RCC_APB2LPENR_SAI1LPEN_Msk           /*!< SAI1 enable */
+#define RCC_APB2LPENR_SAI2LPEN_Pos              (22U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI2LPEN                  RCC_APB2LPENR_SAI2LPEN_Msk           /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENR register  *****************/
+#define RCC_APB3LPENR_DFTLPEN_Pos               (2U)
+#define RCC_APB3LPENR_DFTLPEN_Msk               (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos)  /*!< 0x00000004 */
+#define RCC_APB3LPENR_DFTLPEN                   RCC_APB3LPENR_DFTLPEN_Msk            /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4LPENR1 register  ****************/
+#define RCC_APB4LPENR1_HDPLPEN_Pos              (2U)
+#define RCC_APB4LPENR1_HDPLPEN_Msk              (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR1_HDPLPEN                  RCC_APB4LPENR1_HDPLPEN_Msk           /*!< HDP enable */
+#define RCC_APB4LPENR1_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR1_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos)   /*!< 0x00000008 */
+#define RCC_APB4LPENR1_LPUART1LPEN              RCC_APB4LPENR1_LPUART1LPEN_Msk       /*!< LPUART1 enable */
+#define RCC_APB4LPENR1_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR1_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB4LPENR1_SPI6LPEN                 RCC_APB4LPENR1_SPI6LPEN_Msk          /*!< SPI6 enable */
+#define RCC_APB4LPENR1_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR1_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */
+#define RCC_APB4LPENR1_I2C4LPEN                 RCC_APB4LPENR1_I2C4LPEN_Msk          /*!< I2C4 enable */
+#define RCC_APB4LPENR1_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR1_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4LPENR1_LPTIM2LPEN               RCC_APB4LPENR1_LPTIM2LPEN_Msk        /*!< LPTIM2 enable */
+#define RCC_APB4LPENR1_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR1_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4LPENR1_LPTIM3LPEN               RCC_APB4LPENR1_LPTIM3LPEN_Msk        /*!< LPTIM3 enable */
+#define RCC_APB4LPENR1_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR1_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4LPENR1_LPTIM4LPEN               RCC_APB4LPENR1_LPTIM4LPEN_Msk        /*!< LPTIM4 enable */
+#define RCC_APB4LPENR1_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR1_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4LPENR1_LPTIM5LPEN               RCC_APB4LPENR1_LPTIM5LPEN_Msk        /*!< LPTIM5 enable */
+#define RCC_APB4LPENR1_VREFBUFLPEN_Pos          (15U)
+#define RCC_APB4LPENR1_VREFBUFLPEN_Msk          (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos)   /*!< 0x00008000 */
+#define RCC_APB4LPENR1_VREFBUFLPEN              RCC_APB4LPENR1_VREFBUFLPEN_Msk       /*!< VREFBUF enable */
+#define RCC_APB4LPENR1_RTCLPEN_Pos              (16U)
+#define RCC_APB4LPENR1_RTCLPEN_Msk              (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR1_RTCLPEN                  RCC_APB4LPENR1_RTCLPEN_Msk           /*!< RTC enable */
+#define RCC_APB4LPENR1_RTCAPBLPEN_Pos           (17U)
+#define RCC_APB4LPENR1_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4LPENR1_RTCAPBLPEN               RCC_APB4LPENR1_RTCAPBLPEN_Msk        /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4LPENR2 register  ****************/
+#define RCC_APB4LPENR2_SYSCFGLPEN_Pos           (0U)
+#define RCC_APB4LPENR2_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4LPENR2_SYSCFGLPEN               RCC_APB4LPENR2_SYSCFGLPEN_Msk        /*!< SYSCFG enable */
+#define RCC_APB4LPENR2_BSECLPEN_Pos             (1U)
+#define RCC_APB4LPENR2_BSECLPEN_Msk             (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB4LPENR2_BSECLPEN                 RCC_APB4LPENR2_BSECLPEN_Msk          /*!< BSEC enable */
+#define RCC_APB4LPENR2_DTSLPEN_Pos              (2U)
+#define RCC_APB4LPENR2_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR2_DTSLPEN                  RCC_APB4LPENR2_DTSLPEN_Msk           /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENR register  *****************/
+#define RCC_APB5LPENR_LTDCLPEN_Pos              (1U)
+#define RCC_APB5LPENR_LTDCLPEN_Msk              (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENR_LTDCLPEN                  RCC_APB5LPENR_LTDCLPEN_Msk           /*!< LTDC enable */
+#define RCC_APB5LPENR_DCMIPPLPEN_Pos            (2U)
+#define RCC_APB5LPENR_DCMIPPLPEN_Msk            (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB5LPENR_DCMIPPLPEN                RCC_APB5LPENR_DCMIPPLPEN_Msk         /*!< DCMIPP enable */
+#define RCC_APB5LPENR_GFXTIMLPEN_Pos            (4U)
+#define RCC_APB5LPENR_GFXTIMLPEN_Msk            (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB5LPENR_GFXTIMLPEN                RCC_APB5LPENR_GFXTIMLPEN_Msk         /*!< GFXTIM enable */
+#define RCC_APB5LPENR_VENCLPEN_Pos              (5U)
+#define RCC_APB5LPENR_VENCLPEN_Msk              (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENR_VENCLPEN                  RCC_APB5LPENR_VENCLPEN_Msk           /*!< VENC enable */
+#define RCC_APB5LPENR_CSILPEN_Pos               (6U)
+#define RCC_APB5LPENR_CSILPEN_Msk               (0x1UL << RCC_APB5LPENR_CSILPEN_Pos)  /*!< 0x00000040 */
+#define RCC_APB5LPENR_CSILPEN                   RCC_APB5LPENR_CSILPEN_Msk            /*!< CSI enable */
+
+/*******************  Bit definition for RCC_RDCR register  *******************/
+#define RCC_RDCR_MRD_Pos                        (16U)
+#define RCC_RDCR_MRD_Msk                        (0x1FUL << RCC_RDCR_MRD_Pos)          /*!< 0x001F0000 */
+#define RCC_RDCR_MRD                            RCC_RDCR_MRD_Msk                     /*!< Minimum reset duration */
+
+/*****************  Bit definition for RCC_SECCFGR0 register  *****************/
+#define RCC_SECCFGR0_LSISEC_Pos                 (0U)
+#define RCC_SECCFGR0_LSISEC_Msk                 (0x1UL << RCC_SECCFGR0_LSISEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR0_LSISEC                     RCC_SECCFGR0_LSISEC_Msk              /*!< Secure protection of LSI oscillator configuration bits */
+#define RCC_SECCFGR0_LSESEC_Pos                 (1U)
+#define RCC_SECCFGR0_LSESEC_Msk                 (0x1UL << RCC_SECCFGR0_LSESEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR0_LSESEC                     RCC_SECCFGR0_LSESEC_Msk              /*!< Secure protection of LSE oscillator configuration bits */
+#define RCC_SECCFGR0_MSISEC_Pos                 (2U)
+#define RCC_SECCFGR0_MSISEC_Msk                 (0x1UL << RCC_SECCFGR0_MSISEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR0_MSISEC                     RCC_SECCFGR0_MSISEC_Msk              /*!< Secure protection of MSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSISEC_Pos                 (3U)
+#define RCC_SECCFGR0_HSISEC_Msk                 (0x1UL << RCC_SECCFGR0_HSISEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR0_HSISEC                     RCC_SECCFGR0_HSISEC_Msk              /*!< Secure protection of HSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSESEC_Pos                 (4U)
+#define RCC_SECCFGR0_HSESEC_Msk                 (0x1UL << RCC_SECCFGR0_HSESEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR0_HSESEC                     RCC_SECCFGR0_HSESEC_Msk              /*!< Secure protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR0 register  *****************/
+#define RCC_PRIVCFGR0_LSIPRIV_Pos               (0U)
+#define RCC_PRIVCFGR0_LSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR0_LSIPRIV                   RCC_PRIVCFGR0_LSIPRIV_Msk            /*!< Privileged protection of LSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_LSEPRIV_Pos               (1U)
+#define RCC_PRIVCFGR0_LSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR0_LSEPRIV                   RCC_PRIVCFGR0_LSEPRIV_Msk            /*!< Privileged protection of LSE oscillator configuration bits */
+#define RCC_PRIVCFGR0_MSIPRIV_Pos               (2U)
+#define RCC_PRIVCFGR0_MSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR0_MSIPRIV                   RCC_PRIVCFGR0_MSIPRIV_Msk            /*!< Privileged protection of MSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSIPRIV_Pos               (3U)
+#define RCC_PRIVCFGR0_HSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR0_HSIPRIV                   RCC_PRIVCFGR0_HSIPRIV_Msk            /*!< Privileged protection of HSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSEPRIV_Pos               (4U)
+#define RCC_PRIVCFGR0_HSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR0_HSEPRIV                   RCC_PRIVCFGR0_HSEPRIV_Msk            /*!< Privileged protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR0 register  *****************/
+#define RCC_LOCKCFGR0_LSILOCK_Pos               (0U)
+#define RCC_LOCKCFGR0_LSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR0_LSILOCK                   RCC_LOCKCFGR0_LSILOCK_Msk            /*!< Locked protection of LSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_LSELOCK_Pos               (1U)
+#define RCC_LOCKCFGR0_LSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR0_LSELOCK                   RCC_LOCKCFGR0_LSELOCK_Msk            /*!< Locked protection of LSE oscillator configuration bits */
+#define RCC_LOCKCFGR0_MSILOCK_Pos               (2U)
+#define RCC_LOCKCFGR0_MSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR0_MSILOCK                   RCC_LOCKCFGR0_MSILOCK_Msk            /*!< Locked protection of MSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSILOCK_Pos               (3U)
+#define RCC_LOCKCFGR0_HSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR0_HSILOCK                   RCC_LOCKCFGR0_HSILOCK_Msk            /*!< Locked protection of HSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSELOCK_Pos               (4U)
+#define RCC_LOCKCFGR0_HSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR0_HSELOCK                   RCC_LOCKCFGR0_HSELOCK_Msk            /*!< Locked protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR0 register  *****************/
+#define RCC_PUBCFGR0_LSIPUB_Pos                 (0U)
+#define RCC_PUBCFGR0_LSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR0_LSIPUB                     RCC_PUBCFGR0_LSIPUB_Msk              /*!< Public protection of LSI oscillator configuration bits */
+#define RCC_PUBCFGR0_LSEPUB_Pos                 (1U)
+#define RCC_PUBCFGR0_LSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR0_LSEPUB                     RCC_PUBCFGR0_LSEPUB_Msk              /*!< Public protection of LSE oscillator configuration bits */
+#define RCC_PUBCFGR0_MSIPUB_Pos                 (2U)
+#define RCC_PUBCFGR0_MSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR0_MSIPUB                     RCC_PUBCFGR0_MSIPUB_Msk              /*!< Public protection of MSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSIPUB_Pos                 (3U)
+#define RCC_PUBCFGR0_HSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR0_HSIPUB                     RCC_PUBCFGR0_HSIPUB_Msk              /*!< Public protection of HSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSEPUB_Pos                 (4U)
+#define RCC_PUBCFGR0_HSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR0_HSEPUB                     RCC_PUBCFGR0_HSEPUB_Msk              /*!< Public protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR1 register  *****************/
+#define RCC_SECCFGR1_PLL1SEC_Pos                (0U)
+#define RCC_SECCFGR1_PLL1SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos)   /*!< 0x00000001 */
+#define RCC_SECCFGR1_PLL1SEC                    RCC_SECCFGR1_PLL1SEC_Msk             /*!< Secure protection of PLL1 configuration bits */
+#define RCC_SECCFGR1_PLL2SEC_Pos                (1U)
+#define RCC_SECCFGR1_PLL2SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos)   /*!< 0x00000002 */
+#define RCC_SECCFGR1_PLL2SEC                    RCC_SECCFGR1_PLL2SEC_Msk             /*!< Secure protection of PLL2 configuration bits */
+#define RCC_SECCFGR1_PLL3SEC_Pos                (2U)
+#define RCC_SECCFGR1_PLL3SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR1_PLL3SEC                    RCC_SECCFGR1_PLL3SEC_Msk             /*!< Secure protection of PLL3 configuration bits */
+#define RCC_SECCFGR1_PLL4SEC_Pos                (3U)
+#define RCC_SECCFGR1_PLL4SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR1_PLL4SEC                    RCC_SECCFGR1_PLL4SEC_Msk             /*!< Secure protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR1 register  *****************/
+#define RCC_PRIVCFGR1_PLL1PRIV_Pos              (0U)
+#define RCC_PRIVCFGR1_PLL1PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGR1_PLL1PRIV                  RCC_PRIVCFGR1_PLL1PRIV_Msk           /*!< Privileged protection of PLL1 configuration bits */
+#define RCC_PRIVCFGR1_PLL2PRIV_Pos              (1U)
+#define RCC_PRIVCFGR1_PLL2PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR1_PLL2PRIV                  RCC_PRIVCFGR1_PLL2PRIV_Msk           /*!< Privileged protection of PLL2 configuration bits */
+#define RCC_PRIVCFGR1_PLL3PRIV_Pos              (2U)
+#define RCC_PRIVCFGR1_PLL3PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR1_PLL3PRIV                  RCC_PRIVCFGR1_PLL3PRIV_Msk           /*!< Privileged protection of PLL3 configuration bits */
+#define RCC_PRIVCFGR1_PLL4PRIV_Pos              (3U)
+#define RCC_PRIVCFGR1_PLL4PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR1_PLL4PRIV                  RCC_PRIVCFGR1_PLL4PRIV_Msk           /*!< Privileged protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR1 register  *****************/
+#define RCC_LOCKCFGR1_PLL1LOCK_Pos              (0U)
+#define RCC_LOCKCFGR1_PLL1LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */
+#define RCC_LOCKCFGR1_PLL1LOCK                  RCC_LOCKCFGR1_PLL1LOCK_Msk           /*!< Locked protection of PLL1 configuration bits */
+#define RCC_LOCKCFGR1_PLL2LOCK_Pos              (1U)
+#define RCC_LOCKCFGR1_PLL2LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR1_PLL2LOCK                  RCC_LOCKCFGR1_PLL2LOCK_Msk           /*!< Locked protection of PLL2 configuration bits */
+#define RCC_LOCKCFGR1_PLL3LOCK_Pos              (2U)
+#define RCC_LOCKCFGR1_PLL3LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR1_PLL3LOCK                  RCC_LOCKCFGR1_PLL3LOCK_Msk           /*!< Locked protection of PLL3 configuration bits */
+#define RCC_LOCKCFGR1_PLL4LOCK_Pos              (3U)
+#define RCC_LOCKCFGR1_PLL4LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR1_PLL4LOCK                  RCC_LOCKCFGR1_PLL4LOCK_Msk           /*!< Locked protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR1 register  *****************/
+#define RCC_PUBCFGR1_PLL1PUB_Pos                (0U)
+#define RCC_PUBCFGR1_PLL1PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGR1_PLL1PUB                    RCC_PUBCFGR1_PLL1PUB_Msk             /*!< Public protection of PLL1 configuration bits */
+#define RCC_PUBCFGR1_PLL2PUB_Pos                (1U)
+#define RCC_PUBCFGR1_PLL2PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGR1_PLL2PUB                    RCC_PUBCFGR1_PLL2PUB_Msk             /*!< Public protection of PLL2 configuration bits */
+#define RCC_PUBCFGR1_PLL3PUB_Pos                (2U)
+#define RCC_PUBCFGR1_PLL3PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR1_PLL3PUB                    RCC_PUBCFGR1_PLL3PUB_Msk             /*!< Public protection of PLL3 configuration bits */
+#define RCC_PUBCFGR1_PLL4PUB_Pos                (3U)
+#define RCC_PUBCFGR1_PLL4PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR1_PLL4PUB                    RCC_PUBCFGR1_PLL4PUB_Msk             /*!< Public protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR2 register  *****************/
+#define RCC_SECCFGR2_IC1SEC_Pos                 (0U)
+#define RCC_SECCFGR2_IC1SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC1SEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR2_IC1SEC                     RCC_SECCFGR2_IC1SEC_Msk              /*!< Secure protection of IC1 divider configuration bits */
+#define RCC_SECCFGR2_IC2SEC_Pos                 (1U)
+#define RCC_SECCFGR2_IC2SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC2SEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR2_IC2SEC                     RCC_SECCFGR2_IC2SEC_Msk              /*!< Secure protection of IC2 divider configuration bits */
+#define RCC_SECCFGR2_IC3SEC_Pos                 (2U)
+#define RCC_SECCFGR2_IC3SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC3SEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR2_IC3SEC                     RCC_SECCFGR2_IC3SEC_Msk              /*!< Secure protection of IC3 divider configuration bits */
+#define RCC_SECCFGR2_IC4SEC_Pos                 (3U)
+#define RCC_SECCFGR2_IC4SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC4SEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR2_IC4SEC                     RCC_SECCFGR2_IC4SEC_Msk              /*!< Secure protection of IC4 divider configuration bits */
+#define RCC_SECCFGR2_IC5SEC_Pos                 (4U)
+#define RCC_SECCFGR2_IC5SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC5SEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR2_IC5SEC                     RCC_SECCFGR2_IC5SEC_Msk              /*!< Secure protection of IC5 divider configuration bits */
+#define RCC_SECCFGR2_IC6SEC_Pos                 (5U)
+#define RCC_SECCFGR2_IC6SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC6SEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR2_IC6SEC                     RCC_SECCFGR2_IC6SEC_Msk              /*!< Secure protection of IC6 divider configuration bits */
+#define RCC_SECCFGR2_IC7SEC_Pos                 (6U)
+#define RCC_SECCFGR2_IC7SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC7SEC_Pos)    /*!< 0x00000040 */
+#define RCC_SECCFGR2_IC7SEC                     RCC_SECCFGR2_IC7SEC_Msk              /*!< Secure protection of IC7 divider configuration bits */
+#define RCC_SECCFGR2_IC8SEC_Pos                 (7U)
+#define RCC_SECCFGR2_IC8SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC8SEC_Pos)    /*!< 0x00000080 */
+#define RCC_SECCFGR2_IC8SEC                     RCC_SECCFGR2_IC8SEC_Msk              /*!< Secure protection of IC8 divider configuration bits */
+#define RCC_SECCFGR2_IC9SEC_Pos                 (8U)
+#define RCC_SECCFGR2_IC9SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC9SEC_Pos)    /*!< 0x00000100 */
+#define RCC_SECCFGR2_IC9SEC                     RCC_SECCFGR2_IC9SEC_Msk              /*!< Secure protection of IC9 divider configuration bits */
+#define RCC_SECCFGR2_IC10SEC_Pos                (9U)
+#define RCC_SECCFGR2_IC10SEC_Msk                (0x1UL << RCC_SECCFGR2_IC10SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR2_IC10SEC                    RCC_SECCFGR2_IC10SEC_Msk             /*!< Secure protection of IC10 divider configuration bits */
+#define RCC_SECCFGR2_IC11SEC_Pos                (10U)
+#define RCC_SECCFGR2_IC11SEC_Msk                (0x1UL << RCC_SECCFGR2_IC11SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR2_IC11SEC                    RCC_SECCFGR2_IC11SEC_Msk             /*!< Secure protection of IC11 divider configuration bits */
+#define RCC_SECCFGR2_IC12SEC_Pos                (11U)
+#define RCC_SECCFGR2_IC12SEC_Msk                (0x1UL << RCC_SECCFGR2_IC12SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR2_IC12SEC                    RCC_SECCFGR2_IC12SEC_Msk             /*!< Secure protection of IC12 divider configuration bits */
+#define RCC_SECCFGR2_IC13SEC_Pos                (12U)
+#define RCC_SECCFGR2_IC13SEC_Msk                (0x1UL << RCC_SECCFGR2_IC13SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR2_IC13SEC                    RCC_SECCFGR2_IC13SEC_Msk             /*!< Secure protection of IC13 divider configuration bits */
+#define RCC_SECCFGR2_IC14SEC_Pos                (13U)
+#define RCC_SECCFGR2_IC14SEC_Msk                (0x1UL << RCC_SECCFGR2_IC14SEC_Pos)   /*!< 0x00002000 */
+#define RCC_SECCFGR2_IC14SEC                    RCC_SECCFGR2_IC14SEC_Msk             /*!< Secure protection of IC14 divider configuration bits */
+#define RCC_SECCFGR2_IC15SEC_Pos                (14U)
+#define RCC_SECCFGR2_IC15SEC_Msk                (0x1UL << RCC_SECCFGR2_IC15SEC_Pos)   /*!< 0x00004000 */
+#define RCC_SECCFGR2_IC15SEC                    RCC_SECCFGR2_IC15SEC_Msk             /*!< Secure protection of IC15 divider configuration bits */
+#define RCC_SECCFGR2_IC16SEC_Pos                (15U)
+#define RCC_SECCFGR2_IC16SEC_Msk                (0x1UL << RCC_SECCFGR2_IC16SEC_Pos)   /*!< 0x00008000 */
+#define RCC_SECCFGR2_IC16SEC                    RCC_SECCFGR2_IC16SEC_Msk             /*!< Secure protection of IC16 divider configuration bits */
+#define RCC_SECCFGR2_IC17SEC_Pos                (16U)
+#define RCC_SECCFGR2_IC17SEC_Msk                (0x1UL << RCC_SECCFGR2_IC17SEC_Pos)   /*!< 0x00010000 */
+#define RCC_SECCFGR2_IC17SEC                    RCC_SECCFGR2_IC17SEC_Msk             /*!< Secure protection of IC17 divider configuration bits */
+#define RCC_SECCFGR2_IC18SEC_Pos                (17U)
+#define RCC_SECCFGR2_IC18SEC_Msk                (0x1UL << RCC_SECCFGR2_IC18SEC_Pos)   /*!< 0x00020000 */
+#define RCC_SECCFGR2_IC18SEC                    RCC_SECCFGR2_IC18SEC_Msk             /*!< Secure protection of IC18 divider configuration bits */
+#define RCC_SECCFGR2_IC19SEC_Pos                (18U)
+#define RCC_SECCFGR2_IC19SEC_Msk                (0x1UL << RCC_SECCFGR2_IC19SEC_Pos)   /*!< 0x00040000 */
+#define RCC_SECCFGR2_IC19SEC                    RCC_SECCFGR2_IC19SEC_Msk             /*!< Secure protection of IC19 divider configuration bits */
+#define RCC_SECCFGR2_IC20SEC_Pos                (19U)
+#define RCC_SECCFGR2_IC20SEC_Msk                (0x1UL << RCC_SECCFGR2_IC20SEC_Pos)   /*!< 0x00080000 */
+#define RCC_SECCFGR2_IC20SEC                    RCC_SECCFGR2_IC20SEC_Msk             /*!< Secure protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR2 register  *****************/
+#define RCC_PRIVCFGR2_IC1PRIV_Pos               (0U)
+#define RCC_PRIVCFGR2_IC1PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR2_IC1PRIV                   RCC_PRIVCFGR2_IC1PRIV_Msk            /*!< Privileged protection of IC1 divider configuration bits */
+#define RCC_PRIVCFGR2_IC2PRIV_Pos               (1U)
+#define RCC_PRIVCFGR2_IC2PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR2_IC2PRIV                   RCC_PRIVCFGR2_IC2PRIV_Msk            /*!< Privileged protection of IC2 divider configuration bits */
+#define RCC_PRIVCFGR2_IC3PRIV_Pos               (2U)
+#define RCC_PRIVCFGR2_IC3PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR2_IC3PRIV                   RCC_PRIVCFGR2_IC3PRIV_Msk            /*!< Privileged protection of IC3 divider configuration bits */
+#define RCC_PRIVCFGR2_IC4PRIV_Pos               (3U)
+#define RCC_PRIVCFGR2_IC4PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR2_IC4PRIV                   RCC_PRIVCFGR2_IC4PRIV_Msk            /*!< Privileged protection of IC4 divider configuration bits */
+#define RCC_PRIVCFGR2_IC5PRIV_Pos               (4U)
+#define RCC_PRIVCFGR2_IC5PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR2_IC5PRIV                   RCC_PRIVCFGR2_IC5PRIV_Msk            /*!< Privileged protection of IC5 divider configuration bits */
+#define RCC_PRIVCFGR2_IC6PRIV_Pos               (5U)
+#define RCC_PRIVCFGR2_IC6PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR2_IC6PRIV                   RCC_PRIVCFGR2_IC6PRIV_Msk            /*!< Privileged protection of IC6 divider configuration bits */
+#define RCC_PRIVCFGR2_IC7PRIV_Pos               (6U)
+#define RCC_PRIVCFGR2_IC7PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos)  /*!< 0x00000040 */
+#define RCC_PRIVCFGR2_IC7PRIV                   RCC_PRIVCFGR2_IC7PRIV_Msk            /*!< Privileged protection of IC7 divider configuration bits */
+#define RCC_PRIVCFGR2_IC8PRIV_Pos               (7U)
+#define RCC_PRIVCFGR2_IC8PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos)  /*!< 0x00000080 */
+#define RCC_PRIVCFGR2_IC8PRIV                   RCC_PRIVCFGR2_IC8PRIV_Msk            /*!< Privileged protection of IC8 divider configuration bits */
+#define RCC_PRIVCFGR2_IC9PRIV_Pos               (8U)
+#define RCC_PRIVCFGR2_IC9PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos)  /*!< 0x00000100 */
+#define RCC_PRIVCFGR2_IC9PRIV                   RCC_PRIVCFGR2_IC9PRIV_Msk            /*!< Privileged protection of IC9 divider configuration bits */
+#define RCC_PRIVCFGR2_IC10PRIV_Pos              (9U)
+#define RCC_PRIVCFGR2_IC10PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR2_IC10PRIV                  RCC_PRIVCFGR2_IC10PRIV_Msk           /*!< Privileged protection of IC10 divider configuration bits */
+#define RCC_PRIVCFGR2_IC11PRIV_Pos              (10U)
+#define RCC_PRIVCFGR2_IC11PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR2_IC11PRIV                  RCC_PRIVCFGR2_IC11PRIV_Msk           /*!< Privileged protection of IC11 divider configuration bits */
+#define RCC_PRIVCFGR2_IC12PRIV_Pos              (11U)
+#define RCC_PRIVCFGR2_IC12PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR2_IC12PRIV                  RCC_PRIVCFGR2_IC12PRIV_Msk           /*!< Privileged protection of IC12 divider configuration bits */
+#define RCC_PRIVCFGR2_IC13PRIV_Pos              (12U)
+#define RCC_PRIVCFGR2_IC13PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR2_IC13PRIV                  RCC_PRIVCFGR2_IC13PRIV_Msk           /*!< Privileged protection of IC13 divider configuration bits */
+#define RCC_PRIVCFGR2_IC14PRIV_Pos              (13U)
+#define RCC_PRIVCFGR2_IC14PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGR2_IC14PRIV                  RCC_PRIVCFGR2_IC14PRIV_Msk           /*!< Privileged protection of IC14 divider configuration bits */
+#define RCC_PRIVCFGR2_IC15PRIV_Pos              (14U)
+#define RCC_PRIVCFGR2_IC15PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGR2_IC15PRIV                  RCC_PRIVCFGR2_IC15PRIV_Msk           /*!< Privileged protection of IC15 divider configuration bits */
+#define RCC_PRIVCFGR2_IC16PRIV_Pos              (15U)
+#define RCC_PRIVCFGR2_IC16PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGR2_IC16PRIV                  RCC_PRIVCFGR2_IC16PRIV_Msk           /*!< Privileged protection of IC16 divider configuration bits */
+#define RCC_PRIVCFGR2_IC17PRIV_Pos              (16U)
+#define RCC_PRIVCFGR2_IC17PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGR2_IC17PRIV                  RCC_PRIVCFGR2_IC17PRIV_Msk           /*!< Privileges protection of IC17 divider configuration bits */
+#define RCC_PRIVCFGR2_IC18PRIV_Pos              (17U)
+#define RCC_PRIVCFGR2_IC18PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGR2_IC18PRIV                  RCC_PRIVCFGR2_IC18PRIV_Msk           /*!< Privilege protection of IC18 divider configuration bits */
+#define RCC_PRIVCFGR2_IC19PRIV_Pos              (18U)
+#define RCC_PRIVCFGR2_IC19PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGR2_IC19PRIV                  RCC_PRIVCFGR2_IC19PRIV_Msk           /*!< Privileged protection of IC19 divider configuration bits */
+#define RCC_PRIVCFGR2_IC20PRIV_Pos              (19U)
+#define RCC_PRIVCFGR2_IC20PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGR2_IC20PRIV                  RCC_PRIVCFGR2_IC20PRIV_Msk           /*!< Privileged protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR2 register  *****************/
+#define RCC_LOCKCFGR2_IC1LOCK_Pos               (0U)
+#define RCC_LOCKCFGR2_IC1LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR2_IC1LOCK                   RCC_LOCKCFGR2_IC1LOCK_Msk            /*!< Locked protection of IC1 divider configuration bits */
+#define RCC_LOCKCFGR2_IC2LOCK_Pos               (1U)
+#define RCC_LOCKCFGR2_IC2LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR2_IC2LOCK                   RCC_LOCKCFGR2_IC2LOCK_Msk            /*!< Locked protection of IC2 divider configuration bits */
+#define RCC_LOCKCFGR2_IC3LOCK_Pos               (2U)
+#define RCC_LOCKCFGR2_IC3LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR2_IC3LOCK                   RCC_LOCKCFGR2_IC3LOCK_Msk            /*!< Locked protection of IC3 divider configuration bits */
+#define RCC_LOCKCFGR2_IC4LOCK_Pos               (3U)
+#define RCC_LOCKCFGR2_IC4LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR2_IC4LOCK                   RCC_LOCKCFGR2_IC4LOCK_Msk            /*!< Locked protection of IC4 divider configuration bits */
+#define RCC_LOCKCFGR2_IC5LOCK_Pos               (4U)
+#define RCC_LOCKCFGR2_IC5LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR2_IC5LOCK                   RCC_LOCKCFGR2_IC5LOCK_Msk            /*!< Locked protection of IC5 divider configuration bits */
+#define RCC_LOCKCFGR2_IC6LOCK_Pos               (5U)
+#define RCC_LOCKCFGR2_IC6LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR2_IC6LOCK                   RCC_LOCKCFGR2_IC6LOCK_Msk            /*!< Locked protection of IC6 divider configuration bits */
+#define RCC_LOCKCFGR2_IC7LOCK_Pos               (6U)
+#define RCC_LOCKCFGR2_IC7LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos)  /*!< 0x00000040 */
+#define RCC_LOCKCFGR2_IC7LOCK                   RCC_LOCKCFGR2_IC7LOCK_Msk            /*!< Locked protection of IC7 divider configuration bits */
+#define RCC_LOCKCFGR2_IC8LOCK_Pos               (7U)
+#define RCC_LOCKCFGR2_IC8LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos)  /*!< 0x00000080 */
+#define RCC_LOCKCFGR2_IC8LOCK                   RCC_LOCKCFGR2_IC8LOCK_Msk            /*!< Locked protection of IC8 divider configuration bits */
+#define RCC_LOCKCFGR2_IC9LOCK_Pos               (8U)
+#define RCC_LOCKCFGR2_IC9LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos)  /*!< 0x00000100 */
+#define RCC_LOCKCFGR2_IC9LOCK                   RCC_LOCKCFGR2_IC9LOCK_Msk            /*!< Locked protection of IC9 divider configuration bits */
+#define RCC_LOCKCFGR2_IC10LOCK_Pos              (9U)
+#define RCC_LOCKCFGR2_IC10LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR2_IC10LOCK                  RCC_LOCKCFGR2_IC10LOCK_Msk           /*!< Locked protection of IC10 divider configuration bits */
+#define RCC_LOCKCFGR2_IC11LOCK_Pos              (10U)
+#define RCC_LOCKCFGR2_IC11LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR2_IC11LOCK                  RCC_LOCKCFGR2_IC11LOCK_Msk           /*!< Locked protection of IC11 divider configuration bits */
+#define RCC_LOCKCFGR2_IC12LOCK_Pos              (11U)
+#define RCC_LOCKCFGR2_IC12LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR2_IC12LOCK                  RCC_LOCKCFGR2_IC12LOCK_Msk           /*!< Locked protection of IC12 divider configuration bits */
+#define RCC_LOCKCFGR2_IC13LOCK_Pos              (12U)
+#define RCC_LOCKCFGR2_IC13LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR2_IC13LOCK                  RCC_LOCKCFGR2_IC13LOCK_Msk           /*!< Locked protection of IC13 divider configuration bits */
+#define RCC_LOCKCFGR2_IC14LOCK_Pos              (13U)
+#define RCC_LOCKCFGR2_IC14LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */
+#define RCC_LOCKCFGR2_IC14LOCK                  RCC_LOCKCFGR2_IC14LOCK_Msk           /*!< Locked protection of IC14 divider configuration bits */
+#define RCC_LOCKCFGR2_IC15LOCK_Pos              (14U)
+#define RCC_LOCKCFGR2_IC15LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */
+#define RCC_LOCKCFGR2_IC15LOCK                  RCC_LOCKCFGR2_IC15LOCK_Msk           /*!< Locked protection of IC15 divider configuration bits */
+#define RCC_LOCKCFGR2_IC16LOCK_Pos              (15U)
+#define RCC_LOCKCFGR2_IC16LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */
+#define RCC_LOCKCFGR2_IC16LOCK                  RCC_LOCKCFGR2_IC16LOCK_Msk           /*!< Locked protection of IC16 divider configuration bits */
+#define RCC_LOCKCFGR2_IC17LOCK_Pos              (16U)
+#define RCC_LOCKCFGR2_IC17LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */
+#define RCC_LOCKCFGR2_IC17LOCK                  RCC_LOCKCFGR2_IC17LOCK_Msk           /*!< Locked protection of IC17 divider configuration bits */
+#define RCC_LOCKCFGR2_IC18LOCK_Pos              (17U)
+#define RCC_LOCKCFGR2_IC18LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */
+#define RCC_LOCKCFGR2_IC18LOCK                  RCC_LOCKCFGR2_IC18LOCK_Msk           /*!< Locked protection of IC18 divider configuration bits */
+#define RCC_LOCKCFGR2_IC19LOCK_Pos              (18U)
+#define RCC_LOCKCFGR2_IC19LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */
+#define RCC_LOCKCFGR2_IC19LOCK                  RCC_LOCKCFGR2_IC19LOCK_Msk           /*!< Locked protection of IC19 divider configuration bits */
+#define RCC_LOCKCFGR2_IC20LOCK_Pos              (19U)
+#define RCC_LOCKCFGR2_IC20LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */
+#define RCC_LOCKCFGR2_IC20LOCK                  RCC_LOCKCFGR2_IC20LOCK_Msk           /*!< Locked protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR2 register  *****************/
+#define RCC_PUBCFGR2_IC1PUB_Pos                 (0U)
+#define RCC_PUBCFGR2_IC1PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR2_IC1PUB                     RCC_PUBCFGR2_IC1PUB_Msk              /*!< Public protection of IC1 divider configuration bits */
+#define RCC_PUBCFGR2_IC2PUB_Pos                 (1U)
+#define RCC_PUBCFGR2_IC2PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR2_IC2PUB                     RCC_PUBCFGR2_IC2PUB_Msk              /*!< Public protection of IC2 divider configuration bits */
+#define RCC_PUBCFGR2_IC3PUB_Pos                 (2U)
+#define RCC_PUBCFGR2_IC3PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR2_IC3PUB                     RCC_PUBCFGR2_IC3PUB_Msk              /*!< Public protection of IC3 divider configuration bits */
+#define RCC_PUBCFGR2_IC4PUB_Pos                 (3U)
+#define RCC_PUBCFGR2_IC4PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR2_IC4PUB                     RCC_PUBCFGR2_IC4PUB_Msk              /*!< Public protection of IC4 divider configuration bits */
+#define RCC_PUBCFGR2_IC5PUB_Pos                 (4U)
+#define RCC_PUBCFGR2_IC5PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR2_IC5PUB                     RCC_PUBCFGR2_IC5PUB_Msk              /*!< Public protection of IC5 divider configuration bits */
+#define RCC_PUBCFGR2_IC6PUB_Pos                 (5U)
+#define RCC_PUBCFGR2_IC6PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR2_IC6PUB                     RCC_PUBCFGR2_IC6PUB_Msk              /*!< Public protection of IC6 divider configuration bits */
+#define RCC_PUBCFGR2_IC7PUB_Pos                 (6U)
+#define RCC_PUBCFGR2_IC7PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos)    /*!< 0x00000040 */
+#define RCC_PUBCFGR2_IC7PUB                     RCC_PUBCFGR2_IC7PUB_Msk              /*!< Public protection of IC7 divider configuration bits */
+#define RCC_PUBCFGR2_IC8PUB_Pos                 (7U)
+#define RCC_PUBCFGR2_IC8PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos)    /*!< 0x00000080 */
+#define RCC_PUBCFGR2_IC8PUB                     RCC_PUBCFGR2_IC8PUB_Msk              /*!< Public protection of IC8 divider configuration bits */
+#define RCC_PUBCFGR2_IC9PUB_Pos                 (8U)
+#define RCC_PUBCFGR2_IC9PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos)    /*!< 0x00000100 */
+#define RCC_PUBCFGR2_IC9PUB                     RCC_PUBCFGR2_IC9PUB_Msk              /*!< Public protection of IC9 divider configuration bits */
+#define RCC_PUBCFGR2_IC10PUB_Pos                (9U)
+#define RCC_PUBCFGR2_IC10PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR2_IC10PUB                    RCC_PUBCFGR2_IC10PUB_Msk             /*!< Public protection of IC10 divider configuration bits */
+#define RCC_PUBCFGR2_IC11PUB_Pos                (10U)
+#define RCC_PUBCFGR2_IC11PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR2_IC11PUB                    RCC_PUBCFGR2_IC11PUB_Msk             /*!< Public protection of IC11 divider configuration bits */
+#define RCC_PUBCFGR2_IC12PUB_Pos                (11U)
+#define RCC_PUBCFGR2_IC12PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR2_IC12PUB                    RCC_PUBCFGR2_IC12PUB_Msk             /*!< Public protection of IC12 divider configuration bits */
+#define RCC_PUBCFGR2_IC13PUB_Pos                (12U)
+#define RCC_PUBCFGR2_IC13PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR2_IC13PUB                    RCC_PUBCFGR2_IC13PUB_Msk             /*!< Public protection of IC13 divider configuration bits */
+#define RCC_PUBCFGR2_IC14PUB_Pos                (13U)
+#define RCC_PUBCFGR2_IC14PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos)   /*!< 0x00002000 */
+#define RCC_PUBCFGR2_IC14PUB                    RCC_PUBCFGR2_IC14PUB_Msk             /*!< Public protection of IC14 divider configuration bits */
+#define RCC_PUBCFGR2_IC15PUB_Pos                (14U)
+#define RCC_PUBCFGR2_IC15PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos)   /*!< 0x00004000 */
+#define RCC_PUBCFGR2_IC15PUB                    RCC_PUBCFGR2_IC15PUB_Msk             /*!< Public protection of IC15 divider configuration bits */
+#define RCC_PUBCFGR2_IC16PUB_Pos                (15U)
+#define RCC_PUBCFGR2_IC16PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos)   /*!< 0x00008000 */
+#define RCC_PUBCFGR2_IC16PUB                    RCC_PUBCFGR2_IC16PUB_Msk             /*!< Public protection of IC16 divider configuration bits */
+#define RCC_PUBCFGR2_IC17PUB_Pos                (16U)
+#define RCC_PUBCFGR2_IC17PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos)   /*!< 0x00010000 */
+#define RCC_PUBCFGR2_IC17PUB                    RCC_PUBCFGR2_IC17PUB_Msk             /*!< Public protection of IC17 divider configuration bits */
+#define RCC_PUBCFGR2_IC18PUB_Pos                (17U)
+#define RCC_PUBCFGR2_IC18PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos)   /*!< 0x00020000 */
+#define RCC_PUBCFGR2_IC18PUB                    RCC_PUBCFGR2_IC18PUB_Msk             /*!< Public protection of IC18 divider configuration bits */
+#define RCC_PUBCFGR2_IC19PUB_Pos                (18U)
+#define RCC_PUBCFGR2_IC19PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos)   /*!< 0x00040000 */
+#define RCC_PUBCFGR2_IC19PUB                    RCC_PUBCFGR2_IC19PUB_Msk             /*!< Public protection of IC19 divider configuration bits */
+#define RCC_PUBCFGR2_IC20PUB_Pos                (19U)
+#define RCC_PUBCFGR2_IC20PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos)   /*!< 0x00080000 */
+#define RCC_PUBCFGR2_IC20PUB                    RCC_PUBCFGR2_IC20PUB_Msk             /*!< Public protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR3 register  *****************/
+#define RCC_SECCFGR3_MODSEC_Pos                 (0U)
+#define RCC_SECCFGR3_MODSEC_Msk                 (0x1UL << RCC_SECCFGR3_MODSEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR3_MODSEC                     RCC_SECCFGR3_MODSEC_Msk              /*!< Secure protection of MOD system configuration bits */
+#define RCC_SECCFGR3_SYSSEC_Pos                 (1U)
+#define RCC_SECCFGR3_SYSSEC_Msk                 (0x1UL << RCC_SECCFGR3_SYSSEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR3_SYSSEC                     RCC_SECCFGR3_SYSSEC_Msk              /*!< Secure protection of SYS system configuration bit */
+#define RCC_SECCFGR3_BUSSEC_Pos                 (2U)
+#define RCC_SECCFGR3_BUSSEC_Msk                 (0x1UL << RCC_SECCFGR3_BUSSEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR3_BUSSEC                     RCC_SECCFGR3_BUSSEC_Msk              /*!< Secure protection of BUS system configuration bits */
+#define RCC_SECCFGR3_PERSEC_Pos                 (3U)
+#define RCC_SECCFGR3_PERSEC_Msk                 (0x1UL << RCC_SECCFGR3_PERSEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR3_PERSEC                     RCC_SECCFGR3_PERSEC_Msk              /*!< Secure protection of PER system configuration bits */
+#define RCC_SECCFGR3_INTSEC_Pos                 (4U)
+#define RCC_SECCFGR3_INTSEC_Msk                 (0x1UL << RCC_SECCFGR3_INTSEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR3_INTSEC                     RCC_SECCFGR3_INTSEC_Msk              /*!< Secure protection of INT system configuration bits */
+#define RCC_SECCFGR3_RSTSEC_Pos                 (5U)
+#define RCC_SECCFGR3_RSTSEC_Msk                 (0x1UL << RCC_SECCFGR3_RSTSEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR3_RSTSEC                     RCC_SECCFGR3_RSTSEC_Msk              /*!< Secure protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR3 register  *****************/
+#define RCC_PRIVCFGR3_MODPRIV_Pos               (0U)
+#define RCC_PRIVCFGR3_MODPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR3_MODPRIV                   RCC_PRIVCFGR3_MODPRIV_Msk            /*!< Privileged protection of MOD system configuration bits */
+#define RCC_PRIVCFGR3_SYSPRIV_Pos               (1U)
+#define RCC_PRIVCFGR3_SYSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR3_SYSPRIV                   RCC_PRIVCFGR3_SYSPRIV_Msk            /*!< Privileged protection of SYS system configuration bits */
+#define RCC_PRIVCFGR3_BUSPRIV_Pos               (2U)
+#define RCC_PRIVCFGR3_BUSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR3_BUSPRIV                   RCC_PRIVCFGR3_BUSPRIV_Msk            /*!< Privileged protection of BUS system configuration bits */
+#define RCC_PRIVCFGR3_PERPRIV_Pos               (3U)
+#define RCC_PRIVCFGR3_PERPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR3_PERPRIV                   RCC_PRIVCFGR3_PERPRIV_Msk            /*!< Privileged protection of PER system configuration bits */
+#define RCC_PRIVCFGR3_INTPRIV_Pos               (4U)
+#define RCC_PRIVCFGR3_INTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR3_INTPRIV                   RCC_PRIVCFGR3_INTPRIV_Msk            /*!< Privileged protection of INT system configuration bits */
+#define RCC_PRIVCFGR3_RSTPRIV_Pos               (5U)
+#define RCC_PRIVCFGR3_RSTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR3_RSTPRIV                   RCC_PRIVCFGR3_RSTPRIV_Msk            /*!< Privileged protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR3 register  *****************/
+#define RCC_LOCKCFGR3_MODLOCK_Pos               (0U)
+#define RCC_LOCKCFGR3_MODLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR3_MODLOCK                   RCC_LOCKCFGR3_MODLOCK_Msk            /*!< Locked protection of MOD system configuration bits */
+#define RCC_LOCKCFGR3_SYSLOCK_Pos               (1U)
+#define RCC_LOCKCFGR3_SYSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR3_SYSLOCK                   RCC_LOCKCFGR3_SYSLOCK_Msk            /*!< Locked protection of SYS system configuration bits */
+#define RCC_LOCKCFGR3_BUSLOCK_Pos               (2U)
+#define RCC_LOCKCFGR3_BUSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR3_BUSLOCK                   RCC_LOCKCFGR3_BUSLOCK_Msk            /*!< Locked protection of BUS system configuration bits */
+#define RCC_LOCKCFGR3_PERLOCK_Pos               (3U)
+#define RCC_LOCKCFGR3_PERLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR3_PERLOCK                   RCC_LOCKCFGR3_PERLOCK_Msk            /*!< Locked protection of PER system configuration bits */
+#define RCC_LOCKCFGR3_INTLOCK_Pos               (4U)
+#define RCC_LOCKCFGR3_INTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR3_INTLOCK                   RCC_LOCKCFGR3_INTLOCK_Msk            /*!< Locked protection of INT system configuration bits */
+#define RCC_LOCKCFGR3_RSTLOCK_Pos               (5U)
+#define RCC_LOCKCFGR3_RSTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR3_RSTLOCK                   RCC_LOCKCFGR3_RSTLOCK_Msk            /*!< Locked protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR3 register  *****************/
+#define RCC_PUBCFGR3_MODPUB_Pos                 (0U)
+#define RCC_PUBCFGR3_MODPUB_Msk                 (0x1UL << RCC_PUBCFGR3_MODPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR3_MODPUB                     RCC_PUBCFGR3_MODPUB_Msk              /*!< Public protection of MOD system configuration bits */
+#define RCC_PUBCFGR3_SYSPUB_Pos                 (1U)
+#define RCC_PUBCFGR3_SYSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR3_SYSPUB                     RCC_PUBCFGR3_SYSPUB_Msk              /*!< Public protection of SYS system configuration bits */
+#define RCC_PUBCFGR3_BUSPUB_Pos                 (2U)
+#define RCC_PUBCFGR3_BUSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR3_BUSPUB                     RCC_PUBCFGR3_BUSPUB_Msk              /*!< Public protection of BUS system configuration bits */
+#define RCC_PUBCFGR3_PERPUB_Pos                 (3U)
+#define RCC_PUBCFGR3_PERPUB_Msk                 (0x1UL << RCC_PUBCFGR3_PERPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR3_PERPUB                     RCC_PUBCFGR3_PERPUB_Msk              /*!< Public protection of PER system configuration bits */
+#define RCC_PUBCFGR3_INTPUB_Pos                 (4U)
+#define RCC_PUBCFGR3_INTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_INTPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR3_INTPUB                     RCC_PUBCFGR3_INTPUB_Msk              /*!< Public protection of INT system configuration bits */
+#define RCC_PUBCFGR3_RSTPUB_Pos                 (5U)
+#define RCC_PUBCFGR3_RSTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR3_RSTPUB                     RCC_PUBCFGR3_RSTPUB_Msk              /*!< Public protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR4 register  *****************/
+#define RCC_SECCFGR4_ACLKNSEC_Pos               (0U)
+#define RCC_SECCFGR4_ACLKNSEC_Msk               (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos)  /*!< 0x00000001 */
+#define RCC_SECCFGR4_ACLKNSEC                   RCC_SECCFGR4_ACLKNSEC_Msk            /*!< Secure protection of ACLKN bus configuration bits */
+#define RCC_SECCFGR4_ACLKNCSEC_Pos              (1U)
+#define RCC_SECCFGR4_ACLKNCSEC_Msk              (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */
+#define RCC_SECCFGR4_ACLKNCSEC                  RCC_SECCFGR4_ACLKNCSEC_Msk           /*!< Secure protection of ACLKNC bus configuration bits */
+#define RCC_SECCFGR4_AHBMSEC_Pos                (2U)
+#define RCC_SECCFGR4_AHBMSEC_Msk                (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR4_AHBMSEC                    RCC_SECCFGR4_AHBMSEC_Msk             /*!< Secure protection of AHBM bus configuration bits */
+#define RCC_SECCFGR4_AHB1SEC_Pos                (3U)
+#define RCC_SECCFGR4_AHB1SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR4_AHB1SEC                    RCC_SECCFGR4_AHB1SEC_Msk             /*!< Secure protection of AHB1 bus configuration bits */
+#define RCC_SECCFGR4_AHB2SEC_Pos                (4U)
+#define RCC_SECCFGR4_AHB2SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos)   /*!< 0x00000010 */
+#define RCC_SECCFGR4_AHB2SEC                    RCC_SECCFGR4_AHB2SEC_Msk             /*!< Secure protection of AHB2 bus configuration bits */
+#define RCC_SECCFGR4_AHB3SEC_Pos                (5U)
+#define RCC_SECCFGR4_AHB3SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos)   /*!< 0x00000020 */
+#define RCC_SECCFGR4_AHB3SEC                    RCC_SECCFGR4_AHB3SEC_Msk             /*!< Secure protection of AHB3 bus configuration bits */
+#define RCC_SECCFGR4_AHB4SEC_Pos                (6U)
+#define RCC_SECCFGR4_AHB4SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos)   /*!< 0x00000040 */
+#define RCC_SECCFGR4_AHB4SEC                    RCC_SECCFGR4_AHB4SEC_Msk             /*!< Secure protection of AHB4 bus configuration bits */
+#define RCC_SECCFGR4_AHB5SEC_Pos                (7U)
+#define RCC_SECCFGR4_AHB5SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos)   /*!< 0x00000080 */
+#define RCC_SECCFGR4_AHB5SEC                    RCC_SECCFGR4_AHB5SEC_Msk             /*!< Secure protection of AHB5 bus configuration bits */
+#define RCC_SECCFGR4_APB1SEC_Pos                (8U)
+#define RCC_SECCFGR4_APB1SEC_Msk                (0x1UL << RCC_SECCFGR4_APB1SEC_Pos)   /*!< 0x00000100 */
+#define RCC_SECCFGR4_APB1SEC                    RCC_SECCFGR4_APB1SEC_Msk             /*!< Secure protection of APB1 bus configuration bits */
+#define RCC_SECCFGR4_APB2SEC_Pos                (9U)
+#define RCC_SECCFGR4_APB2SEC_Msk                (0x1UL << RCC_SECCFGR4_APB2SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR4_APB2SEC                    RCC_SECCFGR4_APB2SEC_Msk             /*!< Secure protection of APB2 bus configuration bits */
+#define RCC_SECCFGR4_APB3SEC_Pos                (10U)
+#define RCC_SECCFGR4_APB3SEC_Msk                (0x1UL << RCC_SECCFGR4_APB3SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR4_APB3SEC                    RCC_SECCFGR4_APB3SEC_Msk             /*!< Secure protection of APB3 bus configuration bits */
+#define RCC_SECCFGR4_APB4SEC_Pos                (11U)
+#define RCC_SECCFGR4_APB4SEC_Msk                (0x1UL << RCC_SECCFGR4_APB4SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR4_APB4SEC                    RCC_SECCFGR4_APB4SEC_Msk             /*!< Secure protection of APB4 bus configuration bits */
+#define RCC_SECCFGR4_APB5SEC_Pos                (12U)
+#define RCC_SECCFGR4_APB5SEC_Msk                (0x1UL << RCC_SECCFGR4_APB5SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR4_APB5SEC                    RCC_SECCFGR4_APB5SEC_Msk             /*!< Secure protection of APB5 bus configuration bits */
+#define RCC_SECCFGR4_NOCSEC_Pos                 (13U)
+#define RCC_SECCFGR4_NOCSEC_Msk                 (0x1UL << RCC_SECCFGR4_NOCSEC_Pos)    /*!< 0x00002000 */
+#define RCC_SECCFGR4_NOCSEC                     RCC_SECCFGR4_NOCSEC_Msk              /*!< Secure protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR4 register  *****************/
+#define RCC_PRIVCFGR4_ACLKNPRIV_Pos             (0U)
+#define RCC_PRIVCFGR4_ACLKNPRIV_Msk             (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGR4_ACLKNPRIV                 RCC_PRIVCFGR4_ACLKNPRIV_Msk          /*!< Privileged protection of ACLKN bus configuration bits */
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos            (1U)
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk            (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR4_ACLKNCPRIV                RCC_PRIVCFGR4_ACLKNCPRIV_Msk         /*!< Privileged protection of ACLKNC bus configuration bits */
+#define RCC_PRIVCFGR4_AHBMPRIV_Pos              (2U)
+#define RCC_PRIVCFGR4_AHBMPRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR4_AHBMPRIV                  RCC_PRIVCFGR4_AHBMPRIV_Msk           /*!< Privileged protection of AHBM bus configuration bits */
+#define RCC_PRIVCFGR4_AHB1PRIV_Pos              (3U)
+#define RCC_PRIVCFGR4_AHB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR4_AHB1PRIV                  RCC_PRIVCFGR4_AHB1PRIV_Msk           /*!< Privileged protection of AHB1 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB2PRIV_Pos              (4U)
+#define RCC_PRIVCFGR4_AHB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGR4_AHB2PRIV                  RCC_PRIVCFGR4_AHB2PRIV_Msk           /*!< Privileged protection of AHB2 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB3PRIV_Pos              (5U)
+#define RCC_PRIVCFGR4_AHB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGR4_AHB3PRIV                  RCC_PRIVCFGR4_AHB3PRIV_Msk           /*!< Privileged protection of AHB3 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB4PRIV_Pos              (6U)
+#define RCC_PRIVCFGR4_AHB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGR4_AHB4PRIV                  RCC_PRIVCFGR4_AHB4PRIV_Msk           /*!< Privileged protection of AHB4 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB5PRIV_Pos              (7U)
+#define RCC_PRIVCFGR4_AHB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGR4_AHB5PRIV                  RCC_PRIVCFGR4_AHB5PRIV_Msk           /*!< Privileged protection of AHB5 bus configuration bits */
+#define RCC_PRIVCFGR4_APB1PRIV_Pos              (8U)
+#define RCC_PRIVCFGR4_APB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGR4_APB1PRIV                  RCC_PRIVCFGR4_APB1PRIV_Msk           /*!< Privileged protection of APB1 bus configuration bits */
+#define RCC_PRIVCFGR4_APB2PRIV_Pos              (9U)
+#define RCC_PRIVCFGR4_APB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR4_APB2PRIV                  RCC_PRIVCFGR4_APB2PRIV_Msk           /*!< Privileged protection of APB2 bus configuration bits */
+#define RCC_PRIVCFGR4_APB3PRIV_Pos              (10U)
+#define RCC_PRIVCFGR4_APB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR4_APB3PRIV                  RCC_PRIVCFGR4_APB3PRIV_Msk           /*!< Privileged protection of APB3 bus configuration bits */
+#define RCC_PRIVCFGR4_APB4PRIV_Pos              (11U)
+#define RCC_PRIVCFGR4_APB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR4_APB4PRIV                  RCC_PRIVCFGR4_APB4PRIV_Msk           /*!< Privileged protection of APB4 bus configuration bits */
+#define RCC_PRIVCFGR4_APB5PRIV_Pos              (12U)
+#define RCC_PRIVCFGR4_APB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR4_APB5PRIV                  RCC_PRIVCFGR4_APB5PRIV_Msk           /*!< Privileged protection of APB5 bus configuration bits */
+#define RCC_PRIVCFGR4_NOCPRIV_Pos               (13U)
+#define RCC_PRIVCFGR4_NOCPRIV_Msk               (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos)  /*!< 0x00002000 */
+#define RCC_PRIVCFGR4_NOCPRIV                   RCC_PRIVCFGR4_NOCPRIV_Msk            /*!< Privileged protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR4 register  *****************/
+#define RCC_LOCKCFGR4_ACLKNLOCK_Pos             (0U)
+#define RCC_LOCKCFGR4_ACLKNLOCK_Msk             (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */
+#define RCC_LOCKCFGR4_ACLKNLOCK                 RCC_LOCKCFGR4_ACLKNLOCK_Msk          /*!< Locked protection of ACLKN bus configuration bits */
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos            (1U)
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk            (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR4_ACLKNCLOCK                RCC_LOCKCFGR4_ACLKNCLOCK_Msk         /*!< Locked protection of ACLKNC bus configuration bits */
+#define RCC_LOCKCFGR4_AHBMLOCK_Pos              (2U)
+#define RCC_LOCKCFGR4_AHBMLOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR4_AHBMLOCK                  RCC_LOCKCFGR4_AHBMLOCK_Msk           /*!< Locked protection of AHBM bus configuration bits */
+#define RCC_LOCKCFGR4_AHB1LOCK_Pos              (3U)
+#define RCC_LOCKCFGR4_AHB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR4_AHB1LOCK                  RCC_LOCKCFGR4_AHB1LOCK_Msk           /*!< Locked protection of AHB1 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB2LOCK_Pos              (4U)
+#define RCC_LOCKCFGR4_AHB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */
+#define RCC_LOCKCFGR4_AHB2LOCK                  RCC_LOCKCFGR4_AHB2LOCK_Msk           /*!< Locked protection of AHB2 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB3LOCK_Pos              (5U)
+#define RCC_LOCKCFGR4_AHB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */
+#define RCC_LOCKCFGR4_AHB3LOCK                  RCC_LOCKCFGR4_AHB3LOCK_Msk           /*!< Locked protection of AHB3 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB4LOCK_Pos              (6U)
+#define RCC_LOCKCFGR4_AHB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */
+#define RCC_LOCKCFGR4_AHB4LOCK                  RCC_LOCKCFGR4_AHB4LOCK_Msk           /*!< Locked protection of AHB4 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB5LOCK_Pos              (7U)
+#define RCC_LOCKCFGR4_AHB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */
+#define RCC_LOCKCFGR4_AHB5LOCK                  RCC_LOCKCFGR4_AHB5LOCK_Msk           /*!< Locked protection of AHB5 bus configuration bits */
+#define RCC_LOCKCFGR4_APB1LOCK_Pos              (8U)
+#define RCC_LOCKCFGR4_APB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */
+#define RCC_LOCKCFGR4_APB1LOCK                  RCC_LOCKCFGR4_APB1LOCK_Msk           /*!< Locked protection of APB1 bus configuration bits */
+#define RCC_LOCKCFGR4_APB2LOCK_Pos              (9U)
+#define RCC_LOCKCFGR4_APB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR4_APB2LOCK                  RCC_LOCKCFGR4_APB2LOCK_Msk           /*!< Locked protection of APB2 bus configuration bits */
+#define RCC_LOCKCFGR4_APB3LOCK_Pos              (10U)
+#define RCC_LOCKCFGR4_APB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR4_APB3LOCK                  RCC_LOCKCFGR4_APB3LOCK_Msk           /*!< Locked protection of APB3 bus configuration bits */
+#define RCC_LOCKCFGR4_APB4LOCK_Pos              (11U)
+#define RCC_LOCKCFGR4_APB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR4_APB4LOCK                  RCC_LOCKCFGR4_APB4LOCK_Msk           /*!< Locked protection of APB4 bus configuration bits */
+#define RCC_LOCKCFGR4_APB5LOCK_Pos              (12U)
+#define RCC_LOCKCFGR4_APB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR4_APB5LOCK                  RCC_LOCKCFGR4_APB5LOCK_Msk           /*!< Locked protection of APB5 bus configuration bits */
+#define RCC_LOCKCFGR4_NOCLOCK_Pos               (13U)
+#define RCC_LOCKCFGR4_NOCLOCK_Msk               (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos)  /*!< 0x00002000 */
+#define RCC_LOCKCFGR4_NOCLOCK                   RCC_LOCKCFGR4_NOCLOCK_Msk            /*!< Locked protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR4 register  *****************/
+#define RCC_PUBCFGR4_ACLKNPUB_Pos               (0U)
+#define RCC_PUBCFGR4_ACLKNPUB_Msk               (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGR4_ACLKNPUB                   RCC_PUBCFGR4_ACLKNPUB_Msk            /*!< Public protection of the ACLKN bus configuration bits */
+#define RCC_PUBCFGR4_ACLKNCPUB_Pos              (1U)
+#define RCC_PUBCFGR4_ACLKNCPUB_Msk              (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR4_ACLKNCPUB                  RCC_PUBCFGR4_ACLKNCPUB_Msk           /*!< Public protection of ACLKNC bus configuration bits */
+#define RCC_PUBCFGR4_AHBMPUB_Pos                (2U)
+#define RCC_PUBCFGR4_AHBMPUB_Msk                (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR4_AHBMPUB                    RCC_PUBCFGR4_AHBMPUB_Msk             /*!< Public protection of AHBM bus configuration bits */
+#define RCC_PUBCFGR4_AHB1PUB_Pos                (3U)
+#define RCC_PUBCFGR4_AHB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR4_AHB1PUB                    RCC_PUBCFGR4_AHB1PUB_Msk             /*!< Public protection of AHB1 bus configuration bits */
+#define RCC_PUBCFGR4_AHB2PUB_Pos                (4U)
+#define RCC_PUBCFGR4_AHB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGR4_AHB2PUB                    RCC_PUBCFGR4_AHB2PUB_Msk             /*!< Public protection of AHB2 bus configuration bits */
+#define RCC_PUBCFGR4_AHB3PUB_Pos                (5U)
+#define RCC_PUBCFGR4_AHB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGR4_AHB3PUB                    RCC_PUBCFGR4_AHB3PUB_Msk             /*!< Public protection of AHB3 bus configuration bits */
+#define RCC_PUBCFGR4_AHB4PUB_Pos                (6U)
+#define RCC_PUBCFGR4_AHB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos)   /*!< 0x00000040 */
+#define RCC_PUBCFGR4_AHB4PUB                    RCC_PUBCFGR4_AHB4PUB_Msk             /*!< Public protection of AHB4 bus configuration bits */
+#define RCC_PUBCFGR4_AHB5PUB_Pos                (7U)
+#define RCC_PUBCFGR4_AHB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGR4_AHB5PUB                    RCC_PUBCFGR4_AHB5PUB_Msk             /*!< Public protection of AHB5 bus configuration bits */
+#define RCC_PUBCFGR4_APB1PUB_Pos                (8U)
+#define RCC_PUBCFGR4_APB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGR4_APB1PUB                    RCC_PUBCFGR4_APB1PUB_Msk             /*!< Public protection of APB1 bus configuration bits */
+#define RCC_PUBCFGR4_APB2PUB_Pos                (9U)
+#define RCC_PUBCFGR4_APB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR4_APB2PUB                    RCC_PUBCFGR4_APB2PUB_Msk             /*!< Public protection of APB2 bus configuration bits */
+#define RCC_PUBCFGR4_APB3PUB_Pos                (10U)
+#define RCC_PUBCFGR4_APB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR4_APB3PUB                    RCC_PUBCFGR4_APB3PUB_Msk             /*!< Public protection of APB3 bus configuration bits */
+#define RCC_PUBCFGR4_APB4PUB_Pos                (11U)
+#define RCC_PUBCFGR4_APB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR4_APB4PUB                    RCC_PUBCFGR4_APB4PUB_Msk             /*!< Public protection of APB4 bus configuration bits */
+#define RCC_PUBCFGR4_APB5PUB_Pos                (12U)
+#define RCC_PUBCFGR4_APB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR4_APB5PUB                    RCC_PUBCFGR4_APB5PUB_Msk             /*!< Public protection of APB5 bus configuration bits */
+#define RCC_PUBCFGR4_NOCPUB_Pos                 (13U)
+#define RCC_PUBCFGR4_NOCPUB_Msk                 (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos)    /*!< 0x00002000 */
+#define RCC_PUBCFGR4_NOCPUB                     RCC_PUBCFGR4_NOCPUB_Msk              /*!< Public protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR5 register  *****************/
+#define RCC_PUBCFGR5_AXISRAM3PUB_Pos            (0U)
+#define RCC_PUBCFGR5_AXISRAM3PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGR5_AXISRAM3PUB                RCC_PUBCFGR5_AXISRAM3PUB_Msk         /*!< Public protection of AXISRAM3 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM4PUB_Pos            (1U)
+#define RCC_PUBCFGR5_AXISRAM4PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR5_AXISRAM4PUB                RCC_PUBCFGR5_AXISRAM4PUB_Msk         /*!< Public protection of AXISRAM4 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM5PUB_Pos            (2U)
+#define RCC_PUBCFGR5_AXISRAM5PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGR5_AXISRAM5PUB                RCC_PUBCFGR5_AXISRAM5PUB_Msk         /*!< Public protection of AXISRAM5 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM6PUB_Pos            (3U)
+#define RCC_PUBCFGR5_AXISRAM6PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGR5_AXISRAM6PUB                RCC_PUBCFGR5_AXISRAM6PUB_Msk         /*!< Public protection of AXISRAM6 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos            (4U)
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGR5_AHBSRAM1PUB                RCC_PUBCFGR5_AHBSRAM1PUB_Msk         /*!< Public protection of AHBSRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos            (5U)
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGR5_AHBSRAM2PUB                RCC_PUBCFGR5_AHBSRAM2PUB_Msk         /*!< Public protection of AHBSRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_BKPSRAMPUB_Pos             (6U)
+#define RCC_PUBCFGR5_BKPSRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */
+#define RCC_PUBCFGR5_BKPSRAMPUB                 RCC_PUBCFGR5_BKPSRAMPUB_Msk          /*!< Public protection of BKPSRAM bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM1PUB_Pos            (7U)
+#define RCC_PUBCFGR5_AXISRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGR5_AXISRAM1PUB                RCC_PUBCFGR5_AXISRAM1PUB_Msk         /*!< Public protection of AXISRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM2PUB_Pos            (8U)
+#define RCC_PUBCFGR5_AXISRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGR5_AXISRAM2PUB                RCC_PUBCFGR5_AXISRAM2PUB_Msk         /*!< Public protection of AXISRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_FLEXRAMPUB_Pos             (9U)
+#define RCC_PUBCFGR5_FLEXRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */
+#define RCC_PUBCFGR5_FLEXRAMPUB                 RCC_PUBCFGR5_FLEXRAMPUB_Msk          /*!< Public protection of FLEXRAM bus configuration bits */
+#define RCC_PUBCFGR5_VENCRAMPUB_Pos             (11U)
+#define RCC_PUBCFGR5_VENCRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */
+#define RCC_PUBCFGR5_VENCRAMPUB                 RCC_PUBCFGR5_VENCRAMPUB_Msk          /*!< Public protection of VENCRAM bus configuration bits */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define RCC_CSR_LSIONS_Pos                      (0U)
+#define RCC_CSR_LSIONS_Msk                      (0x1UL << RCC_CSR_LSIONS_Pos)         /*!< 0x00000001 */
+#define RCC_CSR_LSIONS                          RCC_CSR_LSIONS_Msk                   /*!< LSI oscillator enable */
+#define RCC_CSR_LSEONS_Pos                      (1U)
+#define RCC_CSR_LSEONS_Msk                      (0x1UL << RCC_CSR_LSEONS_Pos)         /*!< 0x00000002 */
+#define RCC_CSR_LSEONS                          RCC_CSR_LSEONS_Msk                   /*!< LSE oscillator enable */
+#define RCC_CSR_MSIONS_Pos                      (2U)
+#define RCC_CSR_MSIONS_Msk                      (0x1UL << RCC_CSR_MSIONS_Pos)         /*!< 0x00000004 */
+#define RCC_CSR_MSIONS                          RCC_CSR_MSIONS_Msk                   /*!< MSI oscillator enable */
+#define RCC_CSR_HSIONS_Pos                      (3U)
+#define RCC_CSR_HSIONS_Msk                      (0x1UL << RCC_CSR_HSIONS_Pos)         /*!< 0x00000008 */
+#define RCC_CSR_HSIONS                          RCC_CSR_HSIONS_Msk                   /*!< HSI oscillator enable */
+#define RCC_CSR_HSEONS_Pos                      (4U)
+#define RCC_CSR_HSEONS_Msk                      (0x1UL << RCC_CSR_HSEONS_Pos)         /*!< 0x00000010 */
+#define RCC_CSR_HSEONS                          RCC_CSR_HSEONS_Msk                   /*!< HSE oscillator enable */
+#define RCC_CSR_PLL1ONS_Pos                     (8U)
+#define RCC_CSR_PLL1ONS_Msk                     (0x1UL << RCC_CSR_PLL1ONS_Pos)        /*!< 0x00000100 */
+#define RCC_CSR_PLL1ONS                         RCC_CSR_PLL1ONS_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CSR_PLL2ONS_Pos                     (9U)
+#define RCC_CSR_PLL2ONS_Msk                     (0x1UL << RCC_CSR_PLL2ONS_Pos)        /*!< 0x00000200 */
+#define RCC_CSR_PLL2ONS                         RCC_CSR_PLL2ONS_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CSR_PLL3ONS_Pos                     (10U)
+#define RCC_CSR_PLL3ONS_Msk                     (0x1UL << RCC_CSR_PLL3ONS_Pos)        /*!< 0x00000400 */
+#define RCC_CSR_PLL3ONS                         RCC_CSR_PLL3ONS_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CSR_PLL4ONS_Pos                     (11U)
+#define RCC_CSR_PLL4ONS_Msk                     (0x1UL << RCC_CSR_PLL4ONS_Pos)        /*!< 0x00000800 */
+#define RCC_CSR_PLL4ONS                         RCC_CSR_PLL4ONS_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCSR register  ******************/
+#define RCC_STOPCSR_MSISTOPENS_Pos              (0U)
+#define RCC_STOPCSR_MSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */
+#define RCC_STOPCSR_MSISTOPENS                  RCC_STOPCSR_MSISTOPENS_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCSR_HSISTOPENS_Pos              (1U)
+#define RCC_STOPCSR_HSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */
+#define RCC_STOPCSR_HSISTOPENS                  RCC_STOPCSR_HSISTOPENS_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTSR register  *****************/
+#define RCC_MISCRSTSR_DBGRSTS_Pos               (0U)
+#define RCC_MISCRSTSR_DBGRSTS_Msk               (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTSR_DBGRSTS                   RCC_MISCRSTSR_DBGRSTS_Msk            /*!< DBG reset */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos          (4U)
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS              RCC_MISCRSTSR_XSPIPHY1RSTS_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos          (5U)
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS              RCC_MISCRSTSR_XSPIPHY2RSTS_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos         (7U)
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS             RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos         (8U)
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS             RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTSR register  *****************/
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos           (0U)
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTSR_AXISRAM3RSTS               RCC_MEMRSTSR_AXISRAM3RSTS_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos           (1U)
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTSR_AXISRAM4RSTS               RCC_MEMRSTSR_AXISRAM4RSTS_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos           (2U)
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTSR_AXISRAM5RSTS               RCC_MEMRSTSR_AXISRAM5RSTS_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos           (3U)
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTSR_AXISRAM6RSTS               RCC_MEMRSTSR_AXISRAM6RSTS_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos           (4U)
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS               RCC_MEMRSTSR_AHBSRAM1RSTS_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos           (5U)
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS               RCC_MEMRSTSR_AHBSRAM2RSTS_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos           (7U)
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTSR_AXISRAM1RSTS               RCC_MEMRSTSR_AXISRAM1RSTS_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos           (8U)
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTSR_AXISRAM2RSTS               RCC_MEMRSTSR_AXISRAM2RSTS_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos            (9U)
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTSR_FLEXRAMRSTS                RCC_MEMRSTSR_FLEXRAMRSTS_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTSR_VENCRAMRSTS_Pos            (11U)
+#define RCC_MEMRSTSR_VENCRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTSR_VENCRAMRSTS                RCC_MEMRSTSR_VENCRAMRSTS_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTSR_BOOTROMRSTS_Pos            (12U)
+#define RCC_MEMRSTSR_BOOTROMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTSR_BOOTROMRSTS                RCC_MEMRSTSR_BOOTROMRSTS_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTSR register  *****************/
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos            (4U)
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk            (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTSR_GPDMA1RSTS                RCC_AHB1RSTSR_GPDMA1RSTS_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTSR_ADC12RSTS_Pos             (5U)
+#define RCC_AHB1RSTSR_ADC12RSTS_Msk             (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTSR_ADC12RSTS                 RCC_AHB1RSTSR_ADC12RSTS_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTSR register  *****************/
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos            (12U)
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk            (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTSR_RAMCFGRSTS                RCC_AHB2RSTSR_RAMCFGRSTS_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTSR_MDF1RSTS_Pos              (16U)
+#define RCC_AHB2RSTSR_MDF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTSR_MDF1RSTS                  RCC_AHB2RSTSR_MDF1RSTS_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTSR_ADF1RSTS_Pos              (17U)
+#define RCC_AHB2RSTSR_ADF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTSR_ADF1RSTS                  RCC_AHB2RSTSR_ADF1RSTS_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTSR register  *****************/
+#define RCC_AHB3RSTSR_RNGRSTS_Pos               (0U)
+#define RCC_AHB3RSTSR_RNGRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTSR_RNGRSTS                   RCC_AHB3RSTSR_RNGRSTS_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTSR_HASHRSTS_Pos              (1U)
+#define RCC_AHB3RSTSR_HASHRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTSR_HASHRSTS                  RCC_AHB3RSTSR_HASHRSTS_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTSR_CRYPRSTS_Pos              (2U)
+#define RCC_AHB3RSTSR_CRYPRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_AHB3RSTSR_CRYPRSTS                  RCC_AHB3RSTSR_CRYPRSTS_Msk           /*!< CRYP reset */
+#define RCC_AHB3RSTSR_SAESRSTS_Pos              (4U)
+#define RCC_AHB3RSTSR_SAESRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */
+#define RCC_AHB3RSTSR_SAESRSTS                  RCC_AHB3RSTSR_SAESRSTS_Msk           /*!< SAES reset */
+#define RCC_AHB3RSTSR_PKARSTS_Pos               (8U)
+#define RCC_AHB3RSTSR_PKARSTS_Msk               (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTSR_PKARSTS                   RCC_AHB3RSTSR_PKARSTS_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTSR_IACRSTS_Pos               (10U)
+#define RCC_AHB3RSTSR_IACRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTSR_IACRSTS                   RCC_AHB3RSTSR_IACRSTS_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTSR register  *****************/
+#define RCC_AHB4RSTSR_GPIOARSTS_Pos             (0U)
+#define RCC_AHB4RSTSR_GPIOARSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTSR_GPIOARSTS                 RCC_AHB4RSTSR_GPIOARSTS_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTSR_GPIOBRSTS_Pos             (1U)
+#define RCC_AHB4RSTSR_GPIOBRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTSR_GPIOBRSTS                 RCC_AHB4RSTSR_GPIOBRSTS_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTSR_GPIOCRSTS_Pos             (2U)
+#define RCC_AHB4RSTSR_GPIOCRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTSR_GPIOCRSTS                 RCC_AHB4RSTSR_GPIOCRSTS_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTSR_GPIODRSTS_Pos             (3U)
+#define RCC_AHB4RSTSR_GPIODRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTSR_GPIODRSTS                 RCC_AHB4RSTSR_GPIODRSTS_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTSR_GPIOERSTS_Pos             (4U)
+#define RCC_AHB4RSTSR_GPIOERSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTSR_GPIOERSTS                 RCC_AHB4RSTSR_GPIOERSTS_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTSR_GPIOFRSTS_Pos             (5U)
+#define RCC_AHB4RSTSR_GPIOFRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTSR_GPIOFRSTS                 RCC_AHB4RSTSR_GPIOFRSTS_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTSR_GPIOGRSTS_Pos             (6U)
+#define RCC_AHB4RSTSR_GPIOGRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTSR_GPIOGRSTS                 RCC_AHB4RSTSR_GPIOGRSTS_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTSR_GPIOHRSTS_Pos             (7U)
+#define RCC_AHB4RSTSR_GPIOHRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTSR_GPIOHRSTS                 RCC_AHB4RSTSR_GPIOHRSTS_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTSR_GPIONRSTS_Pos             (13U)
+#define RCC_AHB4RSTSR_GPIONRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTSR_GPIONRSTS                 RCC_AHB4RSTSR_GPIONRSTS_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTSR_GPIOORSTS_Pos             (14U)
+#define RCC_AHB4RSTSR_GPIOORSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTSR_GPIOORSTS                 RCC_AHB4RSTSR_GPIOORSTS_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTSR_GPIOPRSTS_Pos             (15U)
+#define RCC_AHB4RSTSR_GPIOPRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTSR_GPIOPRSTS                 RCC_AHB4RSTSR_GPIOPRSTS_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTSR_GPIOQRSTS_Pos             (16U)
+#define RCC_AHB4RSTSR_GPIOQRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTSR_GPIOQRSTS                 RCC_AHB4RSTSR_GPIOQRSTS_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTSR_PWRRSTS_Pos               (18U)
+#define RCC_AHB4RSTSR_PWRRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTSR_PWRRSTS                   RCC_AHB4RSTSR_PWRRSTS_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTSR_CRCRSTS_Pos               (19U)
+#define RCC_AHB4RSTSR_CRCRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTSR_CRCRSTS                   RCC_AHB4RSTSR_CRCRSTS_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTSR register  *****************/
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos            (0U)
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTSR_HPDMA1RSTS                RCC_AHB5RSTSR_HPDMA1RSTS_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTSR_DMA2DRSTS_Pos             (1U)
+#define RCC_AHB5RSTSR_DMA2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTSR_DMA2DRSTS                 RCC_AHB5RSTSR_DMA2DRSTS_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTSR_JPEGRSTS_Pos              (3U)
+#define RCC_AHB5RSTSR_JPEGRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTSR_JPEGRSTS                  RCC_AHB5RSTSR_JPEGRSTS_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTSR_FMCRSTS_Pos               (4U)
+#define RCC_AHB5RSTSR_FMCRSTS_Msk               (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTSR_FMCRSTS                   RCC_AHB5RSTSR_FMCRSTS_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTSR_XSPI1RSTS_Pos             (5U)
+#define RCC_AHB5RSTSR_XSPI1RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTSR_XSPI1RSTS                 RCC_AHB5RSTSR_XSPI1RSTS_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTSR_PSSIRSTS_Pos              (6U)
+#define RCC_AHB5RSTSR_PSSIRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTSR_PSSIRSTS                  RCC_AHB5RSTSR_PSSIRSTS_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos            (7U)
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTSR_SDMMC2RSTS                RCC_AHB5RSTSR_SDMMC2RSTS_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos            (8U)
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTSR_SDMMC1RSTS                RCC_AHB5RSTSR_SDMMC1RSTS_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTSR_XSPI2RSTS_Pos             (12U)
+#define RCC_AHB5RSTSR_XSPI2RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTSR_XSPI2RSTS                 RCC_AHB5RSTSR_XSPI2RSTS_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTSR_XSPIMRSTS_Pos             (13U)
+#define RCC_AHB5RSTSR_XSPIMRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTSR_XSPIMRSTS                 RCC_AHB5RSTSR_XSPIMRSTS_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTSR_XSPI3RSTS_Pos             (17U)
+#define RCC_AHB5RSTSR_XSPI3RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTSR_XSPI3RSTS                 RCC_AHB5RSTSR_XSPI3RSTS_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTSR_GFXMMURSTS_Pos            (19U)
+#define RCC_AHB5RSTSR_GFXMMURSTS_Msk            (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTSR_GFXMMURSTS                RCC_AHB5RSTSR_GFXMMURSTS_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTSR_GPU2DRSTS_Pos             (20U)
+#define RCC_AHB5RSTSR_GPU2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTSR_GPU2DRSTS                 RCC_AHB5RSTSR_GPU2DRSTS_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos        (23U)
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS            RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos        (24U)
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS            RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTSR_ETH1RSTS_Pos              (25U)
+#define RCC_AHB5RSTSR_ETH1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTSR_ETH1RSTS                  RCC_AHB5RSTSR_ETH1RSTS_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTSR_OTG1RSTS_Pos              (26U)
+#define RCC_AHB5RSTSR_OTG1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTSR_OTG1RSTS                  RCC_AHB5RSTSR_OTG1RSTS_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos           (27U)
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS               RCC_AHB5RSTSR_OTGPHY1RSTS_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos           (28U)
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS               RCC_AHB5RSTSR_OTGPHY2RSTS_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTSR_OTG2RSTS_Pos              (29U)
+#define RCC_AHB5RSTSR_OTG2RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTSR_OTG2RSTS                  RCC_AHB5RSTSR_OTG2RSTS_Msk           /*!< OTG2 reset */
+
+/****************  Bit definition for RCC_APB1RSTSR1 register  ****************/
+#define RCC_APB1RSTSR1_TIM2RSTS_Pos             (0U)
+#define RCC_APB1RSTSR1_TIM2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTSR1_TIM2RSTS                 RCC_APB1RSTSR1_TIM2RSTS_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTSR1_TIM3RSTS_Pos             (1U)
+#define RCC_APB1RSTSR1_TIM3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTSR1_TIM3RSTS                 RCC_APB1RSTSR1_TIM3RSTS_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTSR1_TIM4RSTS_Pos             (2U)
+#define RCC_APB1RSTSR1_TIM4RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTSR1_TIM4RSTS                 RCC_APB1RSTSR1_TIM4RSTS_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTSR1_TIM5RSTS_Pos             (3U)
+#define RCC_APB1RSTSR1_TIM5RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTSR1_TIM5RSTS                 RCC_APB1RSTSR1_TIM5RSTS_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTSR1_TIM6RSTS_Pos             (4U)
+#define RCC_APB1RSTSR1_TIM6RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTSR1_TIM6RSTS                 RCC_APB1RSTSR1_TIM6RSTS_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTSR1_TIM7RSTS_Pos             (5U)
+#define RCC_APB1RSTSR1_TIM7RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTSR1_TIM7RSTS                 RCC_APB1RSTSR1_TIM7RSTS_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTSR1_TIM12RSTS_Pos            (6U)
+#define RCC_APB1RSTSR1_TIM12RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTSR1_TIM12RSTS                RCC_APB1RSTSR1_TIM12RSTS_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTSR1_TIM13RSTS_Pos            (7U)
+#define RCC_APB1RSTSR1_TIM13RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTSR1_TIM13RSTS                RCC_APB1RSTSR1_TIM13RSTS_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTSR1_TIM14RSTS_Pos            (8U)
+#define RCC_APB1RSTSR1_TIM14RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR1_TIM14RSTS                RCC_APB1RSTSR1_TIM14RSTS_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos           (9U)
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTSR1_LPTIM1RSTS               RCC_APB1RSTSR1_LPTIM1RSTS_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTSR1_WWDGRSTS_Pos             (11U)
+#define RCC_APB1RSTSR1_WWDGRSTS_Msk             (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTSR1_WWDGRSTS                 RCC_APB1RSTSR1_WWDGRSTS_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTSR1_TIM10RSTS_Pos            (12U)
+#define RCC_APB1RSTSR1_TIM10RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTSR1_TIM10RSTS                RCC_APB1RSTSR1_TIM10RSTS_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTSR1_TIM11RSTS_Pos            (13U)
+#define RCC_APB1RSTSR1_TIM11RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTSR1_TIM11RSTS                RCC_APB1RSTSR1_TIM11RSTS_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTSR1_SPI2RSTS_Pos             (14U)
+#define RCC_APB1RSTSR1_SPI2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTSR1_SPI2RSTS                 RCC_APB1RSTSR1_SPI2RSTS_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTSR1_SPI3RSTS_Pos             (15U)
+#define RCC_APB1RSTSR1_SPI3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTSR1_SPI3RSTS                 RCC_APB1RSTSR1_SPI3RSTS_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos         (16U)
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk         (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS             RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTSR1_USART2RSTS_Pos           (17U)
+#define RCC_APB1RSTSR1_USART2RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTSR1_USART2RSTS               RCC_APB1RSTSR1_USART2RSTS_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTSR1_USART3RSTS_Pos           (18U)
+#define RCC_APB1RSTSR1_USART3RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTSR1_USART3RSTS               RCC_APB1RSTSR1_USART3RSTS_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTSR1_UART4RSTS_Pos            (19U)
+#define RCC_APB1RSTSR1_UART4RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTSR1_UART4RSTS                RCC_APB1RSTSR1_UART4RSTS_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTSR1_UART5RSTS_Pos            (20U)
+#define RCC_APB1RSTSR1_UART5RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTSR1_UART5RSTS                RCC_APB1RSTSR1_UART5RSTS_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTSR1_I2C1RSTS_Pos             (21U)
+#define RCC_APB1RSTSR1_I2C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTSR1_I2C1RSTS                 RCC_APB1RSTSR1_I2C1RSTS_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTSR1_I2C2RSTS_Pos             (22U)
+#define RCC_APB1RSTSR1_I2C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTSR1_I2C2RSTS                 RCC_APB1RSTSR1_I2C2RSTS_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTSR1_I2C3RSTS_Pos             (23U)
+#define RCC_APB1RSTSR1_I2C3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTSR1_I2C3RSTS                 RCC_APB1RSTSR1_I2C3RSTS_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTSR1_I3C1RSTS_Pos             (24U)
+#define RCC_APB1RSTSR1_I3C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTSR1_I3C1RSTS                 RCC_APB1RSTSR1_I3C1RSTS_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTSR1_I3C2RSTS_Pos             (25U)
+#define RCC_APB1RSTSR1_I3C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTSR1_I3C2RSTS                 RCC_APB1RSTSR1_I3C2RSTS_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTSR1_UART7RSTS_Pos            (30U)
+#define RCC_APB1RSTSR1_UART7RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTSR1_UART7RSTS                RCC_APB1RSTSR1_UART7RSTS_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTSR1_UART8RSTS_Pos            (31U)
+#define RCC_APB1RSTSR1_UART8RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTSR1_UART8RSTS                RCC_APB1RSTSR1_UART8RSTS_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTSR2 register  ****************/
+#define RCC_APB1RSTSR2_MDIOSRSTS_Pos            (5U)
+#define RCC_APB1RSTSR2_MDIOSRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTSR2_MDIOSRSTS                RCC_APB1RSTSR2_MDIOSRSTS_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTSR2_FDCANRSTS_Pos            (8U)
+#define RCC_APB1RSTSR2_FDCANRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR2_FDCANRSTS                RCC_APB1RSTSR2_FDCANRSTS_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTSR2_UCPD1RSTS_Pos            (18U)
+#define RCC_APB1RSTSR2_UCPD1RSTS_Msk            (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTSR2_UCPD1RSTS                RCC_APB1RSTSR2_UCPD1RSTS_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTSR register  *****************/
+#define RCC_APB2RSTSR_TIM1RSTS_Pos              (0U)
+#define RCC_APB2RSTSR_TIM1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTSR_TIM1RSTS                  RCC_APB2RSTSR_TIM1RSTS_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTSR_TIM8RSTS_Pos              (1U)
+#define RCC_APB2RSTSR_TIM8RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTSR_TIM8RSTS                  RCC_APB2RSTSR_TIM8RSTS_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTSR_USART1RSTS_Pos            (4U)
+#define RCC_APB2RSTSR_USART1RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTSR_USART1RSTS                RCC_APB2RSTSR_USART1RSTS_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTSR_USART6RSTS_Pos            (5U)
+#define RCC_APB2RSTSR_USART6RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTSR_USART6RSTS                RCC_APB2RSTSR_USART6RSTS_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTSR_UART9RSTS_Pos             (6U)
+#define RCC_APB2RSTSR_UART9RSTS_Msk             (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTSR_UART9RSTS                 RCC_APB2RSTSR_UART9RSTS_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTSR_USART10RSTS_Pos           (7U)
+#define RCC_APB2RSTSR_USART10RSTS_Msk           (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTSR_USART10RSTS               RCC_APB2RSTSR_USART10RSTS_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTSR_SPI1RSTS_Pos              (12U)
+#define RCC_APB2RSTSR_SPI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTSR_SPI1RSTS                  RCC_APB2RSTSR_SPI1RSTS_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTSR_SPI4RSTS_Pos              (13U)
+#define RCC_APB2RSTSR_SPI4RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTSR_SPI4RSTS                  RCC_APB2RSTSR_SPI4RSTS_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTSR_TIM18RSTS_Pos             (15U)
+#define RCC_APB2RSTSR_TIM18RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTSR_TIM18RSTS                 RCC_APB2RSTSR_TIM18RSTS_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTSR_TIM15RSTS_Pos             (16U)
+#define RCC_APB2RSTSR_TIM15RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTSR_TIM15RSTS                 RCC_APB2RSTSR_TIM15RSTS_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTSR_TIM16RSTS_Pos             (17U)
+#define RCC_APB2RSTSR_TIM16RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTSR_TIM16RSTS                 RCC_APB2RSTSR_TIM16RSTS_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTSR_TIM17RSTS_Pos             (18U)
+#define RCC_APB2RSTSR_TIM17RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTSR_TIM17RSTS                 RCC_APB2RSTSR_TIM17RSTS_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTSR_TIM9RSTS_Pos              (19U)
+#define RCC_APB2RSTSR_TIM9RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTSR_TIM9RSTS                  RCC_APB2RSTSR_TIM9RSTS_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTSR_SPI5RSTS_Pos              (20U)
+#define RCC_APB2RSTSR_SPI5RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTSR_SPI5RSTS                  RCC_APB2RSTSR_SPI5RSTS_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTSR_SAI1RSTS_Pos              (21U)
+#define RCC_APB2RSTSR_SAI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTSR_SAI1RSTS                  RCC_APB2RSTSR_SAI1RSTS_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTSR_SAI2RSTS_Pos              (22U)
+#define RCC_APB2RSTSR_SAI2RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTSR_SAI2RSTS                  RCC_APB2RSTSR_SAI2RSTS_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTSR1 register  ****************/
+#define RCC_APB4RSTSR1_HDPRSTS_Pos              (2U)
+#define RCC_APB4RSTSR1_HDPRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR1_HDPRSTS                  RCC_APB4RSTSR1_HDPRSTS_Msk           /*!< HDP reset */
+#define RCC_APB4RSTSR1_LPUART1RSTS_Pos          (3U)
+#define RCC_APB4RSTSR1_LPUART1RSTS_Msk          (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTSR1_LPUART1RSTS              RCC_APB4RSTSR1_LPUART1RSTS_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTSR1_SPI6RSTS_Pos             (5U)
+#define RCC_APB4RSTSR1_SPI6RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTSR1_SPI6RSTS                 RCC_APB4RSTSR1_SPI6RSTS_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTSR1_I2C4RSTS_Pos             (7U)
+#define RCC_APB4RSTSR1_I2C4RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTSR1_I2C4RSTS                 RCC_APB4RSTSR1_I2C4RSTS_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos           (9U)
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTSR1_LPTIM2RSTS               RCC_APB4RSTSR1_LPTIM2RSTS_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos           (10U)
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTSR1_LPTIM3RSTS               RCC_APB4RSTSR1_LPTIM3RSTS_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos           (11U)
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTSR1_LPTIM4RSTS               RCC_APB4RSTSR1_LPTIM4RSTS_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos           (12U)
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTSR1_LPTIM5RSTS               RCC_APB4RSTSR1_LPTIM5RSTS_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos          (15U)
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk          (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTSR1_VREFBUFRSTS              RCC_APB4RSTSR1_VREFBUFRSTS_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTSR1_RTCRSTS_Pos              (16U)
+#define RCC_APB4RSTSR1_RTCRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTSR1_RTCRSTS                  RCC_APB4RSTSR1_RTCRSTS_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTSR2 register  ****************/
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos           (0U)
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk           (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTSR2_SYSCFGRSTS               RCC_APB4RSTSR2_SYSCFGRSTS_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTSR2_DTSRSTS_Pos              (2U)
+#define RCC_APB4RSTSR2_DTSRSTS_Msk              (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR2_DTSRSTS                  RCC_APB4RSTSR2_DTSRSTS_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTSR register  *****************/
+#define RCC_APB5RSTSR_LTDCRSTS_Pos              (1U)
+#define RCC_APB5RSTSR_LTDCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTSR_LTDCRSTS                  RCC_APB5RSTSR_LTDCRSTS_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTSR_DCMIPPRSTS_Pos            (2U)
+#define RCC_APB5RSTSR_DCMIPPRSTS_Msk            (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTSR_DCMIPPRSTS                RCC_APB5RSTSR_DCMIPPRSTS_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTSR_GFXTIMRSTS_Pos            (4U)
+#define RCC_APB5RSTSR_GFXTIMRSTS_Msk            (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTSR_GFXTIMRSTS                RCC_APB5RSTSR_GFXTIMRSTS_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTSR_VENCRSTS_Pos              (5U)
+#define RCC_APB5RSTSR_VENCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTSR_VENCRSTS                  RCC_APB5RSTSR_VENCRSTS_Msk           /*!< VENC reset */
+#define RCC_APB5RSTSR_CSIRSTS_Pos               (6U)
+#define RCC_APB5RSTSR_CSIRSTS_Msk               (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTSR_CSIRSTS                   RCC_APB5RSTSR_CSIRSTS_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENSR register  ******************/
+#define RCC_DIVENSR_IC1ENS_Pos                  (0U)
+#define RCC_DIVENSR_IC1ENS_Msk                  (0x1UL << RCC_DIVENSR_IC1ENS_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENSR_IC1ENS                      RCC_DIVENSR_IC1ENS_Msk               /*!< IC1 enable */
+#define RCC_DIVENSR_IC2ENS_Pos                  (1U)
+#define RCC_DIVENSR_IC2ENS_Msk                  (0x1UL << RCC_DIVENSR_IC2ENS_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENSR_IC2ENS                      RCC_DIVENSR_IC2ENS_Msk               /*!< IC2 enable */
+#define RCC_DIVENSR_IC3ENS_Pos                  (2U)
+#define RCC_DIVENSR_IC3ENS_Msk                  (0x1UL << RCC_DIVENSR_IC3ENS_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENSR_IC3ENS                      RCC_DIVENSR_IC3ENS_Msk               /*!< IC3 enable */
+#define RCC_DIVENSR_IC4ENS_Pos                  (3U)
+#define RCC_DIVENSR_IC4ENS_Msk                  (0x1UL << RCC_DIVENSR_IC4ENS_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENSR_IC4ENS                      RCC_DIVENSR_IC4ENS_Msk               /*!< IC4 enable */
+#define RCC_DIVENSR_IC5ENS_Pos                  (4U)
+#define RCC_DIVENSR_IC5ENS_Msk                  (0x1UL << RCC_DIVENSR_IC5ENS_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENSR_IC5ENS                      RCC_DIVENSR_IC5ENS_Msk               /*!< IC5 enable */
+#define RCC_DIVENSR_IC6ENS_Pos                  (5U)
+#define RCC_DIVENSR_IC6ENS_Msk                  (0x1UL << RCC_DIVENSR_IC6ENS_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENSR_IC6ENS                      RCC_DIVENSR_IC6ENS_Msk               /*!< IC6 enable */
+#define RCC_DIVENSR_IC7ENS_Pos                  (6U)
+#define RCC_DIVENSR_IC7ENS_Msk                  (0x1UL << RCC_DIVENSR_IC7ENS_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENSR_IC7ENS                      RCC_DIVENSR_IC7ENS_Msk               /*!< IC7 enable */
+#define RCC_DIVENSR_IC8ENS_Pos                  (7U)
+#define RCC_DIVENSR_IC8ENS_Msk                  (0x1UL << RCC_DIVENSR_IC8ENS_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENSR_IC8ENS                      RCC_DIVENSR_IC8ENS_Msk               /*!< IC8 enable */
+#define RCC_DIVENSR_IC9ENS_Pos                  (8U)
+#define RCC_DIVENSR_IC9ENS_Msk                  (0x1UL << RCC_DIVENSR_IC9ENS_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENSR_IC9ENS                      RCC_DIVENSR_IC9ENS_Msk               /*!< IC9 enable */
+#define RCC_DIVENSR_IC10ENS_Pos                 (9U)
+#define RCC_DIVENSR_IC10ENS_Msk                 (0x1UL << RCC_DIVENSR_IC10ENS_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENSR_IC10ENS                     RCC_DIVENSR_IC10ENS_Msk              /*!< IC10 enable */
+#define RCC_DIVENSR_IC11ENS_Pos                 (10U)
+#define RCC_DIVENSR_IC11ENS_Msk                 (0x1UL << RCC_DIVENSR_IC11ENS_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENSR_IC11ENS                     RCC_DIVENSR_IC11ENS_Msk              /*!< IC11 enable */
+#define RCC_DIVENSR_IC12ENS_Pos                 (11U)
+#define RCC_DIVENSR_IC12ENS_Msk                 (0x1UL << RCC_DIVENSR_IC12ENS_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENSR_IC12ENS                     RCC_DIVENSR_IC12ENS_Msk              /*!< IC12 enable */
+#define RCC_DIVENSR_IC13ENS_Pos                 (12U)
+#define RCC_DIVENSR_IC13ENS_Msk                 (0x1UL << RCC_DIVENSR_IC13ENS_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENSR_IC13ENS                     RCC_DIVENSR_IC13ENS_Msk              /*!< IC13 enable */
+#define RCC_DIVENSR_IC14ENS_Pos                 (13U)
+#define RCC_DIVENSR_IC14ENS_Msk                 (0x1UL << RCC_DIVENSR_IC14ENS_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENSR_IC14ENS                     RCC_DIVENSR_IC14ENS_Msk              /*!< IC14 enable */
+#define RCC_DIVENSR_IC15ENS_Pos                 (14U)
+#define RCC_DIVENSR_IC15ENS_Msk                 (0x1UL << RCC_DIVENSR_IC15ENS_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENSR_IC15ENS                     RCC_DIVENSR_IC15ENS_Msk              /*!< IC15 enable */
+#define RCC_DIVENSR_IC16ENS_Pos                 (15U)
+#define RCC_DIVENSR_IC16ENS_Msk                 (0x1UL << RCC_DIVENSR_IC16ENS_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENSR_IC16ENS                     RCC_DIVENSR_IC16ENS_Msk              /*!< IC16 enable */
+#define RCC_DIVENSR_IC17ENS_Pos                 (16U)
+#define RCC_DIVENSR_IC17ENS_Msk                 (0x1UL << RCC_DIVENSR_IC17ENS_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENSR_IC17ENS                     RCC_DIVENSR_IC17ENS_Msk              /*!< IC17 enable */
+#define RCC_DIVENSR_IC18ENS_Pos                 (17U)
+#define RCC_DIVENSR_IC18ENS_Msk                 (0x1UL << RCC_DIVENSR_IC18ENS_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENSR_IC18ENS                     RCC_DIVENSR_IC18ENS_Msk              /*!< IC18 enable */
+#define RCC_DIVENSR_IC19ENS_Pos                 (18U)
+#define RCC_DIVENSR_IC19ENS_Msk                 (0x1UL << RCC_DIVENSR_IC19ENS_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENSR_IC19ENS                     RCC_DIVENSR_IC19ENS_Msk              /*!< IC19 enable */
+#define RCC_DIVENSR_IC20ENS_Pos                 (19U)
+#define RCC_DIVENSR_IC20ENS_Msk                 (0x1UL << RCC_DIVENSR_IC20ENS_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENSR_IC20ENS                     RCC_DIVENSR_IC20ENS_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENSR register  ******************/
+#define RCC_BUSENSR_ACLKNENS_Pos                (0U)
+#define RCC_BUSENSR_ACLKNENS_Msk                (0x1UL << RCC_BUSENSR_ACLKNENS_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENSR_ACLKNENS                    RCC_BUSENSR_ACLKNENS_Msk             /*!< ACLKN enable */
+#define RCC_BUSENSR_ACLKNCENS_Pos               (1U)
+#define RCC_BUSENSR_ACLKNCENS_Msk               (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENSR_ACLKNCENS                   RCC_BUSENSR_ACLKNCENS_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENSR_AHBMENS_Pos                 (2U)
+#define RCC_BUSENSR_AHBMENS_Msk                 (0x1UL << RCC_BUSENSR_AHBMENS_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENSR_AHBMENS                     RCC_BUSENSR_AHBMENS_Msk              /*!< AHBM enable */
+#define RCC_BUSENSR_AHB1ENS_Pos                 (3U)
+#define RCC_BUSENSR_AHB1ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB1ENS_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENSR_AHB1ENS                     RCC_BUSENSR_AHB1ENS_Msk              /*!< AHB1 enable */
+#define RCC_BUSENSR_AHB2ENS_Pos                 (4U)
+#define RCC_BUSENSR_AHB2ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB2ENS_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENSR_AHB2ENS                     RCC_BUSENSR_AHB2ENS_Msk              /*!< AHB2 enable */
+#define RCC_BUSENSR_AHB3ENS_Pos                 (5U)
+#define RCC_BUSENSR_AHB3ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB3ENS_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENSR_AHB3ENS                     RCC_BUSENSR_AHB3ENS_Msk              /*!< AHB3 enable */
+#define RCC_BUSENSR_AHB4ENS_Pos                 (6U)
+#define RCC_BUSENSR_AHB4ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB4ENS_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENSR_AHB4ENS                     RCC_BUSENSR_AHB4ENS_Msk              /*!< AHB4 enable */
+#define RCC_BUSENSR_AHB5ENS_Pos                 (7U)
+#define RCC_BUSENSR_AHB5ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB5ENS_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENSR_AHB5ENS                     RCC_BUSENSR_AHB5ENS_Msk              /*!< AHB5 enable */
+#define RCC_BUSENSR_APB1ENS_Pos                 (8U)
+#define RCC_BUSENSR_APB1ENS_Msk                 (0x1UL << RCC_BUSENSR_APB1ENS_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENSR_APB1ENS                     RCC_BUSENSR_APB1ENS_Msk              /*!< APB1 enable */
+#define RCC_BUSENSR_APB2ENS_Pos                 (9U)
+#define RCC_BUSENSR_APB2ENS_Msk                 (0x1UL << RCC_BUSENSR_APB2ENS_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENSR_APB2ENS                     RCC_BUSENSR_APB2ENS_Msk              /*!< APB2 enable */
+#define RCC_BUSENSR_APB3ENS_Pos                 (10U)
+#define RCC_BUSENSR_APB3ENS_Msk                 (0x1UL << RCC_BUSENSR_APB3ENS_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENSR_APB3ENS                     RCC_BUSENSR_APB3ENS_Msk              /*!< APB3 enable */
+#define RCC_BUSENSR_APB4ENS_Pos                 (11U)
+#define RCC_BUSENSR_APB4ENS_Msk                 (0x1UL << RCC_BUSENSR_APB4ENS_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENSR_APB4ENS                     RCC_BUSENSR_APB4ENS_Msk              /*!< APB4 enable */
+#define RCC_BUSENSR_APB5ENS_Pos                 (12U)
+#define RCC_BUSENSR_APB5ENS_Msk                 (0x1UL << RCC_BUSENSR_APB5ENS_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENSR_APB5ENS                     RCC_BUSENSR_APB5ENS_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENSR register  *****************/
+#define RCC_MISCENSR_DBGENS_Pos                 (0U)
+#define RCC_MISCENSR_DBGENS_Msk                 (0x1UL << RCC_MISCENSR_DBGENS_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENSR_DBGENS                     RCC_MISCENSR_DBGENS_Msk              /*!< DBG enable */
+#define RCC_MISCENSR_MCO1ENS_Pos                (1U)
+#define RCC_MISCENSR_MCO1ENS_Msk                (0x1UL << RCC_MISCENSR_MCO1ENS_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENSR_MCO1ENS                    RCC_MISCENSR_MCO1ENS_Msk             /*!< MCO1 enable */
+#define RCC_MISCENSR_MCO2ENS_Pos                (2U)
+#define RCC_MISCENSR_MCO2ENS_Msk                (0x1UL << RCC_MISCENSR_MCO2ENS_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENSR_MCO2ENS                    RCC_MISCENSR_MCO2ENS_Msk             /*!< MCO2 enable */
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos         (3U)
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk         (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENSR_XSPIPHYCOMPENS             RCC_MISCENSR_XSPIPHYCOMPENS_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENSR_PERENS_Pos                 (6U)
+#define RCC_MISCENSR_PERENS_Msk                 (0x1UL << RCC_MISCENSR_PERENS_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENSR_PERENS                     RCC_MISCENSR_PERENS_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENSR register  ******************/
+#define RCC_MEMENSR_AXISRAM3ENS_Pos             (0U)
+#define RCC_MEMENSR_AXISRAM3ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */
+#define RCC_MEMENSR_AXISRAM3ENS                 RCC_MEMENSR_AXISRAM3ENS_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENSR_AXISRAM4ENS_Pos             (1U)
+#define RCC_MEMENSR_AXISRAM4ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */
+#define RCC_MEMENSR_AXISRAM4ENS                 RCC_MEMENSR_AXISRAM4ENS_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENSR_AXISRAM5ENS_Pos             (2U)
+#define RCC_MEMENSR_AXISRAM5ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */
+#define RCC_MEMENSR_AXISRAM5ENS                 RCC_MEMENSR_AXISRAM5ENS_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENSR_AXISRAM6ENS_Pos             (3U)
+#define RCC_MEMENSR_AXISRAM6ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */
+#define RCC_MEMENSR_AXISRAM6ENS                 RCC_MEMENSR_AXISRAM6ENS_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENSR_AHBSRAM1ENS_Pos             (4U)
+#define RCC_MEMENSR_AHBSRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */
+#define RCC_MEMENSR_AHBSRAM1ENS                 RCC_MEMENSR_AHBSRAM1ENS_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENSR_AHBSRAM2ENS_Pos             (5U)
+#define RCC_MEMENSR_AHBSRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */
+#define RCC_MEMENSR_AHBSRAM2ENS                 RCC_MEMENSR_AHBSRAM2ENS_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENSR_BKPSRAMENS_Pos              (6U)
+#define RCC_MEMENSR_BKPSRAMENS_Msk              (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */
+#define RCC_MEMENSR_BKPSRAMENS                  RCC_MEMENSR_BKPSRAMENS_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENSR_AXISRAM1ENS_Pos             (7U)
+#define RCC_MEMENSR_AXISRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */
+#define RCC_MEMENSR_AXISRAM1ENS                 RCC_MEMENSR_AXISRAM1ENS_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENSR_AXISRAM2ENS_Pos             (8U)
+#define RCC_MEMENSR_AXISRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */
+#define RCC_MEMENSR_AXISRAM2ENS                 RCC_MEMENSR_AXISRAM2ENS_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENSR_FLEXRAMENS_Pos              (9U)
+#define RCC_MEMENSR_FLEXRAMENS_Msk              (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */
+#define RCC_MEMENSR_FLEXRAMENS                  RCC_MEMENSR_FLEXRAMENS_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENSR_VENCRAMENS_Pos              (11U)
+#define RCC_MEMENSR_VENCRAMENS_Msk              (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */
+#define RCC_MEMENSR_VENCRAMENS                  RCC_MEMENSR_VENCRAMENS_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENSR_BOOTROMENS_Pos              (12U)
+#define RCC_MEMENSR_BOOTROMENS_Msk              (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */
+#define RCC_MEMENSR_BOOTROMENS                  RCC_MEMENSR_BOOTROMENS_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENSR register  *****************/
+#define RCC_AHB1ENSR_GPDMA1ENS_Pos              (4U)
+#define RCC_AHB1ENSR_GPDMA1ENS_Msk              (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENSR_GPDMA1ENS                  RCC_AHB1ENSR_GPDMA1ENS_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENSR_ADC12ENS_Pos               (5U)
+#define RCC_AHB1ENSR_ADC12ENS_Msk               (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENSR_ADC12ENS                   RCC_AHB1ENSR_ADC12ENS_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENSR register  *****************/
+#define RCC_AHB2ENSR_RAMCFGENS_Pos              (12U)
+#define RCC_AHB2ENSR_RAMCFGENS_Msk              (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENSR_RAMCFGENS                  RCC_AHB2ENSR_RAMCFGENS_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENSR_MDF1ENS_Pos                (16U)
+#define RCC_AHB2ENSR_MDF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENSR_MDF1ENS                    RCC_AHB2ENSR_MDF1ENS_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENSR_ADF1ENS_Pos                (17U)
+#define RCC_AHB2ENSR_ADF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENSR_ADF1ENS                    RCC_AHB2ENSR_ADF1ENS_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENSR register  *****************/
+#define RCC_AHB3ENSR_RNGENS_Pos                 (0U)
+#define RCC_AHB3ENSR_RNGENS_Msk                 (0x1UL << RCC_AHB3ENSR_RNGENS_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENSR_RNGENS                     RCC_AHB3ENSR_RNGENS_Msk              /*!< RNG enable */
+#define RCC_AHB3ENSR_HASHENS_Pos                (1U)
+#define RCC_AHB3ENSR_HASHENS_Msk                (0x1UL << RCC_AHB3ENSR_HASHENS_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENSR_HASHENS                    RCC_AHB3ENSR_HASHENS_Msk             /*!< HASH enable */
+#define RCC_AHB3ENSR_CRYPENS_Pos                (2U)
+#define RCC_AHB3ENSR_CRYPENS_Msk                (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos)   /*!< 0x00000004 */
+#define RCC_AHB3ENSR_CRYPENS                    RCC_AHB3ENSR_CRYPENS_Msk             /*!< CRYP enable */
+#define RCC_AHB3ENSR_SAESENS_Pos                (4U)
+#define RCC_AHB3ENSR_SAESENS_Msk                (0x1UL << RCC_AHB3ENSR_SAESENS_Pos)   /*!< 0x00000010 */
+#define RCC_AHB3ENSR_SAESENS                    RCC_AHB3ENSR_SAESENS_Msk             /*!< SAES enable */
+#define RCC_AHB3ENSR_PKAENS_Pos                 (8U)
+#define RCC_AHB3ENSR_PKAENS_Msk                 (0x1UL << RCC_AHB3ENSR_PKAENS_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENSR_PKAENS                     RCC_AHB3ENSR_PKAENS_Msk              /*!< PKA enable */
+#define RCC_AHB3ENSR_RIFSCENS_Pos               (9U)
+#define RCC_AHB3ENSR_RIFSCENS_Msk               (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENSR_RIFSCENS                   RCC_AHB3ENSR_RIFSCENS_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENSR_IACENS_Pos                 (10U)
+#define RCC_AHB3ENSR_IACENS_Msk                 (0x1UL << RCC_AHB3ENSR_IACENS_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENSR_IACENS                     RCC_AHB3ENSR_IACENS_Msk              /*!< IAC enable */
+#define RCC_AHB3ENSR_RISAFENS_Pos               (14U)
+#define RCC_AHB3ENSR_RISAFENS_Msk               (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENSR_RISAFENS                   RCC_AHB3ENSR_RISAFENS_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENSR register  *****************/
+#define RCC_AHB4ENSR_GPIOAENS_Pos               (0U)
+#define RCC_AHB4ENSR_GPIOAENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENSR_GPIOAENS                   RCC_AHB4ENSR_GPIOAENS_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENSR_GPIOBENS_Pos               (1U)
+#define RCC_AHB4ENSR_GPIOBENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENSR_GPIOBENS                   RCC_AHB4ENSR_GPIOBENS_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENSR_GPIOCENS_Pos               (2U)
+#define RCC_AHB4ENSR_GPIOCENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENSR_GPIOCENS                   RCC_AHB4ENSR_GPIOCENS_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENSR_GPIODENS_Pos               (3U)
+#define RCC_AHB4ENSR_GPIODENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENSR_GPIODENS                   RCC_AHB4ENSR_GPIODENS_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENSR_GPIOEENS_Pos               (4U)
+#define RCC_AHB4ENSR_GPIOEENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENSR_GPIOEENS                   RCC_AHB4ENSR_GPIOEENS_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENSR_GPIOFENS_Pos               (5U)
+#define RCC_AHB4ENSR_GPIOFENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENSR_GPIOFENS                   RCC_AHB4ENSR_GPIOFENS_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENSR_GPIOGENS_Pos               (6U)
+#define RCC_AHB4ENSR_GPIOGENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENSR_GPIOGENS                   RCC_AHB4ENSR_GPIOGENS_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENSR_GPIOHENS_Pos               (7U)
+#define RCC_AHB4ENSR_GPIOHENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENSR_GPIOHENS                   RCC_AHB4ENSR_GPIOHENS_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENSR_GPIONENS_Pos               (13U)
+#define RCC_AHB4ENSR_GPIONENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENSR_GPIONENS                   RCC_AHB4ENSR_GPIONENS_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENSR_GPIOOENS_Pos               (14U)
+#define RCC_AHB4ENSR_GPIOOENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENSR_GPIOOENS                   RCC_AHB4ENSR_GPIOOENS_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENSR_GPIOPENS_Pos               (15U)
+#define RCC_AHB4ENSR_GPIOPENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENSR_GPIOPENS                   RCC_AHB4ENSR_GPIOPENS_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENSR_GPIOQENS_Pos               (16U)
+#define RCC_AHB4ENSR_GPIOQENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENSR_GPIOQENS                   RCC_AHB4ENSR_GPIOQENS_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENSR_PWRENS_Pos                 (18U)
+#define RCC_AHB4ENSR_PWRENS_Msk                 (0x1UL << RCC_AHB4ENSR_PWRENS_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENSR_PWRENS                     RCC_AHB4ENSR_PWRENS_Msk              /*!< PWR enable */
+#define RCC_AHB4ENSR_CRCENS_Pos                 (19U)
+#define RCC_AHB4ENSR_CRCENS_Msk                 (0x1UL << RCC_AHB4ENSR_CRCENS_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENSR_CRCENS                     RCC_AHB4ENSR_CRCENS_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENSR register  *****************/
+#define RCC_AHB5ENSR_HPDMA1ENS_Pos              (0U)
+#define RCC_AHB5ENSR_HPDMA1ENS_Msk              (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENSR_HPDMA1ENS                  RCC_AHB5ENSR_HPDMA1ENS_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENSR_DMA2DENS_Pos               (1U)
+#define RCC_AHB5ENSR_DMA2DENS_Msk               (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENSR_DMA2DENS                   RCC_AHB5ENSR_DMA2DENS_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENSR_JPEGENS_Pos                (3U)
+#define RCC_AHB5ENSR_JPEGENS_Msk                (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENSR_JPEGENS                    RCC_AHB5ENSR_JPEGENS_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENSR_FMCENS_Pos                 (4U)
+#define RCC_AHB5ENSR_FMCENS_Msk                 (0x1UL << RCC_AHB5ENSR_FMCENS_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENSR_FMCENS                     RCC_AHB5ENSR_FMCENS_Msk              /*!< FMC enable */
+#define RCC_AHB5ENSR_XSPI1ENS_Pos               (5U)
+#define RCC_AHB5ENSR_XSPI1ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENSR_XSPI1ENS                   RCC_AHB5ENSR_XSPI1ENS_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENSR_PSSIENS_Pos                (6U)
+#define RCC_AHB5ENSR_PSSIENS_Msk                (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENSR_PSSIENS                    RCC_AHB5ENSR_PSSIENS_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENSR_SDMMC2ENS_Pos              (7U)
+#define RCC_AHB5ENSR_SDMMC2ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENSR_SDMMC2ENS                  RCC_AHB5ENSR_SDMMC2ENS_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENSR_SDMMC1ENS_Pos              (8U)
+#define RCC_AHB5ENSR_SDMMC1ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENSR_SDMMC1ENS                  RCC_AHB5ENSR_SDMMC1ENS_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENSR_XSPI2ENS_Pos               (12U)
+#define RCC_AHB5ENSR_XSPI2ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENSR_XSPI2ENS                   RCC_AHB5ENSR_XSPI2ENS_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENSR_XSPIMENS_Pos               (13U)
+#define RCC_AHB5ENSR_XSPIMENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENSR_XSPIMENS                   RCC_AHB5ENSR_XSPIMENS_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENSR_MCE1ENS_Pos                (14U)
+#define RCC_AHB5ENSR_MCE1ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos)   /*!< 0x00004000 */
+#define RCC_AHB5ENSR_MCE1ENS                    RCC_AHB5ENSR_MCE1ENS_Msk             /*!< MCE1 enable */
+#define RCC_AHB5ENSR_MCE2ENS_Pos                (15U)
+#define RCC_AHB5ENSR_MCE2ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos)   /*!< 0x00008000 */
+#define RCC_AHB5ENSR_MCE2ENS                    RCC_AHB5ENSR_MCE2ENS_Msk             /*!< MCE2 enable */
+#define RCC_AHB5ENSR_MCE3ENS_Pos                (16U)
+#define RCC_AHB5ENSR_MCE3ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos)   /*!< 0x00010000 */
+#define RCC_AHB5ENSR_MCE3ENS                    RCC_AHB5ENSR_MCE3ENS_Msk             /*!< MCE3 enable */
+#define RCC_AHB5ENSR_XSPI3ENS_Pos               (17U)
+#define RCC_AHB5ENSR_XSPI3ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENSR_XSPI3ENS                   RCC_AHB5ENSR_XSPI3ENS_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENSR_MCE4ENS_Pos                (18U)
+#define RCC_AHB5ENSR_MCE4ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos)   /*!< 0x00040000 */
+#define RCC_AHB5ENSR_MCE4ENS                    RCC_AHB5ENSR_MCE4ENS_Msk             /*!< MCE4 enable */
+#define RCC_AHB5ENSR_GFXMMUENS_Pos              (19U)
+#define RCC_AHB5ENSR_GFXMMUENS_Msk              (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENSR_GFXMMUENS                  RCC_AHB5ENSR_GFXMMUENS_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENSR_GPU2DENS_Pos               (20U)
+#define RCC_AHB5ENSR_GPU2DENS_Msk               (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENSR_GPU2DENS                   RCC_AHB5ENSR_GPU2DENS_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENSR_ETH1MACENS_Pos             (22U)
+#define RCC_AHB5ENSR_ETH1MACENS_Msk             (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENSR_ETH1MACENS                 RCC_AHB5ENSR_ETH1MACENS_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENSR_ETH1TXENS_Pos              (23U)
+#define RCC_AHB5ENSR_ETH1TXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENSR_ETH1TXENS                  RCC_AHB5ENSR_ETH1TXENS_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENSR_ETH1RXENS_Pos              (24U)
+#define RCC_AHB5ENSR_ETH1RXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENSR_ETH1RXENS                  RCC_AHB5ENSR_ETH1RXENS_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENSR_ETH1ENS_Pos                (25U)
+#define RCC_AHB5ENSR_ETH1ENS_Msk                (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENSR_ETH1ENS                    RCC_AHB5ENSR_ETH1ENS_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENSR_OTG1ENS_Pos                (26U)
+#define RCC_AHB5ENSR_OTG1ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENSR_OTG1ENS                    RCC_AHB5ENSR_OTG1ENS_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENSR_OTGPHY1ENS_Pos             (27U)
+#define RCC_AHB5ENSR_OTGPHY1ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENSR_OTGPHY1ENS                 RCC_AHB5ENSR_OTGPHY1ENS_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENSR_OTGPHY2ENS_Pos             (28U)
+#define RCC_AHB5ENSR_OTGPHY2ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENSR_OTGPHY2ENS                 RCC_AHB5ENSR_OTGPHY2ENS_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENSR_OTG2ENS_Pos                (29U)
+#define RCC_AHB5ENSR_OTG2ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENSR_OTG2ENS                    RCC_AHB5ENSR_OTG2ENS_Msk             /*!< OTG2 enable */
+
+/****************  Bit definition for RCC_APB1ENSR1 register  *****************/
+#define RCC_APB1ENSR1_TIM2ENS_Pos               (0U)
+#define RCC_APB1ENSR1_TIM2ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENSR1_TIM2ENS                   RCC_APB1ENSR1_TIM2ENS_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENSR1_TIM3ENS_Pos               (1U)
+#define RCC_APB1ENSR1_TIM3ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENSR1_TIM3ENS                   RCC_APB1ENSR1_TIM3ENS_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENSR1_TIM4ENS_Pos               (2U)
+#define RCC_APB1ENSR1_TIM4ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENSR1_TIM4ENS                   RCC_APB1ENSR1_TIM4ENS_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENSR1_TIM5ENS_Pos               (3U)
+#define RCC_APB1ENSR1_TIM5ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENSR1_TIM5ENS                   RCC_APB1ENSR1_TIM5ENS_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENSR1_TIM6ENS_Pos               (4U)
+#define RCC_APB1ENSR1_TIM6ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENSR1_TIM6ENS                   RCC_APB1ENSR1_TIM6ENS_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENSR1_TIM7ENS_Pos               (5U)
+#define RCC_APB1ENSR1_TIM7ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENSR1_TIM7ENS                   RCC_APB1ENSR1_TIM7ENS_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENSR1_TIM12ENS_Pos              (6U)
+#define RCC_APB1ENSR1_TIM12ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENSR1_TIM12ENS                  RCC_APB1ENSR1_TIM12ENS_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENSR1_TIM13ENS_Pos              (7U)
+#define RCC_APB1ENSR1_TIM13ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENSR1_TIM13ENS                  RCC_APB1ENSR1_TIM13ENS_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENSR1_TIM14ENS_Pos              (8U)
+#define RCC_APB1ENSR1_TIM14ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR1_TIM14ENS                  RCC_APB1ENSR1_TIM14ENS_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENSR1_LPTIM1ENS_Pos             (9U)
+#define RCC_APB1ENSR1_LPTIM1ENS_Msk             (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENSR1_LPTIM1ENS                 RCC_APB1ENSR1_LPTIM1ENS_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENSR1_WWDGENS_Pos               (11U)
+#define RCC_APB1ENSR1_WWDGENS_Msk               (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1ENSR1_WWDGENS                   RCC_APB1ENSR1_WWDGENS_Msk            /*!< WWDG enable */
+#define RCC_APB1ENSR1_TIM10ENS_Pos              (12U)
+#define RCC_APB1ENSR1_TIM10ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENSR1_TIM10ENS                  RCC_APB1ENSR1_TIM10ENS_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENSR1_TIM11ENS_Pos              (13U)
+#define RCC_APB1ENSR1_TIM11ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENSR1_TIM11ENS                  RCC_APB1ENSR1_TIM11ENS_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENSR1_SPI2ENS_Pos               (14U)
+#define RCC_APB1ENSR1_SPI2ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENSR1_SPI2ENS                   RCC_APB1ENSR1_SPI2ENS_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENSR1_SPI3ENS_Pos               (15U)
+#define RCC_APB1ENSR1_SPI3ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENSR1_SPI3ENS                   RCC_APB1ENSR1_SPI3ENS_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos           (16U)
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk           (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENSR1_SPDIFRX1ENS               RCC_APB1ENSR1_SPDIFRX1ENS_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENSR1_USART2ENS_Pos             (17U)
+#define RCC_APB1ENSR1_USART2ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENSR1_USART2ENS                 RCC_APB1ENSR1_USART2ENS_Msk          /*!< USART2 enable */
+#define RCC_APB1ENSR1_USART3ENS_Pos             (18U)
+#define RCC_APB1ENSR1_USART3ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENSR1_USART3ENS                 RCC_APB1ENSR1_USART3ENS_Msk          /*!< USART3 enable */
+#define RCC_APB1ENSR1_UART4ENS_Pos              (19U)
+#define RCC_APB1ENSR1_UART4ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENSR1_UART4ENS                  RCC_APB1ENSR1_UART4ENS_Msk           /*!< UART4 enable */
+#define RCC_APB1ENSR1_UART5ENS_Pos              (20U)
+#define RCC_APB1ENSR1_UART5ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENSR1_UART5ENS                  RCC_APB1ENSR1_UART5ENS_Msk           /*!< UART5 enable */
+#define RCC_APB1ENSR1_I2C1ENS_Pos               (21U)
+#define RCC_APB1ENSR1_I2C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENSR1_I2C1ENS                   RCC_APB1ENSR1_I2C1ENS_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENSR1_I2C2ENS_Pos               (22U)
+#define RCC_APB1ENSR1_I2C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENSR1_I2C2ENS                   RCC_APB1ENSR1_I2C2ENS_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENSR1_I2C3ENS_Pos               (23U)
+#define RCC_APB1ENSR1_I2C3ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENSR1_I2C3ENS                   RCC_APB1ENSR1_I2C3ENS_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENSR1_I3C1ENS_Pos               (24U)
+#define RCC_APB1ENSR1_I3C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENSR1_I3C1ENS                   RCC_APB1ENSR1_I3C1ENS_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENSR1_I3C2ENS_Pos               (25U)
+#define RCC_APB1ENSR1_I3C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENSR1_I3C2ENS                   RCC_APB1ENSR1_I3C2ENS_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENSR1_UART7ENS_Pos              (30U)
+#define RCC_APB1ENSR1_UART7ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENSR1_UART7ENS                  RCC_APB1ENSR1_UART7ENS_Msk           /*!< UART7 enable */
+#define RCC_APB1ENSR1_UART8ENS_Pos              (31U)
+#define RCC_APB1ENSR1_UART8ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENSR1_UART8ENS                  RCC_APB1ENSR1_UART8ENS_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENSR2 register  *****************/
+#define RCC_APB1ENSR2_MDIOSENS_Pos              (5U)
+#define RCC_APB1ENSR2_MDIOSENS_Msk              (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENSR2_MDIOSENS                  RCC_APB1ENSR2_MDIOSENS_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENSR2_FDCANENS_Pos              (8U)
+#define RCC_APB1ENSR2_FDCANENS_Msk              (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR2_FDCANENS                  RCC_APB1ENSR2_FDCANENS_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENSR2_UCPD1ENS_Pos              (18U)
+#define RCC_APB1ENSR2_UCPD1ENS_Msk              (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENSR2_UCPD1ENS                  RCC_APB1ENSR2_UCPD1ENS_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENSR register  *****************/
+#define RCC_APB2ENSR_TIM1ENS_Pos                (0U)
+#define RCC_APB2ENSR_TIM1ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENSR_TIM1ENS                    RCC_APB2ENSR_TIM1ENS_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENSR_TIM8ENS_Pos                (1U)
+#define RCC_APB2ENSR_TIM8ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENSR_TIM8ENS                    RCC_APB2ENSR_TIM8ENS_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENSR_USART1ENS_Pos              (4U)
+#define RCC_APB2ENSR_USART1ENS_Msk              (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENSR_USART1ENS                  RCC_APB2ENSR_USART1ENS_Msk           /*!< USART1 enable */
+#define RCC_APB2ENSR_USART6ENS_Pos              (5U)
+#define RCC_APB2ENSR_USART6ENS_Msk              (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENSR_USART6ENS                  RCC_APB2ENSR_USART6ENS_Msk           /*!< USART6 enable */
+#define RCC_APB2ENSR_UART9ENS_Pos               (6U)
+#define RCC_APB2ENSR_UART9ENS_Msk               (0x1UL << RCC_APB2ENSR_UART9ENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENSR_UART9ENS                   RCC_APB2ENSR_UART9ENS_Msk            /*!< UART9 enable */
+#define RCC_APB2ENSR_USART10ENS_Pos             (7U)
+#define RCC_APB2ENSR_USART10ENS_Msk             (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENSR_USART10ENS                 RCC_APB2ENSR_USART10ENS_Msk          /*!< USART10 enable */
+#define RCC_APB2ENSR_SPI1ENS_Pos                (12U)
+#define RCC_APB2ENSR_SPI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENSR_SPI1ENS                    RCC_APB2ENSR_SPI1ENS_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENSR_SPI4ENS_Pos                (13U)
+#define RCC_APB2ENSR_SPI4ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENSR_SPI4ENS                    RCC_APB2ENSR_SPI4ENS_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENSR_TIM18ENS_Pos               (15U)
+#define RCC_APB2ENSR_TIM18ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENSR_TIM18ENS                   RCC_APB2ENSR_TIM18ENS_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENSR_TIM15ENS_Pos               (16U)
+#define RCC_APB2ENSR_TIM15ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENSR_TIM15ENS                   RCC_APB2ENSR_TIM15ENS_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENSR_TIM16ENS_Pos               (17U)
+#define RCC_APB2ENSR_TIM16ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENSR_TIM16ENS                   RCC_APB2ENSR_TIM16ENS_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENSR_TIM17ENS_Pos               (18U)
+#define RCC_APB2ENSR_TIM17ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENSR_TIM17ENS                   RCC_APB2ENSR_TIM17ENS_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENSR_TIM9ENS_Pos                (19U)
+#define RCC_APB2ENSR_TIM9ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENSR_TIM9ENS                    RCC_APB2ENSR_TIM9ENS_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENSR_SPI5ENS_Pos                (20U)
+#define RCC_APB2ENSR_SPI5ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENSR_SPI5ENS                    RCC_APB2ENSR_SPI5ENS_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENSR_SAI1ENS_Pos                (21U)
+#define RCC_APB2ENSR_SAI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENSR_SAI1ENS                    RCC_APB2ENSR_SAI1ENS_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENSR_SAI2ENS_Pos                (22U)
+#define RCC_APB2ENSR_SAI2ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENSR_SAI2ENS                    RCC_APB2ENSR_SAI2ENS_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENSR register  *****************/
+#define RCC_APB3ENSR_DFTENS_Pos                 (2U)
+#define RCC_APB3ENSR_DFTENS_Msk                 (0x1UL << RCC_APB3ENSR_DFTENS_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENSR_DFTENS                     RCC_APB3ENSR_DFTENS_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENSR1 register  *****************/
+#define RCC_APB4ENSR1_HDPENS_Pos                (2U)
+#define RCC_APB4ENSR1_HDPENS_Msk                (0x1UL << RCC_APB4ENSR1_HDPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR1_HDPENS                    RCC_APB4ENSR1_HDPENS_Msk             /*!< HDP enable */
+#define RCC_APB4ENSR1_LPUART1ENS_Pos            (3U)
+#define RCC_APB4ENSR1_LPUART1ENS_Msk            (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENSR1_LPUART1ENS                RCC_APB4ENSR1_LPUART1ENS_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENSR1_SPI6ENS_Pos               (5U)
+#define RCC_APB4ENSR1_SPI6ENS_Msk               (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENSR1_SPI6ENS                   RCC_APB4ENSR1_SPI6ENS_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENSR1_I2C4ENS_Pos               (7U)
+#define RCC_APB4ENSR1_I2C4ENS_Msk               (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENSR1_I2C4ENS                   RCC_APB4ENSR1_I2C4ENS_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENSR1_LPTIM2ENS_Pos             (9U)
+#define RCC_APB4ENSR1_LPTIM2ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENSR1_LPTIM2ENS                 RCC_APB4ENSR1_LPTIM2ENS_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENSR1_LPTIM3ENS_Pos             (10U)
+#define RCC_APB4ENSR1_LPTIM3ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENSR1_LPTIM3ENS                 RCC_APB4ENSR1_LPTIM3ENS_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENSR1_LPTIM4ENS_Pos             (11U)
+#define RCC_APB4ENSR1_LPTIM4ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENSR1_LPTIM4ENS                 RCC_APB4ENSR1_LPTIM4ENS_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENSR1_LPTIM5ENS_Pos             (12U)
+#define RCC_APB4ENSR1_LPTIM5ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENSR1_LPTIM5ENS                 RCC_APB4ENSR1_LPTIM5ENS_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENSR1_VREFBUFENS_Pos            (15U)
+#define RCC_APB4ENSR1_VREFBUFENS_Msk            (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENSR1_VREFBUFENS                RCC_APB4ENSR1_VREFBUFENS_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENSR1_RTCENS_Pos                (16U)
+#define RCC_APB4ENSR1_RTCENS_Msk                (0x1UL << RCC_APB4ENSR1_RTCENS_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENSR1_RTCENS                    RCC_APB4ENSR1_RTCENS_Msk             /*!< RTC enable */
+#define RCC_APB4ENSR1_RTCAPBENS_Pos             (17U)
+#define RCC_APB4ENSR1_RTCAPBENS_Msk             (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENSR1_RTCAPBENS                 RCC_APB4ENSR1_RTCAPBENS_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENSR2 register  *****************/
+#define RCC_APB4ENSR2_SYSCFGENS_Pos             (0U)
+#define RCC_APB4ENSR2_SYSCFGENS_Msk             (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENSR2_SYSCFGENS                 RCC_APB4ENSR2_SYSCFGENS_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENSR2_BSECENS_Pos               (1U)
+#define RCC_APB4ENSR2_BSECENS_Msk               (0x1UL << RCC_APB4ENSR2_BSECENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENSR2_BSECENS                   RCC_APB4ENSR2_BSECENS_Msk            /*!< BSEC enable */
+#define RCC_APB4ENSR2_DTSENS_Pos                (2U)
+#define RCC_APB4ENSR2_DTSENS_Msk                (0x1UL << RCC_APB4ENSR2_DTSENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR2_DTSENS                    RCC_APB4ENSR2_DTSENS_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENSR register  *****************/
+#define RCC_APB5ENSR_LTDCENS_Pos                (1U)
+#define RCC_APB5ENSR_LTDCENS_Msk                (0x1UL << RCC_APB5ENSR_LTDCENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENSR_LTDCENS                    RCC_APB5ENSR_LTDCENS_Msk             /*!< LTDC enable */
+#define RCC_APB5ENSR_DCMIPPENS_Pos              (2U)
+#define RCC_APB5ENSR_DCMIPPENS_Msk              (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENSR_DCMIPPENS                  RCC_APB5ENSR_DCMIPPENS_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENSR_GFXTIMENS_Pos              (4U)
+#define RCC_APB5ENSR_GFXTIMENS_Msk              (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENSR_GFXTIMENS                  RCC_APB5ENSR_GFXTIMENS_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENSR_VENCENS_Pos                (5U)
+#define RCC_APB5ENSR_VENCENS_Msk                (0x1UL << RCC_APB5ENSR_VENCENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENSR_VENCENS                    RCC_APB5ENSR_VENCENS_Msk             /*!< VENC enable */
+#define RCC_APB5ENSR_CSIENS_Pos                 (6U)
+#define RCC_APB5ENSR_CSIENS_Msk                 (0x1UL << RCC_APB5ENSR_CSIENS_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENSR_CSIENS                     RCC_APB5ENSR_CSIENS_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENSR register  *****************/
+#define RCC_BUSLPENSR_ACLKNLPENS_Pos            (0U)
+#define RCC_BUSLPENSR_ACLKNLPENS_Msk            (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENSR_ACLKNLPENS                RCC_BUSLPENSR_ACLKNLPENS_Msk         /*!< ACLKN enable  */
+#define RCC_BUSLPENSR_ACLKNCLPENS_Pos           (1U)
+#define RCC_BUSLPENSR_ACLKNCLPENS_Msk           (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENSR_ACLKNCLPENS               RCC_BUSLPENSR_ACLKNCLPENS_Msk        /*!< ACLKNC enable  */
+
+/****************  Bit definition for RCC_MISCLPENSR register  ****************/
+#define RCC_MISCLPENSR_DBGLPENS_Pos             (0U)
+#define RCC_MISCLPENSR_DBGLPENS_Msk             (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENSR_DBGLPENS                 RCC_MISCLPENSR_DBGLPENS_Msk          /*!< DBG enable  */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos     (3U)
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk     (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS         RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk  /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENSR_PERLPENS_Pos             (6U)
+#define RCC_MISCLPENSR_PERLPENS_Msk             (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENSR_PERLPENS                 RCC_MISCLPENSR_PERLPENS_Msk          /*!< PER enable  */
+
+/****************  Bit definition for RCC_MEMLPENSR register  *****************/
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos         (0U)
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENSR_AXISRAM3LPENS             RCC_MEMLPENSR_AXISRAM3LPENS_Msk      /*!< AXISRAM3 enable  */
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos         (1U)
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENSR_AXISRAM4LPENS             RCC_MEMLPENSR_AXISRAM4LPENS_Msk      /*!< AXISRAM4 enable  */
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos         (2U)
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENSR_AXISRAM5LPENS             RCC_MEMLPENSR_AXISRAM5LPENS_Msk      /*!< AXISRAM5 enable  */
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos         (3U)
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENSR_AXISRAM6LPENS             RCC_MEMLPENSR_AXISRAM6LPENS_Msk      /*!< AXISRAM6 enable  */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos         (4U)
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS             RCC_MEMLPENSR_AHBSRAM1LPENS_Msk      /*!< AHBSRAM1 enable  */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos         (5U)
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS             RCC_MEMLPENSR_AHBSRAM2LPENS_Msk      /*!< AHBSRAM2 enable  */
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos          (6U)
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENSR_BKPSRAMLPENS              RCC_MEMLPENSR_BKPSRAMLPENS_Msk       /*!< BKPSRAM enable  */
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos         (7U)
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENSR_AXISRAM1LPENS             RCC_MEMLPENSR_AXISRAM1LPENS_Msk      /*!< AXISRAM1 enable  */
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos         (8U)
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENSR_AXISRAM2LPENS             RCC_MEMLPENSR_AXISRAM2LPENS_Msk      /*!< AXISRAM2 enable  */
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos          (9U)
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENSR_FLEXRAMLPENS              RCC_MEMLPENSR_FLEXRAMLPENS_Msk       /*!< FLEXRAM enable  */
+#define RCC_MEMLPENSR_VENCRAMLPENS_Pos          (11U)
+#define RCC_MEMLPENSR_VENCRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENSR_VENCRAMLPENS              RCC_MEMLPENSR_VENCRAMLPENS_Msk       /*!< VENCRAM enable  */
+#define RCC_MEMLPENSR_BOOTROMLPENS_Pos          (12U)
+#define RCC_MEMLPENSR_BOOTROMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENSR_BOOTROMLPENS              RCC_MEMLPENSR_BOOTROMLPENS_Msk       /*!< Boot ROM enable  */
+
+/****************  Bit definition for RCC_AHB1LPENSR register  ****************/
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos          (4U)
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk          (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENSR_GPDMA1LPENS              RCC_AHB1LPENSR_GPDMA1LPENS_Msk       /*!< GPDMA1 enable  */
+#define RCC_AHB1LPENSR_ADC12LPENS_Pos           (5U)
+#define RCC_AHB1LPENSR_ADC12LPENS_Msk           (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENSR_ADC12LPENS               RCC_AHB1LPENSR_ADC12LPENS_Msk        /*!< ADC12 enable  */
+
+/****************  Bit definition for RCC_AHB2LPENSR register  ****************/
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos          (12U)
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk          (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENSR_RAMCFGLPENS              RCC_AHB2LPENSR_RAMCFGLPENS_Msk       /*!< RAMCFG enable  */
+#define RCC_AHB2LPENSR_MDF1LPENS_Pos            (16U)
+#define RCC_AHB2LPENSR_MDF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENSR_MDF1LPENS                RCC_AHB2LPENSR_MDF1LPENS_Msk         /*!< MDF1 enable  */
+#define RCC_AHB2LPENSR_ADF1LPENS_Pos            (17U)
+#define RCC_AHB2LPENSR_ADF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENSR_ADF1LPENS                RCC_AHB2LPENSR_ADF1LPENS_Msk         /*!< ADF1 enable  */
+
+/****************  Bit definition for RCC_AHB3LPENSR register  ****************/
+#define RCC_AHB3LPENSR_RNGLPENS_Pos             (0U)
+#define RCC_AHB3LPENSR_RNGLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENSR_RNGLPENS                 RCC_AHB3LPENSR_RNGLPENS_Msk          /*!< RNG enable  */
+#define RCC_AHB3LPENSR_HASHLPENS_Pos            (1U)
+#define RCC_AHB3LPENSR_HASHLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENSR_HASHLPENS                RCC_AHB3LPENSR_HASHLPENS_Msk         /*!< HASH enable  */
+#define RCC_AHB3LPENSR_CRYPLPENS_Pos            (2U)
+#define RCC_AHB3LPENSR_CRYPLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */
+#define RCC_AHB3LPENSR_CRYPLPENS                RCC_AHB3LPENSR_CRYPLPENS_Msk         /*!< CRYP enable  */
+#define RCC_AHB3LPENSR_SAESLPENS_Pos            (4U)
+#define RCC_AHB3LPENSR_SAESLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */
+#define RCC_AHB3LPENSR_SAESLPENS                RCC_AHB3LPENSR_SAESLPENS_Msk         /*!< SAES enable  */
+#define RCC_AHB3LPENSR_PKALPENS_Pos             (8U)
+#define RCC_AHB3LPENSR_PKALPENS_Msk             (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENSR_PKALPENS                 RCC_AHB3LPENSR_PKALPENS_Msk          /*!< PKA enable  */
+#define RCC_AHB3LPENSR_RIFSCLPENS_Pos           (9U)
+#define RCC_AHB3LPENSR_RIFSCLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENSR_RIFSCLPENS               RCC_AHB3LPENSR_RIFSCLPENS_Msk        /*!< RIFSC enable  */
+#define RCC_AHB3LPENSR_IACLPENS_Pos             (10U)
+#define RCC_AHB3LPENSR_IACLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENSR_IACLPENS                 RCC_AHB3LPENSR_IACLPENS_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENSR_RISAFLPENS_Pos           (14U)
+#define RCC_AHB3LPENSR_RISAFLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENSR_RISAFLPENS               RCC_AHB3LPENSR_RISAFLPENS_Msk        /*!< RISAF enable  */
+
+/****************  Bit definition for RCC_AHB4LPENSR register  ****************/
+#define RCC_AHB4LPENSR_GPIOALPENS_Pos           (0U)
+#define RCC_AHB4LPENSR_GPIOALPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENSR_GPIOALPENS               RCC_AHB4LPENSR_GPIOALPENS_Msk        /*!< GPIO A enable  */
+#define RCC_AHB4LPENSR_GPIOBLPENS_Pos           (1U)
+#define RCC_AHB4LPENSR_GPIOBLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENSR_GPIOBLPENS               RCC_AHB4LPENSR_GPIOBLPENS_Msk        /*!< GPIO B enable  */
+#define RCC_AHB4LPENSR_GPIOCLPENS_Pos           (2U)
+#define RCC_AHB4LPENSR_GPIOCLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENSR_GPIOCLPENS               RCC_AHB4LPENSR_GPIOCLPENS_Msk        /*!< GPIO C enable  */
+#define RCC_AHB4LPENSR_GPIODLPENS_Pos           (3U)
+#define RCC_AHB4LPENSR_GPIODLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENSR_GPIODLPENS               RCC_AHB4LPENSR_GPIODLPENS_Msk        /*!< GPIO D enable  */
+#define RCC_AHB4LPENSR_GPIOELPENS_Pos           (4U)
+#define RCC_AHB4LPENSR_GPIOELPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENSR_GPIOELPENS               RCC_AHB4LPENSR_GPIOELPENS_Msk        /*!< GPIO E enable  */
+#define RCC_AHB4LPENSR_GPIOFLPENS_Pos           (5U)
+#define RCC_AHB4LPENSR_GPIOFLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENSR_GPIOFLPENS               RCC_AHB4LPENSR_GPIOFLPENS_Msk        /*!< GPIO F enable  */
+#define RCC_AHB4LPENSR_GPIOGLPENS_Pos           (6U)
+#define RCC_AHB4LPENSR_GPIOGLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENSR_GPIOGLPENS               RCC_AHB4LPENSR_GPIOGLPENS_Msk        /*!< GPIO G enable  */
+#define RCC_AHB4LPENSR_GPIOHLPENS_Pos           (7U)
+#define RCC_AHB4LPENSR_GPIOHLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENSR_GPIOHLPENS               RCC_AHB4LPENSR_GPIOHLPENS_Msk        /*!< GPIO H enable  */
+#define RCC_AHB4LPENSR_GPIONLPENS_Pos           (13U)
+#define RCC_AHB4LPENSR_GPIONLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENSR_GPIONLPENS               RCC_AHB4LPENSR_GPIONLPENS_Msk        /*!< GPIO N enable  */
+#define RCC_AHB4LPENSR_GPIOOLPENS_Pos           (14U)
+#define RCC_AHB4LPENSR_GPIOOLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENSR_GPIOOLPENS               RCC_AHB4LPENSR_GPIOOLPENS_Msk        /*!< GPIO O enable  */
+#define RCC_AHB4LPENSR_GPIOPLPENS_Pos           (15U)
+#define RCC_AHB4LPENSR_GPIOPLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENSR_GPIOPLPENS               RCC_AHB4LPENSR_GPIOPLPENS_Msk        /*!< GPIO P enable  */
+#define RCC_AHB4LPENSR_GPIOQLPENS_Pos           (16U)
+#define RCC_AHB4LPENSR_GPIOQLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENSR_GPIOQLPENS               RCC_AHB4LPENSR_GPIOQLPENS_Msk        /*!< GPIO Q enable  */
+#define RCC_AHB4LPENSR_PWRLPENS_Pos             (18U)
+#define RCC_AHB4LPENSR_PWRLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENSR_PWRLPENS                 RCC_AHB4LPENSR_PWRLPENS_Msk          /*!< PWR enable  */
+#define RCC_AHB4LPENSR_CRCLPENS_Pos             (19U)
+#define RCC_AHB4LPENSR_CRCLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENSR_CRCLPENS                 RCC_AHB4LPENSR_CRCLPENS_Msk          /*!< CRC enable  */
+
+/****************  Bit definition for RCC_AHB5LPENSR register  ****************/
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos          (0U)
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENSR_HPDMA1LPENS              RCC_AHB5LPENSR_HPDMA1LPENS_Msk       /*!< HPDMA1 enable  */
+#define RCC_AHB5LPENSR_DMA2DLPENS_Pos           (1U)
+#define RCC_AHB5LPENSR_DMA2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENSR_DMA2DLPENS               RCC_AHB5LPENSR_DMA2DLPENS_Msk        /*!< DMA2D enable  */
+#define RCC_AHB5LPENSR_JPEGLPENS_Pos            (3U)
+#define RCC_AHB5LPENSR_JPEGLPENS_Msk            (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENSR_JPEGLPENS                RCC_AHB5LPENSR_JPEGLPENS_Msk         /*!< JPEG enable  */
+#define RCC_AHB5LPENSR_FMCLPENS_Pos             (4U)
+#define RCC_AHB5LPENSR_FMCLPENS_Msk             (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENSR_FMCLPENS                 RCC_AHB5LPENSR_FMCLPENS_Msk          /*!< FMC enable  */
+#define RCC_AHB5LPENSR_XSPI1LPENS_Pos           (5U)
+#define RCC_AHB5LPENSR_XSPI1LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENSR_XSPI1LPENS               RCC_AHB5LPENSR_XSPI1LPENS_Msk        /*!< XSPI1 enable  */
+#define RCC_AHB5LPENSR_PSSILPENS_Pos            (6U)
+#define RCC_AHB5LPENSR_PSSILPENS_Msk            (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENSR_PSSILPENS                RCC_AHB5LPENSR_PSSILPENS_Msk         /*!< PSSI enable  */
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos          (7U)
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENSR_SDMMC2LPENS              RCC_AHB5LPENSR_SDMMC2LPENS_Msk       /*!< SDMMC2 enable  */
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos          (8U)
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENSR_SDMMC1LPENS              RCC_AHB5LPENSR_SDMMC1LPENS_Msk       /*!< SDMMC1 enable  */
+#define RCC_AHB5LPENSR_XSPI2LPENS_Pos           (12U)
+#define RCC_AHB5LPENSR_XSPI2LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENSR_XSPI2LPENS               RCC_AHB5LPENSR_XSPI2LPENS_Msk        /*!< XSPI2 enable  */
+#define RCC_AHB5LPENSR_XSPIMLPENS_Pos           (13U)
+#define RCC_AHB5LPENSR_XSPIMLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENSR_XSPIMLPENS               RCC_AHB5LPENSR_XSPIMLPENS_Msk        /*!< XSPIM enable  */
+#define RCC_AHB5LPENSR_MCE1LPENS_Pos            (14U)
+#define RCC_AHB5LPENSR_MCE1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */
+#define RCC_AHB5LPENSR_MCE1LPENS                RCC_AHB5LPENSR_MCE1LPENS_Msk         /*!< MCE1 enable  */
+#define RCC_AHB5LPENSR_MCE2LPENS_Pos            (15U)
+#define RCC_AHB5LPENSR_MCE2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */
+#define RCC_AHB5LPENSR_MCE2LPENS                RCC_AHB5LPENSR_MCE2LPENS_Msk         /*!< MCE2 enable  */
+#define RCC_AHB5LPENSR_MCE3LPENS_Pos            (16U)
+#define RCC_AHB5LPENSR_MCE3LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */
+#define RCC_AHB5LPENSR_MCE3LPENS                RCC_AHB5LPENSR_MCE3LPENS_Msk         /*!< MCE3 enable  */
+#define RCC_AHB5LPENSR_XSPI3LPENS_Pos           (17U)
+#define RCC_AHB5LPENSR_XSPI3LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENSR_XSPI3LPENS               RCC_AHB5LPENSR_XSPI3LPENS_Msk        /*!< XSPI3 enable  */
+#define RCC_AHB5LPENSR_MCE4LPENS_Pos            (18U)
+#define RCC_AHB5LPENSR_MCE4LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */
+#define RCC_AHB5LPENSR_MCE4LPENS                RCC_AHB5LPENSR_MCE4LPENS_Msk         /*!< MCE4 enable  */
+#define RCC_AHB5LPENSR_GFXMMULPENS_Pos          (19U)
+#define RCC_AHB5LPENSR_GFXMMULPENS_Msk          (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENSR_GFXMMULPENS              RCC_AHB5LPENSR_GFXMMULPENS_Msk       /*!< GFXMMU enable  */
+#define RCC_AHB5LPENSR_GPU2DLPENS_Pos           (20U)
+#define RCC_AHB5LPENSR_GPU2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENSR_GPU2DLPENS               RCC_AHB5LPENSR_GPU2DLPENS_Msk        /*!< GPU2D enable */
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos         (22U)
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk         (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENSR_ETH1MACLPENS             RCC_AHB5LPENSR_ETH1MACLPENS_Msk      /*!< ETH1MAC enable  */
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos          (23U)
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENSR_ETH1TXLPENS              RCC_AHB5LPENSR_ETH1TXLPENS_Msk       /*!< ETH1TX enable  */
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos          (24U)
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENSR_ETH1RXLPENS              RCC_AHB5LPENSR_ETH1RXLPENS_Msk       /*!< ETH1RX enable  */
+#define RCC_AHB5LPENSR_ETH1LPENS_Pos            (25U)
+#define RCC_AHB5LPENSR_ETH1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENSR_ETH1LPENS                RCC_AHB5LPENSR_ETH1LPENS_Msk         /*!< ETH1 enable  */
+#define RCC_AHB5LPENSR_OTG1LPENS_Pos            (26U)
+#define RCC_AHB5LPENSR_OTG1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENSR_OTG1LPENS                RCC_AHB5LPENSR_OTG1LPENS_Msk         /*!< OTG1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos         (27U)
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS             RCC_AHB5LPENSR_OTGPHY1LPENS_Msk      /*!< OTGPHY1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos         (28U)
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS             RCC_AHB5LPENSR_OTGPHY2LPENS_Msk      /*!< OTGPHY2 enable  */
+#define RCC_AHB5LPENSR_OTG2LPENS_Pos            (29U)
+#define RCC_AHB5LPENSR_OTG2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENSR_OTG2LPENS                RCC_AHB5LPENSR_OTG2LPENS_Msk         /*!< OTG2 enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR1 register  ****************/
+#define RCC_APB1LPENSR1_TIM2LPENS_Pos           (0U)
+#define RCC_APB1LPENSR1_TIM2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENSR1_TIM2LPENS               RCC_APB1LPENSR1_TIM2LPENS_Msk        /*!< TIM2 enable  */
+#define RCC_APB1LPENSR1_TIM3LPENS_Pos           (1U)
+#define RCC_APB1LPENSR1_TIM3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENSR1_TIM3LPENS               RCC_APB1LPENSR1_TIM3LPENS_Msk        /*!< TIM3 enable  */
+#define RCC_APB1LPENSR1_TIM4LPENS_Pos           (2U)
+#define RCC_APB1LPENSR1_TIM4LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENSR1_TIM4LPENS               RCC_APB1LPENSR1_TIM4LPENS_Msk        /*!< TIM4 enable  */
+#define RCC_APB1LPENSR1_TIM5LPENS_Pos           (3U)
+#define RCC_APB1LPENSR1_TIM5LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENSR1_TIM5LPENS               RCC_APB1LPENSR1_TIM5LPENS_Msk        /*!< TIM5 enable  */
+#define RCC_APB1LPENSR1_TIM6LPENS_Pos           (4U)
+#define RCC_APB1LPENSR1_TIM6LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENSR1_TIM6LPENS               RCC_APB1LPENSR1_TIM6LPENS_Msk        /*!< TIM6 enable  */
+#define RCC_APB1LPENSR1_TIM7LPENS_Pos           (5U)
+#define RCC_APB1LPENSR1_TIM7LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENSR1_TIM7LPENS               RCC_APB1LPENSR1_TIM7LPENS_Msk        /*!< TIM7 enable  */
+#define RCC_APB1LPENSR1_TIM12LPENS_Pos          (6U)
+#define RCC_APB1LPENSR1_TIM12LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENSR1_TIM12LPENS              RCC_APB1LPENSR1_TIM12LPENS_Msk       /*!< TIM12 enable  */
+#define RCC_APB1LPENSR1_TIM13LPENS_Pos          (7U)
+#define RCC_APB1LPENSR1_TIM13LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENSR1_TIM13LPENS              RCC_APB1LPENSR1_TIM13LPENS_Msk       /*!< TIM13 enable  */
+#define RCC_APB1LPENSR1_TIM14LPENS_Pos          (8U)
+#define RCC_APB1LPENSR1_TIM14LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR1_TIM14LPENS              RCC_APB1LPENSR1_TIM14LPENS_Msk       /*!< TIM14 enable  */
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos         (9U)
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENSR1_LPTIM1LPENS             RCC_APB1LPENSR1_LPTIM1LPENS_Msk      /*!< LPTIM1 enable  */
+#define RCC_APB1LPENSR1_WWDGLPENS_Pos           (11U)
+#define RCC_APB1LPENSR1_WWDGLPENS_Msk           (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENSR1_WWDGLPENS               RCC_APB1LPENSR1_WWDGLPENS_Msk        /*!< WWDG enable  */
+#define RCC_APB1LPENSR1_TIM10LPENS_Pos          (12U)
+#define RCC_APB1LPENSR1_TIM10LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENSR1_TIM10LPENS              RCC_APB1LPENSR1_TIM10LPENS_Msk       /*!< TIM10 enable  */
+#define RCC_APB1LPENSR1_TIM11LPENS_Pos          (13U)
+#define RCC_APB1LPENSR1_TIM11LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENSR1_TIM11LPENS              RCC_APB1LPENSR1_TIM11LPENS_Msk       /*!< TIM11 enable  */
+#define RCC_APB1LPENSR1_SPI2LPENS_Pos           (14U)
+#define RCC_APB1LPENSR1_SPI2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENSR1_SPI2LPENS               RCC_APB1LPENSR1_SPI2LPENS_Msk        /*!< SPI2 enable  */
+#define RCC_APB1LPENSR1_SPI3LPENS_Pos           (15U)
+#define RCC_APB1LPENSR1_SPI3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENSR1_SPI3LPENS               RCC_APB1LPENSR1_SPI3LPENS_Msk        /*!< SPI3 enable  */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos       (16U)
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk       (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS           RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk    /*!< SPDIFRX1 enable  */
+#define RCC_APB1LPENSR1_USART2LPENS_Pos         (17U)
+#define RCC_APB1LPENSR1_USART2LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENSR1_USART2LPENS             RCC_APB1LPENSR1_USART2LPENS_Msk      /*!< USART2 enable  */
+#define RCC_APB1LPENSR1_USART3LPENS_Pos         (18U)
+#define RCC_APB1LPENSR1_USART3LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENSR1_USART3LPENS             RCC_APB1LPENSR1_USART3LPENS_Msk      /*!< USART3 enable  */
+#define RCC_APB1LPENSR1_UART4LPENS_Pos          (19U)
+#define RCC_APB1LPENSR1_UART4LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENSR1_UART4LPENS              RCC_APB1LPENSR1_UART4LPENS_Msk       /*!< UART4 enable  */
+#define RCC_APB1LPENSR1_UART5LPENS_Pos          (20U)
+#define RCC_APB1LPENSR1_UART5LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENSR1_UART5LPENS              RCC_APB1LPENSR1_UART5LPENS_Msk       /*!< UART5 enable  */
+#define RCC_APB1LPENSR1_I2C1LPENS_Pos           (21U)
+#define RCC_APB1LPENSR1_I2C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENSR1_I2C1LPENS               RCC_APB1LPENSR1_I2C1LPENS_Msk        /*!< I2C1 enable  */
+#define RCC_APB1LPENSR1_I2C2LPENS_Pos           (22U)
+#define RCC_APB1LPENSR1_I2C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENSR1_I2C2LPENS               RCC_APB1LPENSR1_I2C2LPENS_Msk        /*!< I2C2 enable  */
+#define RCC_APB1LPENSR1_I2C3LPENS_Pos           (23U)
+#define RCC_APB1LPENSR1_I2C3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENSR1_I2C3LPENS               RCC_APB1LPENSR1_I2C3LPENS_Msk        /*!< I2C3 enable  */
+#define RCC_APB1LPENSR1_I3C1LPENS_Pos           (24U)
+#define RCC_APB1LPENSR1_I3C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENSR1_I3C1LPENS               RCC_APB1LPENSR1_I3C1LPENS_Msk        /*!< I3C1 enable  */
+#define RCC_APB1LPENSR1_I3C2LPENS_Pos           (25U)
+#define RCC_APB1LPENSR1_I3C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENSR1_I3C2LPENS               RCC_APB1LPENSR1_I3C2LPENS_Msk        /*!< I3C2 enable  */
+#define RCC_APB1LPENSR1_UART7LPENS_Pos          (30U)
+#define RCC_APB1LPENSR1_UART7LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENSR1_UART7LPENS              RCC_APB1LPENSR1_UART7LPENS_Msk       /*!< UART7 enable  */
+#define RCC_APB1LPENSR1_UART8LPENS_Pos          (31U)
+#define RCC_APB1LPENSR1_UART8LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENSR1_UART8LPENS              RCC_APB1LPENSR1_UART8LPENS_Msk       /*!< UART8 enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR2 register  ****************/
+#define RCC_APB1LPENSR2_MDIOSLPENS_Pos          (5U)
+#define RCC_APB1LPENSR2_MDIOSLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENSR2_MDIOSLPENS              RCC_APB1LPENSR2_MDIOSLPENS_Msk       /*!< MDIOS enable  */
+#define RCC_APB1LPENSR2_FDCANLPENS_Pos          (8U)
+#define RCC_APB1LPENSR2_FDCANLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR2_FDCANLPENS              RCC_APB1LPENSR2_FDCANLPENS_Msk       /*!< FDCAN enable  */
+#define RCC_APB1LPENSR2_UCPD1LPENS_Pos          (18U)
+#define RCC_APB1LPENSR2_UCPD1LPENS_Msk          (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENSR2_UCPD1LPENS              RCC_APB1LPENSR2_UCPD1LPENS_Msk       /*!< UCPD1 enable  */
+
+/****************  Bit definition for RCC_APB2LPENSR register  ****************/
+#define RCC_APB2LPENSR_TIM1LPENS_Pos            (0U)
+#define RCC_APB2LPENSR_TIM1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENSR_TIM1LPENS                RCC_APB2LPENSR_TIM1LPENS_Msk         /*!< TIM1 enable  */
+#define RCC_APB2LPENSR_TIM8LPENS_Pos            (1U)
+#define RCC_APB2LPENSR_TIM8LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENSR_TIM8LPENS                RCC_APB2LPENSR_TIM8LPENS_Msk         /*!< TIM8 enable  */
+#define RCC_APB2LPENSR_USART1LPENS_Pos          (4U)
+#define RCC_APB2LPENSR_USART1LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENSR_USART1LPENS              RCC_APB2LPENSR_USART1LPENS_Msk       /*!< USART1 enable  */
+#define RCC_APB2LPENSR_USART6LPENS_Pos          (5U)
+#define RCC_APB2LPENSR_USART6LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENSR_USART6LPENS              RCC_APB2LPENSR_USART6LPENS_Msk       /*!< USART6 enable  */
+#define RCC_APB2LPENSR_UART9LPENS_Pos           (6U)
+#define RCC_APB2LPENSR_UART9LPENS_Msk           (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENSR_UART9LPENS               RCC_APB2LPENSR_UART9LPENS_Msk        /*!< UART9 enable  */
+#define RCC_APB2LPENSR_USART10LPENS_Pos         (7U)
+#define RCC_APB2LPENSR_USART10LPENS_Msk         (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENSR_USART10LPENS             RCC_APB2LPENSR_USART10LPENS_Msk      /*!< USART10 enable  */
+#define RCC_APB2LPENSR_SPI1LPENS_Pos            (12U)
+#define RCC_APB2LPENSR_SPI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENSR_SPI1LPENS                RCC_APB2LPENSR_SPI1LPENS_Msk         /*!< SPI1 enable  */
+#define RCC_APB2LPENSR_SPI4LPENS_Pos            (13U)
+#define RCC_APB2LPENSR_SPI4LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENSR_SPI4LPENS                RCC_APB2LPENSR_SPI4LPENS_Msk         /*!< SPI4 enable  */
+#define RCC_APB2LPENSR_TIM18LPENS_Pos           (15U)
+#define RCC_APB2LPENSR_TIM18LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENSR_TIM18LPENS               RCC_APB2LPENSR_TIM18LPENS_Msk        /*!< TIM18 enable  */
+#define RCC_APB2LPENSR_TIM15LPENS_Pos           (16U)
+#define RCC_APB2LPENSR_TIM15LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENSR_TIM15LPENS               RCC_APB2LPENSR_TIM15LPENS_Msk        /*!< TIM15 enable  */
+#define RCC_APB2LPENSR_TIM16LPENS_Pos           (17U)
+#define RCC_APB2LPENSR_TIM16LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENSR_TIM16LPENS               RCC_APB2LPENSR_TIM16LPENS_Msk        /*!< TIM16 enable  */
+#define RCC_APB2LPENSR_TIM17LPENS_Pos           (18U)
+#define RCC_APB2LPENSR_TIM17LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENSR_TIM17LPENS               RCC_APB2LPENSR_TIM17LPENS_Msk        /*!< TIM17 enable  */
+#define RCC_APB2LPENSR_TIM9LPENS_Pos            (19U)
+#define RCC_APB2LPENSR_TIM9LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENSR_TIM9LPENS                RCC_APB2LPENSR_TIM9LPENS_Msk         /*!< TIM9 enable  */
+#define RCC_APB2LPENSR_SPI5LPENS_Pos            (20U)
+#define RCC_APB2LPENSR_SPI5LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENSR_SPI5LPENS                RCC_APB2LPENSR_SPI5LPENS_Msk         /*!< SPI5 enable  */
+#define RCC_APB2LPENSR_SAI1LPENS_Pos            (21U)
+#define RCC_APB2LPENSR_SAI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENSR_SAI1LPENS                RCC_APB2LPENSR_SAI1LPENS_Msk         /*!< SAI1 enable  */
+#define RCC_APB2LPENSR_SAI2LPENS_Pos            (22U)
+#define RCC_APB2LPENSR_SAI2LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENSR_SAI2LPENS                RCC_APB2LPENSR_SAI2LPENS_Msk         /*!< SAI2 enable  */
+
+/****************  Bit definition for RCC_APB3LPENSR register  ****************/
+#define RCC_APB3LPENSR_DFTLPENS_Pos             (2U)
+#define RCC_APB3LPENSR_DFTLPENS_Msk             (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENSR_DFTLPENS                 RCC_APB3LPENSR_DFTLPENS_Msk          /*!< DFT enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR1 register  ****************/
+#define RCC_APB4LPENSR1_HDPLPENS_Pos            (2U)
+#define RCC_APB4LPENSR1_HDPLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR1_HDPLPENS                RCC_APB4LPENSR1_HDPLPENS_Msk         /*!< HDP enable  */
+#define RCC_APB4LPENSR1_LPUART1LPENS_Pos        (3U)
+#define RCC_APB4LPENSR1_LPUART1LPENS_Msk        (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENSR1_LPUART1LPENS            RCC_APB4LPENSR1_LPUART1LPENS_Msk     /*!< LPUART1 enable  */
+#define RCC_APB4LPENSR1_SPI6LPENS_Pos           (5U)
+#define RCC_APB4LPENSR1_SPI6LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENSR1_SPI6LPENS               RCC_APB4LPENSR1_SPI6LPENS_Msk        /*!< SPI6 enable  */
+#define RCC_APB4LPENSR1_I2C4LPENS_Pos           (7U)
+#define RCC_APB4LPENSR1_I2C4LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENSR1_I2C4LPENS               RCC_APB4LPENSR1_I2C4LPENS_Msk        /*!< I2C4 enable  */
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos         (9U)
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENSR1_LPTIM2LPENS             RCC_APB4LPENSR1_LPTIM2LPENS_Msk      /*!< LPTIM2 enable  */
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos         (10U)
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENSR1_LPTIM3LPENS             RCC_APB4LPENSR1_LPTIM3LPENS_Msk      /*!< LPTIM3 enable  */
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos         (11U)
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENSR1_LPTIM4LPENS             RCC_APB4LPENSR1_LPTIM4LPENS_Msk      /*!< LPTIM4 enable  */
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos         (12U)
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENSR1_LPTIM5LPENS             RCC_APB4LPENSR1_LPTIM5LPENS_Msk      /*!< LPTIM5 enable  */
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos        (15U)
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk        (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENSR1_VREFBUFLPENS            RCC_APB4LPENSR1_VREFBUFLPENS_Msk     /*!< VREFBUF enable  */
+#define RCC_APB4LPENSR1_RTCLPENS_Pos            (16U)
+#define RCC_APB4LPENSR1_RTCLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENSR1_RTCLPENS                RCC_APB4LPENSR1_RTCLPENS_Msk         /*!< RTC enable  */
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos         (17U)
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk         (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENSR1_RTCAPBLPENS             RCC_APB4LPENSR1_RTCAPBLPENS_Msk      /*!< RTCAPB enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR2 register  ****************/
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos         (0U)
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk         (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENSR2_SYSCFGLPENS             RCC_APB4LPENSR2_SYSCFGLPENS_Msk      /*!< SYSCFG enable  */
+#define RCC_APB4LPENSR2_BSECLPENS_Pos           (1U)
+#define RCC_APB4LPENSR2_BSECLPENS_Msk           (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENSR2_BSECLPENS               RCC_APB4LPENSR2_BSECLPENS_Msk        /*!< BSEC enable  */
+#define RCC_APB4LPENSR2_DTSLPENS_Pos            (2U)
+#define RCC_APB4LPENSR2_DTSLPENS_Msk            (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR2_DTSLPENS                RCC_APB4LPENSR2_DTSLPENS_Msk         /*!< DTS enable  */
+
+/****************  Bit definition for RCC_APB5LPENSR register  ****************/
+#define RCC_APB5LPENSR_LTDCLPENS_Pos            (1U)
+#define RCC_APB5LPENSR_LTDCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENSR_LTDCLPENS                RCC_APB5LPENSR_LTDCLPENS_Msk         /*!< LTDC enable */
+#define RCC_APB5LPENSR_DCMIPPLPENS_Pos          (2U)
+#define RCC_APB5LPENSR_DCMIPPLPENS_Msk          (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENSR_DCMIPPLPENS              RCC_APB5LPENSR_DCMIPPLPENS_Msk       /*!< DCMIPP enable */
+#define RCC_APB5LPENSR_GFXTIMLPENS_Pos          (4U)
+#define RCC_APB5LPENSR_GFXTIMLPENS_Msk          (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENSR_GFXTIMLPENS              RCC_APB5LPENSR_GFXTIMLPENS_Msk       /*!< GFXTIM enable */
+#define RCC_APB5LPENSR_VENCLPENS_Pos            (5U)
+#define RCC_APB5LPENSR_VENCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENSR_VENCLPENS                RCC_APB5LPENSR_VENCLPENS_Msk         /*!< VENC enable */
+#define RCC_APB5LPENSR_CSILPENS_Pos             (6U)
+#define RCC_APB5LPENSR_CSILPENS_Msk             (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENSR_CSILPENS                 RCC_APB5LPENSR_CSILPENS_Msk          /*!< CSI enable */
+
+/****************  Bit definition for RCC_PRIVCFGSR0 register  ****************/
+#define RCC_PRIVCFGSR0_LSIPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR0_LSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR0_LSIPRIVS                 RCC_PRIVCFGSR0_LSIPRIVS_Msk          /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_LSEPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR0_LSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR0_LSEPRIVS                 RCC_PRIVCFGSR0_LSEPRIVS_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_MSIPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR0_MSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR0_MSIPRIVS                 RCC_PRIVCFGSR0_MSIPRIVS_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSIPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR0_HSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR0_HSIPRIVS                 RCC_PRIVCFGSR0_HSIPRIVS_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSEPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR0_HSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR0_HSEPRIVS                 RCC_PRIVCFGSR0_HSEPRIVS_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR0 register  *****************/
+#define RCC_PUBCFGSR0_LSIPUBS_Pos               (0U)
+#define RCC_PUBCFGSR0_LSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR0_LSIPUBS                   RCC_PUBCFGSR0_LSIPUBS_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_LSEPUBS_Pos               (1U)
+#define RCC_PUBCFGSR0_LSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR0_LSEPUBS                   RCC_PUBCFGSR0_LSEPUBS_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_MSIPUBS_Pos               (2U)
+#define RCC_PUBCFGSR0_MSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR0_MSIPUBS                   RCC_PUBCFGSR0_MSIPUBS_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSIPUBS_Pos               (3U)
+#define RCC_PUBCFGSR0_HSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR0_HSIPUBS                   RCC_PUBCFGSR0_HSIPUBS_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSEPUBS_Pos               (4U)
+#define RCC_PUBCFGSR0_HSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR0_HSEPUBS                   RCC_PUBCFGSR0_HSEPUBS_Msk            /*!< Public protection of he HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR1 register  ****************/
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos            (0U)
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGSR1_PLL1PRIVS                RCC_PRIVCFGSR1_PLL1PRIVS_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos            (1U)
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGSR1_PLL2PRIVS                RCC_PRIVCFGSR1_PLL2PRIVS_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR1_PLL3PRIVS                RCC_PRIVCFGSR1_PLL3PRIVS_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR1_PLL4PRIVS                RCC_PRIVCFGSR1_PLL4PRIVS_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR1 register  *****************/
+#define RCC_PUBCFGSR1_PLL1PUBS_Pos              (0U)
+#define RCC_PUBCFGSR1_PLL1PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGSR1_PLL1PUBS                  RCC_PUBCFGSR1_PLL1PUBS_Msk           /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL2PUBS_Pos              (1U)
+#define RCC_PUBCFGSR1_PLL2PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR1_PLL2PUBS                  RCC_PUBCFGSR1_PLL2PUBS_Msk           /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL3PUBS_Pos              (2U)
+#define RCC_PUBCFGSR1_PLL3PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR1_PLL3PUBS                  RCC_PUBCFGSR1_PLL3PUBS_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL4PUBS_Pos              (3U)
+#define RCC_PUBCFGSR1_PLL4PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR1_PLL4PUBS                  RCC_PUBCFGSR1_PLL4PUBS_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR2 register  ****************/
+#define RCC_PRIVCFGSR2_IC1PRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR2_IC1PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR2_IC1PRIVS                 RCC_PRIVCFGSR2_IC1PRIVS_Msk          /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC2PRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR2_IC2PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR2_IC2PRIVS                 RCC_PRIVCFGSR2_IC2PRIVS_Msk          /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC3PRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR2_IC3PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR2_IC3PRIVS                 RCC_PRIVCFGSR2_IC3PRIVS_Msk          /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC4PRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR2_IC4PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR2_IC4PRIVS                 RCC_PRIVCFGSR2_IC4PRIVS_Msk          /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC5PRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR2_IC5PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR2_IC5PRIVS                 RCC_PRIVCFGSR2_IC5PRIVS_Msk          /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC6PRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR2_IC6PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR2_IC6PRIVS                 RCC_PRIVCFGSR2_IC6PRIVS_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC7PRIVS_Pos             (6U)
+#define RCC_PRIVCFGSR2_IC7PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGSR2_IC7PRIVS                 RCC_PRIVCFGSR2_IC7PRIVS_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC8PRIVS_Pos             (7U)
+#define RCC_PRIVCFGSR2_IC8PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGSR2_IC8PRIVS                 RCC_PRIVCFGSR2_IC8PRIVS_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC9PRIVS_Pos             (8U)
+#define RCC_PRIVCFGSR2_IC9PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGSR2_IC9PRIVS                 RCC_PRIVCFGSR2_IC9PRIVS_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC10PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR2_IC10PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR2_IC10PRIVS                RCC_PRIVCFGSR2_IC10PRIVS_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC11PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR2_IC11PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR2_IC11PRIVS                RCC_PRIVCFGSR2_IC11PRIVS_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC12PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR2_IC12PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR2_IC12PRIVS                RCC_PRIVCFGSR2_IC12PRIVS_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC13PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR2_IC13PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR2_IC13PRIVS                RCC_PRIVCFGSR2_IC13PRIVS_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC14PRIVS_Pos            (13U)
+#define RCC_PRIVCFGSR2_IC14PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGSR2_IC14PRIVS                RCC_PRIVCFGSR2_IC14PRIVS_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC15PRIVS_Pos            (14U)
+#define RCC_PRIVCFGSR2_IC15PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGSR2_IC15PRIVS                RCC_PRIVCFGSR2_IC15PRIVS_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC16PRIVS_Pos            (15U)
+#define RCC_PRIVCFGSR2_IC16PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGSR2_IC16PRIVS                RCC_PRIVCFGSR2_IC16PRIVS_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC17PRIVS_Pos            (16U)
+#define RCC_PRIVCFGSR2_IC17PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGSR2_IC17PRIVS                RCC_PRIVCFGSR2_IC17PRIVS_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC18PRIVS_Pos            (17U)
+#define RCC_PRIVCFGSR2_IC18PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGSR2_IC18PRIVS                RCC_PRIVCFGSR2_IC18PRIVS_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC19PRIVS_Pos            (18U)
+#define RCC_PRIVCFGSR2_IC19PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGSR2_IC19PRIVS                RCC_PRIVCFGSR2_IC19PRIVS_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC20PRIVS_Pos            (19U)
+#define RCC_PRIVCFGSR2_IC20PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGSR2_IC20PRIVS                RCC_PRIVCFGSR2_IC20PRIVS_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR2 register  *****************/
+#define RCC_PUBCFGSR2_IC1PUBS_Pos               (0U)
+#define RCC_PUBCFGSR2_IC1PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR2_IC1PUBS                   RCC_PUBCFGSR2_IC1PUBS_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC2PUBS_Pos               (1U)
+#define RCC_PUBCFGSR2_IC2PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR2_IC2PUBS                   RCC_PUBCFGSR2_IC2PUBS_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC3PUBS_Pos               (2U)
+#define RCC_PUBCFGSR2_IC3PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR2_IC3PUBS                   RCC_PUBCFGSR2_IC3PUBS_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC4PUBS_Pos               (3U)
+#define RCC_PUBCFGSR2_IC4PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR2_IC4PUBS                   RCC_PUBCFGSR2_IC4PUBS_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC5PUBS_Pos               (4U)
+#define RCC_PUBCFGSR2_IC5PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR2_IC5PUBS                   RCC_PUBCFGSR2_IC5PUBS_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC6PUBS_Pos               (5U)
+#define RCC_PUBCFGSR2_IC6PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR2_IC6PUBS                   RCC_PUBCFGSR2_IC6PUBS_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC7PUBS_Pos               (6U)
+#define RCC_PUBCFGSR2_IC7PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR2_IC7PUBS                   RCC_PUBCFGSR2_IC7PUBS_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC8PUBS_Pos               (7U)
+#define RCC_PUBCFGSR2_IC8PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGSR2_IC8PUBS                   RCC_PUBCFGSR2_IC8PUBS_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC9PUBS_Pos               (8U)
+#define RCC_PUBCFGSR2_IC9PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGSR2_IC9PUBS                   RCC_PUBCFGSR2_IC9PUBS_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC10PUBS_Pos              (9U)
+#define RCC_PUBCFGSR2_IC10PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR2_IC10PUBS                  RCC_PUBCFGSR2_IC10PUBS_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC11PUBS_Pos              (10U)
+#define RCC_PUBCFGSR2_IC11PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR2_IC11PUBS                  RCC_PUBCFGSR2_IC11PUBS_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC12PUBS_Pos              (11U)
+#define RCC_PUBCFGSR2_IC12PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR2_IC12PUBS                  RCC_PUBCFGSR2_IC12PUBS_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC13PUBS_Pos              (12U)
+#define RCC_PUBCFGSR2_IC13PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR2_IC13PUBS                  RCC_PUBCFGSR2_IC13PUBS_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC14PUBS_Pos              (13U)
+#define RCC_PUBCFGSR2_IC14PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGSR2_IC14PUBS                  RCC_PUBCFGSR2_IC14PUBS_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC15PUBS_Pos              (14U)
+#define RCC_PUBCFGSR2_IC15PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGSR2_IC15PUBS                  RCC_PUBCFGSR2_IC15PUBS_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC16PUBS_Pos              (15U)
+#define RCC_PUBCFGSR2_IC16PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGSR2_IC16PUBS                  RCC_PUBCFGSR2_IC16PUBS_Msk           /*!< Public protection of th IC16 configuration bits (enable, ready, divider */
+#define RCC_PUBCFGSR2_IC17PUBS_Pos              (16U)
+#define RCC_PUBCFGSR2_IC17PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGSR2_IC17PUBS                  RCC_PUBCFGSR2_IC17PUBS_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC18PUBS_Pos              (17U)
+#define RCC_PUBCFGSR2_IC18PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGSR2_IC18PUBS                  RCC_PUBCFGSR2_IC18PUBS_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC19PUBS_Pos              (18U)
+#define RCC_PUBCFGSR2_IC19PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGSR2_IC19PUBS                  RCC_PUBCFGSR2_IC19PUBS_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC20PUBS_Pos              (19U)
+#define RCC_PUBCFGSR2_IC20PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGSR2_IC20PUBS                  RCC_PUBCFGSR2_IC20PUBS_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR3 register  ****************/
+#define RCC_PRIVCFGSR3_MODPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR3_MODPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR3_MODPRIVS                 RCC_PRIVCFGSR3_MODPRIVS_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_SYSPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR3_SYSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR3_SYSPRIVS                 RCC_PRIVCFGSR3_SYSPRIVS_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_BUSPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR3_BUSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR3_BUSPRIVS                 RCC_PRIVCFGSR3_BUSPRIVS_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_PERPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR3_PERPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR3_PERPRIVS                 RCC_PRIVCFGSR3_PERPRIVS_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_INTPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR3_INTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR3_INTPRIVS                 RCC_PRIVCFGSR3_INTPRIVS_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_RSTPRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR3_RSTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR3_RSTPRIVS                 RCC_PRIVCFGSR3_RSTPRIVS_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR3 register  *****************/
+#define RCC_PUBCFGSR3_MODPUBS_Pos               (0U)
+#define RCC_PUBCFGSR3_MODPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR3_MODPUBS                   RCC_PUBCFGSR3_MODPUBS_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_SYSPUBS_Pos               (1U)
+#define RCC_PUBCFGSR3_SYSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR3_SYSPUBS                   RCC_PUBCFGSR3_SYSPUBS_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_BUSPUBS_Pos               (2U)
+#define RCC_PUBCFGSR3_BUSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR3_BUSPUBS                   RCC_PUBCFGSR3_BUSPUBS_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_PERPUBS_Pos               (3U)
+#define RCC_PUBCFGSR3_PERPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR3_PERPUBS                   RCC_PUBCFGSR3_PERPUBS_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_INTPUBS_Pos               (4U)
+#define RCC_PUBCFGSR3_INTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR3_INTPUBS                   RCC_PUBCFGSR3_INTPUBS_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_RSTPUBS_Pos               (5U)
+#define RCC_PUBCFGSR3_RSTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR3_RSTPUBS                   RCC_PUBCFGSR3_RSTPUBS_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR4 register  ****************/
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos           (0U)
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk           (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGSR4_ACLKNPRIVS               RCC_PRIVCFGSR4_ACLKNPRIVS_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos          (1U)
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk          (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS              RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk       /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR4_AHBMPRIVS                RCC_PRIVCFGSR4_AHBMPRIVS_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR4_AHB1PRIVS                RCC_PRIVCFGSR4_AHB1PRIVS_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos            (4U)
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGSR4_AHB2PRIVS                RCC_PRIVCFGSR4_AHB2PRIVS_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos            (5U)
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGSR4_AHB3PRIVS                RCC_PRIVCFGSR4_AHB3PRIVS_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos            (6U)
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGSR4_AHB4PRIVS                RCC_PRIVCFGSR4_AHB4PRIVS_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos            (7U)
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGSR4_AHB5PRIVS                RCC_PRIVCFGSR4_AHB5PRIVS_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB1PRIVS_Pos            (8U)
+#define RCC_PRIVCFGSR4_APB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGSR4_APB1PRIVS                RCC_PRIVCFGSR4_APB1PRIVS_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB2PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR4_APB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR4_APB2PRIVS                RCC_PRIVCFGSR4_APB2PRIVS_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB3PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR4_APB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR4_APB3PRIVS                RCC_PRIVCFGSR4_APB3PRIVS_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB4PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR4_APB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR4_APB4PRIVS                RCC_PRIVCFGSR4_APB4PRIVS_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB5PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR4_APB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR4_APB5PRIVS                RCC_PRIVCFGSR4_APB5PRIVS_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_NOCPRIVS_Pos             (13U)
+#define RCC_PRIVCFGSR4_NOCPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGSR4_NOCPRIVS                 RCC_PRIVCFGSR4_NOCPRIVS_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR4 register  *****************/
+#define RCC_PUBCFGSR4_ACLKNPUBS_Pos             (0U)
+#define RCC_PUBCFGSR4_ACLKNPUBS_Msk             (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGSR4_ACLKNPUBS                 RCC_PUBCFGSR4_ACLKNPUBS_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos            (1U)
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk            (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR4_ACLKNCPUBS                RCC_PUBCFGSR4_ACLKNCPUBS_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHBMPUBS_Pos              (2U)
+#define RCC_PUBCFGSR4_AHBMPUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR4_AHBMPUBS                  RCC_PUBCFGSR4_AHBMPUBS_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB1PUBS_Pos              (3U)
+#define RCC_PUBCFGSR4_AHB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR4_AHB1PUBS                  RCC_PUBCFGSR4_AHB1PUBS_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB2PUBS_Pos              (4U)
+#define RCC_PUBCFGSR4_AHB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGSR4_AHB2PUBS                  RCC_PUBCFGSR4_AHB2PUBS_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB3PUBS_Pos              (5U)
+#define RCC_PUBCFGSR4_AHB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGSR4_AHB3PUBS                  RCC_PUBCFGSR4_AHB3PUBS_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB4PUBS_Pos              (6U)
+#define RCC_PUBCFGSR4_AHB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGSR4_AHB4PUBS                  RCC_PUBCFGSR4_AHB4PUBS_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB5PUBS_Pos              (7U)
+#define RCC_PUBCFGSR4_AHB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGSR4_AHB5PUBS                  RCC_PUBCFGSR4_AHB5PUBS_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB1PUBS_Pos              (8U)
+#define RCC_PUBCFGSR4_APB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGSR4_APB1PUBS                  RCC_PUBCFGSR4_APB1PUBS_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB2PUBS_Pos              (9U)
+#define RCC_PUBCFGSR4_APB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR4_APB2PUBS                  RCC_PUBCFGSR4_APB2PUBS_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB3PUBS_Pos              (10U)
+#define RCC_PUBCFGSR4_APB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR4_APB3PUBS                  RCC_PUBCFGSR4_APB3PUBS_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB4PUBS_Pos              (11U)
+#define RCC_PUBCFGSR4_APB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR4_APB4PUBS                  RCC_PUBCFGSR4_APB4PUBS_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB5PUBS_Pos              (12U)
+#define RCC_PUBCFGSR4_APB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR4_APB5PUBS                  RCC_PUBCFGSR4_APB5PUBS_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_NOCPUBS_Pos               (13U)
+#define RCC_PUBCFGSR4_NOCPUBS_Msk               (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGSR4_NOCPUBS                   RCC_PUBCFGSR4_NOCPUBS_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR5 register  *****************/
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos          (0U)
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGSR5_AXISRAM3PUBS              RCC_PUBCFGSR5_AXISRAM3PUBS_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos          (1U)
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS              RCC_PUBCFGSR5_AXISRAM4PUBS_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos          (2U)
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS              RCC_PUBCFGSR5_AXISRAM5PUBS_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos          (3U)
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS              RCC_PUBCFGSR5_AXISRAM6PUBS_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos          (4U)
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS              RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos          (5U)
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS              RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos           (6U)
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS               RCC_PUBCFGSR5_BKPSRAMPUBS_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos          (7U)
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS              RCC_PUBCFGSR5_AXISRAM1PUBS_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos          (8U)
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS              RCC_PUBCFGSR5_AXISRAM2PUBS_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos           (9U)
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS               RCC_PUBCFGSR5_FLEXRAMPUBS_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos           (11U)
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGSR5_VENCRAMPUBS               RCC_PUBCFGSR5_VENCRAMPUBS_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+/*******************  Bit definition for RCC_CCR register  ********************/
+#define RCC_CCR_LSIONC_Pos                      (0U)
+#define RCC_CCR_LSIONC_Msk                      (0x1UL << RCC_CCR_LSIONC_Pos)         /*!< 0x00000001 */
+#define RCC_CCR_LSIONC                          RCC_CCR_LSIONC_Msk                   /*!< LSI oscillator enable */
+#define RCC_CCR_LSEONC_Pos                      (1U)
+#define RCC_CCR_LSEONC_Msk                      (0x1UL << RCC_CCR_LSEONC_Pos)         /*!< 0x00000002 */
+#define RCC_CCR_LSEONC                          RCC_CCR_LSEONC_Msk                   /*!< LSE oscillator enable */
+#define RCC_CCR_MSIONC_Pos                      (2U)
+#define RCC_CCR_MSIONC_Msk                      (0x1UL << RCC_CCR_MSIONC_Pos)         /*!< 0x00000004 */
+#define RCC_CCR_MSIONC                          RCC_CCR_MSIONC_Msk                   /*!< MSI oscillator enable */
+#define RCC_CCR_HSIONC_Pos                      (3U)
+#define RCC_CCR_HSIONC_Msk                      (0x1UL << RCC_CCR_HSIONC_Pos)         /*!< 0x00000008 */
+#define RCC_CCR_HSIONC                          RCC_CCR_HSIONC_Msk                   /*!< HSI oscillator enable */
+#define RCC_CCR_HSEONC_Pos                      (4U)
+#define RCC_CCR_HSEONC_Msk                      (0x1UL << RCC_CCR_HSEONC_Pos)         /*!< 0x00000010 */
+#define RCC_CCR_HSEONC                          RCC_CCR_HSEONC_Msk                   /*!< HSE oscillator enable */
+#define RCC_CCR_PLL1ONC_Pos                     (8U)
+#define RCC_CCR_PLL1ONC_Msk                     (0x1UL << RCC_CCR_PLL1ONC_Pos)        /*!< 0x00000100 */
+#define RCC_CCR_PLL1ONC                         RCC_CCR_PLL1ONC_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CCR_PLL2ONC_Pos                     (9U)
+#define RCC_CCR_PLL2ONC_Msk                     (0x1UL << RCC_CCR_PLL2ONC_Pos)        /*!< 0x00000200 */
+#define RCC_CCR_PLL2ONC                         RCC_CCR_PLL2ONC_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CCR_PLL3ONC_Pos                     (10U)
+#define RCC_CCR_PLL3ONC_Msk                     (0x1UL << RCC_CCR_PLL3ONC_Pos)        /*!< 0x00000400 */
+#define RCC_CCR_PLL3ONC                         RCC_CCR_PLL3ONC_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CCR_PLL4ONC_Pos                     (11U)
+#define RCC_CCR_PLL4ONC_Msk                     (0x1UL << RCC_CCR_PLL4ONC_Pos)        /*!< 0x00000800 */
+#define RCC_CCR_PLL4ONC                         RCC_CCR_PLL4ONC_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCCR register  ******************/
+#define RCC_STOPCCR_MSISTOPENC_Pos              (0U)
+#define RCC_STOPCCR_MSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */
+#define RCC_STOPCCR_MSISTOPENC                  RCC_STOPCCR_MSISTOPENC_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCCR_HSISTOPENC_Pos              (1U)
+#define RCC_STOPCCR_HSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */
+#define RCC_STOPCCR_HSISTOPENC                  RCC_STOPCCR_HSISTOPENC_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTCR register  *****************/
+#define RCC_MISCRSTCR_DBGRSTC_Pos               (0U)
+#define RCC_MISCRSTCR_DBGRSTC_Msk               (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTCR_DBGRSTC                   RCC_MISCRSTCR_DBGRSTC_Msk            /*!< DBG reset */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos          (4U)
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC              RCC_MISCRSTCR_XSPIPHY1RSTC_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos          (5U)
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC              RCC_MISCRSTCR_XSPIPHY2RSTC_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos         (7U)
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC             RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos         (8U)
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC             RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTCR register  *****************/
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos           (0U)
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTCR_AXISRAM3RSTC               RCC_MEMRSTCR_AXISRAM3RSTC_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos           (1U)
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTCR_AXISRAM4RSTC               RCC_MEMRSTCR_AXISRAM4RSTC_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos           (2U)
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTCR_AXISRAM5RSTC               RCC_MEMRSTCR_AXISRAM5RSTC_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos           (3U)
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTCR_AXISRAM6RSTC               RCC_MEMRSTCR_AXISRAM6RSTC_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos           (4U)
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC               RCC_MEMRSTCR_AHBSRAM1RSTC_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos           (5U)
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC               RCC_MEMRSTCR_AHBSRAM2RSTC_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos           (7U)
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTCR_AXISRAM1RSTC               RCC_MEMRSTCR_AXISRAM1RSTC_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos           (8U)
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTCR_AXISRAM2RSTC               RCC_MEMRSTCR_AXISRAM2RSTC_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos            (9U)
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTCR_FLEXRAMRSTC                RCC_MEMRSTCR_FLEXRAMRSTC_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTCR_VENCRAMRSTC_Pos            (11U)
+#define RCC_MEMRSTCR_VENCRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTCR_VENCRAMRSTC                RCC_MEMRSTCR_VENCRAMRSTC_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTCR_BOOTROMRSTC_Pos            (12U)
+#define RCC_MEMRSTCR_BOOTROMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTCR_BOOTROMRSTC                RCC_MEMRSTCR_BOOTROMRSTC_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTCR register  *****************/
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos            (4U)
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk            (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTCR_GPDMA1RSTC                RCC_AHB1RSTCR_GPDMA1RSTC_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTCR_ADC12RSTC_Pos             (5U)
+#define RCC_AHB1RSTCR_ADC12RSTC_Msk             (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTCR_ADC12RSTC                 RCC_AHB1RSTCR_ADC12RSTC_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTCR register  *****************/
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos            (12U)
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk            (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTCR_RAMCFGRSTC                RCC_AHB2RSTCR_RAMCFGRSTC_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTCR_MDF1RSTC_Pos              (16U)
+#define RCC_AHB2RSTCR_MDF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTCR_MDF1RSTC                  RCC_AHB2RSTCR_MDF1RSTC_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTCR_ADF1RSTC_Pos              (17U)
+#define RCC_AHB2RSTCR_ADF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTCR_ADF1RSTC                  RCC_AHB2RSTCR_ADF1RSTC_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTCR register  *****************/
+#define RCC_AHB3RSTCR_RNGRSTC_Pos               (0U)
+#define RCC_AHB3RSTCR_RNGRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTCR_RNGRSTC                   RCC_AHB3RSTCR_RNGRSTC_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTCR_HASHRSTC_Pos              (1U)
+#define RCC_AHB3RSTCR_HASHRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTCR_HASHRSTC                  RCC_AHB3RSTCR_HASHRSTC_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTCR_CRYPRSTC_Pos              (2U)
+#define RCC_AHB3RSTCR_CRYPRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_AHB3RSTCR_CRYPRSTC                  RCC_AHB3RSTCR_CRYPRSTC_Msk           /*!< CRYP reset */
+#define RCC_AHB3RSTCR_SAESRSTC_Pos              (4U)
+#define RCC_AHB3RSTCR_SAESRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */
+#define RCC_AHB3RSTCR_SAESRSTC                  RCC_AHB3RSTCR_SAESRSTC_Msk           /*!< SAES reset */
+#define RCC_AHB3RSTCR_PKARSTC_Pos               (8U)
+#define RCC_AHB3RSTCR_PKARSTC_Msk               (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTCR_PKARSTC                   RCC_AHB3RSTCR_PKARSTC_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTCR_IACRSTC_Pos               (10U)
+#define RCC_AHB3RSTCR_IACRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTCR_IACRSTC                   RCC_AHB3RSTCR_IACRSTC_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTCR register  *****************/
+#define RCC_AHB4RSTCR_GPIOARSTC_Pos             (0U)
+#define RCC_AHB4RSTCR_GPIOARSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTCR_GPIOARSTC                 RCC_AHB4RSTCR_GPIOARSTC_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTCR_GPIOBRSTC_Pos             (1U)
+#define RCC_AHB4RSTCR_GPIOBRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTCR_GPIOBRSTC                 RCC_AHB4RSTCR_GPIOBRSTC_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTCR_GPIOCRSTC_Pos             (2U)
+#define RCC_AHB4RSTCR_GPIOCRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTCR_GPIOCRSTC                 RCC_AHB4RSTCR_GPIOCRSTC_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTCR_GPIODRSTC_Pos             (3U)
+#define RCC_AHB4RSTCR_GPIODRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTCR_GPIODRSTC                 RCC_AHB4RSTCR_GPIODRSTC_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTCR_GPIOERSTC_Pos             (4U)
+#define RCC_AHB4RSTCR_GPIOERSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTCR_GPIOERSTC                 RCC_AHB4RSTCR_GPIOERSTC_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTCR_GPIOFRSTC_Pos             (5U)
+#define RCC_AHB4RSTCR_GPIOFRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTCR_GPIOFRSTC                 RCC_AHB4RSTCR_GPIOFRSTC_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTCR_GPIOGRSTC_Pos             (6U)
+#define RCC_AHB4RSTCR_GPIOGRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTCR_GPIOGRSTC                 RCC_AHB4RSTCR_GPIOGRSTC_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTCR_GPIOHRSTC_Pos             (7U)
+#define RCC_AHB4RSTCR_GPIOHRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTCR_GPIOHRSTC                 RCC_AHB4RSTCR_GPIOHRSTC_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTCR_GPIONRSTC_Pos             (13U)
+#define RCC_AHB4RSTCR_GPIONRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTCR_GPIONRSTC                 RCC_AHB4RSTCR_GPIONRSTC_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTCR_GPIOORSTC_Pos             (14U)
+#define RCC_AHB4RSTCR_GPIOORSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTCR_GPIOORSTC                 RCC_AHB4RSTCR_GPIOORSTC_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTCR_GPIOPRSTC_Pos             (15U)
+#define RCC_AHB4RSTCR_GPIOPRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTCR_GPIOPRSTC                 RCC_AHB4RSTCR_GPIOPRSTC_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTCR_GPIOQRSTC_Pos             (16U)
+#define RCC_AHB4RSTCR_GPIOQRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTCR_GPIOQRSTC                 RCC_AHB4RSTCR_GPIOQRSTC_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTCR_PWRRSTC_Pos               (18U)
+#define RCC_AHB4RSTCR_PWRRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTCR_PWRRSTC                   RCC_AHB4RSTCR_PWRRSTC_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTCR_CRCRSTC_Pos               (19U)
+#define RCC_AHB4RSTCR_CRCRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTCR_CRCRSTC                   RCC_AHB4RSTCR_CRCRSTC_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTCR register  *****************/
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos            (0U)
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTCR_HPDMA1RSTC                RCC_AHB5RSTCR_HPDMA1RSTC_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTCR_DMA2DRSTC_Pos             (1U)
+#define RCC_AHB5RSTCR_DMA2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTCR_DMA2DRSTC                 RCC_AHB5RSTCR_DMA2DRSTC_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTCR_JPEGRSTC_Pos              (3U)
+#define RCC_AHB5RSTCR_JPEGRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTCR_JPEGRSTC                  RCC_AHB5RSTCR_JPEGRSTC_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTCR_FMCRSTC_Pos               (4U)
+#define RCC_AHB5RSTCR_FMCRSTC_Msk               (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTCR_FMCRSTC                   RCC_AHB5RSTCR_FMCRSTC_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTCR_XSPI1RSTC_Pos             (5U)
+#define RCC_AHB5RSTCR_XSPI1RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTCR_XSPI1RSTC                 RCC_AHB5RSTCR_XSPI1RSTC_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTCR_PSSIRSTC_Pos              (6U)
+#define RCC_AHB5RSTCR_PSSIRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTCR_PSSIRSTC                  RCC_AHB5RSTCR_PSSIRSTC_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos            (7U)
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTCR_SDMMC2RSTC                RCC_AHB5RSTCR_SDMMC2RSTC_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos            (8U)
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTCR_SDMMC1RSTC                RCC_AHB5RSTCR_SDMMC1RSTC_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTCR_XSPI2RSTC_Pos             (12U)
+#define RCC_AHB5RSTCR_XSPI2RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTCR_XSPI2RSTC                 RCC_AHB5RSTCR_XSPI2RSTC_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTCR_XSPIMRSTC_Pos             (13U)
+#define RCC_AHB5RSTCR_XSPIMRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTCR_XSPIMRSTC                 RCC_AHB5RSTCR_XSPIMRSTC_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTCR_XSPI3RSTC_Pos             (17U)
+#define RCC_AHB5RSTCR_XSPI3RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTCR_XSPI3RSTC                 RCC_AHB5RSTCR_XSPI3RSTC_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTCR_GFXMMURSTC_Pos            (19U)
+#define RCC_AHB5RSTCR_GFXMMURSTC_Msk            (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTCR_GFXMMURSTC                RCC_AHB5RSTCR_GFXMMURSTC_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTCR_GPU2DRSTC_Pos             (20U)
+#define RCC_AHB5RSTCR_GPU2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTCR_GPU2DRSTC                 RCC_AHB5RSTCR_GPU2DRSTC_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos        (23U)
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC            RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos        (24U)
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC            RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTCR_ETH1RSTC_Pos              (25U)
+#define RCC_AHB5RSTCR_ETH1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTCR_ETH1RSTC                  RCC_AHB5RSTCR_ETH1RSTC_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTCR_OTG1RSTC_Pos              (26U)
+#define RCC_AHB5RSTCR_OTG1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTCR_OTG1RSTC                  RCC_AHB5RSTCR_OTG1RSTC_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos           (27U)
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC               RCC_AHB5RSTCR_OTGPHY1RSTC_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos           (28U)
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC               RCC_AHB5RSTCR_OTGPHY2RSTC_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTCR_OTG2RSTC_Pos              (29U)
+#define RCC_AHB5RSTCR_OTG2RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTCR_OTG2RSTC                  RCC_AHB5RSTCR_OTG2RSTC_Msk           /*!< OTG2 reset */
+
+/****************  Bit definition for RCC_APB1RSTCR1 register  ****************/
+#define RCC_APB1RSTCR1_TIM2RSTC_Pos             (0U)
+#define RCC_APB1RSTCR1_TIM2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTCR1_TIM2RSTC                 RCC_APB1RSTCR1_TIM2RSTC_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTCR1_TIM3RSTC_Pos             (1U)
+#define RCC_APB1RSTCR1_TIM3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTCR1_TIM3RSTC                 RCC_APB1RSTCR1_TIM3RSTC_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTCR1_TIM4RSTC_Pos             (2U)
+#define RCC_APB1RSTCR1_TIM4RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTCR1_TIM4RSTC                 RCC_APB1RSTCR1_TIM4RSTC_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTCR1_TIM5RSTC_Pos             (3U)
+#define RCC_APB1RSTCR1_TIM5RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTCR1_TIM5RSTC                 RCC_APB1RSTCR1_TIM5RSTC_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTCR1_TIM6RSTC_Pos             (4U)
+#define RCC_APB1RSTCR1_TIM6RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTCR1_TIM6RSTC                 RCC_APB1RSTCR1_TIM6RSTC_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTCR1_TIM7RSTC_Pos             (5U)
+#define RCC_APB1RSTCR1_TIM7RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTCR1_TIM7RSTC                 RCC_APB1RSTCR1_TIM7RSTC_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTCR1_TIM12RSTC_Pos            (6U)
+#define RCC_APB1RSTCR1_TIM12RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTCR1_TIM12RSTC                RCC_APB1RSTCR1_TIM12RSTC_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTCR1_TIM13RSTC_Pos            (7U)
+#define RCC_APB1RSTCR1_TIM13RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTCR1_TIM13RSTC                RCC_APB1RSTCR1_TIM13RSTC_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTCR1_TIM14RSTC_Pos            (8U)
+#define RCC_APB1RSTCR1_TIM14RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR1_TIM14RSTC                RCC_APB1RSTCR1_TIM14RSTC_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos           (9U)
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTCR1_LPTIM1RSTC               RCC_APB1RSTCR1_LPTIM1RSTC_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTCR1_WWDGRSTC_Pos             (11U)
+#define RCC_APB1RSTCR1_WWDGRSTC_Msk             (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTCR1_WWDGRSTC                 RCC_APB1RSTCR1_WWDGRSTC_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTCR1_TIM10RSTC_Pos            (12U)
+#define RCC_APB1RSTCR1_TIM10RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTCR1_TIM10RSTC                RCC_APB1RSTCR1_TIM10RSTC_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTCR1_TIM11RSTC_Pos            (13U)
+#define RCC_APB1RSTCR1_TIM11RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTCR1_TIM11RSTC                RCC_APB1RSTCR1_TIM11RSTC_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTCR1_SPI2RSTC_Pos             (14U)
+#define RCC_APB1RSTCR1_SPI2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTCR1_SPI2RSTC                 RCC_APB1RSTCR1_SPI2RSTC_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTCR1_SPI3RSTC_Pos             (15U)
+#define RCC_APB1RSTCR1_SPI3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTCR1_SPI3RSTC                 RCC_APB1RSTCR1_SPI3RSTC_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos         (16U)
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk         (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC             RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTCR1_USART2RSTC_Pos           (17U)
+#define RCC_APB1RSTCR1_USART2RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTCR1_USART2RSTC               RCC_APB1RSTCR1_USART2RSTC_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTCR1_USART3RSTC_Pos           (18U)
+#define RCC_APB1RSTCR1_USART3RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTCR1_USART3RSTC               RCC_APB1RSTCR1_USART3RSTC_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTCR1_UART4RSTC_Pos            (19U)
+#define RCC_APB1RSTCR1_UART4RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTCR1_UART4RSTC                RCC_APB1RSTCR1_UART4RSTC_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTCR1_UART5RSTC_Pos            (20U)
+#define RCC_APB1RSTCR1_UART5RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTCR1_UART5RSTC                RCC_APB1RSTCR1_UART5RSTC_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTCR1_I2C1RSTC_Pos             (21U)
+#define RCC_APB1RSTCR1_I2C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTCR1_I2C1RSTC                 RCC_APB1RSTCR1_I2C1RSTC_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTCR1_I2C2RSTC_Pos             (22U)
+#define RCC_APB1RSTCR1_I2C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTCR1_I2C2RSTC                 RCC_APB1RSTCR1_I2C2RSTC_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTCR1_I2C3RSTC_Pos             (23U)
+#define RCC_APB1RSTCR1_I2C3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTCR1_I2C3RSTC                 RCC_APB1RSTCR1_I2C3RSTC_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTCR1_I3C1RSTC_Pos             (24U)
+#define RCC_APB1RSTCR1_I3C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTCR1_I3C1RSTC                 RCC_APB1RSTCR1_I3C1RSTC_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTCR1_I3C2RSTC_Pos             (25U)
+#define RCC_APB1RSTCR1_I3C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTCR1_I3C2RSTC                 RCC_APB1RSTCR1_I3C2RSTC_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTCR1_UART7RSTC_Pos            (30U)
+#define RCC_APB1RSTCR1_UART7RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTCR1_UART7RSTC                RCC_APB1RSTCR1_UART7RSTC_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTCR1_UART8RSTC_Pos            (31U)
+#define RCC_APB1RSTCR1_UART8RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTCR1_UART8RSTC                RCC_APB1RSTCR1_UART8RSTC_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTCR2 register  ****************/
+#define RCC_APB1RSTCR2_MDIOSRSTC_Pos            (5U)
+#define RCC_APB1RSTCR2_MDIOSRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTCR2_MDIOSRSTC                RCC_APB1RSTCR2_MDIOSRSTC_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTCR2_FDCANRSTC_Pos            (8U)
+#define RCC_APB1RSTCR2_FDCANRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR2_FDCANRSTC                RCC_APB1RSTCR2_FDCANRSTC_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTCR2_UCPD1RSTC_Pos            (18U)
+#define RCC_APB1RSTCR2_UCPD1RSTC_Msk            (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTCR2_UCPD1RSTC                RCC_APB1RSTCR2_UCPD1RSTC_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTCR register  *****************/
+#define RCC_APB2RSTCR_TIM1RSTC_Pos              (0U)
+#define RCC_APB2RSTCR_TIM1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTCR_TIM1RSTC                  RCC_APB2RSTCR_TIM1RSTC_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTCR_TIM8RSTC_Pos              (1U)
+#define RCC_APB2RSTCR_TIM8RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTCR_TIM8RSTC                  RCC_APB2RSTCR_TIM8RSTC_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTCR_USART1RSTC_Pos            (4U)
+#define RCC_APB2RSTCR_USART1RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTCR_USART1RSTC                RCC_APB2RSTCR_USART1RSTC_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTCR_USART6RSTC_Pos            (5U)
+#define RCC_APB2RSTCR_USART6RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTCR_USART6RSTC                RCC_APB2RSTCR_USART6RSTC_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTCR_UART9RSTC_Pos             (6U)
+#define RCC_APB2RSTCR_UART9RSTC_Msk             (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTCR_UART9RSTC                 RCC_APB2RSTCR_UART9RSTC_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTCR_USART10RSTC_Pos           (7U)
+#define RCC_APB2RSTCR_USART10RSTC_Msk           (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTCR_USART10RSTC               RCC_APB2RSTCR_USART10RSTC_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTCR_SPI1RSTC_Pos              (12U)
+#define RCC_APB2RSTCR_SPI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTCR_SPI1RSTC                  RCC_APB2RSTCR_SPI1RSTC_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTCR_SPI4RSTC_Pos              (13U)
+#define RCC_APB2RSTCR_SPI4RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTCR_SPI4RSTC                  RCC_APB2RSTCR_SPI4RSTC_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTCR_TIM18RSTC_Pos             (15U)
+#define RCC_APB2RSTCR_TIM18RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTCR_TIM18RSTC                 RCC_APB2RSTCR_TIM18RSTC_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTCR_TIM15RSTC_Pos             (16U)
+#define RCC_APB2RSTCR_TIM15RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTCR_TIM15RSTC                 RCC_APB2RSTCR_TIM15RSTC_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTCR_TIM16RSTC_Pos             (17U)
+#define RCC_APB2RSTCR_TIM16RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTCR_TIM16RSTC                 RCC_APB2RSTCR_TIM16RSTC_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTCR_TIM17RSTC_Pos             (18U)
+#define RCC_APB2RSTCR_TIM17RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTCR_TIM17RSTC                 RCC_APB2RSTCR_TIM17RSTC_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTCR_TIM9RSTC_Pos              (19U)
+#define RCC_APB2RSTCR_TIM9RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTCR_TIM9RSTC                  RCC_APB2RSTCR_TIM9RSTC_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTCR_SPI5RSTC_Pos              (20U)
+#define RCC_APB2RSTCR_SPI5RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTCR_SPI5RSTC                  RCC_APB2RSTCR_SPI5RSTC_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTCR_SAI1RSTC_Pos              (21U)
+#define RCC_APB2RSTCR_SAI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTCR_SAI1RSTC                  RCC_APB2RSTCR_SAI1RSTC_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTCR_SAI2RSTC_Pos              (22U)
+#define RCC_APB2RSTCR_SAI2RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTCR_SAI2RSTC                  RCC_APB2RSTCR_SAI2RSTC_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTCR1 register  ****************/
+#define RCC_APB4RSTCR1_HDPRSTC_Pos              (2U)
+#define RCC_APB4RSTCR1_HDPRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR1_HDPRSTC                  RCC_APB4RSTCR1_HDPRSTC_Msk           /*!< HDP reset */
+#define RCC_APB4RSTCR1_LPUART1RSTC_Pos          (3U)
+#define RCC_APB4RSTCR1_LPUART1RSTC_Msk          (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTCR1_LPUART1RSTC              RCC_APB4RSTCR1_LPUART1RSTC_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTCR1_SPI6RSTC_Pos             (5U)
+#define RCC_APB4RSTCR1_SPI6RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTCR1_SPI6RSTC                 RCC_APB4RSTCR1_SPI6RSTC_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTCR1_I2C4RSTC_Pos             (7U)
+#define RCC_APB4RSTCR1_I2C4RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTCR1_I2C4RSTC                 RCC_APB4RSTCR1_I2C4RSTC_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos           (9U)
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTCR1_LPTIM2RSTC               RCC_APB4RSTCR1_LPTIM2RSTC_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos           (10U)
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTCR1_LPTIM3RSTC               RCC_APB4RSTCR1_LPTIM3RSTC_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos           (11U)
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTCR1_LPTIM4RSTC               RCC_APB4RSTCR1_LPTIM4RSTC_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos           (12U)
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTCR1_LPTIM5RSTC               RCC_APB4RSTCR1_LPTIM5RSTC_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos          (15U)
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk          (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTCR1_VREFBUFRSTC              RCC_APB4RSTCR1_VREFBUFRSTC_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTCR1_RTCRSTC_Pos              (16U)
+#define RCC_APB4RSTCR1_RTCRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTCR1_RTCRSTC                  RCC_APB4RSTCR1_RTCRSTC_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTCR2 register  ****************/
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos           (0U)
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk           (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTCR2_SYSCFGRSTC               RCC_APB4RSTCR2_SYSCFGRSTC_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTCR2_DTSRSTC_Pos              (2U)
+#define RCC_APB4RSTCR2_DTSRSTC_Msk              (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR2_DTSRSTC                  RCC_APB4RSTCR2_DTSRSTC_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTCR register  *****************/
+#define RCC_APB5RSTCR_LTDCRSTC_Pos              (1U)
+#define RCC_APB5RSTCR_LTDCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTCR_LTDCRSTC                  RCC_APB5RSTCR_LTDCRSTC_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTCR_DCMIPPRSTC_Pos            (2U)
+#define RCC_APB5RSTCR_DCMIPPRSTC_Msk            (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTCR_DCMIPPRSTC                RCC_APB5RSTCR_DCMIPPRSTC_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTCR_GFXTIMRSTC_Pos            (4U)
+#define RCC_APB5RSTCR_GFXTIMRSTC_Msk            (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTCR_GFXTIMRSTC                RCC_APB5RSTCR_GFXTIMRSTC_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTCR_VENCRSTC_Pos              (5U)
+#define RCC_APB5RSTCR_VENCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTCR_VENCRSTC                  RCC_APB5RSTCR_VENCRSTC_Msk           /*!< VENC reset */
+#define RCC_APB5RSTCR_CSIRSTC_Pos               (6U)
+#define RCC_APB5RSTCR_CSIRSTC_Msk               (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTCR_CSIRSTC                   RCC_APB5RSTCR_CSIRSTC_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENCR register  ******************/
+#define RCC_DIVENCR_IC1ENC_Pos                  (0U)
+#define RCC_DIVENCR_IC1ENC_Msk                  (0x1UL << RCC_DIVENCR_IC1ENC_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENCR_IC1ENC                      RCC_DIVENCR_IC1ENC_Msk               /*!< IC1 enable */
+#define RCC_DIVENCR_IC2ENC_Pos                  (1U)
+#define RCC_DIVENCR_IC2ENC_Msk                  (0x1UL << RCC_DIVENCR_IC2ENC_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENCR_IC2ENC                      RCC_DIVENCR_IC2ENC_Msk               /*!< IC2 enable */
+#define RCC_DIVENCR_IC3ENC_Pos                  (2U)
+#define RCC_DIVENCR_IC3ENC_Msk                  (0x1UL << RCC_DIVENCR_IC3ENC_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENCR_IC3ENC                      RCC_DIVENCR_IC3ENC_Msk               /*!< IC3 enable */
+#define RCC_DIVENCR_IC4ENC_Pos                  (3U)
+#define RCC_DIVENCR_IC4ENC_Msk                  (0x1UL << RCC_DIVENCR_IC4ENC_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENCR_IC4ENC                      RCC_DIVENCR_IC4ENC_Msk               /*!< IC4 enable */
+#define RCC_DIVENCR_IC5ENC_Pos                  (4U)
+#define RCC_DIVENCR_IC5ENC_Msk                  (0x1UL << RCC_DIVENCR_IC5ENC_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENCR_IC5ENC                      RCC_DIVENCR_IC5ENC_Msk               /*!< IC5 enable */
+#define RCC_DIVENCR_IC6ENC_Pos                  (5U)
+#define RCC_DIVENCR_IC6ENC_Msk                  (0x1UL << RCC_DIVENCR_IC6ENC_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENCR_IC6ENC                      RCC_DIVENCR_IC6ENC_Msk               /*!< IC6 enable */
+#define RCC_DIVENCR_IC7ENC_Pos                  (6U)
+#define RCC_DIVENCR_IC7ENC_Msk                  (0x1UL << RCC_DIVENCR_IC7ENC_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENCR_IC7ENC                      RCC_DIVENCR_IC7ENC_Msk               /*!< IC7 enable */
+#define RCC_DIVENCR_IC8ENC_Pos                  (7U)
+#define RCC_DIVENCR_IC8ENC_Msk                  (0x1UL << RCC_DIVENCR_IC8ENC_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENCR_IC8ENC                      RCC_DIVENCR_IC8ENC_Msk               /*!< IC8 enable */
+#define RCC_DIVENCR_IC9ENC_Pos                  (8U)
+#define RCC_DIVENCR_IC9ENC_Msk                  (0x1UL << RCC_DIVENCR_IC9ENC_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENCR_IC9ENC                      RCC_DIVENCR_IC9ENC_Msk               /*!< IC9 enable */
+#define RCC_DIVENCR_IC10ENC_Pos                 (9U)
+#define RCC_DIVENCR_IC10ENC_Msk                 (0x1UL << RCC_DIVENCR_IC10ENC_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENCR_IC10ENC                     RCC_DIVENCR_IC10ENC_Msk              /*!< IC10 enable */
+#define RCC_DIVENCR_IC11ENC_Pos                 (10U)
+#define RCC_DIVENCR_IC11ENC_Msk                 (0x1UL << RCC_DIVENCR_IC11ENC_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENCR_IC11ENC                     RCC_DIVENCR_IC11ENC_Msk              /*!< IC11 enable */
+#define RCC_DIVENCR_IC12ENC_Pos                 (11U)
+#define RCC_DIVENCR_IC12ENC_Msk                 (0x1UL << RCC_DIVENCR_IC12ENC_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENCR_IC12ENC                     RCC_DIVENCR_IC12ENC_Msk              /*!< IC12 enable */
+#define RCC_DIVENCR_IC13ENC_Pos                 (12U)
+#define RCC_DIVENCR_IC13ENC_Msk                 (0x1UL << RCC_DIVENCR_IC13ENC_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENCR_IC13ENC                     RCC_DIVENCR_IC13ENC_Msk              /*!< IC13 enable */
+#define RCC_DIVENCR_IC14ENC_Pos                 (13U)
+#define RCC_DIVENCR_IC14ENC_Msk                 (0x1UL << RCC_DIVENCR_IC14ENC_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENCR_IC14ENC                     RCC_DIVENCR_IC14ENC_Msk              /*!< IC14 enable */
+#define RCC_DIVENCR_IC15ENC_Pos                 (14U)
+#define RCC_DIVENCR_IC15ENC_Msk                 (0x1UL << RCC_DIVENCR_IC15ENC_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENCR_IC15ENC                     RCC_DIVENCR_IC15ENC_Msk              /*!< IC15 enable */
+#define RCC_DIVENCR_IC16ENC_Pos                 (15U)
+#define RCC_DIVENCR_IC16ENC_Msk                 (0x1UL << RCC_DIVENCR_IC16ENC_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENCR_IC16ENC                     RCC_DIVENCR_IC16ENC_Msk              /*!< IC16 enable */
+#define RCC_DIVENCR_IC17ENC_Pos                 (16U)
+#define RCC_DIVENCR_IC17ENC_Msk                 (0x1UL << RCC_DIVENCR_IC17ENC_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENCR_IC17ENC                     RCC_DIVENCR_IC17ENC_Msk              /*!< IC17 enable */
+#define RCC_DIVENCR_IC18ENC_Pos                 (17U)
+#define RCC_DIVENCR_IC18ENC_Msk                 (0x1UL << RCC_DIVENCR_IC18ENC_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENCR_IC18ENC                     RCC_DIVENCR_IC18ENC_Msk              /*!< IC18 enable */
+#define RCC_DIVENCR_IC19ENC_Pos                 (18U)
+#define RCC_DIVENCR_IC19ENC_Msk                 (0x1UL << RCC_DIVENCR_IC19ENC_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENCR_IC19ENC                     RCC_DIVENCR_IC19ENC_Msk              /*!< IC19 enable */
+#define RCC_DIVENCR_IC20ENC_Pos                 (19U)
+#define RCC_DIVENCR_IC20ENC_Msk                 (0x1UL << RCC_DIVENCR_IC20ENC_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENCR_IC20ENC                     RCC_DIVENCR_IC20ENC_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENCR register  ******************/
+#define RCC_BUSENCR_ACLKNENC_Pos                (0U)
+#define RCC_BUSENCR_ACLKNENC_Msk                (0x1UL << RCC_BUSENCR_ACLKNENC_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENCR_ACLKNENC                    RCC_BUSENCR_ACLKNENC_Msk             /*!< ACLKN enable */
+#define RCC_BUSENCR_ACLKNCENC_Pos               (1U)
+#define RCC_BUSENCR_ACLKNCENC_Msk               (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENCR_ACLKNCENC                   RCC_BUSENCR_ACLKNCENC_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENCR_AHBMENC_Pos                 (2U)
+#define RCC_BUSENCR_AHBMENC_Msk                 (0x1UL << RCC_BUSENCR_AHBMENC_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENCR_AHBMENC                     RCC_BUSENCR_AHBMENC_Msk              /*!< AHBM enable */
+#define RCC_BUSENCR_AHB1ENC_Pos                 (3U)
+#define RCC_BUSENCR_AHB1ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB1ENC_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENCR_AHB1ENC                     RCC_BUSENCR_AHB1ENC_Msk              /*!< AHB1 enable */
+#define RCC_BUSENCR_AHB2ENC_Pos                 (4U)
+#define RCC_BUSENCR_AHB2ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB2ENC_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENCR_AHB2ENC                     RCC_BUSENCR_AHB2ENC_Msk              /*!< AHB2 enable */
+#define RCC_BUSENCR_AHB3ENC_Pos                 (5U)
+#define RCC_BUSENCR_AHB3ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB3ENC_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENCR_AHB3ENC                     RCC_BUSENCR_AHB3ENC_Msk              /*!< AHB3 enable */
+#define RCC_BUSENCR_AHB4ENC_Pos                 (6U)
+#define RCC_BUSENCR_AHB4ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB4ENC_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENCR_AHB4ENC                     RCC_BUSENCR_AHB4ENC_Msk              /*!< AHB4 enable */
+#define RCC_BUSENCR_AHB5ENC_Pos                 (7U)
+#define RCC_BUSENCR_AHB5ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB5ENC_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENCR_AHB5ENC                     RCC_BUSENCR_AHB5ENC_Msk              /*!< AHB5 enable */
+#define RCC_BUSENCR_APB1ENC_Pos                 (8U)
+#define RCC_BUSENCR_APB1ENC_Msk                 (0x1UL << RCC_BUSENCR_APB1ENC_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENCR_APB1ENC                     RCC_BUSENCR_APB1ENC_Msk              /*!< APB1 enable */
+#define RCC_BUSENCR_APB2ENC_Pos                 (9U)
+#define RCC_BUSENCR_APB2ENC_Msk                 (0x1UL << RCC_BUSENCR_APB2ENC_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENCR_APB2ENC                     RCC_BUSENCR_APB2ENC_Msk              /*!< APB2 enable */
+#define RCC_BUSENCR_APB3ENC_Pos                 (10U)
+#define RCC_BUSENCR_APB3ENC_Msk                 (0x1UL << RCC_BUSENCR_APB3ENC_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENCR_APB3ENC                     RCC_BUSENCR_APB3ENC_Msk              /*!< APB3 enable */
+#define RCC_BUSENCR_APB4ENC_Pos                 (11U)
+#define RCC_BUSENCR_APB4ENC_Msk                 (0x1UL << RCC_BUSENCR_APB4ENC_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENCR_APB4ENC                     RCC_BUSENCR_APB4ENC_Msk              /*!< APB4 enable */
+#define RCC_BUSENCR_APB5ENC_Pos                 (12U)
+#define RCC_BUSENCR_APB5ENC_Msk                 (0x1UL << RCC_BUSENCR_APB5ENC_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENCR_APB5ENC                     RCC_BUSENCR_APB5ENC_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENCR register  *****************/
+#define RCC_MISCENCR_DBGENC_Pos                 (0U)
+#define RCC_MISCENCR_DBGENC_Msk                 (0x1UL << RCC_MISCENCR_DBGENC_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENCR_DBGENC                     RCC_MISCENCR_DBGENC_Msk              /*!< DBG enable */
+#define RCC_MISCENCR_MCO1ENC_Pos                (1U)
+#define RCC_MISCENCR_MCO1ENC_Msk                (0x1UL << RCC_MISCENCR_MCO1ENC_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENCR_MCO1ENC                    RCC_MISCENCR_MCO1ENC_Msk             /*!< MCO1 enable */
+#define RCC_MISCENCR_MCO2ENC_Pos                (2U)
+#define RCC_MISCENCR_MCO2ENC_Msk                (0x1UL << RCC_MISCENCR_MCO2ENC_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENCR_MCO2ENC                    RCC_MISCENCR_MCO2ENC_Msk             /*!< MCO2 enable */
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos         (3U)
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk         (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENCR_XSPIPHYCOMPENC             RCC_MISCENCR_XSPIPHYCOMPENC_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENCR_PERENC_Pos                 (6U)
+#define RCC_MISCENCR_PERENC_Msk                 (0x1UL << RCC_MISCENCR_PERENC_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENCR_PERENC                     RCC_MISCENCR_PERENC_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENCR register  ******************/
+#define RCC_MEMENCR_AXISRAM3ENC_Pos             (0U)
+#define RCC_MEMENCR_AXISRAM3ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */
+#define RCC_MEMENCR_AXISRAM3ENC                 RCC_MEMENCR_AXISRAM3ENC_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENCR_AXISRAM4ENC_Pos             (1U)
+#define RCC_MEMENCR_AXISRAM4ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */
+#define RCC_MEMENCR_AXISRAM4ENC                 RCC_MEMENCR_AXISRAM4ENC_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENCR_AXISRAM5ENC_Pos             (2U)
+#define RCC_MEMENCR_AXISRAM5ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */
+#define RCC_MEMENCR_AXISRAM5ENC                 RCC_MEMENCR_AXISRAM5ENC_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENCR_AXISRAM6ENC_Pos             (3U)
+#define RCC_MEMENCR_AXISRAM6ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */
+#define RCC_MEMENCR_AXISRAM6ENC                 RCC_MEMENCR_AXISRAM6ENC_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENCR_AHBSRAM1ENC_Pos             (4U)
+#define RCC_MEMENCR_AHBSRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */
+#define RCC_MEMENCR_AHBSRAM1ENC                 RCC_MEMENCR_AHBSRAM1ENC_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENCR_AHBSRAM2ENC_Pos             (5U)
+#define RCC_MEMENCR_AHBSRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */
+#define RCC_MEMENCR_AHBSRAM2ENC                 RCC_MEMENCR_AHBSRAM2ENC_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENCR_BKPSRAMENC_Pos              (6U)
+#define RCC_MEMENCR_BKPSRAMENC_Msk              (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */
+#define RCC_MEMENCR_BKPSRAMENC                  RCC_MEMENCR_BKPSRAMENC_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENCR_AXISRAM1ENC_Pos             (7U)
+#define RCC_MEMENCR_AXISRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */
+#define RCC_MEMENCR_AXISRAM1ENC                 RCC_MEMENCR_AXISRAM1ENC_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENCR_AXISRAM2ENC_Pos             (8U)
+#define RCC_MEMENCR_AXISRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */
+#define RCC_MEMENCR_AXISRAM2ENC                 RCC_MEMENCR_AXISRAM2ENC_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENCR_FLEXRAMENC_Pos              (9U)
+#define RCC_MEMENCR_FLEXRAMENC_Msk              (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */
+#define RCC_MEMENCR_FLEXRAMENC                  RCC_MEMENCR_FLEXRAMENC_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENCR_VENCRAMENC_Pos              (11U)
+#define RCC_MEMENCR_VENCRAMENC_Msk              (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */
+#define RCC_MEMENCR_VENCRAMENC                  RCC_MEMENCR_VENCRAMENC_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENCR_BOOTROMENC_Pos              (12U)
+#define RCC_MEMENCR_BOOTROMENC_Msk              (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */
+#define RCC_MEMENCR_BOOTROMENC                  RCC_MEMENCR_BOOTROMENC_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENCR register  *****************/
+#define RCC_AHB1ENCR_GPDMA1ENC_Pos              (4U)
+#define RCC_AHB1ENCR_GPDMA1ENC_Msk              (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENCR_GPDMA1ENC                  RCC_AHB1ENCR_GPDMA1ENC_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENCR_ADC12ENC_Pos               (5U)
+#define RCC_AHB1ENCR_ADC12ENC_Msk               (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENCR_ADC12ENC                   RCC_AHB1ENCR_ADC12ENC_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENCR register  *****************/
+#define RCC_AHB2ENCR_RAMCFGENC_Pos              (12U)
+#define RCC_AHB2ENCR_RAMCFGENC_Msk              (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENCR_RAMCFGENC                  RCC_AHB2ENCR_RAMCFGENC_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENCR_MDF1ENC_Pos                (16U)
+#define RCC_AHB2ENCR_MDF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENCR_MDF1ENC                    RCC_AHB2ENCR_MDF1ENC_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENCR_ADF1ENC_Pos                (17U)
+#define RCC_AHB2ENCR_ADF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENCR_ADF1ENC                    RCC_AHB2ENCR_ADF1ENC_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENCR register  *****************/
+#define RCC_AHB3ENCR_RNGENC_Pos                 (0U)
+#define RCC_AHB3ENCR_RNGENC_Msk                 (0x1UL << RCC_AHB3ENCR_RNGENC_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENCR_RNGENC                     RCC_AHB3ENCR_RNGENC_Msk              /*!< RNG enable */
+#define RCC_AHB3ENCR_HASHENC_Pos                (1U)
+#define RCC_AHB3ENCR_HASHENC_Msk                (0x1UL << RCC_AHB3ENCR_HASHENC_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENCR_HASHENC                    RCC_AHB3ENCR_HASHENC_Msk             /*!< HASH enable */
+#define RCC_AHB3ENCR_CRYPENC_Pos                (2U)
+#define RCC_AHB3ENCR_CRYPENC_Msk                (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos)   /*!< 0x00000004 */
+#define RCC_AHB3ENCR_CRYPENC                    RCC_AHB3ENCR_CRYPENC_Msk             /*!< CRYP enable */
+#define RCC_AHB3ENCR_SAESENC_Pos                (4U)
+#define RCC_AHB3ENCR_SAESENC_Msk                (0x1UL << RCC_AHB3ENCR_SAESENC_Pos)   /*!< 0x00000010 */
+#define RCC_AHB3ENCR_SAESENC                    RCC_AHB3ENCR_SAESENC_Msk             /*!< SAES enable */
+#define RCC_AHB3ENCR_PKAENC_Pos                 (8U)
+#define RCC_AHB3ENCR_PKAENC_Msk                 (0x1UL << RCC_AHB3ENCR_PKAENC_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENCR_PKAENC                     RCC_AHB3ENCR_PKAENC_Msk              /*!< PKA enable */
+#define RCC_AHB3ENCR_RIFSCENC_Pos               (9U)
+#define RCC_AHB3ENCR_RIFSCENC_Msk               (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENCR_RIFSCENC                   RCC_AHB3ENCR_RIFSCENC_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENCR_IACENC_Pos                 (10U)
+#define RCC_AHB3ENCR_IACENC_Msk                 (0x1UL << RCC_AHB3ENCR_IACENC_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENCR_IACENC                     RCC_AHB3ENCR_IACENC_Msk              /*!< IAC enable */
+#define RCC_AHB3ENCR_RISAFENC_Pos               (14U)
+#define RCC_AHB3ENCR_RISAFENC_Msk               (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENCR_RISAFENC                   RCC_AHB3ENCR_RISAFENC_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENCR register  *****************/
+#define RCC_AHB4ENCR_GPIOAENC_Pos               (0U)
+#define RCC_AHB4ENCR_GPIOAENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENCR_GPIOAENC                   RCC_AHB4ENCR_GPIOAENC_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENCR_GPIOBENC_Pos               (1U)
+#define RCC_AHB4ENCR_GPIOBENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENCR_GPIOBENC                   RCC_AHB4ENCR_GPIOBENC_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENCR_GPIOCENC_Pos               (2U)
+#define RCC_AHB4ENCR_GPIOCENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENCR_GPIOCENC                   RCC_AHB4ENCR_GPIOCENC_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENCR_GPIODENC_Pos               (3U)
+#define RCC_AHB4ENCR_GPIODENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENCR_GPIODENC                   RCC_AHB4ENCR_GPIODENC_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENCR_GPIOEENC_Pos               (4U)
+#define RCC_AHB4ENCR_GPIOEENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENCR_GPIOEENC                   RCC_AHB4ENCR_GPIOEENC_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENCR_GPIOFENC_Pos               (5U)
+#define RCC_AHB4ENCR_GPIOFENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENCR_GPIOFENC                   RCC_AHB4ENCR_GPIOFENC_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENCR_GPIOGENC_Pos               (6U)
+#define RCC_AHB4ENCR_GPIOGENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENCR_GPIOGENC                   RCC_AHB4ENCR_GPIOGENC_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENCR_GPIOHENC_Pos               (7U)
+#define RCC_AHB4ENCR_GPIOHENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENCR_GPIOHENC                   RCC_AHB4ENCR_GPIOHENC_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENCR_GPIONENC_Pos               (13U)
+#define RCC_AHB4ENCR_GPIONENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENCR_GPIONENC                   RCC_AHB4ENCR_GPIONENC_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENCR_GPIOOENC_Pos               (14U)
+#define RCC_AHB4ENCR_GPIOOENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENCR_GPIOOENC                   RCC_AHB4ENCR_GPIOOENC_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENCR_GPIOPENC_Pos               (15U)
+#define RCC_AHB4ENCR_GPIOPENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENCR_GPIOPENC                   RCC_AHB4ENCR_GPIOPENC_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENCR_GPIOQENC_Pos               (16U)
+#define RCC_AHB4ENCR_GPIOQENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENCR_GPIOQENC                   RCC_AHB4ENCR_GPIOQENC_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENCR_PWRENC_Pos                 (18U)
+#define RCC_AHB4ENCR_PWRENC_Msk                 (0x1UL << RCC_AHB4ENCR_PWRENC_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENCR_PWRENC                     RCC_AHB4ENCR_PWRENC_Msk              /*!< PWR enable */
+#define RCC_AHB4ENCR_CRCENC_Pos                 (19U)
+#define RCC_AHB4ENCR_CRCENC_Msk                 (0x1UL << RCC_AHB4ENCR_CRCENC_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENCR_CRCENC                     RCC_AHB4ENCR_CRCENC_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENCR register  *****************/
+#define RCC_AHB5ENCR_HPDMA1ENC_Pos              (0U)
+#define RCC_AHB5ENCR_HPDMA1ENC_Msk              (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENCR_HPDMA1ENC                  RCC_AHB5ENCR_HPDMA1ENC_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENCR_DMA2DENC_Pos               (1U)
+#define RCC_AHB5ENCR_DMA2DENC_Msk               (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENCR_DMA2DENC                   RCC_AHB5ENCR_DMA2DENC_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENCR_JPEGENC_Pos                (3U)
+#define RCC_AHB5ENCR_JPEGENC_Msk                (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENCR_JPEGENC                    RCC_AHB5ENCR_JPEGENC_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENCR_FMCENC_Pos                 (4U)
+#define RCC_AHB5ENCR_FMCENC_Msk                 (0x1UL << RCC_AHB5ENCR_FMCENC_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENCR_FMCENC                     RCC_AHB5ENCR_FMCENC_Msk              /*!< FMC enable */
+#define RCC_AHB5ENCR_XSPI1ENC_Pos               (5U)
+#define RCC_AHB5ENCR_XSPI1ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENCR_XSPI1ENC                   RCC_AHB5ENCR_XSPI1ENC_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENCR_PSSIENC_Pos                (6U)
+#define RCC_AHB5ENCR_PSSIENC_Msk                (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENCR_PSSIENC                    RCC_AHB5ENCR_PSSIENC_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENCR_SDMMC2ENC_Pos              (7U)
+#define RCC_AHB5ENCR_SDMMC2ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENCR_SDMMC2ENC                  RCC_AHB5ENCR_SDMMC2ENC_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENCR_SDMMC1ENC_Pos              (8U)
+#define RCC_AHB5ENCR_SDMMC1ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENCR_SDMMC1ENC                  RCC_AHB5ENCR_SDMMC1ENC_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENCR_XSPI2ENC_Pos               (12U)
+#define RCC_AHB5ENCR_XSPI2ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENCR_XSPI2ENC                   RCC_AHB5ENCR_XSPI2ENC_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENCR_XSPIMENC_Pos               (13U)
+#define RCC_AHB5ENCR_XSPIMENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENCR_XSPIMENC                   RCC_AHB5ENCR_XSPIMENC_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENCR_MCE1ENC_Pos                (14U)
+#define RCC_AHB5ENCR_MCE1ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos)   /*!< 0x00004000 */
+#define RCC_AHB5ENCR_MCE1ENC                    RCC_AHB5ENCR_MCE1ENC_Msk             /*!< MCE1 enable */
+#define RCC_AHB5ENCR_MCE2ENC_Pos                (15U)
+#define RCC_AHB5ENCR_MCE2ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos)   /*!< 0x00008000 */
+#define RCC_AHB5ENCR_MCE2ENC                    RCC_AHB5ENCR_MCE2ENC_Msk             /*!< MCE2 enable */
+#define RCC_AHB5ENCR_MCE3ENC_Pos                (16U)
+#define RCC_AHB5ENCR_MCE3ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos)   /*!< 0x00010000 */
+#define RCC_AHB5ENCR_MCE3ENC                    RCC_AHB5ENCR_MCE3ENC_Msk             /*!< MCE3 enable */
+#define RCC_AHB5ENCR_XSPI3ENC_Pos               (17U)
+#define RCC_AHB5ENCR_XSPI3ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENCR_XSPI3ENC                   RCC_AHB5ENCR_XSPI3ENC_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENCR_MCE4ENC_Pos                (18U)
+#define RCC_AHB5ENCR_MCE4ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos)   /*!< 0x00040000 */
+#define RCC_AHB5ENCR_MCE4ENC                    RCC_AHB5ENCR_MCE4ENC_Msk             /*!< MCE4 enable */
+#define RCC_AHB5ENCR_GFXMMUENC_Pos              (19U)
+#define RCC_AHB5ENCR_GFXMMUENC_Msk              (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENCR_GFXMMUENC                  RCC_AHB5ENCR_GFXMMUENC_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENCR_GPU2DENC_Pos               (20U)
+#define RCC_AHB5ENCR_GPU2DENC_Msk               (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENCR_GPU2DENC                   RCC_AHB5ENCR_GPU2DENC_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENCR_ETH1MACENC_Pos             (22U)
+#define RCC_AHB5ENCR_ETH1MACENC_Msk             (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENCR_ETH1MACENC                 RCC_AHB5ENCR_ETH1MACENC_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENCR_ETH1TXENC_Pos              (23U)
+#define RCC_AHB5ENCR_ETH1TXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENCR_ETH1TXENC                  RCC_AHB5ENCR_ETH1TXENC_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENCR_ETH1RXENC_Pos              (24U)
+#define RCC_AHB5ENCR_ETH1RXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENCR_ETH1RXENC                  RCC_AHB5ENCR_ETH1RXENC_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENCR_ETH1ENC_Pos                (25U)
+#define RCC_AHB5ENCR_ETH1ENC_Msk                (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENCR_ETH1ENC                    RCC_AHB5ENCR_ETH1ENC_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENCR_OTG1ENC_Pos                (26U)
+#define RCC_AHB5ENCR_OTG1ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENCR_OTG1ENC                    RCC_AHB5ENCR_OTG1ENC_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENCR_OTGPHY1ENC_Pos             (27U)
+#define RCC_AHB5ENCR_OTGPHY1ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENCR_OTGPHY1ENC                 RCC_AHB5ENCR_OTGPHY1ENC_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENCR_OTGPHY2ENC_Pos             (28U)
+#define RCC_AHB5ENCR_OTGPHY2ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENCR_OTGPHY2ENC                 RCC_AHB5ENCR_OTGPHY2ENC_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENCR_OTG2ENC_Pos                (29U)
+#define RCC_AHB5ENCR_OTG2ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENCR_OTG2ENC                    RCC_AHB5ENCR_OTG2ENC_Msk             /*!< OTG2 enable */
+
+/****************  Bit definition for RCC_APB1ENCR1 register  *****************/
+#define RCC_APB1ENCR1_TIM2ENC_Pos               (0U)
+#define RCC_APB1ENCR1_TIM2ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENCR1_TIM2ENC                   RCC_APB1ENCR1_TIM2ENC_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENCR1_TIM3ENC_Pos               (1U)
+#define RCC_APB1ENCR1_TIM3ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENCR1_TIM3ENC                   RCC_APB1ENCR1_TIM3ENC_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENCR1_TIM4ENC_Pos               (2U)
+#define RCC_APB1ENCR1_TIM4ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENCR1_TIM4ENC                   RCC_APB1ENCR1_TIM4ENC_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENCR1_TIM5ENC_Pos               (3U)
+#define RCC_APB1ENCR1_TIM5ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENCR1_TIM5ENC                   RCC_APB1ENCR1_TIM5ENC_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENCR1_TIM6ENC_Pos               (4U)
+#define RCC_APB1ENCR1_TIM6ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENCR1_TIM6ENC                   RCC_APB1ENCR1_TIM6ENC_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENCR1_TIM7ENC_Pos               (5U)
+#define RCC_APB1ENCR1_TIM7ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENCR1_TIM7ENC                   RCC_APB1ENCR1_TIM7ENC_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENCR1_TIM12ENC_Pos              (6U)
+#define RCC_APB1ENCR1_TIM12ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENCR1_TIM12ENC                  RCC_APB1ENCR1_TIM12ENC_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENCR1_TIM13ENC_Pos              (7U)
+#define RCC_APB1ENCR1_TIM13ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENCR1_TIM13ENC                  RCC_APB1ENCR1_TIM13ENC_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENCR1_TIM14ENC_Pos              (8U)
+#define RCC_APB1ENCR1_TIM14ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR1_TIM14ENC                  RCC_APB1ENCR1_TIM14ENC_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENCR1_LPTIM1ENC_Pos             (9U)
+#define RCC_APB1ENCR1_LPTIM1ENC_Msk             (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENCR1_LPTIM1ENC                 RCC_APB1ENCR1_LPTIM1ENC_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENCR1_TIM10ENC_Pos              (12U)
+#define RCC_APB1ENCR1_TIM10ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENCR1_TIM10ENC                  RCC_APB1ENCR1_TIM10ENC_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENCR1_TIM11ENC_Pos              (13U)
+#define RCC_APB1ENCR1_TIM11ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENCR1_TIM11ENC                  RCC_APB1ENCR1_TIM11ENC_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENCR1_SPI2ENC_Pos               (14U)
+#define RCC_APB1ENCR1_SPI2ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENCR1_SPI2ENC                   RCC_APB1ENCR1_SPI2ENC_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENCR1_SPI3ENC_Pos               (15U)
+#define RCC_APB1ENCR1_SPI3ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENCR1_SPI3ENC                   RCC_APB1ENCR1_SPI3ENC_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos           (16U)
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk           (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENCR1_SPDIFRX1ENC               RCC_APB1ENCR1_SPDIFRX1ENC_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENCR1_USART2ENC_Pos             (17U)
+#define RCC_APB1ENCR1_USART2ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENCR1_USART2ENC                 RCC_APB1ENCR1_USART2ENC_Msk          /*!< USART2 enable */
+#define RCC_APB1ENCR1_USART3ENC_Pos             (18U)
+#define RCC_APB1ENCR1_USART3ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENCR1_USART3ENC                 RCC_APB1ENCR1_USART3ENC_Msk          /*!< USART3 enable */
+#define RCC_APB1ENCR1_UART4ENC_Pos              (19U)
+#define RCC_APB1ENCR1_UART4ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENCR1_UART4ENC                  RCC_APB1ENCR1_UART4ENC_Msk           /*!< UART4 enable */
+#define RCC_APB1ENCR1_UART5ENC_Pos              (20U)
+#define RCC_APB1ENCR1_UART5ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENCR1_UART5ENC                  RCC_APB1ENCR1_UART5ENC_Msk           /*!< UART5 enable */
+#define RCC_APB1ENCR1_I2C1ENC_Pos               (21U)
+#define RCC_APB1ENCR1_I2C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENCR1_I2C1ENC                   RCC_APB1ENCR1_I2C1ENC_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENCR1_I2C2ENC_Pos               (22U)
+#define RCC_APB1ENCR1_I2C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENCR1_I2C2ENC                   RCC_APB1ENCR1_I2C2ENC_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENCR1_I2C3ENC_Pos               (23U)
+#define RCC_APB1ENCR1_I2C3ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENCR1_I2C3ENC                   RCC_APB1ENCR1_I2C3ENC_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENCR1_I3C1ENC_Pos               (24U)
+#define RCC_APB1ENCR1_I3C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENCR1_I3C1ENC                   RCC_APB1ENCR1_I3C1ENC_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENCR1_I3C2ENC_Pos               (25U)
+#define RCC_APB1ENCR1_I3C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENCR1_I3C2ENC                   RCC_APB1ENCR1_I3C2ENC_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENCR1_UART7ENC_Pos              (30U)
+#define RCC_APB1ENCR1_UART7ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENCR1_UART7ENC                  RCC_APB1ENCR1_UART7ENC_Msk           /*!< UART7 enable */
+#define RCC_APB1ENCR1_UART8ENC_Pos              (31U)
+#define RCC_APB1ENCR1_UART8ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENCR1_UART8ENC                  RCC_APB1ENCR1_UART8ENC_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENCR2 register  *****************/
+#define RCC_APB1ENCR2_MDIOSENC_Pos              (5U)
+#define RCC_APB1ENCR2_MDIOSENC_Msk              (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENCR2_MDIOSENC                  RCC_APB1ENCR2_MDIOSENC_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENCR2_FDCANENC_Pos              (8U)
+#define RCC_APB1ENCR2_FDCANENC_Msk              (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR2_FDCANENC                  RCC_APB1ENCR2_FDCANENC_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENCR2_UCPD1ENC_Pos              (18U)
+#define RCC_APB1ENCR2_UCPD1ENC_Msk              (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENCR2_UCPD1ENC                  RCC_APB1ENCR2_UCPD1ENC_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENCR register  *****************/
+#define RCC_APB2ENCR_TIM1ENC_Pos                (0U)
+#define RCC_APB2ENCR_TIM1ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENCR_TIM1ENC                    RCC_APB2ENCR_TIM1ENC_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENCR_TIM8ENC_Pos                (1U)
+#define RCC_APB2ENCR_TIM8ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENCR_TIM8ENC                    RCC_APB2ENCR_TIM8ENC_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENCR_USART1ENC_Pos              (4U)
+#define RCC_APB2ENCR_USART1ENC_Msk              (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENCR_USART1ENC                  RCC_APB2ENCR_USART1ENC_Msk           /*!< USART1 enable */
+#define RCC_APB2ENCR_USART6ENC_Pos              (5U)
+#define RCC_APB2ENCR_USART6ENC_Msk              (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENCR_USART6ENC                  RCC_APB2ENCR_USART6ENC_Msk           /*!< USART6 enable */
+#define RCC_APB2ENCR_UART9ENC_Pos               (6U)
+#define RCC_APB2ENCR_UART9ENC_Msk               (0x1UL << RCC_APB2ENCR_UART9ENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENCR_UART9ENC                   RCC_APB2ENCR_UART9ENC_Msk            /*!< UART9 enable */
+#define RCC_APB2ENCR_USART10ENC_Pos             (7U)
+#define RCC_APB2ENCR_USART10ENC_Msk             (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENCR_USART10ENC                 RCC_APB2ENCR_USART10ENC_Msk          /*!< USART10 enable */
+#define RCC_APB2ENCR_SPI1ENC_Pos                (12U)
+#define RCC_APB2ENCR_SPI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENCR_SPI1ENC                    RCC_APB2ENCR_SPI1ENC_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENCR_SPI4ENC_Pos                (13U)
+#define RCC_APB2ENCR_SPI4ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENCR_SPI4ENC                    RCC_APB2ENCR_SPI4ENC_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENCR_TIM18ENC_Pos               (15U)
+#define RCC_APB2ENCR_TIM18ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENCR_TIM18ENC                   RCC_APB2ENCR_TIM18ENC_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENCR_TIM15ENC_Pos               (16U)
+#define RCC_APB2ENCR_TIM15ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENCR_TIM15ENC                   RCC_APB2ENCR_TIM15ENC_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENCR_TIM16ENC_Pos               (17U)
+#define RCC_APB2ENCR_TIM16ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENCR_TIM16ENC                   RCC_APB2ENCR_TIM16ENC_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENCR_TIM17ENC_Pos               (18U)
+#define RCC_APB2ENCR_TIM17ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENCR_TIM17ENC                   RCC_APB2ENCR_TIM17ENC_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENCR_TIM9ENC_Pos                (19U)
+#define RCC_APB2ENCR_TIM9ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENCR_TIM9ENC                    RCC_APB2ENCR_TIM9ENC_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENCR_SPI5ENC_Pos                (20U)
+#define RCC_APB2ENCR_SPI5ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENCR_SPI5ENC                    RCC_APB2ENCR_SPI5ENC_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENCR_SAI1ENC_Pos                (21U)
+#define RCC_APB2ENCR_SAI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENCR_SAI1ENC                    RCC_APB2ENCR_SAI1ENC_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENCR_SAI2ENC_Pos                (22U)
+#define RCC_APB2ENCR_SAI2ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENCR_SAI2ENC                    RCC_APB2ENCR_SAI2ENC_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENCR register  *****************/
+#define RCC_APB3ENCR_DFTENC_Pos                 (2U)
+#define RCC_APB3ENCR_DFTENC_Msk                 (0x1UL << RCC_APB3ENCR_DFTENC_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENCR_DFTENC                     RCC_APB3ENCR_DFTENC_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENCR1 register  *****************/
+#define RCC_APB4ENCR1_HDPENC_Pos                (2U)
+#define RCC_APB4ENCR1_HDPENC_Msk                (0x1UL << RCC_APB4ENCR1_HDPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR1_HDPENC                    RCC_APB4ENCR1_HDPENC_Msk             /*!< HDP enable */
+#define RCC_APB4ENCR1_LPUART1ENC_Pos            (3U)
+#define RCC_APB4ENCR1_LPUART1ENC_Msk            (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENCR1_LPUART1ENC                RCC_APB4ENCR1_LPUART1ENC_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENCR1_SPI6ENC_Pos               (5U)
+#define RCC_APB4ENCR1_SPI6ENC_Msk               (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENCR1_SPI6ENC                   RCC_APB4ENCR1_SPI6ENC_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENCR1_I2C4ENC_Pos               (7U)
+#define RCC_APB4ENCR1_I2C4ENC_Msk               (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENCR1_I2C4ENC                   RCC_APB4ENCR1_I2C4ENC_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENCR1_LPTIM2ENC_Pos             (9U)
+#define RCC_APB4ENCR1_LPTIM2ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENCR1_LPTIM2ENC                 RCC_APB4ENCR1_LPTIM2ENC_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENCR1_LPTIM3ENC_Pos             (10U)
+#define RCC_APB4ENCR1_LPTIM3ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENCR1_LPTIM3ENC                 RCC_APB4ENCR1_LPTIM3ENC_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENCR1_LPTIM4ENC_Pos             (11U)
+#define RCC_APB4ENCR1_LPTIM4ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENCR1_LPTIM4ENC                 RCC_APB4ENCR1_LPTIM4ENC_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENCR1_LPTIM5ENC_Pos             (12U)
+#define RCC_APB4ENCR1_LPTIM5ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENCR1_LPTIM5ENC                 RCC_APB4ENCR1_LPTIM5ENC_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENCR1_VREFBUFENC_Pos            (15U)
+#define RCC_APB4ENCR1_VREFBUFENC_Msk            (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENCR1_VREFBUFENC                RCC_APB4ENCR1_VREFBUFENC_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENCR1_RTCENC_Pos                (16U)
+#define RCC_APB4ENCR1_RTCENC_Msk                (0x1UL << RCC_APB4ENCR1_RTCENC_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENCR1_RTCENC                    RCC_APB4ENCR1_RTCENC_Msk             /*!< RTC enable */
+#define RCC_APB4ENCR1_RTCAPBENC_Pos             (17U)
+#define RCC_APB4ENCR1_RTCAPBENC_Msk             (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENCR1_RTCAPBENC                 RCC_APB4ENCR1_RTCAPBENC_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENCR2 register  *****************/
+#define RCC_APB4ENCR2_SYSCFGENC_Pos             (0U)
+#define RCC_APB4ENCR2_SYSCFGENC_Msk             (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENCR2_SYSCFGENC                 RCC_APB4ENCR2_SYSCFGENC_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENCR2_BSECENC_Pos               (1U)
+#define RCC_APB4ENCR2_BSECENC_Msk               (0x1UL << RCC_APB4ENCR2_BSECENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENCR2_BSECENC                   RCC_APB4ENCR2_BSECENC_Msk            /*!< BSEC enable */
+#define RCC_APB4ENCR2_DTSENC_Pos                (2U)
+#define RCC_APB4ENCR2_DTSENC_Msk                (0x1UL << RCC_APB4ENCR2_DTSENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR2_DTSENC                    RCC_APB4ENCR2_DTSENC_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENCR register  *****************/
+#define RCC_APB5ENCR_LTDCENC_Pos                (1U)
+#define RCC_APB5ENCR_LTDCENC_Msk                (0x1UL << RCC_APB5ENCR_LTDCENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENCR_LTDCENC                    RCC_APB5ENCR_LTDCENC_Msk             /*!< LTDC enable */
+#define RCC_APB5ENCR_DCMIPPENC_Pos              (2U)
+#define RCC_APB5ENCR_DCMIPPENC_Msk              (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENCR_DCMIPPENC                  RCC_APB5ENCR_DCMIPPENC_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENCR_GFXTIMENC_Pos              (4U)
+#define RCC_APB5ENCR_GFXTIMENC_Msk              (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENCR_GFXTIMENC                  RCC_APB5ENCR_GFXTIMENC_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENCR_VENCENC_Pos                (5U)
+#define RCC_APB5ENCR_VENCENC_Msk                (0x1UL << RCC_APB5ENCR_VENCENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENCR_VENCENC                    RCC_APB5ENCR_VENCENC_Msk             /*!< VENC enable */
+#define RCC_APB5ENCR_CSIENC_Pos                 (6U)
+#define RCC_APB5ENCR_CSIENC_Msk                 (0x1UL << RCC_APB5ENCR_CSIENC_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENCR_CSIENC                     RCC_APB5ENCR_CSIENC_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENCR register  *****************/
+#define RCC_BUSLPENCR_ACLKNLPENC_Pos            (0U)
+#define RCC_BUSLPENCR_ACLKNLPENC_Msk            (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENCR_ACLKNLPENC                RCC_BUSLPENCR_ACLKNLPENC_Msk         /*!< ACLKN enable in Sleep mode */
+#define RCC_BUSLPENCR_ACLKNCLPENC_Pos           (1U)
+#define RCC_BUSLPENCR_ACLKNCLPENC_Msk           (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENCR_ACLKNCLPENC               RCC_BUSLPENCR_ACLKNCLPENC_Msk        /*!< ACLKNC enable in Sleep mode */
+
+/****************  Bit definition for RCC_MISCLPENCR register  ****************/
+#define RCC_MISCLPENCR_DBGLPENC_Pos             (0U)
+#define RCC_MISCLPENCR_DBGLPENC_Msk             (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENCR_DBGLPENC                 RCC_MISCLPENCR_DBGLPENC_Msk          /*!< DBG enable in Sleep mode */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos     (3U)
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk     (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC         RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk  /*!< XSPIPHYCOMP enable in Sleep mode */
+#define RCC_MISCLPENCR_PERLPENC_Pos             (6U)
+#define RCC_MISCLPENCR_PERLPENC_Msk             (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENCR_PERLPENC                 RCC_MISCLPENCR_PERLPENC_Msk          /*!< PER enable in Sleep mode */
+
+/****************  Bit definition for RCC_MEMLPENCR register  *****************/
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos         (0U)
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENCR_AXISRAM3LPENC             RCC_MEMLPENCR_AXISRAM3LPENC_Msk      /*!< AXISRAM3 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos         (1U)
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENCR_AXISRAM4LPENC             RCC_MEMLPENCR_AXISRAM4LPENC_Msk      /*!< AXISRAM4 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos         (2U)
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENCR_AXISRAM5LPENC             RCC_MEMLPENCR_AXISRAM5LPENC_Msk      /*!< AXISRAM5 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos         (3U)
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENCR_AXISRAM6LPENC             RCC_MEMLPENCR_AXISRAM6LPENC_Msk      /*!< AXISRAM6 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos         (4U)
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC             RCC_MEMLPENCR_AHBSRAM1LPENC_Msk      /*!< AHBSRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos         (5U)
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC             RCC_MEMLPENCR_AHBSRAM2LPENC_Msk      /*!< AHBSRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos          (6U)
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENCR_BKPSRAMLPENC              RCC_MEMLPENCR_BKPSRAMLPENC_Msk       /*!< BKPSRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos         (7U)
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENCR_AXISRAM1LPENC             RCC_MEMLPENCR_AXISRAM1LPENC_Msk      /*!< AXISRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos         (8U)
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENCR_AXISRAM2LPENC             RCC_MEMLPENCR_AXISRAM2LPENC_Msk      /*!< AXISRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos          (9U)
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENCR_FLEXRAMLPENC              RCC_MEMLPENCR_FLEXRAMLPENC_Msk       /*!< FLEXRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_VENCRAMLPENC_Pos          (11U)
+#define RCC_MEMLPENCR_VENCRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENCR_VENCRAMLPENC              RCC_MEMLPENCR_VENCRAMLPENC_Msk       /*!< VENCRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_BOOTROMLPENC_Pos          (12U)
+#define RCC_MEMLPENCR_BOOTROMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENCR_BOOTROMLPENC              RCC_MEMLPENCR_BOOTROMLPENC_Msk       /*!< Boot ROM enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB1LPENCR register  ****************/
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos          (4U)
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk          (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENCR_GPDMA1LPENC              RCC_AHB1LPENCR_GPDMA1LPENC_Msk       /*!< GPDMA1 enable in Sleep mode */
+#define RCC_AHB1LPENCR_ADC12LPENC_Pos           (5U)
+#define RCC_AHB1LPENCR_ADC12LPENC_Msk           (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENCR_ADC12LPENC               RCC_AHB1LPENCR_ADC12LPENC_Msk        /*!< ADC12 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB2LPENCR register  ****************/
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos          (12U)
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk          (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENCR_RAMCFGLPENC              RCC_AHB2LPENCR_RAMCFGLPENC_Msk       /*!< RAMCFG enable in Sleep mode */
+#define RCC_AHB2LPENCR_MDF1LPENC_Pos            (16U)
+#define RCC_AHB2LPENCR_MDF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENCR_MDF1LPENC                RCC_AHB2LPENCR_MDF1LPENC_Msk         /*!< MDF1 enable in Sleep mode */
+#define RCC_AHB2LPENCR_ADF1LPENC_Pos            (17U)
+#define RCC_AHB2LPENCR_ADF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENCR_ADF1LPENC                RCC_AHB2LPENCR_ADF1LPENC_Msk         /*!< ADF1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB3LPENCR register  ****************/
+#define RCC_AHB3LPENCR_RNGLPENC_Pos             (0U)
+#define RCC_AHB3LPENCR_RNGLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENCR_RNGLPENC                 RCC_AHB3LPENCR_RNGLPENC_Msk          /*!< RNG enable in Sleep mode */
+#define RCC_AHB3LPENCR_HASHLPENC_Pos            (1U)
+#define RCC_AHB3LPENCR_HASHLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENCR_HASHLPENC                RCC_AHB3LPENCR_HASHLPENC_Msk         /*!< HASH enable in Sleep mode */
+#define RCC_AHB3LPENCR_CRYPLPENC_Pos            (2U)
+#define RCC_AHB3LPENCR_CRYPLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */
+#define RCC_AHB3LPENCR_CRYPLPENC                RCC_AHB3LPENCR_CRYPLPENC_Msk         /*!< CRYP enable in Sleep mode */
+#define RCC_AHB3LPENCR_SAESLPENC_Pos            (4U)
+#define RCC_AHB3LPENCR_SAESLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */
+#define RCC_AHB3LPENCR_SAESLPENC                RCC_AHB3LPENCR_SAESLPENC_Msk         /*!< SAES enable in Sleep mode */
+#define RCC_AHB3LPENCR_PKALPENC_Pos             (8U)
+#define RCC_AHB3LPENCR_PKALPENC_Msk             (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENCR_PKALPENC                 RCC_AHB3LPENCR_PKALPENC_Msk          /*!< PKA enable in Sleep mode */
+#define RCC_AHB3LPENCR_RIFSCLPENC_Pos           (9U)
+#define RCC_AHB3LPENCR_RIFSCLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENCR_RIFSCLPENC               RCC_AHB3LPENCR_RIFSCLPENC_Msk        /*!< RIFSC enable in Sleep mode */
+#define RCC_AHB3LPENCR_IACLPENC_Pos             (10U)
+#define RCC_AHB3LPENCR_IACLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENCR_IACLPENC                 RCC_AHB3LPENCR_IACLPENC_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENCR_RISAFLPENC_Pos           (14U)
+#define RCC_AHB3LPENCR_RISAFLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENCR_RISAFLPENC               RCC_AHB3LPENCR_RISAFLPENC_Msk        /*!< RISAF enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB4LPENCR register  ****************/
+#define RCC_AHB4LPENCR_GPIOALPENC_Pos           (0U)
+#define RCC_AHB4LPENCR_GPIOALPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENCR_GPIOALPENC               RCC_AHB4LPENCR_GPIOALPENC_Msk        /*!< GPIO A enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOBLPENC_Pos           (1U)
+#define RCC_AHB4LPENCR_GPIOBLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENCR_GPIOBLPENC               RCC_AHB4LPENCR_GPIOBLPENC_Msk        /*!< GPIO B enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOCLPENC_Pos           (2U)
+#define RCC_AHB4LPENCR_GPIOCLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENCR_GPIOCLPENC               RCC_AHB4LPENCR_GPIOCLPENC_Msk        /*!< GPIO C enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIODLPENC_Pos           (3U)
+#define RCC_AHB4LPENCR_GPIODLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENCR_GPIODLPENC               RCC_AHB4LPENCR_GPIODLPENC_Msk        /*!< GPIO D enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOELPENC_Pos           (4U)
+#define RCC_AHB4LPENCR_GPIOELPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENCR_GPIOELPENC               RCC_AHB4LPENCR_GPIOELPENC_Msk        /*!< GPIO E enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOFLPENC_Pos           (5U)
+#define RCC_AHB4LPENCR_GPIOFLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENCR_GPIOFLPENC               RCC_AHB4LPENCR_GPIOFLPENC_Msk        /*!< GPIO F enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOGLPENC_Pos           (6U)
+#define RCC_AHB4LPENCR_GPIOGLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENCR_GPIOGLPENC               RCC_AHB4LPENCR_GPIOGLPENC_Msk        /*!< GPIO G enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOHLPENC_Pos           (7U)
+#define RCC_AHB4LPENCR_GPIOHLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENCR_GPIOHLPENC               RCC_AHB4LPENCR_GPIOHLPENC_Msk        /*!< GPIO H enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIONLPENC_Pos           (13U)
+#define RCC_AHB4LPENCR_GPIONLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENCR_GPIONLPENC               RCC_AHB4LPENCR_GPIONLPENC_Msk        /*!< GPIO N enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOOLPENC_Pos           (14U)
+#define RCC_AHB4LPENCR_GPIOOLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENCR_GPIOOLPENC               RCC_AHB4LPENCR_GPIOOLPENC_Msk        /*!< GPIO O enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOPLPENC_Pos           (15U)
+#define RCC_AHB4LPENCR_GPIOPLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENCR_GPIOPLPENC               RCC_AHB4LPENCR_GPIOPLPENC_Msk        /*!< GPIO P enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOQLPENC_Pos           (16U)
+#define RCC_AHB4LPENCR_GPIOQLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENCR_GPIOQLPENC               RCC_AHB4LPENCR_GPIOQLPENC_Msk        /*!< GPIO Q enable in Sleep mode */
+#define RCC_AHB4LPENCR_PWRLPENC_Pos             (18U)
+#define RCC_AHB4LPENCR_PWRLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENCR_PWRLPENC                 RCC_AHB4LPENCR_PWRLPENC_Msk          /*!< PWR enable in Sleep mode */
+#define RCC_AHB4LPENCR_CRCLPENC_Pos             (19U)
+#define RCC_AHB4LPENCR_CRCLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENCR_CRCLPENC                 RCC_AHB4LPENCR_CRCLPENC_Msk          /*!< CRC enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB5LPENCR register  ****************/
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos          (0U)
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENCR_HPDMA1LPENC              RCC_AHB5LPENCR_HPDMA1LPENC_Msk       /*!< HPDMA1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_DMA2DLPENC_Pos           (1U)
+#define RCC_AHB5LPENCR_DMA2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENCR_DMA2DLPENC               RCC_AHB5LPENCR_DMA2DLPENC_Msk        /*!< DMA2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_JPEGLPENC_Pos            (3U)
+#define RCC_AHB5LPENCR_JPEGLPENC_Msk            (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENCR_JPEGLPENC                RCC_AHB5LPENCR_JPEGLPENC_Msk         /*!< JPEG enable in Sleep mode */
+#define RCC_AHB5LPENCR_FMCLPENC_Pos             (4U)
+#define RCC_AHB5LPENCR_FMCLPENC_Msk             (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENCR_FMCLPENC                 RCC_AHB5LPENCR_FMCLPENC_Msk          /*!< FMC enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI1LPENC_Pos           (5U)
+#define RCC_AHB5LPENCR_XSPI1LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENCR_XSPI1LPENC               RCC_AHB5LPENCR_XSPI1LPENC_Msk        /*!< XSPI1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_PSSILPENC_Pos            (6U)
+#define RCC_AHB5LPENCR_PSSILPENC_Msk            (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENCR_PSSILPENC                RCC_AHB5LPENCR_PSSILPENC_Msk         /*!< PSSI enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos          (7U)
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENCR_SDMMC2LPENC              RCC_AHB5LPENCR_SDMMC2LPENC_Msk       /*!< SDMMC2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos          (8U)
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENCR_SDMMC1LPENC              RCC_AHB5LPENCR_SDMMC1LPENC_Msk       /*!< SDMMC1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI2LPENC_Pos           (12U)
+#define RCC_AHB5LPENCR_XSPI2LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENCR_XSPI2LPENC               RCC_AHB5LPENCR_XSPI2LPENC_Msk        /*!< XSPI2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPIMLPENC_Pos           (13U)
+#define RCC_AHB5LPENCR_XSPIMLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENCR_XSPIMLPENC               RCC_AHB5LPENCR_XSPIMLPENC_Msk        /*!< XSPIM enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE1LPENC_Pos            (14U)
+#define RCC_AHB5LPENCR_MCE1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */
+#define RCC_AHB5LPENCR_MCE1LPENC                RCC_AHB5LPENCR_MCE1LPENC_Msk         /*!< MCE1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE2LPENC_Pos            (15U)
+#define RCC_AHB5LPENCR_MCE2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */
+#define RCC_AHB5LPENCR_MCE2LPENC                RCC_AHB5LPENCR_MCE2LPENC_Msk         /*!< MCE2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE3LPENC_Pos            (16U)
+#define RCC_AHB5LPENCR_MCE3LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */
+#define RCC_AHB5LPENCR_MCE3LPENC                RCC_AHB5LPENCR_MCE3LPENC_Msk         /*!< MCE3 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI3LPENC_Pos           (17U)
+#define RCC_AHB5LPENCR_XSPI3LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENCR_XSPI3LPENC               RCC_AHB5LPENCR_XSPI3LPENC_Msk        /*!< XSPI3 enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE4LPENC_Pos            (18U)
+#define RCC_AHB5LPENCR_MCE4LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */
+#define RCC_AHB5LPENCR_MCE4LPENC                RCC_AHB5LPENCR_MCE4LPENC_Msk         /*!< MCE4 enable in Sleep mode */
+#define RCC_AHB5LPENCR_GFXMMULPENC_Pos          (19U)
+#define RCC_AHB5LPENCR_GFXMMULPENC_Msk          (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENCR_GFXMMULPENC              RCC_AHB5LPENCR_GFXMMULPENC_Msk       /*!< GFXMMU enable in Sleep mode */
+#define RCC_AHB5LPENCR_GPU2DLPENC_Pos           (20U)
+#define RCC_AHB5LPENCR_GPU2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENCR_GPU2DLPENC               RCC_AHB5LPENCR_GPU2DLPENC_Msk        /*!< GPU2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos         (22U)
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk         (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENCR_ETH1MACLPENC             RCC_AHB5LPENCR_ETH1MACLPENC_Msk      /*!< ETH1MAC enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos          (23U)
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENCR_ETH1TXLPENC              RCC_AHB5LPENCR_ETH1TXLPENC_Msk       /*!< ETH1TX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos          (24U)
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENCR_ETH1RXLPENC              RCC_AHB5LPENCR_ETH1RXLPENC_Msk       /*!< ETH1RX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1LPENC_Pos            (25U)
+#define RCC_AHB5LPENCR_ETH1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENCR_ETH1LPENC                RCC_AHB5LPENCR_ETH1LPENC_Msk         /*!< ETH1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG1LPENC_Pos            (26U)
+#define RCC_AHB5LPENCR_OTG1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENCR_OTG1LPENC                RCC_AHB5LPENCR_OTG1LPENC_Msk         /*!< OTG1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos         (27U)
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC             RCC_AHB5LPENCR_OTGPHY1LPENC_Msk      /*!< OTGPHY1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos         (28U)
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC             RCC_AHB5LPENCR_OTGPHY2LPENC_Msk      /*!< OTGPHY2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG2LPENC_Pos            (29U)
+#define RCC_AHB5LPENCR_OTG2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENCR_OTG2LPENC                RCC_AHB5LPENCR_OTG2LPENC_Msk         /*!< OTG2 enable in Sleep mode */
+
+/***************  Bit definition for RCC_APB1LPENCR1 register  ****************/
+#define RCC_APB1LPENCR1_TIM2LPENC_Pos           (0U)
+#define RCC_APB1LPENCR1_TIM2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENCR1_TIM2LPENC               RCC_APB1LPENCR1_TIM2LPENC_Msk        /*!< TIM2 enable */
+#define RCC_APB1LPENCR1_TIM3LPENC_Pos           (1U)
+#define RCC_APB1LPENCR1_TIM3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENCR1_TIM3LPENC               RCC_APB1LPENCR1_TIM3LPENC_Msk        /*!< TIM3 enable */
+#define RCC_APB1LPENCR1_TIM4LPENC_Pos           (2U)
+#define RCC_APB1LPENCR1_TIM4LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENCR1_TIM4LPENC               RCC_APB1LPENCR1_TIM4LPENC_Msk        /*!< TIM4 enable */
+#define RCC_APB1LPENCR1_TIM5LPENC_Pos           (3U)
+#define RCC_APB1LPENCR1_TIM5LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENCR1_TIM5LPENC               RCC_APB1LPENCR1_TIM5LPENC_Msk        /*!< TIM5 enable */
+#define RCC_APB1LPENCR1_TIM6LPENC_Pos           (4U)
+#define RCC_APB1LPENCR1_TIM6LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENCR1_TIM6LPENC               RCC_APB1LPENCR1_TIM6LPENC_Msk        /*!< TIM6 enable */
+#define RCC_APB1LPENCR1_TIM7LPENC_Pos           (5U)
+#define RCC_APB1LPENCR1_TIM7LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENCR1_TIM7LPENC               RCC_APB1LPENCR1_TIM7LPENC_Msk        /*!< TIM7 enable */
+#define RCC_APB1LPENCR1_TIM12LPENC_Pos          (6U)
+#define RCC_APB1LPENCR1_TIM12LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENCR1_TIM12LPENC              RCC_APB1LPENCR1_TIM12LPENC_Msk       /*!< TIM12 enable */
+#define RCC_APB1LPENCR1_TIM13LPENC_Pos          (7U)
+#define RCC_APB1LPENCR1_TIM13LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENCR1_TIM13LPENC              RCC_APB1LPENCR1_TIM13LPENC_Msk       /*!< TIM13 enable */
+#define RCC_APB1LPENCR1_TIM14LPENC_Pos          (8U)
+#define RCC_APB1LPENCR1_TIM14LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR1_TIM14LPENC              RCC_APB1LPENCR1_TIM14LPENC_Msk       /*!< TIM14 enable */
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos         (9U)
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENCR1_LPTIM1LPENC             RCC_APB1LPENCR1_LPTIM1LPENC_Msk      /*!< LPTIM1 enable */
+#define RCC_APB1LPENCR1_WWDGLPENC_Pos           (11U)
+#define RCC_APB1LPENCR1_WWDGLPENC_Msk           (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENCR1_WWDGLPENC               RCC_APB1LPENCR1_WWDGLPENC_Msk        /*!< WWDG enable */
+#define RCC_APB1LPENCR1_TIM10LPENC_Pos          (12U)
+#define RCC_APB1LPENCR1_TIM10LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENCR1_TIM10LPENC              RCC_APB1LPENCR1_TIM10LPENC_Msk       /*!< TIM10 enable */
+#define RCC_APB1LPENCR1_TIM11LPENC_Pos          (13U)
+#define RCC_APB1LPENCR1_TIM11LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENCR1_TIM11LPENC              RCC_APB1LPENCR1_TIM11LPENC_Msk       /*!< TIM11 enable */
+#define RCC_APB1LPENCR1_SPI2LPENC_Pos           (14U)
+#define RCC_APB1LPENCR1_SPI2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENCR1_SPI2LPENC               RCC_APB1LPENCR1_SPI2LPENC_Msk        /*!< SPI2 enable */
+#define RCC_APB1LPENCR1_SPI3LPENC_Pos           (15U)
+#define RCC_APB1LPENCR1_SPI3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENCR1_SPI3LPENC               RCC_APB1LPENCR1_SPI3LPENC_Msk        /*!< SPI3 enable */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos       (16U)
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk       (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC           RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk    /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENCR1_USART2LPENC_Pos         (17U)
+#define RCC_APB1LPENCR1_USART2LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENCR1_USART2LPENC             RCC_APB1LPENCR1_USART2LPENC_Msk      /*!< USART2 enable */
+#define RCC_APB1LPENCR1_USART3LPENC_Pos         (18U)
+#define RCC_APB1LPENCR1_USART3LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENCR1_USART3LPENC             RCC_APB1LPENCR1_USART3LPENC_Msk      /*!< USART3 enable */
+#define RCC_APB1LPENCR1_UART4LPENC_Pos          (19U)
+#define RCC_APB1LPENCR1_UART4LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENCR1_UART4LPENC              RCC_APB1LPENCR1_UART4LPENC_Msk       /*!< UART4 enable */
+#define RCC_APB1LPENCR1_UART5LPENC_Pos          (20U)
+#define RCC_APB1LPENCR1_UART5LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENCR1_UART5LPENC              RCC_APB1LPENCR1_UART5LPENC_Msk       /*!< UART5 enable */
+#define RCC_APB1LPENCR1_I2C1LPENC_Pos           (21U)
+#define RCC_APB1LPENCR1_I2C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENCR1_I2C1LPENC               RCC_APB1LPENCR1_I2C1LPENC_Msk        /*!< I2C1 enable */
+#define RCC_APB1LPENCR1_I2C2LPENC_Pos           (22U)
+#define RCC_APB1LPENCR1_I2C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENCR1_I2C2LPENC               RCC_APB1LPENCR1_I2C2LPENC_Msk        /*!< I2C2 enable */
+#define RCC_APB1LPENCR1_I2C3LPENC_Pos           (23U)
+#define RCC_APB1LPENCR1_I2C3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENCR1_I2C3LPENC               RCC_APB1LPENCR1_I2C3LPENC_Msk        /*!< I2C3 enable */
+#define RCC_APB1LPENCR1_I3C1LPENC_Pos           (24U)
+#define RCC_APB1LPENCR1_I3C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENCR1_I3C1LPENC               RCC_APB1LPENCR1_I3C1LPENC_Msk        /*!< I3C1 enable */
+#define RCC_APB1LPENCR1_I3C2LPENC_Pos           (25U)
+#define RCC_APB1LPENCR1_I3C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENCR1_I3C2LPENC               RCC_APB1LPENCR1_I3C2LPENC_Msk        /*!< I3C2 enable */
+#define RCC_APB1LPENCR1_UART7LPENC_Pos          (30U)
+#define RCC_APB1LPENCR1_UART7LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENCR1_UART7LPENC              RCC_APB1LPENCR1_UART7LPENC_Msk       /*!< UART7 enable */
+#define RCC_APB1LPENCR1_UART8LPENC_Pos          (31U)
+#define RCC_APB1LPENCR1_UART8LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENCR1_UART8LPENC              RCC_APB1LPENCR1_UART8LPENC_Msk       /*!< UART8 enable */
+
+/***************  Bit definition for RCC_APB1LPENCR2 register  ****************/
+#define RCC_APB1LPENCR2_MDIOSLPENC_Pos          (5U)
+#define RCC_APB1LPENCR2_MDIOSLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENCR2_MDIOSLPENC              RCC_APB1LPENCR2_MDIOSLPENC_Msk       /*!< MDIOS enable */
+#define RCC_APB1LPENCR2_FDCANLPENC_Pos          (8U)
+#define RCC_APB1LPENCR2_FDCANLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR2_FDCANLPENC              RCC_APB1LPENCR2_FDCANLPENC_Msk       /*!< FDCAN enable */
+#define RCC_APB1LPENCR2_UCPD1LPENC_Pos          (18U)
+#define RCC_APB1LPENCR2_UCPD1LPENC_Msk          (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENCR2_UCPD1LPENC              RCC_APB1LPENCR2_UCPD1LPENC_Msk       /*!< UCPD1 enable */
+
+/****************  Bit definition for RCC_APB2LPENCR register  ****************/
+#define RCC_APB2LPENCR_TIM1LPENC_Pos            (0U)
+#define RCC_APB2LPENCR_TIM1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENCR_TIM1LPENC                RCC_APB2LPENCR_TIM1LPENC_Msk         /*!< TIM1 enable */
+#define RCC_APB2LPENCR_TIM8LPENC_Pos            (1U)
+#define RCC_APB2LPENCR_TIM8LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENCR_TIM8LPENC                RCC_APB2LPENCR_TIM8LPENC_Msk         /*!< TIM8 enable */
+#define RCC_APB2LPENCR_USART1LPENC_Pos          (4U)
+#define RCC_APB2LPENCR_USART1LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENCR_USART1LPENC              RCC_APB2LPENCR_USART1LPENC_Msk       /*!< USART1 enable */
+#define RCC_APB2LPENCR_USART6LPENC_Pos          (5U)
+#define RCC_APB2LPENCR_USART6LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENCR_USART6LPENC              RCC_APB2LPENCR_USART6LPENC_Msk       /*!< USART6 enable */
+#define RCC_APB2LPENCR_UART9LPENC_Pos           (6U)
+#define RCC_APB2LPENCR_UART9LPENC_Msk           (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENCR_UART9LPENC               RCC_APB2LPENCR_UART9LPENC_Msk        /*!< UART9 enable */
+#define RCC_APB2LPENCR_USART10LPENC_Pos         (7U)
+#define RCC_APB2LPENCR_USART10LPENC_Msk         (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENCR_USART10LPENC             RCC_APB2LPENCR_USART10LPENC_Msk      /*!< USART10 enable */
+#define RCC_APB2LPENCR_SPI1LPENC_Pos            (12U)
+#define RCC_APB2LPENCR_SPI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENCR_SPI1LPENC                RCC_APB2LPENCR_SPI1LPENC_Msk         /*!< SPI1 enable */
+#define RCC_APB2LPENCR_SPI4LPENC_Pos            (13U)
+#define RCC_APB2LPENCR_SPI4LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENCR_SPI4LPENC                RCC_APB2LPENCR_SPI4LPENC_Msk         /*!< SPI4 enable */
+#define RCC_APB2LPENCR_TIM18LPENC_Pos           (15U)
+#define RCC_APB2LPENCR_TIM18LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENCR_TIM18LPENC               RCC_APB2LPENCR_TIM18LPENC_Msk        /*!< TIM18 enable */
+#define RCC_APB2LPENCR_TIM15LPENC_Pos           (16U)
+#define RCC_APB2LPENCR_TIM15LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENCR_TIM15LPENC               RCC_APB2LPENCR_TIM15LPENC_Msk        /*!< TIM15 enable */
+#define RCC_APB2LPENCR_TIM16LPENC_Pos           (17U)
+#define RCC_APB2LPENCR_TIM16LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENCR_TIM16LPENC               RCC_APB2LPENCR_TIM16LPENC_Msk        /*!< TIM16 enable */
+#define RCC_APB2LPENCR_TIM17LPENC_Pos           (18U)
+#define RCC_APB2LPENCR_TIM17LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENCR_TIM17LPENC               RCC_APB2LPENCR_TIM17LPENC_Msk        /*!< TIM17 enable */
+#define RCC_APB2LPENCR_TIM9LPENC_Pos            (19U)
+#define RCC_APB2LPENCR_TIM9LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENCR_TIM9LPENC                RCC_APB2LPENCR_TIM9LPENC_Msk         /*!< TIM9 enable */
+#define RCC_APB2LPENCR_SPI5LPENC_Pos            (20U)
+#define RCC_APB2LPENCR_SPI5LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENCR_SPI5LPENC                RCC_APB2LPENCR_SPI5LPENC_Msk         /*!< SPI5 enable */
+#define RCC_APB2LPENCR_SAI1LPENC_Pos            (21U)
+#define RCC_APB2LPENCR_SAI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENCR_SAI1LPENC                RCC_APB2LPENCR_SAI1LPENC_Msk         /*!< SAI1 enable */
+#define RCC_APB2LPENCR_SAI2LPENC_Pos            (22U)
+#define RCC_APB2LPENCR_SAI2LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENCR_SAI2LPENC                RCC_APB2LPENCR_SAI2LPENC_Msk         /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENCR register  ****************/
+#define RCC_APB3LPENCR_DFTLPENC_Pos             (2U)
+#define RCC_APB3LPENCR_DFTLPENC_Msk             (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENCR_DFTLPENC                 RCC_APB3LPENCR_DFTLPENC_Msk          /*!< DFT enable */
+
+/***************  Bit definition for RCC_APB4LPENCR1 register  ****************/
+#define RCC_APB4LPENCR1_HDPLPENC_Pos            (2U)
+#define RCC_APB4LPENCR1_HDPLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR1_HDPLPENC                RCC_APB4LPENCR1_HDPLPENC_Msk         /*!< HDP enable */
+#define RCC_APB4LPENCR1_LPUART1LPENC_Pos        (3U)
+#define RCC_APB4LPENCR1_LPUART1LPENC_Msk        (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENCR1_LPUART1LPENC            RCC_APB4LPENCR1_LPUART1LPENC_Msk     /*!< LPUART1 enable */
+#define RCC_APB4LPENCR1_SPI6LPENC_Pos           (5U)
+#define RCC_APB4LPENCR1_SPI6LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENCR1_SPI6LPENC               RCC_APB4LPENCR1_SPI6LPENC_Msk        /*!< SPI6 enable */
+#define RCC_APB4LPENCR1_I2C4LPENC_Pos           (7U)
+#define RCC_APB4LPENCR1_I2C4LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENCR1_I2C4LPENC               RCC_APB4LPENCR1_I2C4LPENC_Msk        /*!< I2C4 enable */
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos         (9U)
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENCR1_LPTIM2LPENC             RCC_APB4LPENCR1_LPTIM2LPENC_Msk      /*!< LPTIM2 enable */
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos         (10U)
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENCR1_LPTIM3LPENC             RCC_APB4LPENCR1_LPTIM3LPENC_Msk      /*!< LPTIM3 enable */
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos         (11U)
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENCR1_LPTIM4LPENC             RCC_APB4LPENCR1_LPTIM4LPENC_Msk      /*!< LPTIM4 enable */
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos         (12U)
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENCR1_LPTIM5LPENC             RCC_APB4LPENCR1_LPTIM5LPENC_Msk      /*!< LPTIM5 enable */
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos        (15U)
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk        (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENCR1_VREFBUFLPENC            RCC_APB4LPENCR1_VREFBUFLPENC_Msk     /*!< VREFBUF enable */
+#define RCC_APB4LPENCR1_RTCLPENC_Pos            (16U)
+#define RCC_APB4LPENCR1_RTCLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENCR1_RTCLPENC                RCC_APB4LPENCR1_RTCLPENC_Msk         /*!< RTC enable */
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos         (17U)
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk         (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENCR1_RTCAPBLPENC             RCC_APB4LPENCR1_RTCAPBLPENC_Msk      /*!< RTCAPB enable */
+
+/***************  Bit definition for RCC_APB4LPENCR2 register  ****************/
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos         (0U)
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk         (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENCR2_SYSCFGLPENC             RCC_APB4LPENCR2_SYSCFGLPENC_Msk      /*!< SYSCFG enable */
+#define RCC_APB4LPENCR2_BSECLPENC_Pos           (1U)
+#define RCC_APB4LPENCR2_BSECLPENC_Msk           (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENCR2_BSECLPENC               RCC_APB4LPENCR2_BSECLPENC_Msk        /*!< BSEC enable */
+#define RCC_APB4LPENCR2_DTSLPENC_Pos            (2U)
+#define RCC_APB4LPENCR2_DTSLPENC_Msk            (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR2_DTSLPENC                RCC_APB4LPENCR2_DTSLPENC_Msk         /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENCR register  ****************/
+#define RCC_APB5LPENCR_LTDCLPENC_Pos            (1U)
+#define RCC_APB5LPENCR_LTDCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENCR_LTDCLPENC                RCC_APB5LPENCR_LTDCLPENC_Msk         /*!< LTDC sleep enable */
+#define RCC_APB5LPENCR_DCMIPPLPENC_Pos          (2U)
+#define RCC_APB5LPENCR_DCMIPPLPENC_Msk          (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENCR_DCMIPPLPENC              RCC_APB5LPENCR_DCMIPPLPENC_Msk       /*!< DCMIPP sleep enable */
+#define RCC_APB5LPENCR_GFXTIMLPENC_Pos          (4U)
+#define RCC_APB5LPENCR_GFXTIMLPENC_Msk          (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENCR_GFXTIMLPENC              RCC_APB5LPENCR_GFXTIMLPENC_Msk       /*!< GFXTIM sleep enable */
+#define RCC_APB5LPENCR_VENCLPENC_Pos            (5U)
+#define RCC_APB5LPENCR_VENCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENCR_VENCLPENC                RCC_APB5LPENCR_VENCLPENC_Msk         /*!< VENC sleep enable */
+#define RCC_APB5LPENCR_CSILPENC_Pos             (6U)
+#define RCC_APB5LPENCR_CSILPENC_Msk             (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENCR_CSILPENC                 RCC_APB5LPENCR_CSILPENC_Msk          /*!< CSI sleep enable */
+
+/****************  Bit definition for RCC_PRIVCFGCR0 register  ****************/
+#define RCC_PRIVCFGCR0_LSIPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR0_LSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR0_LSIPRIVC                 RCC_PRIVCFGCR0_LSIPRIVC_Msk          /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_LSEPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR0_LSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR0_LSEPRIVC                 RCC_PRIVCFGCR0_LSEPRIVC_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_MSIPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR0_MSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR0_MSIPRIVC                 RCC_PRIVCFGCR0_MSIPRIVC_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSIPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR0_HSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR0_HSIPRIVC                 RCC_PRIVCFGCR0_HSIPRIVC_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSEPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR0_HSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR0_HSEPRIVC                 RCC_PRIVCFGCR0_HSEPRIVC_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR0 register  *****************/
+#define RCC_PUBCFGCR0_LSIPUBC_Pos               (0U)
+#define RCC_PUBCFGCR0_LSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR0_LSIPUBC                   RCC_PUBCFGCR0_LSIPUBC_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_LSEPUBC_Pos               (1U)
+#define RCC_PUBCFGCR0_LSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR0_LSEPUBC                   RCC_PUBCFGCR0_LSEPUBC_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_MSIPUBC_Pos               (2U)
+#define RCC_PUBCFGCR0_MSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR0_MSIPUBC                   RCC_PUBCFGCR0_MSIPUBC_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSIPUBC_Pos               (3U)
+#define RCC_PUBCFGCR0_HSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR0_HSIPUBC                   RCC_PUBCFGCR0_HSIPUBC_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSEPUBC_Pos               (4U)
+#define RCC_PUBCFGCR0_HSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR0_HSEPUBC                   RCC_PUBCFGCR0_HSEPUBC_Msk            /*!< Public protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR1 register  ****************/
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos            (0U)
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGCR1_PLL1PRIVC                RCC_PRIVCFGCR1_PLL1PRIVC_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos            (1U)
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGCR1_PLL2PRIVC                RCC_PRIVCFGCR1_PLL2PRIVC_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR1_PLL3PRIVC                RCC_PRIVCFGCR1_PLL3PRIVC_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR1_PLL4PRIVC                RCC_PRIVCFGCR1_PLL4PRIVC_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR1 register  *****************/
+#define RCC_PUBCFGCR1_PLL1PUBC_Pos              (0U)
+#define RCC_PUBCFGCR1_PLL1PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGCR1_PLL1PUBC                  RCC_PUBCFGCR1_PLL1PUBC_Msk           /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL2PUBC_Pos              (1U)
+#define RCC_PUBCFGCR1_PLL2PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR1_PLL2PUBC                  RCC_PUBCFGCR1_PLL2PUBC_Msk           /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL3PUBC_Pos              (2U)
+#define RCC_PUBCFGCR1_PLL3PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR1_PLL3PUBC                  RCC_PUBCFGCR1_PLL3PUBC_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL4PUBC_Pos              (3U)
+#define RCC_PUBCFGCR1_PLL4PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR1_PLL4PUBC                  RCC_PUBCFGCR1_PLL4PUBC_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR2 register  ****************/
+#define RCC_PRIVCFGCR2_IC1PRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR2_IC1PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR2_IC1PRIVC                 RCC_PRIVCFGCR2_IC1PRIVC_Msk          /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC2PRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR2_IC2PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR2_IC2PRIVC                 RCC_PRIVCFGCR2_IC2PRIVC_Msk          /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC3PRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR2_IC3PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR2_IC3PRIVC                 RCC_PRIVCFGCR2_IC3PRIVC_Msk          /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC4PRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR2_IC4PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR2_IC4PRIVC                 RCC_PRIVCFGCR2_IC4PRIVC_Msk          /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC5PRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR2_IC5PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR2_IC5PRIVC                 RCC_PRIVCFGCR2_IC5PRIVC_Msk          /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC6PRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR2_IC6PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR2_IC6PRIVC                 RCC_PRIVCFGCR2_IC6PRIVC_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC7PRIVC_Pos             (6U)
+#define RCC_PRIVCFGCR2_IC7PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGCR2_IC7PRIVC                 RCC_PRIVCFGCR2_IC7PRIVC_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC8PRIVC_Pos             (7U)
+#define RCC_PRIVCFGCR2_IC8PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGCR2_IC8PRIVC                 RCC_PRIVCFGCR2_IC8PRIVC_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC9PRIVC_Pos             (8U)
+#define RCC_PRIVCFGCR2_IC9PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGCR2_IC9PRIVC                 RCC_PRIVCFGCR2_IC9PRIVC_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC10PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR2_IC10PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR2_IC10PRIVC                RCC_PRIVCFGCR2_IC10PRIVC_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC11PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR2_IC11PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR2_IC11PRIVC                RCC_PRIVCFGCR2_IC11PRIVC_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC12PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR2_IC12PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR2_IC12PRIVC                RCC_PRIVCFGCR2_IC12PRIVC_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC13PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR2_IC13PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR2_IC13PRIVC                RCC_PRIVCFGCR2_IC13PRIVC_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC14PRIVC_Pos            (13U)
+#define RCC_PRIVCFGCR2_IC14PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGCR2_IC14PRIVC                RCC_PRIVCFGCR2_IC14PRIVC_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC15PRIVC_Pos            (14U)
+#define RCC_PRIVCFGCR2_IC15PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGCR2_IC15PRIVC                RCC_PRIVCFGCR2_IC15PRIVC_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC16PRIVC_Pos            (15U)
+#define RCC_PRIVCFGCR2_IC16PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGCR2_IC16PRIVC                RCC_PRIVCFGCR2_IC16PRIVC_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC17PRIVC_Pos            (16U)
+#define RCC_PRIVCFGCR2_IC17PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGCR2_IC17PRIVC                RCC_PRIVCFGCR2_IC17PRIVC_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC18PRIVC_Pos            (17U)
+#define RCC_PRIVCFGCR2_IC18PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGCR2_IC18PRIVC                RCC_PRIVCFGCR2_IC18PRIVC_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC19PRIVC_Pos            (18U)
+#define RCC_PRIVCFGCR2_IC19PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGCR2_IC19PRIVC                RCC_PRIVCFGCR2_IC19PRIVC_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC20PRIVC_Pos            (19U)
+#define RCC_PRIVCFGCR2_IC20PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGCR2_IC20PRIVC                RCC_PRIVCFGCR2_IC20PRIVC_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR2 register  *****************/
+#define RCC_PUBCFGCR2_IC1PUBC_Pos               (0U)
+#define RCC_PUBCFGCR2_IC1PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR2_IC1PUBC                   RCC_PUBCFGCR2_IC1PUBC_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC2PUBC_Pos               (1U)
+#define RCC_PUBCFGCR2_IC2PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR2_IC2PUBC                   RCC_PUBCFGCR2_IC2PUBC_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC3PUBC_Pos               (2U)
+#define RCC_PUBCFGCR2_IC3PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR2_IC3PUBC                   RCC_PUBCFGCR2_IC3PUBC_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC4PUBC_Pos               (3U)
+#define RCC_PUBCFGCR2_IC4PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR2_IC4PUBC                   RCC_PUBCFGCR2_IC4PUBC_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC5PUBC_Pos               (4U)
+#define RCC_PUBCFGCR2_IC5PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR2_IC5PUBC                   RCC_PUBCFGCR2_IC5PUBC_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC6PUBC_Pos               (5U)
+#define RCC_PUBCFGCR2_IC6PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR2_IC6PUBC                   RCC_PUBCFGCR2_IC6PUBC_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC7PUBC_Pos               (6U)
+#define RCC_PUBCFGCR2_IC7PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR2_IC7PUBC                   RCC_PUBCFGCR2_IC7PUBC_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC8PUBC_Pos               (7U)
+#define RCC_PUBCFGCR2_IC8PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGCR2_IC8PUBC                   RCC_PUBCFGCR2_IC8PUBC_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC9PUBC_Pos               (8U)
+#define RCC_PUBCFGCR2_IC9PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGCR2_IC9PUBC                   RCC_PUBCFGCR2_IC9PUBC_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC10PUBC_Pos              (9U)
+#define RCC_PUBCFGCR2_IC10PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR2_IC10PUBC                  RCC_PUBCFGCR2_IC10PUBC_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC11PUBC_Pos              (10U)
+#define RCC_PUBCFGCR2_IC11PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR2_IC11PUBC                  RCC_PUBCFGCR2_IC11PUBC_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC12PUBC_Pos              (11U)
+#define RCC_PUBCFGCR2_IC12PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR2_IC12PUBC                  RCC_PUBCFGCR2_IC12PUBC_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC13PUBC_Pos              (12U)
+#define RCC_PUBCFGCR2_IC13PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR2_IC13PUBC                  RCC_PUBCFGCR2_IC13PUBC_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC14PUBC_Pos              (13U)
+#define RCC_PUBCFGCR2_IC14PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGCR2_IC14PUBC                  RCC_PUBCFGCR2_IC14PUBC_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC15PUBC_Pos              (14U)
+#define RCC_PUBCFGCR2_IC15PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGCR2_IC15PUBC                  RCC_PUBCFGCR2_IC15PUBC_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC16PUBC_Pos              (15U)
+#define RCC_PUBCFGCR2_IC16PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGCR2_IC16PUBC                  RCC_PUBCFGCR2_IC16PUBC_Msk           /*!< Public protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC17PUBC_Pos              (16U)
+#define RCC_PUBCFGCR2_IC17PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGCR2_IC17PUBC                  RCC_PUBCFGCR2_IC17PUBC_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC18PUBC_Pos              (17U)
+#define RCC_PUBCFGCR2_IC18PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGCR2_IC18PUBC                  RCC_PUBCFGCR2_IC18PUBC_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC19PUBC_Pos              (18U)
+#define RCC_PUBCFGCR2_IC19PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGCR2_IC19PUBC                  RCC_PUBCFGCR2_IC19PUBC_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC20PUBC_Pos              (19U)
+#define RCC_PUBCFGCR2_IC20PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGCR2_IC20PUBC                  RCC_PUBCFGCR2_IC20PUBC_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR3 register  ****************/
+#define RCC_PRIVCFGCR3_MODPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR3_MODPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR3_MODPRIVC                 RCC_PRIVCFGCR3_MODPRIVC_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_SYSPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR3_SYSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR3_SYSPRIVC                 RCC_PRIVCFGCR3_SYSPRIVC_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_BUSPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR3_BUSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR3_BUSPRIVC                 RCC_PRIVCFGCR3_BUSPRIVC_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_PERPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR3_PERPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR3_PERPRIVC                 RCC_PRIVCFGCR3_PERPRIVC_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_INTPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR3_INTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR3_INTPRIVC                 RCC_PRIVCFGCR3_INTPRIVC_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_RSTPRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR3_RSTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR3_RSTPRIVC                 RCC_PRIVCFGCR3_RSTPRIVC_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR3 register  *****************/
+#define RCC_PUBCFGCR3_MODPUBC_Pos               (0U)
+#define RCC_PUBCFGCR3_MODPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR3_MODPUBC                   RCC_PUBCFGCR3_MODPUBC_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_SYSPUBC_Pos               (1U)
+#define RCC_PUBCFGCR3_SYSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR3_SYSPUBC                   RCC_PUBCFGCR3_SYSPUBC_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_BUSPUBC_Pos               (2U)
+#define RCC_PUBCFGCR3_BUSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR3_BUSPUBC                   RCC_PUBCFGCR3_BUSPUBC_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_PERPUBC_Pos               (3U)
+#define RCC_PUBCFGCR3_PERPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR3_PERPUBC                   RCC_PUBCFGCR3_PERPUBC_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_INTPUBC_Pos               (4U)
+#define RCC_PUBCFGCR3_INTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR3_INTPUBC                   RCC_PUBCFGCR3_INTPUBC_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_RSTPUBC_Pos               (5U)
+#define RCC_PUBCFGCR3_RSTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR3_RSTPUBC                   RCC_PUBCFGCR3_RSTPUBC_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR4 register  ****************/
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos           (0U)
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk           (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGCR4_ACLKNPRIVC               RCC_PRIVCFGCR4_ACLKNPRIVC_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos          (1U)
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk          (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC              RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk       /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR4_AHBMPRIVC                RCC_PRIVCFGCR4_AHBMPRIVC_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR4_AHB1PRIVC                RCC_PRIVCFGCR4_AHB1PRIVC_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos            (4U)
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGCR4_AHB2PRIVC                RCC_PRIVCFGCR4_AHB2PRIVC_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos            (5U)
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGCR4_AHB3PRIVC                RCC_PRIVCFGCR4_AHB3PRIVC_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos            (6U)
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGCR4_AHB4PRIVC                RCC_PRIVCFGCR4_AHB4PRIVC_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos            (7U)
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGCR4_AHB5PRIVC                RCC_PRIVCFGCR4_AHB5PRIVC_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB1PRIVC_Pos            (8U)
+#define RCC_PRIVCFGCR4_APB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGCR4_APB1PRIVC                RCC_PRIVCFGCR4_APB1PRIVC_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB2PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR4_APB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR4_APB2PRIVC                RCC_PRIVCFGCR4_APB2PRIVC_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB3PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR4_APB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR4_APB3PRIVC                RCC_PRIVCFGCR4_APB3PRIVC_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB4PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR4_APB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR4_APB4PRIVC                RCC_PRIVCFGCR4_APB4PRIVC_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB5PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR4_APB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR4_APB5PRIVC                RCC_PRIVCFGCR4_APB5PRIVC_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_NOCPRIVC_Pos             (13U)
+#define RCC_PRIVCFGCR4_NOCPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGCR4_NOCPRIVC                 RCC_PRIVCFGCR4_NOCPRIVC_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR4 register  *****************/
+#define RCC_PUBCFGCR4_ACLKNPUBC_Pos             (0U)
+#define RCC_PUBCFGCR4_ACLKNPUBC_Msk             (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGCR4_ACLKNPUBC                 RCC_PUBCFGCR4_ACLKNPUBC_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos            (1U)
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk            (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR4_ACLKNCPUBC                RCC_PUBCFGCR4_ACLKNCPUBC_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHBMPUBC_Pos              (2U)
+#define RCC_PUBCFGCR4_AHBMPUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR4_AHBMPUBC                  RCC_PUBCFGCR4_AHBMPUBC_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB1PUBC_Pos              (3U)
+#define RCC_PUBCFGCR4_AHB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR4_AHB1PUBC                  RCC_PUBCFGCR4_AHB1PUBC_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB2PUBC_Pos              (4U)
+#define RCC_PUBCFGCR4_AHB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGCR4_AHB2PUBC                  RCC_PUBCFGCR4_AHB2PUBC_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB3PUBC_Pos              (5U)
+#define RCC_PUBCFGCR4_AHB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGCR4_AHB3PUBC                  RCC_PUBCFGCR4_AHB3PUBC_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB4PUBC_Pos              (6U)
+#define RCC_PUBCFGCR4_AHB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGCR4_AHB4PUBC                  RCC_PUBCFGCR4_AHB4PUBC_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB5PUBC_Pos              (7U)
+#define RCC_PUBCFGCR4_AHB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGCR4_AHB5PUBC                  RCC_PUBCFGCR4_AHB5PUBC_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB1PUBC_Pos              (8U)
+#define RCC_PUBCFGCR4_APB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGCR4_APB1PUBC                  RCC_PUBCFGCR4_APB1PUBC_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB2PUBC_Pos              (9U)
+#define RCC_PUBCFGCR4_APB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR4_APB2PUBC                  RCC_PUBCFGCR4_APB2PUBC_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB3PUBC_Pos              (10U)
+#define RCC_PUBCFGCR4_APB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR4_APB3PUBC                  RCC_PUBCFGCR4_APB3PUBC_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB4PUBC_Pos              (11U)
+#define RCC_PUBCFGCR4_APB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR4_APB4PUBC                  RCC_PUBCFGCR4_APB4PUBC_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB5PUBC_Pos              (12U)
+#define RCC_PUBCFGCR4_APB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR4_APB5PUBC                  RCC_PUBCFGCR4_APB5PUBC_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_NOCPUBC_Pos               (13U)
+#define RCC_PUBCFGCR4_NOCPUBC_Msk               (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGCR4_NOCPUBC                   RCC_PUBCFGCR4_NOCPUBC_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR5 register  *****************/
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos          (0U)
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGCR5_AXISRAM3PUBC              RCC_PUBCFGCR5_AXISRAM3PUBC_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos          (1U)
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC              RCC_PUBCFGCR5_AXISRAM4PUBC_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos          (2U)
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC              RCC_PUBCFGCR5_AXISRAM5PUBC_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos          (3U)
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC              RCC_PUBCFGCR5_AXISRAM6PUBC_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos          (4U)
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC              RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos          (5U)
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC              RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos           (6U)
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC               RCC_PUBCFGCR5_BKPSRAMPUBC_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos          (7U)
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC              RCC_PUBCFGCR5_AXISRAM1PUBC_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos          (8U)
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC              RCC_PUBCFGCR5_AXISRAM2PUBC_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos           (9U)
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC               RCC_PUBCFGCR5_FLEXRAMPUBC_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos           (11U)
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGCR5_VENCRAMPUBC               RCC_PUBCFGCR5_VENCRAMPUBC_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*          Resource Isolation Framework Security Controller (RIFSC)          */
+/*                                                                            */
+/******************************************************************************/
+/****************  Bit definition for RIFSC_RISC_CR register  *****************/
+#define RIFSC_RISC_CR_GLOCK_Pos             (0UL)
+#define RIFSC_RISC_CR_GLOCK_Msk             (0x1UL << RIFSC_RISC_CR_GLOCK_Pos)             /*!< 0x00000001 */
+#define RIFSC_RISC_CR_GLOCK                 RIFSC_RISC_CR_GLOCK_Msk                        /*!< Global lock */
+
+/*************  Bit definition for RIFSC_RISC_SECCFGRx register  **************/
+#define RIFSC_RISC_SECCFGRx_SEC0_Pos        (0U)
+#define RIFSC_RISC_SECCFGRx_SEC0_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos)         /*!< 0x00000001 */
+#define RIFSC_RISC_SECCFGRx_SEC0            RIFSC_RISC_SECCFGRx_SEC0_Msk                   /*!< Security configuration for peripheral 0 */
+#define RIFSC_RISC_SECCFGRx_SEC1_Pos        (1U)
+#define RIFSC_RISC_SECCFGRx_SEC1_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos)         /*!< 0x00000002 */
+#define RIFSC_RISC_SECCFGRx_SEC1            RIFSC_RISC_SECCFGRx_SEC1_Msk                   /*!< Security configuration for peripheral 1 */
+#define RIFSC_RISC_SECCFGRx_SEC2_Pos        (2U)
+#define RIFSC_RISC_SECCFGRx_SEC2_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos)         /*!< 0x00000004 */
+#define RIFSC_RISC_SECCFGRx_SEC2            RIFSC_RISC_SECCFGRx_SEC2_Msk                   /*!< Security configuration for peripheral 2 */
+#define RIFSC_RISC_SECCFGRx_SEC3_Pos        (3U)
+#define RIFSC_RISC_SECCFGRx_SEC3_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos)         /*!< 0x00000008 */
+#define RIFSC_RISC_SECCFGRx_SEC3            RIFSC_RISC_SECCFGRx_SEC3_Msk                   /*!< Security configuration for peripheral 3 */
+#define RIFSC_RISC_SECCFGRx_SEC4_Pos        (4U)
+#define RIFSC_RISC_SECCFGRx_SEC4_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos)         /*!< 0x00000010 */
+#define RIFSC_RISC_SECCFGRx_SEC4            RIFSC_RISC_SECCFGRx_SEC4_Msk                   /*!< Security configuration for peripheral 4 */
+#define RIFSC_RISC_SECCFGRx_SEC5_Pos        (5U)
+#define RIFSC_RISC_SECCFGRx_SEC5_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos)         /*!< 0x00000020 */
+#define RIFSC_RISC_SECCFGRx_SEC5            RIFSC_RISC_SECCFGRx_SEC5_Msk                   /*!< Security configuration for peripheral 5 */
+#define RIFSC_RISC_SECCFGRx_SEC6_Pos        (6U)
+#define RIFSC_RISC_SECCFGRx_SEC6_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos)         /*!< 0x00000040 */
+#define RIFSC_RISC_SECCFGRx_SEC6            RIFSC_RISC_SECCFGRx_SEC6_Msk                   /*!< Security configuration for peripheral 6 */
+#define RIFSC_RISC_SECCFGRx_SEC7_Pos        (7U)
+#define RIFSC_RISC_SECCFGRx_SEC7_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos)         /*!< 0x00000080 */
+#define RIFSC_RISC_SECCFGRx_SEC7            RIFSC_RISC_SECCFGRx_SEC7_Msk                   /*!< Security configuration for peripheral 7 */
+#define RIFSC_RISC_SECCFGRx_SEC8_Pos        (8U)
+#define RIFSC_RISC_SECCFGRx_SEC8_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos)         /*!< 0x00000100 */
+#define RIFSC_RISC_SECCFGRx_SEC8            RIFSC_RISC_SECCFGRx_SEC8_Msk                   /*!< Security configuration for peripheral 8 */
+#define RIFSC_RISC_SECCFGRx_SEC9_Pos        (9U)
+#define RIFSC_RISC_SECCFGRx_SEC9_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos)         /*!< 0x00000200 */
+#define RIFSC_RISC_SECCFGRx_SEC9            RIFSC_RISC_SECCFGRx_SEC9_Msk                   /*!< Security configuration for peripheral 9 */
+#define RIFSC_RISC_SECCFGRx_SEC10_Pos       (10U)
+#define RIFSC_RISC_SECCFGRx_SEC10_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos)        /*!< 0x00000400 */
+#define RIFSC_RISC_SECCFGRx_SEC10           RIFSC_RISC_SECCFGRx_SEC10_Msk                  /*!< Security configuration for peripheral 10 */
+#define RIFSC_RISC_SECCFGRx_SEC11_Pos       (11U)
+#define RIFSC_RISC_SECCFGRx_SEC11_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos)        /*!< 0x00000800 */
+#define RIFSC_RISC_SECCFGRx_SEC11           RIFSC_RISC_SECCFGRx_SEC11_Msk                  /*!< Security configuration for peripheral 11 */
+#define RIFSC_RISC_SECCFGRx_SEC12_Pos       (12U)
+#define RIFSC_RISC_SECCFGRx_SEC12_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos)        /*!< 0x00001000 */
+#define RIFSC_RISC_SECCFGRx_SEC12           RIFSC_RISC_SECCFGRx_SEC12_Msk                  /*!< Security configuration for peripheral 12 */
+#define RIFSC_RISC_SECCFGRx_SEC13_Pos       (13U)
+#define RIFSC_RISC_SECCFGRx_SEC13_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos)        /*!< 0x00002000 */
+#define RIFSC_RISC_SECCFGRx_SEC13           RIFSC_RISC_SECCFGRx_SEC13_Msk                  /*!< Security configuration for peripheral 13 */
+#define RIFSC_RISC_SECCFGRx_SEC14_Pos       (14U)
+#define RIFSC_RISC_SECCFGRx_SEC14_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos)        /*!< 0x00004000 */
+#define RIFSC_RISC_SECCFGRx_SEC14           RIFSC_RISC_SECCFGRx_SEC14_Msk                  /*!< Security configuration for peripheral 14 */
+#define RIFSC_RISC_SECCFGRx_SEC15_Pos       (15U)
+#define RIFSC_RISC_SECCFGRx_SEC15_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos)        /*!< 0x00008000 */
+#define RIFSC_RISC_SECCFGRx_SEC15           RIFSC_RISC_SECCFGRx_SEC15_Msk                  /*!< Security configuration for peripheral 15 */
+#define RIFSC_RISC_SECCFGRx_SEC16_Pos       (16U)
+#define RIFSC_RISC_SECCFGRx_SEC16_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos)        /*!< 0x00010000 */
+#define RIFSC_RISC_SECCFGRx_SEC16           RIFSC_RISC_SECCFGRx_SEC16_Msk                  /*!< Security configuration for peripheral 16 */
+#define RIFSC_RISC_SECCFGRx_SEC17_Pos       (17U)
+#define RIFSC_RISC_SECCFGRx_SEC17_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos)        /*!< 0x00020000 */
+#define RIFSC_RISC_SECCFGRx_SEC17           RIFSC_RISC_SECCFGRx_SEC17_Msk                  /*!< Security configuration for peripheral 17 */
+#define RIFSC_RISC_SECCFGRx_SEC18_Pos       (18U)
+#define RIFSC_RISC_SECCFGRx_SEC18_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos)        /*!< 0x00040000 */
+#define RIFSC_RISC_SECCFGRx_SEC18           RIFSC_RISC_SECCFGRx_SEC18_Msk                  /*!< Security configuration for peripheral 18 */
+#define RIFSC_RISC_SECCFGRx_SEC19_Pos       (19U)
+#define RIFSC_RISC_SECCFGRx_SEC19_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos)        /*!< 0x00080000 */
+#define RIFSC_RISC_SECCFGRx_SEC19           RIFSC_RISC_SECCFGRx_SEC19_Msk                  /*!< Security configuration for peripheral 19 */
+#define RIFSC_RISC_SECCFGRx_SEC20_Pos       (20U)
+#define RIFSC_RISC_SECCFGRx_SEC20_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos)        /*!< 0x00100000 */
+#define RIFSC_RISC_SECCFGRx_SEC20           RIFSC_RISC_SECCFGRx_SEC20_Msk                  /*!< Security configuration for peripheral 20 */
+#define RIFSC_RISC_SECCFGRx_SEC21_Pos       (21U)
+#define RIFSC_RISC_SECCFGRx_SEC21_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos)        /*!< 0x00200000 */
+#define RIFSC_RISC_SECCFGRx_SEC21           RIFSC_RISC_SECCFGRx_SEC21_Msk                  /*!< Security configuration for peripheral 21 */
+#define RIFSC_RISC_SECCFGRx_SEC22_Pos       (22U)
+#define RIFSC_RISC_SECCFGRx_SEC22_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos)        /*!< 0x00400000 */
+#define RIFSC_RISC_SECCFGRx_SEC22           RIFSC_RISC_SECCFGRx_SEC22_Msk                  /*!< Security configuration for peripheral 22 */
+#define RIFSC_RISC_SECCFGRx_SEC23_Pos       (23U)
+#define RIFSC_RISC_SECCFGRx_SEC23_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos)        /*!< 0x00800000 */
+#define RIFSC_RISC_SECCFGRx_SEC23           RIFSC_RISC_SECCFGRx_SEC23_Msk                  /*!< Security configuration for peripheral 23 */
+#define RIFSC_RISC_SECCFGRx_SEC24_Pos       (24U)
+#define RIFSC_RISC_SECCFGRx_SEC24_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos)        /*!< 0x01000000 */
+#define RIFSC_RISC_SECCFGRx_SEC24           RIFSC_RISC_SECCFGRx_SEC24_Msk                  /*!< Security configuration for peripheral 24 */
+#define RIFSC_RISC_SECCFGRx_SEC25_Pos       (25U)
+#define RIFSC_RISC_SECCFGRx_SEC25_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos)        /*!< 0x02000000 */
+#define RIFSC_RISC_SECCFGRx_SEC25           RIFSC_RISC_SECCFGRx_SEC25_Msk                  /*!< Security configuration for peripheral 25 */
+#define RIFSC_RISC_SECCFGRx_SEC26_Pos       (26U)
+#define RIFSC_RISC_SECCFGRx_SEC26_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos)        /*!< 0x04000000 */
+#define RIFSC_RISC_SECCFGRx_SEC26           RIFSC_RISC_SECCFGRx_SEC26_Msk                  /*!< Security configuration for peripheral 26 */
+#define RIFSC_RISC_SECCFGRx_SEC27_Pos       (27U)
+#define RIFSC_RISC_SECCFGRx_SEC27_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos)        /*!< 0x08000000 */
+#define RIFSC_RISC_SECCFGRx_SEC27           RIFSC_RISC_SECCFGRx_SEC27_Msk                  /*!< Security configuration for peripheral 27 */
+#define RIFSC_RISC_SECCFGRx_SEC28_Pos       (28U)
+#define RIFSC_RISC_SECCFGRx_SEC28_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos)        /*!< 0x10000000 */
+#define RIFSC_RISC_SECCFGRx_SEC28           RIFSC_RISC_SECCFGRx_SEC28_Msk                  /*!< Security configuration for peripheral 28 */
+#define RIFSC_RISC_SECCFGRx_SEC29_Pos       (29U)
+#define RIFSC_RISC_SECCFGRx_SEC29_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos)        /*!< 0x20000000 */
+#define RIFSC_RISC_SECCFGRx_SEC29           RIFSC_RISC_SECCFGRx_SEC29_Msk                  /*!< Security configuration for peripheral 29 */
+#define RIFSC_RISC_SECCFGRx_SEC30_Pos       (30U)
+#define RIFSC_RISC_SECCFGRx_SEC30_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos)        /*!< 0x40000000 */
+#define RIFSC_RISC_SECCFGRx_SEC30           RIFSC_RISC_SECCFGRx_SEC30_Msk                  /*!< Security configuration for peripheral 30 */
+#define RIFSC_RISC_SECCFGRx_SEC31_Pos       (31U)
+#define RIFSC_RISC_SECCFGRx_SEC31_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos)        /*!< 0x80000000 */
+#define RIFSC_RISC_SECCFGRx_SEC31           RIFSC_RISC_SECCFGRx_SEC31_Msk                  /*!< Security configuration for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_PRIVCFGRx register  *************/
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos      (0U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos)       /*!< 0x00000001 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV0          RIFSC_RISC_PRIVCFGRx_PRIV0_Msk                 /*!< privileged-only access permission for peripheral 0 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos      (1U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos)       /*!< 0x00000002 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1          RIFSC_RISC_PRIVCFGRx_PRIV1_Msk                 /*!< privileged-only access permission for peripheral 1 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos      (2U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos)       /*!< 0x00000004 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2          RIFSC_RISC_PRIVCFGRx_PRIV2_Msk                 /*!< privileged-only access permission for peripheral 2 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos      (3U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos)       /*!< 0x00000008 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3          RIFSC_RISC_PRIVCFGRx_PRIV3_Msk                 /*!< privileged-only access permission for peripheral 3 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos      (4U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos)       /*!< 0x00000010 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4          RIFSC_RISC_PRIVCFGRx_PRIV4_Msk                 /*!< privileged-only access permission for peripheral 4 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos      (5U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos)       /*!< 0x00000020 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5          RIFSC_RISC_PRIVCFGRx_PRIV5_Msk                 /*!< privileged-only access permission for peripheral 5 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos      (6U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos)       /*!< 0x00000040 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6          RIFSC_RISC_PRIVCFGRx_PRIV6_Msk                 /*!< privileged-only access permission for peripheral 6 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos      (7U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos)       /*!< 0x00000080 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7          RIFSC_RISC_PRIVCFGRx_PRIV7_Msk                 /*!< privileged-only access permission for peripheral 7 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos      (8U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos)       /*!< 0x00000100 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8          RIFSC_RISC_PRIVCFGRx_PRIV8_Msk                 /*!< privileged-only access permission for peripheral 8 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos      (9U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos)       /*!< 0x00000200 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9          RIFSC_RISC_PRIVCFGRx_PRIV9_Msk                 /*!< privileged-only access permission for peripheral 9 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos     (10U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos)      /*!< 0x00000400 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10         RIFSC_RISC_PRIVCFGRx_PRIV10_Msk                /*!< privileged-only access permission for peripheral 10 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos     (11U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos)      /*!< 0x00000800 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11         RIFSC_RISC_PRIVCFGRx_PRIV11_Msk                /*!< privileged-only access permission for peripheral 11 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos     (12U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos)      /*!< 0x00001000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12         RIFSC_RISC_PRIVCFGRx_PRIV12_Msk                /*!< privileged-only access permission for peripheral 12 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos     (13U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos)      /*!< 0x00002000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13         RIFSC_RISC_PRIVCFGRx_PRIV13_Msk                /*!< privileged-only access permission for peripheral 13 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos     (14U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos)      /*!< 0x00004000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14         RIFSC_RISC_PRIVCFGRx_PRIV14_Msk                /*!< privileged-only access permission for peripheral 14 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos     (15U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos)      /*!< 0x00008000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15         RIFSC_RISC_PRIVCFGRx_PRIV15_Msk                /*!< privileged-only access permission for peripheral 15 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos     (16U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos)      /*!< 0x00010000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16         RIFSC_RISC_PRIVCFGRx_PRIV16_Msk                /*!< privileged-only access permission for peripheral 16 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos     (17U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos)      /*!< 0x00020000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17         RIFSC_RISC_PRIVCFGRx_PRIV17_Msk                /*!< privileged-only access permission for peripheral 17 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos     (18U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos)      /*!< 0x00040000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18         RIFSC_RISC_PRIVCFGRx_PRIV18_Msk                /*!< privileged-only access permission for peripheral 18 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos     (19U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos)      /*!< 0x00080000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19         RIFSC_RISC_PRIVCFGRx_PRIV19_Msk                /*!< privileged-only access permission for peripheral 19 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos     (20U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos)      /*!< 0x00100000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20         RIFSC_RISC_PRIVCFGRx_PRIV20_Msk                /*!< privileged-only access permission for peripheral 20 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos     (21U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos)      /*!< 0x00200000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21         RIFSC_RISC_PRIVCFGRx_PRIV21_Msk                /*!< privileged-only access permission for peripheral 21 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos     (22U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos)      /*!< 0x00400000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22         RIFSC_RISC_PRIVCFGRx_PRIV22_Msk                /*!< privileged-only access permission for peripheral 22 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos     (23U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos)      /*!< 0x00800000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23         RIFSC_RISC_PRIVCFGRx_PRIV23_Msk                /*!< privileged-only access permission for peripheral 23 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos     (24U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos)      /*!< 0x01000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24         RIFSC_RISC_PRIVCFGRx_PRIV24_Msk                /*!< privileged-only access permission for peripheral 24 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos     (25U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos)      /*!< 0x02000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25         RIFSC_RISC_PRIVCFGRx_PRIV25_Msk                /*!< privileged-only access permission for peripheral 25 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos     (26U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos)      /*!< 0x04000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26         RIFSC_RISC_PRIVCFGRx_PRIV26_Msk                /*!< privileged-only access permission for peripheral 26 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos     (27U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos)      /*!< 0x08000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27         RIFSC_RISC_PRIVCFGRx_PRIV27_Msk                /*!< privileged-only access permission for peripheral 27 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos     (28U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos)      /*!< 0x10000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28         RIFSC_RISC_PRIVCFGRx_PRIV28_Msk                /*!< privileged-only access permission for peripheral 28 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos     (29U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos)      /*!< 0x20000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29         RIFSC_RISC_PRIVCFGRx_PRIV29_Msk                /*!< privileged-only access permission for peripheral 29 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos     (30U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos)      /*!< 0x40000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30         RIFSC_RISC_PRIVCFGRx_PRIV30_Msk                /*!< privileged-only access permission for peripheral 30 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos     (31U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos)      /*!< 0x80000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31         RIFSC_RISC_PRIVCFGRx_PRIV31_Msk                /*!< privileged-only access permission for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_RCFGLOCKRx register  *************/
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos    (0U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos)     /*!< 0x00000001 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0        RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk               /*!< Resource lock for peripheral 0 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos    (1U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos)     /*!< 0x00000002 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1        RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk               /*!< Resource lock for peripheral 1 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos    (2U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos)     /*!< 0x00000004 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2        RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk               /*!< Resource lock for peripheral 2 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos    (3U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos)     /*!< 0x00000008 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3        RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk               /*!< Resource lock for peripheral 3 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos    (4U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos)     /*!< 0x00000010 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4        RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk               /*!< Resource lock for peripheral 4 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos    (5U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos)     /*!< 0x00000020 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5        RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk               /*!< Resource lock for peripheral 5 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos    (6U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos)     /*!< 0x00000040 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6        RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk               /*!< Resource lock for peripheral 6 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos    (7U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos)     /*!< 0x00000080 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7        RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk               /*!< Resource lock for peripheral 7 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos    (8U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos)     /*!< 0x00000100 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8        RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk               /*!< Resource lock for peripheral 8 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos    (9U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos)     /*!< 0x00000200 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9        RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk               /*!< Resource lock for peripheral 9 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos   (10U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos)    /*!< 0x00000400 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10       RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk              /*!< Resource lock for peripheral 10 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos   (11U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos)    /*!< 0x00000800 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11       RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk              /*!< Resource lock for peripheral 11 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos   (12U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos)    /*!< 0x00001000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12       RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk              /*!< Resource lock for peripheral 12 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos   (13U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos)    /*!< 0x00002000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13       RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk              /*!< Resource lock for peripheral 13 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos   (14U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos)    /*!< 0x00004000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14       RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk              /*!< Resource lock for peripheral 14 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos   (15U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos)    /*!< 0x00008000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15       RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk              /*!< Resource lock for peripheral 15 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos   (16U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos)    /*!< 0x00010000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16       RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk              /*!< Resource lock for peripheral 16 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos   (17U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos)    /*!< 0x00020000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17       RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk              /*!< Resource lock for peripheral 17 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos   (18U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos)    /*!< 0x00040000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18       RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk              /*!< Resource lock for peripheral 18 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos   (19U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos)    /*!< 0x00080000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19       RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk              /*!< Resource lock for peripheral 19 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos   (20U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos)    /*!< 0x00100000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20       RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk              /*!< Resource lock for peripheral 20 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos   (21U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos)    /*!< 0x00200000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21       RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk              /*!< Resource lock for peripheral 21 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos   (22U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos)    /*!< 0x00400000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22       RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk              /*!< Resource lock for peripheral 22 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos   (23U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos)    /*!< 0x00800000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23       RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk              /*!< Resource lock for peripheral 23 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos   (24U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos)    /*!< 0x01000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24       RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk              /*!< Resource lock for peripheral 24 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos   (25U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos)    /*!< 0x02000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25       RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk              /*!< Resource lock for peripheral 25 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos   (26U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos)    /*!< 0x04000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26       RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk              /*!< Resource lock for peripheral 26 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos   (27U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos)    /*!< 0x08000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27       RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk              /*!< Resource lock for peripheral 27 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos   (28U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos)    /*!< 0x10000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28       RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk              /*!< Resource lock for peripheral 28 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos   (29U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos)    /*!< 0x20000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29       RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk              /*!< Resource lock for peripheral 29 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos   (30U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos)    /*!< 0x40000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30       RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk              /*!< Resource lock for peripheral 30 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos   (31U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos)    /*!< 0x80000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31       RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk              /*!< Resource lock for peripheral 31 */
+
+/****************  Bit definition for RIFSC_RIMC_CR register  *****************/
+#define RIFSC_RIMC_CR_GLOCK_Pos             (0U)
+#define RIFSC_RIMC_CR_GLOCK_Msk             (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos)              /*!< 0x00000001 */
+#define RIFSC_RIMC_CR_GLOCK                 RIFSC_RIMC_CR_GLOCK_Msk                        /*!< Global lock */
+#define RIFSC_RIMC_CR_DAPCID_Pos            (8U)
+#define RIFSC_RIMC_CR_DAPCID_Msk            (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000700 */
+#define RIFSC_RIMC_CR_DAPCID                RIFSC_RIMC_CR_DAPCID_Msk                       /*!< Debug access port compartment ID */
+#define RIFSC_RIMC_CR_DAPCID_0              (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000100 */
+#define RIFSC_RIMC_CR_DAPCID_1              (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000200 */
+#define RIFSC_RIMC_CR_DAPCID_2              (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000400 */
+
+/***************  Bit definition for RIFSC_RIMC_ATTRx register  ***************/
+#define RIFSC_RIMC_ATTRx_MCID_Pos           (4U)
+#define RIFSC_RIMC_ATTRx_MCID_Msk           (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000070 */
+#define RIFSC_RIMC_ATTRx_MCID               RIFSC_RIMC_ATTRx_MCID_Msk                      /*!< Master CID */
+#define RIFSC_RIMC_ATTRx_MCID_0             (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000010 */
+#define RIFSC_RIMC_ATTRx_MCID_1             (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000020 */
+#define RIFSC_RIMC_ATTRx_MCID_2             (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000040 */
+#define RIFSC_RIMC_ATTRx_MSEC_Pos           (8U)
+#define RIFSC_RIMC_ATTRx_MSEC_Msk           (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos)            /*!< 0x00000100 */
+#define RIFSC_RIMC_ATTRx_MSEC               RIFSC_RIMC_ATTRx_MSEC_Msk                      /*!< Master secure */
+#define RIFSC_RIMC_ATTRx_MPRIV_Pos          (9U)
+#define RIFSC_RIMC_ATTRx_MPRIV_Msk          (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos)           /*!< 0x00000200 */
+#define RIFSC_RIMC_ATTRx_MPRIV              RIFSC_RIMC_ATTRx_MPRIV_Msk                     /*!< Master privileged */
+
+/******************************************************************************/
+/*                                                                            */
+/*     Resource Isolation Slave unit for Address space protection (RISAF)     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RISAF_CR register  *******************/
+#define RISAF_CR_GLOCK_Pos                 (0U)
+#define RISAF_CR_GLOCK_Msk                 (0x1UL << RISAF_CR_GLOCK_Pos)                      /*!< 0x00000001 */
+#define RISAF_CR_GLOCK                     RISAF_CR_GLOCK_Msk                                /*!< Global lock */
+
+/******************  Bit definition for RISAF_IASR register  ******************/
+#define RISAF_IASR_CAEF_Pos                (0U)
+#define RISAF_IASR_CAEF_Msk                (0x1UL << RISAF_IASR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IASR_CAEF                    RISAF_IASR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IASR_IAEF_Pos                (1U)
+#define RISAF_IASR_IAEF_Msk                (0x1UL << RISAF_IASR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IASR_IAEF                    RISAF_IASR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/******************  Bit definition for RISAF_IACR register  ******************/
+#define RISAF_IACR_CAEF_Pos                (0U)
+#define RISAF_IACR_CAEF_Msk                (0x1UL << RISAF_IACR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IACR_CAEF                    RISAF_IACR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IACR_IAEF_Pos                (1U)
+#define RISAF_IACR_IAEF_Msk                (0x1UL << RISAF_IACR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IACR_IAEF                    RISAF_IACR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/*****************  Bit definition for RISAF_IAESR register  *****************/
+#define RISAF_IAESR_IACID_Pos              (0U)
+#define RISAF_IAESR_IACID_Msk              (0x7UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000007 */
+#define RISAF_IAESR_IACID                  RISAF_IAESR_IACID_Msk                            /*!< Illegal access compartment ID */
+#define RISAF_IAESR_IACID_0                (0x1UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000001 */
+#define RISAF_IAESR_IACID_1                (0x2UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000002 */
+#define RISAF_IAESR_IACID_2                (0x4UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000004 */
+#define RISAF_IAESR_IAPRIV_Pos             (4U)
+#define RISAF_IAESR_IAPRIV_Msk             (0x1UL << RISAF_IAESR_IAPRIV_Pos)                 /*!< 0x00000010 */
+#define RISAF_IAESR_IAPRIV                 RISAF_IAESR_IAPRIV_Msk                           /*!< Illegal access privileged */
+#define RISAF_IAESR_IASEC_Pos              (5U)
+#define RISAF_IAESR_IASEC_Msk              (0x1UL << RISAF_IAESR_IASEC_Pos)                  /*!< 0x00000020 */
+#define RISAF_IAESR_IASEC                  RISAF_IAESR_IASEC_Msk                            /*!< Illegal access security */
+#define RISAF_IAESR_IANRW_Pos              (7U)
+#define RISAF_IAESR_IANRW_Msk              (0x1UL << RISAF_IAESR_IANRW_Pos)                  /*!< 0x00000080 */
+#define RISAF_IAESR_IANRW                  RISAF_IAESR_IANRW_Msk                            /*!< Illegal access read/write */
+
+/*****************  Bit definition for RISAF_IADDR register  *****************/
+#define RISAF_IADDR_IADD_Pos                (0U)
+#define RISAF_IADDR_IADD_Msk                (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos)            /*!< 0xFFFFFFFF */
+#define RISAF_IADDR_IADD                    RISAF_IADDR_IADD_Msk                             /*!< Illegal address */
+#define RISAF_IADDR_IADD_0                  (0x1UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000001 */
+#define RISAF_IADDR_IADD_1                  (0x2UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000002 */
+#define RISAF_IADDR_IADD_2                  (0x4UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000004 */
+#define RISAF_IADDR_IADD_3                  (0x8UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000008 */
+#define RISAF_IADDR_IADD_4                  (0x10UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000010 */
+#define RISAF_IADDR_IADD_5                  (0x20UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000020 */
+#define RISAF_IADDR_IADD_6                  (0x40UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000040 */
+#define RISAF_IADDR_IADD_7                  (0x80UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000080 */
+#define RISAF_IADDR_IADD_8                  (0x100UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000100 */
+#define RISAF_IADDR_IADD_9                  (0x200UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000200 */
+#define RISAF_IADDR_IADD_10                 (0x400UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000400 */
+#define RISAF_IADDR_IADD_11                 (0x800UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000800 */
+#define RISAF_IADDR_IADD_12                 (0x1000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00001000 */
+#define RISAF_IADDR_IADD_13                 (0x2000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00002000 */
+#define RISAF_IADDR_IADD_14                 (0x4000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00004000 */
+#define RISAF_IADDR_IADD_15                 (0x8000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00008000 */
+#define RISAF_IADDR_IADD_16                 (0x10000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00010000 */
+#define RISAF_IADDR_IADD_17                 (0x20000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00020000 */
+#define RISAF_IADDR_IADD_18                 (0x40000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00040000 */
+#define RISAF_IADDR_IADD_19                 (0x80000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00080000 */
+#define RISAF_IADDR_IADD_20                 (0x100000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00100000 */
+#define RISAF_IADDR_IADD_21                 (0x200000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00200000 */
+#define RISAF_IADDR_IADD_22                 (0x400000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00400000 */
+#define RISAF_IADDR_IADD_23                 (0x800000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00800000 */
+#define RISAF_IADDR_IADD_24                 (0x1000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x01000000 */
+#define RISAF_IADDR_IADD_25                 (0x2000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x02000000 */
+#define RISAF_IADDR_IADD_26                 (0x4000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x04000000 */
+#define RISAF_IADDR_IADD_27                 (0x8000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x08000000 */
+#define RISAF_IADDR_IADD_28                 (0x10000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x10000000 */
+#define RISAF_IADDR_IADD_29                 (0x20000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x20000000 */
+#define RISAF_IADDR_IADD_30                 (0x40000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x40000000 */
+#define RISAF_IADDR_IADD_31                 (0x80000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_CFGR register  ****************/
+#define RISAF_REGx_CFGR_BREN_Pos           (0U)
+#define RISAF_REGx_CFGR_BREN_Msk           (0x1UL << RISAF_REGx_CFGR_BREN_Pos)                /*!< 0x00000001 */
+#define RISAF_REGx_CFGR_BREN               RISAF_REGx_CFGR_BREN_Msk                          /*!< Base region enable */
+#define RISAF_REGx_CFGR_SEC_Pos            (8U)
+#define RISAF_REGx_CFGR_SEC_Msk            (0x1UL << RISAF_REGx_CFGR_SEC_Pos)                 /*!< 0x00000100 */
+#define RISAF_REGx_CFGR_SEC                RISAF_REGx_CFGR_SEC_Msk                           /*!< Secure region */
+#define RISAF_REGx_CFGR_PRIVC0_Pos         (16U)
+#define RISAF_REGx_CFGR_PRIVC0_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos)              /*!< 0x00010000 */
+#define RISAF_REGx_CFGR_PRIVC0             RISAF_REGx_CFGR_PRIVC0_Msk                        /*!< Privileged access for compartment 0 */
+#define RISAF_REGx_CFGR_PRIVC1_Pos         (17U)
+#define RISAF_REGx_CFGR_PRIVC1_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos)              /*!< 0x00020000 */
+#define RISAF_REGx_CFGR_PRIVC1             RISAF_REGx_CFGR_PRIVC1_Msk                        /*!< Privileged access for compartment 1 */
+#define RISAF_REGx_CFGR_PRIVC2_Pos         (18U)
+#define RISAF_REGx_CFGR_PRIVC2_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos)              /*!< 0x00040000 */
+#define RISAF_REGx_CFGR_PRIVC2             RISAF_REGx_CFGR_PRIVC2_Msk                        /*!< Privileged access for compartment 2 */
+#define RISAF_REGx_CFGR_PRIVC3_Pos         (19U)
+#define RISAF_REGx_CFGR_PRIVC3_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos)              /*!< 0x00080000 */
+#define RISAF_REGx_CFGR_PRIVC3             RISAF_REGx_CFGR_PRIVC3_Msk                        /*!< Privileged access for compartment 3 */
+#define RISAF_REGx_CFGR_PRIVC4_Pos         (20U)
+#define RISAF_REGx_CFGR_PRIVC4_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos)              /*!< 0x00100000 */
+#define RISAF_REGx_CFGR_PRIVC4             RISAF_REGx_CFGR_PRIVC4_Msk                        /*!< Privileged access for compartment 4 */
+#define RISAF_REGx_CFGR_PRIVC5_Pos         (21U)
+#define RISAF_REGx_CFGR_PRIVC5_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos)              /*!< 0x00200000 */
+#define RISAF_REGx_CFGR_PRIVC5             RISAF_REGx_CFGR_PRIVC5_Msk                        /*!< Privileged access for compartment 5 */
+#define RISAF_REGx_CFGR_PRIVC6_Pos         (22U)
+#define RISAF_REGx_CFGR_PRIVC6_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos)              /*!< 0x00400000 */
+#define RISAF_REGx_CFGR_PRIVC6             RISAF_REGx_CFGR_PRIVC6_Msk                        /*!< Privileged access for compartment 6 */
+#define RISAF_REGx_CFGR_PRIVC7_Pos         (23U)
+#define RISAF_REGx_CFGR_PRIVC7_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos)              /*!< 0x00800000 */
+#define RISAF_REGx_CFGR_PRIVC7             RISAF_REGx_CFGR_PRIVC7_Msk                        /*!< Privileged access for compartment 7 */
+
+/**************  Bit definition for RISAF_REGx_STARTR register  ***************/
+#define RISAF_REGx_STARTR_BADDSTART_Pos    (0U)
+#define RISAF_REGx_STARTR_BADDSTART_Msk    (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0xFFFFFFFF */
+#define RISAF_REGx_STARTR_BADDSTART        RISAF_REGx_STARTR_BADDSTART_Msk                   /*!< Base region address start */
+#define RISAF_REGx_STARTR_BADDSTART_0      (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000001 */
+#define RISAF_REGx_STARTR_BADDSTART_1      (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000002 */
+#define RISAF_REGx_STARTR_BADDSTART_2      (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000004 */
+#define RISAF_REGx_STARTR_BADDSTART_3      (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000008 */
+#define RISAF_REGx_STARTR_BADDSTART_4      (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000010 */
+#define RISAF_REGx_STARTR_BADDSTART_5      (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000020 */
+#define RISAF_REGx_STARTR_BADDSTART_6      (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000040 */
+#define RISAF_REGx_STARTR_BADDSTART_7      (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000080 */
+#define RISAF_REGx_STARTR_BADDSTART_8      (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000100 */
+#define RISAF_REGx_STARTR_BADDSTART_9      (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000200 */
+#define RISAF_REGx_STARTR_BADDSTART_10     (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000400 */
+#define RISAF_REGx_STARTR_BADDSTART_11     (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000800 */
+#define RISAF_REGx_STARTR_BADDSTART_12     (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00001000 */
+#define RISAF_REGx_STARTR_BADDSTART_13     (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00002000 */
+#define RISAF_REGx_STARTR_BADDSTART_14     (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00004000 */
+#define RISAF_REGx_STARTR_BADDSTART_15     (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00008000 */
+#define RISAF_REGx_STARTR_BADDSTART_16     (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00010000 */
+#define RISAF_REGx_STARTR_BADDSTART_17     (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00020000 */
+#define RISAF_REGx_STARTR_BADDSTART_18     (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00040000 */
+#define RISAF_REGx_STARTR_BADDSTART_19     (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00080000 */
+#define RISAF_REGx_STARTR_BADDSTART_20     (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00100000 */
+#define RISAF_REGx_STARTR_BADDSTART_21     (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00200000 */
+#define RISAF_REGx_STARTR_BADDSTART_22     (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00400000 */
+#define RISAF_REGx_STARTR_BADDSTART_23     (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00800000 */
+#define RISAF_REGx_STARTR_BADDSTART_24     (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x01000000 */
+#define RISAF_REGx_STARTR_BADDSTART_25     (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x02000000 */
+#define RISAF_REGx_STARTR_BADDSTART_26     (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x04000000 */
+#define RISAF_REGx_STARTR_BADDSTART_27     (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x08000000 */
+#define RISAF_REGx_STARTR_BADDSTART_28     (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x10000000 */
+#define RISAF_REGx_STARTR_BADDSTART_29     (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x20000000 */
+#define RISAF_REGx_STARTR_BADDSTART_30     (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x40000000 */
+#define RISAF_REGx_STARTR_BADDSTART_31     (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_ENDR register  ****************/
+#define RISAF_REGx_ENDR_BADDEND_Pos        (0U)
+#define RISAF_REGx_ENDR_BADDEND_Msk        (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0xFFFFFFFF */
+#define RISAF_REGx_ENDR_BADDEND            RISAF_REGx_ENDR_BADDEND_Msk                       /*!< Base region address end */
+#define RISAF_REGx_ENDR_BADDEND_0          (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000001 */
+#define RISAF_REGx_ENDR_BADDEND_1          (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000002 */
+#define RISAF_REGx_ENDR_BADDEND_2          (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000004 */
+#define RISAF_REGx_ENDR_BADDEND_3          (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000008 */
+#define RISAF_REGx_ENDR_BADDEND_4          (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000010 */
+#define RISAF_REGx_ENDR_BADDEND_5          (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000020 */
+#define RISAF_REGx_ENDR_BADDEND_6          (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000040 */
+#define RISAF_REGx_ENDR_BADDEND_7          (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000080 */
+#define RISAF_REGx_ENDR_BADDEND_8          (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000100 */
+#define RISAF_REGx_ENDR_BADDEND_9          (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000200 */
+#define RISAF_REGx_ENDR_BADDEND_10         (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000400 */
+#define RISAF_REGx_ENDR_BADDEND_11         (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000800 */
+#define RISAF_REGx_ENDR_BADDEND_12         (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00001000 */
+#define RISAF_REGx_ENDR_BADDEND_13         (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00002000 */
+#define RISAF_REGx_ENDR_BADDEND_14         (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00004000 */
+#define RISAF_REGx_ENDR_BADDEND_15         (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00008000 */
+#define RISAF_REGx_ENDR_BADDEND_16         (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00010000 */
+#define RISAF_REGx_ENDR_BADDEND_17         (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00020000 */
+#define RISAF_REGx_ENDR_BADDEND_18         (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00040000 */
+#define RISAF_REGx_ENDR_BADDEND_19         (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00080000 */
+#define RISAF_REGx_ENDR_BADDEND_20         (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00100000 */
+#define RISAF_REGx_ENDR_BADDEND_21         (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00200000 */
+#define RISAF_REGx_ENDR_BADDEND_22         (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00400000 */
+#define RISAF_REGx_ENDR_BADDEND_23         (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00800000 */
+#define RISAF_REGx_ENDR_BADDEND_24         (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x01000000 */
+#define RISAF_REGx_ENDR_BADDEND_25         (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x02000000 */
+#define RISAF_REGx_ENDR_BADDEND_26         (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x04000000 */
+#define RISAF_REGx_ENDR_BADDEND_27         (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x08000000 */
+#define RISAF_REGx_ENDR_BADDEND_28         (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x10000000 */
+#define RISAF_REGx_ENDR_BADDEND_29         (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x20000000 */
+#define RISAF_REGx_ENDR_BADDEND_30         (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x40000000 */
+#define RISAF_REGx_ENDR_BADDEND_31         (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_CIDCFGR register  **************/
+#define RISAF_REGx_CIDCFGR_RDENC0_Pos      (0U)
+#define RISAF_REGx_CIDCFGR_RDENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos)           /*!< 0x00000001 */
+#define RISAF_REGx_CIDCFGR_RDENC0          RISAF_REGx_CIDCFGR_RDENC0_Msk                     /*!< Read enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_RDENC1_Pos      (1U)
+#define RISAF_REGx_CIDCFGR_RDENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos)           /*!< 0x00000002 */
+#define RISAF_REGx_CIDCFGR_RDENC1          RISAF_REGx_CIDCFGR_RDENC1_Msk                     /*!< Read enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_RDENC2_Pos      (2U)
+#define RISAF_REGx_CIDCFGR_RDENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos)           /*!< 0x00000004 */
+#define RISAF_REGx_CIDCFGR_RDENC2          RISAF_REGx_CIDCFGR_RDENC2_Msk                     /*!< Read enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_RDENC3_Pos      (3U)
+#define RISAF_REGx_CIDCFGR_RDENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos)           /*!< 0x00000008 */
+#define RISAF_REGx_CIDCFGR_RDENC3          RISAF_REGx_CIDCFGR_RDENC3_Msk                     /*!< Read enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_RDENC4_Pos      (4U)
+#define RISAF_REGx_CIDCFGR_RDENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_CIDCFGR_RDENC4          RISAF_REGx_CIDCFGR_RDENC4_Msk                     /*!< Read enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_RDENC5_Pos      (5U)
+#define RISAF_REGx_CIDCFGR_RDENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_CIDCFGR_RDENC5          RISAF_REGx_CIDCFGR_RDENC5_Msk                     /*!< Read enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_RDENC6_Pos      (6U)
+#define RISAF_REGx_CIDCFGR_RDENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_CIDCFGR_RDENC6          RISAF_REGx_CIDCFGR_RDENC6_Msk                     /*!< Read enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_RDENC7_Pos      (7U)
+#define RISAF_REGx_CIDCFGR_RDENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_CIDCFGR_RDENC7          RISAF_REGx_CIDCFGR_RDENC7_Msk                     /*!< Read enable for compartment 7 */
+#define RISAF_REGx_CIDCFGR_WRENC0_Pos      (16U)
+#define RISAF_REGx_CIDCFGR_WRENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos)           /*!< 0x00010000 */
+#define RISAF_REGx_CIDCFGR_WRENC0          RISAF_REGx_CIDCFGR_WRENC0_Msk                     /*!< Write enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_WRENC1_Pos      (17U)
+#define RISAF_REGx_CIDCFGR_WRENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos)           /*!< 0x00020000 */
+#define RISAF_REGx_CIDCFGR_WRENC1          RISAF_REGx_CIDCFGR_WRENC1_Msk                     /*!< Write enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_WRENC2_Pos      (18U)
+#define RISAF_REGx_CIDCFGR_WRENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos)           /*!< 0x00040000 */
+#define RISAF_REGx_CIDCFGR_WRENC2          RISAF_REGx_CIDCFGR_WRENC2_Msk                     /*!< Write enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_WRENC3_Pos      (19U)
+#define RISAF_REGx_CIDCFGR_WRENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos)           /*!< 0x00080000 */
+#define RISAF_REGx_CIDCFGR_WRENC3          RISAF_REGx_CIDCFGR_WRENC3_Msk                     /*!< Write enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_WRENC4_Pos      (20U)
+#define RISAF_REGx_CIDCFGR_WRENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos)           /*!< 0x00100000 */
+#define RISAF_REGx_CIDCFGR_WRENC4          RISAF_REGx_CIDCFGR_WRENC4_Msk                     /*!< Write enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_WRENC5_Pos      (21U)
+#define RISAF_REGx_CIDCFGR_WRENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos)           /*!< 0x00200000 */
+#define RISAF_REGx_CIDCFGR_WRENC5          RISAF_REGx_CIDCFGR_WRENC5_Msk                     /*!< Write enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_WRENC6_Pos      (22U)
+#define RISAF_REGx_CIDCFGR_WRENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos)           /*!< 0x00400000 */
+#define RISAF_REGx_CIDCFGR_WRENC6          RISAF_REGx_CIDCFGR_WRENC6_Msk                     /*!< Write enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_WRENC7_Pos      (23U)
+#define RISAF_REGx_CIDCFGR_WRENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos)           /*!< 0x00800000 */
+#define RISAF_REGx_CIDCFGR_WRENC7          RISAF_REGx_CIDCFGR_WRENC7_Msk                     /*!< Write enable for compartment 7 */
+
+/***************  Bit definition for RISAF_REGx_zCFGR register  ***************/
+#define RISAF_REGx_zCFGR_SREN_Pos          (0U)
+#define RISAF_REGx_zCFGR_SREN_Msk          (0x1UL << RISAF_REGx_zCFGR_SREN_Pos)               /*!< 0x00000001 */
+#define RISAF_REGx_zCFGR_SREN              RISAF_REGx_zCFGR_SREN_Msk                         /*!< Subregion enable */
+#define RISAF_REGx_zCFGR_RLOCK_Pos         (1U)
+#define RISAF_REGx_zCFGR_RLOCK_Msk         (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos)              /*!< 0x00000002 */
+#define RISAF_REGx_zCFGR_RLOCK             RISAF_REGx_zCFGR_RLOCK_Msk                        /*!< Resource lock */
+#define RISAF_REGx_zCFGR_SRCID_Pos         (4U)
+#define RISAF_REGx_zCFGR_SRCID_Msk         (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000070 */
+#define RISAF_REGx_zCFGR_SRCID             RISAF_REGx_zCFGR_SRCID_Msk                        /*!< Subregion CID */
+#define RISAF_REGx_zCFGR_SRCID_0           (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000010 */
+#define RISAF_REGx_zCFGR_SRCID_1           (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000020 */
+#define RISAF_REGx_zCFGR_SRCID_2           (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000040 */
+#define RISAF_REGx_zCFGR_SEC_Pos           (8U)
+#define RISAF_REGx_zCFGR_SEC_Msk           (0x1UL << RISAF_REGx_zCFGR_SEC_Pos)                /*!< 0x00000100 */
+#define RISAF_REGx_zCFGR_SEC               RISAF_REGx_zCFGR_SEC_Msk                          /*!< Secure subregion */
+#define RISAF_REGx_zCFGR_PRIV_Pos          (9U)
+#define RISAF_REGx_zCFGR_PRIV_Msk          (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos)               /*!< 0x00000200 */
+#define RISAF_REGx_zCFGR_PRIV              RISAF_REGx_zCFGR_PRIV_Msk                         /*!< Privileged subregion */
+#define RISAF_REGx_zCFGR_RDEN_Pos          (12U)
+#define RISAF_REGx_zCFGR_RDEN_Msk          (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos)               /*!< 0x00001000 */
+#define RISAF_REGx_zCFGR_RDEN              RISAF_REGx_zCFGR_RDEN_Msk                         /*!< Read enable */
+#define RISAF_REGx_zCFGR_WREN_Pos          (13U)
+#define RISAF_REGx_zCFGR_WREN_Msk          (0x1UL << RISAF_REGx_zCFGR_WREN_Pos)               /*!< 0x00002000 */
+#define RISAF_REGx_zCFGR_WREN              RISAF_REGx_zCFGR_WREN_Msk                         /*!< Write enable */
+
+/**************  Bit definition for RISAF_REGx_zSTARTR register  **************/
+#define RISAF_REGx_zSTARTR_SADDSTART_Pos   (0U)
+#define RISAF_REGx_zSTARTR_SADDSTART_Msk   (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zSTARTR_SADDSTART       RISAF_REGx_zSTARTR_SADDSTART_Msk                  /*!< Subregion address start */
+#define RISAF_REGx_zSTARTR_SADDSTART_0     (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000001 */
+#define RISAF_REGx_zSTARTR_SADDSTART_1     (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000002 */
+#define RISAF_REGx_zSTARTR_SADDSTART_2     (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000004 */
+#define RISAF_REGx_zSTARTR_SADDSTART_3     (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000008 */
+#define RISAF_REGx_zSTARTR_SADDSTART_4     (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000010 */
+#define RISAF_REGx_zSTARTR_SADDSTART_5     (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000020 */
+#define RISAF_REGx_zSTARTR_SADDSTART_6     (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000040 */
+#define RISAF_REGx_zSTARTR_SADDSTART_7     (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000080 */
+#define RISAF_REGx_zSTARTR_SADDSTART_8     (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000100 */
+#define RISAF_REGx_zSTARTR_SADDSTART_9     (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000200 */
+#define RISAF_REGx_zSTARTR_SADDSTART_10    (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000400 */
+#define RISAF_REGx_zSTARTR_SADDSTART_11    (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000800 */
+#define RISAF_REGx_zSTARTR_SADDSTART_12    (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00001000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_13    (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00002000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_14    (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00004000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_15    (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00008000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_16    (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00010000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_17    (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00020000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_18    (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00040000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_19    (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00080000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_20    (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00100000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_21    (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00200000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_22    (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00400000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_23    (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00800000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_24    (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x01000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_25    (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x02000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_26    (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x04000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_27    (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x08000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_28    (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_29    (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_30    (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_31    (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_zENDR register  ***************/
+#define RISAF_REGx_zENDR_SADDEND_Pos       (0U)
+#define RISAF_REGx_zENDR_SADDEND_Msk       (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zENDR_SADDEND           RISAF_REGx_zENDR_SADDEND_Msk                      /*!< Subregion address end */
+#define RISAF_REGx_zENDR_SADDEND_0         (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000001 */
+#define RISAF_REGx_zENDR_SADDEND_1         (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000002 */
+#define RISAF_REGx_zENDR_SADDEND_2         (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000004 */
+#define RISAF_REGx_zENDR_SADDEND_3         (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000008 */
+#define RISAF_REGx_zENDR_SADDEND_4         (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_zENDR_SADDEND_5         (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_zENDR_SADDEND_6         (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_zENDR_SADDEND_7         (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_zENDR_SADDEND_8         (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000100 */
+#define RISAF_REGx_zENDR_SADDEND_9         (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000200 */
+#define RISAF_REGx_zENDR_SADDEND_10        (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000400 */
+#define RISAF_REGx_zENDR_SADDEND_11        (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000800 */
+#define RISAF_REGx_zENDR_SADDEND_12        (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00001000 */
+#define RISAF_REGx_zENDR_SADDEND_13        (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00002000 */
+#define RISAF_REGx_zENDR_SADDEND_14        (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00004000 */
+#define RISAF_REGx_zENDR_SADDEND_15        (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00008000 */
+#define RISAF_REGx_zENDR_SADDEND_16        (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00010000 */
+#define RISAF_REGx_zENDR_SADDEND_17        (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00020000 */
+#define RISAF_REGx_zENDR_SADDEND_18        (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00040000 */
+#define RISAF_REGx_zENDR_SADDEND_19        (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00080000 */
+#define RISAF_REGx_zENDR_SADDEND_20        (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00100000 */
+#define RISAF_REGx_zENDR_SADDEND_21        (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00200000 */
+#define RISAF_REGx_zENDR_SADDEND_22        (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00400000 */
+#define RISAF_REGx_zENDR_SADDEND_23        (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00800000 */
+#define RISAF_REGx_zENDR_SADDEND_24        (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x01000000 */
+#define RISAF_REGx_zENDR_SADDEND_25        (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x02000000 */
+#define RISAF_REGx_zENDR_SADDEND_26        (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x04000000 */
+#define RISAF_REGx_zENDR_SADDEND_27        (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x08000000 */
+#define RISAF_REGx_zENDR_SADDEND_28        (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x10000000 */
+#define RISAF_REGx_zENDR_SADDEND_29        (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x20000000 */
+#define RISAF_REGx_zENDR_SADDEND_30        (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x40000000 */
+#define RISAF_REGx_zENDR_SADDEND_31        (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_zNESTR register  ***************/
+#define RISAF_REGx_zNESTR_DCEN_Pos         (2U)
+#define RISAF_REGx_zNESTR_DCEN_Msk         (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos)              /*!< 0x00000004 */
+#define RISAF_REGx_zNESTR_DCEN             RISAF_REGx_zNESTR_DCEN_Msk                        /*!< Delegated configuration enable */
+#define RISAF_REGx_zNESTR_DCCID_Pos        (4U)
+#define RISAF_REGx_zNESTR_DCCID_Msk        (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000070 */
+#define RISAF_REGx_zNESTR_DCCID            RISAF_REGx_zNESTR_DCCID_Msk                       /*!< Delegated configuration CID */
+#define RISAF_REGx_zNESTR_DCCID_0          (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000010 */
+#define RISAF_REGx_zNESTR_DCCID_1          (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000020 */
+#define RISAF_REGx_zNESTR_DCCID_2          (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000040 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (IAC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IAC_IER0 register  *******************/
+#define IAC_IERx_IAIE0_Pos         (0U)
+#define IAC_IERx_IAIE0_Msk         (0x1UL << IAC_IERx_IAIE0_Pos)        /*!< 0x00000001 */
+#define IAC_IERx_IAIE0             IAC_IERx_IAIE0_Msk                  /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_IERx_IAIE1_Pos         (1U)
+#define IAC_IERx_IAIE1_Msk         (0x1UL << IAC_IERx_IAIE1_Pos)        /*!< 0x00000002 */
+#define IAC_IERx_IAIE1             IAC_IERx_IAIE1_Msk                  /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_IERx_IAIE2_Pos         (2U)
+#define IAC_IERx_IAIE2_Msk         (0x1UL << IAC_IERx_IAIE2_Pos)        /*!< 0x00000004 */
+#define IAC_IERx_IAIE2             IAC_IERx_IAIE2_Msk                  /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_IERx_IAIE3_Pos         (3U)
+#define IAC_IERx_IAIE3_Msk         (0x1UL << IAC_IERx_IAIE3_Pos)        /*!< 0x00000008 */
+#define IAC_IERx_IAIE3             IAC_IERx_IAIE3_Msk                  /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_IERx_IAIE4_Pos         (4U)
+#define IAC_IERx_IAIE4_Msk         (0x1UL << IAC_IERx_IAIE4_Pos)        /*!< 0x00000010 */
+#define IAC_IERx_IAIE4             IAC_IERx_IAIE4_Msk                  /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_IERx_IAIE5_Pos         (5U)
+#define IAC_IERx_IAIE5_Msk         (0x1UL << IAC_IERx_IAIE5_Pos)        /*!< 0x00000020 */
+#define IAC_IERx_IAIE5             IAC_IERx_IAIE5_Msk                  /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_IERx_IAIE6_Pos         (6U)
+#define IAC_IERx_IAIE6_Msk         (0x1UL << IAC_IERx_IAIE6_Pos)        /*!< 0x00000040 */
+#define IAC_IERx_IAIE6             IAC_IERx_IAIE6_Msk                  /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_IERx_IAIE7_Pos         (7U)
+#define IAC_IERx_IAIE7_Msk         (0x1UL << IAC_IERx_IAIE7_Pos)        /*!< 0x00000080 */
+#define IAC_IERx_IAIE7             IAC_IERx_IAIE7_Msk                  /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_IERx_IAIE8_Pos         (8U)
+#define IAC_IERx_IAIE8_Msk         (0x1UL << IAC_IERx_IAIE8_Pos)        /*!< 0x00000100 */
+#define IAC_IERx_IAIE8             IAC_IERx_IAIE8_Msk                  /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_IERx_IAIE9_Pos         (9U)
+#define IAC_IERx_IAIE9_Msk         (0x1UL << IAC_IERx_IAIE9_Pos)        /*!< 0x00000200 */
+#define IAC_IERx_IAIE9             IAC_IERx_IAIE9_Msk                  /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_IERx_IAIE10_Pos        (10U)
+#define IAC_IERx_IAIE10_Msk        (0x1UL << IAC_IERx_IAIE10_Pos)       /*!< 0x00000400 */
+#define IAC_IERx_IAIE10            IAC_IERx_IAIE10_Msk                 /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_IERx_IAIE11_Pos        (11U)
+#define IAC_IERx_IAIE11_Msk        (0x1UL << IAC_IERx_IAIE11_Pos)       /*!< 0x00000800 */
+#define IAC_IERx_IAIE11            IAC_IERx_IAIE11_Msk                 /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_IERx_IAIE12_Pos        (12U)
+#define IAC_IERx_IAIE12_Msk        (0x1UL << IAC_IERx_IAIE12_Pos)       /*!< 0x00001000 */
+#define IAC_IERx_IAIE12            IAC_IERx_IAIE12_Msk                 /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_IERx_IAIE13_Pos        (13U)
+#define IAC_IERx_IAIE13_Msk        (0x1UL << IAC_IERx_IAIE13_Pos)       /*!< 0x00002000 */
+#define IAC_IERx_IAIE13            IAC_IERx_IAIE13_Msk                 /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_IERx_IAIE14_Pos        (14U)
+#define IAC_IERx_IAIE14_Msk        (0x1UL << IAC_IERx_IAIE14_Pos)       /*!< 0x00004000 */
+#define IAC_IERx_IAIE14            IAC_IERx_IAIE14_Msk                 /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_IERx_IAIE15_Pos        (15U)
+#define IAC_IERx_IAIE15_Msk        (0x1UL << IAC_IERx_IAIE15_Pos)       /*!< 0x00008000 */
+#define IAC_IERx_IAIE15            IAC_IERx_IAIE15_Msk                 /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_IERx_IAIE16_Pos        (16U)
+#define IAC_IERx_IAIE16_Msk        (0x1UL << IAC_IERx_IAIE16_Pos)       /*!< 0x00010000 */
+#define IAC_IERx_IAIE16            IAC_IERx_IAIE16_Msk                 /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_IERx_IAIE17_Pos        (17U)
+#define IAC_IERx_IAIE17_Msk        (0x1UL << IAC_IERx_IAIE17_Pos)       /*!< 0x00020000 */
+#define IAC_IERx_IAIE17            IAC_IERx_IAIE17_Msk                 /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_IERx_IAIE18_Pos        (18U)
+#define IAC_IERx_IAIE18_Msk        (0x1UL << IAC_IERx_IAIE18_Pos)       /*!< 0x00040000 */
+#define IAC_IERx_IAIE18            IAC_IERx_IAIE18_Msk                 /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_IERx_IAIE19_Pos        (19U)
+#define IAC_IERx_IAIE19_Msk        (0x1UL << IAC_IERx_IAIE19_Pos)       /*!< 0x00080000 */
+#define IAC_IERx_IAIE19            IAC_IERx_IAIE19_Msk                 /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_IERx_IAIE20_Pos        (20U)
+#define IAC_IERx_IAIE20_Msk        (0x1UL << IAC_IERx_IAIE20_Pos)       /*!< 0x00100000 */
+#define IAC_IERx_IAIE20            IAC_IERx_IAIE20_Msk                 /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_IERx_IAIE21_Pos        (21U)
+#define IAC_IERx_IAIE21_Msk        (0x1UL << IAC_IERx_IAIE21_Pos)       /*!< 0x00200000 */
+#define IAC_IERx_IAIE21            IAC_IERx_IAIE21_Msk                 /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_IERx_IAIE22_Pos        (22U)
+#define IAC_IERx_IAIE22_Msk        (0x1UL << IAC_IERx_IAIE22_Pos)       /*!< 0x00400000 */
+#define IAC_IERx_IAIE22            IAC_IERx_IAIE22_Msk                 /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_IERx_IAIE23_Pos        (23U)
+#define IAC_IERx_IAIE23_Msk        (0x1UL << IAC_IERx_IAIE23_Pos)       /*!< 0x00800000 */
+#define IAC_IERx_IAIE23            IAC_IERx_IAIE23_Msk                 /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_IERx_IAIE24_Pos        (24U)
+#define IAC_IERx_IAIE24_Msk        (0x1UL << IAC_IERx_IAIE24_Pos)       /*!< 0x01000000 */
+#define IAC_IERx_IAIE24            IAC_IERx_IAIE24_Msk                 /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_IERx_IAIE25_Pos        (25U)
+#define IAC_IERx_IAIE25_Msk        (0x1UL << IAC_IERx_IAIE25_Pos)       /*!< 0x02000000 */
+#define IAC_IERx_IAIE25            IAC_IERx_IAIE25_Msk                 /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_IERx_IAIE26_Pos        (26U)
+#define IAC_IERx_IAIE26_Msk        (0x1UL << IAC_IERx_IAIE26_Pos)       /*!< 0x04000000 */
+#define IAC_IERx_IAIE26            IAC_IERx_IAIE26_Msk                 /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_IERx_IAIE27_Pos        (27U)
+#define IAC_IERx_IAIE27_Msk        (0x1UL << IAC_IERx_IAIE27_Pos)       /*!< 0x08000000 */
+#define IAC_IERx_IAIE27            IAC_IERx_IAIE27_Msk                 /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_IERx_IAIE28_Pos        (28U)
+#define IAC_IERx_IAIE28_Msk        (0x1UL << IAC_IERx_IAIE28_Pos)       /*!< 0x10000000 */
+#define IAC_IERx_IAIE28            IAC_IERx_IAIE28_Msk                 /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_IERx_IAIE29_Pos        (29U)
+#define IAC_IERx_IAIE29_Msk        (0x1UL << IAC_IERx_IAIE29_Pos)       /*!< 0x20000000 */
+#define IAC_IERx_IAIE29            IAC_IERx_IAIE29_Msk                 /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_IERx_IAIE30_Pos        (30U)
+#define IAC_IERx_IAIE30_Msk        (0x1UL << IAC_IERx_IAIE30_Pos)       /*!< 0x40000000 */
+#define IAC_IERx_IAIE30            IAC_IERx_IAIE30_Msk                 /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_IERx_IAIE31_Pos        (31U)
+#define IAC_IERx_IAIE31_Msk        (0x1UL << IAC_IERx_IAIE31_Pos)       /*!< 0x80000000 */
+#define IAC_IERx_IAIE31            IAC_IERx_IAIE31_Msk                 /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ISRx register  *******************/
+#define IAC_ISRx_IAF0_Pos          (0U)
+#define IAC_ISRx_IAF0_Msk          (0x1UL << IAC_ISRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ISRx_IAF0              IAC_ISRx_IAF0_Msk                   /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_ISRx_IAF1_Pos          (1U)
+#define IAC_ISRx_IAF1_Msk          (0x1UL << IAC_ISRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ISRx_IAF1              IAC_ISRx_IAF1_Msk                   /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_ISRx_IAF2_Pos          (2U)
+#define IAC_ISRx_IAF2_Msk          (0x1UL << IAC_ISRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ISRx_IAF2              IAC_ISRx_IAF2_Msk                   /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_ISRx_IAF3_Pos          (3U)
+#define IAC_ISRx_IAF3_Msk          (0x1UL << IAC_ISRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ISRx_IAF3              IAC_ISRx_IAF3_Msk                   /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_ISRx_IAF4_Pos          (4U)
+#define IAC_ISRx_IAF4_Msk          (0x1UL << IAC_ISRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ISRx_IAF4              IAC_ISRx_IAF4_Msk                   /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_ISRx_IAF5_Pos          (5U)
+#define IAC_ISRx_IAF5_Msk          (0x1UL << IAC_ISRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ISRx_IAF5              IAC_ISRx_IAF5_Msk                   /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_ISRx_IAF6_Pos          (6U)
+#define IAC_ISRx_IAF6_Msk          (0x1UL << IAC_ISRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ISRx_IAF6              IAC_ISRx_IAF6_Msk                   /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_ISRx_IAF7_Pos          (7U)
+#define IAC_ISRx_IAF7_Msk          (0x1UL << IAC_ISRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ISRx_IAF7              IAC_ISRx_IAF7_Msk                   /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_ISRx_IAF8_Pos          (8U)
+#define IAC_ISRx_IAF8_Msk          (0x1UL << IAC_ISRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ISRx_IAF8              IAC_ISRx_IAF8_Msk                   /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_ISRx_IAF9_Pos          (9U)
+#define IAC_ISRx_IAF9_Msk          (0x1UL << IAC_ISRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ISRx_IAF9              IAC_ISRx_IAF9_Msk                   /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_ISRx_IAF10_Pos         (10U)
+#define IAC_ISRx_IAF10_Msk         (0x1UL << IAC_ISRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ISRx_IAF10             IAC_ISRx_IAF10_Msk                  /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_ISRx_IAF11_Pos         (11U)
+#define IAC_ISRx_IAF11_Msk         (0x1UL << IAC_ISRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ISRx_IAF11             IAC_ISRx_IAF11_Msk                  /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_ISRx_IAF12_Pos         (12U)
+#define IAC_ISRx_IAF12_Msk         (0x1UL << IAC_ISRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ISRx_IAF12             IAC_ISRx_IAF12_Msk                  /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_ISRx_IAF13_Pos         (13U)
+#define IAC_ISRx_IAF13_Msk         (0x1UL << IAC_ISRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ISRx_IAF13             IAC_ISRx_IAF13_Msk                  /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_ISRx_IAF14_Pos         (14U)
+#define IAC_ISRx_IAF14_Msk         (0x1UL << IAC_ISRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ISRx_IAF14             IAC_ISRx_IAF14_Msk                  /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_ISRx_IAF15_Pos         (15U)
+#define IAC_ISRx_IAF15_Msk         (0x1UL << IAC_ISRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ISRx_IAF15             IAC_ISRx_IAF15_Msk                  /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_ISRx_IAF16_Pos         (16U)
+#define IAC_ISRx_IAF16_Msk         (0x1UL << IAC_ISRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ISRx_IAF16             IAC_ISRx_IAF16_Msk                  /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_ISRx_IAF17_Pos         (17U)
+#define IAC_ISRx_IAF17_Msk         (0x1UL << IAC_ISRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ISRx_IAF17             IAC_ISRx_IAF17_Msk                  /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_ISRx_IAF18_Pos         (18U)
+#define IAC_ISRx_IAF18_Msk         (0x1UL << IAC_ISRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ISRx_IAF18             IAC_ISRx_IAF18_Msk                  /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_ISRx_IAF19_Pos         (19U)
+#define IAC_ISRx_IAF19_Msk         (0x1UL << IAC_ISRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ISRx_IAF19             IAC_ISRx_IAF19_Msk                  /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_ISRx_IAF20_Pos         (20U)
+#define IAC_ISRx_IAF20_Msk         (0x1UL << IAC_ISRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ISRx_IAF20             IAC_ISRx_IAF20_Msk                  /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_ISRx_IAF21_Pos         (21U)
+#define IAC_ISRx_IAF21_Msk         (0x1UL << IAC_ISRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ISRx_IAF21             IAC_ISRx_IAF21_Msk                  /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_ISRx_IAF22_Pos         (22U)
+#define IAC_ISRx_IAF22_Msk         (0x1UL << IAC_ISRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ISRx_IAF22             IAC_ISRx_IAF22_Msk                  /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_ISRx_IAF23_Pos         (23U)
+#define IAC_ISRx_IAF23_Msk         (0x1UL << IAC_ISRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ISRx_IAF23             IAC_ISRx_IAF23_Msk                  /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_ISRx_IAF24_Pos         (24U)
+#define IAC_ISRx_IAF24_Msk         (0x1UL << IAC_ISRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ISRx_IAF24             IAC_ISRx_IAF24_Msk                  /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_ISRx_IAF25_Pos         (25U)
+#define IAC_ISRx_IAF25_Msk         (0x1UL << IAC_ISRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ISRx_IAF25             IAC_ISRx_IAF25_Msk                  /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_ISRx_IAF26_Pos         (26U)
+#define IAC_ISRx_IAF26_Msk         (0x1UL << IAC_ISRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ISRx_IAF26             IAC_ISRx_IAF26_Msk                  /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_ISRx_IAF27_Pos         (27U)
+#define IAC_ISRx_IAF27_Msk         (0x1UL << IAC_ISRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ISRx_IAF27             IAC_ISRx_IAF27_Msk                  /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_ISRx_IAF28_Pos         (28U)
+#define IAC_ISRx_IAF28_Msk         (0x1UL << IAC_ISRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ISRx_IAF28             IAC_ISRx_IAF28_Msk                  /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_ISRx_IAF29_Pos         (29U)
+#define IAC_ISRx_IAF29_Msk         (0x1UL << IAC_ISRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ISRx_IAF29             IAC_ISRx_IAF29_Msk                  /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_ISRx_IAF30_Pos         (30U)
+#define IAC_ISRx_IAF30_Msk         (0x1UL << IAC_ISRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ISRx_IAF30             IAC_ISRx_IAF30_Msk                  /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_ISRx_IAF31_Pos         (31U)
+#define IAC_ISRx_IAF31_Msk         (0x1UL << IAC_ISRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ISRx_IAF31             IAC_ISRx_IAF31_Msk                  /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ICRx register  *******************/
+#define IAC_ICRx_IAF0_Pos          (0U)
+#define IAC_ICRx_IAF0_Msk          (0x1UL << IAC_ICRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ICRx_IAF0              IAC_ICRx_IAF0_Msk                   /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */
+#define IAC_ICRx_IAF1_Pos          (1U)
+#define IAC_ICRx_IAF1_Msk          (0x1UL << IAC_ICRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ICRx_IAF1              IAC_ICRx_IAF1_Msk                   /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */
+#define IAC_ICRx_IAF2_Pos          (2U)
+#define IAC_ICRx_IAF2_Msk          (0x1UL << IAC_ICRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ICRx_IAF2              IAC_ICRx_IAF2_Msk                   /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */
+#define IAC_ICRx_IAF3_Pos          (3U)
+#define IAC_ICRx_IAF3_Msk          (0x1UL << IAC_ICRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ICRx_IAF3              IAC_ICRx_IAF3_Msk                   /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */
+#define IAC_ICRx_IAF4_Pos          (4U)
+#define IAC_ICRx_IAF4_Msk          (0x1UL << IAC_ICRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ICRx_IAF4              IAC_ICRx_IAF4_Msk                   /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */
+#define IAC_ICRx_IAF5_Pos          (5U)
+#define IAC_ICRx_IAF5_Msk          (0x1UL << IAC_ICRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ICRx_IAF5              IAC_ICRx_IAF5_Msk                   /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */
+#define IAC_ICRx_IAF6_Pos          (6U)
+#define IAC_ICRx_IAF6_Msk          (0x1UL << IAC_ICRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ICRx_IAF6              IAC_ICRx_IAF6_Msk                   /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */
+#define IAC_ICRx_IAF7_Pos          (7U)
+#define IAC_ICRx_IAF7_Msk          (0x1UL << IAC_ICRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ICRx_IAF7              IAC_ICRx_IAF7_Msk                   /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */
+#define IAC_ICRx_IAF8_Pos          (8U)
+#define IAC_ICRx_IAF8_Msk          (0x1UL << IAC_ICRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ICRx_IAF8              IAC_ICRx_IAF8_Msk                   /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */
+#define IAC_ICRx_IAF9_Pos          (9U)
+#define IAC_ICRx_IAF9_Msk          (0x1UL << IAC_ICRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ICRx_IAF9              IAC_ICRx_IAF9_Msk                   /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */
+#define IAC_ICRx_IAF10_Pos         (10U)
+#define IAC_ICRx_IAF10_Msk         (0x1UL << IAC_ICRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ICRx_IAF10             IAC_ICRx_IAF10_Msk                  /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */
+#define IAC_ICRx_IAF11_Pos         (11U)
+#define IAC_ICRx_IAF11_Msk         (0x1UL << IAC_ICRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ICRx_IAF11             IAC_ICRx_IAF11_Msk                  /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */
+#define IAC_ICRx_IAF12_Pos         (12U)
+#define IAC_ICRx_IAF12_Msk         (0x1UL << IAC_ICRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ICRx_IAF12             IAC_ICRx_IAF12_Msk                  /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */
+#define IAC_ICRx_IAF13_Pos         (13U)
+#define IAC_ICRx_IAF13_Msk         (0x1UL << IAC_ICRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ICRx_IAF13             IAC_ICRx_IAF13_Msk                  /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */
+#define IAC_ICRx_IAF14_Pos         (14U)
+#define IAC_ICRx_IAF14_Msk         (0x1UL << IAC_ICRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ICRx_IAF14             IAC_ICRx_IAF14_Msk                  /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */
+#define IAC_ICRx_IAF15_Pos         (15U)
+#define IAC_ICRx_IAF15_Msk         (0x1UL << IAC_ICRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ICRx_IAF15             IAC_ICRx_IAF15_Msk                  /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */
+#define IAC_ICRx_IAF16_Pos         (16U)
+#define IAC_ICRx_IAF16_Msk         (0x1UL << IAC_ICRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ICRx_IAF16             IAC_ICRx_IAF16_Msk                  /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */
+#define IAC_ICRx_IAF17_Pos         (17U)
+#define IAC_ICRx_IAF17_Msk         (0x1UL << IAC_ICRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ICRx_IAF17             IAC_ICRx_IAF17_Msk                  /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */
+#define IAC_ICRx_IAF18_Pos         (18U)
+#define IAC_ICRx_IAF18_Msk         (0x1UL << IAC_ICRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ICRx_IAF18             IAC_ICRx_IAF18_Msk                  /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */
+#define IAC_ICRx_IAF19_Pos         (19U)
+#define IAC_ICRx_IAF19_Msk         (0x1UL << IAC_ICRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ICRx_IAF19             IAC_ICRx_IAF19_Msk                  /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */
+#define IAC_ICRx_IAF20_Pos         (20U)
+#define IAC_ICRx_IAF20_Msk         (0x1UL << IAC_ICRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ICRx_IAF20             IAC_ICRx_IAF20_Msk                  /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */
+#define IAC_ICRx_IAF21_Pos         (21U)
+#define IAC_ICRx_IAF21_Msk         (0x1UL << IAC_ICRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ICRx_IAF21             IAC_ICRx_IAF21_Msk                  /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */
+#define IAC_ICRx_IAF22_Pos         (22U)
+#define IAC_ICRx_IAF22_Msk         (0x1UL << IAC_ICRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ICRx_IAF22             IAC_ICRx_IAF22_Msk                  /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */
+#define IAC_ICRx_IAF23_Pos         (23U)
+#define IAC_ICRx_IAF23_Msk         (0x1UL << IAC_ICRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ICRx_IAF23             IAC_ICRx_IAF23_Msk                  /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */
+#define IAC_ICRx_IAF24_Pos         (24U)
+#define IAC_ICRx_IAF24_Msk         (0x1UL << IAC_ICRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ICRx_IAF24             IAC_ICRx_IAF24_Msk                  /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */
+#define IAC_ICRx_IAF25_Pos         (25U)
+#define IAC_ICRx_IAF25_Msk         (0x1UL << IAC_ICRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ICRx_IAF25             IAC_ICRx_IAF25_Msk                  /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */
+#define IAC_ICRx_IAF26_Pos         (26U)
+#define IAC_ICRx_IAF26_Msk         (0x1UL << IAC_ICRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ICRx_IAF26             IAC_ICRx_IAF26_Msk                  /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */
+#define IAC_ICRx_IAF27_Pos         (27U)
+#define IAC_ICRx_IAF27_Msk         (0x1UL << IAC_ICRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ICRx_IAF27             IAC_ICRx_IAF27_Msk                  /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */
+#define IAC_ICRx_IAF28_Pos         (28U)
+#define IAC_ICRx_IAF28_Msk         (0x1UL << IAC_ICRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ICRx_IAF28             IAC_ICRx_IAF28_Msk                  /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */
+#define IAC_ICRx_IAF29_Pos         (29U)
+#define IAC_ICRx_IAF29_Msk         (0x1UL << IAC_ICRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ICRx_IAF29             IAC_ICRx_IAF29_Msk                  /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */
+#define IAC_ICRx_IAF30_Pos         (30U)
+#define IAC_ICRx_IAF30_Msk         (0x1UL << IAC_ICRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ICRx_IAF30             IAC_ICRx_IAF30_Msk                  /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */
+#define IAC_ICRx_IAF31_Pos         (31U)
+#define IAC_ICRx_IAF31_Msk         (0x1UL << IAC_ICRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ICRx_IAF31             IAC_ICRx_IAF31_Msk                  /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */
+
+/******************  Bit definition for IAC_IISRx register  *******************/
+#define IAC_IISRx_ILACIN0_Pos      (0U)
+#define IAC_IISRx_ILACIN0_Msk      (0x1UL << IAC_IISRx_ILACIN0_Pos)     /*!< 0x00000001 */
+#define IAC_IISRx_ILACIN0          IAC_IISRx_ILACIN0_Msk               /*!< illegal access input 0 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN1_Pos      (1U)
+#define IAC_IISRx_ILACIN1_Msk      (0x1UL << IAC_IISRx_ILACIN1_Pos)     /*!< 0x00000002 */
+#define IAC_IISRx_ILACIN1          IAC_IISRx_ILACIN1_Msk               /*!< illegal access input 1 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN2_Pos      (2U)
+#define IAC_IISRx_ILACIN2_Msk      (0x1UL << IAC_IISRx_ILACIN2_Pos)     /*!< 0x00000004 */
+#define IAC_IISRx_ILACIN2          IAC_IISRx_ILACIN2_Msk               /*!< illegal access input 2 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN3_Pos      (3U)
+#define IAC_IISRx_ILACIN3_Msk      (0x1UL << IAC_IISRx_ILACIN3_Pos)     /*!< 0x00000008 */
+#define IAC_IISRx_ILACIN3          IAC_IISRx_ILACIN3_Msk               /*!< illegal access input 3 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN4_Pos      (4U)
+#define IAC_IISRx_ILACIN4_Msk      (0x1UL << IAC_IISRx_ILACIN4_Pos)     /*!< 0x00000010 */
+#define IAC_IISRx_ILACIN4          IAC_IISRx_ILACIN4_Msk               /*!< illegal access input 4 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN5_Pos      (5U)
+#define IAC_IISRx_ILACIN5_Msk      (0x1UL << IAC_IISRx_ILACIN5_Pos)     /*!< 0x00000020 */
+#define IAC_IISRx_ILACIN5          IAC_IISRx_ILACIN5_Msk               /*!< illegal access input 5 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN6_Pos      (6U)
+#define IAC_IISRx_ILACIN6_Msk      (0x1UL << IAC_IISRx_ILACIN6_Pos)     /*!< 0x00000040 */
+#define IAC_IISRx_ILACIN6          IAC_IISRx_ILACIN6_Msk               /*!< illegal access input 6 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN7_Pos      (7U)
+#define IAC_IISRx_ILACIN7_Msk      (0x1UL << IAC_IISRx_ILACIN7_Pos)     /*!< 0x00000080 */
+#define IAC_IISRx_ILACIN7          IAC_IISRx_ILACIN7_Msk               /*!< illegal access input 7 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN8_Pos      (8U)
+#define IAC_IISRx_ILACIN8_Msk      (0x1UL << IAC_IISRx_ILACIN8_Pos)     /*!< 0x00000100 */
+#define IAC_IISRx_ILACIN8          IAC_IISRx_ILACIN8_Msk               /*!< illegal access input 8 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN9_Pos      (9U)
+#define IAC_IISRx_ILACIN9_Msk      (0x1UL << IAC_IISRx_ILACIN9_Pos)     /*!< 0x00000200 */
+#define IAC_IISRx_ILACIN9          IAC_IISRx_ILACIN9_Msk               /*!< illegal access input 9 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN10_Pos     (10U)
+#define IAC_IISRx_ILACIN10_Msk     (0x1UL << IAC_IISRx_ILACIN10_Pos)    /*!< 0x00000400 */
+#define IAC_IISRx_ILACIN10         IAC_IISRx_ILACIN10_Msk              /*!< illegal access input 10 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN11_Pos     (11U)
+#define IAC_IISRx_ILACIN11_Msk     (0x1UL << IAC_IISRx_ILACIN11_Pos)    /*!< 0x00000800 */
+#define IAC_IISRx_ILACIN11         IAC_IISRx_ILACIN11_Msk              /*!< illegal access input 11 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN12_Pos     (12U)
+#define IAC_IISRx_ILACIN12_Msk     (0x1UL << IAC_IISRx_ILACIN12_Pos)    /*!< 0x00001000 */
+#define IAC_IISRx_ILACIN12         IAC_IISRx_ILACIN12_Msk              /*!< illegal access input 12 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN13_Pos     (13U)
+#define IAC_IISRx_ILACIN13_Msk     (0x1UL << IAC_IISRx_ILACIN13_Pos)    /*!< 0x00002000 */
+#define IAC_IISRx_ILACIN13         IAC_IISRx_ILACIN13_Msk              /*!< illegal access input 13 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN14_Pos     (14U)
+#define IAC_IISRx_ILACIN14_Msk     (0x1UL << IAC_IISRx_ILACIN14_Pos)    /*!< 0x00004000 */
+#define IAC_IISRx_ILACIN14         IAC_IISRx_ILACIN14_Msk              /*!< illegal access input 14 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN15_Pos     (15U)
+#define IAC_IISRx_ILACIN15_Msk     (0x1UL << IAC_IISRx_ILACIN15_Pos)    /*!< 0x00008000 */
+#define IAC_IISRx_ILACIN15         IAC_IISRx_ILACIN15_Msk              /*!< illegal access input 15 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN16_Pos     (16U)
+#define IAC_IISRx_ILACIN16_Msk     (0x1UL << IAC_IISRx_ILACIN16_Pos)    /*!< 0x00010000 */
+#define IAC_IISRx_ILACIN16         IAC_IISRx_ILACIN16_Msk              /*!< illegal access input 16 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN17_Pos     (17U)
+#define IAC_IISRx_ILACIN17_Msk     (0x1UL << IAC_IISRx_ILACIN17_Pos)    /*!< 0x00020000 */
+#define IAC_IISRx_ILACIN17         IAC_IISRx_ILACIN17_Msk              /*!< illegal access input 17 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN18_Pos     (18U)
+#define IAC_IISRx_ILACIN18_Msk     (0x1UL << IAC_IISRx_ILACIN18_Pos)    /*!< 0x00040000 */
+#define IAC_IISRx_ILACIN18         IAC_IISRx_ILACIN18_Msk              /*!< illegal access input 18 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN19_Pos     (19U)
+#define IAC_IISRx_ILACIN19_Msk     (0x1UL << IAC_IISRx_ILACIN19_Pos)    /*!< 0x00080000 */
+#define IAC_IISRx_ILACIN19         IAC_IISRx_ILACIN19_Msk              /*!< illegal access input 19 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN20_Pos     (20U)
+#define IAC_IISRx_ILACIN20_Msk     (0x1UL << IAC_IISRx_ILACIN20_Pos)    /*!< 0x00100000 */
+#define IAC_IISRx_ILACIN20         IAC_IISRx_ILACIN20_Msk              /*!< illegal access input 20 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN21_Pos     (21U)
+#define IAC_IISRx_ILACIN21_Msk     (0x1UL << IAC_IISRx_ILACIN21_Pos)    /*!< 0x00200000 */
+#define IAC_IISRx_ILACIN21         IAC_IISRx_ILACIN21_Msk              /*!< illegal access input 21 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN22_Pos     (22U)
+#define IAC_IISRx_ILACIN22_Msk     (0x1UL << IAC_IISRx_ILACIN22_Pos)    /*!< 0x00400000 */
+#define IAC_IISRx_ILACIN22         IAC_IISRx_ILACIN22_Msk              /*!< illegal access input 22 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN23_Pos     (23U)
+#define IAC_IISRx_ILACIN23_Msk     (0x1UL << IAC_IISRx_ILACIN23_Pos)    /*!< 0x00800000 */
+#define IAC_IISRx_ILACIN23         IAC_IISRx_ILACIN23_Msk              /*!< illegal access input 23 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN24_Pos     (24U)
+#define IAC_IISRx_ILACIN24_Msk     (0x1UL << IAC_IISRx_ILACIN24_Pos)    /*!< 0x01000000 */
+#define IAC_IISRx_ILACIN24         IAC_IISRx_ILACIN24_Msk              /*!< illegal access input 24 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN25_Pos     (25U)
+#define IAC_IISRx_ILACIN25_Msk     (0x1UL << IAC_IISRx_ILACIN25_Pos)    /*!< 0x02000000 */
+#define IAC_IISRx_ILACIN25         IAC_IISRx_ILACIN25_Msk              /*!< illegal access input 25 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN26_Pos     (26U)
+#define IAC_IISRx_ILACIN26_Msk     (0x1UL << IAC_IISRx_ILACIN26_Pos)    /*!< 0x04000000 */
+#define IAC_IISRx_ILACIN26         IAC_IISRx_ILACIN26_Msk              /*!< illegal access input 26 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN27_Pos     (27U)
+#define IAC_IISRx_ILACIN27_Msk     (0x1UL << IAC_IISRx_ILACIN27_Pos)    /*!< 0x08000000 */
+#define IAC_IISRx_ILACIN27         IAC_IISRx_ILACIN27_Msk              /*!< illegal access input 27 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN28_Pos     (28U)
+#define IAC_IISRx_ILACIN28_Msk     (0x1UL << IAC_IISRx_ILACIN28_Pos)    /*!< 0x10000000 */
+#define IAC_IISRx_ILACIN28         IAC_IISRx_ILACIN28_Msk              /*!< illegal access input 28 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN29_Pos     (29U)
+#define IAC_IISRx_ILACIN29_Msk     (0x1UL << IAC_IISRx_ILACIN29_Pos)    /*!< 0x20000000 */
+#define IAC_IISRx_ILACIN29         IAC_IISRx_ILACIN29_Msk              /*!< illegal access input 29 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN30_Pos     (30U)
+#define IAC_IISRx_ILACIN30_Msk     (0x1UL << IAC_IISRx_ILACIN30_Pos)    /*!< 0x40000000 */
+#define IAC_IISRx_ILACIN30         IAC_IISRx_ILACIN30_Msk              /*!< illegal access input 30 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN31_Pos     (31U)
+#define IAC_IISRx_ILACIN31_Msk     (0x1UL << IAC_IISRx_ILACIN31_Pos)    /*!< 0x80000000 */
+#define IAC_IISRx_ILACIN31         IAC_IISRx_ILACIN31_Msk              /*!< illegal access input 31 (i = 0 to 31) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos                    (2U)
+#define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
+#define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos                       (3U)
+#define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
+#define RNG_CR_IE                           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos                      (5U)
+#define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
+#define RNG_CR_CED                          RNG_CR_CED_Msk
+#define RNG_CR_ARDIS_Pos                    (7U)
+#define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
+#define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
+#define RNG_CR_RNG_CONFIG3_Pos              (8U)
+#define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
+#define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
+#define RNG_CR_NISTC_Pos                    (12U)
+#define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
+#define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
+#define RNG_CR_RNG_CONFIG2_Pos              (13U)
+#define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
+#define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
+#define RNG_CR_CLKDIV_Pos                   (16U)
+#define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
+#define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
+#define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
+#define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
+#define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
+#define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
+#define RNG_CR_RNG_CONFIG1_Pos              (20U)
+#define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
+#define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
+#define RNG_CR_CONDRST_Pos                  (30U)
+#define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
+#define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
+#define RNG_CR_CONFIGLOCK_Pos               (31U)
+#define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
+#define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos                     (0U)
+#define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
+#define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos                     (1U)
+#define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
+#define RNG_SR_CECS                         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos                     (2U)
+#define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
+#define RNG_SR_SECS                         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos                     (5U)
+#define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
+#define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos                     (6U)
+#define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
+#define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
+
+/********************  Bits definition for RNG_HTCR register  *******************/
+#define RNG_HTCR_HTCFG_Pos                  (0U)
+#define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
+#define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU_Pos                       (0U)
+#define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                           RTC_TR_SU_Msk
+#define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
+#define RTC_TR_ST_Pos                       (4U)
+#define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                           RTC_TR_ST_Msk
+#define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TR_MNU_Pos                      (8U)
+#define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                          RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TR_MNT_Pos                      (12U)
+#define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                          RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TR_HU_Pos                       (16U)
+#define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                           RTC_TR_HU_Msk
+#define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TR_HT_Pos                       (20U)
+#define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                           RTC_TR_HT_Msk
+#define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TR_PM_Pos                       (22U)
+#define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                           RTC_TR_PM_Msk
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU_Pos                       (0U)
+#define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                           RTC_DR_DU_Msk
+#define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
+#define RTC_DR_DT_Pos                       (4U)
+#define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                           RTC_DR_DT_Msk
+#define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_DR_MU_Pos                       (8U)
+#define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                           RTC_DR_MU_Msk
+#define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_DR_MT_Pos                       (12U)
+#define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                           RTC_DR_MT_Msk
+#define RTC_DR_WDU_Pos                      (13U)
+#define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                          RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_DR_YU_Pos                       (16U)
+#define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                           RTC_DR_YU_Msk
+#define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
+#define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
+#define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
+#define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
+#define RTC_DR_YT_Pos                       (20U)
+#define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                           RTC_DR_YT_Msk
+#define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
+#define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
+#define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
+#define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                      (0U)
+#define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_SSR_SS                          RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_ICSR register  ******************/
+#define RTC_ICSR_WUTWF_Pos                  (2U)
+#define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
+#define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
+#define RTC_ICSR_SHPF_Pos                   (3U)
+#define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
+#define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
+#define RTC_ICSR_INITS_Pos                  (4U)
+#define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
+#define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
+#define RTC_ICSR_RSF_Pos                    (5U)
+#define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
+#define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
+#define RTC_ICSR_INITF_Pos                  (6U)
+#define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
+#define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
+#define RTC_ICSR_INIT_Pos                   (7U)
+#define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
+#define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
+#define RTC_ICSR_BIN_Pos                    (8U)
+#define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
+#define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
+#define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
+#define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
+#define RTC_ICSR_BCDU_Pos                   (10U)
+#define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
+#define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
+#define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
+#define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
+#define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
+#define RTC_ICSR_RECALPF_Pos                (16U)
+#define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
+#define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_S_Pos               (0U)
+#define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
+#define RTC_PRER_PREDIV_A_Pos               (16U)
+#define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos                    (0U)
+#define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
+#define RTC_WUTR_WUTOCLR_Pos                (16U)
+#define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
+#define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_WUCKSEL_Pos                  (0U)
+#define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
+#define RTC_CR_TSEDGE_Pos                   (3U)
+#define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
+#define RTC_CR_REFCKON_Pos                  (4U)
+#define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
+#define RTC_CR_BYPSHAD_Pos                  (5U)
+#define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
+#define RTC_CR_FMT_Pos                      (6U)
+#define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                          RTC_CR_FMT_Msk
+#define RTC_CR_SSRUIE_Pos                   (7U)
+#define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
+#define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
+#define RTC_CR_ALRAE_Pos                    (8U)
+#define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
+#define RTC_CR_ALRBE_Pos                    (9U)
+#define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
+#define RTC_CR_WUTE_Pos                     (10U)
+#define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
+#define RTC_CR_TSE_Pos                      (11U)
+#define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                          RTC_CR_TSE_Msk
+#define RTC_CR_ALRAIE_Pos                   (12U)
+#define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
+#define RTC_CR_ALRBIE_Pos                   (13U)
+#define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
+#define RTC_CR_WUTIE_Pos                    (14U)
+#define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
+#define RTC_CR_TSIE_Pos                     (15U)
+#define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
+#define RTC_CR_ADD1H_Pos                    (16U)
+#define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
+#define RTC_CR_SUB1H_Pos                    (17U)
+#define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
+#define RTC_CR_BKP_Pos                      (18U)
+#define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                          RTC_CR_BKP_Msk
+#define RTC_CR_COSEL_Pos                    (19U)
+#define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
+#define RTC_CR_POL_Pos                      (20U)
+#define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                          RTC_CR_POL_Msk
+#define RTC_CR_OSEL_Pos                     (21U)
+#define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
+#define RTC_CR_COE_Pos                      (23U)
+#define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                          RTC_CR_COE_Msk
+#define RTC_CR_ITSE_Pos                     (24U)
+#define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
+#define RTC_CR_TAMPTS_Pos                   (25U)
+#define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
+#define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
+#define RTC_CR_TAMPOE_Pos                   (26U)
+#define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
+#define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
+#define RTC_CR_ALRAFCLR_Pos                 (27U)
+#define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
+#define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
+#define RTC_CR_ALRBFCLR_Pos                 (28U)
+#define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
+#define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
+#define RTC_CR_TAMPALRM_PU_Pos              (29U)
+#define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
+#define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
+#define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
+#define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
+#define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
+#define RTC_CR_OUT2EN_Pos                   (31U)
+#define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
+#define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
+
+/********************  Bits definition for RTC_PRIVCFGR register  *****************/
+#define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
+#define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
+#define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
+#define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
+#define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
+#define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
+#define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
+#define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
+#define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
+#define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
+#define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
+#define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
+#define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
+#define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
+#define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
+#define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
+#define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
+#define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
+#define RTC_PRIVCFGR_PRIV_Pos               (15U)
+#define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
+#define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
+
+/********************  Bits definition for RTC_SECCFGR register  ******************/
+#define RTC_SECCFGR_ALRASEC_Pos             (0U)
+#define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
+#define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
+#define RTC_SECCFGR_ALRBSEC_Pos             (1U)
+#define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
+#define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
+#define RTC_SECCFGR_WUTSEC_Pos              (2U)
+#define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
+#define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
+#define RTC_SECCFGR_TSSEC_Pos               (3U)
+#define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
+#define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
+#define RTC_SECCFGR_CALSEC_Pos              (13U)
+#define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
+#define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
+#define RTC_SECCFGR_INITSEC_Pos             (14U)
+#define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
+#define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
+#define RTC_SECCFGR_SEC_Pos                 (15U)
+#define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
+#define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                     (0U)
+#define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALM_Pos                   (0U)
+#define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
+#define RTC_CALR_LPCAL_Pos                  (12U)
+#define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
+#define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALW16_Pos                 (13U)
+#define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
+#define RTC_CALR_CALW8_Pos                  (14U)
+#define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALP_Pos                   (15U)
+#define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos                (0U)
+#define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos                (31U)
+#define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_SU_Pos                     (0U)
+#define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
+#define RTC_TSTR_ST_Pos                     (4U)
+#define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_TSTR_MNU_Pos                    (8U)
+#define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_TSTR_MNT_Pos                    (12U)
+#define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_TSTR_HU_Pos                     (16U)
+#define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_TSTR_HT_Pos                     (20U)
+#define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_TSTR_PM_Pos                     (22U)
+#define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_DU_Pos                     (0U)
+#define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
+#define RTC_TSDR_DT_Pos                     (4U)
+#define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
+#define RTC_TSDR_MU_Pos                     (8U)
+#define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
+#define RTC_TSDR_MT_Pos                     (12U)
+#define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
+#define RTC_TSDR_WDU_Pos                    (13U)
+#define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos                    (0U)
+#define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
+#define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_SU_Pos                   (0U)
+#define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMAR_ST_Pos                   (4U)
+#define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMAR_MSK1_Pos                 (7U)
+#define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_MNU_Pos                  (8U)
+#define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMAR_MNT_Pos                  (12U)
+#define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMAR_MSK2_Pos                 (15U)
+#define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_HU_Pos                   (16U)
+#define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMAR_HT_Pos                   (20U)
+#define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMAR_PM_Pos                   (22U)
+#define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_MSK3_Pos                 (23U)
+#define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_DU_Pos                   (24U)
+#define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMAR_DT_Pos                   (28U)
+#define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMAR_WDSEL_Pos                (30U)
+#define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_MSK4_Pos                 (31U)
+#define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_SS_Pos                 (0U)
+#define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
+#define RTC_ALRMASSR_MASKSS_Pos             (24U)
+#define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMASSR_SSCLR_Pos              (31U)
+#define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_SU_Pos                   (0U)
+#define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMBR_ST_Pos                   (4U)
+#define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMBR_MSK1_Pos                 (7U)
+#define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_MNU_Pos                  (8U)
+#define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMBR_MNT_Pos                  (12U)
+#define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMBR_MSK2_Pos                 (15U)
+#define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_HU_Pos                   (16U)
+#define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMBR_HT_Pos                   (20U)
+#define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMBR_PM_Pos                   (22U)
+#define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_MSK3_Pos                 (23U)
+#define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_DU_Pos                   (24U)
+#define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMBR_DT_Pos                   (28U)
+#define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMBR_WDSEL_Pos                (30U)
+#define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_MSK4_Pos                 (31U)
+#define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_SS_Pos                 (0U)
+#define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
+#define RTC_ALRMBSSR_MASKSS_Pos             (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMBSSR_SSCLR_Pos              (31U)
+#define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_SR register  *******************/
+#define RTC_SR_ALRAF_Pos                    (0U)
+#define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
+#define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
+#define RTC_SR_ALRBF_Pos                    (1U)
+#define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
+#define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
+#define RTC_SR_WUTF_Pos                     (2U)
+#define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
+#define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
+#define RTC_SR_TSF_Pos                      (3U)
+#define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
+#define RTC_SR_TSF                          RTC_SR_TSF_Msk
+#define RTC_SR_TSOVF_Pos                    (4U)
+#define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
+#define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
+#define RTC_SR_ITSF_Pos                     (5U)
+#define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
+#define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
+#define RTC_SR_SSRUF_Pos                    (6U)
+#define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
+#define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
+
+/********************  Bits definition for RTC_MISR register  *****************/
+#define RTC_MISR_ALRAMF_Pos                 (0U)
+#define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
+#define RTC_MISR_ALRBMF_Pos                 (1U)
+#define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
+#define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
+#define RTC_MISR_WUTMF_Pos                  (2U)
+#define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
+#define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
+#define RTC_MISR_TSMF_Pos                   (3U)
+#define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
+#define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
+#define RTC_MISR_TSOVMF_Pos                 (4U)
+#define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
+#define RTC_MISR_ITSMF_Pos                  (5U)
+#define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
+#define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
+#define RTC_MISR_SSRUMF_Pos                 (6U)
+#define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
+#define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SMISR register  *****************/
+#define RTC_SMISR_ALRAMF_Pos                (0U)
+#define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
+#define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
+#define RTC_SMISR_ALRBMF_Pos                (1U)
+#define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
+#define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
+#define RTC_SMISR_WUTMF_Pos                 (2U)
+#define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
+#define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
+#define RTC_SMISR_TSMF_Pos                  (3U)
+#define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
+#define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
+#define RTC_SMISR_TSOVMF_Pos                (4U)
+#define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
+#define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
+#define RTC_SMISR_ITSMF_Pos                 (5U)
+#define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
+#define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
+#define RTC_SMISR_SSRUMF_Pos                (6U)
+#define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
+#define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SCR register  ******************/
+#define RTC_SCR_CALRAF_Pos                  (0U)
+#define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
+#define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
+#define RTC_SCR_CALRBF_Pos                  (1U)
+#define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
+#define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
+#define RTC_SCR_CWUTF_Pos                   (2U)
+#define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
+#define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
+#define RTC_SCR_CTSF_Pos                    (3U)
+#define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
+#define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
+#define RTC_SCR_CTSOVF_Pos                  (4U)
+#define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
+#define RTC_SCR_CITSF_Pos                   (5U)
+#define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
+#define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
+#define RTC_SCR_CSSRUF_Pos                  (6U)
+#define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
+#define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
+
+/********************  Bits definition for RTC_ALRABINR register  ******************/
+#define RTC_ALRABINR_SS_Pos                 (0U)
+#define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
+
+/********************  Bits definition for RTC_ALRBBINR register  ******************/
+#define RTC_ALRBBINR_SS_Pos                 (0U)
+#define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*               Secure Advanced Encryption Standard (SAES)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for SAES_CR register  *********************/
+#define SAES_CR_EN_Pos                       (0U)
+#define SAES_CR_EN_Msk                       (0x1UL << SAES_CR_EN_Pos)                /*!< 0x00000001 */
+#define SAES_CR_EN                           SAES_CR_EN_Msk                           /*!< SAES Enable */
+#define SAES_CR_DATATYPE_Pos                 (1U)
+#define SAES_CR_DATATYPE_Msk                 (0x3UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
+#define SAES_CR_DATATYPE                     SAES_CR_DATATYPE_Msk                     /*!< Data type selection */
+#define SAES_CR_DATATYPE_0                   (0x1UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
+#define SAES_CR_DATATYPE_1                   (0x2UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
+#define SAES_CR_MODE_Pos                     (3U)
+#define SAES_CR_MODE_Msk                     (0x3UL << SAES_CR_MODE_Pos)              /*!< 0x00000018 */
+#define SAES_CR_MODE                         SAES_CR_MODE_Msk                         /*!< SAES Mode Of Operation */
+#define SAES_CR_MODE_0                       (0x1UL << SAES_CR_MODE_Pos)              /*!< 0x00000008 */
+#define SAES_CR_MODE_1                       (0x2UL << SAES_CR_MODE_Pos)              /*!< 0x00000010 */
+#define SAES_CR_CHMOD_Pos                    (5U)
+#define SAES_CR_CHMOD_Msk                    (0x803UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010060 */
+#define SAES_CR_CHMOD                        SAES_CR_CHMOD_Msk                        /*!< SAES Chaining Mode */
+#define SAES_CR_CHMOD_0                      (0x1UL << SAES_CR_CHMOD_Pos)             /*!< 0x00000020*/
+#define SAES_CR_CHMOD_1                      (0x2UL << SAES_CR_CHMOD_Pos)             /*!< 0x00000040 */
+#define SAES_CR_CHMOD_2                      (0x800UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010000 */
+#define SAES_CR_DMAINEN_Pos                  (11U)
+#define SAES_CR_DMAINEN_Msk                  (0x1UL << SAES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
+#define SAES_CR_DMAINEN                      SAES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
+#define SAES_CR_DMAOUTEN_Pos                 (12U)
+#define SAES_CR_DMAOUTEN_Msk                 (0x1UL << SAES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
+#define SAES_CR_DMAOUTEN                     SAES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
+#define SAES_CR_GCMPH_Pos                    (13U)
+#define SAES_CR_GCMPH_Msk                    (0x3UL << SAES_CR_GCMPH_Pos)             /*!< 0x0006000 */
+#define SAES_CR_GCMPH                        SAES_CR_GCMPH_Msk                        /*!< GCM or CCM phase selection */
+#define SAES_CR_GCMPH_0                      (0x1UL << SAES_CR_GCMPH_Pos)             /*!< 0x00020000 */
+#define SAES_CR_GCMPH_1                      (0x2UL << SAES_CR_GCMPH_Pos)             /*!< 0x00040000 */
+#define SAES_CR_KEYSIZE_Pos                  (18U)
+#define SAES_CR_KEYSIZE_Msk                  (0x1UL << SAES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
+#define SAES_CR_KEYSIZE                      SAES_CR_KEYSIZE_Msk                      /*!< Key size selection */
+#define SAES_CR_KEYPROT_Pos                  (19U)
+#define SAES_CR_KEYPROT_Msk                  (0x1UL << SAES_CR_KEYPROT_Pos)           /*!< 0x00080000 */
+#define SAES_CR_KEYPROT                      SAES_CR_KEYPROT_Msk                      /*!<  Key protection */
+#define SAES_CR_NPBLB_Pos                    (20U)
+#define SAES_CR_NPBLB_Msk                    (0xFUL << SAES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
+#define SAES_CR_NPBLB                        SAES_CR_NPBLB_Msk                        /*!< Number of padding bytes in last block */
+#define SAES_CR_NPBLB_0                      (0x1UL << SAES_CR_NPBLB_Pos)             /*!< 0x00100000 */
+#define SAES_CR_NPBLB_1                      (0x2UL << SAES_CR_NPBLB_Pos)             /*!< 0x00200000 */
+#define SAES_CR_NPBLB_2                      (0x4UL << SAES_CR_NPBLB_Pos)             /*!< 0x00400000 */
+#define SAES_CR_NPBLB_3                      (0x8UL << SAES_CR_NPBLB_Pos)             /*!< 0x00800000 */
+#define SAES_CR_KMOD_Pos                     (24U)
+#define SAES_CR_KMOD_Msk                     (0x3UL << SAES_CR_KMOD_Pos)              /*!< 0x03000000 */
+#define SAES_CR_KMOD                         SAES_CR_KMOD_Msk                         /*!< Key mode selection */
+#define SAES_CR_KMOD_0                       (0x1UL << SAES_CR_KMOD_Pos)              /*!< 0x01000000 */
+#define SAES_CR_KMOD_1                       (0x2UL << SAES_CR_KMOD_Pos)              /*!< 0x02000000 */
+#define SAES_CR_KSHAREID_Pos                 (26U)
+#define SAES_CR_KSHAREID_Msk                 (0x3UL << SAES_CR_KSHAREID_Pos)          /*!< 0x0C000000 */
+#define SAES_CR_KSHAREID                     SAES_CR_KSHAREID_Msk                     /*!< Key Shared ID */
+#define SAES_CR_KSHAREID_0                   (0x1UL << SAES_CR_KSHAREID_Pos)          /*!< 0x04000000 */
+#define SAES_CR_KSHAREID_1                   (0x2UL << SAES_CR_KSHAREID_Pos)          /*!< 0x08000000 */
+#define SAES_CR_KEYSEL_Pos                   (28U)
+#define SAES_CR_KEYSEL_Msk                   (0x7UL << SAES_CR_KEYSEL_Pos)            /*!< 0x70000000 */
+#define SAES_CR_KEYSEL                       SAES_CR_KEYSEL_Msk                       /*!< Key Selection */
+#define SAES_CR_KEYSEL_0                     (0x1UL << SAES_CR_KEYSEL_Pos)            /*!< 0x10000000 */
+#define SAES_CR_KEYSEL_1                     (0x2UL << SAES_CR_KEYSEL_Pos)            /*!< 0x20000000 */
+#define SAES_CR_KEYSEL_2                     (0x4UL << SAES_CR_KEYSEL_Pos)            /*!< 0x40000000 */
+#define SAES_CR_IPRST_Pos                    (31U)
+#define SAES_CR_IPRST_Msk                    (0x1UL << SAES_CR_IPRST_Pos)             /*!< 0x80000000 */
+#define SAES_CR_IPRST                        SAES_CR_IPRST_Msk                        /*!< SAES IP software reset */
+
+/*******************  Bits definition for SAES_SR register  *********************/
+#define SAES_SR_CCF_Pos                      (0U)
+#define SAES_SR_CCF_Msk                      (0x1UL << SAES_SR_CCF_Pos)               /*!< 0x00000001 */
+#define SAES_SR_CCF                          SAES_SR_CCF_Msk                          /*!< Computation Complete Flag */
+#define SAES_SR_RDERR_Pos                    (1U)
+#define SAES_SR_RDERR_Msk                    (0x1UL << SAES_SR_RDERR_Pos)             /*!< 0x00000002 */
+#define SAES_SR_RDERR                        SAES_SR_RDERR_Msk                        /*!< Read Error Flag */
+#define SAES_SR_WRERR_Pos                    (2U)
+#define SAES_SR_WRERR_Msk                    (0x1UL << SAES_SR_WRERR_Pos)             /*!< 0x00000004 */
+#define SAES_SR_WRERR                        SAES_SR_WRERR_Msk                        /*!< Write Error Flag */
+#define SAES_SR_BUSY_Pos                     (3U)
+#define SAES_SR_BUSY_Msk                     (0x1UL << SAES_SR_BUSY_Pos)              /*!< 0x00000008 */
+#define SAES_SR_BUSY                         SAES_SR_BUSY_Msk                         /*!< Busy Flag */
+#define SAES_SR_KEYVALID_Pos                 (7U)
+#define SAES_SR_KEYVALID_Msk                 (0x1UL << SAES_SR_KEYVALID_Pos)          /*!< 0x00000080 */
+#define SAES_SR_KEYVALID                     SAES_SR_KEYVALID_Msk                     /*!< Key valid Flag */
+
+/*******************  Bits definition for SAES_DINR register  *******************/
+#define SAES_DINR_Pos                        (0U)
+#define SAES_DINR_Msk                        (0xFFFFFFFFUL << SAES_DINR_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_DINR                            SAES_DINR_Msk                            /*!< SAES Data Input Register */
+
+/*******************  Bits definition for SAES_DOUTR register  ******************/
+#define SAES_DOUTR_Pos                       (0U)
+#define SAES_DOUTR_Msk                       (0xFFFFFFFFUL << SAES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_DOUTR                           SAES_DOUTR_Msk                           /*!< SAES Data Output Register */
+
+/*******************  Bits definition for SAES_KEYR0 register  ******************/
+#define SAES_KEYR0_Pos                       (0U)
+#define SAES_KEYR0_Msk                       (0xFFFFFFFFUL << SAES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR0                           SAES_KEYR0_Msk                           /*!< SAES cryptographic key, bits [31:0] */
+
+/*******************  Bits definition for SAES_KEYR1 register  ******************/
+#define SAES_KEYR1_Pos                       (0U)
+#define SAES_KEYR1_Msk                       (0xFFFFFFFFUL << SAES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR1                           SAES_KEYR1_Msk                           /*!< SAES cryptographic key, bits [63:32] */
+
+/*******************  Bits definition for SAES_KEYR2 register  ******************/
+#define SAES_KEYR2_Pos                       (0U)
+#define SAES_KEYR2_Msk                       (0xFFFFFFFFUL << SAES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR2                           SAES_KEYR2_Msk                           /*!< SAES cryptographic key, bits [95:64] */
+
+/*******************  Bits definition for SAES_KEYR3 register  ******************/
+#define SAES_KEYR3_Pos                       (0U)
+#define SAES_KEYR3_Msk                       (0xFFFFFFFFUL << SAES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR3                           SAES_KEYR3_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR4 register  ******************/
+#define SAES_KEYR4_Pos                       (0U)
+#define SAES_KEYR4_Msk                       (0xFFFFFFFFUL << SAES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR4                           SAES_KEYR4_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR5 register  ******************/
+#define SAES_KEYR5_Pos                       (0U)
+#define SAES_KEYR5_Msk                       (0xFFFFFFFFUL << SAES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR5                           SAES_KEYR5_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR6 register  ******************/
+#define SAES_KEYR6_Pos                       (0U)
+#define SAES_KEYR6_Msk                       (0xFFFFFFFFUL << SAES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR6                           SAES_KEYR6_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR7 register  ******************/
+#define SAES_KEYR7_Pos                       (0U)
+#define SAES_KEYR7_Msk                       (0xFFFFFFFFUL << SAES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR7                           SAES_KEYR7_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_IVR0 register   ******************/
+#define SAES_IVR0_Pos                        (0U)
+#define SAES_IVR0_Msk                        (0xFFFFFFFFUL << SAES_IVR0_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR0                            SAES_IVR0_Msk                            /*!< SAES initialization vector input, bits [31:0] */
+
+/*******************  Bits definition for SAES_IVR1 register   ******************/
+#define SAES_IVR1_Pos                        (0U)
+#define SAES_IVR1_Msk                        (0xFFFFFFFFUL << SAES_IVR1_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR1                            SAES_IVR1_Msk                            /*!< SAES initialization vector input, bits [63:32] */
+
+/*******************  Bits definition for SAES_IVR2 register   ******************/
+#define SAES_IVR2_Pos                        (0U)
+#define SAES_IVR2_Msk                        (0xFFFFFFFFUL << SAES_IVR2_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR2                            SAES_IVR2_Msk                            /*!< SAES initialization vector input, bits [95:64] */
+
+/*******************  Bits definition for SAES_IVR3 register   ******************/
+#define SAES_IVR3_Pos                        (0U)
+#define SAES_IVR3_Msk                        (0xFFFFFFFFUL << SAES_IVR3_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR3                            SAES_IVR3_Msk                            /*!< SAES initialization vector input, bits [127:96] */
+
+/*******************  Bits definition for SAES_DPACFGR register     ******************/
+#define SAES_DPACFGR_REDCFG_Pos              (0U)
+#define SAES_DPACFGR_REDCFG_Msk              (0x3UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000003 */
+#define SAES_DPACFGR_REDCFG                  SAES_DPACFGR_REDCFG_Msk                  /*!< Redundancy configuration*/
+#define SAES_DPACFGR_REDCFG_0                (0x1UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000001 */
+#define SAES_DPACFGR_REDCFG_1                (0x2UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000002 */
+#define SAES_DPACFGR_RESEED_Pos              (2U)
+#define SAES_DPACFGR_RESEED_Msk              (0x1UL << SAES_DPACFGR_RESEED_Pos)       /*!< 0x00000004 */
+#define SAES_DPACFGR_RESEED                  SAES_DPACFGR_RESEED_Msk                  /*!< Automatic reseed enable */
+#define SAES_DPACFGR_TRIMCFG_Pos             (3U)
+#define SAES_DPACFGR_TRIMCFG_Msk             (0x3UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000018 */
+#define SAES_DPACFGR_TRIMCFG                 SAES_DPACFGR_TRIMCFG_Msk                 /*!< Clock trimming */
+#define SAES_DPACFGR_TRIMCFG_0               (0x1UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000008 */
+#define SAES_DPACFGR_TRIMCFG_1               (0x2UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000010 */
+#define SAES_DPACFGR_CONFIGLOCK_Pos          (31U)
+#define SAES_DPACFGR_CONFIGLOCK_Msk          (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos)   /*!< 0x80000000 */
+#define SAES_DPACFGR_CONFIGLOCK               SAES_DPACFGR_CONFIGLOCK_Msk             /*!< DPA configuration lock */
+
+/*******************  Bits definition for SAES_IER register     ******************/
+#define SAES_IER_CCFIE_Pos                   (0U)
+#define SAES_IER_CCFIE_Msk                   (0x1UL << SAES_IER_CCFIE_Pos)            /*!< 0x00000001 */
+#define SAES_IER_CCFIE                       SAES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
+#define SAES_IER_RWEIE_Pos                   (1U)
+#define SAES_IER_RWEIE_Msk                   (0x1UL << SAES_IER_RWEIE_Pos)            /*!< 0x00000002 */
+#define SAES_IER_RWEIE                       SAES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
+#define SAES_IER_KEIE_Pos                    (2U)
+#define SAES_IER_KEIE_Msk                    (0x1UL << SAES_IER_KEIE_Pos)             /*!< 0x00000004 */
+#define SAES_IER_KEIE                        SAES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
+#define SAES_IER_RNGEIE_Pos                  (3U)
+#define SAES_IER_RNGEIE_Msk                  (0x1UL << SAES_IER_RNGEIE_Pos)           /*!< 0x00000008 */
+#define SAES_IER_RNGEIE                      SAES_IER_RNGEIE_Msk                      /*!< RNG error interrupt enable */
+
+/*******************  Bits definition for SAES_ISR register     ******************/
+#define SAES_ISR_CCF_Pos                     (0U)
+#define SAES_ISR_CCF_Msk                     (0x1UL << SAES_ISR_CCF_Pos)              /*!< 0x00000001 */
+#define SAES_ISR_CCF                         SAES_ISR_CCF_Msk                         /*!< Computation complete flag */
+#define SAES_ISR_RWEIF_Pos                   (1U)
+#define SAES_ISR_RWEIF_Msk                   (0x1UL << SAES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
+#define SAES_ISR_RWEIF                       SAES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
+#define SAES_ISR_KEIF_Pos                    (2U)
+#define SAES_ISR_KEIF_Msk                    (0x1UL << SAES_ISR_KEIF_Pos)             /*!< 0x00000004 */
+#define SAES_ISR_KEIF                        SAES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
+#define SAES_ISR_RNGEIF_Pos                  (3U)
+#define SAES_ISR_RNGEIF_Msk                  (0x1UL << SAES_ISR_RNGEIF_Pos)           /*!< 0x00000008 */
+#define SAES_ISR_RNGEIF                      SAES_ISR_RNGEIF_Msk                      /*!< RNG error interrupt flag */
+
+/*******************  Bits definition for SAES_ICR register     ******************/
+#define SAES_ICR_CCF_Pos                     (0U)
+#define SAES_ICR_CCF_Msk                     (0x1UL << SAES_ICR_CCF_Pos)              /*!< 0x00000001 */
+#define SAES_ICR_CCF                         SAES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
+#define SAES_ICR_RWEIF_Pos                   (1U)
+#define SAES_ICR_RWEIF_Msk                   (0x1UL << SAES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
+#define SAES_ICR_RWEIF                       SAES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
+#define SAES_ICR_KEIF_Pos                    (2U)
+#define SAES_ICR_KEIF_Msk                    (0x1UL << SAES_ICR_KEIF_Pos)             /*!< 0x00000004 */
+#define SAES_ICR_KEIF                        SAES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
+#define SAES_ICR_RNGEIF_Pos                  (3U)
+#define SAES_ICR_RNGEIF_Msk                  (0x1UL << SAES_ICR_RNGEIF_Pos)           /*!< 0x00000008 */
+#define SAES_ICR_RNGEIF                      SAES_ICR_RNGEIF_Msk                      /*!< RNG error interrupt flag clear */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos                  (0U)
+#define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
+#define SAI_GCR_SYNCOUT_Pos                 (4U)
+#define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos                   (0U)
+#define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
+#define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
+#define SAI_xCR1_PRTCFG_Pos                 (2U)
+#define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
+#define SAI_xCR1_DS_Pos                     (5U)
+#define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
+#define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
+#define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
+#define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
+#define SAI_xCR1_LSBFIRST_Pos               (8U)
+#define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos                  (9U)
+#define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
+#define SAI_xCR1_SYNCEN_Pos                 (10U)
+#define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
+#define SAI_xCR1_MONO_Pos                   (12U)
+#define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
+#define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos                (13U)
+#define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos                  (16U)
+#define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos                  (17U)
+#define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos                  (19U)
+#define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
+#define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
+#define SAI_xCR1_MCKDIV_Pos                 (20U)
+#define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
+#define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
+#define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
+#define SAI_xCR1_OSR_Pos                    (26U)
+#define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
+#define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
+#define SAI_xCR1_MCKEN_Pos                  (27U)
+#define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos                    (0U)
+#define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
+#define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
+#define SAI_xCR2_FFLUSH_Pos                 (3U)
+#define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos                   (4U)
+#define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
+#define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos                   (5U)
+#define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
+#define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos                (6U)
+#define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
+#define SAI_xCR2_MUTECNT_Pos                (7U)
+#define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
+#define SAI_xCR2_CPL_Pos                    (13U)
+#define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
+#define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos                   (14U)
+#define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
+#define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos                   (0U)
+#define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
+#define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
+#define SAI_xFRCR_FSALL_Pos                 (8U)
+#define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
+#define SAI_xFRCR_FSDEF_Pos                 (16U)
+#define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos                 (17U)
+#define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos                 (18U)
+#define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos                (0U)
+#define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
+#define SAI_xSLOTR_SLOTSZ_Pos               (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
+#define SAI_xSLOTR_NBSLOT_Pos               (8U)
+#define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
+#define SAI_xSLOTR_SLOTEN_Pos               (16U)
+#define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos               (0U)
+#define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos              (1U)
+#define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos               (2U)
+#define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos                 (3U)
+#define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos                (4U)
+#define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos               (5U)
+#define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos               (6U)
+#define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos                  (0U)
+#define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos                 (1U)
+#define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos                  (2U)
+#define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos                    (3U)
+#define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos                   (4U)
+#define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos                  (5U)
+#define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos                  (6U)
+#define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
+#define SAI_xSR_FLVL_Pos                    (16U)
+#define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
+#define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos              (0U)
+#define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos             (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos              (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos                (3U)
+#define SAI_xCLRFR_CFREQ_Msk                (0x1UL << SAI_xCLRFR_CFREQ_Pos)         /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ                    SAI_xCLRFR_CFREQ_Msk                    /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos               (4U)
+#define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos              (5U)
+#define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos              (6U)
+#define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos                    (0U)
+#define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA                        SAI_xDR_DATA_Msk
+
+/******************  Bit definition for SAI_PDMCR register  *******************/
+#define SAI_PDMCR_PDMEN_Pos                 (0U)
+#define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
+#define SAI_PDMCR_MICNBR_Pos                (4U)
+#define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
+#define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
+#define SAI_PDMCR_CKEN1_Pos                 (8U)
+#define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
+#define SAI_PDMCR_CKEN2_Pos                 (9U)
+#define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
+#define SAI_PDMCR_CKEN3_Pos                 (10U)
+#define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
+#define SAI_PDMCR_CKEN4_Pos                 (11U)
+#define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos               (0U)
+#define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
+#define SAI_PDMDLY_DLYM1R_Pos               (4U)
+#define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
+#define SAI_PDMDLY_DLYM2L_Pos               (8U)
+#define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
+#define SAI_PDMDLY_DLYM2R_Pos               (12U)
+#define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
+#define SAI_PDMDLY_DLYM3L_Pos               (16U)
+#define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
+#define SAI_PDMDLY_DLYM3R_Pos               (20U)
+#define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
+#define SAI_PDMDLY_DLYM4L_Pos               (24U)
+#define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
+#define SAI_PDMDLY_DLYM4R_Pos               (28U)
+#define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos             (0U)
+#define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos             (2U)
+#define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos           (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos              (4U)
+#define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos              (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos              (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_WIDBUS_Pos              (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
+#define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos                 (18U)
+#define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos                (0U)
+#define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos              (0U)
+#define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos              (6U)
+#define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos               (7U)
+#define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
+#define SDMMC_CMD_WAITRESP_Pos              (8U)
+#define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITINT_Pos               (10U)
+#define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos              (11U)
+#define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos                (12U)
+#define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos                (13U)
+#define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos              (14U)
+#define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos                (15U)
+#define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos           (0U)
+#define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos           (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos                (0U)
+#define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos               (1U)
+#define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos              (2U)
+#define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+#define SDMMC_DCTRL_RWSTART_Pos             (8U)
+#define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos              (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos               (10U)
+#define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos              (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos             (13U)
+#define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos              (0U)
+#define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos              (1U)
+#define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos              (2U)
+#define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos              (3U)
+#define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos              (4U)
+#define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos               (5U)
+#define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos               (6U)
+#define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos               (7U)
+#define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos               (8U)
+#define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos                 (9U)
+#define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos               (10U)
+#define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos                (11U)
+#define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos               (12U)
+#define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos               (13U)
+#define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos              (14U)
+#define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos              (15U)
+#define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos               (16U)
+#define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos               (17U)
+#define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos               (18U)
+#define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos               (19U)
+#define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos                (20U)
+#define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos             (21U)
+#define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos                (22U)
+#define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos               (23U)
+#define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos                (25U)
+#define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos                (26U)
+#define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos                (27U)
+#define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos               (28U)
+#define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos             (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos             (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos             (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos              (5U)
+#define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos              (6U)
+#define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos              (7U)
+#define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos              (8U)
+#define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos                (9U)
+#define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos              (10U)
+#define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos               (11U)
+#define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos               (22U)
+#define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos              (23U)
+#define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos               (25U)
+#define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos               (26U)
+#define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos               (27U)
+#define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos              (28U)
+#define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos            (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos            (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos            (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos            (8U)
+#define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos              (9U)
+#define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos            (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos             (11U)
+#define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
+#define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos             (22U)
+#define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos            (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos             (25U)
+#define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos             (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos            (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFOTHR register  *******************/
+#define SDMMC_FIFOTHR_THR_Pos               (0U)
+#define SDMMC_FIFOTHR_THR_Msk               (0xFUL << SDMMC_FIFOTHR_THR_Pos)        /*!< 0x0000000F */
+#define SDMMC_FIFOTHR_THR                   SDMMC_FIFOTHR_THR_Msk                   /*!<FIFO threshold */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos             (0U)
+#define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos               (0U)
+#define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos            (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos        (6U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0x7FFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0001FFC0 */
+#define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk              /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASER register  ***************/
+#define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */
+
+/*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
+#define SDMMC_IDMALAR_IDMALA_Pos            (0U)
+#define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
+#define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
+#define SDMMC_IDMALAR_ABR_Pos               (29U)
+#define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
+#define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
+#define SDMMC_IDMALAR_ULS_Pos               (30U)
+#define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
+#define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
+#define SDMMC_IDMALAR_ULA_Pos               (31U)
+#define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
+#define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */
+
+/*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
+#define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos                     (0U)
+#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
+#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
+#define SPI_CR1_MASRX_Pos                   (8U)
+#define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
+#define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
+#define SPI_CR1_CSTART_Pos                  (9U)
+#define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
+#define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
+#define SPI_CR1_CSUSP_Pos                   (10U)
+#define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
+#define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
+#define SPI_CR1_HDDIR_Pos                   (11U)
+#define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
+#define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
+#define SPI_CR1_SSI_Pos                     (12U)
+#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
+#define SPI_CR1_CRC33_17_Pos                (13U)
+#define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
+#define SPI_CR1_RCRCINI_Pos                 (14U)
+#define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
+#define SPI_CR1_TCRCINI_Pos                 (15U)
+#define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
+#define SPI_CR1_IOLOCK_Pos                  (16U)
+#define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSIZE_Pos                   (0U)
+#define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
+
+/*******************  Bit definition for SPI_CFG1 register  *******************/
+#define SPI_CFG1_DSIZE_Pos                  (0U)
+#define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
+#define SPI_CFG1_FTHLV_Pos                  (5U)
+#define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
+#define SPI_CFG1_UDRCFG_Pos                 (9U)
+#define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
+#define SPI_CFG1_RXDMAEN_Pos                (14U)
+#define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
+#define SPI_CFG1_TXDMAEN_Pos                (15U)
+#define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
+#define SPI_CFG1_CRCSIZE_Pos                (16U)
+#define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
+#define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
+#define SPI_CFG1_CRCEN_Pos                  (22U)
+#define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
+#define SPI_CFG1_MBR_Pos                    (28U)
+#define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
+#define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
+#define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
+#define SPI_CFG1_BPASS_Pos                  (31U)
+#define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
+#define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
+
+/*******************  Bit definition for SPI_CFG2 register  *******************/
+#define SPI_CFG2_MSSI_Pos                   (0U)
+#define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
+#define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
+#define SPI_CFG2_MIDI_Pos                   (4U)
+#define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
+#define SPI_CFG2_RDIOM_Pos                  (13U)
+#define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
+#define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
+#define SPI_CFG2_RDIOP_Pos                  (14U)
+#define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
+#define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
+#define SPI_CFG2_IOSWP_Pos                  (15U)
+#define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
+#define SPI_CFG2_COMM_Pos                   (17U)
+#define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
+#define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
+#define SPI_CFG2_SP_Pos                     (19U)
+#define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
+#define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
+#define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
+#define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
+#define SPI_CFG2_MASTER_Pos                 (22U)
+#define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
+#define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
+#define SPI_CFG2_LSBFRST_Pos                (23U)
+#define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
+#define SPI_CFG2_CPHA_Pos                   (24U)
+#define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
+#define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
+#define SPI_CFG2_CPOL_Pos                   (25U)
+#define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
+#define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
+#define SPI_CFG2_SSM_Pos                    (26U)
+#define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
+#define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
+#define SPI_CFG2_SSIOP_Pos                  (28U)
+#define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos                   (29U)
+#define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
+#define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos                   (30U)
+#define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
+#define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
+#define SPI_CFG2_AFCNTR_Pos                 (31U)
+#define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos                   (0U)
+#define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
+#define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
+#define SPI_IER_TXPIE_Pos                   (1U)
+#define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
+#define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
+#define SPI_IER_DXPIE_Pos                   (2U)
+#define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
+#define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
+#define SPI_IER_EOTIE_Pos                   (3U)
+#define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
+#define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
+#define SPI_IER_TXTFIE_Pos                  (4U)
+#define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
+#define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
+#define SPI_IER_UDRIE_Pos                   (5U)
+#define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
+#define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
+#define SPI_IER_OVRIE_Pos                   (6U)
+#define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
+#define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
+#define SPI_IER_CRCEIE_Pos                  (7U)
+#define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
+#define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
+#define SPI_IER_TIFREIE_Pos                 (8U)
+#define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
+#define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos                  (9U)
+#define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
+#define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
+
+/*******************  Bit definition for SPI_SR register  *********************/
+#define SPI_SR_RXP_Pos                      (0U)
+#define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
+#define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_TXP_Pos                      (1U)
+#define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
+#define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
+#define SPI_SR_DXP_Pos                      (2U)
+#define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
+#define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_EOT_Pos                      (3U)
+#define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
+#define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_TXTF_Pos                     (4U)
+#define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
+#define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
+#define SPI_SR_UDR_Pos                      (5U)
+#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
+#define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
+#define SPI_SR_OVR_Pos                      (6U)
+#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
+#define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_CRCE_Pos                     (7U)
+#define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
+#define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
+#define SPI_SR_TIFRE_Pos                    (8U)
+#define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
+#define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
+#define SPI_SR_MODF_Pos                     (9U)
+#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
+#define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
+#define SPI_SR_SUSP_Pos                     (11U)
+#define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
+#define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
+#define SPI_SR_TXC_Pos                      (12U)
+#define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
+#define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos                   (13U)
+#define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
+#define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
+#define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos                    (15U)
+#define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
+#define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
+#define SPI_SR_CTSIZE_Pos                   (16U)
+#define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
+
+/*******************  Bit definition for SPI_IFCR register  *******************/
+#define SPI_IFCR_EOTC_Pos                   (3U)
+#define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
+#define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
+#define SPI_IFCR_TXTFC_Pos                  (4U)
+#define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos                   (5U)
+#define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
+#define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
+#define SPI_IFCR_OVRC_Pos                   (6U)
+#define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
+#define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
+#define SPI_IFCR_CRCEC_Pos                  (7U)
+#define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
+#define SPI_IFCR_TIFREC_Pos                 (8U)
+#define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
+#define SPI_IFCR_MODFC_Pos                  (9U)
+#define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
+#define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
+#define SPI_IFCR_SUSPC_Pos                  (11U)
+#define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
+
+/*******************  Bit definition for SPI_TXDR register  *******************/
+#define SPI_TXDR_TXDR_Pos                   (0U)
+#define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  *******************/
+#define SPI_RXDR_RXDR_Pos                   (0U)
+#define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ****************/
+#define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */
+
+/*******************  Bit definition for SPI_TXCRC register  ******************/
+#define SPI_TXCRC_TXCRC_Pos                 (0U)
+#define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ******************/
+#define SPI_RXCRC_RXCRC_Pos                 (0U)
+#define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ******************/
+#define SPI_UDRDR_UDRDR_Pos                 (0U)
+#define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */
+
+/*******************  Bits definition for SPI_I2SCFGR register  ***************/
+#define SPI_I2SCFGR_I2SMOD_Pos              (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)        /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk                  /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos              (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk              (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk                  /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2                (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos              (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk                  /*!<I2SSTD[1:0] I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)       /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk                 /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_DATLEN_Pos              (8U)
+#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk                  /*!<DATLEN[1:0] Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos               (10U)
+#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)         /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk                   /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos               (11U)
+#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)         /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk                   /*!<Serial audio clock polarity */
+#define SPI_I2SCFGR_FIXCH_Pos               (12U)
+#define SPI_I2SCFGR_FIXCH_Msk               (0x1UL << SPI_I2SCFGR_FIXCH_Pos)         /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH                   SPI_I2SCFGR_FIXCH_Msk                   /*!<Fixed channel length in SLAVE */
+#define SPI_I2SCFGR_WSINV_Pos               (13U)
+#define SPI_I2SCFGR_WSINV_Msk               (0x1UL << SPI_I2SCFGR_WSINV_Pos)         /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV                   SPI_I2SCFGR_WSINV_Msk                   /*!<Word select inversion */
+#define SPI_I2SCFGR_DATFMT_Pos              (14U)
+#define SPI_I2SCFGR_DATFMT_Msk              (0x1UL << SPI_I2SCFGR_DATFMT_Pos)        /*!< 0x00003000 */
+#define SPI_I2SCFGR_DATFMT                  SPI_I2SCFGR_DATFMT_Msk                  /*!<Data format */
+#define SPI_I2SCFGR_I2SDIV_Pos              (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk              (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)       /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV                  SPI_I2SCFGR_I2SDIV_Msk                  /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos                 (24U)
+#define SPI_I2SCFGR_ODD_Msk                 (0x1UL << SPI_I2SCFGR_ODD_Pos)           /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD                     SPI_I2SCFGR_ODD_Msk                     /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos               (25U)
+#define SPI_I2SCFGR_MCKOE_Msk               (0x1UL << SPI_I2SCFGR_MCKOE_Pos)         /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE                   SPI_I2SCFGR_MCKOE_Msk                   /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFRXEN_Pos       (0U)
+#define SPDIFRX_CR_SPDIFRXEN_Msk       (0x3UL << SPDIFRX_CR_SPDIFRXEN_Pos)     /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFRXEN           SPDIFRX_CR_SPDIFRXEN_Msk                /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_SPDIFRXEN_0         (0x01UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000001 */
+#define SPDIFRX_CR_SPDIFRXEN_1         (0x02UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000002 */
+#define SPDIFRX_CR_RXDMAEN_Pos         (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk         (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN             SPDIFRX_CR_RXDMAEN_Msk                  /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos          (3U)
+#define SPDIFRX_CR_RXSTEO_Msk          (0x1UL << SPDIFRX_CR_RXSTEO_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO              SPDIFRX_CR_RXSTEO_Msk                   /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos           (4U)
+#define SPDIFRX_CR_DRFMT_Msk           (0x3UL << SPDIFRX_CR_DRFMT_Pos)         /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT               SPDIFRX_CR_DRFMT_Msk                    /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos            (6U)
+#define SPDIFRX_CR_PMSK_Msk            (0x1UL << SPDIFRX_CR_PMSK_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK                SPDIFRX_CR_PMSK_Msk                     /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos            (7U)
+#define SPDIFRX_CR_VMSK_Msk            (0x1UL << SPDIFRX_CR_VMSK_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK                SPDIFRX_CR_VMSK_Msk                     /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos           (8U)
+#define SPDIFRX_CR_CUMSK_Msk           (0x1UL << SPDIFRX_CR_CUMSK_Pos)         /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK               SPDIFRX_CR_CUMSK_Msk                    /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos           (9U)
+#define SPDIFRX_CR_PTMSK_Msk           (0x1UL << SPDIFRX_CR_PTMSK_Pos)         /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK               SPDIFRX_CR_PTMSK_Msk                    /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos         (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk         (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)       /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN             SPDIFRX_CR_CBDMAEN_Msk                  /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos           (11U)
+#define SPDIFRX_CR_CHSEL_Msk           (0x1UL << SPDIFRX_CR_CHSEL_Pos)         /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL               SPDIFRX_CR_CHSEL_Msk                    /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos            (12U)
+#define SPDIFRX_CR_NBTR_Msk            (0x3UL << SPDIFRX_CR_NBTR_Pos)          /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR                SPDIFRX_CR_NBTR_Msk                     /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos             (14U)
+#define SPDIFRX_CR_WFA_Msk             (0x1UL << SPDIFRX_CR_WFA_Pos)           /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA                 SPDIFRX_CR_WFA_Msk                      /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos           (16U)
+#define SPDIFRX_CR_INSEL_Msk           (0x7UL << SPDIFRX_CR_INSEL_Pos)         /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL               SPDIFRX_CR_INSEL_Msk                    /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos           (20U)
+#define SPDIFRX_CR_CKSEN_Msk           (0x1UL << SPDIFRX_CR_CKSEN_Pos)         /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN               SPDIFRX_CR_CKSEN_Msk                    /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos        (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk        (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)      /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN            SPDIFRX_CR_CKSBKPEN_Msk                 /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos         (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk         (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)       /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE             SPDIFRX_IMR_RXNEIE_Msk                  /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos        (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk        (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)      /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE            SPDIFRX_IMR_CSRNEIE_Msk                 /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos         (2U)
+#define SPDIFRX_IMR_PERRIE_Msk         (0x1UL << SPDIFRX_IMR_PERRIE_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE             SPDIFRX_IMR_PERRIE_Msk                  /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos          (3U)
+#define SPDIFRX_IMR_OVRIE_Msk          (0x1UL << SPDIFRX_IMR_OVRIE_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE              SPDIFRX_IMR_OVRIE_Msk                   /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos         (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk         (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE             SPDIFRX_IMR_SBLKIE_Msk                  /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos        (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk        (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)      /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE            SPDIFRX_IMR_SYNCDIE_Msk                 /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos          (6U)
+#define SPDIFRX_IMR_IFEIE_Msk          (0x1UL << SPDIFRX_IMR_IFEIE_Pos)        /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE              SPDIFRX_IMR_IFEIE_Msk                   /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos            (0U)
+#define SPDIFRX_SR_RXNE_Msk            (0x1UL << SPDIFRX_SR_RXNE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE                SPDIFRX_SR_RXNE_Msk                     /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos           (1U)
+#define SPDIFRX_SR_CSRNE_Msk           (0x1UL << SPDIFRX_SR_CSRNE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE               SPDIFRX_SR_CSRNE_Msk                    /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos            (2U)
+#define SPDIFRX_SR_PERR_Msk            (0x1UL << SPDIFRX_SR_PERR_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR                SPDIFRX_SR_PERR_Msk                     /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos             (3U)
+#define SPDIFRX_SR_OVR_Msk             (0x1UL << SPDIFRX_SR_OVR_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR                 SPDIFRX_SR_OVR_Msk                      /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos             (4U)
+#define SPDIFRX_SR_SBD_Msk             (0x1UL << SPDIFRX_SR_SBD_Pos)           /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD                 SPDIFRX_SR_SBD_Msk                      /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos           (5U)
+#define SPDIFRX_SR_SYNCD_Msk           (0x1UL << SPDIFRX_SR_SYNCD_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD               SPDIFRX_SR_SYNCD_Msk                    /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos            (6U)
+#define SPDIFRX_SR_FERR_Msk            (0x1UL << SPDIFRX_SR_FERR_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR                SPDIFRX_SR_FERR_Msk                     /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos            (7U)
+#define SPDIFRX_SR_SERR_Msk            (0x1UL << SPDIFRX_SR_SERR_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR                SPDIFRX_SR_SERR_Msk                     /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos            (8U)
+#define SPDIFRX_SR_TERR_Msk            (0x1UL << SPDIFRX_SR_TERR_Pos)          /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR                SPDIFRX_SR_TERR_Msk                     /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos          (16U)
+#define SPDIFRX_SR_WIDTH5_Msk          (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)     /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5              SPDIFRX_SR_WIDTH5_Msk                   /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos        (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk        (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)      /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF            SPDIFRX_IFCR_PERRCF_Msk                 /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos         (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk         (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)       /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF             SPDIFRX_IFCR_OVRCF_Msk                  /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos         (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk         (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF             SPDIFRX_IFCR_SBDCF_Msk                  /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos       (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk       (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)     /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF           SPDIFRX_IFCR_SYNCDCF_Msk                /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos             (0U)
+#define SPDIFRX_DR0_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)      /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR                 SPDIFRX_DR0_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos             (24U)
+#define SPDIFRX_DR0_PE_Msk             (0x1UL << SPDIFRX_DR0_PE_Pos)           /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE                 SPDIFRX_DR0_PE_Msk                      /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos              (25U)
+#define SPDIFRX_DR0_V_Msk              (0x1UL << SPDIFRX_DR0_V_Pos)            /*!< 0x02000000 */
+#define SPDIFRX_DR0_V                  SPDIFRX_DR0_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos              (26U)
+#define SPDIFRX_DR0_U_Msk              (0x1UL << SPDIFRX_DR0_U_Pos)            /*!< 0x04000000 */
+#define SPDIFRX_DR0_U                  SPDIFRX_DR0_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos              (27U)
+#define SPDIFRX_DR0_C_Msk              (0x1UL << SPDIFRX_DR0_C_Pos)            /*!< 0x08000000 */
+#define SPDIFRX_DR0_C                  SPDIFRX_DR0_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos             (28U)
+#define SPDIFRX_DR0_PT_Msk             (0x3UL << SPDIFRX_DR0_PT_Pos)           /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT                 SPDIFRX_DR0_PT_Msk                      /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos             (8U)
+#define SPDIFRX_DR1_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)      /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR                 SPDIFRX_DR1_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos             (4U)
+#define SPDIFRX_DR1_PT_Msk             (0x3UL << SPDIFRX_DR1_PT_Pos)           /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT                 SPDIFRX_DR1_PT_Msk                      /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos              (3U)
+#define SPDIFRX_DR1_C_Msk              (0x1UL << SPDIFRX_DR1_C_Pos)            /*!< 0x00000008 */
+#define SPDIFRX_DR1_C                  SPDIFRX_DR1_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos              (2U)
+#define SPDIFRX_DR1_U_Msk              (0x1UL << SPDIFRX_DR1_U_Pos)            /*!< 0x00000004 */
+#define SPDIFRX_DR1_U                  SPDIFRX_DR1_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos              (1U)
+#define SPDIFRX_DR1_V_Msk              (0x1UL << SPDIFRX_DR1_V_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_DR1_V                  SPDIFRX_DR1_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos             (0U)
+#define SPDIFRX_DR1_PE_Msk             (0x1UL << SPDIFRX_DR1_PE_Pos)           /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE                 SPDIFRX_DR1_PE_Msk                      /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos          (16U)
+#define SPDIFRX_DR1_DRNL1_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)     /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1              SPDIFRX_DR1_DRNL1_Msk                   /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos          (0U)
+#define SPDIFRX_DR1_DRNL2_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)     /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2              SPDIFRX_DR1_DRNL2_Msk                   /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos            (0U)
+#define SPDIFRX_CSR_USR_Msk            (0xFFFFUL << SPDIFRX_CSR_USR_Pos)       /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR                SPDIFRX_CSR_USR_Msk                     /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos             (16U)
+#define SPDIFRX_CSR_CS_Msk             (0xFFUL << SPDIFRX_CSR_CS_Pos)          /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS                 SPDIFRX_CSR_CS_Msk                      /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos            (24U)
+#define SPDIFRX_CSR_SOB_Msk            (0x1UL << SPDIFRX_CSR_SOB_Pos)          /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB                SPDIFRX_CSR_SOB_Msk                     /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos            (0U)
+#define SPDIFRX_DIR_THI_Msk            (0x1FFFUL << SPDIFRX_DIR_THI_Pos)       /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI                SPDIFRX_DIR_THI_Msk                     /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos            (16U)
+#define SPDIFRX_DIR_TLO_Msk            (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)       /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO                SPDIFRX_DIR_TLO_Msk                     /*!<Threshold HIGH     */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_BOOTCR register  ****************/
+#define SYSCFG_BOOTCR_BOOT0_PD_Pos          (0U)
+#define SYSCFG_BOOTCR_BOOT0_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT0_PD_Pos)   /*!< 0x00000001 */
+#define SYSCFG_BOOTCR_BOOT0_PD              SYSCFG_BOOTCR_BOOT0_PD_Msk              /*!< BOOT0 pin pull-down disable */
+#define SYSCFG_BOOTCR_BOOT1_PD_Pos          (1U)
+#define SYSCFG_BOOTCR_BOOT1_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT1_PD_Pos)   /*!< 0x00000002 */
+#define SYSCFG_BOOTCR_BOOT1_PD              SYSCFG_BOOTCR_BOOT1_PD_Msk              /*!< BOOT1 pin pull-down disable */
+
+/******************  Bit definition for SYSCFG_CM55CR register  ****************/
+#define SYSCFG_CM55CR_FPU_IT_EN_Pos         (0U)
+#define SYSCFG_CM55CR_FPU_IT_EN_Msk         (0x3FUL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x0000003F */
+#define SYSCFG_CM55CR_FPU_IT_EN             SYSCFG_CM55CR_FPU_IT_EN_Msk             /*!< Enable FPU exception */
+#define SYSCFG_CM55CR_FPU_IT_EN_0           (0x1UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55CR_FPU_IT_EN_1           (0x2UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55CR_FPU_IT_EN_2           (0x4UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55CR_FPU_IT_EN_3           (0x8UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000008 */
+#define SYSCFG_CM55CR_FPU_IT_EN_4           (0x10UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000010 */
+#define SYSCFG_CM55CR_FPU_IT_EN_5           (0x20UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000020 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Pos      (16U)
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Msk      (0x1UL << SYSCFG_CM55CR_LOCKSVTAIRCR_Pos) /*!< 0x00010000 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR          SYSCFG_CM55CR_LOCKSVTAIRCR_Msk
+#define SYSCFG_CM55CR_LOCKNSVTOR_Pos        (17U)
+#define SYSCFG_CM55CR_LOCKNSVTOR_Msk        (0x1UL << SYSCFG_CM55CR_LOCKNSVTOR_Pos) /*!< 0x00020000 */
+#define SYSCFG_CM55CR_LOCKNSVTOR            SYSCFG_CM55CR_LOCKNSVTOR_Msk            /*!< Prevent changes to the non-secure vector table base address */
+#define SYSCFG_CM55CR_LOCKSMPU_Pos          (18U)
+#define SYSCFG_CM55CR_LOCKSMPU_Msk          (0x1UL << SYSCFG_CM55CR_LOCKSMPU_Pos)   /*!< 0x00040000 */
+#define SYSCFG_CM55CR_LOCKSMPU              SYSCFG_CM55CR_LOCKSMPU_Msk              /*!< Prevent changes to programmed secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKNSMPU_Pos         (19U)
+#define SYSCFG_CM55CR_LOCKNSMPU_Msk         (0x1UL << SYSCFG_CM55CR_LOCKNSMPU_Pos)  /*!< 0x00080000 */
+#define SYSCFG_CM55CR_LOCKNSMPU             SYSCFG_CM55CR_LOCKNSMPU_Msk             /*!< Prevent changes to programmed non-secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKSAU_Pos           (20U)
+#define SYSCFG_CM55CR_LOCKSAU_Msk           (0x1UL << SYSCFG_CM55CR_LOCKSAU_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CM55CR_LOCKSAU               SYSCFG_CM55CR_LOCKSAU_Msk               /*!< Prevent changes to secure SAU memory regions already programmed */
+#define SYSCFG_CM55CR_LOCKDCAIC_Pos         (21U)
+#define SYSCFG_CM55CR_LOCKDCAIC_Msk         (0x1UL << SYSCFG_CM55CR_LOCKDCAIC_Pos)  /*!< 0x00200000 */
+#define SYSCFG_CM55CR_LOCKDCAIC             SYSCFG_CM55CR_LOCKDCAIC_Msk
+
+/******************  Bit definition for SYSCFG_CM55TCMCR register  ***************/
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Pos      (0U)
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x0000000F */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ          SYSCFG_CM55TCMCR_CFGITCMSZ_Msk               /*!< Select ITCM memory size */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000001 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000002 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000004 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000008 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos      (4U)
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ          SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk               /*!< Select DTCM memory size */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000010 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000020 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000040 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000080 */
+#define SYSCFG_CM55TCMCR_LOCKTCM_Pos        (16U)
+#define SYSCFG_CM55TCMCR_LOCKTCM_Msk        (0x1UL << SYSCFG_CM55TCMCR_LOCKTCM_Pos)      /*!< 0x00010000 */
+#define SYSCFG_CM55TCMCR_LOCKTCM            SYSCFG_CM55TCMCR_LOCKTCM_Msk                 /*!< Disable writes to registers associated with the TCM region */
+#define SYSCFG_CM55TCMCR_LOCKITGU_Pos       (17U)
+#define SYSCFG_CM55TCMCR_LOCKITGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKITGU_Pos)     /*!< 0x00020000 */
+#define SYSCFG_CM55TCMCR_LOCKITGU           SYSCFG_CM55TCMCR_LOCKITGU_Msk                /*!< Disable writes to registers associated with the ITCM interface security/gating */
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Pos       (18U)
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKDTGU_Pos)     /*!< 0x00040000 */
+#define SYSCFG_CM55TCMCR_LOCKDTGU           SYSCFG_CM55TCMCR_LOCKDTGU_Msk                /*!< Disable writes to registers associated with the DTCM interface security/gating. */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos  (23U)
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos) /*!< 0x00800000 */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE      SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended ITCM memory */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos  (24U)
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos) /*!< 0x01000000 */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE      SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended DTCM memory */
+
+
+/******************  Bit definition for SYSCFG_CM55RWMCR register  **************/
+#define SYSCFG_CM55RWMCR_RME_TCM_Pos        (0U)
+#define SYSCFG_CM55RWMCR_RME_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_RME_TCM_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55RWMCR_RME_TCM            SYSCFG_CM55RWMCR_RME_TCM_Msk              /*!< RW margin enable input for TCM memories */
+#define SYSCFG_CM55RWMCR_RM_TCM_Pos         (1U)
+#define SYSCFG_CM55RWMCR_RM_TCM_Msk         (0xFUL << SYSCFG_CM55RWMCR_RM_TCM_Pos)    /*!< 0x0000001E */
+#define SYSCFG_CM55RWMCR_RM_TCM             SYSCFG_CM55RWMCR_RM_TCM_Msk               /*!< External RW margin inputs for TCM memories */
+#define SYSCFG_CM55RWMCR_BC1_TCM_Pos        (5U)
+#define SYSCFG_CM55RWMCR_BC1_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC1_TCM_Pos)   /*!< 0x00000020 */
+#define SYSCFG_CM55RWMCR_BC1_TCM            SYSCFG_CM55RWMCR_BC1_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_TCM_Pos        (6U)
+#define SYSCFG_CM55RWMCR_BC2_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC2_TCM_Pos)   /*!< 0x00000040 */
+#define SYSCFG_CM55RWMCR_BC2_TCM            SYSCFG_CM55RWMCR_BC2_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom + 10% */
+#define SYSCFG_CM55RWMCR_RME_CACHE_Pos      (7U)
+#define SYSCFG_CM55RWMCR_RME_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_RME_CACHE_Pos) /*!< 0x00000080 */
+#define SYSCFG_CM55RWMCR_RME_CACHE          SYSCFG_CM55RWMCR_RME_CACHE_Msk            /*!< RW margin enable input for caches memories */
+#define SYSCFG_CM55RWMCR_RM_CACHE_Pos       (8U)
+#define SYSCFG_CM55RWMCR_RM_CACHE_Msk       (0xFUL << SYSCFG_CM55RWMCR_RM_CACHE_Pos)  /*!< 0x00000F00 */
+#define SYSCFG_CM55RWMCR_RM_CACHE           SYSCFG_CM55RWMCR_RM_CACHE_Msk             /*!< External read/write (RW) margin inputs for caches memories */
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Pos      (12U)
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC1_CACHE_Pos) /*!< 0x0001000 */
+#define SYSCFG_CM55RWMCR_BC1_CACHE          SYSCFG_CM55RWMCR_BC1_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Pos      (13U)
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC2_CACHE_Pos) /*!< 0x00002000 */
+#define SYSCFG_CM55RWMCR_BC2_CACHE          SYSCFG_CM55RWMCR_BC2_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom + 10% */
+
+/******************  Bit definition for SYSCFG_INITSVTORCR register  **************/
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos   (7U)
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk   (0x1FFFFFFUL << SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos)   /*!< 0xFFFFFF80 */
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR       SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk                    /*!< Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_INITNSVTORCR register  **************/
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos  (7U)
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk  (0x1FFFFFFUL << SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos)  /*!< 0xFFFFFF80 */
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR      SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk                   /*!< Non-Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_CM55RSTCR register  **************/
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos     (0U)
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk     (0x1UL << SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE         SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk            /*!< Select reset to apply on core upon SYSRESETREQ */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos       (1U)
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN           SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos       (2U)
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN           SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+
+/******************  Bit definition for SYSCFG_CM55PAHBWPR register  **************/
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos       (0U)
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk       (0x1UL << SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK           SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk            /*!< Error capture in write posting buffer */
+
+/******************  Bit definition for SYSCFG_VENCRAMCR register  **************/
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Pos     (0U)
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Msk     (0x1UL << SYSCFG_VENCRAMCR_VENCRAM_EN_Pos)               /*!< 0x00000001 */
+#define SYSCFG_VENCRAMCR_VENCRAM_EN         SYSCFG_VENCRAMCR_VENCRAM_EN_Msk                          /*!< VENCRAM allocation VENC if active, or to system (if VENC inactive) */
+
+/******************  Bit definition for SYSCFG_POTTAMPRSTCR register  **************/
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos       (0U)
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk       (0x1UL << SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos) /*!< 0x00000001 */
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK           SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk            /*!< mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper */
+
+/******************  Bit definition for SYSCFG_ICNEWRCR register  **************/
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos     (0U)
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000001 */
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC1 early-write response */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos     (1U)
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC2 early-write response */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos       (2U)
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000004 */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk              /*!< USB1 early-write response */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos       (3U)
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000008 */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk              /*!< USB2 early-write response */
+
+/******************  Bit definition for SYSCFG_ICNCGCR register  **************/
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos              (1U)
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk            /*!< CPU_NIC clock gating disable */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos              (2U)
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos) /*!< 0x00000004 */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk            /*!< CPU_NOC clock gating disable */
+
+/******************  Bit definition for SYSCFG_IOCR register  **************/
+#define SYSCFG_IOCR_IOCR_Pos                (0U)
+#define SYSCFG_IOCR_IOCR_Msk                (0xFFFFFFFFUL << SYSCFG_IOCR_IOCR_Pos)         /*!< 0xFFFFFFFF */
+#define SYSCFG_IOCR_IOCR                    SYSCFG_IOCR_IOCR_Msk                           /*!< Digital or analog pins */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCCR register  **************/
+#define SYSCFG_VDDIO2CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO2CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCCR_RANSRC            SYSCFG_VDDIO2CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC            SYSCFG_VDDIO2CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO2CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCCR_EN                SYSCFG_VDDIO2CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO2 */
+#define SYSCFG_VDDIO2CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO2CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO2CCCR_CS                SYSCFG_VDDIO2CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCSR register  **************/
+#define SYSCFG_VDDIO2CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO2CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCSR_ANSRC             SYSCFG_VDDIO2CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO2CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO2CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCSR_APSRC             SYSCFG_VDDIO2CCSR_APSRC_Msk
+#define SYSCFG_VDDIO2CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO2CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO2CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCSR_READY             SYSCFG_VDDIO2CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCCR register  **************/
+#define SYSCFG_VDDIO3CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO3CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCCR_RANSRC            SYSCFG_VDDIO3CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC            SYSCFG_VDDIO3CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO3CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCCR_EN                SYSCFG_VDDIO3CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO3 */
+#define SYSCFG_VDDIO3CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO3CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO3CCCR_CS                SYSCFG_VDDIO3CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCSR register  **************/
+#define SYSCFG_VDDIO3CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO3CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCSR_ANSRC             SYSCFG_VDDIO3CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO3CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO3CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCSR_APSRC             SYSCFG_VDDIO3CCSR_APSRC_Msk
+#define SYSCFG_VDDIO3CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO3CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO3CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCSR_READY             SYSCFG_VDDIO3CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCCR register  **************/
+#define SYSCFG_VDDIO4CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO4CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCCR_RANSRC            SYSCFG_VDDIO4CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC            SYSCFG_VDDIO4CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO4CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCCR_EN                SYSCFG_VDDIO4CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO4 */
+#define SYSCFG_VDDIO4CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO4CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO4CCCR_CS                SYSCFG_VDDIO4CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCSR register  **************/
+#define SYSCFG_VDDIO4CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO4CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCSR_ANSRC             SYSCFG_VDDIO4CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO4CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO4CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCSR_APSRC             SYSCFG_VDDIO4CCSR_APSRC_Msk
+#define SYSCFG_VDDIO4CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO4CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO4CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCSR_READY             SYSCFG_VDDIO4CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCCR register  **************/
+#define SYSCFG_VDDIO5CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO5CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCCR_RANSRC            SYSCFG_VDDIO5CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC            SYSCFG_VDDIO5CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO5CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCCR_EN                SYSCFG_VDDIO5CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO5 */
+#define SYSCFG_VDDIO5CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO5CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO5CCCR_CS                SYSCFG_VDDIO5CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCSR register  **************/
+#define SYSCFG_VDDIO5CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO5CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCSR_ANSRC             SYSCFG_VDDIO5CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO5CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO5CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCSR_APSRC             SYSCFG_VDDIO5CCSR_APSRC_Msk
+#define SYSCFG_VDDIO5CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO5CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO5CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCSR_READY             SYSCFG_VDDIO5CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDCCCR register  **************/
+#define SYSCFG_VDDCCCR_RANSRC_Pos           (0U)
+#define SYSCFG_VDDCCCR_RANSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x0000000F */
+#define SYSCFG_VDDCCCR_RANSRC               SYSCFG_VDDCCCR_RANSRC_Msk                      /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDCCCR_RANSRC_0             (0x1UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000001 */
+#define SYSCFG_VDDCCCR_RANSRC_1             (0x2UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000002 */
+#define SYSCFG_VDDCCCR_RANSRC_2             (0x4UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000004 */
+#define SYSCFG_VDDCCCR_RANSRC_3             (0x8UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000008 */
+#define SYSCFG_VDDCCCR_RAPSRC_Pos           (4U)
+#define SYSCFG_VDDCCCR_RAPSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x000000F0 */
+#define SYSCFG_VDDCCCR_RAPSRC               SYSCFG_VDDCCCR_RAPSRC_Msk                      /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDCCCR_RAPSRC_0             (0x1UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000010 */
+#define SYSCFG_VDDCCCR_RAPSRC_1             (0x2UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000020 */
+#define SYSCFG_VDDCCCR_RAPSRC_2             (0x4UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000040 */
+#define SYSCFG_VDDCCCR_RAPSRC_3             (0x8UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000080 */
+#define SYSCFG_VDDCCCR_EN_Pos               (8U)
+#define SYSCFG_VDDCCCR_EN_Msk               (0x1UL << SYSCFG_VDDCCCR_EN_Pos)               /*!< 0x00000100 */
+#define SYSCFG_VDDCCCR_EN                   SYSCFG_VDDCCCR_EN_Msk                          /*!< Enables the compensation cell of I/Os supplied by VDD */
+#define SYSCFG_VDDCCCR_CS_Pos               (9U)
+#define SYSCFG_VDDCCCR_CS_Msk               (0x1UL << SYSCFG_VDDCCCR_CS_Pos)               /*!< 0x00000200 */
+#define SYSCFG_VDDCCCR_CS                   SYSCFG_VDDCCCR_CS_Msk                          /*!< Code selection for the compensation cell of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_VDDCCSR register  **************/
+#define SYSCFG_VDDCCSR_ANSRC_Pos            (0U)
+#define SYSCFG_VDDCCSR_ANSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x0000000F */
+#define SYSCFG_VDDCCSR_ANSRC                SYSCFG_VDDCCSR_ANSRC_Msk
+#define SYSCFG_VDDCCSR_ANSRC_0              (0x1UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000001 */
+#define SYSCFG_VDDCCSR_ANSRC_1              (0x2UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000002 */
+#define SYSCFG_VDDCCSR_ANSRC_2              (0x4UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000004 */
+#define SYSCFG_VDDCCSR_ANSRC_3              (0x8UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000008 */
+#define SYSCFG_VDDCCSR_APSRC_Pos            (4U)
+#define SYSCFG_VDDCCSR_APSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x000000F0 */
+#define SYSCFG_VDDCCSR_APSRC                SYSCFG_VDDCCSR_APSRC_Msk
+#define SYSCFG_VDDCCSR_APSRC_0              (0x1UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000010 */
+#define SYSCFG_VDDCCSR_APSRC_1              (0x2UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000020 */
+#define SYSCFG_VDDCCSR_APSRC_2              (0x4UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000040 */
+#define SYSCFG_VDDCCSR_APSRC_3              (0x8UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000080 */
+#define SYSCFG_VDDCCSR_READY_Pos            (8U)
+#define SYSCFG_VDDCCSR_READY_Msk            (0x1UL << SYSCFG_VDDCCSR_READY_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDCCSR_READY                SYSCFG_VDDCCSR_READY_Msk                       /*!< Provides the compensation cell status of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_CBR register  **************/
+#define SYSCFG_CBR_CM55L_Pos                (0U)
+#define SYSCFG_CBR_CM55L_Msk                (0x1UL << SYSCFG_CBR_CM55L_Pos)                /*!< 0x00000001 */
+#define SYSCFG_CBR_CM55L                    SYSCFG_CBR_CM55L_Msk                           /*!< CM55 lockup lock enable */
+#define SYSCFG_CBR_PVDL_LOCK_Pos            (2U)
+#define SYSCFG_CBR_PVDL_LOCK_Msk            (0x1UL << SYSCFG_CBR_PVDL_LOCK_Pos)            /*!< 0x00000004 */
+#define SYSCFG_CBR_PVDL_LOCK                SYSCFG_CBR_PVDL_LOCK_Msk                       /*!< PVD lock enable */
+#define SYSCFG_CBR_BKPRAML_Pos              (8U)
+#define SYSCFG_CBR_BKPRAML_Msk              (0x1UL << SYSCFG_CBR_BKPRAML_Pos)              /*!< 0x00000100 */
+#define SYSCFG_CBR_BKPRAML                  SYSCFG_CBR_BKPRAML_Msk                         /*!< Backup SRAM double ECC error lock */
+#define SYSCFG_CBR_CM55CACHEL_Pos           (9U)
+#define SYSCFG_CBR_CM55CACHEL_Msk           (0x1UL << SYSCFG_CBR_CM55CACHEL_Pos)           /*!< 0x00000200 */
+#define SYSCFG_CBR_CM55CACHEL               SYSCFG_CBR_CM55CACHEL_Msk                      /*!< CM55 cache double ECC error lock */
+#define SYSCFG_CBR_CM55TCML_Pos             (10U)
+#define SYSCFG_CBR_CM55TCML_Msk             (0x1UL << SYSCFG_CBR_CM55TCML_Pos)             /*!< 0x00000400 */
+#define SYSCFG_CBR_CM55TCML                 SYSCFG_CBR_CM55TCML_Msk                        /*!< CM55 TCM double ECC error lock */
+
+/******************  Bit definition for SYSCFG_SEC_AIDCR register  **************/
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Pos     (0U)
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Msk     (0x7UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x0000000F */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC         SYSCFG_SEC_AIDCR_DMACID_SEC_Msk                /* Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_0       (0x1UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000001 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_1       (0x2UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_2       (0x4UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000004 */
+
+/******************  Bit definition for SYSCFG_FMC_RETIMECR register  **************/
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos       (0U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos) /*!< 0x00000001 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX           SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk            /*!< Retiming on Rx path */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos       (1U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos) /*!< 0x00000002 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX           SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk            /*!< Retiming on Tx path */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos         (2U)
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk         (0x1UL << SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos)   /*!< 0x00000004 */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180             SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk              /*!< Delay on feedback clock */
+
+/******************  Bit definition for SYSCFG_BOOTSR register  **************/
+#define SYSCFG_BOOTSR_BOOT0_Pos             (0U)
+#define SYSCFG_BOOTSR_BOOT0_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT0_Pos)             /*!< 0x00000001 */
+#define SYSCFG_BOOTSR_BOOT0                 SYSCFG_BOOTSR_BOOT0_Msk                        /*!< BOOT0 pin value */
+#define SYSCFG_BOOTSR_BOOT1_Pos             (1U)
+#define SYSCFG_BOOTSR_BOOT1_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT1_Pos)             /*!< 0x00000002 */
+#define SYSCFG_BOOTSR_BOOT1                 SYSCFG_BOOTSR_BOOT1_Msk                        /*!< BOOT1 pin value */
+
+/******************  Bit definition for SYSCFG_AHBWP_ERROR_SR register  **************/
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos  (0U)
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk  (0xFFFFFFFFUL << SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR      SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk                   /*!< Reports address of the first error in P-AHB write-posting buffer */
+
+/******************  Bit definition for SYSCFG_SECPRIV_AIDCR register  **************/
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos  (0U)
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk  (0x7UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x0000000F */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC      SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk             /* Non-Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_0    (0x1UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000001 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_1    (0x2UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000002 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_2    (0x4UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000004 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Tamper and backup register (TAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for TAMP_CR1 register  *****************/
+#define TAMP_CR1_TAMP1E_Pos                 (0U)
+#define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
+#define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
+#define TAMP_CR1_TAMP2E_Pos                 (1U)
+#define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
+#define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
+#define TAMP_CR1_TAMP3E_Pos                 (2U)
+#define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
+#define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
+#define TAMP_CR1_TAMP4E_Pos                 (3U)
+#define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
+#define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
+#define TAMP_CR1_TAMP5E_Pos                 (4U)
+#define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
+#define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
+#define TAMP_CR1_TAMP6E_Pos                 (5U)
+#define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
+#define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
+#define TAMP_CR1_TAMP7E_Pos                 (6U)
+#define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
+#define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
+#define TAMP_CR1_ITAMP1E_Pos                (16U)
+#define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
+#define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
+#define TAMP_CR1_ITAMP2E_Pos                (17U)
+#define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
+#define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
+#define TAMP_CR1_ITAMP3E_Pos                (18U)
+#define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
+#define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
+#define TAMP_CR1_ITAMP4E_Pos                (19U)
+#define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
+#define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
+#define TAMP_CR1_ITAMP5E_Pos                (20U)
+#define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
+#define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
+#define TAMP_CR1_ITAMP6E_Pos                (21U)
+#define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
+#define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
+#define TAMP_CR1_ITAMP7E_Pos                (22U)
+#define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
+#define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
+#define TAMP_CR1_ITAMP8E_Pos                (23U)
+#define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
+#define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
+#define TAMP_CR1_ITAMP9E_Pos                (24U)
+#define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
+#define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
+#define TAMP_CR1_ITAMP11E_Pos               (26U)
+#define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
+#define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
+
+/********************  Bits definition for TAMP_CR2 register  *****************/
+#define TAMP_CR2_TAMP1POM_Pos               (0U)
+#define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk
+#define TAMP_CR2_TAMP2POM_Pos               (1U)
+#define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk
+#define TAMP_CR2_TAMP3POM_Pos               (2U)
+#define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
+#define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk
+#define TAMP_CR2_TAMP4POM_Pos               (3U)
+#define TAMP_CR2_TAMP4POM_Msk               (0x1UL << TAMP_CR2_TAMP4POM_Pos)        /*!< 0x00000008 */
+#define TAMP_CR2_TAMP4POM                   TAMP_CR2_TAMP4POM_Msk
+#define TAMP_CR2_TAMP5POM_Pos               (4U)
+#define TAMP_CR2_TAMP5POM_Msk               (0x1UL << TAMP_CR2_TAMP5POM_Pos)        /*!< 0x00000010 */
+#define TAMP_CR2_TAMP5POM                   TAMP_CR2_TAMP5POM_Msk
+#define TAMP_CR2_TAMP6POM_Pos               (5U)
+#define TAMP_CR2_TAMP6POM_Msk               (0x1UL << TAMP_CR2_TAMP6POM_Pos)        /*!< 0x00000020 */
+#define TAMP_CR2_TAMP6POM                   TAMP_CR2_TAMP6POM_Msk
+#define TAMP_CR2_TAMP7POM_Pos               (6U)
+#define TAMP_CR2_TAMP7POM_Msk               (0x1UL << TAMP_CR2_TAMP7POM_Pos)        /*!< 0x00000040 */
+#define TAMP_CR2_TAMP7POM                   TAMP_CR2_TAMP7POM_Msk
+#define TAMP_CR2_TAMP1MSK_Pos               (16U)
+#define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos               (17U)
+#define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP3MSK_Pos               (18U)
+#define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
+#define TAMP_CR2_BKBLOCK_Pos                (22U)
+#define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
+#define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
+#define TAMP_CR2_BKERASE_Pos                (23U)
+#define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
+#define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
+#define TAMP_CR2_TAMP1TRG_Pos               (24U)
+#define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos               (25U)
+#define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
+#define TAMP_CR2_TAMP3TRG_Pos               (26U)
+#define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
+#define TAMP_CR2_TAMP4TRG_Pos               (27U)
+#define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
+#define TAMP_CR2_TAMP5TRG_Pos               (28U)
+#define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
+#define TAMP_CR2_TAMP6TRG_Pos               (29U)
+#define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
+#define TAMP_CR2_TAMP7TRG_Pos               (30U)
+#define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
+
+/********************  Bits definition for TAMP_CR3 register  *****************/
+#define TAMP_CR3_ITAMP1POM_Pos              (0U)
+#define TAMP_CR3_ITAMP1POM_Msk              (0x1UL << TAMP_CR3_ITAMP1POM_Pos)       /*!< 0x00000001 */
+#define TAMP_CR3_ITAMP1POM                  TAMP_CR3_ITAMP1POM_Msk
+#define TAMP_CR3_ITAMP2POM_Pos              (1U)
+#define TAMP_CR3_ITAMP2POM_Msk              (0x1UL << TAMP_CR3_ITAMP2POM_Pos)       /*!< 0x00000002 */
+#define TAMP_CR3_ITAMP2POM                  TAMP_CR3_ITAMP2POM_Msk
+#define TAMP_CR3_ITAMP3POM_Pos              (2U)
+#define TAMP_CR3_ITAMP3POM_Msk              (0x1UL << TAMP_CR3_ITAMP3POM_Pos)       /*!< 0x00000004 */
+#define TAMP_CR3_ITAMP3POM                  TAMP_CR3_ITAMP3POM_Msk
+#define TAMP_CR3_ITAMP4POM_Pos              (3U)
+#define TAMP_CR3_ITAMP4POM_Msk              (0x1UL << TAMP_CR3_ITAMP4POM_Pos)       /*!< 0x00000008 */
+#define TAMP_CR3_ITAMP4POM                  TAMP_CR3_ITAMP4POM_Msk
+#define TAMP_CR3_ITAMP5POM_Pos              (4U)
+#define TAMP_CR3_ITAMP5POM_Msk              (0x1UL << TAMP_CR3_ITAMP5POM_Pos)       /*!< 0x00000010 */
+#define TAMP_CR3_ITAMP5POM                  TAMP_CR3_ITAMP5POM_Msk
+#define TAMP_CR3_ITAMP6POM_Pos              (5U)
+#define TAMP_CR3_ITAMP6POM_Msk              (0x1UL << TAMP_CR3_ITAMP6POM_Pos)       /*!< 0x00000020 */
+#define TAMP_CR3_ITAMP6POM                  TAMP_CR3_ITAMP6POM_Msk
+#define TAMP_CR3_ITAMP7POM_Pos              (6U)
+#define TAMP_CR3_ITAMP7POM_Msk              (0x1UL << TAMP_CR3_ITAMP7POM_Pos)       /*!< 0x00000040 */
+#define TAMP_CR3_ITAMP7POM                  TAMP_CR3_ITAMP7POM_Msk
+#define TAMP_CR3_ITAMP8POM_Pos              (7U)
+#define TAMP_CR3_ITAMP8POM_Msk              (0x1UL << TAMP_CR3_ITAMP8POM_Pos)       /*!< 0x00000080 */
+#define TAMP_CR3_ITAMP8POM                  TAMP_CR3_ITAMP8POM_Msk
+#define TAMP_CR3_ITAMP9POM_Pos              (8U)
+#define TAMP_CR3_ITAMP9POM_Msk              (0x1UL << TAMP_CR3_ITAMP9POM_Pos)       /*!< 0x00000100 */
+#define TAMP_CR3_ITAMP9POM                  TAMP_CR3_ITAMP9POM_Msk
+#define TAMP_CR3_ITAMP11POM_Pos             (10U)
+#define TAMP_CR3_ITAMP11POM_Msk             (0x1UL << TAMP_CR3_ITAMP11POM_Pos)      /*!< 0x00000400 */
+#define TAMP_CR3_ITAMP11POM                 TAMP_CR3_ITAMP11POM_Msk
+
+/********************  Bits definition for TAMP_FLTCR register  ***************/
+#define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
+#define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
+#define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
+#define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
+#define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
+#define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
+#define TAMP_FLTCR_TAMPFLT_Pos              (3U)
+#define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
+#define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
+#define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
+#define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
+#define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
+#define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
+#define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
+#define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
+#define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
+#define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
+#define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
+#define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
+
+/********************  Bits definition for TAMP_ATCR1 register  ***************/
+#define TAMP_ATCR1_TAMP1AM_Pos              (0U)
+#define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
+#define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
+#define TAMP_ATCR1_TAMP2AM_Pos              (1U)
+#define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
+#define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
+#define TAMP_ATCR1_TAMP3AM_Pos              (2U)
+#define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
+#define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
+#define TAMP_ATCR1_TAMP4AM_Pos              (3U)
+#define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
+#define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
+#define TAMP_ATCR1_TAMP5AM_Pos              (4U)
+#define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
+#define TAMP_ATCR1_TAMP6AM_Pos              (5U)
+#define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
+#define TAMP_ATCR1_TAMP7AM_Pos              (6U)
+#define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
+#define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
+#define TAMP_ATCR1_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
+#define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
+#define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR1_ATOSEL2_Pos              (10U)
+#define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
+#define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
+#define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR1_ATOSEL3_Pos              (12U)
+#define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
+#define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
+#define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR1_ATOSEL4_Pos              (14U)
+#define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
+#define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
+#define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR1_ATCKSEL_Pos              (16U)
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
+#define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
+#define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR1_ATPER_Pos                (24U)
+#define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
+#define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
+#define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
+#define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
+#define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
+#define TAMP_ATCR1_ATOSHARE_Pos             (30U)
+#define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
+#define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
+#define TAMP_ATCR1_FLTEN_Pos                (31U)
+#define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
+#define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
+
+/********************  Bits definition for TAMP_ATSEEDR register  ******************/
+#define TAMP_ATSEEDR_SEED_Pos               (0U)
+#define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
+
+/********************  Bits definition for TAMP_ATOR register  ******************/
+#define TAMP_ATOR_PRNG_Pos                  (0U)
+#define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)          /*!< 0x000000FF */
+#define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
+#define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
+#define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
+#define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
+#define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
+#define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
+#define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
+#define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
+#define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
+#define TAMP_ATOR_SEEDF_Pos                 (14U)
+#define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
+#define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
+#define TAMP_ATOR_INITS_Pos                 (15U)
+#define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
+#define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
+
+/********************  Bits definition for TAMP_ATCR2 register  ***************/
+#define TAMP_ATCR2_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
+#define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
+#define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR2_ATOSEL2_Pos              (11U)
+#define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
+#define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
+#define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR2_ATOSEL3_Pos              (14U)
+#define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
+#define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
+#define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR2_ATOSEL4_Pos              (17U)
+#define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
+#define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
+#define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR2_ATOSEL5_Pos              (20U)
+#define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
+#define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
+#define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
+#define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
+#define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
+#define TAMP_ATCR2_ATOSEL6_Pos              (23U)
+#define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
+#define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
+#define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
+#define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
+#define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
+#define TAMP_ATCR2_ATOSEL7_Pos              (26U)
+#define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
+#define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
+#define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
+#define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
+#define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
+
+/********************  Bits definition for TAMP_SECCFGR register  *************/
+#define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
+#define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
+#define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
+#define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
+#define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
+#define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
+#define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
+#define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
+#define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
+#define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
+#define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
+#define TAMP_SECCFGR_CNT1SEC_Pos            (15U)
+#define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)     /*!< 0x00008000 */
+#define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
+#define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
+#define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
+#define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
+#define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
+#define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
+#define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
+#define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
+#define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
+#define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
+#define TAMP_SECCFGR_BHKLOCK_Pos            (30U)
+#define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
+#define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
+#define TAMP_SECCFGR_TAMPSEC_Pos            (31U)
+#define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
+#define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk
+
+/********************  Bits definition for TAMP_PRIVCFGR register  ************/
+#define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
+#define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
+#define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
+#define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
+#define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
+#define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
+#define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
+#define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
+#define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
+#define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
+
+/********************  Bits definition for TAMP_IER register  *****************/
+#define TAMP_IER_TAMP1IE_Pos                (0U)
+#define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
+#define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
+#define TAMP_IER_TAMP2IE_Pos                (1U)
+#define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
+#define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
+#define TAMP_IER_TAMP3IE_Pos                (2U)
+#define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
+#define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
+#define TAMP_IER_TAMP4IE_Pos                (3U)
+#define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
+#define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
+#define TAMP_IER_TAMP5IE_Pos                (4U)
+#define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
+#define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
+#define TAMP_IER_TAMP6IE_Pos                (5U)
+#define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
+#define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
+#define TAMP_IER_TAMP7IE_Pos                (6U)
+#define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
+#define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
+#define TAMP_IER_ITAMP1IE_Pos               (16U)
+#define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
+#define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
+#define TAMP_IER_ITAMP2IE_Pos               (17U)
+#define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
+#define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
+#define TAMP_IER_ITAMP3IE_Pos               (18U)
+#define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
+#define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
+#define TAMP_IER_ITAMP4IE_Pos               (19U)
+#define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
+#define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
+#define TAMP_IER_ITAMP5IE_Pos               (20U)
+#define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
+#define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
+#define TAMP_IER_ITAMP6IE_Pos               (21U)
+#define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
+#define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
+#define TAMP_IER_ITAMP7IE_Pos               (22U)
+#define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
+#define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
+#define TAMP_IER_ITAMP8IE_Pos               (23U)
+#define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
+#define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
+#define TAMP_IER_ITAMP9IE_Pos               (24U)
+#define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
+#define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
+#define TAMP_IER_ITAMP11IE_Pos              (26U)
+#define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
+#define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
+
+/********************  Bits definition for TAMP_SR register  *****************/
+#define TAMP_SR_TAMP1F_Pos                  (0U)
+#define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
+#define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
+#define TAMP_SR_TAMP2F_Pos                  (1U)
+#define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
+#define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
+#define TAMP_SR_TAMP3F_Pos                  (2U)
+#define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
+#define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
+#define TAMP_SR_TAMP4F_Pos                  (3U)
+#define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
+#define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
+#define TAMP_SR_TAMP5F_Pos                  (4U)
+#define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
+#define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
+#define TAMP_SR_TAMP6F_Pos                  (5U)
+#define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
+#define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
+#define TAMP_SR_TAMP7F_Pos                  (6U)
+#define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
+#define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
+#define TAMP_SR_ITAMP1F_Pos                 (16U)
+#define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
+#define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
+#define TAMP_SR_ITAMP2F_Pos                 (17U)
+#define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
+#define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
+#define TAMP_SR_ITAMP3F_Pos                 (18U)
+#define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
+#define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
+#define TAMP_SR_ITAMP4F_Pos                 (19U)
+#define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
+#define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
+#define TAMP_SR_ITAMP5F_Pos                 (20U)
+#define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
+#define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
+#define TAMP_SR_ITAMP6F_Pos                 (21U)
+#define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
+#define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
+#define TAMP_SR_ITAMP7F_Pos                 (22U)
+#define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
+#define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
+#define TAMP_SR_ITAMP8F_Pos                 (23U)
+#define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
+#define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
+#define TAMP_SR_ITAMP9F_Pos                 (24U)
+#define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
+#define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
+#define TAMP_SR_ITAMP11F_Pos                (26U)
+#define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
+#define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
+
+/********************  Bits definition for TAMP_MISR register  ****************/
+#define TAMP_MISR_TAMP1MF_Pos               (0U)
+#define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
+#define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
+#define TAMP_MISR_TAMP2MF_Pos               (1U)
+#define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
+#define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
+#define TAMP_MISR_TAMP3MF_Pos               (2U)
+#define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
+#define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
+#define TAMP_MISR_TAMP4MF_Pos               (3U)
+#define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
+#define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
+#define TAMP_MISR_TAMP5MF_Pos               (4U)
+#define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
+#define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
+#define TAMP_MISR_TAMP6MF_Pos               (5U)
+#define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
+#define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
+#define TAMP_MISR_TAMP7MF_Pos               (6U)
+#define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
+#define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
+#define TAMP_MISR_ITAMP1MF_Pos              (16U)
+#define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
+#define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
+#define TAMP_MISR_ITAMP2MF_Pos              (17U)
+#define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
+#define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
+#define TAMP_MISR_ITAMP3MF_Pos              (18U)
+#define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
+#define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
+#define TAMP_MISR_ITAMP4MF_Pos              (19U)
+#define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
+#define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
+#define TAMP_MISR_ITAMP5MF_Pos              (20U)
+#define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
+#define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
+#define TAMP_MISR_ITAMP6MF_Pos              (21U)
+#define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
+#define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
+#define TAMP_MISR_ITAMP7MF_Pos              (22U)
+#define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
+#define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
+#define TAMP_MISR_ITAMP8MF_Pos              (23U)
+#define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
+#define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
+#define TAMP_MISR_ITAMP9MF_Pos              (24U)
+#define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
+#define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
+#define TAMP_MISR_ITAMP11MF_Pos             (26U)
+#define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
+#define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SMISR register  ************ *****/
+#define TAMP_SMISR_TAMP1MF_Pos              (0U)
+#define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
+#define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
+#define TAMP_SMISR_TAMP2MF_Pos              (1U)
+#define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
+#define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
+#define TAMP_SMISR_TAMP3MF_Pos              (2U)
+#define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
+#define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
+#define TAMP_SMISR_TAMP4MF_Pos              (3U)
+#define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
+#define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
+#define TAMP_SMISR_TAMP5MF_Pos              (4U)
+#define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
+#define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
+#define TAMP_SMISR_TAMP6MF_Pos              (5U)
+#define TAMP_SMISR_TAMP6MF_Msk              (0x1UL << TAMP_SMISR_TAMP6MF_Pos)       /*!< 0x00000020 */
+#define TAMP_SMISR_TAMP6MF                  TAMP_SMISR_TAMP6MF_Msk
+#define TAMP_SMISR_TAMP7MF_Pos              (6U)
+#define TAMP_SMISR_TAMP7MF_Msk              (0x1UL << TAMP_SMISR_TAMP7MF_Pos)       /*!< 0x00000040 */
+#define TAMP_SMISR_TAMP7MF                  TAMP_SMISR_TAMP7MF_Msk
+#define TAMP_SMISR_ITAMP1MF_Pos             (16U)
+#define TAMP_SMISR_ITAMP1MF_Msk             (0x1UL << TAMP_SMISR_ITAMP1MF_Pos)      /*!< 0x00010000 */
+#define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
+#define TAMP_SMISR_ITAMP2MF_Pos             (17U)
+#define TAMP_SMISR_ITAMP2MF_Msk             (0x1UL << TAMP_SMISR_ITAMP2MF_Pos)      /*!< 0x00020000 */
+#define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
+#define TAMP_SMISR_ITAMP3MF_Pos             (18U)
+#define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
+#define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
+#define TAMP_SMISR_ITAMP4MF_Pos             (19U)
+#define TAMP_SMISR_ITAMP4MF_Msk             (0x1UL << TAMP_SMISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
+#define TAMP_SMISR_ITAMP4MF                 TAMP_SMISR_ITAMP4MF_Msk
+#define TAMP_SMISR_ITAMP5MF_Pos             (20U)
+#define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
+#define TAMP_SMISR_ITAMP6MF_Pos             (21U)
+#define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
+#define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
+#define TAMP_SMISR_ITAMP7MF_Pos             (22U)
+#define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
+#define TAMP_SMISR_ITAMP8MF_Pos             (23U)
+#define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
+#define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
+#define TAMP_SMISR_ITAMP9MF_Pos             (24U)
+#define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
+#define TAMP_SMISR_ITAMP11MF_Pos            (26U)
+#define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SCR register  *****************/
+#define TAMP_SCR_CTAMP1F_Pos                (0U)
+#define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
+#define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
+#define TAMP_SCR_CTAMP2F_Pos                (1U)
+#define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
+#define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
+#define TAMP_SCR_CTAMP3F_Pos                (2U)
+#define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
+#define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
+#define TAMP_SCR_CTAMP4F_Pos                (3U)
+#define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
+#define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
+#define TAMP_SCR_CTAMP5F_Pos                (4U)
+#define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
+#define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
+#define TAMP_SCR_CTAMP6F_Pos                (5U)
+#define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
+#define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
+#define TAMP_SCR_CTAMP7F_Pos                (6U)
+#define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
+#define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
+#define TAMP_SCR_CTAMP8F_Pos                (7U)
+#define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
+#define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
+#define TAMP_SCR_CITAMP1F_Pos               (16U)
+#define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
+#define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
+#define TAMP_SCR_CITAMP2F_Pos               (17U)
+#define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
+#define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
+#define TAMP_SCR_CITAMP3F_Pos               (18U)
+#define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
+#define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
+#define TAMP_SCR_CITAMP4F_Pos               (19U)
+#define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
+#define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
+#define TAMP_SCR_CITAMP5F_Pos               (20U)
+#define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
+#define TAMP_SCR_CITAMP6F_Pos               (21U)
+#define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
+#define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
+#define TAMP_SCR_CITAMP7F_Pos               (22U)
+#define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
+#define TAMP_SCR_CITAMP8F_Pos               (23U)
+#define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
+#define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
+#define TAMP_SCR_CITAMP9F_Pos               (24U)
+#define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
+#define TAMP_SCR_CITAMP11F_Pos              (26U)
+#define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
+
+/********************  Bits definition for TAMP_COUNT1R register  ***************/
+#define TAMP_COUNT1R_COUNT_Pos              (0U)
+#define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
+#define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
+
+/********************  Bits definition for TAMP_OR register  ***************/
+#define TAMP_OR_VCOREMEN_Pos                (0U)
+#define TAMP_OR_VCOREMEN_Msk                (0x1UL << TAMP_OR_VCOREMEN_Pos)         /*!< 0x00000001 */
+#define TAMP_OR_VCOREMEN                    TAMP_OR_VCOREMEN_Msk
+
+/********************  Bits definition for TAMP_RPCFGR register  ***************/
+#define TAMP_RPCFGR_RPCFG0_Pos              (0U)
+#define TAMP_RPCFGR_RPCFG0_Msk              (0x1UL << TAMP_RPCFGR_RPCFG0_Pos)       /*!< 0x00000001 */
+#define TAMP_RPCFGR_RPCFG0                  TAMP_RPCFGR_RPCFG0_Msk
+
+/********************  Bits definition for TAMP_BKP0R register  ***************/
+#define TAMP_BKP0R_Pos                      (0U)
+#define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP0R                          TAMP_BKP0R_Msk
+
+/********************  Bits definition for TAMP_BKP1R register  ****************/
+#define TAMP_BKP1R_Pos                      (0U)
+#define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP1R                          TAMP_BKP1R_Msk
+
+/********************  Bits definition for TAMP_BKP2R register  ****************/
+#define TAMP_BKP2R_Pos                      (0U)
+#define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP2R                          TAMP_BKP2R_Msk
+
+/********************  Bits definition for TAMP_BKP3R register  ****************/
+#define TAMP_BKP3R_Pos                      (0U)
+#define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP3R                          TAMP_BKP3R_Msk
+
+/********************  Bits definition for TAMP_BKP4R register  ****************/
+#define TAMP_BKP4R_Pos                      (0U)
+#define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP4R                          TAMP_BKP4R_Msk
+
+/********************  Bits definition for TAMP_BKP5R register  ****************/
+#define TAMP_BKP5R_Pos                      (0U)
+#define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP5R                          TAMP_BKP5R_Msk
+
+/********************  Bits definition for TAMP_BKP6R register  ****************/
+#define TAMP_BKP6R_Pos                      (0U)
+#define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP6R                          TAMP_BKP6R_Msk
+
+/********************  Bits definition for TAMP_BKP7R register  ****************/
+#define TAMP_BKP7R_Pos                      (0U)
+#define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP7R                          TAMP_BKP7R_Msk
+
+/********************  Bits definition for TAMP_BKP8R register  ****************/
+#define TAMP_BKP8R_Pos                      (0U)
+#define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP8R                          TAMP_BKP8R_Msk
+
+/********************  Bits definition for TAMP_BKP9R register  ****************/
+#define TAMP_BKP9R_Pos                      (0U)
+#define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP9R                          TAMP_BKP9R_Msk
+
+/********************  Bits definition for TAMP_BKP10R register  ***************/
+#define TAMP_BKP10R_Pos                     (0U)
+#define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP10R                         TAMP_BKP10R_Msk
+
+/********************  Bits definition for TAMP_BKP11R register  ***************/
+#define TAMP_BKP11R_Pos                     (0U)
+#define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP11R                         TAMP_BKP11R_Msk
+
+/********************  Bits definition for TAMP_BKP12R register  ***************/
+#define TAMP_BKP12R_Pos                     (0U)
+#define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP12R                         TAMP_BKP12R_Msk
+
+/********************  Bits definition for TAMP_BKP13R register  ***************/
+#define TAMP_BKP13R_Pos                     (0U)
+#define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP13R                         TAMP_BKP13R_Msk
+
+/********************  Bits definition for TAMP_BKP14R register  ***************/
+#define TAMP_BKP14R_Pos                     (0U)
+#define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP14R                         TAMP_BKP14R_Msk
+
+/********************  Bits definition for TAMP_BKP15R register  ***************/
+#define TAMP_BKP15R_Pos                     (0U)
+#define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP15R                         TAMP_BKP15R_Msk
+
+/********************  Bits definition for TAMP_BKP16R register  ***************/
+#define TAMP_BKP16R_Pos                     (0U)
+#define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP16R                         TAMP_BKP16R_Msk
+
+/********************  Bits definition for TAMP_BKP17R register  ***************/
+#define TAMP_BKP17R_Pos                     (0U)
+#define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP17R                         TAMP_BKP17R_Msk
+
+/********************  Bits definition for TAMP_BKP18R register  ***************/
+#define TAMP_BKP18R_Pos                     (0U)
+#define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP18R                         TAMP_BKP18R_Msk
+
+/********************  Bits definition for TAMP_BKP19R register  ***************/
+#define TAMP_BKP19R_Pos                     (0U)
+#define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP19R                         TAMP_BKP19R_Msk
+
+/********************  Bits definition for TAMP_BKP20R register  ***************/
+#define TAMP_BKP20R_Pos                     (0U)
+#define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP20R                         TAMP_BKP20R_Msk
+
+/********************  Bits definition for TAMP_BKP21R register  ***************/
+#define TAMP_BKP21R_Pos                     (0U)
+#define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP21R                         TAMP_BKP21R_Msk
+
+/********************  Bits definition for TAMP_BKP22R register  ***************/
+#define TAMP_BKP22R_Pos                     (0U)
+#define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP22R                         TAMP_BKP22R_Msk
+
+/********************  Bits definition for TAMP_BKP23R register  ***************/
+#define TAMP_BKP23R_Pos                     (0U)
+#define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP23R                         TAMP_BKP23R_Msk
+
+/********************  Bits definition for TAMP_BKP24R register  ***************/
+#define TAMP_BKP24R_Pos                     (0U)
+#define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP24R                         TAMP_BKP24R_Msk
+
+/********************  Bits definition for TAMP_BKP25R register  ***************/
+#define TAMP_BKP25R_Pos                     (0U)
+#define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP25R                         TAMP_BKP25R_Msk
+
+/********************  Bits definition for TAMP_BKP26R register  ***************/
+#define TAMP_BKP26R_Pos                     (0U)
+#define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP26R                         TAMP_BKP26R_Msk
+
+/********************  Bits definition for TAMP_BKP27R register  ***************/
+#define TAMP_BKP27R_Pos                     (0U)
+#define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP27R                         TAMP_BKP27R_Msk
+
+/********************  Bits definition for TAMP_BKP28R register  ***************/
+#define TAMP_BKP28R_Pos                     (0U)
+#define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP28R                         TAMP_BKP28R_Msk
+
+/********************  Bits definition for TAMP_BKP29R register  ***************/
+#define TAMP_BKP29R_Pos                     (0U)
+#define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP29R                         TAMP_BKP29R_Msk
+
+/********************  Bits definition for TAMP_BKP30R register  ***************/
+#define TAMP_BKP30R_Pos                     (0U)
+#define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP30R                         TAMP_BKP30R_Msk
+
+/********************  Bits definition for TAMP_BKP31R register  ***************/
+#define TAMP_BKP31R_Pos                     (0U)
+#define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP31R                         TAMP_BKP31R_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+#define TIM_CR1_DITHEN_Pos        (12U)
+#define TIM_CR1_DITHEN_Msk        (0x1UL << TIM_CR1_DITHEN_Pos)                /*!< 0x00001000 */
+#define TIM_CR1_DITHEN            TIM_CR1_DITHEN_Msk                           /*!<Dithering enable */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (     0x1UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (     0x2UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (     0x4UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
+#define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS4N_Pos         (15U)
+#define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
+#define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
+#define TIM_CR2_ADSYNC_Pos        (28U)
+#define TIM_CR2_ADSYNC_Msk        (0x1UL << TIM_CR2_ADSYNC_Pos)                /*!< 0x10000000 */
+#define TIM_CR2_ADSYNC            TIM_CR2_ADSYNC_Msk                           /*!<ADC synchronization */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+#define TIM_SMCR_SMSPE_Pos        (24U)
+#define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
+#define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
+#define TIM_SMCR_SMSPS_Pos        (25U)
+#define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
+#define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+#define TIM_DIER_IDXIE_Pos        (20U)
+#define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
+#define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
+#define TIM_DIER_DIRIE_Pos        (21U)
+#define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
+#define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
+#define TIM_DIER_IERRIE_Pos       (22U)
+#define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
+#define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
+#define TIM_DIER_TERRIE_Pos       (23U)
+#define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
+#define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_IDXF_Pos           (20U)
+#define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
+#define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
+#define TIM_SR_DIRF_Pos           (21U)
+#define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
+#define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
+#define TIM_SR_IERRF_Pos          (22U)
+#define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
+#define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
+#define TIM_SR_TERRF_Pos          (23U)
+#define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
+#define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NE_Pos        (14U)
+#define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
+#define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFUL << TIM_CCR5_CCR5_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFFUL << TIM_CCR6_CCR6_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_DTR2 register  *********************/
+#define TIM_DTR2_DTGF_Pos         (0U)
+#define TIM_DTR2_DTGF_Msk         (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
+#define TIM_DTR2_DTGF             TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
+#define TIM_DTR2_DTGF_0           (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
+#define TIM_DTR2_DTGF_1           (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
+#define TIM_DTR2_DTGF_2           (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
+#define TIM_DTR2_DTGF_3           (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
+#define TIM_DTR2_DTGF_4           (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
+#define TIM_DTR2_DTGF_5           (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
+#define TIM_DTR2_DTGF_6           (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
+#define TIM_DTR2_DTGF_7           (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
+#define TIM_DTR2_DTAE_Pos         (16U)
+#define TIM_DTR2_DTAE_Msk         (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
+#define TIM_DTR2_DTAE             TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
+#define TIM_DTR2_DTPE_Pos         (17U)
+#define TIM_DTR2_DTPE_Msk         (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
+#define TIM_DTR2_DTPE             TIM_DTR2_DTPE_Msk                            /*!<Deadtime preload enable */
+
+/*******************  Bit definition for TIM_ECR register  *********************/
+#define TIM_ECR_IE_Pos            (0U)
+#define TIM_ECR_IE_Msk            (0x1UL << TIM_ECR_IE_Pos)                    /*!< 0x00000001 */
+#define TIM_ECR_IE                TIM_ECR_IE_Msk                               /*!<Index enable */
+#define TIM_ECR_IDIR_Pos          (1U)
+#define TIM_ECR_IDIR_Msk          (0x3UL << TIM_ECR_IDIR_Pos)                  /*!< 0x00000006 */
+#define TIM_ECR_IDIR              TIM_ECR_IDIR_Msk                             /*!<IDIR[1:0] bits (Index direction)*/
+#define TIM_ECR_IDIR_0            (0x01UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000001 */
+#define TIM_ECR_IDIR_1            (0x02UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000002 */
+#define TIM_ECR_IBLK_Pos          (3U)
+#define TIM_ECR_IBLK_Msk          (0x3UL << TIM_ECR_IBLK_Pos)                  /*!< 0x00000018 */
+#define TIM_ECR_IBLK              TIM_ECR_IBLK_Msk                             /*!<IBLK[1:0] bits (Index blanking)*/
+#define TIM_ECR_IBLK_0            (0x01UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000008 */
+#define TIM_ECR_IBLK_1            (0x02UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000010 */
+#define TIM_ECR_FIDX_Pos          (5U)
+#define TIM_ECR_FIDX_Msk          (0x1UL << TIM_ECR_FIDX_Pos)                  /*!< 0x00000020 */
+#define TIM_ECR_FIDX              TIM_ECR_FIDX_Msk                             /*!<First index enable */
+#define TIM_ECR_IPOS_Pos          (6U)
+#define TIM_ECR_IPOS_Msk          (0x3UL << TIM_ECR_IPOS_Pos)                  /*!< 0x000000C0 */
+#define TIM_ECR_IPOS              TIM_ECR_IPOS_Msk                             /*!<IPOS[1:0] bits (Index positioning)*/
+#define TIM_ECR_IPOS_0            (0x01UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000040 */
+#define TIM_ECR_IPOS_1            (0x02UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000080 */
+#define TIM_ECR_PW_Pos            (16U)
+#define TIM_ECR_PW_Msk            (0xFFUL << TIM_ECR_PW_Pos)                   /*!< 0x00FF0000 */
+#define TIM_ECR_PW                TIM_ECR_PW_Msk                               /*!<PW[7:0] bits (Pulse width)*/
+#define TIM_ECR_PW_0              (0x01UL << TIM_ECR_PW_Pos)                   /*!< 0x00010000 */
+#define TIM_ECR_PW_1              (0x02UL << TIM_ECR_PW_Pos)                   /*!< 0x00020000 */
+#define TIM_ECR_PW_2              (0x04UL << TIM_ECR_PW_Pos)                   /*!< 0x00040000 */
+#define TIM_ECR_PW_3              (0x08UL << TIM_ECR_PW_Pos)                   /*!< 0x00080000 */
+#define TIM_ECR_PW_4              (0x10UL << TIM_ECR_PW_Pos)                   /*!< 0x00100000 */
+#define TIM_ECR_PW_5              (0x20UL << TIM_ECR_PW_Pos)                   /*!< 0x00200000 */
+#define TIM_ECR_PW_6              (0x40UL << TIM_ECR_PW_Pos)                   /*!< 0x00400000 */
+#define TIM_ECR_PW_7              (0x80UL << TIM_ECR_PW_Pos)                   /*!< 0x00800000 */
+#define TIM_ECR_PWPRSC_Pos        (24U)
+#define TIM_ECR_PWPRSC_Msk        (0x7UL << TIM_ECR_PWPRSC_Pos)                /*!< 0x07000000 */
+#define TIM_ECR_PWPRSC            TIM_ECR_PWPRSC_Msk                           /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
+#define TIM_ECR_PWPRSC_0          (0x01UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x01000000 */
+#define TIM_ECR_PWPRSC_1          (0x02UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x02000000 */
+#define TIM_ECR_PWPRSC_2          (0x04UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x04000000 */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits */
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits */
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits */
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits */
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM_AF1 register  ********************/
+#define TIM_AF1_BKINE_Pos        (0U)
+#define TIM_AF1_BKINE_Msk        (0x1UL << TIM_AF1_BKINE_Pos)                  /*!< 0x00000001 */
+#define TIM_AF1_BKINE            TIM_AF1_BKINE_Msk                             /*!<BRK BKIN input enable */
+#define TIM_AF1_BKCMP1E_Pos      (1U)
+#define TIM_AF1_BKCMP1E_Msk      (0x1UL << TIM_AF1_BKCMP1E_Pos)                /*!< 0x00000002 */
+#define TIM_AF1_BKCMP1E          TIM_AF1_BKCMP1E_Msk                           /*!<BRK CMP1 enable */
+#define TIM_AF1_BKCMP2E_Pos      (2U)
+#define TIM_AF1_BKCMP2E_Msk      (0x1UL << TIM_AF1_BKCMP2E_Pos)                /*!< 0x00000004 */
+#define TIM_AF1_BKCMP2E          TIM_AF1_BKCMP2E_Msk                           /*!<BRK CMP2 enable */
+#define TIM_AF1_BKCMP3E_Pos      (3U)
+#define TIM_AF1_BKCMP3E_Msk      (0x1UL << TIM_AF1_BKCMP3E_Pos)                /*!< 0x00000008 */
+#define TIM_AF1_BKCMP3E          TIM_AF1_BKCMP3E_Msk                           /*!<BRK CMP3 enable */
+#define TIM_AF1_BKCMP4E_Pos      (4U)
+#define TIM_AF1_BKCMP4E_Msk      (0x1UL << TIM_AF1_BKCMP4E_Pos)                /*!< 0x00000010 */
+#define TIM_AF1_BKCMP4E          TIM_AF1_BKCMP4E_Msk                           /*!<BRK CMP4 enable */
+#define TIM_AF1_BKCMP5E_Pos      (5U)
+#define TIM_AF1_BKCMP5E_Msk      (0x1UL << TIM_AF1_BKCMP5E_Pos)                /*!< 0x00000020 */
+#define TIM_AF1_BKCMP5E          TIM_AF1_BKCMP5E_Msk                           /*!<BRK CMP5 enable */
+#define TIM_AF1_BKCMP6E_Pos      (6U)
+#define TIM_AF1_BKCMP6E_Msk      (0x1UL << TIM_AF1_BKCMP6E_Pos)                /*!< 0x00000040 */
+#define TIM_AF1_BKCMP6E          TIM_AF1_BKCMP6E_Msk                           /*!<BRK CMP6 enable */
+#define TIM_AF1_BKCMP7E_Pos      (7U)
+#define TIM_AF1_BKCMP7E_Msk      (0x1UL << TIM_AF1_BKCMP7E_Pos)                /*!< 0x00000080 */
+#define TIM_AF1_BKCMP7E          TIM_AF1_BKCMP7E_Msk                           /*!<BRK CMP7 enable */
+#define TIM_AF1_BKCMP8E_Pos      (8U)
+#define TIM_AF1_BKCMP8E_Msk      (0x1UL << TIM_AF1_BKCMP8E_Pos)                /*!< 0x00000100 */
+#define TIM_AF1_BKCMP8E          TIM_AF1_BKCMP8E_Msk                           /*!<BRK CMP8 enable */
+#define TIM_AF1_BKINP_Pos        (9U)
+#define TIM_AF1_BKINP_Msk        (0x1UL << TIM_AF1_BKINP_Pos)                  /*!< 0x00000200 */
+#define TIM_AF1_BKINP            TIM_AF1_BKINP_Msk                             /*!<BRK BKIN input polarity */
+#define TIM_AF1_BKCMP1P_Pos      (10U)
+#define TIM_AF1_BKCMP1P_Msk      (0x1UL << TIM_AF1_BKCMP1P_Pos)                /*!< 0x00000400 */
+#define TIM_AF1_BKCMP1P          TIM_AF1_BKCMP1P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP2P_Pos      (11U)
+#define TIM_AF1_BKCMP2P_Msk      (0x1UL << TIM_AF1_BKCMP2P_Pos)                /*!< 0x00000800 */
+#define TIM_AF1_BKCMP2P          TIM_AF1_BKCMP2P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP3P_Pos      (12U)
+#define TIM_AF1_BKCMP3P_Msk      (0x1UL << TIM_AF1_BKCMP3P_Pos)                /*!< 0x00001000 */
+#define TIM_AF1_BKCMP3P          TIM_AF1_BKCMP3P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP4P_Pos      (13U)
+#define TIM_AF1_BKCMP4P_Msk      (0x1UL << TIM_AF1_BKCMP4P_Pos)                /*!< 0x00002000 */
+#define TIM_AF1_BKCMP4P          TIM_AF1_BKCMP4P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_ETRSEL_Pos       (14U)
+#define TIM_AF1_ETRSEL_Msk       (0xFUL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x0003C000 */
+#define TIM_AF1_ETRSEL           TIM_AF1_ETRSEL_Msk                            /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
+#define TIM_AF1_ETRSEL_0         (0x1UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM_AF1_ETRSEL_1         (0x2UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM_AF1_ETRSEL_2         (0x4UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM_AF1_ETRSEL_3         (0x8UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM_AF2 register  ********************/
+#define TIM_AF2_BK2INE_Pos       (0U)
+#define TIM_AF2_BK2INE_Msk       (0x1UL << TIM_AF2_BK2INE_Pos)                 /*!< 0x00000001 */
+#define TIM_AF2_BK2INE           TIM_AF2_BK2INE_Msk                            /*!<BRK2 BKIN input enable */
+#define TIM_AF2_BK2CMP8E_Pos     (8U)
+#define TIM_AF2_BK2CMP8E_Msk     (0x1UL << TIM_AF2_BK2CMP8E_Pos)               /*!< 0x00000100 */
+#define TIM_AF2_BK2CMP8E         TIM_AF2_BK2CMP8E_Msk                          /*!<BRK2 CMP8 enable */
+#define TIM_AF2_BK2INP_Pos       (9U)
+#define TIM_AF2_BK2INP_Msk       (0x1UL << TIM_AF2_BK2INP_Pos)                 /*!< 0x00000200 */
+#define TIM_AF2_BK2INP           TIM_AF2_BK2INP_Msk                            /*!<BRK2 BKIN input polarity */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
+#define TIM_DCR_DBSS_Pos          (16U)
+#define TIM_DCR_DBSS_Msk          (0xFUL << TIM_DCR_DBSS_Pos)                  /*!< 0x000F0000 */
+#define TIM_DCR_DBSS              TIM_DCR_DBSS_Msk                             /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
+#define TIM_DCR_DBSS_0            (0x01UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00010000 */
+#define TIM_DCR_DBSS_1            (0x02UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00020000 */
+#define TIM_DCR_DBSS_2            (0x04UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00040000 */
+#define TIM_DCR_DBSS_3            (0x08UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                    UCPD                                       */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bits definition for UCPD_CFG1 register  *******************/
+#define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
+#define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
+#define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
+#define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
+#define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
+#define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
+#define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
+#define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
+#define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
+#define UCPD_CFG1_IFRGAP_Pos                (6U)
+#define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
+#define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
+#define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
+#define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
+#define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
+#define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
+#define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
+#define UCPD_CFG1_TRANSWIN_Pos              (11U)
+#define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
+#define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
+#define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
+#define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
+#define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
+#define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
+#define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
+#define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
+#define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
+#define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
+#define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
+#define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
+#define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
+#define UCPD_CFG1_RXORDSETEN_Pos            (20U)
+#define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
+#define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
+#define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
+#define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
+#define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
+#define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
+#define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
+#define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
+#define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
+#define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
+#define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
+#define UCPD_CFG1_TXDMAEN_Pos               (29U)
+#define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
+#define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
+#define UCPD_CFG1_RXDMAEN_Pos               (30U)
+#define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
+#define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
+#define UCPD_CFG1_UCPDEN_Pos                (31U)
+#define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
+#define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
+
+/********************  Bits definition for UCPD_CFG2 register  *******************/
+#define UCPD_CFG2_RXFILTDIS_Pos             (0U)
+#define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
+#define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
+#define UCPD_CFG2_RXFILT2N3_Pos             (1U)
+#define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
+#define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
+#define UCPD_CFG2_FORCECLK_Pos              (2U)
+#define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
+#define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
+#define UCPD_CFG2_WUPEN_Pos                 (3U)
+#define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
+#define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
+#define UCPD_CFG2_RXAFILTEN_Pos             (8U)
+#define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)   /*!< 0x00000100 */
+#define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk              /*!< Rx analog filter enable */
+
+/********************  Bits definition for UCPD_CR register  *********************/
+#define UCPD_CR_TXMODE_Pos                  (0U)
+#define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
+#define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
+#define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
+#define UCPD_CR_TXSEND_Pos                  (2U)
+#define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
+#define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXHRST_Pos                  (3U)
+#define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
+#define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
+#define UCPD_CR_RXMODE_Pos                  (4U)
+#define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
+#define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
+#define UCPD_CR_PHYRXEN_Pos                 (5U)
+#define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
+#define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
+#define UCPD_CR_PHYCCSEL_Pos                (6U)
+#define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
+#define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
+#define UCPD_CR_ANASUBMODE_Pos              (7U)
+#define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
+#define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
+#define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
+#define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
+#define UCPD_CR_ANAMODE_Pos                 (9U)
+#define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
+#define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
+#define UCPD_CR_CCENABLE_Pos                (10U)
+#define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
+#define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
+#define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
+#define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
+#define UCPD_CR_USEEXTPHY_Pos               (12U)
+#define UCPD_CR_USEEXTPHY_Msk               (0x1UL << UCPD_CR_USEEXTPHY_Pos)     /*!< 0x00001000 */
+#define UCPD_CR_USEEXTPHY                   UCPD_CR_USEEXTPHY_Msk                /*!< Controls enable of USB Power Delivery transmitter */
+#define UCPD_CR_CC2VCONNEN_Pos              (13U)
+#define UCPD_CR_CC2VCONNEN_Msk              (0x1UL << UCPD_CR_CC2VCONNEN_Pos)    /*!< 0x00002000 */
+#define UCPD_CR_CC2VCONNEN                  UCPD_CR_CC2VCONNEN_Msk               /*!< VCONN enable for CC2 */
+#define UCPD_CR_CC1VCONNEN_Pos              (14U)
+#define UCPD_CR_CC1VCONNEN_Msk              (0x1UL << UCPD_CR_CC1VCONNEN_Pos)    /*!< 0x00004000 */
+#define UCPD_CR_CC1VCONNEN                  UCPD_CR_CC1VCONNEN_Msk               /*!< VCONN enable for CC1 */
+#define UCPD_CR_DBATEN_Pos                  (15U)
+#define UCPD_CR_DBATEN_Msk                  (0x1UL << UCPD_CR_DBATEN_Pos)        /*!< 0x00008000 */
+#define UCPD_CR_DBATEN                      UCPD_CR_DBATEN_Msk                   /*!< Enable dead battery behavior (Active High) */
+#define UCPD_CR_FRSTX_Pos                   (17U)
+#define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
+#define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
+#define UCPD_CR_RDCH_Pos                    (18U)
+#define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
+#define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
+#define UCPD_CR_RPUSBABSENT_Pos             (19U)
+#define UCPD_CR_RPUSBABSENT_Msk             (0x1UL << UCPD_CR_RPUSBABSENT_Pos)   /*!< 0x00080000 */
+#define UCPD_CR_RPUSBABSENT                 UCPD_CR_RPUSBABSENT_Msk              /*!<  */
+#define UCPD_CR_CC1TCDIS_Pos                (20U)
+#define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
+#define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
+#define UCPD_CR_CC2TCDIS_Pos                (21U)
+#define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
+#define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
+
+/********************  Bits definition for UCPD_IMR register  ********************/
+#define UCPD_IMR_TXISIE_Pos                 (0U)
+#define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
+#define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
+#define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
+#define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
+#define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
+#define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
+#define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
+#define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
+#define UCPD_IMR_TXMSGABTIE_Pos             (3U)
+#define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
+#define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
+#define UCPD_IMR_HRSTDISCIE_Pos             (4U)
+#define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
+#define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
+#define UCPD_IMR_HRSTSENTIE_Pos             (5U)
+#define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
+#define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
+#define UCPD_IMR_TXUNDIE_Pos                (6U)
+#define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
+#define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
+#define UCPD_IMR_RXNEIE_Pos                 (8U)
+#define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
+#define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
+#define UCPD_IMR_RXORDDETIE_Pos             (9U)
+#define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
+#define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
+#define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
+#define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
+#define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
+#define UCPD_IMR_RXOVRIE_Pos                (11U)
+#define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
+#define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
+#define UCPD_IMR_RXMSGENDIE_Pos             (12U)
+#define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
+#define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
+#define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
+#define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
+#define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
+#define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
+#define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
+#define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
+
+/********************  Bits definition for UCPD_SR register  *********************/
+#define UCPD_SR_TXIS_Pos                    (0U)
+#define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
+#define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
+#define UCPD_SR_TXMSGDISC_Pos               (1U)
+#define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
+#define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
+#define UCPD_SR_TXMSGSENT_Pos               (2U)
+#define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
+#define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
+#define UCPD_SR_TXMSGABT_Pos                (3U)
+#define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
+#define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
+#define UCPD_SR_HRSTDISC_Pos                (4U)
+#define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
+#define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
+#define UCPD_SR_HRSTSENT_Pos                (5U)
+#define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
+#define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
+#define UCPD_SR_TXUND_Pos                   (6U)
+#define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
+#define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
+#define UCPD_SR_RXNE_Pos                    (8U)
+#define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
+#define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
+#define UCPD_SR_RXORDDET_Pos                (9U)
+#define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
+#define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
+#define UCPD_SR_RXHRSTDET_Pos               (10U)
+#define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
+#define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
+#define UCPD_SR_RXOVR_Pos                   (11U)
+#define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
+#define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
+#define UCPD_SR_RXMSGEND_Pos                (12U)
+#define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
+#define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
+#define UCPD_SR_RXERR_Pos                   (13U)
+#define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
+#define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
+#define UCPD_SR_TYPECEVT1_Pos               (14U)
+#define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
+#define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
+#define UCPD_SR_TYPECEVT2_Pos               (15U)
+#define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
+#define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
+#define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
+#define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
+
+/********************  Bits definition for UCPD_ICR register  ********************/
+#define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
+#define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
+#define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
+#define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
+#define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
+#define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
+#define UCPD_ICR_TXMSGABTCF_Pos             (3U)
+#define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
+#define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
+#define UCPD_ICR_HRSTDISCCF_Pos             (4U)
+#define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
+#define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
+#define UCPD_ICR_HRSTSENTCF_Pos             (5U)
+#define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
+#define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
+#define UCPD_ICR_TXUNDCF_Pos                (6U)
+#define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
+#define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
+#define UCPD_ICR_RXORDDETCF_Pos             (9U)
+#define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
+#define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
+#define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
+#define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
+#define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
+#define UCPD_ICR_RXOVRCF_Pos                (11U)
+#define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
+#define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
+#define UCPD_ICR_RXMSGENDCF_Pos             (12U)
+#define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
+#define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
+#define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
+#define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
+#define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
+#define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
+#define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
+#define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
+
+/********************  Bits definition for UCPD_TXORDSET register  ***************/
+#define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
+#define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
+#define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
+
+/********************  Bits definition for UCPD_TXPAYSZ register  ****************/
+#define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
+#define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
+
+/********************  Bits definition for UCPD_TXDR register  *******************/
+#define UCPD_TXDR_TXDATA_Pos                (0U)
+#define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                 /*!< Tx Data Register */
+
+/********************  Bits definition for UCPD_RXORDSET register  ***************/
+#define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
+#define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
+#define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
+#define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
+#define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
+#define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
+#define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
+#define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
+#define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
+#define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
+
+/********************  Bits definition for UCPD_RXPAYSZ register  ****************/
+#define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
+#define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
+
+/********************  Bits definition for UCPD_RXDR register  *******************/
+#define UCPD_RXDR_RXDATA_Pos                (0U)
+#define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
+
+/********************  Bits definition for UCPD_RXORDEXT1 register  **************/
+#define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
+#define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+/********************  Bits definition for UCPD_RXORDEXT2 register  **************/
+#define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
+#define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                    (0U)
+#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
+#define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
+#define USART_CR1_UESM_Pos                  (1U)
+#define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
+#define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                    (2U)
+#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
+#define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                    (3U)
+#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
+#define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos                (4U)
+#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos                (5U)
+#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
+#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
+#define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos                  (6U)
+#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
+#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos                 (7U)
+#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos                  (8U)
+#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
+#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                    (9U)
+#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
+#define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
+#define USART_CR1_PCE_Pos                   (10U)
+#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
+#define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos                  (11U)
+#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
+#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                     (12U)
+#define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                         USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                    (12U)
+#define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
+#define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos                   (13U)
+#define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
+#define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos                  (14U)
+#define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
+#define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match Interrupt Enable */
+#define USART_CR1_OVER8_Pos                 (15U)
+#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos                  (16U)
+#define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
+#define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos                  (21U)
+#define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
+#define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos                 (26U)
+#define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
+#define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
+#define USART_CR1_EOBIE_Pos                 (27U)
+#define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
+#define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
+#define USART_CR1_M1_Pos                    (28U)
+#define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
+#define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos                (29U)
+#define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos                (30U)
+#define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
+#define USART_CR1_RXFFIE_Pos                (31U)
+#define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos                 (0U)
+#define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
+#define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
+#define USART_CR2_DIS_NSS_Pos               (3U)
+#define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos                 (4U)
+#define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
+#define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos                  (5U)
+#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
+#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos                 (6U)
+#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
+#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos                  (8U)
+#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
+#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos                  (9U)
+#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
+#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos                  (10U)
+#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
+#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos                 (11U)
+#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
+#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
+#define USART_CR2_STOP_Pos                  (12U)
+#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
+#define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos                 (14U)
+#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
+#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos                  (15U)
+#define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
+#define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos                 (16U)
+#define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
+#define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos                 (17U)
+#define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
+#define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos               (18U)
+#define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
+#define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos              (19U)
+#define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos                 (20U)
+#define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
+#define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos               (21U)
+#define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
+#define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos                 (23U)
+#define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
+#define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos                   (24U)
+#define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
+#define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos                   (0U)
+#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
+#define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos                  (1U)
+#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
+#define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos                  (2U)
+#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
+#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos                 (3U)
+#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
+#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos                  (4U)
+#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
+#define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos                  (5U)
+#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
+#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos                  (6U)
+#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
+#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos                  (7U)
+#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
+#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos                  (8U)
+#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
+#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos                  (9U)
+#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
+#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos                 (10U)
+#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
+#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos                (11U)
+#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos                (12U)
+#define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos                  (13U)
+#define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
+#define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos                   (14U)
+#define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
+#define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos                   (15U)
+#define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
+#define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos               (17U)
+#define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos                   (20U)
+#define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
+#define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos                 (22U)
+#define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
+#define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos                (23U)
+#define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TCBGTIE_Pos               (24U)
+#define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_Pos               (25U)
+#define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
+#define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos                (28U)
+#define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TXFTCFG_Pos               (29U)
+#define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
+#define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_LPUART                    ((uint32_t)0x000FFFFF)                  /*!< LPUART Baud rate register [19:0] */
+#define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos                  (0U)
+#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
+#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos                   (8U)
+#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
+#define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos                  (0U)
+#define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Timeout Value */
+#define USART_RTOR_BLEN_Pos                 (24U)
+#define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos                 (0U)
+#define USART_RQR_ABRRQ_Msk                 (0x1UL << USART_RQR_ABRRQ_Pos)          /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                     USART_RQR_ABRRQ_Msk                     /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos                 (1U)
+#define USART_RQR_SBKRQ_Msk                 (0x1UL << USART_RQR_SBKRQ_Pos)          /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                     USART_RQR_SBKRQ_Msk                     /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos                  (2U)
+#define USART_RQR_MMRQ_Msk                  (0x1UL << USART_RQR_MMRQ_Pos)           /*!< 0x00000004 */
+#define USART_RQR_MMRQ                      USART_RQR_MMRQ_Msk                      /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos                 (3U)
+#define USART_RQR_RXFRQ_Msk                 (0x1UL << USART_RQR_RXFRQ_Pos)          /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                     USART_RQR_RXFRQ_Msk                     /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos                 (4U)
+#define USART_RQR_TXFRQ_Msk                 (0x1UL << USART_RQR_TXFRQ_Pos)          /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                     USART_RQR_TXFRQ_Msk                     /*!< Transmit Data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                    (0U)
+#define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
+#define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
+#define USART_ISR_FE_Pos                    (1U)
+#define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
+#define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
+#define USART_ISR_NE_Pos                    (2U)
+#define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
+#define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise Error detection Flag */
+#define USART_ISR_ORE_Pos                   (3U)
+#define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
+#define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos                  (4U)
+#define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
+#define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos                  (5U)
+#define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
+#define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
+#define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
+#define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                    (6U)
+#define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
+#define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos                   (7U)
+#define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
+#define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
+#define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
+#define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos                  (8U)
+#define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
+#define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos                 (9U)
+#define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
+#define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
+#define USART_ISR_CTS_Pos                   (10U)
+#define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
+#define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS Flag */
+#define USART_ISR_RTOF_Pos                  (11U)
+#define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
+#define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Timeout */
+#define USART_ISR_EOBF_Pos                  (12U)
+#define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
+#define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos                   (13U)
+#define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
+#define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
+#define USART_ISR_ABRE_Pos                  (14U)
+#define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
+#define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos                  (15U)
+#define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
+#define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos                  (16U)
+#define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
+#define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
+#define USART_ISR_CMF_Pos                   (17U)
+#define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
+#define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos                  (18U)
+#define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
+#define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos                   (19U)
+#define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
+#define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos                   (20U)
+#define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
+#define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
+#define USART_ISR_TEACK_Pos                 (21U)
+#define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
+#define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos                 (22U)
+#define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
+#define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos                  (23U)
+#define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
+#define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
+#define USART_ISR_RXFF_Pos                  (24U)
+#define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
+#define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
+#define USART_ISR_TCBGT_Pos                 (25U)
+#define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
+#define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
+#define USART_ISR_RXFT_Pos                  (26U)
+#define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
+#define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
+#define USART_ISR_TXFT_Pos                  (27U)
+#define USART_ISR_TXFT_Msk                 (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
+#define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos                  (0U)
+#define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
+#define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos                  (1U)
+#define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
+#define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos                  (2U)
+#define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
+#define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
+#define USART_ICR_ORECF_Pos                 (3U)
+#define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
+#define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos                (4U)
+#define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
+#define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos                (5U)
+#define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
+#define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
+#define USART_ICR_TCCF_Pos                  (6U)
+#define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
+#define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos               (7U)
+#define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos                 (8U)
+#define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
+#define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos                 (9U)
+#define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
+#define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos                 (11U)
+#define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
+#define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos                 (12U)
+#define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
+#define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos                 (13U)
+#define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
+#define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF_Pos                  (17U)
+#define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
+#define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos                  (20U)
+#define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
+#define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ****************/
+#define USART_PRESC_PRESCALER_Pos           (0U)
+#define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_CSRSTDONE_Pos            (29U)
+#define USB_OTG_GRSTCTL_CSRSTDONE_Msk            (0x1UL << USB_OTG_GRSTCTL_CSRSTDONE_Pos) /*!< 0x20000000 */
+#define USB_OTG_GRSTCTL_CSRSTDONE                USB_OTG_GRSTCTL_CSRSTDONE_Msk   /*!< Core soft reset done            */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_HS_GCCFG register  ********************/
+#define USB_OTG_GCCFG_CHGDET_Pos                 (0U)
+#define USB_OTG_GCCFG_CHGDET_Msk                 (0x1U << USB_OTG_GCCFG_CHGDET_Pos)           /*!< 0x00000001 */
+#define USB_OTG_GCCFG_CHGDET                     USB_OTG_GCCFG_CHGDET_Msk                     /*!< Battery Charger Detection */
+#define USB_OTG_GCCFG_FSVPLUS_Pos                (1U)
+#define USB_OTG_GCCFG_FSVPLUS_Msk                (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos)          /*!< 0x00000002 */
+#define USB_OTG_GCCFG_FSVPLUS                    USB_OTG_GCCFG_FSVPLUS_Msk                    /*!< Single-Ended DP2 indicator DP voltage level  */
+#define USB_OTG_GCCFG_FSVMINUS_Pos               (2U)
+#define USB_OTG_GCCFG_FSVMINUS_Msk               0x1U << USB_OTG_GCCFG_FSVMINUS_Pos)         /*!< 0x00000004 */
+#define USB_OTG_GCCFG_FSVMINUS                   USB_OTG_GCCFG_FSVMINUS_Msk                  /*!< Single-Ended DM2 indicator DM voltage level  */
+#define USB_OTG_GCCFG_SESSVLD_Pos                (3U)
+#define USB_OTG_GCCFG_SESSVLD_Msk                (0x1U << USB_OTG_GCCFG_SESSVLD_Pos)          /*!< 0x00000008 */
+#define USB_OTG_GCCFG_SESSVLD                    USB_OTG_GCCFG_SESSVLD_Msk                    /*!< VBUS session valid indicator: Vbus is above VBUS session threshold.  */
+#define USB_OTG_GCCFG_VBUSVLD_Pos                (4U)
+#define USB_OTG_GCCFG_VBUSVLD_Msk                (0x1U << USB_OTG_GCCFG_VBUSVLD_Pos)          /*!< 0x00000010 */
+#define USB_OTG_GCCFG_VBUSVLD                    USB_OTG_GCCFG_VBUSVLD_Msk                    /*!< VBUS session valid indicator: VBUS is above VBUS valid threshold.  */
+#define USB_OTG_GCCFG_H_CDPEN_Pos                (16U)
+#define USB_OTG_GCCFG_H_CDPEN_Msk                (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos)          /*!< 0x00010000 */
+#define USB_OTG_GCCFG_H_CDPEN                    USB_OTG_GCCFG_H_CDPEN_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
+#define USB_OTG_GCCFG_H_CDPDETEN_Pos             (17U)
+#define USB_OTG_GCCFG_H_CDPDETEN_Msk             (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos)       /*!< 0x00020000 */
+#define USB_OTG_GCCFG_H_CDPDETEN                 USB_OTG_GCCFG_H_CDPDETEN_Msk                 /*!< Enable of voltage detector on DP for CDP port  */
+#define USB_OTG_GCCFG_H_VDMSRCEN_Pos             (18U)
+#define USB_OTG_GCCFG_H_VDMSRCEN_Msk             (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos)       /*!< 0x00040000 */
+#define USB_OTG_GCCFG_H_VDMSRCEN                 USB_OTG_GCCFG_H_VDMSRCEN_Msk                 /*!< Enable Voltage source on DM for CDP port */
+#define USB_OTG_GCCFG_DCDETEN_Pos                (19U)
+#define USB_OTG_GCCFG_DCDETEN_Msk                (0x1U << USB_OTG_GCCFG_DCDETEN_Pos)          /*!< 0x00080000 */
+#define USB_OTG_GCCFG_DCDETEN                    USB_OTG_GCCFG_DCDETEN_Msk                    /*!< Data contact detection (DCD) mode enable */
+#define USB_OTG_GCCFG_PDETEN_Pos                 (20U)
+#define USB_OTG_GCCFG_PDETEN_Msk                 (0x1U << USB_OTG_GCCFG_PDETEN_Pos)           /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDETEN                     USB_OTG_GCCFG_PDETEN_Msk                     /*!< Primary detection (PD) mode enable */
+#define USB_OTG_GCCFG_SDETEN_Pos                 (22U)
+#define USB_OTG_GCCFG_SDETEN_Msk                 (0x1U << USB_OTG_GCCFG_SDETEN_Pos)           /*!< 0x00400000 */
+#define USB_OTG_GCCFG_SDETEN                     USB_OTG_GCCFG_SDETEN_Msk                     /*!< Secondary detection (PD) mode enable */
+#define USB_OTG_GCCFG_VBVALOVAL_Pos              (23U)
+#define USB_OTG_GCCFG_VBVALOVAL_Msk              (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos)        /*!< 0x00800000 */
+#define USB_OTG_GCCFG_VBVALOVAL                  USB_OTG_GCCFG_VBVALOVAL_Msk                  /*!< Value of VBUSVLDEXT0 PHY input */
+#define USB_OTG_GCCFG_VBVALEXTOEN_Pos            (24U)
+#define USB_OTG_GCCFG_VBVALEXTOEN_Msk            (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos)      /*!< 0x01000000 */
+#define USB_OTG_GCCFG_VBVALEXTOEN                USB_OTG_GCCFG_VBVALEXTOEN_Msk                /*!< Enables of VBUSVLDEXT0 PHY input override */
+#define USB_OTG_GCCFG_PULLDOWNEN_Pos             (25U)
+#define USB_OTG_GCCFG_PULLDOWNEN_Msk             (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos)       /*!< 0x02000000 */
+#define USB_OTG_GCCFG_PULLDOWNEN                 USB_OTG_GCCFG_PULLDOWNEN_Msk                 /*!< Enables Host pulldown resistors, used when ID PAD is disabled */
+#define USB_OTG_GCCFG_FORCEBCMODE_Pos            (26U)
+#define USB_OTG_GCCFG_FORCEBCMODE_Msk            (0x1U << USB_OTG_GCCFG_FORCEBCMODE_Pos)      /*!< 0x04000000 */
+#define USB_OTG_GCCFG_FORCEBCMODE                USB_OTG_GCCFG_FORCEBCMODE_Msk                /*!< Force Battery charging (BC) mode */
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Pos           (28U)
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Msk           (0x1U << USB_OTG_GCCFG_IDPULLUP_DIS_Pos)      /*!< 0x10000000 */
+#define USB_OTG_GCCFG_IDPULLUP_DIS               USB_OTG_GCCFG_IDPULLUP_DIS_Msk                /*!< Analog ID Input Sample Disable: disable sampling on the analog ID line */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL1 register  ********************/
+#define USB_OTG_PCGCCTL1_GATEEN_Pos               (0U)
+#define USB_OTG_PCGCCTL1_GATEEN_Msk               (0x1UL << USB_OTG_PCGCCTL1_GATEEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL1_GATEEN                   USB_OTG_PCGCCTL1_GATEEN_Msk   /*!< Enable Active Clock Gating */
+#define USB_OTG_PCGCCTL1_COUNTER_Pos              (1U)
+#define USB_OTG_PCGCCTL1_COUNTER_Msk              (0x3UL << USB_OTG_PCGCCTL1_COUNTER_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL1_COUNTER                  USB_OTG_PCGCCTL1_COUNTER_Msk   /*!< Count to Gate Clock */
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Pos            (3U)
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Msk            (0x1UL << USB_OTG_PCGCCTL1_RAMGATEEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL1_RAMGATEEN                USB_OTG_PCGCCTL1_RAMGATEEN_Msk   /*!< RAM Clock Gating Enable */
+
+/*!< USB registers base address */
+#define USB_OTG_GLOBAL_BASE                       (0x000UL)
+#define USB_OTG_DEVICE_BASE                       (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE                  (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE                 (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                       (0x20UL)
+#define USB_OTG_HOST_BASE                         (0x400UL)
+#define USB_OTG_HOST_PORT_BASE                    (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE                 (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE                 (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                      (0xE00UL)
+#define USB_OTG_FIFO_BASE                         (0x1000UL)
+#define USB_OTG_FIFO_SIZE                         (0x1000UL)
+#define USB_OTG_HS_EP_NBR                         (9UL)            /*!< Number of USB HS Device endpoints */
+#define USB_OTG_HS_CH_NBR                         (16UL)           /*!< Number of USB HS Host channels */
+
+/********************  Bit definition for USB_USBPHYC_CR register  ********************/
+#define USB_USBPHYC_CR_RETENABLEN1_Pos          (0U)
+#define USB_USBPHYC_CR_RETENABLEN1_Msk          (0x1UL << USB_USBPHYC_CR_RETENABLEN1_Pos)    /*!< 0x00000001 */
+#define USB_USBPHYC_CR_RETENABLEN1              USB_USBPHYC_CR_RETENABLEN1_Msk               /*!< Retention mode enable */
+#define USB_USBPHYC_CR_AUTORSMENB1_Pos          (1U)
+#define USB_USBPHYC_CR_AUTORSMENB1_Msk          (0x1UL << USB_USBPHYC_CR_AUTORSMENB1_Pos)    /*!< 0x00000002 */
+#define USB_USBPHYC_CR_AUTORSMENB1              USB_USBPHYC_CR_AUTORSMENB1_Msk               /*!< Auto-resume mode enable */
+#define USB_USBPHYC_CR_CMN_Pos                  (2U)
+#define USB_USBPHYC_CR_CMN_Msk                  (0x1UL << USB_USBPHYC_CR_CMN_Pos)            /*!< 0x00000004 */
+#define USB_USBPHYC_CR_CMN                      USB_USBPHYC_CR_CMN_Msk                       /*!< Controls the power down of analog blocks during Suspend and Sleep */
+#define USB_USBPHYC_CR_FSEL_Pos                 (4U)
+#define USB_USBPHYC_CR_FSEL_Msk                 (0x7UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000070 */
+#define USB_USBPHYC_CR_FSEL                     USB_USBPHYC_CR_FSEL_Msk                      /*!< Frequency selection */
+#define USB_USBPHYC_CR_FSEL_0                   (0x1UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000010 */
+#define USB_USBPHYC_CR_FSEL_1                   (0x2UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000020 */
+#define USB_USBPHYC_CR_FSEL_2                   (0x3UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000040 */
+#define USB_USBPHYC_CR_OTGDISABLE0_Pos          (16U)
+#define USB_USBPHYC_CR_OTGDISABLE0_Msk          (0x1UL << USB_USBPHYC_CR_OTGDISABLE0_Pos)    /*!< 0x00010000 */
+#define USB_USBPHYC_CR_OTGDISABLE0              USB_USBPHYC_CR_OTGDISABLE0_Msk               /*!< OTG disable 0 */
+#define USB_USBPHYC_CR_DRVVBUS0_Pos             (17U)
+#define USB_USBPHYC_CR_DRVVBUS0_Msk             (0x1UL << USB_USBPHYC_CR_DRVVBUS0_Pos)       /*!< 0x00020000 */
+#define USB_USBPHYC_CR_DRVVBUS0                 USB_USBPHYC_CR_DRVVBUS0_Msk                  /*!< Drive VBUS 0 */
+#define USB_USBPHYC_CR_SELOTGDBG_Pos            (31U)
+#define USB_USBPHYC_CR_SELOTGDBG_Msk            (0x1UL << USB_USBPHYC_CR_SELOTGDBG_Pos)      /*!< 0x80000000 */
+#define USB_USBPHYC_CR_SELOTGDBG                USB_USBPHYC_CR_SELOTGDBG_Msk                 /*!< Select HS PHY debug port */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)
+#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)
+#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos     (3U)
+#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos     (4U)
+#define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
+#define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000040 */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos                (0U)
+#define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos                       (0U)
+#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
+#define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
+#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
+#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
+#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
+#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
+#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
+#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
+#define WWDG_CR_WDGA_Pos                    (7U)
+#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
+#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos                      (0U)
+#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
+#define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
+#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
+#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
+#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
+#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
+#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
+#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
+#define WWDG_CFR_EWI_Pos                    (9U)
+#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
+#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
+#define WWDG_CFR_WDGTB_Pos                  (11U)
+#define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos                    (0U)
+#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
+#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Extended-SPI Interface (XSPI)                         */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for XSPI_CR register  *******************/
+#define XSPI_CR_EN_Pos                   (0U)
+#define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)            /*!< 0x00000001 */
+#define XSPI_CR_EN                       XSPI_CR_EN_Msk                       /*!< Enable */
+#define XSPI_CR_ABORT_Pos                (1U)
+#define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
+#define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define XSPI_CR_DMAEN_Pos                (2U)
+#define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
+#define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define XSPI_CR_TCEN_Pos                 (3U)
+#define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
+#define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define XSPI_CR_DMM_Pos                  (6U)
+#define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)           /*!< 0x00000040 */
+#define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                      /*!< Dual Memory Mode */
+#define XSPI_CR_FSEL_Pos                 (7U)
+#define XSPI_CR_FSEL_Msk                 (0x1UL << XSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
+#define XSPI_CR_FSEL                     XSPI_CR_FSEL_Msk                     /*!< Flash Select */
+#define XSPI_CR_FTHRES_Pos               (8U)
+#define XSPI_CR_FTHRES_Msk               (0x3FUL << XSPI_CR_FTHRES_Pos)       /*!< 0x00003F00 */
+#define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */
+#define XSPI_CR_TEIE_Pos                 (16U)
+#define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
+#define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define XSPI_CR_TCIE_Pos                 (17U)
+#define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
+#define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define XSPI_CR_FTIE_Pos                 (18U)
+#define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
+#define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define XSPI_CR_SMIE_Pos                 (19U)
+#define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
+#define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define XSPI_CR_TOIE_Pos                 (20U)
+#define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
+#define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define XSPI_CR_APMS_Pos                 (22U)
+#define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)          /*!< 0x00400000 */
+#define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */
+#define XSPI_CR_PMM_Pos                  (23U)
+#define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)           /*!< 0x00800000 */
+#define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define XSPI_CR_CSSEL_Pos                (24U)
+#define XSPI_CR_CSSEL_Msk                (0x1UL << XSPI_CR_CSSEL_Pos)         /*!< 0x01000000 */
+#define XSPI_CR_CSSEL                    XSPI_CR_CSSEL_Msk                    /*!< Chip Select Selection */
+#define XSPI_CR_NOPREF_Pos               (25U)
+#define XSPI_CR_NOPREF_Msk               (0x1UL << XSPI_CR_NOPREF_Pos)        /*!< 0x02000000 */
+#define XSPI_CR_NOPREF                   XSPI_CR_NOPREF_Msk                   /*!< No Prefetch Data */
+#define XSPI_CR_NOPREF_AXI_Pos           (26U)
+#define XSPI_CR_NOPREF_AXI_Msk           (0x1UL << XSPI_CR_NOPREF_AXI_Pos)    /*!< 0x04000000 */
+#define XSPI_CR_NOPREF_AXI               XSPI_CR_NOPREF_AXI_Msk               /*!< No Prefetch For Signaled AXI Transactions */
+#define XSPI_CR_FMODE_Pos                (28U)
+#define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)         /*!< 0x30000000 */
+#define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                    /*!< Functional Mode */
+#define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)         /*!< 0x10000000 */
+#define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)         /*!< 0x20000000 */
+#define XSPI_CR_MSEL_Pos                 (30U)
+#define XSPI_CR_MSEL_Msk                 (0x3UL << XSPI_CR_MSEL_Pos)          /*!< 0xC0000000 */
+#define XSPI_CR_MSEL                     XSPI_CR_MSEL_Msk                     /*!< Memory Select */
+#define XSPI_CR_MSEL_0                   (0x1UL << XSPI_CR_MSEL_Pos)          /*!< 0x40000000 */
+#define XSPI_CR_MSEL_1                   (0x2UL << XSPI_CR_MSEL_Pos)          /*!< 0x80000000 */
+
+/****************  Bit definition for XSPI_DCR1 register  ******************/
+#define XSPI_DCR1_CKMODE_Pos             (0U)
+#define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */
+#define XSPI_DCR1_FRCK_Pos               (1U)
+#define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)        /*!< 0x00000002 */
+#define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */
+#define XSPI_DCR1_CSHT_Pos               (8U)
+#define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)       /*!< 0x00003F00 */
+#define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
+#define XSPI_DCR1_DEVSIZE_Pos            (16U)
+#define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */
+#define XSPI_DCR1_EXTENDMEM_Pos          (21U)
+#define XSPI_DCR1_EXTENDMEM_Msk          (0x1UL << XSPI_DCR1_EXTENDMEM_Pos)   /*!< 0x00200000 */
+#define XSPI_DCR1_EXTENDMEM              XSPI_DCR1_EXTENDMEM_Msk              /*!< Extended Memory Support */
+#define XSPI_DCR1_MTYP_Pos               (24U)
+#define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x07000000 */
+#define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                   /*!< Memory Type */
+#define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x01000000 */
+#define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x02000000 */
+#define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x04000000 */
+
+/****************  Bit definition for XSPI_DCR2 register  ******************/
+#define XSPI_DCR2_PRESCALER_Pos          (0U)
+#define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)  /*!< 0x000000FF */
+#define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */
+#define XSPI_DCR2_WRAPSIZE_Pos           (16U)
+#define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00070000 */
+#define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */
+#define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00010000 */
+#define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00020000 */
+#define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00040000 */
+
+/****************  Bit definition for XSPI_DCR3 register  ******************/
+#define XSPI_DCR3_MAXTRAN_Pos            (0U)
+#define XSPI_DCR3_MAXTRAN_Msk            (0xFFUL << XSPI_DCR3_MAXTRAN_Pos)    /*!< 0x000000FF */
+#define XSPI_DCR3_MAXTRAN                XSPI_DCR3_MAXTRAN_Msk                /*!< Maximum transfer */
+#define XSPI_DCR3_CSBOUND_Pos            (16U)
+#define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                /*!< Maximum transfer */
+
+/****************  Bit definition for XSPI_DCR4 register  ******************/
+#define XSPI_DCR4_REFRESH_Pos            (0U)
+#define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */
+
+/*****************  Bit definition for XSPI_SR register  *******************/
+#define XSPI_SR_TEF_Pos                  (0U)
+#define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)           /*!< 0x00000001 */
+#define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define XSPI_SR_TCF_Pos                  (1U)
+#define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)           /*!< 0x00000002 */
+#define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define XSPI_SR_FTF_Pos                  (2U)
+#define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)           /*!< 0x00000004 */
+#define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */
+#define XSPI_SR_SMF_Pos                  (3U)
+#define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)           /*!< 0x00000008 */
+#define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define XSPI_SR_TOF_Pos                  (4U)
+#define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)           /*!< 0x00000010 */
+#define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define XSPI_SR_BUSY_Pos                 (5U)
+#define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
+#define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                     /*!< Busy */
+#define XSPI_SR_FLEVEL_Pos               (8U)
+#define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)       /*!< 0x00007F00 */
+#define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */
+
+/****************  Bit definition for XSPI_FCR register  *******************/
+#define XSPI_FCR_CTEF_Pos                (0U)
+#define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
+#define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define XSPI_FCR_CTCF_Pos                (1U)
+#define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
+#define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define XSPI_FCR_CSMF_Pos                (3U)
+#define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
+#define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define XSPI_FCR_CTOF_Pos                (4U)
+#define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
+#define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/****************  Bit definition for XSPI_DLR register  *******************/
+#define XSPI_DLR_DL_Pos                  (0U)
+#define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
+#define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                      /*!< Data Length */
+
+/*****************  Bit definition for XSPI_AR register  *******************/
+#define XSPI_AR_ADDRESS_Pos              (0U)
+#define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                  /*!< Address */
+
+/*****************  Bit definition for XSPI_DR register  *******************/
+#define XSPI_DR_DATA_Pos                 (0U)
+#define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
+#define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                     /*!< Data */
+
+/***************  Bit definition for XSPI_PSMKR register  ******************/
+#define XSPI_PSMKR_MASK_Pos              (0U)
+#define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                  /*!< Status mask */
+
+/***************  Bit definition for XSPI_PSMAR register  ******************/
+#define XSPI_PSMAR_MATCH_Pos             (0U)
+#define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                 /*!< Status match */
+
+/****************  Bit definition for XSPI_PIR register  *******************/
+#define XSPI_PIR_INTERVAL_Pos            (0U)
+#define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
+#define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */
+
+/****************  Bit definition for XSPI_CCR register  *******************/
+#define XSPI_CCR_IMODE_Pos               (0U)
+#define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000007 */
+#define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */
+#define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000001 */
+#define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000002 */
+#define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000004 */
+#define XSPI_CCR_IDTR_Pos                (3U)
+#define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)         /*!< 0x00000008 */
+#define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */
+#define XSPI_CCR_ISIZE_Pos               (4U)
+#define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000030 */
+#define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */
+#define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000010 */
+#define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000020 */
+#define XSPI_CCR_ADMODE_Pos              (8U)
+#define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000700 */
+#define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                  /*!< Address Mode */
+#define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000100 */
+#define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000200 */
+#define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define XSPI_CCR_ADDTR_Pos               (11U)
+#define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)        /*!< 0x00000800 */
+#define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */
+#define XSPI_CCR_ADSIZE_Pos              (12U)
+#define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                  /*!< Address Size */
+#define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define XSPI_CCR_ABMODE_Pos              (16U)
+#define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00070000 */
+#define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */
+#define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00010000 */
+#define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00020000 */
+#define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00040000 */
+#define XSPI_CCR_ABDTR_Pos               (19U)
+#define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)        /*!< 0x00080000 */
+#define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_CCR_ABSIZE_Pos              (20U)
+#define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00300000 */
+#define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */
+#define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00100000 */
+#define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00200000 */
+#define XSPI_CCR_DMODE_Pos               (24U)
+#define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)        /*!< 0x07000000 */
+#define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                   /*!< Data Mode */
+#define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)        /*!< 0x04000000 */
+#define XSPI_CCR_DDTR_Pos                (27U)
+#define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)         /*!< 0x08000000 */
+#define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */
+#define XSPI_CCR_DQSE_Pos                (29U)
+#define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)         /*!< 0x20000000 */
+#define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                    /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_TCR register  *******************/
+#define XSPI_TCR_DCYC_Pos                (0U)
+#define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)        /*!< 0x0000001F */
+#define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */
+#define XSPI_TCR_DHQC_Pos                (28U)
+#define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)         /*!< 0x10000000 */
+#define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */
+#define XSPI_TCR_SSHIFT_Pos              (30U)
+#define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)       /*!< 0x40000000 */
+#define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_IR register  *******************/
+#define XSPI_IR_INSTRUCTION_Pos          (0U)
+#define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk              /*!< Instruction */
+
+/****************  Bit definition for XSPI_ABR register  *******************/
+#define XSPI_ABR_ALTERNATE_Pos           (0U)
+#define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_LPTR register  ******************/
+#define XSPI_LPTR_TIMEOUT_Pos            (0U)
+#define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
+#define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */
+
+/****************  Bit definition for XSPI_WPCCR register  *******************/
+#define XSPI_WPCCR_IMODE_Pos             (0U)
+#define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000007 */
+#define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */
+#define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000002 */
+#define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000004 */
+#define XSPI_WPCCR_IDTR_Pos              (3U)
+#define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)       /*!< 0x00000008 */
+#define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */
+#define XSPI_WPCCR_ISIZE_Pos             (4U)
+#define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000030 */
+#define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */
+#define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000010 */
+#define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000020 */
+#define XSPI_WPCCR_ADMODE_Pos            (8U)
+#define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000700 */
+#define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */
+#define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000100 */
+#define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000200 */
+#define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000400 */
+#define XSPI_WPCCR_ADDTR_Pos             (11U)
+#define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)      /*!< 0x00000800 */
+#define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */
+#define XSPI_WPCCR_ADSIZE_Pos            (12U)
+#define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00003000 */
+#define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */
+#define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00001000 */
+#define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00002000 */
+#define XSPI_WPCCR_ABMODE_Pos            (16U)
+#define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00070000 */
+#define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */
+#define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00010000 */
+#define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00020000 */
+#define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00040000 */
+#define XSPI_WPCCR_ABDTR_Pos             (19U)
+#define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)      /*!< 0x00080000 */
+#define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WPCCR_ABSIZE_Pos            (20U)
+#define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00300000 */
+#define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */
+#define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00100000 */
+#define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00200000 */
+#define XSPI_WPCCR_DMODE_Pos             (24U)
+#define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x07000000 */
+#define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */
+#define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x01000000 */
+#define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x02000000 */
+#define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x04000000 */
+#define XSPI_WPCCR_DDTR_Pos              (27U)
+#define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)       /*!< 0x08000000 */
+#define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */
+#define XSPI_WPCCR_DQSE_Pos              (29U)
+#define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)       /*!< 0x20000000 */
+#define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WPTCR register  *******************/
+#define XSPI_WPTCR_DCYC_Pos              (0U)
+#define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)      /*!< 0x0000001F */
+#define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */
+#define XSPI_WPTCR_DHQC_Pos              (28U)
+#define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)       /*!< 0x10000000 */
+#define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */
+#define XSPI_WPTCR_SSHIFT_Pos            (30U)
+#define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)     /*!< 0x40000000 */
+#define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_WPIR register  *******************/
+#define XSPI_WPIR_INSTRUCTION_Pos        (0U)
+#define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */
+
+/****************  Bit definition for XSPI_WPABR register  *******************/
+#define XSPI_WPABR_ALTERNATE_Pos         (0U)
+#define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_WCCR register  ******************/
+#define XSPI_WCCR_IMODE_Pos              (0U)
+#define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000007 */
+#define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */
+#define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000001 */
+#define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000002 */
+#define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000004 */
+#define XSPI_WCCR_IDTR_Pos               (3U)
+#define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)        /*!< 0x00000008 */
+#define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */
+#define XSPI_WCCR_ISIZE_Pos              (4U)
+#define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000030 */
+#define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */
+#define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000010 */
+#define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000020 */
+#define XSPI_WCCR_ADMODE_Pos             (8U)
+#define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000700 */
+#define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */
+#define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000100 */
+#define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000200 */
+#define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000400 */
+#define XSPI_WCCR_ADDTR_Pos              (11U)
+#define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)       /*!< 0x00000800 */
+#define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */
+#define XSPI_WCCR_ADSIZE_Pos             (12U)
+#define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00003000 */
+#define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */
+#define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00001000 */
+#define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00002000 */
+#define XSPI_WCCR_ABMODE_Pos             (16U)
+#define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00070000 */
+#define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */
+#define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00010000 */
+#define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00020000 */
+#define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00040000 */
+#define XSPI_WCCR_ABDTR_Pos              (19U)
+#define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)       /*!< 0x00080000 */
+#define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WCCR_ABSIZE_Pos             (20U)
+#define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00300000 */
+#define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */
+#define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00100000 */
+#define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00200000 */
+#define XSPI_WCCR_DMODE_Pos              (24U)
+#define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x07000000 */
+#define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                  /*!< Data Mode */
+#define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x01000000 */
+#define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x02000000 */
+#define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x04000000 */
+#define XSPI_WCCR_DDTR_Pos               (27U)
+#define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)        /*!< 0x08000000 */
+#define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */
+#define XSPI_WCCR_DQSE_Pos               (29U)
+#define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)        /*!< 0x20000000 */
+#define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WTCR register  ******************/
+#define XSPI_WTCR_DCYC_Pos               (0U)
+#define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)       /*!< 0x0000001F */
+#define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */
+
+/****************  Bit definition for XSPI_WIR register  *******************/
+#define XSPI_WIR_INSTRUCTION_Pos         (0U)
+#define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */
+
+/****************  Bit definition for XSPI_WABR register  ******************/
+#define XSPI_WABR_ALTERNATE_Pos          (0U)
+#define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_HLCR register  ******************/
+#define XSPI_HLCR_LM_Pos                 (0U)
+#define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)          /*!< 0x00000001 */
+#define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                     /*!< Latency Mode */
+#define XSPI_HLCR_WZL_Pos                (1U)
+#define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)         /*!< 0x00000002 */
+#define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */
+#define XSPI_HLCR_TACC_Pos               (8U)
+#define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)       /*!< 0x0000FF00 */
+#define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                   /*!< Access Time */
+#define XSPI_HLCR_TRWR_Pos               (16U)
+#define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)       /*!< 0x00FF0000 */
+#define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */
+
+/****************  Bit definition for XSPI_CALFCR register  ****************/
+#define XSPI_CALFCR_FINE_Pos             (0U)
+#define XSPI_CALFCR_FINE_Msk             (0x7FUL << XSPI_CALFCR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALFCR_FINE                 XSPI_CALFCR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALFCR_COARSE_Pos           (16U)
+#define XSPI_CALFCR_COARSE_Msk           (0x1FUL << XSPI_CALFCR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALFCR_COARSE               XSPI_CALFCR_COARSE_Msk               /*!< Coarse Calibration */
+#define XSPI_CALFCR_CALMAX_Pos           (31U)
+#define XSPI_CALFCR_CALMAX_Msk           (0x1UL << XSPI_CALFCR_CALMAX_Pos)    /*!< 0x80000000 */
+#define XSPI_CALFCR_CALMAX               XSPI_CALFCR_CALMAX_Msk               /*!< Max Value */
+
+/****************  Bit definition for XSPI_CALMR register  *****************/
+#define XSPI_CALMR_FINE_Pos              (0U)
+#define XSPI_CALMR_FINE_Msk              (0x7FUL << XSPI_CALMR_FINE_Pos)      /*!< 0x0000007F */
+#define XSPI_CALMR_FINE                  XSPI_CALMR_FINE_Msk                  /*!< Fine Calibration */
+#define XSPI_CALMR_COARSE_Pos            (16U)
+#define XSPI_CALMR_COARSE_Msk            (0x1FUL << XSPI_CALMR_COARSE_Pos)    /*!< 0x001F0000 */
+#define XSPI_CALMR_COARSE                XSPI_CALMR_COARSE_Msk                /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSOR register  ****************/
+#define XSPI_CALSOR_FINE_Pos             (0U)
+#define XSPI_CALSOR_FINE_Msk             (0x7FUL << XSPI_CALSOR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSOR_FINE                 XSPI_CALSOR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSOR_COARSE_Pos           (16U)
+#define XSPI_CALSOR_COARSE_Msk           (0x1FUL << XSPI_CALSOR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSOR_COARSE               XSPI_CALSOR_COARSE_Msk               /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSIR register  ****************/
+#define XSPI_CALSIR_FINE_Pos             (0U)
+#define XSPI_CALSIR_FINE_Msk             (0x7FUL << XSPI_CALSIR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSIR_FINE                 XSPI_CALSIR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSIR_COARSE_Pos           (16U)
+#define XSPI_CALSIR_COARSE_Msk           (0x1FUL << XSPI_CALSIR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSIR_COARSE               XSPI_CALSIR_COARSE_Msk               /*!< Coarse Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 XSPIM                                      */
+/*                                                                            */
+/******************************************************************************/
+/***************  Bit definition for XSPIM_CR register  ********************/
+#define XSPIM_CR_MUXEN_Pos               (0U)
+#define XSPIM_CR_MUXEN_Msk               (0x1UL << XSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */
+#define XSPIM_CR_MUXEN                   XSPIM_CR_MUXEN_Msk                   /*!< Multiplexed Mode Enable */
+#define XSPIM_CR_MODE_Pos                (1U)
+#define XSPIM_CR_MODE_Msk                (0x1UL << XSPIM_CR_MODE_Pos)         /*!< 0x00000002 */
+#define XSPIM_CR_MODE                    XSPIM_CR_MODE_Msk                    /*!< Multiplexing Mode */
+#define XSPIM_CR_CSSEL_OVR_EN_Pos        (4U)
+#define XSPIM_CR_CSSEL_OVR_EN_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_EN_Pos) /*!< 0x00000010 */
+#define XSPIM_CR_CSSEL_OVR_EN            XSPIM_CR_CSSEL_OVR_EN_Msk            /*!< Chip Select Selector Override Enable */
+#define XSPIM_CR_CSSEL_OVR_O1_Pos        (5U)
+#define XSPIM_CR_CSSEL_OVR_O1_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O1_Pos) /*!< 0x00000020 */
+#define XSPIM_CR_CSSEL_OVR_O1            XSPIM_CR_CSSEL_OVR_O1_Msk            /*!< Chip Select Selector Override Setting For XSPI1 */
+#define XSPIM_CR_CSSEL_OVR_O2_Pos        (6U)
+#define XSPIM_CR_CSSEL_OVR_O2_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O2_Pos) /*!< 0x00000040 */
+#define XSPIM_CR_CSSEL_OVR_O2            XSPIM_CR_CSSEL_OVR_O2_Msk            /*!< Chip Select Selector Override Setting For XSPI2 */
+#define XSPIM_CR_REQ2ACK_TIME_Pos        (16U)
+#define XSPIM_CR_REQ2ACK_TIME_Msk        (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
+#define XSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK Time */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Exported_macros
+  * @{
+  */
+#if defined (CPU_IN_SECURE_STATE)
+/* Instances allowed from Secure state */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_S) || ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_S) || ((INSTANCE) == ADC12_COMMON_NS))
+
+/****************************** BSEC Instances *******************************/
+#define IS_BSEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == BSEC_S)
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_S) || ((INSTANCE) == CRC_NS))
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMI_S) || ((INSTANCE) == DCMI_NS))
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMIPP_S) || ((INSTANCE) == DCMIPP_NS))
+
+/********************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_S) || ((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_S) || ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S)  || ((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_S)  || ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_S)  || ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_S)  || ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA2D_S) || ((INSTANCE) == DMA2D_NS))
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DTS_S) || ((INSTANCE) == DTS_NS))
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ETH1_S) || ((INSTANCE) == ETH1_NS))
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_S) || ((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_S) || ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_S) || ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN_CONFIG_S) || ((INSTANCE) == FDCAN_CONFIG_NS))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_S)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_S) || ((INSTANCE) == GFXMMU_NS))
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXTIM_S) || ((INSTANCE) == GFXTIM_NS))
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_S) || ((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_S) || ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_S) || ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_S) || ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_S) || ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_S) || ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_S) || ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_S) || ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_S) || ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_S) || ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_S) || ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_S) || ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPU2D_BASE_S) || ((INSTANCE) == GPU2D_BASE_NS))
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_S) || ((INSTANCE) == I3C1_NS) || \
+                                       ((INSTANCE) == I3C2_S) || ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_S) || ((INSTANCE) == IWDG_NS))
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == JPEG_S) || ((INSTANCE) == JPEG_NS))
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LTDC_S) || ((INSTANCE) == LTDC_NS))
+
+/******************************* MCE Instances *******************************/
+#define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_S) || ((INSTANCE) == MCE1_NS) || \
+                                       ((INSTANCE) == MCE2_S) || ((INSTANCE) == MCE2_NS) || \
+                                       ((INSTANCE) == MCE3_S) || ((INSTANCE) == MCE3_NS) || \
+                                       ((INSTANCE) == MCE4_S) || ((INSTANCE) == MCE4_NS))
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_S) || ((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_S) || ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_S) || ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_S) || ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_S) || ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_S) || ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_S) || ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDIOS_S) || ((INSTANCE) == MDIOS_NS))
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_S) || ((INSTANCE) == PKA_NS))
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PSSI_S) || ((INSTANCE) == PSSI_NS))
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM1_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM2_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM1_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_S)    || ((INSTANCE) == RAMCFG_BKPSRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)    || ((INSTANCE) == RAMCFG_FLEXRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_S)   || ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_S)  || ((INSTANCE) == RAMCFG_BKPSRAM_NS)  || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)  || ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_S) || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_S) || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_S) || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_S) || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_S) || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_S) || ((INSTANCE) == RNG_NS))
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_S) || ((INSTANCE) == RTC_NS))
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_S) || ((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_S) || ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_S) || ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_S) || ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_S) || ((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_S) || ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPDIFRX_S) || ((INSTANCE) == SPDIFRX_NS))
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_S) || ((INSTANCE) == UCPD1_NS))
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_S) || ((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_S) || ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                        ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS) || \
+                                         ((INSTANCE) == TIM18_S)  || ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                               ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                               ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                               ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                          ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                          ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                          ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                          ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                          ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                          ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                          ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                          ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     (((INSTANCE) == TIM15_S)   &&                               \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)                  \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                      ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                      ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                      ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                      ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                      ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_S)  || ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_S)  || ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_S) || ((INSTANCE) == WWDG_NS))
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_S) || ((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_S) || ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_S) || ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPIM_S) || ((INSTANCE) == XSPIM_NS))
+
+#else
+/* Instances allowed from Non-Secure state - only alias Non-Secure */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS)
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI_NS)
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP_NS)
+
+/******************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_NS) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_NS) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D_NS)
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS_NS)
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH1_NS)
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_NS)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU_NS)
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXTIM_NS)
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPU2D_BASE_NS)
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
+                                      ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS)
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == JPEG_NS)
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC_NS)
+
+/******************************* MCE Instances *******************************/
+#define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_NS) || \
+                                       ((INSTANCE) == MCE2_NS) || \
+                                       ((INSTANCE) == MCE3_NS) || \
+                                       ((INSTANCE) == MCE4_NS))
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS_NS)
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI_NS)
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS)
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS)
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX_NS)
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_NS)
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                        ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || \
+                                               ((INSTANCE) == TIM3_NS)  || \
+                                               ((INSTANCE) == TIM4_NS)  || \
+                                               ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || \
+                                          ((INSTANCE) == TIM2_NS)   || \
+                                          ((INSTANCE) == TIM3_NS)   || \
+                                          ((INSTANCE) == TIM4_NS)   || \
+                                          ((INSTANCE) == TIM5_NS)   || \
+                                          ((INSTANCE) == TIM8_NS)   || \
+                                          ((INSTANCE) == TIM15_NS)  || \
+                                          ((INSTANCE) == TIM16_NS)  || \
+                                          ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM9_NS)   &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM10_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM11_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM12_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM13_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM14_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM8_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM15_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM16_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM17_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                      ((INSTANCE) == TIM2_NS)  || \
+                                                      ((INSTANCE) == TIM3_NS)  || \
+                                                      ((INSTANCE) == TIM4_NS)  || \
+                                                      ((INSTANCE) == TIM5_NS)  || \
+                                                      ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS)
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == XSPIM_NS)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Exported_macros */
+
+/** @} */ /* End of group STM32N655xx */
+
+/** @} */ /* End of group ST */
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* STM32N655xx_H */
diff --git a/stm32cube/stm32n6xx/soc/stm32n657xx.h b/stm32cube/stm32n6xx/soc/stm32n657xx.h
new file mode 100644
index 000000000..a6da42ca0
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/stm32n657xx.h
@@ -0,0 +1,43092 @@
+/**
+  ******************************************************************************
+  * @file    stm32n657xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N657xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+#ifndef STM32N657xx_H
+#define STM32N657xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup ST
+  * @{
+  */
+
+/** @addtogroup STM32N657xx
+  * @{
+  */
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+typedef enum
+{
+/* ======================================  ARM Cortex-M55 Specific Interrupt Numbers  ======================================== */
+  NonMaskableInt_IRQn        = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted                         */
+  HardFault_IRQn             = -13,    /*!< -13 Hard Fault, all classes of Fault                                               */
+  MemoryManagement_IRQn      = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match       */
+  BusFault_IRQn              = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn            = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition                  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  SecureFault_IRQn           = -9,     /*!< -9  Secure Fault                                                                   */
+#endif
+  SVCall_IRQn                = -5,     /*!< -5  System Service Call via SVC instruction                                        */
+  DebugMonitor_IRQn          = -4,     /*!< -4  Debug Monitor                                                                  */
+  PendSV_IRQn                = -2,     /*!< -2  Pendable request for system service                                            */
+  SysTick_IRQn               = -1,     /*!< -1  System Tick Timer                                                              */
+
+/* ======================================  STM32N6xx Specific Interrupt Numbers  ============================================= */
+  PVD_PVM_IRQn               = 0,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection                                */
+  DTS_IRQn                   = 2,      /*!< Thermal Sensor interruption                                                        */
+  RCC_IRQn                   = 3,      /*!< RCC non-secure global interrupts through EXTI Line detection                       */
+  LOCKUP_IRQn                = 4,      /*!< LOCKUP / (no Overstack in CM55)                                                    */
+  CACHE_ECC_IRQn             = 5,      /*!< Error ECC cache interrupt                                                          */
+  TCM_ECC_IRQn               = 6,      /*!< TCM ECC interrupts                                                                 */
+  BKP_ECC_IRQn               = 7,      /*!< Backup RAM Interrupts                                                              */
+  FPU_IRQn                   = 8,      /*!< FPU interrupt                                                                      */
+  RTC_S_IRQn                 = 10,     /*!< RTC secure interrupts through EXTI Line detection                                  */
+  TAMP_IRQn                  = 11,     /*!< Tamper secure and non-secure interrupts through EXTI Line detection                */
+  RIFSC_TAMPER_IRQn          = 12,     /*!< RIF Tamper interrupts                                                              */
+  IAC_IRQn                   = 13,     /*!< IAC interrupt                                                                      */
+  RCC_S_IRQn                 = 14,     /*!< RCC secure global interrupts through EXTI Line detection                           */
+  RTC_IRQn                   = 16,     /*!< RTC non-secure interrupts through EXTI Line detection                              */
+  IWDG_IRQn                  = 18,     /*!< Internal Watchdog interrupt                                                        */
+  WWDG_IRQn                  = 19,     /*!< Window Watchdog interrupt                                                          */
+  EXTI0_IRQn                 = 20,     /*!< EXTI Line0 interrupt                                                               */
+  EXTI1_IRQn                 = 21,     /*!< EXTI Line1 interrupt                                                               */
+  EXTI2_IRQn                 = 22,     /*!< EXTI Line2 interrupt                                                               */
+  EXTI3_IRQn                 = 23,     /*!< EXTI Line3 interrupt                                                               */
+  EXTI4_IRQn                 = 24,     /*!< EXTI Line4 interrupt                                                               */
+  EXTI5_IRQn                 = 25,     /*!< EXTI Line5 interrupt                                                               */
+  EXTI6_IRQn                 = 26,     /*!< EXTI Line6 interrupt                                                               */
+  EXTI7_IRQn                 = 27,     /*!< EXTI Line7 interrupt                                                               */
+  EXTI8_IRQn                 = 28,     /*!< EXTI Line8 interrupt                                                               */
+  EXTI9_IRQn                 = 29,     /*!< EXTI Line9 interrupt                                                               */
+  EXTI10_IRQn                = 30,     /*!< EXTI Line10 interrupt                                                              */
+  EXTI11_IRQn                = 31,     /*!< EXTI Line11 interrupt                                                              */
+  EXTI12_IRQn                = 32,     /*!< EXTI Line12 interrupt                                                              */
+  EXTI13_IRQn                = 33,     /*!< EXTI Line13 interrupt                                                              */
+  EXTI14_IRQn                = 34,     /*!< EXTI Line14 interrupt                                                              */
+  EXTI15_IRQn                = 35,     /*!< EXTI Line15 interrupt                                                              */
+  SAES_IRQn                  = 36,     /*!< SAES interrupt                                                                     */
+  CRYP_IRQn                  = 37,     /*!< CRYP interrupt                                                                     */
+  PKA_IRQn                   = 38,     /*!< PKA interrupt                                                                      */
+  HASH_IRQn                  = 39,     /*!< HASH interrupt                                                                     */
+  RNG_IRQn                   = 40,     /*!< RNG global interrupt                                                               */
+  MCE1_IRQn                  = 42,     /*!< MCE1 global interrupt                                                              */
+  MCE2_IRQn                  = 43,     /*!< MCE2 global interrupt                                                              */
+  MCE3_IRQn                  = 44,     /*!< MCE3 global interrupt                                                              */
+  MCE4_IRQn                  = 45,     /*!< MCE4 global interrupt                                                              */
+  ADC1_2_IRQn                = 46,     /*!< ADC1 & ADC2 interrupt                                                              */
+  CSI_IRQn                   = 47,     /*!< CSI global interrupt                                                               */
+  DCMIPP_IRQn                = 48,     /*!< DCMIPP global interrupt                                                            */
+  PAHB_ERR_IRQn              = 52,     /*!< PAHB error interrupt                                                               */
+  NPU0_IRQn                  = 53,     /*!< NPU mst_ints[0] line interrupt                                                     */
+  NPU1_IRQn                  = 54,     /*!< NPU mst_ints[1] line interrupt                                                     */
+  NPU2_IRQn                  = 55,     /*!< NPU mst_ints[2] line interrupt                                                     */
+  NPU3_IRQn                  = 56,     /*!< NPU mst_ints[3] line interrupt                                                     */
+  CACHEAXI_IRQn              = 57,     /*!< NPU cache interrupt                                                                */
+  LTDC_LO_IRQn               = 58,     /*!< LTDC low-layer global interrupt                                                    */
+  LTDC_LO_ERR_IRQn           = 59,     /*!< LTDC low-layer error interrupt                                                     */
+  DMA2D_IRQn                 = 60,     /*!< DMA2D global interrupt                                                             */
+  JPEG_IRQn                  = 61,     /*!< JPEG global interrupt                                                              */
+  VENC_IRQn                  = 62,     /*!< VENC global interrupt                                                              */
+  GFXMMU_IRQn                = 63,     /*!< GFXMMU global interrupt                                                            */
+  GFXTIM_IRQn                = 64,     /*!< GFXTIM global interrupt                                                            */
+  GPU2D_IRQn                 = 65,     /*!< GPU2D interrupt                                                                    */
+  GPU2D_ER_IRQn              = 66,     /*!< GPU2D error interrupt                                                              */
+  ICACHE_IRQn                = 67,     /*!< GPU2D cache interrupt                                                              */
+  HPDMA1_Channel0_IRQn       = 68,     /*!< HPDMA1 Channel 0 global interrupt                                                  */
+  HPDMA1_Channel1_IRQn       = 69,     /*!< HPDMA1 Channel 1 global interrupt                                                  */
+  HPDMA1_Channel2_IRQn       = 70,     /*!< HPDMA1 Channel 2 global interrupt                                                  */
+  HPDMA1_Channel3_IRQn       = 71,     /*!< HPDMA1 Channel 3 global interrupt                                                  */
+  HPDMA1_Channel4_IRQn       = 72,     /*!< HPDMA1 Channel 4 global interrupt                                                  */
+  HPDMA1_Channel5_IRQn       = 73,     /*!< HPDMA1 Channel 5 global interrupt                                                  */
+  HPDMA1_Channel6_IRQn       = 74,     /*!< HPDMA1 Channel 6 global interrupt                                                  */
+  HPDMA1_Channel7_IRQn       = 75,     /*!< HPDMA1 Channel 7 global interrupt                                                  */
+  HPDMA1_Channel8_IRQn       = 76,     /*!< HPDMA1 Channel 8 global interrupt                                                  */
+  HPDMA1_Channel9_IRQn       = 77,     /*!< HPDMA1 Channel 9 global interrupt                                                  */
+  HPDMA1_Channel10_IRQn      = 78,     /*!< HPDMA1 Channel 10 global interrupt                                                 */
+  HPDMA1_Channel11_IRQn      = 79,     /*!< HPDMA1 Channel 11 global interrupt                                                 */
+  HPDMA1_Channel12_IRQn      = 80,     /*!< HPDMA1 Channel 12 global interrupt                                                 */
+  HPDMA1_Channel13_IRQn      = 81,     /*!< HPDMA1 Channel 13 global interrupt                                                 */
+  HPDMA1_Channel14_IRQn      = 82,     /*!< HPDMA1 Channel 14 global interrupt                                                 */
+  HPDMA1_Channel15_IRQn      = 83,     /*!< HPDMA1 Channel 15 global interrupt                                                 */
+  GPDMA1_Channel0_IRQn       = 84,     /*!< GPDMA1 Channel 0 interrupt                                                         */
+  GPDMA1_Channel1_IRQn       = 85,     /*!< GPDMA1 Channel 1 interrupt                                                         */
+  GPDMA1_Channel2_IRQn       = 86,     /*!< GPDMA1 Channel 2 interrupt                                                         */
+  GPDMA1_Channel3_IRQn       = 87,     /*!< GPDMA1 Channel 3 interrupt                                                         */
+  GPDMA1_Channel4_IRQn       = 88,     /*!< GPDMA1 Channel 4 interrupt                                                         */
+  GPDMA1_Channel5_IRQn       = 89,     /*!< GPDMA1 Channel 5 interrupt                                                         */
+  GPDMA1_Channel6_IRQn       = 90,     /*!< GPDMA1 Channel 6 interrupt                                                         */
+  GPDMA1_Channel7_IRQn       = 91,     /*!< GPDMA1 Channel 7 interrupt                                                         */
+  GPDMA1_Channel8_IRQn       = 92,     /*!< GPDMA1 Channel 8 interrupt                                                         */
+  GPDMA1_Channel9_IRQn       = 93,     /*!< GPDMA1 Channel 9 interrupt                                                         */
+  GPDMA1_Channel10_IRQn      = 94,     /*!< GPDMA1 Channel 10 interrupt                                                        */
+  GPDMA1_Channel11_IRQn      = 95,     /*!< GPDMA1 Channel 11 interrupt                                                        */
+  GPDMA1_Channel12_IRQn      = 96,     /*!< GPDMA1 Channel 12 interrupt                                                        */
+  GPDMA1_Channel13_IRQn      = 97,     /*!< GPDMA1 Channel 13 interrupt                                                        */
+  GPDMA1_Channel14_IRQn      = 98,     /*!< GPDMA1 Channel 14 interrupt                                                        */
+  GPDMA1_Channel15_IRQn      = 99,     /*!< GPDMA1 Channel 15 interrupt                                                        */
+  I2C1_EV_IRQn               = 100,    /*!< I2C1 event interrupt                                                               */
+  I2C1_ER_IRQn               = 101,    /*!< I2C1 error interrupt                                                               */
+  I2C2_EV_IRQn               = 102,    /*!< I2C2 event interrupt                                                               */
+  I2C2_ER_IRQn               = 103,    /*!< I2C2 error interrupt                                                               */
+  I2C3_EV_IRQn               = 104,    /*!< I2C3 event interrupt                                                               */
+  I2C3_ER_IRQn               = 105,    /*!< I2C3 error interrupt                                                               */
+  I2C4_EV_IRQn               = 106,    /*!< I2C4 event interrupt                                                               */
+  I2C4_ER_IRQn               = 107,    /*!< I2C4 error interrupt                                                               */
+  I3C1_EV_IRQn               = 108,    /*!< I3C1 event interrupt                                                               */
+  I3C1_ER_IRQn               = 109,    /*!< I3C1 error interrupt                                                               */
+  I3C2_EV_IRQn               = 110,    /*!< I3C2 event interrupt                                                               */
+  I3C2_ER_IRQn               = 111,    /*!< I3C2 error interrupt                                                               */
+  TIM1_BRK_IRQn              = 112,    /*!< TIM1 Break interrupt                                                               */
+  TIM1_UP_IRQn               = 113,    /*!< TIM1 Update interrupt                                                              */
+  TIM1_TRG_COM_IRQn          = 114,    /*!< TIM1 Trigger and Commutation interrupt                                             */
+  TIM1_CC_IRQn               = 115,    /*!< TIM1 Capture Compare interrupt                                                     */
+  TIM2_IRQn                  = 116,    /*!< TIM2 global interrupt                                                              */
+  TIM3_IRQn                  = 117,    /*!< TIM3 global interrupt                                                              */
+  TIM4_IRQn                  = 118,    /*!< TIM4 global interrupt                                                              */
+  TIM5_IRQn                  = 119,    /*!< TIM5 global interrupt                                                              */
+  TIM6_IRQn                  = 120,    /*!< TIM6 global interrupt                                                              */
+  TIM7_IRQn                  = 121,    /*!< TIM7 global interrupt                                                              */
+  TIM8_BRK_IRQn              = 122,    /*!< TIM8 Break interrupt                                                               */
+  TIM8_UP_IRQn               = 123,    /*!< TIM8 Update interrupt                                                              */
+  TIM8_TRG_COM_IRQn          = 124,    /*!< TIM8 Trigger and Commutation interrupt                                             */
+  TIM8_CC_IRQn               = 125,    /*!< TIM8 Capture Compare interrupt                                                     */
+  TIM9_IRQn                  = 126,    /*!< TIM9 global interrupt                                                              */
+  TIM10_IRQn                 = 127,    /*!< TIM10 global interrupt                                                             */
+  TIM11_IRQn                 = 128,    /*!< TIM11 global interrupt                                                             */
+  TIM12_IRQn                 = 129,    /*!< TIM12 global interrupt                                                             */
+  TIM13_IRQn                 = 130,    /*!< TIM13 global interrupt                                                             */
+  TIM14_IRQn                 = 131,    /*!< TIM14 global interrupt                                                             */
+  TIM15_IRQn                 = 132,    /*!< TIM15 global interrupt                                                             */
+  TIM16_IRQn                 = 133,    /*!< TIM16 global interrupt                                                             */
+  TIM17_IRQn                 = 134,    /*!< TIM17 global interrupt                                                             */
+  TIM18_IRQn                 = 135,    /*!< TIM18 global interrupt                                                             */
+  LPTIM1_IRQn                = 136,    /*!< LPTIM1 global interrupt                                                            */
+  LPTIM2_IRQn                = 137,    /*!< LPTIM2 global interrupt                                                            */
+  LPTIM3_IRQn                = 138,    /*!< LPTIM3 global interrupt                                                            */
+  LPTIM4_IRQn                = 139,    /*!< LPTIM4 global interrupt                                                            */
+  LPTIM5_IRQn                = 140,    /*!< LPTIM5 global interrupt                                                            */
+  ADF1_FLT0_IRQn             = 141,    /*!< ADF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT0_IRQn             = 142,    /*!< MDF1 Filter 0 global interrupt                                                     */
+  MDF1_FLT1_IRQn             = 143,    /*!< MDF1 Filter 1 global interrupt                                                     */
+  MDF1_FLT2_IRQn             = 144,    /*!< MDF1 Filter 2 global interrupt                                                     */
+  MDF1_FLT3_IRQn             = 145,    /*!< MDF1 Filter 3 global interrupt                                                     */
+  MDF1_FLT4_IRQn             = 146,    /*!< MDF1 Filter 4 global interrupt                                                     */
+  MDF1_FLT5_IRQn             = 147,    /*!< MDF1 Filter 5 global interrupt                                                     */
+  SAI1_A_IRQn                = 148,    /*!< Serial Audio Interface 1 block A interrupt                                         */
+  SAI1_B_IRQn                = 149,    /*!< Serial Audio Interface 1 block B interrupt                                         */
+  SAI2_A_IRQn                = 150,    /*!< Serial Audio Interface 2 block A interrupt                                         */
+  SAI2_B_IRQn                = 151,    /*!< Serial Audio Interface 2 block B interrupt                                         */
+  SPDIFRX1_IRQn              = 152,    /*!< SPDIFRX1 interrupt                                                                 */
+  SPI1_IRQn                  = 153,    /*!< SPI1 global interrupt                                                              */
+  SPI2_IRQn                  = 154,    /*!< SPI2 global interrupt                                                              */
+  SPI3_IRQn                  = 155,    /*!< SPI3 global interrupt                                                              */
+  SPI4_IRQn                  = 156,    /*!< SPI4 global interrupt                                                              */
+  SPI5_IRQn                  = 157,    /*!< SPI5 global interrupt                                                              */
+  SPI6_IRQn                  = 158,    /*!< SPI6 global interrupt                                                              */
+  USART1_IRQn                = 159,    /*!< USART1 global interrupt                                                            */
+  USART2_IRQn                = 160,    /*!< USART2 global interrupt                                                            */
+  USART3_IRQn                = 161,    /*!< USART3 global interrupt                                                            */
+  UART4_IRQn                 = 162,    /*!< UART4 global interrupt                                                             */
+  UART5_IRQn                 = 163,    /*!< UART5 global interrupt                                                             */
+  USART6_IRQn                = 164,    /*!< USART3 global interrupt                                                            */
+  UART7_IRQn                 = 165,    /*!< UART7 global interrupt                                                             */
+  UART8_IRQn                 = 166,    /*!< UART8 global interrupt                                                             */
+  UART9_IRQn                 = 167,    /*!< UART9 global interrupt                                                             */
+  USART10_IRQn               = 168,    /*!< USART10 global interrupt                                                           */
+  LPUART1_IRQn               = 169,    /*!< LPUART1 global interrupt                                                           */
+  XSPI1_IRQn                 = 170,    /*!< XSPI1 global interrupt                                                             */
+  XSPI2_IRQn                 = 171,    /*!< XSPI2 global interrupt                                                             */
+  XSPI3_IRQn                 = 172,    /*!< XSPI3 global interrupt                                                             */
+  FMC_IRQn                   = 173,    /*!< FMC global interrupt                                                               */
+  SDMMC1_IRQn                = 174,    /*!< SDMMC1 global interrupt                                                            */
+  SDMMC2_IRQn                = 175,    /*!< SDMMC2 global interrupt                                                            */
+  UCPD1_IRQn                 = 176,    /*!< UCPD1 global interrupt                                                             */
+  USB1_OTG_HS_IRQn           = 177,    /*!< USB1 OTG HS interrupt                                                              */
+  USB2_OTG_HS_IRQn           = 178,    /*!< USB2 OTG HS interrupt                                                              */
+  ETH1_IRQn                  = 179,    /*!< ETH1 global interrupt                                                              */
+  FDCAN1_IT0_IRQn            = 180,    /*!< FDCAN1 interrupt 0                                                                 */
+  FDCAN1_IT1_IRQn            = 181,    /*!< FDCAN1 interrupt 1                                                                 */
+  FDCAN2_IT0_IRQn            = 182,    /*!< FDCAN2 interrupt 0                                                                 */
+  FDCAN2_IT1_IRQn            = 183,    /*!< FDCAN2 interrupt 1                                                                 */
+  FDCAN3_IT0_IRQn            = 184,    /*!< FDCAN3 interrupt 0                                                                 */
+  FDCAN3_IT1_IRQn            = 185,    /*!< FDCAN3 interrupt 1                                                                 */
+  FDCAN_CU_IRQn              = 186,    /*!< FDCAN Clock Unit interrupt                                                         */
+  MDIOS_IRQn                 = 187,    /*!< MDIOS global interrupt                                                             */
+  DCMI_PSSI_IRQn             = 188,    /*!< DCMI/PSSI global interrupt                                                         */
+  WAKEUP_PIN_IRQn            = 189,    /*!< Wake-up pins interrupt                                                             */
+  CTI_INT0_IRQn              = 190,    /*!< CTI INT0 interrupt                                                                 */
+  CTI_INT1_IRQn              = 191,    /*!< CTI INT1 interrupt                                                                 */
+  LTDC_UP_IRQn               = 193,    /*!< LTDC up-layer global interrupt                                                     */
+  LTDC_UP_ERR_IRQn           = 194,    /*!< LTDC up-layer error interrupt                                                      */
+} IRQn_Type;
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/**
+  * @brief Configuration of the Cortex-M55 Processor and Core Peripherals
+   */
+#define __CM55_REV                0x0101U /*!< Cortex-M55 revision r1p1                      */
+#define __FPU_PRESENT             1U      /*!< CM55 Floating Point Unit present              */
+#define __DSP_PRESENT             1U      /*!< CM55 Digital Signal Processing Unit present   */
+#define __MPU_PRESENT             1U      /*!< CM55 Memory Programming Unit present          */
+#define __ICACHE_PRESENT          1U      /*!< CM55 Instruction cache present                */
+#define __DCACHE_PRESENT          1U      /*!< CM55 Data cache present                       */
+#define __VTOR_PRESENT            1U      /*!< CM55 Vector table offset register present     */
+#define __PMU_PRESENT             1U      /*!< CM55 Performance Monitoring Unit present      */
+#define __PMU_NUM_EVENTCNT        8U      /*!< CM55 can monitor up to 8 PMU events           */
+#define __NVIC_PRIO_BITS          4U      /*!< CM55 uses 4 bits for the Priority Levels      */
+#define __Vendor_SysTickConfig    0U      /*!< Set to 1 if different SysTick Config is used  */
+#define __SAUREGION_PRESENT       1U      /*!< SAU regions present                           */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define CPU_IN_SECURE_STATE
+#endif
+
+#define CPU_AS_TRUSTED_DOMAIN
+
+#include "core_cm55.h"                    /*!< ARM Cortex-M55 processor and core peripherals */
+#include "system_stm32n6xx.h"             /*!< STM32N6xx System */
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+/** @addtogroup STM32N6xx_peripherals
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter (ADC)
+  */
+typedef struct
+{
+  __IO uint32_t ISR;           /*!< ADC interrupt and status register,                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< ADC interrupt enable register,                         Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< ADC control register,                                  Address offset: 0x08 */
+  __IO uint32_t CFGR1;         /*!< ADC configuration register 1,                          Address offset: 0x0C */
+  __IO uint32_t CFGR2;         /*!< ADC configuration register 2,                          Address offset: 0x10 */
+  __IO uint32_t SMPR1;         /*!< ADC sample time register 1,                            Address offset: 0x14 */
+  __IO uint32_t SMPR2;         /*!< ADC sample time register 2,                            Address offset: 0x18 */
+  __IO uint32_t PCSEL;         /*!< ADC channel preselection register,                     Address offset: 0x1C */
+  uint32_t      RESERVED1[4];  /*!< Reserved,                                              Address offset: 0x020-0x02C */
+  __IO uint32_t SQR1;          /*!< ADC regular sequence register 1,                       Address offset: 0x30 */
+  __IO uint32_t SQR2;          /*!< ADC regular sequence register 2,                       Address offset: 0x34 */
+  __IO uint32_t SQR3;          /*!< ADC regular sequence register 3,                       Address offset: 0x38 */
+  __IO uint32_t SQR4;          /*!< ADC regular sequence register 4,                       Address offset: 0x3C */
+  __IO uint32_t DR;            /*!< ADC regular data register,                             Address offset: 0x40 */
+  uint32_t      RESERVED2[2];  /*!< Reserved,                                              Address offset: 0x044-0x048 */
+  __IO uint32_t JSQR;          /*!< ADC injected sequence register,                        Address offset: 0x4C */
+  __IO uint32_t OFCFGR1;       /*!< ADC offset configuration register 1,                   Address offset: 0x50 */
+  __IO uint32_t OFCFGR2;       /*!< ADC offset configuration register 2,                   Address offset: 0x54 */
+  __IO uint32_t OFCFGR3;       /*!< ADC offset configuration register 3,                   Address offset: 0x58 */
+  __IO uint32_t OFCFGR4;       /*!< ADC offset configuration register 4,                   Address offset: 0x5C */
+  __IO uint32_t OFR1;          /*!< ADC offset register 1,                                 Address offset: 0x60 */
+  __IO uint32_t OFR2;          /*!< ADC offset register 2,                                 Address offset: 0x64 */
+  __IO uint32_t OFR3;          /*!< ADC offset register 3,                                 Address offset: 0x68 */
+  __IO uint32_t OFR4;          /*!< ADC offset register 4,                                 Address offset: 0x6C */
+  __IO uint32_t GCOMP;         /*!< ADC gain compensation register,                        Address offset: 0x70 */
+  uint32_t      RESERVED3[3];  /*!< Reserved,                                              Address offset: 0x074-0x07C */
+  __IO uint32_t JDR1;          /*!< ADC injected data register 1,                          Address offset: 0x80 */
+  __IO uint32_t JDR2;          /*!< ADC injected data register 2,                          Address offset: 0x84 */
+  __IO uint32_t JDR3;          /*!< ADC injected data register 3,                          Address offset: 0x88 */
+  __IO uint32_t JDR4;          /*!< ADC injected data register 4,                          Address offset: 0x8C */
+  uint32_t      RESERVED4[4];  /*!< Reserved,                                              Address offset: 0x090-0x09C */
+  __IO uint32_t AWD2CR;        /*!< ADC analog watchdog 2 configuration register,          Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;        /*!< ADC analog watchdog 3 configuration register,          Address offset: 0xA4 */
+  __IO uint32_t AWD1LTR;       /*!< ADC analog watchdog 1 low threshold register,          Address offset: 0xA8 */
+  __IO uint32_t AWD1HTR;       /*!< ADC analog watchdog 1 high threshold register,         Address offset: 0xAC */
+  __IO uint32_t AWD2LTR;       /*!< ADC analog watchdog 2 low threshold register,          Address offset: 0xB0 */
+  __IO uint32_t AWD2HTR;       /*!< ADC analog watchdog 2 high threshold register,         Address offset: 0xB4 */
+  __IO uint32_t AWD3LTR;       /*!< ADC analog watchdog 3 low threshold register,          Address offset: 0xB8 */
+  __IO uint32_t AWD3HTR;       /*!< ADC analog watchdog 3 high threshold register,         Address offset: 0xBC */
+  __IO uint32_t DIFSEL;        /*!< ADC differential mode selection register,              Address offset: 0xC0 */
+  __IO uint32_t CALFACT;       /*!< ADC calibration factors,                               Address offset: 0xC4 */
+  uint32_t      RESERVED5[2];  /*!< Reserved,                                              Address offset: 0x0C8-0x0CC */
+  __IO uint32_t OR;            /*!< ADC option register,                                   Address offset: 0xD0 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;           /*!< ADC common status register,                            Address offset: 0x300 */
+  uint32_t RESERVED;           /*!< Reserved,                                              Address offset: 0x304 */
+  __IO uint32_t CCR;           /*!< ADC common control register,                           Address offset: 0x308 */
+  __IO uint32_t CDR;           /*!< ADC common regular data register for dual mode,        Address offset: 0x30C */
+  __IO uint32_t CDR2;          /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Boot and Security
+  */
+
+typedef struct
+{
+  __IO uint32_t FVRw[384];       /*!< BSEC fuse word (0-383) value register,       Address offset: 0x000-0x5FC */
+       uint32_t RESERVED0[128];  /*!< Reserved,                                    Address offset: 0x600-0x7FC */
+  __IO uint32_t SPLOCKx[12];     /*!< BSEC sticky program lock register (0-11),    Address offset: 0x800-0x82C */
+       uint32_t RESERVED1[4];    /*!< Reserved,                                    Address offset: 0x830-0x83C */
+  __IO uint32_t SWLOCKx[12];     /*!< BSEC sticky write lock register (0-11),      Address offset: 0x840-0x86C */
+       uint32_t RESERVED2[4];    /*!< Reserved,                                    Address offset: 0x870-0x87C */
+  __IO uint32_t SRLOCKx[12];     /*!< BSEC sticky reload lock register (0-11),     Address offset: 0x880-0x8AC */
+       uint32_t RESERVED3[4];    /*!< Reserved,                                    Address offset: 0x8B0-0x8BC */
+  __IO uint32_t OTPVLDRx[12];    /*!< BSEC OTP valid register (0-11),              Address offset: 0x8C0-0x8EC */
+       uint32_t RESERVED4[20];   /*!< Reserved,                                    Address offset: 0x8F0-0x93C */
+  __IO uint32_t SFSRx[12];       /*!< BSEC shadowed fuses status register (0-11),  Address offset: 0x940-0x96C */
+       uint32_t RESERVED5[165];  /*!< Reserved,                                    Address offset: 0x970-0xC00 */
+  __IO uint32_t OTPCR;           /*!< BSEC OTP control register,                   Address offset: 0xC04 */
+  __IO uint32_t WDR;             /*!< BSEC write data register,                    Address offset: 0xC08 */
+       uint32_t RESERVED6[125];  /*!< Reserved,                                    Address offset: 0xC0C-0xDFC */
+  __IO uint32_t SCRATCHRx[4];    /*!< BSEC scratch register (0-3),                 Address offset: 0xE00-0xE0C */
+  __IO uint32_t LOCKR;           /*!< BSEC lock register,                          Address offset: 0xE10 */
+  __IO uint32_t JTAGINR;         /*!< BSEC JTAG input register,                    Address offset: 0xE14 */
+  __IO uint32_t JTAGOUTR;        /*!< BSEC JTAG output register,                   Address offset: 0xE18 */
+       uint32_t RESERVED7[2];    /*!< Reserved,                                    Address offset: 0xE1C-0xE20 */
+  __IO uint32_t UNMAPR;          /*!< BSEC unmap register,                         Address offset: 0xE24 */
+       uint32_t RESERVED8[6];    /*!< Reserved,                                    Address offset: 0xE28-0xE3C */
+  __IO uint32_t SR;              /*!< BSEC status register,                        Address offset: 0xE40 */
+  __IO uint32_t OTPSR;           /*!< BSEC OTP status register,                    Address offset: 0xE44 */
+       uint32_t RESERVED9[14];   /*!< Reserved,                                    Address offset: 0xE48-0xE7C */
+  __IO uint32_t EPOCHRx[2];      /*!< BSEC epoch register (0-1),                   Address offset: 0xE80-0xE84 */
+  __IO uint32_t EPOCHSELR;       /*!< BSEC epoch select register,                  Address offset: 0xE88 */
+  __IO uint32_t DBGCR;           /*!< BSEC debug control register,                 Address offset: 0xE8C */
+  __IO uint32_t AP_UNLOCK;       /*!< BSEC AP unlock,                              Address offset: 0xE90 */
+  __IO uint32_t HDPLSR;          /*!< BSEC hide protection level status register,  Address offset: 0xE94 */
+  __IO uint32_t HDPLCR;          /*!< BSEC hide protection level control register, Address offset: 0xE98 */
+  __IO uint32_t NEXTLR;          /*!< BSEC next hide protection level register,    Address offset: 0xE9C */
+       uint32_t RESERVED10[40];  /*!< Reserved,                                    Address offset: 0xEA0-0xF3C */
+  __IO uint32_t WOSCRx[8];       /*!< BSEC write once scratch register (0-7),      Address offset: 0xF40-0xF5C */
+       uint32_t RESERVED11[34];  /*!< Reserved,                                    Address offset: 0xF60-0xFE4 */
+  __IO uint32_t HRCR;            /*!< BSEC hot reset count register,               Address offset: 0xFE8 */
+  __IO uint32_t WRCR;            /*!< BSEC warm reset count register,              Address offset: 0xFEC */
+} BSEC_TypeDef;
+
+/**
+  * @brief Axi Cache
+  */
+typedef struct
+{
+  __IO uint32_t CR1;            /*!< CACHEAXI control register 1,                   Address offset: 0x00 */
+  __IO uint32_t SR;             /*!< CACHEAXI status register,                      Address offset: 0x04 */
+  __IO uint32_t IER;            /*!< CACHEAXI interrupt enable register,            Address offset: 0x08 */
+  __IO uint32_t FCR;            /*!< CACHEAXI flag clear register,                  Address offset: 0x0C */
+  __IO uint32_t RHMONR;         /*!< CACHEAXI read hit monitor register,            Address offset: 0x10 */
+  __IO uint32_t RMMONR;         /*!< CACHEAXI read miss monitor register,           Address offset: 0x14 */
+  __IO uint32_t RAMMONR;        /*!< CACHEAXI read-allocate miss monitor register,  Address offset: 0x18 */
+  __IO uint32_t EVIMONR;        /*!< CACHEAXI eviction monitor register,            Address offset: 0x1C */
+  __IO uint32_t WHMONR;         /*!< CACHEAXI write-hit monitor register,           Address offset: 0x20 */
+  __IO uint32_t WMMONR;         /*!< CACHEAXI write-miss monitor register,          Address offset: 0x24 */
+  __IO uint32_t WAMMONR;        /*!< CACHEAXI write-allocate miss monitor register, Address offset: 0x28 */
+  __IO uint32_t WTMONR;         /*!< CACHEAXI write-through monitor register,       Address offset: 0x2C */
+       uint32_t RESERVED1[52];  /*!< Reserved,                                      Address offset: 0x30-0xFC */
+  __IO uint32_t CR2;            /*!< CACHEAXI control register 2,                   Address offset: 0x100 */
+  __IO uint32_t CMDRSADDRR;     /*!< CACHEAXI command start address register,       Address offset: 0x104 */
+  __IO uint32_t CMDREADDRR;     /*!< CACHEAXI command end address register,         Address offset: 0x108 */
+} CACHEAXI_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+typedef struct
+{
+  __IO uint32_t DR;            /*!< CRC Data register,                              Address offset: 0x00 */
+  __IO uint32_t IDR;           /*!< CRC Independent data register,                  Address offset: 0x04 */
+  __IO uint32_t CR;            /*!< CRC Control register,                           Address offset: 0x08 */
+       uint32_t RESERVED1;     /*!< Reserved,                                                       0x0C */
+  __IO uint32_t INIT;          /*!< Initial CRC value register,                     Address offset: 0x10 */
+  __IO uint32_t POL;           /*!< CRC polynomial register,                        Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Cryp Processor
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
+  __IO uint32_t DIN;        /*!< CRYP data input register,                                 Address offset: 0x08 */
+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/*
+ * @brief  (CSI)
+ */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< CSI-2 Host control register                           Address offset: 0x0000 */
+  __IO uint32_t PCR;              /*!< CSI-2 Host DPHY_RX control register                   Address offset: 0x0004 */
+       uint32_t RESERVED0[2];     /*!< Reserved                                              Address offset: 0x0008-0x000C */
+  __IO uint32_t VC0CFGR1;         /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */
+  __IO uint32_t VC0CFGR2;         /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */
+  __IO uint32_t VC0CFGR3;         /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */
+  __IO uint32_t VC0CFGR4;         /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */
+  __IO uint32_t VC1CFGR1;         /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */
+  __IO uint32_t VC1CFGR2;         /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */
+  __IO uint32_t VC1CFGR3;         /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */
+  __IO uint32_t VC1CFGR4;         /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */
+  __IO uint32_t VC2CFGR1;         /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */
+  __IO uint32_t VC2CFGR2;         /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */
+  __IO uint32_t VC2CFGR3;         /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */
+  __IO uint32_t VC2CFGR4;         /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */
+  __IO uint32_t VC3CFGR1;         /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */
+  __IO uint32_t VC3CFGR2;         /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */
+  __IO uint32_t VC3CFGR3;         /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */
+  __IO uint32_t VC3CFGR4;         /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */
+  __IO uint32_t LB0CFGR;          /*!< CSI-2 Host line byte 0 configuration register         Address offset: 0x0050 */
+  __IO uint32_t LB1CFGR;          /*!< CSI-2 Host line byte 1 configuration register         Address offset: 0x0054 */
+  __IO uint32_t LB2CFGR;          /*!< CSI-2 Host line byte 2 configuration register         Address offset: 0x0058 */
+  __IO uint32_t LB3CFGR;          /*!< CSI-2 Host line byte 3 configuration register         Address offset: 0x005C */
+  __IO uint32_t TIM0CFGR;         /*!< CSI-2 Host timer 0 configuration register             Address offset: 0x0060 */
+  __IO uint32_t TIM1CFGR;         /*!< CSI-2 Host timer 1 configuration register             Address offset: 0x0064 */
+  __IO uint32_t TIM2CFGR;         /*!< CSI-2 Host timer 2 configuration register             Address offset: 0x0068 */
+  __IO uint32_t TIM3CFGR;         /*!< CSI-2 Host timer 3 configuration register             Address offset: 0x006C */
+  __IO uint32_t LMCFGR;           /*!< CSI-2 Host lane merger configuration register         Address offset: 0x0070 */
+  __IO uint32_t PRGITR;           /*!< CSI-2 Host program interrupt register                 Address offset: 0x0074 */
+  __IO uint32_t WDR;              /*!< CSI-2 Host watchdog register                          Address offset: 0x0078 */
+       uint32_t RESERVED1;        /*!< Reserved                                              Address offset: 0x007C */
+  __IO uint32_t IER0;             /*!< CSI-2 Host Interrupt enable register 0                Address offset: 0x0080 */
+  __IO uint32_t IER1;             /*!< CSI-2 Host Interrupt enable register 1                Address offset: 0x0084 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                              Address offset: 0x0088-0x008C */
+  __IO uint32_t SR0;              /*!< CSI-2 Host status register 0                          Address offset: 0x0090 */
+  __IO uint32_t SR1;              /*!< CSI-2 Host status register 1                          Address offset: 0x0094 */
+       uint32_t RESERVED3[26];    /*!< Reserved                                              Address offset: 0x0098-0x00FC */
+  __IO uint32_t FCR0;             /*!< CSI-2 Host Flag clear register 0                      Address offset: 0x0100 */
+  __IO uint32_t FCR1;             /*!< CSI-2 Host Flag clear register 1                      Address offset: 0x0104 */
+       uint32_t RESERVED4[2];     /*!< Reserved                                              Address offset: 0x0108-0x010C */
+  __IO uint32_t SPDFR;            /*!< CSI-2 Host short packet data field register           Address offset: 0x0110 */
+  __IO uint32_t ERR1;             /*!< CSI-2 Host error register 1                           Address offset: 0x0114 */
+  __IO uint32_t ERR2;             /*!< CSI-2 Host error register 2                           Address offset: 0x0118 */
+       uint32_t RESERVED5[953];   /*!< Reserved                                              Address offset: 0x011C-0x0FFC */
+  __IO uint32_t PRCR;             /*!< CSI PHY reset control register                        Address offset: 0x1000 */
+  __IO uint32_t PMCR;             /*!< CSI PHY mode control register                         Address offset: 0x1004 */
+  __IO uint32_t PFCR;             /*!< CSI PHY frequency control register                    Address offset: 0x1008 */
+       uint32_t RESERVED6;        /*!< Reserved                                              Address offset: 0x100C */
+  __IO uint32_t PTCR0;            /*!< CSI PHY test control register 0                       Address offset: 0x1010 */
+  __IO uint32_t PTCR1;            /*!< CSI PHY test control register 1                       Address offset: 0x1014 */
+  __IO uint32_t PTSR;             /*!< CSI PHY test status register                          Address offset: 0x1018 */
+       uint32_t RESERVED7[1017];  /*!< Reserved                                              Address offset: 0x101C-0x1FFC */
+} CSI_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                            Address offset: 0x00  */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,              Address offset: 0x04  */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t APB1LFZ1;      /*!< Debug MCU APB1LFZ1 freeze register,            Address offset: 0x10  */
+  __IO uint32_t APB1HFZ1;      /*!< Debug MCU APB1HFZ1 freeze register,            Address offset: 0x14  */
+  __IO uint32_t APB2FZ1;       /*!< Debug MCU APB2FZ1 freeze register,             Address offset: 0x18  */
+  __IO uint32_t APB4FZ1;       /*!< Debug MCU APB4FZ1 freeze register,             Address offset: 0x1C  */
+  __IO uint32_t APB5FZ1;       /*!< Debug MCU APB5FZ1 freeze register,             Address offset: 0x20  */
+  __IO uint32_t AHB1FZ1;       /*!< Debug MCU AHB1FZ1 freeze register,             Address offset: 0x24  */
+  __IO uint32_t AHB5FZ1;       /*!< Debug MCU AHB5FZ1 freeze register,             Address offset: 0x28  */
+  uint32_t RESERVED2[52];      /*!< Reserved,                                  Address offset: 0x2C-0xF8 */
+  __IO uint32_t SR;            /*!< Debug MCU status register,                     Address offset: 0xFC  */
+  __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register,        Address offset: 0x100 */
+  __IO uint32_t DBG_AUTH_DEV;  /*!< Debug MCU authentication device register,      Address offset: 0x104 */
+  __IO uint32_t DBG_AUTH_ACK;  /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */
+} DBGMCU_TypeDef;
+
+/**
+  * @brief DCMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+#define DCMIPP_NUM_OF_PIPES 0x03U
+
+typedef struct
+{
+  uint32_t PxRIxCR1;      /*! DCMIPP Pipex ROIx configuration register 1  Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2)  */
+  uint32_t PxRIxCR2;      /*! DCMIPP Pipex ROIx configuration register 2  Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2)  */
+} DCMIPP_Region_TypeDef;
+
+/*
+ * @brief Digital camera interface pixel pipeline DCMIPP
+ */
+typedef struct
+{
+  __IO uint32_t IPGR1;           /*!< DCMIPP IPPLUG global register 1                                    Address offset: 0x000 */
+  __IO uint32_t IPGR2;           /*!< DCMIPP IPPLUG global register 2                                    Address offset: 0x004 */
+  __IO uint32_t IPGR3;           /*!< DCMIPP IPPLUG global register 3                                    Address offset: 0x008 */
+       uint32_t RESERVED0[4];    /*!< Reserved                                                           Address offset: 0x00C-0x018 */
+  __IO uint32_t IPGR8;           /*!< DCMIPP IPPLUG identification register                              Address offset: 0x01C */
+  __IO uint32_t IPC1R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */
+  __IO uint32_t IPC1R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */
+       uint32_t RESERVED1;       /*!< Reserved                                                           Address offset: 0x02C */
+  __IO uint32_t IPC2R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x030 */
+  __IO uint32_t IPC2R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x034 */
+  __IO uint32_t IPC2R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x038 */
+       uint32_t RESERVED2;       /*!< Reserved                                                           Address offset: 0x03C */
+  __IO uint32_t IPC3R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x040 */
+  __IO uint32_t IPC3R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x044 */
+  __IO uint32_t IPC3R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x048 */
+       uint32_t RESERVED3;       /*!< Reserved                                                           Address offset: 0x04C */
+  __IO uint32_t IPC4R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x050 */
+  __IO uint32_t IPC4R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x054 */
+  __IO uint32_t IPC4R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x058 */
+       uint32_t RESERVED4;       /*!< Reserved                                                           Address offset: 0x05C */
+  __IO uint32_t IPC5R1;          /*!< DCMIPP IPPLUG Clientx register 1                                   Address offset: 0x060 */
+  __IO uint32_t IPC5R2;          /*!< DCMIPP IPPLUG Clientx register 2                                   Address offset: 0x064 */
+  __IO uint32_t IPC5R3;          /*!< DCMIPP IPPLUG Clientx register 3                                   Address offset: 0x068 */
+       uint32_t RESERVED5[38];   /*!< Reserved                                                           Address offset: 0x06C-0x100 */
+  __IO uint32_t PRCR;            /*!< DCMIPP parallel interface control register                         Address offset: 0x104 */
+  __IO uint32_t PRESCR;          /*!< DCMIPP parallel interface embedded synchronization code register   Address offset: 0x108 */
+  __IO uint32_t PRESUR;          /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */
+       uint32_t RESERVED6[57];   /*!< Reserved                                                           Address offset: 0x110-0x1F0 */
+  __IO uint32_t PRIER;           /*!< DCMIPP parallel interface interrupt enable register                Address offset: 0x1F4 */
+  __IO uint32_t PRSR;            /*!< DCMIPP parallel interface status register                          Address offset: 0x1F8 */
+  __IO uint32_t PRFCR;           /*!< DCMIPP parallel interface interrupt clear register                 Address offset: 0x1FC */
+       uint32_t RESERVED7;       /*!< Reserved                                                           Address offset: 0x200 */
+  __IO uint32_t CMCR;            /*!< DCMIPP common configuration register                               Address offset: 0x204 */
+  __IO uint32_t CMFRCR;          /*!< DCMIPP common frame counter register                               Address offset: 0x208 */
+       uint32_t RESERVED8[121];  /*!< Reserved                                                           Address offset: 0x20C-0x3EC */
+  __IO uint32_t CMIER;           /*!< DCMIPP common interrupt enable register                            Address offset: 0x3F0 */
+  __IO uint32_t CMSR1;           /*!< DCMIPP common status register 1                                    Address offset: 0x3F4 */
+  __IO uint32_t CMSR2;           /*!< DCMIPP common status register 2                                    Address offset: 0x3F8 */
+  __IO uint32_t CMFCR;           /*!< DCMIPP common interrupt clear register                             Address offset: 0x3FC */
+       uint32_t RESERVED9;            /*!< Reserved                                                      Address offset: 0x400 */
+  __IO uint32_t P0FSCR;          /*!< DCMIPP Pipe0 flow selection configuration register                 Address offset: 0x404 */
+       uint32_t RESERVED10[62];  /*!< Reserved                                                           Address offset: 0x408-0x4FC */
+  __IO uint32_t P0FCTCR;         /*!< DCMIPP Pipe0 flow control configuration register                   Address offset: 0x500 */
+  __IO uint32_t P0SCSTR;         /*!< DCMIPP Pipe0 stat/crop start register                              Address offset: 0x504 */
+  __IO uint32_t P0SCSZR;         /*!< DCMIPP Pipe0 stat/crop size register                               Address offset: 0x508 */
+       uint32_t RESERVED11[41];  /*!< Reserved                                                           Address offset: 0x50C-0x5AC */
+  __IO uint32_t P0DCCNTR;        /*!< DCMIPP Pipe0 dump counter register                                 Address offset: 0x5B0 */
+  __IO uint32_t P0DCLMTR;        /*!< DCMIPP Pipe0 dump limit register                                   Address offset: 0x5B4 */
+       uint32_t RESERVED12[2];   /*!< Reserved                                                           Address offset: 0x5B8-0x5BC */
+  __IO uint32_t P0PPCR;          /*!< DCMIPP Pipe0 pixel packer configuration register                   Address offset: 0x5C0 */
+  __IO uint32_t P0PPM0AR1;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1               Address offset: 0x5C4 */
+  __IO uint32_t P0PPM0AR2;       /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2               Address offset: 0x5C8 */
+       uint32_t RESERVED13;      /*!< Reserved                                                           Address offset: 0x5C8-0x5CC */
+  __IO uint32_t P0STM0AR;        /*!< DCMIPP Pipe0 status Memory0 address register                       Address offset: 0x5D0 */
+       uint32_t RESERVED14[8];   /*!< Reserved                                                           Address offset: 0x5D4-0x5F0 */
+  __IO uint32_t P0IER;           /*!< DCMIPP Pipe0 interrupt enable register                             Address offset: 0x5F4 */
+  __IO uint32_t P0SR;            /*!< DCMIPP Pipe0 status register                                       Address offset: 0x5F8 */
+  __IO uint32_t P0FCR;           /*!< DCMIPP Pipe0 interrupt clear register                              Address offset: 0x5FC */
+       uint32_t RESERVED15;      /*!< Reserved                                                           Address offset: 0x600 */
+  __IO uint32_t P0CFSCR;         /*!< DCMIPP Pipe0 current flow selection configuration register         Address offset: 0x604 */
+       uint32_t RESERVED17[62];  /*!< Reserved                                                           Address offset: 0x608-0x6FC */
+  __IO uint32_t P0CFCTCR;        /*!< DCMIPP Pipe0 current flow control configuration register           Address offset: 0x700 */
+  __IO uint32_t P0CSCSTR;        /*!< DCMIPP Pipe0 current stat/crop start register                      Address offset: 0x704 */
+  __IO uint32_t P0CSCSZR;        /*!< DCMIPP Pipe0 current stat/crop size register                       Address offset: 0x708 */
+       uint32_t RESERVED18[45];  /*!< Reserved                                                           Address offset: 0x70C-0x7BC */
+  __IO uint32_t P0CPPCR;         /*!< DCMIPP Pipe0 current pixel packer configuration register           Address offset: 0x7C0 */
+  __IO uint32_t P0CPPM0AR1;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1       Address offset: 0x7C4 */
+  __IO uint32_t P0CPPM0AR2;      /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2       Address offset: */
+       uint32_t RESERVED19[14];  /*!< Reserved                                                           Address offset: 0x7C8-0x7FC */
+  __IO uint32_t P1FSCR;          /*!< DCMIPP Pipe1 flow selection configuration register                 Address offset: 0x804 */
+       uint32_t RESERVED20[6];   /*!< Reserved                                                           Address offset: 0x808-0x81C */
+  __IO uint32_t P1SRCR;          /*!< DCMIPP Pipe1 stat removal configuration register                   Address offset: 0x820 */
+  __IO uint32_t P1BPRCR;         /*!< DCMIPP Pipe1 bad pixel removal control register                    Address offset: 0x824 */
+  __IO uint32_t P1BPRSR;         /*!< DCMIPP Pipe1 bad pixel removal status register                     Address offset: 0x828 */
+       uint32_t RESERVED21;      /*!< Reserved                                                           Address offset: 0x82C */
+  __IO uint32_t P1DECR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x830 */
+       uint32_t RESERVED22[3];   /*!< Reserved                                                           Address offset: 0x834-0x83C */
+  __IO uint32_t P1BLCCR;         /*!< DCMIPP Pipe1 black level calibration control register              Address offset: 0x840 */
+  __IO uint32_t P1EXCR1;         /*!< DCMIPP Pipe1 exposure control register 1                           Address offset: 0x844 */
+  __IO uint32_t P1EXCR2;         /*!< DCMIPP Pipe1 exposure control register 2                           Address offset: 0x848 */
+       uint32_t RESERVED23;      /*!< Reserved                                                           Address offset: 0x84C */
+  __IO uint32_t P1ST1CR;         /*!< DCMIPP Pipe1 statistics 1 control register                         Address offset: 0x850 */
+  __IO uint32_t P1ST2CR;         /*!< DCMIPP Pipe1 statistics 2 control register                         Address offset: 0x854 */
+  __IO uint32_t P1ST3CR;         /*!< DCMIPP Pipe1 statistics 3 control register                         Address offset: 0x858 */
+  __IO uint32_t P1STSTR;         /*!< DCMIPP Pipe1 statistics window start register                      Address offset: 0x85C */
+  __IO uint32_t P1STSZR;         /*!< DCMIPP Pipe1 statistics window size register                       Address offset: 0x860 */
+  __IO uint32_t P1ST1SR;         /*!< DCMIPP Pipe1 statistics 1 status register                          Address offset: 0x864 */
+  __IO uint32_t P1ST2SR;         /*!< DCMIPP Pipe1 statistics 2 status register                          Address offset: 0x868 */
+  __IO uint32_t P1ST3SR;         /*!< DCMIPP Pipe1 statistics 3 status register                          Address offset: 0x86C */
+  __IO uint32_t P1DMCR;          /*!< DCMIPP Pipe1 demosaicing configuration register                    Address offset: 0x870 */
+       uint32_t RESERVED24[3];   /*!< Reserved                                                           Address offset: 0x874-0x87C */
+  __IO uint32_t P1CCCR;          /*!< DCMIPP Pipe1 ColorConv configuration register                      Address offset: 0x880 */
+  __IO uint32_t P1CCRR1;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 1                  Address offset: 0x884 */
+  __IO uint32_t P1CCRR2;         /*!< DCMIPP Pipe1 ColorConv red coefficient register 2                  Address offset: 0x888 */
+  __IO uint32_t P1CCGR1;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 1                Address offset: 0x88C */
+  __IO uint32_t P1CCGR2;         /*!< DCMIPP Pipe1 ColorConv green coefficient register 2                Address offset: 0x890 */
+  __IO uint32_t P1CCBR1;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1                 Address offset: 0x894 */
+  __IO uint32_t P1CCBR2;         /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2                 Address offset: 0x898 */
+       uint32_t RESERVED25;      /*!< Reserved                                                           Address offset: 0x89C */
+  __IO uint32_t P1CTCR1;         /*!< DCMIPP Pipe1 contrast control register 1                           Address offset: 0x8A0 */
+  __IO uint32_t P1CTCR2;         /*!< DCMIPP Pipe1 contrast control register 2                           Address offset: 0x8A4 */
+  __IO uint32_t P1CTCR3;         /*!< DCMIPP Pipe1 contrast control register 3                           Address offset: 0x8A8 */
+       uint32_t RESERVED26[21];  /*!< Reserved                                                           Address offset: 0x8AC-0x8FC */
+  __IO uint32_t P1FCTCR;         /*!< DCMIPP Pipe1 flow control configuration register                   Address offset: 0x900 */
+  __IO uint32_t P1CRSTR;         /*!< DCMIPP Pipe1 crop window start register                            Address offset: 0x904 */
+  __IO uint32_t P1CRSZR;         /*!< DCMIPP Pipe1 crop window size register                             Address offset: 0x908 */
+  __IO uint32_t P1DCCR;          /*!< DCMIPP Pipe1 decimation register                                   Address offset: 0x90C */
+  __IO uint32_t P1DSCR;          /*!< DCMIPP Pipe1 downsize configuration register                       Address offset: 0x910 */
+  __IO uint32_t P1DSRTIOR;       /*!< DCMIPP Pipe1 downsize ratio register                               Address offset: 0x914 */
+  __IO uint32_t P1DSSZR;         /*!< DCMIPP Pipe1 downsize destination size register                    Address offset: 0x918 */
+       uint32_t RESERVED28;      /*!< Reserved                                                           Address offset:  */
+  __IO uint32_t P1CMRICR;        /*!< DCMIPP Pipe1 common ROI configuration register                     Address offset: 0x920 */
+  __IO uint32_t P1RIxCR1;        /*!< DCMIPP Pipe1 ROIx configuration register 1                         Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P1RIxCR2;        /*!< DCMIPP Pipe1 ROIx configuration register 2                         Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED29[17];      /*!< Reserved                                                       Address offset:  */
+  __IO uint32_t P1GMCR;          /*!< DCMIPP Pipe1 gamma configuration register                          Address offset: 0x970 */
+       uint32_t RESERVED30[3];   /*!< Reserved                                                           Address offset: 0x974-0x97C */
+  __IO uint32_t P1YUVCR;         /*!< DCMIPP Pipe1 YUVConv configuration register                        Address offset: 0x980 */
+  __IO uint32_t P1YUVRR1;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 1                    Address offset: 0x984 */
+  __IO uint32_t P1YUVRR2;        /*!< DCMIPP Pipe1 YUVConv red coefficient register 2                    Address offset: 0x988 */
+  __IO uint32_t P1YUVGR1;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 1                  Address offset: 0x98C */
+  __IO uint32_t P1YUVGR2;        /*!< DCMIPP Pipe1 YUVConv green coefficient register 2                  Address offset: 0x990 */
+  __IO uint32_t P1YUVBR1;        /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1                   Address offset: 0x994 */
+  __IO uint32_t P1YUVBR2;        /*!< DCMIPP Pipe1 YUV blue coefficient register 2                       Address offset: 0x998 */
+       uint32_t RESERVED31[9];   /*!< Reserved                                                           Address offset: 0x99C-0x9BC */
+  __IO uint32_t P1PPCR;          /*!< DCMIPP Pipe1 pixel packer configuration register                   Address offset: 0x9C0 */
+  __IO uint32_t P1PPM0AR1;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1               Address offset: 0x9C4 */
+  __IO uint32_t P1PPM0AR2;       /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2               Address offset: 0x9C8 */
+  __IO uint32_t P1PPM0PR;        /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register                   Address offset: 0x9CC */
+  __IO uint32_t P1STM0AR;        /*!< DCMIPP Pipe1 status Memory0 address register                       Address offset: 0x9D0 */
+  __IO uint32_t P1PPM1AR1;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1               Address offset: 0x9D4 */
+  __IO uint32_t P1PPM1AR2;       /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2               Address offset: 0x9D8 */
+  __IO uint32_t P1PPM1PR;        /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register                   Address offset: 0x9DC */
+  __IO uint32_t P1STM1AR;        /*!< DCMIPP Pipe1 status Memory1 address register                       Address offset: 0x9E0 */
+  __IO uint32_t P1PPM2AR1;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 1               Address offset: 0x9E4 */
+  __IO uint32_t P1PPM2AR2;       /*!< DCMIPP Pipe1 pixel packer memory2 address register 2               Address offset: 0x9E8 */
+  __IO uint32_t RESERVED34;      /*!< Reserved                                                           Address offset: 0x9EC */
+  __IO uint32_t P1STM2AR;        /*!< DCMIPP Pipe1 status Memory2 address register                       Address offset: 0x9F0 */
+  __IO uint32_t P1IER;           /*!< DCMIPP Pipe1 interrupt enable register                             Address offset: 0x9F4 */
+  __IO uint32_t P1SR;            /*!< DCMIPP Pipe1 status register                                       Address offset: 0x9F8 */
+  __IO uint32_t P1FCR;           /*!< DCMIPP Pipe1 interrupt clear register                              Address offset: 0x9FC */
+       uint32_t RESERVED35;      /*!< Reserved                                                           Address offset: 0xA00 */
+  __IO uint32_t P1CFSCR;         /*!< DCMIPP Pipe1 current flow selection configuration register         Address offset: 0xA04 */
+       uint32_t RESERVED36[7];   /*!< Reserved                                                           Address offset: 0xA08-0xA20 */
+  __IO uint32_t P1CBPRCR;        /*!< DCMIPP Pipe1 current bad pixel removal register                    Address offset: 0xA24 */
+       uint32_t RESERVED37[6];   /*!< Reserved                                                           Address offset: 0xA28-0xA3C */
+  __IO uint32_t P1CBLCCR;        /*!< DCMIPP Pipe1 current black level calibration control register      Address offset: 0xA40 */
+  __IO uint32_t P1CEXCR1;        /*!< DCMIPP Pipe1 current exposure control register 1                   Address offset: 0xA44 */
+  __IO uint32_t P1CEXCR2;        /*!< DCMIPP Pipe1 current exposure control register 2                   Address offset: 0xA48 */
+       uint32_t RESERVED38;      /*!< Reserved                                                           Address offset: 0xA4C */
+  __IO uint32_t P1CST1CR;        /*!< DCMIPP Pipe1 current statistics 1 control register                 Address offset: 0xA50 */
+  __IO uint32_t P1CST2CR;        /*!< DCMIPP Pipe1 current statistics 2 control register                 Address offset: 0xA54 */
+  __IO uint32_t P1CST3CR;        /*!< DCMIPP Pipe1 current statistics 3 control register                 Address offset: 0xA58 */
+  __IO uint32_t P1CSTSTR;        /*!< DCMIPP Pipe1 current statistics window start register              Address offset: 0xA5C */
+  __IO uint32_t P1CSTSZR;        /*!< DCMIPP Pipe1 current statistics window size register               Address offset: 0xA60 */
+       uint32_t RESERVED39[7];   /*!< Reserved                                                           Address offset: 0xA64-0xA7C */
+  __IO uint32_t P1CCCCR;         /*!< DCMIPP Pipe1 current ColorConv configuration register              Address offset: 0xA80 */
+  __IO uint32_t P1CCCRR1;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1          Address offset: 0xA84 */
+  __IO uint32_t P1CCCRR2;        /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2          Address offset: 0xA88 */
+  __IO uint32_t P1CCCGR1;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1        Address offset: 0xA8C */
+  __IO uint32_t P1CCCGR2;        /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2        Address offset: 0xA90 */
+  __IO uint32_t P1CCCBR1;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1         Address offset: 0xA94 */
+  __IO uint32_t P1CCCBR2;        /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2         Address offset: 0xA98 */
+       uint32_t RESERVED40;      /*!< Reserved                                                           Address offset: 0xA9C */
+  __IO uint32_t P1CCTCR1;        /*!< DCMIPP Pipe1 current contrast control register 1                   Address offset: 0xAA0 */
+  __IO uint32_t P1CCTCR2;        /*!< DCMIPP Pipe1 current contrast control register 2                   Address offset: 0xAA4 */
+  __IO uint32_t P1CCTCR3;        /*!< DCMIPP Pipe1 current contrast control register 3                   Address offset: 0xAA8 */
+       uint32_t RESERVED41[21];  /*!< Reserved                                                           Address offset: 0xAAC-0xAFC */
+  __IO uint32_t P1CFCTCR;        /*!< DCMIPP Pipe1 current flow control configuration register           Address offset: 0xB00 */
+  __IO uint32_t P1CCRSTR;        /*!< DCMIPP Pipe1 current crop window start register                    Address offset: 0xB04 */
+  __IO uint32_t P1CCRSZR;        /*!< DCMIPP Pipe1 current crop window size register                     Address offset: 0xB08 */
+  __IO uint32_t P1CDCCR;         /*!< DCMIPP Pipe1 current decimation register                           Address offset: 0xB0C */
+  __IO uint32_t P1CDSCR;         /*!< DCMIPP Pipe1 current downsize configuration register               Address offset: 0xB10 */
+  __IO uint32_t P1CDSRTIOR;      /*!< DCMIPP Pipe1 current downsize ratio register                       Address offset: 0xB14 */
+  __IO uint32_t P1CDSSZR;        /*!< DCMIPP Pipe1 current downsize destination size register            Address offset: 0xB18 */
+       uint32_t RESERVED43;      /*!< Reserved                                                           Address offset: 0xB1C */
+       uint32_t P1CCMRICR;       /*!< DCMIPP Pipe1 current common ROI configuration register             Address offset: 0xB20 */
+  __IO uint32_t P1CRIxCR1;       /*!< DCMIPP Pipe1 current ROIx configuration register 1                 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */
+  __IO uint32_t P1CRIxCR2;       /*!< DCMIPP Pipe1 current ROIx configuration register 2                 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */
+  uint32_t RESERVED44[37];       /*!< Reserved                                                           Address offset: 0xB64-0xBBC */
+  __IO uint32_t P1CPPCR;         /*!< DCMIPP Pipe1 current pixel packer configuration register           Address offset: 0xBC0 */
+  __IO uint32_t P1CPPM0AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC4 */
+  __IO uint32_t P1CPPM0AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1       Address offset: 0xBC8 */
+  __IO uint32_t P1CPPM0PR;       /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register           Address offset: 0xBCC */
+       uint32_t RESERVED45;      /*!< Reserved                                                           Address offset: 0xBD0 */
+  __IO uint32_t P1CPPM1AR1;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1       Address offset: 0xBD4 */
+  __IO uint32_t P1CPPM1AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2       Address offset: 0xBD8 */
+  __IO uint32_t P1CPPM1PR;       /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register           Address offset: 0xBDC */
+       uint32_t RESERVED47;      /*!< Reserved                                                           Address offset: 0xBE0 */
+  __IO uint32_t P1CPPM2AR1;      /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1       Address offset: 0xBE4 */
+  __IO uint32_t P1CPPM2AR2;      /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2       Address offset: 0xBE8 */
+       uint32_t RESERVED48[6];   /*!< Reserved                                                           Address offset: 0xBE8-0xBFC */
+  __IO uint32_t P2FSCR;          /*!< DCMIPP Pipe2 flow selection configuration register                 Address offset: 0xC04 */
+       uint32_t RESERVED49[62];  /*!< Reserved                                                           Address offset: 0xC08-0xCFC */
+  __IO uint32_t P2FCTCR;         /*!< DCMIPP Pipe2 flow control configuration register                   Address offset: 0xD00 */
+  __IO uint32_t P2CRSTR;         /*!< DCMIPP Pipe2 crop window start register                            Address offset: 0xD04 */
+  __IO uint32_t P2CRSZR;         /*!< DCMIPP Pipe2 crop window size register                             Address offset: 0xD08 */
+  __IO uint32_t P2DCCR;          /*!< DCMIPP Pipe2 decimation register                                   Address offset: 0xD0C */
+  __IO uint32_t P2DSCR;          /*!< DCMIPP Pipe2 downsize configuration register                       Address offset: 0xD10 */
+  __IO uint32_t P2DSRTIOR;       /*!< DCMIPP Pipe2 downsize ratio register                               Address offset: 0xD14 */
+  __IO uint32_t P2DSSZR;         /*!< DCMIPP Pipe2 downsize destination size register                    Address offset: 0xD18 */
+       uint32_t RESERVED51;      /*!< Reserved                                                           Address offset:  0xD1C */
+  __IO uint32_t P2CMRICR;        /*!< DCMIPP Pipe2 common ROI configuration register                     Address offset:  0xD20 */
+  __IO uint32_t P2RIxCR1;        /*!< DCMIPP Pipe2 ROIx configuration register 1                         Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */
+  __IO uint32_t P2RIxCR2;        /*!< DCMIPP Pipe2 ROIx configuration register 2                         Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */
+       uint32_t RESERVED53[17];  /*!< Reserved                                                           Address offset: */
+  __IO uint32_t P2GMCR;          /*!< DCMIPP Pipe2 gamma configuration register                          Address offset: 0xD70 */
+       uint32_t RESERVED54[19];  /*!< Reserved                                                           Address offset: 0xD74-0xDBC */
+  __IO uint32_t P2PPCR;          /*!< DCMIPP Pipe2 pixel packer configuration register                   Address offset: 0xDC0 */
+  __IO uint32_t P2PPM0AR1;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1               Address offset: 0xDC4 */
+  __IO uint32_t P2PPM0AR2;       /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2               Address offset: 0xDC8 */
+  __IO uint32_t P2PPM0PR;        /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register                   Address offset: 0xDCC */
+  __IO uint32_t P2STM0AR;        /*!< DCMIPP Pipe2 status Memory0 address register                       Address offset: 0xDD0 */
+       uint32_t RESERVED55[8];   /*!< Reserved                                                           Address offset: 0xDD4-0xDF0 */
+  __IO uint32_t P2IER;           /*!< DCMIPP Pipe2 interrupt enable register                             Address offset: 0xDF4 */
+  __IO uint32_t P2SR;            /*!< DCMIPP Pipe2 status register                                       Address offset: 0xDF8 */
+  __IO uint32_t P2FCR;           /*!< DCMIPP Pipe2 interrupt clear register                              Address offset: 0xDFC */
+       uint32_t RESERVED56;      /*!< Reserved                                                           Address offset: 0xE00 */
+  __IO uint32_t P2CFSCR;         /*!< DCMIPP Pipe2 current flow selection configuration register         Address offset: 0xE04 */
+       uint32_t RESERVED57[62];  /*!< Reserved                                                           Address offset: 0xE08-0xEFC */
+  __IO uint32_t P2CFCTCR;        /*!< DCMIPP Pipe2 current flow control configuration register           Address offset: 0xF00 */
+  __IO uint32_t P2CCRSTR;        /*!< DCMIPP Pipe2 current crop window start register                    Address offset: 0xF04 */
+  __IO uint32_t P2CCRSZR;        /*!< DCMIPP Pipe2 current crop window size register                     Address offset: 0xF08 */
+  __IO uint32_t P2CDCCR;         /*!< DCMIPP Pipe2 current decimation register                           Address offset: 0xF0C */
+  __IO uint32_t P2CDSCR;         /*!< DCMIPP Pipe2 current downsize configuration register               Address offset: 0xF10 */
+  __IO uint32_t P2CDSRTIOR;      /*!< DCMIPP Pipe2 current downsize ratio register                       Address offset: 0xF14 */
+  __IO uint32_t P2CDSSZR;        /*!< DCMIPP Pipe2 current downsize destination size register            Address offset: 0xF18 */
+  __IO uint32_t RESERVED59[2];   /*!< Reserved                                                           Address offset: 0xF1C-0xF20 */
+  __IO uint32_t P2CRIxCR1;       /*!< Pipe2 current ROIx configuration register 1                        Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/
+  __IO uint32_t P2CRIxCR2;       /*!< Pipe2 current ROIx configuration register 2                        Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/
+       uint32_t RESERVED60[37];  /*!< Reserved                                                           Address offset: 0xF64-0xFBC */
+  __IO uint32_t P2CPPCR;         /*!< DCMIPP Pipe2 current pixel packer configuration register           Address offset: 0xFC0 */
+  __IO uint32_t P2CPPM0AR1;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1       Address offset: 0xFC4 */
+  __IO uint32_t P2CPPM0AR2;      /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2       Address offset: 0xFC8 */
+  __IO uint32_t P2CPPM0PR;       /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register           Address offset: 0xFCC */
+       uint32_t RESERVED61[7];   /*!< Reserved                                                           Address offset: 0xFD0-0xFE8 */
+  __IO uint32_t HWCFGR2;         /*!< DCMIPP hardware configuration register 2                           Address offset: 0xFEC */
+  __IO uint32_t HWCFGR1;         /*!< DCMIPP hardware configuration register 1                           Address offset: 0xFF0 */
+  __IO uint32_t VERR;            /*!< DCMIPP version register                                            Address offset: 0xFF4 */
+  __IO uint32_t IPIDR;           /*!< DCMIPP identification register                                     Address offset: 0xFF8 */
+  __IO uint32_t SIDR;            /*!< DCMIPP size identification register                                Address offset: 0xFFC */
+} DCMIPP_TypeDef;
+
+/**
+  * @ brief Delay Block
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< Delay Block Control Register,       Address offset: 0x00 */
+  __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t SECCFGR;      /*!< DMA secure configuration register,               Address offset: 0x00  */
+  __IO uint32_t PRIVCFGR;     /*!< DMA privileged configuration register,           Address offset: 0x04 */
+  __IO uint32_t RCFGLOCKR;    /*!< DMA configuration lock register,                 Address offset: 0x08 */
+  __IO uint32_t MISR;         /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
+  __IO uint32_t SMISR;        /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CLBAR;         /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
+  __IO uint32_t CCIDCFGR;      /*!< DMA channel x CID register,                      Address offset: 0x54 + (x * 0x80) */
+       uint32_t RESERVED1[1];  /*!< Reserved 1,                                      Address offset: 0x58 + (x * 0x80) */
+  __IO uint32_t CFCR;          /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
+  __IO uint32_t CSR;           /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
+  __IO uint32_t CCR;           /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
+       uint32_t RESERVED2[10]; /*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C + (x * 0x80) */
+  __IO uint32_t CTR1;          /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
+  __IO uint32_t CTR2;          /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
+  __IO uint32_t CBR1;          /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
+  __IO uint32_t CSAR;          /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
+  __IO uint32_t CDAR;          /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
+  __IO uint32_t CTR3;          /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
+  __IO uint32_t CBR2;          /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
+       uint32_t RESERVED3[8];  /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8 + (x * 0x80) */
+  __IO uint32_t CLLR;          /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
+} DMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
+} DMA2D_TypeDef;
+
+/**
+  * @brief DTS Controller
+  */
+typedef struct
+{
+  uint32_t      RESERVED1[4];    /*!< Reserved,                                 Address offset: 0x00-0x0F */
+  __IO uint32_t PVTREG_LOCKR;    /*!< DTS PVT Register Lock Register,           Address offset: 0x10 */
+  __IO uint32_t PVTLOCK_SR;      /*!< DTS PVT Lock Status Register,             Address offset: 0x14 */
+  uint32_t      RESERVED2[2];    /*!< Reserved,                                 Address offset: 0x18-0x1F */
+  __IO uint32_t PVTTMR_CR;       /*!< DTS PVT Timer Control Register,           Address offset: 0x20 */
+  __IO uint32_t PVTTMR_SR;       /*!< DTS PVT Timer Status Register,            Address offset: 0x24 */
+  uint32_t      RESERVED3[6];    /*!< Reserved,                                 Address offset: 0x28-0x3F */
+  __IO uint32_t PVT_IER;         /*!< DTS PVT IRQ Enable Register,              Address offset: 0x40 */
+  uint32_t      RESERVED4[3];    /*!< Reserved,                                 Address offset: 0x44-0x4F */
+  __IO uint32_t PVTIRQTRMASKR;   /*!< DTS PVT IRQ Timer Mask Register,          Address offset: 0x50 */
+  __IO uint32_t TS_MR;           /*!< DTS PVT IRQ TS Mask Register,             Address offset: 0x54 */
+  uint32_t      RESERVED5[2];    /*!< Reserved,                                 Address offset: 0x58-0x5F */
+  __IO uint32_t PVTTR_SR;        /*!< DTS PVT IRQ Timer Status Register,        Address offset: 0x60 */
+  __IO uint32_t TS_ISR;          /*!< DTS PVT IRQ TS Status Register,           Address offset: 0x64 */
+  uint32_t      RESERVED6[2];    /*!< Reserved,                                 Address offset: 0x68-0x6F */
+  __IO uint32_t PVTTMRRAW_ISR;   /*!< DTS PVT IRQ Timer Raw Status Register,    Address offset: 0x70 */
+  __IO uint32_t TSRAW_ISR;       /*!< DTS PVT IRQ TS Raw Status Register,       Address offset: 0x74 */
+  uint32_t      RESERVED7[2];    /*!< Reserved,                                 Address offset: 0x78-0x7F */
+  __IO uint32_t TSCCLKSYNTHR;    /*!< DTS TSC Clock Synthesizer Register,       Address offset: 0x80 */
+  __IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register,  Address offset: 0x84 */
+  __IO uint32_t TSCSDIF_SR;      /*!< DTS TSC SDIF Status Register,             Address offset: 0x88 */
+  __IO uint32_t TSCSDIF_CR;      /*!< DTS TSC SDIF Register,                    Address offset: 0x8C */
+  __IO uint32_t TSCSDIFHALTR;    /*!< DTS TSC SDIF Halt Register,               Address offset: 0x90 */
+  __IO uint32_t TSCSDIF_CFGR;    /*!< DTS TSC SDIF Control Register,            Address offset: 0x94 */
+  uint32_t      RESERVED8[2];    /*!< Reserved,                                 Address offset: 0x98-0x9F */
+  __IO uint32_t TSCSMPL_CR;      /*!< DTS TSC Sample Control Register,          Address offset: 0xA0 */
+  __IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register,            Address offset: 0xA4 */
+  __IO uint32_t TSCSMPLCNTR;     /*!< DTS TSC Sample Count Register,            Address offset: 0xA8 */
+} DTS_TypeDef;
+
+/**
+  * @brief DTS Sensor Controller
+  */
+typedef struct
+{
+  __IO uint32_t TS_IER;          /*!< DTS TSx IRQ Enable Register,              Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ISR;          /*!< DTS TSx IRQ Status Register,              Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TS_ICR;          /*!< DTS TSx IRQ Clear Register,               Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSIRQTESTR;      /*!< DTS TSx IRQ Test Register,                Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFRDATAR;    /*!< DTS TSx SDIF RDATA Register,              Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDONER;     /*!< DTS TSx SDIF Done Register,               Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSSDIFDATAR;     /*!< DTS TSx SDIF Data Register,               Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */
+  uint32_t      RESERVED1[1];    /*!< Reserved,                                 Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMA_CFGR;   /*!< DTS TSx Alarm A Configuration Register,   Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSALARMB_CFGR;   /*!< DTS TSx Alarm B Configuration Register,   Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHLSAMPLER;     /*!< DTS TSx High/Low Sample Register,         Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */
+  __IO uint32_t TSHILORESETR;    /*!< DTS TSx High/Low Reset Register,          Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */
+} DTS_SensorTypeDef;
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;               /*!< Operating mode configuration register,                        Address offset: 0x00 */
+  __IO uint32_t MACECR;              /*!< Extended operating mode configuration register,               Address offset: 0x04 */
+  __IO uint32_t MACPFR;              /*!< Packet filtering control register             ,               Address offset: 0x08 */
+  __IO uint32_t MACWTR;              /*!< Watchdog timeout register,                                    Address offset: 0x0C */
+  __IO uint32_t MACHT0R;             /*!< Hash Table 0 register,                                        Address offset: 0x10 */
+  __IO uint32_t MACHT1R;             /*!< Hash Table 1 register,                                        Address offset: 0x14 */
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTCR;             /*!< VLAN tag Control register,                                    Address offset: 0x50 */
+  __IO uint32_t MACVTDR;             /*!< VLAN tag data register,                                       Address offset: 0x54 */
+  __IO uint32_t MACVHTR;             /*!< VLAN Hash table register,                                     Address offset: 0x58 */
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVIR;              /*!< VLAN inclusion register,                                      Address offset: 0x60 */
+  __IO uint32_t MACIVIR;             /*!< Inner VLAN inclusion register,                                Address offset: 0x64 */
+  uint32_t      RESERVED3[2];
+  __IO uint32_t MACQ0TXFCR;          /*!< Tx Queue 0 flow control register,                             Address offset: 0x70 */
+  uint32_t      RESERVED4[7];
+  __IO uint32_t MACRXFCR;            /*!< Rx flow control register,                                     Address offset: 0x90 */
+  __IO uint32_t MACRXQCR;            /*!< Rx Queue control register,                                    Address offset: 0x94 */
+  uint32_t      RESERVED5[2];
+  __IO uint32_t MACRXQC0R;           /*!< Rx queue control 0 register,                                  Address offset: 0xA0 */
+  __IO uint32_t MACRXQC1R;           /*!< Rx queue control 1 register,                                  Address offset: 0xA4 */
+  __IO uint32_t MACRXQC2R;           /*!< Rx queue control 2 register,                                  Address offset: 0xA8 */
+  uint32_t      RESERVED6;
+  __IO uint32_t MACISR;              /*!< Interrupt status register,                                    Address offset: 0xB0 */
+  __IO uint32_t MACIER;              /*!< Interrupt enable register,                                    Address offset: 0xB4 */
+  __IO uint32_t MACRXTXSR;           /*!< Rx Tx status register,                                        Address offset: 0xB8 */
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;             /*!< PMT control status register,                                  Address offset: 0xC0 */
+  __IO uint32_t MACRWKPFR;           /*!< Remote wakeup packet filter register,                         Address offset: 0xC4 */
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;             /*!< LPI control and status register,                              Address offset: 0xD0 */
+  __IO uint32_t MACLTCR;             /*!< LPI timers control register,                                  Address offset: 0xD4 */
+  __IO uint32_t MACLETR;             /*!< LPI entry timer register,                                     Address offset: 0xD8 */
+  __IO uint32_t MAC1USTCR;           /*!< One-microsecond-tick counter register,                        Address offset: 0xDC */
+  uint32_t      RESERVED9[6];
+  __IO uint32_t MACPHYCSR;           /*!< PHYIF control status register,                                Address offset: 0xF8 */
+  uint32_t      RESERVED10[5];
+  __IO uint32_t MACVR;               /*!< Version register,                                             Address offset: 0x110 */
+  __IO uint32_t MACDR;               /*!< Debug register,                                               Address offset: 0x114 */
+  uint32_t      RESERVED11;
+  __IO uint32_t MACHWF0R;            /*!< HW feature 0 register,                                        Address offset: 0x11C */
+  __IO uint32_t MACHWF1R;            /*!< HW feature 1 register,                                        Address offset: 0x120 */
+  __IO uint32_t MACHWF2R;            /*!< HW feature 2 register,                                        Address offset: 0x124 */
+  __IO uint32_t MACHWF3R;            /*!< HW feature 3 register,                                        Address offset: 0x128 */
+  uint32_t      RESERVED12[53];
+  __IO uint32_t MACMDIOAR;           /*!< MDIO address register,                                        Address offset: 0x200 */
+  __IO uint32_t MACMDIODR;           /*!< MDIO data register,                                           Address offset: 0x204 */
+  uint32_t      RESERVED13[2];
+  __IO uint32_t MACARPAR;            /*!< ARP address register,                                         Address offset: 0x210 */
+  uint32_t      RESERVED14[7];
+  __IO uint32_t MACCSRSWCR;          /*!< CSR software control register,                                Address offset: 0x230 */
+  __IO uint32_t MACFPECSR;           /*!< FPE control and status register,                              Address offset: 0x234 */
+   uint32_t     RESERVED15[2];
+  __IO uint32_t MACPRSTIMR;          /*!< MAC presentation time register,                               Address offset: 0x0240 */
+  __IO uint32_t MACPRSTIMUR;         /*!< MAC presentation time update register,                        Address offset: 0x0244 */
+   uint32_t     RESERVED16[46];
+  __IO uint32_t MACA0HR;             /*!< MAC Address 0 high register,                                  Address offset: 0x0300 */
+  __IO uint32_t MACA0LR;             /*!< MAC Address 0 low register,                                   Address offset: 0x0304 */
+  __IO uint32_t MACA1HR;             /*!< MAC Address 1 high register,                                  Address offset: 0x0308 */
+  __IO uint32_t MACA1LR;             /*!< MAC Address 1 low register,                                   Address offset: 0x030C */
+  __IO uint32_t MACA2HR;             /*!< MAC Address 2 high register,                                  Address offset: 0x0310 */
+  __IO uint32_t MACA2LR;             /*!< MAC Address 2 low register,                                   Address offset: 0x0314 */
+  __IO uint32_t MACA3HR;             /*!< MAC Address 3 high register,                                  Address offset: 0x0318 */
+  __IO uint32_t MACA3LR;             /*!< MAC Address 3 low register,                                   Address offset: 0x031C */
+  uint32_t      RESERVED17[248];
+  __IO uint32_t MMCCR;               /*!< MMC control register,                                         Address offset: 0x0700 */
+  __IO uint32_t MMCRIR;              /*!< MMC Rx interrupt register,                                    Address offset: 0x0704 */
+  __IO uint32_t MMCTIR;              /*!< MMC Tx interrupt register,                                    Address offset: 0x0708 */
+  __IO uint32_t MMCRIMR;             /*!< MMC Rx interrupt mask register,                               Address offset: 0x070C */
+  __IO uint32_t MMCTIMR;             /*!< MMC Tx interrupt mask register,                               Address offset: 0x0710 */
+  uint32_t      RESERVED18[14];
+  __IO uint32_t MMCTSCGPR;           /*!< Tx single collision good packets register,                    Address offset: 0x074C */
+  __IO uint32_t MMCTMCGPR;           /*!< Tx multiple collision good packets register,                  Address offset: 0x0750 */
+  uint32_t      RESERVED19[5];
+  __IO uint32_t MMCTPCGR;            /*!< Tx packet count good register,                                Address offset: 0x0768 */
+  uint32_t      RESERVED20[10];
+  __IO uint32_t MMCRCRCEPR;          /*!< Rx CRC error packets register,                                Address offset: 0x0794 */
+  __IO uint32_t MMCRAEPR;            /*!< Rx alignment error packets register,                          Address offset: 0x0798 */
+  uint32_t      RESERVED21[10];
+  __IO uint32_t MMCRUPGR;            /*!< Rx unicast packets good register,                             Address offset: 0x07C4 */
+  uint32_t      RESERVED22[9];
+  __IO uint32_t MMCTLPIMSTR;         /*!< Tx LPI microsecond timer register,                            Address offset: 0x07EC */
+  __IO uint32_t MMCTLPITCR;          /*!< Tx LPI transition counter register,                           Address offset: 0x07F0 */
+  __IO uint32_t MMCRLPIMSTR;         /*!< Rx LPI microsecond counter register,                          Address offset: 0x07F4 */
+  __IO uint32_t MMCRLPITCR;          /*!< Rx LPI transition counter register,                           Address offset: 0x07F8 */
+  uint32_t      RESERVED23[41];
+  __IO uint32_t MMCFPETISR;          /*!< MMC FPE Tx interrupt status register,                         Address offset: 0x08A0 */
+  __IO uint32_t MMCFPETIMR;          /*!< MMC FPE Tx interrupt mask register,                           Address offset: 0x08A4 */
+  __IO uint32_t MMCFPETFCR;          /*!< MMC FPE Tx fragment counter register,       -                 Address offset: 0x08A8 */
+  __IO uint32_t MMCTHRCR;            /*!< MMC Tx hold request counter register,                         Address offset: 0x08AC */
+  uint32_t      RESERVED24[4];
+  __IO uint32_t MMCFPERISR;          /*!< MMC FPE Rx interrupt status register,                         Address offset: 0x08C0 */
+  __IO uint32_t MMCFPERIMR;          /*!< MMC FPE Rx interrupt mask register,                           Address offset: 0x08C4 */
+  __IO uint32_t MMCRPAER;            /*!< MMC Rx packet assembly error register,                        Address offset: 0x08C8 */
+  __IO uint32_t MMCRPSMDER;          /*!< MMC Rx packet SMD error register,                             Address offset: 0x08CC */
+  __IO uint32_t MMCRPAOKR;           /*!< MMC Rx packet assembly OK register,                           Address offset: 0x08D0 */
+  __IO uint32_t MMCFPERFCR;          /*!< MMC Rx FPE fragments counter register,                        Address offset: 0x08D4 */
+  uint32_t      RESERVED25[10];
+  __IO uint32_t MACL3L4C0R;          /*!< L3 and L4 control 0 register,                                 Address offset: 0x0900 */
+  __IO uint32_t MACL4A0R;            /*!< Layer4 Address filter 0 register,                             Address offset: 0x0904 */
+  uint32_t      RESERVED26[2];
+  __IO uint32_t MACL3A0R0R;           /*!< Layer3 Address 0 filter 0 register,                           Address offset: 0x0910 */
+  __IO uint32_t MACL3A1R0R;           /*!< Layer3 Address 1 filter 0 register,                           Address offset: 0x0914 */
+  __IO uint32_t MACL3A2R0R;           /*!< Layer3 Address 2 filter 0 register,                           Address offset: 0x0918 */
+  __IO uint32_t MACL3A3R0R;           /*!< Layer3 Address 3 filter 0 register,                           Address offset: 0x091C */
+  uint32_t      RESERVED27[4];
+  __IO uint32_t MACL3L4C1R;          /*!< L3 and L4 control 1 register,                                 Address offset: 0x0930 */
+  __IO uint32_t MACL4A1R;            /*!< Layer 4 address filter 1 register,                            Address offset: 0x0934 */
+  uint32_t      RESERVED28[2];
+  __IO uint32_t MACL3A01R;           /*!< Layer3 address 0 filter 1 Register,                           Address offset: 0x0940 */
+  __IO uint32_t MACL3A11R;           /*!< Layer3 address 1 filter 1 register,                           Address offset: 0x0944 */
+  __IO uint32_t MACL3A21R;           /*!< Layer3 address 2 filter 1 Register,                           Address offset: 0x0948 */
+  __IO uint32_t MACL3A31R;           /*!< Layer3 address 3 filter 1 register,                           Address offset: 0x094C */
+  uint32_t      RESERVED29[72];
+  __IO uint32_t MACIACR;             /*!< MAC Indirect Access Control register,                         Address offset: 0x0A70 */
+  __IO uint32_t MACTMRQR;            /*!< MAC type-based Rx Queue mapping register,                     Address offset: 0x0A74 */
+  uint32_t      RESERVED30[34];
+  __IO uint32_t MACTSCR;             /*!< Timestamp control Register,                                   Address offset: 0x0B00 */
+  __IO uint32_t MACSSIR;             /*!< Subsecond increment register,                                 Address offset: 0x0B04 */
+  __IO uint32_t MACSTSR;             /*!< System time seconds register,                                 Address offset: 0x0B08 */
+  __IO uint32_t MACSTNR;             /*!< System time nanoseconds register,                             Address offset: 0x0B0C */
+  __IO uint32_t MACSTSUR;            /*!< System time seconds update register,                          Address offset: 0x0B10 */
+  __IO uint32_t MACSTNUR;            /*!< System time nanoseconds update register,                      Address offset: 0x0B14 */
+  __IO uint32_t MACTSAR;             /*!< Timestamp addend register,                                    Address offset: 0x0B18 */
+  uint32_t      RESERVED31;
+  __IO uint32_t MACTSSR;             /*!< Timestamp status register,                                    Address offset: 0x0B20 */
+  uint32_t      RESERVED32[3];
+  __IO uint32_t MACTXTSSNR;          /*!< Tx timestamp status nanoseconds register,                     Address offset: 0x0B30 */
+  __IO uint32_t MACTXTSSSR;          /*!< Tx timestamp status seconds register,                         Address offset: 0x0B34 */
+  uint32_t      RESERVED33[2];
+  __IO uint32_t MACACR;              /*!< Auxiliary control register,                                   Address offset: 0x0B40 */
+  uint32_t      RESERVED34;
+  __IO uint32_t MACATSNR;            /*!< Auxiliary timestamp nanoseconds register,                     Address offset: 0x0B48 */
+  __IO uint32_t MACATSSR;            /*!< Auxiliary timestamp seconds register,                         Address offset: 0x0B4C */
+  __IO uint32_t MACTSIACR;           /*!< Timestamp Ingress asymmetric correction register,             Address offset: 0x0B50 */
+  __IO uint32_t MACTSEACR;           /*!< Timestamp Egress asymmetric correction register,              Address offset: 0x0B54 */
+  __IO uint32_t MACTSICNR;           /*!< Timestamp Ingress correction nanosecond register,             Address offset: 0x0B58 */
+  __IO uint32_t MACTSECNR;           /*!< Timestamp Egress correction nanosecond register,              Address offset: 0x0B5C */
+  uint32_t      RESERVED35[2];
+  __IO uint32_t MACTSILR;            /*!< Timestamp Ingress Latency register,                           Address offset: 0x0B68 */
+  __IO uint32_t MACTSELR;            /*!< Timestamp Egress Latency register,                            Address offset: 0x0B6C */
+  __IO uint32_t MACPPSCR;            /*!< PPS control register,                                         Address offset: 0x0B70 */
+  uint32_t      RESERVED36[3];
+  __IO uint32_t MACPPSTTS0R;         /*!< PPS 0 target time seconds register,                           Address offset: 0x0B80 */
+  __IO uint32_t MACPPSTTN0R;         /*!< PPS 0 target time nanoseconds register,                       Address offset: 0x0B84 */
+  __IO uint32_t MACPPSI0R;           /*!< PPS 0 interval register,                                      Address offset: 0x0B88 */
+  __IO uint32_t MACPPSW0R;           /*!< PPS 0 width register,                                         Address offset: 0x0B8C */
+  __IO uint32_t MACPPSTTS1R;         /*!< PPS 1 target time seconds register,                           Address offset: 0x0B90 */
+  __IO uint32_t MACPPSTTN1R;         /*!< PPS 1 target time nanoseconds register,                       Address offset: 0x0B94 */
+  __IO uint32_t MACPPSI1R;           /*!< PPS 1 interval register,                                      Address offset: 0x0B98 */
+  __IO uint32_t MACPPSW1R;           /*!< PPS 1 width register,                                         Address offset: 0x0B9C */
+  uint32_t      RESERVED37[8];
+  __IO uint32_t MACPOCR;             /*!< PTP Offload control register,                                 Address offset: 0x0BC0 */
+  __IO uint32_t MACSPI0R;            /*!< PTP Source Port Identity 0 Register,                          Address offset: 0x0BC4 */
+  __IO uint32_t MACSPI1R;            /*!< PTP Source port identity 1 register,                          Address offset: 0x0BC8 */
+  __IO uint32_t MACSPI2R;            /*!< PTP Source port identity 2 register,                          Address offset: 0x0BCC */
+  __IO uint32_t MACLMIR;             /*!< Log message interval register,                                Address offset: 0x0BD0 */
+  uint32_t      RESERVED38[11];
+  __IO uint32_t MTLOMR;              /*!< Operating mode Register,                                      Address offset: 0x0C00 */
+  uint32_t      RESERVED39[7];
+  __IO uint32_t MTLISR;              /*!< Interrupt status Register,                                    Address offset: 0x0C20 */
+  uint32_t      RESERVED40[3];
+  __IO uint32_t MTLRXQDMAMR;         /*!< Rx Queue and DMA Channel Mapping Register,                    Address offset: 0x0C30 */
+  uint32_t      RESERVED41[3];
+  __IO uint32_t MTLTBSCR;            /*!< TBS control register,                                         Address offset: 0x0C40 */
+  uint32_t      RESERVED42[3];
+  __IO uint32_t MTLESTCR;            /*!< EST Control Register,                                         Address offset: 0x0C50 */
+  __IO uint32_t MTLESTECR;           /*!< EST Extended Control Register,                                Address offset: 0x0C54 */
+  __IO uint32_t MTLESTSR;            /*!< EST Status Register,                                          Address offset: 0x0C58 */
+  uint32_t      RESERVED43;
+  __IO uint32_t MTLESTSCHER;         /*!< EST Schedule Error Register,                                  Address offset: 0x0C60 */
+  __IO uint32_t MTLESTFSER;          /*!< EST Frame size Error Register,                                Address offset: 0x0C64 */
+  __IO uint32_t MTLESTFSCR;          /*!< EST Frame size Capture Register,                              Address offset: 0x0C68 */
+  uint32_t      RESERVED44;
+  __IO uint32_t MTLESTIER;           /*!< EST Interrupt Enable Register,                                Address offset: 0x0C70 */
+  uint32_t      RESERVED45[3];
+  __IO uint32_t MTLESTGCLCR;         /*!< EST Gate Control List Register,                               Address offset: 0x0C80 */
+  __IO uint32_t MTLESTGCLDR;         /*!< EST Gate Control List Data Register,                          Address offset: 0x0C84 */
+  uint32_t      RESERVED46[2];
+  __IO uint32_t MTLFPECSR;           /*!< FPE Frame Preemption Control Status Register,                 Address offset: 0x0C90 */
+  __IO uint32_t MTLFPEAR;            /*!< FPE Frame Preemption Advance Register,                        Address offset: 0x0C94 */
+  uint32_t      RESERVED47[26];
+  struct {
+  __IO uint32_t MTLTXQOMR;           /*!< Tx queue x operating mode Register,                           Address offset: 0x0D00 */
+  __IO uint32_t MTLTXQUR;            /*!< Tx queue x underflow register,                                Address offset: 0x0D04 */
+  __IO uint32_t MTLTXQDR;            /*!< Tx queue x debug register,                                    Address offset: 0x0D08 */
+  uint32_t      RESERVED48[1];
+  __IO uint32_t MTLTXQ1ECR;           /*!< Tx queue 1 ETS control Register,                              Address offset: 0x0D50 */
+  __IO uint32_t MTLTXQESR;           /*!< Tx queue x ETS status Register,                               Address offset: 0x0D14 */
+  __IO uint32_t MTLTXQQWR;           /*!< Tx queue x quantum weight register,                           Address offset: 0x0D18 */
+  __IO uint32_t MTLTXQ1SSCR;          /*!< Tx queue 1 send slope credit Register,                        Address offset: 0x0D5C */
+  __IO uint32_t MTLTXQ1HCR;           /*!< Tx Queue 1 hiCredit register,                                 Address offset: 0x0D60 */
+  __IO uint32_t MTLTXQ1LCR;           /*!< Tx queue 1 loCredit register,                                 Address offset: 0x0D64 */
+  uint32_t      RESERVED49[1];
+  __IO uint32_t MTLQICSR;           /*!< Queue 0 interrupt control status Register,                    Address offset: 0x0D2C */
+  __IO uint32_t MTLRXQOMR;          /*!< Rx queue x operating mode register,                           Address offset: 0x0D30 */
+  __IO uint32_t MTLRXQMPOCR;        /*!< Rx queue x missed packet and overflow counter register,       Address offset: 0x0D34 */
+  __IO uint32_t MTLRXQDR;           /*!< Rx queue x debug register,                                    Address offset: 0x0D38 */
+  __IO uint32_t MTLRXQCR;           /*!< Rx queue x control register,                                  Address offset: 0x0D3C */
+  } MTL_QUEUE[2];
+  uint32_t      RESERVED52[160];
+  __IO uint32_t DMAMR;               /*!< DMA mode register,                                            Address offset: 0x1000 */
+  __IO uint32_t DMASBMR;             /*!< System bus mode register,                                     Address offset: 0x1004 */
+  __IO uint32_t DMAISR;              /*!< Interrupt status register,                                    Address offset: 0x1008 */
+  __IO uint32_t DMADSR;              /*!< Debug status register,                                        Address offset: 0x100C */
+  uint32_t      RESERVED53[4];
+  __IO uint32_t DMAA4TXACR;          /*!< AXI4 transmit channel ACE control register,                   Address offset: 0x1020 */
+  __IO uint32_t DMAA4RXACR;          /*!< AXI4 receive channel ACE control register,                    Address offset: 0x1024 */
+  __IO uint32_t DMAA4DACR;           /*!< AXI4 descriptor ACE control register,                         Address offset: 0x1028 */
+  uint32_t      RESERVED54[5];
+  __IO uint32_t DMALPIEI;            /*!< AXI4 LPI Entry Interval register,                             Address offset: 0x1040 */
+  uint32_t      RESERVED55[3];
+  __IO uint32_t DMATBSCTRL0R;        /*!< DMA TBS control register 0,                                   Address offset: 0x1050 */
+  uint32_t      RESERVED56[37];
+  struct {
+  uint32_t      RESERVED57[6];
+  __IO uint32_t DMACCR;             /*!< Channel x control register,                                   Address offset: 0x1100 */
+  __IO uint32_t DMACTXCR;           /*!< Channel x transmit control register,                          Address offset: 0x1104 */
+  __IO uint32_t DMACRXCR;           /*!< Channel x receive control register,                           Address offset: 0x1108 */
+  uint32_t      RESERVED58[2];
+  __IO uint32_t DMACTXDLAR;         /*!< Channel x Tx descriptor list address register,                Address offset: 0x1114 */
+  uint32_t      RESERVED59;
+  __IO uint32_t DMACRXDLAR;         /*!< Channel x Rx descriptor list address register,                Address offset: 0x111C */
+  __IO uint32_t DMACTXDTPR;         /*!< Channel x Tx descriptor tail pointer register,                Address offset: 0x1120 */
+  uint32_t      RESERVED60;
+  __IO uint32_t DMACRXDTPR;         /*!< Channel x Rx descriptor tail pointer register,                Address offset: 0x1128 */
+  __IO uint32_t DMACTXRLR;          /*!< Channel x Tx descriptor ring length register,                 Address offset: 0x112C */
+  __IO uint32_t DMACRXRLR;          /*!< Channel x Rx descriptor ring length register,                 Address offset: 0x1130 */
+  __IO uint32_t DMACIER;            /*!< Channel x interrupt enable register,                          Address offset: 0x1134 */
+  __IO uint32_t DMACRXIWTR;         /*!< Channel x Rx interrupt watchdog timer register,               Address offset: 0x1138 */
+  __IO uint32_t DMACSFCSR;          /*!< Channel x slot function control status register,              Address offset: 0x113C */
+  uint32_t      RESERVED61;
+  __IO uint32_t DMACCATXDR;         /*!< Channel x current application transmit descriptor register,   Address offset: 0x1144 */
+  uint32_t      RESERVED62;
+  __IO uint32_t DMACCARXDR;         /*!< Channel x current application receive descriptor register,    Address offset: 0x114C */
+  uint32_t      RESERVED63;
+  __IO uint32_t DMACCATXBR;         /*!< Channel x current application transmit buffer register,       Address offset: 0x1154 */
+  uint32_t      RESERVED64;
+  __IO uint32_t DMACCARXBR;         /*!< Channel x current application receive buffer register,        Address offset: 0x115C */
+  __IO uint32_t DMACSR;             /*!< Channel x status register,                                    Address offset: 0x1160 */
+  __IO uint32_t DMACMFCR;            /*!< Channel x missed frame count register,                        Address offset: 0x1164 */
+  } DMA_CH[2];
+}ETH_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+typedef struct
+{
+  __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
+  __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
+  __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
+  __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
+  __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
+  __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
+  __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
+       uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x1C */
+  __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
+  __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
+  __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
+  __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
+  __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
+  __IO uint32_t SECCFGR2;       /*!< EXTI Security Configuration Register 2,          Address offset:   0x34 */
+  __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
+       uint32_t RESERVED2;      /*!< Reserved 2,                                      Address offset:   0x3C */
+  __IO uint32_t RTSR3;          /*!< EXTI Rising Trigger Selection Register 3,        Address offset:   0x40 */
+  __IO uint32_t FTSR3;          /*!< EXTI Falling Trigger Selection Register 3,       Address offset:   0x44 */
+  __IO uint32_t SWIER3;         /*!< EXTI Software Interrupt event Register 3,        Address offset:   0x48 */
+  __IO uint32_t RPR3;           /*!< EXTI Rising Pending Register 3,                  Address offset:   0x4C */
+  __IO uint32_t FPR3;           /*!< EXTI Falling Pending Register 3,                 Address offset:   0x50 */
+  __IO uint32_t SECCFGR3;       /*!< EXTI Security Configuration Register 3,          Address offset:   0x54 */
+  __IO uint32_t PRIVCFGR3;      /*!< EXTI Privilege Configuration Register 3,         Address offset:   0x58 */
+       uint32_t RESERVED3;      /*!< Reserved 3,                                      Address offset:   0x5C */
+  __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
+  __IO uint32_t LOCKR;          /*!< EXTI Lock Register,                              Address offset:   0x70 */
+       uint32_t RESERVED4[3];   /*!< Reserved 4,                                                0x74 -- 0x7C */
+  __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
+  __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
+       uint32_t RESERVED5[2];   /*!< Reserved 5,                                                0x88 -- 0x8C */
+  __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
+  __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
+       uint32_t RESERVED6[2];   /*!< Reserved 6,                                                0x98 -- 0x9C */
+  __IO uint32_t IMR3;           /*!< EXTI Interrupt Mask Register 3,                  Address offset:   0xA0 */
+  __IO uint32_t EMR3;           /*!< EXTI Event Mask Register 3,                      Address offset:   0xA4 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t CREL;           /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+ __IO uint32_t ENDN;           /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+ __IO uint32_t RESERVED1;      /*!< Reserved,                                                                        0x008 */
+ __IO uint32_t DBTP;           /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+ __IO uint32_t TEST;           /*!< FDCAN Test register,                                             Address offset: 0x010 */
+ __IO uint32_t RWD;            /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+ __IO uint32_t CCCR;           /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+ __IO uint32_t NBTP;           /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+ __IO uint32_t TSCC;           /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+ __IO uint32_t TSCV;           /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+ __IO uint32_t TOCC;           /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+ __IO uint32_t TOCV;           /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+ __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                                0x030 - 0x03C */
+ __IO uint32_t ECR;            /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+ __IO uint32_t PSR;            /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+ __IO uint32_t TDCR;           /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+ __IO uint32_t RESERVED3;      /*!< Reserved,                                                                        0x04C */
+ __IO uint32_t IR;             /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+ __IO uint32_t IE;             /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+ __IO uint32_t ILS;            /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+ __IO uint32_t ILE;            /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+ __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                                0x060 - 0x07C */
+ __IO uint32_t GFC;            /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+ __IO uint32_t SIDFC;          /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+ __IO uint32_t XIDFC;          /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+ __IO uint32_t RESERVED5;      /*!< Reserved,                                                                        0x08C */
+ __IO uint32_t XIDAM;          /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+ __IO uint32_t HPMS;           /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+ __IO uint32_t NDAT1;          /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+ __IO uint32_t NDAT2;          /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+ __IO uint32_t RXF0C;          /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+ __IO uint32_t RXF0S;          /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+ __IO uint32_t RXF0A;          /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+ __IO uint32_t RXBC;           /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+ __IO uint32_t RXF1C;          /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+ __IO uint32_t RXF1S;          /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+ __IO uint32_t RXF1A;          /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+ __IO uint32_t RXESC;          /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+ __IO uint32_t TXBC;           /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+ __IO uint32_t TXFQS;          /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+ __IO uint32_t TXESC;          /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+ __IO uint32_t TXBRP;          /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+ __IO uint32_t TXBAR;          /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+ __IO uint32_t TXBCR;          /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+ __IO uint32_t TXBTO;          /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+ __IO uint32_t TXBCF;          /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+ __IO uint32_t TXBTIE;         /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+ __IO uint32_t TXBCIE;         /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+ __IO uint32_t RESERVED6[2];   /*!< Reserved,                                                                0x0E8 - 0x0EC */
+ __IO uint32_t TXEFC;          /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+ __IO uint32_t TXEFS;          /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+ __IO uint32_t TXEFA;          /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+ __IO uint32_t RESERVED7;      /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;         /*!< TT Trigger Memory Configuration register,        Address offset: 0x100 */
+  __IO uint32_t TTRMC;         /*!< TT Reference Message Configuration register,     Address offset: 0x104 */
+  __IO uint32_t TTOCF;         /*!< TT Operation Configuration register,             Address offset: 0x108 */
+  __IO uint32_t TTMLM;         /*!< TT Matrix Limits register,                       Address offset: 0x10C */
+  __IO uint32_t TURCF;         /*!< TUR Configuration register,                      Address offset: 0x110 */
+  __IO uint32_t TTOCN;         /*!< TT Operation Control register,                   Address offset: 0x114 */
+  __IO uint32_t TTGTP;         /*!< TT Global Time Preset register,                  Address offset: 0x118 */
+  __IO uint32_t TTTMK;         /*!< TT Time Mark register,                          Address offset: 0x11C */
+  __IO uint32_t TTIR;          /*!< TT Interrupt register,                           Address offset: 0x120 */
+  __IO uint32_t TTIE;          /*!< TT Interrupt Enable register,                    Address offset: 0x124 */
+  __IO uint32_t TTILS;         /*!< TT Interrupt Line Select register,               Address offset: 0x128 */
+  __IO uint32_t TTOST;         /*!< TT Operation Status register,                    Address offset: 0x12C */
+  __IO uint32_t TURNA;         /*!< TT TUR Numerator Actual register,                Address offset: 0x130 */
+  __IO uint32_t TTLGT;         /*!< TT Local and Global Time register,               Address offset: 0x134 */
+  __IO uint32_t TTCTC;         /*!< TT Cycle Time and Count register,                Address offset: 0x138 */
+  __IO uint32_t TTCPT;         /*!< TT Capture Time register,                        Address offset: 0x13C */
+  __IO uint32_t TTCSM;         /*!< TT Cycle Sync Mark register,                     Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111];/*!< Reserved,                                                0x144 - 0x2FC */
+  __IO uint32_t TTTS;          /*!< TT Trigger Select register,                      Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;          /*!< Clock Calibration Unit Core Release register,    Address offset: 0x00 */
+  __IO uint32_t CCFG;          /*!< Calibration Configuration register,              Address offset: 0x04 */
+  __IO uint32_t CSTAT;         /*!< Calibration Status register,                     Address offset: 0x08 */
+  __IO uint32_t CWD;           /*!< Calibration Watchdog register,                   Address offset: 0x0C */
+  __IO uint32_t IR;            /*!< CCU Interrupt register,                          Address offset: 0x10 */
+  __IO uint32_t IE;            /*!< CCU Interrupt Enable register,                   Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+/**
+ * @brief FD Controller Area Network Configuration
+ */
+typedef struct
+{
+ __IO uint32_t CKDIV;          /*!< FDCAN clock divider register,            Address offset: 0x100 + 0x000 */
+      uint32_t RESERVED1[128]; /*!< Reserved,                                0x100 + 0x004 - 0x100 + 0x200 */
+ __IO uint32_t OPTR;           /*!< FDCAN option register,                   Address offset: 0x100 + 0x204 */
+      uint32_t RESERVED2[58];  /*!< Reserved,                                0x100 + 0x208 - 0x100 + 0x2EC */
+ __IO uint32_t HWCFG;          /*!< FDCAN hardware configuration register,   Address offset: 0x100 + 0x2F0 */
+ __IO uint32_t VERR;           /*!< FDCAN IP version register,               Address offset: 0x100 + 0x2F4 */
+ __IO uint32_t IPIDR;          /*!< FDCAN IP ID register,                    Address offset: 0x100 + 0x2F8 */
+ __IO uint32_t SIDR;           /*!< FDCAN size ID register,                  Address offset: 0x100 + 0x2FC */
+} FDCAN_Config_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1
+  */
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+typedef struct
+{
+  __IO uint32_t SDCR[2];         /*!< SDRAM device 1/2 control register                      Address offset: 0x140-0x144 */
+  __IO uint32_t SDTR;            /*!< SDRAM timing register                                  Address offset: 0x148 */
+       uint32_t RESERVED0;       /*!< Reserved                                               Address offset: 0x14C */
+  __IO uint32_t SDCMR;           /*!< SDRAM command mode register                            Address offset: 0x150 */
+  __IO uint32_t SDRTR;           /*!< SDRAM refresh timer register                           Address offset: 0x154 */
+  __IO uint32_t SDSR;            /*!< SDRAM status register                                  Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+typedef struct
+{
+  __IO uint32_t PCR;             /*!< NAND Flash Programmable control register               Address offset: 0x080 */
+  __IO uint32_t SR;              /*!< FMC status register                                    Address offset: 0x084 */
+  __IO uint32_t PMEM;            /*!< Common memory space timing register                    Address offset: 0x088 */
+  __IO uint32_t PATT;            /*!< Attribute memory space timing registers                Address offset: 0x08C */
+  __IO uint32_t HPR;             /*!< FMC Hamming parity result registers                    Address offset: 0x090 */
+  __IO uint32_t HECCR;           /*!< FMC Hamming code ECC result register                   Address offset: 0x094 */
+       uint32_t RESERVED0[58];   /*!< Reserved                                               Address offset: 0x098-0x17C */
+  __IO uint32_t IER;             /*!< FMC NAND Interrupt Enable Register                     Address offset: 0x180 */
+  __IO uint32_t ISR;             /*!< FMC Controller Interrupt Status Register               Address offset: 0x184 */
+  __IO uint32_t ICR;             /*!< FMC NAND Controller Interrupt Clear Register           Address offset: 0x188 */
+       uint32_t RESERVED1[29];   /*!< Reserved                                               Address offset: 0x18C-0x1FC */
+  __IO uint32_t CSQCR;           /*!< FMC NAND Command Sequencer Control Register            Address offset: 0x200 */
+  __IO uint32_t CSQCFGR1;        /*!< FMC NAND Command Sequencer Configuration Register 1    Address offset: 0x204 */
+  __IO uint32_t CSQCFGR2;        /*!< FMC NAND Command Sequencer Configuration Register 2    Address offset: 0x208 */
+  __IO uint32_t CSQCFGR3;        /*!< FMC NAND sequencer configuration register 3            Address offset: 0x20C */
+  __IO uint32_t CSQAR1;          /*!< FMC NAND Command Sequencer Address Register 1          Address offset: 0x210 */
+  __IO uint32_t CSQAR2;          /*!< FMC NAND Command Sequencer Address Register 2          Address offset: 0x214 */
+       uint32_t RESERVED2[2];    /*!< Reserved                                               Address offset: 0x218-0x21C */
+  __IO uint32_t CSQIER;          /*!< FMC NAND Command Sequencer Interrupt Enable Register   Address offset: 0x220 */
+  __IO uint32_t CSQISR;          /*!< FMC NAND Command Sequencer Interrupt Status Register   Address offset: 0x224 */
+  __IO uint32_t CSQICR;          /*!< FMC NAND Command Sequencer Interrupt Clear Register    Address offset: 0x228 */
+       uint32_t RESERVED3;       /*!< Reserved                                               Address offset: 0x22C */
+  __IO uint32_t CSQEMSR;         /*!< FMC Command Sequencer Error Mapping Status register    Address offset: 0x230 */
+       uint32_t RESERVED4[7];    /*!< Reserved                                               Address offset: 0x234-0x24C */
+  __IO uint32_t BCHIER;          /*!< FMC BCH Interrupt enable register                      Address offset: 0x250 */
+  __IO uint32_t BCHISR;          /*!< FMC BCH Interrupt and Status Register                  Address offset: 0x254 */
+  __IO uint32_t BCHICR;          /*!< FMC BCH Interrupt Clear Register                       Address offset: 0x258 */
+       uint32_t RESERVED5;       /*!< Reserved                                               Address offset: 0x25C */
+  __IO uint32_t BCHPBR1;         /*!< FMC BCH Parity Bits Register 1                         Address offset: 0x260 */
+  __IO uint32_t BCHPBR2;         /*!< FMC BCH Parity Bits Register 2                         Address offset: 0x264 */
+  __IO uint32_t BCHPBR3;         /*!< FMC BCH Parity Bits Register 3                         Address offset: 0x268 */
+  __IO uint32_t BCHPBR4;         /*!< FMC BCH Parity Bits Register 4                         Address offset: 0x26C */
+       uint32_t RESERVED6[3];    /*!< Reserved                                               Address offset: 0x270-0x278 */
+  __IO uint32_t BCHDSR0;         /*!< FMC BCH Decoder Status register 0                      Address offset: 0x27C */
+  __IO uint32_t BCHDSR1;         /*!< FMC BCH Decoder Status register for bank 1             Address offset: 0x280 */
+  __IO uint32_t BCHDSR2;         /*!< FMC BCH Decoder Status register for bank 2             Address offset: 0x284 */
+  __IO uint32_t BCHDSR3;         /*!< FMC BCH Decoder Status register for bank 3             Address offset: 0x288 */
+  __IO uint32_t BCHDSR4;         /*!< FMC BCH Decoder Status register for bank 4             Address offset: 0x28C */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Common
+  */
+typedef struct{
+  __IO uint32_t CFGR;            /*!< FMC common configuration register                      Address offset: 0x020 */
+} FMC_Common_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+typedef struct
+{
+  __IO uint32_t MODER;         /*!< GPIO port mode register,                     Address offset: 0x00      */
+  __IO uint32_t OTYPER;        /*!< GPIO port output type register,              Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;       /*!< GPIO port output speed register,             Address offset: 0x08      */
+  __IO uint32_t PUPDR;         /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
+  __IO uint32_t IDR;           /*!< GPIO port input data register,               Address offset: 0x10      */
+  __IO uint32_t ODR;           /*!< GPIO port output data register,              Address offset: 0x14      */
+  __IO uint32_t BSRR;          /*!< GPIO port bit set/reset  register,           Address offset: 0x18      */
+  __IO uint32_t LCKR;          /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
+  __IO uint32_t AFR[2];        /*!< GPIO alternate function registers,           Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;           /*!< GPIO bit reset register,                     Address offset: 0x28      */
+       uint32_t RESERVED0;     /*!< Reserved,                                    Address offset: 0x2C      */
+  __IO uint32_t SECCFGR;       /*!< GPIO port secure configuration register,     Address offset: 0x30      */
+  __IO uint32_t PRIVCFGR;      /*!< GPIO port privileged configuration register, Address offset: 0x34      */
+  __IO uint32_t RCFGLOCKR;     /*!< GPIO port resource configuration register,   Address offset: 0x38      */
+       uint32_t RESERVED1;     /*!< Reserved,                                    Address offset: 0x3C      */
+  __IO uint32_t DELAYR[2];     /*!< GPIO port delay register,                    Address offset: 0x40-0x44 */
+  __IO uint32_t ADVCFGR[2];    /*!< GPIO port advanced configuration register,   Address offset: 0x48-0x4C */
+} GPIO_TypeDef;
+
+/**
+  * @brief GFXMMU
+  */
+typedef struct
+{
+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
+       uint32_t RESERVED0;       /*!< Reserved0,                                         Address offset: 0x0C */
+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
+  __IO uint32_t DAR;             /*!< GFXMMU default alpha register,                     Address offset: 0x14 */
+       uint32_t RESERVED1[2];    /*!< Reserved1,                                 Address offset: 0x18 to 0x1C */
+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                 Address offset: 0x30 to 0xFFC */
+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                      Address offset: 0x1000 to 0x2FFC
+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
+} GFXMMU_TypeDef;
+
+/**
+  * @brief GFXTIM
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< GFXTIM configuration register,                    Address offset: 0x00 */
+  __IO uint32_t CGCR;          /*!< GFXTIM clock generator configuration register,    Address offset: 0x04 */
+  __IO uint32_t TCR;           /*!< GFXTIM timers configuration register,             Address offset: 0x08 */
+  __IO uint32_t TDR;           /*!< GFXTIM timers disable register,                   Address offset: 0x0C */
+  __IO uint32_t EVCR;          /*!< GFXTIM events control register,                   Address offset: 0x10 */
+  __IO uint32_t EVSR;          /*!< GFXTIM events selection register,                 Address offset: 0x14 */
+  uint32_t RESERVED1[2];       /*!< Reserved,                                         Address offset: 0x18-0x1C */
+  __IO uint32_t WDGTCR;        /*!< GFXTIM watchdog timer configuration register,     Address offset: 0x20 */
+  uint32_t RESERVED2[3];       /*!< Reserved,                                         Address offset: 0x24-0x2C */
+  __IO uint32_t ISR;           /*!< GFXTIM interrupt status register,                 Address offset: 0x30 */
+  __IO uint32_t ICR;           /*!< GFXTIM interrupt clear register,                  Address offset: 0x34 */
+  __IO uint32_t IER;           /*!< GFXTIM interrupt enable register,                 Address offset: 0x38 */
+  __IO uint32_t TSR;           /*!< GFXTIM timers status register,                    Address offset: 0x3C */
+  __IO uint32_t LCCRR;         /*!< GFXTIM line clock counter reload register,        Address offset: 0x40 */
+  __IO uint32_t FCCRR;         /*!< GFXTIM frame clock counter reload register,       Address offset: 0x44 */
+  uint32_t RESERVED3[2];       /*!< Reserved,                                         Address offset: 0x48-0x4C */
+  __IO uint32_t ATR;           /*!< GFXTIM absolute time register,                    Address offset: 0x50 */
+  __IO uint32_t AFCR;          /*!< GFXTIM absolute frame counter register,           Address offset: 0x54 */
+  __IO uint32_t ALCR;          /*!< GFXTIM absolute line counter register,            Address offset: 0x58 */
+  uint32_t RESERVED4[1];       /*!< Reserved,                                         Address offset: 0x5C */
+  __IO uint32_t AFCC1R;        /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
+  uint32_t RESERVED5[3];       /*!< Reserved,                                         Address offset: 0x64-0X6C */
+  __IO uint32_t ALCC1R;        /*!< GFXTIM absolute line counter compare 1 register,  Address offset: 0x70 */
+  __IO uint32_t ALCC2R;        /*!< GFXTIM absolute line counter compare 2 register,  Address offset: 0x74 */
+  uint32_t RESERVED6[2];       /*!< Reserved,                                         Address offset: 0x78-0X7C */
+  __IO uint32_t RFC1R;         /*!< GFXTIM relative frame counter 1 register,         Address offset: 0x80 */
+  __IO uint32_t RFC1RR;        /*!< GFXTIM relative frame counter 1 reload register,  Address offset: 0x84 */
+  __IO uint32_t RFC2R;         /*!< GFXTIM relative frame counter 2 register,         Address offset: 0x88 */
+  __IO uint32_t RFC2RR;        /*!< GFXTIM relative frame counter 2 reload register,  Address offset: 0x8C */
+  uint32_t RESERVED7[4];       /*!< Reserved,                                         Address offset: 0x90-0X9C */
+  __IO uint32_t WDGCR;         /*!< GFXTIM watchdog counter register,                 Address offset: 0xA0 */
+  __IO uint32_t WDGRR;         /*!< GFXTIM watchdog reload register,                  Address offset: 0xA4 */
+  __IO uint32_t WDGPAR;        /*!< GFXTIM watchdog pre-alarm register,               Address offset: 0xA8 */
+  uint32_t RESERVED8[209];     /*!< Reserved,                                         Address offset: 0xAC-0X3EC */
+  __IO uint32_t HWCFGR;        /*!< GFXTIM HW configuration register,                 Address offset: 0x3F0 */
+  __IO uint32_t VERR;          /*!< GFXTIM version register,                          Address offset: 0x3F4 */
+  __IO uint32_t IPIDR;         /*!< GFXTIM identification register,                   Address offset: 0x3F8 */
+  __IO uint32_t SIDR;          /*!< GFXTIM size identification register,              Address offset: 0x3FC */
+} GFXTIM_TypeDef;
+
+/**
+  * @brief HASH
+  */
+typedef struct
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[103];         /*!< HASH context swap registers,    Address offset: 0x0F8-0x290 */
+} HASH_TypeDef;
+
+/**
+  * @brief HASH_DIGEST
+  */
+typedef struct
+{
+  __IO uint32_t HR[16];           /*!< HASH digest registers,          Address offset: 0x310-0x34C */
+} HASH_DIGEST_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Improved Inter-integrated Circuit Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
+  uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
+  __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
+  __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
+  __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
+  __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
+  __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
+  __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
+  __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
+  __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
+  uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
+  __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
+  uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
+  __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
+  __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
+  __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
+  uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
+  __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
+  __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
+  uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
+  __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
+  __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
+  uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
+  __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
+  __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
+  __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
+  uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
+  __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
+  __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
+  __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
+  __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
+  __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
+  __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
+} I3C_TypeDef;
+
+/**
+  * @brief Illegal Access Controller
+  */
+typedef struct
+{
+  __IO uint32_t IER[5];         /*!< Interrupt Enable register,                 Address offset: 0x000       */
+  uint32_t      RESERVED1[27];  /*!< Reserved,                                  Address offset: 0x014-0x07C */
+  __IO uint32_t ISR[5];         /*!< Interrupt Status register,                 Address offset: 0x080       */
+  uint32_t      RESERVED2[27];  /*!< Reserved,                                  Address offset: 0x094-0x0FC */
+  __IO uint32_t ICR[5];         /*!< Interrupt Clear register,                  Address offset: 0x100       */
+} IAC_TypeDef;
+
+/**
+  * @brief Instruction Cache
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
+  __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
+  __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
+  __IO uint32_t FCR;            /*!< ICACHE flag clear register,             Address offset: 0x0C */
+  __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
+  __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
+} ICACHE_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t KR;              /*!< IWDG key register                    Address offset: 0x000 */
+  __IO uint32_t PR;              /*!< IWDG prescaler register              Address offset: 0x004 */
+  __IO uint32_t RLR;             /*!< IWDG reload register                 Address offset: 0x008 */
+  __IO uint32_t SR;              /*!< IWDG status register                 Address offset: 0x00C */
+  __IO uint32_t WINR;            /*!< IWDG window register                 Address offset: 0x010 */
+  __IO uint32_t EWCR;            /*!< IWDG early wakeup interrupt register Address offset: 0x014 */
+  __IO uint32_t ICR;             /*!< IWDG interrupt clear register        Address offset: 0x018 */
+} IWDG_TypeDef;
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+
+/**
+  * @brief LCD-TFT Display Controller (LTDC)
+  */
+typedef struct
+{
+       uint32_t RESERVED0[2];   /*!< Reserved Address offset: 0x00-0x04 */
+  __IO uint32_t SSCR;           /*!< LTDC synchronization size configuration register Address offset: 0x8 */
+  __IO uint32_t BPCR;           /*!< LTDC back porch configuration register Address offset: 0xc */
+  __IO uint32_t AWCR;           /*!< LTDC active width configuration register Address offset: 0x10 */
+  __IO uint32_t TWCR;           /*!< LTDC total width configuration register Address offset: 0x14 */
+  __IO uint32_t GCR;            /*!< LTDC global control register Address offset: 0x18 */
+       uint32_t RESERVED1[2];   /*!< Reserved Address offset: */
+  __IO uint32_t SRCR;           /*!< LTDC shadow reload configuration register Address offset: 0x24 */
+  __IO uint32_t GCCR;           /*!< LTDC gamma correction configuration register Address offset: 0x28 */
+  __IO uint32_t BCCR;           /*!< LTDC background color configuration register Address offset: 0x2c */
+       uint32_t RESERVED2;      /*!< Reserved Address offset: 0x30 */
+  __IO uint32_t IER;            /*!< LTDC interrupt enable register Address offset: 0x34 */
+  __IO uint32_t ISR;            /*!< LTDC interrupt status register Address offset: 0x38 */
+  __IO uint32_t ICR;            /*!< LTDC Interrupt Clear Register Address offset: 0x3c */
+  __IO uint32_t LIPCR;          /*!< LTDC line interrupt position configuration register Address offset: 0x40 */
+  __IO uint32_t CPSR;           /*!< LTDC current position status register Address offset: 0x44 */
+  __IO uint32_t CDSR;           /*!< LTDC current display status register Address offset: 0x48 */
+       uint32_t RESERVED3[5];   /*!< Reserved Address offset: 0x4c */
+  __IO uint32_t EDCR;           /*!< LTDC external display control register Address offset: 0x60 */
+  __IO uint32_t IER2;           /*!< LTDC interrupt enable register 2 Address offset: 0x64 */
+  __IO uint32_t ISR2;           /*!< LTDC interrupt status register 2 Address offset: 0x68 */
+  __IO uint32_t ICR2;           /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */
+  __IO uint32_t LIPCR2;         /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */
+       uint32_t RESERVED4;      /*!< Reserved Address offset: 0x74 */
+  __IO uint32_t ECRCR;          /*!< LTDC expected CRC register Address offset: 0x78 */
+  __IO uint32_t CCRCR;          /*!< LTDC computed CRC register Address offset: 0x7c */
+  __IO uint32_t RB0AR;          /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */
+  __IO uint32_t RB1AR;          /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */
+  __IO uint32_t RBPR;           /*!< LTDC rotation buffer pitch register Address offset: 0x88 */
+  __IO uint32_t RIFCR;          /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */
+  __IO uint32_t FUTR;           /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller (LTDC)
+  */
+typedef struct
+{
+  __IO uint32_t C0R;          /*!< LTDC layer x configuration 0 register Address offset: 0x100 */
+  __IO uint32_t C1R;          /*!< LTDC layer x configuration 1 register Address offset: 0x104 */
+  __IO uint32_t RCR;          /*!< LTDC layer x reload control register Address offset: 0x108 */
+  __IO uint32_t CR;           /*!< LTDC layer x control register Address offset: 0x10c */
+  __IO uint32_t WHPCR;        /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */
+  __IO uint32_t WVPCR;        /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */
+  __IO uint32_t CKCR;         /*!< LTDC layer x color keying configuration register Address offset: 0x118 */
+  __IO uint32_t PFCR;         /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */
+  __IO uint32_t CACR;         /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */
+  __IO uint32_t DCCR;         /*!< LTDC layer x default color configuration register Address offset: 0x124 */
+  __IO uint32_t BFCR;         /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */
+  __IO uint32_t BLCR;         /*!< LTDC layer x burst length configuration register Address offset: 0x12c */
+  __IO uint32_t PCR;          /*!< LTDC layer x planar configuration register Address offset: 0x130 */
+  __IO uint32_t CFBAR;        /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */
+  __IO uint32_t CFBLR;        /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */
+  __IO uint32_t CFBLNR;       /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */
+  __IO uint32_t AFBA0R;       /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */
+  __IO uint32_t AFBA1R;       /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */
+  __IO uint32_t AFBLR;        /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */
+  __IO uint32_t AFBLNR;       /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */
+  __IO uint32_t CLUTWR;       /*!< LTDC layer x CLUT write register Address offset: 0x150 */
+  __IO uint32_t SISR;         /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */
+  __IO uint32_t SOSR;         /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */
+  __IO uint32_t SVSFR;        /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */
+  __IO uint32_t SVSPR;        /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */
+  __IO uint32_t SHSFR;        /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */
+  __IO uint32_t SHSPR;        /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */
+  __IO uint32_t CYR0R;        /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */
+  __IO uint32_t CYR1R;        /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */
+  __IO uint32_t FPF0R;        /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */
+  __IO uint32_t FPF1R;        /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */
+} LTDC_Layer_TypeDef;
+
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
+  __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
+  __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
+  __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
+  __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
+  __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
+  __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
+  __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
+  __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x20 */
+  __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
+  __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
+  __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
+  __IO uint32_t RESERVED2;      /*!< Reserved,                               Address offset: 0x30 */
+  __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Memory Cipher Engine (MCE)
+  */
+typedef struct
+{
+  __IO uint32_t REGCR;            /*!< MCE region configuration register,             Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */
+  __IO uint32_t SADDR;            /*!< MCE region start address register,             Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */
+  __IO uint32_t EADDR;            /*!< MCE region end address register,               Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */
+} MCE_Region_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCCFGR;           /*!< MCE cipher context configuration register,     Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCNR0;            /*!< MCE cipher context nonce register 0,           Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCNR1;            /*!< MCE cipher context nonce register 1,           Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR0;          /*!< MCE cipher context key register 0,             Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR1;          /*!< MCE cipher context key register 1,             Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR2;          /*!< MCE cipher context key register 2,             Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */
+  __IO uint32_t CCKEYR3;          /*!< MCE cipher context key register 3,             Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */
+} MCE_Context_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< MCE configuration register,                           Address offset: 0x000       */
+  __IO uint32_t SR;               /*!< MCE status register,                                  Address offset: 0x004       */
+  __IO uint32_t IASR;             /*!< MCE illegal access status register,                   Address offset: 0x008       */
+  __IO uint32_t IACR;             /*!< MCE illegal access clear register,                    Address offset: 0x00C       */
+  __IO uint32_t IAIER;            /*!< MCE illegal access interrupt enable register,         Address offset: 0x010       */
+  uint32_t RESERVED0[4];          /*!< Reserved,                                             Address offset: 0x014-0x20  */
+  __IO uint32_t IADDR;            /*!< MCE illegal address register,                         Address offset: 0x024       */
+  uint32_t RESERVED1[118];        /*!< Reserved,                                             Address offset: 0x028-0x1FC */
+  __IO uint32_t MKEYR0;           /*!< MCE master key register 0,                            Address offset: 0x200       */
+  __IO uint32_t MKEYR1;           /*!< MCE master key register 1,                            Address offset: 0x204       */
+  __IO uint32_t MKEYR2;           /*!< MCE master key register 2,                            Address offset: 0x208       */
+  __IO uint32_t MKEYR3;           /*!< MCE master key register 3,                            Address offset: 0x20C       */
+  __IO uint32_t MKEYR4;           /*!< MCE master key register 4,                            Address offset: 0x210       */
+  __IO uint32_t MKEYR5;           /*!< MCE master key register 5,                            Address offset: 0x214       */
+  __IO uint32_t MKEYR6;           /*!< MCE master key register 6,                            Address offset: 0x218       */
+  __IO uint32_t MKEYR7;           /*!< MCE master key register 7,                            Address offset: 0x21C       */
+  __IO uint32_t FMKEYR0;          /*!< MCE fast master key register 0,                       Address offset: 0x220       */
+  __IO uint32_t FMKEYR1;          /*!< MCE fast master key register 1,                       Address offset: 0x224       */
+  __IO uint32_t FMKEYR2;          /*!< MCE fast master key register 2,                       Address offset: 0x228       */
+  __IO uint32_t FMKEYR3;          /*!< MCE fast master key register 3,                       Address offset: 0x22C       */
+  __IO uint32_t FMKEYR4;          /*!< MCE fast master key register 4,                       Address offset: 0x230       */
+  __IO uint32_t FMKEYR5;          /*!< MCE fast master key register 5,                       Address offset: 0x234       */
+  __IO uint32_t FMKEYR6;          /*!< MCE fast master key register 6,                       Address offset: 0x238       */
+  __IO uint32_t FMKEYR7;          /*!< MCE fast master key register 7,                       Address offset: 0x23C       */
+} MCE_TypeDef;
+
+
+
+/**
+  * @brief ADF
+  */
+typedef struct
+{
+  __IO uint32_t GCR;            /*!< MDF Global Control register,             Address offset: 0x00  */
+  __IO uint32_t CKGCR;          /*!< MDF Clock Generator Control Register,    Address offset: 0x04  */
+  uint32_t      RESERVED1[6];   /*!< Reserved, 0x08-0x1C                                            */
+  __IO uint32_t OR;             /*!< MDF  Option Register,                    Address offset: 0x20  */
+} MDF_TypeDef;
+
+/**
+  * @brief ADF filter
+  */
+typedef struct
+{
+ __IO uint32_t SITFCR;         /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
+ __IO uint32_t BSMXCR;         /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
+ __IO uint32_t DFLTCR;         /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
+ __IO uint32_t DFLTCICR;       /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
+ __IO uint32_t DFLTRSFR;       /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
+ __IO uint32_t DFLTINTR;       /*!< MDF Integrator Configuration Register,          Address offset: 0x94 */
+ __IO uint32_t OLDCR;          /*!< MDF Out-Of Limit Detector Control Register,     Address offset: 0x98 */
+ __IO uint32_t OLDTHLR;        /*!< MDF OLD Threshold Low Register,                 Address offset: 0x9C */
+ __IO uint32_t OLDTHHR;        /*!< MDF OLD Threshold High Register,                Address offset: 0xA0 */
+ __IO uint32_t DLYCR;          /*!< MDF Delay control Register,                     Address offset: 0xA4 */
+ __IO uint32_t SCDCR;          /*!< MDF short circuit detector control Register,    Address offset: 0xA8 */
+ __IO uint32_t DFLTIER;        /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
+ __IO uint32_t DFLTISR;        /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
+ __IO uint32_t OECCR;          /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
+ __IO uint32_t SADCR;          /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
+ __IO uint32_t SADCFGR;        /*!< MDF SAD configuration register,                 Address offset: 0xBC */
+ __IO uint32_t SADSDLVR;       /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
+ __IO uint32_t SADANLVR;       /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
+ uint32_t     RESERVED1[9];    /*!< Reserved, 0xC8-0xE8                                                  */
+ __IO uint32_t SNPSDR;         /*!< MDF Snapshot Data Register,                     Address offset: 0xEC */
+ __IO uint32_t DFLTDR;         /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
+} MDF_Filter_TypeDef;
+
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+/**
+  * @brief PSSI
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< PSSI control register,                 Address offset: 0x000 */
+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
+} PSSI_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+typedef struct
+{
+  __IO uint32_t CR1;             /*!< PWR Control register 1                           Address offset: 0x000 */
+  __IO uint32_t CR2;             /*!< PWR Control Register 2                           Address offset: 0x004 */
+  __IO uint32_t CR3;             /*!< PWR Control Register 3                           Address offset: 0x008 */
+  __IO uint32_t CR4;             /*!< PWR Control Register 4                           Address offset: 0x00C */
+       uint32_t RESERVED0[4];    /*!< Reserved                                         Address offset: 0x010-0x01C */
+  __IO uint32_t VOSCR;           /*!< PWR Voltage scaling control register             Address offset: 0x020 */
+  __IO uint32_t BDCR1;           /*!< PWR Backup domain control register 1             Address offset: 0x024 */
+  __IO uint32_t BDCR2;           /*!< PWR Backup domain control register 2             Address offset: 0x028 */
+  __IO uint32_t DBPCR;           /*!< PWR Disable backup protection control register   Address offset: 0x02C */
+  __IO uint32_t CPUCR;           /*!< PWR CPU control register                         Address offset: 0x030 */
+  __IO uint32_t SVMCR1;          /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */
+  __IO uint32_t SVMCR2;          /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */
+  __IO uint32_t SVMCR3;          /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */
+       uint32_t RESERVED1[4];    /*!< Reserved                                         Address offset: 0x040-0x04C */
+  __IO uint32_t WKUPCR;          /*!< PWR Wakeup control register 1                    Address offset: 0x050 */
+  __IO uint32_t WKUPSR;          /*!< PWR Wakeup control register 2                    Address offset: 0x054 */
+  __IO uint32_t WKUPEPR;         /*!< PWR Wakeup control register 3                    Address offset: 0x058 */
+       uint32_t RESERVED2[5];    /*!< Reserved                                         Address offset: 0x05C-0x06C */
+  __IO uint32_t SECCFGR;         /*!< PWR Security configuration register              Address offset: 0x070 */
+  __IO uint32_t PRIVCFGR;        /*!< PWR Privilege configuration register             Address offset: 0x074 */
+} PWR_TypeDef;
+
+/**
+  * @brief PKA
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< PKA control register,             Address offset: 0x00 */
+  __IO uint32_t SR;            /*!< PKA status register,              Address offset: 0x04 */
+  __IO uint32_t CLRFR;         /*!< PKA clear flag register,          Address offset: 0x08 */
+  uint32_t Reserved[253];      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
+  __IO uint32_t RAM[1334];     /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
+} PKA_TypeDef;
+
+/**
+  * @brief RAMs configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control Register,                    Address offset: 0x00 */
+  __IO uint32_t IER;         /*!< Interrupt Enable Register,           Address offset: 0x04 */
+  __IO uint32_t ISR;         /*!< Interrupt Status Register,           Address offset: 0x08 */
+  __IO uint32_t ESEAR;       /*!< ECC Single Error Address Register,   Address offset: 0x0C */
+  __IO uint32_t EDEAR;       /*!< ECC Double Error Address Register,   Address offset: 0x10 */
+  __IO uint32_t ICR;         /*!< Interrupt Clear Register,            Address offset: 0x14 */
+  uint32_t      RESERVED[3]; /*!< Reserved,                       Address offset: 0x18-0x20 */
+  __IO uint32_t ECCKEYR;     /*!< RAM ECC Key Register,                Address offset: 0x24 */
+  __IO uint32_t ERKEYR;      /*!< RAM Erase Key Register,              Address offset: 0x28 */
+}RAMCFG_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;               /*!< RCC control register                                           Address offset: 0x0000 */
+  __IO uint32_t SR;               /*!< RCC status register                                            Address offset: 0x0004 */
+  __IO uint32_t STOPCR;           /*!< RCC Stop mode control register                                 Address offset: 0x0008 */
+       uint32_t RESERVED0[5];     /*!< Reserved                                                       Address offset: 0x000C-0x001C */
+  __IO uint32_t CFGR1;            /*!< RCC configuration register 1                                   Address offset: 0x0020 */
+  __IO uint32_t CFGR2;            /*!< RCC configuration register 2                                   Address offset: 0x0024 */
+       uint32_t RESERVED1;        /*!< Reserved                                                       Address offset: 0x0028 */
+  __IO uint32_t BDCR;             /*!< RCC backup domain protection register                          Address offset: 0x002C */
+  __IO uint32_t HWRSR;            /*!< RCC reset status register for hardware                         Address offset: 0x0030 */
+  __IO uint32_t RSR;              /*!< RCC reset register                                             Address offset: 0x0034 */
+       uint32_t RESERVED2[2];     /*!< Reserved                                                       Address offset: 0x0038-0x003C */
+  __IO uint32_t LSECFGR;          /*!< RCC LSE configuration register                                 Address offset: 0x0040 */
+  __IO uint32_t MSICFGR;          /*!< RCC MSI configuration register                                 Address offset: 0x0044 */
+  __IO uint32_t HSICFGR;          /*!< RCC HSI configuration register                                 Address offset: 0x0048 */
+  __IO uint32_t HSIMCR;           /*!< RCC HSI Monitor control register                               Address offset: 0x004C */
+  __IO uint32_t HSIMSR;           /*!< RCC HSI Monitor status register                                Address offset: 0x0050 */
+  __IO uint32_t HSECFGR;          /*!< RCC HSE configuration register                                 Address offset: 0x0054 */
+       uint32_t RESERVED3[10];    /*!< Reserved                                                       Address offset: 0x0058-0x007C */
+  __IO uint32_t PLL1CFGR1;        /*!< RCC PLL1 configuration register 1                              Address offset: 0x0080 */
+  __IO uint32_t PLL1CFGR2;        /*!< RCC PLL1 configuration register 2                              Address offset: 0x0084 */
+  __IO uint32_t PLL1CFGR3;        /*!< RCC PLL1 configuration register 3                              Address offset: 0x0088 */
+       uint32_t RESERVED4;        /*!< Reserved                                                       Address offset: 0x008C */
+  __IO uint32_t PLL2CFGR1;        /*!< RCC PLL2 configuration register 1                              Address offset: 0x0090 */
+  __IO uint32_t PLL2CFGR2;        /*!< RCC PLL2 configuration register 2                              Address offset: 0x0094 */
+  __IO uint32_t PLL2CFGR3;        /*!< RCC PLL2 configuration register 3                              Address offset: 0x0098 */
+       uint32_t RESERVED5;        /*!< Reserved                                                       Address offset: 0x009C */
+  __IO uint32_t PLL3CFGR1;        /*!< RCC PLL3 configuration register 1                              Address offset: 0x00A0 */
+  __IO uint32_t PLL3CFGR2;        /*!< RCC PLL3 configuration register 2                              Address offset: 0x00A4 */
+  __IO uint32_t PLL3CFGR3;        /*!< RCC PLL3 configuration register 3                              Address offset: 0x00A8 */
+       uint32_t RESERVED6;        /*!< Reserved                                                       Address offset: 0x00AC */
+  __IO uint32_t PLL4CFGR1;        /*!< RCC PLL4 configuration register 1                              Address offset: 0x00B0 */
+  __IO uint32_t PLL4CFGR2;        /*!< RCC PLL4 configuration register 2                              Address offset: 0x00B4 */
+  __IO uint32_t PLL4CFGR3;        /*!< RCC PLL4 configuration register 3                              Address offset: 0x00B8 */
+       uint32_t RESERVED7[2];     /*!< Reserved                                                       Address offset: 0x00BC-0x00C0 */
+  __IO uint32_t IC1CFGR;          /*!< RCC IC1 configuration register                                 Address offset: 0x00C4 */
+  __IO uint32_t IC2CFGR;          /*!< RCC IC2 configuration register                                 Address offset: 0x00C8 */
+  __IO uint32_t IC3CFGR;          /*!< RCC IC3 configuration register                                 Address offset: 0x00CC */
+  __IO uint32_t IC4CFGR;          /*!< RCC IC4 configuration register                                 Address offset: 0x00D0 */
+  __IO uint32_t IC5CFGR;          /*!< RCC IC5 configuration register                                 Address offset: 0x00D4 */
+  __IO uint32_t IC6CFGR;          /*!< RCC IC6 configuration register                                 Address offset: 0x00D8 */
+  __IO uint32_t IC7CFGR;          /*!< RCC IC7 configuration register                                 Address offset: 0x00DC */
+  __IO uint32_t IC8CFGR;          /*!< RCC IC8 configuration register                                 Address offset: 0x00E0 */
+  __IO uint32_t IC9CFGR;          /*!< RCC IC9 configuration register                                 Address offset: 0x00E4 */
+  __IO uint32_t IC10CFGR;         /*!< RCC IC10 configuration register                                Address offset: 0x00E8 */
+  __IO uint32_t IC11CFGR;         /*!< RCC IC11 configuration register                                Address offset: 0x00EC */
+  __IO uint32_t IC12CFGR;         /*!< RCC IC12 configuration register                                Address offset: 0x00F0 */
+  __IO uint32_t IC13CFGR;         /*!< RCC IC13 configuration register                                Address offset: 0x00F4 */
+  __IO uint32_t IC14CFGR;         /*!< RCC IC14 configuration register                                Address offset: 0x00F8 */
+  __IO uint32_t IC15CFGR;         /*!< RCC IC15 configuration register                                Address offset: 0x00FC */
+  __IO uint32_t IC16CFGR;         /*!< RCC IC16 configuration register                                Address offset: 0x0100 */
+  __IO uint32_t IC17CFGR;         /*!< RCC IC17 configuration register                                Address offset: 0x0104 */
+  __IO uint32_t IC18CFGR;         /*!< RCC IC18 configuration register                                Address offset: 0x0108 */
+  __IO uint32_t IC19CFGR;         /*!< RCC IC19 configuration register                                Address offset: 0x010C */
+  __IO uint32_t IC20CFGR;         /*!< RCC IC20 configuration register                                Address offset: 0x0110 */
+       uint32_t RESERVED8[4];     /*!< Reserved                                                       Address offset: 0x0114-0x0120 */
+  __IO uint32_t CIER;             /*!< RCC clock-source interrupt enable register                     Address offset: 0x0124 */
+  __IO uint32_t CIFR;             /*!< RCC clock-source interrupt flag register                       Address offset: 0x0128 */
+  __IO uint32_t CICR;             /*!< RCC clock-source interrupt clear register                      Address offset: 0x012C */
+       uint32_t RESERVED9[5];     /*!< Reserved                                                       Address offset: 0x0130-0x0140 */
+  __IO uint32_t CCIPR1;           /*!< RCC clock configuration for independent peripheral register 1  Address offset: 0x0144 */
+  __IO uint32_t CCIPR2;           /*!< RCC clock configuration for independent peripheral register 2  Address offset: 0x0148 */
+  __IO uint32_t CCIPR3;           /*!< RCC clock configuration for independent peripheral register 3  Address offset: 0x014C */
+  __IO uint32_t CCIPR4;           /*!< RCC clock configuration for independent peripheral register 4  Address offset: 0x0150 */
+  __IO uint32_t CCIPR5;           /*!< RCC clock configuration for independent peripheral register 5  Address offset: 0x0154 */
+  __IO uint32_t CCIPR6;           /*!< RCC clock configuration for independent peripheral register 6  Address offset: 0x0158 */
+  __IO uint32_t CCIPR7;           /*!< RCC clock configuration for independent peripheral register 7  Address offset: 0x015C */
+  __IO uint32_t CCIPR8;           /*!< RCC clock configuration for independent peripheral register 8  Address offset: 0x0160 */
+  __IO uint32_t CCIPR9;           /*!< RCC clock configuration for independent peripheral register 9  Address offset: 0x0164 */
+       uint32_t RESERVED10[2];    /*!< Reserved                                                       Address offset: 0x0168-0x016C */
+  __IO uint32_t CCIPR12;          /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */
+  __IO uint32_t CCIPR13;          /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */
+  __IO uint32_t CCIPR14;          /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */
+       uint32_t RESERVED11[35];   /*!< Reserved                                                       Address offset: 0x017C-0x0204 */
+  __IO uint32_t MISCRSTR;         /*!< RCC miscellaneous configurations reset register                Address offset: 0x0208 */
+  __IO uint32_t MEMRSTR;          /*!< RCC embedded memories reset register                           Address offset: 0x020C */
+  __IO uint32_t AHB1RSTR;         /*!< RCC AHB1 reset register                                        Address offset: 0x0210 */
+  __IO uint32_t AHB2RSTR;         /*!< RCC AHB2 reset register                                        Address offset: 0x0214 */
+  __IO uint32_t AHB3RSTR;         /*!< RCC AHB3 reset register                                        Address offset: 0x0218 */
+  __IO uint32_t AHB4RSTR;         /*!< RCC AHB4 reset register                                        Address offset: 0x021C */
+  __IO uint32_t AHB5RSTR;         /*!< RCC AHB5 reset register                                        Address offset: 0x0220 */
+  __IO uint32_t APB1RSTR1;        /*!< RCC APB1 reset register 1                                      Address offset: 0x0224 */
+  __IO uint32_t APB1RSTR2;        /*!< RCC APB1 reset register 2                                      Address offset: 0x0228 */
+  __IO uint32_t APB2RSTR;         /*!< RCC APB2 reset register                                        Address offset: 0x022C */
+       uint32_t RESERVED12;       /*!< Reserved                                                       Address offset: 0x0230 */
+  __IO uint32_t APB4RSTR1;        /*!< RCC APB4 reset register 1                                      Address offset: 0x0234 */
+  __IO uint32_t APB4RSTR2;        /*!< RCC APB4 reset register 2                                      Address offset: 0x0238 */
+  __IO uint32_t APB5RSTR;         /*!< RCC APB5 reset register                                        Address offset: 0x023C */
+  __IO uint32_t DIVENR;           /*!< RCC IC dividers enable register                                Address offset: 0x0240 */
+  __IO uint32_t BUSENR;           /*!< RCC embedded buses enable register                             Address offset: 0x0244 */
+  __IO uint32_t MISCENR;          /*!< RCC miscellaneous configurations enable register               Address offset: 0x0248 */
+  __IO uint32_t MEMENR;           /*!< RCC embedded memories enable register                          Address offset: 0x024C */
+  __IO uint32_t AHB1ENR;          /*!< RCC AHB1 enable register                                       Address offset: 0x0250 */
+  __IO uint32_t AHB2ENR;          /*!< RCC AHB2 enable register                                       Address offset: 0x0254 */
+  __IO uint32_t AHB3ENR;          /*!< RCC AHB3 enable register                                       Address offset: 0x0258 */
+  __IO uint32_t AHB4ENR;          /*!< RCC AHB4 enable register                                       Address offset: 0x025C */
+  __IO uint32_t AHB5ENR;          /*!< RCC AHB5 enable register                                       Address offset: 0x0260 */
+  __IO uint32_t APB1ENR1;         /*!< RCC APB1 enable register 1                                     Address offset: 0x0264 */
+  __IO uint32_t APB1ENR2;         /*!< RCC APB1 enable register 2                                     Address offset: 0x0268 */
+  __IO uint32_t APB2ENR;          /*!< RCC APB2 enable register                                       Address offset: 0x026C */
+  __IO uint32_t APB3ENR;          /*!< RCC APB3 enable register                                       Address offset: 0x0270 */
+  __IO uint32_t APB4ENR1;         /*!< RCC APB4 enable register 1                                     Address offset: 0x0274 */
+  __IO uint32_t APB4ENR2;         /*!< RCC APB4 enable register 2                                     Address offset: 0x0278 */
+  __IO uint32_t APB5ENR;          /*!< RCC APB5 enable register                                       Address offset: 0x027C */
+       uint32_t RESERVED13;       /*!< Reserved                                                       Address offset: 0x0280 */
+  __IO uint32_t BUSLPENR;         /*!< RCC embedded buses sleep enable register                       Address offset: 0x0284 */
+  __IO uint32_t MISCLPENR;        /*!< RCC miscellaneous configurations sleep enable register         Address offset: 0x0288 */
+  __IO uint32_t MEMLPENR;         /*!< RCC embedded memories sleep enable register                    Address offset: 0x028C */
+  __IO uint32_t AHB1LPENR;        /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0290 */
+  __IO uint32_t AHB2LPENR;        /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0294 */
+  __IO uint32_t AHB3LPENR;        /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0298 */
+  __IO uint32_t AHB4LPENR;        /*!< RCC AHB4 sleep enable register                                 Address offset: 0x029C */
+  __IO uint32_t AHB5LPENR;        /*!< RCC AHB5 sleep enable register                                 Address offset: 0x02A0 */
+  __IO uint32_t APB1LPENR1;       /*!< RCC APB1 sleep enable register 1                               Address offset: 0x02A4 */
+  __IO uint32_t APB1LPENR2;       /*!< RCC APB1 sleep enable register 2                               Address offset: 0x02A8 */
+  __IO uint32_t APB2LPENR;        /*!< RCC APB2 sleep enable register                                 Address offset: 0x02AC */
+  __IO uint32_t APB3LPENR;        /*!< RCC APB3 sleep enable register                                 Address offset: 0x02B0 */
+  __IO uint32_t APB4LPENR1;       /*!< RCC APB4 sleep enable register 1                               Address offset: 0x02B4 */
+  __IO uint32_t APB4LPENR2;       /*!< RCC APB4 sleep enable register 2                               Address offset: 0x02B8 */
+  __IO uint32_t APB5LPENR;        /*!< RCC APB5 sleep enable register                                 Address offset: 0x02BC */
+       uint32_t RESERVED14[99];   /*!< Reserved                                                       Address offset: 0x02C0-0x0448 */
+  __IO uint32_t RDCR;             /*!< RCC reset duration control register                            Address offset: 0x044C */
+       uint32_t RESERVED15[204];  /*!< Reserved                                                       Address offset: 0x0450-0x077C */
+  __IO uint32_t SECCFGR0;         /*!< RCC oscillator secure configuration register 0                 Address offset: 0x0780 */
+  __IO uint32_t PRIVCFGR0;        /*!< RCC oscillator privilege configuration register 0              Address offset: 0x0784 */
+  __IO uint32_t LOCKCFGR0;        /*!< RCC oscillator lock configuration register 0                   Address offset: 0x0788 */
+  __IO uint32_t PUBCFGR0;         /*!< RCC oscillator public configuration register 0                 Address offset: 0x078C */
+  __IO uint32_t SECCFGR1;         /*!< RCC PLL secure configuration register 1                        Address offset: 0x0790 */
+  __IO uint32_t PRIVCFGR1;        /*!< RCC PLL privilege configuration register 1                     Address offset: 0x0794 */
+  __IO uint32_t LOCKCFGR1;        /*!< RCC PLL lock configuration register 1                          Address offset: 0x0798 */
+  __IO uint32_t PUBCFGR1;         /*!< RCC PLL public configuration register 1                        Address offset: 0x079C */
+  __IO uint32_t SECCFGR2;         /*!< RCC divider secure configuration register 2                    Address offset: 0x07A0 */
+  __IO uint32_t PRIVCFGR2;        /*!< RCC divider privilege configuration register 2                 Address offset: 0x07A4 */
+  __IO uint32_t LOCKCFGR2;        /*!< RCC divider lock configuration register 2                      Address offset: 0x07A8 */
+  __IO uint32_t PUBCFGR2;         /*!< RCC divider public configuration register 2                    Address offset: 0x07AC */
+  __IO uint32_t SECCFGR3;         /*!< RCC system secure configuration register 3                     Address offset: 0x07B0 */
+  __IO uint32_t PRIVCFGR3;        /*!< RCC system privilege configuration register 3                  Address offset: 0x07B4 */
+  __IO uint32_t LOCKCFGR3;        /*!< RCC system lock configuration register 3                       Address offset: 0x07B8 */
+  __IO uint32_t PUBCFGR3;         /*!< RCC system public configuration register 3                     Address offset: 0x07BC */
+  __IO uint32_t SECCFGR4;         /*!< RCC bus secure configuration register 4                        Address offset: 0x07C0 */
+  __IO uint32_t PRIVCFGR4;        /*!< RCC bus privilege configuration register 4                     Address offset: 0x07C4 */
+  __IO uint32_t LOCKCFGR4;        /*!< RCC bus lock configuration register 4                          Address offset: 0x07C8 */
+  __IO uint32_t PUBCFGR4;         /*!< RCC bus public configuration register 4                        Address offset: 0x07CC */
+  __IO uint32_t PUBCFGR5;         /*!< RCC bus public configuration register 4                        Address offset: 0x07D0 */
+       uint32_t RESERVED16[11];   /*!< Reserved                                                       Address offset: 0x07D4-0x07FC */
+  __IO uint32_t CSR;              /*!< RCC control Set register                                       Address offset: 0x0800 */
+       uint32_t RESERVED17;       /*!< Reserved                                                       Address offset: 0x0804 */
+  __IO uint32_t STOPCSR;          /*!< RCC STOPCSR configuration register                             Address offset: 0x0808 */
+       uint32_t RESERVED18[127];  /*!< Reserved                                                       Address offset: 0x080C-0x0A00 */
+  __IO uint32_t MISCRSTSR;        /*!< RCC miscellaneous reset register                               Address offset: 0x0A08 */
+  __IO uint32_t MEMRSTSR;         /*!< RCC memory reset register                                      Address offset: 0x0A0C */
+  __IO uint32_t AHB1RSTSR;        /*!< RCC AHB1 reset register                                        Address offset: 0x0A10 */
+  __IO uint32_t AHB2RSTSR;        /*!< RCC AHB2 reset register                                        Address offset: 0x0A14 */
+  __IO uint32_t AHB3RSTSR;        /*!< RCC AHB3 reset register                                        Address offset: 0x0A18 */
+  __IO uint32_t AHB4RSTSR;        /*!< RCC AHB4 reset register                                        Address offset: 0x0A1C */
+  __IO uint32_t AHB5RSTSR;        /*!< RCC AHB5 reset register                                        Address offset: 0x0A20 */
+  __IO uint32_t APB1RSTSR1;       /*!< RCC APB1 reset register 1                                      Address offset: 0x0A24 */
+  __IO uint32_t APB1RSTSR2;       /*!< RCC APB1 reset register 2                                      Address offset: 0x0A28 */
+  __IO uint32_t APB2RSTSR;        /*!< RCC APB2 reset register                                        Address offset: 0x0A2C */
+       uint32_t RESERVED19;       /*!< Reserved                                                       Address offset: 0x0A30 */
+  __IO uint32_t APB4RSTSR1;       /*!< RCC APB4 reset register 1                                      Address offset: 0x0A34 */
+  __IO uint32_t APB4RSTSR2;       /*!< RCC APB4 reset register 2                                      Address offset: 0x0A38 */
+  __IO uint32_t APB5RSTSR;        /*!< RCC APB5 reset register                                        Address offset: 0x0A3C */
+  __IO uint32_t DIVENSR;          /*!< RCC divider enable register                                    Address offset: 0x0A40 */
+  __IO uint32_t BUSENSR;          /*!< RCC bus enable register                                        Address offset: 0x0A44 */
+  __IO uint32_t MISCENSR;         /*!< RCC miscellaneous enable register                              Address offset: 0x0A48 */
+  __IO uint32_t MEMENSR;          /*!< RCC memory enable register                                     Address offset: 0x0A4C */
+  __IO uint32_t AHB1ENSR;         /*!< RCC AHB1 enable register                                       Address offset: 0x0A50 */
+  __IO uint32_t AHB2ENSR;         /*!< RCC AHB2 enable register                                       Address offset: 0x0A54 */
+  __IO uint32_t AHB3ENSR;         /*!< RCC AHB3 enable register                                       Address offset: 0x0A58 */
+  __IO uint32_t AHB4ENSR;         /*!< RCC AHB4 enable register                                       Address offset: 0x0A5C */
+  __IO uint32_t AHB5ENSR;         /*!< RCC AHB5 enable register                                       Address offset: 0x0A60 */
+  __IO uint32_t APB1ENSR1;        /*!< RCC APB1 enable register 1                                     Address offset: 0x0A64 */
+  __IO uint32_t APB1ENSR2;        /*!< RCC APB1 enable register 2                                     Address offset: 0x0A68 */
+  __IO uint32_t APB2ENSR;         /*!< RCC APB2 enable register                                       Address offset: 0x0A6C */
+  __IO uint32_t APB3ENSR;         /*!< RCC APB3 enable register                                       Address offset: 0x0A70 */
+  __IO uint32_t APB4ENSR1;        /*!< RCC APB4 enable register 1                                     Address offset: 0x0A74 */
+  __IO uint32_t APB4ENSR2;        /*!< RCC APB4 enable register 2                                     Address offset: 0x0A78 */
+  __IO uint32_t APB5ENSR;         /*!< RCC APB5 enable register                                       Address offset: 0x0A7C */
+       uint32_t RESERVED20;       /*!< Reserved                                                       Address offset: 0x0A80 */
+  __IO uint32_t BUSLPENSR;        /*!< RCC bus sleep enable register                                  Address offset: 0x0A84 */
+  __IO uint32_t MISCLPENSR;       /*!< RCC miscellaneous sleep enable register                        Address offset: 0x0A88 */
+  __IO uint32_t MEMLPENSR;        /*!< RCC memory sleep enable register                               Address offset: 0x0A8C */
+  __IO uint32_t AHB1LPENSR;       /*!< RCC AHB1 sleep enable register                                 Address offset: 0x0A90 */
+  __IO uint32_t AHB2LPENSR;       /*!< RCC AHB2 sleep enable register                                 Address offset: 0x0A94 */
+  __IO uint32_t AHB3LPENSR;       /*!< RCC AHB3 sleep enable register                                 Address offset: 0x0A98 */
+  __IO uint32_t AHB4LPENSR;       /*!< RCC AHB4 sleep enable register                                 Address offset: 0x0A9C */
+  __IO uint32_t AHB5LPENSR;       /*!< RCC AHB5 sleep enable register                                 Address offset: 0x0AA0 */
+  __IO uint32_t APB1LPENSR1;      /*!< RCC APB1 sleep enable register 1                               Address offset: 0x0AA4 */
+  __IO uint32_t APB1LPENSR2;      /*!< RCC APB1 sleep enable register 2                               Address offset: 0x0AA8 */
+  __IO uint32_t APB2LPENSR;       /*!< RCC APB2 sleep enable register                                 Address offset: 0x0AAC */
+  __IO uint32_t APB3LPENSR;       /*!< RCC APB3 sleep enable register                                 Address offset: 0x0AB0 */
+  __IO uint32_t APB4LPENSR1;      /*!< RCC APB4 sleep enable register 1                               Address offset: 0x0AB4 */
+  __IO uint32_t APB4LPENSR2;      /*!< RCC APB4 sleep enable register 2                               Address offset: 0x0AB8 */
+  __IO uint32_t APB5LPENSR;       /*!< RCC APB5 sleep enable register                                 Address offset: 0x0ABC */
+       uint32_t RESERVED21[305];  /*!< Reserved                                                       Address offset: 0x0AC0-0x0F80 */
+  __IO uint32_t PRIVCFGSR0;       /*!< RCC oscillator privilege configuration set register 0          Address offset: 0x0F84 */
+       uint32_t RESERVED22;       /*!< Reserved                                                       Address offset: 0x0F88 */
+  __IO uint32_t PUBCFGSR0;        /*!< RCC oscillator public configuration set register 0             Address offset: 0x0F8C */
+       uint32_t RESERVED23;       /*!< Reserved                                                       Address offset: 0x0F90 */
+  __IO uint32_t PRIVCFGSR1;       /*!< RCC PLL privilege configuration set register 1                 Address offset: 0x0F94 */
+       uint32_t RESERVED24;       /*!< Reserved                                                       Address offset: 0x0F98 */
+  __IO uint32_t PUBCFGSR1;        /*!< RCC PLL public configuration set register 1                    Address offset: 0x0F9C */
+       uint32_t RESERVED25;       /*!< Reserved                                                       Address offset: 0x0FA0 */
+  __IO uint32_t PRIVCFGSR2;       /*!< RCC divider privilege configuration set register 2             Address offset: 0x0FA4 */
+       uint32_t RESERVED26;       /*!< Reserved                                                       Address offset: 0x0FA8 */
+  __IO uint32_t PUBCFGSR2;        /*!< RCC divider public configuration set register 2                Address offset: 0x0FAC */
+       uint32_t RESERVED27;       /*!< Reserved                                                       Address offset: 0x0FB0 */
+  __IO uint32_t PRIVCFGSR3;       /*!< RCC system privilege configuration set register 3              Address offset: 0x0FB4 */
+       uint32_t RESERVED28;       /*!< Reserved                                                       Address offset: 0x0FB8 */
+  __IO uint32_t PUBCFGSR3;        /*!< RCC system public configuration set register 3                 Address offset: 0x0FBC */
+       uint32_t RESERVED29;       /*!< Reserved                                                       Address offset: 0x0FC0 */
+  __IO uint32_t PRIVCFGSR4;       /*!< RCC privilege configuration set register 4                     Address offset: 0x0FC4 */
+       uint32_t RESERVED30;       /*!< Reserved                                                       Address offset: 0x0FC8 */
+  __IO uint32_t PUBCFGSR4;        /*!< RCC public configuration set register 4                            Address offset: 0x0FCC */
+  __IO uint32_t PUBCFGSR5;        /*!< RCC public configuration set register 5                            Address offset: 0x0FD0 */
+       uint32_t RESERVED31[11];   /*!< Reserved                                                       Address offset: 0x0FD4-0x0FFC */
+  __IO uint32_t CCR;              /*!< RCC control clear register                                     Address offset: 0x1000 */
+       uint32_t RESERVED32;       /*!< Reserved                                                       Address offset: 0x1004 */
+  __IO uint32_t STOPCCR;          /*!< RCC Stop mode configuration clear register                     Address offset: 0x1008 */
+       uint32_t RESERVED33[127];  /*!< Reserved                                                       Address offset: 0x100C-0x1200 */
+  __IO uint32_t MISCRSTCR;        /*!< RCC miscellaneous reset clear register                         Address offset: 0x1208 */
+  __IO uint32_t MEMRSTCR;         /*!< RCC memory reset clear register                                Address offset: 0x120C */
+  __IO uint32_t AHB1RSTCR;        /*!< RCC AHB1 reset clear register                                  Address offset: 0x1210 */
+  __IO uint32_t AHB2RSTCR;        /*!< RCC AHB2 reset clear register                                  Address offset: 0x1214 */
+  __IO uint32_t AHB3RSTCR;        /*!< RCC AHB3 reset r clear register                                Address offset: 0x1218 */
+  __IO uint32_t AHB4RSTCR;        /*!< RCC AHB4 reset clear register                                  Address offset: 0x121C */
+  __IO uint32_t AHB5RSTCR;        /*!< RCC AHB5 reset clear register                                  Address offset: 0x1220 */
+  __IO uint32_t APB1RSTCR1;       /*!< RCC APB1 reset clear register 1                                Address offset: 0x1224 */
+  __IO uint32_t APB1RSTCR2;       /*!< RCC APB1 reset clear register 2                                Address offset: 0x1228 */
+  __IO uint32_t APB2RSTCR;        /*!< RCC APB2 reset clear register                                  Address offset: 0x122C */
+       uint32_t RESERVED34;       /*!< Reserved                                                       Address offset: 0x1230 */
+  __IO uint32_t APB4RSTCR1;       /*!< RCC APB4 reset clear register 1                                Address offset: 0x1234 */
+  __IO uint32_t APB4RSTCR2;       /*!< RCC APB4 reset clear register 2                                Address offset: 0x1238 */
+  __IO uint32_t APB5RSTCR;        /*!< RCC APB5 reset clear register                                  Address offset: 0x123C */
+  __IO uint32_t DIVENCR;          /*!< RCC divider enable clear register                              Address offset: 0x1240 */
+  __IO uint32_t BUSENCR;          /*!< RCC bus enable clear register                                  Address offset: 0x1244 */
+  __IO uint32_t MISCENCR;         /*!< RCC miscellaneous enable clear register                        Address offset: 0x1248 */
+  __IO uint32_t MEMENCR;          /*!< RCC memory enable clear register                               Address offset: 0x124C */
+  __IO uint32_t AHB1ENCR;         /*!< RCC AHB1 enable clear register                                 Address offset: 0x1250 */
+  __IO uint32_t AHB2ENCR;         /*!< RCC AHB2 enable clear register                                 Address offset: 0x1254 */
+  __IO uint32_t AHB3ENCR;         /*!< RCC AHB3 enable clear register                                 Address offset: 0x1258 */
+  __IO uint32_t AHB4ENCR;         /*!< RCC AHB4 enable clear register                                 Address offset: 0x125C */
+  __IO uint32_t AHB5ENCR;         /*!< RCC AHB5 enable clear register                                 Address offset: 0x1260 */
+  __IO uint32_t APB1ENCR1;        /*!< RCC APB1 enable clear register 1                               Address offset: 0x1264 */
+  __IO uint32_t APB1ENCR2;        /*!< RCC APB1 enable clear register 2                               Address offset: 0x1268 */
+  __IO uint32_t APB2ENCR;         /*!< RCC APB2 enable clear register                                 Address offset: 0x126C */
+  __IO uint32_t APB3ENCR;         /*!< RCC APB3 enable clear register                                 Address offset: 0x1270 */
+  __IO uint32_t APB4ENCR1;        /*!< RCC APB4 enable clear register 1                               Address offset: 0x1274 */
+  __IO uint32_t APB4ENCR2;        /*!< RCC APB4 enable clear register 2                               Address offset: 0x1278 */
+  __IO uint32_t APB5ENCR;         /*!< RCC APB5 enable clear register                                 Address offset: 0x127C */
+       uint32_t RESERVED35;       /*!< Reserved                                                       Address offset: 0x1280 */
+  __IO uint32_t BUSLPENCR;        /*!< RCC bus sleep enable clear register                            Address offset: 0x1284 */
+  __IO uint32_t MISCLPENCR;       /*!< RCC miscellaneous sleep enable clear register                  Address offset: 0x1288 */
+  __IO uint32_t MEMLPENCR;        /*!< RCC memory sleep enable clear register                         Address offset: 0x128C */
+  __IO uint32_t AHB1LPENCR;       /*!< RCC AHB1 sleep enable clear register                           Address offset: 0x1290 */
+  __IO uint32_t AHB2LPENCR;       /*!< RCC AHB2 sleep enable clear register                           Address offset: 0x1294 */
+  __IO uint32_t AHB3LPENCR;       /*!< RCC AHB3 sleep enable clear register                           Address offset: 0x1298 */
+  __IO uint32_t AHB4LPENCR;       /*!< RCC AHB4 sleep enable clear register                           Address offset: 0x129C */
+  __IO uint32_t AHB5LPENCR;       /*!< RCC AHB5 sleep enable clear register                           Address offset: 0x12A0 */
+  __IO uint32_t APB1LPENCR1;      /*!< RCC APB1 sleep enable clear register 1                         Address offset: 0x12A4 */
+  __IO uint32_t APB1LPENCR2;      /*!< RCC APB1 sleep enable clear register 2                         Address offset: 0x12A8 */
+  __IO uint32_t APB2LPENCR;       /*!< RCC APB2 sleep enable clear register                           Address offset: 0x12AC */
+  __IO uint32_t APB3LPENCR;       /*!< RCC APB3 sleep enable clear register                           Address offset: 0x12B0 */
+  __IO uint32_t APB4LPENCR1;      /*!< RCC APB4 sleep enable clear register 1                         Address offset: 0x12B4 */
+  __IO uint32_t APB4LPENCR2;      /*!< RCC APB4 sleep enable clear register 2                         Address offset: 0x12B8 */
+  __IO uint32_t APB5LPENCR;       /*!< RCC APB5 sleep enable clear register                           Address offset: 0x12BC */
+       uint32_t RESERVED36[305];  /*!< Reserved                                                       Address offset: 0x12C0-0x1780 */
+  __IO uint32_t PRIVCFGCR0;       /*!< RCC oscillator privilege configuration clear register 0        Address offset: 0x1784 */
+       uint32_t RESERVED37;       /*!< Reserved                                                       Address offset: 0x1788 */
+  __IO uint32_t PUBCFGCR0;        /*!< RCC oscillator public configuration clear register 0           Address offset: 0x178C */
+       uint32_t RESERVED38;       /*!< Reserved                                                       Address offset: 0x1790 */
+  __IO uint32_t PRIVCFGCR1;       /*!< RCC PLL privilege configuration clear register 1               Address offset: 0x1794 */
+       uint32_t RESERVED39;       /*!< Reserved                                                       Address offset: 0x1798 */
+  __IO uint32_t PUBCFGCR1;        /*!< RCC PLL public configuration clear register 1                  Address offset: 0x179C */
+       uint32_t RESERVED40;       /*!< Reserved                                                       Address offset: 0x17A0 */
+  __IO uint32_t PRIVCFGCR2;       /*!< RCC divider privilege configuration clear register 2           Address offset: 0x17A4 */
+       uint32_t RESERVED41;       /*!< Reserved                                                       Address offset: 0x17A8 */
+  __IO uint32_t PUBCFGCR2;        /*!< RCC divider public configuration clear register 2              Address offset: 0x17AC */
+       uint32_t RESERVED42;       /*!< Reserved                                                       Address offset: 0x17B0 */
+  __IO uint32_t PRIVCFGCR3;       /*!< RCC system privilege configuration clear register 3            Address offset: 0x17B4 */
+       uint32_t RESERVED43;       /*!< Reserved                                                       Address offset: 0x17B8 */
+  __IO uint32_t PUBCFGCR3;        /*!< RCC system public configuration clear register 3               Address offset: 0x17BC */
+       uint32_t RESERVED44;       /*!< Reserved                                                       Address offset: 0x17C0 */
+  __IO uint32_t PRIVCFGCR4;       /*!< RCC privilege configuration clear register 4                   Address offset: 0x17C4 */
+       uint32_t RESERVED45;       /*!< Reserved                                                       Address offset: 0x17C8 */
+  __IO uint32_t PUBCFGCR4;        /*!< RCC public configuration clear register 4                      Address offset: 0x17CC */
+  __IO uint32_t PUBCFGCR5;        /*!< RCC public configuration clear register 5                      Address offset: 0x17D0 */
+} RCC_TypeDef;
+
+/*
+ * @brief  RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1)
+ */
+typedef struct
+{
+  __IO uint32_t RISC_CR;            /*!< RIFSC RISC slave configuration register x               Address offset: 0x000 */
+       uint32_t RESERVED0[3];       /*!< Reserved                                                Address offset: 0x004-0x00C */
+  __IO uint32_t RISC_SECCFGRx[6];   /*!< RIFSC RISC slave security configuration register x      Address offset: 0x010-0x24 */
+       uint32_t RESERVED1[2];       /*!< Reserved                                                Address offset: 0x028-0x02C */
+  __IO uint32_t RISC_PRIVCFGRx[6];  /*!< RIFSC RISFC slave privileged register x                 Address offset: 0x030-0x44 */
+       uint32_t RESERVED2[2];       /*!< Reserved                                                Address offset: 0x048-0x04C */
+  __IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */
+       uint32_t RESERVED3[742];     /*!< Reserved                                                Address offset: 0x068-0xBFC */
+  __IO uint32_t RIMC_CR;            /*!< RIFSC RIMC master configuration register                Address offset: 0xC00 */
+       uint32_t RESERVED4[3];       /*!< Reserved                                                Address offset: 0xC04-0xC0C */
+  __IO uint32_t RIMC_ATTRx[13];     /*!< RIFSC RIMC master attribute register x                  Address offset: 0xC10-0xC40 */
+       uint32_t RESERVED5[219];     /*!< Reserved                                                Address offset: 0xC40-0xFAC */
+  __IO uint32_t PPSRx[6];           /*!< RIFSC peripheral protection status register x           Address offset: 0xFB0-0xFC4 */
+       uint32_t RESERVED6[8];       /*!< Reserved                                                Address offset: 0xFC8-0xFE4 */
+} RIFSC_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version)
+  */
+typedef struct
+{
+  __IO uint32_t CFGR;          /*!< RISAF Region X configuration register             */
+  __IO uint32_t STARTR;        /*!< RISAF Region X start address register             */
+  __IO uint32_t ENDR;          /*!< RISAF Region X end address register               */
+  __IO uint32_t CIDCFGR;       /*!< RISAF Region X CID configuration register         */
+  __IO uint32_t ACFGR;         /*!< RISAF Region X subregion A configuration register */
+  __IO uint32_t ASTARTR;       /*!< RISAF Region X subregion A start address register */
+  __IO uint32_t AENDR;         /*!< RISAF Region X subregion A end address register   */
+  __IO uint32_t ANESTR;        /*!< RISAF Region X subregion A nested mode register   */
+  __IO uint32_t BCFGR;         /*!< RISAF Region X subregion B configuration register */
+  __IO uint32_t BSTARTR;       /*!< RISAF Region X subregion B start address register */
+  __IO uint32_t BENDR;         /*!< RISAF Region X subregion B end address register   */
+  __IO uint32_t BNESTR;        /*!< RISAF Region X subregion B nested mode register   */
+       uint32_t RESERVED0[4];  /*!< Reserved                                          */
+} RISAF_Region_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t IAESR;         /*!< RISAF Illegal access error status register */
+  __IO uint32_t IADDR;         /*!< RISAF Illegal address register,            */
+} RISAF_Illegal_TypeDef;
+
+/**
+  * @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14)
+  */
+typedef struct
+{
+  __IO uint32_t              CR;            /*!< RISAF Configuration register,                            Address offset: 0x000 */
+  __IO uint32_t              RESERVED0;     /*!< Reserved,                                                Address offset: 0x004 */
+  __IO uint32_t              IASR;          /*!< RISAF Illegal access status register,                    Address offset: 0x008 */
+  __IO uint32_t              IACR;          /*!< RISAF Illegal access clear register,                     Address offset: 0x00C */
+       uint32_t              RESERVED1[4];  /*!< Reserved,                                                          0x010-0x01C */
+       RISAF_Illegal_TypeDef IAR[1];        /*!< RISAF Illegal access error status and address register,            0x020-0x024 */
+       uint32_t              RESERVED2[6];  /*!< Reserved,                                                          0x028-0x03C */
+       RISAF_Region_TypeDef  REG[15];       /*!< RISAF Region X configuration register,                             0x040-0x3FC */
+} RISAF_TypeDef;
+
+/**
+  * @brief RNG
+  */
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+  uint32_t RESERVED;
+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
+} RNG_TypeDef;
+
+/*
+* @brief RTC Specific device feature definitions
+*/
+#define RTC_BKP_NB         32U
+#define RTC_TAMP_NB        7U
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
+ __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
+ __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
+ __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
+ __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
+ __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
+ __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
+__IO uint32_t SECCFGR;      /*!< RTC secure mode control register,               Address offset: 0x20 */
+ __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
+ __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
+ __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
+ __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
+ __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
+ __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
+      uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
+ __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
+ __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
+ __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
+ __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
+ __IO uint32_t SMISR;       /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
+ __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
+      uint32_t RESERVED3[4];/*!< Reserved,                                       Address offset: 0x58 */
+ __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
+ __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
+} RTC_TypeDef;
+
+/**
+  * @brief SAES Processor
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< SAES control register,                      Address offset: 0x000 */
+  __IO uint32_t SR;             /*!< SAES status register,                       Address offset: 0x004 */
+  __IO uint32_t DINR;           /*!< SAES data input register,                   Address offset: 0x008 */
+  __IO uint32_t DOUTR;          /*!< SAES data output register,                  Address offset: 0x00C */
+  __IO uint32_t KEYR0;          /*!< SAES key register 0,                        Address offset: 0x010 */
+  __IO uint32_t KEYR1;          /*!< SAES key register 1,                        Address offset: 0x014 */
+  __IO uint32_t KEYR2;          /*!< SAES key register 2,                        Address offset: 0x018 */
+  __IO uint32_t KEYR3;          /*!< SAES key register 3,                        Address offset: 0x01C */
+  __IO uint32_t IVR0;           /*!< SAES initialization vector register 0,      Address offset: 0x020 */
+  __IO uint32_t IVR1;           /*!< SAES initialization vector register 1,      Address offset: 0x024 */
+  __IO uint32_t IVR2;           /*!< SAES initialization vector register 2,      Address offset: 0x028 */
+  __IO uint32_t IVR3;           /*!< SAES initialization vector register 3,      Address offset: 0x02C */
+  __IO uint32_t KEYR4;          /*!< SAES key register 4,                        Address offset: 0x030 */
+  __IO uint32_t KEYR5;          /*!< SAES key register 5,                        Address offset: 0x034 */
+  __IO uint32_t KEYR6;          /*!< SAES key register 6,                        Address offset: 0x038 */
+  __IO uint32_t KEYR7;          /*!< SAES key register 7,                        Address offset: 0x03C */
+       uint32_t RESERVED1[48];  /*!< Reserved,                                   Address offset: 0x040 -- 0x0FC */
+  __IO uint32_t DPACFGR;        /*!< SAES DPA configuration register,            Address offset: 0x100 */
+       uint32_t RESERVED2[127]; /*!< Reserved,                                   Address offset: 0x104 -- 0x2FC */
+  __IO uint32_t IER;            /*!< SAES Interrupt Enable Register,             Address offset: 0x300 */
+  __IO uint32_t ISR;            /*!< SAES Interrupt Status Register,             Address offset: 0x304 */
+  __IO uint32_t ICR;            /*!< SAES Interrupt Clear Register,              Address offset: 0x308 */
+} SAES_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+typedef struct
+{
+  __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
+  uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
+  __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
+  __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,              Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,              Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                   Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                    Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,           Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                 Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                 Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                 Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                 Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                 Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,                Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,               Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,               Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,                     Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,            Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                       Address offset: 0x3C */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,      Address offset: 0x40 */
+  __IO uint32_t FIFOTHR;        /*!< SDMMC data FIFO threshold register,        Address offset: 0x44 */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x48 - 0x4C                                           */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,                Address offset: 0x50 */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,            Address offset: 0x54 */
+  __IO uint32_t IDMABASER;      /*!< SDMMC DMA buffer base address register,    Address offset: 0x58 */
+  uint32_t      RESERVED1[2];   /*!< Reserved, 0x5C - 0x60                                           */
+  __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,    Address offset: 0x64 */
+  __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
+  uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                  Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+/**
+  * @brief SPI
+  */
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief UCPD
+  */
+typedef struct
+{
+  __IO uint32_t CFG1;        /*!< UCPD configuration register 1,            Address offset: 0x00 */
+  __IO uint32_t CFG2;        /*!< UCPD configuration register 2,            Address offset: 0x04 */
+  __IO uint32_t RESERVED0;   /*!< UCPD reserved register,                   Address offset: 0x08 */
+  __IO uint32_t CR;          /*!< UCPD control register,                    Address offset: 0x0C */
+  __IO uint32_t IMR;         /*!< UCPD interrupt mask register,             Address offset: 0x10 */
+  __IO uint32_t SR;          /*!< UCPD status register,                     Address offset: 0x14 */
+  __IO uint32_t ICR;         /*!< UCPD interrupt flag clear register        Address offset: 0x18 */
+  __IO uint32_t TX_ORDSET;   /*!< UCPD Tx ordered set type register,        Address offset: 0x1C */
+  __IO uint32_t TX_PAYSZ;    /*!< UCPD Tx payload size register,            Address offset: 0x20 */
+  __IO uint32_t TXDR;        /*!< UCPD Tx data register,                    Address offset: 0x24 */
+  __IO uint32_t RX_ORDSET;   /*!< UCPD Rx ordered set type register,        Address offset: 0x28 */
+  __IO uint32_t RX_PAYSZ;    /*!< UCPD Rx payload size register,            Address offset: 0x2C */
+  __IO uint32_t RXDR;        /*!< UCPD Rx data register,                    Address offset: 0x30 */
+  __IO uint32_t RX_ORDEXT1;  /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
+  __IO uint32_t RX_ORDEXT2;  /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
+} UCPD_TypeDef;
+
+/**
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;             /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t GOTGINT;             /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t GAHBCFG;             /*!< Core AHB Configuration Register,           Address offset: 008h */
+  __IO uint32_t GUSBCFG;             /*!< Core USB Configuration Register,           Address offset: 00Ch */
+  __IO uint32_t GRSTCTL;             /*!< Core Reset Register,                       Address offset: 010h */
+  __IO uint32_t GINTSTS;             /*!< Core Interrupt Register,                   Address offset: 014h */
+  __IO uint32_t GINTMSK;             /*!< Core Interrupt Mask Register,              Address offset: 018h */
+  __IO uint32_t GRXSTSR;             /*!< Receive Sts Q Read Register,               Address offset: 01Ch */
+  __IO uint32_t GRXSTSP;             /*!< Receive Sts Q Read & POP Register,         Address offset: 020h */
+  __IO uint32_t GRXFSIZ;             /*!< Receive FIFO Size Register,                Address offset: 024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;  /*!< EP0 / Non Periodic Tx FIFO Size Register,  Address offset: 028h */
+  __IO uint32_t HNPTXSTS;            /*!< Non Periodic Tx FIFO/Queue Sts reg,        Address offset: 02Ch */
+  __IO uint32_t Reserved30[2];       /*!< Reserved,                                  Address offset: 030h */
+  __IO uint32_t GCCFG;               /*!< General Purpose IO Register,               Address offset: 038h */
+  __IO uint32_t CID;                 /*!< User ID Register,                          Address offset: 03Ch */
+  __IO uint32_t GSNPSID;             /*!< USB_OTG core ID,                           Address offset: 040h */
+  __IO uint32_t GHWCFG1;             /*!< User HW config1,                           Address offset: 044h */
+  __IO uint32_t GHWCFG2;             /*!< User HW config2,                           Address offset: 048h */
+  __IO uint32_t GHWCFG3;             /*!< User HW config3,                           Address offset: 04Ch */
+  __IO uint32_t Reserved6;           /*!< Reserved,                                  Address offset: 050h */
+  __IO uint32_t GLPMCFG;             /*!< LPM Register,                              Address offset: 054h */
+  __IO uint32_t GPWRDN;              /*!< Power Down Register,                       Address offset: 058h */
+  __IO uint32_t GDFIFOCFG;           /*!< DFIFO Software Config Register,            Address offset: 05Ch */
+  __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register,    Address offset: 60Ch */
+  __IO uint32_t Reserved43[39];      /*!< Reserved,                                  Address offset: 058h */
+  __IO uint32_t HPTXFSIZ;            /*!< Host Periodic Tx FIFO Size Reg,            Address offset: 100h */
+  __IO uint32_t DIEPTXF[0x0F];       /*!< dev Periodic Transmit FIFO                 Address offset: 104h */
+} USB_OTG_GlobalTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;          /*!< USB_OTG Control and Status Register,       Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;     /*!< USB_OTG Interrupt Register,                Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;     /*!< Core AHB Configuration Register,           Address offset: 008h */
+} USB_PHY_GlobalTypeDef;
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;                /*!< dev Configuration Register,   Address offset: 800h */
+  __IO uint32_t DCTL;                /*!< dev Control Register,         Address offset: 804h */
+  __IO uint32_t DSTS;                /*!< dev Status Register (RO),     Address offset: 808h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                     Address offset: 80Ch */
+  __IO uint32_t DIEPMSK;             /*!< dev IN Endpoint Mask,         Address offset: 810h */
+  __IO uint32_t DOEPMSK;             /*!< dev OUT Endpoint Mask,        Address offset: 814h */
+  __IO uint32_t DAINT;               /*!< dev All Endpoints Itr Reg,    Address offset: 818h */
+  __IO uint32_t DAINTMSK;            /*!< dev All Endpoints Itr Mask,   Address offset: 81Ch */
+  __IO uint32_t Reserved20;          /*!< Reserved,                     Address offset: 820h */
+  __IO uint32_t Reserved9;           /*!< Reserved,                     Address offset: 824h */
+  __IO uint32_t DVBUSDIS;            /*!< dev VBUS discharge Register,  Address offset: 828h */
+  __IO uint32_t DVBUSPULSE;          /*!< dev VBUS Pulse Register,      Address offset: 82Ch */
+  __IO uint32_t DTHRCTL;             /*!< dev threshold,                Address offset: 830h */
+  __IO uint32_t DIEPEMPMSK;          /*!< dev empty msk,                Address offset: 834h */
+  __IO uint32_t DEACHINT;            /*!< dedicated EP interrupt,       Address offset: 838h */
+  __IO uint32_t DEACHMSK;            /*!< dedicated EP msk,             Address offset: 83Ch */
+  __IO uint32_t Reserved40;          /*!< dedicated EP mask,            Address offset: 840h */
+  __IO uint32_t DINEP1MSK;           /*!< dedicated EP mask,            Address offset: 844h */
+  __IO uint32_t Reserved44[15];      /*!< Reserved,                     Address offset: 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;          /*!< dedicated EP msk,             Address offset: 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;             /*!< dev IN Endpoint Control Register,          Address offset: 900h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;             /*!< dev IN Endpoint Itr Register,              Address offset: 900h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;            /*!< IN Endpoint Txfer Size Register,           Address offset: 900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;             /*!< IN Endpoint DMA Address Register,          Address offset: 900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;             /*!< IN Endpoint Tx FIFO Status Register,       Address offset: 900h + (ep_num * 20h) + 18h */
+  __IO uint32_t Reserved18;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;             /*!< dev OUT Endpoint Control Register,         Address offset: B00h + (ep_num * 20h) + 00h */
+  __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;             /*!< dev OUT Endpoint Itr Register,             Address offset: B00h + (ep_num * 20h) + 08h */
+  __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;            /*!< dev OUT Endpoint Txfer Size Register,      Address offset: B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;             /*!< dev OUT Endpoint DMA Address Register,     Address offset: B00h + (ep_num * 20h) + 14h */
+  __IO uint32_t Reserved18[2];       /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 18h */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;                 /*!< Host Configuration Register,              Address offset: 400h */
+  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register,             Address offset: 404h */
+  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining,           Address offset: 408h */
+  __IO uint32_t Reserved40C;          /*!< Reserved,                                 Address offset: 40Ch */
+  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status,      Address offset: 410h */
+  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register,     Address offset: 414h */
+  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask,         Address offset: 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;               /*!< Host Channel Characteristics Register,    Address offset: 500h */
+  __IO uint32_t HCSPLT;               /*!< Host Channel Split Control Register,      Address offset: 504h */
+  __IO uint32_t HCINT;                /*!< Host Channel Interrupt Register,          Address offset: 508h */
+  __IO uint32_t HCINTMSK;             /*!< Host Channel Interrupt Mask Register,     Address offset: 50Ch */
+  __IO uint32_t HCTSIZ;               /*!< Host Channel Transfer Size Register,      Address offset: 510h */
+  __IO uint32_t HCDMA;                /*!< Host Channel DMA Address Register,        Address offset: 514h */
+  uint32_t Reserved[2];               /*!< Reserved,                                 Address offset: 518h */
+} USB_OTG_HostChannelTypeDef;
+
+typedef struct
+{
+  __IO uint32_t USBPHYC_CR;           /*!< USB HS PHY Control Register,              Address offset: 000h */
+  __IO uint32_t USBPHYC_TRIM1CR;      /*!< USB HS PHY Trimming_1 Register,           Address offset: 004h */
+  __IO uint32_t USBPHYC_TRIM2CR;      /*!< USB HS PHY Trimming_2 Register,           Address offset: 008h */
+} USB_HS_PHYC_GlobalTypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t IMR;         /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t IFCR;        /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t DR;          /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t CSR;         /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t DIR;         /*!< Debug Information register,         Address offset: 0x18 */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+typedef struct
+{
+  __IO uint32_t BOOTCR;         /*!< SYSCFG boot pin control register,                                            Address offset: 0x00 */
+  __IO uint32_t CM55CR;         /*!< SYSCFG Cortex-M55 control register,                                          Address offset: 0x04 */
+  __IO uint32_t CM55TCMCR;      /*!< SYSCFG Cortex-M55 TCM control register,                                      Address offset: 0x08 */
+  __IO uint32_t CM55RWMCR;      /*!< SYSCFG Cortex-M55 memory RW margin register,                                 Address offset: 0x0C */
+  __IO uint32_t INITSVTORCR;    /*!< SYSCFG Cortex-M55 SVTOR control register,                                    Address offset: 0x10 */
+  __IO uint32_t INITNSVTORCR;   /*!< Cortex-M55 NSVTOR control register,                                          Address offset: 0x14 */
+  __IO uint32_t CM55RSTCR;      /*!< SYSCFG Cortex-M55 reset type control register,                               Address offset: 0x18 */
+  __IO uint32_t CM55PAHBWPR;    /*!< SYSCFG Cortex-M55 P-AHB write posting control register,                      Address offset: 0x1C */
+  __IO uint32_t VENCRAMCR;      /*!< SYSCFG VENCRAM control register,                                             Address offset: 0x20 */
+  __IO uint32_t POTTAMPRSTCR;   /*!< SYSCFG potential tamper reset register,                                      Address offset: 0x24 */
+  __IO uint32_t NPUNICQOSCR;    /*!< SYSCFG NPUNIC QoS control register,                                          Address offset: 0x28 */
+  uint32_t      RESERVED1[2];   /*!< Reserved,                                                                    Address offset: 0x2C-0x30 */
+  __IO uint32_t ICNEWRCR;       /*!< SYSCFG AHB-AXI bridge early write response,                                  Address offset: 0x34 */
+  __IO uint32_t ICNCGCR;        /*!< SYSCFG ICN clock gating control register,                                    Address offset: 0x38 */
+  uint32_t      RESERVED2[2];   /*!< Reserved,                                                                    Address offset: 0x3C-0x40 */
+  __IO uint32_t VDDIO2CCCR;     /*!< SYSCFG VDDIO2 compensation cell control register,                            Address offset: 0x44 */
+  __IO uint32_t VDDIO2CCSR;     /*!< SYSCFG VDDIO2 compensation cell status register,                             Address offset: 0x48 */
+  __IO uint32_t VDDIO3CCCR;     /*!< SYSCFG VDDIO3 compensation cell control register,                            Address offset: 0x4C */
+  __IO uint32_t VDDIO3CCSR;     /*!< SYSCFG VDDIO3 compensation cell status register,                             Address offset: 0x50 */
+  __IO uint32_t VDDIO4CCCR;     /*!< SYSCFG VDDIO4 compensation cell control register,                            Address offset: 0x54 */
+  __IO uint32_t VDDIO4CCSR;     /*!< SYSCFG VDDIO4 compensation cell status register,                             Address offset: 0x58 */
+  __IO uint32_t VDDIO5CCCR;     /*!< SYSCFG VDDIO5 compensation cell control register,                            Address offset: 0x5C */
+  __IO uint32_t VDDIO5CCSR;     /*!< SYSCFG VDDIO5 compensation cell status register,                             Address offset: 0x60 */
+  __IO uint32_t VDDCCCR;        /*!< SYSCFG VDD compensation cell control register,                               Address offset: 0x64 */
+  __IO uint32_t VDDCCSR;        /*!< SYSCFG VDD compensation cell status register,                                Address offset: 0x68 */
+  __IO uint32_t CBR;            /*!< SYSCFG control timer break register,                                         Address offset: 0x6C */
+  __IO uint32_t SEC_AIDCR;      /*!< SYSCFG DMA CID secure control register,                                      Address offset: 0x70 */
+  __IO uint32_t FMC_RETIMECR;   /*!< SYSCFG FMC retiming logic control register,                                  Address offset: 0x74 */
+  __IO uint32_t NPU_ICNCR;      /*!< SYSCFG NPU RAM interleaving control register,                                Address offset: 0x78 */
+  uint32_t      RESERVED3[33];  /*!< Reserved,                                                                    Address offset: 0x7C-0xFC */
+  __IO uint32_t BOOTSR;         /*!< SYSCFG boot pin status register,                                             Address offset: 0x100 */
+  __IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register,                             Address offset: 0x104 */
+  uint32_t      RESERVED4[446]; /*!< Reserved,                                                                    Address offset: 0x108-0x3FC */
+  __IO uint32_t SECPRIV_AIDCR;  /*!< SYSCFG DMA CID non-secure control register,                                  Address offset: 0x800 */
+  uint32_t      RESERVED5[507]; /*!< Reserved,                                                                    Address offset: 0x804-0xFEC */
+  __IO uint32_t DEVICEID;       /*!< SYSCFG Device ID,                                                            Address offset: 0xFF0 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Tamper and backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1;           /*!< TAMP configuration register 1,                    Address offset: 0x00 */
+ __IO uint32_t CR2;           /*!< TAMP configuration register 2,                    Address offset: 0x04 */
+ __IO uint32_t CR3;           /*!< TAMP configuration register 3,                    Address offset: 0x08 */
+ __IO uint32_t FLTCR;         /*!< TAMP filter control register,                     Address offset: 0x0C */
+ __IO uint32_t ATCR1;         /*!< TAMP filter control register 1                    Address offset: 0x10 */
+ __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,                 Address offset: 0x14 */
+ __IO uint32_t ATOR;          /*!< TAMP active tamper output register,               Address offset: 0x18 */
+ __IO uint32_t ATCR2;         /*!< TAMP filter control register 2,                   Address offset: 0x1C */
+ __IO uint32_t SECCFGR;       /*!< TAMP secure mode control register,                Address offset: 0x20 */
+ __IO uint32_t PRIVCFGR;      /*!< TAMP privilege mode control register,             Address offset: 0x24 */
+      uint32_t RESERVED2;     /*!< Reserved,                                         Address offset: 0x28 */
+ __IO uint32_t IER;           /*!< TAMP interrupt enable register,                   Address offset: 0x2C */
+ __IO uint32_t SR;            /*!< TAMP status register,                             Address offset: 0x30 */
+ __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,            Address offset: 0x34 */
+ __IO uint32_t SMISR;         /*!< TAMP secure masked interrupt status register,     Address offset: 0x38 */
+ __IO uint32_t SCR;           /*!< TAMP status clear register,                       Address offset: 0x3C */
+ __IO uint32_t COUNT1R;       /*!< TAMP monotonic counter register,                  Address offset: 0x40 */
+      uint32_t RESERVED4[3];  /*!< Reserved,                                         Address offset: 0x43 -- 0x4C */
+ __IO uint32_t OR;            /*!< TAMP option register,                             Address offset: 0x50 */
+ __IO uint32_t RPCFGR;        /*!< TAMP resources protection configuration register, Address offset: 0x54 */
+      uint32_t RESERVED5[42]; /*!< Reserved,                                         Address offset: 0x58 -- 0xFC */
+ __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                           Address offset: 0x100 */
+ __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                           Address offset: 0x104 */
+ __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                           Address offset: 0x108 */
+ __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                           Address offset: 0x10C */
+ __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                           Address offset: 0x110 */
+ __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                           Address offset: 0x114 */
+ __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                           Address offset: 0x118 */
+ __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                           Address offset: 0x11C */
+ __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                           Address offset: 0x120 */
+ __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                           Address offset: 0x124 */
+ __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                          Address offset: 0x128 */
+ __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                          Address offset: 0x12C */
+ __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                          Address offset: 0x130 */
+ __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                          Address offset: 0x134 */
+ __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                          Address offset: 0x138 */
+ __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                          Address offset: 0x13C */
+ __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                          Address offset: 0x140 */
+ __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                          Address offset: 0x144 */
+ __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                          Address offset: 0x148 */
+ __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                          Address offset: 0x14C */
+ __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                          Address offset: 0x150 */
+ __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                          Address offset: 0x154 */
+ __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                          Address offset: 0x158 */
+ __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                          Address offset: 0x15C */
+ __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                          Address offset: 0x160 */
+ __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                          Address offset: 0x164 */
+ __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                          Address offset: 0x168 */
+ __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                          Address offset: 0x16C */
+ __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                          Address offset: 0x170 */
+ __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                          Address offset: 0x174 */
+ __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                          Address offset: 0x178 */
+ __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                          Address offset: 0x17C */
+} TAMP_TypeDef;
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint32_t CR1;            /*!< TIM control register 1,                   Address offset:  0x00 */
+  __IO uint32_t CR2;            /*!< TIM control register 2,                   Address offset:  0x04 */
+  __IO uint32_t SMCR;           /*!< TIM slave mode control register,          Address offset:  0x08 */
+  __IO uint32_t DIER;           /*!< TIM DMA/interrupt enable register,        Address offset:  0x0C */
+  __IO uint32_t SR;             /*!< TIM status register,                      Address offset:  0x10 */
+  __IO uint32_t EGR;            /*!< TIM event generation register,            Address offset:  0x14 */
+  __IO uint32_t CCMR1;          /*!< TIM capture/compare mode register 1,      Address offset:  0x18 */
+  __IO uint32_t CCMR2;          /*!< TIM capture/compare mode register 2,      Address offset:  0x1C */
+  __IO uint32_t CCER;           /*!< TIM capture/compare enable register,      Address offset:  0x20 */
+  __IO uint32_t CNT;            /*!< TIM counter register,                     Address offset:  0x24 */
+  __IO uint32_t PSC;            /*!< TIM prescaler,                            Address offset:  0x28 */
+  __IO uint32_t ARR;            /*!< TIM auto-reload register,                 Address offset:  0x2C */
+  __IO uint32_t RCR;            /*!< TIM repetition counter register,          Address offset:  0x30 */
+  __IO uint32_t CCR1;           /*!< TIM capture/compare register 1,           Address offset:  0x34 */
+  __IO uint32_t CCR2;           /*!< TIM capture/compare register 2,           Address offset:  0x38 */
+  __IO uint32_t CCR3;           /*!< TIM capture/compare register 3,           Address offset:  0x3C */
+  __IO uint32_t CCR4;           /*!< TIM capture/compare register 4,           Address offset:  0x40 */
+  __IO uint32_t BDTR;           /*!< TIM break and dead-time register,         Address offset:  0x44 */
+  __IO uint32_t CCR5;           /*!< TIM capture/compare register 5,           Address offset:  0x48 */
+  __IO uint32_t CCR6;           /*!< TIM capture/compare register 6,           Address offset:  0x4C */
+  __IO uint32_t CCMR3;          /*!< TIM capture/compare mode register 3,      Address offset:  0x50 */
+  __IO uint32_t DTR2;           /*!< TIM deadtime register 2,                  Address offset:  0x54 */
+  __IO uint32_t ECR;            /*!< TIM encoder control register,             Address offset:  0x58 */
+  __IO uint32_t TISEL;          /*!< TIM Input Selection register,             Address offset:  0x5C */
+  __IO uint32_t AF1;            /*!< TIM alternate function option register 1, Address offset:  0x60 */
+  __IO uint32_t AF2;            /*!< TIM alternate function option register 2, Address offset:  0x64 */
+       uint32_t RESERVED1[221]; /*!< Reserved,                                            0x6C-0x3D8 */
+  __IO uint32_t DCR;            /*!< TIM DMA control register,                 Address offset: 0x3DC */
+  __IO uint32_t DMAR;           /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C */
+} USART_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief Window Watchdog
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,              Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,               Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief Extended-SPI Interface
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI Control Register,                                Address offset: 0x000         */
+       uint32_t RESERVED1;      /*!< Reserved,                                             Address offset: 0x004         */
+  __IO uint32_t DCR1;           /*!< XSPI Device Configuration Register 1,                 Address offset: 0x008         */
+  __IO uint32_t DCR2;           /*!< XSPI Device Configuration Register 2,                 Address offset: 0x00C         */
+  __IO uint32_t DCR3;           /*!< XSPI Device Configuration Register 3,                 Address offset: 0x010         */
+  __IO uint32_t DCR4;           /*!< XSPI Device Configuration Register 4,                 Address offset: 0x014         */
+       uint32_t RESERVED2[2];   /*!< Reserved,                                             Address offset: 0x018 - 0x01C */
+  __IO uint32_t SR;             /*!< XSPI Status Register,                                 Address offset: 0x020         */
+  __IO uint32_t FCR;            /*!< XSPI Flag Clear Register,                             Address offset: 0x024         */
+       uint32_t RESERVED3[6];   /*!< Reserved,                                             Address offset: 0x028 - 0x03C */
+  __IO uint32_t DLR;            /*!< XSPI Data Length Register,                            Address offset: 0x040         */
+       uint32_t RESERVED4;      /*!< Reserved,                                             Address offset: 0x044         */
+  __IO uint32_t AR;             /*!< XSPI Address Register,                                Address offset: 0x048         */
+       uint32_t RESERVED5;      /*!< Reserved,                                             Address offset: 0x04C         */
+  __IO uint32_t DR;             /*!< XSPI Data Register,                                   Address offset: 0x050         */
+       uint32_t RESERVED6[11];  /*!< Reserved,                                             Address offset: 0x054 - 0x07C */
+  __IO uint32_t PSMKR;          /*!< XSPI Polling Status Mask Register,                    Address offset: 0x080         */
+       uint32_t RESERVED7;      /*!< Reserved,                                             Address offset: 0x084         */
+  __IO uint32_t PSMAR;          /*!< XSPI Polling Status Match Register,                   Address offset: 0x088         */
+       uint32_t RESERVED8;      /*!< Reserved,                                             Address offset: 0x08C         */
+  __IO uint32_t PIR;            /*!< XSPI Polling Interval Register,                       Address offset: 0x090         */
+       uint32_t RESERVED9[27];  /*!< Reserved,                                             Address offset: 0x094 - 0x0FC */
+  __IO uint32_t CCR;            /*!< XSPI Communication Configuration Register,            Address offset: 0x100         */
+       uint32_t RESERVED10;     /*!< Reserved,                                             Address offset: 0x104         */
+  __IO uint32_t TCR;            /*!< XSPI Timing Configuration Register,                   Address offset: 0x108         */
+       uint32_t RESERVED11;     /*!< Reserved,                                             Address offset: 0x10C         */
+  __IO uint32_t IR;             /*!< XSPI Instruction Register,                            Address offset: 0x110         */
+       uint32_t RESERVED12[3];  /*!< Reserved,                                             Address offset: 0x114 - 0x11C */
+  __IO uint32_t ABR;            /*!< XSPI Alternate Bytes Register,                        Address offset: 0x120         */
+       uint32_t RESERVED13[3];  /*!< Reserved,                                             Address offset: 0x124 - 0x12C */
+  __IO uint32_t LPTR;           /*!< XSPI Low-Power Timeout Register,                      Address offset: 0x130         */
+       uint32_t RESERVED14[3];  /*!< Reserved,                                             Address offset: 0x134 - 0x13C */
+  __IO uint32_t WPCCR;          /*!< XSPI Wrap Communication Configuration Register,       Address offset: 0x140         */
+       uint32_t RESERVED15;     /*!< Reserved,                                             Address offset: 0x144         */
+  __IO uint32_t WPTCR;          /*!< XSPI Wrap Timing Configuration Register,              Address offset: 0x148         */
+       uint32_t RESERVED16;     /*!< Reserved,                                             Address offset: 0x14C         */
+  __IO uint32_t WPIR;           /*!< XSPI Wrap Instruction Register,                       Address offset: 0x150         */
+       uint32_t RESERVED17[3];  /*!< Reserved,                                             Address offset: 0x154 - 0x15C */
+  __IO uint32_t WPABR;          /*!< XSPI Wrap Alternate Bytes Register,                   Address offset: 0x160         */
+       uint32_t RESERVED18[7];  /*!< Reserved,                                             Address offset: 0x164 - 0x17C */
+  __IO uint32_t WCCR;           /*!< XSPI Write Communication Configuration Register,      Address offset: 0x180         */
+       uint32_t RESERVED19;     /*!< Reserved,                                             Address offset: 0x184         */
+  __IO uint32_t WTCR;           /*!< XSPI Write Timing Configuration Register,             Address offset: 0x188         */
+       uint32_t RESERVED20;     /*!< Reserved,                                             Address offset: 0x18C         */
+  __IO uint32_t WIR;            /*!< XSPI Write Instruction Register,                      Address offset: 0x190         */
+       uint32_t RESERVED21[3];  /*!< Reserved,                                             Address offset: 0x194 - 0x19C */
+  __IO uint32_t WABR;           /*!< XSPI Write Alternate Bytes Register,                  Address offset: 0x1A0         */
+       uint32_t RESERVED22[23]; /*!< Reserved,                                             Address offset: 0x1A4 - 0x1FC */
+  __IO uint32_t HLCR;           /*!< XSPI HyperBus Latency Configuration Register,         Address offset: 0x200         */
+       uint32_t RESERVED23[3];  /*!< Reserved,                                             Address offset: 0x204 - 0x20C */
+  __IO uint32_t CALFCR;         /*!< XSPI Full-Cycle Calibration Configuration Register,   Address offset: 0x210         */
+       uint32_t RESERVED24;     /*!< Reserved,                                             Address offset: 0x214         */
+  __IO uint32_t CALMR;          /*!< XSPI DLL Master Calibration Configuration Register,   Address offset: 0x218         */
+       uint32_t RESERVED25;     /*!< Reserved,                                             Address offset: 0x21C         */
+  __IO uint32_t CALSOR;         /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220         */
+       uint32_t RESERVED26;     /*!< Reserved,                                             Address offset: 0x224         */
+  __IO uint32_t CALSIR;         /*!< XSPI Slave Input Calibration Configuration Register,  Address offset: 0x228         */
+} XSPI_TypeDef;
+
+/**
+  * @brief XSPI IO Manager
+  */
+typedef struct
+{
+  __IO uint32_t CR;             /*!< XSPI IO Manager Control Register,                     Address offset: 0x00        */
+} XSPIM_TypeDef;
+
+/** @} */ /* End of group STM32N6xx_peripherals */
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_peripheralAddr
+  * @{
+  */
+
+/* Internal RAMs sizes */
+#define SRAM1_AXI_SIZE                  0x100000UL   /*!< SRAM1_AXI = 1024 Kbytes */
+#define SRAM2_AXI_SIZE                  0x100000UL   /*!< SRAM2_AXI = 1024 Kbytes */
+#define FLEXRAM_SIZE                     0x64000UL   /*!< FLEXRAM <= 400 Kbytes   */
+#define SRAM3_AXI_SIZE                   0x70000UL   /*!< SRAM3_AXI = 448 Kbytes  */
+#define SRAM4_AXI_SIZE                   0x70000UL   /*!< SRAM4_AXI = 448 Kbytes  */
+#define SRAM5_AXI_SIZE                   0x70000UL   /*!< SRAM5_AXI = 448 Kbytes  */
+#define SRAM6_AXI_SIZE                   0x70000UL   /*!< SRAM6_AXI = 448 Kbytes  */
+#define SRAM1_AHB_SIZE                    0x4000UL   /*!< SRAM1_AHB = 16 Kbytes   */
+#define SRAM2_AHB_SIZE                    0x4000UL   /*!< SRAM2_AHB = 16 Kbytes   */
+#define VENC_RAM_SIZE                    0x20000UL   /*!< VENC RAM  = 128 Kbytes  */
+#define CACHEAXI_RAM_SIZE                0x40000UL   /*!< CACHEAXI RAM = 256 Kbytes */
+#define BKPSRAM_SIZE                      0x2000UL   /*!< BKPSRAM  = 8 Kbytes     */
+
+
+#define FMC_BASE                        0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */
+#define FMC_BANK1                       FMC_BASE
+#define FMC_BANK1_1                     FMC_BANK1
+#define FMC_BANK1_2                     (FMC_BANK1 + 0x04000000UL)
+#define FMC_BANK1_3                     (FMC_BANK1 + 0x08000000UL)
+#define FMC_BANK1_4                     (FMC_BANK1 + 0x0C000000UL)
+#define FMC_BANK5                       0xC0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK5_1                     FMC_BANK5
+#define FMC_BANK5_2                     (FMC_BANK5 + 0x04000000UL)
+#define FMC_BANK5_3                     (FMC_BANK5 + 0x08000000UL)
+#define FMC_BANK5_4                     (FMC_BANK5 + 0x0C000000UL)
+#define FMC_BANK6                       0xD0000000UL  /*!< Base address of : FMC SDRAM memories accessible over AXI */
+#define FMC_BANK6_1                     FMC_BANK6
+#define FMC_BANK6_2                     (FMC_BANK6 + 0x04000000UL)
+#define FMC_BANK6_3                     (FMC_BANK6 + 0x08000000UL)
+#define FMC_BANK6_4                     (FMC_BANK6 + 0x0C000000UL)
+#define XSPI1_BASE                      0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI    */
+#define XSPI2_BASE                      0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI    */
+#define XSPI3_BASE                      0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI    */
+
+/**************************************************************************/
+/*                                                                        */
+/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */
+/*                                                                        */
+/**************************************************************************/
+
+#define ITCM_BASE_NS                    0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_NS                 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_NS                    0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_NS               0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_NS               0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_NS               0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_NS               0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_NS               0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_NS               0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_NS                SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define CACHEAXI_RAM_BASE_NS            0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI   */
+#define VENC_RAM_BASE_NS                0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS  0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS  0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS  0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS  0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_NS         0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_NS               0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_NS               0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_NS                SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */
+#define BKPSRAM_BASE_NS                 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge      */
+#define PERIPH_BASE_NS                  0x40000000UL /*!< Base address of : AHB/APB Peripherals                      */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_NS              PERIPH_BASE_NS
+#define AHB1PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x00020000UL)
+#define APB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02000000UL)
+#define AHB2PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x02020000UL)
+#define APB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04000000UL)
+#define AHB3PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x04020000UL)
+#define APB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06000000UL)
+#define AHB4PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x06020000UL)
+#define APB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08000000UL)
+#define AHB5PERIPH_BASE_NS              (PERIPH_BASE_NS + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0000UL)
+#define TIM3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0400UL)
+#define TIM4_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0800UL)
+#define TIM5_BASE_NS                    (APB1PERIPH_BASE_NS + 0x0C00UL)
+#define TIM6_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1000UL)
+#define TIM7_BASE_NS                    (APB1PERIPH_BASE_NS + 0x1400UL)
+#define TIM12_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1800UL)
+#define TIM13_BASE_NS                   (APB1PERIPH_BASE_NS + 0x1C00UL)
+#define TIM14_BASE_NS                   (APB1PERIPH_BASE_NS + 0x2000UL)
+#define LPTIM1_BASE_NS                  (APB1PERIPH_BASE_NS + 0x2400UL)
+#define WWDG_BASE_NS                    (APB1PERIPH_BASE_NS + 0x2C00UL)
+#define TIM10_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3000UL)
+#define TIM11_BASE_NS                   (APB1PERIPH_BASE_NS + 0x3400UL)
+#define SPI2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3800UL)
+#define SPI3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x3C00UL)
+#define SPDIFRX_BASE_NS                 (APB1PERIPH_BASE_NS + 0x4000UL)
+#define USART2_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4400UL)
+#define USART3_BASE_NS                  (APB1PERIPH_BASE_NS + 0x4800UL)
+#define UART4_BASE_NS                   (APB1PERIPH_BASE_NS + 0x4C00UL)
+#define UART5_BASE_NS                   (APB1PERIPH_BASE_NS + 0x5000UL)
+#define I2C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5400UL)
+#define I2C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5800UL)
+#define I2C3_BASE_NS                    (APB1PERIPH_BASE_NS + 0x5C00UL)
+#define I3C1_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6000UL)
+#define I3C2_BASE_NS                    (APB1PERIPH_BASE_NS + 0x6400UL)
+#define UART7_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7800UL)
+#define UART8_BASE_NS                   (APB1PERIPH_BASE_NS + 0x7C00UL)
+#define MDIOS_BASE_NS                   (APB1PERIPH_BASE_NS + 0x9400UL)
+#define FDCAN1_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA000UL)
+#define FDCAN_CONFIG_BASE_NS            (APB1PERIPH_BASE_NS + 0xA100UL)
+#define FDCAN2_BASE_NS                  (APB1PERIPH_BASE_NS + 0xA400UL)
+#define FDCAN_CCU_BASE_NS               (APB1PERIPH_BASE_NS + 0xA800UL)
+#define SRAMCAN_BASE_NS                 (APB1PERIPH_BASE_NS + 0xC000UL)
+#define FDCAN3_BASE_NS                  (APB1PERIPH_BASE_NS + 0xE800UL)
+#define UCPD1_BASE_NS                   (APB1PERIPH_BASE_NS + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_NS                  (AHB1PERIPH_BASE_NS + 0x1000UL)
+#define GPDMA1_Channel0_BASE_NS         (GPDMA1_BASE_NS + 0x0050UL)
+#define GPDMA1_Channel1_BASE_NS         (GPDMA1_BASE_NS + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_NS         (GPDMA1_BASE_NS + 0x0150UL)
+#define GPDMA1_Channel3_BASE_NS         (GPDMA1_BASE_NS + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_NS         (GPDMA1_BASE_NS + 0x0250UL)
+#define GPDMA1_Channel5_BASE_NS         (GPDMA1_BASE_NS + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_NS         (GPDMA1_BASE_NS + 0x0350UL)
+#define GPDMA1_Channel7_BASE_NS         (GPDMA1_BASE_NS + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_NS         (GPDMA1_BASE_NS + 0x0450UL)
+#define GPDMA1_Channel9_BASE_NS         (GPDMA1_BASE_NS + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_NS        (GPDMA1_BASE_NS + 0x0550UL)
+#define GPDMA1_Channel11_BASE_NS        (GPDMA1_BASE_NS + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_NS        (GPDMA1_BASE_NS + 0x0650UL)
+#define GPDMA1_Channel13_BASE_NS        (GPDMA1_BASE_NS + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_NS        (GPDMA1_BASE_NS + 0x0750UL)
+#define GPDMA1_Channel15_BASE_NS        (GPDMA1_BASE_NS + 0x07D0UL)
+#define ADC1_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2000UL)
+#define ADC2_BASE_NS                    (AHB1PERIPH_BASE_NS + 0x2100UL)
+#define ADC12_COMMON_BASE_NS            (AHB1PERIPH_BASE_NS + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0000UL)
+#define TIM8_BASE_NS                    (APB2PERIPH_BASE_NS + 0x0400UL)
+#define USART1_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1000UL)
+#define USART6_BASE_NS                  (APB2PERIPH_BASE_NS + 0x1400UL)
+#define UART9_BASE_NS                   (APB2PERIPH_BASE_NS + 0x1800UL)
+#define USART10_BASE_NS                 (APB2PERIPH_BASE_NS + 0x1C00UL)
+#define SPI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3000UL)
+#define SPI4_BASE_NS                    (APB2PERIPH_BASE_NS + 0x3400UL)
+#define TIM18_BASE_NS                   (APB2PERIPH_BASE_NS + 0x3C00UL)
+#define TIM15_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4000UL)
+#define TIM16_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4400UL)
+#define TIM17_BASE_NS                   (APB2PERIPH_BASE_NS + 0x4800UL)
+#define TIM9_BASE_NS                    (APB2PERIPH_BASE_NS + 0x4C00UL)
+#define SPI5_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5000UL)
+#define SAI1_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5800UL)
+#define SAI1_Block_A_BASE_NS            (SAI1_BASE_NS + 0x0004UL)
+#define SAI1_Block_B_BASE_NS            (SAI1_BASE_NS + 0x0024UL)
+#define SAI2_BASE_NS                    (APB2PERIPH_BASE_NS + 0x5C00UL)
+#define SAI2_Block_A_BASE_NS            (SAI2_BASE_NS + 0x0004UL)
+#define SAI2_Block_B_BASE_NS            (SAI2_BASE_NS + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_NS                  (AHB2PERIPH_BASE_NS + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_NS        (RAMCFG_BASE_NS)
+#define RAMCFG_SRAM2_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_NS        (RAMCFG_BASE_NS + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_NS        (RAMCFG_BASE_NS + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_NS         (RAMCFG_BASE_NS + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_NS          (RAMCFG_BASE_NS + 0x0500UL)
+#define MDF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x5000UL)
+#define MDF1_Filter0_BASE_NS            (MDF1_BASE_NS + 0x0080UL)
+#define MDF1_Filter1_BASE_NS            (MDF1_BASE_NS + 0x0100UL)
+#define MDF1_Filter2_BASE_NS            (MDF1_BASE_NS + 0x0180UL)
+#define MDF1_Filter3_BASE_NS            (MDF1_BASE_NS + 0x0200UL)
+#define MDF1_Filter4_BASE_NS            (MDF1_BASE_NS + 0x0280UL)
+#define MDF1_Filter5_BASE_NS            (MDF1_BASE_NS + 0x0300UL)
+#define ADF1_BASE_NS                    (AHB2PERIPH_BASE_NS + 0x6000UL)
+#define ADF1_Filter0_BASE_NS            (ADF1_BASE_NS + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_NS                 (APB3PERIPH_BASE_NS + 0x0000UL)
+#define DBGMCU_BASE_NS                  (APB3PERIPH_BASE_NS + 0x1000UL)
+#define DFT_APB_BASE_NS                 (APB3PERIPH_BASE_NS + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x0000UL)
+#define HASH_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0400UL)
+#define HASH_DIGEST_BASE_NS             (AHB3PERIPH_BASE_NS + 0x0710UL)
+#define CRYP_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x0800UL)
+#define SAES_BASE_NS                    (AHB3PERIPH_BASE_NS + 0x1000UL)
+#define PKA_BASE_NS                     (AHB3PERIPH_BASE_NS + 0x2000UL)
+#define RIFSC_BASE_NS                   (AHB3PERIPH_BASE_NS + 0x4000UL)
+#define RISAF1_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x6000UL)
+#define RISAF2_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x7000UL)
+#define RISAF3_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x8000UL)
+#define RISAF4_BASE_NS                  (AHB3PERIPH_BASE_NS + 0x9000UL)
+#define RISAF5_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xA000UL)
+#define RISAF6_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xB000UL)
+#define RISAF7_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xC000UL)
+#define RISAF8_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xD000UL)
+#define RISAF9_BASE_NS                  (AHB3PERIPH_BASE_NS + 0xE000UL)
+#define RISAF11_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x010000UL)
+#define RISAF12_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x011000UL)
+#define RISAF13_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x012000UL)
+#define RISAF14_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x013000UL)
+#define RISAF15_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x014000UL)
+#define RISAF21_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x015000UL)
+#define RISAF22_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x016000UL)
+#define RISAF23_BASE_NS                 (AHB3PERIPH_BASE_NS + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_NS                     (APB4PERIPH_BASE_NS + 0x0800UL)
+#define LPUART1_BASE_NS                 (APB4PERIPH_BASE_NS + 0x0C00UL)
+#define SPI6_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1400UL)
+#define I2C4_BASE_NS                    (APB4PERIPH_BASE_NS + 0x1C00UL)
+#define LPTIM2_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2400UL)
+#define LPTIM3_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2800UL)
+#define LPTIM4_BASE_NS                  (APB4PERIPH_BASE_NS + 0x2C00UL)
+#define LPTIM5_BASE_NS                  (APB4PERIPH_BASE_NS + 0x3000UL)
+#define VREFBUF_BASE_NS                 (APB4PERIPH_BASE_NS + 0x3C00UL)
+#define RTC_BASE_NS                     (APB4PERIPH_BASE_NS + 0x4000UL)
+#define TAMP_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4400UL)
+#define IWDG_BASE_NS                    (APB4PERIPH_BASE_NS + 0x4800UL)
+#define SERC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x7C00UL)
+#define SYSCFG_BASE_NS                  (APB4PERIPH_BASE_NS + 0x8000UL)
+#define BSEC_BASE_NS                    (APB4PERIPH_BASE_NS + 0x9000UL)
+#define DTS_BASE_NS                     (APB4PERIPH_BASE_NS + 0xA000UL)
+#define DTS_Sensor0_BASE_NS             (DTS_BASE_NS + 0x0C0UL)
+#define DTS_Sensor1_BASE_NS             (DTS_BASE_NS + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0000UL)
+#define GPIOB_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0400UL)
+#define GPIOC_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0800UL)
+#define GPIOD_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x0C00UL)
+#define GPIOE_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1000UL)
+#define GPIOF_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1400UL)
+#define GPIOG_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1800UL)
+#define GPIOH_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x1C00UL)
+#define GPION_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3400UL)
+#define GPIOO_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3800UL)
+#define GPIOP_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x3C00UL)
+#define GPIOQ_BASE_NS                   (AHB4PERIPH_BASE_NS + 0x4000UL)
+#define PWR_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4800UL)
+#define CRC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x4C00UL)
+#define EXTI_BASE_NS                    (AHB4PERIPH_BASE_NS + 0x5000UL)
+#define RCC_BASE_NS                     (AHB4PERIPH_BASE_NS + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x1000UL)
+#define LTDC_Layer1_BASE_NS             (LTDC_BASE_NS + 0x0100UL)
+#define LTDC_Layer2_BASE_NS             (LTDC_BASE_NS + 0x0200UL)
+#define DCMIPP_BASE_NS                  (APB5PERIPH_BASE_NS + 0x2000UL)
+#define GFXTIM_BASE_NS                  (APB5PERIPH_BASE_NS + 0x4000UL)
+#define VENC_BASE_NS                    (APB5PERIPH_BASE_NS + 0x5000UL)
+#define CSI_BASE_NS                     (APB5PERIPH_BASE_NS + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x0000UL)
+#define HPDMA1_Channel0_BASE_NS         (HPDMA1_BASE_NS + 0x0050UL)
+#define HPDMA1_Channel1_BASE_NS         (HPDMA1_BASE_NS + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_NS         (HPDMA1_BASE_NS + 0x0150UL)
+#define HPDMA1_Channel3_BASE_NS         (HPDMA1_BASE_NS + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_NS         (HPDMA1_BASE_NS + 0x0250UL)
+#define HPDMA1_Channel5_BASE_NS         (HPDMA1_BASE_NS + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_NS         (HPDMA1_BASE_NS + 0x0350UL)
+#define HPDMA1_Channel7_BASE_NS         (HPDMA1_BASE_NS + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_NS         (HPDMA1_BASE_NS + 0x0450UL)
+#define HPDMA1_Channel9_BASE_NS         (HPDMA1_BASE_NS + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_NS        (HPDMA1_BASE_NS + 0x0550UL)
+#define HPDMA1_Channel11_BASE_NS        (HPDMA1_BASE_NS + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_NS        (HPDMA1_BASE_NS + 0x0650UL)
+#define HPDMA1_Channel13_BASE_NS        (HPDMA1_BASE_NS + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_NS        (HPDMA1_BASE_NS + 0x0750UL)
+#define HPDMA1_Channel15_BASE_NS        (HPDMA1_BASE_NS + 0x07D0UL)
+#define DMA2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x1000UL)
+#define JPEG_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x3000UL)
+#define FMC_R_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x4000UL)
+#define FMC_Bank1_R_BASE_NS             (FMC_R_BASE_NS + 0x0000UL)
+#define FMC_Bank1E_R_BASE_NS            (FMC_R_BASE_NS + 0x0104UL)
+#define FMC_Bank3_R_BASE_NS             (FMC_R_BASE_NS + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_NS           (FMC_R_BASE_NS + 0x0140UL)
+#define FMC_Common_R_BASE_NS            (FMC_R_BASE_NS + 0x0020UL)
+#define XSPI1_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x5000UL)
+#define PSSI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x6400UL)
+#define SDMMC2_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x6800UL)
+#define DLYB_SDMMC2_BASE_NS             (AHB5PERIPH_BASE_NS + 0x6C00UL)
+#define SDMMC1_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x7000UL)
+#define DLYB_SDMMC1_BASE_NS             (AHB5PERIPH_BASE_NS + 0x8000UL)
+#define DCMI_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x8400UL)
+#define XSPI2_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xA000UL)
+#define XSPIM_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xB400UL)
+#define MCE1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xB800UL)
+#define MCE1_REGION1_BASE_NS            (MCE1_BASE_NS + 0x040UL)
+#define MCE1_REGION2_BASE_NS            (MCE1_BASE_NS + 0x050UL)
+#define MCE1_REGION3_BASE_NS            (MCE1_BASE_NS + 0x060UL)
+#define MCE1_REGION4_BASE_NS            (MCE1_BASE_NS + 0x070UL)
+#define MCE1_CONTEXT1_BASE_NS           (MCE1_BASE_NS + 0x240UL)
+#define MCE1_CONTEXT2_BASE_NS           (MCE1_BASE_NS + 0x270UL)
+#define MCE2_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xBC00UL)
+#define MCE2_REGION1_BASE_NS            (MCE2_BASE_NS + 0x040UL)
+#define MCE2_REGION2_BASE_NS            (MCE2_BASE_NS + 0x050UL)
+#define MCE2_REGION3_BASE_NS            (MCE2_BASE_NS + 0x060UL)
+#define MCE2_REGION4_BASE_NS            (MCE2_BASE_NS + 0x070UL)
+#define MCE2_CONTEXT1_BASE_NS           (MCE2_BASE_NS + 0x240UL)
+#define MCE2_CONTEXT2_BASE_NS           (MCE2_BASE_NS + 0x270UL)
+#define MCE3_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xC000UL)
+#define MCE3_REGION1_BASE_NS            (MCE3_BASE_NS + 0x040UL)
+#define MCE3_REGION2_BASE_NS            (MCE3_BASE_NS + 0x050UL)
+#define MCE3_REGION3_BASE_NS            (MCE3_BASE_NS + 0x060UL)
+#define MCE3_REGION4_BASE_NS            (MCE3_BASE_NS + 0x070UL)
+#define MCE3_CONTEXT1_BASE_NS           (MCE3_BASE_NS + 0x240UL)
+#define MCE3_CONTEXT2_BASE_NS           (MCE3_BASE_NS + 0x270UL)
+#define MCE4_BASE_NS                    (AHB5PERIPH_BASE_NS + 0xE000UL)
+#define MCE4_REGION1_BASE_NS            (MCE4_BASE_NS + 0x040UL)
+#define MCE4_REGION2_BASE_NS            (MCE4_BASE_NS + 0x050UL)
+#define MCE4_REGION3_BASE_NS            (MCE4_BASE_NS + 0x060UL)
+#define MCE4_REGION4_BASE_NS            (MCE4_BASE_NS + 0x070UL)
+#define MCE4_CONTEXT1_BASE_NS           (MCE4_BASE_NS + 0x240UL)
+#define MCE4_CONTEXT2_BASE_NS           (MCE4_BASE_NS + 0x270UL)
+#define XSPI3_BASE_NS                   (AHB5PERIPH_BASE_NS + 0xD000UL)
+#define GFXMMU_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x010000UL)
+#define GPU2D_BASE_NS                   (AHB5PERIPH_BASE_NS + 0x014000UL)
+#define GPUCACHE_BASE_NS                (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ICACHE_BASE_NS                  (AHB5PERIPH_BASE_NS + 0x015000UL)
+#define ETH1_BASE_NS                    (AHB5PERIPH_BASE_NS + 0x016000UL)
+#define ETH1_MAC_BASE_NS                (ETH1_BASE_NS)
+#define USB1_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_NS            (AHB5PERIPH_BASE_NS + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x020000UL)
+#define USB2_OTG_HS_BASE_NS             (AHB5PERIPH_BASE_NS + 0x060000UL)
+#define CACHEAXI_BASE_NS                (AHB5PERIPH_BASE_NS + 0x0BFC00UL)
+#define NPU_BASE_NS                     (AHB5PERIPH_BASE_NS + 0x0C0000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_NS                     (0x46009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_NS                   (BOOTROM_BASE_NS + 0x0047ECUL)
+
+
+#if defined (CPU_IN_SECURE_STATE)
+/*********************************************************************/
+/*                                                                   */
+/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */
+/*                                                                   */
+/*********************************************************************/
+#define ITCM_BASE_S                     0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB               */
+#define BOOTROM_BASE_S                  0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI        */
+#define DTCM_BASE_S                     0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB              */
+#define SRAM1_AXI_BASE_S                0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
+#define SRAM2_AXI_BASE_S                0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI      */
+#define SRAM3_AXI_BASE_S                0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI      */
+#define SRAM4_AXI_BASE_S                0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
+#define SRAM5_AXI_BASE_S                0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
+#define SRAM6_AXI_BASE_S                0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
+#define SRAM_AXI_BASE_S                 SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
+#define CACHEAXI_RAM_BASE_S             0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI   */
+#define VENC_RAM_BASE_S                 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
+#define GFXMMU_VIRTUAL_BUFFER0_BASE_S   0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0               */
+#define GFXMMU_VIRTUAL_BUFFER1_BASE_S   0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1               */
+#define GFXMMU_VIRTUAL_BUFFER2_BASE_S   0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2               */
+#define GFXMMU_VIRTUAL_BUFFER3_BASE_S   0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3               */
+#define STM500_CHANNELS_BASE_S          0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace)     */
+#define SRAM1_AHB_BASE_S                0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge    */
+#define SRAM2_AHB_BASE_S                0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge    */
+#define SRAM_AHB_BASE_S                 SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge  */
+#define BKPSRAM_BASE_S                  0x3C000000UL   /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge    */
+#define PERIPH_BASE_S                   0x50000000UL   /*!< Base address of : AHB/APB Peripherals                    */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE_S               PERIPH_BASE_S
+#define AHB1PERIPH_BASE_S               (PERIPH_BASE_S + 0x00020000UL)
+#define APB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02000000UL)
+#define AHB2PERIPH_BASE_S               (PERIPH_BASE_S + 0x02020000UL)
+#define APB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04000000UL)
+#define AHB3PERIPH_BASE_S               (PERIPH_BASE_S + 0x04020000UL)
+#define APB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06000000UL)
+#define AHB4PERIPH_BASE_S               (PERIPH_BASE_S + 0x06020000UL)
+#define APB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08000000UL)
+#define AHB5PERIPH_BASE_S               (PERIPH_BASE_S + 0x08020000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE_S                     (APB1PERIPH_BASE_S + 0x0000UL)
+#define TIM3_BASE_S                     (APB1PERIPH_BASE_S + 0x0400UL)
+#define TIM4_BASE_S                     (APB1PERIPH_BASE_S + 0x0800UL)
+#define TIM5_BASE_S                     (APB1PERIPH_BASE_S + 0x0C00UL)
+#define TIM6_BASE_S                     (APB1PERIPH_BASE_S + 0x1000UL)
+#define TIM7_BASE_S                     (APB1PERIPH_BASE_S + 0x1400UL)
+#define TIM12_BASE_S                    (APB1PERIPH_BASE_S + 0x1800UL)
+#define TIM13_BASE_S                    (APB1PERIPH_BASE_S + 0x1C00UL)
+#define TIM14_BASE_S                    (APB1PERIPH_BASE_S + 0x2000UL)
+#define LPTIM1_BASE_S                   (APB1PERIPH_BASE_S + 0x2400UL)
+#define WWDG_BASE_S                     (APB1PERIPH_BASE_S + 0x2C00UL)
+#define TIM10_BASE_S                    (APB1PERIPH_BASE_S + 0x3000UL)
+#define TIM11_BASE_S                    (APB1PERIPH_BASE_S + 0x3400UL)
+#define SPI2_BASE_S                     (APB1PERIPH_BASE_S + 0x3800UL)
+#define SPI3_BASE_S                     (APB1PERIPH_BASE_S + 0x3C00UL)
+#define SPDIFRX_BASE_S                  (APB1PERIPH_BASE_S + 0x4000UL)
+#define USART2_BASE_S                   (APB1PERIPH_BASE_S + 0x4400UL)
+#define USART3_BASE_S                   (APB1PERIPH_BASE_S + 0x4800UL)
+#define UART4_BASE_S                    (APB1PERIPH_BASE_S + 0x4C00UL)
+#define UART5_BASE_S                    (APB1PERIPH_BASE_S + 0x5000UL)
+#define I2C1_BASE_S                     (APB1PERIPH_BASE_S + 0x5400UL)
+#define I2C2_BASE_S                     (APB1PERIPH_BASE_S + 0x5800UL)
+#define I2C3_BASE_S                     (APB1PERIPH_BASE_S + 0x5C00UL)
+#define I3C1_BASE_S                     (APB1PERIPH_BASE_S + 0x6000UL)
+#define I3C2_BASE_S                     (APB1PERIPH_BASE_S + 0x6400UL)
+#define UART7_BASE_S                    (APB1PERIPH_BASE_S + 0x7800UL)
+#define UART8_BASE_S                    (APB1PERIPH_BASE_S + 0x7C00UL)
+#define MDIOS_BASE_S                    (APB1PERIPH_BASE_S + 0x9400UL)
+#define FDCAN1_BASE_S                   (APB1PERIPH_BASE_S + 0xA000UL)
+#define FDCAN_CONFIG_BASE_S             (APB1PERIPH_BASE_S + 0xA100UL)
+#define FDCAN2_BASE_S                   (APB1PERIPH_BASE_S + 0xA400UL)
+#define FDCAN_CCU_BASE_S                (APB1PERIPH_BASE_S + 0xA800UL)
+#define SRAMCAN_BASE_S                  (APB1PERIPH_BASE_S + 0xC000UL)
+#define FDCAN3_BASE_S                   (APB1PERIPH_BASE_S + 0xE800UL)
+#define UCPD1_BASE_S                    (APB1PERIPH_BASE_S + 0xFC00UL)
+
+/*!< AHB1 peripherals */
+#define GPDMA1_BASE_S                   (AHB1PERIPH_BASE_S + 0x1000UL)
+#define GPDMA1_Channel0_BASE_S          (GPDMA1_BASE_S + 0x0050UL)
+#define GPDMA1_Channel1_BASE_S          (GPDMA1_BASE_S + 0x00D0UL)
+#define GPDMA1_Channel2_BASE_S          (GPDMA1_BASE_S + 0x0150UL)
+#define GPDMA1_Channel3_BASE_S          (GPDMA1_BASE_S + 0x01D0UL)
+#define GPDMA1_Channel4_BASE_S          (GPDMA1_BASE_S + 0x0250UL)
+#define GPDMA1_Channel5_BASE_S          (GPDMA1_BASE_S + 0x02D0UL)
+#define GPDMA1_Channel6_BASE_S          (GPDMA1_BASE_S + 0x0350UL)
+#define GPDMA1_Channel7_BASE_S          (GPDMA1_BASE_S + 0x03D0UL)
+#define GPDMA1_Channel8_BASE_S          (GPDMA1_BASE_S + 0x0450UL)
+#define GPDMA1_Channel9_BASE_S          (GPDMA1_BASE_S + 0x04D0UL)
+#define GPDMA1_Channel10_BASE_S         (GPDMA1_BASE_S + 0x0550UL)
+#define GPDMA1_Channel11_BASE_S         (GPDMA1_BASE_S + 0x05D0UL)
+#define GPDMA1_Channel12_BASE_S         (GPDMA1_BASE_S + 0x0650UL)
+#define GPDMA1_Channel13_BASE_S         (GPDMA1_BASE_S + 0x06D0UL)
+#define GPDMA1_Channel14_BASE_S         (GPDMA1_BASE_S + 0x0750UL)
+#define GPDMA1_Channel15_BASE_S         (GPDMA1_BASE_S + 0x07D0UL)
+#define ADC1_BASE_S                     (AHB1PERIPH_BASE_S + 0x2000UL)
+#define ADC2_BASE_S                     (AHB1PERIPH_BASE_S + 0x2100UL)
+#define ADC12_COMMON_BASE_S             (AHB1PERIPH_BASE_S + 0x2300UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE_S                     (APB2PERIPH_BASE_S + 0x0000UL)
+#define TIM8_BASE_S                     (APB2PERIPH_BASE_S + 0x0400UL)
+#define USART1_BASE_S                   (APB2PERIPH_BASE_S + 0x1000UL)
+#define USART6_BASE_S                   (APB2PERIPH_BASE_S + 0x1400UL)
+#define UART9_BASE_S                    (APB2PERIPH_BASE_S + 0x1800UL)
+#define USART10_BASE_S                  (APB2PERIPH_BASE_S + 0x1C00UL)
+#define SPI1_BASE_S                     (APB2PERIPH_BASE_S + 0x3000UL)
+#define SPI4_BASE_S                     (APB2PERIPH_BASE_S + 0x3400UL)
+#define TIM18_BASE_S                    (APB2PERIPH_BASE_S + 0x3C00UL)
+#define TIM15_BASE_S                    (APB2PERIPH_BASE_S + 0x4000UL)
+#define TIM16_BASE_S                    (APB2PERIPH_BASE_S + 0x4400UL)
+#define TIM17_BASE_S                    (APB2PERIPH_BASE_S + 0x4800UL)
+#define TIM9_BASE_S                     (APB2PERIPH_BASE_S + 0x4C00UL)
+#define SPI5_BASE_S                     (APB2PERIPH_BASE_S + 0x5000UL)
+#define SAI1_BASE_S                     (APB2PERIPH_BASE_S + 0x5800UL)
+#define SAI1_Block_A_BASE_S             (SAI1_BASE_S + 0x0004UL)
+#define SAI1_Block_B_BASE_S             (SAI1_BASE_S + 0x0024UL)
+#define SAI2_BASE_S                     (APB2PERIPH_BASE_S + 0x5C00UL)
+#define SAI2_Block_A_BASE_S             (SAI2_BASE_S + 0x0004UL)
+#define SAI2_Block_B_BASE_S             (SAI2_BASE_S + 0x0024UL)
+
+/*!< AHB2 peripherals */
+#define RAMCFG_BASE_S                   (AHB2PERIPH_BASE_S + 0x3000UL)
+#define RAMCFG_SRAM1_AXI_BASE_S         (RAMCFG_BASE_S)
+#define RAMCFG_SRAM2_AXI_BASE_S         (RAMCFG_BASE_S + 0x0080UL)
+#define RAMCFG_SRAM3_AXI_BASE_S         (RAMCFG_BASE_S + 0x0100UL)
+#define RAMCFG_SRAM4_AXI_BASE_S         (RAMCFG_BASE_S + 0x0180UL)
+#define RAMCFG_SRAM5_AXI_BASE_S         (RAMCFG_BASE_S + 0x0200UL)
+#define RAMCFG_SRAM6_AXI_BASE_S         (RAMCFG_BASE_S + 0x0280UL)
+#define RAMCFG_SRAM1_AHB_BASE_S         (RAMCFG_BASE_S + 0x0300UL)
+#define RAMCFG_SRAM2_AHB_BASE_S         (RAMCFG_BASE_S + 0x0380UL)
+#define RAMCFG_VENC_RAM_BASE_S          (RAMCFG_BASE_S + 0x0400UL)
+#define RAMCFG_BKPSRAM_BASE_S           (RAMCFG_BASE_S + 0x0480UL)
+#define RAMCFG_FLEXRAM_BASE_S           (RAMCFG_BASE_S + 0x0500UL)
+#define MDF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x5000UL)
+#define MDF1_Filter0_BASE_S             (MDF1_BASE_S + 0x0080UL)
+#define MDF1_Filter1_BASE_S             (MDF1_BASE_S + 0x0100UL)
+#define MDF1_Filter2_BASE_S             (MDF1_BASE_S + 0x0180UL)
+#define MDF1_Filter3_BASE_S             (MDF1_BASE_S + 0x0200UL)
+#define MDF1_Filter4_BASE_S             (MDF1_BASE_S + 0x0280UL)
+#define MDF1_Filter5_BASE_S             (MDF1_BASE_S + 0x0300UL)
+#define ADF1_BASE_S                     (AHB2PERIPH_BASE_S + 0x6000UL)
+#define ADF1_Filter0_BASE_S             (ADF1_BASE_S + 0x0080UL)
+
+/*!< APB3 peripherals */
+#define DAP_ROM_BASE_S                  (APB3PERIPH_BASE_S + 0x0000UL)
+#define DBGMCU_BASE_S                   (APB3PERIPH_BASE_S + 0x1000UL)
+#define DFT_APB_BASE_S                  (APB3PERIPH_BASE_S + 0x2000UL)
+
+/*!< AHB3 peripherals */
+#define RNG_BASE_S                      (AHB3PERIPH_BASE_S + 0x0000UL)
+#define HASH_BASE_S                     (AHB3PERIPH_BASE_S + 0x0400UL)
+#define HASH_DIGEST_BASE_S              (AHB3PERIPH_BASE_S + 0x0710UL)
+#define CRYP_BASE_S                     (AHB3PERIPH_BASE_S + 0x0800UL)
+#define SAES_BASE_S                     (AHB3PERIPH_BASE_S + 0x1000UL)
+#define PKA_BASE_S                      (AHB3PERIPH_BASE_S + 0x2000UL)
+#define RIFSC_BASE_S                    (AHB3PERIPH_BASE_S + 0x4000UL)
+#define IAC_BASE_S                      (AHB3PERIPH_BASE_S + 0x5000UL)
+#define RISAF1_BASE_S                   (AHB3PERIPH_BASE_S + 0x6000UL)
+#define RISAF2_BASE_S                   (AHB3PERIPH_BASE_S + 0x7000UL)
+#define RISAF3_BASE_S                   (AHB3PERIPH_BASE_S + 0x8000UL)
+#define RISAF4_BASE_S                   (AHB3PERIPH_BASE_S + 0x9000UL)
+#define RISAF5_BASE_S                   (AHB3PERIPH_BASE_S + 0xA000UL)
+#define RISAF6_BASE_S                   (AHB3PERIPH_BASE_S + 0xB000UL)
+#define RISAF7_BASE_S                   (AHB3PERIPH_BASE_S + 0xC000UL)
+#define RISAF8_BASE_S                   (AHB3PERIPH_BASE_S + 0xD000UL)
+#define RISAF9_BASE_S                   (AHB3PERIPH_BASE_S + 0xE000UL)
+#define RISAF11_BASE_S                  (AHB3PERIPH_BASE_S + 0x010000UL)
+#define RISAF12_BASE_S                  (AHB3PERIPH_BASE_S + 0x011000UL)
+#define RISAF13_BASE_S                  (AHB3PERIPH_BASE_S + 0x012000UL)
+#define RISAF14_BASE_S                  (AHB3PERIPH_BASE_S + 0x013000UL)
+#define RISAF15_BASE_S                  (AHB3PERIPH_BASE_S + 0x014000UL)
+#define RISAF21_BASE_S                  (AHB3PERIPH_BASE_S + 0x015000UL)
+#define RISAF22_BASE_S                  (AHB3PERIPH_BASE_S + 0x016000UL)
+#define RISAF23_BASE_S                  (AHB3PERIPH_BASE_S + 0x017000UL)
+
+/*!< APB4 peripherals */
+#define HDP_BASE_S                      (APB4PERIPH_BASE_S + 0x0800UL)
+#define LPUART1_BASE_S                  (APB4PERIPH_BASE_S + 0x0C00UL)
+#define SPI6_BASE_S                     (APB4PERIPH_BASE_S + 0x1400UL)
+#define I2C4_BASE_S                     (APB4PERIPH_BASE_S + 0x1C00UL)
+#define LPTIM2_BASE_S                   (APB4PERIPH_BASE_S + 0x2400UL)
+#define LPTIM3_BASE_S                   (APB4PERIPH_BASE_S + 0x2800UL)
+#define LPTIM4_BASE_S                   (APB4PERIPH_BASE_S + 0x2C00UL)
+#define LPTIM5_BASE_S                   (APB4PERIPH_BASE_S + 0x3000UL)
+#define VREFBUF_BASE_S                  (APB4PERIPH_BASE_S + 0x3C00UL)
+#define RTC_BASE_S                      (APB4PERIPH_BASE_S + 0x4000UL)
+#define TAMP_BASE_S                     (APB4PERIPH_BASE_S + 0x4400UL)
+#define IWDG_BASE_S                     (APB4PERIPH_BASE_S + 0x4800UL)
+
+#define SERC_BASE_S                     (APB4PERIPH_BASE_S + 0x7C00UL)
+#define SYSCFG_BASE_S                   (APB4PERIPH_BASE_S + 0x8000UL)
+#define BSEC_BASE_S                     (APB4PERIPH_BASE_S + 0x9000UL)
+#define DTS_BASE_S                      (APB4PERIPH_BASE_S + 0xA000UL)
+#define DTS_Sensor0_BASE_S              (DTS_BASE_S + 0x0C0UL)
+#define DTS_Sensor1_BASE_S              (DTS_BASE_S + 0x100UL)
+
+/*!< AHB4 peripherals */
+#define GPIOA_BASE_S                    (AHB4PERIPH_BASE_S + 0x0000UL)
+#define GPIOB_BASE_S                    (AHB4PERIPH_BASE_S + 0x0400UL)
+#define GPIOC_BASE_S                    (AHB4PERIPH_BASE_S + 0x0800UL)
+#define GPIOD_BASE_S                    (AHB4PERIPH_BASE_S + 0x0C00UL)
+#define GPIOE_BASE_S                    (AHB4PERIPH_BASE_S + 0x1000UL)
+#define GPIOF_BASE_S                    (AHB4PERIPH_BASE_S + 0x1400UL)
+#define GPIOG_BASE_S                    (AHB4PERIPH_BASE_S + 0x1800UL)
+#define GPIOH_BASE_S                    (AHB4PERIPH_BASE_S + 0x1C00UL)
+#define GPION_BASE_S                    (AHB4PERIPH_BASE_S + 0x3400UL)
+#define GPIOO_BASE_S                    (AHB4PERIPH_BASE_S + 0x3800UL)
+#define GPIOP_BASE_S                    (AHB4PERIPH_BASE_S + 0x3C00UL)
+#define GPIOQ_BASE_S                    (AHB4PERIPH_BASE_S + 0x4000UL)
+#define PWR_BASE_S                      (AHB4PERIPH_BASE_S + 0x4800UL)
+#define CRC_BASE_S                      (AHB4PERIPH_BASE_S + 0x4C00UL)
+#define EXTI_BASE_S                     (AHB4PERIPH_BASE_S + 0x5000UL)
+#define RCC_BASE_S                      (AHB4PERIPH_BASE_S + 0x8000UL)
+
+/*!< APB5 peripherals */
+#define LTDC_BASE_S                     (APB5PERIPH_BASE_S + 0x1000UL)
+#define LTDC_Layer1_BASE_S              (LTDC_BASE_S + 0x0100UL)
+#define LTDC_Layer2_BASE_S              (LTDC_BASE_S + 0x0200UL)
+#define DCMIPP_BASE_S                   (APB5PERIPH_BASE_S + 0x2000UL)
+#define GFXTIM_BASE_S                   (APB5PERIPH_BASE_S + 0x4000UL)
+#define VENC_BASE_S                     (APB5PERIPH_BASE_S + 0x5000UL)
+#define CSI_BASE_S                      (APB5PERIPH_BASE_S + 0x6000UL)
+
+/*!< AHB5 peripherals */
+#define HPDMA1_BASE_S                   (AHB5PERIPH_BASE_S + 0x0000UL)
+#define HPDMA1_Channel0_BASE_S          (HPDMA1_BASE_S + 0x0050UL)
+#define HPDMA1_Channel1_BASE_S          (HPDMA1_BASE_S + 0x00D0UL)
+#define HPDMA1_Channel2_BASE_S          (HPDMA1_BASE_S + 0x0150UL)
+#define HPDMA1_Channel3_BASE_S          (HPDMA1_BASE_S + 0x01D0UL)
+#define HPDMA1_Channel4_BASE_S          (HPDMA1_BASE_S + 0x0250UL)
+#define HPDMA1_Channel5_BASE_S          (HPDMA1_BASE_S + 0x02D0UL)
+#define HPDMA1_Channel6_BASE_S          (HPDMA1_BASE_S + 0x0350UL)
+#define HPDMA1_Channel7_BASE_S          (HPDMA1_BASE_S + 0x03D0UL)
+#define HPDMA1_Channel8_BASE_S          (HPDMA1_BASE_S + 0x0450UL)
+#define HPDMA1_Channel9_BASE_S          (HPDMA1_BASE_S + 0x04D0UL)
+#define HPDMA1_Channel10_BASE_S         (HPDMA1_BASE_S + 0x0550UL)
+#define HPDMA1_Channel11_BASE_S         (HPDMA1_BASE_S + 0x05D0UL)
+#define HPDMA1_Channel12_BASE_S         (HPDMA1_BASE_S + 0x0650UL)
+#define HPDMA1_Channel13_BASE_S         (HPDMA1_BASE_S + 0x06D0UL)
+#define HPDMA1_Channel14_BASE_S         (HPDMA1_BASE_S + 0x0750UL)
+#define HPDMA1_Channel15_BASE_S         (HPDMA1_BASE_S + 0x07D0UL)
+#define DMA2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x1000UL)
+#define JPEG_BASE_S                     (AHB5PERIPH_BASE_S + 0x3000UL)
+#define FMC_R_BASE_S                    (AHB5PERIPH_BASE_S + 0x4000UL)
+#define FMC_Bank1_R_BASE_S              (FMC_R_BASE_S + 0x0000UL)
+#define FMC_Bank1E_R_BASE_S             (FMC_R_BASE_S + 0x0104UL)
+#define FMC_Bank3_R_BASE_S              (FMC_R_BASE_S + 0x0080UL)
+#define FMC_Bank5_6_R_BASE_S            (FMC_R_BASE_S + 0x0140UL)
+#define FMC_Common_R_BASE_S             (FMC_R_BASE_S + 0x0020UL)
+#define XSPI1_BASE_S                    (AHB5PERIPH_BASE_S + 0x5000UL)
+#define PSSI_BASE_S                     (AHB5PERIPH_BASE_S + 0x6400UL)
+#define SDMMC2_BASE_S                   (AHB5PERIPH_BASE_S + 0x6800UL)
+#define DLYB_SDMMC2_BASE_S              (AHB5PERIPH_BASE_S + 0x6C00UL)
+#define SDMMC1_BASE_S                   (AHB5PERIPH_BASE_S + 0x7000UL)
+#define DLYB_SDMMC1_BASE_S              (AHB5PERIPH_BASE_S + 0x8000UL)
+#define DCMI_BASE_S                     (AHB5PERIPH_BASE_S + 0x8400UL)
+#define XSPI2_BASE_S                    (AHB5PERIPH_BASE_S + 0xA000UL)
+#define XSPIM_BASE_S                    (AHB5PERIPH_BASE_S + 0xB400UL)
+#define MCE1_BASE_S                     (AHB5PERIPH_BASE_S + 0xB800UL)
+#define MCE1_REGION1_BASE_S             (MCE1_BASE_S + 0x040UL)
+#define MCE1_REGION2_BASE_S             (MCE1_BASE_S + 0x050UL)
+#define MCE1_REGION3_BASE_S             (MCE1_BASE_S + 0x060UL)
+#define MCE1_REGION4_BASE_S             (MCE1_BASE_S + 0x070UL)
+#define MCE1_CONTEXT1_BASE_S            (MCE1_BASE_S + 0x240UL)
+#define MCE1_CONTEXT2_BASE_S            (MCE1_BASE_S + 0x270UL)
+#define MCE2_BASE_S                     (AHB5PERIPH_BASE_S + 0xBC00UL)
+#define MCE2_REGION1_BASE_S             (MCE2_BASE_S + 0x040UL)
+#define MCE2_REGION2_BASE_S             (MCE2_BASE_S + 0x050UL)
+#define MCE2_REGION3_BASE_S             (MCE2_BASE_S + 0x060UL)
+#define MCE2_REGION4_BASE_S             (MCE2_BASE_S + 0x070UL)
+#define MCE2_CONTEXT1_BASE_S            (MCE2_BASE_S + 0x240UL)
+#define MCE2_CONTEXT2_BASE_S            (MCE2_BASE_S + 0x270UL)
+#define MCE3_BASE_S                     (AHB5PERIPH_BASE_S + 0xC000UL)
+#define MCE3_REGION1_BASE_S             (MCE3_BASE_S + 0x040UL)
+#define MCE3_REGION2_BASE_S             (MCE3_BASE_S + 0x050UL)
+#define MCE3_REGION3_BASE_S             (MCE3_BASE_S + 0x060UL)
+#define MCE3_REGION4_BASE_S             (MCE3_BASE_S + 0x070UL)
+#define MCE3_CONTEXT1_BASE_S            (MCE3_BASE_S + 0x240UL)
+#define MCE3_CONTEXT2_BASE_S            (MCE3_BASE_S + 0x270UL)
+#define MCE4_BASE_S                     (AHB5PERIPH_BASE_S + 0xE000UL)
+#define MCE4_REGION1_BASE_S             (MCE4_BASE_S + 0x040UL)
+#define MCE4_REGION2_BASE_S             (MCE4_BASE_S + 0x050UL)
+#define MCE4_REGION3_BASE_S             (MCE4_BASE_S + 0x060UL)
+#define MCE4_REGION4_BASE_S             (MCE4_BASE_S + 0x070UL)
+#define MCE4_CONTEXT1_BASE_S            (MCE4_BASE_S + 0x240UL)
+#define MCE4_CONTEXT2_BASE_S            (MCE4_BASE_S + 0x270UL)
+#define XSPI3_BASE_S                    (AHB5PERIPH_BASE_S + 0xD000UL)
+#define GFXMMU_BASE_S                   (AHB5PERIPH_BASE_S + 0x010000UL)
+#define GPU2D_BASE_S                    (AHB5PERIPH_BASE_S + 0x014000UL)
+#define GPUCACHE_BASE_S                 (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ICACHE_BASE_S                   (AHB5PERIPH_BASE_S + 0x015000UL)
+#define ETH1_BASE_S                     (AHB5PERIPH_BASE_S + 0x016000UL)
+#define ETH1_MAC_BASE_S                 (ETH1_BASE_S)
+#define USB1_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x01FC00UL)
+#define USB2_HS_PHYC_BASE_S             (AHB5PERIPH_BASE_S + 0x0A0000UL)
+#define USB1_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x020000UL)
+#define USB2_OTG_HS_BASE_S              (AHB5PERIPH_BASE_S + 0x060000UL)
+#define CACHEAXI_BASE_S                 (AHB5PERIPH_BASE_S + 0x0BFC00UL)
+#define NPU_BASE_S                      (AHB5PERIPH_BASE_S + 0x0C0000UL)
+
+
+/*!< Unique device ID register base address */
+#define UID_BASE_S                      (0x56009014UL)
+
+/*!< Revision ID base address */
+#define REVID_BASE_S                    (BOOTROM_BASE_S + 0x0047ECUL)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+/** @addtogroup STM32N6xx_Peripheral_declaration
+  * @{
+  */
+#define ADC12_COMMON_NS           ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
+#define ADC1_NS                   ((ADC_TypeDef *) ADC1_BASE_NS)
+#define ADC2_NS                   ((ADC_TypeDef *) ADC2_BASE_NS)
+#define ADF1_NS                   ((MDF_TypeDef *) ADF1_BASE_NS)
+#define ADF1_Filter0_NS           ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS)
+#define BSEC_NS                   ((BSEC_TypeDef *) BSEC_BASE_NS)
+#define CACHEAXI_NS               ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS)
+#define CRC_NS                    ((CRC_TypeDef *) CRC_BASE_NS)
+#define CRYP_NS                   ((CRYP_TypeDef *) CRYP_BASE_NS)
+#define CSI_NS                    ((CSI_TypeDef *) CSI_BASE_NS)
+#define DBGMCU_NS                 ((DBGMCU_TypeDef *) DBGMCU_BASE_NS)
+#define DCMI_NS                   ((DCMI_TypeDef *) DCMI_BASE_NS)
+#define DCMIPP_NS                 ((DCMIPP_TypeDef *) DCMIPP_BASE_NS)
+#define DLYB_SDMMC1_NS            ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
+#define DLYB_SDMMC2_NS            ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
+#define DMA2D_NS                  ((DMA2D_TypeDef *) DMA2D_BASE_NS)
+#define DTS_NS                    ((DTS_TypeDef *) DTS_BASE_NS)
+#define DTS_Sensor0_NS            ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS)
+#define DTS_Sensor1_NS            ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS)
+#define ETH1_NS                   ((ETH_TypeDef *) ETH1_BASE_NS)
+#define EXTI_NS                   ((EXTI_TypeDef *) EXTI_BASE_NS)
+#define FDCAN1_NS                 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
+#define FDCAN2_NS                 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS)
+#define FDCAN3_NS                 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS)
+#define FDCAN_CCU_NS              ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS)
+#define FDCAN_CONFIG_NS           ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
+#define FMC_Bank1E_R_NS           ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
+#define FMC_Bank1_R_NS            ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
+#define FMC_Bank3_R_NS            ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
+#define FMC_Bank5_6_R_NS          ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS)
+#define FMC_Common_R_NS           ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS)
+#define GFXMMU_NS                 ((GFXMMU_TypeDef *) GFXMMU_BASE_NS)
+#define GFXTIM_NS                 ((GFXTIM_TypeDef *) GFXTIM_BASE_NS)
+#define GPDMA1_NS                 ((DMA_TypeDef *) GPDMA1_BASE_NS)
+#define GPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
+#define GPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
+#define GPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
+#define GPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
+#define GPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
+#define GPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
+#define GPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
+#define GPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
+#define GPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
+#define GPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
+#define GPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
+#define GPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
+#define GPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
+#define GPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
+#define GPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
+#define GPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
+#define GPIOA_NS                  ((GPIO_TypeDef *) GPIOA_BASE_NS)
+#define GPIOB_NS                  ((GPIO_TypeDef *) GPIOB_BASE_NS)
+#define GPIOC_NS                  ((GPIO_TypeDef *) GPIOC_BASE_NS)
+#define GPIOD_NS                  ((GPIO_TypeDef *) GPIOD_BASE_NS)
+#define GPIOE_NS                  ((GPIO_TypeDef *) GPIOE_BASE_NS)
+#define GPIOF_NS                  ((GPIO_TypeDef *) GPIOF_BASE_NS)
+#define GPIOG_NS                  ((GPIO_TypeDef *) GPIOG_BASE_NS)
+#define GPIOH_NS                  ((GPIO_TypeDef *) GPIOH_BASE_NS)
+#define GPION_NS                  ((GPIO_TypeDef *) GPION_BASE_NS)
+#define GPIOO_NS                  ((GPIO_TypeDef *) GPIOO_BASE_NS)
+#define GPIOP_NS                  ((GPIO_TypeDef *) GPIOP_BASE_NS)
+#define GPIOQ_NS                  ((GPIO_TypeDef *) GPIOQ_BASE_NS)
+#define HASH_NS                   ((HASH_TypeDef *) HASH_BASE_NS)
+#define HASH_DIGEST_NS            ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
+#define HPDMA1_NS                 ((DMA_TypeDef *) HPDMA1_BASE_NS)
+#define HPDMA1_Channel0_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS)
+#define HPDMA1_Channel1_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS)
+#define HPDMA1_Channel2_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS)
+#define HPDMA1_Channel3_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS)
+#define HPDMA1_Channel4_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS)
+#define HPDMA1_Channel5_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS)
+#define HPDMA1_Channel6_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS)
+#define HPDMA1_Channel7_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS)
+#define HPDMA1_Channel8_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS)
+#define HPDMA1_Channel9_NS        ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS)
+#define HPDMA1_Channel10_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS)
+#define HPDMA1_Channel11_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS)
+#define HPDMA1_Channel12_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS)
+#define HPDMA1_Channel13_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS)
+#define HPDMA1_Channel14_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS)
+#define HPDMA1_Channel15_NS       ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS)
+#define I2C1_NS                   ((I2C_TypeDef *) I2C1_BASE_NS)
+#define I2C2_NS                   ((I2C_TypeDef *) I2C2_BASE_NS)
+#define I2C3_NS                   ((I2C_TypeDef *) I2C3_BASE_NS)
+#define I2C4_NS                   ((I2C_TypeDef *) I2C4_BASE_NS)
+#define I3C1_NS                   ((I3C_TypeDef *) I3C1_BASE_NS)
+#define I3C2_NS                   ((I3C_TypeDef *) I3C2_BASE_NS)
+#define ICACHE_NS                 ((ICACHE_TypeDef *) ICACHE_BASE_NS)
+#define IWDG_NS                   ((IWDG_TypeDef *) IWDG_BASE_NS)
+#define JPEG_NS                   ((JPEG_TypeDef *) JPEG_BASE_NS)
+#define LPTIM1_NS                 ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
+#define LPTIM2_NS                 ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
+#define LPTIM3_NS                 ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
+#define LPTIM4_NS                 ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
+#define LPTIM5_NS                 ((LPTIM_TypeDef *) LPTIM5_BASE_NS)
+#define LPUART1_NS                ((USART_TypeDef *) LPUART1_BASE_NS)
+#define LTDC_NS                   ((LTDC_TypeDef *)LTDC_BASE_NS)
+#define LTDC_Layer1_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS)
+#define LTDC_Layer2_NS            ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS)
+#define MCE1_NS                   ((MCE_TypeDef *) MCE1_BASE_NS)
+#define MCE1_REGION1_NS           ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS)
+#define MCE1_REGION2_NS           ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS)
+#define MCE1_REGION3_NS           ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS)
+#define MCE1_REGION4_NS           ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS)
+#define MCE1_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS)
+#define MCE1_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS)
+#define MCE2_NS                   ((MCE_TypeDef *) MCE2_BASE_NS)
+#define MCE2_REGION1_NS           ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS)
+#define MCE2_REGION2_NS           ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS)
+#define MCE2_REGION3_NS           ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS)
+#define MCE2_REGION4_NS           ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS)
+#define MCE2_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS)
+#define MCE2_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS)
+#define MCE3_NS                   ((MCE_TypeDef *) MCE3_BASE_NS)
+#define MCE3_REGION1_NS           ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS)
+#define MCE3_REGION2_NS           ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS)
+#define MCE3_REGION3_NS           ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS)
+#define MCE3_REGION4_NS           ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS)
+#define MCE3_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS)
+#define MCE3_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS)
+#define MCE4_NS                   ((MCE_TypeDef *) MCE4_BASE_NS)
+#define MCE4_REGION1_NS           ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS)
+#define MCE4_REGION2_NS           ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS)
+#define MCE4_REGION3_NS           ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS)
+#define MCE4_REGION4_NS           ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS)
+#define MCE4_CONTEXT1_NS          ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS)
+#define MCE4_CONTEXT2_NS          ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS)
+#define MDF1_NS                   ((MDF_TypeDef *) MDF1_BASE_NS)
+#define MDF1_Filter0_NS           ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS)
+#define MDF1_Filter1_NS           ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS)
+#define MDF1_Filter2_NS           ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS)
+#define MDF1_Filter3_NS           ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS)
+#define MDF1_Filter4_NS           ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS)
+#define MDF1_Filter5_NS           ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS)
+#define MDIOS_NS                  ((MDIOS_TypeDef *) MDIOS_BASE_NS)
+#define PKA_NS                    ((PKA_TypeDef *) PKA_BASE_NS)
+#define PSSI_NS                   ((PSSI_TypeDef *) PSSI_BASE_NS)
+#define PWR_NS                    ((PWR_TypeDef *) PWR_BASE_NS)
+#define RAMCFG_NS                 ((RAMCFG_TypeDef *) RAMCFG_BASE_NS)
+#define RAMCFG_SRAM1_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS)
+#define RAMCFG_SRAM2_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS)
+#define RAMCFG_SRAM3_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS)
+#define RAMCFG_SRAM4_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS)
+#define RAMCFG_SRAM5_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS)
+#define RAMCFG_SRAM6_AXI_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS)
+#define RAMCFG_SRAM1_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS)
+#define RAMCFG_SRAM2_AHB_NS       ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS)
+#define RAMCFG_VENC_RAM_NS        ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS)
+#define RAMCFG_FLEXRAM_NS         ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS)
+#define RCC_NS                    ((RCC_TypeDef *) RCC_BASE_NS)
+#define RIFSC_NS                  ((RIFSC_TypeDef *) RIFSC_BASE_NS)
+#define RISAF1_NS                 ((RISAF_TypeDef *) RISAF1_BASE_NS)
+#define RISAF2_NS                 ((RISAF_TypeDef *) RISAF2_BASE_NS)
+#define RISAF3_NS                 ((RISAF_TypeDef *) RISAF3_BASE_NS)
+#define RISAF4_NS                 ((RISAF_TypeDef *) RISAF4_BASE_NS)
+#define RISAF5_NS                 ((RISAF_TypeDef *) RISAF5_BASE_NS)
+#define RISAF6_NS                 ((RISAF_TypeDef *) RISAF6_BASE_NS)
+#define RISAF7_NS                 ((RISAF_TypeDef *) RISAF7_BASE_NS)
+#define RISAF8_NS                 ((RISAF_TypeDef *) RISAF8_BASE_NS)
+#define RISAF9_NS                 ((RISAF_TypeDef *) RISAF9_BASE_NS)
+#define RISAF11_NS                ((RISAF_TypeDef *) RISAF11_BASE_NS)
+#define RISAF12_NS                ((RISAF_TypeDef *) RISAF12_BASE_NS)
+#define RISAF13_NS                ((RISAF_TypeDef *) RISAF13_BASE_NS)
+#define RISAF14_NS                ((RISAF_TypeDef *) RISAF14_BASE_NS)
+#define RISAF15_NS                ((RISAF_TypeDef *) RISAF15_BASE_NS)
+#define RISAF21_NS                ((RISAF_TypeDef *) RISAF21_BASE_NS)
+#define RISAF22_NS                ((RISAF_TypeDef *) RISAF22_BASE_NS)
+#define RISAF23_NS                ((RISAF_TypeDef *) RISAF23_BASE_NS)
+#define RNG_NS                    ((RNG_TypeDef *) RNG_BASE_NS)
+#define RTC_NS                    ((RTC_TypeDef *) RTC_BASE_NS)
+#define SAES_NS                   ((SAES_TypeDef *) SAES_BASE_NS)
+#define SAI1_NS                   ((SAI_TypeDef *) SAI1_BASE_NS)
+#define SAI1_Block_A_NS           ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS)
+#define SAI1_Block_B_NS           ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS)
+#define SAI2_NS                   ((SAI_TypeDef *) SAI2_BASE_NS)
+#define SAI2_Block_A_NS           ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS)
+#define SAI2_Block_B_NS           ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS)
+#define SDMMC1_NS                 ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
+#define SDMMC2_NS                 ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
+#define SPDIFRX_NS                ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS)
+#define SPI1_NS                   ((SPI_TypeDef *) SPI1_BASE_NS)
+#define SPI2_NS                   ((SPI_TypeDef *) SPI2_BASE_NS)
+#define SPI3_NS                   ((SPI_TypeDef *) SPI3_BASE_NS)
+#define SPI4_NS                   ((SPI_TypeDef *) SPI4_BASE_NS)
+#define SPI5_NS                   ((SPI_TypeDef *) SPI5_BASE_NS)
+#define SPI6_NS                   ((SPI_TypeDef *) SPI6_BASE_NS)
+#define SYSCFG_NS                 ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
+#define TAMP_NS                   ((TAMP_TypeDef *) TAMP_BASE_NS)
+#define TIM1_NS                   ((TIM_TypeDef *) TIM1_BASE_NS)
+#define TIM2_NS                   ((TIM_TypeDef *) TIM2_BASE_NS)
+#define TIM3_NS                   ((TIM_TypeDef *) TIM3_BASE_NS)
+#define TIM4_NS                   ((TIM_TypeDef *) TIM4_BASE_NS)
+#define TIM5_NS                   ((TIM_TypeDef *) TIM5_BASE_NS)
+#define TIM6_NS                   ((TIM_TypeDef *) TIM6_BASE_NS)
+#define TIM7_NS                   ((TIM_TypeDef *) TIM7_BASE_NS)
+#define TIM8_NS                   ((TIM_TypeDef *) TIM8_BASE_NS)
+#define TIM9_NS                   ((TIM_TypeDef *) TIM9_BASE_NS)
+#define TIM10_NS                  ((TIM_TypeDef *) TIM10_BASE_NS)
+#define TIM11_NS                  ((TIM_TypeDef *) TIM11_BASE_NS)
+#define TIM12_NS                  ((TIM_TypeDef *) TIM12_BASE_NS)
+#define TIM13_NS                  ((TIM_TypeDef *) TIM13_BASE_NS)
+#define TIM14_NS                  ((TIM_TypeDef *) TIM14_BASE_NS)
+#define TIM15_NS                  ((TIM_TypeDef *) TIM15_BASE_NS)
+#define TIM16_NS                  ((TIM_TypeDef *) TIM16_BASE_NS)
+#define TIM17_NS                  ((TIM_TypeDef *) TIM17_BASE_NS)
+#define TIM18_NS                  ((TIM_TypeDef *) TIM18_BASE_NS)
+#define UART4_NS                  ((USART_TypeDef *) UART4_BASE_NS)
+#define UART5_NS                  ((USART_TypeDef *) UART5_BASE_NS)
+#define UART7_NS                  ((USART_TypeDef *) UART7_BASE_NS)
+#define UART8_NS                  ((USART_TypeDef *) UART8_BASE_NS)
+#define UART9_NS                  ((USART_TypeDef *) UART9_BASE_NS)
+#define UCPD1_NS                  ((UCPD_TypeDef *) UCPD1_BASE_NS)
+#define USART1_NS                 ((USART_TypeDef *) USART1_BASE_NS)
+#define USART2_NS                 ((USART_TypeDef *) USART2_BASE_NS)
+#define USART3_NS                 ((USART_TypeDef *) USART3_BASE_NS)
+#define USART6_NS                 ((USART_TypeDef *) USART6_BASE_NS)
+#define USART10_NS                ((USART_TypeDef *) USART10_BASE_NS)
+#define USB1_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS)
+#define USB2_OTG_HS_NS            ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS)
+#define USB1_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS)
+#define USB2_HS_PHYC_NS           ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS)
+#define VENC_NS                   ((VENC_TypeDef *) VENC_BASE_NS)
+#define VREFBUF_NS                ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
+#define WWDG_NS                   ((WWDG_TypeDef *) WWDG_BASE_NS)
+#define XSPI1_NS                  ((XSPI_TypeDef *) XSPI1_BASE_NS)
+#define XSPI2_NS                  ((XSPI_TypeDef *) XSPI2_BASE_NS)
+#define XSPI3_NS                  ((XSPI_TypeDef *) XSPI3_BASE_NS)
+#define XSPIM_NS                  ((XSPIM_TypeDef *) XSPIM_BASE_NS)
+
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON_S            ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
+#define ADC1_S                    ((ADC_TypeDef *) ADC1_BASE_S)
+#define ADC2_S                    ((ADC_TypeDef *) ADC2_BASE_S)
+#define ADF1_S                    ((MDF_TypeDef *) ADF1_BASE_S)
+#define ADF1_Filter0_S            ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S)
+#define BSEC_S                    ((BSEC_TypeDef *) BSEC_BASE_S)
+#define CACHEAXI_S                ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S)
+#define CRC_S                     ((CRC_TypeDef *) CRC_BASE_S)
+#define CRYP_S                    ((CRYP_TypeDef *) CRYP_BASE_S)
+#define CSI_S                     ((CSI_TypeDef *) CSI_BASE_S)
+#define DBGMCU_S                  ((DBGMCU_TypeDef *) DBGMCU_BASE_S)
+#define DCMI_S                    ((DCMI_TypeDef *) DCMI_BASE_S)
+#define DCMIPP_S                  ((DCMIPP_TypeDef *) DCMIPP_BASE_S)
+#define DLYB_SDMMC1_S             ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
+#define DLYB_SDMMC2_S             ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
+#define DMA2D_S                   ((DMA2D_TypeDef *) DMA2D_BASE_S)
+#define DTS_S                     ((DTS_TypeDef *) DTS_BASE_S)
+#define DTS_Sensor0_S             ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S)
+#define DTS_Sensor1_S             ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S)
+#define ETH1_S                    ((ETH_TypeDef *) ETH1_BASE_S)
+#define EXTI_S                    ((EXTI_TypeDef *) EXTI_BASE_S)
+#define FDCAN1_S                  ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
+#define FDCAN2_S                  ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S)
+#define FDCAN3_S                  ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S)
+#define FDCAN_CCU_S               ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S)
+#define FDCAN_CONFIG_S            ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
+#define FMC_Bank1E_R_S            ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
+#define FMC_Bank1_R_S             ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
+#define FMC_Bank3_R_S             ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
+#define FMC_Bank5_6_R_S           ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S)
+#define FMC_Common_R_S            ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S)
+#define GFXMMU_S                  ((GFXMMU_TypeDef *) GFXMMU_BASE_S)
+#define GFXTIM_S                  ((GFXTIM_TypeDef *) GFXTIM_BASE_S)
+#define GPDMA1_S                  ((DMA_TypeDef *) GPDMA1_BASE_S)
+#define GPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
+#define GPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
+#define GPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
+#define GPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
+#define GPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
+#define GPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
+#define GPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
+#define GPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
+#define GPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
+#define GPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
+#define GPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
+#define GPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
+#define GPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
+#define GPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
+#define GPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
+#define GPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
+#define GPIOA_S                   ((GPIO_TypeDef *) GPIOA_BASE_S)
+#define GPIOB_S                   ((GPIO_TypeDef *) GPIOB_BASE_S)
+#define GPIOC_S                   ((GPIO_TypeDef *) GPIOC_BASE_S)
+#define GPIOD_S                   ((GPIO_TypeDef *) GPIOD_BASE_S)
+#define GPIOE_S                   ((GPIO_TypeDef *) GPIOE_BASE_S)
+#define GPIOF_S                   ((GPIO_TypeDef *) GPIOF_BASE_S)
+#define GPIOG_S                   ((GPIO_TypeDef *) GPIOG_BASE_S)
+#define GPIOH_S                   ((GPIO_TypeDef *) GPIOH_BASE_S)
+#define GPION_S                   ((GPIO_TypeDef *) GPION_BASE_S)
+#define GPIOO_S                   ((GPIO_TypeDef *) GPIOO_BASE_S)
+#define GPIOP_S                   ((GPIO_TypeDef *) GPIOP_BASE_S)
+#define GPIOQ_S                   ((GPIO_TypeDef *) GPIOQ_BASE_S)
+#define HASH_S                    ((HASH_TypeDef *) HASH_BASE_S)
+#define HASH_DIGEST_S             ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
+#define HPDMA1_S                  ((DMA_TypeDef *) HPDMA1_BASE_S)
+#define HPDMA1_Channel0_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S)
+#define HPDMA1_Channel1_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S)
+#define HPDMA1_Channel2_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S)
+#define HPDMA1_Channel3_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S)
+#define HPDMA1_Channel4_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S)
+#define HPDMA1_Channel5_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S)
+#define HPDMA1_Channel6_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S)
+#define HPDMA1_Channel7_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S)
+#define HPDMA1_Channel8_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S)
+#define HPDMA1_Channel9_S         ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S)
+#define HPDMA1_Channel10_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S)
+#define HPDMA1_Channel11_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S)
+#define HPDMA1_Channel12_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S)
+#define HPDMA1_Channel13_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S)
+#define HPDMA1_Channel14_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S)
+#define HPDMA1_Channel15_S        ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S)
+#define I2C1_S                    ((I2C_TypeDef *) I2C1_BASE_S)
+#define I2C2_S                    ((I2C_TypeDef *) I2C2_BASE_S)
+#define I2C3_S                    ((I2C_TypeDef *) I2C3_BASE_S)
+#define I2C4_S                    ((I2C_TypeDef *) I2C4_BASE_S)
+#define I3C1_S                    ((I3C_TypeDef *) I3C1_BASE_S)
+#define I3C2_S                    ((I3C_TypeDef *) I3C2_BASE_S)
+#define IAC_S                     ((IAC_TypeDef *) IAC_BASE_S)
+#define ICACHE_S                  ((ICACHE_TypeDef *) ICACHE_BASE_S)
+#define IWDG_S                    ((IWDG_TypeDef *) IWDG_BASE_S)
+#define JPEG_S                    ((JPEG_TypeDef *) JPEG_BASE_S)
+#define LPTIM1_S                  ((LPTIM_TypeDef *) LPTIM1_BASE_S)
+#define LPTIM2_S                  ((LPTIM_TypeDef *) LPTIM2_BASE_S)
+#define LPTIM3_S                  ((LPTIM_TypeDef *) LPTIM3_BASE_S)
+#define LPTIM4_S                  ((LPTIM_TypeDef *) LPTIM4_BASE_S)
+#define LPTIM5_S                  ((LPTIM_TypeDef *) LPTIM5_BASE_S)
+#define LPUART1_S                 ((USART_TypeDef *) LPUART1_BASE_S)
+#define LTDC_S                    ((LTDC_TypeDef *)LTDC_BASE_S)
+#define LTDC_Layer1_S             ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S)
+#define LTDC_Layer2_S             ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S)
+#define MCE1_S                    ((MCE_TypeDef *) MCE1_BASE_S)
+#define MCE1_REGION1_S            ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S)
+#define MCE1_REGION2_S            ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S)
+#define MCE1_REGION3_S            ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S)
+#define MCE1_REGION4_S            ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S)
+#define MCE1_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S)
+#define MCE1_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S)
+#define MCE2_S                    ((MCE_TypeDef *) MCE2_BASE_S)
+#define MCE2_REGION1_S            ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S)
+#define MCE2_REGION2_S            ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S)
+#define MCE2_REGION3_S            ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S)
+#define MCE2_REGION4_S            ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S)
+#define MCE2_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S)
+#define MCE2_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S)
+#define MCE3_S                    ((MCE_TypeDef *) MCE3_BASE_S)
+#define MCE3_REGION1_S            ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S)
+#define MCE3_REGION2_S            ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S)
+#define MCE3_REGION3_S            ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S)
+#define MCE3_REGION4_S            ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S)
+#define MCE3_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S)
+#define MCE3_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S)
+#define MCE4_S                    ((MCE_TypeDef *) MCE4_BASE_S)
+#define MCE4_REGION1_S            ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S)
+#define MCE4_REGION2_S            ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S)
+#define MCE4_REGION3_S            ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S)
+#define MCE4_REGION4_S            ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S)
+#define MCE4_CONTEXT1_S           ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S)
+#define MCE4_CONTEXT2_S           ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S)
+#define MDF1_S                    ((MDF_TypeDef *) MDF1_BASE_S)
+#define MDF1_Filter0_S            ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S)
+#define MDF1_Filter1_S            ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S)
+#define MDF1_Filter2_S            ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S)
+#define MDF1_Filter3_S            ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S)
+#define MDF1_Filter4_S            ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S)
+#define MDF1_Filter5_S            ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S)
+#define MDIOS_S                   ((MDIOS_TypeDef *) MDIOS_BASE_S)
+#define PKA_S                     ((PKA_TypeDef *) PKA_BASE_S)
+#define PSSI_S                    ((PSSI_TypeDef *) PSSI_BASE_S)
+#define PWR_S                     ((PWR_TypeDef *) PWR_BASE_S)
+#define RAMCFG_S                  ((RAMCFG_TypeDef *) RAMCFG_BASE_S)
+#define RAMCFG_SRAM1_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S)
+#define RAMCFG_SRAM2_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S)
+#define RAMCFG_SRAM3_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S)
+#define RAMCFG_SRAM4_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S)
+#define RAMCFG_SRAM5_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S)
+#define RAMCFG_SRAM6_AXI_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S)
+#define RAMCFG_SRAM1_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S)
+#define RAMCFG_SRAM2_AHB_S        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S)
+#define RAMCFG_VENC_RAM_S         ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
+#define RAMCFG_BKPSRAM_S          ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S)
+#define RAMCFG_FLEXRAM_S          ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S)
+#define RCC_S                     ((RCC_TypeDef *) RCC_BASE_S)
+#define RIFSC_S                   ((RIFSC_TypeDef *) RIFSC_BASE_S)
+#define RISAF1_S                  ((RISAF_TypeDef *) RISAF1_BASE_S)
+#define RISAF2_S                  ((RISAF_TypeDef *) RISAF2_BASE_S)
+#define RISAF3_S                  ((RISAF_TypeDef *) RISAF3_BASE_S)
+#define RISAF4_S                  ((RISAF_TypeDef *) RISAF4_BASE_S)
+#define RISAF5_S                  ((RISAF_TypeDef *) RISAF5_BASE_S)
+#define RISAF6_S                  ((RISAF_TypeDef *) RISAF6_BASE_S)
+#define RISAF7_S                  ((RISAF_TypeDef *) RISAF7_BASE_S)
+#define RISAF8_S                  ((RISAF_TypeDef *) RISAF8_BASE_S)
+#define RISAF9_S                  ((RISAF_TypeDef *) RISAF9_BASE_S)
+#define RISAF11_S                 ((RISAF_TypeDef *) RISAF11_BASE_S)
+#define RISAF12_S                 ((RISAF_TypeDef *) RISAF12_BASE_S)
+#define RISAF13_S                 ((RISAF_TypeDef *) RISAF13_BASE_S)
+#define RISAF14_S                 ((RISAF_TypeDef *) RISAF14_BASE_S)
+#define RISAF15_S                 ((RISAF_TypeDef *) RISAF15_BASE_S)
+#define RISAF21_S                 ((RISAF_TypeDef *) RISAF21_BASE_S)
+#define RISAF22_S                 ((RISAF_TypeDef *) RISAF22_BASE_S)
+#define RISAF23_S                 ((RISAF_TypeDef *) RISAF23_BASE_S)
+#define RNG_S                     ((RNG_TypeDef *) RNG_BASE_S)
+#define RTC_S                     ((RTC_TypeDef *) RTC_BASE_S)
+#define SAES_S                    ((SAES_TypeDef *) SAES_BASE_S)
+#define SAI1_S                    ((SAI_TypeDef *) SAI1_BASE_S)
+#define SAI1_Block_A_S            ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S)
+#define SAI1_Block_B_S            ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S)
+#define SAI2_S                    ((SAI_TypeDef *) SAI2_BASE_S)
+#define SAI2_Block_A_S            ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S)
+#define SAI2_Block_B_S            ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S)
+#define SDMMC1_S                  ((SDMMC_TypeDef *) SDMMC1_BASE_S)
+#define SDMMC2_S                  ((SDMMC_TypeDef *) SDMMC2_BASE_S)
+#define SPDIFRX_S                 ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S)
+#define SPI1_S                    ((SPI_TypeDef *) SPI1_BASE_S)
+#define SPI2_S                    ((SPI_TypeDef *) SPI2_BASE_S)
+#define SPI3_S                    ((SPI_TypeDef *) SPI3_BASE_S)
+#define SPI4_S                    ((SPI_TypeDef *) SPI4_BASE_S)
+#define SPI5_S                    ((SPI_TypeDef *) SPI5_BASE_S)
+#define SPI6_S                    ((SPI_TypeDef *) SPI6_BASE_S)
+#define SYSCFG_S                  ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
+#define TAMP_S                    ((TAMP_TypeDef *) TAMP_BASE_S)
+#define TIM1_S                    ((TIM_TypeDef *) TIM1_BASE_S)
+#define TIM2_S                    ((TIM_TypeDef *) TIM2_BASE_S)
+#define TIM3_S                    ((TIM_TypeDef *) TIM3_BASE_S)
+#define TIM4_S                    ((TIM_TypeDef *) TIM4_BASE_S)
+#define TIM5_S                    ((TIM_TypeDef *) TIM5_BASE_S)
+#define TIM6_S                    ((TIM_TypeDef *) TIM6_BASE_S)
+#define TIM7_S                    ((TIM_TypeDef *) TIM7_BASE_S)
+#define TIM8_S                    ((TIM_TypeDef *) TIM8_BASE_S)
+#define TIM9_S                    ((TIM_TypeDef *) TIM9_BASE_S)
+#define TIM10_S                   ((TIM_TypeDef *) TIM10_BASE_S)
+#define TIM11_S                   ((TIM_TypeDef *) TIM11_BASE_S)
+#define TIM12_S                   ((TIM_TypeDef *) TIM12_BASE_S)
+#define TIM13_S                   ((TIM_TypeDef *) TIM13_BASE_S)
+#define TIM14_S                   ((TIM_TypeDef *) TIM14_BASE_S)
+#define TIM15_S                   ((TIM_TypeDef *) TIM15_BASE_S)
+#define TIM16_S                   ((TIM_TypeDef *) TIM16_BASE_S)
+#define TIM17_S                   ((TIM_TypeDef *) TIM17_BASE_S)
+#define TIM18_S                   ((TIM_TypeDef *) TIM18_BASE_S)
+#define UART4_S                   ((USART_TypeDef *) UART4_BASE_S)
+#define UART5_S                   ((USART_TypeDef *) UART5_BASE_S)
+#define UART7_S                   ((USART_TypeDef *) UART7_BASE_S)
+#define UART8_S                   ((USART_TypeDef *) UART8_BASE_S)
+#define UART9_S                   ((USART_TypeDef *) UART9_BASE_S)
+#define UCPD1_S                   ((UCPD_TypeDef *) UCPD1_BASE_S)
+#define USART1_S                  ((USART_TypeDef *) USART1_BASE_S)
+#define USART2_S                  ((USART_TypeDef *) USART2_BASE_S)
+#define USART3_S                  ((USART_TypeDef *) USART3_BASE_S)
+#define USART6_S                  ((USART_TypeDef *) USART6_BASE_S)
+#define USART10_S                 ((USART_TypeDef *) USART10_BASE_S)
+#define USB1_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S)
+#define USB2_OTG_HS_S             ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S)
+#define USB1_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S)
+#define USB2_HS_PHYC_S            ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S)
+#define VENC_S                    ((VENC_TypeDef *) VENC_BASE_S)
+#define VREFBUF_S                 ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
+#define WWDG_S                    ((WWDG_TypeDef *) WWDG_BASE_S)
+#define XSPI1_S                   ((XSPI_TypeDef *) XSPI1_BASE_S)
+#define XSPI2_S                   ((XSPI_TypeDef *) XSPI2_BASE_S)
+#define XSPI3_S                   ((XSPI_TypeDef *) XSPI3_BASE_S)
+#define XSPIM_S                   ((XSPIM_TypeDef *) XSPIM_BASE_S)
+#endif
+
+/*!< Peripheral Instance aliases for Non-Secure/Secure execution  */
+#if defined (CPU_IN_SECURE_STATE)
+#define ADC12_COMMON              ADC12_COMMON_S
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_S
+
+#define ADC1                      ADC1_S
+#define ADC1_BASE                 ADC1_BASE_S
+
+#define ADC2                      ADC2_S
+#define ADC2_BASE                 ADC2_BASE_S
+
+#define ADF1                      ADF1_S
+#define ADF1_BASE                 ADF1_BASE_S
+
+#define ADF1_Filter0              ADF1_Filter0_S
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_S
+
+#define BSEC                      BSEC_S
+#define BSEC_BASE                 BSEC_BASE_S
+
+#define CACHEAXI                  CACHEAXI_S
+#define CACHEAXI_BASE             CACHEAXI_BASE_S
+
+#define CRC                       CRC_S
+#define CRC_BASE                  CRC_BASE_S
+
+#define CRYP                      CRYP_S
+#define CRYP_BASE                 CRYP_BASE_S
+
+#define CSI                       CSI_S
+#define CSI_BASE                  CSI_BASE_S
+
+#define DBGMCU                    DBGMCU_S
+#define DBGMCU_BASE               DBGMCU_BASE_S
+
+#define DCMI                      DCMI_S
+#define DCMI_BASE                 DCMI_BASE_S
+
+#define DCMIPP                    DCMIPP_S
+#define DCMIPP_BASE               DCMIPP_BASE_S
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_S
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_S
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_S
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_S
+
+#define DMA2D                     DMA2D_S
+#define DMA2D_BASE                DMA2D_BASE_S
+
+#define DTS                       DTS_S
+#define DTS_BASE                  DTS_BASE_S
+
+#define DTS_Sensor0               DTS_Sensor0_S
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_S
+
+#define DTS_Sensor1               DTS_Sensor1_S
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_S
+
+#define ETH1                      ETH1_S
+#define ETH1_BASE                 ETH1_BASE_S
+
+#define EXTI                      EXTI_S
+#define EXTI_BASE                 EXTI_BASE_S
+
+#define FDCAN1                    FDCAN1_S
+#define FDCAN1_BASE               FDCAN1_BASE_S
+
+#define FDCAN2                    FDCAN2_S
+#define FDCAN2_BASE               FDCAN2_BASE_S
+
+#define FDCAN3                    FDCAN3_S
+#define FDCAN3_BASE               FDCAN3_BASE_S
+
+#define FDCAN_CCU                 FDCAN_CCU_S
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_S
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_S
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_S
+
+#define FMC_R_BASE                FMC_R_BASE_S
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_S
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_S
+
+#define FMC_Bank1_R               FMC_Bank1_R_S
+#define FMC_Bank1_R_BASE          FMC_Bank1_R_BASE_S
+
+#define FMC_Bank3_R               FMC_Bank3_R_S
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_S
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_S
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_S
+
+#define FMC_Common_R              FMC_Common_R_S
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_S
+
+#define GFXMMU                       GFXMMU_S
+#define GFXMMU_BASE                  GFXMMU_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_S
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_S
+
+#define GFXTIM                    GFXTIM_S
+#define GFXTIM_BASE               GFXTIM_BASE_S
+
+#define GPDMA1                    GPDMA1_S
+#define GPDMA1_BASE               GPDMA1_BASE_S
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_S
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_S
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_S
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_S
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_S
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_S
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_S
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_S
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_S
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_S
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_S
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_S
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_S
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_S
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_S
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_S
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_S
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_S
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_S
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_S
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_S
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_S
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_S
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_S
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_S
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_S
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_S
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_S
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_S
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_S
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_S
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_S
+
+#define GPIOA                     GPIOA_S
+#define GPIOA_BASE                GPIOA_BASE_S
+
+#define GPIOB                     GPIOB_S
+#define GPIOB_BASE                GPIOB_BASE_S
+
+#define GPIOC                     GPIOC_S
+#define GPIOC_BASE                GPIOC_BASE_S
+
+#define GPIOD                     GPIOD_S
+#define GPIOD_BASE                GPIOD_BASE_S
+
+#define GPIOE                     GPIOE_S
+#define GPIOE_BASE                GPIOE_BASE_S
+
+#define GPIOF                     GPIOF_S
+#define GPIOF_BASE                GPIOF_BASE_S
+
+#define GPIOG                     GPIOG_S
+#define GPIOG_BASE                GPIOG_BASE_S
+
+#define GPIOH                     GPIOH_S
+#define GPIOH_BASE                GPIOH_BASE_S
+
+#define GPION                     GPION_S
+#define GPION_BASE                GPION_BASE_S
+
+#define GPIOO                     GPIOO_S
+#define GPIOO_BASE                GPIOO_BASE_S
+
+#define GPIOP                     GPIOP_S
+#define GPIOP_BASE                GPIOP_BASE_S
+
+#define GPIOQ                     GPIOQ_S
+#define GPIOQ_BASE                GPIOQ_BASE_S
+
+#define GPU2D                     GPU2D_BASE_S
+#define GPU2D_BASE                GPU2D_BASE_S
+
+#define HASH                      HASH_S
+#define HASH_BASE                 HASH_BASE_S
+
+#define HASH_DIGEST               HASH_DIGEST_S
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_S
+
+#define HPDMA1                    HPDMA1_S
+#define HPDMA1_BASE               HPDMA1_BASE_S
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_S
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_S
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_S
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_S
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_S
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_S
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_S
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_S
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_S
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_S
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_S
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_S
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_S
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_S
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_S
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_S
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_S
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_S
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_S
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_S
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_S
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_S
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_S
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_S
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_S
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_S
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_S
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_S
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_S
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_S
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_S
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_S
+
+#define I2C1                      I2C1_S
+#define I2C1_BASE                 I2C1_BASE_S
+
+#define I2C2                      I2C2_S
+#define I2C2_BASE                 I2C2_BASE_S
+
+#define I2C3                      I2C3_S
+#define I2C3_BASE                 I2C3_BASE_S
+
+#define I2C4                      I2C4_S
+#define I2C4_BASE                 I2C4_BASE_S
+
+#define I3C1                      I3C1_S
+#define I3C1_BASE                 I3C1_BASE_S
+
+#define I3C2                      I3C2_S
+#define I3C2_BASE                 I3C2_BASE_S
+
+#define IAC                       IAC_S
+#define IAC_BASE                  IAC_BASE_S
+
+#define ICACHE                    ICACHE_S
+#define ICACHE_BASE               ICACHE_BASE_S
+
+#define IWDG                      IWDG_S
+#define IWDG_BASE                 IWDG_BASE_S
+
+#define JPEG                      JPEG_S
+#define JPEG_BASE                 JPEG_BASE_S
+
+#define LPTIM1                    LPTIM1_S
+#define LPTIM1_BASE               LPTIM1_BASE_S
+
+#define LPTIM2                    LPTIM2_S
+#define LPTIM2_BASE               LPTIM2_BASE_S
+
+#define LPTIM3                    LPTIM3_S
+#define LPTIM3_BASE               LPTIM3_BASE_S
+
+#define LPTIM4                    LPTIM4_S
+#define LPTIM4_BASE               LPTIM4_BASE_S
+
+#define LPTIM5                    LPTIM5_S
+#define LPTIM5_BASE               LPTIM5_BASE_S
+
+#define LPUART1                   LPUART1_S
+#define LPUART1_BASE              LPUART1_BASE_S
+
+#define LTDC                      LTDC_S
+#define LTDC_BASE                 LTDC_BASE_S
+
+#define LTDC_Layer1               LTDC_Layer1_S
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_S
+
+#define LTDC_Layer2               LTDC_Layer2_S
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_S
+
+#define MCE1                      MCE1_S
+#define MCE1_BASE                 MCE1_BASE_S
+
+#define MCE1_REGION1              MCE1_REGION1_S
+#define MCE1_REGION1_BASE         MCE1_REGION1_BASE_S
+
+#define MCE1_REGION2              MCE1_REGION2_S
+#define MCE1_REGION2_BASE         MCE1_REGION2_BASE_S
+
+#define MCE1_REGION3              MCE1_REGION3_S
+#define MCE1_REGION3_BASE         MCE1_REGION3_BASE_S
+
+#define MCE1_REGION4              MCE1_REGION4_S
+#define MCE1_REGION4_BASE         MCE1_REGION4_BASE_S
+
+#define MCE1_CONTEXT1             MCE1_CONTEXT1_S
+#define MCE1_CONTEXT1_BASE        MCE1_CONTEXT1_BASE_S
+
+#define MCE1_CONTEXT2             MCE1_CONTEXT2_S
+#define MCE1_CONTEXT2_BASE        MCE1_CONTEXT2_BASE_S
+
+#define MCE2                      MCE2_S
+#define MCE2_BASE                 MCE2_BASE_S
+
+#define MCE2_REGION1              MCE2_REGION1_S
+#define MCE2_REGION1_BASE         MCE2_REGION1_BASE_S
+
+#define MCE2_REGION2              MCE2_REGION2_S
+#define MCE2_REGION2_BASE         MCE2_REGION2_BASE_S
+
+#define MCE2_REGION3              MCE2_REGION3_S
+#define MCE2_REGION3_BASE         MCE2_REGION3_BASE_S
+
+#define MCE2_REGION4              MCE2_REGION4_S
+#define MCE2_REGION4_BASE         MCE2_REGION4_BASE_S
+
+#define MCE2_CONTEXT1             MCE2_CONTEXT1_S
+#define MCE2_CONTEXT1_BASE        MCE2_CONTEXT1_BASE_S
+
+#define MCE2_CONTEXT2             MCE2_CONTEXT2_S
+#define MCE2_CONTEXT2_BASE        MCE2_CONTEXT2_BASE_S
+
+#define MCE3                      MCE3_S
+#define MCE3_BASE                 MCE3_BASE_S
+
+#define MCE3_REGION1              MCE3_REGION1_S
+#define MCE3_REGION1_BASE         MCE3_REGION1_BASE_S
+
+#define MCE3_REGION2              MCE3_REGION2_S
+#define MCE3_REGION2_BASE         MCE3_REGION2_BASE_S
+
+#define MCE3_REGION3              MCE3_REGION3_S
+#define MCE3_REGION3_BASE         MCE3_REGION3_BASE_S
+
+#define MCE3_REGION4              MCE3_REGION4_S
+#define MCE3_REGION4_BASE         MCE3_REGION4_BASE_S
+
+#define MCE3_CONTEXT1             MCE3_CONTEXT1_S
+#define MCE3_CONTEXT1_BASE        MCE3_CONTEXT1_BASE_S
+
+#define MCE3_CONTEXT2             MCE3_CONTEXT2_S
+#define MCE3_CONTEXT2_BASE        MCE3_CONTEXT2_BASE_S
+
+#define MCE4                      MCE4_S
+#define MCE4_BASE                 MCE4_BASE_S
+
+#define MCE4_REGION1              MCE4_REGION1_S
+#define MCE4_REGION1_BASE         MCE4_REGION1_BASE_S
+
+#define MCE4_REGION2              MCE4_REGION2_S
+#define MCE4_REGION2_BASE         MCE4_REGION2_BASE_S
+
+#define MCE4_REGION3              MCE4_REGION3_S
+#define MCE4_REGION3_BASE         MCE4_REGION3_BASE_S
+
+#define MCE4_REGION4              MCE4_REGION4_S
+#define MCE4_REGION4_BASE         MCE4_REGION4_BASE_S
+
+#define MCE4_CONTEXT1             MCE4_CONTEXT1_S
+#define MCE4_CONTEXT1_BASE        MCE4_CONTEXT1_BASE_S
+
+#define MCE4_CONTEXT2             MCE4_CONTEXT2_S
+#define MCE4_CONTEXT2_BASE        MCE4_CONTEXT2_BASE_S
+
+#define MDF1                      MDF1_S
+#define MDF1_BASE                 MDF1_BASE_S
+
+#define MDF1_Filter0              MDF1_Filter0_S
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_S
+
+#define MDF1_Filter1              MDF1_Filter1_S
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_S
+
+#define MDF1_Filter2              MDF1_Filter2_S
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_S
+
+#define MDF1_Filter3              MDF1_Filter3_S
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_S
+
+#define MDF1_Filter4              MDF1_Filter4_S
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_S
+
+#define MDF1_Filter5              MDF1_Filter5_S
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_S
+
+#define MDIOS                     MDIOS_S
+#define MDIOS_BASE                MDIOS_BASE_S
+
+#define NPU_PRESENT
+#define NPU_BASE                  NPU_BASE_S
+
+#define PKA                       PKA_S
+#define PKA_BASE                  PKA_BASE_S
+
+#define PSSI                      PSSI_S
+#define PSSI_BASE                 PSSI_BASE_S
+
+#define PWR                       PWR_S
+#define PWR_BASE                  PWR_BASE_S
+
+#define RAMCFG                    RAMCFG_S
+#define RAMCFG_BASE               RAMCFG_BASE_S
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_S
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_S
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_S
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_S
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_S
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_S
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_S
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_S
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_S
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_S
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_S
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_S
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_S
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_S
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_S
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_S
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_S
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_S
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_S
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_S
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_S
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_S
+
+#define RCC                       RCC_S
+#define RCC_BASE                  RCC_BASE_S
+
+#define RIFSC                     RIFSC_S
+#define RIFSC_BASE                RIFSC_BASE_S
+
+#define RISAF1                    RISAF1_S
+#define RISAF1_BASE               RISAF1_BASE_S
+
+#define RISAF2                    RISAF2_S
+#define RISAF2_BASE               RISAF2_BASE_S
+
+#define RISAF3                    RISAF3_S
+#define RISAF3_BASE               RISAF3_BASE_S
+
+#define RISAF4                    RISAF4_S
+#define RISAF4_BASE               RISAF4_BASE_S
+
+#define RISAF5                    RISAF5_S
+#define RISAF5_BASE               RISAF5_BASE_S
+
+#define RISAF6                    RISAF6_S
+#define RISAF6_BASE               RISAF6_BASE_S
+
+#define RISAF7                    RISAF7_S
+#define RISAF7_BASE               RISAF7_BASE_S
+
+#define RISAF8                    RISAF8_S
+#define RISAF8_BASE               RISAF8_BASE_S
+
+#define RISAF9                    RISAF9_S
+#define RISAF9_BASE               RISAF9_BASE_S
+
+#define RISAF11                   RISAF11_S
+#define RISAF11_BASE              RISAF11_BASE_S
+
+#define RISAF12                   RISAF12_S
+#define RISAF12_BASE              RISAF12_BASE_S
+
+#define RISAF13                   RISAF13_S
+#define RISAF13_BASE              RISAF13_BASE_S
+
+#define RISAF14                   RISAF14_S
+#define RISAF14_BASE              RISAF14_BASE_S
+
+#define RISAF15                   RISAF15_S
+#define RISAF15_BASE              RISAF15_BASE_S
+
+#define RISAF21                   RISAF21_S
+#define RISAF21_BASE              RISAF21_BASE_S
+
+#define RISAF22                   RISAF22_S
+#define RISAF22_BASE              RISAF22_BASE_S
+
+#define RISAF23                   RISAF23_S
+#define RISAF23_BASE              RISAF23_BASE_S
+
+#define RNG                       RNG_S
+#define RNG_BASE                  RNG_BASE_S
+
+#define RTC                       RTC_S
+#define RTC_BASE                  RTC_BASE_S
+
+#define SAES                      SAES_S
+#define SAES_BASE                 SAES_BASE_S
+
+#define SAI1                      SAI1_S
+#define SAI1_BASE                 SAI1_BASE_S
+
+#define SAI1_Block_A              SAI1_Block_A_S
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_S
+
+#define SAI1_Block_B              SAI1_Block_B_S
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_S
+
+#define SAI2                      SAI2_S
+#define SAI2_BASE                 SAI2_BASE_S
+
+#define SAI2_Block_A              SAI2_Block_A_S
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_S
+
+#define SAI2_Block_B              SAI2_Block_B_S
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_S
+
+#define SDMMC1                    SDMMC1_S
+#define SDMMC1_BASE               SDMMC1_BASE_S
+
+#define SDMMC2                    SDMMC2_S
+#define SDMMC2_BASE               SDMMC2_BASE_S
+
+#define SPDIFRX                   SPDIFRX_S
+#define SPDIFRX_BASE              SPDIFRX_BASE_S
+
+#define SPI1                      SPI1_S
+#define SPI1_BASE                 SPI1_BASE_S
+
+#define SPI2                      SPI2_S
+#define SPI2_BASE                 SPI2_BASE_S
+
+#define SPI3                      SPI3_S
+#define SPI3_BASE                 SPI3_BASE_S
+
+#define SPI4                      SPI4_S
+#define SPI4_BASE                 SPI4_BASE_S
+
+#define SPI5                      SPI5_S
+#define SPI5_BASE                 SPI5_BASE_S
+
+#define SPI6                      SPI6_S
+#define SPI6_BASE                 SPI6_BASE_S
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_S
+
+#define SYSCFG                    SYSCFG_S
+#define SYSCFG_BASE               SYSCFG_BASE_S
+
+#define TAMP                      TAMP_S
+#define TAMP_BASE                 TAMP_BASE_S
+
+#define TIM1                      TIM1_S
+#define TIM1_BASE                 TIM1_BASE_S
+
+#define TIM2                      TIM2_S
+#define TIM2_BASE                 TIM2_BASE_S
+
+#define TIM3                      TIM3_S
+#define TIM3_BASE                 TIM3_BASE_S
+
+#define TIM4                      TIM4_S
+#define TIM4_BASE                 TIM4_BASE_S
+
+#define TIM5                      TIM5_S
+#define TIM5_BASE                 TIM5_BASE_S
+
+#define TIM6                      TIM6_S
+#define TIM6_BASE                 TIM6_BASE_S
+
+#define TIM7                      TIM7_S
+#define TIM7_BASE                 TIM7_BASE_S
+
+#define TIM8                      TIM8_S
+#define TIM8_BASE                 TIM8_BASE_S
+
+#define TIM9                      TIM9_S
+#define TIM9_BASE                 TIM9_BASE_S
+
+#define TIM10                     TIM10_S
+#define TIM10_BASE                TIM10_BASE_S
+
+#define TIM11                     TIM11_S
+#define TIM11_BASE                TIM11_BASE_S
+
+#define TIM12                     TIM12_S
+#define TIM12_BASE                TIM12_BASE_S
+
+#define TIM13                     TIM13_S
+#define TIM13_BASE                TIM13_BASE_S
+
+#define TIM14                     TIM14_S
+#define TIM14_BASE                TIM14_BASE_S
+
+#define TIM15                     TIM15_S
+#define TIM15_BASE                TIM15_BASE_S
+
+#define TIM16                     TIM16_S
+#define TIM16_BASE                TIM16_BASE_S
+
+#define TIM17                     TIM17_S
+#define TIM17_BASE                TIM17_BASE_S
+
+#define TIM18                     TIM18_S
+#define TIM18_BASE                TIM18_BASE_S
+
+#define UART4                     UART4_S
+#define UART4_BASE                UART4_BASE_S
+
+#define UART5                     UART5_S
+#define UART5_BASE                UART5_BASE_S
+
+#define UART7                     UART7_S
+#define UART7_BASE                UART7_BASE_S
+
+#define UART8                     UART8_S
+#define UART8_BASE                UART8_BASE_S
+
+#define UART9                     UART9_S
+#define UART9_BASE                UART9_BASE_S
+
+#define UCPD1                     UCPD1_S
+#define UCPD1_BASE                UCPD1_BASE_S
+
+#define USART1                    USART1_S
+#define USART1_BASE               USART1_BASE_S
+
+#define USART2                    USART2_S
+#define USART2_BASE               USART2_BASE_S
+
+#define USART3                    USART3_S
+#define USART3_BASE               USART3_BASE_S
+
+#define USART6                    USART6_S
+#define USART6_BASE               USART6_BASE_S
+
+#define USART10                   USART10_S
+#define USART10_BASE              USART10_BASE_S
+
+#define USB1_OTG_HS               USB1_OTG_HS_S
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_S
+
+#define USB2_OTG_HS               USB2_OTG_HS_S
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_S
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_S
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_S
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_S
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_S
+
+#define VENC                      VENC_S
+#define VENC_BASE                 VENC_BASE_S
+
+#define VREFBUF                   VREFBUF_S
+#define VREFBUF_BASE              VREFBUF_BASE_S
+
+#define WWDG                      WWDG_S
+#define WWDG_BASE                 WWDG_BASE_S
+
+#define XSPI1                     XSPI1_S
+
+#define XSPI2                     XSPI2_S
+
+#define XSPI3                     XSPI3_S
+
+#define XSPIM                     XSPIM_S
+#define XSPIM_BASE                XSPIM_BASE_S
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_S
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_S
+
+#else
+
+#define ADC12_COMMON              ADC12_COMMON_NS
+#define ADC12_COMMON_BASE         ADC12_COMMON_BASE_NS
+
+#define ADC1                      ADC1_NS
+#define ADC1_BASE                 ADC1_BASE_NS
+
+#define ADC2                      ADC2_NS
+#define ADC2_BASE                 ADC2_BASE_NS
+
+#define ADF1                      ADF1_NS
+#define ADF1_BASE                 ADF1_BASE_NS
+
+#define ADF1_Filter0              ADF1_Filter0_NS
+#define ADF1_Filter0_BASE         ADF1_Filter0_BASE_NS
+
+#define BSEC                      BSEC_NS
+#define BSEC_BASE                 BSEC_BASE_NS
+
+#define CACHEAXI                  CACHEAXI_NS
+#define CACHEAXI_BASE             CACHEAXI_BASE_NS
+
+#define CRC                       CRC_NS
+#define CRC_BASE                  CRC_BASE_NS
+
+#define CRYP                      CRYP_NS
+#define CRYP_BASE                 CRYP_BASE_NS
+
+#define CSI                       CSI_NS
+#define CSI_BASE                  CSI_BASE_NS
+
+#define DBGMCU                    DBGMCU_NS
+#define DBGMCU_BASE               DBGMCU_BASE_NS
+
+#define DCMI                      DCMI_NS
+#define DCMI_BASE                 DCMI_BASE_NS
+
+#define DCMIPP                    DCMIPP_NS
+#define DCMIPP_BASE               DCMIPP_BASE_NS
+
+#define DLYB_SDMMC1               DLYB_SDMMC1_NS
+#define DLYB_SDMMC1_BASE          DLYB_SDMMC1_BASE_NS
+
+#define DLYB_SDMMC2               DLYB_SDMMC2_NS
+#define DLYB_SDMMC2_BASE          DLYB_SDMMC2_BASE_NS
+
+#define DMA2D                     DMA2D_NS
+#define DMA2D_BASE                DMA2D_BASE_NS
+
+#define DTS                       DTS_NS
+#define DTS_BASE                  DTS_BASE_NS
+
+#define DTS_Sensor0               DTS_Sensor0_NS
+#define DTS_Sensor0_BASE          DTS_Sensor0_BASE_NS
+
+#define DTS_Sensor1               DTS_Sensor1_NS
+#define DTS_Sensor1_BASE          DTS_Sensor1_BASE_NS
+
+#define ETH1                      ETH1_NS
+#define ETH1_BASE                 ETH1_BASE_NS
+
+#define EXTI                      EXTI_NS
+#define EXTI_BASE                 EXTI_BASE_NS
+
+#define FDCAN1                    FDCAN1_NS
+#define FDCAN1_BASE               FDCAN1_BASE_NS
+
+#define FDCAN2                    FDCAN2_NS
+#define FDCAN2_BASE               FDCAN2_BASE_NS
+
+#define FDCAN3                    FDCAN3_NS
+#define FDCAN3_BASE               FDCAN3_BASE_NS
+
+#define FDCAN_CCU                 FDCAN_CCU_NS
+#define FDCAN_CCU_BASE            FDCAN_CCU_BASE_NS
+
+#define FDCAN_CONFIG              FDCAN_CONFIG_NS
+#define FDCAN_CONFIG_BASE         FDCAN_CONFIG_BASE_NS
+
+#define FMC_R_BASE                FMC_R_BASE_NS
+#define FMC_R_BASE_BASE           FMC_R_BASE_BASE_NS
+
+#define FMC_Bank1E_R              FMC_Bank1E_R_NS
+#define FMC_Bank1E_R_BASE         FMC_Bank1E_R_BASE_NS
+
+#define FMC_Bank1_R               FMC_Bank1_R_NS
+#define FMC_Bank1_Rv              FMC_Bank1_R_BASE_NS
+
+#define FMC_Bank3_R               FMC_Bank3_R_NS
+#define FMC_Bank3_R_BASE          FMC_Bank3_R_BASE_NS
+
+#define FMC_Bank5_6_R             FMC_Bank5_6_R_NS
+#define FMC_Bank5_6_R_BASE        FMC_Bank5_6_R_BASE_NS
+
+#define FMC_Common_R              FMC_Common_R_NS
+#define FMC_Common_R_BASE         FMC_Common_R_BASE_NS
+
+#define GFXMMU                       GFXMMU_NS
+#define GFXMMU_BASE                  GFXMMU_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER0_BASE  GFXMMU_VIRTUAL_BUFFER0_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER1_BASE  GFXMMU_VIRTUAL_BUFFER1_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER2_BASE  GFXMMU_VIRTUAL_BUFFER2_BASE_NS
+#define GFXMMU_VIRTUAL_BUFFER3_BASE  GFXMMU_VIRTUAL_BUFFER3_BASE_NS
+
+#define GFXTIM                    GFXTIM_NS
+#define GFXTIM_BASE               GFXTIM_BASE_NS
+
+#define GPDMA1                    GPDMA1_NS
+#define GPDMA1_BASE               GPDMA1_BASE_NS
+
+#define GPDMA1_Channel0           GPDMA1_Channel0_NS
+#define GPDMA1_Channel0_BASE      GPDMA1_Channel0_BASE_NS
+
+#define GPDMA1_Channel1           GPDMA1_Channel1_NS
+#define GPDMA1_Channel1_BASE      GPDMA1_Channel1_BASE_NS
+
+#define GPDMA1_Channel2           GPDMA1_Channel2_NS
+#define GPDMA1_Channel2_BASE      GPDMA1_Channel2_BASE_NS
+
+#define GPDMA1_Channel3           GPDMA1_Channel3_NS
+#define GPDMA1_Channel3_BASE      GPDMA1_Channel3_BASE_NS
+
+#define GPDMA1_Channel4           GPDMA1_Channel4_NS
+#define GPDMA1_Channel4_BASE      GPDMA1_Channel4_BASE_NS
+
+#define GPDMA1_Channel5           GPDMA1_Channel5_NS
+#define GPDMA1_Channel5_BASE      GPDMA1_Channel5_BASE_NS
+
+#define GPDMA1_Channel6           GPDMA1_Channel6_NS
+#define GPDMA1_Channel6_BASE      GPDMA1_Channel6_BASE_NS
+
+#define GPDMA1_Channel7           GPDMA1_Channel7_NS
+#define GPDMA1_Channel7_BASE      GPDMA1_Channel7_BASE_NS
+
+#define GPDMA1_Channel8           GPDMA1_Channel8_NS
+#define GPDMA1_Channel8_BASE      GPDMA1_Channel8_BASE_NS
+
+#define GPDMA1_Channel9           GPDMA1_Channel9_NS
+#define GPDMA1_Channel9_BASE      GPDMA1_Channel9_BASE_NS
+
+#define GPDMA1_Channel10          GPDMA1_Channel10_NS
+#define GPDMA1_Channel10_BASE     GPDMA1_Channel10_BASE_NS
+
+#define GPDMA1_Channel11          GPDMA1_Channel11_NS
+#define GPDMA1_Channel11_BASE     GPDMA1_Channel11_BASE_NS
+
+#define GPDMA1_Channel12          GPDMA1_Channel12_NS
+#define GPDMA1_Channel12_BASE     GPDMA1_Channel12_BASE_NS
+
+#define GPDMA1_Channel13          GPDMA1_Channel13_NS
+#define GPDMA1_Channel13_BASE     GPDMA1_Channel13_BASE_NS
+
+#define GPDMA1_Channel14          GPDMA1_Channel14_NS
+#define GPDMA1_Channel14_BASE     GPDMA1_Channel14_BASE_NS
+
+#define GPDMA1_Channel15          GPDMA1_Channel15_NS
+#define GPDMA1_Channel15_BASE     GPDMA1_Channel15_BASE_NS
+
+#define GPIOA                     GPIOA_NS
+#define GPIOA_BASE                GPIOA_BASE_NS
+
+#define GPIOB                     GPIOB_NS
+#define GPIOB_BASE                GPIOB_BASE_NS
+
+#define GPIOC                     GPIOC_NS
+#define GPIOC_BASE                GPIOC_BASE_NS
+
+#define GPIOD                     GPIOD_NS
+#define GPIOD_BASE                GPIOD_BASE_NS
+
+#define GPIOE                     GPIOE_NS
+#define GPIOE_BASE                GPIOE_BASE_NS
+
+#define GPIOF                     GPIOF_NS
+#define GPIOF_BASE                GPIOF_BASE_NS
+
+#define GPIOG                     GPIOG_NS
+#define GPIOG_BASE                GPIOG_BASE_NS
+
+#define GPIOH                     GPIOH_NS
+#define GPIOH_BASE                GPIOH_BASE_NS
+
+#define GPION                     GPION_NS
+#define GPION_BASE                GPION_BASE_NS
+
+#define GPIOO                     GPIOO_NS
+#define GPIOO_BASE                GPIOO_BASE_NS
+
+#define GPIOP                     GPIOP_NS
+#define GPIOP_BASE                GPIOP_BASE_NS
+
+#define GPIOQ                     GPIOQ_NS
+#define GPIOQ_BASE                GPIOQ_BASE_NS
+
+#define GPU2D                     GPU2D_BASE_NS
+#define GPU2D_BASE                GPU2D_BASE_NS
+
+#define HASH                      HASH_NS
+#define HASH_BASE                 HASH_BASE_NS
+
+#define HASH_DIGEST               HASH_DIGEST_NS
+#define HASH_DIGEST_BASE          HASH_DIGEST_BASE_NS
+
+#define HPDMA1                    HPDMA1_NS
+#define HPDMA1_BASE               HPDMA1_BASE_NS
+
+#define HPDMA1_Channel0           HPDMA1_Channel0_NS
+#define HPDMA1_Channel0_BASE      HPDMA1_Channel0_BASE_NS
+
+#define HPDMA1_Channel1           HPDMA1_Channel1_NS
+#define HPDMA1_Channel1_BASE      HPDMA1_Channel1_BASE_NS
+
+#define HPDMA1_Channel2           HPDMA1_Channel2_NS
+#define HPDMA1_Channel2_BASE      HPDMA1_Channel2_BASE_NS
+
+#define HPDMA1_Channel3           HPDMA1_Channel3_NS
+#define HPDMA1_Channel3_BASE      HPDMA1_Channel3_BASE_NS
+
+#define HPDMA1_Channel4           HPDMA1_Channel4_NS
+#define HPDMA1_Channel4_BASE      HPDMA1_Channel4_BASE_NS
+
+#define HPDMA1_Channel5           HPDMA1_Channel5_NS
+#define HPDMA1_Channel5_BASE      HPDMA1_Channel5_BASE_NS
+
+#define HPDMA1_Channel6           HPDMA1_Channel6_NS
+#define HPDMA1_Channel6_BASE      HPDMA1_Channel6_BASE_NS
+
+#define HPDMA1_Channel7           HPDMA1_Channel7_NS
+#define HPDMA1_Channel7_BASE      HPDMA1_Channel7_BASE_NS
+
+#define HPDMA1_Channel8           HPDMA1_Channel8_NS
+#define HPDMA1_Channel8_BASE      HPDMA1_Channel8_BASE_NS
+
+#define HPDMA1_Channel9           HPDMA1_Channel9_NS
+#define HPDMA1_Channel9_BASE      HPDMA1_Channel9_BASE_NS
+
+#define HPDMA1_Channel10          HPDMA1_Channel10_NS
+#define HPDMA1_Channel10_BASE     HPDMA1_Channel10_BASE_NS
+
+#define HPDMA1_Channel11          HPDMA1_Channel11_NS
+#define HPDMA1_Channel11_BASE     HPDMA1_Channel11_BASE_NS
+
+#define HPDMA1_Channel12          HPDMA1_Channel12_NS
+#define HPDMA1_Channel12_BASE     HPDMA1_Channel12_BASE_NS
+
+#define HPDMA1_Channel13          HPDMA1_Channel13_NS
+#define HPDMA1_Channel13_BASE     HPDMA1_Channel13_BASE_NS
+
+#define HPDMA1_Channel14          HPDMA1_Channel14_NS
+#define HPDMA1_Channel14_BASE     HPDMA1_Channel14_BASE_NS
+
+#define HPDMA1_Channel15          HPDMA1_Channel15_NS
+#define HPDMA1_Channel15_BASE     HPDMA1_Channel15_BASE_NS
+
+#define I2C1                      I2C1_NS
+#define I2C1_BASE                 I2C1_BASE_NS
+
+#define I2C2                      I2C2_NS
+#define I2C2_BASE                 I2C2_BASE_NS
+
+#define I2C3                      I2C3_NS
+#define I2C3_BASE                 I2C3_BASE_NS
+
+#define I2C4                      I2C4_NS
+#define I2C4_BASE                 I2C4_BASE_NS
+
+#define I3C1                      I3C1_NS
+#define I3C1_BASE                 I3C1_BASE_NS
+
+#define I3C2                      I3C2_NS
+#define I3C2_BASE                 I3C2_BASE_NS
+
+#define ICACHE                    ICACHE_NS
+#define ICACHE_BASE               ICACHE_BASE_NS
+
+#define IWDG                      IWDG_NS
+#define IWDG_BASE                 IWDG_BASE_NS
+
+#define JPEG                      JPEG_NS
+#define JPEG_BASE                 JPEG_BASE_NS
+
+#define LPTIM1                    LPTIM1_NS
+#define LPTIM1_BASE               LPTIM1_BASE_NS
+
+#define LPTIM2                    LPTIM2_NS
+#define LPTIM2_BASE               LPTIM2_BASE_NS
+
+#define LPTIM3                    LPTIM3_NS
+#define LPTIM3_BASE               LPTIM3_BASE_NS
+
+#define LPTIM4                    LPTIM4_NS
+#define LPTIM4_BASE               LPTIM4_BASE_NS
+
+#define LPTIM5                    LPTIM5_NS
+#define LPTIM5_BASE               LPTIM5_BASE_NS
+
+#define LPUART1                   LPUART1_NS
+#define LPUART1_BASE              LPUART1_BASE_NS
+
+#define LTDC                      LTDC_NS
+#define LTDC_BASE                 LTDC_BASE_NS
+
+#define LTDC_Layer1               LTDC_Layer1_NS
+#define LTDC_Layer1_BASE          LTDC_Layer1_BASE_NS
+
+#define LTDC_Layer2               LTDC_Layer2_NS
+#define LTDC_Layer2_BASE          LTDC_Layer2_BASE_NS
+
+#define MCE1                      MCE1_NS
+#define MCE1_BASE                 MCE1_BASE_NS
+
+#define MCE1_REGION1              MCE1_REGION1_NS
+#define MCE1_REGION1_BASE         MCE1_REGION1_BASE_NS
+
+#define MCE1_REGION2              MCE1_REGION2_NS
+#define MCE1_REGION2_BASE         MCE1_REGION2_BASE_NS
+
+#define MCE1_REGION3              MCE1_REGION3_NS
+#define MCE1_REGION3_BASE         MCE1_REGION3_BASE_NS
+
+#define MCE1_REGION4              MCE1_REGION4_NS
+#define MCE1_REGION4_BASE         MCE1_REGION4_BASE_NS
+
+#define MCE1_CONTEXT1             MCE1_CONTEXT1_NS
+#define MCE1_CONTEXT1_BASE        MCE1_CONTEXT1_BASE_NS
+
+#define MCE1_CONTEXT2             MCE1_CONTEXT2_NS
+#define MCE1_CONTEXT2_BASE        MCE1_CONTEXT2_BASE_NS
+
+#define MCE2                      MCE2_NS
+#define MCE2_BASE                 MCE2_BASE_NS
+
+#define MCE2_REGION1              MCE2_REGION1_NS
+#define MCE2_REGION1_BASE         MCE2_REGION1_BASE_NS
+
+#define MCE2_REGION2              MCE2_REGION2_NS
+#define MCE2_REGION2_BASE         MCE2_REGION2_BASE_NS
+
+#define MCE2_REGION3              MCE2_REGION3_NS
+#define MCE2_REGION3_BASE         MCE2_REGION3_BASE_NS
+
+#define MCE2_REGION4              MCE2_REGION4_NS
+#define MCE2_REGION4_BASE         MCE2_REGION4_BASE_NS
+
+#define MCE2_CONTEXT1             MCE2_CONTEXT1_NS
+#define MCE2_CONTEXT1_BASE        MCE2_CONTEXT1_BASE_NS
+
+#define MCE2_CONTEXT2             MCE2_CONTEXT2_NS
+#define MCE2_CONTEXT2_BASE        MCE2_CONTEXT2_BASE_NS
+
+#define MCE3                      MCE3_NS
+#define MCE3_BASE                 MCE3_BASE_NS
+
+#define MCE3_REGION1              MCE3_REGION1_NS
+#define MCE3_REGION1_BASE         MCE3_REGION1_BASE_NS
+
+#define MCE3_REGION2              MCE3_REGION2_NS
+#define MCE3_REGION2_BASE         MCE3_REGION2_BASE_NS
+
+#define MCE3_REGION3              MCE3_REGION3_NS
+#define MCE3_REGION3_BASE         MCE3_REGION3_BASE_NS
+
+#define MCE3_REGION4              MCE3_REGION4_NS
+#define MCE3_REGION4_BASE         MCE3_REGION4_BASE_NS
+
+#define MCE3_CONTEXT1             MCE3_CONTEXT1_NS
+#define MCE3_CONTEXT1_BASE        MCE3_CONTEXT1_BASE_NS
+
+#define MCE3_CONTEXT2             MCE3_CONTEXT2_NS
+#define MCE3_CONTEXT2_BASE        MCE3_CONTEXT2_BASE_NS
+
+#define MCE4                      MCE4_NS
+#define MCE4_BASE                 MCE4_BASE_NS
+
+#define MCE4_REGION1              MCE4_REGION1_NS
+#define MCE4_REGION1_BASE         MCE4_REGION1_BASE_NS
+
+#define MCE4_REGION2              MCE4_REGION2_NS
+#define MCE4_REGION2_BASE         MCE4_REGION2_BASE_NS
+
+#define MCE4_REGION3              MCE4_REGION3_NS
+#define MCE4_REGION3_BASE         MCE4_REGION3_BASE_NS
+
+#define MCE4_REGION4              MCE4_REGION4_NS
+#define MCE4_REGION4_BASE         MCE4_REGION4_BASE_NS
+
+#define MCE4_CONTEXT1             MCE4_CONTEXT1_NS
+#define MCE4_CONTEXT1_BASE        MCE4_CONTEXT1_BASE_NS
+
+#define MCE4_CONTEXT2             MCE4_CONTEXT2_NS
+#define MCE4_CONTEXT2_BASE        MCE4_CONTEXT2_BASE_NS
+
+#define MDF1                      MDF1_NS
+#define MDF1_BASE                 MDF1_BASE_NS
+
+#define MDF1_Filter0              MDF1_Filter0_NS
+#define MDF1_Filter0_BASE         MDF1_Filter0_BASE_NS
+
+#define MDF1_Filter1              MDF1_Filter1_NS
+#define MDF1_Filter1_BASE         MDF1_Filter1_BASE_NS
+
+#define MDF1_Filter2              MDF1_Filter2_NS
+#define MDF1_Filter2_BASE         MDF1_Filter2_BASE_NS
+
+#define MDF1_Filter3              MDF1_Filter3_NS
+#define MDF1_Filter3_BASE         MDF1_Filter3_BASE_NS
+
+#define MDF1_Filter4              MDF1_Filter4_NS
+#define MDF1_Filter4_BASE         MDF1_Filter4_BASE_NS
+
+#define MDF1_Filter5              MDF1_Filter5_NS
+#define MDF1_Filter5_BASE         MDF1_Filter5_BASE_NS
+
+#define MDIOS                     MDIOS_NS
+#define MDIOS_BASE                MDIOS_BASE_NS
+
+#define NPU_PRESENT
+#define NPU_BASE                  NPU_BASE_NS
+
+#define PKA                       PKA_NS
+#define PKA_BASE                  PKA_BASE_NS
+
+#define PSSI                      PSSI_NS
+#define PSSI_BASE                 PSSI_BASE_NS
+
+#define PWR                       PWR_NS
+#define PWR_BASE                  PWR_BASE_NS
+
+#define RAMCFG                    RAMCFG_NS
+#define RAMCFG_BASE               RAMCFG_BASE_NS
+
+#define RAMCFG_SRAM1_AXI          RAMCFG_SRAM1_AXI_NS
+#define RAMCFG_SRAM1_AXI_BASE     RAMCFG_SRAM1_AXI_BASE_NS
+
+#define RAMCFG_SRAM2_AXI          RAMCFG_SRAM2_AXI_NS
+#define RAMCFG_SRAM2_AXI_BASE     RAMCFG_SRAM2_AXI_BASE_NS
+
+#define RAMCFG_SRAM3_AXI          RAMCFG_SRAM3_AXI_NS
+#define RAMCFG_SRAM3_AXI_BASE     RAMCFG_SRAM3_AXI_BASE_NS
+
+#define RAMCFG_SRAM4_AXI          RAMCFG_SRAM4_AXI_NS
+#define RAMCFG_SRAM4_AXI_BASE     RAMCFG_SRAM4_AXI_BASE_NS
+
+#define RAMCFG_SRAM5_AXI          RAMCFG_SRAM5_AXI_NS
+#define RAMCFG_SRAM5_AXI_BASE     RAMCFG_SRAM5_AXI_BASE_NS
+
+#define RAMCFG_SRAM6_AXI          RAMCFG_SRAM6_AXI_NS
+#define RAMCFG_SRAM6_AXI_BASE     RAMCFG_SRAM6_AXI_BASE_NS
+
+#define RAMCFG_SRAM1_AHB          RAMCFG_SRAM1_AHB_NS
+#define RAMCFG_SRAM1_AHB_BASE     RAMCFG_SRAM1_AHB_BASE_NS
+
+#define RAMCFG_SRAM2_AHB          RAMCFG_SRAM2_AHB_NS
+#define RAMCFG_SRAM2_AHB_BASE     RAMCFG_SRAM2_AHB_BASE_NS
+
+#define RAMCFG_VENC_RAM           RAMCFG_VENC_RAM_NS
+#define RAMCFG_VENC_RAM_BASE      RAMCFG_VENC_RAM_BASE_NS
+
+#define RAMCFG_BKPSRAM            RAMCFG_BKPSRAM_NS
+#define RAMCFG_BKPSRAM_BASE       RAMCFG_BKPSRAM_BASE_NS
+
+#define RAMCFG_FLEXRAM            RAMCFG_FLEXRAM_NS
+#define RAMCFG_FLEXRAM_BASE       RAMCFG_FLEXRAM_BASE_NS
+
+#define RCC                       RCC_NS
+#define RCC_BASE                  RCC_BASE_NS
+
+#define RIFSC                     RIFSC_NS
+#define RIFSC_BASE                RIFSC_BASE_NS
+
+#define RISAF1                    RISAF1_NS
+#define RISAF1_BASE               RISAF1_BASE_NS
+
+#define RISAF2                    RISAF2_NS
+#define RISAF2_BASE               RISAF2_BASE_NS
+
+#define RISAF3                    RISAF3_NS
+#define RISAF3_BASE               RISAF3_BASE_NS
+
+#define RISAF4                    RISAF4_NS
+#define RISAF4_BASE               RISAF4_BASE_NS
+
+#define RISAF5                    RISAF5_NS
+#define RISAF5_BASE               RISAF5_BASE_NS
+
+#define RISAF6                    RISAF6_NS
+#define RISAF6_BASE               RISAF6_BASE_NS
+
+#define RISAF7                    RISAF7_NS
+#define RISAF7_BASE               RISAF7_BASE_NS
+
+#define RISAF8                    RISAF8_NS
+#define RISAF8_BASE               RISAF8_BASE_NS
+
+#define RISAF9                    RISAF9_NS
+#define RISAF9_BASE               RISAF9_BASE_NS
+
+#define RISAF11                   RISAF11_NS
+#define RISAF11_BASE              RISAF11_BASE_NS
+
+#define RISAF12                   RISAF12_NS
+#define RISAF12_BASE              RISAF12_BASE_NS
+
+#define RISAF13                   RISAF13_NS
+#define RISAF13_BASE              RISAF13_BASE_NS
+
+#define RISAF14                   RISAF14_NS
+#define RISAF14_BASE              RISAF14_BASE_NS
+
+#define RISAF15                   RISAF15_NS
+#define RISAF15_BASE              RISAF15_BASE_NS
+
+#define RISAF21                   RISAF21_NS
+#define RISAF21_BASE              RISAF21_BASE_NS
+
+#define RISAF22                   RISAF22_NS
+#define RISAF22_BASE              RISAF22_BASE_NS
+
+#define RISAF23                   RISAF23_NS
+#define RISAF23_BASE              RISAF23_BASE_NS
+
+#define RNG                       RNG_NS
+#define RNG_BASE                  RNG_BASE_NS
+
+#define RTC                       RTC_NS
+#define RTC_BASE                  RTC_BASE_NS
+
+#define SAES                      SAES_NS
+#define SAES_BASE                 SAES_BASE_NS
+
+#define SAI1                      SAI1_NS
+#define SAI1_BASE                 SAI1_BASE_NS
+
+#define SAI1_Block_A              SAI1_Block_A_NS
+#define SAI1_Block_A_BASE         SAI1_Block_A_BASE_NS
+
+#define SAI1_Block_B              SAI1_Block_B_NS
+#define SAI1_Block_B_BASE         SAI1_Block_B_BASE_NS
+
+#define SAI2                      SAI2_NS
+#define SAI2_BASE                 SAI2_BASE_NS
+
+#define SAI2_Block_A              SAI2_Block_A_NS
+#define SAI2_Block_A_BASE         SAI2_Block_A_BASE_NS
+
+#define SAI2_Block_B              SAI2_Block_B_NS
+#define SAI2_Block_B_BASE         SAI2_Block_B_BASE_NS
+
+#define SDMMC1                    SDMMC1_NS
+#define SDMMC1_BASE               SDMMC1_BASE_NS
+
+#define SDMMC2                    SDMMC2_NS
+#define SDMMC2_BASE               SDMMC2_BASE_NS
+
+#define SPDIFRX                   SPDIFRX_NS
+#define SPDIFRX_BASE              SPDIFRX_BASE_NS
+
+#define SPI1                      SPI1_NS
+#define SPI1_BASE                 SPI1_BASE_NS
+
+#define SPI2                      SPI2_NS
+#define SPI2_BASE                 SPI2_BASE_NS
+
+#define SPI3                      SPI3_NS
+#define SPI3_BASE                 SPI3_BASE_NS
+
+#define SPI4                      SPI4_NS
+#define SPI4_BASE                 SPI4_BASE_NS
+
+#define SPI5                      SPI5_NS
+#define SPI5_BASE                 SPI5_BASE_NS
+
+#define SPI6                      SPI6_NS
+#define SPI6_BASE                 SPI6_BASE_NS
+
+#define SRAMCAN_BASE              SRAMCAN_BASE_NS
+
+#define SYSCFG                    SYSCFG_NS
+#define SYSCFG_BASE               SYSCFG_BASE_NS
+
+#define TAMP                      TAMP_NS
+#define TAMP_BASE                 TAMP_BASE_NS
+
+#define TIM1                      TIM1_NS
+#define TIM1_BASE                 TIM1_BASE_NS
+
+#define TIM2                      TIM2_NS
+#define TIM2_BASE                 TIM2_BASE_NS
+
+#define TIM3                      TIM3_NS
+#define TIM3_BASE                 TIM3_BASE_NS
+
+#define TIM4                      TIM4_NS
+#define TIM4_BASE                 TIM4_BASE_NS
+
+#define TIM5                      TIM5_NS
+#define TIM5_BASE                 TIM5_BASE_NS
+
+#define TIM6                      TIM6_NS
+#define TIM6_BASE                 TIM6_BASE_NS
+
+#define TIM7                      TIM7_NS
+#define TIM7_BASE                 TIM7_BASE_NS
+
+#define TIM8                      TIM8_NS
+#define TIM8_BASE                 TIM8_BASE_NS
+
+#define TIM9                      TIM9_NS
+#define TIM9_BASE                 TIM9_BASE_NS
+
+#define TIM10                     TIM10_NS
+#define TIM10_BASE                TIM10_BASE_NS
+
+#define TIM11                     TIM11_NS
+#define TIM11_BASE                TIM11_BASE_NS
+
+#define TIM12                     TIM12_NS
+#define TIM12_BASE                TIM12_BASE_NS
+
+#define TIM13                     TIM13_NS
+#define TIM13_BASE                TIM13_BASE_NS
+
+#define TIM14                     TIM14_NS
+#define TIM14_BASE                TIM14_BASE_NS
+
+#define TIM15                     TIM15_NS
+#define TIM15_BASE                TIM15_BASE_NS
+
+#define TIM16                     TIM16_NS
+#define TIM16_BASE                TIM16_BASE_NS
+
+#define TIM17                     TIM17_NS
+#define TIM17_BASE                TIM17_BASE_NS
+
+#define TIM18                     TIM18_NS
+#define TIM18_BASE                TIM18_BASE_NS
+
+#define UART4                     UART4_NS
+#define UART4_BASE                UART4_BASE_NS
+
+#define UART5                     UART5_NS
+#define UART5_BASE                UART5_BASE_NS
+
+#define UART7                     UART7_NS
+#define UART7_BASE                UART7_BASE_NS
+
+#define UART8                     UART8_NS
+#define UART8_BASE                UART8_BASE_NS
+
+#define UART9                     UART9_NS
+#define UART9_BASE                UART9_BASE_NS
+
+#define UCPD1                     UCPD1_NS
+#define UCPD1_BASE                UCPD1_BASE_NS
+
+#define USART1                    USART1_NS
+#define USART1_BASE               USART1_BASE_NS
+
+#define USART2                    USART2_NS
+#define USART2_BASE               USART2_BASE_NS
+
+#define USART3                    USART3_NS
+#define USART3_BASE               USART3_BASE_NS
+
+#define USART6                    USART6_NS
+#define USART6_BASE               USART6_BASE_NS
+
+#define USART10                   USART10_NS
+#define USART10_BASE              USART10_BASE_NS
+
+#define USB1_OTG_HS               USB1_OTG_HS_NS
+#define USB1_OTG_HS_BASE          USB1_OTG_HS_BASE_NS
+
+#define USB2_OTG_HS               USB2_OTG_HS_NS
+#define USB2_OTG_HS_BASE          USB2_OTG_HS_BASE_NS
+
+#define USB1_HS_PHYC              USB1_HS_PHYC_NS
+#define USB1_HS_PHYC_BASE         USB1_HS_PHYC_BASE_NS
+
+#define USB2_HS_PHYC              USB2_HS_PHYC_NS
+#define USB2_HS_PHYC_BASE         USB2_HS_PHYC_BASE_NS
+
+#define VENC                      VENC_NS
+#define VENC_BASE                 VENC_BASE_NS
+
+#define VREFBUF                   VREFBUF_NS
+#define VREFBUF_BASE              VREFBUF_BASE_NS
+
+#define WWDG                      WWDG_NS
+#define WWDG_BASE                 WWDG_BASE_NS
+
+#define XSPI1                     XSPI1_NS
+
+#define XSPI2                     XSPI2_NS
+
+#define XSPI3                     XSPI3_NS
+
+#define XSPIM                     XSPIM_NS
+#define XSPIM_BASE                XSPIM_BASE_NS
+
+/*!< Unique device ID register base address */
+#define UID_BASE                  UID_BASE_NS
+
+/*!< Revision ID base address */
+#define REVID_BASE                REVID_BASE_NS
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Timing_Definition
+  * @{
+  */
+
+#define LSI_STARTUP_TIME                16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter (ADC)                   */
+/*                                                                            */
+/******************************************************************************/
+
+/* Specific device feature definitions */
+#define ADC_MULTIMODE_SUPPORT         /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)
+#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)
+#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)
+#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)
+#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)
+#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)
+#define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)
+#define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)
+#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)
+#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)
+#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)
+#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)
+#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)
+#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)
+#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)
+#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)
+#define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)
+#define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)
+#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)
+#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)
+#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)
+#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)
+#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)
+#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)
+#define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)
+#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)
+#define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_DEEPPWD_Pos             (29U)
+#define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)
+#define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)
+#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR1 register  ******************/
+#define ADC_CFGR1_DMNGT_Pos            (0U)
+#define ADC_CFGR1_DMNGT_Msk            (0x3UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000003 */
+#define ADC_CFGR1_DMNGT                ADC_CFGR1_DMNGT_Msk                     /*!< ADC data management configuration */
+#define ADC_CFGR1_DMNGT_0              (0x1UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR1_DMNGT_1              (0x2UL << ADC_CFGR1_DMNGT_Pos)          /*!< 0x00000002 */
+
+#define ADC_CFGR1_RES_Pos              (2U)
+#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x0000000C */
+#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
+#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
+
+#define ADC_CFGR1_EXTSEL_Pos           (5U)
+#define ADC_CFGR1_EXTSEL_Msk           (0x1FUL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x000003E0 */
+#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
+#define ADC_CFGR1_EXTSEL_0             (0x01UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_CFGR1_EXTSEL_1             (0x02UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_2             (0x04UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_3             (0x08UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000100 */
+#define ADC_CFGR1_EXTSEL_4             (0x10UL << ADC_CFGR1_EXTSEL_Pos)        /*!< 0x00000200 */
+
+#define ADC_CFGR1_EXTEN_Pos            (10U)
+#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
+
+#define ADC_CFGR1_OVRMOD_Pos           (12U)
+#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
+#define ADC_CFGR1_CONT_Pos             (13U)
+#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
+#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR1_AUTDLY_Pos           (14U)
+#define ADC_CFGR1_AUTDLY_Msk           (0x1UL << ADC_CFGR1_AUTDLY_Pos)         /*!< 0x00004000 */
+#define ADC_CFGR1_AUTDLY               ADC_CFGR1_AUTDLY_Msk                    /*!< ADC low power auto wait */
+
+#define ADC_CFGR1_DISCEN_Pos           (16U)
+#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR1_DISCNUM_Pos          (17U)
+#define ADC_CFGR1_DISCNUM_Msk          (0x7UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x000E0000 */
+#define ADC_CFGR1_DISCNUM              ADC_CFGR1_DISCNUM_Msk                   /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR1_DISCNUM_0            (0x1UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00020000 */
+#define ADC_CFGR1_DISCNUM_1            (0x2UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00040000 */
+#define ADC_CFGR1_DISCNUM_2            (0x4UL << ADC_CFGR1_DISCNUM_Pos)        /*!< 0x00080000 */
+
+#define ADC_CFGR1_JDISCEN_Pos          (20U)
+#define ADC_CFGR1_JDISCEN_Msk          (0x1UL << ADC_CFGR1_JDISCEN_Pos)        /*!< 0x00100000 */
+#define ADC_CFGR1_JDISCEN              ADC_CFGR1_JDISCEN_Msk                   /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CFGR1_AWD1SGL_Pos          (22U)
+#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
+#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR1_AWD1EN_Pos           (23U)
+#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
+#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR1_JAWD1EN_Pos          (24U)
+#define ADC_CFGR1_JAWD1EN_Msk          (0x1UL << ADC_CFGR1_JAWD1EN_Pos)        /*!< 0x01000000 */
+#define ADC_CFGR1_JAWD1EN              ADC_CFGR1_JAWD1EN_Msk                   /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR1_JAUTO_Pos            (25U)
+#define ADC_CFGR1_JAUTO_Msk            (0x1UL << ADC_CFGR1_JAUTO_Pos)          /*!< 0x02000000 */
+#define ADC_CFGR1_JAUTO                ADC_CFGR1_JAUTO_Msk                     /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR1_AWD1CH_Pos           (26U)
+#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
+#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
+#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
+#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
+#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
+#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)
+#define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)
+#define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)
+#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)
+#define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)
+#define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+#define ADC_CFGR2_BULB_Pos             (13U)
+#define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)            /*!< 0x00002000 */
+#define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                       /*!< ADC bulb sampling mode */
+
+#define ADC_CFGR2_SWTRIG_Pos           (14U)
+#define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)          /*!< 0x00004000 */
+#define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                     /*!< ADC software trigger bit for sampling time control trigger mode */
+
+#define ADC_CFGR2_SMPTRIG_Pos          (15U)
+#define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)         /*!< 0x00008000 */
+#define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                    /*!< ADC sampling time control trigger mode */
+
+#define ADC_CFGR2_OVSR_Pos             (16U)
+#define ADC_CFGR2_OVSR_Msk             (0x3FFUL << ADC_CFGR2_OVSR_Pos)          /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                       /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x001UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1               (0x002UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2               (0x004UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3               (0x008UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4               (0x010UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5               (0x020UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6               (0x040UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7               (0x080UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8               (0x100UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9               (0x200UL << ADC_CFGR2_OVSR_Pos)          /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos           (28U)
+#define ADC_CFGR2_LSHIFT_Msk           (0xFUL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT               ADC_CFGR2_LSHIFT_Msk                     /*!< ADC left shift factor */
+#define ADC_CFGR2_LSHIFT_0             (0x1UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1             (0x2UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2             (0x4UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3             (0x8UL << ADC_CFGR2_LSHIFT_Pos)          /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)
+#define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)
+#define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)
+#define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)
+#define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)
+#define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)
+#define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)
+#define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)
+#define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)
+#define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)
+#define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)
+#define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)
+#define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)
+#define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)
+#define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)
+#define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)
+#define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)
+#define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)
+#define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)
+#define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos            (27U)
+#define ADC_SMPR2_SMP19_Msk            (0x7UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                ADC_SMPR2_SMP19_Msk                     /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0              (0x1UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1              (0x2UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2              (0x4UL << ADC_SMPR2_SMP19_Pos)          /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  *****************/
+#define ADC_PCSEL_PCSEL_Pos            (0U)
+#define ADC_PCSEL_PCSEL_Msk            (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                ADC_PCSEL_PCSEL_Msk                   /*!< ADC channel preselection */
+#define ADC_PCSEL_PCSEL_0              (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1              (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2              (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3              (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4              (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5              (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6              (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7              (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8              (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9              (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10             (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11             (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12             (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13             (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14             (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15             (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16             (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17             (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18             (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19             (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)
+#define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)
+#define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)
+#define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)
+#define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)
+#define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)
+#define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)
+#define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)
+#define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)
+#define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)
+#define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)
+#define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)
+#define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)
+#define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)
+#define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)
+#define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)
+#define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)
+#define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)
+#define ADC_DR_RDATA_Msk               (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)      /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x00000001UL << ADC_DR_RDATA_Pos)      /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x00000002UL << ADC_DR_RDATA_Pos)      /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x00000004UL << ADC_DR_RDATA_Pos)      /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x00000008UL << ADC_DR_RDATA_Pos)      /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x00000010UL << ADC_DR_RDATA_Pos)      /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x00000020UL << ADC_DR_RDATA_Pos)      /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x00000040UL << ADC_DR_RDATA_Pos)      /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x00000080UL << ADC_DR_RDATA_Pos)      /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x00000100UL << ADC_DR_RDATA_Pos)      /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x00000200UL << ADC_DR_RDATA_Pos)      /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x00000400UL << ADC_DR_RDATA_Pos)      /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x00000800UL << ADC_DR_RDATA_Pos)      /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x00001000UL << ADC_DR_RDATA_Pos)      /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x00002000UL << ADC_DR_RDATA_Pos)      /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x00004000UL << ADC_DR_RDATA_Pos)      /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x00008000UL << ADC_DR_RDATA_Pos)      /*!< 0x00008000 */
+#define ADC_DR_RDATA_16                (0x00010000UL << ADC_DR_RDATA_Pos)      /*!< 0x00010000 */
+#define ADC_DR_RDATA_17                (0x00020000UL << ADC_DR_RDATA_Pos)      /*!< 0x00020000 */
+#define ADC_DR_RDATA_18                (0x00040000UL << ADC_DR_RDATA_Pos)      /*!< 0x00040000 */
+#define ADC_DR_RDATA_19                (0x00080000UL << ADC_DR_RDATA_Pos)      /*!< 0x00080000 */
+#define ADC_DR_RDATA_20                (0x00100000UL << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
+#define ADC_DR_RDATA_21                (0x00200000UL << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
+#define ADC_DR_RDATA_22                (0x00400000UL << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
+#define ADC_DR_RDATA_23                (0x00800000UL << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
+#define ADC_DR_RDATA_24                (0x01000000UL << ADC_DR_RDATA_Pos)      /*!< 0x01000000 */
+#define ADC_DR_RDATA_25                (0x02000000UL << ADC_DR_RDATA_Pos)      /*!< 0x02000000 */
+#define ADC_DR_RDATA_26                (0x04000000UL << ADC_DR_RDATA_Pos)      /*!< 0x04000000 */
+#define ADC_DR_RDATA_27                (0x08000000UL << ADC_DR_RDATA_Pos)      /*!< 0x08000000 */
+#define ADC_DR_RDATA_28                (0x10000000UL << ADC_DR_RDATA_Pos)      /*!< 0x10000000 */
+#define ADC_DR_RDATA_29                (0x20000000UL << ADC_DR_RDATA_Pos)      /*!< 0x20000000 */
+#define ADC_DR_RDATA_30                (0x40000000UL << ADC_DR_RDATA_Pos)      /*!< 0x40000000 */
+#define ADC_DR_RDATA_31                (0x80000000UL << ADC_DR_RDATA_Pos)      /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)
+#define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)
+#define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x01UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x02UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x04UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x08UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos            (7U)
+#define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos              (9U)
+#define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos              (15U)
+#define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos              (21U)
+#define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (27U)
+#define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR1 register  ***************/
+#define ADC_OFCFGR1_POSOFF_Pos         (24U)
+#define ADC_OFCFGR1_POSOFF_Msk         (0x01UL << ADC_OFCFGR1_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR1_POSOFF             ADC_OFCFGR1_POSOFF_Msk                  /*!< ADC offset instance 1 positive offset enable */
+
+#define ADC_OFCFGR1_USAT_Pos           (25U)
+#define ADC_OFCFGR1_USAT_Msk           (0x01UL << ADC_OFCFGR1_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR1_USAT               ADC_OFCFGR1_USAT_Msk                    /*!< ADC offset instance 1  unsigned saturation value */
+
+#define ADC_OFCFGR1_SSAT_Pos           (26U)
+#define ADC_OFCFGR1_SSAT_Msk           (0x01UL << ADC_OFCFGR1_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR1_SSAT               ADC_OFCFGR1_SSAT_Msk                    /*!< ADC offset instance 1 signed satuaration enable */
+
+#define ADC_OFCFGR1_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR1_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR1_OFFSET_CH          ADC_OFCFGR1_OFFSET_CH_Msk               /*!< ADC offset instance 1 channel selection */
+#define ADC_OFCFGR1_OFFSET_CH_0        (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR1_OFFSET_CH_1        (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR1_OFFSET_CH_2        (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR1_OFFSET_CH_3        (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR1_OFFSET_CH_4        (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR2 register  ***************/
+#define ADC_OFCFGR2_POSOFF_Pos         (24U)
+#define ADC_OFCFGR2_POSOFF_Msk         (0x01UL << ADC_OFCFGR2_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR2_POSOFF             ADC_OFCFGR2_POSOFF_Msk                  /*!< ADC offset instance 2 positive offset enable */
+
+#define ADC_OFCFGR2_USAT_Pos           (25U)
+#define ADC_OFCFGR2_USAT_Msk           (0x01UL << ADC_OFCFGR2_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR2_USAT               ADC_OFCFGR2_USAT_Msk                    /*!< ADC offset instance 2 unsigned saturation value */
+
+#define ADC_OFCFGR2_SSAT_Pos           (26U)
+#define ADC_OFCFGR2_SSAT_Msk           (0x01UL << ADC_OFCFGR2_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR2_SSAT               ADC_OFCFGR2_SSAT_Msk                    /*!< ADC offset instance 2 signed satuaration enable */
+
+#define ADC_OFCFGR2_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR2_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR2_OFFSET_CH          ADC_OFCFGR2_OFFSET_CH_Msk               /*!< ADC offset instance 2 channel selection */
+#define ADC_OFCFGR2_OFFSET_CH_0        (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR2_OFFSET_CH_1        (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR2_OFFSET_CH_2        (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR2_OFFSET_CH_3        (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR2_OFFSET_CH_4        (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR3 register  ***************/
+#define ADC_OFCFGR3_POSOFF_Pos         (24U)
+#define ADC_OFCFGR3_POSOFF_Msk         (0x01UL << ADC_OFCFGR3_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR3_POSOFF             ADC_OFCFGR3_POSOFF_Msk                  /*!< ADC offset instance 3 positive offset enable */
+
+#define ADC_OFCFGR3_USAT_Pos           (25U)
+#define ADC_OFCFGR3_USAT_Msk           (0x01UL << ADC_OFCFGR3_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR3_USAT               ADC_OFCFGR3_USAT_Msk                    /*!< ADC offset instance 3 unsigned saturation value */
+
+#define ADC_OFCFGR3_SSAT_Pos           (26U)
+#define ADC_OFCFGR3_SSAT_Msk           (0x01UL << ADC_OFCFGR3_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR3_SSAT               ADC_OFCFGR3_SSAT_Msk                    /*!< ADC offset instance 3 signed satuaration enable */
+
+#define ADC_OFCFGR3_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR3_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR3_OFFSET_CH          ADC_OFCFGR3_OFFSET_CH_Msk               /*!< ADC offset instance 3 channel selection for the data offset */
+#define ADC_OFCFGR3_OFFSET_CH_0        (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR3_OFFSET_CH_1        (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR3_OFFSET_CH_2        (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR3_OFFSET_CH_3        (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR3_OFFSET_CH_4        (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFCFGR4 register  ***************/
+#define ADC_OFCFGR4_POSOFF_Pos         (24U)
+#define ADC_OFCFGR4_POSOFF_Msk         (0x01UL << ADC_OFCFGR4_POSOFF_Pos)      /*!< 0x01000000 */
+#define ADC_OFCFGR4_POSOFF             ADC_OFCFGR4_POSOFF_Msk                  /*!< ADC offset instance 4 positive offset enable */
+
+#define ADC_OFCFGR4_USAT_Pos           (25U)
+#define ADC_OFCFGR4_USAT_Msk           (0x01UL << ADC_OFCFGR4_USAT_Pos)        /*!< 0x02000000 */
+#define ADC_OFCFGR4_USAT               ADC_OFCFGR4_USAT_Msk                    /*!< ADC offset instance 4 unsigned saturation value */
+
+#define ADC_OFCFGR4_SSAT_Pos           (26U)
+#define ADC_OFCFGR4_SSAT_Msk           (0x01UL << ADC_OFCFGR4_SSAT_Pos)        /*!< 0x04000000 */
+#define ADC_OFCFGR4_SSAT               ADC_OFCFGR4_SSAT_Msk                    /*!< ADC offset instance 4 signed satuaration enable */
+
+#define ADC_OFCFGR4_OFFSET_CH_Pos      (27U)
+#define ADC_OFCFGR4_OFFSET_CH_Msk      (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos)   /*!< 0xF8000000 */
+#define ADC_OFCFGR4_OFFSET_CH          ADC_OFCFGR4_OFFSET_CH_Msk               /*!< ADC offset instance 4 channel selection for the data offset */
+#define ADC_OFCFGR4_OFFSET_CH_0        (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x08000000 */
+#define ADC_OFCFGR4_OFFSET_CH_1        (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x10000000 */
+#define ADC_OFCFGR4_OFFSET_CH_2        (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x20000000 */
+#define ADC_OFCFGR4_OFFSET_CH_3        (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x40000000 */
+#define ADC_OFCFGR4_OFFSET_CH_4        (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET_Pos            (0U)
+#define ADC_OFR1_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR1_OFFSET                ADC_OFR1_OFFSET_Msk                     /*!< ADC offset instance 1 offset level */
+#define ADC_OFR1_OFFSET_0              (0x0000001UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET_1              (0x0000002UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET_2              (0x0000004UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET_3              (0x0000008UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET_4              (0x0000010UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET_5              (0x0000020UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET_6              (0x0000040UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET_7              (0x0000080UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET_8              (0x0000100UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET_9              (0x0000200UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET_10             (0x0000400UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET_11             (0x0000800UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET_12             (0x0001000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET_13             (0x0002000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET_14             (0x0004000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET_15             (0x0008000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET_16             (0x0010000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET_17             (0x0020000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET_18             (0x0040000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET_19             (0x0080000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET_20             (0x0100000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET_21             (0x0200000UL << ADC_OFR1_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET_Pos            (0U)
+#define ADC_OFR2_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR2_OFFSET                ADC_OFR2_OFFSET_Msk                     /*!< ADC offset instance 2 offset level */
+#define ADC_OFR2_OFFSET_0              (0x0000001UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET_1              (0x0000002UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET_2              (0x0000004UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET_3              (0x0000008UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET_4              (0x0000010UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET_5              (0x0000020UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET_6              (0x0000040UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET_7              (0x0000080UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET_8              (0x0000100UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET_9              (0x0000200UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET_10             (0x0000400UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET_11             (0x0000800UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET_12             (0x0001000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET_13             (0x0002000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET_14             (0x0004000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET_15             (0x0008000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET_16             (0x0010000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET_17             (0x0020000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET_18             (0x0040000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET_19             (0x0080000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET_20             (0x0100000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET_21             (0x0200000UL << ADC_OFR2_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET_Pos            (0U)
+#define ADC_OFR3_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR3_OFFSET                ADC_OFR3_OFFSET_Msk                     /*!< ADC offset instance 3 offset level */
+#define ADC_OFR3_OFFSET_0              (0x0000001UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET_1              (0x0000002UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET_2              (0x0000004UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET_3              (0x0000008UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET_4              (0x0000010UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET_5              (0x0000020UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET_6              (0x0000040UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET_7              (0x0000080UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET_8              (0x0000100UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET_9              (0x0000200UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET_10             (0x0000400UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET_11             (0x0000800UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET_12             (0x0001000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET_13             (0x0002000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET_14             (0x0004000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET_15             (0x0008000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET_16             (0x0010000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET_17             (0x0020000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET_18             (0x0040000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET_19             (0x0080000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET_20             (0x0100000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET_21             (0x0200000UL << ADC_OFR3_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET_Pos            (0U)
+#define ADC_OFR4_OFFSET_Msk            (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos)    /*!< 0x003FFFFF */
+#define ADC_OFR4_OFFSET                ADC_OFR4_OFFSET_Msk                     /*!< ADC offset instance 4 offset level */
+#define ADC_OFR4_OFFSET_0              (0x0000001UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET_1              (0x0000002UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET_2              (0x0000004UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET_3              (0x0000008UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET_4              (0x0000010UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET_5              (0x0000020UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET_6              (0x0000040UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET_7              (0x0000080UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET_8              (0x0000100UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET_9              (0x0000200UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET_10             (0x0000400UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET_11             (0x0000800UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET_12             (0x0001000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET_13             (0x0002000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET_14             (0x0004000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET_15             (0x0008000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET_16             (0x0010000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET_17             (0x0020000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET_18             (0x0040000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET_19             (0x0080000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET_20             (0x0100000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET_21             (0x0200000UL << ADC_OFR4_OFFSET_Pos)    /*!< 0x00200000 */
+
+/********************  Bit definition for ADC_GCOMP register  *****************/
+#define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
+#define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
+#define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< Gain compensation coefficient */
+#define ADC_GCOMP_GCOMP_Pos            (31U)
+#define ADC_GCOMP_GCOMP_Msk            (0x1UL << ADC_GCOMP_GCOMP_Pos)          /*!< 0x80000000 */
+#define ADC_GCOMP_GCOMP                ADC_GCOMP_GCOMP_Msk                     /*!< Gain compensation mode */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)
+#define ADC_JDR1_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x00000001UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x00000002UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x00000004UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x00000008UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x00000010UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x00000020UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x00000040UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x00000080UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x00000100UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x00000200UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x00000400UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x00000800UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x00001000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x00002000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x00004000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x00008000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16              (0x00010000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17              (0x00020000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18              (0x00040000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19              (0x00080000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20              (0x00100000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21              (0x00200000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22              (0x00400000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23              (0x00800000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24              (0x01000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25              (0x02000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26              (0x04000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27              (0x08000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28              (0x10000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29              (0x20000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30              (0x40000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31              (0x80000000UL << ADC_JDR1_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos             (0U)
+#define ADC_JDR2_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x00000001UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x00000002UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x00000004UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x00000008UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x00000010UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x00000020UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x00000040UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x00000080UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x00000100UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x00000200UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x00000400UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x00000800UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x00001000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x00002000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x00004000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x00008000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16              (0x00010000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17              (0x00020000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18              (0x00040000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19              (0x00080000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20              (0x00100000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21              (0x00200000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22              (0x00400000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23              (0x00800000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24              (0x01000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25              (0x02000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26              (0x04000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27              (0x08000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28              (0x10000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29              (0x20000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30              (0x40000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31              (0x80000000UL << ADC_JDR2_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos             (0U)
+#define ADC_JDR3_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x00000001UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x00000002UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x00000004UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x00000008UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x00000010UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x00000020UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x00000040UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x00000080UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x00000100UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x00000200UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x00000400UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x00000800UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x00001000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x00002000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x00004000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x00008000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16              (0x00010000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17              (0x00020000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18              (0x00040000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19              (0x00080000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20              (0x00100000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21              (0x00200000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22              (0x00400000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23              (0x00800000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24              (0x01000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25              (0x02000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26              (0x04000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27              (0x08000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28              (0x10000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29              (0x20000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30              (0x40000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31              (0x80000000UL << ADC_JDR3_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos             (0U)
+#define ADC_JDR4_JDATA_Msk             (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x00000001UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x00000002UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x00000004UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x00000008UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x00000010UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x00000020UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x00000040UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x00000080UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x00000100UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x00000200UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x00000400UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x00000800UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x00001000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x00002000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x00004000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x00008000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16              (0x00010000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17              (0x00020000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18              (0x00040000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19              (0x00080000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20              (0x00100000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21              (0x00200000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22              (0x00400000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23              (0x00800000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24              (0x01000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25              (0x02000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26              (0x04000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27              (0x08000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28              (0x10000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29              (0x20000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30              (0x40000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31              (0x80000000UL << ADC_JDR4_JDATA_Pos)    /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)
+#define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)
+#define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19           (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD1TR_LT register  *************/
+#define ADC_AWD1LTR_LTR_Pos            (0U)
+#define ADC_AWD1LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1LTR_LTR                ADC_AWD1LTR_LTR_Msk                    /*!< ADC analog watchdog 1 threshold low */
+#define ADC_AWD1LTR_LTR_0              (0x000001UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1LTR_LTR_1              (0x000002UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1LTR_LTR_2              (0x000004UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1LTR_LTR_3              (0x000008UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1LTR_LTR_4              (0x000010UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1LTR_LTR_5              (0x000020UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1LTR_LTR_6              (0x000040UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1LTR_LTR_7              (0x000080UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1LTR_LTR_8              (0x000100UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1LTR_LTR_9              (0x000200UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1LTR_LTR_10             (0x000400UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1LTR_LTR_11             (0x000800UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1LTR_LTR_12             (0x001000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1LTR_LTR_13             (0x002000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1LTR_LTR_14             (0x004000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1LTR_LTR_15             (0x008000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1LTR_LTR_16             (0x010000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1LTR_LTR_17             (0x020000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1LTR_LTR_18             (0x040000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1LTR_LTR_19             (0x080000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1LTR_LTR_20             (0x100000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1LTR_LTR_21             (0x200000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1LTR_LTR_22             (0x400000UL << ADC_AWD1LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD1TR_HT register  *******************/
+#define ADC_AWD1HTR_HTR_Pos            (0U)
+#define ADC_AWD1HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD1HTR_HTR                ADC_AWD1HTR_HTR_Msk                    /*!< ADC analog watchdog 1 threshold high */
+#define ADC_AWD1HTR_HTR_0              (0x000001UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD1HTR_HTR_1              (0x000002UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD1HTR_HTR_2              (0x000004UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD1HTR_HTR_3              (0x000008UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD1HTR_HTR_4              (0x000010UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD1HTR_HTR_5              (0x000020UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD1HTR_HTR_6              (0x000040UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD1HTR_HTR_7              (0x000080UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD1HTR_HTR_8              (0x000100UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD1HTR_HTR_9              (0x000200UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD1HTR_HTR_10             (0x000400UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD1HTR_HTR_11             (0x000800UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD1HTR_HTR_12             (0x001000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD1HTR_HTR_13             (0x002000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD1HTR_HTR_14             (0x004000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD1HTR_HTR_15             (0x008000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD1HTR_HTR_16             (0x010000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD1HTR_HTR_17             (0x020000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD1HTR_HTR_18             (0x040000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD1HTR_HTR_19             (0x080000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD1HTR_HTR_20             (0x100000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD1HTR_HTR_21             (0x200000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD1HTR_HTR_22             (0x400000UL << ADC_AWD1HTR_HTR_Pos)    /*!< 0x00400000 */
+
+#define ADC_AWD1HTR_AWDFILT_Pos         (29U)
+#define ADC_AWD1HTR_AWDFILT_Msk         (0x7UL << ADC_AWD1HTR_AWDFILT_Pos)      /*!< 0x00000007 */
+#define ADC_AWD1HTR_AWDFILT             ADC_AWD1HTR_AWDFILT_Msk                 /*!< ADC analog watchdog 1 filtering */
+#define ADC_AWD1HTR_AWDFILT_0           (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */
+#define ADC_AWD1HTR_AWDFILT_1           (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */
+#define ADC_AWD1HTR_AWDFILT_2           (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */
+
+/********************  Bit definition for ADC_AWD2TR_LT register  *******************/
+#define ADC_AWD2LTR_LTR_Pos            (0U)
+#define ADC_AWD2LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2LTR_LTR                ADC_AWD2LTR_LTR_Msk                    /*!< ADC analog watchdog 2 threshold low */
+#define ADC_AWD2LTR_LTR_0              (0x000001UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2LTR_LTR_1              (0x000002UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2LTR_LTR_2              (0x000004UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2LTR_LTR_3              (0x000008UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2LTR_LTR_4              (0x000010UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2LTR_LTR_5              (0x000020UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2LTR_LTR_6              (0x000040UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2LTR_LTR_7              (0x000080UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2LTR_LTR_8              (0x000100UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2LTR_LTR_9              (0x000200UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2LTR_LTR_10             (0x000400UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2LTR_LTR_11             (0x000800UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2LTR_LTR_12             (0x001000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2LTR_LTR_13             (0x002000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2LTR_LTR_14             (0x004000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2LTR_LTR_15             (0x008000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2LTR_LTR_16             (0x010000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2LTR_LTR_17             (0x020000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2LTR_LTR_18             (0x040000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2LTR_LTR_19             (0x080000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2LTR_LTR_20             (0x100000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2LTR_LTR_21             (0x200000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2LTR_LTR_22             (0x400000UL << ADC_AWD2LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD2TR_HT register  *******************/
+#define ADC_AWD2HTR_HTR_Pos            (0U)
+#define ADC_AWD2HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD2HTR_HTR                ADC_AWD2HTR_HTR_Msk                    /*!< ADC analog watchdog 2 threshold high */
+#define ADC_AWD2HTR_HTR_0              (0x000001UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD2HTR_HTR_1              (0x000002UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD2HTR_HTR_2              (0x000004UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD2HTR_HTR_3              (0x000008UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD2HTR_HTR_4              (0x000010UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD2HTR_HTR_5              (0x000020UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD2HTR_HTR_6              (0x000040UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD2HTR_HTR_7              (0x000080UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD2HTR_HTR_8              (0x000100UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD2HTR_HTR_9              (0x000200UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD2HTR_HTR_10             (0x000400UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD2HTR_HTR_11             (0x000800UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD2HTR_HTR_12             (0x001000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD2HTR_HTR_13             (0x002000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD2HTR_HTR_14             (0x004000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD2HTR_HTR_15             (0x008000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD2HTR_HTR_16             (0x010000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD2HTR_HTR_17             (0x020000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD2HTR_HTR_18             (0x040000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD2HTR_HTR_19             (0x080000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD2HTR_HTR_20             (0x100000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD2HTR_HTR_21             (0x200000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD2HTR_HTR_22             (0x400000UL << ADC_AWD2HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_LT register  *******************/
+#define ADC_AWD3LTR_LTR_Pos            (0U)
+#define ADC_AWD3LTR_LTR_Msk            (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3LTR_LTR                ADC_AWD3LTR_LTR_Msk                    /*!< ADC analog watchdog 3 threshold low */
+#define ADC_AWD3LTR_LTR_0              (0x000001UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3LTR_LTR_1              (0x000002UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3LTR_LTR_2              (0x000004UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3LTR_LTR_3              (0x000008UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3LTR_LTR_4              (0x000010UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3LTR_LTR_5              (0x000020UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3LTR_LTR_6              (0x000040UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3LTR_LTR_7              (0x000080UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3LTR_LTR_8              (0x000100UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3LTR_LTR_9              (0x000200UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3LTR_LTR_10             (0x000400UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3LTR_LTR_11             (0x000800UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3LTR_LTR_12             (0x001000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3LTR_LTR_13             (0x002000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3LTR_LTR_14             (0x004000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3LTR_LTR_15             (0x008000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3LTR_LTR_16             (0x010000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3LTR_LTR_17             (0x020000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3LTR_LTR_18             (0x040000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3LTR_LTR_19             (0x080000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3LTR_LTR_20             (0x100000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3LTR_LTR_21             (0x200000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3LTR_LTR_22             (0x400000UL << ADC_AWD3LTR_LTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_AWD3TR_HT register  *******************/
+#define ADC_AWD3HTR_HTR_Pos            (0U)
+#define ADC_AWD3HTR_HTR_Msk            (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos)  /*!< 0x007FFFFF */
+#define ADC_AWD3HTR_HTR                ADC_AWD3HTR_HTR_Msk                    /*!< ADC analog watchdog 3 threshold high */
+#define ADC_AWD3HTR_HTR_0              (0x000001UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000001 */
+#define ADC_AWD3HTR_HTR_1              (0x000002UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000002 */
+#define ADC_AWD3HTR_HTR_2              (0x000004UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000004 */
+#define ADC_AWD3HTR_HTR_3              (0x000008UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000008 */
+#define ADC_AWD3HTR_HTR_4              (0x000010UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000010 */
+#define ADC_AWD3HTR_HTR_5              (0x000020UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000020 */
+#define ADC_AWD3HTR_HTR_6              (0x000040UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000040 */
+#define ADC_AWD3HTR_HTR_7              (0x000080UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000080 */
+#define ADC_AWD3HTR_HTR_8              (0x000100UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000100 */
+#define ADC_AWD3HTR_HTR_9              (0x000200UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000200 */
+#define ADC_AWD3HTR_HTR_10             (0x000400UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000400 */
+#define ADC_AWD3HTR_HTR_11             (0x000800UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00000800 */
+#define ADC_AWD3HTR_HTR_12             (0x001000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00001000 */
+#define ADC_AWD3HTR_HTR_13             (0x002000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00002000 */
+#define ADC_AWD3HTR_HTR_14             (0x004000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00004000 */
+#define ADC_AWD3HTR_HTR_15             (0x008000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00008000 */
+#define ADC_AWD3HTR_HTR_16             (0x010000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00010000 */
+#define ADC_AWD3HTR_HTR_17             (0x020000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00020000 */
+#define ADC_AWD3HTR_HTR_18             (0x040000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00040000 */
+#define ADC_AWD3HTR_HTR_19             (0x080000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00080000 */
+#define ADC_AWD3HTR_HTR_20             (0x100000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00100000 */
+#define ADC_AWD3HTR_HTR_21             (0x200000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00200000 */
+#define ADC_AWD3HTR_HTR_22             (0x400000UL << ADC_AWD3HTR_HTR_Pos)    /*!< 0x00400000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)
+#define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode selection */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)
+#define ADC_CALFACT_CALFACT_S_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos)  /*!< 0x000003FF */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7        (0x80UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8        (0x100UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9        (0x200UL<< ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000200 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)
+#define ADC_CALFACT_CALFACT_D_Msk      (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos)  /*!< 0x03FF0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7        (0x80UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8        (0x100UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9        (0x200UL<< ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x02000000 */
+
+#define ADC_CALFACT_CALADDOS_Pos       (31U)
+#define ADC_CALFACT_CALADDOS_Msk       (0x01UL << ADC_CALFACT_CALADDOS_Pos)    /*!< 0x80000000 */
+#define ADC_CALFACT_CALADDOS           ADC_CALFACT_CALADDOS_Msk                /*!< ADC calibration additional offset mode */
+
+/********************  Bit definition for ADC_OR option register  ***************/
+#define ADC_OR_OP0_Pos                 (0U)
+#define ADC_OR_OP0_Msk                 (0x1UL << ADC_OR_OP0_Pos)               /*!< 0x00000001 */
+#define ADC_OR_OP0                     ADC_OR_OP0_Msk                          /*!< ADC internal reference voltage buffer */
+
+#define ADC_OR_OP1_Pos                 (1U)
+#define ADC_OR_OP1_Msk                 (0x1UL << ADC_OR_OP1_Pos)               /*!< 0x00000002 */
+#define ADC_OR_OP1                     ADC_OR_OP1_Msk                          /*!< ADC internal bandgap */
+
+#define ADC_OR_OP2_Pos                 (2U)
+#define ADC_OR_OP2_Msk                 (0x1UL << ADC_OR_OP2_Pos)               /*!< 0x00000004 */
+#define ADC_OR_OP2                     ADC_OR_OP2_Msk                          /*!< ADC internal path to VDDCORE */
+
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)
+#define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)
+#define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)
+#define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)
+#define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)
+#define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)
+#define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)
+#define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)
+#define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)
+#define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)
+#define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)
+#define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)
+#define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)
+#define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)
+#define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)
+#define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)
+#define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)
+#define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)
+#define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)
+#define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)
+#define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
+
+#define ADC_CCR_DAMDF_Pos              (14U)
+#define ADC_CCR_DAMDF_Msk              (0x3UL << ADC_CCR_DAMDF_Pos)            /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                  ADC_CCR_DAMDF_Msk                       /*!< ADC multimode data format */
+#define ADC_CCR_DAMDF_0                (0x1UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                (0x2UL << ADC_CCR_DAMDF_Pos)            /*!< 0x00008000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)
+#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+
+#define ADC_CCR_VBATEN_Pos             (24U)
+#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos         (0U)
+#define ADC_CDR2_RDATA_ALT_Msk         (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT             ADC_CDR2_RDATA_ALT_Msk                   /*!< ADC multimode master or slave (alternated) group regular conversion data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       BSEC unit (Boot and Security)                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for BSEC_FVRw register  *******************/
+#define BSEC_FVRw_FV_Pos               (0U)
+#define BSEC_FVRw_FV_Msk               (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos)           /*!< 0xFFFFFFFF */
+#define BSEC_FVRw_FV                   BSEC_FVRw_FV_Msk                            /*!< Fuse value */
+
+/*****************  Bit definition for BSEC_SPLOCKx register  *****************/
+#define BSEC_SPLOCKx_SPLOCK0_Pos       (0U)
+#define BSEC_SPLOCKx_SPLOCK0_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SPLOCKx_SPLOCK0           BSEC_SPLOCKx_SPLOCK0_Msk                    /*!< Sticky programming lock for word (32*x) */
+#define BSEC_SPLOCKx_SPLOCK1_Pos       (1U)
+#define BSEC_SPLOCKx_SPLOCK1_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SPLOCKx_SPLOCK1           BSEC_SPLOCKx_SPLOCK1_Msk                    /*!< Sticky programming lock for word (1+32*x) */
+#define BSEC_SPLOCKx_SPLOCK2_Pos       (2U)
+#define BSEC_SPLOCKx_SPLOCK2_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SPLOCKx_SPLOCK2           BSEC_SPLOCKx_SPLOCK2_Msk                    /*!< Sticky programming lock for word (2+32*x) */
+#define BSEC_SPLOCKx_SPLOCK3_Pos       (3U)
+#define BSEC_SPLOCKx_SPLOCK3_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SPLOCKx_SPLOCK3           BSEC_SPLOCKx_SPLOCK3_Msk                    /*!< Sticky programming lock for word (3+32*x) */
+#define BSEC_SPLOCKx_SPLOCK4_Pos       (4U)
+#define BSEC_SPLOCKx_SPLOCK4_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SPLOCKx_SPLOCK4           BSEC_SPLOCKx_SPLOCK4_Msk                    /*!< Sticky programming lock for word (4+32*x) */
+#define BSEC_SPLOCKx_SPLOCK5_Pos       (5U)
+#define BSEC_SPLOCKx_SPLOCK5_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SPLOCKx_SPLOCK5           BSEC_SPLOCKx_SPLOCK5_Msk                    /*!< Sticky programming lock for word (5+32*x) */
+#define BSEC_SPLOCKx_SPLOCK6_Pos       (6U)
+#define BSEC_SPLOCKx_SPLOCK6_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SPLOCKx_SPLOCK6           BSEC_SPLOCKx_SPLOCK6_Msk                    /*!< Sticky programming lock for word (6+32*x) */
+#define BSEC_SPLOCKx_SPLOCK7_Pos       (7U)
+#define BSEC_SPLOCKx_SPLOCK7_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SPLOCKx_SPLOCK7           BSEC_SPLOCKx_SPLOCK7_Msk                    /*!< Sticky programming lock for word (7+32*x) */
+#define BSEC_SPLOCKx_SPLOCK8_Pos       (8U)
+#define BSEC_SPLOCKx_SPLOCK8_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SPLOCKx_SPLOCK8           BSEC_SPLOCKx_SPLOCK8_Msk                    /*!< Sticky programming lock for word (8+32*x) */
+#define BSEC_SPLOCKx_SPLOCK9_Pos       (9U)
+#define BSEC_SPLOCKx_SPLOCK9_Msk       (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SPLOCKx_SPLOCK9           BSEC_SPLOCKx_SPLOCK9_Msk                    /*!< Sticky programming lock for word (9+32*x) */
+#define BSEC_SPLOCKx_SPLOCK10_Pos      (10U)
+#define BSEC_SPLOCKx_SPLOCK10_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SPLOCKx_SPLOCK10          BSEC_SPLOCKx_SPLOCK10_Msk                   /*!< Sticky programming lock for word (10+32*x) */
+#define BSEC_SPLOCKx_SPLOCK11_Pos      (11U)
+#define BSEC_SPLOCKx_SPLOCK11_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SPLOCKx_SPLOCK11          BSEC_SPLOCKx_SPLOCK11_Msk                   /*!< Sticky programming lock for word (11+32*x) */
+#define BSEC_SPLOCKx_SPLOCK12_Pos      (12U)
+#define BSEC_SPLOCKx_SPLOCK12_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SPLOCKx_SPLOCK12          BSEC_SPLOCKx_SPLOCK12_Msk                   /*!< Sticky programming lock for word (12+32*x) */
+#define BSEC_SPLOCKx_SPLOCK13_Pos      (13U)
+#define BSEC_SPLOCKx_SPLOCK13_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SPLOCKx_SPLOCK13          BSEC_SPLOCKx_SPLOCK13_Msk                   /*!< Sticky programming lock for word (13+32*x) */
+#define BSEC_SPLOCKx_SPLOCK14_Pos      (14U)
+#define BSEC_SPLOCKx_SPLOCK14_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SPLOCKx_SPLOCK14          BSEC_SPLOCKx_SPLOCK14_Msk                   /*!< Sticky programming lock for word (14+32*x) */
+#define BSEC_SPLOCKx_SPLOCK15_Pos      (15U)
+#define BSEC_SPLOCKx_SPLOCK15_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SPLOCKx_SPLOCK15          BSEC_SPLOCKx_SPLOCK15_Msk                   /*!< Sticky programming lock for word (15+32*x) */
+#define BSEC_SPLOCKx_SPLOCK16_Pos      (16U)
+#define BSEC_SPLOCKx_SPLOCK16_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SPLOCKx_SPLOCK16          BSEC_SPLOCKx_SPLOCK16_Msk                   /*!< Sticky programming lock for word (16+32*x) */
+#define BSEC_SPLOCKx_SPLOCK17_Pos      (17U)
+#define BSEC_SPLOCKx_SPLOCK17_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SPLOCKx_SPLOCK17          BSEC_SPLOCKx_SPLOCK17_Msk                   /*!< Sticky programming lock for word (17+32*x) */
+#define BSEC_SPLOCKx_SPLOCK18_Pos      (18U)
+#define BSEC_SPLOCKx_SPLOCK18_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SPLOCKx_SPLOCK18          BSEC_SPLOCKx_SPLOCK18_Msk                   /*!< Sticky programming lock for word (18+32*x) */
+#define BSEC_SPLOCKx_SPLOCK19_Pos      (19U)
+#define BSEC_SPLOCKx_SPLOCK19_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SPLOCKx_SPLOCK19          BSEC_SPLOCKx_SPLOCK19_Msk                   /*!< Sticky programming lock for word (19+32*x) */
+#define BSEC_SPLOCKx_SPLOCK20_Pos      (20U)
+#define BSEC_SPLOCKx_SPLOCK20_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SPLOCKx_SPLOCK20          BSEC_SPLOCKx_SPLOCK20_Msk                   /*!< Sticky programming lock for word (20+32*x) */
+#define BSEC_SPLOCKx_SPLOCK21_Pos      (21U)
+#define BSEC_SPLOCKx_SPLOCK21_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SPLOCKx_SPLOCK21          BSEC_SPLOCKx_SPLOCK21_Msk                   /*!< Sticky programming lock for word (21+32*x) */
+#define BSEC_SPLOCKx_SPLOCK22_Pos      (22U)
+#define BSEC_SPLOCKx_SPLOCK22_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SPLOCKx_SPLOCK22          BSEC_SPLOCKx_SPLOCK22_Msk                   /*!< Sticky programming lock for word (22+32*x) */
+#define BSEC_SPLOCKx_SPLOCK23_Pos      (23U)
+#define BSEC_SPLOCKx_SPLOCK23_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SPLOCKx_SPLOCK23          BSEC_SPLOCKx_SPLOCK23_Msk                   /*!< Sticky programming lock for word (23+32*x) */
+#define BSEC_SPLOCKx_SPLOCK24_Pos      (24U)
+#define BSEC_SPLOCKx_SPLOCK24_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SPLOCKx_SPLOCK24          BSEC_SPLOCKx_SPLOCK24_Msk                   /*!< Sticky programming lock for word (24+32*x) */
+#define BSEC_SPLOCKx_SPLOCK25_Pos      (25U)
+#define BSEC_SPLOCKx_SPLOCK25_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SPLOCKx_SPLOCK25          BSEC_SPLOCKx_SPLOCK25_Msk                   /*!< Sticky programming lock for word (25+32*x) */
+#define BSEC_SPLOCKx_SPLOCK26_Pos      (26U)
+#define BSEC_SPLOCKx_SPLOCK26_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SPLOCKx_SPLOCK26          BSEC_SPLOCKx_SPLOCK26_Msk                   /*!< Sticky programming lock for word (26+32*x) */
+#define BSEC_SPLOCKx_SPLOCK27_Pos      (27U)
+#define BSEC_SPLOCKx_SPLOCK27_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SPLOCKx_SPLOCK27          BSEC_SPLOCKx_SPLOCK27_Msk                   /*!< Sticky programming lock for word (27+32*x) */
+#define BSEC_SPLOCKx_SPLOCK28_Pos      (28U)
+#define BSEC_SPLOCKx_SPLOCK28_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SPLOCKx_SPLOCK28          BSEC_SPLOCKx_SPLOCK28_Msk                   /*!< Sticky programming lock for word (28+32*x) */
+#define BSEC_SPLOCKx_SPLOCK29_Pos      (29U)
+#define BSEC_SPLOCKx_SPLOCK29_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SPLOCKx_SPLOCK29          BSEC_SPLOCKx_SPLOCK29_Msk                   /*!< Sticky programming lock for word (29+32*x) */
+#define BSEC_SPLOCKx_SPLOCK30_Pos      (30U)
+#define BSEC_SPLOCKx_SPLOCK30_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SPLOCKx_SPLOCK30          BSEC_SPLOCKx_SPLOCK30_Msk                   /*!< Sticky programming lock for word (30+32*x) */
+#define BSEC_SPLOCKx_SPLOCK31_Pos      (31U)
+#define BSEC_SPLOCKx_SPLOCK31_Msk      (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SPLOCKx_SPLOCK31          BSEC_SPLOCKx_SPLOCK31_Msk                   /*!< Sticky programming lock for word (31+32*x) */
+
+/*****************  Bit definition for BSEC_SWLOCKx register  *****************/
+#define BSEC_SWLOCKx_SWLOCK0_Pos       (0U)
+#define BSEC_SWLOCKx_SWLOCK0_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SWLOCKx_SWLOCK0           BSEC_SWLOCKx_SWLOCK0_Msk                    /*!< Sticky write lock for shadow register (32*x) */
+#define BSEC_SWLOCKx_SWLOCK1_Pos       (1U)
+#define BSEC_SWLOCKx_SWLOCK1_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SWLOCKx_SWLOCK1           BSEC_SWLOCKx_SWLOCK1_Msk                    /*!< Sticky write lock for shadow register (1+32*x) */
+#define BSEC_SWLOCKx_SWLOCK2_Pos       (2U)
+#define BSEC_SWLOCKx_SWLOCK2_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SWLOCKx_SWLOCK2           BSEC_SWLOCKx_SWLOCK2_Msk                    /*!< Sticky write lock for shadow register (2+32*x) */
+#define BSEC_SWLOCKx_SWLOCK3_Pos       (3U)
+#define BSEC_SWLOCKx_SWLOCK3_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SWLOCKx_SWLOCK3           BSEC_SWLOCKx_SWLOCK3_Msk                    /*!< Sticky write lock for shadow register (3+32*x) */
+#define BSEC_SWLOCKx_SWLOCK4_Pos       (4U)
+#define BSEC_SWLOCKx_SWLOCK4_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SWLOCKx_SWLOCK4           BSEC_SWLOCKx_SWLOCK4_Msk                    /*!< Sticky write lock for shadow register (4+32*x) */
+#define BSEC_SWLOCKx_SWLOCK5_Pos       (5U)
+#define BSEC_SWLOCKx_SWLOCK5_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SWLOCKx_SWLOCK5           BSEC_SWLOCKx_SWLOCK5_Msk                    /*!< Sticky write lock for shadow register (5+32*x) */
+#define BSEC_SWLOCKx_SWLOCK6_Pos       (6U)
+#define BSEC_SWLOCKx_SWLOCK6_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SWLOCKx_SWLOCK6           BSEC_SWLOCKx_SWLOCK6_Msk                    /*!< Sticky write lock for shadow register (6+32*x) */
+#define BSEC_SWLOCKx_SWLOCK7_Pos       (7U)
+#define BSEC_SWLOCKx_SWLOCK7_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SWLOCKx_SWLOCK7           BSEC_SWLOCKx_SWLOCK7_Msk                    /*!< Sticky write lock for shadow register (7+32*x) */
+#define BSEC_SWLOCKx_SWLOCK8_Pos       (8U)
+#define BSEC_SWLOCKx_SWLOCK8_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SWLOCKx_SWLOCK8           BSEC_SWLOCKx_SWLOCK8_Msk                    /*!< Sticky write lock for shadow register (8+32*x) */
+#define BSEC_SWLOCKx_SWLOCK9_Pos       (9U)
+#define BSEC_SWLOCKx_SWLOCK9_Msk       (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SWLOCKx_SWLOCK9           BSEC_SWLOCKx_SWLOCK9_Msk                    /*!< Sticky write lock for shadow register (9+32*x) */
+#define BSEC_SWLOCKx_SWLOCK10_Pos      (10U)
+#define BSEC_SWLOCKx_SWLOCK10_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SWLOCKx_SWLOCK10          BSEC_SWLOCKx_SWLOCK10_Msk                   /*!< Sticky write lock for shadow register (10+32*x) */
+#define BSEC_SWLOCKx_SWLOCK11_Pos      (11U)
+#define BSEC_SWLOCKx_SWLOCK11_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SWLOCKx_SWLOCK11          BSEC_SWLOCKx_SWLOCK11_Msk                   /*!< Sticky write lock for shadow register (11+32*x) */
+#define BSEC_SWLOCKx_SWLOCK12_Pos      (12U)
+#define BSEC_SWLOCKx_SWLOCK12_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SWLOCKx_SWLOCK12          BSEC_SWLOCKx_SWLOCK12_Msk                   /*!< Sticky write lock for shadow register (12+32*x) */
+#define BSEC_SWLOCKx_SWLOCK13_Pos      (13U)
+#define BSEC_SWLOCKx_SWLOCK13_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SWLOCKx_SWLOCK13          BSEC_SWLOCKx_SWLOCK13_Msk                   /*!< Sticky write lock for shadow register (13+32*x) */
+#define BSEC_SWLOCKx_SWLOCK14_Pos      (14U)
+#define BSEC_SWLOCKx_SWLOCK14_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SWLOCKx_SWLOCK14          BSEC_SWLOCKx_SWLOCK14_Msk                   /*!< Sticky write lock for shadow register (14+32*x) */
+#define BSEC_SWLOCKx_SWLOCK15_Pos      (15U)
+#define BSEC_SWLOCKx_SWLOCK15_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SWLOCKx_SWLOCK15          BSEC_SWLOCKx_SWLOCK15_Msk                   /*!< Sticky write lock for shadow register (15+32*x) */
+#define BSEC_SWLOCKx_SWLOCK16_Pos      (16U)
+#define BSEC_SWLOCKx_SWLOCK16_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SWLOCKx_SWLOCK16          BSEC_SWLOCKx_SWLOCK16_Msk                   /*!< Sticky write lock for shadow register (16+32*x) */
+#define BSEC_SWLOCKx_SWLOCK17_Pos      (17U)
+#define BSEC_SWLOCKx_SWLOCK17_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SWLOCKx_SWLOCK17          BSEC_SWLOCKx_SWLOCK17_Msk                   /*!< Sticky write lock for shadow register (17+32*x) */
+#define BSEC_SWLOCKx_SWLOCK18_Pos      (18U)
+#define BSEC_SWLOCKx_SWLOCK18_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SWLOCKx_SWLOCK18          BSEC_SWLOCKx_SWLOCK18_Msk                   /*!< Sticky write lock for shadow register (18+32*x) */
+#define BSEC_SWLOCKx_SWLOCK19_Pos      (19U)
+#define BSEC_SWLOCKx_SWLOCK19_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SWLOCKx_SWLOCK19          BSEC_SWLOCKx_SWLOCK19_Msk                   /*!< Sticky write lock for shadow register (19+32*x) */
+#define BSEC_SWLOCKx_SWLOCK20_Pos      (20U)
+#define BSEC_SWLOCKx_SWLOCK20_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SWLOCKx_SWLOCK20          BSEC_SWLOCKx_SWLOCK20_Msk                   /*!< Sticky write lock for shadow register (20+32*x) */
+#define BSEC_SWLOCKx_SWLOCK21_Pos      (21U)
+#define BSEC_SWLOCKx_SWLOCK21_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SWLOCKx_SWLOCK21          BSEC_SWLOCKx_SWLOCK21_Msk                   /*!< Sticky write lock for shadow register (21+32*x) */
+#define BSEC_SWLOCKx_SWLOCK22_Pos      (22U)
+#define BSEC_SWLOCKx_SWLOCK22_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SWLOCKx_SWLOCK22          BSEC_SWLOCKx_SWLOCK22_Msk                   /*!< Sticky write lock for shadow register (22+32*x) */
+#define BSEC_SWLOCKx_SWLOCK23_Pos      (23U)
+#define BSEC_SWLOCKx_SWLOCK23_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SWLOCKx_SWLOCK23          BSEC_SWLOCKx_SWLOCK23_Msk                   /*!< Sticky write lock for shadow register (23+32*x) */
+#define BSEC_SWLOCKx_SWLOCK24_Pos      (24U)
+#define BSEC_SWLOCKx_SWLOCK24_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SWLOCKx_SWLOCK24          BSEC_SWLOCKx_SWLOCK24_Msk                   /*!< Sticky write lock for shadow register (24+32*x) */
+#define BSEC_SWLOCKx_SWLOCK25_Pos      (25U)
+#define BSEC_SWLOCKx_SWLOCK25_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SWLOCKx_SWLOCK25          BSEC_SWLOCKx_SWLOCK25_Msk                   /*!< Sticky write lock for shadow register (25+32*x) */
+#define BSEC_SWLOCKx_SWLOCK26_Pos      (26U)
+#define BSEC_SWLOCKx_SWLOCK26_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SWLOCKx_SWLOCK26          BSEC_SWLOCKx_SWLOCK26_Msk                   /*!< Sticky write lock for shadow register (26+32*x) */
+#define BSEC_SWLOCKx_SWLOCK27_Pos      (27U)
+#define BSEC_SWLOCKx_SWLOCK27_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SWLOCKx_SWLOCK27          BSEC_SWLOCKx_SWLOCK27_Msk                   /*!< Sticky write lock for shadow register (27+32*x) */
+#define BSEC_SWLOCKx_SWLOCK28_Pos      (28U)
+#define BSEC_SWLOCKx_SWLOCK28_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SWLOCKx_SWLOCK28          BSEC_SWLOCKx_SWLOCK28_Msk                   /*!< Sticky write lock for shadow register (28+32*x) */
+#define BSEC_SWLOCKx_SWLOCK29_Pos      (29U)
+#define BSEC_SWLOCKx_SWLOCK29_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SWLOCKx_SWLOCK29          BSEC_SWLOCKx_SWLOCK29_Msk                   /*!< Sticky write lock for shadow register (29+32*x) */
+#define BSEC_SWLOCKx_SWLOCK30_Pos      (30U)
+#define BSEC_SWLOCKx_SWLOCK30_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SWLOCKx_SWLOCK30          BSEC_SWLOCKx_SWLOCK30_Msk                   /*!< Sticky write lock for shadow register (30+32*x) */
+#define BSEC_SWLOCKx_SWLOCK31_Pos      (31U)
+#define BSEC_SWLOCKx_SWLOCK31_Msk      (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SWLOCKx_SWLOCK31          BSEC_SWLOCKx_SWLOCK31_Msk                   /*!< Sticky write lock for shadow register (31+32*x) */
+
+/*****************  Bit definition for BSEC_SRLOCKx register  *****************/
+#define BSEC_SRLOCKx_SRLOCK0_Pos       (0U)
+#define BSEC_SRLOCKx_SRLOCK0_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos)          /*!< 0x00000001 */
+#define BSEC_SRLOCKx_SRLOCK0           BSEC_SRLOCKx_SRLOCK0_Msk                    /*!< Sticky reload lock for fuse word (32*x) */
+#define BSEC_SRLOCKx_SRLOCK1_Pos       (1U)
+#define BSEC_SRLOCKx_SRLOCK1_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos)          /*!< 0x00000002 */
+#define BSEC_SRLOCKx_SRLOCK1           BSEC_SRLOCKx_SRLOCK1_Msk                    /*!< Sticky reload lock for fuse word (1+32*x) */
+#define BSEC_SRLOCKx_SRLOCK2_Pos       (2U)
+#define BSEC_SRLOCKx_SRLOCK2_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos)          /*!< 0x00000004 */
+#define BSEC_SRLOCKx_SRLOCK2           BSEC_SRLOCKx_SRLOCK2_Msk                    /*!< Sticky reload lock for fuse word (2+32*x) */
+#define BSEC_SRLOCKx_SRLOCK3_Pos       (3U)
+#define BSEC_SRLOCKx_SRLOCK3_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos)          /*!< 0x00000008 */
+#define BSEC_SRLOCKx_SRLOCK3           BSEC_SRLOCKx_SRLOCK3_Msk                    /*!< Sticky reload lock for fuse word (3+32*x) */
+#define BSEC_SRLOCKx_SRLOCK4_Pos       (4U)
+#define BSEC_SRLOCKx_SRLOCK4_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos)          /*!< 0x00000010 */
+#define BSEC_SRLOCKx_SRLOCK4           BSEC_SRLOCKx_SRLOCK4_Msk                    /*!< Sticky reload lock for fuse word (4+32*x) */
+#define BSEC_SRLOCKx_SRLOCK5_Pos       (5U)
+#define BSEC_SRLOCKx_SRLOCK5_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos)          /*!< 0x00000020 */
+#define BSEC_SRLOCKx_SRLOCK5           BSEC_SRLOCKx_SRLOCK5_Msk                    /*!< Sticky reload lock for fuse word (5+32*x) */
+#define BSEC_SRLOCKx_SRLOCK6_Pos       (6U)
+#define BSEC_SRLOCKx_SRLOCK6_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos)          /*!< 0x00000040 */
+#define BSEC_SRLOCKx_SRLOCK6           BSEC_SRLOCKx_SRLOCK6_Msk                    /*!< Sticky reload lock for fuse word (6+32*x) */
+#define BSEC_SRLOCKx_SRLOCK7_Pos       (7U)
+#define BSEC_SRLOCKx_SRLOCK7_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos)          /*!< 0x00000080 */
+#define BSEC_SRLOCKx_SRLOCK7           BSEC_SRLOCKx_SRLOCK7_Msk                    /*!< Sticky reload lock for fuse word (7+32*x) */
+#define BSEC_SRLOCKx_SRLOCK8_Pos       (8U)
+#define BSEC_SRLOCKx_SRLOCK8_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos)          /*!< 0x00000100 */
+#define BSEC_SRLOCKx_SRLOCK8           BSEC_SRLOCKx_SRLOCK8_Msk                    /*!< Sticky reload lock for fuse word (8+32*x) */
+#define BSEC_SRLOCKx_SRLOCK9_Pos       (9U)
+#define BSEC_SRLOCKx_SRLOCK9_Msk       (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos)          /*!< 0x00000200 */
+#define BSEC_SRLOCKx_SRLOCK9           BSEC_SRLOCKx_SRLOCK9_Msk                    /*!< Sticky reload lock for fuse word (9+32*x) */
+#define BSEC_SRLOCKx_SRLOCK10_Pos      (10U)
+#define BSEC_SRLOCKx_SRLOCK10_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos)         /*!< 0x00000400 */
+#define BSEC_SRLOCKx_SRLOCK10          BSEC_SRLOCKx_SRLOCK10_Msk                   /*!< Sticky reload lock for fuse word (10+2*x) */
+#define BSEC_SRLOCKx_SRLOCK11_Pos      (11U)
+#define BSEC_SRLOCKx_SRLOCK11_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos)         /*!< 0x00000800 */
+#define BSEC_SRLOCKx_SRLOCK11          BSEC_SRLOCKx_SRLOCK11_Msk                   /*!< Sticky reload lock for fuse word (11+32*x) */
+#define BSEC_SRLOCKx_SRLOCK12_Pos      (12U)
+#define BSEC_SRLOCKx_SRLOCK12_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos)         /*!< 0x00001000 */
+#define BSEC_SRLOCKx_SRLOCK12          BSEC_SRLOCKx_SRLOCK12_Msk                   /*!< Sticky reload lock for fuse word (12+32*x) */
+#define BSEC_SRLOCKx_SRLOCK13_Pos      (13U)
+#define BSEC_SRLOCKx_SRLOCK13_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos)         /*!< 0x00002000 */
+#define BSEC_SRLOCKx_SRLOCK13          BSEC_SRLOCKx_SRLOCK13_Msk                   /*!< Sticky reload lock for fuse word (13+32*x) */
+#define BSEC_SRLOCKx_SRLOCK14_Pos      (14U)
+#define BSEC_SRLOCKx_SRLOCK14_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos)         /*!< 0x00004000 */
+#define BSEC_SRLOCKx_SRLOCK14          BSEC_SRLOCKx_SRLOCK14_Msk                   /*!< Sticky reload lock for fuse word (14+32*x) */
+#define BSEC_SRLOCKx_SRLOCK15_Pos      (15U)
+#define BSEC_SRLOCKx_SRLOCK15_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos)         /*!< 0x00008000 */
+#define BSEC_SRLOCKx_SRLOCK15          BSEC_SRLOCKx_SRLOCK15_Msk                   /*!< Sticky reload lock for fuse word (15+32*x) */
+#define BSEC_SRLOCKx_SRLOCK16_Pos      (16U)
+#define BSEC_SRLOCKx_SRLOCK16_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos)         /*!< 0x00010000 */
+#define BSEC_SRLOCKx_SRLOCK16          BSEC_SRLOCKx_SRLOCK16_Msk                   /*!< Sticky reload lock for fuse word (16+32*x) */
+#define BSEC_SRLOCKx_SRLOCK17_Pos      (17U)
+#define BSEC_SRLOCKx_SRLOCK17_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos)         /*!< 0x00020000 */
+#define BSEC_SRLOCKx_SRLOCK17          BSEC_SRLOCKx_SRLOCK17_Msk                   /*!< Sticky reload lock for fuse word (17+32*x) */
+#define BSEC_SRLOCKx_SRLOCK18_Pos      (18U)
+#define BSEC_SRLOCKx_SRLOCK18_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos)         /*!< 0x00040000 */
+#define BSEC_SRLOCKx_SRLOCK18          BSEC_SRLOCKx_SRLOCK18_Msk                   /*!< Sticky reload lock for fuse word (18+32*x) */
+#define BSEC_SRLOCKx_SRLOCK19_Pos      (19U)
+#define BSEC_SRLOCKx_SRLOCK19_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos)         /*!< 0x00080000 */
+#define BSEC_SRLOCKx_SRLOCK19          BSEC_SRLOCKx_SRLOCK19_Msk                   /*!< Sticky reload lock for fuse word (19+32*x) */
+#define BSEC_SRLOCKx_SRLOCK20_Pos      (20U)
+#define BSEC_SRLOCKx_SRLOCK20_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos)         /*!< 0x00100000 */
+#define BSEC_SRLOCKx_SRLOCK20          BSEC_SRLOCKx_SRLOCK20_Msk                   /*!< Sticky reload lock for fuse word (20+32*x) */
+#define BSEC_SRLOCKx_SRLOCK21_Pos      (21U)
+#define BSEC_SRLOCKx_SRLOCK21_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos)         /*!< 0x00200000 */
+#define BSEC_SRLOCKx_SRLOCK21          BSEC_SRLOCKx_SRLOCK21_Msk                   /*!< Sticky reload lock for fuse word (21+32*x) */
+#define BSEC_SRLOCKx_SRLOCK22_Pos      (22U)
+#define BSEC_SRLOCKx_SRLOCK22_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos)         /*!< 0x00400000 */
+#define BSEC_SRLOCKx_SRLOCK22          BSEC_SRLOCKx_SRLOCK22_Msk                   /*!< Sticky reload lock for fuse word (22+32*x) */
+#define BSEC_SRLOCKx_SRLOCK23_Pos      (23U)
+#define BSEC_SRLOCKx_SRLOCK23_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos)         /*!< 0x00800000 */
+#define BSEC_SRLOCKx_SRLOCK23          BSEC_SRLOCKx_SRLOCK23_Msk                   /*!< Sticky reload lock for fuse word (23+32*x) */
+#define BSEC_SRLOCKx_SRLOCK24_Pos      (24U)
+#define BSEC_SRLOCKx_SRLOCK24_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos)         /*!< 0x01000000 */
+#define BSEC_SRLOCKx_SRLOCK24          BSEC_SRLOCKx_SRLOCK24_Msk                   /*!< Sticky reload lock for fuse word (24+32*x) */
+#define BSEC_SRLOCKx_SRLOCK25_Pos      (25U)
+#define BSEC_SRLOCKx_SRLOCK25_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos)         /*!< 0x02000000 */
+#define BSEC_SRLOCKx_SRLOCK25          BSEC_SRLOCKx_SRLOCK25_Msk                   /*!< Sticky reload lock for fuse word (25+32*x) */
+#define BSEC_SRLOCKx_SRLOCK26_Pos      (26U)
+#define BSEC_SRLOCKx_SRLOCK26_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos)         /*!< 0x04000000 */
+#define BSEC_SRLOCKx_SRLOCK26          BSEC_SRLOCKx_SRLOCK26_Msk                   /*!< Sticky reload lock for fuse word (26+32*x) */
+#define BSEC_SRLOCKx_SRLOCK27_Pos      (27U)
+#define BSEC_SRLOCKx_SRLOCK27_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos)         /*!< 0x08000000 */
+#define BSEC_SRLOCKx_SRLOCK27          BSEC_SRLOCKx_SRLOCK27_Msk                   /*!< Sticky reload lock for fuse word (27+32*x) */
+#define BSEC_SRLOCKx_SRLOCK28_Pos      (28U)
+#define BSEC_SRLOCKx_SRLOCK28_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos)         /*!< 0x10000000 */
+#define BSEC_SRLOCKx_SRLOCK28          BSEC_SRLOCKx_SRLOCK28_Msk                   /*!< Sticky reload lock for fuse word (28+32*x) */
+#define BSEC_SRLOCKx_SRLOCK29_Pos      (29U)
+#define BSEC_SRLOCKx_SRLOCK29_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos)         /*!< 0x20000000 */
+#define BSEC_SRLOCKx_SRLOCK29          BSEC_SRLOCKx_SRLOCK29_Msk                   /*!< Sticky reload lock for fuse word (29+32*x) */
+#define BSEC_SRLOCKx_SRLOCK30_Pos      (30U)
+#define BSEC_SRLOCKx_SRLOCK30_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos)         /*!< 0x40000000 */
+#define BSEC_SRLOCKx_SRLOCK30          BSEC_SRLOCKx_SRLOCK30_Msk                   /*!< Sticky reload lock for fuse word (30+32*x) */
+#define BSEC_SRLOCKx_SRLOCK31_Pos      (31U)
+#define BSEC_SRLOCKx_SRLOCK31_Msk      (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos)         /*!< 0x80000000 */
+#define BSEC_SRLOCKx_SRLOCK31          BSEC_SRLOCKx_SRLOCK31_Msk                   /*!< Sticky reload lock for fuse word (31+32*x) */
+
+/****************  Bit definition for BSEC_OTPVLDRx register  *****************/
+#define BSEC_OTPVLDRx_VLDF0_Pos        (0U)
+#define BSEC_OTPVLDRx_VLDF0_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos)           /*!< 0x00000001 */
+#define BSEC_OTPVLDRx_VLDF0            BSEC_OTPVLDRx_VLDF0_Msk                     /*!< Valid flag for shadow register (32*x) */
+#define BSEC_OTPVLDRx_VLDF1_Pos        (1U)
+#define BSEC_OTPVLDRx_VLDF1_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos)           /*!< 0x00000002 */
+#define BSEC_OTPVLDRx_VLDF1            BSEC_OTPVLDRx_VLDF1_Msk                     /*!< Valid flag for shadow register (1+32*x) */
+#define BSEC_OTPVLDRx_VLDF2_Pos        (2U)
+#define BSEC_OTPVLDRx_VLDF2_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos)           /*!< 0x00000004 */
+#define BSEC_OTPVLDRx_VLDF2            BSEC_OTPVLDRx_VLDF2_Msk                     /*!< Valid flag for shadow register (2+32*x) */
+#define BSEC_OTPVLDRx_VLDF3_Pos        (3U)
+#define BSEC_OTPVLDRx_VLDF3_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos)           /*!< 0x00000008 */
+#define BSEC_OTPVLDRx_VLDF3            BSEC_OTPVLDRx_VLDF3_Msk                     /*!< Valid flag for shadow register (3+32*x) */
+#define BSEC_OTPVLDRx_VLDF4_Pos        (4U)
+#define BSEC_OTPVLDRx_VLDF4_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos)           /*!< 0x00000010 */
+#define BSEC_OTPVLDRx_VLDF4            BSEC_OTPVLDRx_VLDF4_Msk                     /*!< Valid flag for shadow register (4+32*x) */
+#define BSEC_OTPVLDRx_VLDF5_Pos        (5U)
+#define BSEC_OTPVLDRx_VLDF5_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos)           /*!< 0x00000020 */
+#define BSEC_OTPVLDRx_VLDF5            BSEC_OTPVLDRx_VLDF5_Msk                     /*!< Valid flag for shadow register (5+32*x) */
+#define BSEC_OTPVLDRx_VLDF6_Pos        (6U)
+#define BSEC_OTPVLDRx_VLDF6_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos)           /*!< 0x00000040 */
+#define BSEC_OTPVLDRx_VLDF6            BSEC_OTPVLDRx_VLDF6_Msk                     /*!< Valid flag for shadow register (6+32*x) */
+#define BSEC_OTPVLDRx_VLDF7_Pos        (7U)
+#define BSEC_OTPVLDRx_VLDF7_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos)           /*!< 0x00000080 */
+#define BSEC_OTPVLDRx_VLDF7            BSEC_OTPVLDRx_VLDF7_Msk                     /*!< Valid flag for shadow register (7+32*x) */
+#define BSEC_OTPVLDRx_VLDF8_Pos        (8U)
+#define BSEC_OTPVLDRx_VLDF8_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos)           /*!< 0x00000100 */
+#define BSEC_OTPVLDRx_VLDF8            BSEC_OTPVLDRx_VLDF8_Msk                     /*!< Valid flag for shadow register (8+32*x) */
+#define BSEC_OTPVLDRx_VLDF9_Pos        (9U)
+#define BSEC_OTPVLDRx_VLDF9_Msk        (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos)           /*!< 0x00000200 */
+#define BSEC_OTPVLDRx_VLDF9            BSEC_OTPVLDRx_VLDF9_Msk                     /*!< Valid flag for shadow register (9+32*x) */
+#define BSEC_OTPVLDRx_VLDF10_Pos       (10U)
+#define BSEC_OTPVLDRx_VLDF10_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos)          /*!< 0x00000400 */
+#define BSEC_OTPVLDRx_VLDF10           BSEC_OTPVLDRx_VLDF10_Msk                    /*!< Valid flag for shadow register (10+32*x) */
+#define BSEC_OTPVLDRx_VLDF11_Pos       (11U)
+#define BSEC_OTPVLDRx_VLDF11_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos)          /*!< 0x00000800 */
+#define BSEC_OTPVLDRx_VLDF11           BSEC_OTPVLDRx_VLDF11_Msk                    /*!< Valid flag for shadow register (11+32*x) */
+#define BSEC_OTPVLDRx_VLDF12_Pos       (12U)
+#define BSEC_OTPVLDRx_VLDF12_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos)          /*!< 0x00001000 */
+#define BSEC_OTPVLDRx_VLDF12           BSEC_OTPVLDRx_VLDF12_Msk                    /*!< Valid flag for shadow register (12+32*x) */
+#define BSEC_OTPVLDRx_VLDF13_Pos       (13U)
+#define BSEC_OTPVLDRx_VLDF13_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos)          /*!< 0x00002000 */
+#define BSEC_OTPVLDRx_VLDF13           BSEC_OTPVLDRx_VLDF13_Msk                    /*!< Valid flag for shadow register (13+32*x) */
+#define BSEC_OTPVLDRx_VLDF14_Pos       (14U)
+#define BSEC_OTPVLDRx_VLDF14_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos)          /*!< 0x00004000 */
+#define BSEC_OTPVLDRx_VLDF14           BSEC_OTPVLDRx_VLDF14_Msk                    /*!< Valid flag for shadow register (14+32*x) */
+#define BSEC_OTPVLDRx_VLDF15_Pos       (15U)
+#define BSEC_OTPVLDRx_VLDF15_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos)          /*!< 0x00008000 */
+#define BSEC_OTPVLDRx_VLDF15           BSEC_OTPVLDRx_VLDF15_Msk                    /*!< Valid flag for shadow register (15+32*x) */
+#define BSEC_OTPVLDRx_VLDF16_Pos       (16U)
+#define BSEC_OTPVLDRx_VLDF16_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos)          /*!< 0x00010000 */
+#define BSEC_OTPVLDRx_VLDF16           BSEC_OTPVLDRx_VLDF16_Msk                    /*!< Valid flag for shadow register (16+32*x) */
+#define BSEC_OTPVLDRx_VLDF17_Pos       (17U)
+#define BSEC_OTPVLDRx_VLDF17_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos)          /*!< 0x00020000 */
+#define BSEC_OTPVLDRx_VLDF17           BSEC_OTPVLDRx_VLDF17_Msk                    /*!< Valid flag for shadow register (17+32*x) */
+#define BSEC_OTPVLDRx_VLDF18_Pos       (18U)
+#define BSEC_OTPVLDRx_VLDF18_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos)          /*!< 0x00040000 */
+#define BSEC_OTPVLDRx_VLDF18           BSEC_OTPVLDRx_VLDF18_Msk                    /*!< Valid flag for shadow register (18+32*x) */
+#define BSEC_OTPVLDRx_VLDF19_Pos       (19U)
+#define BSEC_OTPVLDRx_VLDF19_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos)          /*!< 0x00080000 */
+#define BSEC_OTPVLDRx_VLDF19           BSEC_OTPVLDRx_VLDF19_Msk                    /*!< Valid flag for shadow register (19+32*x) */
+#define BSEC_OTPVLDRx_VLDF20_Pos       (20U)
+#define BSEC_OTPVLDRx_VLDF20_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos)          /*!< 0x00100000 */
+#define BSEC_OTPVLDRx_VLDF20           BSEC_OTPVLDRx_VLDF20_Msk                    /*!< Valid flag for shadow register (20+32*x) */
+#define BSEC_OTPVLDRx_VLDF21_Pos       (21U)
+#define BSEC_OTPVLDRx_VLDF21_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos)          /*!< 0x00200000 */
+#define BSEC_OTPVLDRx_VLDF21           BSEC_OTPVLDRx_VLDF21_Msk                    /*!< Valid flag for shadow register (21+32*x) */
+#define BSEC_OTPVLDRx_VLDF22_Pos       (22U)
+#define BSEC_OTPVLDRx_VLDF22_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos)          /*!< 0x00400000 */
+#define BSEC_OTPVLDRx_VLDF22           BSEC_OTPVLDRx_VLDF22_Msk                    /*!< Valid flag for shadow register (22+32*x) */
+#define BSEC_OTPVLDRx_VLDF23_Pos       (23U)
+#define BSEC_OTPVLDRx_VLDF23_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos)          /*!< 0x00800000 */
+#define BSEC_OTPVLDRx_VLDF23           BSEC_OTPVLDRx_VLDF23_Msk                    /*!< Valid flag for shadow register (23+32*x) */
+#define BSEC_OTPVLDRx_VLDF24_Pos       (24U)
+#define BSEC_OTPVLDRx_VLDF24_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos)          /*!< 0x01000000 */
+#define BSEC_OTPVLDRx_VLDF24           BSEC_OTPVLDRx_VLDF24_Msk                    /*!< Valid flag for shadow register (24+32*x) */
+#define BSEC_OTPVLDRx_VLDF25_Pos       (25U)
+#define BSEC_OTPVLDRx_VLDF25_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos)          /*!< 0x02000000 */
+#define BSEC_OTPVLDRx_VLDF25           BSEC_OTPVLDRx_VLDF25_Msk                    /*!< Valid flag for shadow register (25+32*x) */
+#define BSEC_OTPVLDRx_VLDF26_Pos       (26U)
+#define BSEC_OTPVLDRx_VLDF26_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos)          /*!< 0x04000000 */
+#define BSEC_OTPVLDRx_VLDF26           BSEC_OTPVLDRx_VLDF26_Msk                    /*!< Valid flag for shadow register (26+32*x) */
+#define BSEC_OTPVLDRx_VLDF27_Pos       (27U)
+#define BSEC_OTPVLDRx_VLDF27_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos)          /*!< 0x08000000 */
+#define BSEC_OTPVLDRx_VLDF27           BSEC_OTPVLDRx_VLDF27_Msk                    /*!< Valid flag for shadow register (27+32*x) */
+#define BSEC_OTPVLDRx_VLDF28_Pos       (28U)
+#define BSEC_OTPVLDRx_VLDF28_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos)          /*!< 0x10000000 */
+#define BSEC_OTPVLDRx_VLDF28           BSEC_OTPVLDRx_VLDF28_Msk                    /*!< Valid flag for shadow register (28+32*x) */
+#define BSEC_OTPVLDRx_VLDF29_Pos       (29U)
+#define BSEC_OTPVLDRx_VLDF29_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos)          /*!< 0x20000000 */
+#define BSEC_OTPVLDRx_VLDF29           BSEC_OTPVLDRx_VLDF29_Msk                    /*!< Valid flag for shadow register (29+32*x) */
+#define BSEC_OTPVLDRx_VLDF30_Pos       (30U)
+#define BSEC_OTPVLDRx_VLDF30_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos)          /*!< 0x40000000 */
+#define BSEC_OTPVLDRx_VLDF30           BSEC_OTPVLDRx_VLDF30_Msk                    /*!< Valid flag for shadow register (30+32*x) */
+#define BSEC_OTPVLDRx_VLDF31_Pos       (31U)
+#define BSEC_OTPVLDRx_VLDF31_Msk       (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos)          /*!< 0x80000000 */
+#define BSEC_OTPVLDRx_VLDF31           BSEC_OTPVLDRx_VLDF31_Msk                    /*!< Valid flag for shadow register (31+32*x) */
+
+/******************  Bit definition for BSEC_SFSRx register  ******************/
+#define BSEC_SFSRx_SFW0_Pos            (0U)
+#define BSEC_SFSRx_SFW0_Msk            (0x1UL << BSEC_SFSRx_SFW0_Pos)               /*!< 0x00000001 */
+#define BSEC_SFSRx_SFW0                BSEC_SFSRx_SFW0_Msk                         /*!< Shadowed fuse word (32*x) */
+#define BSEC_SFSRx_SFW1_Pos            (1U)
+#define BSEC_SFSRx_SFW1_Msk            (0x1UL << BSEC_SFSRx_SFW1_Pos)               /*!< 0x00000002 */
+#define BSEC_SFSRx_SFW1                BSEC_SFSRx_SFW1_Msk                         /*!< Shadowed fuse word (1+32*x) */
+#define BSEC_SFSRx_SFW2_Pos            (2U)
+#define BSEC_SFSRx_SFW2_Msk            (0x1UL << BSEC_SFSRx_SFW2_Pos)               /*!< 0x00000004 */
+#define BSEC_SFSRx_SFW2                BSEC_SFSRx_SFW2_Msk                         /*!< Shadowed fuse word (2+32*x) */
+#define BSEC_SFSRx_SFW3_Pos            (3U)
+#define BSEC_SFSRx_SFW3_Msk            (0x1UL << BSEC_SFSRx_SFW3_Pos)               /*!< 0x00000008 */
+#define BSEC_SFSRx_SFW3                BSEC_SFSRx_SFW3_Msk                         /*!< Shadowed fuse word (3+32*x) */
+#define BSEC_SFSRx_SFW4_Pos            (4U)
+#define BSEC_SFSRx_SFW4_Msk            (0x1UL << BSEC_SFSRx_SFW4_Pos)               /*!< 0x00000010 */
+#define BSEC_SFSRx_SFW4                BSEC_SFSRx_SFW4_Msk                         /*!< Shadowed fuse word (4+32*x) */
+#define BSEC_SFSRx_SFW5_Pos            (5U)
+#define BSEC_SFSRx_SFW5_Msk            (0x1UL << BSEC_SFSRx_SFW5_Pos)               /*!< 0x00000020 */
+#define BSEC_SFSRx_SFW5                BSEC_SFSRx_SFW5_Msk                         /*!< Shadowed fuse word (5+32*x) */
+#define BSEC_SFSRx_SFW6_Pos            (6U)
+#define BSEC_SFSRx_SFW6_Msk            (0x1UL << BSEC_SFSRx_SFW6_Pos)               /*!< 0x00000040 */
+#define BSEC_SFSRx_SFW6                BSEC_SFSRx_SFW6_Msk                         /*!< Shadowed fuse word (6+32*x) */
+#define BSEC_SFSRx_SFW7_Pos            (7U)
+#define BSEC_SFSRx_SFW7_Msk            (0x1UL << BSEC_SFSRx_SFW7_Pos)               /*!< 0x00000080 */
+#define BSEC_SFSRx_SFW7                BSEC_SFSRx_SFW7_Msk                         /*!< Shadowed fuse word (7+32*x) */
+#define BSEC_SFSRx_SFW8_Pos            (8U)
+#define BSEC_SFSRx_SFW8_Msk            (0x1UL << BSEC_SFSRx_SFW8_Pos)               /*!< 0x00000100 */
+#define BSEC_SFSRx_SFW8                BSEC_SFSRx_SFW8_Msk                         /*!< Shadowed fuse word (8+32*x) */
+#define BSEC_SFSRx_SFW9_Pos            (9U)
+#define BSEC_SFSRx_SFW9_Msk            (0x1UL << BSEC_SFSRx_SFW9_Pos)               /*!< 0x00000200 */
+#define BSEC_SFSRx_SFW9                BSEC_SFSRx_SFW9_Msk                         /*!< Shadowed fuse word (9+32*x) */
+#define BSEC_SFSRx_SFW10_Pos           (10U)
+#define BSEC_SFSRx_SFW10_Msk           (0x1UL << BSEC_SFSRx_SFW10_Pos)              /*!< 0x00000400 */
+#define BSEC_SFSRx_SFW10               BSEC_SFSRx_SFW10_Msk                        /*!< Shadowed fuse word (10+32*x) */
+#define BSEC_SFSRx_SFW11_Pos           (11U)
+#define BSEC_SFSRx_SFW11_Msk           (0x1UL << BSEC_SFSRx_SFW11_Pos)              /*!< 0x00000800 */
+#define BSEC_SFSRx_SFW11               BSEC_SFSRx_SFW11_Msk                        /*!< Shadowed fuse word (11+32*x) */
+#define BSEC_SFSRx_SFW12_Pos           (12U)
+#define BSEC_SFSRx_SFW12_Msk           (0x1UL << BSEC_SFSRx_SFW12_Pos)              /*!< 0x00001000 */
+#define BSEC_SFSRx_SFW12               BSEC_SFSRx_SFW12_Msk                        /*!< Shadowed fuse word (12+32*x) */
+#define BSEC_SFSRx_SFW13_Pos           (13U)
+#define BSEC_SFSRx_SFW13_Msk           (0x1UL << BSEC_SFSRx_SFW13_Pos)              /*!< 0x00002000 */
+#define BSEC_SFSRx_SFW13               BSEC_SFSRx_SFW13_Msk                        /*!< Shadowed fuse word (13+32*x) */
+#define BSEC_SFSRx_SFW14_Pos           (14U)
+#define BSEC_SFSRx_SFW14_Msk           (0x1UL << BSEC_SFSRx_SFW14_Pos)              /*!< 0x00004000 */
+#define BSEC_SFSRx_SFW14               BSEC_SFSRx_SFW14_Msk                        /*!< Shadowed fuse word (14+32*x) */
+#define BSEC_SFSRx_SFW15_Pos           (15U)
+#define BSEC_SFSRx_SFW15_Msk           (0x1UL << BSEC_SFSRx_SFW15_Pos)              /*!< 0x00008000 */
+#define BSEC_SFSRx_SFW15               BSEC_SFSRx_SFW15_Msk                        /*!< Shadowed fuse word (15+32*x) */
+#define BSEC_SFSRx_SFW16_Pos           (16U)
+#define BSEC_SFSRx_SFW16_Msk           (0x1UL << BSEC_SFSRx_SFW16_Pos)              /*!< 0x00010000 */
+#define BSEC_SFSRx_SFW16               BSEC_SFSRx_SFW16_Msk                        /*!< Shadowed fuse word (16+32*x) */
+#define BSEC_SFSRx_SFW17_Pos           (17U)
+#define BSEC_SFSRx_SFW17_Msk           (0x1UL << BSEC_SFSRx_SFW17_Pos)              /*!< 0x00020000 */
+#define BSEC_SFSRx_SFW17               BSEC_SFSRx_SFW17_Msk                        /*!< Shadowed fuse word (17+32*x) */
+#define BSEC_SFSRx_SFW18_Pos           (18U)
+#define BSEC_SFSRx_SFW18_Msk           (0x1UL << BSEC_SFSRx_SFW18_Pos)              /*!< 0x00040000 */
+#define BSEC_SFSRx_SFW18               BSEC_SFSRx_SFW18_Msk                        /*!< Shadowed fuse word (18+32*x) */
+#define BSEC_SFSRx_SFW19_Pos           (19U)
+#define BSEC_SFSRx_SFW19_Msk           (0x1UL << BSEC_SFSRx_SFW19_Pos)              /*!< 0x00080000 */
+#define BSEC_SFSRx_SFW19               BSEC_SFSRx_SFW19_Msk                        /*!< Shadowed fuse word (19+32*x) */
+#define BSEC_SFSRx_SFW20_Pos           (20U)
+#define BSEC_SFSRx_SFW20_Msk           (0x1UL << BSEC_SFSRx_SFW20_Pos)              /*!< 0x00100000 */
+#define BSEC_SFSRx_SFW20               BSEC_SFSRx_SFW20_Msk                        /*!< Shadowed fuse word (20+32*x) */
+#define BSEC_SFSRx_SFW21_Pos           (21U)
+#define BSEC_SFSRx_SFW21_Msk           (0x1UL << BSEC_SFSRx_SFW21_Pos)              /*!< 0x00200000 */
+#define BSEC_SFSRx_SFW21               BSEC_SFSRx_SFW21_Msk                        /*!< Shadowed fuse word (21+32*x) */
+#define BSEC_SFSRx_SFW22_Pos           (22U)
+#define BSEC_SFSRx_SFW22_Msk           (0x1UL << BSEC_SFSRx_SFW22_Pos)              /*!< 0x00400000 */
+#define BSEC_SFSRx_SFW22               BSEC_SFSRx_SFW22_Msk                        /*!< Shadowed fuse word (22+32*x) */
+#define BSEC_SFSRx_SFW23_Pos           (23U)
+#define BSEC_SFSRx_SFW23_Msk           (0x1UL << BSEC_SFSRx_SFW23_Pos)              /*!< 0x00800000 */
+#define BSEC_SFSRx_SFW23               BSEC_SFSRx_SFW23_Msk                        /*!< Shadowed fuse word (23+32*x) */
+#define BSEC_SFSRx_SFW24_Pos           (24U)
+#define BSEC_SFSRx_SFW24_Msk           (0x1UL << BSEC_SFSRx_SFW24_Pos)              /*!< 0x01000000 */
+#define BSEC_SFSRx_SFW24               BSEC_SFSRx_SFW24_Msk                        /*!< Shadowed fuse word (24+32*x) */
+#define BSEC_SFSRx_SFW25_Pos           (25U)
+#define BSEC_SFSRx_SFW25_Msk           (0x1UL << BSEC_SFSRx_SFW25_Pos)              /*!< 0x02000000 */
+#define BSEC_SFSRx_SFW25               BSEC_SFSRx_SFW25_Msk                        /*!< Shadowed fuse word (25+32*x) */
+#define BSEC_SFSRx_SFW26_Pos           (26U)
+#define BSEC_SFSRx_SFW26_Msk           (0x1UL << BSEC_SFSRx_SFW26_Pos)              /*!< 0x04000000 */
+#define BSEC_SFSRx_SFW26               BSEC_SFSRx_SFW26_Msk                        /*!< Shadowed fuse word (26+32*x) */
+#define BSEC_SFSRx_SFW27_Pos           (27U)
+#define BSEC_SFSRx_SFW27_Msk           (0x1UL << BSEC_SFSRx_SFW27_Pos)              /*!< 0x08000000 */
+#define BSEC_SFSRx_SFW27               BSEC_SFSRx_SFW27_Msk                        /*!< Shadowed fuse word (27+32*x) */
+#define BSEC_SFSRx_SFW28_Pos           (28U)
+#define BSEC_SFSRx_SFW28_Msk           (0x1UL << BSEC_SFSRx_SFW28_Pos)              /*!< 0x10000000 */
+#define BSEC_SFSRx_SFW28               BSEC_SFSRx_SFW28_Msk                        /*!< Shadowed fuse word (28+32*x) */
+#define BSEC_SFSRx_SFW29_Pos           (29U)
+#define BSEC_SFSRx_SFW29_Msk           (0x1UL << BSEC_SFSRx_SFW29_Pos)              /*!< 0x20000000 */
+#define BSEC_SFSRx_SFW29               BSEC_SFSRx_SFW29_Msk                        /*!< Shadowed fuse word (29+32*x) */
+#define BSEC_SFSRx_SFW30_Pos           (30U)
+#define BSEC_SFSRx_SFW30_Msk           (0x1UL << BSEC_SFSRx_SFW30_Pos)              /*!< 0x40000000 */
+#define BSEC_SFSRx_SFW30               BSEC_SFSRx_SFW30_Msk                        /*!< Shadowed fuse word (30+32*x) */
+#define BSEC_SFSRx_SFW31_Pos           (31U)
+#define BSEC_SFSRx_SFW31_Msk           (0x1UL << BSEC_SFSRx_SFW31_Pos)              /*!< 0x80000000 */
+#define BSEC_SFSRx_SFW31               BSEC_SFSRx_SFW31_Msk                        /*!< Shadowed fuse word (31+32*x) */
+
+/******************  Bit definition for BSEC_OTPCR register  ******************/
+#define BSEC_OTPCR_ADDR_Pos            (0U)
+#define BSEC_OTPCR_ADDR_Msk            (0x1FFUL << BSEC_OTPCR_ADDR_Pos)             /*!< 0x000001FF */
+#define BSEC_OTPCR_ADDR                BSEC_OTPCR_ADDR_Msk                         /*!< Fuse word address */
+#define BSEC_OTPCR_PROG_Pos            (13U)
+#define BSEC_OTPCR_PROG_Msk            (0x1UL << BSEC_OTPCR_PROG_Pos)               /*!< 0x00002000 */
+#define BSEC_OTPCR_PROG                BSEC_OTPCR_PROG_Msk                         /*!< Fuse word programming */
+#define BSEC_OTPCR_PPLOCK_Pos          (14U)
+#define BSEC_OTPCR_PPLOCK_Msk          (0x1UL << BSEC_OTPCR_PPLOCK_Pos)             /*!< 0x00004000 */
+#define BSEC_OTPCR_PPLOCK              BSEC_OTPCR_PPLOCK_Msk                       /*!< Permanent programming lock */
+#define BSEC_OTPCR_LASTCID_Pos         (19U)
+#define BSEC_OTPCR_LASTCID_Msk         (0x7UL << BSEC_OTPCR_LASTCID_Pos)            /*!< 0x00380000 */
+#define BSEC_OTPCR_LASTCID             BSEC_OTPCR_LASTCID_Msk                      /*!< Last CID */
+
+/*******************  Bit definition for BSEC_WDR register  *******************/
+#define BSEC_WDR_WRDATA_Pos            (0U)
+#define BSEC_WDR_WRDATA_Msk            (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos)        /*!< 0xFFFFFFFF */
+#define BSEC_WDR_WRDATA                BSEC_WDR_WRDATA_Msk                         /*!< OTP write data */
+
+/****************  Bit definition for BSEC_SCRATCHRx register  ****************/
+#define BSEC_SCRATCHRx_SDATA_Pos       (0U)
+#define BSEC_SCRATCHRx_SDATA_Msk       (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_SCRATCHRx_SDATA           BSEC_SCRATCHRx_SDATA_Msk                    /*!< Scratch data */
+
+/******************  Bit definition for BSEC_LOCKR register  ******************/
+#define BSEC_LOCKR_GWLOCK_Pos          (0U)
+#define BSEC_LOCKR_GWLOCK_Msk          (0x1UL << BSEC_LOCKR_GWLOCK_Pos)             /*!< 0x00000001 */
+#define BSEC_LOCKR_GWLOCK              BSEC_LOCKR_GWLOCK_Msk                       /*!< Global write lock */
+#define BSEC_LOCKR_HKLOCK_Pos          (2U)
+#define BSEC_LOCKR_HKLOCK_Msk          (0x1UL << BSEC_LOCKR_HKLOCK_Pos)             /*!< 0x00000004 */
+#define BSEC_LOCKR_HKLOCK              BSEC_LOCKR_HKLOCK_Msk                       /*!< Hardware key lock */
+
+/*****************  Bit definition for BSEC_JTAGINR register  *****************/
+#define BSEC_JTAGINR_JDATAIN_Pos       (0U)
+#define BSEC_JTAGINR_JDATAIN_Msk       (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos)   /*!< 0xFFFFFFFF */
+#define BSEC_JTAGINR_JDATAIN           BSEC_JTAGINR_JDATAIN_Msk                    /*!< JTAG input data */
+
+/****************  Bit definition for BSEC_JTAGOUTR register  *****************/
+#define BSEC_JTAGOUTR_JDATAOUT_Pos     (0U)
+#define BSEC_JTAGOUTR_JDATAOUT_Msk     (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define BSEC_JTAGOUTR_JDATAOUT         BSEC_JTAGOUTR_JDATAOUT_Msk                  /*!< JTAG output data */
+
+/*****************  Bit definition for BSEC_UNMAPR register  ******************/
+#define BSEC_UNMAPR_UNMAP_Pos          (0U)
+#define BSEC_UNMAPR_UNMAP_Msk          (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos)      /*!< 0xFFFFFFFF */
+#define BSEC_UNMAPR_UNMAP              BSEC_UNMAPR_UNMAP_Msk                       /*!< Unmap key */
+
+/*******************  Bit definition for BSEC_SR register  ********************/
+#define BSEC_SR_HVALID_Pos             (1U)
+#define BSEC_SR_HVALID_Msk             (0x1UL << BSEC_SR_HVALID_Pos)                /*!< 0x00000002 */
+#define BSEC_SR_HVALID                 BSEC_SR_HVALID_Msk                          /*!< Hardware key valid */
+#define BSEC_SR_DBGREQ_Pos             (16U)
+#define BSEC_SR_DBGREQ_Msk             (0x1UL << BSEC_SR_DBGREQ_Pos)                /*!< 0x00010000 */
+#define BSEC_SR_DBGREQ                 BSEC_SR_DBGREQ_Msk                          /*!< Debug request */
+#define BSEC_SR_NVSTATE_Pos            (26U)
+#define BSEC_SR_NVSTATE_Msk            (0x3FUL << BSEC_SR_NVSTATE_Pos)              /*!< 0xFC000000 */
+#define BSEC_SR_NVSTATE                BSEC_SR_NVSTATE_Msk                         /*!< Non-volatile state */
+
+/******************  Bit definition for BSEC_OTPSR register  ******************/
+#define BSEC_OTPSR_BUSY_Pos            (0U)
+#define BSEC_OTPSR_BUSY_Msk            (0x1UL << BSEC_OTPSR_BUSY_Pos)               /*!< 0x00000001 */
+#define BSEC_OTPSR_BUSY                BSEC_OTPSR_BUSY_Msk                         /*!< Busy flag */
+#define BSEC_OTPSR_INIT_DONE_Pos       (1U)
+#define BSEC_OTPSR_INIT_DONE_Msk       (0x1UL << BSEC_OTPSR_INIT_DONE_Pos)          /*!< 0x00000002 */
+#define BSEC_OTPSR_INIT_DONE           BSEC_OTPSR_INIT_DONE_Msk                    /*!< Initialization done */
+#define BSEC_OTPSR_HIDEUP_Pos          (2U)
+#define BSEC_OTPSR_HIDEUP_Msk          (0x1UL << BSEC_OTPSR_HIDEUP_Pos)             /*!< 0x00000004 */
+#define BSEC_OTPSR_HIDEUP              BSEC_OTPSR_HIDEUP_Msk                       /*!< Hide upper fuse words */
+#define BSEC_OTPSR_OTPNVIR_Pos         (4U)
+#define BSEC_OTPSR_OTPNVIR_Msk         (0x1UL << BSEC_OTPSR_OTPNVIR_Pos)            /*!< 0x00000010 */
+#define BSEC_OTPSR_OTPNVIR             BSEC_OTPSR_OTPNVIR_Msk                      /*!< OTP not virgin */
+#define BSEC_OTPSR_OTPERR_Pos          (5U)
+#define BSEC_OTPSR_OTPERR_Msk          (0x1UL << BSEC_OTPSR_OTPERR_Pos)             /*!< 0x00000020 */
+#define BSEC_OTPSR_OTPERR              BSEC_OTPSR_OTPERR_Msk                       /*!< OTP with error */
+#define BSEC_OTPSR_OTPSEC_Pos          (6U)
+#define BSEC_OTPSR_OTPSEC_Msk          (0x1UL << BSEC_OTPSR_OTPSEC_Pos)             /*!< 0x00000040 */
+#define BSEC_OTPSR_OTPSEC              BSEC_OTPSR_OTPSEC_Msk                       /*!< OTP with single error correction */
+#define BSEC_OTPSR_PROGFAIL_Pos        (16U)
+#define BSEC_OTPSR_PROGFAIL_Msk        (0x1UL << BSEC_OTPSR_PROGFAIL_Pos)           /*!< 0x00010000 */
+#define BSEC_OTPSR_PROGFAIL            BSEC_OTPSR_PROGFAIL_Msk                     /*!< Programming failed */
+#define BSEC_OTPSR_DISTURBF_Pos        (17U)
+#define BSEC_OTPSR_DISTURBF_Msk        (0x1UL << BSEC_OTPSR_DISTURBF_Pos)           /*!< 0x00020000 */
+#define BSEC_OTPSR_DISTURBF            BSEC_OTPSR_DISTURBF_Msk                     /*!< Disturb flag */
+#define BSEC_OTPSR_DEDF_Pos            (18U)
+#define BSEC_OTPSR_DEDF_Msk            (0x1UL << BSEC_OTPSR_DEDF_Pos)               /*!< 0x00040000 */
+#define BSEC_OTPSR_DEDF                BSEC_OTPSR_DEDF_Msk                         /*!< Double error detection flag */
+#define BSEC_OTPSR_SECF_Pos            (19U)
+#define BSEC_OTPSR_SECF_Msk            (0x1UL << BSEC_OTPSR_SECF_Pos)               /*!< 0x00080000 */
+#define BSEC_OTPSR_SECF                BSEC_OTPSR_SECF_Msk                         /*!< Single error correction flag */
+#define BSEC_OTPSR_PPLF_Pos            (20U)
+#define BSEC_OTPSR_PPLF_Msk            (0x1UL << BSEC_OTPSR_PPLF_Pos)               /*!< 0x00100000 */
+#define BSEC_OTPSR_PPLF                BSEC_OTPSR_PPLF_Msk                         /*!< Permanent programming lock flag */
+#define BSEC_OTPSR_PPLMF_Pos           (21U)
+#define BSEC_OTPSR_PPLMF_Msk           (0x1UL << BSEC_OTPSR_PPLMF_Pos)              /*!< 0x00200000 */
+#define BSEC_OTPSR_PPLMF               BSEC_OTPSR_PPLMF_Msk                        /*!< Permanent programming lock mismatch flag */
+#define BSEC_OTPSR_AMEF_Pos            (22U)
+#define BSEC_OTPSR_AMEF_Msk            (0x1UL << BSEC_OTPSR_AMEF_Pos)               /*!< 0x00400000 */
+#define BSEC_OTPSR_AMEF                BSEC_OTPSR_AMEF_Msk                         /*!< Addresses mismatch error flag */
+
+/*****************  Bit definition for BSEC_EPOCHRx register  *****************/
+#define BSEC_EPOCHRx_EPOCH_Pos         (0U)
+#define BSEC_EPOCHRx_EPOCH_Msk         (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos)     /*!< 0xFFFFFFFF */
+#define BSEC_EPOCHRx_EPOCH             BSEC_EPOCHRx_EPOCH_Msk                      /*!< Epoch */
+
+/****************  Bit definition for BSEC_EPOCHSELR register  ****************/
+#define BSEC_EPOCHSELR_EPSEL_Pos       (0U)
+#define BSEC_EPOCHSELR_EPSEL_Msk       (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos)          /*!< 0x00000001 */
+#define BSEC_EPOCHSELR_EPSEL           BSEC_EPOCHSELR_EPSEL_Msk                    /*!< Epoch selection */
+
+/******************  Bit definition for BSEC_DBGCR register  ******************/
+#define BSEC_DBGCR_UNLOCK_Pos          (8U)
+#define BSEC_DBGCR_UNLOCK_Msk          (0xFFUL << BSEC_DBGCR_UNLOCK_Pos)            /*!< 0x0000FF00 */
+#define BSEC_DBGCR_UNLOCK              BSEC_DBGCR_UNLOCK_Msk                       /*!< Non-secure debug authorization */
+#define BSEC_DBGCR_AUTH_HDPL_Pos       (16U)
+#define BSEC_DBGCR_AUTH_HDPL_Msk       (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos)         /*!< 0x00FF0000 */
+#define BSEC_DBGCR_AUTH_HDPL           BSEC_DBGCR_AUTH_HDPL_Msk                    /*!< Level at which debug may be opened */
+#define BSEC_DBGCR_AUTH_SEC_Pos        (24U)
+#define BSEC_DBGCR_AUTH_SEC_Msk        (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos)          /*!< 0xFF000000 */
+#define BSEC_DBGCR_AUTH_SEC            BSEC_DBGCR_AUTH_SEC_Msk                     /*!< Secure debug authorization */
+
+/***************  Bit definition for BSEC_AP_UNLOCK register  *****************/
+#define BSEC_AP_UNLOCK_UNLOCK_Pos      (0U)
+#define BSEC_AP_UNLOCK_UNLOCK_Msk      (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos)        /*!< 0x000000FF */
+#define BSEC_AP_UNLOCK_UNLOCK          BSEC_AP_UNLOCK_UNLOCK_Msk                   /*!< Unlock DBG_MCU AP interface */
+
+/*****************  Bit definition for BSEC_HDPLSR register  ******************/
+#define BSEC_HDPLSR_HDPL_Pos           (0U)
+#define BSEC_HDPLSR_HDPL_Msk           (0xFFUL << BSEC_HDPLSR_HDPL_Pos)             /*!< 0x000000FF */
+#define BSEC_HDPLSR_HDPL               BSEC_HDPLSR_HDPL_Msk                        /*!< Current HDPL */
+
+/*****************  Bit definition for BSEC_HDPLCR register  ******************/
+#define BSEC_HDPLCR_INCR_HDPL_Pos      (0U)
+#define BSEC_HDPLCR_INCR_HDPL_Msk      (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos)  /*!< 0xFFFFFFFF */
+#define BSEC_HDPLCR_INCR_HDPL          BSEC_HDPLCR_INCR_HDPL_Msk                   /*!< Increment HDPL */
+
+/*****************  Bit definition for BSEC_NEXTLR register  ******************/
+#define BSEC_NEXTLR_INCR_Pos           (0U)
+#define BSEC_NEXTLR_INCR_Msk           (0x3UL << BSEC_NEXTLR_INCR_Pos)              /*!< 0x00000003 */
+#define BSEC_NEXTLR_INCR               BSEC_NEXTLR_INCR_Msk                        /*!< Increment */
+
+/*****************  Bit definition for BSEC_WOSCRx register  ******************/
+#define BSEC_WOSCRx_WOSDATA_Pos        (0U)
+#define BSEC_WOSCRx_WOSDATA_Msk        (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos)    /*!< 0xFFFFFFFF */
+#define BSEC_WOSCRx_WOSDATA            BSEC_WOSCRx_WOSDATA_Msk                     /*!< Write once scratch data */
+
+/******************  Bit definition for BSEC_HRCR register  *******************/
+#define BSEC_HRCR_HRC_Pos              (0U)
+#define BSEC_HRCR_HRC_Msk              (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_HRCR_HRC                  BSEC_HRCR_HRC_Msk                           /*!< Hot reset counter */
+
+/******************  Bit definition for BSEC_WRCR register  *******************/
+#define BSEC_WRCR_WRC_Pos              (0U)
+#define BSEC_WRCR_WRC_Msk              (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos)          /*!< 0xFFFFFFFF */
+#define BSEC_WRCR_WRC                  BSEC_WRCR_WRC_Msk                           /*!< Warm reset counter */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 CACHEAXI                                   */
+/*                                                                            */
+/******************************************************************************/
+/****************  Bit definition for CACHEAXI_CR1 register  ******************/
+#define CACHEAXI_CR1_EN_Pos                   (0U)
+#define CACHEAXI_CR1_EN_Msk                   (0x1UL << CACHEAXI_CR1_EN_Pos)             /*!< 0x00000001 */
+#define CACHEAXI_CR1_EN                       CACHEAXI_CR1_EN_Msk                        /*!< Enable */
+#define CACHEAXI_CR1_CACHEINV_Pos             (1U)
+#define CACHEAXI_CR1_CACHEINV_Msk             (0x1UL << CACHEAXI_CR1_CACHEINV_Pos)       /*!< 0x00000002 */
+#define CACHEAXI_CR1_CACHEINV                 CACHEAXI_CR1_CACHEINV_Msk                  /*!< Cache invalidation */
+#define CACHEAXI_CR1_RHITMEN_Pos              (16U)
+#define CACHEAXI_CR1_RHITMEN_Msk              (0x1UL << CACHEAXI_CR1_RHITMEN_Pos)        /*!< 0x00010000 */
+#define CACHEAXI_CR1_RHITMEN                  CACHEAXI_CR1_RHITMEN_Msk                   /*!< Read Hit monitor enable */
+#define CACHEAXI_CR1_RMISSMEN_Pos             (17U)
+#define CACHEAXI_CR1_RMISSMEN_Msk             (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos)       /*!< 0x00020000 */
+#define CACHEAXI_CR1_RMISSMEN                 CACHEAXI_CR1_RMISSMEN_Msk                  /*!< Read Miss monitor enable */
+#define CACHEAXI_CR1_RHITMRST_Pos             (18U)
+#define CACHEAXI_CR1_RHITMRST_Msk             (0x1UL << CACHEAXI_CR1_RHITMRST_Pos)       /*!< 0x00040000 */
+#define CACHEAXI_CR1_RHITMRST                 CACHEAXI_CR1_RHITMRST_Msk                  /*!< Read Hit monitor reset */
+#define CACHEAXI_CR1_RMISSMRST_Pos            (19U)
+#define CACHEAXI_CR1_RMISSMRST_Msk            (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos)      /*!< 0x00080000 */
+#define CACHEAXI_CR1_RMISSMRST                CACHEAXI_CR1_RMISSMRST_Msk                 /*!< Read Miss monitor reset */
+#define CACHEAXI_CR1_WHITMEN_Pos              (20U)
+#define CACHEAXI_CR1_WHITMEN_Msk              (0x1UL << CACHEAXI_CR1_WHITMEN_Pos)        /*!< 0x00100000 */
+#define CACHEAXI_CR1_WHITMEN                  CACHEAXI_CR1_WHITMEN_Msk                   /*!< Write Hit monitor enable */
+#define CACHEAXI_CR1_WMISSMEN_Pos             (21U)
+#define CACHEAXI_CR1_WMISSMEN_Msk             (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos)       /*!< 0x00200000 */
+#define CACHEAXI_CR1_WMISSMEN                 CACHEAXI_CR1_WMISSMEN_Msk                  /*!< Write Miss monitor enable */
+#define CACHEAXI_CR1_WHITMRST_Pos             (22U)
+#define CACHEAXI_CR1_WHITMRST_Msk             (0x1UL << CACHEAXI_CR1_WHITMRST_Pos)       /*!< 0x00400000 */
+#define CACHEAXI_CR1_WHITMRST                 CACHEAXI_CR1_WHITMRST_Msk                  /*!< Write Hit monitor reset */
+#define CACHEAXI_CR1_WMISSMRST_Pos            (23U)
+#define CACHEAXI_CR1_WMISSMRST_Msk            (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos)      /*!< 0x00800000 */
+#define CACHEAXI_CR1_WMISSMRST                CACHEAXI_CR1_WMISSMRST_Msk                 /*!< Write Miss monitor reset */
+#define CACHEAXI_CR1_RAMMEN_Pos               (24U)
+#define CACHEAXI_CR1_RAMMEN_Msk               (0x1UL << CACHEAXI_CR1_RAMMEN_Pos)         /*!< 0x01000000 */
+#define CACHEAXI_CR1_RAMMEN                   CACHEAXI_CR1_RAMMEN_Msk                    /*!< Read-allocate miss monitor enable */
+#define CACHEAXI_CR1_WAMMEN_Pos               (25U)
+#define CACHEAXI_CR1_WAMMEN_Msk               (0x1UL << CACHEAXI_CR1_WAMMEN_Pos)         /*!< 0x02000000 */
+#define CACHEAXI_CR1_WAMMEN                   CACHEAXI_CR1_WAMMEN_Msk                    /*!< Write-allocate miss monitor enable */
+#define CACHEAXI_CR1_RAMMRST_Pos              (26U)
+#define CACHEAXI_CR1_RAMMRST_Msk              (0x1UL << CACHEAXI_CR1_RAMMRST_Pos)        /*!< 0x04000000 */
+#define CACHEAXI_CR1_RAMMRST                  CACHEAXI_CR1_RAMMRST_Msk                   /*!< Read-allocate miss monitor reset */
+#define CACHEAXI_CR1_WAMMRST_Pos              (27U)
+#define CACHEAXI_CR1_WAMMRST_Msk              (0x1UL << CACHEAXI_CR1_WAMMRST_Pos)        /*!< 0x08000000 */
+#define CACHEAXI_CR1_WAMMRST                  CACHEAXI_CR1_WAMMRST_Msk                   /*!< Write-allocate miss monitor reset */
+#define CACHEAXI_CR1_WTMEN_Pos                (28U)
+#define CACHEAXI_CR1_WTMEN_Msk                (0x1UL << CACHEAXI_CR1_WTMEN_Pos)          /*!< 0x10000000 */
+#define CACHEAXI_CR1_WTMEN                    CACHEAXI_CR1_WTMEN_Msk                     /*!< Write-through monitor enable */
+#define CACHEAXI_CR1_EVIMEN_Pos               (29U)
+#define CACHEAXI_CR1_EVIMEN_Msk               (0x1UL << CACHEAXI_CR1_EVIMEN_Pos)         /*!< 0x20000000 */
+#define CACHEAXI_CR1_EVIMEN                   CACHEAXI_CR1_EVIMEN_Msk                    /*!< Eviction monitor enable */
+#define CACHEAXI_CR1_WTMRST_Pos               (30U)
+#define CACHEAXI_CR1_WTMRST_Msk               (0x1UL << CACHEAXI_CR1_WTMRST_Pos)         /*!< 0x40000000 */
+#define CACHEAXI_CR1_WTMRST                   CACHEAXI_CR1_WTMRST_Msk                    /*!< Write-through monitor reset */
+#define CACHEAXI_CR1_EVIMRST_Pos              (31U)
+#define CACHEAXI_CR1_EVIMRST_Msk              (0x1UL << CACHEAXI_CR1_EVIMRST_Pos)        /*!< 0x80000000 */
+#define CACHEAXI_CR1_EVIMRST                  CACHEAXI_CR1_EVIMRST_Msk                   /*!< Eviction monitor reset */
+
+/******************  Bit definition for CACHEAXI_SR register  *******************/
+#define CACHEAXI_SR_BUSYF_Pos                 (0U)
+#define CACHEAXI_SR_BUSYF_Msk                 (0x1UL << CACHEAXI_SR_BUSYF_Pos)           /*!< 0x00000001 */
+#define CACHEAXI_SR_BUSYF                     CACHEAXI_SR_BUSYF_Msk                      /*!< Busy flag */
+#define CACHEAXI_SR_BSYENDF_Pos               (1U)
+#define CACHEAXI_SR_BSYENDF_Msk               (0x1UL << CACHEAXI_SR_BSYENDF_Pos)         /*!< 0x00000002 */
+#define CACHEAXI_SR_BSYENDF                   CACHEAXI_SR_BSYENDF_Msk                    /*!< Busy end flag */
+#define CACHEAXI_SR_ERRF_Pos                  (2U)
+#define CACHEAXI_SR_ERRF_Msk                  (0x1UL << CACHEAXI_SR_ERRF_Pos)            /*!< 0x00000004 */
+#define CACHEAXI_SR_ERRF                      CACHEAXI_SR_ERRF_Msk                       /*!< Cache error flag */
+#define CACHEAXI_SR_BUSYCMDF_Pos              (3U)
+#define CACHEAXI_SR_BUSYCMDF_Msk              (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos)        /*!< 0x00000008 */
+#define CACHEAXI_SR_BUSYCMDF                  CACHEAXI_SR_BUSYCMDF_Msk                   /*!< Busy command flag */
+#define CACHEAXI_SR_CMDENDF_Pos               (4U)
+#define CACHEAXI_SR_CMDENDF_Msk               (0x1UL << CACHEAXI_SR_CMDENDF_Pos)         /*!< 0x00000010 */
+#define CACHEAXI_SR_CMDENDF                   CACHEAXI_SR_CMDENDF_Msk                    /*!< Command end flag */
+
+/******************  Bit definition for CACHEAXI_IER register  ******************/
+#define CACHEAXI_IER_BSYENDIE_Pos             (1U)
+#define CACHEAXI_IER_BSYENDIE_Msk             (0x1UL << CACHEAXI_IER_BSYENDIE_Pos)       /*!< 0x00000002 */
+#define CACHEAXI_IER_BSYENDIE                 CACHEAXI_IER_BSYENDIE_Msk                  /*!< Busy end interrupt enable */
+#define CACHEAXI_IER_ERRIE_Pos                (2U)
+#define CACHEAXI_IER_ERRIE_Msk                (0x1UL << CACHEAXI_IER_ERRIE_Pos)          /*!< 0x00000004 */
+#define CACHEAXI_IER_ERRIE                    CACHEAXI_IER_ERRIE_Msk                     /*!< Cache error interrupt enable */
+#define CACHEAXI_IER_CMDENDIE_Pos             (4U)
+#define CACHEAXI_IER_CMDENDIE_Msk             (0x1UL << CACHEAXI_IER_CMDENDIE_Pos)       /*!< 0x00000010 */
+#define CACHEAXI_IER_CMDENDIE                 CACHEAXI_IER_CMDENDIE_Msk                  /*!< Command end interrupt enable */
+
+/******************  Bit definition for CACHEAXI_FCR register  ******************/
+#define CACHEAXI_FCR_CBSYENDF_Pos             (1U)
+#define CACHEAXI_FCR_CBSYENDF_Msk             (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos)       /*!< 0x00000002 */
+#define CACHEAXI_FCR_CBSYENDF                 CACHEAXI_FCR_CBSYENDF_Msk                  /*!< Busy end flag clear */
+#define CACHEAXI_FCR_CERRF_Pos                (2U)
+#define CACHEAXI_FCR_CERRF_Msk                (0x1UL << CACHEAXI_FCR_CERRF_Pos)          /*!< 0x00000004 */
+#define CACHEAXI_FCR_CERRF                    CACHEAXI_FCR_CERRF_Msk                     /*!< Cache error flag clear */
+#define CACHEAXI_FCR_CCMDENDF_Pos             (4U)
+#define CACHEAXI_FCR_CCMDENDF_Msk             (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos)       /*!< 0x00000010 */
+#define CACHEAXI_FCR_CCMDENDF                 CACHEAXI_FCR_CCMDENDF_Msk                  /*!< Command end flag clear */
+
+/******************  Bit definition for CACHEAXI_RHMONR register  ****************/
+#define CACHEAXI_RHMONR_RHITMON_Pos           (0U)
+#define CACHEAXI_RHMONR_RHITMON_Msk           (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_RHMONR_RHITMON               CACHEAXI_RHMONR_RHITMON_Msk                    /*!< Cache read hit monitor register */
+
+/******************  Bit definition for CACHEAXI_RMMONR register  ****************/
+#define CACHEAXI_RMMONR_RMISSMON_Pos          (0U)
+#define CACHEAXI_RMMONR_RMISSMON_Msk          (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */
+#define CACHEAXI_RMMONR_RMISSMON              CACHEAXI_RMMONR_RMISSMON_Msk                   /*!< Cache read miss monitor register */
+
+/******************  Bit definition for CACHEAXI_RAMMONR register  ****************/
+#define CACHEAXI_RAMMONR_RAMMON_Pos           (0U)
+#define CACHEAXI_RAMMONR_RAMMON_Msk           (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_RAMMONR_RAMMON               CACHEAXI_RAMMONR_RAMMON_Msk                    /*!< Cache read-allocate miss monitor counter */
+
+/******************  Bit definition for CACHEAXI_EVIMONR register  ****************/
+#define CACHEAXI_EVIMONR_EVIMON_Pos           (0U)
+#define CACHEAXI_EVIMONR_EVIMON_Msk           (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_EVIMONR_EVIMON               CACHEAXI_EVIMONR_EVIMON_Msk                    /*!< Cache eviction monitor counter */
+
+/******************  Bit definition for CACHEAXI_WHMONR register  ****************/
+#define CACHEAXI_WHMONR_WHITMON_Pos           (0U)
+#define CACHEAXI_WHMONR_WHITMON_Msk           (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_WHMONR_WHITMON               CACHEAXI_WHMONR_WHITMON_Msk                    /*!< Cache write hit monitor register */
+
+/******************  Bit definition for CACHEAXI_WMMONR register  ****************/
+#define CACHEAXI_WMMONR_WMISSMON_Pos          (0U)
+#define CACHEAXI_WMMONR_WMISSMON_Msk          (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */
+#define CACHEAXI_WMMONR_WMISSMON              CACHEAXI_WMMONR_WMISSMON_Msk                   /*!< Cache write miss monitor register */
+
+/******************  Bit definition for CACHEAXI_WAMMONR register  ****************/
+#define CACHEAXI_WAMMONR_WAMMON_Pos           (0U)
+#define CACHEAXI_WAMMONR_WAMMON_Msk           (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos)  /*!< 0xFFFFFFFF */
+#define CACHEAXI_WAMMONR_WAMMON               CACHEAXI_WAMMONR_WAMMON_Msk                    /*!< Cache write-allocate miss monitor register */
+
+/******************  Bit definition for CACHEAXI_WTMONR register  ****************/
+#define CACHEAXI_WTMONR_WTMON_Pos             (0U)
+#define CACHEAXI_WTMONR_WTMON_Msk             (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos)    /*!< 0xFFFFFFFF */
+#define CACHEAXI_WTMONR_WTMON                 CACHEAXI_WTMONR_WTMON_Msk                      /*!< Cache write-through monitor register */
+
+/****************  Bit definition for CACHEAXI_CR2 register  ******************/
+#define CACHEAXI_CR2_STARTCMD_Pos             (0U)
+#define CACHEAXI_CR2_STARTCMD_Msk             (0x1UL << CACHEAXI_CR2_STARTCMD_Pos)           /*!< 0x00000001 */
+#define CACHEAXI_CR2_STARTCMD                 CACHEAXI_CR2_STARTCMD_Msk                      /*!< Starts maintenance range command */
+#define CACHEAXI_CR2_CACHECMD_Pos             (1U)
+#define CACHEAXI_CR2_CACHECMD_Msk             (0x3UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000006 */
+#define CACHEAXI_CR2_CACHECMD                 CACHEAXI_CR2_CACHECMD_Msk                      /*!< Cache command maintenance operation */
+#define CACHEAXI_CR2_CACHECMD_0               (0x1UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000002 */
+#define CACHEAXI_CR2_CACHECMD_1               (0x2UL << CACHEAXI_CR2_CACHECMD_Pos)           /*!< 0x00000004 */
+
+/******************  Bit definition for CACHEAXI_CMDRSADDRR register  ****************/
+#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos  (0U)
+#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk  (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */
+#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR      CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk           /*!< Command start address */
+
+/******************  Bit definition for CACHEAXI_CMDREADDRR register  ****************/
+#define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos    (0U)
+#define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk    (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos)   /*!< 0xFFFFFFC0 */
+#define CACHEAXI_CMDREADDRR_CMDENDADDR        CACHEAXI_CMDREADDRR_CMDENDADDR_Msk             /*!< Command end address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos              (0U)
+#define CRC_DR_DR_Msk              (0xFFFFFFFFUL << CRC_DR_DR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                  CRC_DR_DR_Msk                               /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos            (0U)
+#define CRC_IDR_IDR_Msk            (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR                CRC_IDR_IDR_Msk                             /*!< General-purpose 32-bits data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos           (0U)
+#define CRC_CR_RESET_Msk           (0x1UL << CRC_CR_RESET_Pos)                 /*!< 0x00000001 */
+#define CRC_CR_RESET               CRC_CR_RESET_Msk                            /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos        (3U)
+#define CRC_CR_POLYSIZE_Msk        (0x3UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE            CRC_CR_POLYSIZE_Msk                         /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0          (0x1UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1          (0x2UL << CRC_CR_POLYSIZE_Pos)              /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos          (5U)
+#define CRC_CR_REV_IN_Msk          (0x3UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000060 */
+#define CRC_CR_REV_IN              CRC_CR_REV_IN_Msk                           /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0            (0x1UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1            (0x2UL << CRC_CR_REV_IN_Pos)                /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos         (7U)
+#define CRC_CR_REV_OUT_Msk         (0x3UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000180 */
+#define CRC_CR_REV_OUT             CRC_CR_REV_OUT_Msk                          /*!< REV_OUT Reverse Output Data bits */
+#define CRC_CR_REV_OUT_0           (0x1UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000080 */
+#define CRC_CR_REV_OUT_1           (0x2UL << CRC_CR_REV_OUT_Pos)               /*!< 0x00000100 */
+#define CRC_CR_RTYPE_IN_Pos        (9U)
+#define CRC_CR_RTYPE_IN_Msk        (0x1UL << CRC_CR_RTYPE_IN_Pos)              /*!< 0x00000200 */
+#define CRC_CR_RTYPE_IN            CRC_CR_RTYPE_IN_Msk                         /*!< Reverse type input */
+#define CRC_CR_RTYPE_OUT_Pos       (10U)
+#define CRC_CR_RTYPE_OUT_Msk       (0x1UL << CRC_CR_RTYPE_OUT_Pos)             /*!< 0x00000400 */
+#define CRC_CR_RTYPE_OUT           CRC_CR_RTYPE_OUT_Msk                        /*!< Reverse type output*/
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos          (0U)
+#define CRC_INIT_INIT_Msk          (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)         /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT              CRC_INIT_INIT_Msk                           /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos            (0U)
+#define CRC_POL_POL_Msk            (0xFFFFFFFFUL << CRC_POL_POL_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_POL_POL                CRC_POL_POL_Msk                             /*!< Coefficients of the polynomial */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Cryp Processor                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register  ********************/
+#define CRYP_CR_ALGODIR_Pos              (2U)
+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)           /*!< 0x00000004 */
+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk                      /*!< Algorithm direction (Encrypt/Decrypt) */
+
+#define CRYP_CR_ALGOMODE_Pos             (3U)
+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080038 */
+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk                     /*!< Algorithm mode */
+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_3               (0x10000UL << CRYP_CR_ALGOMODE_Pos)      /*!< 0x00080000 */
+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)  /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)  /*!< 0x00000028 */
+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)  /*!< 0x00000030 */
+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)  /*!< 0x00000038 */
+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)
+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)  /*!< 0x00080000 */
+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk
+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)
+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk
+
+#define CRYP_CR_DATATYPE_Pos             (6U)
+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x000000C0 */
+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk                     /*!< Data Type selection */
+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000040 */
+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)          /*!< 0x00000080 */
+#define CRYP_CR_KEYSIZE_Pos              (8U)
+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000300 */
+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk                      /*!< Key Size selection */
+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000100 */
+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)           /*!< 0x00000200 */
+#define CRYP_CR_FFLUSH_Pos               (14U)
+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)            /*!< 0x00004000 */
+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk                       /*!< CRYP FIFO Flush */
+#define CRYP_CR_CRYPEN_Pos               (15U)
+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)            /*!< 0x00008000 */
+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk                       /*!< CRYP processor enable */
+
+#define CRYP_CR_GCM_CCMPH_Pos            (16U)
+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00030000 */
+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk                    /*!< GCM or CCM Phase selection */
+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00010000 */
+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)         /*!< 0x00020000 */
+
+#define CRYP_CR_NPBLB_Pos                (20U)
+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)             /*!< 0x00F00000 */
+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk                        /*!< Number of Padding Bytes in Last Block of payload */
+
+#define CRYP_CR_KMOD_Pos                (24U)
+#define CRYP_CR_KMOD_Msk                (0x3UL << CRYP_CR_KMOD_Pos)               /*!< 0x03000000 */
+#define CRYP_CR_KMOD                    CRYP_CR_KMOD_Msk                          /*!< Key mode selection */
+#define CRYP_CR_KMOD_0                  (0x1UL << CRYP_CR_KMOD_Pos)               /*!< 0x01000000 */
+#define CRYP_CR_KMOD_1                  (0x2UL << CRYP_CR_KMOD_Pos)               /*!< 0x02000000 */
+
+#define CRYP_CR_IPRST_Pos               (31U)
+#define CRYP_CR_IPRST_Msk               (0x1UL << CRYP_CR_IPRST_Pos)              /*!< 0x80000000 */
+#define CRYP_CR_IPRST                   CRYP_CR_IPRST_Msk                         /*!< CRYP peripheral software reset */
+
+/****************** Bits definition for CRYP_SR register  *********************/
+#define CRYP_SR_IFEM_Pos                 (0U)
+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)              /*!< 0x00000001 */
+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk                         /*!< Input FIFO empty flag */
+#define CRYP_SR_IFNF_Pos                 (1U)
+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)              /*!< 0x00000002 */
+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk                         /*!< Input FIFO not full flag */
+#define CRYP_SR_OFNE_Pos                 (2U)
+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)              /*!< 0x00000004 */
+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk                         /*!< Output FIFO not empty flag */
+#define CRYP_SR_OFFU_Pos                 (3U)
+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)              /*!< 0x00000008 */
+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk                         /*!< Output FIFO full flag */
+#define CRYP_SR_BUSY_Pos                 (4U)
+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)              /*!< 0x00000010 */
+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk                         /*!< Busy bit */
+#define CRYP_SR_KERF_Pos                 (6U)
+#define CRYP_SR_KERF_Msk                 (0x1UL << CRYP_SR_KERF_Pos)              /*!< 0x00000040 */
+#define CRYP_SR_KERF                     CRYP_SR_KERF_Msk                         /*!< Key error flag */
+#define CRYP_SR_KEYVALID_Pos             (7U)
+#define CRYP_SR_KEYVALID_Msk             (0x1UL << CRYP_SR_KEYVALID_Pos)          /*!< 0x00000080 */
+#define CRYP_SR_KEYVALID                 CRYP_SR_KEYVALID_Msk                     /*!< Key valid flag */
+
+/*******************  Bit definition for CRYP_DIN register  *******************/
+#define CRYP_DIN_DATAIN_Pos              (0U)
+#define CRYP_DIN_DATAIN_Msk              (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos)    /*!< 0xFFFFFFFF */
+#define CRYP_DIN_DATAIN                  CRYP_DIN_DATAIN_Msk                      /*!< CRYP Data Input */
+
+/*******************  Bit definition for CRYP_DIN register  *******************/
+#define CRYP_DOUT_DATAOUT_Pos            (0U)
+#define CRYP_DOUT_DATAOUT_Msk            (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos)  /*!< 0xFFFFFFFF */
+#define CRYP_DOUT_DATAOUT                CRYP_DOUT_DATAOUT_Msk                    /*!< CRYP Data Output */
+
+/****************** Bits definition for CRYP_DMACR register  ******************/
+#define CRYP_DMACR_DIEN_Pos              (0U)
+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)           /*!< 0x00000001 */
+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk                      /*!< DMA Input Enable */
+#define CRYP_DMACR_DOEN_Pos              (1U)
+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)           /*!< 0x00000002 */
+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk                      /*!< DMA Output Enable */
+
+/*****************  Bits definition for CRYP_IMSCR register  ******************/
+#define CRYP_IMSCR_INIM_Pos              (0U)
+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)           /*!< 0x00000001 */
+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk                      /*!< Input FIFO service interrupt mask */
+#define CRYP_IMSCR_OUTIM_Pos             (1U)
+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)          /*!< 0x00000002 */
+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk                     /*!< Output FIFO service interrupt mask */
+
+/****************** Bits definition for CRYP_RISR register  *******************/
+#define CRYP_RISR_INRIS_Pos              (0U)
+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)           /*!< 0x00000001 */
+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk                      /*!< Input FIFO service raw interrupt status */
+#define CRYP_RISR_OUTRIS_Pos             (1U)
+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)          /*!< 0x00000002 */
+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk                     /*!< Output FIFO service raw interrupt mask */
+
+/****************** Bits definition for CRYP_MISR register  *******************/
+#define CRYP_MISR_INMIS_Pos              (0U)
+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)           /*!< 0x00000001 */
+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk                      /*!< Input FIFO service masked interrupt status */
+#define CRYP_MISR_OUTMIS_Pos             (1U)
+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)          /*!< 0x00000002 */
+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk                     /*!< Output FIFO service masked interrupt status */
+
+/*******************  Bit definition for CRYP_K0LR register  ******************/
+#define CRYP_K0LR_K_Pos                  (0U)
+#define CRYP_K0LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K0LR_K                      CRYP_K0LR_K_Msk                          /*!< AES key bit x (x= 224 to 255) */
+
+/*******************  Bit definition for CRYP_K0RR register  ******************/
+#define CRYP_K0RR_K_Pos                  (0U)
+#define CRYP_K0RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K0RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K0RR_K                      CRYP_K0RR_K_Msk                          /*!< AES key bit x (x= 192 to 223) */
+
+/*******************  Bit definition for CRYP_IV1LR register  ******************/
+#define CRYP_IV1LR_K_Pos                  (0U)
+#define CRYP_IV1LR_K_Msk                  (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_IV1LR_K                      CRYP_IV1LR_K_Msk                          /*!< AES key bit x (x= 160 to 291) */
+
+/*******************  Bit definition for CRYP_IV1RR register  ******************/
+#define CRYP_IV1RR_K_Pos                  (0U)
+#define CRYP_IV1RR_K_Msk                  (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_IV1RR_K                      CRYP_IV1RR_K_Msk                          /*!< AES key bit x (x= 128 to 159) */
+
+/*******************  Bit definition for CRYP_K2LR register  ******************/
+#define CRYP_K2LR_K_Pos                  (0U)
+#define CRYP_K2LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K2LR_K                      CRYP_K2LR_K_Msk                          /*!< AES key bit x (x= 96 to 127) */
+
+/*******************  Bit definition for CRYP_K2RR register  ******************/
+#define CRYP_K2RR_K_Pos                  (0U)
+#define CRYP_K2RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K2RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K2RR_K                      CRYP_K2RR_K_Msk                          /*!< AES key bit x (x= 64 to 95) */
+
+/*******************  Bit definition for CRYP_K3LR register  ******************/
+#define CRYP_K3LR_K_Pos                  (0U)
+#define CRYP_K3LR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3LR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K3LR_K                      CRYP_K3LR_K_Msk                          /*!< AES key bit x (x= 32 to 63) */
+
+/*******************  Bit definition for CRYP_K3RR register  ******************/
+#define CRYP_K3RR_K_Pos                  (0U)
+#define CRYP_K3RR_K_Msk                  (0xFFFFFFFFUL << CRYP_K3RR_K_Pos)        /*!< 0xFFFFFFFF */
+#define CRYP_K3RR_K                      CRYP_K3RR_K_Msk                          /*!< AES key bit x (x= 0 to 31) */
+
+/*******************  Bit definition for CRYP_IV0LR register  ******************/
+#define CRYP_IV0LR_IV_Pos                (0U)
+#define CRYP_IV0LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV0LR_IV                    CRYP_IV0LR_IV_Msk                        /*!< Initialization vector bit x (x= 0 to 31) */
+
+/*******************  Bit definition for CRYP_IV0RR register  ******************/
+#define CRYP_IV0RR_IV_Pos                (0U)
+#define CRYP_IV0RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV0RR_IV                    CRYP_IV0RR_IV_Msk                        /*!< Initialization vector bit x (x= 32 to 63) */
+
+/*******************  Bit definition for CRYP_IV1LR register  ******************/
+#define CRYP_IV1LR_IV_Pos                (0U)
+#define CRYP_IV1LR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV1LR_IV                    CRYP_IV1LR_IV_Msk                        /*!< Initialization vector bit x (x= 64 to 95) */
+
+/*******************  Bit definition for CRYP_IV1RR register  ******************/
+#define CRYP_IV1RR_IV_Pos                (0U)
+#define CRYP_IV1RR_IV_Msk                (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos)      /*!< 0xFFFFFFFF */
+#define CRYP_IV1RR_IV                    CRYP_IV1RR_IV_Msk                        /*!< Initialization vector bit x (x= 96 to 127) */
+
+/*******************  Bit definition for CRYP_CSGCMCCM0R register  ******************/
+#define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos          (0U)
+#define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM0R_CSGCMCCM0              CRYP_CSGCMCCM0R_CSGCMCCM0_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM1R register  ******************/
+#define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos          (0U)
+#define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM1R_CSGCMCCM1              CRYP_CSGCMCCM1R_CSGCMCCM1_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM2R register  ******************/
+#define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos          (0U)
+#define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM2R_CSGCMCCM2              CRYP_CSGCMCCM2R_CSGCMCCM2_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM3R register  ******************/
+#define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos          (0U)
+#define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM3R_CSGCMCCM3              CRYP_CSGCMCCM3R_CSGCMCCM3_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM4R register  ******************/
+#define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos          (0U)
+#define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM4R_CSGCMCCM4              CRYP_CSGCMCCM4R_CSGCMCCM4_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM5R register  ******************/
+#define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos          (0U)
+#define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM5R_CSGCMCCM5              CRYP_CSGCMCCM5R_CSGCMCCM5_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM6R register  ******************/
+#define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos          (0U)
+#define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM6R_CSGCMCCM6              CRYP_CSGCMCCM6R_CSGCMCCM6_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCMCCM7R register  ******************/
+#define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos          (0U)
+#define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCMCCM7R_CSGCMCCM7              CRYP_CSGCMCCM7R_CSGCMCCM7_Msk                   /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
+
+/*******************  Bit definition for CRYP_CSGCM0R register  ******************/
+#define CRYP_CSGCM0R_CSGCM0_Pos          (0U)
+#define CRYP_CSGCM0R_CSGCM0_Msk          (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM0R_CSGCM0              CRYP_CSGCM0R_CSGCM0_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM1R register  ******************/
+#define CRYP_CSGCM1R_CSGCM1_Pos          (0U)
+#define CRYP_CSGCM1R_CSGCM1_Msk          (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM1R_CSGCM1              CRYP_CSGCM1R_CSGCM1_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM2R register  ******************/
+#define CRYP_CSGCM2R_CSGCM2_Pos          (0U)
+#define CRYP_CSGCM2R_CSGCM2_Msk          (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM2R_CSGCM2              CRYP_CSGCM2R_CSGCM2_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM3R register  ******************/
+#define CRYP_CSGCM3R_CSGCM3_Pos          (0U)
+#define CRYP_CSGCM3R_CSGCM3_Msk          (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM3R_CSGCM3              CRYP_CSGCM3R_CSGCM3_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM4R register  ******************/
+#define CRYP_CSGCM4R_CSGCM4_Pos          (0U)
+#define CRYP_CSGCM4R_CSGCM4_Msk          (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM4R_CSGCM4              CRYP_CSGCM4R_CSGCM4_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM5R register  ******************/
+#define CRYP_CSGCM5R_CSGCM5_Pos          (0U)
+#define CRYP_CSGCM5R_CSGCM5_Msk          (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM5R_CSGCM5              CRYP_CSGCM5R_CSGCM5_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM6R register  ******************/
+#define CRYP_CSGCM6R_CSGCM6_Pos          (0U)
+#define CRYP_CSGCM6R_CSGCM6_Msk          (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM6R_CSGCM6              CRYP_CSGCM6R_CSGCM6_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+/*******************  Bit definition for CRYP_CSGCM7R register  ******************/
+#define CRYP_CSGCM7R_CSGCM7_Pos          (0U)
+#define CRYP_CSGCM7R_CSGCM7_Msk          (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_CSGCM7R_CSGCM7              CRYP_CSGCM7R_CSGCM7_Msk                   /*!< CRYP internal state registers for GCM and GMAC modes */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (CSI)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CSI_CR register  ********************/
+#define CSI_CR_CSIEN_Pos                (0U)
+#define CSI_CR_CSIEN_Msk                (0x1UL << CSI_CR_CSIEN_Pos)               /*!< 0x00000001 */
+#define CSI_CR_CSIEN                    CSI_CR_CSIEN_Msk                         /*!< CSI-2 enable */
+#define CSI_CR_VC0START_Pos             (2U)
+#define CSI_CR_VC0START_Msk             (0x1UL << CSI_CR_VC0START_Pos)            /*!< 0x00000004 */
+#define CSI_CR_VC0START                 CSI_CR_VC0START_Msk                      /*!< Virtual channel 0 start */
+#define CSI_CR_VC0STOP_Pos              (3U)
+#define CSI_CR_VC0STOP_Msk              (0x1UL << CSI_CR_VC0STOP_Pos)             /*!< 0x00000008 */
+#define CSI_CR_VC0STOP                  CSI_CR_VC0STOP_Msk                       /*!< Virtual channel 0 stop */
+#define CSI_CR_VC1START_Pos             (6U)
+#define CSI_CR_VC1START_Msk             (0x1UL << CSI_CR_VC1START_Pos)            /*!< 0x00000040 */
+#define CSI_CR_VC1START                 CSI_CR_VC1START_Msk                      /*!< Virtual channel 1 start */
+#define CSI_CR_VC1STOP_Pos              (7U)
+#define CSI_CR_VC1STOP_Msk              (0x1UL << CSI_CR_VC1STOP_Pos)             /*!< 0x00000080 */
+#define CSI_CR_VC1STOP                  CSI_CR_VC1STOP_Msk                       /*!< Virtual channel 1 stop */
+#define CSI_CR_VC2START_Pos             (10U)
+#define CSI_CR_VC2START_Msk             (0x1UL << CSI_CR_VC2START_Pos)            /*!< 0x00000400 */
+#define CSI_CR_VC2START                 CSI_CR_VC2START_Msk                      /*!< Virtual channel 2 start */
+#define CSI_CR_VC2STOP_Pos              (11U)
+#define CSI_CR_VC2STOP_Msk              (0x1UL << CSI_CR_VC2STOP_Pos)             /*!< 0x00000800 */
+#define CSI_CR_VC2STOP                  CSI_CR_VC2STOP_Msk                       /*!< Virtual channel 2 stop */
+#define CSI_CR_VC3START_Pos             (14U)
+#define CSI_CR_VC3START_Msk             (0x1UL << CSI_CR_VC3START_Pos)            /*!< 0x00004000 */
+#define CSI_CR_VC3START                 CSI_CR_VC3START_Msk                      /*!< Virtual channel 3 start */
+#define CSI_CR_VC3STOP_Pos              (15U)
+#define CSI_CR_VC3STOP_Msk              (0x1UL << CSI_CR_VC3STOP_Pos)             /*!< 0x00008000 */
+#define CSI_CR_VC3STOP                  CSI_CR_VC3STOP_Msk                       /*!< Virtual channel 3 stop */
+
+/*******************  Bit definition for CSI_PCR register  ********************/
+#define CSI_PCR_PWRDOWN_Pos             (0U)
+#define CSI_PCR_PWRDOWN_Msk             (0x1UL << CSI_PCR_PWRDOWN_Pos)            /*!< 0x00000001 */
+#define CSI_PCR_PWRDOWN                 CSI_PCR_PWRDOWN_Msk                      /*!< Virtual channel 3 start */
+#define CSI_PCR_CLEN_Pos                (1U)
+#define CSI_PCR_CLEN_Msk                (0x1UL << CSI_PCR_CLEN_Pos)               /*!< 0x00000002 */
+#define CSI_PCR_CLEN                    CSI_PCR_CLEN_Msk                         /*!< Clock lane enable */
+#define CSI_PCR_DL0EN_Pos               (2U)
+#define CSI_PCR_DL0EN_Msk               (0x1UL << CSI_PCR_DL0EN_Pos)              /*!< 0x00000004 */
+#define CSI_PCR_DL0EN                   CSI_PCR_DL0EN_Msk                        /*!< D-PHY_RX data lane 0 enable */
+#define CSI_PCR_DL1EN_Pos               (3U)
+#define CSI_PCR_DL1EN_Msk               (0x1UL << CSI_PCR_DL1EN_Pos)              /*!< 0x00000008 */
+#define CSI_PCR_DL1EN                   CSI_PCR_DL1EN_Msk                        /*!< D-PHY_RX data lane 1 enable */
+
+/*****************  Bit definition for CSI_VC0CFGR1 register  *****************/
+#define CSI_VC0CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC0CFGR1_ALLDT_Msk          (0x1UL << CSI_VC0CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC0CFGR1_ALLDT              CSI_VC0CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC0CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC0CFGR1_DT0EN_Msk          (0x1UL << CSI_VC0CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC0CFGR1_DT0EN              CSI_VC0CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC0CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC0CFGR1_DT1EN_Msk          (0x1UL << CSI_VC0CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC0CFGR1_DT1EN              CSI_VC0CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC0CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC0CFGR1_DT2EN_Msk          (0x1UL << CSI_VC0CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC0CFGR1_DT2EN              CSI_VC0CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC0CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC0CFGR1_DT3EN_Msk          (0x1UL << CSI_VC0CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC0CFGR1_DT3EN              CSI_VC0CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC0CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC0CFGR1_DT4EN_Msk          (0x1UL << CSI_VC0CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC0CFGR1_DT4EN              CSI_VC0CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC0CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC0CFGR1_DT5EN_Msk          (0x1UL << CSI_VC0CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC0CFGR1_DT5EN              CSI_VC0CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC0CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC0CFGR1_DT6EN_Msk          (0x1UL << CSI_VC0CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC0CFGR1_DT6EN              CSI_VC0CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC0CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC0CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR1_CDTFT              CSI_VC0CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC0CFGR1_DT0_Pos            (16U)
+#define CSI_VC0CFGR1_DT0_Msk            (0x3FUL << CSI_VC0CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR1_DT0                CSI_VC0CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC0CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC0CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR1_DT0FT              CSI_VC0CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC0CFGR2 register  *****************/
+#define CSI_VC0CFGR2_DT1_Pos            (0U)
+#define CSI_VC0CFGR2_DT1_Msk            (0x3FUL << CSI_VC0CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR2_DT1                CSI_VC0CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC0CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR2_DT1FT              CSI_VC0CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC0CFGR2_DT2_Pos            (16U)
+#define CSI_VC0CFGR2_DT2_Msk            (0x3FUL << CSI_VC0CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR2_DT2                CSI_VC0CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC0CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC0CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR2_DT2FT              CSI_VC0CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC0CFGR3 register  *****************/
+#define CSI_VC0CFGR3_DT3_Pos            (0U)
+#define CSI_VC0CFGR3_DT3_Msk            (0x3FUL << CSI_VC0CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR3_DT3                CSI_VC0CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC0CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR3_DT3FT              CSI_VC0CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC0CFGR3_DT4_Pos            (16U)
+#define CSI_VC0CFGR3_DT4_Msk            (0x3FUL << CSI_VC0CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR3_DT4                CSI_VC0CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC0CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC0CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR3_DT4FT              CSI_VC0CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC0CFGR4 register  *****************/
+#define CSI_VC0CFGR4_DT5_Pos            (0U)
+#define CSI_VC0CFGR4_DT5_Msk            (0x3FUL << CSI_VC0CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC0CFGR4_DT5                CSI_VC0CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC0CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC0CFGR4_DT5FT              CSI_VC0CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC0CFGR4_DT6_Pos            (16U)
+#define CSI_VC0CFGR4_DT6_Msk            (0x3FUL << CSI_VC0CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC0CFGR4_DT6                CSI_VC0CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC0CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC0CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC0CFGR4_DT6FT              CSI_VC0CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC1CFGR1 register  *****************/
+#define CSI_VC1CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC1CFGR1_ALLDT_Msk          (0x1UL << CSI_VC1CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC1CFGR1_ALLDT              CSI_VC1CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC1CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC1CFGR1_DT0EN_Msk          (0x1UL << CSI_VC1CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC1CFGR1_DT0EN              CSI_VC1CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC1CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC1CFGR1_DT1EN_Msk          (0x1UL << CSI_VC1CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC1CFGR1_DT1EN              CSI_VC1CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC1CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC1CFGR1_DT2EN_Msk          (0x1UL << CSI_VC1CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC1CFGR1_DT2EN              CSI_VC1CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC1CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC1CFGR1_DT3EN_Msk          (0x1UL << CSI_VC1CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC1CFGR1_DT3EN              CSI_VC1CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC1CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC1CFGR1_DT4EN_Msk          (0x1UL << CSI_VC1CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC1CFGR1_DT4EN              CSI_VC1CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC1CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC1CFGR1_DT5EN_Msk          (0x1UL << CSI_VC1CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC1CFGR1_DT5EN              CSI_VC1CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC1CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC1CFGR1_DT6EN_Msk          (0x1UL << CSI_VC1CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC1CFGR1_DT6EN              CSI_VC1CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC1CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC1CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR1_CDTFT              CSI_VC1CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC1CFGR1_DT0_Pos            (16U)
+#define CSI_VC1CFGR1_DT0_Msk            (0x3FUL << CSI_VC1CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR1_DT0                CSI_VC1CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC1CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC1CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR1_DT0FT              CSI_VC1CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC1CFGR2 register  *****************/
+#define CSI_VC1CFGR2_DT1_Pos            (0U)
+#define CSI_VC1CFGR2_DT1_Msk            (0x3FUL << CSI_VC1CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR2_DT1                CSI_VC1CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC1CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR2_DT1FT              CSI_VC1CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC1CFGR2_DT2_Pos            (16U)
+#define CSI_VC1CFGR2_DT2_Msk            (0x3FUL << CSI_VC1CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR2_DT2                CSI_VC1CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC1CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC1CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR2_DT2FT              CSI_VC1CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC1CFGR3 register  *****************/
+#define CSI_VC1CFGR3_DT3_Pos            (0U)
+#define CSI_VC1CFGR3_DT3_Msk            (0x3FUL << CSI_VC1CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR3_DT3                CSI_VC1CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC1CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR3_DT3FT              CSI_VC1CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC1CFGR3_DT4_Pos            (16U)
+#define CSI_VC1CFGR3_DT4_Msk            (0x3FUL << CSI_VC1CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR3_DT4                CSI_VC1CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC1CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC1CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR3_DT4FT              CSI_VC1CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC1CFGR4 register  *****************/
+#define CSI_VC1CFGR4_DT5_Pos            (0U)
+#define CSI_VC1CFGR4_DT5_Msk            (0x3FUL << CSI_VC1CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC1CFGR4_DT5                CSI_VC1CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC1CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC1CFGR4_DT5FT              CSI_VC1CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC1CFGR4_DT6_Pos            (16U)
+#define CSI_VC1CFGR4_DT6_Msk            (0x3FUL << CSI_VC1CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC1CFGR4_DT6                CSI_VC1CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC1CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC1CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC1CFGR4_DT6FT              CSI_VC1CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC2CFGR1 register  *****************/
+#define CSI_VC2CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC2CFGR1_ALLDT_Msk          (0x1UL << CSI_VC2CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC2CFGR1_ALLDT              CSI_VC2CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC2CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC2CFGR1_DT0EN_Msk          (0x1UL << CSI_VC2CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC2CFGR1_DT0EN              CSI_VC2CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC2CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC2CFGR1_DT1EN_Msk          (0x1UL << CSI_VC2CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC2CFGR1_DT1EN              CSI_VC2CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC2CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC2CFGR1_DT2EN_Msk          (0x1UL << CSI_VC2CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC2CFGR1_DT2EN              CSI_VC2CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC2CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC2CFGR1_DT3EN_Msk          (0x1UL << CSI_VC2CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC2CFGR1_DT3EN              CSI_VC2CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC2CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC2CFGR1_DT4EN_Msk          (0x1UL << CSI_VC2CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC2CFGR1_DT4EN              CSI_VC2CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC2CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC2CFGR1_DT5EN_Msk          (0x1UL << CSI_VC2CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC2CFGR1_DT5EN              CSI_VC2CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC2CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC2CFGR1_DT6EN_Msk          (0x1UL << CSI_VC2CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC2CFGR1_DT6EN              CSI_VC2CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC2CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC2CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR1_CDTFT              CSI_VC2CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC2CFGR1_DT0_Pos            (16U)
+#define CSI_VC2CFGR1_DT0_Msk            (0x3FUL << CSI_VC2CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR1_DT0                CSI_VC2CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC2CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC2CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR1_DT0FT              CSI_VC2CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC2CFGR2 register  *****************/
+#define CSI_VC2CFGR2_DT1_Pos            (0U)
+#define CSI_VC2CFGR2_DT1_Msk            (0x3FUL << CSI_VC2CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR2_DT1                CSI_VC2CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC2CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR2_DT1FT              CSI_VC2CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC2CFGR2_DT2_Pos            (16U)
+#define CSI_VC2CFGR2_DT2_Msk            (0x3FUL << CSI_VC2CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR2_DT2                CSI_VC2CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC2CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC2CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR2_DT2FT              CSI_VC2CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC2CFGR3 register  *****************/
+#define CSI_VC2CFGR3_DT3_Pos            (0U)
+#define CSI_VC2CFGR3_DT3_Msk            (0x3FUL << CSI_VC2CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR3_DT3                CSI_VC2CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC2CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR3_DT3FT              CSI_VC2CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC2CFGR3_DT4_Pos            (16U)
+#define CSI_VC2CFGR3_DT4_Msk            (0x3FUL << CSI_VC2CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR3_DT4                CSI_VC2CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC2CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC2CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR3_DT4FT              CSI_VC2CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC2CFGR4 register  *****************/
+#define CSI_VC2CFGR4_DT5_Pos            (0U)
+#define CSI_VC2CFGR4_DT5_Msk            (0x3FUL << CSI_VC2CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC2CFGR4_DT5                CSI_VC2CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC2CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC2CFGR4_DT5FT              CSI_VC2CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC2CFGR4_DT6_Pos            (16U)
+#define CSI_VC2CFGR4_DT6_Msk            (0x3FUL << CSI_VC2CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC2CFGR4_DT6                CSI_VC2CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC2CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC2CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC2CFGR4_DT6FT              CSI_VC2CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_VC3CFGR1 register  *****************/
+#define CSI_VC3CFGR1_ALLDT_Pos          (0U)
+#define CSI_VC3CFGR1_ALLDT_Msk          (0x1UL << CSI_VC3CFGR1_ALLDT_Pos)         /*!< 0x00000001 */
+#define CSI_VC3CFGR1_ALLDT              CSI_VC3CFGR1_ALLDT_Msk                   /*!< All data types enable for the virtual channel x */
+#define CSI_VC3CFGR1_DT0EN_Pos          (1U)
+#define CSI_VC3CFGR1_DT0EN_Msk          (0x1UL << CSI_VC3CFGR1_DT0EN_Pos)         /*!< 0x00000002 */
+#define CSI_VC3CFGR1_DT0EN              CSI_VC3CFGR1_DT0EN_Msk                   /*!< Data type 0 enable */
+#define CSI_VC3CFGR1_DT1EN_Pos          (2U)
+#define CSI_VC3CFGR1_DT1EN_Msk          (0x1UL << CSI_VC3CFGR1_DT1EN_Pos)         /*!< 0x00000004 */
+#define CSI_VC3CFGR1_DT1EN              CSI_VC3CFGR1_DT1EN_Msk                   /*!< Data type 1 enable */
+#define CSI_VC3CFGR1_DT2EN_Pos          (3U)
+#define CSI_VC3CFGR1_DT2EN_Msk          (0x1UL << CSI_VC3CFGR1_DT2EN_Pos)         /*!< 0x00000008 */
+#define CSI_VC3CFGR1_DT2EN              CSI_VC3CFGR1_DT2EN_Msk                   /*!< Data type 2 enable */
+#define CSI_VC3CFGR1_DT3EN_Pos          (4U)
+#define CSI_VC3CFGR1_DT3EN_Msk          (0x1UL << CSI_VC3CFGR1_DT3EN_Pos)         /*!< 0x00000010 */
+#define CSI_VC3CFGR1_DT3EN              CSI_VC3CFGR1_DT3EN_Msk                   /*!< Data type 3 enable */
+#define CSI_VC3CFGR1_DT4EN_Pos          (5U)
+#define CSI_VC3CFGR1_DT4EN_Msk          (0x1UL << CSI_VC3CFGR1_DT4EN_Pos)         /*!< 0x00000020 */
+#define CSI_VC3CFGR1_DT4EN              CSI_VC3CFGR1_DT4EN_Msk                   /*!< Data type 4 enable */
+#define CSI_VC3CFGR1_DT5EN_Pos          (6U)
+#define CSI_VC3CFGR1_DT5EN_Msk          (0x1UL << CSI_VC3CFGR1_DT5EN_Pos)         /*!< 0x00000040 */
+#define CSI_VC3CFGR1_DT5EN              CSI_VC3CFGR1_DT5EN_Msk                   /*!< Data type 5 enable */
+#define CSI_VC3CFGR1_DT6EN_Pos          (7U)
+#define CSI_VC3CFGR1_DT6EN_Msk          (0x1UL << CSI_VC3CFGR1_DT6EN_Pos)         /*!< 0x00000080 */
+#define CSI_VC3CFGR1_DT6EN              CSI_VC3CFGR1_DT6EN_Msk                   /*!< Data type 6 enable */
+#define CSI_VC3CFGR1_CDTFT_Pos          (8U)
+#define CSI_VC3CFGR1_CDTFT_Msk          (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR1_CDTFT              CSI_VC3CFGR1_CDTFT_Msk                   /*!< Common format for all data types */
+#define CSI_VC3CFGR1_DT0_Pos            (16U)
+#define CSI_VC3CFGR1_DT0_Msk            (0x3FUL << CSI_VC3CFGR1_DT0_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR1_DT0                CSI_VC3CFGR1_DT0_Msk                     /*!< Data type 0 class selection for virtual channel x */
+#define CSI_VC3CFGR1_DT0FT_Pos          (24U)
+#define CSI_VC3CFGR1_DT0FT_Msk          (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR1_DT0FT              CSI_VC3CFGR1_DT0FT_Msk                   /*!< Data type 0 format */
+
+/*****************  Bit definition for CSI_VC3CFGR2 register  *****************/
+#define CSI_VC3CFGR2_DT1_Pos            (0U)
+#define CSI_VC3CFGR2_DT1_Msk            (0x3FUL << CSI_VC3CFGR2_DT1_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR2_DT1                CSI_VC3CFGR2_DT1_Msk                     /*!< Data type 1 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT1FT_Pos          (8U)
+#define CSI_VC3CFGR2_DT1FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR2_DT1FT              CSI_VC3CFGR2_DT1FT_Msk                   /*!< Data type 1 format */
+#define CSI_VC3CFGR2_DT2_Pos            (16U)
+#define CSI_VC3CFGR2_DT2_Msk            (0x3FUL << CSI_VC3CFGR2_DT2_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR2_DT2                CSI_VC3CFGR2_DT2_Msk                     /*!< Data type 2 class selection for virtual channel x */
+#define CSI_VC3CFGR2_DT2FT_Pos          (24U)
+#define CSI_VC3CFGR2_DT2FT_Msk          (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR2_DT2FT              CSI_VC3CFGR2_DT2FT_Msk                   /*!< Data type 2 format */
+
+/*****************  Bit definition for CSI_VC3CFGR3 register  *****************/
+#define CSI_VC3CFGR3_DT3_Pos            (0U)
+#define CSI_VC3CFGR3_DT3_Msk            (0x3FUL << CSI_VC3CFGR3_DT3_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR3_DT3                CSI_VC3CFGR3_DT3_Msk                     /*!< Data type 3 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT3FT_Pos          (8U)
+#define CSI_VC3CFGR3_DT3FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR3_DT3FT              CSI_VC3CFGR3_DT3FT_Msk                   /*!< Data type 3 format */
+#define CSI_VC3CFGR3_DT4_Pos            (16U)
+#define CSI_VC3CFGR3_DT4_Msk            (0x3FUL << CSI_VC3CFGR3_DT4_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR3_DT4                CSI_VC3CFGR3_DT4_Msk                     /*!< Data type 4 class selection for virtual channel x */
+#define CSI_VC3CFGR3_DT4FT_Pos          (24U)
+#define CSI_VC3CFGR3_DT4FT_Msk          (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR3_DT4FT              CSI_VC3CFGR3_DT4FT_Msk                   /*!< Data type 4 format */
+
+/*****************  Bit definition for CSI_VC3CFGR4 register  *****************/
+#define CSI_VC3CFGR4_DT5_Pos            (0U)
+#define CSI_VC3CFGR4_DT5_Msk            (0x3FUL << CSI_VC3CFGR4_DT5_Pos)          /*!< 0x0000003F */
+#define CSI_VC3CFGR4_DT5                CSI_VC3CFGR4_DT5_Msk                     /*!< Data type 5 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT5FT_Pos          (8U)
+#define CSI_VC3CFGR4_DT5FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos)        /*!< 0x00001F00 */
+#define CSI_VC3CFGR4_DT5FT              CSI_VC3CFGR4_DT5FT_Msk                   /*!< Data type 5 format */
+#define CSI_VC3CFGR4_DT6_Pos            (16U)
+#define CSI_VC3CFGR4_DT6_Msk            (0x3FUL << CSI_VC3CFGR4_DT6_Pos)          /*!< 0x003F0000 */
+#define CSI_VC3CFGR4_DT6                CSI_VC3CFGR4_DT6_Msk                     /*!< Data type 6 class selection for virtual channel x */
+#define CSI_VC3CFGR4_DT6FT_Pos          (24U)
+#define CSI_VC3CFGR4_DT6FT_Msk          (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos)        /*!< 0x1F000000 */
+#define CSI_VC3CFGR4_DT6FT              CSI_VC3CFGR4_DT6FT_Msk                   /*!< Data type 6 format */
+
+/*****************  Bit definition for CSI_LB0CFGR register  ******************/
+#define CSI_LB0CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB0CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB0CFGR_BYTECNT             CSI_LB0CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB0CFGR_LINECNT_Pos         (16U)
+#define CSI_LB0CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB0CFGR_LINECNT             CSI_LB0CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB1CFGR register  ******************/
+#define CSI_LB1CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB1CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB1CFGR_BYTECNT             CSI_LB1CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB1CFGR_LINECNT_Pos         (16U)
+#define CSI_LB1CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB1CFGR_LINECNT             CSI_LB1CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB2CFGR register  ******************/
+#define CSI_LB2CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB2CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB2CFGR_BYTECNT             CSI_LB2CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB2CFGR_LINECNT_Pos         (16U)
+#define CSI_LB2CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB2CFGR_LINECNT             CSI_LB2CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_LB3CFGR register  ******************/
+#define CSI_LB3CFGR_BYTECNT_Pos         (0U)
+#define CSI_LB3CFGR_BYTECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos)     /*!< 0x0000FFFF */
+#define CSI_LB3CFGR_BYTECNT             CSI_LB3CFGR_BYTECNT_Msk                  /*!< Byte counter */
+#define CSI_LB3CFGR_LINECNT_Pos         (16U)
+#define CSI_LB3CFGR_LINECNT_Msk         (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos)     /*!< 0xFFFF0000 */
+#define CSI_LB3CFGR_LINECNT             CSI_LB3CFGR_LINECNT_Msk                  /*!< Line counter */
+
+/*****************  Bit definition for CSI_TIM0CFGR register  *****************/
+#define CSI_TIM0CFGR_COUNT_Pos          (0U)
+#define CSI_TIM0CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM0CFGR_COUNT              CSI_TIM0CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM1CFGR register  *****************/
+#define CSI_TIM1CFGR_COUNT_Pos          (0U)
+#define CSI_TIM1CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM1CFGR_COUNT              CSI_TIM1CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM2CFGR register  *****************/
+#define CSI_TIM2CFGR_COUNT_Pos          (0U)
+#define CSI_TIM2CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM2CFGR_COUNT              CSI_TIM2CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/*****************  Bit definition for CSI_TIM3CFGR register  *****************/
+#define CSI_TIM3CFGR_COUNT_Pos          (0U)
+#define CSI_TIM3CFGR_COUNT_Msk          (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos)   /*!< 0x01FFFFFF */
+#define CSI_TIM3CFGR_COUNT              CSI_TIM3CFGR_COUNT_Msk                   /*!< Clock cycle counter */
+
+/******************  Bit definition for CSI_LMCFGR register  ******************/
+#define CSI_LMCFGR_LANENB_Pos           (8U)
+#define CSI_LMCFGR_LANENB_Msk           (0x7UL << CSI_LMCFGR_LANENB_Pos)          /*!< 0x00000700 */
+#define CSI_LMCFGR_LANENB               CSI_LMCFGR_LANENB_Msk                    /*!< Number of lanes */
+#define CSI_LMCFGR_DL0MAP_Pos           (16U)
+#define CSI_LMCFGR_DL0MAP_Msk           (0x7UL << CSI_LMCFGR_DL0MAP_Pos)          /*!< 0x00070000 */
+#define CSI_LMCFGR_DL0MAP               CSI_LMCFGR_DL0MAP_Msk                    /*!< Physical mapping of logical data lane 0 */
+#define CSI_LMCFGR_DL1MAP_Pos           (20U)
+#define CSI_LMCFGR_DL1MAP_Msk           (0x7UL << CSI_LMCFGR_DL1MAP_Pos)          /*!< 0x00700000 */
+#define CSI_LMCFGR_DL1MAP               CSI_LMCFGR_DL1MAP_Msk                    /*!< Physical mapping of logical data lane 1 */
+
+/******************  Bit definition for CSI_PRGITR register  ******************/
+#define CSI_PRGITR_LB0VC_Pos            (0U)
+#define CSI_PRGITR_LB0VC_Msk            (0x3UL << CSI_PRGITR_LB0VC_Pos)           /*!< 0x00000003 */
+#define CSI_PRGITR_LB0VC                CSI_PRGITR_LB0VC_Msk                     /*!< Line/Byte counter 0 linked to a virtual channel */
+#define CSI_PRGITR_LB0EN_Pos            (3U)
+#define CSI_PRGITR_LB0EN_Msk            (0x1UL << CSI_PRGITR_LB0EN_Pos)           /*!< 0x00000008 */
+#define CSI_PRGITR_LB0EN                CSI_PRGITR_LB0EN_Msk                     /*!< Line/Byte 0counter enable */
+#define CSI_PRGITR_LB1VC_Pos            (4U)
+#define CSI_PRGITR_LB1VC_Msk            (0x3UL << CSI_PRGITR_LB1VC_Pos)           /*!< 0x00000030 */
+#define CSI_PRGITR_LB1VC                CSI_PRGITR_LB1VC_Msk                     /*!< Line/Byte counter 1 linked to a virtual channel */
+#define CSI_PRGITR_LB1EN_Pos            (7U)
+#define CSI_PRGITR_LB1EN_Msk            (0x1UL << CSI_PRGITR_LB1EN_Pos)           /*!< 0x00000080 */
+#define CSI_PRGITR_LB1EN                CSI_PRGITR_LB1EN_Msk                     /*!< Line/Byte 1 counter enable */
+#define CSI_PRGITR_LB2VC_Pos            (8U)
+#define CSI_PRGITR_LB2VC_Msk            (0x3UL << CSI_PRGITR_LB2VC_Pos)           /*!< 0x00000300 */
+#define CSI_PRGITR_LB2VC                CSI_PRGITR_LB2VC_Msk                     /*!< Line/Byte counter 2 linked to a virtual channel */
+#define CSI_PRGITR_LB2EN_Pos            (11U)
+#define CSI_PRGITR_LB2EN_Msk            (0x1UL << CSI_PRGITR_LB2EN_Pos)           /*!< 0x00000800 */
+#define CSI_PRGITR_LB2EN                CSI_PRGITR_LB2EN_Msk                     /*!< Line/Byte 2 counter enable */
+#define CSI_PRGITR_LB3VC_Pos            (12U)
+#define CSI_PRGITR_LB3VC_Msk            (0x3UL << CSI_PRGITR_LB3VC_Pos)           /*!< 0x00003000 */
+#define CSI_PRGITR_LB3VC                CSI_PRGITR_LB3VC_Msk                     /*!< Line/Byte counter 3 linked to a virtual channel */
+#define CSI_PRGITR_LB3EN_Pos            (15U)
+#define CSI_PRGITR_LB3EN_Msk            (0x1UL << CSI_PRGITR_LB3EN_Pos)           /*!< 0x00008000 */
+#define CSI_PRGITR_LB3EN                CSI_PRGITR_LB3EN_Msk                     /*!< Line/Byte 3 counter enable */
+#define CSI_PRGITR_TIM0VC_Pos           (16U)
+#define CSI_PRGITR_TIM0VC_Msk           (0x3UL << CSI_PRGITR_TIM0VC_Pos)          /*!< 0x00030000 */
+#define CSI_PRGITR_TIM0VC               CSI_PRGITR_TIM0VC_Msk                    /*!< TIM0 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM0EOF_Pos          (18U)
+#define CSI_PRGITR_TIM0EOF_Msk          (0x1UL << CSI_PRGITR_TIM0EOF_Pos)         /*!< 0x00040000 */
+#define CSI_PRGITR_TIM0EOF              CSI_PRGITR_TIM0EOF_Msk                   /*!< TIM0 base time starting from the end of frame */
+#define CSI_PRGITR_TIM0EN_Pos           (19U)
+#define CSI_PRGITR_TIM0EN_Msk           (0x1UL << CSI_PRGITR_TIM0EN_Pos)          /*!< 0x00080000 */
+#define CSI_PRGITR_TIM0EN               CSI_PRGITR_TIM0EN_Msk                    /*!< TIM0 base time enable */
+#define CSI_PRGITR_TIM1VC_Pos           (20U)
+#define CSI_PRGITR_TIM1VC_Msk           (0x3UL << CSI_PRGITR_TIM1VC_Pos)          /*!< 0x00300000 */
+#define CSI_PRGITR_TIM1VC               CSI_PRGITR_TIM1VC_Msk                    /*!< TIM1 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM1EOF_Pos          (22U)
+#define CSI_PRGITR_TIM1EOF_Msk          (0x1UL << CSI_PRGITR_TIM1EOF_Pos)         /*!< 0x00400000 */
+#define CSI_PRGITR_TIM1EOF              CSI_PRGITR_TIM1EOF_Msk                   /*!< TIM1 base time starting from the end of frame */
+#define CSI_PRGITR_TIM1EN_Pos           (23U)
+#define CSI_PRGITR_TIM1EN_Msk           (0x1UL << CSI_PRGITR_TIM1EN_Pos)          /*!< 0x00800000 */
+#define CSI_PRGITR_TIM1EN               CSI_PRGITR_TIM1EN_Msk                    /*!< TIM1 base time enable */
+#define CSI_PRGITR_TIM2VC_Pos           (24U)
+#define CSI_PRGITR_TIM2VC_Msk           (0x3UL << CSI_PRGITR_TIM2VC_Pos)          /*!< 0x03000000 */
+#define CSI_PRGITR_TIM2VC               CSI_PRGITR_TIM2VC_Msk                    /*!< TIM2 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM2EOF_Pos          (26U)
+#define CSI_PRGITR_TIM2EOF_Msk          (0x1UL << CSI_PRGITR_TIM2EOF_Pos)         /*!< 0x04000000 */
+#define CSI_PRGITR_TIM2EOF              CSI_PRGITR_TIM2EOF_Msk                   /*!< TIM2 base time starting from the end of frame */
+#define CSI_PRGITR_TIM2EN_Pos           (27U)
+#define CSI_PRGITR_TIM2EN_Msk           (0x1UL << CSI_PRGITR_TIM2EN_Pos)          /*!< 0x08000000 */
+#define CSI_PRGITR_TIM2EN               CSI_PRGITR_TIM2EN_Msk                    /*!< TIM2 base time enable */
+#define CSI_PRGITR_TIM3VC_Pos           (28U)
+#define CSI_PRGITR_TIM3VC_Msk           (0x3UL << CSI_PRGITR_TIM3VC_Pos)          /*!< 0x30000000 */
+#define CSI_PRGITR_TIM3VC               CSI_PRGITR_TIM3VC_Msk                    /*!< TIM3 base time linked to a virtual channel */
+#define CSI_PRGITR_TIM3EOF_Pos          (30U)
+#define CSI_PRGITR_TIM3EOF_Msk          (0x1UL << CSI_PRGITR_TIM3EOF_Pos)         /*!< 0x40000000 */
+#define CSI_PRGITR_TIM3EOF              CSI_PRGITR_TIM3EOF_Msk                   /*!< TIM3 base time starting from the end of frame */
+#define CSI_PRGITR_TIM3EN_Pos           (31U)
+#define CSI_PRGITR_TIM3EN_Msk           (0x1UL << CSI_PRGITR_TIM3EN_Pos)          /*!< 0x80000000 */
+#define CSI_PRGITR_TIM3EN               CSI_PRGITR_TIM3EN_Msk                    /*!< TIM3 base time enable */
+
+/*******************  Bit definition for CSI_WDR register  ********************/
+#define CSI_WDR_CNT_Pos                 (0U)
+#define CSI_WDR_CNT_Msk                 (0xFFFFFFFFUL << CSI_WDR_CNT_Pos)         /*!< 0xFFFFFFFF */
+#define CSI_WDR_CNT                     CSI_WDR_CNT_Msk                          /*!< Watchdog counter */
+
+/*******************  Bit definition for CSI_IER0 register  *******************/
+#define CSI_IER0_LB0IE_Pos              (0U)
+#define CSI_IER0_LB0IE_Msk              (0x1UL << CSI_IER0_LB0IE_Pos)             /*!< 0x00000001 */
+#define CSI_IER0_LB0IE                  CSI_IER0_LB0IE_Msk                       /*!< Line byte counter 0 interrupt enable */
+#define CSI_IER0_LB1IE_Pos              (1U)
+#define CSI_IER0_LB1IE_Msk              (0x1UL << CSI_IER0_LB1IE_Pos)             /*!< 0x00000002 */
+#define CSI_IER0_LB1IE                  CSI_IER0_LB1IE_Msk                       /*!< Line byte counter 1 interrupt enable */
+#define CSI_IER0_LB2IE_Pos              (2U)
+#define CSI_IER0_LB2IE_Msk              (0x1UL << CSI_IER0_LB2IE_Pos)             /*!< 0x00000004 */
+#define CSI_IER0_LB2IE                  CSI_IER0_LB2IE_Msk                       /*!< Line byte counter 2 interrupt enable */
+#define CSI_IER0_LB3IE_Pos              (3U)
+#define CSI_IER0_LB3IE_Msk              (0x1UL << CSI_IER0_LB3IE_Pos)             /*!< 0x00000008 */
+#define CSI_IER0_LB3IE                  CSI_IER0_LB3IE_Msk                       /*!< Line byte counter 3 interrupt enable */
+#define CSI_IER0_TIM0IE_Pos             (4U)
+#define CSI_IER0_TIM0IE_Msk             (0x1UL << CSI_IER0_TIM0IE_Pos)            /*!< 0x00000010 */
+#define CSI_IER0_TIM0IE                 CSI_IER0_TIM0IE_Msk                      /*!< Timer 0 interrupt enable */
+#define CSI_IER0_TIM1IE_Pos             (5U)
+#define CSI_IER0_TIM1IE_Msk             (0x1UL << CSI_IER0_TIM1IE_Pos)            /*!< 0x00000020 */
+#define CSI_IER0_TIM1IE                 CSI_IER0_TIM1IE_Msk                      /*!< Timer 1 interrupt enable */
+#define CSI_IER0_TIM2IE_Pos             (6U)
+#define CSI_IER0_TIM2IE_Msk             (0x1UL << CSI_IER0_TIM2IE_Pos)            /*!< 0x00000040 */
+#define CSI_IER0_TIM2IE                 CSI_IER0_TIM2IE_Msk                      /*!< Timer 2 interrupt enable */
+#define CSI_IER0_TIM3IE_Pos             (7U)
+#define CSI_IER0_TIM3IE_Msk             (0x1UL << CSI_IER0_TIM3IE_Pos)            /*!< 0x00000080 */
+#define CSI_IER0_TIM3IE                 CSI_IER0_TIM3IE_Msk                      /*!< Timer 3 interrupt enable */
+#define CSI_IER0_SOF0IE_Pos             (8U)
+#define CSI_IER0_SOF0IE_Msk             (0x1UL << CSI_IER0_SOF0IE_Pos)            /*!< 0x00000100 */
+#define CSI_IER0_SOF0IE                 CSI_IER0_SOF0IE_Msk                      /*!< Start of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_SOF1IE_Pos             (9U)
+#define CSI_IER0_SOF1IE_Msk             (0x1UL << CSI_IER0_SOF1IE_Pos)            /*!< 0x00000200 */
+#define CSI_IER0_SOF1IE                 CSI_IER0_SOF1IE_Msk                      /*!< Start of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_SOF2IE_Pos             (10U)
+#define CSI_IER0_SOF2IE_Msk             (0x1UL << CSI_IER0_SOF2IE_Pos)            /*!< 0x00000400 */
+#define CSI_IER0_SOF2IE                 CSI_IER0_SOF2IE_Msk                      /*!< Start of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_SOF3IE_Pos             (11U)
+#define CSI_IER0_SOF3IE_Msk             (0x1UL << CSI_IER0_SOF3IE_Pos)            /*!< 0x00000800 */
+#define CSI_IER0_SOF3IE                 CSI_IER0_SOF3IE_Msk                      /*!< Start of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_EOF0IE_Pos             (12U)
+#define CSI_IER0_EOF0IE_Msk             (0x1UL << CSI_IER0_EOF0IE_Pos)            /*!< 0x00001000 */
+#define CSI_IER0_EOF0IE                 CSI_IER0_EOF0IE_Msk                      /*!< End of frame for virtual channel 0 interrupt enable */
+#define CSI_IER0_EOF1IE_Pos             (13U)
+#define CSI_IER0_EOF1IE_Msk             (0x1UL << CSI_IER0_EOF1IE_Pos)            /*!< 0x00002000 */
+#define CSI_IER0_EOF1IE                 CSI_IER0_EOF1IE_Msk                      /*!< End of frame for virtual channel 1 interrupt enable */
+#define CSI_IER0_EOF2IE_Pos             (14U)
+#define CSI_IER0_EOF2IE_Msk             (0x1UL << CSI_IER0_EOF2IE_Pos)            /*!< 0x00004000 */
+#define CSI_IER0_EOF2IE                 CSI_IER0_EOF2IE_Msk                      /*!< End of frame for virtual channel 2 interrupt enable */
+#define CSI_IER0_EOF3IE_Pos             (15U)
+#define CSI_IER0_EOF3IE_Msk             (0x1UL << CSI_IER0_EOF3IE_Pos)            /*!< 0x00008000 */
+#define CSI_IER0_EOF3IE                 CSI_IER0_EOF3IE_Msk                      /*!< End of frame for virtual channel 3 interrupt enable */
+#define CSI_IER0_SPKTIE_Pos             (16U)
+#define CSI_IER0_SPKTIE_Msk             (0x1UL << CSI_IER0_SPKTIE_Pos)            /*!< 0x00010000 */
+#define CSI_IER0_SPKTIE                 CSI_IER0_SPKTIE_Msk                      /*!< Short packet interrupt enable */
+#define CSI_IER0_CCFIFOFIE_Pos          (21U)
+#define CSI_IER0_CCFIFOFIE_Msk          (0x1UL << CSI_IER0_CCFIFOFIE_Pos)         /*!< 0x00200000 */
+#define CSI_IER0_CCFIFOFIE              CSI_IER0_CCFIFOFIE_Msk                   /*!< Clock changer FIFO full interrupt enable */
+#define CSI_IER0_CRCERRIE_Pos           (24U)
+#define CSI_IER0_CRCERRIE_Msk           (0x1UL << CSI_IER0_CRCERRIE_Pos)          /*!< 0x01000000 */
+#define CSI_IER0_CRCERRIE               CSI_IER0_CRCERRIE_Msk                    /*!< CRC error interrupt enable */
+#define CSI_IER0_ECCERRIE_Pos           (25U)
+#define CSI_IER0_ECCERRIE_Msk           (0x1UL << CSI_IER0_ECCERRIE_Pos)          /*!< 0x02000000 */
+#define CSI_IER0_ECCERRIE               CSI_IER0_ECCERRIE_Msk                    /*!< ECC error interrupt enable */
+#define CSI_IER0_CECCERRIE_Pos          (26U)
+#define CSI_IER0_CECCERRIE_Msk          (0x1UL << CSI_IER0_CECCERRIE_Pos)         /*!< 0x04000000 */
+#define CSI_IER0_CECCERRIE              CSI_IER0_CECCERRIE_Msk                   /*!< Corrected ECC error interrupt enable */
+#define CSI_IER0_IDERRIE_Pos            (27U)
+#define CSI_IER0_IDERRIE_Msk            (0x1UL << CSI_IER0_IDERRIE_Pos)           /*!< 0x08000000 */
+#define CSI_IER0_IDERRIE                CSI_IER0_IDERRIE_Msk                     /*!< Data type ID error interrupt enable */
+#define CSI_IER0_SPKTERRIE_Pos          (28U)
+#define CSI_IER0_SPKTERRIE_Msk          (0x1UL << CSI_IER0_SPKTERRIE_Pos)         /*!< 0x10000000 */
+#define CSI_IER0_SPKTERRIE              CSI_IER0_SPKTERRIE_Msk                   /*!< Short packet error interrupt enable */
+#define CSI_IER0_WDERRIE_Pos            (29U)
+#define CSI_IER0_WDERRIE_Msk            (0x1UL << CSI_IER0_WDERRIE_Pos)           /*!< 0x20000000 */
+#define CSI_IER0_WDERRIE                CSI_IER0_WDERRIE_Msk                     /*!< Watchdog error interrupt enable */
+#define CSI_IER0_SYNCERRIE_Pos          (30U)
+#define CSI_IER0_SYNCERRIE_Msk          (0x1UL << CSI_IER0_SYNCERRIE_Pos)         /*!< 0x40000000 */
+#define CSI_IER0_SYNCERRIE              CSI_IER0_SYNCERRIE_Msk                   /*!< Invalid synchronization error interrupt enable */
+
+/*******************  Bit definition for CSI_IER1 register  *******************/
+#define CSI_IER1_ESOTDL0IE_Pos          (0U)
+#define CSI_IER1_ESOTDL0IE_Msk          (0x1UL << CSI_IER1_ESOTDL0IE_Pos)         /*!< 0x00000001 */
+#define CSI_IER1_ESOTDL0IE              CSI_IER1_ESOTDL0IE_Msk                   /*!< Start of transmission error interrupt enable on lane 0 */
+#define CSI_IER1_ESOTSYNCDL0IE_Pos      (1U)
+#define CSI_IER1_ESOTSYNCDL0IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos)     /*!< 0x00000002 */
+#define CSI_IER1_ESOTSYNCDL0IE          CSI_IER1_ESOTSYNCDL0IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 0 */
+#define CSI_IER1_EESCDL0IE_Pos          (2U)
+#define CSI_IER1_EESCDL0IE_Msk          (0x1UL << CSI_IER1_EESCDL0IE_Pos)         /*!< 0x00000004 */
+#define CSI_IER1_EESCDL0IE              CSI_IER1_EESCDL0IE_Msk                   /*!< D-PHY_RX lane 0 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL0IE_Pos      (3U)
+#define CSI_IER1_ESYNCESCDL0IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos)     /*!< 0x00000008 */
+#define CSI_IER1_ESYNCESCDL0IE          CSI_IER1_ESYNCESCDL0IE_Msk               /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL0IE_Pos         (4U)
+#define CSI_IER1_ECTRLDL0IE_Msk         (0x1UL << CSI_IER1_ECTRLDL0IE_Pos)        /*!< 0x00000010 */
+#define CSI_IER1_ECTRLDL0IE             CSI_IER1_ECTRLDL0IE_Msk                  /*!< D-PHY_RX lane 0 control error interrupt enable */
+#define CSI_IER1_ESOTDL1IE_Pos          (8U)
+#define CSI_IER1_ESOTDL1IE_Msk          (0x1UL << CSI_IER1_ESOTDL1IE_Pos)         /*!< 0x00000100 */
+#define CSI_IER1_ESOTDL1IE              CSI_IER1_ESOTDL1IE_Msk                   /*!< Start of transmission error interrupt enable on lane 1 */
+#define CSI_IER1_ESOTSYNCDL1IE_Pos      (9U)
+#define CSI_IER1_ESOTSYNCDL1IE_Msk      (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos)     /*!< 0x00000200 */
+#define CSI_IER1_ESOTSYNCDL1IE          CSI_IER1_ESOTSYNCDL1IE_Msk               /*!< Start of transmission synchronization interrupt error enable on lane 1 */
+#define CSI_IER1_EESCDL1IE_Pos          (10U)
+#define CSI_IER1_EESCDL1IE_Msk          (0x1UL << CSI_IER1_EESCDL1IE_Pos)         /*!< 0x00000400 */
+#define CSI_IER1_EESCDL1IE              CSI_IER1_EESCDL1IE_Msk                   /*!< D-PHY_RX lane 1 escape entry error interrupt enable */
+#define CSI_IER1_ESYNCESCDL1IE_Pos      (11U)
+#define CSI_IER1_ESYNCESCDL1IE_Msk      (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos)     /*!< 0x00000800 */
+#define CSI_IER1_ESYNCESCDL1IE          CSI_IER1_ESYNCESCDL1IE_Msk               /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */
+#define CSI_IER1_ECTRLDL1IE_Pos         (12U)
+#define CSI_IER1_ECTRLDL1IE_Msk         (0x1UL << CSI_IER1_ECTRLDL1IE_Pos)        /*!< 0x00001000 */
+#define CSI_IER1_ECTRLDL1IE             CSI_IER1_ECTRLDL1IE_Msk                  /*!< D-PHY_RX lane 1 control error interrupt enable */
+
+/*******************  Bit definition for CSI_SR0 register  ********************/
+#define CSI_SR0_LB0F_Pos                (0U)
+#define CSI_SR0_LB0F_Msk                (0x1UL << CSI_SR0_LB0F_Pos)               /*!< 0x00000001 */
+#define CSI_SR0_LB0F                    CSI_SR0_LB0F_Msk                         /*!< Line byte counter 0 flag */
+#define CSI_SR0_LB1F_Pos                (1U)
+#define CSI_SR0_LB1F_Msk                (0x1UL << CSI_SR0_LB1F_Pos)               /*!< 0x00000002 */
+#define CSI_SR0_LB1F                    CSI_SR0_LB1F_Msk                         /*!< Line byte counter 1 flag */
+#define CSI_SR0_LB2F_Pos                (2U)
+#define CSI_SR0_LB2F_Msk                (0x1UL << CSI_SR0_LB2F_Pos)               /*!< 0x00000004 */
+#define CSI_SR0_LB2F                    CSI_SR0_LB2F_Msk                         /*!< Line byte counter 2 flag */
+#define CSI_SR0_LB3F_Pos                (3U)
+#define CSI_SR0_LB3F_Msk                (0x1UL << CSI_SR0_LB3F_Pos)               /*!< 0x00000008 */
+#define CSI_SR0_LB3F                    CSI_SR0_LB3F_Msk                         /*!< Line byte counter 3 flag */
+#define CSI_SR0_TIM0F_Pos               (4U)
+#define CSI_SR0_TIM0F_Msk               (0x1UL << CSI_SR0_TIM0F_Pos)              /*!< 0x00000010 */
+#define CSI_SR0_TIM0F                   CSI_SR0_TIM0F_Msk                        /*!< Timer 0 flag */
+#define CSI_SR0_TIM1F_Pos               (5U)
+#define CSI_SR0_TIM1F_Msk               (0x1UL << CSI_SR0_TIM1F_Pos)              /*!< 0x00000020 */
+#define CSI_SR0_TIM1F                   CSI_SR0_TIM1F_Msk                        /*!< Timer 1 flag */
+#define CSI_SR0_TIM2F_Pos               (6U)
+#define CSI_SR0_TIM2F_Msk               (0x1UL << CSI_SR0_TIM2F_Pos)              /*!< 0x00000040 */
+#define CSI_SR0_TIM2F                   CSI_SR0_TIM2F_Msk                        /*!< Timer 2 flag */
+#define CSI_SR0_TIM3F_Pos               (7U)
+#define CSI_SR0_TIM3F_Msk               (0x1UL << CSI_SR0_TIM3F_Pos)              /*!< 0x00000080 */
+#define CSI_SR0_TIM3F                   CSI_SR0_TIM3F_Msk                        /*!< Timer 3 flag */
+#define CSI_SR0_SOF0F_Pos               (8U)
+#define CSI_SR0_SOF0F_Msk               (0x1UL << CSI_SR0_SOF0F_Pos)              /*!< 0x00000100 */
+#define CSI_SR0_SOF0F                   CSI_SR0_SOF0F_Msk                        /*!< Start of frame flag for virtual channel 0 */
+#define CSI_SR0_SOF1F_Pos               (9U)
+#define CSI_SR0_SOF1F_Msk               (0x1UL << CSI_SR0_SOF1F_Pos)              /*!< 0x00000200 */
+#define CSI_SR0_SOF1F                   CSI_SR0_SOF1F_Msk                        /*!< Start of frame flag for virtual channel 1 */
+#define CSI_SR0_SOF2F_Pos               (10U)
+#define CSI_SR0_SOF2F_Msk               (0x1UL << CSI_SR0_SOF2F_Pos)              /*!< 0x00000400 */
+#define CSI_SR0_SOF2F                   CSI_SR0_SOF2F_Msk                        /*!< Start of frame flag for virtual channel 2 */
+#define CSI_SR0_SOF3F_Pos               (11U)
+#define CSI_SR0_SOF3F_Msk               (0x1UL << CSI_SR0_SOF3F_Pos)              /*!< 0x00000800 */
+#define CSI_SR0_SOF3F                   CSI_SR0_SOF3F_Msk                        /*!< Start of frame flag for virtual channel 3 */
+#define CSI_SR0_EOF0F_Pos               (12U)
+#define CSI_SR0_EOF0F_Msk               (0x1UL << CSI_SR0_EOF0F_Pos)              /*!< 0x00001000 */
+#define CSI_SR0_EOF0F                   CSI_SR0_EOF0F_Msk                        /*!< End of frame flag for virtual channel 0 */
+#define CSI_SR0_EOF1F_Pos               (13U)
+#define CSI_SR0_EOF1F_Msk               (0x1UL << CSI_SR0_EOF1F_Pos)              /*!< 0x00002000 */
+#define CSI_SR0_EOF1F                   CSI_SR0_EOF1F_Msk                        /*!< End of frame flag for virtual channel 1 */
+#define CSI_SR0_EOF2F_Pos               (14U)
+#define CSI_SR0_EOF2F_Msk               (0x1UL << CSI_SR0_EOF2F_Pos)              /*!< 0x00004000 */
+#define CSI_SR0_EOF2F                   CSI_SR0_EOF2F_Msk                        /*!< End of frame flag for virtual channel 2 */
+#define CSI_SR0_EOF3F_Pos               (15U)
+#define CSI_SR0_EOF3F_Msk               (0x1UL << CSI_SR0_EOF3F_Pos)              /*!< 0x00008000 */
+#define CSI_SR0_EOF3F                   CSI_SR0_EOF3F_Msk                        /*!< End of frame flag for virtual channel 3 */
+#define CSI_SR0_SPKTF_Pos               (16U)
+#define CSI_SR0_SPKTF_Msk               (0x1UL << CSI_SR0_SPKTF_Pos)              /*!< 0x00010000 */
+#define CSI_SR0_SPKTF                   CSI_SR0_SPKTF_Msk                        /*!< Short packet flag */
+#define CSI_SR0_VC0STATEF_Pos           (17U)
+#define CSI_SR0_VC0STATEF_Msk           (0x1UL << CSI_SR0_VC0STATEF_Pos)          /*!< 0x00020000 */
+#define CSI_SR0_VC0STATEF               CSI_SR0_VC0STATEF_Msk                    /*!< Virtual channel 0 state flag */
+#define CSI_SR0_VC1STATEF_Pos           (18U)
+#define CSI_SR0_VC1STATEF_Msk           (0x1UL << CSI_SR0_VC1STATEF_Pos)          /*!< 0x00040000 */
+#define CSI_SR0_VC1STATEF               CSI_SR0_VC1STATEF_Msk                    /*!< Virtual channel 1 state flag */
+#define CSI_SR0_VC2STATEF_Pos           (19U)
+#define CSI_SR0_VC2STATEF_Msk           (0x1UL << CSI_SR0_VC2STATEF_Pos)          /*!< 0x00080000 */
+#define CSI_SR0_VC2STATEF               CSI_SR0_VC2STATEF_Msk                    /*!< Virtual channel 2 state flag */
+#define CSI_SR0_VC3STATEF_Pos           (20U)
+#define CSI_SR0_VC3STATEF_Msk           (0x1UL << CSI_SR0_VC3STATEF_Pos)          /*!< 0x00100000 */
+#define CSI_SR0_VC3STATEF               CSI_SR0_VC3STATEF_Msk                    /*!< Virtual channel 3 state flag */
+#define CSI_SR0_CCFIFOFF_Pos            (21U)
+#define CSI_SR0_CCFIFOFF_Msk            (0x1UL << CSI_SR0_CCFIFOFF_Pos)           /*!< 0x00200000 */
+#define CSI_SR0_CCFIFOFF                CSI_SR0_CCFIFOFF_Msk                     /*!< Clock changer FIFO full flag */
+#define CSI_SR0_CRCERRF_Pos             (24U)
+#define CSI_SR0_CRCERRF_Msk             (0x1UL << CSI_SR0_CRCERRF_Pos)            /*!< 0x01000000 */
+#define CSI_SR0_CRCERRF                 CSI_SR0_CRCERRF_Msk                      /*!< CRC error flag */
+#define CSI_SR0_ECCERRF_Pos             (25U)
+#define CSI_SR0_ECCERRF_Msk             (0x1UL << CSI_SR0_ECCERRF_Pos)            /*!< 0x02000000 */
+#define CSI_SR0_ECCERRF                 CSI_SR0_ECCERRF_Msk                      /*!< ECC error flag */
+#define CSI_SR0_CECCERRF_Pos            (26U)
+#define CSI_SR0_CECCERRF_Msk            (0x1UL << CSI_SR0_CECCERRF_Pos)           /*!< 0x04000000 */
+#define CSI_SR0_CECCERRF                CSI_SR0_CECCERRF_Msk                     /*!< Corrected ECC error flag */
+#define CSI_SR0_IDERRF_Pos              (27U)
+#define CSI_SR0_IDERRF_Msk              (0x1UL << CSI_SR0_IDERRF_Pos)             /*!< 0x08000000 */
+#define CSI_SR0_IDERRF                  CSI_SR0_IDERRF_Msk                       /*!< Data type ID error flag */
+#define CSI_SR0_SPKTERRF_Pos            (28U)
+#define CSI_SR0_SPKTERRF_Msk            (0x1UL << CSI_SR0_SPKTERRF_Pos)           /*!< 0x10000000 */
+#define CSI_SR0_SPKTERRF                CSI_SR0_SPKTERRF_Msk                     /*!< Short packet error flag */
+#define CSI_SR0_WDERRF_Pos              (29U)
+#define CSI_SR0_WDERRF_Msk              (0x1UL << CSI_SR0_WDERRF_Pos)             /*!< 0x20000000 */
+#define CSI_SR0_WDERRF                  CSI_SR0_WDERRF_Msk                       /*!< Watchdog error flag */
+#define CSI_SR0_SYNCERRF_Pos            (30U)
+#define CSI_SR0_SYNCERRF_Msk            (0x1UL << CSI_SR0_SYNCERRF_Pos)           /*!< 0x40000000 */
+#define CSI_SR0_SYNCERRF                CSI_SR0_SYNCERRF_Msk                     /*!< Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_SR1 register  ********************/
+#define CSI_SR1_ESOTDL0F_Pos            (0U)
+#define CSI_SR1_ESOTDL0F_Msk            (0x1UL << CSI_SR1_ESOTDL0F_Pos)           /*!< 0x00000001 */
+#define CSI_SR1_ESOTDL0F                CSI_SR1_ESOTDL0F_Msk                     /*!< Start of transmission error flag on lane 0 */
+#define CSI_SR1_ESOTSYNCDL0F_Pos        (1U)
+#define CSI_SR1_ESOTSYNCDL0F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos)       /*!< 0x00000002 */
+#define CSI_SR1_ESOTSYNCDL0F            CSI_SR1_ESOTSYNCDL0F_Msk                 /*!< Start of transmission synchronization error flag on lane 0 */
+#define CSI_SR1_EESCDL0F_Pos            (2U)
+#define CSI_SR1_EESCDL0F_Msk            (0x1UL << CSI_SR1_EESCDL0F_Pos)           /*!< 0x00000004 */
+#define CSI_SR1_EESCDL0F                CSI_SR1_EESCDL0F_Msk                     /*!< D-PHY_RX lane 0 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL0F_Pos        (3U)
+#define CSI_SR1_ESYNCESCDL0F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos)       /*!< 0x00000008 */
+#define CSI_SR1_ESYNCESCDL0F            CSI_SR1_ESYNCESCDL0F_Msk                 /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL0F_Pos           (4U)
+#define CSI_SR1_ECTRLDL0F_Msk           (0x1UL << CSI_SR1_ECTRLDL0F_Pos)          /*!< 0x00000010 */
+#define CSI_SR1_ECTRLDL0F               CSI_SR1_ECTRLDL0F_Msk                    /*!< D-PHY_RX lane 0 control error flag */
+#define CSI_SR1_ESOTDL1F_Pos            (8U)
+#define CSI_SR1_ESOTDL1F_Msk            (0x1UL << CSI_SR1_ESOTDL1F_Pos)           /*!< 0x00000100 */
+#define CSI_SR1_ESOTDL1F                CSI_SR1_ESOTDL1F_Msk                     /*!< Start of transmission error flag on lane 1 */
+#define CSI_SR1_ESOTSYNCDL1F_Pos        (9U)
+#define CSI_SR1_ESOTSYNCDL1F_Msk        (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos)       /*!< 0x00000200 */
+#define CSI_SR1_ESOTSYNCDL1F            CSI_SR1_ESOTSYNCDL1F_Msk                 /*!< Start of transmission synchronization error flag on lane 1 */
+#define CSI_SR1_EESCDL1F_Pos            (10U)
+#define CSI_SR1_EESCDL1F_Msk            (0x1UL << CSI_SR1_EESCDL1F_Pos)           /*!< 0x00000400 */
+#define CSI_SR1_EESCDL1F                CSI_SR1_EESCDL1F_Msk                     /*!< D-PHY_RX lane 1 escape entry error flag */
+#define CSI_SR1_ESYNCESCDL1F_Pos        (11U)
+#define CSI_SR1_ESYNCESCDL1F_Msk        (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos)       /*!< 0x00000800 */
+#define CSI_SR1_ESYNCESCDL1F            CSI_SR1_ESYNCESCDL1F_Msk                 /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_SR1_ECTRLDL1F_Pos           (12U)
+#define CSI_SR1_ECTRLDL1F_Msk           (0x1UL << CSI_SR1_ECTRLDL1F_Pos)          /*!< 0x00001000 */
+#define CSI_SR1_ECTRLDL1F               CSI_SR1_ECTRLDL1F_Msk                    /*!< D-PHY_RX lane 1 control error flag */
+#define CSI_SR1_ACTDL0F_Pos             (16U)
+#define CSI_SR1_ACTDL0F_Msk             (0x1UL << CSI_SR1_ACTDL0F_Pos)            /*!< 0x00010000 */
+#define CSI_SR1_ACTDL0F                 CSI_SR1_ACTDL0F_Msk                      /*!< D-PHY_RX lane 0 High speed reception active */
+#define CSI_SR1_SYNCDL0F_Pos            (17U)
+#define CSI_SR1_SYNCDL0F_Msk            (0x1UL << CSI_SR1_SYNCDL0F_Pos)           /*!< 0x00020000 */
+#define CSI_SR1_SYNCDL0F                CSI_SR1_SYNCDL0F_Msk                     /*!< D-PHY_RX lane 0 receiver synchronization observed */
+#define CSI_SR1_SKCALDL0F_Pos           (18U)
+#define CSI_SR1_SKCALDL0F_Msk           (0x1UL << CSI_SR1_SKCALDL0F_Pos)          /*!< 0x00040000 */
+#define CSI_SR1_SKCALDL0F               CSI_SR1_SKCALDL0F_Msk                    /*!< D-PHY_RX lane 0 High speed skew calibration */
+#define CSI_SR1_STOPDL0F_Pos            (19U)
+#define CSI_SR1_STOPDL0F_Msk            (0x1UL << CSI_SR1_STOPDL0F_Pos)           /*!< 0x00080000 */
+#define CSI_SR1_STOPDL0F                CSI_SR1_STOPDL0F_Msk                     /*!< D-PHY_RX receiver data lane 0 in stop state */
+#define CSI_SR1_ULPNDL0F_Pos            (20U)
+#define CSI_SR1_ULPNDL0F_Msk            (0x1UL << CSI_SR1_ULPNDL0F_Pos)           /*!< 0x00100000 */
+#define CSI_SR1_ULPNDL0F                CSI_SR1_ULPNDL0F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */
+#define CSI_SR1_ACTDL1F_Pos             (22U)
+#define CSI_SR1_ACTDL1F_Msk             (0x1UL << CSI_SR1_ACTDL1F_Pos)            /*!< 0x00400000 */
+#define CSI_SR1_ACTDL1F                 CSI_SR1_ACTDL1F_Msk                      /*!< D-PHY_RX lane 1 High speed reception active */
+#define CSI_SR1_SYNCDL1F_Pos            (23U)
+#define CSI_SR1_SYNCDL1F_Msk            (0x1UL << CSI_SR1_SYNCDL1F_Pos)           /*!< 0x00800000 */
+#define CSI_SR1_SYNCDL1F                CSI_SR1_SYNCDL1F_Msk                     /*!< D-PHY_RX lane 1 receiver synchronization observed */
+#define CSI_SR1_SKCALDL1F_Pos           (24U)
+#define CSI_SR1_SKCALDL1F_Msk           (0x1UL << CSI_SR1_SKCALDL1F_Pos)          /*!< 0x01000000 */
+#define CSI_SR1_SKCALDL1F               CSI_SR1_SKCALDL1F_Msk                    /*!< D-PHY_RX lane 1 High speed skew calibration */
+#define CSI_SR1_STOPDL1F_Pos            (25U)
+#define CSI_SR1_STOPDL1F_Msk            (0x1UL << CSI_SR1_STOPDL1F_Pos)           /*!< 0x02000000 */
+#define CSI_SR1_STOPDL1F                CSI_SR1_STOPDL1F_Msk                     /*!< D-PHY_RX receiver data lane 1 in stop state */
+#define CSI_SR1_ULPNDL1F_Pos            (26U)
+#define CSI_SR1_ULPNDL1F_Msk            (0x1UL << CSI_SR1_ULPNDL1F_Pos)           /*!< 0x04000000 */
+#define CSI_SR1_ULPNDL1F                CSI_SR1_ULPNDL1F_Msk                     /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */
+#define CSI_SR1_STOPCLF_Pos             (28U)
+#define CSI_SR1_STOPCLF_Msk             (0x1UL << CSI_SR1_STOPCLF_Pos)            /*!< 0x10000000 */
+#define CSI_SR1_STOPCLF                 CSI_SR1_STOPCLF_Msk                      /*!< D-PHY_RX receiver in stop state for the clock lane */
+#define CSI_SR1_ULPNACTF_Pos            (29U)
+#define CSI_SR1_ULPNACTF_Msk            (0x1UL << CSI_SR1_ULPNACTF_Pos)           /*!< 0x20000000 */
+#define CSI_SR1_ULPNACTF                CSI_SR1_ULPNACTF_Msk                     /*!< D-PHY_RX receiver ULP state (not) active */
+#define CSI_SR1_ULPNCLF_Pos             (30U)
+#define CSI_SR1_ULPNCLF_Msk             (0x1UL << CSI_SR1_ULPNCLF_Pos)            /*!< 0x40000000 */
+#define CSI_SR1_ULPNCLF                 CSI_SR1_ULPNCLF_Msk                      /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */
+#define CSI_SR1_ACTCLF_Pos              (31U)
+#define CSI_SR1_ACTCLF_Msk              (0x1UL << CSI_SR1_ACTCLF_Pos)             /*!< 0x80000000 */
+#define CSI_SR1_ACTCLF                  CSI_SR1_ACTCLF_Msk                       /*!< D-PHY_RX receiver clock active flag */
+
+/*******************  Bit definition for CSI_FCR0 register  *******************/
+#define CSI_FCR0_CLB0F_Pos              (0U)
+#define CSI_FCR0_CLB0F_Msk              (0x1UL << CSI_FCR0_CLB0F_Pos)             /*!< 0x00000001 */
+#define CSI_FCR0_CLB0F                  CSI_FCR0_CLB0F_Msk                       /*!< Clear Line byte counter 0 flag */
+#define CSI_FCR0_CLB1F_Pos              (1U)
+#define CSI_FCR0_CLB1F_Msk              (0x1UL << CSI_FCR0_CLB1F_Pos)             /*!< 0x00000002 */
+#define CSI_FCR0_CLB1F                  CSI_FCR0_CLB1F_Msk                       /*!< Clear Line byte counter 1 flag */
+#define CSI_FCR0_CLB2F_Pos              (2U)
+#define CSI_FCR0_CLB2F_Msk              (0x1UL << CSI_FCR0_CLB2F_Pos)             /*!< 0x00000004 */
+#define CSI_FCR0_CLB2F                  CSI_FCR0_CLB2F_Msk                       /*!< Clear Line byte counter 2 flag */
+#define CSI_FCR0_CLB3F_Pos              (3U)
+#define CSI_FCR0_CLB3F_Msk              (0x1UL << CSI_FCR0_CLB3F_Pos)             /*!< 0x00000008 */
+#define CSI_FCR0_CLB3F                  CSI_FCR0_CLB3F_Msk                       /*!< Clear Line byte counter 3 flag */
+#define CSI_FCR0_CTIM0F_Pos             (4U)
+#define CSI_FCR0_CTIM0F_Msk             (0x1UL << CSI_FCR0_CTIM0F_Pos)            /*!< 0x00000010 */
+#define CSI_FCR0_CTIM0F                 CSI_FCR0_CTIM0F_Msk                      /*!< Clear Timer 0 flag */
+#define CSI_FCR0_CTIM1F_Pos             (5U)
+#define CSI_FCR0_CTIM1F_Msk             (0x1UL << CSI_FCR0_CTIM1F_Pos)            /*!< 0x00000020 */
+#define CSI_FCR0_CTIM1F                 CSI_FCR0_CTIM1F_Msk                      /*!< Clear Timer 1 flag */
+#define CSI_FCR0_CTIM2F_Pos             (6U)
+#define CSI_FCR0_CTIM2F_Msk             (0x1UL << CSI_FCR0_CTIM2F_Pos)            /*!< 0x00000040 */
+#define CSI_FCR0_CTIM2F                 CSI_FCR0_CTIM2F_Msk                      /*!< Clear Timer 2 flag */
+#define CSI_FCR0_CTIM3F_Pos             (7U)
+#define CSI_FCR0_CTIM3F_Msk             (0x1UL << CSI_FCR0_CTIM3F_Pos)            /*!< 0x00000080 */
+#define CSI_FCR0_CTIM3F                 CSI_FCR0_CTIM3F_Msk                      /*!< Clear Timer 3 flag */
+#define CSI_FCR0_CSOF0F_Pos             (8U)
+#define CSI_FCR0_CSOF0F_Msk             (0x1UL << CSI_FCR0_CSOF0F_Pos)            /*!< 0x00000100 */
+#define CSI_FCR0_CSOF0F                 CSI_FCR0_CSOF0F_Msk                      /*!< Clear Start of frame flag for virtual channel 0 */
+#define CSI_FCR0_CSOF1F_Pos             (9U)
+#define CSI_FCR0_CSOF1F_Msk             (0x1UL << CSI_FCR0_CSOF1F_Pos)            /*!< 0x00000200 */
+#define CSI_FCR0_CSOF1F                 CSI_FCR0_CSOF1F_Msk                      /*!< Clear Start of frame flag for virtual channel 1 */
+#define CSI_FCR0_CSOF2F_Pos             (10U)
+#define CSI_FCR0_CSOF2F_Msk             (0x1UL << CSI_FCR0_CSOF2F_Pos)            /*!< 0x00000400 */
+#define CSI_FCR0_CSOF2F                 CSI_FCR0_CSOF2F_Msk                      /*!< Clear Start of frame flag for virtual channel 2 */
+#define CSI_FCR0_CSOF3F_Pos             (11U)
+#define CSI_FCR0_CSOF3F_Msk             (0x1UL << CSI_FCR0_CSOF3F_Pos)            /*!< 0x00000800 */
+#define CSI_FCR0_CSOF3F                 CSI_FCR0_CSOF3F_Msk                      /*!< Clear Start of frame flag for virtual channel 3 */
+#define CSI_FCR0_CEOF0F_Pos             (12U)
+#define CSI_FCR0_CEOF0F_Msk             (0x1UL << CSI_FCR0_CEOF0F_Pos)            /*!< 0x00001000 */
+#define CSI_FCR0_CEOF0F                 CSI_FCR0_CEOF0F_Msk                      /*!< Clear End of frame flag for virtual channel 0 */
+#define CSI_FCR0_CEOF1F_Pos             (13U)
+#define CSI_FCR0_CEOF1F_Msk             (0x1UL << CSI_FCR0_CEOF1F_Pos)            /*!< 0x00002000 */
+#define CSI_FCR0_CEOF1F                 CSI_FCR0_CEOF1F_Msk                      /*!< Clear End of frame flag for virtual channel 1 */
+#define CSI_FCR0_CEOF2F_Pos             (14U)
+#define CSI_FCR0_CEOF2F_Msk             (0x1UL << CSI_FCR0_CEOF2F_Pos)            /*!< 0x00004000 */
+#define CSI_FCR0_CEOF2F                 CSI_FCR0_CEOF2F_Msk                      /*!< Clear End of frame flag for virtual channel 2 */
+#define CSI_FCR0_CEOF3F_Pos             (15U)
+#define CSI_FCR0_CEOF3F_Msk             (0x1UL << CSI_FCR0_CEOF3F_Pos)            /*!< 0x00008000 */
+#define CSI_FCR0_CEOF3F                 CSI_FCR0_CEOF3F_Msk                      /*!< Clear End of frame flag for virtual channel 3 */
+#define CSI_FCR0_CSPKTF_Pos             (16U)
+#define CSI_FCR0_CSPKTF_Msk             (0x1UL << CSI_FCR0_CSPKTF_Pos)            /*!< 0x00010000 */
+#define CSI_FCR0_CSPKTF                 CSI_FCR0_CSPKTF_Msk                      /*!< Clear Short packet flag */
+#define CSI_FCR0_CCCFIFOFF_Pos          (21U)
+#define CSI_FCR0_CCCFIFOFF_Msk          (0x1UL << CSI_FCR0_CCCFIFOFF_Pos)         /*!< 0x00200000 */
+#define CSI_FCR0_CCCFIFOFF              CSI_FCR0_CCCFIFOFF_Msk                   /*!< Clear Clock changer FIFO full flag */
+#define CSI_FCR0_CCRCERRF_Pos           (24U)
+#define CSI_FCR0_CCRCERRF_Msk           (0x1UL << CSI_FCR0_CCRCERRF_Pos)          /*!< 0x01000000 */
+#define CSI_FCR0_CCRCERRF               CSI_FCR0_CCRCERRF_Msk                    /*!< Clear CRC error flag */
+#define CSI_FCR0_CECCERRF_Pos           (25U)
+#define CSI_FCR0_CECCERRF_Msk           (0x1UL << CSI_FCR0_CECCERRF_Pos)          /*!< 0x02000000 */
+#define CSI_FCR0_CECCERRF               CSI_FCR0_CECCERRF_Msk                    /*!< Clear ECC error flag */
+#define CSI_FCR0_CCECCERRF_Pos          (26U)
+#define CSI_FCR0_CCECCERRF_Msk          (0x1UL << CSI_FCR0_CCECCERRF_Pos)         /*!< 0x04000000 */
+#define CSI_FCR0_CCECCERRF              CSI_FCR0_CCECCERRF_Msk                   /*!< Clear Corrected ECC error flag */
+#define CSI_FCR0_CIDERRF_Pos            (27U)
+#define CSI_FCR0_CIDERRF_Msk            (0x1UL << CSI_FCR0_CIDERRF_Pos)           /*!< 0x08000000 */
+#define CSI_FCR0_CIDERRF                CSI_FCR0_CIDERRF_Msk                     /*!< Clear Data type ID error flag */
+#define CSI_FCR0_CSPKTERRF_Pos          (28U)
+#define CSI_FCR0_CSPKTERRF_Msk          (0x1UL << CSI_FCR0_CSPKTERRF_Pos)         /*!< 0x10000000 */
+#define CSI_FCR0_CSPKTERRF              CSI_FCR0_CSPKTERRF_Msk                   /*!< Clear Short packet error flag */
+#define CSI_FCR0_CWDERRF_Pos            (29U)
+#define CSI_FCR0_CWDERRF_Msk            (0x1UL << CSI_FCR0_CWDERRF_Pos)           /*!< 0x20000000 */
+#define CSI_FCR0_CWDERRF                CSI_FCR0_CWDERRF_Msk                     /*!< Clear Watchdog error flag */
+#define CSI_FCR0_CSYNCERRF_Pos          (30U)
+#define CSI_FCR0_CSYNCERRF_Msk          (0x1UL << CSI_FCR0_CSYNCERRF_Pos)         /*!< 0x40000000 */
+#define CSI_FCR0_CSYNCERRF              CSI_FCR0_CSYNCERRF_Msk                   /*!< Clear Invalid synchronization error flag */
+
+/*******************  Bit definition for CSI_FCR1 register  *******************/
+#define CSI_FCR1_CESOTDL0F_Pos          (0U)
+#define CSI_FCR1_CESOTDL0F_Msk          (0x1UL << CSI_FCR1_CESOTDL0F_Pos)         /*!< 0x00000001 */
+#define CSI_FCR1_CESOTDL0F              CSI_FCR1_CESOTDL0F_Msk                   /*!< Clear Start of transmission error flag on lane 0 */
+#define CSI_FCR1_CESOTSYNCDL0F_Pos      (1U)
+#define CSI_FCR1_CESOTSYNCDL0F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos)     /*!< 0x00000002 */
+#define CSI_FCR1_CESOTSYNCDL0F          CSI_FCR1_CESOTSYNCDL0F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 0 */
+#define CSI_FCR1_CEESCDL0F_Pos          (2U)
+#define CSI_FCR1_CEESCDL0F_Msk          (0x1UL << CSI_FCR1_CEESCDL0F_Pos)         /*!< 0x00000004 */
+#define CSI_FCR1_CEESCDL0F              CSI_FCR1_CEESCDL0F_Msk                   /*!< Clear D-PHY_RX lane 0 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL0F_Pos      (3U)
+#define CSI_FCR1_CESYNCESCDL0F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos)     /*!< 0x00000008 */
+#define CSI_FCR1_CESYNCESCDL0F          CSI_FCR1_CESYNCESCDL0F_Msk               /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL0F_Pos         (4U)
+#define CSI_FCR1_CECTRLDL0F_Msk         (0x1UL << CSI_FCR1_CECTRLDL0F_Pos)        /*!< 0x00000010 */
+#define CSI_FCR1_CECTRLDL0F             CSI_FCR1_CECTRLDL0F_Msk                  /*!< Clear D-PHY_RX lane 0 control error flag */
+#define CSI_FCR1_CESOTDL1F_Pos          (8U)
+#define CSI_FCR1_CESOTDL1F_Msk          (0x1UL << CSI_FCR1_CESOTDL1F_Pos)         /*!< 0x00000100 */
+#define CSI_FCR1_CESOTDL1F              CSI_FCR1_CESOTDL1F_Msk                   /*!< Clear Start of transmission error flag on lane 1 */
+#define CSI_FCR1_CESOTSYNCDL1F_Pos      (9U)
+#define CSI_FCR1_CESOTSYNCDL1F_Msk      (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos)     /*!< 0x00000200 */
+#define CSI_FCR1_CESOTSYNCDL1F          CSI_FCR1_CESOTSYNCDL1F_Msk               /*!< Clear Start of transmission synchronization error flag on lane 1 */
+#define CSI_FCR1_CEESCDL1F_Pos          (10U)
+#define CSI_FCR1_CEESCDL1F_Msk          (0x1UL << CSI_FCR1_CEESCDL1F_Pos)         /*!< 0x00000400 */
+#define CSI_FCR1_CEESCDL1F              CSI_FCR1_CEESCDL1F_Msk                   /*!< Clear D-PHY_RX lane 1 escape entry error flag */
+#define CSI_FCR1_CESYNCESCDL1F_Pos      (11U)
+#define CSI_FCR1_CESYNCESCDL1F_Msk      (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos)     /*!< 0x00000800 */
+#define CSI_FCR1_CESYNCESCDL1F          CSI_FCR1_CESYNCESCDL1F_Msk               /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */
+#define CSI_FCR1_CECTRLDL1F_Pos         (12U)
+#define CSI_FCR1_CECTRLDL1F_Msk         (0x1UL << CSI_FCR1_CECTRLDL1F_Pos)        /*!< 0x00001000 */
+#define CSI_FCR1_CECTRLDL1F             CSI_FCR1_CECTRLDL1F_Msk                  /*!< Clear D-PHY_RX lane 1 control error flag */
+
+/******************  Bit definition for CSI_SPDFR register  *******************/
+#define CSI_SPDFR_DATAFIELD_Pos         (0U)
+#define CSI_SPDFR_DATAFIELD_Msk         (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos)     /*!< 0x0000FFFF */
+#define CSI_SPDFR_DATAFIELD             CSI_SPDFR_DATAFIELD_Msk                  /*!< Data field */
+#define CSI_SPDFR_DATATYPE_Pos          (16U)
+#define CSI_SPDFR_DATATYPE_Msk          (0x3FUL << CSI_SPDFR_DATATYPE_Pos)        /*!< 0x003F0000 */
+#define CSI_SPDFR_DATATYPE              CSI_SPDFR_DATATYPE_Msk                   /*!< Data type class */
+#define CSI_SPDFR_VCHANNEL_Pos          (22U)
+#define CSI_SPDFR_VCHANNEL_Msk          (0x3UL << CSI_SPDFR_VCHANNEL_Pos)         /*!< 0x00C00000 */
+#define CSI_SPDFR_VCHANNEL              CSI_SPDFR_VCHANNEL_Msk                   /*!< Virtual channel */
+
+/*******************  Bit definition for CSI_ERR1 register  *******************/
+#define CSI_ERR1_CRCDTERR_Pos           (0U)
+#define CSI_ERR1_CRCDTERR_Msk           (0x3FUL << CSI_ERR1_CRCDTERR_Pos)         /*!< 0x0000003F */
+#define CSI_ERR1_CRCDTERR               CSI_ERR1_CRCDTERR_Msk                    /*!< Data type having a CRC error */
+#define CSI_ERR1_CRCVCERR_Pos           (6U)
+#define CSI_ERR1_CRCVCERR_Msk           (0x3UL << CSI_ERR1_CRCVCERR_Pos)          /*!< 0x000000C0 */
+#define CSI_ERR1_CRCVCERR               CSI_ERR1_CRCVCERR_Msk                    /*!< Virtual channel having a CRC error */
+#define CSI_ERR1_CECCDTERR_Pos          (8U)
+#define CSI_ERR1_CECCDTERR_Msk          (0x3FUL << CSI_ERR1_CECCDTERR_Pos)        /*!< 0x00003F00 */
+#define CSI_ERR1_CECCDTERR              CSI_ERR1_CECCDTERR_Msk                   /*!< Data type having a corrected ECC error */
+#define CSI_ERR1_CECCVCERR_Pos          (14U)
+#define CSI_ERR1_CECCVCERR_Msk          (0x3UL << CSI_ERR1_CECCVCERR_Pos)         /*!< 0x0000C000 */
+#define CSI_ERR1_CECCVCERR              CSI_ERR1_CECCVCERR_Msk                   /*!< Virtual channel having a corrected ECC error */
+#define CSI_ERR1_IDDTERR_Pos            (16U)
+#define CSI_ERR1_IDDTERR_Msk            (0x3FUL << CSI_ERR1_IDDTERR_Pos)          /*!< 0x003F0000 */
+#define CSI_ERR1_IDDTERR                CSI_ERR1_IDDTERR_Msk                     /*!< Data type in error */
+#define CSI_ERR1_IDVCERR_Pos            (22U)
+#define CSI_ERR1_IDVCERR_Msk            (0x3UL << CSI_ERR1_IDVCERR_Pos)           /*!< 0x00C00000 */
+#define CSI_ERR1_IDVCERR                CSI_ERR1_IDVCERR_Msk                     /*!< Virtual channel having ID error */
+
+/*******************  Bit definition for CSI_ERR2 register  *******************/
+#define CSI_ERR2_SPKTDTERR_Pos          (0U)
+#define CSI_ERR2_SPKTDTERR_Msk          (0x3FUL << CSI_ERR2_SPKTDTERR_Pos)        /*!< 0x0000003F */
+#define CSI_ERR2_SPKTDTERR              CSI_ERR2_SPKTDTERR_Msk                   /*!< Data type having a short packet error */
+#define CSI_ERR2_SPKTVCERR_Pos          (6U)
+#define CSI_ERR2_SPKTVCERR_Msk          (0x3UL << CSI_ERR2_SPKTVCERR_Pos)         /*!< 0x000000C0 */
+#define CSI_ERR2_SPKTVCERR              CSI_ERR2_SPKTVCERR_Msk                   /*!< Virtual channel having a short packet error */
+#define CSI_ERR2_WDVCERR_Pos            (16U)
+#define CSI_ERR2_WDVCERR_Msk            (0x3UL << CSI_ERR2_WDVCERR_Pos)           /*!< 0x00030000 */
+#define CSI_ERR2_WDVCERR                CSI_ERR2_WDVCERR_Msk                     /*!< Virtual channel having a watchdog error */
+#define CSI_ERR2_SYNCVCERR_Pos          (18U)
+#define CSI_ERR2_SYNCVCERR_Msk          (0x3UL << CSI_ERR2_SYNCVCERR_Pos)         /*!< 0x000C0000 */
+#define CSI_ERR2_SYNCVCERR              CSI_ERR2_SYNCVCERR_Msk                   /*!< Virtual channel having synchronization error */
+
+/*******************  Bit definition for CSI_PRCR register  *******************/
+#define CSI_PRCR_PEN_Pos                (1U)
+#define CSI_PRCR_PEN_Msk                (0x1UL << CSI_PRCR_PEN_Pos)               /*!< 0x00000002 */
+#define CSI_PRCR_PEN                    CSI_PRCR_PEN_Msk                         /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */
+
+/*******************  Bit definition for CSI_PMCR register  *******************/
+#define CSI_PMCR_FRXMDL0_Pos            (0U)
+#define CSI_PMCR_FRXMDL0_Msk            (0x1UL << CSI_PMCR_FRXMDL0_Pos)           /*!< 0x00000001 */
+#define CSI_PMCR_FRXMDL0                CSI_PMCR_FRXMDL0_Msk                     /*!< Force to Rx Mode the Data Lane 0 */
+#define CSI_PMCR_FRXMDL1_Pos            (1U)
+#define CSI_PMCR_FRXMDL1_Msk            (0x1UL << CSI_PMCR_FRXMDL1_Pos)           /*!< 0x00000002 */
+#define CSI_PMCR_FRXMDL1                CSI_PMCR_FRXMDL1_Msk                     /*!< Force to Rx Mode the Data Lane 1 */
+#define CSI_PMCR_FTXSMDL0_Pos           (2U)
+#define CSI_PMCR_FTXSMDL0_Msk           (0x1UL << CSI_PMCR_FTXSMDL0_Pos)          /*!< 0x00000004 */
+#define CSI_PMCR_FTXSMDL0               CSI_PMCR_FTXSMDL0_Msk                    /*!< Force to Tx Stop Mode the Data Lane 0 */
+#define CSI_PMCR_DTDL_Pos               (4U)
+#define CSI_PMCR_DTDL_Msk               (0x1UL << CSI_PMCR_DTDL_Pos)              /*!< 0x00000010 */
+#define CSI_PMCR_DTDL                   CSI_PMCR_DTDL_Msk                        /*!< Disable Turn-around Data Lane 0 */
+#define CSI_PMCR_RTDL0_Pos              (8U)
+#define CSI_PMCR_RTDL0_Msk              (0x1UL << CSI_PMCR_RTDL0_Pos)             /*!< 0x00000100 */
+#define CSI_PMCR_RTDL0                  CSI_PMCR_RTDL0_Msk                       /*!< Turn-around Request Data Lane 0 */
+#define CSI_PMCR_TUESDL0_Pos            (12U)
+#define CSI_PMCR_TUESDL0_Msk            (0x1UL << CSI_PMCR_TUESDL0_Pos)           /*!< 0x00001000 */
+#define CSI_PMCR_TUESDL0                CSI_PMCR_TUESDL0_Msk                     /*!< Tx ULP Escape-mode Data Lane 0 */
+#define CSI_PMCR_TUEXDL0_Pos            (16U)
+#define CSI_PMCR_TUEXDL0_Msk            (0x1UL << CSI_PMCR_TUEXDL0_Pos)           /*!< 0x00010000 */
+#define CSI_PMCR_TUEXDL0                CSI_PMCR_TUEXDL0_Msk                     /*!< Tx ULP Exit-sequence Data Lane 0 */
+
+/*******************  Bit definition for CSI_PFCR register  *******************/
+#define CSI_PFCR_CCFR_Pos               (0U)
+#define CSI_PFCR_CCFR_Msk               (0x3FUL << CSI_PFCR_CCFR_Pos)             /*!< 0x0000003F */
+#define CSI_PFCR_CCFR                   CSI_PFCR_CCFR_Msk                        /*!< Configuration Clock Frequency Range selection */
+#define CSI_PFCR_HSFR_Pos               (8U)
+#define CSI_PFCR_HSFR_Msk               (0x7FUL << CSI_PFCR_HSFR_Pos)             /*!< 0x00007F00 */
+#define CSI_PFCR_HSFR                   CSI_PFCR_HSFR_Msk                        /*!< PHY-high-speed Frequency Range selection */
+#define CSI_PFCR_DLD_Pos                (16U)
+#define CSI_PFCR_DLD_Msk                (0x1UL << CSI_PFCR_DLD_Pos)               /*!< 0x00010000 */
+#define CSI_PFCR_DLD                    CSI_PFCR_DLD_Msk                         /*!< Data Lane Direction of lane0 */
+
+/******************  Bit definition for CSI_PTCR0 register  *******************/
+#define CSI_PTCR0_TCKEN_Pos             (0U)
+#define CSI_PTCR0_TCKEN_Msk             (0x1UL << CSI_PTCR0_TCKEN_Pos)            /*!< 0x00000001 */
+#define CSI_PTCR0_TCKEN                 CSI_PTCR0_TCKEN_Msk                      /*!< Test-interface Clock Enable for the TDI bus into the PHY */
+#define CSI_PTCR0_TRSEN_Pos             (1U)
+#define CSI_PTCR0_TRSEN_Msk             (0x1UL << CSI_PTCR0_TRSEN_Pos)            /*!< 0x00000002 */
+#define CSI_PTCR0_TRSEN                 CSI_PTCR0_TRSEN_Msk                      /*!< Test-interface Reset Enable for the TDI bus into the PHY */
+
+/******************  Bit definition for CSI_PTCR1 register  *******************/
+#define CSI_PTCR1_TDI_Pos               (0U)
+#define CSI_PTCR1_TDI_Msk               (0xFFUL << CSI_PTCR1_TDI_Pos)             /*!< 0x000000FF */
+#define CSI_PTCR1_TDI                   CSI_PTCR1_TDI_Msk                        /*!< Test-interface Data In */
+#define CSI_PTCR1_TWM_Pos               (16U)
+#define CSI_PTCR1_TWM_Msk               (0x1UL << CSI_PTCR1_TWM_Pos)              /*!< 0x00010000 */
+#define CSI_PTCR1_TWM                   CSI_PTCR1_TWM_Msk                        /*!< Test-interface Write Mode selector */
+
+/*******************  Bit definition for CSI_PTSR register  *******************/
+#define CSI_PTSR_TDO_Pos                (0U)
+#define CSI_PTSR_TDO_Msk                (0xFFUL << CSI_PTSR_TDO_Pos)              /*!< 0x000000FF */
+#define CSI_PTSR_TDO                    CSI_PTSR_TDO_Msk                         /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                DBGMCU                                         */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  ****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos             (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk             (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)          /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                 DBGMCU_IDCODE_DEV_ID_Msk                       /*!< Device ID */
+#define DBGMCU_IDCODE_REV_ID_Pos             (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk             (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)         /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                 DBGMCU_IDCODE_REV_ID_Msk                       /*!< Revision ID */
+
+/********************  Bit definition for DBGMCU_CR register  ********************/
+#define DBGMCU_CR_DBG_SLEEP_Pos              (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk              (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)             /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                  DBGMCU_CR_DBG_SLEEP_Msk                        /*!< Allow debug in Sleep mode */
+#define DBGMCU_CR_DBG_STOP_Pos               (1U)
+#define DBGMCU_CR_DBG_STOP_Msk               (0x1UL << DBGMCU_CR_DBG_STOP_Pos)              /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                   DBGMCU_CR_DBG_STOP_Msk                         /*!< Allow debug in Stop mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos            (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk            (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)           /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                DBGMCU_CR_DBG_STANDBY_Msk                      /*!< Allow debug in Standby mode */
+#define DBGMCU_CR_DBGCLKEN_Pos               (20U)
+#define DBGMCU_CR_DBGCLKEN_Msk               (0x1UL << DBGMCU_CR_DBGCLKEN_Pos)              /*!< 0x00100000 */
+#define DBGMCU_CR_DBGCLKEN                   DBGMCU_CR_DBGCLKEN_Msk                         /*!< Debug clock enable through software */
+#define DBGMCU_CR_TRACECLKEN_Pos             (21U)
+#define DBGMCU_CR_TRACECLKEN_Msk             (0x1UL << DBGMCU_CR_TRACECLKEN_Pos)            /*!< 0x00200000 */
+#define DBGMCU_CR_TRACECLKEN                 DBGMCU_CR_TRACECLKEN_Msk                       /*!< TPIU export clock enable through software */
+#define DBGMCU_CR_DBTRGOEN_Pos               (28U)
+#define DBGMCU_CR_DBTRGOEN_Msk               (0x1UL << DBGMCU_CR_DBTRGOEN_Pos)              /*!< 0x10000000 */
+#define DBGMCU_CR_DBTRGOEN                   DBGMCU_CR_DBTRGOEN_Msk                         /*!< DBTRGIO connection control */
+#define DBGMCU_CR_HLT_TSGEN_EN_Pos           (31U)
+#define DBGMCU_CR_HLT_TSGEN_EN_Msk           (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos)          /*!< 0x80000000 */
+#define DBGMCU_CR_HLT_TSGEN_EN               DBGMCU_CR_HLT_TSGEN_EN_Msk                     /*!< TSGEN halt enable */
+
+/********************  Bit definition for DBGMCU_APB1LFZ1 register  ***************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos    (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP        DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk              /*!< TIM2 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos    (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP        DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk              /*!< TIM3 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos    (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP        DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk              /*!< TIM4 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos    (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP        DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk              /*!< TIM5 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos    (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP        DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk              /*!< TIM6 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos    (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos)  /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP        DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk             /*!< TIM7 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos   (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos)  /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP       DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk             /*!< TIM12 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos   (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos)  /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP       DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk             /*!< TIM13 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos   (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP       DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk             /*!< TIM14 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos  (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP      DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk            /*!< LPTIM1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos   (11U)
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP       DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk             /*!< WWDG1 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos   (12U)
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP       DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk             /*!< TIM10 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos   (13U)
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP       DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk             /*!< TIM11 stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos    (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos)   /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP        DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk              /*!< I2C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos    (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos)   /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP        DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk              /*!< I2C2 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos    (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos)   /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP        DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk              /*!< I2C3 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos    (24U)
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos)   /*!< 0x01000000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP        DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk              /*!< I3C1 SMBUS timeout stop in debug */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos    (25U)
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP        DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk              /*!< I3C2 SMBUS timeout stop in debug */
+
+/********************  Bit definition for DBGMCU_APB1HFZ1 register  ***************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos   (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk   (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos)  /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP       DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk             /*!< FDCAN stop in debug */
+
+/********************  Bit definition for DBGMCU_APB2FZ1 register  ***************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos     (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos)    /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1_STOP         DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk               /*!< TIM1 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos     (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos)    /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8_STOP         DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk               /*!< TIM8 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos    (15U)
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos)   /*!< 0x00008000 */
+#define DBGMCU_APB2FZ1_DBG_TIM18_STOP        DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk              /*!< TIM18 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos    (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos)   /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15_STOP        DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk              /*!< TIM15 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos    (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos)   /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16_STOP        DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk              /*!< TIM16 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos    (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk    (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos)   /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17_STOP        DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk              /*!< TIM17 stop in debug */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos     (19U)
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk     (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos)    /*!< 0x00080000 */
+#define DBGMCU_APB2FZ1_DBG_TIM9_STOP         DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk               /*!< TIM9 stop in debug */
+
+/********************  Bit definition for DBGMCU_APB4FZ1 register  ***************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos     (8U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos)    /*!< 0x00000100 */
+#define DBGMCU_APB4FZ1_DBG_I2C4_STOP         DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk               /*!< I2C4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos   (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos)  /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP       DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk             /*!< LPTIM2 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos   (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP       DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk             /*!< LPTIM3 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos   (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP       DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk             /*!< LPTIM4 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos   (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP       DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk             /*!< LPTIM5 stop in debug */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos      (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos)     /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC_STOP          DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk                /*!< RTC stop in debug */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos     (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos)    /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG_STOP         DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk               /*!< IWDG stop in debug */
+
+/********************  Bit definition for DBGMCU_APB5FZ1 register  ***************/
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos   (4U)
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk   (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos)  /*!< 0x00000010 */
+#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP       DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk             /*!< GFXTIM stop in debug */
+
+/********************  Bit definition for DBGMCU_AHB1FZ1 register  ***************/
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk              /*!< GPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk              /*!< GPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk              /*!< GPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk              /*!< GPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk              /*!< GPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk              /*!< GPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk              /*!< GPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk              /*!< GPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk              /*!< GPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP        DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk              /*!< GPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk             /*!< GPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk             /*!< GPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk             /*!< GPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk             /*!< GPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk             /*!< GPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP       DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk             /*!< GPDMA1_CH15 suspend in debug */
+
+/********************  Bit definition for DBGMCU_AHB5FZ1 register  ***************/
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos    (0U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos)   /*!< 0x00000001 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk              /*!< HPDMA1_CH0 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos    (1U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos)   /*!< 0x00000002 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk              /*!< HPDMA1_CH1 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos    (2U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos)   /*!< 0x00000004 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk              /*!< HPDMA1_CH2 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos    (3U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos)   /*!< 0x00000008 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk              /*!< HPDMA1_CH3 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos    (4U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos)   /*!< 0x00000010 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk              /*!< HPDMA1_CH4 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos    (5U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos)   /*!< 0x00000020 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk              /*!< HPDMA1_CH5 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos    (6U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos)   /*!< 0x00000040 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk              /*!< HPDMA1_CH6 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos    (7U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos)   /*!< 0x00000080 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk              /*!< HPDMA1_CH7 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos    (8U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos)   /*!< 0x00000100 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk              /*!< HPDMA1_CH8 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos    (9U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk    (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos)   /*!< 0x00000200 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP        DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk              /*!< HPDMA1_CH9 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos   (10U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos)  /*!< 0x00000400 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk             /*!< HPDMA1_CH10 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos   (11U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos)  /*!< 0x00000800 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk             /*!< HPDMA1_CH11 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos   (12U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos)  /*!< 0x00001000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk             /*!< HPDMA1_CH12 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos   (13U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos)  /*!< 0x00002000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk             /*!< HPDMA1_CH13 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos   (14U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos)  /*!< 0x00004000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk             /*!< HPDMA1_CH14 suspend in debug */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos   (15U)
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk   (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos)  /*!< 0x00008000 */
+#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP       DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk             /*!< HPDMA1_CH15 suspend in debug */
+#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos         (16U)
+#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk         (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos)        /*!< 0x00010000 */
+#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE             DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk                   /*!< NPU stop in debug mode */
+
+/********************  Bit definition for DBGMCU_SR register  ***************/
+#define DBGMCU_SR_AP0_PRESENT_Pos            (0U)
+#define DBGMCU_SR_AP0_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos)           /*!< 0x00000001 */
+#define DBGMCU_SR_AP0_PRESENT                DBGMCU_SR_AP0_PRESENT_Msk                      /*!< Access point 0 presence */
+#define DBGMCU_SR_AP1_PRESENT_Pos            (1U)
+#define DBGMCU_SR_AP1_PRESENT_Msk            (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos)           /*!< 0x00000002 */
+#define DBGMCU_SR_AP1_PRESENT                DBGMCU_SR_AP1_PRESENT_Msk                      /*!< Access point 1 presence */
+#define DBGMCU_SR_AP0_ENABLE_Pos             (16U)
+#define DBGMCU_SR_AP0_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos)            /*!< 0x00010000 */
+#define DBGMCU_SR_AP0_ENABLE                 DBGMCU_SR_AP0_ENABLE_Msk                       /*!< Access point 0 enable */
+#define DBGMCU_SR_AP1_ENABLE_Pos             (17U)
+#define DBGMCU_SR_AP1_ENABLE_Msk             (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos)            /*!< 0x00020000 */
+#define DBGMCU_SR_AP1_ENABLE                 DBGMCU_SR_AP1_ENABLE_Msk                       /*!< Access point 1 enable */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_HOST register  **********************/
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos     (0U)
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk     (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_HOST_MESSAGE         DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk                   /*!< Message[31:0] */
+
+/******************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos      (0U)
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk      (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos)  /*!< 0xFFFFFFFF */
+#define DBGMCU_DBG_AUTH_DEV_MESSAGE          DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk                    /*!< Message[31:0] */
+
+/********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***************/
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos     (0U)
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk     (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos)    /*!< 0x00000001 */
+#define DBGMCU_DBG_AUTH_ACK_HOST_ACK         DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk               /*!< Access status to DBG_AUTH_HOST register */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos   (1U)
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk   (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos)  /*!< 0x00000002 */
+#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK       DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk             /*!< Access status to DBG_AUTH_DEV register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos                 (0U)
+#define DCMI_CR_CAPTURE_Msk                 (0x1UL << DCMI_CR_CAPTURE_Pos)          /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE                     DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos                      (1U)
+#define DCMI_CR_CM_Msk                      (0x1UL << DCMI_CR_CM_Pos)               /*!< 0x00000002 */
+#define DCMI_CR_CM                          DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos                    (2U)
+#define DCMI_CR_CROP_Msk                    (0x1UL << DCMI_CR_CROP_Pos)             /*!< 0x00000004 */
+#define DCMI_CR_CROP                        DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos                    (3U)
+#define DCMI_CR_JPEG_Msk                    (0x1UL << DCMI_CR_JPEG_Pos)             /*!< 0x00000008 */
+#define DCMI_CR_JPEG                        DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos                     (4U)
+#define DCMI_CR_ESS_Msk                     (0x1UL << DCMI_CR_ESS_Pos)              /*!< 0x00000010 */
+#define DCMI_CR_ESS                         DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos                  (5U)
+#define DCMI_CR_PCKPOL_Msk                  (0x1UL << DCMI_CR_PCKPOL_Pos)           /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL                      DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos                   (6U)
+#define DCMI_CR_HSPOL_Msk                   (0x1UL << DCMI_CR_HSPOL_Pos)            /*!< 0x00000040 */
+#define DCMI_CR_HSPOL                       DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos                   (7U)
+#define DCMI_CR_VSPOL_Msk                   (0x1UL << DCMI_CR_VSPOL_Pos)            /*!< 0x00000080 */
+#define DCMI_CR_VSPOL                       DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_Pos                    (8U)
+#define DCMI_CR_FCRC_Msk                    (0x3UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000300 */
+#define DCMI_CR_FCRC                        DCMI_CR_FCRC_Msk                        /*!< DCMI Frame capture rate control FCRC[1:0] */
+#define DCMI_CR_FCRC_0                      (0x1UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000100 */
+#define DCMI_CR_FCRC_1                      (0x2UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000200 */
+#define DCMI_CR_EDM_Pos                     (10U)
+#define DCMI_CR_EDM_Msk                     (0x3UL << DCMI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define DCMI_CR_EDM                         DCMI_CR_EDM_Msk                         /*!< DCMI Extended data mode EDM[1:0] */
+#define DCMI_CR_EDM_0                       (0x1UL << DCMI_CR_EDM_Pos)              /*!< 0x00000400 */
+#define DCMI_CR_EDM_1                       (0x2UL << DCMI_CR_EDM_Pos)              /*!< 0x00000800 */
+#define DCMI_CR_ENABLE_Pos                  (14U)
+#define DCMI_CR_ENABLE_Msk                  (0x1UL << DCMI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define DCMI_CR_ENABLE                      DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos                     (16U)
+#define DCMI_CR_BSM_Msk                     (0x3UL << DCMI_CR_BSM_Pos)              /*!< 0x00030000 */
+#define DCMI_CR_BSM                         DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0                       (0x1UL << DCMI_CR_BSM_Pos)              /*!< 0x00010000 */
+#define DCMI_CR_BSM_1                       (0x2UL << DCMI_CR_BSM_Pos)              /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos                    (18U)
+#define DCMI_CR_OEBS_Msk                    (0x1UL << DCMI_CR_OEBS_Pos)             /*!< 0x00040000 */
+#define DCMI_CR_OEBS                        DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos                     (19U)
+#define DCMI_CR_LSM_Msk                     (0x1UL << DCMI_CR_LSM_Pos)              /*!< 0x00080000 */
+#define DCMI_CR_LSM                         DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos                    (20U)
+#define DCMI_CR_OELS_Msk                    (0x1UL << DCMI_CR_OELS_Pos)             /*!< 0x00100000 */
+#define DCMI_CR_OELS                        DCMI_CR_OELS_Msk
+#define DCMI_CR_PSDM_Pos                    (31U)
+#define DCMI_CR_PSDM_Msk                    (0x0UL << DCMI_CR_PSDM_Pos)             /*!< 0x00000000 */
+#define DCMI_CR_PSDM                        DCMI_CR_PSDM_Msk                        /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos                   (0U)
+#define DCMI_SR_HSYNC_Msk                   (0x1UL << DCMI_SR_HSYNC_Pos)            /*!< 0x00000001 */
+#define DCMI_SR_HSYNC                       DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos                   (1U)
+#define DCMI_SR_VSYNC_Msk                   (0x1UL << DCMI_SR_VSYNC_Pos)            /*!< 0x00000002 */
+#define DCMI_SR_VSYNC                       DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos                     (2U)
+#define DCMI_SR_FNE_Msk                     (0x1UL << DCMI_SR_FNE_Pos)              /*!< 0x00000004 */
+#define DCMI_SR_FNE                         DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos              (0U)
+#define DCMI_RIS_FRAME_RIS_Msk              (0x1UL << DCMI_RIS_FRAME_RIS_Pos)       /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS                  DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos                (1U)
+#define DCMI_RIS_OVR_RIS_Msk                (0x1UL << DCMI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS                    DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos                (2U)
+#define DCMI_RIS_ERR_RIS_Msk                (0x1UL << DCMI_RIS_ERR_RIS_Pos)         /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS                    DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos              (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk              (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)       /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos               (4U)
+#define DCMI_RIS_LINE_RIS_Msk               (0x1UL << DCMI_RIS_LINE_RIS_Pos)        /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS                   DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos               (0U)
+#define DCMI_IER_FRAME_IE_Msk               (0x1UL << DCMI_IER_FRAME_IE_Pos)        /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE                   DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos                 (1U)
+#define DCMI_IER_OVR_IE_Msk                 (0x1UL << DCMI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE                     DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos                 (2U)
+#define DCMI_IER_ERR_IE_Msk                 (0x1UL << DCMI_IER_ERR_IE_Pos)          /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE                     DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos               (3U)
+#define DCMI_IER_VSYNC_IE_Msk               (0x1UL << DCMI_IER_VSYNC_IE_Pos)        /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE                   DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos                (4U)
+#define DCMI_IER_LINE_IE_Msk                (0x1UL << DCMI_IER_LINE_IE_Pos)         /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE                    DCMI_IER_LINE_IE_Msk
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos              (0U)
+#define DCMI_MIS_FRAME_MIS_Msk              (0x1UL << DCMI_MIS_FRAME_MIS_Pos)       /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS                  DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos                (1U)
+#define DCMI_MIS_OVR_MIS_Msk                (0x1UL << DCMI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS                    DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos                (2U)
+#define DCMI_MIS_ERR_MIS_Msk                (0x1UL << DCMI_MIS_ERR_MIS_Pos)         /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS                    DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos              (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk              (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)       /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos               (4U)
+#define DCMI_MIS_LINE_MIS_Msk               (0x1UL << DCMI_MIS_LINE_MIS_Pos)        /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS                   DCMI_MIS_LINE_MIS_Msk
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos              (0U)
+#define DCMI_ICR_FRAME_ISC_Msk              (0x1UL << DCMI_ICR_FRAME_ISC_Pos)       /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC                  DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos                (1U)
+#define DCMI_ICR_OVR_ISC_Msk                (0x1UL << DCMI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC                    DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos                (2U)
+#define DCMI_ICR_ERR_ISC_Msk                (0x1UL << DCMI_ICR_ERR_ISC_Pos)         /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC                    DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos              (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk              (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)       /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC                  DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos               (4U)
+#define DCMI_ICR_LINE_ISC_Msk               (0x1UL << DCMI_ICR_LINE_ISC_Pos)        /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC                   DCMI_ICR_LINE_ISC_Msk
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos                   (0U)
+#define DCMI_ESCR_FSC_Msk                   (0xFFUL << DCMI_ESCR_FSC_Pos)           /*!< 0x000000FF */
+#define DCMI_ESCR_FSC                       DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos                   (8U)
+#define DCMI_ESCR_LSC_Msk                   (0xFFUL << DCMI_ESCR_LSC_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC                       DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos                   (16U)
+#define DCMI_ESCR_LEC_Msk                   (0xFFUL << DCMI_ESCR_LEC_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC                       DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos                   (24U)
+#define DCMI_ESCR_FEC_Msk                   (0xFFUL << DCMI_ESCR_FEC_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC                       DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos                   (0U)
+#define DCMI_ESUR_FSU_Msk                   (0xFFUL << DCMI_ESUR_FSU_Pos)           /*!< 0x000000FF */
+#define DCMI_ESUR_FSU                       DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos                   (8U)
+#define DCMI_ESUR_LSU_Msk                   (0xFFUL << DCMI_ESUR_LSU_Pos)           /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU                       DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos                   (16U)
+#define DCMI_ESUR_LEU_Msk                   (0xFFUL << DCMI_ESUR_LEU_Pos)           /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU                       DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos                   (24U)
+#define DCMI_ESUR_FEU_Msk                   (0xFFUL << DCMI_ESUR_FEU_Pos)           /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU                       DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos             (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk             (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)   /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT                 DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos                 (16U)
+#define DCMI_CWSTRT_VST_Msk                 (0x1FFFUL << DCMI_CWSTRT_VST_Pos)       /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST                     DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos              (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk              (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)    /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT                  DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos               (16U)
+#define DCMI_CWSIZE_VLINE_Msk               (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)     /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE                   DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos                   (0U)
+#define DCMI_DR_BYTE0_Msk                   (0xFFUL << DCMI_DR_BYTE0_Pos)           /*!< 0x000000FF */
+#define DCMI_DR_BYTE0                       DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos                   (8U)
+#define DCMI_DR_BYTE1_Msk                   (0xFFUL << DCMI_DR_BYTE1_Pos)           /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1                       DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos                   (16U)
+#define DCMI_DR_BYTE2_Msk                   (0xFFUL << DCMI_DR_BYTE2_Pos)           /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2                       DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos                   (24U)
+#define DCMI_DR_BYTE3_Msk                   (0xFFUL << DCMI_DR_BYTE3_Pos)           /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3                       DCMI_DR_BYTE3_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   DCMIPP                                   */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for DCMIPP_IPGR1 register  *****************/
+#define DCMIPP_IPGR1_MEMORYPAGE_Pos         (0U)
+#define DCMIPP_IPGR1_MEMORYPAGE_Msk         (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos)           /*!< 0x00000007 */
+#define DCMIPP_IPGR1_MEMORYPAGE             DCMIPP_IPGR1_MEMORYPAGE_Msk                     /*!< Memory page size, as power of 2 of 64-byte units: */
+#define DCMIPP_IPGR1_QOS_MODE_Pos           (24U)
+#define DCMIPP_IPGR1_QOS_MODE_Msk           (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_IPGR1_QOS_MODE               DCMIPP_IPGR1_QOS_MODE_Msk                       /*!< Quality of service */
+
+/*****************  Bit definition for DCMIPP_IPGR2 register  *****************/
+#define DCMIPP_IPGR2_PSTART_Pos             (0U)
+#define DCMIPP_IPGR2_PSTART_Msk             (0x1UL << DCMIPP_IPGR2_PSTART_Pos)               /*!< 0x00000001 */
+#define DCMIPP_IPGR2_PSTART                 DCMIPP_IPGR2_PSTART_Msk                         /*!< Request to lock the IP-Plug, to allow reconfiguration */
+
+/*****************  Bit definition for DCMIPP_IPGR3 register  *****************/
+#define DCMIPP_IPGR3_IDLE_Pos               (0U)
+#define DCMIPP_IPGR3_IDLE_Msk               (0x1UL << DCMIPP_IPGR3_IDLE_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_IPGR3_IDLE                   DCMIPP_IPGR3_IDLE_Msk                           /*!< Status of IP-Plug */
+
+/*****************  Bit definition for DCMIPP_IPGR8 register  *****************/
+#define DCMIPP_IPGR8_DID_Pos                (0U)
+#define DCMIPP_IPGR8_DID_Msk                (0x3FUL << DCMIPP_IPGR8_DID_Pos)                 /*!< 0x0000003F */
+#define DCMIPP_IPGR8_DID                    DCMIPP_IPGR8_DID_Msk                            /*!< Division identifier (0x14) */
+#define DCMIPP_IPGR8_REVID_Pos              (8U)
+#define DCMIPP_IPGR8_REVID_Msk              (0x1FUL << DCMIPP_IPGR8_REVID_Pos)               /*!< 0x00001F00 */
+#define DCMIPP_IPGR8_REVID                  DCMIPP_IPGR8_REVID_Msk                          /*!< Revision identifier (0x03) */
+#define DCMIPP_IPGR8_ARCHIID_Pos            (16U)
+#define DCMIPP_IPGR8_ARCHIID_Msk            (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos)             /*!< 0x001F0000 */
+#define DCMIPP_IPGR8_ARCHIID                DCMIPP_IPGR8_ARCHIID_Msk                        /*!< Architecture identifier (0x04) */
+#define DCMIPP_IPGR8_IPPID_Pos              (24U)
+#define DCMIPP_IPGR8_IPPID_Msk              (0xFFUL << DCMIPP_IPGR8_IPPID_Pos)               /*!< 0xFF000000 */
+#define DCMIPP_IPGR8_IPPID                  DCMIPP_IPGR8_IPPID_Msk                          /*!< IP identifier (0xAA) */
+
+/****************  Bit definition for DCMIPP_IPC1R1 register  *****************/
+#define DCMIPP_IPC1R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC1R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC1R1_TRAFFIC               DCMIPP_IPC1R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC1R1_OTR_Pos               (8U)
+#define DCMIPP_IPC1R1_OTR_Msk               (0xFUL << DCMIPP_IPC1R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC1R1_OTR                   DCMIPP_IPC1R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC1R2 register  *****************/
+#define DCMIPP_IPC1R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC1R2_WLRU_Msk              (0xFUL << DCMIPP_IPC1R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC1R2_WLRU                  DCMIPP_IPC1R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC1R3 register  *****************/
+#define DCMIPP_IPC1R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC1R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC1R3_DPREGSTART            DCMIPP_IPC1R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC1R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC1R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC1R3_DPREGEND              DCMIPP_IPC1R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC2R1 register  *****************/
+#define DCMIPP_IPC2R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC2R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC2R1_TRAFFIC               DCMIPP_IPC2R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC2R1_OTR_Pos               (8U)
+#define DCMIPP_IPC2R1_OTR_Msk               (0xFUL << DCMIPP_IPC2R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC2R1_OTR                   DCMIPP_IPC2R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC2R2 register  *****************/
+#define DCMIPP_IPC2R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC2R2_WLRU_Msk              (0xFUL << DCMIPP_IPC2R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC2R2_WLRU                  DCMIPP_IPC2R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC2R3 register  *****************/
+#define DCMIPP_IPC2R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC2R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC2R3_DPREGSTART            DCMIPP_IPC2R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC2R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC2R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC2R3_DPREGEND              DCMIPP_IPC2R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC3R1 register  *****************/
+#define DCMIPP_IPC3R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC3R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC3R1_TRAFFIC               DCMIPP_IPC3R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC3R1_OTR_Pos               (8U)
+#define DCMIPP_IPC3R1_OTR_Msk               (0xFUL << DCMIPP_IPC3R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC3R1_OTR                   DCMIPP_IPC3R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC3R2 register  *****************/
+#define DCMIPP_IPC3R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC3R2_WLRU_Msk              (0xFUL << DCMIPP_IPC3R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC3R2_WLRU                  DCMIPP_IPC3R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC3R3 register  *****************/
+#define DCMIPP_IPC3R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC3R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC3R3_DPREGSTART            DCMIPP_IPC3R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC3R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC3R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC3R3_DPREGEND              DCMIPP_IPC3R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC4R1 register  *****************/
+#define DCMIPP_IPC4R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC4R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC4R1_TRAFFIC               DCMIPP_IPC4R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC4R1_OTR_Pos               (8U)
+#define DCMIPP_IPC4R1_OTR_Msk               (0xFUL << DCMIPP_IPC4R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC4R1_OTR                   DCMIPP_IPC4R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC4R2 register  *****************/
+#define DCMIPP_IPC4R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC4R2_WLRU_Msk              (0xFUL << DCMIPP_IPC4R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC4R2_WLRU                  DCMIPP_IPC4R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC4R3 register  *****************/
+#define DCMIPP_IPC4R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC4R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC4R3_DPREGSTART            DCMIPP_IPC4R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC4R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC4R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC4R3_DPREGEND              DCMIPP_IPC4R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/****************  Bit definition for DCMIPP_IPC5R1 register  *****************/
+#define DCMIPP_IPC5R1_TRAFFIC_Pos           (0U)
+#define DCMIPP_IPC5R1_TRAFFIC_Msk           (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos)             /*!< 0x00000007 */
+#define DCMIPP_IPC5R1_TRAFFIC               DCMIPP_IPC5R1_TRAFFIC_Msk                       /*!< Burst size as power of 2 of 8 bytes units */
+#define DCMIPP_IPC5R1_OTR_Pos               (8U)
+#define DCMIPP_IPC5R1_OTR_Msk               (0xFUL << DCMIPP_IPC5R1_OTR_Pos)                 /*!< 0x00000F00 */
+#define DCMIPP_IPC5R1_OTR                   DCMIPP_IPC5R1_OTR_Msk                           /*!< max outstanding transactions: */
+
+/****************  Bit definition for DCMIPP_IPC5R2 register  *****************/
+#define DCMIPP_IPC5R2_WLRU_Pos              (16U)
+#define DCMIPP_IPC5R2_WLRU_Msk              (0xFUL << DCMIPP_IPC5R2_WLRU_Pos)                /*!< 0x000F0000 */
+#define DCMIPP_IPC5R2_WLRU                  DCMIPP_IPC5R2_WLRU_Msk                          /*!< Ratio for WLRU[3:0] arbitration: */
+
+/****************  Bit definition for DCMIPP_IPC5R3 register  *****************/
+#define DCMIPP_IPC5R3_DPREGSTART_Pos        (0U)
+#define DCMIPP_IPC5R3_DPREGSTART_Msk        (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos)        /*!< 0x000003FF */
+#define DCMIPP_IPC5R3_DPREGSTART            DCMIPP_IPC5R3_DPREGSTART_Msk                    /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
+#define DCMIPP_IPC5R3_DPREGEND_Pos          (16U)
+#define DCMIPP_IPC5R3_DPREGEND_Msk          (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos)          /*!< 0x03FF0000 */
+#define DCMIPP_IPC5R3_DPREGEND              DCMIPP_IPC5R3_DPREGEND_Msk                      /*!< End word (AXI width = 64 bits) of the FIFO of this client */
+
+/***************  Bit definition for DCMIPP_PRHWCFGR register  ****************/
+
+/*****************  Bit definition for DCMIPP_PRCR register  ******************/
+#define DCMIPP_PRCR_ESS_Pos                 (4U)
+#define DCMIPP_PRCR_ESS_Msk                 (0x1UL << DCMIPP_PRCR_ESS_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_PRCR_ESS                     DCMIPP_PRCR_ESS_Msk                             /*!< Embedded synchronization select */
+#define DCMIPP_PRCR_PCKPOL_Pos              (5U)
+#define DCMIPP_PRCR_PCKPOL_Msk              (0x1UL << DCMIPP_PRCR_PCKPOL_Pos)                /*!< 0x00000020 */
+#define DCMIPP_PRCR_PCKPOL                  DCMIPP_PRCR_PCKPOL_Msk                          /*!< Pixel clock polarity */
+#define DCMIPP_PRCR_HSPOL_Pos               (6U)
+#define DCMIPP_PRCR_HSPOL_Msk               (0x1UL << DCMIPP_PRCR_HSPOL_Pos)                 /*!< 0x00000040 */
+#define DCMIPP_PRCR_HSPOL                   DCMIPP_PRCR_HSPOL_Msk                           /*!< Horizontal synchronization polarity */
+#define DCMIPP_PRCR_VSPOL_Pos               (7U)
+#define DCMIPP_PRCR_VSPOL_Msk               (0x1UL << DCMIPP_PRCR_VSPOL_Pos)                 /*!< 0x00000080 */
+#define DCMIPP_PRCR_VSPOL                   DCMIPP_PRCR_VSPOL_Msk                           /*!< Vertical synchronization polarity */
+#define DCMIPP_PRCR_EDM_Pos                 (10U)
+#define DCMIPP_PRCR_EDM_Msk                 (0x7UL << DCMIPP_PRCR_EDM_Pos)                   /*!< 0x00001C00 */
+#define DCMIPP_PRCR_EDM                     DCMIPP_PRCR_EDM_Msk                             /*!< Extended data mode */
+#define DCMIPP_PRCR_ENABLE_Pos              (14U)
+#define DCMIPP_PRCR_ENABLE_Msk              (0x1UL << DCMIPP_PRCR_ENABLE_Pos)                /*!< 0x00004000 */
+#define DCMIPP_PRCR_ENABLE                  DCMIPP_PRCR_ENABLE_Msk                          /*!< Parallel interface enable */
+#define DCMIPP_PRCR_FORMAT_Pos              (16U)
+#define DCMIPP_PRCR_FORMAT_Msk              (0xFFUL << DCMIPP_PRCR_FORMAT_Pos)               /*!< 0x00FF0000 */
+#define DCMIPP_PRCR_FORMAT                  DCMIPP_PRCR_FORMAT_Msk                          /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */
+#define DCMIPP_PRCR_SWAPCYCLES_Pos          (25U)
+#define DCMIPP_PRCR_SWAPCYCLES_Msk          (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos)            /*!< 0x02000000 */
+#define DCMIPP_PRCR_SWAPCYCLES              DCMIPP_PRCR_SWAPCYCLES_Msk                      /*!< Swap data from cycle 0 vs */
+#define DCMIPP_PRCR_SWAPBITS_Pos            (26U)
+#define DCMIPP_PRCR_SWAPBITS_Msk            (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos)              /*!< 0x04000000 */
+#define DCMIPP_PRCR_SWAPBITS                DCMIPP_PRCR_SWAPBITS_Msk                        /*!< Swap LSB vs */
+
+/****************  Bit definition for DCMIPP_PRESCR register  *****************/
+#define DCMIPP_PRESCR_FSC_Pos               (0U)
+#define DCMIPP_PRESCR_FSC_Msk               (0xFFUL << DCMIPP_PRESCR_FSC_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESCR_FSC                   DCMIPP_PRESCR_FSC_Msk                           /*!< Frame start delimiter code */
+#define DCMIPP_PRESCR_LSC_Pos               (8U)
+#define DCMIPP_PRESCR_LSC_Msk               (0xFFUL << DCMIPP_PRESCR_LSC_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESCR_LSC                   DCMIPP_PRESCR_LSC_Msk                           /*!< Line start delimiter code */
+#define DCMIPP_PRESCR_LEC_Pos               (16U)
+#define DCMIPP_PRESCR_LEC_Msk               (0xFFUL << DCMIPP_PRESCR_LEC_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESCR_LEC                   DCMIPP_PRESCR_LEC_Msk                           /*!< Line end delimiter code */
+#define DCMIPP_PRESCR_FEC_Pos               (24U)
+#define DCMIPP_PRESCR_FEC_Msk               (0xFFUL << DCMIPP_PRESCR_FEC_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESCR_FEC                   DCMIPP_PRESCR_FEC_Msk                           /*!< Frame end delimiter code */
+
+/****************  Bit definition for DCMIPP_PRESUR register  *****************/
+#define DCMIPP_PRESUR_FSU_Pos               (0U)
+#define DCMIPP_PRESUR_FSU_Msk               (0xFFUL << DCMIPP_PRESUR_FSU_Pos)                /*!< 0x000000FF */
+#define DCMIPP_PRESUR_FSU                   DCMIPP_PRESUR_FSU_Msk                           /*!< Frame start delimiter unmask */
+#define DCMIPP_PRESUR_LSU_Pos               (8U)
+#define DCMIPP_PRESUR_LSU_Msk               (0xFFUL << DCMIPP_PRESUR_LSU_Pos)                /*!< 0x0000FF00 */
+#define DCMIPP_PRESUR_LSU                   DCMIPP_PRESUR_LSU_Msk                           /*!< Line start delimiter unmask */
+#define DCMIPP_PRESUR_LEU_Pos               (16U)
+#define DCMIPP_PRESUR_LEU_Msk               (0xFFUL << DCMIPP_PRESUR_LEU_Pos)                /*!< 0x00FF0000 */
+#define DCMIPP_PRESUR_LEU                   DCMIPP_PRESUR_LEU_Msk                           /*!< Line end delimiter unmask */
+#define DCMIPP_PRESUR_FEU_Pos               (24U)
+#define DCMIPP_PRESUR_FEU_Msk               (0xFFUL << DCMIPP_PRESUR_FEU_Pos)                /*!< 0xFF000000 */
+#define DCMIPP_PRESUR_FEU                   DCMIPP_PRESUR_FEU_Msk                           /*!< Frame end delimiter unmask */
+
+/*****************  Bit definition for DCMIPP_PRIER register  *****************/
+#define DCMIPP_PRIER_ERRIE_Pos              (6U)
+#define DCMIPP_PRIER_ERRIE_Msk              (0x1UL << DCMIPP_PRIER_ERRIE_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRIER_ERRIE                  DCMIPP_PRIER_ERRIE_Msk                          /*!< Synchronization error interrupt enable */
+
+/*****************  Bit definition for DCMIPP_PRSR register  ******************/
+#define DCMIPP_PRSR_ERRF_Pos                (6U)
+#define DCMIPP_PRSR_ERRF_Msk                (0x1UL << DCMIPP_PRSR_ERRF_Pos)                  /*!< 0x00000040 */
+#define DCMIPP_PRSR_ERRF                    DCMIPP_PRSR_ERRF_Msk                            /*!< Synchronization error raw interrupt status */
+#define DCMIPP_PRSR_HSYNC_Pos               (16U)
+#define DCMIPP_PRSR_HSYNC_Msk               (0x1UL << DCMIPP_PRSR_HSYNC_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_PRSR_HSYNC                   DCMIPP_PRSR_HSYNC_Msk                           /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */
+#define DCMIPP_PRSR_VSYNC_Pos               (17U)
+#define DCMIPP_PRSR_VSYNC_Msk               (0x1UL << DCMIPP_PRSR_VSYNC_Pos)                 /*!< 0x00020000 */
+#define DCMIPP_PRSR_VSYNC                   DCMIPP_PRSR_VSYNC_Msk                           /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */
+
+/*****************  Bit definition for DCMIPP_PRFCR register  *****************/
+#define DCMIPP_PRFCR_CERRF_Pos              (6U)
+#define DCMIPP_PRFCR_CERRF_Msk              (0x1UL << DCMIPP_PRFCR_CERRF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_PRFCR_CERRF                  DCMIPP_PRFCR_CERRF_Msk                          /*!< Synchronization error interrupt status clear */
+
+/*****************  Bit definition for DCMIPP_CMCR register  ******************/
+#define DCMIPP_CMCR_INSEL_Pos               (0U)
+#define DCMIPP_CMCR_INSEL_Msk               (0x1UL << DCMIPP_CMCR_INSEL_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_CMCR_INSEL                   DCMIPP_CMCR_INSEL_Msk                           /*!< input selection */
+#define DCMIPP_CMCR_PSFC_Pos                (1U)
+#define DCMIPP_CMCR_PSFC_Msk                (0x3UL << DCMIPP_CMCR_PSFC_Pos)                  /*!< 0x00000006 */
+#define DCMIPP_CMCR_PSFC                    DCMIPP_CMCR_PSFC_Msk                            /*!< Pipe selection for the frame counter */
+#define DCMIPP_CMCR_CFC_Pos                 (4U)
+#define DCMIPP_CMCR_CFC_Msk                 (0x1UL << DCMIPP_CMCR_CFC_Pos)                   /*!< 0x00000010 */
+#define DCMIPP_CMCR_CFC                     DCMIPP_CMCR_CFC_Msk                             /*!< Clear frame counter */
+#define DCMIPP_CMCR_SWAPRB_Pos              (7U)
+#define DCMIPP_CMCR_SWAPRB_Msk              (0x1UL << DCMIPP_CMCR_SWAPRB_Pos)                /*!< 0x00000080 */
+#define DCMIPP_CMCR_SWAPRB                  DCMIPP_CMCR_SWAPRB_Msk                          /*!< Swap R/U and B/V */
+
+/****************  Bit definition for DCMIPP_CMFRCR register  *****************/
+#define DCMIPP_CMFRCR_FRMCNT_Pos            (0U)
+#define DCMIPP_CMFRCR_FRMCNT_Msk            (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_CMFRCR_FRMCNT                DCMIPP_CMFRCR_FRMCNT_Msk                        /*!< Frame counter, read-only, loops around */
+
+/*****************  Bit definition for DCMIPP_CMIER register  *****************/
+#define DCMIPP_CMIER_ATXERRIE_Pos           (5U)
+#define DCMIPP_CMIER_ATXERRIE_Msk           (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMIER_ATXERRIE               DCMIPP_CMIER_ATXERRIE_Msk                       /*!< AXI Transfer error interrupt enable for IPPLUG */
+#define DCMIPP_CMIER_PRERRIE_Pos            (6U)
+#define DCMIPP_CMIER_PRERRIE_Msk            (0x1UL << DCMIPP_CMIER_PRERRIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMIER_PRERRIE                DCMIPP_CMIER_PRERRIE_Msk                        /*!< limit interrupt enable for the Parallel Interface */
+#define DCMIPP_CMIER_P0LINEIE_Pos           (8U)
+#define DCMIPP_CMIER_P0LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMIER_P0LINEIE               DCMIPP_CMIER_P0LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0FRAMEIE_Pos          (9U)
+#define DCMIPP_CMIER_P0FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMIER_P0FRAMEIE              DCMIPP_CMIER_P0FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0VSYNCIE_Pos          (10U)
+#define DCMIPP_CMIER_P0VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMIER_P0VSYNCIE              DCMIPP_CMIER_P0VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0LIMITIE_Pos          (14U)
+#define DCMIPP_CMIER_P0LIMITIE_Msk          (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMIER_P0LIMITIE              DCMIPP_CMIER_P0LIMITIE_Msk                      /*!< limit interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P0OVRIE_Pos            (15U)
+#define DCMIPP_CMIER_P0OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMIER_P0OVRIE                DCMIPP_CMIER_P0OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe0 */
+#define DCMIPP_CMIER_P1LINEIE_Pos           (16U)
+#define DCMIPP_CMIER_P1LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMIER_P1LINEIE               DCMIPP_CMIER_P1LINEIE_Msk                       /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */
+#define DCMIPP_CMIER_P1FRAMEIE_Pos          (17U)
+#define DCMIPP_CMIER_P1FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMIER_P1FRAMEIE              DCMIPP_CMIER_P1FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1VSYNCIE_Pos          (18U)
+#define DCMIPP_CMIER_P1VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMIER_P1VSYNCIE              DCMIPP_CMIER_P1VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P1OVRIE_Pos            (23U)
+#define DCMIPP_CMIER_P1OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMIER_P1OVRIE                DCMIPP_CMIER_P1OVRIE_Msk                        /*!< Overrun interrupt enable for the Pipe1 */
+#define DCMIPP_CMIER_P2LINEIE_Pos           (24U)
+#define DCMIPP_CMIER_P2LINEIE_Msk           (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMIER_P2LINEIE               DCMIPP_CMIER_P2LINEIE_Msk                       /*!< multi-Line Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2FRAMEIE_Pos          (25U)
+#define DCMIPP_CMIER_P2FRAMEIE_Msk          (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMIER_P2FRAMEIE              DCMIPP_CMIER_P2FRAMEIE_Msk                      /*!< Frame Capture complete interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2VSYNCIE_Pos          (26U)
+#define DCMIPP_CMIER_P2VSYNCIE_Msk          (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMIER_P2VSYNCIE              DCMIPP_CMIER_P2VSYNCIE_Msk                      /*!< Vertical sync interrupt enable for the Pipe2 */
+#define DCMIPP_CMIER_P2OVRIE_Pos            (31U)
+#define DCMIPP_CMIER_P2OVRIE_Msk            (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMIER_P2OVRIE                DCMIPP_CMIER_P2OVRIE_Msk                        /*!< Overrun interrupt status enable for the Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR1 register  *****************/
+#define DCMIPP_CMSR1_PRHSYNC_Pos            (0U)
+#define DCMIPP_CMSR1_PRHSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos)              /*!< 0x00000001 */
+#define DCMIPP_CMSR1_PRHSYNC                DCMIPP_CMSR1_PRHSYNC_Msk                        /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_PRVSYNC_Pos            (1U)
+#define DCMIPP_CMSR1_PRVSYNC_Msk            (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos)              /*!< 0x00000002 */
+#define DCMIPP_CMSR1_PRVSYNC                DCMIPP_CMSR1_PRVSYNC_Msk                        /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */
+#define DCMIPP_CMSR1_P0LSTLINE_Pos          (8U)
+#define DCMIPP_CMSR1_P0LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos)            /*!< 0x00000100 */
+#define DCMIPP_CMSR1_P0LSTLINE              DCMIPP_CMSR1_P0LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0LSTFRM_Pos           (9U)
+#define DCMIPP_CMSR1_P0LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR1_P0LSTFRM               DCMIPP_CMSR1_P0LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */
+#define DCMIPP_CMSR1_P0CPTACT_Pos           (15U)
+#define DCMIPP_CMSR1_P0CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos)             /*!< 0x00008000 */
+#define DCMIPP_CMSR1_P0CPTACT               DCMIPP_CMSR1_P0CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */
+#define DCMIPP_CMSR1_P1LSTLINE_Pos          (16U)
+#define DCMIPP_CMSR1_P1LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos)            /*!< 0x00010000 */
+#define DCMIPP_CMSR1_P1LSTLINE              DCMIPP_CMSR1_P1LSTLINE_Msk                      /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1LSTFRM_Pos           (17U)
+#define DCMIPP_CMSR1_P1LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR1_P1LSTFRM               DCMIPP_CMSR1_P1LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */
+#define DCMIPP_CMSR1_P1CPTACT_Pos           (23U)
+#define DCMIPP_CMSR1_P1CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos)             /*!< 0x00800000 */
+#define DCMIPP_CMSR1_P1CPTACT               DCMIPP_CMSR1_P1CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */
+#define DCMIPP_CMSR1_P2LSTLINE_Pos          (24U)
+#define DCMIPP_CMSR1_P2LSTLINE_Msk          (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos)            /*!< 0x01000000 */
+#define DCMIPP_CMSR1_P2LSTLINE              DCMIPP_CMSR1_P2LSTLINE_Msk                      /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2LSTFRM_Pos           (25U)
+#define DCMIPP_CMSR1_P2LSTFRM_Msk           (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR1_P2LSTFRM               DCMIPP_CMSR1_P2LSTFRM_Msk                       /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */
+#define DCMIPP_CMSR1_P2CPTACT_Pos           (31U)
+#define DCMIPP_CMSR1_P2CPTACT_Msk           (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos)             /*!< 0x80000000 */
+#define DCMIPP_CMSR1_P2CPTACT               DCMIPP_CMSR1_P2CPTACT_Msk                       /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMSR2 register  *****************/
+#define DCMIPP_CMSR2_ATXERRF_Pos            (5U)
+#define DCMIPP_CMSR2_ATXERRF_Msk            (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos)              /*!< 0x00000020 */
+#define DCMIPP_CMSR2_ATXERRF                DCMIPP_CMSR2_ATXERRF_Msk                        /*!< AXI transfer error interrupt status flag for the IPPLUG */
+#define DCMIPP_CMSR2_PRERRF_Pos             (6U)
+#define DCMIPP_CMSR2_PRERRF_Msk             (0x1UL << DCMIPP_CMSR2_PRERRF_Pos)               /*!< 0x00000040 */
+#define DCMIPP_CMSR2_PRERRF                 DCMIPP_CMSR2_PRERRF_Msk                         /*!< Synchronization error raw interrupt status for the parallel interface */
+#define DCMIPP_CMSR2_P0LINEF_Pos            (8U)
+#define DCMIPP_CMSR2_P0LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos)              /*!< 0x00000100 */
+#define DCMIPP_CMSR2_P0LINEF                DCMIPP_CMSR2_P0LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0FRAMEF_Pos           (9U)
+#define DCMIPP_CMSR2_P0FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos)             /*!< 0x00000200 */
+#define DCMIPP_CMSR2_P0FRAMEF               DCMIPP_CMSR2_P0FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0VSYNCF_Pos           (10U)
+#define DCMIPP_CMSR2_P0VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos)             /*!< 0x00000400 */
+#define DCMIPP_CMSR2_P0VSYNCF               DCMIPP_CMSR2_P0VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0LIMITF_Pos           (14U)
+#define DCMIPP_CMSR2_P0LIMITF_Msk           (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos)             /*!< 0x00004000 */
+#define DCMIPP_CMSR2_P0LIMITF               DCMIPP_CMSR2_P0LIMITF_Msk                       /*!< Limit raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P0OVRF_Pos             (15U)
+#define DCMIPP_CMSR2_P0OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos)               /*!< 0x00008000 */
+#define DCMIPP_CMSR2_P0OVRF                 DCMIPP_CMSR2_P0OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe0 */
+#define DCMIPP_CMSR2_P1LINEF_Pos            (16U)
+#define DCMIPP_CMSR2_P1LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos)              /*!< 0x00010000 */
+#define DCMIPP_CMSR2_P1LINEF                DCMIPP_CMSR2_P1LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1FRAMEF_Pos           (17U)
+#define DCMIPP_CMSR2_P1FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos)             /*!< 0x00020000 */
+#define DCMIPP_CMSR2_P1FRAMEF               DCMIPP_CMSR2_P1FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1VSYNCF_Pos           (18U)
+#define DCMIPP_CMSR2_P1VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos)             /*!< 0x00040000 */
+#define DCMIPP_CMSR2_P1VSYNCF               DCMIPP_CMSR2_P1VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P1OVRF_Pos             (23U)
+#define DCMIPP_CMSR2_P1OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos)               /*!< 0x00800000 */
+#define DCMIPP_CMSR2_P1OVRF                 DCMIPP_CMSR2_P1OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe1 */
+#define DCMIPP_CMSR2_P2LINEF_Pos            (24U)
+#define DCMIPP_CMSR2_P2LINEF_Msk            (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos)              /*!< 0x01000000 */
+#define DCMIPP_CMSR2_P2LINEF                DCMIPP_CMSR2_P2LINEF_Msk                        /*!< Multi-line capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2FRAMEF_Pos           (25U)
+#define DCMIPP_CMSR2_P2FRAMEF_Msk           (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos)             /*!< 0x02000000 */
+#define DCMIPP_CMSR2_P2FRAMEF               DCMIPP_CMSR2_P2FRAMEF_Msk                       /*!< Frame capture completed raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2VSYNCF_Pos           (26U)
+#define DCMIPP_CMSR2_P2VSYNCF_Msk           (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos)             /*!< 0x04000000 */
+#define DCMIPP_CMSR2_P2VSYNCF               DCMIPP_CMSR2_P2VSYNCF_Msk                       /*!< VSYNC raw interrupt status for Pipe2 */
+#define DCMIPP_CMSR2_P2OVRF_Pos             (31U)
+#define DCMIPP_CMSR2_P2OVRF_Msk             (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos)               /*!< 0x80000000 */
+#define DCMIPP_CMSR2_P2OVRF                 DCMIPP_CMSR2_P2OVRF_Msk                         /*!< Overrun raw interrupt status for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_CMFCR register  *****************/
+#define DCMIPP_CMFCR_CATXERRF_Pos           (5U)
+#define DCMIPP_CMFCR_CATXERRF_Msk           (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos)             /*!< 0x00000020 */
+#define DCMIPP_CMFCR_CATXERRF               DCMIPP_CMFCR_CATXERRF_Msk                       /*!< AXI Transfer error interrupt status clear */
+#define DCMIPP_CMFCR_CPRERRF_Pos            (6U)
+#define DCMIPP_CMFCR_CPRERRF_Msk            (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_CMFCR_CPRERRF                DCMIPP_CMFCR_CPRERRF_Msk                        /*!< Synchronization error interrupt status clear */
+#define DCMIPP_CMFCR_CP0LINEF_Pos           (8U)
+#define DCMIPP_CMFCR_CP0LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos)             /*!< 0x00000100 */
+#define DCMIPP_CMFCR_CP0LINEF               DCMIPP_CMFCR_CP0LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0FRAMEF_Pos          (9U)
+#define DCMIPP_CMFCR_CP0FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos)            /*!< 0x00000200 */
+#define DCMIPP_CMFCR_CP0FRAMEF              DCMIPP_CMFCR_CP0FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP0VSYNCF_Pos          (10U)
+#define DCMIPP_CMFCR_CP0VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos)            /*!< 0x00000400 */
+#define DCMIPP_CMFCR_CP0VSYNCF              DCMIPP_CMFCR_CP0VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP0LIMITF_Pos          (14U)
+#define DCMIPP_CMFCR_CP0LIMITF_Msk          (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos)            /*!< 0x00004000 */
+#define DCMIPP_CMFCR_CP0LIMITF              DCMIPP_CMFCR_CP0LIMITF_Msk                      /*!< limit interrupt status clear */
+#define DCMIPP_CMFCR_CP0OVRF_Pos            (15U)
+#define DCMIPP_CMFCR_CP0OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos)              /*!< 0x00008000 */
+#define DCMIPP_CMFCR_CP0OVRF                DCMIPP_CMFCR_CP0OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP1LINEF_Pos           (16U)
+#define DCMIPP_CMFCR_CP1LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos)             /*!< 0x00010000 */
+#define DCMIPP_CMFCR_CP1LINEF               DCMIPP_CMFCR_CP1LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1FRAMEF_Pos          (17U)
+#define DCMIPP_CMFCR_CP1FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos)            /*!< 0x00020000 */
+#define DCMIPP_CMFCR_CP1FRAMEF              DCMIPP_CMFCR_CP1FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP1VSYNCF_Pos          (18U)
+#define DCMIPP_CMFCR_CP1VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_CMFCR_CP1VSYNCF              DCMIPP_CMFCR_CP1VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP1OVRF_Pos            (23U)
+#define DCMIPP_CMFCR_CP1OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos)              /*!< 0x00800000 */
+#define DCMIPP_CMFCR_CP1OVRF                DCMIPP_CMFCR_CP1OVRF_Msk                        /*!< Overrun interrupt status clear */
+#define DCMIPP_CMFCR_CP2LINEF_Pos           (24U)
+#define DCMIPP_CMFCR_CP2LINEF_Msk           (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos)             /*!< 0x01000000 */
+#define DCMIPP_CMFCR_CP2LINEF               DCMIPP_CMFCR_CP2LINEF_Msk                       /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2FRAMEF_Pos          (25U)
+#define DCMIPP_CMFCR_CP2FRAMEF_Msk          (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos)            /*!< 0x02000000 */
+#define DCMIPP_CMFCR_CP2FRAMEF              DCMIPP_CMFCR_CP2FRAMEF_Msk                      /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_CMFCR_CP2VSYNCF_Pos          (26U)
+#define DCMIPP_CMFCR_CP2VSYNCF_Msk          (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos)            /*!< 0x04000000 */
+#define DCMIPP_CMFCR_CP2VSYNCF              DCMIPP_CMFCR_CP2VSYNCF_Msk                      /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_CMFCR_CP2OVRF_Pos            (31U)
+#define DCMIPP_CMFCR_CP2OVRF_Msk            (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos)              /*!< 0x80000000 */
+#define DCMIPP_CMFCR_CP2OVRF                DCMIPP_CMFCR_CP2OVRF_Msk                        /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0FSCR register  *****************/
+#define DCMIPP_P0FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P0FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P0FSCR_DTIDA                 DCMIPP_P0FSCR_DTIDA_Msk                         /*!< Data type selection ID A */
+#define DCMIPP_P0FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P0FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P0FSCR_DTIDB                 DCMIPP_P0FSCR_DTIDB_Msk                         /*!< Data type selection ID B */
+#define DCMIPP_P0FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P0FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P0FSCR_DTMODE                DCMIPP_P0FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_VC_Pos                (19U)
+#define DCMIPP_P0FSCR_VC_Msk                (0x3UL << DCMIPP_P0FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P0FSCR_VC                    DCMIPP_P0FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P0FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P0FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P0FSCR_PIPEN                 DCMIPP_P0FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P0FCTCR register  ****************/
+#define DCMIPP_P0FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P0FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P0FCTCR_FRATE                DCMIPP_P0FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P0FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P0FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P0FCTCR_CPTMODE              DCMIPP_P0FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P0FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P0FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P0FCTCR_CPTREQ               DCMIPP_P0FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P0SCSTR register  ****************/
+#define DCMIPP_P0SCSTR_HSTART_Pos           (0U)
+#define DCMIPP_P0SCSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0SCSTR_HSTART               DCMIPP_P0SCSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0SCSTR_VSTART_Pos           (16U)
+#define DCMIPP_P0SCSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSTR_VSTART               DCMIPP_P0SCSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P0SCSZR register  ****************/
+#define DCMIPP_P0SCSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P0SCSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P0SCSZR_HSIZE                DCMIPP_P0SCSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0SCSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P0SCSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P0SCSZR_VSIZE                DCMIPP_P0SCSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0SCSZR_POSNEG_Pos           (30U)
+#define DCMIPP_P0SCSZR_POSNEG_Msk           (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P0SCSZR_POSNEG               DCMIPP_P0SCSZR_POSNEG_Msk                       /*!< This bit is set and cleared by software */
+#define DCMIPP_P0SCSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P0SCSZR_ENABLE_Msk           (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P0SCSZR_ENABLE               DCMIPP_P0SCSZR_ENABLE_Msk                       /*!< This bit is set and cleared by software */
+
+/***************  Bit definition for DCMIPP_P0DCCNTR register  ****************/
+#define DCMIPP_P0DCCNTR_CNT_Pos             (0U)
+#define DCMIPP_P0DCCNTR_CNT_Msk             (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos)         /*!< 0x03FFFFFF */
+#define DCMIPP_P0DCCNTR_CNT                 DCMIPP_P0DCCNTR_CNT_Msk                         /*!< Number of data dumped during the frame */
+
+/***************  Bit definition for DCMIPP_P0DCLMTR register  ****************/
+#define DCMIPP_P0DCLMTR_LIMIT_Pos           (0U)
+#define DCMIPP_P0DCLMTR_LIMIT_Msk           (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos)        /*!< 0x00FFFFFF */
+#define DCMIPP_P0DCLMTR_LIMIT               DCMIPP_P0DCLMTR_LIMIT_Msk                       /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */
+#define DCMIPP_P0DCLMTR_ENABLE_Pos          (31U)
+#define DCMIPP_P0DCLMTR_ENABLE_Msk          (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0DCLMTR_ENABLE              DCMIPP_P0DCLMTR_ENABLE_Msk                      /*!<  */
+
+/****************  Bit definition for DCMIPP_P0PPCR register  *****************/
+#define DCMIPP_P0PPCR_SWAPYUV_Pos           (0U)
+#define DCMIPP_P0PPCR_SWAPYUV_Msk           (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P0PPCR_SWAPYUV               DCMIPP_P0PPCR_SWAPYUV_Msk                       /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0PPCR_PAD_Pos               (5U)
+#define DCMIPP_P0PPCR_PAD_Msk               (0x1UL << DCMIPP_P0PPCR_PAD_Pos)                 /*!< 0x00000020 */
+#define DCMIPP_P0PPCR_PAD                   DCMIPP_P0PPCR_PAD_Msk                           /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0PPCR_HEADEREN_Pos          (6U)
+#define DCMIPP_P0PPCR_HEADEREN_Msk          (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos)            /*!< 0x00000040 */
+#define DCMIPP_P0PPCR_HEADEREN              DCMIPP_P0PPCR_HEADEREN_Msk                      /*!< CSI header dump enable */
+#define DCMIPP_P0PPCR_BSM_Pos               (7U)
+#define DCMIPP_P0PPCR_BSM_Msk               (0x3UL << DCMIPP_P0PPCR_BSM_Pos)                 /*!< 0x00000180 */
+#define DCMIPP_P0PPCR_BSM                   DCMIPP_P0PPCR_BSM_Msk                           /*!< Byte select mode */
+#define DCMIPP_P0PPCR_OEBS_Pos              (9U)
+#define DCMIPP_P0PPCR_OEBS_Msk              (0x1UL << DCMIPP_P0PPCR_OEBS_Pos)                /*!< 0x00000200 */
+#define DCMIPP_P0PPCR_OEBS                  DCMIPP_P0PPCR_OEBS_Msk                          /*!< Odd/even byte select (byte select start) */
+#define DCMIPP_P0PPCR_LSM_Pos               (10U)
+#define DCMIPP_P0PPCR_LSM_Msk               (0x1UL << DCMIPP_P0PPCR_LSM_Pos)                 /*!< 0x00000400 */
+#define DCMIPP_P0PPCR_LSM                   DCMIPP_P0PPCR_LSM_Msk                           /*!< Line select mode */
+#define DCMIPP_P0PPCR_OELS_Pos              (11U)
+#define DCMIPP_P0PPCR_OELS_Msk              (0x1UL << DCMIPP_P0PPCR_OELS_Pos)                /*!< 0x00000800 */
+#define DCMIPP_P0PPCR_OELS                  DCMIPP_P0PPCR_OELS_Msk                          /*!< Odd/even line select (line select start) */
+#define DCMIPP_P0PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P0PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P0PPCR_LINEMULT              DCMIPP_P0PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0PPCR_DBM_Pos               (16U)
+#define DCMIPP_P0PPCR_DBM_Msk               (0x1UL << DCMIPP_P0PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P0PPCR_DBM                   DCMIPP_P0PPCR_DBM_Msk                           /*!< Double buffer mode */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR1 register  ***************/
+#define DCMIPP_P0PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR1_M0A                DCMIPP_P0PPM0AR1_M0A_Msk                        /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P0PPM0AR2 register  ***************/
+#define DCMIPP_P0PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P0PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P0PPM0AR2_M0A                DCMIPP_P0PPM0AR2_M0A_Msk                        /*!< Memory0 address */
+
+/*****************  Bit definition for DCMIPP_P0IER register  *****************/
+#define DCMIPP_P0IER_LINEIE_Pos             (0U)
+#define DCMIPP_P0IER_LINEIE_Msk             (0x1UL << DCMIPP_P0IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0IER_LINEIE                 DCMIPP_P0IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P0IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P0IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0IER_FRAMEIE                DCMIPP_P0IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P0IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P0IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0IER_VSYNCIE                DCMIPP_P0IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P0IER_LIMITIE_Pos            (6U)
+#define DCMIPP_P0IER_LIMITIE_Msk            (0x1UL << DCMIPP_P0IER_LIMITIE_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0IER_LIMITIE                DCMIPP_P0IER_LIMITIE_Msk                        /*!< Limit interrupt enable */
+#define DCMIPP_P0IER_OVRIE_Pos              (7U)
+#define DCMIPP_P0IER_OVRIE_Msk              (0x1UL << DCMIPP_P0IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0IER_OVRIE                  DCMIPP_P0IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P0SR register  ******************/
+#define DCMIPP_P0SR_LINEF_Pos               (0U)
+#define DCMIPP_P0SR_LINEF_Msk               (0x1UL << DCMIPP_P0SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P0SR_LINEF                   DCMIPP_P0SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P0SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P0SR_FRAMEF_Msk              (0x1UL << DCMIPP_P0SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P0SR_FRAMEF                  DCMIPP_P0SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P0SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P0SR_VSYNCF_Msk              (0x1UL << DCMIPP_P0SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P0SR_VSYNCF                  DCMIPP_P0SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P0SR_LIMITF_Pos              (6U)
+#define DCMIPP_P0SR_LIMITF_Msk              (0x1UL << DCMIPP_P0SR_LIMITF_Pos)                /*!< 0x00000040 */
+#define DCMIPP_P0SR_LIMITF                  DCMIPP_P0SR_LIMITF_Msk                          /*!< Limit raw interrupt status */
+#define DCMIPP_P0SR_OVRF_Pos                (7U)
+#define DCMIPP_P0SR_OVRF_Msk                (0x1UL << DCMIPP_P0SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P0SR_OVRF                    DCMIPP_P0SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P0SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P0SR_LSTLINE_Msk             (0x1UL << DCMIPP_P0SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P0SR_LSTLINE                 DCMIPP_P0SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P0SR_LSTFRM_Msk              (0x1UL << DCMIPP_P0SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P0SR_LSTFRM                  DCMIPP_P0SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P0SR_CPTACT_Pos              (23U)
+#define DCMIPP_P0SR_CPTACT_Msk              (0x1UL << DCMIPP_P0SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P0SR_CPTACT                  DCMIPP_P0SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P0FCR register  *****************/
+#define DCMIPP_P0FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P0FCR_CLINEF_Msk             (0x1UL << DCMIPP_P0FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P0FCR_CLINEF                 DCMIPP_P0FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P0FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P0FCR_CFRAMEF                DCMIPP_P0FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P0FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P0FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P0FCR_CVSYNCF                DCMIPP_P0FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P0FCR_CLIMITF_Pos            (6U)
+#define DCMIPP_P0FCR_CLIMITF_Msk            (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos)              /*!< 0x00000040 */
+#define DCMIPP_P0FCR_CLIMITF                DCMIPP_P0FCR_CLIMITF_Msk                        /*!< limit interrupt status clear */
+#define DCMIPP_P0FCR_COVRF_Pos              (7U)
+#define DCMIPP_P0FCR_COVRF_Msk              (0x1UL << DCMIPP_P0FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P0FCR_COVRF                  DCMIPP_P0FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P0CFSCR register  ****************/
+#define DCMIPP_P0CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P0CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P0CFSCR_DTIDA                DCMIPP_P0CFSCR_DTIDA_Msk                        /*!< Current Data type selection ID A */
+#define DCMIPP_P0CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P0CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P0CFSCR_DTIDB                DCMIPP_P0CFSCR_DTIDB_Msk                        /*!< Current Data type selection ID B */
+#define DCMIPP_P0CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P0CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P0CFSCR_DTMODE               DCMIPP_P0CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P0CFSCR_VC_Pos               (19U)
+#define DCMIPP_P0CFSCR_VC_Msk               (0x3UL << DCMIPP_P0CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P0CFSCR_VC                   DCMIPP_P0CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P0CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P0CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P0CFSCR_PIPEN                DCMIPP_P0CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P0CFCTCR register  ****************/
+#define DCMIPP_P0CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P0CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P0CFCTCR_FRATE               DCMIPP_P0CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P0CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P0CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P0CFCTCR_CPTMODE             DCMIPP_P0CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P0CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P0CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P0CFCTCR_CPTREQ              DCMIPP_P0CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P0CSCSTR register  ****************/
+#define DCMIPP_P0CSCSTR_HSTART_Pos          (0U)
+#define DCMIPP_P0CSCSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSTR_HSTART              DCMIPP_P0CSCSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 words wide */
+#define DCMIPP_P0CSCSTR_VSTART_Pos          (16U)
+#define DCMIPP_P0CSCSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSTR_VSTART              DCMIPP_P0CSCSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P0CSCSZR register  ****************/
+#define DCMIPP_P0CSCSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P0CSCSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P0CSCSZR_HSIZE               DCMIPP_P0CSCSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */
+#define DCMIPP_P0CSCSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P0CSCSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P0CSCSZR_VSIZE               DCMIPP_P0CSCSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P0CSCSZR_POSNEG_Pos          (30U)
+#define DCMIPP_P0CSCSZR_POSNEG_Msk          (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos)            /*!< 0x40000000 */
+#define DCMIPP_P0CSCSZR_POSNEG              DCMIPP_P0CSCSZR_POSNEG_Msk                      /*!< Current value of the POSNEG bit */
+#define DCMIPP_P0CSCSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P0CSCSZR_ENABLE_Msk          (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P0CSCSZR_ENABLE              DCMIPP_P0CSCSZR_ENABLE_Msk                      /*!< Current value of the ENABLE bit */
+
+/****************  Bit definition for DCMIPP_P0CPPCR register  ****************/
+#define DCMIPP_P0CPPCR_SWAPYUV_Pos          (0U)
+#define DCMIPP_P0CPPCR_SWAPYUV_Msk          (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P0CPPCR_SWAPYUV              DCMIPP_P0CPPCR_SWAPYUV_Msk                      /*!< SwapY vs UV bits, when the YUV mode is active */
+#define DCMIPP_P0CPPCR_PAD_Pos              (5U)
+#define DCMIPP_P0CPPCR_PAD_Msk              (0x1UL << DCMIPP_P0CPPCR_PAD_Pos)                /*!< 0x00000020 */
+#define DCMIPP_P0CPPCR_PAD                  DCMIPP_P0CPPCR_PAD_Msk                          /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
+#define DCMIPP_P0CPPCR_HEADEREN_Pos         (6U)
+#define DCMIPP_P0CPPCR_HEADEREN_Msk         (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos)           /*!< 0x00000040 */
+#define DCMIPP_P0CPPCR_HEADEREN             DCMIPP_P0CPPCR_HEADEREN_Msk                     /*!< Current CSI header dump enable */
+#define DCMIPP_P0CPPCR_BSM_Pos              (7U)
+#define DCMIPP_P0CPPCR_BSM_Msk              (0x3UL << DCMIPP_P0CPPCR_BSM_Pos)                /*!< 0x00000180 */
+#define DCMIPP_P0CPPCR_BSM                  DCMIPP_P0CPPCR_BSM_Msk                          /*!< Current Byte select mode */
+#define DCMIPP_P0CPPCR_OEBS_Pos             (9U)
+#define DCMIPP_P0CPPCR_OEBS_Msk             (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos)               /*!< 0x00000200 */
+#define DCMIPP_P0CPPCR_OEBS                 DCMIPP_P0CPPCR_OEBS_Msk                         /*!< Current odd/even byte select (Byte select start) */
+#define DCMIPP_P0CPPCR_LSM_Pos              (10U)
+#define DCMIPP_P0CPPCR_LSM_Msk              (0x1UL << DCMIPP_P0CPPCR_LSM_Pos)                /*!< 0x00000400 */
+#define DCMIPP_P0CPPCR_LSM                  DCMIPP_P0CPPCR_LSM_Msk                          /*!< Current Line select mode */
+#define DCMIPP_P0CPPCR_OELS_Pos             (11U)
+#define DCMIPP_P0CPPCR_OELS_Msk             (0x1UL << DCMIPP_P0CPPCR_OELS_Pos)               /*!< 0x00000800 */
+#define DCMIPP_P0CPPCR_OELS                 DCMIPP_P0CPPCR_OELS_Msk                         /*!< Current odd/even line select (Line select start) */
+#define DCMIPP_P0CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P0CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P0CPPCR_LINEMULT             DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Current amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P0CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P0CPPCR_DBM_Msk              (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P0CPPCR_DBM                  DCMIPP_P0CPPCR_LINEMULT_Msk                     /*!< Double buffer mode */
+
+/**************  Bit definition for DCMIPP_P0CPPM0AR1 register  ***************/
+#define DCMIPP_P0CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P0CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P0CPPM0AR1_M0A               DCMIPP_P0CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/****************  Bit definition for DCMIPP_P1FSCR register  *****************/
+#define DCMIPP_P1FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P1FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P1FSCR_DTIDA                 DCMIPP_P1FSCR_DTIDA_Msk                         /*!< Data type ID A */
+#define DCMIPP_P1FSCR_DTIDB_Pos             (8U)
+#define DCMIPP_P1FSCR_DTIDB_Msk             (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos)              /*!< 0x00003F00 */
+#define DCMIPP_P1FSCR_DTIDB                 DCMIPP_P1FSCR_DTIDB_Msk                         /*!< Data type ID B */
+#define DCMIPP_P1FSCR_DTMODE_Pos            (16U)
+#define DCMIPP_P1FSCR_DTMODE_Msk            (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos)              /*!< 0x00030000 */
+#define DCMIPP_P1FSCR_DTMODE                DCMIPP_P1FSCR_DTMODE_Msk                        /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_PIPEDIFF_Pos          (18U)
+#define DCMIPP_P1FSCR_PIPEDIFF_Msk          (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos)            /*!< 0x00040000 */
+#define DCMIPP_P1FSCR_PIPEDIFF              DCMIPP_P1FSCR_PIPEDIFF_Msk                      /*!< Differentiates Pipe2 vs */
+#define DCMIPP_P1FSCR_VC_Pos                (19U)
+#define DCMIPP_P1FSCR_VC_Msk                (0x3UL << DCMIPP_P1FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P1FSCR_VC                    DCMIPP_P1FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P1FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P1FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P1FSCR_FDTF                  DCMIPP_P1FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P1FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P1FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P1FSCR_FDTFEN                DCMIPP_P1FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P1FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P1FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P1FSCR_PIPEN                 DCMIPP_P1FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P1SRCR register  *****************/
+#define DCMIPP_P1SRCR_LASTLINE_Pos          (0U)
+#define DCMIPP_P1SRCR_LASTLINE_Msk          (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1SRCR_LASTLINE              DCMIPP_P1SRCR_LASTLINE_Msk                      /*!< Number of the last line to be kept when CROPEN = 1 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos      (12U)
+#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk      (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos)        /*!< 0x00007000 */
+#define DCMIPP_P1SRCR_FIRSTLINEDEL          DCMIPP_P1SRCR_FIRSTLINEDEL_Msk                  /*!< Number of lines to be deleted when CROPEN = 1 */
+#define DCMIPP_P1SRCR_CROPEN_Pos            (15U)
+#define DCMIPP_P1SRCR_CROPEN_Msk            (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos)              /*!< 0x00008000 */
+#define DCMIPP_P1SRCR_CROPEN                DCMIPP_P1SRCR_CROPEN_Msk                        /*!< Crop line enable */
+
+/****************  Bit definition for DCMIPP_P1BPRCR register  ****************/
+#define DCMIPP_P1BPRCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BPRCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BPRCR_ENABLE               DCMIPP_P1BPRCR_ENABLE_Msk                       /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */
+#define DCMIPP_P1BPRCR_STRENGTH_Pos         (1U)
+#define DCMIPP_P1BPRCR_STRENGTH_Msk         (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos)           /*!< 0x0000000E */
+#define DCMIPP_P1BPRCR_STRENGTH             DCMIPP_P1BPRCR_STRENGTH_Msk                     /*!< Strength (aggressivity) of the bad pixel detection: */
+
+/****************  Bit definition for DCMIPP_P1BPRSR register  ****************/
+#define DCMIPP_P1BPRSR_BADCNT_Pos           (0U)
+#define DCMIPP_P1BPRSR_BADCNT_Msk           (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1BPRSR_BADCNT               DCMIPP_P1BPRSR_BADCNT_Msk                       /*!< Amount of detected bad pixels */
+
+/****************  Bit definition for DCMIPP_P1DECR register  *****************/
+#define DCMIPP_P1DECR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DECR_ENABLE_Msk            (0x1UL << DCMIPP_P1DECR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DECR_ENABLE                DCMIPP_P1DECR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DECR_HDEC_Pos              (1U)
+#define DCMIPP_P1DECR_HDEC_Msk              (0x3UL << DCMIPP_P1DECR_HDEC_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DECR_HDEC                  DCMIPP_P1DECR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DECR_VDEC_Pos              (3U)
+#define DCMIPP_P1DECR_VDEC_Msk              (0x3UL << DCMIPP_P1DECR_VDEC_Pos)                /*!< 0x00000018 */
+#define DCMIPP_P1DECR_VDEC                  DCMIPP_P1DECR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1BLCCR register  ****************/
+#define DCMIPP_P1BLCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1BLCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1BLCCR_ENABLE               DCMIPP_P1BLCCR_ENABLE_Msk                       /*!< Black level calibration */
+#define DCMIPP_P1BLCCR_BLCB_Pos             (8U)
+#define DCMIPP_P1BLCCR_BLCB_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos)              /*!< 0x0000FF00 */
+#define DCMIPP_P1BLCCR_BLCB                 DCMIPP_P1BLCCR_BLCB_Msk                         /*!< Black level calibration - Blue */
+#define DCMIPP_P1BLCCR_BLCG_Pos             (16U)
+#define DCMIPP_P1BLCCR_BLCG_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos)              /*!< 0x00FF0000 */
+#define DCMIPP_P1BLCCR_BLCG                 DCMIPP_P1BLCCR_BLCG_Msk                         /*!< Black level calibration - Green */
+#define DCMIPP_P1BLCCR_BLCR_Pos             (24U)
+#define DCMIPP_P1BLCCR_BLCR_Msk             (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos)              /*!< 0xFF000000 */
+#define DCMIPP_P1BLCCR_BLCR                 DCMIPP_P1BLCCR_BLCR_Msk                         /*!< Black level calibration - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR1 register  ****************/
+#define DCMIPP_P1EXCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1EXCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1EXCR1_ENABLE               DCMIPP_P1EXCR1_ENABLE_Msk                       /*!< Exposure control (multiplication and shift) of all red, green and blue */
+#define DCMIPP_P1EXCR1_MULTR_Pos            (20U)
+#define DCMIPP_P1EXCR1_MULTR_Msk            (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR1_MULTR                DCMIPP_P1EXCR1_MULTR_Msk                        /*!< Exposure multiplier - Red */
+#define DCMIPP_P1EXCR1_SHFR_Pos             (28U)
+#define DCMIPP_P1EXCR1_SHFR_Msk             (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR1_SHFR                 DCMIPP_P1EXCR1_SHFR_Msk                         /*!< Exposure shift - Red */
+
+/****************  Bit definition for DCMIPP_P1EXCR2 register  ****************/
+#define DCMIPP_P1EXCR2_MULTB_Pos            (4U)
+#define DCMIPP_P1EXCR2_MULTB_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos)             /*!< 0x00000FF0 */
+#define DCMIPP_P1EXCR2_MULTB                DCMIPP_P1EXCR2_MULTB_Msk                        /*!< Exposure multiplier - Blue */
+#define DCMIPP_P1EXCR2_SHFB_Pos             (12U)
+#define DCMIPP_P1EXCR2_SHFB_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos)               /*!< 0x00007000 */
+#define DCMIPP_P1EXCR2_SHFB                 DCMIPP_P1EXCR2_SHFB_Msk                         /*!< Exposure shift - Blue */
+#define DCMIPP_P1EXCR2_MULTG_Pos            (20U)
+#define DCMIPP_P1EXCR2_MULTG_Msk            (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos)             /*!< 0x0FF00000 */
+#define DCMIPP_P1EXCR2_MULTG                DCMIPP_P1EXCR2_MULTG_Msk                        /*!< Exposure multiplier - Green */
+#define DCMIPP_P1EXCR2_SHFG_Pos             (28U)
+#define DCMIPP_P1EXCR2_SHFG_Msk             (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos)               /*!< 0x70000000 */
+#define DCMIPP_P1EXCR2_SHFG                 DCMIPP_P1EXCR2_SHFG_Msk                         /*!< Exposure shift - Green */
+
+/****************  Bit definition for DCMIPP_P1ST1CR register  ****************/
+#define DCMIPP_P1ST1CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST1CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST1CR_ENABLE               DCMIPP_P1ST1CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST1CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST1CR_BINS_Msk             (0x3UL << DCMIPP_P1ST1CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST1CR_BINS                 DCMIPP_P1ST1CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST1CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST1CR_SRC_Msk              (0x7UL << DCMIPP_P1ST1CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST1CR_SRC                  DCMIPP_P1ST1CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST1CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST1CR_MODE_Msk             (0x1UL << DCMIPP_P1ST1CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST1CR_MODE                 DCMIPP_P1ST1CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST2CR register  ****************/
+#define DCMIPP_P1ST2CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST2CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST2CR_ENABLE               DCMIPP_P1ST2CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST2CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST2CR_BINS_Msk             (0x3UL << DCMIPP_P1ST2CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST2CR_BINS                 DCMIPP_P1ST2CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST2CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST2CR_SRC_Msk              (0x7UL << DCMIPP_P1ST2CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST2CR_SRC                  DCMIPP_P1ST2CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST2CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST2CR_MODE_Msk             (0x1UL << DCMIPP_P1ST2CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST2CR_MODE                 DCMIPP_P1ST2CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1ST3CR register  ****************/
+#define DCMIPP_P1ST3CR_ENABLE_Pos           (0U)
+#define DCMIPP_P1ST3CR_ENABLE_Msk           (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1ST3CR_ENABLE               DCMIPP_P1ST3CR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1ST3CR_BINS_Pos             (2U)
+#define DCMIPP_P1ST3CR_BINS_Msk             (0x3UL << DCMIPP_P1ST3CR_BINS_Pos)               /*!< 0x0000000C */
+#define DCMIPP_P1ST3CR_BINS                 DCMIPP_P1ST3CR_BINS_Msk                         /*!< Bin definition */
+#define DCMIPP_P1ST3CR_SRC_Pos              (4U)
+#define DCMIPP_P1ST3CR_SRC_Msk              (0x7UL << DCMIPP_P1ST3CR_SRC_Pos)                /*!< 0x00000070 */
+#define DCMIPP_P1ST3CR_SRC                  DCMIPP_P1ST3CR_SRC_Msk                          /*!< Statistics source */
+#define DCMIPP_P1ST3CR_MODE_Pos             (7U)
+#define DCMIPP_P1ST3CR_MODE_Msk             (0x1UL << DCMIPP_P1ST3CR_MODE_Pos)               /*!< 0x00000080 */
+#define DCMIPP_P1ST3CR_MODE                 DCMIPP_P1ST3CR_MODE_Msk                         /*!< Statistics mode */
+
+/****************  Bit definition for DCMIPP_P1STSTR register  ****************/
+#define DCMIPP_P1STSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1STSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1STSTR_HSTART               DCMIPP_P1STSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1STSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSTR_VSTART               DCMIPP_P1STSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1STSZR register  ****************/
+#define DCMIPP_P1STSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1STSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1STSZR_HSIZE                DCMIPP_P1STSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1STSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1STSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1STSZR_VSIZE                DCMIPP_P1STSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1STSZR_CROPEN_Pos           (31U)
+#define DCMIPP_P1STSZR_CROPEN_Msk           (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1STSZR_CROPEN               DCMIPP_P1STSZR_CROPEN_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1ST1SR register  ****************/
+#define DCMIPP_P1ST1SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST1SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST1SR_ACCU                 DCMIPP_P1ST1SR_ACCU_Msk                         /*!< Accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST2SR register  ****************/
+#define DCMIPP_P1ST2SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST2SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST2SR_ACCU                 DCMIPP_P1ST2SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1ST3SR register  ****************/
+#define DCMIPP_P1ST3SR_ACCU_Pos             (0U)
+#define DCMIPP_P1ST3SR_ACCU_Msk             (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos)          /*!< 0x00FFFFFF */
+#define DCMIPP_P1ST3SR_ACCU                 DCMIPP_P1ST3SR_ACCU_Msk                         /*!< accumulation result, divided by 256 */
+
+/****************  Bit definition for DCMIPP_P1DMCR register  *****************/
+#define DCMIPP_P1DMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1DMCR_ENABLE                DCMIPP_P1DMCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1DMCR_TYPE_Pos              (1U)
+#define DCMIPP_P1DMCR_TYPE_Msk              (0x3UL << DCMIPP_P1DMCR_TYPE_Pos)                /*!< 0x00000006 */
+#define DCMIPP_P1DMCR_TYPE                  DCMIPP_P1DMCR_TYPE_Msk                          /*!< Raw Bayer type */
+#define DCMIPP_P1DMCR_PEAK_Pos              (16U)
+#define DCMIPP_P1DMCR_PEAK_Msk              (0x7UL << DCMIPP_P1DMCR_PEAK_Pos)                /*!< 0x00070000 */
+#define DCMIPP_P1DMCR_PEAK                  DCMIPP_P1DMCR_PEAK_Msk                          /*!< Strength of the peak detection */
+#define DCMIPP_P1DMCR_LINEV_Pos             (20U)
+#define DCMIPP_P1DMCR_LINEV_Msk             (0x7UL << DCMIPP_P1DMCR_LINEV_Pos)               /*!< 0x00700000 */
+#define DCMIPP_P1DMCR_LINEV                 DCMIPP_P1DMCR_LINEV_Msk                         /*!< Strength of the vertical line detection */
+#define DCMIPP_P1DMCR_LINEH_Pos             (24U)
+#define DCMIPP_P1DMCR_LINEH_Msk             (0x7UL << DCMIPP_P1DMCR_LINEH_Pos)               /*!< 0x07000000 */
+#define DCMIPP_P1DMCR_LINEH                 DCMIPP_P1DMCR_LINEH_Msk                         /*!< Strength of the horizontal line detection */
+#define DCMIPP_P1DMCR_EDGE_Pos              (28U)
+#define DCMIPP_P1DMCR_EDGE_Msk              (0x7UL << DCMIPP_P1DMCR_EDGE_Pos)                /*!< 0x70000000 */
+#define DCMIPP_P1DMCR_EDGE                  DCMIPP_P1DMCR_EDGE_Msk                          /*!< Strength of the edge detection */
+
+/****************  Bit definition for DCMIPP_P1CCCR register  *****************/
+#define DCMIPP_P1CCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1CCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P1CCCR_ENABLE                DCMIPP_P1CCCR_ENABLE_Msk                        /*!<  */
+#define DCMIPP_P1CCCR_TYPE_Pos              (1U)
+#define DCMIPP_P1CCCR_TYPE_Msk              (0x1UL << DCMIPP_P1CCCR_TYPE_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1CCCR_TYPE                  DCMIPP_P1CCCR_TYPE_Msk                          /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCR_CLAMP_Pos             (2U)
+#define DCMIPP_P1CCCR_CLAMP_Msk             (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos)               /*!< 0x00000004 */
+#define DCMIPP_P1CCCR_CLAMP                 DCMIPP_P1CCCR_CLAMP_Msk                         /*!< Clamp the output samples */
+
+/****************  Bit definition for DCMIPP_P1CCRR1 register  ****************/
+#define DCMIPP_P1CCRR1_RR_Pos               (0U)
+#define DCMIPP_P1CCRR1_RR_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR1_RR                   DCMIPP_P1CCRR1_RR_Msk                           /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCRR1_RG_Pos               (16U)
+#define DCMIPP_P1CCRR1_RG_Msk               (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCRR1_RG                   DCMIPP_P1CCRR1_RG_Msk                           /*!< Coefficient row 1 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCRR2 register  ****************/
+#define DCMIPP_P1CCRR2_RB_Pos               (0U)
+#define DCMIPP_P1CCRR2_RB_Msk               (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCRR2_RB                   DCMIPP_P1CCRR2_RB_Msk                           /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCRR2_RA_Pos               (16U)
+#define DCMIPP_P1CCRR2_RA_Msk               (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCRR2_RA                   DCMIPP_P1CCRR2_RA_Msk                           /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCGR1 register  ****************/
+#define DCMIPP_P1CCGR1_GR_Pos               (0U)
+#define DCMIPP_P1CCGR1_GR_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR1_GR                   DCMIPP_P1CCGR1_GR_Msk                           /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCGR1_GG_Pos               (16U)
+#define DCMIPP_P1CCGR1_GG_Msk               (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCGR1_GG                   DCMIPP_P1CCGR1_GG_Msk                           /*!< Coefficient row 2 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCGR2 register  ****************/
+#define DCMIPP_P1CCGR2_GB_Pos               (0U)
+#define DCMIPP_P1CCGR2_GB_Msk               (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCGR2_GB                   DCMIPP_P1CCGR2_GB_Msk                           /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCGR2_GA_Pos               (16U)
+#define DCMIPP_P1CCGR2_GA_Msk               (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCGR2_GA                   DCMIPP_P1CCGR2_GA_Msk                           /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CCBR1 register  ****************/
+#define DCMIPP_P1CCBR1_BR_Pos               (0U)
+#define DCMIPP_P1CCBR1_BR_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR1_BR                   DCMIPP_P1CCBR1_BR_Msk                           /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCBR1_BG_Pos               (16U)
+#define DCMIPP_P1CCBR1_BG_Msk               (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos)               /*!< 0x07FF0000 */
+#define DCMIPP_P1CCBR1_BG                   DCMIPP_P1CCBR1_BG_Msk                           /*!< Coefficient row 3 column 2 of the matrix */
+
+/****************  Bit definition for DCMIPP_P1CCBR2 register  ****************/
+#define DCMIPP_P1CCBR2_BB_Pos               (0U)
+#define DCMIPP_P1CCBR2_BB_Msk               (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos)               /*!< 0x000007FF */
+#define DCMIPP_P1CCBR2_BB                   DCMIPP_P1CCBR2_BB_Msk                           /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCBR2_BA_Pos               (16U)
+#define DCMIPP_P1CCBR2_BA_Msk               (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos)               /*!< 0x03FF0000 */
+#define DCMIPP_P1CCBR2_BA                   DCMIPP_P1CCBR2_BA_Msk                           /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1CTCR1 register  ****************/
+#define DCMIPP_P1CTCR1_ENABLE_Pos           (0U)
+#define DCMIPP_P1CTCR1_ENABLE_Msk           (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CTCR1_ENABLE               DCMIPP_P1CTCR1_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1CTCR1_LUM0_Pos             (9U)
+#define DCMIPP_P1CTCR1_LUM0_Msk             (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR1_LUM0                 DCMIPP_P1CTCR1_LUM0_Msk                         /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR2 register  ****************/
+#define DCMIPP_P1CTCR2_LUM4_Pos             (1U)
+#define DCMIPP_P1CTCR2_LUM4_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR2_LUM4                 DCMIPP_P1CTCR2_LUM4_Msk                         /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM3_Pos             (9U)
+#define DCMIPP_P1CTCR2_LUM3_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR2_LUM3                 DCMIPP_P1CTCR2_LUM3_Msk                         /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM2_Pos             (17U)
+#define DCMIPP_P1CTCR2_LUM2_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR2_LUM2                 DCMIPP_P1CTCR2_LUM2_Msk                         /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR2_LUM1_Pos             (25U)
+#define DCMIPP_P1CTCR2_LUM1_Msk             (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR2_LUM1                 DCMIPP_P1CTCR2_LUM1_Msk                         /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1CTCR3 register  ****************/
+#define DCMIPP_P1CTCR3_LUM8_Pos             (1U)
+#define DCMIPP_P1CTCR3_LUM8_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos)              /*!< 0x0000007E */
+#define DCMIPP_P1CTCR3_LUM8                 DCMIPP_P1CTCR3_LUM8_Msk                         /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM7_Pos             (9U)
+#define DCMIPP_P1CTCR3_LUM7_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos)              /*!< 0x00007E00 */
+#define DCMIPP_P1CTCR3_LUM7                 DCMIPP_P1CTCR3_LUM7_Msk                         /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM6_Pos             (17U)
+#define DCMIPP_P1CTCR3_LUM6_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos)              /*!< 0x007E0000 */
+#define DCMIPP_P1CTCR3_LUM6                 DCMIPP_P1CTCR3_LUM6_Msk                         /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CTCR3_LUM5_Pos             (25U)
+#define DCMIPP_P1CTCR3_LUM5_Msk             (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos)              /*!< 0x7E000000 */
+#define DCMIPP_P1CTCR3_LUM5                 DCMIPP_P1CTCR3_LUM5_Msk                         /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/****************  Bit definition for DCMIPP_P1FCTCR register  ****************/
+#define DCMIPP_P1FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P1FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P1FCTCR_FRATE                DCMIPP_P1FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P1FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P1FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P1FCTCR_CPTMODE              DCMIPP_P1FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P1FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P1FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P1FCTCR_CPTREQ               DCMIPP_P1FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P1CRSTR register  ****************/
+#define DCMIPP_P1CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P1CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CRSTR_HSTART               DCMIPP_P1CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P1CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSTR_VSTART               DCMIPP_P1CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CRSZR register  ****************/
+#define DCMIPP_P1CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1CRSZR_HSIZE                DCMIPP_P1CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1CRSZR_VSIZE                DCMIPP_P1CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CRSZR_ENABLE               DCMIPP_P1CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P1DCCR register  *****************/
+#define DCMIPP_P1DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1DCCR_ENABLE                DCMIPP_P1DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P1DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P1DCCR_HDEC_Msk              (0x3UL << DCMIPP_P1DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1DCCR_HDEC                  DCMIPP_P1DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P1DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P1DCCR_VDEC_Msk              (0x3UL << DCMIPP_P1DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1DCCR_VDEC                  DCMIPP_P1DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1DSCR register  *****************/
+#define DCMIPP_P1DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P1DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P1DSCR_HDIV                  DCMIPP_P1DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P1DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1DSCR_VDIV                  DCMIPP_P1DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P1DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1DSCR_ENABLE                DCMIPP_P1DSCR_ENABLE_Msk                        /*!<  Downscaler Enable */
+
+/***************  Bit definition for DCMIPP_P1DSRTIOR register  ***************/
+#define DCMIPP_P1DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P1DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P1DSRTIOR_HRATIO             DCMIPP_P1DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P1DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P1DSRTIOR_VRATIO             DCMIPP_P1DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P1DSSZR register  ****************/
+#define DCMIPP_P1DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P1DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P1DSSZR_HSIZE                DCMIPP_P1DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P1DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P1DSSZR_VSIZE                DCMIPP_P1DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CMRICR register  ***************/
+#define DCMIPP_P1CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P1CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P1CMRICR_ROILSZ              DCMIPP_P1CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P1CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P1CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P1CMRICR_ROI1EN              DCMIPP_P1CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P1CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P1CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P1CMRICR_ROI2EN              DCMIPP_P1CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P1CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P1CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CMRICR_ROI3EN              DCMIPP_P1CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P1CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P1CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P1CMRICR_ROI4EN              DCMIPP_P1CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P1CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P1CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P1CMRICR_ROI5EN              DCMIPP_P1CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P1CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P1CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P1CMRICR_ROI6EN              DCMIPP_P1CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P1CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P1CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P1CMRICR_ROI7EN              DCMIPP_P1CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P1CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P1CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P1CMRICR_ROI8EN              DCMIPP_P1CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P1RIxCR1 register  ***************/
+#define DCMIPP_P1RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P1RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P1RIxCR1_HSTART              DCMIPP_P1RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P1RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P1RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P1RIxCR1_CLB                 DCMIPP_P1RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P1RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P1RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P1RIxCR1_CLG                 DCMIPP_P1RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P1RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P1RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P1RIxCR1_VSTART              DCMIPP_P1RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P1RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P1RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P1RIxCR1_CLR                 DCMIPP_P1RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P1RIxCR2 register  ***************/
+#define DCMIPP_P1RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P1RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P1RIxCR2_VSIZE               DCMIPP_P1RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P1RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P1RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P1RIxCR2_HSIZE               DCMIPP_P1RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P1GMCR register  *****************/
+#define DCMIPP_P1GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P1GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos)              /*!< 0x00000001   */
+#define DCMIPP_P1GMCR_ENABLE                DCMIPP_P1GMCR_ENABLE_Msk                        /*!<  Gamma  enable*/
+
+/****************  Bit definition for DCMIPP_P1YUVCR register  ****************/
+#define DCMIPP_P1YUVCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1YUVCR_ENABLE_Msk           (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1YUVCR_ENABLE               DCMIPP_P1YUVCR_ENABLE_Msk                       /*!<  */
+#define DCMIPP_P1YUVCR_TYPE_Pos             (1U)
+#define DCMIPP_P1YUVCR_TYPE_Msk             (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1YUVCR_TYPE                 DCMIPP_P1YUVCR_TYPE_Msk                         /*!< Output samples type used while CLAMP is activated */
+#define DCMIPP_P1YUVCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1YUVCR_CLAMP_Msk            (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1YUVCR_CLAMP                DCMIPP_P1YUVCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1YUVRR1 register  ****************/
+#define DCMIPP_P1YUVRR1_RR_Pos              (0U)
+#define DCMIPP_P1YUVRR1_RR_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR1_RR                  DCMIPP_P1YUVRR1_RR_Msk                          /*!< Coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1YUVRR1_RG_Pos              (16U)
+#define DCMIPP_P1YUVRR1_RG_Msk              (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVRR1_RG                  DCMIPP_P1YUVRR1_RG_Msk                          /*!< Coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVRR2 register  ****************/
+#define DCMIPP_P1YUVRR2_RB_Pos              (0U)
+#define DCMIPP_P1YUVRR2_RB_Msk              (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVRR2_RB                  DCMIPP_P1YUVRR2_RB_Msk                          /*!< Coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1YUVRR2_RA_Pos              (16U)
+#define DCMIPP_P1YUVRR2_RA_Msk              (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVRR2_RA                  DCMIPP_P1YUVRR2_RA_Msk                          /*!< Coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVGR1 register  ****************/
+#define DCMIPP_P1YUVGR1_GR_Pos              (0U)
+#define DCMIPP_P1YUVGR1_GR_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR1_GR                  DCMIPP_P1YUVGR1_GR_Msk                          /*!< Coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1YUVGR1_GG_Pos              (16U)
+#define DCMIPP_P1YUVGR1_GG_Msk              (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVGR1_GG                  DCMIPP_P1YUVGR1_GG_Msk                          /*!< Coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVGR2 register  ****************/
+#define DCMIPP_P1YUVGR2_GB_Pos              (0U)
+#define DCMIPP_P1YUVGR2_GB_Msk              (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVGR2_GB                  DCMIPP_P1YUVGR2_GB_Msk                          /*!< Coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1YUVGR2_GA_Pos              (16U)
+#define DCMIPP_P1YUVGR2_GA_Msk              (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVGR2_GA                  DCMIPP_P1YUVGR2_GA_Msk                          /*!< Coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1YUVBR1 register  ****************/
+#define DCMIPP_P1YUVBR1_BR_Pos              (0U)
+#define DCMIPP_P1YUVBR1_BR_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR1_BR                  DCMIPP_P1YUVBR1_BR_Msk                          /*!< Coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1YUVBR1_BG_Pos              (16U)
+#define DCMIPP_P1YUVBR1_BG_Msk              (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1YUVBR1_BG                  DCMIPP_P1YUVBR1_BG_Msk                          /*!< Coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1YUVBR2 register  ****************/
+#define DCMIPP_P1YUVBR2_BB_Pos              (0U)
+#define DCMIPP_P1YUVBR2_BB_Msk              (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1YUVBR2_BB                  DCMIPP_P1YUVBR2_BB_Msk                          /*!< Coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1YUVBR2_BA_Pos              (16U)
+#define DCMIPP_P1YUVBR2_BA_Msk              (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1YUVBR2_BA                  DCMIPP_P1YUVBR2_BA_Msk                          /*!< Coefficient row 3 of the added column (signed integer value) */
+
+/****************  Bit definition for DCMIPP_P1PPCR register  *****************/
+#define DCMIPP_P1PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P1PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P1PPCR_FORMAT                DCMIPP_P1PPCR_FORMAT_Msk                        /*!< Memory format */
+#define DCMIPP_P1PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P1PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P1PPCR_SWAPRB                DCMIPP_P1PPCR_SWAPRB_Msk                        /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P1PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P1PPCR_LINEMULT              DCMIPP_P1PPCR_LINEMULT_Msk                      /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P1PPCR_DBM_Pos               (16U)
+#define DCMIPP_P1PPCR_DBM_Msk               (0x1UL << DCMIPP_P1PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P1PPCR_DBM                   DCMIPP_P1PPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P1PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P1PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos)                /*!< 0x000E0000 */
+#define DCMIPP_P1PPCR_LMAWM                 DCMIPP_P1PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P1PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P1PPCR_LMAWE_Msk             (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos)                /*!< 0x00100000 */
+#define DCMIPP_P1PPCR_LMAWE                 DCMIPP_P1PPCR_LMAWE_Msk                           /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P1PPM0AR1 register  ***************/
+#define DCMIPP_P1PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR1_M0A                DCMIPP_P1PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM0AR2 register  ***************/
+#define DCMIPP_P1PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P1PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM0AR2_M0A                DCMIPP_P1PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1PPM0PR register  ****************/
+#define DCMIPP_P1PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM0PR_PITCH               DCMIPP_P1PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR1 register  ***************/
+#define DCMIPP_P1PPM1AR1_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR1_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR1_M1A                DCMIPP_P1PPM1AR1_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1AR2 register  ***************/
+#define DCMIPP_P1PPM1AR2_M1A_Pos            (0U)
+#define DCMIPP_P1PPM1AR2_M1A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM1AR2_M1A                DCMIPP_P1PPM1AR2_M1A_Msk                        /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1PPM1PR register  ****************/
+#define DCMIPP_P1PPM1PR_PITCH_Pos           (0U)
+#define DCMIPP_P1PPM1PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P1PPM1PR_PITCH               DCMIPP_P1PPM1PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P1STM1AR register  ****************/
+#define DCMIPP_P1STM1AR_M1A_Pos             (0U)
+#define DCMIPP_P1STM1AR_M1A_Msk             (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM1AR_M1A                 DCMIPP_P1STM1AR_M1A_Msk                         /*!< status Memory1 address register */
+
+/***************  Bit definition for DCMIPP_P1PPM2AR1 register  ***************/
+#define DCMIPP_P1PPM2AR1_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR1_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR1_M2A                DCMIPP_P1PPM2AR1_M2A_Msk                        /*!< Memory2 address register 1*/
+
+/***************  Bit definition for DCMIPP_P1PPM2AR2 register  ***************/
+#define DCMIPP_P1PPM2AR2_M2A_Pos            (0U)
+#define DCMIPP_P1PPM2AR2_M2A_Msk            (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1PPM2AR2_M2A                DCMIPP_P1PPM2AR2_M2A_Msk                        /*!< Memory2 address register 2 */
+
+/***************  Bit definition for DCMIPP_P1STM2AR register  ****************/
+#define DCMIPP_P1STM2AR_M2A_Pos             (0U)
+#define DCMIPP_P1STM2AR_M2A_Msk             (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P1STM2AR_M2A                 DCMIPP_P1STM2AR_M2A_Msk                         /*!< status Memory2 address register */
+
+/*****************  Bit definition for DCMIPP_P1IER register  *****************/
+#define DCMIPP_P1IER_LINEIE_Pos             (0U)
+#define DCMIPP_P1IER_LINEIE_Msk             (0x1UL << DCMIPP_P1IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1IER_LINEIE                 DCMIPP_P1IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P1IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P1IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1IER_FRAMEIE                DCMIPP_P1IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P1IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P1IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1IER_VSYNCIE                DCMIPP_P1IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P1IER_OVRIE_Pos              (7U)
+#define DCMIPP_P1IER_OVRIE_Msk              (0x1UL << DCMIPP_P1IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1IER_OVRIE                  DCMIPP_P1IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P1SR register  ******************/
+#define DCMIPP_P1SR_LINEF_Pos               (0U)
+#define DCMIPP_P1SR_LINEF_Msk               (0x1UL << DCMIPP_P1SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P1SR_LINEF                   DCMIPP_P1SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P1SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P1SR_FRAMEF_Msk              (0x1UL << DCMIPP_P1SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P1SR_FRAMEF                  DCMIPP_P1SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P1SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P1SR_VSYNCF_Msk              (0x1UL << DCMIPP_P1SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P1SR_VSYNCF                  DCMIPP_P1SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P1SR_OVRF_Pos                (7U)
+#define DCMIPP_P1SR_OVRF_Msk                (0x1UL << DCMIPP_P1SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P1SR_OVRF                    DCMIPP_P1SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P1SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P1SR_LSTLINE_Msk             (0x1UL << DCMIPP_P1SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P1SR_LSTLINE                 DCMIPP_P1SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P1SR_LSTFRM_Msk              (0x1UL << DCMIPP_P1SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P1SR_LSTFRM                  DCMIPP_P1SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P1SR_CPTACT_Pos              (23U)
+#define DCMIPP_P1SR_CPTACT_Msk              (0x1UL << DCMIPP_P1SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P1SR_CPTACT                  DCMIPP_P1SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P1FCR register  *****************/
+#define DCMIPP_P1FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P1FCR_CLINEF_Msk             (0x1UL << DCMIPP_P1FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P1FCR_CLINEF                 DCMIPP_P1FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P1FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P1FCR_CFRAMEF                DCMIPP_P1FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P1FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P1FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1FCR_CVSYNCF                DCMIPP_P1FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P1FCR_COVRF_Pos              (7U)
+#define DCMIPP_P1FCR_COVRF_Msk              (0x1UL << DCMIPP_P1FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P1FCR_COVRF                  DCMIPP_P1FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P1CFSCR register  ****************/
+#define DCMIPP_P1CFSCR_DTIDA_Pos            (0U)
+#define DCMIPP_P1CFSCR_DTIDA_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos)             /*!< 0x0000003F */
+#define DCMIPP_P1CFSCR_DTIDA                DCMIPP_P1CFSCR_DTIDA_Msk                        /*!< Current Data type ID A */
+#define DCMIPP_P1CFSCR_DTIDB_Pos            (8U)
+#define DCMIPP_P1CFSCR_DTIDB_Msk            (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos)             /*!< 0x00003F00 */
+#define DCMIPP_P1CFSCR_DTIDB                DCMIPP_P1CFSCR_DTIDB_Msk                        /*!< Current Data type ID B */
+#define DCMIPP_P1CFSCR_DTMODE_Pos           (16U)
+#define DCMIPP_P1CFSCR_DTMODE_Msk           (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos)             /*!< 0x00030000 */
+#define DCMIPP_P1CFSCR_DTMODE               DCMIPP_P1CFSCR_DTMODE_Msk                       /*!< Flow selection mode */
+#define DCMIPP_P1CFSCR_PIPEDIFF_Pos         (18U)
+#define DCMIPP_P1CFSCR_PIPEDIFF_Msk         (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P1CFSCR_PIPEDIFF             DCMIPP_P1CFSCR_PIPEDIFF_Msk                     /*!< Current differentiates Pipe2 vs */
+#define DCMIPP_P1CFSCR_VC_Pos               (19U)
+#define DCMIPP_P1CFSCR_VC_Msk               (0x3UL << DCMIPP_P1CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P1CFSCR_VC                   DCMIPP_P1CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P1CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P1CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P1CFSCR_FDTF                 DCMIPP_P1CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P1CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P1CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P1CFSCR_FDTFEN               DCMIPP_P1CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P1CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P1CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P1CFSCR_PIPEN                DCMIPP_P1CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P1CBPRCR register  ****************/
+#define DCMIPP_P1CBPRCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBPRCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBPRCR_ENABLE              DCMIPP_P1CBPRCR_ENABLE_Msk                      /*!< Current status of enable bit */
+#define DCMIPP_P1CBPRCR_STRENGTH_Pos        (1U)
+#define DCMIPP_P1CBPRCR_STRENGTH_Msk        (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos)          /*!< 0x0000000E */
+#define DCMIPP_P1CBPRCR_STRENGTH            DCMIPP_P1CBPRCR_STRENGTH_Msk                    /*!< Current strength (aggressivity) of the bad pixel detection: */
+
+/***************  Bit definition for DCMIPP_P1CBLCCR register  ****************/
+#define DCMIPP_P1CBLCCR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CBLCCR_ENABLE_Msk          (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CBLCCR_ENABLE              DCMIPP_P1CBLCCR_ENABLE_Msk                      /*!< For current black level calibration */
+#define DCMIPP_P1CBLCCR_BLCB_Pos            (8U)
+#define DCMIPP_P1CBLCCR_BLCB_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos)             /*!< 0x0000FF00 */
+#define DCMIPP_P1CBLCCR_BLCB                DCMIPP_P1CBLCCR_BLCB_Msk                        /*!< Current black level calibration - Blue */
+#define DCMIPP_P1CBLCCR_BLCG_Pos            (16U)
+#define DCMIPP_P1CBLCCR_BLCG_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos)             /*!< 0x00FF0000 */
+#define DCMIPP_P1CBLCCR_BLCG                DCMIPP_P1CBLCCR_BLCG_Msk                        /*!< Current black level calibration - Green */
+#define DCMIPP_P1CBLCCR_BLCR_Pos            (24U)
+#define DCMIPP_P1CBLCCR_BLCR_Msk            (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos)             /*!< 0xFF000000 */
+#define DCMIPP_P1CBLCCR_BLCR                DCMIPP_P1CBLCCR_BLCR_Msk                        /*!< Current black level calibration - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR1 register  ****************/
+#define DCMIPP_P1CEXCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CEXCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CEXCR1_ENABLE              DCMIPP_P1CEXCR1_ENABLE_Msk                      /*!< for exposure control (multiplication and shift) */
+#define DCMIPP_P1CEXCR1_MULTR_Pos           (20U)
+#define DCMIPP_P1CEXCR1_MULTR_Msk           (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR1_MULTR               DCMIPP_P1CEXCR1_MULTR_Msk                       /*!< Current exposure multiplier - Red */
+#define DCMIPP_P1CEXCR1_SHFR_Pos            (28U)
+#define DCMIPP_P1CEXCR1_SHFR_Msk            (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR1_SHFR                DCMIPP_P1CEXCR1_SHFR_Msk                        /*!< Current exposure shift - Red */
+
+/***************  Bit definition for DCMIPP_P1CEXCR2 register  ****************/
+#define DCMIPP_P1CEXCR2_MULTB_Pos           (4U)
+#define DCMIPP_P1CEXCR2_MULTB_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos)            /*!< 0x00000FF0 */
+#define DCMIPP_P1CEXCR2_MULTB               DCMIPP_P1CEXCR2_MULTB_Msk                       /*!< Current exposure multiplier - Blue */
+#define DCMIPP_P1CEXCR2_SHFB_Pos            (12U)
+#define DCMIPP_P1CEXCR2_SHFB_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos)              /*!< 0x00007000 */
+#define DCMIPP_P1CEXCR2_SHFB                DCMIPP_P1CEXCR2_SHFB_Msk                        /*!< Current exposure shift - Blue */
+#define DCMIPP_P1CEXCR2_MULTG_Pos           (20U)
+#define DCMIPP_P1CEXCR2_MULTG_Msk           (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos)            /*!< 0x0FF00000 */
+#define DCMIPP_P1CEXCR2_MULTG               DCMIPP_P1CEXCR2_MULTG_Msk                       /*!< Current exposure multiplier - Green */
+#define DCMIPP_P1CEXCR2_SHFG_Pos            (28U)
+#define DCMIPP_P1CEXCR2_SHFG_Msk            (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos)              /*!< 0x70000000 */
+#define DCMIPP_P1CEXCR2_SHFG                DCMIPP_P1CEXCR2_SHFG_Msk                        /*!< Current exposure shift - Green */
+
+/***************  Bit definition for DCMIPP_P1CST1CR register  ****************/
+#define DCMIPP_P1CST1CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST1CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST1CR_ENABLE              DCMIPP_P1CST1CR_ENABLE_Msk                      /*!< Current enable bit value */
+#define DCMIPP_P1CST1CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST1CR_BINS_Msk            (0x3UL << DCMIPP_P1CST1CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST1CR_BINS                DCMIPP_P1CST1CR_BINS_Msk                        /*!< Current bin definition */
+#define DCMIPP_P1CST1CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST1CR_SRC_Msk             (0x7UL << DCMIPP_P1CST1CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST1CR_SRC                 DCMIPP_P1CST1CR_SRC_Msk                         /*!< Current source of statistics */
+#define DCMIPP_P1CST1CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST1CR_MODE_Msk            (0x1UL << DCMIPP_P1CST1CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST1CR_MODE                DCMIPP_P1CST1CR_MODE_Msk                        /*!< Current statistics mode */
+#define DCMIPP_P1CST1CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST1CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST1CR_ACCU                DCMIPP_P1CST1CR_ACCU_Msk                        /*!< Current accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST2CR register  ****************/
+#define DCMIPP_P1CST2CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST2CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST2CR_ENABLE              DCMIPP_P1CST2CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST2CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST2CR_BINS_Msk            (0x3UL << DCMIPP_P1CST2CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST2CR_BINS                DCMIPP_P1CST2CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST2CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST2CR_SRC_Msk             (0x7UL << DCMIPP_P1CST2CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST2CR_SRC                 DCMIPP_P1CST2CR_SRC_Msk                         /*!< source of stat */
+#define DCMIPP_P1CST2CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST2CR_MODE_Msk            (0x1UL << DCMIPP_P1CST2CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST2CR_MODE                DCMIPP_P1CST2CR_MODE_Msk                        /*!< statistics mode */
+#define DCMIPP_P1CST2CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST2CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST2CR_ACCU                DCMIPP_P1CST2CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CST3CR register  ****************/
+#define DCMIPP_P1CST3CR_ENABLE_Pos          (0U)
+#define DCMIPP_P1CST3CR_ENABLE_Msk          (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CST3CR_ENABLE              DCMIPP_P1CST3CR_ENABLE_Msk                      /*!<  */
+#define DCMIPP_P1CST3CR_BINS_Pos            (2U)
+#define DCMIPP_P1CST3CR_BINS_Msk            (0x3UL << DCMIPP_P1CST3CR_BINS_Pos)              /*!< 0x0000000C */
+#define DCMIPP_P1CST3CR_BINS                DCMIPP_P1CST3CR_BINS_Msk                        /*!< Bin definition */
+#define DCMIPP_P1CST3CR_SRC_Pos             (4U)
+#define DCMIPP_P1CST3CR_SRC_Msk             (0x7UL << DCMIPP_P1CST3CR_SRC_Pos)               /*!< 0x00000070 */
+#define DCMIPP_P1CST3CR_SRC                 DCMIPP_P1CST3CR_SRC_Msk                         /*!< Statistics source */
+#define DCMIPP_P1CST3CR_MODE_Pos            (7U)
+#define DCMIPP_P1CST3CR_MODE_Msk            (0x1UL << DCMIPP_P1CST3CR_MODE_Pos)              /*!< 0x00000080 */
+#define DCMIPP_P1CST3CR_MODE                DCMIPP_P1CST3CR_MODE_Msk                        /*!< Statistics mode */
+#define DCMIPP_P1CST3CR_ACCU_Pos            (8U)
+#define DCMIPP_P1CST3CR_ACCU_Msk            (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos)         /*!< 0xFFFFFF00 */
+#define DCMIPP_P1CST3CR_ACCU                DCMIPP_P1CST3CR_ACCU_Msk                        /*!< Accumulation result, divided by 256 */
+
+/***************  Bit definition for DCMIPP_P1CSTSTR register  ****************/
+#define DCMIPP_P1CSTSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CSTSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSTR_HSTART              DCMIPP_P1CSTSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CSTSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSTR_VSTART              DCMIPP_P1CSTSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CSTSZR register  ****************/
+#define DCMIPP_P1CSTSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CSTSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CSTSZR_HSIZE               DCMIPP_P1CSTSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CSTSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CSTSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CSTSZR_VSIZE               DCMIPP_P1CSTSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CSTSZR_CROPEN_Pos          (31U)
+#define DCMIPP_P1CSTSZR_CROPEN_Msk          (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CSTSZR_CROPEN              DCMIPP_P1CSTSZR_CROPEN_Msk                      /*!< Current CROPEN bit value */
+
+/****************  Bit definition for DCMIPP_P1CCCCR register  ****************/
+#define DCMIPP_P1CCCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CCCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P1CCCCR_ENABLE               DCMIPP_P1CCCCR_ENABLE_Msk                       /*!< This bit indicates the current value applied */
+#define DCMIPP_P1CCCCR_TYPE_Pos             (1U)
+#define DCMIPP_P1CCCCR_TYPE_Msk             (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos)               /*!< 0x00000002 */
+#define DCMIPP_P1CCCCR_TYPE                 DCMIPP_P1CCCCR_TYPE_Msk                         /*!< output samples type used while CLAMP is activated */
+#define DCMIPP_P1CCCCR_CLAMP_Pos            (2U)
+#define DCMIPP_P1CCCCR_CLAMP_Msk            (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P1CCCCR_CLAMP                DCMIPP_P1CCCCR_CLAMP_Msk                        /*!< Clamp the output samples */
+
+/***************  Bit definition for DCMIPP_P1CCCRR1 register  ****************/
+#define DCMIPP_P1CCCRR1_RR_Pos              (0U)
+#define DCMIPP_P1CCCRR1_RR_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR1_RR                  DCMIPP_P1CCCRR1_RR_Msk                          /*!< Current coefficient row 1 column 1 of the matrix */
+#define DCMIPP_P1CCCRR1_RG_Pos              (16U)
+#define DCMIPP_P1CCCRR1_RG_Msk              (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCRR1_RG                  DCMIPP_P1CCCRR1_RG_Msk                          /*!< Current coefficient row 1 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCRR2 register  ****************/
+#define DCMIPP_P1CCCRR2_RB_Pos              (0U)
+#define DCMIPP_P1CCCRR2_RB_Msk              (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCRR2_RB                  DCMIPP_P1CCCRR2_RB_Msk                          /*!< Current coefficient row 1 column 3 of the matrix */
+#define DCMIPP_P1CCCRR2_RA_Pos              (16U)
+#define DCMIPP_P1CCCRR2_RA_Msk              (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCRR2_RA                  DCMIPP_P1CCCRR2_RA_Msk                          /*!< Current coefficient row 1 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCGR1 register  ****************/
+#define DCMIPP_P1CCCGR1_GR_Pos              (0U)
+#define DCMIPP_P1CCCGR1_GR_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR1_GR                  DCMIPP_P1CCCGR1_GR_Msk                          /*!< Current coefficient row 2 column 1 of the matrix */
+#define DCMIPP_P1CCCGR1_GG_Pos              (16U)
+#define DCMIPP_P1CCCGR1_GG_Msk              (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCGR1_GG                  DCMIPP_P1CCCGR1_GG_Msk                          /*!< Current coefficient row 2 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCGR2 register  ****************/
+#define DCMIPP_P1CCCGR2_GB_Pos              (0U)
+#define DCMIPP_P1CCCGR2_GB_Msk              (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCGR2_GB                  DCMIPP_P1CCCGR2_GB_Msk                          /*!< Current coefficient row 2 column 3 of the matrix */
+#define DCMIPP_P1CCCGR2_GA_Pos              (16U)
+#define DCMIPP_P1CCCGR2_GA_Msk              (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCGR2_GA                  DCMIPP_P1CCCGR2_GA_Msk                          /*!< Current coefficient row 2 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCCBR1 register  ****************/
+#define DCMIPP_P1CCCBR1_BR_Pos              (0U)
+#define DCMIPP_P1CCCBR1_BR_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR1_BR                  DCMIPP_P1CCCBR1_BR_Msk                          /*!< Current coefficient row 3 column 1 of the matrix */
+#define DCMIPP_P1CCCBR1_BG_Pos              (16U)
+#define DCMIPP_P1CCCBR1_BG_Msk              (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos)              /*!< 0x07FF0000 */
+#define DCMIPP_P1CCCBR1_BG                  DCMIPP_P1CCCBR1_BG_Msk                          /*!< Current coefficient row 3 column 2 of the matrix */
+
+/***************  Bit definition for DCMIPP_P1CCCBR2 register  ****************/
+#define DCMIPP_P1CCCBR2_BB_Pos              (0U)
+#define DCMIPP_P1CCCBR2_BB_Msk              (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos)              /*!< 0x000007FF */
+#define DCMIPP_P1CCCBR2_BB                  DCMIPP_P1CCCBR2_BB_Msk                          /*!< Current coefficient row 3 column 3 of the matrix */
+#define DCMIPP_P1CCCBR2_BA_Pos              (16U)
+#define DCMIPP_P1CCCBR2_BA_Msk              (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P1CCCBR2_BA                  DCMIPP_P1CCCBR2_BA_Msk                          /*!< Current coefficient row 3 of the added column (signed integer value) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR1 register  ****************/
+#define DCMIPP_P1CCTCR1_ENABLE_Pos          (0U)
+#define DCMIPP_P1CCTCR1_ENABLE_Msk          (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CCTCR1_ENABLE              DCMIPP_P1CCTCR1_ENABLE_Msk                      /*!< Current ENABLE bit value */
+#define DCMIPP_P1CCTCR1_LUM0_Pos            (9U)
+#define DCMIPP_P1CCTCR1_LUM0_Msk            (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR1_LUM0                DCMIPP_P1CCTCR1_LUM0_Msk                        /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR2 register  ****************/
+#define DCMIPP_P1CCTCR2_LUM4_Pos            (1U)
+#define DCMIPP_P1CCTCR2_LUM4_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR2_LUM4                DCMIPP_P1CCTCR2_LUM4_Msk                        /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM3_Pos            (9U)
+#define DCMIPP_P1CCTCR2_LUM3_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR2_LUM3                DCMIPP_P1CCTCR2_LUM3_Msk                        /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM2_Pos            (17U)
+#define DCMIPP_P1CCTCR2_LUM2_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR2_LUM2                DCMIPP_P1CCTCR2_LUM2_Msk                        /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR2_LUM1_Pos            (25U)
+#define DCMIPP_P1CCTCR2_LUM1_Msk            (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR2_LUM1                DCMIPP_P1CCTCR2_LUM1_Msk                        /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CCTCR3 register  ****************/
+#define DCMIPP_P1CCTCR3_LUM8_Pos            (1U)
+#define DCMIPP_P1CCTCR3_LUM8_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos)             /*!< 0x0000007E */
+#define DCMIPP_P1CCTCR3_LUM8                DCMIPP_P1CCTCR3_LUM8_Msk                        /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM7_Pos            (9U)
+#define DCMIPP_P1CCTCR3_LUM7_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos)             /*!< 0x00007E00 */
+#define DCMIPP_P1CCTCR3_LUM7                DCMIPP_P1CCTCR3_LUM7_Msk                        /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM6_Pos            (17U)
+#define DCMIPP_P1CCTCR3_LUM6_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos)             /*!< 0x007E0000 */
+#define DCMIPP_P1CCTCR3_LUM6                DCMIPP_P1CCTCR3_LUM6_Msk                        /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
+#define DCMIPP_P1CCTCR3_LUM5_Pos            (25U)
+#define DCMIPP_P1CCTCR3_LUM5_Msk            (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos)             /*!< 0x7E000000 */
+#define DCMIPP_P1CCTCR3_LUM5                DCMIPP_P1CCTCR3_LUM5_Msk                        /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
+
+/***************  Bit definition for DCMIPP_P1CFCTCR register  ****************/
+#define DCMIPP_P1CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P1CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P1CFCTCR_FRATE               DCMIPP_P1CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P1CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P1CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P1CFCTCR_CPTMODE             DCMIPP_P1CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P1CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P1CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P1CFCTCR_CPTREQ              DCMIPP_P1CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P1CCRSTR register  ****************/
+#define DCMIPP_P1CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P1CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSTR_HSTART              DCMIPP_P1CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P1CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSTR_VSTART              DCMIPP_P1CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P1CCRSZR register  ****************/
+#define DCMIPP_P1CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CCRSZR_HSIZE               DCMIPP_P1CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CCRSZR_VSIZE               DCMIPP_P1CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P1CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P1CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P1CCRSZR_ENABLE              DCMIPP_P1CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P1CDCCR register  *****************/
+#define DCMIPP_P1CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P1CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P1CDCCR_ENABLE               DCMIPP_P1CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P1CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P1CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P1CDCCR_HDEC                 DCMIPP_P1CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P1CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P1CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P1CDCCR_VDEC                 DCMIPP_P1CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P1CDSCR register  ****************/
+#define DCMIPP_P1CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P1CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P1CDSCR_HDIV                 DCMIPP_P1CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P1CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P1CDSCR_VDIV                 DCMIPP_P1CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P1CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P1CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P1CDSCR_ENABLE               DCMIPP_P1CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P1CDSRTIOR register  ***************/
+#define DCMIPP_P1CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P1CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P1CDSRTIOR_HRATIO            DCMIPP_P1CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P1CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P1CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P1CDSRTIOR_VRATIO            DCMIPP_P1CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P1CDSSZR register  ****************/
+#define DCMIPP_P1CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P1CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P1CDSSZR_HSIZE               DCMIPP_P1CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P1CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P1CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P1CDSSZR_VSIZE               DCMIPP_P1CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P1CPPCR register  ****************/
+#define DCMIPP_P1CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P1CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P1CPPCR_FORMAT               DCMIPP_P1CPPCR_FORMAT_Msk                       /*!< Memory format */
+#define DCMIPP_P1CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P1CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P1CPPCR_SWAPRB               DCMIPP_P1CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
+#define DCMIPP_P1CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P1CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P1CPPCR_LINEMULT             DCMIPP_P1CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+
+/**************  Bit definition for DCMIPP_P1CPPM0AR1 register  ***************/
+#define DCMIPP_P1CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P1CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM0AR1_M0A               DCMIPP_P1CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM0PR register  ***************/
+#define DCMIPP_P1CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM0PR_PITCH              DCMIPP_P1CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM1AR1 register  ***************/
+#define DCMIPP_P1CPPM1AR1_M1A_Pos           (0U)
+#define DCMIPP_P1CPPM1AR1_M1A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM1AR1_M1A               DCMIPP_P1CPPM1AR1_M1A_Msk                       /*!< Memory1 address */
+
+/***************  Bit definition for DCMIPP_P1CPPM1PR register  ***************/
+#define DCMIPP_P1CPPM1PR_PITCH_Pos          (0U)
+#define DCMIPP_P1CPPM1PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P1CPPM1PR_PITCH              DCMIPP_P1CPPM1PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/**************  Bit definition for DCMIPP_P1CPPM2AR1 register  ***************/
+#define DCMIPP_P1CPPM2AR1_M2A_Pos           (0U)
+#define DCMIPP_P1CPPM2AR1_M2A_Msk           (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P1CPPM2AR1_M2A               DCMIPP_P1CPPM2AR1_M2A_Msk                       /*!< Memory 2 address */
+
+/****************  Bit definition for DCMIPP_P2FSCR register  *****************/
+#define DCMIPP_P2FSCR_DTIDA_Pos             (0U)
+#define DCMIPP_P2FSCR_DTIDA_Msk             (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2FSCR_DTIDA                 DCMIPP_P2FSCR_DTIDA_Msk                         /*!< Data type ID */
+#define DCMIPP_P2FSCR_VC_Pos                (19U)
+#define DCMIPP_P2FSCR_VC_Msk                (0x3UL << DCMIPP_P2FSCR_VC_Pos)                  /*!< 0x00180000 */
+#define DCMIPP_P2FSCR_VC                    DCMIPP_P2FSCR_VC_Msk                            /*!< Flow selection mode */
+#define DCMIPP_P2FSCR_FDTF_Pos              (24U)
+#define DCMIPP_P2FSCR_FDTF_Msk              (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos)               /*!< 0x3F000000 */
+#define DCMIPP_P2FSCR_FDTF                  DCMIPP_P2FSCR_FDTF_Msk                          /*!< Force Data type format */
+#define DCMIPP_P2FSCR_FDTFEN_Pos            (30U)
+#define DCMIPP_P2FSCR_FDTFEN_Msk            (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos)              /*!< 0x40000000 */
+#define DCMIPP_P2FSCR_FDTFEN                DCMIPP_P2FSCR_FDTFEN_Msk                        /*!< Force Data type format enable */
+#define DCMIPP_P2FSCR_PIPEN_Pos             (31U)
+#define DCMIPP_P2FSCR_PIPEN_Msk             (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos)               /*!< 0x80000000 */
+#define DCMIPP_P2FSCR_PIPEN                 DCMIPP_P2FSCR_PIPEN_Msk                         /*!< Activation of PipeN */
+
+/****************  Bit definition for DCMIPP_P2FCTCR register  ****************/
+#define DCMIPP_P2FCTCR_FRATE_Pos            (0U)
+#define DCMIPP_P2FCTCR_FRATE_Msk            (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos)              /*!< 0x00000003 */
+#define DCMIPP_P2FCTCR_FRATE                DCMIPP_P2FCTCR_FRATE_Msk                        /*!< Frame capture rate control */
+#define DCMIPP_P2FCTCR_CPTMODE_Pos          (2U)
+#define DCMIPP_P2FCTCR_CPTMODE_Msk          (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos)            /*!< 0x00000004 */
+#define DCMIPP_P2FCTCR_CPTMODE              DCMIPP_P2FCTCR_CPTMODE_Msk                      /*!< Capture mode */
+#define DCMIPP_P2FCTCR_CPTREQ_Pos           (3U)
+#define DCMIPP_P2FCTCR_CPTREQ_Msk           (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos)             /*!< 0x00000008 */
+#define DCMIPP_P2FCTCR_CPTREQ               DCMIPP_P2FCTCR_CPTREQ_Msk                       /*!< Capture requested */
+
+/****************  Bit definition for DCMIPP_P2CRSTR register  ****************/
+#define DCMIPP_P2CRSTR_HSTART_Pos           (0U)
+#define DCMIPP_P2CRSTR_HSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CRSTR_HSTART               DCMIPP_P2CRSTR_HSTART_Msk                       /*!< Horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSTR_VSTART_Pos           (16U)
+#define DCMIPP_P2CRSTR_VSTART_Msk           (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSTR_VSTART               DCMIPP_P2CRSTR_VSTART_Msk                       /*!< Vertical start, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CRSZR register  ****************/
+#define DCMIPP_P2CRSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2CRSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2CRSZR_HSIZE                DCMIPP_P2CRSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CRSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2CRSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2CRSZR_VSIZE                DCMIPP_P2CRSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CRSZR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CRSZR_ENABLE_Msk           (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CRSZR_ENABLE               DCMIPP_P2CRSZR_ENABLE_Msk                       /*!<  */
+
+/****************  Bit definition for DCMIPP_P2DCCR register  *****************/
+#define DCMIPP_P2DCCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2DCCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos)             /*!< 0x00000001 */
+#define DCMIPP_P2DCCR_ENABLE                DCMIPP_P2DCCR_ENABLE_Msk                        /*!< Decimation enable */
+#define DCMIPP_P2DCCR_HDEC_Pos              (1U)
+#define DCMIPP_P2DCCR_HDEC_Msk              (0x3UL << DCMIPP_P2DCCR_HDEC_Pos)               /*!< 0x00000006 */
+#define DCMIPP_P2DCCR_HDEC                  DCMIPP_P2DCCR_HDEC_Msk                          /*!< Horizontal decimation ratio */
+#define DCMIPP_P2DCCR_VDEC_Pos              (3U)
+#define DCMIPP_P2DCCR_VDEC_Msk              (0x3UL << DCMIPP_P2DCCR_VDEC_Pos)               /*!< 0x00000018 */
+#define DCMIPP_P2DCCR_VDEC                  DCMIPP_P2DCCR_VDEC_Msk                          /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2DSCR register  *****************/
+#define DCMIPP_P2DSCR_HDIV_Pos              (0U)
+#define DCMIPP_P2DSCR_HDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos)              /*!< 0x000003FF */
+#define DCMIPP_P2DSCR_HDIV                  DCMIPP_P2DSCR_HDIV_Msk                          /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_VDIV_Pos              (16U)
+#define DCMIPP_P2DSCR_VDIV_Msk              (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos)              /*!< 0x03FF0000 */
+#define DCMIPP_P2DSCR_VDIV                  DCMIPP_P2DSCR_VDIV_Msk                          /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2DSCR_ENABLE_Pos            (31U)
+#define DCMIPP_P2DSCR_ENABLE_Msk            (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2DSCR_ENABLE                DCMIPP_P2DSCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2DSRTIOR register  ***************/
+#define DCMIPP_P2DSRTIOR_HRATIO_Pos         (0U)
+#define DCMIPP_P2DSRTIOR_HRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos)        /*!< 0x0000FFFF */
+#define DCMIPP_P2DSRTIOR_HRATIO             DCMIPP_P2DSRTIOR_HRATIO_Msk                     /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2DSRTIOR_VRATIO_Pos         (16U)
+#define DCMIPP_P2DSRTIOR_VRATIO_Msk         (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos)        /*!< 0xFFFF0000 */
+#define DCMIPP_P2DSRTIOR_VRATIO             DCMIPP_P2DSRTIOR_VRATIO_Msk                     /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/****************  Bit definition for DCMIPP_P2DSSZR register  ****************/
+#define DCMIPP_P2DSSZR_HSIZE_Pos            (0U)
+#define DCMIPP_P2DSSZR_HSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos)            /*!< 0x00000FFF */
+#define DCMIPP_P2DSSZR_HSIZE                DCMIPP_P2DSSZR_HSIZE_Msk                        /*!< Horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2DSSZR_VSIZE_Pos            (16U)
+#define DCMIPP_P2DSSZR_VSIZE_Msk            (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos)            /*!< 0x0FFF0000 */
+#define DCMIPP_P2DSSZR_VSIZE                DCMIPP_P2DSSZR_VSIZE_Msk                        /*!< Vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2GMCR register  *****************/
+#define DCMIPP_P2GMCR_ENABLE_Pos            (0U)
+#define DCMIPP_P2GMCR_ENABLE_Msk            (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos)              /*!< 0x00000001 */
+#define DCMIPP_P2GMCR_ENABLE                DCMIPP_P2GMCR_ENABLE_Msk                        /*!<  */
+
+/***************  Bit definition for DCMIPP_P2CMRICR register  ***************/
+#define DCMIPP_P2CMRICR_ROILSZ_Pos          (0U)
+#define DCMIPP_P2CMRICR_ROILSZ_Msk          (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos)           /*!< 0x00000003 */
+#define DCMIPP_P2CMRICR_ROILSZ              DCMIPP_P2CMRICR_ROILSZ_Msk                      /*!< Region of interest line size width */
+#define DCMIPP_P2CMRICR_ROI1EN_Pos          (16U)
+#define DCMIPP_P2CMRICR_ROI1EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos)           /*!< 0x00010000 */
+#define DCMIPP_P2CMRICR_ROI1EN              DCMIPP_P2CMRICR_ROI1EN_Msk                      /*!< Region Of Interest 1 Enable */
+#define DCMIPP_P2CMRICR_ROI2EN_Pos          (17U)
+#define DCMIPP_P2CMRICR_ROI2EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos)           /*!< 0x00020000 */
+#define DCMIPP_P2CMRICR_ROI2EN              DCMIPP_P2CMRICR_ROI2EN_Msk                      /*!< Region Of Interest 2 Enable */
+#define DCMIPP_P2CMRICR_ROI3EN_Pos          (18U)
+#define DCMIPP_P2CMRICR_ROI3EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos)           /*!< 0x00040000 */
+#define DCMIPP_P2CMRICR_ROI3EN              DCMIPP_P2CMRICR_ROI3EN_Msk                      /*!< Region Of Interest 3 Enable */
+#define DCMIPP_P2CMRICR_ROI4EN_Pos          (19U)
+#define DCMIPP_P2CMRICR_ROI4EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos)           /*!< 0x00080000 */
+#define DCMIPP_P2CMRICR_ROI4EN              DCMIPP_P2CMRICR_ROI4EN_Msk                      /*!< Region Of Interest 4 Enable */
+#define DCMIPP_P2CMRICR_ROI5EN_Pos          (20U)
+#define DCMIPP_P2CMRICR_ROI5EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos)           /*!< 0x00100000 */
+#define DCMIPP_P2CMRICR_ROI5EN              DCMIPP_P2CMRICR_ROI5EN_Msk                      /*!< Region Of Interest 5 Enable */
+#define DCMIPP_P2CMRICR_ROI6EN_Pos          (21U)
+#define DCMIPP_P2CMRICR_ROI6EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos)           /*!< 0x00200000 */
+#define DCMIPP_P2CMRICR_ROI6EN              DCMIPP_P2CMRICR_ROI6EN_Msk                      /*!< Region Of Interest 6 Enable */
+#define DCMIPP_P2CMRICR_ROI7EN_Pos          (22U)
+#define DCMIPP_P2CMRICR_ROI7EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos)           /*!< 0x00400000 */
+#define DCMIPP_P2CMRICR_ROI7EN              DCMIPP_P2CMRICR_ROI7EN_Msk                      /*!< Region Of Interest 7 Enable */
+#define DCMIPP_P2CMRICR_ROI8EN_Pos          (23U)
+#define DCMIPP_P2CMRICR_ROI8EN_Msk          (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos)           /*!< 0x00800000 */
+#define DCMIPP_P2CMRICR_ROI8EN              DCMIPP_P2CMRICR_ROI8EN_Msk                      /*!< Region Of Interest 8 Enable */
+
+/***************  Bit definition for DCMIPP_P2RIxCR1 register  ***************/
+#define DCMIPP_P2RIxCR1_HSTART_Pos          (0U)
+#define DCMIPP_P2RIxCR1_HSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos)        /*!< 0x00000FFF */
+#define DCMIPP_P2RIxCR1_HSTART              DCMIPP_P2RIxCR1_HSTART_Msk                     /*!< Horizontal start */
+#define DCMIPP_P2RIxCR1_CLB_Pos             (12U)
+#define DCMIPP_P2RIxCR1_CLB_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos)             /*!< 0x00003000 */
+#define DCMIPP_P2RIxCR1_CLB                 DCMIPP_P2RIxCR1_CLB_Msk                        /*!< Color line blue */
+#define DCMIPP_P2RIxCR1_CLG_Pos             (14U)
+#define DCMIPP_P2RIxCR1_CLG_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos)             /*!< 0x0000C000 */
+#define DCMIPP_P2RIxCR1_CLG                 DCMIPP_P2RIxCR1_CLG_Msk                        /*!< Color line green */
+#define DCMIPP_P2RIxCR1_VSTART_Pos          (16U)
+#define DCMIPP_P2RIxCR1_VSTART_Msk          (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos)        /*!< 0x0FFF0000 */
+#define DCMIPP_P2RIxCR1_VSTART              DCMIPP_P2RIxCR1_VSTART_Msk                     /*!< Vertical start */
+#define DCMIPP_P2RIxCR1_CLR_Pos             (28U)
+#define DCMIPP_P2RIxCR1_CLR_Msk             (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos)             /*!< 0x30000000 */
+#define DCMIPP_P2RIxCR1_CLR                 DCMIPP_P2RIxCR1_CLR_Msk                        /*!< Color line red */
+
+/***************  Bit definition for DCMIPP_P2RIxCR2 register  ***************/
+#define DCMIPP_P2RIxCR2_VSIZE_Pos           (0U)
+#define DCMIPP_P2RIxCR2_VSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos)        /*!<  0x00000FFF */
+#define DCMIPP_P2RIxCR2_VSIZE               DCMIPP_P2RIxCR2_VSIZE_Msk                     /*!< Vertical Size */
+#define DCMIPP_P2RIxCR2_HSIZE_Pos           (16U)
+#define DCMIPP_P2RIxCR2_HSIZE_Msk           (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos)        /*!<  0x07FF8000 */
+#define DCMIPP_P2RIxCR2_HSIZE               DCMIPP_P2RIxCR2_HSIZE_Msk                     /*!< Horizontal Size */
+
+/****************  Bit definition for DCMIPP_P2PPCR register  *****************/
+#define DCMIPP_P2PPCR_FORMAT_Pos            (0U)
+#define DCMIPP_P2PPCR_FORMAT_Msk            (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos)              /*!< 0x0000000F */
+#define DCMIPP_P2PPCR_FORMAT                DCMIPP_P2PPCR_FORMAT_Msk                         /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2PPCR_SWAPRB_Pos            (4U)
+#define DCMIPP_P2PPCR_SWAPRB_Msk            (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos)              /*!< 0x00000010 */
+#define DCMIPP_P2PPCR_SWAPRB                DCMIPP_P2PPCR_SWAPRB_Msk                         /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2PPCR_LINEMULT_Pos          (13U)
+#define DCMIPP_P2PPCR_LINEMULT_Msk          (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos)            /*!< 0x0000E000 */
+#define DCMIPP_P2PPCR_LINEMULT              DCMIPP_P2PPCR_LINEMULT_Msk                       /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2PPCR_DBM_Pos               (16U)
+#define DCMIPP_P2PPCR_DBM_Msk               (0x1UL << DCMIPP_P2PPCR_DBM_Pos)                 /*!< 0x00010000 */
+#define DCMIPP_P2PPCR_DBM                   DCMIPP_P2PPCR_DBM_Msk                            /*!< Double buffer mode */
+#define DCMIPP_P2PPCR_LMAWM_Pos             (17U)
+#define DCMIPP_P2PPCR_LMAWM_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos)               /*!< 0x000E0000 */
+#define DCMIPP_P2PPCR_LMAWM                 DCMIPP_P2PPCR_LMAWM_Msk                          /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2PPCR_LMAWE_Pos             (20U)
+#define DCMIPP_P2PPCR_LMAWE_Msk             (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos)               /*!< 0x00100000 */
+#define DCMIPP_P2PPCR_LMAWE                 DCMIPP_P2PPCR_LMAWE_Msk                          /*!< Line multi address wrapping enable */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR1 register  ***************/
+#define DCMIPP_P2PPM0AR1_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR1_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR1_M0A                DCMIPP_P2PPM0AR1_M0A_Msk                        /*!< Memory0 address register 1 */
+
+/***************  Bit definition for DCMIPP_P2PPM0AR2 register  ***************/
+#define DCMIPP_P2PPM0AR2_M0A_Pos            (0U)
+#define DCMIPP_P2PPM0AR2_M0A_Msk            (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos)       /*!< 0xFFFFFFFF */
+#define DCMIPP_P2PPM0AR2_M0A                DCMIPP_P2PPM0AR2_M0A_Msk                        /*!< Memory0 address register 2*/
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2PPM0PR_PITCH_Pos           (0U)
+#define DCMIPP_P2PPM0PR_PITCH_Msk           (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos)          /*!< 0x00007FFF */
+#define DCMIPP_P2PPM0PR_PITCH               DCMIPP_P2PPM0PR_PITCH_Msk                       /*!< Number of bytes between the address of two consecutive lines */
+
+/***************  Bit definition for DCMIPP_P2PPM0PR register  ****************/
+#define DCMIPP_P2STM0AR_Pos                 (0U)
+#define DCMIPP_P2STM0AR_Msk                 (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_P2STM0AR                     DCMIPP_P2STM0AR_Msk                             /*!< Pipe2 status Memory0 address register */
+
+/*****************  Bit definition for DCMIPP_P2IER register  *****************/
+#define DCMIPP_P2IER_LINEIE_Pos             (0U)
+#define DCMIPP_P2IER_LINEIE_Msk             (0x1UL << DCMIPP_P2IER_LINEIE_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2IER_LINEIE                 DCMIPP_P2IER_LINEIE_Msk                         /*!< Multi-line capture completed interrupt enable */
+#define DCMIPP_P2IER_FRAMEIE_Pos            (1U)
+#define DCMIPP_P2IER_FRAMEIE_Msk            (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2IER_FRAMEIE                DCMIPP_P2IER_FRAMEIE_Msk                        /*!< Frame capture completed interrupt enable */
+#define DCMIPP_P2IER_VSYNCIE_Pos            (2U)
+#define DCMIPP_P2IER_VSYNCIE_Msk            (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2IER_VSYNCIE                DCMIPP_P2IER_VSYNCIE_Msk                        /*!< VSYNC interrupt enable */
+#define DCMIPP_P2IER_OVRIE_Pos              (7U)
+#define DCMIPP_P2IER_OVRIE_Msk              (0x1UL << DCMIPP_P2IER_OVRIE_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2IER_OVRIE                  DCMIPP_P2IER_OVRIE_Msk                          /*!< Overrun interrupt enable */
+
+/*****************  Bit definition for DCMIPP_P2SR register  ******************/
+#define DCMIPP_P2SR_LINEF_Pos               (0U)
+#define DCMIPP_P2SR_LINEF_Msk               (0x1UL << DCMIPP_P2SR_LINEF_Pos)                 /*!< 0x00000001 */
+#define DCMIPP_P2SR_LINEF                   DCMIPP_P2SR_LINEF_Msk                           /*!< Multi-line capture completed raw interrupt status */
+#define DCMIPP_P2SR_FRAMEF_Pos              (1U)
+#define DCMIPP_P2SR_FRAMEF_Msk              (0x1UL << DCMIPP_P2SR_FRAMEF_Pos)                /*!< 0x00000002 */
+#define DCMIPP_P2SR_FRAMEF                  DCMIPP_P2SR_FRAMEF_Msk                          /*!< Frame capture completed raw interrupt status */
+#define DCMIPP_P2SR_VSYNCF_Pos              (2U)
+#define DCMIPP_P2SR_VSYNCF_Msk              (0x1UL << DCMIPP_P2SR_VSYNCF_Pos)                /*!< 0x00000004 */
+#define DCMIPP_P2SR_VSYNCF                  DCMIPP_P2SR_VSYNCF_Msk                          /*!< VSYNC raw interrupt status */
+#define DCMIPP_P2SR_OVRF_Pos                (7U)
+#define DCMIPP_P2SR_OVRF_Msk                (0x1UL << DCMIPP_P2SR_OVRF_Pos)                  /*!< 0x00000080 */
+#define DCMIPP_P2SR_OVRF                    DCMIPP_P2SR_OVRF_Msk                            /*!< Overrun raw interrupt status */
+#define DCMIPP_P2SR_LSTLINE_Pos             (16U)
+#define DCMIPP_P2SR_LSTLINE_Msk             (0x1UL << DCMIPP_P2SR_LSTLINE_Pos)               /*!< 0x00010000 */
+#define DCMIPP_P2SR_LSTLINE                 DCMIPP_P2SR_LSTLINE_Msk                         /*!< Last line LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_LSTFRM_Pos              (17U)
+#define DCMIPP_P2SR_LSTFRM_Msk              (0x1UL << DCMIPP_P2SR_LSTFRM_Pos)                /*!< 0x00020000 */
+#define DCMIPP_P2SR_LSTFRM                  DCMIPP_P2SR_LSTFRM_Msk                          /*!< Last frame LSB bit, sampled at frame capture complete event */
+#define DCMIPP_P2SR_CPTACT_Pos              (23U)
+#define DCMIPP_P2SR_CPTACT_Msk              (0x1UL << DCMIPP_P2SR_CPTACT_Pos)                /*!< 0x00800000 */
+#define DCMIPP_P2SR_CPTACT                  DCMIPP_P2SR_CPTACT_Msk                          /*!< Capture immediate status */
+
+/*****************  Bit definition for DCMIPP_P2FCR register  *****************/
+#define DCMIPP_P2FCR_CLINEF_Pos             (0U)
+#define DCMIPP_P2FCR_CLINEF_Msk             (0x1UL << DCMIPP_P2FCR_CLINEF_Pos)               /*!< 0x00000001 */
+#define DCMIPP_P2FCR_CLINEF                 DCMIPP_P2FCR_CLINEF_Msk                         /*!< Multi-line capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CFRAMEF_Pos            (1U)
+#define DCMIPP_P2FCR_CFRAMEF_Msk            (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos)              /*!< 0x00000002 */
+#define DCMIPP_P2FCR_CFRAMEF                DCMIPP_P2FCR_CFRAMEF_Msk                        /*!< Frame capture complete interrupt status clear */
+#define DCMIPP_P2FCR_CVSYNCF_Pos            (2U)
+#define DCMIPP_P2FCR_CVSYNCF_Msk            (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos)              /*!< 0x00000004 */
+#define DCMIPP_P2FCR_CVSYNCF                DCMIPP_P2FCR_CVSYNCF_Msk                        /*!< Vertical synchronization interrupt status clear */
+#define DCMIPP_P2FCR_COVRF_Pos              (7U)
+#define DCMIPP_P2FCR_COVRF_Msk              (0x1UL << DCMIPP_P2FCR_COVRF_Pos)                /*!< 0x00000080 */
+#define DCMIPP_P2FCR_COVRF                  DCMIPP_P2FCR_COVRF_Msk                          /*!< Overrun interrupt status clear */
+
+/****************  Bit definition for DCMIPP_P2CFSCR register  ****************/
+#define DCMIPP_P2CFSCR_DTID_Pos             (0U)
+#define DCMIPP_P2CFSCR_DTID_Msk             (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos)              /*!< 0x0000003F */
+#define DCMIPP_P2CFSCR_DTID                 DCMIPP_P2CFSCR_DTID_Msk                         /*!< Current Data type ID */
+#define DCMIPP_P2CFSCR_VC_Pos               (19U)
+#define DCMIPP_P2CFSCR_VC_Msk               (0x3UL << DCMIPP_P2CFSCR_VC_Pos)                 /*!< 0x00180000 */
+#define DCMIPP_P2CFSCR_VC                   DCMIPP_P2CFSCR_VC_Msk                           /*!< Current flow selection mode */
+#define DCMIPP_P2CFSCR_FDTF_Pos             (24U)
+#define DCMIPP_P2CFSCR_FDTF_Msk             (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos)              /*!< 0x3F000000 */
+#define DCMIPP_P2CFSCR_FDTF                 DCMIPP_P2CFSCR_FDTF_Msk                         /*!< Current force Data type format */
+#define DCMIPP_P2CFSCR_FDTFEN_Pos           (30U)
+#define DCMIPP_P2CFSCR_FDTFEN_Msk           (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos)             /*!< 0x40000000 */
+#define DCMIPP_P2CFSCR_FDTFEN               DCMIPP_P2CFSCR_FDTFEN_Msk                       /*!< Current force Data type format enable */
+#define DCMIPP_P2CFSCR_PIPEN_Pos            (31U)
+#define DCMIPP_P2CFSCR_PIPEN_Msk            (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos)              /*!< 0x80000000 */
+#define DCMIPP_P2CFSCR_PIPEN                DCMIPP_P2CFSCR_PIPEN_Msk                        /*!< Current activation of PipeN */
+
+/***************  Bit definition for DCMIPP_P2CFCTCR register  ****************/
+#define DCMIPP_P2CFCTCR_FRATE_Pos           (0U)
+#define DCMIPP_P2CFCTCR_FRATE_Msk           (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos)             /*!< 0x00000003 */
+#define DCMIPP_P2CFCTCR_FRATE               DCMIPP_P2CFCTCR_FRATE_Msk                       /*!< Frame capture rate control */
+#define DCMIPP_P2CFCTCR_CPTMODE_Pos         (2U)
+#define DCMIPP_P2CFCTCR_CPTMODE_Msk         (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos)           /*!< 0x00000004 */
+#define DCMIPP_P2CFCTCR_CPTMODE             DCMIPP_P2CFCTCR_CPTMODE_Msk                     /*!< Capture mode */
+#define DCMIPP_P2CFCTCR_CPTREQ_Pos          (3U)
+#define DCMIPP_P2CFCTCR_CPTREQ_Msk          (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos)            /*!< 0x00000008 */
+#define DCMIPP_P2CFCTCR_CPTREQ              DCMIPP_P2CFCTCR_CPTREQ_Msk                      /*!< Capture requested */
+
+/***************  Bit definition for DCMIPP_P2CCRSTR register  ****************/
+#define DCMIPP_P2CCRSTR_HSTART_Pos          (0U)
+#define DCMIPP_P2CCRSTR_HSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos)          /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSTR_HSTART              DCMIPP_P2CCRSTR_HSTART_Msk                      /*!< Current horizontal start, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSTR_VSTART_Pos          (16U)
+#define DCMIPP_P2CCRSTR_VSTART_Msk          (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos)          /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSTR_VSTART              DCMIPP_P2CCRSTR_VSTART_Msk                      /*!< Current vertical start, from 0 to 4094 pixels high */
+
+/***************  Bit definition for DCMIPP_P2CCRSZR register  ****************/
+#define DCMIPP_P2CCRSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CCRSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CCRSZR_HSIZE               DCMIPP_P2CCRSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CCRSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CCRSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CCRSZR_VSIZE               DCMIPP_P2CCRSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+#define DCMIPP_P2CCRSZR_ENABLE_Pos          (31U)
+#define DCMIPP_P2CCRSZR_ENABLE_Msk          (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos)            /*!< 0x80000000 */
+#define DCMIPP_P2CCRSZR_ENABLE              DCMIPP_P2CCRSZR_ENABLE_Msk                      /*!< Current ENABLE bit value */
+
+/****************  Bit definition for DCMIPP_P2CDCCR register  *****************/
+#define DCMIPP_P2CDCCR_ENABLE_Pos           (0U)
+#define DCMIPP_P2CDCCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos)            /*!< 0x00000001 */
+#define DCMIPP_P2CDCCR_ENABLE               DCMIPP_P2CDCCR_ENABLE_Msk                       /*!< Decimation enable */
+#define DCMIPP_P2CDCCR_HDEC_Pos             (1U)
+#define DCMIPP_P2CDCCR_HDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos)              /*!< 0x00000006 */
+#define DCMIPP_P2CDCCR_HDEC                 DCMIPP_P2CDCCR_HDEC_Msk                         /*!< Horizontal decimation ratio */
+#define DCMIPP_P2CDCCR_VDEC_Pos             (3U)
+#define DCMIPP_P2CDCCR_VDEC_Msk             (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos)              /*!< 0x00000018 */
+#define DCMIPP_P2CDCCR_VDEC                 DCMIPP_P2CDCCR_VDEC_Msk                         /*!< Vertical decimation ratio */
+
+/****************  Bit definition for DCMIPP_P2CDSCR register  ****************/
+#define DCMIPP_P2CDSCR_HDIV_Pos             (0U)
+#define DCMIPP_P2CDSCR_HDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos)             /*!< 0x000003FF */
+#define DCMIPP_P2CDSCR_HDIV                 DCMIPP_P2CDSCR_HDIV_Msk                         /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_VDIV_Pos             (16U)
+#define DCMIPP_P2CDSCR_VDIV_Msk             (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos)             /*!< 0x03FF0000 */
+#define DCMIPP_P2CDSCR_VDIV                 DCMIPP_P2CDSCR_VDIV_Msk                         /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
+#define DCMIPP_P2CDSCR_ENABLE_Pos           (31U)
+#define DCMIPP_P2CDSCR_ENABLE_Msk           (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos)             /*!< 0x80000000 */
+#define DCMIPP_P2CDSCR_ENABLE               DCMIPP_P2CDSCR_ENABLE_Msk                       /*!< Current value of the bit ENABLE */
+
+/**************  Bit definition for DCMIPP_P2CDSRTIOR register  ***************/
+#define DCMIPP_P2CDSRTIOR_HRATIO_Pos        (0U)
+#define DCMIPP_P2CDSRTIOR_HRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos)       /*!< 0x0000FFFF */
+#define DCMIPP_P2CDSRTIOR_HRATIO            DCMIPP_P2CDSRTIOR_HRATIO_Msk                    /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
+#define DCMIPP_P2CDSRTIOR_VRATIO_Pos        (16U)
+#define DCMIPP_P2CDSRTIOR_VRATIO_Msk        (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos)       /*!< 0xFFFF0000 */
+#define DCMIPP_P2CDSRTIOR_VRATIO            DCMIPP_P2CDSRTIOR_VRATIO_Msk                    /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
+
+/***************  Bit definition for DCMIPP_P2CDSSZR register  ****************/
+#define DCMIPP_P2CDSSZR_HSIZE_Pos           (0U)
+#define DCMIPP_P2CDSSZR_HSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos)           /*!< 0x00000FFF */
+#define DCMIPP_P2CDSSZR_HSIZE               DCMIPP_P2CDSSZR_HSIZE_Msk                       /*!< Current horizontal size, from 0 to 4094 pixels wide */
+#define DCMIPP_P2CDSSZR_VSIZE_Pos           (16U)
+#define DCMIPP_P2CDSSZR_VSIZE_Msk           (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos)           /*!< 0x0FFF0000 */
+#define DCMIPP_P2CDSSZR_VSIZE               DCMIPP_P2CDSSZR_VSIZE_Msk                       /*!< Current vertical size, from 0 to 4094 pixels high */
+
+/****************  Bit definition for DCMIPP_P2CPPCR register  ****************/
+#define DCMIPP_P2CPPCR_FORMAT_Pos           (0U)
+#define DCMIPP_P2CPPCR_FORMAT_Msk           (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos)             /*!< 0x0000000F */
+#define DCMIPP_P2CPPCR_FORMAT               DCMIPP_P2CPPCR_FORMAT_Msk                       /*!< Memory format (only coplanar formats are supported in Pipe2) */
+#define DCMIPP_P2CPPCR_SWAPRB_Pos           (4U)
+#define DCMIPP_P2CPPCR_SWAPRB_Msk           (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos)             /*!< 0x00000010 */
+#define DCMIPP_P2CPPCR_SWAPRB               DCMIPP_P2CPPCR_SWAPRB_Msk                       /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
+#define DCMIPP_P2CPPCR_LINEMULT_Pos         (13U)
+#define DCMIPP_P2CPPCR_LINEMULT_Msk         (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos)           /*!< 0x0000E000 */
+#define DCMIPP_P2CPPCR_LINEMULT             DCMIPP_P2CPPCR_LINEMULT_Msk                     /*!< Amount of capture completed lines for LINE Event and Interrupt */
+#define DCMIPP_P2CPPCR_DBM_Pos              (16U)
+#define DCMIPP_P2CPPCR_DBM_Msk              (0x1UL << DCMIPP_P2CPPCR_DBM_Pos)                /*!< 0x00010000 */
+#define DCMIPP_P2CPPCR_DBM                  DCMIPP_P2CPPCR_DBM_Msk                           /*!< Double buffer mode */
+#define DCMIPP_P2CPPCR_LMAWM_Pos            (17U)
+#define DCMIPP_P2CPPCR_LMAWM_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos)              /*!< 0x000E0000 */
+#define DCMIPP_P2CPPCR_LMAWM                DCMIPP_P2CPPCR_LMAWM_Msk                         /*!< Line multi address wrapping modulo */
+#define DCMIPP_P2CPPCR_LMAWE_Pos            (20U)
+#define DCMIPP_P2CPPCR_LMAWE_Msk            (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos)              /*!< 0x00100000 */
+#define DCMIPP_P2CPPCR_LMAWE                DCMIPP_P2CPPCR_LMAWE_Msk                         /*!< Line multi address wrapping enable */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR1 register  ***************/
+#define DCMIPP_P2CPPM0AR1_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR1_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR1_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address */
+
+/**************  Bit definition for DCMIPP_P2CPPM0AR2 register  ***************/
+#define DCMIPP_P2CPPM0AR2_M0A_Pos           (0U)
+#define DCMIPP_P2CPPM0AR2_M0A_Msk           (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos)      /*!< 0xFFFFFFFF */
+#define DCMIPP_P2CPPM0AR2_M0A               DCMIPP_P2CPPM0AR1_M0A_Msk                       /*!< Memory0 address Register 2 */
+
+/***************  Bit definition for DCMIPP_P2CPPM0PR register  ***************/
+#define DCMIPP_P2CPPM0PR_PITCH_Pos          (0U)
+#define DCMIPP_P2CPPM0PR_PITCH_Msk          (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos)         /*!< 0x00007FFF */
+#define DCMIPP_P2CPPM0PR_PITCH              DCMIPP_P2CPPM0PR_PITCH_Msk                      /*!< Number of bytes between the address of two consecutive lines */
+
+/****************  Bit definition for DCMIPP_HWCFGR2 register  ****************/
+#define DCMIPP_HWCFGR2_VPFT_Pos             (0U)
+#define DCMIPP_HWCFGR2_VPFT_Msk             (0x7U << DCMIPP_HWCFGR2_VPFT_Pos)               /*!< 0x00000007 */
+#define DCMIPP_HWCFGR2_VPFT                 DCMIPP_HWCFGR2_VPFT_Msk                         /*!< Virtual pipe function */
+#define DCMIPP_HWCFGR2_DBMFT_Pos            (4U)
+#define DCMIPP_HWCFGR2_DBMFT_Msk            (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos)              /*!< 0x00000010 */
+#define DCMIPP_HWCFGR2_DBMFT                DCMIPP_HWCFGR2_DBMFT_Msk                        /*!< Double buffer mode featured */
+#define DCMIPP_HWCFGR2_PROCCLK_Pos          (8U)
+#define DCMIPP_HWCFGR2_PROCCLK_Msk          (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos)            /*!< 0x00000100 */
+#define DCMIPP_HWCFGR2_PROCCLK              DCMIPP_HWCFGR2_PROCCLK_Msk                      /*!< Processing clock linked to AXI clock featured */
+#define DCMIPP_HWCFGR2_ADDMOD_Pos           (12U)
+#define DCMIPP_HWCFGR2_ADDMOD_Msk           (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR2_ADDMOD               DCMIPP_HWCFGR2_ADDMOD_Msk                       /*!< Address modulo computation to access a small buffer in streaming featured */
+#define DCMIPP_HWCFGR2_DEC1_Pos             (16U)
+#define DCMIPP_HWCFGR2_DEC1_Msk             (0x1U << DCMIPP_HWCFGR2_DEC1_Pos)               /*!< 0x00010000 */
+#define DCMIPP_HWCFGR2_DEC1                 DCMIPP_HWCFGR2_DEC1_Msk                         /*!< Decimation on Pipe1 before downsize */
+#define DCMIPP_HWCFGR2_DEC2_Pos             (17U)
+#define DCMIPP_HWCFGR2_DEC2_Msk             (0x1U << DCMIPP_HWCFGR2_DEC2_Pos)               /*!< 0x00020000 */
+#define DCMIPP_HWCFGR2_DEC2                 DCMIPP_HWCFGR2_DEC2_Msk                         /*!< Decimation on Pipe2 before downsize */
+#define DCMIPP_HWCFGR2_MCU_Pos              (20U)
+#define DCMIPP_HWCFGR2_MCU_Msk              (0x1U << DCMIPP_HWCFGR2_MCU_Pos)                /*!< 0x00100000 */
+#define DCMIPP_HWCFGR2_MCU                  DCMIPP_HWCFGR2_MCU_Msk                          /*!< Macroblock unit as pixel format  */
+#define DCMIPP_HWCFGR2_TPG_Pos              (24U)
+#define DCMIPP_HWCFGR2_TPG_Msk              (0x1U << DCMIPP_HWCFGR2_TPG_Pos)                /*!< 0x01000000 */
+#define DCMIPP_HWCFGR2_TPG                  DCMIPP_HWCFGR2_TPG_Msk                          /*!< Test Pattern Generator */
+#define DCMIPP_HWCFGR2_STV_Pos              (28U)
+#define DCMIPP_HWCFGR2_STV_Msk              (0x1U << DCMIPP_HWCFGR2_STV_Pos)                /*!< 0x10000000 */
+#define DCMIPP_HWCFGR2_STV                  DCMIPP_HWCFGR2_STV_Msk                          /*!< Statistic Version */
+
+/****************  Bit definition for DCMIPP_HWCFGR1 register  ****************/
+#define DCMIPP_HWCFGR1_CSIFT_Pos            (0U)
+#define DCMIPP_HWCFGR1_CSIFT_Msk            (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos)              /*!< 0x00000001 */
+#define DCMIPP_HWCFGR1_CSIFT                DCMIPP_HWCFGR1_CSIFT_Msk                        /*!< CSI2 host protocol compliant */
+#define DCMIPP_HWCFGR1_PIPENB_Pos           (4U)
+#define DCMIPP_HWCFGR1_PIPENB_Msk           (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos)             /*!< 0x00000030 */
+#define DCMIPP_HWCFGR1_PIPENB               DCMIPP_HWCFGR1_PIPENB_Msk                       /*!< Number of pipes */
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos        (8U)
+#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk        (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos)          /*!< 0x00000100 */
+#define DCMIPP_HWCFGR1_IPPLUGCFG            DCMIPP_HWCFGR1_IPPLUGCFG_Msk                    /*!< IP-Plug configuration */
+#define DCMIPP_HWCFGR1_DSP1FT_Pos           (12U)
+#define DCMIPP_HWCFGR1_DSP1FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos)             /*!< 0x00001000 */
+#define DCMIPP_HWCFGR1_DSP1FT               DCMIPP_HWCFGR1_DSP1FT_Msk                       /*!< Down-sampling feature for the pixel Pipe1 */
+#define DCMIPP_HWCFGR1_DSP2FT_Pos           (13U)
+#define DCMIPP_HWCFGR1_DSP2FT_Msk           (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos)             /*!< 0x00002000 */
+#define DCMIPP_HWCFGR1_DSP2FT               DCMIPP_HWCFGR1_DSP2FT_Msk                       /*!< Down-sampling feature for the pixel Pipe2 */
+#define DCMIPP_HWCFGR1_RB2RGB_Pos           (16U)
+#define DCMIPP_HWCFGR1_RB2RGB_Msk           (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos)             /*!< 0x00010000 */
+#define DCMIPP_HWCFGR1_RB2RGB               DCMIPP_HWCFGR1_RB2RGB_Msk                       /*!< Raw Bayer to RGB feature (demosaicer) */
+#define DCMIPP_HWCFGR1_PLANARFT_Pos         (20U)
+#define DCMIPP_HWCFGR1_PLANARFT_Msk         (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos)           /*!< 0x00300000 */
+#define DCMIPP_HWCFGR1_PLANARFT             DCMIPP_HWCFGR1_PLANARFT_Msk                     /*!< Buffer features for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI1NB_Pos           (24U)
+#define DCMIPP_HWCFGR1_ROI1NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos)             /*!< 0x0F000000 */
+#define DCMIPP_HWCFGR1_ROI1NB               DCMIPP_HWCFGR1_ROI1NB_Msk                       /*!< Number of ROIs for Pipe1 */
+#define DCMIPP_HWCFGR1_ROI2NB_Pos           (28U)
+#define DCMIPP_HWCFGR1_ROI2NB_Msk           (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos)             /*!< 0xF0000000 */
+#define DCMIPP_HWCFGR1_ROI2NB               DCMIPP_HWCFGR1_ROI2NB_Msk                       /*!< Number of ROIs for Pipe2 */
+
+/*****************  Bit definition for DCMIPP_VERR register  ******************/
+#define DCMIPP_VERR_MINREV_Pos              (0U)
+#define DCMIPP_VERR_MINREV_Msk              (0xFU << DCMIPP_VERR_MINREV_Pos)                /*!< 0x0000000F */
+#define DCMIPP_VERR_MINREV                  DCMIPP_VERR_MINREV_Msk                          /*!< DCMIPP minor revision */
+#define DCMIPP_VERR_MAJREV_Pos              (4U)
+#define DCMIPP_VERR_MAJREV_Msk              (0xFU << DCMIPP_VERR_MAJREV_Pos)                /*!< 0x000000F0 */
+#define DCMIPP_VERR_MAJREV                  DCMIPP_VERR_MAJREV_Msk                          /*!< DCMIPP major revision */
+
+/*****************  Bit definition for DCMIPP_IPIDR register  *****************/
+#define DCMIPP_IPIDR_IDR_Pos                (0U)
+#define DCMIPP_IPIDR_IDR_Msk                (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos)           /*!< 0xFFFFFFFF */
+#define DCMIPP_IPIDR_IDR                    DCMIPP_IPIDR_IDR_Msk                            /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */
+
+/*****************  Bit definition for DCMIPP_SIDR register  ******************/
+#define DCMIPP_SIDR_SID_Pos                 (0U)
+#define DCMIPP_SIDR_SID_Msk                 (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos)            /*!< 0xFFFFFFFF */
+#define DCMIPP_SIDR_SID                     DCMIPP_SIDR_SID_Msk                             /*!< 4-Kbyte decoding space */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos                     (0U)
+#define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
+#define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos                     (1U)
+#define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
+#define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos                   (0U)
+#define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
+#define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos                  (8U)
+#define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos                   (16U)
+#define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos                  (31U)
+#define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_SECCFGR register  ****************/
+#define DMA_SECCFGR_SEC0_Pos     (0U)
+#define DMA_SECCFGR_SEC0_Msk     (0x1UL << DMA_SECCFGR_SEC0_Pos)                /*!< 0x00000001 */
+#define DMA_SECCFGR_SEC0         DMA_SECCFGR_SEC0_Msk                          /*!< Secure State of Channel 0 */
+#define DMA_SECCFGR_SEC1_Pos     (1U)
+#define DMA_SECCFGR_SEC1_Msk     (0x1UL << DMA_SECCFGR_SEC1_Pos)                /*!< 0x00000002 */
+#define DMA_SECCFGR_SEC1         DMA_SECCFGR_SEC1_Msk                          /*!< Secure State of Channel 1 */
+#define DMA_SECCFGR_SEC2_Pos     (2U)
+#define DMA_SECCFGR_SEC2_Msk     (0x1UL << DMA_SECCFGR_SEC2_Pos)                /*!< 0x00000004 */
+#define DMA_SECCFGR_SEC2         DMA_SECCFGR_SEC2_Msk                          /*!< Secure State of Channel 2 */
+#define DMA_SECCFGR_SEC3_Pos     (3U)
+#define DMA_SECCFGR_SEC3_Msk     (0x1UL << DMA_SECCFGR_SEC3_Pos)                /*!< 0x00000008 */
+#define DMA_SECCFGR_SEC3         DMA_SECCFGR_SEC3_Msk                          /*!< Secure State of Channel 3 */
+#define DMA_SECCFGR_SEC4_Pos     (4U)
+#define DMA_SECCFGR_SEC4_Msk     (0x1UL << DMA_SECCFGR_SEC4_Pos)                /*!< 0x00000010 */
+#define DMA_SECCFGR_SEC4         DMA_SECCFGR_SEC4_Msk                          /*!< Secure State of Channel 4 */
+#define DMA_SECCFGR_SEC5_Pos     (5U)
+#define DMA_SECCFGR_SEC5_Msk     (0x1UL << DMA_SECCFGR_SEC5_Pos)                /*!< 0x00000020 */
+#define DMA_SECCFGR_SEC5         DMA_SECCFGR_SEC5_Msk                          /*!< Secure State of Channel 5 */
+#define DMA_SECCFGR_SEC6_Pos     (6U)
+#define DMA_SECCFGR_SEC6_Msk     (0x1UL << DMA_SECCFGR_SEC6_Pos)                /*!< 0x00000040 */
+#define DMA_SECCFGR_SEC6         DMA_SECCFGR_SEC6_Msk                          /*!< Secure State of Channel 6 */
+#define DMA_SECCFGR_SEC7_Pos     (7U)
+#define DMA_SECCFGR_SEC7_Msk     (0x1UL << DMA_SECCFGR_SEC7_Pos)                /*!< 0x00000080 */
+#define DMA_SECCFGR_SEC7         DMA_SECCFGR_SEC7_Msk                          /*!< Secure State of Channel 7 */
+#define DMA_SECCFGR_SEC8_Pos     (8U)
+#define DMA_SECCFGR_SEC8_Msk     (0x1UL << DMA_SECCFGR_SEC8_Pos)                /*!< 0x00000100 */
+#define DMA_SECCFGR_SEC8         DMA_SECCFGR_SEC8_Msk                          /*!< Secure State of Channel 8 */
+#define DMA_SECCFGR_SEC9_Pos     (9U)
+#define DMA_SECCFGR_SEC9_Msk     (0x1UL << DMA_SECCFGR_SEC9_Pos)                /*!< 0x00000200 */
+#define DMA_SECCFGR_SEC9         DMA_SECCFGR_SEC9_Msk                          /*!< Secure State of Channel 9 */
+#define DMA_SECCFGR_SEC10_Pos    (10U)
+#define DMA_SECCFGR_SEC10_Msk    (0x1UL << DMA_SECCFGR_SEC10_Pos)               /*!< 0x00000400 */
+#define DMA_SECCFGR_SEC10        DMA_SECCFGR_SEC10_Msk                         /*!< Secure State of Channel 10 */
+#define DMA_SECCFGR_SEC11_Pos    (11U)
+#define DMA_SECCFGR_SEC11_Msk    (0x1UL << DMA_SECCFGR_SEC11_Pos)               /*!< 0x00000800 */
+#define DMA_SECCFGR_SEC11        DMA_SECCFGR_SEC11_Msk                         /*!< Secure State of Channel 11 */
+#define DMA_SECCFGR_SEC12_Pos    (12U)
+#define DMA_SECCFGR_SEC12_Msk    (0x1UL << DMA_SECCFGR_SEC12_Pos)               /*!< 0x00001000 */
+#define DMA_SECCFGR_SEC12        DMA_SECCFGR_SEC12_Msk                         /*!< Secure State of Channel 12 */
+#define DMA_SECCFGR_SEC13_Pos    (13U)
+#define DMA_SECCFGR_SEC13_Msk    (0x1UL << DMA_SECCFGR_SEC13_Pos)               /*!< 0x00002000 */
+#define DMA_SECCFGR_SEC13        DMA_SECCFGR_SEC13_Msk                         /*!< Secure State of Channel 13 */
+#define DMA_SECCFGR_SEC14_Pos    (14U)
+#define DMA_SECCFGR_SEC14_Msk    (0x1UL << DMA_SECCFGR_SEC14_Pos)               /*!< 0x00004000 */
+#define DMA_SECCFGR_SEC14        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 14 */
+#define DMA_SECCFGR_SEC15_Pos    (15U)
+#define DMA_SECCFGR_SEC15_Msk    (0x1UL << DMA_SECCFGR_SEC15_Pos)               /*!< 0x00008000 */
+#define DMA_SECCFGR_SEC15        DMA_SECCFGR_SEC14_Msk                         /*!< Secure State of Channel 15 */
+
+/*******************  Bit definition for DMA_PRIVCFGR register  ****************/
+#define DMA_PRIVCFGR_PRIV0_Pos              (0U)
+#define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0 */
+#define DMA_PRIVCFGR_PRIV1_Pos              (1U)
+#define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1 */
+#define DMA_PRIVCFGR_PRIV2_Pos              (2U)
+#define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2 */
+#define DMA_PRIVCFGR_PRIV3_Pos              (3U)
+#define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3 */
+#define DMA_PRIVCFGR_PRIV4_Pos              (4U)
+#define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4 */
+#define DMA_PRIVCFGR_PRIV5_Pos              (5U)
+#define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5 */
+#define DMA_PRIVCFGR_PRIV6_Pos              (6U)
+#define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6 */
+#define DMA_PRIVCFGR_PRIV7_Pos              (7U)
+#define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7 */
+#define DMA_PRIVCFGR_PRIV8_Pos              (8U)
+#define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
+#define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8 */
+#define DMA_PRIVCFGR_PRIV9_Pos              (9U)
+#define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
+#define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9 */
+#define DMA_PRIVCFGR_PRIV10_Pos             (10U)
+#define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
+#define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
+#define DMA_PRIVCFGR_PRIV11_Pos             (11U)
+#define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
+#define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */
+#define DMA_PRIVCFGR_PRIV12_Pos             (12U)
+#define DMA_PRIVCFGR_PRIV12_Msk             (0x1UL << DMA_PRIVCFGR_PRIV12_Pos)      /*!< 0x00001000 */
+#define DMA_PRIVCFGR_PRIV12                 DMA_PRIVCFGR_PRIV12_Msk                 /*!< Privileged State of Channel 12 */
+#define DMA_PRIVCFGR_PRIV13_Pos             (13U)
+#define DMA_PRIVCFGR_PRIV13_Msk             (0x1UL << DMA_PRIVCFGR_PRIV13_Pos)      /*!< 0x00002000 */
+#define DMA_PRIVCFGR_PRIV13                 DMA_PRIVCFGR_PRIV13_Msk                 /*!< Privileged State of Channel 13 */
+#define DMA_PRIVCFGR_PRIV14_Pos             (14U)
+#define DMA_PRIVCFGR_PRIV14_Msk             (0x1UL << DMA_PRIVCFGR_PRIV14_Pos)      /*!< 0x00004000 */
+#define DMA_PRIVCFGR_PRIV14                 DMA_PRIVCFGR_PRIV14_Msk                 /*!< Privileged State of Channel 14 */
+#define DMA_PRIVCFGR_PRIV15_Pos             (15U)
+#define DMA_PRIVCFGR_PRIV15_Msk             (0x1UL << DMA_PRIVCFGR_PRIV15_Pos)      /*!< 0x00008000 */
+#define DMA_PRIVCFGR_PRIV15                 DMA_PRIVCFGR_PRIV15_Msk                 /*!< Privileged State of Channel 15 */
+
+/*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
+#define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
+#define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
+#define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
+#define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
+#define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
+#define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
+#define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
+#define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
+#define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
+#define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
+#define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
+#define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
+#define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
+#define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
+#define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
+#define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
+#define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
+#define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
+#define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
+#define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
+#define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
+#define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
+#define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
+#define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
+#define DMA_RCFGLOCKR_LOCK8_Pos              (8U)
+#define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
+#define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
+#define DMA_RCFGLOCKR_LOCK9_Pos              (9U)
+#define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
+#define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
+#define DMA_RCFGLOCKR_LOCK10_Pos             (10U)
+#define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
+#define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
+#define DMA_RCFGLOCKR_LOCK11_Pos             (11U)
+#define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
+#define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */
+#define DMA_RCFGLOCKR_LOCK12_Pos             (12U)
+#define DMA_RCFGLOCKR_LOCK12_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos)      /*!< 0x00001000 */
+#define DMA_RCFGLOCKR_LOCK12                 DMA_RCFGLOCKR_LOCK12_Msk                 /*!< Lock the configuration of Channel 12 */
+#define DMA_RCFGLOCKR_LOCK13_Pos             (13U)
+#define DMA_RCFGLOCKR_LOCK13_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos)      /*!< 0x00002000 */
+#define DMA_RCFGLOCKR_LOCK13                 DMA_RCFGLOCKR_LOCK13_Msk                 /*!< Lock the configuration of Channel 13 */
+#define DMA_RCFGLOCKR_LOCK14_Pos             (14U)
+#define DMA_RCFGLOCKR_LOCK14_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos)      /*!< 0x00004000 */
+#define DMA_RCFGLOCKR_LOCK14                 DMA_RCFGLOCKR_LOCK14_Msk                 /*!< Lock the configuration of Channel 14 */
+#define DMA_RCFGLOCKR_LOCK15_Pos             (15U)
+#define DMA_RCFGLOCKR_LOCK15_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos)      /*!< 0x00008000 */
+#define DMA_RCFGLOCKR_LOCK15                 DMA_RCFGLOCKR_LOCK15_Msk                 /*!< Lock the configuration of Channel 15 */
+
+/*******************  Bit definition for DMA_MISR register  ****************/
+#define DMA_MISR_MIS0_Pos                   (0U)
+#define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
+#define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0 */
+#define DMA_MISR_MIS1_Pos                   (1U)
+#define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
+#define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1 */
+#define DMA_MISR_MIS2_Pos                   (2U)
+#define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
+#define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2 */
+#define DMA_MISR_MIS3_Pos                   (3U)
+#define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
+#define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3 */
+#define DMA_MISR_MIS4_Pos                   (4U)
+#define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
+#define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4 */
+#define DMA_MISR_MIS5_Pos                   (5U)
+#define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
+#define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5 */
+#define DMA_MISR_MIS6_Pos                   (6U)
+#define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
+#define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6 */
+#define DMA_MISR_MIS7_Pos                   (7U)
+#define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
+#define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7 */
+#define DMA_MISR_MIS8_Pos                   (8U)
+#define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
+#define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 8 */
+#define DMA_MISR_MIS9_Pos                   (9U)
+#define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
+#define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 9 */
+#define DMA_MISR_MIS10_Pos                  (10U)
+#define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
+#define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 10 */
+#define DMA_MISR_MIS11_Pos                  (11U)
+#define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
+#define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 11 */
+#define DMA_MISR_MIS12_Pos                  (12U)
+#define DMA_MISR_MIS12_Msk                  (0x1UL << DMA_MISR_MIS12_Pos)           /*!< 0x00001000 */
+#define DMA_MISR_MIS12                      DMA_MISR_MIS12_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 12 */
+#define DMA_MISR_MIS13_Pos                  (13U)
+#define DMA_MISR_MIS13_Msk                  (0x1UL << DMA_MISR_MIS13_Pos)           /*!< 0x00002000 */
+#define DMA_MISR_MIS13                      DMA_MISR_MIS13_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 13 */
+#define DMA_MISR_MIS14_Pos                  (14U)
+#define DMA_MISR_MIS14_Msk                  (0x1UL << DMA_MISR_MIS14_Pos)           /*!< 0x00004000 */
+#define DMA_MISR_MIS14                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 14 */
+#define DMA_MISR_MIS15_Pos                  (15U)
+#define DMA_MISR_MIS15_Msk                  (0x1UL << DMA_MISR_MIS15_Pos)           /*!< 0x00008000 */
+#define DMA_MISR_MIS15                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 15 */
+
+/*******************  Bit definition for DMA_SMISR register  ****************/
+#define DMA_SMISR_MIS0_Pos       (0U)
+#define DMA_SMISR_MIS0_Msk       (0x1UL << DMA_SMISR_MIS0_Pos)                  /*!< 0x00000001 */
+#define DMA_SMISR_MIS0           DMA_SMISR_MIS0_Msk                            /*!< Masked Interrupt State of Secure Channel 0 */
+#define DMA_SMISR_MIS1_Pos       (1U)
+#define DMA_SMISR_MIS1_Msk       (0x1UL << DMA_SMISR_MIS1_Pos)                  /*!< 0x00000002 */
+#define DMA_SMISR_MIS1           DMA_SMISR_MIS1_Msk                            /*!< Masked Interrupt State of Secure Channel 1 */
+#define DMA_SMISR_MIS2_Pos       (2U)
+#define DMA_SMISR_MIS2_Msk       (0x1UL << DMA_SMISR_MIS2_Pos)                  /*!< 0x00000004 */
+#define DMA_SMISR_MIS2           DMA_SMISR_MIS2_Msk                            /*!< Masked Interrupt State of Secure Channel 2 */
+#define DMA_SMISR_MIS3_Pos       (3U)
+#define DMA_SMISR_MIS3_Msk       (0x1UL << DMA_SMISR_MIS3_Pos)                  /*!< 0x00000008 */
+#define DMA_SMISR_MIS3           DMA_SMISR_MIS3_Msk                            /*!< Masked Interrupt State of Secure Channel 3 */
+#define DMA_SMISR_MIS4_Pos       (4U)
+#define DMA_SMISR_MIS4_Msk       (0x1UL << DMA_SMISR_MIS4_Pos)                  /*!< 0x00000010 */
+#define DMA_SMISR_MIS4           DMA_SMISR_MIS4_Msk                            /*!< Masked Interrupt State of Secure Channel 4 */
+#define DMA_SMISR_MIS5_Pos       (5U)
+#define DMA_SMISR_MIS5_Msk       (0x1UL << DMA_SMISR_MIS5_Pos)                  /*!< 0x00000020 */
+#define DMA_SMISR_MIS5           DMA_SMISR_MIS5_Msk                            /*!< Masked Interrupt State of Secure Channel 5 */
+#define DMA_SMISR_MIS6_Pos       (6U)
+#define DMA_SMISR_MIS6_Msk       (0x1UL << DMA_SMISR_MIS6_Pos)                  /*!< 0x00000040 */
+#define DMA_SMISR_MIS6           DMA_SMISR_MIS6_Msk                            /*!< Masked Interrupt State of Secure Channel 6 */
+#define DMA_SMISR_MIS7_Pos       (7U)
+#define DMA_SMISR_MIS7_Msk       (0x1UL << DMA_SMISR_MIS7_Pos)                  /*!< 0x00000080 */
+#define DMA_SMISR_MIS7           DMA_SMISR_MIS7_Msk                            /*!< Masked Interrupt State of Secure Channel 7 */
+#define DMA_SMISR_MIS8_Pos       (8U)
+#define DMA_SMISR_MIS8_Msk       (0x1UL << DMA_SMISR_MIS8_Pos)                  /*!< 0x00000100 */
+#define DMA_SMISR_MIS8           DMA_SMISR_MIS8_Msk                            /*!< Masked Interrupt State of Secure Channel 8 */
+#define DMA_SMISR_MIS9_Pos       (9U)
+#define DMA_SMISR_MIS9_Msk       (0x1UL << DMA_SMISR_MIS9_Pos)                  /*!< 0x00000200 */
+#define DMA_SMISR_MIS9           DMA_SMISR_MIS9_Msk                            /*!< Masked Interrupt State of Secure Channel 9 */
+#define DMA_SMISR_MIS10_Pos      (10U)
+#define DMA_SMISR_MIS10_Msk      (0x1UL << DMA_SMISR_MIS10_Pos)                 /*!< 0x00000400 */
+#define DMA_SMISR_MIS10          DMA_SMISR_MIS10_Msk                           /*!< Masked Interrupt State of Secure Channel 10 */
+#define DMA_SMISR_MIS11_Pos      (11U)
+#define DMA_SMISR_MIS11_Msk      (0x1UL << DMA_SMISR_MIS11_Pos)                 /*!< 0x00000800 */
+#define DMA_SMISR_MIS11          DMA_SMISR_MIS11_Msk                           /*!< Masked Interrupt State of Secure Channel 11 */
+#define DMA_SMISR_MIS12_Pos      (12U)
+#define DMA_SMISR_MIS12_Msk      (0x1UL << DMA_SMISR_MIS12_Pos)                 /*!< 0x00001000 */
+#define DMA_SMISR_MIS12          DMA_SMISR_MIS12_Msk                           /*!< Masked Interrupt State of Secure Channel 12 */
+#define DMA_SMISR_MIS13_Pos      (13U)
+#define DMA_SMISR_MIS13_Msk      (0x1UL << DMA_SMISR_MIS13_Pos)                 /*!< 0x00002000 */
+#define DMA_SMISR_MIS13          DMA_SMISR_MIS13_Msk                           /*!< Masked Interrupt State of Secure Channel 13 */
+#define DMA_SMISR_MIS14_Pos      (14U)
+#define DMA_SMISR_MIS14_Msk      (0x1UL << DMA_SMISR_MIS14_Pos)                 /*!< 0x00004000 */
+#define DMA_SMISR_MIS14          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 14 */
+#define DMA_SMISR_MIS15_Pos      (15U)
+#define DMA_SMISR_MIS15_Msk      (0x1UL << DMA_SMISR_MIS15_Pos)                 /*!< 0x00008000 */
+#define DMA_SMISR_MIS15          DMA_SMISR_MIS14_Msk                           /*!< Masked Interrupt State of Secure Channel 15 */
+
+/*******************  Bit definition for DMA_CLBAR register  ****************/
+#define DMA_CLBAR_LBA_Pos                   (16U)
+#define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
+#define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
+
+/*******************  Bit definition for DMA_CCIDCFGR register  *******************/
+#define DMA_CCIDCFGR_CFEN_Pos           (0U)
+#define DMA_CCIDCFGR_CFEN_Msk           (0x1UL << DMA_CCIDCFGR_CFEN_Pos)         /*!< 0x00000001 */
+#define DMA_CCIDCFGR_CFEN               DMA_CCIDCFGR_CFEN_Msk                   /*!< CID filtering enable of the channel x */
+#define DMA_CCIDCFGR_SCID_Pos           (4U)
+#define DMA_CCIDCFGR_SCID_Msk           (0x7UL << DMA_CCIDCFGR_SCID_Pos)         /*!< 0x00000070 */
+#define DMA_CCIDCFGR_SCID               DMA_CCIDCFGR_SCID_Msk                   /*!< select a static CID to the channel x */
+
+/*******************  Bit definition for DMA_CFCR register  *******************/
+#define DMA_CFCR_TCF_Pos                    (8U)
+#define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
+#define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear */
+#define DMA_CFCR_HTF_Pos                    (9U)
+#define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
+#define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear */
+#define DMA_CFCR_DTEF_Pos                   (10U)
+#define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
+#define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear */
+#define DMA_CFCR_ULEF_Pos                   (11U)
+#define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
+#define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
+#define DMA_CFCR_USEF_Pos                   (12U)
+#define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
+#define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear */
+#define DMA_CFCR_SUSPF_Pos                  (13U)
+#define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
+#define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear */
+#define DMA_CFCR_TOF_Pos                    (14U)
+#define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
+#define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun clear flag */
+
+/*******************  Bit definition for DMA_CSR register  *******************/
+#define DMA_CSR_IDLEF_Pos                   (0U)
+#define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
+#define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag */
+#define DMA_CSR_TCF_Pos                     (8U)
+#define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
+#define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag */
+#define DMA_CSR_HTF_Pos                     (9U)
+#define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
+#define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag */
+#define DMA_CSR_DTEF_Pos                    (10U)
+#define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
+#define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag */
+#define DMA_CSR_ULEF_Pos                    (11U)
+#define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
+#define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
+#define DMA_CSR_USEF_Pos                    (12U)
+#define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
+#define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag */
+#define DMA_CSR_SUSPF_Pos                   (13U)
+#define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
+#define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag */
+#define DMA_CSR_TOF_Pos                     (14U)
+#define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
+#define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag */
+#define DMA_CSR_FIFOL_Pos                   (16U)
+#define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
+#define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos                      (0U)
+#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable */
+#define DMA_CCR_RESET_Pos                   (1U)
+#define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
+#define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset */
+#define DMA_CCR_SUSP_Pos                    (2U)
+#define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
+#define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend */
+#define DMA_CCR_TCIE_Pos                    (8U)
+#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
+#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos                    (9U)
+#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
+#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable */
+#define DMA_CCR_DTEIE_Pos                   (10U)
+#define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
+#define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable */
+#define DMA_CCR_ULEIE_Pos                   (11U)
+#define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
+#define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
+#define DMA_CCR_USEIE_Pos                   (12U)
+#define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
+#define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable */
+#define DMA_CCR_SUSPIE_Pos                  (13U)
+#define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
+#define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable */
+#define DMA_CCR_TOIE_Pos                    (14U)
+#define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
+#define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable */
+#define DMA_CCR_LSM_Pos                     (16U)
+#define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
+#define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode */
+#define DMA_CCR_LAP_Pos                     (17U)
+#define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
+#define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port */
+#define DMA_CCR_PRIO_Pos                    (22U)
+#define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
+#define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level */
+#define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
+#define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
+
+/*******************  Bit definition for DMA_CTR1 register  *******************/
+#define DMA_CTR1_SDW_LOG2_Pos               (0U)
+#define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
+#define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst */
+#define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_SINC_Pos                   (3U)
+#define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
+#define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst */
+#define DMA_CTR1_SBL_1_Pos                  (4U)
+#define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
+#define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1 */
+#define DMA_CTR1_PAM_Pos                    (11U)
+#define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
+#define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode */
+#define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
+#define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
+#define DMA_CTR1_SBX_Pos                    (13U)
+#define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
+#define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
+#define DMA_CTR1_SAP_Pos                    (14U)
+#define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
+#define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port */
+#define DMA_CTR1_SSEC_Pos                   (15U)
+#define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
+#define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source */
+#define DMA_CTR1_DDW_LOG2_Pos               (16U)
+#define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
+#define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst */
+#define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
+#define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
+#define DMA_CTR1_DINC_Pos                   (19U)
+#define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
+#define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst */
+#define DMA_CTR1_DBL_1_Pos                  (20U)
+#define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
+#define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1 */
+#define DMA_CTR1_DBX_Pos                    (26U)
+#define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
+#define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange */
+#define DMA_CTR1_DHX_Pos                    (27U)
+#define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
+#define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange */
+#define DMA_CTR1_DWX_Pos                    (28U)
+#define DMA_CTR1_DWX_Msk                    (0x1UL << DMA_CTR1_DWX_Pos)             /*!< 0x10000000 */
+#define DMA_CTR1_DWX                        DMA_CTR1_DWX_Msk                        /*!< Destination word-word exchange */
+#define DMA_CTR1_DAP_Pos                    (30U)
+#define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
+#define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port */
+#define DMA_CTR1_DSEC_Pos                   (31U)
+#define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
+#define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination */
+
+/******************  Bit definition for DMA_CTR2 register  *******************/
+#define DMA_CTR2_REQSEL_Pos                 (0U)
+#define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
+#define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
+#define DMA_CTR2_SWREQ_Pos                  (9U)
+#define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
+#define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request */
+#define DMA_CTR2_DREQ_Pos                   (10U)
+#define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
+#define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request */
+#define DMA_CTR2_BREQ_Pos                   (11U)
+#define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
+#define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request */
+#define DMA_CTR2_PFREQ_Pos                  (12U)
+#define DMA_CTR2_PFREQ_Msk                  (0x1UL << DMA_CTR2_PFREQ_Pos)           /*!< 0x00001000 */
+#define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Hardware request in peripheral flow control mode */
+#define DMA_CTR2_TRIGM_Pos                  (14U)
+#define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
+#define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode */
+#define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
+#define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
+#define DMA_CTR2_TRIGSEL_Pos                (16U)
+#define DMA_CTR2_TRIGSEL_Msk                (0x7FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x007F0000 */
+#define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection */
+#define DMA_CTR2_TRIGPOL_Pos                (24U)
+#define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
+#define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity */
+#define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
+#define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
+#define DMA_CTR2_TCEM_Pos                   (30U)
+#define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
+#define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode */
+#define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
+#define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
+
+/******************  Bit definition for DMA_CBR1 register  *******************/
+#define DMA_CBR1_BNDT_Pos                   (0U)
+#define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
+#define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
+#define DMA_CBR1_BRC_Pos                    (16U)
+#define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
+#define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter */
+#define DMA_CBR1_SDEC_Pos                   (28U)
+#define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
+#define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement */
+#define DMA_CBR1_DDEC_Pos                   (29U)
+#define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
+#define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement */
+#define DMA_CBR1_BRSDEC_Pos                 (30U)
+#define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
+#define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement */
+#define DMA_CBR1_BRDDEC_Pos                 (31U)
+#define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
+#define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement */
+
+/******************  Bit definition for DMA_CSAR register  ********************/
+#define DMA_CSAR_SA_Pos                     (0U)
+#define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
+
+/******************  Bit definition for DMA_CDAR register  *******************/
+#define DMA_CDAR_DA_Pos                     (0U)
+#define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
+
+/******************  Bit definition for DMA_CTR3 register  *******************/
+#define DMA_CTR3_SAO_Pos                    (0U)
+#define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
+#define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment */
+#define DMA_CTR3_DAO_Pos                    (16U)
+#define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
+#define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
+
+/******************  Bit definition for DMA_CBR2 register  *******************/
+#define DMA_CBR2_BRSAO_Pos                  (0U)
+#define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
+#define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset */
+#define DMA_CBR2_BRDAO_Pos                  (16U)
+#define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
+#define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
+
+/******************  Bit definition for DMA_CLLR register  *******************/
+#define DMA_CLLR_LA_Pos                     (2U)
+#define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
+#define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
+#define DMA_CLLR_ULL_Pos                    (16U)
+#define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
+#define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory */
+#define DMA_CLLR_UB2_Pos                    (25U)
+#define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
+#define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory */
+#define DMA_CLLR_UT3_Pos                    (26U)
+#define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
+#define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM */
+#define DMA_CLLR_UDA_Pos                    (27U)
+#define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
+#define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM */
+#define DMA_CLLR_USA_Pos                    (28U)
+#define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
+#define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM */
+#define DMA_CLLR_UB1_Pos                    (29U)
+#define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
+#define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM */
+#define DMA_CLLR_UT2_Pos                    (30U)
+#define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
+#define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM */
+#define DMA_CLLR_UT1_Pos                    (31U)
+#define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
+#define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          DMA2D Controller (DMA2D)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DMA2D_CR register  ******************/
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0] */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /*!< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+/*!<Mode_ARGB8888/RGB888 */
+#define DMA2D_OCOLR_BLUE_1         (0x000000FFUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_1        (0x0000FF00UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_1          (0x00FF0000UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1        (0xFF000000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_2        (0x000007E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_2          (0x0000F800UL)                              /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3         (0x0000001FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_3        (0x000003E0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_3          (0x00007C00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3        (0x00008000UL)                              /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4         (0x0000000FUL)                              /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_4        (0x000000F0UL)                              /*!< Green Value  */
+#define DMA2D_OCOLR_RED_4          (0x00000F00UL)                              /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4        (0x0000F000UL)                              /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital Temperature Sensor                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DTS_PVTREG_LOCKR register  *****************/
+#define DTS_PVTREG_LOCKR_LOCK_Pos                 (0U)
+#define DTS_PVTREG_LOCKR_LOCK_Msk                 (0xFFFFFFFFUL << DTS_PVTREG_LOCKR_LOCK_Pos)         /*!< 0xFFFFFFFF */
+#define DTS_PVTREG_LOCKR_LOCK                     DTS_PVTREG_LOCKR_LOCK_Msk                           /*!< PVT software lock */
+
+/*******************  Bit definition for DTS_PVTLOCK_SR register  *****************/
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos         (0U)
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos)        /*!< 0x00000001 */
+#define DTS_PVTLOCK_SR_SW_LOCK_STATUS             DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk                   /*!< Software lock status */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos         (1U)
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk         (0x1UL << DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos)        /*!< 0x00000002 */
+#define DTS_PVTLOCK_SR_HW_LOCK_STATUS             DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk                   /*!< Hardware lock status */
+
+/*******************  Bit definition for DTS_PVTTMR_CR register  *****************/
+#define DTS_PVTTMR_CR_TMR_DELAY_Pos               (0U)
+#define DTS_PVTTMR_CR_TMR_DELAY_Msk               (0xFFFFUL << DTS_PVTTMR_CR_TMR_DELAY_Pos)           /*!< 0x0000FFFF */
+#define DTS_PVTTMR_CR_TMR_DELAY                   DTS_PVTTMR_CR_TMR_DELAY_Msk                         /*!< Timer delay */
+#define DTS_PVTTMR_CR_TMR_RUN_Pos                 (16U)
+#define DTS_PVTTMR_CR_TMR_RUN_Msk                 (0x1UL << DTS_PVTTMR_CR_TMR_RUN_Pos)                /*!< 0x00010000 */
+#define DTS_PVTTMR_CR_TMR_RUN                     DTS_PVTTMR_CR_TMR_RUN_Msk                           /*!< Enable */
+
+/*******************  Bit definition for DTS_PVTTMR_SR register  *****************/
+#define DTS_PVTTMR_SR_TMR_BUSY_Pos                (0U)
+#define DTS_PVTTMR_SR_TMR_BUSY_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_BUSY_Pos)               /*!< 0x00000001 */
+#define DTS_PVTTMR_SR_TMR_BUSY                    DTS_PVTTMR_SR_TMR_BUSY_Msk                          /*!< Counter busy flag */
+#define DTS_PVTTMR_SR_TMR_DONE_Pos                (1U)
+#define DTS_PVTTMR_SR_TMR_DONE_Msk                (0x1UL << DTS_PVTTMR_SR_TMR_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_PVTTMR_SR_TMR_DONE                    DTS_PVTTMR_SR_TMR_DONE_Msk                          /*!< Cnt delay timeout */
+
+/*******************  Bit definition for DTS_PVT_IER register  *****************/
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Pos            (0U)
+#define DTS_PVT_IER_TMR_IRQ_ENABLE_Msk            (0x1UL << DTS_PVT_IER_TMR_IRQ_ENABLE_Pos)           /*!< 0x00000001 */
+#define DTS_PVT_IER_TMR_IRQ_ENABLE                DTS_PVT_IER_TMR_IRQ_ENABLE_Msk                      /*!< Timer IRQ enable */
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Pos             (1U)
+#define DTS_PVT_IER_TS_IRQ_ENABLE_Msk             (0x1UL << DTS_PVT_IER_TS_IRQ_ENABLE_Pos)            /*!< 0x00000002 */
+#define DTS_PVT_IER_TS_IRQ_ENABLE                 DTS_PVT_IER_TS_IRQ_ENABLE_Msk                       /*!< TS IRQ enable */
+
+/*******************  Bit definition for DTS_PVTIRQTRMASKR register  *****************/
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos        (0U)
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk        (0x1UL << DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos)       /*!< 0x00000001 */
+#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK            DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk                  /*!< Timer IRQ mask */
+
+/*******************  Bit definition for DTS_TS_MR register  *****************/
+#define DTS_TS_MR_TS0_IRQ_MASK_Pos                (0U)
+#define DTS_TS_MR_TS0_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS0_IRQ_MASK_Pos)               /*!< 0x00000001 */
+#define DTS_TS_MR_TS0_IRQ_MASK                    DTS_TS_MR_TS0_IRQ_MASK_Msk                          /*!< TS0 IRQ mask */
+#define DTS_TS_MR_TS1_IRQ_MASK_Pos                (1U)
+#define DTS_TS_MR_TS1_IRQ_MASK_Msk                (0x1UL << DTS_TS_MR_TS1_IRQ_MASK_Pos)               /*!< 0x00000002 */
+#define DTS_TS_MR_TS1_IRQ_MASK                    DTS_TS_MR_TS1_IRQ_MASK_Msk                          /*!< TS1 IRQ mask */
+
+/*******************  Bit definition for DTS_PVTTR_SR register  *****************/
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos           (0U)
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk           (0x1UL << DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos)          /*!< 0x00000001 */
+#define DTS_PVTTR_SR_TMR_IRQ_STATUS               DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk                     /*!< Timer IRQ status after masking */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Pos             (0U)
+#define DTS_TS_ISR_TS0_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS0_IRQ_STATUS_Pos)            /*!< 0x00000001 */
+#define DTS_TS_ISR_TS0_IRQ_STATUS                 DTS_TS_ISR_TS0_IRQ_STATUS_Msk                       /*!< TS0 IRQ status after masking */
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Pos             (1U)
+#define DTS_TS_ISR_TS1_IRQ_STATUS_Msk             (0x1UL << DTS_TS_ISR_TS1_IRQ_STATUS_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ISR_TS1_IRQ_STATUS                 DTS_TS_ISR_TS1_IRQ_STATUS_Msk                       /*!< TS1 IRQ status after masking */
+
+/*******************  Bit definition for DTS_PVTTMRRAW_ISR register  *****************/
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos  (0U)
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk  (0x1UL << DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos) /*!< 0x00000001 */
+#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS      DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk            /*!< Timer IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSRAW_ISR register  *****************/
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos      (0U)
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos)     /*!< 0x00000001 */
+#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS0_RAW_IRQ_STATUS_Msk                /*!< TS0 IRQ status before masking */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos      (1U)
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk      (0x1UL << DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos)     /*!< 0x00000002 */
+#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS          DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk                /*!< TS1 IRQ status before masking */
+
+/*******************  Bit definition for DTS_TSCCLKSYNTHR register  *****************/
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos         (0U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos)       /*!< 0x000000FF */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO             DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk                   /*!< Synthesized clk_ts low period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos         (8U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk         (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos)       /*!< 0x0000FF00 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI             DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk                   /*!< Synthesized clk_ts ghigh period */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos       (16U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk       (0xFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos)      /*!< 0x000F0000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD           DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk                 /*!< Hold input or output delay */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos         (24U)
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk         (0x1UL << DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos)        /*!< 0x01000000 */
+#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN             DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk                   /*!< Synthesized enable */
+
+/*******************  Bit definition for DTS_TSCSDIFDISABLER register  *****************/
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos  (0U)
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk            /*!< TS0 SDIF disable */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos  (1U)
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk  (0x1UL << DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos) /*!< 0x00000002 */
+#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE      DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk            /*!< TS1 SDIF disable */
+
+/*******************  Bit definition for DTS_TSCSDIF_SR register  *****************/
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Pos              (0U)
+#define DTS_TSCSDIF_SR_SDIF_BUSY_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_BUSY_Pos)             /*!< 0x00000001 */
+#define DTS_TSCSDIF_SR_SDIF_BUSY                  DTS_TSCSDIF_SR_SDIF_BUSY_Msk                        /*!< SDIF busy flag */
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Pos              (1U)
+#define DTS_TSCSDIF_SR_SDIF_LOCK_Msk              (0x1UL << DTS_TSCSDIF_SR_SDIF_LOCK_Pos)             /*!< 0x00000002 */
+#define DTS_TSCSDIF_SR_SDIF_LOCK                  DTS_TSCSDIF_SR_SDIF_LOCK_Msk                        /*!< SDIF locked flag */
+
+/*******************  Bit definition for DTS_TSCSDIF_CR register  *****************/
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Pos             (0U)
+#define DTS_TSCSDIF_CR_SDIF_WDATA_Msk             (0xFFFFFFUL << DTS_TSCSDIF_CR_SDIF_WDATA_Pos)       /*!< 0x00FFFFFF */
+#define DTS_TSCSDIF_CR_SDIF_WDATA                 DTS_TSCSDIF_CR_SDIF_WDATA_Msk                       /*!< SDIF write data */
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Pos              (24U)
+#define DTS_TSCSDIF_CR_SDIF_ADDR_Msk              (0x7UL << DTS_TSCSDIF_CR_SDIF_ADDR_Pos)             /*!< 0x07000000 */
+#define DTS_TSCSDIF_CR_SDIF_ADDR                  DTS_TSCSDIF_CR_SDIF_ADDR_Msk                        /*!< SDIF register address */
+#define DTS_TSCSDIF_CR_SDIF_WRN_Pos               (27U)
+#define DTS_TSCSDIF_CR_SDIF_WRN_Msk               (0x1UL << DTS_TSCSDIF_CR_SDIF_WRN_Pos)              /*!< 0x08000000 */
+#define DTS_TSCSDIF_CR_SDIF_WRN                   DTS_TSCSDIF_CR_SDIF_WRN_Msk                         /*!< SDIF write no read control */
+#define DTS_TSCSDIF_CR_SDIF_PROG_Pos              (31U)
+#define DTS_TSCSDIF_CR_SDIF_PROG_Msk              (0x1UL << DTS_TSCSDIF_CR_SDIF_PROG_Pos)             /*!< 0x80000000 */
+#define DTS_TSCSDIF_CR_SDIF_PROG                  DTS_TSCSDIF_CR_SDIF_PROG_Msk                        /*!< SDIF program request */
+
+/*******************  Bit definition for DTS_TSCSDIFHALTR register  *****************/
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Pos            (0U)
+#define DTS_TSCSDIFHALTR_SDIF_STOP_Msk            (0x1UL << DTS_TSCSDIFHALTR_SDIF_STOP_Pos)           /*!< 0x00000001 */
+#define DTS_TSCSDIFHALTR_SDIF_STOP                DTS_TSCSDIFHALTR_SDIF_STOP_Msk                      /*!< SDIF stop */
+
+/*******************  Bit definition for DTS_TSCSDIF_CFGR register  *****************/
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos         (0U)
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk         (0x3UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000003 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT             DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk                   /*!< SDIF programming inhibit */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_0           (0x1UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000001 */
+#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_1           (0x2UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos)        /*!< 0x00000002 */
+
+/*******************  Bit definition for DTS_TSCSMPL_CR register  *****************/
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos       (0U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk       (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos)      /*!< 0x00000001 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE           DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk                 /*!< Sample counter disable */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos          (1U)
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk          (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos)         /*!< 0x00000002 */
+#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD              DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk                    /*!< Sample counter hold */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Pos           (2U)
+#define DTS_TSCSMPL_CR_SMPL_DISCARD_Msk           (0x1UL << DTS_TSCSMPL_CR_SMPL_DISCARD_Pos)          /*!< 0x00000004 */
+#define DTS_TSCSMPL_CR_SMPL_DISCARD               DTS_TSCSMPL_CR_SMPL_DISCARD_Msk                     /*!< Sample discard */
+
+/*******************  Bit definition for DTS_TSCSDIFSMPLCLRR register  *****************/
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos  (0U)
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk  (0x1UL << DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos) /*!< 0x00000001 */
+#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR      DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk            /*!< Sample counter clear */
+
+/*******************  Bit definition for DTS_TSCSMPLCNTR register  *****************/
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Pos            (0U)
+#define DTS_TSCSMPLCNTR_SMPL_COUNT_Msk            (0xFFFFUL << DTS_TSCSMPLCNTR_SMPL_COUNT_Pos)        /*!< 0x0000FFFF */
+#define DTS_TSCSMPLCNTR_SMPL_COUNT                DTS_TSCSMPLCNTR_SMPL_COUNT_Msk                      /*!< Sample counter  */
+
+/*******************  Bit definition for DTS_TS_IER register  *****************/
+#define DTS_TS_IER_IRQ_EN_FAULT_Pos               (0U)
+#define DTS_TS_IER_IRQ_EN_FAULT_Msk               (0x1UL << DTS_TS_IER_IRQ_EN_FAULT_Pos)              /*!< 0x00000001 */
+#define DTS_TS_IER_IRQ_EN_FAULT                   DTS_TS_IER_IRQ_EN_FAULT_Msk                         /*!< TS Fault IRQ enable */
+#define DTS_TS_IER_IRQ_EN_DONE_Pos                (1U)
+#define DTS_TS_IER_IRQ_EN_DONE_Msk                (0x1UL << DTS_TS_IER_IRQ_EN_DONE_Pos)               /*!< 0x00000002 */
+#define DTS_TS_IER_IRQ_EN_DONE                    DTS_TS_IER_IRQ_EN_DONE_Msk                          /*!< TS Sample done IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMA_Pos              (3U)
+#define DTS_TS_IER_IRQ_EN_ALARMA_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMA_Pos)             /*!< 0x00000008 */
+#define DTS_TS_IER_IRQ_EN_ALARMA                  DTS_TS_IER_IRQ_EN_ALARMA_Msk                        /*!< TS Alarm A IRQ enable */
+#define DTS_TS_IER_IRQ_EN_ALARMB_Pos              (4U)
+#define DTS_TS_IER_IRQ_EN_ALARMB_Msk              (0x1UL << DTS_TS_IER_IRQ_EN_ALARMB_Pos)             /*!< 0x00000010 */
+#define DTS_TS_IER_IRQ_EN_ALARMB                  DTS_TS_IER_IRQ_EN_ALARMB_Msk                        /*!< TS Alarm B IRQ enable */
+
+/*******************  Bit definition for DTS_TS_ISR register  *****************/
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Pos           (0U)
+#define DTS_TS_ISR_IRQ_STATUS_FAULT_Msk           (0x1UL << DTS_TS_ISR_IRQ_STATUS_FAULT_Pos)          /*!< 0x00000001 */
+#define DTS_TS_ISR_IRQ_STATUS_FAULT               DTS_TS_ISR_IRQ_STATUS_FAULT_Msk                     /*!< TS Fault IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Pos            (1U)
+#define DTS_TS_ISR_IRQ_STATUS_DONE_Msk            (0x1UL << DTS_TS_ISR_IRQ_STATUS_DONE_Pos)           /*!< 0x00000002 */
+#define DTS_TS_ISR_IRQ_STATUS_DONE                DTS_TS_ISR_IRQ_STATUS_DONE_Msk                      /*!< TS Sample done IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos          (3U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos)         /*!< 0x00000008 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMA              DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk                    /*!< TS Alarm A IRQ status */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos          (4U)
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk          (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos)         /*!< 0x00000010 */
+#define DTS_TS_ISR_IRQ_STATUS_ALARMB              DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk                    /*!< TS Alarm B IRQ status */
+
+/*******************  Bit definition for DTS_TS_ICR register  *****************/
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos            (0U)
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk            (0x1UL << DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos)           /*!< 0x00000001 */
+#define DTS_TS_ICR_IRQ_CLEAR_FAULT                DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk                      /*!< TS Fault IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Pos             (1U)
+#define DTS_TS_ICR_IRQ_CLEAR_DONE_Msk             (0x1UL << DTS_TS_ICR_IRQ_CLEAR_DONE_Pos)            /*!< 0x00000002 */
+#define DTS_TS_ICR_IRQ_CLEAR_DONE                 DTS_TS_ICR_IRQ_CLEAR_DONE_Msk                       /*!< TS Sample done IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos           (3U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos)          /*!< 0x00000008 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMA               DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk                     /*!< TS Alarm A IRQ clear */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos           (4U)
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk           (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos)          /*!< 0x00000010 */
+#define DTS_TS_ICR_IRQ_CLEAR_ALARMB               DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk                     /*!< TS Alarm B IRQ clear */
+
+/*******************  Bit definition for DTS_TSIRQTESTR register  *****************/
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos         (0U)
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk         (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos)        /*!< 0x00000001 */
+#define DTS_TSIRQTESTR_IRQ_TEST_FAULT             DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk                   /*!< TS Fault IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos          (1U)
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk          (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos)         /*!< 0x00000002 */
+#define DTS_TSIRQTESTR_IRQ_TEST_DONE              DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk                    /*!< TS Sample done IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos        (3U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos)       /*!< 0x00000008 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA            DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk                  /*!< TS Alarm A IRQ test */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos        (4U)
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk        (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos)       /*!< 0x00000010 */
+#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB            DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk                  /*!< TS Alarm B IRQ test */
+
+/*******************  Bit definition for DTS_TSSDIFRDATAR register  *****************/
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Pos           (0U)
+#define DTS_TSSDIFRDATAR_SDIF_RDATA_Msk           (0xFFFFFFUL << DTS_TSSDIFRDATAR_SDIF_RDATA_Pos)     /*!< 0x00FFFFFF */
+#define DTS_TSSDIFRDATAR_SDIF_RDATA               DTS_TSSDIFRDATAR_SDIF_RDATA_Msk                     /*!< TS SDIF read data */
+
+/*******************  Bit definition for DTS_TSSDIFDONER register  *****************/
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos        (0U)
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk        (0x1UL << DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos)       /*!< 0x00000001 */
+#define DTS_TSSDIFDONER_SDIF_SMPL_DONE            DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk                  /*!< TS Sample done flag */
+
+/*******************  Bit definition for DTS_TSSDIFDATAR register  *****************/
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Pos           (0U)
+#define DTS_TSSDIFDATAR_SAMPLE_DATA_Msk           (0xFFFFUL << DTS_TSSDIFDATAR_SAMPLE_DATA_Pos)       /*!< 0x0000FFFF */
+#define DTS_TSSDIFDATAR_SAMPLE_DATA               DTS_TSSDIFDATAR_SAMPLE_DATA_Msk                     /*!< TS Sample data */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos           (16U)
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk           (0x1UL << DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos)          /*!< 0x00010000 */
+#define DTS_TSSDIFDATAR_SAMPLE_TYPE               DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk                     /*!< TS Sample type */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos          (17U)
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk          (0x1UL << DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos)         /*!< 0x00020000 */
+#define DTS_TSSDIFDATAR_SAMPLE_FAULT              DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk                    /*!< TS Sample fault */
+
+/*******************  Bit definition for DTS_TSALARMA_CFGR register  *****************/
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos        (0U)
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk        (0xFFFFUL << DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMA_CFGR_HYSTA_THRESH            DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk                  /*!< TS Alarm A hysteresis threshold */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos       (16U)
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk       (0xFFFFUL << DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMA_CFGR_ALARMA_THRESH           DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk                 /*!< TS Alarm A threshold */
+
+/*******************  Bit definition for DTS_TSALARMB_CFGR register  *****************/
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos        (0U)
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk        (0xFFFFUL << DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos)    /*!< 0x0000FFFF */
+#define DTS_TSALARMB_CFGR_HYSTB_THRESH            DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk                  /*!< TS Alarm B hysteresis threshold */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos       (16U)
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk       (0xFFFFUL << DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos)   /*!< 0xFFFF0000 */
+#define DTS_TSALARMB_CFGR_ALARMB_THRESH           DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk                 /*!< TS Alarm B threshold */
+
+/*******************  Bit definition for DTS_TSHLSAMPLER register  *****************/
+#define DTS_TSHLSAMPLER_SMPL_LO_Pos               (0U)
+#define DTS_TSHLSAMPLER_SMPL_LO_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_LO_Pos)           /*!< 0x0000FFFF */
+#define DTS_TSHLSAMPLER_SMPL_LO                   DTS_TSHLSAMPLER_SMPL_LO_Msk                         /*!< TS Lowest valid data sample value received */
+#define DTS_TSHLSAMPLER_SMPL_HI_Pos               (16U)
+#define DTS_TSHLSAMPLER_SMPL_HI_Msk               (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_HI_Pos)           /*!< 0xFFFF0000 */
+#define DTS_TSHLSAMPLER_SMPL_HI                   DTS_TSHLSAMPLER_SMPL_HI_Msk                         /*!< TS Highest valid data sample value received */
+
+/*******************  Bit definition for DTS_TSHILORESETR register  *****************/
+#define DTS_TSHILORESETR_SMPL_LO_SET_Pos          (0U)
+#define DTS_TSHILORESETR_SMPL_LO_SET_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_LO_SET_Pos)         /*!< 0x00000001 */
+#define DTS_TSHILORESETR_SMPL_LO_SET              DTS_TSHILORESETR_SMPL_LO_SET_Msk                    /*!< TS Sample Low Set */
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Pos          (1U)
+#define DTS_TSHILORESETR_SMPL_HI_CLR_Msk          (0x1UL << DTS_TSHILORESETR_SMPL_HI_CLR_Pos)         /*!< 0x00000002 */
+#define DTS_TSHILORESETR_SMPL_HI_CLR              DTS_TSHILORESETR_SMPL_HI_CLR_Msk                    /*!< TS Sample high clear 0 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              Ethernet MAC                                  */
+/*                                                                            */
+/******************************************************************************/
+/******  Bit definition for Ethernet MAC Configuration Register  **************/
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_PB_Pos                              (18U)
+#define ETH_MACCR_PB_Msk                              (0x1UL << ETH_MACCR_PB_Pos) /*!< 0x00040000 */
+#define ETH_MACCR_PB                                  ETH_MACCR_PB_Msk         /* Packet Burst Enable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_PS_Pos                              (15U)
+#define ETH_MACCR_PS_Msk                              (0x1UL << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
+#define ETH_MACCR_PS                                  ETH_MACCR_PS_Msk         /* Port Select */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* MAC speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/******  Bit definition for Ethernet MAC Extended Configuration Register  ***********/
+#define ETH_MACECR_APDIM_Pos                          (30U)
+#define ETH_MACECR_APDIM_Msk                          (0x1FUL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */
+#define ETH_MACECR_APDIM                              ETH_MACECR_APDIM_Msk      /* ARP Packet Drop if IP Address Mismatch */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/************  Bit definition for Ethernet MAC Packet Filter Register  ***************/
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/************  Bit definition for Ethernet MAC Watchdog Timeout Register  ***************/
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/************  Bit definition for Ethernet MAC Hash Table 0 register  ***************/
+#define ETH_MACHT0R_HTH_Pos                           (0U)
+#define ETH_MACHT0R_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT0R_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/************  Bit definition for Ethernet MAC Hash Table 1 register  ***************/
+#define ETH_MACHT1R_HTL_Pos                           (0U)
+#define ETH_MACHT1R_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT1R_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/************  Bit definition for Ethernet MAC VLAN tag Control register  ***************/
+#define ETH_MACVTCR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTCR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTCR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTCR_EIVLRXS                            ETH_MACVTCR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTCR_EIVLS_Pos                          (28U)
+#define ETH_MACVTCR_EIVLS_Msk                          (0x3UL << ETH_MACVTCR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS                              ETH_MACVTCR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFPASS                  ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTCR_EIVLS_STRIPIFFAILS                 ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP                  ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTCR_ERIVLT_Msk                         (0x1UL << ETH_MACVTCR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTCR_ERIVLT                             ETH_MACVTCR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTCR_EDVLP_Pos                          (26U)
+#define ETH_MACVTCR_EDVLP_Msk                          (0x1UL << ETH_MACVTCR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTCR_EDVLP                              ETH_MACVTCR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTCR_VTHM_Pos                           (25U)
+#define ETH_MACVTCR_VTHM_Msk                           (0x1UL << ETH_MACVTCR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTCR_VTHM                               ETH_MACVTCR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTCR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTCR_EVLRXS_Msk                         (0x1UL << ETH_MACVTCR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTCR_EVLRXS                             ETH_MACVTCR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTCR_EVLS_Pos                           (21U)
+#define ETH_MACVTCR_EVLS_Msk                           (0x3UL << ETH_MACVTCR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS                               ETH_MACVTCR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTCR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTCR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTCR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTCR_EVLS_STRIPIFPASS                   ETH_MACVTCR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTCR_EVLS_STRIPIFFAILS                  ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTCR_EVLS_ALWAYSSTRIP                   ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTCR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTCR_DOVLTC_Msk                         (0x1UL << ETH_MACVTCR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTCR_DOVLTC                             ETH_MACVTCR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTCR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTCR_ERSVLM_Msk                         (0x1UL << ETH_MACVTCR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTCR_ERSVLM                             ETH_MACVTCR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTCR_ESVL_Pos                           (18U)
+#define ETH_MACVTCR_ESVL_Msk                           (0x1UL << ETH_MACVTCR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTCR_ESVL                               ETH_MACVTCR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTCR_VTIM_Pos                           (17U)
+#define ETH_MACVTCR_VTIM_Msk                           (0x1UL << ETH_MACVTCR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTCR_VTIM                               ETH_MACVTCR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTCR_ETV_Pos                            (16U)
+#define ETH_MACVTCR_ETV_Msk                            (0x1UL << ETH_MACVTCR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTCR_ETV                                ETH_MACVTCR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTCR_OFS_Pos                            (2U)
+#define ETH_MACVTCR_OFS_Msk                            (0x3UL << ETH_MACVTCR_OFS_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS                                ETH_MACVTCR_EVLS_Msk      /* Offset */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER0             ((uint32_t)0x00000000)   /* holds MAC VLAN Tag Filter0 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos) /*!< 0x00000004 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk /* holds MAC VLAN Tag Filter1 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos         (3U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk         (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos) /*!< 0x00000008 */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk /* holds MAC VLAN Tag Filter2 content */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos         (2U)
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk         (0x3UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos) /*!< 0x0000000C */
+#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3             ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk /* holds MAC VLAN Tag Filter3 content */
+#define ETH_MACVTCR_CT_Pos                             (1U)
+#define ETH_MACVTCR_CT_Msk                             (0x1UL << ETH_MACVTCR_CT_Pos) /*!< 0x00000002 */
+#define ETH_MACVTCR_CT                                 ETH_MACVTCR_CT_Msk       /* Command Type */
+#define ETH_MACVTCR_OB_Pos                             (0U)
+#define ETH_MACVTCR_OB_Msk                             (0x1UL << ETH_MACVTCR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACVTCR_OB                                 ETH_MACVTCR_OB_Msk       /* Operation Busy */
+
+/************  Bit definition for Ethernet MAC VLAN tag data register  ***************/
+#define ETH_MACVTDR_DMACHN_Pos                        (25U)
+#define ETH_MACVTDR_DMACHN_Msk                        (0x1UL << ETH_MACVTDR_DMACHN_Pos) /*!< 0x02000000 */
+#define ETH_MACVTDR_DMACHN                            ETH_MACVTDR_DMACHN_Msk   /* DMA Channel Number */
+#define ETH_MACVTDR_DMACHEN_Pos                       (24U)
+#define ETH_MACVTDR_DMACHEN_Msk                       (0x1UL << ETH_MACVTDR_DMACHEN_Pos) /*!< 0x01000000 */
+#define ETH_MACVTDR_DMACHEN                           ETH_MACVTDR_DMACHEN_Msk   /* DMA Channel Number Enable */
+#define ETH_MACVTDR_ERIVLT_Pos                        (20U)
+#define ETH_MACVTDR_ERIVLT_Msk                        (0x1UL << ETH_MACVTDR_ERIVLT_Pos) /*!< 0x00100000 */
+#define ETH_MACVTDR_ERIVLT                            ETH_MACVTDR_ERIVLT_Msk   /* Enable Inner VLAN Tag Comparison */
+#define ETH_MACVTDR_ERSVLM_Pos                        (19U)
+#define ETH_MACVTDR_ERSVLM_Msk                        (0x1UL << ETH_MACVTDR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_ERSVLM                            ETH_MACVTDR_ERSVLM_Msk   /* Enable S-VLAN Match for received Frames */
+#define ETH_MACVTDR_DOVLTC_Pos                        (18U)
+#define ETH_MACVTDR_DOVLTC_Msk                        (0x1UL << ETH_MACVTDR_DOVLTC_Pos) /*!< 0x00080000 */
+#define ETH_MACVTDR_DOVLTC                            ETH_MACVTDR_DOVLTC_Msk   /* Disable VLAN Type Comparison */
+#define ETH_MACVTDR_ETV_Pos                           (17U)
+#define ETH_MACVTDR_ETV_Msk                           (0x1UL << ETH_MACVTDR_ETV_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV                               ETH_MACVTDR_ETV_Msk   /* 12-bit or 16-bit VLAN comparison */
+#define ETH_MACVTDR_ETV_VLAN16B                       ((uint32_t)0x00000000)   /* 16-bit VLAN */
+#define ETH_MACVTDR_ETV_VLAN12B_Pos                   (17U)
+#define ETH_MACVTDR_ETV_VLAN12B_Msk                   (0x1UL << ETH_MACVTDR_ETV_VLAN12B_Pos) /*!< 0x00020000 */
+#define ETH_MACVTDR_ETV_VLAN12B                       ETH_MACVTDR_ETV_VLAN12B_Msk   /* 12-bit VLAN */
+#define ETH_MACVTDR_VEN_Pos                           (16U)
+#define ETH_MACVTDR_VEN_Msk                           (0x1UL << ETH_MACVTDR_VEN_Pos) /*!< 0x00010000 */
+#define ETH_MACVTDR_VEN                               ETH_MACVTDR_VEN_Msk   /* VLAN Tag Enable */
+#define ETH_MACVTDR_VID_Pos                           (0U)
+#define ETH_MACVTDR_VID_Msk                           (0xFFFFUL << ETH_MACVTDR_VID_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID                               ETH_MACVTDR_VID_Msk        /* VLAN Tag ID */
+#define ETH_MACVTDR_VID_12BIT_Msk                     (0xFFFU << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000FFF */
+#define ETH_MACVTDR_VID_12BIT                         ETH_MACVTDR_VID_12BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 12bit */
+#define ETH_MACVTDR_VID_16BIT_Msk                     (0xFFFFU << ETH_MACVTDR_VID_Pos)                    /*!< 0x0000FFFF */
+#define ETH_MACVTDR_VID_16BIT                         ETH_MACVTDR_VID_16BIT_Msk                           /*!< VLAN Tag Identifier field of VLAN tag 16bit */
+#define ETH_MACVTDR_VID_0                             (0x1U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000001 */
+#define ETH_MACVTDR_VID_1                             (0x2U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000002 */
+#define ETH_MACVTDR_VID_2                             (0x4U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000004 */
+#define ETH_MACVTDR_VID_3                             (0x8U << ETH_MACVTDR_VID_Pos)                       /*!< 0x00000008 */
+#define ETH_MACVTDR_VID_4                             (0x10U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000010 */
+#define ETH_MACVTDR_VID_5                             (0x20U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000020 */
+#define ETH_MACVTDR_VID_6                             (0x40U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000040 */
+#define ETH_MACVTDR_VID_7                             (0x80U << ETH_MACVTDR_VID_Pos)                      /*!< 0x00000080 */
+#define ETH_MACVTDR_VID_8                             (0x100U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000100 */
+#define ETH_MACVTDR_VID_9                             (0x200U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000200 */
+#define ETH_MACVTDR_VID_10                            (0x400U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000400 */
+#define ETH_MACVTDR_VID_11                            (0x800U << ETH_MACVTDR_VID_Pos)                     /*!< 0x00000800 */
+#define ETH_MACVTDR_VID_12                            (0x1000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00001000 */
+#define ETH_MACVTDR_VID_13                            (0x2000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00002000 */
+#define ETH_MACVTDR_VID_14                            (0x4000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00004000 */
+#define ETH_MACVTDR_VID_15                            (0x8000U << ETH_MACVTDR_VID_Pos)                    /*!< 0x00008000 */
+
+/************  Bit definition for Ethernet MAC VLAN Hash Table Register  ***************/
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/************  Bit definition for Ethernet MAC VLAN inclusion Register  ***************/
+#define ETH_MACVIR_BUSY_Pos                           (31U)
+#define ETH_MACVIR_BUSY_Msk                           (0x1UL << ETH_MACVIR_BUSY_Pos) /*!< 0x80000000 */
+#define ETH_MACVIR_BUSY                               ETH_MACVIR_BUSY_Msk      /* Busy */
+#define ETH_MACVIR_RDWR_Pos                           (30U)
+#define ETH_MACVIR_RDWR_Msk                           (0x1UL << ETH_MACVIR_RDWR_Pos) /*!< 0x40000000 */
+#define ETH_MACVIR_RDWR                               ETH_MACVIR_RDWR_Msk      /* Read write control */
+#define ETH_MACVIR_ADDR_Pos                           (24U)
+#define ETH_MACVIR_ADDR_Msk                           (0x1UL << ETH_MACVIR_ADDR_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR                               ETH_MACVIR_ADDR_Msk      /* Address */
+#define ETH_MACVIR_ADDR_VLANINSTXQ0                   ((uint32_t)0x00000000)   /* VLAN tag for insertion in the Transmit packets from Tx Queue 0 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Pos               (24U)
+#define ETH_MACVIR_ADDR_VLANINSTXQ1_Msk               (0x1UL << ETH_MACVIR_ADDR_VLANINSTXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACVIR_ADDR_VLANINSTXQ1                   ETH_MACVIR_ADDR_VLANINSTXQ1_Msk   /* VLAN tag for insertion in the Transmit packets from Tx Queue 1 */
+#define ETH_MACVIR_CBTI_Pos                           (21U)
+#define ETH_MACVIR_CBTI_Msk                           (0x1UL << ETH_MACVIR_CBTI_Pos) /*!< 0x00200000 */
+#define ETH_MACVIR_CBTI                               ETH_MACVIR_CBTI_Msk      /* Channel based tag insertion */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Inner_VLAN Incl Register   ***************/
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/************ Bit definition for Ethernet MAC Tx Queue 0 flow control Register   ***************/
+#define ETH_MACQ0TXFCR_PT_Pos                         (16U)
+#define ETH_MACQ0TXFCR_PT_Msk                         (0xFFFFUL << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACQ0TXFCR_PT                             ETH_MACQ0TXFCR_PT_Msk       /* Pause Time */
+#define ETH_MACQ0TXFCR_DZPQ_Pos                       (7U)
+#define ETH_MACQ0TXFCR_DZPQ_Msk                       (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACQ0TXFCR_DZPQ                           ETH_MACQ0TXFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACQ0TXFCR_PLT_Pos                        (4U)
+#define ETH_MACQ0TXFCR_PLT_Msk                        (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACQ0TXFCR_PLT                            ETH_MACQ0TXFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACQ0TXFCR_PLT_MINUS4                     ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Pos                (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS28_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACQ0TXFCR_PLT_MINUS28                    ETH_MACQ0TXFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Pos                (5U)
+#define ETH_MACQ0TXFCR_PLT_MINUS36_Msk                (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACQ0TXFCR_PLT_MINUS36                    ETH_MACQ0TXFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS144_Msk               (0x3UL << ETH_MACQ0TXFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACQ0TXFCR_PLT_MINUS144                   ETH_MACQ0TXFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Pos               (6U)
+#define ETH_MACQ0TXFCR_PLT_MINUS256_Msk               (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACQ0TXFCR_PLT_MINUS256                   ETH_MACQ0TXFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Pos               (4U)
+#define ETH_MACQ0TXFCR_PLT_MINUS512_Msk               (0x5UL << ETH_MACQ0TXFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACQ0TXFCR_PLT_MINUS512                   ETH_MACQ0TXFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACQ0TXFCR_TFE_Pos                        (1U)
+#define ETH_MACQ0TXFCR_TFE_Msk                        (0x1UL << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACQ0TXFCR_TFE                            ETH_MACQ0TXFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACQ0TXFCR_FCB_Pos                        (0U)
+#define ETH_MACQ0TXFCR_FCB_Msk                        (0x1UL << ETH_MACQ0TXFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACQ0TXFCR_FCB                            ETH_MACQ0TXFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/************ Bit definition for Ethernet MAC Rx flow control Register   ***************/
+#define ETH_MACRXFCR_UP_Pos                            (1U)
+#define ETH_MACRXFCR_UP_Msk                            (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRXFCR_UP                                ETH_MACRXFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRXFCR_RFE_Pos                           (0U)
+#define ETH_MACRXFCR_RFE_Msk                           (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXFCR_RFE                               ETH_MACRXFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/************ Bit definition for Ethernet MAC Rx Queue control Register  ***************/
+#define ETH_MACRXQCR_VFFQ_Pos                         (17U)
+#define ETH_MACRXQCR_VFFQ_Msk                         (0x1UL << ETH_MACRXQCR_VFFQ_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ                             ETH_MACRXQCR_VFFQ_Msk       /* VLAN Tag Filter Fail Packets Queue */
+#define ETH_MACRXQCR_VFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_VFFQ_Q1_Pos                      (17U)
+#define ETH_MACRXQCR_VFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_VFFQ_Q1_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQCR_VFFQ_Q1                          ETH_MACRXQCR_VFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_VFFQE_Pos                        (16U)
+#define ETH_MACRXQCR_VFFQE_Msk                        (0x1UL << ETH_MACRXQCR_VFFQE_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQCR_VFFQE                            ETH_MACRXQCR_VFFQE_Msk       /* VLAN Tag Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_MFFQ_Pos                         (9U)
+#define ETH_MACRXQCR_MFFQ_Msk                         (0x1UL << ETH_MACRXQCR_MFFQ_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ                             ETH_MACRXQCR_MFFQ_Msk       /* Multicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_MFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_MFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_MFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_MFFQ_Q1_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQCR_MFFQ_Q1                          ETH_MACRXQCR_MFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_MFFQE_Pos                        (8U)
+#define ETH_MACRXQCR_MFFQE_Msk                        (0x1UL << ETH_MACRXQCR_MFFQE_Pos) /*!< 0x00000100 */
+#define ETH_MACRXQCR_MFFQE                            ETH_MACRXQCR_MFFQE_Msk       /* Multicast Address Filter Fail Packets Queuing Enable */
+#define ETH_MACRXQCR_UFFQ_Pos                         (1U)
+#define ETH_MACRXQCR_UFFQ_Msk                         (0x1UL << ETH_MACRXQCR_UFFQ_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ                             ETH_MACRXQCR_UFFQ_Msk       /* Unicast Address Filter Fail Packets Queue */
+#define ETH_MACRXQCR_UFFQ_Q0                          ((uint32_t)0x00000000)      /* Queue 0 */
+#define ETH_MACRXQCR_UFFQ_Q1_Pos                      (9U)
+#define ETH_MACRXQCR_UFFQ_Q1_Msk                      (0x1UL << ETH_MACRXQCR_UFFQ_Q1_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQCR_UFFQ_Q1                          ETH_MACRXQCR_UFFQ_Q1_Msk    /* Queue 1 */
+#define ETH_MACRXQCR_UFFQE_Pos                        (0U)
+#define ETH_MACRXQCR_UFFQE_Msk                        (0x1UL << ETH_MACRXQCR_UFFQE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQCR_UFFQE                            ETH_MACRXQCR_UFFQE_Msk       /* Unicast Address Filter Fail Packets Queuing Enable */
+
+/************ Bit definition for Ethernet MAC Rx queue control 0 Register   ***************/
+#define ETH_MACRXQC0R_RXQ1EN_Pos                      (2U)
+#define ETH_MACRXQC0R_RXQ1EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
+#define ETH_MACRXQC0R_RXQ1EN                          ETH_MACRXQC0R_RXQ1EN_Msk       /* Receive Queue 1 Enable */
+#define ETH_MACRXQC0R_RXQ1EN_NOT                      ((uint32_t)0x00000000)        /* Queue 1 Not enabled */
+#define ETH_MACRXQC0R_RXQ1EN_AV_Pos                   (2U)
+#define ETH_MACRXQC0R_RXQ1EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_AV_Pos) /*!< 0x00000004 */
+#define ETH_MACRXQC0R_RXQ1EN_AV                       ETH_MACRXQC0R_RXQ1EN_AV_Msk   /* Queue 1 enabled for AV */
+#define ETH_MACRXQC0R_RXQ1EN_GT_Pos                   (3U)
+#define ETH_MACRXQC0R_RXQ1EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ1EN_GT_Pos) /*!< 0x00000008 */
+#define ETH_MACRXQC0R_RXQ1EN_GT                       ETH_MACRXQC0R_RXQ1EN_GT_Msk   /* Queue 1 enabled for Generic traffic */
+#define ETH_MACRXQC0R_RXQ0EN_Pos                      (0U)
+#define ETH_MACRXQC0R_RXQ0EN_Msk                      (0x3UL << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
+#define ETH_MACRXQC0R_RXQ0EN                          ETH_MACRXQC0R_RXQ0EN_Msk       /* Receive Queue 0 Enable */
+#define ETH_MACRXQC0R_RXQ0EN_NOT                      ((uint32_t)0x00000000)        /* Queue 0 Not enabled */
+#define ETH_MACRXQC0R_RXQ0EN_AV_Pos                   (0U)
+#define ETH_MACRXQC0R_RXQ0EN_AV_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_AV_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC0R_RXQ0EN_AV                       ETH_MACRXQC0R_RXQ0EN_AV_Msk   /* Queue 0 enabled for AV */
+#define ETH_MACRXQC0R_RXQ0EN_GT_Pos                   (1U)
+#define ETH_MACRXQC0R_RXQ0EN_GT_Msk                   (0x1UL << ETH_MACRXQC0R_RXQ0EN_GT_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQC0R_RXQ0EN_GT                       ETH_MACRXQC0R_RXQ0EN_GT_Msk   /* Queue 0 enabled for Generic traffic */
+
+/************ Bit definition for Ethernet MAC Rx queue control 1 Register   ***************/
+#define ETH_MACRXQC1R_TBRQE_Pos                       (29U)
+#define ETH_MACRXQC1R_TBRQE_Msk                       (0x1UL << ETH_MACRXQC1R_TBRQE_Pos) /*!< 0x20000000 */
+#define ETH_MACRXQC1R_TBRQE                           ETH_MACRXQC1R_TBRQE_Msk       /* Type Field Based Rx Queuing Enable */
+#define ETH_MACRXQC1R_OMCBCQ_Pos                      (28U)
+#define ETH_MACRXQC1R_OMCBCQ_Msk                      (0x1UL << ETH_MACRXQC1R_OMCBCQ_Pos) /*!< 0x10000000 */
+#define ETH_MACRXQC1R_OMCBCQ                          ETH_MACRXQC1R_OMCBCQ_Msk       /* Overriding MC-BC queue priority select */
+#define ETH_MACRXQC1R_FPRQ_Pos                        (24U)
+#define ETH_MACRXQC1R_FPRQ_Msk                        (0x7UL << ETH_MACRXQC1R_FPRQ_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_FPRQ                            ETH_MACRXQC1R_FPRQ_Msk       /* Frame Preemption Residue Queue */
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Pos                   (24U)
+#define ETH_MACRXQC1R_FPRQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_FPRQ_RXQ1_Pos) /*!< 0x01000000 */
+#define ETH_MACRXQC1R_FPRQ_RXQ1                       ETH_MACRXQC1R_FPRQ_RXQ1_Msk       /* Rx queue 1 */
+#define ETH_MACRXQC1R_TPQC_Pos                        (22U)
+#define ETH_MACRXQC1R_TPQC_Msk                        (0x3UL << ETH_MACRXQC1R_TPQC_Pos) /*!< 0x07000000 */
+#define ETH_MACRXQC1R_TPQC                            ETH_MACRXQC1R_TPQC_Msk   /* Tagged PTP over Ethernet Packets Queuing Control */
+#define ETH_MACRXQC1R_TPQC_PTPGENVLANTAG              ((uint32_t)0x00000000)   /* VLAN tagged PTPoE packets are routed as generic VLAN tagged packet */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos             (22U)
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk             (0x1UL << ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos) /*!< 0x000400000 */
+#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ                 ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk /* VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos           (23U)
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk           (0x1UL << ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos) /*!< 0x00080000 */
+#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ               ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk /* VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ */
+#define ETH_MACRXQC1R_TACPQE_Pos                      (21U)
+#define ETH_MACRXQC1R_TACPQE_Msk                      (0x1UL << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
+#define ETH_MACRXQC1R_TACPQE                          ETH_MACRXQC1R_TACPQE_Msk       /* Tagged AV Control Packets Queuing Enable */
+#define ETH_MACRXQC1R_MCBCQEN_Pos                     (20U)
+#define ETH_MACRXQC1R_MCBCQEN_Msk                     (0x1UL << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
+#define ETH_MACRXQC1R_MCBCQEN                         ETH_MACRXQC1R_MCBCQEN_Msk     /* Multicast and Broadcast Queue Enable */
+#define ETH_MACRXQC1R_MCBCQ_Pos                       (16U)
+#define ETH_MACRXQC1R_MCBCQ_Msk                       (0x7UL << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
+#define ETH_MACRXQC1R_MCBCQ                           ETH_MACRXQC1R_MCBCQ_Msk       /* Multicast and Broadcast Queue */
+#define ETH_MACRXQC1R_MCBCQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Pos                  (16U)
+#define ETH_MACRXQC1R_MCBCQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_MCBCQ_RXQ1_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQC1R_MCBCQ_RXQ1                      ETH_MACRXQC1R_MCBCQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_UPQ_Pos                         (12U)
+#define ETH_MACRXQC1R_UPQ_Msk                         (0x7UL << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
+#define ETH_MACRXQC1R_UPQ                             ETH_MACRXQC1R_UPQ_Msk       /* Untagged Packet Queue */
+#define ETH_MACRXQC1R_UPQ_RXQ0                        ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_UPQ_RXQ1_Pos                    (12U)
+#define ETH_MACRXQC1R_UPQ_RXQ1_Msk                    (0x1UL << ETH_MACRXQC1R_UPQ_RXQ1_Pos) /*!< 0x00001000 */
+#define ETH_MACRXQC1R_UPQ_RXQ1                        ETH_MACRXQC1R_UPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_PTPQ_Pos                        (4U)
+#define ETH_MACRXQC1R_PTPQ_Msk                        (0x7UL << ETH_MACRXQC1R_PTPQ_Pos) /*!< 0x00000070 */
+#define ETH_MACRXQC1R_PTPQ                            ETH_MACRXQC1R_PTPQ_Msk       /* PTP Packets Queue */
+#define ETH_MACRXQC1R_PTPQ_RXQ0                       ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Pos                   (4U)
+#define ETH_MACRXQC1R_PTPQ_RXQ1_Msk                   (0x1UL << ETH_MACRXQC1R_PTPQ_RXQ1_Pos) /*!< 0x00000010 */
+#define ETH_MACRXQC1R_PTPQ_RXQ1                       ETH_MACRXQC1R_PTPQ_RXQ1_Msk  /* Rx queue 1 */
+#define ETH_MACRXQC1R_AVCPQ_Pos                       (0U)
+#define ETH_MACRXQC1R_AVCPQ_Msk                       (0x7UL << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
+#define ETH_MACRXQC1R_AVCPQ                           ETH_MACRXQC1R_AVCPQ_Msk       /* AV Untagged Control Packets Queue */
+#define ETH_MACRXQC1R_AVCPQ_RXQ0                      ((uint32_t)0x00000000)   /* Rx queue 0 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Pos                  (0U)
+#define ETH_MACRXQC1R_AVCPQ_RXQ1_Msk                  (0x1UL << ETH_MACRXQC1R_AVCPQ_RXQ1_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC1R_AVCPQ_RXQ1                      ETH_MACRXQC1R_AVCPQ_RXQ1_Msk  /* Rx queue 1 */
+
+/************ Bit definition for Ethernet MAC Rx queue control 2 Register   ***************/
+#define ETH_MACRXQC2R_PSRQ1_Pos                       (8U)
+#define ETH_MACRXQC2R_PSRQ1_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
+#define ETH_MACRXQC2R_PSRQ1                           ETH_MACRXQC2R_PSRQ1_Msk       /* Priorities Selected in the Receive Queue 1 */
+#define ETH_MACRXQC2R_PSRQ0_Pos                       (0U)
+#define ETH_MACRXQC2R_PSRQ0_Msk                       (0xFFUL << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
+#define ETH_MACRXQC2R_PSRQ0                           ETH_MACRXQC2R_PSRQ0_Msk       /* Priorities Selected in the Receive Queue 0 */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MFRIS_Pos                          (20U)
+#define ETH_MACISR_MFRIS_Msk                          (0x1UL << ETH_MACISR_MFRIS_Pos) /*!< 0x00100000 */
+#define ETH_MACISR_MFRIS                              ETH_MACISR_MFRIS_Msk   /* MMC FPE Receive Interrupt Status */
+#define ETH_MACISR_MFTIS_Pos                          (19U)
+#define ETH_MACISR_MFTIS_Msk                          (0x1UL << ETH_MACISR_MFTIS_Pos) /*!< 0x00080000 */
+#define ETH_MACISR_MFTIS                              ETH_MACISR_MFTIS_Msk   /* MMC FPE Transmit Interrupt Status */
+#define ETH_MACISR_MDIOIS_Pos                         (18U)
+#define ETH_MACISR_MDIOIS_Msk                         (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIS                             ETH_MACISR_MDIOIS_Msk   /* MDIO Interrupt Status*/
+#define ETH_MACISR_FPEIS_Pos                          (17U)
+#define ETH_MACISR_FPEIS_Msk                          (0x1UL << ETH_MACISR_FPEIS_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIS                              ETH_MACISR_FPEIS_Msk   /* Frame Preemption Interrupt Status */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+#define ETH_MACISR_RGSMIIIS_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIS_Msk                       (0x1UL << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIS                           ETH_MACISR_RGSMIIIS_Msk     /* RGMII Interrupt Status */
+
+/************ Bit definition for Ethernet MAC Interrupt Status Register   ***************/
+#define ETH_MACISR_MDIOIE_Pos                         (18U)
+#define ETH_MACISR_MDIOIE_Msk                         (0x1UL << ETH_MACISR_MDIOIE_Pos) /*!< 0x00040000 */
+#define ETH_MACISR_MDIOIE                             ETH_MACISR_MDIOIE_Msk   /* Receive Interrupt Enable*/
+#define ETH_MACISR_FPEIE_Pos                          (17U)
+#define ETH_MACISR_FPEIE_Msk                          (0x1UL << ETH_MACISR_FPEIE_Pos) /*!< 0x00020000 */
+#define ETH_MACISR_FPEIE                              ETH_MACISR_FPEIE_Msk   /* Frame Preemption Interrupt Enable */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+#define ETH_MACISR_RGSMIIIE_Pos                       (0U)
+#define ETH_MACISR_RGSMIIIE_Msk                       (0x1UL << ETH_MACISR_RGSMIIIE_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIE                           ETH_MACISR_RGSMIIIE_Msk     /* RGMII Interrupt Enable */
+
+/************ Bit definition for Ethernet MAC Rx Tx Status Register   ***************/
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/************ Bit definition for Ethernet MAC PMT Control Status Register   ***************/
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/************ Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register   ***************/
+#define ETH_MACRWKPFR_MACRWKPFR_Pos                   (0U)
+#define ETH_MACRWKPFR_MACRWKPFR_Msk                   (0xFFFFFFFFUL << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWKPFR_MACRWKPFR                       ETH_MACRWKPFR_MACRWKPFR_Msk  /* Wake-up Packet filter register data */
+
+/************ Bit definition for Ethernet MAC LPI Control Status Register   ***************/
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLSEN_Pos                         (18U)
+#define ETH_MACLCSR_PLSEN_Msk                         (0x1UL << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
+#define ETH_MACLCSR_PLSEN                             ETH_MACLCSR_PLSEN_Msk      /* PHY Link Status Enable */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/************ Bit definition for Ethernet MAC LPI Timers Control Register   ***************/
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/************ Bit definition for Ethernet MAC LPI Entry Timer Register   ***************/
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/************ Bit definition for Ethernet MAC 1US Tic Counter Register   ***************/
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/************ Bit definition for Ethernet MAC PHYIF control status Register   ***************/
+#define ETH_MACPHYCSR_LNKSTS_Pos                      (19U)
+#define ETH_MACPHYCSR_LNKSTS_Msk                      (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS                          ETH_MACPHYCSR_LNKSTS_Msk  /* Link Status */
+#define ETH_MACPHYCSR_LNKSTS_LD                       ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LNKSTS_LU_Pos                   (19U)
+#define ETH_MACPHYCSR_LNKSTS_LU_Msk                   (0x1UL << ETH_MACPHYCSR_LNKSTS_LU_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS_LU                       ETH_MACPHYCSR_LNKSTS_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_LNKSPEED_Pos                    (17U)
+#define ETH_MACPHYCSR_LNKSPEED_Msk                    (0x3UL << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
+#define ETH_MACPHYCSR_LNKSPEED                        ETH_MACPHYCSR_LNKSPEED_Msk  /* Link Speed */
+#define ETH_MACPHYCSR_LNKSPEED_2_5MHZ                 ((uint32_t)0x00000000)    /* 2.5 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos              (17U)
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk              (0x1UL << ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos) /*!< 0x00020000 */
+#define ETH_MACPHYCSR_LNKSPEED_25MHZ                  ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk   /* 25 MHz */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos             (18U)
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk             (0x1UL << ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos) /*!< 0x00040000 */
+#define ETH_MACPHYCSR_LNKSPEED_125MHZ                 ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk  /* 125 MHz */
+#define ETH_MACPHYCSR_LNKMOD_Pos                      (16U)
+#define ETH_MACPHYCSR_LNKMOD_Msk                      (0x1UL << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKMOD                          ETH_MACPHYCSR_LNKMOD_Msk  /* Link Mode */
+#define ETH_MACPHYCSR_LNKMOD_HD                       ((uint32_t)0x00000000)    /* Half-duplex mode */
+#define ETH_MACPHYCSR_LNKMOD_FD_Pos                   (16U)
+#define ETH_MACPHYCSR_LNKMOD_FD_Msk                   (0x1UL << ETH_MACPHYCSR_LNKMOD_FD_Pos) /*!< 0x00010000 */
+#define ETH_MACPHYCSR_LNKMOD_FD                       ETH_MACPHYCSR_LNKMOD_FD_Msk  /* Full-duplex mode */
+#define ETH_MACPHYCSR_LUD_Pos                         (1U)
+#define ETH_MACPHYCSR_LUD_Msk                         (0x1UL << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD                             ETH_MACPHYCSR_LUD_Msk  /* Link Up or Down */
+#define ETH_MACPHYCSR_LUD_LD                          ((uint32_t)0x00000000)    /* Link down */
+#define ETH_MACPHYCSR_LUD_LU_Pos                      (1U)
+#define ETH_MACPHYCSR_LUD_LU_Msk                      (0x1UL << ETH_MACPHYCSR_LUD_LU_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD_LU                          ETH_MACPHYCSR_LUD_LU_Msk  /* Link up */
+#define ETH_MACPHYCSR_TC_Pos                          (0U)
+#define ETH_MACPHYCSR_TC_Msk                          (0x1UL << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
+#define ETH_MACPHYCSR_TC                              ETH_MACPHYCSR_TC_Msk  /* Transmit Configuration in RGMII */
+
+/************ Bit definition for Ethernet MAC Version Register   ***************/
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/************ Bit definition for Ethernet MAC Debug Register   ***************/
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/************ Bit definition for Ethernet MAC HW Feature 0 Register   ***************/
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos              (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RGMII                  ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk /* RGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos              (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk              (0x1UL << ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SGMII                  ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SGMII */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Pos                (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_TBI_Msk                (0x3UL << ETH_MACHWF0R_ACTPHYSEL_TBI_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_TBI                    ETH_MACHWF0R_ACTPHYSEL_TBI_Msk /* TBI */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos               (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk               (0x5UL << ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos) /*!< 0x50000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RTBI                   ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk /* RTBI */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Pos               (29U)
+#define ETH_MACHWF0R_ACTPHYSEL_SMII_Msk               (0x3UL << ETH_MACHWF0R_ACTPHYSEL_SMII_Pos) /*!< 0x60000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_SMII                   ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/************ Bit definition for Ethernet MAC HW Feature 1 Register   ***************/
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_HASHTBLSZ_NOHASH                 ((uint32_t)0x00000000)   /* No Hash table */
+#define ETH_MACHWF1R_HASHTBLSZ_64_Pos                 (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_64_Msk                 (0x1UL << ETH_MACHWF1R_HASHTBLSZ_64_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_64                     ETH_MACHWF1R_HASHTBLSZ_64_Msk /* 64 */
+#define ETH_MACHWF1R_HASHTBLSZ_128_Pos                (25U)
+#define ETH_MACHWF1R_HASHTBLSZ_128_Msk                (0x1UL << ETH_MACHWF1R_HASHTBLSZ_128_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_128                    ETH_MACHWF1R_HASHTBLSZ_128_Msk /* 128 */
+#define ETH_MACHWF1R_HASHTBLSZ_256_Pos                (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_256_Msk                (0x3UL << ETH_MACHWF1R_HASHTBLSZ_256_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_256                    ETH_MACHWF1R_HASHTBLSZ_256_Msk /* 256 */
+#define ETH_MACHWF1R_POUOST_Pos                       (23U)
+#define ETH_MACHWF1R_POUOST_Msk                       (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_POUOST                           ETH_MACHWF1R_POUOST_Msk   /* One Step for PTP over UDP/IP Feature Enable */
+#define ETH_MACHWF1R_RAVSEL_Pos                       (21U)
+#define ETH_MACHWF1R_RAVSEL_Msk                       (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_RAVSEL                           ETH_MACHWF1R_RAVSEL_Msk   /* Rx Side Only AV Feature Enable */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_SPRAM_Pos                        (5U)
+#define ETH_MACHWF1R_SPRAM_Msk                        (0x1FUL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF1R_SPRAM                            ETH_MACHWF1R_SPRAM_Msk /* MTL Receive FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/************ Bit definition for Ethernet MAC HW Feature 2 Register   ***************/
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TDCSZ_Pos                        (22U)
+#define ETH_MACHWF2R_TDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_TDCSZ                            ETH_MACHWF2R_TDCSZ_Msk /* Tx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_TXCHCNT_1DMATXCH                 ((uint32_t)0x00000000) /* 1 DMA Tx Channel */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos             (18U)
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk             (0x1UL << ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_TXCHCNT_2DMATXCH                 ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk  /* 2 DMA Tx Channels */
+#define ETH_MACHWF2R_RDCSZ_Pos                        (16U)
+#define ETH_MACHWF2R_RDCSZ_Msk                        (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00C00000 */
+#define ETH_MACHWF2R_RDCSZ                            ETH_MACHWF2R_RDCSZ_Msk /* Rx DMA Descriptor Cache Size in terms of 16-byte descriptors */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (12U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_RXCHCNT_1DMARXCH                 ((uint32_t)0x00000000) /* 1 DMA Rx Channel */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos             (12U)
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk             (0x1UL << ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_RXCHCNT_2DMARXCH                 ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk  /* 2 DMA Rx Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_TXQCNT_1MTLTXQ                   ((uint32_t)0x00000000) /* 1 MTL Tx queue */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos               (6U)
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk               (0x1UL << ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF2R_TXQCNT_2MTLTXQ                   ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk  /* 2 MTL Tx queue */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+#define ETH_MACHWF2R_RXQCNT_1MTLRXQ                   ((uint32_t)0x00000000) /* 1 MTL Rx queue */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos               (0U)
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk               (0x1UL << ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF2R_RXQCNT_2MTLRXQ                   ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk  /* 2 MTL Rx queue */
+
+/************ Bit definition for Ethernet MAC HW Feature 3 Register    ***************/
+#define ETH_MACHWF3R_ASP_Pos                          (28U)
+#define ETH_MACHWF3R_ASP_Msk                          (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP                              ETH_MACHWF3R_ASP_Msk /* Automotive Safety Package */
+#define ETH_MACHWF3R_ASP_NONE                         ((uint32_t)0x00000000) /* None */
+#define ETH_MACHWF3R_ASP_ECC_Pos                      (28U)
+#define ETH_MACHWF3R_ASP_ECC_Msk                      (0x1UL << ETH_MACHWF3R_ASP_ECC_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF3R_ASP_ECC                          ETH_MACHWF3R_ASP_ECC_Msk  /* ECC only */
+#define ETH_MACHWF3R_ASP_ASNPPE_Pos                   (29U)
+#define ETH_MACHWF3R_ASP_ASNPPE_Msk                   (0x1UL << ETH_MACHWF3R_ASP_ASNPPE_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF3R_ASP_ASNPPE                       ETH_MACHWF3R_ASP_ASNPPE_Msk  /* AS_NPPE */
+#define ETH_MACHWF3R_ASP_ASPPE_Pos                    (28U)
+#define ETH_MACHWF3R_ASP_ASPPE_Msk                    (0x3UL << ETH_MACHWF3R_ASP_ASPPE_Pos) /*!< 0x30000000 */
+#define ETH_MACHWF3R_ASP_ASPPE                        ETH_MACHWF3R_ASP_ASPPE_Msk  /* AS_PPE */
+#define ETH_MACHWF3R_TBSSEL_Pos                       (27U)
+#define ETH_MACHWF3R_TBSSEL_Msk                       (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF3R_TBSSEL                           ETH_MACHWF3R_TBSSEL_Msk /* Time-based scheduling Enable */
+#define ETH_MACHWF3R_FPESEL_Pos                       (26U)
+#define ETH_MACHWF3R_FPESEL_Msk                       (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF3R_FPESEL                           ETH_MACHWF3R_FPESEL_Msk /* Frame Preemption Enable */
+#define ETH_MACHWF3R_ESTWID_Pos                       (20U)
+#define ETH_MACHWF3R_ESTWID_Msk                       (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID                           ETH_MACHWF3R_ESTWID_Msk /* Width of the Time Interval field in the Gate Control List */
+#define ETH_MACHWF3R_ESTWID_NOWIDTH                   ((uint32_t)0x00000000) /* No Width */
+#define ETH_MACHWF3R_ESTWID_16_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_16_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_16_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF3R_ESTWID_16                        ETH_MACHWF3R_ESTWID_16_Msk  /* 16 Width */
+#define ETH_MACHWF3R_ESTWID_20_Pos                    (21U)
+#define ETH_MACHWF3R_ESTWID_20_Msk                    (0x1UL << ETH_MACHWF3R_ESTWID_20_Pos) /*!< 0x00200000 */
+#define ETH_MACHWF3R_ESTWID_20                        ETH_MACHWF3R_ESTWID_20_Msk  /* 20 Width */
+#define ETH_MACHWF3R_ESTWID_24_Pos                    (20U)
+#define ETH_MACHWF3R_ESTWID_24_Msk                    (0x3UL << ETH_MACHWF3R_ESTWID_24_Pos) /*!< 0x00300000 */
+#define ETH_MACHWF3R_ESTWID_24                        ETH_MACHWF3R_ESTWID_24_Msk  /* 24 Width */
+#define ETH_MACHWF3R_ESTDEP_Pos                       (17U)
+#define ETH_MACHWF3R_ESTDEP_Msk                       (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */
+#define ETH_MACHWF3R_ESTDEP                           ETH_MACHWF3R_ESTDEP_Msk /* Depth of the Gate Control List */
+#define ETH_MACHWF3R_ESTDEP_NODEPTH                   ((uint32_t)0x00000000) /* No depth */
+#define ETH_MACHWF3R_ESTDEP_64_Pos                    (17U)
+#define ETH_MACHWF3R_ESTDEP_64_Msk                    (0x1UL << ETH_MACHWF3R_ESTDEP_64_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF3R_ESTDEP_64                        ETH_MACHWF3R_ESTDEP_64_Msk  /* 64 depth */
+#define ETH_MACHWF3R_ESTDEP_128_Pos                   (18U)
+#define ETH_MACHWF3R_ESTDEP_128_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_128_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF3R_ESTDEP_128                       ETH_MACHWF3R_ESTDEP_128_Msk  /* 128 depth */
+#define ETH_MACHWF3R_ESTDEP_256_Pos                   (17U)
+#define ETH_MACHWF3R_ESTDEP_256_Msk                   (0x3UL << ETH_MACHWF3R_ESTDEP_256_Pos) /*!< 0x00060000 */
+#define ETH_MACHWF3R_ESTDEP_256                       ETH_MACHWF3R_ESTDEP_256_Msk  /* 256 depth */
+#define ETH_MACHWF3R_ESTDEP_512_Pos                   (19U)
+#define ETH_MACHWF3R_ESTDEP_512_Msk                   (0x1UL << ETH_MACHWF3R_ESTDEP_512_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF3R_ESTDEP_512                       ETH_MACHWF3R_ESTDEP_512_Msk  /* 512 depth */
+#define ETH_MACHWF3R_ESTDEP_1024_Pos                  (17U)
+#define ETH_MACHWF3R_ESTDEP_1024_Msk                  (0x5UL << ETH_MACHWF3R_ESTDEP_1024_Pos) /*!< 0x000A0000 */
+#define ETH_MACHWF3R_ESTDEP_1024                      ETH_MACHWF3R_ESTDEP_1024_Msk  /* 1024 depth */
+#define ETH_MACHWF3R_ESTSEL_Pos                       (16U)
+#define ETH_MACHWF3R_ESTSEL_Msk                       (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF3R_ESTSEL                           ETH_MACHWF3R_ESTSEL_Msk  /* Enhancements to Scheduled Traffic Enable */
+#define ETH_MACHWF3R_FRPES_Pos                        (13U)
+#define ETH_MACHWF3R_FRPES_Msk                        (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */
+#define ETH_MACHWF3R_FRPES                            ETH_MACHWF3R_FRPES_Msk  /* Flexible Receive Parser Table Entries size */
+#define ETH_MACHWF3R_FRPES_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPES_128_Pos                    (13U)
+#define ETH_MACHWF3R_FRPES_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_128_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF3R_FRPES_128                        ETH_MACHWF3R_FRPES_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPES_256_Pos                    (14U)
+#define ETH_MACHWF3R_FRPES_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPES_256_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF3R_FRPES_256                        ETH_MACHWF3R_FRPES_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPBS_Pos                        (11U)
+#define ETH_MACHWF3R_FRPBS_Msk                        (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */
+#define ETH_MACHWF3R_FRPBS                            ETH_MACHWF3R_FRPBS_Msk  /* Flexible Receive Parser Buffer size */
+#define ETH_MACHWF3R_FRPBS_64                         ((uint32_t)0x00000000) /* 64 entries */
+#define ETH_MACHWF3R_FRPBS_128_Pos                    (11U)
+#define ETH_MACHWF3R_FRPBS_128_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_128_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF3R_FRPBS_128                        ETH_MACHWF3R_FRPBS_128_Msk  /* 128 entries */
+#define ETH_MACHWF3R_FRPBS_256_Pos                    (12U)
+#define ETH_MACHWF3R_FRPBS_256_Msk                    (0x1UL << ETH_MACHWF3R_FRPBS_256_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF3R_FRPBS_256                        ETH_MACHWF3R_FRPBS_256_Msk  /* 256 entries */
+#define ETH_MACHWF3R_FRPSEL_Pos                       (10U)
+#define ETH_MACHWF3R_FRPSEL_Msk                       (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */
+#define ETH_MACHWF3R_FRPSEL                           ETH_MACHWF3R_FRPSEL_Msk  /* Flexible Receive Parser Selected */
+#define ETH_MACHWF3R_PDUPSEL_Pos                      (9U)
+#define ETH_MACHWF3R_PDUPSEL_Msk                      (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF3R_PDUPSEL                          ETH_MACHWF3R_PDUPSEL_Msk  /* Broadcast/Multicast Packet Duplication */
+#define ETH_MACHWF3R_DVLAN_Pos                        (5U)
+#define ETH_MACHWF3R_DVLAN_Msk                        (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF3R_DVLAN                            ETH_MACHWF3R_DVLAN_Msk  /* Double VLAN processing enable */
+#define ETH_MACHWF3R_CBTISEL_Pos                      (4U)
+#define ETH_MACHWF3R_CBTISEL_Msk                      (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF3R_CBTISEL                          ETH_MACHWF3R_CBTISEL_Msk  /* Queue/Channel based VLAN tag insertion on Tx enable */
+#define ETH_MACHWF3R_NRVF_Pos                         (0U)
+#define ETH_MACHWF3R_NRVF_Msk                         (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */
+#define ETH_MACHWF3R_NRVF                             ETH_MACHWF3R_NRVF_Msk  /* Number of Extended VLAN Tag Filters Enabled */
+#define ETH_MACHWF3R_NRVF_NOEXRXVLANFLTR              ((uint32_t)0x00000000) /* No Extended Rx VLAN Filters */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos           (0U)
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR               ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos           (1U)
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk           (0x1UL << ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR               ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk          (0x3UL << ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos) /*!< 0x00000003 */
+#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR              ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos          (2U)
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk          (0x1UL << ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR              ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos          (0U)
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk          (0x5UL << ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos) /*!< 0x00000005 */
+#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR              ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk
+
+/************ Bit definition for Ethernet MAC MDIO Address Register   ***************/
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV204_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV204_Msk                   (0x3UL << ETH_MACMDIOAR_CR_DIV204_Pos) /*!< 0x00000600 */
+#define ETH_MACMDIOAR_CR_DIV204                       ETH_MACMDIOAR_CR_DIV204_Msk /* CSR clock/204 */
+#define ETH_MACMDIOAR_CR_DIV324_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV324_Msk                   (0x7UL << ETH_MACMDIOAR_CR_DIV324_Pos) /*!< 0x00000700 */
+#define ETH_MACMDIOAR_CR_DIV324                       ETH_MACMDIOAR_CR_DIV324_Msk /* CSR clock/304 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_GOC_Pos                         (2U)
+#define ETH_MACMDIOAR_GOC_Msk                         (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_GOC_0                           (0x1U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000004 */
+#define ETH_MACMDIOAR_GOC_1                           (0x2U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000008 */
+#define ETH_MACMDIOAR_GOC                             ETH_MACMDIOAR_GOC_Msk    /* GMII Operation Command */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_GB_Pos                          (0U)
+#define ETH_MACMDIOAR_GB_Msk                          (0x1UL << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_GB                              ETH_MACMDIOAR_GB_Msk     /* GMII Busy */
+
+/************ Bit definition for Ethernet MAC MDIO Data Register   ***************/
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_GD_Pos                          (0U)
+#define ETH_MACMDIODR_GD_Msk                          (0xFFFFUL << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_GD                              ETH_MACMDIODR_GD_Msk     /* GMII Data */
+
+/************ Bit definition for Ethernet ARP Address Register    ***************/
+#define ETH_MACARPAR_ARPPA_Pos                        (0U)
+#define ETH_MACARPAR_ARPPA_Msk                        (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                            ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/************ Bit definition for Ethernet MAC CSR software control Register   ***************/
+#define ETH_MACCSRSWCR_SEEN_Pos                       (8U)
+#define ETH_MACCSRSWCR_SEEN_Msk                       (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */
+#define ETH_MACCSRSWCR_SEEN                           ETH_MACCSRSWCR_SEEN_Msk /* Slave Error Response Enable */
+#define ETH_MACCSRSWCR_RCWE_Pos                       (0U)
+#define ETH_MACCSRSWCR_RCWE_Msk                       (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */
+#define ETH_MACCSRSWCR_RCWE                           ETH_MACCSRSWCR_RCWE_Msk /* Register Clear on Write 1 Enable */
+
+/************ Bit definition for Ethernet MAC FPE control and status Register   ***************/
+#define ETH_MACFPECSR_TRSP_Pos                        (19U)
+#define ETH_MACFPECSR_TRSP_Msk                        (0x1UL << ETH_MACFPECSR_TRSP_Pos) /*!< 0x00080000 */
+#define ETH_MACFPECSR_TRSP                            ETH_MACFPECSR_TRSP_Msk /* Transmitted Respond Frame */
+#define ETH_MACFPECSR_TVER_Pos                        (18U)
+#define ETH_MACFPECSR_TVER_Msk                        (0x1UL << ETH_MACFPECSR_TVER_Pos) /*!< 0x00040000 */
+#define ETH_MACFPECSR_TVER                            ETH_MACFPECSR_TVER_Msk /* Transmitted Verify Frame */
+#define ETH_MACFPECSR_RRSP_Pos                        (17U)
+#define ETH_MACFPECSR_RRSP_Msk                        (0x1UL << ETH_MACFPECSR_RRSP_Pos) /*!< 0x00020000 */
+#define ETH_MACFPECSR_RRSP                            ETH_MACFPECSR_RRSP_Msk /* Received Respond Frame */
+#define ETH_MACFPECSR_RVER_Pos                        (16U)
+#define ETH_MACFPECSR_RVER_Msk                        (0x1UL << ETH_MACFPECSR_RVER_Pos) /*!< 0x00010000 */
+#define ETH_MACFPECSR_RVER                            ETH_MACFPECSR_RVER_Msk /* Received Verify Frame */
+#define ETH_MACFPECSR_SRSP_Pos                        (2U)
+#define ETH_MACFPECSR_SRSP_Msk                        (0x1UL << ETH_MACFPECSR_SRSP_Pos) /*!< 0x00000004 */
+#define ETH_MACFPECSR_SRSP                            ETH_MACFPECSR_SRSP_Msk /* Send Respond mPacket */
+#define ETH_MACFPECSR_SVER_Pos                        (1U)
+#define ETH_MACFPECSR_SVER_Msk                        (0x1UL << ETH_MACFPECSR_SVER_Pos) /*!< 0x00000002 */
+#define ETH_MACFPECSR_SVER                            ETH_MACFPECSR_SVER_Msk /* Send Verify mPacket */
+#define ETH_MACFPECSR_EFPE_Pos                        (0U)
+#define ETH_MACFPECSR_EFPE_Msk                        (0x1UL << ETH_MACFPECSR_EFPE_Pos) /*!< 0x00000001 */
+#define ETH_MACFPECSR_EFPE                            ETH_MACFPECSR_EFPE_Msk /* Enable Tx Frame Preemption */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMR_MPTN_Pos                        (0U)
+#define ETH_MACPRSTIMR_MPTN_Msk                        (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMR_MPTN                            ETH_MACPRSTIMR_MPTN_Msk /* MAC 1722 Presentation Time in ns */
+
+/************ Bit definition for Ethernet MAC presentation time Register   ***************/
+#define ETH_MACPRSTIMUR_MPTU_Pos                       (0U)
+#define ETH_MACPRSTIMUR_MPTU_Msk                       (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPRSTIMUR_MPTU                           ETH_MACPRSTIMUR_MPTU_Msk /* MAC 1722 Presentation Time Update */
+
+/************ Bit definition for Ethernet MAC Address 0 High Register   ***************/
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_DCS_Pos                           (16U)
+#define ETH_MACA0HR_DCS_Msk                           (0x1UL << ETH_MACA0HR_DCS_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_DCS                               ETH_MACA0HR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/************ Bit definition for Ethernet MAC Address x Low Register   ***************/
+#define ETH_MACAxLR_ADDRLO_Pos                        (0U)
+#define ETH_MACAxLR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACAxLR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACAxLR_ADDRLO                            ETH_MACAxLR_ADDRLO_Msk   /* MAC Address x*/
+
+/************ Bit definition for Ethernet MAC Address x High Register  ***************/
+#define ETH_MACAxHR_AE_Pos                            (31U)
+#define ETH_MACAxHR_AE_Msk                            (0x1UL << ETH_MACAxHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAxHR_AE                                ETH_MACAxHR_AE_Msk /* Address Enable*/
+#define ETH_MACAxHR_SA_Pos                            (30U)
+#define ETH_MACAxHR_SA_Msk                            (0x1UL << ETH_MACAxHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAxHR_SA                                ETH_MACAxHR_SA_Msk /* Source Address */
+#define ETH_MACAxHR_MBC_Pos                           (24U)
+#define ETH_MACAxHR_MBC_Msk                           (0x3FUL << ETH_MACAxHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAxHR_MBC                               ETH_MACAxHR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACAxHR_DCS_Pos                           (16U)
+#define ETH_MACAxHR_DCS_Msk                           (0x1UL << ETH_MACAxHR_DCS_Pos) /*!< 0x00010000 */
+#define ETH_MACAxHR_DCS                               ETH_MACAxHR_DCS_Msk /* DMA Channel Select */
+#define ETH_MACAxHR_ADDRHI_Pos                        (0U)
+#define ETH_MACAxHR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACAxHR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAxHR_ADDRHI                            ETH_MACAxHR_ADDRHI_Msk   /* MAC Address 1*/
+
+/************ Bit definition for Ethernet MMC Control Register   ***************/
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/************ Bit definition for Ethernet MMC Rx Interrupt Register  ***************/
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Register   ***************/
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/************ Bit definition for Ethernet MMC Rx interrupt Mask Register   ***************/
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Interrupt Mask Register   ***************/
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx Single Collision Good Packets Register   ***************/
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register   ***************/
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/************ Bit definition for Ethernet MMC Tx Packet Count Good Register  ***************/
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/************ Bit definition for Ethernet MMC Rx CRC Error Packets Register  ***************/
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx alignment error packets Register   ***************/
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/************ Bit definition for Ethernet MMC Rx Unicast Packets Good Register   ***************/
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/************ Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register   ***************/
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Tx LPI Transition Counter Register   ***************/
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register   ***************/
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/************ Bit definition for Ethernet MMC Rx LPI Transition Counter Register   ***************/
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt status Register   ***************/
+#define ETH_MMCFPETISR_HRCIS_Pos                      (1U)
+#define ETH_MMCFPETISR_HRCIS_msk                      (0x1UL <<  ETH_MMCFPETISR_HRCIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETISR_HRCIS                          ETH_MMCFPETISR_HRCIS_msk /* MMC Tx Hold Request Counter Interrupt Status */
+#define ETH_MMCFPETISR_FCIS_Pos                       (0U)
+#define ETH_MMCFPETISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPETISR_FCIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETISR_FCIS                           ETH_MMCFPETISR_FCIS_msk /* MMC Tx FPE Fragment Counter Interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Tx interrupt mask Register   ***************/
+#define ETH_MMCFPETIMR_HRCIM_Pos                      (1U)
+#define ETH_MMCFPETIMR_HRCIM_msk                      (0x1UL <<  ETH_MMCFPETIMR_HRCIM_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPETIMR_HRCIM                          ETH_MMCFPETIMR_HRCIM_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+#define ETH_MMCFPETIMR_FCIM_Pos                       (0U)
+#define ETH_MMCFPETIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPETIMR_FCIM_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPETIMR_FCIM                           ETH_MMCFPETIMR_FCIM_msk /* MMC Transmit Fragment Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC FPE Tx fragment counter Register   ***************/
+#define ETH_MMCFPETFCR_TXFFC_Pos                      (0U)
+#define ETH_MMCFPETFCR_TXFFC_msk                      (0xFFFFFFFFUL <<  ETH_MMCFPETFCR_TXFFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPETFCR_TXFFC                          ETH_MMCFPETFCR_TXFFC_msk /* MMC transmit Hold Request Counter Interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Tx hold request counter Register   ***************/
+#define ETH_MMCTHRCR_TXHRC_Pos                        (0U)
+#define ETH_MMCTHRCR_TXHRC_msk                        (0xFFFFFFFFUL <<  ETH_MMCTHRCR_TXHRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTHRCR_TXHRC                            ETH_MMCTHRCR_TXHRC_msk /* Tx hold request counter */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt status Register   ***************/
+#define ETH_MMCFPERISR_FCIS_Pos                       (3U)
+#define ETH_MMCFPERISR_FCIS_msk                       (0x1UL <<  ETH_MMCFPERISR_FCIS_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERISR_FCIS                           ETH_MMCFPERISR_FCIS_msk /* MMC Rx FPE Fragment Counter Interrupt Status */
+#define ETH_MMCFPERISR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERISR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERISR_PAOCIS                         ETH_MMCFPERISR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt status */
+#define ETH_MMCFPERISR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERISR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERISR_PSECIS                         ETH_MMCFPERISR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt status */
+#define ETH_MMCFPERISR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERISR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERISR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERISR_PAECIS                         ETH_MMCFPERISR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt status */
+
+/************ Bit definition for Ethernet MMC FPE Rx interrupt mask Register   ***************/
+#define ETH_MMCFPERIMR_FCIM_Pos                       (3U)
+#define ETH_MMCFPERIMR_FCIM_msk                       (0x1UL <<  ETH_MMCFPERIMR_FCIM_Pos) /*!< 0x00000008 */
+#define ETH_MMCFPERIMR_FCIM                           ETH_MMCFPERIMR_FCIM_msk /* MMC Rx FPE Fragment Counter Interrupt Mask */
+#define ETH_MMCFPERIMR_PAOCIS_Pos                     (2U)
+#define ETH_MMCFPERIMR_PAOCIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAOCIS_Pos) /*!< 0x00000004 */
+#define ETH_MMCFPERIMR_PAOCIS                         ETH_MMCFPERIMR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt Mask */
+#define ETH_MMCFPERIMR_PSECIS_Pos                     (1U)
+#define ETH_MMCFPERIMR_PSECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PSECIS_Pos) /*!< 0x00000002 */
+#define ETH_MMCFPERIMR_PSECIS                         ETH_MMCFPERIMR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt Mask */
+#define ETH_MMCFPERIMR_PAECIS_Pos                     (0U)
+#define ETH_MMCFPERIMR_PAECIS_msk                     (0x1UL <<  ETH_MMCFPERIMR_PAECIS_Pos) /*!< 0x00000001 */
+#define ETH_MMCFPERIMR_PAECIS                         ETH_MMCFPERIMR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt Mask */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly error Register   ***************/
+#define ETH_MMCRPAER_PAEC_Pos                         (0U)
+#define ETH_MMCRPAER_PAEC_msk                         (0xFFFFFFFFUL <<  ETH_MMCRPAER_PAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAER_PAEC                             ETH_MMCRPAER_PAEC_msk /* Rx Packet Assembly Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet SMD error Register   ***************/
+#define ETH_MMCRPSMDER_PSEC_Pos                       (0U)
+#define ETH_MMCRPSMDER_PSEC_msk                       (0xFFFFFFFFUL <<  ETH_MMCRPSMDER_PSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPSMDER_PSEC                           ETH_MMCRPSMDER_PSEC_msk /* Rx Packet SMD Error Counter */
+
+/************ Bit definition for Ethernet MMC Rx packet assembly OK Register   ***************/
+#define ETH_MMCRPAOKR_PAOC_Pos                        (0U)
+#define ETH_MMCRPAOKR_PAOC_msk                        (0xFFFFFFFFUL <<  ETH_MMCRPAOKR_PAOC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRPAOKR_PAOC                            ETH_MMCRPAOKR_PAOC_msk /* Rx Packet Assembly OK Counter */
+
+/************ Bit definition for Ethernet MMC Rx FPE fragments counter Register   ***************/
+#define ETH_MMCFPERFCR_FFC_Pos                        (0U)
+#define ETH_MMCFPERFCR_FFC_msk                        (0xFFFFFFFFUL <<  ETH_MMCFPERFCR_FFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCFPERFCR_FFC                            ETH_MMCFPERFCR_FFC_msk /* Rx FPE Fragment Counter */
+
+/************ Bit definition for Ethernet MAC L3 and L4 control 0 Register   ***************/
+#define ETH_MACL3L4C0R_DMCHEN0_Pos                     (28U)
+#define ETH_MACL3L4C0R_DMCHEN0_Msk                     (0x1UL << ETH_MACL3L4C0R_DMCHEN0_Pos) /*!< 0x10000000 */
+#define ETH_MACL3L4C0R_DMCHEN0                         ETH_MACL3L4C0R_DMCHEN0_Msk /* DMA Channel Select Enable */
+#define ETH_MACL3L4C0R_DMCHN0_Pos                      (24U)
+#define ETH_MACL3L4C0R_DMCHN0_Msk                      (0x1UL << ETH_MACL3L4C0R_DMCHN0_Pos) /*!< 0x01000000 */
+#define ETH_MACL3L4C0R_DMCHN0                          ETH_MACL3L4C0R_DMCHN0_Msk /* DMA Channel Number */
+#define ETH_MACL3L4C0R_L4DPIM0_Pos                     (21U)
+#define ETH_MACL3L4C0R_L4DPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4C0R_L4DPIM0                         ETH_MACL3L4C0R_L4DPIM0_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4DPM0_Pos                      (20U)
+#define ETH_MACL3L4C0R_L4DPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4C0R_L4DPM0                          ETH_MACL3L4C0R_L4DPM0_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4C0R_L4SPIM0_Pos                     (19U)
+#define ETH_MACL3L4C0R_L4SPIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4C0R_L4SPIM0                         ETH_MACL3L4C0R_L4SPIM0_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4SPM0_Pos                      (18U)
+#define ETH_MACL3L4C0R_L4SPM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4C0R_L4SPM0                          ETH_MACL3L4C0R_L4SPM0_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4C0R_L4PEN0_Pos                      (16U)
+#define ETH_MACL3L4C0R_L4PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4C0R_L4PEN0                          ETH_MACL3L4C0R_L4PEN0_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4C0R_L3HDBM0_Pos                     (11U)
+#define ETH_MACL3L4C0R_L3HDBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4C0R_L3HDBM0                         ETH_MACL3L4C0R_L3HDBM0_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3HSBM0_Pos                     (6U)
+#define ETH_MACL3L4C0R_L3HSBM0_Msk                     (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4C0R_L3HSBM0                         ETH_MACL3L4C0R_L3HSBM0_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3DAIM0_Pos                     (5U)
+#define ETH_MACL3L4C0R_L3DAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4C0R_L3DAIM0                         ETH_MACL3L4C0R_L3DAIM0_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3DAM0_Pos                      (4U)
+#define ETH_MACL3L4C0R_L3DAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4C0R_L3DAM0                          ETH_MACL3L4C0R_L3DAM0_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4C0R_L3SAIM0_Pos                     (3U)
+#define ETH_MACL3L4C0R_L3SAIM0_Msk                     (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4C0R_L3SAIM0                         ETH_MACL3L4C0R_L3SAIM0_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3SAM0_Pos                      (2U)
+#define ETH_MACL3L4C0R_L3SAM0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4C0R_L3SAM0                          ETH_MACL3L4C0R_L3SAM0_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4C0R_L3PEN0_Pos                      (0U)
+#define ETH_MACL3L4C0R_L3PEN0_Msk                      (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4C0R_L3PEN0                          ETH_MACL3L4C0R_L3PEN0_Msk  /* Layer 3 Protocol Enable */
+
+/************ Bit definition for Ethernet MAC Layer4 Address filter Register   ***************/
+#define ETH_MACL4A0R_L4DP0_Pos                        (16U)
+#define ETH_MACL4A0R_L4DP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4A0R_L4DP0                            ETH_MACL4A0R_L4DP0_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4A0R_L4SP0_Pos                        (0U)
+#define ETH_MACL4A0R_L4SP0_Msk                        (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4A0R_L4SP0                            ETH_MACL4A0R_L4SP0_Msk     /* Layer 4 Source Port Number Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 0 Register   ***************/
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 1 Register   ***************/
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 2 Register   ***************/
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/************ Bit definition for Ethernet MAC Layer3 Address 3 Register   ***************/
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/************ Bit definition for Ethernet MAC Indirect Access Control Register   ***************/
+#define ETH_MACIACR_MSEL_Pos                           (16U)
+#define ETH_MACIACR_MSEL_Msk                           (0xFUL << ETH_MACIACR_MSEL_Pos) /*!< 0x000F0000 */
+#define ETH_MACIACR_MSEL                               ETH_MACIACR_MSEL_Msk    /* Mode Select */
+#define ETH_MACIACR_MSEL_RXQ                           ((uint32_t)0x00000000)   /* Type-based RXQ mapping */
+#define ETH_MACIACR_AOFF_Pos                           (8U)
+#define ETH_MACIACR_AOFF_Msk                           (0xFFUL << ETH_MACIACR_AOFF_Pos) /*!< 0x0000FF00 */
+#define ETH_MACIACR_AOFF                               ETH_MACIACR_AOFF_Msk    /* Address Offset */
+#define ETH_MACIACR_AOFF_IndReg0                       ((uint32_t)0x00000000)   /* Indirect register 0 */
+#define ETH_MACIACR_AOFF_IndReg1_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg1_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg1_Pos) /*!< 0x00000100 */
+#define ETH_MACIACR_AOFF_IndReg1                       ETH_MACIACR_AOFF_IndReg1_Msk  /* Indirect register 1 */
+#define ETH_MACIACR_AOFF_IndReg2_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg2_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg2_Pos) /*!< 0x00000200 */
+#define ETH_MACIACR_AOFF_IndReg2                       ETH_MACIACR_AOFF_IndReg2_Msk  /* Indirect register 2 */
+#define ETH_MACIACR_AOFF_IndReg3_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg3_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg3_Pos) /*!< 0x00000300 */
+#define ETH_MACIACR_AOFF_IndReg3                       ETH_MACIACR_AOFF_IndReg3_Msk  /* Indirect register 3 */
+#define ETH_MACIACR_AOFF_IndReg4_Pos                   (10U)
+#define ETH_MACIACR_AOFF_IndReg4_Msk                   (0x1UL << ETH_MACIACR_AOFF_IndReg4_Pos) /*!< 0x00000400 */
+#define ETH_MACIACR_AOFF_IndReg4                       ETH_MACIACR_AOFF_IndReg4_Msk  /* Indirect register 4 */
+#define ETH_MACIACR_AOFF_IndReg5_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg5_Msk                   (0x5UL << ETH_MACIACR_AOFF_IndReg5_Pos) /*!< 0x00000500 */
+#define ETH_MACIACR_AOFF_IndReg5                       ETH_MACIACR_AOFF_IndReg5_Msk  /* Indirect register 5 */
+#define ETH_MACIACR_AOFF_IndReg6_Pos                   (9U)
+#define ETH_MACIACR_AOFF_IndReg6_Msk                   (0x3UL << ETH_MACIACR_AOFF_IndReg6_Pos) /*!< 0x00000600 */
+#define ETH_MACIACR_AOFF_IndReg6                       ETH_MACIACR_AOFF_IndReg6_Msk  /* Indirect register 6 */
+#define ETH_MACIACR_AOFF_IndReg7_Pos                   (8U)
+#define ETH_MACIACR_AOFF_IndReg7_Msk                   (0x7UL << ETH_MACIACR_AOFF_IndReg7_Pos) /*!< 0x00000700 */
+#define ETH_MACIACR_AOFF_IndReg7                       ETH_MACIACR_AOFF_IndReg7_Msk  /* Indirect register 7 */
+#define ETH_MACIACR_AUTO_Pos                           (5U)
+#define ETH_MACIACR_AUTO_Msk                           (0x1UL << ETH_MACIACR_AUTO_Pos) /*!< 0x00000020 */
+#define ETH_MACIACR_AUTO                               ETH_MACIACR_AUTO_Msk    /* Auto-increment */
+#define ETH_MACIACR_COM_Pos                            (1U)
+#define ETH_MACIACR_COM_Msk                            (0x1UL << ETH_MACIACR_COM_Pos) /*!< 0x00000002 */
+#define ETH_MACIACR_COM                                ETH_MACIACR_COM_Msk    /* Command type: 1: read operation / 0: write operation */
+#define ETH_MACIACR_OB_Pos                             (0U)
+#define ETH_MACIACR_OB_Msk                             (0x1UL << ETH_MACIACR_OB_Pos) /*!< 0x00000001 */
+#define ETH_MACIACR_OB                                 ETH_MACIACR_OB_Msk    /* Operation Busy */
+
+/************ Bit definition for Ethernet MAC type-based Rx Queue mapping Register   ***************/
+#define ETH_MACTMRQR_PFEX_Pos                          (20U)
+#define ETH_MACTMRQR_PFEX_Msk                          (0x1UL << ETH_MACTMRQR_PFEX_Pos) /*!< 0x00100000 */
+#define ETH_MACTMRQR_PFEX                              ETH_MACTMRQR_PFEX_Msk    /* Preemption or Express Packet */
+#define ETH_MACTMRQR_TMRQ_Pos                          (16U)
+#define ETH_MACTMRQR_TMRQ_Msk                          (0x7UL << ETH_MACTMRQR_TMRQ_Pos) /*!< 0x00070000 */
+#define ETH_MACTMRQR_TMRQ                              ETH_MACTMRQR_TMRQ_Msk    /* Type Match Rx Queue Number */
+#define ETH_MACTMRQR_TYP_Pos                           (0U)
+#define ETH_MACTMRQR_TYP_Msk                           (0xFFFFUL << ETH_MACTMRQR_TYP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACTMRQR_TYP                               ETH_MACTMRQR_TYP_Msk    /* Type field Value */
+
+/************ Bit definition for Ethernet MAC Timestamp Control Register   ***************/
+#define ETH_MACTSCR_AV8021ASMEN_Pos                   (28U)
+#define ETH_MACTSCR_AV8021ASMEN_Msk                   (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
+#define ETH_MACTSCR_AV8021ASMEN                       ETH_MACTSCR_AV8021ASMEN_Msk  /* AV 802.1AS Mode Enable */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_ESTI_Pos                          (20U)
+#define ETH_MACTSCR_ESTI_Msk                          (0x1UL << ETH_MACTSCR_ESTI_Pos) /*!< 0x00100000 */
+#define ETH_MACTSCR_ESTI                              ETH_MACTSCR_ESTI_Msk  /* External System Time Input */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_PTGE_Pos                          (6U)
+#define ETH_MACTSCR_PTGE_Msk                          (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */
+#define ETH_MACTSCR_PTGE                              ETH_MACTSCR_PTGE_Msk  /* Presentation Time Generation Enable */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/************ Bit definition for Ethernet MAC Sub-second Increment Register   ***************/
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Register   ***************/
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Register   ***************/
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC System Time Seconds Update Register   ***************/
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/************ Bit definition for Ethernet MAC System Time Nanoseconds Update Register   ***************/
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Addend Register   ***************/
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/************ Bit definition for Ethernet MAC Timestamp Status Register   ***************/
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR1_Pos                    (5U)
+#define ETH_MACTSSR_TSTRGTERR1_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR1_Pos) /*!< 0x00000020 */
+#define ETH_MACTSSR_TSTRGTERR1                        ETH_MACTSSR_TSTRGTERR1_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_TSTARGT1_Pos                      (4U)
+#define ETH_MACTSSR_TSTARGT1_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT1_Pos) /*!< 0x00000010 */
+#define ETH_MACTSSR_TSTARGT1                          ETH_MACTSSR_TSTARGT1_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register   ***************/
+#define ETH_MACTXTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTXTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTXTSSNR_TXTSSMIS                        ETH_MACTXTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTXTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTXTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTXTSSNR_TXTSSLO                         ETH_MACTXTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+/************ Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register   ***************/
+#define ETH_MACTXTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTXTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTXTSSSR_TXTSSHI                         ETH_MACTXTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/************ Bit definition for Ethernet MAC Auxiliary Control Register   ***************/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register   ***************/
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register   ***************/
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register   ***************/
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction  ***************/
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond   ***************/
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond   ***************/
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/************ Bit definition for Ethernet MAC Timestamp Ingress Latency   ***************/
+#define ETH_MACTSILR_ITLNS_Pos                        (16U)
+#define ETH_MACTSILR_ITLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSILR_ITLNS                            ETH_MACTSILR_ITLNS_Msk  /* Ingress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSILR_ITLSNS_Pos                       (8U)
+#define ETH_MACTSILR_ITLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSILR_ITLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Ingress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC Timestamp Egress Latency Register   ***************/
+#define ETH_MACTSELR_ETLNS_Pos                        (16U)
+#define ETH_MACTSELR_ETLNS_Msk                        (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
+#define ETH_MACTSELR_ETLNS                            ETH_MACTSILR_ITLNS_Msk  /* Egress Timestamp Latency, in nanoseconds */
+#define ETH_MACTSELR_ETLSNS_Pos                       (8U)
+#define ETH_MACTSELR_ETLSNS_Msk                       (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTSELR_ETLSNS                           ETH_MACTSILR_ITLSNS_Msk  /* Egress Timestamp Latency, in subnanoseconds */
+
+/************ Bit definition for Ethernet MAC PPS Control Register   ***************/
+#define ETH_MACPPSCR_TIMESEL_Pos                      (28U)
+#define ETH_MACPPSCR_TIMESEL_Msk                      (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSCR_TIMESEL                          ETH_MACPPSCR_TIMESEL_Msk  /* Time Select */
+#define ETH_MACPPSCR_MCGREN0_Pos                      (7U)
+#define ETH_MACPPSCR_MCGREN0_Msk                      (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0                          ETH_MACPPSCR_MCGREN0_Msk  /* MCGR Mode Enable for PPS0 Output */
+#define ETH_MACPPSCR_MCGREN0_PPS                      ((uint32_t)0x00000000)   /* PPS mode */
+#define ETH_MACPPSCR_MCGREN0_MCGR_Pos                 (7U)
+#define ETH_MACPPSCR_MCGREN0_MCGR_Msk                 (0x1UL << ETH_MACPPSCR_MCGREN0_MCGR_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSCR_MCGREN0_MCGR                     ETH_MACPPSCR_MCGREN0_MCGR_Msk  /* MCGR mode */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/************ Bit definition for Ethernet MAC PPS x target time seconds Register   ***************/
+#define ETH_MACPPSTTSxR_TSTRH0_Pos                    (0U)
+#define ETH_MACPPSTTSxR_TSTRH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSTTSxR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSxR_TSTRH0                        ETH_MACPPSTTSxR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/************ Bit definition for Ethernet MAC PPS x target time nanoseconds Register   ***************/
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Pos                 (31U)
+#define ETH_MACPPSTTNxR_TRGTBUSY0_Msk                 (0x1UL << ETH_MACPPSTTNxR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNxR_TRGTBUSY0                     ETH_MACPPSTTNxR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNxR_TTSL0_Pos                     (0U)
+#define ETH_MACPPSTTNxR_TTSL0_Msk                     (0x7FFFFFFFUL << ETH_MACPPSTTNxR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNxR_TTSL0                         ETH_MACPPSTTNxR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/************ Bit definition for Ethernet MAC PPS x Interval Register   ***************/
+#define ETH_MACPPSIxR_PPSINT0_Pos                     (0U)
+#define ETH_MACPPSIxR_PPSINT0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSIxR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIxR_PPSINT0                         ETH_MACPPSIxR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/************ Bit definition for Ethernet MAC PPS x Width Register   ***************/
+#define ETH_MACPPSWxR_PPSWIDTH0_Pos                   (0U)
+#define ETH_MACPPSWxR_PPSWIDTH0_Msk                   (0xFFFFFFFFUL << ETH_MACPPSWxR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWxR_PPSWIDTH0                       ETH_MACPPSWxR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/************ Bit definition for Ethernet MAC PTP Offload Control Register   ***************/
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_PDRDIS_Pos                        (7U)
+#define ETH_MACPOCR_PDRDIS_Msk                        (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */
+#define ETH_MACPOCR_PDRDIS                            ETH_MACPOCR_PDRDIS_Msk  /* Disable Peer Delay Response response generation */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 0 Register   ***************/
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 1 Register   ***************/
+#define ETH_MACSPI1R_SPI1_Pos                        (0U)
+#define ETH_MACSPI1R_SPI1_Msk                        (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                            ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/************ Bit definition for Ethernet MAC PTP Source Port Identity 2 Register   ***************/
+#define ETH_MACSPI2R_SPI2_Pos                        (0U)
+#define ETH_MACSPI2R_SPI2_Msk                        (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                            ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/************ Bit definition for Ethernet MAC Log Message Interval Register   ***************/
+#define ETH_MACLMIR_LMPDRI_Pos                       (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                       (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                            ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                      (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                      (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                          ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                          (0U)
+#define ETH_MACLMIR_LSI_Msk                          (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                              ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/************ Bit definition for Ethernet MTL Operation Mode Register   ***************/
+#define ETH_MTLOMR_CNTCLR_Pos                        (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                        (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                            ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                       (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                       (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                           ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_SCHALG_Pos                        (5U)
+#define ETH_MTLOMR_SCHALG_Msk                        (0x3UL << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG                            ETH_MTLOMR_SCHALG_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_SCHALG_WRR                        ((uint32_t)0x00000000)   /* Weighted round robin (WRR) algorithm */
+#define ETH_MTLOMR_SCHALG_SP_Pos                     (5U)
+#define ETH_MTLOMR_SCHALG_SP_Msk                     (0x3UL << ETH_MTLOMR_SCHALG_SP_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG_SP                         ETH_MTLOMR_SCHALG_SP_Msk  /* Strict priority (SP) algorithm */
+#define ETH_MTLOMR_RAA_Pos                           (2U)
+#define ETH_MTLOMR_RAA_Msk                           (0x1UL << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA                               ETH_MTLOMR_RAA_Msk   /* Tx Scheduling Algorithm */
+#define ETH_MTLOMR_RAA_SP                            ((uint32_t)0x00000000)   /* Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest */
+#define ETH_MTLOMR_RAA_WSP_Pos                       (2U)
+#define ETH_MTLOMR_RAA_WSP_Msk                       (0x1UL << ETH_MTLOMR_RAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA_WSP                           ETH_MTLOMR_RAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_MTLOMR_DTXSTS_Pos                        (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                        (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                            ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/************ Bit definition for Ethernet MTL Interrupt Status Register   ***************/
+#define ETH_MTLISR_ESTIS_Pos                          (18U)
+#define ETH_MTLISR_ESTIS_Msk                          (0x1UL << ETH_MTLISR_ESTIS_Pos) /*!< 0x00040000 */
+#define ETH_MTLISR_ESTIS                              ETH_MTLISR_ESTIS_Msk     /* EST (TAS- 802.1Qbv) Interrupt Status */
+#define ETH_MTLISR_Q1IS_Pos                           (1U)
+#define ETH_MTLISR_Q1IS_Msk                           (0x1UL << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
+#define ETH_MTLISR_Q1IS                               ETH_MTLISR_Q1IS_Msk       /* Queue 1 Interrupt status */
+#define ETH_MTLISR_Q0IS_Pos                           (0U)
+#define ETH_MTLISR_Q0IS_Msk                           (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_Q0IS                               ETH_MTLISR_Q0IS_Msk       /* Queue 0 Interrupt status */
+
+/************ Bit definition for Ethernet MTL Rx Queue and DMA Channel Mapping   ***************/
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Pos                 (12U)
+#define ETH_MTLRXQDMAMR_Q1DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1DDMACH_Pos) /*!< 0x00001000 */
+#define ETH_MTLRXQDMAMR_Q1DDMACH                     ETH_MTLRXQDMAMR_Q1DDMACH_Msk /* Queue 1 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Pos                 (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH                     ETH_MTLRXQDMAMR_Q1MDMACH_Msk /* Queue 1 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos          (8U)
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk /* DMA Channel 1 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Pos                 (4U)
+#define ETH_MTLRXQDMAMR_Q0DDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0DDMACH_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQDMAMR_Q0DDMACH                     ETH_MTLRXQDMAMR_Q0DDMACH_Msk /* Queue 0 Enabled for DA-based DMA Channel Selection */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Pos                 (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_Msk                 (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH                     ETH_MTLRXQDMAMR_Q0MDMACH_Msk /* Queue 0 Mapped to DMA Channel */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0              ((uint32_t)0x00000000)   /* DMA Channel 0 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos          (0U)
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk          (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1              ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk /* DMA Channel 1 */
+
+/************ Bit definition for Ethernet MTL TBS control Register   ***************/
+#define ETH_MTLTBSCR_LEOS_Pos                       (8U)
+#define ETH_MTLTBSCR_LEOS_Msk                       (0xFFFFFFUL << ETH_MTLTBSCR_LEOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEOS                           ETH_MTLTBSCR_LEOS_Msk /* Launch Expiry Offset */
+#define ETH_MTLTBSCR_LEGOS_Pos                      (4U)
+#define ETH_MTLTBSCR_LEGOS_Msk                      (0x7UL << ETH_MTLTBSCR_LEGOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_MTLTBSCR_LEGOS                          ETH_MTLTBSCR_LEGOS_Msk /* Launch Expiry GSN Offset */
+#define ETH_MTLTBSCR_LEOV_Pos                       (1U)
+#define ETH_MTLTBSCR_LEOV_Msk                       (0x1UL << ETH_MTLTBSCR_LEOV_Pos) /*!< 0x00000002 */
+#define ETH_MTLTBSCR_LEOV                           ETH_MTLTBSCR_LEOV_Msk /* Launch expiry offset valid */
+#define ETH_MTLTBSCR_ESTM_Pos                       (0U)
+#define ETH_MTLTBSCR_ESTM_Msk                       (0x1UL << ETH_MTLTBSCR_ESTM_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM                           ETH_MTLTBSCR_ESTM_Msk /* EST offset mode */
+#define ETH_MTLTBSCR_ESTM_ESTOFFDIS                 ((uint32_t)0x00000000)   /* EST offset mode disabled */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos              (0U)
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk              (0x1UL << ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos) /*!< 0x00000001 */
+#define ETH_MTLTBSCR_ESTM_ESTOFFEN                   ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk  /* EST offset mode enabled */
+
+/************ Bit definition for Ethernet MTL EST Control Register   ***************/
+#define ETH_MTLESTCR_PTOV_Pos                       (24U)
+#define ETH_MTLESTCR_PTOV_Msk                       (0xFFFFFFUL << ETH_MTLESTCR_PTOV_Pos) /*!< 0xFF000000 */
+#define ETH_MTLESTCR_PTOV                           ETH_MTLESTCR_PTOV_Msk /* PTP Time Offset Value */
+#define ETH_MTLESTCR_CTOV_Pos                       (12U)
+#define ETH_MTLESTCR_CTOV_Msk                       (0xFFFUL << ETH_MTLESTCR_CTOV_Pos) /*!< 0x00FFF000 */
+#define ETH_MTLESTCR_CTOV                           ETH_MTLESTCR_CTOV_Msk /* Current Time Offset Value */
+#define ETH_MTLESTCR_TILS_Pos                       (8U)
+#define ETH_MTLESTCR_TILS_Msk                       (0x7UL << ETH_MTLESTCR_TILS_Pos) /*!< 0x00000700 */
+#define ETH_MTLESTCR_TILS                           ETH_MTLESTCR_TILS_Msk /* Time Interval Left Shift Amount */
+#define ETH_MTLESTCR_LCSE_Pos                       (6U)
+#define ETH_MTLESTCR_LCSE_Msk                       (0x3UL << ETH_MTLESTCR_LCSE_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE                           ETH_MTLESTCR_LCSE_Msk /* Loop Count to report Scheduling Error */
+#define ETH_MTLESTCR_LCSE_4IT                       ((uint32_t)0x00000000)   /* 4 iterations */
+#define ETH_MTLESTCR_LCSE_8IT_Pos                   (6U)
+#define ETH_MTLESTCR_LCSE_8IT_Msk                   (0x1UL << ETH_MTLESTCR_LCSE_8IT_Pos) /*!< 0x00000040 */
+#define ETH_MTLESTCR_LCSE_8IT                       ETH_MTLESTCR_LCSE_8IT_Msk   /* 8 iterations */
+#define ETH_MTLESTCR_LCSE_16IT_Pos                  (7U)
+#define ETH_MTLESTCR_LCSE_16IT_Msk                  (0x1UL << ETH_MTLESTCR_LCSE_16IT_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTCR_LCSE_16IT                      ETH_MTLESTCR_LCSE_16IT_Msk  /* 16 iterations */
+#define ETH_MTLESTCR_LCSE_32IT_Pos                  (6U)
+#define ETH_MTLESTCR_LCSE_32IT_Msk                  (0x3UL << ETH_MTLESTCR_LCSE_32IT_Pos) /*!< 0x000000C0 */
+#define ETH_MTLESTCR_LCSE_32IT                      ETH_MTLESTCR_LCSE_32IT_Msk  /* 32 iterations */
+#define ETH_MTLESTCR_DFBS_Pos                       (5U)
+#define ETH_MTLESTCR_DFBS_Msk                       (0x1UL << ETH_MTLESTCR_DFBS_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTCR_DFBS                           ETH_MTLESTCR_DFBS_Msk /* Drop Frames causing Scheduling Error */
+#define ETH_MTLESTCR_DDBF_Pos                       (4U)
+#define ETH_MTLESTCR_DDBF_Msk                       (0x1UL << ETH_MTLESTCR_DDBF_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTCR_DDBF                           ETH_MTLESTCR_DDBF_Msk /* Do not Drop frames during Frame Size Error */
+#define ETH_MTLESTCR_SSWL_Pos                       (1U)
+#define ETH_MTLESTCR_SSWL_Msk                       (0x1UL << ETH_MTLESTCR_SSWL_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTCR_SSWL                           ETH_MTLESTCR_SSWL_Msk /* Switch to S/W owned list */
+#define ETH_MTLESTCR_EEST_Pos                       (0U)
+#define ETH_MTLESTCR_EEST_Msk                       (0x1UL << ETH_MTLESTCR_EEST_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTCR_EEST                           ETH_MTLESTCR_EEST_Msk /* Enable EST */
+
+/************ Bit definition for Ethernet MTL EST Extended Control Register   ***************/
+/* Bit definition for Ethernet MTL EST Extended Control Register */
+#define ETH_MTLESTECR_OVHD_Pos                       (0U)
+#define ETH_MTLESTECR_OVHD_Msk                       (0x3FUL << ETH_MTLESTECR_OVHD_Pos) /*!< 0x0000003F */
+#define ETH_MTLESTECR_OVHD                           ETH_MTLESTECR_OVHD_Msk /* Overhead Bytes Value */
+
+/************ Bit definition for Ethernet MTL EST Status Register   ***************/
+#define ETH_MTLESTSR_CGSN_Pos                       (16U)
+#define ETH_MTLESTSR_CGSN_Msk                       (0xFUL << ETH_MTLESTSR_CGSN_Pos) /*!< 0x000F0000 */
+#define ETH_MTLESTSR_CGSN                           ETH_MTLESTSR_CGSN_Msk /* Current GCL slot number */
+#define ETH_MTLESTSR_BTRL_Pos                       (8U)
+#define ETH_MTLESTSR_BTRL_Msk                       (0xFFUL << ETH_MTLESTSR_BTRL_Pos) /*!< 0x00000F00 */
+#define ETH_MTLESTSR_BTRL                           ETH_MTLESTSR_CGSN_Msk /* BTR Error Loop Count */
+#define ETH_MTLESTSR_SWOL_Pos                       (7U)
+#define ETH_MTLESTSR_SWOL_Msk                       (0x1UL << ETH_MTLESTSR_SWOL_Pos) /*!< 0x00000080 */
+#define ETH_MTLESTSR_SWOL                           ETH_MTLESTSR_SWOL_Msk /* S/W owned list */
+#define ETH_MTLESTSR_CGCE_Pos                       (4U)
+#define ETH_MTLESTSR_CGCE_Msk                       (0x1UL << ETH_MTLESTSR_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTSR_CGCE                           ETH_MTLESTSR_CGCE_Msk /* Constant Gate Control Error */
+#define ETH_MTLESTSR_HLBS_Pos                       (3U)
+#define ETH_MTLESTSR_HLBS_Msk                       (0x1UL << ETH_MTLESTSR_HLBS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTSR_HLBS                           ETH_MTLESTSR_HLBS_Msk /* Head-Of-Line Blocking due to Scheduling */
+#define ETH_MTLESTSR_HLBF_Pos                       (2U)
+#define ETH_MTLESTSR_HLBF_Msk                       (0x1UL << ETH_MTLESTSR_HLBF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTSR_HLBF                           ETH_MTLESTSR_HLBF_Msk /* Head-Of-Line Blocking due to Frame Size */
+#define ETH_MTLESTSR_BTRE_Pos                       (1U)
+#define ETH_MTLESTSR_BTRE_Msk                       (0x1UL << ETH_MTLESTSR_BTRE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTSR_BTRE                           ETH_MTLESTSR_BTRE_Msk /* BTR Error */
+#define ETH_MTLESTSR_SWLC_Pos                       (0U)
+#define ETH_MTLESTSR_SWLC_Msk                       (0x1UL << ETH_MTLESTSR_SWLC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTSR_SWLC                           ETH_MTLESTSR_SWLC_Msk /* Switch to S/W owned list Complete */
+
+/************ Bit definition for Ethernet MTL EST Schedule Error Register   ***************/
+/* Bit definition for Ethernet MTL EST Schedule Error Register */
+#define ETH_MTLESTSCHER_SEQN_Pos                       (0U)
+#define ETH_MTLESTSCHER_SEQN_Msk                       (0x3UL << ETH_MTLESTSCHER_SEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTSCHER_SEQN                           ETH_MTLESTSCHER_SEQN_Msk /* Schedule Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Error Register   ***************/
+#define ETH_MTLESTFSER_FEQN_Pos                       (0U)
+#define ETH_MTLESTFSER_FEQN_Msk                       (0x3UL << ETH_MTLESTFSER_FEQN_Pos) /*!< 0x00000003 */
+#define ETH_MTLESTFSER_FEQN                           ETH_MTLESTFSER_FEQN_Msk /* Frame Size Error Queue Number */
+
+/************ Bit definition for Ethernet MTL EST Frame size Capture Register   ***************/
+#define ETH_MTLESTFSCR_HBFQ_Pos                       (16U)
+#define ETH_MTLESTFSCR_HBFQ_Msk                       (0x1UL << ETH_MTLESTFSCR_HBFQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLESTFSCR_HBFQ                           ETH_MTLESTFSCR_HBFQ_Msk /* Queue Number of HLBF */
+#define ETH_MTLESTFSCR_HBFS_Pos                       (0U)
+#define ETH_MTLESTFSCR_HBFS_Msk                       (0x7FFFUL << ETH_MTLESTFSCR_HBFS_Pos) /*!< 0x00007FFF */
+#define ETH_MTLESTFSCR_HBFS                           ETH_MTLESTFSCR_HBFS_Msk /* Frame Size of HLBF */
+
+/************ Bit definition for Ethernet MTL EST Interrupt Enable Register   ***************/
+/* Bit definition for Ethernet MTL EST Interrupt Enable Register */
+#define ETH_MTLESTIER_CGCE_Pos                       (4U)
+#define ETH_MTLESTIER_CGCE_Msk                       (0x1UL << ETH_MTLESTIER_CGCE_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTIER_CGCE                           ETH_MTLESTIER_CGCE_Msk /* Interrupt Enable for CGCE */
+#define ETH_MTLESTIER_IEHS_Pos                       (3U)
+#define ETH_MTLESTIER_IEHS_Msk                       (0x1UL << ETH_MTLESTIER_IEHS_Pos) /*!< 0x00000008 */
+#define ETH_MTLESTIER_IEHS                           ETH_MTLESTIER_IEHS_Msk /* Interrupt Enable for HLBS */
+#define ETH_MTLESTIER_IEHF_Pos                       (2U)
+#define ETH_MTLESTIER_IEHF_Msk                       (0x1UL << ETH_MTLESTIER_IEHF_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTIER_IEHF                           ETH_MTLESTIER_IEHF_Msk /* Interrupt Enable for HLBF */
+#define ETH_MTLESTIER_IEBE_Pos                       (1U)
+#define ETH_MTLESTIER_IEBE_Msk                       (0x1UL << ETH_MTLESTIER_IEBE_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTIER_IEBE                           ETH_MTLESTIER_IEBE_Msk /* Interrupt Enable for BTR Error */
+#define ETH_MTLESTIER_IECC_Pos                       (0U)
+#define ETH_MTLESTIER_IECC_Msk                       (0x1UL << ETH_MTLESTIER_IECC_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTIER_IECC                           ETH_MTLESTIER_IECC_Msk /* Interrupt Enable for Switch List */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Register   ***************/
+#define ETH_MTLESTGCLCR_ADDR_Pos                       (8U)
+#define ETH_MTLESTGCLCR_ADDR_Msk                       (0x3FUL << ETH_MTLESTGCLCR_ADDR_Pos) /*!< 0x00003F00 */
+#define ETH_MTLESTGCLCR_ADDR                           ETH_MTLESTGCLCR_ADDR_Msk /* Gate Control List Address */
+#define ETH_MTLESTGCLCR_ADDR_BTRLOW                    ((uint32_t)0x00000000)   /* BTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk               (0x1UL << ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos) /*!< 0x00000100 */
+#define ETH_MTLESTGCLCR_ADDR_BTRHIGH                   ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk /* BTR High (63:31) */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos                (9U)
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk                (0x1UL << ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos) /*!< 0x00000200 */
+#define ETH_MTLESTGCLCR_ADDR_CTRLOW                    ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk /* CTR Low (31:0) */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos               (8U)
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk               (0x3UL << ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos) /*!< 0x00000300 */
+#define ETH_MTLESTGCLCR_ADDR_CTRHIGH                   ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk /* CTR High (39:32) */
+#define ETH_MTLESTGCLCR_ADDR_TER_Pos                   (10U)
+#define ETH_MTLESTGCLCR_ADDR_TER_Msk                   (0x1UL << ETH_MTLESTGCLCR_ADDR_TER_Pos) /*!< 0x00000400 */
+#define ETH_MTLESTGCLCR_ADDR_TER                       ETH_MTLESTGCLCR_ADDR_TER_Msk /* TER (30:0) */
+#define ETH_MTLESTGCLCR_ADDR_LLR_Pos                   (8U)
+#define ETH_MTLESTGCLCR_ADDR_LLR_Msk                   (0x5UL << ETH_MTLESTGCLCR_ADDR_LLR_Pos) /*!< 0x00000500 */
+#define ETH_MTLESTGCLCR_ADDR_LLR                       ETH_MTLESTGCLCR_ADDR_LLR_Msk /* LLR (6:0) */
+#define ETH_MTLESTGCLCR_DBGB_Pos                       (5U)
+#define ETH_MTLESTGCLCR_DBGB_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGB_Pos) /*!< 0x00000020 */
+#define ETH_MTLESTGCLCR_DBGB                           ETH_MTLESTGCLCR_DBGB_Msk /* Debug Mode Bank Select */
+#define ETH_MTLESTGCLCR_DBGM_Pos                       (4U)
+#define ETH_MTLESTGCLCR_DBGM_Msk                       (0x1UL << ETH_MTLESTGCLCR_DBGM_Pos) /*!< 0x00000010 */
+#define ETH_MTLESTGCLCR_DBGM                           ETH_MTLESTGCLCR_DBGM_Msk /* Debug Mode */
+#define ETH_MTLESTGCLCR_GCRR_Pos                       (2U)
+#define ETH_MTLESTGCLCR_GCRR_Msk                       (0x1UL << ETH_MTLESTGCLCR_GCRR_Pos) /*!< 0x00000004 */
+#define ETH_MTLESTGCLCR_GCRR                           ETH_MTLESTGCLCR_GCRR_Msk /* Gate Control Related Registers */
+#define ETH_MTLESTGCLCR_R1W0_Pos                       (1U)
+#define ETH_MTLESTGCLCR_R1W0_Msk                       (0x1UL << ETH_MTLESTGCLCR_R1W0_Pos) /*!< 0x00000002 */
+#define ETH_MTLESTGCLCR_R1W0                           ETH_MTLESTGCLCR_R1W0_Msk /* Read 1, Write 0 */
+#define ETH_MTLESTGCLCR_SRWO_Pos                       (0U)
+#define ETH_MTLESTGCLCR_SRWO_Msk                       (0x1UL << ETH_MTLESTGCLCR_SRWO_Pos) /*!< 0x00000001 */
+#define ETH_MTLESTGCLCR_SRWO                           ETH_MTLESTGCLCR_SRWO_Msk /* Start Read/Write Operation */
+
+/************ Bit definition for Ethernet MTL EST Gate Control List Data Register   ***************/
+#define ETH_MTLESTGCLDR_GCD_Pos                        (0U)
+#define ETH_MTLESTGCLDR_GCD_Msk                        (0xFFFFFFFFUL << ETH_MTLESTGCLDR_GCD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MTLESTGCLDR_GCD                            ETH_MTLESTGCLDR_GCD_Msk /* Gate Control Data */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Control Status Register   ***************/
+#define ETH_MTLFPECSR_HRS_Pos                          (28U)
+#define ETH_MTLFPECSR_HRS_Msk                          (0x1UL << ETH_MTLFPECSR_HRS_Pos) /*!< 0x10000000 */
+#define ETH_MTLFPECSR_HRS                              ETH_MTLFPECSR_HRS_Msk /* Hold/Release Status */
+#define ETH_MTLFPECSR_PEC_Pos                          (8U)
+#define ETH_MTLFPECSR_PEC_Msk                          (0x3UL << ETH_MTLFPECSR_PEC_Pos) /*!< 0x00000300 */
+#define ETH_MTLFPECSR_PEC                              ETH_MTLFPECSR_PEC_Msk /* Preemption Classification */
+#define ETH_MTLFPECSR_AFSZ_Pos                         (0U)
+#define ETH_MTLFPECSR_AFSZ_Msk                         (0x3UL << ETH_MTLFPECSR_AFSZ_Pos) /*!< 0x00000003 */
+#define ETH_MTLFPECSR_AFSZ                             ETH_MTLFPECSR_AFSZ_Msk /* Additional Fragment Size */
+
+/************ Bit definition for Ethernet MTL FPE Frame Preemption Advance Register   ***************/
+#define ETH_MTLFPEAR_RADV_Pos                          (16U)
+#define ETH_MTLFPEAR_RADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_RADV_Pos) /*!< 0xFFFF0000 */
+#define ETH_MTLFPEAR_RADV                              ETH_MTLFPEAR_RADV_Msk /* Release Advance */
+#define ETH_MTLFPEAR_HADV_Pos                          (0U)
+#define ETH_MTLFPEAR_HADV_Msk                          (0xFFFFUL << ETH_MTLFPEAR_HADV_Pos) /*!< 0x0000FFFF */
+#define ETH_MTLFPEAR_HADV                              ETH_MTLFPEAR_HADV_Msk /* Hold Advance */
+
+/************ Bit definition for Ethernet MTL Tx queue x operating mode Register   ***************/
+#define ETH_MTLTXQxOMR_TQS_Pos                          (16U)
+#define ETH_MTLTXQxOMR_TQS_Msk                          (0xFUL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x000F0000 */
+#define ETH_MTLTXQxOMR_TQS                              ETH_MTLTXQxOMR_TQS_Msk     /* Transmit queue size */
+#define ETH_MTLTXQxOMR_TQS_0                            (0x1UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00010000 */
+#define ETH_MTLTXQxOMR_TQS_1                            (0x2UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00020000 */
+#define ETH_MTLTXQxOMR_TQS_2                            (0x4UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00040000 */
+#define ETH_MTLTXQxOMR_TQS_3                            (0x8UL << ETH_MTLTXQxOMR_TQS_Pos)                /*!< 0x00080000 */
+#define ETH_MTLTXQxOMR_TTC_Pos                          (4U)
+#define ETH_MTLTXQxOMR_TTC_Msk                          (0x7UL << ETH_MTLTXQxOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQxOMR_TTC                              ETH_MTLTXQxOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTXQxOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTXQxOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTXQxOMR_TXQEN_Pos                        (2U)
+#define ETH_MTLTXQxOMR_TXQEN_Msk                        (0x3UL << ETH_MTLTXQxOMR_TXQEN_Pos) /*!< 0x0000000C */
+#define ETH_MTLTXQxOMR_TXQEN                            ETH_MTLTXQxOMR_TXQEN_Msk     /* Transmit Queue Enable */
+#define ETH_MTLTXQxOMR_TXQEN_NOT                        ((uint32_t)0x00000000)   /* Not enabled */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos                 (2U)
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk                 (0x1UL << ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQxOMR_TXQEN_AVMODE                     ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk     /* Enable in AV mode */
+#define ETH_MTLTXQxOMR_TXQEN_EN_Pos                     (3U)
+#define ETH_MTLTXQxOMR_TXQEN_EN_Msk                     (0x1UL << ETH_MTLTXQxOMR_TXQEN_EN_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxOMR_TXQEN_EN                         ETH_MTLTXQxOMR_TXQEN_EN_Msk     /* Enabled */
+#define ETH_MTLTXQxOMR_TSF_Pos                          (1U)
+#define ETH_MTLTXQxOMR_TSF_Msk                          (0x1UL << ETH_MTLTXQxOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQxOMR_TSF                              ETH_MTLTXQxOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTXQxOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTXQxOMR_FTQ_Msk                          (0x1UL << ETH_MTLTXQxOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxOMR_FTQ                              ETH_MTLTXQxOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Underflow Register   ***************/
+#define ETH_MTLTXQxUR_UFCNTOVF_Pos                     (11U)
+#define ETH_MTLTXQxUR_UFCNTOVF_Msk                     (0x1UL << ETH_MTLTXQxUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQxUR_UFCNTOVF                         ETH_MTLTXQxUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTXQxUR_UFPKTCNT_Pos                     (0U)
+#define ETH_MTLTXQxUR_UFPKTCNT_Msk                     (0x7FFUL << ETH_MTLTXQxUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTXQxUR_UFPKTCNT                         ETH_MTLTXQxUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Tx Queue x Debug Register   ***************/
+#define ETH_MTLTXQxDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTXQxDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTXQxDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTXQxDR_STXSTSF                           ETH_MTLTXQxDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTXQxDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTXQxDR_PTXQ_Msk                          (0x7UL << ETH_MTLTXQxDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTXQxDR_PTXQ                              ETH_MTLTXQxDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTXQxDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTXQxDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTXQxDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQxDR_TXSTSFSTS                         ETH_MTLTXQxDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTXQxDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTXQxDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQxDR_TXQSTS                            ETH_MTLTXQxDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTXQxDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTXQxDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTXQxDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQxDR_TWCSTS                            ETH_MTLTXQxDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTXQxDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTXQxDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTXQxDR_TRCSTS                            ETH_MTLTXQ0DR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTXQxDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTXQxDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTXQxDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTXQxDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTXQxDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTXQxDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTXQxDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQxDR_TXQPAUSED                         ETH_MTLTXQxDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/************ Bit definition for Ethernet MTL Tx queue x ETS status Register   ***************/
+#define ETH_MTLTXQxESR_ABS_Pos                       (0U)
+#define ETH_MTLTXQxESR_ABS_Msk                       (0xFFFFFFUL << ETH_MTLTXQxESR_ABS_Pos) /*!< 0x00FFFFFF */
+#define ETH_MTLTXQxESR_ABS                           ETH_MTLTXQxESR_ABS_Msk  /* Average Bits per Slot */
+
+/************ Bit definition for Ethernet MTL Tx queue 0 quantum weight Register   ***************/
+#define ETH_MTLTXQ0QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ0QWR_ISCQW_Msk                       (0x7FUL << ETH_MTLTXQ0QWR_ISCQW_Pos) /*!< 0x0000007F */
+#define ETH_MTLTXQ0QWR_ISCQW                           ETH_MTLTXQ0QWR_ISCQW_Msk  /* Weights */
+
+/************ Bit definition for Ethernet MTL Queue x Interrupt Control Status Register   ***************/
+#define ETH_MTLQxICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQxICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQxICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQxICSR_RXOIE                            ETH_MTLQxICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQxICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQxICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQxICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQxICSR_RXOVFIS                          ETH_MTLQxICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQxICSR_ABPSIE_Pos                       (9U)
+#define ETH_MTLQxICSR_ABPSIE_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIE_Pos) /*!< 0x00000200 */
+#define ETH_MTLQxICSR_ABPSIE                           ETH_MTLQxICSR_ABPSIE_Msk   /* Average Bits Per Slot Interrupt Enable */
+#define ETH_MTLQxICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQxICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQxICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQxICSR_TXUIE                            ETH_MTLQxICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQxICSR_ABPSIS_Pos                       (1U)
+#define ETH_MTLQxICSR_ABPSIS_Msk                       (0x1UL << ETH_MTLQxICSR_ABPSIS_Pos) /*!< 0x00000002 */
+#define ETH_MTLQxICSR_ABPSIS                           ETH_MTLQxICSR_ABPSIS_Msk /* Average Bits Per Slot Interrupt Status */
+#define ETH_MTLQxICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQxICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQxICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQxICSR_TXUNFIS                          ETH_MTLQxICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Operation Mode Register   ***************/
+#define ETH_MTLRXQxOMR_RQS_Pos                          (20U)
+#define ETH_MTLRXQxOMR_RQS_Msk                          (0xFUL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00F00000 */
+#define ETH_MTLRXQxOMR_RQS                              ETH_MTLRXQxOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRXQxOMR_RQS_0                            (0x1UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00100000 */
+#define ETH_MTLRXQxOMR_RQS_1                            (0x2UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00200000 */
+#define ETH_MTLRXQxOMR_RQS_2                            (0x4UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00400000 */
+#define ETH_MTLRXQxOMR_RQS_3                            (0x8UL << ETH_MTLRXQxOMR_RQS_Pos)               /*!< 0x00800000 */
+#define ETH_MTLRXQxOMR_RFD_Pos                          (14U)
+#define ETH_MTLRXQxOMR_RFD_Msk                          (0x7UL << ETH_MTLRXQxOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRXQxOMR_RFD                              ETH_MTLRXQxOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRXQxOMR_RFA_Pos                          (8U)
+#define ETH_MTLRXQxOMR_RFA_Msk                          (0x7UL << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRXQxOMR_RFA                              ETH_MTLRXQxOMR_RFA_Pos /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRXQxOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRXQxOMR_EHFC_Msk                         (0x1UL << ETH_MTLRXQxOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQxOMR_EHFC                             ETH_MTLRXQxOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRXQxOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRXQxOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRXQxOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQxOMR_DISTCPEF                         ETH_MTLRXQxOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRXQxOMR_RSF_Pos                          (5U)
+#define ETH_MTLRXQxOMR_RSF_Msk                          (0x1UL << ETH_MTLRXQxOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxOMR_RSF                              ETH_MTLRXQxOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRXQxOMR_FEP_Pos                          (4U)
+#define ETH_MTLRXQxOMR_FEP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxOMR_FEP                              ETH_MTLRXQxOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRXQxOMR_FUP_Pos                          (3U)
+#define ETH_MTLRXQxOMR_FUP_Msk                          (0x1UL << ETH_MTLRXQxOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxOMR_FUP                              ETH_MTLRXQxOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRXQxOMR_RTC_Pos                          (0U)
+#define ETH_MTLRXQxOMR_RTC_Msk                          (0x3UL << ETH_MTLRXQxOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRXQxOMR_RTC                              ETH_MTLRXQxOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRXQxOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRXQxOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Missed Packet Overflow Cnt Register   ***************/
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRXQxMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQxMPOCR_MISCNTOVF                      ETH_MTLRXQxMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRXQxMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRXQxMPOCR_MISPKTCNT                      ETH_MTLRXQxMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRXQxMPOCR_OVFCNTOVF                      ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRXQxMPOCR_OVFPKTCNT                      ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Debug Register   ***************/
+#define ETH_MTLRXQxDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRXQxDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRXQxDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRXQxDR_PRXQ                              ETH_MTLRXQxDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRXQxDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRXQxDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS                            ETH_MTLRXQxDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRXQxDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRXQxDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRXQxDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQxDR_RXQSTS_FULL                       ETH_MTLRXQxDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRXQxDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRXQxDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRXQxDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS                            ETH_MTLRXQxDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRXQxDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS              ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQxDR_RRCSTS_FLUSHING                   ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRXQxDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRXQxDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRXQxDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQxDR_RWCSTS                            ETH_MTLRXQxDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/************ Bit definition for Ethernet MTL Rx Queue x Control Register   ***************/
+#define ETH_MTLRXQxCR_RQPA_Pos                          (3U)
+#define ETH_MTLRXQxCR_RQPA_Msk                          (0x1UL << ETH_MTLRXQxCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQxCR_RQPA                              ETH_MTLRXQxCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRXQxCR_RQW_Pos                           (0U)
+#define ETH_MTLRXQxCR_RQW_Msk                           (0x7UL << ETH_MTLRXQxCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRXQxCR_RQW                               ETH_MTLRXQxCR_RQW_Msk      /* Receive Queue Weight */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 ETS control Register   ***************/
+#define ETH_MTLTXQ1ECR_SLC_Pos                         (4U)
+#define ETH_MTLTXQ1ECR_SLC_Msk                         (0x7UL << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQ1ECR_SLC                             ETH_MTLTXQ1ECR_SLC_Msk     /* Slot Count */
+#define ETH_MTLTXQ1ECR_SLC_1SLOT                       ((uint32_t)0x00000000)   /* 1 Slot */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_2SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_2SLOT_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1ECR_SLC_2SLOT                       ETH_MTLTXQ1ECR_SLC_2SLOT_Msk     /* 2 Slots */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Pos                   (5U)
+#define ETH_MTLTXQ1ECR_SLC_4SLOT_Msk                   (0x1UL << ETH_MTLTXQ1ECR_SLC_4SLOT_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1ECR_SLC_4SLOT                       ETH_MTLTXQ1ECR_SLC_4SLOT_Msk     /* 4 Slots */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Pos                   (4U)
+#define ETH_MTLTXQ1ECR_SLC_8SLOT_Msk                   (0x3UL << ETH_MTLTXQ1ECR_SLC_8SLOT_Pos) /*!< 0x00000030 */
+#define ETH_MTLTXQ1ECR_SLC_8SLOT                       ETH_MTLTXQ1ECR_SLC_8SLOT_Msk     /* 8 Slots */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Pos                  (6U)
+#define ETH_MTLTXQ1ECR_SLC_16SLOT_Msk                  (0x1UL << ETH_MTLTXQ1ECR_SLC_16SLOT_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1ECR_SLC_16SLOT                      ETH_MTLTXQ1ECR_SLC_16SLOT_Msk     /* 16 Slots */
+#define ETH_MTLTXQ1ECR_CC_Pos                          (3U)
+#define ETH_MTLTXQ1ECR_CC_Msk                          (0x1UL << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1ECR_CC                              ETH_MTLTXQ1ECR_CC_Msk     /* Credit Control */
+#define ETH_MTLTXQ1ECR_AVALG_Pos                       (2U)
+#define ETH_MTLTXQ1ECR_AVALG_Msk                       (0x1UL << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1ECR_AVALG                           ETH_MTLTXQ1ECR_AVALG_Msk     /* Credit Control */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 quantum weight Register   ***************/
+#define ETH_MTLTXQ1QWR_ISCQW_Pos                       (0U)
+#define ETH_MTLTXQ1QWR_ISCQW_Msk                       (0x3FFFUL << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1QWR_ISCQW                           ETH_MTLTXQ1QWR_ISCQW_Msk     /* IdleSlopeCredit or Weights */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 send slope credit Register   ***************/
+#define ETH_MTLTXQ1SSCR_SSC_Pos                        (0U)
+#define ETH_MTLTXQ1SSCR_SSC_Msk                        (0x3FFFUL << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1SSCR_SSC                            ETH_MTLTXQ1SSCR_SSC_Msk     /* sendSlopeCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx Queue 1 hiCredit Register   ***************/
+#define ETH_MTLTXQ1HCR_HC_Pos                          (0U)
+#define ETH_MTLTXQ1HCR_HC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1HCR_HC                              ETH_MTLTXQ1HCR_HC_Msk     /* hiCredit Value */
+
+/************ Bit definition for Ethernet MTL Tx queue 1 loCredit Register   ***************/
+#define ETH_MTLTXQ1LCR_LC_Pos                          (0U)
+#define ETH_MTLTXQ1LCR_LC_Msk                          (0x1FFFFFFFUL << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1LCR_LC                              ETH_MTLTXQ1LCR_LC_Msk     /* loCredit Value */
+
+/************ Bit definition for Ethernet DMA Mode Register   ***************/
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk         /* Transmit priority */
+#define ETH_DMAMR_DSPW_Pos                            (8U)
+#define ETH_DMAMR_DSPW_Msk                            (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */
+#define ETH_DMAMR_DSPW                                ETH_DMAMR_DSPW_Msk         /* Descriptor Posted Write */
+#define ETH_DMAMR_TAA_Pos                             (2U)
+#define ETH_DMAMR_TAA_Msk                             (0x7UL << ETH_DMAMR_TAA_Pos) /*!< 0x000001C0 */
+#define ETH_DMAMR_TAA                                 ETH_DMAMR_TAA_Msk         /* Transmit Arbitration Algorithm */
+#define ETH_DMAMR_TAA_FP                              ((uint32_t)0x00000000)    /* Fixed priority */
+#define ETH_DMAMR_TAA_WSP_Pos                         (2U)
+#define ETH_DMAMR_TAA_WSP_Msk                         (0x1UL << ETH_DMAMR_TAA_WSP_Pos) /*!< 0x00000004 */
+#define ETH_DMAMR_TAA_WSP                             ETH_DMAMR_TAA_WSP_Msk  /* Weighted Strict priority (WSP) */
+#define ETH_DMAMR_TAA_WRR_Pos                         (3U)
+#define ETH_DMAMR_TAA_WRR_Msk                         (0x1UL << ETH_DMAMR_TAA_WRR_Pos) /*!< 0x00000008 */
+#define ETH_DMAMR_TAA_WRR                             ETH_DMAMR_TAA_WRR_Msk  /* Weighted Round-Robin (WRR) */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk  /* Software Reset */
+
+/************ Bit definition for Ethernet DMA System bus mode Register   ***************/
+#define ETH_DMASBMR_ENLPI_Pos                         (31U)
+#define ETH_DMASBMR_ENLPI_Msk                         (0x1UL << ETH_DMASBMR_ENLPI_Pos) /*!< 0x80000000 */
+#define ETH_DMASBMR_ENLPI                             ETH_DMASBMR_ENLPI_Msk       /* Enable Low Power Interface (LPI) */
+#define ETH_DMASBMR_LPIXPKT_Pos                       (30U)
+#define ETH_DMASBMR_LPIXPKT_Msk                       (0x1UL << ETH_DMASBMR_LPIXPKT_Pos) /*!< 0x40000000 */
+#define ETH_DMASBMR_LPIXPKT                           ETH_DMASBMR_LPIXPKT_Msk       /* Unlock on Magic Packet or Remote wakeup Packet */
+#define ETH_DMASBMR_WR_OSR_LMT_Pos                    (24U)
+#define ETH_DMASBMR_WR_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
+#define ETH_DMASBMR_WR_OSR_LMT                        ETH_DMASBMR_WR_OSR_LMT_Msk            /*!< AXI Maximum Write Outstanding Request Limit */
+#define ETH_DMASBMR_WR_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
+#define ETH_DMASBMR_WR_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
+#define ETH_DMASBMR_RD_OSR_LMT_Pos                    (16U)
+#define ETH_DMASBMR_RD_OSR_LMT_Msk                    (0x3UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
+#define ETH_DMASBMR_RD_OSR_LMT                        ETH_DMASBMR_RD_OSR_LMT_Msk            /*!< AXI Maximum Read Outstanding Request Limit */
+#define ETH_DMASBMR_RD_OSR_LMT_0                      (0x1UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
+#define ETH_DMASBMR_RD_OSR_LMT_1                      (0x2UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
+#define ETH_DMASBMR_ONEKBBE_Pos                       (13U)
+#define ETH_DMASBMR_ONEKBBE_Msk                       (0x1UL << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
+#define ETH_DMASBMR_ONEKBBE                           ETH_DMASBMR_ONEKBBE_Msk       /* 1 Kbyte Boundary Crossing Enable for the AXI Master */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_AALE_Pos                          (10U)
+#define ETH_DMASBMR_AALE_Msk                          (0x1UL << ETH_DMASBMR_AALE_Pos) /*!< 0x00000400 */
+#define ETH_DMASBMR_AALE                              ETH_DMASBMR_AALE_Msk       /* Automatic AXI LPI enable */
+#define ETH_DMASBMR_BLEN256_Pos                       (7U)
+#define ETH_DMASBMR_BLEN256_Msk                       (0x1UL << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
+#define ETH_DMASBMR_BLEN256                           ETH_DMASBMR_BLEN256_Msk       /* AXI Burst Length 256 */
+#define ETH_DMASBMR_BLEN128_Pos                       (6U)
+#define ETH_DMASBMR_BLEN128_Msk                       (0x1UL << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
+#define ETH_DMASBMR_BLEN128                           ETH_DMASBMR_BLEN128_Msk       /* AXI Burst Length 128 */
+#define ETH_DMASBMR_BLEN64_Pos                        (5U)
+#define ETH_DMASBMR_BLEN64_Msk                        (0x1UL << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
+#define ETH_DMASBMR_BLEN64                            ETH_DMASBMR_BLEN64_Msk       /* AXI Burst Length 64 */
+#define ETH_DMASBMR_BLEN32_Pos                        (4U)
+#define ETH_DMASBMR_BLEN32_Msk                        (0x1UL << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
+#define ETH_DMASBMR_BLEN32                            ETH_DMASBMR_BLEN32_Msk       /* AXI Burst Length 32 */
+#define ETH_DMASBMR_BLEN16_Pos                        (3U)
+#define ETH_DMASBMR_BLEN16_Msk                        (0x1UL << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
+#define ETH_DMASBMR_BLEN16                            ETH_DMASBMR_BLEN16_Msk       /* AXI Burst Length 16 */
+#define ETH_DMASBMR_BLEN8_Pos                         (2U)
+#define ETH_DMASBMR_BLEN8_Msk                         (0x1UL << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
+#define ETH_DMASBMR_BLEN8                             ETH_DMASBMR_BLEN8_Msk       /* AXI Burst Length 8 */
+#define ETH_DMASBMR_BLEN4_Pos                         (1U)
+#define ETH_DMASBMR_BLEN4_Msk                         (0x1UL << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
+#define ETH_DMASBMR_BLEN4                             ETH_DMASBMR_BLEN4_Msk       /* AXI Burst Length 4 */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/************ Bit definition for Ethernet DMA Interrupt Status Register   ***************/
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMAC1IS_Pos                        (1U)
+#define ETH_DMAISR_DMAC1IS_Msk                        (0x1UL << ETH_DMAISR_DMAC1IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC1IS                            ETH_DMAISR_DMAC1IS_Msk    /* DMA Channel 1 Interrupt Status */
+#define ETH_DMAISR_DMAC0IS_Pos                        (0U)
+#define ETH_DMAISR_DMAC0IS_Msk                        (0x1UL << ETH_DMAISR_DMAC0IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMAC0IS                            ETH_DMAISR_DMAC0IS_Msk    /* DMA Channel 0 Interrupt Status */
+
+/************ Bit definition for Ethernet DMA Debug Status Register   ***************/
+#define ETH_DMADSR_TPS1_Pos                            (20U)
+#define ETH_DMADSR_TPS1_Msk                            (0xFUL << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
+#define ETH_DMADSR_TPS1                                ETH_DMADSR_TPS1_Msk       /* DMA Channel 1 Transmit Process State */
+#define ETH_DMADSR_TPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS1_FETCHING_Pos                   (20U)
+#define ETH_DMADSR_TPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS1_FETCHING_Pos) /*!< 0x00100000 */
+#define ETH_DMADSR_TPS1_FETCHING                       ETH_DMADSR_TPS1_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS1_WAITING_Pos                    (21U)
+#define ETH_DMADSR_TPS1_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS1_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_DMADSR_TPS1_WAITING                        ETH_DMADSR_TPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS1_READING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_READING_Msk                    (0x3UL << ETH_DMADSR_TPS1_READING_Pos) /*!< 0x00300000 */
+#define ETH_DMADSR_TPS1_READING                        ETH_DMADSR_TPS1_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos               (22U)
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos) /*!< 0x00400000 */
+#define ETH_DMADSR_TPS1_TIMESTAMP_WR                   ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS1_SUSPENDED_Pos                  (21U)
+#define ETH_DMADSR_TPS1_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS1_SUSPENDED_Pos) /*!< 0x00600000 */
+#define ETH_DMADSR_TPS1_SUSPENDED                      ETH_DMADSR_TPS1_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS1_CLOSING_Pos                    (20U)
+#define ETH_DMADSR_TPS1_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS1_CLOSING_Pos) /*!< 0x00700000 */
+#define ETH_DMADSR_TPS1_CLOSING                        ETH_DMADSR_TPS1_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS1_Pos                            (16U)
+#define ETH_DMADSR_RPS1_Msk                            (0xFUL << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
+#define ETH_DMADSR_RPS1                                ETH_DMADSR_RPS1_Msk       /* DMA Channel 1 Receive Process State */
+#define ETH_DMADSR_RPS1_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS1_FETCHING_Pos                   (16U)
+#define ETH_DMADSR_RPS1_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS1_FETCHING_Pos) /*!< 0x00010000 */
+#define ETH_DMADSR_RPS1_FETCHING                       ETH_DMADSR_RPS1_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS1_WAITING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS1_WAITING_Pos) /*!< 0x00030000 */
+#define ETH_DMADSR_RPS1_WAITING                        ETH_DMADSR_RPS1_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS1_SUSPENDED_Pos                  (18U)
+#define ETH_DMADSR_RPS1_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS1_SUSPENDED_Pos) /*!< 0x00040000 */
+#define ETH_DMADSR_RPS1_SUSPENDED                      ETH_DMADSR_RPS1_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS1_CLOSING_Pos                    (16U)
+#define ETH_DMADSR_RPS1_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS1_CLOSING_Pos) /*!< 0x00050000 */
+#define ETH_DMADSR_RPS1_CLOSING                        ETH_DMADSR_RPS1_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos               (17U)
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos) /*!< 0x00060000 */
+#define ETH_DMADSR_RPS1_TIMESTAMP_WR                   ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS1_TRANSFERRING_Pos               (16U)
+#define ETH_DMADSR_RPS1_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS1_TRANSFERRING_Pos) /*!< 0x00070000 */
+#define ETH_DMADSR_RPS1_TRANSFERRING                   ETH_DMADSR_RPS1_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_TPS0_Pos                            (12U)
+#define ETH_DMADSR_TPS0_Msk                            (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS0                                ETH_DMADSR_TPS0_Msk       /* DMA Channel 0 Transmit Process State */
+#define ETH_DMADSR_TPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS0_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS0_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS0_FETCHING                       ETH_DMADSR_TPS0_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS0_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS0_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS0_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS0_WAITING                        ETH_DMADSR_TPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS0_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_READING_Msk                    (0x3UL << ETH_DMADSR_TPS0_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS0_READING                        ETH_DMADSR_TPS0_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS0_TIMESTAMP_WR                   ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS0_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS0_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS0_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS0_SUSPENDED                      ETH_DMADSR_TPS0_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS0_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS0_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS0_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS0_CLOSING                        ETH_DMADSR_TPS0_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS0_Pos                            (8U)
+#define ETH_DMADSR_RPS0_Msk                            (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS0                                ETH_DMADSR_RPS0_Msk       /* DMA Channel 0 Receive Process State */
+#define ETH_DMADSR_RPS0_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS0_FETCHING_Pos                   (8U)
+#define ETH_DMADSR_RPS0_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS0_FETCHING_Pos) /*!< 0x00000100 */
+#define ETH_DMADSR_RPS0_FETCHING                       ETH_DMADSR_RPS0_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS0_WAITING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS0_WAITING_Pos) /*!< 0x00000300 */
+#define ETH_DMADSR_RPS0_WAITING                        ETH_DMADSR_RPS0_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS0_SUSPENDED_Pos                  (10U)
+#define ETH_DMADSR_RPS0_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS0_SUSPENDED_Pos) /*!< 0x00000400 */
+#define ETH_DMADSR_RPS0_SUSPENDED                      ETH_DMADSR_RPS0_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS0_CLOSING_Pos                    (8U)
+#define ETH_DMADSR_RPS0_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS0_CLOSING_Pos) /*!< 0x00000500 */
+#define ETH_DMADSR_RPS0_CLOSING                        ETH_DMADSR_RPS0_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos               (9U)
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos) /*!< 0x00000600 */
+#define ETH_DMADSR_RPS0_TIMESTAMP_WR                   ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS0_TRANSFERRING_Pos               (8U)
+#define ETH_DMADSR_RPS0_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS0_TRANSFERRING_Pos) /*!< 0x00000700 */
+#define ETH_DMADSR_RPS0_TRANSFERRING                   ETH_DMADSR_RPS0_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+#define ETH_DMADSR_AXRHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXRHSTS_Msk                         (0x1UL << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
+#define ETH_DMADSR_AXRHSTS                             ETH_DMADSR_AXRHSTS_Msk /* AXI Master Read Channel Status */
+#define ETH_DMADSR_AXWHSTS_Pos                         (1U)
+#define ETH_DMADSR_AXWHSTS_Msk                         (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
+#define ETH_DMADSR_AXWHSTS                             ETH_DMADSR_AXWHSTS_Msk /* AXI Master Write Channel */
+
+/************ Bit definition for Ethernet DMA AXI4 transmit channel ACE control Register   ***************/
+#define ETH_DMAA4TXACR_THC_Pos                         (16U)
+#define ETH_DMAA4TXACR_THC_Msk                         (0xFUL << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4TXACR_THC                             ETH_DMAA4TXACR_THC_Msk       /* Transmit DMA First Packet Buffer or TSO Header Cache Control */
+#define ETH_DMAA4TXACR_TEC_Pos                         (8U)
+#define ETH_DMAA4TXACR_TEC_Msk                         (0xFUL << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4TXACR_TEC                             ETH_DMAA4TXACR_TEC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+#define ETH_DMAA4TXACR_TDRC_Pos                        (0U)
+#define ETH_DMAA4TXACR_TDRC_Msk                        (0xFUL << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4TXACR_TDRC                            ETH_DMAA4TXACR_TDRC_Msk       /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 receive channel ACE control Register   ***************/
+#define ETH_DMAA4RXACR_RDC_Pos                         (24U)
+#define ETH_DMAA4RXACR_RDC_Msk                         (0xFUL << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
+#define ETH_DMAA4RXACR_RDC                             ETH_DMAA4RXACR_RDC_Msk       /* Receive DMA Buffer Cache Control */
+#define ETH_DMAA4RXACR_RHC_Pos                         (16U)
+#define ETH_DMAA4RXACR_RHC_Msk                         (0xFUL << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4RXACR_RHC                             ETH_DMAA4RXACR_RHC_Msk       /* Receive DMA Header Cache Control */
+#define ETH_DMAA4RXACR_RPC_Pos                         (8U)
+#define ETH_DMAA4RXACR_RPC_Msk                         (0xFUL << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4RXACR_RPC                             ETH_DMAA4RXACR_RPC_Msk       /* Receive DMA Payload Cache Control */
+#define ETH_DMAA4RXACR_RDWC_Pos                        (0U)
+#define ETH_DMAA4RXACR_RDWC_Msk                        (0xFUL << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4RXACR_RDWC                            ETH_DMAA4RXACR_RDWC_Msk   /* Receive DMA Write Descriptor Cache Control */
+
+/************ Bit definition for Ethernet DMA AXI4 descriptor ACE control Register   ***************/
+#define ETH_DMAA4DACR_RDRC_Pos                         (8U)
+#define ETH_DMAA4DACR_RDRC_Msk                         (0xFUL << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4DACR_RDRC                             ETH_DMAA4DACR_RDRC_Msk       /* Receive DMA Read Descriptor Cache control */
+#define ETH_DMAA4DACR_TDWD_Pos                         (4U)
+#define ETH_DMAA4DACR_TDWD_Msk                         (0xFUL << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
+#define ETH_DMAA4DACR_TDWD                             ETH_DMAA4DACR_TDWD_Msk       /* Transmit DMA Write Descriptor Domain control */
+#define ETH_DMAA4DACR_TDWC_Pos                         (0U)
+#define ETH_DMAA4DACR_TDWC_Msk                         (0xFUL << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4DACR_TDWC                             ETH_DMAA4DACR_TDWC_Msk       /* Transmit DMA Write Descriptor Cache control */
+
+/************ Bit definition for Ethernet DMA AXI4 LPI Entry Interval Register   ***************/
+/* Bit definition for Ethernet DMA AXI4 LPI Entry Interval register */
+#define ETH_DMALPIEI_LPIEI_Pos                         (0U)
+#define ETH_DMALPIEI_LPIEI_Msk                         (0xFUL << ETH_DMALPIEI_LPIEI_Pos) /*!< 0x0000000F */
+#define ETH_DMALPIEI_LPIEI                             ETH_DMALPIEI_LPIEI_Msk   /* LPI Entry Interval */
+
+/************ Bit definition for Ethernet DMA TBS control Register   ***************/
+#define ETH_DMATBSCTRL0R_FTOS_Pos                      (8U)
+#define ETH_DMATBSCTRL0R_FTOS_Msk                      (0xFFFFFFUL << ETH_DMATBSCTRL0R_FTOS_Pos) /*!< 0xFFFFFF00 */
+#define ETH_DMATBSCTRL0R_FTOS                          ETH_DMATBSCTRL0R_FTOS_Msk   /* Fetch time offset */
+#define ETH_DMATBSCTRL0R_FGOS_Pos                      (4U)
+#define ETH_DMATBSCTRL0R_FGOS_Msk                      (0x7UL << ETH_DMATBSCTRL0R_FGOS_Pos) /*!< 0x00000070 */
+#define ETH_DMATBSCTRL0R_FGOS                          ETH_DMATBSCTRL0R_FGOS_Msk   /* Fetch GSN offset */
+#define ETH_DMATBSCTRL0R_FTOV_Pos                      (0U)
+#define ETH_DMATBSCTRL0R_FTOV_Msk                      (0x1UL << ETH_DMATBSCTRL0R_FTOV_Pos) /*!< 0x00000001 */
+#define ETH_DMATBSCTRL0R_FTOV                          ETH_DMATBSCTRL0R_FTOV_Msk   /* Fetch time offset valid */
+
+/************ Bit definition for Ethernet DMA Channel x Control Register   ***************/
+#define ETH_DMACxCR_DSL_Pos                            (18U)
+#define ETH_DMACxCR_DSL_Msk                            (0x7UL << ETH_DMACxCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACxCR_DSL                                ETH_DMACxCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACxCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACxCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACxCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACxCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACxCR_PBLX8_Pos                          (16U)
+#define ETH_DMACxCR_PBLX8_Msk                          (0x1UL << ETH_DMACxCR_PBLX8_Pos) /*!< 0x00010000 */
+#define ETH_DMACxCR_PBLX8                              ETH_DMACxCR_PBLX8_Msk  /* 8xPBL mode */
+#define ETH_DMACxCR_MSS_Pos                            (0U)
+#define ETH_DMACxCR_MSS_Msk                            (0x3FFFUL << ETH_DMACxCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACxCR_MSS                                ETH_DMACxCR_MSS_Msk       /* Maximum Segment Size */
+
+/************ Bit definition for Ethernet DMA Channel x transmit control Register   ***************/
+#define ETH_DMACxTXCR_EDSE_Pos                         (28U)
+#define ETH_DMACxTXCR_EDSE_Msk                         (0x1UL << ETH_DMACxTXCR_EDSE_Pos) /*!< 0x10000000 */
+#define ETH_DMACxTXCR_EDSE                             ETH_DMACxTXCR_EDSE_Msk       /* Enhanced Descriptor Enable */
+#define ETH_DMACxTXCR_TQOS_Pos                         (24U)
+#define ETH_DMACxTXCR_TQOS_Msk                         (0xFUL << ETH_DMACxTXCR_TQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxTXCR_TQOS                             ETH_DMACxTXCR_TQOS_Msk       /* Transmit QOS */
+#define ETH_DMACxTXCR_TXPBL_Pos                        (16U)
+#define ETH_DMACxTXCR_TXPBL_Msk                        (0x3FUL << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxTXCR_TXPBL                            ETH_DMACxTXCR_TXPBL_Msk       /* Transmit Programmable Burst Length */
+#define ETH_DMACxTXCR_TXPBL_1PBL                       (0x1U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00010000 */
+#define ETH_DMACxTXCR_TXPBL_2PBL                       (0x2U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00020000 */
+#define ETH_DMACxTXCR_TXPBL_4PBL                       (0x4U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00040000 */
+#define ETH_DMACxTXCR_TXPBL_8PBL                       (0x8U << ETH_DMACxTXCR_TXPBL_Pos)                   /*!< 0x00080000 */
+#define ETH_DMACxTXCR_TXPBL_16PBL                      (0x10U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00100000 */
+#define ETH_DMACxTXCR_TXPBL_32PBL                      (0x20U << ETH_DMACxTXCR_TXPBL_Pos)                  /*!< 0x00200000 */
+#define ETH_DMACxTXCR_IPBL_Pos                         (15U)
+#define ETH_DMACxTXCR_IPBL_Msk                         (0x1UL << ETH_DMACxTXCR_IPBL_Pos) /*!< 0x00008000 */
+#define ETH_DMACxTXCR_IPBL                             ETH_DMACxTXCR_IPBL_Msk       /* Ignore PBL Requirement */
+#define ETH_DMACxTXCR_TSE_Pos                          (12U)
+#define ETH_DMACxTXCR_TSE_Msk                          (0x1UL << ETH_DMACxTXCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxTXCR_TSE                              ETH_DMACxTXCR_TSE_Msk       /* TCP Segmentation Enabled */
+#define ETH_DMACxTXCR_OSF_Pos                          (4U)
+#define ETH_DMACxTXCR_OSF_Msk                          (0x1UL << ETH_DMACxTXCR_OSF_Pos) /*!< 0x00000010 */
+#define ETH_DMACxTXCR_OSF                              ETH_DMACxTXCR_OSF_Msk       /* Operate on Second Packet */
+#define ETH_DMACxTXCR_TCW_Pos                          (1U)
+#define ETH_DMACxTXCR_TCW_Msk                          (0x7UL << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000E */
+#define ETH_DMACxTXCR_TCW                              ETH_DMACxTXCR_TCW_Msk       /* Transmit Channel Weight */
+#define ETH_DMACxTXCR_TCW_1                            (0x1U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000002 */
+#define ETH_DMACxTXCR_TCW_2                            (0x2U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000004 */
+#define ETH_DMACxTXCR_TCW_3                            (0x3U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000006 */
+#define ETH_DMACxTXCR_TCW_4                            (0x4U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x00000008 */
+#define ETH_DMACxTXCR_TCW_5                            (0x5U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000A */
+#define ETH_DMACxTXCR_TCW_6                            (0x6U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000C */
+#define ETH_DMACxTXCR_TCW_7                            (0x7U << ETH_DMACxTXCR_TCW_Pos)  /*!< 0x0000000E */
+#define ETH_DMACxTXCR_ST_Pos                           (0U)
+#define ETH_DMACxTXCR_ST_Msk                           (0x1UL << ETH_DMACxTXCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACxTXCR_ST                               ETH_DMACxTXCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/************ Bit definition for Ethernet DMA Channel x receive control Register   ***************/
+#define ETH_DMACxRXCR_RPF_Pos                         (31U)
+#define ETH_DMACxRXCR_RPF_Msk                         (0x1UL << ETH_DMACxRXCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACxRXCR_RPF                             ETH_DMACxRXCR_RPF_Msk       /* DMA Rx Channel Packet Flush */
+#define ETH_DMACxRXCR_RQOS_Pos                        (24U)
+#define ETH_DMACxRXCR_RQOS_Msk                        (0xFUL << ETH_DMACxRXCR_RQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMACxRXCR_RQOS                            ETH_DMACxRXCR_RQOS_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_Pos                       (16U)
+#define ETH_DMACxRXCR_RXPBL_Msk                       (0x3FUL << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACxRXCR_RXPBL                           ETH_DMACxRXCR_RXPBL_Msk       /* Rx AXI4 QOS */
+#define ETH_DMACxRXCR_RXPBL_1PBL                      (0x1U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00010000 */
+#define ETH_DMACxRXCR_RXPBL_2PBL                      (0x2U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00020000 */
+#define ETH_DMACxRXCR_RXPBL_4PBL                      (0x4U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00040000 */
+#define ETH_DMACxRXCR_RXPBL_8PBL                      (0x8U << ETH_DMACxRXCR_RXPBL_Pos)     /*!< 0x00080000 */
+#define ETH_DMACxRXCR_RXPBL_16PBL                     (0x10U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00100000 */
+#define ETH_DMACxRXCR_RXPBL_32PBL                     (0x20U << ETH_DMACxRXCR_RXPBL_Pos)    /*!< 0x00200000 */
+#define ETH_DMACxRXCR_RBSZ_Pos                        (1U)
+#define ETH_DMACxRXCR_RBSZ_Msk                        (0x1FFFUL << ETH_DMACxRXCR_RBSZ_Pos) /*!< 0x00003FFE */
+#define ETH_DMACxRXCR_RBSZ                            ETH_DMACxRXCR_RBSZ_Msk       /* Receive Buffer size */
+#define ETH_DMACxRXCR_SR_Pos                          (0U)
+#define ETH_DMACxRXCR_SR_Msk                          (0x1UL << ETH_DMACxRXCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACxRXCR_SR                              ETH_DMACxRXCR_SR_Msk       /* Start or Stop Receive */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor list address Register   ***************/
+#define ETH_DMACxTXDLAR_TDESLA_Pos                    (0U)
+#define ETH_DMACxTXDLAR_TDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDLAR_TDESLA                        ETH_DMACxTXDLAR_TDESLA_Msk   /* Start of Transmit List */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor list address Register   ***************/
+#define ETH_DMACxRXDLAR_RDESLA_Pos                    (0U)
+#define ETH_DMACxRXDLAR_RDESLA_Msk                    (0xFFFFFFFFUL << ETH_DMACxRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDLAR_RDESLA                        ETH_DMACxRXDLAR_RDESLA_Msk   /* Start of Receive List */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor tail pointer Register   ***************/
+#define ETH_DMACxTXDTPR_TDT_Pos                       (0U)
+#define ETH_DMACxTXDTPR_TDT_Msk                       (0xFFFFFFFFUL << ETH_DMACxTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxTXDTPR_TDT                           ETH_DMACxTXDTPR_TDT_Msk   /* Transmit Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor tail pointer Register   ***************/
+#define ETH_DMACxRXDTPR_TDT_Pos                      (0U)
+#define ETH_DMACxRXDTPR_TDT_Msk                      (0xFFFFFFFFUL << ETH_DMACxRXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxRXDTPR_TDT                          ETH_DMACxRXDTPR_TDT_Msk   /* Receive Descriptor Tail Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Tx descriptor ring length Register   ***************/
+#define ETH_DMACxTXRLR_TDRL_Pos                       (0U)
+#define ETH_DMACxTXRLR_TDRL_Msk                       (0x3FFUL << ETH_DMACxTXRLR_TDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxTXRLR_TDRL                           ETH_DMACxTXRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Rx descriptor ring length Register   ***************/
+#define ETH_DMACxRXRLR_ARBS_Pos                       (17U)
+#define ETH_DMACxRXRLR_ARBS_Msk                       (0x7FUL << ETH_DMACxRXRLR_ARBS_Pos) /*!< 0x000FE0000 */
+#define ETH_DMACxRXRLR_ARBS                           ETH_DMACxRXRLR_ARBS_Msk   /* Alternate Receive Buffer Size */
+#define ETH_DMACxRXRLR_RDRL_Pos                       (0U)
+#define ETH_DMACxRXRLR_RDRL_Msk                       (0x3FFUL << ETH_DMACxRXRLR_RDRL_Pos) /*!< 0x0000003FF */
+#define ETH_DMACxRXRLR_RDRL                           ETH_DMACxRXRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/************ Bit definition for Ethernet DMA Channel x Interrupt Enable Register   ***************/
+#define ETH_DMACxIER_NIE_Pos                           (15U)
+#define ETH_DMACxIER_NIE_Msk                           (0x1UL << ETH_DMACxIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACxIER_NIE                               ETH_DMACxIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACxIER_AIE_Pos                           (14U)
+#define ETH_DMACxIER_AIE_Msk                           (0x1UL << ETH_DMACxIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACxIER_AIE                               ETH_DMACxIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACxIER_CDEE_Pos                          (13U)
+#define ETH_DMACxIER_CDEE_Msk                          (0x1UL << ETH_DMACxIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxIER_CDEE                              ETH_DMACxIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACxIER_FBEE_Pos                          (12U)
+#define ETH_DMACxIER_FBEE_Msk                          (0x1UL << ETH_DMACxIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxIER_FBEE                              ETH_DMACxIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACxIER_ERIE_Pos                          (11U)
+#define ETH_DMACxIER_ERIE_Msk                          (0x1UL << ETH_DMACxIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACxIER_ERIE                              ETH_DMACxIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACxIER_ETIE_Pos                          (10U)
+#define ETH_DMACxIER_ETIE_Msk                          (0x1UL << ETH_DMACxIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACxIER_ETIE                              ETH_DMACxIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACxIER_RWTE_Pos                          (9U)
+#define ETH_DMACxIER_RWTE_Msk                          (0x1UL << ETH_DMACxIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACxIER_RWTE                              ETH_DMACxIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACxIER_RSE_Pos                           (8U)
+#define ETH_DMACxIER_RSE_Msk                           (0x1UL << ETH_DMACxIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACxIER_RSE                               ETH_DMACxIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACxIER_RBUE_Pos                          (7U)
+#define ETH_DMACxIER_RBUE_Msk                          (0x1UL << ETH_DMACxIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACxIER_RBUE                              ETH_DMACxIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACxIER_RIE_Pos                           (6U)
+#define ETH_DMACxIER_RIE_Msk                           (0x1UL << ETH_DMACxIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACxIER_RIE                               ETH_DMACxIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACxIER_TBUE_Pos                          (2U)
+#define ETH_DMACxIER_TBUE_Msk                          (0x1UL << ETH_DMACxIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACxIER_TBUE                              ETH_DMACxIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACxIER_TXSE_Pos                          (1U)
+#define ETH_DMACxIER_TXSE_Msk                          (0x1UL << ETH_DMACxIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACxIER_TXSE                              ETH_DMACxIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACxIER_TIE_Pos                           (0U)
+#define ETH_DMACxIER_TIE_Msk                           (0x1UL << ETH_DMACxIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACxIER_TIE                               ETH_DMACxIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/************ Bit definition for Ethernet DMA Channel x Rx Interrupt Watchdog Timer Register   ***************/
+#define ETH_DMACxRXIWTR_RWTU_Pos                        (16U)
+#define ETH_DMACxRXIWTR_RWTU_Msk                        (0x3UL << ETH_DMACxRXIWTR_RWTU_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU                            ETH_DMACxRXIWTR_RWTU_Msk    /* Receive Interrupt Watchdog Timer Count Units */
+#define ETH_DMACxRXIWTR_RWTU_256                        ((uint32_t)0x00000000)   /* 256 */
+#define ETH_DMACxRXIWTR_RWTU_512_Pos                    (16U)
+#define ETH_DMACxRXIWTR_RWTU_512_Msk                    (0x1UL << ETH_DMACxRXIWTR_RWTU_512_Pos) /*!< 0x00010000 */
+#define ETH_DMACxRXIWTR_RWTU_512                        ETH_DMACxRXIWTR_RWTU_512_Msk    /* 512 */
+#define ETH_DMACxRXIWTR_RWTU_1024_Pos                   (17U)
+#define ETH_DMACxRXIWTR_RWTU_1024_Msk                   (0x1UL << ETH_DMACxRXIWTR_RWTU_1024_Pos) /*!< 0x00020000 */
+#define ETH_DMACxRXIWTR_RWTU_1024                       ETH_DMACxRXIWTR_RWTU_1024_Msk    /* 1024 */
+#define ETH_DMACxRXIWTR_RWTU_2048_Pos                   (16U)
+#define ETH_DMACxRXIWTR_RWTU_2048_Msk                   (0x3UL << ETH_DMACxRXIWTR_RWTU_2048_Pos) /*!< 0x00030000 */
+#define ETH_DMACxRXIWTR_RWTU_2048                       ETH_DMACxRXIWTR_RWTU_2048_Msk    /* 2048 */
+#define ETH_DMACxRXIWTR_RWT_Pos                         (0U)
+#define ETH_DMACxRXIWTR_RWT_Msk                         (0xFFUL << ETH_DMACxRXIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACxRXIWTR_RWT                             ETH_DMACxRXIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/************ Bit definition for Ethernet DMA Channel x slot function control status Register   ***************/
+#define ETH_DMACxSFCSR_RSN_Pos                        (16U)
+#define ETH_DMACxSFCSR_RSN_Msk                        (0xFUL << ETH_DMACxSFCSR_RSN_Pos) /*!< 0x000F0000 */
+#define ETH_DMACxSFCSR_RSN                            ETH_DMACxSFCSR_RSN_Msk    /* Reference Slot Number */
+#define ETH_DMACxSFCSR_SIV_Pos                        (4U)
+#define ETH_DMACxSFCSR_SIV_Msk                        (0xFFFUL << ETH_DMACxSFCSR_SIV_Pos) /*!< 0x0000FFF0 */
+#define ETH_DMACxSFCSR_SIV                            ETH_DMACxSFCSR_SIV_Msk    /* Slot Interval Value */
+#define ETH_DMACxSFCSR_ASC_Pos                        (1U)
+#define ETH_DMACxSFCSR_ASC_Msk                        (0x1UL << ETH_DMACxSFCSR_ASC_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSFCSR_ASC                            ETH_DMACxSFCSR_ASC_Msk    /* Advance Slot Check */
+#define ETH_DMACxSFCSR_ESC_Pos                        (0U)
+#define ETH_DMACxSFCSR_ESC_Msk                        (0x1UL << ETH_DMACxSFCSR_ESC_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSFCSR_ESC                            ETH_DMACxSFCSR_ESC_Msk    /* Enable Slot Comparison */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Desc Register   ***************/
+#define ETH_DMACxCATXDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACxCATXDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXDR_CURTDESAPTR                     ETH_DMACxCATXDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Desc Register   ***************/
+#define ETH_DMACxCARXDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACxCARXDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXDR_CURRDESAPTR                     ETH_DMACxCARXDR_CURRDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Tx Buffer Register   ***************/
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCATXBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCATXBR_CURTBUFAPTR                     ETH_DMACxCATXBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Current App Rx Buffer Register   ***************/
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACxCARXBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACxCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACxCARXBR_CURRBUFAPTR                     ETH_DMACxCARXBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/************ Bit definition for Ethernet DMA Channel x Status Register   ***************/
+#define ETH_DMACxSR_REB_Pos                            (19U)
+#define ETH_DMACxSR_REB_Msk                            (0x7UL << ETH_DMACxSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACxSR_REB                                ETH_DMACxSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACxSR_TEB_Pos                            (16U)
+#define ETH_DMACxSR_TEB_Msk                            (0x7UL << ETH_DMACxSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACxSR_TEB                                ETH_DMACxSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACxSR_NIS_Pos                            (15U)
+#define ETH_DMACxSR_NIS_Msk                            (0x1UL << ETH_DMACxSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACxSR_NIS                                ETH_DMACxSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACxSR_AIS_Pos                            (14U)
+#define ETH_DMACxSR_AIS_Msk                            (0x1UL << ETH_DMACxSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACxSR_AIS                                ETH_DMACxSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACxSR_CDE_Pos                            (13U)
+#define ETH_DMACxSR_CDE_Msk                            (0x1UL << ETH_DMACxSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACxSR_CDE                                ETH_DMACxSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACxSR_FBE_Pos                            (12U)
+#define ETH_DMACxSR_FBE_Msk                            (0x1UL << ETH_DMACxSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACxSR_FBE                                ETH_DMACxSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACxSR_ERI_Pos                            (11U)
+#define ETH_DMACxSR_ERI_Msk                            (0x1UL << ETH_DMACxSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACxSR_ERI                                ETH_DMACxSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACxSR_ETI_Pos                            (10U)
+#define ETH_DMACxSR_ETI_Msk                            (0x1UL << ETH_DMACxSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACxSR_ETI                                ETH_DMACxSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACxSR_RWT_Pos                            (9U)
+#define ETH_DMACxSR_RWT_Msk                            (0x1UL << ETH_DMACxSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACxSR_RWT                                ETH_DMACxSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACxSR_RPS_Pos                            (8U)
+#define ETH_DMACxSR_RPS_Msk                            (0x1UL << ETH_DMACxSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACxSR_RPS                                ETH_DMACxSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACxSR_RBU_Pos                            (7U)
+#define ETH_DMACxSR_RBU_Msk                            (0x1UL << ETH_DMACxSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACxSR_RBU                                ETH_DMACxSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACxSR_RI_Pos                             (6U)
+#define ETH_DMACxSR_RI_Msk                             (0x1UL << ETH_DMACxSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACxSR_RI                                 ETH_DMACxSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACxSR_TBU_Pos                            (2U)
+#define ETH_DMACxSR_TBU_Msk                            (0x1UL << ETH_DMACxSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACxSR_TBU                                ETH_DMACxSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACxSR_TPS_Pos                            (1U)
+#define ETH_DMACxSR_TPS_Msk                            (0x1UL << ETH_DMACxSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACxSR_TPS                                ETH_DMACxSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACxSR_TI_Pos                             (0U)
+#define ETH_DMACxSR_TI_Msk                             (0x1UL << ETH_DMACxSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACxSR_TI                                 ETH_DMACxSR_TI_Msk        /* Transmit Interrupt */
+
+/************ Bit definition for Ethernet DMA Channel x missed frame count Register   ***************/
+#define ETH_DMACxMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACxMFCR_MFCO_Msk                         (0x1UL << ETH_DMACxMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACxMFCR_MFCO                             ETH_DMACxMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACxMFCR_MFC_Pos                          (0U)
+#define ETH_DMACxMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACxMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACxMFCR_MFC                              ETH_DMACxMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_RTSR1 register  *****************/
+#define EXTI_RTSR1_RT0_Pos           (0U)
+#define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
+#define EXTI_RTSR1_RT1_Pos           (1U)
+#define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
+#define EXTI_RTSR1_RT2_Pos           (2U)
+#define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
+#define EXTI_RTSR1_RT3_Pos           (3U)
+#define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
+#define EXTI_RTSR1_RT4_Pos           (4U)
+#define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
+#define EXTI_RTSR1_RT5_Pos           (5U)
+#define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
+#define EXTI_RTSR1_RT6_Pos           (6U)
+#define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
+#define EXTI_RTSR1_RT7_Pos           (7U)
+#define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
+#define EXTI_RTSR1_RT8_Pos           (8U)
+#define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
+#define EXTI_RTSR1_RT9_Pos           (9U)
+#define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
+#define EXTI_RTSR1_RT10_Pos          (10U)
+#define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
+#define EXTI_RTSR1_RT11_Pos          (11U)
+#define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
+#define EXTI_RTSR1_RT12_Pos          (12U)
+#define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
+#define EXTI_RTSR1_RT13_Pos          (13U)
+#define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
+#define EXTI_RTSR1_RT14_Pos          (14U)
+#define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
+#define EXTI_RTSR1_RT15_Pos          (15U)
+#define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
+#define EXTI_RTSR1_RT20_Pos          (20U)
+#define EXTI_RTSR1_RT20_Msk          (0x1UL << EXTI_RTSR1_RT20_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20              EXTI_RTSR1_RT20_Msk                       /*!< Rising trigger configuration for input line 20 */
+#define EXTI_RTSR1_RT21_Pos          (21U)
+#define EXTI_RTSR1_RT21_Msk          (0x1UL << EXTI_RTSR1_RT21_Pos)            /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21              EXTI_RTSR1_RT21_Msk                       /*!< Rising trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_FTSR1 register  *****************/
+#define EXTI_FTSR1_FT0_Pos           (0U)
+#define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
+#define EXTI_FTSR1_FT1_Pos           (1U)
+#define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
+#define EXTI_FTSR1_FT2_Pos           (2U)
+#define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
+#define EXTI_FTSR1_FT3_Pos           (3U)
+#define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
+#define EXTI_FTSR1_FT4_Pos           (4U)
+#define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
+#define EXTI_FTSR1_FT5_Pos           (5U)
+#define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
+#define EXTI_FTSR1_FT6_Pos           (6U)
+#define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
+#define EXTI_FTSR1_FT7_Pos           (7U)
+#define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
+#define EXTI_FTSR1_FT8_Pos           (8U)
+#define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
+#define EXTI_FTSR1_FT9_Pos           (9U)
+#define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
+#define EXTI_FTSR1_FT10_Pos          (10U)
+#define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
+#define EXTI_FTSR1_FT11_Pos          (11U)
+#define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
+#define EXTI_FTSR1_FT12_Pos          (12U)
+#define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
+#define EXTI_FTSR1_FT13_Pos          (13U)
+#define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
+#define EXTI_FTSR1_FT14_Pos          (14U)
+#define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
+#define EXTI_FTSR1_FT15_Pos          (15U)
+#define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
+#define EXTI_FTSR1_FT20_Pos          (20U)
+#define EXTI_FTSR1_FT20_Msk          (0x1UL << EXTI_FTSR1_FT20_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20              EXTI_FTSR1_FT20_Msk                       /*!< Falling trigger configuration for input line 20 */
+#define EXTI_FTSR1_FT21_Pos          (21U)
+#define EXTI_FTSR1_FT21_Msk          (0x1UL << EXTI_FTSR1_FT21_Pos)            /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21              EXTI_FTSR1_FT21_Msk                       /*!< Falling trigger configuration for input line 21 */
+
+/*******************  Bit definition for EXTI_SWIER1 register  ****************/
+#define EXTI_SWIER1_SWI0_Pos         (0U)
+#define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos         (1U)
+#define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos         (2U)
+#define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos         (3U)
+#define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos         (4U)
+#define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos         (5U)
+#define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos         (6U)
+#define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos         (7U)
+#define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos         (8U)
+#define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos         (9U)
+#define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos        (10U)
+#define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos        (11U)
+#define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos        (12U)
+#define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos        (13U)
+#define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos        (14U)
+#define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos        (15U)
+#define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI20_Pos        (20U)
+#define EXTI_SWIER1_SWI20_Msk        (0x1UL << EXTI_SWIER1_SWI20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20            EXTI_SWIER1_SWI20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos        (21U)
+#define EXTI_SWIER1_SWI21_Msk        (0x1UL << EXTI_SWIER1_SWI21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21            EXTI_SWIER1_SWI21_Msk                     /*!< Software Interrupt on line 21 */
+
+/*******************  Bit definition for EXTI_RPR1 register  ******************/
+#define EXTI_RPR1_RPIF0_Pos          (0U)
+#define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
+#define EXTI_RPR1_RPIF1_Pos          (1U)
+#define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
+#define EXTI_RPR1_RPIF2_Pos          (2U)
+#define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
+#define EXTI_RPR1_RPIF3_Pos          (3U)
+#define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
+#define EXTI_RPR1_RPIF4_Pos          (4U)
+#define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
+#define EXTI_RPR1_RPIF5_Pos          (5U)
+#define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
+#define EXTI_RPR1_RPIF6_Pos          (6U)
+#define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
+#define EXTI_RPR1_RPIF7_Pos          (7U)
+#define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
+#define EXTI_RPR1_RPIF8_Pos          (8U)
+#define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
+#define EXTI_RPR1_RPIF9_Pos          (9U)
+#define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
+#define EXTI_RPR1_RPIF10_Pos         (10U)
+#define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
+#define EXTI_RPR1_RPIF11_Pos         (11U)
+#define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
+#define EXTI_RPR1_RPIF12_Pos         (12U)
+#define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
+#define EXTI_RPR1_RPIF13_Pos         (13U)
+#define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
+#define EXTI_RPR1_RPIF14_Pos         (14U)
+#define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
+#define EXTI_RPR1_RPIF15_Pos         (15U)
+#define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
+#define EXTI_RPR1_RPIF20_Pos         (20U)
+#define EXTI_RPR1_RPIF20_Msk         (0x1UL << EXTI_RPR1_RPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_RPR1_RPIF20             EXTI_RPR1_RPIF20_Msk                      /*!< Rising Pending Interrupt Flag on line 20 */
+#define EXTI_RPR1_RPIF21_Pos         (21U)
+#define EXTI_RPR1_RPIF21_Msk         (0x1UL << EXTI_RPR1_RPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_RPR1_RPIF21             EXTI_RPR1_RPIF21_Msk                      /*!< Rising Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_FPR1 register  ******************/
+#define EXTI_FPR1_FPIF0_Pos          (0U)
+#define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
+#define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
+#define EXTI_FPR1_FPIF1_Pos          (1U)
+#define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
+#define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
+#define EXTI_FPR1_FPIF2_Pos          (2U)
+#define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
+#define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
+#define EXTI_FPR1_FPIF3_Pos          (3U)
+#define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
+#define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
+#define EXTI_FPR1_FPIF4_Pos          (4U)
+#define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
+#define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
+#define EXTI_FPR1_FPIF5_Pos          (5U)
+#define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
+#define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
+#define EXTI_FPR1_FPIF6_Pos          (6U)
+#define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
+#define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
+#define EXTI_FPR1_FPIF7_Pos          (7U)
+#define EXTI_FPR1_FPIF7_Msk           (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
+#define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
+#define EXTI_FPR1_FPIF8_Pos          (8U)
+#define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
+#define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
+#define EXTI_FPR1_FPIF9_Pos          (9U)
+#define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
+#define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
+#define EXTI_FPR1_FPIF10_Pos         (10U)
+#define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
+#define EXTI_FPR1_FPIF11_Pos         (11U)
+#define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
+#define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
+#define EXTI_FPR1_FPIF12_Pos         (12U)
+#define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
+#define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
+#define EXTI_FPR1_FPIF13_Pos         (13U)
+#define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */
+#define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
+#define EXTI_FPR1_FPIF14_Pos         (14U)
+#define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */
+#define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
+#define EXTI_FPR1_FPIF15_Pos         (15U)
+#define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */
+#define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
+#define EXTI_FPR1_FPIF20_Pos         (20U)
+#define EXTI_FPR1_FPIF20_Msk         (0x1UL << EXTI_FPR1_FPIF20_Pos)           /*!< 0x00020000 */
+#define EXTI_FPR1_FPIF20             EXTI_FPR1_FPIF20_Msk                      /*!< Falling Pending Interrupt Flag on line 20 */
+#define EXTI_FPR1_FPIF21_Pos         (21U)
+#define EXTI_FPR1_FPIF21_Msk         (0x1UL << EXTI_FPR1_FPIF21_Pos)           /*!< 0x00040000 */
+#define EXTI_FPR1_FPIF21             EXTI_FPR1_FPIF21_Msk                      /*!< Falling Pending Interrupt Flag on line 21 */
+
+/*******************  Bit definition for EXTI_SECCFGR1 register  ******************/
+#define EXTI_SECCFGR1_SEC0_Pos       (0U)
+#define EXTI_SECCFGR1_SEC0_Msk       (0x1UL << EXTI_SECCFGR1_SEC0_Pos)         /*!< 0x00000001 */
+#define EXTI_SECCFGR1_SEC0           EXTI_SECCFGR1_SEC0_Msk                    /*!< Security enable on line 0 */
+#define EXTI_SECCFGR1_SEC1_Pos       (1U)
+#define EXTI_SECCFGR1_SEC1_Msk       (0x1UL << EXTI_SECCFGR1_SEC1_Pos)         /*!< 0x00000002 */
+#define EXTI_SECCFGR1_SEC1           EXTI_SECCFGR1_SEC1_Msk                    /*!< Security enable on line 1 */
+#define EXTI_SECCFGR1_SEC2_Pos       (2U)
+#define EXTI_SECCFGR1_SEC2_Msk       (0x1UL << EXTI_SECCFGR1_SEC2_Pos)         /*!< 0x00000004 */
+#define EXTI_SECCFGR1_SEC2           EXTI_SECCFGR1_SEC2_Msk                    /*!< Security enable on line 2 */
+#define EXTI_SECCFGR1_SEC3_Pos       (3U)
+#define EXTI_SECCFGR1_SEC3_Msk       (0x1UL << EXTI_SECCFGR1_SEC3_Pos)         /*!< 0x00000008 */
+#define EXTI_SECCFGR1_SEC3           EXTI_SECCFGR1_SEC3_Msk                    /*!< Security enable on line 3 */
+#define EXTI_SECCFGR1_SEC4_Pos       (4U)
+#define EXTI_SECCFGR1_SEC4_Msk       (0x1UL << EXTI_SECCFGR1_SEC4_Pos)         /*!< 0x00000010 */
+#define EXTI_SECCFGR1_SEC4           EXTI_SECCFGR1_SEC4_Msk                    /*!< Security enable on line 4 */
+#define EXTI_SECCFGR1_SEC5_Pos       (5U)
+#define EXTI_SECCFGR1_SEC5_Msk       (0x1UL << EXTI_SECCFGR1_SEC5_Pos)         /*!< 0x00000020 */
+#define EXTI_SECCFGR1_SEC5           EXTI_SECCFGR1_SEC5_Msk                    /*!< Security enable on line 5 */
+#define EXTI_SECCFGR1_SEC6_Pos       (6U)
+#define EXTI_SECCFGR1_SEC6_Msk       (0x1UL << EXTI_SECCFGR1_SEC6_Pos)         /*!< 0x00000040 */
+#define EXTI_SECCFGR1_SEC6           EXTI_SECCFGR1_SEC6_Msk                    /*!< Security enable on line 6 */
+#define EXTI_SECCFGR1_SEC7_Pos       (7U)
+#define EXTI_SECCFGR1_SEC7_Msk       (0x1UL << EXTI_SECCFGR1_SEC7_Pos)         /*!< 0x00000080 */
+#define EXTI_SECCFGR1_SEC7           EXTI_SECCFGR1_SEC7_Msk                    /*!< Security enable on line 7 */
+#define EXTI_SECCFGR1_SEC8_Pos       (8U)
+#define EXTI_SECCFGR1_SEC8_Msk       (0x1UL << EXTI_SECCFGR1_SEC8_Pos)         /*!< 0x00000100 */
+#define EXTI_SECCFGR1_SEC8           EXTI_SECCFGR1_SEC8_Msk                    /*!< Security enable on line 8 */
+#define EXTI_SECCFGR1_SEC9_Pos       (9U)
+#define EXTI_SECCFGR1_SEC9_Msk       (0x1UL << EXTI_SECCFGR1_SEC9_Pos)         /*!< 0x00000200 */
+#define EXTI_SECCFGR1_SEC9           EXTI_SECCFGR1_SEC9_Msk                    /*!< Security enable on line 9 */
+#define EXTI_SECCFGR1_SEC10_Pos      (10U)
+#define EXTI_SECCFGR1_SEC10_Msk      (0x1UL << EXTI_SECCFGR1_SEC10_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR1_SEC10          EXTI_SECCFGR1_SEC10_Msk                   /*!< Security enable on line 10 */
+#define EXTI_SECCFGR1_SEC11_Pos      (11U)
+#define EXTI_SECCFGR1_SEC11_Msk      (0x1UL << EXTI_SECCFGR1_SEC11_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR1_SEC11          EXTI_SECCFGR1_SEC11_Msk                   /*!< Security enable on line 11 */
+#define EXTI_SECCFGR1_SEC12_Pos      (12U)
+#define EXTI_SECCFGR1_SEC12_Msk      (0x1UL << EXTI_SECCFGR1_SEC12_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR1_SEC12          EXTI_SECCFGR1_SEC12_Msk                   /*!< Security enable on line 12 */
+#define EXTI_SECCFGR1_SEC13_Pos      (13U)
+#define EXTI_SECCFGR1_SEC13_Msk      (0x1UL << EXTI_SECCFGR1_SEC13_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR1_SEC13          EXTI_SECCFGR1_SEC13_Msk                   /*!< Security enable on line 13 */
+#define EXTI_SECCFGR1_SEC14_Pos      (14U)
+#define EXTI_SECCFGR1_SEC14_Msk      (0x1UL << EXTI_SECCFGR1_SEC14_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR1_SEC14          EXTI_SECCFGR1_SEC14_Msk                   /*!< Security enable on line 14 */
+#define EXTI_SECCFGR1_SEC15_Pos      (15U)
+#define EXTI_SECCFGR1_SEC15_Msk      (0x1UL << EXTI_SECCFGR1_SEC15_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR1_SEC15          EXTI_SECCFGR1_SEC15_Msk                   /*!< Security enable on line 15 */
+#define EXTI_SECCFGR1_SEC17_Pos      (17U)
+#define EXTI_SECCFGR1_SEC17_Msk      (0x1UL << EXTI_SECCFGR1_SEC17_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR1_SEC17          EXTI_SECCFGR1_SEC17_Msk                   /*!< Security enable on line 17 */
+#define EXTI_SECCFGR1_SEC18_Pos      (18U)
+#define EXTI_SECCFGR1_SEC18_Msk      (0x1UL << EXTI_SECCFGR1_SEC18_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR1_SEC18          EXTI_SECCFGR1_SEC18_Msk                   /*!< Security enable on line 18 */
+#define EXTI_SECCFGR1_SEC19_Pos      (19U)
+#define EXTI_SECCFGR1_SEC19_Msk      (0x1UL << EXTI_SECCFGR1_SEC19_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR1_SEC19          EXTI_SECCFGR1_SEC19_Msk                   /*!< Security enable on line 19 */
+#define EXTI_SECCFGR1_SEC20_Pos      (20U)
+#define EXTI_SECCFGR1_SEC20_Msk      (0x1UL << EXTI_SECCFGR1_SEC20_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR1_SEC20          EXTI_SECCFGR1_SEC20_Msk                   /*!< Security enable on line 20 */
+#define EXTI_SECCFGR1_SEC21_Pos      (21U)
+#define EXTI_SECCFGR1_SEC21_Msk      (0x1UL << EXTI_SECCFGR1_SEC21_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR1_SEC21          EXTI_SECCFGR1_SEC21_Msk                   /*!< Security enable on line 21 */
+#define EXTI_SECCFGR1_SEC22_Pos      (22U)
+#define EXTI_SECCFGR1_SEC22_Msk      (0x1UL << EXTI_SECCFGR1_SEC22_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR1_SEC22          EXTI_SECCFGR1_SEC22_Msk                   /*!< Security enable on line 22 */
+#define EXTI_SECCFGR1_SEC23_Pos      (23U)
+#define EXTI_SECCFGR1_SEC23_Msk      (0x1UL << EXTI_SECCFGR1_SEC23_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR1_SEC23          EXTI_SECCFGR1_SEC23_Msk                   /*!< Security enable on line 23 */
+#define EXTI_SECCFGR1_SEC24_Pos      (24U)
+#define EXTI_SECCFGR1_SEC24_Msk      (0x1UL << EXTI_SECCFGR1_SEC24_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR1_SEC24          EXTI_SECCFGR1_SEC24_Msk                   /*!< Security enable on line 24 */
+#define EXTI_SECCFGR1_SEC25_Pos      (25U)
+#define EXTI_SECCFGR1_SEC25_Msk      (0x1UL << EXTI_SECCFGR1_SEC25_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR1_SEC25          EXTI_SECCFGR1_SEC25_Msk                   /*!< Security enable on line 25 */
+#define EXTI_SECCFGR1_SEC26_Pos      (26U)
+#define EXTI_SECCFGR1_SEC26_Msk      (0x1UL << EXTI_SECCFGR1_SEC26_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR1_SEC26          EXTI_SECCFGR1_SEC26_Msk                   /*!< Security enable on line 26 */
+#define EXTI_SECCFGR1_SEC27_Pos      (27U)
+#define EXTI_SECCFGR1_SEC27_Msk      (0x1UL << EXTI_SECCFGR1_SEC27_Pos)        /*!< 0x08000000 */
+#define EXTI_SECCFGR1_SEC27          EXTI_SECCFGR1_SEC27_Msk                   /*!< Security enable on line 27 */
+#define EXTI_SECCFGR1_SEC28_Pos      (28U)
+#define EXTI_SECCFGR1_SEC28_Msk      (0x1UL << EXTI_SECCFGR1_SEC28_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR1_SEC28          EXTI_SECCFGR1_SEC28_Msk                   /*!< Security enable on line 28 */
+#define EXTI_SECCFGR1_SEC29_Pos      (29U)
+#define EXTI_SECCFGR1_SEC29_Msk      (0x1UL << EXTI_SECCFGR1_SEC29_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR1_SEC29          EXTI_SECCFGR1_SEC29_Msk                   /*!< Security enable on line 29 */
+#define EXTI_SECCFGR1_SEC30_Pos      (30U)
+#define EXTI_SECCFGR1_SEC30_Msk      (0x1UL << EXTI_SECCFGR1_SEC30_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR1_SEC30          EXTI_SECCFGR1_SEC30_Msk                   /*!< Security enable on line 30 */
+#define EXTI_SECCFGR1_SEC31_Pos      (31U)
+#define EXTI_SECCFGR1_SEC31_Msk      (0x1UL << EXTI_SECCFGR1_SEC31_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR1_SEC31          EXTI_SECCFGR1_SEC31_Msk                   /*!< Security enable on line 31 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR1 register  ******************/
+#define EXTI_PRIVCFGR1_PRIV0_Pos     (0U)
+#define EXTI_PRIVCFGR1_PRIV0_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos)       /*!< 0x00000001 */
+#define EXTI_PRIVCFGR1_PRIV0         EXTI_PRIVCFGR1_PRIV0_Msk                  /*!< Privilege enable on line 0 */
+#define EXTI_PRIVCFGR1_PRIV1_Pos     (1U)
+#define EXTI_PRIVCFGR1_PRIV1_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos)       /*!< 0x00000002 */
+#define EXTI_PRIVCFGR1_PRIV1         EXTI_PRIVCFGR1_PRIV1_Msk                  /*!< Privilege enable on line 1 */
+#define EXTI_PRIVCFGR1_PRIV2_Pos     (2U)
+#define EXTI_PRIVCFGR1_PRIV2_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos)       /*!< 0x00000004 */
+#define EXTI_PRIVCFGR1_PRIV2         EXTI_PRIVCFGR1_PRIV2_Msk                  /*!< Privilege enable on line 2 */
+#define EXTI_PRIVCFGR1_PRIV3_Pos     (3U)
+#define EXTI_PRIVCFGR1_PRIV3_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos)       /*!< 0x00000008 */
+#define EXTI_PRIVCFGR1_PRIV3         EXTI_PRIVCFGR1_PRIV3_Msk                  /*!< Privilege enable on line 3 */
+#define EXTI_PRIVCFGR1_PRIV4_Pos     (4U)
+#define EXTI_PRIVCFGR1_PRIV4_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos)       /*!< 0x00000010 */
+#define EXTI_PRIVCFGR1_PRIV4         EXTI_PRIVCFGR1_PRIV4_Msk                  /*!< Privilege enable on line 4 */
+#define EXTI_PRIVCFGR1_PRIV5_Pos     (5U)
+#define EXTI_PRIVCFGR1_PRIV5_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos)       /*!< 0x00000020 */
+#define EXTI_PRIVCFGR1_PRIV5         EXTI_PRIVCFGR1_PRIV5_Msk                  /*!< Privilege enable on line 5 */
+#define EXTI_PRIVCFGR1_PRIV6_Pos     (6U)
+#define EXTI_PRIVCFGR1_PRIV6_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos)       /*!< 0x00000040 */
+#define EXTI_PRIVCFGR1_PRIV6         EXTI_PRIVCFGR1_PRIV6_Msk                  /*!< Privilege enable on line 6 */
+#define EXTI_PRIVCFGR1_PRIV7_Pos     (7U)
+#define EXTI_PRIVCFGR1_PRIV7_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos)       /*!< 0x00000080 */
+#define EXTI_PRIVCFGR1_PRIV7         EXTI_PRIVCFGR1_PRIV7_Msk                  /*!< Privilege enable on line 7 */
+#define EXTI_PRIVCFGR1_PRIV8_Pos     (8U)
+#define EXTI_PRIVCFGR1_PRIV8_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos)       /*!< 0x00000100 */
+#define EXTI_PRIVCFGR1_PRIV8         EXTI_PRIVCFGR1_PRIV8_Msk                  /*!< Privilege enable on line 8 */
+#define EXTI_PRIVCFGR1_PRIV9_Pos     (9U)
+#define EXTI_PRIVCFGR1_PRIV9_Msk     (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos)       /*!< 0x00000200 */
+#define EXTI_PRIVCFGR1_PRIV9         EXTI_PRIVCFGR1_PRIV9_Msk                  /*!< Privilege enable on line 9 */
+#define EXTI_PRIVCFGR1_PRIV10_Pos    (10U)
+#define EXTI_PRIVCFGR1_PRIV10_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR1_PRIV10        EXTI_PRIVCFGR1_PRIV10_Msk                 /*!< Privilege enable on line 10 */
+#define EXTI_PRIVCFGR1_PRIV11_Pos    (11U)
+#define EXTI_PRIVCFGR1_PRIV11_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR1_PRIV11        EXTI_PRIVCFGR1_PRIV11_Msk                 /*!< Privilege enable on line 11 */
+#define EXTI_PRIVCFGR1_PRIV12_Pos    (12U)
+#define EXTI_PRIVCFGR1_PRIV12_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR1_PRIV12        EXTI_PRIVCFGR1_PRIV12_Msk                 /*!< Privilege enable on line 12 */
+#define EXTI_PRIVCFGR1_PRIV13_Pos    (13U)
+#define EXTI_PRIVCFGR1_PRIV13_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR1_PRIV13        EXTI_PRIVCFGR1_PRIV13_Msk                 /*!< Privilege enable on line 13 */
+#define EXTI_PRIVCFGR1_PRIV14_Pos    (14U)
+#define EXTI_PRIVCFGR1_PRIV14_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR1_PRIV14        EXTI_PRIVCFGR1_PRIV14_Msk                 /*!< Privilege enable on line 14 */
+#define EXTI_PRIVCFGR1_PRIV15_Pos    (15U)
+#define EXTI_PRIVCFGR1_PRIV15_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR1_PRIV15        EXTI_PRIVCFGR1_PRIV15_Msk                 /*!< Privilege enable on line 15 */
+#define EXTI_PRIVCFGR1_PRIV17_Pos    (17U)
+#define EXTI_PRIVCFGR1_PRIV17_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR1_PRIV17        EXTI_PRIVCFGR1_PRIV17_Msk                 /*!< Privilege enable on line 17 */
+#define EXTI_PRIVCFGR1_PRIV18_Pos    (18U)
+#define EXTI_PRIVCFGR1_PRIV18_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR1_PRIV18        EXTI_PRIVCFGR1_PRIV18_Msk                 /*!< Privilege enable on line 18 */
+#define EXTI_PRIVCFGR1_PRIV19_Pos    (19U)
+#define EXTI_PRIVCFGR1_PRIV19_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR1_PRIV19        EXTI_PRIVCFGR1_PRIV19_Msk                 /*!< Privilege enable on line 19 */
+#define EXTI_PRIVCFGR1_PRIV20_Pos    (20U)
+#define EXTI_PRIVCFGR1_PRIV20_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR1_PRIV20        EXTI_PRIVCFGR1_PRIV20_Msk                 /*!< Privilege enable on line 20 */
+#define EXTI_PRIVCFGR1_PRIV21_Pos    (21U)
+#define EXTI_PRIVCFGR1_PRIV21_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR1_PRIV21        EXTI_PRIVCFGR1_PRIV21_Msk                 /*!< Privilege enable on line 21 */
+#define EXTI_PRIVCFGR1_PRIV22_Pos    (22U)
+#define EXTI_PRIVCFGR1_PRIV22_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR1_PRIV22        EXTI_PRIVCFGR1_PRIV22_Msk                 /*!< Privilege enable on line 22 */
+#define EXTI_PRIVCFGR1_PRIV23_Pos    (23U)
+#define EXTI_PRIVCFGR1_PRIV23_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR1_PRIV23        EXTI_PRIVCFGR1_PRIV23_Msk                 /*!< Privilege enable on line 23 */
+#define EXTI_PRIVCFGR1_PRIV24_Pos    (24U)
+#define EXTI_PRIVCFGR1_PRIV24_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR1_PRIV24        EXTI_PRIVCFGR1_PRIV24_Msk                 /*!< Privilege enable on line 24 */
+#define EXTI_PRIVCFGR1_PRIV25_Pos    (25U)
+#define EXTI_PRIVCFGR1_PRIV25_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR1_PRIV25        EXTI_PRIVCFGR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
+#define EXTI_PRIVCFGR1_PRIV26_Pos    (26U)
+#define EXTI_PRIVCFGR1_PRIV26_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR1_PRIV26        EXTI_PRIVCFGR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
+#define EXTI_PRIVCFGR1_PRIV27_Pos    (27U)
+#define EXTI_PRIVCFGR1_PRIV27_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos)      /*!< 0x08000000 */
+#define EXTI_PRIVCFGR1_PRIV27        EXTI_PRIVCFGR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
+#define EXTI_PRIVCFGR1_PRIV28_Pos    (28U)
+#define EXTI_PRIVCFGR1_PRIV28_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR1_PRIV28        EXTI_PRIVCFGR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
+#define EXTI_PRIVCFGR1_PRIV29_Pos    (29U)
+#define EXTI_PRIVCFGR1_PRIV29_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR1_PRIV29        EXTI_PRIVCFGR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
+#define EXTI_PRIVCFGR1_PRIV30_Pos    (30U)
+#define EXTI_PRIVCFGR1_PRIV30_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR1_PRIV30        EXTI_PRIVCFGR1_PRIV30_Msk                 /*!< Privilege enable on line 30 */
+#define EXTI_PRIVCFGR1_PRIV31_Pos    (31U)
+#define EXTI_PRIVCFGR1_PRIV31_Msk    (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR1_PRIV31        EXTI_PRIVCFGR1_PRIV31_Msk                 /*!< Privilege enable on line 31 */
+
+/*******************  Bit definition for EXTI_RTSR2 register  *****************/
+#define EXTI_RTSR2_RT39_Pos          (7U)
+#define EXTI_RTSR2_RT39_Msk          (0x1UL << EXTI_RTSR2_RT39_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR2_RT39              EXTI_RTSR2_RT39_Msk                       /*!< Rising trigger configuration for input line 39 */
+#define EXTI_RTSR2_RT40_Pos          (8U)
+#define EXTI_RTSR2_RT40_Msk          (0x1UL << EXTI_RTSR2_RT40_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR2_RT40              EXTI_RTSR2_RT40_Msk                       /*!< Rising trigger configuration for input line 40 */
+#define EXTI_RTSR2_RT51_Pos          (19U)
+#define EXTI_RTSR2_RT51_Msk          (0x1UL << EXTI_RTSR2_RT51_Pos)            /*!< 0x00080000 */
+#define EXTI_RTSR2_RT51              EXTI_RTSR2_RT51_Msk                       /*!< Rising trigger configuration for input line 51 */
+#define EXTI_RTSR2_RT54_Pos          (22U)
+#define EXTI_RTSR2_RT54_Msk          (0x1UL << EXTI_RTSR2_RT54_Pos)            /*!< 0x00400000 */
+#define EXTI_RTSR2_RT54              EXTI_RTSR2_RT54_Msk                       /*!< Rising trigger configuration for input line 54 */
+#define EXTI_RTSR2_RT56_Pos          (24U)
+#define EXTI_RTSR2_RT56_Msk          (0x1UL << EXTI_RTSR2_RT56_Pos)            /*!< 0x00100000 */
+#define EXTI_RTSR2_RT56              EXTI_RTSR2_RT56_Msk                       /*!< Rising trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_FTSR2 register  *****************/
+#define EXTI_FTSR2_FT39_Pos          (7U)
+#define EXTI_FTSR2_FT39_Msk          (0x1UL << EXTI_FTSR2_FT39_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR2_FT39              EXTI_FTSR2_FT39_Msk                       /*!< Falling trigger configuration for input line 39 */
+#define EXTI_FTSR2_FT40_Pos          (8U)
+#define EXTI_FTSR2_FT40_Msk          (0x1UL << EXTI_FTSR2_FT40_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR2_FT40              EXTI_FTSR2_FT40_Msk                       /*!< Falling trigger configuration for input line 40 */
+#define EXTI_FTSR2_FT51_Pos          (19U)
+#define EXTI_FTSR2_FT51_Msk          (0x1UL << EXTI_FTSR2_FT51_Pos)            /*!< 0x00080000 */
+#define EXTI_FTSR2_FT51              EXTI_FTSR2_FT51_Msk                       /*!< Falling trigger configuration for input line 51 */
+#define EXTI_FTSR2_FT54_Pos          (22U)
+#define EXTI_FTSR2_FT54_Msk          (0x1UL << EXTI_FTSR2_FT54_Pos)            /*!< 0x00400000 */
+#define EXTI_FTSR2_FT54              EXTI_FTSR2_FT54_Msk                       /*!< Falling trigger configuration for input line 54 */
+#define EXTI_FTSR2_FT56_Pos          (24U)
+#define EXTI_FTSR2_FT56_Msk          (0x1UL << EXTI_FTSR2_FT56_Pos)            /*!< 0x00100000 */
+#define EXTI_FTSR2_FT56              EXTI_FTSR2_FT56_Msk                       /*!< Falling trigger configuration for input line 56 */
+
+/*******************  Bit definition for EXTI_SWIER2 register  ****************/
+#define EXTI_SWIER2_SWI39_Pos        (7U)
+#define EXTI_SWIER2_SWI39_Msk        (0x1UL << EXTI_SWIER2_SWI39_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER2_SWI39            EXTI_SWIER2_SWI39_Msk                     /*!< Software Interrupt on line 39 */
+#define EXTI_SWIER2_SWI40_Pos        (8U)
+#define EXTI_SWIER2_SWI40_Msk        (0x1UL << EXTI_SWIER2_SWI40_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER2_SWI40            EXTI_SWIER2_SWI40_Msk                     /*!< Software Interrupt on line 40 */
+#define EXTI_SWIER2_SWI51_Pos        (19U)
+#define EXTI_SWIER2_SWI51_Msk        (0x1UL << EXTI_SWIER2_SWI51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWI51            EXTI_SWIER2_SWI51_Msk                     /*!< Software Interrupt on line 51 */
+#define EXTI_SWIER2_SWI54_Pos        (22U)
+#define EXTI_SWIER2_SWI54_Msk        (0x1UL << EXTI_SWIER2_SWI54_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER2_SWI54            EXTI_SWIER2_SWI54_Msk                     /*!< Software Interrupt on line 54 */
+#define EXTI_SWIER2_SWI56_Pos        (24U)
+#define EXTI_SWIER2_SWI56_Msk        (0x1UL << EXTI_SWIER2_SWI56_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER2_SWI56            EXTI_SWIER2_SWI56_Msk                     /*!< Software Interrupt on line 56 */
+
+/*******************  Bit definition for EXTI_RPR2 register  ******************/
+#define EXTI_RPR2_RPIF39_Pos         (7U)
+#define EXTI_RPR2_RPIF39_Msk         (0x1UL << EXTI_RPR2_RPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR2_RPIF39             EXTI_RPR2_RPIF39_Msk                      /*!< Rising Pending Interrupt Flag on line 39 */
+#define EXTI_RPR2_RPIF40_Pos         (8U)
+#define EXTI_RPR2_RPIF40_Msk         (0x1UL << EXTI_RPR2_RPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR2_RPIF40             EXTI_RPR2_RPIF40_Msk                      /*!< Rising Pending Interrupt Flag on line 40 */
+#define EXTI_RPR2_RPIF51_Pos         (19U)
+#define EXTI_RPR2_RPIF51_Msk         (0x1UL << EXTI_RPR2_RPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_RPR2_RPIF51             EXTI_RPR2_RPIF51_Msk                      /*!< Rising Pending Interrupt Flag on line 51 */
+#define EXTI_RPR2_RPIF54_Pos         (22U)
+#define EXTI_RPR2_RPIF54_Msk         (0x1UL << EXTI_RPR2_RPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_RPR2_RPIF54             EXTI_RPR2_RPIF54_Msk                      /*!< Rising Pending Interrupt Flag on line 54 */
+#define EXTI_RPR2_RPIF56_Pos         (24U)
+#define EXTI_RPR2_RPIF56_Msk         (0x1UL << EXTI_RPR2_RPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_RPR2_RPIF56             EXTI_RPR2_RPIF56_Msk                      /*!< Rising Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_FPR2 register  ******************/
+#define EXTI_FPR2_FPIF39_Pos         (7U)
+#define EXTI_FPR2_FPIF39_Msk         (0x1UL << EXTI_FPR2_FPIF39_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR2_FPIF39             EXTI_FPR2_FPIF39_Msk                      /*!< Falling Pending Interrupt Flag on line 39 */
+#define EXTI_FPR2_FPIF40_Pos         (8U)
+#define EXTI_FPR2_FPIF40_Msk         (0x1UL << EXTI_FPR2_FPIF40_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR2_FPIF40             EXTI_FPR2_FPIF40_Msk                      /*!< Falling Pending Interrupt Flag on line 40 */
+#define EXTI_FPR2_FPIF51_Pos         (19U)
+#define EXTI_FPR2_FPIF51_Msk         (0x1UL << EXTI_FPR2_FPIF51_Pos)           /*!< 0x00080000 */
+#define EXTI_FPR2_FPIF51             EXTI_FPR2_FPIF51_Msk                      /*!< Falling Pending Interrupt Flag on line 51 */
+#define EXTI_FPR2_FPIF54_Pos         (22U)
+#define EXTI_FPR2_FPIF54_Msk         (0x1UL << EXTI_FPR2_FPIF54_Pos)           /*!< 0x00400000 */
+#define EXTI_FPR2_FPIF54             EXTI_FPR2_FPIF54_Msk                      /*!< Falling Pending Interrupt Flag on line 54 */
+#define EXTI_FPR2_FPIF56_Pos         (24U)
+#define EXTI_FPR2_FPIF56_Msk         (0x1UL << EXTI_FPR2_FPIF56_Pos)           /*!< 0x00100000 */
+#define EXTI_FPR2_FPIF56             EXTI_FPR2_FPIF56_Msk                      /*!< Falling Pending Interrupt Flag on line 56 */
+
+/*******************  Bit definition for EXTI_SECCFGR2 register  ******************/
+#define EXTI_SECCFGR2_SEC32_Pos      (0U)
+#define EXTI_SECCFGR2_SEC32_Msk      (0x1UL << EXTI_SECCFGR2_SEC32_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR2_SEC32          EXTI_SECCFGR2_SEC32_Msk                   /*!< Security enable on line 32 */
+#define EXTI_SECCFGR2_SEC33_Pos      (1U)
+#define EXTI_SECCFGR2_SEC33_Msk      (0x1UL << EXTI_SECCFGR2_SEC33_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR2_SEC33          EXTI_SECCFGR2_SEC33_Msk                   /*!< Security enable on line 33 */
+#define EXTI_SECCFGR2_SEC34_Pos      (2U)
+#define EXTI_SECCFGR2_SEC34_Msk      (0x1UL << EXTI_SECCFGR2_SEC34_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR2_SEC34          EXTI_SECCFGR2_SEC34_Msk                   /*!< Security enable on line 34 */
+#define EXTI_SECCFGR2_SEC35_Pos      (3U)
+#define EXTI_SECCFGR2_SEC35_Msk      (0x1UL << EXTI_SECCFGR2_SEC35_Pos)        /*!< 0x00000008 */
+#define EXTI_SECCFGR2_SEC35          EXTI_SECCFGR2_SEC35_Msk                   /*!< Security enable on line 35 */
+#define EXTI_SECCFGR2_SEC36_Pos      (4U)
+#define EXTI_SECCFGR2_SEC36_Msk      (0x1UL << EXTI_SECCFGR2_SEC36_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR2_SEC36          EXTI_SECCFGR2_SEC36_Msk                   /*!< Security enable on line 36 */
+#define EXTI_SECCFGR2_SEC37_Pos      (5U)
+#define EXTI_SECCFGR2_SEC37_Msk      (0x1UL << EXTI_SECCFGR2_SEC37_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR2_SEC37          EXTI_SECCFGR2_SEC37_Msk                   /*!< Security enable on line 37 */
+#define EXTI_SECCFGR2_SEC38_Pos      (6U)
+#define EXTI_SECCFGR2_SEC38_Msk      (0x1UL << EXTI_SECCFGR2_SEC38_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR2_SEC38          EXTI_SECCFGR2_SEC38_Msk                   /*!< Security enable on line 38 */
+#define EXTI_SECCFGR2_SEC39_Pos      (7U)
+#define EXTI_SECCFGR2_SEC39_Msk      (0x1UL << EXTI_SECCFGR2_SEC39_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR2_SEC39          EXTI_SECCFGR2_SEC39_Msk                   /*!< Security enable on line 39 */
+#define EXTI_SECCFGR2_SEC40_Pos      (8U)
+#define EXTI_SECCFGR2_SEC40_Msk      (0x1UL << EXTI_SECCFGR2_SEC40_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR2_SEC40          EXTI_SECCFGR2_SEC40_Msk                   /*!< Security enable on line 40 */
+#define EXTI_SECCFGR2_SEC41_Pos      (9U)
+#define EXTI_SECCFGR2_SEC41_Msk      (0x1UL << EXTI_SECCFGR2_SEC41_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR2_SEC41          EXTI_SECCFGR2_SEC41_Msk                   /*!< Security enable on line 41 */
+#define EXTI_SECCFGR2_SEC42_Pos      (10U)
+#define EXTI_SECCFGR2_SEC42_Msk      (0x1UL << EXTI_SECCFGR2_SEC42_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR2_SEC42          EXTI_SECCFGR2_SEC42_Msk                   /*!< Security enable on line 42 */
+#define EXTI_SECCFGR2_SEC43_Pos      (11U)
+#define EXTI_SECCFGR2_SEC43_Msk      (0x1UL << EXTI_SECCFGR2_SEC43_Pos)        /*!< 0x00000800 */
+#define EXTI_SECCFGR2_SEC43          EXTI_SECCFGR2_SEC43_Msk                   /*!< Security enable on line 43 */
+#define EXTI_SECCFGR2_SEC44_Pos      (12U)
+#define EXTI_SECCFGR2_SEC44_Msk      (0x1UL << EXTI_SECCFGR2_SEC44_Pos)        /*!< 0x00001000 */
+#define EXTI_SECCFGR2_SEC44          EXTI_SECCFGR2_SEC44_Msk                   /*!< Security enable on line 44 */
+#define EXTI_SECCFGR2_SEC45_Pos      (13U)
+#define EXTI_SECCFGR2_SEC45_Msk      (0x1UL << EXTI_SECCFGR2_SEC45_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR2_SEC45          EXTI_SECCFGR2_SEC45                       /*!< Security enable on line 45 */
+#define EXTI_SECCFGR2_SEC46_Pos      (14U)
+#define EXTI_SECCFGR2_SEC46_Msk      (0x1UL << EXTI_SECCFGR2_SEC46_Pos)        /*!< 0x00004000 */
+#define EXTI_SECCFGR2_SEC46          EXTI_SECCFGR2_SEC46_Msk                   /*!< Security enable on line 46 */
+#define EXTI_SECCFGR2_SEC47_Pos      (15U)
+#define EXTI_SECCFGR2_SEC47_Msk      (0x1UL << EXTI_SECCFGR2_SEC47_Pos)        /*!< 0x00008000 */
+#define EXTI_SECCFGR2_SEC47          EXTI_SECCFGR2_SEC47_Msk                   /*!< Security enable on line 47 */
+#define EXTI_SECCFGR2_SEC48_Pos      (16U)
+#define EXTI_SECCFGR2_SEC48_Msk      (0x1UL << EXTI_SECCFGR2_SEC48_Pos)        /*!< 0x00010000 */
+#define EXTI_SECCFGR2_SEC48          EXTI_SECCFGR2_SEC48_Msk                   /*!< Security enable on line 48 */
+#define EXTI_SECCFGR2_SEC49_Pos      (17U)
+#define EXTI_SECCFGR2_SEC49_Msk      (0x1UL << EXTI_SECCFGR2_SEC49_Pos)        /*!< 0x00020000 */
+#define EXTI_SECCFGR2_SEC49          EXTI_SECCFGR2_SEC49_Msk                   /*!< Security enable on line 49 */
+#define EXTI_SECCFGR2_SEC50_Pos      (18U)
+#define EXTI_SECCFGR2_SEC50_Msk      (0x1UL << EXTI_SECCFGR2_SEC50_Pos)        /*!< 0x00040000 */
+#define EXTI_SECCFGR2_SEC50          EXTI_SECCFGR2_SEC50_Msk                   /*!< Security enable on line 50 */
+#define EXTI_SECCFGR2_SEC51_Pos      (19U)
+#define EXTI_SECCFGR2_SEC51_Msk      (0x1UL << EXTI_SECCFGR2_SEC51_Pos)        /*!< 0x00080000 */
+#define EXTI_SECCFGR2_SEC51          EXTI_SECCFGR2_SEC51_Msk                   /*!< Security enable on line 51 */
+#define EXTI_SECCFGR2_SEC52_Pos      (20U)
+#define EXTI_SECCFGR2_SEC52_Msk      (0x1UL << EXTI_SECCFGR2_SEC52_Pos)        /*!< 0x00100000 */
+#define EXTI_SECCFGR2_SEC52          EXTI_SECCFGR2_SEC52_Msk                   /*!< Security enable on line 52 */
+#define EXTI_SECCFGR2_SEC53_Pos      (21U)
+#define EXTI_SECCFGR2_SEC53_Msk      (0x1UL << EXTI_SECCFGR2_SEC53_Pos)        /*!< 0x00200000 */
+#define EXTI_SECCFGR2_SEC53          EXTI_SECCFGR2_SEC53_Msk                   /*!< Security enable on line 53 */
+#define EXTI_SECCFGR2_SEC54_Pos      (22U)
+#define EXTI_SECCFGR2_SEC54_Msk      (0x1UL << EXTI_SECCFGR2_SEC54_Pos)        /*!< 0x00400000 */
+#define EXTI_SECCFGR2_SEC54          EXTI_SECCFGR2_SEC54_Msk                   /*!< Security enable on line 54 */
+#define EXTI_SECCFGR2_SEC55_Pos      (23U)
+#define EXTI_SECCFGR2_SEC55_Msk      (0x1UL << EXTI_SECCFGR2_SEC55_Pos)        /*!< 0x00800000 */
+#define EXTI_SECCFGR2_SEC55          EXTI_SECCFGR2_SEC55_Msk                   /*!< Security enable on line 55 */
+#define EXTI_SECCFGR2_SEC56_Pos      (24U)
+#define EXTI_SECCFGR2_SEC56_Msk      (0x1UL << EXTI_SECCFGR2_SEC56_Pos)        /*!< 0x01000000 */
+#define EXTI_SECCFGR2_SEC56          EXTI_SECCFGR2_SEC56_Msk                   /*!< Security enable on line 56 */
+#define EXTI_SECCFGR2_SEC57_Pos      (25U)
+#define EXTI_SECCFGR2_SEC57_Msk      (0x1UL << EXTI_SECCFGR2_SEC57_Pos)        /*!< 0x02000000 */
+#define EXTI_SECCFGR2_SEC57          EXTI_SECCFGR2_SEC57_Msk                   /*!< Security enable on line 57 */
+#define EXTI_SECCFGR2_SEC58_Pos      (26U)
+#define EXTI_SECCFGR2_SEC58_Msk      (0x1UL << EXTI_SECCFGR2_SEC58_Pos)        /*!< 0x04000000 */
+#define EXTI_SECCFGR2_SEC58          EXTI_SECCFGR2_SEC58_Msk                   /*!< Security enable on line 58 */
+#define EXTI_SECCFGR2_SEC60_Pos      (28U)
+#define EXTI_SECCFGR2_SEC60_Msk      (0x1UL << EXTI_SECCFGR2_SEC60_Pos)        /*!< 0x10000000 */
+#define EXTI_SECCFGR2_SEC60          EXTI_SECCFGR2_SEC60_Msk                   /*!< Security enable on line 60 */
+#define EXTI_SECCFGR2_SEC61_Pos      (29U)
+#define EXTI_SECCFGR2_SEC61_Msk      (0x1UL << EXTI_SECCFGR2_SEC61_Pos)        /*!< 0x20000000 */
+#define EXTI_SECCFGR2_SEC61          EXTI_SECCFGR2_SEC61_Msk                   /*!< Security enable on line 61 */
+#define EXTI_SECCFGR2_SEC62_Pos      (30U)
+#define EXTI_SECCFGR2_SEC62_Msk      (0x1UL << EXTI_SECCFGR2_SEC62_Pos)        /*!< 0x40000000 */
+#define EXTI_SECCFGR2_SEC62          EXTI_SECCFGR2_SEC62_Msk                   /*!< Security enable on line 62 */
+#define EXTI_SECCFGR2_SEC63_Pos      (31U)
+#define EXTI_SECCFGR2_SEC63_Msk      (0x1UL << EXTI_SECCFGR2_SEC63_Pos)        /*!< 0x80000000 */
+#define EXTI_SECCFGR2_SEC63          EXTI_SECCFGR2_SEC63_Msk                   /*!< Security enable on line 63 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR2 register  ******************/
+#define EXTI_PRIVCFGR2_PRIV32_Pos    (0U)
+#define EXTI_PRIVCFGR2_PRIV32_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR2_PRIV32        EXTI_PRIVCFGR2_PRIV32_Msk                 /*!< Privilege enable on line 32 */
+#define EXTI_PRIVCFGR2_PRIV33_Pos    (1U)
+#define EXTI_PRIVCFGR2_PRIV33_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR2_PRIV33        EXTI_PRIVCFGR2_PRIV33_Msk                 /*!< Privilege enable on line 33 */
+#define EXTI_PRIVCFGR2_PRIV34_Pos    (2U)
+#define EXTI_PRIVCFGR2_PRIV34_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR2_PRIV34        EXTI_PRIVCFGR2_PRIV34_Msk                 /*!< Privilege enable on line 34 */
+#define EXTI_PRIVCFGR2_PRIV35_Pos    (3U)
+#define EXTI_PRIVCFGR2_PRIV35_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos)      /*!< 0x00000008 */
+#define EXTI_PRIVCFGR2_PRIV35        EXTI_PRIVCFGR2_PRIV35_Msk                 /*!< Privilege enable on line 35 */
+#define EXTI_PRIVCFGR2_PRIV36_Pos    (4U)
+#define EXTI_PRIVCFGR2_PRIV36_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR2_PRIV36        EXTI_PRIVCFGR2_PRIV36_Msk                 /*!< Privilege enable on line 36 */
+#define EXTI_PRIVCFGR2_PRIV37_Pos    (5U)
+#define EXTI_PRIVCFGR2_PRIV37_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR2_PRIV37        EXTI_PRIVCFGR2_PRIV37_Msk                 /*!< Privilege enable on line 37 */
+#define EXTI_PRIVCFGR2_PRIV38_Pos    (6U)
+#define EXTI_PRIVCFGR2_PRIV38_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR2_PRIV38        EXTI_PRIVCFGR2_PRIV38_Msk                 /*!< Privilege enable on line 38 */
+#define EXTI_PRIVCFGR2_PRIV39_Pos    (7U)
+#define EXTI_PRIVCFGR2_PRIV39_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR2_PRIV39        EXTI_PRIVCFGR2_PRIV39_Msk                 /*!< Privilege enable on line 39 */
+#define EXTI_PRIVCFGR2_PRIV40_Pos    (8U)
+#define EXTI_PRIVCFGR2_PRIV40_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV40_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR2_PRIV40        EXTI_PRIVCFGR2_PRIV40_Msk                 /*!< Privilege enable on line 40 */
+#define EXTI_PRIVCFGR2_PRIV41_Pos    (9U)
+#define EXTI_PRIVCFGR2_PRIV41_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV41_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR2_PRIV41        EXTI_PRIVCFGR2_PRIV41_Msk                 /*!< Privilege enable on line 41 */
+#define EXTI_PRIVCFGR2_PRIV42_Pos    (10U)
+#define EXTI_PRIVCFGR2_PRIV42_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV42_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR2_PRIV42        EXTI_PRIVCFGR2_PRIV42_Msk                 /*!< Privilege enable on line 42 */
+#define EXTI_PRIVCFGR2_PRIV43_Pos    (11U)
+#define EXTI_PRIVCFGR2_PRIV43_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV43_Pos)      /*!< 0x00000800 */
+#define EXTI_PRIVCFGR2_PRIV43        EXTI_PRIVCFGR2_PRIV43_Msk                 /*!< Privilege enable on line 43 */
+#define EXTI_PRIVCFGR2_PRIV44_Pos    (12U)
+#define EXTI_PRIVCFGR2_PRIV44_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV44_Pos)      /*!< 0x00001000 */
+#define EXTI_PRIVCFGR2_PRIV44        EXTI_PRIVCFGR2_PRIV44_Msk                 /*!< Privilege enable on line 44 */
+#define EXTI_PRIVCFGR2_PRIV45_Pos    (13U)
+#define EXTI_PRIVCFGR2_PRIV45_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV45_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR2_PRIV45        EXTI_PRIVCFGR2_PRIV45                     /*!< Privilege enable on line 45 */
+#define EXTI_PRIVCFGR2_PRIV46_Pos    (14U)
+#define EXTI_PRIVCFGR2_PRIV46_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV46_Pos)      /*!< 0x00004000 */
+#define EXTI_PRIVCFGR2_PRIV46        EXTI_PRIVCFGR2_PRIV46_Msk                 /*!< Privilege enable on line 46 */
+#define EXTI_PRIVCFGR2_PRIV47_Pos    (15U)
+#define EXTI_PRIVCFGR2_PRIV47_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV47_Pos)      /*!< 0x00008000 */
+#define EXTI_PRIVCFGR2_PRIV47        EXTI_PRIVCFGR2_PRIV47_Msk                 /*!< Privilege enable on line 47 */
+#define EXTI_PRIVCFGR2_PRIV48_Pos    (16U)
+#define EXTI_PRIVCFGR2_PRIV48_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV48_Pos)      /*!< 0x00010000 */
+#define EXTI_PRIVCFGR2_PRIV48        EXTI_PRIVCFGR2_PRIV48_Msk                 /*!< Privilege enable on line 48 */
+#define EXTI_PRIVCFGR2_PRIV49_Pos    (17U)
+#define EXTI_PRIVCFGR2_PRIV49_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV49_Pos)      /*!< 0x00020000 */
+#define EXTI_PRIVCFGR2_PRIV49        EXTI_PRIVCFGR2_PRIV49_Msk                 /*!< Privilege enable on line 49 */
+#define EXTI_PRIVCFGR2_PRIV50_Pos    (18U)
+#define EXTI_PRIVCFGR2_PRIV50_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV50_Pos)      /*!< 0x00040000 */
+#define EXTI_PRIVCFGR2_PRIV50        EXTI_PRIVCFGR2_PRIV50_Msk                 /*!< Privilege enable on line 50 */
+#define EXTI_PRIVCFGR2_PRIV51_Pos    (19U)
+#define EXTI_PRIVCFGR2_PRIV51_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV51_Pos)      /*!< 0x00080000 */
+#define EXTI_PRIVCFGR2_PRIV51        EXTI_PRIVCFGR2_PRIV51_Msk                 /*!< Privilege enable on line 51 */
+#define EXTI_PRIVCFGR2_PRIV52_Pos    (20U)
+#define EXTI_PRIVCFGR2_PRIV52_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV52_Pos)      /*!< 0x00100000 */
+#define EXTI_PRIVCFGR2_PRIV52        EXTI_PRIVCFGR2_PRIV52_Msk                 /*!< Privilege enable on line 52 */
+#define EXTI_PRIVCFGR2_PRIV53_Pos    (21U)
+#define EXTI_PRIVCFGR2_PRIV53_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV53_Pos)      /*!< 0x00200000 */
+#define EXTI_PRIVCFGR2_PRIV53        EXTI_PRIVCFGR2_PRIV53_Msk                 /*!< Privilege enable on line 53 */
+#define EXTI_PRIVCFGR2_PRIV54_Pos    (22U)
+#define EXTI_PRIVCFGR2_PRIV54_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV54_Pos)      /*!< 0x00400000 */
+#define EXTI_PRIVCFGR2_PRIV54        EXTI_PRIVCFGR2_PRIV54_Msk                 /*!< Privilege enable on line 54 */
+#define EXTI_PRIVCFGR2_PRIV55_Pos    (23U)
+#define EXTI_PRIVCFGR2_PRIV55_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV55_Pos)      /*!< 0x00800000 */
+#define EXTI_PRIVCFGR2_PRIV55        EXTI_PRIVCFGR2_PRIV55_Msk                 /*!< Privilege enable on line 55 */
+#define EXTI_PRIVCFGR2_PRIV56_Pos    (24U)
+#define EXTI_PRIVCFGR2_PRIV56_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV56_Pos)      /*!< 0x01000000 */
+#define EXTI_PRIVCFGR2_PRIV56        EXTI_PRIVCFGR2_PRIV56_Msk                 /*!< Privilege enable on line 56 */
+#define EXTI_PRIVCFGR2_PRIV57_Pos    (25U)
+#define EXTI_PRIVCFGR2_PRIV57_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV57_Pos)      /*!< 0x02000000 */
+#define EXTI_PRIVCFGR2_PRIV57        EXTI_PRIVCFGR2_PRIV57_Msk                 /*!< Privilege enable on line 57 */
+#define EXTI_PRIVCFGR2_PRIV58_Pos    (26U)
+#define EXTI_PRIVCFGR2_PRIV58_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV58_Pos)      /*!< 0x04000000 */
+#define EXTI_PRIVCFGR2_PRIV58        EXTI_PRIVCFGR2_PRIV58_Msk                 /*!< Privilege enable on line 58 */
+#define EXTI_PRIVCFGR2_PRIV60_Pos    (28U)
+#define EXTI_PRIVCFGR2_PRIV60_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV60_Pos)      /*!< 0x10000000 */
+#define EXTI_PRIVCFGR2_PRIV60        EXTI_PRIVCFGR2_PRIV60_Msk                 /*!< Privilege enable on line 60 */
+#define EXTI_PRIVCFGR2_PRIV61_Pos    (29U)
+#define EXTI_PRIVCFGR2_PRIV61_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV61_Pos)      /*!< 0x20000000 */
+#define EXTI_PRIVCFGR2_PRIV61        EXTI_PRIVCFGR2_PRIV61_Msk                 /*!< Privilege enable on line 61 */
+#define EXTI_PRIVCFGR2_PRIV62_Pos    (30U)
+#define EXTI_PRIVCFGR2_PRIV62_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV62_Pos)      /*!< 0x40000000 */
+#define EXTI_PRIVCFGR2_PRIV62        EXTI_PRIVCFGR2_PRIV62_Msk                 /*!< Privilege enable on line 62 */
+#define EXTI_PRIVCFGR2_PRIV63_Pos    (31U)
+#define EXTI_PRIVCFGR2_PRIV63_Msk    (0x1UL << EXTI_PRIVCFGR2_PRIV63_Pos)      /*!< 0x80000000 */
+#define EXTI_PRIVCFGR2_PRIV63        EXTI_PRIVCFGR2_PRIV63_Msk                 /*!< Privilege enable on line 63 */
+
+/*******************  Bit definition for EXTI_RTSR3 register  *****************/
+#define EXTI_RTSR3_RT66_Pos          (2U)
+#define EXTI_RTSR3_RT66_Msk          (0x1UL << EXTI_RTSR3_RT66_Pos)            /*!< 0x00000004 */
+#define EXTI_RTSR3_RT66              EXTI_RTSR3_RT66_Msk                       /*!< Rising trigger configuration for input line 66 */
+#define EXTI_RTSR3_RT68_Pos          (4U)
+#define EXTI_RTSR3_RT68_Msk          (0x1UL << EXTI_RTSR3_RT68_Pos)            /*!< 0x00000010 */
+#define EXTI_RTSR3_RT68              EXTI_RTSR3_RT68_Msk                       /*!< Rising trigger configuration for input line 68 */
+#define EXTI_RTSR3_RT69_Pos          (5U)
+#define EXTI_RTSR3_RT69_Msk          (0x1UL << EXTI_RTSR3_RT69_Pos)            /*!< 0x00000020 */
+#define EXTI_RTSR3_RT69              EXTI_RTSR3_RT69_Msk                       /*!< Rising trigger configuration for input line 69 */
+#define EXTI_RTSR3_RT70_Pos          (6U)
+#define EXTI_RTSR3_RT70_Msk          (0x1UL << EXTI_RTSR3_RT70_Pos)            /*!< 0x00000040 */
+#define EXTI_RTSR3_RT70              EXTI_RTSR3_RT70_Msk                       /*!< Rising trigger configuration for input line 70 */
+#define EXTI_RTSR3_RT71_Pos          (7U)
+#define EXTI_RTSR3_RT71_Msk          (0x1UL << EXTI_RTSR3_RT71_Pos)            /*!< 0x00000080 */
+#define EXTI_RTSR3_RT71              EXTI_RTSR3_RT71_Msk                       /*!< Rising trigger configuration for input line 71 */
+#define EXTI_RTSR3_RT72_Pos          (8U)
+#define EXTI_RTSR3_RT72_Msk          (0x1UL << EXTI_RTSR3_RT72_Pos)            /*!< 0x00000100 */
+#define EXTI_RTSR3_RT72              EXTI_RTSR3_RT72_Msk                       /*!< Rising trigger configuration for input line 72 */
+#define EXTI_RTSR3_RT73_Pos          (9U)
+#define EXTI_RTSR3_RT73_Msk          (0x1UL << EXTI_RTSR3_RT73_Pos)            /*!< 0x00000200 */
+#define EXTI_RTSR3_RT73              EXTI_RTSR3_RT73_Msk                       /*!< Rising trigger configuration for input line 73 */
+#define EXTI_RTSR3_RT74_Pos          (10U)
+#define EXTI_RTSR3_RT74_Msk          (0x1UL << EXTI_RTSR3_RT74_Pos)            /*!< 0x00000400 */
+#define EXTI_RTSR3_RT74              EXTI_RTSR3_RT74_Msk                       /*!< Rising trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_FTSR3 register  *****************/
+#define EXTI_FTSR3_FT66_Pos          (2U)
+#define EXTI_FTSR3_FT66_Msk          (0x1UL << EXTI_FTSR3_FT66_Pos)            /*!< 0x00000004 */
+#define EXTI_FTSR3_FT66              EXTI_FTSR3_FT66_Msk                       /*!< Falling trigger configuration for input line 66 */
+#define EXTI_FTSR3_FT68_Pos          (4U)
+#define EXTI_FTSR3_FT68_Msk          (0x1UL << EXTI_FTSR3_FT68_Pos)            /*!< 0x00000010 */
+#define EXTI_FTSR3_FT68              EXTI_FTSR3_FT68_Msk                       /*!< Falling trigger configuration for input line 68 */
+#define EXTI_FTSR3_FT69_Pos          (5U)
+#define EXTI_FTSR3_FT69_Msk          (0x1UL << EXTI_FTSR3_FT69_Pos)            /*!< 0x00000020 */
+#define EXTI_FTSR3_FT69              EXTI_FTSR3_FT69_Msk                       /*!< Falling trigger configuration for input line 69 */
+#define EXTI_FTSR3_FT70_Pos          (6U)
+#define EXTI_FTSR3_FT70_Msk          (0x1UL << EXTI_FTSR3_FT70_Pos)            /*!< 0x00000040 */
+#define EXTI_FTSR3_FT70              EXTI_FTSR3_FT70_Msk                       /*!< Falling trigger configuration for input line 70 */
+#define EXTI_FTSR3_FT71_Pos          (7U)
+#define EXTI_FTSR3_FT71_Msk          (0x1UL << EXTI_FTSR3_FT71_Pos)            /*!< 0x00000080 */
+#define EXTI_FTSR3_FT71              EXTI_FTSR3_FT71_Msk                       /*!< Falling trigger configuration for input line 71 */
+#define EXTI_FTSR3_FT72_Pos          (8U)
+#define EXTI_FTSR3_FT72_Msk          (0x1UL << EXTI_FTSR3_FT72_Pos)            /*!< 0x00000100 */
+#define EXTI_FTSR3_FT72              EXTI_FTSR3_FT72_Msk                       /*!< Falling trigger configuration for input line 72 */
+#define EXTI_FTSR3_FT73_Pos          (9U)
+#define EXTI_FTSR3_FT73_Msk          (0x1UL << EXTI_FTSR3_FT73_Pos)            /*!< 0x00000200 */
+#define EXTI_FTSR3_FT73              EXTI_FTSR3_FT73_Msk                       /*!< Falling trigger configuration for input line 73 */
+#define EXTI_FTSR3_FT74_Pos          (10U)
+#define EXTI_FTSR3_FT74_Msk          (0x1UL << EXTI_FTSR3_FT74_Pos)            /*!< 0x00000400 */
+#define EXTI_FTSR3_FT74              EXTI_FTSR3_FT74_Msk                       /*!< Falling trigger configuration for input line 74 */
+
+/*******************  Bit definition for EXTI_SWIER3 register  ****************/
+#define EXTI_SWIER3_SWI66_Pos        (2U)
+#define EXTI_SWIER3_SWI66_Msk        (0x1UL << EXTI_SWIER3_SWI66_Pos)          /*!< 0x00000004 */
+#define EXTI_SWIER3_SWI66            EXTI_SWIER3_SWI66_Msk                     /*!< Software Interrupt on line 66 */
+#define EXTI_SWIER3_SWI68_Pos        (4U)
+#define EXTI_SWIER3_SWI68_Msk        (0x1UL << EXTI_SWIER3_SWI68_Pos)          /*!< 0x00000010 */
+#define EXTI_SWIER3_SWI68            EXTI_SWIER3_SWI68_Msk                     /*!< Software Interrupt on line 68 */
+#define EXTI_SWIER3_SWI69_Pos        (5U)
+#define EXTI_SWIER3_SWI69_Msk        (0x1UL << EXTI_SWIER3_SWI69_Pos)          /*!< 0x00000020 */
+#define EXTI_SWIER3_SWI69            EXTI_SWIER3_SWI69_Msk                     /*!< Software Interrupt on line 69 */
+#define EXTI_SWIER3_SWI70_Pos        (6U)
+#define EXTI_SWIER3_SWI70_Msk        (0x1UL << EXTI_SWIER3_SWI70_Pos)          /*!< 0x00000040 */
+#define EXTI_SWIER3_SWI70            EXTI_SWIER3_SWI70_Msk                     /*!< Software Interrupt on line 70 */
+#define EXTI_SWIER3_SWI71_Pos        (7U)
+#define EXTI_SWIER3_SWI71_Msk        (0x1UL << EXTI_SWIER3_SWI71_Pos)          /*!< 0x00000080 */
+#define EXTI_SWIER3_SWI71            EXTI_SWIER3_SWI71_Msk                     /*!< Software Interrupt on line 71 */
+#define EXTI_SWIER3_SWI72_Pos        (8U)
+#define EXTI_SWIER3_SWI72_Msk        (0x1UL << EXTI_SWIER3_SWI72_Pos)          /*!< 0x00000100 */
+#define EXTI_SWIER3_SWI72            EXTI_SWIER3_SWI72_Msk                     /*!< Software Interrupt on line 72 */
+#define EXTI_SWIER3_SWI73_Pos        (9U)
+#define EXTI_SWIER3_SWI73_Msk        (0x1UL << EXTI_SWIER3_SWI73_Pos)          /*!< 0x00000200 */
+#define EXTI_SWIER3_SWI73            EXTI_SWIER3_SWI73_Msk                     /*!< Software Interrupt on line 73 */
+#define EXTI_SWIER3_SWI74_Pos        (10U)
+#define EXTI_SWIER3_SWI74_Msk        (0x1UL << EXTI_SWIER3_SWI74_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER3_SWI74            EXTI_SWIER3_SWI74_Msk                     /*!< Software Interrupt on line 74 */
+
+/*******************  Bit definition for EXTI_RPR3 register  ******************/
+#define EXTI_RPR3_RPIF66_Pos         (2U)
+#define EXTI_RPR3_RPIF66_Msk         (0x1UL << EXTI_RPR3_RPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_RPR3_RPIF66             EXTI_RPR3_RPIF66_Msk                      /*!< Rising Pending Interrupt Flag on line 66 */
+#define EXTI_RPR3_RPIF68_Pos         (4U)
+#define EXTI_RPR3_RPIF68_Msk         (0x1UL << EXTI_RPR3_RPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_RPR3_RPIF68             EXTI_RPR3_RPIF68_Msk                      /*!< Rising Pending Interrupt Flag on line 68 */
+#define EXTI_RPR3_RPIF69_Pos         (5U)
+#define EXTI_RPR3_RPIF69_Msk         (0x1UL << EXTI_RPR3_RPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_RPR3_RPIF69             EXTI_RPR3_RPIF69_Msk                      /*!< Rising Pending Interrupt Flag on line 69 */
+#define EXTI_RPR3_RPIF70_Pos         (6U)
+#define EXTI_RPR3_RPIF70_Msk         (0x1UL << EXTI_RPR3_RPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_RPR3_RPIF70             EXTI_RPR3_RPIF70_Msk                      /*!< Rising Pending Interrupt Flag on line 70 */
+#define EXTI_RPR3_RPIF71_Pos         (7U)
+#define EXTI_RPR3_RPIF71_Msk         (0x1UL << EXTI_RPR3_RPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_RPR3_RPIF71             EXTI_RPR3_RPIF71_Msk                      /*!< Rising Pending Interrupt Flag on line 71 */
+#define EXTI_RPR3_RPIF72_Pos         (8U)
+#define EXTI_RPR3_RPIF72_Msk         (0x1UL << EXTI_RPR3_RPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_RPR3_RPIF72             EXTI_RPR3_RPIF72_Msk                      /*!< Rising Pending Interrupt Flag on line 72 */
+#define EXTI_RPR3_RPIF73_Pos         (9U)
+#define EXTI_RPR3_RPIF73_Msk         (0x1UL << EXTI_RPR3_RPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_RPR3_RPIF73             EXTI_RPR3_RPIF73_Msk                      /*!< Rising Pending Interrupt Flag on line 73 */
+#define EXTI_RPR3_RPIF74_Pos         (10U)
+#define EXTI_RPR3_RPIF74_Msk         (0x1UL << EXTI_RPR3_RPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_RPR3_RPIF74             EXTI_RPR3_RPIF74_Msk                      /*!< Rising Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_FPR3 register  ******************/
+#define EXTI_FPR3_FPIF66_Pos         (2U)
+#define EXTI_FPR3_FPIF66_Msk         (0x1UL << EXTI_FPR3_FPIF66_Pos)           /*!< 0x00000004 */
+#define EXTI_FPR3_FPIF66             EXTI_FPR3_FPIF66_Msk                      /*!< Falling Pending Interrupt Flag on line 66 */
+#define EXTI_FPR3_FPIF68_Pos         (4U)
+#define EXTI_FPR3_FPIF68_Msk         (0x1UL << EXTI_FPR3_FPIF68_Pos)           /*!< 0x00000010 */
+#define EXTI_FPR3_FPIF68             EXTI_FPR3_FPIF68_Msk                      /*!< Falling Pending Interrupt Flag on line 68 */
+#define EXTI_FPR3_FPIF69_Pos         (5U)
+#define EXTI_FPR3_FPIF69_Msk         (0x1UL << EXTI_FPR3_FPIF69_Pos)           /*!< 0x00000020 */
+#define EXTI_FPR3_FPIF69             EXTI_FPR3_FPIF69_Msk                      /*!< Falling Pending Interrupt Flag online  69 */
+#define EXTI_FPR3_FPIF70_Pos         (6U)
+#define EXTI_FPR3_FPIF70_Msk         (0x1UL << EXTI_FPR3_FPIF70_Pos)           /*!< 0x00000040 */
+#define EXTI_FPR3_FPIF70             EXTI_FPR3_FPIF70_Msk                      /*!< Falling Pending Interrupt Flag on line 70 */
+#define EXTI_FPR3_FPIF71_Pos         (7U)
+#define EXTI_FPR3_FPIF71_Msk         (0x1UL << EXTI_FPR3_FPIF71_Pos)           /*!< 0x00000080 */
+#define EXTI_FPR3_FPIF71             EXTI_FPR3_FPIF71_Msk                      /*!< Falling Pending Interrupt Flag on line 71 */
+#define EXTI_FPR3_FPIF72_Pos         (8U)
+#define EXTI_FPR3_FPIF72_Msk         (0x1UL << EXTI_FPR3_FPIF72_Pos)           /*!< 0x00000100 */
+#define EXTI_FPR3_FPIF72             EXTI_FPR3_FPIF72_Msk                      /*!< Falling Pending Interrupt Flag on line 72 */
+#define EXTI_FPR3_FPIF73_Pos         (9U)
+#define EXTI_FPR3_FPIF73_Msk         (0x1UL << EXTI_FPR3_FPIF73_Pos)           /*!< 0x00000200 */
+#define EXTI_FPR3_FPIF73             EXTI_FPR3_FPIF73_Msk                      /*!< Falling Pending Interrupt Flag on line 73 */
+#define EXTI_FPR3_FPIF74_Pos         (10U)
+#define EXTI_FPR3_FPIF74_Msk         (0x1UL << EXTI_FPR3_FPIF74_Pos)           /*!< 0x00000400 */
+#define EXTI_FPR3_FPIF74             EXTI_FPR3_FPIF74_Msk                      /*!< Falling Pending Interrupt Flag on line 74 */
+
+/*******************  Bit definition for EXTI_SECCFGR3 register  ******************/
+#define EXTI_SECCFGR3_SEC64_Pos      (0U)
+#define EXTI_SECCFGR3_SEC64_Msk      (0x1UL << EXTI_SECCFGR3_SEC64_Pos)        /*!< 0x00000001 */
+#define EXTI_SECCFGR3_SEC64          EXTI_SECCFGR3_SEC64_Msk                   /*!< Security enable on line 64 */
+#define EXTI_SECCFGR3_SEC65_Pos      (1U)
+#define EXTI_SECCFGR3_SEC65_Msk      (0x1UL << EXTI_SECCFGR3_SEC65_Pos)        /*!< 0x00000002 */
+#define EXTI_SECCFGR3_SEC65          EXTI_SECCFGR3_SEC65_Msk                   /*!< Security enable on line 65 */
+#define EXTI_SECCFGR3_SEC66_Pos      (2U)
+#define EXTI_SECCFGR3_SEC66_Msk      (0x1UL << EXTI_SECCFGR3_SEC66_Pos)        /*!< 0x00000004 */
+#define EXTI_SECCFGR3_SEC66          EXTI_SECCFGR3_SEC66_Msk                   /*!< Security enable on line 66  */
+#define EXTI_SECCFGR3_SEC68_Pos      (4U)
+#define EXTI_SECCFGR3_SEC68_Msk      (0x1UL << EXTI_SECCFGR3_SEC68_Pos)        /*!< 0x00000010 */
+#define EXTI_SECCFGR3_SEC68          EXTI_SECCFGR3_SEC68_Msk                   /*!< Security enable on line 68 */
+#define EXTI_SECCFGR3_SEC69_Pos      (5U)
+#define EXTI_SECCFGR3_SEC69_Msk      (0x1UL << EXTI_SECCFGR3_SEC69_Pos)        /*!< 0x00000020 */
+#define EXTI_SECCFGR3_SEC69          EXTI_SECCFGR3_SEC69_Msk                   /*!< Security enable on line 69 */
+#define EXTI_SECCFGR3_SEC70_Pos      (6U)
+#define EXTI_SECCFGR3_SEC70_Msk      (0x1UL << EXTI_SECCFGR3_SEC70_Pos)        /*!< 0x00000040 */
+#define EXTI_SECCFGR3_SEC70          EXTI_SECCFGR3_SEC70_Msk                   /*!< Security enable on line 70 */
+#define EXTI_SECCFGR3_SEC71_Pos      (7U)
+#define EXTI_SECCFGR3_SEC71_Msk      (0x1UL << EXTI_SECCFGR3_SEC71_Pos)        /*!< 0x00000080 */
+#define EXTI_SECCFGR3_SEC71          EXTI_SECCFGR3_SEC71_Msk                   /*!< Security enable on line 71 */
+#define EXTI_SECCFGR3_SEC72_Pos      (8U)
+#define EXTI_SECCFGR3_SEC72_Msk      (0x1UL << EXTI_SECCFGR3_SEC72_Pos)        /*!< 0x00000100 */
+#define EXTI_SECCFGR3_SEC72          EXTI_SECCFGR3_SEC72_Msk                   /*!< Security enable on line 72 */
+#define EXTI_SECCFGR3_SEC73_Pos      (9U)
+#define EXTI_SECCFGR3_SEC73_Msk      (0x1UL << EXTI_SECCFGR3_SEC73_Pos)        /*!< 0x00000200 */
+#define EXTI_SECCFGR3_SEC73          EXTI_SECCFGR3_SEC73_Msk                   /*!< Security enable on line 73 */
+#define EXTI_SECCFGR3_SEC74_Pos      (10U)
+#define EXTI_SECCFGR3_SEC74_Msk      (0x1UL << EXTI_SECCFGR3_SEC74_Pos)        /*!< 0x00000400 */
+#define EXTI_SECCFGR3_SEC74          EXTI_SECCFGR3_SEC74_Msk                   /*!< Security enable on line 74 */
+#define EXTI_SECCFGR3_SEC77_Pos      (13U)
+#define EXTI_SECCFGR3_SEC77_Msk      (0x1UL << EXTI_SECCFGR3_SEC77_Pos)        /*!< 0x00002000 */
+#define EXTI_SECCFGR3_SEC77          EXTI_SECCFGR3_SEC77_Msk                   /*!< Security enable on line 77 */
+
+/*******************  Bit definition for EXTI_PRIVCFGR3 register  ******************/
+#define EXTI_PRIVCFGR3_PRIV64_Pos    (0U)
+#define EXTI_PRIVCFGR3_PRIV64_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV64_Pos)      /*!< 0x00000001 */
+#define EXTI_PRIVCFGR3_PRIV64        EXTI_PRIVCFGR3_PRIV64_Msk                 /*!< Privilege enable on line 64 */
+#define EXTI_PRIVCFGR3_PRIV65_Pos    (1U)
+#define EXTI_PRIVCFGR3_PRIV65_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV65_Pos)      /*!< 0x00000002 */
+#define EXTI_PRIVCFGR3_PRIV65        EXTI_PRIVCFGR3_PRIV65_Msk                 /*!< Privilege enable on line 65 */
+#define EXTI_PRIVCFGR3_PRIV66_Pos    (2U)
+#define EXTI_PRIVCFGR3_PRIV66_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV66_Pos)      /*!< 0x00000004 */
+#define EXTI_PRIVCFGR3_PRIV66        EXTI_PRIVCFGR3_PRIV66_Msk                 /*!< Privilege enable on line 66  */
+#define EXTI_PRIVCFGR3_PRIV68_Pos    (4U)
+#define EXTI_PRIVCFGR3_PRIV68_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV68_Pos)      /*!< 0x00000010 */
+#define EXTI_PRIVCFGR3_PRIV68        EXTI_PRIVCFGR3_PRIV68_Msk                 /*!< Privilege enable on line 68 */
+#define EXTI_PRIVCFGR3_PRIV69_Pos    (5U)
+#define EXTI_PRIVCFGR3_PRIV69_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV69_Pos)      /*!< 0x00000020 */
+#define EXTI_PRIVCFGR3_PRIV69        EXTI_PRIVCFGR3_PRIV69_Msk                 /*!< Privilege enable on line 69 */
+#define EXTI_PRIVCFGR3_PRIV70_Pos    (6U)
+#define EXTI_PRIVCFGR3_PRIV70_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV70_Pos)      /*!< 0x00000040 */
+#define EXTI_PRIVCFGR3_PRIV70        EXTI_PRIVCFGR3_PRIV70_Msk                 /*!< Privilege enable on line 70 */
+#define EXTI_PRIVCFGR3_PRIV71_Pos    (7U)
+#define EXTI_PRIVCFGR3_PRIV71_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV71_Pos)      /*!< 0x00000080 */
+#define EXTI_PRIVCFGR3_PRIV71        EXTI_PRIVCFGR3_PRIV71_Msk                 /*!< Privilege enable on line 71 */
+#define EXTI_PRIVCFGR3_PRIV72_Pos    (8U)
+#define EXTI_PRIVCFGR3_PRIV72_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV72_Pos)      /*!< 0x00000100 */
+#define EXTI_PRIVCFGR3_PRIV72        EXTI_PRIVCFGR3_PRIV72_Msk                 /*!< Privilege enable on line 72 */
+#define EXTI_PRIVCFGR3_PRIV73_Pos    (9U)
+#define EXTI_PRIVCFGR3_PRIV73_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV73_Pos)      /*!< 0x00000200 */
+#define EXTI_PRIVCFGR3_PRIV73        EXTI_PRIVCFGR3_PRIV73_Msk                 /*!< Privilege enable on line 73 */
+#define EXTI_PRIVCFGR3_PRIV74_Pos    (10U)
+#define EXTI_PRIVCFGR3_PRIV74_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV74_Pos)      /*!< 0x00000400 */
+#define EXTI_PRIVCFGR3_PRIV74        EXTI_PRIVCFGR3_PRIV74_Msk                 /*!< Privilege enable on line 74 */
+#define EXTI_PRIVCFGR3_PRIV77_Pos    (13U)
+#define EXTI_PRIVCFGR3_PRIV77_Msk    (0x1UL << EXTI_PRIVCFGR3_PRIV77_Pos)      /*!< 0x00002000 */
+#define EXTI_PRIVCFGR3_PRIV77        EXTI_PRIVCFGR3_PRIV77_Msk                 /*!< Privilege enable on line 77 */
+
+/*****************  Bit definition for EXTI_EXTICR1 register  **************/
+#define EXTI_EXTICR1_EXTI0_Pos       (0U)
+#define EXTI_EXTICR1_EXTI0_Msk       (0xFFUL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
+#define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR1_EXTI0_3         (0x8UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR1_EXTI0_4         (0x10UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR1_EXTI0_5         (0x20UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR1_EXTI0_6         (0x40UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR1_EXTI0_7         (0x80UL << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR1_EXTI1_Pos       (8U)
+#define EXTI_EXTICR1_EXTI1_Msk       (0xFFUL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
+#define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR1_EXTI1_3         (0x8UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR1_EXTI1_4         (0x10UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR1_EXTI1_5         (0x20UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR1_EXTI1_6         (0x40UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR1_EXTI1_7         (0x80UL << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR1_EXTI2_Pos       (16U)
+#define EXTI_EXTICR1_EXTI2_Msk       (0xFFUL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
+#define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR1_EXTI2_3         (0x8UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR1_EXTI2_4         (0x10UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR1_EXTI2_5         (0x20UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR1_EXTI2_6         (0x40UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR1_EXTI2_7         (0x80UL << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR1_EXTI3_Pos       (24U)
+#define EXTI_EXTICR1_EXTI3_Msk       (0xFFUL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
+#define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR1_EXTI3_3         (0x8UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR1_EXTI3_4         (0x10UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR1_EXTI3_5         (0x20UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR1_EXTI3_6         (0x40UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR1_EXTI3_7         (0x80UL << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR2 register  **************/
+#define EXTI_EXTICR2_EXTI4_Pos       (0U)
+#define EXTI_EXTICR2_EXTI4_Msk       (0xFFUL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
+#define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR2_EXTI4_3         (0x8UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR2_EXTI4_4         (0x10UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR2_EXTI4_5         (0x20UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR2_EXTI4_6         (0x40UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR2_EXTI4_7         (0x80UL << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR2_EXTI5_Pos       (8U)
+#define EXTI_EXTICR2_EXTI5_Msk       (0xFFUL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
+#define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR2_EXTI5_3         (0x8UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR2_EXTI5_4         (0x10UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR2_EXTI5_5         (0x20UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR2_EXTI5_6         (0x40UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR2_EXTI5_7         (0x80UL << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR2_EXTI6_Pos       (16U)
+#define EXTI_EXTICR2_EXTI6_Msk       (0xFFUL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00FF0000 */
+#define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
+#define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
+#define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
+#define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
+#define EXTI_EXTICR2_EXTI6_3         (0x8UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00080000 */
+#define EXTI_EXTICR2_EXTI6_4         (0x10UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00100000 */
+#define EXTI_EXTICR2_EXTI6_5         (0x20UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00200000 */
+#define EXTI_EXTICR2_EXTI6_6         (0x40UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00400000 */
+#define EXTI_EXTICR2_EXTI6_7         (0x80UL << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x00800000 */
+#define EXTI_EXTICR2_EXTI7_Pos       (24U)
+#define EXTI_EXTICR2_EXTI7_Msk       (0xFFUL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0xFF000000 */
+#define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
+#define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
+#define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
+#define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
+#define EXTI_EXTICR2_EXTI7_3         (0x8UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x08000000 */
+#define EXTI_EXTICR2_EXTI7_4         (0x10UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x10000000 */
+#define EXTI_EXTICR2_EXTI7_5         (0x20UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x20000000 */
+#define EXTI_EXTICR2_EXTI7_6         (0x40UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x40000000 */
+#define EXTI_EXTICR2_EXTI7_7         (0x80UL << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR3 register  **************/
+#define EXTI_EXTICR3_EXTI8_Pos       (0U)
+#define EXTI_EXTICR3_EXTI8_Msk       (0xFFUL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x000000FF */
+#define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
+#define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
+#define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
+#define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
+#define EXTI_EXTICR3_EXTI8_3         (0x8UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000008 */
+#define EXTI_EXTICR3_EXTI8_4         (0x10UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000010 */
+#define EXTI_EXTICR3_EXTI8_5         (0x20UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000020 */
+#define EXTI_EXTICR3_EXTI8_6         (0x40UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000040 */
+#define EXTI_EXTICR3_EXTI8_7         (0x80UL << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x00000080 */
+#define EXTI_EXTICR3_EXTI9_Pos       (8U)
+#define EXTI_EXTICR3_EXTI9_Msk       (0xFFUL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x0000FF00 */
+#define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
+#define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
+#define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
+#define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
+#define EXTI_EXTICR3_EXTI9_3         (0x8UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000800 */
+#define EXTI_EXTICR3_EXTI9_4         (0x10UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00001000 */
+#define EXTI_EXTICR3_EXTI9_5         (0x20UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00002000 */
+#define EXTI_EXTICR3_EXTI9_6         (0x40UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00004000 */
+#define EXTI_EXTICR3_EXTI9_7         (0x80UL << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00008000 */
+#define EXTI_EXTICR3_EXTI10_Pos      (16U)
+#define EXTI_EXTICR3_EXTI10_Msk      (0xFFUL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
+#define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR3_EXTI10_3        (0x8UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR3_EXTI10_4        (0x10UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR3_EXTI10_5        (0x20UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR3_EXTI10_6        (0x40UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR3_EXTI10_7        (0x80UL << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR3_EXTI11_Pos      (24U)
+#define EXTI_EXTICR3_EXTI11_Msk      (0xFFUL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
+#define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR3_EXTI11_3        (0x8UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR3_EXTI11_4        (0x10UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR3_EXTI11_5        (0x20UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR3_EXTI11_6        (0x40UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR3_EXTI11_7        (0x80UL << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x80000000 */
+
+/*****************  Bit definition for EXTI_EXTICR4 register  **************/
+#define EXTI_EXTICR4_EXTI12_Pos      (0U)
+#define EXTI_EXTICR4_EXTI12_Msk      (0xFFUL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x000000FF */
+#define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
+#define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
+#define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
+#define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
+#define EXTI_EXTICR4_EXTI12_3        (0x8UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000008 */
+#define EXTI_EXTICR4_EXTI12_4        (0x10UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000010 */
+#define EXTI_EXTICR4_EXTI12_5        (0x20UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000020 */
+#define EXTI_EXTICR4_EXTI12_6        (0x40UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000040 */
+#define EXTI_EXTICR4_EXTI12_7        (0x80UL << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x00000080 */
+#define EXTI_EXTICR4_EXTI13_Pos      (8U)
+#define EXTI_EXTICR4_EXTI13_Msk      (0xFFUL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x0000FF00 */
+#define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
+#define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
+#define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000200 */
+#define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000400 */
+#define EXTI_EXTICR4_EXTI13_3        (0x8UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000800 */
+#define EXTI_EXTICR4_EXTI13_4        (0x10UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00001000 */
+#define EXTI_EXTICR4_EXTI13_5        (0x20UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00002000 */
+#define EXTI_EXTICR4_EXTI13_6        (0x40UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00004000 */
+#define EXTI_EXTICR4_EXTI13_7        (0x80UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00008000 */
+#define EXTI_EXTICR4_EXTI14_Pos      (16U)
+#define EXTI_EXTICR4_EXTI14_Msk      (0xFFUL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00FF0000 */
+#define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
+#define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
+#define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
+#define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
+#define EXTI_EXTICR4_EXTI14_3        (0x8UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00080000 */
+#define EXTI_EXTICR4_EXTI14_4        (0x10UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00100000 */
+#define EXTI_EXTICR4_EXTI14_5        (0x20UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00200000 */
+#define EXTI_EXTICR4_EXTI14_6        (0x40UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00400000 */
+#define EXTI_EXTICR4_EXTI14_7        (0x80UL << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x00800000 */
+#define EXTI_EXTICR4_EXTI15_Pos      (24U)
+#define EXTI_EXTICR4_EXTI15_Msk      (0xFFUL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0xFF000000 */
+#define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
+#define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
+#define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
+#define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
+#define EXTI_EXTICR4_EXTI15_3        (0x8UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x08000000 */
+#define EXTI_EXTICR4_EXTI15_4        (0x10UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x10000000 */
+#define EXTI_EXTICR4_EXTI15_5        (0x20UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x20000000 */
+#define EXTI_EXTICR4_EXTI15_6        (0x40UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x40000000 */
+#define EXTI_EXTICR4_EXTI15_7        (0x80UL << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x80000000 */
+
+/*******************  Bit definition I_LOCKR register  ******************/
+#define EXTI_LOCKR_LOCK_Pos          (0U)
+#define EXTI_LOCKR_LOCK_Msk          (0x1UL << EXTI_LOCKR_LOCK_Pos)            /*!< 0x00000001 */
+#define EXTI_LOCKR_LOCK              EXTI_LOCKR_LOCK_Msk                       /*!< Security and privilege configuration lock */
+
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos            (0U)
+#define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
+#define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos            (1U)
+#define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
+#define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos            (2U)
+#define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
+#define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos            (3U)
+#define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
+#define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos            (4U)
+#define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
+#define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos            (5U)
+#define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
+#define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos            (6U)
+#define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
+#define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos            (7U)
+#define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
+#define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos            (8U)
+#define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
+#define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos            (9U)
+#define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
+#define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos           (10U)
+#define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos           (11U)
+#define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos           (12U)
+#define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos           (13U)
+#define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos           (14U)
+#define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos           (15U)
+#define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM17_Pos           (17U)
+#define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos           (18U)
+#define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos           (19U)
+#define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos           (20U)
+#define EXTI_IMR1_IM20_Msk           (0x1UL << EXTI_IMR1_IM20_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR1_IM20               EXTI_IMR1_IM20_Msk                        /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos           (21U)
+#define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos           (22U)
+#define EXTI_IMR1_IM22_Msk           (0x1UL << EXTI_IMR1_IM22_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR1_IM22               EXTI_IMR1_IM22_Msk                        /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos           (23U)
+#define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos           (24U)
+#define EXTI_IMR1_IM24_Msk           (0x1UL << EXTI_IMR1_IM24_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR1_IM24               EXTI_IMR1_IM24_Msk                        /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos           (25U)
+#define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos           (26U)
+#define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos           (27U)
+#define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */
+#define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos           (28U)
+#define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos           (29U)
+#define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos           (30U)
+#define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos           (31U)
+#define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos             (0U)
+#define EXTI_IMR1_IM_Msk             (0xFFFEFFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos            (0U)
+#define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
+#define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos            (1U)
+#define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
+#define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos            (2U)
+#define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
+#define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos            (3U)
+#define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
+#define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos            (4U)
+#define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
+#define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos            (5U)
+#define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
+#define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos            (6U)
+#define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
+#define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos            (7U)
+#define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
+#define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos            (8U)
+#define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
+#define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos            (9U)
+#define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
+#define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos           (10U)
+#define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos           (11U)
+#define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos           (12U)
+#define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos           (13U)
+#define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos           (14U)
+#define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos           (15U)
+#define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM17_Pos           (17U)
+#define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos           (18U)
+#define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos           (19U)
+#define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos           (20U)
+#define EXTI_EMR1_EM20_Msk           (0x1UL << EXTI_EMR1_EM20_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR1_EM20               EXTI_EMR1_EM20_Msk                        /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos           (21U)
+#define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos           (22U)
+#define EXTI_EMR1_EM22_Msk           (0x1UL << EXTI_EMR1_EM22_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR1_EM22               EXTI_EMR1_EM22_Msk                        /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos           (23U)
+#define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos           (24U)
+#define EXTI_EMR1_EM24_Msk           (0x1UL << EXTI_EMR1_EM24_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR1_EM24               EXTI_EMR1_EM24_Msk                        /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos           (25U)
+#define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos           (26U)
+#define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos           (27U)
+#define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */
+#define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos           (28U)
+#define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos           (29U)
+#define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos           (30U)
+#define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos           (31U)
+#define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */
+#define EXTI_EMR1_EM_Pos             (0U)
+#define EXTI_EMR1_EM_Msk             (0xFFFEFFFFUL << EXTI_EMR1_EM_Pos)        /*!< 0xFFFEFFFF */
+#define EXTI_EMR1_EM                 EXTI_EMR1_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos           (0U)
+#define EXTI_IMR2_IM32_Msk           (0x1UL << EXTI_IMR2_IM32_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR2_IM32               EXTI_IMR2_IM32_Msk                        /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos           (1U)
+#define EXTI_IMR2_IM33_Msk           (0x1UL << EXTI_IMR2_IM33_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR2_IM33               EXTI_IMR2_IM33_Msk                        /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos           (2U)
+#define EXTI_IMR2_IM34_Msk           (0x1UL << EXTI_IMR2_IM34_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR2_IM34               EXTI_IMR2_IM34_Msk                        /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos           (3U)
+#define EXTI_IMR2_IM35_Msk           (0x1UL << EXTI_IMR2_IM35_Pos)             /*!< 0x00000008 */
+#define EXTI_IMR2_IM35               EXTI_IMR2_IM35_Msk                        /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos           (4U)
+#define EXTI_IMR2_IM36_Msk           (0x1UL << EXTI_IMR2_IM36_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR2_IM36               EXTI_IMR2_IM36_Msk                        /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos           (5U)
+#define EXTI_IMR2_IM37_Msk           (0x1UL << EXTI_IMR2_IM37_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR2_IM37               EXTI_IMR2_IM37_Msk                        /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos           (6U)
+#define EXTI_IMR2_IM38_Msk           (0x1UL << EXTI_IMR2_IM38_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR2_IM38               EXTI_IMR2_IM38_Msk                        /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos           (7U)
+#define EXTI_IMR2_IM39_Msk           (0x1UL << EXTI_IMR2_IM39_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR2_IM39               EXTI_IMR2_IM39_Msk                        /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos           (8U)
+#define EXTI_IMR2_IM40_Msk           (0x1UL << EXTI_IMR2_IM40_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR2_IM40               EXTI_IMR2_IM40_Msk                        /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos           (9U)
+#define EXTI_IMR2_IM41_Msk           (0x1UL << EXTI_IMR2_IM41_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR2_IM41               EXTI_IMR2_IM41_Msk                        /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos           (10U)
+#define EXTI_IMR2_IM42_Msk           (0x1UL << EXTI_IMR2_IM42_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR2_IM42               EXTI_IMR2_IM42_Msk                        /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos           (11U)
+#define EXTI_IMR2_IM43_Msk           (0x1UL << EXTI_IMR2_IM43_Pos)             /*!< 0x00000800 */
+#define EXTI_IMR2_IM43               EXTI_IMR2_IM43_Msk                        /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos           (12U)
+#define EXTI_IMR2_IM44_Msk           (0x1UL << EXTI_IMR2_IM44_Pos)             /*!< 0x00001000 */
+#define EXTI_IMR2_IM44               EXTI_IMR2_IM44_Msk                        /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM45_Pos           (13U)
+#define EXTI_IMR2_IM45_Msk           (0x1UL << EXTI_IMR2_IM45_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR2_IM45               EXTI_IMR2_IM45_Msk                        /*!< Interrupt Mask on line 45 */
+#define EXTI_IMR2_IM46_Pos           (14U)
+#define EXTI_IMR2_IM46_Msk           (0x1UL << EXTI_IMR2_IM46_Pos)             /*!< 0x00004000 */
+#define EXTI_IMR2_IM46               EXTI_IMR2_IM46_Msk                        /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos           (15U)
+#define EXTI_IMR2_IM47_Msk           (0x1UL << EXTI_IMR2_IM47_Pos)             /*!< 0x00008000 */
+#define EXTI_IMR2_IM47               EXTI_IMR2_IM47_Msk                        /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos           (16U)
+#define EXTI_IMR2_IM48_Msk           (0x1UL << EXTI_IMR2_IM48_Pos)             /*!< 0x00010000 */
+#define EXTI_IMR2_IM48               EXTI_IMR2_IM48_Msk                        /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos           (17U)
+#define EXTI_IMR2_IM49_Msk           (0x1UL << EXTI_IMR2_IM49_Pos)             /*!< 0x00020000 */
+#define EXTI_IMR2_IM49               EXTI_IMR2_IM49_Msk                        /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos           (18U)
+#define EXTI_IMR2_IM50_Msk           (0x1UL << EXTI_IMR2_IM50_Pos)             /*!< 0x00040000 */
+#define EXTI_IMR2_IM50               EXTI_IMR2_IM50_Msk                        /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos           (19U)
+#define EXTI_IMR2_IM51_Msk           (0x1UL << EXTI_IMR2_IM51_Pos)             /*!< 0x00080000 */
+#define EXTI_IMR2_IM51               EXTI_IMR2_IM51_Msk                        /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos           (20U)
+#define EXTI_IMR2_IM52_Msk           (0x1UL << EXTI_IMR2_IM52_Pos)             /*!< 0x00100000 */
+#define EXTI_IMR2_IM52               EXTI_IMR2_IM52_Msk                        /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos           (21U)
+#define EXTI_IMR2_IM53_Msk           (0x1UL << EXTI_IMR2_IM53_Pos)             /*!< 0x00200000 */
+#define EXTI_IMR2_IM53               EXTI_IMR2_IM53_Msk                        /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos           (22U)
+#define EXTI_IMR2_IM54_Msk           (0x1UL << EXTI_IMR2_IM54_Pos)             /*!< 0x00400000 */
+#define EXTI_IMR2_IM54               EXTI_IMR2_IM54_Msk                        /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos           (23U)
+#define EXTI_IMR2_IM55_Msk           (0x1UL << EXTI_IMR2_IM55_Pos)             /*!< 0x00800000 */
+#define EXTI_IMR2_IM55               EXTI_IMR2_IM55_Msk                        /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos           (24U)
+#define EXTI_IMR2_IM56_Msk           (0x1UL << EXTI_IMR2_IM56_Pos)             /*!< 0x01000000 */
+#define EXTI_IMR2_IM56               EXTI_IMR2_IM56_Msk                        /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos           (25U)
+#define EXTI_IMR2_IM57_Msk           (0x1UL << EXTI_IMR2_IM57_Pos)             /*!< 0x02000000 */
+#define EXTI_IMR2_IM57               EXTI_IMR2_IM57_Msk                        /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos           (26U)
+#define EXTI_IMR2_IM58_Msk           (0x1UL << EXTI_IMR2_IM58_Pos)             /*!< 0x04000000 */
+#define EXTI_IMR2_IM58               EXTI_IMR2_IM58_Msk                        /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM60_Pos           (28U)
+#define EXTI_IMR2_IM60_Msk           (0x1UL << EXTI_IMR2_IM60_Pos)             /*!< 0x10000000 */
+#define EXTI_IMR2_IM60               EXTI_IMR2_IM60_Msk                        /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos           (29U)
+#define EXTI_IMR2_IM61_Msk           (0x1UL << EXTI_IMR2_IM61_Pos)             /*!< 0x20000000 */
+#define EXTI_IMR2_IM61               EXTI_IMR2_IM61_Msk                        /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos           (30U)
+#define EXTI_IMR2_IM62_Msk           (0x1UL << EXTI_IMR2_IM62_Pos)             /*!< 0x40000000 */
+#define EXTI_IMR2_IM62               EXTI_IMR2_IM62_Msk                        /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos           (31U)
+#define EXTI_IMR2_IM63_Msk           (0x1UL << EXTI_IMR2_IM63_Pos)             /*!< 0x80000000 */
+#define EXTI_IMR2_IM63               EXTI_IMR2_IM63_Msk                        /*!< Interrupt Mask on line 63 */
+#define EXTI_IMR2_IM_Pos             (0U)
+#define EXTI_IMR2_IM_Msk             (0xF7FFFFFFUL << EXTI_IMR2_IM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_IMR2_IM                 EXTI_IMR2_IM_Msk                          /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos           (0U)
+#define EXTI_EMR2_EM32_Msk           (0x1UL << EXTI_EMR2_EM32_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR2_EM32               EXTI_EMR2_EM32_Msk                        /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos           (1U)
+#define EXTI_EMR2_EM33_Msk           (0x1UL << EXTI_EMR2_EM33_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR2_EM33               EXTI_EMR2_EM33_Msk                        /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos           (2U)
+#define EXTI_EMR2_EM34_Msk           (0x1UL << EXTI_EMR2_EM34_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR2_EM34               EXTI_EMR2_EM34_Msk                        /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos           (3U)
+#define EXTI_EMR2_EM35_Msk           (0x1UL << EXTI_EMR2_EM35_Pos)             /*!< 0x00000008 */
+#define EXTI_EMR2_EM35               EXTI_EMR2_EM35_Msk                        /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos           (4U)
+#define EXTI_EMR2_EM36_Msk           (0x1UL << EXTI_EMR2_EM36_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR2_EM36               EXTI_EMR2_EM36_Msk                        /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos           (5U)
+#define EXTI_EMR2_EM37_Msk           (0x1UL << EXTI_EMR2_EM37_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR2_EM37               EXTI_EMR2_EM37_Msk                        /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos           (6U)
+#define EXTI_EMR2_EM38_Msk           (0x1UL << EXTI_EMR2_EM38_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR2_EM38               EXTI_EMR2_EM38_Msk                        /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos           (7U)
+#define EXTI_EMR2_EM39_Msk           (0x1UL << EXTI_EMR2_EM39_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR2_EM39               EXTI_EMR2_EM39_Msk                        /*!< Event Mask on line 39 */
+#define EXTI_EMR2_EM40_Pos           (8U)
+#define EXTI_EMR2_EM40_Msk           (0x1UL << EXTI_EMR2_EM40_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR2_EM40               EXTI_EMR2_EM40_Msk                        /*!< Event Mask on line 40 */
+#define EXTI_EMR2_EM41_Pos           (9U)
+#define EXTI_EMR2_EM41_Msk           (0x1UL << EXTI_EMR2_EM41_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR2_EM41               EXTI_EMR2_EM41_Msk                        /*!< Event Mask on line 41 */
+#define EXTI_EMR2_EM42_Pos           (10U)
+#define EXTI_EMR2_EM42_Msk           (0x1UL << EXTI_EMR2_EM42_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR2_EM42               EXTI_EMR2_EM42_Msk                        /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos           (11U)
+#define EXTI_EMR2_EM43_Msk           (0x1UL << EXTI_EMR2_EM43_Pos)             /*!< 0x00000800 */
+#define EXTI_EMR2_EM43               EXTI_EMR2_EM43_Msk                        /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos           (12U)
+#define EXTI_EMR2_EM44_Msk           (0x1UL << EXTI_EMR2_EM44_Pos)             /*!< 0x00001000 */
+#define EXTI_EMR2_EM44               EXTI_EMR2_EM44_Msk                        /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM45_Pos           (13U)
+#define EXTI_EMR2_EM45_Msk           (0x1UL << EXTI_EMR2_EM45_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR2_EM45               EXTI_EMR2_EM45_Msk                        /*!< Event Mask on line 45 */
+#define EXTI_EMR2_EM46_Pos           (14U)
+#define EXTI_EMR2_EM46_Msk           (0x1UL << EXTI_EMR2_EM46_Pos)             /*!< 0x00004000 */
+#define EXTI_EMR2_EM46               EXTI_EMR2_EM46_Msk                        /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos           (15U)
+#define EXTI_EMR2_EM47_Msk           (0x1UL << EXTI_EMR2_EM47_Pos)             /*!< 0x00008000 */
+#define EXTI_EMR2_EM47               EXTI_EMR2_EM47_Msk                        /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos           (16U)
+#define EXTI_EMR2_EM48_Msk           (0x1UL << EXTI_EMR2_EM48_Pos)             /*!< 0x00010000 */
+#define EXTI_EMR2_EM48               EXTI_EMR2_EM48_Msk                        /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos           (17U)
+#define EXTI_EMR2_EM49_Msk           (0x1UL << EXTI_EMR2_EM49_Pos)             /*!< 0x00020000 */
+#define EXTI_EMR2_EM49               EXTI_EMR2_EM49_Msk                        /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos           (18U)
+#define EXTI_EMR2_EM50_Msk           (0x1UL << EXTI_EMR2_EM50_Pos)             /*!< 0x00040000 */
+#define EXTI_EMR2_EM50               EXTI_EMR2_EM50_Msk                        /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos           (19U)
+#define EXTI_EMR2_EM51_Msk           (0x1UL << EXTI_EMR2_EM51_Pos)             /*!< 0x00080000 */
+#define EXTI_EMR2_EM51               EXTI_EMR2_EM51_Msk                        /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos           (20U)
+#define EXTI_EMR2_EM52_Msk           (0x1UL << EXTI_EMR2_EM52_Pos)             /*!< 0x00100000 */
+#define EXTI_EMR2_EM52               EXTI_EMR2_EM52_Msk                        /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos           (21U)
+#define EXTI_EMR2_EM53_Msk           (0x1UL << EXTI_EMR2_EM53_Pos)             /*!< 0x00200000 */
+#define EXTI_EMR2_EM53               EXTI_EMR2_EM53_Msk                        /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos           (22U)
+#define EXTI_EMR2_EM54_Msk           (0x1UL << EXTI_EMR2_EM54_Pos)             /*!< 0x00400000 */
+#define EXTI_EMR2_EM54               EXTI_EMR2_EM54_Msk                        /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos           (23U)
+#define EXTI_EMR2_EM55_Msk           (0x1UL << EXTI_EMR2_EM55_Pos)             /*!< 0x00800000 */
+#define EXTI_EMR2_EM55               EXTI_EMR2_EM55_Msk                        /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos           (24U)
+#define EXTI_EMR2_EM56_Msk           (0x1UL << EXTI_EMR2_EM56_Pos)             /*!< 0x01000000 */
+#define EXTI_EMR2_EM56               EXTI_EMR2_EM56_Msk                        /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos           (25U)
+#define EXTI_EMR2_EM57_Msk           (0x1UL << EXTI_EMR2_EM57_Pos)             /*!< 0x02000000 */
+#define EXTI_EMR2_EM57               EXTI_EMR2_EM57_Msk                        /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos           (26U)
+#define EXTI_EMR2_EM58_Msk           (0x1UL << EXTI_EMR2_EM58_Pos)             /*!< 0x04000000 */
+#define EXTI_EMR2_EM58               EXTI_EMR2_EM58_Msk                        /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM60_Pos           (28U)
+#define EXTI_EMR2_EM60_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x10000000 */
+#define EXTI_EMR2_EM60               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos           (29U)
+#define EXTI_EMR2_EM61_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x20000000 */
+#define EXTI_EMR2_EM61               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos           (30U)
+#define EXTI_EMR2_EM62_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x40000000 */
+#define EXTI_EMR2_EM62               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos           (31U)
+#define EXTI_EMR2_EM63_Msk           (0x1UL << EXTI_EMR2_EM60_Pos)             /*!< 0x80000000 */
+#define EXTI_EMR2_EM63               EXTI_EMR2_EM60_Msk                        /*!< Event Mask on line 63 */
+#define EXTI_EMR2_EM_Pos             (0U)
+#define EXTI_EMR2_EM_Msk             (0xF7FFFFFFUL << EXTI_EMR2_EM_Pos)        /*!< 0xF7FFFFFF */
+#define EXTI_EMR2_EM                 EXTI_EMR2_EM_Msk                          /*!< Event Mask All */
+
+/*******************  Bit definition for EXTI_IMR3 register  ******************/
+#define EXTI_IMR3_IM64_Pos           (0U)
+#define EXTI_IMR3_IM64_Msk           (0x1UL << EXTI_IMR3_IM64_Pos)             /*!< 0x00000001 */
+#define EXTI_IMR3_IM64               EXTI_IMR3_IM64_Msk                        /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos           (1U)
+#define EXTI_IMR3_IM65_Msk           (0x1UL << EXTI_IMR3_IM65_Pos)             /*!< 0x00000002 */
+#define EXTI_IMR3_IM65               EXTI_IMR3_IM65_Msk                        /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos           (2U)
+#define EXTI_IMR3_IM66_Msk           (0x1UL << EXTI_IMR3_IM66_Pos)             /*!< 0x00000004 */
+#define EXTI_IMR3_IM66               EXTI_IMR3_IM66_Msk                        /*!< Interrupt Mask on line 66  */
+#define EXTI_IMR3_IM68_Pos           (4U)
+#define EXTI_IMR3_IM68_Msk           (0x1UL << EXTI_IMR3_IM68_Pos)             /*!< 0x00000010 */
+#define EXTI_IMR3_IM68               EXTI_IMR3_IM68_Msk                        /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos           (5U)
+#define EXTI_IMR3_IM69_Msk           (0x1UL << EXTI_IMR3_IM69_Pos)             /*!< 0x00000020 */
+#define EXTI_IMR3_IM69               EXTI_IMR3_IM69_Msk                        /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos           (6U)
+#define EXTI_IMR3_IM70_Msk           (0x1UL << EXTI_IMR3_IM70_Pos)             /*!< 0x00000040 */
+#define EXTI_IMR3_IM70               EXTI_IMR3_IM70_Msk                        /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos           (7U)
+#define EXTI_IMR3_IM71_Msk           (0x1UL << EXTI_IMR3_IM71_Pos)             /*!< 0x00000080 */
+#define EXTI_IMR3_IM71               EXTI_IMR3_IM71_Msk                        /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos           (8U)
+#define EXTI_IMR3_IM72_Msk           (0x1UL << EXTI_IMR3_IM72_Pos)             /*!< 0x00000100 */
+#define EXTI_IMR3_IM72               EXTI_IMR3_IM72_Msk                        /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos           (9U)
+#define EXTI_IMR3_IM73_Msk           (0x1UL << EXTI_IMR3_IM73_Pos)             /*!< 0x00000200 */
+#define EXTI_IMR3_IM73               EXTI_IMR3_IM73_Msk                        /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos           (10U)
+#define EXTI_IMR3_IM74_Msk           (0x1UL << EXTI_IMR3_IM74_Pos)             /*!< 0x00000400 */
+#define EXTI_IMR3_IM74               EXTI_IMR3_IM74_Msk                        /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM77_Pos           (13U)
+#define EXTI_IMR3_IM77_Msk           (0x1UL << EXTI_IMR3_IM77_Pos)             /*!< 0x00002000 */
+#define EXTI_IMR3_IM77               EXTI_IMR3_IM77_Msk                        /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM_Pos             (0U)
+#define EXTI_IMR3_IM_Msk             (0x27F7UL << EXTI_IMR3_IM_Pos)             /*!< 0x000027F7 */
+#define EXTI_IMR3_IM                 EXTI_IMR3_IM_Msk                           /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR3 register  ******************/
+#define EXTI_EMR3_EM64_Pos           (0U)
+#define EXTI_EMR3_EM64_Msk           (0x1UL << EXTI_EMR3_EM64_Pos)             /*!< 0x00000001 */
+#define EXTI_EMR3_EM64               EXTI_EMR3_EM64_Msk                        /*!< Event Mask on line 64 */
+#define EXTI_EMR3_EM65_Pos           (1U)
+#define EXTI_EMR3_EM65_Msk           (0x1UL << EXTI_EMR3_EM65_Pos)             /*!< 0x00000002 */
+#define EXTI_EMR3_EM65               EXTI_EMR3_EM65_Msk                        /*!< Event Mask on line 65 */
+#define EXTI_EMR3_EM66_Pos           (2U)
+#define EXTI_EMR3_EM66_Msk           (0x1UL << EXTI_EMR3_EM66_Pos)             /*!< 0x00000004 */
+#define EXTI_EMR3_EM66               EXTI_EMR3_EM66_Msk                        /*!< Event Mask on line 66  */
+#define EXTI_EMR3_EM68_Pos           (4U)
+#define EXTI_EMR3_EM68_Msk           (0x1UL << EXTI_EMR3_EM68_Pos)             /*!< 0x00000010 */
+#define EXTI_EMR3_EM68               EXTI_EMR3_EM68_Msk                        /*!< Event Mask on line 68 */
+#define EXTI_EMR3_EM69_Pos           (5U)
+#define EXTI_EMR3_EM69_Msk           (0x1UL << EXTI_EMR3_EM69_Pos)             /*!< 0x00000020 */
+#define EXTI_EMR3_EM69               EXTI_EMR3_EM69_Msk                        /*!< Event Mask on line 69 */
+#define EXTI_EMR3_EM70_Pos           (6U)
+#define EXTI_EMR3_EM70_Msk           (0x1UL << EXTI_EMR3_EM70_Pos)             /*!< 0x00000040 */
+#define EXTI_EMR3_EM70               EXTI_EMR3_EM70_Msk                        /*!< Event Mask on line 70 */
+#define EXTI_EMR3_EM71_Pos           (7U)
+#define EXTI_EMR3_EM71_Msk           (0x1UL << EXTI_EMR3_EM71_Pos)             /*!< 0x00000080 */
+#define EXTI_EMR3_EM71               EXTI_EMR3_EM71_Msk                        /*!< Event Mask on line 71 */
+#define EXTI_EMR3_EM72_Pos           (8U)
+#define EXTI_EMR3_EM72_Msk           (0x1UL << EXTI_EMR3_EM72_Pos)             /*!< 0x00000100 */
+#define EXTI_EMR3_EM72               EXTI_EMR3_EM72_Msk                        /*!< Event Mask on line 72 */
+#define EXTI_EMR3_EM73_Pos           (9U)
+#define EXTI_EMR3_EM73_Msk           (0x1UL << EXTI_EMR3_EM73_Pos)             /*!< 0x00000200 */
+#define EXTI_EMR3_EM73               EXTI_EMR3_EM73_Msk                        /*!< Event Mask on line 73 */
+#define EXTI_EMR3_EM74_Pos           (10U)
+#define EXTI_EMR3_EM74_Msk           (0x1UL << EXTI_EMR3_EM74_Pos)             /*!< 0x00000400 */
+#define EXTI_EMR3_EM74               EXTI_EMR3_EM74_Msk                        /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM77_Pos           (13U)
+#define EXTI_EMR3_EM77_Msk           (0x1UL << EXTI_EMR3_EM77_Pos)             /*!< 0x00002000 */
+#define EXTI_EMR3_EM77               EXTI_EMR3_EM77_Msk                        /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM_Pos             (0U)
+#define EXTI_EMR3_EM_Msk             (0x27F7UL << EXTI_EMR3_EM_Pos)             /*!< 0x000027F7 */
+#define EXTI_EMR3_EM                 EXTI_EMR3_EM_Msk                           /*!< Event Mask All */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos           (0U)
+#define FDCAN_CREL_DAY_Msk           (0xFFUL << FDCAN_CREL_DAY_Pos)            /*!< 0x000000FF */
+#define FDCAN_CREL_DAY               FDCAN_CREL_DAY_Msk                        /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos           (8U)
+#define FDCAN_CREL_MON_Msk           (0xFFUL << FDCAN_CREL_MON_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON               FDCAN_CREL_MON_Msk                        /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos          (16U)
+#define FDCAN_CREL_YEAR_Msk          (0xFUL << FDCAN_CREL_YEAR_Pos)            /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR              FDCAN_CREL_YEAR_Msk                       /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos       (20U)
+#define FDCAN_CREL_SUBSTEP_Msk       (0xFUL << FDCAN_CREL_SUBSTEP_Pos)         /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP           FDCAN_CREL_SUBSTEP_Msk                    /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos          (24U)
+#define FDCAN_CREL_STEP_Msk          (0xFUL << FDCAN_CREL_STEP_Pos)            /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP              FDCAN_CREL_STEP_Msk                       /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos           (28U)
+#define FDCAN_CREL_REL_Msk           (0xFUL << FDCAN_CREL_REL_Pos)             /*!< 0xF0000000 */
+#define FDCAN_CREL_REL               FDCAN_CREL_REL_Msk                        /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos           (0U)
+#define FDCAN_ENDN_ETV_Msk           (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV               FDCAN_ENDN_ETV_Msk                        /*!<Endianness Test Value                   */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos          (0U)
+#define FDCAN_DBTP_DSJW_Msk          (0xFUL << FDCAN_DBTP_DSJW_Pos)            /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW              FDCAN_DBTP_DSJW_Msk                       /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos        (4U)
+#define FDCAN_DBTP_DTSEG2_Msk        (0xFUL << FDCAN_DBTP_DTSEG2_Pos)          /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2            FDCAN_DBTP_DTSEG2_Msk                     /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos        (8U)
+#define FDCAN_DBTP_DTSEG1_Msk        (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)         /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1            FDCAN_DBTP_DTSEG1_Msk                     /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos          (16U)
+#define FDCAN_DBTP_DBRP_Msk          (0x1FUL << FDCAN_DBTP_DBRP_Pos)           /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP              FDCAN_DBTP_DBRP_Msk                       /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos           (23U)
+#define FDCAN_DBTP_TDC_Msk           (0x1UL << FDCAN_DBTP_TDC_Pos)             /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC               FDCAN_DBTP_TDC_Msk                        /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos          (4U)
+#define FDCAN_TEST_LBCK_Msk          (0x1UL << FDCAN_TEST_LBCK_Pos)            /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK              FDCAN_TEST_LBCK_Msk                       /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos            (5U)
+#define FDCAN_TEST_TX_Msk            (0x3UL << FDCAN_TEST_TX_Pos)              /*!< 0x00000060 */
+#define FDCAN_TEST_TX                FDCAN_TEST_TX_Msk                         /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos            (7U)
+#define FDCAN_TEST_RX_Msk            (0x1UL << FDCAN_TEST_RX_Pos)              /*!< 0x00000080 */
+#define FDCAN_TEST_RX                FDCAN_TEST_RX_Msk                         /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos            (0U)
+#define FDCAN_RWD_WDC_Msk            (0xFFUL << FDCAN_RWD_WDC_Pos)             /*!< 0x000000FF */
+#define FDCAN_RWD_WDC                FDCAN_RWD_WDC_Msk                         /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos            (8U)
+#define FDCAN_RWD_WDV_Msk            (0xFFUL << FDCAN_RWD_WDV_Pos)             /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV                FDCAN_RWD_WDV_Msk                         /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  *******************/
+#define FDCAN_CCCR_INIT_Pos          (0U)
+#define FDCAN_CCCR_INIT_Msk          (0x1UL << FDCAN_CCCR_INIT_Pos)            /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT              FDCAN_CCCR_INIT_Msk                       /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos           (1U)
+#define FDCAN_CCCR_CCE_Msk           (0x1UL << FDCAN_CCCR_CCE_Pos)             /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE               FDCAN_CCCR_CCE_Msk                        /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos           (2U)
+#define FDCAN_CCCR_ASM_Msk           (0x1UL << FDCAN_CCCR_ASM_Pos)             /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM               FDCAN_CCCR_ASM_Msk                        /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos           (3U)
+#define FDCAN_CCCR_CSA_Msk           (0x1UL << FDCAN_CCCR_CSA_Pos)             /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA               FDCAN_CCCR_CSA_Msk                        /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos           (4U)
+#define FDCAN_CCCR_CSR_Msk           (0x1UL << FDCAN_CCCR_CSR_Pos)             /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR               FDCAN_CCCR_CSR_Msk                        /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos           (5U)
+#define FDCAN_CCCR_MON_Msk           (0x1UL << FDCAN_CCCR_MON_Pos)             /*!< 0x00000020 */
+#define FDCAN_CCCR_MON               FDCAN_CCCR_MON_Msk                        /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos           (6U)
+#define FDCAN_CCCR_DAR_Msk           (0x1UL << FDCAN_CCCR_DAR_Pos)             /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR               FDCAN_CCCR_DAR_Msk                        /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos          (7U)
+#define FDCAN_CCCR_TEST_Msk          (0x1UL << FDCAN_CCCR_TEST_Pos)            /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST              FDCAN_CCCR_TEST_Msk                       /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos          (8U)
+#define FDCAN_CCCR_FDOE_Msk          (0x1UL << FDCAN_CCCR_FDOE_Pos)            /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE              FDCAN_CCCR_FDOE_Msk                       /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos          (9U)
+#define FDCAN_CCCR_BRSE_Msk          (0x1UL << FDCAN_CCCR_BRSE_Pos)            /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE              FDCAN_CCCR_BRSE_Msk                       /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos          (12U)
+#define FDCAN_CCCR_PXHD_Msk          (0x1UL << FDCAN_CCCR_PXHD_Pos)            /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD              FDCAN_CCCR_PXHD_Msk                       /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos          (13U)
+#define FDCAN_CCCR_EFBI_Msk          (0x1UL << FDCAN_CCCR_EFBI_Pos)            /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI              FDCAN_CCCR_EFBI_Msk                       /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos           (14U)
+#define FDCAN_CCCR_TXP_Msk           (0x1UL << FDCAN_CCCR_TXP_Pos)             /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP               FDCAN_CCCR_TXP_Msk                        /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos          (15U)
+#define FDCAN_CCCR_NISO_Msk          (0x1UL << FDCAN_CCCR_NISO_Pos)            /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO              FDCAN_CCCR_NISO_Msk                       /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  *******************/
+#define FDCAN_NBTP_NTSEG2_Pos        (0U)
+#define FDCAN_NBTP_NTSEG2_Msk        (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)         /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2            FDCAN_NBTP_NTSEG2_Msk                     /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos        (8U)
+#define FDCAN_NBTP_NTSEG1_Msk        (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)         /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1            FDCAN_NBTP_NTSEG1_Msk                     /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos          (16U)
+#define FDCAN_NBTP_NBRP_Msk          (0x1FFUL << FDCAN_NBTP_NBRP_Pos)          /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP              FDCAN_NBTP_NBRP_Msk                       /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos          (25U)
+#define FDCAN_NBTP_NSJW_Msk          (0x7FUL << FDCAN_NBTP_NSJW_Pos)           /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW              FDCAN_NBTP_NSJW_Msk                       /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  *******************/
+#define FDCAN_TSCC_TSS_Pos           (0U)
+#define FDCAN_TSCC_TSS_Msk           (0x3UL << FDCAN_TSCC_TSS_Pos)             /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS               FDCAN_TSCC_TSS_Msk                        /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos           (16U)
+#define FDCAN_TSCC_TCP_Msk           (0xFUL << FDCAN_TSCC_TCP_Pos)             /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP               FDCAN_TSCC_TCP_Msk                        /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  *******************/
+#define FDCAN_TSCV_TSC_Pos           (0U)
+#define FDCAN_TSCV_TSC_Msk           (0xFFFFUL << FDCAN_TSCV_TSC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC               FDCAN_TSCV_TSC_Msk                        /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  *******************/
+#define FDCAN_TOCC_ETOC_Pos          (0U)
+#define FDCAN_TOCC_ETOC_Msk          (0x1UL << FDCAN_TOCC_ETOC_Pos)            /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC              FDCAN_TOCC_ETOC_Msk                       /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos           (1U)
+#define FDCAN_TOCC_TOS_Msk           (0x3UL << FDCAN_TOCC_TOS_Pos)             /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS               FDCAN_TOCC_TOS_Msk                        /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos           (16U)
+#define FDCAN_TOCC_TOP_Msk           (0xFFFFUL << FDCAN_TOCC_TOP_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP               FDCAN_TOCC_TOP_Msk                        /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  *******************/
+#define FDCAN_TOCV_TOC_Pos           (0U)
+#define FDCAN_TOCV_TOC_Msk           (0xFFFFUL << FDCAN_TOCV_TOC_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC               FDCAN_TOCV_TOC_Msk                        /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  ********************/
+#define FDCAN_ECR_TEC_Pos            (0U)
+#define FDCAN_ECR_TEC_Msk            (0xFFUL << FDCAN_ECR_TEC_Pos)             /*!< 0x000000FF */
+#define FDCAN_ECR_TEC                FDCAN_ECR_TEC_Msk                         /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos            (8U)
+#define FDCAN_ECR_REC_Msk            (0x7FUL << FDCAN_ECR_REC_Pos)             /*!< 0x00007F00 */
+#define FDCAN_ECR_REC                FDCAN_ECR_REC_Msk                         /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos             (15U)
+#define FDCAN_ECR_RP_Msk             (0x1UL << FDCAN_ECR_RP_Pos)               /*!< 0x00008000 */
+#define FDCAN_ECR_RP                 FDCAN_ECR_RP_Msk                          /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos            (16U)
+#define FDCAN_ECR_CEL_Msk            (0xFFUL << FDCAN_ECR_CEL_Pos)             /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL                FDCAN_ECR_CEL_Msk                         /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  ********************/
+#define FDCAN_PSR_LEC_Pos            (0U)
+#define FDCAN_PSR_LEC_Msk            (0x7UL << FDCAN_PSR_LEC_Pos)              /*!< 0x00000007 */
+#define FDCAN_PSR_LEC                FDCAN_PSR_LEC_Msk                         /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos            (3U)
+#define FDCAN_PSR_ACT_Msk            (0x3UL << FDCAN_PSR_ACT_Pos)              /*!< 0x00000018 */
+#define FDCAN_PSR_ACT                FDCAN_PSR_ACT_Msk                         /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos             (5U)
+#define FDCAN_PSR_EP_Msk             (0x1UL << FDCAN_PSR_EP_Pos)               /*!< 0x00000020 */
+#define FDCAN_PSR_EP                 FDCAN_PSR_EP_Msk                          /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos             (6U)
+#define FDCAN_PSR_EW_Msk             (0x1UL << FDCAN_PSR_EW_Pos)               /*!< 0x00000040 */
+#define FDCAN_PSR_EW                 FDCAN_PSR_EW_Msk                          /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos             (7U)
+#define FDCAN_PSR_BO_Msk             (0x1UL << FDCAN_PSR_BO_Pos)               /*!< 0x00000080 */
+#define FDCAN_PSR_BO                 FDCAN_PSR_BO_Msk                          /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos           (8U)
+#define FDCAN_PSR_DLEC_Msk           (0x7UL << FDCAN_PSR_DLEC_Pos)             /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC               FDCAN_PSR_DLEC_Msk                        /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos           (11U)
+#define FDCAN_PSR_RESI_Msk           (0x1UL << FDCAN_PSR_RESI_Pos)             /*!< 0x00000800 */
+#define FDCAN_PSR_RESI               FDCAN_PSR_RESI_Msk                        /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos           (12U)
+#define FDCAN_PSR_RBRS_Msk           (0x1UL << FDCAN_PSR_RBRS_Pos)             /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS               FDCAN_PSR_RBRS_Msk                        /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos           (13U)
+#define FDCAN_PSR_REDL_Msk           (0x1UL << FDCAN_PSR_REDL_Pos)             /*!< 0x00002000 */
+#define FDCAN_PSR_REDL               FDCAN_PSR_REDL_Msk                        /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos            (14U)
+#define FDCAN_PSR_PXE_Msk            (0x1UL << FDCAN_PSR_PXE_Pos)              /*!< 0x00004000 */
+#define FDCAN_PSR_PXE                FDCAN_PSR_PXE_Msk                         /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos           (16U)
+#define FDCAN_PSR_TDCV_Msk           (0x7FUL << FDCAN_PSR_TDCV_Pos)            /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV               FDCAN_PSR_TDCV_Msk                        /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  *******************/
+#define FDCAN_TDCR_TDCF_Pos          (0U)
+#define FDCAN_TDCR_TDCF_Msk          (0x7FUL << FDCAN_TDCR_TDCF_Pos)           /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF              FDCAN_TDCR_TDCF_Msk                       /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos          (8U)
+#define FDCAN_TDCR_TDCO_Msk          (0x7FUL << FDCAN_TDCR_TDCO_Pos)           /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO              FDCAN_TDCR_TDCO_Msk                       /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  *********************/
+#define FDCAN_IR_RF0N_Pos            (0U)
+#define FDCAN_IR_RF0N_Msk            (0x1UL << FDCAN_IR_RF0N_Pos)              /*!< 0x00000001 */
+#define FDCAN_IR_RF0N                FDCAN_IR_RF0N_Msk                         /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos            (1U)
+#define FDCAN_IR_RF0W_Msk            (0x1UL << FDCAN_IR_RF0W_Pos)              /*!< 0x00000002 */
+#define FDCAN_IR_RF0W                FDCAN_IR_RF0W_Msk                         /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos            (2U)
+#define FDCAN_IR_RF0F_Msk            (0x1UL << FDCAN_IR_RF0F_Pos)              /*!< 0x00000004 */
+#define FDCAN_IR_RF0F                FDCAN_IR_RF0F_Msk                         /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos            (3U)
+#define FDCAN_IR_RF0L_Msk            (0x1UL << FDCAN_IR_RF0L_Pos)              /*!< 0x00000008 */
+#define FDCAN_IR_RF0L                FDCAN_IR_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos            (4U)
+#define FDCAN_IR_RF1N_Msk            (0x1UL << FDCAN_IR_RF1N_Pos)              /*!< 0x00000010 */
+#define FDCAN_IR_RF1N                FDCAN_IR_RF1N_Msk                         /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos            (5U)
+#define FDCAN_IR_RF1W_Msk            (0x1UL << FDCAN_IR_RF1W_Pos)              /*!< 0x00000020 */
+#define FDCAN_IR_RF1W                FDCAN_IR_RF1W_Msk                         /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos            (6U)
+#define FDCAN_IR_RF1F_Msk            (0x1UL << FDCAN_IR_RF1F_Pos)              /*!< 0x00000040 */
+#define FDCAN_IR_RF1F                FDCAN_IR_RF1F_Msk                         /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos            (7U)
+#define FDCAN_IR_RF1L_Msk            (0x1UL << FDCAN_IR_RF1L_Pos)              /*!< 0x00000080 */
+#define FDCAN_IR_RF1L                FDCAN_IR_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos             (8U)
+#define FDCAN_IR_HPM_Msk             (0x1UL << FDCAN_IR_HPM_Pos)               /*!< 0x00000100 */
+#define FDCAN_IR_HPM                 FDCAN_IR_HPM_Msk                          /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos              (9U)
+#define FDCAN_IR_TC_Msk              (0x1UL << FDCAN_IR_TC_Pos)                /*!< 0x00000200 */
+#define FDCAN_IR_TC                  FDCAN_IR_TC_Msk                           /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos             (10U)
+#define FDCAN_IR_TCF_Msk             (0x1UL << FDCAN_IR_TCF_Pos)               /*!< 0x00000400 */
+#define FDCAN_IR_TCF                 FDCAN_IR_TCF_Msk                          /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos             (11U)
+#define FDCAN_IR_TFE_Msk             (0x1UL << FDCAN_IR_TFE_Pos)               /*!< 0x00000800 */
+#define FDCAN_IR_TFE                 FDCAN_IR_TFE_Msk                          /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos            (12U)
+#define FDCAN_IR_TEFN_Msk            (0x1UL << FDCAN_IR_TEFN_Pos)              /*!< 0x00001000 */
+#define FDCAN_IR_TEFN                FDCAN_IR_TEFN_Msk                         /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos            (13U)
+#define FDCAN_IR_TEFW_Msk            (0x1UL << FDCAN_IR_TEFW_Pos)              /*!< 0x00002000 */
+#define FDCAN_IR_TEFW                FDCAN_IR_TEFW_Msk                         /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos            (14U)
+#define FDCAN_IR_TEFF_Msk            (0x1UL << FDCAN_IR_TEFF_Pos)              /*!< 0x00004000 */
+#define FDCAN_IR_TEFF                FDCAN_IR_TEFF_Msk                         /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos            (15U)
+#define FDCAN_IR_TEFL_Msk            (0x1UL << FDCAN_IR_TEFL_Pos)              /*!< 0x00008000 */
+#define FDCAN_IR_TEFL                FDCAN_IR_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos             (16U)
+#define FDCAN_IR_TSW_Msk             (0x1UL << FDCAN_IR_TSW_Pos)               /*!< 0x00010000 */
+#define FDCAN_IR_TSW                 FDCAN_IR_TSW_Msk                          /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos            (17U)
+#define FDCAN_IR_MRAF_Msk            (0x1UL << FDCAN_IR_MRAF_Pos)              /*!< 0x00020000 */
+#define FDCAN_IR_MRAF                FDCAN_IR_MRAF_Msk                         /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos             (18U)
+#define FDCAN_IR_TOO_Msk             (0x1UL << FDCAN_IR_TOO_Pos)               /*!< 0x00040000 */
+#define FDCAN_IR_TOO                 FDCAN_IR_TOO_Msk                          /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos             (19U)
+#define FDCAN_IR_DRX_Msk             (0x1UL << FDCAN_IR_DRX_Pos)               /*!< 0x00080000 */
+#define FDCAN_IR_DRX                 FDCAN_IR_DRX_Msk                          /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos             (22U)
+#define FDCAN_IR_ELO_Msk             (0x1UL << FDCAN_IR_ELO_Pos)               /*!< 0x00400000 */
+#define FDCAN_IR_ELO                 FDCAN_IR_ELO_Msk                          /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos              (23U)
+#define FDCAN_IR_EP_Msk              (0x1UL << FDCAN_IR_EP_Pos)                /*!< 0x00800000 */
+#define FDCAN_IR_EP                  FDCAN_IR_EP_Msk                           /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos              (24U)
+#define FDCAN_IR_EW_Msk              (0x1UL << FDCAN_IR_EW_Pos)                /*!< 0x01000000 */
+#define FDCAN_IR_EW                  FDCAN_IR_EW_Msk                           /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos              (25U)
+#define FDCAN_IR_BO_Msk              (0x1UL << FDCAN_IR_BO_Pos)                /*!< 0x02000000 */
+#define FDCAN_IR_BO                  FDCAN_IR_BO_Msk                           /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos             (26U)
+#define FDCAN_IR_WDI_Msk             (0x1UL << FDCAN_IR_WDI_Pos)               /*!< 0x04000000 */
+#define FDCAN_IR_WDI                 FDCAN_IR_WDI_Msk                          /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos             (27U)
+#define FDCAN_IR_PEA_Msk             (0x1UL << FDCAN_IR_PEA_Pos)               /*!< 0x08000000 */
+#define FDCAN_IR_PEA                 FDCAN_IR_PEA_Msk                          /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos             (28U)
+#define FDCAN_IR_PED_Msk             (0x1UL << FDCAN_IR_PED_Pos)               /*!< 0x10000000 */
+#define FDCAN_IR_PED                 FDCAN_IR_PED_Msk                          /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos             (29U)
+#define FDCAN_IR_ARA_Msk             (0x1UL << FDCAN_IR_ARA_Pos)               /*!< 0x20000000 */
+#define FDCAN_IR_ARA                 FDCAN_IR_ARA_Msk                          /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  *********************/
+#define FDCAN_IE_RF0NE_Pos           (0U)
+#define FDCAN_IE_RF0NE_Msk           (0x1UL << FDCAN_IE_RF0NE_Pos)             /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE               FDCAN_IE_RF0NE_Msk                        /*!<Rx FIFO 0 New Message Enable             */
+#define FDCAN_IE_RF0WE_Pos           (1U)
+#define FDCAN_IE_RF0WE_Msk           (0x1UL << FDCAN_IE_RF0WE_Pos)             /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE               FDCAN_IE_RF0WE_Msk                        /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos           (2U)
+#define FDCAN_IE_RF0FE_Msk           (0x1UL << FDCAN_IE_RF0FE_Pos)             /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE               FDCAN_IE_RF0FE_Msk                        /*!<Rx FIFO 0 Full Enable                    */
+#define FDCAN_IE_RF0LE_Pos           (3U)
+#define FDCAN_IE_RF0LE_Msk           (0x1UL << FDCAN_IE_RF0LE_Pos)             /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE               FDCAN_IE_RF0LE_Msk                        /*!<Rx FIFO 0 Message Lost Enable            */
+#define FDCAN_IE_RF1NE_Pos           (4U)
+#define FDCAN_IE_RF1NE_Msk           (0x1UL << FDCAN_IE_RF1NE_Pos)             /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE               FDCAN_IE_RF1NE_Msk                        /*!<Rx FIFO 1 New Message Enable             */
+#define FDCAN_IE_RF1WE_Pos           (5U)
+#define FDCAN_IE_RF1WE_Msk           (0x1UL << FDCAN_IE_RF1WE_Pos)             /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE               FDCAN_IE_RF1WE_Msk                        /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos           (6U)
+#define FDCAN_IE_RF1FE_Msk           (0x1UL << FDCAN_IE_RF1FE_Pos)             /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE               FDCAN_IE_RF1FE_Msk                        /*!<Rx FIFO 1 Full Enable                    */
+#define FDCAN_IE_RF1LE_Pos           (7U)
+#define FDCAN_IE_RF1LE_Msk           (0x1UL << FDCAN_IE_RF1LE_Pos)             /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE               FDCAN_IE_RF1LE_Msk                        /*!<Rx FIFO 1 Message Lost Enable            */
+#define FDCAN_IE_HPME_Pos            (8U)
+#define FDCAN_IE_HPME_Msk            (0x1UL << FDCAN_IE_HPME_Pos)              /*!< 0x00000100 */
+#define FDCAN_IE_HPME                FDCAN_IE_HPME_Msk                         /*!<High Priority Message Enable             */
+#define FDCAN_IE_TCE_Pos             (9U)
+#define FDCAN_IE_TCE_Msk             (0x1UL << FDCAN_IE_TCE_Pos)               /*!< 0x00000200 */
+#define FDCAN_IE_TCE                 FDCAN_IE_TCE_Msk                          /*!<Transmission Completed Enable            */
+#define FDCAN_IE_TCFE_Pos            (10U)
+#define FDCAN_IE_TCFE_Msk            (0x1UL << FDCAN_IE_TCFE_Pos)              /*!< 0x00000400 */
+#define FDCAN_IE_TCFE                FDCAN_IE_TCFE_Msk                         /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos            (11U)
+#define FDCAN_IE_TFEE_Msk            (0x1UL << FDCAN_IE_TFEE_Pos)              /*!< 0x00000800 */
+#define FDCAN_IE_TFEE                FDCAN_IE_TFEE_Msk                         /*!<Tx FIFO Empty Enable                     */
+#define FDCAN_IE_TEFNE_Pos           (12U)
+#define FDCAN_IE_TEFNE_Msk           (0x1UL << FDCAN_IE_TEFNE_Pos)             /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE               FDCAN_IE_TEFNE_Msk                        /*!<Tx Event FIFO New Entry Enable           */
+#define FDCAN_IE_TEFWE_Pos           (13U)
+#define FDCAN_IE_TEFWE_Msk           (0x1UL << FDCAN_IE_TEFWE_Pos)             /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE               FDCAN_IE_TEFWE_Msk                        /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos           (14U)
+#define FDCAN_IE_TEFFE_Msk           (0x1UL << FDCAN_IE_TEFFE_Pos)             /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE               FDCAN_IE_TEFFE_Msk                        /*!<Tx Event FIFO Full Enable                */
+#define FDCAN_IE_TEFLE_Pos           (15U)
+#define FDCAN_IE_TEFLE_Msk           (0x1UL << FDCAN_IE_TEFLE_Pos)             /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE               FDCAN_IE_TEFLE_Msk                        /*!<Tx Event FIFO Element Lost Enable        */
+#define FDCAN_IE_TSWE_Pos            (16U)
+#define FDCAN_IE_TSWE_Msk            (0x1UL << FDCAN_IE_TSWE_Pos)              /*!< 0x00010000 */
+#define FDCAN_IE_TSWE                FDCAN_IE_TSWE_Msk                         /*!<Timestamp Wraparound Enable              */
+#define FDCAN_IE_MRAFE_Pos           (17U)
+#define FDCAN_IE_MRAFE_Msk           (0x1UL << FDCAN_IE_MRAFE_Pos)             /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE               FDCAN_IE_MRAFE_Msk                        /*!<Message RAM Access Failure Enable        */
+#define FDCAN_IE_TOOE_Pos            (18U)
+#define FDCAN_IE_TOOE_Msk            (0x1UL << FDCAN_IE_TOOE_Pos)              /*!< 0x00040000 */
+#define FDCAN_IE_TOOE                FDCAN_IE_TOOE_Msk                         /*!<Timeout Occurred Enable                  */
+#define FDCAN_IE_DRXE_Pos            (19U)
+#define FDCAN_IE_DRXE_Msk            (0x1UL << FDCAN_IE_DRXE_Pos)              /*!< 0x00080000 */
+#define FDCAN_IE_DRXE                FDCAN_IE_DRXE_Msk                         /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos            (20U)
+#define FDCAN_IE_BECE_Msk            (0x1UL << FDCAN_IE_BECE_Pos)              /*!< 0x00100000 */
+#define FDCAN_IE_BECE                FDCAN_IE_BECE_Msk                         /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos            (21U)
+#define FDCAN_IE_BEUE_Msk            (0x1UL << FDCAN_IE_BEUE_Pos)              /*!< 0x00200000 */
+#define FDCAN_IE_BEUE                FDCAN_IE_BEUE_Msk                         /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos            (22U)
+#define FDCAN_IE_ELOE_Msk            (0x1UL << FDCAN_IE_ELOE_Pos)              /*!< 0x00400000 */
+#define FDCAN_IE_ELOE                FDCAN_IE_ELOE_Msk                         /*!<Error Logging Overflow Enable            */
+#define FDCAN_IE_EPE_Pos             (23U)
+#define FDCAN_IE_EPE_Msk             (0x1UL << FDCAN_IE_EPE_Pos)               /*!< 0x00800000 */
+#define FDCAN_IE_EPE                 FDCAN_IE_EPE_Msk                          /*!<Error Passive Enable                     */
+#define FDCAN_IE_EWE_Pos             (24U)
+#define FDCAN_IE_EWE_Msk             (0x1UL << FDCAN_IE_EWE_Pos)               /*!< 0x01000000 */
+#define FDCAN_IE_EWE                 FDCAN_IE_EWE_Msk                          /*!<Warning Status Enable                    */
+#define FDCAN_IE_BOE_Pos             (25U)
+#define FDCAN_IE_BOE_Msk             (0x1UL << FDCAN_IE_BOE_Pos)               /*!< 0x02000000 */
+#define FDCAN_IE_BOE                 FDCAN_IE_BOE_Msk                          /*!<Bus_Off Status Enable                    */
+#define FDCAN_IE_WDIE_Pos            (26U)
+#define FDCAN_IE_WDIE_Msk            (0x1UL << FDCAN_IE_WDIE_Pos)              /*!< 0x04000000 */
+#define FDCAN_IE_WDIE                FDCAN_IE_WDIE_Msk                         /*!<Watchdog Interrupt Enable                */
+#define FDCAN_IE_PEAE_Pos            (27U)
+#define FDCAN_IE_PEAE_Msk            (0x1UL << FDCAN_IE_PEAE_Pos)              /*!< 0x08000000 */
+#define FDCAN_IE_PEAE                FDCAN_IE_PEAE_Msk                         /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos            (28U)
+#define FDCAN_IE_PEDE_Msk            (0x1UL << FDCAN_IE_PEDE_Pos)              /*!< 0x10000000 */
+#define FDCAN_IE_PEDE                FDCAN_IE_PEDE_Msk                         /*!<Protocol Error in Data Phase Enable      */
+#define FDCAN_IE_ARAE_Pos            (29U)
+#define FDCAN_IE_ARAE_Msk            (0x1UL << FDCAN_IE_ARAE_Pos)              /*!< 0x20000000 */
+#define FDCAN_IE_ARAE                FDCAN_IE_ARAE_Msk                         /*!<Access to Reserved Address Enable        */
+
+/*****************  Bit definition for FDCAN_ILS register  ********************/
+#define FDCAN_ILS_RF0NL_Pos          (0U)
+#define FDCAN_ILS_RF0NL_Msk          (0x1UL << FDCAN_ILS_RF0NL_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL              FDCAN_ILS_RF0NL_Msk                       /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos          (1U)
+#define FDCAN_ILS_RF0WL_Msk          (0x1UL << FDCAN_ILS_RF0WL_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL              FDCAN_ILS_RF0WL_Msk                       /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos          (2U)
+#define FDCAN_ILS_RF0FL_Msk          (0x1UL << FDCAN_ILS_RF0FL_Pos)            /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL              FDCAN_ILS_RF0FL_Msk                       /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos          (3U)
+#define FDCAN_ILS_RF0LL_Msk          (0x1UL << FDCAN_ILS_RF0LL_Pos)            /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL              FDCAN_ILS_RF0LL_Msk                       /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos          (4U)
+#define FDCAN_ILS_RF1NL_Msk          (0x1UL << FDCAN_ILS_RF1NL_Pos)            /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL              FDCAN_ILS_RF1NL_Msk                       /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos          (5U)
+#define FDCAN_ILS_RF1WL_Msk          (0x1UL << FDCAN_ILS_RF1WL_Pos)            /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL              FDCAN_ILS_RF1WL_Msk                       /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos          (6U)
+#define FDCAN_ILS_RF1FL_Msk          (0x1UL << FDCAN_ILS_RF1FL_Pos)            /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL              FDCAN_ILS_RF1FL_Msk                       /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos          (7U)
+#define FDCAN_ILS_RF1LL_Msk          (0x1UL << FDCAN_ILS_RF1LL_Pos)            /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL              FDCAN_ILS_RF1LL_Msk                       /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos           (8U)
+#define FDCAN_ILS_HPML_Msk           (0x1UL << FDCAN_ILS_HPML_Pos)             /*!< 0x00000100 */
+#define FDCAN_ILS_HPML               FDCAN_ILS_HPML_Msk                        /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos            (9U)
+#define FDCAN_ILS_TCL_Msk            (0x1UL << FDCAN_ILS_TCL_Pos)              /*!< 0x00000200 */
+#define FDCAN_ILS_TCL                FDCAN_ILS_TCL_Msk                         /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos           (10U)
+#define FDCAN_ILS_TCFL_Msk           (0x1UL << FDCAN_ILS_TCFL_Pos)             /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL               FDCAN_ILS_TCFL_Msk                        /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos           (11U)
+#define FDCAN_ILS_TFEL_Msk           (0x1UL << FDCAN_ILS_TFEL_Pos)             /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL               FDCAN_ILS_TFEL_Msk                        /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos          (12U)
+#define FDCAN_ILS_TEFNL_Msk          (0x1UL << FDCAN_ILS_TEFNL_Pos)            /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL              FDCAN_ILS_TEFNL_Msk                       /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos          (13U)
+#define FDCAN_ILS_TEFWL_Msk          (0x1UL << FDCAN_ILS_TEFWL_Pos)            /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL              FDCAN_ILS_TEFWL_Msk                       /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos          (14U)
+#define FDCAN_ILS_TEFFL_Msk          (0x1UL << FDCAN_ILS_TEFFL_Pos)            /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL              FDCAN_ILS_TEFFL_Msk                       /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos          (15U)
+#define FDCAN_ILS_TEFLL_Msk          (0x1UL << FDCAN_ILS_TEFLL_Pos)            /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL              FDCAN_ILS_TEFLL_Msk                       /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos           (16U)
+#define FDCAN_ILS_TSWL_Msk           (0x1UL << FDCAN_ILS_TSWL_Pos)             /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL               FDCAN_ILS_TSWL_Msk                        /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFL_Pos          (17U)
+#define FDCAN_ILS_MRAFL_Msk          (0x1UL << FDCAN_ILS_MRAFL_Pos)            /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFL              FDCAN_ILS_MRAFL_Msk                       /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOL_Pos           (18U)
+#define FDCAN_ILS_TOOL_Msk           (0x1UL << FDCAN_ILS_TOOL_Pos)             /*!< 0x00040000 */
+#define FDCAN_ILS_TOOL               FDCAN_ILS_TOOL_Msk                        /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXL_Pos           (19U)
+#define FDCAN_ILS_DRXL_Msk           (0x1UL << FDCAN_ILS_DRXL_Pos)             /*!< 0x00080000 */
+#define FDCAN_ILS_DRXL               FDCAN_ILS_DRXL_Msk                        /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_ELOL_Pos           (22U)
+#define FDCAN_ILS_ELOL_Msk           (0x1UL << FDCAN_ILS_ELOL_Pos)             /*!< 0x00400000 */
+#define FDCAN_ILS_ELOL               FDCAN_ILS_ELOL_Msk                        /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPL_Pos            (23U)
+#define FDCAN_ILS_EPL_Msk            (0x1UL << FDCAN_ILS_EPL_Pos)              /*!< 0x00800000 */
+#define FDCAN_ILS_EPL                FDCAN_ILS_EPL_Msk                         /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWL_Pos            (24U)
+#define FDCAN_ILS_EWL_Msk            (0x1UL << FDCAN_ILS_EWL_Pos)              /*!< 0x01000000 */
+#define FDCAN_ILS_EWL                FDCAN_ILS_EWL_Msk                         /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOL_Pos            (25U)
+#define FDCAN_ILS_BOL_Msk            (0x1UL << FDCAN_ILS_BOL_Pos)              /*!< 0x02000000 */
+#define FDCAN_ILS_BOL                FDCAN_ILS_BOL_Msk                         /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIL_Pos           (26U)
+#define FDCAN_ILS_WDIL_Msk           (0x1UL << FDCAN_ILS_WDIL_Pos)             /*!< 0x04000000 */
+#define FDCAN_ILS_WDIL               FDCAN_ILS_WDIL_Msk                        /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAL_Pos           (27U)
+#define FDCAN_ILS_PEAL_Msk           (0x1UL << FDCAN_ILS_PEAL_Pos)             /*!< 0x08000000 */
+#define FDCAN_ILS_PEAL               FDCAN_ILS_PEAL_Msk                        /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDL_Pos           (28U)
+#define FDCAN_ILS_PEDL_Msk           (0x1UL << FDCAN_ILS_PEDL_Pos)             /*!< 0x10000000 */
+#define FDCAN_ILS_PEDL               FDCAN_ILS_PEDL_Msk                        /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAL_Pos           (29U)
+#define FDCAN_ILS_ARAL_Msk           (0x1UL << FDCAN_ILS_ARAL_Pos)             /*!< 0x20000000 */
+#define FDCAN_ILS_ARAL               FDCAN_ILS_ARAL_Msk                        /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  ********************/
+#define FDCAN_ILE_EINT0_Pos          (0U)
+#define FDCAN_ILE_EINT0_Msk          (0x1UL << FDCAN_ILE_EINT0_Pos)            /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0              FDCAN_ILE_EINT0_Msk                       /*!<Enable Interrupt Line 0                  */
+#define FDCAN_ILE_EINT1_Pos          (1U)
+#define FDCAN_ILE_EINT1_Msk          (0x1UL << FDCAN_ILE_EINT1_Pos)            /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1              FDCAN_ILE_EINT1_Msk                       /*!<Enable Interrupt Line 1                  */
+
+/*****************  Bit definition for FDCAN_GFC register  ******************/
+#define FDCAN_GFC_RRFE_Pos           (0U)
+#define FDCAN_GFC_RRFE_Msk           (0x1UL << FDCAN_GFC_RRFE_Pos)             /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE               FDCAN_GFC_RRFE_Msk                        /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos           (1U)
+#define FDCAN_GFC_RRFS_Msk           (0x1UL << FDCAN_GFC_RRFS_Pos)             /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS               FDCAN_GFC_RRFS_Msk                        /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos           (2U)
+#define FDCAN_GFC_ANFE_Msk           (0x3UL << FDCAN_GFC_ANFE_Pos)             /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE               FDCAN_GFC_ANFE_Msk                        /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos           (4U)
+#define FDCAN_GFC_ANFS_Msk           (0x3UL << FDCAN_GFC_ANFS_Pos)             /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS               FDCAN_GFC_ANFS_Msk                        /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos        (2U)
+#define FDCAN_SIDFC_FLSSA_Msk        (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA            FDCAN_SIDFC_FLSSA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos          (16U)
+#define FDCAN_SIDFC_LSS_Msk          (0xFFUL << FDCAN_SIDFC_LSS_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS              FDCAN_SIDFC_LSS_Msk                       /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos        (2U)
+#define FDCAN_XIDFC_FLESA_Msk        (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)       /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA            FDCAN_XIDFC_FLESA_Msk                     /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos          (16U)
+#define FDCAN_XIDFC_LSE_Msk          (0x7FUL << FDCAN_XIDFC_LSE_Pos)           /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE              FDCAN_XIDFC_LSE_Msk                       /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ******************/
+#define FDCAN_XIDAM_EIDM_Pos         (0U)
+#define FDCAN_XIDAM_EIDM_Msk         (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)    /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM             FDCAN_XIDAM_EIDM_Msk                      /*!<Extended ID Mask                         */
+
+/*****************  Bit definition for FDCAN_HPMS register  *******************/
+#define FDCAN_HPMS_BIDX_Pos          (0U)
+#define FDCAN_HPMS_BIDX_Msk          (0x3FUL << FDCAN_HPMS_BIDX_Pos)           /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX              FDCAN_HPMS_BIDX_Msk                       /*!<Buffer Index                             */
+#define FDCAN_HPMS_MSI_Pos           (6U)
+#define FDCAN_HPMS_MSI_Msk           (0x3UL << FDCAN_HPMS_MSI_Pos)             /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI               FDCAN_HPMS_MSI_Msk                        /*!<Message Storage Indicator                */
+#define FDCAN_HPMS_FIDX_Pos          (8U)
+#define FDCAN_HPMS_FIDX_Msk          (0x7FUL << FDCAN_HPMS_FIDX_Pos)           /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX              FDCAN_HPMS_FIDX_Msk                       /*!<Filter Index                             */
+#define FDCAN_HPMS_FLST_Pos          (15U)
+#define FDCAN_HPMS_FLST_Msk          (0x1UL << FDCAN_HPMS_FLST_Pos)            /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST              FDCAN_HPMS_FLST_Msk                       /*!<Filter List                              */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos          (0U)
+#define FDCAN_NDAT1_ND0_Msk          (0x1UL << FDCAN_NDAT1_ND0_Pos)            /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0              FDCAN_NDAT1_ND0_Msk                       /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos          (1U)
+#define FDCAN_NDAT1_ND1_Msk          (0x1UL << FDCAN_NDAT1_ND1_Pos)            /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1              FDCAN_NDAT1_ND1_Msk                       /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos          (2U)
+#define FDCAN_NDAT1_ND2_Msk          (0x1UL << FDCAN_NDAT1_ND2_Pos)            /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2              FDCAN_NDAT1_ND2_Msk                       /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos          (3U)
+#define FDCAN_NDAT1_ND3_Msk          (0x1UL << FDCAN_NDAT1_ND3_Pos)            /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3              FDCAN_NDAT1_ND3_Msk                       /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos          (4U)
+#define FDCAN_NDAT1_ND4_Msk          (0x1UL << FDCAN_NDAT1_ND4_Pos)            /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4              FDCAN_NDAT1_ND4_Msk                       /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos          (5U)
+#define FDCAN_NDAT1_ND5_Msk          (0x1UL << FDCAN_NDAT1_ND5_Pos)            /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5              FDCAN_NDAT1_ND5_Msk                       /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos          (6U)
+#define FDCAN_NDAT1_ND6_Msk          (0x1UL << FDCAN_NDAT1_ND6_Pos)            /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6              FDCAN_NDAT1_ND6_Msk                       /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos          (7U)
+#define FDCAN_NDAT1_ND7_Msk          (0x1UL << FDCAN_NDAT1_ND7_Pos)            /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7              FDCAN_NDAT1_ND7_Msk                       /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos          (8U)
+#define FDCAN_NDAT1_ND8_Msk          (0x1UL << FDCAN_NDAT1_ND8_Pos)            /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8              FDCAN_NDAT1_ND8_Msk                       /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos              (9U)
+#define FDCAN_NDAT1_ND9_Msk          (0x1UL << FDCAN_NDAT1_ND9_Pos)            /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9              FDCAN_NDAT1_ND9_Msk                       /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos            (10U)
+#define FDCAN_NDAT1_ND10_Msk         (0x1UL << FDCAN_NDAT1_ND10_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10             FDCAN_NDAT1_ND10_Msk                      /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos         (11U)
+#define FDCAN_NDAT1_ND11_Msk         (0x1UL << FDCAN_NDAT1_ND11_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11             FDCAN_NDAT1_ND11_Msk                      /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos         (12U)
+#define FDCAN_NDAT1_ND12_Msk         (0x1UL << FDCAN_NDAT1_ND12_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12             FDCAN_NDAT1_ND12_Msk                      /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos         (13U)
+#define FDCAN_NDAT1_ND13_Msk         (0x1UL << FDCAN_NDAT1_ND13_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13             FDCAN_NDAT1_ND13_Msk                      /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos         (14U)
+#define FDCAN_NDAT1_ND14_Msk         (0x1UL << FDCAN_NDAT1_ND14_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14             FDCAN_NDAT1_ND14_Msk                      /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos         (15U)
+#define FDCAN_NDAT1_ND15_Msk         (0x1UL << FDCAN_NDAT1_ND15_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15             FDCAN_NDAT1_ND15_Msk                      /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos         (16U)
+#define FDCAN_NDAT1_ND16_Msk         (0x1UL << FDCAN_NDAT1_ND16_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16             FDCAN_NDAT1_ND16_Msk                      /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos         (17U)
+#define FDCAN_NDAT1_ND17_Msk         (0x1UL << FDCAN_NDAT1_ND17_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17             FDCAN_NDAT1_ND17_Msk                      /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos         (18U)
+#define FDCAN_NDAT1_ND18_Msk         (0x1UL << FDCAN_NDAT1_ND18_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18             FDCAN_NDAT1_ND18_Msk                      /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos         (19U)
+#define FDCAN_NDAT1_ND19_Msk         (0x1UL << FDCAN_NDAT1_ND19_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19             FDCAN_NDAT1_ND19_Msk                      /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos         (20U)
+#define FDCAN_NDAT1_ND20_Msk         (0x1UL << FDCAN_NDAT1_ND20_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20             FDCAN_NDAT1_ND20_Msk                      /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos         (21U)
+#define FDCAN_NDAT1_ND21_Msk         (0x1UL << FDCAN_NDAT1_ND21_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21             FDCAN_NDAT1_ND21_Msk                      /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos         (22U)
+#define FDCAN_NDAT1_ND22_Msk         (0x1UL << FDCAN_NDAT1_ND22_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22             FDCAN_NDAT1_ND22_Msk                      /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos         (23U)
+#define FDCAN_NDAT1_ND23_Msk         (0x1UL << FDCAN_NDAT1_ND23_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23             FDCAN_NDAT1_ND23_Msk                      /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos         (24U)
+#define FDCAN_NDAT1_ND24_Msk         (0x1UL << FDCAN_NDAT1_ND24_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24             FDCAN_NDAT1_ND24_Msk                      /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos         (25U)
+#define FDCAN_NDAT1_ND25_Msk         (0x1UL << FDCAN_NDAT1_ND25_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25             FDCAN_NDAT1_ND25_Msk                      /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos         (26U)
+#define FDCAN_NDAT1_ND26_Msk         (0x1UL << FDCAN_NDAT1_ND26_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26             FDCAN_NDAT1_ND26_Msk                      /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos         (27U)
+#define FDCAN_NDAT1_ND27_Msk         (0x1UL << FDCAN_NDAT1_ND27_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27             FDCAN_NDAT1_ND27_Msk                      /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos         (28U)
+#define FDCAN_NDAT1_ND28_Msk         (0x1UL << FDCAN_NDAT1_ND28_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28             FDCAN_NDAT1_ND28_Msk                      /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos         (29U)
+#define FDCAN_NDAT1_ND29_Msk         (0x1UL << FDCAN_NDAT1_ND29_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29             FDCAN_NDAT1_ND29_Msk                      /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos         (30U)
+#define FDCAN_NDAT1_ND30_Msk         (0x1UL << FDCAN_NDAT1_ND30_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30             FDCAN_NDAT1_ND30_Msk                      /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos         (31U)
+#define FDCAN_NDAT1_ND31_Msk         (0x1UL << FDCAN_NDAT1_ND31_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31             FDCAN_NDAT1_ND31_Msk                      /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos         (0U)
+#define FDCAN_NDAT2_ND32_Msk         (0x1UL << FDCAN_NDAT2_ND32_Pos)           /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32             FDCAN_NDAT2_ND32_Msk                      /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos         (1U)
+#define FDCAN_NDAT2_ND33_Msk         (0x1UL << FDCAN_NDAT2_ND33_Pos)           /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33             FDCAN_NDAT2_ND33_Msk                      /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos         (2U)
+#define FDCAN_NDAT2_ND34_Msk         (0x1UL << FDCAN_NDAT2_ND34_Pos)           /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34             FDCAN_NDAT2_ND34_Msk                      /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos         (3U)
+#define FDCAN_NDAT2_ND35_Msk         (0x1UL << FDCAN_NDAT2_ND35_Pos)           /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35             FDCAN_NDAT2_ND35_Msk                      /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos         (4U)
+#define FDCAN_NDAT2_ND36_Msk         (0x1UL << FDCAN_NDAT2_ND36_Pos)           /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36             FDCAN_NDAT2_ND36_Msk                      /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos         (5U)
+#define FDCAN_NDAT2_ND37_Msk         (0x1UL << FDCAN_NDAT2_ND37_Pos)           /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37             FDCAN_NDAT2_ND37_Msk                      /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos         (6U)
+#define FDCAN_NDAT2_ND38_Msk         (0x1UL << FDCAN_NDAT2_ND38_Pos)           /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38             FDCAN_NDAT2_ND38_Msk                      /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos         (7U)
+#define FDCAN_NDAT2_ND39_Msk         (0x1UL << FDCAN_NDAT2_ND39_Pos)           /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39             FDCAN_NDAT2_ND39_Msk                      /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos         (8U)
+#define FDCAN_NDAT2_ND40_Msk         (0x1UL << FDCAN_NDAT2_ND40_Pos)           /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40             FDCAN_NDAT2_ND40_Msk                      /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos         (9U)
+#define FDCAN_NDAT2_ND41_Msk         (0x1UL << FDCAN_NDAT2_ND41_Pos)           /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41             FDCAN_NDAT2_ND41_Msk                      /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos         (10U)
+#define FDCAN_NDAT2_ND42_Msk         (0x1UL << FDCAN_NDAT2_ND42_Pos)           /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42             FDCAN_NDAT2_ND42_Msk                      /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos         (11U)
+#define FDCAN_NDAT2_ND43_Msk         (0x1UL << FDCAN_NDAT2_ND43_Pos)           /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43             FDCAN_NDAT2_ND43_Msk                      /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos         (12U)
+#define FDCAN_NDAT2_ND44_Msk         (0x1UL << FDCAN_NDAT2_ND44_Pos)           /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44             FDCAN_NDAT2_ND44_Msk                      /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos         (13U)
+#define FDCAN_NDAT2_ND45_Msk         (0x1UL << FDCAN_NDAT2_ND45_Pos)           /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45             FDCAN_NDAT2_ND45_Msk                      /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos         (14U)
+#define FDCAN_NDAT2_ND46_Msk         (0x1UL << FDCAN_NDAT2_ND46_Pos)           /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46             FDCAN_NDAT2_ND46_Msk                      /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos         (15U)
+#define FDCAN_NDAT2_ND47_Msk         (0x1UL << FDCAN_NDAT2_ND47_Pos)           /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47             FDCAN_NDAT2_ND47_Msk                      /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos         (16U)
+#define FDCAN_NDAT2_ND48_Msk         (0x1UL << FDCAN_NDAT2_ND48_Pos)           /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48             FDCAN_NDAT2_ND48_Msk                      /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos         (17U)
+#define FDCAN_NDAT2_ND49_Msk         (0x1UL << FDCAN_NDAT2_ND49_Pos)           /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49             FDCAN_NDAT2_ND49_Msk                      /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos         (18U)
+#define FDCAN_NDAT2_ND50_Msk         (0x1UL << FDCAN_NDAT2_ND50_Pos)           /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50             FDCAN_NDAT2_ND50_Msk                      /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos         (19U)
+#define FDCAN_NDAT2_ND51_Msk         (0x1UL << FDCAN_NDAT2_ND51_Pos)           /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51             FDCAN_NDAT2_ND51_Msk                      /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos         (20U)
+#define FDCAN_NDAT2_ND52_Msk         (0x1UL << FDCAN_NDAT2_ND52_Pos)           /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52             FDCAN_NDAT2_ND52_Msk                      /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos         (21U)
+#define FDCAN_NDAT2_ND53_Msk         (0x1UL << FDCAN_NDAT2_ND53_Pos)           /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53             FDCAN_NDAT2_ND53_Msk                      /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos         (22U)
+#define FDCAN_NDAT2_ND54_Msk         (0x1UL << FDCAN_NDAT2_ND54_Pos)           /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54             FDCAN_NDAT2_ND54_Msk                      /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos         (23U)
+#define FDCAN_NDAT2_ND55_Msk         (0x1UL << FDCAN_NDAT2_ND55_Pos)           /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55             FDCAN_NDAT2_ND55_Msk                      /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos         (24U)
+#define FDCAN_NDAT2_ND56_Msk         (0x1UL << FDCAN_NDAT2_ND56_Pos)           /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56             FDCAN_NDAT2_ND56_Msk                      /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos         (25U)
+#define FDCAN_NDAT2_ND57_Msk         (0x1UL << FDCAN_NDAT2_ND57_Pos)           /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57             FDCAN_NDAT2_ND57_Msk                      /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos         (26U)
+#define FDCAN_NDAT2_ND58_Msk         (0x1UL << FDCAN_NDAT2_ND58_Pos)           /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58             FDCAN_NDAT2_ND58_Msk                      /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos         (27U)
+#define FDCAN_NDAT2_ND59_Msk         (0x1UL << FDCAN_NDAT2_ND59_Pos)           /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59             FDCAN_NDAT2_ND59_Msk                      /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos         (28U)
+#define FDCAN_NDAT2_ND60_Msk         (0x1UL << FDCAN_NDAT2_ND60_Pos)           /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60             FDCAN_NDAT2_ND60_Msk                      /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos         (29U)
+#define FDCAN_NDAT2_ND61_Msk         (0x1UL << FDCAN_NDAT2_ND61_Pos)           /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61             FDCAN_NDAT2_ND61_Msk                      /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos         (30U)
+#define FDCAN_NDAT2_ND62_Msk         (0x1UL << FDCAN_NDAT2_ND62_Pos)           /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62             FDCAN_NDAT2_ND62_Msk                      /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos         (31U)
+#define FDCAN_NDAT2_ND63_Msk         (0x1UL << FDCAN_NDAT2_ND63_Pos)           /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63             FDCAN_NDAT2_ND63_Msk                      /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos         (2U)
+#define FDCAN_RXF0C_F0SA_Msk         (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA             FDCAN_RXF0C_F0SA_Msk                      /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos          (16U)
+#define FDCAN_RXF0C_F0S_Msk          (0x7FUL << FDCAN_RXF0C_F0S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S              FDCAN_RXF0C_F0S_Msk                       /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos         (24U)
+#define FDCAN_RXF0C_F0WM_Msk         (0x7FUL << FDCAN_RXF0C_F0WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM             FDCAN_RXF0C_F0WM_Msk                      /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos         (31U)
+#define FDCAN_RXF0C_F0OM_Msk         (0x1UL << FDCAN_RXF0C_F0OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM             FDCAN_RXF0C_F0OM_Msk                      /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ******************/
+#define FDCAN_RXF0S_F0FL_Pos         (0U)
+#define FDCAN_RXF0S_F0FL_Msk         (0x7FUL << FDCAN_RXF0S_F0FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL             FDCAN_RXF0S_F0FL_Msk                      /*!<Rx FIFO 0 Fill Level                     */
+#define FDCAN_RXF0S_F0GI_Pos         (8U)
+#define FDCAN_RXF0S_F0GI_Msk         (0x3FUL << FDCAN_RXF0S_F0GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI             FDCAN_RXF0S_F0GI_Msk                      /*!<Rx FIFO 0 Get Index                      */
+#define FDCAN_RXF0S_F0PI_Pos         (16U)
+#define FDCAN_RXF0S_F0PI_Msk         (0x3FUL << FDCAN_RXF0S_F0PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI             FDCAN_RXF0S_F0PI_Msk                      /*!<Rx FIFO 0 Put Index                      */
+#define FDCAN_RXF0S_F0F_Pos          (24U)
+#define FDCAN_RXF0S_F0F_Msk          (0x1UL << FDCAN_RXF0S_F0F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F              FDCAN_RXF0S_F0F_Msk                       /*!<Rx FIFO 0 Full                           */
+#define FDCAN_RXF0S_RF0L_Pos         (25U)
+#define FDCAN_RXF0S_RF0L_Msk         (0x1UL << FDCAN_RXF0S_RF0L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L             FDCAN_RXF0S_RF0L_Msk                      /*!<Rx FIFO 0 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ******************/
+#define FDCAN_RXF0A_F0AI_Pos         (0U)
+#define FDCAN_RXF0A_F0AI_Msk         (0x3FUL << FDCAN_RXF0A_F0AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI             FDCAN_RXF0A_F0AI_Msk                      /*!<Rx FIFO 0 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos          (2U)
+#define FDCAN_RXBC_RBSA_Msk          (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA              FDCAN_RXBC_RBSA_Msk                       /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ******************/
+#define FDCAN_RXF1C_F1SA_Pos         (2U)
+#define FDCAN_RXF1C_F1SA_Msk         (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA             FDCAN_RXF1C_F1SA_Msk                      /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos          (16U)
+#define FDCAN_RXF1C_F1S_Msk          (0x7FUL << FDCAN_RXF1C_F1S_Pos)           /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S              FDCAN_RXF1C_F1S_Msk                       /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos         (24U)
+#define FDCAN_RXF1C_F1WM_Msk         (0x7FUL << FDCAN_RXF1C_F1WM_Pos)          /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM             FDCAN_RXF1C_F1WM_Msk                      /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos         (31U)
+#define FDCAN_RXF1C_F1OM_Msk         (0x1UL << FDCAN_RXF1C_F1OM_Pos)           /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM             FDCAN_RXF1C_F1OM_Msk                      /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ******************/
+#define FDCAN_RXF1S_F1FL_Pos         (0U)
+#define FDCAN_RXF1S_F1FL_Msk         (0x7FUL << FDCAN_RXF1S_F1FL_Pos)          /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL             FDCAN_RXF1S_F1FL_Msk                      /*!<Rx FIFO 1 Fill Level                     */
+#define FDCAN_RXF1S_F1GI_Pos         (8U)
+#define FDCAN_RXF1S_F1GI_Msk         (0x3FUL << FDCAN_RXF1S_F1GI_Pos)          /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI             FDCAN_RXF1S_F1GI_Msk                      /*!<Rx FIFO 1 Get Index                      */
+#define FDCAN_RXF1S_F1PI_Pos         (16U)
+#define FDCAN_RXF1S_F1PI_Msk         (0x3FUL << FDCAN_RXF1S_F1PI_Pos)          /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI             FDCAN_RXF1S_F1PI_Msk                      /*!<Rx FIFO 1 Put Index                      */
+#define FDCAN_RXF1S_F1F_Pos          (24U)
+#define FDCAN_RXF1S_F1F_Msk          (0x1UL << FDCAN_RXF1S_F1F_Pos)            /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F              FDCAN_RXF1S_F1F_Msk                       /*!<Rx FIFO 1 Full                           */
+#define FDCAN_RXF1S_RF1L_Pos         (25U)
+#define FDCAN_RXF1S_RF1L_Msk         (0x1UL << FDCAN_RXF1S_RF1L_Pos)           /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L             FDCAN_RXF1S_RF1L_Msk                      /*!<Rx FIFO 1 Message Lost                   */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ******************/
+#define FDCAN_RXF1A_F1AI_Pos         (0U)
+#define FDCAN_RXF1A_F1AI_Msk         (0x3FUL << FDCAN_RXF1A_F1AI_Pos)          /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI             FDCAN_RXF1A_F1AI_Msk                      /*!<Rx FIFO 1 Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_RXESC register  ******************/
+#define FDCAN_RXESC_F0DS_Pos         (0U)
+#define FDCAN_RXESC_F0DS_Msk         (0x7UL << FDCAN_RXESC_F0DS_Pos)           /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS             FDCAN_RXESC_F0DS_Msk                      /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos         (4U)
+#define FDCAN_RXESC_F1DS_Msk         (0x7UL << FDCAN_RXESC_F1DS_Pos)           /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS             FDCAN_RXESC_F1DS_Msk                      /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos         (8U)
+#define FDCAN_RXESC_RBDS_Msk         (0x7UL << FDCAN_RXESC_RBDS_Pos)           /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS             FDCAN_RXESC_RBDS_Msk                      /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *******************/
+#define FDCAN_TXBC_TBSA_Pos          (2U)
+#define FDCAN_TXBC_TBSA_Msk          (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)         /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA              FDCAN_TXBC_TBSA_Msk                       /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos          (16U)
+#define FDCAN_TXBC_NDTB_Msk          (0x3FUL << FDCAN_TXBC_NDTB_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB              FDCAN_TXBC_NDTB_Msk                       /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos          (24U)
+#define FDCAN_TXBC_TFQS_Msk          (0x3FUL << FDCAN_TXBC_TFQS_Pos)           /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS              FDCAN_TXBC_TFQS_Msk                       /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos          (30U)
+#define FDCAN_TXBC_TFQM_Msk          (0x1UL << FDCAN_TXBC_TFQM_Pos)            /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM              FDCAN_TXBC_TFQM_Msk                       /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  ******************/
+#define FDCAN_TXFQS_TFFL_Pos         (0U)
+#define FDCAN_TXFQS_TFFL_Msk         (0x3FUL << FDCAN_TXFQS_TFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL             FDCAN_TXFQS_TFFL_Msk                      /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos         (8U)
+#define FDCAN_TXFQS_TFGI_Msk         (0x1FUL << FDCAN_TXFQS_TFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI             FDCAN_TXFQS_TFGI_Msk                      /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos        (16U)
+#define FDCAN_TXFQS_TFQPI_Msk        (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)         /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI            FDCAN_TXFQS_TFQPI_Msk                     /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos         (21U)
+#define FDCAN_TXFQS_TFQF_Msk         (0x1UL << FDCAN_TXFQS_TFQF_Pos)           /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF             FDCAN_TXFQS_TFQF_Msk                      /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  ******************/
+#define FDCAN_TXESC_TBDS_Pos         (0U)
+#define FDCAN_TXESC_TBDS_Msk         (0x7UL << FDCAN_TXESC_TBDS_Pos)           /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS             FDCAN_TXESC_TBDS_Msk                      /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  ******************/
+#define FDCAN_TXBRP_TRP_Pos          (0U)
+#define FDCAN_TXBRP_TRP_Msk          (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)     /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP              FDCAN_TXBRP_TRP_Msk                       /*!<Transmission Request Pending             */
+
+/*****************  Bit definition for FDCAN_TXBAR register  ******************/
+#define FDCAN_TXBAR_AR_Pos           (0U)
+#define FDCAN_TXBAR_AR_Msk           (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR               FDCAN_TXBAR_AR_Msk                        /*!<Add Request                              */
+
+/*****************  Bit definition for FDCAN_TXBCR register  ******************/
+#define FDCAN_TXBCR_CR_Pos           (0U)
+#define FDCAN_TXBCR_CR_Msk           (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR               FDCAN_TXBCR_CR_Msk                        /*!<Cancellation Request                     */
+
+/*****************  Bit definition for FDCAN_TXBTO register  ******************/
+#define FDCAN_TXBTO_TO_Pos           (0U)
+#define FDCAN_TXBTO_TO_Msk           (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO               FDCAN_TXBTO_TO_Msk                        /*!<Transmission Occurred                    */
+
+/*****************  Bit definition for FDCAN_TXBCF register  ******************/
+#define FDCAN_TXBCF_CF_Pos           (0U)
+#define FDCAN_TXBCF_CF_Msk           (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF               FDCAN_TXBCF_CF_Msk                        /*!<Cancellation Finished                    */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  *****************/
+#define FDCAN_TXBTIE_TIE_Pos         (0U)
+#define FDCAN_TXBTIE_TIE_Msk         (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)    /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE             FDCAN_TXBTIE_TIE_Msk                      /*!<Transmission Interrupt Enable            */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  ****************/
+#define FDCAN_TXBCIE_CFIE_Pos        (0U)
+#define FDCAN_TXBCIE_CFIE_Msk        (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)   /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE            FDCAN_TXBCIE_CFIE_Msk                     /*!<Cancellation Finished Interrupt Enable   */
+
+/*****************  Bit definition for FDCAN_TXEFC register  ******************/
+#define FDCAN_TXEFC_EFSA_Pos         (2U)
+#define FDCAN_TXEFC_EFSA_Msk         (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA             FDCAN_TXEFC_EFSA_Msk                      /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos          (16U)
+#define FDCAN_TXEFC_EFS_Msk          (0x3FUL << FDCAN_TXEFC_EFS_Pos)           /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS              FDCAN_TXEFC_EFS_Msk                       /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos         (24U)
+#define FDCAN_TXEFC_EFWM_Msk         (0x3FUL << FDCAN_TXEFC_EFWM_Pos)          /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM             FDCAN_TXEFC_EFWM_Msk                      /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  ******************/
+#define FDCAN_TXEFS_EFFL_Pos         (0U)
+#define FDCAN_TXEFS_EFFL_Msk         (0x3FUL << FDCAN_TXEFS_EFFL_Pos)          /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL             FDCAN_TXEFS_EFFL_Msk                      /*!<Event FIFO Fill Level                    */
+#define FDCAN_TXEFS_EFGI_Pos         (8U)
+#define FDCAN_TXEFS_EFGI_Msk         (0x1FUL << FDCAN_TXEFS_EFGI_Pos)          /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI             FDCAN_TXEFS_EFGI_Msk                      /*!<Event FIFO Get Index                     */
+#define FDCAN_TXEFS_EFPI_Pos         (16U)
+#define FDCAN_TXEFS_EFPI_Msk         (0x1FUL << FDCAN_TXEFS_EFPI_Pos)          /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI             FDCAN_TXEFS_EFPI_Msk                      /*!<Event FIFO Put Index                     */
+#define FDCAN_TXEFS_EFF_Pos          (24U)
+#define FDCAN_TXEFS_EFF_Msk          (0x1UL << FDCAN_TXEFS_EFF_Pos)            /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF              FDCAN_TXEFS_EFF_Msk                       /*!<Event FIFO Full                          */
+#define FDCAN_TXEFS_TEFL_Pos         (25U)
+#define FDCAN_TXEFS_TEFL_Msk         (0x1UL << FDCAN_TXEFS_TEFL_Pos)           /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL             FDCAN_TXEFS_TEFL_Msk                      /*!<Tx Event FIFO Element Lost               */
+
+/*****************  Bit definition for FDCAN_TXEFA register  ******************/
+#define FDCAN_TXEFA_EFAI_Pos         (0U)
+#define FDCAN_TXEFA_EFAI_Msk         (0x1FUL << FDCAN_TXEFA_EFAI_Pos)          /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI             FDCAN_TXEFA_EFAI_Msk                      /*!<Event FIFO Acknowledge Index             */
+
+/*****************  Bit definition for FDCAN_TTTMC register  ******************/
+#define FDCAN_TTTMC_TMSA_Pos         (2U)
+#define FDCAN_TTTMC_TMSA_Msk         (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)        /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA             FDCAN_TTTMC_TMSA_Msk                      /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos          (16U)
+#define FDCAN_TTTMC_TME_Msk          (0x7FUL << FDCAN_TTTMC_TME_Pos)           /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME              FDCAN_TTTMC_TME_Msk                       /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  ******************/
+#define FDCAN_TTRMC_RID_Pos          (0U)
+#define FDCAN_TTRMC_RID_Msk          (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)     /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID              FDCAN_TTRMC_RID_Msk                       /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos          (30U)
+#define FDCAN_TTRMC_XTD_Msk          (0x1UL << FDCAN_TTRMC_XTD_Pos)            /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD              FDCAN_TTRMC_XTD_Msk                       /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos         (31U)
+#define FDCAN_TTRMC_RMPS_Msk         (0x1UL << FDCAN_TTRMC_RMPS_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS             FDCAN_TTRMC_RMPS_Msk                      /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  ******************/
+#define FDCAN_TTOCF_OM_Pos           (0U)
+#define FDCAN_TTOCF_OM_Msk           (0x3UL << FDCAN_TTOCF_OM_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM               FDCAN_TTOCF_OM_Msk                        /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos          (3U)
+#define FDCAN_TTOCF_GEN_Msk          (0x1UL << FDCAN_TTOCF_GEN_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN              FDCAN_TTOCF_GEN_Msk                       /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos           (4U)
+#define FDCAN_TTOCF_TM_Msk           (0x1UL << FDCAN_TTOCF_TM_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM               FDCAN_TTOCF_TM_Msk                        /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos        (5U)
+#define FDCAN_TTOCF_LDSDL_Msk        (0x7UL << FDCAN_TTOCF_LDSDL_Pos)          /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL            FDCAN_TTOCF_LDSDL_Msk                     /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos         (8U)
+#define FDCAN_TTOCF_IRTO_Msk         (0x7FUL << FDCAN_TTOCF_IRTO_Pos)          /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO             FDCAN_TTOCF_IRTO_Msk                      /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos         (15U)
+#define FDCAN_TTOCF_EECS_Msk         (0x1UL << FDCAN_TTOCF_EECS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS             FDCAN_TTOCF_EECS_Msk                      /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos          (16U)
+#define FDCAN_TTOCF_AWL_Msk          (0xFFUL << FDCAN_TTOCF_AWL_Pos)           /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL              FDCAN_TTOCF_AWL_Msk                       /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos         (24U)
+#define FDCAN_TTOCF_EGTF_Msk         (0x1UL << FDCAN_TTOCF_EGTF_Pos)           /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF             FDCAN_TTOCF_EGTF_Msk                      /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos          (25U)
+#define FDCAN_TTOCF_ECC_Msk          (0x1UL << FDCAN_TTOCF_ECC_Pos)            /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC              FDCAN_TTOCF_ECC_Msk                       /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos         (26U)
+#define FDCAN_TTOCF_EVTP_Msk         (0x1UL << FDCAN_TTOCF_EVTP_Pos)           /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP             FDCAN_TTOCF_EVTP_Msk                      /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  ******************/
+#define FDCAN_TTMLM_CCM_Pos          (0U)
+#define FDCAN_TTMLM_CCM_Msk          (0x3FUL << FDCAN_TTMLM_CCM_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM              FDCAN_TTMLM_CCM_Msk                       /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos          (6U)
+#define FDCAN_TTMLM_CSS_Msk          (0x3UL << FDCAN_TTMLM_CSS_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS              FDCAN_TTMLM_CSS_Msk                       /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos         (8U)
+#define FDCAN_TTMLM_TXEW_Msk         (0xFUL << FDCAN_TTMLM_TXEW_Pos)           /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW             FDCAN_TTMLM_TXEW_Msk                      /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos         (16U)
+#define FDCAN_TTMLM_ENTT_Msk         (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)         /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT             FDCAN_TTMLM_ENTT_Msk                      /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  ******************/
+#define FDCAN_TURCF_NCL_Pos          (0U)
+#define FDCAN_TURCF_NCL_Msk          (0xFFFFUL << FDCAN_TURCF_NCL_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL              FDCAN_TURCF_NCL_Msk                       /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos           (16U)
+#define FDCAN_TURCF_DC_Msk           (0x3FFFUL << FDCAN_TURCF_DC_Pos)          /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC               FDCAN_TURCF_DC_Msk                        /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos          (31U)
+#define FDCAN_TURCF_ELT_Msk          (0x1UL << FDCAN_TURCF_ELT_Pos)            /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT              FDCAN_TURCF_ELT_Msk                       /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ******************/
+#define FDCAN_TTOCN_SGT_Pos          (0U)
+#define FDCAN_TTOCN_SGT_Msk          (0x1UL << FDCAN_TTOCN_SGT_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT              FDCAN_TTOCN_SGT_Msk                       /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos          (1U)
+#define FDCAN_TTOCN_ECS_Msk          (0x1UL << FDCAN_TTOCN_ECS_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS              FDCAN_TTOCN_ECS_Msk                       /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos          (2U)
+#define FDCAN_TTOCN_SWP_Msk          (0x1UL << FDCAN_TTOCN_SWP_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP              FDCAN_TTOCN_SWP_Msk                       /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos          (3U)
+#define FDCAN_TTOCN_SWS_Msk          (0x3UL << FDCAN_TTOCN_SWS_Pos)            /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS              FDCAN_TTOCN_SWS_Msk                       /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos         (5U)
+#define FDCAN_TTOCN_RTIE_Msk         (0x1UL << FDCAN_TTOCN_RTIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE             FDCAN_TTOCN_RTIE_Msk                      /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos          (6U)
+#define FDCAN_TTOCN_TMC_Msk          (0x3UL << FDCAN_TTOCN_TMC_Pos)            /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC              FDCAN_TTOCN_TMC_Msk                       /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos         (8U)
+#define FDCAN_TTOCN_TTIE_Msk         (0x1UL << FDCAN_TTOCN_TTIE_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE             FDCAN_TTOCN_TTIE_Msk                      /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos          (9U)
+#define FDCAN_TTOCN_GCS_Msk          (0x1UL << FDCAN_TTOCN_GCS_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS              FDCAN_TTOCN_GCS_Msk                       /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos          (10U)
+#define FDCAN_TTOCN_FGP_Msk          (0x1UL << FDCAN_TTOCN_FGP_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP              FDCAN_TTOCN_FGP_Msk                       /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos          (11U)
+#define FDCAN_TTOCN_TMG_Msk          (0x1UL << FDCAN_TTOCN_TMG_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG              FDCAN_TTOCN_TMG_Msk                       /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos          (12U)
+#define FDCAN_TTOCN_NIG_Msk          (0x1UL << FDCAN_TTOCN_NIG_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG              FDCAN_TTOCN_NIG_Msk                       /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos         (13U)
+#define FDCAN_TTOCN_ESCN_Msk         (0x1UL << FDCAN_TTOCN_ESCN_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN             FDCAN_TTOCN_ESCN_Msk                      /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos         (15U)
+#define FDCAN_TTOCN_LCKC_Msk         (0x1UL << FDCAN_TTOCN_LCKC_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC             FDCAN_TTOCN_LCKC_Msk                      /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ******************/
+#define FDCAN_TTGTP_TP_Pos           (0U)
+#define FDCAN_TTGTP_TP_Msk           (0xFFFFUL << FDCAN_TTGTP_TP_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP               FDCAN_TTGTP_TP_Msk                        /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos          (16U)
+#define FDCAN_TTGTP_CTP_Msk          (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP              FDCAN_TTGTP_CTP_Msk                       /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ******************/
+#define FDCAN_TTTMK_TM_Pos           (0U)
+#define FDCAN_TTTMK_TM_Msk           (0xFFFFUL << FDCAN_TTTMK_TM_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM               FDCAN_TTTMK_TM_Msk                        /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos         (16U)
+#define FDCAN_TTTMK_TICC_Msk         (0x7FUL << FDCAN_TTTMK_TICC_Pos)          /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC             FDCAN_TTTMK_TICC_Msk                      /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos         (31U)
+#define FDCAN_TTTMK_LCKM_Msk         (0x1UL << FDCAN_TTTMK_LCKM_Pos)           /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM             FDCAN_TTTMK_LCKM_Msk                      /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  *******************/
+#define FDCAN_TTIR_SBC_Pos           (0U)
+#define FDCAN_TTIR_SBC_Msk           (0x1UL << FDCAN_TTIR_SBC_Pos)             /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC               FDCAN_TTIR_SBC_Msk                        /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos           (1U)
+#define FDCAN_TTIR_SMC_Msk           (0x1UL << FDCAN_TTIR_SMC_Pos)             /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC               FDCAN_TTIR_SMC_Msk                        /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos           (2U)
+#define FDCAN_TTIR_CSM_Msk           (0x1UL << FDCAN_TTIR_CSM_Pos)             /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM               FDCAN_TTIR_CSM_Msk                        /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos           (3U)
+#define FDCAN_TTIR_SOG_Msk           (0x1UL << FDCAN_TTIR_SOG_Pos)             /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG               FDCAN_TTIR_SOG_Msk                        /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos          (4U)
+#define FDCAN_TTIR_RTMI_Msk          (0x1UL << FDCAN_TTIR_RTMI_Pos)            /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI              FDCAN_TTIR_RTMI_Msk                       /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos          (5U)
+#define FDCAN_TTIR_TTMI_Msk          (0x1UL << FDCAN_TTIR_TTMI_Pos)            /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI              FDCAN_TTIR_TTMI_Msk                       /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos           (6U)
+#define FDCAN_TTIR_SWE_Msk           (0x1UL << FDCAN_TTIR_SWE_Pos)             /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE               FDCAN_TTIR_SWE_Msk                        /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos           (7U)
+#define FDCAN_TTIR_GTW_Msk           (0x1UL << FDCAN_TTIR_GTW_Pos)             /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW               FDCAN_TTIR_GTW_Msk                        /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos           (8U)
+#define FDCAN_TTIR_GTD_Msk           (0x1UL << FDCAN_TTIR_GTD_Pos)             /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD               FDCAN_TTIR_GTD_Msk                        /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos           (9U)
+#define FDCAN_TTIR_GTE_Msk           (0x1UL << FDCAN_TTIR_GTE_Pos)             /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE               FDCAN_TTIR_GTE_Msk                        /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos           (10U)
+#define FDCAN_TTIR_TXU_Msk           (0x1UL << FDCAN_TTIR_TXU_Pos)             /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU               FDCAN_TTIR_TXU_Msk                        /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos           (11U)
+#define FDCAN_TTIR_TXO_Msk           (0x1UL << FDCAN_TTIR_TXO_Pos)             /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO               FDCAN_TTIR_TXO_Msk                        /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos           (12U)
+#define FDCAN_TTIR_SE1_Msk           (0x1UL << FDCAN_TTIR_SE1_Pos)             /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1               FDCAN_TTIR_SE1_Msk                        /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos           (13U)
+#define FDCAN_TTIR_SE2_Msk           (0x1UL << FDCAN_TTIR_SE2_Pos)             /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2               FDCAN_TTIR_SE2_Msk                        /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos           (14U)
+#define FDCAN_TTIR_ELC_Msk           (0x1UL << FDCAN_TTIR_ELC_Pos)             /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC               FDCAN_TTIR_ELC_Msk                        /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos           (15U)
+#define FDCAN_TTIR_IWT_Msk           (0x1UL << FDCAN_TTIR_IWT_Pos)             /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT               FDCAN_TTIR_IWT_Msk                        /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos            (16U)
+#define FDCAN_TTIR_WT_Msk            (0x1UL << FDCAN_TTIR_WT_Pos)              /*!< 0x00010000 */
+#define FDCAN_TTIR_WT                FDCAN_TTIR_WT_Msk                         /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos            (17U)
+#define FDCAN_TTIR_AW_Msk            (0x1UL << FDCAN_TTIR_AW_Pos)              /*!< 0x00020000 */
+#define FDCAN_TTIR_AW                FDCAN_TTIR_AW_Msk                         /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos           (18U)
+#define FDCAN_TTIR_CER_Msk           (0x1UL << FDCAN_TTIR_CER_Pos)             /*!< 0x00040000 */
+#define FDCAN_TTIR_CER               FDCAN_TTIR_CER_Msk                        /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  *******************/
+#define FDCAN_TTIE_SBCE_Pos          (0U)
+#define FDCAN_TTIE_SBCE_Msk          (0x1UL << FDCAN_TTIE_SBCE_Pos)            /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE              FDCAN_TTIE_SBCE_Msk                       /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos          (1U)
+#define FDCAN_TTIE_SMCE_Msk          (0x1UL << FDCAN_TTIE_SMCE_Pos)            /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE              FDCAN_TTIE_SMCE_Msk                       /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos          (2U)
+#define FDCAN_TTIE_CSME_Msk          (0x1UL << FDCAN_TTIE_CSME_Pos)            /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME              FDCAN_TTIE_CSME_Msk                       /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos          (3U)
+#define FDCAN_TTIE_SOGE_Msk          (0x1UL << FDCAN_TTIE_SOGE_Pos)            /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE              FDCAN_TTIE_SOGE_Msk                       /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos         (4U)
+#define FDCAN_TTIE_RTMIE_Msk         (0x1UL << FDCAN_TTIE_RTMIE_Pos)           /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE             FDCAN_TTIE_RTMIE_Msk                      /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos         (5U)
+#define FDCAN_TTIE_TTMIE_Msk         (0x1UL << FDCAN_TTIE_TTMIE_Pos)           /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE             FDCAN_TTIE_TTMIE_Msk                      /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos          (6U)
+#define FDCAN_TTIE_SWEE_Msk          (0x1UL << FDCAN_TTIE_SWEE_Pos)            /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE              FDCAN_TTIE_SWEE_Msk                       /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos          (7U)
+#define FDCAN_TTIE_GTWE_Msk          (0x1UL << FDCAN_TTIE_GTWE_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE              FDCAN_TTIE_GTWE_Msk                       /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos          (8U)
+#define FDCAN_TTIE_GTDE_Msk          (0x1UL << FDCAN_TTIE_GTDE_Pos)            /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE              FDCAN_TTIE_GTDE_Msk                       /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos          (9U)
+#define FDCAN_TTIE_GTEE_Msk          (0x1UL << FDCAN_TTIE_GTEE_Pos)            /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE              FDCAN_TTIE_GTEE_Msk                       /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos          (10U)
+#define FDCAN_TTIE_TXUE_Msk          (0x1UL << FDCAN_TTIE_TXUE_Pos)            /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE              FDCAN_TTIE_TXUE_Msk                       /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos          (11U)
+#define FDCAN_TTIE_TXOE_Msk          (0x1UL << FDCAN_TTIE_TXOE_Pos)            /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE              FDCAN_TTIE_TXOE_Msk                       /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos          (12U)
+#define FDCAN_TTIE_SE1E_Msk          (0x1UL << FDCAN_TTIE_SE1E_Pos)            /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E              FDCAN_TTIE_SE1E_Msk                       /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos          (13U)
+#define FDCAN_TTIE_SE2E_Msk          (0x1UL << FDCAN_TTIE_SE2E_Pos)            /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E              FDCAN_TTIE_SE2E_Msk                       /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos          (14U)
+#define FDCAN_TTIE_ELCE_Msk          (0x1UL << FDCAN_TTIE_ELCE_Pos)            /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE              FDCAN_TTIE_ELCE_Msk                       /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos          (15U)
+#define FDCAN_TTIE_IWTE_Msk          (0x1UL << FDCAN_TTIE_IWTE_Pos)            /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE              FDCAN_TTIE_IWTE_Msk                       /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos           (16U)
+#define FDCAN_TTIE_WTE_Msk           (0x1UL << FDCAN_TTIE_WTE_Pos)             /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE               FDCAN_TTIE_WTE_Msk                        /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos           (17U)
+#define FDCAN_TTIE_AWE_Msk           (0x1UL << FDCAN_TTIE_AWE_Pos)             /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE               FDCAN_TTIE_AWE_Msk                        /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos          (18U)
+#define FDCAN_TTIE_CERE_Msk          (0x1UL << FDCAN_TTIE_CERE_Pos)            /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE              FDCAN_TTIE_CERE_Msk                       /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ******************/
+#define FDCAN_TTILS_SBCS_Pos         (0U)
+#define FDCAN_TTILS_SBCS_Msk         (0x1UL << FDCAN_TTILS_SBCS_Pos)           /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS             FDCAN_TTILS_SBCS_Msk                      /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos         (1U)
+#define FDCAN_TTILS_SMCS_Msk         (0x1UL << FDCAN_TTILS_SMCS_Pos)           /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS             FDCAN_TTILS_SMCS_Msk                      /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos         (2U)
+#define FDCAN_TTILS_CSMS_Msk         (0x1UL << FDCAN_TTILS_CSMS_Pos)           /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS             FDCAN_TTILS_CSMS_Msk                      /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos         (3U)
+#define FDCAN_TTILS_SOGS_Msk         (0x1UL << FDCAN_TTILS_SOGS_Pos)           /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS             FDCAN_TTILS_SOGS_Msk                      /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos        (4U)
+#define FDCAN_TTILS_RTMIS_Msk        (0x1UL << FDCAN_TTILS_RTMIS_Pos)          /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS            FDCAN_TTILS_RTMIS_Msk                     /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos        (5U)
+#define FDCAN_TTILS_TTMIS_Msk        (0x1UL << FDCAN_TTILS_TTMIS_Pos)          /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS            FDCAN_TTILS_TTMIS_Msk                     /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos         (6U)
+#define FDCAN_TTILS_SWES_Msk         (0x1UL << FDCAN_TTILS_SWES_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES             FDCAN_TTILS_SWES_Msk                      /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos         (7U)
+#define FDCAN_TTILS_GTWS_Msk         (0x1UL << FDCAN_TTILS_GTWS_Pos)           /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS             FDCAN_TTILS_GTWS_Msk                      /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos         (8U)
+#define FDCAN_TTILS_GTDS_Msk         (0x1UL << FDCAN_TTILS_GTDS_Pos)           /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS             FDCAN_TTILS_GTDS_Msk                      /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos         (9U)
+#define FDCAN_TTILS_GTES_Msk         (0x1UL << FDCAN_TTILS_GTES_Pos)           /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES             FDCAN_TTILS_GTES_Msk                      /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos         (10U)
+#define FDCAN_TTILS_TXUS_Msk         (0x1UL << FDCAN_TTILS_TXUS_Pos)           /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS             FDCAN_TTILS_TXUS_Msk                      /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos         (11U)
+#define FDCAN_TTILS_TXOS_Msk         (0x1UL << FDCAN_TTILS_TXOS_Pos)           /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS             FDCAN_TTILS_TXOS_Msk                      /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos         (12U)
+#define FDCAN_TTILS_SE1S_Msk         (0x1UL << FDCAN_TTILS_SE1S_Pos)           /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S             FDCAN_TTILS_SE1S_Msk                      /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos         (13U)
+#define FDCAN_TTILS_SE2S_Msk         (0x1UL << FDCAN_TTILS_SE2S_Pos)           /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S             FDCAN_TTILS_SE2S_Msk                      /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos         (14U)
+#define FDCAN_TTILS_ELCS_Msk         (0x1UL << FDCAN_TTILS_ELCS_Pos)           /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS             FDCAN_TTILS_ELCS_Msk                      /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos         (15U)
+#define FDCAN_TTILS_IWTS_Msk         (0x1UL << FDCAN_TTILS_IWTS_Pos)           /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS             FDCAN_TTILS_IWTS_Msk                      /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos          (16U)
+#define FDCAN_TTILS_WTS_Msk          (0x1UL << FDCAN_TTILS_WTS_Pos)            /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS              FDCAN_TTILS_WTS_Msk                       /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos          (17U)
+#define FDCAN_TTILS_AWS_Msk          (0x1UL << FDCAN_TTILS_AWS_Pos)            /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS              FDCAN_TTILS_AWS_Msk                       /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos         (18U)
+#define FDCAN_TTILS_CERS_Msk         (0x1UL << FDCAN_TTILS_CERS_Pos)           /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS             FDCAN_TTILS_CERS_Msk                      /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ******************/
+#define FDCAN_TTOST_EL_Pos           (0U)
+#define FDCAN_TTOST_EL_Msk           (0x3UL << FDCAN_TTOST_EL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTOST_EL               FDCAN_TTOST_EL_Msk                        /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos           (2U)
+#define FDCAN_TTOST_MS_Msk           (0x3UL << FDCAN_TTOST_MS_Pos)             /*!< 0x0000000C */
+#define FDCAN_TTOST_MS               FDCAN_TTOST_MS_Msk                        /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos          (4U)
+#define FDCAN_TTOST_SYS_Msk          (0x3UL << FDCAN_TTOST_SYS_Pos)            /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS              FDCAN_TTOST_SYS_Msk                       /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos         (6U)
+#define FDCAN_TTOST_QGTP_Msk         (0x1UL << FDCAN_TTOST_QGTP_Pos)           /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP             FDCAN_TTOST_QGTP_Msk                      /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos          (7U)
+#define FDCAN_TTOST_QCS_Msk          (0x1UL << FDCAN_TTOST_QCS_Pos)            /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS              FDCAN_TTOST_QCS_Msk                       /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos          (8U)
+#define FDCAN_TTOST_RTO_Msk          (0xFFUL << FDCAN_TTOST_RTO_Pos)           /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO              FDCAN_TTOST_RTO_Msk                       /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos         (22U)
+#define FDCAN_TTOST_WGTD_Msk         (0x1UL << FDCAN_TTOST_WGTD_Pos)           /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD             FDCAN_TTOST_WGTD_Msk                      /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos          (23U)
+#define FDCAN_TTOST_GFI_Msk          (0x1UL << FDCAN_TTOST_GFI_Pos)            /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI              FDCAN_TTOST_GFI_Msk                       /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos          (24U)
+#define FDCAN_TTOST_TMP_Msk          (0x7UL << FDCAN_TTOST_TMP_Pos)            /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP              FDCAN_TTOST_TMP_Msk                       /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos          (27U)
+#define FDCAN_TTOST_GSI_Msk          (0x1UL << FDCAN_TTOST_GSI_Pos)            /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI              FDCAN_TTOST_GSI_Msk                       /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos          (28U)
+#define FDCAN_TTOST_WFE_Msk          (0x1UL << FDCAN_TTOST_WFE_Pos)            /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE              FDCAN_TTOST_WFE_Msk                       /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos          (29U)
+#define FDCAN_TTOST_AWE_Msk          (0x1UL << FDCAN_TTOST_AWE_Pos)            /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE              FDCAN_TTOST_AWE_Msk                       /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos         (30U)
+#define FDCAN_TTOST_WECS_Msk         (0x1UL << FDCAN_TTOST_WECS_Pos)           /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS             FDCAN_TTOST_WECS_Msk                      /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos          (31U)
+#define FDCAN_TTOST_SPL_Msk          (0x1UL << FDCAN_TTOST_SPL_Pos)            /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL              FDCAN_TTOST_SPL_Msk                       /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ******************/
+#define FDCAN_TURNA_NAV_Pos          (0U)
+#define FDCAN_TURNA_NAV_Msk          (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)        /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV              FDCAN_TURNA_NAV_Msk                       /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ******************/
+#define FDCAN_TTLGT_LT_Pos           (0U)
+#define FDCAN_TTLGT_LT_Msk           (0xFFFFUL << FDCAN_TTLGT_LT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT               FDCAN_TTLGT_LT_Msk                        /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos           (16U)
+#define FDCAN_TTLGT_GT_Msk           (0xFFFFUL << FDCAN_TTLGT_GT_Pos)          /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT               FDCAN_TTLGT_GT_Msk                        /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ******************/
+#define FDCAN_TTCTC_CT_Pos           (0U)
+#define FDCAN_TTCTC_CT_Msk           (0xFFFFUL << FDCAN_TTCTC_CT_Pos)          /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT               FDCAN_TTCTC_CT_Msk                        /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos           (16U)
+#define FDCAN_TTCTC_CC_Msk           (0x3FUL << FDCAN_TTCTC_CC_Pos)            /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC               FDCAN_TTCTC_CC_Msk                        /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ******************/
+#define FDCAN_TTCPT_CCV_Pos          (0U)
+#define FDCAN_TTCPT_CCV_Msk          (0x3FUL << FDCAN_TTCPT_CCV_Pos)           /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV              FDCAN_TTCPT_CCV_Msk                       /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos          (16U)
+#define FDCAN_TTCPT_SWV_Msk          (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)         /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV              FDCAN_TTCPT_SWV_Msk                       /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ******************/
+#define FDCAN_TTCSM_CSM_Pos          (0U)
+#define FDCAN_TTCSM_CSM_Msk          (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)         /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM              FDCAN_TTCSM_CSM_Msk                       /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *******************/
+#define FDCAN_TTTS_SWTSEL_Pos        (0U)
+#define FDCAN_TTTS_SWTSEL_Msk        (0x3UL << FDCAN_TTTS_SWTSEL_Pos)          /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL            FDCAN_TTTS_SWTSEL_Msk                     /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos        (4U)
+#define FDCAN_TTTS_EVTSEL_Msk        (0x3UL << FDCAN_TTTS_EVTSEL_Pos)          /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL            FDCAN_TTTS_EVTSEL_Msk                     /*!<Event trigger input selection            */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FDCANCCU (Clock Calibration unit)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ****************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ****************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  ***************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ****************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *****************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *****************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  **********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!< Memory bank enable bit */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!< Address/data multiplexing enable bit */
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!< Memory type */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                /*!< 0x00000008 */
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!< Memory data bus width */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000020 */
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!< Flash access enable */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!< Burst enable bit */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!< Wait signal polarity bit */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!< Wait timing configuration */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!< Write enable bit */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!< Wait enable bit */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!< Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!< Wait signal during asynchronous transfers */
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!< CRAM page size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!< Write burst enable */
+#define FMC_BCRx_CSCOUNT_Pos       (20U)
+#define FMC_BCRx_CSCOUNT_Msk       (0x3UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00300000 */
+#define FMC_BCRx_CSCOUNT           FMC_BCRx_CSCOUNT_Msk                        /*!< Chip Select (CS) counter */
+#define FMC_BCRx_CSCOUNT_0         (0x1UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00100000 */
+#define FMC_BCRx_CSCOUNT_1         (0x2UL << FMC_BCRx_CSCOUNT_Pos)             /*!< 0x00200000 */
+#define FMC_BCRx_NBLSET_Pos        (22U)
+#define FMC_BCRx_NBLSET_Msk        (0x3UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00C00000 */
+#define FMC_BCRx_NBLSET            FMC_BCRx_NBLSET_Msk                         /*!< Byte lane (NBL) setup */
+#define FMC_BCRx_NBLSET_0          (0x1UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00400000 */
+#define FMC_BCRx_NBLSET_1          (0x2UL << FMC_BCRx_NBLSET_Pos)              /*!< 0x00800000 */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  **********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!< Address setup phase duration */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)              /*!< 0x00000008 */
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!< Address-hold phase duration */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!< Data-phase duration */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)             /*!< 0x00008000 */
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!< Bus turnaround phase duration */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!< Clock divide ratio */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00800000 */
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!< Data latency for synchronous memory */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)              /*!< 0x08000000 */
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!< Access mode */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+#define FMC_BTRx_DATAHLD_Pos       (30U)
+#define FMC_BTRx_DATAHLD_Msk       (0x3UL << FMC_BTRx_DATAHLD_Pos)              /*!< 0xC0000000 */
+#define FMC_BTRx_DATAHLD           FMC_BTRx_DATAHLD_Msk                        /*!< Data Hold phase duration */
+#define FMC_BTRx_DATAHLD_0         (0x1UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x40000000 */
+#define FMC_BTRx_DATAHLD_1         (0x2UL << FMC_BTRx_DATAHLD_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_CFGR register  *****************/
+#define FMC_CFGR_CLKDIV_Pos        (16U)
+#define FMC_CFGR_CLKDIV_Msk        (0xFUL << FMC_CFGR_CLKDIV_Pos)               /*!< 0x000F0000 */
+#define FMC_CFGR_CLKDIV            FMC_CFGR_CLKDIV_Msk                         /*!< Clock divide ratio (for FMC_CLK signal) */
+#define FMC_CFGR_CLKDIV_0          (0x1UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00010000 */
+#define FMC_CFGR_CLKDIV_1          (0x2UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00020000 */
+#define FMC_CFGR_CLKDIV_2          (0x4UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00040000 */
+#define FMC_CFGR_CLKDIV_3          (0x8UL << FMC_CFGR_CLKDIV_Pos)              /*!< 0x00080000 */
+#define FMC_CFGR_CCLKEN_Pos        (20U)
+#define FMC_CFGR_CCLKEN_Msk        (0x1UL << FMC_CFGR_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_CFGR_CCLKEN            FMC_CFGR_CCLKEN_Msk                         /*!< Continuous clock enable */
+#define FMC_CFGR_BMAP_Pos          (24U)
+#define FMC_CFGR_BMAP_Msk          (0x3UL << FMC_CFGR_BMAP_Pos)                 /*!< 0x03000000 */
+#define FMC_CFGR_BMAP              FMC_CFGR_BMAP_Msk                           /*!< FMC memory region mapping */
+#define FMC_CFGR_BMAP_0            (0x1UL << FMC_CFGR_BMAP_Pos)                /*!< 0x01000000 */
+#define FMC_CFGR_BMAP_1            (0x2UL << FMC_CFGR_BMAP_Pos)                /*!< 0x02000000 */
+#define FMC_CFGR_FMCEN_Pos         (31U)
+#define FMC_CFGR_FMCEN_Msk         (0x1UL << FMC_CFGR_FMCEN_Pos)                /*!< 0x80000000 */
+#define FMC_CFGR_FMCEN             FMC_CFGR_FMCEN_Msk                          /*!< FMC controller enable */
+
+/******************  Bit definition for FMC_PCR register  *********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!< Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!< NAND Flash memory bank enable bit */
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!< Data bus width */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!< ECC computation logic enable bit */
+#define FMC_PCR_ECCALG_Pos         (8U)
+#define FMC_PCR_ECCALG_Msk         (0x1UL << FMC_PCR_ECCALG_Pos)               /*!< 0x00000100 */
+#define FMC_PCR_ECCALG             FMC_PCR_ECCALG_Msk                          /*!< ECC algorithm */
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!< CLE to RE delay */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!< ALE to RE delay */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */
+#define FMC_PCR_ECCSS_Pos          (17U)
+#define FMC_PCR_ECCSS_Msk          (0x7UL << FMC_PCR_ECCSS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCSS              FMC_PCR_ECCSS_Msk                           /*!< ECC page size */
+#define FMC_PCR_ECCSS_0            (0x1UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00020000 */
+#define FMC_PCR_ECCSS_1            (0x2UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00040000 */
+#define FMC_PCR_ECCSS_2            (0x4UL << FMC_PCR_ECCSS_Pos)                /*!< 0x00080000 */
+#define FMC_PCR_BCHECC_Pos         (24U)
+#define FMC_PCR_BCHECC_Msk         (0x1UL << FMC_PCR_BCHECC_Pos)                /*!< 0x01000000 */
+#define FMC_PCR_BCHECC             FMC_PCR_BCHECC_Msk                          /*!< BCH error correction capability */
+#define FMC_PCR_WEN_Pos            (25U)
+#define FMC_PCR_WEN_Msk            (0x1UL << FMC_PCR_WEN_Pos)                   /*!< 0x02000000 */
+#define FMC_PCR_WEN                FMC_PCR_WEN_Msk                             /*!< Write enable */
+
+/******************  Bit definition for FMC_SR register  ******************/
+#define FMC_SR_ISOST_Pos           (0U)
+#define FMC_SR_ISOST_Msk           (0x3UL << FMC_SR_ISOST_Pos)                  /*!< 0x00000003 */
+#define FMC_SR_ISOST               FMC_SR_ISOST_Msk                            /*!< FMC isolation state with respect to the AXI interface */
+#define FMC_SR_PEF_Pos             (4U)
+#define FMC_SR_PEF_Msk             (0x1UL << FMC_SR_PEF_Pos)                    /*!< 0x00000010 */
+#define FMC_SR_PEF                 FMC_SR_PEF_Msk                              /*!< Pipe Empty Flag */
+#define FMC_SR_NWRF_Pos            (6U)
+#define FMC_SR_NWRF_Msk            (0x1UL << FMC_SR_NWRF_Pos)                   /*!< 0x00000040 */
+#define FMC_SR_NWRF                FMC_SR_NWRF_Msk                             /*!< NAND write request flag */
+
+/******************  Bit definition for FMC_PMEM register  ********************/
+#define FMC_PMEM_MEMSET_Pos        (0U)
+#define FMC_PMEM_MEMSET_Msk        (0xFFUL << FMC_PMEM_MEMSET_Pos)             /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!< Common memory setup time */
+#define FMC_PMEM_MEMSET_0          (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+#define FMC_PMEM_MEMWAIT_Pos       (8U)
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFUL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!< Common memory wait time */
+#define FMC_PMEM_MEMWAIT_0         (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PMEM_MEMHOLD_Pos       (16U)
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFUL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!< Common memory hold time */
+#define FMC_PMEM_MEMHOLD_0         (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PMEM_MEMHIZ_Pos        (24U)
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFUL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!< Common memory databus Hi-Z time */
+#define FMC_PMEM_MEMHIZ_0          (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ********************/
+#define FMC_PATT_ATTSET_Pos        (0U)
+#define FMC_PATT_ATTSET_Msk        (0xFFUL << FMC_PATT_ATTSET_Pos)             /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!< Attribute memory setup time */
+#define FMC_PATT_ATTSET_0          (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+#define FMC_PATT_ATTWAIT_Pos       (8U)
+#define FMC_PATT_ATTWAIT_Msk       (0xFFUL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!< Attribute memory wait time */
+#define FMC_PATT_ATTWAIT_0         (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_PATT_ATTHOLD_Pos       (16U)
+#define FMC_PATT_ATTHOLD_Msk       (0xFFUL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!< Attribute memory hold time */
+#define FMC_PATT_ATTHOLD_0         (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+#define FMC_PATT_ATTHIZ_Pos        (24U)
+#define FMC_PATT_ATTHIZ_Msk        (0xFFUL << FMC_PATT_ATTHIZ_Pos)             /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!< Attribute memory data bus Hi-Z time */
+#define FMC_PATT_ATTHIZ_0          (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/*****************  Bit definition for FMC_HPR register  ******************/
+#define FMC_HPR_HPR_Pos            (0U)
+#define FMC_HPR_HPR_Msk            (0xFFFFFFFFUL << FMC_HPR_HPR_Pos)            /*!< 0xFFFFFFFF */
+#define FMC_HPR_HPR                FMC_HPR_HPR_Msk                             /*!< Hamming parity result */
+
+/****************  Bit definition for FMC_HECCR register  *****************/
+#define FMC_HECCR_HECC_Pos         (0U)
+#define FMC_HECCR_HECC_Msk         (0xFFFFFFFFUL << FMC_HECCR_HECC_Pos)         /*!< 0xFFFFFFFF */
+#define FMC_HECCR_HECC             FMC_HECCR_HECC_Msk                          /*!< ECC result */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!< Address setup phase duration */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x00000008 */
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!< Address-hold phase duration */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x00000080 */
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!< Data-phase duration */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)            /*!< 0x00008000 */
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!< Bus turnaround phase duration */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x00080000 */
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!< Access mode */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x20000000 */
+#define FMC_BWTRx_DATAHLD_Pos      (30U)
+#define FMC_BWTRx_DATAHLD_Msk      (0x3UL << FMC_BWTRx_DATAHLD_Pos)             /*!< 0xC0000000 */
+#define FMC_BWTRx_DATAHLD          FMC_BWTRx_DATAHLD_Msk                       /*!< Data Hold phase duration */
+#define FMC_BWTRx_DATAHLD_0        (0x1UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x40000000 */
+#define FMC_BWTRx_DATAHLD_1        (0x2UL << FMC_BWTRx_DATAHLD_Pos)            /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!< Number of column address bits */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000002 */
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!< Number of row address bits */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                 /*!< 0x00000008 */
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!< Memory data bus width */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000020 */
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!< Number of internal banks */
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!< CAS latency */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!< Write protection */
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!< SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000800 */
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!< Read pipe */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00004000 */
+#define FMC_SDCRx_SDEN_Pos         (16U)
+#define FMC_SDCRx_SDEN_Msk         (0x1UL << FMC_SDCRx_SDEN_Pos)               /*!< 0x00010000 */
+#define FMC_SDCRx_SDEN             FMC_SDCRx_SDEN_Msk                          /*!< SDRAM device enable */
+#define FMC_SDCRx_SDINIT_Pos       (17U)
+#define FMC_SDCRx_SDINIT_Msk       (0x1UL << FMC_SDCRx_SDINIT_Pos)             /*!< 0x00020000 */
+#define FMC_SDCRx_SDINIT           FMC_SDCRx_SDINIT_Msk                        /*!< SDRAM device initialization */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  **************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!< Load mode register to active */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)               /*!< 0x00000008 */
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<Exit self-refresh delay */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)               /*!< 0x00000080 */
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!< Self refresh time */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000800 */
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!< Row cycle delay */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00004000 */
+#define FMC_SDTRx_TRC_3            (0x8UL << FMC_SDTRx_TRC_Pos)                /*!< 0x00008000 */
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!< Recovery delay */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00040000 */
+#define FMC_SDTRx_TWR_3            (0x8UL << FMC_SDTRx_TWR_Pos)                /*!< 0x00080000 */
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!< Row precharge delay */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00400000 */
+#define FMC_SDTRx_TRP_3            (0x8UL << FMC_SDTRx_TRP_Pos)                /*!< 0x00800000 */
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!< Row to column delay */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x04000000 */
+#define FMC_SDTRx_TRCD_3           (0x8UL << FMC_SDTRx_TRCD_Pos)               /*!< 0x08000000 */
+
+/******************  Bit definition for FMC_SDCMR register  *******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!< Command mode */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
+#define FMC_SDCMR_DS2_Pos          (3U)
+#define FMC_SDCMR_DS2_Msk          (0x1UL << FMC_SDCMR_DS2_Pos)                /*!< 0x00000008 */
+#define FMC_SDCMR_DS2              FMC_SDCMR_DS2_Msk                           /*!< Command targeting SDRAM device 2 */
+#define FMC_SDCMR_DS1_Pos          (4U)
+#define FMC_SDCMR_DS1_Msk          (0x1UL << FMC_SDCMR_DS1_Pos)                /*!< 0x00000010 */
+#define FMC_SDCMR_DS1              FMC_SDCMR_DS1_Msk                           /*!< Command targeting SDRAM device 1 */
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!< Number of auto-refresh */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x3FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x007FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!< Mode register definition */
+
+/******************  Bit definition for FMC_SDRTR register  *******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!< Clear refresh error flag */
+#define FMC_SDRTR_RFSCNT_Pos       (1U)
+#define FMC_SDRTR_RFSCNT_Msk       (0x1FFFUL << FMC_SDRTR_RFSCNT_Pos)          /*!< 0x00003FFE */
+#define FMC_SDRTR_RFSCNT           FMC_SDRTR_RFSCNT_Msk                        /*!< Refresh timer count */
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!< RES interrupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ********************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!< Refresh error flag */
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!< Status mode for bank 1 */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!< Status mode for bank 2 */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
+#define FMC_SDSR_CMDOK_Pos         (15U)
+#define FMC_SDSR_CMDOK_Msk         (0x1UL << FMC_SDSR_CMDOK_Pos)               /*!< 0x00004000 */
+#define FMC_SDSR_CMDOK             FMC_SDSR_CMDOK_Msk                          /*!< Previous command status */
+
+/*******************  Bit definition for FMC_IER register  ********************/
+#define FMC_IER_IREE_Pos              (0U)
+#define FMC_IER_IREE_Msk              (0x1UL << FMC_IER_IREE_Pos)               /*!< 0x00000001 */
+#define FMC_IER_IREE                  FMC_IER_IREE_Msk                         /*!< Interrupt rising edge detection enable bit */
+#define FMC_IER_IHLE_Pos              (1U)
+#define FMC_IER_IHLE_Msk              (0x1UL << FMC_IER_IHLE_Pos)               /*!< 0x00000002 */
+#define FMC_IER_IHLE                  FMC_IER_IHLE_Msk                         /*!< Interrupt high-level detection enable bit */
+#define FMC_IER_IFEE_Pos              (2U)
+#define FMC_IER_IFEE_Msk              (0x1UL << FMC_IER_IFEE_Pos)               /*!< 0x00000004 */
+#define FMC_IER_IFEE                  FMC_IER_IFEE_Msk                         /*!< Interrupt falling edge detection enable bit */
+
+/*******************  Bit definition for FMC_ISR register  ********************/
+#define FMC_ISR_IREF_Pos              (0U)
+#define FMC_ISR_IREF_Msk              (0x1UL << FMC_ISR_IREF_Pos)               /*!< 0x00000001 */
+#define FMC_ISR_IREF                  FMC_ISR_IREF_Msk                         /*!< Interrupt rising edge flag */
+#define FMC_ISR_IHLF_Pos              (1U)
+#define FMC_ISR_IHLF_Msk              (0x1UL << FMC_ISR_IHLF_Pos)               /*!< 0x00000002 */
+#define FMC_ISR_IHLF                  FMC_ISR_IHLF_Msk                         /*!< Interrupt high-level flag */
+#define FMC_ISR_IFEF_Pos              (2U)
+#define FMC_ISR_IFEF_Msk              (0x1UL << FMC_ISR_IFEF_Pos)               /*!< 0x00000004 */
+#define FMC_ISR_IFEF                  FMC_ISR_IFEF_Msk                         /*!< Interrupt falling edge flag */
+
+/*******************  Bit definition for FMC_ICR register  ********************/
+#define FMC_ICR_CIREF_Pos             (0U)
+#define FMC_ICR_CIREF_Msk             (0x1UL << FMC_ICR_CIREF_Pos)              /*!< 0x00000001 */
+#define FMC_ICR_CIREF                 FMC_ICR_CIREF_Msk                        /*!< Clear Interrupt rising edge flag */
+#define FMC_ICR_CIHLF_Pos             (1U)
+#define FMC_ICR_CIHLF_Msk             (0x1UL << FMC_ICR_CIHLF_Pos)              /*!< 0x00000002 */
+#define FMC_ICR_CIHLF                 FMC_ICR_CIHLF_Msk                        /*!< Clear Interrupt high-level flag */
+#define FMC_ICR_CIFEF_Pos             (2U)
+#define FMC_ICR_CIFEF_Msk             (0x1UL << FMC_ICR_CIFEF_Pos)              /*!< 0x00000004 */
+#define FMC_ICR_CIFEF                 FMC_ICR_CIFEF_Msk                        /*!< Clear Interrupt falling edge flag */
+
+/****************  Bit definition for FMC_CSQCR register  *****************/
+#define FMC_CSQCR_CSQSTART_Pos        (0U)
+#define FMC_CSQCR_CSQSTART_Msk        (0x1UL << FMC_CSQCR_CSQSTART_Pos)         /*!< 0x00000001 */
+#define FMC_CSQCR_CSQSTART            FMC_CSQCR_CSQSTART_Msk                   /*!< Command Sequencer Enable */
+
+/***************  Bit definition for FMC_CSQCFGR1 register  ***************/
+#define FMC_CSQCFGR1_CMD2EN_Pos       (1U)
+#define FMC_CSQCFGR1_CMD2EN_Msk       (0x1UL << FMC_CSQCFGR1_CMD2EN_Pos)        /*!< 0x00000002 */
+#define FMC_CSQCFGR1_CMD2EN           FMC_CSQCFGR1_CMD2EN_Msk                  /*!< Command cycle 2 Enable */
+#define FMC_CSQCFGR1_DMADEN_Pos       (2U)
+#define FMC_CSQCFGR1_DMADEN_Msk       (0x1UL << FMC_CSQCFGR1_DMADEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR1_DMADEN           FMC_CSQCFGR1_DMADEN_Msk                  /*!< Command sequencer DMA request data enable */
+#define FMC_CSQCFGR1_ACYNBR_Pos       (4U)
+#define FMC_CSQCFGR1_ACYNBR_Msk       (0x7UL << FMC_CSQCFGR1_ACYNBR_Pos)        /*!< 0x00000070 */
+#define FMC_CSQCFGR1_ACYNBR           FMC_CSQCFGR1_ACYNBR_Msk                  /*!< Address Cycle number */
+#define FMC_CSQCFGR1_CMD1_Pos         (8U)
+#define FMC_CSQCFGR1_CMD1_Msk         (0xFFUL << FMC_CSQCFGR1_CMD1_Pos)         /*!< 0x0000FF00 */
+#define FMC_CSQCFGR1_CMD1             FMC_CSQCFGR1_CMD1_Msk                    /*!< Command 1 sequencer */
+#define FMC_CSQCFGR1_CMD2_Pos         (16U)
+#define FMC_CSQCFGR1_CMD2_Msk         (0xFFUL << FMC_CSQCFGR1_CMD2_Pos)         /*!< 0x00FF0000 */
+#define FMC_CSQCFGR1_CMD2             FMC_CSQCFGR1_CMD2_Msk                    /*!< Command 2 sequencer */
+#define FMC_CSQCFGR1_CMD1T_Pos        (24U)
+#define FMC_CSQCFGR1_CMD1T_Msk        (0x1UL << FMC_CSQCFGR1_CMD1T_Pos)         /*!< 0x01000000 */
+#define FMC_CSQCFGR1_CMD1T            FMC_CSQCFGR1_CMD1T_Msk                   /*!< Command 1 Sequencer timings */
+#define FMC_CSQCFGR1_CMD2T_Pos        (25U)
+#define FMC_CSQCFGR1_CMD2T_Msk        (0x1UL << FMC_CSQCFGR1_CMD2T_Pos)         /*!< 0x02000000 */
+#define FMC_CSQCFGR1_CMD2T            FMC_CSQCFGR1_CMD2T_Msk                   /*!< Command 2 Sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR2 register  ***************/
+#define FMC_CSQCFGR2_SQSDTEN_Pos      (0U)
+#define FMC_CSQCFGR2_SQSDTEN_Msk      (0x1UL << FMC_CSQCFGR2_SQSDTEN_Pos)       /*!< 0x00000001 */
+#define FMC_CSQCFGR2_SQSDTEN          FMC_CSQCFGR2_SQSDTEN_Msk                 /*!< Sequencer spare data transfer enable */
+#define FMC_CSQCFGR2_RCMD2EN_Pos      (1U)
+#define FMC_CSQCFGR2_RCMD2EN_Msk      (0x1UL << FMC_CSQCFGR2_RCMD2EN_Pos)       /*!< 0x00000002 */
+#define FMC_CSQCFGR2_RCMD2EN          FMC_CSQCFGR2_RCMD2EN_Msk                 /*!< Random Command 2 sequencer enable */
+#define FMC_CSQCFGR2_DMASEN_Pos       (2U)
+#define FMC_CSQCFGR2_DMASEN_Msk       (0x1UL << FMC_CSQCFGR2_DMASEN_Pos)        /*!< 0x00000004 */
+#define FMC_CSQCFGR2_DMASEN           FMC_CSQCFGR2_DMASEN_Msk                  /*!< Command sequencer DMA request decoding status enable */
+#define FMC_CSQCFGR2_RCMD1_Pos        (8U)
+#define FMC_CSQCFGR2_RCMD1_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD1_Pos)        /*!< 0x0000FF00 */
+#define FMC_CSQCFGR2_RCMD1            FMC_CSQCFGR2_RCMD1_Msk                   /*!< Random Command 1 sequencer */
+#define FMC_CSQCFGR2_RCMD2_Pos        (16U)
+#define FMC_CSQCFGR2_RCMD2_Msk        (0xFFUL << FMC_CSQCFGR2_RCMD2_Pos)        /*!< 0x00FF0000 */
+#define FMC_CSQCFGR2_RCMD2            FMC_CSQCFGR2_RCMD2_Msk                   /*!< Random Command 2 sequencer */
+#define FMC_CSQCFGR2_RCMD1T_Pos       (24U)
+#define FMC_CSQCFGR2_RCMD1T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD1T_Pos)        /*!< 0x01000000 */
+#define FMC_CSQCFGR2_RCMD1T           FMC_CSQCFGR2_RCMD1T_Msk                  /*!< Command 1 sequencer timings */
+#define FMC_CSQCFGR2_RCMD2T_Pos       (25U)
+#define FMC_CSQCFGR2_RCMD2T_Msk       (0x1UL << FMC_CSQCFGR2_RCMD2T_Pos)        /*!< 0x02000000 */
+#define FMC_CSQCFGR2_RCMD2T           FMC_CSQCFGR2_RCMD2T_Msk                  /*!< Command 1 sequencer timings */
+
+/***************  Bit definition for FMC_CSQCFGR3 register  ***************/
+#define FMC_CSQCFGR3_SNBR_Pos         (8U)
+#define FMC_CSQCFGR3_SNBR_Msk         (0x3FUL << FMC_CSQCFGR3_SNBR_Pos)         /*!< 0x00003F00 */
+#define FMC_CSQCFGR3_SNBR             FMC_CSQCFGR3_SNBR_Msk                    /*!< Number of sectors to be read/written */
+#define FMC_CSQCFGR3_AC1T_Pos         (16U)
+#define FMC_CSQCFGR3_AC1T_Msk         (0x1UL << FMC_CSQCFGR3_AC1T_Pos)          /*!< 0x00010000 */
+#define FMC_CSQCFGR3_AC1T             FMC_CSQCFGR3_AC1T_Msk                    /*!< Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_AC2T_Pos         (17U)
+#define FMC_CSQCFGR3_AC2T_Msk         (0x1UL << FMC_CSQCFGR3_AC2T_Pos)          /*!< 0x00020000 */
+#define FMC_CSQCFGR3_AC2T             FMC_CSQCFGR3_AC2T_Msk                    /*!< Address cycle 2 sequencer timings */
+#define FMC_CSQCFGR3_AC3T_Pos         (18U)
+#define FMC_CSQCFGR3_AC3T_Msk         (0x1UL << FMC_CSQCFGR3_AC3T_Pos)          /*!< 0x00040000 */
+#define FMC_CSQCFGR3_AC3T             FMC_CSQCFGR3_AC3T_Msk                    /*!< Address cycle 3 sequencer timings */
+#define FMC_CSQCFGR3_AC4T_Pos         (19U)
+#define FMC_CSQCFGR3_AC4T_Msk         (0x1UL << FMC_CSQCFGR3_AC4T_Pos)          /*!< 0x00080000 */
+#define FMC_CSQCFGR3_AC4T             FMC_CSQCFGR3_AC4T_Msk                    /*!< Address cycle 4sequencer timings */
+#define FMC_CSQCFGR3_AC5T_Pos         (20U)
+#define FMC_CSQCFGR3_AC5T_Msk         (0x1UL << FMC_CSQCFGR3_AC5T_Pos)          /*!< 0x00100000 */
+#define FMC_CSQCFGR3_AC5T             FMC_CSQCFGR3_AC5T_Msk                    /*!< Address cycle 5 sequencer timings */
+#define FMC_CSQCFGR3_SDT_Pos          (21U)
+#define FMC_CSQCFGR3_SDT_Msk          (0x1UL << FMC_CSQCFGR3_SDT_Pos)           /*!< 0x00200000 */
+#define FMC_CSQCFGR3_SDT              FMC_CSQCFGR3_SDT_Msk                     /*!< Spare data transfer sequencer timings */
+#define FMC_CSQCFGR3_RAC1T_Pos        (22U)
+#define FMC_CSQCFGR3_RAC1T_Msk        (0x1UL << FMC_CSQCFGR3_RAC1T_Pos)         /*!< 0x00400000 */
+#define FMC_CSQCFGR3_RAC1T            FMC_CSQCFGR3_RAC1T_Msk                   /*!< Random Address cycle 1 sequencer timings */
+#define FMC_CSQCFGR3_RAC2T_Pos        (23U)
+#define FMC_CSQCFGR3_RAC2T_Msk        (0x1UL << FMC_CSQCFGR3_RAC2T_Pos)         /*!< 0x00800000 */
+#define FMC_CSQCFGR3_RAC2T            FMC_CSQCFGR3_RAC2T_Msk                   /*!< Random Address cycle 2 sequencer timings */
+
+/****************  Bit definition for FMC_CSQAR1 register  ****************/
+#define FMC_CSQAR1_ADDC1_Pos          (0U)
+#define FMC_CSQAR1_ADDC1_Msk          (0xFFUL << FMC_CSQAR1_ADDC1_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR1_ADDC1              FMC_CSQAR1_ADDC1_Msk                     /*!< Address Cycle 1 */
+#define FMC_CSQAR1_ADDC2_Pos          (8U)
+#define FMC_CSQAR1_ADDC2_Msk          (0xFFUL << FMC_CSQAR1_ADDC2_Pos)          /*!< 0x0000FF00 */
+#define FMC_CSQAR1_ADDC2              FMC_CSQAR1_ADDC2_Msk                     /*!< Address Cycle 2 */
+#define FMC_CSQAR1_ADDC3_Pos          (16U)
+#define FMC_CSQAR1_ADDC3_Msk          (0xFFUL << FMC_CSQAR1_ADDC3_Pos)          /*!< 0x00FF0000 */
+#define FMC_CSQAR1_ADDC3              FMC_CSQAR1_ADDC3_Msk                     /*!< Address Cycle 3 */
+#define FMC_CSQAR1_ADDC4_Pos          (24U)
+#define FMC_CSQAR1_ADDC4_Msk          (0xFFUL << FMC_CSQAR1_ADDC4_Pos)          /*!< 0xFF000000 */
+#define FMC_CSQAR1_ADDC4              FMC_CSQAR1_ADDC4_Msk                     /*!< Address Cycle 4 */
+
+/****************  Bit definition for FMC_CSQAR2 register  ****************/
+#define FMC_CSQAR2_ADDC5_Pos          (0U)
+#define FMC_CSQAR2_ADDC5_Msk          (0xFFUL << FMC_CSQAR2_ADDC5_Pos)          /*!< 0x000000FF */
+#define FMC_CSQAR2_ADDC5              FMC_CSQAR2_ADDC5_Msk                     /*!< Address Cycle 5 */
+#define FMC_CSQAR2_SAO_Pos            (16U)
+#define FMC_CSQAR2_SAO_Msk            (0xFFFFUL << FMC_CSQAR2_SAO_Pos)          /*!< 0xFFFF0000 */
+#define FMC_CSQAR2_SAO                FMC_CSQAR2_SAO_Msk                       /*!< Spare Area Address Offset. */
+
+/****************  Bit definition for FMC_CSQIER register  ****************/
+#define FMC_CSQIER_TCIE_Pos           (0U)
+#define FMC_CSQIER_TCIE_Msk           (0x1UL << FMC_CSQIER_TCIE_Pos)            /*!< 0x00000001 */
+#define FMC_CSQIER_TCIE               FMC_CSQIER_TCIE_Msk                      /*!< Transfer Complete Interrupt enable */
+#define FMC_CSQIER_SCIE_Pos           (1U)
+#define FMC_CSQIER_SCIE_Msk           (0x1UL << FMC_CSQIER_SCIE_Pos)            /*!< 0x00000002 */
+#define FMC_CSQIER_SCIE               FMC_CSQIER_SCIE_Msk                      /*!< Sector Complete interrupt enable */
+#define FMC_CSQIER_SEIE_Pos           (2U)
+#define FMC_CSQIER_SEIE_Msk           (0x1UL << FMC_CSQIER_SEIE_Pos)            /*!< 0x00000004 */
+#define FMC_CSQIER_SEIE               FMC_CSQIER_SEIE_Msk                      /*!< Sector Error interrupt enable */
+#define FMC_CSQIER_SUEIE_Pos          (3U)
+#define FMC_CSQIER_SUEIE_Msk          (0x1UL << FMC_CSQIER_SUEIE_Pos)           /*!< 0x00000008 */
+#define FMC_CSQIER_SUEIE              FMC_CSQIER_SUEIE_Msk                     /*!< Sector Uncorrectable Error interrupt enable */
+#define FMC_CSQIER_CMDTCIE_Pos        (4U)
+#define FMC_CSQIER_CMDTCIE_Msk        (0x1UL << FMC_CSQIER_CMDTCIE_Pos)         /*!< 0x00000010 */
+#define FMC_CSQIER_CMDTCIE            FMC_CSQIER_CMDTCIE_Msk                   /*!< Command Transfer Complete interrupt enable */
+
+/****************  Bit definition for FMC_CSQISR register  ****************/
+#define FMC_CSQISR_TCF_Pos            (0U)
+#define FMC_CSQISR_TCF_Msk            (0x1UL << FMC_CSQISR_TCF_Pos)             /*!< 0x00000001 */
+#define FMC_CSQISR_TCF                FMC_CSQISR_TCF_Msk                       /*!< Transfer Complete flag */
+#define FMC_CSQISR_SCF_Pos            (1U)
+#define FMC_CSQISR_SCF_Msk            (0x1UL << FMC_CSQISR_SCF_Pos)             /*!< 0x00000002 */
+#define FMC_CSQISR_SCF                FMC_CSQISR_SCF_Msk                       /*!< Sector Complete flag */
+#define FMC_CSQISR_SEF_Pos            (2U)
+#define FMC_CSQISR_SEF_Msk            (0x1UL << FMC_CSQISR_SEF_Pos)             /*!< 0x00000004 */
+#define FMC_CSQISR_SEF                FMC_CSQISR_SEF_Msk                       /*!< Sector Error flag */
+#define FMC_CSQISR_SUEF_Pos           (3U)
+#define FMC_CSQISR_SUEF_Msk           (0x1UL << FMC_CSQISR_SUEF_Pos)            /*!< 0x00000008 */
+#define FMC_CSQISR_SUEF               FMC_CSQISR_SUEF_Msk                      /*!< Sector Uncorrectable Error flag */
+#define FMC_CSQISR_CMDTCF_Pos         (4U)
+#define FMC_CSQISR_CMDTCF_Msk         (0x1UL << FMC_CSQISR_CMDTCF_Pos)          /*!< 0x00000010 */
+#define FMC_CSQISR_CMDTCF             FMC_CSQISR_CMDTCF_Msk                    /*!< Command Transfer Complete flag */
+
+/****************  Bit definition for FMC_CSQICR register  ****************/
+#define FMC_CSQICR_CTCF_Pos           (0U)
+#define FMC_CSQICR_CTCF_Msk           (0x1UL << FMC_CSQICR_CTCF_Pos)            /*!< 0x00000001 */
+#define FMC_CSQICR_CTCF               FMC_CSQICR_CTCF_Msk                      /*!< Clear Transfer Complete flag */
+#define FMC_CSQICR_CSCF_Pos           (1U)
+#define FMC_CSQICR_CSCF_Msk           (0x1UL << FMC_CSQICR_CSCF_Pos)            /*!< 0x00000002 */
+#define FMC_CSQICR_CSCF               FMC_CSQICR_CSCF_Msk                      /*!< Clear Sector Complete flag */
+#define FMC_CSQICR_CSEF_Pos           (2U)
+#define FMC_CSQICR_CSEF_Msk           (0x1UL << FMC_CSQICR_CSEF_Pos)            /*!< 0x00000004 */
+#define FMC_CSQICR_CSEF               FMC_CSQICR_CSEF_Msk                      /*!< Clear Sector Error flag */
+#define FMC_CSQICR_CSUEF_Pos          (3U)
+#define FMC_CSQICR_CSUEF_Msk          (0x1UL << FMC_CSQICR_CSUEF_Pos)           /*!< 0x00000008 */
+#define FMC_CSQICR_CSUEF              FMC_CSQICR_CSUEF_Msk                     /*!< Clear Sector uncorrectable Error flag */
+#define FMC_CSQICR_CCMDTCF_Pos        (4U)
+#define FMC_CSQICR_CCMDTCF_Msk        (0x1UL << FMC_CSQICR_CCMDTCF_Pos)         /*!< 0x00000010 */
+#define FMC_CSQICR_CCMDTCF            FMC_CSQICR_CCMDTCF_Msk                   /*!< Clear Command Transfer Complete flag */
+
+/***************  Bit definition for FMC_CSQEMSR register  ****************/
+#define FMC_CSQEMSR_SEM_Pos           (0U)
+#define FMC_CSQEMSR_SEM_Msk           (0xFFFFUL << FMC_CSQEMSR_SEM_Pos)         /*!< 0x0000FFFF */
+#define FMC_CSQEMSR_SEM               FMC_CSQEMSR_SEM_Msk                      /*!< Sector Error mapping */
+
+/****************  Bit definition for FMC_BCHIER register  ****************/
+#define FMC_BCHIER_DUEIE_Pos          (0U)
+#define FMC_BCHIER_DUEIE_Msk          (0x1UL << FMC_BCHIER_DUEIE_Pos)           /*!< 0x00000001 */
+#define FMC_BCHIER_DUEIE              FMC_BCHIER_DUEIE_Msk                     /*!< Decoder Uncorrectable Errors Interrupt enable */
+#define FMC_BCHIER_DERIE_Pos          (1U)
+#define FMC_BCHIER_DERIE_Msk          (0x1UL << FMC_BCHIER_DERIE_Pos)           /*!< 0x00000002 */
+#define FMC_BCHIER_DERIE              FMC_BCHIER_DERIE_Msk                     /*!< Decoder Error Ready Interrupt enable */
+#define FMC_BCHIER_DEFIE_Pos          (2U)
+#define FMC_BCHIER_DEFIE_Msk          (0x1UL << FMC_BCHIER_DEFIE_Pos)           /*!< 0x00000004 */
+#define FMC_BCHIER_DEFIE              FMC_BCHIER_DEFIE_Msk                     /*!< Decoder Error Found Interrupt enable */
+#define FMC_BCHIER_DSRIE_Pos          (3U)
+#define FMC_BCHIER_DSRIE_Msk          (0x1UL << FMC_BCHIER_DSRIE_Pos)           /*!< 0x00000008 */
+#define FMC_BCHIER_DSRIE              FMC_BCHIER_DSRIE_Msk                     /*!< Decoder Syndrome Ready Interrupt enable */
+#define FMC_BCHIER_EPBRIE_Pos         (4U)
+#define FMC_BCHIER_EPBRIE_Msk         (0x1UL << FMC_BCHIER_EPBRIE_Pos)          /*!< 0x00000010 */
+#define FMC_BCHIER_EPBRIE             FMC_BCHIER_EPBRIE_Msk                    /*!< Decoder Parity Bits Ready Interrupt enable */
+
+/****************  Bit definition for FMC_BCHISR register  ****************/
+#define FMC_BCHISR_DUEF_Pos           (0U)
+#define FMC_BCHISR_DUEF_Msk           (0x1UL << FMC_BCHISR_DUEF_Pos)            /*!< 0x00000001 */
+#define FMC_BCHISR_DUEF               FMC_BCHISR_DUEF_Msk                      /*!< Decoder Uncorrectable Errors flag */
+#define FMC_BCHISR_DERF_Pos           (1U)
+#define FMC_BCHISR_DERF_Msk           (0x1UL << FMC_BCHISR_DERF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHISR_DERF               FMC_BCHISR_DERF_Msk                      /*!< Decoder Error Ready flag */
+#define FMC_BCHISR_DEFF_Pos           (2U)
+#define FMC_BCHISR_DEFF_Msk           (0x1UL << FMC_BCHISR_DEFF_Pos)            /*!< 0x00000004 */
+#define FMC_BCHISR_DEFF               FMC_BCHISR_DEFF_Msk                      /*!< Decoder Error Found flag */
+#define FMC_BCHISR_DSRF_Pos           (3U)
+#define FMC_BCHISR_DSRF_Msk           (0x1UL << FMC_BCHISR_DSRF_Pos)            /*!< 0x00000008 */
+#define FMC_BCHISR_DSRF               FMC_BCHISR_DSRF_Msk                      /*!< Decoder Syndrome Ready flag */
+#define FMC_BCHISR_EPBRF_Pos          (4U)
+#define FMC_BCHISR_EPBRF_Msk          (0x1UL << FMC_BCHISR_EPBRF_Pos)           /*!< 0x00000010 */
+#define FMC_BCHISR_EPBRF              FMC_BCHISR_EPBRF_Msk                     /*!< Encoder Parity Bits Ready flag */
+
+/****************  Bit definition for FMC_BCHICR register  ****************/
+#define FMC_BCHICR_CDUEF_Pos          (0U)
+#define FMC_BCHICR_CDUEF_Msk          (0x1UL << FMC_BCHICR_CDUEF_Pos)           /*!< 0x00000001 */
+#define FMC_BCHICR_CDUEF              FMC_BCHICR_CDUEF_Msk                     /*!< Clear Decoder Uncorrectable Error flag */
+#define FMC_BCHICR_CDERF_Pos          (1U)
+#define FMC_BCHICR_CDERF_Msk          (0x1UL << FMC_BCHICR_CDERF_Pos)           /*!< 0x00000002 */
+#define FMC_BCHICR_CDERF              FMC_BCHICR_CDERF_Msk                     /*!< Clear Decoder Error ready flag */
+#define FMC_BCHICR_CDEFF_Pos          (2U)
+#define FMC_BCHICR_CDEFF_Msk          (0x1UL << FMC_BCHICR_CDEFF_Pos)           /*!< 0x00000004 */
+#define FMC_BCHICR_CDEFF              FMC_BCHICR_CDEFF_Msk                     /*!< Clear Decoder Error Found flag */
+#define FMC_BCHICR_CDSRF_Pos          (3U)
+#define FMC_BCHICR_CDSRF_Msk          (0x1UL << FMC_BCHICR_CDSRF_Pos)           /*!< 0x00000008 */
+#define FMC_BCHICR_CDSRF              FMC_BCHICR_CDSRF_Msk                     /*!< Clear Decoder Syndrome Ready flag */
+#define FMC_BCHICR_CEPBRF_Pos         (4U)
+#define FMC_BCHICR_CEPBRF_Msk         (0x1UL << FMC_BCHICR_CEPBRF_Pos)          /*!< 0x00000010 */
+#define FMC_BCHICR_CEPBRF             FMC_BCHICR_CEPBRF_Msk                    /*!< Clear Encoder Parity Bits Ready flag */
+
+/***************  Bit definition for FMC_BCHPBR1 register  ****************/
+#define FMC_BCHPBR1_BCHPB_Pos         (0U)
+#define FMC_BCHPBR1_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR1_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR1_BCHPB             FMC_BCHPBR1_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR2 register  ****************/
+#define FMC_BCHPBR2_BCHPB_Pos         (0U)
+#define FMC_BCHPBR2_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR2_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR2_BCHPB             FMC_BCHPBR2_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR3 register  ****************/
+#define FMC_BCHPBR3_BCHPB_Pos         (0U)
+#define FMC_BCHPBR3_BCHPB_Msk         (0xFFFFFFFFUL << FMC_BCHPBR3_BCHPB_Pos)   /*!< 0xFFFFFFFF */
+#define FMC_BCHPBR3_BCHPB             FMC_BCHPBR3_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHPBR4 register  ****************/
+#define FMC_BCHPBR4_BCHPB_Pos         (0U)
+#define FMC_BCHPBR4_BCHPB_Msk         (0xFFUL << FMC_BCHPBR4_BCHPB_Pos)         /*!< 0x000000FF */
+#define FMC_BCHPBR4_BCHPB             FMC_BCHPBR4_BCHPB_Msk                    /*!< BCH parity bits */
+
+/***************  Bit definition for FMC_BCHDSR0 register  ****************/
+#define FMC_BCHDSR0_DUE_Pos           (0U)
+#define FMC_BCHDSR0_DUE_Msk           (0x1UL << FMC_BCHDSR0_DUE_Pos)            /*!< 0x00000001 */
+#define FMC_BCHDSR0_DUE               FMC_BCHDSR0_DUE_Msk                      /*!< Decoder uncorrectable error */
+#define FMC_BCHDSR0_DEF_Pos           (1U)
+#define FMC_BCHDSR0_DEF_Msk           (0x1UL << FMC_BCHDSR0_DEF_Pos)            /*!< 0x00000002 */
+#define FMC_BCHDSR0_DEF               FMC_BCHDSR0_DEF_Msk                      /*!< Decoder error found */
+#define FMC_BCHDSR0_DEN_Pos           (4U)
+#define FMC_BCHDSR0_DEN_Msk           (0xFUL << FMC_BCHDSR0_DEN_Pos)            /*!< 0x000000F0 */
+#define FMC_BCHDSR0_DEN               FMC_BCHDSR0_DEN_Msk                      /*!< Decoder error number */
+
+/***************  Bit definition for FMC_BCHDSR1 register  ****************/
+#define FMC_BCHDSR1_EBP1_Pos          (0U)
+#define FMC_BCHDSR1_EBP1_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP1_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR1_EBP1              FMC_BCHDSR1_EBP1_Msk                     /*!< Error bit position for error number 1 */
+#define FMC_BCHDSR1_EBP2_Pos          (16U)
+#define FMC_BCHDSR1_EBP2_Msk          (0x1FFFUL << FMC_BCHDSR1_EBP2_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR1_EBP2              FMC_BCHDSR1_EBP2_Msk                     /*!< Error bit position for error number 2 */
+
+/***************  Bit definition for FMC_BCHDSR2 register  ****************/
+#define FMC_BCHDSR2_EBP3_Pos          (0U)
+#define FMC_BCHDSR2_EBP3_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP3_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR2_EBP3              FMC_BCHDSR2_EBP3_Msk                     /*!< Error bit position for error number 3 */
+#define FMC_BCHDSR2_EBP4_Pos          (16U)
+#define FMC_BCHDSR2_EBP4_Msk          (0x1FFFUL << FMC_BCHDSR2_EBP4_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR2_EBP4              FMC_BCHDSR2_EBP4_Msk                     /*!< Error bit position for error number 4 */
+
+/***************  Bit definition for FMC_BCHDSR3 register  ****************/
+#define FMC_BCHDSR3_EBP5_Pos          (0U)
+#define FMC_BCHDSR3_EBP5_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP5_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR3_EBP5              FMC_BCHDSR3_EBP5_Msk                     /*!< Error bit position for error number 5 */
+#define FMC_BCHDSR3_EBP6_Pos          (16U)
+#define FMC_BCHDSR3_EBP6_Msk          (0x1FFFUL << FMC_BCHDSR3_EBP6_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR3_EBP6              FMC_BCHDSR3_EBP6_Msk                     /*!< Error bit position for error number 6 */
+
+/***************  Bit definition for FMC_BCHDSR4 register  ****************/
+#define FMC_BCHDSR4_EBP7_Pos          (0U)
+#define FMC_BCHDSR4_EBP7_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP7_Pos)        /*!< 0x00001FFF */
+#define FMC_BCHDSR4_EBP7              FMC_BCHDSR4_EBP7_Msk                     /*!< Error bit position for error number 7 */
+#define FMC_BCHDSR4_EBP8_Pos          (16U)
+#define FMC_BCHDSR4_EBP8_Msk          (0x1FFFUL << FMC_BCHDSR4_EBP8_Pos)        /*!< 0x1FFF0000 */
+#define FMC_BCHDSR4_EBP8              FMC_BCHDSR4_EBP8_Msk                     /*!< Error bit position for error number 8 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic MMU (GFXMMU)                                 */
+/*                                                                            */
+/******************************************************************************/
+/****************** Bits definition for GFXMMU_CR register ********************/
+#define GFXMMU_CR_B0OIE_Pos                (0U)
+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)      /*!< 0x00000001 */
+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */
+#define GFXMMU_CR_B1OIE_Pos                (1U)
+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)      /*!< 0x00000002 */
+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */
+#define GFXMMU_CR_B2OIE_Pos                (2U)
+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)      /*!< 0x00000004 */
+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */
+#define GFXMMU_CR_B3OIE_Pos                (3U)
+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)      /*!< 0x00000008 */
+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */
+#define GFXMMU_CR_AMEIE_Pos                (4U)
+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)      /*!< 0x00000010 */
+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */
+#define GFXMMU_CR_BS_Pos                   (6U)
+#define GFXMMU_CR_BS_Msk                   (0x1UL << GFXMMU_CR_BS_Pos)         /*!< 0x00000040 */
+#define GFXMMU_CR_BS                       GFXMMU_CR_BS_Msk                    /*!< Block size */
+#define GFXMMU_CR_ATE_Pos                  (15U)
+#define GFXMMU_CR_ATE_Msk                  (0x1UL << GFXMMU_CR_ATE_Pos)        /*!< 0x00008000 */
+#define GFXMMU_CR_ATE                      GFXMMU_CR_ATE_Msk                   /*!< Address translation enable */
+#define GFXMMU_CR_B0PE_Pos                 (24U)
+#define GFXMMU_CR_B0PE_Msk                 (0x1UL << GFXMMU_CR_B0PE_Pos)       /*!< 0x01000000 */
+#define GFXMMU_CR_B0PE                     GFXMMU_CR_B0PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B0PM_Pos                 (25U)
+#define GFXMMU_CR_B0PM_Msk                 (0x1UL << GFXMMU_CR_B0PM_Pos)       /*!< 0x02000000 */
+#define GFXMMU_CR_B0PM                     GFXMMU_CR_B0PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B1PE_Pos                 (26U)
+#define GFXMMU_CR_B1PE_Msk                 (0x1UL << GFXMMU_CR_B1PE_Pos)       /*!< 0x04000000 */
+#define GFXMMU_CR_B1PE                     GFXMMU_CR_B1PE_Msk                  /*!< Buffer 1 packing enable */
+#define GFXMMU_CR_B1PM_Pos                 (27U)
+#define GFXMMU_CR_B1PM_Msk                 (0x1UL << GFXMMU_CR_B1PM_Pos)       /*!< 0x08000000 */
+#define GFXMMU_CR_B1PM                     GFXMMU_CR_B1PM_Msk                  /*!< Buffer 1 packing mode */
+#define GFXMMU_CR_B2PE_Pos                 (28U)
+#define GFXMMU_CR_B2PE_Msk                 (0x1UL << GFXMMU_CR_B2PE_Pos)       /*!< 0x10000000 */
+#define GFXMMU_CR_B2PE                     GFXMMU_CR_B2PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B2PM_Pos                 (29U)
+#define GFXMMU_CR_B2PM_Msk                 (0x1UL << GFXMMU_CR_B2PM_Pos)       /*!< 0x20000000 */
+#define GFXMMU_CR_B2PM                     GFXMMU_CR_B2PM_Msk                  /*!< Buffer 0 packing mode */
+#define GFXMMU_CR_B3PE_Pos                 (30U)
+#define GFXMMU_CR_B3PE_Msk                 (0x1UL << GFXMMU_CR_B3PE_Pos)       /*!< 0x40000000 */
+#define GFXMMU_CR_B3PE                     GFXMMU_CR_B3PE_Msk                  /*!< Buffer 0 packing enable */
+#define GFXMMU_CR_B3PM_Pos                 (31U)
+#define GFXMMU_CR_B3PM_Msk                 (0x1UL << GFXMMU_CR_B3PM_Pos)       /*!< 0x80000000 */
+#define GFXMMU_CR_B3PM                     GFXMMU_CR_B3PM_Msk                  /*!< Buffer 0 packing mode */
+
+/****************** Bits definition for GFXMMU_SR register ********************/
+#define GFXMMU_SR_B0OF_Pos                 (0U)
+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)       /*!< 0x00000001 */
+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */
+#define GFXMMU_SR_B1OF_Pos                 (1U)
+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)       /*!< 0x00000002 */
+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */
+#define GFXMMU_SR_B2OF_Pos                 (2U)
+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)       /*!< 0x00000004 */
+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */
+#define GFXMMU_SR_B3OF_Pos                 (3U)
+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)       /*!< 0x00000008 */
+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */
+#define GFXMMU_SR_AMEF_Pos                 (4U)
+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)       /*!< 0x00000010 */
+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AXI master error flag */
+
+/****************** Bits definition for GFXMMU_FCR register *******************/
+#define GFXMMU_FCR_CB0OF_Pos               (0U)
+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)     /*!< 0x00000001 */
+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */
+#define GFXMMU_FCR_CB1OF_Pos               (1U)
+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)     /*!< 0x00000002 */
+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */
+#define GFXMMU_FCR_CB2OF_Pos               (2U)
+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)     /*!< 0x00000004 */
+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */
+#define GFXMMU_FCR_CB3OF_Pos               (3U)
+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)     /*!< 0x00000008 */
+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */
+#define GFXMMU_FCR_CAMEF_Pos               (4U)
+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)     /*!< 0x00000010 */
+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */
+
+/****************** Bits definition for GFXMMU_DVR register *******************/
+#define GFXMMU_DVR_DV_Pos                  (0U)
+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */
+
+/****************** Bits definition for GFXMMU_DAR register *******************/
+#define GFXMMU_DAR_DA_Pos                  (0U)
+#define GFXMMU_DAR_DA_Msk                  (0xFFUL << GFXMMU_DVR_DA_Pos)       /*!< 0x000000FF */
+#define GFXMMU_DAR_DA                      GFXMMU_DVR_DA_Msk                   /*!< DA[7:0] bits (Default alpha) */
+
+/****************** Bits definition for GFXMMU_B0CR register ******************/
+#define GFXMMU_B0CR_PBO_Pos                (4U)
+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B0CR_PBBA_Pos               (23U)
+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B1CR register ******************/
+#define GFXMMU_B1CR_PBO_Pos                (4U)
+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B1CR_PBBA_Pos               (23U)
+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B2CR register ******************/
+#define GFXMMU_B2CR_PBO_Pos                (4U)
+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B2CR_PBBA_Pos               (23U)
+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_B3CR register ******************/
+#define GFXMMU_B3CR_PBO_Pos                (4U)
+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)  /*!< 0x007FFFF0 */
+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */
+#define GFXMMU_B3CR_PBBA_Pos               (23U)
+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)   /*!< 0xFF800000 */
+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */
+
+/****************** Bits definition for GFXMMU_LUTxL register *****************/
+#define GFXMMU_LUTxL_EN_Pos                (0U)
+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)      /*!< 0x00000001 */
+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */
+#define GFXMMU_LUTxL_FVB_Pos               (8U)
+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)    /*!< 0x0000FF00 */
+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */
+#define GFXMMU_LUTxL_LVB_Pos               (16U)
+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)    /*!< 0x00FF0000 */
+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */
+
+/****************** Bits definition for GFXMMU_LUTxH register *****************/
+#define GFXMMU_LUTxH_LO_Pos                (0U)
+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)  /*!< 0x0003FFFF */
+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[17:0] bits (Line offset) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Graphic Timer (GFXTIM)                               */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CR_TES_Pos              (0U)
+#define GFXTIM_CR_TES_Msk              (0x3UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000003 */
+#define GFXTIM_CR_TES                  GFXTIM_CR_TES_Msk
+#define GFXTIM_CR_TES_0                (0x1UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000001 */
+#define GFXTIM_CR_TES_1                (0x2UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000002 */
+
+#define GFXTIM_CR_TEPOL_Pos            (4U)
+#define GFXTIM_CR_TEPOL_Msk            (0x1UL << GFXTIM_CR_TEPOL_Pos)          /*!< 0x00000010 */
+#define GFXTIM_CR_TEPOL                GFXTIM_CR_TEPOL_Msk
+
+#define GFXTIM_CR_SYNCS_Pos            (8U)
+#define GFXTIM_CR_SYNCS_Msk            (0x3UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000300 */
+#define GFXTIM_CR_SYNCS                GFXTIM_CR_SYNCS_Msk
+#define GFXTIM_CR_SYNCS_0              (0x1UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000100 */
+#define GFXTIM_CR_SYNCS_1              (0x2UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000200 */
+
+#define GFXTIM_CR_FCCOE_Pos            (16U)
+#define GFXTIM_CR_FCCOE_Msk            (0x1UL << GFXTIM_CR_FCCOE_Pos)          /*!< 0x00010000 */
+#define GFXTIM_CR_FCCOE                GFXTIM_CR_FCCOE_Msk
+
+#define GFXTIM_CR_LCCOE_Pos            (17U)
+#define GFXTIM_CR_LCCOE_Msk            (0x1UL << GFXTIM_CR_LCCOE_Pos)          /*!< 0x00020000 */
+#define GFXTIM_CR_LCCOE                GFXTIM_CR_LCCOE_Msk
+
+/******************  Bits definition for GFXTIM_CR register  ******************/
+#define GFXTIM_CGCR_LCS_Pos           (0U)
+#define GFXTIM_CGCR_LCS_Msk           (0x7UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_LCS               GFXTIM_CGCR_LCS_Msk
+#define GFXTIM_CGCR_LCS_0             (0x1UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000001 */
+#define GFXTIM_CGCR_LCS_1             (0x2UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000002 */
+#define GFXTIM_CGCR_LCS_2             (0x4UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000004 */
+
+#define GFXTIM_CGCR_LCCCS_Pos         (4U)
+#define GFXTIM_CGCR_LCCCS_Msk         (0x1UL << GFXTIM_CGCR_LCCCS_Pos)         /*!< 0x00000010 */
+#define GFXTIM_CGCR_LCCCS             GFXTIM_CGCR_LCCCS_Msk
+
+#define GFXTIM_CGCR_LCCFR_Pos         (8U)
+#define GFXTIM_CGCR_LCCFR_Msk         (0x1UL << GFXTIM_CGCR_LCCFR_Pos)         /*!< 0x00000100 */
+#define GFXTIM_CGCR_LCCFR             GFXTIM_CGCR_LCCFR_Msk
+
+#define GFXTIM_CGCR_LCCHRS_Pos        (12U)
+#define GFXTIM_CGCR_LCCHRS_Msk        (0x7UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00007000 */
+#define GFXTIM_CGCR_LCCHRS            GFXTIM_CGCR_LCCHRS_Msk
+#define GFXTIM_CGCR_LCCHRS_0          (0x1UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00001000 */
+#define GFXTIM_CGCR_LCCHRS_1          (0x2UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00002000 */
+#define GFXTIM_CGCR_LCCHRS_2          (0x4UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCS_Pos           (16U)
+#define GFXTIM_CGCR_FCS_Msk           (0x7UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00000007 */
+#define GFXTIM_CGCR_FCS               GFXTIM_CGCR_FCS_Msk
+#define GFXTIM_CGCR_FCS_0             (0x1UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00001000 */
+#define GFXTIM_CGCR_FCS_1             (0x2UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00002000 */
+#define GFXTIM_CGCR_FCS_2             (0x4UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00004000 */
+
+#define GFXTIM_CGCR_FCCCS_Pos         (20U)
+#define GFXTIM_CGCR_FCCCS_Msk         (0x7UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00070000 */
+#define GFXTIM_CGCR_FCCCS             GFXTIM_CGCR_FCCCS_Msk
+#define GFXTIM_CGCR_FCCCS_0           (0x1UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00010000 */
+#define GFXTIM_CGCR_FCCCS_1           (0x2UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00020000 */
+#define GFXTIM_CGCR_FCCCS_2           (0x4UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_CGCR_FCCFR_Pos         (24U)
+#define GFXTIM_CGCR_FCCFR_Msk         (0x1UL << GFXTIM_CGCR_FCCFR_Pos)         /*!< 0x00100000 */
+#define GFXTIM_CGCR_FCCFR             GFXTIM_CGCR_FCCFR_Msk
+
+#define GFXTIM_CGCR_FCCHRS_Pos        (28U)
+#define GFXTIM_CGCR_FCCHRS_Msk        (0x7UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x70000000 */
+#define GFXTIM_CGCR_FCCHRS            GFXTIM_CGCR_FCCHRS_Msk
+#define GFXTIM_CGCR_FCCHRS_0          (0x1UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x10000000 */
+#define GFXTIM_CGCR_FCCHRS_1          (0x2UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x20000000 */
+#define GFXTIM_CGCR_FCCHRS_2          (0x4UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_TCR register  *****************/
+#define GFXTIM_TCR_AFCEN_Pos           (0U)
+#define GFXTIM_TCR_AFCEN_Msk           (0x1UL << GFXTIM_TCR_AFCEN_Pos)         /*!< 0x00000001 */
+#define GFXTIM_TCR_AFCEN               GFXTIM_TCR_AFCEN_Msk
+
+#define GFXTIM_TCR_FAFCR_Pos           (1U)
+#define GFXTIM_TCR_FAFCR_Msk           (0x1UL << GFXTIM_TCR_FAFCR_Pos)         /*!< 0x00000002 */
+#define GFXTIM_TCR_FAFCR               GFXTIM_TCR_FAFCR_Msk
+
+#define GFXTIM_TCR_ALCEN_Pos           (4U)
+#define GFXTIM_TCR_ALCEN_Msk           (0x1UL << GFXTIM_TCR_ALCEN_Pos)         /*!< 0x00000010 */
+#define GFXTIM_TCR_ALCEN               GFXTIM_TCR_ALCEN_Msk
+
+#define GFXTIM_TCR_FALCR_Pos           (5U)
+#define GFXTIM_TCR_FALCR_Msk           (0x1UL << GFXTIM_TCR_FALCR_Pos)         /*!< 0x00000020 */
+#define GFXTIM_TCR_FALCR               GFXTIM_TCR_FALCR_Msk
+
+#define GFXTIM_TCR_RFC1EN_Pos          (16U)
+#define GFXTIM_TCR_RFC1EN_Msk          (0x1UL << GFXTIM_TCR_RFC1EN_Pos)        /*!< 0x00010000 */
+#define GFXTIM_TCR_RFC1EN              GFXTIM_TCR_RFC1EN_Msk
+
+#define GFXTIM_TCR_RFC1CM_Pos          (17U)
+#define GFXTIM_TCR_RFC1CM_Msk          (0x1UL << GFXTIM_TCR_RFC1CM_Pos)        /*!< 0x00020000 */
+#define GFXTIM_TCR_RFC1CM              GFXTIM_TCR_RFC1CM_Msk
+
+#define GFXTIM_TCR_FRFC1R_Pos          (18U)
+#define GFXTIM_TCR_FRFC1R_Msk          (0x1UL << GFXTIM_TCR_FRFC1R_Pos)        /*!< 0x00040000 */
+#define GFXTIM_TCR_FRFC1R              GFXTIM_TCR_FRFC1R_Msk
+
+#define GFXTIM_TCR_RFC2EN_Pos          (20U)
+#define GFXTIM_TCR_RFC2EN_Msk          (0x1UL << GFXTIM_TCR_RFC2EN_Pos)        /*!< 0x00100000 */
+#define GFXTIM_TCR_RFC2EN              GFXTIM_TCR_RFC2EN_Msk
+
+#define GFXTIM_TCR_RFC2CM_Pos          (21U)
+#define GFXTIM_TCR_RFC2CM_Msk          (0x1UL << GFXTIM_TCR_RFC2CM_Pos)        /*!< 0x00200000 */
+#define GFXTIM_TCR_RFC2CM              GFXTIM_TCR_RFC2CM_Msk
+
+#define GFXTIM_TCR_FRFC2R_Pos          (22U)
+#define GFXTIM_TCR_FRFC2R_Msk          (0x1UL << GFXTIM_TCR_FRFC2R_Pos)        /*!< 0x00400000 */
+#define GFXTIM_TCR_FRFC2R              GFXTIM_TCR_FRFC2R_Msk
+
+/******************  Bits definition for GFXTIM_TDR register  *****************/
+#define GFXTIM_TDR_AFCDIS_Pos          (0U)
+#define GFXTIM_TDR_AFCDIS_Msk          (0x1UL << GFXTIM_TDR_AFCDIS_Pos)        /*!< 0x00000001 */
+#define GFXTIM_TDR_AFCDIS              GFXTIM_TDR_AFCDIS_Msk
+
+#define GFXTIM_TDR_ALCDIS_Pos          (4U)
+#define GFXTIM_TDR_ALCDIS_Msk          (0x1UL << GFXTIM_TDR_ALCDIS_Pos)        /*!< 0x00000010 */
+#define GFXTIM_TDR_ALCDIS              GFXTIM_TDR_ALCDIS_Msk
+
+#define GFXTIM_TDR_RFC1DIS_Pos         (16U)
+#define GFXTIM_TDR_RFC1DIS_Msk         (0x1UL << GFXTIM_TDR_RFC1DIS_Pos)       /*!< 0x00010000 */
+#define GFXTIM_TDR_RFC1DIS             GFXTIM_TDR_RFC1DIS_Msk
+
+#define GFXTIM_TDR_RFC2DIS_Pos         (20U)
+#define GFXTIM_TDR_RFC2DIS_Msk         (0x1UL << GFXTIM_TDR_RFC2DIS_Pos)       /*!< 0x00100000 */
+#define GFXTIM_TDR_RFC2DIS             GFXTIM_TDR_RFC2DIS_Msk
+
+/******************  Bits definition for GFXTIM_EVCR register  ****************/
+#define GFXTIM_EVCR_EV1EN_Pos          (0U)
+#define GFXTIM_EVCR_EV1EN_Msk          (0x1UL << GFXTIM_EVCR_EV1EN_Pos)        /*!< 0x00000001 */
+#define GFXTIM_EVCR_EV1EN              GFXTIM_EVCR_EV1EN_Msk
+
+#define GFXTIM_EVCR_EV2EN_Pos          (1U)
+#define GFXTIM_EVCR_EV2EN_Msk          (0x1UL << GFXTIM_EVCR_EV2EN_Pos)        /*!< 0x00000002 */
+#define GFXTIM_EVCR_EV2EN              GFXTIM_EVCR_EV2EN_Msk
+
+#define GFXTIM_EVCR_EV3EN_Pos          (2U)
+#define GFXTIM_EVCR_EV3EN_Msk          (0x1UL << GFXTIM_EVCR_EV3EN_Pos)        /*!< 0x00000004 */
+#define GFXTIM_EVCR_EV3EN              GFXTIM_EVCR_EV3EN_Msk
+
+#define GFXTIM_EVCR_EV4EN_Pos          (3U)
+#define GFXTIM_EVCR_EV4EN_Msk          (0x1UL << GFXTIM_EVCR_EV4EN_Pos)        /*!< 0x00000008 */
+#define GFXTIM_EVCR_EV4EN              GFXTIM_EVCR_EV4EN_Msk
+
+/******************  Bits definition for GFXTIM_EVSR register  ****************/
+#define GFXTIM_EVSR_LES1_Pos           (0U)
+#define GFXTIM_EVSR_LES1_Msk           (0x7UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000007 */
+#define GFXTIM_EVSR_LES1               GFXTIM_EVSR_LES1_Msk
+#define GFXTIM_EVSR_LES1_0             (0x1UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000001 */
+#define GFXTIM_EVSR_LES1_1             (0x2UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000002 */
+#define GFXTIM_EVSR_LES1_2             (0x4UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000004 */
+
+#define GFXTIM_EVSR_FES1_Pos           (4U)
+#define GFXTIM_EVSR_FES1_Msk           (0x7UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000070 */
+#define GFXTIM_EVSR_FES1               GFXTIM_EVSR_FES1_Msk
+#define GFXTIM_EVSR_FES1_0             (0x1UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000010 */
+#define GFXTIM_EVSR_FES1_1             (0x2UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000020 */
+#define GFXTIM_EVSR_FES1_2             (0x4UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000040 */
+
+#define GFXTIM_EVSR_LES2_Pos           (8U)
+#define GFXTIM_EVSR_LES2_Msk           (0x7UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000700 */
+#define GFXTIM_EVSR_LES2               GFXTIM_EVSR_LES2_Msk
+#define GFXTIM_EVSR_LES2_0             (0x1UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000100 */
+#define GFXTIM_EVSR_LES2_1             (0x2UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000200 */
+#define GFXTIM_EVSR_LES2_2             (0x4UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000400 */
+
+#define GFXTIM_EVSR_FES2_Pos           (12U)
+#define GFXTIM_EVSR_FES2_Msk           (0x7UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00007000 */
+#define GFXTIM_EVSR_FES2               GFXTIM_EVSR_FES2_Msk
+#define GFXTIM_EVSR_FES2_0             (0x1UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00001000 */
+#define GFXTIM_EVSR_FES2_1             (0x2UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00002000 */
+#define GFXTIM_EVSR_FES2_2             (0x4UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00004000 */
+
+#define GFXTIM_EVSR_LES3_Pos           (16U)
+#define GFXTIM_EVSR_LES3_Msk           (0x7UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00070000 */
+#define GFXTIM_EVSR_LES3               GFXTIM_EVSR_LES3_Msk
+#define GFXTIM_EVSR_LES3_0             (0x1UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00010000 */
+#define GFXTIM_EVSR_LES3_1             (0x2UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00020000 */
+#define GFXTIM_EVSR_LES3_2             (0x4UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00040000 */
+
+#define GFXTIM_EVSR_FES3_Pos           (20U)
+#define GFXTIM_EVSR_FES3_Msk           (0x7UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00700000 */
+#define GFXTIM_EVSR_FES3               GFXTIM_EVSR_FES3_Msk
+#define GFXTIM_EVSR_FES3_0             (0x1UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00100000 */
+#define GFXTIM_EVSR_FES3_1             (0x2UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00200000 */
+#define GFXTIM_EVSR_FES3_2             (0x4UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00400000 */
+
+#define GFXTIM_EVSR_LES4_Pos           (24U)
+#define GFXTIM_EVSR_LES4_Msk           (0x7UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x07000000 */
+#define GFXTIM_EVSR_LES4               GFXTIM_EVSR_LES4_Msk
+#define GFXTIM_EVSR_LES4_0             (0x1UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x01000000 */
+#define GFXTIM_EVSR_LES4_1             (0x2UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x02000000 */
+#define GFXTIM_EVSR_LES4_2             (0x4UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x04000000 */
+
+#define GFXTIM_EVSR_FES4_Pos           (28U)
+#define GFXTIM_EVSR_FES4_Msk           (0x7UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x70000000 */
+#define GFXTIM_EVSR_FES4               GFXTIM_EVSR_FES4_Msk
+#define GFXTIM_EVSR_FES4_0             (0x1UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x10000000 */
+#define GFXTIM_EVSR_FES4_1             (0x2UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x20000000 */
+#define GFXTIM_EVSR_FES4_2             (0x4UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x40000000 */
+
+/******************  Bits definition for GFXTIM_WDGTCR register  **************/
+#define GFXTIM_WDGTCR_WDGEN_Pos        (0U)
+#define GFXTIM_WDGTCR_WDGEN_Msk        (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos)      /*!< 0x00000001 */
+#define GFXTIM_WDGTCR_WDGEN            GFXTIM_WDGTCR_WDGEN_Msk
+
+#define GFXTIM_WDGTCR_WDGDIS_Pos       (1U)
+#define GFXTIM_WDGTCR_WDGDIS_Msk       (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos)     /*!< 0x00000002 */
+#define GFXTIM_WDGTCR_WDGDIS           GFXTIM_WDGTCR_WDGDIS_Msk
+
+#define GFXTIM_WDGTCR_WDGS_Pos         (2U)
+#define GFXTIM_WDGTCR_WDGS_Msk         (0x1UL << GFXTIM_WDGTCR_WDGS_Pos)       /*!< 0x00000004 */
+#define GFXTIM_WDGTCR_WDGS             GFXTIM_WDGTCR_WDGS_Msk
+
+#define GFXTIM_WDGTCR_WDGHRC_Pos       (4U)
+#define GFXTIM_WDGTCR_WDGHRC_Msk       (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000030 */
+#define GFXTIM_WDGTCR_WDGHRC           GFXTIM_WDGTCR_WDGHRC_Msk
+#define GFXTIM_WDGTCR_WDGHRC_0         (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000010 */
+#define GFXTIM_WDGTCR_WDGHRC_1         (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000020 */
+
+#define GFXTIM_WDGTCR_WDGCS_Pos        (8U)
+#define GFXTIM_WDGTCR_WDGCS_Msk        (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000700 */
+#define GFXTIM_WDGTCR_WDGCS            GFXTIM_WDGTCR_WDGCS_Msk
+#define GFXTIM_WDGTCR_WDGCS_0          (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000100 */
+#define GFXTIM_WDGTCR_WDGCS_1          (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000200 */
+#define GFXTIM_WDGTCR_WDGCS_2          (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000400 */
+#define GFXTIM_WDGTCR_WDGCS_3          (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000800 */
+
+#define GFXTIM_WDGTCR_FWDGR_Pos        (16U)
+#define GFXTIM_WDGTCR_FWDGR_Msk        (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos)      /*!< 0x00010000 */
+#define GFXTIM_WDGTCR_FWDGR            GFXTIM_WDGTCR_FWDGR_Msk
+
+/******************  Bits definition for GFXTIM_ISR register  *****************/
+#define GFXTIM_ISR_AFCOF_Pos           (0U)
+#define GFXTIM_ISR_AFCOF_Msk           (0x1UL << GFXTIM_ISR_AFCOF_Pos)         /*!< 0x00000001 */
+#define GFXTIM_ISR_AFCOF               GFXTIM_ISR_AFCOF_Msk
+
+#define GFXTIM_ISR_ALCOF_Pos           (1U)
+#define GFXTIM_ISR_ALCOF_Msk           (0x1UL << GFXTIM_ISR_ALCOF_Pos)         /*!< 0x00000002 */
+#define GFXTIM_ISR_ALCOF               GFXTIM_ISR_ALCOF_Msk
+
+#define GFXTIM_ISR_TEF_Pos             (2U)
+#define GFXTIM_ISR_TEF_Msk             (0x1UL << GFXTIM_ISR_TEF_Pos)           /*!< 0x00000004 */
+#define GFXTIM_ISR_TEF                 GFXTIM_ISR_TEF_Msk
+
+#define GFXTIM_ISR_AFCC1F_Pos          (4U)
+#define GFXTIM_ISR_AFCC1F_Msk          (0x1UL << GFXTIM_ISR_AFCC1F_Pos)        /*!< 0x00000010 */
+#define GFXTIM_ISR_AFCC1F              GFXTIM_ISR_AFCC1F_Msk
+
+#define GFXTIM_ISR_ALCC1F_Pos          (8U)
+#define GFXTIM_ISR_ALCC1F_Msk          (0x1UL << GFXTIM_ISR_ALCC1F_Pos)        /*!< 0x00000100 */
+#define GFXTIM_ISR_ALCC1F              GFXTIM_ISR_ALCC1F_Msk
+
+#define GFXTIM_ISR_ALCC2F_Pos          (9U)
+#define GFXTIM_ISR_ALCC2F_Msk          (0x1UL << GFXTIM_ISR_ALCC2F_Pos)        /*!< 0x00000200 */
+#define GFXTIM_ISR_ALCC2F              GFXTIM_ISR_ALCC2F_Msk
+
+#define GFXTIM_ISR_RFC1RF_Pos          (12U)
+#define GFXTIM_ISR_RFC1RF_Msk          (0x1UL << GFXTIM_ISR_RFC1RF_Pos)        /*!< 0x00001000 */
+#define GFXTIM_ISR_RFC1RF              GFXTIM_ISR_RFC1RF_Msk
+
+#define GFXTIM_ISR_RFC2RF_Pos          (13U)
+#define GFXTIM_ISR_RFC2RF_Msk          (0x1UL << GFXTIM_ISR_RFC2RF_Pos)        /*!< 0x00002000 */
+#define GFXTIM_ISR_RFC2RF              GFXTIM_ISR_RFC2RF_Msk
+
+#define GFXTIM_ISR_EV1F_Pos            (16U)
+#define GFXTIM_ISR_EV1F_Msk            (0x1UL << GFXTIM_ISR_EV1F_Pos)          /*!< 0x00010000 */
+#define GFXTIM_ISR_EV1F                GFXTIM_ISR_EV1F_Msk
+
+#define GFXTIM_ISR_EV2F_Pos            (17U)
+#define GFXTIM_ISR_EV2F_Msk            (0x1UL << GFXTIM_ISR_EV2F_Pos)          /*!< 0x00020000 */
+#define GFXTIM_ISR_EV2F                GFXTIM_ISR_EV2F_Msk
+
+#define GFXTIM_ISR_EV3F_Pos            (18U)
+#define GFXTIM_ISR_EV3F_Msk            (0x1UL << GFXTIM_ISR_EV3F_Pos)          /*!< 0x00040000 */
+#define GFXTIM_ISR_EV3F                GFXTIM_ISR_EV3F_Msk
+
+#define GFXTIM_ISR_EV4F_Pos            (19U)
+#define GFXTIM_ISR_EV4F_Msk            (0x1UL << GFXTIM_ISR_EV4F_Pos)          /*!< 0x00080000 */
+#define GFXTIM_ISR_EV4F                GFXTIM_ISR_EV4F_Msk
+
+#define GFXTIM_ISR_WDGAF_Pos           (24U)
+#define GFXTIM_ISR_WDGAF_Msk           (0x1UL << GFXTIM_ISR_WDGAF_Pos)         /*!< 0x01000000 */
+#define GFXTIM_ISR_WDGAF               GFXTIM_ISR_WDGAF_Msk
+
+#define GFXTIM_ISR_WDGPF_Pos           (25U)
+#define GFXTIM_ISR_WDGPF_Msk           (0x1UL << GFXTIM_ISR_WDGPF_Pos)         /*!< 0x02000000 */
+#define GFXTIM_ISR_WDGPF               GFXTIM_ISR_WDGPF_Msk
+
+/******************  Bits definition for GFXTIM_ICR register  *****************/
+#define GFXTIM_ICR_CAFCOF_Pos          (0U)
+#define GFXTIM_ICR_CAFCOF_Msk          (0x1UL << GFXTIM_ICR_CAFCOF_Pos)        /*!< 0x00000001 */
+#define GFXTIM_ICR_CAFCOF              GFXTIM_ICR_CAFCOF_Msk
+
+#define GFXTIM_ICR_CALCOF_Pos          (1U)
+#define GFXTIM_ICR_CALCOF_Msk          (0x1UL << GFXTIM_ICR_CALCOF_Pos)        /*!< 0x00000002 */
+#define GFXTIM_ICR_CALCOF              GFXTIM_ICR_CALCOF_Msk
+
+#define GFXTIM_ICR_CTEF_Pos            (2U)
+#define GFXTIM_ICR_CTEF_Msk            (0x1UL << GFXTIM_ICR_CTEF_Pos)          /*!< 0x00000004 */
+#define GFXTIM_ICR_CTEF                GFXTIM_ICR_CTEF_Msk
+
+#define GFXTIM_ICR_CAFCC1F_Pos         (4U)
+#define GFXTIM_ICR_CAFCC1F_Msk         (0x1UL << GFXTIM_ICR_CAFCC1F_Pos)       /*!< 0x00000010 */
+#define GFXTIM_ICR_CAFCC1F             GFXTIM_ICR_CAFCC1F_Msk
+
+#define GFXTIM_ICR_CALCC1F_Pos         (8U)
+#define GFXTIM_ICR_CALCC1F_Msk         (0x1UL << GFXTIM_ICR_CALCC1F_Pos)       /*!< 0x00000100 */
+#define GFXTIM_ICR_CALCC1F             GFXTIM_ICR_CALCC1F_Msk
+
+#define GFXTIM_ICR_CALCC2F_Pos         (9U)
+#define GFXTIM_ICR_CALCC2F_Msk         (0x1UL << GFXTIM_ICR_CALCC2F_Pos)       /*!< 0x00000200 */
+#define GFXTIM_ICR_CALCC2F             GFXTIM_ICR_CALCC2F_Msk
+
+#define GFXTIM_ICR_CRFC1RF_Pos         (12U)
+#define GFXTIM_ICR_CRFC1RF_Msk         (0x1UL << GFXTIM_ICR_CRFC1RF_Pos)       /*!< 0x00001000 */
+#define GFXTIM_ICR_CRFC1RF             GFXTIM_ICR_CRFC1RF_Msk
+
+#define GFXTIM_ICR_CRFC2RF_Pos         (13U)
+#define GFXTIM_ICR_CRFC2RF_Msk         (0x1UL << GFXTIM_ICR_CRFC2RF_Pos)       /*!< 0x00002000 */
+#define GFXTIM_ICR_CRFC2RF             GFXTIM_ICR_CRFC2RF_Msk
+
+#define GFXTIM_ICR_CEV1F_Pos           (16U)
+#define GFXTIM_ICR_CEV1F_Msk           (0x1UL << GFXTIM_ICR_CEV1F_Pos)         /*!< 0x00010000 */
+#define GFXTIM_ICR_CEV1F               GFXTIM_ICR_CEV1F_Msk
+
+#define GFXTIM_ICR_CEV2F_Pos           (17U)
+#define GFXTIM_ICR_CEV2F_Msk           (0x1UL << GFXTIM_ICR_CEV2F_Pos)         /*!< 0x00020000 */
+#define GFXTIM_ICR_CEV2F               GFXTIM_ICR_CEV2F_Msk
+
+#define GFXTIM_ICR_CEV3F_Pos           (18U)
+#define GFXTIM_ICR_CEV3F_Msk           (0x1UL << GFXTIM_ICR_CEV3F_Pos)         /*!< 0x00040000 */
+#define GFXTIM_ICR_CEV3F               GFXTIM_ICR_CEV3F_Msk
+
+#define GFXTIM_ICR_CEV4F_Pos           (19U)
+#define GFXTIM_ICR_CEV4F_Msk           (0x1UL << GFXTIM_ICR_CEV4F_Pos)         /*!< 0x00080000 */
+#define GFXTIM_ICR_CEV4F               GFXTIM_ICR_CEV4F_Msk
+
+#define GFXTIM_ICR_CWDGAF_Pos          (24U)
+#define GFXTIM_ICR_CWDGAF_Msk          (0x1UL << GFXTIM_ICR_CWDGAF_Pos)        /*!< 0x01000000 */
+#define GFXTIM_ICR_CWDGAF              GFXTIM_ICR_CWDGAF_Msk
+
+#define GFXTIM_ICR_CWDGPF_Pos          (25U)
+#define GFXTIM_ICR_CWDGPF_Msk          (0x1UL << GFXTIM_ICR_CWDGPF_Pos)        /*!< 0x02000000 */
+#define GFXTIM_ICR_CWDGPF              GFXTIM_ICR_CWDGPF_Msk
+
+/******************  Bits definition for GFXTIM_IER register  *****************/
+#define GFXTIM_IER_AFCOIE_Pos          (0U)
+#define GFXTIM_IER_AFCOIE_Msk          (0x1UL << GFXTIM_IER_AFCOIE_Pos)        /*!< 0x00000001 */
+#define GFXTIM_IER_AFCOIE              GFXTIM_IER_AFCOIE_Msk
+
+#define GFXTIM_IER_ALCOIE_Pos          (1U)
+#define GFXTIM_IER_ALCOIE_Msk          (0x1UL << GFXTIM_IER_ALCOIE_Pos)        /*!< 0x00000002 */
+#define GFXTIM_IER_ALCOIE              GFXTIM_IER_ALCOIE_Msk
+
+#define GFXTIM_IER_TEIE_Pos            (2U)
+#define GFXTIM_IER_TEIE_Msk            (0x1UL << GFXTIM_IER_TEIE_Pos)          /*!< 0x00000004 */
+#define GFXTIM_IER_TEIE                GFXTIM_IER_TEIE_Msk
+
+#define GFXTIM_IER_AFCC1IE_Pos         (4U)
+#define GFXTIM_IER_AFCC1IE_Msk         (0x1UL << GFXTIM_IER_AFCC1IE_Pos)       /*!< 0x00000010 */
+#define GFXTIM_IER_AFCC1IE             GFXTIM_IER_AFCC1IE_Msk
+
+#define GFXTIM_IER_ALCC1IE_Pos         (8U)
+#define GFXTIM_IER_ALCC1IE_Msk         (0x1UL << GFXTIM_IER_ALCC1IE_Pos)       /*!< 0x00000100 */
+#define GFXTIM_IER_ALCC1IE             GFXTIM_IER_ALCC1IE_Msk
+
+#define GFXTIM_IER_ALCC2IE_Pos         (9U)
+#define GFXTIM_IER_ALCC2IE_Msk         (0x1UL << GFXTIM_IER_ALCC2IE_Pos)       /*!< 0x00000200 */
+#define GFXTIM_IER_ALCC2IE             GFXTIM_IER_ALCC2IE_Msk
+
+#define GFXTIM_IER_RFC1RIE_Pos         (12U)
+#define GFXTIM_IER_RFC1RIE_Msk         (0x1UL << GFXTIM_IER_RFC1RIE_Pos)       /*!< 0x00001000 */
+#define GFXTIM_IER_RFC1RIE             GFXTIM_IER_RFC1RIE_Msk
+
+#define GFXTIM_IER_RFC2RIE_Pos         (13U)
+#define GFXTIM_IER_RFC2RIE_Msk         (0x1UL << GFXTIM_IER_RFC2RIE_Pos)       /*!< 0x00002000 */
+#define GFXTIM_IER_RFC2RIE             GFXTIM_IER_RFC2RIE_Msk
+
+#define GFXTIM_IER_EV1IE_Pos           (16U)
+#define GFXTIM_IER_EV1IE_Msk           (0x1UL << GFXTIM_IER_EV1IE_Pos)         /*!< 0x00010000 */
+#define GFXTIM_IER_EV1IE               GFXTIM_IER_EV1IE_Msk
+
+#define GFXTIM_IER_EV2IE_Pos           (17U)
+#define GFXTIM_IER_EV2IE_Msk           (0x1UL << GFXTIM_IER_EV2IE_Pos)         /*!< 0x00020000 */
+#define GFXTIM_IER_EV2IE               GFXTIM_IER_EV2IE_Msk
+
+#define GFXTIM_IER_EV3IE_Pos           (18U)
+#define GFXTIM_IER_EV3IE_Msk           (0x1UL << GFXTIM_IER_EV3IE_Pos)         /*!< 0x00040000 */
+#define GFXTIM_IER_EV3IE               GFXTIM_IER_EV3IE_Msk
+
+#define GFXTIM_IER_EV4IE_Pos           (19U)
+#define GFXTIM_IER_EV4IE_Msk           (0x1UL << GFXTIM_IER_EV4IE_Pos)         /*!< 0x00080000 */
+#define GFXTIM_IER_EV4IE               GFXTIM_IER_EV4IE_Msk
+
+#define GFXTIM_IER_WDGAIE_Pos          (24U)
+#define GFXTIM_IER_WDGAIE_Msk          (0x1UL << GFXTIM_IER_WDGAIE_Pos)        /*!< 0x01000000 */
+#define GFXTIM_IER_WDGAIE              GFXTIM_IER_WDGAIE_Msk
+
+#define GFXTIM_IER_WDGPIE_Pos          (25U)
+#define GFXTIM_IER_WDGPIE_Msk          (0x1UL << GFXTIM_IER_WDGPIE_Pos)        /*!< 0x02000000 */
+#define GFXTIM_IER_WDGPIE              GFXTIM_IER_WDGPIE_Msk
+
+/******************  Bits definition for GFXTIM_TSR register  *****************/
+#define GFXTIM_TSR_AFCS_Pos            (0U)
+#define GFXTIM_TSR_AFCS_Msk            (0x1UL << GFXTIM_TSR_AFCS_Pos)          /*!< 0x00000001 */
+#define GFXTIM_TSR_AFCS                GFXTIM_TSR_AFCS_Msk
+
+#define GFXTIM_TSR_ALCS_Pos            (4U)
+#define GFXTIM_TSR_ALCS_Msk            (0x1UL << GFXTIM_TSR_ALCS_Pos)          /*!< 0x00000010 */
+#define GFXTIM_TSR_ALCS                GFXTIM_TSR_ALCS_Msk
+
+#define GFXTIM_TSR_RFC1S_Pos           (16U)
+#define GFXTIM_TSR_RFC1S_Msk           (0x1UL << GFXTIM_TSR_RFC1S_Pos)         /*!< 0x00010000 */
+#define GFXTIM_TSR_RFC1S               GFXTIM_TSR_RFC1S_Msk
+
+#define GFXTIM_TSR_RFC2S_Pos           (20U)
+#define GFXTIM_TSR_RFC2S_Msk           (0x1UL << GFXTIM_TSR_RFC2S_Pos)         /*!< 0x00100000 */
+#define GFXTIM_TSR_RFC2S               GFXTIM_TSR_RFC2S_Msk
+
+/******************  Bits definition for GFXTIM_LCCRR register  ***************/
+#define GFXTIM_LCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_LCCRR_RELOAD_Msk        (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
+#define GFXTIM_LCCRR_RELOAD            GFXTIM_LCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_FCCRR register  ***************/
+#define GFXTIM_FCCRR_RELOAD_Pos        (0U)
+#define GFXTIM_FCCRR_RELOAD_Msk        (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_FCCRR_RELOAD            GFXTIM_FCCRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_ATR register  *****************/
+#define GFXTIM_ATR_LINE_Pos            (0U)
+#define GFXTIM_ATR_LINE_Msk            (0xFFFUL << GFXTIM_ATR_LINE_Pos)        /*!< 0x00000FFF */
+#define GFXTIM_ATR_LINE                GFXTIM_ATR_LINE_Msk
+
+#define GFXTIM_ATR_FRAME_Pos           (12U)
+#define GFXTIM_ATR_FRAME_Msk           (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos)     /*!< 0xFFFFF000 */
+#define GFXTIM_ATR_FRAME               GFXTIM_ATR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_AFCR register  ****************/
+#define GFXTIM_AFCR_FRAME_Pos          (0U)
+#define GFXTIM_AFCR_FRAME_Msk          (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos)    /*!< 0x000FFFFF */
+#define GFXTIM_AFCR_FRAME              GFXTIM_AFCR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCR register  ****************/
+#define GFXTIM_ALCR_LINE_Pos           (0U)
+#define GFXTIM_ALCR_LINE_Msk           (0xFFFUL << GFXTIM_ALCR_LINE_Pos)       /*!< 0x00000FFF */
+#define GFXTIM_ALCR_LINE               GFXTIM_ALCR_LINE_Msk
+
+/******************  Bits definition for GFXTIM_AFCC1R register  **************/
+#define GFXTIM_AFCC1R_FRAME_Pos        (0U)
+#define GFXTIM_AFCC1R_FRAME_Msk        (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos)  /*!< 0x000FFFFF */
+#define GFXTIM_AFCC1R_FRAME            GFXTIM_AFCC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_ALCC1R register  **************/
+#define GFXTIM_ALCC1R_LINE_Pos         (0U)
+#define GFXTIM_ALCC1R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC1R_LINE             GFXTIM_ALCC1R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_ALCC2R register  **************/
+#define GFXTIM_ALCC2R_LINE_Pos         (0U)
+#define GFXTIM_ALCC2R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_ALCC2R_LINE             GFXTIM_ALCC2R_LINE_Msk
+
+/******************  Bits definition for GFXTIM_RFC1R register  ***************/
+#define GFXTIM_RFC1R_FRAME_Pos         (0U)
+#define GFXTIM_RFC1R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC1R_FRAME             GFXTIM_RFC1R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC1RR register  **************/
+#define GFXTIM_RFC1RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC1RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC1RR_FRAME            GFXTIM_RFC1RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2R register  ***************/
+#define GFXTIM_RFC2R_FRAME_Pos         (0U)
+#define GFXTIM_RFC2R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos)     /*!< 0x00000FFF */
+#define GFXTIM_RFC2R_FRAME             GFXTIM_RFC2R_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_RFC2RR register  **************/
+#define GFXTIM_RFC2RR_FRAME_Pos        (0U)
+#define GFXTIM_RFC2RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos)    /*!< 0x00000FFF */
+#define GFXTIM_RFC2RR_FRAME            GFXTIM_RFC2RR_FRAME_Msk
+
+/******************  Bits definition for GFXTIM_WDGCR register  ***************/
+#define GFXTIM_WDGCR_VALUE_Pos         (0U)
+#define GFXTIM_WDGCR_VALUE_Msk         (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos)    /*!< 0x0000FFFF */
+#define GFXTIM_WDGCR_VALUE             GFXTIM_WDGCR_VALUE_Msk
+
+/******************  Bits definition for GFXTIM_WDGRR register  ***************/
+#define GFXTIM_WDGRR_RELOAD_Pos        (0U)
+#define GFXTIM_WDGRR_RELOAD_Msk        (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos)   /*!< 0x0000FFFF */
+#define GFXTIM_WDGRR_RELOAD            GFXTIM_WDGRR_RELOAD_Msk
+
+/******************  Bits definition for GFXTIM_WDGPAR register  **************/
+#define GFXTIM_WDGPAR_PREALARM_Pos      (0U)
+#define GFXTIM_WDGPAR_PREALARM_Msk     (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
+#define GFXTIM_WDGPAR_PREALARM          GFXTIM_WDGPAR_PREALARM_Msk
+
+/******************  Bits definition for GFXTIM_HWCFGR register  **************/
+
+/******************  Bits definition for GFXTIM_VERR register  ****************/
+#define GFXTIM_VERR_MINREV_Pos         (0U)
+#define GFXTIM_VERR_MINREV_Msk         (0xFUL << GFXTIM_VERR_MINREV_Pos)       /*!< 0x0000000F */
+#define GFXTIM_VERR_MINREV             GFXTIM_VERR_MINREV_Msk
+
+#define GFXTIM_VERR_MAJREV_Pos         (4U)
+#define GFXTIM_VERR_MAJREV_Msk         (0xFUL << GFXTIM_VERR_MAJREV_Pos)       /*!< 0x000000F0 */
+#define GFXTIM_VERR_MAJREV             GFXTIM_VERR_MAJREV_Msk
+
+/******************  Bits definition for GFXTIM_IPIDR register  ***************/
+#define GFXTIM_IPIDR_ID_Pos            (0U)
+#define GFXTIM_IPIDR_ID_Msk            (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_IPIDR_ID                GFXTIM_IPIDR_ID_Msk
+
+/******************  Bits definition for GFXTIM_SIDR register  ****************/
+#define GFXTIM_SIDR_SID_Pos            (0U)
+#define GFXTIM_SIDR_SID_Msk            (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos)   /*!< 0xFFFFFFFF */
+#define GFXTIM_SIDR_SID                GFXTIM_SIDR_SID_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)
+#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos               (1U)
+#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos               (2U)
+#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos               (3U)
+#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos               (4U)
+#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos               (5U)
+#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos               (6U)
+#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos               (7U)
+#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos               (8U)
+#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos               (9U)
+#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos              (10U)
+#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos              (11U)
+#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos              (12U)
+#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos              (13U)
+#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos              (14U)
+#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos              (15U)
+#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
+
+/******************  Bits definition for GPIO_SECCFGR register  ******************/
+#define GPIO_SECCFGR_SEC0_Pos          (0U)
+#define GPIO_SECCFGR_SEC0_Msk          (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
+#define GPIO_SECCFGR_SEC0              GPIO_SECCFGR_SEC0_Msk
+#define GPIO_SECCFGR_SEC1_Pos          (1U)
+#define GPIO_SECCFGR_SEC1_Msk          (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
+#define GPIO_SECCFGR_SEC1              GPIO_SECCFGR_SEC1_Msk
+#define GPIO_SECCFGR_SEC2_Pos          (2U)
+#define GPIO_SECCFGR_SEC2_Msk          (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
+#define GPIO_SECCFGR_SEC2              GPIO_SECCFGR_SEC2_Msk
+#define GPIO_SECCFGR_SEC3_Pos          (3U)
+#define GPIO_SECCFGR_SEC3_Msk          (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
+#define GPIO_SECCFGR_SEC3              GPIO_SECCFGR_SEC3_Msk
+#define GPIO_SECCFGR_SEC4_Pos          (4U)
+#define GPIO_SECCFGR_SEC4_Msk          (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
+#define GPIO_SECCFGR_SEC4              GPIO_SECCFGR_SEC4_Msk
+#define GPIO_SECCFGR_SEC5_Pos          (5U)
+#define GPIO_SECCFGR_SEC5_Msk          (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
+#define GPIO_SECCFGR_SEC5              GPIO_SECCFGR_SEC5_Msk
+#define GPIO_SECCFGR_SEC6_Pos          (6U)
+#define GPIO_SECCFGR_SEC6_Msk          (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
+#define GPIO_SECCFGR_SEC6              GPIO_SECCFGR_SEC6_Msk
+#define GPIO_SECCFGR_SEC7_Pos          (7U)
+#define GPIO_SECCFGR_SEC7_Msk          (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
+#define GPIO_SECCFGR_SEC7              GPIO_SECCFGR_SEC7_Msk
+#define GPIO_SECCFGR_SEC8_Pos          (8U)
+#define GPIO_SECCFGR_SEC8_Msk          (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
+#define GPIO_SECCFGR_SEC8              GPIO_SECCFGR_SEC8_Msk
+#define GPIO_SECCFGR_SEC9_Pos          (9U)
+#define GPIO_SECCFGR_SEC9_Msk          (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
+#define GPIO_SECCFGR_SEC9              GPIO_SECCFGR_SEC9_Msk
+#define GPIO_SECCFGR_SEC10_Pos         (10U)
+#define GPIO_SECCFGR_SEC10_Msk         (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
+#define GPIO_SECCFGR_SEC10             GPIO_SECCFGR_SEC10_Msk
+#define GPIO_SECCFGR_SEC11_Pos         (11U)
+#define GPIO_SECCFGR_SEC11_Msk         (0x1UL << GPIO_SECCFGR_SEC11_Pos)       /*!< 0x00000800 */
+#define GPIO_SECCFGR_SEC11             GPIO_SECCFGR_SEC11_Msk
+#define GPIO_SECCFGR_SEC12_Pos         (12U)
+#define GPIO_SECCFGR_SEC12_Msk         (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
+#define GPIO_SECCFGR_SEC12             GPIO_SECCFGR_SEC12_Msk
+#define GPIO_SECCFGR_SEC13_Pos         (13U)
+#define GPIO_SECCFGR_SEC13_Msk         (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
+#define GPIO_SECCFGR_SEC13             GPIO_SECCFGR_SEC13_Msk
+#define GPIO_SECCFGR_SEC14_Pos         (14U)
+#define GPIO_SECCFGR_SEC14_Msk         (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
+#define GPIO_SECCFGR_SEC14             GPIO_SECCFGR_SEC14_Msk
+#define GPIO_SECCFGR_SEC15_Pos         (15U)
+#define GPIO_SECCFGR_SEC15_Msk         (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
+#define GPIO_SECCFGR_SEC15             GPIO_SECCFGR_SEC15_Msk
+
+/******************  Bits definition for GPIO_PRIVCFGR register  ******************/
+#define GPIO_PRIVCFGR_PRIV0_Pos        (0U)
+#define GPIO_PRIVCFGR_PRIV0_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV0_Pos)      /*!< 0x00000001 */
+#define GPIO_PRIVCFGR_PRIV0            GPIO_PRIVCFGR_PRIV0_Msk
+#define GPIO_PRIVCFGR_PRIV1_Pos        (1U)
+#define GPIO_PRIVCFGR_PRIV1_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV1_Pos)      /*!< 0x00000002 */
+#define GPIO_PRIVCFGR_PRIV1            GPIO_PRIVCFGR_PRIV1_Msk
+#define GPIO_PRIVCFGR_PRIV2_Pos        (2U)
+#define GPIO_PRIVCFGR_PRIV2_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV2_Pos)      /*!< 0x00000004 */
+#define GPIO_PRIVCFGR_PRIV2            GPIO_PRIVCFGR_PRIV2_Msk
+#define GPIO_PRIVCFGR_PRIV3_Pos        (3U)
+#define GPIO_PRIVCFGR_PRIV3_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV3_Pos)      /*!< 0x00000008 */
+#define GPIO_PRIVCFGR_PRIV3            GPIO_PRIVCFGR_PRIV3_Msk
+#define GPIO_PRIVCFGR_PRIV4_Pos        (4U)
+#define GPIO_PRIVCFGR_PRIV4_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV4_Pos)      /*!< 0x00000010 */
+#define GPIO_PRIVCFGR_PRIV4            GPIO_PRIVCFGR_PRIV4_Msk
+#define GPIO_PRIVCFGR_PRIV5_Pos        (5U)
+#define GPIO_PRIVCFGR_PRIV5_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV5_Pos)      /*!< 0x00000020 */
+#define GPIO_PRIVCFGR_PRIV5            GPIO_PRIVCFGR_PRIV5_Msk
+#define GPIO_PRIVCFGR_PRIV6_Pos        (6U)
+#define GPIO_PRIVCFGR_PRIV6_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV6_Pos)      /*!< 0x00000040 */
+#define GPIO_PRIVCFGR_PRIV6            GPIO_PRIVCFGR_PRIV6_Msk
+#define GPIO_PRIVCFGR_PRIV7_Pos        (7U)
+#define GPIO_PRIVCFGR_PRIV7_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV7_Pos)      /*!< 0x00000080 */
+#define GPIO_PRIVCFGR_PRIV7            GPIO_PRIVCFGR_PRIV7_Msk
+#define GPIO_PRIVCFGR_PRIV8_Pos        (8U)
+#define GPIO_PRIVCFGR_PRIV8_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV8_Pos)      /*!< 0x00000100 */
+#define GPIO_PRIVCFGR_PRIV8            GPIO_PRIVCFGR_PRIV8_Msk
+#define GPIO_PRIVCFGR_PRIV9_Pos        (9U)
+#define GPIO_PRIVCFGR_PRIV9_Msk        (0x1UL << GPIO_PRIVCFGR_PRIV9_Pos)      /*!< 0x00000200 */
+#define GPIO_PRIVCFGR_PRIV9            GPIO_PRIVCFGR_PRIV9_Msk
+#define GPIO_PRIVCFGR_PRIV10_Pos       (10U)
+#define GPIO_PRIVCFGR_PRIV10_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV10_Pos)     /*!< 0x00000400 */
+#define GPIO_PRIVCFGR_PRIV10           GPIO_PRIVCFGR_PRIV10_Msk
+#define GPIO_PRIVCFGR_PRIV11_Pos       (11U)
+#define GPIO_PRIVCFGR_PRIV11_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV11_Pos)     /*!< 0x00000800 */
+#define GPIO_PRIVCFGR_PRIV11           GPIO_PRIVCFGR_PRIV11_Msk
+#define GPIO_PRIVCFGR_PRIV12_Pos       (12U)
+#define GPIO_PRIVCFGR_PRIV12_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV12_Pos)     /*!< 0x00001000 */
+#define GPIO_PRIVCFGR_PRIV12           GPIO_PRIVCFGR_PRIV12_Msk
+#define GPIO_PRIVCFGR_PRIV13_Pos       (13U)
+#define GPIO_PRIVCFGR_PRIV13_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV13_Pos)     /*!< 0x00002000 */
+#define GPIO_PRIVCFGR_PRIV13           GPIO_PRIVCFGR_PRIV13_Msk
+#define GPIO_PRIVCFGR_PRIV14_Pos       (14U)
+#define GPIO_PRIVCFGR_PRIV14_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV14_Pos)     /*!< 0x00004000 */
+#define GPIO_PRIVCFGR_PRIV14           GPIO_PRIVCFGR_PRIV14_Msk
+#define GPIO_PRIVCFGR_PRIV15_Pos       (15U)
+#define GPIO_PRIVCFGR_PRIV15_Msk       (0x1UL << GPIO_PRIVCFGR_PRIV15_Pos)     /*!< 0x00008000 */
+#define GPIO_PRIVCFGR_PRIV15           GPIO_PRIVCFGR_PRIV15_Msk
+
+/******************  Bits definition for GPIO_RCFGLOCKR register  ******************/
+#define GPIO_RCFGLOCKR_RLOCK0_Pos      (0U)
+#define GPIO_RCFGLOCKR_RLOCK0_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK0_Pos)    /*!< 0x00000001 */
+#define GPIO_RCFGLOCKR_RLOCK0          GPIO_RCFGLOCKR_RLOCK0_Msk
+#define GPIO_RCFGLOCKR_RLOCK1_Pos      (1U)
+#define GPIO_RCFGLOCKR_RLOCK1_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK1_Pos)    /*!< 0x00000002 */
+#define GPIO_RCFGLOCKR_RLOCK1          GPIO_RCFGLOCKR_RLOCK1_Msk
+#define GPIO_RCFGLOCKR_RLOCK2_Pos      (2U)
+#define GPIO_RCFGLOCKR_RLOCK2_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK2_Pos)    /*!< 0x00000004 */
+#define GPIO_RCFGLOCKR_RLOCK2          GPIO_RCFGLOCKR_RLOCK2_Msk
+#define GPIO_RCFGLOCKR_RLOCK3_Pos      (3U)
+#define GPIO_RCFGLOCKR_RLOCK3_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK3_Pos)    /*!< 0x00000008 */
+#define GPIO_RCFGLOCKR_RLOCK3          GPIO_RCFGLOCKR_RLOCK3_Msk
+#define GPIO_RCFGLOCKR_RLOCK4_Pos      (4U)
+#define GPIO_RCFGLOCKR_RLOCK4_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK4_Pos)    /*!< 0x00000010 */
+#define GPIO_RCFGLOCKR_RLOCK4          GPIO_RCFGLOCKR_RLOCK4_Msk
+#define GPIO_RCFGLOCKR_RLOCK5_Pos      (5U)
+#define GPIO_RCFGLOCKR_RLOCK5_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK5_Pos)    /*!< 0x00000020 */
+#define GPIO_RCFGLOCKR_RLOCK5          GPIO_RCFGLOCKR_RLOCK5_Msk
+#define GPIO_RCFGLOCKR_RLOCK6_Pos      (6U)
+#define GPIO_RCFGLOCKR_RLOCK6_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK6_Pos)    /*!< 0x00000040 */
+#define GPIO_RCFGLOCKR_RLOCK6          GPIO_RCFGLOCKR_RLOCK6_Msk
+#define GPIO_RCFGLOCKR_RLOCK7_Pos      (7U)
+#define GPIO_RCFGLOCKR_RLOCK7_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK7_Pos)    /*!< 0x00000080 */
+#define GPIO_RCFGLOCKR_RLOCK7          GPIO_RCFGLOCKR_RLOCK7_Msk
+#define GPIO_RCFGLOCKR_RLOCK8_Pos      (8U)
+#define GPIO_RCFGLOCKR_RLOCK8_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK8_Pos)    /*!< 0x00000100 */
+#define GPIO_RCFGLOCKR_RLOCK8          GPIO_RCFGLOCKR_RLOCK8_Msk
+#define GPIO_RCFGLOCKR_RLOCK9_Pos      (9U)
+#define GPIO_RCFGLOCKR_RLOCK9_Msk      (0x1UL << GPIO_RCFGLOCKR_RLOCK9_Pos)    /*!< 0x00000200 */
+#define GPIO_RCFGLOCKR_RLOCK9          GPIO_RCFGLOCKR_RLOCK9_Msk
+#define GPIO_RCFGLOCKR_RLOCK10_Pos     (10U)
+#define GPIO_RCFGLOCKR_RLOCK10_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK10_Pos)   /*!< 0x00000400 */
+#define GPIO_RCFGLOCKR_RLOCK10         GPIO_RCFGLOCKR_RLOCK10_Msk
+#define GPIO_RCFGLOCKR_RLOCK11_Pos     (11U)
+#define GPIO_RCFGLOCKR_RLOCK11_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK11_Pos)   /*!< 0x00000800 */
+#define GPIO_RCFGLOCKR_RLOCK11         GPIO_RCFGLOCKR_RLOCK11_Msk
+#define GPIO_RCFGLOCKR_RLOCK12_Pos     (12U)
+#define GPIO_RCFGLOCKR_RLOCK12_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK12_Pos)   /*!< 0x00001000 */
+#define GPIO_RCFGLOCKR_RLOCK12         GPIO_RCFGLOCKR_RLOCK12_Msk
+#define GPIO_RCFGLOCKR_RLOCK13_Pos     (13U)
+#define GPIO_RCFGLOCKR_RLOCK13_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK13_Pos)   /*!< 0x00002000 */
+#define GPIO_RCFGLOCKR_RLOCK13         GPIO_RCFGLOCKR_RLOCK13_Msk
+#define GPIO_RCFGLOCKR_RLOCK14_Pos     (14U)
+#define GPIO_RCFGLOCKR_RLOCK14_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK14_Pos)   /*!< 0x00004000 */
+#define GPIO_RCFGLOCKR_RLOCK14         GPIO_RCFGLOCKR_RLOCK14_Msk
+#define GPIO_RCFGLOCKR_RLOCK15_Pos     (15U)
+#define GPIO_RCFGLOCKR_RLOCK15_Msk     (0x1UL << GPIO_RCFGLOCKR_RLOCK15_Pos)   /*!< 0x00008000 */
+#define GPIO_RCFGLOCKR_RLOCK15         GPIO_RCFGLOCKR_RLOCK15_Msk
+
+/****************** Bit definition for GPIO_DELAYRL register *********************/
+#define GPIO_DELAYRL_DLY0_Pos        (0U)
+#define GPIO_DELAYRL_DLY0_Msk        (0xFUL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRL_DLY0            GPIO_DELAYRL_DLY0_Msk
+#define GPIO_DELAYRL_DLY0_0          (0x1UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRL_DLY0_1          (0x2UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRL_DLY0_2          (0x4UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRL_DLY0_3          (0x8UL << GPIO_DELAYRL_DLY0_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRL_DLY1_Pos        (4U)
+#define GPIO_DELAYRL_DLY1_Msk        (0xFUL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRL_DLY1            GPIO_DELAYRL_DLY1_Msk
+#define GPIO_DELAYRL_DLY1_0          (0x1UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRL_DLY1_1          (0x2UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRL_DLY1_2          (0x4UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRL_DLY1_3          (0x8UL << GPIO_DELAYRL_DLY1_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRL_DLY2_Pos        (8U)
+#define GPIO_DELAYRL_DLY2_Msk        (0xFUL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000F00 */
+#define GPIO_DELAYRL_DLY2            GPIO_DELAYRL_DLY2_Msk
+#define GPIO_DELAYRL_DLY2_0          (0x1UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000100 */
+#define GPIO_DELAYRL_DLY2_1          (0x2UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000200 */
+#define GPIO_DELAYRL_DLY2_2          (0x4UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000400 */
+#define GPIO_DELAYRL_DLY2_3          (0x8UL << GPIO_DELAYRL_DLY2_Pos)          /*!< 0x00000800 */
+#define GPIO_DELAYRL_DLY3_Pos        (12U)
+#define GPIO_DELAYRL_DLY3_Msk        (0xFUL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x0000F000 */
+#define GPIO_DELAYRL_DLY3            GPIO_DELAYRL_DLY3_Msk
+#define GPIO_DELAYRL_DLY3_0          (0x1UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00001000 */
+#define GPIO_DELAYRL_DLY3_1          (0x2UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00002000 */
+#define GPIO_DELAYRL_DLY3_2          (0x4UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00004000 */
+#define GPIO_DELAYRL_DLY3_3          (0x8UL << GPIO_DELAYRL_DLY3_Pos)          /*!< 0x00008000 */
+#define GPIO_DELAYRL_DLY4_Pos        (16U)
+#define GPIO_DELAYRL_DLY4_Msk        (0xFUL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x000F0000 */
+#define GPIO_DELAYRL_DLY4            GPIO_DELAYRL_DLY4_Msk
+#define GPIO_DELAYRL_DLY4_0          (0x1UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00010000 */
+#define GPIO_DELAYRL_DLY4_1          (0x2UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00020000 */
+#define GPIO_DELAYRL_DLY4_2          (0x4UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00040000 */
+#define GPIO_DELAYRL_DLY4_3          (0x8UL << GPIO_DELAYRL_DLY4_Pos)          /*!< 0x00080000 */
+#define GPIO_DELAYRL_DLY5_Pos        (20U)
+#define GPIO_DELAYRL_DLY5_Msk        (0xFUL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00F00000 */
+#define GPIO_DELAYRL_DLY5            GPIO_DELAYRL_DLY5_Msk
+#define GPIO_DELAYRL_DLY5_0          (0x1UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00100000 */
+#define GPIO_DELAYRL_DLY5_1          (0x2UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00200000 */
+#define GPIO_DELAYRL_DLY5_2          (0x4UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00400000 */
+#define GPIO_DELAYRL_DLY5_3          (0x8UL << GPIO_DELAYRL_DLY5_Pos)          /*!< 0x00800000 */
+#define GPIO_DELAYRL_DLY6_Pos        (24U)
+#define GPIO_DELAYRL_DLY6_Msk        (0xFUL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x0F000000 */
+#define GPIO_DELAYRL_DLY6            GPIO_DELAYRL_DLY6_Msk
+#define GPIO_DELAYRL_DLY6_0          (0x1UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x01000000 */
+#define GPIO_DELAYRL_DLY6_1          (0x2UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x02000000 */
+#define GPIO_DELAYRL_DLY6_2          (0x4UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x04000000 */
+#define GPIO_DELAYRL_DLY6_3          (0x8UL << GPIO_DELAYRL_DLY6_Pos)          /*!< 0x08000000 */
+#define GPIO_DELAYRL_DLY7_Pos        (28U)
+#define GPIO_DELAYRL_DLY7_Msk        (0xFUL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0xF0000000 */
+#define GPIO_DELAYRL_DLY7            GPIO_DELAYRL_DLY7_Msk
+#define GPIO_DELAYRL_DLY7_0          (0x1UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x10000000 */
+#define GPIO_DELAYRL_DLY7_1          (0x2UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x20000000 */
+#define GPIO_DELAYRL_DLY7_2          (0x4UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x40000000 */
+#define GPIO_DELAYRL_DLY7_3          (0x8UL << GPIO_DELAYRL_DLY7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_DELAYRH register *********************/
+#define GPIO_DELAYRH_DLY8_Pos        (0U)
+#define GPIO_DELAYRH_DLY8_Msk        (0xFUL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x0000000F */
+#define GPIO_DELAYRH_DLY8            GPIO_DELAYRH_DLY8_Msk
+#define GPIO_DELAYRH_DLY8_0          (0x1UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000001 */
+#define GPIO_DELAYRH_DLY8_1          (0x2UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000002 */
+#define GPIO_DELAYRH_DLY8_2          (0x4UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000004 */
+#define GPIO_DELAYRH_DLY8_3          (0x8UL << GPIO_DELAYRH_DLY8_Pos)          /*!< 0x00000008 */
+#define GPIO_DELAYRH_DLY9_Pos        (4U)
+#define GPIO_DELAYRH_DLY9_Msk        (0xFUL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x000000F0 */
+#define GPIO_DELAYRH_DLY9            GPIO_DELAYRH_DLY9_Msk
+#define GPIO_DELAYRH_DLY9_0          (0x1UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000010 */
+#define GPIO_DELAYRH_DLY9_1          (0x2UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000020 */
+#define GPIO_DELAYRH_DLY9_2          (0x4UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000040 */
+#define GPIO_DELAYRH_DLY9_3          (0x8UL << GPIO_DELAYRH_DLY9_Pos)          /*!< 0x00000080 */
+#define GPIO_DELAYRH_DLY10_Pos       (8U)
+#define GPIO_DELAYRH_DLY10_Msk       (0xFUL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000F00 */
+#define GPIO_DELAYRH_DLY10           GPIO_DELAYRH_DLY10_Msk
+#define GPIO_DELAYRH_DLY10_0         (0x1UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000100 */
+#define GPIO_DELAYRH_DLY10_1         (0x2UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000200 */
+#define GPIO_DELAYRH_DLY10_2         (0x4UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000400 */
+#define GPIO_DELAYRH_DLY10_3         (0x8UL << GPIO_DELAYRH_DLY10_Pos)         /*!< 0x00000800 */
+#define GPIO_DELAYRH_DLY11_Pos       (12U)
+#define GPIO_DELAYRH_DLY11_Msk       (0xFUL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x0000F000 */
+#define GPIO_DELAYRH_DLY11           GPIO_DELAYRH_DLY11_Msk
+#define GPIO_DELAYRH_DLY11_0         (0x1UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00001000 */
+#define GPIO_DELAYRH_DLY11_1         (0x2UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00002000 */
+#define GPIO_DELAYRH_DLY11_2         (0x4UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00004000 */
+#define GPIO_DELAYRH_DLY11_3         (0x8UL << GPIO_DELAYRH_DLY11_Pos)         /*!< 0x00008000 */
+#define GPIO_DELAYRH_DLY12_Pos       (16U)
+#define GPIO_DELAYRH_DLY12_Msk       (0xFUL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x000F0000 */
+#define GPIO_DELAYRH_DLY12           GPIO_DELAYRH_DLY12_Msk
+#define GPIO_DELAYRH_DLY12_0         (0x1UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00010000 */
+#define GPIO_DELAYRH_DLY12_1         (0x2UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00020000 */
+#define GPIO_DELAYRH_DLY12_2         (0x4UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00040000 */
+#define GPIO_DELAYRH_DLY12_3         (0x8UL << GPIO_DELAYRH_DLY12_Pos)         /*!< 0x00080000 */
+#define GPIO_DELAYRH_DLY13_Pos       (20U)
+#define GPIO_DELAYRH_DLY13_Msk       (0xFUL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00F00000 */
+#define GPIO_DELAYRH_DLY13           GPIO_DELAYRH_DLY13_Msk
+#define GPIO_DELAYRH_DLY13_0         (0x1UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00100000 */
+#define GPIO_DELAYRH_DLY13_1         (0x2UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00200000 */
+#define GPIO_DELAYRH_DLY13_2         (0x4UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00400000 */
+#define GPIO_DELAYRH_DLY13_3         (0x8UL << GPIO_DELAYRH_DLY13_Pos)         /*!< 0x00800000 */
+#define GPIO_DELAYRH_DLY14_Pos       (24U)
+#define GPIO_DELAYRH_DLY14_Msk       (0xFUL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x0F000000 */
+#define GPIO_DELAYRH_DLY14           GPIO_DELAYRH_DLY14_Msk
+#define GPIO_DELAYRH_DLY14_0         (0x1UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x01000000 */
+#define GPIO_DELAYRH_DLY14_1         (0x2UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x02000000 */
+#define GPIO_DELAYRH_DLY14_2         (0x4UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x04000000 */
+#define GPIO_DELAYRH_DLY14_3         (0x8UL << GPIO_DELAYRH_DLY14_Pos)         /*!< 0x08000000 */
+#define GPIO_DELAYRH_DLY15_Pos       (28U)
+#define GPIO_DELAYRH_DLY15_Msk       (0xFUL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0xF0000000 */
+#define GPIO_DELAYRH_DLY15           GPIO_DELAYRH_DLY15_Msk
+#define GPIO_DELAYRH_DLY15_0         (0x1UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x10000000 */
+#define GPIO_DELAYRH_DLY15_1         (0x2UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x20000000 */
+#define GPIO_DELAYRH_DLY15_2         (0x4UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x40000000 */
+#define GPIO_DELAYRH_DLY15_3         (0x8UL << GPIO_DELAYRH_DLY15_Pos)         /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRL register *********************/
+#define GPIO_ADVCFGRL_0_Pos            (0U)
+#define GPIO_ADVCFGRL_0_Msk            (0xFUL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRL_0                GPIO_ADVCFGRL_0_Msk
+#define GPIO_ADVCFGRL_DLYPATH0         (0x1UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRL_DE0              (0x2UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRL_INVCLK0          (0x4UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRL_RET0             (0x8UL << GPIO_ADVCFGRL_0_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRL_1_Pos            (4U)
+#define GPIO_ADVCFGRL_1_Msk            (0xFUL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRL_1                GPIO_ADVCFGRL_1_Msk
+#define GPIO_ADVCFGRL_DLYPATH1         (0x1UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRL_DE1              (0x2UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRL_INVCLK1          (0x4UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRL_RET1             (0x8UL << GPIO_ADVCFGRL_1_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRL_2_Pos            (8U)
+#define GPIO_ADVCFGRL_2_Msk            (0xFUL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000F00 */
+#define GPIO_ADVCFGRL_2                GPIO_ADVCFGRL_2_Msk
+#define GPIO_ADVCFGRL_DLYPATH2         (0x1UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000100 */
+#define GPIO_ADVCFGRL_DE2              (0x2UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000200 */
+#define GPIO_ADVCFGRL_INVCLK2          (0x4UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000400 */
+#define GPIO_ADVCFGRL_RET2             (0x8UL << GPIO_ADVCFGRL_2_Pos)          /*!< 0x00000800 */
+#define GPIO_ADVCFGRL_3_Pos            (12U)
+#define GPIO_ADVCFGRL_3_Msk            (0xFUL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x0000F000 */
+#define GPIO_ADVCFGRL_3                GPIO_ADVCFGRL_3_Msk
+#define GPIO_ADVCFGRL_DLYPATH3         (0x1UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00001000 */
+#define GPIO_ADVCFGRL_DE3              (0x2UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00002000 */
+#define GPIO_ADVCFGRL_INVCLK3          (0x4UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00004000 */
+#define GPIO_ADVCFGRL_RET3             (0x8UL << GPIO_ADVCFGRL_3_Pos)          /*!< 0x00008000 */
+#define GPIO_ADVCFGRL_4_Pos            (16U)
+#define GPIO_ADVCFGRL_4_Msk            (0xFUL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x000F0000 */
+#define GPIO_ADVCFGRL_4                GPIO_ADVCFGRL_4_Msk
+#define GPIO_ADVCFGRL_DLYPATH4         (0x1UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00010000 */
+#define GPIO_ADVCFGRL_DE4              (0x2UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00020000 */
+#define GPIO_ADVCFGRL_INVCLK4          (0x4UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00040000 */
+#define GPIO_ADVCFGRL_RET4             (0x8UL << GPIO_ADVCFGRL_4_Pos)          /*!< 0x00080000 */
+#define GPIO_ADVCFGRL_5_Pos            (20U)
+#define GPIO_ADVCFGRL_5_Msk            (0xFUL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00F00000 */
+#define GPIO_ADVCFGRL_5                GPIO_ADVCFGRL_5_Msk
+#define GPIO_ADVCFGRL_DLYPATH5         (0x1UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00100000 */
+#define GPIO_ADVCFGRL_DE5              (0x2UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00200000 */
+#define GPIO_ADVCFGRL_INVCLK5          (0x4UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00400000 */
+#define GPIO_ADVCFGRL_RET5             (0x8UL << GPIO_ADVCFGRL_5_Pos)          /*!< 0x00800000 */
+#define GPIO_ADVCFGRL_6_Pos            (24U)
+#define GPIO_ADVCFGRL_6_Msk            (0xFUL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x0F000000 */
+#define GPIO_ADVCFGRL_6                GPIO_ADVCFGRL_6_Msk
+#define GPIO_ADVCFGRL_DLYPATH6         (0x1UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x01000000 */
+#define GPIO_ADVCFGRL_DE6              (0x2UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x02000000 */
+#define GPIO_ADVCFGRL_INVCLK6          (0x4UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x04000000 */
+#define GPIO_ADVCFGRL_RET6             (0x8UL << GPIO_ADVCFGRL_6_Pos)          /*!< 0x08000000 */
+#define GPIO_ADVCFGRL_7_Pos            (28U)
+#define GPIO_ADVCFGRL_7_Msk            (0xFUL << GPIO_ADVCFGRL_7_Pos)          /*!< 0xF0000000 */
+#define GPIO_ADVCFGRL_7                GPIO_ADVCFGRL_7_Msk
+#define GPIO_ADVCFGRL_DLYPATH7         (0x1UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x10000000 */
+#define GPIO_ADVCFGRL_DE7              (0x2UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x20000000 */
+#define GPIO_ADVCFGRL_INVCLK7          (0x4UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x40000000 */
+#define GPIO_ADVCFGRL_RET7             (0x8UL << GPIO_ADVCFGRL_7_Pos)          /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_ADVCFGRH register *********************/
+#define GPIO_ADVCFGRH_8_Pos            (0U)
+#define GPIO_ADVCFGRH_8_Msk            (0xFUL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x0000000F */
+#define GPIO_ADVCFGRH_8                GPIO_ADVCFGRH_8_Msk
+#define GPIO_ADVCFGRH_DLYPATH8         (0x1UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000001 */
+#define GPIO_ADVCFGRH_DE8              (0x2UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000002 */
+#define GPIO_ADVCFGRH_INVCLK8          (0x4UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000004 */
+#define GPIO_ADVCFGRH_RET8             (0x8UL << GPIO_ADVCFGRH_8_Pos)          /*!< 0x00000008 */
+#define GPIO_ADVCFGRH_9_Pos            (4U)
+#define GPIO_ADVCFGRH_9_Msk            (0xFUL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x000000F0 */
+#define GPIO_ADVCFGRH_9                GPIO_ADVCFGRH_9_Msk
+#define GPIO_ADVCFGRH_DLYPATH9         (0x1UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000010 */
+#define GPIO_ADVCFGRH_DE9              (0x2UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000020 */
+#define GPIO_ADVCFGRH_INVCLK9          (0x4UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000040 */
+#define GPIO_ADVCFGRH_RET9             (0x8UL << GPIO_ADVCFGRH_9_Pos)          /*!< 0x00000080 */
+#define GPIO_ADVCFGRH_10_Pos           (8U)
+#define GPIO_ADVCFGRH_10_Msk           (0xFUL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000F00 */
+#define GPIO_ADVCFGRH_10               GPIO_ADVCFGRH_10_Msk
+#define GPIO_ADVCFGRH_DLYPATH10        (0x1UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000100 */
+#define GPIO_ADVCFGRH_DE10             (0x2UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000200 */
+#define GPIO_ADVCFGRH_INVCLK10         (0x4UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000400 */
+#define GPIO_ADVCFGRH_RET10            (0x8UL << GPIO_ADVCFGRH_10_Pos)         /*!< 0x00000800 */
+#define GPIO_ADVCFGRH_11_Pos           (12U)
+#define GPIO_ADVCFGRH_11_Msk           (0xFUL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x0000F000 */
+#define GPIO_ADVCFGRH_11               GPIO_ADVCFGRH_11_Msk
+#define GPIO_ADVCFGRH_DLYPATH11        (0x1UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00001000 */
+#define GPIO_ADVCFGRH_DE11             (0x2UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00002000 */
+#define GPIO_ADVCFGRH_INVCLK11         (0x4UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00004000 */
+#define GPIO_ADVCFGRH_RET11            (0x8UL << GPIO_ADVCFGRH_11_Pos)         /*!< 0x00008000 */
+#define GPIO_ADVCFGRH_12_Pos           (16U)
+#define GPIO_ADVCFGRH_12_Msk           (0xFUL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x000F0000 */
+#define GPIO_ADVCFGRH_12               GPIO_ADVCFGRH_12_Msk
+#define GPIO_ADVCFGRH_DLYPATH12        (0x1UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00010000 */
+#define GPIO_ADVCFGRH_DE12             (0x2UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00020000 */
+#define GPIO_ADVCFGRH_INVCLK12         (0x4UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00040000 */
+#define GPIO_ADVCFGRH_RET12            (0x8UL << GPIO_ADVCFGRH_12_Pos)         /*!< 0x00080000 */
+#define GPIO_ADVCFGRH_13_Pos           (20U)
+#define GPIO_ADVCFGRH_13_Msk           (0xFUL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00F00000 */
+#define GPIO_ADVCFGRH_13               GPIO_ADVCFGRH_13_Msk
+#define GPIO_ADVCFGRH_DLYPATH13        (0x1UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00100000 */
+#define GPIO_ADVCFGRH_DE13             (0x2UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00200000 */
+#define GPIO_ADVCFGRH_INVCLK13         (0x4UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00400000 */
+#define GPIO_ADVCFGRH_RET13            (0x8UL << GPIO_ADVCFGRH_13_Pos)         /*!< 0x00800000 */
+#define GPIO_ADVCFGRH_14_Pos           (24U)
+#define GPIO_ADVCFGRH_14_Msk           (0xFUL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x0F000000 */
+#define GPIO_ADVCFGRH_14               GPIO_ADVCFGRH_14_Msk
+#define GPIO_ADVCFGRH_DLYPATH14        (0x1UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x01000000 */
+#define GPIO_ADVCFGRH_DE14             (0x2UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x02000000 */
+#define GPIO_ADVCFGRH_INVCLK14         (0x4UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x04000000 */
+#define GPIO_ADVCFGRH_RET14            (0x8UL << GPIO_ADVCFGRH_14_Pos)         /*!< 0x08000000 */
+#define GPIO_ADVCFGRH_15_Pos           (28U)
+#define GPIO_ADVCFGRH_15_Msk           (0xFUL << GPIO_ADVCFGRH_15_Pos)         /*!< 0xF0000000 */
+#define GPIO_ADVCFGRH_15               GPIO_ADVCFGRH_15_Msk
+#define GPIO_ADVCFGRH_DLYPATH15        (0x1UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x10000000 */
+#define GPIO_ADVCFGRH_DE15             (0x2UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x20000000 */
+#define GPIO_ADVCFGRH_INVCLK15         (0x4UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x40000000 */
+#define GPIO_ADVCFGRH_RET15            (0x8UL << GPIO_ADVCFGRH_15_Pos)         /*!< 0x80000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT_Pos                    (2U)
+#define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
+#define HASH_CR_INIT                        HASH_CR_INIT_Msk
+#define HASH_CR_DMAE_Pos                    (3U)
+#define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
+#define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
+#define HASH_CR_DATATYPE_Pos                (4U)
+#define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
+#define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
+#define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos                    (6U)
+#define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
+#define HASH_CR_MODE                        HASH_CR_MODE_Msk
+#define HASH_CR_NBW_Pos                     (8U)
+#define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
+#define HASH_CR_NBW                         HASH_CR_NBW_Msk
+#define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
+#define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
+#define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
+#define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos                   (12U)
+#define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
+#define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
+#define HASH_CR_MDMAT_Pos                   (13U)
+#define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
+#define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
+#define HASH_CR_LKEY_Pos                    (16U)
+#define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
+#define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
+#define HASH_CR_ALGO_Pos                    (17U)
+#define HASH_CR_ALGO_Msk                    (0xFUL << HASH_CR_ALGO_Pos)             /*!< 0x001E0000 */
+#define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
+#define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
+#define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
+#define HASH_CR_ALGO_2                      (0x4UL << HASH_CR_ALGO_Pos)             /*!< 0x00080000 */
+#define HASH_CR_ALGO_3                      (0x8UL << HASH_CR_ALGO_Pos)             /*!< 0x00100000 */
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBLW_Pos                   (0U)
+#define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
+#define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
+#define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
+#define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
+#define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
+#define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
+#define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos                   (8U)
+#define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
+#define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIE_Pos                  (0U)
+#define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
+#define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
+#define HASH_IMR_DCIE_Pos                   (1U)
+#define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
+#define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS_Pos                   (0U)
+#define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
+#define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
+#define HASH_SR_DCIS_Pos                    (1U)
+#define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
+#define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
+#define HASH_SR_DMAS_Pos                    (2U)
+#define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
+#define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
+#define HASH_SR_BUSY_Pos                    (3U)
+#define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
+#define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
+#define HASH_SR_NBWE_Pos                    (16U)
+#define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
+#define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
+#define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
+#define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
+#define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
+#define HASH_SR_DINNE_Pos                   (15U)
+#define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
+#define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
+#define HASH_SR_NBWP_Pos                    (9U)
+#define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
+#define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
+#define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
+#define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
+#define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
+#define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos                      (0U)
+#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
+#define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos                    (1U)
+#define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
+#define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos                    (2U)
+#define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
+#define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos                  (3U)
+#define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos                  (4U)
+#define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
+#define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos                  (5U)
+#define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
+#define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos                    (6U)
+#define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos                   (7U)
+#define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos                     (8U)
+#define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
+#define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos                  (12U)
+#define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos                   (13U)
+#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
+#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos                 (14U)
+#define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos                 (15U)
+#define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos                     (16U)
+#define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
+#define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos               (17U)
+#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos                   (18U)
+#define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos                    (19U)
+#define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
+#define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos                  (20U)
+#define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos                  (21U)
+#define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos                 (22U)
+#define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos                   (23U)
+#define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
+#define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
+#define I2C_CR1_FMP_Pos                     (24U)
+#define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
+#define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
+#define I2C_CR1_ADDRACLR_Pos                (30U)
+#define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
+#define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
+#define I2C_CR1_STOPFACLR_Pos               (31U)
+#define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
+#define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos                    (0U)
+#define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
+#define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos                  (10U)
+#define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos                   (11U)
+#define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
+#define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos                 (12U)
+#define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos                   (13U)
+#define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
+#define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
+#define I2C_CR2_STOP_Pos                    (14U)
+#define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
+#define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos                    (15U)
+#define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
+#define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos                  (16U)
+#define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos                  (24U)
+#define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
+#define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos                 (25U)
+#define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos                 (26U)
+#define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos                    (0U)
+#define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
+#define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos                (10U)
+#define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos                  (15U)
+#define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos                    (1U)
+#define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
+#define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos                 (8U)
+#define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos              (8U)
+#define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos              (9U)
+#define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos              (8U)
+#define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos              (10U)
+#define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos              (8U)
+#define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos              (9U)
+#define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos              (8U)
+#define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos                  (15U)
+#define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos                (0U)
+#define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos                (8U)
+#define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos              (16U)
+#define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos              (20U)
+#define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos               (28U)
+#define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos              (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos                     (0U)
+#define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
+#define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos                    (1U)
+#define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
+#define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos                    (2U)
+#define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
+#define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos                    (3U)
+#define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
+#define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos                   (4U)
+#define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
+#define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos                   (5U)
+#define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
+#define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos                      (6U)
+#define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
+#define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos                     (7U)
+#define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
+#define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos                    (8U)
+#define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
+#define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
+#define I2C_ISR_ARLO_Pos                    (9U)
+#define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
+#define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos                     (10U)
+#define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
+#define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos                  (11U)
+#define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
+#define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos                 (12U)
+#define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos                   (13U)
+#define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
+#define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos                    (15U)
+#define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
+#define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
+#define I2C_ISR_DIR_Pos                     (16U)
+#define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
+#define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos                 (17U)
+#define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos                  (3U)
+#define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos                  (4U)
+#define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
+#define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos                  (5U)
+#define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
+#define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos                  (8U)
+#define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
+#define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos                  (9U)
+#define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos                   (10U)
+#define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos                   (11U)
+#define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
+#define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos                (12U)
+#define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos                 (13U)
+#define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos                    (0U)
+#define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
+#define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos                 (0U)
+#define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos                 (0U)
+#define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Improved Inter-integrated Circuit Interface (I3C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I3C_CR register  *********************/
+#define I3C_CR_DCNT_Pos                     (0U)
+#define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
+#define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
+#define I3C_CR_RNW_Pos                      (16U)
+#define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
+#define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
+#define I3C_CR_CCC_Pos                      (16U)
+#define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
+#define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
+#define I3C_CR_ADD_Pos                      (17U)
+#define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
+#define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
+#define I3C_CR_MTYPE_Pos                    (27U)
+#define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
+#define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
+#define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
+#define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
+#define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
+#define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
+#define I3C_CR_MEND_Pos                     (31U)
+#define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
+#define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
+
+/*******************  Bit definition for I3C_CFGR register  *******************/
+#define I3C_CFGR_EN_Pos                     (0U)
+#define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
+#define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
+#define I3C_CFGR_CRINIT_Pos                 (1U)
+#define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
+#define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
+#define I3C_CFGR_NOARBH_Pos                 (2U)
+#define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
+#define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
+#define I3C_CFGR_RSTPTRN_Pos                (3U)
+#define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
+#define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
+#define I3C_CFGR_EXITPTRN_Pos               (4U)
+#define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
+#define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
+#define I3C_CFGR_HKSDAEN_Pos                (5U)
+#define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
+#define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
+#define I3C_CFGR_HJACK_Pos                  (7U)
+#define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
+#define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
+#define I3C_CFGR_RXDMAEN_Pos                (8U)
+#define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
+#define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
+#define I3C_CFGR_RXFLUSH_Pos                (9U)
+#define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
+#define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
+#define I3C_CFGR_RXTHRES_Pos                (10U)
+#define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
+#define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
+#define I3C_CFGR_TXDMAEN_Pos                (12U)
+#define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
+#define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
+#define I3C_CFGR_TXFLUSH_Pos                (13U)
+#define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
+#define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
+#define I3C_CFGR_TXTHRES_Pos                (14U)
+#define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
+#define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
+#define I3C_CFGR_SDMAEN_Pos                 (16U)
+#define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
+#define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
+#define I3C_CFGR_SFLUSH_Pos                 (17U)
+#define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
+#define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
+#define I3C_CFGR_SMODE_Pos                  (18U)
+#define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
+#define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
+#define I3C_CFGR_TMODE_Pos                  (19U)
+#define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
+#define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
+#define I3C_CFGR_CDMAEN_Pos                 (20U)
+#define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
+#define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
+#define I3C_CFGR_CFLUSH_Pos                 (21U)
+#define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
+#define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
+#define I3C_CFGR_TSFSET_Pos                 (30U)
+#define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
+#define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
+
+/*******************  Bit definition for I3C_RDR register  ********************/
+#define I3C_RDR_RDB0_Pos                    (0U)
+#define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
+#define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
+
+/******************  Bit definition for I3C_RDWR register  ********************/
+#define I3C_RDWR_RDBx_Pos                   (0U)
+#define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
+#define I3C_RDWR_RDB0_Pos                   (0U)
+#define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
+#define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
+#define I3C_RDWR_RDB1_Pos                   (8U)
+#define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
+#define I3C_RDWR_RDB2_Pos                   (16U)
+#define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
+#define I3C_RDWR_RDB3_Pos                   (24U)
+#define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
+
+/*******************  Bit definition for I3C_TDR register  ********************/
+#define I3C_TDR_TDB0_Pos                    (0U)
+#define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
+#define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
+
+/******************  Bit definition for I3C_TDWR register  ********************/
+#define I3C_TDWR_TDBx_Pos                   (0U)
+#define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
+#define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
+#define I3C_TDWR_TDB0_Pos                   (0U)
+#define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
+#define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
+#define I3C_TDWR_TDB1_Pos                   (8U)
+#define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
+#define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
+#define I3C_TDWR_TDB2_Pos                   (16U)
+#define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
+#define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
+#define I3C_TDWR_TDB3_Pos                   (24U)
+#define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
+#define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
+
+/*******************  Bit definition for I3C_IBIDR register  ******************/
+#define I3C_IBIDR_IBIDBx_Pos                (0U)
+#define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
+#define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
+#define I3C_IBIDR_IBIDB0_Pos                (0U)
+#define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
+#define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
+#define I3C_IBIDR_IBIDB1_Pos                (8U)
+#define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
+#define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
+#define I3C_IBIDR_IBIDB2_Pos                (16U)
+#define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
+#define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
+#define I3C_IBIDR_IBIDB3_Pos                (24U)
+#define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
+#define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
+
+/******************  Bit definition for I3C_TGTTDR register  ******************/
+#define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
+#define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
+#define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
+#define I3C_TGTTDR_PRELOAD_Pos              (16U)
+#define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
+#define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
+
+/*******************  Bit definition for I3C_SR register  *********************/
+#define I3C_SR_XDCNT_Pos                    (0U)
+#define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
+#define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
+#define I3C_SR_ABT_Pos                      (17U)
+#define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
+#define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
+#define I3C_SR_DIR_Pos                      (18U)
+#define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
+#define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
+#define I3C_SR_MID_Pos                      (24U)
+#define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
+#define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
+
+/*******************  Bit definition for I3C_SER register  ********************/
+#define I3C_SER_CODERR_Pos                  (0U)
+#define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
+#define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
+#define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
+#define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
+#define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
+#define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
+#define I3C_SER_PERR_Pos                    (4U)
+#define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
+#define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
+#define I3C_SER_STALL_Pos                   (5U)
+#define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
+#define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
+#define I3C_SER_DOVR_Pos                    (6U)
+#define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
+#define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
+#define I3C_SER_COVR_Pos                    (7U)
+#define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
+#define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
+#define I3C_SER_ANACK_Pos                   (8U)
+#define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
+#define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
+#define I3C_SER_DNACK_Pos                   (9U)
+#define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
+#define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
+#define I3C_SER_DERR_Pos                    (10U)
+#define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
+#define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
+
+/*******************  Bit definition for I3C_RMR register  ********************/
+#define I3C_RMR_IBIRDCNT_Pos                (0U)
+#define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
+#define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
+#define I3C_RMR_RCODE_Pos                   (8U)
+#define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
+#define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
+#define I3C_RMR_RADD_Pos                    (17U)
+#define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
+#define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
+
+/*******************  Bit definition for I3C_EVR register  ********************/
+#define I3C_EVR_CFEF_Pos                    (0U)
+#define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
+#define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
+#define I3C_EVR_TXFEF_Pos                   (1U)
+#define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
+#define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
+#define I3C_EVR_CFNFF_Pos                   (2U)
+#define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
+#define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
+#define I3C_EVR_SFNEF_Pos                   (3U)
+#define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
+#define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
+#define I3C_EVR_TXFNFF_Pos                  (4U)
+#define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
+#define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
+#define I3C_EVR_RXFNEF_Pos                  (5U)
+#define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
+#define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
+#define I3C_EVR_TXLASTF_Pos                 (6U)
+#define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
+#define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
+#define I3C_EVR_RXLASTF_Pos                 (7U)
+#define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
+#define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
+#define I3C_EVR_FCF_Pos                     (9U)
+#define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
+#define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
+#define I3C_EVR_RXTGTENDF_Pos               (10U)
+#define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
+#define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
+#define I3C_EVR_ERRF_Pos                    (11U)
+#define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
+#define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
+#define I3C_EVR_IBIF_Pos                    (15U)
+#define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
+#define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
+#define I3C_EVR_IBIENDF_Pos                 (16U)
+#define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
+#define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
+#define I3C_EVR_CRF_Pos                     (17U)
+#define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
+#define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
+#define I3C_EVR_CRUPDF_Pos                  (18U)
+#define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
+#define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
+#define I3C_EVR_HJF_Pos                     (19U)
+#define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
+#define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
+#define I3C_EVR_WKPF_Pos                    (21U)
+#define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
+#define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
+#define I3C_EVR_GETF_Pos                    (22U)
+#define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
+#define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
+#define I3C_EVR_STAF_Pos                    (23U)
+#define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
+#define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
+#define I3C_EVR_DAUPDF_Pos                  (24U)
+#define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
+#define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
+#define I3C_EVR_MWLUPDF_Pos                 (25U)
+#define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
+#define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
+#define I3C_EVR_MRLUPDF_Pos                 (26U)
+#define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
+#define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
+#define I3C_EVR_RSTF_Pos                    (27U)
+#define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
+#define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
+#define I3C_EVR_ASUPDF_Pos                  (28U)
+#define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
+#define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
+#define I3C_EVR_INTUPDF_Pos                 (29U)
+#define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
+#define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
+#define I3C_EVR_DEFF_Pos                    (30U)
+#define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
+#define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
+#define I3C_EVR_GRPF_Pos                    (31U)
+#define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
+#define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
+
+/*******************  Bit definition for I3C_IER register  ********************/
+#define I3C_IER_CFNFIE_Pos                  (2U)
+#define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
+#define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
+#define I3C_IER_SFNEIE_Pos                  (3U)
+#define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
+#define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
+#define I3C_IER_TXFNFIE_Pos                 (4U)
+#define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
+#define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
+#define I3C_IER_RXFNEIE_Pos                 (5U)
+#define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
+#define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
+#define I3C_IER_FCIE_Pos                    (9U)
+#define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
+#define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
+#define I3C_IER_RXTGTENDIE_Pos              (10U)
+#define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
+#define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
+#define I3C_IER_ERRIE_Pos                   (11U)
+#define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
+#define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
+#define I3C_IER_IBIIE_Pos                   (15U)
+#define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
+#define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
+#define I3C_IER_IBIENDIE_Pos                (16U)
+#define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
+#define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
+#define I3C_IER_CRIE_Pos                    (17U)
+#define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
+#define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
+#define I3C_IER_CRUPDIE_Pos                 (18U)
+#define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
+#define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
+#define I3C_IER_HJIE_Pos                    (19U)
+#define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
+#define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
+#define I3C_IER_WKPIE_Pos                   (21U)
+#define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
+#define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
+#define I3C_IER_GETIE_Pos                   (22U)
+#define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
+#define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
+#define I3C_IER_STAIE_Pos                   (23U)
+#define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
+#define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
+#define I3C_IER_DAUPDIE_Pos                 (24U)
+#define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
+#define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
+#define I3C_IER_MWLUPDIE_Pos                (25U)
+#define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
+#define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
+#define I3C_IER_MRLUPDIE_Pos                (26U)
+#define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
+#define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
+#define I3C_IER_RSTIE_Pos                   (27U)
+#define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
+#define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
+#define I3C_IER_ASUPDIE_Pos                 (28U)
+#define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
+#define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
+#define I3C_IER_INTUPDIE_Pos                (29U)
+#define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
+#define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
+#define I3C_IER_DEFIE_Pos                   (30U)
+#define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
+#define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
+#define I3C_IER_GRPIE_Pos                   (31U)
+#define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
+#define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
+
+/*******************  Bit definition for I3C_CEVR register  *******************/
+#define I3C_CEVR_CFCF_Pos                   (9U)
+#define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
+#define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
+#define I3C_CEVR_CRXTGTENDF_Pos             (10U)
+#define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
+#define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
+#define I3C_CEVR_CERRF_Pos                  (11U)
+#define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
+#define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
+#define I3C_CEVR_CIBIF_Pos                  (15U)
+#define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
+#define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
+#define I3C_CEVR_CIBIENDF_Pos               (16U)
+#define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
+#define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
+#define I3C_CEVR_CCRF_Pos                   (17U)
+#define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
+#define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
+#define I3C_CEVR_CCRUPDF_Pos                (18U)
+#define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
+#define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
+#define I3C_CEVR_CHJF_Pos                   (19U)
+#define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
+#define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
+#define I3C_CEVR_CWKPF_Pos                  (21U)
+#define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
+#define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
+#define I3C_CEVR_CGETF_Pos                  (22U)
+#define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
+#define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
+#define I3C_CEVR_CSTAF_Pos                  (23U)
+#define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
+#define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
+#define I3C_CEVR_CDAUPDF_Pos                (24U)
+#define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
+#define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
+#define I3C_CEVR_CMWLUPDF_Pos               (25U)
+#define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
+#define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
+#define I3C_CEVR_CMRLUPDF_Pos               (26U)
+#define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
+#define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
+#define I3C_CEVR_CRSTF_Pos                  (27U)
+#define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
+#define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
+#define I3C_CEVR_CASUPDF_Pos                (28U)
+#define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
+#define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
+#define I3C_CEVR_CINTUPDF_Pos               (29U)
+#define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
+#define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
+#define I3C_CEVR_CDEFF_Pos                  (30U)
+#define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
+#define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
+#define I3C_CEVR_CGRPF_Pos                  (31U)
+#define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
+#define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
+
+/******************  Bit definition for I3C_DEVR0 register  *******************/
+#define I3C_DEVR0_DAVAL_Pos                 (0U)
+#define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
+#define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
+#define I3C_DEVR0_DA_Pos                    (1U)
+#define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
+#define I3C_DEVR0_IBIEN_Pos                 (16U)
+#define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
+#define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
+#define I3C_DEVR0_CREN_Pos                  (17U)
+#define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
+#define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
+#define I3C_DEVR0_HJEN_Pos                  (19U)
+#define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
+#define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
+#define I3C_DEVR0_AS_Pos                    (20U)
+#define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
+#define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
+#define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
+#define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
+#define I3C_DEVR0_RSTACT_Pos                (22U)
+#define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
+#define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
+#define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
+#define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
+#define I3C_DEVR0_RSTVAL_Pos                (24U)
+#define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
+#define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
+
+/******************  Bit definition for I3C_DEVRX register  *******************/
+#define I3C_DEVRX_DA_Pos                    (1U)
+#define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
+#define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
+#define I3C_DEVRX_IBIACK_Pos                (16U)
+#define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
+#define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
+#define I3C_DEVRX_CRACK_Pos                 (17U)
+#define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
+#define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
+#define I3C_DEVRX_IBIDEN_Pos                (18U)
+#define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
+#define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
+#define I3C_DEVRX_SUSP_Pos                  (19U)
+#define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
+#define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
+#define I3C_DEVRX_DIS_Pos                   (31U)
+#define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
+#define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
+
+/******************  Bit definition for I3C_MAXRLR register  ******************/
+#define I3C_MAXRLR_MRL_Pos                  (0U)
+#define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
+#define I3C_MAXRLR_IBIP_Pos                 (16U)
+#define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
+#define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
+#define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
+#define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
+#define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
+
+/******************  Bit definition for I3C_MAXWLR register  ******************/
+#define I3C_MAXWLR_MWL_Pos                  (0U)
+#define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
+#define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
+
+/****************  Bit definition for I3C_TIMINGR0 register  ******************/
+#define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
+#define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
+#define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
+#define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
+#define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
+#define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
+#define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
+#define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
+#define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
+#define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
+#define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
+#define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
+
+/****************  Bit definition for I3C_TIMINGR1 register  ******************/
+#define I3C_TIMINGR1_AVAL_Pos               (0U)
+#define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
+#define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
+#define I3C_TIMINGR1_ASNCR_Pos              (8U)
+#define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
+#define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
+#define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
+#define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
+#define I3C_TIMINGR1_FREE_Pos               (16U)
+#define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
+#define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
+#define I3C_TIMINGR1_SDA_HD_Pos             (28U)
+#define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
+#define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
+
+/****************  Bit definition for I3C_TIMINGR2 register  ******************/
+#define I3C_TIMINGR2_STALLT_Pos             (0U)
+#define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x0000001 */
+#define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
+#define I3C_TIMINGR2_STALLD_Pos             (1U)
+#define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x0000002 */
+#define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
+#define I3C_TIMINGR2_STALLC_Pos             (2U)
+#define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x0000004 */
+#define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
+#define I3C_TIMINGR2_STALLA_Pos             (3U)
+#define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x0000008 */
+#define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
+#define I3C_TIMINGR2_STALL_Pos              (8U)
+#define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x000FF00 */
+#define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
+
+/*******************  Bit definition for I3C_BCR register  ********************/
+#define I3C_BCR_BCR_Pos                     (0U)
+#define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
+#define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
+#define I3C_BCR_BCR0_Pos                    (0U)
+#define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
+#define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
+#define I3C_BCR_BCR1_Pos                    (1U)
+#define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
+#define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
+#define I3C_BCR_BCR2_Pos                    (2U)
+#define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
+#define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
+#define I3C_BCR_BCR3_Pos                    (3U)
+#define I3C_BCR_BCR3_Msk                    (0x1UL << I3C_BCR_BCR3_Pos)             /*!< 0x00000008 */
+#define I3C_BCR_BCR3                        I3C_BCR_BCR3_Msk                        /*!< Offline capable */
+#define I3C_BCR_BCR4_Pos                    (4U)
+#define I3C_BCR_BCR4_Msk                    (0x1UL << I3C_BCR_BCR4_Pos)             /*!< 0x00000010 */
+#define I3C_BCR_BCR4                        I3C_BCR_BCR4_Msk                        /*!< Virtual target support */
+#define I3C_BCR_BCR5_Pos                    (5U)
+#define I3C_BCR_BCR5_Msk                    (0x1UL << I3C_BCR_BCR5_Pos)             /*!< 0x00000020 */
+#define I3C_BCR_BCR5                        I3C_BCR_BCR5_Msk                        /*!< Advanced capabilities */
+#define I3C_BCR_BCR6_Pos                    (6U)
+#define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
+#define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
+
+/*******************  Bit definition for I3C_DCR register  ********************/
+#define I3C_DCR_DCR_Pos                     (0U)
+#define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x00000FF */
+#define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
+
+/*****************  Bit definition for I3C_GETCAPR register  ******************/
+#define I3C_GETCAPR_CAPPEND_Pos             (14U)
+#define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
+#define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
+
+/*****************  Bit definition for I3C_CRCAPR register  *******************/
+#define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
+#define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
+#define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
+#define I3C_CRCAPR_CAPGRP_Pos               (9U)
+#define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
+#define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
+
+/****************  Bit definition for I3C_GETMXDSR register  ******************/
+#define I3C_GETMXDSR_HOFFAS_Pos             (0U)
+#define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
+#define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
+#define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
+#define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
+#define I3C_GETMXDSR_FMT_Pos                (8U)
+#define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
+#define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
+#define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
+#define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
+#define I3C_GETMXDSR_RDTURN_Pos             (16U)
+#define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
+#define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
+#define I3C_GETMXDSR_TSCO_Pos               (24U)
+#define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
+#define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
+
+/******************  Bit definition for I3C_EPIDR register  *******************/
+#define I3C_EPIDR_MIPIID_Pos                (12U)
+#define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
+#define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
+#define I3C_EPIDR_IDTSEL_Pos                (16U)
+#define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
+#define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
+#define I3C_EPIDR_MIPIMID_Pos               (17U)
+#define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
+#define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*             Illegal Access Controller (IAC)                                */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for IAC_IER0 register *******************/
+#define IAC_IER0_IAIE0_Pos            (0U)
+#define IAC_IER0_IAIE0_Msk            (0x1UL << IAC_IER0_IAIE0_Pos)              /*!< 0x00000001 */
+#define IAC_IER0_IAIE0                IAC_IER0_IAIE0_Msk
+#define IAC_IER0_IAIE1_Pos            (1U)
+#define IAC_IER0_IAIE1_Msk            (0x1UL << IAC_IER0_IAIE1_Pos)              /*!< 0x00000002 */
+#define IAC_IER0_IAIE1                IAC_IER0_IAIE1_Msk
+#define IAC_IER0_IAIE2_Pos            (2U)
+#define IAC_IER0_IAIE2_Msk            (0x1UL << IAC_IER0_IAIE2_Pos)              /*!< 0x00000004 */
+#define IAC_IER0_IAIE2                IAC_IER0_IAIE2_Msk
+#define IAC_IER0_IAIE3_Pos            (3U)
+#define IAC_IER0_IAIE3_Msk            (0x1UL << IAC_IER0_IAIE3_Pos)              /*!< 0x00000008 */
+#define IAC_IER0_IAIE3                IAC_IER0_IAIE3_Msk
+#define IAC_IER0_IAIE4_Pos            (4U)
+#define IAC_IER0_IAIE4_Msk            (0x1UL << IAC_IER0_IAIE4_Pos)              /*!< 0x00000010 */
+#define IAC_IER0_IAIE4                IAC_IER0_IAIE4_Msk
+#define IAC_IER0_IAIE5_Pos            (5U)
+#define IAC_IER0_IAIE5_Msk            (0x1UL << IAC_IER0_IAIE5_Pos)              /*!< 0x00000020 */
+#define IAC_IER0_IAIE5                IAC_IER0_IAIE5_Msk
+#define IAC_IER0_IAIE6_Pos            (6U)
+#define IAC_IER0_IAIE6_Msk            (0x1UL << IAC_IER0_IAIE6_Pos)              /*!< 0x00000040 */
+#define IAC_IER0_IAIE6                IAC_IER0_IAIE6_Msk
+#define IAC_IER0_IAIE8_Pos            (8U)
+#define IAC_IER0_IAIE8_Msk            (0x1UL << IAC_IER0_IAIE8_Pos)              /*!< 0x00000100 */
+#define IAC_IER0_IAIE8                IAC_IER0_IAIE8_Msk
+#define IAC_IER0_IAIE9_Pos            (9U)
+#define IAC_IER0_IAIE9_Msk            (0x1UL << IAC_IER0_IAIE9_Pos)              /*!< 0x00000200 */
+#define IAC_IER0_IAIE9                IAC_IER0_IAIE9_Msk
+#define IAC_IER0_IAIE10_Pos           (10U)
+#define IAC_IER0_IAIE10_Msk           (0x1UL << IAC_IER0_IAIE10_Pos)             /*!< 0x00000400 */
+#define IAC_IER0_IAIE10               IAC_IER0_IAIE10_Msk
+#define IAC_IER0_IAIE11_Pos           (11U)
+#define IAC_IER0_IAIE11_Msk           (0x1UL << IAC_IER0_IAIE11_Pos)             /*!< 0x00000800 */
+#define IAC_IER0_IAIE11               IAC_IER0_IAIE11_Msk
+#define IAC_IER0_IAIE12_Pos           (12U)
+#define IAC_IER0_IAIE12_Msk           (0x1UL << IAC_IER0_IAIE12_Pos)             /*!< 0x00001000 */
+#define IAC_IER0_IAIE12               IAC_IER0_IAIE12_Msk
+#define IAC_IER0_IAIE13_Pos           (13U)
+#define IAC_IER0_IAIE13_Msk           (0x1UL << IAC_IER0_IAIE13_Pos)             /*!< 0x00002000 */
+#define IAC_IER0_IAIE13               IAC_IER0_IAIE13_Msk
+#define IAC_IER0_IAIE14_Pos           (14U)
+#define IAC_IER0_IAIE14_Msk           (0x1UL << IAC_IER0_IAIE14_Pos)             /*!< 0x00004000 */
+#define IAC_IER0_IAIE14               IAC_IER0_IAIE14_Msk
+#define IAC_IER0_IAIE15_Pos           (15U)
+#define IAC_IER0_IAIE15_Msk           (0x1UL << IAC_IER0_IAIE15_Pos)             /*!< 0x00008000 */
+#define IAC_IER0_IAIE15               IAC_IER0_IAIE15_Msk
+#define IAC_IER0_IAIE16_Pos           (16U)
+#define IAC_IER0_IAIE16_Msk           (0x1UL << IAC_IER0_IAIE16_Pos)             /*!< 0x00010000 */
+#define IAC_IER0_IAIE16               IAC_IER0_IAIE16_Msk
+#define IAC_IER0_IAIE17_Pos           (17U)
+#define IAC_IER0_IAIE17_Msk           (0x1UL << IAC_IER0_IAIE17_Pos)             /*!< 0x00020000 */
+#define IAC_IER0_IAIE17               IAC_IER0_IAIE17_Msk
+#define IAC_IER0_IAIE18_Pos           (18U)
+#define IAC_IER0_IAIE18_Msk           (0x1UL << IAC_IER0_IAIE18_Pos)             /*!< 0x00040000 */
+#define IAC_IER0_IAIE18               IAC_IER0_IAIE18_Msk
+#define IAC_IER0_IAIE19_Pos           (19U)
+#define IAC_IER0_IAIE19_Msk           (0x1UL << IAC_IER0_IAIE19_Pos)             /*!< 0x00080000 */
+#define IAC_IER0_IAIE19               IAC_IER0_IAIE19_Msk
+#define IAC_IER0_IAIE20_Pos           (20U)
+#define IAC_IER0_IAIE20_Msk           (0x1UL << IAC_IER0_IAIE20_Pos)             /*!< 0x00100000 */
+#define IAC_IER0_IAIE20               IAC_IER0_IAIE20_Msk
+#define IAC_IER0_IAIE21_Pos           (21U)
+#define IAC_IER0_IAIE21_Msk           (0x1UL << IAC_IER0_IAIE21_Pos)             /*!< 0x00200000 */
+#define IAC_IER0_IAIE21               IAC_IER0_IAIE21_Msk
+#define IAC_IER0_IAIE22_Pos           (22U)
+#define IAC_IER0_IAIE22_Msk           (0x1UL << IAC_IER0_IAIE22_Pos)             /*!< 0x00400000 */
+#define IAC_IER0_IAIE22               IAC_IER0_IAIE22_Msk
+#define IAC_IER0_IAIE23_Pos           (23U)
+#define IAC_IER0_IAIE23_Msk           (0x1UL << IAC_IER0_IAIE23_Pos)             /*!< 0x00800000 */
+#define IAC_IER0_IAIE23               IAC_IER0_IAIE23_Msk
+#define IAC_IER0_IAIE24_Pos           (24U)
+#define IAC_IER0_IAIE24_Msk           (0x1UL << IAC_IER0_IAIE24_Pos)             /*!< 0x01000000 */
+#define IAC_IER0_IAIE24               IAC_IER0_IAIE24_Msk
+#define IAC_IER0_IAIE25_Pos           (25U)
+#define IAC_IER0_IAIE25_Msk           (0x1UL << IAC_IER0_IAIE25_Pos)             /*!< 0x02000000 */
+#define IAC_IER0_IAIE25               IAC_IER0_IAIE25_Msk
+#define IAC_IER0_IAIE26_Pos           (26U)
+#define IAC_IER0_IAIE26_Msk           (0x1UL << IAC_IER0_IAIE26_Pos)             /*!< 0x04000000 */
+#define IAC_IER0_IAIE26               IAC_IER0_IAIE26_Msk
+#define IAC_IER0_IAIE27_Pos           (27U)
+#define IAC_IER0_IAIE27_Msk           (0x1UL << IAC_IER0_IAIE27_Pos)             /*!< 0x08000000 */
+#define IAC_IER0_IAIE27               IAC_IER0_IAIE27_Msk
+#define IAC_IER0_IAIE28_Pos           (28U)
+#define IAC_IER0_IAIE28_Msk           (0x1UL << IAC_IER0_IAIE28_Pos)             /*!< 0x10000000 */
+#define IAC_IER0_IAIE28               IAC_IER0_IAIE28_Msk
+#define IAC_IER0_IAIE29_Pos           (29U)
+#define IAC_IER0_IAIE29_Msk           (0x1UL << IAC_IER0_IAIE29_Pos)             /*!< 0x20000000 */
+#define IAC_IER0_IAIE29               IAC_IER0_IAIE29_Msk
+#define IAC_IER0_IAIE30_Pos           (30U)
+#define IAC_IER0_IAIE30_Msk           (0x1UL << IAC_IER0_IAIE30_Pos)             /*!< 0x40000000 */
+#define IAC_IER0_IAIE30               IAC_IER0_IAIE30_Msk
+#define IAC_IER0_IAIE31_Pos           (31U)
+#define IAC_IER0_IAIE31_Msk           (0x1UL << IAC_IER0_IAIE31_Pos)             /*!< 0x80000000 */
+#define IAC_IER0_IAIE31               IAC_IER0_IAIE31_Msk
+
+/*******************  Bits definition for IAC_IER1 register *******************/
+#define IAC_IER1_IAIE32_Pos           (0U)
+#define IAC_IER1_IAIE32_Msk           (0x1UL << IAC_IER1_IAIE32_Pos)             /*!< 0x00000001 */
+#define IAC_IER1_IAIE32               IAC_IER1_IAIE32_Msk
+#define IAC_IER1_IAIE33_Pos           (1U)
+#define IAC_IER1_IAIE33_Msk           (0x1UL << IAC_IER1_IAIE33_Pos)             /*!< 0x00000002 */
+#define IAC_IER1_IAIE33               IAC_IER1_IAIE33_Msk
+#define IAC_IER1_IAIE34_Pos           (2U)
+#define IAC_IER1_IAIE34_Msk           (0x1UL << IAC_IER1_IAIE34_Pos)             /*!< 0x00000004 */
+#define IAC_IER1_IAIE34               IAC_IER1_IAIE34_Msk
+#define IAC_IER1_IAIE35_Pos           (3U)
+#define IAC_IER1_IAIE35_Msk           (0x1UL << IAC_IER1_IAIE35_Pos)             /*!< 0x00000008 */
+#define IAC_IER1_IAIE35               IAC_IER1_IAIE35_Msk
+#define IAC_IER1_IAIE36_Pos           (4U)
+#define IAC_IER1_IAIE36_Msk           (0x1UL << IAC_IER1_IAIE36_Pos)             /*!< 0x00000010 */
+#define IAC_IER1_IAIE36               IAC_IER1_IAIE36_Msk
+#define IAC_IER1_IAIE37_Pos           (5U)
+#define IAC_IER1_IAIE37_Msk           (0x1UL << IAC_IER1_IAIE37_Pos)             /*!< 0x00000020 */
+#define IAC_IER1_IAIE37               IAC_IER1_IAIE37_Msk
+#define IAC_IER1_IAIE38_Pos           (6U)
+#define IAC_IER1_IAIE38_Msk           (0x1UL << IAC_IER1_IAIE38_Pos)             /*!< 0x00000040 */
+#define IAC_IER1_IAIE38               IAC_IER1_IAIE38_Msk
+#define IAC_IER1_IAIE39_Pos           (7U)
+#define IAC_IER1_IAIE39_Msk           (0x1UL << IAC_IER1_IAIE39_Pos)             /*!< 0x00000080 */
+#define IAC_IER1_IAIE39               IAC_IER1_IAIE39_Msk
+#define IAC_IER1_IAIE40_Pos           (8U)
+#define IAC_IER1_IAIE40_Msk           (0x1UL << IAC_IER1_IAIE40_Pos)             /*!< 0x00000100 */
+#define IAC_IER1_IAIE40               IAC_IER1_IAIE40_Msk
+#define IAC_IER1_IAIE41_Pos           (9U)
+#define IAC_IER1_IAIE41_Msk           (0x1UL << IAC_IER1_IAIE41_Pos)             /*!< 0x00000200 */
+#define IAC_IER1_IAIE41               IAC_IER1_IAIE41_Msk
+#define IAC_IER1_IAIE42_Pos           (10U)
+#define IAC_IER1_IAIE42_Msk           (0x1UL << IAC_IER1_IAIE42_Pos)             /*!< 0x00000400 */
+#define IAC_IER1_IAIE42               IAC_IER1_IAIE42_Msk
+#define IAC_IER1_IAIE43_Pos           (11U)
+#define IAC_IER1_IAIE43_Msk           (0x1UL << IAC_IER1_IAIE43_Pos)             /*!< 0x00000800 */
+#define IAC_IER1_IAIE43               IAC_IER1_IAIE43_Msk
+#define IAC_IER1_IAIE44_Pos           (12U)
+#define IAC_IER1_IAIE44_Msk           (0x1UL << IAC_IER1_IAIE44_Pos)             /*!< 0x00001000 */
+#define IAC_IER1_IAIE44               IAC_IER1_IAIE44_Msk
+#define IAC_IER1_IAIE45_Pos           (13U)
+#define IAC_IER1_IAIE45_Msk           (0x1UL << IAC_IER1_IAIE45_Pos)             /*!< 0x00002000 */
+#define IAC_IER1_IAIE45               IAC_IER1_IAIE45_Msk
+#define IAC_IER1_IAIE46_Pos           (14U)
+#define IAC_IER1_IAIE46_Msk           (0x1UL << IAC_IER1_IAIE46_Pos)             /*!< 0x00004000 */
+#define IAC_IER1_IAIE46               IAC_IER1_IAIE46_Msk
+#define IAC_IER1_IAIE47_Pos           (15U)
+#define IAC_IER1_IAIE47_Msk           (0x1UL << IAC_IER1_IAIE47_Pos)             /*!< 0x00008000 */
+#define IAC_IER1_IAIE47               IAC_IER1_IAIE47_Msk
+#define IAC_IER1_IAIE48_Pos           (16U)
+#define IAC_IER1_IAIE48_Msk           (0x1UL << IAC_IER1_IAIE48_Pos)             /*!< 0x00010000 */
+#define IAC_IER1_IAIE48               IAC_IER1_IAIE48_Msk
+#define IAC_IER1_IAIE49_Pos           (17U)
+#define IAC_IER1_IAIE49_Msk           (0x1UL << IAC_IER1_IAIE49_Pos)             /*!< 0x00020000 */
+#define IAC_IER1_IAIE49               IAC_IER1_IAIE49_Msk
+#define IAC_IER1_IAIE50_Pos           (18U)
+#define IAC_IER1_IAIE50_Msk           (0x1UL << IAC_IER1_IAIE50_Pos)             /*!< 0x00040000 */
+#define IAC_IER1_IAIE50               IAC_IER1_IAIE50_Msk
+#define IAC_IER1_IAIE51_Pos           (19U)
+#define IAC_IER1_IAIE51_Msk           (0x1UL << IAC_IER1_IAIE51_Pos)             /*!< 0x00080000 */
+#define IAC_IER1_IAIE51               IAC_IER1_IAIE51_Msk
+#define IAC_IER1_IAIE52_Pos           (20U)
+#define IAC_IER1_IAIE52_Msk           (0x1UL << IAC_IER1_IAIE52_Pos)             /*!< 0x00100000 */
+#define IAC_IER1_IAIE52               IAC_IER1_IAIE52_Msk
+#define IAC_IER1_IAIE53_Pos           (21U)
+#define IAC_IER1_IAIE53_Msk           (0x1UL << IAC_IER1_IAIE53_Pos)             /*!< 0x00200000 */
+#define IAC_IER1_IAIE53               IAC_IER1_IAIE53_Msk
+#define IAC_IER1_IAIE54_Pos           (22U)
+#define IAC_IER1_IAIE54_Msk           (0x1UL << IAC_IER1_IAIE54_Pos)             /*!< 0x00400000 */
+#define IAC_IER1_IAIE54               IAC_IER1_IAIE54_Msk
+#define IAC_IER1_IAIE55_Pos           (23U)
+#define IAC_IER1_IAIE55_Msk           (0x1UL << IAC_IER1_IAIE55_Pos)             /*!< 0x00800000 */
+#define IAC_IER1_IAIE55               IAC_IER1_IAIE55_Msk
+#define IAC_IER1_IAIE56_Pos           (24U)
+#define IAC_IER1_IAIE56_Msk           (0x1UL << IAC_IER1_IAIE56_Pos)             /*!< 0x01000000 */
+#define IAC_IER1_IAIE56               IAC_IER1_IAIE56_Msk
+#define IAC_IER1_IAIE57_Pos           (25U)
+#define IAC_IER1_IAIE57_Msk           (0x1UL << IAC_IER1_IAIE57_Pos)             /*!< 0x02000000 */
+#define IAC_IER1_IAIE57               IAC_IER1_IAIE57_Msk
+#define IAC_IER1_IAIE58_Pos           (26U)
+#define IAC_IER1_IAIE58_Msk           (0x1UL << IAC_IER1_IAIE58_Pos)             /*!< 0x04000000 */
+#define IAC_IER1_IAIE58               IAC_IER1_IAIE58_Msk
+#define IAC_IER1_IAIE60_Pos           (28U)
+#define IAC_IER1_IAIE60_Msk           (0x1UL << IAC_IER1_IAIE60_Pos)             /*!< 0x10000000 */
+#define IAC_IER1_IAIE60               IAC_IER1_IAIE60_Msk
+#define IAC_IER1_IAIE61_Pos           (29U)
+#define IAC_IER1_IAIE61_Msk           (0x1UL << IAC_IER1_IAIE61_Pos)             /*!< 0x20000000 */
+#define IAC_IER1_IAIE61               IAC_IER1_IAIE61_Msk
+#define IAC_IER1_IAIE62_Pos           (30U)
+#define IAC_IER1_IAIE62_Msk           (0x1UL << IAC_IER1_IAIE62_Pos)             /*!< 0x40000000 */
+#define IAC_IER1_IAIE62               IAC_IER1_IAIE62_Msk
+
+/*******************  Bits definition for IAC_IER2 register *******************/
+#define IAC_IER2_IAIE64_Pos           (0U)
+#define IAC_IER2_IAIE64_Msk           (0x1UL << IAC_IER2_IAIE64_Pos)             /*!< 0x00000001 */
+#define IAC_IER2_IAIE64               IAC_IER2_IAIE64_Msk
+#define IAC_IER2_IAIE65_Pos           (1U)
+#define IAC_IER2_IAIE65_Msk           (0x1UL << IAC_IER2_IAIE65_Pos)             /*!< 0x00000002 */
+#define IAC_IER2_IAIE65               IAC_IER2_IAIE65_Msk
+#define IAC_IER2_IAIE67_Pos           (3U)
+#define IAC_IER2_IAIE67_Msk           (0x1UL << IAC_IER2_IAIE67_Pos)             /*!< 0x00000008 */
+#define IAC_IER2_IAIE67               IAC_IER2_IAIE67_Msk
+#define IAC_IER2_IAIE68_Pos           (4U)
+#define IAC_IER2_IAIE68_Msk           (0x1UL << IAC_IER2_IAIE68_Pos)             /*!< 0x00000010 */
+#define IAC_IER2_IAIE68               IAC_IER2_IAIE68_Msk
+#define IAC_IER2_IAIE69_Pos           (5U)
+#define IAC_IER2_IAIE69_Msk           (0x1UL << IAC_IER2_IAIE69_Pos)             /*!< 0x00000020 */
+#define IAC_IER2_IAIE69               IAC_IER2_IAIE69_Msk
+#define IAC_IER2_IAIE76_Pos           (12U)
+#define IAC_IER2_IAIE76_Msk           (0x1UL << IAC_IER2_IAIE76_Pos)             /*!< 0x00001000 */
+#define IAC_IER2_IAIE76               IAC_IER2_IAIE76_Msk
+#define IAC_IER2_IAIE77_Pos           (13U)
+#define IAC_IER2_IAIE77_Msk           (0x1UL << IAC_IER2_IAIE77_Pos)             /*!< 0x00002000 */
+#define IAC_IER2_IAIE77               IAC_IER2_IAIE77_Msk
+#define IAC_IER2_IAIE78_Pos           (14U)
+#define IAC_IER2_IAIE78_Msk           (0x1UL << IAC_IER2_IAIE78_Pos)             /*!< 0x00004000 */
+#define IAC_IER2_IAIE78               IAC_IER2_IAIE78_Msk
+#define IAC_IER2_IAIE79_Pos           (15U)
+#define IAC_IER2_IAIE79_Msk           (0x1UL << IAC_IER2_IAIE79_Pos)             /*!< 0x00008000 */
+#define IAC_IER2_IAIE79               IAC_IER2_IAIE79_Msk
+#define IAC_IER2_IAIE80_Pos           (16U)
+#define IAC_IER2_IAIE80_Msk           (0x1UL << IAC_IER2_IAIE80_Pos)             /*!< 0x00010000 */
+#define IAC_IER2_IAIE80               IAC_IER2_IAIE80_Msk
+#define IAC_IER2_IAIE81_Pos           (17U)
+#define IAC_IER2_IAIE81_Msk           (0x1UL << IAC_IER2_IAIE81_Pos)             /*!< 0x00020000 */
+#define IAC_IER2_IAIE81               IAC_IER2_IAIE81_Msk
+#define IAC_IER2_IAIE82_Pos           (18U)
+#define IAC_IER2_IAIE82_Msk           (0x1UL << IAC_IER2_IAIE82_Pos)             /*!< 0x00040000 */
+#define IAC_IER2_IAIE82               IAC_IER2_IAIE82_Msk
+#define IAC_IER2_IAIE83_Pos           (19U)
+#define IAC_IER2_IAIE83_Msk           (0x1UL << IAC_IER2_IAIE83_Pos)             /*!< 0x00080000 */
+#define IAC_IER2_IAIE83               IAC_IER2_IAIE83_Msk
+#define IAC_IER2_IAIE84_Pos           (20U)
+#define IAC_IER2_IAIE84_Msk           (0x1UL << IAC_IER2_IAIE84_Pos)             /*!< 0x00100000 */
+#define IAC_IER2_IAIE84               IAC_IER2_IAIE84_Msk
+#define IAC_IER2_IAIE86_Pos           (22U)
+#define IAC_IER2_IAIE86_Msk           (0x1UL << IAC_IER2_IAIE86_Pos)             /*!< 0x00400000 */
+#define IAC_IER2_IAIE86               IAC_IER2_IAIE86_Msk
+#define IAC_IER2_IAIE87_Pos           (23U)
+#define IAC_IER2_IAIE87_Msk           (0x1UL << IAC_IER2_IAIE87_Pos)             /*!< 0x00800000 */
+#define IAC_IER2_IAIE87               IAC_IER2_IAIE87_Msk
+#define IAC_IER2_IAIE88_Pos           (24U)
+#define IAC_IER2_IAIE88_Msk           (0x1UL << IAC_IER2_IAIE88_Pos)             /*!< 0x01000000 */
+#define IAC_IER2_IAIE88               IAC_IER2_IAIE88_Msk
+#define IAC_IER2_IAIE89_Pos           (25U)
+#define IAC_IER2_IAIE89_Msk           (0x1UL << IAC_IER2_IAIE89_Pos)             /*!< 0x02000000 */
+#define IAC_IER2_IAIE89               IAC_IER2_IAIE89_Msk
+#define IAC_IER2_IAIE90_Pos           (26U)
+#define IAC_IER2_IAIE90_Msk           (0x1UL << IAC_IER2_IAIE90_Pos)             /*!< 0x04000000 */
+#define IAC_IER2_IAIE90               IAC_IER2_IAIE90_Msk
+#define IAC_IER2_IAIE92_Pos           (28U)
+#define IAC_IER2_IAIE92_Msk           (0x1UL << IAC_IER2_IAIE92_Pos)             /*!< 0x10000000 */
+#define IAC_IER2_IAIE92               IAC_IER2_IAIE92_Msk
+#define IAC_IER2_IAIE93_Pos           (29U)
+#define IAC_IER2_IAIE93_Msk           (0x1UL << IAC_IER2_IAIE93_Pos)             /*!< 0x20000000 */
+#define IAC_IER2_IAIE93               IAC_IER2_IAIE93_Msk
+#define IAC_IER2_IAIE94_Pos           (30U)
+#define IAC_IER2_IAIE94_Msk           (0x1UL << IAC_IER2_IAIE94_Pos)             /*!< 0x40000000 */
+#define IAC_IER2_IAIE94               IAC_IER2_IAIE94_Msk
+#define IAC_IER2_IAIE95_Pos           (31U)
+#define IAC_IER2_IAIE95_Msk           (0x1UL << IAC_IER2_IAIE95_Pos)             /*!< 0x80000000 */
+#define IAC_IER2_IAIE95               IAC_IER2_IAIE95_Msk
+
+/*******************  Bits definition for IAC_IER3 register *******************/
+#define IAC_IER3_IAIE96_Pos           (0U)
+#define IAC_IER3_IAIE96_Msk           (0x1UL << IAC_IER3_IAIE96_Pos)             /*!< 0x00000001 */
+#define IAC_IER3_IAIE96               IAC_IER3_IAIE96_Msk
+#define IAC_IER3_IAIE97_Pos           (1U)
+#define IAC_IER3_IAIE97_Msk           (0x1UL << IAC_IER3_IAIE97_Pos)             /*!< 0x00000002 */
+#define IAC_IER3_IAIE97               IAC_IER3_IAIE97_Msk
+#define IAC_IER3_IAIE98_Pos           (2U)
+#define IAC_IER3_IAIE98_Msk           (0x1UL << IAC_IER3_IAIE98_Pos)             /*!< 0x00000004 */
+#define IAC_IER3_IAIE98               IAC_IER3_IAIE98_Msk
+#define IAC_IER3_IAIE99_Pos           (3U)
+#define IAC_IER3_IAIE99_Msk           (0x1UL << IAC_IER3_IAIE99_Pos)             /*!< 0x00000008 */
+#define IAC_IER3_IAIE99               IAC_IER3_IAIE99_Msk
+#define IAC_IER3_IAIE100_Pos          (4U)
+#define IAC_IER3_IAIE100_Msk          (0x1UL << IAC_IER3_IAIE100_Pos)            /*!< 0x00000010 */
+#define IAC_IER3_IAIE100              IAC_IER3_IAIE100_Msk
+#define IAC_IER3_IAIE101_Pos          (5U)
+#define IAC_IER3_IAIE101_Msk          (0x1UL << IAC_IER3_IAIE101_Pos)            /*!< 0x00000020 */
+#define IAC_IER3_IAIE101              IAC_IER3_IAIE101_Msk
+#define IAC_IER3_IAIE102_Pos          (6U)
+#define IAC_IER3_IAIE102_Msk          (0x1UL << IAC_IER3_IAIE102_Pos)            /*!< 0x00000040 */
+#define IAC_IER3_IAIE102              IAC_IER3_IAIE102_Msk
+#define IAC_IER3_IAIE103_Pos          (7U)
+#define IAC_IER3_IAIE103_Msk          (0x1UL << IAC_IER3_IAIE103_Pos)            /*!< 0x00000080 */
+#define IAC_IER3_IAIE103              IAC_IER3_IAIE103_Msk
+#define IAC_IER3_IAIE104_Pos          (8U)
+#define IAC_IER3_IAIE104_Msk          (0x1UL << IAC_IER3_IAIE104_Pos)            /*!< 0x00000100 */
+#define IAC_IER3_IAIE104              IAC_IER3_IAIE104_Msk
+#define IAC_IER3_IAIE106_Pos          (10U)
+#define IAC_IER3_IAIE106_Msk          (0x1UL << IAC_IER3_IAIE106_Pos)            /*!< 0x00000400 */
+#define IAC_IER3_IAIE106              IAC_IER3_IAIE106_Msk
+
+/*******************  Bits definition for IAC_IER4 register *******************/
+#define IAC_IER4_IAIE128_Pos          (0U)
+#define IAC_IER4_IAIE128_Msk          (0x1UL << IAC_IER4_IAIE128_Pos)            /*!< 0x00000001 */
+#define IAC_IER4_IAIE128              IAC_IER4_IAIE128_Msk
+#define IAC_IER4_IAIE129_Pos          (1U)
+#define IAC_IER4_IAIE129_Msk          (0x1UL << IAC_IER4_IAIE129_Pos)            /*!< 0x00000002 */
+#define IAC_IER4_IAIE129              IAC_IER4_IAIE129_Msk
+#define IAC_IER4_IAIE130_Pos          (2U)
+#define IAC_IER4_IAIE130_Msk          (0x1UL << IAC_IER4_IAIE130_Pos)            /*!< 0x00000004 */
+#define IAC_IER4_IAIE130              IAC_IER4_IAIE130_Msk
+#define IAC_IER4_IAIE131_Pos          (3U)
+#define IAC_IER4_IAIE131_Msk          (0x1UL << IAC_IER4_IAIE131_Pos)            /*!< 0x00000008 */
+#define IAC_IER4_IAIE131              IAC_IER4_IAIE131_Msk
+#define IAC_IER4_IAIE133_Pos          (5U)
+#define IAC_IER4_IAIE133_Msk          (0x1UL << IAC_IER4_IAIE133_Pos)            /*!< 0x00000020 */
+#define IAC_IER4_IAIE133              IAC_IER4_IAIE133_Msk
+#define IAC_IER4_IAIE134_Pos          (6U)
+#define IAC_IER4_IAIE134_Msk          (0x1UL << IAC_IER4_IAIE134_Pos)            /*!< 0x00000040 */
+#define IAC_IER4_IAIE134              IAC_IER4_IAIE134_Msk
+#define IAC_IER4_IAIE135_Pos          (7U)
+#define IAC_IER4_IAIE135_Msk          (0x1UL << IAC_IER4_IAIE135_Pos)            /*!< 0x00000080 */
+#define IAC_IER4_IAIE135              IAC_IER4_IAIE135_Msk
+#define IAC_IER4_IAIE136_Pos          (8U)
+#define IAC_IER4_IAIE136_Msk          (0x1UL << IAC_IER4_IAIE136_Pos)            /*!< 0x00000100 */
+#define IAC_IER4_IAIE136              IAC_IER4_IAIE136_Msk
+#define IAC_IER4_IAIE137_Pos          (9U)
+#define IAC_IER4_IAIE137_Msk          (0x1UL << IAC_IER4_IAIE137_Pos)            /*!< 0x00000200 */
+#define IAC_IER4_IAIE137              IAC_IER4_IAIE137_Msk
+#define IAC_IER4_IAIE138_Pos          (10U)
+#define IAC_IER4_IAIE138_Msk          (0x1UL << IAC_IER4_IAIE138_Pos)            /*!< 0x00000400 */
+#define IAC_IER4_IAIE138              IAC_IER4_IAIE138_Msk
+#define IAC_IER4_IAIE139_Pos          (11U)
+#define IAC_IER4_IAIE139_Msk          (0x1UL << IAC_IER4_IAIE139_Pos)            /*!< 0x00000800 */
+#define IAC_IER4_IAIE139              IAC_IER4_IAIE139_Msk
+#define IAC_IER4_IAIE140_Pos          (12U)
+#define IAC_IER4_IAIE140_Msk          (0x1UL << IAC_IER4_IAIE140_Pos)            /*!< 0x00001000 */
+#define IAC_IER4_IAIE140              IAC_IER4_IAIE140_Msk
+#define IAC_IER4_IAIE141_Pos          (13U)
+#define IAC_IER4_IAIE141_Msk          (0x1UL << IAC_IER4_IAIE141_Pos)            /*!< 0x00002000 */
+#define IAC_IER4_IAIE141              IAC_IER4_IAIE141_Msk
+#define IAC_IER4_IAIE142_Pos          (14U)
+#define IAC_IER4_IAIE142_Msk          (0x1UL << IAC_IER4_IAIE142_Pos)            /*!< 0x00004000 */
+#define IAC_IER4_IAIE142              IAC_IER4_IAIE142_Msk
+#define IAC_IER4_IAIE143_Pos          (15U)
+#define IAC_IER4_IAIE143_Msk          (0x1UL << IAC_IER4_IAIE143_Pos)            /*!< 0x00008000 */
+#define IAC_IER4_IAIE143              IAC_IER4_IAIE143_Msk
+#define IAC_IER4_IAIE144_Pos          (16U)
+#define IAC_IER4_IAIE144_Msk          (0x1UL << IAC_IER4_IAIE144_Pos)            /*!< 0x00010000 */
+#define IAC_IER4_IAIE144              IAC_IER4_IAIE144_Msk
+#define IAC_IER4_IAIE145_Pos          (17U)
+#define IAC_IER4_IAIE145_Msk          (0x1UL << IAC_IER4_IAIE145_Pos)            /*!< 0x00020000 */
+#define IAC_IER4_IAIE145              IAC_IER4_IAIE145_Msk
+#define IAC_IER4_IAIE146_Pos          (18U)
+#define IAC_IER4_IAIE146_Msk          (0x1UL << IAC_IER4_IAIE146_Pos)            /*!< 0x00040000 */
+#define IAC_IER4_IAIE146              IAC_IER4_IAIE146_Msk
+#define IAC_IER4_IAIE147_Pos          (19U)
+#define IAC_IER4_IAIE147_Msk          (0x1UL << IAC_IER4_IAIE147_Pos)            /*!< 0x00080000 */
+#define IAC_IER4_IAIE147              IAC_IER4_IAIE147_Msk
+#define IAC_IER4_IAIE149_Pos          (21U)
+#define IAC_IER4_IAIE149_Msk          (0x1UL << IAC_IER4_IAIE149_Pos)            /*!< 0x00200000 */
+#define IAC_IER4_IAIE149              IAC_IER4_IAIE149_Msk
+#define IAC_IER4_IAIE150_Pos          (22U)
+#define IAC_IER4_IAIE150_Msk          (0x1UL << IAC_IER4_IAIE150_Pos)            /*!< 0x00400000 */
+#define IAC_IER4_IAIE150              IAC_IER4_IAIE150_Msk
+#define IAC_IER4_IAIE151_Pos          (23U)
+#define IAC_IER4_IAIE151_Msk          (0x1UL << IAC_IER4_IAIE151_Pos)            /*!< 0x00800000 */
+#define IAC_IER4_IAIE151              IAC_IER4_IAIE151_Msk
+#define IAC_IER4_IAIE152_Pos          (24U)
+#define IAC_IER4_IAIE152_Msk          (0x1UL << IAC_IER4_IAIE152_Pos)            /*!< 0x01000000 */
+#define IAC_IER4_IAIE152              IAC_IER4_IAIE152_Msk
+#define IAC_IER4_IAIE153_Pos          (25U)
+#define IAC_IER4_IAIE153_Msk          (0x1UL << IAC_IER4_IAIE153_Pos)            /*!< 0x02000000 */
+#define IAC_IER4_IAIE153              IAC_IER4_IAIE153_Msk
+#define IAC_IER4_IAIE155_Pos          (27U)
+#define IAC_IER4_IAIE155_Msk          (0x1UL << IAC_IER4_IAIE155_Pos)            /*!< 0x08000000 */
+#define IAC_IER4_IAIE155              IAC_IER4_IAIE155_Msk
+#define IAC_IER4_IAIE156_Pos          (28U)
+#define IAC_IER4_IAIE156_Msk          (0x1UL << IAC_IER4_IAIE156_Pos)            /*!< 0x10000000 */
+#define IAC_IER4_IAIE156              IAC_IER4_IAIE156_Msk
+#define IAC_IER4_IAIE157_Pos          (29U)
+#define IAC_IER4_IAIE157_Msk          (0x1UL << IAC_IER4_IAIE157_Pos)            /*!< 0x20000000 */
+#define IAC_IER4_IAIE157              IAC_IER4_IAIE157_Msk
+
+/*******************  Bits definition for IAC_ISR0 register *******************/
+#define IAC_ISR0_IAF0_Pos             (0U)
+#define IAC_ISR0_IAF0_Msk             (0x1UL << IAC_ISR0_IAF0_Pos)               /*!< 0x00000001 */
+#define IAC_ISR0_IAF0                 IAC_ISR0_IAF0_Msk
+#define IAC_ISR0_IAF1_Pos             (1U)
+#define IAC_ISR0_IAF1_Msk             (0x1UL << IAC_ISR0_IAF1_Pos)               /*!< 0x00000002 */
+#define IAC_ISR0_IAF1                 IAC_ISR0_IAF1_Msk
+#define IAC_ISR0_IAF2_Pos             (2U)
+#define IAC_ISR0_IAF2_Msk             (0x1UL << IAC_ISR0_IAF2_Pos)               /*!< 0x00000004 */
+#define IAC_ISR0_IAF2                 IAC_ISR0_IAF2_Msk
+#define IAC_ISR0_IAF3_Pos             (3U)
+#define IAC_ISR0_IAF3_Msk             (0x1UL << IAC_ISR0_IAF3_Pos)               /*!< 0x00000008 */
+#define IAC_ISR0_IAF3                 IAC_ISR0_IAF3_Msk
+#define IAC_ISR0_IAF4_Pos             (4U)
+#define IAC_ISR0_IAF4_Msk             (0x1UL << IAC_ISR0_IAF4_Pos)               /*!< 0x00000010 */
+#define IAC_ISR0_IAF4                 IAC_ISR0_IAF4_Msk
+#define IAC_ISR0_IAF5_Pos             (5U)
+#define IAC_ISR0_IAF5_Msk             (0x1UL << IAC_ISR0_IAF5_Pos)               /*!< 0x00000020 */
+#define IAC_ISR0_IAF5                 IAC_ISR0_IAF5_Msk
+#define IAC_ISR0_IAF6_Pos             (6U)
+#define IAC_ISR0_IAF6_Msk             (0x1UL << IAC_ISR0_IAF6_Pos)               /*!< 0x00000040 */
+#define IAC_ISR0_IAF6                 IAC_ISR0_IAF6_Msk
+#define IAC_ISR0_IAF8_Pos             (8U)
+#define IAC_ISR0_IAF8_Msk             (0x1UL << IAC_ISR0_IAF8_Pos)               /*!< 0x00000100 */
+#define IAC_ISR0_IAF8                 IAC_ISR0_IAF8_Msk
+#define IAC_ISR0_IAF9_Pos             (9U)
+#define IAC_ISR0_IAF9_Msk             (0x1UL << IAC_ISR0_IAF9_Pos)               /*!< 0x00000200 */
+#define IAC_ISR0_IAF9                 IAC_ISR0_IAF9_Msk
+#define IAC_ISR0_IAF10_Pos            (10U)
+#define IAC_ISR0_IAF10_Msk            (0x1UL << IAC_ISR0_IAF10_Pos)              /*!< 0x00000400 */
+#define IAC_ISR0_IAF10                IAC_ISR0_IAF10_Msk
+#define IAC_ISR0_IAF11_Pos            (11U)
+#define IAC_ISR0_IAF11_Msk            (0x1UL << IAC_ISR0_IAF11_Pos)              /*!< 0x00000800 */
+#define IAC_ISR0_IAF11                IAC_ISR0_IAF11_Msk
+#define IAC_ISR0_IAF12_Pos            (12U)
+#define IAC_ISR0_IAF12_Msk            (0x1UL << IAC_ISR0_IAF12_Pos)              /*!< 0x00001000 */
+#define IAC_ISR0_IAF12                IAC_ISR0_IAF12_Msk
+#define IAC_ISR0_IAF13_Pos            (13U)
+#define IAC_ISR0_IAF13_Msk            (0x1UL << IAC_ISR0_IAF13_Pos)              /*!< 0x00002000 */
+#define IAC_ISR0_IAF13                IAC_ISR0_IAF13_Msk
+#define IAC_ISR0_IAF14_Pos            (14U)
+#define IAC_ISR0_IAF14_Msk            (0x1UL << IAC_ISR0_IAF14_Pos)              /*!< 0x00004000 */
+#define IAC_ISR0_IAF14                IAC_ISR0_IAF14_Msk
+#define IAC_ISR0_IAF15_Pos            (15U)
+#define IAC_ISR0_IAF15_Msk            (0x1UL << IAC_ISR0_IAF15_Pos)              /*!< 0x00008000 */
+#define IAC_ISR0_IAF15                IAC_ISR0_IAF15_Msk
+#define IAC_ISR0_IAF16_Pos            (16U)
+#define IAC_ISR0_IAF16_Msk            (0x1UL << IAC_ISR0_IAF16_Pos)              /*!< 0x00010000 */
+#define IAC_ISR0_IAF16                IAC_ISR0_IAF16_Msk
+#define IAC_ISR0_IAF17_Pos            (17U)
+#define IAC_ISR0_IAF17_Msk            (0x1UL << IAC_ISR0_IAF17_Pos)              /*!< 0x00020000 */
+#define IAC_ISR0_IAF17                IAC_ISR0_IAF17_Msk
+#define IAC_ISR0_IAF18_Pos            (18U)
+#define IAC_ISR0_IAF18_Msk            (0x1UL << IAC_ISR0_IAF18_Pos)              /*!< 0x00040000 */
+#define IAC_ISR0_IAF18                IAC_ISR0_IAF18_Msk
+#define IAC_ISR0_IAF19_Pos            (19U)
+#define IAC_ISR0_IAF19_Msk            (0x1UL << IAC_ISR0_IAF19_Pos)              /*!< 0x00080000 */
+#define IAC_ISR0_IAF19                IAC_ISR0_IAF19_Msk
+#define IAC_ISR0_IAF20_Pos            (20U)
+#define IAC_ISR0_IAF20_Msk            (0x1UL << IAC_ISR0_IAF20_Pos)              /*!< 0x00100000 */
+#define IAC_ISR0_IAF20                IAC_ISR0_IAF20_Msk
+#define IAC_ISR0_IAF21_Pos            (21U)
+#define IAC_ISR0_IAF21_Msk            (0x1UL << IAC_ISR0_IAF21_Pos)              /*!< 0x00200000 */
+#define IAC_ISR0_IAF21                IAC_ISR0_IAF21_Msk
+#define IAC_ISR0_IAF22_Pos            (22U)
+#define IAC_ISR0_IAF22_Msk            (0x1UL << IAC_ISR0_IAF22_Pos)              /*!< 0x00400000 */
+#define IAC_ISR0_IAF22                IAC_ISR0_IAF22_Msk
+#define IAC_ISR0_IAF23_Pos            (23U)
+#define IAC_ISR0_IAF23_Msk            (0x1UL << IAC_ISR0_IAF23_Pos)              /*!< 0x00800000 */
+#define IAC_ISR0_IAF23                IAC_ISR0_IAF23_Msk
+#define IAC_ISR0_IAF24_Pos            (24U)
+#define IAC_ISR0_IAF24_Msk            (0x1UL << IAC_ISR0_IAF24_Pos)              /*!< 0x01000000 */
+#define IAC_ISR0_IAF24                IAC_ISR0_IAF24_Msk
+#define IAC_ISR0_IAF25_Pos            (25U)
+#define IAC_ISR0_IAF25_Msk            (0x1UL << IAC_ISR0_IAF25_Pos)              /*!< 0x02000000 */
+#define IAC_ISR0_IAF25                IAC_ISR0_IAF25_Msk
+#define IAC_ISR0_IAF26_Pos            (26U)
+#define IAC_ISR0_IAF26_Msk            (0x1UL << IAC_ISR0_IAF26_Pos)              /*!< 0x04000000 */
+#define IAC_ISR0_IAF26                IAC_ISR0_IAF26_Msk
+#define IAC_ISR0_IAF27_Pos            (27U)
+#define IAC_ISR0_IAF27_Msk            (0x1UL << IAC_ISR0_IAF27_Pos)              /*!< 0x08000000 */
+#define IAC_ISR0_IAF27                IAC_ISR0_IAF27_Msk
+#define IAC_ISR0_IAF28_Pos            (28U)
+#define IAC_ISR0_IAF28_Msk            (0x1UL << IAC_ISR0_IAF28_Pos)              /*!< 0x10000000 */
+#define IAC_ISR0_IAF28                IAC_ISR0_IAF28_Msk
+#define IAC_ISR0_IAF29_Pos            (29U)
+#define IAC_ISR0_IAF29_Msk            (0x1UL << IAC_ISR0_IAF29_Pos)              /*!< 0x20000000 */
+#define IAC_ISR0_IAF29                IAC_ISR0_IAF29_Msk
+#define IAC_ISR0_IAF30_Pos            (30U)
+#define IAC_ISR0_IAF30_Msk            (0x1UL << IAC_ISR0_IAF30_Pos)              /*!< 0x40000000 */
+#define IAC_ISR0_IAF30                IAC_ISR0_IAF30_Msk
+#define IAC_ISR0_IAF31_Pos            (31U)
+#define IAC_ISR0_IAF31_Msk            (0x1UL << IAC_ISR0_IAF31_Pos)              /*!< 0x80000000 */
+#define IAC_ISR0_IAF31                IAC_ISR0_IAF31_Msk
+
+/*******************  Bits definition for IAC_ISR1 register *******************/
+#define IAC_ISR1_IAF32_Pos            (0U)
+#define IAC_ISR1_IAF32_Msk            (0x1UL << IAC_ISR1_IAF32_Pos)              /*!< 0x00000001 */
+#define IAC_ISR1_IAF32                IAC_ISR1_IAF32_Msk
+#define IAC_ISR1_IAF33_Pos            (1U)
+#define IAC_ISR1_IAF33_Msk            (0x1UL << IAC_ISR1_IAF33_Pos)              /*!< 0x00000002 */
+#define IAC_ISR1_IAF33                IAC_ISR1_IAF33_Msk
+#define IAC_ISR1_IAF34_Pos            (2U)
+#define IAC_ISR1_IAF34_Msk            (0x1UL << IAC_ISR1_IAF34_Pos)              /*!< 0x00000004 */
+#define IAC_ISR1_IAF34                IAC_ISR1_IAF34_Msk
+#define IAC_ISR1_IAF35_Pos            (3U)
+#define IAC_ISR1_IAF35_Msk            (0x1UL << IAC_ISR1_IAF35_Pos)              /*!< 0x00000008 */
+#define IAC_ISR1_IAF35                IAC_ISR1_IAF35_Msk
+#define IAC_ISR1_IAF36_Pos            (4U)
+#define IAC_ISR1_IAF36_Msk            (0x1UL << IAC_ISR1_IAF36_Pos)              /*!< 0x00000010 */
+#define IAC_ISR1_IAF36                IAC_ISR1_IAF36_Msk
+#define IAC_ISR1_IAF37_Pos            (5U)
+#define IAC_ISR1_IAF37_Msk            (0x1UL << IAC_ISR1_IAF37_Pos)              /*!< 0x00000020 */
+#define IAC_ISR1_IAF37                IAC_ISR1_IAF37_Msk
+#define IAC_ISR1_IAF38_Pos            (6U)
+#define IAC_ISR1_IAF38_Msk            (0x1UL << IAC_ISR1_IAF38_Pos)              /*!< 0x00000040 */
+#define IAC_ISR1_IAF38                IAC_ISR1_IAF38_Msk
+#define IAC_ISR1_IAF39_Pos            (7U)
+#define IAC_ISR1_IAF39_Msk            (0x1UL << IAC_ISR1_IAF39_Pos)              /*!< 0x00000080 */
+#define IAC_ISR1_IAF39                IAC_ISR1_IAF39_Msk
+#define IAC_ISR1_IAF40_Pos            (8U)
+#define IAC_ISR1_IAF40_Msk            (0x1UL << IAC_ISR1_IAF40_Pos)              /*!< 0x00000100 */
+#define IAC_ISR1_IAF40                IAC_ISR1_IAF40_Msk
+#define IAC_ISR1_IAF41_Pos            (9U)
+#define IAC_ISR1_IAF41_Msk            (0x1UL << IAC_ISR1_IAF41_Pos)              /*!< 0x00000200 */
+#define IAC_ISR1_IAF41                IAC_ISR1_IAF41_Msk
+#define IAC_ISR1_IAF42_Pos            (10U)
+#define IAC_ISR1_IAF42_Msk            (0x1UL << IAC_ISR1_IAF42_Pos)              /*!< 0x00000400 */
+#define IAC_ISR1_IAF42                IAC_ISR1_IAF42_Msk
+#define IAC_ISR1_IAF43_Pos            (11U)
+#define IAC_ISR1_IAF43_Msk            (0x1UL << IAC_ISR1_IAF43_Pos)              /*!< 0x00000800 */
+#define IAC_ISR1_IAF43                IAC_ISR1_IAF43_Msk
+#define IAC_ISR1_IAF44_Pos            (12U)
+#define IAC_ISR1_IAF44_Msk            (0x1UL << IAC_ISR1_IAF44_Pos)              /*!< 0x00001000 */
+#define IAC_ISR1_IAF44                IAC_ISR1_IAF44_Msk
+#define IAC_ISR1_IAF45_Pos            (13U)
+#define IAC_ISR1_IAF45_Msk            (0x1UL << IAC_ISR1_IAF45_Pos)              /*!< 0x00002000 */
+#define IAC_ISR1_IAF45                IAC_ISR1_IAF45_Msk
+#define IAC_ISR1_IAF46_Pos            (14U)
+#define IAC_ISR1_IAF46_Msk            (0x1UL << IAC_ISR1_IAF46_Pos)              /*!< 0x00004000 */
+#define IAC_ISR1_IAF46                IAC_ISR1_IAF46_Msk
+#define IAC_ISR1_IAF47_Pos            (15U)
+#define IAC_ISR1_IAF47_Msk            (0x1UL << IAC_ISR1_IAF47_Pos)              /*!< 0x00008000 */
+#define IAC_ISR1_IAF47                IAC_ISR1_IAF47_Msk
+#define IAC_ISR1_IAF48_Pos            (16U)
+#define IAC_ISR1_IAF48_Msk            (0x1UL << IAC_ISR1_IAF48_Pos)              /*!< 0x00010000 */
+#define IAC_ISR1_IAF48                IAC_ISR1_IAF48_Msk
+#define IAC_ISR1_IAF49_Pos            (17U)
+#define IAC_ISR1_IAF49_Msk            (0x1UL << IAC_ISR1_IAF49_Pos)              /*!< 0x00020000 */
+#define IAC_ISR1_IAF49                IAC_ISR1_IAF49_Msk
+#define IAC_ISR1_IAF50_Pos            (18U)
+#define IAC_ISR1_IAF50_Msk            (0x1UL << IAC_ISR1_IAF50_Pos)              /*!< 0x00040000 */
+#define IAC_ISR1_IAF50                IAC_ISR1_IAF50_Msk
+#define IAC_ISR1_IAF51_Pos            (19U)
+#define IAC_ISR1_IAF51_Msk            (0x1UL << IAC_ISR1_IAF51_Pos)              /*!< 0x00080000 */
+#define IAC_ISR1_IAF51                IAC_ISR1_IAF51_Msk
+#define IAC_ISR1_IAF52_Pos            (20U)
+#define IAC_ISR1_IAF52_Msk            (0x1UL << IAC_ISR1_IAF52_Pos)              /*!< 0x00100000 */
+#define IAC_ISR1_IAF52                IAC_ISR1_IAF52_Msk
+#define IAC_ISR1_IAF53_Pos            (21U)
+#define IAC_ISR1_IAF53_Msk            (0x1UL << IAC_ISR1_IAF53_Pos)              /*!< 0x00200000 */
+#define IAC_ISR1_IAF53                IAC_ISR1_IAF53_Msk
+#define IAC_ISR1_IAF54_Pos            (22U)
+#define IAC_ISR1_IAF54_Msk            (0x1UL << IAC_ISR1_IAF54_Pos)              /*!< 0x00400000 */
+#define IAC_ISR1_IAF54                IAC_ISR1_IAF54_Msk
+#define IAC_ISR1_IAF55_Pos            (23U)
+#define IAC_ISR1_IAF55_Msk            (0x1UL << IAC_ISR1_IAF55_Pos)              /*!< 0x00800000 */
+#define IAC_ISR1_IAF55                IAC_ISR1_IAF55_Msk
+#define IAC_ISR1_IAF56_Pos            (24U)
+#define IAC_ISR1_IAF56_Msk            (0x1UL << IAC_ISR1_IAF56_Pos)              /*!< 0x01000000 */
+#define IAC_ISR1_IAF56                IAC_ISR1_IAF56_Msk
+#define IAC_ISR1_IAF57_Pos            (25U)
+#define IAC_ISR1_IAF57_Msk            (0x1UL << IAC_ISR1_IAF57_Pos)              /*!< 0x02000000 */
+#define IAC_ISR1_IAF57                IAC_ISR1_IAF57_Msk
+#define IAC_ISR1_IAF58_Pos            (26U)
+#define IAC_ISR1_IAF58_Msk            (0x1UL << IAC_ISR1_IAF58_Pos)              /*!< 0x04000000 */
+#define IAC_ISR1_IAF58                IAC_ISR1_IAF58_Msk
+#define IAC_ISR1_IAF60_Pos            (28U)
+#define IAC_ISR1_IAF60_Msk            (0x1UL << IAC_ISR1_IAF60_Pos)              /*!< 0x10000000 */
+#define IAC_ISR1_IAF60                IAC_ISR1_IAF60_Msk
+#define IAC_ISR1_IAF61_Pos            (29U)
+#define IAC_ISR1_IAF61_Msk            (0x1UL << IAC_ISR1_IAF61_Pos)              /*!< 0x20000000 */
+#define IAC_ISR1_IAF61                IAC_ISR1_IAF61_Msk
+#define IAC_ISR1_IAF62_Pos            (30U)
+#define IAC_ISR1_IAF62_Msk            (0x1UL << IAC_ISR1_IAF62_Pos)              /*!< 0x40000000 */
+#define IAC_ISR1_IAF62                IAC_ISR1_IAF62_Msk
+
+/*******************  Bits definition for IAC_ISR2 register *******************/
+#define IAC_ISR2_IAF64_Pos            (0U)
+#define IAC_ISR2_IAF64_Msk            (0x1UL << IAC_ISR2_IAF64_Pos)              /*!< 0x00000001 */
+#define IAC_ISR2_IAF64                IAC_ISR2_IAF64_Msk
+#define IAC_ISR2_IAF65_Pos            (1U)
+#define IAC_ISR2_IAF65_Msk            (0x1UL << IAC_ISR2_IAF65_Pos)              /*!< 0x00000002 */
+#define IAC_ISR2_IAF65                IAC_ISR2_IAF65_Msk
+#define IAC_ISR2_IAF67_Pos            (3U)
+#define IAC_ISR2_IAF67_Msk            (0x1UL << IAC_ISR2_IAF67_Pos)              /*!< 0x00000008 */
+#define IAC_ISR2_IAF67                IAC_ISR2_IAF67_Msk
+#define IAC_ISR2_IAF68_Pos            (4U)
+#define IAC_ISR2_IAF68_Msk            (0x1UL << IAC_ISR2_IAF68_Pos)              /*!< 0x00000010 */
+#define IAC_ISR2_IAF68                IAC_ISR2_IAF68_Msk
+#define IAC_ISR2_IAF69_Pos            (5U)
+#define IAC_ISR2_IAF69_Msk            (0x1UL << IAC_ISR2_IAF69_Pos)              /*!< 0x00000020 */
+#define IAC_ISR2_IAF69                IAC_ISR2_IAF69_Msk
+#define IAC_ISR2_IAF76_Pos            (12U)
+#define IAC_ISR2_IAF76_Msk            (0x1UL << IAC_ISR2_IAF76_Pos)              /*!< 0x00001000 */
+#define IAC_ISR2_IAF76                IAC_ISR2_IAF76_Msk
+#define IAC_ISR2_IAF77_Pos            (13U)
+#define IAC_ISR2_IAF77_Msk            (0x1UL << IAC_ISR2_IAF77_Pos)              /*!< 0x00002000 */
+#define IAC_ISR2_IAF77                IAC_ISR2_IAF77_Msk
+#define IAC_ISR2_IAF78_Pos            (14U)
+#define IAC_ISR2_IAF78_Msk            (0x1UL << IAC_ISR2_IAF78_Pos)              /*!< 0x00004000 */
+#define IAC_ISR2_IAF78                IAC_ISR2_IAF78_Msk
+#define IAC_ISR2_IAF79_Pos            (15U)
+#define IAC_ISR2_IAF79_Msk            (0x1UL << IAC_ISR2_IAF79_Pos)              /*!< 0x00008000 */
+#define IAC_ISR2_IAF79                IAC_ISR2_IAF79_Msk
+#define IAC_ISR2_IAF80_Pos            (16U)
+#define IAC_ISR2_IAF80_Msk            (0x1UL << IAC_ISR2_IAF80_Pos)              /*!< 0x00010000 */
+#define IAC_ISR2_IAF80                IAC_ISR2_IAF80_Msk
+#define IAC_ISR2_IAF81_Pos            (17U)
+#define IAC_ISR2_IAF81_Msk            (0x1UL << IAC_ISR2_IAF81_Pos)              /*!< 0x00020000 */
+#define IAC_ISR2_IAF81                IAC_ISR2_IAF81_Msk
+#define IAC_ISR2_IAF82_Pos            (18U)
+#define IAC_ISR2_IAF82_Msk            (0x1UL << IAC_ISR2_IAF82_Pos)              /*!< 0x00040000 */
+#define IAC_ISR2_IAF82                IAC_ISR2_IAF82_Msk
+#define IAC_ISR2_IAF83_Pos            (19U)
+#define IAC_ISR2_IAF83_Msk            (0x1UL << IAC_ISR2_IAF83_Pos)              /*!< 0x00080000 */
+#define IAC_ISR2_IAF83                IAC_ISR2_IAF83_Msk
+#define IAC_ISR2_IAF84_Pos            (20U)
+#define IAC_ISR2_IAF84_Msk            (0x1UL << IAC_ISR2_IAF84_Pos)              /*!< 0x00100000 */
+#define IAC_ISR2_IAF84                IAC_ISR2_IAF84_Msk
+#define IAC_ISR2_IAF86_Pos            (22U)
+#define IAC_ISR2_IAF86_Msk            (0x1UL << IAC_ISR2_IAF86_Pos)              /*!< 0x00400000 */
+#define IAC_ISR2_IAF86                IAC_ISR2_IAF86_Msk
+#define IAC_ISR2_IAF87_Pos            (23U)
+#define IAC_ISR2_IAF87_Msk            (0x1UL << IAC_ISR2_IAF87_Pos)              /*!< 0x00800000 */
+#define IAC_ISR2_IAF87                IAC_ISR2_IAF87_Msk
+#define IAC_ISR2_IAF88_Pos            (24U)
+#define IAC_ISR2_IAF88_Msk            (0x1UL << IAC_ISR2_IAF88_Pos)              /*!< 0x01000000 */
+#define IAC_ISR2_IAF88                IAC_ISR2_IAF88_Msk
+#define IAC_ISR2_IAF89_Pos            (25U)
+#define IAC_ISR2_IAF89_Msk            (0x1UL << IAC_ISR2_IAF89_Pos)              /*!< 0x02000000 */
+#define IAC_ISR2_IAF89                IAC_ISR2_IAF89_Msk
+#define IAC_ISR2_IAF90_Pos            (26U)
+#define IAC_ISR2_IAF90_Msk            (0x1UL << IAC_ISR2_IAF90_Pos)              /*!< 0x04000000 */
+#define IAC_ISR2_IAF90                IAC_ISR2_IAF90_Msk
+#define IAC_ISR2_IAF92_Pos            (28U)
+#define IAC_ISR2_IAF92_Msk            (0x1UL << IAC_ISR2_IAF92_Pos)              /*!< 0x10000000 */
+#define IAC_ISR2_IAF92                IAC_ISR2_IAF92_Msk
+#define IAC_ISR2_IAF93_Pos            (29U)
+#define IAC_ISR2_IAF93_Msk            (0x1UL << IAC_ISR2_IAF93_Pos)              /*!< 0x20000000 */
+#define IAC_ISR2_IAF93                IAC_ISR2_IAF93_Msk
+#define IAC_ISR2_IAF94_Pos            (30U)
+#define IAC_ISR2_IAF94_Msk            (0x1UL << IAC_ISR2_IAF94_Pos)              /*!< 0x40000000 */
+#define IAC_ISR2_IAF94                IAC_ISR2_IAF94_Msk
+#define IAC_ISR2_IAF95_Pos            (31U)
+#define IAC_ISR2_IAF95_Msk            (0x1UL << IAC_ISR2_IAF95_Pos)              /*!< 0x80000000 */
+#define IAC_ISR2_IAF95                IAC_ISR2_IAF95_Msk
+
+/*******************  Bits definition for IAC_ISR3 register *******************/
+#define IAC_ISR3_IAF96_Pos            (0U)
+#define IAC_ISR3_IAF96_Msk            (0x1UL << IAC_ISR3_IAF96_Pos)              /*!< 0x00000001 */
+#define IAC_ISR3_IAF96                IAC_ISR3_IAF96_Msk
+#define IAC_ISR3_IAF97_Pos            (1U)
+#define IAC_ISR3_IAF97_Msk            (0x1UL << IAC_ISR3_IAF97_Pos)              /*!< 0x00000002 */
+#define IAC_ISR3_IAF97                IAC_ISR3_IAF97_Msk
+#define IAC_ISR3_IAF98_Pos            (2U)
+#define IAC_ISR3_IAF98_Msk            (0x1UL << IAC_ISR3_IAF98_Pos)              /*!< 0x00000004 */
+#define IAC_ISR3_IAF98                IAC_ISR3_IAF98_Msk
+#define IAC_ISR3_IAF99_Pos            (3U)
+#define IAC_ISR3_IAF99_Msk            (0x1UL << IAC_ISR3_IAF99_Pos)              /*!< 0x00000008 */
+#define IAC_ISR3_IAF99                IAC_ISR3_IAF99_Msk
+#define IAC_ISR3_IAF100_Pos           (4U)
+#define IAC_ISR3_IAF100_Msk           (0x1UL << IAC_ISR3_IAF100_Pos)             /*!< 0x00000010 */
+#define IAC_ISR3_IAF100               IAC_ISR3_IAF100_Msk
+#define IAC_ISR3_IAF101_Pos           (5U)
+#define IAC_ISR3_IAF101_Msk           (0x1UL << IAC_ISR3_IAF101_Pos)             /*!< 0x00000020 */
+#define IAC_ISR3_IAF101               IAC_ISR3_IAF101_Msk
+#define IAC_ISR3_IAF102_Pos           (6U)
+#define IAC_ISR3_IAF102_Msk           (0x1UL << IAC_ISR3_IAF102_Pos)             /*!< 0x00000040 */
+#define IAC_ISR3_IAF102               IAC_ISR3_IAF102_Msk
+#define IAC_ISR3_IAF103_Pos           (7U)
+#define IAC_ISR3_IAF103_Msk           (0x1UL << IAC_ISR3_IAF103_Pos)             /*!< 0x00000080 */
+#define IAC_ISR3_IAF103               IAC_ISR3_IAF103_Msk
+#define IAC_ISR3_IAF104_Pos           (8U)
+#define IAC_ISR3_IAF104_Msk           (0x1UL << IAC_ISR3_IAF104_Pos)             /*!< 0x00000100 */
+#define IAC_ISR3_IAF104               IAC_ISR3_IAF104_Msk
+#define IAC_ISR3_IAF106_Pos           (10U)
+#define IAC_ISR3_IAF106_Msk           (0x1UL << IAC_ISR3_IAF106_Pos)             /*!< 0x00000400 */
+#define IAC_ISR3_IAF106               IAC_ISR3_IAF106_Msk
+
+/*******************  Bits definition for IAC_ISR4 register *******************/
+#define IAC_ISR4_IAF128_Pos           (0U)
+#define IAC_ISR4_IAF128_Msk           (0x1UL << IAC_ISR4_IAF128_Pos)             /*!< 0x00000001 */
+#define IAC_ISR4_IAF128               IAC_ISR4_IAF128_Msk
+#define IAC_ISR4_IAF129_Pos           (1U)
+#define IAC_ISR4_IAF129_Msk           (0x1UL << IAC_ISR4_IAF129_Pos)             /*!< 0x00000002 */
+#define IAC_ISR4_IAF129               IAC_ISR4_IAF129_Msk
+#define IAC_ISR4_IAF130_Pos           (2U)
+#define IAC_ISR4_IAF130_Msk           (0x1UL << IAC_ISR4_IAF130_Pos)             /*!< 0x00000004 */
+#define IAC_ISR4_IAF130               IAC_ISR4_IAF130_Msk
+#define IAC_ISR4_IAF131_Pos           (3U)
+#define IAC_ISR4_IAF131_Msk           (0x1UL << IAC_ISR4_IAF131_Pos)             /*!< 0x00000008 */
+#define IAC_ISR4_IAF131               IAC_ISR4_IAF131_Msk
+#define IAC_ISR4_IAF133_Pos           (5U)
+#define IAC_ISR4_IAF133_Msk           (0x1UL << IAC_ISR4_IAF133_Pos)             /*!< 0x00000020 */
+#define IAC_ISR4_IAF133               IAC_ISR4_IAF133_Msk
+#define IAC_ISR4_IAF134_Pos           (6U)
+#define IAC_ISR4_IAF134_Msk           (0x1UL << IAC_ISR4_IAF134_Pos)             /*!< 0x00000040 */
+#define IAC_ISR4_IAF134               IAC_ISR4_IAF134_Msk
+#define IAC_ISR4_IAF135_Pos           (7U)
+#define IAC_ISR4_IAF135_Msk           (0x1UL << IAC_ISR4_IAF135_Pos)             /*!< 0x00000080 */
+#define IAC_ISR4_IAF135               IAC_ISR4_IAF135_Msk
+#define IAC_ISR4_IAF136_Pos           (8U)
+#define IAC_ISR4_IAF136_Msk           (0x1UL << IAC_ISR4_IAF136_Pos)             /*!< 0x00000100 */
+#define IAC_ISR4_IAF136               IAC_ISR4_IAF136_Msk
+#define IAC_ISR4_IAF137_Pos           (9U)
+#define IAC_ISR4_IAF137_Msk           (0x1UL << IAC_ISR4_IAF137_Pos)             /*!< 0x00000200 */
+#define IAC_ISR4_IAF137               IAC_ISR4_IAF137_Msk
+#define IAC_ISR4_IAF138_Pos           (10U)
+#define IAC_ISR4_IAF138_Msk           (0x1UL << IAC_ISR4_IAF138_Pos)             /*!< 0x00000400 */
+#define IAC_ISR4_IAF138               IAC_ISR4_IAF138_Msk
+#define IAC_ISR4_IAF139_Pos           (11U)
+#define IAC_ISR4_IAF139_Msk           (0x1UL << IAC_ISR4_IAF139_Pos)             /*!< 0x00000800 */
+#define IAC_ISR4_IAF139               IAC_ISR4_IAF139_Msk
+#define IAC_ISR4_IAF140_Pos           (12U)
+#define IAC_ISR4_IAF140_Msk           (0x1UL << IAC_ISR4_IAF140_Pos)             /*!< 0x00001000 */
+#define IAC_ISR4_IAF140               IAC_ISR4_IAF140_Msk
+#define IAC_ISR4_IAF141_Pos           (13U)
+#define IAC_ISR4_IAF141_Msk           (0x1UL << IAC_ISR4_IAF141_Pos)             /*!< 0x00002000 */
+#define IAC_ISR4_IAF141               IAC_ISR4_IAF141_Msk
+#define IAC_ISR4_IAF142_Pos           (14U)
+#define IAC_ISR4_IAF142_Msk           (0x1UL << IAC_ISR4_IAF142_Pos)             /*!< 0x00004000 */
+#define IAC_ISR4_IAF142               IAC_ISR4_IAF142_Msk
+#define IAC_ISR4_IAF143_Pos           (15U)
+#define IAC_ISR4_IAF143_Msk           (0x1UL << IAC_ISR4_IAF143_Pos)             /*!< 0x00008000 */
+#define IAC_ISR4_IAF143               IAC_ISR4_IAF143_Msk
+#define IAC_ISR4_IAF144_Pos           (16U)
+#define IAC_ISR4_IAF144_Msk           (0x1UL << IAC_ISR4_IAF144_Pos)             /*!< 0x00010000 */
+#define IAC_ISR4_IAF144               IAC_ISR4_IAF144_Msk
+#define IAC_ISR4_IAF145_Pos           (17U)
+#define IAC_ISR4_IAF145_Msk           (0x1UL << IAC_ISR4_IAF145_Pos)             /*!< 0x00020000 */
+#define IAC_ISR4_IAF145               IAC_ISR4_IAF145_Msk
+#define IAC_ISR4_IAF146_Pos           (18U)
+#define IAC_ISR4_IAF146_Msk           (0x1UL << IAC_ISR4_IAF146_Pos)             /*!< 0x00040000 */
+#define IAC_ISR4_IAF146               IAC_ISR4_IAF146_Msk
+#define IAC_ISR4_IAF147_Pos           (19U)
+#define IAC_ISR4_IAF147_Msk           (0x1UL << IAC_ISR4_IAF147_Pos)             /*!< 0x00080000 */
+#define IAC_ISR4_IAF147               IAC_ISR4_IAF147_Msk
+#define IAC_ISR4_IAF149_Pos           (21U)
+#define IAC_ISR4_IAF149_Msk           (0x1UL << IAC_ISR4_IAF149_Pos)             /*!< 0x00200000 */
+#define IAC_ISR4_IAF149               IAC_ISR4_IAF149_Msk
+#define IAC_ISR4_IAF150_Pos           (22U)
+#define IAC_ISR4_IAF150_Msk           (0x1UL << IAC_ISR4_IAF150_Pos)             /*!< 0x00400000 */
+#define IAC_ISR4_IAF150               IAC_ISR4_IAF150_Msk
+#define IAC_ISR4_IAF151_Pos           (23U)
+#define IAC_ISR4_IAF151_Msk           (0x1UL << IAC_ISR4_IAF151_Pos)             /*!< 0x00800000 */
+#define IAC_ISR4_IAF151               IAC_ISR4_IAF151_Msk
+#define IAC_ISR4_IAF152_Pos           (24U)
+#define IAC_ISR4_IAF152_Msk           (0x1UL << IAC_ISR4_IAF152_Pos)             /*!< 0x01000000 */
+#define IAC_ISR4_IAF152               IAC_ISR4_IAF152_Msk
+#define IAC_ISR4_IAF153_Pos           (25U)
+#define IAC_ISR4_IAF153_Msk           (0x1UL << IAC_ISR4_IAF153_Pos)             /*!< 0x02000000 */
+#define IAC_ISR4_IAF153               IAC_ISR4_IAF153_Msk
+#define IAC_ISR4_IAF155_Pos           (27U)
+#define IAC_ISR4_IAF155_Msk           (0x1UL << IAC_ISR4_IAF155_Pos)             /*!< 0x08000000 */
+#define IAC_ISR4_IAF155               IAC_ISR4_IAF155_Msk
+#define IAC_ISR4_IAF156_Pos           (28U)
+#define IAC_ISR4_IAF156_Msk           (0x1UL << IAC_ISR4_IAF156_Pos)             /*!< 0x10000000 */
+#define IAC_ISR4_IAF156               IAC_ISR4_IAF156_Msk
+#define IAC_ISR4_IAF157_Pos           (29U)
+#define IAC_ISR4_IAF157_Msk           (0x1UL << IAC_ISR4_IAF157_Pos)             /*!< 0x20000000 */
+#define IAC_ISR4_IAF157               IAC_ISR4_IAF157_Msk
+
+/*******************  Bits definition for IAC_ICR0 register *******************/
+#define IAC_ICR0_IACF0_Pos            (0U)
+#define IAC_ICR0_IACF0_Msk            (0x1UL << IAC_ICR0_IACF0_Pos)               /*!< 0x00000001 */
+#define IAC_ICR0_IACF0                IAC_ICR0_IACF0_Msk
+#define IAC_ICR0_IACF1_Pos            (1U)
+#define IAC_ICR0_IACF1_Msk            (0x1UL << IAC_ICR0_IACF1_Pos)               /*!< 0x00000002 */
+#define IAC_ICR0_IACF1                IAC_ICR0_IACF1_Msk
+#define IAC_ICR0_IACF2_Pos            (2U)
+#define IAC_ICR0_IACF2_Msk            (0x1UL << IAC_ICR0_IACF2_Pos)               /*!< 0x00000004 */
+#define IAC_ICR0_IACF2                IAC_ICR0_IACF2_Msk
+#define IAC_ICR0_IACF3_Pos            (3U)
+#define IAC_ICR0_IACF3_Msk            (0x1UL << IAC_ICR0_IACF3_Pos)               /*!< 0x00000008 */
+#define IAC_ICR0_IACF3                IAC_ICR0_IACF3_Msk
+#define IAC_ICR0_IACF4_Pos            (4U)
+#define IAC_ICR0_IACF4_Msk            (0x1UL << IAC_ICR0_IACF4_Pos)               /*!< 0x00000010 */
+#define IAC_ICR0_IACF4                IAC_ICR0_IACF4_Msk
+#define IAC_ICR0_IACF5_Pos            (5U)
+#define IAC_ICR0_IACF5_Msk            (0x1UL << IAC_ICR0_IACF5_Pos)               /*!< 0x00000020 */
+#define IAC_ICR0_IACF5                IAC_ICR0_IACF5_Msk
+#define IAC_ICR0_IACF6_Pos            (6U)
+#define IAC_ICR0_IACF6_Msk            (0x1UL << IAC_ICR0_IACF6_Pos)               /*!< 0x00000040 */
+#define IAC_ICR0_IACF6                IAC_ICR0_IACF6_Msk
+#define IAC_ICR0_IACF8_Pos            (8U)
+#define IAC_ICR0_IACF8_Msk            (0x1UL << IAC_ICR0_IACF8_Pos)               /*!< 0x00000100 */
+#define IAC_ICR0_IACF8                IAC_ICR0_IACF8_Msk
+#define IAC_ICR0_IACF9_Pos            (9U)
+#define IAC_ICR0_IACF9_Msk            (0x1UL << IAC_ICR0_IACF9_Pos)               /*!< 0x00000200 */
+#define IAC_ICR0_IACF9                IAC_ICR0_IACF9_Msk
+#define IAC_ICR0_IACF10_Pos           (10U)
+#define IAC_ICR0_IACF10_Msk           (0x1UL << IAC_ICR0_IACF10_Pos)              /*!< 0x00000400 */
+#define IAC_ICR0_IACF10               IAC_ICR0_IACF10_Msk
+#define IAC_ICR0_IACF11_Pos           (11U)
+#define IAC_ICR0_IACF11_Msk           (0x1UL << IAC_ICR0_IACF11_Pos)              /*!< 0x00000800 */
+#define IAC_ICR0_IACF11               IAC_ICR0_IACF11_Msk
+#define IAC_ICR0_IACF12_Pos           (12U)
+#define IAC_ICR0_IACF12_Msk           (0x1UL << IAC_ICR0_IACF12_Pos)              /*!< 0x00001000 */
+#define IAC_ICR0_IACF12               IAC_ICR0_IACF12_Msk
+#define IAC_ICR0_IACF13_Pos           (13U)
+#define IAC_ICR0_IACF13_Msk           (0x1UL << IAC_ICR0_IACF13_Pos)              /*!< 0x00002000 */
+#define IAC_ICR0_IACF13               IAC_ICR0_IACF13_Msk
+#define IAC_ICR0_IACF14_Pos           (14U)
+#define IAC_ICR0_IACF14_Msk           (0x1UL << IAC_ICR0_IACF14_Pos)              /*!< 0x00004000 */
+#define IAC_ICR0_IACF14               IAC_ICR0_IACF14_Msk
+#define IAC_ICR0_IACF15_Pos           (15U)
+#define IAC_ICR0_IACF15_Msk           (0x1UL << IAC_ICR0_IACF15_Pos)              /*!< 0x00008000 */
+#define IAC_ICR0_IACF15               IAC_ICR0_IACF15_Msk
+#define IAC_ICR0_IACF16_Pos           (16U)
+#define IAC_ICR0_IACF16_Msk           (0x1UL << IAC_ICR0_IACF16_Pos)              /*!< 0x00010000 */
+#define IAC_ICR0_IACF16               IAC_ICR0_IACF16_Msk
+#define IAC_ICR0_IACF17_Pos           (17U)
+#define IAC_ICR0_IACF17_Msk           (0x1UL << IAC_ICR0_IACF17_Pos)              /*!< 0x00020000 */
+#define IAC_ICR0_IACF17               IAC_ICR0_IACF17_Msk
+#define IAC_ICR0_IACF18_Pos           (18U)
+#define IAC_ICR0_IACF18_Msk           (0x1UL << IAC_ICR0_IACF18_Pos)              /*!< 0x00040000 */
+#define IAC_ICR0_IACF18               IAC_ICR0_IACF18_Msk
+#define IAC_ICR0_IACF19_Pos           (19U)
+#define IAC_ICR0_IACF19_Msk           (0x1UL << IAC_ICR0_IACF19_Pos)              /*!< 0x00080000 */
+#define IAC_ICR0_IACF19               IAC_ICR0_IACF19_Msk
+#define IAC_ICR0_IACF20_Pos           (20U)
+#define IAC_ICR0_IACF20_Msk           (0x1UL << IAC_ICR0_IACF20_Pos)              /*!< 0x00100000 */
+#define IAC_ICR0_IACF20               IAC_ICR0_IACF20_Msk
+#define IAC_ICR0_IACF21_Pos           (21U)
+#define IAC_ICR0_IACF21_Msk           (0x1UL << IAC_ICR0_IACF21_Pos)              /*!< 0x00200000 */
+#define IAC_ICR0_IACF21               IAC_ICR0_IACF21_Msk
+#define IAC_ICR0_IACF22_Pos           (22U)
+#define IAC_ICR0_IACF22_Msk           (0x1UL << IAC_ICR0_IACF22_Pos)              /*!< 0x00400000 */
+#define IAC_ICR0_IACF22               IAC_ICR0_IACF22_Msk
+#define IAC_ICR0_IACF23_Pos           (23U)
+#define IAC_ICR0_IACF23_Msk           (0x1UL << IAC_ICR0_IACF23_Pos)              /*!< 0x00800000 */
+#define IAC_ICR0_IACF23               IAC_ICR0_IACF23_Msk
+#define IAC_ICR0_IACF24_Pos           (24U)
+#define IAC_ICR0_IACF24_Msk           (0x1UL << IAC_ICR0_IACF24_Pos)              /*!< 0x01000000 */
+#define IAC_ICR0_IACF24               IAC_ICR0_IACF24_Msk
+#define IAC_ICR0_IACF25_Pos           (25U)
+#define IAC_ICR0_IACF25_Msk           (0x1UL << IAC_ICR0_IACF25_Pos)              /*!< 0x02000000 */
+#define IAC_ICR0_IACF25               IAC_ICR0_IACF25_Msk
+#define IAC_ICR0_IACF26_Pos           (26U)
+#define IAC_ICR0_IACF26_Msk           (0x1UL << IAC_ICR0_IACF26_Pos)              /*!< 0x04000000 */
+#define IAC_ICR0_IACF26               IAC_ICR0_IACF26_Msk
+#define IAC_ICR0_IACF27_Pos           (27U)
+#define IAC_ICR0_IACF27_Msk           (0x1UL << IAC_ICR0_IACF27_Pos)              /*!< 0x08000000 */
+#define IAC_ICR0_IACF27               IAC_ICR0_IACF27_Msk
+#define IAC_ICR0_IACF28_Pos           (28U)
+#define IAC_ICR0_IACF28_Msk           (0x1UL << IAC_ICR0_IACF28_Pos)              /*!< 0x10000000 */
+#define IAC_ICR0_IACF28               IAC_ICR0_IACF28_Msk
+#define IAC_ICR0_IACF29_Pos           (29U)
+#define IAC_ICR0_IACF29_Msk           (0x1UL << IAC_ICR0_IACF29_Pos)              /*!< 0x20000000 */
+#define IAC_ICR0_IACF29               IAC_ICR0_IACF29_Msk
+#define IAC_ICR0_IACF30_Pos           (30U)
+#define IAC_ICR0_IACF30_Msk           (0x1UL << IAC_ICR0_IACF30_Pos)              /*!< 0x40000000 */
+#define IAC_ICR0_IACF30               IAC_ICR0_IACF30_Msk
+#define IAC_ICR0_IACF31_Pos           (31U)
+#define IAC_ICR0_IACF31_Msk           (0x1UL << IAC_ICR0_IACF31_Pos)              /*!< 0x80000000 */
+#define IAC_ICR0_IACF31               IAC_ICR0_IACF31_Msk
+
+/*******************  Bits definition for IAC_ICR1 register *******************/
+#define IAC_ICR1_IACF32_Pos           (0U)
+#define IAC_ICR1_IACF32_Msk           (0x1UL << IAC_ICR1_IACF32_Pos)              /*!< 0x00000001 */
+#define IAC_ICR1_IACF32               IAC_ICR1_IACF32_Msk
+#define IAC_ICR1_IACF33_Pos           (1U)
+#define IAC_ICR1_IACF33_Msk           (0x1UL << IAC_ICR1_IACF33_Pos)              /*!< 0x00000002 */
+#define IAC_ICR1_IACF33               IAC_ICR1_IACF33_Msk
+#define IAC_ICR1_IACF34_Pos           (2U)
+#define IAC_ICR1_IACF34_Msk           (0x1UL << IAC_ICR1_IACF34_Pos)              /*!< 0x00000004 */
+#define IAC_ICR1_IACF34               IAC_ICR1_IACF34_Msk
+#define IAC_ICR1_IACF35_Pos           (3U)
+#define IAC_ICR1_IACF35_Msk           (0x1UL << IAC_ICR1_IACF35_Pos)              /*!< 0x00000008 */
+#define IAC_ICR1_IACF35               IAC_ICR1_IACF35_Msk
+#define IAC_ICR1_IACF36_Pos           (4U)
+#define IAC_ICR1_IACF36_Msk           (0x1UL << IAC_ICR1_IACF36_Pos)              /*!< 0x00000010 */
+#define IAC_ICR1_IACF36               IAC_ICR1_IACF36_Msk
+#define IAC_ICR1_IACF37_Pos           (5U)
+#define IAC_ICR1_IACF37_Msk           (0x1UL << IAC_ICR1_IACF37_Pos)              /*!< 0x00000020 */
+#define IAC_ICR1_IACF37               IAC_ICR1_IACF37_Msk
+#define IAC_ICR1_IACF38_Pos           (6U)
+#define IAC_ICR1_IACF38_Msk           (0x1UL << IAC_ICR1_IACF38_Pos)              /*!< 0x00000040 */
+#define IAC_ICR1_IACF38               IAC_ICR1_IACF38_Msk
+#define IAC_ICR1_IACF39_Pos           (7U)
+#define IAC_ICR1_IACF39_Msk           (0x1UL << IAC_ICR1_IACF39_Pos)              /*!< 0x00000080 */
+#define IAC_ICR1_IACF39               IAC_ICR1_IACF39_Msk
+#define IAC_ICR1_IACF40_Pos           (8U)
+#define IAC_ICR1_IACF40_Msk           (0x1UL << IAC_ICR1_IACF40_Pos)              /*!< 0x00000100 */
+#define IAC_ICR1_IACF40               IAC_ICR1_IACF40_Msk
+#define IAC_ICR1_IACF41_Pos           (9U)
+#define IAC_ICR1_IACF41_Msk           (0x1UL << IAC_ICR1_IACF41_Pos)              /*!< 0x00000200 */
+#define IAC_ICR1_IACF41               IAC_ICR1_IACF41_Msk
+#define IAC_ICR1_IACF42_Pos           (10U)
+#define IAC_ICR1_IACF42_Msk           (0x1UL << IAC_ICR1_IACF42_Pos)              /*!< 0x00000400 */
+#define IAC_ICR1_IACF42               IAC_ICR1_IACF42_Msk
+#define IAC_ICR1_IACF43_Pos           (11U)
+#define IAC_ICR1_IACF43_Msk           (0x1UL << IAC_ICR1_IACF43_Pos)              /*!< 0x00000800 */
+#define IAC_ICR1_IACF43               IAC_ICR1_IACF43_Msk
+#define IAC_ICR1_IACF44_Pos           (12U)
+#define IAC_ICR1_IACF44_Msk           (0x1UL << IAC_ICR1_IACF44_Pos)              /*!< 0x00001000 */
+#define IAC_ICR1_IACF44               IAC_ICR1_IACF44_Msk
+#define IAC_ICR1_IACF45_Pos           (13U)
+#define IAC_ICR1_IACF45_Msk           (0x1UL << IAC_ICR1_IACF45_Pos)              /*!< 0x00002000 */
+#define IAC_ICR1_IACF45               IAC_ICR1_IACF45_Msk
+#define IAC_ICR1_IACF46_Pos           (14U)
+#define IAC_ICR1_IACF46_Msk           (0x1UL << IAC_ICR1_IACF46_Pos)              /*!< 0x00004000 */
+#define IAC_ICR1_IACF46               IAC_ICR1_IACF46_Msk
+#define IAC_ICR1_IACF47_Pos           (15U)
+#define IAC_ICR1_IACF47_Msk           (0x1UL << IAC_ICR1_IACF47_Pos)              /*!< 0x00008000 */
+#define IAC_ICR1_IACF47               IAC_ICR1_IACF47_Msk
+#define IAC_ICR1_IACF48_Pos           (16U)
+#define IAC_ICR1_IACF48_Msk           (0x1UL << IAC_ICR1_IACF48_Pos)              /*!< 0x00010000 */
+#define IAC_ICR1_IACF48               IAC_ICR1_IACF48_Msk
+#define IAC_ICR1_IACF49_Pos           (17U)
+#define IAC_ICR1_IACF49_Msk           (0x1UL << IAC_ICR1_IACF49_Pos)              /*!< 0x00020000 */
+#define IAC_ICR1_IACF49               IAC_ICR1_IACF49_Msk
+#define IAC_ICR1_IACF50_Pos           (18U)
+#define IAC_ICR1_IACF50_Msk           (0x1UL << IAC_ICR1_IACF50_Pos)              /*!< 0x00040000 */
+#define IAC_ICR1_IACF50               IAC_ICR1_IACF50_Msk
+#define IAC_ICR1_IACF51_Pos           (19U)
+#define IAC_ICR1_IACF51_Msk           (0x1UL << IAC_ICR1_IACF51_Pos)              /*!< 0x00080000 */
+#define IAC_ICR1_IACF51               IAC_ICR1_IACF51_Msk
+#define IAC_ICR1_IACF52_Pos           (20U)
+#define IAC_ICR1_IACF52_Msk           (0x1UL << IAC_ICR1_IACF52_Pos)              /*!< 0x00100000 */
+#define IAC_ICR1_IACF52               IAC_ICR1_IACF52_Msk
+#define IAC_ICR1_IACF53_Pos           (21U)
+#define IAC_ICR1_IACF53_Msk           (0x1UL << IAC_ICR1_IACF53_Pos)              /*!< 0x00200000 */
+#define IAC_ICR1_IACF53               IAC_ICR1_IACF53_Msk
+#define IAC_ICR1_IACF54_Pos           (22U)
+#define IAC_ICR1_IACF54_Msk           (0x1UL << IAC_ICR1_IACF54_Pos)              /*!< 0x00400000 */
+#define IAC_ICR1_IACF54               IAC_ICR1_IACF54_Msk
+#define IAC_ICR1_IACF55_Pos           (23U)
+#define IAC_ICR1_IACF55_Msk           (0x1UL << IAC_ICR1_IACF55_Pos)              /*!< 0x00800000 */
+#define IAC_ICR1_IACF55               IAC_ICR1_IACF55_Msk
+#define IAC_ICR1_IACF56_Pos           (24U)
+#define IAC_ICR1_IACF56_Msk           (0x1UL << IAC_ICR1_IACF56_Pos)              /*!< 0x01000000 */
+#define IAC_ICR1_IACF56               IAC_ICR1_IACF56_Msk
+#define IAC_ICR1_IACF57_Pos           (25U)
+#define IAC_ICR1_IACF57_Msk           (0x1UL << IAC_ICR1_IACF57_Pos)              /*!< 0x02000000 */
+#define IAC_ICR1_IACF57               IAC_ICR1_IACF57_Msk
+#define IAC_ICR1_IACF58_Pos           (26U)
+#define IAC_ICR1_IACF58_Msk           (0x1UL << IAC_ICR1_IACF58_Pos)              /*!< 0x04000000 */
+#define IAC_ICR1_IACF58               IAC_ICR1_IACF58_Msk
+#define IAC_ICR1_IACF60_Pos           (28U)
+#define IAC_ICR1_IACF60_Msk           (0x1UL << IAC_ICR1_IACF60_Pos)              /*!< 0x10000000 */
+#define IAC_ICR1_IACF60               IAC_ICR1_IACF60_Msk
+#define IAC_ICR1_IACF61_Pos           (29U)
+#define IAC_ICR1_IACF61_Msk           (0x1UL << IAC_ICR1_IACF61_Pos)              /*!< 0x20000000 */
+#define IAC_ICR1_IACF61               IAC_ICR1_IACF61_Msk
+#define IAC_ICR1_IACF62_Pos           (30U)
+#define IAC_ICR1_IACF62_Msk           (0x1UL << IAC_ICR1_IACF62_Pos)              /*!< 0x40000000 */
+#define IAC_ICR1_IACF62               IAC_ICR1_IACF62_Msk
+
+/*******************  Bits definition for IAC_ICR2 register *******************/
+#define IAC_ICR2_IACF64_Pos           (0U)
+#define IAC_ICR2_IACF64_Msk           (0x1UL << IAC_ICR2_IACF64_Pos)              /*!< 0x00000001 */
+#define IAC_ICR2_IACF64               IAC_ICR2_IACF64_Msk
+#define IAC_ICR2_IACF65_Pos           (1U)
+#define IAC_ICR2_IACF65_Msk           (0x1UL << IAC_ICR2_IACF65_Pos)              /*!< 0x00000002 */
+#define IAC_ICR2_IACF65               IAC_ICR2_IACF65_Msk
+#define IAC_ICR2_IACF67_Pos           (3U)
+#define IAC_ICR2_IACF67_Msk           (0x1UL << IAC_ICR2_IACF67_Pos)              /*!< 0x00000008 */
+#define IAC_ICR2_IACF67               IAC_ICR2_IACF67_Msk
+#define IAC_ICR2_IACF68_Pos           (4U)
+#define IAC_ICR2_IACF68_Msk           (0x1UL << IAC_ICR2_IACF68_Pos)              /*!< 0x00000010 */
+#define IAC_ICR2_IACF68               IAC_ICR2_IACF68_Msk
+#define IAC_ICR2_IACF69_Pos           (5U)
+#define IAC_ICR2_IACF69_Msk           (0x1UL << IAC_ICR2_IACF69_Pos)              /*!< 0x00000020 */
+#define IAC_ICR2_IACF69               IAC_ICR2_IACF69_Msk
+#define IAC_ICR2_IACF76_Pos           (12U)
+#define IAC_ICR2_IACF76_Msk           (0x1UL << IAC_ICR2_IACF76_Pos)              /*!< 0x00001000 */
+#define IAC_ICR2_IACF76               IAC_ICR2_IACF76_Msk
+#define IAC_ICR2_IACF77_Pos           (13U)
+#define IAC_ICR2_IACF77_Msk           (0x1UL << IAC_ICR2_IACF77_Pos)              /*!< 0x00002000 */
+#define IAC_ICR2_IACF77               IAC_ICR2_IACF77_Msk
+#define IAC_ICR2_IACF78_Pos           (14U)
+#define IAC_ICR2_IACF78_Msk           (0x1UL << IAC_ICR2_IACF78_Pos)              /*!< 0x00004000 */
+#define IAC_ICR2_IACF78               IAC_ICR2_IACF78_Msk
+#define IAC_ICR2_IACF79_Pos           (15U)
+#define IAC_ICR2_IACF79_Msk           (0x1UL << IAC_ICR2_IACF79_Pos)              /*!< 0x00008000 */
+#define IAC_ICR2_IACF79               IAC_ICR2_IACF79_Msk
+#define IAC_ICR2_IACF80_Pos           (16U)
+#define IAC_ICR2_IACF80_Msk           (0x1UL << IAC_ICR2_IACF80_Pos)              /*!< 0x00010000 */
+#define IAC_ICR2_IACF80               IAC_ICR2_IACF80_Msk
+#define IAC_ICR2_IACF81_Pos           (17U)
+#define IAC_ICR2_IACF81_Msk           (0x1UL << IAC_ICR2_IACF81_Pos)              /*!< 0x00020000 */
+#define IAC_ICR2_IACF81               IAC_ICR2_IACF81_Msk
+#define IAC_ICR2_IACF82_Pos           (18U)
+#define IAC_ICR2_IACF82_Msk           (0x1UL << IAC_ICR2_IACF82_Pos)              /*!< 0x00040000 */
+#define IAC_ICR2_IACF82               IAC_ICR2_IACF82_Msk
+#define IAC_ICR2_IACF83_Pos           (19U)
+#define IAC_ICR2_IACF83_Msk           (0x1UL << IAC_ICR2_IACF83_Pos)              /*!< 0x00080000 */
+#define IAC_ICR2_IACF83               IAC_ICR2_IACF83_Msk
+#define IAC_ICR2_IACF84_Pos           (20U)
+#define IAC_ICR2_IACF84_Msk           (0x1UL << IAC_ICR2_IACF84_Pos)              /*!< 0x00100000 */
+#define IAC_ICR2_IACF84               IAC_ICR2_IACF84_Msk
+#define IAC_ICR2_IACF86_Pos           (22U)
+#define IAC_ICR2_IACF86_Msk           (0x1UL << IAC_ICR2_IACF86_Pos)              /*!< 0x00400000 */
+#define IAC_ICR2_IACF86               IAC_ICR2_IACF86_Msk
+#define IAC_ICR2_IACF87_Pos           (23U)
+#define IAC_ICR2_IACF87_Msk           (0x1UL << IAC_ICR2_IACF87_Pos)              /*!< 0x00800000 */
+#define IAC_ICR2_IACF87               IAC_ICR2_IACF87_Msk
+#define IAC_ICR2_IACF88_Pos           (24U)
+#define IAC_ICR2_IACF88_Msk           (0x1UL << IAC_ICR2_IACF88_Pos)              /*!< 0x01000000 */
+#define IAC_ICR2_IACF88               IAC_ICR2_IACF88_Msk
+#define IAC_ICR2_IACF89_Pos           (25U)
+#define IAC_ICR2_IACF89_Msk           (0x1UL << IAC_ICR2_IACF89_Pos)              /*!< 0x02000000 */
+#define IAC_ICR2_IACF89               IAC_ICR2_IACF89_Msk
+#define IAC_ICR2_IACF90_Pos           (26U)
+#define IAC_ICR2_IACF90_Msk           (0x1UL << IAC_ICR2_IACF90_Pos)              /*!< 0x04000000 */
+#define IAC_ICR2_IACF90               IAC_ICR2_IACF90_Msk
+#define IAC_ICR2_IACF92_Pos           (28U)
+#define IAC_ICR2_IACF92_Msk           (0x1UL << IAC_ICR2_IACF92_Pos)              /*!< 0x10000000 */
+#define IAC_ICR2_IACF92               IAC_ICR2_IACF92_Msk
+#define IAC_ICR2_IACF93_Pos           (29U)
+#define IAC_ICR2_IACF93_Msk           (0x1UL << IAC_ICR2_IACF93_Pos)              /*!< 0x20000000 */
+#define IAC_ICR2_IACF93               IAC_ICR2_IACF93_Msk
+#define IAC_ICR2_IACF94_Pos           (30U)
+#define IAC_ICR2_IACF94_Msk           (0x1UL << IAC_ICR2_IACF94_Pos)              /*!< 0x40000000 */
+#define IAC_ICR2_IACF94               IAC_ICR2_IACF94_Msk
+#define IAC_ICR2_IACF95_Pos           (31U)
+#define IAC_ICR2_IACF95_Msk           (0x1UL << IAC_ICR2_IACF95_Pos)              /*!< 0x80000000 */
+#define IAC_ICR2_IACF95               IAC_ICR2_IACF95_Msk
+
+/*******************  Bits definition for IAC_ICR3 register *******************/
+#define IAC_ICR3_IACF96_Pos           (0U)
+#define IAC_ICR3_IACF96_Msk           (0x1UL << IAC_ICR3_IACF96_Pos)              /*!< 0x00000001 */
+#define IAC_ICR3_IACF96               IAC_ICR3_IACF96_Msk
+#define IAC_ICR3_IACF97_Pos           (1U)
+#define IAC_ICR3_IACF97_Msk           (0x1UL << IAC_ICR3_IACF97_Pos)              /*!< 0x00000002 */
+#define IAC_ICR3_IACF97               IAC_ICR3_IACF97_Msk
+#define IAC_ICR3_IACF98_Pos           (2U)
+#define IAC_ICR3_IACF98_Msk           (0x1UL << IAC_ICR3_IACF98_Pos)              /*!< 0x00000004 */
+#define IAC_ICR3_IACF98               IAC_ICR3_IACF98_Msk
+#define IAC_ICR3_IACF99_Pos           (3U)
+#define IAC_ICR3_IACF99_Msk           (0x1UL << IAC_ICR3_IACF99_Pos)              /*!< 0x00000008 */
+#define IAC_ICR3_IACF99               IAC_ICR3_IACF99_Msk
+#define IAC_ICR3_IACF100_Pos          (4U)
+#define IAC_ICR3_IACF100_Msk          (0x1UL << IAC_ICR3_IACF100_Pos)             /*!< 0x00000010 */
+#define IAC_ICR3_IACF100              IAC_ICR3_IACF100_Msk
+#define IAC_ICR3_IACF101_Pos          (5U)
+#define IAC_ICR3_IACF101_Msk          (0x1UL << IAC_ICR3_IACF101_Pos)             /*!< 0x00000020 */
+#define IAC_ICR3_IACF101              IAC_ICR3_IACF101_Msk
+#define IAC_ICR3_IACF102_Pos          (6U)
+#define IAC_ICR3_IACF102_Msk          (0x1UL << IAC_ICR3_IACF102_Pos)             /*!< 0x00000040 */
+#define IAC_ICR3_IACF102              IAC_ICR3_IACF102_Msk
+#define IAC_ICR3_IACF103_Pos          (7U)
+#define IAC_ICR3_IACF103_Msk          (0x1UL << IAC_ICR3_IACF103_Pos)             /*!< 0x00000080 */
+#define IAC_ICR3_IACF103              IAC_ICR3_IACF103_Msk
+#define IAC_ICR3_IACF104_Pos          (8U)
+#define IAC_ICR3_IACF104_Msk          (0x1UL << IAC_ICR3_IACF104_Pos)             /*!< 0x00000100 */
+#define IAC_ICR3_IACF104              IAC_ICR3_IACF104_Msk
+#define IAC_ICR3_IACF106_Pos          (10U)
+#define IAC_ICR3_IACF106_Msk          (0x1UL << IAC_ICR3_IACF106_Pos)             /*!< 0x00000400 */
+#define IAC_ICR3_IACF106              IAC_ICR3_IACF106_Msk
+
+/*******************  Bits definition for IAC_ICR4 register *******************/
+#define IAC_ICR4_IACF128_Pos          (0U)
+#define IAC_ICR4_IACF128_Msk          (0x1UL << IAC_ICR4_IACF128_Pos)             /*!< 0x00000001 */
+#define IAC_ICR4_IACF128              IAC_ICR4_IACF128_Msk
+#define IAC_ICR4_IACF129_Pos          (1U)
+#define IAC_ICR4_IACF129_Msk          (0x1UL << IAC_ICR4_IACF129_Pos)             /*!< 0x00000002 */
+#define IAC_ICR4_IACF129              IAC_ICR4_IACF129_Msk
+#define IAC_ICR4_IACF130_Pos          (2U)
+#define IAC_ICR4_IACF130_Msk          (0x1UL << IAC_ICR4_IACF130_Pos)             /*!< 0x00000004 */
+#define IAC_ICR4_IACF130              IAC_ICR4_IACF130_Msk
+#define IAC_ICR4_IACF131_Pos          (3U)
+#define IAC_ICR4_IACF131_Msk          (0x1UL << IAC_ICR4_IACF131_Pos)             /*!< 0x00000008 */
+#define IAC_ICR4_IACF131              IAC_ICR4_IACF131_Msk
+#define IAC_ICR4_IACF133_Pos          (5U)
+#define IAC_ICR4_IACF133_Msk          (0x1UL << IAC_ICR4_IACF133_Pos)             /*!< 0x00000020 */
+#define IAC_ICR4_IACF133              IAC_ICR4_IACF133_Msk
+#define IAC_ICR4_IACF134_Pos          (6U)
+#define IAC_ICR4_IACF134_Msk          (0x1UL << IAC_ICR4_IACF134_Pos)             /*!< 0x00000040 */
+#define IAC_ICR4_IACF134              IAC_ICR4_IACF134_Msk
+#define IAC_ICR4_IACF135_Pos          (7U)
+#define IAC_ICR4_IACF135_Msk          (0x1UL << IAC_ICR4_IACF135_Pos)             /*!< 0x00000080 */
+#define IAC_ICR4_IACF135              IAC_ICR4_IACF135_Msk
+#define IAC_ICR4_IACF136_Pos          (8U)
+#define IAC_ICR4_IACF136_Msk          (0x1UL << IAC_ICR4_IACF136_Pos)             /*!< 0x00000100 */
+#define IAC_ICR4_IACF136              IAC_ICR4_IACF136_Msk
+#define IAC_ICR4_IACF137_Pos          (9U)
+#define IAC_ICR4_IACF137_Msk          (0x1UL << IAC_ICR4_IACF137_Pos)             /*!< 0x00000200 */
+#define IAC_ICR4_IACF137              IAC_ICR4_IACF137_Msk
+#define IAC_ICR4_IACF138_Pos          (10U)
+#define IAC_ICR4_IACF138_Msk          (0x1UL << IAC_ICR4_IACF138_Pos)             /*!< 0x00000400 */
+#define IAC_ICR4_IACF138              IAC_ICR4_IACF138_Msk
+#define IAC_ICR4_IACF139_Pos          (11U)
+#define IAC_ICR4_IACF139_Msk          (0x1UL << IAC_ICR4_IACF139_Pos)             /*!< 0x00000800 */
+#define IAC_ICR4_IACF139              IAC_ICR4_IACF139_Msk
+#define IAC_ICR4_IACF140_Pos          (12U)
+#define IAC_ICR4_IACF140_Msk          (0x1UL << IAC_ICR4_IACF140_Pos)             /*!< 0x00001000 */
+#define IAC_ICR4_IACF140              IAC_ICR4_IACF140_Msk
+#define IAC_ICR4_IACF141_Pos          (13U)
+#define IAC_ICR4_IACF141_Msk          (0x1UL << IAC_ICR4_IACF141_Pos)             /*!< 0x00002000 */
+#define IAC_ICR4_IACF141              IAC_ICR4_IACF141_Msk
+#define IAC_ICR4_IACF142_Pos          (14U)
+#define IAC_ICR4_IACF142_Msk          (0x1UL << IAC_ICR4_IACF142_Pos)             /*!< 0x00004000 */
+#define IAC_ICR4_IACF142              IAC_ICR4_IACF142_Msk
+#define IAC_ICR4_IACF143_Pos          (15U)
+#define IAC_ICR4_IACF143_Msk          (0x1UL << IAC_ICR4_IACF143_Pos)             /*!< 0x00008000 */
+#define IAC_ICR4_IACF143              IAC_ICR4_IACF143_Msk
+#define IAC_ICR4_IACF144_Pos          (16U)
+#define IAC_ICR4_IACF144_Msk          (0x1UL << IAC_ICR4_IACF144_Pos)             /*!< 0x00010000 */
+#define IAC_ICR4_IACF144              IAC_ICR4_IACF144_Msk
+#define IAC_ICR4_IACF145_Pos          (17U)
+#define IAC_ICR4_IACF145_Msk          (0x1UL << IAC_ICR4_IACF145_Pos)             /*!< 0x00020000 */
+#define IAC_ICR4_IACF145              IAC_ICR4_IACF145_Msk
+#define IAC_ICR4_IACF146_Pos          (18U)
+#define IAC_ICR4_IACF146_Msk          (0x1UL << IAC_ICR4_IACF146_Pos)             /*!< 0x00040000 */
+#define IAC_ICR4_IACF146              IAC_ICR4_IACF146_Msk
+#define IAC_ICR4_IACF147_Pos          (19U)
+#define IAC_ICR4_IACF147_Msk          (0x1UL << IAC_ICR4_IACF147_Pos)             /*!< 0x00080000 */
+#define IAC_ICR4_IACF147              IAC_ICR4_IACF147_Msk
+#define IAC_ICR4_IACF149_Pos          (21U)
+#define IAC_ICR4_IACF149_Msk          (0x1UL << IAC_ICR4_IACF149_Pos)             /*!< 0x00200000 */
+#define IAC_ICR4_IACF149              IAC_ICR4_IACF149_Msk
+#define IAC_ICR4_IACF150_Pos          (22U)
+#define IAC_ICR4_IACF150_Msk          (0x1UL << IAC_ICR4_IACF150_Pos)             /*!< 0x00400000 */
+#define IAC_ICR4_IACF150              IAC_ICR4_IACF150_Msk
+#define IAC_ICR4_IACF151_Pos          (23U)
+#define IAC_ICR4_IACF151_Msk          (0x1UL << IAC_ICR4_IACF151_Pos)             /*!< 0x00800000 */
+#define IAC_ICR4_IACF151              IAC_ICR4_IACF151_Msk
+#define IAC_ICR4_IACF152_Pos          (24U)
+#define IAC_ICR4_IACF152_Msk          (0x1UL << IAC_ICR4_IACF152_Pos)             /*!< 0x01000000 */
+#define IAC_ICR4_IACF152              IAC_ICR4_IACF152_Msk
+#define IAC_ICR4_IACF153_Pos          (25U)
+#define IAC_ICR4_IACF153_Msk          (0x1UL << IAC_ICR4_IACF153_Pos)             /*!< 0x02000000 */
+#define IAC_ICR4_IACF153              IAC_ICR4_IACF153_Msk
+#define IAC_ICR4_IACF155_Pos          (27U)
+#define IAC_ICR4_IACF155_Msk          (0x1UL << IAC_ICR4_IACF155_Pos)             /*!< 0x08000000 */
+#define IAC_ICR4_IACF155              IAC_ICR4_IACF155_Msk
+#define IAC_ICR4_IACF156_Pos          (28U)
+#define IAC_ICR4_IACF156_Msk          (0x1UL << IAC_ICR4_IACF156_Pos)             /*!< 0x10000000 */
+#define IAC_ICR4_IACF156              IAC_ICR4_IACF156_Msk
+#define IAC_ICR4_IACF157_Pos          (29U)
+#define IAC_ICR4_IACF157_Msk          (0x1UL << IAC_ICR4_IACF157_Pos)             /*!< 0x20000000 */
+#define IAC_ICR4_IACF157              IAC_ICR4_IACF157_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 ICACHE                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for ICACHE_CR register  *******************/
+#define ICACHE_CR_EN_Pos               (0U)
+#define ICACHE_CR_EN_Msk               (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
+#define ICACHE_CR_EN                   ICACHE_CR_EN_Msk                        /*!< Enable */
+#define ICACHE_CR_CACHEINV_Pos         (1U)
+#define ICACHE_CR_CACHEINV_Msk         (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
+#define ICACHE_CR_CACHEINV             ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
+#define ICACHE_CR_WAYSEL_Pos           (2U)
+#define ICACHE_CR_WAYSEL_Msk           (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
+#define ICACHE_CR_WAYSEL               ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
+#define ICACHE_CR_HITMEN_Pos           (16U)
+#define ICACHE_CR_HITMEN_Msk           (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
+#define ICACHE_CR_HITMEN               ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
+#define ICACHE_CR_MISSMEN_Pos          (17U)
+#define ICACHE_CR_MISSMEN_Msk          (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
+#define ICACHE_CR_MISSMEN              ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
+#define ICACHE_CR_HITMRST_Pos          (18U)
+#define ICACHE_CR_HITMRST_Msk          (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
+#define ICACHE_CR_HITMRST              ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
+#define ICACHE_CR_MISSMRST_Pos         (19U)
+#define ICACHE_CR_MISSMRST_Msk         (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
+#define ICACHE_CR_MISSMRST             ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
+
+/******************  Bit definition for ICACHE_SR register  *******************/
+#define ICACHE_SR_BUSYF_Pos            (0U)
+#define ICACHE_SR_BUSYF_Msk            (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
+#define ICACHE_SR_BUSYF                ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
+#define ICACHE_SR_BSYENDF_Pos          (1U)
+#define ICACHE_SR_BSYENDF_Msk          (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
+#define ICACHE_SR_BSYENDF              ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
+#define ICACHE_SR_ERRF_Pos             (2U)
+#define ICACHE_SR_ERRF_Msk             (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
+#define ICACHE_SR_ERRF                 ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
+
+/******************  Bit definition for ICACHE_IER register  ******************/
+#define ICACHE_IER_BSYENDIE_Pos        (1U)
+#define ICACHE_IER_BSYENDIE_Msk        (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
+#define ICACHE_IER_BSYENDIE            ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
+#define ICACHE_IER_ERRIE_Pos           (2U)
+#define ICACHE_IER_ERRIE_Msk           (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
+#define ICACHE_IER_ERRIE               ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
+
+/******************  Bit definition for ICACHE_FCR register  ******************/
+#define ICACHE_FCR_CBSYENDF_Pos        (1U)
+#define ICACHE_FCR_CBSYENDF_Msk        (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
+#define ICACHE_FCR_CBSYENDF            ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
+#define ICACHE_FCR_CERRF_Pos           (2U)
+#define ICACHE_FCR_CERRF_Msk           (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
+#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
+
+/******************  Bit definition for ICACHE_HMONR register  ****************/
+#define ICACHE_HMONR_HITMON_Pos         (0U)
+#define ICACHE_HMONR_HITMON_Msk         (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)/*!< 0xFFFFFFFF */
+#define ICACHE_HMONR_HITMON             ICACHE_HMONR_HITMON_Msk                /*!< Cache hit monitor register */
+
+/******************  Bit definition for ICACHE_MMONR register  ****************/
+#define ICACHE_MMONR_MISSMON_Pos        (0U)
+#define ICACHE_MMONR_MISSMON_Msk        (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
+#define ICACHE_MMONR_MISSMON            ICACHE_MMONR_MISSMON_Msk               /*!< Cache miss monitor register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent Watchdog (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos             (0U)
+#define IWDG_KR_KEY_Msk             (0xFFFFUL << IWDG_KR_KEY_Pos)          /*!< 0x0000FFFF */
+#define IWDG_KR_KEY                 IWDG_KR_KEY_Msk                       /*!< Key value (write only, read 0x0000) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos              (0U)
+#define IWDG_PR_PR_Msk              (0xFUL << IWDG_PR_PR_Pos)              /*!< 0x0000000F */
+#define IWDG_PR_PR                  IWDG_PR_PR_Msk                        /*!< Prescaler divider */
+#define IWDG_PR_PR_0                (0x1UL << IWDG_PR_PR_Pos)              /*!< 0x00000001 */
+#define IWDG_PR_PR_1                (0x2UL << IWDG_PR_PR_Pos)              /*!< 0x00000002 */
+#define IWDG_PR_PR_2                (0x4UL << IWDG_PR_PR_Pos)              /*!< 0x00000004 */
+#define IWDG_PR_PR_3                (0x8UL << IWDG_PR_PR_Pos)              /*!< 0x00000008 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos             (0U)
+#define IWDG_RLR_RL_Msk             (0xFFFUL << IWDG_RLR_RL_Pos)           /*!< 0x00000FFF */
+#define IWDG_RLR_RL                 IWDG_RLR_RL_Msk                       /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos             (0U)
+#define IWDG_SR_PVU_Msk             (0x1UL << IWDG_SR_PVU_Pos)             /*!< 0x00000001 */
+#define IWDG_SR_PVU                 IWDG_SR_PVU_Msk                       /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos             (1U)
+#define IWDG_SR_RVU_Msk             (0x1UL << IWDG_SR_RVU_Pos)             /*!< 0x00000002 */
+#define IWDG_SR_RVU                 IWDG_SR_RVU_Msk                       /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos             (2U)
+#define IWDG_SR_WVU_Msk             (0x1UL << IWDG_SR_WVU_Pos)             /*!< 0x00000004 */
+#define IWDG_SR_WVU                 IWDG_SR_WVU_Msk                       /*!< Watchdog counter window value update */
+#define IWDG_SR_EWU_Pos             (3U)
+#define IWDG_SR_EWU_Msk             (0x1UL << IWDG_SR_EWU_Pos)             /*!< 0x00000008 */
+#define IWDG_SR_EWU                 IWDG_SR_EWU_Msk                       /*!< Watchdog interrupt comparator value update */
+#define IWDG_SR_ONF_Pos             (8U)
+#define IWDG_SR_ONF_Msk             (0x1UL << IWDG_SR_ONF_Pos)             /*!< 0x00000100 */
+#define IWDG_SR_ONF                 IWDG_SR_ONF_Msk                       /*!< Watchdog Enable status bit */
+#define IWDG_SR_EWIF_Pos            (15U)
+#define IWDG_SR_EWIF_Msk            (0x1UL << IWDG_SR_EWIF_Pos)            /*!< 0x00008000 */
+#define IWDG_SR_EWIF                IWDG_SR_EWIF_Msk                      /*!< Watchdog Early Interrupt flag */
+
+/******************  Bit definition for IWDG_WINR register  *******************/
+#define IWDG_WINR_WIN_Pos           (0U)
+#define IWDG_WINR_WIN_Msk           (0xFFFUL << IWDG_WINR_WIN_Pos)         /*!< 0x00000FFF */
+#define IWDG_WINR_WIN               IWDG_WINR_WIN_Msk                     /*!< Watchdog counter window value */
+
+/******************  Bit definition for IWDG_EWCR register  *******************/
+#define IWDG_EWCR_EWIT_Pos          (0U)
+#define IWDG_EWCR_EWIT_Msk          (0xFFFUL << IWDG_EWCR_EWIT_Pos)        /*!< 0x00000FFF */
+#define IWDG_EWCR_EWIT              IWDG_EWCR_EWIT_Msk                    /*!< Watchdog counter window value */
+#define IWDG_EWCR_EWIE_Pos          (15U)
+#define IWDG_EWCR_EWIE_Msk          (0x1UL << IWDG_EWCR_EWIE_Pos)          /*!< 0x00008000 */
+#define IWDG_EWCR_EWIE              IWDG_EWCR_EWIE_Msk                    /*!< Watchdog early interrupt enable */
+
+/*******************  Bit definition for IWDG_ICR register  *******************/
+#define IWDG_ICR_EWIC_Pos           (15U)
+#define IWDG_ICR_EWIC_Msk           (0x1UL << IWDG_ICR_EWIC_Pos)           /*!< 0x00008000 */
+#define IWDG_ICR_EWIC               IWDG_ICR_EWIC_Msk                     /*!< Watchdog early interrupt acknowledge */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)         /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                    /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                       /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                       /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk               /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)    /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)            /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                       /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                      /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                    /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)    /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                     /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)      /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                    /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                      /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                      /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)            /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                       /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)            /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                       /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)            /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                       /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)            /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)            /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                       /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)            /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                      /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)           /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)           /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                      /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)              /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                         /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)             /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                        /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)            /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                       /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)             /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                        /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)            /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                       /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)             /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                        /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)             /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                        /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IDMAEN_Pos              (11U)
+#define JPEG_CR_IDMAEN_Msk              (0x1UL << JPEG_CR_IDMAEN_Pos)            /*!< 0x00000800 */
+#define JPEG_CR_IDMAEN                  JPEG_CR_IDMAEN_Msk                       /*!<Input DMA enable */
+#define JPEG_CR_ODMAEN_Pos              (12U)
+#define JPEG_CR_ODMAEN_Msk              (0x1UL << JPEG_CR_ODMAEN_Pos)            /*!< 0x00001000 */
+#define JPEG_CR_ODMAEN                  JPEG_CR_ODMAEN_Msk                       /*!<Output DMA enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)               /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                          /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)               /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                          /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)              /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                         /*!<Input FIFO is not full and is below its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)             /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                        /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)              /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                         /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)             /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                        /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)              /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                         /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)              /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                         /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)               /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                          /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (5U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                       /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (6U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                       /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)    /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                      /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)   /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                     /*!<Data Output FIFO */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTIM)                            */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CC1IF_Pos         (0U)
+#define LPTIM_ISR_CC1IF_Msk         (0x1UL << LPTIM_ISR_CC1IF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ISR_CC1IF             LPTIM_ISR_CC1IF_Msk                        /*!< Capture/Compare 1 interrupt flag */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMP1OK_Pos        (3U)
+#define LPTIM_ISR_CMP1OK_Msk        (0x1UL << LPTIM_ISR_CMP1OK_Pos)            /*!< 0x00000008 */
+#define LPTIM_ISR_CMP1OK            LPTIM_ISR_CMP1OK_Msk                       /*!< Compare register 1 update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+#define LPTIM_ISR_UE_Pos            (7U)
+#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
+#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
+#define LPTIM_ISR_REPOK_Pos         (8U)
+#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
+#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
+#define LPTIM_ISR_CC2IF_Pos         (9U)
+#define LPTIM_ISR_CC2IF_Msk         (0x1UL << LPTIM_ISR_CC2IF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ISR_CC2IF             LPTIM_ISR_CC2IF_Msk                        /*!< Capture/Compare 2 interrupt flag */
+#define LPTIM_ISR_CC1OF_Pos         (12U)
+#define LPTIM_ISR_CC1OF_Msk         (0x1UL << LPTIM_ISR_CC1OF_Pos)             /*!< 0x00001000 */
+#define LPTIM_ISR_CC1OF             LPTIM_ISR_CC1OF_Msk                        /*!< Capture/Compare 1 over-capture flag */
+#define LPTIM_ISR_CC2OF_Pos         (13U)
+#define LPTIM_ISR_CC2OF_Msk         (0x1UL << LPTIM_ISR_CC2OF_Pos)             /*!< 0x00002000 */
+#define LPTIM_ISR_CC2OF             LPTIM_ISR_CC2OF_Msk                        /*!< Capture/Compare 2 over-capture flag */
+#define LPTIM_ISR_CMP2OK_Pos        (19U)
+#define LPTIM_ISR_CMP2OK_Msk        (0x1UL << LPTIM_ISR_CMP2OK_Pos)            /*!< 0x00080000 */
+#define LPTIM_ISR_CMP2OK            LPTIM_ISR_CMP2OK_Msk                       /*!< Compare register 2 update OK */
+#define LPTIM_ISR_DIEROK_Pos        (24U)
+#define LPTIM_ISR_DIEROK_Msk        (0x1UL << LPTIM_ISR_DIEROK_Pos)            /*!< 0x01000000 */
+#define LPTIM_ISR_DIEROK            LPTIM_ISR_DIEROK_Msk                       /*!< Interrupt enable register update OK */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CC1CF_Pos         (0U)
+#define LPTIM_ICR_CC1CF_Msk         (0x1UL << LPTIM_ICR_CC1CF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CC1CF              LPTIM_ICR_CC1CF_Msk                       /*!< Capture/Compare 1 clear flag  */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMP1OKCF_Pos      (3U)
+#define LPTIM_ICR_CMP1OKCF_Msk      (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)          /*!< 0x00000008 */
+#define LPTIM_ICR_CMP1OKCF          LPTIM_ICR_CMP1OKCF_Msk                     /*!< Compare register 1 update OK clear flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+#define LPTIM_ICR_UECF_Pos          (7U)
+#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
+#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
+#define LPTIM_ICR_REPOKCF_Pos       (8U)
+#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
+#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
+#define LPTIM_ICR_CC2CF_Pos         (9U)
+#define LPTIM_ICR_CC2CF_Msk         (0x1UL << LPTIM_ICR_CC2CF_Pos)             /*!< 0x00000200 */
+#define LPTIM_ICR_CC2CF             LPTIM_ICR_CC2CF_Msk                        /*!< Capture/Compare 2 clear flag  */
+#define LPTIM_ICR_CC1OCF_Pos        (12U)
+#define LPTIM_ICR_CC1OCF_Msk        (0x1UL << LPTIM_ICR_CC1OCF_Pos)            /*!< 0x00001000 */
+#define LPTIM_ICR_CC1OCF            LPTIM_ICR_CC1OCF_Msk                       /*!< Capture/Compare 1 over-capture clear flag */
+#define LPTIM_ICR_CC2OCF_Pos        (13U)
+#define LPTIM_ICR_CC2OCF_Msk        (0x1UL << LPTIM_ICR_CC2OCF_Pos)            /*!< 0x00002000 */
+#define LPTIM_ICR_CC2OCF            LPTIM_ICR_CC2OCF_Msk                       /*!< Capture/Compare 2 over-capture clear flag */
+#define LPTIM_ICR_CMP2OKCF_Pos      (19U)
+#define LPTIM_ICR_CMP2OKCF_Msk      (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)          /*!< 0x00080000 */
+#define LPTIM_ICR_CMP2OKCF          LPTIM_ICR_CMP2OKCF_Msk                     /*!< Compare register 2 update OK clear flag */
+#define LPTIM_ICR_DIEROKCF_Pos      (24U)
+#define LPTIM_ICR_DIEROKCF_Msk      (0x1UL << LPTIM_ICR_DIEROKCF_Pos)          /*!< 0x01000000 */
+#define LPTIM_ICR_DIEROKCF          LPTIM_ICR_DIEROKCF_Msk                     /*!< Interrupt enable register update OK clear flag */
+
+/******************  Bit definition for LPTIM_DIER register *******************/
+#define LPTIM_DIER_CC1IE_Pos        (0U)
+#define LPTIM_DIER_CC1IE_Msk        (0x1UL << LPTIM_DIER_CC1IE_Pos)            /*!< 0x00000001 */
+#define LPTIM_DIER_CC1IE            LPTIM_DIER_CC1IE_Msk                       /*!< Compare/Compare interrupt enable */
+#define LPTIM_DIER_ARRMIE_Pos        (1U)
+#define LPTIM_DIER_ARRMIE_Msk       (0x1UL << LPTIM_DIER_ARRMIE_Pos)           /*!< 0x00000002 */
+#define LPTIM_DIER_ARRMIE           LPTIM_DIER_ARRMIE_Msk                      /*!< Autoreload match Interrupt Enable */
+#define LPTIM_DIER_EXTTRIGIE_Pos    (2U)
+#define LPTIM_DIER_EXTTRIGIE_Msk    (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)        /*!< 0x00000004 */
+#define LPTIM_DIER_EXTTRIGIE        LPTIM_DIER_EXTTRIGIE_Msk                   /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_DIER_CMP1OKIE_Pos     (3U)
+#define LPTIM_DIER_CMP1OKIE_Msk     (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)         /*!< 0x00000008 */
+#define LPTIM_DIER_CMP1OKIE         LPTIM_DIER_CMP1OKIE_Msk                    /*!< Compare register 1 update OK interrupt enable */
+#define LPTIM_DIER_ARROKIE_Pos      (4U)
+#define LPTIM_DIER_ARROKIE_Msk      (0x1UL << LPTIM_DIER_ARROKIE_Pos)          /*!< 0x00000010 */
+#define LPTIM_DIER_ARROKIE          LPTIM_DIER_ARROKIE_Msk                     /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_DIER_UPIE_Pos         (5U)
+#define LPTIM_DIER_UPIE_Msk         (0x1UL << LPTIM_DIER_UPIE_Pos)             /*!< 0x00000020 */
+#define LPTIM_DIER_UPIE             LPTIM_DIER_UPIE_Msk                        /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_DIER_DOWNIE_Pos       (6U)
+#define LPTIM_DIER_DOWNIE_Msk       (0x1UL << LPTIM_DIER_DOWNIE_Pos)           /*!< 0x00000040 */
+#define LPTIM_DIER_DOWNIE           LPTIM_DIER_DOWNIE_Msk                      /*!< Counter direction change up to down Interrupt Enable */
+#define LPTIM_DIER_UEIE_Pos         (7U)
+#define LPTIM_DIER_UEIE_Msk         (0x1UL << LPTIM_DIER_UEIE_Pos)             /*!< 0x00000080 */
+#define LPTIM_DIER_UEIE             LPTIM_DIER_UEIE_Msk                        /*!< Update event Interrupt Enable */
+#define LPTIM_DIER_REPOKIE_Pos      (8U)
+#define LPTIM_DIER_REPOKIE_Msk      (0x1UL << LPTIM_DIER_REPOKIE_Pos)          /*!< 0x00000100 */
+#define LPTIM_DIER_REPOKIE          LPTIM_DIER_REPOKIE_Msk                     /*!< Repetition register update OK Interrupt Enable */
+#define LPTIM_DIER_CC2IE_Pos        (9U)
+#define LPTIM_DIER_CC2IE_Msk        (0x1UL << LPTIM_DIER_CC2IE_Pos)            /*!< 0x00000200 */
+#define LPTIM_DIER_CC2IE            LPTIM_DIER_CC2IE_Msk                       /*!< Capture/Compare 2 interrupt interrupt enable */
+#define LPTIM_DIER_CC1OIE_Pos       (12U)
+#define LPTIM_DIER_CC1OIE_Msk       (0x1UL << LPTIM_DIER_CC1OIE_Pos)           /*!< 0x00001000 */
+#define LPTIM_DIER_CC1OIE           LPTIM_DIER_CC1OIE_Msk                      /*!< Capture/Compare 1 over-capture interrupt enable */
+#define LPTIM_DIER_CC2OIE_Pos       (13U)
+#define LPTIM_DIER_CC2OIE_Msk       (0x1UL << LPTIM_DIER_CC2OIE_Pos)           /*!< 0x00002000 */
+#define LPTIM_DIER_CC2OIE           LPTIM_DIER_CC2OIE_Msk                      /*!< Capture/Compare 2 over-capture interrupt enable */
+#define LPTIM_DIER_CC1DE_Pos        (16U)
+#define LPTIM_DIER_CC1DE_Msk        (0x1UL << LPTIM_DIER_CC1DE_Pos)            /*!< 0x00010000 */
+#define LPTIM_DIER_CC1DE            LPTIM_DIER_CC1DE_Msk                       /*!< Capture/Compare 1 DMA request enable */
+#define LPTIM_DIER_CMP2OKIE_Pos     (19U)
+#define LPTIM_DIER_CMP2OKIE_Msk     (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)         /*!< 0x00080000 */
+#define LPTIM_DIER_CMP2OKIE         LPTIM_DIER_CMP2OKIE_Msk                    /*!< Compare register 2 update OK interrupt enable */
+#define LPTIM_DIER_UEDE_Pos         (23U)
+#define LPTIM_DIER_UEDE_Msk         (0x1UL << LPTIM_DIER_UEDE_Pos)             /*!< 0x00800000 */
+#define LPTIM_DIER_UEDE             LPTIM_DIER_UEDE_Msk                        /*!< Update event DMA request enable */
+#define LPTIM_DIER_CC2DE_Pos        (25U)
+#define LPTIM_DIER_CC2DE_Msk        (0x1UL << LPTIM_DIER_CC2DE_Pos)            /*!< 0x02000000 */
+#define LPTIM_DIER_CC2DE            LPTIM_DIER_CC2DE_Msk                       /*!< Capture/Compare 2 DMA request enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CCR1_CCR1_Pos           (0U)
+#define LPTIM_CCR1_CCR1_Msk           (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)        /*!< 0x0000FFFF */
+#define LPTIM_CCR1_CCR1               LPTIM_CCR1_CCR1_Msk                      /*!< Compare register 1 */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000020 */
+#define LPTIM_CFGR2_IC1SEL_Pos      (16U)
+#define LPTIM_CFGR2_IC1SEL_Msk      (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IC1SEL          LPTIM_CFGR2_IC1SEL_Msk                     /*!< IC1SEL[17:16] bits */
+#define LPTIM_CFGR2_IC1SEL_0        (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CFGR2_IC1SEL_1        (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)          /*!< 0x00020000 */
+#define LPTIM_CFGR2_IC2SEL_Pos      (20U)
+#define LPTIM_CFGR2_IC2SEL_Msk      (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IC2SEL          LPTIM_CFGR2_IC2SEL_Msk                     /*!< IC2SEL[21:20] bits */
+#define LPTIM_CFGR2_IC2SEL_0        (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00100000 */
+#define LPTIM_CFGR2_IC2SEL_1        (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)          /*!< 0x00200000 */
+
+/******************  Bit definition for LPTIM_RCR register  *******************/
+#define LPTIM_RCR_REP_Pos           (0U)
+#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
+#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!< Repetition Counter Value */
+
+/*****************  Bit definition for LPTIM_CCMR1 register  ******************/
+#define LPTIM_CCMR1_CC1SEL_Pos      (0U)
+#define LPTIM_CCMR1_CC1SEL_Msk      (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)          /*!< 0x00000001 */
+#define LPTIM_CCMR1_CC1SEL          LPTIM_CCMR1_CC1SEL_Msk                     /*!< Capture/Compare 1 selection */
+#define LPTIM_CCMR1_CC1E_Pos        (1U)
+#define LPTIM_CCMR1_CC1E_Msk        (0x1UL << LPTIM_CCMR1_CC1E_Pos)            /*!< 0x00000002 */
+#define LPTIM_CCMR1_CC1E            LPTIM_CCMR1_CC1E_Msk                       /*!< Capture/Compare 1 output enable */
+#define LPTIM_CCMR1_CC1P_Pos        (2U)
+#define LPTIM_CCMR1_CC1P_Msk        (0x3UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x0000000C */
+#define LPTIM_CCMR1_CC1P            LPTIM_CCMR1_CC1P_Msk                       /*!< Capture/Compare 1 output polarity */
+#define LPTIM_CCMR1_CC1P_0          (0x1UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000004 */
+#define LPTIM_CCMR1_CC1P_1          (0x2UL << LPTIM_CCMR1_CC1P_Pos)            /*!< 0x00000008 */
+#define LPTIM_CCMR1_IC1PSC_Pos      (8U)
+#define LPTIM_CCMR1_IC1PSC_Msk      (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000300 */
+#define LPTIM_CCMR1_IC1PSC          LPTIM_CCMR1_IC1PSC_Msk                     /*!< Input capture 1 prescaler */
+#define LPTIM_CCMR1_IC1PSC_0        (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000100 */
+#define LPTIM_CCMR1_IC1PSC_1        (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)          /*!< 0x00000200 */
+#define LPTIM_CCMR1_IC1F_Pos        (12U)
+#define LPTIM_CCMR1_IC1F_Msk        (0x3UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00003000 */
+#define LPTIM_CCMR1_IC1F            LPTIM_CCMR1_IC1F_Msk                       /*!< Input capture 1 filter */
+#define LPTIM_CCMR1_IC1F_0          (0x1UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00001000 */
+#define LPTIM_CCMR1_IC1F_1          (0x2UL << LPTIM_CCMR1_IC1F_Pos)            /*!< 0x00002000 */
+#define LPTIM_CCMR1_CC2SEL_Pos      (16U)
+#define LPTIM_CCMR1_CC2SEL_Msk      (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)          /*!< 0x00010000 */
+#define LPTIM_CCMR1_CC2SEL          LPTIM_CCMR1_CC2SEL_Msk                     /*!< Capture/Compare 2 selection */
+#define LPTIM_CCMR1_CC2E_Pos        (17U)
+#define LPTIM_CCMR1_CC2E_Msk        (0x1UL << LPTIM_CCMR1_CC2E_Pos)            /*!< 0x00020000 */
+#define LPTIM_CCMR1_CC2E            LPTIM_CCMR1_CC2E_Msk                       /*!< Capture/Compare 2 output enable */
+#define LPTIM_CCMR1_CC2P_Pos        (18U)
+#define LPTIM_CCMR1_CC2P_Msk        (0x3UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x000C0000 */
+#define LPTIM_CCMR1_CC2P            LPTIM_CCMR1_CC2P_Msk                       /*!< Capture/Compare 2 output polarity */
+#define LPTIM_CCMR1_CC2P_0          (0x1UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00040000 */
+#define LPTIM_CCMR1_CC2P_1          (0x2UL << LPTIM_CCMR1_CC2P_Pos)            /*!< 0x00080000 */
+#define LPTIM_CCMR1_IC2PSC_Pos      (24U)
+#define LPTIM_CCMR1_IC2PSC_Msk      (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x03000000 */
+#define LPTIM_CCMR1_IC2PSC          LPTIM_CCMR1_IC2PSC_Msk                     /*!< Input capture 2 prescaler */
+#define LPTIM_CCMR1_IC2PSC_0        (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x01000000 */
+#define LPTIM_CCMR1_IC2PSC_1        (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)          /*!< 0x02000000 */
+#define LPTIM_CCMR1_IC2F_Pos        (28U)
+#define LPTIM_CCMR1_IC2F_Msk        (0x3UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x30000000 */
+#define LPTIM_CCMR1_IC2F            LPTIM_CCMR1_IC2F_Msk                       /*!< Input capture 2 filter */
+#define LPTIM_CCMR1_IC2F_0          (0x1UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x10000000 */
+#define LPTIM_CCMR1_IC2F_1          (0x2UL << LPTIM_CCMR1_IC2F_Pos)            /*!< 0x20000000 */
+
+/******************  Bit definition for LPTIM_CCR2 register  ******************/
+#define LPTIM_CCR2_CCR2_Pos         (0U)
+#define LPTIM_CCR2_CCR2_Msk         (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)           /*!< 0x0000FFFF */
+#define LPTIM_CCR2_CCR2             LPTIM_CCR2_CCR2_Msk                         /*!< Compare register 2 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/* Bit fields for LTDC_SSCR register */
+#define LTDC_SSCR_VSH_Pos                (0U)
+#define LTDC_SSCR_VSH_Msk                (0xfffUL << LTDC_SSCR_VSH_Pos)
+#define LTDC_SSCR_VSH                    LTDC_SSCR_VSH_Msk  /*!< vertical synchronization height (in units of horizontal scan line)These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. */
+#define LTDC_SSCR_HSW_Pos                (16U)
+#define LTDC_SSCR_HSW_Msk                (0xfffUL << LTDC_SSCR_HSW_Pos)
+#define LTDC_SSCR_HSW                    LTDC_SSCR_HSW_Msk  /*!< horizontal synchronization width (in units of pixel clock period)These bits define the number of Horizontal Synchronization pixel minus 1. */
+
+/* Bit fields for LTDC_BPCR register */
+#define LTDC_BPCR_AVBP_Pos               (0U)
+#define LTDC_BPCR_AVBP_Msk               (0xfffUL << LTDC_BPCR_AVBP_Pos)
+#define LTDC_BPCR_AVBP                   LTDC_BPCR_AVBP_Msk  /*!< accumulated Vertical back porch (in units of horizontal scan line)These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1.The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. */
+#define LTDC_BPCR_AHBP_Pos               (16U)
+#define LTDC_BPCR_AHBP_Msk               (0xfffUL << LTDC_BPCR_AHBP_Pos)
+#define LTDC_BPCR_AHBP                   LTDC_BPCR_AHBP_Msk  /*!< accumulated horizontal back porch (in units of pixel clock period)These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1.The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. */
+
+/* Bit fields for LTDC_AWCR register */
+#define LTDC_AWCR_AAH_Pos                (0U)
+#define LTDC_AWCR_AAH_Msk                (0xfffUL << LTDC_AWCR_AAH_Pos)
+#define LTDC_AWCR_AAH                    LTDC_AWCR_AAH_Msk  /*!< accumulated active height (in units of horizontal scan line)These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel.Refer to device datasheet for maximum active height supported following maximum pixel clock. */
+#define LTDC_AWCR_AAW_Pos                (16U)
+#define LTDC_AWCR_AAW_Msk                (0xfffUL << LTDC_AWCR_AAW_Pos)
+#define LTDC_AWCR_AAW                    LTDC_AWCR_AAW_Msk  /*!< accumulated active width (in units of pixel clock period)These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1.The active width is the number of pixels in active display area of the panel scan line.Refer to device datasheet for maximum active width supported following maximum pixel clock. */
+
+/* Bit fields for LTDC_TWCR register */
+#define LTDC_TWCR_TOTALH_Pos             (0U)
+#define LTDC_TWCR_TOTALH_Msk             (0xfffUL << LTDC_TWCR_TOTALH_Pos)
+#define LTDC_TWCR_TOTALH                 LTDC_TWCR_TOTALH_Msk  /*!< total height (in units of horizontal scan line)These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. */
+#define LTDC_TWCR_TOTALW_Pos             (16U)
+#define LTDC_TWCR_TOTALW_Msk             (0xfffUL << LTDC_TWCR_TOTALW_Pos)
+#define LTDC_TWCR_TOTALW                 LTDC_TWCR_TOTALW_Msk  /*!< total width (in units of pixel clock period)These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. */
+
+/* Bit fields for LTDC_GCR register */
+#define LTDC_GCR_LTDCEN_Pos              (0U)
+#define LTDC_GCR_LTDCEN_Msk              (0x1UL << LTDC_GCR_LTDCEN_Pos)
+#define LTDC_GCR_LTDCEN                  LTDC_GCR_LTDCEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: LTDC disable- 1: LTDC enable */
+#define LTDC_GCR_GAMEN_Pos               (1U)
+#define LTDC_GCR_GAMEN_Msk               (0x1UL << LTDC_GCR_GAMEN_Pos)
+#define LTDC_GCR_GAMEN                   LTDC_GCR_GAMEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: GammaCorrection disable (pixels bypass the gamma operator)- 1: Gamma Correction enable */
+#define LTDC_GCR_ROTEN_Pos               (2U)
+#define LTDC_GCR_ROTEN_Msk               (0x1UL << LTDC_GCR_ROTEN_Pos)
+#define LTDC_GCR_ROTEN                   LTDC_GCR_ROTEN_Msk  /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: Rotation disable- 1: Rotation enable (for a pure visual rotation, the mirroring has to be activated) */
+#define LTDC_GCR_DBW_Pos                 (4U)
+#define LTDC_GCR_DBW_Msk                 (0x7UL << LTDC_GCR_DBW_Pos)
+#define LTDC_GCR_DBW                     LTDC_GCR_DBW_Msk  /*!< dither blue widthThese bits return the dither blue bits. */
+#define LTDC_GCR_DGW_Pos                 (8U)
+#define LTDC_GCR_DGW_Msk                 (0x7UL << LTDC_GCR_DGW_Pos)
+#define LTDC_GCR_DGW                     LTDC_GCR_DGW_Msk  /*!< dither green widthThese bits return the dither green bits. */
+#define LTDC_GCR_DRW_Pos                 (12U)
+#define LTDC_GCR_DRW_Msk                 (0x7UL << LTDC_GCR_DRW_Pos)
+#define LTDC_GCR_DRW                     LTDC_GCR_DRW_Msk  /*!< dither red widthThese bits return the Dither Red Bits. */
+#define LTDC_GCR_DEN_Pos                 (16U)
+#define LTDC_GCR_DEN_Msk                 (0x1UL << LTDC_GCR_DEN_Pos)
+#define LTDC_GCR_DEN                     LTDC_GCR_DEN_Msk  /*!< dither enableThis bit is set and cleared by software.- 0: dither disable- 1: dither enable */
+#define LTDC_GCR_BCKEN_Pos               (17U)
+#define LTDC_GCR_BCKEN_Msk               (0x1UL << LTDC_GCR_BCKEN_Pos)
+#define LTDC_GCR_BCKEN                   LTDC_GCR_BCKEN_Msk  /*!< backgroundlayer enableThis bit is set and cleared by software.- 0: backgrounddisable- 1: background enable */
+#define LTDC_GCR_CRCEN_Pos               (19U)
+#define LTDC_GCR_CRCEN_Msk               (0x1UL << LTDC_GCR_CRCEN_Pos)
+#define LTDC_GCR_CRCEN                   LTDC_GCR_CRCEN_Msk  /*!< CRC enableThis bit is set and cleared by software.- 0: CRC disable- 1: CRC enable */
+#define LTDC_GCR_SFEN_Pos                (24U)
+#define LTDC_GCR_SFEN_Msk                (0x1UL << LTDC_GCR_SFEN_Pos)
+#define LTDC_GCR_SFEN                    LTDC_GCR_SFEN_Msk  /*!< single-frame mode: mode enableThis bit is set and cleared by software.- 0: single-frame disable:a trigger (on SFSW or External) will generate a continuous flow.- 1: single-frame enable: a trigger (on SFSW or External) will generate a single frame. */
+#define LTDC_GCR_SFSWTR_Pos              (25U)
+#define LTDC_GCR_SFSWTR_Msk              (0x1UL << LTDC_GCR_SFSWTR_Pos)
+#define LTDC_GCR_SFSWTR                  LTDC_GCR_SFSWTR_Msk  /*!< single-frame mode: software triggerThis bit is set by software and cleared by hardware.- 0: no action- 1: triggers one frame */
+#define LTDC_GCR_SFEXEN_Pos              (26U)
+#define LTDC_GCR_SFEXEN_Msk              (0x1UL << LTDC_GCR_SFEXEN_Pos)
+#define LTDC_GCR_SFEXEN                  LTDC_GCR_SFEXEN_Msk  /*!< single-frame mode: external trigger enableThis bit is set and cleared by software.- 0: external trigger disable- 1: external trigger enable: a trigger on the external trigger will generate one single frame. */
+#define LTDC_GCR_PCPOL_Pos               (28U)
+#define LTDC_GCR_PCPOL_Msk               (0x1UL << LTDC_GCR_PCPOL_Pos)
+#define LTDC_GCR_PCPOL                   LTDC_GCR_PCPOL_Msk  /*!< pixel clock polarityThis bit is set and cleared by software.- 0: pixel clock polarity is active low.- 1: pixel clock is active high. */
+#define LTDC_GCR_DEPOL_Pos               (29U)
+#define LTDC_GCR_DEPOL_Msk               (0x1UL << LTDC_GCR_DEPOL_Pos)
+#define LTDC_GCR_DEPOL                   LTDC_GCR_DEPOL_Msk  /*!< blanking (=no data/pixel) polarityThis bit is set and cleared by software.- 0: blanking (no data/pixel) polarity is active low.- 1: blanking (no data/pixel) polarity is active high. */
+#define LTDC_GCR_VSPOL_Pos               (30U)
+#define LTDC_GCR_VSPOL_Msk               (0x1UL << LTDC_GCR_VSPOL_Pos)
+#define LTDC_GCR_VSPOL                   LTDC_GCR_VSPOL_Msk  /*!< vertical synchronization polarityThis bit is set and cleared by software.- 0: vertical synchronization is active low.- 1: vertical synchronization is active high. */
+#define LTDC_GCR_HSPOL_Pos               (31U)
+#define LTDC_GCR_HSPOL_Msk               (0x1UL << LTDC_GCR_HSPOL_Pos)
+#define LTDC_GCR_HSPOL                   LTDC_GCR_HSPOL_Msk  /*!< horizontal synchronization polarityThis bit is set and cleared by software.- 0: horizontal synchronization polarity is active low.- 1: horizontal synchronization polarity is active high. */
+
+/* Bit fields for LTDC_SRCR register */
+#define LTDC_SRCR_IMR_Pos                (0U)
+#define LTDC_SRCR_IMR_Msk                (0x1UL << LTDC_SRCR_IMR_Pos)
+#define LTDC_SRCR_IMR                    LTDC_SRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_SRCR_VBR_Pos                (1U)
+#define LTDC_SRCR_VBR_Msk                (0x1UL << LTDC_SRCR_VBR_Pos)
+#define LTDC_SRCR_VBR                    LTDC_SRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+
+/* Bit fields for LTDC_GCCR register */
+#define LTDC_GCCR_ADDR_Pos               (0U)
+#define LTDC_GCCR_ADDR_Msk               (0xffUL << LTDC_GCCR_ADDR_Pos)
+#define LTDC_GCCR_ADDR                   LTDC_GCCR_ADDR_Msk  /*!< address of the R,G,B table where the COMP component is written.When LTDC_GC1R.GCT=2, the gamma is implemented with 8 interpolated segment. In that case, the valid ADDR addresses are: 0, 32, 64, 96, 128, 160, 192, 224, 255.Note that for ADDR=255, the gamma interpolation hardware considers that the address is 256. */
+#define LTDC_GCCR_COMP_Pos               (8U)
+#define LTDC_GCCR_COMP_Msk               (0xffUL << LTDC_GCCR_COMP_Pos)
+#define LTDC_GCCR_COMP                   LTDC_GCCR_COMP_Msk  /*!< color component to be written, in either (or all) the R,G,B tables.. */
+#define LTDC_GCCR_BEN_Pos                (16U)
+#define LTDC_GCCR_BEN_Msk                (0x1UL << LTDC_GCCR_BEN_Pos)
+#define LTDC_GCCR_BEN                    LTDC_GCCR_BEN_Msk  /*!< write trigger to the blue table- 0: no action done- 1: COMP is written at ADDR in the Blue table. */
+#define LTDC_GCCR_GEN_Pos                (17U)
+#define LTDC_GCCR_GEN_Msk                (0x1UL << LTDC_GCCR_GEN_Pos)
+#define LTDC_GCCR_GEN                    LTDC_GCCR_GEN_Msk  /*!< write trigger to the green table- 0: no action done- 1: COMP is written at ADDR in the Green table. */
+#define LTDC_GCCR_REN_Pos                (18U)
+#define LTDC_GCCR_REN_Msk                (0x1UL << LTDC_GCCR_REN_Pos)
+#define LTDC_GCCR_REN                    LTDC_GCCR_REN_Msk  /*!< write trigger to the red table- 0: no action done- 1: COMP is written at ADDR in the Red table. */
+
+/* Bit fields for LTDC_BCCR register */
+#define LTDC_BCCR_BCBLUE_Pos             (0U)
+#define LTDC_BCCR_BCBLUE_Msk             (0xffUL << LTDC_BCCR_BCBLUE_Pos)
+#define LTDC_BCCR_BCBLUE                 LTDC_BCCR_BCBLUE_Msk  /*!< background color blue valueThese bits configure the background blue value. */
+#define LTDC_BCCR_BCGREEN_Pos            (8U)
+#define LTDC_BCCR_BCGREEN_Msk            (0xffUL << LTDC_BCCR_BCGREEN_Pos)
+#define LTDC_BCCR_BCGREEN                LTDC_BCCR_BCGREEN_Msk  /*!< background color green valueThese bits configure the background green value. */
+#define LTDC_BCCR_BCRED_Pos              (16U)
+#define LTDC_BCCR_BCRED_Msk              (0xffUL << LTDC_BCCR_BCRED_Pos)
+#define LTDC_BCCR_BCRED                  LTDC_BCCR_BCRED_Msk  /*!< background color red valueThese bits configure the background red value. */
+
+/* Bit fields for LTDC_IER register */
+#define LTDC_IER_LIE_Pos                 (0U)
+#define LTDC_IER_LIE_Msk                 (0x1UL << LTDC_IER_LIE_Pos)
+#define LTDC_IER_LIE                     LTDC_IER_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER_FUWIE_Pos               (1U)
+#define LTDC_IER_FUWIE_Msk               (0x1UL << LTDC_IER_FUWIE_Pos)
+#define LTDC_IER_FUWIE                   LTDC_IER_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER_TERRIE_Pos              (2U)
+#define LTDC_IER_TERRIE_Msk              (0x1UL << LTDC_IER_TERRIE_Pos)
+#define LTDC_IER_TERRIE                  LTDC_IER_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER_RRIE_Pos                (3U)
+#define LTDC_IER_RRIE_Msk                (0x1UL << LTDC_IER_RRIE_Pos)
+#define LTDC_IER_RRIE                    LTDC_IER_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER_FUIE_Pos                (6U)
+#define LTDC_IER_FUIE_Msk                (0x1UL << LTDC_IER_FUIE_Pos)
+#define LTDC_IER_FUIE                    LTDC_IER_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER_CRCIE_Pos               (7U)
+#define LTDC_IER_CRCIE_Msk               (0x1UL << LTDC_IER_CRCIE_Pos)
+#define LTDC_IER_CRCIE                   LTDC_IER_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+#define LTDC_IER_FURIE_Pos               (8U)
+#define LTDC_IER_FURIE_Msk               (0x1UL << LTDC_IER_FURIE_Pos)
+#define LTDC_IER_FURIE                   LTDC_IER_FURIE_Msk  /*!< FIFOunderrun at rotation interrupt enableThis bit is set and cleared by software.- 0: FIFOunderrun at rotation interrupt disable- 1: FIFO underrunat rotation interrupt enable */
+
+/* Bit fields for LTDC_ISR register */
+#define LTDC_ISR_LIF_Pos                 (0U)
+#define LTDC_ISR_LIF_Msk                 (0x1UL << LTDC_ISR_LIF_Pos)
+#define LTDC_ISR_LIF                     LTDC_ISR_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR_FUWIF_Pos               (1U)
+#define LTDC_ISR_FUWIF_Msk               (0x1UL << LTDC_ISR_FUWIF_Pos)
+#define LTDC_ISR_FUWIF                   LTDC_ISR_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR_TERRIF_Pos              (2U)
+#define LTDC_ISR_TERRIF_Msk              (0x1UL << LTDC_ISR_TERRIF_Pos)
+#define LTDC_ISR_TERRIF                  LTDC_ISR_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR_RRIF_Pos                (3U)
+#define LTDC_ISR_RRIF_Msk                (0x1UL << LTDC_ISR_RRIF_Pos)
+#define LTDC_ISR_RRIF                    LTDC_ISR_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR_FUIF_Pos                (6U)
+#define LTDC_ISR_FUIF_Msk                (0x1UL << LTDC_ISR_FUIF_Pos)
+#define LTDC_ISR_FUIF                    LTDC_ISR_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data is read from the FIFO */
+#define LTDC_ISR_CRCIF_Pos               (7U)
+#define LTDC_ISR_CRCIF_Msk               (0x1UL << LTDC_ISR_CRCIF_Pos)
+#define LTDC_ISR_CRCIF                   LTDC_ISR_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when the computed CRC is different from the expected CRC. */
+#define LTDC_ISR_FURIF_Pos               (8U)
+#define LTDC_ISR_FURIF_Msk               (0x1UL << LTDC_ISR_FURIF_Pos)
+#define LTDC_ISR_FURIF                   LTDC_ISR_FURIF_Msk  /*!< FIFO underrun at rotation interrupt flag- 0: no FIFO underrun at rotation interrupt generated- 1: FIFO underrun at rotation interrupt generated */
+
+/* Bit fields for LTDC_ICR register */
+#define LTDC_ICR_CLIF_Pos                (0U)
+#define LTDC_ICR_CLIF_Msk                (0x1UL << LTDC_ICR_CLIF_Pos)
+#define LTDC_ICR_CLIF                    LTDC_ICR_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFUWIF_Pos              (1U)
+#define LTDC_ICR_CFUWIF_Msk              (0x1UL << LTDC_ICR_CFUWIF_Pos)
+#define LTDC_ICR_CFUWIF                  LTDC_ICR_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CTERRIF_Pos             (2U)
+#define LTDC_ICR_CTERRIF_Msk             (0x1UL << LTDC_ICR_CTERRIF_Pos)
+#define LTDC_ICR_CTERRIF                 LTDC_ICR_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CRRIF_Pos               (3U)
+#define LTDC_ICR_CRRIF_Msk               (0x1UL << LTDC_ICR_CRRIF_Pos)
+#define LTDC_ICR_CRRIF                   LTDC_ICR_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR_CFUIF_Pos               (6U)
+#define LTDC_ICR_CFUIF_Msk               (0x1UL << LTDC_ICR_CFUIF_Pos)
+#define LTDC_ICR_CFUIF                   LTDC_ICR_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CCRCIF_Pos              (7U)
+#define LTDC_ICR_CCRCIF_Msk              (0x1UL << LTDC_ICR_CCRCIF_Pos)
+#define LTDC_ICR_CCRCIF                  LTDC_ICR_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+#define LTDC_ICR_CFURIF_Pos              (8U)
+#define LTDC_ICR_CFURIF_Msk              (0x1UL << LTDC_ICR_CFURIF_Pos)
+#define LTDC_ICR_CFURIF                  LTDC_ICR_CFURIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the FURIF flag in the LTDC_ISR register */
+
+/* Bit fields for LTDC_LIPCR register */
+#define LTDC_LIPCR_LIPOS_Pos             (0U)
+#define LTDC_LIPCR_LIPOS_Msk             (0xfffUL << LTDC_LIPCR_LIPOS_Pos)
+#define LTDC_LIPCR_LIPOS                 LTDC_LIPCR_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR register */
+#define LTDC_CPSR_CYPOS_Pos              (0U)
+#define LTDC_CPSR_CYPOS_Msk              (0xfffUL << LTDC_CPSR_CYPOS_Pos)
+#define LTDC_CPSR_CYPOS                  LTDC_CPSR_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR_CXPOS_Pos              (16U)
+#define LTDC_CPSR_CXPOS_Msk              (0xfffUL << LTDC_CPSR_CXPOS_Pos)
+#define LTDC_CPSR_CXPOS                  LTDC_CPSR_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_CDSR register */
+#define LTDC_CDSR_VDES_Pos               (0U)
+#define LTDC_CDSR_VDES_Msk               (0x1UL << LTDC_CDSR_VDES_Pos)
+#define LTDC_CDSR_VDES                   LTDC_CDSR_VDES_Msk  /*!< vertical data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HDES_Pos               (1U)
+#define LTDC_CDSR_HDES_Msk               (0x1UL << LTDC_CDSR_HDES_Pos)
+#define LTDC_CDSR_HDES                   LTDC_CDSR_HDES_Msk  /*!< horizontal data enable display status- 0: active low- 1: active high */
+#define LTDC_CDSR_VSYNCS_Pos             (2U)
+#define LTDC_CDSR_VSYNCS_Msk             (0x1UL << LTDC_CDSR_VSYNCS_Pos)
+#define LTDC_CDSR_VSYNCS                 LTDC_CDSR_VSYNCS_Msk  /*!< vertical synchronization display status- 0: active low- 1: active high */
+#define LTDC_CDSR_HSYNCS_Pos             (3U)
+#define LTDC_CDSR_HSYNCS_Msk             (0x1UL << LTDC_CDSR_HSYNCS_Pos)
+#define LTDC_CDSR_HSYNCS                 LTDC_CDSR_HSYNCS_Msk  /*!< horizontal synchronization display status- 0: active low- 1: active high */
+
+/* Bit fields for LTDC_EDCR register */
+#define LTDC_EDCR_OCYEN_Pos              (25U)
+#define LTDC_EDCR_OCYEN_Msk              (0x1UL << LTDC_EDCR_OCYEN_Pos)
+#define LTDC_EDCR_OCYEN                  LTDC_EDCR_OCYEN_Msk  /*!< output conversion to YCbCr 422: Enable- 0: conversion is disabled- 1: conversion is enabled */
+#define LTDC_EDCR_OCYSEL_Pos             (26U)
+#define LTDC_EDCR_OCYSEL_Msk             (0x1UL << LTDC_EDCR_OCYSEL_Pos)
+#define LTDC_EDCR_OCYSEL                 LTDC_EDCR_OCYSEL_Msk  /*!< output conversion to YCbCr 422: selection of the CCIR hard-wired coefficients:- 0: use CCIR-BT601 set (for typically SDTV analog-like displays)- 1: use CCIR-BT709 set (for typically HDTV digital-like displays) */
+#define LTDC_EDCR_OCYCO_Pos              (27U)
+#define LTDC_EDCR_OCYCO_Msk              (0x1UL << LTDC_EDCR_OCYCO_Pos)
+#define LTDC_EDCR_OCYCO                  LTDC_EDCR_OCYCO_Msk  /*!< output conversion to YCbCr 422: chrominance order.- 0: Cb is output first (so: Y0Cb, then Y1Cr, Y2Cb, etc .. ).- 1: Cr is output first (so: Y0Cr, then Y1Cb, Y2Cr, etc ..). */
+
+/* Bit fields for LTDC_IER2 register */
+#define LTDC_IER2_LIE_Pos                (0U)
+#define LTDC_IER2_LIE_Msk                (0x1UL << LTDC_IER2_LIE_Pos)
+#define LTDC_IER2_LIE                    LTDC_IER2_LIE_Msk  /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
+#define LTDC_IER2_FUWIE_Pos              (1U)
+#define LTDC_IER2_FUWIE_Msk              (0x1UL << LTDC_IER2_FUWIE_Pos)
+#define LTDC_IER2_FUWIE                  LTDC_IER2_FUWIE_Msk  /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
+#define LTDC_IER2_TERRIE_Pos             (2U)
+#define LTDC_IER2_TERRIE_Msk             (0x1UL << LTDC_IER2_TERRIE_Pos)
+#define LTDC_IER2_TERRIE                 LTDC_IER2_TERRIE_Msk  /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
+#define LTDC_IER2_RRIE_Pos               (3U)
+#define LTDC_IER2_RRIE_Msk               (0x1UL << LTDC_IER2_RRIE_Pos)
+#define LTDC_IER2_RRIE                   LTDC_IER2_RRIE_Msk  /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
+#define LTDC_IER2_FUIE_Pos               (6U)
+#define LTDC_IER2_FUIE_Msk               (0x1UL << LTDC_IER2_FUIE_Pos)
+#define LTDC_IER2_FUIE                   LTDC_IER2_FUIE_Msk  /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
+#define LTDC_IER2_CRCIE_Pos              (7U)
+#define LTDC_IER2_CRCIE_Msk              (0x1UL << LTDC_IER2_CRCIE_Pos)
+#define LTDC_IER2_CRCIE                  LTDC_IER2_CRCIE_Msk  /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
+
+/* Bit fields for LTDC_ISR2 register */
+#define LTDC_ISR2_LIF_Pos                (0U)
+#define LTDC_ISR2_LIF_Msk                (0x1UL << LTDC_ISR2_LIF_Pos)
+#define LTDC_ISR2_LIF                    LTDC_ISR2_LIF_Msk  /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
+#define LTDC_ISR2_FUWIF_Pos              (1U)
+#define LTDC_ISR2_FUWIF_Msk              (0x1UL << LTDC_ISR2_FUWIF_Pos)
+#define LTDC_ISR2_FUWIF                  LTDC_ISR2_FUWIF_Msk  /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
+#define LTDC_ISR2_TERRIF_Pos             (2U)
+#define LTDC_ISR2_TERRIF_Msk             (0x1UL << LTDC_ISR2_TERRIF_Pos)
+#define LTDC_ISR2_TERRIF                 LTDC_ISR2_TERRIF_Msk  /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
+#define LTDC_ISR2_RRIF_Pos               (3U)
+#define LTDC_ISR2_RRIF_Msk               (0x1UL << LTDC_ISR2_RRIF_Pos)
+#define LTDC_ISR2_RRIF                   LTDC_ISR2_RRIF_Msk  /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
+#define LTDC_ISR2_FUIF_Pos               (6U)
+#define LTDC_ISR2_FUIF_Msk               (0x1UL << LTDC_ISR2_FUIF_Pos)
+#define LTDC_ISR2_FUIF                   LTDC_ISR2_FUIF_Msk  /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO */
+#define LTDC_ISR2_CRCIF_Pos              (7U)
+#define LTDC_ISR2_CRCIF_Msk              (0x1UL << LTDC_ISR2_CRCIF_Pos)
+#define LTDC_ISR2_CRCIF                  LTDC_ISR2_CRCIF_Msk  /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when a bus error occurs */
+
+/* Bit fields for LTDC_ICR2 register */
+#define LTDC_ICR2_CLIF_Pos               (0U)
+#define LTDC_ICR2_CLIF_Msk               (0x1UL << LTDC_ICR2_CLIF_Pos)
+#define LTDC_ICR2_CLIF                   LTDC_ICR2_CLIF_Msk  /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CFUWIF_Pos             (1U)
+#define LTDC_ICR2_CFUWIF_Msk             (0x1UL << LTDC_ICR2_CFUWIF_Pos)
+#define LTDC_ICR2_CFUWIF                 LTDC_ICR2_CFUWIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CTERRIF_Pos            (2U)
+#define LTDC_ICR2_CTERRIF_Msk            (0x1UL << LTDC_ICR2_CTERRIF_Pos)
+#define LTDC_ICR2_CTERRIF                LTDC_ICR2_CTERRIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CRRIF_Pos              (3U)
+#define LTDC_ICR2_CRRIF_Msk              (0x1UL << LTDC_ICR2_CRRIF_Pos)
+#define LTDC_ICR2_CRRIF                  LTDC_ICR2_CRRIF_Msk  /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
+#define LTDC_ICR2_CFUIF_Pos              (6U)
+#define LTDC_ICR2_CFUIF_Msk              (0x1UL << LTDC_ICR2_CFUIF_Pos)
+#define LTDC_ICR2_CFUIF                  LTDC_ICR2_CFUIF_Msk  /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
+#define LTDC_ICR2_CCRCIF_Pos             (7U)
+#define LTDC_ICR2_CCRCIF_Msk             (0x1UL << LTDC_ICR2_CCRCIF_Pos)
+#define LTDC_ICR2_CCRCIF                 LTDC_ICR2_CCRCIF_Msk  /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
+
+/* Bit fields for LTDC_LIPCR2 register */
+#define LTDC_LIPCR2_LIPOS_Pos             (0U)
+#define LTDC_LIPCR2_LIPOS_Msk             (0xffffUL << LTDC_LIPCR2_LIPOS_Pos)
+#define LTDC_LIPCR2_LIPOS                 LTDC_LIPCR2_LIPOS_Msk  /*!< line interrupt positionThese bits configure the line interrupt position. */
+
+/* Bit fields for LTDC_CPSR2 register */
+#define LTDC_CPSR2_CYPOS_Pos             (0U)
+#define LTDC_CPSR2_CYPOS_Msk             (0xffffUL << LTDC_CPSR2_CYPOS_Pos)
+#define LTDC_CPSR2_CYPOS                 LTDC_CPSR2_CYPOS_Msk  /*!< current Y positionThese bits return the current Y position. */
+#define LTDC_CPSR2_CXPOS_Pos             (16U)
+#define LTDC_CPSR2_CXPOS_Msk             (0xffffUL << LTDC_CPSR2_CXPOS_Pos)
+#define LTDC_CPSR2_CXPOS                 LTDC_CPSR2_CXPOS_Msk  /*!< current X positionThese bits return the current X position. */
+
+/* Bit fields for LTDC_ECRCR register */
+#define LTDC_ECRCR_ECRC_Pos              (0U)
+#define LTDC_ECRCR_ECRC_Msk              (0xffffUL << LTDC_ECRCR_ECRC_Pos)
+#define LTDC_ECRCR_ECRC                  LTDC_ECRCR_ECRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_CCRCR register */
+#define LTDC_CCRCR_CCRC_Pos              (0U)
+#define LTDC_CCRCR_CCRC_Msk              (0xffffUL << LTDC_CCRCR_CCRC_Pos)
+#define LTDC_CCRCR_CCRC                  LTDC_CCRCR_CCRC_Msk  /*!< expected CRC of frame */
+
+/* Bit fields for LTDC_FUTR register */
+#define LTDC_FUTR_THRE_Pos               (0U)
+#define LTDC_FUTR_THRE_Msk               (0xffffUL << LTDC_FUTR_THRE_Pos)
+#define LTDC_FUTR_THRE                   LTDC_FUTR_THRE_Msk  /*!< threshold to trigger a FIFO underrun killing interrupt (unit is per fifo word, 64bit) */
+
+/* Bit fields for LTDC_LxC0R register */
+#define LTDC_LxC0R_CKTA_Pos              (0U)
+#define LTDC_LxC0R_CKTA_Msk              (0x1UL << LTDC_LxC0R_CKTA_Pos)
+#define LTDC_LxC0R_CKTA                  LTDC_LxC0R_CKTA_Msk  /*!< color key transparency Ability */
+#define LTDC_LxC0R_CFBDA_Pos             (1U)
+#define LTDC_LxC0R_CFBDA_Msk             (0x1UL << LTDC_LxC0R_CFBDA_Pos)
+#define LTDC_LxC0R_CFBDA                 LTDC_LxC0R_CFBDA_Msk  /*!< color frame buffer duplication ability */
+#define LTDC_LxC0R_CFBPA_Pos             (2U)
+#define LTDC_LxC0R_CFBPA_Msk             (0x1UL << LTDC_LxC0R_CFBPA_Pos)
+#define LTDC_LxC0R_CFBPA                 LTDC_LxC0R_CFBPA_Msk  /*!< color frame buffer pitch ability */
+#define LTDC_LxC0R_APA_Pos               (3U)
+#define LTDC_LxC0R_APA_Msk               (0x1UL << LTDC_LxC0R_APA_Pos)
+#define LTDC_LxC0R_APA                   LTDC_LxC0R_APA_Msk  /*!< alpha plane ability */
+#define LTDC_LxC0R_DCP_Pos               (4U)
+#define LTDC_LxC0R_DCP_Msk               (0x1UL << LTDC_LxC0R_DCP_Pos)
+#define LTDC_LxC0R_DCP                   LTDC_LxC0R_DCP_Msk  /*!< default color programmability */
+#define LTDC_LxC0R_WINA_Pos              (5U)
+#define LTDC_LxC0R_WINA_Msk              (0x1UL << LTDC_LxC0R_WINA_Pos)
+#define LTDC_LxC0R_WINA                  LTDC_LxC0R_WINA_Msk  /*!< windowing ability */
+#define LTDC_LxC0R_CLUTA_Pos             (6U)
+#define LTDC_LxC0R_CLUTA_Msk             (0x1UL << LTDC_LxC0R_CLUTA_Pos)
+#define LTDC_LxC0R_CLUTA                 LTDC_LxC0R_CLUTA_Msk  /*!< CLUT ability */
+#define LTDC_LxC0R_CKRA_Pos              (7U)
+#define LTDC_LxC0R_CKRA_Msk              (0x1UL << LTDC_LxC0R_CKRA_Pos)
+#define LTDC_LxC0R_CKRA                  LTDC_LxC0R_CKRA_Msk  /*!< color key replace ability */
+#define LTDC_LxC0R_F21_Pos               (8U)
+#define LTDC_LxC0R_F21_Msk               (0x1UL << LTDC_LxC0R_F21_Pos)
+#define LTDC_LxC0R_F21                   LTDC_LxC0R_F21_Msk  /*!< blending factor 2, ability for: 1.0 */
+#define LTDC_LxC0R_F20_Pos               (9U)
+#define LTDC_LxC0R_F20_Msk               (0x1UL << LTDC_LxC0R_F20_Pos)
+#define LTDC_LxC0R_F20                   LTDC_LxC0R_F20_Msk  /*!< blending factor 2, ability for: 0.0 */
+#define LTDC_LxC0R_F2P_Pos               (10U)
+#define LTDC_LxC0R_F2P_Msk               (0x1UL << LTDC_LxC0R_F2P_Pos)
+#define LTDC_LxC0R_F2P                   LTDC_LxC0R_F2P_Msk  /*!< blending factor 2, ability for: pixel_alpha */
+#define LTDC_LxC0R_F21P_Pos              (11U)
+#define LTDC_LxC0R_F21P_Msk              (0x1UL << LTDC_LxC0R_F21P_Pos)
+#define LTDC_LxC0R_F21P                  LTDC_LxC0R_F21P_Msk  /*!< blending factor 2, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F2C_Pos               (12U)
+#define LTDC_LxC0R_F2C_Msk               (0x1UL << LTDC_LxC0R_F2C_Pos)
+#define LTDC_LxC0R_F2C                   LTDC_LxC0R_F2C_Msk  /*!< blending factor 2, ability for: constant_alpha */
+#define LTDC_LxC0R_F21C_Pos              (13U)
+#define LTDC_LxC0R_F21C_Msk              (0x1UL << LTDC_LxC0R_F21C_Pos)
+#define LTDC_LxC0R_F21C                  LTDC_LxC0R_F21C_Msk  /*!< blending factor 2, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F2PC_Pos              (14U)
+#define LTDC_LxC0R_F2PC_Msk              (0x1UL << LTDC_LxC0R_F2PC_Pos)
+#define LTDC_LxC0R_F2PC                  LTDC_LxC0R_F2PC_Msk  /*!< blending factor 2, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F21PC_Pos             (15U)
+#define LTDC_LxC0R_F21PC_Msk             (0x1UL << LTDC_LxC0R_F21PC_Pos)
+#define LTDC_LxC0R_F21PC                 LTDC_LxC0R_F21PC_Msk  /*!< blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_F11_Pos               (16U)
+#define LTDC_LxC0R_F11_Msk               (0x1UL << LTDC_LxC0R_F11_Pos)
+#define LTDC_LxC0R_F11                   LTDC_LxC0R_F11_Msk  /*!< blending factor 1, ability for: 1.0 */
+#define LTDC_LxC0R_F10_Pos               (17U)
+#define LTDC_LxC0R_F10_Msk               (0x1UL << LTDC_LxC0R_F10_Pos)
+#define LTDC_LxC0R_F10                   LTDC_LxC0R_F10_Msk  /*!< blending factor 1,ability for: 0.0 */
+#define LTDC_LxC0R_F1P_Pos               (18U)
+#define LTDC_LxC0R_F1P_Msk               (0x1UL << LTDC_LxC0R_F1P_Pos)
+#define LTDC_LxC0R_F1P                   LTDC_LxC0R_F1P_Msk  /*!< blending factor 1, ability for: pixel_alpha */
+#define LTDC_LxC0R_F11P_Pos              (19U)
+#define LTDC_LxC0R_F11P_Msk              (0x1UL << LTDC_LxC0R_F11P_Pos)
+#define LTDC_LxC0R_F11P                  LTDC_LxC0R_F11P_Msk  /*!< blending factor 1, ability for: 1.0 - pixel_alpha */
+#define LTDC_LxC0R_F1C_Pos               (20U)
+#define LTDC_LxC0R_F1C_Msk               (0x1UL << LTDC_LxC0R_F1C_Pos)
+#define LTDC_LxC0R_F1C                   LTDC_LxC0R_F1C_Msk  /*!< blending factor 1, ability for: constant_alpha */
+#define LTDC_LxC0R_F11C_Pos              (21U)
+#define LTDC_LxC0R_F11C_Msk              (0x1UL << LTDC_LxC0R_F11C_Pos)
+#define LTDC_LxC0R_F11C                  LTDC_LxC0R_F11C_Msk  /*!< blending factor 1, ability for: 1.0 - constant_alpha */
+#define LTDC_LxC0R_F1PC_Pos              (22U)
+#define LTDC_LxC0R_F1PC_Msk              (0x1UL << LTDC_LxC0R_F1PC_Pos)
+#define LTDC_LxC0R_F1PC                  LTDC_LxC0R_F1PC_Msk  /*!< blending factor 1, ability for: pixel_alpha * constant_alpha */
+#define LTDC_LxC0R_F11PC_Pos             (23U)
+#define LTDC_LxC0R_F11PC_Msk             (0x1UL << LTDC_LxC0R_F11PC_Pos)
+#define LTDC_LxC0R_F11PC                 LTDC_LxC0R_F11PC_Msk  /*!< blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) */
+#define LTDC_LxC0R_P88_Pos               (24U)
+#define LTDC_LxC0R_P88_Msk               (0x1UL << LTDC_LxC0R_P88_Pos)
+#define LTDC_LxC0R_P88                   LTDC_LxC0R_P88_Msk  /*!< pixel format, ability for: AL88. */
+#define LTDC_LxC0R_P44_Pos               (25U)
+#define LTDC_LxC0R_P44_Msk               (0x1UL << LTDC_LxC0R_P44_Pos)
+#define LTDC_LxC0R_P44                   LTDC_LxC0R_P44_Msk  /*!< pixel format, ability for: AL44. */
+#define LTDC_LxC0R_P8_Pos                (26U)
+#define LTDC_LxC0R_P8_Msk                (0x1UL << LTDC_LxC0R_P8_Pos)
+#define LTDC_LxC0R_P8                    LTDC_LxC0R_P8_Msk  /*!< pixel format, ability for: L8. */
+#define LTDC_LxC0R_P4444_Pos             (27U)
+#define LTDC_LxC0R_P4444_Msk             (0x1UL << LTDC_LxC0R_P4444_Pos)
+#define LTDC_LxC0R_P4444                 LTDC_LxC0R_P4444_Msk  /*!< pixel format, ability for: ARGB4444. */
+#define LTDC_LxC0R_P1555_Pos             (28U)
+#define LTDC_LxC0R_P1555_Msk             (0x1UL << LTDC_LxC0R_P1555_Pos)
+#define LTDC_LxC0R_P1555                 LTDC_LxC0R_P1555_Msk  /*!< pixel format, ability for: ARGB1555. */
+#define LTDC_LxC0R_P565_Pos              (29U)
+#define LTDC_LxC0R_P565_Msk              (0x1UL << LTDC_LxC0R_P565_Pos)
+#define LTDC_LxC0R_P565                  LTDC_LxC0R_P565_Msk  /*!< pixel format, ability for: RGB565. */
+#define LTDC_LxC0R_P888_Pos              (30U)
+#define LTDC_LxC0R_P888_Msk              (0x1UL << LTDC_LxC0R_P888_Pos)
+#define LTDC_LxC0R_P888                  LTDC_LxC0R_P888_Msk  /*!< pixel format, ability for: RGB888. */
+#define LTDC_LxC0R_P8888_Pos             (31U)
+#define LTDC_LxC0R_P8888_Msk             (0x1UL << LTDC_LxC0R_P8888_Pos)
+#define LTDC_LxC0R_P8888                 LTDC_LxC0R_P8888_Msk  /*!< pixel format, ability for: ARGB8888. */
+
+/* Bit fields for LTDC_LxC1R register */
+#define LTDC_LxC1R_YIA_Pos               (0U)
+#define LTDC_LxC1R_YIA_Msk               (0x1UL << LTDC_LxC1R_YIA_Pos)
+#define LTDC_LxC1R_YIA                   LTDC_LxC1R_YIA_Msk  /*!< YCbCr 422 interleaved ability for that layer.- 0: interleaved not available- 1: interleaved available */
+#define LTDC_LxC1R_YSPA_Pos              (1U)
+#define LTDC_LxC1R_YSPA_Msk              (0x1UL << LTDC_LxC1R_YSPA_Pos)
+#define LTDC_LxC1R_YSPA                  LTDC_LxC1R_YSPA_Msk  /*!< YCbCr 420 semi-planar ability for that layer.- 0: semiplanar not available- 1: semi-planar available */
+#define LTDC_LxC1R_YFPA_Pos              (2U)
+#define LTDC_LxC1R_YFPA_Msk              (0x1UL << LTDC_LxC1R_YFPA_Pos)
+#define LTDC_LxC1R_YFPA                  LTDC_LxC1R_YFPA_Msk  /*!< YCbCr 420 full-planar ability for that layer.- 0: full planar not available- 1: full planar available */
+#define LTDC_LxC1R_SCA_Pos               (31U)
+#define LTDC_LxC1R_SCA_Msk               (0x1UL << LTDC_LxC1R_SCA_Pos)
+#define LTDC_LxC1R_SCA                   LTDC_LxC1R_SCA_Msk  /*!< scaling ability for that layer.- 0: scaling not available- 1: scaling available */
+
+/* Bit fields for LTDC_LxRCR register */
+#define LTDC_LxRCR_IMR_Pos               (0U)
+#define LTDC_LxRCR_IMR_Msk               (0x1UL << LTDC_LxRCR_IMR_Pos)
+#define LTDC_LxRCR_IMR                   LTDC_LxRCR_IMR_Msk  /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
+#define LTDC_LxRCR_VBR_Pos               (1U)
+#define LTDC_LxRCR_VBR_Msk               (0x1UL << LTDC_LxRCR_VBR_Pos)
+#define LTDC_LxRCR_VBR                   LTDC_LxRCR_VBR_Msk  /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
+#define LTDC_LxRCR_GRMSK_Pos             (2U)
+#define LTDC_LxRCR_GRMSK_Msk             (0x1UL << LTDC_LxRCR_GRMSK_Pos)
+#define LTDC_LxRCR_GRMSK                 LTDC_LxRCR_GRMSK_Msk  /*!< shadow reload control: global (centralized) reload maskedThis bit is set and cleared by software.- 0: global reload active (the control from the LTDC_SRCR are enabled)- 1: global reload is masked (the control from the LTDC_SRCR are disabled) */
+
+/* Bit fields for LTDC_LxCR register */
+#define LTDC_LxCR_LEN_Pos                (0U)
+#define LTDC_LxCR_LEN_Msk                (0x1UL << LTDC_LxCR_LEN_Pos)
+#define LTDC_LxCR_LEN                    LTDC_LxCR_LEN_Msk  /*!< layer enable: the bit is used to enable/disable the presence of this whole layer.This bit is set and cleared by software.- 0: layer disabled- 1: layer enabled */
+#define LTDC_LxCR_CKEN_Pos               (1U)
+#define LTDC_LxCR_CKEN_Msk               (0x1UL << LTDC_LxCR_CKEN_Pos)
+#define LTDC_LxCR_CKEN                   LTDC_LxCR_CKEN_Msk  /*!< color keying enableThis bit is set and cleared by software.- 0: color keying disabled- 1: color keying enabled: if RGB matches, then the ARGB are set to 0. */
+#define LTDC_LxCR_VPDEN_Pos              (2U)
+#define LTDC_LxCR_VPDEN_Msk              (0x1UL << LTDC_LxCR_VPDEN_Pos)
+#define LTDC_LxCR_VPDEN                  LTDC_LxCR_VPDEN_Msk  /*!< vertical pixel duplication enableThis bit is set and cleared by software.- 0: duplication disabled- 1: duplication enabled */
+#define LTDC_LxCR_CLUTEN_Pos             (4U)
+#define LTDC_LxCR_CLUTEN_Msk             (0x1UL << LTDC_LxCR_CLUTEN_Pos)
+#define LTDC_LxCR_CLUTEN                 LTDC_LxCR_CLUTEN_Msk  /*!< color look-up table enableThis bit is set and cleared by software.- 0: color look-up table disabled- 1: color look-up table enabledThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up table (CLUT) */
+#define LTDC_LxCR_HMEN_Pos               (8U)
+#define LTDC_LxCR_HMEN_Msk               (0x1UL << LTDC_LxCR_HMEN_Pos)
+#define LTDC_LxCR_HMEN                   LTDC_LxCR_HMEN_Msk  /*!< horizontal mirroring enableThis bit is set and cleared by software.- 0: mirror disabled- 1: mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instannce: if line is 100 pixels, 24bpp, then address is set to 299) */
+#define LTDC_LxCR_DCBEN_Pos              (9U)
+#define LTDC_LxCR_DCBEN_Msk              (0x1UL << LTDC_LxCR_DCBEN_Pos)
+#define LTDC_LxCR_DCBEN                  LTDC_LxCR_DCBEN_Msk  /*!< default color blending enableThis bit is set and cleared by software.- 0: blending disabled- 1: blending enabled */
+
+/* Bit fields for LTDC_LxWHPCR register */
+#define LTDC_LxWHPCR_WHSTPOS_Pos         (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSTPOS_Pos)
+#define LTDC_LxWHPCR_WHSTPOS             LTDC_LxWHPCR_WHSTPOS_Msk  /*!< window horizontal start positionThese bits configure the first visible pixel of a line of the layer window.WHSTPOS[15:0] must be >= AAW[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWHPCR_WHSPPOS_Pos         (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk         (0xfffUL << LTDC_LxWHPCR_WHSPPOS_Pos)
+#define LTDC_LxWHPCR_WHSPPOS             LTDC_LxWHPCR_WHSPPOS_Msk  /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxWVPCR register */
+#define LTDC_LxWVPCR_WVSTPOS_Pos         (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSTPOS_Pos)
+#define LTDC_LxWVPCR_WVSTPOS             LTDC_LxWVPCR_WVSTPOS_Msk  /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */
+#define LTDC_LxWVPCR_WVSPPOS_Pos         (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk         (0xfffUL << LTDC_LxWVPCR_WVSPPOS_Pos)
+#define LTDC_LxWVPCR_WVSPPOS             LTDC_LxWVPCR_WVSPPOS_Msk  /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
+
+/* Bit fields for LTDC_LxCKCR register */
+#define LTDC_LxCKCR_CKBLUE_Pos           (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk           (0xffUL << LTDC_LxCKCR_CKBLUE_Pos)
+#define LTDC_LxCKCR_CKBLUE               LTDC_LxCKCR_CKBLUE_Msk  /*!< color key blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos          (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk          (0xffUL << LTDC_LxCKCR_CKGREEN_Pos)
+#define LTDC_LxCKCR_CKGREEN              LTDC_LxCKCR_CKGREEN_Msk  /*!< color key green value */
+#define LTDC_LxCKCR_CKRED_Pos            (16U)
+#define LTDC_LxCKCR_CKRED_Msk            (0xffUL << LTDC_LxCKCR_CKRED_Pos)
+#define LTDC_LxCKCR_CKRED                LTDC_LxCKCR_CKRED_Msk  /*!< color key red value */
+
+/* Bit fields for LTDC_LxPFCR register */
+#define LTDC_LxPFCR_PF_Pos               (0U)
+#define LTDC_LxPFCR_PF_Msk               (0x7UL << LTDC_LxPFCR_PF_Pos)
+#define LTDC_LxPFCR_PF                   LTDC_LxPFCR_PF_Msk  /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */
+
+/* Bit fields for LTDC_LxCACR register */
+#define LTDC_LxCACR_CONSTA_Pos           (0U)
+#define LTDC_LxCACR_CONSTA_Msk           (0xffUL << LTDC_LxCACR_CONSTA_Pos)
+#define LTDC_LxCACR_CONSTA               LTDC_LxCACR_CONSTA_Msk  /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */
+
+/* Bit fields for LTDC_LxDCCR register */
+#define LTDC_LxDCCR_DCBLUE_Pos           (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk           (0xffUL << LTDC_LxDCCR_DCBLUE_Pos)
+#define LTDC_LxDCCR_DCBLUE               LTDC_LxDCCR_DCBLUE_Msk  /*!< default color blueThese bits configure the default blue value. */
+#define LTDC_LxDCCR_DCGREEN_Pos          (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk          (0xffUL << LTDC_LxDCCR_DCGREEN_Pos)
+#define LTDC_LxDCCR_DCGREEN              LTDC_LxDCCR_DCGREEN_Msk  /*!< default color greenThese bits configure the default green value. */
+#define LTDC_LxDCCR_DCRED_Pos            (16U)
+#define LTDC_LxDCCR_DCRED_Msk            (0xffUL << LTDC_LxDCCR_DCRED_Pos)
+#define LTDC_LxDCCR_DCRED                LTDC_LxDCCR_DCRED_Msk  /*!< default color redThese bits configure the default red value. */
+#define LTDC_LxDCCR_DCALPHA_Pos          (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk          (0xffUL << LTDC_LxDCCR_DCALPHA_Pos)
+#define LTDC_LxDCCR_DCALPHA              LTDC_LxDCCR_DCALPHA_Msk  /*!< default color alphaThese bits configure the default alpha value. */
+
+/* Bit fields for LTDC_LxBFCR register */
+#define LTDC_LxBFCR_BF2_Pos              (0U)
+#define LTDC_LxBFCR_BF2_Msk              (0x7UL << LTDC_LxBFCR_BF2_Pos)
+#define LTDC_LxBFCR_BF2                  LTDC_LxBFCR_BF2_Msk  /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */
+#define LTDC_LxBFCR_BF1_Pos              (8U)
+#define LTDC_LxBFCR_BF1_Msk              (0x7UL << LTDC_LxBFCR_BF1_Pos)
+#define LTDC_LxBFCR_BF1                  LTDC_LxBFCR_BF1_Msk  /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */
+#define LTDC_LxBFCR_BOR_Pos              (16U)
+#define LTDC_LxBFCR_BOR_Msk              (0x1UL << LTDC_LxBFCR_BOR_Pos)
+#define LTDC_LxBFCR_BOR                  LTDC_LxBFCR_BOR_Msk  /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */
+
+/* Bit fields for LTDC_LxBLCR register */
+#define LTDC_LxBLCR_BL_Pos               (0U)
+#define LTDC_LxBLCR_BL_Msk               (0x1fUL << LTDC_LxBLCR_BL_Pos)
+#define LTDC_LxBLCR_BL                   LTDC_LxBLCR_BL_Msk  /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */
+
+/* Bit fields for LTDC_LxPCR register */
+#define LTDC_LxPCR_YCEN_Pos              (3U)
+#define LTDC_LxPCR_YCEN_Msk              (0x1UL << LTDC_LxPCR_YCEN_Pos)
+#define LTDC_LxPCR_YCEN                  LTDC_LxPCR_YCEN_Msk  /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */
+#define LTDC_LxPCR_YCM_Pos               (4U)
+#define LTDC_LxPCR_YCM_Msk               (0x3UL << LTDC_LxPCR_YCM_Pos)
+#define LTDC_LxPCR_YCM                   LTDC_LxPCR_YCM_Msk  /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */
+#define LTDC_LxPCR_YF_Pos                (6U)
+#define LTDC_LxPCR_YF_Msk                (0x1UL << LTDC_LxPCR_YF_Pos)
+#define LTDC_LxPCR_YF                    LTDC_LxPCR_YF_Msk  /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */
+#define LTDC_LxPCR_CBF_Pos               (7U)
+#define LTDC_LxPCR_CBF_Msk               (0x1UL << LTDC_LxPCR_CBF_Pos)
+#define LTDC_LxPCR_CBF                   LTDC_LxPCR_CBF_Msk  /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */
+#define LTDC_LxPCR_OF_Pos                (8U)
+#define LTDC_LxPCR_OF_Msk                (0x1UL << LTDC_LxPCR_OF_Pos)
+#define LTDC_LxPCR_OF                    LTDC_LxPCR_OF_Msk  /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */
+#define LTDC_LxPCR_YREN_Pos              (9U)
+#define LTDC_LxPCR_YREN_Msk              (0x1UL << LTDC_LxPCR_YREN_Pos)
+#define LTDC_LxPCR_YREN                  LTDC_LxPCR_YREN_Msk  /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */
+
+/* Bit fields for LTDC_LxCFBAR register */
+#define LTDC_LxCFBAR_CFBADD_Pos          (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk          (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos)
+#define LTDC_LxCFBAR_CFBADD              LTDC_LxCFBAR_CFBADD_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxCFBLR register */
+#define LTDC_LxCFBLR_CFBLL_Pos           (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk           (0x3fffUL << LTDC_LxCFBLR_CFBLL_Pos)
+#define LTDC_LxCFBLR_CFBLL               LTDC_LxCFBLR_CFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_LxCFBLR_CFBP_Pos            (16U)
+#define LTDC_LxCFBLR_CFBP_Msk            (0x7fffUL << LTDC_LxCFBLR_CFBP_Pos)
+#define LTDC_LxCFBLR_CFBP                LTDC_LxCFBLR_CFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxCFBLNR register */
+#define LTDC_LxCFBLNR_CFBLNBR_Pos        (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk        (0xfffUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
+#define LTDC_LxCFBLNR_CFBLNBR            LTDC_LxCFBLNR_CFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_L1AFBA0R register */
+#define LTDC_L1AFBA0R_AFBADD0_Pos        (0U)
+#define LTDC_L1AFBA0R_AFBADD0_Msk        (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos)
+#define LTDC_L1AFBA0R_AFBADD0            LTDC_L1AFBA0R_AFBADD0_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBA1R register */
+#define LTDC_L1AFBA1R_AFBADD1_Pos        (0U)
+#define LTDC_L1AFBA1R_AFBADD1_Msk        (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos)
+#define LTDC_L1AFBA1R_AFBADD1            LTDC_L1AFBA1R_AFBADD1_Msk  /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
+
+/* Bit fields for LTDC_LxAFBLR register */
+#define LTDC_L1AFBLR_AFBLL_Pos           (0U)
+#define LTDC_L1AFBLR_AFBLL_Msk           (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos)
+#define LTDC_L1AFBLR_AFBLL               LTDC_L1AFBLR_AFBLL_Msk  /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
+#define LTDC_L1AFBLR_AFBP_Pos            (16U)
+#define LTDC_L1AFBLR_AFBP_Msk            (0xffffUL << LTDC_L1AFBLR_AFBP_Pos)
+#define LTDC_L1AFBLR_AFBP                LTDC_L1AFBLR_AFBP_Msk  /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
+
+/* Bit fields for LTDC_LxAFBLNR register */
+#define LTDC_L1AFBLNR_AFBLNBR_Pos        (0U)
+#define LTDC_L1AFBLNR_AFBLNBR_Msk        (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos)
+#define LTDC_L1AFBLNR_AFBLNBR            LTDC_L1AFBLNR_AFBLNBR_Msk  /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
+
+/* Bit fields for LTDC_LxCLUTWR register */
+#define LTDC_LxCLUTWR_BLUE_Pos           (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk           (0xffUL << LTDC_LxCLUTWR_BLUE_Pos)
+#define LTDC_LxCLUTWR_BLUE               LTDC_LxCLUTWR_BLUE_Msk  /*!< blue valueThese bits configure the blue value. */
+#define LTDC_LxCLUTWR_GREEN_Pos          (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk          (0xffUL << LTDC_LxCLUTWR_GREEN_Pos)
+#define LTDC_LxCLUTWR_GREEN              LTDC_LxCLUTWR_GREEN_Msk  /*!< green valueThese bits configure the green value. */
+#define LTDC_LxCLUTWR_RED_Pos            (16U)
+#define LTDC_LxCLUTWR_RED_Msk            (0xffUL << LTDC_LxCLUTWR_RED_Pos)
+#define LTDC_LxCLUTWR_RED                LTDC_LxCLUTWR_RED_Msk  /*!< red valueThese bits configure the red value. */
+#define LTDC_LxCLUTWR_CLUTADD_Pos        (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk        (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos)
+#define LTDC_LxCLUTWR_CLUTADD            LTDC_LxCLUTWR_CLUTADD_Msk  /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */
+
+/* Bit fields for LTDC_LxCYR0R register */
+#define LTDC_LxCYR0R_CR2R_Pos            (0U)
+#define LTDC_LxCYR0R_CR2R_Msk            (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos)
+#define LTDC_LxCYR0R_CR2R                LTDC_LxCYR0R_CR2R_Msk  /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR0R_CB2B_Pos            (16U)
+#define LTDC_LxCYR0R_CB2B_Msk            (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos)
+#define LTDC_LxCYR0R_CB2B                LTDC_LxCYR0R_CB2B_Msk  /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxCYR1R register */
+#define LTDC_LxCYR1R_CR2G_Pos            (0U)
+#define LTDC_LxCYR1R_CR2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos)
+#define LTDC_LxCYR1R_CR2G                LTDC_LxCYR1R_CR2G_Msk  /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+#define LTDC_LxCYR1R_CB2G_Pos            (16U)
+#define LTDC_LxCYR1R_CB2G_Msk            (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos)
+#define LTDC_LxCYR1R_CB2G                LTDC_LxCYR1R_CB2G_Msk  /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
+
+/* Bit fields for LTDC_LxFPF0R register */
+#define LTDC_LxFPF0R_APOS_Pos            (0U)
+#define LTDC_LxFPF0R_APOS_Msk            (0x1fUL << LTDC_LxFPF0R_APOS_Pos)
+#define LTDC_LxFPF0R_APOS                LTDC_LxFPF0R_APOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_ALEN_Pos            (5U)
+#define LTDC_LxFPF0R_ALEN_Msk            (0xfUL << LTDC_LxFPF0R_ALEN_Pos)
+#define LTDC_LxFPF0R_ALEN                LTDC_LxFPF0R_ALEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF0R_RPOS_Pos            (9U)
+#define LTDC_LxFPF0R_RPOS_Msk            (0x1fUL << LTDC_LxFPF0R_RPOS_Pos)
+#define LTDC_LxFPF0R_RPOS                LTDC_LxFPF0R_RPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF0R_RLEN_Pos            (14U)
+#define LTDC_LxFPF0R_RLEN_Msk            (0xfUL << LTDC_LxFPF0R_RLEN_Pos)
+#define LTDC_LxFPF0R_RLEN                LTDC_LxFPF0R_RLEN_Msk  /*!< Width of the red component (in bits). */
+
+/* Bit fields for LTDC_LxFPF1R register */
+#define LTDC_LxFPF1R_GPOS_Pos            (0U)
+#define LTDC_LxFPF1R_GPOS_Msk            (0x1fUL << LTDC_LxFPF1R_GPOS_Pos)
+#define LTDC_LxFPF1R_GPOS                LTDC_LxFPF1R_GPOS_Msk  /*!< Location of the alpha component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_GLEN_Pos            (5U)
+#define LTDC_LxFPF1R_GLEN_Msk            (0xfUL << LTDC_LxFPF1R_GLEN_Pos)
+#define LTDC_LxFPF1R_GLEN                LTDC_LxFPF1R_GLEN_Msk  /*!< Width of the alpha component (in bits). */
+
+#define LTDC_LxFPF1R_BPOS_Pos            (9U)
+#define LTDC_LxFPF1R_BPOS_Msk            (0x1fUL << LTDC_LxFPF1R_BPOS_Pos)
+#define LTDC_LxFPF1R_BPOS                LTDC_LxFPF1R_BPOS_Msk  /*!< Location of the red component inside the pixel memory word (in bits). */
+
+#define LTDC_LxFPF1R_BLEN_Pos            (14U)
+#define LTDC_LxFPF1R_BLEN_Msk            (0xfUL << LTDC_LxFPF1R_BLEN_Pos)
+#define LTDC_LxFPF1R_BLEN                LTDC_LxFPF1R_BLEN_Msk  /*!< Width of the red component (in bits). */
+
+#define LTDC_LxFPF1R_PSIZE_Pos            (18U)
+#define LTDC_LxFPF1R_PSIZE_Msk            (0x7UL << LTDC_LxFPF1R_PSIZE_Pos)
+#define LTDC_LxFPF1R_PSIZE                LTDC_LxFPF1R_PSIZE_Msk  /*!< Width of the red component (in bits). */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Memory Cipher Engine (MCE)                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MCE_CR register  ********************/
+#define MCE_CR_GLOCK_Pos               (0U)
+#define MCE_CR_GLOCK_Msk               (0x1UL << MCE_CR_GLOCK_Pos)             /*!< 0x00000001 */
+#define MCE_CR_GLOCK                   MCE_CR_GLOCK_Msk                        /*!< MCE global lock */
+#define MCE_CR_MKLOCK_Pos              (1U)
+#define MCE_CR_MKLOCK_Msk              (0x1UL << MCE_CR_MKLOCK_Pos)            /*!< 0x00000002 */
+#define MCE_CR_MKLOCK                  MCE_CR_MKLOCK_Msk                       /*!< MCE master and fast master keys lock */
+#define MCE_CR_CIPHERSEL_Pos           (4U)
+#define MCE_CR_CIPHERSEL_Msk           (0x3UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000030 */
+#define MCE_CR_CIPHERSEL               MCE_CR_CIPHERSEL_Msk                    /*!< MCE Cipher selection */
+#define MCE_CR_CIPHERSEL_0             (0x1UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000010 */
+#define MCE_CR_CIPHERSEL_1             (0x2UL << MCE_CR_CIPHERSEL_Pos)         /*!< 0x00000020 */
+
+/********************  Bit definition for MCE_SR register  ********************/
+#define MCE_SR_MKVALID_Pos             (0U)
+#define MCE_SR_MKVALID_Msk             (0x1UL << MCE_SR_MKVALID_Pos)           /*!< 0x00000001 */
+#define MCE_SR_MKVALID                 MCE_SR_MKVALID_Msk                      /*!< MCE master key valid flag */
+#define MCE_SR_FMKVALID_Pos            (2U)
+#define MCE_SR_FMKVALID_Msk            (0x1UL << MCE_SR_FMKVALID_Pos)          /*!< 0x00000004 */
+#define MCE_SR_FMKVALID                 MCE_SR_FMKVALID_Msk                    /*!< MCE fast master key valid flag */
+#define MCE_SR_ENCDIS_Pos              (4U)
+#define MCE_SR_ENCDIS_Msk              (0x1UL << MCE_SR_ENCDIS_Pos)            /*!< 0x00000010 */
+#define MCE_SR_ENCDIS                  MCE_SR_ENCDIS_Msk                       /*!< MCE encryption disabled flag */
+
+/********************  Bit definition for MCE_IASR register  ******************/
+#define MCE_IASR_IAEF_Pos              (1U)
+#define MCE_IASR_IAEF_Msk              (0x1UL << MCE_IASR_IAEF_Pos)             /*!< 0x00000002 */
+#define MCE_IASR_IAEF                  MCE_IASR_IAEF_Msk                        /*!< MCE illegal access error flag */
+
+/********************  Bit definition for MCE_IACR register  ******************/
+#define MCE_IACR_IAEF_Pos              (1U)
+#define MCE_IACR_IAEF_Msk              (0x1UL << MCE_IACR_IAEF_Pos)             /*!< 0x00000002 */
+#define MCE_IACR_IAEF                  MCE_IACR_IAEF_Msk                        /*!< MCE illegal access error clear bit */
+
+/********************  Bit definition for MCE_IAIER register  *****************/
+#define MCE_IAIER_IAEIE_Pos            (1U)
+#define MCE_IAIER_IAEIE_Msk            (0x1UL << MCE_IAIER_IAEIE_Pos)           /*!< 0x00000002 */
+#define MCE_IAIER_IAEIE                MCE_IAIER_IAEIE_Msk                      /*!< MCE illegal access error interrupt enable */
+
+/********************  Bit definition for MCE_IADDR register  *****************/
+#define MCE_IADDR_IADD_Pos             (0U)
+#define MCE_IADDR_IADD_Msk             (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_IADDR_IADD                 MCE_IADDR_IADD_Msk                      /*!< MCE illegal access */
+
+/********************  Bit definition for MCE_REGCR register  *****************/
+#define MCE_REGCR_BREN_Pos             (0U)
+#define MCE_REGCR_BREN_Msk             (0x1UL << MCE_REGCR_BREN_Pos)            /*!< 0x00000001 */
+#define MCE_REGCR_BREN                 MCE_REGCR_BREN_Msk                       /*!< MCE base region enable */
+#define MCE_REGCR_CTXID_Pos            (9U)
+#define MCE_REGCR_CTXID_Msk            (0x3UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000600 */
+#define MCE_REGCR_CTXID                MCE_REGCR_CTXID_Msk                      /*!< MCE context ID */
+#define MCE_REGCR_CTXID_0              (0x1UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000200 */
+#define MCE_REGCR_CTXID_1              (0x2UL << MCE_REGCR_CTXID_Pos)           /*!< 0x00000400 */
+#define MCE_REGCR_ENC_Pos              (14U)
+#define MCE_REGCR_ENC_Msk              (0x3UL << MCE_REGCR_ENC_Pos)             /*!< 0x0000C000 */
+#define MCE_REGCR_ENC                  MCE_REGCR_ENC_Msk                        /*!< MCE encrypted region */
+#define MCE_REGCR_ENC_0                (0x1UL << MCE_REGCR_ENC_Pos)             /*!< 0x00004000 */
+#define MCE_REGCR_ENC_1                (0x2UL << MCE_REGCR_ENC_Pos)             /*!< 0x00008000 */
+
+/********************  Bit definition for MCE_SADDR register  *****************/
+#define MCE_SADDR_BADDSTART_Pos        (12U)
+#define MCE_SADDR_BADDSTART_Msk        (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos)   /*!< 0xFFFFF000 */
+#define MCE_SADDR_BADDSTART            MCE_SADDR_BADDSTART_Msk                  /*!< MCE region address start */
+
+/********************  Bit definition for MCE_EADDR register  *****************/
+#define MCE_EADDR_BADDEND_Pos          (12U)
+#define MCE_EADDR_BADDEND_Msk          (0xFFFFFUL << MCE_EADDR_BADDEND_Pos)     /*!< 0xFFFFF000 */
+#define MCE_EADDR_BADDEND              MCE_EADDR_BADDEND_Msk                    /*!< MCE region address end */
+
+/********************  Bit definition for MCE_MKEYR0 register  ****************/
+#define MCE_MKEYR0_MKEY_Pos            (0U)
+#define MCE_MKEYR0_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR0_MKEY                MCE_MKEYR0_MKEY_Msk                      /*!< MCE master key, bits [31:0] */
+
+/********************  Bit definition for MCE_MKEYR1 register  ****************/
+#define MCE_MKEYR1_MKEY_Pos            (0U)
+#define MCE_MKEYR1_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR1_MKEY                MCE_MKEYR1_MKEY_Msk                      /*!< MCE master key, bits [63:32] */
+
+/********************  Bit definition for MCE_MKEYR2 register  ****************/
+#define MCE_MKEYR2_MKEY_Pos            (0U)
+#define MCE_MKEYR2_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR2_MKEY                MCE_MKEYR2_MKEY_Msk                      /*!< MCE master key, bits [95:64] */
+
+/********************  Bit definition for MCE_MKEYR3 register  ****************/
+#define MCE_MKEYR3_MKEY_Pos            (0U)
+#define MCE_MKEYR3_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR3_MKEY                MCE_MKEYR3_MKEY_Msk                      /*!< MCE master key, bits [127:96] */
+
+/********************  Bit definition for MCE_MKEYR4 register  ****************/
+#define MCE_MKEYR4_MKEY_Pos            (0U)
+#define MCE_MKEYR4_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR4_MKEY                MCE_MKEYR4_MKEY_Msk                      /*!< MCE master key, bits [159:128] */
+
+/********************  Bit definition for MCE_MKEYR5 register  ****************/
+#define MCE_MKEYR5_MKEY_Pos            (0U)
+#define MCE_MKEYR5_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR5_MKEY                MCE_MKEYR5_MKEY_Msk                      /*!< MCE master key, bits [191:160] */
+
+/********************  Bit definition for MCE_MKEYR6 register  ****************/
+#define MCE_MKEYR6_MKEY_Pos            (0U)
+#define MCE_MKEYR6_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR6_MKEY                MCE_MKEYR6_MKEY_Msk                      /*!< MCE master key, bits [223:192] */
+
+/********************  Bit definition for MCE_MKEYR7 register  ****************/
+#define MCE_MKEYR7_MKEY_Pos            (0U)
+#define MCE_MKEYR7_MKEY_Msk            (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_MKEYR7_MKEY                MCE_MKEYR7_MKEY_Msk                      /*!< MCE master key, bits [255:224] */
+
+/********************  Bit definition for MCE_FMKEYR0 register  ***************/
+#define MCE_FMKEYR0_FMKEY_Pos          (0U)
+#define MCE_FMKEYR0_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR0_FMKEY              MCE_FMKEYR0_FMKEY_Msk                    /*!< MCE fast master key, bits [31:0] */
+
+/********************  Bit definition for MCE_FMKEYR1 register  ***************/
+#define MCE_FMKEYR1_FMKEY_Pos          (0U)
+#define MCE_FMKEYR1_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR1_FMKEY              MCE_FMKEYR1_FMKEY_Msk                    /*!< MCE fast master key, bits [63:32] */
+
+/********************  Bit definition for MCE_FMKEYR2 register  ***************/
+#define MCE_FMKEYR2_FMKEY_Pos          (0U)
+#define MCE_FMKEYR2_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR2_FMKEY              MCE_FMKEYR2_FMKEY_Msk                    /*!< MCE fast master key, bits [95:64] */
+
+/********************  Bit definition for MCE_FMKEYR3 register  ***************/
+#define MCE_FMKEYR3_FMKEY_Pos          (0U)
+#define MCE_FMKEYR3_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR3_FMKEY              MCE_FMKEYR3_FMKEY_Msk                    /*!< MCE fast master key, bits [127:96] */
+
+/********************  Bit definition for MCE_FMKEYR4 register  ****************/
+#define MCE_FMKEYR4_FMKEY_Pos          (0U)
+#define MCE_FMKEYR4_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR4_FMKEY              MCE_FMKEYR4_FMKEY_Msk                    /*!< MCE fast master key, bits [159:128] */
+
+/********************  Bit definition for MCE_FMKEYR5 register  ****************/
+#define MCE_FMKEYR5_FMKEY_Pos          (0U)
+#define MCE_FMKEYR5_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR5_FMKEY              MCE_FMKEYR5_FMKEY_Msk                    /*!< MCE fast master key, bits [191:160] */
+
+/********************  Bit definition for MCE_FMKEYR6 register  ****************/
+#define MCE_FMKEYR6_FMKEY_Pos          (0U)
+#define MCE_FMKEYR6_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR6_FMKEY              MCE_FMKEYR6_FMKEY_Msk                    /*!< MCE fast master key, bits [223:192] */
+
+/********************  Bit definition for MCE_FMKEYR7 register  ****************/
+#define MCE_FMKEYR7_FMKEY_Pos          (0U)
+#define MCE_FMKEYR7_FMKEY_Msk          (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_FMKEYR7_FMKEY              MCE_FMKEYR7_FMKEY_Msk                    /*!< MCE fast master key, bits [255:224] */
+
+/********************  Bit definition for MCE_CCCFGR register  ****************/
+#define MCE_CCCFGR_CCEN_Pos             (0U)
+#define MCE_CCCFGR_CCEN_Msk             (0x1UL << MCE_CCCFGR_CCEN_Pos)          /*!< 0x00000001 */
+#define MCE_CCCFGR_CCEN                 MCE_CCCFGR_CCEN_Msk                     /*!< MCE cipher context enable */
+#define MCE_CCCFGR_CCLOCK_Pos           (1U)
+#define MCE_CCCFGR_CCLOCK_Msk           (0x1UL << MCE_CCCFGR_CCLOCK_Pos)        /*!< 0x00000002 */
+#define MCE_CCCFGR_CCLOCK               MCE_CCCFGR_CCLOCK_Msk                   /*!< MCE cipher context lock */
+#define MCE_CCCFGR_KEYLOCK_Pos          (2U)
+#define MCE_CCCFGR_KEYLOCK_Msk          (0x1UL << MCE_CCCFGR_KEYLOCK_Pos)       /*!< 0x00000004 */
+#define MCE_CCCFGR_KEYLOCK              MCE_CCCFGR_KEYLOCK_Msk                  /*!< MCE cipher context key lock */
+#define MCE_CCCFGR_MODE_Pos             (4U)
+#define MCE_CCCFGR_MODE_Msk             (0x3UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000030 */
+#define MCE_CCCFGR_MODE                 MCE_CCCFGR_MODE_Msk                     /*!< MCE authorized cipher mode */
+#define MCE_CCCFGR_MODE_0               (0x1UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000010 */
+#define MCE_CCCFGR_MODE_1               (0x2UL << MCE_CCCFGR_MODE_Pos)          /*!< 0x00000020 */
+#define MCE_CCCFGR_KEYCRC_Pos           (8U)
+#define MCE_CCCFGR_KEYCRC_Msk           (0xFFUL << MCE_CCCFGR_KEYCRC_Pos)       /*!< 0x0000FF00 */
+#define MCE_CCCFGR_KEYCRC               MCE_CCCFGR_KEYCRC_Msk                   /*!< MCE cipher context key CRC */
+#define MCE_CCCFGR_VERSION_Pos          (16U)
+#define MCE_CCCFGR_VERSION_Msk          (0xFFFFUL << MCE_CCCFGR_VERSION_Pos)    /*!< 0xFFFF0000 */
+#define MCE_CCCFGR_VERSION              MCE_CCCFGR_VERSION_Msk                  /*!< MCE cipher context version */
+
+/********************  Bit definition for MCE_CCNR0 register  *****************/
+#define MCE_CCNR0_SCNONCE_Pos          (0U)
+#define MCE_CCNR0_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_CCNR0_SCNONCE              MCE_CCNR0_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [31:0] */
+
+/********************  Bit definition for MCE_CCNR1 register  ****************/
+#define MCE_CCNR1_SCNONCE_Pos          (0U)
+#define MCE_CCNR1_SCNONCE_Msk          (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos)  /*!< 0xFFFFFFFF */
+#define MCE_CCNR1_SCNONCE              MCE_CCNR1_SCNONCE_Msk                    /*!< MCE cipher context stream cipher nonce, bits [63:32] */
+
+/********************  Bit definition for MCE_CCKEYR0 register  ***************/
+#define MCE_CCKEYR0_KEY_Pos            (0U)
+#define MCE_CCKEYR0_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR0_KEY                MCE_CCKEYR0_KEY_Msk                      /*!< MCE cipher context key, bits [31:0] */
+
+/********************  Bit definition for MCE_CCKEYR1 register  ***************/
+#define MCE_CCKEYR1_KEY_Pos            (0U)
+#define MCE_CCKEYR1_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR1_KEY                MCE_CCKEYR1_KEY_Msk                      /*!< MCE fast master key, bits [63:32] */
+
+/********************  Bit definition for MCE_CCKEYR2 register  ***************/
+#define MCE_CCKEYR2_KEY_Pos            (0U)
+#define MCE_CCKEYR2_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR2_KEY                MCE_CCKEYR2_KEY_Msk                      /*!< MCE fast master key, bits [95:64] */
+
+/********************  Bit definition for MCE_CCKEYR3 register  ***************/
+#define MCE_CCKEYR3_KEY_Pos            (0U)
+#define MCE_CCKEYR3_KEY_Msk            (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos)    /*!< 0xFFFFFFFF */
+#define MCE_CCKEYR3_KEY                MCE_CCKEYR3_KEY_Msk                      /*!< MCE fast master key, bits [127:96] */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDF/ADF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for MDF/ADF_GCR register  ****************/
+#define MDF_GCR_TRGO_Pos                    (0U)
+#define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
+#define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!< Trigger output control */
+#define MDF_GCR_ILVNB_Pos                   (4U)
+#define MDF_GCR_ILVNB_Msk                   (0xFUL << MDF_GCR_ILVNB_Pos)            /*!< 0x000000F0 */
+#define MDF_GCR_ILVNB                       MDF_GCR_ILVNB_Msk                       /*!< Interleaved Number */
+
+/*******************  Bit definition for MDF/ADF_CKGCR register  ********************/
+#define MDF_CKGCR_CKDEN_Pos                 (0U)
+#define MDF_CKGCR_CKDEN_Msk                 (0x1UL << MDF_CKGCR_CKDEN_Pos)          /*!< 0x00000001 */
+#define MDF_CKGCR_CKDEN                     MDF_CKGCR_CKDEN_Msk                     /*!<CKGEN diveders enable */
+#define MDF_CKGCR_CCK0EN_Pos                (1U)
+#define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
+#define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!<CCK0 clock enable */
+#define MDF_CKGCR_CCK1EN_Pos                (2U)
+#define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
+#define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!<CCK1 clock enable */
+#define MDF_CKGCR_CKGMOD_Pos                (4U)
+#define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
+#define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!<Clock genartor mode */
+#define MDF_CKGCR_CCK0DIR_Pos               (5U)
+#define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
+#define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!<CCK0 clock direction */
+#define MDF_CKGCR_CCK1DIR_Pos               (6U)
+#define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
+#define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!<CCK1 clock direction */
+#define MDF_CKGCR_TRGSENS_Pos               (8U)
+#define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
+#define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!<CKGEN trigger sensitivity selection */
+#define MDF_CKGCR_TRGSRC_Pos                (12U)
+#define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
+#define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!<Digital Filter trigger signal selection */
+#define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
+#define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
+#define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
+#define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
+#define MDF_CKGCR_CCKDIV_Pos                (16U)
+#define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
+#define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!<Divider to control the MDF_CCK clock */
+#define MDF_CKGCR_PROCDIV_Pos               (24U)
+#define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
+#define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!<Divider to control the serial interface clock */
+#define MDF_CKGCR_CCKACTIVE_Pos             (31U)
+#define MDF_CKGCR_CCKACTIVE_Msk             (0x1UL << MDF_CKGCR_CCKACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_CKGCR_CCKACTIVE                 MDF_CKGCR_CCKACTIVE_Msk                 /*!<Clock generator active flag */
+
+/*******************  Bit definition for MDF/ADF_OR register  ********************/
+#define MDF_OR_OPTION_Pos                   (0U)
+#define MDF_OR_OPTION_Msk                   (0xFFFFFFFFUL << MDF_OR_OPTION_Pos)     /*!< 0xFFFFFFFF */
+#define MDF_OR_OPTION                       MDF_OR_OPTION_Msk                       /*!<Option Control Bits */
+
+/*******************  Bit definition for MDF/ADF_SITFxCR register  ********************/
+#define MDF_SITFCR_SITFEN_Pos               (0U)
+#define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
+#define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!<Serial interface enable */
+#define MDF_SITFCR_SCKSRC_Pos               (1U)
+#define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
+#define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!<Serial clock source */
+#define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
+#define MDF_SITFCR_SITFMOD_Pos              (4U)
+#define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
+#define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!<Serial interface type */
+#define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
+#define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
+#define MDF_SITFCR_STH_Pos                  (8U)
+#define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
+#define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!<Manchester Symbol threshold / SPI threshold */
+#define MDF_SITFCR_SITFACTIVE_Pos           (31U)
+#define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
+#define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!<Serial interface active flag */
+
+/*******************  Bit definition for MDF/ADF_BSMXxCR register  ********************/
+#define MDF_BSMXCR_BSSEL_Pos                (0U)
+#define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
+#define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!<Bit Streal selection */
+#define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
+#define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
+#define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
+#define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
+#define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
+#define MDF_BSMXCR_BSMXACTIVATE_Pos         (31U)
+#define MDF_BSMXCR_BSMXACTIVATE_Msk         (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos)  /*!< 0x80000000 */
+#define MDF_BSMXCR_BSMXACTIVATE             MDF_BSMXCR_BSMXACTIVATE_Msk             /*!<Bit Streal activation flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCR register  ********************/
+#define MDF_DFLTCR_DFLTEN_Pos               (0U)
+#define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!<Digital filter enable */
+#define MDF_DFLTCR_DMAEN_Pos                (1U)
+#define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
+#define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!<DMA request enable */
+#define MDF_DFLTCR_FTH_Pos                  (2U)
+#define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
+#define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!<RXFIFO Threshold selection */
+#define MDF_DFLTCR_ACQMOD_Pos               (4U)
+#define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!<Digital filter trigger mode */
+#define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
+#define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
+#define MDF_DFLTCR_TRGSENS_Pos              (8U)
+#define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!<Digital filter trigger sensitivity selection */
+#define MDF_DFLTCR_TRGSRC_Pos               (12U)
+#define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!<Digital filter trigger signal selection */
+#define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
+#define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
+#define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
+#define MDF_DFLTCR_SNPSFMT_Pos              (16U)
+#define MDF_DFLTCR_SNPSFMT_Msk              (0x1UL << MDF_DFLTCR_SNPSFMT_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_SNPSFMT                  MDF_DFLTCR_SNPSFMT_Msk                  /*!<SnapShot Data format */
+#define MDF_DFLTCR_NBDIS_Pos                (20U)
+#define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!<Number of samples to be discard */
+#define MDF_DFLTCR_DFLTRUN_Pos              (30U)
+#define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!<Digital filter run status flag */
+#define MDF_DFLTCR_DFLTACTIVE_Pos           (31U)
+#define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
+#define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!<Digital filter active flag */
+
+/*******************  Bit definition for MDF/ADF_DFLTxCICR register  ********************/
+#define MDF_DFLTCICR_DATSRC_Pos             (0U)
+#define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!<Source Data for the digital filter */
+#define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTCICR_CICMOD_Pos             (4U)
+#define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
+#define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!<Select the CIC Mode*/
+#define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
+#define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
+#define MDF_DFLTCICR_MCICD_Pos              (8U)
+#define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
+#define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!<CIC decimation ratio selection*/
+#define MDF_DFLTCICR_SCALE_Pos              (20U)
+#define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
+#define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!<Scaling factor selection*/
+
+/*******************  Bit definition for MDF/ADF_DFLTxRSFR register  ********************/
+#define MDF_DFLTRSFR_RSFLTBYP_Pos           (0U)
+#define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
+#define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!<Reshape filter bypass*/
+#define MDF_DFLTRSFR_RSFLTD_Pos             (4U)
+#define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
+#define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!<Reshape filter decimation ratio*/
+#define MDF_DFLTRSFR_HPFBYP_Pos             (7U)
+#define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!<High-pass filter bypass*/
+#define MDF_DFLTRSFR_HPFC_Pos               (8U)
+#define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
+#define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!<High-pass filter cut-off frequency*/
+#define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
+#define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)
+
+/*******************  Bit definition for MDF/ADF_DFLTxINTR register  ********************/
+#define MDF_DFLTINTR_INTDIV_Pos             (0U)
+#define MDF_DFLTINTR_INTDIV_Msk             (0x3UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000003 */
+#define MDF_DFLTINTR_INTDIV                 MDF_DFLTINTR_INTDIV_Msk                 /*!<Integrator output dividion*/
+#define MDF_DFLTINTR_INTDIV_0               (0x1UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000001 */
+#define MDF_DFLTINTR_INTDIV_1               (0x2UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000002 */
+#define MDF_DFLTINTR_INTVAL_Pos             (4U)
+#define MDF_DFLTINTR_INTVAL_Msk             (0x7FUL << MDF_DFLTINTR_INTVAL_Pos)     /*!< 0x000007F0 */
+#define MDF_DFLTINTR_INTVAL                 MDF_DFLTINTR_INTVAL_Msk                 /*!<Integrator value selection*/
+
+/*******************  Bit definition for MDF/ADF_OLDxCR register  ********************/
+#define MDF_OLDCR_OLDEN_Pos                 (0U)
+#define MDF_OLDCR_OLDEN_Msk                 (0x1UL << MDF_OLDCR_OLDEN_Pos)          /*!< 0x00000001 */
+#define MDF_OLDCR_OLDEN                     MDF_OLDCR_OLDEN_Msk                     /*!<OLD enable*/
+#define MDF_OLDCR_THINB_Pos                 (1U)
+#define MDF_OLDCR_THINB_Msk                 (0x1UL << MDF_OLDCR_THINB_Pos)          /*!< 0x00000002 */
+#define MDF_OLDCR_THINB                     MDF_OLDCR_THINB_Msk                     /*!<OLD threshold in band*/
+#define MDF_OLDCR_BKOLD_Pos                 (4U)
+#define MDF_OLDCR_BKOLD_Msk                 (0xFUL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x000000F0 */
+#define MDF_OLDCR_BKOLD                     MDF_OLDCR_BKOLD_Msk                     /*!<Bteak signal assignment for OLD*/
+#define MDF_OLDCR_BKOLD_0                   (0x1UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000010 */
+#define MDF_OLDCR_BKOLD_1                   (0x2UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000020 */
+#define MDF_OLDCR_BKOLD_2                   (0x4UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000040 */
+#define MDF_OLDCR_BKOLD_3                   (0x8UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000080 */
+#define MDF_OLDCR_ACICN_Pos                 (12U)
+#define MDF_OLDCR_ACICN_Msk                 (0x3UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00003000 */
+#define MDF_OLDCR_ACICN                     MDF_OLDCR_ACICN_Msk                     /*!<OLD CIC order selection*/
+#define MDF_OLDCR_ACICN_0                   (0x1UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00001000 */
+#define MDF_OLDCR_ACICN_1                   (0x2UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00002000 */
+#define MDF_OLDCR_ACICD_Pos                 (17U)
+#define MDF_OLDCR_ACICD_Msk                 (0x1FUL << MDF_OLDCR_ACICD_Pos)         /*!< 0x003E0000 */
+#define MDF_OLDCR_ACICD                     MDF_OLDCR_ACICD_Msk                     /*!<OLD CIC decimation ratio selection*/
+#define MDF_OLDCR_OLDACTIVE_Pos             (31U)
+#define MDF_OLDCR_OLDACTIVE_Msk             (0x1UL << MDF_OLDCR_OLDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_OLDCR_OLDACTIVE                 MDF_OLDCR_OLDACTIVE_Msk                 /*!<OLD active flag*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHLR register  ********************/
+#define MDF_OLDTHLR_OLDTHL_Pos              (0U)
+#define MDF_OLDTHLR_OLDTHL_Msk              (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHLR_OLDTHL                  MDF_OLDTHLR_OLDTHL_Msk                  /*!<OLD Low threshold value*/
+
+/*******************  Bit definition for MDF/ADF_OLDxTHHR register  ********************/
+#define MDF_OLDTHHR_OLDTHH_Pos              (0U)
+#define MDF_OLDTHHR_OLDTHH_Msk              (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) /*!< 0x03FFFFFF */
+#define MDF_OLDTHHR_OLDTHH                  MDF_OLDTHHR_OLDTHH_Msk                  /*!<OLD High threshold value*/
+
+/*******************  Bit definition for MDF/ADF_DLYxCR register  ********************/
+#define MDF_DLYCR_SKPDLY_Pos                (0U)
+#define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
+#define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!<Delay to apply to a bitstream*/
+#define MDF_DLYCR_SKPBF_Pos                 (31U)
+#define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
+#define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!<DSkip Busy Flag*/
+
+/*******************  Bit definition for MDF/ADF_SCDxCR register  ********************/
+#define MDF_SCDCR_SCDEN_Pos                 (0U)
+#define MDF_SCDCR_SCDEN_Msk                 (0x1UL << MDF_SCDCR_SCDEN_Pos)          /*!< 0x00000001 */
+#define MDF_SCDCR_SCDEN                     MDF_SCDCR_SCDEN_Msk                     /*!<Short circuit detector enable*/
+#define MDF_SCDCR_BKSCD_Pos                 (4U)
+#define MDF_SCDCR_BKSCD_Msk                 (0xFUL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x000000F0 */
+#define MDF_SCDCR_BKSCD                     MDF_SCDCR_BKSCD_Msk                     /*!<Break signal assignment to short circuit detector */
+#define MDF_SCDCR_BKSCD_0                   (0x1UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000010 */
+#define MDF_SCDCR_BKSCD_1                   (0x2UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000020 */
+#define MDF_SCDCR_BKSCD_2                   (0x4UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000040 */
+#define MDF_SCDCR_BKSCD_3                   (0x8UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000080 */
+#define MDF_SCDCR_SCDT_Pos                  (12U)
+#define MDF_SCDCR_SCDT_Msk                  (0xFFUL << MDF_SCDCR_SCDT_Pos)          /*!< 0x00000FF00 */
+#define MDF_SCDCR_SCDT                      MDF_SCDCR_SCDT_Msk                      /*!<Short circuit detector threshold*/
+#define MDF_SCDCR_SCDACTIVE_Pos             (31U)
+#define MDF_SCDCR_SCDACTIVE_Msk             (0x1UL << MDF_SCDCR_SCDACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SCDCR_SCDACTIVE                 MDF_SCDCR_SCDACTIVE_Msk                 /*!<Short circuit detector active flag*/
+
+/*******************  Bit definition for MDF/ADF_DFLTIER register  ********************/
+#define MDF_DFLTIER_FTHIE_Pos               (0U)
+#define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
+#define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!<RXFIFO threshold interrupt enable*/
+#define MDF_DFLTIER_DOVRIE_Pos              (1U)
+#define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
+#define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!<Data overflow interrupt enable*/
+#define MDF_DFLTIER_SSDRIE_Pos              (2U)
+#define MDF_DFLTIER_SSDRIE_Msk              (0x1UL << MDF_DFLTIER_SSDRIE_Pos)       /*!< 0x00000004 */
+#define MDF_DFLTIER_SSDRIE                  MDF_DFLTIER_SSDRIE_Msk                  /*!<Snapshot data ready interrupt enable*/
+#define MDF_DFLTIER_OLDIE_Pos               (4U)
+#define MDF_DFLTIER_OLDIE_Msk               (0x1UL << MDF_DFLTIER_OLDIE_Pos)        /*!< 0x00000010 */
+#define MDF_DFLTIER_OLDIE                   MDF_DFLTIER_OLDIE_Msk                   /*!<OLD interrupt enable*/
+#define MDF_DFLTIER_SSOVRIE_Pos             (7U)
+#define MDF_DFLTIER_SSOVRIE_Msk             (0x1UL << MDF_DFLTIER_SSOVRIE_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTIER_SSOVRIE                 MDF_DFLTIER_SSOVRIE_Msk                 /*!<Snapshot overrun interrupt enable*/
+#define MDF_DFLTIER_SCDIE_Pos               (8U)
+#define MDF_DFLTIER_SCDIE_Msk               (0x1UL << MDF_DFLTIER_SCDIE_Pos)        /*!< 0x00000100 */
+#define MDF_DFLTIER_SCDIE                   MDF_DFLTIER_SCDIE_Msk                   /*!<Short circuit dtector interrupt enable*/
+#define MDF_DFLTIER_SATIE_Pos               (9U)
+#define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
+#define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!<Saturation detection interrupt enable*/
+#define MDF_DFLTIER_CKABIE_Pos              (10U)
+#define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
+#define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!<Clock absence detection interrupt enable*/
+#define MDF_DFLTIER_RFOVRIE_Pos             (11U)
+#define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
+#define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!<reshape filter overrun interrupt enable*/
+#define MDF_DFLTIER_SDDETIE_Pos             (12U)
+#define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
+#define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!<SAD interrupt enable*/
+#define MDF_DFLTIER_SDLVLIE_Pos             (13U)
+#define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
+#define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!<Sound level value ready interrupt enable*/
+
+/*******************  Bit definition for MDF/ADF_DFLTISR register  ********************/
+#define MDF_DFLTISR_FTHF_Pos                (0U)
+#define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
+#define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!<RXFIFO threshold interrupt flag*/
+#define MDF_DFLTISR_DOVRF_Pos               (1U)
+#define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
+#define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!<Data overflow interrupt flag*/
+#define MDF_DFLTISR_SSDRF_Pos               (2U)
+#define MDF_DFLTISR_SSDRF_Msk               (0x1UL << MDF_DFLTISR_SSDRF_Pos)        /*!< 0x00000004 */
+#define MDF_DFLTISR_SSDRF                   MDF_DFLTISR_SSDRF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_RXNEF_Pos               (3U)
+#define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
+#define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!<Snapshot data ready interrupt flag*/
+#define MDF_DFLTISR_OLDF_Pos                (4U)
+#define MDF_DFLTISR_OLDF_Msk                (0x1UL << MDF_DFLTISR_OLDF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_OLDF                    MDF_DFLTISR_OLDF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THLF_Pos                (5U)
+#define MDF_DFLTISR_THLF_Msk                (0x1UL << MDF_DFLTISR_THLF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THLF                    MDF_DFLTISR_THLF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_THHF_Pos                (6U)
+#define MDF_DFLTISR_THHF_Msk                (0x1UL << MDF_DFLTISR_THHF_Pos)         /*!< 0x00000010 */
+#define MDF_DFLTISR_THHF                    MDF_DFLTISR_THHF_Msk                    /*!<OLD interrupt flag*/
+#define MDF_DFLTISR_SSOVRF_Pos              (7U)
+#define MDF_DFLTISR_SSOVRF_Msk              (0x1UL << MDF_DFLTISR_SSOVRF_Pos)      /*!< 0x00000080 */
+#define MDF_DFLTISR_SSOVRF                  MDF_DFLTISR_SSOVRF_Msk                  /*!<Snapshot overrun interrupt flag*/
+#define MDF_DFLTISR_SCDF_Pos                (8U)
+#define MDF_DFLTISR_SCDF_Msk                (0x1UL << MDF_DFLTISR_SCDF_Pos)         /*!< 0x00000100 */
+#define MDF_DFLTISR_SCDF                    MDF_DFLTISR_SCDF_Msk                    /*!<Short circuit dtector interrupt flag*/
+#define MDF_DFLTISR_SATF_Pos                (9U)
+#define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
+#define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!<Saturation detection interrupt flag*/
+#define MDF_DFLTISR_CKABF_Pos               (10U)
+#define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
+#define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!<Clock absence detection interrupt flag*/
+#define MDF_DFLTISR_RFOVRF_Pos              (11U)
+#define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
+#define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!<reshape filter overrun interrupt flag*/
+#define MDF_DFLTISR_SDDETF_Pos              (12U)
+#define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
+#define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!<SAD interrupt flag*/
+#define MDF_DFLTISR_SDLVLF_Pos              (13U)
+#define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
+#define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!<Sound level value ready interrupt flag*/
+
+/*******************  Bit definition for MDF/ADF_OECCR register  ********************/
+#define MDF_OECCR_OFFSET_Pos                (0U)
+#define MDF_OECCR_OFFSET_Msk                (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos)   /*!< 0x03FFFFFF */
+#define MDF_OECCR_OFFSET                    MDF_OECCR_OFFSET_Msk                    /*!<Short circuit detector enable*/
+
+/*******************  Bit definition for MDF/ADF_SADCR register  ********************/
+#define MDF_SADCR_SADEN_Pos                 (0U)
+#define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
+#define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!<SAD enable*/
+#define MDF_SADCR_DATCAP_Pos                (1U)
+#define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
+#define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!<SAD data capture mode*/
+#define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
+#define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
+#define MDF_SADCR_DETCFG_Pos                (3U)
+#define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
+#define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!<SAD trigger event configuration*/
+#define MDF_SADCR_SADST_Pos                 (4U)
+#define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
+#define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!<SAD state*/
+#define MDF_SADCR_HYSTEN_Pos                (7U)
+#define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
+#define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!<Hysteresis enable*/
+#define MDF_SADCR_FRSIZE_Pos                (8U)
+#define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
+#define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!<Frame size*/
+#define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
+#define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
+#define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
+#define MDF_SADCR_SADMOD_Pos                (12U)
+#define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
+#define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!<SAD working mode*/
+#define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
+#define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
+#define MDF_SADCR_SADACTIVE_Pos             (31U)
+#define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
+#define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!<SAD active flag*/
+
+/*******************  Bit definition for MDF/ADF_SADCFGR register  ********************/
+#define MDF_SADCFGR_SNTHR_Pos               (0U)
+#define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
+#define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!<Signal to noise threshold*/
+#define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
+#define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
+#define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
+#define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
+#define MDF_SADCFGR_ANSLP_Pos               (4U)
+#define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
+#define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!<Ambiant noise slope control*/
+#define MDF_SADCFGR_LFRNB_Pos               (8U)
+#define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
+#define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!<Number of learning frames*/
+#define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
+#define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
+#define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
+#define MDF_SADCFGR_HGOVR_Pos               (12U)
+#define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
+#define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!<Hangover time window*/
+#define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
+#define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
+#define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
+#define MDF_SADCFGR_ANMIN_Pos               (16U)
+#define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
+#define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!<Hangover time window*/
+
+/*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
+#define MDF_SADSDLVR_SDLVL_Pos              (0U)
+#define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!<Short term sound level*/
+
+/*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
+#define MDF_SADANLVR_ANLVL_Pos              (0U)
+#define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
+#define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!<Ambiant noise level estimation*/
+
+/*******************  Bit definition for MDF/ADF_SNPSDR register  ********************/
+#define MDF_SNPSDR_MCICDC_Pos               (0U)
+#define MDF_SNPSDR_MCICDC_Msk               (0x1FFUL << MDF_SNPSDR_MCICDC_Pos)      /*!< 0x000001FF */
+#define MDF_SNPSDR_MCICDC                   MDF_SNPSDR_MCICDC_Msk                   /*!<MCIC decimation counter*/
+#define MDF_SNPSDR_EXTSDR_Pos               (9U)
+#define MDF_SNPSDR_EXTSDR_Msk               (0x7FUL << MDF_SNPSDR_EXTSDR_Pos)       /*!< 0x0000FE00 */
+#define MDF_SNPSDR_EXTSDR                   MDF_SNPSDR_EXTSDR_Msk                   /*!<Extended data size*/
+#define MDF_SNPSDR_SDR_Pos                  (16U)
+#define MDF_SNPSDR_SDR_Msk                  (0xFFFFUL << MDF_SNPSDR_SDR_Pos)        /*!< 0xFFFF0000 */
+#define MDF_SNPSDR_SDR                      MDF_SNPSDR_SDR_Msk                      /*!<Extended data size*/
+
+/*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
+#define MDF_DFLTDR_DR_Pos                   (8U)
+#define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
+#define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!<MCIC decimation counter*/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 MDIOS                                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Public Key Accelerator (PKA)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PKA_CR register  *********************/
+#define PKA_CR_EN_Pos                       (0U)
+#define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
+#define PKA_CR_EN                           PKA_CR_EN_Msk                           /*!< PKA enable */
+#define PKA_CR_START_Pos                    (1U)
+#define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
+#define PKA_CR_START                        PKA_CR_START_Msk                        /*!< Start operation */
+#define PKA_CR_MODE_Pos                     (8U)
+#define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
+#define PKA_CR_MODE                         PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
+#define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
+#define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
+#define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
+#define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
+#define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
+#define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
+#define PKA_CR_PROCENDIE_Pos                (17U)
+#define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
+#define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
+#define PKA_CR_RAMERRIE_Pos                 (19U)
+#define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
+#define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
+#define PKA_CR_ADDRERRIE_Pos                (20U)
+#define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
+#define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                    /*!< Address error interrupt enable */
+#define PKA_CR_OPERRIE_Pos                  (21U)
+#define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)           /*!< 0x00200000 */
+#define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                      /*!< Operation Error interrupt enable */
+
+/*******************  Bit definition for PKA_SR register  *********************/
+#define PKA_SR_INITOK_Pos                   (0U)
+#define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)            /*!< 0x00000001 */
+#define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                       /*!< PKA initialisation flag */
+#define PKA_SR_BUSY_Pos                     (16U)
+#define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
+#define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
+#define PKA_SR_PROCENDF_Pos                 (17U)
+#define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
+#define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
+#define PKA_SR_RAMERRF_Pos                  (19U)
+#define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
+#define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
+#define PKA_SR_ADDRERRF_Pos                 (20U)
+#define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
+#define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
+#define PKA_SR_OPERRF_Pos                   (21U)
+#define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)            /*!< 0x00200000 */
+#define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                       /*!< PKA operation Error flag*/
+
+/*******************  Bit definition for PKA_CLRFR register  ******************/
+#define PKA_CLRFR_PROCENDFC_Pos             (17U)
+#define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
+#define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
+#define PKA_CLRFR_RAMERRFC_Pos              (19U)
+#define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
+#define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
+#define PKA_CLRFR_ADDRERRFC_Pos             (20U)
+#define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
+#define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
+#define PKA_CLRFR_OPERRFC_Pos               (21U)
+#define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)        /*!< 0x00200000 */
+#define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                   /*!< Clear PKA operation Error flag*/
+
+/*******************  Bits definition for PKA RAM  *************************/
+#define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */
+
+/* Compute Montgomery parameter input data */
+#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Compute Montgomery parameter output data */
+#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */
+
+/* Compute modular exponentiation input data */
+#define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
+#define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+#define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
+#define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
+#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
+#define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */
+
+/* Compute modular exponentiation output data */
+#define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
+#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
+#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */
+
+/* Compute ECC scalar multiplication input data */
+#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */
+
+/* Compute ECC scalar multiplication output data */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
+#define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
+
+/* Point check input data */
+#define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
+
+/* Point check output data */
+#define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+
+/* ECDSA signature input data */
+#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
+#define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
+#define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA signature output data */
+#define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */
+
+
+/* ECDSA verification input data */
+#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
+#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
+#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
+#define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
+#define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
+#define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
+#define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+
+/* ECDSA verification output data */
+#define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* RSA CRT exponentiation input data */
+#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
+#define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
+#define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
+#define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
+#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
+
+/* RSA CRT exponentiation output data */
+#define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular reduction input data */
+#define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
+#define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
+#define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
+#define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
+
+/* Modular reduction output data */
+#define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic addition input data */
+#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic addition output data */
+#define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic subtraction input data */
+#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic subtraction output data */
+#define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Arithmetic multiplication input data */
+#define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Arithmetic multiplication output data */
+#define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Comparison input data */
+#define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+
+/* Comparison output data */
+#define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular addition input data */
+#define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
+
+/* Modular addition output data */
+#define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular inversion input data */
+#define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
+
+/* Modular inversion output data */
+#define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Modular subtraction input data */
+#define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
+
+/* Modular subtraction output data */
+#define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Montgomery multiplication input data */
+#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
+
+/* Montgomery multiplication output data */
+#define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
+
+/* Generic Arithmetic input data */
+#define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
+#define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
+
+/* Generic Arithmetic output data */
+#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)   /*!< Output result for arithmetic operations */
+
+/* Compute ECC complete addition input data */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)   /*!< Input Modulus number of bits */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Z coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q X coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)   /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC complete addition output data */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
+#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)   /*!< Output result Z coordinate */
+
+/* Compute ECC double base ladder input data */
+#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS  ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN         ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF              ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
+#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER            ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X             ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y             ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z             ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X             ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y             ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
+#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z             ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
+
+/* Compute ECC double base ladder output data */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)      /*!< Output result X coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y          ((0x05D0UL - PKA_RAM_OFFSET)>>2)      /*!< Output result Y coordinate (affine coordinate) */
+#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR             ((0x0520UL - PKA_RAM_OFFSET)>>2)      /*!< Output result error */
+
+/* Compute ECC projective to affine conversion input data */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)  /*!< Input Modulus number of bits */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)  /*!< Input modulus GF(p) */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X               ((0x0D60UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P X coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y               ((0x0DB8UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Y coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z               ((0x0E10UL - PKA_RAM_OFFSET)>>2)  /*!< Input initial projective point P Z coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2   ((0x04C8UL - PKA_RAM_OFFSET)>>2)  /*!< Input storage area for Montgomery parameter */
+
+/* Compute ECC projective to affine conversion output data */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X      ((0x0578UL - PKA_RAM_OFFSET)>>2)         /*!< Output result x affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y      ((0x05D0UL - PKA_RAM_OFFSET)>>2)         /*!< Output result y affine coordinate */
+#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR         ((0x0680UL - PKA_RAM_OFFSET)>>2)         /*!< Output result error */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                Parallel Synchronous Slave Interface (PSSI )                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PSSI_CR register  *******************/
+#define PSSI_CR_CKPOL_Pos                   (5U)
+#define PSSI_CR_CKPOL_Msk                   (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
+#define PSSI_CR_CKPOL                       PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
+#define PSSI_CR_DEPOL_Pos                   (6U)
+#define PSSI_CR_DEPOL_Msk                   (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
+#define PSSI_CR_DEPOL                       PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
+#define PSSI_CR_RDYPOL_Pos                  (8U)
+#define PSSI_CR_RDYPOL_Msk                  (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
+#define PSSI_CR_RDYPOL                      PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
+#define PSSI_CR_EDM_Pos                     (10U)
+#define PSSI_CR_EDM_Msk                     (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
+#define PSSI_CR_EDM                         PSSI_CR_EDM_Msk                         /*!< Extended data mode */
+#define PSSI_CR_ENABLE_Pos                  (14U)
+#define PSSI_CR_ENABLE_Msk                  (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
+#define PSSI_CR_ENABLE                      PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
+#define PSSI_CR_DERDYCFG_Pos                (18U)
+#define PSSI_CR_DERDYCFG_Msk                (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
+#define PSSI_CR_DERDYCFG                    PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
+#define PSSI_CR_CKSRC_Pos                   (29U)
+#define PSSI_CR_CKSRC_Msk                   (0x1UL << PSSI_CR_CKSRC_Pos)            /*!< 0x20000000 */
+#define PSSI_CR_CKSRC                       PSSI_CR_CKSRC_Msk                       /*!< Clock source */
+#define PSSI_CR_DMAEN_Pos                   (30U)
+#define PSSI_CR_DMAEN_Msk                   (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
+#define PSSI_CR_DMAEN                       PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
+#define PSSI_CR_OUTEN_Pos                   (31U)
+#define PSSI_CR_OUTEN_Msk                   (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
+#define PSSI_CR_OUTEN                       PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */
+
+/********************  Bit definition for PSSI_SR register  *******************/
+#define PSSI_SR_RTT4B_Pos                   (2U)
+#define PSSI_SR_RTT4B_Msk                   (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
+#define PSSI_SR_RTT4B                       PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
+#define PSSI_SR_RTT1B_Pos                   (3U)
+#define PSSI_SR_RTT1B_Msk                   (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
+#define PSSI_SR_RTT1B                       PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */
+
+/********************  Bit definition for PSSI_RIS register  *******************/
+#define PSSI_RIS_OVR_RIS_Pos                (1U)
+#define PSSI_RIS_OVR_RIS_Msk                (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
+#define PSSI_RIS_OVR_RIS                    PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */
+
+/********************  Bit definition for PSSI_IER register  *******************/
+#define PSSI_IER_OVR_IE_Pos                 (1U)
+#define PSSI_IER_OVR_IE_Msk                 (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
+#define PSSI_IER_OVR_IE                     PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */
+
+/********************  Bit definition for PSSI_MIS register  *******************/
+#define PSSI_MIS_OVR_MIS_Pos                (1U)
+#define PSSI_MIS_OVR_MIS_Msk                (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
+#define PSSI_MIS_OVR_MIS                    PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */
+
+/********************  Bit definition for PSSI_ICR register  *******************/
+#define PSSI_ICR_OVR_ISC_Pos                (1U)
+#define PSSI_ICR_OVR_ISC_Msk                (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
+#define PSSI_ICR_OVR_ISC                    PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */
+
+/********************  Bit definition for PSSI_DR register  *******************/
+#define PSSI_DR_DR_Pos                      (0U)
+#define PSSI_DR_DR_Msk                      (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
+#define PSSI_DR_DR                          PSSI_DR_DR_Msk                          /*!< Data register  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for PWR_CR1 register  ********************/
+#define PWR_CR1_SDEN_Pos                (2U)
+#define PWR_CR1_SDEN_Msk                (0x1UL << PWR_CR1_SDEN_Pos)             /*!< 0x00000004 */
+#define PWR_CR1_SDEN                    PWR_CR1_SDEN_Msk                        /*!< SMPS step-down converter enable */
+#define PWR_CR1_MODE_PDN_Pos            (4U)
+#define PWR_CR1_MODE_PDN_Msk            (0x1UL << PWR_CR1_MODE_PDN_Pos)         /*!< 0x00000010 */
+#define PWR_CR1_MODE_PDN                PWR_CR1_MODE_PDN_Msk                    /*!< Pull down on output voltage during power down mode */
+#define PWR_CR1_LPDS08V_Pos             (5U)
+#define PWR_CR1_LPDS08V_Msk             (0x1UL << PWR_CR1_LPDS08V_Pos)          /*!< 0x00000020 */
+#define PWR_CR1_LPDS08V                 PWR_CR1_LPDS08V_Msk                     /*!< SMPS Low power mode enable (SVOS high only) */
+#define PWR_CR1_VDD18SMPSVMEN_Pos       (8U)
+#define PWR_CR1_VDD18SMPSVMEN_Msk       (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos)    /*!< 0x00000100 */
+#define PWR_CR1_VDD18SMPSVMEN           PWR_CR1_VDD18SMPSVMEN_Msk               /*!< VDD18SMPS voltage monitor enable */
+#define PWR_CR1_VDD18SMPSRDY_Pos        (15U)
+#define PWR_CR1_VDD18SMPSRDY_Msk        (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos)     /*!< 0x00008000 */
+#define PWR_CR1_VDD18SMPSRDY            PWR_CR1_VDD18SMPSRDY_Msk                /*!< VDD18SMPS ready */
+#define PWR_CR1_POPL_Pos                (16U)
+#define PWR_CR1_POPL_Msk                (0x1FUL << PWR_CR1_POPL_Pos)            /*!< 0x001F0000 */
+#define PWR_CR1_POPL                    PWR_CR1_POPL_Msk                        /*!< pwr_on pulse low configuration */
+#define PWR_CR1_POPL_0                  (0x1UL << PWR_CR1_POPL_Pos)             /*!< 0x00010000 */
+#define PWR_CR1_POPL_1                  (0x2UL << PWR_CR1_POPL_Pos)             /*!< 0x00020000 */
+#define PWR_CR1_POPL_2                  (0x4UL << PWR_CR1_POPL_Pos)             /*!< 0x00040000 */
+#define PWR_CR1_POPL_3                  (0x8UL << PWR_CR1_POPL_Pos)             /*!< 0x00080000 */
+#define PWR_CR1_POPL_4                  (0x10UL << PWR_CR1_POPL_Pos)            /*!< 0x00100000 */
+
+/*******************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_PVDEN_Pos               (0U)
+#define PWR_CR2_PVDEN_Msk               (0x1UL << PWR_CR2_PVDEN_Pos)            /*!< 0x00000001 */
+#define PWR_CR2_PVDEN                   PWR_CR2_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR2_PVDO_Pos                (8U)
+#define PWR_CR2_PVDO_Msk                (0x1UL << PWR_CR2_PVDO_Pos)             /*!< 0x00000100 */
+#define PWR_CR2_PVDO                    PWR_CR2_PVDO_Msk                        /*!< Programmable Voltage Detect Output */
+
+/*******************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_VCOREMONEN_Pos          (0U)
+#define PWR_CR3_VCOREMONEN_Msk          (0x1UL << PWR_CR3_VCOREMONEN_Pos)       /*!< 0x00000001 */
+#define PWR_CR3_VCOREMONEN              PWR_CR3_VCOREMONEN_Msk                  /*!< VDDCORE monitoring enable */
+#define PWR_CR3_VCORELLS_Pos            (4U)
+#define PWR_CR3_VCORELLS_Msk            (0x1UL << PWR_CR3_VCORELLS_Pos)         /*!< 0x00000010 */
+#define PWR_CR3_VCORELLS                PWR_CR3_VCORELLS_Msk                    /*!< VDDCORE Voltage Detector low level selection */
+#define PWR_CR3_VCOREL_Pos              (8U)
+#define PWR_CR3_VCOREL_Msk              (0x1UL << PWR_CR3_VCOREL_Pos)           /*!< 0x00000100 */
+#define PWR_CR3_VCOREL                  PWR_CR3_VCOREL_Msk                      /*!< Monitored VDDCORE level above low threshold */
+#define PWR_CR3_VCOREH_Pos              (9U)
+#define PWR_CR3_VCOREH_Msk              (0x1UL << PWR_CR3_VCOREH_Pos)           /*!< 0x00000200 */
+#define PWR_CR3_VCOREH                  PWR_CR3_VCOREH_Msk                      /*!< Monitored VDDCORE level above high threshold */
+
+/*******************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_TCMRBSEN_Pos            (0U)
+#define PWR_CR4_TCMRBSEN_Msk            (0x1UL << PWR_CR4_TCMRBSEN_Pos)         /*!< 0x00000001 */
+#define PWR_CR4_TCMRBSEN                PWR_CR4_TCMRBSEN_Msk                    /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */
+#define PWR_CR4_TCMFLXRBSEN_Pos         (4U)
+#define PWR_CR4_TCMFLXRBSEN_Msk         (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos)      /*!< 0x00000010 */
+#define PWR_CR4_TCMFLXRBSEN             PWR_CR4_TCMFLXRBSEN_Msk                 /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */
+
+/******************  Bit definition for PWR_VOSCR register  *******************/
+#define PWR_VOSCR_VOS_Pos               (0U)
+#define PWR_VOSCR_VOS_Msk               (0x1UL << PWR_VOSCR_VOS_Pos)            /*!< 0x00000001 */
+#define PWR_VOSCR_VOS                   PWR_VOSCR_VOS_Msk                       /*!< Voltage scaling selection according to performance */
+#define PWR_VOSCR_VOSRDY_Pos            (1U)
+#define PWR_VOSCR_VOSRDY_Msk            (0x1UL << PWR_VOSCR_VOSRDY_Pos)         /*!< 0x00000002 */
+#define PWR_VOSCR_VOSRDY                PWR_VOSCR_VOSRDY_Msk                    /*!< VOS Ready bit for VCORE voltage scaling output selection */
+#define PWR_VOSCR_ACTVOS_Pos            (16U)
+#define PWR_VOSCR_ACTVOS_Msk            (0x1UL << PWR_VOSCR_ACTVOS_Pos)         /*!< 0x00010000 */
+#define PWR_VOSCR_ACTVOS                PWR_VOSCR_ACTVOS_Msk                    /*!< VOS currently applied for VCORE voltage scaling selection */
+#define PWR_VOSCR_ACTVOSRDY_Pos         (17U)
+#define PWR_VOSCR_ACTVOSRDY_Msk         (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos)      /*!< 0x00020000 */
+#define PWR_VOSCR_ACTVOSRDY             PWR_VOSCR_ACTVOSRDY_Msk                 /*!< Voltage levels ready bit for currently used ACTVOS */
+
+/******************  Bit definition for PWR_BDCR1 register  *******************/
+#define PWR_BDCR1_MONEN_Pos             (0U)
+#define PWR_BDCR1_MONEN_Msk             (0x1UL << PWR_BDCR1_MONEN_Pos)          /*!< 0x00000001 */
+#define PWR_BDCR1_MONEN                 PWR_BDCR1_MONEN_Msk                     /*!< VBAT and temperature monitoring enable */
+#define PWR_BDCR1_VBATL_Pos             (16U)
+#define PWR_BDCR1_VBATL_Msk             (0x1UL << PWR_BDCR1_VBATL_Pos)          /*!< 0x00010000 */
+#define PWR_BDCR1_VBATL                 PWR_BDCR1_VBATL_Msk                     /*!< VBAT level monitoring versus low threshold */
+#define PWR_BDCR1_VBATH_Pos             (17U)
+#define PWR_BDCR1_VBATH_Msk             (0x1UL << PWR_BDCR1_VBATH_Pos)          /*!< 0x00020000 */
+#define PWR_BDCR1_VBATH                 PWR_BDCR1_VBATH_Msk                     /*!< VBAT level monitoring versus high threshold */
+#define PWR_BDCR1_TEMPL_Pos             (18U)
+#define PWR_BDCR1_TEMPL_Msk             (0x1UL << PWR_BDCR1_TEMPL_Pos)          /*!< 0x00040000 */
+#define PWR_BDCR1_TEMPL                 PWR_BDCR1_TEMPL_Msk                     /*!< Temperature level monitoring versus low threshold */
+#define PWR_BDCR1_TEMPH_Pos             (19U)
+#define PWR_BDCR1_TEMPH_Msk             (0x1UL << PWR_BDCR1_TEMPH_Pos)          /*!< 0x00080000 */
+#define PWR_BDCR1_TEMPH                 PWR_BDCR1_TEMPH_Msk                     /*!< Temperature level monitoring versus high threshold */
+
+/******************  Bit definition for PWR_BDCR2 register  *******************/
+#define PWR_BDCR2_BKPRBSEN_Pos          (0U)
+#define PWR_BDCR2_BKPRBSEN_Msk          (0x1UL << PWR_BDCR2_BKPRBSEN_Pos)       /*!< 0x00000001 */
+#define PWR_BDCR2_BKPRBSEN              PWR_BDCR2_BKPRBSEN_Msk                  /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */
+
+/******************  Bit definition for PWR_DBPCR register  *******************/
+#define PWR_DBPCR_DBP_Pos               (0U)
+#define PWR_DBPCR_DBP_Msk               (0x1UL << PWR_DBPCR_DBP_Pos)            /*!< 0x00000001 */
+#define PWR_DBPCR_DBP                   PWR_DBPCR_DBP_Msk                       /*!< Disable backup domain write protection */
+
+/******************  Bit definition for PWR_CPUCR register  *******************/
+#define PWR_CPUCR_PDDS_Pos              (0U)
+#define PWR_CPUCR_PDDS_Msk              (0x1UL << PWR_CPUCR_PDDS_Pos)           /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS                  PWR_CPUCR_PDDS_Msk                      /*!< Power Down Deepsleep selection */
+#define PWR_CPUCR_CSSF_Pos              (1U)
+#define PWR_CPUCR_CSSF_Msk              (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000002 */
+#define PWR_CPUCR_CSSF                  PWR_CPUCR_CSSF_Msk                      /*!< Clear Standby and Stop flags (always read as 0) */
+#define PWR_CPUCR_STOPF_Pos             (8U)
+#define PWR_CPUCR_STOPF_Msk             (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000100 */
+#define PWR_CPUCR_STOPF                 PWR_CPUCR_STOPF_Msk                     /*!< STOP flag */
+#define PWR_CPUCR_SBF_Pos               (9U)
+#define PWR_CPUCR_SBF_Msk               (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000200 */
+#define PWR_CPUCR_SBF                   PWR_CPUCR_SBF_Msk                       /*!< System Standby flag */
+#define PWR_CPUCR_SVOS_Pos              (16U)
+#define PWR_CPUCR_SVOS_Msk              (0x1UL << PWR_CPUCR_SVOS_Pos)           /*!< 0x00010000 */
+#define PWR_CPUCR_SVOS                  PWR_CPUCR_SVOS_Msk                      /*!< System Stop mode voltage scaling selection */
+
+/******************  Bit definition for PWR_SVMCR1 register  ******************/
+#define PWR_SVMCR1_VDDIO4VMEN_Pos       (0U)
+#define PWR_SVMCR1_VDDIO4VMEN_Msk       (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR1_VDDIO4VMEN           PWR_SVMCR1_VDDIO4VMEN_Msk               /*!< VDDOI4 Independent I/Os voltage monitor enable */
+#define PWR_SVMCR1_VDDIO4SV_Pos         (8U)
+#define PWR_SVMCR1_VDDIO4SV_Msk         (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR1_VDDIO4SV             PWR_SVMCR1_VDDIO4SV_Msk                 /*!< VDDIO4 Independent I/Os supply valid */
+#define PWR_SVMCR1_VDDIO4RDY_Pos        (16U)
+#define PWR_SVMCR1_VDDIO4RDY_Msk        (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR1_VDDIO4RDY            PWR_SVMCR1_VDDIO4RDY_Msk                /*!< VDDIO4 ready */
+#define PWR_SVMCR1_VDDIO4VRSEL_Pos      (24U)
+#define PWR_SVMCR1_VDDIO4VRSEL_Msk      (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR1_VDDIO4VRSEL          PWR_SVMCR1_VDDIO4VRSEL_Msk              /*!< VDDIO4 IO voltage range selection */
+#define PWR_SVMCR1_VDDIO4VRSTBY_Pos     (25U)
+#define PWR_SVMCR1_VDDIO4VRSTBY_Msk     (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos)  /*!< 0x04000000 */
+#define PWR_SVMCR1_VDDIO4VRSTBY         PWR_SVMCR1_VDDIO4VRSTBY_Msk             /*!< VDDIO4 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR2 register  ******************/
+#define PWR_SVMCR2_VDDIO5VMEN_Pos       (0U)
+#define PWR_SVMCR2_VDDIO5VMEN_Msk       (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR2_VDDIO5VMEN           PWR_SVMCR2_VDDIO5VMEN_Msk               /*!< VDDIO5 Independent voltage monitor enable */
+#define PWR_SVMCR2_VDDIO5SV_Pos         (8U)
+#define PWR_SVMCR2_VDDIO5SV_Msk         (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR2_VDDIO5SV             PWR_SVMCR2_VDDIO5SV_Msk                 /*!< VDDIO5 Independent supply valid */
+#define PWR_SVMCR2_VDDIO5RDY_Pos        (16U)
+#define PWR_SVMCR2_VDDIO5RDY_Msk        (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR2_VDDIO5RDY            PWR_SVMCR2_VDDIO5RDY_Msk                /*!< VDDIO5 ready */
+#define PWR_SVMCR2_VDDIO5VRSEL_Pos      (24U)
+#define PWR_SVMCR2_VDDIO5VRSEL_Msk      (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos)   /*!< 0x01000000 */
+#define PWR_SVMCR2_VDDIO5VRSEL          PWR_SVMCR2_VDDIO5VRSEL_Msk              /*!< VDDIO5 IO voltage range selection */
+#define PWR_SVMCR2_VDDIO5VRSTBY_Pos     (25U)
+#define PWR_SVMCR2_VDDIO5VRSTBY_Msk     (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos)  /*!< 0x02000000 */
+#define PWR_SVMCR2_VDDIO5VRSTBY         PWR_SVMCR2_VDDIO5VRSTBY_Msk             /*!< VDDIO5 IO voltage range standby mode */
+
+/******************  Bit definition for PWR_SVMCR3 register  ******************/
+#define PWR_SVMCR3_VDDIO2VMEN_Pos       (0U)
+#define PWR_SVMCR3_VDDIO2VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos)    /*!< 0x00000001 */
+#define PWR_SVMCR3_VDDIO2VMEN           PWR_SVMCR3_VDDIO2VMEN_Msk               /*!< VDDIO2 Independent voltage monitor enable */
+#define PWR_SVMCR3_VDDIO3VMEN_Pos       (1U)
+#define PWR_SVMCR3_VDDIO3VMEN_Msk       (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos)    /*!< 0x00000002 */
+#define PWR_SVMCR3_VDDIO3VMEN           PWR_SVMCR3_VDDIO3VMEN_Msk               /*!< VDDIO3 Independent voltage monitor enable */
+#define PWR_SVMCR3_USB33VMEN_Pos        (2U)
+#define PWR_SVMCR3_USB33VMEN_Msk        (0x1UL << PWR_SVMCR3_USB33VMEN_Pos)     /*!< 0x00000004 */
+#define PWR_SVMCR3_USB33VMEN            PWR_SVMCR3_USB33VMEN_Msk                /*!< VDD33USB Independent USB 33 voltage monitor enable */
+#define PWR_SVMCR3_AVMEN_Pos            (4U)
+#define PWR_SVMCR3_AVMEN_Msk            (0x1UL << PWR_SVMCR3_AVMEN_Pos)         /*!< 0x00000010 */
+#define PWR_SVMCR3_AVMEN                PWR_SVMCR3_AVMEN_Msk                    /*!< VDDA18ADC Independent ADC voltage monitor enable */
+#define PWR_SVMCR3_VDDIO2SV_Pos         (8U)
+#define PWR_SVMCR3_VDDIO2SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos)      /*!< 0x00000100 */
+#define PWR_SVMCR3_VDDIO2SV             PWR_SVMCR3_VDDIO2SV_Msk                 /*!< VDDIO2 Independent supply valid */
+#define PWR_SVMCR3_VDDIO3SV_Pos         (9U)
+#define PWR_SVMCR3_VDDIO3SV_Msk         (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos)      /*!< 0x00000200 */
+#define PWR_SVMCR3_VDDIO3SV             PWR_SVMCR3_VDDIO3SV_Msk                 /*!< VDDIO3 Independent supply valid */
+#define PWR_SVMCR3_USB33SV_Pos          (10U)
+#define PWR_SVMCR3_USB33SV_Msk          (0x1UL << PWR_SVMCR3_USB33SV_Pos)       /*!< 0x00000400 */
+#define PWR_SVMCR3_USB33SV              PWR_SVMCR3_USB33SV_Msk                  /*!< VDD33USB Independent supply valid */
+#define PWR_SVMCR3_ASV_Pos              (12U)
+#define PWR_SVMCR3_ASV_Msk              (0x1UL << PWR_SVMCR3_ASV_Pos)           /*!< 0x00001000 */
+#define PWR_SVMCR3_ASV                  PWR_SVMCR3_ASV_Msk                      /*!< VDDA18ADC Independent supply valid */
+#define PWR_SVMCR3_VDDIO2RDY_Pos        (16U)
+#define PWR_SVMCR3_VDDIO2RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos)     /*!< 0x00010000 */
+#define PWR_SVMCR3_VDDIO2RDY            PWR_SVMCR3_VDDIO2RDY_Msk                /*!< VDDIO2 ready */
+#define PWR_SVMCR3_VDDIO3RDY_Pos        (17U)
+#define PWR_SVMCR3_VDDIO3RDY_Msk        (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos)     /*!< 0x00020000 */
+#define PWR_SVMCR3_VDDIO3RDY            PWR_SVMCR3_VDDIO3RDY_Msk                /*!< VDDIO3 ready */
+#define PWR_SVMCR3_USB33RDY_Pos         (18U)
+#define PWR_SVMCR3_USB33RDY_Msk         (0x1UL << PWR_SVMCR3_USB33RDY_Pos)      /*!< 0x00040000 */
+#define PWR_SVMCR3_USB33RDY             PWR_SVMCR3_USB33RDY_Msk                 /*!< VDD33USB ready */
+#define PWR_SVMCR3_ARDY_Pos             (20U)
+#define PWR_SVMCR3_ARDY_Msk             (0x1UL << PWR_SVMCR3_ARDY_Pos)          /*!< 0x00100000 */
+#define PWR_SVMCR3_ARDY                 PWR_SVMCR3_ARDY_Msk                     /*!< VDDA18ADC ready */
+#define PWR_SVMCR3_VDDIOVRSEL_Pos       (24U)
+#define PWR_SVMCR3_VDDIOVRSEL_Msk       (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos)    /*!< 0x01000000 */
+#define PWR_SVMCR3_VDDIOVRSEL           PWR_SVMCR3_VDDIOVRSEL_Msk               /*!< VDD IO voltage range selection */
+#define PWR_SVMCR3_VDDIO2VRSEL_Pos      (25U)
+#define PWR_SVMCR3_VDDIO2VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos)   /*!< 0x02000000 */
+#define PWR_SVMCR3_VDDIO2VRSEL          PWR_SVMCR3_VDDIO2VRSEL_Msk              /*!< VDDIO2 IO voltage range selection */
+#define PWR_SVMCR3_VDDIO3VRSEL_Pos      (26U)
+#define PWR_SVMCR3_VDDIO3VRSEL_Msk      (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos)   /*!< 0x04000000 */
+#define PWR_SVMCR3_VDDIO3VRSEL          PWR_SVMCR3_VDDIO3VRSEL_Msk              /*!< VDDIO3 IO voltage range selection */
+
+/*****************  Bit definition for PWR_WKUPCR register  *******************/
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                    /*!< Clear Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                    /*!< Clear Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                    /*!< Clear Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                    /*!< Clear Wakeup Flag for WKUP4 pin */
+#define PWR_WKUPCR_WKUPC_Pos           (0U)
+#define PWR_WKUPCR_WKUPC_Msk           (0xFUL << PWR_WKUPCR_WKUPC_Pos)         /*!< 0x0000000F */
+#define PWR_WKUPCR_WKUPC               PWR_WKUPCR_WKUPC_Msk                    /*!< Clear Wakeup Flag 1 to 4 */
+
+/*****************  Bit definition for PWR_WKUPSR register  *******************/
+#define PWR_WKUPSR_WKUPF1_Pos          (0U)
+#define PWR_WKUPSR_WKUPF1_Msk          (0x1UL << PWR_WKUPSR_WKUPF1_Pos)         /*!< 0x00000001 */
+#define PWR_WKUPSR_WKUPF1              PWR_WKUPSR_WKUPF1_Msk                    /*!< Wakeup Flag for WKUP1 pin */
+#define PWR_WKUPSR_WKUPF2_Pos          (1U)
+#define PWR_WKUPSR_WKUPF2_Msk          (0x1UL << PWR_WKUPSR_WKUPF2_Pos)         /*!< 0x00000002 */
+#define PWR_WKUPSR_WKUPF2              PWR_WKUPSR_WKUPF2_Msk                    /*!< Wakeup Flag for WKUP2 pin */
+#define PWR_WKUPSR_WKUPF3_Pos          (2U)
+#define PWR_WKUPSR_WKUPF3_Msk          (0x1UL << PWR_WKUPSR_WKUPF3_Pos)         /*!< 0x00000004 */
+#define PWR_WKUPSR_WKUPF3              PWR_WKUPSR_WKUPF3_Msk                    /*!< Wakeup Flag for WKUP3 pin */
+#define PWR_WKUPSR_WKUPF4_Pos          (3U)
+#define PWR_WKUPSR_WKUPF4_Msk          (0x1UL << PWR_WKUPSR_WKUPF4_Pos)         /*!< 0x00000008 */
+#define PWR_WKUPSR_WKUPF4              PWR_WKUPSR_WKUPF4_Msk                    /*!< Wakeup Flag for WKUP4 pin */
+
+/*****************  Bit definition for PWR_WKUPEPR register  *******************/
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)       /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                  /*!< Enable Wakeup pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)       /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                  /*!< Enable Wakeup pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)       /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                  /*!< Enable Wakeup pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)       /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                  /*!< Enable Wakeup pin WKUP4 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)        /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                   /*!< Wakeup Polarity bit for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)        /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                   /*!< Wakeup Polarity bit for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)        /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                   /*!< Wakeup Polarity bit for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)        /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                   /*!< Wakeup Polarity bit for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPP_Pos          (8U)
+#define PWR_WKUPEPR_WKUPP_Msk          (0x0FUL << PWR_WKUPEPR_WKUPP_Pos)        /*!< 0x0000300F */
+#define PWR_WKUPEPR_WKUPP              PWR_WKUPEPR_WKUPP_Msk                    /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk                /*!< Wakeup pull configuration for WKUP1 pin */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)     /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk                /*!< Wakeup pull configuration for WKUP2 pin */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)     /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk                /*!< Wakeup pull configuration for WKUP3 pin */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)     /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk                /*!< Wakeup pull configuration for WKUP4 pin */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)     /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos)       /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                   /*!< Enable all Wakeup Pin */
+
+/*****************  Bit definition for PWR_SECCFGR register  ******************/
+#define PWR_SECCFGR_SEC0_Pos            (0U)
+#define PWR_SECCFGR_SEC0_Msk            (0x1UL << PWR_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
+#define PWR_SECCFGR_SEC0                PWR_SECCFGR_SEC0_Msk                    /*!< System supply configuration secure protection */
+#define PWR_SECCFGR_SEC1_Pos            (1U)
+#define PWR_SECCFGR_SEC1_Msk            (0x1UL << PWR_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
+#define PWR_SECCFGR_SEC1                PWR_SECCFGR_SEC1_Msk                    /*!< Programmable voltage detector secure protection */
+#define PWR_SECCFGR_SEC2_Pos            (2U)
+#define PWR_SECCFGR_SEC2_Msk            (0x1UL << PWR_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
+#define PWR_SECCFGR_SEC2                PWR_SECCFGR_SEC2_Msk                    /*!< VDDCORE monitor secure protection */
+#define PWR_SECCFGR_SEC3_Pos            (3U)
+#define PWR_SECCFGR_SEC3_Msk            (0x1UL << PWR_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
+#define PWR_SECCFGR_SEC3                PWR_SECCFGR_SEC3_Msk                    /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */
+#define PWR_SECCFGR_SEC4_Pos            (4U)
+#define PWR_SECCFGR_SEC4_Msk            (0x1UL << PWR_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
+#define PWR_SECCFGR_SEC4                PWR_SECCFGR_SEC4_Msk                    /*!< Voltage scaling selection secure protection */
+#define PWR_SECCFGR_SEC5_Pos            (5U)
+#define PWR_SECCFGR_SEC5_Msk            (0x1UL << PWR_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
+#define PWR_SECCFGR_SEC5                PWR_SECCFGR_SEC5_Msk                    /*!< Backup domain secure protection */
+#define PWR_SECCFGR_SEC6_Pos            (6U)
+#define PWR_SECCFGR_SEC6_Msk            (0x1UL << PWR_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
+#define PWR_SECCFGR_SEC6                PWR_SECCFGR_SEC6_Msk                    /*!< CPU power control secure protection */
+#define PWR_SECCFGR_SEC7_Pos            (7U)
+#define PWR_SECCFGR_SEC7_Msk            (0x1UL << PWR_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
+#define PWR_SECCFGR_SEC7                PWR_SECCFGR_SEC7_Msk                    /*!< Peripheral voltage monitor secure protection */
+#define PWR_SECCFGR_WKUPSEC1_Pos        (16U)
+#define PWR_SECCFGR_WKUPSEC1_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos)     /*!< 0x00010000 */
+#define PWR_SECCFGR_WKUPSEC1            PWR_SECCFGR_WKUPSEC1_Msk                /*!< WKUP1 secure protection */
+#define PWR_SECCFGR_WKUPSEC2_Pos        (17U)
+#define PWR_SECCFGR_WKUPSEC2_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos)     /*!< 0x00020000 */
+#define PWR_SECCFGR_WKUPSEC2            PWR_SECCFGR_WKUPSEC2_Msk                /*!< WKUP2 secure protection */
+#define PWR_SECCFGR_WKUPSEC3_Pos        (18U)
+#define PWR_SECCFGR_WKUPSEC3_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos)     /*!< 0x00040000 */
+#define PWR_SECCFGR_WKUPSEC3            PWR_SECCFGR_WKUPSEC3_Msk                /*!< WKUP3 secure protection */
+#define PWR_SECCFGR_WKUPSEC4_Pos        (19U)
+#define PWR_SECCFGR_WKUPSEC4_Msk        (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos)     /*!< 0x00080000 */
+#define PWR_SECCFGR_WKUPSEC4            PWR_SECCFGR_WKUPSEC4_Msk                /*!< WKUP4 secure protection */
+
+/*****************  Bit definition for PWR_PRIVCFGR register  *****************/
+#define PWR_PRIVCFGR_PRIV0_Pos          (0U)
+#define PWR_PRIVCFGR_PRIV0_Msk          (0x1UL << PWR_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
+#define PWR_PRIVCFGR_PRIV0              PWR_PRIVCFGR_PRIV0_Msk                  /*!< System supply configuration privileged protection */
+#define PWR_PRIVCFGR_PRIV1_Pos          (1U)
+#define PWR_PRIVCFGR_PRIV1_Msk          (0x1UL << PWR_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
+#define PWR_PRIVCFGR_PRIV1              PWR_PRIVCFGR_PRIV1_Msk                  /*!< Programmable voltage detector privileged protection */
+#define PWR_PRIVCFGR_PRIV2_Pos          (2U)
+#define PWR_PRIVCFGR_PRIV2_Msk          (0x1UL << PWR_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
+#define PWR_PRIVCFGR_PRIV2              PWR_PRIVCFGR_PRIV2_Msk                  /*!< VDDCORE monitor privileged protection */
+#define PWR_PRIVCFGR_PRIV3_Pos          (3U)
+#define PWR_PRIVCFGR_PRIV3_Msk          (0x1UL << PWR_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
+#define PWR_PRIVCFGR_PRIV3              PWR_PRIVCFGR_PRIV3_Msk                  /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */
+#define PWR_PRIVCFGR_PRIV4_Pos          (4U)
+#define PWR_PRIVCFGR_PRIV4_Msk          (0x1UL << PWR_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
+#define PWR_PRIVCFGR_PRIV4              PWR_PRIVCFGR_PRIV4_Msk                  /*!< Voltage scaling selection privileged protection */
+#define PWR_PRIVCFGR_PRIV5_Pos          (5U)
+#define PWR_PRIVCFGR_PRIV5_Msk          (0x1UL << PWR_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
+#define PWR_PRIVCFGR_PRIV5              PWR_PRIVCFGR_PRIV5_Msk                  /*!< Backup domain privileged protection */
+#define PWR_PRIVCFGR_PRIV6_Pos          (6U)
+#define PWR_PRIVCFGR_PRIV6_Msk          (0x1UL << PWR_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
+#define PWR_PRIVCFGR_PRIV6              PWR_PRIVCFGR_PRIV6_Msk                  /*!< CPU power control privileged protection */
+#define PWR_PRIVCFGR_PRIV7_Pos          (7U)
+#define PWR_PRIVCFGR_PRIV7_Msk          (0x1UL << PWR_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
+#define PWR_PRIVCFGR_PRIV7              PWR_PRIVCFGR_PRIV7_Msk                  /*!< Peripheral voltage monitor privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV1_Pos      (16U)
+#define PWR_PRIVCFGR_WKUPPRIV1_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos)   /*!< 0x00010000 */
+#define PWR_PRIVCFGR_WKUPPRIV1          PWR_PRIVCFGR_WKUPPRIV1_Msk              /*!< WKUP1 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV2_Pos      (17U)
+#define PWR_PRIVCFGR_WKUPPRIV2_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos)   /*!< 0x00020000 */
+#define PWR_PRIVCFGR_WKUPPRIV2          PWR_PRIVCFGR_WKUPPRIV2_Msk              /*!< WKUP2 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV3_Pos      (18U)
+#define PWR_PRIVCFGR_WKUPPRIV3_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos)   /*!< 0x00040000 */
+#define PWR_PRIVCFGR_WKUPPRIV3          PWR_PRIVCFGR_WKUPPRIV3_Msk              /*!< WKUP3 privileged protection */
+#define PWR_PRIVCFGR_WKUPPRIV4_Pos      (19U)
+#define PWR_PRIVCFGR_WKUPPRIV4_Msk      (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos)   /*!< 0x00080000 */
+#define PWR_PRIVCFGR_WKUPPRIV4          PWR_PRIVCFGR_WKUPPRIV4_Msk              /*!< WKUP4 privileged protection */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                       RAMs configuration controller                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RAMCFG_CR register  ******************/
+#define RAMCFG_CR_ECCE_Pos              (0U)
+#define RAMCFG_CR_ECCE_Msk              (0x1UL << RAMCFG_CR_ECCE_Pos)          /*!< 0x00000001 */
+#define RAMCFG_CR_ECCE                  RAMCFG_CR_ECCE_Msk                     /*!< ECC Enable */
+#define RAMCFG_CR_ALE_Pos               (4U)
+#define RAMCFG_CR_ALE_Msk               (0x1UL << RAMCFG_CR_ALE_Pos)           /*!< 0x00000010 */
+#define RAMCFG_CR_ALE                   RAMCFG_CR_ALE_Msk                      /*!< Address Latching Enable */
+#define RAMCFG_CR_SRAMER_Pos            (8U)
+#define RAMCFG_CR_SRAMER_Msk            (0x1UL << RAMCFG_CR_SRAMER_Pos)        /*!< 0x00000100 */
+#define RAMCFG_CR_SRAMER                RAMCFG_CR_SRAMER_Msk                   /*!< Start Erase */
+#define RAMCFG_CR_SRAMHWERDIS_Pos       (12U)
+#define RAMCFG_CR_SRAMHWERDIS_Msk       (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos)   /*!< 0x00001000 */
+#define RAMCFG_CR_SRAMHWERDIS           RAMCFG_CR_SRAMHWERDIS_Msk              /*!< SRAM hardware erase disable */
+#define RAMCFG_CR_ITCMCFG_Pos           (16U)
+#define RAMCFG_CR_ITCMCFG_Msk           (0x3UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00030000 */
+#define RAMCFG_CR_ITCMCFG               RAMCFG_CR_ITCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+#define RAMCFG_CR_ITCMCFG_0             (0x1UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00010000 */
+#define RAMCFG_CR_ITCMCFG_1             (0x2UL << RAMCFG_CR_ITCMCFG_Pos)       /*!< 0x00020000 */
+#define RAMCFG_CR_SRAMSD_Pos            (20U)
+#define RAMCFG_CR_SRAMSD_Msk            (0x1UL << RAMCFG_CR_SRAMSD_Pos)        /*!< 0x00100000 */
+#define RAMCFG_CR_SRAMSD                RAMCFG_CR_SRAMSD_Msk                   /*!< Shutdown AXISRAMx */
+#define RAMCFG_CR_DTCMCFG_Pos           (24U)
+#define RAMCFG_CR_DTCMCFG_Msk           (0x1UL << RAMCFG_CR_DTCMCFG_Pos)       /*!< 0x01000000 */
+#define RAMCFG_CR_DTCMCFG               RAMCFG_CR_DTCMCFG_Msk                  /*!< Configuration of the FLEXMEM D-TCM extension */
+
+/*******************  Bit definition for RAMCFG_IER register  *****************/
+#define RAMCFG_IER_SEIE_Pos             (0U)
+#define RAMCFG_IER_SEIE_Msk             (0x1UL << RAMCFG_IER_SEIE_Pos)         /*!< 0x00000001 */
+#define RAMCFG_IER_SEIE                 RAMCFG_IER_SEIE_Msk                    /*!< Single Error Interrupt Enable */
+#define RAMCFG_IER_DEIE_Pos             (1U)
+#define RAMCFG_IER_DEIE_Msk             (0x1UL << RAMCFG_IER_DEIE_Pos)         /*!< 0x00000002 */
+#define RAMCFG_IER_DEIE                 RAMCFG_IER_DEIE_Msk                    /*!< Double Error Interrupt Enable */
+
+/*******************  Bit definition for RAMCFG_ISR register  *****************/
+#define RAMCFG_ISR_SEDC_Pos             (0U)
+#define RAMCFG_ISR_SEDC_Msk             (0x1UL << RAMCFG_ISR_SEDC_Pos)         /*!< 0x00000001 */
+#define RAMCFG_ISR_SEDC                 RAMCFG_ISR_SEDC_Msk                    /*!< Single Error Detected and Corrected flag */
+#define RAMCFG_ISR_DED_Pos              (1U)
+#define RAMCFG_ISR_DED_Msk              (0x1UL << RAMCFG_ISR_DED_Pos)          /*!< 0x00000002 */
+#define RAMCFG_ISR_DED                  RAMCFG_ISR_DED_Msk                     /*!< Double Error Detected flag */
+#define RAMCFG_ISR_SRAMBUSY_Pos         (8U)
+#define RAMCFG_ISR_SRAMBUSY_Msk         (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)     /*!< 0x00000100 */
+#define RAMCFG_ISR_SRAMBUSY             RAMCFG_ISR_SRAMBUSY_Msk                /*!< SRAM busy flag */
+
+/*******************  Bit definition for RAMCFG_ESEAR register  ****************/
+#define RAMCFG_ESEAR_ESEA_Pos           (0U)
+#define RAMCFG_ESEAR_ESEA_Msk           (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_ESEAR_ESEA               RAMCFG_ESEAR_ESEA_Msk                  /*!< ECC Single Error Address */
+
+/*******************  Bit definition for RAMCFG_EDEAR register  ****************/
+#define RAMCFG_EDEAR_EDEA_Pos           (0U)
+#define RAMCFG_EDEAR_EDEA_Msk           (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos)     /*!< 0x000007FF */
+#define RAMCFG_EDEAR_EDEA               RAMCFG_EDEAR_EDEA_Msk                  /*!< ECC Double Error Address */
+
+/*******************  Bit definition for RAMCFG_ICR register  *****************/
+#define RAMCFG_ICR_CSEDC_Pos            (0U)
+#define RAMCFG_ICR_CSEDC_Msk            (0x1UL << RAMCFG_ICR_CSEDC_Pos)        /*!< 0x00000001 */
+#define RAMCFG_ICR_CSEDC                RAMCFG_ICR_CSEDC_Msk                   /*!< Clear ECC Single Error Detected and Corrected Flag */
+#define RAMCFG_ICR_CDED_Pos             (1U)
+#define RAMCFG_ICR_CDED_Msk             (0x1UL << RAMCFG_ICR_CDED_Pos)         /*!< 0x00000002 */
+#define RAMCFG_ICR_CDED                 RAMCFG_ICR_CDED_Msk                    /*!< Clear ECC Double Error Detected Flag*/
+
+/*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
+#define RAMCFG_ECCKEYR_ECCKEY_Pos       (0U)
+#define RAMCFG_ECCKEYR_ECCKEY_Msk       (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)  /*!< 0x000000FF */
+#define RAMCFG_ECCKEYR_ECCKEY           RAMCFG_ECCKEYR_ECCKEY_Msk              /*!< ECC Write Protection Key */
+
+/*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
+#define RAMCFG_ERKEYR_ERASEKEY_Pos      (0U)
+#define RAMCFG_ERKEYR_ERASEKEY_Msk      (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */
+#define RAMCFG_ERKEYR_ERASEKEY          RAMCFG_ERKEYR_ERASEKEY_Msk             /*!< Erase Write Protection Key */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (RCC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_LSION_Pos                        (0U)
+#define RCC_CR_LSION_Msk                        (0x1UL << RCC_CR_LSION_Pos)           /*!< 0x00000001 */
+#define RCC_CR_LSION                            RCC_CR_LSION_Msk                     /*!< LSI oscillator enable */
+#define RCC_CR_LSEON_Pos                        (1U)
+#define RCC_CR_LSEON_Msk                        (0x1UL << RCC_CR_LSEON_Pos)           /*!< 0x00000002 */
+#define RCC_CR_LSEON                            RCC_CR_LSEON_Msk                     /*!< LSE oscillator enable */
+#define RCC_CR_MSION_Pos                        (2U)
+#define RCC_CR_MSION_Msk                        (0x1UL << RCC_CR_MSION_Pos)           /*!< 0x00000004 */
+#define RCC_CR_MSION                            RCC_CR_MSION_Msk                     /*!< MSI oscillator enable */
+#define RCC_CR_HSION_Pos                        (3U)
+#define RCC_CR_HSION_Msk                        (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000008 */
+#define RCC_CR_HSION                            RCC_CR_HSION_Msk                     /*!< HSI oscillator enable */
+#define RCC_CR_HSEON_Pos                        (4U)
+#define RCC_CR_HSEON_Msk                        (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00000010 */
+#define RCC_CR_HSEON                            RCC_CR_HSEON_Msk                     /*!< HSE oscillator enable */
+#define RCC_CR_PLL1ON_Pos                       (8U)
+#define RCC_CR_PLL1ON_Msk                       (0x1UL << RCC_CR_PLL1ON_Pos)          /*!< 0x00000100 */
+#define RCC_CR_PLL1ON                           RCC_CR_PLL1ON_Msk                    /*!< PLL1 enable */
+#define RCC_CR_PLL2ON_Pos                       (9U)
+#define RCC_CR_PLL2ON_Msk                       (0x1UL << RCC_CR_PLL2ON_Pos)          /*!< 0x00000200 */
+#define RCC_CR_PLL2ON                           RCC_CR_PLL2ON_Msk                    /*!< PLL2 enable */
+#define RCC_CR_PLL3ON_Pos                       (10U)
+#define RCC_CR_PLL3ON_Msk                       (0x1UL << RCC_CR_PLL3ON_Pos)          /*!< 0x00000400 */
+#define RCC_CR_PLL3ON                           RCC_CR_PLL3ON_Msk                    /*!< PLL3 enable */
+#define RCC_CR_PLL4ON_Pos                       (11U)
+#define RCC_CR_PLL4ON_Msk                       (0x1UL << RCC_CR_PLL4ON_Pos)          /*!< 0x00000800 */
+#define RCC_CR_PLL4ON                           RCC_CR_PLL4ON_Msk                    /*!< PLL4 enable */
+
+/********************  Bit definition for RCC_SR register  ********************/
+#define RCC_SR_LSIRDY_Pos                       (0U)
+#define RCC_SR_LSIRDY_Msk                       (0x1UL << RCC_SR_LSIRDY_Pos)          /*!< 0x00000001 */
+#define RCC_SR_LSIRDY                           RCC_SR_LSIRDY_Msk                    /*!< LSI clock ready flag */
+#define RCC_SR_LSERDY_Pos                       (1U)
+#define RCC_SR_LSERDY_Msk                       (0x1UL << RCC_SR_LSERDY_Pos)          /*!< 0x00000002 */
+#define RCC_SR_LSERDY                           RCC_SR_LSERDY_Msk                    /*!< LSE clock ready flag */
+#define RCC_SR_MSIRDY_Pos                       (2U)
+#define RCC_SR_MSIRDY_Msk                       (0x1UL << RCC_SR_MSIRDY_Pos)          /*!< 0x00000004 */
+#define RCC_SR_MSIRDY                           RCC_SR_MSIRDY_Msk                    /*!< MSI clock ready flag */
+#define RCC_SR_HSIRDY_Pos                       (3U)
+#define RCC_SR_HSIRDY_Msk                       (0x1UL << RCC_SR_HSIRDY_Pos)          /*!< 0x00000008 */
+#define RCC_SR_HSIRDY                           RCC_SR_HSIRDY_Msk                    /*!< HSI clock ready flag */
+#define RCC_SR_HSERDY_Pos                       (4U)
+#define RCC_SR_HSERDY_Msk                       (0x1UL << RCC_SR_HSERDY_Pos)          /*!< 0x00000010 */
+#define RCC_SR_HSERDY                           RCC_SR_HSERDY_Msk                    /*!< HSE clock ready flag */
+#define RCC_SR_PLL1RDY_Pos                      (8U)
+#define RCC_SR_PLL1RDY_Msk                      (0x1UL << RCC_SR_PLL1RDY_Pos)         /*!< 0x00000100 */
+#define RCC_SR_PLL1RDY                          RCC_SR_PLL1RDY_Msk                   /*!< PLL1 clock ready flag */
+#define RCC_SR_PLL2RDY_Pos                      (9U)
+#define RCC_SR_PLL2RDY_Msk                      (0x1UL << RCC_SR_PLL2RDY_Pos)         /*!< 0x00000200 */
+#define RCC_SR_PLL2RDY                          RCC_SR_PLL2RDY_Msk                   /*!< PLL2 clock ready flag */
+#define RCC_SR_PLL3RDY_Pos                      (10U)
+#define RCC_SR_PLL3RDY_Msk                      (0x1UL << RCC_SR_PLL3RDY_Pos)         /*!< 0x00000400 */
+#define RCC_SR_PLL3RDY                          RCC_SR_PLL3RDY_Msk                   /*!< PLL3 clock ready flag */
+#define RCC_SR_PLL4RDY_Pos                      (11U)
+#define RCC_SR_PLL4RDY_Msk                      (0x1UL << RCC_SR_PLL4RDY_Pos)         /*!< 0x00000800 */
+#define RCC_SR_PLL4RDY                          RCC_SR_PLL4RDY_Msk                   /*!< PLL4 clock ready flag */
+
+/******************  Bit definition for RCC_STOPCR register  ******************/
+#define RCC_STOPCR_MSISTOPEN_Pos                (0U)
+#define RCC_STOPCR_MSISTOPEN_Msk                (0x1UL << RCC_STOPCR_MSISTOPEN_Pos)   /*!< 0x00000001 */
+#define RCC_STOPCR_MSISTOPEN                    RCC_STOPCR_MSISTOPEN_Msk             /*!< MSI oscillator enable */
+#define RCC_STOPCR_HSISTOPEN_Pos                (1U)
+#define RCC_STOPCR_HSISTOPEN_Msk                (0x1UL << RCC_STOPCR_HSISTOPEN_Pos)   /*!< 0x00000002 */
+#define RCC_STOPCR_HSISTOPEN                    RCC_STOPCR_HSISTOPEN_Msk             /*!< HSI oscillator enable */
+
+/******************  Bit definition for RCC_CFGR1 register  *******************/
+#define RCC_CFGR1_STOPWUCK_Pos                  (0U)
+#define RCC_CFGR1_STOPWUCK_Msk                  (0x1UL << RCC_CFGR1_STOPWUCK_Pos)     /*!< 0x00000001 */
+#define RCC_CFGR1_STOPWUCK                      RCC_CFGR1_STOPWUCK_Msk               /*!< System clock selection after a wake up from system stop */
+#define RCC_CFGR1_CPUSW_Pos                     (16U)
+#define RCC_CFGR1_CPUSW_Msk                     (0x3UL << RCC_CFGR1_CPUSW_Pos)        /*!< 0x00030000 */
+#define RCC_CFGR1_CPUSW                         RCC_CFGR1_CPUSW_Msk                  /*!< CPU clock switch selection */
+#define RCC_CFGR1_CPUSW_0                       (0x1UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR1_CPUSW_1                       (0x2UL << RCC_CFGR1_CPUSW_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR1_CPUSWS_Pos                    (20U)
+#define RCC_CFGR1_CPUSWS_Msk                    (0x3UL << RCC_CFGR1_CPUSWS_Pos)       /*!< 0x00300000 */
+#define RCC_CFGR1_CPUSWS                        RCC_CFGR1_CPUSWS_Msk                 /*!< CPU clock switch status */
+#define RCC_CFGR1_CPUSWS_0                      (0x1UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00100000 */
+#define RCC_CFGR1_CPUSWS_1                      (0x2UL << RCC_CFGR1_CPUSWS_Pos)      /*!< 0x00200000 */
+#define RCC_CFGR1_SYSSW_Pos                     (24U)
+#define RCC_CFGR1_SYSSW_Msk                     (0x3UL << RCC_CFGR1_SYSSW_Pos)        /*!< 0x03000000 */
+#define RCC_CFGR1_SYSSW                         RCC_CFGR1_SYSSW_Msk                  /*!< System clock switch selection */
+#define RCC_CFGR1_SYSSW_0                       (0x1UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x01000000 */
+#define RCC_CFGR1_SYSSW_1                       (0x2UL << RCC_CFGR1_SYSSW_Pos)       /*!< 0x02000000 */
+#define RCC_CFGR1_SYSSWS_Pos                    (28U)
+#define RCC_CFGR1_SYSSWS_Msk                    (0x3UL << RCC_CFGR1_SYSSWS_Pos)       /*!< 0x30000000 */
+#define RCC_CFGR1_SYSSWS                        RCC_CFGR1_SYSSWS_Msk                 /*!< System clock switch status */
+#define RCC_CFGR1_SYSSWS_0                      (0x1UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR1_SYSSWS_1                      (0x2UL << RCC_CFGR1_SYSSWS_Pos)      /*!< 0x20000000 */
+
+/******************  Bit definition for RCC_CFGR2 register  *******************/
+#define RCC_CFGR2_PPRE1_Pos                     (0U)
+#define RCC_CFGR2_PPRE1_Msk                     (0x7UL << RCC_CFGR2_PPRE1_Pos)        /*!< 0x00000007 */
+#define RCC_CFGR2_PPRE1                         RCC_CFGR2_PPRE1_Msk                  /*!< CPU domain APB1 prescaler */
+#define RCC_CFGR2_PPRE1_0                       (0x1UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000001 */
+#define RCC_CFGR2_PPRE1_1                       (0x2UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000002 */
+#define RCC_CFGR2_PPRE1_2                       (0x4UL << RCC_CFGR2_PPRE1_Pos)       /*!< 0x00000004 */
+#define RCC_CFGR2_PPRE2_Pos                     (4U)
+#define RCC_CFGR2_PPRE2_Msk                     (0x7UL << RCC_CFGR2_PPRE2_Pos)        /*!< 0x00000070 */
+#define RCC_CFGR2_PPRE2                         RCC_CFGR2_PPRE2_Msk                  /*!< CPU domain APB2 prescaler */
+#define RCC_CFGR2_PPRE2_0                       (0x1UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR2_PPRE2_1                       (0x2UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR2_PPRE2_2                       (0x4UL << RCC_CFGR2_PPRE2_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR2_PPRE4_Pos                     (12U)
+#define RCC_CFGR2_PPRE4_Msk                     (0x7UL << RCC_CFGR2_PPRE4_Pos)        /*!< 0x00007000 */
+#define RCC_CFGR2_PPRE4                         RCC_CFGR2_PPRE4_Msk                  /*!< CPU domain APB4 prescaler */
+#define RCC_CFGR2_PPRE4_0                       (0x1UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR2_PPRE4_1                       (0x2UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00002000 */
+#define RCC_CFGR2_PPRE4_2                       (0x4UL << RCC_CFGR2_PPRE4_Pos)       /*!< 0x00004000 */
+#define RCC_CFGR2_PPRE5_Pos                     (16U)
+#define RCC_CFGR2_PPRE5_Msk                     (0x7UL << RCC_CFGR2_PPRE5_Pos)        /*!< 0x00070000 */
+#define RCC_CFGR2_PPRE5                         RCC_CFGR2_PPRE5_Msk                  /*!< CPU domain APB5 prescaler */
+#define RCC_CFGR2_PPRE5_0                       (0x1UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00010000 */
+#define RCC_CFGR2_PPRE5_1                       (0x2UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00020000 */
+#define RCC_CFGR2_PPRE5_2                       (0x4UL << RCC_CFGR2_PPRE5_Pos)       /*!< 0x00040000 */
+#define RCC_CFGR2_HPRE_Pos                      (20U)
+#define RCC_CFGR2_HPRE_Msk                      (0x7UL << RCC_CFGR2_HPRE_Pos)         /*!< 0x00700000 */
+#define RCC_CFGR2_HPRE                          RCC_CFGR2_HPRE_Msk                   /*!< AHB clock prescaler */
+#define RCC_CFGR2_HPRE_0                        (0x1UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00100000 */
+#define RCC_CFGR2_HPRE_1                        (0x2UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00200000 */
+#define RCC_CFGR2_HPRE_2                        (0x4UL << RCC_CFGR2_HPRE_Pos)        /*!< 0x00400000 */
+#define RCC_CFGR2_TIMPRE_Pos                    (24U)
+#define RCC_CFGR2_TIMPRE_Msk                    (0x3UL << RCC_CFGR2_TIMPRE_Pos)       /*!< 0x03000000 */
+#define RCC_CFGR2_TIMPRE                        RCC_CFGR2_TIMPRE_Msk                 /*!< Timer clock prescaler selection */
+#define RCC_CFGR2_TIMPRE_0                      (0x1UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR2_TIMPRE_1                      (0x2UL << RCC_CFGR2_TIMPRE_Pos)      /*!< 0x02000000 */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define RCC_BDCR_VSWRST_Pos                     (31U)
+#define RCC_BDCR_VSWRST_Msk                     (0x1UL << RCC_BDCR_VSWRST_Pos)       /*!< 0x80000000 */
+#define RCC_BDCR_VSWRST                         RCC_BDCR_VSWRST_Msk                  /*!< Vswitch (VSW) domain software reset */
+
+/******************  Bit definition for RCC_HWRSR register  *******************/
+#define RCC_HWRSR_RMVF_Pos                      (16U)
+#define RCC_HWRSR_RMVF_Msk                      (0x1UL << RCC_HWRSR_RMVF_Pos)         /*!< 0x00010000 */
+#define RCC_HWRSR_RMVF                          RCC_HWRSR_RMVF_Msk                   /*!< Remove reset flag */
+#define RCC_HWRSR_LCKRSTF_Pos                   (17U)
+#define RCC_HWRSR_LCKRSTF_Msk                   (0x1UL << RCC_HWRSR_LCKRSTF_Pos)      /*!< 0x00020000 */
+#define RCC_HWRSR_LCKRSTF                       RCC_HWRSR_LCKRSTF_Msk                /*!< CPU lockup reset flag */
+#define RCC_HWRSR_BORRSTF_Pos                   (21U)
+#define RCC_HWRSR_BORRSTF_Msk                   (0x1UL << RCC_HWRSR_BORRSTF_Pos)      /*!< 0x00200000 */
+#define RCC_HWRSR_BORRSTF                       RCC_HWRSR_BORRSTF_Msk                /*!< BOR reset flag */
+#define RCC_HWRSR_PINRSTF_Pos                   (22U)
+#define RCC_HWRSR_PINRSTF_Msk                   (0x1UL << RCC_HWRSR_PINRSTF_Pos)      /*!< 0x00400000 */
+#define RCC_HWRSR_PINRSTF                       RCC_HWRSR_PINRSTF_Msk                /*!< Pin reset flag (NRST)  */
+#define RCC_HWRSR_PORRSTF_Pos                   (23U)
+#define RCC_HWRSR_PORRSTF_Msk                   (0x1UL << RCC_HWRSR_PORRSTF_Pos)      /*!< 0x00800000 */
+#define RCC_HWRSR_PORRSTF                       RCC_HWRSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
+#define RCC_HWRSR_SFTRSTF_Pos                   (24U)
+#define RCC_HWRSR_SFTRSTF_Msk                   (0x1UL << RCC_HWRSR_SFTRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_HWRSR_SFTRSTF                       RCC_HWRSR_SFTRSTF_Msk                /*!< Software system reset flag  */
+#define RCC_HWRSR_IWDGRSTF_Pos                  (26U)
+#define RCC_HWRSR_IWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_IWDGRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_HWRSR_IWDGRSTF                      RCC_HWRSR_IWDGRSTF_Msk               /*!< Independent watchdog reset flag */
+#define RCC_HWRSR_WWDGRSTF_Pos                  (28U)
+#define RCC_HWRSR_WWDGRSTF_Msk                  (0x1UL << RCC_HWRSR_WWDGRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_HWRSR_WWDGRSTF                      RCC_HWRSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
+#define RCC_HWRSR_LPWRRSTF_Pos                  (30U)
+#define RCC_HWRSR_LPWRRSTF_Msk                  (0x1UL << RCC_HWRSR_LPWRRSTF_Pos)     /*!< 0x40000000 */
+#define RCC_HWRSR_LPWRRSTF                      RCC_HWRSR_LPWRRSTF_Msk               /*!< Illegal Stop or Standby flag */
+
+/*******************  Bit definition for RCC_RSR register  ********************/
+#define RCC_RSR_RMVF_Pos                        (16U)
+#define RCC_RSR_RMVF_Msk                        (0x1UL << RCC_RSR_RMVF_Pos)           /*!< 0x00010000 */
+#define RCC_RSR_RMVF                            RCC_RSR_RMVF_Msk                     /*!< Remove reset flag */
+#define RCC_RSR_LCKRSTF_Pos                     (17U)
+#define RCC_RSR_LCKRSTF_Msk                     (0x1UL << RCC_RSR_LCKRSTF_Pos)        /*!< 0x00020000 */
+#define RCC_RSR_LCKRSTF                         RCC_RSR_LCKRSTF_Msk                  /*!< CPU lockup reset flag */
+#define RCC_RSR_BORRSTF_Pos                     (21U)
+#define RCC_RSR_BORRSTF_Msk                     (0x1UL << RCC_RSR_BORRSTF_Pos)        /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                         RCC_RSR_BORRSTF_Msk                  /*!< BOR reset flag */
+#define RCC_RSR_PINRSTF_Pos                     (22U)
+#define RCC_RSR_PINRSTF_Msk                     (0x1UL << RCC_RSR_PINRSTF_Pos)        /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                         RCC_RSR_PINRSTF_Msk                  /*!< Pin reset flag (NRST)  */
+#define RCC_RSR_PORRSTF_Pos                     (23U)
+#define RCC_RSR_PORRSTF_Msk                     (0x1UL << RCC_RSR_PORRSTF_Pos)        /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                         RCC_RSR_PORRSTF_Msk                  /*!< POR/PDR reset flag */
+#define RCC_RSR_SFTRSTF_Pos                     (24U)
+#define RCC_RSR_SFTRSTF_Msk                     (0x1UL << RCC_RSR_SFTRSTF_Pos)        /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                         RCC_RSR_SFTRSTF_Msk                  /*!< Software system reset flag  */
+#define RCC_RSR_IWDGRSTF_Pos                    (26U)
+#define RCC_RSR_IWDGRSTF_Msk                    (0x1UL << RCC_RSR_IWDGRSTF_Pos)       /*!< 0x04000000 */
+#define RCC_RSR_IWDGRSTF                        RCC_RSR_IWDGRSTF_Msk                 /*!< Independent watchdog reset flag */
+#define RCC_RSR_WWDGRSTF_Pos                    (28U)
+#define RCC_RSR_WWDGRSTF_Msk                    (0x1UL << RCC_RSR_WWDGRSTF_Pos)       /*!< 0x10000000 */
+#define RCC_RSR_WWDGRSTF                        RCC_RSR_WWDGRSTF_Msk                 /*!< Window watchdog reset flag */
+#define RCC_RSR_LPWRRSTF_Pos                    (30U)
+#define RCC_RSR_LPWRRSTF_Msk                    (0x1UL << RCC_RSR_LPWRRSTF_Pos)       /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                        RCC_RSR_LPWRRSTF_Msk                 /*!< Illegal Stop or Standby flag */
+
+/*****************  Bit definition for RCC_LSECFGR register  ******************/
+#define RCC_LSECFGR_LSECSSON_Pos                (7U)
+#define RCC_LSECFGR_LSECSSON_Msk                (0x1UL << RCC_LSECFGR_LSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_LSECFGR_LSECSSON                    RCC_LSECFGR_LSECSSON_Msk             /*!< LSE clock security system (CSS) enable */
+#define RCC_LSECFGR_LSECSSRA_Pos                (8U)
+#define RCC_LSECFGR_LSECSSRA_Msk                (0x1UL << RCC_LSECFGR_LSECSSRA_Pos)   /*!< 0x00000100 */
+#define RCC_LSECFGR_LSECSSRA                    RCC_LSECFGR_LSECSSRA_Msk             /*!< LSE clock security system (CSS) rearm function */
+#define RCC_LSECFGR_LSECSSD_Pos                 (9U)
+#define RCC_LSECFGR_LSECSSD_Msk                 (0x1UL << RCC_LSECFGR_LSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_LSECFGR_LSECSSD                     RCC_LSECFGR_LSECSSD_Msk              /*!< LSE clock security system (CSS) failure detection */
+#define RCC_LSECFGR_LSEBYP_Pos                  (15U)
+#define RCC_LSECFGR_LSEBYP_Msk                  (0x1UL << RCC_LSECFGR_LSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_LSECFGR_LSEBYP                      RCC_LSECFGR_LSEBYP_Msk               /*!< LSE clock bypass */
+#define RCC_LSECFGR_LSEEXT_Pos                  (16U)
+#define RCC_LSECFGR_LSEEXT_Msk                  (0x1UL << RCC_LSECFGR_LSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_LSECFGR_LSEEXT                      RCC_LSECFGR_LSEEXT_Msk               /*!< LSE clock type in bypass mode */
+#define RCC_LSECFGR_LSEGFON_Pos                 (17U)
+#define RCC_LSECFGR_LSEGFON_Msk                 (0x1UL << RCC_LSECFGR_LSEGFON_Pos)    /*!< 0x00020000 */
+#define RCC_LSECFGR_LSEGFON                     RCC_LSECFGR_LSEGFON_Msk              /*!< LSE clock glitch filter enable */
+#define RCC_LSECFGR_LSEDRV_Pos                  (18U)
+#define RCC_LSECFGR_LSEDRV_Msk                  (0x3UL << RCC_LSECFGR_LSEDRV_Pos)     /*!< 0x000C0000 */
+#define RCC_LSECFGR_LSEDRV                      RCC_LSECFGR_LSEDRV_Msk               /*!< LSE oscillator driving capability */
+#define RCC_LSECFGR_LSEDRV_0                    (0x1UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00040000 */
+#define RCC_LSECFGR_LSEDRV_1                    (0x2UL << RCC_LSECFGR_LSEDRV_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for RCC_MSICFGR register  ******************/
+#define RCC_MSICFGR_MSIFREQSEL_Pos              (9U)
+#define RCC_MSICFGR_MSIFREQSEL_Msk              (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */
+#define RCC_MSICFGR_MSIFREQSEL                  RCC_MSICFGR_MSIFREQSEL_Msk           /*!< MSI oscillator frequency selection */
+#define RCC_MSICFGR_MSITRIM_Pos                 (16U)
+#define RCC_MSICFGR_MSITRIM_Msk                 (0x1FUL << RCC_MSICFGR_MSITRIM_Pos)   /*!< 0x001F0000 */
+#define RCC_MSICFGR_MSITRIM                     RCC_MSICFGR_MSITRIM_Msk              /*!< MSI clock trimming */
+#define RCC_MSICFGR_MSICAL_Pos                  (23U)
+#define RCC_MSICFGR_MSICAL_Msk                  (0xFFUL << RCC_MSICFGR_MSICAL_Pos)    /*!< 0x7F800000 */
+#define RCC_MSICFGR_MSICAL                      RCC_MSICFGR_MSICAL_Msk               /*!< MSI clock calibration */
+
+/*****************  Bit definition for RCC_HSICFGR register  ******************/
+#define RCC_HSICFGR_HSIDIV_Pos                  (7U)
+#define RCC_HSICFGR_HSIDIV_Msk                  (0x3UL << RCC_HSICFGR_HSIDIV_Pos)     /*!< 0x00000180 */
+#define RCC_HSICFGR_HSIDIV                      RCC_HSICFGR_HSIDIV_Msk               /*!< HSI clock divider */
+#define RCC_HSICFGR_HSIDIV_0                    (0x1UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000080 */
+#define RCC_HSICFGR_HSIDIV_1                    (0x2UL << RCC_HSICFGR_HSIDIV_Pos)    /*!< 0x00000100 */
+#define RCC_HSICFGR_HSITRIM_Pos                 (16U)
+#define RCC_HSICFGR_HSITRIM_Msk                 (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)   /*!< 0x007F0000 */
+#define RCC_HSICFGR_HSITRIM                     RCC_HSICFGR_HSITRIM_Msk              /*!< HSI clock trimming */
+#define RCC_HSICFGR_HSICAL_Pos                  (23U)
+#define RCC_HSICFGR_HSICAL_Msk                  (0x1FFUL << RCC_HSICFGR_HSICAL_Pos)   /*!< 0xFF800000 */
+#define RCC_HSICFGR_HSICAL                      RCC_HSICFGR_HSICAL_Msk               /*!< HSI clock calibration */
+
+/******************  Bit definition for RCC_HSIMCR register  ******************/
+#define RCC_HSIMCR_HSIREF_Pos                   (0U)
+#define RCC_HSIMCR_HSIREF_Msk                   (0x7FFUL << RCC_HSIMCR_HSIREF_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMCR_HSIREF                       RCC_HSIMCR_HSIREF_Msk                /*!< HSI clock-cycle counter reference value */
+#define RCC_HSIMCR_HSIDEV_Pos                   (16U)
+#define RCC_HSIMCR_HSIDEV_Msk                   (0x3FUL << RCC_HSIMCR_HSIDEV_Pos)     /*!< 0x003F0000 */
+#define RCC_HSIMCR_HSIDEV                       RCC_HSIMCR_HSIDEV_Msk                /*!< HSI clock count deviation value */
+#define RCC_HSIMCR_HSIMONEN_Pos                 (31U)
+#define RCC_HSIMCR_HSIMONEN_Msk                 (0x1UL << RCC_HSIMCR_HSIMONEN_Pos)    /*!< 0x80000000 */
+#define RCC_HSIMCR_HSIMONEN                     RCC_HSIMCR_HSIMONEN_Msk              /*!< HSI clock period monitor enable */
+
+/******************  Bit definition for RCC_HSIMSR register  ******************/
+#define RCC_HSIMSR_HSIVAL_Pos                   (0U)
+#define RCC_HSIMSR_HSIVAL_Msk                   (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos)    /*!< 0x000007FF */
+#define RCC_HSIMSR_HSIVAL                       RCC_HSIMSR_HSIVAL_Msk                /*!< HSI clock-cycle counter measured value */
+
+/*****************  Bit definition for RCC_HSECFGR register  ******************/
+#define RCC_HSECFGR_HSEDIV2SEL_Pos              (6U)
+#define RCC_HSECFGR_HSEDIV2SEL_Msk              (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */
+#define RCC_HSECFGR_HSEDIV2SEL                  RCC_HSECFGR_HSEDIV2SEL_Msk           /*!< HSE div2 clock source select */
+#define RCC_HSECFGR_HSECSSON_Pos                (7U)
+#define RCC_HSECFGR_HSECSSON_Msk                (0x1UL << RCC_HSECFGR_HSECSSON_Pos)   /*!< 0x00000080 */
+#define RCC_HSECFGR_HSECSSON                    RCC_HSECFGR_HSECSSON_Msk             /*!< HSE CSS enable */
+#define RCC_HSECFGR_HSECSSD_Pos                 (9U)
+#define RCC_HSECFGR_HSECSSD_Msk                 (0x1UL << RCC_HSECFGR_HSECSSD_Pos)    /*!< 0x00000200 */
+#define RCC_HSECFGR_HSECSSD                     RCC_HSECFGR_HSECSSD_Msk              /*!< HSE CSS failure detection */
+#define RCC_HSECFGR_HSECSSBYP_Pos               (10U)
+#define RCC_HSECFGR_HSECSSBYP_Msk               (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos)  /*!< 0x00000400 */
+#define RCC_HSECFGR_HSECSSBYP                   RCC_HSECFGR_HSECSSBYP_Msk            /*!< HSE CSS bypass enable */
+#define RCC_HSECFGR_HSECSSBPRE_Pos              (11U)
+#define RCC_HSECFGR_HSECSSBPRE_Msk              (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */
+#define RCC_HSECFGR_HSECSSBPRE                  RCC_HSECFGR_HSECSSBPRE_Msk           /*!< HSE CSS bypass divider */
+#define RCC_HSECFGR_HSECSSBPRE_0                (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */
+#define RCC_HSECFGR_HSECSSBPRE_1                (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */
+#define RCC_HSECFGR_HSECSSBPRE_2                (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */
+#define RCC_HSECFGR_HSECSSBPRE_3                (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */
+#define RCC_HSECFGR_HSEBYP_Pos                  (15U)
+#define RCC_HSECFGR_HSEBYP_Msk                  (0x1UL << RCC_HSECFGR_HSEBYP_Pos)     /*!< 0x00008000 */
+#define RCC_HSECFGR_HSEBYP                      RCC_HSECFGR_HSEBYP_Msk               /*!< HSE clock bypass */
+#define RCC_HSECFGR_HSEEXT_Pos                  (16U)
+#define RCC_HSECFGR_HSEEXT_Msk                  (0x1UL << RCC_HSECFGR_HSEEXT_Pos)     /*!< 0x00010000 */
+#define RCC_HSECFGR_HSEEXT                      RCC_HSECFGR_HSEEXT_Msk               /*!< HSE clock type in bypass mode */
+
+/****************  Bit definition for RCC_PLL1CFGR1 register  *****************/
+#define RCC_PLL1CFGR1_PLL1DIVN_Pos              (8U)
+#define RCC_PLL1CFGR1_PLL1DIVN_Msk              (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL1CFGR1_PLL1DIVN                  RCC_PLL1CFGR1_PLL1DIVN_Msk           /*!< PLL1 integer part for the VCO multiplication factor */
+#define RCC_PLL1CFGR1_PLL1DIVM_Pos              (20U)
+#define RCC_PLL1CFGR1_PLL1DIVM_Msk              (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL1CFGR1_PLL1DIVM                  RCC_PLL1CFGR1_PLL1DIVM_Msk           /*!< PLL1 reference input clock divide frequency ratio */
+#define RCC_PLL1CFGR1_PLL1BYP_Pos               (27U)
+#define RCC_PLL1CFGR1_PLL1BYP_Msk               (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL1CFGR1_PLL1BYP                   RCC_PLL1CFGR1_PLL1BYP_Msk            /*!< PLL1 bypass */
+#define RCC_PLL1CFGR1_PLL1SEL_Pos               (28U)
+#define RCC_PLL1CFGR1_PLL1SEL_Msk               (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL1CFGR1_PLL1SEL                   RCC_PLL1CFGR1_PLL1SEL_Msk            /*!< PLL1 source selection of the reference clock */
+#define RCC_PLL1CFGR1_PLL1SEL_0                 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_1                 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL1CFGR1_PLL1SEL_2                 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL1CFGR2 register  *****************/
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos          (0U)
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL1CFGR2_PLL1DIVNFRAC              RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk       /*!< PLL1 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL1CFGR3 register  *****************/
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos          (0U)
+#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL1CFGR3_PLL1MODSSRST              RCC_PLL1CFGR3_PLL1MODSSRST_Msk       /*!< PLL1 modulation spread spectrum reset */
+#define RCC_PLL1CFGR3_PLL1DACEN_Pos             (1U)
+#define RCC_PLL1CFGR3_PLL1DACEN_Msk             (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL1CFGR3_PLL1DACEN                 RCC_PLL1CFGR3_PLL1DACEN_Msk          /*!< PLL1 noise canceling DAC enable in fractional mode */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos          (2U)
+#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL1CFGR3_PLL1MODSSDIS              RCC_PLL1CFGR3_PLL1MODSSDIS_Msk       /*!< PLL1 modulation spread spectrum disable  */
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos           (3U)
+#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk           (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL1CFGR3_PLL1MODDSEN               RCC_PLL1CFGR3_PLL1MODDSEN_Msk        /*!< PLL1 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos          (4U)
+#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk          (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL1CFGR3_PLL1MODSPRDW              RCC_PLL1CFGR3_PLL1MODSPRDW_Msk       /*!< PLL1 modulation spread spectrum down */
+#define RCC_PLL1CFGR3_PLL1MODDIV_Pos            (8U)
+#define RCC_PLL1CFGR3_PLL1MODDIV_Msk            (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL1CFGR3_PLL1MODDIV                RCC_PLL1CFGR3_PLL1MODDIV_Msk         /*!< PLL1 modulation division frequency adjustment  */
+#define RCC_PLL1CFGR3_PLL1MODSPR_Pos            (16U)
+#define RCC_PLL1CFGR3_PLL1MODSPR_Msk            (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL1CFGR3_PLL1MODSPR                RCC_PLL1CFGR3_PLL1MODSPR_Msk         /*!< PLL1 modulation spread depth adjustment */
+#define RCC_PLL1CFGR3_PLL1PDIV2_Pos             (24U)
+#define RCC_PLL1CFGR3_PLL1PDIV2_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV2                 RCC_PLL1CFGR3_PLL1PDIV2_Msk          /*!< PLL1 VCO frequency divider level 2 */
+#define RCC_PLL1CFGR3_PLL1PDIV1_Pos             (27U)
+#define RCC_PLL1CFGR3_PLL1PDIV1_Msk             (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL1CFGR3_PLL1PDIV1                 RCC_PLL1CFGR3_PLL1PDIV1_Msk          /*!< PLL1 VCO frequency divider level 1 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos            (30U)
+#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk            (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL1CFGR3_PLL1PDIVEN                RCC_PLL1CFGR3_PLL1PDIVEN_Msk         /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL2CFGR1 register  *****************/
+#define RCC_PLL2CFGR1_PLL2DIVN_Pos              (8U)
+#define RCC_PLL2CFGR1_PLL2DIVN_Msk              (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL2CFGR1_PLL2DIVN                  RCC_PLL2CFGR1_PLL2DIVN_Msk           /*!< PLL2 integer part for the VCO multiplication factor */
+#define RCC_PLL2CFGR1_PLL2DIVM_Pos              (20U)
+#define RCC_PLL2CFGR1_PLL2DIVM_Msk              (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL2CFGR1_PLL2DIVM                  RCC_PLL2CFGR1_PLL2DIVM_Msk           /*!< PLL2 reference input clock divide frequency ratio */
+#define RCC_PLL2CFGR1_PLL2BYP_Pos               (27U)
+#define RCC_PLL2CFGR1_PLL2BYP_Msk               (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL2CFGR1_PLL2BYP                   RCC_PLL2CFGR1_PLL2BYP_Msk            /*!< PLL2 bypass */
+#define RCC_PLL2CFGR1_PLL2SEL_Pos               (28U)
+#define RCC_PLL2CFGR1_PLL2SEL_Msk               (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL2CFGR1_PLL2SEL                   RCC_PLL2CFGR1_PLL2SEL_Msk            /*!< PLL2 source selection of the reference clock */
+#define RCC_PLL2CFGR1_PLL2SEL_0                 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_1                 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL2CFGR1_PLL2SEL_2                 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL2CFGR2 register  *****************/
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos          (0U)
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL2CFGR2_PLL2DIVNFRAC              RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk       /*!< PLL2 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL2CFGR3 register  *****************/
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos          (0U)
+#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL2CFGR3_PLL2MODSSRST              RCC_PLL2CFGR3_PLL2MODSSRST_Msk       /*!< PLL2 modulation spread spectrum reset */
+#define RCC_PLL2CFGR3_PLL2DACEN_Pos             (1U)
+#define RCC_PLL2CFGR3_PLL2DACEN_Msk             (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL2CFGR3_PLL2DACEN                 RCC_PLL2CFGR3_PLL2DACEN_Msk          /*!< PLL2 noise canceling DAC enable in fractional mode */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos          (2U)
+#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL2CFGR3_PLL2MODSSDIS              RCC_PLL2CFGR3_PLL2MODSSDIS_Msk       /*!< PLL2 modulation spread spectrum disable  */
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos           (3U)
+#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk           (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL2CFGR3_PLL2MODDSEN               RCC_PLL2CFGR3_PLL2MODDSEN_Msk        /*!< PLL2 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos          (4U)
+#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk          (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL2CFGR3_PLL2MODSPRDW              RCC_PLL2CFGR3_PLL2MODSPRDW_Msk       /*!< PLL2 modulation down spread */
+#define RCC_PLL2CFGR3_PLL2MODDIV_Pos            (8U)
+#define RCC_PLL2CFGR3_PLL2MODDIV_Msk            (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL2CFGR3_PLL2MODDIV                RCC_PLL2CFGR3_PLL2MODDIV_Msk         /*!< PLL2 modulation division frequency adjustment  */
+#define RCC_PLL2CFGR3_PLL2MODSPR_Pos            (16U)
+#define RCC_PLL2CFGR3_PLL2MODSPR_Msk            (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL2CFGR3_PLL2MODSPR                RCC_PLL2CFGR3_PLL2MODSPR_Msk         /*!< PLL2 modulation spread depth adjustment */
+#define RCC_PLL2CFGR3_PLL2PDIV2_Pos             (24U)
+#define RCC_PLL2CFGR3_PLL2PDIV2_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV2                 RCC_PLL2CFGR3_PLL2PDIV2_Msk          /*!< PLL2 VCO frequency divider level 2 */
+#define RCC_PLL2CFGR3_PLL2PDIV1_Pos             (27U)
+#define RCC_PLL2CFGR3_PLL2PDIV1_Msk             (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL2CFGR3_PLL2PDIV1                 RCC_PLL2CFGR3_PLL2PDIV1_Msk          /*!< PLL2 VCO frequency divider level 1 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos            (30U)
+#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk            (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL2CFGR3_PLL2PDIVEN                RCC_PLL2CFGR3_PLL2PDIVEN_Msk         /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL3CFGR1 register  *****************/
+#define RCC_PLL3CFGR1_PLL3DIVN_Pos              (8U)
+#define RCC_PLL3CFGR1_PLL3DIVN_Msk              (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL3CFGR1_PLL3DIVN                  RCC_PLL3CFGR1_PLL3DIVN_Msk           /*!< PLL3 Integer part for the VCO multiplication factor */
+#define RCC_PLL3CFGR1_PLL3DIVM_Pos              (20U)
+#define RCC_PLL3CFGR1_PLL3DIVM_Msk              (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL3CFGR1_PLL3DIVM                  RCC_PLL3CFGR1_PLL3DIVM_Msk           /*!< PLL3 reference input clock divide frequency ratio */
+#define RCC_PLL3CFGR1_PLL3BYP_Pos               (27U)
+#define RCC_PLL3CFGR1_PLL3BYP_Msk               (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL3CFGR1_PLL3BYP                   RCC_PLL3CFGR1_PLL3BYP_Msk            /*!< PLL3 bypass */
+#define RCC_PLL3CFGR1_PLL3SEL_Pos               (28U)
+#define RCC_PLL3CFGR1_PLL3SEL_Msk               (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL3CFGR1_PLL3SEL                   RCC_PLL3CFGR1_PLL3SEL_Msk            /*!< PLL3 source selection of the reference clock */
+#define RCC_PLL3CFGR1_PLL3SEL_0                 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_1                 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL3CFGR1_PLL3SEL_2                 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL3CFGR2 register  *****************/
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos          (0U)
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL3CFGR2_PLL3DIVNFRAC              RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk       /*!< PLL3 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL3CFGR3 register  *****************/
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos          (0U)
+#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL3CFGR3_PLL3MODSSRST              RCC_PLL3CFGR3_PLL3MODSSRST_Msk       /*!< PLL3 modulation spread spectrum reset */
+#define RCC_PLL3CFGR3_PLL3DACEN_Pos             (1U)
+#define RCC_PLL3CFGR3_PLL3DACEN_Msk             (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL3CFGR3_PLL3DACEN                 RCC_PLL3CFGR3_PLL3DACEN_Msk          /*!< PLL3 noise canceling DAC enable in fractional mode */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos          (2U)
+#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL3CFGR3_PLL3MODSSDIS              RCC_PLL3CFGR3_PLL3MODSSDIS_Msk       /*!< PLL3 modulation spread spectrum disable  */
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos           (3U)
+#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk           (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL3CFGR3_PLL3MODDSEN               RCC_PLL3CFGR3_PLL3MODDSEN_Msk        /*!< PLL3 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos          (4U)
+#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk          (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL3CFGR3_PLL3MODSPRDW              RCC_PLL3CFGR3_PLL3MODSPRDW_Msk       /*!< PLL3 modulation down spread */
+#define RCC_PLL3CFGR3_PLL3MODDIV_Pos            (8U)
+#define RCC_PLL3CFGR3_PLL3MODDIV_Msk            (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL3CFGR3_PLL3MODDIV                RCC_PLL3CFGR3_PLL3MODDIV_Msk         /*!< PLL3 modulation division frequency adjustment  */
+#define RCC_PLL3CFGR3_PLL3MODSPR_Pos            (16U)
+#define RCC_PLL3CFGR3_PLL3MODSPR_Msk            (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL3CFGR3_PLL3MODSPR                RCC_PLL3CFGR3_PLL3MODSPR_Msk         /*!< PLL3 modulation spread depth adjustment */
+#define RCC_PLL3CFGR3_PLL3PDIV2_Pos             (24U)
+#define RCC_PLL3CFGR3_PLL3PDIV2_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV2                 RCC_PLL3CFGR3_PLL3PDIV2_Msk          /*!< PLL3 VCO frequency divider level 2 */
+#define RCC_PLL3CFGR3_PLL3PDIV1_Pos             (27U)
+#define RCC_PLL3CFGR3_PLL3PDIV1_Msk             (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL3CFGR3_PLL3PDIV1                 RCC_PLL3CFGR3_PLL3PDIV1_Msk          /*!< PLL3 VCO frequency divider level 1 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos            (30U)
+#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk            (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL3CFGR3_PLL3PDIVEN                RCC_PLL3CFGR3_PLL3PDIVEN_Msk         /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/****************  Bit definition for RCC_PLL4CFGR1 register  *****************/
+#define RCC_PLL4CFGR1_PLL4DIVN_Pos              (8U)
+#define RCC_PLL4CFGR1_PLL4DIVN_Msk              (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */
+#define RCC_PLL4CFGR1_PLL4DIVN                  RCC_PLL4CFGR1_PLL4DIVN_Msk           /*!< PLL4 integer part for the VCO multiplication factor */
+#define RCC_PLL4CFGR1_PLL4DIVM_Pos              (20U)
+#define RCC_PLL4CFGR1_PLL4DIVM_Msk              (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */
+#define RCC_PLL4CFGR1_PLL4DIVM                  RCC_PLL4CFGR1_PLL4DIVM_Msk           /*!< PLL4 reference input clock divide frequency ratio */
+#define RCC_PLL4CFGR1_PLL4BYP_Pos               (27U)
+#define RCC_PLL4CFGR1_PLL4BYP_Msk               (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos)  /*!< 0x08000000 */
+#define RCC_PLL4CFGR1_PLL4BYP                   RCC_PLL4CFGR1_PLL4BYP_Msk            /*!< PLL4 bypass */
+#define RCC_PLL4CFGR1_PLL4SEL_Pos               (28U)
+#define RCC_PLL4CFGR1_PLL4SEL_Msk               (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos)  /*!< 0x70000000 */
+#define RCC_PLL4CFGR1_PLL4SEL                   RCC_PLL4CFGR1_PLL4SEL_Msk            /*!< PLL4 source selection of the reference clock */
+#define RCC_PLL4CFGR1_PLL4SEL_0                 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_1                 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */
+#define RCC_PLL4CFGR1_PLL4SEL_2                 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */
+
+/****************  Bit definition for RCC_PLL4CFGR2 register  *****************/
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos          (0U)
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk          (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos)        /*!< 0x00FFFFFF */
+#define RCC_PLL4CFGR2_PLL4DIVNFRAC              RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk       /*!< PLL4 fractional part of the VCO multiplication factor */
+
+/****************  Bit definition for RCC_PLL4CFGR3 register  *****************/
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos          (0U)
+#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos)   /*!< 0x00000001 */
+#define RCC_PLL4CFGR3_PLL4MODSSRST              RCC_PLL4CFGR3_PLL4MODSSRST_Msk       /*!< PLL4 modulation spread spectrum reset */
+#define RCC_PLL4CFGR3_PLL4DACEN_Pos             (1U)
+#define RCC_PLL4CFGR3_PLL4DACEN_Msk             (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */
+#define RCC_PLL4CFGR3_PLL4DACEN                 RCC_PLL4CFGR3_PLL4DACEN_Msk          /*!< PLL4 noise canceling DAC enable in fractional mode */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos          (2U)
+#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos)   /*!< 0x00000004 */
+#define RCC_PLL4CFGR3_PLL4MODSSDIS              RCC_PLL4CFGR3_PLL4MODSSDIS_Msk       /*!< PLL4 modulation spread spectrum disable  */
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos           (3U)
+#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk           (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos)  /*!< 0x00000008 */
+#define RCC_PLL4CFGR3_PLL4MODDSEN               RCC_PLL4CFGR3_PLL4MODDSEN_Msk        /*!< PLL4 modulation spread spectrum (and fractional divide) enable */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos          (4U)
+#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk          (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos)   /*!< 0x00000010 */
+#define RCC_PLL4CFGR3_PLL4MODSPRDW              RCC_PLL4CFGR3_PLL4MODSPRDW_Msk       /*!< PLL4 modulation down spread */
+#define RCC_PLL4CFGR3_PLL4MODDIV_Pos            (8U)
+#define RCC_PLL4CFGR3_PLL4MODDIV_Msk            (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */
+#define RCC_PLL4CFGR3_PLL4MODDIV                RCC_PLL4CFGR3_PLL4MODDIV_Msk         /*!< PLL4 modulation division frequency adjustment  */
+#define RCC_PLL4CFGR3_PLL4MODSPR_Pos            (16U)
+#define RCC_PLL4CFGR3_PLL4MODSPR_Msk            (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos)  /*!< 0x001F0000 */
+#define RCC_PLL4CFGR3_PLL4MODSPR                RCC_PLL4CFGR3_PLL4MODSPR_Msk         /*!< PLL4 modulation spread depth adjustment */
+#define RCC_PLL4CFGR3_PLL4PDIV2_Pos             (24U)
+#define RCC_PLL4CFGR3_PLL4PDIV2_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV2                 RCC_PLL4CFGR3_PLL4PDIV2_Msk          /*!< PLL4 VCO frequency divider level 2 */
+#define RCC_PLL4CFGR3_PLL4PDIV1_Pos             (27U)
+#define RCC_PLL4CFGR3_PLL4PDIV1_Msk             (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */
+#define RCC_PLL4CFGR3_PLL4PDIV1                 RCC_PLL4CFGR3_PLL4PDIV1_Msk          /*!< PLL4 VCO frequency divider level 1 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos            (30U)
+#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk            (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */
+#define RCC_PLL4CFGR3_PLL4PDIVEN                RCC_PLL4CFGR3_PLL4PDIVEN_Msk         /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
+
+/*****************  Bit definition for RCC_IC1CFGR register  ******************/
+#define RCC_IC1CFGR_IC1INT_Pos                  (16U)
+#define RCC_IC1CFGR_IC1INT_Msk                  (0xFFUL << RCC_IC1CFGR_IC1INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC1CFGR_IC1INT                      RCC_IC1CFGR_IC1INT_Msk               /*!< Divider IC1 integer division factor */
+#define RCC_IC1CFGR_IC1SEL_Pos                  (28U)
+#define RCC_IC1CFGR_IC1SEL_Msk                  (0x3UL << RCC_IC1CFGR_IC1SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC1CFGR_IC1SEL                      RCC_IC1CFGR_IC1SEL_Msk               /*!< Divider IC1 source selection */
+#define RCC_IC1CFGR_IC1SEL_0                    (0x1UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC1CFGR_IC1SEL_1                    (0x2UL << RCC_IC1CFGR_IC1SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC2CFGR register  ******************/
+#define RCC_IC2CFGR_IC2INT_Pos                  (16U)
+#define RCC_IC2CFGR_IC2INT_Msk                  (0xFFUL << RCC_IC2CFGR_IC2INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC2CFGR_IC2INT                      RCC_IC2CFGR_IC2INT_Msk               /*!< Divider IC2 integer division factor */
+#define RCC_IC2CFGR_IC2SEL_Pos                  (28U)
+#define RCC_IC2CFGR_IC2SEL_Msk                  (0x3UL << RCC_IC2CFGR_IC2SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC2CFGR_IC2SEL                      RCC_IC2CFGR_IC2SEL_Msk               /*!< Divider IC2 source selection */
+#define RCC_IC2CFGR_IC2SEL_0                    (0x1UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC2CFGR_IC2SEL_1                    (0x2UL << RCC_IC2CFGR_IC2SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC3CFGR register  ******************/
+#define RCC_IC3CFGR_IC3INT_Pos                  (16U)
+#define RCC_IC3CFGR_IC3INT_Msk                  (0xFFUL << RCC_IC3CFGR_IC3INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC3CFGR_IC3INT                      RCC_IC3CFGR_IC3INT_Msk               /*!< Divider IC3 integer division factor */
+#define RCC_IC3CFGR_IC3SEL_Pos                  (28U)
+#define RCC_IC3CFGR_IC3SEL_Msk                  (0x3UL << RCC_IC3CFGR_IC3SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC3CFGR_IC3SEL                      RCC_IC3CFGR_IC3SEL_Msk               /*!< Divider IC3 source selection */
+#define RCC_IC3CFGR_IC3SEL_0                    (0x1UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC3CFGR_IC3SEL_1                    (0x2UL << RCC_IC3CFGR_IC3SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC4CFGR register  ******************/
+#define RCC_IC4CFGR_IC4INT_Pos                  (16U)
+#define RCC_IC4CFGR_IC4INT_Msk                  (0xFFUL << RCC_IC4CFGR_IC4INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC4CFGR_IC4INT                      RCC_IC4CFGR_IC4INT_Msk               /*!< Divider IC4 integer division factor */
+#define RCC_IC4CFGR_IC4SEL_Pos                  (28U)
+#define RCC_IC4CFGR_IC4SEL_Msk                  (0x3UL << RCC_IC4CFGR_IC4SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC4CFGR_IC4SEL                      RCC_IC4CFGR_IC4SEL_Msk               /*!< Divider IC4 source selection */
+#define RCC_IC4CFGR_IC4SEL_0                    (0x1UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC4CFGR_IC4SEL_1                    (0x2UL << RCC_IC4CFGR_IC4SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC5CFGR register  ******************/
+#define RCC_IC5CFGR_IC5INT_Pos                  (16U)
+#define RCC_IC5CFGR_IC5INT_Msk                  (0xFFUL << RCC_IC5CFGR_IC5INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC5CFGR_IC5INT                      RCC_IC5CFGR_IC5INT_Msk               /*!< Divider IC5 integer division factor */
+#define RCC_IC5CFGR_IC5SEL_Pos                  (28U)
+#define RCC_IC5CFGR_IC5SEL_Msk                  (0x3UL << RCC_IC5CFGR_IC5SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC5CFGR_IC5SEL                      RCC_IC5CFGR_IC5SEL_Msk               /*!< Divider IC5 source selection */
+#define RCC_IC5CFGR_IC5SEL_0                    (0x1UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC5CFGR_IC5SEL_1                    (0x2UL << RCC_IC5CFGR_IC5SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC6CFGR register  ******************/
+#define RCC_IC6CFGR_IC6INT_Pos                  (16U)
+#define RCC_IC6CFGR_IC6INT_Msk                  (0xFFUL << RCC_IC6CFGR_IC6INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC6CFGR_IC6INT                      RCC_IC6CFGR_IC6INT_Msk               /*!< Divider IC6 integer division factor */
+#define RCC_IC6CFGR_IC6SEL_Pos                  (28U)
+#define RCC_IC6CFGR_IC6SEL_Msk                  (0x3UL << RCC_IC6CFGR_IC6SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC6CFGR_IC6SEL                      RCC_IC6CFGR_IC6SEL_Msk               /*!< Divider IC6 source selection */
+#define RCC_IC6CFGR_IC6SEL_0                    (0x1UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC6CFGR_IC6SEL_1                    (0x2UL << RCC_IC6CFGR_IC6SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC7CFGR register  ******************/
+#define RCC_IC7CFGR_IC7INT_Pos                  (16U)
+#define RCC_IC7CFGR_IC7INT_Msk                  (0xFFUL << RCC_IC7CFGR_IC7INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC7CFGR_IC7INT                      RCC_IC7CFGR_IC7INT_Msk               /*!< Divider IC7 integer division factor */
+#define RCC_IC7CFGR_IC7SEL_Pos                  (28U)
+#define RCC_IC7CFGR_IC7SEL_Msk                  (0x3UL << RCC_IC7CFGR_IC7SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC7CFGR_IC7SEL                      RCC_IC7CFGR_IC7SEL_Msk               /*!< Divider IC7 source selection */
+#define RCC_IC7CFGR_IC7SEL_0                    (0x1UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC7CFGR_IC7SEL_1                    (0x2UL << RCC_IC7CFGR_IC7SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC8CFGR register  ******************/
+#define RCC_IC8CFGR_IC8INT_Pos                  (16U)
+#define RCC_IC8CFGR_IC8INT_Msk                  (0xFFUL << RCC_IC8CFGR_IC8INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC8CFGR_IC8INT                      RCC_IC8CFGR_IC8INT_Msk               /*!< Divider IC8 integer division factor */
+#define RCC_IC8CFGR_IC8SEL_Pos                  (28U)
+#define RCC_IC8CFGR_IC8SEL_Msk                  (0x3UL << RCC_IC8CFGR_IC8SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC8CFGR_IC8SEL                      RCC_IC8CFGR_IC8SEL_Msk               /*!< Divider IC8 source selection */
+#define RCC_IC8CFGR_IC8SEL_0                    (0x1UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC8CFGR_IC8SEL_1                    (0x2UL << RCC_IC8CFGR_IC8SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC9CFGR register  ******************/
+#define RCC_IC9CFGR_IC9INT_Pos                  (16U)
+#define RCC_IC9CFGR_IC9INT_Msk                  (0xFFUL << RCC_IC9CFGR_IC9INT_Pos)    /*!< 0x00FF0000 */
+#define RCC_IC9CFGR_IC9INT                      RCC_IC9CFGR_IC9INT_Msk               /*!< Divider IC9 integer division factor */
+#define RCC_IC9CFGR_IC9SEL_Pos                  (28U)
+#define RCC_IC9CFGR_IC9SEL_Msk                  (0x3UL << RCC_IC9CFGR_IC9SEL_Pos)     /*!< 0x30000000 */
+#define RCC_IC9CFGR_IC9SEL                      RCC_IC9CFGR_IC9SEL_Msk               /*!< Divider IC9 source selection */
+#define RCC_IC9CFGR_IC9SEL_0                    (0x1UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x10000000 */
+#define RCC_IC9CFGR_IC9SEL_1                    (0x2UL << RCC_IC9CFGR_IC9SEL_Pos)    /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC10CFGR register  *****************/
+#define RCC_IC10CFGR_IC10INT_Pos                (16U)
+#define RCC_IC10CFGR_IC10INT_Msk                (0xFFUL << RCC_IC10CFGR_IC10INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC10CFGR_IC10INT                    RCC_IC10CFGR_IC10INT_Msk             /*!< Divider IC10 integer division factor */
+#define RCC_IC10CFGR_IC10SEL_Pos                (28U)
+#define RCC_IC10CFGR_IC10SEL_Msk                (0x3UL << RCC_IC10CFGR_IC10SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC10CFGR_IC10SEL                    RCC_IC10CFGR_IC10SEL_Msk             /*!< Divider IC10 source selection */
+#define RCC_IC10CFGR_IC10SEL_0                  (0x1UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC10CFGR_IC10SEL_1                  (0x2UL << RCC_IC10CFGR_IC10SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC11CFGR register  *****************/
+#define RCC_IC11CFGR_IC11INT_Pos                (16U)
+#define RCC_IC11CFGR_IC11INT_Msk                (0xFFUL << RCC_IC11CFGR_IC11INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC11CFGR_IC11INT                    RCC_IC11CFGR_IC11INT_Msk             /*!< Divider IC11 integer division factor */
+#define RCC_IC11CFGR_IC11SEL_Pos                (28U)
+#define RCC_IC11CFGR_IC11SEL_Msk                (0x3UL << RCC_IC11CFGR_IC11SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC11CFGR_IC11SEL                    RCC_IC11CFGR_IC11SEL_Msk             /*!< Divider IC11 source selection */
+#define RCC_IC11CFGR_IC11SEL_0                  (0x1UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC11CFGR_IC11SEL_1                  (0x2UL << RCC_IC11CFGR_IC11SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC12CFGR register  *****************/
+#define RCC_IC12CFGR_IC12INT_Pos                (16U)
+#define RCC_IC12CFGR_IC12INT_Msk                (0xFFUL << RCC_IC12CFGR_IC12INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC12CFGR_IC12INT                    RCC_IC12CFGR_IC12INT_Msk             /*!< Divider IC12 integer division factor */
+#define RCC_IC12CFGR_IC12SEL_Pos                (28U)
+#define RCC_IC12CFGR_IC12SEL_Msk                (0x3UL << RCC_IC12CFGR_IC12SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC12CFGR_IC12SEL                    RCC_IC12CFGR_IC12SEL_Msk             /*!< Divider IC12 source selection */
+#define RCC_IC12CFGR_IC12SEL_0                  (0x1UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC12CFGR_IC12SEL_1                  (0x2UL << RCC_IC12CFGR_IC12SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC13CFGR register  *****************/
+#define RCC_IC13CFGR_IC13INT_Pos                (16U)
+#define RCC_IC13CFGR_IC13INT_Msk                (0xFFUL << RCC_IC13CFGR_IC13INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC13CFGR_IC13INT                    RCC_IC13CFGR_IC13INT_Msk             /*!< Divider IC13 integer division factor */
+#define RCC_IC13CFGR_IC13SEL_Pos                (28U)
+#define RCC_IC13CFGR_IC13SEL_Msk                (0x3UL << RCC_IC13CFGR_IC13SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC13CFGR_IC13SEL                    RCC_IC13CFGR_IC13SEL_Msk             /*!< Divider IC13 source selection */
+#define RCC_IC13CFGR_IC13SEL_0                  (0x1UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC13CFGR_IC13SEL_1                  (0x2UL << RCC_IC13CFGR_IC13SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC14CFGR register  *****************/
+#define RCC_IC14CFGR_IC14INT_Pos                (16U)
+#define RCC_IC14CFGR_IC14INT_Msk                (0xFFUL << RCC_IC14CFGR_IC14INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC14CFGR_IC14INT                    RCC_IC14CFGR_IC14INT_Msk             /*!< Divider IC14 integer division factor */
+#define RCC_IC14CFGR_IC14SEL_Pos                (28U)
+#define RCC_IC14CFGR_IC14SEL_Msk                (0x3UL << RCC_IC14CFGR_IC14SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC14CFGR_IC14SEL                    RCC_IC14CFGR_IC14SEL_Msk             /*!< Divider IC14 source selection */
+#define RCC_IC14CFGR_IC14SEL_0                  (0x1UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC14CFGR_IC14SEL_1                  (0x2UL << RCC_IC14CFGR_IC14SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC15CFGR register  *****************/
+#define RCC_IC15CFGR_IC15INT_Pos                (16U)
+#define RCC_IC15CFGR_IC15INT_Msk                (0xFFUL << RCC_IC15CFGR_IC15INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC15CFGR_IC15INT                    RCC_IC15CFGR_IC15INT_Msk             /*!< Divider IC15 integer division factor */
+#define RCC_IC15CFGR_IC15SEL_Pos                (28U)
+#define RCC_IC15CFGR_IC15SEL_Msk                (0x3UL << RCC_IC15CFGR_IC15SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC15CFGR_IC15SEL                    RCC_IC15CFGR_IC15SEL_Msk             /*!< Divider IC15 source selection */
+#define RCC_IC15CFGR_IC15SEL_0                  (0x1UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC15CFGR_IC15SEL_1                  (0x2UL << RCC_IC15CFGR_IC15SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC16CFGR register  *****************/
+#define RCC_IC16CFGR_IC16INT_Pos                (16U)
+#define RCC_IC16CFGR_IC16INT_Msk                (0xFFUL << RCC_IC16CFGR_IC16INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC16CFGR_IC16INT                    RCC_IC16CFGR_IC16INT_Msk             /*!< Divider IC16 integer division factor */
+#define RCC_IC16CFGR_IC16SEL_Pos                (28U)
+#define RCC_IC16CFGR_IC16SEL_Msk                (0x3UL << RCC_IC16CFGR_IC16SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC16CFGR_IC16SEL                    RCC_IC16CFGR_IC16SEL_Msk             /*!< Divider IC16 source selection */
+#define RCC_IC16CFGR_IC16SEL_0                  (0x1UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC16CFGR_IC16SEL_1                  (0x2UL << RCC_IC16CFGR_IC16SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC17CFGR register  *****************/
+#define RCC_IC17CFGR_IC17INT_Pos                (16U)
+#define RCC_IC17CFGR_IC17INT_Msk                (0xFFUL << RCC_IC17CFGR_IC17INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC17CFGR_IC17INT                    RCC_IC17CFGR_IC17INT_Msk             /*!< Divider IC17 integer division factor */
+#define RCC_IC17CFGR_IC17SEL_Pos                (28U)
+#define RCC_IC17CFGR_IC17SEL_Msk                (0x3UL << RCC_IC17CFGR_IC17SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC17CFGR_IC17SEL                    RCC_IC17CFGR_IC17SEL_Msk             /*!< Divider IC17 source selection */
+#define RCC_IC17CFGR_IC17SEL_0                  (0x1UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC17CFGR_IC17SEL_1                  (0x2UL << RCC_IC17CFGR_IC17SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC18CFGR register  *****************/
+#define RCC_IC18CFGR_IC18INT_Pos                (16U)
+#define RCC_IC18CFGR_IC18INT_Msk                (0xFFUL << RCC_IC18CFGR_IC18INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC18CFGR_IC18INT                    RCC_IC18CFGR_IC18INT_Msk             /*!< Divider IC18 integer division factor */
+#define RCC_IC18CFGR_IC18SEL_Pos                (28U)
+#define RCC_IC18CFGR_IC18SEL_Msk                (0x3UL << RCC_IC18CFGR_IC18SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC18CFGR_IC18SEL                    RCC_IC18CFGR_IC18SEL_Msk             /*!< Divider IC18 source selection */
+#define RCC_IC18CFGR_IC18SEL_0                  (0x1UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC18CFGR_IC18SEL_1                  (0x2UL << RCC_IC18CFGR_IC18SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC19CFGR register  *****************/
+#define RCC_IC19CFGR_IC19INT_Pos                (16U)
+#define RCC_IC19CFGR_IC19INT_Msk                (0xFFUL << RCC_IC19CFGR_IC19INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC19CFGR_IC19INT                    RCC_IC19CFGR_IC19INT_Msk             /*!< Divider IC19 integer division factor */
+#define RCC_IC19CFGR_IC19SEL_Pos                (28U)
+#define RCC_IC19CFGR_IC19SEL_Msk                (0x3UL << RCC_IC19CFGR_IC19SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC19CFGR_IC19SEL                    RCC_IC19CFGR_IC19SEL_Msk             /*!< Divider IC19 source selection */
+#define RCC_IC19CFGR_IC19SEL_0                  (0x1UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC19CFGR_IC19SEL_1                  (0x2UL << RCC_IC19CFGR_IC19SEL_Pos)  /*!< 0x20000000 */
+
+/*****************  Bit definition for RCC_IC20CFGR register  *****************/
+#define RCC_IC20CFGR_IC20INT_Pos                (16U)
+#define RCC_IC20CFGR_IC20INT_Msk                (0xFFUL << RCC_IC20CFGR_IC20INT_Pos)  /*!< 0x00FF0000 */
+#define RCC_IC20CFGR_IC20INT                    RCC_IC20CFGR_IC20INT_Msk             /*!< Divider IC20 integer division factor */
+#define RCC_IC20CFGR_IC20SEL_Pos                (28U)
+#define RCC_IC20CFGR_IC20SEL_Msk                (0x3UL << RCC_IC20CFGR_IC20SEL_Pos)   /*!< 0x30000000 */
+#define RCC_IC20CFGR_IC20SEL                    RCC_IC20CFGR_IC20SEL_Msk             /*!< Divider IC20 source selection */
+#define RCC_IC20CFGR_IC20SEL_0                  (0x1UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x10000000 */
+#define RCC_IC20CFGR_IC20SEL_1                  (0x2UL << RCC_IC20CFGR_IC20SEL_Pos)  /*!< 0x20000000 */
+
+/*******************  Bit definition for RCC_CIER register  *******************/
+#define RCC_CIER_LSIRDYIE_Pos                   (0U)
+#define RCC_CIER_LSIRDYIE_Msk                   (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                       RCC_CIER_LSIRDYIE_Msk                /*!< LSI ready interrupt enable */
+#define RCC_CIER_LSERDYIE_Pos                   (1U)
+#define RCC_CIER_LSERDYIE_Msk                   (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                       RCC_CIER_LSERDYIE_Msk                /*!< LSE ready interrupt enable */
+#define RCC_CIER_MSIRDYIE_Pos                   (2U)
+#define RCC_CIER_MSIRDYIE_Msk                   (0x1UL << RCC_CIER_MSIRDYIE_Pos)      /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                       RCC_CIER_MSIRDYIE_Msk                /*!< MSI ready interrupt enable */
+#define RCC_CIER_HSIRDYIE_Pos                   (3U)
+#define RCC_CIER_HSIRDYIE_Msk                   (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                       RCC_CIER_HSIRDYIE_Msk                /*!< HSI ready interrupt enable */
+#define RCC_CIER_HSERDYIE_Pos                   (4U)
+#define RCC_CIER_HSERDYIE_Msk                   (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                       RCC_CIER_HSERDYIE_Msk                /*!< HSE ready interrupt enable */
+#define RCC_CIER_PLL1RDYIE_Pos                  (8U)
+#define RCC_CIER_PLL1RDYIE_Msk                  (0x1UL << RCC_CIER_PLL1RDYIE_Pos)     /*!< 0x00000100 */
+#define RCC_CIER_PLL1RDYIE                      RCC_CIER_PLL1RDYIE_Msk               /*!< PLL1 ready interrupt enable */
+#define RCC_CIER_PLL2RDYIE_Pos                  (9U)
+#define RCC_CIER_PLL2RDYIE_Msk                  (0x1UL << RCC_CIER_PLL2RDYIE_Pos)     /*!< 0x00000200 */
+#define RCC_CIER_PLL2RDYIE                      RCC_CIER_PLL2RDYIE_Msk               /*!< PLL2 ready interrupt enable */
+#define RCC_CIER_PLL3RDYIE_Pos                  (10U)
+#define RCC_CIER_PLL3RDYIE_Msk                  (0x1UL << RCC_CIER_PLL3RDYIE_Pos)     /*!< 0x00000400 */
+#define RCC_CIER_PLL3RDYIE                      RCC_CIER_PLL3RDYIE_Msk               /*!< PLL3 ready interrupt enable */
+#define RCC_CIER_PLL4RDYIE_Pos                  (11U)
+#define RCC_CIER_PLL4RDYIE_Msk                  (0x1UL << RCC_CIER_PLL4RDYIE_Pos)     /*!< 0x00000800 */
+#define RCC_CIER_PLL4RDYIE                      RCC_CIER_PLL4RDYIE_Msk               /*!< PLL4 ready interrupt enable */
+#define RCC_CIER_LSECSSIE_Pos                   (16U)
+#define RCC_CIER_LSECSSIE_Msk                   (0x1UL << RCC_CIER_LSECSSIE_Pos)      /*!< 0x00010000 */
+#define RCC_CIER_LSECSSIE                       RCC_CIER_LSECSSIE_Msk                /*!< LSE CSS interrupt enable */
+#define RCC_CIER_HSECSSIE_Pos                   (17U)
+#define RCC_CIER_HSECSSIE_Msk                   (0x1UL << RCC_CIER_HSECSSIE_Pos)      /*!< 0x00020000 */
+#define RCC_CIER_HSECSSIE                       RCC_CIER_HSECSSIE_Msk                /*!< HSE CSS interrupt enable */
+#define RCC_CIER_WKUPIE_Pos                     (24U)
+#define RCC_CIER_WKUPIE_Msk                     (0x1UL << RCC_CIER_WKUPIE_Pos)        /*!< 0x01000000 */
+#define RCC_CIER_WKUPIE                         RCC_CIER_WKUPIE_Msk                  /*!< CPU wake-up from Stop interrupt enable */
+
+/*******************  Bit definition for RCC_CIFR register  *******************/
+#define RCC_CIFR_LSIRDYF_Pos                    (0U)
+#define RCC_CIFR_LSIRDYF_Msk                    (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                        RCC_CIFR_LSIRDYF_Msk                 /*!< LSI ready interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos                    (1U)
+#define RCC_CIFR_LSERDYF_Msk                    (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                        RCC_CIFR_LSERDYF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos                    (2U)
+#define RCC_CIFR_MSIRDYF_Msk                    (0x1UL << RCC_CIFR_MSIRDYF_Pos)       /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                        RCC_CIFR_MSIRDYF_Msk                 /*!< MSI ready interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos                    (3U)
+#define RCC_CIFR_HSIRDYF_Msk                    (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                        RCC_CIFR_HSIRDYF_Msk                 /*!< HSI ready interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos                    (4U)
+#define RCC_CIFR_HSERDYF_Msk                    (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                        RCC_CIFR_HSERDYF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_PLL1RDYF_Pos                   (8U)
+#define RCC_CIFR_PLL1RDYF_Msk                   (0x1UL << RCC_CIFR_PLL1RDYF_Pos)      /*!< 0x00000100 */
+#define RCC_CIFR_PLL1RDYF                       RCC_CIFR_PLL1RDYF_Msk                /*!< PLL1 ready interrupt flag */
+#define RCC_CIFR_PLL2RDYF_Pos                   (9U)
+#define RCC_CIFR_PLL2RDYF_Msk                   (0x1UL << RCC_CIFR_PLL2RDYF_Pos)      /*!< 0x00000200 */
+#define RCC_CIFR_PLL2RDYF                       RCC_CIFR_PLL2RDYF_Msk                /*!< PLL2 ready interrupt flag */
+#define RCC_CIFR_PLL3RDYF_Pos                   (10U)
+#define RCC_CIFR_PLL3RDYF_Msk                   (0x1UL << RCC_CIFR_PLL3RDYF_Pos)      /*!< 0x00000400 */
+#define RCC_CIFR_PLL3RDYF                       RCC_CIFR_PLL3RDYF_Msk                /*!< PLL3 ready interrupt flag */
+#define RCC_CIFR_PLL4RDYF_Pos                   (11U)
+#define RCC_CIFR_PLL4RDYF_Msk                   (0x1UL << RCC_CIFR_PLL4RDYF_Pos)      /*!< 0x00000800 */
+#define RCC_CIFR_PLL4RDYF                       RCC_CIFR_PLL4RDYF_Msk                /*!< PLL4 ready interrupt flag */
+#define RCC_CIFR_LSECSSF_Pos                    (16U)
+#define RCC_CIFR_LSECSSF_Msk                    (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00010000 */
+#define RCC_CIFR_LSECSSF                        RCC_CIFR_LSECSSF_Msk                 /*!< LSE ready interrupt flag */
+#define RCC_CIFR_HSECSSF_Pos                    (17U)
+#define RCC_CIFR_HSECSSF_Msk                    (0x1UL << RCC_CIFR_HSECSSF_Pos)       /*!< 0x00020000 */
+#define RCC_CIFR_HSECSSF                        RCC_CIFR_HSECSSF_Msk                 /*!< HSE ready interrupt flag */
+#define RCC_CIFR_WKUPF_Pos                      (24U)
+#define RCC_CIFR_WKUPF_Msk                      (0x1UL << RCC_CIFR_WKUPF_Pos)         /*!< 0x01000000 */
+#define RCC_CIFR_WKUPF                          RCC_CIFR_WKUPF_Msk                   /*!< CPU wake-up from Stop interrupt flag */
+
+/*******************  Bit definition for RCC_CICR register  *******************/
+#define RCC_CICR_LSIRDYC_Pos                    (0U)
+#define RCC_CICR_LSIRDYC_Msk                    (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                        RCC_CICR_LSIRDYC_Msk                 /*!< LSI ready interrupt clear */
+#define RCC_CICR_LSERDYC_Pos                    (1U)
+#define RCC_CICR_LSERDYC_Msk                    (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                        RCC_CICR_LSERDYC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_MSIRDYC_Pos                    (2U)
+#define RCC_CICR_MSIRDYC_Msk                    (0x1UL << RCC_CICR_MSIRDYC_Pos)       /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                        RCC_CICR_MSIRDYC_Msk                 /*!< MSI ready interrupt clear */
+#define RCC_CICR_HSIRDYC_Pos                    (3U)
+#define RCC_CICR_HSIRDYC_Msk                    (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                        RCC_CICR_HSIRDYC_Msk                 /*!< HSI ready interrupt clear */
+#define RCC_CICR_HSERDYC_Pos                    (4U)
+#define RCC_CICR_HSERDYC_Msk                    (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                        RCC_CICR_HSERDYC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_PLL1RDYC_Pos                   (8U)
+#define RCC_CICR_PLL1RDYC_Msk                   (0x1UL << RCC_CICR_PLL1RDYC_Pos)      /*!< 0x00000100 */
+#define RCC_CICR_PLL1RDYC                       RCC_CICR_PLL1RDYC_Msk                /*!< PLL1 ready interrupt clear */
+#define RCC_CICR_PLL2RDYC_Pos                   (9U)
+#define RCC_CICR_PLL2RDYC_Msk                   (0x1UL << RCC_CICR_PLL2RDYC_Pos)      /*!< 0x00000200 */
+#define RCC_CICR_PLL2RDYC                       RCC_CICR_PLL2RDYC_Msk                /*!< PLL2 ready interrupt clear */
+#define RCC_CICR_PLL3RDYC_Pos                   (10U)
+#define RCC_CICR_PLL3RDYC_Msk                   (0x1UL << RCC_CICR_PLL3RDYC_Pos)      /*!< 0x00000400 */
+#define RCC_CICR_PLL3RDYC                       RCC_CICR_PLL3RDYC_Msk                /*!< PLL3 ready interrupt clear */
+#define RCC_CICR_PLL4RDYC_Pos                   (11U)
+#define RCC_CICR_PLL4RDYC_Msk                   (0x1UL << RCC_CICR_PLL4RDYC_Pos)      /*!< 0x00000800 */
+#define RCC_CICR_PLL4RDYC                       RCC_CICR_PLL4RDYC_Msk                /*!< PLL4 ready interrupt clear */
+#define RCC_CICR_LSECSSC_Pos                    (16U)
+#define RCC_CICR_LSECSSC_Msk                    (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00010000 */
+#define RCC_CICR_LSECSSC                        RCC_CICR_LSECSSC_Msk                 /*!< LSE ready interrupt clear */
+#define RCC_CICR_HSECSSC_Pos                    (17U)
+#define RCC_CICR_HSECSSC_Msk                    (0x1UL << RCC_CICR_HSECSSC_Pos)       /*!< 0x00020000 */
+#define RCC_CICR_HSECSSC                        RCC_CICR_HSECSSC_Msk                 /*!< HSE ready interrupt clear */
+#define RCC_CICR_WKUPFC_Pos                     (24U)
+#define RCC_CICR_WKUPFC_Msk                     (0x1UL << RCC_CICR_WKUPFC_Pos)        /*!< 0x01000000 */
+#define RCC_CICR_WKUPFC                         RCC_CICR_WKUPFC_Msk                  /*!< CPU wake-up ready interrupt clear */
+
+/******************  Bit definition for RCC_CCIPR1 register  ******************/
+#define RCC_CCIPR1_ADF1SEL_Pos                  (0U)
+#define RCC_CCIPR1_ADF1SEL_Msk                  (0x7UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR1_ADF1SEL                      RCC_CCIPR1_ADF1SEL_Msk                            /*!< Source selection for the ADF1 kernel clock */
+#define RCC_CCIPR1_ADF1SEL_0                    (0x1UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR1_ADF1SEL_1                    (0x2UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR1_ADF1SEL_2                    (0x4UL << RCC_CCIPR1_ADF1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR1_ADC12SEL_Pos                 (4U)
+#define RCC_CCIPR1_ADC12SEL_Msk                 (0x7UL << RCC_CCIPR1_ADC12SEL_Pos)                 /*!< 0x00000070 */
+#define RCC_CCIPR1_ADC12SEL                     RCC_CCIPR1_ADC12SEL_Msk                           /*!< Source selection for the ADC12 kernel clock */
+#define RCC_CCIPR1_ADC12SEL_0                   (0x1UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR1_ADC12SEL_1                   (0x2UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR1_ADC12SEL_2                   (0x4UL << RCC_CCIPR1_ADC12SEL_Pos)                /*!< 0x00000040 */
+#define RCC_CCIPR1_ADCPRE_Pos                   (8U)
+#define RCC_CCIPR1_ADCPRE_Msk                   (0xFFUL << RCC_CCIPR1_ADCPRE_Pos)                  /*!< 0x0000FF00 */
+#define RCC_CCIPR1_ADCPRE                       RCC_CCIPR1_ADCPRE_Msk                             /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */
+#define RCC_CCIPR1_ADCPRE_0                     (0x1UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR1_ADCPRE_1                     (0x2UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR1_ADCPRE_2                     (0x4UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000400 */
+#define RCC_CCIPR1_ADCPRE_3                     (0x8UL << RCC_CCIPR1_ADCPRE_Pos)                 /*!< 0x00000800 */
+#define RCC_CCIPR1_ADCPRE_4                     (0x10UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR1_ADCPRE_5                     (0x20UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR1_ADCPRE_6                     (0x40UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR1_ADCPRE_7                     (0x80UL << RCC_CCIPR1_ADCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR1_DCMIPPSEL_Pos                (20U)
+#define RCC_CCIPR1_DCMIPPSEL_Msk                (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos)                /*!< 0x00300000 */
+#define RCC_CCIPR1_DCMIPPSEL                    RCC_CCIPR1_DCMIPPSEL_Msk                          /*!< Source selection for the DCMIPP kernel clock */
+#define RCC_CCIPR1_DCMIPPSEL_0                  (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00100000 */
+#define RCC_CCIPR1_DCMIPPSEL_1                  (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos)           /*!< 0x00200000 */
+
+/******************  Bit definition for RCC_CCIPR2 register  ******************/
+#define RCC_CCIPR2_ETH1PTPSEL_Pos               (0U)
+#define RCC_CCIPR2_ETH1PTPSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000003 */
+#define RCC_CCIPR2_ETH1PTPSEL                   RCC_CCIPR2_ETH1PTPSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1PTPSEL_0                 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR2_ETH1PTPSEL_1                 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR2_ETH1PTPDIV_Pos               (4U)
+#define RCC_CCIPR2_ETH1PTPDIV_Msk               (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos)               /*!< 0x000000F0 */
+#define RCC_CCIPR2_ETH1PTPDIV                   RCC_CCIPR2_ETH1PTPDIV_Msk                         /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */
+#define RCC_CCIPR2_ETH1PTPDIV_0                 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR2_ETH1PTPDIV_1                 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR2_ETH1PTPDIV_2                 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR2_ETH1PTPDIV_3                 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos)              /*!< 0x00000080 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos           (8U)
+#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk           (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos)           /*!< 0x00000100 */
+#define RCC_CCIPR2_ETH1PWRDOWNACK               RCC_CCIPR2_ETH1PWRDOWNACK_Msk                     /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1CLKSEL_Pos               (12U)
+#define RCC_CCIPR2_ETH1CLKSEL_Msk               (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR2_ETH1CLKSEL                   RCC_CCIPR2_ETH1CLKSEL_Msk                         /*!< Source selection for the ETH1 kernel clock */
+#define RCC_CCIPR2_ETH1CLKSEL_0                 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR2_ETH1CLKSEL_1                 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR2_ETH1SEL_Pos                  (16U)
+#define RCC_CCIPR2_ETH1SEL_Msk                  (0x7UL << RCC_CCIPR2_ETH1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR2_ETH1SEL                      RCC_CCIPR2_ETH1SEL_Msk                            /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1SEL_0                    (0x1UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR2_ETH1SEL_1                    (0x2UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR2_ETH1SEL_2                    (0x4UL << RCC_CCIPR2_ETH1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL_Pos            (20U)
+#define RCC_CCIPR2_ETH1REFCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos)            /*!< 0x00100000 */
+#define RCC_CCIPR2_ETH1REFCLKSEL                RCC_CCIPR2_ETH1REFCLKSEL_Msk                      /*!< Set and reset by software */
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos            (24U)
+#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk            (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR2_ETH1GTXCLKSEL                RCC_CCIPR2_ETH1GTXCLKSEL_Msk                      /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR3 register  ******************/
+#define RCC_CCIPR3_FDCANSEL_Pos                 (0U)
+#define RCC_CCIPR3_FDCANSEL_Msk                 (0x3UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR3_FDCANSEL                     RCC_CCIPR3_FDCANSEL_Msk                           /*!< Source selection for the FDCAN kernel clock */
+#define RCC_CCIPR3_FDCANSEL_0                   (0x1UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR3_FDCANSEL_1                   (0x2UL << RCC_CCIPR3_FDCANSEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR3_FMCSEL_Pos                   (4U)
+#define RCC_CCIPR3_FMCSEL_Msk                   (0x3UL << RCC_CCIPR3_FMCSEL_Pos)                   /*!< 0x00000030 */
+#define RCC_CCIPR3_FMCSEL                       RCC_CCIPR3_FMCSEL_Msk                             /*!< Source selection for the FMC kernel clock */
+#define RCC_CCIPR3_FMCSEL_0                     (0x1UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000010 */
+#define RCC_CCIPR3_FMCSEL_1                     (0x2UL << RCC_CCIPR3_FMCSEL_Pos)                  /*!< 0x00000020 */
+#define RCC_CCIPR3_DFTSEL_Pos                   (8U)
+#define RCC_CCIPR3_DFTSEL_Msk                   (0x1UL << RCC_CCIPR3_DFTSEL_Pos)                   /*!< 0x00000100 */
+#define RCC_CCIPR3_DFTSEL                       RCC_CCIPR3_DFTSEL_Msk                             /*!< Source selection for the DFT kernel clock */
+
+/******************  Bit definition for RCC_CCIPR4 register  ******************/
+#define RCC_CCIPR4_I2C1SEL_Pos                  (0U)
+#define RCC_CCIPR4_I2C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR4_I2C1SEL                      RCC_CCIPR4_I2C1SEL_Msk                            /*!< Source selection for the I2C1 kernel clock */
+#define RCC_CCIPR4_I2C1SEL_0                    (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR4_I2C1SEL_1                    (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR4_I2C1SEL_2                    (0x4UL << RCC_CCIPR4_I2C1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR4_I2C2SEL_Pos                  (4U)
+#define RCC_CCIPR4_I2C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C2SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR4_I2C2SEL                      RCC_CCIPR4_I2C2SEL_Msk                            /*!< Source selection for the I2C2 kernel clock */
+#define RCC_CCIPR4_I2C2SEL_0                    (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR4_I2C2SEL_1                    (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR4_I2C2SEL_2                    (0x4UL << RCC_CCIPR4_I2C2SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR4_I2C3SEL_Pos                  (8U)
+#define RCC_CCIPR4_I2C3SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C3SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR4_I2C3SEL                      RCC_CCIPR4_I2C3SEL_Msk                            /*!< Source selection for the I2C3 kernel clock */
+#define RCC_CCIPR4_I2C3SEL_0                    (0x1UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR4_I2C3SEL_1                    (0x2UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR4_I2C3SEL_2                    (0x4UL << RCC_CCIPR4_I2C3SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR4_I2C4SEL_Pos                  (12U)
+#define RCC_CCIPR4_I2C4SEL_Msk                  (0x7UL << RCC_CCIPR4_I2C4SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR4_I2C4SEL                      RCC_CCIPR4_I2C4SEL_Msk                            /*!< Source selection for the I2C4 kernel clock */
+#define RCC_CCIPR4_I2C4SEL_0                    (0x1UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR4_I2C4SEL_1                    (0x2UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR4_I2C4SEL_2                    (0x4UL << RCC_CCIPR4_I2C4SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR4_I3C1SEL_Pos                  (16U)
+#define RCC_CCIPR4_I3C1SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR4_I3C1SEL                      RCC_CCIPR4_I3C1SEL_Msk                            /*!< Source selection for the I3C1 kernel clock */
+#define RCC_CCIPR4_I3C1SEL_0                    (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR4_I3C1SEL_1                    (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR4_I3C1SEL_2                    (0x4UL << RCC_CCIPR4_I3C1SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR4_I3C2SEL_Pos                  (20U)
+#define RCC_CCIPR4_I3C2SEL_Msk                  (0x7UL << RCC_CCIPR4_I3C2SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR4_I3C2SEL                      RCC_CCIPR4_I3C2SEL_Msk                            /*!< Source selection for the I3C2 kernel clock */
+#define RCC_CCIPR4_I3C2SEL_0                    (0x1UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR4_I3C2SEL_1                    (0x2UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR4_I3C2SEL_2                    (0x4UL << RCC_CCIPR4_I3C2SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR4_LTDCSEL_Pos                  (24U)
+#define RCC_CCIPR4_LTDCSEL_Msk                  (0x3UL << RCC_CCIPR4_LTDCSEL_Pos)                  /*!< 0x03000000 */
+#define RCC_CCIPR4_LTDCSEL                      RCC_CCIPR4_LTDCSEL_Msk                            /*!< Source selection for the LTDC kernel clock */
+#define RCC_CCIPR4_LTDCSEL_0                    (0x1UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR4_LTDCSEL_1                    (0x2UL << RCC_CCIPR4_LTDCSEL_Pos)            /*!< 0x02000000 */
+
+/******************  Bit definition for RCC_CCIPR5 register  ******************/
+#define RCC_CCIPR5_MCO1SEL_Pos                  (0U)
+#define RCC_CCIPR5_MCO1SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000007 */
+#define RCC_CCIPR5_MCO1SEL                      RCC_CCIPR5_MCO1SEL_Msk                            /*!< Source selection for the MCO1 kernel clock */
+#define RCC_CCIPR5_MCO1SEL_0                    (0x1UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000001 */
+#define RCC_CCIPR5_MCO1SEL_1                    (0x2UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000002 */
+#define RCC_CCIPR5_MCO1SEL_2                    (0x4UL << RCC_CCIPR5_MCO1SEL_Pos)                  /*!< 0x00000004 */
+#define RCC_CCIPR5_MCO1PRE_Pos                  (4U)
+#define RCC_CCIPR5_MCO1PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO1PRE_Pos)                  /*!< 0x000000F0 */
+#define RCC_CCIPR5_MCO1PRE                      RCC_CCIPR5_MCO1PRE_Msk                            /*!< MCO1 Kernel clock divider selection (for clock MCO1) */
+#define RCC_CCIPR5_MCO1PRE_0                    (0x1UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR5_MCO1PRE_1                    (0x2UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR5_MCO1PRE_2                    (0x4UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR5_MCO1PRE_3                    (0x8UL << RCC_CCIPR5_MCO1PRE_Pos)                 /*!< 0x00000080 */
+#define RCC_CCIPR5_MCO2SEL_Pos                  (8U)
+#define RCC_CCIPR5_MCO2SEL_Msk                  (0x7UL << RCC_CCIPR5_MCO2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR5_MCO2SEL                      RCC_CCIPR5_MCO2SEL_Msk                            /*!< Source selection for the MCO2 kernel clock */
+#define RCC_CCIPR5_MCO2SEL_0                    (0x1UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR5_MCO2SEL_1                    (0x2UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR5_MCO2SEL_2                    (0x4UL << RCC_CCIPR5_MCO2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR5_MCO2PRE_Pos                  (12U)
+#define RCC_CCIPR5_MCO2PRE_Msk                  (0xFUL << RCC_CCIPR5_MCO2PRE_Pos)                  /*!< 0x0000F000 */
+#define RCC_CCIPR5_MCO2PRE                      RCC_CCIPR5_MCO2PRE_Msk                            /*!< MCO2 Kernel clock divider selection (for clock MCO2) */
+#define RCC_CCIPR5_MCO2PRE_0                    (0x1UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR5_MCO2PRE_1                    (0x2UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR5_MCO2PRE_2                    (0x4UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR5_MCO2PRE_3                    (0x8UL << RCC_CCIPR5_MCO2PRE_Pos)               /*!< 0x00008000 */
+#define RCC_CCIPR5_MDF1SEL_Pos                  (16U)
+#define RCC_CCIPR5_MDF1SEL_Msk                  (0x7UL << RCC_CCIPR5_MDF1SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR5_MDF1SEL                      RCC_CCIPR5_MDF1SEL_Msk                            /*!< Source selection for the MDF1 kernel clock */
+#define RCC_CCIPR5_MDF1SEL_0                    (0x1UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR5_MDF1SEL_1                    (0x2UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR5_MDF1SEL_2                    (0x4UL << RCC_CCIPR5_MDF1SEL_Pos)              /*!< 0x00040000 */
+
+/******************  Bit definition for RCC_CCIPR6 register  ******************/
+#define RCC_CCIPR6_XSPI1SEL_Pos                 (0U)
+#define RCC_CCIPR6_XSPI1SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000003 */
+#define RCC_CCIPR6_XSPI1SEL                     RCC_CCIPR6_XSPI1SEL_Msk                           /*!< Source selection for the XSPI1 kernel clock */
+#define RCC_CCIPR6_XSPI1SEL_0                   (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000001 */
+#define RCC_CCIPR6_XSPI1SEL_1                   (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos)                 /*!< 0x00000002 */
+#define RCC_CCIPR6_XSPI2SEL_Pos                 (4U)
+#define RCC_CCIPR6_XSPI2SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos)                 /*!< 0x00000030 */
+#define RCC_CCIPR6_XSPI2SEL                     RCC_CCIPR6_XSPI2SEL_Msk                           /*!< Source selection for the XSPI2 kernel clock */
+#define RCC_CCIPR6_XSPI2SEL_0                   (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000010 */
+#define RCC_CCIPR6_XSPI2SEL_1                   (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos)                /*!< 0x00000020 */
+#define RCC_CCIPR6_XSPI3SEL_Pos                 (8U)
+#define RCC_CCIPR6_XSPI3SEL_Msk                 (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos)                 /*!< 0x00000300 */
+#define RCC_CCIPR6_XSPI3SEL                     RCC_CCIPR6_XSPI3SEL_Msk                           /*!< Source selection for the XSPI3 kernel clock */
+#define RCC_CCIPR6_XSPI3SEL_0                   (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000100 */
+#define RCC_CCIPR6_XSPI3SEL_1                   (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos)               /*!< 0x00000200 */
+#define RCC_CCIPR6_OTGPHY1SEL_Pos               (12U)
+#define RCC_CCIPR6_OTGPHY1SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos)               /*!< 0x00003000 */
+#define RCC_CCIPR6_OTGPHY1SEL                   RCC_CCIPR6_OTGPHY1SEL_Msk                         /*!< Source selection for the OTGPHY1 kernel clock */
+#define RCC_CCIPR6_OTGPHY1SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR6_OTGPHY1SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos          (16U)
+#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos)          /*!< 0x00010000 */
+#define RCC_CCIPR6_OTGPHY1CKREFSEL              RCC_CCIPR6_OTGPHY1CKREFSEL_Msk                    /*!< Set and reset by software */
+#define RCC_CCIPR6_OTGPHY2SEL_Pos               (20U)
+#define RCC_CCIPR6_OTGPHY2SEL_Msk               (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos)               /*!< 0x00300000 */
+#define RCC_CCIPR6_OTGPHY2SEL                   RCC_CCIPR6_OTGPHY2SEL_Msk                         /*!< Source selection for the OTGPHY2 kernel clock */
+#define RCC_CCIPR6_OTGPHY2SEL_0                 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR6_OTGPHY2SEL_1                 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos          (24U)
+#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk          (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR6_OTGPHY2CKREFSEL              RCC_CCIPR6_OTGPHY2CKREFSEL_Msk                    /*!< Set and reset by software */
+
+/******************  Bit definition for RCC_CCIPR7 register  ******************/
+#define RCC_CCIPR7_PERSEL_Pos                   (0U)
+#define RCC_CCIPR7_PERSEL_Msk                   (0x7UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000007 */
+#define RCC_CCIPR7_PERSEL                       RCC_CCIPR7_PERSEL_Msk                             /*!< Source selection for the PER kernel clock */
+#define RCC_CCIPR7_PERSEL_0                     (0x1UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000001 */
+#define RCC_CCIPR7_PERSEL_1                     (0x2UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000002 */
+#define RCC_CCIPR7_PERSEL_2                     (0x4UL << RCC_CCIPR7_PERSEL_Pos)                   /*!< 0x00000004 */
+#define RCC_CCIPR7_PSSISEL_Pos                  (4U)
+#define RCC_CCIPR7_PSSISEL_Msk                  (0x3UL << RCC_CCIPR7_PSSISEL_Pos)                  /*!< 0x00000030 */
+#define RCC_CCIPR7_PSSISEL                      RCC_CCIPR7_PSSISEL_Msk                            /*!< Source selection for the PSSI kernel clock */
+#define RCC_CCIPR7_PSSISEL_0                    (0x1UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR7_PSSISEL_1                    (0x2UL << RCC_CCIPR7_PSSISEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR7_RTCSEL_Pos                   (8U)
+#define RCC_CCIPR7_RTCSEL_Msk                   (0x3UL << RCC_CCIPR7_RTCSEL_Pos)                   /*!< 0x00000300 */
+#define RCC_CCIPR7_RTCSEL                       RCC_CCIPR7_RTCSEL_Msk                             /*!< Source selection for the RTC kernel clock */
+#define RCC_CCIPR7_RTCSEL_0                     (0x1UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000100 */
+#define RCC_CCIPR7_RTCSEL_1                     (0x2UL << RCC_CCIPR7_RTCSEL_Pos)                 /*!< 0x00000200 */
+#define RCC_CCIPR7_RTCPRE_Pos                   (12U)
+#define RCC_CCIPR7_RTCPRE_Msk                   (0x3FUL << RCC_CCIPR7_RTCPRE_Pos)                  /*!< 0x0003F000 */
+#define RCC_CCIPR7_RTCPRE                       RCC_CCIPR7_RTCPRE_Msk                             /*!< RTC OSC clock divider selection (for clock hse_ck) */
+#define RCC_CCIPR7_RTCPRE_0                     (0x1UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00001000 */
+#define RCC_CCIPR7_RTCPRE_1                     (0x2UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00002000 */
+#define RCC_CCIPR7_RTCPRE_2                     (0x4UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00004000 */
+#define RCC_CCIPR7_RTCPRE_3                     (0x8UL << RCC_CCIPR7_RTCPRE_Pos)                /*!< 0x00008000 */
+#define RCC_CCIPR7_RTCPRE_4                     (0x10UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00010000 */
+#define RCC_CCIPR7_RTCPRE_5                     (0x20UL << RCC_CCIPR7_RTCPRE_Pos)               /*!< 0x00020000 */
+#define RCC_CCIPR7_SAI1SEL_Pos                  (20U)
+#define RCC_CCIPR7_SAI1SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI1SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR7_SAI1SEL                      RCC_CCIPR7_SAI1SEL_Msk                            /*!< Source selection for the SAI1 kernel clock */
+#define RCC_CCIPR7_SAI1SEL_0                    (0x1UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR7_SAI1SEL_1                    (0x2UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR7_SAI1SEL_2                    (0x4UL << RCC_CCIPR7_SAI1SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR7_SAI2SEL_Pos                  (24U)
+#define RCC_CCIPR7_SAI2SEL_Msk                  (0x7UL << RCC_CCIPR7_SAI2SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR7_SAI2SEL                      RCC_CCIPR7_SAI2SEL_Msk                            /*!< Source selection for the SAI2 kernel clock */
+#define RCC_CCIPR7_SAI2SEL_0                    (0x1UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR7_SAI2SEL_1                    (0x2UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR7_SAI2SEL_2                    (0x4UL << RCC_CCIPR7_SAI2SEL_Pos)            /*!< 0x04000000 */
+
+/******************  Bit definition for RCC_CCIPR8 register  ******************/
+#define RCC_CCIPR8_SDMMC1SEL_Pos                (0U)
+#define RCC_CCIPR8_SDMMC1SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000003 */
+#define RCC_CCIPR8_SDMMC1SEL                    RCC_CCIPR8_SDMMC1SEL_Msk                          /*!< Source selection for the SDMMC1 kernel clock */
+#define RCC_CCIPR8_SDMMC1SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR8_SDMMC1SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR8_SDMMC2SEL_Pos                (4U)
+#define RCC_CCIPR8_SDMMC2SEL_Msk                (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos)                /*!< 0x00000030 */
+#define RCC_CCIPR8_SDMMC2SEL                    RCC_CCIPR8_SDMMC2SEL_Msk                          /*!< Source selection for the SDMMC2 kernel clock */
+#define RCC_CCIPR8_SDMMC2SEL_0                  (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000010 */
+#define RCC_CCIPR8_SDMMC2SEL_1                  (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos)               /*!< 0x00000020 */
+
+/******************  Bit definition for RCC_CCIPR9 register  ******************/
+#define RCC_CCIPR9_SPDIFRX1SEL_Pos              (0U)
+#define RCC_CCIPR9_SPDIFRX1SEL_Msk              (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000007 */
+#define RCC_CCIPR9_SPDIFRX1SEL                  RCC_CCIPR9_SPDIFRX1SEL_Msk                        /*!< Source selection for the SPDIFRX1 kernel clock */
+#define RCC_CCIPR9_SPDIFRX1SEL_0                (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000001 */
+#define RCC_CCIPR9_SPDIFRX1SEL_1                (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000002 */
+#define RCC_CCIPR9_SPDIFRX1SEL_2                (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos)              /*!< 0x00000004 */
+#define RCC_CCIPR9_SPI1SEL_Pos                  (4U)
+#define RCC_CCIPR9_SPI1SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI1SEL_Pos)                  /*!< 0x00000070 */
+#define RCC_CCIPR9_SPI1SEL                      RCC_CCIPR9_SPI1SEL_Msk                            /*!< Source selection for the SPI1 kernel clock */
+#define RCC_CCIPR9_SPI1SEL_0                    (0x1UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000010 */
+#define RCC_CCIPR9_SPI1SEL_1                    (0x2UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000020 */
+#define RCC_CCIPR9_SPI1SEL_2                    (0x4UL << RCC_CCIPR9_SPI1SEL_Pos)                 /*!< 0x00000040 */
+#define RCC_CCIPR9_SPI2SEL_Pos                  (8U)
+#define RCC_CCIPR9_SPI2SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI2SEL_Pos)                  /*!< 0x00000700 */
+#define RCC_CCIPR9_SPI2SEL                      RCC_CCIPR9_SPI2SEL_Msk                            /*!< Source selection for the SPI2 kernel clock */
+#define RCC_CCIPR9_SPI2SEL_0                    (0x1UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000100 */
+#define RCC_CCIPR9_SPI2SEL_1                    (0x2UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000200 */
+#define RCC_CCIPR9_SPI2SEL_2                    (0x4UL << RCC_CCIPR9_SPI2SEL_Pos)                /*!< 0x00000400 */
+#define RCC_CCIPR9_SPI3SEL_Pos                  (12U)
+#define RCC_CCIPR9_SPI3SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI3SEL_Pos)                  /*!< 0x00007000 */
+#define RCC_CCIPR9_SPI3SEL                      RCC_CCIPR9_SPI3SEL_Msk                            /*!< Source selection for the SPI3 kernel clock */
+#define RCC_CCIPR9_SPI3SEL_0                    (0x1UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00001000 */
+#define RCC_CCIPR9_SPI3SEL_1                    (0x2UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00002000 */
+#define RCC_CCIPR9_SPI3SEL_2                    (0x4UL << RCC_CCIPR9_SPI3SEL_Pos)               /*!< 0x00004000 */
+#define RCC_CCIPR9_SPI4SEL_Pos                  (16U)
+#define RCC_CCIPR9_SPI4SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI4SEL_Pos)                  /*!< 0x00070000 */
+#define RCC_CCIPR9_SPI4SEL                      RCC_CCIPR9_SPI4SEL_Msk                            /*!< Source selection for the SPI4 kernel clock */
+#define RCC_CCIPR9_SPI4SEL_0                    (0x1UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00010000 */
+#define RCC_CCIPR9_SPI4SEL_1                    (0x2UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00020000 */
+#define RCC_CCIPR9_SPI4SEL_2                    (0x4UL << RCC_CCIPR9_SPI4SEL_Pos)              /*!< 0x00040000 */
+#define RCC_CCIPR9_SPI5SEL_Pos                  (20U)
+#define RCC_CCIPR9_SPI5SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI5SEL_Pos)                  /*!< 0x00700000 */
+#define RCC_CCIPR9_SPI5SEL                      RCC_CCIPR9_SPI5SEL_Msk                            /*!< Source selection for the SPI5 kernel clock */
+#define RCC_CCIPR9_SPI5SEL_0                    (0x1UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00100000 */
+#define RCC_CCIPR9_SPI5SEL_1                    (0x2UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00200000 */
+#define RCC_CCIPR9_SPI5SEL_2                    (0x4UL << RCC_CCIPR9_SPI5SEL_Pos)             /*!< 0x00400000 */
+#define RCC_CCIPR9_SPI6SEL_Pos                  (24U)
+#define RCC_CCIPR9_SPI6SEL_Msk                  (0x7UL << RCC_CCIPR9_SPI6SEL_Pos)                  /*!< 0x07000000 */
+#define RCC_CCIPR9_SPI6SEL                      RCC_CCIPR9_SPI6SEL_Msk                            /*!< Source selection for the SPI6 kernel clock */
+#define RCC_CCIPR9_SPI6SEL_0                    (0x1UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x01000000 */
+#define RCC_CCIPR9_SPI6SEL_1                    (0x2UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x02000000 */
+#define RCC_CCIPR9_SPI6SEL_2                    (0x4UL << RCC_CCIPR9_SPI6SEL_Pos)            /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR12 register  ******************/
+#define RCC_CCIPR12_LPTIM1SEL_Pos               (8U)
+#define RCC_CCIPR12_LPTIM1SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR12_LPTIM1SEL                   RCC_CCIPR12_LPTIM1SEL_Msk                         /*!< Source selection for the LPTIM1 kernel clock */
+#define RCC_CCIPR12_LPTIM1SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR12_LPTIM1SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR12_LPTIM1SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR12_LPTIM2SEL_Pos               (12U)
+#define RCC_CCIPR12_LPTIM2SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos)               /*!< 0x00007000 */
+#define RCC_CCIPR12_LPTIM2SEL                   RCC_CCIPR12_LPTIM2SEL_Msk                         /*!< Source selection for the LPTIM2 kernel clock */
+#define RCC_CCIPR12_LPTIM2SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00001000 */
+#define RCC_CCIPR12_LPTIM2SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00002000 */
+#define RCC_CCIPR12_LPTIM2SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos)            /*!< 0x00004000 */
+#define RCC_CCIPR12_LPTIM3SEL_Pos               (16U)
+#define RCC_CCIPR12_LPTIM3SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos)               /*!< 0x00070000 */
+#define RCC_CCIPR12_LPTIM3SEL                   RCC_CCIPR12_LPTIM3SEL_Msk                         /*!< Source selection for the LPTIM3 kernel clock */
+#define RCC_CCIPR12_LPTIM3SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00010000 */
+#define RCC_CCIPR12_LPTIM3SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00020000 */
+#define RCC_CCIPR12_LPTIM3SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos)           /*!< 0x00040000 */
+#define RCC_CCIPR12_LPTIM4SEL_Pos               (20U)
+#define RCC_CCIPR12_LPTIM4SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR12_LPTIM4SEL                   RCC_CCIPR12_LPTIM4SEL_Msk                         /*!< Source selection for the LPTIM4 kernel clock */
+#define RCC_CCIPR12_LPTIM4SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR12_LPTIM4SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR12_LPTIM4SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR12_LPTIM5SEL_Pos               (24U)
+#define RCC_CCIPR12_LPTIM5SEL_Msk               (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos)               /*!< 0x07000000 */
+#define RCC_CCIPR12_LPTIM5SEL                   RCC_CCIPR12_LPTIM5SEL_Msk                         /*!< Source selection for the LPTIM5 kernel clock */
+#define RCC_CCIPR12_LPTIM5SEL_0                 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x01000000 */
+#define RCC_CCIPR12_LPTIM5SEL_1                 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x02000000 */
+#define RCC_CCIPR12_LPTIM5SEL_2                 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos)         /*!< 0x04000000 */
+
+/*****************  Bit definition for RCC_CCIPR13 register  ******************/
+#define RCC_CCIPR13_USART1SEL_Pos               (0U)
+#define RCC_CCIPR13_USART1SEL_Msk               (0x7UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000007 */
+#define RCC_CCIPR13_USART1SEL                   RCC_CCIPR13_USART1SEL_Msk                         /*!< Source selection for the USART1 kernel clock */
+#define RCC_CCIPR13_USART1SEL_0                 (0x1UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000001 */
+#define RCC_CCIPR13_USART1SEL_1                 (0x2UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000002 */
+#define RCC_CCIPR13_USART1SEL_2                 (0x4UL << RCC_CCIPR13_USART1SEL_Pos)               /*!< 0x00000004 */
+#define RCC_CCIPR13_USART2SEL_Pos               (4U)
+#define RCC_CCIPR13_USART2SEL_Msk               (0x7UL << RCC_CCIPR13_USART2SEL_Pos)               /*!< 0x00000070 */
+#define RCC_CCIPR13_USART2SEL                   RCC_CCIPR13_USART2SEL_Msk                         /*!< Source selection for the USART2 kernel clock */
+#define RCC_CCIPR13_USART2SEL_0                 (0x1UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000010 */
+#define RCC_CCIPR13_USART2SEL_1                 (0x2UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000020 */
+#define RCC_CCIPR13_USART2SEL_2                 (0x4UL << RCC_CCIPR13_USART2SEL_Pos)              /*!< 0x00000040 */
+#define RCC_CCIPR13_USART3SEL_Pos               (8U)
+#define RCC_CCIPR13_USART3SEL_Msk               (0x7UL << RCC_CCIPR13_USART3SEL_Pos)               /*!< 0x00000700 */
+#define RCC_CCIPR13_USART3SEL                   RCC_CCIPR13_USART3SEL_Msk                         /*!< Source selection for the USART3 kernel clock */
+#define RCC_CCIPR13_USART3SEL_0                 (0x1UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000100 */
+#define RCC_CCIPR13_USART3SEL_1                 (0x2UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000200 */
+#define RCC_CCIPR13_USART3SEL_2                 (0x4UL << RCC_CCIPR13_USART3SEL_Pos)             /*!< 0x00000400 */
+#define RCC_CCIPR13_UART4SEL_Pos                (12U)
+#define RCC_CCIPR13_UART4SEL_Msk                (0x7UL << RCC_CCIPR13_UART4SEL_Pos)                /*!< 0x00007000 */
+#define RCC_CCIPR13_UART4SEL                    RCC_CCIPR13_UART4SEL_Msk                          /*!< Source selection for the UART4 kernel clock */
+#define RCC_CCIPR13_UART4SEL_0                  (0x1UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00001000 */
+#define RCC_CCIPR13_UART4SEL_1                  (0x2UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00002000 */
+#define RCC_CCIPR13_UART4SEL_2                  (0x4UL << RCC_CCIPR13_UART4SEL_Pos)             /*!< 0x00004000 */
+#define RCC_CCIPR13_UART5SEL_Pos                (16U)
+#define RCC_CCIPR13_UART5SEL_Msk                (0x7UL << RCC_CCIPR13_UART5SEL_Pos)                /*!< 0x00070000 */
+#define RCC_CCIPR13_UART5SEL                    RCC_CCIPR13_UART5SEL_Msk                          /*!< Source selection for the UART5 kernel clock */
+#define RCC_CCIPR13_UART5SEL_0                  (0x1UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00010000 */
+#define RCC_CCIPR13_UART5SEL_1                  (0x2UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00020000 */
+#define RCC_CCIPR13_UART5SEL_2                  (0x4UL << RCC_CCIPR13_UART5SEL_Pos)            /*!< 0x00040000 */
+#define RCC_CCIPR13_USART6SEL_Pos               (20U)
+#define RCC_CCIPR13_USART6SEL_Msk               (0x7UL << RCC_CCIPR13_USART6SEL_Pos)               /*!< 0x00700000 */
+#define RCC_CCIPR13_USART6SEL                   RCC_CCIPR13_USART6SEL_Msk                         /*!< Source selection for the USART6 kernel clock */
+#define RCC_CCIPR13_USART6SEL_0                 (0x1UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00100000 */
+#define RCC_CCIPR13_USART6SEL_1                 (0x2UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00200000 */
+#define RCC_CCIPR13_USART6SEL_2                 (0x4UL << RCC_CCIPR13_USART6SEL_Pos)          /*!< 0x00400000 */
+#define RCC_CCIPR13_UART7SEL_Pos                (24U)
+#define RCC_CCIPR13_UART7SEL_Msk                (0x7UL << RCC_CCIPR13_UART7SEL_Pos)                /*!< 0x07000000 */
+#define RCC_CCIPR13_UART7SEL                    RCC_CCIPR13_UART7SEL_Msk                          /*!< Source selection for the UART7 kernel clock */
+#define RCC_CCIPR13_UART7SEL_0                  (0x1UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x01000000 */
+#define RCC_CCIPR13_UART7SEL_1                  (0x2UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x02000000 */
+#define RCC_CCIPR13_UART7SEL_2                  (0x4UL << RCC_CCIPR13_UART7SEL_Pos)          /*!< 0x04000000 */
+#define RCC_CCIPR13_UART8SEL_Pos                (28U)
+#define RCC_CCIPR13_UART8SEL_Msk                (0x7UL << RCC_CCIPR13_UART8SEL_Pos)                /*!< 0x70000000 */
+#define RCC_CCIPR13_UART8SEL                    RCC_CCIPR13_UART8SEL_Msk                          /*!< Source selection for the UART8 kernel clock */
+#define RCC_CCIPR13_UART8SEL_0                  (0x1UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x10000000 */
+#define RCC_CCIPR13_UART8SEL_1                  (0x2UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x20000000 */
+#define RCC_CCIPR13_UART8SEL_2                  (0x4UL << RCC_CCIPR13_UART8SEL_Pos)         /*!< 0x40000000 */
+
+/*****************  Bit definition for RCC_CCIPR14 register  ******************/
+#define RCC_CCIPR14_UART9SEL_Pos                (0U)
+#define RCC_CCIPR14_UART9SEL_Msk                (0x7UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000007 */
+#define RCC_CCIPR14_UART9SEL                    RCC_CCIPR14_UART9SEL_Msk                          /*!< Source selection for the UART9 kernel clock */
+#define RCC_CCIPR14_UART9SEL_0                  (0x1UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000001 */
+#define RCC_CCIPR14_UART9SEL_1                  (0x2UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000002 */
+#define RCC_CCIPR14_UART9SEL_2                  (0x4UL << RCC_CCIPR14_UART9SEL_Pos)                /*!< 0x00000004 */
+#define RCC_CCIPR14_USART10SEL_Pos              (4U)
+#define RCC_CCIPR14_USART10SEL_Msk              (0x7UL << RCC_CCIPR14_USART10SEL_Pos)              /*!< 0x00000070 */
+#define RCC_CCIPR14_USART10SEL                  RCC_CCIPR14_USART10SEL_Msk                        /*!< Source selection for the USART10 kernel clock */
+#define RCC_CCIPR14_USART10SEL_0                (0x1UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000010 */
+#define RCC_CCIPR14_USART10SEL_1                (0x2UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000020 */
+#define RCC_CCIPR14_USART10SEL_2                (0x4UL << RCC_CCIPR14_USART10SEL_Pos)             /*!< 0x00000040 */
+#define RCC_CCIPR14_LPUART1SEL_Pos              (8U)
+#define RCC_CCIPR14_LPUART1SEL_Msk              (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos)              /*!< 0x00000700 */
+#define RCC_CCIPR14_LPUART1SEL                  RCC_CCIPR14_LPUART1SEL_Msk                        /*!< Source selection for the LPUART1 kernel clock */
+#define RCC_CCIPR14_LPUART1SEL_0                (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000100 */
+#define RCC_CCIPR14_LPUART1SEL_1                (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000200 */
+#define RCC_CCIPR14_LPUART1SEL_2                (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos)            /*!< 0x00000400 */
+
+/*****************  Bit definition for RCC_MISCRSTR register  *****************/
+#define RCC_MISCRSTR_DBGRST_Pos                 (0U)
+#define RCC_MISCRSTR_DBGRST_Msk                 (0x1UL << RCC_MISCRSTR_DBGRST_Pos)    /*!< 0x00000001 */
+#define RCC_MISCRSTR_DBGRST                     RCC_MISCRSTR_DBGRST_Msk              /*!< DBG reset */
+#define RCC_MISCRSTR_XSPIPHY1RST_Pos            (4U)
+#define RCC_MISCRSTR_XSPIPHY1RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */
+#define RCC_MISCRSTR_XSPIPHY1RST                RCC_MISCRSTR_XSPIPHY1RST_Msk         /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTR_XSPIPHY2RST_Pos            (5U)
+#define RCC_MISCRSTR_XSPIPHY2RST_Msk            (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */
+#define RCC_MISCRSTR_XSPIPHY2RST                RCC_MISCRSTR_XSPIPHY2RST_Msk         /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTR_SDMMC1DLLRST_Pos           (7U)
+#define RCC_MISCRSTR_SDMMC1DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos)  /*!< 0x00000080 */
+#define RCC_MISCRSTR_SDMMC1DLLRST               RCC_MISCRSTR_SDMMC1DLLRST_Msk        /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTR_SDMMC2DLLRST_Pos           (8U)
+#define RCC_MISCRSTR_SDMMC2DLLRST_Msk           (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos)  /*!< 0x00000100 */
+#define RCC_MISCRSTR_SDMMC2DLLRST               RCC_MISCRSTR_SDMMC2DLLRST_Msk        /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTR register  ******************/
+#define RCC_MEMRSTR_AXISRAM3RST_Pos             (0U)
+#define RCC_MEMRSTR_AXISRAM3RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */
+#define RCC_MEMRSTR_AXISRAM3RST                 RCC_MEMRSTR_AXISRAM3RST_Msk          /*!< AXISRAM3 reset */
+#define RCC_MEMRSTR_AXISRAM4RST_Pos             (1U)
+#define RCC_MEMRSTR_AXISRAM4RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */
+#define RCC_MEMRSTR_AXISRAM4RST                 RCC_MEMRSTR_AXISRAM4RST_Msk          /*!< AXISRAM4 reset */
+#define RCC_MEMRSTR_AXISRAM5RST_Pos             (2U)
+#define RCC_MEMRSTR_AXISRAM5RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */
+#define RCC_MEMRSTR_AXISRAM5RST                 RCC_MEMRSTR_AXISRAM5RST_Msk          /*!< AXISRAM5 reset */
+#define RCC_MEMRSTR_AXISRAM6RST_Pos             (3U)
+#define RCC_MEMRSTR_AXISRAM6RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */
+#define RCC_MEMRSTR_AXISRAM6RST                 RCC_MEMRSTR_AXISRAM6RST_Msk          /*!< AXISRAM6 reset */
+#define RCC_MEMRSTR_AHBSRAM1RST_Pos             (4U)
+#define RCC_MEMRSTR_AHBSRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */
+#define RCC_MEMRSTR_AHBSRAM1RST                 RCC_MEMRSTR_AHBSRAM1RST_Msk          /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTR_AHBSRAM2RST_Pos             (5U)
+#define RCC_MEMRSTR_AHBSRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */
+#define RCC_MEMRSTR_AHBSRAM2RST                 RCC_MEMRSTR_AHBSRAM2RST_Msk          /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTR_AXISRAM1RST_Pos             (7U)
+#define RCC_MEMRSTR_AXISRAM1RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */
+#define RCC_MEMRSTR_AXISRAM1RST                 RCC_MEMRSTR_AXISRAM1RST_Msk          /*!< AXISRAM1 reset */
+#define RCC_MEMRSTR_AXISRAM2RST_Pos             (8U)
+#define RCC_MEMRSTR_AXISRAM2RST_Msk             (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */
+#define RCC_MEMRSTR_AXISRAM2RST                 RCC_MEMRSTR_AXISRAM2RST_Msk          /*!< AXISRAM2 reset */
+#define RCC_MEMRSTR_FLEXRAMRST_Pos              (9U)
+#define RCC_MEMRSTR_FLEXRAMRST_Msk              (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTR_FLEXRAMRST                  RCC_MEMRSTR_FLEXRAMRST_Msk           /*!< FLEXRAM reset */
+#define RCC_MEMRSTR_CACHEAXIRAMRST_Pos          (10U)
+#define RCC_MEMRSTR_CACHEAXIRAMRST_Msk          (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos)   /*!< 0x00000400 */
+#define RCC_MEMRSTR_CACHEAXIRAMRST              RCC_MEMRSTR_CACHEAXIRAMRST_Msk       /*!< CACHEAXIRAM reset */
+#define RCC_MEMRSTR_VENCRAMRST_Pos              (11U)
+#define RCC_MEMRSTR_VENCRAMRST_Msk              (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTR_VENCRAMRST                  RCC_MEMRSTR_VENCRAMRST_Msk           /*!< VENCRAM reset */
+#define RCC_MEMRSTR_BOOTROMRST_Pos              (12U)
+#define RCC_MEMRSTR_BOOTROMRST_Msk              (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTR_BOOTROMRST                  RCC_MEMRSTR_BOOTROMRST_Msk           /*!< Boot ROM reset */
+
+/*****************  Bit definition for RCC_AHB1RSTR register  *****************/
+#define RCC_AHB1RSTR_GPDMA1RST_Pos              (4U)
+#define RCC_AHB1RSTR_GPDMA1RST_Msk              (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPDMA1RST                  RCC_AHB1RSTR_GPDMA1RST_Msk           /*!< GPDMA1 reset */
+#define RCC_AHB1RSTR_ADC12RST_Pos               (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk               (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                   RCC_AHB1RSTR_ADC12RST_Msk            /*!< ADC12 reset */
+
+/*****************  Bit definition for RCC_AHB2RSTR register  *****************/
+#define RCC_AHB2RSTR_RAMCFGRST_Pos              (12U)
+#define RCC_AHB2RSTR_RAMCFGRST_Msk              (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_RAMCFGRST                  RCC_AHB2RSTR_RAMCFGRST_Msk           /*!< RAMCFG reset */
+#define RCC_AHB2RSTR_MDF1RST_Pos                (16U)
+#define RCC_AHB2RSTR_MDF1RST_Msk                (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2RSTR_MDF1RST                    RCC_AHB2RSTR_MDF1RST_Msk             /*!< MDF1 reset */
+#define RCC_AHB2RSTR_ADF1RST_Pos                (17U)
+#define RCC_AHB2RSTR_ADF1RST_Msk                (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2RSTR_ADF1RST                    RCC_AHB2RSTR_ADF1RST_Msk             /*!< ADF1 reset */
+
+/*****************  Bit definition for RCC_AHB3RSTR register  *****************/
+#define RCC_AHB3RSTR_RNGRST_Pos                 (0U)
+#define RCC_AHB3RSTR_RNGRST_Msk                 (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3RSTR_RNGRST                     RCC_AHB3RSTR_RNGRST_Msk              /*!< RNG reset */
+#define RCC_AHB3RSTR_HASHRST_Pos                (1U)
+#define RCC_AHB3RSTR_HASHRST_Msk                (0x1UL << RCC_AHB3RSTR_HASHRST_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3RSTR_HASHRST                    RCC_AHB3RSTR_HASHRST_Msk             /*!< HASH reset */
+#define RCC_AHB3RSTR_CRYPRST_Pos                (2U)
+#define RCC_AHB3RSTR_CRYPRST_Msk                (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos)   /*!< 0x00000004 */
+#define RCC_AHB3RSTR_CRYPRST                    RCC_AHB3RSTR_CRYPRST_Msk             /*!< CRYP reset */
+#define RCC_AHB3RSTR_SAESRST_Pos                (4U)
+#define RCC_AHB3RSTR_SAESRST_Msk                (0x1UL << RCC_AHB3RSTR_SAESRST_Pos)   /*!< 0x00000010 */
+#define RCC_AHB3RSTR_SAESRST                    RCC_AHB3RSTR_SAESRST_Msk             /*!< SAES reset */
+#define RCC_AHB3RSTR_PKARST_Pos                 (8U)
+#define RCC_AHB3RSTR_PKARST_Msk                 (0x1UL << RCC_AHB3RSTR_PKARST_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3RSTR_PKARST                     RCC_AHB3RSTR_PKARST_Msk              /*!< PKA reset */
+#define RCC_AHB3RSTR_IACRST_Pos                 (10U)
+#define RCC_AHB3RSTR_IACRST_Msk                 (0x1UL << RCC_AHB3RSTR_IACRST_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3RSTR_IACRST                     RCC_AHB3RSTR_IACRST_Msk              /*!< IAC reset */
+
+/*****************  Bit definition for RCC_AHB4RSTR register  *****************/
+#define RCC_AHB4RSTR_GPIOARST_Pos               (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                   RCC_AHB4RSTR_GPIOARST_Msk            /*!< GPIO A reset */
+#define RCC_AHB4RSTR_GPIOBRST_Pos               (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                   RCC_AHB4RSTR_GPIOBRST_Msk            /*!< GPIO B reset */
+#define RCC_AHB4RSTR_GPIOCRST_Pos               (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                   RCC_AHB4RSTR_GPIOCRST_Msk            /*!< GPIO C reset */
+#define RCC_AHB4RSTR_GPIODRST_Pos               (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                   RCC_AHB4RSTR_GPIODRST_Msk            /*!< GPIO D reset */
+#define RCC_AHB4RSTR_GPIOERST_Pos               (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                   RCC_AHB4RSTR_GPIOERST_Msk            /*!< GPIO E reset */
+#define RCC_AHB4RSTR_GPIOFRST_Pos               (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                   RCC_AHB4RSTR_GPIOFRST_Msk            /*!< GPIO F reset */
+#define RCC_AHB4RSTR_GPIOGRST_Pos               (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                   RCC_AHB4RSTR_GPIOGRST_Msk            /*!< GPIO G reset */
+#define RCC_AHB4RSTR_GPIOHRST_Pos               (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                   RCC_AHB4RSTR_GPIOHRST_Msk            /*!< GPIO H reset */
+#define RCC_AHB4RSTR_GPIONRST_Pos               (13U)
+#define RCC_AHB4RSTR_GPIONRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4RSTR_GPIONRST                   RCC_AHB4RSTR_GPIONRST_Msk            /*!< GPIO N reset */
+#define RCC_AHB4RSTR_GPIOORST_Pos               (14U)
+#define RCC_AHB4RSTR_GPIOORST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4RSTR_GPIOORST                   RCC_AHB4RSTR_GPIOORST_Msk            /*!< GPIO O reset */
+#define RCC_AHB4RSTR_GPIOPRST_Pos               (15U)
+#define RCC_AHB4RSTR_GPIOPRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4RSTR_GPIOPRST                   RCC_AHB4RSTR_GPIOPRST_Msk            /*!< GPIO P reset */
+#define RCC_AHB4RSTR_GPIOQRST_Pos               (16U)
+#define RCC_AHB4RSTR_GPIOQRST_Msk               (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4RSTR_GPIOQRST                   RCC_AHB4RSTR_GPIOQRST_Msk            /*!< GPIO Q reset */
+#define RCC_AHB4RSTR_PWRRST_Pos                 (18U)
+#define RCC_AHB4RSTR_PWRRST_Msk                 (0x1UL << RCC_AHB4RSTR_PWRRST_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4RSTR_PWRRST                     RCC_AHB4RSTR_PWRRST_Msk              /*!< PWR reset */
+#define RCC_AHB4RSTR_CRCRST_Pos                 (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                 (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                     RCC_AHB4RSTR_CRCRST_Msk              /*!< CRC reset */
+
+/*****************  Bit definition for RCC_AHB5RSTR register  *****************/
+#define RCC_AHB5RSTR_HPDMA1RST_Pos              (0U)
+#define RCC_AHB5RSTR_HPDMA1RST_Msk              (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTR_HPDMA1RST                  RCC_AHB5RSTR_HPDMA1RST_Msk           /*!< HPDMA1 reset */
+#define RCC_AHB5RSTR_DMA2DRST_Pos               (1U)
+#define RCC_AHB5RSTR_DMA2DRST_Msk               (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5RSTR_DMA2DRST                   RCC_AHB5RSTR_DMA2DRST_Msk            /*!< DMA2D reset */
+#define RCC_AHB5RSTR_JPEGRST_Pos                (3U)
+#define RCC_AHB5RSTR_JPEGRST_Msk                (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5RSTR_JPEGRST                    RCC_AHB5RSTR_JPEGRST_Msk             /*!< JPEG reset */
+#define RCC_AHB5RSTR_FMCRST_Pos                 (4U)
+#define RCC_AHB5RSTR_FMCRST_Msk                 (0x1UL << RCC_AHB5RSTR_FMCRST_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5RSTR_FMCRST                     RCC_AHB5RSTR_FMCRST_Msk              /*!< FMC reset */
+#define RCC_AHB5RSTR_XSPI1RST_Pos               (5U)
+#define RCC_AHB5RSTR_XSPI1RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5RSTR_XSPI1RST                   RCC_AHB5RSTR_XSPI1RST_Msk            /*!< XSPI1 reset */
+#define RCC_AHB5RSTR_PSSIRST_Pos                (6U)
+#define RCC_AHB5RSTR_PSSIRST_Msk                (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5RSTR_PSSIRST                    RCC_AHB5RSTR_PSSIRST_Msk             /*!< PSSI reset */
+#define RCC_AHB5RSTR_SDMMC2RST_Pos              (7U)
+#define RCC_AHB5RSTR_SDMMC2RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTR_SDMMC2RST                  RCC_AHB5RSTR_SDMMC2RST_Msk           /*!< SDMMC2 reset */
+#define RCC_AHB5RSTR_SDMMC1RST_Pos              (8U)
+#define RCC_AHB5RSTR_SDMMC1RST_Msk              (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTR_SDMMC1RST                  RCC_AHB5RSTR_SDMMC1RST_Msk           /*!< SDMMC1 reset */
+#define RCC_AHB5RSTR_XSPI2RST_Pos               (12U)
+#define RCC_AHB5RSTR_XSPI2RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5RSTR_XSPI2RST                   RCC_AHB5RSTR_XSPI2RST_Msk            /*!< XSPI2 reset */
+#define RCC_AHB5RSTR_XSPIMRST_Pos               (13U)
+#define RCC_AHB5RSTR_XSPIMRST_Msk               (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5RSTR_XSPIMRST                   RCC_AHB5RSTR_XSPIMRST_Msk            /*!< XSPIM reset */
+#define RCC_AHB5RSTR_XSPI3RST_Pos               (17U)
+#define RCC_AHB5RSTR_XSPI3RST_Msk               (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5RSTR_XSPI3RST                   RCC_AHB5RSTR_XSPI3RST_Msk            /*!< XSPI3 reset */
+#define RCC_AHB5RSTR_GFXMMURST_Pos              (19U)
+#define RCC_AHB5RSTR_GFXMMURST_Msk              (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTR_GFXMMURST                  RCC_AHB5RSTR_GFXMMURST_Msk           /*!< GFXMMU reset */
+#define RCC_AHB5RSTR_GPU2DRST_Pos               (20U)
+#define RCC_AHB5RSTR_GPU2DRST_Msk               (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5RSTR_GPU2DRST                   RCC_AHB5RSTR_GPU2DRST_Msk            /*!< GPU2D reset */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos          (23U)
+#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5RSTR_OTG1PHYCTLRST              RCC_AHB5RSTR_OTG1PHYCTLRST_Msk       /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos          (24U)
+#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk          (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5RSTR_OTG2PHYCTLRST              RCC_AHB5RSTR_OTG2PHYCTLRST_Msk       /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTR_ETH1RST_Pos                (25U)
+#define RCC_AHB5RSTR_ETH1RST_Msk                (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5RSTR_ETH1RST                    RCC_AHB5RSTR_ETH1RST_Msk             /*!< ETH1 reset */
+#define RCC_AHB5RSTR_OTG1RST_Pos                (26U)
+#define RCC_AHB5RSTR_OTG1RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5RSTR_OTG1RST                    RCC_AHB5RSTR_OTG1RST_Msk             /*!< OTG1 reset */
+#define RCC_AHB5RSTR_OTGPHY1RST_Pos             (27U)
+#define RCC_AHB5RSTR_OTGPHY1RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */
+#define RCC_AHB5RSTR_OTGPHY1RST                 RCC_AHB5RSTR_OTGPHY1RST_Msk          /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTR_OTGPHY2RST_Pos             (28U)
+#define RCC_AHB5RSTR_OTGPHY2RST_Msk             (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */
+#define RCC_AHB5RSTR_OTGPHY2RST                 RCC_AHB5RSTR_OTGPHY2RST_Msk          /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTR_OTG2RST_Pos                (29U)
+#define RCC_AHB5RSTR_OTG2RST_Msk                (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5RSTR_OTG2RST                    RCC_AHB5RSTR_OTG2RST_Msk             /*!< OTG2 reset */
+#define RCC_AHB5RSTR_CACHEAXIRST_Pos            (30U)
+#define RCC_AHB5RSTR_CACHEAXIRST_Msk            (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */
+#define RCC_AHB5RSTR_CACHEAXIRST                RCC_AHB5RSTR_CACHEAXIRST_Msk         /*!< CACHEAXI reset */
+#define RCC_AHB5RSTR_NPURST_Pos                 (31U)
+#define RCC_AHB5RSTR_NPURST_Msk                 (0x1UL << RCC_AHB5RSTR_NPURST_Pos)    /*!< 0x80000000 */
+#define RCC_AHB5RSTR_NPURST                     RCC_AHB5RSTR_NPURST_Msk              /*!< NPU reset */
+
+/****************  Bit definition for RCC_APB1RSTR1 register  *****************/
+#define RCC_APB1RSTR1_TIM2RST_Pos               (0U)
+#define RCC_APB1RSTR1_TIM2RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                   RCC_APB1RSTR1_TIM2RST_Msk            /*!< TIM2 reset */
+#define RCC_APB1RSTR1_TIM3RST_Pos               (1U)
+#define RCC_APB1RSTR1_TIM3RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                   RCC_APB1RSTR1_TIM3RST_Msk            /*!< TIM3 reset */
+#define RCC_APB1RSTR1_TIM4RST_Pos               (2U)
+#define RCC_APB1RSTR1_TIM4RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)  /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                   RCC_APB1RSTR1_TIM4RST_Msk            /*!< TIM4 reset */
+#define RCC_APB1RSTR1_TIM5RST_Pos               (3U)
+#define RCC_APB1RSTR1_TIM5RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)  /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                   RCC_APB1RSTR1_TIM5RST_Msk            /*!< TIM5 reset */
+#define RCC_APB1RSTR1_TIM6RST_Pos               (4U)
+#define RCC_APB1RSTR1_TIM6RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)  /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                   RCC_APB1RSTR1_TIM6RST_Msk            /*!< TIM6 reset */
+#define RCC_APB1RSTR1_TIM7RST_Pos               (5U)
+#define RCC_APB1RSTR1_TIM7RST_Msk               (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                   RCC_APB1RSTR1_TIM7RST_Msk            /*!< TIM7 reset */
+#define RCC_APB1RSTR1_TIM12RST_Pos              (6U)
+#define RCC_APB1RSTR1_TIM12RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR1_TIM12RST                  RCC_APB1RSTR1_TIM12RST_Msk           /*!< TIM12 reset */
+#define RCC_APB1RSTR1_TIM13RST_Pos              (7U)
+#define RCC_APB1RSTR1_TIM13RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR1_TIM13RST                  RCC_APB1RSTR1_TIM13RST_Msk           /*!< TIM13 reset */
+#define RCC_APB1RSTR1_TIM14RST_Pos              (8U)
+#define RCC_APB1RSTR1_TIM14RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR1_TIM14RST                  RCC_APB1RSTR1_TIM14RST_Msk           /*!< TIM14 reset */
+#define RCC_APB1RSTR1_LPTIM1RST_Pos             (9U)
+#define RCC_APB1RSTR1_LPTIM1RST_Msk             (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */
+#define RCC_APB1RSTR1_LPTIM1RST                 RCC_APB1RSTR1_LPTIM1RST_Msk          /*!< LPTIM1 reset */
+#define RCC_APB1RSTR1_WWDGRST_Pos               (11U)
+#define RCC_APB1RSTR1_WWDGRST_Msk               (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos)  /*!< 0x00000800 */
+#define RCC_APB1RSTR1_WWDGRST                   RCC_APB1RSTR1_WWDGRST_Msk            /*!< WWDG reset */
+#define RCC_APB1RSTR1_TIM10RST_Pos              (12U)
+#define RCC_APB1RSTR1_TIM10RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTR1_TIM10RST                  RCC_APB1RSTR1_TIM10RST_Msk           /*!< TIM10 reset */
+#define RCC_APB1RSTR1_TIM11RST_Pos              (13U)
+#define RCC_APB1RSTR1_TIM11RST_Msk              (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTR1_TIM11RST                  RCC_APB1RSTR1_TIM11RST_Msk           /*!< TIM11 reset */
+#define RCC_APB1RSTR1_SPI2RST_Pos               (14U)
+#define RCC_APB1RSTR1_SPI2RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                   RCC_APB1RSTR1_SPI2RST_Msk            /*!< SPI2 reset */
+#define RCC_APB1RSTR1_SPI3RST_Pos               (15U)
+#define RCC_APB1RSTR1_SPI3RST_Msk               (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                   RCC_APB1RSTR1_SPI3RST_Msk            /*!< SPI3 reset */
+#define RCC_APB1RSTR1_SPDIFRX1RST_Pos           (16U)
+#define RCC_APB1RSTR1_SPDIFRX1RST_Msk           (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB1RSTR1_SPDIFRX1RST               RCC_APB1RSTR1_SPDIFRX1RST_Msk        /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTR1_USART2RST_Pos             (17U)
+#define RCC_APB1RSTR1_USART2RST_Msk             (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST                 RCC_APB1RSTR1_USART2RST_Msk          /*!< USART2 reset */
+#define RCC_APB1RSTR1_USART3RST_Pos             (18U)
+#define RCC_APB1RSTR1_USART3RST_Msk             (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST                 RCC_APB1RSTR1_USART3RST_Msk          /*!< USART3 reset */
+#define RCC_APB1RSTR1_UART4RST_Pos              (19U)
+#define RCC_APB1RSTR1_UART4RST_Msk              (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST                  RCC_APB1RSTR1_UART4RST_Msk           /*!< UART4 reset */
+#define RCC_APB1RSTR1_UART5RST_Pos              (20U)
+#define RCC_APB1RSTR1_UART5RST_Msk              (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST                  RCC_APB1RSTR1_UART5RST_Msk           /*!< UART5 reset */
+#define RCC_APB1RSTR1_I2C1RST_Pos               (21U)
+#define RCC_APB1RSTR1_I2C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                   RCC_APB1RSTR1_I2C1RST_Msk            /*!< I2C1 reset */
+#define RCC_APB1RSTR1_I2C2RST_Pos               (22U)
+#define RCC_APB1RSTR1_I2C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                   RCC_APB1RSTR1_I2C2RST_Msk            /*!< I2C2 reset */
+#define RCC_APB1RSTR1_I2C3RST_Pos               (23U)
+#define RCC_APB1RSTR1_I2C3RST_Msk               (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                   RCC_APB1RSTR1_I2C3RST_Msk            /*!< I2C3 reset */
+#define RCC_APB1RSTR1_I3C1RST_Pos               (24U)
+#define RCC_APB1RSTR1_I3C1RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos)  /*!< 0x01000000 */
+#define RCC_APB1RSTR1_I3C1RST                   RCC_APB1RSTR1_I3C1RST_Msk            /*!< I3C1 reset */
+#define RCC_APB1RSTR1_I3C2RST_Pos               (25U)
+#define RCC_APB1RSTR1_I3C2RST_Msk               (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos)  /*!< 0x02000000 */
+#define RCC_APB1RSTR1_I3C2RST                   RCC_APB1RSTR1_I3C2RST_Msk            /*!< I3C2 reset */
+#define RCC_APB1RSTR1_UART7RST_Pos              (30U)
+#define RCC_APB1RSTR1_UART7RST_Msk              (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_UART7RST                  RCC_APB1RSTR1_UART7RST_Msk           /*!< UART7 reset */
+#define RCC_APB1RSTR1_UART8RST_Pos              (31U)
+#define RCC_APB1RSTR1_UART8RST_Msk              (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_UART8RST                  RCC_APB1RSTR1_UART8RST_Msk           /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTR2 register  *****************/
+#define RCC_APB1RSTR2_MDIOSRST_Pos              (5U)
+#define RCC_APB1RSTR2_MDIOSRST_Msk              (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_MDIOSRST                  RCC_APB1RSTR2_MDIOSRST_Msk            /*!< MDIOS reset */
+#define RCC_APB1RSTR2_FDCANRST_Pos              (8U)
+#define RCC_APB1RSTR2_FDCANRST_Msk              (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR2_FDCANRST                  RCC_APB1RSTR2_FDCANRST_Msk            /*!< FDCAN reset */
+#define RCC_APB1RSTR2_UCPD1RST_Pos              (18U)
+#define RCC_APB1RSTR2_UCPD1RST_Msk              (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR2_UCPD1RST                  RCC_APB1RSTR2_UCPD1RST_Msk            /*!< UCPD1 reset */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define RCC_APB2RSTR_TIM1RST_Pos                (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk                (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)   /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                    RCC_APB2RSTR_TIM1RST_Msk             /*!< TIM1 reset */
+#define RCC_APB2RSTR_TIM8RST_Pos                (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk                (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)   /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                    RCC_APB2RSTR_TIM8RST_Msk             /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST_Pos              (4U)
+#define RCC_APB2RSTR_USART1RST_Msk              (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                  RCC_APB2RSTR_USART1RST_Msk           /*!< USART1 reset */
+#define RCC_APB2RSTR_USART6RST_Pos              (5U)
+#define RCC_APB2RSTR_USART6RST_Msk              (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                  RCC_APB2RSTR_USART6RST_Msk           /*!< USART6 reset */
+#define RCC_APB2RSTR_UART9RST_Pos               (6U)
+#define RCC_APB2RSTR_UART9RST_Msk               (0x1UL << RCC_APB2RSTR_UART9RST_Pos)  /*!< 0x00000040 */
+#define RCC_APB2RSTR_UART9RST                   RCC_APB2RSTR_UART9RST_Msk            /*!< UART9 reset */
+#define RCC_APB2RSTR_USART10RST_Pos             (7U)
+#define RCC_APB2RSTR_USART10RST_Msk             (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */
+#define RCC_APB2RSTR_USART10RST                 RCC_APB2RSTR_USART10RST_Msk          /*!< USART10 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos                (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk                (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)   /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                    RCC_APB2RSTR_SPI1RST_Msk             /*!< SPI1 reset */
+#define RCC_APB2RSTR_SPI4RST_Pos                (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk                (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)   /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                    RCC_APB2RSTR_SPI4RST_Msk             /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM18RST_Pos               (15U)
+#define RCC_APB2RSTR_TIM18RST_Msk               (0x1UL << RCC_APB2RSTR_TIM18RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB2RSTR_TIM18RST                   RCC_APB2RSTR_TIM18RST_Msk            /*!< TIM18 reset */
+#define RCC_APB2RSTR_TIM15RST_Pos               (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk               (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                   RCC_APB2RSTR_TIM15RST_Msk            /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST_Pos               (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk               (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)  /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                   RCC_APB2RSTR_TIM16RST_Msk            /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST_Pos               (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk               (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)  /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                   RCC_APB2RSTR_TIM17RST_Msk            /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM9RST_Pos                (19U)
+#define RCC_APB2RSTR_TIM9RST_Msk                (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)   /*!< 0x00080000 */
+#define RCC_APB2RSTR_TIM9RST                    RCC_APB2RSTR_TIM9RST_Msk             /*!< TIM9 reset */
+#define RCC_APB2RSTR_SPI5RST_Pos                (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk                (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)   /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                    RCC_APB2RSTR_SPI5RST_Msk             /*!< SPI5 reset */
+#define RCC_APB2RSTR_SAI1RST_Pos                (21U)
+#define RCC_APB2RSTR_SAI1RST_Msk                (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)   /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                    RCC_APB2RSTR_SAI1RST_Msk             /*!< SAI1 reset */
+#define RCC_APB2RSTR_SAI2RST_Pos                (22U)
+#define RCC_APB2RSTR_SAI2RST_Msk                (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)   /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                    RCC_APB2RSTR_SAI2RST_Msk             /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTR1 register  *****************/
+#define RCC_APB4RSTR1_HDPRST_Pos                (2U)
+#define RCC_APB4RSTR1_HDPRST_Msk                (0x1UL << RCC_APB4RSTR1_HDPRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR1_HDPRST                    RCC_APB4RSTR1_HDPRST_Msk             /*!< HDP reset */
+#define RCC_APB4RSTR1_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR1_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR1_LPUART1RST                RCC_APB4RSTR1_LPUART1RST_Msk         /*!< LPUART1 reset */
+#define RCC_APB4RSTR1_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR1_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB4RSTR1_SPI6RST                   RCC_APB4RSTR1_SPI6RST_Msk            /*!< SPI6 reset */
+#define RCC_APB4RSTR1_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR1_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos)  /*!< 0x00000080 */
+#define RCC_APB4RSTR1_I2C4RST                   RCC_APB4RSTR1_I2C4RST_Msk            /*!< I2C4 reset */
+#define RCC_APB4RSTR1_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR1_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */
+#define RCC_APB4RSTR1_LPTIM2RST                 RCC_APB4RSTR1_LPTIM2RST_Msk          /*!< LPTIM2 reset */
+#define RCC_APB4RSTR1_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR1_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */
+#define RCC_APB4RSTR1_LPTIM3RST                 RCC_APB4RSTR1_LPTIM3RST_Msk          /*!< LPTIM3 reset */
+#define RCC_APB4RSTR1_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR1_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */
+#define RCC_APB4RSTR1_LPTIM4RST                 RCC_APB4RSTR1_LPTIM4RST_Msk          /*!< LPTIM4 reset */
+#define RCC_APB4RSTR1_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR1_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */
+#define RCC_APB4RSTR1_LPTIM5RST                 RCC_APB4RSTR1_LPTIM5RST_Msk          /*!< LPTIM5 reset */
+#define RCC_APB4RSTR1_VREFBUFRST_Pos            (15U)
+#define RCC_APB4RSTR1_VREFBUFRST_Msk            (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR1_VREFBUFRST                RCC_APB4RSTR1_VREFBUFRST_Msk         /*!< VREFBUF reset */
+#define RCC_APB4RSTR1_RTCRST_Pos                (16U)
+#define RCC_APB4RSTR1_RTCRST_Msk                (0x1UL << RCC_APB4RSTR1_RTCRST_Pos)   /*!< 0x00010000 */
+#define RCC_APB4RSTR1_RTCRST                    RCC_APB4RSTR1_RTCRST_Msk             /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTR2 register  *****************/
+#define RCC_APB4RSTR2_SYSCFGRST_Pos             (0U)
+#define RCC_APB4RSTR2_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */
+#define RCC_APB4RSTR2_SYSCFGRST                 RCC_APB4RSTR2_SYSCFGRST_Msk          /*!< SYSCFG reset */
+#define RCC_APB4RSTR2_DTSRST_Pos                (2U)
+#define RCC_APB4RSTR2_DTSRST_Msk                (0x1UL << RCC_APB4RSTR2_DTSRST_Pos)   /*!< 0x00000004 */
+#define RCC_APB4RSTR2_DTSRST                    RCC_APB4RSTR2_DTSRST_Msk             /*!< DTS reset */
+
+/*****************  Bit definition for RCC_APB5RSTR register  *****************/
+#define RCC_APB5RSTR_LTDCRST_Pos                (1U)
+#define RCC_APB5RSTR_LTDCRST_Msk                (0x1UL << RCC_APB5RSTR_LTDCRST_Pos)   /*!< 0x00000002 */
+#define RCC_APB5RSTR_LTDCRST                    RCC_APB5RSTR_LTDCRST_Msk             /*!< LTDC reset */
+#define RCC_APB5RSTR_DCMIPPRST_Pos              (2U)
+#define RCC_APB5RSTR_DCMIPPRST_Msk              (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTR_DCMIPPRST                  RCC_APB5RSTR_DCMIPPRST_Msk           /*!< DCMIPP reset */
+#define RCC_APB5RSTR_GFXTIMRST_Pos              (4U)
+#define RCC_APB5RSTR_GFXTIMRST_Msk              (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTR_GFXTIMRST                  RCC_APB5RSTR_GFXTIMRST_Msk           /*!< GFXTIM reset */
+#define RCC_APB5RSTR_VENCRST_Pos                (5U)
+#define RCC_APB5RSTR_VENCRST_Msk                (0x1UL << RCC_APB5RSTR_VENCRST_Pos)   /*!< 0x00000020 */
+#define RCC_APB5RSTR_VENCRST                    RCC_APB5RSTR_VENCRST_Msk             /*!< VENC reset */
+#define RCC_APB5RSTR_CSIRST_Pos                 (6U)
+#define RCC_APB5RSTR_CSIRST_Msk                 (0x1UL << RCC_APB5RSTR_CSIRST_Pos)    /*!< 0x00000040 */
+#define RCC_APB5RSTR_CSIRST                     RCC_APB5RSTR_CSIRST_Msk              /*!< CSI reset */
+
+/******************  Bit definition for RCC_DIVENR register  ******************/
+#define RCC_DIVENR_IC1EN_Pos                    (0U)
+#define RCC_DIVENR_IC1EN_Msk                    (0x1UL << RCC_DIVENR_IC1EN_Pos)       /*!< 0x00000001 */
+#define RCC_DIVENR_IC1EN                        RCC_DIVENR_IC1EN_Msk                 /*!< IC1 enable */
+#define RCC_DIVENR_IC2EN_Pos                    (1U)
+#define RCC_DIVENR_IC2EN_Msk                    (0x1UL << RCC_DIVENR_IC2EN_Pos)       /*!< 0x00000002 */
+#define RCC_DIVENR_IC2EN                        RCC_DIVENR_IC2EN_Msk                 /*!< IC2 enable */
+#define RCC_DIVENR_IC3EN_Pos                    (2U)
+#define RCC_DIVENR_IC3EN_Msk                    (0x1UL << RCC_DIVENR_IC3EN_Pos)       /*!< 0x00000004 */
+#define RCC_DIVENR_IC3EN                        RCC_DIVENR_IC3EN_Msk                 /*!< IC3 enable */
+#define RCC_DIVENR_IC4EN_Pos                    (3U)
+#define RCC_DIVENR_IC4EN_Msk                    (0x1UL << RCC_DIVENR_IC4EN_Pos)       /*!< 0x00000008 */
+#define RCC_DIVENR_IC4EN                        RCC_DIVENR_IC4EN_Msk                 /*!< IC4 enable */
+#define RCC_DIVENR_IC5EN_Pos                    (4U)
+#define RCC_DIVENR_IC5EN_Msk                    (0x1UL << RCC_DIVENR_IC5EN_Pos)       /*!< 0x00000010 */
+#define RCC_DIVENR_IC5EN                        RCC_DIVENR_IC5EN_Msk                 /*!< IC5 enable */
+#define RCC_DIVENR_IC6EN_Pos                    (5U)
+#define RCC_DIVENR_IC6EN_Msk                    (0x1UL << RCC_DIVENR_IC6EN_Pos)       /*!< 0x00000020 */
+#define RCC_DIVENR_IC6EN                        RCC_DIVENR_IC6EN_Msk                 /*!< IC6 enable */
+#define RCC_DIVENR_IC7EN_Pos                    (6U)
+#define RCC_DIVENR_IC7EN_Msk                    (0x1UL << RCC_DIVENR_IC7EN_Pos)       /*!< 0x00000040 */
+#define RCC_DIVENR_IC7EN                        RCC_DIVENR_IC7EN_Msk                 /*!< IC7 enable */
+#define RCC_DIVENR_IC8EN_Pos                    (7U)
+#define RCC_DIVENR_IC8EN_Msk                    (0x1UL << RCC_DIVENR_IC8EN_Pos)       /*!< 0x00000080 */
+#define RCC_DIVENR_IC8EN                        RCC_DIVENR_IC8EN_Msk                 /*!< IC8 enable */
+#define RCC_DIVENR_IC9EN_Pos                    (8U)
+#define RCC_DIVENR_IC9EN_Msk                    (0x1UL << RCC_DIVENR_IC9EN_Pos)       /*!< 0x00000100 */
+#define RCC_DIVENR_IC9EN                        RCC_DIVENR_IC9EN_Msk                 /*!< IC9 enable */
+#define RCC_DIVENR_IC10EN_Pos                   (9U)
+#define RCC_DIVENR_IC10EN_Msk                   (0x1UL << RCC_DIVENR_IC10EN_Pos)      /*!< 0x00000200 */
+#define RCC_DIVENR_IC10EN                       RCC_DIVENR_IC10EN_Msk                /*!< IC10 enable */
+#define RCC_DIVENR_IC11EN_Pos                   (10U)
+#define RCC_DIVENR_IC11EN_Msk                   (0x1UL << RCC_DIVENR_IC11EN_Pos)      /*!< 0x00000400 */
+#define RCC_DIVENR_IC11EN                       RCC_DIVENR_IC11EN_Msk                /*!< IC11 enable */
+#define RCC_DIVENR_IC12EN_Pos                   (11U)
+#define RCC_DIVENR_IC12EN_Msk                   (0x1UL << RCC_DIVENR_IC12EN_Pos)      /*!< 0x00000800 */
+#define RCC_DIVENR_IC12EN                       RCC_DIVENR_IC12EN_Msk                /*!< IC12 enable */
+#define RCC_DIVENR_IC13EN_Pos                   (12U)
+#define RCC_DIVENR_IC13EN_Msk                   (0x1UL << RCC_DIVENR_IC13EN_Pos)      /*!< 0x00001000 */
+#define RCC_DIVENR_IC13EN                       RCC_DIVENR_IC13EN_Msk                /*!< IC13 enable */
+#define RCC_DIVENR_IC14EN_Pos                   (13U)
+#define RCC_DIVENR_IC14EN_Msk                   (0x1UL << RCC_DIVENR_IC14EN_Pos)      /*!< 0x00002000 */
+#define RCC_DIVENR_IC14EN                       RCC_DIVENR_IC14EN_Msk                /*!< IC14 enable */
+#define RCC_DIVENR_IC15EN_Pos                   (14U)
+#define RCC_DIVENR_IC15EN_Msk                   (0x1UL << RCC_DIVENR_IC15EN_Pos)      /*!< 0x00004000 */
+#define RCC_DIVENR_IC15EN                       RCC_DIVENR_IC15EN_Msk                /*!< IC15 enable */
+#define RCC_DIVENR_IC16EN_Pos                   (15U)
+#define RCC_DIVENR_IC16EN_Msk                   (0x1UL << RCC_DIVENR_IC16EN_Pos)      /*!< 0x00008000 */
+#define RCC_DIVENR_IC16EN                       RCC_DIVENR_IC16EN_Msk                /*!< IC16 enable */
+#define RCC_DIVENR_IC17EN_Pos                   (16U)
+#define RCC_DIVENR_IC17EN_Msk                   (0x1UL << RCC_DIVENR_IC17EN_Pos)      /*!< 0x00010000 */
+#define RCC_DIVENR_IC17EN                       RCC_DIVENR_IC17EN_Msk                /*!< IC17 enable */
+#define RCC_DIVENR_IC18EN_Pos                   (17U)
+#define RCC_DIVENR_IC18EN_Msk                   (0x1UL << RCC_DIVENR_IC18EN_Pos)      /*!< 0x00020000 */
+#define RCC_DIVENR_IC18EN                       RCC_DIVENR_IC18EN_Msk                /*!< IC18 enable */
+#define RCC_DIVENR_IC19EN_Pos                   (18U)
+#define RCC_DIVENR_IC19EN_Msk                   (0x1UL << RCC_DIVENR_IC19EN_Pos)      /*!< 0x00040000 */
+#define RCC_DIVENR_IC19EN                       RCC_DIVENR_IC19EN_Msk                /*!< IC19 enable */
+#define RCC_DIVENR_IC20EN_Pos                   (19U)
+#define RCC_DIVENR_IC20EN_Msk                   (0x1UL << RCC_DIVENR_IC20EN_Pos)      /*!< 0x00080000 */
+#define RCC_DIVENR_IC20EN                       RCC_DIVENR_IC20EN_Msk                /*!< IC20 enable */
+
+/******************  Bit definition for RCC_BUSENR register  ******************/
+#define RCC_BUSENR_ACLKNEN_Pos                  (0U)
+#define RCC_BUSENR_ACLKNEN_Msk                  (0x1UL << RCC_BUSENR_ACLKNEN_Pos)     /*!< 0x00000001 */
+#define RCC_BUSENR_ACLKNEN                      RCC_BUSENR_ACLKNEN_Msk               /*!< ACLKN enable */
+#define RCC_BUSENR_ACLKNCEN_Pos                 (1U)
+#define RCC_BUSENR_ACLKNCEN_Msk                 (0x1UL << RCC_BUSENR_ACLKNCEN_Pos)    /*!< 0x00000002 */
+#define RCC_BUSENR_ACLKNCEN                     RCC_BUSENR_ACLKNCEN_Msk              /*!< ACLKNC enable */
+#define RCC_BUSENR_AHBMEN_Pos                   (2U)
+#define RCC_BUSENR_AHBMEN_Msk                   (0x1UL << RCC_BUSENR_AHBMEN_Pos)      /*!< 0x00000004 */
+#define RCC_BUSENR_AHBMEN                       RCC_BUSENR_AHBMEN_Msk                /*!< AHBM enable */
+#define RCC_BUSENR_AHB1EN_Pos                   (3U)
+#define RCC_BUSENR_AHB1EN_Msk                   (0x1UL << RCC_BUSENR_AHB1EN_Pos)      /*!< 0x00000008 */
+#define RCC_BUSENR_AHB1EN                       RCC_BUSENR_AHB1EN_Msk                /*!< AHB1 enable */
+#define RCC_BUSENR_AHB2EN_Pos                   (4U)
+#define RCC_BUSENR_AHB2EN_Msk                   (0x1UL << RCC_BUSENR_AHB2EN_Pos)      /*!< 0x00000010 */
+#define RCC_BUSENR_AHB2EN                       RCC_BUSENR_AHB2EN_Msk                /*!< AHB2 enable */
+#define RCC_BUSENR_AHB3EN_Pos                   (5U)
+#define RCC_BUSENR_AHB3EN_Msk                   (0x1UL << RCC_BUSENR_AHB3EN_Pos)      /*!< 0x00000020 */
+#define RCC_BUSENR_AHB3EN                       RCC_BUSENR_AHB3EN_Msk                /*!< AHB3 enable */
+#define RCC_BUSENR_AHB4EN_Pos                   (6U)
+#define RCC_BUSENR_AHB4EN_Msk                   (0x1UL << RCC_BUSENR_AHB4EN_Pos)      /*!< 0x00000040 */
+#define RCC_BUSENR_AHB4EN                       RCC_BUSENR_AHB4EN_Msk                /*!< AHB4 enable */
+#define RCC_BUSENR_AHB5EN_Pos                   (7U)
+#define RCC_BUSENR_AHB5EN_Msk                   (0x1UL << RCC_BUSENR_AHB5EN_Pos)      /*!< 0x00000080 */
+#define RCC_BUSENR_AHB5EN                       RCC_BUSENR_AHB5EN_Msk                /*!< AHB5 enable */
+#define RCC_BUSENR_APB1EN_Pos                   (8U)
+#define RCC_BUSENR_APB1EN_Msk                   (0x1UL << RCC_BUSENR_APB1EN_Pos)      /*!< 0x00000100 */
+#define RCC_BUSENR_APB1EN                       RCC_BUSENR_APB1EN_Msk                /*!< APB1 enable */
+#define RCC_BUSENR_APB2EN_Pos                   (9U)
+#define RCC_BUSENR_APB2EN_Msk                   (0x1UL << RCC_BUSENR_APB2EN_Pos)      /*!< 0x00000200 */
+#define RCC_BUSENR_APB2EN                       RCC_BUSENR_APB2EN_Msk                /*!< APB2 enable */
+#define RCC_BUSENR_APB3EN_Pos                   (10U)
+#define RCC_BUSENR_APB3EN_Msk                   (0x1UL << RCC_BUSENR_APB3EN_Pos)      /*!< 0x00000400 */
+#define RCC_BUSENR_APB3EN                       RCC_BUSENR_APB3EN_Msk                /*!< APB3 enable */
+#define RCC_BUSENR_APB4EN_Pos                   (11U)
+#define RCC_BUSENR_APB4EN_Msk                   (0x1UL << RCC_BUSENR_APB4EN_Pos)      /*!< 0x00000800 */
+#define RCC_BUSENR_APB4EN                       RCC_BUSENR_APB4EN_Msk                /*!< APB4 enable */
+#define RCC_BUSENR_APB5EN_Pos                   (12U)
+#define RCC_BUSENR_APB5EN_Msk                   (0x1UL << RCC_BUSENR_APB5EN_Pos)      /*!< 0x00001000 */
+#define RCC_BUSENR_APB5EN                       RCC_BUSENR_APB5EN_Msk                /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENR register  ******************/
+#define RCC_MISCENR_DBGEN_Pos                   (0U)
+#define RCC_MISCENR_DBGEN_Msk                   (0x1UL << RCC_MISCENR_DBGEN_Pos)      /*!< 0x00000001 */
+#define RCC_MISCENR_DBGEN                       RCC_MISCENR_DBGEN_Msk                /*!< DBG enable */
+#define RCC_MISCENR_MCO1EN_Pos                  (1U)
+#define RCC_MISCENR_MCO1EN_Msk                  (0x1UL << RCC_MISCENR_MCO1EN_Pos)     /*!< 0x00000002 */
+#define RCC_MISCENR_MCO1EN                      RCC_MISCENR_MCO1EN_Msk               /*!< MCO1 enable */
+#define RCC_MISCENR_MCO2EN_Pos                  (2U)
+#define RCC_MISCENR_MCO2EN_Msk                  (0x1UL << RCC_MISCENR_MCO2EN_Pos)     /*!< 0x00000004 */
+#define RCC_MISCENR_MCO2EN                      RCC_MISCENR_MCO2EN_Msk               /*!< MCO2 enable */
+#define RCC_MISCENR_XSPIPHYCOMPEN_Pos           (3U)
+#define RCC_MISCENR_XSPIPHYCOMPEN_Msk           (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MISCENR_XSPIPHYCOMPEN               RCC_MISCENR_XSPIPHYCOMPEN_Msk        /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENR_PEREN_Pos                   (6U)
+#define RCC_MISCENR_PEREN_Msk                   (0x1UL << RCC_MISCENR_PEREN_Pos)      /*!< 0x00000040 */
+#define RCC_MISCENR_PEREN                       RCC_MISCENR_PEREN_Msk                /*!< PER enable */
+
+/******************  Bit definition for RCC_MEMENR register  ******************/
+#define RCC_MEMENR_AXISRAM3EN_Pos               (0U)
+#define RCC_MEMENR_AXISRAM3EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMENR_AXISRAM3EN                   RCC_MEMENR_AXISRAM3EN_Msk            /*!< AXISRAM3 enable */
+#define RCC_MEMENR_AXISRAM4EN_Pos               (1U)
+#define RCC_MEMENR_AXISRAM4EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMENR_AXISRAM4EN                   RCC_MEMENR_AXISRAM4EN_Msk            /*!< AXISRAM4 enable */
+#define RCC_MEMENR_AXISRAM5EN_Pos               (2U)
+#define RCC_MEMENR_AXISRAM5EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMENR_AXISRAM5EN                   RCC_MEMENR_AXISRAM5EN_Msk            /*!< AXISRAM5 enable */
+#define RCC_MEMENR_AXISRAM6EN_Pos               (3U)
+#define RCC_MEMENR_AXISRAM6EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMENR_AXISRAM6EN                   RCC_MEMENR_AXISRAM6EN_Msk            /*!< AXISRAM6 enable */
+#define RCC_MEMENR_AHBSRAM1EN_Pos               (4U)
+#define RCC_MEMENR_AHBSRAM1EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMENR_AHBSRAM1EN                   RCC_MEMENR_AHBSRAM1EN_Msk            /*!< AHBSRAM1 enable */
+#define RCC_MEMENR_AHBSRAM2EN_Pos               (5U)
+#define RCC_MEMENR_AHBSRAM2EN_Msk               (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMENR_AHBSRAM2EN                   RCC_MEMENR_AHBSRAM2EN_Msk            /*!< AHBSRAM2 enable */
+#define RCC_MEMENR_BKPSRAMEN_Pos                (6U)
+#define RCC_MEMENR_BKPSRAMEN_Msk                (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos)   /*!< 0x00000040 */
+#define RCC_MEMENR_BKPSRAMEN                    RCC_MEMENR_BKPSRAMEN_Msk             /*!< BKPSRAM enable */
+#define RCC_MEMENR_AXISRAM1EN_Pos               (7U)
+#define RCC_MEMENR_AXISRAM1EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMENR_AXISRAM1EN                   RCC_MEMENR_AXISRAM1EN_Msk            /*!< AXISRAM1 enable */
+#define RCC_MEMENR_AXISRAM2EN_Pos               (8U)
+#define RCC_MEMENR_AXISRAM2EN_Msk               (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMENR_AXISRAM2EN                   RCC_MEMENR_AXISRAM2EN_Msk            /*!< AXISRAM2 enable */
+#define RCC_MEMENR_FLEXRAMEN_Pos                (9U)
+#define RCC_MEMENR_FLEXRAMEN_Msk                (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos)   /*!< 0x00000200 */
+#define RCC_MEMENR_FLEXRAMEN                    RCC_MEMENR_FLEXRAMEN_Msk             /*!< FLEXRAM enable */
+#define RCC_MEMENR_CACHEAXIRAMEN_Pos            (10U)
+#define RCC_MEMENR_CACHEAXIRAMEN_Msk            (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */
+#define RCC_MEMENR_CACHEAXIRAMEN                RCC_MEMENR_CACHEAXIRAMEN_Msk         /*!< CACHEAXIRAM enable */
+#define RCC_MEMENR_VENCRAMEN_Pos                (11U)
+#define RCC_MEMENR_VENCRAMEN_Msk                (0x1UL << RCC_MEMENR_VENCRAMEN_Pos)   /*!< 0x00000800 */
+#define RCC_MEMENR_VENCRAMEN                    RCC_MEMENR_VENCRAMEN_Msk             /*!< VENCRAM enable */
+#define RCC_MEMENR_BOOTROMEN_Pos                (12U)
+#define RCC_MEMENR_BOOTROMEN_Msk                (0x1UL << RCC_MEMENR_BOOTROMEN_Pos)   /*!< 0x00001000 */
+#define RCC_MEMENR_BOOTROMEN                    RCC_MEMENR_BOOTROMEN_Msk             /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENR register  ******************/
+#define RCC_AHB1ENR_GPDMA1EN_Pos                (4U)
+#define RCC_AHB1ENR_GPDMA1EN_Msk                (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPDMA1EN                    RCC_AHB1ENR_GPDMA1EN_Msk             /*!< GPDMA1 enable */
+#define RCC_AHB1ENR_ADC12EN_Pos                 (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                 (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                     RCC_AHB1ENR_ADC12EN_Msk              /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENR register  ******************/
+#define RCC_AHB2ENR_RAMCFGEN_Pos                (12U)
+#define RCC_AHB2ENR_RAMCFGEN_Msk                (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2ENR_RAMCFGEN                    RCC_AHB2ENR_RAMCFGEN_Msk             /*!< RAMCFG enable */
+#define RCC_AHB2ENR_MDF1EN_Pos                  (16U)
+#define RCC_AHB2ENR_MDF1EN_Msk                  (0x1UL << RCC_AHB2ENR_MDF1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB2ENR_MDF1EN                      RCC_AHB2ENR_MDF1EN_Msk               /*!< MDF1 enable */
+#define RCC_AHB2ENR_ADF1EN_Pos                  (17U)
+#define RCC_AHB2ENR_ADF1EN_Msk                  (0x1UL << RCC_AHB2ENR_ADF1EN_Pos)     /*!< 0x00020000 */
+#define RCC_AHB2ENR_ADF1EN                      RCC_AHB2ENR_ADF1EN_Msk               /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENR register  ******************/
+#define RCC_AHB3ENR_RNGEN_Pos                   (0U)
+#define RCC_AHB3ENR_RNGEN_Msk                   (0x1UL << RCC_AHB3ENR_RNGEN_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3ENR_RNGEN                       RCC_AHB3ENR_RNGEN_Msk                /*!< RNG enable */
+#define RCC_AHB3ENR_HASHEN_Pos                  (1U)
+#define RCC_AHB3ENR_HASHEN_Msk                  (0x1UL << RCC_AHB3ENR_HASHEN_Pos)     /*!< 0x00000002 */
+#define RCC_AHB3ENR_HASHEN                      RCC_AHB3ENR_HASHEN_Msk               /*!< HASH enable */
+#define RCC_AHB3ENR_CRYPEN_Pos                  (2U)
+#define RCC_AHB3ENR_CRYPEN_Msk                  (0x1UL << RCC_AHB3ENR_CRYPEN_Pos)     /*!< 0x00000004 */
+#define RCC_AHB3ENR_CRYPEN                      RCC_AHB3ENR_CRYPEN_Msk               /*!< CRYP enable */
+#define RCC_AHB3ENR_SAESEN_Pos                  (4U)
+#define RCC_AHB3ENR_SAESEN_Msk                  (0x1UL << RCC_AHB3ENR_SAESEN_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3ENR_SAESEN                      RCC_AHB3ENR_SAESEN_Msk               /*!< SAES enable */
+#define RCC_AHB3ENR_PKAEN_Pos                   (8U)
+#define RCC_AHB3ENR_PKAEN_Msk                   (0x1UL << RCC_AHB3ENR_PKAEN_Pos)      /*!< 0x00000100 */
+#define RCC_AHB3ENR_PKAEN                       RCC_AHB3ENR_PKAEN_Msk                /*!< PKA enable */
+#define RCC_AHB3ENR_RIFSCEN_Pos                 (9U)
+#define RCC_AHB3ENR_RIFSCEN_Msk                 (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos)    /*!< 0x00000200 */
+#define RCC_AHB3ENR_RIFSCEN                     RCC_AHB3ENR_RIFSCEN_Msk              /*!< RIFSC enable */
+#define RCC_AHB3ENR_IACEN_Pos                   (10U)
+#define RCC_AHB3ENR_IACEN_Msk                   (0x1UL << RCC_AHB3ENR_IACEN_Pos)      /*!< 0x00000400 */
+#define RCC_AHB3ENR_IACEN                       RCC_AHB3ENR_IACEN_Msk                /*!< IAC enable */
+#define RCC_AHB3ENR_RISAFEN_Pos                 (14U)
+#define RCC_AHB3ENR_RISAFEN_Msk                 (0x1UL << RCC_AHB3ENR_RISAFEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB3ENR_RISAFEN                     RCC_AHB3ENR_RISAFEN_Msk              /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                 (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                     RCC_AHB4ENR_GPIOAEN_Msk              /*!< GPIO A enable */
+#define RCC_AHB4ENR_GPIOBEN_Pos                 (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                     RCC_AHB4ENR_GPIOBEN_Msk              /*!< GPIO B enable */
+#define RCC_AHB4ENR_GPIOCEN_Pos                 (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)    /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                     RCC_AHB4ENR_GPIOCEN_Msk              /*!< GPIO C enable */
+#define RCC_AHB4ENR_GPIODEN_Pos                 (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)    /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                     RCC_AHB4ENR_GPIODEN_Msk              /*!< GPIO D enable */
+#define RCC_AHB4ENR_GPIOEEN_Pos                 (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)    /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                     RCC_AHB4ENR_GPIOEEN_Msk              /*!< GPIO E enable */
+#define RCC_AHB4ENR_GPIOFEN_Pos                 (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                     RCC_AHB4ENR_GPIOFEN_Msk              /*!< GPIO F enable */
+#define RCC_AHB4ENR_GPIOGEN_Pos                 (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)    /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                     RCC_AHB4ENR_GPIOGEN_Msk              /*!< GPIO G enable */
+#define RCC_AHB4ENR_GPIOHEN_Pos                 (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)    /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                     RCC_AHB4ENR_GPIOHEN_Msk              /*!< GPIO H enable */
+#define RCC_AHB4ENR_GPIONEN_Pos                 (13U)
+#define RCC_AHB4ENR_GPIONEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIONEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB4ENR_GPIONEN                     RCC_AHB4ENR_GPIONEN_Msk              /*!< GPIO N enable */
+#define RCC_AHB4ENR_GPIOOEN_Pos                 (14U)
+#define RCC_AHB4ENR_GPIOOEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos)    /*!< 0x00004000 */
+#define RCC_AHB4ENR_GPIOOEN                     RCC_AHB4ENR_GPIOOEN_Msk              /*!< GPIO O enable */
+#define RCC_AHB4ENR_GPIOPEN_Pos                 (15U)
+#define RCC_AHB4ENR_GPIOPEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos)    /*!< 0x00008000 */
+#define RCC_AHB4ENR_GPIOPEN                     RCC_AHB4ENR_GPIOPEN_Msk              /*!< GPIO P enable */
+#define RCC_AHB4ENR_GPIOQEN_Pos                 (16U)
+#define RCC_AHB4ENR_GPIOQEN_Msk                 (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos)    /*!< 0x00010000 */
+#define RCC_AHB4ENR_GPIOQEN                     RCC_AHB4ENR_GPIOQEN_Msk              /*!< GPIO Q enable */
+#define RCC_AHB4ENR_PWREN_Pos                   (18U)
+#define RCC_AHB4ENR_PWREN_Msk                   (0x1UL << RCC_AHB4ENR_PWREN_Pos)      /*!< 0x00040000 */
+#define RCC_AHB4ENR_PWREN                       RCC_AHB4ENR_PWREN_Msk                /*!< PWR enable */
+#define RCC_AHB4ENR_CRCEN_Pos                   (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                   (0x1UL << RCC_AHB4ENR_CRCEN_Pos)      /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                       RCC_AHB4ENR_CRCEN_Msk                /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENR register  ******************/
+#define RCC_AHB5ENR_HPDMA1EN_Pos                (0U)
+#define RCC_AHB5ENR_HPDMA1EN_Msk                (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5ENR_HPDMA1EN                    RCC_AHB5ENR_HPDMA1EN_Msk             /*!< HPDMA1 enable */
+#define RCC_AHB5ENR_DMA2DEN_Pos                 (1U)
+#define RCC_AHB5ENR_DMA2DEN_Msk                 (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos)    /*!< 0x00000002 */
+#define RCC_AHB5ENR_DMA2DEN                     RCC_AHB5ENR_DMA2DEN_Msk              /*!< DMA2D enable */
+#define RCC_AHB5ENR_JPEGEN_Pos                  (3U)
+#define RCC_AHB5ENR_JPEGEN_Msk                  (0x1UL << RCC_AHB5ENR_JPEGEN_Pos)     /*!< 0x00000008 */
+#define RCC_AHB5ENR_JPEGEN                      RCC_AHB5ENR_JPEGEN_Msk               /*!< JPEG enable */
+#define RCC_AHB5ENR_FMCEN_Pos                   (4U)
+#define RCC_AHB5ENR_FMCEN_Msk                   (0x1UL << RCC_AHB5ENR_FMCEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB5ENR_FMCEN                       RCC_AHB5ENR_FMCEN_Msk                /*!< FMC enable */
+#define RCC_AHB5ENR_XSPI1EN_Pos                 (5U)
+#define RCC_AHB5ENR_XSPI1EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB5ENR_XSPI1EN                     RCC_AHB5ENR_XSPI1EN_Msk              /*!< XSPI1 enable */
+#define RCC_AHB5ENR_PSSIEN_Pos                  (6U)
+#define RCC_AHB5ENR_PSSIEN_Msk                  (0x1UL << RCC_AHB5ENR_PSSIEN_Pos)     /*!< 0x00000040 */
+#define RCC_AHB5ENR_PSSIEN                      RCC_AHB5ENR_PSSIEN_Msk               /*!< PSSI enable */
+#define RCC_AHB5ENR_SDMMC2EN_Pos                (7U)
+#define RCC_AHB5ENR_SDMMC2EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5ENR_SDMMC2EN                    RCC_AHB5ENR_SDMMC2EN_Msk             /*!< SDMMC2 enable */
+#define RCC_AHB5ENR_SDMMC1EN_Pos                (8U)
+#define RCC_AHB5ENR_SDMMC1EN_Msk                (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5ENR_SDMMC1EN                    RCC_AHB5ENR_SDMMC1EN_Msk             /*!< SDMMC1 enable */
+#define RCC_AHB5ENR_XSPI2EN_Pos                 (12U)
+#define RCC_AHB5ENR_XSPI2EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos)    /*!< 0x00001000 */
+#define RCC_AHB5ENR_XSPI2EN                     RCC_AHB5ENR_XSPI2EN_Msk              /*!< XSPI2 enable */
+#define RCC_AHB5ENR_XSPIMEN_Pos                 (13U)
+#define RCC_AHB5ENR_XSPIMEN_Msk                 (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos)    /*!< 0x00002000 */
+#define RCC_AHB5ENR_XSPIMEN                     RCC_AHB5ENR_XSPIMEN_Msk              /*!< XSPIM enable */
+#define RCC_AHB5ENR_MCE1EN_Pos                  (14U)
+#define RCC_AHB5ENR_MCE1EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE1EN_Pos)     /*!< 0x00004000 */
+#define RCC_AHB5ENR_MCE1EN                      RCC_AHB5ENR_MCE1EN_Msk               /*!< MCE1 enable */
+#define RCC_AHB5ENR_MCE2EN_Pos                  (15U)
+#define RCC_AHB5ENR_MCE2EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE2EN_Pos)     /*!< 0x00008000 */
+#define RCC_AHB5ENR_MCE2EN                      RCC_AHB5ENR_MCE2EN_Msk               /*!< MCE2 enable */
+#define RCC_AHB5ENR_MCE3EN_Pos                  (16U)
+#define RCC_AHB5ENR_MCE3EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE3EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB5ENR_MCE3EN                      RCC_AHB5ENR_MCE3EN_Msk               /*!< MCE3 enable */
+#define RCC_AHB5ENR_XSPI3EN_Pos                 (17U)
+#define RCC_AHB5ENR_XSPI3EN_Msk                 (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos)    /*!< 0x00020000 */
+#define RCC_AHB5ENR_XSPI3EN                     RCC_AHB5ENR_XSPI3EN_Msk              /*!< XSPI3 enable */
+#define RCC_AHB5ENR_MCE4EN_Pos                  (18U)
+#define RCC_AHB5ENR_MCE4EN_Msk                  (0x1UL << RCC_AHB5ENR_MCE4EN_Pos)     /*!< 0x00040000 */
+#define RCC_AHB5ENR_MCE4EN                      RCC_AHB5ENR_MCE4EN_Msk               /*!< MCE4 enable */
+#define RCC_AHB5ENR_GFXMMUEN_Pos                (19U)
+#define RCC_AHB5ENR_GFXMMUEN_Msk                (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5ENR_GFXMMUEN                    RCC_AHB5ENR_GFXMMUEN_Msk             /*!< GFXMMU enable */
+#define RCC_AHB5ENR_GPU2DEN_Pos                 (20U)
+#define RCC_AHB5ENR_GPU2DEN_Msk                 (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos)    /*!< 0x00100000 */
+#define RCC_AHB5ENR_GPU2DEN                     RCC_AHB5ENR_GPU2DEN_Msk              /*!< GPU2D enable */
+#define RCC_AHB5ENR_ETH1MACEN_Pos               (22U)
+#define RCC_AHB5ENR_ETH1MACEN_Msk               (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5ENR_ETH1MACEN                   RCC_AHB5ENR_ETH1MACEN_Msk            /*!< ETH1MAC enable */
+#define RCC_AHB5ENR_ETH1TXEN_Pos                (23U)
+#define RCC_AHB5ENR_ETH1TXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5ENR_ETH1TXEN                    RCC_AHB5ENR_ETH1TXEN_Msk             /*!< ETH1TX enable */
+#define RCC_AHB5ENR_ETH1RXEN_Pos                (24U)
+#define RCC_AHB5ENR_ETH1RXEN_Msk                (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5ENR_ETH1RXEN                    RCC_AHB5ENR_ETH1RXEN_Msk             /*!< ETH1RX enable */
+#define RCC_AHB5ENR_ETH1EN_Pos                  (25U)
+#define RCC_AHB5ENR_ETH1EN_Msk                  (0x1UL << RCC_AHB5ENR_ETH1EN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB5ENR_ETH1EN                      RCC_AHB5ENR_ETH1EN_Msk               /*!< ETH1 enable */
+#define RCC_AHB5ENR_OTG1EN_Pos                  (26U)
+#define RCC_AHB5ENR_OTG1EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG1EN_Pos)     /*!< 0x04000000 */
+#define RCC_AHB5ENR_OTG1EN                      RCC_AHB5ENR_OTG1EN_Msk               /*!< OTG1 enable */
+#define RCC_AHB5ENR_OTGPHY1EN_Pos               (27U)
+#define RCC_AHB5ENR_OTGPHY1EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5ENR_OTGPHY1EN                   RCC_AHB5ENR_OTGPHY1EN_Msk            /*!< OTGPHY1 enable */
+#define RCC_AHB5ENR_OTGPHY2EN_Pos               (28U)
+#define RCC_AHB5ENR_OTGPHY2EN_Msk               (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5ENR_OTGPHY2EN                   RCC_AHB5ENR_OTGPHY2EN_Msk            /*!< OTGPHY2 enable */
+#define RCC_AHB5ENR_OTG2EN_Pos                  (29U)
+#define RCC_AHB5ENR_OTG2EN_Msk                  (0x1UL << RCC_AHB5ENR_OTG2EN_Pos)     /*!< 0x20000000 */
+#define RCC_AHB5ENR_OTG2EN                      RCC_AHB5ENR_OTG2EN_Msk               /*!< OTG2 enable */
+#define RCC_AHB5ENR_CACHEAXIEN_Pos              (30U)
+#define RCC_AHB5ENR_CACHEAXIEN_Msk              (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB5ENR_CACHEAXIEN                  RCC_AHB5ENR_CACHEAXIEN_Msk           /*!< CACHEAXI enable */
+#define RCC_AHB5ENR_NPUEN_Pos                   (31U)
+#define RCC_AHB5ENR_NPUEN_Msk                   (0x1UL << RCC_AHB5ENR_NPUEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB5ENR_NPUEN                       RCC_AHB5ENR_NPUEN_Msk                /*!< NPU enable */
+
+/*****************  Bit definition for RCC_APB1ENR1 register  *****************/
+#define RCC_APB1ENR1_TIM2EN_Pos                 (0U)
+#define RCC_APB1ENR1_TIM2EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                     RCC_APB1ENR1_TIM2EN_Msk              /*!< TIM2 enable */
+#define RCC_APB1ENR1_TIM3EN_Pos                 (1U)
+#define RCC_APB1ENR1_TIM3EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                     RCC_APB1ENR1_TIM3EN_Msk              /*!< TIM3 enable */
+#define RCC_APB1ENR1_TIM4EN_Pos                 (2U)
+#define RCC_APB1ENR1_TIM4EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)    /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                     RCC_APB1ENR1_TIM4EN_Msk              /*!< TIM4 enable */
+#define RCC_APB1ENR1_TIM5EN_Pos                 (3U)
+#define RCC_APB1ENR1_TIM5EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)    /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                     RCC_APB1ENR1_TIM5EN_Msk              /*!< TIM5 enable */
+#define RCC_APB1ENR1_TIM6EN_Pos                 (4U)
+#define RCC_APB1ENR1_TIM6EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)    /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                     RCC_APB1ENR1_TIM6EN_Msk              /*!< TIM6 enable */
+#define RCC_APB1ENR1_TIM7EN_Pos                 (5U)
+#define RCC_APB1ENR1_TIM7EN_Msk                 (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                     RCC_APB1ENR1_TIM7EN_Msk              /*!< TIM7 enable */
+#define RCC_APB1ENR1_TIM12EN_Pos                (6U)
+#define RCC_APB1ENR1_TIM12EN_Msk                (0x1UL << RCC_APB1ENR1_TIM12EN_Pos)   /*!< 0x00000040 */
+#define RCC_APB1ENR1_TIM12EN                    RCC_APB1ENR1_TIM12EN_Msk             /*!< TIM12 enable */
+#define RCC_APB1ENR1_TIM13EN_Pos                (7U)
+#define RCC_APB1ENR1_TIM13EN_Msk                (0x1UL << RCC_APB1ENR1_TIM13EN_Pos)   /*!< 0x00000080 */
+#define RCC_APB1ENR1_TIM13EN                    RCC_APB1ENR1_TIM13EN_Msk             /*!< TIM13 enable */
+#define RCC_APB1ENR1_TIM14EN_Pos                (8U)
+#define RCC_APB1ENR1_TIM14EN_Msk                (0x1UL << RCC_APB1ENR1_TIM14EN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR1_TIM14EN                    RCC_APB1ENR1_TIM14EN_Msk             /*!< TIM14 enable */
+#define RCC_APB1ENR1_LPTIM1EN_Pos               (9U)
+#define RCC_APB1ENR1_LPTIM1EN_Msk               (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LPTIM1EN                   RCC_APB1ENR1_LPTIM1EN_Msk            /*!< LPTIM1 enable */
+#define RCC_APB1ENR1_WWDGEN_Pos                 (11U)
+#define RCC_APB1ENR1_WWDGEN_Msk                 (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                     RCC_APB1ENR1_WWDGEN_Msk              /*!< WWDG enable */
+#define RCC_APB1ENR1_TIM10EN_Pos                (12U)
+#define RCC_APB1ENR1_TIM10EN_Msk                (0x1UL << RCC_APB1ENR1_TIM10EN_Pos)   /*!< 0x00001000 */
+#define RCC_APB1ENR1_TIM10EN                    RCC_APB1ENR1_TIM10EN_Msk             /*!< TIM10 enable */
+#define RCC_APB1ENR1_TIM11EN_Pos                (13U)
+#define RCC_APB1ENR1_TIM11EN_Msk                (0x1UL << RCC_APB1ENR1_TIM11EN_Pos)   /*!< 0x00002000 */
+#define RCC_APB1ENR1_TIM11EN                    RCC_APB1ENR1_TIM11EN_Msk             /*!< TIM11 enable */
+#define RCC_APB1ENR1_SPI2EN_Pos                 (14U)
+#define RCC_APB1ENR1_SPI2EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                     RCC_APB1ENR1_SPI2EN_Msk              /*!< SPI2 enable */
+#define RCC_APB1ENR1_SPI3EN_Pos                 (15U)
+#define RCC_APB1ENR1_SPI3EN_Msk                 (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                     RCC_APB1ENR1_SPI3EN_Msk              /*!< SPI3 enable */
+#define RCC_APB1ENR1_SPDIFRX1EN_Pos             (16U)
+#define RCC_APB1ENR1_SPDIFRX1EN_Msk             (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */
+#define RCC_APB1ENR1_SPDIFRX1EN                 RCC_APB1ENR1_SPDIFRX1EN_Msk          /*!< SPDIFRX1 enable */
+#define RCC_APB1ENR1_USART2EN_Pos               (17U)
+#define RCC_APB1ENR1_USART2EN_Msk               (0x1UL << RCC_APB1ENR1_USART2EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                   RCC_APB1ENR1_USART2EN_Msk            /*!< USART2 enable */
+#define RCC_APB1ENR1_USART3EN_Pos               (18U)
+#define RCC_APB1ENR1_USART3EN_Msk               (0x1UL << RCC_APB1ENR1_USART3EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                   RCC_APB1ENR1_USART3EN_Msk            /*!< USART3 enable */
+#define RCC_APB1ENR1_UART4EN_Pos                (19U)
+#define RCC_APB1ENR1_UART4EN_Msk                (0x1UL << RCC_APB1ENR1_UART4EN_Pos)   /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                    RCC_APB1ENR1_UART4EN_Msk             /*!< UART4 enable */
+#define RCC_APB1ENR1_UART5EN_Pos                (20U)
+#define RCC_APB1ENR1_UART5EN_Msk                (0x1UL << RCC_APB1ENR1_UART5EN_Pos)   /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                    RCC_APB1ENR1_UART5EN_Msk             /*!< UART5 enable */
+#define RCC_APB1ENR1_I2C1EN_Pos                 (21U)
+#define RCC_APB1ENR1_I2C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                     RCC_APB1ENR1_I2C1EN_Msk              /*!< I2C1 enable */
+#define RCC_APB1ENR1_I2C2EN_Pos                 (22U)
+#define RCC_APB1ENR1_I2C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                     RCC_APB1ENR1_I2C2EN_Msk              /*!< I2C2 enable */
+#define RCC_APB1ENR1_I2C3EN_Pos                 (23U)
+#define RCC_APB1ENR1_I2C3EN_Msk                 (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                     RCC_APB1ENR1_I2C3EN_Msk              /*!< I2C3 enable */
+#define RCC_APB1ENR1_I3C1EN_Pos                 (24U)
+#define RCC_APB1ENR1_I3C1EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C1EN_Pos)    /*!< 0x01000000 */
+#define RCC_APB1ENR1_I3C1EN                     RCC_APB1ENR1_I3C1EN_Msk              /*!< I3C1 enable */
+#define RCC_APB1ENR1_I3C2EN_Pos                 (25U)
+#define RCC_APB1ENR1_I3C2EN_Msk                 (0x1UL << RCC_APB1ENR1_I3C2EN_Pos)    /*!< 0x02000000 */
+#define RCC_APB1ENR1_I3C2EN                     RCC_APB1ENR1_I3C2EN_Msk              /*!< I3C2 enable */
+#define RCC_APB1ENR1_UART7EN_Pos                (30U)
+#define RCC_APB1ENR1_UART7EN_Msk                (0x1UL << RCC_APB1ENR1_UART7EN_Pos)   /*!< 0x40000000 */
+#define RCC_APB1ENR1_UART7EN                    RCC_APB1ENR1_UART7EN_Msk             /*!< UART7 enable */
+#define RCC_APB1ENR1_UART8EN_Pos                (31U)
+#define RCC_APB1ENR1_UART8EN_Msk                (0x1UL << RCC_APB1ENR1_UART8EN_Pos)   /*!< 0x80000000 */
+#define RCC_APB1ENR1_UART8EN                    RCC_APB1ENR1_UART8EN_Msk             /*!< UART8 enable */
+
+/*****************  Bit definition for RCC_APB1ENR2 register  *****************/
+#define RCC_APB1ENR2_MDIOSEN_Pos                (5U)
+#define RCC_APB1ENR2_MDIOSEN_Msk                (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos)   /*!< 0x00000020 */
+#define RCC_APB1ENR2_MDIOSEN                    RCC_APB1ENR2_MDIOSEN_Msk             /*!< MDIOS enable */
+#define RCC_APB1ENR2_FDCANEN_Pos                (8U)
+#define RCC_APB1ENR2_FDCANEN_Msk                (0x1UL << RCC_APB1ENR2_FDCANEN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR2_FDCANEN                    RCC_APB1ENR2_FDCANEN_Msk             /*!< FDCAN enable */
+#define RCC_APB1ENR2_UCPD1EN_Pos                (18U)
+#define RCC_APB1ENR2_UCPD1EN_Msk                (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB1ENR2_UCPD1EN                    RCC_APB1ENR2_UCPD1EN_Msk             /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                  (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                  (0x1UL << RCC_APB2ENR_TIM1EN_Pos)     /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                      RCC_APB2ENR_TIM1EN_Msk               /*!< TIM1 enable */
+#define RCC_APB2ENR_TIM8EN_Pos                  (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                  (0x1UL << RCC_APB2ENR_TIM8EN_Pos)     /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                      RCC_APB2ENR_TIM8EN_Msk               /*!< TIM8 enable */
+#define RCC_APB2ENR_USART1EN_Pos                (4U)
+#define RCC_APB2ENR_USART1EN_Msk                (0x1UL << RCC_APB2ENR_USART1EN_Pos)   /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                    RCC_APB2ENR_USART1EN_Msk             /*!< USART1 enable */
+#define RCC_APB2ENR_USART6EN_Pos                (5U)
+#define RCC_APB2ENR_USART6EN_Msk                (0x1UL << RCC_APB2ENR_USART6EN_Pos)   /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                    RCC_APB2ENR_USART6EN_Msk             /*!< USART6 enable */
+#define RCC_APB2ENR_UART9EN_Pos                 (6U)
+#define RCC_APB2ENR_UART9EN_Msk                 (0x1UL << RCC_APB2ENR_UART9EN_Pos)    /*!< 0x00000040 */
+#define RCC_APB2ENR_UART9EN                     RCC_APB2ENR_UART9EN_Msk              /*!< UART9 enable */
+#define RCC_APB2ENR_USART10EN_Pos               (7U)
+#define RCC_APB2ENR_USART10EN_Msk               (0x1UL << RCC_APB2ENR_USART10EN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk            /*!< USART10 enable */
+#define RCC_APB2ENR_SPI1EN_Pos                  (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                  (0x1UL << RCC_APB2ENR_SPI1EN_Pos)     /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                      RCC_APB2ENR_SPI1EN_Msk               /*!< SPI1 enable */
+#define RCC_APB2ENR_SPI4EN_Pos                  (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                  (0x1UL << RCC_APB2ENR_SPI4EN_Pos)     /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                      RCC_APB2ENR_SPI4EN_Msk               /*!< SPI4 enable */
+#define RCC_APB2ENR_TIM18EN_Pos                 (15U)
+#define RCC_APB2ENR_TIM18EN_Msk                 (0x1UL << RCC_APB2ENR_TIM18EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB2ENR_TIM18EN                     RCC_APB2ENR_TIM18EN_Msk              /*!< TIM18 enable */
+#define RCC_APB2ENR_TIM15EN_Pos                 (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                 (0x1UL << RCC_APB2ENR_TIM15EN_Pos)    /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                     RCC_APB2ENR_TIM15EN_Msk              /*!< TIM15 enable */
+#define RCC_APB2ENR_TIM16EN_Pos                 (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                 (0x1UL << RCC_APB2ENR_TIM16EN_Pos)    /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                     RCC_APB2ENR_TIM16EN_Msk              /*!< TIM16 enable */
+#define RCC_APB2ENR_TIM17EN_Pos                 (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                 (0x1UL << RCC_APB2ENR_TIM17EN_Pos)    /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                     RCC_APB2ENR_TIM17EN_Msk              /*!< TIM17 enable */
+#define RCC_APB2ENR_TIM9EN_Pos                  (19U)
+#define RCC_APB2ENR_TIM9EN_Msk                  (0x1UL << RCC_APB2ENR_TIM9EN_Pos)     /*!< 0x00080000 */
+#define RCC_APB2ENR_TIM9EN                      RCC_APB2ENR_TIM9EN_Msk               /*!< TIM9 enable */
+#define RCC_APB2ENR_SPI5EN_Pos                  (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                  (0x1UL << RCC_APB2ENR_SPI5EN_Pos)     /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                      RCC_APB2ENR_SPI5EN_Msk               /*!< SPI5 enable */
+#define RCC_APB2ENR_SAI1EN_Pos                  (21U)
+#define RCC_APB2ENR_SAI1EN_Msk                  (0x1UL << RCC_APB2ENR_SAI1EN_Pos)     /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                      RCC_APB2ENR_SAI1EN_Msk               /*!< SAI1 enable */
+#define RCC_APB2ENR_SAI2EN_Pos                  (22U)
+#define RCC_APB2ENR_SAI2EN_Msk                  (0x1UL << RCC_APB2ENR_SAI2EN_Pos)     /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                      RCC_APB2ENR_SAI2EN_Msk               /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_DFTEN_Pos                   (2U)
+#define RCC_APB3ENR_DFTEN_Msk                   (0x1UL << RCC_APB3ENR_DFTEN_Pos)      /*!< 0x00000004 */
+#define RCC_APB3ENR_DFTEN                       RCC_APB3ENR_DFTEN_Msk                /*!< DFT enable */
+
+/*****************  Bit definition for RCC_APB4ENR1 register  *****************/
+#define RCC_APB4ENR1_HDPEN_Pos                  (2U)
+#define RCC_APB4ENR1_HDPEN_Msk                  (0x1UL << RCC_APB4ENR1_HDPEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR1_HDPEN                      RCC_APB4ENR1_HDPEN_Msk               /*!< HDP enable */
+#define RCC_APB4ENR1_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR1_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR1_LPUART1EN                  RCC_APB4ENR1_LPUART1EN_Msk           /*!< LPUART1 enable */
+#define RCC_APB4ENR1_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR1_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR1_SPI6EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB4ENR1_SPI6EN                     RCC_APB4ENR1_SPI6EN_Msk              /*!< SPI6 enable */
+#define RCC_APB4ENR1_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR1_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR1_I2C4EN_Pos)    /*!< 0x00000080 */
+#define RCC_APB4ENR1_I2C4EN                     RCC_APB4ENR1_I2C4EN_Msk              /*!< I2C4 enable */
+#define RCC_APB4ENR1_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR1_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4ENR1_LPTIM2EN                   RCC_APB4ENR1_LPTIM2EN_Msk            /*!< LPTIM2 enable */
+#define RCC_APB4ENR1_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR1_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4ENR1_LPTIM3EN                   RCC_APB4ENR1_LPTIM3EN_Msk            /*!< LPTIM3 enable */
+#define RCC_APB4ENR1_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR1_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4ENR1_LPTIM4EN                   RCC_APB4ENR1_LPTIM4EN_Msk            /*!< LPTIM4 enable */
+#define RCC_APB4ENR1_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR1_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4ENR1_LPTIM5EN                   RCC_APB4ENR1_LPTIM5EN_Msk            /*!< LPTIM5 enable */
+#define RCC_APB4ENR1_VREFBUFEN_Pos              (15U)
+#define RCC_APB4ENR1_VREFBUFEN_Msk              (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR1_VREFBUFEN                  RCC_APB4ENR1_VREFBUFEN_Msk           /*!< VREFBUF enable */
+#define RCC_APB4ENR1_RTCEN_Pos                  (16U)
+#define RCC_APB4ENR1_RTCEN_Msk                  (0x1UL << RCC_APB4ENR1_RTCEN_Pos)     /*!< 0x00010000 */
+#define RCC_APB4ENR1_RTCEN                      RCC_APB4ENR1_RTCEN_Msk               /*!< RTC enable */
+#define RCC_APB4ENR1_RTCAPBEN_Pos               (17U)
+#define RCC_APB4ENR1_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4ENR1_RTCAPBEN                   RCC_APB4ENR1_RTCAPBEN_Msk            /*!< RTCAPB enable */
+
+/*****************  Bit definition for RCC_APB4ENR2 register  *****************/
+#define RCC_APB4ENR2_SYSCFGEN_Pos               (0U)
+#define RCC_APB4ENR2_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4ENR2_SYSCFGEN                   RCC_APB4ENR2_SYSCFGEN_Msk            /*!< SYSCFG enable */
+#define RCC_APB4ENR2_BSECEN_Pos                 (1U)
+#define RCC_APB4ENR2_BSECEN_Msk                 (0x1UL << RCC_APB4ENR2_BSECEN_Pos)    /*!< 0x00000002 */
+#define RCC_APB4ENR2_BSECEN                     RCC_APB4ENR2_BSECEN_Msk              /*!< BSEC enable */
+#define RCC_APB4ENR2_DTSEN_Pos                  (2U)
+#define RCC_APB4ENR2_DTSEN_Msk                  (0x1UL << RCC_APB4ENR2_DTSEN_Pos)     /*!< 0x00000004 */
+#define RCC_APB4ENR2_DTSEN                      RCC_APB4ENR2_DTSEN_Msk               /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENR register  ******************/
+#define RCC_APB5ENR_LTDCEN_Pos                  (1U)
+#define RCC_APB5ENR_LTDCEN_Msk                  (0x1UL << RCC_APB5ENR_LTDCEN_Pos)     /*!< 0x00000002 */
+#define RCC_APB5ENR_LTDCEN                      RCC_APB5ENR_LTDCEN_Msk               /*!< LTDC enable */
+#define RCC_APB5ENR_DCMIPPEN_Pos                (2U)
+#define RCC_APB5ENR_DCMIPPEN_Msk                (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos)   /*!< 0x00000004 */
+#define RCC_APB5ENR_DCMIPPEN                    RCC_APB5ENR_DCMIPPEN_Msk             /*!< DCMIPP enable */
+#define RCC_APB5ENR_GFXTIMEN_Pos                (4U)
+#define RCC_APB5ENR_GFXTIMEN_Msk                (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos)   /*!< 0x00000010 */
+#define RCC_APB5ENR_GFXTIMEN                    RCC_APB5ENR_GFXTIMEN_Msk             /*!< GFXTIM enable */
+#define RCC_APB5ENR_VENCEN_Pos                  (5U)
+#define RCC_APB5ENR_VENCEN_Msk                  (0x1UL << RCC_APB5ENR_VENCEN_Pos)     /*!< 0x00000020 */
+#define RCC_APB5ENR_VENCEN                      RCC_APB5ENR_VENCEN_Msk               /*!< VENC enable */
+#define RCC_APB5ENR_CSIEN_Pos                   (6U)
+#define RCC_APB5ENR_CSIEN_Msk                   (0x1UL << RCC_APB5ENR_CSIEN_Pos)      /*!< 0x00000040 */
+#define RCC_APB5ENR_CSIEN                       RCC_APB5ENR_CSIEN_Msk                /*!< CSI enable */
+
+/*****************  Bit definition for RCC_BUSLPENR register  *****************/
+#define RCC_BUSLPENR_ACLKNLPEN_Pos              (0U)
+#define RCC_BUSLPENR_ACLKNLPEN_Msk              (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENR_ACLKNLPEN                  RCC_BUSLPENR_ACLKNLPEN_Msk           /*!< ACLKN enable  */
+#define RCC_BUSLPENR_ACLKNCLPEN_Pos             (1U)
+#define RCC_BUSLPENR_ACLKNCLPEN_Msk             (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */
+#define RCC_BUSLPENR_ACLKNCLPEN                 RCC_BUSLPENR_ACLKNCLPEN_Msk          /*!< ACLKNC enable */
+
+/****************  Bit definition for RCC_MISCLPENR register  *****************/
+#define RCC_MISCLPENR_DBGLPEN_Pos               (0U)
+#define RCC_MISCLPENR_DBGLPEN_Msk               (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MISCLPENR_DBGLPEN                   RCC_MISCLPENR_DBGLPEN_Msk            /*!< DBG enable  */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos       (3U)
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk       (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos)      /*!< 0x00000008 */
+#define RCC_MISCLPENR_XSPIPHYCOMPLPEN           RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk    /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENR_PERLPEN_Pos               (6U)
+#define RCC_MISCLPENR_PERLPEN_Msk               (0x1UL << RCC_MISCLPENR_PERLPEN_Pos)  /*!< 0x00000040 */
+#define RCC_MISCLPENR_PERLPEN                   RCC_MISCLPENR_PERLPEN_Msk            /*!< PER enable  */
+
+/*****************  Bit definition for RCC_MEMLPENR register  *****************/
+#define RCC_MEMLPENR_AXISRAM3LPEN_Pos           (0U)
+#define RCC_MEMLPENR_AXISRAM3LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos)  /*!< 0x00000001 */
+#define RCC_MEMLPENR_AXISRAM3LPEN               RCC_MEMLPENR_AXISRAM3LPEN_Msk        /*!< AXISRAM3 enable */
+#define RCC_MEMLPENR_AXISRAM4LPEN_Pos           (1U)
+#define RCC_MEMLPENR_AXISRAM4LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos)  /*!< 0x00000002 */
+#define RCC_MEMLPENR_AXISRAM4LPEN               RCC_MEMLPENR_AXISRAM4LPEN_Msk        /*!< AXISRAM4 enable */
+#define RCC_MEMLPENR_AXISRAM5LPEN_Pos           (2U)
+#define RCC_MEMLPENR_AXISRAM5LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos)  /*!< 0x00000004 */
+#define RCC_MEMLPENR_AXISRAM5LPEN               RCC_MEMLPENR_AXISRAM5LPEN_Msk        /*!< AXISRAM5 enable */
+#define RCC_MEMLPENR_AXISRAM6LPEN_Pos           (3U)
+#define RCC_MEMLPENR_AXISRAM6LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos)  /*!< 0x00000008 */
+#define RCC_MEMLPENR_AXISRAM6LPEN               RCC_MEMLPENR_AXISRAM6LPEN_Msk        /*!< AXISRAM6 enable */
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos           (4U)
+#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos)  /*!< 0x00000010 */
+#define RCC_MEMLPENR_AHBSRAM1LPEN               RCC_MEMLPENR_AHBSRAM1LPEN_Msk        /*!< AHBSRAM1 enable */
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos           (5U)
+#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos)  /*!< 0x00000020 */
+#define RCC_MEMLPENR_AHBSRAM2LPEN               RCC_MEMLPENR_AHBSRAM2LPEN_Msk        /*!< AHBSRAM2 enable */
+#define RCC_MEMLPENR_BKPSRAMLPEN_Pos            (6U)
+#define RCC_MEMLPENR_BKPSRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */
+#define RCC_MEMLPENR_BKPSRAMLPEN                RCC_MEMLPENR_BKPSRAMLPEN_Msk         /*!< BKPSRAM enable */
+#define RCC_MEMLPENR_AXISRAM1LPEN_Pos           (7U)
+#define RCC_MEMLPENR_AXISRAM1LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_MEMLPENR_AXISRAM1LPEN               RCC_MEMLPENR_AXISRAM1LPEN_Msk        /*!< AXISRAM1 enable */
+#define RCC_MEMLPENR_AXISRAM2LPEN_Pos           (8U)
+#define RCC_MEMLPENR_AXISRAM2LPEN_Msk           (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos)  /*!< 0x00000100 */
+#define RCC_MEMLPENR_AXISRAM2LPEN               RCC_MEMLPENR_AXISRAM2LPEN_Msk        /*!< AXISRAM2 enable */
+#define RCC_MEMLPENR_FLEXRAMLPEN_Pos            (9U)
+#define RCC_MEMLPENR_FLEXRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */
+#define RCC_MEMLPENR_FLEXRAMLPEN                RCC_MEMLPENR_FLEXRAMLPEN_Msk         /*!< FLEXRAM enable */
+#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos        (10U)
+#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk        (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos)     /*!< 0x00000400 */
+#define RCC_MEMLPENR_CACHEAXIRAMLPEN            RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk     /*!< CACHEAXIRAM enable */
+#define RCC_MEMLPENR_VENCRAMLPEN_Pos            (11U)
+#define RCC_MEMLPENR_VENCRAMLPEN_Msk            (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */
+#define RCC_MEMLPENR_VENCRAMLPEN                RCC_MEMLPENR_VENCRAMLPEN_Msk         /*!< VENCRAM enable */
+#define RCC_MEMLPENR_BOOTROMLPEN_Pos            (12U)
+#define RCC_MEMLPENR_BOOTROMLPEN_Msk            (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */
+#define RCC_MEMLPENR_BOOTROMLPEN                RCC_MEMLPENR_BOOTROMLPEN_Msk         /*!< Boot ROM enable */
+
+/****************  Bit definition for RCC_AHB1LPENR register  *****************/
+#define RCC_AHB1LPENR_GPDMA1LPEN_Pos            (4U)
+#define RCC_AHB1LPENR_GPDMA1LPEN_Msk            (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPDMA1LPEN                RCC_AHB1LPENR_GPDMA1LPEN_Msk         /*!< GPDMA1 enable */
+#define RCC_AHB1LPENR_ADC12LPEN_Pos             (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk             (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                 RCC_AHB1LPENR_ADC12LPEN_Msk          /*!< ADC12 enable */
+
+/****************  Bit definition for RCC_AHB2LPENR register  *****************/
+#define RCC_AHB2LPENR_RAMCFGLPEN_Pos            (12U)
+#define RCC_AHB2LPENR_RAMCFGLPEN_Msk            (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2LPENR_RAMCFGLPEN                RCC_AHB2LPENR_RAMCFGLPEN_Msk         /*!< RAMCFG enable */
+#define RCC_AHB2LPENR_MDF1LPEN_Pos              (16U)
+#define RCC_AHB2LPENR_MDF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENR_MDF1LPEN                  RCC_AHB2LPENR_MDF1LPEN_Msk           /*!< MDF1 enable */
+#define RCC_AHB2LPENR_ADF1LPEN_Pos              (17U)
+#define RCC_AHB2LPENR_ADF1LPEN_Msk              (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENR_ADF1LPEN                  RCC_AHB2LPENR_ADF1LPEN_Msk           /*!< ADF1 enable */
+
+/****************  Bit definition for RCC_AHB3LPENR register  *****************/
+#define RCC_AHB3LPENR_RNGLPEN_Pos               (0U)
+#define RCC_AHB3LPENR_RNGLPEN_Msk               (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3LPENR_RNGLPEN                   RCC_AHB3LPENR_RNGLPEN_Msk            /*!< RNG enable */
+#define RCC_AHB3LPENR_HASHLPEN_Pos              (1U)
+#define RCC_AHB3LPENR_HASHLPEN_Msk              (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENR_HASHLPEN                  RCC_AHB3LPENR_HASHLPEN_Msk           /*!< HASH enable */
+#define RCC_AHB3LPENR_CRYPLPEN_Pos              (2U)
+#define RCC_AHB3LPENR_CRYPLPEN_Msk              (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB3LPENR_CRYPLPEN                  RCC_AHB3LPENR_CRYPLPEN_Msk           /*!< CRYP enable */
+#define RCC_AHB3LPENR_SAESLPEN_Pos              (4U)
+#define RCC_AHB3LPENR_SAESLPEN_Msk              (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB3LPENR_SAESLPEN                  RCC_AHB3LPENR_SAESLPEN_Msk           /*!< SAES enable */
+#define RCC_AHB3LPENR_PKALPEN_Pos               (8U)
+#define RCC_AHB3LPENR_PKALPEN_Msk               (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3LPENR_PKALPEN                   RCC_AHB3LPENR_PKALPEN_Msk            /*!< PKA enable */
+#define RCC_AHB3LPENR_RIFSCLPEN_Pos             (9U)
+#define RCC_AHB3LPENR_RIFSCLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */
+#define RCC_AHB3LPENR_RIFSCLPEN                 RCC_AHB3LPENR_RIFSCLPEN_Msk          /*!< RIFSC enable */
+#define RCC_AHB3LPENR_IACLPEN_Pos               (10U)
+#define RCC_AHB3LPENR_IACLPEN_Msk               (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3LPENR_IACLPEN                   RCC_AHB3LPENR_IACLPEN_Msk            /*!< IAC enable */
+#define RCC_AHB3LPENR_RISAFLPEN_Pos             (14U)
+#define RCC_AHB3LPENR_RISAFLPEN_Msk             (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB3LPENR_RISAFLPEN                 RCC_AHB3LPENR_RISAFLPEN_Msk          /*!< RISAF enable */
+
+/****************  Bit definition for RCC_AHB4LPENR register  *****************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos             (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                 RCC_AHB4LPENR_GPIOALPEN_Msk          /*!< GPIO A enable */
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos             (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                 RCC_AHB4LPENR_GPIOBLPEN_Msk          /*!< GPIO B enable */
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos             (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                 RCC_AHB4LPENR_GPIOCLPEN_Msk          /*!< GPIO C enable */
+#define RCC_AHB4LPENR_GPIODLPEN_Pos             (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                 RCC_AHB4LPENR_GPIODLPEN_Msk          /*!< GPIO D enable */
+#define RCC_AHB4LPENR_GPIOELPEN_Pos             (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                 RCC_AHB4LPENR_GPIOELPEN_Msk          /*!< GPIO E enable */
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos             (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                 RCC_AHB4LPENR_GPIOFLPEN_Msk          /*!< GPIO F enable */
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos             (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                 RCC_AHB4LPENR_GPIOGLPEN_Msk          /*!< GPIO G enable */
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos             (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                 RCC_AHB4LPENR_GPIOHLPEN_Msk          /*!< GPIO H enable */
+#define RCC_AHB4LPENR_GPIONLPEN_Pos             (13U)
+#define RCC_AHB4LPENR_GPIONLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB4LPENR_GPIONLPEN                 RCC_AHB4LPENR_GPIONLPEN_Msk          /*!< GPIO N enable */
+#define RCC_AHB4LPENR_GPIOOLPEN_Pos             (14U)
+#define RCC_AHB4LPENR_GPIOOLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */
+#define RCC_AHB4LPENR_GPIOOLPEN                 RCC_AHB4LPENR_GPIOOLPEN_Msk          /*!< GPIO O enable */
+#define RCC_AHB4LPENR_GPIOPLPEN_Pos             (15U)
+#define RCC_AHB4LPENR_GPIOPLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */
+#define RCC_AHB4LPENR_GPIOPLPEN                 RCC_AHB4LPENR_GPIOPLPEN_Msk          /*!< GPIO P enable */
+#define RCC_AHB4LPENR_GPIOQLPEN_Pos             (16U)
+#define RCC_AHB4LPENR_GPIOQLPEN_Msk             (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */
+#define RCC_AHB4LPENR_GPIOQLPEN                 RCC_AHB4LPENR_GPIOQLPEN_Msk          /*!< GPIO Q enable */
+#define RCC_AHB4LPENR_PWRLPEN_Pos               (18U)
+#define RCC_AHB4LPENR_PWRLPEN_Msk               (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4LPENR_PWRLPEN                   RCC_AHB4LPENR_PWRLPEN_Msk            /*!< PWR enable */
+#define RCC_AHB4LPENR_CRCLPEN_Pos               (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk               (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                   RCC_AHB4LPENR_CRCLPEN_Msk            /*!< CRC enable */
+
+/****************  Bit definition for RCC_AHB5LPENR register  *****************/
+#define RCC_AHB5LPENR_HPDMA1LPEN_Pos            (0U)
+#define RCC_AHB5LPENR_HPDMA1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB5LPENR_HPDMA1LPEN                RCC_AHB5LPENR_HPDMA1LPEN_Msk         /*!< HPDMA1 enable */
+#define RCC_AHB5LPENR_DMA2DLPEN_Pos             (1U)
+#define RCC_AHB5LPENR_DMA2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */
+#define RCC_AHB5LPENR_DMA2DLPEN                 RCC_AHB5LPENR_DMA2DLPEN_Msk          /*!< DMA2D enable */
+#define RCC_AHB5LPENR_JPEGLPEN_Pos              (3U)
+#define RCC_AHB5LPENR_JPEGLPEN_Msk              (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENR_JPEGLPEN                  RCC_AHB5LPENR_JPEGLPEN_Msk           /*!< JPEG enable */
+#define RCC_AHB5LPENR_FMCLPEN_Pos               (4U)
+#define RCC_AHB5LPENR_FMCLPEN_Msk               (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5LPENR_FMCLPEN                   RCC_AHB5LPENR_FMCLPEN_Msk            /*!< FMC enable */
+#define RCC_AHB5LPENR_XSPI1LPEN_Pos             (5U)
+#define RCC_AHB5LPENR_XSPI1LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */
+#define RCC_AHB5LPENR_XSPI1LPEN                 RCC_AHB5LPENR_XSPI1LPEN_Msk          /*!< XSPI1 enable */
+#define RCC_AHB5LPENR_PSSILPEN_Pos              (6U)
+#define RCC_AHB5LPENR_PSSILPEN_Msk              (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENR_PSSILPEN                  RCC_AHB5LPENR_PSSILPEN_Msk           /*!< PSSI enable */
+#define RCC_AHB5LPENR_SDMMC2LPEN_Pos            (7U)
+#define RCC_AHB5LPENR_SDMMC2LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB5LPENR_SDMMC2LPEN                RCC_AHB5LPENR_SDMMC2LPEN_Msk         /*!< SDMMC2 enable */
+#define RCC_AHB5LPENR_SDMMC1LPEN_Pos            (8U)
+#define RCC_AHB5LPENR_SDMMC1LPEN_Msk            (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB5LPENR_SDMMC1LPEN                RCC_AHB5LPENR_SDMMC1LPEN_Msk         /*!< SDMMC1 enable */
+#define RCC_AHB5LPENR_XSPI2LPEN_Pos             (12U)
+#define RCC_AHB5LPENR_XSPI2LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */
+#define RCC_AHB5LPENR_XSPI2LPEN                 RCC_AHB5LPENR_XSPI2LPEN_Msk          /*!< XSPI2 enable */
+#define RCC_AHB5LPENR_XSPIMLPEN_Pos             (13U)
+#define RCC_AHB5LPENR_XSPIMLPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */
+#define RCC_AHB5LPENR_XSPIMLPEN                 RCC_AHB5LPENR_XSPIMLPEN_Msk          /*!< XSPIM enable */
+#define RCC_AHB5LPENR_MCE1LPEN_Pos              (14U)
+#define RCC_AHB5LPENR_MCE1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB5LPENR_MCE1LPEN                  RCC_AHB5LPENR_MCE1LPEN_Msk           /*!< MCE1 enable */
+#define RCC_AHB5LPENR_MCE2LPEN_Pos              (15U)
+#define RCC_AHB5LPENR_MCE2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB5LPENR_MCE2LPEN                  RCC_AHB5LPENR_MCE2LPEN_Msk           /*!< MCE2 enable */
+#define RCC_AHB5LPENR_MCE3LPEN_Pos              (16U)
+#define RCC_AHB5LPENR_MCE3LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB5LPENR_MCE3LPEN                  RCC_AHB5LPENR_MCE3LPEN_Msk           /*!< MCE3 enable */
+#define RCC_AHB5LPENR_XSPI3LPEN_Pos             (17U)
+#define RCC_AHB5LPENR_XSPI3LPEN_Msk             (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */
+#define RCC_AHB5LPENR_XSPI3LPEN                 RCC_AHB5LPENR_XSPI3LPEN_Msk          /*!< XSPI3 enable */
+#define RCC_AHB5LPENR_MCE4LPEN_Pos              (18U)
+#define RCC_AHB5LPENR_MCE4LPEN_Msk              (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB5LPENR_MCE4LPEN                  RCC_AHB5LPENR_MCE4LPEN_Msk           /*!< MCE4 enable */
+#define RCC_AHB5LPENR_GFXMMULPEN_Pos            (19U)
+#define RCC_AHB5LPENR_GFXMMULPEN_Msk            (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB5LPENR_GFXMMULPEN                RCC_AHB5LPENR_GFXMMULPEN_Msk         /*!< GFXMMU enable */
+#define RCC_AHB5LPENR_GPU2DLPEN_Pos             (20U)
+#define RCC_AHB5LPENR_GPU2DLPEN_Msk             (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */
+#define RCC_AHB5LPENR_GPU2DLPEN                 RCC_AHB5LPENR_GPU2DLPEN_Msk          /*!< GPU2D enable */
+#define RCC_AHB5LPENR_ETH1MACLPEN_Pos           (22U)
+#define RCC_AHB5LPENR_ETH1MACLPEN_Msk           (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos)  /*!< 0x00400000 */
+#define RCC_AHB5LPENR_ETH1MACLPEN               RCC_AHB5LPENR_ETH1MACLPEN_Msk        /*!< ETH1MAC enable */
+#define RCC_AHB5LPENR_ETH1TXLPEN_Pos            (23U)
+#define RCC_AHB5LPENR_ETH1TXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB5LPENR_ETH1TXLPEN                RCC_AHB5LPENR_ETH1TXLPEN_Msk         /*!< ETH1TX enable */
+#define RCC_AHB5LPENR_ETH1RXLPEN_Pos            (24U)
+#define RCC_AHB5LPENR_ETH1RXLPEN_Msk            (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB5LPENR_ETH1RXLPEN                RCC_AHB5LPENR_ETH1RXLPEN_Msk         /*!< ETH1RX enable */
+#define RCC_AHB5LPENR_ETH1LPEN_Pos              (25U)
+#define RCC_AHB5LPENR_ETH1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENR_ETH1LPEN                  RCC_AHB5LPENR_ETH1LPEN_Msk           /*!< ETH1 enable */
+#define RCC_AHB5LPENR_OTG1LPEN_Pos              (26U)
+#define RCC_AHB5LPENR_OTG1LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENR_OTG1LPEN                  RCC_AHB5LPENR_OTG1LPEN_Msk           /*!< OTG1 enable */
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos           (27U)
+#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5LPENR_OTGPHY1LPEN               RCC_AHB5LPENR_OTGPHY1LPEN_Msk        /*!< OTGPHY1 enable */
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos           (28U)
+#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk           (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5LPENR_OTGPHY2LPEN               RCC_AHB5LPENR_OTGPHY2LPEN_Msk        /*!< OTGPHY2 enable */
+#define RCC_AHB5LPENR_OTG2LPEN_Pos              (29U)
+#define RCC_AHB5LPENR_OTG2LPEN_Msk              (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENR_OTG2LPEN                  RCC_AHB5LPENR_OTG2LPEN_Msk           /*!< OTG2 enable */
+#define RCC_AHB5LPENR_CACHEAXILPEN_Pos          (30U)
+#define RCC_AHB5LPENR_CACHEAXILPEN_Msk          (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos)   /*!< 0x40000000 */
+#define RCC_AHB5LPENR_CACHEAXILPEN              RCC_AHB5LPENR_CACHEAXILPEN_Msk       /*!< CACHEAXI enable */
+#define RCC_AHB5LPENR_NPULPEN_Pos               (31U)
+#define RCC_AHB5LPENR_NPULPEN_Msk               (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos)  /*!< 0x80000000 */
+#define RCC_AHB5LPENR_NPULPEN                   RCC_AHB5LPENR_NPULPEN_Msk            /*!< NPU enable */
+
+/****************  Bit definition for RCC_APB1LPENR1 register  ****************/
+#define RCC_APB1LPENR1_TIM2LPEN_Pos             (0U)
+#define RCC_APB1LPENR1_TIM2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */
+#define RCC_APB1LPENR1_TIM2LPEN                 RCC_APB1LPENR1_TIM2LPEN_Msk          /*!< TIM2 enable */
+#define RCC_APB1LPENR1_TIM3LPEN_Pos             (1U)
+#define RCC_APB1LPENR1_TIM3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB1LPENR1_TIM3LPEN                 RCC_APB1LPENR1_TIM3LPEN_Msk          /*!< TIM3 enable */
+#define RCC_APB1LPENR1_TIM4LPEN_Pos             (2U)
+#define RCC_APB1LPENR1_TIM4LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */
+#define RCC_APB1LPENR1_TIM4LPEN                 RCC_APB1LPENR1_TIM4LPEN_Msk          /*!< TIM4 enable */
+#define RCC_APB1LPENR1_TIM5LPEN_Pos             (3U)
+#define RCC_APB1LPENR1_TIM5LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */
+#define RCC_APB1LPENR1_TIM5LPEN                 RCC_APB1LPENR1_TIM5LPEN_Msk          /*!< TIM5 enable */
+#define RCC_APB1LPENR1_TIM6LPEN_Pos             (4U)
+#define RCC_APB1LPENR1_TIM6LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */
+#define RCC_APB1LPENR1_TIM6LPEN                 RCC_APB1LPENR1_TIM6LPEN_Msk          /*!< TIM6 enable */
+#define RCC_APB1LPENR1_TIM7LPEN_Pos             (5U)
+#define RCC_APB1LPENR1_TIM7LPEN_Msk             (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB1LPENR1_TIM7LPEN                 RCC_APB1LPENR1_TIM7LPEN_Msk          /*!< TIM7 enable */
+#define RCC_APB1LPENR1_TIM12LPEN_Pos            (6U)
+#define RCC_APB1LPENR1_TIM12LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR1_TIM12LPEN                RCC_APB1LPENR1_TIM12LPEN_Msk         /*!< TIM12 enable */
+#define RCC_APB1LPENR1_TIM13LPEN_Pos            (7U)
+#define RCC_APB1LPENR1_TIM13LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR1_TIM13LPEN                RCC_APB1LPENR1_TIM13LPEN_Msk         /*!< TIM13 enable */
+#define RCC_APB1LPENR1_TIM14LPEN_Pos            (8U)
+#define RCC_APB1LPENR1_TIM14LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR1_TIM14LPEN                RCC_APB1LPENR1_TIM14LPEN_Msk         /*!< TIM14 enable */
+#define RCC_APB1LPENR1_LPTIM1LPEN_Pos           (9U)
+#define RCC_APB1LPENR1_LPTIM1LPEN_Msk           (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1LPENR1_LPTIM1LPEN               RCC_APB1LPENR1_LPTIM1LPEN_Msk        /*!< LPTIM1 enable */
+#define RCC_APB1LPENR1_WWDGLPEN_Pos             (11U)
+#define RCC_APB1LPENR1_WWDGLPEN_Msk             (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */
+#define RCC_APB1LPENR1_WWDGLPEN                 RCC_APB1LPENR1_WWDGLPEN_Msk          /*!< WWDG enable */
+#define RCC_APB1LPENR1_TIM10LPEN_Pos            (12U)
+#define RCC_APB1LPENR1_TIM10LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB1LPENR1_TIM10LPEN                RCC_APB1LPENR1_TIM10LPEN_Msk         /*!< TIM10 enable */
+#define RCC_APB1LPENR1_TIM11LPEN_Pos            (13U)
+#define RCC_APB1LPENR1_TIM11LPEN_Msk            (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB1LPENR1_TIM11LPEN                RCC_APB1LPENR1_TIM11LPEN_Msk         /*!< TIM11 enable */
+#define RCC_APB1LPENR1_SPI2LPEN_Pos             (14U)
+#define RCC_APB1LPENR1_SPI2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */
+#define RCC_APB1LPENR1_SPI2LPEN                 RCC_APB1LPENR1_SPI2LPEN_Msk          /*!< SPI2 enable */
+#define RCC_APB1LPENR1_SPI3LPEN_Pos             (15U)
+#define RCC_APB1LPENR1_SPI3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB1LPENR1_SPI3LPEN                 RCC_APB1LPENR1_SPI3LPEN_Msk          /*!< SPI3 enable */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos         (16U)
+#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk         (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos)    /*!< 0x00010000 */
+#define RCC_APB1LPENR1_SPDIFRX1LPEN             RCC_APB1LPENR1_SPDIFRX1LPEN_Msk      /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENR1_USART2LPEN_Pos           (17U)
+#define RCC_APB1LPENR1_USART2LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1LPENR1_USART2LPEN               RCC_APB1LPENR1_USART2LPEN_Msk        /*!< USART2 enable */
+#define RCC_APB1LPENR1_USART3LPEN_Pos           (18U)
+#define RCC_APB1LPENR1_USART3LPEN_Msk           (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1LPENR1_USART3LPEN               RCC_APB1LPENR1_USART3LPEN_Msk        /*!< USART3 enable */
+#define RCC_APB1LPENR1_UART4LPEN_Pos            (19U)
+#define RCC_APB1LPENR1_UART4LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR1_UART4LPEN                RCC_APB1LPENR1_UART4LPEN_Msk         /*!< UART4 enable */
+#define RCC_APB1LPENR1_UART5LPEN_Pos            (20U)
+#define RCC_APB1LPENR1_UART5LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR1_UART5LPEN                RCC_APB1LPENR1_UART5LPEN_Msk         /*!< UART5 enable */
+#define RCC_APB1LPENR1_I2C1LPEN_Pos             (21U)
+#define RCC_APB1LPENR1_I2C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */
+#define RCC_APB1LPENR1_I2C1LPEN                 RCC_APB1LPENR1_I2C1LPEN_Msk          /*!< I2C1 enable */
+#define RCC_APB1LPENR1_I2C2LPEN_Pos             (22U)
+#define RCC_APB1LPENR1_I2C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */
+#define RCC_APB1LPENR1_I2C2LPEN                 RCC_APB1LPENR1_I2C2LPEN_Msk          /*!< I2C2 enable */
+#define RCC_APB1LPENR1_I2C3LPEN_Pos             (23U)
+#define RCC_APB1LPENR1_I2C3LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */
+#define RCC_APB1LPENR1_I2C3LPEN                 RCC_APB1LPENR1_I2C3LPEN_Msk          /*!< I2C3 enable */
+#define RCC_APB1LPENR1_I3C1LPEN_Pos             (24U)
+#define RCC_APB1LPENR1_I3C1LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */
+#define RCC_APB1LPENR1_I3C1LPEN                 RCC_APB1LPENR1_I3C1LPEN_Msk          /*!< I3C1 enable */
+#define RCC_APB1LPENR1_I3C2LPEN_Pos             (25U)
+#define RCC_APB1LPENR1_I3C2LPEN_Msk             (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */
+#define RCC_APB1LPENR1_I3C2LPEN                 RCC_APB1LPENR1_I3C2LPEN_Msk          /*!< I3C2 enable */
+#define RCC_APB1LPENR1_UART7LPEN_Pos            (30U)
+#define RCC_APB1LPENR1_UART7LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR1_UART7LPEN                RCC_APB1LPENR1_UART7LPEN_Msk         /*!< UART7 enable */
+#define RCC_APB1LPENR1_UART8LPEN_Pos            (31U)
+#define RCC_APB1LPENR1_UART8LPEN_Msk            (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR1_UART8LPEN                RCC_APB1LPENR1_UART8LPEN_Msk         /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1LPENR2 register  ****************/
+#define RCC_APB1LPENR2_MDIOSLPEN_Pos            (5U)
+#define RCC_APB1LPENR2_MDIOSLPEN_Msk            (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR2_MDIOSLPEN                RCC_APB1LPENR2_MDIOSLPEN_Msk         /*!< MDIOS enable in Sleep mode */
+#define RCC_APB1LPENR2_FDCANLPEN_Pos            (8U)
+#define RCC_APB1LPENR2_FDCANLPEN_Msk            (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR2_FDCANLPEN                RCC_APB1LPENR2_FDCANLPEN_Msk         /*!< FDCAN enablein Sleep mode */
+#define RCC_APB1LPENR2_UCPD1LPEN_Pos            (18U)
+#define RCC_APB1LPENR2_UCPD1LPEN_Msk            (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR2_UCPD1LPEN                RCC_APB1LPENR2_UCPD1LPEN_Msk         /*!< UCPD1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_APB2LPENR register  *****************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos              (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                  RCC_APB2LPENR_TIM1LPEN_Msk           /*!< TIM1 enable */
+#define RCC_APB2LPENR_TIM8LPEN_Pos              (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                  RCC_APB2LPENR_TIM8LPEN_Msk           /*!< TIM8 enable */
+#define RCC_APB2LPENR_USART1LPEN_Pos            (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN                RCC_APB2LPENR_USART1LPEN_Msk         /*!< USART1 enable */
+#define RCC_APB2LPENR_USART6LPEN_Pos            (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk            (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN                RCC_APB2LPENR_USART6LPEN_Msk         /*!< USART6 enable */
+#define RCC_APB2LPENR_UART9LPEN_Pos             (6U)
+#define RCC_APB2LPENR_UART9LPEN_Msk             (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */
+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk          /*!< UART9 enable */
+#define RCC_APB2LPENR_USART10LPEN_Pos           (7U)
+#define RCC_APB2LPENR_USART10LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)  /*!< 0x00000080 */
+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk        /*!< USART10 enable */
+#define RCC_APB2LPENR_SPI1LPEN_Pos              (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                  RCC_APB2LPENR_SPI1LPEN_Msk           /*!< SPI1 enable */
+#define RCC_APB2LPENR_SPI4LPEN_Pos              (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                  RCC_APB2LPENR_SPI4LPEN_Msk           /*!< SPI4 enable */
+#define RCC_APB2LPENR_TIM18LPEN_Pos             (15U)
+#define RCC_APB2LPENR_TIM18LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */
+#define RCC_APB2LPENR_TIM18LPEN                 RCC_APB2LPENR_TIM18LPEN_Msk          /*!< TIM18 enable */
+#define RCC_APB2LPENR_TIM15LPEN_Pos             (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                 RCC_APB2LPENR_TIM15LPEN_Msk          /*!< TIM15 enable */
+#define RCC_APB2LPENR_TIM16LPEN_Pos             (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                 RCC_APB2LPENR_TIM16LPEN_Msk          /*!< TIM16 enable */
+#define RCC_APB2LPENR_TIM17LPEN_Pos             (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                 RCC_APB2LPENR_TIM17LPEN_Msk          /*!< TIM17 enable */
+#define RCC_APB2LPENR_TIM9LPEN_Pos              (19U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk              (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENR_TIM9LPEN                  RCC_APB2LPENR_TIM9LPEN_Msk           /*!< TIM9 enable */
+#define RCC_APB2LPENR_SPI5LPEN_Pos              (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk              (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                  RCC_APB2LPENR_SPI5LPEN_Msk           /*!< SPI5 enable */
+#define RCC_APB2LPENR_SAI1LPEN_Pos              (21U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SAI1LPEN                  RCC_APB2LPENR_SAI1LPEN_Msk           /*!< SAI1 enable */
+#define RCC_APB2LPENR_SAI2LPEN_Pos              (22U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk              (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI2LPEN                  RCC_APB2LPENR_SAI2LPEN_Msk           /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENR register  *****************/
+#define RCC_APB3LPENR_DFTLPEN_Pos               (2U)
+#define RCC_APB3LPENR_DFTLPEN_Msk               (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos)  /*!< 0x00000004 */
+#define RCC_APB3LPENR_DFTLPEN                   RCC_APB3LPENR_DFTLPEN_Msk            /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4LPENR1 register  ****************/
+#define RCC_APB4LPENR1_HDPLPEN_Pos              (2U)
+#define RCC_APB4LPENR1_HDPLPEN_Msk              (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR1_HDPLPEN                  RCC_APB4LPENR1_HDPLPEN_Msk           /*!< HDP enable */
+#define RCC_APB4LPENR1_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR1_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos)   /*!< 0x00000008 */
+#define RCC_APB4LPENR1_LPUART1LPEN              RCC_APB4LPENR1_LPUART1LPEN_Msk       /*!< LPUART1 enable */
+#define RCC_APB4LPENR1_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR1_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */
+#define RCC_APB4LPENR1_SPI6LPEN                 RCC_APB4LPENR1_SPI6LPEN_Msk          /*!< SPI6 enable */
+#define RCC_APB4LPENR1_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR1_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */
+#define RCC_APB4LPENR1_I2C4LPEN                 RCC_APB4LPENR1_I2C4LPEN_Msk          /*!< I2C4 enable */
+#define RCC_APB4LPENR1_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR1_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB4LPENR1_LPTIM2LPEN               RCC_APB4LPENR1_LPTIM2LPEN_Msk        /*!< LPTIM2 enable */
+#define RCC_APB4LPENR1_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR1_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos)  /*!< 0x00000400 */
+#define RCC_APB4LPENR1_LPTIM3LPEN               RCC_APB4LPENR1_LPTIM3LPEN_Msk        /*!< LPTIM3 enable */
+#define RCC_APB4LPENR1_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR1_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos)  /*!< 0x00000800 */
+#define RCC_APB4LPENR1_LPTIM4LPEN               RCC_APB4LPENR1_LPTIM4LPEN_Msk        /*!< LPTIM4 enable */
+#define RCC_APB4LPENR1_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR1_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos)  /*!< 0x00001000 */
+#define RCC_APB4LPENR1_LPTIM5LPEN               RCC_APB4LPENR1_LPTIM5LPEN_Msk        /*!< LPTIM5 enable */
+#define RCC_APB4LPENR1_VREFBUFLPEN_Pos          (15U)
+#define RCC_APB4LPENR1_VREFBUFLPEN_Msk          (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos)   /*!< 0x00008000 */
+#define RCC_APB4LPENR1_VREFBUFLPEN              RCC_APB4LPENR1_VREFBUFLPEN_Msk       /*!< VREFBUF enable */
+#define RCC_APB4LPENR1_RTCLPEN_Pos              (16U)
+#define RCC_APB4LPENR1_RTCLPEN_Msk              (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR1_RTCLPEN                  RCC_APB4LPENR1_RTCLPEN_Msk           /*!< RTC enable */
+#define RCC_APB4LPENR1_RTCAPBLPEN_Pos           (17U)
+#define RCC_APB4LPENR1_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos)  /*!< 0x00020000 */
+#define RCC_APB4LPENR1_RTCAPBLPEN               RCC_APB4LPENR1_RTCAPBLPEN_Msk        /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4LPENR2 register  ****************/
+#define RCC_APB4LPENR2_SYSCFGLPEN_Pos           (0U)
+#define RCC_APB4LPENR2_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos)  /*!< 0x00000001 */
+#define RCC_APB4LPENR2_SYSCFGLPEN               RCC_APB4LPENR2_SYSCFGLPEN_Msk        /*!< SYSCFG enable */
+#define RCC_APB4LPENR2_BSECLPEN_Pos             (1U)
+#define RCC_APB4LPENR2_BSECLPEN_Msk             (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */
+#define RCC_APB4LPENR2_BSECLPEN                 RCC_APB4LPENR2_BSECLPEN_Msk          /*!< BSEC enable */
+#define RCC_APB4LPENR2_DTSLPEN_Pos              (2U)
+#define RCC_APB4LPENR2_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENR2_DTSLPEN                  RCC_APB4LPENR2_DTSLPEN_Msk           /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENR register  *****************/
+#define RCC_APB5LPENR_LTDCLPEN_Pos              (1U)
+#define RCC_APB5LPENR_LTDCLPEN_Msk              (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENR_LTDCLPEN                  RCC_APB5LPENR_LTDCLPEN_Msk           /*!< LTDC enable */
+#define RCC_APB5LPENR_DCMIPPLPEN_Pos            (2U)
+#define RCC_APB5LPENR_DCMIPPLPEN_Msk            (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB5LPENR_DCMIPPLPEN                RCC_APB5LPENR_DCMIPPLPEN_Msk         /*!< DCMIPP enable */
+#define RCC_APB5LPENR_GFXTIMLPEN_Pos            (4U)
+#define RCC_APB5LPENR_GFXTIMLPEN_Msk            (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB5LPENR_GFXTIMLPEN                RCC_APB5LPENR_GFXTIMLPEN_Msk         /*!< GFXTIM enable */
+#define RCC_APB5LPENR_VENCLPEN_Pos              (5U)
+#define RCC_APB5LPENR_VENCLPEN_Msk              (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENR_VENCLPEN                  RCC_APB5LPENR_VENCLPEN_Msk           /*!< VENC enable */
+#define RCC_APB5LPENR_CSILPEN_Pos               (6U)
+#define RCC_APB5LPENR_CSILPEN_Msk               (0x1UL << RCC_APB5LPENR_CSILPEN_Pos)  /*!< 0x00000040 */
+#define RCC_APB5LPENR_CSILPEN                   RCC_APB5LPENR_CSILPEN_Msk            /*!< CSI enable */
+
+/*******************  Bit definition for RCC_RDCR register  *******************/
+#define RCC_RDCR_MRD_Pos                        (16U)
+#define RCC_RDCR_MRD_Msk                        (0x1FUL << RCC_RDCR_MRD_Pos)          /*!< 0x001F0000 */
+#define RCC_RDCR_MRD                            RCC_RDCR_MRD_Msk                     /*!< Minimum reset duration */
+
+/*****************  Bit definition for RCC_SECCFGR0 register  *****************/
+#define RCC_SECCFGR0_LSISEC_Pos                 (0U)
+#define RCC_SECCFGR0_LSISEC_Msk                 (0x1UL << RCC_SECCFGR0_LSISEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR0_LSISEC                     RCC_SECCFGR0_LSISEC_Msk              /*!< Secure protection of LSI oscillator configuration bits */
+#define RCC_SECCFGR0_LSESEC_Pos                 (1U)
+#define RCC_SECCFGR0_LSESEC_Msk                 (0x1UL << RCC_SECCFGR0_LSESEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR0_LSESEC                     RCC_SECCFGR0_LSESEC_Msk              /*!< Secure protection of LSE oscillator configuration bits */
+#define RCC_SECCFGR0_MSISEC_Pos                 (2U)
+#define RCC_SECCFGR0_MSISEC_Msk                 (0x1UL << RCC_SECCFGR0_MSISEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR0_MSISEC                     RCC_SECCFGR0_MSISEC_Msk              /*!< Secure protection of MSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSISEC_Pos                 (3U)
+#define RCC_SECCFGR0_HSISEC_Msk                 (0x1UL << RCC_SECCFGR0_HSISEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR0_HSISEC                     RCC_SECCFGR0_HSISEC_Msk              /*!< Secure protection of HSI oscillator configuration bits */
+#define RCC_SECCFGR0_HSESEC_Pos                 (4U)
+#define RCC_SECCFGR0_HSESEC_Msk                 (0x1UL << RCC_SECCFGR0_HSESEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR0_HSESEC                     RCC_SECCFGR0_HSESEC_Msk              /*!< Secure protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR0 register  *****************/
+#define RCC_PRIVCFGR0_LSIPRIV_Pos               (0U)
+#define RCC_PRIVCFGR0_LSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR0_LSIPRIV                   RCC_PRIVCFGR0_LSIPRIV_Msk            /*!< Privileged protection of LSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_LSEPRIV_Pos               (1U)
+#define RCC_PRIVCFGR0_LSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR0_LSEPRIV                   RCC_PRIVCFGR0_LSEPRIV_Msk            /*!< Privileged protection of LSE oscillator configuration bits */
+#define RCC_PRIVCFGR0_MSIPRIV_Pos               (2U)
+#define RCC_PRIVCFGR0_MSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR0_MSIPRIV                   RCC_PRIVCFGR0_MSIPRIV_Msk            /*!< Privileged protection of MSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSIPRIV_Pos               (3U)
+#define RCC_PRIVCFGR0_HSIPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR0_HSIPRIV                   RCC_PRIVCFGR0_HSIPRIV_Msk            /*!< Privileged protection of HSI oscillator configuration bits */
+#define RCC_PRIVCFGR0_HSEPRIV_Pos               (4U)
+#define RCC_PRIVCFGR0_HSEPRIV_Msk               (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR0_HSEPRIV                   RCC_PRIVCFGR0_HSEPRIV_Msk            /*!< Privileged protection of HSE oscillator configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR0 register  *****************/
+#define RCC_LOCKCFGR0_LSILOCK_Pos               (0U)
+#define RCC_LOCKCFGR0_LSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR0_LSILOCK                   RCC_LOCKCFGR0_LSILOCK_Msk            /*!< Locked protection of LSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_LSELOCK_Pos               (1U)
+#define RCC_LOCKCFGR0_LSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR0_LSELOCK                   RCC_LOCKCFGR0_LSELOCK_Msk            /*!< Locked protection of LSE oscillator configuration bits */
+#define RCC_LOCKCFGR0_MSILOCK_Pos               (2U)
+#define RCC_LOCKCFGR0_MSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR0_MSILOCK                   RCC_LOCKCFGR0_MSILOCK_Msk            /*!< Locked protection of MSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSILOCK_Pos               (3U)
+#define RCC_LOCKCFGR0_HSILOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR0_HSILOCK                   RCC_LOCKCFGR0_HSILOCK_Msk            /*!< Locked protection of HSI oscillator configuration bits */
+#define RCC_LOCKCFGR0_HSELOCK_Pos               (4U)
+#define RCC_LOCKCFGR0_HSELOCK_Msk               (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR0_HSELOCK                   RCC_LOCKCFGR0_HSELOCK_Msk            /*!< Locked protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR0 register  *****************/
+#define RCC_PUBCFGR0_LSIPUB_Pos                 (0U)
+#define RCC_PUBCFGR0_LSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR0_LSIPUB                     RCC_PUBCFGR0_LSIPUB_Msk              /*!< Public protection of LSI oscillator configuration bits */
+#define RCC_PUBCFGR0_LSEPUB_Pos                 (1U)
+#define RCC_PUBCFGR0_LSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR0_LSEPUB                     RCC_PUBCFGR0_LSEPUB_Msk              /*!< Public protection of LSE oscillator configuration bits */
+#define RCC_PUBCFGR0_MSIPUB_Pos                 (2U)
+#define RCC_PUBCFGR0_MSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR0_MSIPUB                     RCC_PUBCFGR0_MSIPUB_Msk              /*!< Public protection of MSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSIPUB_Pos                 (3U)
+#define RCC_PUBCFGR0_HSIPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR0_HSIPUB                     RCC_PUBCFGR0_HSIPUB_Msk              /*!< Public protection of HSI oscillator configuration bits */
+#define RCC_PUBCFGR0_HSEPUB_Pos                 (4U)
+#define RCC_PUBCFGR0_HSEPUB_Msk                 (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR0_HSEPUB                     RCC_PUBCFGR0_HSEPUB_Msk              /*!< Public protection of HSE oscillator configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR1 register  *****************/
+#define RCC_SECCFGR1_PLL1SEC_Pos                (0U)
+#define RCC_SECCFGR1_PLL1SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos)   /*!< 0x00000001 */
+#define RCC_SECCFGR1_PLL1SEC                    RCC_SECCFGR1_PLL1SEC_Msk             /*!< Secure protection of PLL1 configuration bits */
+#define RCC_SECCFGR1_PLL2SEC_Pos                (1U)
+#define RCC_SECCFGR1_PLL2SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos)   /*!< 0x00000002 */
+#define RCC_SECCFGR1_PLL2SEC                    RCC_SECCFGR1_PLL2SEC_Msk             /*!< Secure protection of PLL2 configuration bits */
+#define RCC_SECCFGR1_PLL3SEC_Pos                (2U)
+#define RCC_SECCFGR1_PLL3SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR1_PLL3SEC                    RCC_SECCFGR1_PLL3SEC_Msk             /*!< Secure protection of PLL3 configuration bits */
+#define RCC_SECCFGR1_PLL4SEC_Pos                (3U)
+#define RCC_SECCFGR1_PLL4SEC_Msk                (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR1_PLL4SEC                    RCC_SECCFGR1_PLL4SEC_Msk             /*!< Secure protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR1 register  *****************/
+#define RCC_PRIVCFGR1_PLL1PRIV_Pos              (0U)
+#define RCC_PRIVCFGR1_PLL1PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGR1_PLL1PRIV                  RCC_PRIVCFGR1_PLL1PRIV_Msk           /*!< Privileged protection of PLL1 configuration bits */
+#define RCC_PRIVCFGR1_PLL2PRIV_Pos              (1U)
+#define RCC_PRIVCFGR1_PLL2PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR1_PLL2PRIV                  RCC_PRIVCFGR1_PLL2PRIV_Msk           /*!< Privileged protection of PLL2 configuration bits */
+#define RCC_PRIVCFGR1_PLL3PRIV_Pos              (2U)
+#define RCC_PRIVCFGR1_PLL3PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR1_PLL3PRIV                  RCC_PRIVCFGR1_PLL3PRIV_Msk           /*!< Privileged protection of PLL3 configuration bits */
+#define RCC_PRIVCFGR1_PLL4PRIV_Pos              (3U)
+#define RCC_PRIVCFGR1_PLL4PRIV_Msk              (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR1_PLL4PRIV                  RCC_PRIVCFGR1_PLL4PRIV_Msk           /*!< Privileged protection of PLL4 configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR1 register  *****************/
+#define RCC_LOCKCFGR1_PLL1LOCK_Pos              (0U)
+#define RCC_LOCKCFGR1_PLL1LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */
+#define RCC_LOCKCFGR1_PLL1LOCK                  RCC_LOCKCFGR1_PLL1LOCK_Msk           /*!< Locked protection of PLL1 configuration bits */
+#define RCC_LOCKCFGR1_PLL2LOCK_Pos              (1U)
+#define RCC_LOCKCFGR1_PLL2LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR1_PLL2LOCK                  RCC_LOCKCFGR1_PLL2LOCK_Msk           /*!< Locked protection of PLL2 configuration bits */
+#define RCC_LOCKCFGR1_PLL3LOCK_Pos              (2U)
+#define RCC_LOCKCFGR1_PLL3LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR1_PLL3LOCK                  RCC_LOCKCFGR1_PLL3LOCK_Msk           /*!< Locked protection of PLL3 configuration bits */
+#define RCC_LOCKCFGR1_PLL4LOCK_Pos              (3U)
+#define RCC_LOCKCFGR1_PLL4LOCK_Msk              (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR1_PLL4LOCK                  RCC_LOCKCFGR1_PLL4LOCK_Msk           /*!< Locked protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR1 register  *****************/
+#define RCC_PUBCFGR1_PLL1PUB_Pos                (0U)
+#define RCC_PUBCFGR1_PLL1PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGR1_PLL1PUB                    RCC_PUBCFGR1_PLL1PUB_Msk             /*!< Public protection of PLL1 configuration bits */
+#define RCC_PUBCFGR1_PLL2PUB_Pos                (1U)
+#define RCC_PUBCFGR1_PLL2PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGR1_PLL2PUB                    RCC_PUBCFGR1_PLL2PUB_Msk             /*!< Public protection of PLL2 configuration bits */
+#define RCC_PUBCFGR1_PLL3PUB_Pos                (2U)
+#define RCC_PUBCFGR1_PLL3PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR1_PLL3PUB                    RCC_PUBCFGR1_PLL3PUB_Msk             /*!< Public protection of PLL3 configuration bits */
+#define RCC_PUBCFGR1_PLL4PUB_Pos                (3U)
+#define RCC_PUBCFGR1_PLL4PUB_Msk                (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR1_PLL4PUB                    RCC_PUBCFGR1_PLL4PUB_Msk             /*!< Public protection of PLL4 configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR2 register  *****************/
+#define RCC_SECCFGR2_IC1SEC_Pos                 (0U)
+#define RCC_SECCFGR2_IC1SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC1SEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR2_IC1SEC                     RCC_SECCFGR2_IC1SEC_Msk              /*!< Secure protection of IC1 divider configuration bits */
+#define RCC_SECCFGR2_IC2SEC_Pos                 (1U)
+#define RCC_SECCFGR2_IC2SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC2SEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR2_IC2SEC                     RCC_SECCFGR2_IC2SEC_Msk              /*!< Secure protection of IC2 divider configuration bits */
+#define RCC_SECCFGR2_IC3SEC_Pos                 (2U)
+#define RCC_SECCFGR2_IC3SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC3SEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR2_IC3SEC                     RCC_SECCFGR2_IC3SEC_Msk              /*!< Secure protection of IC3 divider configuration bits */
+#define RCC_SECCFGR2_IC4SEC_Pos                 (3U)
+#define RCC_SECCFGR2_IC4SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC4SEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR2_IC4SEC                     RCC_SECCFGR2_IC4SEC_Msk              /*!< Secure protection of IC4 divider configuration bits */
+#define RCC_SECCFGR2_IC5SEC_Pos                 (4U)
+#define RCC_SECCFGR2_IC5SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC5SEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR2_IC5SEC                     RCC_SECCFGR2_IC5SEC_Msk              /*!< Secure protection of IC5 divider configuration bits */
+#define RCC_SECCFGR2_IC6SEC_Pos                 (5U)
+#define RCC_SECCFGR2_IC6SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC6SEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR2_IC6SEC                     RCC_SECCFGR2_IC6SEC_Msk              /*!< Secure protection of IC6 divider configuration bits */
+#define RCC_SECCFGR2_IC7SEC_Pos                 (6U)
+#define RCC_SECCFGR2_IC7SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC7SEC_Pos)    /*!< 0x00000040 */
+#define RCC_SECCFGR2_IC7SEC                     RCC_SECCFGR2_IC7SEC_Msk              /*!< Secure protection of IC7 divider configuration bits */
+#define RCC_SECCFGR2_IC8SEC_Pos                 (7U)
+#define RCC_SECCFGR2_IC8SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC8SEC_Pos)    /*!< 0x00000080 */
+#define RCC_SECCFGR2_IC8SEC                     RCC_SECCFGR2_IC8SEC_Msk              /*!< Secure protection of IC8 divider configuration bits */
+#define RCC_SECCFGR2_IC9SEC_Pos                 (8U)
+#define RCC_SECCFGR2_IC9SEC_Msk                 (0x1UL << RCC_SECCFGR2_IC9SEC_Pos)    /*!< 0x00000100 */
+#define RCC_SECCFGR2_IC9SEC                     RCC_SECCFGR2_IC9SEC_Msk              /*!< Secure protection of IC9 divider configuration bits */
+#define RCC_SECCFGR2_IC10SEC_Pos                (9U)
+#define RCC_SECCFGR2_IC10SEC_Msk                (0x1UL << RCC_SECCFGR2_IC10SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR2_IC10SEC                    RCC_SECCFGR2_IC10SEC_Msk             /*!< Secure protection of IC10 divider configuration bits */
+#define RCC_SECCFGR2_IC11SEC_Pos                (10U)
+#define RCC_SECCFGR2_IC11SEC_Msk                (0x1UL << RCC_SECCFGR2_IC11SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR2_IC11SEC                    RCC_SECCFGR2_IC11SEC_Msk             /*!< Secure protection of IC11 divider configuration bits */
+#define RCC_SECCFGR2_IC12SEC_Pos                (11U)
+#define RCC_SECCFGR2_IC12SEC_Msk                (0x1UL << RCC_SECCFGR2_IC12SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR2_IC12SEC                    RCC_SECCFGR2_IC12SEC_Msk             /*!< Secure protection of IC12 divider configuration bits */
+#define RCC_SECCFGR2_IC13SEC_Pos                (12U)
+#define RCC_SECCFGR2_IC13SEC_Msk                (0x1UL << RCC_SECCFGR2_IC13SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR2_IC13SEC                    RCC_SECCFGR2_IC13SEC_Msk             /*!< Secure protection of IC13 divider configuration bits */
+#define RCC_SECCFGR2_IC14SEC_Pos                (13U)
+#define RCC_SECCFGR2_IC14SEC_Msk                (0x1UL << RCC_SECCFGR2_IC14SEC_Pos)   /*!< 0x00002000 */
+#define RCC_SECCFGR2_IC14SEC                    RCC_SECCFGR2_IC14SEC_Msk             /*!< Secure protection of IC14 divider configuration bits */
+#define RCC_SECCFGR2_IC15SEC_Pos                (14U)
+#define RCC_SECCFGR2_IC15SEC_Msk                (0x1UL << RCC_SECCFGR2_IC15SEC_Pos)   /*!< 0x00004000 */
+#define RCC_SECCFGR2_IC15SEC                    RCC_SECCFGR2_IC15SEC_Msk             /*!< Secure protection of IC15 divider configuration bits */
+#define RCC_SECCFGR2_IC16SEC_Pos                (15U)
+#define RCC_SECCFGR2_IC16SEC_Msk                (0x1UL << RCC_SECCFGR2_IC16SEC_Pos)   /*!< 0x00008000 */
+#define RCC_SECCFGR2_IC16SEC                    RCC_SECCFGR2_IC16SEC_Msk             /*!< Secure protection of IC16 divider configuration bits */
+#define RCC_SECCFGR2_IC17SEC_Pos                (16U)
+#define RCC_SECCFGR2_IC17SEC_Msk                (0x1UL << RCC_SECCFGR2_IC17SEC_Pos)   /*!< 0x00010000 */
+#define RCC_SECCFGR2_IC17SEC                    RCC_SECCFGR2_IC17SEC_Msk             /*!< Secure protection of IC17 divider configuration bits */
+#define RCC_SECCFGR2_IC18SEC_Pos                (17U)
+#define RCC_SECCFGR2_IC18SEC_Msk                (0x1UL << RCC_SECCFGR2_IC18SEC_Pos)   /*!< 0x00020000 */
+#define RCC_SECCFGR2_IC18SEC                    RCC_SECCFGR2_IC18SEC_Msk             /*!< Secure protection of IC18 divider configuration bits */
+#define RCC_SECCFGR2_IC19SEC_Pos                (18U)
+#define RCC_SECCFGR2_IC19SEC_Msk                (0x1UL << RCC_SECCFGR2_IC19SEC_Pos)   /*!< 0x00040000 */
+#define RCC_SECCFGR2_IC19SEC                    RCC_SECCFGR2_IC19SEC_Msk             /*!< Secure protection of IC19 divider configuration bits */
+#define RCC_SECCFGR2_IC20SEC_Pos                (19U)
+#define RCC_SECCFGR2_IC20SEC_Msk                (0x1UL << RCC_SECCFGR2_IC20SEC_Pos)   /*!< 0x00080000 */
+#define RCC_SECCFGR2_IC20SEC                    RCC_SECCFGR2_IC20SEC_Msk             /*!< Secure protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR2 register  *****************/
+#define RCC_PRIVCFGR2_IC1PRIV_Pos               (0U)
+#define RCC_PRIVCFGR2_IC1PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR2_IC1PRIV                   RCC_PRIVCFGR2_IC1PRIV_Msk            /*!< Privileged protection of IC1 divider configuration bits */
+#define RCC_PRIVCFGR2_IC2PRIV_Pos               (1U)
+#define RCC_PRIVCFGR2_IC2PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR2_IC2PRIV                   RCC_PRIVCFGR2_IC2PRIV_Msk            /*!< Privileged protection of IC2 divider configuration bits */
+#define RCC_PRIVCFGR2_IC3PRIV_Pos               (2U)
+#define RCC_PRIVCFGR2_IC3PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR2_IC3PRIV                   RCC_PRIVCFGR2_IC3PRIV_Msk            /*!< Privileged protection of IC3 divider configuration bits */
+#define RCC_PRIVCFGR2_IC4PRIV_Pos               (3U)
+#define RCC_PRIVCFGR2_IC4PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR2_IC4PRIV                   RCC_PRIVCFGR2_IC4PRIV_Msk            /*!< Privileged protection of IC4 divider configuration bits */
+#define RCC_PRIVCFGR2_IC5PRIV_Pos               (4U)
+#define RCC_PRIVCFGR2_IC5PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR2_IC5PRIV                   RCC_PRIVCFGR2_IC5PRIV_Msk            /*!< Privileged protection of IC5 divider configuration bits */
+#define RCC_PRIVCFGR2_IC6PRIV_Pos               (5U)
+#define RCC_PRIVCFGR2_IC6PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR2_IC6PRIV                   RCC_PRIVCFGR2_IC6PRIV_Msk            /*!< Privileged protection of IC6 divider configuration bits */
+#define RCC_PRIVCFGR2_IC7PRIV_Pos               (6U)
+#define RCC_PRIVCFGR2_IC7PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos)  /*!< 0x00000040 */
+#define RCC_PRIVCFGR2_IC7PRIV                   RCC_PRIVCFGR2_IC7PRIV_Msk            /*!< Privileged protection of IC7 divider configuration bits */
+#define RCC_PRIVCFGR2_IC8PRIV_Pos               (7U)
+#define RCC_PRIVCFGR2_IC8PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos)  /*!< 0x00000080 */
+#define RCC_PRIVCFGR2_IC8PRIV                   RCC_PRIVCFGR2_IC8PRIV_Msk            /*!< Privileged protection of IC8 divider configuration bits */
+#define RCC_PRIVCFGR2_IC9PRIV_Pos               (8U)
+#define RCC_PRIVCFGR2_IC9PRIV_Msk               (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos)  /*!< 0x00000100 */
+#define RCC_PRIVCFGR2_IC9PRIV                   RCC_PRIVCFGR2_IC9PRIV_Msk            /*!< Privileged protection of IC9 divider configuration bits */
+#define RCC_PRIVCFGR2_IC10PRIV_Pos              (9U)
+#define RCC_PRIVCFGR2_IC10PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR2_IC10PRIV                  RCC_PRIVCFGR2_IC10PRIV_Msk           /*!< Privileged protection of IC10 divider configuration bits */
+#define RCC_PRIVCFGR2_IC11PRIV_Pos              (10U)
+#define RCC_PRIVCFGR2_IC11PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR2_IC11PRIV                  RCC_PRIVCFGR2_IC11PRIV_Msk           /*!< Privileged protection of IC11 divider configuration bits */
+#define RCC_PRIVCFGR2_IC12PRIV_Pos              (11U)
+#define RCC_PRIVCFGR2_IC12PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR2_IC12PRIV                  RCC_PRIVCFGR2_IC12PRIV_Msk           /*!< Privileged protection of IC12 divider configuration bits */
+#define RCC_PRIVCFGR2_IC13PRIV_Pos              (12U)
+#define RCC_PRIVCFGR2_IC13PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR2_IC13PRIV                  RCC_PRIVCFGR2_IC13PRIV_Msk           /*!< Privileged protection of IC13 divider configuration bits */
+#define RCC_PRIVCFGR2_IC14PRIV_Pos              (13U)
+#define RCC_PRIVCFGR2_IC14PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGR2_IC14PRIV                  RCC_PRIVCFGR2_IC14PRIV_Msk           /*!< Privileged protection of IC14 divider configuration bits */
+#define RCC_PRIVCFGR2_IC15PRIV_Pos              (14U)
+#define RCC_PRIVCFGR2_IC15PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGR2_IC15PRIV                  RCC_PRIVCFGR2_IC15PRIV_Msk           /*!< Privileged protection of IC15 divider configuration bits */
+#define RCC_PRIVCFGR2_IC16PRIV_Pos              (15U)
+#define RCC_PRIVCFGR2_IC16PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGR2_IC16PRIV                  RCC_PRIVCFGR2_IC16PRIV_Msk           /*!< Privileged protection of IC16 divider configuration bits */
+#define RCC_PRIVCFGR2_IC17PRIV_Pos              (16U)
+#define RCC_PRIVCFGR2_IC17PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGR2_IC17PRIV                  RCC_PRIVCFGR2_IC17PRIV_Msk           /*!< Privileges protection of IC17 divider configuration bits */
+#define RCC_PRIVCFGR2_IC18PRIV_Pos              (17U)
+#define RCC_PRIVCFGR2_IC18PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGR2_IC18PRIV                  RCC_PRIVCFGR2_IC18PRIV_Msk           /*!< Privilege protection of IC18 divider configuration bits */
+#define RCC_PRIVCFGR2_IC19PRIV_Pos              (18U)
+#define RCC_PRIVCFGR2_IC19PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGR2_IC19PRIV                  RCC_PRIVCFGR2_IC19PRIV_Msk           /*!< Privileged protection of IC19 divider configuration bits */
+#define RCC_PRIVCFGR2_IC20PRIV_Pos              (19U)
+#define RCC_PRIVCFGR2_IC20PRIV_Msk              (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGR2_IC20PRIV                  RCC_PRIVCFGR2_IC20PRIV_Msk           /*!< Privileged protection of IC20 divider configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR2 register  *****************/
+#define RCC_LOCKCFGR2_IC1LOCK_Pos               (0U)
+#define RCC_LOCKCFGR2_IC1LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR2_IC1LOCK                   RCC_LOCKCFGR2_IC1LOCK_Msk            /*!< Locked protection of IC1 divider configuration bits */
+#define RCC_LOCKCFGR2_IC2LOCK_Pos               (1U)
+#define RCC_LOCKCFGR2_IC2LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR2_IC2LOCK                   RCC_LOCKCFGR2_IC2LOCK_Msk            /*!< Locked protection of IC2 divider configuration bits */
+#define RCC_LOCKCFGR2_IC3LOCK_Pos               (2U)
+#define RCC_LOCKCFGR2_IC3LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR2_IC3LOCK                   RCC_LOCKCFGR2_IC3LOCK_Msk            /*!< Locked protection of IC3 divider configuration bits */
+#define RCC_LOCKCFGR2_IC4LOCK_Pos               (3U)
+#define RCC_LOCKCFGR2_IC4LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR2_IC4LOCK                   RCC_LOCKCFGR2_IC4LOCK_Msk            /*!< Locked protection of IC4 divider configuration bits */
+#define RCC_LOCKCFGR2_IC5LOCK_Pos               (4U)
+#define RCC_LOCKCFGR2_IC5LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR2_IC5LOCK                   RCC_LOCKCFGR2_IC5LOCK_Msk            /*!< Locked protection of IC5 divider configuration bits */
+#define RCC_LOCKCFGR2_IC6LOCK_Pos               (5U)
+#define RCC_LOCKCFGR2_IC6LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR2_IC6LOCK                   RCC_LOCKCFGR2_IC6LOCK_Msk            /*!< Locked protection of IC6 divider configuration bits */
+#define RCC_LOCKCFGR2_IC7LOCK_Pos               (6U)
+#define RCC_LOCKCFGR2_IC7LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos)  /*!< 0x00000040 */
+#define RCC_LOCKCFGR2_IC7LOCK                   RCC_LOCKCFGR2_IC7LOCK_Msk            /*!< Locked protection of IC7 divider configuration bits */
+#define RCC_LOCKCFGR2_IC8LOCK_Pos               (7U)
+#define RCC_LOCKCFGR2_IC8LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos)  /*!< 0x00000080 */
+#define RCC_LOCKCFGR2_IC8LOCK                   RCC_LOCKCFGR2_IC8LOCK_Msk            /*!< Locked protection of IC8 divider configuration bits */
+#define RCC_LOCKCFGR2_IC9LOCK_Pos               (8U)
+#define RCC_LOCKCFGR2_IC9LOCK_Msk               (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos)  /*!< 0x00000100 */
+#define RCC_LOCKCFGR2_IC9LOCK                   RCC_LOCKCFGR2_IC9LOCK_Msk            /*!< Locked protection of IC9 divider configuration bits */
+#define RCC_LOCKCFGR2_IC10LOCK_Pos              (9U)
+#define RCC_LOCKCFGR2_IC10LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR2_IC10LOCK                  RCC_LOCKCFGR2_IC10LOCK_Msk           /*!< Locked protection of IC10 divider configuration bits */
+#define RCC_LOCKCFGR2_IC11LOCK_Pos              (10U)
+#define RCC_LOCKCFGR2_IC11LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR2_IC11LOCK                  RCC_LOCKCFGR2_IC11LOCK_Msk           /*!< Locked protection of IC11 divider configuration bits */
+#define RCC_LOCKCFGR2_IC12LOCK_Pos              (11U)
+#define RCC_LOCKCFGR2_IC12LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR2_IC12LOCK                  RCC_LOCKCFGR2_IC12LOCK_Msk           /*!< Locked protection of IC12 divider configuration bits */
+#define RCC_LOCKCFGR2_IC13LOCK_Pos              (12U)
+#define RCC_LOCKCFGR2_IC13LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR2_IC13LOCK                  RCC_LOCKCFGR2_IC13LOCK_Msk           /*!< Locked protection of IC13 divider configuration bits */
+#define RCC_LOCKCFGR2_IC14LOCK_Pos              (13U)
+#define RCC_LOCKCFGR2_IC14LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */
+#define RCC_LOCKCFGR2_IC14LOCK                  RCC_LOCKCFGR2_IC14LOCK_Msk           /*!< Locked protection of IC14 divider configuration bits */
+#define RCC_LOCKCFGR2_IC15LOCK_Pos              (14U)
+#define RCC_LOCKCFGR2_IC15LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */
+#define RCC_LOCKCFGR2_IC15LOCK                  RCC_LOCKCFGR2_IC15LOCK_Msk           /*!< Locked protection of IC15 divider configuration bits */
+#define RCC_LOCKCFGR2_IC16LOCK_Pos              (15U)
+#define RCC_LOCKCFGR2_IC16LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */
+#define RCC_LOCKCFGR2_IC16LOCK                  RCC_LOCKCFGR2_IC16LOCK_Msk           /*!< Locked protection of IC16 divider configuration bits */
+#define RCC_LOCKCFGR2_IC17LOCK_Pos              (16U)
+#define RCC_LOCKCFGR2_IC17LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */
+#define RCC_LOCKCFGR2_IC17LOCK                  RCC_LOCKCFGR2_IC17LOCK_Msk           /*!< Locked protection of IC17 divider configuration bits */
+#define RCC_LOCKCFGR2_IC18LOCK_Pos              (17U)
+#define RCC_LOCKCFGR2_IC18LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */
+#define RCC_LOCKCFGR2_IC18LOCK                  RCC_LOCKCFGR2_IC18LOCK_Msk           /*!< Locked protection of IC18 divider configuration bits */
+#define RCC_LOCKCFGR2_IC19LOCK_Pos              (18U)
+#define RCC_LOCKCFGR2_IC19LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */
+#define RCC_LOCKCFGR2_IC19LOCK                  RCC_LOCKCFGR2_IC19LOCK_Msk           /*!< Locked protection of IC19 divider configuration bits */
+#define RCC_LOCKCFGR2_IC20LOCK_Pos              (19U)
+#define RCC_LOCKCFGR2_IC20LOCK_Msk              (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */
+#define RCC_LOCKCFGR2_IC20LOCK                  RCC_LOCKCFGR2_IC20LOCK_Msk           /*!< Locked protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR2 register  *****************/
+#define RCC_PUBCFGR2_IC1PUB_Pos                 (0U)
+#define RCC_PUBCFGR2_IC1PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR2_IC1PUB                     RCC_PUBCFGR2_IC1PUB_Msk              /*!< Public protection of IC1 divider configuration bits */
+#define RCC_PUBCFGR2_IC2PUB_Pos                 (1U)
+#define RCC_PUBCFGR2_IC2PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR2_IC2PUB                     RCC_PUBCFGR2_IC2PUB_Msk              /*!< Public protection of IC2 divider configuration bits */
+#define RCC_PUBCFGR2_IC3PUB_Pos                 (2U)
+#define RCC_PUBCFGR2_IC3PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR2_IC3PUB                     RCC_PUBCFGR2_IC3PUB_Msk              /*!< Public protection of IC3 divider configuration bits */
+#define RCC_PUBCFGR2_IC4PUB_Pos                 (3U)
+#define RCC_PUBCFGR2_IC4PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR2_IC4PUB                     RCC_PUBCFGR2_IC4PUB_Msk              /*!< Public protection of IC4 divider configuration bits */
+#define RCC_PUBCFGR2_IC5PUB_Pos                 (4U)
+#define RCC_PUBCFGR2_IC5PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR2_IC5PUB                     RCC_PUBCFGR2_IC5PUB_Msk              /*!< Public protection of IC5 divider configuration bits */
+#define RCC_PUBCFGR2_IC6PUB_Pos                 (5U)
+#define RCC_PUBCFGR2_IC6PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR2_IC6PUB                     RCC_PUBCFGR2_IC6PUB_Msk              /*!< Public protection of IC6 divider configuration bits */
+#define RCC_PUBCFGR2_IC7PUB_Pos                 (6U)
+#define RCC_PUBCFGR2_IC7PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos)    /*!< 0x00000040 */
+#define RCC_PUBCFGR2_IC7PUB                     RCC_PUBCFGR2_IC7PUB_Msk              /*!< Public protection of IC7 divider configuration bits */
+#define RCC_PUBCFGR2_IC8PUB_Pos                 (7U)
+#define RCC_PUBCFGR2_IC8PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos)    /*!< 0x00000080 */
+#define RCC_PUBCFGR2_IC8PUB                     RCC_PUBCFGR2_IC8PUB_Msk              /*!< Public protection of IC8 divider configuration bits */
+#define RCC_PUBCFGR2_IC9PUB_Pos                 (8U)
+#define RCC_PUBCFGR2_IC9PUB_Msk                 (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos)    /*!< 0x00000100 */
+#define RCC_PUBCFGR2_IC9PUB                     RCC_PUBCFGR2_IC9PUB_Msk              /*!< Public protection of IC9 divider configuration bits */
+#define RCC_PUBCFGR2_IC10PUB_Pos                (9U)
+#define RCC_PUBCFGR2_IC10PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR2_IC10PUB                    RCC_PUBCFGR2_IC10PUB_Msk             /*!< Public protection of IC10 divider configuration bits */
+#define RCC_PUBCFGR2_IC11PUB_Pos                (10U)
+#define RCC_PUBCFGR2_IC11PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR2_IC11PUB                    RCC_PUBCFGR2_IC11PUB_Msk             /*!< Public protection of IC11 divider configuration bits */
+#define RCC_PUBCFGR2_IC12PUB_Pos                (11U)
+#define RCC_PUBCFGR2_IC12PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR2_IC12PUB                    RCC_PUBCFGR2_IC12PUB_Msk             /*!< Public protection of IC12 divider configuration bits */
+#define RCC_PUBCFGR2_IC13PUB_Pos                (12U)
+#define RCC_PUBCFGR2_IC13PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR2_IC13PUB                    RCC_PUBCFGR2_IC13PUB_Msk             /*!< Public protection of IC13 divider configuration bits */
+#define RCC_PUBCFGR2_IC14PUB_Pos                (13U)
+#define RCC_PUBCFGR2_IC14PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos)   /*!< 0x00002000 */
+#define RCC_PUBCFGR2_IC14PUB                    RCC_PUBCFGR2_IC14PUB_Msk             /*!< Public protection of IC14 divider configuration bits */
+#define RCC_PUBCFGR2_IC15PUB_Pos                (14U)
+#define RCC_PUBCFGR2_IC15PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos)   /*!< 0x00004000 */
+#define RCC_PUBCFGR2_IC15PUB                    RCC_PUBCFGR2_IC15PUB_Msk             /*!< Public protection of IC15 divider configuration bits */
+#define RCC_PUBCFGR2_IC16PUB_Pos                (15U)
+#define RCC_PUBCFGR2_IC16PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos)   /*!< 0x00008000 */
+#define RCC_PUBCFGR2_IC16PUB                    RCC_PUBCFGR2_IC16PUB_Msk             /*!< Public protection of IC16 divider configuration bits */
+#define RCC_PUBCFGR2_IC17PUB_Pos                (16U)
+#define RCC_PUBCFGR2_IC17PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos)   /*!< 0x00010000 */
+#define RCC_PUBCFGR2_IC17PUB                    RCC_PUBCFGR2_IC17PUB_Msk             /*!< Public protection of IC17 divider configuration bits */
+#define RCC_PUBCFGR2_IC18PUB_Pos                (17U)
+#define RCC_PUBCFGR2_IC18PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos)   /*!< 0x00020000 */
+#define RCC_PUBCFGR2_IC18PUB                    RCC_PUBCFGR2_IC18PUB_Msk             /*!< Public protection of IC18 divider configuration bits */
+#define RCC_PUBCFGR2_IC19PUB_Pos                (18U)
+#define RCC_PUBCFGR2_IC19PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos)   /*!< 0x00040000 */
+#define RCC_PUBCFGR2_IC19PUB                    RCC_PUBCFGR2_IC19PUB_Msk             /*!< Public protection of IC19 divider configuration bits */
+#define RCC_PUBCFGR2_IC20PUB_Pos                (19U)
+#define RCC_PUBCFGR2_IC20PUB_Msk                (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos)   /*!< 0x00080000 */
+#define RCC_PUBCFGR2_IC20PUB                    RCC_PUBCFGR2_IC20PUB_Msk             /*!< Public protection of IC20 divider configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR3 register  *****************/
+#define RCC_SECCFGR3_MODSEC_Pos                 (0U)
+#define RCC_SECCFGR3_MODSEC_Msk                 (0x1UL << RCC_SECCFGR3_MODSEC_Pos)    /*!< 0x00000001 */
+#define RCC_SECCFGR3_MODSEC                     RCC_SECCFGR3_MODSEC_Msk              /*!< Secure protection of MOD system configuration bits */
+#define RCC_SECCFGR3_SYSSEC_Pos                 (1U)
+#define RCC_SECCFGR3_SYSSEC_Msk                 (0x1UL << RCC_SECCFGR3_SYSSEC_Pos)    /*!< 0x00000002 */
+#define RCC_SECCFGR3_SYSSEC                     RCC_SECCFGR3_SYSSEC_Msk              /*!< Secure protection of SYS system configuration bit */
+#define RCC_SECCFGR3_BUSSEC_Pos                 (2U)
+#define RCC_SECCFGR3_BUSSEC_Msk                 (0x1UL << RCC_SECCFGR3_BUSSEC_Pos)    /*!< 0x00000004 */
+#define RCC_SECCFGR3_BUSSEC                     RCC_SECCFGR3_BUSSEC_Msk              /*!< Secure protection of BUS system configuration bits */
+#define RCC_SECCFGR3_PERSEC_Pos                 (3U)
+#define RCC_SECCFGR3_PERSEC_Msk                 (0x1UL << RCC_SECCFGR3_PERSEC_Pos)    /*!< 0x00000008 */
+#define RCC_SECCFGR3_PERSEC                     RCC_SECCFGR3_PERSEC_Msk              /*!< Secure protection of PER system configuration bits */
+#define RCC_SECCFGR3_INTSEC_Pos                 (4U)
+#define RCC_SECCFGR3_INTSEC_Msk                 (0x1UL << RCC_SECCFGR3_INTSEC_Pos)    /*!< 0x00000010 */
+#define RCC_SECCFGR3_INTSEC                     RCC_SECCFGR3_INTSEC_Msk              /*!< Secure protection of INT system configuration bits */
+#define RCC_SECCFGR3_RSTSEC_Pos                 (5U)
+#define RCC_SECCFGR3_RSTSEC_Msk                 (0x1UL << RCC_SECCFGR3_RSTSEC_Pos)    /*!< 0x00000020 */
+#define RCC_SECCFGR3_RSTSEC                     RCC_SECCFGR3_RSTSEC_Msk              /*!< Secure protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR3 register  *****************/
+#define RCC_PRIVCFGR3_MODPRIV_Pos               (0U)
+#define RCC_PRIVCFGR3_MODPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGR3_MODPRIV                   RCC_PRIVCFGR3_MODPRIV_Msk            /*!< Privileged protection of MOD system configuration bits */
+#define RCC_PRIVCFGR3_SYSPRIV_Pos               (1U)
+#define RCC_PRIVCFGR3_SYSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos)  /*!< 0x00000002 */
+#define RCC_PRIVCFGR3_SYSPRIV                   RCC_PRIVCFGR3_SYSPRIV_Msk            /*!< Privileged protection of SYS system configuration bits */
+#define RCC_PRIVCFGR3_BUSPRIV_Pos               (2U)
+#define RCC_PRIVCFGR3_BUSPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos)  /*!< 0x00000004 */
+#define RCC_PRIVCFGR3_BUSPRIV                   RCC_PRIVCFGR3_BUSPRIV_Msk            /*!< Privileged protection of BUS system configuration bits */
+#define RCC_PRIVCFGR3_PERPRIV_Pos               (3U)
+#define RCC_PRIVCFGR3_PERPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos)  /*!< 0x00000008 */
+#define RCC_PRIVCFGR3_PERPRIV                   RCC_PRIVCFGR3_PERPRIV_Msk            /*!< Privileged protection of PER system configuration bits */
+#define RCC_PRIVCFGR3_INTPRIV_Pos               (4U)
+#define RCC_PRIVCFGR3_INTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos)  /*!< 0x00000010 */
+#define RCC_PRIVCFGR3_INTPRIV                   RCC_PRIVCFGR3_INTPRIV_Msk            /*!< Privileged protection of INT system configuration bits */
+#define RCC_PRIVCFGR3_RSTPRIV_Pos               (5U)
+#define RCC_PRIVCFGR3_RSTPRIV_Msk               (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos)  /*!< 0x00000020 */
+#define RCC_PRIVCFGR3_RSTPRIV                   RCC_PRIVCFGR3_RSTPRIV_Msk            /*!< Privileged protection of RST system configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR3 register  *****************/
+#define RCC_LOCKCFGR3_MODLOCK_Pos               (0U)
+#define RCC_LOCKCFGR3_MODLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos)  /*!< 0x00000001 */
+#define RCC_LOCKCFGR3_MODLOCK                   RCC_LOCKCFGR3_MODLOCK_Msk            /*!< Locked protection of MOD system configuration bits */
+#define RCC_LOCKCFGR3_SYSLOCK_Pos               (1U)
+#define RCC_LOCKCFGR3_SYSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos)  /*!< 0x00000002 */
+#define RCC_LOCKCFGR3_SYSLOCK                   RCC_LOCKCFGR3_SYSLOCK_Msk            /*!< Locked protection of SYS system configuration bits */
+#define RCC_LOCKCFGR3_BUSLOCK_Pos               (2U)
+#define RCC_LOCKCFGR3_BUSLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos)  /*!< 0x00000004 */
+#define RCC_LOCKCFGR3_BUSLOCK                   RCC_LOCKCFGR3_BUSLOCK_Msk            /*!< Locked protection of BUS system configuration bits */
+#define RCC_LOCKCFGR3_PERLOCK_Pos               (3U)
+#define RCC_LOCKCFGR3_PERLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos)  /*!< 0x00000008 */
+#define RCC_LOCKCFGR3_PERLOCK                   RCC_LOCKCFGR3_PERLOCK_Msk            /*!< Locked protection of PER system configuration bits */
+#define RCC_LOCKCFGR3_INTLOCK_Pos               (4U)
+#define RCC_LOCKCFGR3_INTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos)  /*!< 0x00000010 */
+#define RCC_LOCKCFGR3_INTLOCK                   RCC_LOCKCFGR3_INTLOCK_Msk            /*!< Locked protection of INT system configuration bits */
+#define RCC_LOCKCFGR3_RSTLOCK_Pos               (5U)
+#define RCC_LOCKCFGR3_RSTLOCK_Msk               (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos)  /*!< 0x00000020 */
+#define RCC_LOCKCFGR3_RSTLOCK                   RCC_LOCKCFGR3_RSTLOCK_Msk            /*!< Locked protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR3 register  *****************/
+#define RCC_PUBCFGR3_MODPUB_Pos                 (0U)
+#define RCC_PUBCFGR3_MODPUB_Msk                 (0x1UL << RCC_PUBCFGR3_MODPUB_Pos)    /*!< 0x00000001 */
+#define RCC_PUBCFGR3_MODPUB                     RCC_PUBCFGR3_MODPUB_Msk              /*!< Public protection of MOD system configuration bits */
+#define RCC_PUBCFGR3_SYSPUB_Pos                 (1U)
+#define RCC_PUBCFGR3_SYSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos)    /*!< 0x00000002 */
+#define RCC_PUBCFGR3_SYSPUB                     RCC_PUBCFGR3_SYSPUB_Msk              /*!< Public protection of SYS system configuration bits */
+#define RCC_PUBCFGR3_BUSPUB_Pos                 (2U)
+#define RCC_PUBCFGR3_BUSPUB_Msk                 (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos)    /*!< 0x00000004 */
+#define RCC_PUBCFGR3_BUSPUB                     RCC_PUBCFGR3_BUSPUB_Msk              /*!< Public protection of BUS system configuration bits */
+#define RCC_PUBCFGR3_PERPUB_Pos                 (3U)
+#define RCC_PUBCFGR3_PERPUB_Msk                 (0x1UL << RCC_PUBCFGR3_PERPUB_Pos)    /*!< 0x00000008 */
+#define RCC_PUBCFGR3_PERPUB                     RCC_PUBCFGR3_PERPUB_Msk              /*!< Public protection of PER system configuration bits */
+#define RCC_PUBCFGR3_INTPUB_Pos                 (4U)
+#define RCC_PUBCFGR3_INTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_INTPUB_Pos)    /*!< 0x00000010 */
+#define RCC_PUBCFGR3_INTPUB                     RCC_PUBCFGR3_INTPUB_Msk              /*!< Public protection of INT system configuration bits */
+#define RCC_PUBCFGR3_RSTPUB_Pos                 (5U)
+#define RCC_PUBCFGR3_RSTPUB_Msk                 (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos)    /*!< 0x00000020 */
+#define RCC_PUBCFGR3_RSTPUB                     RCC_PUBCFGR3_RSTPUB_Msk              /*!< Public protection of RST system configuration bits */
+
+/*****************  Bit definition for RCC_SECCFGR4 register  *****************/
+#define RCC_SECCFGR4_ACLKNSEC_Pos               (0U)
+#define RCC_SECCFGR4_ACLKNSEC_Msk               (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos)  /*!< 0x00000001 */
+#define RCC_SECCFGR4_ACLKNSEC                   RCC_SECCFGR4_ACLKNSEC_Msk            /*!< Secure protection of ACLKN bus configuration bits */
+#define RCC_SECCFGR4_ACLKNCSEC_Pos              (1U)
+#define RCC_SECCFGR4_ACLKNCSEC_Msk              (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */
+#define RCC_SECCFGR4_ACLKNCSEC                  RCC_SECCFGR4_ACLKNCSEC_Msk           /*!< Secure protection of ACLKNC bus configuration bits */
+#define RCC_SECCFGR4_AHBMSEC_Pos                (2U)
+#define RCC_SECCFGR4_AHBMSEC_Msk                (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos)   /*!< 0x00000004 */
+#define RCC_SECCFGR4_AHBMSEC                    RCC_SECCFGR4_AHBMSEC_Msk             /*!< Secure protection of AHBM bus configuration bits */
+#define RCC_SECCFGR4_AHB1SEC_Pos                (3U)
+#define RCC_SECCFGR4_AHB1SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos)   /*!< 0x00000008 */
+#define RCC_SECCFGR4_AHB1SEC                    RCC_SECCFGR4_AHB1SEC_Msk             /*!< Secure protection of AHB1 bus configuration bits */
+#define RCC_SECCFGR4_AHB2SEC_Pos                (4U)
+#define RCC_SECCFGR4_AHB2SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos)   /*!< 0x00000010 */
+#define RCC_SECCFGR4_AHB2SEC                    RCC_SECCFGR4_AHB2SEC_Msk             /*!< Secure protection of AHB2 bus configuration bits */
+#define RCC_SECCFGR4_AHB3SEC_Pos                (5U)
+#define RCC_SECCFGR4_AHB3SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos)   /*!< 0x00000020 */
+#define RCC_SECCFGR4_AHB3SEC                    RCC_SECCFGR4_AHB3SEC_Msk             /*!< Secure protection of AHB3 bus configuration bits */
+#define RCC_SECCFGR4_AHB4SEC_Pos                (6U)
+#define RCC_SECCFGR4_AHB4SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos)   /*!< 0x00000040 */
+#define RCC_SECCFGR4_AHB4SEC                    RCC_SECCFGR4_AHB4SEC_Msk             /*!< Secure protection of AHB4 bus configuration bits */
+#define RCC_SECCFGR4_AHB5SEC_Pos                (7U)
+#define RCC_SECCFGR4_AHB5SEC_Msk                (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos)   /*!< 0x00000080 */
+#define RCC_SECCFGR4_AHB5SEC                    RCC_SECCFGR4_AHB5SEC_Msk             /*!< Secure protection of AHB5 bus configuration bits */
+#define RCC_SECCFGR4_APB1SEC_Pos                (8U)
+#define RCC_SECCFGR4_APB1SEC_Msk                (0x1UL << RCC_SECCFGR4_APB1SEC_Pos)   /*!< 0x00000100 */
+#define RCC_SECCFGR4_APB1SEC                    RCC_SECCFGR4_APB1SEC_Msk             /*!< Secure protection of APB1 bus configuration bits */
+#define RCC_SECCFGR4_APB2SEC_Pos                (9U)
+#define RCC_SECCFGR4_APB2SEC_Msk                (0x1UL << RCC_SECCFGR4_APB2SEC_Pos)   /*!< 0x00000200 */
+#define RCC_SECCFGR4_APB2SEC                    RCC_SECCFGR4_APB2SEC_Msk             /*!< Secure protection of APB2 bus configuration bits */
+#define RCC_SECCFGR4_APB3SEC_Pos                (10U)
+#define RCC_SECCFGR4_APB3SEC_Msk                (0x1UL << RCC_SECCFGR4_APB3SEC_Pos)   /*!< 0x00000400 */
+#define RCC_SECCFGR4_APB3SEC                    RCC_SECCFGR4_APB3SEC_Msk             /*!< Secure protection of APB3 bus configuration bits */
+#define RCC_SECCFGR4_APB4SEC_Pos                (11U)
+#define RCC_SECCFGR4_APB4SEC_Msk                (0x1UL << RCC_SECCFGR4_APB4SEC_Pos)   /*!< 0x00000800 */
+#define RCC_SECCFGR4_APB4SEC                    RCC_SECCFGR4_APB4SEC_Msk             /*!< Secure protection of APB4 bus configuration bits */
+#define RCC_SECCFGR4_APB5SEC_Pos                (12U)
+#define RCC_SECCFGR4_APB5SEC_Msk                (0x1UL << RCC_SECCFGR4_APB5SEC_Pos)   /*!< 0x00001000 */
+#define RCC_SECCFGR4_APB5SEC                    RCC_SECCFGR4_APB5SEC_Msk             /*!< Secure protection of APB5 bus configuration bits */
+#define RCC_SECCFGR4_NOCSEC_Pos                 (13U)
+#define RCC_SECCFGR4_NOCSEC_Msk                 (0x1UL << RCC_SECCFGR4_NOCSEC_Pos)    /*!< 0x00002000 */
+#define RCC_SECCFGR4_NOCSEC                     RCC_SECCFGR4_NOCSEC_Msk              /*!< Secure protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_PRIVCFGR4 register  *****************/
+#define RCC_PRIVCFGR4_ACLKNPRIV_Pos             (0U)
+#define RCC_PRIVCFGR4_ACLKNPRIV_Msk             (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGR4_ACLKNPRIV                 RCC_PRIVCFGR4_ACLKNPRIV_Msk          /*!< Privileged protection of ACLKN bus configuration bits */
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos            (1U)
+#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk            (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGR4_ACLKNCPRIV                RCC_PRIVCFGR4_ACLKNCPRIV_Msk         /*!< Privileged protection of ACLKNC bus configuration bits */
+#define RCC_PRIVCFGR4_AHBMPRIV_Pos              (2U)
+#define RCC_PRIVCFGR4_AHBMPRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGR4_AHBMPRIV                  RCC_PRIVCFGR4_AHBMPRIV_Msk           /*!< Privileged protection of AHBM bus configuration bits */
+#define RCC_PRIVCFGR4_AHB1PRIV_Pos              (3U)
+#define RCC_PRIVCFGR4_AHB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGR4_AHB1PRIV                  RCC_PRIVCFGR4_AHB1PRIV_Msk           /*!< Privileged protection of AHB1 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB2PRIV_Pos              (4U)
+#define RCC_PRIVCFGR4_AHB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGR4_AHB2PRIV                  RCC_PRIVCFGR4_AHB2PRIV_Msk           /*!< Privileged protection of AHB2 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB3PRIV_Pos              (5U)
+#define RCC_PRIVCFGR4_AHB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGR4_AHB3PRIV                  RCC_PRIVCFGR4_AHB3PRIV_Msk           /*!< Privileged protection of AHB3 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB4PRIV_Pos              (6U)
+#define RCC_PRIVCFGR4_AHB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGR4_AHB4PRIV                  RCC_PRIVCFGR4_AHB4PRIV_Msk           /*!< Privileged protection of AHB4 bus configuration bits */
+#define RCC_PRIVCFGR4_AHB5PRIV_Pos              (7U)
+#define RCC_PRIVCFGR4_AHB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGR4_AHB5PRIV                  RCC_PRIVCFGR4_AHB5PRIV_Msk           /*!< Privileged protection of AHB5 bus configuration bits */
+#define RCC_PRIVCFGR4_APB1PRIV_Pos              (8U)
+#define RCC_PRIVCFGR4_APB1PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGR4_APB1PRIV                  RCC_PRIVCFGR4_APB1PRIV_Msk           /*!< Privileged protection of APB1 bus configuration bits */
+#define RCC_PRIVCFGR4_APB2PRIV_Pos              (9U)
+#define RCC_PRIVCFGR4_APB2PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGR4_APB2PRIV                  RCC_PRIVCFGR4_APB2PRIV_Msk           /*!< Privileged protection of APB2 bus configuration bits */
+#define RCC_PRIVCFGR4_APB3PRIV_Pos              (10U)
+#define RCC_PRIVCFGR4_APB3PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGR4_APB3PRIV                  RCC_PRIVCFGR4_APB3PRIV_Msk           /*!< Privileged protection of APB3 bus configuration bits */
+#define RCC_PRIVCFGR4_APB4PRIV_Pos              (11U)
+#define RCC_PRIVCFGR4_APB4PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGR4_APB4PRIV                  RCC_PRIVCFGR4_APB4PRIV_Msk           /*!< Privileged protection of APB4 bus configuration bits */
+#define RCC_PRIVCFGR4_APB5PRIV_Pos              (12U)
+#define RCC_PRIVCFGR4_APB5PRIV_Msk              (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGR4_APB5PRIV                  RCC_PRIVCFGR4_APB5PRIV_Msk           /*!< Privileged protection of APB5 bus configuration bits */
+#define RCC_PRIVCFGR4_NOCPRIV_Pos               (13U)
+#define RCC_PRIVCFGR4_NOCPRIV_Msk               (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos)  /*!< 0x00002000 */
+#define RCC_PRIVCFGR4_NOCPRIV                   RCC_PRIVCFGR4_NOCPRIV_Msk            /*!< Privileged protection of NOC bus configuration bits */
+
+/****************  Bit definition for RCC_LOCKCFGR4 register  *****************/
+#define RCC_LOCKCFGR4_ACLKNLOCK_Pos             (0U)
+#define RCC_LOCKCFGR4_ACLKNLOCK_Msk             (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */
+#define RCC_LOCKCFGR4_ACLKNLOCK                 RCC_LOCKCFGR4_ACLKNLOCK_Msk          /*!< Locked protection of ACLKN bus configuration bits */
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos            (1U)
+#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk            (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */
+#define RCC_LOCKCFGR4_ACLKNCLOCK                RCC_LOCKCFGR4_ACLKNCLOCK_Msk         /*!< Locked protection of ACLKNC bus configuration bits */
+#define RCC_LOCKCFGR4_AHBMLOCK_Pos              (2U)
+#define RCC_LOCKCFGR4_AHBMLOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */
+#define RCC_LOCKCFGR4_AHBMLOCK                  RCC_LOCKCFGR4_AHBMLOCK_Msk           /*!< Locked protection of AHBM bus configuration bits */
+#define RCC_LOCKCFGR4_AHB1LOCK_Pos              (3U)
+#define RCC_LOCKCFGR4_AHB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */
+#define RCC_LOCKCFGR4_AHB1LOCK                  RCC_LOCKCFGR4_AHB1LOCK_Msk           /*!< Locked protection of AHB1 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB2LOCK_Pos              (4U)
+#define RCC_LOCKCFGR4_AHB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */
+#define RCC_LOCKCFGR4_AHB2LOCK                  RCC_LOCKCFGR4_AHB2LOCK_Msk           /*!< Locked protection of AHB2 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB3LOCK_Pos              (5U)
+#define RCC_LOCKCFGR4_AHB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */
+#define RCC_LOCKCFGR4_AHB3LOCK                  RCC_LOCKCFGR4_AHB3LOCK_Msk           /*!< Locked protection of AHB3 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB4LOCK_Pos              (6U)
+#define RCC_LOCKCFGR4_AHB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */
+#define RCC_LOCKCFGR4_AHB4LOCK                  RCC_LOCKCFGR4_AHB4LOCK_Msk           /*!< Locked protection of AHB4 bus configuration bits */
+#define RCC_LOCKCFGR4_AHB5LOCK_Pos              (7U)
+#define RCC_LOCKCFGR4_AHB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */
+#define RCC_LOCKCFGR4_AHB5LOCK                  RCC_LOCKCFGR4_AHB5LOCK_Msk           /*!< Locked protection of AHB5 bus configuration bits */
+#define RCC_LOCKCFGR4_APB1LOCK_Pos              (8U)
+#define RCC_LOCKCFGR4_APB1LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */
+#define RCC_LOCKCFGR4_APB1LOCK                  RCC_LOCKCFGR4_APB1LOCK_Msk           /*!< Locked protection of APB1 bus configuration bits */
+#define RCC_LOCKCFGR4_APB2LOCK_Pos              (9U)
+#define RCC_LOCKCFGR4_APB2LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */
+#define RCC_LOCKCFGR4_APB2LOCK                  RCC_LOCKCFGR4_APB2LOCK_Msk           /*!< Locked protection of APB2 bus configuration bits */
+#define RCC_LOCKCFGR4_APB3LOCK_Pos              (10U)
+#define RCC_LOCKCFGR4_APB3LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */
+#define RCC_LOCKCFGR4_APB3LOCK                  RCC_LOCKCFGR4_APB3LOCK_Msk           /*!< Locked protection of APB3 bus configuration bits */
+#define RCC_LOCKCFGR4_APB4LOCK_Pos              (11U)
+#define RCC_LOCKCFGR4_APB4LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */
+#define RCC_LOCKCFGR4_APB4LOCK                  RCC_LOCKCFGR4_APB4LOCK_Msk           /*!< Locked protection of APB4 bus configuration bits */
+#define RCC_LOCKCFGR4_APB5LOCK_Pos              (12U)
+#define RCC_LOCKCFGR4_APB5LOCK_Msk              (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */
+#define RCC_LOCKCFGR4_APB5LOCK                  RCC_LOCKCFGR4_APB5LOCK_Msk           /*!< Locked protection of APB5 bus configuration bits */
+#define RCC_LOCKCFGR4_NOCLOCK_Pos               (13U)
+#define RCC_LOCKCFGR4_NOCLOCK_Msk               (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos)  /*!< 0x00002000 */
+#define RCC_LOCKCFGR4_NOCLOCK                   RCC_LOCKCFGR4_NOCLOCK_Msk            /*!< Locked protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR4 register  *****************/
+#define RCC_PUBCFGR4_ACLKNPUB_Pos               (0U)
+#define RCC_PUBCFGR4_ACLKNPUB_Msk               (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGR4_ACLKNPUB                   RCC_PUBCFGR4_ACLKNPUB_Msk            /*!< Public protection of the ACLKN bus configuration bits */
+#define RCC_PUBCFGR4_ACLKNCPUB_Pos              (1U)
+#define RCC_PUBCFGR4_ACLKNCPUB_Msk              (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR4_ACLKNCPUB                  RCC_PUBCFGR4_ACLKNCPUB_Msk           /*!< Public protection of ACLKNC bus configuration bits */
+#define RCC_PUBCFGR4_AHBMPUB_Pos                (2U)
+#define RCC_PUBCFGR4_AHBMPUB_Msk                (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGR4_AHBMPUB                    RCC_PUBCFGR4_AHBMPUB_Msk             /*!< Public protection of AHBM bus configuration bits */
+#define RCC_PUBCFGR4_AHB1PUB_Pos                (3U)
+#define RCC_PUBCFGR4_AHB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGR4_AHB1PUB                    RCC_PUBCFGR4_AHB1PUB_Msk             /*!< Public protection of AHB1 bus configuration bits */
+#define RCC_PUBCFGR4_AHB2PUB_Pos                (4U)
+#define RCC_PUBCFGR4_AHB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGR4_AHB2PUB                    RCC_PUBCFGR4_AHB2PUB_Msk             /*!< Public protection of AHB2 bus configuration bits */
+#define RCC_PUBCFGR4_AHB3PUB_Pos                (5U)
+#define RCC_PUBCFGR4_AHB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGR4_AHB3PUB                    RCC_PUBCFGR4_AHB3PUB_Msk             /*!< Public protection of AHB3 bus configuration bits */
+#define RCC_PUBCFGR4_AHB4PUB_Pos                (6U)
+#define RCC_PUBCFGR4_AHB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos)   /*!< 0x00000040 */
+#define RCC_PUBCFGR4_AHB4PUB                    RCC_PUBCFGR4_AHB4PUB_Msk             /*!< Public protection of AHB4 bus configuration bits */
+#define RCC_PUBCFGR4_AHB5PUB_Pos                (7U)
+#define RCC_PUBCFGR4_AHB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGR4_AHB5PUB                    RCC_PUBCFGR4_AHB5PUB_Msk             /*!< Public protection of AHB5 bus configuration bits */
+#define RCC_PUBCFGR4_APB1PUB_Pos                (8U)
+#define RCC_PUBCFGR4_APB1PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGR4_APB1PUB                    RCC_PUBCFGR4_APB1PUB_Msk             /*!< Public protection of APB1 bus configuration bits */
+#define RCC_PUBCFGR4_APB2PUB_Pos                (9U)
+#define RCC_PUBCFGR4_APB2PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos)   /*!< 0x00000200 */
+#define RCC_PUBCFGR4_APB2PUB                    RCC_PUBCFGR4_APB2PUB_Msk             /*!< Public protection of APB2 bus configuration bits */
+#define RCC_PUBCFGR4_APB3PUB_Pos                (10U)
+#define RCC_PUBCFGR4_APB3PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos)   /*!< 0x00000400 */
+#define RCC_PUBCFGR4_APB3PUB                    RCC_PUBCFGR4_APB3PUB_Msk             /*!< Public protection of APB3 bus configuration bits */
+#define RCC_PUBCFGR4_APB4PUB_Pos                (11U)
+#define RCC_PUBCFGR4_APB4PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos)   /*!< 0x00000800 */
+#define RCC_PUBCFGR4_APB4PUB                    RCC_PUBCFGR4_APB4PUB_Msk             /*!< Public protection of APB4 bus configuration bits */
+#define RCC_PUBCFGR4_APB5PUB_Pos                (12U)
+#define RCC_PUBCFGR4_APB5PUB_Msk                (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos)   /*!< 0x00001000 */
+#define RCC_PUBCFGR4_APB5PUB                    RCC_PUBCFGR4_APB5PUB_Msk             /*!< Public protection of APB5 bus configuration bits */
+#define RCC_PUBCFGR4_NOCPUB_Pos                 (13U)
+#define RCC_PUBCFGR4_NOCPUB_Msk                 (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos)    /*!< 0x00002000 */
+#define RCC_PUBCFGR4_NOCPUB                     RCC_PUBCFGR4_NOCPUB_Msk              /*!< Public protection of NOC bus configuration bits */
+
+/*****************  Bit definition for RCC_PUBCFGR5 register  *****************/
+#define RCC_PUBCFGR5_AXISRAM3PUB_Pos            (0U)
+#define RCC_PUBCFGR5_AXISRAM3PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGR5_AXISRAM3PUB                RCC_PUBCFGR5_AXISRAM3PUB_Msk         /*!< Public protection of AXISRAM3 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM4PUB_Pos            (1U)
+#define RCC_PUBCFGR5_AXISRAM4PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGR5_AXISRAM4PUB                RCC_PUBCFGR5_AXISRAM4PUB_Msk         /*!< Public protection of AXISRAM4 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM5PUB_Pos            (2U)
+#define RCC_PUBCFGR5_AXISRAM5PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGR5_AXISRAM5PUB                RCC_PUBCFGR5_AXISRAM5PUB_Msk         /*!< Public protection of AXISRAM5 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM6PUB_Pos            (3U)
+#define RCC_PUBCFGR5_AXISRAM6PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGR5_AXISRAM6PUB                RCC_PUBCFGR5_AXISRAM6PUB_Msk         /*!< Public protection of AXISRAM6 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos            (4U)
+#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGR5_AHBSRAM1PUB                RCC_PUBCFGR5_AHBSRAM1PUB_Msk         /*!< Public protection of AHBSRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos            (5U)
+#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGR5_AHBSRAM2PUB                RCC_PUBCFGR5_AHBSRAM2PUB_Msk         /*!< Public protection of AHBSRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_BKPSRAMPUB_Pos             (6U)
+#define RCC_PUBCFGR5_BKPSRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */
+#define RCC_PUBCFGR5_BKPSRAMPUB                 RCC_PUBCFGR5_BKPSRAMPUB_Msk          /*!< Public protection of BKPSRAM bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM1PUB_Pos            (7U)
+#define RCC_PUBCFGR5_AXISRAM1PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGR5_AXISRAM1PUB                RCC_PUBCFGR5_AXISRAM1PUB_Msk         /*!< Public protection of AXISRAM1 bus configuration bits */
+#define RCC_PUBCFGR5_AXISRAM2PUB_Pos            (8U)
+#define RCC_PUBCFGR5_AXISRAM2PUB_Msk            (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGR5_AXISRAM2PUB                RCC_PUBCFGR5_AXISRAM2PUB_Msk         /*!< Public protection of AXISRAM2 bus configuration bits */
+#define RCC_PUBCFGR5_FLEXRAMPUB_Pos             (9U)
+#define RCC_PUBCFGR5_FLEXRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */
+#define RCC_PUBCFGR5_FLEXRAMPUB                 RCC_PUBCFGR5_FLEXRAMPUB_Msk          /*!< Public protection of FLEXRAM bus configuration bits */
+#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos         (10U)
+#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk         (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos)    /*!< 0x00000400 */
+#define RCC_PUBCFGR5_CACHEAXIRAMPUB             RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk      /*!< Public protection of CACHEAXIRAM bus configuration bits */
+#define RCC_PUBCFGR5_VENCRAMPUB_Pos             (11U)
+#define RCC_PUBCFGR5_VENCRAMPUB_Msk             (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */
+#define RCC_PUBCFGR5_VENCRAMPUB                 RCC_PUBCFGR5_VENCRAMPUB_Msk          /*!< Public protection of VENCRAM bus configuration bits */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define RCC_CSR_LSIONS_Pos                      (0U)
+#define RCC_CSR_LSIONS_Msk                      (0x1UL << RCC_CSR_LSIONS_Pos)         /*!< 0x00000001 */
+#define RCC_CSR_LSIONS                          RCC_CSR_LSIONS_Msk                   /*!< LSI oscillator enable */
+#define RCC_CSR_LSEONS_Pos                      (1U)
+#define RCC_CSR_LSEONS_Msk                      (0x1UL << RCC_CSR_LSEONS_Pos)         /*!< 0x00000002 */
+#define RCC_CSR_LSEONS                          RCC_CSR_LSEONS_Msk                   /*!< LSE oscillator enable */
+#define RCC_CSR_MSIONS_Pos                      (2U)
+#define RCC_CSR_MSIONS_Msk                      (0x1UL << RCC_CSR_MSIONS_Pos)         /*!< 0x00000004 */
+#define RCC_CSR_MSIONS                          RCC_CSR_MSIONS_Msk                   /*!< MSI oscillator enable */
+#define RCC_CSR_HSIONS_Pos                      (3U)
+#define RCC_CSR_HSIONS_Msk                      (0x1UL << RCC_CSR_HSIONS_Pos)         /*!< 0x00000008 */
+#define RCC_CSR_HSIONS                          RCC_CSR_HSIONS_Msk                   /*!< HSI oscillator enable */
+#define RCC_CSR_HSEONS_Pos                      (4U)
+#define RCC_CSR_HSEONS_Msk                      (0x1UL << RCC_CSR_HSEONS_Pos)         /*!< 0x00000010 */
+#define RCC_CSR_HSEONS                          RCC_CSR_HSEONS_Msk                   /*!< HSE oscillator enable */
+#define RCC_CSR_PLL1ONS_Pos                     (8U)
+#define RCC_CSR_PLL1ONS_Msk                     (0x1UL << RCC_CSR_PLL1ONS_Pos)        /*!< 0x00000100 */
+#define RCC_CSR_PLL1ONS                         RCC_CSR_PLL1ONS_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CSR_PLL2ONS_Pos                     (9U)
+#define RCC_CSR_PLL2ONS_Msk                     (0x1UL << RCC_CSR_PLL2ONS_Pos)        /*!< 0x00000200 */
+#define RCC_CSR_PLL2ONS                         RCC_CSR_PLL2ONS_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CSR_PLL3ONS_Pos                     (10U)
+#define RCC_CSR_PLL3ONS_Msk                     (0x1UL << RCC_CSR_PLL3ONS_Pos)        /*!< 0x00000400 */
+#define RCC_CSR_PLL3ONS                         RCC_CSR_PLL3ONS_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CSR_PLL4ONS_Pos                     (11U)
+#define RCC_CSR_PLL4ONS_Msk                     (0x1UL << RCC_CSR_PLL4ONS_Pos)        /*!< 0x00000800 */
+#define RCC_CSR_PLL4ONS                         RCC_CSR_PLL4ONS_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCSR register  ******************/
+#define RCC_STOPCSR_MSISTOPENS_Pos              (0U)
+#define RCC_STOPCSR_MSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */
+#define RCC_STOPCSR_MSISTOPENS                  RCC_STOPCSR_MSISTOPENS_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCSR_HSISTOPENS_Pos              (1U)
+#define RCC_STOPCSR_HSISTOPENS_Msk              (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */
+#define RCC_STOPCSR_HSISTOPENS                  RCC_STOPCSR_HSISTOPENS_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTSR register  *****************/
+#define RCC_MISCRSTSR_DBGRSTS_Pos               (0U)
+#define RCC_MISCRSTSR_DBGRSTS_Msk               (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTSR_DBGRSTS                   RCC_MISCRSTSR_DBGRSTS_Msk            /*!< DBG reset */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos          (4U)
+#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTSR_XSPIPHY1RSTS              RCC_MISCRSTSR_XSPIPHY1RSTS_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos          (5U)
+#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk          (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTSR_XSPIPHY2RSTS              RCC_MISCRSTSR_XSPIPHY2RSTS_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos         (7U)
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTSR_SDMMC1DLLRSTS             RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos         (8U)
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk         (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTSR_SDMMC2DLLRSTS             RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTSR register  *****************/
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos           (0U)
+#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTSR_AXISRAM3RSTS               RCC_MEMRSTSR_AXISRAM3RSTS_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos           (1U)
+#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTSR_AXISRAM4RSTS               RCC_MEMRSTSR_AXISRAM4RSTS_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos           (2U)
+#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTSR_AXISRAM5RSTS               RCC_MEMRSTSR_AXISRAM5RSTS_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos           (3U)
+#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTSR_AXISRAM6RSTS               RCC_MEMRSTSR_AXISRAM6RSTS_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos           (4U)
+#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTSR_AHBSRAM1RSTS               RCC_MEMRSTSR_AHBSRAM1RSTS_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos           (5U)
+#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTSR_AHBSRAM2RSTS               RCC_MEMRSTSR_AHBSRAM2RSTS_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos           (7U)
+#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTSR_AXISRAM1RSTS               RCC_MEMRSTSR_AXISRAM1RSTS_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos           (8U)
+#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk           (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTSR_AXISRAM2RSTS               RCC_MEMRSTSR_AXISRAM2RSTS_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos            (9U)
+#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTSR_FLEXRAMRSTS                RCC_MEMRSTSR_FLEXRAMRSTS_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos        (10U)
+#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk        (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos)     /*!< 0x00000400 */
+#define RCC_MEMRSTSR_CACHEAXIRAMRSTS            RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk     /*!< CACHEAXIRAM reset */
+#define RCC_MEMRSTSR_VENCRAMRSTS_Pos            (11U)
+#define RCC_MEMRSTSR_VENCRAMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTSR_VENCRAMRSTS                RCC_MEMRSTSR_VENCRAMRSTS_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTSR_BOOTROMRSTS_Pos            (12U)
+#define RCC_MEMRSTSR_BOOTROMRSTS_Msk            (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTSR_BOOTROMRSTS                RCC_MEMRSTSR_BOOTROMRSTS_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTSR register  *****************/
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos            (4U)
+#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk            (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTSR_GPDMA1RSTS                RCC_AHB1RSTSR_GPDMA1RSTS_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTSR_ADC12RSTS_Pos             (5U)
+#define RCC_AHB1RSTSR_ADC12RSTS_Msk             (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTSR_ADC12RSTS                 RCC_AHB1RSTSR_ADC12RSTS_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTSR register  *****************/
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos            (12U)
+#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk            (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTSR_RAMCFGRSTS                RCC_AHB2RSTSR_RAMCFGRSTS_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTSR_MDF1RSTS_Pos              (16U)
+#define RCC_AHB2RSTSR_MDF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTSR_MDF1RSTS                  RCC_AHB2RSTSR_MDF1RSTS_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTSR_ADF1RSTS_Pos              (17U)
+#define RCC_AHB2RSTSR_ADF1RSTS_Msk              (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTSR_ADF1RSTS                  RCC_AHB2RSTSR_ADF1RSTS_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTSR register  *****************/
+#define RCC_AHB3RSTSR_RNGRSTS_Pos               (0U)
+#define RCC_AHB3RSTSR_RNGRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTSR_RNGRSTS                   RCC_AHB3RSTSR_RNGRSTS_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTSR_HASHRSTS_Pos              (1U)
+#define RCC_AHB3RSTSR_HASHRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTSR_HASHRSTS                  RCC_AHB3RSTSR_HASHRSTS_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTSR_CRYPRSTS_Pos              (2U)
+#define RCC_AHB3RSTSR_CRYPRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_AHB3RSTSR_CRYPRSTS                  RCC_AHB3RSTSR_CRYPRSTS_Msk           /*!< CRYP reset */
+#define RCC_AHB3RSTSR_SAESRSTS_Pos              (4U)
+#define RCC_AHB3RSTSR_SAESRSTS_Msk              (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */
+#define RCC_AHB3RSTSR_SAESRSTS                  RCC_AHB3RSTSR_SAESRSTS_Msk           /*!< SAES reset */
+#define RCC_AHB3RSTSR_PKARSTS_Pos               (8U)
+#define RCC_AHB3RSTSR_PKARSTS_Msk               (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTSR_PKARSTS                   RCC_AHB3RSTSR_PKARSTS_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTSR_IACRSTS_Pos               (10U)
+#define RCC_AHB3RSTSR_IACRSTS_Msk               (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTSR_IACRSTS                   RCC_AHB3RSTSR_IACRSTS_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTSR register  *****************/
+#define RCC_AHB4RSTSR_GPIOARSTS_Pos             (0U)
+#define RCC_AHB4RSTSR_GPIOARSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTSR_GPIOARSTS                 RCC_AHB4RSTSR_GPIOARSTS_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTSR_GPIOBRSTS_Pos             (1U)
+#define RCC_AHB4RSTSR_GPIOBRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTSR_GPIOBRSTS                 RCC_AHB4RSTSR_GPIOBRSTS_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTSR_GPIOCRSTS_Pos             (2U)
+#define RCC_AHB4RSTSR_GPIOCRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTSR_GPIOCRSTS                 RCC_AHB4RSTSR_GPIOCRSTS_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTSR_GPIODRSTS_Pos             (3U)
+#define RCC_AHB4RSTSR_GPIODRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTSR_GPIODRSTS                 RCC_AHB4RSTSR_GPIODRSTS_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTSR_GPIOERSTS_Pos             (4U)
+#define RCC_AHB4RSTSR_GPIOERSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTSR_GPIOERSTS                 RCC_AHB4RSTSR_GPIOERSTS_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTSR_GPIOFRSTS_Pos             (5U)
+#define RCC_AHB4RSTSR_GPIOFRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTSR_GPIOFRSTS                 RCC_AHB4RSTSR_GPIOFRSTS_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTSR_GPIOGRSTS_Pos             (6U)
+#define RCC_AHB4RSTSR_GPIOGRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTSR_GPIOGRSTS                 RCC_AHB4RSTSR_GPIOGRSTS_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTSR_GPIOHRSTS_Pos             (7U)
+#define RCC_AHB4RSTSR_GPIOHRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTSR_GPIOHRSTS                 RCC_AHB4RSTSR_GPIOHRSTS_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTSR_GPIONRSTS_Pos             (13U)
+#define RCC_AHB4RSTSR_GPIONRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTSR_GPIONRSTS                 RCC_AHB4RSTSR_GPIONRSTS_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTSR_GPIOORSTS_Pos             (14U)
+#define RCC_AHB4RSTSR_GPIOORSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTSR_GPIOORSTS                 RCC_AHB4RSTSR_GPIOORSTS_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTSR_GPIOPRSTS_Pos             (15U)
+#define RCC_AHB4RSTSR_GPIOPRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTSR_GPIOPRSTS                 RCC_AHB4RSTSR_GPIOPRSTS_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTSR_GPIOQRSTS_Pos             (16U)
+#define RCC_AHB4RSTSR_GPIOQRSTS_Msk             (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTSR_GPIOQRSTS                 RCC_AHB4RSTSR_GPIOQRSTS_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTSR_PWRRSTS_Pos               (18U)
+#define RCC_AHB4RSTSR_PWRRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTSR_PWRRSTS                   RCC_AHB4RSTSR_PWRRSTS_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTSR_CRCRSTS_Pos               (19U)
+#define RCC_AHB4RSTSR_CRCRSTS_Msk               (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTSR_CRCRSTS                   RCC_AHB4RSTSR_CRCRSTS_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTSR register  *****************/
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos            (0U)
+#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTSR_HPDMA1RSTS                RCC_AHB5RSTSR_HPDMA1RSTS_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTSR_DMA2DRSTS_Pos             (1U)
+#define RCC_AHB5RSTSR_DMA2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTSR_DMA2DRSTS                 RCC_AHB5RSTSR_DMA2DRSTS_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTSR_JPEGRSTS_Pos              (3U)
+#define RCC_AHB5RSTSR_JPEGRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTSR_JPEGRSTS                  RCC_AHB5RSTSR_JPEGRSTS_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTSR_FMCRSTS_Pos               (4U)
+#define RCC_AHB5RSTSR_FMCRSTS_Msk               (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTSR_FMCRSTS                   RCC_AHB5RSTSR_FMCRSTS_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTSR_XSPI1RSTS_Pos             (5U)
+#define RCC_AHB5RSTSR_XSPI1RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTSR_XSPI1RSTS                 RCC_AHB5RSTSR_XSPI1RSTS_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTSR_PSSIRSTS_Pos              (6U)
+#define RCC_AHB5RSTSR_PSSIRSTS_Msk              (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTSR_PSSIRSTS                  RCC_AHB5RSTSR_PSSIRSTS_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos            (7U)
+#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTSR_SDMMC2RSTS                RCC_AHB5RSTSR_SDMMC2RSTS_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos            (8U)
+#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk            (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTSR_SDMMC1RSTS                RCC_AHB5RSTSR_SDMMC1RSTS_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTSR_XSPI2RSTS_Pos             (12U)
+#define RCC_AHB5RSTSR_XSPI2RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTSR_XSPI2RSTS                 RCC_AHB5RSTSR_XSPI2RSTS_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTSR_XSPIMRSTS_Pos             (13U)
+#define RCC_AHB5RSTSR_XSPIMRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTSR_XSPIMRSTS                 RCC_AHB5RSTSR_XSPIMRSTS_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTSR_XSPI3RSTS_Pos             (17U)
+#define RCC_AHB5RSTSR_XSPI3RSTS_Msk             (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTSR_XSPI3RSTS                 RCC_AHB5RSTSR_XSPI3RSTS_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTSR_GFXMMURSTS_Pos            (19U)
+#define RCC_AHB5RSTSR_GFXMMURSTS_Msk            (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTSR_GFXMMURSTS                RCC_AHB5RSTSR_GFXMMURSTS_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTSR_GPU2DRSTS_Pos             (20U)
+#define RCC_AHB5RSTSR_GPU2DRSTS_Msk             (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTSR_GPU2DRSTS                 RCC_AHB5RSTSR_GPU2DRSTS_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos        (23U)
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS            RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos        (24U)
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk        (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS            RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTSR_ETH1RSTS_Pos              (25U)
+#define RCC_AHB5RSTSR_ETH1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTSR_ETH1RSTS                  RCC_AHB5RSTSR_ETH1RSTS_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTSR_OTG1RSTS_Pos              (26U)
+#define RCC_AHB5RSTSR_OTG1RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTSR_OTG1RSTS                  RCC_AHB5RSTSR_OTG1RSTS_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos           (27U)
+#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTSR_OTGPHY1RSTS               RCC_AHB5RSTSR_OTGPHY1RSTS_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos           (28U)
+#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk           (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTSR_OTGPHY2RSTS               RCC_AHB5RSTSR_OTGPHY2RSTS_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTSR_OTG2RSTS_Pos              (29U)
+#define RCC_AHB5RSTSR_OTG2RSTS_Msk              (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTSR_OTG2RSTS                  RCC_AHB5RSTSR_OTG2RSTS_Msk           /*!< OTG2 reset */
+#define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos          (30U)
+#define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk          (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos)   /*!< 0x40000000 */
+#define RCC_AHB5RSTSR_CACHEAXIRSTS              RCC_AHB5RSTSR_CACHEAXIRSTS_Msk       /*!< CACHEAXI reset */
+#define RCC_AHB5RSTSR_NPURSTS_Pos               (31U)
+#define RCC_AHB5RSTSR_NPURSTS_Msk               (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos)  /*!< 0x80000000 */
+#define RCC_AHB5RSTSR_NPURSTS                   RCC_AHB5RSTSR_NPURSTS_Msk            /*!< NPU reset */
+
+/****************  Bit definition for RCC_APB1RSTSR1 register  ****************/
+#define RCC_APB1RSTSR1_TIM2RSTS_Pos             (0U)
+#define RCC_APB1RSTSR1_TIM2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTSR1_TIM2RSTS                 RCC_APB1RSTSR1_TIM2RSTS_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTSR1_TIM3RSTS_Pos             (1U)
+#define RCC_APB1RSTSR1_TIM3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTSR1_TIM3RSTS                 RCC_APB1RSTSR1_TIM3RSTS_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTSR1_TIM4RSTS_Pos             (2U)
+#define RCC_APB1RSTSR1_TIM4RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTSR1_TIM4RSTS                 RCC_APB1RSTSR1_TIM4RSTS_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTSR1_TIM5RSTS_Pos             (3U)
+#define RCC_APB1RSTSR1_TIM5RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTSR1_TIM5RSTS                 RCC_APB1RSTSR1_TIM5RSTS_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTSR1_TIM6RSTS_Pos             (4U)
+#define RCC_APB1RSTSR1_TIM6RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTSR1_TIM6RSTS                 RCC_APB1RSTSR1_TIM6RSTS_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTSR1_TIM7RSTS_Pos             (5U)
+#define RCC_APB1RSTSR1_TIM7RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTSR1_TIM7RSTS                 RCC_APB1RSTSR1_TIM7RSTS_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTSR1_TIM12RSTS_Pos            (6U)
+#define RCC_APB1RSTSR1_TIM12RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTSR1_TIM12RSTS                RCC_APB1RSTSR1_TIM12RSTS_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTSR1_TIM13RSTS_Pos            (7U)
+#define RCC_APB1RSTSR1_TIM13RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTSR1_TIM13RSTS                RCC_APB1RSTSR1_TIM13RSTS_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTSR1_TIM14RSTS_Pos            (8U)
+#define RCC_APB1RSTSR1_TIM14RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR1_TIM14RSTS                RCC_APB1RSTSR1_TIM14RSTS_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos           (9U)
+#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTSR1_LPTIM1RSTS               RCC_APB1RSTSR1_LPTIM1RSTS_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTSR1_WWDGRSTS_Pos             (11U)
+#define RCC_APB1RSTSR1_WWDGRSTS_Msk             (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTSR1_WWDGRSTS                 RCC_APB1RSTSR1_WWDGRSTS_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTSR1_TIM10RSTS_Pos            (12U)
+#define RCC_APB1RSTSR1_TIM10RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTSR1_TIM10RSTS                RCC_APB1RSTSR1_TIM10RSTS_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTSR1_TIM11RSTS_Pos            (13U)
+#define RCC_APB1RSTSR1_TIM11RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTSR1_TIM11RSTS                RCC_APB1RSTSR1_TIM11RSTS_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTSR1_SPI2RSTS_Pos             (14U)
+#define RCC_APB1RSTSR1_SPI2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTSR1_SPI2RSTS                 RCC_APB1RSTSR1_SPI2RSTS_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTSR1_SPI3RSTS_Pos             (15U)
+#define RCC_APB1RSTSR1_SPI3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTSR1_SPI3RSTS                 RCC_APB1RSTSR1_SPI3RSTS_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos         (16U)
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk         (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTSR1_SPDIFRX1RSTS             RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTSR1_USART2RSTS_Pos           (17U)
+#define RCC_APB1RSTSR1_USART2RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTSR1_USART2RSTS               RCC_APB1RSTSR1_USART2RSTS_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTSR1_USART3RSTS_Pos           (18U)
+#define RCC_APB1RSTSR1_USART3RSTS_Msk           (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTSR1_USART3RSTS               RCC_APB1RSTSR1_USART3RSTS_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTSR1_UART4RSTS_Pos            (19U)
+#define RCC_APB1RSTSR1_UART4RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTSR1_UART4RSTS                RCC_APB1RSTSR1_UART4RSTS_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTSR1_UART5RSTS_Pos            (20U)
+#define RCC_APB1RSTSR1_UART5RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTSR1_UART5RSTS                RCC_APB1RSTSR1_UART5RSTS_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTSR1_I2C1RSTS_Pos             (21U)
+#define RCC_APB1RSTSR1_I2C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTSR1_I2C1RSTS                 RCC_APB1RSTSR1_I2C1RSTS_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTSR1_I2C2RSTS_Pos             (22U)
+#define RCC_APB1RSTSR1_I2C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTSR1_I2C2RSTS                 RCC_APB1RSTSR1_I2C2RSTS_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTSR1_I2C3RSTS_Pos             (23U)
+#define RCC_APB1RSTSR1_I2C3RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTSR1_I2C3RSTS                 RCC_APB1RSTSR1_I2C3RSTS_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTSR1_I3C1RSTS_Pos             (24U)
+#define RCC_APB1RSTSR1_I3C1RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTSR1_I3C1RSTS                 RCC_APB1RSTSR1_I3C1RSTS_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTSR1_I3C2RSTS_Pos             (25U)
+#define RCC_APB1RSTSR1_I3C2RSTS_Msk             (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTSR1_I3C2RSTS                 RCC_APB1RSTSR1_I3C2RSTS_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTSR1_UART7RSTS_Pos            (30U)
+#define RCC_APB1RSTSR1_UART7RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTSR1_UART7RSTS                RCC_APB1RSTSR1_UART7RSTS_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTSR1_UART8RSTS_Pos            (31U)
+#define RCC_APB1RSTSR1_UART8RSTS_Msk            (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTSR1_UART8RSTS                RCC_APB1RSTSR1_UART8RSTS_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTSR2 register  ****************/
+#define RCC_APB1RSTSR2_MDIOSRSTS_Pos            (5U)
+#define RCC_APB1RSTSR2_MDIOSRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTSR2_MDIOSRSTS                RCC_APB1RSTSR2_MDIOSRSTS_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTSR2_FDCANRSTS_Pos            (8U)
+#define RCC_APB1RSTSR2_FDCANRSTS_Msk            (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTSR2_FDCANRSTS                RCC_APB1RSTSR2_FDCANRSTS_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTSR2_UCPD1RSTS_Pos            (18U)
+#define RCC_APB1RSTSR2_UCPD1RSTS_Msk            (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTSR2_UCPD1RSTS                RCC_APB1RSTSR2_UCPD1RSTS_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTSR register  *****************/
+#define RCC_APB2RSTSR_TIM1RSTS_Pos              (0U)
+#define RCC_APB2RSTSR_TIM1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTSR_TIM1RSTS                  RCC_APB2RSTSR_TIM1RSTS_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTSR_TIM8RSTS_Pos              (1U)
+#define RCC_APB2RSTSR_TIM8RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTSR_TIM8RSTS                  RCC_APB2RSTSR_TIM8RSTS_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTSR_USART1RSTS_Pos            (4U)
+#define RCC_APB2RSTSR_USART1RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTSR_USART1RSTS                RCC_APB2RSTSR_USART1RSTS_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTSR_USART6RSTS_Pos            (5U)
+#define RCC_APB2RSTSR_USART6RSTS_Msk            (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTSR_USART6RSTS                RCC_APB2RSTSR_USART6RSTS_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTSR_UART9RSTS_Pos             (6U)
+#define RCC_APB2RSTSR_UART9RSTS_Msk             (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTSR_UART9RSTS                 RCC_APB2RSTSR_UART9RSTS_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTSR_USART10RSTS_Pos           (7U)
+#define RCC_APB2RSTSR_USART10RSTS_Msk           (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTSR_USART10RSTS               RCC_APB2RSTSR_USART10RSTS_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTSR_SPI1RSTS_Pos              (12U)
+#define RCC_APB2RSTSR_SPI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTSR_SPI1RSTS                  RCC_APB2RSTSR_SPI1RSTS_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTSR_SPI4RSTS_Pos              (13U)
+#define RCC_APB2RSTSR_SPI4RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTSR_SPI4RSTS                  RCC_APB2RSTSR_SPI4RSTS_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTSR_TIM18RSTS_Pos             (15U)
+#define RCC_APB2RSTSR_TIM18RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTSR_TIM18RSTS                 RCC_APB2RSTSR_TIM18RSTS_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTSR_TIM15RSTS_Pos             (16U)
+#define RCC_APB2RSTSR_TIM15RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTSR_TIM15RSTS                 RCC_APB2RSTSR_TIM15RSTS_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTSR_TIM16RSTS_Pos             (17U)
+#define RCC_APB2RSTSR_TIM16RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTSR_TIM16RSTS                 RCC_APB2RSTSR_TIM16RSTS_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTSR_TIM17RSTS_Pos             (18U)
+#define RCC_APB2RSTSR_TIM17RSTS_Msk             (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTSR_TIM17RSTS                 RCC_APB2RSTSR_TIM17RSTS_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTSR_TIM9RSTS_Pos              (19U)
+#define RCC_APB2RSTSR_TIM9RSTS_Msk              (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTSR_TIM9RSTS                  RCC_APB2RSTSR_TIM9RSTS_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTSR_SPI5RSTS_Pos              (20U)
+#define RCC_APB2RSTSR_SPI5RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTSR_SPI5RSTS                  RCC_APB2RSTSR_SPI5RSTS_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTSR_SAI1RSTS_Pos              (21U)
+#define RCC_APB2RSTSR_SAI1RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTSR_SAI1RSTS                  RCC_APB2RSTSR_SAI1RSTS_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTSR_SAI2RSTS_Pos              (22U)
+#define RCC_APB2RSTSR_SAI2RSTS_Msk              (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTSR_SAI2RSTS                  RCC_APB2RSTSR_SAI2RSTS_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTSR1 register  ****************/
+#define RCC_APB4RSTSR1_HDPRSTS_Pos              (2U)
+#define RCC_APB4RSTSR1_HDPRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR1_HDPRSTS                  RCC_APB4RSTSR1_HDPRSTS_Msk           /*!< HDP reset */
+#define RCC_APB4RSTSR1_LPUART1RSTS_Pos          (3U)
+#define RCC_APB4RSTSR1_LPUART1RSTS_Msk          (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTSR1_LPUART1RSTS              RCC_APB4RSTSR1_LPUART1RSTS_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTSR1_SPI6RSTS_Pos             (5U)
+#define RCC_APB4RSTSR1_SPI6RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTSR1_SPI6RSTS                 RCC_APB4RSTSR1_SPI6RSTS_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTSR1_I2C4RSTS_Pos             (7U)
+#define RCC_APB4RSTSR1_I2C4RSTS_Msk             (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTSR1_I2C4RSTS                 RCC_APB4RSTSR1_I2C4RSTS_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos           (9U)
+#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTSR1_LPTIM2RSTS               RCC_APB4RSTSR1_LPTIM2RSTS_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos           (10U)
+#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTSR1_LPTIM3RSTS               RCC_APB4RSTSR1_LPTIM3RSTS_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos           (11U)
+#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTSR1_LPTIM4RSTS               RCC_APB4RSTSR1_LPTIM4RSTS_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos           (12U)
+#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk           (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTSR1_LPTIM5RSTS               RCC_APB4RSTSR1_LPTIM5RSTS_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos          (15U)
+#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk          (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTSR1_VREFBUFRSTS              RCC_APB4RSTSR1_VREFBUFRSTS_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTSR1_RTCRSTS_Pos              (16U)
+#define RCC_APB4RSTSR1_RTCRSTS_Msk              (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTSR1_RTCRSTS                  RCC_APB4RSTSR1_RTCRSTS_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTSR2 register  ****************/
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos           (0U)
+#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk           (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTSR2_SYSCFGRSTS               RCC_APB4RSTSR2_SYSCFGRSTS_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTSR2_DTSRSTS_Pos              (2U)
+#define RCC_APB4RSTSR2_DTSRSTS_Msk              (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTSR2_DTSRSTS                  RCC_APB4RSTSR2_DTSRSTS_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTSR register  *****************/
+#define RCC_APB5RSTSR_LTDCRSTS_Pos              (1U)
+#define RCC_APB5RSTSR_LTDCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTSR_LTDCRSTS                  RCC_APB5RSTSR_LTDCRSTS_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTSR_DCMIPPRSTS_Pos            (2U)
+#define RCC_APB5RSTSR_DCMIPPRSTS_Msk            (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTSR_DCMIPPRSTS                RCC_APB5RSTSR_DCMIPPRSTS_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTSR_GFXTIMRSTS_Pos            (4U)
+#define RCC_APB5RSTSR_GFXTIMRSTS_Msk            (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTSR_GFXTIMRSTS                RCC_APB5RSTSR_GFXTIMRSTS_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTSR_VENCRSTS_Pos              (5U)
+#define RCC_APB5RSTSR_VENCRSTS_Msk              (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTSR_VENCRSTS                  RCC_APB5RSTSR_VENCRSTS_Msk           /*!< VENC reset */
+#define RCC_APB5RSTSR_CSIRSTS_Pos               (6U)
+#define RCC_APB5RSTSR_CSIRSTS_Msk               (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTSR_CSIRSTS                   RCC_APB5RSTSR_CSIRSTS_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENSR register  ******************/
+#define RCC_DIVENSR_IC1ENS_Pos                  (0U)
+#define RCC_DIVENSR_IC1ENS_Msk                  (0x1UL << RCC_DIVENSR_IC1ENS_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENSR_IC1ENS                      RCC_DIVENSR_IC1ENS_Msk               /*!< IC1 enable */
+#define RCC_DIVENSR_IC2ENS_Pos                  (1U)
+#define RCC_DIVENSR_IC2ENS_Msk                  (0x1UL << RCC_DIVENSR_IC2ENS_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENSR_IC2ENS                      RCC_DIVENSR_IC2ENS_Msk               /*!< IC2 enable */
+#define RCC_DIVENSR_IC3ENS_Pos                  (2U)
+#define RCC_DIVENSR_IC3ENS_Msk                  (0x1UL << RCC_DIVENSR_IC3ENS_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENSR_IC3ENS                      RCC_DIVENSR_IC3ENS_Msk               /*!< IC3 enable */
+#define RCC_DIVENSR_IC4ENS_Pos                  (3U)
+#define RCC_DIVENSR_IC4ENS_Msk                  (0x1UL << RCC_DIVENSR_IC4ENS_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENSR_IC4ENS                      RCC_DIVENSR_IC4ENS_Msk               /*!< IC4 enable */
+#define RCC_DIVENSR_IC5ENS_Pos                  (4U)
+#define RCC_DIVENSR_IC5ENS_Msk                  (0x1UL << RCC_DIVENSR_IC5ENS_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENSR_IC5ENS                      RCC_DIVENSR_IC5ENS_Msk               /*!< IC5 enable */
+#define RCC_DIVENSR_IC6ENS_Pos                  (5U)
+#define RCC_DIVENSR_IC6ENS_Msk                  (0x1UL << RCC_DIVENSR_IC6ENS_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENSR_IC6ENS                      RCC_DIVENSR_IC6ENS_Msk               /*!< IC6 enable */
+#define RCC_DIVENSR_IC7ENS_Pos                  (6U)
+#define RCC_DIVENSR_IC7ENS_Msk                  (0x1UL << RCC_DIVENSR_IC7ENS_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENSR_IC7ENS                      RCC_DIVENSR_IC7ENS_Msk               /*!< IC7 enable */
+#define RCC_DIVENSR_IC8ENS_Pos                  (7U)
+#define RCC_DIVENSR_IC8ENS_Msk                  (0x1UL << RCC_DIVENSR_IC8ENS_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENSR_IC8ENS                      RCC_DIVENSR_IC8ENS_Msk               /*!< IC8 enable */
+#define RCC_DIVENSR_IC9ENS_Pos                  (8U)
+#define RCC_DIVENSR_IC9ENS_Msk                  (0x1UL << RCC_DIVENSR_IC9ENS_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENSR_IC9ENS                      RCC_DIVENSR_IC9ENS_Msk               /*!< IC9 enable */
+#define RCC_DIVENSR_IC10ENS_Pos                 (9U)
+#define RCC_DIVENSR_IC10ENS_Msk                 (0x1UL << RCC_DIVENSR_IC10ENS_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENSR_IC10ENS                     RCC_DIVENSR_IC10ENS_Msk              /*!< IC10 enable */
+#define RCC_DIVENSR_IC11ENS_Pos                 (10U)
+#define RCC_DIVENSR_IC11ENS_Msk                 (0x1UL << RCC_DIVENSR_IC11ENS_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENSR_IC11ENS                     RCC_DIVENSR_IC11ENS_Msk              /*!< IC11 enable */
+#define RCC_DIVENSR_IC12ENS_Pos                 (11U)
+#define RCC_DIVENSR_IC12ENS_Msk                 (0x1UL << RCC_DIVENSR_IC12ENS_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENSR_IC12ENS                     RCC_DIVENSR_IC12ENS_Msk              /*!< IC12 enable */
+#define RCC_DIVENSR_IC13ENS_Pos                 (12U)
+#define RCC_DIVENSR_IC13ENS_Msk                 (0x1UL << RCC_DIVENSR_IC13ENS_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENSR_IC13ENS                     RCC_DIVENSR_IC13ENS_Msk              /*!< IC13 enable */
+#define RCC_DIVENSR_IC14ENS_Pos                 (13U)
+#define RCC_DIVENSR_IC14ENS_Msk                 (0x1UL << RCC_DIVENSR_IC14ENS_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENSR_IC14ENS                     RCC_DIVENSR_IC14ENS_Msk              /*!< IC14 enable */
+#define RCC_DIVENSR_IC15ENS_Pos                 (14U)
+#define RCC_DIVENSR_IC15ENS_Msk                 (0x1UL << RCC_DIVENSR_IC15ENS_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENSR_IC15ENS                     RCC_DIVENSR_IC15ENS_Msk              /*!< IC15 enable */
+#define RCC_DIVENSR_IC16ENS_Pos                 (15U)
+#define RCC_DIVENSR_IC16ENS_Msk                 (0x1UL << RCC_DIVENSR_IC16ENS_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENSR_IC16ENS                     RCC_DIVENSR_IC16ENS_Msk              /*!< IC16 enable */
+#define RCC_DIVENSR_IC17ENS_Pos                 (16U)
+#define RCC_DIVENSR_IC17ENS_Msk                 (0x1UL << RCC_DIVENSR_IC17ENS_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENSR_IC17ENS                     RCC_DIVENSR_IC17ENS_Msk              /*!< IC17 enable */
+#define RCC_DIVENSR_IC18ENS_Pos                 (17U)
+#define RCC_DIVENSR_IC18ENS_Msk                 (0x1UL << RCC_DIVENSR_IC18ENS_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENSR_IC18ENS                     RCC_DIVENSR_IC18ENS_Msk              /*!< IC18 enable */
+#define RCC_DIVENSR_IC19ENS_Pos                 (18U)
+#define RCC_DIVENSR_IC19ENS_Msk                 (0x1UL << RCC_DIVENSR_IC19ENS_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENSR_IC19ENS                     RCC_DIVENSR_IC19ENS_Msk              /*!< IC19 enable */
+#define RCC_DIVENSR_IC20ENS_Pos                 (19U)
+#define RCC_DIVENSR_IC20ENS_Msk                 (0x1UL << RCC_DIVENSR_IC20ENS_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENSR_IC20ENS                     RCC_DIVENSR_IC20ENS_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENSR register  ******************/
+#define RCC_BUSENSR_ACLKNENS_Pos                (0U)
+#define RCC_BUSENSR_ACLKNENS_Msk                (0x1UL << RCC_BUSENSR_ACLKNENS_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENSR_ACLKNENS                    RCC_BUSENSR_ACLKNENS_Msk             /*!< ACLKN enable */
+#define RCC_BUSENSR_ACLKNCENS_Pos               (1U)
+#define RCC_BUSENSR_ACLKNCENS_Msk               (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENSR_ACLKNCENS                   RCC_BUSENSR_ACLKNCENS_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENSR_AHBMENS_Pos                 (2U)
+#define RCC_BUSENSR_AHBMENS_Msk                 (0x1UL << RCC_BUSENSR_AHBMENS_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENSR_AHBMENS                     RCC_BUSENSR_AHBMENS_Msk              /*!< AHBM enable */
+#define RCC_BUSENSR_AHB1ENS_Pos                 (3U)
+#define RCC_BUSENSR_AHB1ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB1ENS_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENSR_AHB1ENS                     RCC_BUSENSR_AHB1ENS_Msk              /*!< AHB1 enable */
+#define RCC_BUSENSR_AHB2ENS_Pos                 (4U)
+#define RCC_BUSENSR_AHB2ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB2ENS_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENSR_AHB2ENS                     RCC_BUSENSR_AHB2ENS_Msk              /*!< AHB2 enable */
+#define RCC_BUSENSR_AHB3ENS_Pos                 (5U)
+#define RCC_BUSENSR_AHB3ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB3ENS_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENSR_AHB3ENS                     RCC_BUSENSR_AHB3ENS_Msk              /*!< AHB3 enable */
+#define RCC_BUSENSR_AHB4ENS_Pos                 (6U)
+#define RCC_BUSENSR_AHB4ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB4ENS_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENSR_AHB4ENS                     RCC_BUSENSR_AHB4ENS_Msk              /*!< AHB4 enable */
+#define RCC_BUSENSR_AHB5ENS_Pos                 (7U)
+#define RCC_BUSENSR_AHB5ENS_Msk                 (0x1UL << RCC_BUSENSR_AHB5ENS_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENSR_AHB5ENS                     RCC_BUSENSR_AHB5ENS_Msk              /*!< AHB5 enable */
+#define RCC_BUSENSR_APB1ENS_Pos                 (8U)
+#define RCC_BUSENSR_APB1ENS_Msk                 (0x1UL << RCC_BUSENSR_APB1ENS_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENSR_APB1ENS                     RCC_BUSENSR_APB1ENS_Msk              /*!< APB1 enable */
+#define RCC_BUSENSR_APB2ENS_Pos                 (9U)
+#define RCC_BUSENSR_APB2ENS_Msk                 (0x1UL << RCC_BUSENSR_APB2ENS_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENSR_APB2ENS                     RCC_BUSENSR_APB2ENS_Msk              /*!< APB2 enable */
+#define RCC_BUSENSR_APB3ENS_Pos                 (10U)
+#define RCC_BUSENSR_APB3ENS_Msk                 (0x1UL << RCC_BUSENSR_APB3ENS_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENSR_APB3ENS                     RCC_BUSENSR_APB3ENS_Msk              /*!< APB3 enable */
+#define RCC_BUSENSR_APB4ENS_Pos                 (11U)
+#define RCC_BUSENSR_APB4ENS_Msk                 (0x1UL << RCC_BUSENSR_APB4ENS_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENSR_APB4ENS                     RCC_BUSENSR_APB4ENS_Msk              /*!< APB4 enable */
+#define RCC_BUSENSR_APB5ENS_Pos                 (12U)
+#define RCC_BUSENSR_APB5ENS_Msk                 (0x1UL << RCC_BUSENSR_APB5ENS_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENSR_APB5ENS                     RCC_BUSENSR_APB5ENS_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENSR register  *****************/
+#define RCC_MISCENSR_DBGENS_Pos                 (0U)
+#define RCC_MISCENSR_DBGENS_Msk                 (0x1UL << RCC_MISCENSR_DBGENS_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENSR_DBGENS                     RCC_MISCENSR_DBGENS_Msk              /*!< DBG enable */
+#define RCC_MISCENSR_MCO1ENS_Pos                (1U)
+#define RCC_MISCENSR_MCO1ENS_Msk                (0x1UL << RCC_MISCENSR_MCO1ENS_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENSR_MCO1ENS                    RCC_MISCENSR_MCO1ENS_Msk             /*!< MCO1 enable */
+#define RCC_MISCENSR_MCO2ENS_Pos                (2U)
+#define RCC_MISCENSR_MCO2ENS_Msk                (0x1UL << RCC_MISCENSR_MCO2ENS_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENSR_MCO2ENS                    RCC_MISCENSR_MCO2ENS_Msk             /*!< MCO2 enable */
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos         (3U)
+#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk         (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENSR_XSPIPHYCOMPENS             RCC_MISCENSR_XSPIPHYCOMPENS_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENSR_PERENS_Pos                 (6U)
+#define RCC_MISCENSR_PERENS_Msk                 (0x1UL << RCC_MISCENSR_PERENS_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENSR_PERENS                     RCC_MISCENSR_PERENS_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENSR register  ******************/
+#define RCC_MEMENSR_AXISRAM3ENS_Pos             (0U)
+#define RCC_MEMENSR_AXISRAM3ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */
+#define RCC_MEMENSR_AXISRAM3ENS                 RCC_MEMENSR_AXISRAM3ENS_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENSR_AXISRAM4ENS_Pos             (1U)
+#define RCC_MEMENSR_AXISRAM4ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */
+#define RCC_MEMENSR_AXISRAM4ENS                 RCC_MEMENSR_AXISRAM4ENS_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENSR_AXISRAM5ENS_Pos             (2U)
+#define RCC_MEMENSR_AXISRAM5ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */
+#define RCC_MEMENSR_AXISRAM5ENS                 RCC_MEMENSR_AXISRAM5ENS_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENSR_AXISRAM6ENS_Pos             (3U)
+#define RCC_MEMENSR_AXISRAM6ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */
+#define RCC_MEMENSR_AXISRAM6ENS                 RCC_MEMENSR_AXISRAM6ENS_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENSR_AHBSRAM1ENS_Pos             (4U)
+#define RCC_MEMENSR_AHBSRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */
+#define RCC_MEMENSR_AHBSRAM1ENS                 RCC_MEMENSR_AHBSRAM1ENS_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENSR_AHBSRAM2ENS_Pos             (5U)
+#define RCC_MEMENSR_AHBSRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */
+#define RCC_MEMENSR_AHBSRAM2ENS                 RCC_MEMENSR_AHBSRAM2ENS_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENSR_BKPSRAMENS_Pos              (6U)
+#define RCC_MEMENSR_BKPSRAMENS_Msk              (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */
+#define RCC_MEMENSR_BKPSRAMENS                  RCC_MEMENSR_BKPSRAMENS_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENSR_AXISRAM1ENS_Pos             (7U)
+#define RCC_MEMENSR_AXISRAM1ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */
+#define RCC_MEMENSR_AXISRAM1ENS                 RCC_MEMENSR_AXISRAM1ENS_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENSR_AXISRAM2ENS_Pos             (8U)
+#define RCC_MEMENSR_AXISRAM2ENS_Msk             (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */
+#define RCC_MEMENSR_AXISRAM2ENS                 RCC_MEMENSR_AXISRAM2ENS_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENSR_FLEXRAMENS_Pos              (9U)
+#define RCC_MEMENSR_FLEXRAMENS_Msk              (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */
+#define RCC_MEMENSR_FLEXRAMENS                  RCC_MEMENSR_FLEXRAMENS_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENSR_CACHEAXIRAMENS_Pos          (10U)
+#define RCC_MEMENSR_CACHEAXIRAMENS_Msk          (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos)   /*!< 0x00000400 */
+#define RCC_MEMENSR_CACHEAXIRAMENS              RCC_MEMENSR_CACHEAXIRAMENS_Msk       /*!< CACHEAXIRAM enable */
+#define RCC_MEMENSR_VENCRAMENS_Pos              (11U)
+#define RCC_MEMENSR_VENCRAMENS_Msk              (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */
+#define RCC_MEMENSR_VENCRAMENS                  RCC_MEMENSR_VENCRAMENS_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENSR_BOOTROMENS_Pos              (12U)
+#define RCC_MEMENSR_BOOTROMENS_Msk              (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */
+#define RCC_MEMENSR_BOOTROMENS                  RCC_MEMENSR_BOOTROMENS_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENSR register  *****************/
+#define RCC_AHB1ENSR_GPDMA1ENS_Pos              (4U)
+#define RCC_AHB1ENSR_GPDMA1ENS_Msk              (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENSR_GPDMA1ENS                  RCC_AHB1ENSR_GPDMA1ENS_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENSR_ADC12ENS_Pos               (5U)
+#define RCC_AHB1ENSR_ADC12ENS_Msk               (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENSR_ADC12ENS                   RCC_AHB1ENSR_ADC12ENS_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENSR register  *****************/
+#define RCC_AHB2ENSR_RAMCFGENS_Pos              (12U)
+#define RCC_AHB2ENSR_RAMCFGENS_Msk              (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENSR_RAMCFGENS                  RCC_AHB2ENSR_RAMCFGENS_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENSR_MDF1ENS_Pos                (16U)
+#define RCC_AHB2ENSR_MDF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENSR_MDF1ENS                    RCC_AHB2ENSR_MDF1ENS_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENSR_ADF1ENS_Pos                (17U)
+#define RCC_AHB2ENSR_ADF1ENS_Msk                (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENSR_ADF1ENS                    RCC_AHB2ENSR_ADF1ENS_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENSR register  *****************/
+#define RCC_AHB3ENSR_RNGENS_Pos                 (0U)
+#define RCC_AHB3ENSR_RNGENS_Msk                 (0x1UL << RCC_AHB3ENSR_RNGENS_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENSR_RNGENS                     RCC_AHB3ENSR_RNGENS_Msk              /*!< RNG enable */
+#define RCC_AHB3ENSR_HASHENS_Pos                (1U)
+#define RCC_AHB3ENSR_HASHENS_Msk                (0x1UL << RCC_AHB3ENSR_HASHENS_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENSR_HASHENS                    RCC_AHB3ENSR_HASHENS_Msk             /*!< HASH enable */
+#define RCC_AHB3ENSR_CRYPENS_Pos                (2U)
+#define RCC_AHB3ENSR_CRYPENS_Msk                (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos)   /*!< 0x00000004 */
+#define RCC_AHB3ENSR_CRYPENS                    RCC_AHB3ENSR_CRYPENS_Msk             /*!< CRYP enable */
+#define RCC_AHB3ENSR_SAESENS_Pos                (4U)
+#define RCC_AHB3ENSR_SAESENS_Msk                (0x1UL << RCC_AHB3ENSR_SAESENS_Pos)   /*!< 0x00000010 */
+#define RCC_AHB3ENSR_SAESENS                    RCC_AHB3ENSR_SAESENS_Msk             /*!< SAES enable */
+#define RCC_AHB3ENSR_PKAENS_Pos                 (8U)
+#define RCC_AHB3ENSR_PKAENS_Msk                 (0x1UL << RCC_AHB3ENSR_PKAENS_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENSR_PKAENS                     RCC_AHB3ENSR_PKAENS_Msk              /*!< PKA enable */
+#define RCC_AHB3ENSR_RIFSCENS_Pos               (9U)
+#define RCC_AHB3ENSR_RIFSCENS_Msk               (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENSR_RIFSCENS                   RCC_AHB3ENSR_RIFSCENS_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENSR_IACENS_Pos                 (10U)
+#define RCC_AHB3ENSR_IACENS_Msk                 (0x1UL << RCC_AHB3ENSR_IACENS_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENSR_IACENS                     RCC_AHB3ENSR_IACENS_Msk              /*!< IAC enable */
+#define RCC_AHB3ENSR_RISAFENS_Pos               (14U)
+#define RCC_AHB3ENSR_RISAFENS_Msk               (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENSR_RISAFENS                   RCC_AHB3ENSR_RISAFENS_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENSR register  *****************/
+#define RCC_AHB4ENSR_GPIOAENS_Pos               (0U)
+#define RCC_AHB4ENSR_GPIOAENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENSR_GPIOAENS                   RCC_AHB4ENSR_GPIOAENS_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENSR_GPIOBENS_Pos               (1U)
+#define RCC_AHB4ENSR_GPIOBENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENSR_GPIOBENS                   RCC_AHB4ENSR_GPIOBENS_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENSR_GPIOCENS_Pos               (2U)
+#define RCC_AHB4ENSR_GPIOCENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENSR_GPIOCENS                   RCC_AHB4ENSR_GPIOCENS_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENSR_GPIODENS_Pos               (3U)
+#define RCC_AHB4ENSR_GPIODENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENSR_GPIODENS                   RCC_AHB4ENSR_GPIODENS_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENSR_GPIOEENS_Pos               (4U)
+#define RCC_AHB4ENSR_GPIOEENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENSR_GPIOEENS                   RCC_AHB4ENSR_GPIOEENS_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENSR_GPIOFENS_Pos               (5U)
+#define RCC_AHB4ENSR_GPIOFENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENSR_GPIOFENS                   RCC_AHB4ENSR_GPIOFENS_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENSR_GPIOGENS_Pos               (6U)
+#define RCC_AHB4ENSR_GPIOGENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENSR_GPIOGENS                   RCC_AHB4ENSR_GPIOGENS_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENSR_GPIOHENS_Pos               (7U)
+#define RCC_AHB4ENSR_GPIOHENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENSR_GPIOHENS                   RCC_AHB4ENSR_GPIOHENS_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENSR_GPIONENS_Pos               (13U)
+#define RCC_AHB4ENSR_GPIONENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENSR_GPIONENS                   RCC_AHB4ENSR_GPIONENS_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENSR_GPIOOENS_Pos               (14U)
+#define RCC_AHB4ENSR_GPIOOENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENSR_GPIOOENS                   RCC_AHB4ENSR_GPIOOENS_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENSR_GPIOPENS_Pos               (15U)
+#define RCC_AHB4ENSR_GPIOPENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENSR_GPIOPENS                   RCC_AHB4ENSR_GPIOPENS_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENSR_GPIOQENS_Pos               (16U)
+#define RCC_AHB4ENSR_GPIOQENS_Msk               (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENSR_GPIOQENS                   RCC_AHB4ENSR_GPIOQENS_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENSR_PWRENS_Pos                 (18U)
+#define RCC_AHB4ENSR_PWRENS_Msk                 (0x1UL << RCC_AHB4ENSR_PWRENS_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENSR_PWRENS                     RCC_AHB4ENSR_PWRENS_Msk              /*!< PWR enable */
+#define RCC_AHB4ENSR_CRCENS_Pos                 (19U)
+#define RCC_AHB4ENSR_CRCENS_Msk                 (0x1UL << RCC_AHB4ENSR_CRCENS_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENSR_CRCENS                     RCC_AHB4ENSR_CRCENS_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENSR register  *****************/
+#define RCC_AHB5ENSR_HPDMA1ENS_Pos              (0U)
+#define RCC_AHB5ENSR_HPDMA1ENS_Msk              (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENSR_HPDMA1ENS                  RCC_AHB5ENSR_HPDMA1ENS_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENSR_DMA2DENS_Pos               (1U)
+#define RCC_AHB5ENSR_DMA2DENS_Msk               (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENSR_DMA2DENS                   RCC_AHB5ENSR_DMA2DENS_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENSR_JPEGENS_Pos                (3U)
+#define RCC_AHB5ENSR_JPEGENS_Msk                (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENSR_JPEGENS                    RCC_AHB5ENSR_JPEGENS_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENSR_FMCENS_Pos                 (4U)
+#define RCC_AHB5ENSR_FMCENS_Msk                 (0x1UL << RCC_AHB5ENSR_FMCENS_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENSR_FMCENS                     RCC_AHB5ENSR_FMCENS_Msk              /*!< FMC enable */
+#define RCC_AHB5ENSR_XSPI1ENS_Pos               (5U)
+#define RCC_AHB5ENSR_XSPI1ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENSR_XSPI1ENS                   RCC_AHB5ENSR_XSPI1ENS_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENSR_PSSIENS_Pos                (6U)
+#define RCC_AHB5ENSR_PSSIENS_Msk                (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENSR_PSSIENS                    RCC_AHB5ENSR_PSSIENS_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENSR_SDMMC2ENS_Pos              (7U)
+#define RCC_AHB5ENSR_SDMMC2ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENSR_SDMMC2ENS                  RCC_AHB5ENSR_SDMMC2ENS_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENSR_SDMMC1ENS_Pos              (8U)
+#define RCC_AHB5ENSR_SDMMC1ENS_Msk              (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENSR_SDMMC1ENS                  RCC_AHB5ENSR_SDMMC1ENS_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENSR_XSPI2ENS_Pos               (12U)
+#define RCC_AHB5ENSR_XSPI2ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENSR_XSPI2ENS                   RCC_AHB5ENSR_XSPI2ENS_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENSR_XSPIMENS_Pos               (13U)
+#define RCC_AHB5ENSR_XSPIMENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENSR_XSPIMENS                   RCC_AHB5ENSR_XSPIMENS_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENSR_MCE1ENS_Pos                (14U)
+#define RCC_AHB5ENSR_MCE1ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos)   /*!< 0x00004000 */
+#define RCC_AHB5ENSR_MCE1ENS                    RCC_AHB5ENSR_MCE1ENS_Msk             /*!< MCE1 enable */
+#define RCC_AHB5ENSR_MCE2ENS_Pos                (15U)
+#define RCC_AHB5ENSR_MCE2ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos)   /*!< 0x00008000 */
+#define RCC_AHB5ENSR_MCE2ENS                    RCC_AHB5ENSR_MCE2ENS_Msk             /*!< MCE2 enable */
+#define RCC_AHB5ENSR_MCE3ENS_Pos                (16U)
+#define RCC_AHB5ENSR_MCE3ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos)   /*!< 0x00010000 */
+#define RCC_AHB5ENSR_MCE3ENS                    RCC_AHB5ENSR_MCE3ENS_Msk             /*!< MCE3 enable */
+#define RCC_AHB5ENSR_XSPI3ENS_Pos               (17U)
+#define RCC_AHB5ENSR_XSPI3ENS_Msk               (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENSR_XSPI3ENS                   RCC_AHB5ENSR_XSPI3ENS_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENSR_MCE4ENS_Pos                (18U)
+#define RCC_AHB5ENSR_MCE4ENS_Msk                (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos)   /*!< 0x00040000 */
+#define RCC_AHB5ENSR_MCE4ENS                    RCC_AHB5ENSR_MCE4ENS_Msk             /*!< MCE4 enable */
+#define RCC_AHB5ENSR_GFXMMUENS_Pos              (19U)
+#define RCC_AHB5ENSR_GFXMMUENS_Msk              (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENSR_GFXMMUENS                  RCC_AHB5ENSR_GFXMMUENS_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENSR_GPU2DENS_Pos               (20U)
+#define RCC_AHB5ENSR_GPU2DENS_Msk               (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENSR_GPU2DENS                   RCC_AHB5ENSR_GPU2DENS_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENSR_ETH1MACENS_Pos             (22U)
+#define RCC_AHB5ENSR_ETH1MACENS_Msk             (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENSR_ETH1MACENS                 RCC_AHB5ENSR_ETH1MACENS_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENSR_ETH1TXENS_Pos              (23U)
+#define RCC_AHB5ENSR_ETH1TXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENSR_ETH1TXENS                  RCC_AHB5ENSR_ETH1TXENS_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENSR_ETH1RXENS_Pos              (24U)
+#define RCC_AHB5ENSR_ETH1RXENS_Msk              (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENSR_ETH1RXENS                  RCC_AHB5ENSR_ETH1RXENS_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENSR_ETH1ENS_Pos                (25U)
+#define RCC_AHB5ENSR_ETH1ENS_Msk                (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENSR_ETH1ENS                    RCC_AHB5ENSR_ETH1ENS_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENSR_OTG1ENS_Pos                (26U)
+#define RCC_AHB5ENSR_OTG1ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENSR_OTG1ENS                    RCC_AHB5ENSR_OTG1ENS_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENSR_OTGPHY1ENS_Pos             (27U)
+#define RCC_AHB5ENSR_OTGPHY1ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENSR_OTGPHY1ENS                 RCC_AHB5ENSR_OTGPHY1ENS_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENSR_OTGPHY2ENS_Pos             (28U)
+#define RCC_AHB5ENSR_OTGPHY2ENS_Msk             (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENSR_OTGPHY2ENS                 RCC_AHB5ENSR_OTGPHY2ENS_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENSR_OTG2ENS_Pos                (29U)
+#define RCC_AHB5ENSR_OTG2ENS_Msk                (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENSR_OTG2ENS                    RCC_AHB5ENSR_OTG2ENS_Msk             /*!< OTG2 enable */
+#define RCC_AHB5ENSR_CACHEAXIENS_Pos            (30U)
+#define RCC_AHB5ENSR_CACHEAXIENS_Msk            (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */
+#define RCC_AHB5ENSR_CACHEAXIENS                RCC_AHB5ENSR_CACHEAXIENS_Msk         /*!< CACHEAXI enable */
+#define RCC_AHB5ENSR_NPUENS_Pos                 (31U)
+#define RCC_AHB5ENSR_NPUENS_Msk                 (0x1UL << RCC_AHB5ENSR_NPUENS_Pos)    /*!< 0x80000000 */
+#define RCC_AHB5ENSR_NPUENS                     RCC_AHB5ENSR_NPUENS_Msk              /*!< NPU enable */
+
+/****************  Bit definition for RCC_APB1ENSR1 register  *****************/
+#define RCC_APB1ENSR1_TIM2ENS_Pos               (0U)
+#define RCC_APB1ENSR1_TIM2ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENSR1_TIM2ENS                   RCC_APB1ENSR1_TIM2ENS_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENSR1_TIM3ENS_Pos               (1U)
+#define RCC_APB1ENSR1_TIM3ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENSR1_TIM3ENS                   RCC_APB1ENSR1_TIM3ENS_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENSR1_TIM4ENS_Pos               (2U)
+#define RCC_APB1ENSR1_TIM4ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENSR1_TIM4ENS                   RCC_APB1ENSR1_TIM4ENS_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENSR1_TIM5ENS_Pos               (3U)
+#define RCC_APB1ENSR1_TIM5ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENSR1_TIM5ENS                   RCC_APB1ENSR1_TIM5ENS_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENSR1_TIM6ENS_Pos               (4U)
+#define RCC_APB1ENSR1_TIM6ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENSR1_TIM6ENS                   RCC_APB1ENSR1_TIM6ENS_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENSR1_TIM7ENS_Pos               (5U)
+#define RCC_APB1ENSR1_TIM7ENS_Msk               (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENSR1_TIM7ENS                   RCC_APB1ENSR1_TIM7ENS_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENSR1_TIM12ENS_Pos              (6U)
+#define RCC_APB1ENSR1_TIM12ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENSR1_TIM12ENS                  RCC_APB1ENSR1_TIM12ENS_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENSR1_TIM13ENS_Pos              (7U)
+#define RCC_APB1ENSR1_TIM13ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENSR1_TIM13ENS                  RCC_APB1ENSR1_TIM13ENS_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENSR1_TIM14ENS_Pos              (8U)
+#define RCC_APB1ENSR1_TIM14ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR1_TIM14ENS                  RCC_APB1ENSR1_TIM14ENS_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENSR1_LPTIM1ENS_Pos             (9U)
+#define RCC_APB1ENSR1_LPTIM1ENS_Msk             (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENSR1_LPTIM1ENS                 RCC_APB1ENSR1_LPTIM1ENS_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENSR1_WWDGENS_Pos               (11U)
+#define RCC_APB1ENSR1_WWDGENS_Msk               (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1ENSR1_WWDGENS                   RCC_APB1ENSR1_WWDGENS_Msk            /*!< WWDG enable */
+#define RCC_APB1ENSR1_TIM10ENS_Pos              (12U)
+#define RCC_APB1ENSR1_TIM10ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENSR1_TIM10ENS                  RCC_APB1ENSR1_TIM10ENS_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENSR1_TIM11ENS_Pos              (13U)
+#define RCC_APB1ENSR1_TIM11ENS_Msk              (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENSR1_TIM11ENS                  RCC_APB1ENSR1_TIM11ENS_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENSR1_SPI2ENS_Pos               (14U)
+#define RCC_APB1ENSR1_SPI2ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENSR1_SPI2ENS                   RCC_APB1ENSR1_SPI2ENS_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENSR1_SPI3ENS_Pos               (15U)
+#define RCC_APB1ENSR1_SPI3ENS_Msk               (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENSR1_SPI3ENS                   RCC_APB1ENSR1_SPI3ENS_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos           (16U)
+#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk           (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENSR1_SPDIFRX1ENS               RCC_APB1ENSR1_SPDIFRX1ENS_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENSR1_USART2ENS_Pos             (17U)
+#define RCC_APB1ENSR1_USART2ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENSR1_USART2ENS                 RCC_APB1ENSR1_USART2ENS_Msk          /*!< USART2 enable */
+#define RCC_APB1ENSR1_USART3ENS_Pos             (18U)
+#define RCC_APB1ENSR1_USART3ENS_Msk             (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENSR1_USART3ENS                 RCC_APB1ENSR1_USART3ENS_Msk          /*!< USART3 enable */
+#define RCC_APB1ENSR1_UART4ENS_Pos              (19U)
+#define RCC_APB1ENSR1_UART4ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENSR1_UART4ENS                  RCC_APB1ENSR1_UART4ENS_Msk           /*!< UART4 enable */
+#define RCC_APB1ENSR1_UART5ENS_Pos              (20U)
+#define RCC_APB1ENSR1_UART5ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENSR1_UART5ENS                  RCC_APB1ENSR1_UART5ENS_Msk           /*!< UART5 enable */
+#define RCC_APB1ENSR1_I2C1ENS_Pos               (21U)
+#define RCC_APB1ENSR1_I2C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENSR1_I2C1ENS                   RCC_APB1ENSR1_I2C1ENS_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENSR1_I2C2ENS_Pos               (22U)
+#define RCC_APB1ENSR1_I2C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENSR1_I2C2ENS                   RCC_APB1ENSR1_I2C2ENS_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENSR1_I2C3ENS_Pos               (23U)
+#define RCC_APB1ENSR1_I2C3ENS_Msk               (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENSR1_I2C3ENS                   RCC_APB1ENSR1_I2C3ENS_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENSR1_I3C1ENS_Pos               (24U)
+#define RCC_APB1ENSR1_I3C1ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENSR1_I3C1ENS                   RCC_APB1ENSR1_I3C1ENS_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENSR1_I3C2ENS_Pos               (25U)
+#define RCC_APB1ENSR1_I3C2ENS_Msk               (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENSR1_I3C2ENS                   RCC_APB1ENSR1_I3C2ENS_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENSR1_UART7ENS_Pos              (30U)
+#define RCC_APB1ENSR1_UART7ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENSR1_UART7ENS                  RCC_APB1ENSR1_UART7ENS_Msk           /*!< UART7 enable */
+#define RCC_APB1ENSR1_UART8ENS_Pos              (31U)
+#define RCC_APB1ENSR1_UART8ENS_Msk              (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENSR1_UART8ENS                  RCC_APB1ENSR1_UART8ENS_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENSR2 register  *****************/
+#define RCC_APB1ENSR2_MDIOSENS_Pos              (5U)
+#define RCC_APB1ENSR2_MDIOSENS_Msk              (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENSR2_MDIOSENS                  RCC_APB1ENSR2_MDIOSENS_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENSR2_FDCANENS_Pos              (8U)
+#define RCC_APB1ENSR2_FDCANENS_Msk              (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENSR2_FDCANENS                  RCC_APB1ENSR2_FDCANENS_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENSR2_UCPD1ENS_Pos              (18U)
+#define RCC_APB1ENSR2_UCPD1ENS_Msk              (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENSR2_UCPD1ENS                  RCC_APB1ENSR2_UCPD1ENS_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENSR register  *****************/
+#define RCC_APB2ENSR_TIM1ENS_Pos                (0U)
+#define RCC_APB2ENSR_TIM1ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENSR_TIM1ENS                    RCC_APB2ENSR_TIM1ENS_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENSR_TIM8ENS_Pos                (1U)
+#define RCC_APB2ENSR_TIM8ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENSR_TIM8ENS                    RCC_APB2ENSR_TIM8ENS_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENSR_USART1ENS_Pos              (4U)
+#define RCC_APB2ENSR_USART1ENS_Msk              (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENSR_USART1ENS                  RCC_APB2ENSR_USART1ENS_Msk           /*!< USART1 enable */
+#define RCC_APB2ENSR_USART6ENS_Pos              (5U)
+#define RCC_APB2ENSR_USART6ENS_Msk              (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENSR_USART6ENS                  RCC_APB2ENSR_USART6ENS_Msk           /*!< USART6 enable */
+#define RCC_APB2ENSR_UART9ENS_Pos               (6U)
+#define RCC_APB2ENSR_UART9ENS_Msk               (0x1UL << RCC_APB2ENSR_UART9ENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENSR_UART9ENS                   RCC_APB2ENSR_UART9ENS_Msk            /*!< UART9 enable */
+#define RCC_APB2ENSR_USART10ENS_Pos             (7U)
+#define RCC_APB2ENSR_USART10ENS_Msk             (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENSR_USART10ENS                 RCC_APB2ENSR_USART10ENS_Msk          /*!< USART10 enable */
+#define RCC_APB2ENSR_SPI1ENS_Pos                (12U)
+#define RCC_APB2ENSR_SPI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENSR_SPI1ENS                    RCC_APB2ENSR_SPI1ENS_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENSR_SPI4ENS_Pos                (13U)
+#define RCC_APB2ENSR_SPI4ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENSR_SPI4ENS                    RCC_APB2ENSR_SPI4ENS_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENSR_TIM18ENS_Pos               (15U)
+#define RCC_APB2ENSR_TIM18ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENSR_TIM18ENS                   RCC_APB2ENSR_TIM18ENS_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENSR_TIM15ENS_Pos               (16U)
+#define RCC_APB2ENSR_TIM15ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENSR_TIM15ENS                   RCC_APB2ENSR_TIM15ENS_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENSR_TIM16ENS_Pos               (17U)
+#define RCC_APB2ENSR_TIM16ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENSR_TIM16ENS                   RCC_APB2ENSR_TIM16ENS_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENSR_TIM17ENS_Pos               (18U)
+#define RCC_APB2ENSR_TIM17ENS_Msk               (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENSR_TIM17ENS                   RCC_APB2ENSR_TIM17ENS_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENSR_TIM9ENS_Pos                (19U)
+#define RCC_APB2ENSR_TIM9ENS_Msk                (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENSR_TIM9ENS                    RCC_APB2ENSR_TIM9ENS_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENSR_SPI5ENS_Pos                (20U)
+#define RCC_APB2ENSR_SPI5ENS_Msk                (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENSR_SPI5ENS                    RCC_APB2ENSR_SPI5ENS_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENSR_SAI1ENS_Pos                (21U)
+#define RCC_APB2ENSR_SAI1ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENSR_SAI1ENS                    RCC_APB2ENSR_SAI1ENS_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENSR_SAI2ENS_Pos                (22U)
+#define RCC_APB2ENSR_SAI2ENS_Msk                (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENSR_SAI2ENS                    RCC_APB2ENSR_SAI2ENS_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENSR register  *****************/
+#define RCC_APB3ENSR_DFTENS_Pos                 (2U)
+#define RCC_APB3ENSR_DFTENS_Msk                 (0x1UL << RCC_APB3ENSR_DFTENS_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENSR_DFTENS                     RCC_APB3ENSR_DFTENS_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENSR1 register  *****************/
+#define RCC_APB4ENSR1_HDPENS_Pos                (2U)
+#define RCC_APB4ENSR1_HDPENS_Msk                (0x1UL << RCC_APB4ENSR1_HDPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR1_HDPENS                    RCC_APB4ENSR1_HDPENS_Msk             /*!< HDP enable */
+#define RCC_APB4ENSR1_LPUART1ENS_Pos            (3U)
+#define RCC_APB4ENSR1_LPUART1ENS_Msk            (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENSR1_LPUART1ENS                RCC_APB4ENSR1_LPUART1ENS_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENSR1_SPI6ENS_Pos               (5U)
+#define RCC_APB4ENSR1_SPI6ENS_Msk               (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENSR1_SPI6ENS                   RCC_APB4ENSR1_SPI6ENS_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENSR1_I2C4ENS_Pos               (7U)
+#define RCC_APB4ENSR1_I2C4ENS_Msk               (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENSR1_I2C4ENS                   RCC_APB4ENSR1_I2C4ENS_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENSR1_LPTIM2ENS_Pos             (9U)
+#define RCC_APB4ENSR1_LPTIM2ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENSR1_LPTIM2ENS                 RCC_APB4ENSR1_LPTIM2ENS_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENSR1_LPTIM3ENS_Pos             (10U)
+#define RCC_APB4ENSR1_LPTIM3ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENSR1_LPTIM3ENS                 RCC_APB4ENSR1_LPTIM3ENS_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENSR1_LPTIM4ENS_Pos             (11U)
+#define RCC_APB4ENSR1_LPTIM4ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENSR1_LPTIM4ENS                 RCC_APB4ENSR1_LPTIM4ENS_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENSR1_LPTIM5ENS_Pos             (12U)
+#define RCC_APB4ENSR1_LPTIM5ENS_Msk             (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENSR1_LPTIM5ENS                 RCC_APB4ENSR1_LPTIM5ENS_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENSR1_VREFBUFENS_Pos            (15U)
+#define RCC_APB4ENSR1_VREFBUFENS_Msk            (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENSR1_VREFBUFENS                RCC_APB4ENSR1_VREFBUFENS_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENSR1_RTCENS_Pos                (16U)
+#define RCC_APB4ENSR1_RTCENS_Msk                (0x1UL << RCC_APB4ENSR1_RTCENS_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENSR1_RTCENS                    RCC_APB4ENSR1_RTCENS_Msk             /*!< RTC enable */
+#define RCC_APB4ENSR1_RTCAPBENS_Pos             (17U)
+#define RCC_APB4ENSR1_RTCAPBENS_Msk             (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENSR1_RTCAPBENS                 RCC_APB4ENSR1_RTCAPBENS_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENSR2 register  *****************/
+#define RCC_APB4ENSR2_SYSCFGENS_Pos             (0U)
+#define RCC_APB4ENSR2_SYSCFGENS_Msk             (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENSR2_SYSCFGENS                 RCC_APB4ENSR2_SYSCFGENS_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENSR2_BSECENS_Pos               (1U)
+#define RCC_APB4ENSR2_BSECENS_Msk               (0x1UL << RCC_APB4ENSR2_BSECENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENSR2_BSECENS                   RCC_APB4ENSR2_BSECENS_Msk            /*!< BSEC enable */
+#define RCC_APB4ENSR2_DTSENS_Pos                (2U)
+#define RCC_APB4ENSR2_DTSENS_Msk                (0x1UL << RCC_APB4ENSR2_DTSENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENSR2_DTSENS                    RCC_APB4ENSR2_DTSENS_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENSR register  *****************/
+#define RCC_APB5ENSR_LTDCENS_Pos                (1U)
+#define RCC_APB5ENSR_LTDCENS_Msk                (0x1UL << RCC_APB5ENSR_LTDCENS_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENSR_LTDCENS                    RCC_APB5ENSR_LTDCENS_Msk             /*!< LTDC enable */
+#define RCC_APB5ENSR_DCMIPPENS_Pos              (2U)
+#define RCC_APB5ENSR_DCMIPPENS_Msk              (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENSR_DCMIPPENS                  RCC_APB5ENSR_DCMIPPENS_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENSR_GFXTIMENS_Pos              (4U)
+#define RCC_APB5ENSR_GFXTIMENS_Msk              (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENSR_GFXTIMENS                  RCC_APB5ENSR_GFXTIMENS_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENSR_VENCENS_Pos                (5U)
+#define RCC_APB5ENSR_VENCENS_Msk                (0x1UL << RCC_APB5ENSR_VENCENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENSR_VENCENS                    RCC_APB5ENSR_VENCENS_Msk             /*!< VENC enable */
+#define RCC_APB5ENSR_CSIENS_Pos                 (6U)
+#define RCC_APB5ENSR_CSIENS_Msk                 (0x1UL << RCC_APB5ENSR_CSIENS_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENSR_CSIENS                     RCC_APB5ENSR_CSIENS_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENSR register  *****************/
+#define RCC_BUSLPENSR_ACLKNLPENS_Pos            (0U)
+#define RCC_BUSLPENSR_ACLKNLPENS_Msk            (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENSR_ACLKNLPENS                RCC_BUSLPENSR_ACLKNLPENS_Msk         /*!< ACLKN enable  */
+#define RCC_BUSLPENSR_ACLKNCLPENS_Pos           (1U)
+#define RCC_BUSLPENSR_ACLKNCLPENS_Msk           (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENSR_ACLKNCLPENS               RCC_BUSLPENSR_ACLKNCLPENS_Msk        /*!< ACLKNC enable  */
+
+/****************  Bit definition for RCC_MISCLPENSR register  ****************/
+#define RCC_MISCLPENSR_DBGLPENS_Pos             (0U)
+#define RCC_MISCLPENSR_DBGLPENS_Msk             (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENSR_DBGLPENS                 RCC_MISCLPENSR_DBGLPENS_Msk          /*!< DBG enable  */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos     (3U)
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk     (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS         RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk  /*!< XSPIPHYCOMP enable  */
+#define RCC_MISCLPENSR_PERLPENS_Pos             (6U)
+#define RCC_MISCLPENSR_PERLPENS_Msk             (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENSR_PERLPENS                 RCC_MISCLPENSR_PERLPENS_Msk          /*!< PER enable  */
+
+/****************  Bit definition for RCC_MEMLPENSR register  *****************/
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos         (0U)
+#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENSR_AXISRAM3LPENS             RCC_MEMLPENSR_AXISRAM3LPENS_Msk      /*!< AXISRAM3 enable  */
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos         (1U)
+#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENSR_AXISRAM4LPENS             RCC_MEMLPENSR_AXISRAM4LPENS_Msk      /*!< AXISRAM4 enable  */
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos         (2U)
+#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENSR_AXISRAM5LPENS             RCC_MEMLPENSR_AXISRAM5LPENS_Msk      /*!< AXISRAM5 enable  */
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos         (3U)
+#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENSR_AXISRAM6LPENS             RCC_MEMLPENSR_AXISRAM6LPENS_Msk      /*!< AXISRAM6 enable  */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos         (4U)
+#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENSR_AHBSRAM1LPENS             RCC_MEMLPENSR_AHBSRAM1LPENS_Msk      /*!< AHBSRAM1 enable  */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos         (5U)
+#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENSR_AHBSRAM2LPENS             RCC_MEMLPENSR_AHBSRAM2LPENS_Msk      /*!< AHBSRAM2 enable  */
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos          (6U)
+#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENSR_BKPSRAMLPENS              RCC_MEMLPENSR_BKPSRAMLPENS_Msk       /*!< BKPSRAM enable  */
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos         (7U)
+#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENSR_AXISRAM1LPENS             RCC_MEMLPENSR_AXISRAM1LPENS_Msk      /*!< AXISRAM1 enable  */
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos         (8U)
+#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk         (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENSR_AXISRAM2LPENS             RCC_MEMLPENSR_AXISRAM2LPENS_Msk      /*!< AXISRAM2 enable  */
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos          (9U)
+#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENSR_FLEXRAMLPENS              RCC_MEMLPENSR_FLEXRAMLPENS_Msk       /*!< FLEXRAM enable  */
+#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos      (10U)
+#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk      (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos)       /*!< 0x00000400 */
+#define RCC_MEMLPENSR_CACHEAXIRAMLPENS          RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk   /*!< CACHEAXIRAM enable  */
+#define RCC_MEMLPENSR_VENCRAMLPENS_Pos          (11U)
+#define RCC_MEMLPENSR_VENCRAMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENSR_VENCRAMLPENS              RCC_MEMLPENSR_VENCRAMLPENS_Msk       /*!< VENCRAM enable  */
+#define RCC_MEMLPENSR_BOOTROMLPENS_Pos          (12U)
+#define RCC_MEMLPENSR_BOOTROMLPENS_Msk          (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENSR_BOOTROMLPENS              RCC_MEMLPENSR_BOOTROMLPENS_Msk       /*!< Boot ROM enable  */
+
+/****************  Bit definition for RCC_AHB1LPENSR register  ****************/
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos          (4U)
+#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk          (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENSR_GPDMA1LPENS              RCC_AHB1LPENSR_GPDMA1LPENS_Msk       /*!< GPDMA1 enable  */
+#define RCC_AHB1LPENSR_ADC12LPENS_Pos           (5U)
+#define RCC_AHB1LPENSR_ADC12LPENS_Msk           (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENSR_ADC12LPENS               RCC_AHB1LPENSR_ADC12LPENS_Msk        /*!< ADC12 enable  */
+
+/****************  Bit definition for RCC_AHB2LPENSR register  ****************/
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos          (12U)
+#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk          (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENSR_RAMCFGLPENS              RCC_AHB2LPENSR_RAMCFGLPENS_Msk       /*!< RAMCFG enable  */
+#define RCC_AHB2LPENSR_MDF1LPENS_Pos            (16U)
+#define RCC_AHB2LPENSR_MDF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENSR_MDF1LPENS                RCC_AHB2LPENSR_MDF1LPENS_Msk         /*!< MDF1 enable  */
+#define RCC_AHB2LPENSR_ADF1LPENS_Pos            (17U)
+#define RCC_AHB2LPENSR_ADF1LPENS_Msk            (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENSR_ADF1LPENS                RCC_AHB2LPENSR_ADF1LPENS_Msk         /*!< ADF1 enable  */
+
+/****************  Bit definition for RCC_AHB3LPENSR register  ****************/
+#define RCC_AHB3LPENSR_RNGLPENS_Pos             (0U)
+#define RCC_AHB3LPENSR_RNGLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENSR_RNGLPENS                 RCC_AHB3LPENSR_RNGLPENS_Msk          /*!< RNG enable  */
+#define RCC_AHB3LPENSR_HASHLPENS_Pos            (1U)
+#define RCC_AHB3LPENSR_HASHLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENSR_HASHLPENS                RCC_AHB3LPENSR_HASHLPENS_Msk         /*!< HASH enable  */
+#define RCC_AHB3LPENSR_CRYPLPENS_Pos            (2U)
+#define RCC_AHB3LPENSR_CRYPLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */
+#define RCC_AHB3LPENSR_CRYPLPENS                RCC_AHB3LPENSR_CRYPLPENS_Msk         /*!< CRYP enable  */
+#define RCC_AHB3LPENSR_SAESLPENS_Pos            (4U)
+#define RCC_AHB3LPENSR_SAESLPENS_Msk            (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */
+#define RCC_AHB3LPENSR_SAESLPENS                RCC_AHB3LPENSR_SAESLPENS_Msk         /*!< SAES enable  */
+#define RCC_AHB3LPENSR_PKALPENS_Pos             (8U)
+#define RCC_AHB3LPENSR_PKALPENS_Msk             (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENSR_PKALPENS                 RCC_AHB3LPENSR_PKALPENS_Msk          /*!< PKA enable  */
+#define RCC_AHB3LPENSR_RIFSCLPENS_Pos           (9U)
+#define RCC_AHB3LPENSR_RIFSCLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENSR_RIFSCLPENS               RCC_AHB3LPENSR_RIFSCLPENS_Msk        /*!< RIFSC enable  */
+#define RCC_AHB3LPENSR_IACLPENS_Pos             (10U)
+#define RCC_AHB3LPENSR_IACLPENS_Msk             (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENSR_IACLPENS                 RCC_AHB3LPENSR_IACLPENS_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENSR_RISAFLPENS_Pos           (14U)
+#define RCC_AHB3LPENSR_RISAFLPENS_Msk           (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENSR_RISAFLPENS               RCC_AHB3LPENSR_RISAFLPENS_Msk        /*!< RISAF enable  */
+
+/****************  Bit definition for RCC_AHB4LPENSR register  ****************/
+#define RCC_AHB4LPENSR_GPIOALPENS_Pos           (0U)
+#define RCC_AHB4LPENSR_GPIOALPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENSR_GPIOALPENS               RCC_AHB4LPENSR_GPIOALPENS_Msk        /*!< GPIO A enable  */
+#define RCC_AHB4LPENSR_GPIOBLPENS_Pos           (1U)
+#define RCC_AHB4LPENSR_GPIOBLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENSR_GPIOBLPENS               RCC_AHB4LPENSR_GPIOBLPENS_Msk        /*!< GPIO B enable  */
+#define RCC_AHB4LPENSR_GPIOCLPENS_Pos           (2U)
+#define RCC_AHB4LPENSR_GPIOCLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENSR_GPIOCLPENS               RCC_AHB4LPENSR_GPIOCLPENS_Msk        /*!< GPIO C enable  */
+#define RCC_AHB4LPENSR_GPIODLPENS_Pos           (3U)
+#define RCC_AHB4LPENSR_GPIODLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENSR_GPIODLPENS               RCC_AHB4LPENSR_GPIODLPENS_Msk        /*!< GPIO D enable  */
+#define RCC_AHB4LPENSR_GPIOELPENS_Pos           (4U)
+#define RCC_AHB4LPENSR_GPIOELPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENSR_GPIOELPENS               RCC_AHB4LPENSR_GPIOELPENS_Msk        /*!< GPIO E enable  */
+#define RCC_AHB4LPENSR_GPIOFLPENS_Pos           (5U)
+#define RCC_AHB4LPENSR_GPIOFLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENSR_GPIOFLPENS               RCC_AHB4LPENSR_GPIOFLPENS_Msk        /*!< GPIO F enable  */
+#define RCC_AHB4LPENSR_GPIOGLPENS_Pos           (6U)
+#define RCC_AHB4LPENSR_GPIOGLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENSR_GPIOGLPENS               RCC_AHB4LPENSR_GPIOGLPENS_Msk        /*!< GPIO G enable  */
+#define RCC_AHB4LPENSR_GPIOHLPENS_Pos           (7U)
+#define RCC_AHB4LPENSR_GPIOHLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENSR_GPIOHLPENS               RCC_AHB4LPENSR_GPIOHLPENS_Msk        /*!< GPIO H enable  */
+#define RCC_AHB4LPENSR_GPIONLPENS_Pos           (13U)
+#define RCC_AHB4LPENSR_GPIONLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENSR_GPIONLPENS               RCC_AHB4LPENSR_GPIONLPENS_Msk        /*!< GPIO N enable  */
+#define RCC_AHB4LPENSR_GPIOOLPENS_Pos           (14U)
+#define RCC_AHB4LPENSR_GPIOOLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENSR_GPIOOLPENS               RCC_AHB4LPENSR_GPIOOLPENS_Msk        /*!< GPIO O enable  */
+#define RCC_AHB4LPENSR_GPIOPLPENS_Pos           (15U)
+#define RCC_AHB4LPENSR_GPIOPLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENSR_GPIOPLPENS               RCC_AHB4LPENSR_GPIOPLPENS_Msk        /*!< GPIO P enable  */
+#define RCC_AHB4LPENSR_GPIOQLPENS_Pos           (16U)
+#define RCC_AHB4LPENSR_GPIOQLPENS_Msk           (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENSR_GPIOQLPENS               RCC_AHB4LPENSR_GPIOQLPENS_Msk        /*!< GPIO Q enable  */
+#define RCC_AHB4LPENSR_PWRLPENS_Pos             (18U)
+#define RCC_AHB4LPENSR_PWRLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENSR_PWRLPENS                 RCC_AHB4LPENSR_PWRLPENS_Msk          /*!< PWR enable  */
+#define RCC_AHB4LPENSR_CRCLPENS_Pos             (19U)
+#define RCC_AHB4LPENSR_CRCLPENS_Msk             (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENSR_CRCLPENS                 RCC_AHB4LPENSR_CRCLPENS_Msk          /*!< CRC enable  */
+
+/****************  Bit definition for RCC_AHB5LPENSR register  ****************/
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos          (0U)
+#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENSR_HPDMA1LPENS              RCC_AHB5LPENSR_HPDMA1LPENS_Msk       /*!< HPDMA1 enable  */
+#define RCC_AHB5LPENSR_DMA2DLPENS_Pos           (1U)
+#define RCC_AHB5LPENSR_DMA2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENSR_DMA2DLPENS               RCC_AHB5LPENSR_DMA2DLPENS_Msk        /*!< DMA2D enable  */
+#define RCC_AHB5LPENSR_JPEGLPENS_Pos            (3U)
+#define RCC_AHB5LPENSR_JPEGLPENS_Msk            (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENSR_JPEGLPENS                RCC_AHB5LPENSR_JPEGLPENS_Msk         /*!< JPEG enable  */
+#define RCC_AHB5LPENSR_FMCLPENS_Pos             (4U)
+#define RCC_AHB5LPENSR_FMCLPENS_Msk             (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENSR_FMCLPENS                 RCC_AHB5LPENSR_FMCLPENS_Msk          /*!< FMC enable  */
+#define RCC_AHB5LPENSR_XSPI1LPENS_Pos           (5U)
+#define RCC_AHB5LPENSR_XSPI1LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENSR_XSPI1LPENS               RCC_AHB5LPENSR_XSPI1LPENS_Msk        /*!< XSPI1 enable  */
+#define RCC_AHB5LPENSR_PSSILPENS_Pos            (6U)
+#define RCC_AHB5LPENSR_PSSILPENS_Msk            (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENSR_PSSILPENS                RCC_AHB5LPENSR_PSSILPENS_Msk         /*!< PSSI enable  */
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos          (7U)
+#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENSR_SDMMC2LPENS              RCC_AHB5LPENSR_SDMMC2LPENS_Msk       /*!< SDMMC2 enable  */
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos          (8U)
+#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk          (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENSR_SDMMC1LPENS              RCC_AHB5LPENSR_SDMMC1LPENS_Msk       /*!< SDMMC1 enable  */
+#define RCC_AHB5LPENSR_XSPI2LPENS_Pos           (12U)
+#define RCC_AHB5LPENSR_XSPI2LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENSR_XSPI2LPENS               RCC_AHB5LPENSR_XSPI2LPENS_Msk        /*!< XSPI2 enable  */
+#define RCC_AHB5LPENSR_XSPIMLPENS_Pos           (13U)
+#define RCC_AHB5LPENSR_XSPIMLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENSR_XSPIMLPENS               RCC_AHB5LPENSR_XSPIMLPENS_Msk        /*!< XSPIM enable  */
+#define RCC_AHB5LPENSR_MCE1LPENS_Pos            (14U)
+#define RCC_AHB5LPENSR_MCE1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */
+#define RCC_AHB5LPENSR_MCE1LPENS                RCC_AHB5LPENSR_MCE1LPENS_Msk         /*!< MCE1 enable  */
+#define RCC_AHB5LPENSR_MCE2LPENS_Pos            (15U)
+#define RCC_AHB5LPENSR_MCE2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */
+#define RCC_AHB5LPENSR_MCE2LPENS                RCC_AHB5LPENSR_MCE2LPENS_Msk         /*!< MCE2 enable  */
+#define RCC_AHB5LPENSR_MCE3LPENS_Pos            (16U)
+#define RCC_AHB5LPENSR_MCE3LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */
+#define RCC_AHB5LPENSR_MCE3LPENS                RCC_AHB5LPENSR_MCE3LPENS_Msk         /*!< MCE3 enable  */
+#define RCC_AHB5LPENSR_XSPI3LPENS_Pos           (17U)
+#define RCC_AHB5LPENSR_XSPI3LPENS_Msk           (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENSR_XSPI3LPENS               RCC_AHB5LPENSR_XSPI3LPENS_Msk        /*!< XSPI3 enable  */
+#define RCC_AHB5LPENSR_MCE4LPENS_Pos            (18U)
+#define RCC_AHB5LPENSR_MCE4LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */
+#define RCC_AHB5LPENSR_MCE4LPENS                RCC_AHB5LPENSR_MCE4LPENS_Msk         /*!< MCE4 enable  */
+#define RCC_AHB5LPENSR_GFXMMULPENS_Pos          (19U)
+#define RCC_AHB5LPENSR_GFXMMULPENS_Msk          (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENSR_GFXMMULPENS              RCC_AHB5LPENSR_GFXMMULPENS_Msk       /*!< GFXMMU enable  */
+#define RCC_AHB5LPENSR_GPU2DLPENS_Pos           (20U)
+#define RCC_AHB5LPENSR_GPU2DLPENS_Msk           (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENSR_GPU2DLPENS               RCC_AHB5LPENSR_GPU2DLPENS_Msk        /*!< GPU2D enable */
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos         (22U)
+#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk         (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENSR_ETH1MACLPENS             RCC_AHB5LPENSR_ETH1MACLPENS_Msk      /*!< ETH1MAC enable  */
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos          (23U)
+#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENSR_ETH1TXLPENS              RCC_AHB5LPENSR_ETH1TXLPENS_Msk       /*!< ETH1TX enable  */
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos          (24U)
+#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk          (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENSR_ETH1RXLPENS              RCC_AHB5LPENSR_ETH1RXLPENS_Msk       /*!< ETH1RX enable  */
+#define RCC_AHB5LPENSR_ETH1LPENS_Pos            (25U)
+#define RCC_AHB5LPENSR_ETH1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENSR_ETH1LPENS                RCC_AHB5LPENSR_ETH1LPENS_Msk         /*!< ETH1 enable  */
+#define RCC_AHB5LPENSR_OTG1LPENS_Pos            (26U)
+#define RCC_AHB5LPENSR_OTG1LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENSR_OTG1LPENS                RCC_AHB5LPENSR_OTG1LPENS_Msk         /*!< OTG1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos         (27U)
+#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENSR_OTGPHY1LPENS             RCC_AHB5LPENSR_OTGPHY1LPENS_Msk      /*!< OTGPHY1 enable  */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos         (28U)
+#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk         (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENSR_OTGPHY2LPENS             RCC_AHB5LPENSR_OTGPHY2LPENS_Msk      /*!< OTGPHY2 enable  */
+#define RCC_AHB5LPENSR_OTG2LPENS_Pos            (29U)
+#define RCC_AHB5LPENSR_OTG2LPENS_Msk            (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENSR_OTG2LPENS                RCC_AHB5LPENSR_OTG2LPENS_Msk         /*!< OTG2 enable  */
+#define RCC_AHB5LPENSR_CACHEAXILPENS_Pos        (30U)
+#define RCC_AHB5LPENSR_CACHEAXILPENS_Msk        (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos)     /*!< 0x40000000 */
+#define RCC_AHB5LPENSR_CACHEAXILPENS            RCC_AHB5LPENSR_CACHEAXILPENS_Msk     /*!< CACHEAXI enable  */
+#define RCC_AHB5LPENSR_NPULPENS_Pos             (31U)
+#define RCC_AHB5LPENSR_NPULPENS_Msk             (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */
+#define RCC_AHB5LPENSR_NPULPENS                 RCC_AHB5LPENSR_NPULPENS_Msk          /*!< NPU enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR1 register  ****************/
+#define RCC_APB1LPENSR1_TIM2LPENS_Pos           (0U)
+#define RCC_APB1LPENSR1_TIM2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENSR1_TIM2LPENS               RCC_APB1LPENSR1_TIM2LPENS_Msk        /*!< TIM2 enable  */
+#define RCC_APB1LPENSR1_TIM3LPENS_Pos           (1U)
+#define RCC_APB1LPENSR1_TIM3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENSR1_TIM3LPENS               RCC_APB1LPENSR1_TIM3LPENS_Msk        /*!< TIM3 enable  */
+#define RCC_APB1LPENSR1_TIM4LPENS_Pos           (2U)
+#define RCC_APB1LPENSR1_TIM4LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENSR1_TIM4LPENS               RCC_APB1LPENSR1_TIM4LPENS_Msk        /*!< TIM4 enable  */
+#define RCC_APB1LPENSR1_TIM5LPENS_Pos           (3U)
+#define RCC_APB1LPENSR1_TIM5LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENSR1_TIM5LPENS               RCC_APB1LPENSR1_TIM5LPENS_Msk        /*!< TIM5 enable  */
+#define RCC_APB1LPENSR1_TIM6LPENS_Pos           (4U)
+#define RCC_APB1LPENSR1_TIM6LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENSR1_TIM6LPENS               RCC_APB1LPENSR1_TIM6LPENS_Msk        /*!< TIM6 enable  */
+#define RCC_APB1LPENSR1_TIM7LPENS_Pos           (5U)
+#define RCC_APB1LPENSR1_TIM7LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENSR1_TIM7LPENS               RCC_APB1LPENSR1_TIM7LPENS_Msk        /*!< TIM7 enable  */
+#define RCC_APB1LPENSR1_TIM12LPENS_Pos          (6U)
+#define RCC_APB1LPENSR1_TIM12LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENSR1_TIM12LPENS              RCC_APB1LPENSR1_TIM12LPENS_Msk       /*!< TIM12 enable  */
+#define RCC_APB1LPENSR1_TIM13LPENS_Pos          (7U)
+#define RCC_APB1LPENSR1_TIM13LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENSR1_TIM13LPENS              RCC_APB1LPENSR1_TIM13LPENS_Msk       /*!< TIM13 enable  */
+#define RCC_APB1LPENSR1_TIM14LPENS_Pos          (8U)
+#define RCC_APB1LPENSR1_TIM14LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR1_TIM14LPENS              RCC_APB1LPENSR1_TIM14LPENS_Msk       /*!< TIM14 enable  */
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos         (9U)
+#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENSR1_LPTIM1LPENS             RCC_APB1LPENSR1_LPTIM1LPENS_Msk      /*!< LPTIM1 enable  */
+#define RCC_APB1LPENSR1_WWDGLPENS_Pos           (11U)
+#define RCC_APB1LPENSR1_WWDGLPENS_Msk           (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENSR1_WWDGLPENS               RCC_APB1LPENSR1_WWDGLPENS_Msk        /*!< WWDG enable  */
+#define RCC_APB1LPENSR1_TIM10LPENS_Pos          (12U)
+#define RCC_APB1LPENSR1_TIM10LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENSR1_TIM10LPENS              RCC_APB1LPENSR1_TIM10LPENS_Msk       /*!< TIM10 enable  */
+#define RCC_APB1LPENSR1_TIM11LPENS_Pos          (13U)
+#define RCC_APB1LPENSR1_TIM11LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENSR1_TIM11LPENS              RCC_APB1LPENSR1_TIM11LPENS_Msk       /*!< TIM11 enable  */
+#define RCC_APB1LPENSR1_SPI2LPENS_Pos           (14U)
+#define RCC_APB1LPENSR1_SPI2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENSR1_SPI2LPENS               RCC_APB1LPENSR1_SPI2LPENS_Msk        /*!< SPI2 enable  */
+#define RCC_APB1LPENSR1_SPI3LPENS_Pos           (15U)
+#define RCC_APB1LPENSR1_SPI3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENSR1_SPI3LPENS               RCC_APB1LPENSR1_SPI3LPENS_Msk        /*!< SPI3 enable  */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos       (16U)
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk       (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENSR1_SPDIFRX1LPENS           RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk    /*!< SPDIFRX1 enable  */
+#define RCC_APB1LPENSR1_USART2LPENS_Pos         (17U)
+#define RCC_APB1LPENSR1_USART2LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENSR1_USART2LPENS             RCC_APB1LPENSR1_USART2LPENS_Msk      /*!< USART2 enable  */
+#define RCC_APB1LPENSR1_USART3LPENS_Pos         (18U)
+#define RCC_APB1LPENSR1_USART3LPENS_Msk         (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENSR1_USART3LPENS             RCC_APB1LPENSR1_USART3LPENS_Msk      /*!< USART3 enable  */
+#define RCC_APB1LPENSR1_UART4LPENS_Pos          (19U)
+#define RCC_APB1LPENSR1_UART4LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENSR1_UART4LPENS              RCC_APB1LPENSR1_UART4LPENS_Msk       /*!< UART4 enable  */
+#define RCC_APB1LPENSR1_UART5LPENS_Pos          (20U)
+#define RCC_APB1LPENSR1_UART5LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENSR1_UART5LPENS              RCC_APB1LPENSR1_UART5LPENS_Msk       /*!< UART5 enable  */
+#define RCC_APB1LPENSR1_I2C1LPENS_Pos           (21U)
+#define RCC_APB1LPENSR1_I2C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENSR1_I2C1LPENS               RCC_APB1LPENSR1_I2C1LPENS_Msk        /*!< I2C1 enable  */
+#define RCC_APB1LPENSR1_I2C2LPENS_Pos           (22U)
+#define RCC_APB1LPENSR1_I2C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENSR1_I2C2LPENS               RCC_APB1LPENSR1_I2C2LPENS_Msk        /*!< I2C2 enable  */
+#define RCC_APB1LPENSR1_I2C3LPENS_Pos           (23U)
+#define RCC_APB1LPENSR1_I2C3LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENSR1_I2C3LPENS               RCC_APB1LPENSR1_I2C3LPENS_Msk        /*!< I2C3 enable  */
+#define RCC_APB1LPENSR1_I3C1LPENS_Pos           (24U)
+#define RCC_APB1LPENSR1_I3C1LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENSR1_I3C1LPENS               RCC_APB1LPENSR1_I3C1LPENS_Msk        /*!< I3C1 enable  */
+#define RCC_APB1LPENSR1_I3C2LPENS_Pos           (25U)
+#define RCC_APB1LPENSR1_I3C2LPENS_Msk           (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENSR1_I3C2LPENS               RCC_APB1LPENSR1_I3C2LPENS_Msk        /*!< I3C2 enable  */
+#define RCC_APB1LPENSR1_UART7LPENS_Pos          (30U)
+#define RCC_APB1LPENSR1_UART7LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENSR1_UART7LPENS              RCC_APB1LPENSR1_UART7LPENS_Msk       /*!< UART7 enable  */
+#define RCC_APB1LPENSR1_UART8LPENS_Pos          (31U)
+#define RCC_APB1LPENSR1_UART8LPENS_Msk          (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENSR1_UART8LPENS              RCC_APB1LPENSR1_UART8LPENS_Msk       /*!< UART8 enable  */
+
+/***************  Bit definition for RCC_APB1LPENSR2 register  ****************/
+#define RCC_APB1LPENSR2_MDIOSLPENS_Pos          (5U)
+#define RCC_APB1LPENSR2_MDIOSLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENSR2_MDIOSLPENS              RCC_APB1LPENSR2_MDIOSLPENS_Msk       /*!< MDIOS enable  */
+#define RCC_APB1LPENSR2_FDCANLPENS_Pos          (8U)
+#define RCC_APB1LPENSR2_FDCANLPENS_Msk          (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENSR2_FDCANLPENS              RCC_APB1LPENSR2_FDCANLPENS_Msk       /*!< FDCAN enable  */
+#define RCC_APB1LPENSR2_UCPD1LPENS_Pos          (18U)
+#define RCC_APB1LPENSR2_UCPD1LPENS_Msk          (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENSR2_UCPD1LPENS              RCC_APB1LPENSR2_UCPD1LPENS_Msk       /*!< UCPD1 enable  */
+
+/****************  Bit definition for RCC_APB2LPENSR register  ****************/
+#define RCC_APB2LPENSR_TIM1LPENS_Pos            (0U)
+#define RCC_APB2LPENSR_TIM1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENSR_TIM1LPENS                RCC_APB2LPENSR_TIM1LPENS_Msk         /*!< TIM1 enable  */
+#define RCC_APB2LPENSR_TIM8LPENS_Pos            (1U)
+#define RCC_APB2LPENSR_TIM8LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENSR_TIM8LPENS                RCC_APB2LPENSR_TIM8LPENS_Msk         /*!< TIM8 enable  */
+#define RCC_APB2LPENSR_USART1LPENS_Pos          (4U)
+#define RCC_APB2LPENSR_USART1LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENSR_USART1LPENS              RCC_APB2LPENSR_USART1LPENS_Msk       /*!< USART1 enable  */
+#define RCC_APB2LPENSR_USART6LPENS_Pos          (5U)
+#define RCC_APB2LPENSR_USART6LPENS_Msk          (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENSR_USART6LPENS              RCC_APB2LPENSR_USART6LPENS_Msk       /*!< USART6 enable  */
+#define RCC_APB2LPENSR_UART9LPENS_Pos           (6U)
+#define RCC_APB2LPENSR_UART9LPENS_Msk           (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENSR_UART9LPENS               RCC_APB2LPENSR_UART9LPENS_Msk        /*!< UART9 enable  */
+#define RCC_APB2LPENSR_USART10LPENS_Pos         (7U)
+#define RCC_APB2LPENSR_USART10LPENS_Msk         (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENSR_USART10LPENS             RCC_APB2LPENSR_USART10LPENS_Msk      /*!< USART10 enable  */
+#define RCC_APB2LPENSR_SPI1LPENS_Pos            (12U)
+#define RCC_APB2LPENSR_SPI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENSR_SPI1LPENS                RCC_APB2LPENSR_SPI1LPENS_Msk         /*!< SPI1 enable  */
+#define RCC_APB2LPENSR_SPI4LPENS_Pos            (13U)
+#define RCC_APB2LPENSR_SPI4LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENSR_SPI4LPENS                RCC_APB2LPENSR_SPI4LPENS_Msk         /*!< SPI4 enable  */
+#define RCC_APB2LPENSR_TIM18LPENS_Pos           (15U)
+#define RCC_APB2LPENSR_TIM18LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENSR_TIM18LPENS               RCC_APB2LPENSR_TIM18LPENS_Msk        /*!< TIM18 enable  */
+#define RCC_APB2LPENSR_TIM15LPENS_Pos           (16U)
+#define RCC_APB2LPENSR_TIM15LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENSR_TIM15LPENS               RCC_APB2LPENSR_TIM15LPENS_Msk        /*!< TIM15 enable  */
+#define RCC_APB2LPENSR_TIM16LPENS_Pos           (17U)
+#define RCC_APB2LPENSR_TIM16LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENSR_TIM16LPENS               RCC_APB2LPENSR_TIM16LPENS_Msk        /*!< TIM16 enable  */
+#define RCC_APB2LPENSR_TIM17LPENS_Pos           (18U)
+#define RCC_APB2LPENSR_TIM17LPENS_Msk           (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENSR_TIM17LPENS               RCC_APB2LPENSR_TIM17LPENS_Msk        /*!< TIM17 enable  */
+#define RCC_APB2LPENSR_TIM9LPENS_Pos            (19U)
+#define RCC_APB2LPENSR_TIM9LPENS_Msk            (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENSR_TIM9LPENS                RCC_APB2LPENSR_TIM9LPENS_Msk         /*!< TIM9 enable  */
+#define RCC_APB2LPENSR_SPI5LPENS_Pos            (20U)
+#define RCC_APB2LPENSR_SPI5LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENSR_SPI5LPENS                RCC_APB2LPENSR_SPI5LPENS_Msk         /*!< SPI5 enable  */
+#define RCC_APB2LPENSR_SAI1LPENS_Pos            (21U)
+#define RCC_APB2LPENSR_SAI1LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENSR_SAI1LPENS                RCC_APB2LPENSR_SAI1LPENS_Msk         /*!< SAI1 enable  */
+#define RCC_APB2LPENSR_SAI2LPENS_Pos            (22U)
+#define RCC_APB2LPENSR_SAI2LPENS_Msk            (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENSR_SAI2LPENS                RCC_APB2LPENSR_SAI2LPENS_Msk         /*!< SAI2 enable  */
+
+/****************  Bit definition for RCC_APB3LPENSR register  ****************/
+#define RCC_APB3LPENSR_DFTLPENS_Pos             (2U)
+#define RCC_APB3LPENSR_DFTLPENS_Msk             (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENSR_DFTLPENS                 RCC_APB3LPENSR_DFTLPENS_Msk          /*!< DFT enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR1 register  ****************/
+#define RCC_APB4LPENSR1_HDPLPENS_Pos            (2U)
+#define RCC_APB4LPENSR1_HDPLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR1_HDPLPENS                RCC_APB4LPENSR1_HDPLPENS_Msk         /*!< HDP enable  */
+#define RCC_APB4LPENSR1_LPUART1LPENS_Pos        (3U)
+#define RCC_APB4LPENSR1_LPUART1LPENS_Msk        (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENSR1_LPUART1LPENS            RCC_APB4LPENSR1_LPUART1LPENS_Msk     /*!< LPUART1 enable  */
+#define RCC_APB4LPENSR1_SPI6LPENS_Pos           (5U)
+#define RCC_APB4LPENSR1_SPI6LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENSR1_SPI6LPENS               RCC_APB4LPENSR1_SPI6LPENS_Msk        /*!< SPI6 enable  */
+#define RCC_APB4LPENSR1_I2C4LPENS_Pos           (7U)
+#define RCC_APB4LPENSR1_I2C4LPENS_Msk           (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENSR1_I2C4LPENS               RCC_APB4LPENSR1_I2C4LPENS_Msk        /*!< I2C4 enable  */
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos         (9U)
+#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENSR1_LPTIM2LPENS             RCC_APB4LPENSR1_LPTIM2LPENS_Msk      /*!< LPTIM2 enable  */
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos         (10U)
+#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENSR1_LPTIM3LPENS             RCC_APB4LPENSR1_LPTIM3LPENS_Msk      /*!< LPTIM3 enable  */
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos         (11U)
+#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENSR1_LPTIM4LPENS             RCC_APB4LPENSR1_LPTIM4LPENS_Msk      /*!< LPTIM4 enable  */
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos         (12U)
+#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk         (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENSR1_LPTIM5LPENS             RCC_APB4LPENSR1_LPTIM5LPENS_Msk      /*!< LPTIM5 enable  */
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos        (15U)
+#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk        (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENSR1_VREFBUFLPENS            RCC_APB4LPENSR1_VREFBUFLPENS_Msk     /*!< VREFBUF enable  */
+#define RCC_APB4LPENSR1_RTCLPENS_Pos            (16U)
+#define RCC_APB4LPENSR1_RTCLPENS_Msk            (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENSR1_RTCLPENS                RCC_APB4LPENSR1_RTCLPENS_Msk         /*!< RTC enable  */
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos         (17U)
+#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk         (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENSR1_RTCAPBLPENS             RCC_APB4LPENSR1_RTCAPBLPENS_Msk      /*!< RTCAPB enable  */
+
+/***************  Bit definition for RCC_APB4LPENSR2 register  ****************/
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos         (0U)
+#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk         (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENSR2_SYSCFGLPENS             RCC_APB4LPENSR2_SYSCFGLPENS_Msk      /*!< SYSCFG enable  */
+#define RCC_APB4LPENSR2_BSECLPENS_Pos           (1U)
+#define RCC_APB4LPENSR2_BSECLPENS_Msk           (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENSR2_BSECLPENS               RCC_APB4LPENSR2_BSECLPENS_Msk        /*!< BSEC enable  */
+#define RCC_APB4LPENSR2_DTSLPENS_Pos            (2U)
+#define RCC_APB4LPENSR2_DTSLPENS_Msk            (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENSR2_DTSLPENS                RCC_APB4LPENSR2_DTSLPENS_Msk         /*!< DTS enable  */
+
+/****************  Bit definition for RCC_APB5LPENSR register  ****************/
+#define RCC_APB5LPENSR_LTDCLPENS_Pos            (1U)
+#define RCC_APB5LPENSR_LTDCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENSR_LTDCLPENS                RCC_APB5LPENSR_LTDCLPENS_Msk         /*!< LTDC enable */
+#define RCC_APB5LPENSR_DCMIPPLPENS_Pos          (2U)
+#define RCC_APB5LPENSR_DCMIPPLPENS_Msk          (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENSR_DCMIPPLPENS              RCC_APB5LPENSR_DCMIPPLPENS_Msk       /*!< DCMIPP enable */
+#define RCC_APB5LPENSR_GFXTIMLPENS_Pos          (4U)
+#define RCC_APB5LPENSR_GFXTIMLPENS_Msk          (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENSR_GFXTIMLPENS              RCC_APB5LPENSR_GFXTIMLPENS_Msk       /*!< GFXTIM enable */
+#define RCC_APB5LPENSR_VENCLPENS_Pos            (5U)
+#define RCC_APB5LPENSR_VENCLPENS_Msk            (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENSR_VENCLPENS                RCC_APB5LPENSR_VENCLPENS_Msk         /*!< VENC enable */
+#define RCC_APB5LPENSR_CSILPENS_Pos             (6U)
+#define RCC_APB5LPENSR_CSILPENS_Msk             (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENSR_CSILPENS                 RCC_APB5LPENSR_CSILPENS_Msk          /*!< CSI enable */
+
+/****************  Bit definition for RCC_PRIVCFGSR0 register  ****************/
+#define RCC_PRIVCFGSR0_LSIPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR0_LSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR0_LSIPRIVS                 RCC_PRIVCFGSR0_LSIPRIVS_Msk          /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_LSEPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR0_LSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR0_LSEPRIVS                 RCC_PRIVCFGSR0_LSEPRIVS_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_MSIPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR0_MSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR0_MSIPRIVS                 RCC_PRIVCFGSR0_MSIPRIVS_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSIPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR0_HSIPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR0_HSIPRIVS                 RCC_PRIVCFGSR0_HSIPRIVS_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR0_HSEPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR0_HSEPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR0_HSEPRIVS                 RCC_PRIVCFGSR0_HSEPRIVS_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR0 register  *****************/
+#define RCC_PUBCFGSR0_LSIPUBS_Pos               (0U)
+#define RCC_PUBCFGSR0_LSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR0_LSIPUBS                   RCC_PUBCFGSR0_LSIPUBS_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_LSEPUBS_Pos               (1U)
+#define RCC_PUBCFGSR0_LSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR0_LSEPUBS                   RCC_PUBCFGSR0_LSEPUBS_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_MSIPUBS_Pos               (2U)
+#define RCC_PUBCFGSR0_MSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR0_MSIPUBS                   RCC_PUBCFGSR0_MSIPUBS_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSIPUBS_Pos               (3U)
+#define RCC_PUBCFGSR0_HSIPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR0_HSIPUBS                   RCC_PUBCFGSR0_HSIPUBS_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR0_HSEPUBS_Pos               (4U)
+#define RCC_PUBCFGSR0_HSEPUBS_Msk               (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR0_HSEPUBS                   RCC_PUBCFGSR0_HSEPUBS_Msk            /*!< Public protection of he HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR1 register  ****************/
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos            (0U)
+#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGSR1_PLL1PRIVS                RCC_PRIVCFGSR1_PLL1PRIVS_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos            (1U)
+#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGSR1_PLL2PRIVS                RCC_PRIVCFGSR1_PLL2PRIVS_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR1_PLL3PRIVS                RCC_PRIVCFGSR1_PLL3PRIVS_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR1_PLL4PRIVS                RCC_PRIVCFGSR1_PLL4PRIVS_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR1 register  *****************/
+#define RCC_PUBCFGSR1_PLL1PUBS_Pos              (0U)
+#define RCC_PUBCFGSR1_PLL1PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGSR1_PLL1PUBS                  RCC_PUBCFGSR1_PLL1PUBS_Msk           /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL2PUBS_Pos              (1U)
+#define RCC_PUBCFGSR1_PLL2PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR1_PLL2PUBS                  RCC_PUBCFGSR1_PLL2PUBS_Msk           /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL3PUBS_Pos              (2U)
+#define RCC_PUBCFGSR1_PLL3PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR1_PLL3PUBS                  RCC_PUBCFGSR1_PLL3PUBS_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR1_PLL4PUBS_Pos              (3U)
+#define RCC_PUBCFGSR1_PLL4PUBS_Msk              (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR1_PLL4PUBS                  RCC_PUBCFGSR1_PLL4PUBS_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR2 register  ****************/
+#define RCC_PRIVCFGSR2_IC1PRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR2_IC1PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR2_IC1PRIVS                 RCC_PRIVCFGSR2_IC1PRIVS_Msk          /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC2PRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR2_IC2PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR2_IC2PRIVS                 RCC_PRIVCFGSR2_IC2PRIVS_Msk          /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC3PRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR2_IC3PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR2_IC3PRIVS                 RCC_PRIVCFGSR2_IC3PRIVS_Msk          /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC4PRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR2_IC4PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR2_IC4PRIVS                 RCC_PRIVCFGSR2_IC4PRIVS_Msk          /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC5PRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR2_IC5PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR2_IC5PRIVS                 RCC_PRIVCFGSR2_IC5PRIVS_Msk          /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC6PRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR2_IC6PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR2_IC6PRIVS                 RCC_PRIVCFGSR2_IC6PRIVS_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC7PRIVS_Pos             (6U)
+#define RCC_PRIVCFGSR2_IC7PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGSR2_IC7PRIVS                 RCC_PRIVCFGSR2_IC7PRIVS_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC8PRIVS_Pos             (7U)
+#define RCC_PRIVCFGSR2_IC8PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGSR2_IC8PRIVS                 RCC_PRIVCFGSR2_IC8PRIVS_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC9PRIVS_Pos             (8U)
+#define RCC_PRIVCFGSR2_IC9PRIVS_Msk             (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGSR2_IC9PRIVS                 RCC_PRIVCFGSR2_IC9PRIVS_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC10PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR2_IC10PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR2_IC10PRIVS                RCC_PRIVCFGSR2_IC10PRIVS_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC11PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR2_IC11PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR2_IC11PRIVS                RCC_PRIVCFGSR2_IC11PRIVS_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC12PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR2_IC12PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR2_IC12PRIVS                RCC_PRIVCFGSR2_IC12PRIVS_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC13PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR2_IC13PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR2_IC13PRIVS                RCC_PRIVCFGSR2_IC13PRIVS_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC14PRIVS_Pos            (13U)
+#define RCC_PRIVCFGSR2_IC14PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGSR2_IC14PRIVS                RCC_PRIVCFGSR2_IC14PRIVS_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC15PRIVS_Pos            (14U)
+#define RCC_PRIVCFGSR2_IC15PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGSR2_IC15PRIVS                RCC_PRIVCFGSR2_IC15PRIVS_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC16PRIVS_Pos            (15U)
+#define RCC_PRIVCFGSR2_IC16PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGSR2_IC16PRIVS                RCC_PRIVCFGSR2_IC16PRIVS_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC17PRIVS_Pos            (16U)
+#define RCC_PRIVCFGSR2_IC17PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGSR2_IC17PRIVS                RCC_PRIVCFGSR2_IC17PRIVS_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC18PRIVS_Pos            (17U)
+#define RCC_PRIVCFGSR2_IC18PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGSR2_IC18PRIVS                RCC_PRIVCFGSR2_IC18PRIVS_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC19PRIVS_Pos            (18U)
+#define RCC_PRIVCFGSR2_IC19PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGSR2_IC19PRIVS                RCC_PRIVCFGSR2_IC19PRIVS_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR2_IC20PRIVS_Pos            (19U)
+#define RCC_PRIVCFGSR2_IC20PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGSR2_IC20PRIVS                RCC_PRIVCFGSR2_IC20PRIVS_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR2 register  *****************/
+#define RCC_PUBCFGSR2_IC1PUBS_Pos               (0U)
+#define RCC_PUBCFGSR2_IC1PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR2_IC1PUBS                   RCC_PUBCFGSR2_IC1PUBS_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC2PUBS_Pos               (1U)
+#define RCC_PUBCFGSR2_IC2PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR2_IC2PUBS                   RCC_PUBCFGSR2_IC2PUBS_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC3PUBS_Pos               (2U)
+#define RCC_PUBCFGSR2_IC3PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR2_IC3PUBS                   RCC_PUBCFGSR2_IC3PUBS_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC4PUBS_Pos               (3U)
+#define RCC_PUBCFGSR2_IC4PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR2_IC4PUBS                   RCC_PUBCFGSR2_IC4PUBS_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC5PUBS_Pos               (4U)
+#define RCC_PUBCFGSR2_IC5PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR2_IC5PUBS                   RCC_PUBCFGSR2_IC5PUBS_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC6PUBS_Pos               (5U)
+#define RCC_PUBCFGSR2_IC6PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR2_IC6PUBS                   RCC_PUBCFGSR2_IC6PUBS_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC7PUBS_Pos               (6U)
+#define RCC_PUBCFGSR2_IC7PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR2_IC7PUBS                   RCC_PUBCFGSR2_IC7PUBS_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC8PUBS_Pos               (7U)
+#define RCC_PUBCFGSR2_IC8PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGSR2_IC8PUBS                   RCC_PUBCFGSR2_IC8PUBS_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC9PUBS_Pos               (8U)
+#define RCC_PUBCFGSR2_IC9PUBS_Msk               (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGSR2_IC9PUBS                   RCC_PUBCFGSR2_IC9PUBS_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC10PUBS_Pos              (9U)
+#define RCC_PUBCFGSR2_IC10PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR2_IC10PUBS                  RCC_PUBCFGSR2_IC10PUBS_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC11PUBS_Pos              (10U)
+#define RCC_PUBCFGSR2_IC11PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR2_IC11PUBS                  RCC_PUBCFGSR2_IC11PUBS_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC12PUBS_Pos              (11U)
+#define RCC_PUBCFGSR2_IC12PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR2_IC12PUBS                  RCC_PUBCFGSR2_IC12PUBS_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC13PUBS_Pos              (12U)
+#define RCC_PUBCFGSR2_IC13PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR2_IC13PUBS                  RCC_PUBCFGSR2_IC13PUBS_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC14PUBS_Pos              (13U)
+#define RCC_PUBCFGSR2_IC14PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGSR2_IC14PUBS                  RCC_PUBCFGSR2_IC14PUBS_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC15PUBS_Pos              (14U)
+#define RCC_PUBCFGSR2_IC15PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGSR2_IC15PUBS                  RCC_PUBCFGSR2_IC15PUBS_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC16PUBS_Pos              (15U)
+#define RCC_PUBCFGSR2_IC16PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGSR2_IC16PUBS                  RCC_PUBCFGSR2_IC16PUBS_Msk           /*!< Public protection of th IC16 configuration bits (enable, ready, divider */
+#define RCC_PUBCFGSR2_IC17PUBS_Pos              (16U)
+#define RCC_PUBCFGSR2_IC17PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGSR2_IC17PUBS                  RCC_PUBCFGSR2_IC17PUBS_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC18PUBS_Pos              (17U)
+#define RCC_PUBCFGSR2_IC18PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGSR2_IC18PUBS                  RCC_PUBCFGSR2_IC18PUBS_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC19PUBS_Pos              (18U)
+#define RCC_PUBCFGSR2_IC19PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGSR2_IC19PUBS                  RCC_PUBCFGSR2_IC19PUBS_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR2_IC20PUBS_Pos              (19U)
+#define RCC_PUBCFGSR2_IC20PUBS_Msk              (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGSR2_IC20PUBS                  RCC_PUBCFGSR2_IC20PUBS_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR3 register  ****************/
+#define RCC_PRIVCFGSR3_MODPRIVS_Pos             (0U)
+#define RCC_PRIVCFGSR3_MODPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGSR3_MODPRIVS                 RCC_PRIVCFGSR3_MODPRIVS_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_SYSPRIVS_Pos             (1U)
+#define RCC_PRIVCFGSR3_SYSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGSR3_SYSPRIVS                 RCC_PRIVCFGSR3_SYSPRIVS_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_BUSPRIVS_Pos             (2U)
+#define RCC_PRIVCFGSR3_BUSPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGSR3_BUSPRIVS                 RCC_PRIVCFGSR3_BUSPRIVS_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_PERPRIVS_Pos             (3U)
+#define RCC_PRIVCFGSR3_PERPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGSR3_PERPRIVS                 RCC_PRIVCFGSR3_PERPRIVS_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_INTPRIVS_Pos             (4U)
+#define RCC_PRIVCFGSR3_INTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGSR3_INTPRIVS                 RCC_PRIVCFGSR3_INTPRIVS_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR3_RSTPRIVS_Pos             (5U)
+#define RCC_PRIVCFGSR3_RSTPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGSR3_RSTPRIVS                 RCC_PRIVCFGSR3_RSTPRIVS_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR3 register  *****************/
+#define RCC_PUBCFGSR3_MODPUBS_Pos               (0U)
+#define RCC_PUBCFGSR3_MODPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGSR3_MODPUBS                   RCC_PUBCFGSR3_MODPUBS_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_SYSPUBS_Pos               (1U)
+#define RCC_PUBCFGSR3_SYSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGSR3_SYSPUBS                   RCC_PUBCFGSR3_SYSPUBS_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_BUSPUBS_Pos               (2U)
+#define RCC_PUBCFGSR3_BUSPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGSR3_BUSPUBS                   RCC_PUBCFGSR3_BUSPUBS_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_PERPUBS_Pos               (3U)
+#define RCC_PUBCFGSR3_PERPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGSR3_PERPUBS                   RCC_PUBCFGSR3_PERPUBS_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_INTPUBS_Pos               (4U)
+#define RCC_PUBCFGSR3_INTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGSR3_INTPUBS                   RCC_PUBCFGSR3_INTPUBS_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR3_RSTPUBS_Pos               (5U)
+#define RCC_PUBCFGSR3_RSTPUBS_Msk               (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGSR3_RSTPUBS                   RCC_PUBCFGSR3_RSTPUBS_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGSR4 register  ****************/
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos           (0U)
+#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk           (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGSR4_ACLKNPRIVS               RCC_PRIVCFGSR4_ACLKNPRIVS_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos          (1U)
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk          (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGSR4_ACLKNCPRIVS              RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk       /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos            (2U)
+#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGSR4_AHBMPRIVS                RCC_PRIVCFGSR4_AHBMPRIVS_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos            (3U)
+#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGSR4_AHB1PRIVS                RCC_PRIVCFGSR4_AHB1PRIVS_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos            (4U)
+#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGSR4_AHB2PRIVS                RCC_PRIVCFGSR4_AHB2PRIVS_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos            (5U)
+#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGSR4_AHB3PRIVS                RCC_PRIVCFGSR4_AHB3PRIVS_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos            (6U)
+#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGSR4_AHB4PRIVS                RCC_PRIVCFGSR4_AHB4PRIVS_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos            (7U)
+#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGSR4_AHB5PRIVS                RCC_PRIVCFGSR4_AHB5PRIVS_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB1PRIVS_Pos            (8U)
+#define RCC_PRIVCFGSR4_APB1PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGSR4_APB1PRIVS                RCC_PRIVCFGSR4_APB1PRIVS_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB2PRIVS_Pos            (9U)
+#define RCC_PRIVCFGSR4_APB2PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGSR4_APB2PRIVS                RCC_PRIVCFGSR4_APB2PRIVS_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB3PRIVS_Pos            (10U)
+#define RCC_PRIVCFGSR4_APB3PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGSR4_APB3PRIVS                RCC_PRIVCFGSR4_APB3PRIVS_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB4PRIVS_Pos            (11U)
+#define RCC_PRIVCFGSR4_APB4PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGSR4_APB4PRIVS                RCC_PRIVCFGSR4_APB4PRIVS_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_APB5PRIVS_Pos            (12U)
+#define RCC_PRIVCFGSR4_APB5PRIVS_Msk            (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGSR4_APB5PRIVS                RCC_PRIVCFGSR4_APB5PRIVS_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGSR4_NOCPRIVS_Pos             (13U)
+#define RCC_PRIVCFGSR4_NOCPRIVS_Msk             (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGSR4_NOCPRIVS                 RCC_PRIVCFGSR4_NOCPRIVS_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR4 register  *****************/
+#define RCC_PUBCFGSR4_ACLKNPUBS_Pos             (0U)
+#define RCC_PUBCFGSR4_ACLKNPUBS_Msk             (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGSR4_ACLKNPUBS                 RCC_PUBCFGSR4_ACLKNPUBS_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos            (1U)
+#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk            (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGSR4_ACLKNCPUBS                RCC_PUBCFGSR4_ACLKNCPUBS_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHBMPUBS_Pos              (2U)
+#define RCC_PUBCFGSR4_AHBMPUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGSR4_AHBMPUBS                  RCC_PUBCFGSR4_AHBMPUBS_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB1PUBS_Pos              (3U)
+#define RCC_PUBCFGSR4_AHB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGSR4_AHB1PUBS                  RCC_PUBCFGSR4_AHB1PUBS_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB2PUBS_Pos              (4U)
+#define RCC_PUBCFGSR4_AHB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGSR4_AHB2PUBS                  RCC_PUBCFGSR4_AHB2PUBS_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB3PUBS_Pos              (5U)
+#define RCC_PUBCFGSR4_AHB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGSR4_AHB3PUBS                  RCC_PUBCFGSR4_AHB3PUBS_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB4PUBS_Pos              (6U)
+#define RCC_PUBCFGSR4_AHB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGSR4_AHB4PUBS                  RCC_PUBCFGSR4_AHB4PUBS_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_AHB5PUBS_Pos              (7U)
+#define RCC_PUBCFGSR4_AHB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGSR4_AHB5PUBS                  RCC_PUBCFGSR4_AHB5PUBS_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB1PUBS_Pos              (8U)
+#define RCC_PUBCFGSR4_APB1PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGSR4_APB1PUBS                  RCC_PUBCFGSR4_APB1PUBS_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB2PUBS_Pos              (9U)
+#define RCC_PUBCFGSR4_APB2PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGSR4_APB2PUBS                  RCC_PUBCFGSR4_APB2PUBS_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB3PUBS_Pos              (10U)
+#define RCC_PUBCFGSR4_APB3PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGSR4_APB3PUBS                  RCC_PUBCFGSR4_APB3PUBS_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB4PUBS_Pos              (11U)
+#define RCC_PUBCFGSR4_APB4PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGSR4_APB4PUBS                  RCC_PUBCFGSR4_APB4PUBS_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_APB5PUBS_Pos              (12U)
+#define RCC_PUBCFGSR4_APB5PUBS_Msk              (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGSR4_APB5PUBS                  RCC_PUBCFGSR4_APB5PUBS_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR4_NOCPUBS_Pos               (13U)
+#define RCC_PUBCFGSR4_NOCPUBS_Msk               (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGSR4_NOCPUBS                   RCC_PUBCFGSR4_NOCPUBS_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGSR5 register  *****************/
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos          (0U)
+#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGSR5_AXISRAM3PUBS              RCC_PUBCFGSR5_AXISRAM3PUBS_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos          (1U)
+#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGSR5_AXISRAM4PUBS              RCC_PUBCFGSR5_AXISRAM4PUBS_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos          (2U)
+#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGSR5_AXISRAM5PUBS              RCC_PUBCFGSR5_AXISRAM5PUBS_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos          (3U)
+#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGSR5_AXISRAM6PUBS              RCC_PUBCFGSR5_AXISRAM6PUBS_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos          (4U)
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGSR5_AHBSRAM1PUBS              RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos          (5U)
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGSR5_AHBSRAM2PUBS              RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos           (6U)
+#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGSR5_BKPSRAMPUBS               RCC_PUBCFGSR5_BKPSRAMPUBS_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos          (7U)
+#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGSR5_AXISRAM1PUBS              RCC_PUBCFGSR5_AXISRAM1PUBS_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos          (8U)
+#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk          (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGSR5_AXISRAM2PUBS              RCC_PUBCFGSR5_AXISRAM2PUBS_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos           (9U)
+#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGSR5_FLEXRAMPUBS               RCC_PUBCFGSR5_FLEXRAMPUBS_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos       (10U)
+#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk       (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos)      /*!< 0x00000400 */
+#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS           RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk    /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos           (11U)
+#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk           (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGSR5_VENCRAMPUBS               RCC_PUBCFGSR5_VENCRAMPUBS_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+/*******************  Bit definition for RCC_CCR register  ********************/
+#define RCC_CCR_LSIONC_Pos                      (0U)
+#define RCC_CCR_LSIONC_Msk                      (0x1UL << RCC_CCR_LSIONC_Pos)         /*!< 0x00000001 */
+#define RCC_CCR_LSIONC                          RCC_CCR_LSIONC_Msk                   /*!< LSI oscillator enable */
+#define RCC_CCR_LSEONC_Pos                      (1U)
+#define RCC_CCR_LSEONC_Msk                      (0x1UL << RCC_CCR_LSEONC_Pos)         /*!< 0x00000002 */
+#define RCC_CCR_LSEONC                          RCC_CCR_LSEONC_Msk                   /*!< LSE oscillator enable */
+#define RCC_CCR_MSIONC_Pos                      (2U)
+#define RCC_CCR_MSIONC_Msk                      (0x1UL << RCC_CCR_MSIONC_Pos)         /*!< 0x00000004 */
+#define RCC_CCR_MSIONC                          RCC_CCR_MSIONC_Msk                   /*!< MSI oscillator enable */
+#define RCC_CCR_HSIONC_Pos                      (3U)
+#define RCC_CCR_HSIONC_Msk                      (0x1UL << RCC_CCR_HSIONC_Pos)         /*!< 0x00000008 */
+#define RCC_CCR_HSIONC                          RCC_CCR_HSIONC_Msk                   /*!< HSI oscillator enable */
+#define RCC_CCR_HSEONC_Pos                      (4U)
+#define RCC_CCR_HSEONC_Msk                      (0x1UL << RCC_CCR_HSEONC_Pos)         /*!< 0x00000010 */
+#define RCC_CCR_HSEONC                          RCC_CCR_HSEONC_Msk                   /*!< HSE oscillator enable */
+#define RCC_CCR_PLL1ONC_Pos                     (8U)
+#define RCC_CCR_PLL1ONC_Msk                     (0x1UL << RCC_CCR_PLL1ONC_Pos)        /*!< 0x00000100 */
+#define RCC_CCR_PLL1ONC                         RCC_CCR_PLL1ONC_Msk                  /*!< PLL1 oscillator enable */
+#define RCC_CCR_PLL2ONC_Pos                     (9U)
+#define RCC_CCR_PLL2ONC_Msk                     (0x1UL << RCC_CCR_PLL2ONC_Pos)        /*!< 0x00000200 */
+#define RCC_CCR_PLL2ONC                         RCC_CCR_PLL2ONC_Msk                  /*!< PLL2 oscillator enable */
+#define RCC_CCR_PLL3ONC_Pos                     (10U)
+#define RCC_CCR_PLL3ONC_Msk                     (0x1UL << RCC_CCR_PLL3ONC_Pos)        /*!< 0x00000400 */
+#define RCC_CCR_PLL3ONC                         RCC_CCR_PLL3ONC_Msk                  /*!< PLL3 oscillator enable */
+#define RCC_CCR_PLL4ONC_Pos                     (11U)
+#define RCC_CCR_PLL4ONC_Msk                     (0x1UL << RCC_CCR_PLL4ONC_Pos)        /*!< 0x00000800 */
+#define RCC_CCR_PLL4ONC                         RCC_CCR_PLL4ONC_Msk                  /*!< PLL4 oscillator enable */
+
+/*****************  Bit definition for RCC_STOPCCR register  ******************/
+#define RCC_STOPCCR_MSISTOPENC_Pos              (0U)
+#define RCC_STOPCCR_MSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */
+#define RCC_STOPCCR_MSISTOPENC                  RCC_STOPCCR_MSISTOPENC_Msk           /*!< MSI oscillator enable */
+#define RCC_STOPCCR_HSISTOPENC_Pos              (1U)
+#define RCC_STOPCCR_HSISTOPENC_Msk              (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */
+#define RCC_STOPCCR_HSISTOPENC                  RCC_STOPCCR_HSISTOPENC_Msk           /*!< HSI oscillator enable */
+
+/****************  Bit definition for RCC_MISCRSTCR register  *****************/
+#define RCC_MISCRSTCR_DBGRSTC_Pos               (0U)
+#define RCC_MISCRSTCR_DBGRSTC_Msk               (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MISCRSTCR_DBGRSTC                   RCC_MISCRSTCR_DBGRSTC_Msk            /*!< DBG reset */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos          (4U)
+#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos)   /*!< 0x00000010 */
+#define RCC_MISCRSTCR_XSPIPHY1RSTC              RCC_MISCRSTCR_XSPIPHY1RSTC_Msk       /*!< XSPIPHY1 reset */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos          (5U)
+#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk          (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos)   /*!< 0x00000020 */
+#define RCC_MISCRSTCR_XSPIPHY2RSTC              RCC_MISCRSTCR_XSPIPHY2RSTC_Msk       /*!< XSPIPHY2 reset */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos         (7U)
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos)    /*!< 0x00000080 */
+#define RCC_MISCRSTCR_SDMMC1DLLRSTC             RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk      /*!< SDMMC1DLL reset */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos         (8U)
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk         (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos)    /*!< 0x00000100 */
+#define RCC_MISCRSTCR_SDMMC2DLLRSTC             RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk      /*!< SDMMC2DLL reset */
+
+/*****************  Bit definition for RCC_MEMRSTCR register  *****************/
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos           (0U)
+#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos)  /*!< 0x00000001 */
+#define RCC_MEMRSTCR_AXISRAM3RSTC               RCC_MEMRSTCR_AXISRAM3RSTC_Msk        /*!< AXISRAM3 reset */
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos           (1U)
+#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos)  /*!< 0x00000002 */
+#define RCC_MEMRSTCR_AXISRAM4RSTC               RCC_MEMRSTCR_AXISRAM4RSTC_Msk        /*!< AXISRAM4 reset */
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos           (2U)
+#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos)  /*!< 0x00000004 */
+#define RCC_MEMRSTCR_AXISRAM5RSTC               RCC_MEMRSTCR_AXISRAM5RSTC_Msk        /*!< AXISRAM5 reset */
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos           (3U)
+#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos)  /*!< 0x00000008 */
+#define RCC_MEMRSTCR_AXISRAM6RSTC               RCC_MEMRSTCR_AXISRAM6RSTC_Msk        /*!< AXISRAM6 reset */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos           (4U)
+#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos)  /*!< 0x00000010 */
+#define RCC_MEMRSTCR_AHBSRAM1RSTC               RCC_MEMRSTCR_AHBSRAM1RSTC_Msk        /*!< AHBSRAM1 reset */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos           (5U)
+#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos)  /*!< 0x00000020 */
+#define RCC_MEMRSTCR_AHBSRAM2RSTC               RCC_MEMRSTCR_AHBSRAM2RSTC_Msk        /*!< AHBSRAM2 reset */
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos           (7U)
+#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_MEMRSTCR_AXISRAM1RSTC               RCC_MEMRSTCR_AXISRAM1RSTC_Msk        /*!< AXISRAM1 reset */
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos           (8U)
+#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk           (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos)  /*!< 0x00000100 */
+#define RCC_MEMRSTCR_AXISRAM2RSTC               RCC_MEMRSTCR_AXISRAM2RSTC_Msk        /*!< AXISRAM2 reset */
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos            (9U)
+#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */
+#define RCC_MEMRSTCR_FLEXRAMRSTC                RCC_MEMRSTCR_FLEXRAMRSTC_Msk         /*!< FLEXRAM reset */
+#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos        (10U)
+#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk        (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos)     /*!< 0x00000400 */
+#define RCC_MEMRSTCR_CACHEAXIRAMRSTC            RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk     /*!< CACHEAXIRAM reset */
+#define RCC_MEMRSTCR_VENCRAMRSTC_Pos            (11U)
+#define RCC_MEMRSTCR_VENCRAMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */
+#define RCC_MEMRSTCR_VENCRAMRSTC                RCC_MEMRSTCR_VENCRAMRSTC_Msk         /*!< VENCRAM reset */
+#define RCC_MEMRSTCR_BOOTROMRSTC_Pos            (12U)
+#define RCC_MEMRSTCR_BOOTROMRSTC_Msk            (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */
+#define RCC_MEMRSTCR_BOOTROMRSTC                RCC_MEMRSTCR_BOOTROMRSTC_Msk         /*!< Boot ROM reset */
+
+/****************  Bit definition for RCC_AHB1RSTCR register  *****************/
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos            (4U)
+#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk            (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTCR_GPDMA1RSTC                RCC_AHB1RSTCR_GPDMA1RSTC_Msk         /*!< GPDMA1 reset */
+#define RCC_AHB1RSTCR_ADC12RSTC_Pos             (5U)
+#define RCC_AHB1RSTCR_ADC12RSTC_Msk             (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB1RSTCR_ADC12RSTC                 RCC_AHB1RSTCR_ADC12RSTC_Msk          /*!< ADC12 reset */
+
+/****************  Bit definition for RCC_AHB2RSTCR register  *****************/
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos            (12U)
+#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk            (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTCR_RAMCFGRSTC                RCC_AHB2RSTCR_RAMCFGRSTC_Msk         /*!< RAMCFG reset */
+#define RCC_AHB2RSTCR_MDF1RSTC_Pos              (16U)
+#define RCC_AHB2RSTCR_MDF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2RSTCR_MDF1RSTC                  RCC_AHB2RSTCR_MDF1RSTC_Msk           /*!< MDF1 reset */
+#define RCC_AHB2RSTCR_ADF1RSTC_Pos              (17U)
+#define RCC_AHB2RSTCR_ADF1RSTC_Msk              (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2RSTCR_ADF1RSTC                  RCC_AHB2RSTCR_ADF1RSTC_Msk           /*!< ADF1 reset */
+
+/****************  Bit definition for RCC_AHB3RSTCR register  *****************/
+#define RCC_AHB3RSTCR_RNGRSTC_Pos               (0U)
+#define RCC_AHB3RSTCR_RNGRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTCR_RNGRSTC                   RCC_AHB3RSTCR_RNGRSTC_Msk            /*!< RNG reset */
+#define RCC_AHB3RSTCR_HASHRSTC_Pos              (1U)
+#define RCC_AHB3RSTCR_HASHRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3RSTCR_HASHRSTC                  RCC_AHB3RSTCR_HASHRSTC_Msk           /*!< HASH reset */
+#define RCC_AHB3RSTCR_CRYPRSTC_Pos              (2U)
+#define RCC_AHB3RSTCR_CRYPRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_AHB3RSTCR_CRYPRSTC                  RCC_AHB3RSTCR_CRYPRSTC_Msk           /*!< CRYP reset */
+#define RCC_AHB3RSTCR_SAESRSTC_Pos              (4U)
+#define RCC_AHB3RSTCR_SAESRSTC_Msk              (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */
+#define RCC_AHB3RSTCR_SAESRSTC                  RCC_AHB3RSTCR_SAESRSTC_Msk           /*!< SAES reset */
+#define RCC_AHB3RSTCR_PKARSTC_Pos               (8U)
+#define RCC_AHB3RSTCR_PKARSTC_Msk               (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3RSTCR_PKARSTC                   RCC_AHB3RSTCR_PKARSTC_Msk            /*!< PKA reset */
+#define RCC_AHB3RSTCR_IACRSTC_Pos               (10U)
+#define RCC_AHB3RSTCR_IACRSTC_Msk               (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos)  /*!< 0x00000400 */
+#define RCC_AHB3RSTCR_IACRSTC                   RCC_AHB3RSTCR_IACRSTC_Msk            /*!< IAC reset */
+
+/****************  Bit definition for RCC_AHB4RSTCR register  *****************/
+#define RCC_AHB4RSTCR_GPIOARSTC_Pos             (0U)
+#define RCC_AHB4RSTCR_GPIOARSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */
+#define RCC_AHB4RSTCR_GPIOARSTC                 RCC_AHB4RSTCR_GPIOARSTC_Msk          /*!< GPIO A reset */
+#define RCC_AHB4RSTCR_GPIOBRSTC_Pos             (1U)
+#define RCC_AHB4RSTCR_GPIOBRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB4RSTCR_GPIOBRSTC                 RCC_AHB4RSTCR_GPIOBRSTC_Msk          /*!< GPIO B reset */
+#define RCC_AHB4RSTCR_GPIOCRSTC_Pos             (2U)
+#define RCC_AHB4RSTCR_GPIOCRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */
+#define RCC_AHB4RSTCR_GPIOCRSTC                 RCC_AHB4RSTCR_GPIOCRSTC_Msk          /*!< GPIO C reset */
+#define RCC_AHB4RSTCR_GPIODRSTC_Pos             (3U)
+#define RCC_AHB4RSTCR_GPIODRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */
+#define RCC_AHB4RSTCR_GPIODRSTC                 RCC_AHB4RSTCR_GPIODRSTC_Msk          /*!< GPIO D reset */
+#define RCC_AHB4RSTCR_GPIOERSTC_Pos             (4U)
+#define RCC_AHB4RSTCR_GPIOERSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */
+#define RCC_AHB4RSTCR_GPIOERSTC                 RCC_AHB4RSTCR_GPIOERSTC_Msk          /*!< GPIO E reset */
+#define RCC_AHB4RSTCR_GPIOFRSTC_Pos             (5U)
+#define RCC_AHB4RSTCR_GPIOFRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB4RSTCR_GPIOFRSTC                 RCC_AHB4RSTCR_GPIOFRSTC_Msk          /*!< GPIO F reset */
+#define RCC_AHB4RSTCR_GPIOGRSTC_Pos             (6U)
+#define RCC_AHB4RSTCR_GPIOGRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */
+#define RCC_AHB4RSTCR_GPIOGRSTC                 RCC_AHB4RSTCR_GPIOGRSTC_Msk          /*!< GPIO G reset */
+#define RCC_AHB4RSTCR_GPIOHRSTC_Pos             (7U)
+#define RCC_AHB4RSTCR_GPIOHRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */
+#define RCC_AHB4RSTCR_GPIOHRSTC                 RCC_AHB4RSTCR_GPIOHRSTC_Msk          /*!< GPIO H reset */
+#define RCC_AHB4RSTCR_GPIONRSTC_Pos             (13U)
+#define RCC_AHB4RSTCR_GPIONRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB4RSTCR_GPIONRSTC                 RCC_AHB4RSTCR_GPIONRSTC_Msk          /*!< GPIO N reset */
+#define RCC_AHB4RSTCR_GPIOORSTC_Pos             (14U)
+#define RCC_AHB4RSTCR_GPIOORSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */
+#define RCC_AHB4RSTCR_GPIOORSTC                 RCC_AHB4RSTCR_GPIOORSTC_Msk          /*!< GPIO O reset */
+#define RCC_AHB4RSTCR_GPIOPRSTC_Pos             (15U)
+#define RCC_AHB4RSTCR_GPIOPRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */
+#define RCC_AHB4RSTCR_GPIOPRSTC                 RCC_AHB4RSTCR_GPIOPRSTC_Msk          /*!< GPIO P reset */
+#define RCC_AHB4RSTCR_GPIOQRSTC_Pos             (16U)
+#define RCC_AHB4RSTCR_GPIOQRSTC_Msk             (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */
+#define RCC_AHB4RSTCR_GPIOQRSTC                 RCC_AHB4RSTCR_GPIOQRSTC_Msk          /*!< GPIO Q reset */
+#define RCC_AHB4RSTCR_PWRRSTC_Pos               (18U)
+#define RCC_AHB4RSTCR_PWRRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos)  /*!< 0x00040000 */
+#define RCC_AHB4RSTCR_PWRRSTC                   RCC_AHB4RSTCR_PWRRSTC_Msk            /*!< PWR reset */
+#define RCC_AHB4RSTCR_CRCRSTC_Pos               (19U)
+#define RCC_AHB4RSTCR_CRCRSTC_Msk               (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos)  /*!< 0x00080000 */
+#define RCC_AHB4RSTCR_CRCRSTC                   RCC_AHB4RSTCR_CRCRSTC_Msk            /*!< CRC reset */
+
+/****************  Bit definition for RCC_AHB5RSTCR register  *****************/
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos            (0U)
+#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5RSTCR_HPDMA1RSTC                RCC_AHB5RSTCR_HPDMA1RSTC_Msk         /*!< HPDMA1 reset */
+#define RCC_AHB5RSTCR_DMA2DRSTC_Pos             (1U)
+#define RCC_AHB5RSTCR_DMA2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */
+#define RCC_AHB5RSTCR_DMA2DRSTC                 RCC_AHB5RSTCR_DMA2DRSTC_Msk          /*!< DMA2D reset */
+#define RCC_AHB5RSTCR_JPEGRSTC_Pos              (3U)
+#define RCC_AHB5RSTCR_JPEGRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5RSTCR_JPEGRSTC                  RCC_AHB5RSTCR_JPEGRSTC_Msk           /*!< JPEG reset */
+#define RCC_AHB5RSTCR_FMCRSTC_Pos               (4U)
+#define RCC_AHB5RSTCR_FMCRSTC_Msk               (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB5RSTCR_FMCRSTC                   RCC_AHB5RSTCR_FMCRSTC_Msk            /*!< FMC reset */
+#define RCC_AHB5RSTCR_XSPI1RSTC_Pos             (5U)
+#define RCC_AHB5RSTCR_XSPI1RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */
+#define RCC_AHB5RSTCR_XSPI1RSTC                 RCC_AHB5RSTCR_XSPI1RSTC_Msk          /*!< XSPI1 reset */
+#define RCC_AHB5RSTCR_PSSIRSTC_Pos              (6U)
+#define RCC_AHB5RSTCR_PSSIRSTC_Msk              (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5RSTCR_PSSIRSTC                  RCC_AHB5RSTCR_PSSIRSTC_Msk           /*!< PSSI reset */
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos            (7U)
+#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5RSTCR_SDMMC2RSTC                RCC_AHB5RSTCR_SDMMC2RSTC_Msk         /*!< SDMMC2 reset */
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos            (8U)
+#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk            (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5RSTCR_SDMMC1RSTC                RCC_AHB5RSTCR_SDMMC1RSTC_Msk         /*!< SDMMC1 reset */
+#define RCC_AHB5RSTCR_XSPI2RSTC_Pos             (12U)
+#define RCC_AHB5RSTCR_XSPI2RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */
+#define RCC_AHB5RSTCR_XSPI2RSTC                 RCC_AHB5RSTCR_XSPI2RSTC_Msk          /*!< XSPI2 reset */
+#define RCC_AHB5RSTCR_XSPIMRSTC_Pos             (13U)
+#define RCC_AHB5RSTCR_XSPIMRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */
+#define RCC_AHB5RSTCR_XSPIMRSTC                 RCC_AHB5RSTCR_XSPIMRSTC_Msk          /*!< XSPIM reset */
+#define RCC_AHB5RSTCR_XSPI3RSTC_Pos             (17U)
+#define RCC_AHB5RSTCR_XSPI3RSTC_Msk             (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */
+#define RCC_AHB5RSTCR_XSPI3RSTC                 RCC_AHB5RSTCR_XSPI3RSTC_Msk          /*!< XSPI3 reset */
+#define RCC_AHB5RSTCR_GFXMMURSTC_Pos            (19U)
+#define RCC_AHB5RSTCR_GFXMMURSTC_Msk            (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5RSTCR_GFXMMURSTC                RCC_AHB5RSTCR_GFXMMURSTC_Msk         /*!< GFXMMU reset */
+#define RCC_AHB5RSTCR_GPU2DRSTC_Pos             (20U)
+#define RCC_AHB5RSTCR_GPU2DRSTC_Msk             (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */
+#define RCC_AHB5RSTCR_GPU2DRSTC                 RCC_AHB5RSTCR_GPU2DRSTC_Msk          /*!< GPU2D reset */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos        (23U)
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos)     /*!< 0x00800000 */
+#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC            RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk     /*!< OTG1PHYCTL reset */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos        (24U)
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk        (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos)     /*!< 0x01000000 */
+#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC            RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk     /*!< OTG2PHYCTL reset */
+#define RCC_AHB5RSTCR_ETH1RSTC_Pos              (25U)
+#define RCC_AHB5RSTCR_ETH1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5RSTCR_ETH1RSTC                  RCC_AHB5RSTCR_ETH1RSTC_Msk           /*!< ETH1 reset */
+#define RCC_AHB5RSTCR_OTG1RSTC_Pos              (26U)
+#define RCC_AHB5RSTCR_OTG1RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5RSTCR_OTG1RSTC                  RCC_AHB5RSTCR_OTG1RSTC_Msk           /*!< OTG1 reset */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos           (27U)
+#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos)  /*!< 0x08000000 */
+#define RCC_AHB5RSTCR_OTGPHY1RSTC               RCC_AHB5RSTCR_OTGPHY1RSTC_Msk        /*!< OTGPHY1 reset */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos           (28U)
+#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk           (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos)  /*!< 0x10000000 */
+#define RCC_AHB5RSTCR_OTGPHY2RSTC               RCC_AHB5RSTCR_OTGPHY2RSTC_Msk        /*!< OTGPHY2 reset */
+#define RCC_AHB5RSTCR_OTG2RSTC_Pos              (29U)
+#define RCC_AHB5RSTCR_OTG2RSTC_Msk              (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5RSTCR_OTG2RSTC                  RCC_AHB5RSTCR_OTG2RSTC_Msk           /*!< OTG2 reset */
+#define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos          (30U)
+#define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk          (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos)   /*!< 0x40000000 */
+#define RCC_AHB5RSTCR_CACHEAXIRSTC              RCC_AHB5RSTCR_CACHEAXIRSTC_Msk       /*!< CACHEAXI reset */
+#define RCC_AHB5RSTCR_NPURSTC_Pos               (31U)
+#define RCC_AHB5RSTCR_NPURSTC_Msk               (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos)  /*!< 0x80000000 */
+#define RCC_AHB5RSTCR_NPURSTC                   RCC_AHB5RSTCR_NPURSTC_Msk            /*!< NPU reset */
+
+/****************  Bit definition for RCC_APB1RSTCR1 register  ****************/
+#define RCC_APB1RSTCR1_TIM2RSTC_Pos             (0U)
+#define RCC_APB1RSTCR1_TIM2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */
+#define RCC_APB1RSTCR1_TIM2RSTC                 RCC_APB1RSTCR1_TIM2RSTC_Msk          /*!< TIM2 reset */
+#define RCC_APB1RSTCR1_TIM3RSTC_Pos             (1U)
+#define RCC_APB1RSTCR1_TIM3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */
+#define RCC_APB1RSTCR1_TIM3RSTC                 RCC_APB1RSTCR1_TIM3RSTC_Msk          /*!< TIM3 reset */
+#define RCC_APB1RSTCR1_TIM4RSTC_Pos             (2U)
+#define RCC_APB1RSTCR1_TIM4RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */
+#define RCC_APB1RSTCR1_TIM4RSTC                 RCC_APB1RSTCR1_TIM4RSTC_Msk          /*!< TIM4 reset */
+#define RCC_APB1RSTCR1_TIM5RSTC_Pos             (3U)
+#define RCC_APB1RSTCR1_TIM5RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */
+#define RCC_APB1RSTCR1_TIM5RSTC                 RCC_APB1RSTCR1_TIM5RSTC_Msk          /*!< TIM5 reset */
+#define RCC_APB1RSTCR1_TIM6RSTC_Pos             (4U)
+#define RCC_APB1RSTCR1_TIM6RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */
+#define RCC_APB1RSTCR1_TIM6RSTC                 RCC_APB1RSTCR1_TIM6RSTC_Msk          /*!< TIM6 reset */
+#define RCC_APB1RSTCR1_TIM7RSTC_Pos             (5U)
+#define RCC_APB1RSTCR1_TIM7RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB1RSTCR1_TIM7RSTC                 RCC_APB1RSTCR1_TIM7RSTC_Msk          /*!< TIM7 reset */
+#define RCC_APB1RSTCR1_TIM12RSTC_Pos            (6U)
+#define RCC_APB1RSTCR1_TIM12RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTCR1_TIM12RSTC                RCC_APB1RSTCR1_TIM12RSTC_Msk         /*!< TIM12 reset */
+#define RCC_APB1RSTCR1_TIM13RSTC_Pos            (7U)
+#define RCC_APB1RSTCR1_TIM13RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTCR1_TIM13RSTC                RCC_APB1RSTCR1_TIM13RSTC_Msk         /*!< TIM13 reset */
+#define RCC_APB1RSTCR1_TIM14RSTC_Pos            (8U)
+#define RCC_APB1RSTCR1_TIM14RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR1_TIM14RSTC                RCC_APB1RSTCR1_TIM14RSTC_Msk         /*!< TIM14 reset */
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos           (9U)
+#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB1RSTCR1_LPTIM1RSTC               RCC_APB1RSTCR1_LPTIM1RSTC_Msk        /*!< LPTIM1 reset */
+#define RCC_APB1RSTCR1_WWDGRSTC_Pos             (11U)
+#define RCC_APB1RSTCR1_WWDGRSTC_Msk             (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */
+#define RCC_APB1RSTCR1_WWDGRSTC                 RCC_APB1RSTCR1_WWDGRSTC_Msk          /*!< WWDG reset */
+#define RCC_APB1RSTCR1_TIM10RSTC_Pos            (12U)
+#define RCC_APB1RSTCR1_TIM10RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB1RSTCR1_TIM10RSTC                RCC_APB1RSTCR1_TIM10RSTC_Msk         /*!< TIM10 reset */
+#define RCC_APB1RSTCR1_TIM11RSTC_Pos            (13U)
+#define RCC_APB1RSTCR1_TIM11RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB1RSTCR1_TIM11RSTC                RCC_APB1RSTCR1_TIM11RSTC_Msk         /*!< TIM11 reset */
+#define RCC_APB1RSTCR1_SPI2RSTC_Pos             (14U)
+#define RCC_APB1RSTCR1_SPI2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */
+#define RCC_APB1RSTCR1_SPI2RSTC                 RCC_APB1RSTCR1_SPI2RSTC_Msk          /*!< SPI2 reset */
+#define RCC_APB1RSTCR1_SPI3RSTC_Pos             (15U)
+#define RCC_APB1RSTCR1_SPI3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB1RSTCR1_SPI3RSTC                 RCC_APB1RSTCR1_SPI3RSTC_Msk          /*!< SPI3 reset */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos         (16U)
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk         (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos)    /*!< 0x00010000 */
+#define RCC_APB1RSTCR1_SPDIFRX1RSTC             RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk      /*!< SPDIFRX1 reset */
+#define RCC_APB1RSTCR1_USART2RSTC_Pos           (17U)
+#define RCC_APB1RSTCR1_USART2RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos)  /*!< 0x00020000 */
+#define RCC_APB1RSTCR1_USART2RSTC               RCC_APB1RSTCR1_USART2RSTC_Msk        /*!< USART2 reset */
+#define RCC_APB1RSTCR1_USART3RSTC_Pos           (18U)
+#define RCC_APB1RSTCR1_USART3RSTC_Msk           (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos)  /*!< 0x00040000 */
+#define RCC_APB1RSTCR1_USART3RSTC               RCC_APB1RSTCR1_USART3RSTC_Msk        /*!< USART3 reset */
+#define RCC_APB1RSTCR1_UART4RSTC_Pos            (19U)
+#define RCC_APB1RSTCR1_UART4RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTCR1_UART4RSTC                RCC_APB1RSTCR1_UART4RSTC_Msk         /*!< UART4 reset */
+#define RCC_APB1RSTCR1_UART5RSTC_Pos            (20U)
+#define RCC_APB1RSTCR1_UART5RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTCR1_UART5RSTC                RCC_APB1RSTCR1_UART5RSTC_Msk         /*!< UART5 reset */
+#define RCC_APB1RSTCR1_I2C1RSTC_Pos             (21U)
+#define RCC_APB1RSTCR1_I2C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */
+#define RCC_APB1RSTCR1_I2C1RSTC                 RCC_APB1RSTCR1_I2C1RSTC_Msk          /*!< I2C1 reset */
+#define RCC_APB1RSTCR1_I2C2RSTC_Pos             (22U)
+#define RCC_APB1RSTCR1_I2C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */
+#define RCC_APB1RSTCR1_I2C2RSTC                 RCC_APB1RSTCR1_I2C2RSTC_Msk          /*!< I2C2 reset */
+#define RCC_APB1RSTCR1_I2C3RSTC_Pos             (23U)
+#define RCC_APB1RSTCR1_I2C3RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */
+#define RCC_APB1RSTCR1_I2C3RSTC                 RCC_APB1RSTCR1_I2C3RSTC_Msk          /*!< I2C3 reset */
+#define RCC_APB1RSTCR1_I3C1RSTC_Pos             (24U)
+#define RCC_APB1RSTCR1_I3C1RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */
+#define RCC_APB1RSTCR1_I3C1RSTC                 RCC_APB1RSTCR1_I3C1RSTC_Msk          /*!< I3C1 reset */
+#define RCC_APB1RSTCR1_I3C2RSTC_Pos             (25U)
+#define RCC_APB1RSTCR1_I3C2RSTC_Msk             (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */
+#define RCC_APB1RSTCR1_I3C2RSTC                 RCC_APB1RSTCR1_I3C2RSTC_Msk          /*!< I3C2 reset */
+#define RCC_APB1RSTCR1_UART7RSTC_Pos            (30U)
+#define RCC_APB1RSTCR1_UART7RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTCR1_UART7RSTC                RCC_APB1RSTCR1_UART7RSTC_Msk         /*!< UART7 reset */
+#define RCC_APB1RSTCR1_UART8RSTC_Pos            (31U)
+#define RCC_APB1RSTCR1_UART8RSTC_Msk            (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTCR1_UART8RSTC                RCC_APB1RSTCR1_UART8RSTC_Msk         /*!< UART8 reset */
+
+/****************  Bit definition for RCC_APB1RSTCR2 register  ****************/
+#define RCC_APB1RSTCR2_MDIOSRSTC_Pos            (5U)
+#define RCC_APB1RSTCR2_MDIOSRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTCR2_MDIOSRSTC                RCC_APB1RSTCR2_MDIOSRSTC_Msk         /*!< MDIOS reset */
+#define RCC_APB1RSTCR2_FDCANRSTC_Pos            (8U)
+#define RCC_APB1RSTCR2_FDCANRSTC_Msk            (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTCR2_FDCANRSTC                RCC_APB1RSTCR2_FDCANRSTC_Msk         /*!< FDCAN reset */
+#define RCC_APB1RSTCR2_UCPD1RSTC_Pos            (18U)
+#define RCC_APB1RSTCR2_UCPD1RSTC_Msk            (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTCR2_UCPD1RSTC                RCC_APB1RSTCR2_UCPD1RSTC_Msk         /*!< UCPD1 reset */
+
+/****************  Bit definition for RCC_APB2RSTCR register  *****************/
+#define RCC_APB2RSTCR_TIM1RSTC_Pos              (0U)
+#define RCC_APB2RSTCR_TIM1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTCR_TIM1RSTC                  RCC_APB2RSTCR_TIM1RSTC_Msk           /*!< TIM1 reset */
+#define RCC_APB2RSTCR_TIM8RSTC_Pos              (1U)
+#define RCC_APB2RSTCR_TIM8RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTCR_TIM8RSTC                  RCC_APB2RSTCR_TIM8RSTC_Msk           /*!< TIM8 reset */
+#define RCC_APB2RSTCR_USART1RSTC_Pos            (4U)
+#define RCC_APB2RSTCR_USART1RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTCR_USART1RSTC                RCC_APB2RSTCR_USART1RSTC_Msk         /*!< USART1 reset */
+#define RCC_APB2RSTCR_USART6RSTC_Pos            (5U)
+#define RCC_APB2RSTCR_USART6RSTC_Msk            (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTCR_USART6RSTC                RCC_APB2RSTCR_USART6RSTC_Msk         /*!< USART6 reset */
+#define RCC_APB2RSTCR_UART9RSTC_Pos             (6U)
+#define RCC_APB2RSTCR_UART9RSTC_Msk             (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */
+#define RCC_APB2RSTCR_UART9RSTC                 RCC_APB2RSTCR_UART9RSTC_Msk          /*!< UART9 reset */
+#define RCC_APB2RSTCR_USART10RSTC_Pos           (7U)
+#define RCC_APB2RSTCR_USART10RSTC_Msk           (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos)  /*!< 0x00000080 */
+#define RCC_APB2RSTCR_USART10RSTC               RCC_APB2RSTCR_USART10RSTC_Msk        /*!< USART10 reset */
+#define RCC_APB2RSTCR_SPI1RSTC_Pos              (12U)
+#define RCC_APB2RSTCR_SPI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTCR_SPI1RSTC                  RCC_APB2RSTCR_SPI1RSTC_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTCR_SPI4RSTC_Pos              (13U)
+#define RCC_APB2RSTCR_SPI4RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTCR_SPI4RSTC                  RCC_APB2RSTCR_SPI4RSTC_Msk           /*!< SPI4 reset */
+#define RCC_APB2RSTCR_TIM18RSTC_Pos             (15U)
+#define RCC_APB2RSTCR_TIM18RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */
+#define RCC_APB2RSTCR_TIM18RSTC                 RCC_APB2RSTCR_TIM18RSTC_Msk          /*!< TIM18 reset */
+#define RCC_APB2RSTCR_TIM15RSTC_Pos             (16U)
+#define RCC_APB2RSTCR_TIM15RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */
+#define RCC_APB2RSTCR_TIM15RSTC                 RCC_APB2RSTCR_TIM15RSTC_Msk          /*!< TIM15 reset */
+#define RCC_APB2RSTCR_TIM16RSTC_Pos             (17U)
+#define RCC_APB2RSTCR_TIM16RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */
+#define RCC_APB2RSTCR_TIM16RSTC                 RCC_APB2RSTCR_TIM16RSTC_Msk          /*!< TIM16 reset */
+#define RCC_APB2RSTCR_TIM17RSTC_Pos             (18U)
+#define RCC_APB2RSTCR_TIM17RSTC_Msk             (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */
+#define RCC_APB2RSTCR_TIM17RSTC                 RCC_APB2RSTCR_TIM17RSTC_Msk          /*!< TIM17 reset */
+#define RCC_APB2RSTCR_TIM9RSTC_Pos              (19U)
+#define RCC_APB2RSTCR_TIM9RSTC_Msk              (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTCR_TIM9RSTC                  RCC_APB2RSTCR_TIM9RSTC_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTCR_SPI5RSTC_Pos              (20U)
+#define RCC_APB2RSTCR_SPI5RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTCR_SPI5RSTC                  RCC_APB2RSTCR_SPI5RSTC_Msk           /*!< SPI5 reset */
+#define RCC_APB2RSTCR_SAI1RSTC_Pos              (21U)
+#define RCC_APB2RSTCR_SAI1RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTCR_SAI1RSTC                  RCC_APB2RSTCR_SAI1RSTC_Msk           /*!< SAI1 reset */
+#define RCC_APB2RSTCR_SAI2RSTC_Pos              (22U)
+#define RCC_APB2RSTCR_SAI2RSTC_Msk              (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTCR_SAI2RSTC                  RCC_APB2RSTCR_SAI2RSTC_Msk           /*!< SAI2 reset */
+
+/****************  Bit definition for RCC_APB4RSTCR1 register  ****************/
+#define RCC_APB4RSTCR1_HDPRSTC_Pos              (2U)
+#define RCC_APB4RSTCR1_HDPRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR1_HDPRSTC                  RCC_APB4RSTCR1_HDPRSTC_Msk           /*!< HDP reset */
+#define RCC_APB4RSTCR1_LPUART1RSTC_Pos          (3U)
+#define RCC_APB4RSTCR1_LPUART1RSTC_Msk          (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos)   /*!< 0x00000008 */
+#define RCC_APB4RSTCR1_LPUART1RSTC              RCC_APB4RSTCR1_LPUART1RSTC_Msk       /*!< LPUART1 reset */
+#define RCC_APB4RSTCR1_SPI6RSTC_Pos             (5U)
+#define RCC_APB4RSTCR1_SPI6RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */
+#define RCC_APB4RSTCR1_SPI6RSTC                 RCC_APB4RSTCR1_SPI6RSTC_Msk          /*!< SPI6 reset */
+#define RCC_APB4RSTCR1_I2C4RSTC_Pos             (7U)
+#define RCC_APB4RSTCR1_I2C4RSTC_Msk             (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */
+#define RCC_APB4RSTCR1_I2C4RSTC                 RCC_APB4RSTCR1_I2C4RSTC_Msk          /*!< I2C4 reset */
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos           (9U)
+#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos)  /*!< 0x00000200 */
+#define RCC_APB4RSTCR1_LPTIM2RSTC               RCC_APB4RSTCR1_LPTIM2RSTC_Msk        /*!< LPTIM2 reset */
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos           (10U)
+#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos)  /*!< 0x00000400 */
+#define RCC_APB4RSTCR1_LPTIM3RSTC               RCC_APB4RSTCR1_LPTIM3RSTC_Msk        /*!< LPTIM3 reset */
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos           (11U)
+#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos)  /*!< 0x00000800 */
+#define RCC_APB4RSTCR1_LPTIM4RSTC               RCC_APB4RSTCR1_LPTIM4RSTC_Msk        /*!< LPTIM4 reset */
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos           (12U)
+#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk           (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos)  /*!< 0x00001000 */
+#define RCC_APB4RSTCR1_LPTIM5RSTC               RCC_APB4RSTCR1_LPTIM5RSTC_Msk        /*!< LPTIM5 reset */
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos          (15U)
+#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk          (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos)   /*!< 0x00008000 */
+#define RCC_APB4RSTCR1_VREFBUFRSTC              RCC_APB4RSTCR1_VREFBUFRSTC_Msk       /*!< VREFBUF reset */
+#define RCC_APB4RSTCR1_RTCRSTC_Pos              (16U)
+#define RCC_APB4RSTCR1_RTCRSTC_Msk              (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */
+#define RCC_APB4RSTCR1_RTCRSTC                  RCC_APB4RSTCR1_RTCRSTC_Msk           /*!< RTC reset */
+
+/****************  Bit definition for RCC_APB4RSTCR2 register  ****************/
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos           (0U)
+#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk           (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos)  /*!< 0x00000001 */
+#define RCC_APB4RSTCR2_SYSCFGRSTC               RCC_APB4RSTCR2_SYSCFGRSTC_Msk        /*!< SYSCFG reset */
+#define RCC_APB4RSTCR2_DTSRSTC_Pos              (2U)
+#define RCC_APB4RSTCR2_DTSRSTC_Msk              (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB4RSTCR2_DTSRSTC                  RCC_APB4RSTCR2_DTSRSTC_Msk           /*!< DTS reset */
+
+/****************  Bit definition for RCC_APB5RSTCR register  *****************/
+#define RCC_APB5RSTCR_LTDCRSTC_Pos              (1U)
+#define RCC_APB5RSTCR_LTDCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */
+#define RCC_APB5RSTCR_LTDCRSTC                  RCC_APB5RSTCR_LTDCRSTC_Msk           /*!< LTDC reset */
+#define RCC_APB5RSTCR_DCMIPPRSTC_Pos            (2U)
+#define RCC_APB5RSTCR_DCMIPPRSTC_Msk            (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */
+#define RCC_APB5RSTCR_DCMIPPRSTC                RCC_APB5RSTCR_DCMIPPRSTC_Msk         /*!< DCMIPP reset */
+#define RCC_APB5RSTCR_GFXTIMRSTC_Pos            (4U)
+#define RCC_APB5RSTCR_GFXTIMRSTC_Msk            (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */
+#define RCC_APB5RSTCR_GFXTIMRSTC                RCC_APB5RSTCR_GFXTIMRSTC_Msk         /*!< GFXTIM reset */
+#define RCC_APB5RSTCR_VENCRSTC_Pos              (5U)
+#define RCC_APB5RSTCR_VENCRSTC_Msk              (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */
+#define RCC_APB5RSTCR_VENCRSTC                  RCC_APB5RSTCR_VENCRSTC_Msk           /*!< VENC reset */
+#define RCC_APB5RSTCR_CSIRSTC_Pos               (6U)
+#define RCC_APB5RSTCR_CSIRSTC_Msk               (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos)  /*!< 0x00000040 */
+#define RCC_APB5RSTCR_CSIRSTC                   RCC_APB5RSTCR_CSIRSTC_Msk            /*!< CSI reset */
+
+/*****************  Bit definition for RCC_DIVENCR register  ******************/
+#define RCC_DIVENCR_IC1ENC_Pos                  (0U)
+#define RCC_DIVENCR_IC1ENC_Msk                  (0x1UL << RCC_DIVENCR_IC1ENC_Pos)     /*!< 0x00000001 */
+#define RCC_DIVENCR_IC1ENC                      RCC_DIVENCR_IC1ENC_Msk               /*!< IC1 enable */
+#define RCC_DIVENCR_IC2ENC_Pos                  (1U)
+#define RCC_DIVENCR_IC2ENC_Msk                  (0x1UL << RCC_DIVENCR_IC2ENC_Pos)     /*!< 0x00000002 */
+#define RCC_DIVENCR_IC2ENC                      RCC_DIVENCR_IC2ENC_Msk               /*!< IC2 enable */
+#define RCC_DIVENCR_IC3ENC_Pos                  (2U)
+#define RCC_DIVENCR_IC3ENC_Msk                  (0x1UL << RCC_DIVENCR_IC3ENC_Pos)     /*!< 0x00000004 */
+#define RCC_DIVENCR_IC3ENC                      RCC_DIVENCR_IC3ENC_Msk               /*!< IC3 enable */
+#define RCC_DIVENCR_IC4ENC_Pos                  (3U)
+#define RCC_DIVENCR_IC4ENC_Msk                  (0x1UL << RCC_DIVENCR_IC4ENC_Pos)     /*!< 0x00000008 */
+#define RCC_DIVENCR_IC4ENC                      RCC_DIVENCR_IC4ENC_Msk               /*!< IC4 enable */
+#define RCC_DIVENCR_IC5ENC_Pos                  (4U)
+#define RCC_DIVENCR_IC5ENC_Msk                  (0x1UL << RCC_DIVENCR_IC5ENC_Pos)     /*!< 0x00000010 */
+#define RCC_DIVENCR_IC5ENC                      RCC_DIVENCR_IC5ENC_Msk               /*!< IC5 enable */
+#define RCC_DIVENCR_IC6ENC_Pos                  (5U)
+#define RCC_DIVENCR_IC6ENC_Msk                  (0x1UL << RCC_DIVENCR_IC6ENC_Pos)     /*!< 0x00000020 */
+#define RCC_DIVENCR_IC6ENC                      RCC_DIVENCR_IC6ENC_Msk               /*!< IC6 enable */
+#define RCC_DIVENCR_IC7ENC_Pos                  (6U)
+#define RCC_DIVENCR_IC7ENC_Msk                  (0x1UL << RCC_DIVENCR_IC7ENC_Pos)     /*!< 0x00000040 */
+#define RCC_DIVENCR_IC7ENC                      RCC_DIVENCR_IC7ENC_Msk               /*!< IC7 enable */
+#define RCC_DIVENCR_IC8ENC_Pos                  (7U)
+#define RCC_DIVENCR_IC8ENC_Msk                  (0x1UL << RCC_DIVENCR_IC8ENC_Pos)     /*!< 0x00000080 */
+#define RCC_DIVENCR_IC8ENC                      RCC_DIVENCR_IC8ENC_Msk               /*!< IC8 enable */
+#define RCC_DIVENCR_IC9ENC_Pos                  (8U)
+#define RCC_DIVENCR_IC9ENC_Msk                  (0x1UL << RCC_DIVENCR_IC9ENC_Pos)     /*!< 0x00000100 */
+#define RCC_DIVENCR_IC9ENC                      RCC_DIVENCR_IC9ENC_Msk               /*!< IC9 enable */
+#define RCC_DIVENCR_IC10ENC_Pos                 (9U)
+#define RCC_DIVENCR_IC10ENC_Msk                 (0x1UL << RCC_DIVENCR_IC10ENC_Pos)    /*!< 0x00000200 */
+#define RCC_DIVENCR_IC10ENC                     RCC_DIVENCR_IC10ENC_Msk              /*!< IC10 enable */
+#define RCC_DIVENCR_IC11ENC_Pos                 (10U)
+#define RCC_DIVENCR_IC11ENC_Msk                 (0x1UL << RCC_DIVENCR_IC11ENC_Pos)    /*!< 0x00000400 */
+#define RCC_DIVENCR_IC11ENC                     RCC_DIVENCR_IC11ENC_Msk              /*!< IC11 enable */
+#define RCC_DIVENCR_IC12ENC_Pos                 (11U)
+#define RCC_DIVENCR_IC12ENC_Msk                 (0x1UL << RCC_DIVENCR_IC12ENC_Pos)    /*!< 0x00000800 */
+#define RCC_DIVENCR_IC12ENC                     RCC_DIVENCR_IC12ENC_Msk              /*!< IC12 enable */
+#define RCC_DIVENCR_IC13ENC_Pos                 (12U)
+#define RCC_DIVENCR_IC13ENC_Msk                 (0x1UL << RCC_DIVENCR_IC13ENC_Pos)    /*!< 0x00001000 */
+#define RCC_DIVENCR_IC13ENC                     RCC_DIVENCR_IC13ENC_Msk              /*!< IC13 enable */
+#define RCC_DIVENCR_IC14ENC_Pos                 (13U)
+#define RCC_DIVENCR_IC14ENC_Msk                 (0x1UL << RCC_DIVENCR_IC14ENC_Pos)    /*!< 0x00002000 */
+#define RCC_DIVENCR_IC14ENC                     RCC_DIVENCR_IC14ENC_Msk              /*!< IC14 enable */
+#define RCC_DIVENCR_IC15ENC_Pos                 (14U)
+#define RCC_DIVENCR_IC15ENC_Msk                 (0x1UL << RCC_DIVENCR_IC15ENC_Pos)    /*!< 0x00004000 */
+#define RCC_DIVENCR_IC15ENC                     RCC_DIVENCR_IC15ENC_Msk              /*!< IC15 enable */
+#define RCC_DIVENCR_IC16ENC_Pos                 (15U)
+#define RCC_DIVENCR_IC16ENC_Msk                 (0x1UL << RCC_DIVENCR_IC16ENC_Pos)    /*!< 0x00008000 */
+#define RCC_DIVENCR_IC16ENC                     RCC_DIVENCR_IC16ENC_Msk              /*!< IC16 enable */
+#define RCC_DIVENCR_IC17ENC_Pos                 (16U)
+#define RCC_DIVENCR_IC17ENC_Msk                 (0x1UL << RCC_DIVENCR_IC17ENC_Pos)    /*!< 0x00010000 */
+#define RCC_DIVENCR_IC17ENC                     RCC_DIVENCR_IC17ENC_Msk              /*!< IC17 enable */
+#define RCC_DIVENCR_IC18ENC_Pos                 (17U)
+#define RCC_DIVENCR_IC18ENC_Msk                 (0x1UL << RCC_DIVENCR_IC18ENC_Pos)    /*!< 0x00020000 */
+#define RCC_DIVENCR_IC18ENC                     RCC_DIVENCR_IC18ENC_Msk              /*!< IC18 enable */
+#define RCC_DIVENCR_IC19ENC_Pos                 (18U)
+#define RCC_DIVENCR_IC19ENC_Msk                 (0x1UL << RCC_DIVENCR_IC19ENC_Pos)    /*!< 0x00040000 */
+#define RCC_DIVENCR_IC19ENC                     RCC_DIVENCR_IC19ENC_Msk              /*!< IC19 enable */
+#define RCC_DIVENCR_IC20ENC_Pos                 (19U)
+#define RCC_DIVENCR_IC20ENC_Msk                 (0x1UL << RCC_DIVENCR_IC20ENC_Pos)    /*!< 0x00080000 */
+#define RCC_DIVENCR_IC20ENC                     RCC_DIVENCR_IC20ENC_Msk              /*!< IC20 enable */
+
+/*****************  Bit definition for RCC_BUSENCR register  ******************/
+#define RCC_BUSENCR_ACLKNENC_Pos                (0U)
+#define RCC_BUSENCR_ACLKNENC_Msk                (0x1UL << RCC_BUSENCR_ACLKNENC_Pos)   /*!< 0x00000001 */
+#define RCC_BUSENCR_ACLKNENC                    RCC_BUSENCR_ACLKNENC_Msk             /*!< ACLKN enable */
+#define RCC_BUSENCR_ACLKNCENC_Pos               (1U)
+#define RCC_BUSENCR_ACLKNCENC_Msk               (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSENCR_ACLKNCENC                   RCC_BUSENCR_ACLKNCENC_Msk            /*!< ACLKNC enable */
+#define RCC_BUSENCR_AHBMENC_Pos                 (2U)
+#define RCC_BUSENCR_AHBMENC_Msk                 (0x1UL << RCC_BUSENCR_AHBMENC_Pos)    /*!< 0x00000004 */
+#define RCC_BUSENCR_AHBMENC                     RCC_BUSENCR_AHBMENC_Msk              /*!< AHBM enable */
+#define RCC_BUSENCR_AHB1ENC_Pos                 (3U)
+#define RCC_BUSENCR_AHB1ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB1ENC_Pos)    /*!< 0x00000008 */
+#define RCC_BUSENCR_AHB1ENC                     RCC_BUSENCR_AHB1ENC_Msk              /*!< AHB1 enable */
+#define RCC_BUSENCR_AHB2ENC_Pos                 (4U)
+#define RCC_BUSENCR_AHB2ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB2ENC_Pos)    /*!< 0x00000010 */
+#define RCC_BUSENCR_AHB2ENC                     RCC_BUSENCR_AHB2ENC_Msk              /*!< AHB2 enable */
+#define RCC_BUSENCR_AHB3ENC_Pos                 (5U)
+#define RCC_BUSENCR_AHB3ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB3ENC_Pos)    /*!< 0x00000020 */
+#define RCC_BUSENCR_AHB3ENC                     RCC_BUSENCR_AHB3ENC_Msk              /*!< AHB3 enable */
+#define RCC_BUSENCR_AHB4ENC_Pos                 (6U)
+#define RCC_BUSENCR_AHB4ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB4ENC_Pos)    /*!< 0x00000040 */
+#define RCC_BUSENCR_AHB4ENC                     RCC_BUSENCR_AHB4ENC_Msk              /*!< AHB4 enable */
+#define RCC_BUSENCR_AHB5ENC_Pos                 (7U)
+#define RCC_BUSENCR_AHB5ENC_Msk                 (0x1UL << RCC_BUSENCR_AHB5ENC_Pos)    /*!< 0x00000080 */
+#define RCC_BUSENCR_AHB5ENC                     RCC_BUSENCR_AHB5ENC_Msk              /*!< AHB5 enable */
+#define RCC_BUSENCR_APB1ENC_Pos                 (8U)
+#define RCC_BUSENCR_APB1ENC_Msk                 (0x1UL << RCC_BUSENCR_APB1ENC_Pos)    /*!< 0x00000100 */
+#define RCC_BUSENCR_APB1ENC                     RCC_BUSENCR_APB1ENC_Msk              /*!< APB1 enable */
+#define RCC_BUSENCR_APB2ENC_Pos                 (9U)
+#define RCC_BUSENCR_APB2ENC_Msk                 (0x1UL << RCC_BUSENCR_APB2ENC_Pos)    /*!< 0x00000200 */
+#define RCC_BUSENCR_APB2ENC                     RCC_BUSENCR_APB2ENC_Msk              /*!< APB2 enable */
+#define RCC_BUSENCR_APB3ENC_Pos                 (10U)
+#define RCC_BUSENCR_APB3ENC_Msk                 (0x1UL << RCC_BUSENCR_APB3ENC_Pos)    /*!< 0x00000400 */
+#define RCC_BUSENCR_APB3ENC                     RCC_BUSENCR_APB3ENC_Msk              /*!< APB3 enable */
+#define RCC_BUSENCR_APB4ENC_Pos                 (11U)
+#define RCC_BUSENCR_APB4ENC_Msk                 (0x1UL << RCC_BUSENCR_APB4ENC_Pos)    /*!< 0x00000800 */
+#define RCC_BUSENCR_APB4ENC                     RCC_BUSENCR_APB4ENC_Msk              /*!< APB4 enable */
+#define RCC_BUSENCR_APB5ENC_Pos                 (12U)
+#define RCC_BUSENCR_APB5ENC_Msk                 (0x1UL << RCC_BUSENCR_APB5ENC_Pos)    /*!< 0x00001000 */
+#define RCC_BUSENCR_APB5ENC                     RCC_BUSENCR_APB5ENC_Msk              /*!< APB5 enable */
+
+/*****************  Bit definition for RCC_MISCENCR register  *****************/
+#define RCC_MISCENCR_DBGENC_Pos                 (0U)
+#define RCC_MISCENCR_DBGENC_Msk                 (0x1UL << RCC_MISCENCR_DBGENC_Pos)    /*!< 0x00000001 */
+#define RCC_MISCENCR_DBGENC                     RCC_MISCENCR_DBGENC_Msk              /*!< DBG enable */
+#define RCC_MISCENCR_MCO1ENC_Pos                (1U)
+#define RCC_MISCENCR_MCO1ENC_Msk                (0x1UL << RCC_MISCENCR_MCO1ENC_Pos)   /*!< 0x00000002 */
+#define RCC_MISCENCR_MCO1ENC                    RCC_MISCENCR_MCO1ENC_Msk             /*!< MCO1 enable */
+#define RCC_MISCENCR_MCO2ENC_Pos                (2U)
+#define RCC_MISCENCR_MCO2ENC_Msk                (0x1UL << RCC_MISCENCR_MCO2ENC_Pos)   /*!< 0x00000004 */
+#define RCC_MISCENCR_MCO2ENC                    RCC_MISCENCR_MCO2ENC_Msk             /*!< MCO2 enable */
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos         (3U)
+#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk         (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MISCENCR_XSPIPHYCOMPENC             RCC_MISCENCR_XSPIPHYCOMPENC_Msk      /*!< XSPIPHYCOMP enable */
+#define RCC_MISCENCR_PERENC_Pos                 (6U)
+#define RCC_MISCENCR_PERENC_Msk                 (0x1UL << RCC_MISCENCR_PERENC_Pos)    /*!< 0x00000040 */
+#define RCC_MISCENCR_PERENC                     RCC_MISCENCR_PERENC_Msk              /*!< PER enable */
+
+/*****************  Bit definition for RCC_MEMENCR register  ******************/
+#define RCC_MEMENCR_AXISRAM3ENC_Pos             (0U)
+#define RCC_MEMENCR_AXISRAM3ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */
+#define RCC_MEMENCR_AXISRAM3ENC                 RCC_MEMENCR_AXISRAM3ENC_Msk          /*!< AXISRAM3 enable */
+#define RCC_MEMENCR_AXISRAM4ENC_Pos             (1U)
+#define RCC_MEMENCR_AXISRAM4ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */
+#define RCC_MEMENCR_AXISRAM4ENC                 RCC_MEMENCR_AXISRAM4ENC_Msk          /*!< AXISRAM4 enable */
+#define RCC_MEMENCR_AXISRAM5ENC_Pos             (2U)
+#define RCC_MEMENCR_AXISRAM5ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */
+#define RCC_MEMENCR_AXISRAM5ENC                 RCC_MEMENCR_AXISRAM5ENC_Msk          /*!< AXISRAM5 enable */
+#define RCC_MEMENCR_AXISRAM6ENC_Pos             (3U)
+#define RCC_MEMENCR_AXISRAM6ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */
+#define RCC_MEMENCR_AXISRAM6ENC                 RCC_MEMENCR_AXISRAM6ENC_Msk          /*!< AXISRAM6 enable */
+#define RCC_MEMENCR_AHBSRAM1ENC_Pos             (4U)
+#define RCC_MEMENCR_AHBSRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */
+#define RCC_MEMENCR_AHBSRAM1ENC                 RCC_MEMENCR_AHBSRAM1ENC_Msk          /*!< AHBSRAM1 enable */
+#define RCC_MEMENCR_AHBSRAM2ENC_Pos             (5U)
+#define RCC_MEMENCR_AHBSRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */
+#define RCC_MEMENCR_AHBSRAM2ENC                 RCC_MEMENCR_AHBSRAM2ENC_Msk          /*!< AHBSRAM2 enable */
+#define RCC_MEMENCR_BKPSRAMENC_Pos              (6U)
+#define RCC_MEMENCR_BKPSRAMENC_Msk              (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */
+#define RCC_MEMENCR_BKPSRAMENC                  RCC_MEMENCR_BKPSRAMENC_Msk           /*!< BKPSRAM enable */
+#define RCC_MEMENCR_AXISRAM1ENC_Pos             (7U)
+#define RCC_MEMENCR_AXISRAM1ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */
+#define RCC_MEMENCR_AXISRAM1ENC                 RCC_MEMENCR_AXISRAM1ENC_Msk          /*!< AXISRAM1 enable */
+#define RCC_MEMENCR_AXISRAM2ENC_Pos             (8U)
+#define RCC_MEMENCR_AXISRAM2ENC_Msk             (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */
+#define RCC_MEMENCR_AXISRAM2ENC                 RCC_MEMENCR_AXISRAM2ENC_Msk          /*!< AXISRAM2 enable */
+#define RCC_MEMENCR_FLEXRAMENC_Pos              (9U)
+#define RCC_MEMENCR_FLEXRAMENC_Msk              (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */
+#define RCC_MEMENCR_FLEXRAMENC                  RCC_MEMENCR_FLEXRAMENC_Msk           /*!< FLEXRAM enable */
+#define RCC_MEMENCR_CACHEAXIRAMENC_Pos          (10U)
+#define RCC_MEMENCR_CACHEAXIRAMENC_Msk          (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos)   /*!< 0x00000400 */
+#define RCC_MEMENCR_CACHEAXIRAMENC              RCC_MEMENCR_CACHEAXIRAMENC_Msk       /*!< CACHEAXIRAM enable */
+#define RCC_MEMENCR_VENCRAMENC_Pos              (11U)
+#define RCC_MEMENCR_VENCRAMENC_Msk              (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */
+#define RCC_MEMENCR_VENCRAMENC                  RCC_MEMENCR_VENCRAMENC_Msk           /*!< VENCRAM enable */
+#define RCC_MEMENCR_BOOTROMENC_Pos              (12U)
+#define RCC_MEMENCR_BOOTROMENC_Msk              (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */
+#define RCC_MEMENCR_BOOTROMENC                  RCC_MEMENCR_BOOTROMENC_Msk           /*!< Boot ROM enable */
+
+/*****************  Bit definition for RCC_AHB1ENCR register  *****************/
+#define RCC_AHB1ENCR_GPDMA1ENC_Pos              (4U)
+#define RCC_AHB1ENCR_GPDMA1ENC_Msk              (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */
+#define RCC_AHB1ENCR_GPDMA1ENC                  RCC_AHB1ENCR_GPDMA1ENC_Msk           /*!< GPDMA1 enable */
+#define RCC_AHB1ENCR_ADC12ENC_Pos               (5U)
+#define RCC_AHB1ENCR_ADC12ENC_Msk               (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1ENCR_ADC12ENC                   RCC_AHB1ENCR_ADC12ENC_Msk            /*!< ADC12 enable */
+
+/*****************  Bit definition for RCC_AHB2ENCR register  *****************/
+#define RCC_AHB2ENCR_RAMCFGENC_Pos              (12U)
+#define RCC_AHB2ENCR_RAMCFGENC_Msk              (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENCR_RAMCFGENC                  RCC_AHB2ENCR_RAMCFGENC_Msk           /*!< RAMCFG enable */
+#define RCC_AHB2ENCR_MDF1ENC_Pos                (16U)
+#define RCC_AHB2ENCR_MDF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos)   /*!< 0x00010000 */
+#define RCC_AHB2ENCR_MDF1ENC                    RCC_AHB2ENCR_MDF1ENC_Msk             /*!< MDF1 enable */
+#define RCC_AHB2ENCR_ADF1ENC_Pos                (17U)
+#define RCC_AHB2ENCR_ADF1ENC_Msk                (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos)   /*!< 0x00020000 */
+#define RCC_AHB2ENCR_ADF1ENC                    RCC_AHB2ENCR_ADF1ENC_Msk             /*!< ADF1 enable */
+
+/*****************  Bit definition for RCC_AHB3ENCR register  *****************/
+#define RCC_AHB3ENCR_RNGENC_Pos                 (0U)
+#define RCC_AHB3ENCR_RNGENC_Msk                 (0x1UL << RCC_AHB3ENCR_RNGENC_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENCR_RNGENC                     RCC_AHB3ENCR_RNGENC_Msk              /*!< RNG enable */
+#define RCC_AHB3ENCR_HASHENC_Pos                (1U)
+#define RCC_AHB3ENCR_HASHENC_Msk                (0x1UL << RCC_AHB3ENCR_HASHENC_Pos)   /*!< 0x00000002 */
+#define RCC_AHB3ENCR_HASHENC                    RCC_AHB3ENCR_HASHENC_Msk             /*!< HASH enable */
+#define RCC_AHB3ENCR_CRYPENC_Pos                (2U)
+#define RCC_AHB3ENCR_CRYPENC_Msk                (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos)   /*!< 0x00000004 */
+#define RCC_AHB3ENCR_CRYPENC                    RCC_AHB3ENCR_CRYPENC_Msk             /*!< CRYP enable */
+#define RCC_AHB3ENCR_SAESENC_Pos                (4U)
+#define RCC_AHB3ENCR_SAESENC_Msk                (0x1UL << RCC_AHB3ENCR_SAESENC_Pos)   /*!< 0x00000010 */
+#define RCC_AHB3ENCR_SAESENC                    RCC_AHB3ENCR_SAESENC_Msk             /*!< SAES enable */
+#define RCC_AHB3ENCR_PKAENC_Pos                 (8U)
+#define RCC_AHB3ENCR_PKAENC_Msk                 (0x1UL << RCC_AHB3ENCR_PKAENC_Pos)    /*!< 0x00000100 */
+#define RCC_AHB3ENCR_PKAENC                     RCC_AHB3ENCR_PKAENC_Msk              /*!< PKA enable */
+#define RCC_AHB3ENCR_RIFSCENC_Pos               (9U)
+#define RCC_AHB3ENCR_RIFSCENC_Msk               (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3ENCR_RIFSCENC                   RCC_AHB3ENCR_RIFSCENC_Msk            /*!< RIFSC enable */
+#define RCC_AHB3ENCR_IACENC_Pos                 (10U)
+#define RCC_AHB3ENCR_IACENC_Msk                 (0x1UL << RCC_AHB3ENCR_IACENC_Pos)    /*!< 0x00000400 */
+#define RCC_AHB3ENCR_IACENC                     RCC_AHB3ENCR_IACENC_Msk              /*!< IAC enable */
+#define RCC_AHB3ENCR_RISAFENC_Pos               (14U)
+#define RCC_AHB3ENCR_RISAFENC_Msk               (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3ENCR_RISAFENC                   RCC_AHB3ENCR_RISAFENC_Msk            /*!< RISAF enable */
+
+/*****************  Bit definition for RCC_AHB4ENCR register  *****************/
+#define RCC_AHB4ENCR_GPIOAENC_Pos               (0U)
+#define RCC_AHB4ENCR_GPIOAENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4ENCR_GPIOAENC                   RCC_AHB4ENCR_GPIOAENC_Msk            /*!< GPIO A enable */
+#define RCC_AHB4ENCR_GPIOBENC_Pos               (1U)
+#define RCC_AHB4ENCR_GPIOBENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4ENCR_GPIOBENC                   RCC_AHB4ENCR_GPIOBENC_Msk            /*!< GPIO B enable */
+#define RCC_AHB4ENCR_GPIOCENC_Pos               (2U)
+#define RCC_AHB4ENCR_GPIOCENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4ENCR_GPIOCENC                   RCC_AHB4ENCR_GPIOCENC_Msk            /*!< GPIO C enable */
+#define RCC_AHB4ENCR_GPIODENC_Pos               (3U)
+#define RCC_AHB4ENCR_GPIODENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4ENCR_GPIODENC                   RCC_AHB4ENCR_GPIODENC_Msk            /*!< GPIO D enable */
+#define RCC_AHB4ENCR_GPIOEENC_Pos               (4U)
+#define RCC_AHB4ENCR_GPIOEENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4ENCR_GPIOEENC                   RCC_AHB4ENCR_GPIOEENC_Msk            /*!< GPIO E enable */
+#define RCC_AHB4ENCR_GPIOFENC_Pos               (5U)
+#define RCC_AHB4ENCR_GPIOFENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4ENCR_GPIOFENC                   RCC_AHB4ENCR_GPIOFENC_Msk            /*!< GPIO F enable */
+#define RCC_AHB4ENCR_GPIOGENC_Pos               (6U)
+#define RCC_AHB4ENCR_GPIOGENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4ENCR_GPIOGENC                   RCC_AHB4ENCR_GPIOGENC_Msk            /*!< GPIO G enable */
+#define RCC_AHB4ENCR_GPIOHENC_Pos               (7U)
+#define RCC_AHB4ENCR_GPIOHENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4ENCR_GPIOHENC                   RCC_AHB4ENCR_GPIOHENC_Msk            /*!< GPIO H enable */
+#define RCC_AHB4ENCR_GPIONENC_Pos               (13U)
+#define RCC_AHB4ENCR_GPIONENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4ENCR_GPIONENC                   RCC_AHB4ENCR_GPIONENC_Msk            /*!< GPIO N enable */
+#define RCC_AHB4ENCR_GPIOOENC_Pos               (14U)
+#define RCC_AHB4ENCR_GPIOOENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4ENCR_GPIOOENC                   RCC_AHB4ENCR_GPIOOENC_Msk            /*!< GPIO O enable */
+#define RCC_AHB4ENCR_GPIOPENC_Pos               (15U)
+#define RCC_AHB4ENCR_GPIOPENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4ENCR_GPIOPENC                   RCC_AHB4ENCR_GPIOPENC_Msk            /*!< GPIO P enable */
+#define RCC_AHB4ENCR_GPIOQENC_Pos               (16U)
+#define RCC_AHB4ENCR_GPIOQENC_Msk               (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4ENCR_GPIOQENC                   RCC_AHB4ENCR_GPIOQENC_Msk            /*!< GPIO Q enable */
+#define RCC_AHB4ENCR_PWRENC_Pos                 (18U)
+#define RCC_AHB4ENCR_PWRENC_Msk                 (0x1UL << RCC_AHB4ENCR_PWRENC_Pos)    /*!< 0x00040000 */
+#define RCC_AHB4ENCR_PWRENC                     RCC_AHB4ENCR_PWRENC_Msk              /*!< PWR enable */
+#define RCC_AHB4ENCR_CRCENC_Pos                 (19U)
+#define RCC_AHB4ENCR_CRCENC_Msk                 (0x1UL << RCC_AHB4ENCR_CRCENC_Pos)    /*!< 0x00080000 */
+#define RCC_AHB4ENCR_CRCENC                     RCC_AHB4ENCR_CRCENC_Msk              /*!< CRC enable */
+
+/*****************  Bit definition for RCC_AHB5ENCR register  *****************/
+#define RCC_AHB5ENCR_HPDMA1ENC_Pos              (0U)
+#define RCC_AHB5ENCR_HPDMA1ENC_Msk              (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */
+#define RCC_AHB5ENCR_HPDMA1ENC                  RCC_AHB5ENCR_HPDMA1ENC_Msk           /*!< HPDMA1 enable */
+#define RCC_AHB5ENCR_DMA2DENC_Pos               (1U)
+#define RCC_AHB5ENCR_DMA2DENC_Msk               (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5ENCR_DMA2DENC                   RCC_AHB5ENCR_DMA2DENC_Msk            /*!< DMA2D enable */
+#define RCC_AHB5ENCR_JPEGENC_Pos                (3U)
+#define RCC_AHB5ENCR_JPEGENC_Msk                (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos)   /*!< 0x00000008 */
+#define RCC_AHB5ENCR_JPEGENC                    RCC_AHB5ENCR_JPEGENC_Msk             /*!< JPEG enable */
+#define RCC_AHB5ENCR_FMCENC_Pos                 (4U)
+#define RCC_AHB5ENCR_FMCENC_Msk                 (0x1UL << RCC_AHB5ENCR_FMCENC_Pos)    /*!< 0x00000010 */
+#define RCC_AHB5ENCR_FMCENC                     RCC_AHB5ENCR_FMCENC_Msk              /*!< FMC enable */
+#define RCC_AHB5ENCR_XSPI1ENC_Pos               (5U)
+#define RCC_AHB5ENCR_XSPI1ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5ENCR_XSPI1ENC                   RCC_AHB5ENCR_XSPI1ENC_Msk            /*!< XSPI1 enable */
+#define RCC_AHB5ENCR_PSSIENC_Pos                (6U)
+#define RCC_AHB5ENCR_PSSIENC_Msk                (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos)   /*!< 0x00000040 */
+#define RCC_AHB5ENCR_PSSIENC                    RCC_AHB5ENCR_PSSIENC_Msk             /*!< PSSI enable */
+#define RCC_AHB5ENCR_SDMMC2ENC_Pos              (7U)
+#define RCC_AHB5ENCR_SDMMC2ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */
+#define RCC_AHB5ENCR_SDMMC2ENC                  RCC_AHB5ENCR_SDMMC2ENC_Msk           /*!< SDMMC2 enable */
+#define RCC_AHB5ENCR_SDMMC1ENC_Pos              (8U)
+#define RCC_AHB5ENCR_SDMMC1ENC_Msk              (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */
+#define RCC_AHB5ENCR_SDMMC1ENC                  RCC_AHB5ENCR_SDMMC1ENC_Msk           /*!< SDMMC1 enable */
+#define RCC_AHB5ENCR_XSPI2ENC_Pos               (12U)
+#define RCC_AHB5ENCR_XSPI2ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5ENCR_XSPI2ENC                   RCC_AHB5ENCR_XSPI2ENC_Msk            /*!< XSPI2 enable */
+#define RCC_AHB5ENCR_XSPIMENC_Pos               (13U)
+#define RCC_AHB5ENCR_XSPIMENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5ENCR_XSPIMENC                   RCC_AHB5ENCR_XSPIMENC_Msk            /*!< XSPIM enable */
+#define RCC_AHB5ENCR_MCE1ENC_Pos                (14U)
+#define RCC_AHB5ENCR_MCE1ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos)   /*!< 0x00004000 */
+#define RCC_AHB5ENCR_MCE1ENC                    RCC_AHB5ENCR_MCE1ENC_Msk             /*!< MCE1 enable */
+#define RCC_AHB5ENCR_MCE2ENC_Pos                (15U)
+#define RCC_AHB5ENCR_MCE2ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos)   /*!< 0x00008000 */
+#define RCC_AHB5ENCR_MCE2ENC                    RCC_AHB5ENCR_MCE2ENC_Msk             /*!< MCE2 enable */
+#define RCC_AHB5ENCR_MCE3ENC_Pos                (16U)
+#define RCC_AHB5ENCR_MCE3ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos)   /*!< 0x00010000 */
+#define RCC_AHB5ENCR_MCE3ENC                    RCC_AHB5ENCR_MCE3ENC_Msk             /*!< MCE3 enable */
+#define RCC_AHB5ENCR_XSPI3ENC_Pos               (17U)
+#define RCC_AHB5ENCR_XSPI3ENC_Msk               (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5ENCR_XSPI3ENC                   RCC_AHB5ENCR_XSPI3ENC_Msk            /*!< XSPI3 enable */
+#define RCC_AHB5ENCR_MCE4ENC_Pos                (18U)
+#define RCC_AHB5ENCR_MCE4ENC_Msk                (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos)   /*!< 0x00040000 */
+#define RCC_AHB5ENCR_MCE4ENC                    RCC_AHB5ENCR_MCE4ENC_Msk             /*!< MCE4 enable */
+#define RCC_AHB5ENCR_GFXMMUENC_Pos              (19U)
+#define RCC_AHB5ENCR_GFXMMUENC_Msk              (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */
+#define RCC_AHB5ENCR_GFXMMUENC                  RCC_AHB5ENCR_GFXMMUENC_Msk           /*!< GFXMMU enable */
+#define RCC_AHB5ENCR_GPU2DENC_Pos               (20U)
+#define RCC_AHB5ENCR_GPU2DENC_Msk               (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5ENCR_GPU2DENC                   RCC_AHB5ENCR_GPU2DENC_Msk            /*!< GPU2D enable */
+#define RCC_AHB5ENCR_ETH1MACENC_Pos             (22U)
+#define RCC_AHB5ENCR_ETH1MACENC_Msk             (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */
+#define RCC_AHB5ENCR_ETH1MACENC                 RCC_AHB5ENCR_ETH1MACENC_Msk          /*!< ETH1MAC enable */
+#define RCC_AHB5ENCR_ETH1TXENC_Pos              (23U)
+#define RCC_AHB5ENCR_ETH1TXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */
+#define RCC_AHB5ENCR_ETH1TXENC                  RCC_AHB5ENCR_ETH1TXENC_Msk           /*!< ETH1TX enable */
+#define RCC_AHB5ENCR_ETH1RXENC_Pos              (24U)
+#define RCC_AHB5ENCR_ETH1RXENC_Msk              (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */
+#define RCC_AHB5ENCR_ETH1RXENC                  RCC_AHB5ENCR_ETH1RXENC_Msk           /*!< ETH1RX enable */
+#define RCC_AHB5ENCR_ETH1ENC_Pos                (25U)
+#define RCC_AHB5ENCR_ETH1ENC_Msk                (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos)   /*!< 0x02000000 */
+#define RCC_AHB5ENCR_ETH1ENC                    RCC_AHB5ENCR_ETH1ENC_Msk             /*!< ETH1 enable */
+#define RCC_AHB5ENCR_OTG1ENC_Pos                (26U)
+#define RCC_AHB5ENCR_OTG1ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos)   /*!< 0x04000000 */
+#define RCC_AHB5ENCR_OTG1ENC                    RCC_AHB5ENCR_OTG1ENC_Msk             /*!< OTG1 enable */
+#define RCC_AHB5ENCR_OTGPHY1ENC_Pos             (27U)
+#define RCC_AHB5ENCR_OTGPHY1ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */
+#define RCC_AHB5ENCR_OTGPHY1ENC                 RCC_AHB5ENCR_OTGPHY1ENC_Msk          /*!< OTGPHY1 enable */
+#define RCC_AHB5ENCR_OTGPHY2ENC_Pos             (28U)
+#define RCC_AHB5ENCR_OTGPHY2ENC_Msk             (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */
+#define RCC_AHB5ENCR_OTGPHY2ENC                 RCC_AHB5ENCR_OTGPHY2ENC_Msk          /*!< OTGPHY2 enable */
+#define RCC_AHB5ENCR_OTG2ENC_Pos                (29U)
+#define RCC_AHB5ENCR_OTG2ENC_Msk                (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos)   /*!< 0x20000000 */
+#define RCC_AHB5ENCR_OTG2ENC                    RCC_AHB5ENCR_OTG2ENC_Msk             /*!< OTG2 enable */
+#define RCC_AHB5ENCR_CACHEAXIENC_Pos            (30U)
+#define RCC_AHB5ENCR_CACHEAXIENC_Msk            (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */
+#define RCC_AHB5ENCR_CACHEAXIENC                RCC_AHB5ENCR_CACHEAXIENC_Msk         /*!< CACHEAXI enable */
+#define RCC_AHB5ENCR_NPUENC_Pos                 (31U)
+#define RCC_AHB5ENCR_NPUENC_Msk                 (0x1UL << RCC_AHB5ENCR_NPUENC_Pos)    /*!< 0x80000000 */
+#define RCC_AHB5ENCR_NPUENC                     RCC_AHB5ENCR_NPUENC_Msk              /*!< NPU enable */
+
+/****************  Bit definition for RCC_APB1ENCR1 register  *****************/
+#define RCC_APB1ENCR1_TIM2ENC_Pos               (0U)
+#define RCC_APB1ENCR1_TIM2ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1ENCR1_TIM2ENC                   RCC_APB1ENCR1_TIM2ENC_Msk            /*!< TIM2 enable */
+#define RCC_APB1ENCR1_TIM3ENC_Pos               (1U)
+#define RCC_APB1ENCR1_TIM3ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1ENCR1_TIM3ENC                   RCC_APB1ENCR1_TIM3ENC_Msk            /*!< TIM3 enable */
+#define RCC_APB1ENCR1_TIM4ENC_Pos               (2U)
+#define RCC_APB1ENCR1_TIM4ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1ENCR1_TIM4ENC                   RCC_APB1ENCR1_TIM4ENC_Msk            /*!< TIM4 enable */
+#define RCC_APB1ENCR1_TIM5ENC_Pos               (3U)
+#define RCC_APB1ENCR1_TIM5ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1ENCR1_TIM5ENC                   RCC_APB1ENCR1_TIM5ENC_Msk            /*!< TIM5 enable */
+#define RCC_APB1ENCR1_TIM6ENC_Pos               (4U)
+#define RCC_APB1ENCR1_TIM6ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1ENCR1_TIM6ENC                   RCC_APB1ENCR1_TIM6ENC_Msk            /*!< TIM6 enable */
+#define RCC_APB1ENCR1_TIM7ENC_Pos               (5U)
+#define RCC_APB1ENCR1_TIM7ENC_Msk               (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1ENCR1_TIM7ENC                   RCC_APB1ENCR1_TIM7ENC_Msk            /*!< TIM7 enable */
+#define RCC_APB1ENCR1_TIM12ENC_Pos              (6U)
+#define RCC_APB1ENCR1_TIM12ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENCR1_TIM12ENC                  RCC_APB1ENCR1_TIM12ENC_Msk           /*!< TIM12 enable */
+#define RCC_APB1ENCR1_TIM13ENC_Pos              (7U)
+#define RCC_APB1ENCR1_TIM13ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENCR1_TIM13ENC                  RCC_APB1ENCR1_TIM13ENC_Msk           /*!< TIM13 enable */
+#define RCC_APB1ENCR1_TIM14ENC_Pos              (8U)
+#define RCC_APB1ENCR1_TIM14ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR1_TIM14ENC                  RCC_APB1ENCR1_TIM14ENC_Msk           /*!< TIM14 enable */
+#define RCC_APB1ENCR1_LPTIM1ENC_Pos             (9U)
+#define RCC_APB1ENCR1_LPTIM1ENC_Msk             (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB1ENCR1_LPTIM1ENC                 RCC_APB1ENCR1_LPTIM1ENC_Msk          /*!< LPTIM1 enable */
+#define RCC_APB1ENCR1_TIM10ENC_Pos              (12U)
+#define RCC_APB1ENCR1_TIM10ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */
+#define RCC_APB1ENCR1_TIM10ENC                  RCC_APB1ENCR1_TIM10ENC_Msk           /*!< TIM10 enable */
+#define RCC_APB1ENCR1_TIM11ENC_Pos              (13U)
+#define RCC_APB1ENCR1_TIM11ENC_Msk              (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */
+#define RCC_APB1ENCR1_TIM11ENC                  RCC_APB1ENCR1_TIM11ENC_Msk           /*!< TIM11 enable */
+#define RCC_APB1ENCR1_SPI2ENC_Pos               (14U)
+#define RCC_APB1ENCR1_SPI2ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1ENCR1_SPI2ENC                   RCC_APB1ENCR1_SPI2ENC_Msk            /*!< SPI2 enable */
+#define RCC_APB1ENCR1_SPI3ENC_Pos               (15U)
+#define RCC_APB1ENCR1_SPI3ENC_Msk               (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1ENCR1_SPI3ENC                   RCC_APB1ENCR1_SPI3ENC_Msk            /*!< SPI3 enable */
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos           (16U)
+#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk           (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB1ENCR1_SPDIFRX1ENC               RCC_APB1ENCR1_SPDIFRX1ENC_Msk        /*!< SPDIFRX1 enable */
+#define RCC_APB1ENCR1_USART2ENC_Pos             (17U)
+#define RCC_APB1ENCR1_USART2ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */
+#define RCC_APB1ENCR1_USART2ENC                 RCC_APB1ENCR1_USART2ENC_Msk          /*!< USART2 enable */
+#define RCC_APB1ENCR1_USART3ENC_Pos             (18U)
+#define RCC_APB1ENCR1_USART3ENC_Msk             (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */
+#define RCC_APB1ENCR1_USART3ENC                 RCC_APB1ENCR1_USART3ENC_Msk          /*!< USART3 enable */
+#define RCC_APB1ENCR1_UART4ENC_Pos              (19U)
+#define RCC_APB1ENCR1_UART4ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENCR1_UART4ENC                  RCC_APB1ENCR1_UART4ENC_Msk           /*!< UART4 enable */
+#define RCC_APB1ENCR1_UART5ENC_Pos              (20U)
+#define RCC_APB1ENCR1_UART5ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENCR1_UART5ENC                  RCC_APB1ENCR1_UART5ENC_Msk           /*!< UART5 enable */
+#define RCC_APB1ENCR1_I2C1ENC_Pos               (21U)
+#define RCC_APB1ENCR1_I2C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1ENCR1_I2C1ENC                   RCC_APB1ENCR1_I2C1ENC_Msk            /*!< I2C1 enable */
+#define RCC_APB1ENCR1_I2C2ENC_Pos               (22U)
+#define RCC_APB1ENCR1_I2C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1ENCR1_I2C2ENC                   RCC_APB1ENCR1_I2C2ENC_Msk            /*!< I2C2 enable */
+#define RCC_APB1ENCR1_I2C3ENC_Pos               (23U)
+#define RCC_APB1ENCR1_I2C3ENC_Msk               (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1ENCR1_I2C3ENC                   RCC_APB1ENCR1_I2C3ENC_Msk            /*!< I2C3 enable */
+#define RCC_APB1ENCR1_I3C1ENC_Pos               (24U)
+#define RCC_APB1ENCR1_I3C1ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENCR1_I3C1ENC                   RCC_APB1ENCR1_I3C1ENC_Msk            /*!< I3C1 enable */
+#define RCC_APB1ENCR1_I3C2ENC_Pos               (25U)
+#define RCC_APB1ENCR1_I3C2ENC_Msk               (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1ENCR1_I3C2ENC                   RCC_APB1ENCR1_I3C2ENC_Msk            /*!< I3C2 enable */
+#define RCC_APB1ENCR1_UART7ENC_Pos              (30U)
+#define RCC_APB1ENCR1_UART7ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENCR1_UART7ENC                  RCC_APB1ENCR1_UART7ENC_Msk           /*!< UART7 enable */
+#define RCC_APB1ENCR1_UART8ENC_Pos              (31U)
+#define RCC_APB1ENCR1_UART8ENC_Msk              (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENCR1_UART8ENC                  RCC_APB1ENCR1_UART8ENC_Msk           /*!< UART8 enable */
+
+/****************  Bit definition for RCC_APB1ENCR2 register  *****************/
+#define RCC_APB1ENCR2_MDIOSENC_Pos              (5U)
+#define RCC_APB1ENCR2_MDIOSENC_Msk              (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENCR2_MDIOSENC                  RCC_APB1ENCR2_MDIOSENC_Msk           /*!< MDIOS enable */
+#define RCC_APB1ENCR2_FDCANENC_Pos              (8U)
+#define RCC_APB1ENCR2_FDCANENC_Msk              (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENCR2_FDCANENC                  RCC_APB1ENCR2_FDCANENC_Msk           /*!< FDCAN enable */
+#define RCC_APB1ENCR2_UCPD1ENC_Pos              (18U)
+#define RCC_APB1ENCR2_UCPD1ENC_Msk              (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENCR2_UCPD1ENC                  RCC_APB1ENCR2_UCPD1ENC_Msk           /*!< UCPD1 enable */
+
+/*****************  Bit definition for RCC_APB2ENCR register  *****************/
+#define RCC_APB2ENCR_TIM1ENC_Pos                (0U)
+#define RCC_APB2ENCR_TIM1ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos)   /*!< 0x00000001 */
+#define RCC_APB2ENCR_TIM1ENC                    RCC_APB2ENCR_TIM1ENC_Msk             /*!< TIM1 enable */
+#define RCC_APB2ENCR_TIM8ENC_Pos                (1U)
+#define RCC_APB2ENCR_TIM8ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB2ENCR_TIM8ENC                    RCC_APB2ENCR_TIM8ENC_Msk             /*!< TIM8 enable */
+#define RCC_APB2ENCR_USART1ENC_Pos              (4U)
+#define RCC_APB2ENCR_USART1ENC_Msk              (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENCR_USART1ENC                  RCC_APB2ENCR_USART1ENC_Msk           /*!< USART1 enable */
+#define RCC_APB2ENCR_USART6ENC_Pos              (5U)
+#define RCC_APB2ENCR_USART6ENC_Msk              (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENCR_USART6ENC                  RCC_APB2ENCR_USART6ENC_Msk           /*!< USART6 enable */
+#define RCC_APB2ENCR_UART9ENC_Pos               (6U)
+#define RCC_APB2ENCR_UART9ENC_Msk               (0x1UL << RCC_APB2ENCR_UART9ENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2ENCR_UART9ENC                   RCC_APB2ENCR_UART9ENC_Msk            /*!< UART9 enable */
+#define RCC_APB2ENCR_USART10ENC_Pos             (7U)
+#define RCC_APB2ENCR_USART10ENC_Msk             (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */
+#define RCC_APB2ENCR_USART10ENC                 RCC_APB2ENCR_USART10ENC_Msk          /*!< USART10 enable */
+#define RCC_APB2ENCR_SPI1ENC_Pos                (12U)
+#define RCC_APB2ENCR_SPI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENCR_SPI1ENC                    RCC_APB2ENCR_SPI1ENC_Msk             /*!< SPI1 enable */
+#define RCC_APB2ENCR_SPI4ENC_Pos                (13U)
+#define RCC_APB2ENCR_SPI4ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB2ENCR_SPI4ENC                    RCC_APB2ENCR_SPI4ENC_Msk             /*!< SPI4 enable */
+#define RCC_APB2ENCR_TIM18ENC_Pos               (15U)
+#define RCC_APB2ENCR_TIM18ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2ENCR_TIM18ENC                   RCC_APB2ENCR_TIM18ENC_Msk            /*!< TIM18 enable */
+#define RCC_APB2ENCR_TIM15ENC_Pos               (16U)
+#define RCC_APB2ENCR_TIM15ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2ENCR_TIM15ENC                   RCC_APB2ENCR_TIM15ENC_Msk            /*!< TIM15 enable */
+#define RCC_APB2ENCR_TIM16ENC_Pos               (17U)
+#define RCC_APB2ENCR_TIM16ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2ENCR_TIM16ENC                   RCC_APB2ENCR_TIM16ENC_Msk            /*!< TIM16 enable */
+#define RCC_APB2ENCR_TIM17ENC_Pos               (18U)
+#define RCC_APB2ENCR_TIM17ENC_Msk               (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2ENCR_TIM17ENC                   RCC_APB2ENCR_TIM17ENC_Msk            /*!< TIM17 enable */
+#define RCC_APB2ENCR_TIM9ENC_Pos                (19U)
+#define RCC_APB2ENCR_TIM9ENC_Msk                (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB2ENCR_TIM9ENC                    RCC_APB2ENCR_TIM9ENC_Msk             /*!< TIM9 enable */
+#define RCC_APB2ENCR_SPI5ENC_Pos                (20U)
+#define RCC_APB2ENCR_SPI5ENC_Msk                (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB2ENCR_SPI5ENC                    RCC_APB2ENCR_SPI5ENC_Msk             /*!< SPI5 enable */
+#define RCC_APB2ENCR_SAI1ENC_Pos                (21U)
+#define RCC_APB2ENCR_SAI1ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos)   /*!< 0x00200000 */
+#define RCC_APB2ENCR_SAI1ENC                    RCC_APB2ENCR_SAI1ENC_Msk             /*!< SAI1 enable */
+#define RCC_APB2ENCR_SAI2ENC_Pos                (22U)
+#define RCC_APB2ENCR_SAI2ENC_Msk                (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos)   /*!< 0x00400000 */
+#define RCC_APB2ENCR_SAI2ENC                    RCC_APB2ENCR_SAI2ENC_Msk             /*!< SAI2 enable */
+
+/*****************  Bit definition for RCC_APB3ENCR register  *****************/
+#define RCC_APB3ENCR_DFTENC_Pos                 (2U)
+#define RCC_APB3ENCR_DFTENC_Msk                 (0x1UL << RCC_APB3ENCR_DFTENC_Pos)    /*!< 0x00000004 */
+#define RCC_APB3ENCR_DFTENC                     RCC_APB3ENCR_DFTENC_Msk              /*!< DFT enable */
+
+/****************  Bit definition for RCC_APB4ENCR1 register  *****************/
+#define RCC_APB4ENCR1_HDPENC_Pos                (2U)
+#define RCC_APB4ENCR1_HDPENC_Msk                (0x1UL << RCC_APB4ENCR1_HDPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR1_HDPENC                    RCC_APB4ENCR1_HDPENC_Msk             /*!< HDP enable */
+#define RCC_APB4ENCR1_LPUART1ENC_Pos            (3U)
+#define RCC_APB4ENCR1_LPUART1ENC_Msk            (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENCR1_LPUART1ENC                RCC_APB4ENCR1_LPUART1ENC_Msk         /*!< LPUART1 enable */
+#define RCC_APB4ENCR1_SPI6ENC_Pos               (5U)
+#define RCC_APB4ENCR1_SPI6ENC_Msk               (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4ENCR1_SPI6ENC                   RCC_APB4ENCR1_SPI6ENC_Msk            /*!< SPI6 enable */
+#define RCC_APB4ENCR1_I2C4ENC_Pos               (7U)
+#define RCC_APB4ENCR1_I2C4ENC_Msk               (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4ENCR1_I2C4ENC                   RCC_APB4ENCR1_I2C4ENC_Msk            /*!< I2C4 enable */
+#define RCC_APB4ENCR1_LPTIM2ENC_Pos             (9U)
+#define RCC_APB4ENCR1_LPTIM2ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */
+#define RCC_APB4ENCR1_LPTIM2ENC                 RCC_APB4ENCR1_LPTIM2ENC_Msk          /*!< LPTIM2 enable */
+#define RCC_APB4ENCR1_LPTIM3ENC_Pos             (10U)
+#define RCC_APB4ENCR1_LPTIM3ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */
+#define RCC_APB4ENCR1_LPTIM3ENC                 RCC_APB4ENCR1_LPTIM3ENC_Msk          /*!< LPTIM3 enable */
+#define RCC_APB4ENCR1_LPTIM4ENC_Pos             (11U)
+#define RCC_APB4ENCR1_LPTIM4ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */
+#define RCC_APB4ENCR1_LPTIM4ENC                 RCC_APB4ENCR1_LPTIM4ENC_Msk          /*!< LPTIM4 enable */
+#define RCC_APB4ENCR1_LPTIM5ENC_Pos             (12U)
+#define RCC_APB4ENCR1_LPTIM5ENC_Msk             (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */
+#define RCC_APB4ENCR1_LPTIM5ENC                 RCC_APB4ENCR1_LPTIM5ENC_Msk          /*!< LPTIM5 enable */
+#define RCC_APB4ENCR1_VREFBUFENC_Pos            (15U)
+#define RCC_APB4ENCR1_VREFBUFENC_Msk            (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENCR1_VREFBUFENC                RCC_APB4ENCR1_VREFBUFENC_Msk         /*!< VREFBUF enable */
+#define RCC_APB4ENCR1_RTCENC_Pos                (16U)
+#define RCC_APB4ENCR1_RTCENC_Msk                (0x1UL << RCC_APB4ENCR1_RTCENC_Pos)   /*!< 0x00010000 */
+#define RCC_APB4ENCR1_RTCENC                    RCC_APB4ENCR1_RTCENC_Msk             /*!< RTC enable */
+#define RCC_APB4ENCR1_RTCAPBENC_Pos             (17U)
+#define RCC_APB4ENCR1_RTCAPBENC_Msk             (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */
+#define RCC_APB4ENCR1_RTCAPBENC                 RCC_APB4ENCR1_RTCAPBENC_Msk          /*!< RTCAPB enable */
+
+/****************  Bit definition for RCC_APB4ENCR2 register  *****************/
+#define RCC_APB4ENCR2_SYSCFGENC_Pos             (0U)
+#define RCC_APB4ENCR2_SYSCFGENC_Msk             (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */
+#define RCC_APB4ENCR2_SYSCFGENC                 RCC_APB4ENCR2_SYSCFGENC_Msk          /*!< SYSCFG enable */
+#define RCC_APB4ENCR2_BSECENC_Pos               (1U)
+#define RCC_APB4ENCR2_BSECENC_Msk               (0x1UL << RCC_APB4ENCR2_BSECENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4ENCR2_BSECENC                   RCC_APB4ENCR2_BSECENC_Msk            /*!< BSEC enable */
+#define RCC_APB4ENCR2_DTSENC_Pos                (2U)
+#define RCC_APB4ENCR2_DTSENC_Msk                (0x1UL << RCC_APB4ENCR2_DTSENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB4ENCR2_DTSENC                    RCC_APB4ENCR2_DTSENC_Msk             /*!< DTS enable */
+
+/*****************  Bit definition for RCC_APB5ENCR register  *****************/
+#define RCC_APB5ENCR_LTDCENC_Pos                (1U)
+#define RCC_APB5ENCR_LTDCENC_Msk                (0x1UL << RCC_APB5ENCR_LTDCENC_Pos)   /*!< 0x00000002 */
+#define RCC_APB5ENCR_LTDCENC                    RCC_APB5ENCR_LTDCENC_Msk             /*!< LTDC enable */
+#define RCC_APB5ENCR_DCMIPPENC_Pos              (2U)
+#define RCC_APB5ENCR_DCMIPPENC_Msk              (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB5ENCR_DCMIPPENC                  RCC_APB5ENCR_DCMIPPENC_Msk           /*!< DCMIPP enable */
+#define RCC_APB5ENCR_GFXTIMENC_Pos              (4U)
+#define RCC_APB5ENCR_GFXTIMENC_Msk              (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */
+#define RCC_APB5ENCR_GFXTIMENC                  RCC_APB5ENCR_GFXTIMENC_Msk           /*!< GFXTIM enable */
+#define RCC_APB5ENCR_VENCENC_Pos                (5U)
+#define RCC_APB5ENCR_VENCENC_Msk                (0x1UL << RCC_APB5ENCR_VENCENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB5ENCR_VENCENC                    RCC_APB5ENCR_VENCENC_Msk             /*!< VENC enable */
+#define RCC_APB5ENCR_CSIENC_Pos                 (6U)
+#define RCC_APB5ENCR_CSIENC_Msk                 (0x1UL << RCC_APB5ENCR_CSIENC_Pos)    /*!< 0x00000040 */
+#define RCC_APB5ENCR_CSIENC                     RCC_APB5ENCR_CSIENC_Msk              /*!< CSI enable */
+
+/****************  Bit definition for RCC_BUSLPENCR register  *****************/
+#define RCC_BUSLPENCR_ACLKNLPENC_Pos            (0U)
+#define RCC_BUSLPENCR_ACLKNLPENC_Msk            (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */
+#define RCC_BUSLPENCR_ACLKNLPENC                RCC_BUSLPENCR_ACLKNLPENC_Msk         /*!< ACLKN enable in Sleep mode */
+#define RCC_BUSLPENCR_ACLKNCLPENC_Pos           (1U)
+#define RCC_BUSLPENCR_ACLKNCLPENC_Msk           (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_BUSLPENCR_ACLKNCLPENC               RCC_BUSLPENCR_ACLKNCLPENC_Msk        /*!< ACLKNC enable in Sleep mode */
+
+/****************  Bit definition for RCC_MISCLPENCR register  ****************/
+#define RCC_MISCLPENCR_DBGLPENC_Pos             (0U)
+#define RCC_MISCLPENCR_DBGLPENC_Msk             (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_MISCLPENCR_DBGLPENC                 RCC_MISCLPENCR_DBGLPENC_Msk          /*!< DBG enable in Sleep mode */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos     (3U)
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk     (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos)        /*!< 0x00000008 */
+#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC         RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk  /*!< XSPIPHYCOMP enable in Sleep mode */
+#define RCC_MISCLPENCR_PERLPENC_Pos             (6U)
+#define RCC_MISCLPENCR_PERLPENC_Msk             (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */
+#define RCC_MISCLPENCR_PERLPENC                 RCC_MISCLPENCR_PERLPENC_Msk          /*!< PER enable in Sleep mode */
+
+/****************  Bit definition for RCC_MEMLPENCR register  *****************/
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos         (0U)
+#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos)    /*!< 0x00000001 */
+#define RCC_MEMLPENCR_AXISRAM3LPENC             RCC_MEMLPENCR_AXISRAM3LPENC_Msk      /*!< AXISRAM3 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos         (1U)
+#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos)    /*!< 0x00000002 */
+#define RCC_MEMLPENCR_AXISRAM4LPENC             RCC_MEMLPENCR_AXISRAM4LPENC_Msk      /*!< AXISRAM4 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos         (2U)
+#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos)    /*!< 0x00000004 */
+#define RCC_MEMLPENCR_AXISRAM5LPENC             RCC_MEMLPENCR_AXISRAM5LPENC_Msk      /*!< AXISRAM5 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos         (3U)
+#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos)    /*!< 0x00000008 */
+#define RCC_MEMLPENCR_AXISRAM6LPENC             RCC_MEMLPENCR_AXISRAM6LPENC_Msk      /*!< AXISRAM6 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos         (4U)
+#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos)    /*!< 0x00000010 */
+#define RCC_MEMLPENCR_AHBSRAM1LPENC             RCC_MEMLPENCR_AHBSRAM1LPENC_Msk      /*!< AHBSRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos         (5U)
+#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos)    /*!< 0x00000020 */
+#define RCC_MEMLPENCR_AHBSRAM2LPENC             RCC_MEMLPENCR_AHBSRAM2LPENC_Msk      /*!< AHBSRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos          (6U)
+#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos)   /*!< 0x00000040 */
+#define RCC_MEMLPENCR_BKPSRAMLPENC              RCC_MEMLPENCR_BKPSRAMLPENC_Msk       /*!< BKPSRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos         (7U)
+#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_MEMLPENCR_AXISRAM1LPENC             RCC_MEMLPENCR_AXISRAM1LPENC_Msk      /*!< AXISRAM1 enable in Sleep mode */
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos         (8U)
+#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk         (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos)    /*!< 0x00000100 */
+#define RCC_MEMLPENCR_AXISRAM2LPENC             RCC_MEMLPENCR_AXISRAM2LPENC_Msk      /*!< AXISRAM2 enable in Sleep mode */
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos          (9U)
+#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos)   /*!< 0x00000200 */
+#define RCC_MEMLPENCR_FLEXRAMLPENC              RCC_MEMLPENCR_FLEXRAMLPENC_Msk       /*!< FLEXRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos      (10U)
+#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk      (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos)       /*!< 0x00000400 */
+#define RCC_MEMLPENCR_CACHEAXIRAMLPENC          RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk   /*!< CACHEAXIRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_VENCRAMLPENC_Pos          (11U)
+#define RCC_MEMLPENCR_VENCRAMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos)   /*!< 0x00000800 */
+#define RCC_MEMLPENCR_VENCRAMLPENC              RCC_MEMLPENCR_VENCRAMLPENC_Msk       /*!< VENCRAM enable in Sleep mode */
+#define RCC_MEMLPENCR_BOOTROMLPENC_Pos          (12U)
+#define RCC_MEMLPENCR_BOOTROMLPENC_Msk          (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_MEMLPENCR_BOOTROMLPENC              RCC_MEMLPENCR_BOOTROMLPENC_Msk       /*!< Boot ROM enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB1LPENCR register  ****************/
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos          (4U)
+#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk          (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1LPENCR_GPDMA1LPENC              RCC_AHB1LPENCR_GPDMA1LPENC_Msk       /*!< GPDMA1 enable in Sleep mode */
+#define RCC_AHB1LPENCR_ADC12LPENC_Pos           (5U)
+#define RCC_AHB1LPENCR_ADC12LPENC_Msk           (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB1LPENCR_ADC12LPENC               RCC_AHB1LPENCR_ADC12LPENC_Msk        /*!< ADC12 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB2LPENCR register  ****************/
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos          (12U)
+#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk          (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos)   /*!< 0x00001000 */
+#define RCC_AHB2LPENCR_RAMCFGLPENC              RCC_AHB2LPENCR_RAMCFGLPENC_Msk       /*!< RAMCFG enable in Sleep mode */
+#define RCC_AHB2LPENCR_MDF1LPENC_Pos            (16U)
+#define RCC_AHB2LPENCR_MDF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */
+#define RCC_AHB2LPENCR_MDF1LPENC                RCC_AHB2LPENCR_MDF1LPENC_Msk         /*!< MDF1 enable in Sleep mode */
+#define RCC_AHB2LPENCR_ADF1LPENC_Pos            (17U)
+#define RCC_AHB2LPENCR_ADF1LPENC_Msk            (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */
+#define RCC_AHB2LPENCR_ADF1LPENC                RCC_AHB2LPENCR_ADF1LPENC_Msk         /*!< ADF1 enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB3LPENCR register  ****************/
+#define RCC_AHB3LPENCR_RNGLPENC_Pos             (0U)
+#define RCC_AHB3LPENCR_RNGLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */
+#define RCC_AHB3LPENCR_RNGLPENC                 RCC_AHB3LPENCR_RNGLPENC_Msk          /*!< RNG enable in Sleep mode */
+#define RCC_AHB3LPENCR_HASHLPENC_Pos            (1U)
+#define RCC_AHB3LPENCR_HASHLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */
+#define RCC_AHB3LPENCR_HASHLPENC                RCC_AHB3LPENCR_HASHLPENC_Msk         /*!< HASH enable in Sleep mode */
+#define RCC_AHB3LPENCR_CRYPLPENC_Pos            (2U)
+#define RCC_AHB3LPENCR_CRYPLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */
+#define RCC_AHB3LPENCR_CRYPLPENC                RCC_AHB3LPENCR_CRYPLPENC_Msk         /*!< CRYP enable in Sleep mode */
+#define RCC_AHB3LPENCR_SAESLPENC_Pos            (4U)
+#define RCC_AHB3LPENCR_SAESLPENC_Msk            (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */
+#define RCC_AHB3LPENCR_SAESLPENC                RCC_AHB3LPENCR_SAESLPENC_Msk         /*!< SAES enable in Sleep mode */
+#define RCC_AHB3LPENCR_PKALPENC_Pos             (8U)
+#define RCC_AHB3LPENCR_PKALPENC_Msk             (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */
+#define RCC_AHB3LPENCR_PKALPENC                 RCC_AHB3LPENCR_PKALPENC_Msk          /*!< PKA enable in Sleep mode */
+#define RCC_AHB3LPENCR_RIFSCLPENC_Pos           (9U)
+#define RCC_AHB3LPENCR_RIFSCLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos)  /*!< 0x00000200 */
+#define RCC_AHB3LPENCR_RIFSCLPENC               RCC_AHB3LPENCR_RIFSCLPENC_Msk        /*!< RIFSC enable in Sleep mode */
+#define RCC_AHB3LPENCR_IACLPENC_Pos             (10U)
+#define RCC_AHB3LPENCR_IACLPENC_Msk             (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */
+#define RCC_AHB3LPENCR_IACLPENC                 RCC_AHB3LPENCR_IACLPENC_Msk          /*!< IAC enable in Sleep mode */
+#define RCC_AHB3LPENCR_RISAFLPENC_Pos           (14U)
+#define RCC_AHB3LPENCR_RISAFLPENC_Msk           (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB3LPENCR_RISAFLPENC               RCC_AHB3LPENCR_RISAFLPENC_Msk        /*!< RISAF enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB4LPENCR register  ****************/
+#define RCC_AHB4LPENCR_GPIOALPENC_Pos           (0U)
+#define RCC_AHB4LPENCR_GPIOALPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos)  /*!< 0x00000001 */
+#define RCC_AHB4LPENCR_GPIOALPENC               RCC_AHB4LPENCR_GPIOALPENC_Msk        /*!< GPIO A enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOBLPENC_Pos           (1U)
+#define RCC_AHB4LPENCR_GPIOBLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB4LPENCR_GPIOBLPENC               RCC_AHB4LPENCR_GPIOBLPENC_Msk        /*!< GPIO B enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOCLPENC_Pos           (2U)
+#define RCC_AHB4LPENCR_GPIOCLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos)  /*!< 0x00000004 */
+#define RCC_AHB4LPENCR_GPIOCLPENC               RCC_AHB4LPENCR_GPIOCLPENC_Msk        /*!< GPIO C enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIODLPENC_Pos           (3U)
+#define RCC_AHB4LPENCR_GPIODLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos)  /*!< 0x00000008 */
+#define RCC_AHB4LPENCR_GPIODLPENC               RCC_AHB4LPENCR_GPIODLPENC_Msk        /*!< GPIO D enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOELPENC_Pos           (4U)
+#define RCC_AHB4LPENCR_GPIOELPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos)  /*!< 0x00000010 */
+#define RCC_AHB4LPENCR_GPIOELPENC               RCC_AHB4LPENCR_GPIOELPENC_Msk        /*!< GPIO E enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOFLPENC_Pos           (5U)
+#define RCC_AHB4LPENCR_GPIOFLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB4LPENCR_GPIOFLPENC               RCC_AHB4LPENCR_GPIOFLPENC_Msk        /*!< GPIO F enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOGLPENC_Pos           (6U)
+#define RCC_AHB4LPENCR_GPIOGLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos)  /*!< 0x00000040 */
+#define RCC_AHB4LPENCR_GPIOGLPENC               RCC_AHB4LPENCR_GPIOGLPENC_Msk        /*!< GPIO G enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOHLPENC_Pos           (7U)
+#define RCC_AHB4LPENCR_GPIOHLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos)  /*!< 0x00000080 */
+#define RCC_AHB4LPENCR_GPIOHLPENC               RCC_AHB4LPENCR_GPIOHLPENC_Msk        /*!< GPIO H enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIONLPENC_Pos           (13U)
+#define RCC_AHB4LPENCR_GPIONLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB4LPENCR_GPIONLPENC               RCC_AHB4LPENCR_GPIONLPENC_Msk        /*!< GPIO N enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOOLPENC_Pos           (14U)
+#define RCC_AHB4LPENCR_GPIOOLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos)  /*!< 0x00004000 */
+#define RCC_AHB4LPENCR_GPIOOLPENC               RCC_AHB4LPENCR_GPIOOLPENC_Msk        /*!< GPIO O enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOPLPENC_Pos           (15U)
+#define RCC_AHB4LPENCR_GPIOPLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos)  /*!< 0x00008000 */
+#define RCC_AHB4LPENCR_GPIOPLPENC               RCC_AHB4LPENCR_GPIOPLPENC_Msk        /*!< GPIO P enable in Sleep mode */
+#define RCC_AHB4LPENCR_GPIOQLPENC_Pos           (16U)
+#define RCC_AHB4LPENCR_GPIOQLPENC_Msk           (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos)  /*!< 0x00010000 */
+#define RCC_AHB4LPENCR_GPIOQLPENC               RCC_AHB4LPENCR_GPIOQLPENC_Msk        /*!< GPIO Q enable in Sleep mode */
+#define RCC_AHB4LPENCR_PWRLPENC_Pos             (18U)
+#define RCC_AHB4LPENCR_PWRLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */
+#define RCC_AHB4LPENCR_PWRLPENC                 RCC_AHB4LPENCR_PWRLPENC_Msk          /*!< PWR enable in Sleep mode */
+#define RCC_AHB4LPENCR_CRCLPENC_Pos             (19U)
+#define RCC_AHB4LPENCR_CRCLPENC_Msk             (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */
+#define RCC_AHB4LPENCR_CRCLPENC                 RCC_AHB4LPENCR_CRCLPENC_Msk          /*!< CRC enable in Sleep mode */
+
+/****************  Bit definition for RCC_AHB5LPENCR register  ****************/
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos          (0U)
+#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos)   /*!< 0x00000001 */
+#define RCC_AHB5LPENCR_HPDMA1LPENC              RCC_AHB5LPENCR_HPDMA1LPENC_Msk       /*!< HPDMA1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_DMA2DLPENC_Pos           (1U)
+#define RCC_AHB5LPENCR_DMA2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_AHB5LPENCR_DMA2DLPENC               RCC_AHB5LPENCR_DMA2DLPENC_Msk        /*!< DMA2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_JPEGLPENC_Pos            (3U)
+#define RCC_AHB5LPENCR_JPEGLPENC_Msk            (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */
+#define RCC_AHB5LPENCR_JPEGLPENC                RCC_AHB5LPENCR_JPEGLPENC_Msk         /*!< JPEG enable in Sleep mode */
+#define RCC_AHB5LPENCR_FMCLPENC_Pos             (4U)
+#define RCC_AHB5LPENCR_FMCLPENC_Msk             (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */
+#define RCC_AHB5LPENCR_FMCLPENC                 RCC_AHB5LPENCR_FMCLPENC_Msk          /*!< FMC enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI1LPENC_Pos           (5U)
+#define RCC_AHB5LPENCR_XSPI1LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_AHB5LPENCR_XSPI1LPENC               RCC_AHB5LPENCR_XSPI1LPENC_Msk        /*!< XSPI1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_PSSILPENC_Pos            (6U)
+#define RCC_AHB5LPENCR_PSSILPENC_Msk            (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */
+#define RCC_AHB5LPENCR_PSSILPENC                RCC_AHB5LPENCR_PSSILPENC_Msk         /*!< PSSI enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos          (7U)
+#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_AHB5LPENCR_SDMMC2LPENC              RCC_AHB5LPENCR_SDMMC2LPENC_Msk       /*!< SDMMC2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos          (8U)
+#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk          (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_AHB5LPENCR_SDMMC1LPENC              RCC_AHB5LPENCR_SDMMC1LPENC_Msk       /*!< SDMMC1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI2LPENC_Pos           (12U)
+#define RCC_AHB5LPENCR_XSPI2LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos)  /*!< 0x00001000 */
+#define RCC_AHB5LPENCR_XSPI2LPENC               RCC_AHB5LPENCR_XSPI2LPENC_Msk        /*!< XSPI2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPIMLPENC_Pos           (13U)
+#define RCC_AHB5LPENCR_XSPIMLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos)  /*!< 0x00002000 */
+#define RCC_AHB5LPENCR_XSPIMLPENC               RCC_AHB5LPENCR_XSPIMLPENC_Msk        /*!< XSPIM enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE1LPENC_Pos            (14U)
+#define RCC_AHB5LPENCR_MCE1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */
+#define RCC_AHB5LPENCR_MCE1LPENC                RCC_AHB5LPENCR_MCE1LPENC_Msk         /*!< MCE1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE2LPENC_Pos            (15U)
+#define RCC_AHB5LPENCR_MCE2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */
+#define RCC_AHB5LPENCR_MCE2LPENC                RCC_AHB5LPENCR_MCE2LPENC_Msk         /*!< MCE2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE3LPENC_Pos            (16U)
+#define RCC_AHB5LPENCR_MCE3LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */
+#define RCC_AHB5LPENCR_MCE3LPENC                RCC_AHB5LPENCR_MCE3LPENC_Msk         /*!< MCE3 enable in Sleep mode */
+#define RCC_AHB5LPENCR_XSPI3LPENC_Pos           (17U)
+#define RCC_AHB5LPENCR_XSPI3LPENC_Msk           (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_AHB5LPENCR_XSPI3LPENC               RCC_AHB5LPENCR_XSPI3LPENC_Msk        /*!< XSPI3 enable in Sleep mode */
+#define RCC_AHB5LPENCR_MCE4LPENC_Pos            (18U)
+#define RCC_AHB5LPENCR_MCE4LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */
+#define RCC_AHB5LPENCR_MCE4LPENC                RCC_AHB5LPENCR_MCE4LPENC_Msk         /*!< MCE4 enable in Sleep mode */
+#define RCC_AHB5LPENCR_GFXMMULPENC_Pos          (19U)
+#define RCC_AHB5LPENCR_GFXMMULPENC_Msk          (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos)   /*!< 0x00080000 */
+#define RCC_AHB5LPENCR_GFXMMULPENC              RCC_AHB5LPENCR_GFXMMULPENC_Msk       /*!< GFXMMU enable in Sleep mode */
+#define RCC_AHB5LPENCR_GPU2DLPENC_Pos           (20U)
+#define RCC_AHB5LPENCR_GPU2DLPENC_Msk           (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos)  /*!< 0x00100000 */
+#define RCC_AHB5LPENCR_GPU2DLPENC               RCC_AHB5LPENCR_GPU2DLPENC_Msk        /*!< GPU2D enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos         (22U)
+#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk         (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos)    /*!< 0x00400000 */
+#define RCC_AHB5LPENCR_ETH1MACLPENC             RCC_AHB5LPENCR_ETH1MACLPENC_Msk      /*!< ETH1MAC enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos          (23U)
+#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos)   /*!< 0x00800000 */
+#define RCC_AHB5LPENCR_ETH1TXLPENC              RCC_AHB5LPENCR_ETH1TXLPENC_Msk       /*!< ETH1TX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos          (24U)
+#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk          (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos)   /*!< 0x01000000 */
+#define RCC_AHB5LPENCR_ETH1RXLPENC              RCC_AHB5LPENCR_ETH1RXLPENC_Msk       /*!< ETH1RX enable in Sleep mode */
+#define RCC_AHB5LPENCR_ETH1LPENC_Pos            (25U)
+#define RCC_AHB5LPENCR_ETH1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */
+#define RCC_AHB5LPENCR_ETH1LPENC                RCC_AHB5LPENCR_ETH1LPENC_Msk         /*!< ETH1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG1LPENC_Pos            (26U)
+#define RCC_AHB5LPENCR_OTG1LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */
+#define RCC_AHB5LPENCR_OTG1LPENC                RCC_AHB5LPENCR_OTG1LPENC_Msk         /*!< OTG1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos         (27U)
+#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos)    /*!< 0x08000000 */
+#define RCC_AHB5LPENCR_OTGPHY1LPENC             RCC_AHB5LPENCR_OTGPHY1LPENC_Msk      /*!< OTGPHY1 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos         (28U)
+#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk         (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos)    /*!< 0x10000000 */
+#define RCC_AHB5LPENCR_OTGPHY2LPENC             RCC_AHB5LPENCR_OTGPHY2LPENC_Msk      /*!< OTGPHY2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_OTG2LPENC_Pos            (29U)
+#define RCC_AHB5LPENCR_OTG2LPENC_Msk            (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */
+#define RCC_AHB5LPENCR_OTG2LPENC                RCC_AHB5LPENCR_OTG2LPENC_Msk         /*!< OTG2 enable in Sleep mode */
+#define RCC_AHB5LPENCR_CACHEAXILPENC_Pos        (30U)
+#define RCC_AHB5LPENCR_CACHEAXILPENC_Msk        (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos)     /*!< 0x40000000 */
+#define RCC_AHB5LPENCR_CACHEAXILPENC            RCC_AHB5LPENCR_CACHEAXILPENC_Msk     /*!< CACHEAXI enable in Sleep mode */
+#define RCC_AHB5LPENCR_NPULPENC_Pos             (31U)
+#define RCC_AHB5LPENCR_NPULPENC_Msk             (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */
+#define RCC_AHB5LPENCR_NPULPENC                 RCC_AHB5LPENCR_NPULPENC_Msk          /*!< NPU enable in Sleep mode */
+
+/***************  Bit definition for RCC_APB1LPENCR1 register  ****************/
+#define RCC_APB1LPENCR1_TIM2LPENC_Pos           (0U)
+#define RCC_APB1LPENCR1_TIM2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos)  /*!< 0x00000001 */
+#define RCC_APB1LPENCR1_TIM2LPENC               RCC_APB1LPENCR1_TIM2LPENC_Msk        /*!< TIM2 enable */
+#define RCC_APB1LPENCR1_TIM3LPENC_Pos           (1U)
+#define RCC_APB1LPENCR1_TIM3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB1LPENCR1_TIM3LPENC               RCC_APB1LPENCR1_TIM3LPENC_Msk        /*!< TIM3 enable */
+#define RCC_APB1LPENCR1_TIM4LPENC_Pos           (2U)
+#define RCC_APB1LPENCR1_TIM4LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos)  /*!< 0x00000004 */
+#define RCC_APB1LPENCR1_TIM4LPENC               RCC_APB1LPENCR1_TIM4LPENC_Msk        /*!< TIM4 enable */
+#define RCC_APB1LPENCR1_TIM5LPENC_Pos           (3U)
+#define RCC_APB1LPENCR1_TIM5LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos)  /*!< 0x00000008 */
+#define RCC_APB1LPENCR1_TIM5LPENC               RCC_APB1LPENCR1_TIM5LPENC_Msk        /*!< TIM5 enable */
+#define RCC_APB1LPENCR1_TIM6LPENC_Pos           (4U)
+#define RCC_APB1LPENCR1_TIM6LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos)  /*!< 0x00000010 */
+#define RCC_APB1LPENCR1_TIM6LPENC               RCC_APB1LPENCR1_TIM6LPENC_Msk        /*!< TIM6 enable */
+#define RCC_APB1LPENCR1_TIM7LPENC_Pos           (5U)
+#define RCC_APB1LPENCR1_TIM7LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB1LPENCR1_TIM7LPENC               RCC_APB1LPENCR1_TIM7LPENC_Msk        /*!< TIM7 enable */
+#define RCC_APB1LPENCR1_TIM12LPENC_Pos          (6U)
+#define RCC_APB1LPENCR1_TIM12LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos)   /*!< 0x00000040 */
+#define RCC_APB1LPENCR1_TIM12LPENC              RCC_APB1LPENCR1_TIM12LPENC_Msk       /*!< TIM12 enable */
+#define RCC_APB1LPENCR1_TIM13LPENC_Pos          (7U)
+#define RCC_APB1LPENCR1_TIM13LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos)   /*!< 0x00000080 */
+#define RCC_APB1LPENCR1_TIM13LPENC              RCC_APB1LPENCR1_TIM13LPENC_Msk       /*!< TIM13 enable */
+#define RCC_APB1LPENCR1_TIM14LPENC_Pos          (8U)
+#define RCC_APB1LPENCR1_TIM14LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR1_TIM14LPENC              RCC_APB1LPENCR1_TIM14LPENC_Msk       /*!< TIM14 enable */
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos         (9U)
+#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB1LPENCR1_LPTIM1LPENC             RCC_APB1LPENCR1_LPTIM1LPENC_Msk      /*!< LPTIM1 enable */
+#define RCC_APB1LPENCR1_WWDGLPENC_Pos           (11U)
+#define RCC_APB1LPENCR1_WWDGLPENC_Msk           (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos)  /*!< 0x00000800 */
+#define RCC_APB1LPENCR1_WWDGLPENC               RCC_APB1LPENCR1_WWDGLPENC_Msk        /*!< WWDG enable */
+#define RCC_APB1LPENCR1_TIM10LPENC_Pos          (12U)
+#define RCC_APB1LPENCR1_TIM10LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos)   /*!< 0x00001000 */
+#define RCC_APB1LPENCR1_TIM10LPENC              RCC_APB1LPENCR1_TIM10LPENC_Msk       /*!< TIM10 enable */
+#define RCC_APB1LPENCR1_TIM11LPENC_Pos          (13U)
+#define RCC_APB1LPENCR1_TIM11LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos)   /*!< 0x00002000 */
+#define RCC_APB1LPENCR1_TIM11LPENC              RCC_APB1LPENCR1_TIM11LPENC_Msk       /*!< TIM11 enable */
+#define RCC_APB1LPENCR1_SPI2LPENC_Pos           (14U)
+#define RCC_APB1LPENCR1_SPI2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos)  /*!< 0x00004000 */
+#define RCC_APB1LPENCR1_SPI2LPENC               RCC_APB1LPENCR1_SPI2LPENC_Msk        /*!< SPI2 enable */
+#define RCC_APB1LPENCR1_SPI3LPENC_Pos           (15U)
+#define RCC_APB1LPENCR1_SPI3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB1LPENCR1_SPI3LPENC               RCC_APB1LPENCR1_SPI3LPENC_Msk        /*!< SPI3 enable */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos       (16U)
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk       (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos)      /*!< 0x00010000 */
+#define RCC_APB1LPENCR1_SPDIFRX1LPENC           RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk    /*!< SPDIFRX1 enable */
+#define RCC_APB1LPENCR1_USART2LPENC_Pos         (17U)
+#define RCC_APB1LPENCR1_USART2LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB1LPENCR1_USART2LPENC             RCC_APB1LPENCR1_USART2LPENC_Msk      /*!< USART2 enable */
+#define RCC_APB1LPENCR1_USART3LPENC_Pos         (18U)
+#define RCC_APB1LPENCR1_USART3LPENC_Msk         (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos)    /*!< 0x00040000 */
+#define RCC_APB1LPENCR1_USART3LPENC             RCC_APB1LPENCR1_USART3LPENC_Msk      /*!< USART3 enable */
+#define RCC_APB1LPENCR1_UART4LPENC_Pos          (19U)
+#define RCC_APB1LPENCR1_UART4LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos)   /*!< 0x00080000 */
+#define RCC_APB1LPENCR1_UART4LPENC              RCC_APB1LPENCR1_UART4LPENC_Msk       /*!< UART4 enable */
+#define RCC_APB1LPENCR1_UART5LPENC_Pos          (20U)
+#define RCC_APB1LPENCR1_UART5LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos)   /*!< 0x00100000 */
+#define RCC_APB1LPENCR1_UART5LPENC              RCC_APB1LPENCR1_UART5LPENC_Msk       /*!< UART5 enable */
+#define RCC_APB1LPENCR1_I2C1LPENC_Pos           (21U)
+#define RCC_APB1LPENCR1_I2C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos)  /*!< 0x00200000 */
+#define RCC_APB1LPENCR1_I2C1LPENC               RCC_APB1LPENCR1_I2C1LPENC_Msk        /*!< I2C1 enable */
+#define RCC_APB1LPENCR1_I2C2LPENC_Pos           (22U)
+#define RCC_APB1LPENCR1_I2C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos)  /*!< 0x00400000 */
+#define RCC_APB1LPENCR1_I2C2LPENC               RCC_APB1LPENCR1_I2C2LPENC_Msk        /*!< I2C2 enable */
+#define RCC_APB1LPENCR1_I2C3LPENC_Pos           (23U)
+#define RCC_APB1LPENCR1_I2C3LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos)  /*!< 0x00800000 */
+#define RCC_APB1LPENCR1_I2C3LPENC               RCC_APB1LPENCR1_I2C3LPENC_Msk        /*!< I2C3 enable */
+#define RCC_APB1LPENCR1_I3C1LPENC_Pos           (24U)
+#define RCC_APB1LPENCR1_I3C1LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos)  /*!< 0x01000000 */
+#define RCC_APB1LPENCR1_I3C1LPENC               RCC_APB1LPENCR1_I3C1LPENC_Msk        /*!< I3C1 enable */
+#define RCC_APB1LPENCR1_I3C2LPENC_Pos           (25U)
+#define RCC_APB1LPENCR1_I3C2LPENC_Msk           (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos)  /*!< 0x02000000 */
+#define RCC_APB1LPENCR1_I3C2LPENC               RCC_APB1LPENCR1_I3C2LPENC_Msk        /*!< I3C2 enable */
+#define RCC_APB1LPENCR1_UART7LPENC_Pos          (30U)
+#define RCC_APB1LPENCR1_UART7LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos)   /*!< 0x40000000 */
+#define RCC_APB1LPENCR1_UART7LPENC              RCC_APB1LPENCR1_UART7LPENC_Msk       /*!< UART7 enable */
+#define RCC_APB1LPENCR1_UART8LPENC_Pos          (31U)
+#define RCC_APB1LPENCR1_UART8LPENC_Msk          (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos)   /*!< 0x80000000 */
+#define RCC_APB1LPENCR1_UART8LPENC              RCC_APB1LPENCR1_UART8LPENC_Msk       /*!< UART8 enable */
+
+/***************  Bit definition for RCC_APB1LPENCR2 register  ****************/
+#define RCC_APB1LPENCR2_MDIOSLPENC_Pos          (5U)
+#define RCC_APB1LPENCR2_MDIOSLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB1LPENCR2_MDIOSLPENC              RCC_APB1LPENCR2_MDIOSLPENC_Msk       /*!< MDIOS enable */
+#define RCC_APB1LPENCR2_FDCANLPENC_Pos          (8U)
+#define RCC_APB1LPENCR2_FDCANLPENC_Msk          (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos)   /*!< 0x00000100 */
+#define RCC_APB1LPENCR2_FDCANLPENC              RCC_APB1LPENCR2_FDCANLPENC_Msk       /*!< FDCAN enable */
+#define RCC_APB1LPENCR2_UCPD1LPENC_Pos          (18U)
+#define RCC_APB1LPENCR2_UCPD1LPENC_Msk          (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos)   /*!< 0x00040000 */
+#define RCC_APB1LPENCR2_UCPD1LPENC              RCC_APB1LPENCR2_UCPD1LPENC_Msk       /*!< UCPD1 enable */
+
+/****************  Bit definition for RCC_APB2LPENCR register  ****************/
+#define RCC_APB2LPENCR_TIM1LPENC_Pos            (0U)
+#define RCC_APB2LPENCR_TIM1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENCR_TIM1LPENC                RCC_APB2LPENCR_TIM1LPENC_Msk         /*!< TIM1 enable */
+#define RCC_APB2LPENCR_TIM8LPENC_Pos            (1U)
+#define RCC_APB2LPENCR_TIM8LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENCR_TIM8LPENC                RCC_APB2LPENCR_TIM8LPENC_Msk         /*!< TIM8 enable */
+#define RCC_APB2LPENCR_USART1LPENC_Pos          (4U)
+#define RCC_APB2LPENCR_USART1LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB2LPENCR_USART1LPENC              RCC_APB2LPENCR_USART1LPENC_Msk       /*!< USART1 enable */
+#define RCC_APB2LPENCR_USART6LPENC_Pos          (5U)
+#define RCC_APB2LPENCR_USART6LPENC_Msk          (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos)   /*!< 0x00000020 */
+#define RCC_APB2LPENCR_USART6LPENC              RCC_APB2LPENCR_USART6LPENC_Msk       /*!< USART6 enable */
+#define RCC_APB2LPENCR_UART9LPENC_Pos           (6U)
+#define RCC_APB2LPENCR_UART9LPENC_Msk           (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos)  /*!< 0x00000040 */
+#define RCC_APB2LPENCR_UART9LPENC               RCC_APB2LPENCR_UART9LPENC_Msk        /*!< UART9 enable */
+#define RCC_APB2LPENCR_USART10LPENC_Pos         (7U)
+#define RCC_APB2LPENCR_USART10LPENC_Msk         (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos)    /*!< 0x00000080 */
+#define RCC_APB2LPENCR_USART10LPENC             RCC_APB2LPENCR_USART10LPENC_Msk      /*!< USART10 enable */
+#define RCC_APB2LPENCR_SPI1LPENC_Pos            (12U)
+#define RCC_APB2LPENCR_SPI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENCR_SPI1LPENC                RCC_APB2LPENCR_SPI1LPENC_Msk         /*!< SPI1 enable */
+#define RCC_APB2LPENCR_SPI4LPENC_Pos            (13U)
+#define RCC_APB2LPENCR_SPI4LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENCR_SPI4LPENC                RCC_APB2LPENCR_SPI4LPENC_Msk         /*!< SPI4 enable */
+#define RCC_APB2LPENCR_TIM18LPENC_Pos           (15U)
+#define RCC_APB2LPENCR_TIM18LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos)  /*!< 0x00008000 */
+#define RCC_APB2LPENCR_TIM18LPENC               RCC_APB2LPENCR_TIM18LPENC_Msk        /*!< TIM18 enable */
+#define RCC_APB2LPENCR_TIM15LPENC_Pos           (16U)
+#define RCC_APB2LPENCR_TIM15LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos)  /*!< 0x00010000 */
+#define RCC_APB2LPENCR_TIM15LPENC               RCC_APB2LPENCR_TIM15LPENC_Msk        /*!< TIM15 enable */
+#define RCC_APB2LPENCR_TIM16LPENC_Pos           (17U)
+#define RCC_APB2LPENCR_TIM16LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos)  /*!< 0x00020000 */
+#define RCC_APB2LPENCR_TIM16LPENC               RCC_APB2LPENCR_TIM16LPENC_Msk        /*!< TIM16 enable */
+#define RCC_APB2LPENCR_TIM17LPENC_Pos           (18U)
+#define RCC_APB2LPENCR_TIM17LPENC_Msk           (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos)  /*!< 0x00040000 */
+#define RCC_APB2LPENCR_TIM17LPENC               RCC_APB2LPENCR_TIM17LPENC_Msk        /*!< TIM17 enable */
+#define RCC_APB2LPENCR_TIM9LPENC_Pos            (19U)
+#define RCC_APB2LPENCR_TIM9LPENC_Msk            (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */
+#define RCC_APB2LPENCR_TIM9LPENC                RCC_APB2LPENCR_TIM9LPENC_Msk         /*!< TIM9 enable */
+#define RCC_APB2LPENCR_SPI5LPENC_Pos            (20U)
+#define RCC_APB2LPENCR_SPI5LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENCR_SPI5LPENC                RCC_APB2LPENCR_SPI5LPENC_Msk         /*!< SPI5 enable */
+#define RCC_APB2LPENCR_SAI1LPENC_Pos            (21U)
+#define RCC_APB2LPENCR_SAI1LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENCR_SAI1LPENC                RCC_APB2LPENCR_SAI1LPENC_Msk         /*!< SAI1 enable */
+#define RCC_APB2LPENCR_SAI2LPENC_Pos            (22U)
+#define RCC_APB2LPENCR_SAI2LPENC_Msk            (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENCR_SAI2LPENC                RCC_APB2LPENCR_SAI2LPENC_Msk         /*!< SAI2 enable */
+
+/****************  Bit definition for RCC_APB3LPENCR register  ****************/
+#define RCC_APB3LPENCR_DFTLPENC_Pos             (2U)
+#define RCC_APB3LPENCR_DFTLPENC_Msk             (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */
+#define RCC_APB3LPENCR_DFTLPENC                 RCC_APB3LPENCR_DFTLPENC_Msk          /*!< DFT enable */
+
+/***************  Bit definition for RCC_APB4LPENCR1 register  ****************/
+#define RCC_APB4LPENCR1_HDPLPENC_Pos            (2U)
+#define RCC_APB4LPENCR1_HDPLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR1_HDPLPENC                RCC_APB4LPENCR1_HDPLPENC_Msk         /*!< HDP enable */
+#define RCC_APB4LPENCR1_LPUART1LPENC_Pos        (3U)
+#define RCC_APB4LPENCR1_LPUART1LPENC_Msk        (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos)     /*!< 0x00000008 */
+#define RCC_APB4LPENCR1_LPUART1LPENC            RCC_APB4LPENCR1_LPUART1LPENC_Msk     /*!< LPUART1 enable */
+#define RCC_APB4LPENCR1_SPI6LPENC_Pos           (5U)
+#define RCC_APB4LPENCR1_SPI6LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos)  /*!< 0x00000020 */
+#define RCC_APB4LPENCR1_SPI6LPENC               RCC_APB4LPENCR1_SPI6LPENC_Msk        /*!< SPI6 enable */
+#define RCC_APB4LPENCR1_I2C4LPENC_Pos           (7U)
+#define RCC_APB4LPENCR1_I2C4LPENC_Msk           (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos)  /*!< 0x00000080 */
+#define RCC_APB4LPENCR1_I2C4LPENC               RCC_APB4LPENCR1_I2C4LPENC_Msk        /*!< I2C4 enable */
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos         (9U)
+#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos)    /*!< 0x00000200 */
+#define RCC_APB4LPENCR1_LPTIM2LPENC             RCC_APB4LPENCR1_LPTIM2LPENC_Msk      /*!< LPTIM2 enable */
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos         (10U)
+#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos)    /*!< 0x00000400 */
+#define RCC_APB4LPENCR1_LPTIM3LPENC             RCC_APB4LPENCR1_LPTIM3LPENC_Msk      /*!< LPTIM3 enable */
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos         (11U)
+#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos)    /*!< 0x00000800 */
+#define RCC_APB4LPENCR1_LPTIM4LPENC             RCC_APB4LPENCR1_LPTIM4LPENC_Msk      /*!< LPTIM4 enable */
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos         (12U)
+#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk         (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos)    /*!< 0x00001000 */
+#define RCC_APB4LPENCR1_LPTIM5LPENC             RCC_APB4LPENCR1_LPTIM5LPENC_Msk      /*!< LPTIM5 enable */
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos        (15U)
+#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk        (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos)     /*!< 0x00008000 */
+#define RCC_APB4LPENCR1_VREFBUFLPENC            RCC_APB4LPENCR1_VREFBUFLPENC_Msk     /*!< VREFBUF enable */
+#define RCC_APB4LPENCR1_RTCLPENC_Pos            (16U)
+#define RCC_APB4LPENCR1_RTCLPENC_Msk            (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENCR1_RTCLPENC                RCC_APB4LPENCR1_RTCLPENC_Msk         /*!< RTC enable */
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos         (17U)
+#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk         (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos)    /*!< 0x00020000 */
+#define RCC_APB4LPENCR1_RTCAPBLPENC             RCC_APB4LPENCR1_RTCAPBLPENC_Msk      /*!< RTCAPB enable */
+
+/***************  Bit definition for RCC_APB4LPENCR2 register  ****************/
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos         (0U)
+#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk         (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos)    /*!< 0x00000001 */
+#define RCC_APB4LPENCR2_SYSCFGLPENC             RCC_APB4LPENCR2_SYSCFGLPENC_Msk      /*!< SYSCFG enable */
+#define RCC_APB4LPENCR2_BSECLPENC_Pos           (1U)
+#define RCC_APB4LPENCR2_BSECLPENC_Msk           (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos)  /*!< 0x00000002 */
+#define RCC_APB4LPENCR2_BSECLPENC               RCC_APB4LPENCR2_BSECLPENC_Msk        /*!< BSEC enable */
+#define RCC_APB4LPENCR2_DTSLPENC_Pos            (2U)
+#define RCC_APB4LPENCR2_DTSLPENC_Msk            (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */
+#define RCC_APB4LPENCR2_DTSLPENC                RCC_APB4LPENCR2_DTSLPENC_Msk         /*!< DTS enable */
+
+/****************  Bit definition for RCC_APB5LPENCR register  ****************/
+#define RCC_APB5LPENCR_LTDCLPENC_Pos            (1U)
+#define RCC_APB5LPENCR_LTDCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */
+#define RCC_APB5LPENCR_LTDCLPENC                RCC_APB5LPENCR_LTDCLPENC_Msk         /*!< LTDC sleep enable */
+#define RCC_APB5LPENCR_DCMIPPLPENC_Pos          (2U)
+#define RCC_APB5LPENCR_DCMIPPLPENC_Msk          (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos)   /*!< 0x00000004 */
+#define RCC_APB5LPENCR_DCMIPPLPENC              RCC_APB5LPENCR_DCMIPPLPENC_Msk       /*!< DCMIPP sleep enable */
+#define RCC_APB5LPENCR_GFXTIMLPENC_Pos          (4U)
+#define RCC_APB5LPENCR_GFXTIMLPENC_Msk          (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos)   /*!< 0x00000010 */
+#define RCC_APB5LPENCR_GFXTIMLPENC              RCC_APB5LPENCR_GFXTIMLPENC_Msk       /*!< GFXTIM sleep enable */
+#define RCC_APB5LPENCR_VENCLPENC_Pos            (5U)
+#define RCC_APB5LPENCR_VENCLPENC_Msk            (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */
+#define RCC_APB5LPENCR_VENCLPENC                RCC_APB5LPENCR_VENCLPENC_Msk         /*!< VENC sleep enable */
+#define RCC_APB5LPENCR_CSILPENC_Pos             (6U)
+#define RCC_APB5LPENCR_CSILPENC_Msk             (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */
+#define RCC_APB5LPENCR_CSILPENC                 RCC_APB5LPENCR_CSILPENC_Msk          /*!< CSI sleep enable */
+
+/****************  Bit definition for RCC_PRIVCFGCR0 register  ****************/
+#define RCC_PRIVCFGCR0_LSIPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR0_LSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR0_LSIPRIVC                 RCC_PRIVCFGCR0_LSIPRIVC_Msk          /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_LSEPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR0_LSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR0_LSEPRIVC                 RCC_PRIVCFGCR0_LSEPRIVC_Msk          /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_MSIPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR0_MSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR0_MSIPRIVC                 RCC_PRIVCFGCR0_MSIPRIVC_Msk          /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSIPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR0_HSIPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR0_HSIPRIVC                 RCC_PRIVCFGCR0_HSIPRIVC_Msk          /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR0_HSEPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR0_HSEPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR0_HSEPRIVC                 RCC_PRIVCFGCR0_HSEPRIVC_Msk          /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR0 register  *****************/
+#define RCC_PUBCFGCR0_LSIPUBC_Pos               (0U)
+#define RCC_PUBCFGCR0_LSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR0_LSIPUBC                   RCC_PUBCFGCR0_LSIPUBC_Msk            /*!< Public protection of LSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_LSEPUBC_Pos               (1U)
+#define RCC_PUBCFGCR0_LSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR0_LSEPUBC                   RCC_PUBCFGCR0_LSEPUBC_Msk            /*!< Public protection of LSE configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_MSIPUBC_Pos               (2U)
+#define RCC_PUBCFGCR0_MSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR0_MSIPUBC                   RCC_PUBCFGCR0_MSIPUBC_Msk            /*!< Public protection of MSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSIPUBC_Pos               (3U)
+#define RCC_PUBCFGCR0_HSIPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR0_HSIPUBC                   RCC_PUBCFGCR0_HSIPUBC_Msk            /*!< Public protection of HSI configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR0_HSEPUBC_Pos               (4U)
+#define RCC_PUBCFGCR0_HSEPUBC_Msk               (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR0_HSEPUBC                   RCC_PUBCFGCR0_HSEPUBC_Msk            /*!< Public protection of HSE configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR1 register  ****************/
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos            (0U)
+#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */
+#define RCC_PRIVCFGCR1_PLL1PRIVC                RCC_PRIVCFGCR1_PLL1PRIVC_Msk         /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos            (1U)
+#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */
+#define RCC_PRIVCFGCR1_PLL2PRIVC                RCC_PRIVCFGCR1_PLL2PRIVC_Msk         /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR1_PLL3PRIVC                RCC_PRIVCFGCR1_PLL3PRIVC_Msk         /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR1_PLL4PRIVC                RCC_PRIVCFGCR1_PLL4PRIVC_Msk         /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR1 register  *****************/
+#define RCC_PUBCFGCR1_PLL1PUBC_Pos              (0U)
+#define RCC_PUBCFGCR1_PLL1PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */
+#define RCC_PUBCFGCR1_PLL1PUBC                  RCC_PUBCFGCR1_PLL1PUBC_Msk           /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL2PUBC_Pos              (1U)
+#define RCC_PUBCFGCR1_PLL2PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR1_PLL2PUBC                  RCC_PUBCFGCR1_PLL2PUBC_Msk           /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL3PUBC_Pos              (2U)
+#define RCC_PUBCFGCR1_PLL3PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR1_PLL3PUBC                  RCC_PUBCFGCR1_PLL3PUBC_Msk           /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR1_PLL4PUBC_Pos              (3U)
+#define RCC_PUBCFGCR1_PLL4PUBC_Msk              (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR1_PLL4PUBC                  RCC_PUBCFGCR1_PLL4PUBC_Msk           /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR2 register  ****************/
+#define RCC_PRIVCFGCR2_IC1PRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR2_IC1PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR2_IC1PRIVC                 RCC_PRIVCFGCR2_IC1PRIVC_Msk          /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC2PRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR2_IC2PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR2_IC2PRIVC                 RCC_PRIVCFGCR2_IC2PRIVC_Msk          /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC3PRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR2_IC3PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR2_IC3PRIVC                 RCC_PRIVCFGCR2_IC3PRIVC_Msk          /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC4PRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR2_IC4PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR2_IC4PRIVC                 RCC_PRIVCFGCR2_IC4PRIVC_Msk          /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC5PRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR2_IC5PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR2_IC5PRIVC                 RCC_PRIVCFGCR2_IC5PRIVC_Msk          /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC6PRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR2_IC6PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR2_IC6PRIVC                 RCC_PRIVCFGCR2_IC6PRIVC_Msk          /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC7PRIVC_Pos             (6U)
+#define RCC_PRIVCFGCR2_IC7PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */
+#define RCC_PRIVCFGCR2_IC7PRIVC                 RCC_PRIVCFGCR2_IC7PRIVC_Msk          /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC8PRIVC_Pos             (7U)
+#define RCC_PRIVCFGCR2_IC8PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */
+#define RCC_PRIVCFGCR2_IC8PRIVC                 RCC_PRIVCFGCR2_IC8PRIVC_Msk          /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC9PRIVC_Pos             (8U)
+#define RCC_PRIVCFGCR2_IC9PRIVC_Msk             (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */
+#define RCC_PRIVCFGCR2_IC9PRIVC                 RCC_PRIVCFGCR2_IC9PRIVC_Msk          /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC10PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR2_IC10PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR2_IC10PRIVC                RCC_PRIVCFGCR2_IC10PRIVC_Msk         /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC11PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR2_IC11PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR2_IC11PRIVC                RCC_PRIVCFGCR2_IC11PRIVC_Msk         /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC12PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR2_IC12PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR2_IC12PRIVC                RCC_PRIVCFGCR2_IC12PRIVC_Msk         /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC13PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR2_IC13PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR2_IC13PRIVC                RCC_PRIVCFGCR2_IC13PRIVC_Msk         /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC14PRIVC_Pos            (13U)
+#define RCC_PRIVCFGCR2_IC14PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */
+#define RCC_PRIVCFGCR2_IC14PRIVC                RCC_PRIVCFGCR2_IC14PRIVC_Msk         /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC15PRIVC_Pos            (14U)
+#define RCC_PRIVCFGCR2_IC15PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */
+#define RCC_PRIVCFGCR2_IC15PRIVC                RCC_PRIVCFGCR2_IC15PRIVC_Msk         /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC16PRIVC_Pos            (15U)
+#define RCC_PRIVCFGCR2_IC16PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */
+#define RCC_PRIVCFGCR2_IC16PRIVC                RCC_PRIVCFGCR2_IC16PRIVC_Msk         /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC17PRIVC_Pos            (16U)
+#define RCC_PRIVCFGCR2_IC17PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */
+#define RCC_PRIVCFGCR2_IC17PRIVC                RCC_PRIVCFGCR2_IC17PRIVC_Msk         /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC18PRIVC_Pos            (17U)
+#define RCC_PRIVCFGCR2_IC18PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */
+#define RCC_PRIVCFGCR2_IC18PRIVC                RCC_PRIVCFGCR2_IC18PRIVC_Msk         /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC19PRIVC_Pos            (18U)
+#define RCC_PRIVCFGCR2_IC19PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */
+#define RCC_PRIVCFGCR2_IC19PRIVC                RCC_PRIVCFGCR2_IC19PRIVC_Msk         /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR2_IC20PRIVC_Pos            (19U)
+#define RCC_PRIVCFGCR2_IC20PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */
+#define RCC_PRIVCFGCR2_IC20PRIVC                RCC_PRIVCFGCR2_IC20PRIVC_Msk         /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR2 register  *****************/
+#define RCC_PUBCFGCR2_IC1PUBC_Pos               (0U)
+#define RCC_PUBCFGCR2_IC1PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR2_IC1PUBC                   RCC_PUBCFGCR2_IC1PUBC_Msk            /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC2PUBC_Pos               (1U)
+#define RCC_PUBCFGCR2_IC2PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR2_IC2PUBC                   RCC_PUBCFGCR2_IC2PUBC_Msk            /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC3PUBC_Pos               (2U)
+#define RCC_PUBCFGCR2_IC3PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR2_IC3PUBC                   RCC_PUBCFGCR2_IC3PUBC_Msk            /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC4PUBC_Pos               (3U)
+#define RCC_PUBCFGCR2_IC4PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR2_IC4PUBC                   RCC_PUBCFGCR2_IC4PUBC_Msk            /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC5PUBC_Pos               (4U)
+#define RCC_PUBCFGCR2_IC5PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR2_IC5PUBC                   RCC_PUBCFGCR2_IC5PUBC_Msk            /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC6PUBC_Pos               (5U)
+#define RCC_PUBCFGCR2_IC6PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR2_IC6PUBC                   RCC_PUBCFGCR2_IC6PUBC_Msk            /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC7PUBC_Pos               (6U)
+#define RCC_PUBCFGCR2_IC7PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR2_IC7PUBC                   RCC_PUBCFGCR2_IC7PUBC_Msk            /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC8PUBC_Pos               (7U)
+#define RCC_PUBCFGCR2_IC8PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos)  /*!< 0x00000080 */
+#define RCC_PUBCFGCR2_IC8PUBC                   RCC_PUBCFGCR2_IC8PUBC_Msk            /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC9PUBC_Pos               (8U)
+#define RCC_PUBCFGCR2_IC9PUBC_Msk               (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos)  /*!< 0x00000100 */
+#define RCC_PUBCFGCR2_IC9PUBC                   RCC_PUBCFGCR2_IC9PUBC_Msk            /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC10PUBC_Pos              (9U)
+#define RCC_PUBCFGCR2_IC10PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR2_IC10PUBC                  RCC_PUBCFGCR2_IC10PUBC_Msk           /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC11PUBC_Pos              (10U)
+#define RCC_PUBCFGCR2_IC11PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR2_IC11PUBC                  RCC_PUBCFGCR2_IC11PUBC_Msk           /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC12PUBC_Pos              (11U)
+#define RCC_PUBCFGCR2_IC12PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR2_IC12PUBC                  RCC_PUBCFGCR2_IC12PUBC_Msk           /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC13PUBC_Pos              (12U)
+#define RCC_PUBCFGCR2_IC13PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR2_IC13PUBC                  RCC_PUBCFGCR2_IC13PUBC_Msk           /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC14PUBC_Pos              (13U)
+#define RCC_PUBCFGCR2_IC14PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */
+#define RCC_PUBCFGCR2_IC14PUBC                  RCC_PUBCFGCR2_IC14PUBC_Msk           /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC15PUBC_Pos              (14U)
+#define RCC_PUBCFGCR2_IC15PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */
+#define RCC_PUBCFGCR2_IC15PUBC                  RCC_PUBCFGCR2_IC15PUBC_Msk           /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC16PUBC_Pos              (15U)
+#define RCC_PUBCFGCR2_IC16PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */
+#define RCC_PUBCFGCR2_IC16PUBC                  RCC_PUBCFGCR2_IC16PUBC_Msk           /*!< Public protection of IC16 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC17PUBC_Pos              (16U)
+#define RCC_PUBCFGCR2_IC17PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */
+#define RCC_PUBCFGCR2_IC17PUBC                  RCC_PUBCFGCR2_IC17PUBC_Msk           /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC18PUBC_Pos              (17U)
+#define RCC_PUBCFGCR2_IC18PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */
+#define RCC_PUBCFGCR2_IC18PUBC                  RCC_PUBCFGCR2_IC18PUBC_Msk           /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC19PUBC_Pos              (18U)
+#define RCC_PUBCFGCR2_IC19PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */
+#define RCC_PUBCFGCR2_IC19PUBC                  RCC_PUBCFGCR2_IC19PUBC_Msk           /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR2_IC20PUBC_Pos              (19U)
+#define RCC_PUBCFGCR2_IC20PUBC_Msk              (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */
+#define RCC_PUBCFGCR2_IC20PUBC                  RCC_PUBCFGCR2_IC20PUBC_Msk           /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR3 register  ****************/
+#define RCC_PRIVCFGCR3_MODPRIVC_Pos             (0U)
+#define RCC_PRIVCFGCR3_MODPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */
+#define RCC_PRIVCFGCR3_MODPRIVC                 RCC_PRIVCFGCR3_MODPRIVC_Msk          /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_SYSPRIVC_Pos             (1U)
+#define RCC_PRIVCFGCR3_SYSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */
+#define RCC_PRIVCFGCR3_SYSPRIVC                 RCC_PRIVCFGCR3_SYSPRIVC_Msk          /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_BUSPRIVC_Pos             (2U)
+#define RCC_PRIVCFGCR3_BUSPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */
+#define RCC_PRIVCFGCR3_BUSPRIVC                 RCC_PRIVCFGCR3_BUSPRIVC_Msk          /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_PERPRIVC_Pos             (3U)
+#define RCC_PRIVCFGCR3_PERPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */
+#define RCC_PRIVCFGCR3_PERPRIVC                 RCC_PRIVCFGCR3_PERPRIVC_Msk          /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_INTPRIVC_Pos             (4U)
+#define RCC_PRIVCFGCR3_INTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */
+#define RCC_PRIVCFGCR3_INTPRIVC                 RCC_PRIVCFGCR3_INTPRIVC_Msk          /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR3_RSTPRIVC_Pos             (5U)
+#define RCC_PRIVCFGCR3_RSTPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */
+#define RCC_PRIVCFGCR3_RSTPRIVC                 RCC_PRIVCFGCR3_RSTPRIVC_Msk          /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR3 register  *****************/
+#define RCC_PUBCFGCR3_MODPUBC_Pos               (0U)
+#define RCC_PUBCFGCR3_MODPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos)  /*!< 0x00000001 */
+#define RCC_PUBCFGCR3_MODPUBC                   RCC_PUBCFGCR3_MODPUBC_Msk            /*!< Public protection of MOD configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_SYSPUBC_Pos               (1U)
+#define RCC_PUBCFGCR3_SYSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos)  /*!< 0x00000002 */
+#define RCC_PUBCFGCR3_SYSPUBC                   RCC_PUBCFGCR3_SYSPUBC_Msk            /*!< Public protection of SYS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_BUSPUBC_Pos               (2U)
+#define RCC_PUBCFGCR3_BUSPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos)  /*!< 0x00000004 */
+#define RCC_PUBCFGCR3_BUSPUBC                   RCC_PUBCFGCR3_BUSPUBC_Msk            /*!< Public protection of BUS configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_PERPUBC_Pos               (3U)
+#define RCC_PUBCFGCR3_PERPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos)  /*!< 0x00000008 */
+#define RCC_PUBCFGCR3_PERPUBC                   RCC_PUBCFGCR3_PERPUBC_Msk            /*!< Public protection of PER configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_INTPUBC_Pos               (4U)
+#define RCC_PUBCFGCR3_INTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos)  /*!< 0x00000010 */
+#define RCC_PUBCFGCR3_INTPUBC                   RCC_PUBCFGCR3_INTPUBC_Msk            /*!< Public protection of INT configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR3_RSTPUBC_Pos               (5U)
+#define RCC_PUBCFGCR3_RSTPUBC_Msk               (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos)  /*!< 0x00000020 */
+#define RCC_PUBCFGCR3_RSTPUBC                   RCC_PUBCFGCR3_RSTPUBC_Msk            /*!< Public protection of RST configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PRIVCFGCR4 register  ****************/
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos           (0U)
+#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk           (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos)  /*!< 0x00000001 */
+#define RCC_PRIVCFGCR4_ACLKNPRIVC               RCC_PRIVCFGCR4_ACLKNPRIVC_Msk        /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos          (1U)
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk          (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos)   /*!< 0x00000002 */
+#define RCC_PRIVCFGCR4_ACLKNCPRIVC              RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk       /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos            (2U)
+#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */
+#define RCC_PRIVCFGCR4_AHBMPRIVC                RCC_PRIVCFGCR4_AHBMPRIVC_Msk         /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos            (3U)
+#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */
+#define RCC_PRIVCFGCR4_AHB1PRIVC                RCC_PRIVCFGCR4_AHB1PRIVC_Msk         /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos            (4U)
+#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */
+#define RCC_PRIVCFGCR4_AHB2PRIVC                RCC_PRIVCFGCR4_AHB2PRIVC_Msk         /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos            (5U)
+#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */
+#define RCC_PRIVCFGCR4_AHB3PRIVC                RCC_PRIVCFGCR4_AHB3PRIVC_Msk         /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos            (6U)
+#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */
+#define RCC_PRIVCFGCR4_AHB4PRIVC                RCC_PRIVCFGCR4_AHB4PRIVC_Msk         /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos            (7U)
+#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */
+#define RCC_PRIVCFGCR4_AHB5PRIVC                RCC_PRIVCFGCR4_AHB5PRIVC_Msk         /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB1PRIVC_Pos            (8U)
+#define RCC_PRIVCFGCR4_APB1PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */
+#define RCC_PRIVCFGCR4_APB1PRIVC                RCC_PRIVCFGCR4_APB1PRIVC_Msk         /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB2PRIVC_Pos            (9U)
+#define RCC_PRIVCFGCR4_APB2PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */
+#define RCC_PRIVCFGCR4_APB2PRIVC                RCC_PRIVCFGCR4_APB2PRIVC_Msk         /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB3PRIVC_Pos            (10U)
+#define RCC_PRIVCFGCR4_APB3PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */
+#define RCC_PRIVCFGCR4_APB3PRIVC                RCC_PRIVCFGCR4_APB3PRIVC_Msk         /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB4PRIVC_Pos            (11U)
+#define RCC_PRIVCFGCR4_APB4PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */
+#define RCC_PRIVCFGCR4_APB4PRIVC                RCC_PRIVCFGCR4_APB4PRIVC_Msk         /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_APB5PRIVC_Pos            (12U)
+#define RCC_PRIVCFGCR4_APB5PRIVC_Msk            (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */
+#define RCC_PRIVCFGCR4_APB5PRIVC                RCC_PRIVCFGCR4_APB5PRIVC_Msk         /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PRIVCFGCR4_NOCPRIVC_Pos             (13U)
+#define RCC_PRIVCFGCR4_NOCPRIVC_Msk             (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */
+#define RCC_PRIVCFGCR4_NOCPRIVC                 RCC_PRIVCFGCR4_NOCPRIVC_Msk          /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR4 register  *****************/
+#define RCC_PUBCFGCR4_ACLKNPUBC_Pos             (0U)
+#define RCC_PUBCFGCR4_ACLKNPUBC_Msk             (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */
+#define RCC_PUBCFGCR4_ACLKNPUBC                 RCC_PUBCFGCR4_ACLKNPUBC_Msk          /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos            (1U)
+#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk            (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */
+#define RCC_PUBCFGCR4_ACLKNCPUBC                RCC_PUBCFGCR4_ACLKNCPUBC_Msk         /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHBMPUBC_Pos              (2U)
+#define RCC_PUBCFGCR4_AHBMPUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */
+#define RCC_PUBCFGCR4_AHBMPUBC                  RCC_PUBCFGCR4_AHBMPUBC_Msk           /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB1PUBC_Pos              (3U)
+#define RCC_PUBCFGCR4_AHB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */
+#define RCC_PUBCFGCR4_AHB1PUBC                  RCC_PUBCFGCR4_AHB1PUBC_Msk           /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB2PUBC_Pos              (4U)
+#define RCC_PUBCFGCR4_AHB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */
+#define RCC_PUBCFGCR4_AHB2PUBC                  RCC_PUBCFGCR4_AHB2PUBC_Msk           /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB3PUBC_Pos              (5U)
+#define RCC_PUBCFGCR4_AHB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */
+#define RCC_PUBCFGCR4_AHB3PUBC                  RCC_PUBCFGCR4_AHB3PUBC_Msk           /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB4PUBC_Pos              (6U)
+#define RCC_PUBCFGCR4_AHB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */
+#define RCC_PUBCFGCR4_AHB4PUBC                  RCC_PUBCFGCR4_AHB4PUBC_Msk           /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_AHB5PUBC_Pos              (7U)
+#define RCC_PUBCFGCR4_AHB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */
+#define RCC_PUBCFGCR4_AHB5PUBC                  RCC_PUBCFGCR4_AHB5PUBC_Msk           /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB1PUBC_Pos              (8U)
+#define RCC_PUBCFGCR4_APB1PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */
+#define RCC_PUBCFGCR4_APB1PUBC                  RCC_PUBCFGCR4_APB1PUBC_Msk           /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB2PUBC_Pos              (9U)
+#define RCC_PUBCFGCR4_APB2PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */
+#define RCC_PUBCFGCR4_APB2PUBC                  RCC_PUBCFGCR4_APB2PUBC_Msk           /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB3PUBC_Pos              (10U)
+#define RCC_PUBCFGCR4_APB3PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */
+#define RCC_PUBCFGCR4_APB3PUBC                  RCC_PUBCFGCR4_APB3PUBC_Msk           /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB4PUBC_Pos              (11U)
+#define RCC_PUBCFGCR4_APB4PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */
+#define RCC_PUBCFGCR4_APB4PUBC                  RCC_PUBCFGCR4_APB4PUBC_Msk           /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_APB5PUBC_Pos              (12U)
+#define RCC_PUBCFGCR4_APB5PUBC_Msk              (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */
+#define RCC_PUBCFGCR4_APB5PUBC                  RCC_PUBCFGCR4_APB5PUBC_Msk           /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR4_NOCPUBC_Pos               (13U)
+#define RCC_PUBCFGCR4_NOCPUBC_Msk               (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos)  /*!< 0x00002000 */
+#define RCC_PUBCFGCR4_NOCPUBC                   RCC_PUBCFGCR4_NOCPUBC_Msk            /*!< Public protection of NOC configuration bits (enable, ready, divider) */
+
+/****************  Bit definition for RCC_PUBCFGCR5 register  *****************/
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos          (0U)
+#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos)   /*!< 0x00000001 */
+#define RCC_PUBCFGCR5_AXISRAM3PUBC              RCC_PUBCFGCR5_AXISRAM3PUBC_Msk       /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos          (1U)
+#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos)   /*!< 0x00000002 */
+#define RCC_PUBCFGCR5_AXISRAM4PUBC              RCC_PUBCFGCR5_AXISRAM4PUBC_Msk       /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos          (2U)
+#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos)   /*!< 0x00000004 */
+#define RCC_PUBCFGCR5_AXISRAM5PUBC              RCC_PUBCFGCR5_AXISRAM5PUBC_Msk       /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos          (3U)
+#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos)   /*!< 0x00000008 */
+#define RCC_PUBCFGCR5_AXISRAM6PUBC              RCC_PUBCFGCR5_AXISRAM6PUBC_Msk       /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos          (4U)
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos)   /*!< 0x00000010 */
+#define RCC_PUBCFGCR5_AHBSRAM1PUBC              RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk       /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos          (5U)
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos)   /*!< 0x00000020 */
+#define RCC_PUBCFGCR5_AHBSRAM2PUBC              RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk       /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos           (6U)
+#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos)  /*!< 0x00000040 */
+#define RCC_PUBCFGCR5_BKPSRAMPUBC               RCC_PUBCFGCR5_BKPSRAMPUBC_Msk        /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos          (7U)
+#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos)   /*!< 0x00000080 */
+#define RCC_PUBCFGCR5_AXISRAM1PUBC              RCC_PUBCFGCR5_AXISRAM1PUBC_Msk       /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos          (8U)
+#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk          (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos)   /*!< 0x00000100 */
+#define RCC_PUBCFGCR5_AXISRAM2PUBC              RCC_PUBCFGCR5_AXISRAM2PUBC_Msk       /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos           (9U)
+#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos)  /*!< 0x00000200 */
+#define RCC_PUBCFGCR5_FLEXRAMPUBC               RCC_PUBCFGCR5_FLEXRAMPUBC_Msk        /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
+#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos       (10U)
+#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk       (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos)      /*!< 0x00000400 */
+#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC           RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk    /*!< Public protection of CACHEAXIRAM configuration bits  */
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos           (11U)
+#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk           (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos)  /*!< 0x00000800 */
+#define RCC_PUBCFGCR5_VENCRAMPUBC               RCC_PUBCFGCR5_VENCRAMPUBC_Msk        /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*          Resource Isolation Framework Security Controller (RIFSC)          */
+/*                                                                            */
+/******************************************************************************/
+/****************  Bit definition for RIFSC_RISC_CR register  *****************/
+#define RIFSC_RISC_CR_GLOCK_Pos             (0UL)
+#define RIFSC_RISC_CR_GLOCK_Msk             (0x1UL << RIFSC_RISC_CR_GLOCK_Pos)             /*!< 0x00000001 */
+#define RIFSC_RISC_CR_GLOCK                 RIFSC_RISC_CR_GLOCK_Msk                        /*!< Global lock */
+
+/*************  Bit definition for RIFSC_RISC_SECCFGRx register  **************/
+#define RIFSC_RISC_SECCFGRx_SEC0_Pos        (0U)
+#define RIFSC_RISC_SECCFGRx_SEC0_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos)         /*!< 0x00000001 */
+#define RIFSC_RISC_SECCFGRx_SEC0            RIFSC_RISC_SECCFGRx_SEC0_Msk                   /*!< Security configuration for peripheral 0 */
+#define RIFSC_RISC_SECCFGRx_SEC1_Pos        (1U)
+#define RIFSC_RISC_SECCFGRx_SEC1_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos)         /*!< 0x00000002 */
+#define RIFSC_RISC_SECCFGRx_SEC1            RIFSC_RISC_SECCFGRx_SEC1_Msk                   /*!< Security configuration for peripheral 1 */
+#define RIFSC_RISC_SECCFGRx_SEC2_Pos        (2U)
+#define RIFSC_RISC_SECCFGRx_SEC2_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos)         /*!< 0x00000004 */
+#define RIFSC_RISC_SECCFGRx_SEC2            RIFSC_RISC_SECCFGRx_SEC2_Msk                   /*!< Security configuration for peripheral 2 */
+#define RIFSC_RISC_SECCFGRx_SEC3_Pos        (3U)
+#define RIFSC_RISC_SECCFGRx_SEC3_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos)         /*!< 0x00000008 */
+#define RIFSC_RISC_SECCFGRx_SEC3            RIFSC_RISC_SECCFGRx_SEC3_Msk                   /*!< Security configuration for peripheral 3 */
+#define RIFSC_RISC_SECCFGRx_SEC4_Pos        (4U)
+#define RIFSC_RISC_SECCFGRx_SEC4_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos)         /*!< 0x00000010 */
+#define RIFSC_RISC_SECCFGRx_SEC4            RIFSC_RISC_SECCFGRx_SEC4_Msk                   /*!< Security configuration for peripheral 4 */
+#define RIFSC_RISC_SECCFGRx_SEC5_Pos        (5U)
+#define RIFSC_RISC_SECCFGRx_SEC5_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos)         /*!< 0x00000020 */
+#define RIFSC_RISC_SECCFGRx_SEC5            RIFSC_RISC_SECCFGRx_SEC5_Msk                   /*!< Security configuration for peripheral 5 */
+#define RIFSC_RISC_SECCFGRx_SEC6_Pos        (6U)
+#define RIFSC_RISC_SECCFGRx_SEC6_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos)         /*!< 0x00000040 */
+#define RIFSC_RISC_SECCFGRx_SEC6            RIFSC_RISC_SECCFGRx_SEC6_Msk                   /*!< Security configuration for peripheral 6 */
+#define RIFSC_RISC_SECCFGRx_SEC7_Pos        (7U)
+#define RIFSC_RISC_SECCFGRx_SEC7_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos)         /*!< 0x00000080 */
+#define RIFSC_RISC_SECCFGRx_SEC7            RIFSC_RISC_SECCFGRx_SEC7_Msk                   /*!< Security configuration for peripheral 7 */
+#define RIFSC_RISC_SECCFGRx_SEC8_Pos        (8U)
+#define RIFSC_RISC_SECCFGRx_SEC8_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos)         /*!< 0x00000100 */
+#define RIFSC_RISC_SECCFGRx_SEC8            RIFSC_RISC_SECCFGRx_SEC8_Msk                   /*!< Security configuration for peripheral 8 */
+#define RIFSC_RISC_SECCFGRx_SEC9_Pos        (9U)
+#define RIFSC_RISC_SECCFGRx_SEC9_Msk        (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos)         /*!< 0x00000200 */
+#define RIFSC_RISC_SECCFGRx_SEC9            RIFSC_RISC_SECCFGRx_SEC9_Msk                   /*!< Security configuration for peripheral 9 */
+#define RIFSC_RISC_SECCFGRx_SEC10_Pos       (10U)
+#define RIFSC_RISC_SECCFGRx_SEC10_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos)        /*!< 0x00000400 */
+#define RIFSC_RISC_SECCFGRx_SEC10           RIFSC_RISC_SECCFGRx_SEC10_Msk                  /*!< Security configuration for peripheral 10 */
+#define RIFSC_RISC_SECCFGRx_SEC11_Pos       (11U)
+#define RIFSC_RISC_SECCFGRx_SEC11_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos)        /*!< 0x00000800 */
+#define RIFSC_RISC_SECCFGRx_SEC11           RIFSC_RISC_SECCFGRx_SEC11_Msk                  /*!< Security configuration for peripheral 11 */
+#define RIFSC_RISC_SECCFGRx_SEC12_Pos       (12U)
+#define RIFSC_RISC_SECCFGRx_SEC12_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos)        /*!< 0x00001000 */
+#define RIFSC_RISC_SECCFGRx_SEC12           RIFSC_RISC_SECCFGRx_SEC12_Msk                  /*!< Security configuration for peripheral 12 */
+#define RIFSC_RISC_SECCFGRx_SEC13_Pos       (13U)
+#define RIFSC_RISC_SECCFGRx_SEC13_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos)        /*!< 0x00002000 */
+#define RIFSC_RISC_SECCFGRx_SEC13           RIFSC_RISC_SECCFGRx_SEC13_Msk                  /*!< Security configuration for peripheral 13 */
+#define RIFSC_RISC_SECCFGRx_SEC14_Pos       (14U)
+#define RIFSC_RISC_SECCFGRx_SEC14_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos)        /*!< 0x00004000 */
+#define RIFSC_RISC_SECCFGRx_SEC14           RIFSC_RISC_SECCFGRx_SEC14_Msk                  /*!< Security configuration for peripheral 14 */
+#define RIFSC_RISC_SECCFGRx_SEC15_Pos       (15U)
+#define RIFSC_RISC_SECCFGRx_SEC15_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos)        /*!< 0x00008000 */
+#define RIFSC_RISC_SECCFGRx_SEC15           RIFSC_RISC_SECCFGRx_SEC15_Msk                  /*!< Security configuration for peripheral 15 */
+#define RIFSC_RISC_SECCFGRx_SEC16_Pos       (16U)
+#define RIFSC_RISC_SECCFGRx_SEC16_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos)        /*!< 0x00010000 */
+#define RIFSC_RISC_SECCFGRx_SEC16           RIFSC_RISC_SECCFGRx_SEC16_Msk                  /*!< Security configuration for peripheral 16 */
+#define RIFSC_RISC_SECCFGRx_SEC17_Pos       (17U)
+#define RIFSC_RISC_SECCFGRx_SEC17_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos)        /*!< 0x00020000 */
+#define RIFSC_RISC_SECCFGRx_SEC17           RIFSC_RISC_SECCFGRx_SEC17_Msk                  /*!< Security configuration for peripheral 17 */
+#define RIFSC_RISC_SECCFGRx_SEC18_Pos       (18U)
+#define RIFSC_RISC_SECCFGRx_SEC18_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos)        /*!< 0x00040000 */
+#define RIFSC_RISC_SECCFGRx_SEC18           RIFSC_RISC_SECCFGRx_SEC18_Msk                  /*!< Security configuration for peripheral 18 */
+#define RIFSC_RISC_SECCFGRx_SEC19_Pos       (19U)
+#define RIFSC_RISC_SECCFGRx_SEC19_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos)        /*!< 0x00080000 */
+#define RIFSC_RISC_SECCFGRx_SEC19           RIFSC_RISC_SECCFGRx_SEC19_Msk                  /*!< Security configuration for peripheral 19 */
+#define RIFSC_RISC_SECCFGRx_SEC20_Pos       (20U)
+#define RIFSC_RISC_SECCFGRx_SEC20_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos)        /*!< 0x00100000 */
+#define RIFSC_RISC_SECCFGRx_SEC20           RIFSC_RISC_SECCFGRx_SEC20_Msk                  /*!< Security configuration for peripheral 20 */
+#define RIFSC_RISC_SECCFGRx_SEC21_Pos       (21U)
+#define RIFSC_RISC_SECCFGRx_SEC21_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos)        /*!< 0x00200000 */
+#define RIFSC_RISC_SECCFGRx_SEC21           RIFSC_RISC_SECCFGRx_SEC21_Msk                  /*!< Security configuration for peripheral 21 */
+#define RIFSC_RISC_SECCFGRx_SEC22_Pos       (22U)
+#define RIFSC_RISC_SECCFGRx_SEC22_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos)        /*!< 0x00400000 */
+#define RIFSC_RISC_SECCFGRx_SEC22           RIFSC_RISC_SECCFGRx_SEC22_Msk                  /*!< Security configuration for peripheral 22 */
+#define RIFSC_RISC_SECCFGRx_SEC23_Pos       (23U)
+#define RIFSC_RISC_SECCFGRx_SEC23_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos)        /*!< 0x00800000 */
+#define RIFSC_RISC_SECCFGRx_SEC23           RIFSC_RISC_SECCFGRx_SEC23_Msk                  /*!< Security configuration for peripheral 23 */
+#define RIFSC_RISC_SECCFGRx_SEC24_Pos       (24U)
+#define RIFSC_RISC_SECCFGRx_SEC24_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos)        /*!< 0x01000000 */
+#define RIFSC_RISC_SECCFGRx_SEC24           RIFSC_RISC_SECCFGRx_SEC24_Msk                  /*!< Security configuration for peripheral 24 */
+#define RIFSC_RISC_SECCFGRx_SEC25_Pos       (25U)
+#define RIFSC_RISC_SECCFGRx_SEC25_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos)        /*!< 0x02000000 */
+#define RIFSC_RISC_SECCFGRx_SEC25           RIFSC_RISC_SECCFGRx_SEC25_Msk                  /*!< Security configuration for peripheral 25 */
+#define RIFSC_RISC_SECCFGRx_SEC26_Pos       (26U)
+#define RIFSC_RISC_SECCFGRx_SEC26_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos)        /*!< 0x04000000 */
+#define RIFSC_RISC_SECCFGRx_SEC26           RIFSC_RISC_SECCFGRx_SEC26_Msk                  /*!< Security configuration for peripheral 26 */
+#define RIFSC_RISC_SECCFGRx_SEC27_Pos       (27U)
+#define RIFSC_RISC_SECCFGRx_SEC27_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos)        /*!< 0x08000000 */
+#define RIFSC_RISC_SECCFGRx_SEC27           RIFSC_RISC_SECCFGRx_SEC27_Msk                  /*!< Security configuration for peripheral 27 */
+#define RIFSC_RISC_SECCFGRx_SEC28_Pos       (28U)
+#define RIFSC_RISC_SECCFGRx_SEC28_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos)        /*!< 0x10000000 */
+#define RIFSC_RISC_SECCFGRx_SEC28           RIFSC_RISC_SECCFGRx_SEC28_Msk                  /*!< Security configuration for peripheral 28 */
+#define RIFSC_RISC_SECCFGRx_SEC29_Pos       (29U)
+#define RIFSC_RISC_SECCFGRx_SEC29_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos)        /*!< 0x20000000 */
+#define RIFSC_RISC_SECCFGRx_SEC29           RIFSC_RISC_SECCFGRx_SEC29_Msk                  /*!< Security configuration for peripheral 29 */
+#define RIFSC_RISC_SECCFGRx_SEC30_Pos       (30U)
+#define RIFSC_RISC_SECCFGRx_SEC30_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos)        /*!< 0x40000000 */
+#define RIFSC_RISC_SECCFGRx_SEC30           RIFSC_RISC_SECCFGRx_SEC30_Msk                  /*!< Security configuration for peripheral 30 */
+#define RIFSC_RISC_SECCFGRx_SEC31_Pos       (31U)
+#define RIFSC_RISC_SECCFGRx_SEC31_Msk       (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos)        /*!< 0x80000000 */
+#define RIFSC_RISC_SECCFGRx_SEC31           RIFSC_RISC_SECCFGRx_SEC31_Msk                  /*!< Security configuration for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_PRIVCFGRx register  *************/
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos      (0U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos)       /*!< 0x00000001 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV0          RIFSC_RISC_PRIVCFGRx_PRIV0_Msk                 /*!< privileged-only access permission for peripheral 0 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos      (1U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos)       /*!< 0x00000002 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV1          RIFSC_RISC_PRIVCFGRx_PRIV1_Msk                 /*!< privileged-only access permission for peripheral 1 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos      (2U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos)       /*!< 0x00000004 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV2          RIFSC_RISC_PRIVCFGRx_PRIV2_Msk                 /*!< privileged-only access permission for peripheral 2 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos      (3U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos)       /*!< 0x00000008 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV3          RIFSC_RISC_PRIVCFGRx_PRIV3_Msk                 /*!< privileged-only access permission for peripheral 3 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos      (4U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos)       /*!< 0x00000010 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV4          RIFSC_RISC_PRIVCFGRx_PRIV4_Msk                 /*!< privileged-only access permission for peripheral 4 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos      (5U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos)       /*!< 0x00000020 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV5          RIFSC_RISC_PRIVCFGRx_PRIV5_Msk                 /*!< privileged-only access permission for peripheral 5 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos      (6U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos)       /*!< 0x00000040 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV6          RIFSC_RISC_PRIVCFGRx_PRIV6_Msk                 /*!< privileged-only access permission for peripheral 6 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos      (7U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos)       /*!< 0x00000080 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV7          RIFSC_RISC_PRIVCFGRx_PRIV7_Msk                 /*!< privileged-only access permission for peripheral 7 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos      (8U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos)       /*!< 0x00000100 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV8          RIFSC_RISC_PRIVCFGRx_PRIV8_Msk                 /*!< privileged-only access permission for peripheral 8 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos      (9U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk      (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos)       /*!< 0x00000200 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV9          RIFSC_RISC_PRIVCFGRx_PRIV9_Msk                 /*!< privileged-only access permission for peripheral 9 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos     (10U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos)      /*!< 0x00000400 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV10         RIFSC_RISC_PRIVCFGRx_PRIV10_Msk                /*!< privileged-only access permission for peripheral 10 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos     (11U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos)      /*!< 0x00000800 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV11         RIFSC_RISC_PRIVCFGRx_PRIV11_Msk                /*!< privileged-only access permission for peripheral 11 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos     (12U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos)      /*!< 0x00001000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV12         RIFSC_RISC_PRIVCFGRx_PRIV12_Msk                /*!< privileged-only access permission for peripheral 12 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos     (13U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos)      /*!< 0x00002000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV13         RIFSC_RISC_PRIVCFGRx_PRIV13_Msk                /*!< privileged-only access permission for peripheral 13 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos     (14U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos)      /*!< 0x00004000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV14         RIFSC_RISC_PRIVCFGRx_PRIV14_Msk                /*!< privileged-only access permission for peripheral 14 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos     (15U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos)      /*!< 0x00008000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV15         RIFSC_RISC_PRIVCFGRx_PRIV15_Msk                /*!< privileged-only access permission for peripheral 15 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos     (16U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos)      /*!< 0x00010000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV16         RIFSC_RISC_PRIVCFGRx_PRIV16_Msk                /*!< privileged-only access permission for peripheral 16 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos     (17U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos)      /*!< 0x00020000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV17         RIFSC_RISC_PRIVCFGRx_PRIV17_Msk                /*!< privileged-only access permission for peripheral 17 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos     (18U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos)      /*!< 0x00040000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV18         RIFSC_RISC_PRIVCFGRx_PRIV18_Msk                /*!< privileged-only access permission for peripheral 18 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos     (19U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos)      /*!< 0x00080000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV19         RIFSC_RISC_PRIVCFGRx_PRIV19_Msk                /*!< privileged-only access permission for peripheral 19 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos     (20U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos)      /*!< 0x00100000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV20         RIFSC_RISC_PRIVCFGRx_PRIV20_Msk                /*!< privileged-only access permission for peripheral 20 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos     (21U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos)      /*!< 0x00200000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV21         RIFSC_RISC_PRIVCFGRx_PRIV21_Msk                /*!< privileged-only access permission for peripheral 21 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos     (22U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos)      /*!< 0x00400000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV22         RIFSC_RISC_PRIVCFGRx_PRIV22_Msk                /*!< privileged-only access permission for peripheral 22 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos     (23U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos)      /*!< 0x00800000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV23         RIFSC_RISC_PRIVCFGRx_PRIV23_Msk                /*!< privileged-only access permission for peripheral 23 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos     (24U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos)      /*!< 0x01000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV24         RIFSC_RISC_PRIVCFGRx_PRIV24_Msk                /*!< privileged-only access permission for peripheral 24 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos     (25U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos)      /*!< 0x02000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV25         RIFSC_RISC_PRIVCFGRx_PRIV25_Msk                /*!< privileged-only access permission for peripheral 25 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos     (26U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos)      /*!< 0x04000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV26         RIFSC_RISC_PRIVCFGRx_PRIV26_Msk                /*!< privileged-only access permission for peripheral 26 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos     (27U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos)      /*!< 0x08000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV27         RIFSC_RISC_PRIVCFGRx_PRIV27_Msk                /*!< privileged-only access permission for peripheral 27 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos     (28U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos)      /*!< 0x10000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV28         RIFSC_RISC_PRIVCFGRx_PRIV28_Msk                /*!< privileged-only access permission for peripheral 28 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos     (29U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos)      /*!< 0x20000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV29         RIFSC_RISC_PRIVCFGRx_PRIV29_Msk                /*!< privileged-only access permission for peripheral 29 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos     (30U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos)      /*!< 0x40000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV30         RIFSC_RISC_PRIVCFGRx_PRIV30_Msk                /*!< privileged-only access permission for peripheral 30 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos     (31U)
+#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk     (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos)      /*!< 0x80000000 */
+#define RIFSC_RISC_PRIVCFGRx_PRIV31         RIFSC_RISC_PRIVCFGRx_PRIV31_Msk                /*!< privileged-only access permission for peripheral 31 */
+
+/*************  Bit definition for RIFSC_RISC_RCFGLOCKRx register  *************/
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos    (0U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos)     /*!< 0x00000001 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK0        RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk               /*!< Resource lock for peripheral 0 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos    (1U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos)     /*!< 0x00000002 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK1        RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk               /*!< Resource lock for peripheral 1 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos    (2U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos)     /*!< 0x00000004 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK2        RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk               /*!< Resource lock for peripheral 2 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos    (3U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos)     /*!< 0x00000008 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK3        RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk               /*!< Resource lock for peripheral 3 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos    (4U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos)     /*!< 0x00000010 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK4        RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk               /*!< Resource lock for peripheral 4 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos    (5U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos)     /*!< 0x00000020 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK5        RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk               /*!< Resource lock for peripheral 5 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos    (6U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos)     /*!< 0x00000040 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK6        RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk               /*!< Resource lock for peripheral 6 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos    (7U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos)     /*!< 0x00000080 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK7        RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk               /*!< Resource lock for peripheral 7 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos    (8U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos)     /*!< 0x00000100 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK8        RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk               /*!< Resource lock for peripheral 8 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos    (9U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk    (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos)     /*!< 0x00000200 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK9        RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk               /*!< Resource lock for peripheral 9 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos   (10U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos)    /*!< 0x00000400 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK10       RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk              /*!< Resource lock for peripheral 10 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos   (11U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos)    /*!< 0x00000800 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK11       RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk              /*!< Resource lock for peripheral 11 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos   (12U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos)    /*!< 0x00001000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK12       RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk              /*!< Resource lock for peripheral 12 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos   (13U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos)    /*!< 0x00002000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK13       RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk              /*!< Resource lock for peripheral 13 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos   (14U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos)    /*!< 0x00004000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK14       RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk              /*!< Resource lock for peripheral 14 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos   (15U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos)    /*!< 0x00008000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK15       RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk              /*!< Resource lock for peripheral 15 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos   (16U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos)    /*!< 0x00010000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK16       RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk              /*!< Resource lock for peripheral 16 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos   (17U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos)    /*!< 0x00020000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK17       RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk              /*!< Resource lock for peripheral 17 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos   (18U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos)    /*!< 0x00040000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK18       RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk              /*!< Resource lock for peripheral 18 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos   (19U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos)    /*!< 0x00080000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK19       RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk              /*!< Resource lock for peripheral 19 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos   (20U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos)    /*!< 0x00100000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK20       RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk              /*!< Resource lock for peripheral 20 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos   (21U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos)    /*!< 0x00200000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK21       RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk              /*!< Resource lock for peripheral 21 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos   (22U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos)    /*!< 0x00400000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK22       RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk              /*!< Resource lock for peripheral 22 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos   (23U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos)    /*!< 0x00800000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK23       RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk              /*!< Resource lock for peripheral 23 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos   (24U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos)    /*!< 0x01000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK24       RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk              /*!< Resource lock for peripheral 24 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos   (25U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos)    /*!< 0x02000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK25       RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk              /*!< Resource lock for peripheral 25 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos   (26U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos)    /*!< 0x04000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK26       RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk              /*!< Resource lock for peripheral 26 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos   (27U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos)    /*!< 0x08000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK27       RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk              /*!< Resource lock for peripheral 27 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos   (28U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos)    /*!< 0x10000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK28       RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk              /*!< Resource lock for peripheral 28 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos   (29U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos)    /*!< 0x20000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK29       RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk              /*!< Resource lock for peripheral 29 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos   (30U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos)    /*!< 0x40000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK30       RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk              /*!< Resource lock for peripheral 30 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos   (31U)
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk   (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos)    /*!< 0x80000000 */
+#define RIFSC_RISC_RCFGLOCKRx_RLOCK31       RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk              /*!< Resource lock for peripheral 31 */
+
+/****************  Bit definition for RIFSC_RIMC_CR register  *****************/
+#define RIFSC_RIMC_CR_GLOCK_Pos             (0U)
+#define RIFSC_RIMC_CR_GLOCK_Msk             (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos)              /*!< 0x00000001 */
+#define RIFSC_RIMC_CR_GLOCK                 RIFSC_RIMC_CR_GLOCK_Msk                        /*!< Global lock */
+#define RIFSC_RIMC_CR_DAPCID_Pos            (8U)
+#define RIFSC_RIMC_CR_DAPCID_Msk            (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000700 */
+#define RIFSC_RIMC_CR_DAPCID                RIFSC_RIMC_CR_DAPCID_Msk                       /*!< Debug access port compartment ID */
+#define RIFSC_RIMC_CR_DAPCID_0              (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000100 */
+#define RIFSC_RIMC_CR_DAPCID_1              (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000200 */
+#define RIFSC_RIMC_CR_DAPCID_2              (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos)             /*!< 0x00000400 */
+
+/***************  Bit definition for RIFSC_RIMC_ATTRx register  ***************/
+#define RIFSC_RIMC_ATTRx_MCID_Pos           (4U)
+#define RIFSC_RIMC_ATTRx_MCID_Msk           (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000070 */
+#define RIFSC_RIMC_ATTRx_MCID               RIFSC_RIMC_ATTRx_MCID_Msk                      /*!< Master CID */
+#define RIFSC_RIMC_ATTRx_MCID_0             (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000010 */
+#define RIFSC_RIMC_ATTRx_MCID_1             (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000020 */
+#define RIFSC_RIMC_ATTRx_MCID_2             (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos)            /*!< 0x00000040 */
+#define RIFSC_RIMC_ATTRx_MSEC_Pos           (8U)
+#define RIFSC_RIMC_ATTRx_MSEC_Msk           (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos)            /*!< 0x00000100 */
+#define RIFSC_RIMC_ATTRx_MSEC               RIFSC_RIMC_ATTRx_MSEC_Msk                      /*!< Master secure */
+#define RIFSC_RIMC_ATTRx_MPRIV_Pos          (9U)
+#define RIFSC_RIMC_ATTRx_MPRIV_Msk          (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos)           /*!< 0x00000200 */
+#define RIFSC_RIMC_ATTRx_MPRIV              RIFSC_RIMC_ATTRx_MPRIV_Msk                     /*!< Master privileged */
+
+/******************************************************************************/
+/*                                                                            */
+/*     Resource Isolation Slave unit for Address space protection (RISAF)     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for RISAF_CR register  *******************/
+#define RISAF_CR_GLOCK_Pos                 (0U)
+#define RISAF_CR_GLOCK_Msk                 (0x1UL << RISAF_CR_GLOCK_Pos)                      /*!< 0x00000001 */
+#define RISAF_CR_GLOCK                     RISAF_CR_GLOCK_Msk                                /*!< Global lock */
+
+/******************  Bit definition for RISAF_IASR register  ******************/
+#define RISAF_IASR_CAEF_Pos                (0U)
+#define RISAF_IASR_CAEF_Msk                (0x1UL << RISAF_IASR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IASR_CAEF                    RISAF_IASR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IASR_IAEF_Pos                (1U)
+#define RISAF_IASR_IAEF_Msk                (0x1UL << RISAF_IASR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IASR_IAEF                    RISAF_IASR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/******************  Bit definition for RISAF_IACR register  ******************/
+#define RISAF_IACR_CAEF_Pos                (0U)
+#define RISAF_IACR_CAEF_Msk                (0x1UL << RISAF_IACR_CAEF_Pos)                     /*!< 0x00000001 */
+#define RISAF_IACR_CAEF                    RISAF_IACR_CAEF_Msk                               /*!< Configuration access error flag */
+#define RISAF_IACR_IAEF_Pos                (1U)
+#define RISAF_IACR_IAEF_Msk                (0x1UL << RISAF_IACR_IAEF_Pos)                     /*!< 0x00000002 */
+#define RISAF_IACR_IAEF                    RISAF_IACR_IAEF_Msk                               /*!< Illegal access error flag */
+
+/*****************  Bit definition for RISAF_IAESR register  *****************/
+#define RISAF_IAESR_IACID_Pos              (0U)
+#define RISAF_IAESR_IACID_Msk              (0x7UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000007 */
+#define RISAF_IAESR_IACID                  RISAF_IAESR_IACID_Msk                            /*!< Illegal access compartment ID */
+#define RISAF_IAESR_IACID_0                (0x1UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000001 */
+#define RISAF_IAESR_IACID_1                (0x2UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000002 */
+#define RISAF_IAESR_IACID_2                (0x4UL << RISAF_IAESR_IACID_Pos)                  /*!< 0x00000004 */
+#define RISAF_IAESR_IAPRIV_Pos             (4U)
+#define RISAF_IAESR_IAPRIV_Msk             (0x1UL << RISAF_IAESR_IAPRIV_Pos)                 /*!< 0x00000010 */
+#define RISAF_IAESR_IAPRIV                 RISAF_IAESR_IAPRIV_Msk                           /*!< Illegal access privileged */
+#define RISAF_IAESR_IASEC_Pos              (5U)
+#define RISAF_IAESR_IASEC_Msk              (0x1UL << RISAF_IAESR_IASEC_Pos)                  /*!< 0x00000020 */
+#define RISAF_IAESR_IASEC                  RISAF_IAESR_IASEC_Msk                            /*!< Illegal access security */
+#define RISAF_IAESR_IANRW_Pos              (7U)
+#define RISAF_IAESR_IANRW_Msk              (0x1UL << RISAF_IAESR_IANRW_Pos)                  /*!< 0x00000080 */
+#define RISAF_IAESR_IANRW                  RISAF_IAESR_IANRW_Msk                            /*!< Illegal access read/write */
+
+/*****************  Bit definition for RISAF_IADDR register  *****************/
+#define RISAF_IADDR_IADD_Pos                (0U)
+#define RISAF_IADDR_IADD_Msk                (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos)            /*!< 0xFFFFFFFF */
+#define RISAF_IADDR_IADD                    RISAF_IADDR_IADD_Msk                             /*!< Illegal address */
+#define RISAF_IADDR_IADD_0                  (0x1UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000001 */
+#define RISAF_IADDR_IADD_1                  (0x2UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000002 */
+#define RISAF_IADDR_IADD_2                  (0x4UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000004 */
+#define RISAF_IADDR_IADD_3                  (0x8UL << RISAF_IADDR_IADD_Pos)                   /*!< 0x00000008 */
+#define RISAF_IADDR_IADD_4                  (0x10UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000010 */
+#define RISAF_IADDR_IADD_5                  (0x20UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000020 */
+#define RISAF_IADDR_IADD_6                  (0x40UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000040 */
+#define RISAF_IADDR_IADD_7                  (0x80UL << RISAF_IADDR_IADD_Pos)                  /*!< 0x00000080 */
+#define RISAF_IADDR_IADD_8                  (0x100UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000100 */
+#define RISAF_IADDR_IADD_9                  (0x200UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000200 */
+#define RISAF_IADDR_IADD_10                 (0x400UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000400 */
+#define RISAF_IADDR_IADD_11                 (0x800UL << RISAF_IADDR_IADD_Pos)                 /*!< 0x00000800 */
+#define RISAF_IADDR_IADD_12                 (0x1000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00001000 */
+#define RISAF_IADDR_IADD_13                 (0x2000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00002000 */
+#define RISAF_IADDR_IADD_14                 (0x4000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00004000 */
+#define RISAF_IADDR_IADD_15                 (0x8000UL << RISAF_IADDR_IADD_Pos)                /*!< 0x00008000 */
+#define RISAF_IADDR_IADD_16                 (0x10000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00010000 */
+#define RISAF_IADDR_IADD_17                 (0x20000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00020000 */
+#define RISAF_IADDR_IADD_18                 (0x40000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00040000 */
+#define RISAF_IADDR_IADD_19                 (0x80000UL << RISAF_IADDR_IADD_Pos)               /*!< 0x00080000 */
+#define RISAF_IADDR_IADD_20                 (0x100000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00100000 */
+#define RISAF_IADDR_IADD_21                 (0x200000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00200000 */
+#define RISAF_IADDR_IADD_22                 (0x400000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00400000 */
+#define RISAF_IADDR_IADD_23                 (0x800000UL << RISAF_IADDR_IADD_Pos)              /*!< 0x00800000 */
+#define RISAF_IADDR_IADD_24                 (0x1000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x01000000 */
+#define RISAF_IADDR_IADD_25                 (0x2000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x02000000 */
+#define RISAF_IADDR_IADD_26                 (0x4000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x04000000 */
+#define RISAF_IADDR_IADD_27                 (0x8000000UL << RISAF_IADDR_IADD_Pos)             /*!< 0x08000000 */
+#define RISAF_IADDR_IADD_28                 (0x10000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x10000000 */
+#define RISAF_IADDR_IADD_29                 (0x20000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x20000000 */
+#define RISAF_IADDR_IADD_30                 (0x40000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x40000000 */
+#define RISAF_IADDR_IADD_31                 (0x80000000UL << RISAF_IADDR_IADD_Pos)            /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_CFGR register  ****************/
+#define RISAF_REGx_CFGR_BREN_Pos           (0U)
+#define RISAF_REGx_CFGR_BREN_Msk           (0x1UL << RISAF_REGx_CFGR_BREN_Pos)                /*!< 0x00000001 */
+#define RISAF_REGx_CFGR_BREN               RISAF_REGx_CFGR_BREN_Msk                          /*!< Base region enable */
+#define RISAF_REGx_CFGR_SEC_Pos            (8U)
+#define RISAF_REGx_CFGR_SEC_Msk            (0x1UL << RISAF_REGx_CFGR_SEC_Pos)                 /*!< 0x00000100 */
+#define RISAF_REGx_CFGR_SEC                RISAF_REGx_CFGR_SEC_Msk                           /*!< Secure region */
+#define RISAF_REGx_CFGR_PRIVC0_Pos         (16U)
+#define RISAF_REGx_CFGR_PRIVC0_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos)              /*!< 0x00010000 */
+#define RISAF_REGx_CFGR_PRIVC0             RISAF_REGx_CFGR_PRIVC0_Msk                        /*!< Privileged access for compartment 0 */
+#define RISAF_REGx_CFGR_PRIVC1_Pos         (17U)
+#define RISAF_REGx_CFGR_PRIVC1_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos)              /*!< 0x00020000 */
+#define RISAF_REGx_CFGR_PRIVC1             RISAF_REGx_CFGR_PRIVC1_Msk                        /*!< Privileged access for compartment 1 */
+#define RISAF_REGx_CFGR_PRIVC2_Pos         (18U)
+#define RISAF_REGx_CFGR_PRIVC2_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos)              /*!< 0x00040000 */
+#define RISAF_REGx_CFGR_PRIVC2             RISAF_REGx_CFGR_PRIVC2_Msk                        /*!< Privileged access for compartment 2 */
+#define RISAF_REGx_CFGR_PRIVC3_Pos         (19U)
+#define RISAF_REGx_CFGR_PRIVC3_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos)              /*!< 0x00080000 */
+#define RISAF_REGx_CFGR_PRIVC3             RISAF_REGx_CFGR_PRIVC3_Msk                        /*!< Privileged access for compartment 3 */
+#define RISAF_REGx_CFGR_PRIVC4_Pos         (20U)
+#define RISAF_REGx_CFGR_PRIVC4_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos)              /*!< 0x00100000 */
+#define RISAF_REGx_CFGR_PRIVC4             RISAF_REGx_CFGR_PRIVC4_Msk                        /*!< Privileged access for compartment 4 */
+#define RISAF_REGx_CFGR_PRIVC5_Pos         (21U)
+#define RISAF_REGx_CFGR_PRIVC5_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos)              /*!< 0x00200000 */
+#define RISAF_REGx_CFGR_PRIVC5             RISAF_REGx_CFGR_PRIVC5_Msk                        /*!< Privileged access for compartment 5 */
+#define RISAF_REGx_CFGR_PRIVC6_Pos         (22U)
+#define RISAF_REGx_CFGR_PRIVC6_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos)              /*!< 0x00400000 */
+#define RISAF_REGx_CFGR_PRIVC6             RISAF_REGx_CFGR_PRIVC6_Msk                        /*!< Privileged access for compartment 6 */
+#define RISAF_REGx_CFGR_PRIVC7_Pos         (23U)
+#define RISAF_REGx_CFGR_PRIVC7_Msk         (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos)              /*!< 0x00800000 */
+#define RISAF_REGx_CFGR_PRIVC7             RISAF_REGx_CFGR_PRIVC7_Msk                        /*!< Privileged access for compartment 7 */
+
+/**************  Bit definition for RISAF_REGx_STARTR register  ***************/
+#define RISAF_REGx_STARTR_BADDSTART_Pos    (0U)
+#define RISAF_REGx_STARTR_BADDSTART_Msk    (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0xFFFFFFFF */
+#define RISAF_REGx_STARTR_BADDSTART        RISAF_REGx_STARTR_BADDSTART_Msk                   /*!< Base region address start */
+#define RISAF_REGx_STARTR_BADDSTART_0      (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000001 */
+#define RISAF_REGx_STARTR_BADDSTART_1      (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000002 */
+#define RISAF_REGx_STARTR_BADDSTART_2      (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000004 */
+#define RISAF_REGx_STARTR_BADDSTART_3      (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos)         /*!< 0x00000008 */
+#define RISAF_REGx_STARTR_BADDSTART_4      (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000010 */
+#define RISAF_REGx_STARTR_BADDSTART_5      (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000020 */
+#define RISAF_REGx_STARTR_BADDSTART_6      (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000040 */
+#define RISAF_REGx_STARTR_BADDSTART_7      (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos)        /*!< 0x00000080 */
+#define RISAF_REGx_STARTR_BADDSTART_8      (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000100 */
+#define RISAF_REGx_STARTR_BADDSTART_9      (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000200 */
+#define RISAF_REGx_STARTR_BADDSTART_10     (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000400 */
+#define RISAF_REGx_STARTR_BADDSTART_11     (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos)       /*!< 0x00000800 */
+#define RISAF_REGx_STARTR_BADDSTART_12     (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00001000 */
+#define RISAF_REGx_STARTR_BADDSTART_13     (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00002000 */
+#define RISAF_REGx_STARTR_BADDSTART_14     (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00004000 */
+#define RISAF_REGx_STARTR_BADDSTART_15     (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos)      /*!< 0x00008000 */
+#define RISAF_REGx_STARTR_BADDSTART_16     (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00010000 */
+#define RISAF_REGx_STARTR_BADDSTART_17     (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00020000 */
+#define RISAF_REGx_STARTR_BADDSTART_18     (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00040000 */
+#define RISAF_REGx_STARTR_BADDSTART_19     (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos)     /*!< 0x00080000 */
+#define RISAF_REGx_STARTR_BADDSTART_20     (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00100000 */
+#define RISAF_REGx_STARTR_BADDSTART_21     (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00200000 */
+#define RISAF_REGx_STARTR_BADDSTART_22     (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00400000 */
+#define RISAF_REGx_STARTR_BADDSTART_23     (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos)    /*!< 0x00800000 */
+#define RISAF_REGx_STARTR_BADDSTART_24     (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x01000000 */
+#define RISAF_REGx_STARTR_BADDSTART_25     (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x02000000 */
+#define RISAF_REGx_STARTR_BADDSTART_26     (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x04000000 */
+#define RISAF_REGx_STARTR_BADDSTART_27     (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)   /*!< 0x08000000 */
+#define RISAF_REGx_STARTR_BADDSTART_28     (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x10000000 */
+#define RISAF_REGx_STARTR_BADDSTART_29     (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x20000000 */
+#define RISAF_REGx_STARTR_BADDSTART_30     (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x40000000 */
+#define RISAF_REGx_STARTR_BADDSTART_31     (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos)  /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_ENDR register  ****************/
+#define RISAF_REGx_ENDR_BADDEND_Pos        (0U)
+#define RISAF_REGx_ENDR_BADDEND_Msk        (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0xFFFFFFFF */
+#define RISAF_REGx_ENDR_BADDEND            RISAF_REGx_ENDR_BADDEND_Msk                       /*!< Base region address end */
+#define RISAF_REGx_ENDR_BADDEND_0          (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000001 */
+#define RISAF_REGx_ENDR_BADDEND_1          (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000002 */
+#define RISAF_REGx_ENDR_BADDEND_2          (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000004 */
+#define RISAF_REGx_ENDR_BADDEND_3          (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos)             /*!< 0x00000008 */
+#define RISAF_REGx_ENDR_BADDEND_4          (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000010 */
+#define RISAF_REGx_ENDR_BADDEND_5          (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000020 */
+#define RISAF_REGx_ENDR_BADDEND_6          (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000040 */
+#define RISAF_REGx_ENDR_BADDEND_7          (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos)            /*!< 0x00000080 */
+#define RISAF_REGx_ENDR_BADDEND_8          (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000100 */
+#define RISAF_REGx_ENDR_BADDEND_9          (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000200 */
+#define RISAF_REGx_ENDR_BADDEND_10         (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000400 */
+#define RISAF_REGx_ENDR_BADDEND_11         (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos)           /*!< 0x00000800 */
+#define RISAF_REGx_ENDR_BADDEND_12         (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00001000 */
+#define RISAF_REGx_ENDR_BADDEND_13         (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00002000 */
+#define RISAF_REGx_ENDR_BADDEND_14         (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00004000 */
+#define RISAF_REGx_ENDR_BADDEND_15         (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos)          /*!< 0x00008000 */
+#define RISAF_REGx_ENDR_BADDEND_16         (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00010000 */
+#define RISAF_REGx_ENDR_BADDEND_17         (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00020000 */
+#define RISAF_REGx_ENDR_BADDEND_18         (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00040000 */
+#define RISAF_REGx_ENDR_BADDEND_19         (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos)         /*!< 0x00080000 */
+#define RISAF_REGx_ENDR_BADDEND_20         (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00100000 */
+#define RISAF_REGx_ENDR_BADDEND_21         (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00200000 */
+#define RISAF_REGx_ENDR_BADDEND_22         (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00400000 */
+#define RISAF_REGx_ENDR_BADDEND_23         (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos)        /*!< 0x00800000 */
+#define RISAF_REGx_ENDR_BADDEND_24         (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x01000000 */
+#define RISAF_REGx_ENDR_BADDEND_25         (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x02000000 */
+#define RISAF_REGx_ENDR_BADDEND_26         (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x04000000 */
+#define RISAF_REGx_ENDR_BADDEND_27         (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos)       /*!< 0x08000000 */
+#define RISAF_REGx_ENDR_BADDEND_28         (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x10000000 */
+#define RISAF_REGx_ENDR_BADDEND_29         (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x20000000 */
+#define RISAF_REGx_ENDR_BADDEND_30         (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x40000000 */
+#define RISAF_REGx_ENDR_BADDEND_31         (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos)      /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_CIDCFGR register  **************/
+#define RISAF_REGx_CIDCFGR_RDENC0_Pos      (0U)
+#define RISAF_REGx_CIDCFGR_RDENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos)           /*!< 0x00000001 */
+#define RISAF_REGx_CIDCFGR_RDENC0          RISAF_REGx_CIDCFGR_RDENC0_Msk                     /*!< Read enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_RDENC1_Pos      (1U)
+#define RISAF_REGx_CIDCFGR_RDENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos)           /*!< 0x00000002 */
+#define RISAF_REGx_CIDCFGR_RDENC1          RISAF_REGx_CIDCFGR_RDENC1_Msk                     /*!< Read enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_RDENC2_Pos      (2U)
+#define RISAF_REGx_CIDCFGR_RDENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos)           /*!< 0x00000004 */
+#define RISAF_REGx_CIDCFGR_RDENC2          RISAF_REGx_CIDCFGR_RDENC2_Msk                     /*!< Read enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_RDENC3_Pos      (3U)
+#define RISAF_REGx_CIDCFGR_RDENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos)           /*!< 0x00000008 */
+#define RISAF_REGx_CIDCFGR_RDENC3          RISAF_REGx_CIDCFGR_RDENC3_Msk                     /*!< Read enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_RDENC4_Pos      (4U)
+#define RISAF_REGx_CIDCFGR_RDENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_CIDCFGR_RDENC4          RISAF_REGx_CIDCFGR_RDENC4_Msk                     /*!< Read enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_RDENC5_Pos      (5U)
+#define RISAF_REGx_CIDCFGR_RDENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_CIDCFGR_RDENC5          RISAF_REGx_CIDCFGR_RDENC5_Msk                     /*!< Read enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_RDENC6_Pos      (6U)
+#define RISAF_REGx_CIDCFGR_RDENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_CIDCFGR_RDENC6          RISAF_REGx_CIDCFGR_RDENC6_Msk                     /*!< Read enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_RDENC7_Pos      (7U)
+#define RISAF_REGx_CIDCFGR_RDENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_CIDCFGR_RDENC7          RISAF_REGx_CIDCFGR_RDENC7_Msk                     /*!< Read enable for compartment 7 */
+#define RISAF_REGx_CIDCFGR_WRENC0_Pos      (16U)
+#define RISAF_REGx_CIDCFGR_WRENC0_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos)           /*!< 0x00010000 */
+#define RISAF_REGx_CIDCFGR_WRENC0          RISAF_REGx_CIDCFGR_WRENC0_Msk                     /*!< Write enable for compartment 0 */
+#define RISAF_REGx_CIDCFGR_WRENC1_Pos      (17U)
+#define RISAF_REGx_CIDCFGR_WRENC1_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos)           /*!< 0x00020000 */
+#define RISAF_REGx_CIDCFGR_WRENC1          RISAF_REGx_CIDCFGR_WRENC1_Msk                     /*!< Write enable for compartment 1 */
+#define RISAF_REGx_CIDCFGR_WRENC2_Pos      (18U)
+#define RISAF_REGx_CIDCFGR_WRENC2_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos)           /*!< 0x00040000 */
+#define RISAF_REGx_CIDCFGR_WRENC2          RISAF_REGx_CIDCFGR_WRENC2_Msk                     /*!< Write enable for compartment 2 */
+#define RISAF_REGx_CIDCFGR_WRENC3_Pos      (19U)
+#define RISAF_REGx_CIDCFGR_WRENC3_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos)           /*!< 0x00080000 */
+#define RISAF_REGx_CIDCFGR_WRENC3          RISAF_REGx_CIDCFGR_WRENC3_Msk                     /*!< Write enable for compartment 3 */
+#define RISAF_REGx_CIDCFGR_WRENC4_Pos      (20U)
+#define RISAF_REGx_CIDCFGR_WRENC4_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos)           /*!< 0x00100000 */
+#define RISAF_REGx_CIDCFGR_WRENC4          RISAF_REGx_CIDCFGR_WRENC4_Msk                     /*!< Write enable for compartment 4 */
+#define RISAF_REGx_CIDCFGR_WRENC5_Pos      (21U)
+#define RISAF_REGx_CIDCFGR_WRENC5_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos)           /*!< 0x00200000 */
+#define RISAF_REGx_CIDCFGR_WRENC5          RISAF_REGx_CIDCFGR_WRENC5_Msk                     /*!< Write enable for compartment 5 */
+#define RISAF_REGx_CIDCFGR_WRENC6_Pos      (22U)
+#define RISAF_REGx_CIDCFGR_WRENC6_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos)           /*!< 0x00400000 */
+#define RISAF_REGx_CIDCFGR_WRENC6          RISAF_REGx_CIDCFGR_WRENC6_Msk                     /*!< Write enable for compartment 6 */
+#define RISAF_REGx_CIDCFGR_WRENC7_Pos      (23U)
+#define RISAF_REGx_CIDCFGR_WRENC7_Msk      (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos)           /*!< 0x00800000 */
+#define RISAF_REGx_CIDCFGR_WRENC7          RISAF_REGx_CIDCFGR_WRENC7_Msk                     /*!< Write enable for compartment 7 */
+
+/***************  Bit definition for RISAF_REGx_zCFGR register  ***************/
+#define RISAF_REGx_zCFGR_SREN_Pos          (0U)
+#define RISAF_REGx_zCFGR_SREN_Msk          (0x1UL << RISAF_REGx_zCFGR_SREN_Pos)               /*!< 0x00000001 */
+#define RISAF_REGx_zCFGR_SREN              RISAF_REGx_zCFGR_SREN_Msk                         /*!< Subregion enable */
+#define RISAF_REGx_zCFGR_RLOCK_Pos         (1U)
+#define RISAF_REGx_zCFGR_RLOCK_Msk         (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos)              /*!< 0x00000002 */
+#define RISAF_REGx_zCFGR_RLOCK             RISAF_REGx_zCFGR_RLOCK_Msk                        /*!< Resource lock */
+#define RISAF_REGx_zCFGR_SRCID_Pos         (4U)
+#define RISAF_REGx_zCFGR_SRCID_Msk         (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000070 */
+#define RISAF_REGx_zCFGR_SRCID             RISAF_REGx_zCFGR_SRCID_Msk                        /*!< Subregion CID */
+#define RISAF_REGx_zCFGR_SRCID_0           (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000010 */
+#define RISAF_REGx_zCFGR_SRCID_1           (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000020 */
+#define RISAF_REGx_zCFGR_SRCID_2           (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos)              /*!< 0x00000040 */
+#define RISAF_REGx_zCFGR_SEC_Pos           (8U)
+#define RISAF_REGx_zCFGR_SEC_Msk           (0x1UL << RISAF_REGx_zCFGR_SEC_Pos)                /*!< 0x00000100 */
+#define RISAF_REGx_zCFGR_SEC               RISAF_REGx_zCFGR_SEC_Msk                          /*!< Secure subregion */
+#define RISAF_REGx_zCFGR_PRIV_Pos          (9U)
+#define RISAF_REGx_zCFGR_PRIV_Msk          (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos)               /*!< 0x00000200 */
+#define RISAF_REGx_zCFGR_PRIV              RISAF_REGx_zCFGR_PRIV_Msk                         /*!< Privileged subregion */
+#define RISAF_REGx_zCFGR_RDEN_Pos          (12U)
+#define RISAF_REGx_zCFGR_RDEN_Msk          (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos)               /*!< 0x00001000 */
+#define RISAF_REGx_zCFGR_RDEN              RISAF_REGx_zCFGR_RDEN_Msk                         /*!< Read enable */
+#define RISAF_REGx_zCFGR_WREN_Pos          (13U)
+#define RISAF_REGx_zCFGR_WREN_Msk          (0x1UL << RISAF_REGx_zCFGR_WREN_Pos)               /*!< 0x00002000 */
+#define RISAF_REGx_zCFGR_WREN              RISAF_REGx_zCFGR_WREN_Msk                         /*!< Write enable */
+
+/**************  Bit definition for RISAF_REGx_zSTARTR register  **************/
+#define RISAF_REGx_zSTARTR_SADDSTART_Pos   (0U)
+#define RISAF_REGx_zSTARTR_SADDSTART_Msk   (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zSTARTR_SADDSTART       RISAF_REGx_zSTARTR_SADDSTART_Msk                  /*!< Subregion address start */
+#define RISAF_REGx_zSTARTR_SADDSTART_0     (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000001 */
+#define RISAF_REGx_zSTARTR_SADDSTART_1     (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000002 */
+#define RISAF_REGx_zSTARTR_SADDSTART_2     (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000004 */
+#define RISAF_REGx_zSTARTR_SADDSTART_3     (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)        /*!< 0x00000008 */
+#define RISAF_REGx_zSTARTR_SADDSTART_4     (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000010 */
+#define RISAF_REGx_zSTARTR_SADDSTART_5     (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000020 */
+#define RISAF_REGx_zSTARTR_SADDSTART_6     (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000040 */
+#define RISAF_REGx_zSTARTR_SADDSTART_7     (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)       /*!< 0x00000080 */
+#define RISAF_REGx_zSTARTR_SADDSTART_8     (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000100 */
+#define RISAF_REGx_zSTARTR_SADDSTART_9     (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000200 */
+#define RISAF_REGx_zSTARTR_SADDSTART_10    (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000400 */
+#define RISAF_REGx_zSTARTR_SADDSTART_11    (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)      /*!< 0x00000800 */
+#define RISAF_REGx_zSTARTR_SADDSTART_12    (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00001000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_13    (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00002000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_14    (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00004000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_15    (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)     /*!< 0x00008000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_16    (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00010000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_17    (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00020000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_18    (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00040000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_19    (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)    /*!< 0x00080000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_20    (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00100000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_21    (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00200000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_22    (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00400000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_23    (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)   /*!< 0x00800000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_24    (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x01000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_25    (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x02000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_26    (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x04000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_27    (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos)  /*!< 0x08000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_28    (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_29    (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_30    (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */
+#define RISAF_REGx_zSTARTR_SADDSTART_31    (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */
+
+/***************  Bit definition for RISAF_REGx_zENDR register  ***************/
+#define RISAF_REGx_zENDR_SADDEND_Pos       (0U)
+#define RISAF_REGx_zENDR_SADDEND_Msk       (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0xFFFFFFFF */
+#define RISAF_REGx_zENDR_SADDEND           RISAF_REGx_zENDR_SADDEND_Msk                      /*!< Subregion address end */
+#define RISAF_REGx_zENDR_SADDEND_0         (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000001 */
+#define RISAF_REGx_zENDR_SADDEND_1         (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000002 */
+#define RISAF_REGx_zENDR_SADDEND_2         (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000004 */
+#define RISAF_REGx_zENDR_SADDEND_3         (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos)            /*!< 0x00000008 */
+#define RISAF_REGx_zENDR_SADDEND_4         (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000010 */
+#define RISAF_REGx_zENDR_SADDEND_5         (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000020 */
+#define RISAF_REGx_zENDR_SADDEND_6         (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000040 */
+#define RISAF_REGx_zENDR_SADDEND_7         (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos)           /*!< 0x00000080 */
+#define RISAF_REGx_zENDR_SADDEND_8         (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000100 */
+#define RISAF_REGx_zENDR_SADDEND_9         (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000200 */
+#define RISAF_REGx_zENDR_SADDEND_10        (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000400 */
+#define RISAF_REGx_zENDR_SADDEND_11        (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos)          /*!< 0x00000800 */
+#define RISAF_REGx_zENDR_SADDEND_12        (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00001000 */
+#define RISAF_REGx_zENDR_SADDEND_13        (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00002000 */
+#define RISAF_REGx_zENDR_SADDEND_14        (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00004000 */
+#define RISAF_REGx_zENDR_SADDEND_15        (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos)         /*!< 0x00008000 */
+#define RISAF_REGx_zENDR_SADDEND_16        (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00010000 */
+#define RISAF_REGx_zENDR_SADDEND_17        (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00020000 */
+#define RISAF_REGx_zENDR_SADDEND_18        (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00040000 */
+#define RISAF_REGx_zENDR_SADDEND_19        (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos)        /*!< 0x00080000 */
+#define RISAF_REGx_zENDR_SADDEND_20        (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00100000 */
+#define RISAF_REGx_zENDR_SADDEND_21        (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00200000 */
+#define RISAF_REGx_zENDR_SADDEND_22        (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00400000 */
+#define RISAF_REGx_zENDR_SADDEND_23        (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos)       /*!< 0x00800000 */
+#define RISAF_REGx_zENDR_SADDEND_24        (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x01000000 */
+#define RISAF_REGx_zENDR_SADDEND_25        (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x02000000 */
+#define RISAF_REGx_zENDR_SADDEND_26        (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x04000000 */
+#define RISAF_REGx_zENDR_SADDEND_27        (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos)      /*!< 0x08000000 */
+#define RISAF_REGx_zENDR_SADDEND_28        (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x10000000 */
+#define RISAF_REGx_zENDR_SADDEND_29        (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x20000000 */
+#define RISAF_REGx_zENDR_SADDEND_30        (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x40000000 */
+#define RISAF_REGx_zENDR_SADDEND_31        (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos)     /*!< 0x80000000 */
+
+/**************  Bit definition for RISAF_REGx_zNESTR register  ***************/
+#define RISAF_REGx_zNESTR_DCEN_Pos         (2U)
+#define RISAF_REGx_zNESTR_DCEN_Msk         (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos)              /*!< 0x00000004 */
+#define RISAF_REGx_zNESTR_DCEN             RISAF_REGx_zNESTR_DCEN_Msk                        /*!< Delegated configuration enable */
+#define RISAF_REGx_zNESTR_DCCID_Pos        (4U)
+#define RISAF_REGx_zNESTR_DCCID_Msk        (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000070 */
+#define RISAF_REGx_zNESTR_DCCID            RISAF_REGx_zNESTR_DCCID_Msk                       /*!< Delegated configuration CID */
+#define RISAF_REGx_zNESTR_DCCID_0          (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000010 */
+#define RISAF_REGx_zNESTR_DCCID_1          (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000020 */
+#define RISAF_REGx_zNESTR_DCCID_2          (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos)             /*!< 0x00000040 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    (IAC)                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IAC_IER0 register  *******************/
+#define IAC_IERx_IAIE0_Pos         (0U)
+#define IAC_IERx_IAIE0_Msk         (0x1UL << IAC_IERx_IAIE0_Pos)        /*!< 0x00000001 */
+#define IAC_IERx_IAIE0             IAC_IERx_IAIE0_Msk                  /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_IERx_IAIE1_Pos         (1U)
+#define IAC_IERx_IAIE1_Msk         (0x1UL << IAC_IERx_IAIE1_Pos)        /*!< 0x00000002 */
+#define IAC_IERx_IAIE1             IAC_IERx_IAIE1_Msk                  /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_IERx_IAIE2_Pos         (2U)
+#define IAC_IERx_IAIE2_Msk         (0x1UL << IAC_IERx_IAIE2_Pos)        /*!< 0x00000004 */
+#define IAC_IERx_IAIE2             IAC_IERx_IAIE2_Msk                  /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_IERx_IAIE3_Pos         (3U)
+#define IAC_IERx_IAIE3_Msk         (0x1UL << IAC_IERx_IAIE3_Pos)        /*!< 0x00000008 */
+#define IAC_IERx_IAIE3             IAC_IERx_IAIE3_Msk                  /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_IERx_IAIE4_Pos         (4U)
+#define IAC_IERx_IAIE4_Msk         (0x1UL << IAC_IERx_IAIE4_Pos)        /*!< 0x00000010 */
+#define IAC_IERx_IAIE4             IAC_IERx_IAIE4_Msk                  /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_IERx_IAIE5_Pos         (5U)
+#define IAC_IERx_IAIE5_Msk         (0x1UL << IAC_IERx_IAIE5_Pos)        /*!< 0x00000020 */
+#define IAC_IERx_IAIE5             IAC_IERx_IAIE5_Msk                  /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_IERx_IAIE6_Pos         (6U)
+#define IAC_IERx_IAIE6_Msk         (0x1UL << IAC_IERx_IAIE6_Pos)        /*!< 0x00000040 */
+#define IAC_IERx_IAIE6             IAC_IERx_IAIE6_Msk                  /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_IERx_IAIE7_Pos         (7U)
+#define IAC_IERx_IAIE7_Msk         (0x1UL << IAC_IERx_IAIE7_Pos)        /*!< 0x00000080 */
+#define IAC_IERx_IAIE7             IAC_IERx_IAIE7_Msk                  /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_IERx_IAIE8_Pos         (8U)
+#define IAC_IERx_IAIE8_Msk         (0x1UL << IAC_IERx_IAIE8_Pos)        /*!< 0x00000100 */
+#define IAC_IERx_IAIE8             IAC_IERx_IAIE8_Msk                  /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_IERx_IAIE9_Pos         (9U)
+#define IAC_IERx_IAIE9_Msk         (0x1UL << IAC_IERx_IAIE9_Pos)        /*!< 0x00000200 */
+#define IAC_IERx_IAIE9             IAC_IERx_IAIE9_Msk                  /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_IERx_IAIE10_Pos        (10U)
+#define IAC_IERx_IAIE10_Msk        (0x1UL << IAC_IERx_IAIE10_Pos)       /*!< 0x00000400 */
+#define IAC_IERx_IAIE10            IAC_IERx_IAIE10_Msk                 /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_IERx_IAIE11_Pos        (11U)
+#define IAC_IERx_IAIE11_Msk        (0x1UL << IAC_IERx_IAIE11_Pos)       /*!< 0x00000800 */
+#define IAC_IERx_IAIE11            IAC_IERx_IAIE11_Msk                 /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_IERx_IAIE12_Pos        (12U)
+#define IAC_IERx_IAIE12_Msk        (0x1UL << IAC_IERx_IAIE12_Pos)       /*!< 0x00001000 */
+#define IAC_IERx_IAIE12            IAC_IERx_IAIE12_Msk                 /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_IERx_IAIE13_Pos        (13U)
+#define IAC_IERx_IAIE13_Msk        (0x1UL << IAC_IERx_IAIE13_Pos)       /*!< 0x00002000 */
+#define IAC_IERx_IAIE13            IAC_IERx_IAIE13_Msk                 /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_IERx_IAIE14_Pos        (14U)
+#define IAC_IERx_IAIE14_Msk        (0x1UL << IAC_IERx_IAIE14_Pos)       /*!< 0x00004000 */
+#define IAC_IERx_IAIE14            IAC_IERx_IAIE14_Msk                 /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_IERx_IAIE15_Pos        (15U)
+#define IAC_IERx_IAIE15_Msk        (0x1UL << IAC_IERx_IAIE15_Pos)       /*!< 0x00008000 */
+#define IAC_IERx_IAIE15            IAC_IERx_IAIE15_Msk                 /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_IERx_IAIE16_Pos        (16U)
+#define IAC_IERx_IAIE16_Msk        (0x1UL << IAC_IERx_IAIE16_Pos)       /*!< 0x00010000 */
+#define IAC_IERx_IAIE16            IAC_IERx_IAIE16_Msk                 /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_IERx_IAIE17_Pos        (17U)
+#define IAC_IERx_IAIE17_Msk        (0x1UL << IAC_IERx_IAIE17_Pos)       /*!< 0x00020000 */
+#define IAC_IERx_IAIE17            IAC_IERx_IAIE17_Msk                 /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_IERx_IAIE18_Pos        (18U)
+#define IAC_IERx_IAIE18_Msk        (0x1UL << IAC_IERx_IAIE18_Pos)       /*!< 0x00040000 */
+#define IAC_IERx_IAIE18            IAC_IERx_IAIE18_Msk                 /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_IERx_IAIE19_Pos        (19U)
+#define IAC_IERx_IAIE19_Msk        (0x1UL << IAC_IERx_IAIE19_Pos)       /*!< 0x00080000 */
+#define IAC_IERx_IAIE19            IAC_IERx_IAIE19_Msk                 /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_IERx_IAIE20_Pos        (20U)
+#define IAC_IERx_IAIE20_Msk        (0x1UL << IAC_IERx_IAIE20_Pos)       /*!< 0x00100000 */
+#define IAC_IERx_IAIE20            IAC_IERx_IAIE20_Msk                 /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_IERx_IAIE21_Pos        (21U)
+#define IAC_IERx_IAIE21_Msk        (0x1UL << IAC_IERx_IAIE21_Pos)       /*!< 0x00200000 */
+#define IAC_IERx_IAIE21            IAC_IERx_IAIE21_Msk                 /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_IERx_IAIE22_Pos        (22U)
+#define IAC_IERx_IAIE22_Msk        (0x1UL << IAC_IERx_IAIE22_Pos)       /*!< 0x00400000 */
+#define IAC_IERx_IAIE22            IAC_IERx_IAIE22_Msk                 /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_IERx_IAIE23_Pos        (23U)
+#define IAC_IERx_IAIE23_Msk        (0x1UL << IAC_IERx_IAIE23_Pos)       /*!< 0x00800000 */
+#define IAC_IERx_IAIE23            IAC_IERx_IAIE23_Msk                 /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_IERx_IAIE24_Pos        (24U)
+#define IAC_IERx_IAIE24_Msk        (0x1UL << IAC_IERx_IAIE24_Pos)       /*!< 0x01000000 */
+#define IAC_IERx_IAIE24            IAC_IERx_IAIE24_Msk                 /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_IERx_IAIE25_Pos        (25U)
+#define IAC_IERx_IAIE25_Msk        (0x1UL << IAC_IERx_IAIE25_Pos)       /*!< 0x02000000 */
+#define IAC_IERx_IAIE25            IAC_IERx_IAIE25_Msk                 /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_IERx_IAIE26_Pos        (26U)
+#define IAC_IERx_IAIE26_Msk        (0x1UL << IAC_IERx_IAIE26_Pos)       /*!< 0x04000000 */
+#define IAC_IERx_IAIE26            IAC_IERx_IAIE26_Msk                 /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_IERx_IAIE27_Pos        (27U)
+#define IAC_IERx_IAIE27_Msk        (0x1UL << IAC_IERx_IAIE27_Pos)       /*!< 0x08000000 */
+#define IAC_IERx_IAIE27            IAC_IERx_IAIE27_Msk                 /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_IERx_IAIE28_Pos        (28U)
+#define IAC_IERx_IAIE28_Msk        (0x1UL << IAC_IERx_IAIE28_Pos)       /*!< 0x10000000 */
+#define IAC_IERx_IAIE28            IAC_IERx_IAIE28_Msk                 /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_IERx_IAIE29_Pos        (29U)
+#define IAC_IERx_IAIE29_Msk        (0x1UL << IAC_IERx_IAIE29_Pos)       /*!< 0x20000000 */
+#define IAC_IERx_IAIE29            IAC_IERx_IAIE29_Msk                 /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_IERx_IAIE30_Pos        (30U)
+#define IAC_IERx_IAIE30_Msk        (0x1UL << IAC_IERx_IAIE30_Pos)       /*!< 0x40000000 */
+#define IAC_IERx_IAIE30            IAC_IERx_IAIE30_Msk                 /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_IERx_IAIE31_Pos        (31U)
+#define IAC_IERx_IAIE31_Msk        (0x1UL << IAC_IERx_IAIE31_Pos)       /*!< 0x80000000 */
+#define IAC_IERx_IAIE31            IAC_IERx_IAIE31_Msk                 /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ISRx register  *******************/
+#define IAC_ISRx_IAF0_Pos          (0U)
+#define IAC_ISRx_IAF0_Msk          (0x1UL << IAC_ISRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ISRx_IAF0              IAC_ISRx_IAF0_Msk                   /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
+#define IAC_ISRx_IAF1_Pos          (1U)
+#define IAC_ISRx_IAF1_Msk          (0x1UL << IAC_ISRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ISRx_IAF1              IAC_ISRx_IAF1_Msk                   /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
+#define IAC_ISRx_IAF2_Pos          (2U)
+#define IAC_ISRx_IAF2_Msk          (0x1UL << IAC_ISRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ISRx_IAF2              IAC_ISRx_IAF2_Msk                   /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
+#define IAC_ISRx_IAF3_Pos          (3U)
+#define IAC_ISRx_IAF3_Msk          (0x1UL << IAC_ISRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ISRx_IAF3              IAC_ISRx_IAF3_Msk                   /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
+#define IAC_ISRx_IAF4_Pos          (4U)
+#define IAC_ISRx_IAF4_Msk          (0x1UL << IAC_ISRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ISRx_IAF4              IAC_ISRx_IAF4_Msk                   /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
+#define IAC_ISRx_IAF5_Pos          (5U)
+#define IAC_ISRx_IAF5_Msk          (0x1UL << IAC_ISRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ISRx_IAF5              IAC_ISRx_IAF5_Msk                   /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
+#define IAC_ISRx_IAF6_Pos          (6U)
+#define IAC_ISRx_IAF6_Msk          (0x1UL << IAC_ISRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ISRx_IAF6              IAC_ISRx_IAF6_Msk                   /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
+#define IAC_ISRx_IAF7_Pos          (7U)
+#define IAC_ISRx_IAF7_Msk          (0x1UL << IAC_ISRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ISRx_IAF7              IAC_ISRx_IAF7_Msk                   /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
+#define IAC_ISRx_IAF8_Pos          (8U)
+#define IAC_ISRx_IAF8_Msk          (0x1UL << IAC_ISRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ISRx_IAF8              IAC_ISRx_IAF8_Msk                   /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
+#define IAC_ISRx_IAF9_Pos          (9U)
+#define IAC_ISRx_IAF9_Msk          (0x1UL << IAC_ISRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ISRx_IAF9              IAC_ISRx_IAF9_Msk                   /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
+#define IAC_ISRx_IAF10_Pos         (10U)
+#define IAC_ISRx_IAF10_Msk         (0x1UL << IAC_ISRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ISRx_IAF10             IAC_ISRx_IAF10_Msk                  /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
+#define IAC_ISRx_IAF11_Pos         (11U)
+#define IAC_ISRx_IAF11_Msk         (0x1UL << IAC_ISRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ISRx_IAF11             IAC_ISRx_IAF11_Msk                  /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
+#define IAC_ISRx_IAF12_Pos         (12U)
+#define IAC_ISRx_IAF12_Msk         (0x1UL << IAC_ISRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ISRx_IAF12             IAC_ISRx_IAF12_Msk                  /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
+#define IAC_ISRx_IAF13_Pos         (13U)
+#define IAC_ISRx_IAF13_Msk         (0x1UL << IAC_ISRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ISRx_IAF13             IAC_ISRx_IAF13_Msk                  /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
+#define IAC_ISRx_IAF14_Pos         (14U)
+#define IAC_ISRx_IAF14_Msk         (0x1UL << IAC_ISRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ISRx_IAF14             IAC_ISRx_IAF14_Msk                  /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
+#define IAC_ISRx_IAF15_Pos         (15U)
+#define IAC_ISRx_IAF15_Msk         (0x1UL << IAC_ISRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ISRx_IAF15             IAC_ISRx_IAF15_Msk                  /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
+#define IAC_ISRx_IAF16_Pos         (16U)
+#define IAC_ISRx_IAF16_Msk         (0x1UL << IAC_ISRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ISRx_IAF16             IAC_ISRx_IAF16_Msk                  /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
+#define IAC_ISRx_IAF17_Pos         (17U)
+#define IAC_ISRx_IAF17_Msk         (0x1UL << IAC_ISRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ISRx_IAF17             IAC_ISRx_IAF17_Msk                  /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
+#define IAC_ISRx_IAF18_Pos         (18U)
+#define IAC_ISRx_IAF18_Msk         (0x1UL << IAC_ISRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ISRx_IAF18             IAC_ISRx_IAF18_Msk                  /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
+#define IAC_ISRx_IAF19_Pos         (19U)
+#define IAC_ISRx_IAF19_Msk         (0x1UL << IAC_ISRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ISRx_IAF19             IAC_ISRx_IAF19_Msk                  /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
+#define IAC_ISRx_IAF20_Pos         (20U)
+#define IAC_ISRx_IAF20_Msk         (0x1UL << IAC_ISRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ISRx_IAF20             IAC_ISRx_IAF20_Msk                  /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
+#define IAC_ISRx_IAF21_Pos         (21U)
+#define IAC_ISRx_IAF21_Msk         (0x1UL << IAC_ISRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ISRx_IAF21             IAC_ISRx_IAF21_Msk                  /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
+#define IAC_ISRx_IAF22_Pos         (22U)
+#define IAC_ISRx_IAF22_Msk         (0x1UL << IAC_ISRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ISRx_IAF22             IAC_ISRx_IAF22_Msk                  /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
+#define IAC_ISRx_IAF23_Pos         (23U)
+#define IAC_ISRx_IAF23_Msk         (0x1UL << IAC_ISRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ISRx_IAF23             IAC_ISRx_IAF23_Msk                  /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
+#define IAC_ISRx_IAF24_Pos         (24U)
+#define IAC_ISRx_IAF24_Msk         (0x1UL << IAC_ISRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ISRx_IAF24             IAC_ISRx_IAF24_Msk                  /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
+#define IAC_ISRx_IAF25_Pos         (25U)
+#define IAC_ISRx_IAF25_Msk         (0x1UL << IAC_ISRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ISRx_IAF25             IAC_ISRx_IAF25_Msk                  /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
+#define IAC_ISRx_IAF26_Pos         (26U)
+#define IAC_ISRx_IAF26_Msk         (0x1UL << IAC_ISRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ISRx_IAF26             IAC_ISRx_IAF26_Msk                  /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
+#define IAC_ISRx_IAF27_Pos         (27U)
+#define IAC_ISRx_IAF27_Msk         (0x1UL << IAC_ISRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ISRx_IAF27             IAC_ISRx_IAF27_Msk                  /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
+#define IAC_ISRx_IAF28_Pos         (28U)
+#define IAC_ISRx_IAF28_Msk         (0x1UL << IAC_ISRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ISRx_IAF28             IAC_ISRx_IAF28_Msk                  /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
+#define IAC_ISRx_IAF29_Pos         (29U)
+#define IAC_ISRx_IAF29_Msk         (0x1UL << IAC_ISRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ISRx_IAF29             IAC_ISRx_IAF29_Msk                  /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
+#define IAC_ISRx_IAF30_Pos         (30U)
+#define IAC_ISRx_IAF30_Msk         (0x1UL << IAC_ISRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ISRx_IAF30             IAC_ISRx_IAF30_Msk                  /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
+#define IAC_ISRx_IAF31_Pos         (31U)
+#define IAC_ISRx_IAF31_Msk         (0x1UL << IAC_ISRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ISRx_IAF31             IAC_ISRx_IAF31_Msk                  /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
+
+/*******************  Bit definition for IAC_ICRx register  *******************/
+#define IAC_ICRx_IAF0_Pos          (0U)
+#define IAC_ICRx_IAF0_Msk          (0x1UL << IAC_ICRx_IAF0_Pos)         /*!< 0x00000001 */
+#define IAC_ICRx_IAF0              IAC_ICRx_IAF0_Msk                   /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */
+#define IAC_ICRx_IAF1_Pos          (1U)
+#define IAC_ICRx_IAF1_Msk          (0x1UL << IAC_ICRx_IAF1_Pos)         /*!< 0x00000002 */
+#define IAC_ICRx_IAF1              IAC_ICRx_IAF1_Msk                   /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */
+#define IAC_ICRx_IAF2_Pos          (2U)
+#define IAC_ICRx_IAF2_Msk          (0x1UL << IAC_ICRx_IAF2_Pos)         /*!< 0x00000004 */
+#define IAC_ICRx_IAF2              IAC_ICRx_IAF2_Msk                   /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */
+#define IAC_ICRx_IAF3_Pos          (3U)
+#define IAC_ICRx_IAF3_Msk          (0x1UL << IAC_ICRx_IAF3_Pos)         /*!< 0x00000008 */
+#define IAC_ICRx_IAF3              IAC_ICRx_IAF3_Msk                   /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */
+#define IAC_ICRx_IAF4_Pos          (4U)
+#define IAC_ICRx_IAF4_Msk          (0x1UL << IAC_ICRx_IAF4_Pos)         /*!< 0x00000010 */
+#define IAC_ICRx_IAF4              IAC_ICRx_IAF4_Msk                   /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */
+#define IAC_ICRx_IAF5_Pos          (5U)
+#define IAC_ICRx_IAF5_Msk          (0x1UL << IAC_ICRx_IAF5_Pos)         /*!< 0x00000020 */
+#define IAC_ICRx_IAF5              IAC_ICRx_IAF5_Msk                   /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */
+#define IAC_ICRx_IAF6_Pos          (6U)
+#define IAC_ICRx_IAF6_Msk          (0x1UL << IAC_ICRx_IAF6_Pos)         /*!< 0x00000040 */
+#define IAC_ICRx_IAF6              IAC_ICRx_IAF6_Msk                   /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */
+#define IAC_ICRx_IAF7_Pos          (7U)
+#define IAC_ICRx_IAF7_Msk          (0x1UL << IAC_ICRx_IAF7_Pos)         /*!< 0x00000080 */
+#define IAC_ICRx_IAF7              IAC_ICRx_IAF7_Msk                   /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */
+#define IAC_ICRx_IAF8_Pos          (8U)
+#define IAC_ICRx_IAF8_Msk          (0x1UL << IAC_ICRx_IAF8_Pos)         /*!< 0x00000100 */
+#define IAC_ICRx_IAF8              IAC_ICRx_IAF8_Msk                   /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */
+#define IAC_ICRx_IAF9_Pos          (9U)
+#define IAC_ICRx_IAF9_Msk          (0x1UL << IAC_ICRx_IAF9_Pos)         /*!< 0x00000200 */
+#define IAC_ICRx_IAF9              IAC_ICRx_IAF9_Msk                   /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */
+#define IAC_ICRx_IAF10_Pos         (10U)
+#define IAC_ICRx_IAF10_Msk         (0x1UL << IAC_ICRx_IAF10_Pos)        /*!< 0x00000400 */
+#define IAC_ICRx_IAF10             IAC_ICRx_IAF10_Msk                  /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */
+#define IAC_ICRx_IAF11_Pos         (11U)
+#define IAC_ICRx_IAF11_Msk         (0x1UL << IAC_ICRx_IAF11_Pos)        /*!< 0x00000800 */
+#define IAC_ICRx_IAF11             IAC_ICRx_IAF11_Msk                  /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */
+#define IAC_ICRx_IAF12_Pos         (12U)
+#define IAC_ICRx_IAF12_Msk         (0x1UL << IAC_ICRx_IAF12_Pos)        /*!< 0x00001000 */
+#define IAC_ICRx_IAF12             IAC_ICRx_IAF12_Msk                  /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */
+#define IAC_ICRx_IAF13_Pos         (13U)
+#define IAC_ICRx_IAF13_Msk         (0x1UL << IAC_ICRx_IAF13_Pos)        /*!< 0x00002000 */
+#define IAC_ICRx_IAF13             IAC_ICRx_IAF13_Msk                  /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */
+#define IAC_ICRx_IAF14_Pos         (14U)
+#define IAC_ICRx_IAF14_Msk         (0x1UL << IAC_ICRx_IAF14_Pos)        /*!< 0x00004000 */
+#define IAC_ICRx_IAF14             IAC_ICRx_IAF14_Msk                  /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */
+#define IAC_ICRx_IAF15_Pos         (15U)
+#define IAC_ICRx_IAF15_Msk         (0x1UL << IAC_ICRx_IAF15_Pos)        /*!< 0x00008000 */
+#define IAC_ICRx_IAF15             IAC_ICRx_IAF15_Msk                  /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */
+#define IAC_ICRx_IAF16_Pos         (16U)
+#define IAC_ICRx_IAF16_Msk         (0x1UL << IAC_ICRx_IAF16_Pos)        /*!< 0x00010000 */
+#define IAC_ICRx_IAF16             IAC_ICRx_IAF16_Msk                  /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */
+#define IAC_ICRx_IAF17_Pos         (17U)
+#define IAC_ICRx_IAF17_Msk         (0x1UL << IAC_ICRx_IAF17_Pos)        /*!< 0x00020000 */
+#define IAC_ICRx_IAF17             IAC_ICRx_IAF17_Msk                  /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */
+#define IAC_ICRx_IAF18_Pos         (18U)
+#define IAC_ICRx_IAF18_Msk         (0x1UL << IAC_ICRx_IAF18_Pos)        /*!< 0x00040000 */
+#define IAC_ICRx_IAF18             IAC_ICRx_IAF18_Msk                  /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */
+#define IAC_ICRx_IAF19_Pos         (19U)
+#define IAC_ICRx_IAF19_Msk         (0x1UL << IAC_ICRx_IAF19_Pos)        /*!< 0x00080000 */
+#define IAC_ICRx_IAF19             IAC_ICRx_IAF19_Msk                  /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */
+#define IAC_ICRx_IAF20_Pos         (20U)
+#define IAC_ICRx_IAF20_Msk         (0x1UL << IAC_ICRx_IAF20_Pos)        /*!< 0x00100000 */
+#define IAC_ICRx_IAF20             IAC_ICRx_IAF20_Msk                  /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */
+#define IAC_ICRx_IAF21_Pos         (21U)
+#define IAC_ICRx_IAF21_Msk         (0x1UL << IAC_ICRx_IAF21_Pos)        /*!< 0x00200000 */
+#define IAC_ICRx_IAF21             IAC_ICRx_IAF21_Msk                  /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */
+#define IAC_ICRx_IAF22_Pos         (22U)
+#define IAC_ICRx_IAF22_Msk         (0x1UL << IAC_ICRx_IAF22_Pos)        /*!< 0x00400000 */
+#define IAC_ICRx_IAF22             IAC_ICRx_IAF22_Msk                  /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */
+#define IAC_ICRx_IAF23_Pos         (23U)
+#define IAC_ICRx_IAF23_Msk         (0x1UL << IAC_ICRx_IAF23_Pos)        /*!< 0x00800000 */
+#define IAC_ICRx_IAF23             IAC_ICRx_IAF23_Msk                  /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */
+#define IAC_ICRx_IAF24_Pos         (24U)
+#define IAC_ICRx_IAF24_Msk         (0x1UL << IAC_ICRx_IAF24_Pos)        /*!< 0x01000000 */
+#define IAC_ICRx_IAF24             IAC_ICRx_IAF24_Msk                  /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */
+#define IAC_ICRx_IAF25_Pos         (25U)
+#define IAC_ICRx_IAF25_Msk         (0x1UL << IAC_ICRx_IAF25_Pos)        /*!< 0x02000000 */
+#define IAC_ICRx_IAF25             IAC_ICRx_IAF25_Msk                  /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */
+#define IAC_ICRx_IAF26_Pos         (26U)
+#define IAC_ICRx_IAF26_Msk         (0x1UL << IAC_ICRx_IAF26_Pos)        /*!< 0x04000000 */
+#define IAC_ICRx_IAF26             IAC_ICRx_IAF26_Msk                  /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */
+#define IAC_ICRx_IAF27_Pos         (27U)
+#define IAC_ICRx_IAF27_Msk         (0x1UL << IAC_ICRx_IAF27_Pos)        /*!< 0x08000000 */
+#define IAC_ICRx_IAF27             IAC_ICRx_IAF27_Msk                  /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */
+#define IAC_ICRx_IAF28_Pos         (28U)
+#define IAC_ICRx_IAF28_Msk         (0x1UL << IAC_ICRx_IAF28_Pos)        /*!< 0x10000000 */
+#define IAC_ICRx_IAF28             IAC_ICRx_IAF28_Msk                  /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */
+#define IAC_ICRx_IAF29_Pos         (29U)
+#define IAC_ICRx_IAF29_Msk         (0x1UL << IAC_ICRx_IAF29_Pos)        /*!< 0x20000000 */
+#define IAC_ICRx_IAF29             IAC_ICRx_IAF29_Msk                  /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */
+#define IAC_ICRx_IAF30_Pos         (30U)
+#define IAC_ICRx_IAF30_Msk         (0x1UL << IAC_ICRx_IAF30_Pos)        /*!< 0x40000000 */
+#define IAC_ICRx_IAF30             IAC_ICRx_IAF30_Msk                  /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */
+#define IAC_ICRx_IAF31_Pos         (31U)
+#define IAC_ICRx_IAF31_Msk         (0x1UL << IAC_ICRx_IAF31_Pos)        /*!< 0x80000000 */
+#define IAC_ICRx_IAF31             IAC_ICRx_IAF31_Msk                  /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */
+
+/******************  Bit definition for IAC_IISRx register  *******************/
+#define IAC_IISRx_ILACIN0_Pos      (0U)
+#define IAC_IISRx_ILACIN0_Msk      (0x1UL << IAC_IISRx_ILACIN0_Pos)     /*!< 0x00000001 */
+#define IAC_IISRx_ILACIN0          IAC_IISRx_ILACIN0_Msk               /*!< illegal access input 0 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN1_Pos      (1U)
+#define IAC_IISRx_ILACIN1_Msk      (0x1UL << IAC_IISRx_ILACIN1_Pos)     /*!< 0x00000002 */
+#define IAC_IISRx_ILACIN1          IAC_IISRx_ILACIN1_Msk               /*!< illegal access input 1 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN2_Pos      (2U)
+#define IAC_IISRx_ILACIN2_Msk      (0x1UL << IAC_IISRx_ILACIN2_Pos)     /*!< 0x00000004 */
+#define IAC_IISRx_ILACIN2          IAC_IISRx_ILACIN2_Msk               /*!< illegal access input 2 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN3_Pos      (3U)
+#define IAC_IISRx_ILACIN3_Msk      (0x1UL << IAC_IISRx_ILACIN3_Pos)     /*!< 0x00000008 */
+#define IAC_IISRx_ILACIN3          IAC_IISRx_ILACIN3_Msk               /*!< illegal access input 3 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN4_Pos      (4U)
+#define IAC_IISRx_ILACIN4_Msk      (0x1UL << IAC_IISRx_ILACIN4_Pos)     /*!< 0x00000010 */
+#define IAC_IISRx_ILACIN4          IAC_IISRx_ILACIN4_Msk               /*!< illegal access input 4 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN5_Pos      (5U)
+#define IAC_IISRx_ILACIN5_Msk      (0x1UL << IAC_IISRx_ILACIN5_Pos)     /*!< 0x00000020 */
+#define IAC_IISRx_ILACIN5          IAC_IISRx_ILACIN5_Msk               /*!< illegal access input 5 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN6_Pos      (6U)
+#define IAC_IISRx_ILACIN6_Msk      (0x1UL << IAC_IISRx_ILACIN6_Pos)     /*!< 0x00000040 */
+#define IAC_IISRx_ILACIN6          IAC_IISRx_ILACIN6_Msk               /*!< illegal access input 6 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN7_Pos      (7U)
+#define IAC_IISRx_ILACIN7_Msk      (0x1UL << IAC_IISRx_ILACIN7_Pos)     /*!< 0x00000080 */
+#define IAC_IISRx_ILACIN7          IAC_IISRx_ILACIN7_Msk               /*!< illegal access input 7 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN8_Pos      (8U)
+#define IAC_IISRx_ILACIN8_Msk      (0x1UL << IAC_IISRx_ILACIN8_Pos)     /*!< 0x00000100 */
+#define IAC_IISRx_ILACIN8          IAC_IISRx_ILACIN8_Msk               /*!< illegal access input 8 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN9_Pos      (9U)
+#define IAC_IISRx_ILACIN9_Msk      (0x1UL << IAC_IISRx_ILACIN9_Pos)     /*!< 0x00000200 */
+#define IAC_IISRx_ILACIN9          IAC_IISRx_ILACIN9_Msk               /*!< illegal access input 9 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN10_Pos     (10U)
+#define IAC_IISRx_ILACIN10_Msk     (0x1UL << IAC_IISRx_ILACIN10_Pos)    /*!< 0x00000400 */
+#define IAC_IISRx_ILACIN10         IAC_IISRx_ILACIN10_Msk              /*!< illegal access input 10 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN11_Pos     (11U)
+#define IAC_IISRx_ILACIN11_Msk     (0x1UL << IAC_IISRx_ILACIN11_Pos)    /*!< 0x00000800 */
+#define IAC_IISRx_ILACIN11         IAC_IISRx_ILACIN11_Msk              /*!< illegal access input 11 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN12_Pos     (12U)
+#define IAC_IISRx_ILACIN12_Msk     (0x1UL << IAC_IISRx_ILACIN12_Pos)    /*!< 0x00001000 */
+#define IAC_IISRx_ILACIN12         IAC_IISRx_ILACIN12_Msk              /*!< illegal access input 12 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN13_Pos     (13U)
+#define IAC_IISRx_ILACIN13_Msk     (0x1UL << IAC_IISRx_ILACIN13_Pos)    /*!< 0x00002000 */
+#define IAC_IISRx_ILACIN13         IAC_IISRx_ILACIN13_Msk              /*!< illegal access input 13 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN14_Pos     (14U)
+#define IAC_IISRx_ILACIN14_Msk     (0x1UL << IAC_IISRx_ILACIN14_Pos)    /*!< 0x00004000 */
+#define IAC_IISRx_ILACIN14         IAC_IISRx_ILACIN14_Msk              /*!< illegal access input 14 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN15_Pos     (15U)
+#define IAC_IISRx_ILACIN15_Msk     (0x1UL << IAC_IISRx_ILACIN15_Pos)    /*!< 0x00008000 */
+#define IAC_IISRx_ILACIN15         IAC_IISRx_ILACIN15_Msk              /*!< illegal access input 15 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN16_Pos     (16U)
+#define IAC_IISRx_ILACIN16_Msk     (0x1UL << IAC_IISRx_ILACIN16_Pos)    /*!< 0x00010000 */
+#define IAC_IISRx_ILACIN16         IAC_IISRx_ILACIN16_Msk              /*!< illegal access input 16 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN17_Pos     (17U)
+#define IAC_IISRx_ILACIN17_Msk     (0x1UL << IAC_IISRx_ILACIN17_Pos)    /*!< 0x00020000 */
+#define IAC_IISRx_ILACIN17         IAC_IISRx_ILACIN17_Msk              /*!< illegal access input 17 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN18_Pos     (18U)
+#define IAC_IISRx_ILACIN18_Msk     (0x1UL << IAC_IISRx_ILACIN18_Pos)    /*!< 0x00040000 */
+#define IAC_IISRx_ILACIN18         IAC_IISRx_ILACIN18_Msk              /*!< illegal access input 18 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN19_Pos     (19U)
+#define IAC_IISRx_ILACIN19_Msk     (0x1UL << IAC_IISRx_ILACIN19_Pos)    /*!< 0x00080000 */
+#define IAC_IISRx_ILACIN19         IAC_IISRx_ILACIN19_Msk              /*!< illegal access input 19 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN20_Pos     (20U)
+#define IAC_IISRx_ILACIN20_Msk     (0x1UL << IAC_IISRx_ILACIN20_Pos)    /*!< 0x00100000 */
+#define IAC_IISRx_ILACIN20         IAC_IISRx_ILACIN20_Msk              /*!< illegal access input 20 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN21_Pos     (21U)
+#define IAC_IISRx_ILACIN21_Msk     (0x1UL << IAC_IISRx_ILACIN21_Pos)    /*!< 0x00200000 */
+#define IAC_IISRx_ILACIN21         IAC_IISRx_ILACIN21_Msk              /*!< illegal access input 21 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN22_Pos     (22U)
+#define IAC_IISRx_ILACIN22_Msk     (0x1UL << IAC_IISRx_ILACIN22_Pos)    /*!< 0x00400000 */
+#define IAC_IISRx_ILACIN22         IAC_IISRx_ILACIN22_Msk              /*!< illegal access input 22 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN23_Pos     (23U)
+#define IAC_IISRx_ILACIN23_Msk     (0x1UL << IAC_IISRx_ILACIN23_Pos)    /*!< 0x00800000 */
+#define IAC_IISRx_ILACIN23         IAC_IISRx_ILACIN23_Msk              /*!< illegal access input 23 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN24_Pos     (24U)
+#define IAC_IISRx_ILACIN24_Msk     (0x1UL << IAC_IISRx_ILACIN24_Pos)    /*!< 0x01000000 */
+#define IAC_IISRx_ILACIN24         IAC_IISRx_ILACIN24_Msk              /*!< illegal access input 24 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN25_Pos     (25U)
+#define IAC_IISRx_ILACIN25_Msk     (0x1UL << IAC_IISRx_ILACIN25_Pos)    /*!< 0x02000000 */
+#define IAC_IISRx_ILACIN25         IAC_IISRx_ILACIN25_Msk              /*!< illegal access input 25 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN26_Pos     (26U)
+#define IAC_IISRx_ILACIN26_Msk     (0x1UL << IAC_IISRx_ILACIN26_Pos)    /*!< 0x04000000 */
+#define IAC_IISRx_ILACIN26         IAC_IISRx_ILACIN26_Msk              /*!< illegal access input 26 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN27_Pos     (27U)
+#define IAC_IISRx_ILACIN27_Msk     (0x1UL << IAC_IISRx_ILACIN27_Pos)    /*!< 0x08000000 */
+#define IAC_IISRx_ILACIN27         IAC_IISRx_ILACIN27_Msk              /*!< illegal access input 27 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN28_Pos     (28U)
+#define IAC_IISRx_ILACIN28_Msk     (0x1UL << IAC_IISRx_ILACIN28_Pos)    /*!< 0x10000000 */
+#define IAC_IISRx_ILACIN28         IAC_IISRx_ILACIN28_Msk              /*!< illegal access input 28 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN29_Pos     (29U)
+#define IAC_IISRx_ILACIN29_Msk     (0x1UL << IAC_IISRx_ILACIN29_Pos)    /*!< 0x20000000 */
+#define IAC_IISRx_ILACIN29         IAC_IISRx_ILACIN29_Msk              /*!< illegal access input 29 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN30_Pos     (30U)
+#define IAC_IISRx_ILACIN30_Msk     (0x1UL << IAC_IISRx_ILACIN30_Pos)    /*!< 0x40000000 */
+#define IAC_IISRx_ILACIN30         IAC_IISRx_ILACIN30_Msk              /*!< illegal access input 30 (i = 0 to 31) */
+#define IAC_IISRx_ILACIN31_Pos     (31U)
+#define IAC_IISRx_ILACIN31_Msk     (0x1UL << IAC_IISRx_ILACIN31_Pos)    /*!< 0x80000000 */
+#define IAC_IISRx_ILACIN31         IAC_IISRx_ILACIN31_Msk              /*!< illegal access input 31 (i = 0 to 31) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos                    (2U)
+#define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
+#define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos                       (3U)
+#define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
+#define RNG_CR_IE                           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos                      (5U)
+#define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
+#define RNG_CR_CED                          RNG_CR_CED_Msk
+#define RNG_CR_ARDIS_Pos                    (7U)
+#define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
+#define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
+#define RNG_CR_RNG_CONFIG3_Pos              (8U)
+#define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
+#define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
+#define RNG_CR_NISTC_Pos                    (12U)
+#define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
+#define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
+#define RNG_CR_RNG_CONFIG2_Pos              (13U)
+#define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
+#define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
+#define RNG_CR_CLKDIV_Pos                   (16U)
+#define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
+#define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
+#define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
+#define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
+#define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
+#define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
+#define RNG_CR_RNG_CONFIG1_Pos              (20U)
+#define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
+#define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
+#define RNG_CR_CONDRST_Pos                  (30U)
+#define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
+#define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
+#define RNG_CR_CONFIGLOCK_Pos               (31U)
+#define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
+#define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos                     (0U)
+#define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
+#define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos                     (1U)
+#define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
+#define RNG_SR_CECS                         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos                     (2U)
+#define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
+#define RNG_SR_SECS                         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos                     (5U)
+#define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
+#define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos                     (6U)
+#define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
+#define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
+
+/********************  Bits definition for RNG_HTCR register  *******************/
+#define RNG_HTCR_HTCFG_Pos                  (0U)
+#define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
+#define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_SU_Pos                       (0U)
+#define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                           RTC_TR_SU_Msk
+#define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
+#define RTC_TR_ST_Pos                       (4U)
+#define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                           RTC_TR_ST_Msk
+#define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TR_MNU_Pos                      (8U)
+#define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                          RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TR_MNT_Pos                      (12U)
+#define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                          RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TR_HU_Pos                       (16U)
+#define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                           RTC_TR_HU_Msk
+#define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TR_HT_Pos                       (20U)
+#define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                           RTC_TR_HT_Msk
+#define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TR_PM_Pos                       (22U)
+#define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                           RTC_TR_PM_Msk
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_DU_Pos                       (0U)
+#define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                           RTC_DR_DU_Msk
+#define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
+#define RTC_DR_DT_Pos                       (4U)
+#define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                           RTC_DR_DT_Msk
+#define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_DR_MU_Pos                       (8U)
+#define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                           RTC_DR_MU_Msk
+#define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_DR_MT_Pos                       (12U)
+#define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                           RTC_DR_MT_Msk
+#define RTC_DR_WDU_Pos                      (13U)
+#define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                          RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_DR_YU_Pos                       (16U)
+#define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                           RTC_DR_YU_Msk
+#define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
+#define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
+#define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
+#define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
+#define RTC_DR_YT_Pos                       (20U)
+#define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                           RTC_DR_YT_Msk
+#define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
+#define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
+#define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
+#define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                      (0U)
+#define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_SSR_SS                          RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_ICSR register  ******************/
+#define RTC_ICSR_WUTWF_Pos                  (2U)
+#define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
+#define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
+#define RTC_ICSR_SHPF_Pos                   (3U)
+#define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
+#define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
+#define RTC_ICSR_INITS_Pos                  (4U)
+#define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
+#define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
+#define RTC_ICSR_RSF_Pos                    (5U)
+#define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
+#define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
+#define RTC_ICSR_INITF_Pos                  (6U)
+#define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
+#define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
+#define RTC_ICSR_INIT_Pos                   (7U)
+#define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
+#define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
+#define RTC_ICSR_BIN_Pos                    (8U)
+#define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
+#define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
+#define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
+#define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
+#define RTC_ICSR_BCDU_Pos                   (10U)
+#define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
+#define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
+#define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
+#define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
+#define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
+#define RTC_ICSR_RECALPF_Pos                (16U)
+#define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
+#define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_S_Pos               (0U)
+#define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
+#define RTC_PRER_PREDIV_A_Pos               (16U)
+#define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos                    (0U)
+#define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
+#define RTC_WUTR_WUTOCLR_Pos                (16U)
+#define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
+#define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_WUCKSEL_Pos                  (0U)
+#define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
+#define RTC_CR_TSEDGE_Pos                   (3U)
+#define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
+#define RTC_CR_REFCKON_Pos                  (4U)
+#define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
+#define RTC_CR_BYPSHAD_Pos                  (5U)
+#define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
+#define RTC_CR_FMT_Pos                      (6U)
+#define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                          RTC_CR_FMT_Msk
+#define RTC_CR_SSRUIE_Pos                   (7U)
+#define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
+#define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
+#define RTC_CR_ALRAE_Pos                    (8U)
+#define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
+#define RTC_CR_ALRBE_Pos                    (9U)
+#define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
+#define RTC_CR_WUTE_Pos                     (10U)
+#define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
+#define RTC_CR_TSE_Pos                      (11U)
+#define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                          RTC_CR_TSE_Msk
+#define RTC_CR_ALRAIE_Pos                   (12U)
+#define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
+#define RTC_CR_ALRBIE_Pos                   (13U)
+#define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
+#define RTC_CR_WUTIE_Pos                    (14U)
+#define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
+#define RTC_CR_TSIE_Pos                     (15U)
+#define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
+#define RTC_CR_ADD1H_Pos                    (16U)
+#define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
+#define RTC_CR_SUB1H_Pos                    (17U)
+#define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
+#define RTC_CR_BKP_Pos                      (18U)
+#define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                          RTC_CR_BKP_Msk
+#define RTC_CR_COSEL_Pos                    (19U)
+#define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
+#define RTC_CR_POL_Pos                      (20U)
+#define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                          RTC_CR_POL_Msk
+#define RTC_CR_OSEL_Pos                     (21U)
+#define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
+#define RTC_CR_COE_Pos                      (23U)
+#define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                          RTC_CR_COE_Msk
+#define RTC_CR_ITSE_Pos                     (24U)
+#define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
+#define RTC_CR_TAMPTS_Pos                   (25U)
+#define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
+#define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
+#define RTC_CR_TAMPOE_Pos                   (26U)
+#define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
+#define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
+#define RTC_CR_ALRAFCLR_Pos                 (27U)
+#define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
+#define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
+#define RTC_CR_ALRBFCLR_Pos                 (28U)
+#define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
+#define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
+#define RTC_CR_TAMPALRM_PU_Pos              (29U)
+#define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
+#define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
+#define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
+#define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
+#define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
+#define RTC_CR_OUT2EN_Pos                   (31U)
+#define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
+#define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
+
+/********************  Bits definition for RTC_PRIVCFGR register  *****************/
+#define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
+#define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
+#define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
+#define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
+#define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
+#define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
+#define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
+#define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
+#define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
+#define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
+#define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
+#define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
+#define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
+#define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
+#define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
+#define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
+#define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
+#define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
+#define RTC_PRIVCFGR_PRIV_Pos               (15U)
+#define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
+#define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
+
+/********************  Bits definition for RTC_SECCFGR register  ******************/
+#define RTC_SECCFGR_ALRASEC_Pos             (0U)
+#define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
+#define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
+#define RTC_SECCFGR_ALRBSEC_Pos             (1U)
+#define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
+#define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
+#define RTC_SECCFGR_WUTSEC_Pos              (2U)
+#define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
+#define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
+#define RTC_SECCFGR_TSSEC_Pos               (3U)
+#define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
+#define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
+#define RTC_SECCFGR_CALSEC_Pos              (13U)
+#define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
+#define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
+#define RTC_SECCFGR_INITSEC_Pos             (14U)
+#define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
+#define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
+#define RTC_SECCFGR_SEC_Pos                 (15U)
+#define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
+#define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                     (0U)
+#define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALM_Pos                   (0U)
+#define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
+#define RTC_CALR_LPCAL_Pos                  (12U)
+#define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
+#define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALW16_Pos                 (13U)
+#define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
+#define RTC_CALR_CALW8_Pos                  (14U)
+#define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALP_Pos                   (15U)
+#define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos                (0U)
+#define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos                (31U)
+#define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_SU_Pos                     (0U)
+#define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
+#define RTC_TSTR_ST_Pos                     (4U)
+#define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_TSTR_MNU_Pos                    (8U)
+#define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_TSTR_MNT_Pos                    (12U)
+#define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_TSTR_HU_Pos                     (16U)
+#define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_TSTR_HT_Pos                     (20U)
+#define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_TSTR_PM_Pos                     (22U)
+#define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_DU_Pos                     (0U)
+#define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
+#define RTC_TSDR_DT_Pos                     (4U)
+#define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
+#define RTC_TSDR_MU_Pos                     (8U)
+#define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
+#define RTC_TSDR_MT_Pos                     (12U)
+#define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
+#define RTC_TSDR_WDU_Pos                    (13U)
+#define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos                    (0U)
+#define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
+#define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_SU_Pos                   (0U)
+#define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMAR_ST_Pos                   (4U)
+#define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMAR_MSK1_Pos                 (7U)
+#define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_MNU_Pos                  (8U)
+#define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMAR_MNT_Pos                  (12U)
+#define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMAR_MSK2_Pos                 (15U)
+#define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_HU_Pos                   (16U)
+#define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMAR_HT_Pos                   (20U)
+#define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMAR_PM_Pos                   (22U)
+#define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_MSK3_Pos                 (23U)
+#define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_DU_Pos                   (24U)
+#define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMAR_DT_Pos                   (28U)
+#define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMAR_WDSEL_Pos                (30U)
+#define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_MSK4_Pos                 (31U)
+#define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_SS_Pos                 (0U)
+#define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
+#define RTC_ALRMASSR_MASKSS_Pos             (24U)
+#define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMASSR_SSCLR_Pos              (31U)
+#define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_SU_Pos                   (0U)
+#define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
+#define RTC_ALRMBR_ST_Pos                   (4U)
+#define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
+#define RTC_ALRMBR_MSK1_Pos                 (7U)
+#define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_MNU_Pos                  (8U)
+#define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
+#define RTC_ALRMBR_MNT_Pos                  (12U)
+#define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
+#define RTC_ALRMBR_MSK2_Pos                 (15U)
+#define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_HU_Pos                   (16U)
+#define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
+#define RTC_ALRMBR_HT_Pos                   (20U)
+#define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
+#define RTC_ALRMBR_PM_Pos                   (22U)
+#define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_MSK3_Pos                 (23U)
+#define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_DU_Pos                   (24U)
+#define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
+#define RTC_ALRMBR_DT_Pos                   (28U)
+#define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
+#define RTC_ALRMBR_WDSEL_Pos                (30U)
+#define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_MSK4_Pos                 (31U)
+#define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_SS_Pos                 (0U)
+#define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
+#define RTC_ALRMBSSR_MASKSS_Pos             (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
+#define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
+#define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
+#define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
+#define RTC_ALRMBSSR_SSCLR_Pos              (31U)
+#define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
+#define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
+
+/********************  Bits definition for RTC_SR register  *******************/
+#define RTC_SR_ALRAF_Pos                    (0U)
+#define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
+#define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
+#define RTC_SR_ALRBF_Pos                    (1U)
+#define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
+#define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
+#define RTC_SR_WUTF_Pos                     (2U)
+#define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
+#define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
+#define RTC_SR_TSF_Pos                      (3U)
+#define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
+#define RTC_SR_TSF                          RTC_SR_TSF_Msk
+#define RTC_SR_TSOVF_Pos                    (4U)
+#define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
+#define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
+#define RTC_SR_ITSF_Pos                     (5U)
+#define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
+#define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
+#define RTC_SR_SSRUF_Pos                    (6U)
+#define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
+#define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
+
+/********************  Bits definition for RTC_MISR register  *****************/
+#define RTC_MISR_ALRAMF_Pos                 (0U)
+#define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
+#define RTC_MISR_ALRBMF_Pos                 (1U)
+#define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
+#define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
+#define RTC_MISR_WUTMF_Pos                  (2U)
+#define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
+#define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
+#define RTC_MISR_TSMF_Pos                   (3U)
+#define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
+#define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
+#define RTC_MISR_TSOVMF_Pos                 (4U)
+#define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
+#define RTC_MISR_ITSMF_Pos                  (5U)
+#define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
+#define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
+#define RTC_MISR_SSRUMF_Pos                 (6U)
+#define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
+#define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SMISR register  *****************/
+#define RTC_SMISR_ALRAMF_Pos                (0U)
+#define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
+#define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
+#define RTC_SMISR_ALRBMF_Pos                (1U)
+#define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
+#define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
+#define RTC_SMISR_WUTMF_Pos                 (2U)
+#define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
+#define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
+#define RTC_SMISR_TSMF_Pos                  (3U)
+#define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
+#define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
+#define RTC_SMISR_TSOVMF_Pos                (4U)
+#define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
+#define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
+#define RTC_SMISR_ITSMF_Pos                 (5U)
+#define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
+#define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
+#define RTC_SMISR_SSRUMF_Pos                (6U)
+#define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
+#define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk
+
+/********************  Bits definition for RTC_SCR register  ******************/
+#define RTC_SCR_CALRAF_Pos                  (0U)
+#define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
+#define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
+#define RTC_SCR_CALRBF_Pos                  (1U)
+#define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
+#define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
+#define RTC_SCR_CWUTF_Pos                   (2U)
+#define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
+#define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
+#define RTC_SCR_CTSF_Pos                    (3U)
+#define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
+#define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
+#define RTC_SCR_CTSOVF_Pos                  (4U)
+#define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
+#define RTC_SCR_CITSF_Pos                   (5U)
+#define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
+#define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
+#define RTC_SCR_CSSRUF_Pos                  (6U)
+#define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
+#define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
+
+/********************  Bits definition for RTC_ALRABINR register  ******************/
+#define RTC_ALRABINR_SS_Pos                 (0U)
+#define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
+
+/********************  Bits definition for RTC_ALRBBINR register  ******************/
+#define RTC_ALRBBINR_SS_Pos                 (0U)
+#define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
+#define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*               Secure Advanced Encryption Standard (SAES)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for SAES_CR register  *********************/
+#define SAES_CR_EN_Pos                       (0U)
+#define SAES_CR_EN_Msk                       (0x1UL << SAES_CR_EN_Pos)                /*!< 0x00000001 */
+#define SAES_CR_EN                           SAES_CR_EN_Msk                           /*!< SAES Enable */
+#define SAES_CR_DATATYPE_Pos                 (1U)
+#define SAES_CR_DATATYPE_Msk                 (0x3UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
+#define SAES_CR_DATATYPE                     SAES_CR_DATATYPE_Msk                     /*!< Data type selection */
+#define SAES_CR_DATATYPE_0                   (0x1UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
+#define SAES_CR_DATATYPE_1                   (0x2UL << SAES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
+#define SAES_CR_MODE_Pos                     (3U)
+#define SAES_CR_MODE_Msk                     (0x3UL << SAES_CR_MODE_Pos)              /*!< 0x00000018 */
+#define SAES_CR_MODE                         SAES_CR_MODE_Msk                         /*!< SAES Mode Of Operation */
+#define SAES_CR_MODE_0                       (0x1UL << SAES_CR_MODE_Pos)              /*!< 0x00000008 */
+#define SAES_CR_MODE_1                       (0x2UL << SAES_CR_MODE_Pos)              /*!< 0x00000010 */
+#define SAES_CR_CHMOD_Pos                    (5U)
+#define SAES_CR_CHMOD_Msk                    (0x803UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010060 */
+#define SAES_CR_CHMOD                        SAES_CR_CHMOD_Msk                        /*!< SAES Chaining Mode */
+#define SAES_CR_CHMOD_0                      (0x1UL << SAES_CR_CHMOD_Pos)             /*!< 0x00000020*/
+#define SAES_CR_CHMOD_1                      (0x2UL << SAES_CR_CHMOD_Pos)             /*!< 0x00000040 */
+#define SAES_CR_CHMOD_2                      (0x800UL << SAES_CR_CHMOD_Pos)           /*!< 0x00010000 */
+#define SAES_CR_DMAINEN_Pos                  (11U)
+#define SAES_CR_DMAINEN_Msk                  (0x1UL << SAES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
+#define SAES_CR_DMAINEN                      SAES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
+#define SAES_CR_DMAOUTEN_Pos                 (12U)
+#define SAES_CR_DMAOUTEN_Msk                 (0x1UL << SAES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
+#define SAES_CR_DMAOUTEN                     SAES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
+#define SAES_CR_GCMPH_Pos                    (13U)
+#define SAES_CR_GCMPH_Msk                    (0x3UL << SAES_CR_GCMPH_Pos)             /*!< 0x0006000 */
+#define SAES_CR_GCMPH                        SAES_CR_GCMPH_Msk                        /*!< GCM or CCM phase selection */
+#define SAES_CR_GCMPH_0                      (0x1UL << SAES_CR_GCMPH_Pos)             /*!< 0x00020000 */
+#define SAES_CR_GCMPH_1                      (0x2UL << SAES_CR_GCMPH_Pos)             /*!< 0x00040000 */
+#define SAES_CR_KEYSIZE_Pos                  (18U)
+#define SAES_CR_KEYSIZE_Msk                  (0x1UL << SAES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
+#define SAES_CR_KEYSIZE                      SAES_CR_KEYSIZE_Msk                      /*!< Key size selection */
+#define SAES_CR_KEYPROT_Pos                  (19U)
+#define SAES_CR_KEYPROT_Msk                  (0x1UL << SAES_CR_KEYPROT_Pos)           /*!< 0x00080000 */
+#define SAES_CR_KEYPROT                      SAES_CR_KEYPROT_Msk                      /*!<  Key protection */
+#define SAES_CR_NPBLB_Pos                    (20U)
+#define SAES_CR_NPBLB_Msk                    (0xFUL << SAES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
+#define SAES_CR_NPBLB                        SAES_CR_NPBLB_Msk                        /*!< Number of padding bytes in last block */
+#define SAES_CR_NPBLB_0                      (0x1UL << SAES_CR_NPBLB_Pos)             /*!< 0x00100000 */
+#define SAES_CR_NPBLB_1                      (0x2UL << SAES_CR_NPBLB_Pos)             /*!< 0x00200000 */
+#define SAES_CR_NPBLB_2                      (0x4UL << SAES_CR_NPBLB_Pos)             /*!< 0x00400000 */
+#define SAES_CR_NPBLB_3                      (0x8UL << SAES_CR_NPBLB_Pos)             /*!< 0x00800000 */
+#define SAES_CR_KMOD_Pos                     (24U)
+#define SAES_CR_KMOD_Msk                     (0x3UL << SAES_CR_KMOD_Pos)              /*!< 0x03000000 */
+#define SAES_CR_KMOD                         SAES_CR_KMOD_Msk                         /*!< Key mode selection */
+#define SAES_CR_KMOD_0                       (0x1UL << SAES_CR_KMOD_Pos)              /*!< 0x01000000 */
+#define SAES_CR_KMOD_1                       (0x2UL << SAES_CR_KMOD_Pos)              /*!< 0x02000000 */
+#define SAES_CR_KSHAREID_Pos                 (26U)
+#define SAES_CR_KSHAREID_Msk                 (0x3UL << SAES_CR_KSHAREID_Pos)          /*!< 0x0C000000 */
+#define SAES_CR_KSHAREID                     SAES_CR_KSHAREID_Msk                     /*!< Key Shared ID */
+#define SAES_CR_KSHAREID_0                   (0x1UL << SAES_CR_KSHAREID_Pos)          /*!< 0x04000000 */
+#define SAES_CR_KSHAREID_1                   (0x2UL << SAES_CR_KSHAREID_Pos)          /*!< 0x08000000 */
+#define SAES_CR_KEYSEL_Pos                   (28U)
+#define SAES_CR_KEYSEL_Msk                   (0x7UL << SAES_CR_KEYSEL_Pos)            /*!< 0x70000000 */
+#define SAES_CR_KEYSEL                       SAES_CR_KEYSEL_Msk                       /*!< Key Selection */
+#define SAES_CR_KEYSEL_0                     (0x1UL << SAES_CR_KEYSEL_Pos)            /*!< 0x10000000 */
+#define SAES_CR_KEYSEL_1                     (0x2UL << SAES_CR_KEYSEL_Pos)            /*!< 0x20000000 */
+#define SAES_CR_KEYSEL_2                     (0x4UL << SAES_CR_KEYSEL_Pos)            /*!< 0x40000000 */
+#define SAES_CR_IPRST_Pos                    (31U)
+#define SAES_CR_IPRST_Msk                    (0x1UL << SAES_CR_IPRST_Pos)             /*!< 0x80000000 */
+#define SAES_CR_IPRST                        SAES_CR_IPRST_Msk                        /*!< SAES IP software reset */
+
+/*******************  Bits definition for SAES_SR register  *********************/
+#define SAES_SR_CCF_Pos                      (0U)
+#define SAES_SR_CCF_Msk                      (0x1UL << SAES_SR_CCF_Pos)               /*!< 0x00000001 */
+#define SAES_SR_CCF                          SAES_SR_CCF_Msk                          /*!< Computation Complete Flag */
+#define SAES_SR_RDERR_Pos                    (1U)
+#define SAES_SR_RDERR_Msk                    (0x1UL << SAES_SR_RDERR_Pos)             /*!< 0x00000002 */
+#define SAES_SR_RDERR                        SAES_SR_RDERR_Msk                        /*!< Read Error Flag */
+#define SAES_SR_WRERR_Pos                    (2U)
+#define SAES_SR_WRERR_Msk                    (0x1UL << SAES_SR_WRERR_Pos)             /*!< 0x00000004 */
+#define SAES_SR_WRERR                        SAES_SR_WRERR_Msk                        /*!< Write Error Flag */
+#define SAES_SR_BUSY_Pos                     (3U)
+#define SAES_SR_BUSY_Msk                     (0x1UL << SAES_SR_BUSY_Pos)              /*!< 0x00000008 */
+#define SAES_SR_BUSY                         SAES_SR_BUSY_Msk                         /*!< Busy Flag */
+#define SAES_SR_KEYVALID_Pos                 (7U)
+#define SAES_SR_KEYVALID_Msk                 (0x1UL << SAES_SR_KEYVALID_Pos)          /*!< 0x00000080 */
+#define SAES_SR_KEYVALID                     SAES_SR_KEYVALID_Msk                     /*!< Key valid Flag */
+
+/*******************  Bits definition for SAES_DINR register  *******************/
+#define SAES_DINR_Pos                        (0U)
+#define SAES_DINR_Msk                        (0xFFFFFFFFUL << SAES_DINR_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_DINR                            SAES_DINR_Msk                            /*!< SAES Data Input Register */
+
+/*******************  Bits definition for SAES_DOUTR register  ******************/
+#define SAES_DOUTR_Pos                       (0U)
+#define SAES_DOUTR_Msk                       (0xFFFFFFFFUL << SAES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_DOUTR                           SAES_DOUTR_Msk                           /*!< SAES Data Output Register */
+
+/*******************  Bits definition for SAES_KEYR0 register  ******************/
+#define SAES_KEYR0_Pos                       (0U)
+#define SAES_KEYR0_Msk                       (0xFFFFFFFFUL << SAES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR0                           SAES_KEYR0_Msk                           /*!< SAES cryptographic key, bits [31:0] */
+
+/*******************  Bits definition for SAES_KEYR1 register  ******************/
+#define SAES_KEYR1_Pos                       (0U)
+#define SAES_KEYR1_Msk                       (0xFFFFFFFFUL << SAES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR1                           SAES_KEYR1_Msk                           /*!< SAES cryptographic key, bits [63:32] */
+
+/*******************  Bits definition for SAES_KEYR2 register  ******************/
+#define SAES_KEYR2_Pos                       (0U)
+#define SAES_KEYR2_Msk                       (0xFFFFFFFFUL << SAES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR2                           SAES_KEYR2_Msk                           /*!< SAES cryptographic key, bits [95:64] */
+
+/*******************  Bits definition for SAES_KEYR3 register  ******************/
+#define SAES_KEYR3_Pos                       (0U)
+#define SAES_KEYR3_Msk                       (0xFFFFFFFFUL << SAES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR3                           SAES_KEYR3_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR4 register  ******************/
+#define SAES_KEYR4_Pos                       (0U)
+#define SAES_KEYR4_Msk                       (0xFFFFFFFFUL << SAES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR4                           SAES_KEYR4_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR5 register  ******************/
+#define SAES_KEYR5_Pos                       (0U)
+#define SAES_KEYR5_Msk                       (0xFFFFFFFFUL << SAES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR5                           SAES_KEYR5_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR6 register  ******************/
+#define SAES_KEYR6_Pos                       (0U)
+#define SAES_KEYR6_Msk                       (0xFFFFFFFFUL << SAES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR6                           SAES_KEYR6_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_KEYR7 register  ******************/
+#define SAES_KEYR7_Pos                       (0U)
+#define SAES_KEYR7_Msk                       (0xFFFFFFFFUL << SAES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
+#define SAES_KEYR7                           SAES_KEYR7_Msk                           /*!< SAES cryptographic key, bits [127:96] */
+
+/*******************  Bits definition for SAES_IVR0 register   ******************/
+#define SAES_IVR0_Pos                        (0U)
+#define SAES_IVR0_Msk                        (0xFFFFFFFFUL << SAES_IVR0_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR0                            SAES_IVR0_Msk                            /*!< SAES initialization vector input, bits [31:0] */
+
+/*******************  Bits definition for SAES_IVR1 register   ******************/
+#define SAES_IVR1_Pos                        (0U)
+#define SAES_IVR1_Msk                        (0xFFFFFFFFUL << SAES_IVR1_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR1                            SAES_IVR1_Msk                            /*!< SAES initialization vector input, bits [63:32] */
+
+/*******************  Bits definition for SAES_IVR2 register   ******************/
+#define SAES_IVR2_Pos                        (0U)
+#define SAES_IVR2_Msk                        (0xFFFFFFFFUL << SAES_IVR2_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR2                            SAES_IVR2_Msk                            /*!< SAES initialization vector input, bits [95:64] */
+
+/*******************  Bits definition for SAES_IVR3 register   ******************/
+#define SAES_IVR3_Pos                        (0U)
+#define SAES_IVR3_Msk                        (0xFFFFFFFFUL << SAES_IVR3_Pos)          /*!< 0xFFFFFFFF */
+#define SAES_IVR3                            SAES_IVR3_Msk                            /*!< SAES initialization vector input, bits [127:96] */
+
+/*******************  Bits definition for SAES_DPACFGR register     ******************/
+#define SAES_DPACFGR_REDCFG_Pos              (0U)
+#define SAES_DPACFGR_REDCFG_Msk              (0x3UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000003 */
+#define SAES_DPACFGR_REDCFG                  SAES_DPACFGR_REDCFG_Msk                  /*!< Redundancy configuration*/
+#define SAES_DPACFGR_REDCFG_0                (0x1UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000001 */
+#define SAES_DPACFGR_REDCFG_1                (0x2UL << SAES_DPACFGR_REDCFG_Pos)       /*!< 0x00000002 */
+#define SAES_DPACFGR_RESEED_Pos              (2U)
+#define SAES_DPACFGR_RESEED_Msk              (0x1UL << SAES_DPACFGR_RESEED_Pos)       /*!< 0x00000004 */
+#define SAES_DPACFGR_RESEED                  SAES_DPACFGR_RESEED_Msk                  /*!< Automatic reseed enable */
+#define SAES_DPACFGR_TRIMCFG_Pos             (3U)
+#define SAES_DPACFGR_TRIMCFG_Msk             (0x3UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000018 */
+#define SAES_DPACFGR_TRIMCFG                 SAES_DPACFGR_TRIMCFG_Msk                 /*!< Clock trimming */
+#define SAES_DPACFGR_TRIMCFG_0               (0x1UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000008 */
+#define SAES_DPACFGR_TRIMCFG_1               (0x2UL << SAES_DPACFGR_TRIMCFG_Pos)      /*!< 0x00000010 */
+#define SAES_DPACFGR_CONFIGLOCK_Pos          (31U)
+#define SAES_DPACFGR_CONFIGLOCK_Msk          (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos)   /*!< 0x80000000 */
+#define SAES_DPACFGR_CONFIGLOCK               SAES_DPACFGR_CONFIGLOCK_Msk             /*!< DPA configuration lock */
+
+/*******************  Bits definition for SAES_IER register     ******************/
+#define SAES_IER_CCFIE_Pos                   (0U)
+#define SAES_IER_CCFIE_Msk                   (0x1UL << SAES_IER_CCFIE_Pos)            /*!< 0x00000001 */
+#define SAES_IER_CCFIE                       SAES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
+#define SAES_IER_RWEIE_Pos                   (1U)
+#define SAES_IER_RWEIE_Msk                   (0x1UL << SAES_IER_RWEIE_Pos)            /*!< 0x00000002 */
+#define SAES_IER_RWEIE                       SAES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
+#define SAES_IER_KEIE_Pos                    (2U)
+#define SAES_IER_KEIE_Msk                    (0x1UL << SAES_IER_KEIE_Pos)             /*!< 0x00000004 */
+#define SAES_IER_KEIE                        SAES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
+#define SAES_IER_RNGEIE_Pos                  (3U)
+#define SAES_IER_RNGEIE_Msk                  (0x1UL << SAES_IER_RNGEIE_Pos)           /*!< 0x00000008 */
+#define SAES_IER_RNGEIE                      SAES_IER_RNGEIE_Msk                      /*!< RNG error interrupt enable */
+
+/*******************  Bits definition for SAES_ISR register     ******************/
+#define SAES_ISR_CCF_Pos                     (0U)
+#define SAES_ISR_CCF_Msk                     (0x1UL << SAES_ISR_CCF_Pos)              /*!< 0x00000001 */
+#define SAES_ISR_CCF                         SAES_ISR_CCF_Msk                         /*!< Computation complete flag */
+#define SAES_ISR_RWEIF_Pos                   (1U)
+#define SAES_ISR_RWEIF_Msk                   (0x1UL << SAES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
+#define SAES_ISR_RWEIF                       SAES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
+#define SAES_ISR_KEIF_Pos                    (2U)
+#define SAES_ISR_KEIF_Msk                    (0x1UL << SAES_ISR_KEIF_Pos)             /*!< 0x00000004 */
+#define SAES_ISR_KEIF                        SAES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
+#define SAES_ISR_RNGEIF_Pos                  (3U)
+#define SAES_ISR_RNGEIF_Msk                  (0x1UL << SAES_ISR_RNGEIF_Pos)           /*!< 0x00000008 */
+#define SAES_ISR_RNGEIF                      SAES_ISR_RNGEIF_Msk                      /*!< RNG error interrupt flag */
+
+/*******************  Bits definition for SAES_ICR register     ******************/
+#define SAES_ICR_CCF_Pos                     (0U)
+#define SAES_ICR_CCF_Msk                     (0x1UL << SAES_ICR_CCF_Pos)              /*!< 0x00000001 */
+#define SAES_ICR_CCF                         SAES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
+#define SAES_ICR_RWEIF_Pos                   (1U)
+#define SAES_ICR_RWEIF_Msk                   (0x1UL << SAES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
+#define SAES_ICR_RWEIF                       SAES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
+#define SAES_ICR_KEIF_Pos                    (2U)
+#define SAES_ICR_KEIF_Msk                    (0x1UL << SAES_ICR_KEIF_Pos)             /*!< 0x00000004 */
+#define SAES_ICR_KEIF                        SAES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
+#define SAES_ICR_RNGEIF_Pos                  (3U)
+#define SAES_ICR_RNGEIF_Msk                  (0x1UL << SAES_ICR_RNGEIF_Pos)           /*!< 0x00000008 */
+#define SAES_ICR_RNGEIF                      SAES_ICR_RNGEIF_Msk                      /*!< RNG error interrupt flag clear */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos                  (0U)
+#define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
+#define SAI_GCR_SYNCOUT_Pos                 (4U)
+#define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos                   (0U)
+#define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
+#define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
+#define SAI_xCR1_PRTCFG_Pos                 (2U)
+#define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
+#define SAI_xCR1_DS_Pos                     (5U)
+#define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
+#define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
+#define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
+#define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
+#define SAI_xCR1_LSBFIRST_Pos               (8U)
+#define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos                  (9U)
+#define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
+#define SAI_xCR1_SYNCEN_Pos                 (10U)
+#define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
+#define SAI_xCR1_MONO_Pos                   (12U)
+#define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
+#define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos                (13U)
+#define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos                  (16U)
+#define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos                  (17U)
+#define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos                  (19U)
+#define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
+#define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
+#define SAI_xCR1_MCKDIV_Pos                 (20U)
+#define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
+#define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
+#define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
+#define SAI_xCR1_OSR_Pos                    (26U)
+#define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
+#define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
+#define SAI_xCR1_MCKEN_Pos                  (27U)
+#define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos                    (0U)
+#define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
+#define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
+#define SAI_xCR2_FFLUSH_Pos                 (3U)
+#define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos                   (4U)
+#define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
+#define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos                   (5U)
+#define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
+#define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos                (6U)
+#define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
+#define SAI_xCR2_MUTECNT_Pos                (7U)
+#define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
+#define SAI_xCR2_CPL_Pos                    (13U)
+#define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
+#define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos                   (14U)
+#define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
+#define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos                   (0U)
+#define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
+#define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
+#define SAI_xFRCR_FSALL_Pos                 (8U)
+#define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
+#define SAI_xFRCR_FSDEF_Pos                 (16U)
+#define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos                 (17U)
+#define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos                 (18U)
+#define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos                (0U)
+#define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
+#define SAI_xSLOTR_SLOTSZ_Pos               (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
+#define SAI_xSLOTR_NBSLOT_Pos               (8U)
+#define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
+#define SAI_xSLOTR_SLOTEN_Pos               (16U)
+#define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos               (0U)
+#define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos              (1U)
+#define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos               (2U)
+#define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos                 (3U)
+#define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos                (4U)
+#define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos               (5U)
+#define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos               (6U)
+#define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos                  (0U)
+#define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos                 (1U)
+#define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos                  (2U)
+#define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos                    (3U)
+#define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos                   (4U)
+#define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos                  (5U)
+#define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos                  (6U)
+#define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
+#define SAI_xSR_FLVL_Pos                    (16U)
+#define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
+#define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos              (0U)
+#define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos             (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos              (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos                (3U)
+#define SAI_xCLRFR_CFREQ_Msk                (0x1UL << SAI_xCLRFR_CFREQ_Pos)         /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ                    SAI_xCLRFR_CFREQ_Msk                    /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos               (4U)
+#define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos              (5U)
+#define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos              (6U)
+#define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos                    (0U)
+#define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA                        SAI_xDR_DATA_Msk
+
+/******************  Bit definition for SAI_PDMCR register  *******************/
+#define SAI_PDMCR_PDMEN_Pos                 (0U)
+#define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
+#define SAI_PDMCR_MICNBR_Pos                (4U)
+#define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
+#define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
+#define SAI_PDMCR_CKEN1_Pos                 (8U)
+#define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
+#define SAI_PDMCR_CKEN2_Pos                 (9U)
+#define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
+#define SAI_PDMCR_CKEN3_Pos                 (10U)
+#define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
+#define SAI_PDMCR_CKEN4_Pos                 (11U)
+#define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos               (0U)
+#define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
+#define SAI_PDMDLY_DLYM1R_Pos               (4U)
+#define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
+#define SAI_PDMDLY_DLYM2L_Pos               (8U)
+#define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
+#define SAI_PDMDLY_DLYM2R_Pos               (12U)
+#define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
+#define SAI_PDMDLY_DLYM3L_Pos               (16U)
+#define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
+#define SAI_PDMDLY_DLYM3R_Pos               (20U)
+#define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
+#define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
+#define SAI_PDMDLY_DLYM4L_Pos               (24U)
+#define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
+#define SAI_PDMDLY_DLYM4R_Pos               (28U)
+#define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
+#define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos             (0U)
+#define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos             (2U)
+#define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos           (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos              (4U)
+#define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos              (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos              (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_WIDBUS_Pos              (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
+#define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos                 (18U)
+#define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos                (0U)
+#define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos              (0U)
+#define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos              (6U)
+#define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos               (7U)
+#define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
+#define SDMMC_CMD_WAITRESP_Pos              (8U)
+#define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITINT_Pos               (10U)
+#define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos              (11U)
+#define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos                (12U)
+#define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos                (13U)
+#define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos              (14U)
+#define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos                (15U)
+#define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos           (0U)
+#define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos           (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos                (0U)
+#define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos               (1U)
+#define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos              (2U)
+#define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+#define SDMMC_DCTRL_RWSTART_Pos             (8U)
+#define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos              (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos               (10U)
+#define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos              (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos             (13U)
+#define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos              (0U)
+#define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos              (1U)
+#define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos              (2U)
+#define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos              (3U)
+#define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos              (4U)
+#define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos               (5U)
+#define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos               (6U)
+#define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos               (7U)
+#define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos               (8U)
+#define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos                 (9U)
+#define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos               (10U)
+#define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos                (11U)
+#define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos               (12U)
+#define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos               (13U)
+#define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos              (14U)
+#define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos              (15U)
+#define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos               (16U)
+#define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos               (17U)
+#define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos               (18U)
+#define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos               (19U)
+#define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos                (20U)
+#define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos             (21U)
+#define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos                (22U)
+#define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos               (23U)
+#define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos                (25U)
+#define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos                (26U)
+#define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos                (27U)
+#define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos               (28U)
+#define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos             (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos             (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos             (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos              (5U)
+#define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos              (6U)
+#define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos              (7U)
+#define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos              (8U)
+#define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos                (9U)
+#define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos              (10U)
+#define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos               (11U)
+#define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos               (22U)
+#define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos              (23U)
+#define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos               (25U)
+#define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos               (26U)
+#define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos               (27U)
+#define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos              (28U)
+#define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos            (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos            (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos            (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos            (8U)
+#define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos              (9U)
+#define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos            (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos             (11U)
+#define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
+#define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos             (22U)
+#define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos            (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos             (25U)
+#define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos             (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos            (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFOTHR register  *******************/
+#define SDMMC_FIFOTHR_THR_Pos               (0U)
+#define SDMMC_FIFOTHR_THR_Msk               (0xFUL << SDMMC_FIFOTHR_THR_Pos)        /*!< 0x0000000F */
+#define SDMMC_FIFOTHR_THR                   SDMMC_FIFOTHR_THR_Msk                   /*!<FIFO threshold */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos             (0U)
+#define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos               (0U)
+#define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos            (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos        (6U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0x7FFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0001FFC0 */
+#define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk              /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASER register  ***************/
+#define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */
+
+/*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
+#define SDMMC_IDMALAR_IDMALA_Pos            (0U)
+#define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
+#define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
+#define SDMMC_IDMALAR_ABR_Pos               (29U)
+#define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
+#define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
+#define SDMMC_IDMALAR_ULS_Pos               (30U)
+#define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
+#define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
+#define SDMMC_IDMALAR_ULA_Pos               (31U)
+#define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
+#define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */
+
+/*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
+#define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos                     (0U)
+#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
+#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
+#define SPI_CR1_MASRX_Pos                   (8U)
+#define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
+#define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
+#define SPI_CR1_CSTART_Pos                  (9U)
+#define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
+#define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
+#define SPI_CR1_CSUSP_Pos                   (10U)
+#define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
+#define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
+#define SPI_CR1_HDDIR_Pos                   (11U)
+#define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
+#define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
+#define SPI_CR1_SSI_Pos                     (12U)
+#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
+#define SPI_CR1_CRC33_17_Pos                (13U)
+#define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
+#define SPI_CR1_RCRCINI_Pos                 (14U)
+#define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
+#define SPI_CR1_TCRCINI_Pos                 (15U)
+#define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
+#define SPI_CR1_IOLOCK_Pos                  (16U)
+#define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSIZE_Pos                   (0U)
+#define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
+
+/*******************  Bit definition for SPI_CFG1 register  *******************/
+#define SPI_CFG1_DSIZE_Pos                  (0U)
+#define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
+#define SPI_CFG1_FTHLV_Pos                  (5U)
+#define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
+#define SPI_CFG1_UDRCFG_Pos                 (9U)
+#define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
+#define SPI_CFG1_RXDMAEN_Pos                (14U)
+#define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
+#define SPI_CFG1_TXDMAEN_Pos                (15U)
+#define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
+#define SPI_CFG1_CRCSIZE_Pos                (16U)
+#define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
+#define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
+#define SPI_CFG1_CRCEN_Pos                  (22U)
+#define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
+#define SPI_CFG1_MBR_Pos                    (28U)
+#define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
+#define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
+#define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
+#define SPI_CFG1_BPASS_Pos                  (31U)
+#define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
+#define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
+
+/*******************  Bit definition for SPI_CFG2 register  *******************/
+#define SPI_CFG2_MSSI_Pos                   (0U)
+#define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
+#define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
+#define SPI_CFG2_MIDI_Pos                   (4U)
+#define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
+#define SPI_CFG2_RDIOM_Pos                  (13U)
+#define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
+#define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
+#define SPI_CFG2_RDIOP_Pos                  (14U)
+#define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
+#define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
+#define SPI_CFG2_IOSWP_Pos                  (15U)
+#define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
+#define SPI_CFG2_COMM_Pos                   (17U)
+#define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
+#define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
+#define SPI_CFG2_SP_Pos                     (19U)
+#define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
+#define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
+#define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
+#define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
+#define SPI_CFG2_MASTER_Pos                 (22U)
+#define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
+#define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
+#define SPI_CFG2_LSBFRST_Pos                (23U)
+#define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
+#define SPI_CFG2_CPHA_Pos                   (24U)
+#define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
+#define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
+#define SPI_CFG2_CPOL_Pos                   (25U)
+#define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
+#define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
+#define SPI_CFG2_SSM_Pos                    (26U)
+#define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
+#define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
+#define SPI_CFG2_SSIOP_Pos                  (28U)
+#define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos                   (29U)
+#define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
+#define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos                   (30U)
+#define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
+#define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
+#define SPI_CFG2_AFCNTR_Pos                 (31U)
+#define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos                   (0U)
+#define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
+#define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
+#define SPI_IER_TXPIE_Pos                   (1U)
+#define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
+#define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
+#define SPI_IER_DXPIE_Pos                   (2U)
+#define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
+#define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
+#define SPI_IER_EOTIE_Pos                   (3U)
+#define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
+#define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
+#define SPI_IER_TXTFIE_Pos                  (4U)
+#define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
+#define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
+#define SPI_IER_UDRIE_Pos                   (5U)
+#define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
+#define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
+#define SPI_IER_OVRIE_Pos                   (6U)
+#define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
+#define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
+#define SPI_IER_CRCEIE_Pos                  (7U)
+#define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
+#define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
+#define SPI_IER_TIFREIE_Pos                 (8U)
+#define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
+#define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos                  (9U)
+#define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
+#define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
+
+/*******************  Bit definition for SPI_SR register  *********************/
+#define SPI_SR_RXP_Pos                      (0U)
+#define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
+#define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_TXP_Pos                      (1U)
+#define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
+#define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
+#define SPI_SR_DXP_Pos                      (2U)
+#define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
+#define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_EOT_Pos                      (3U)
+#define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
+#define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
+#define SPI_SR_TXTF_Pos                     (4U)
+#define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
+#define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
+#define SPI_SR_UDR_Pos                      (5U)
+#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
+#define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
+#define SPI_SR_OVR_Pos                      (6U)
+#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
+#define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
+#define SPI_SR_CRCE_Pos                     (7U)
+#define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
+#define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
+#define SPI_SR_TIFRE_Pos                    (8U)
+#define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
+#define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
+#define SPI_SR_MODF_Pos                     (9U)
+#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
+#define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
+#define SPI_SR_SUSP_Pos                     (11U)
+#define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
+#define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
+#define SPI_SR_TXC_Pos                      (12U)
+#define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
+#define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos                   (13U)
+#define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
+#define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
+#define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos                    (15U)
+#define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
+#define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
+#define SPI_SR_CTSIZE_Pos                   (16U)
+#define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
+
+/*******************  Bit definition for SPI_IFCR register  *******************/
+#define SPI_IFCR_EOTC_Pos                   (3U)
+#define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
+#define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
+#define SPI_IFCR_TXTFC_Pos                  (4U)
+#define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos                   (5U)
+#define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
+#define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
+#define SPI_IFCR_OVRC_Pos                   (6U)
+#define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
+#define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
+#define SPI_IFCR_CRCEC_Pos                  (7U)
+#define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
+#define SPI_IFCR_TIFREC_Pos                 (8U)
+#define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
+#define SPI_IFCR_MODFC_Pos                  (9U)
+#define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
+#define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
+#define SPI_IFCR_SUSPC_Pos                  (11U)
+#define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
+
+/*******************  Bit definition for SPI_TXDR register  *******************/
+#define SPI_TXDR_TXDR_Pos                   (0U)
+#define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  *******************/
+#define SPI_RXDR_RXDR_Pos                   (0U)
+#define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ****************/
+#define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */
+
+/*******************  Bit definition for SPI_TXCRC register  ******************/
+#define SPI_TXCRC_TXCRC_Pos                 (0U)
+#define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ******************/
+#define SPI_RXCRC_RXCRC_Pos                 (0U)
+#define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ******************/
+#define SPI_UDRDR_UDRDR_Pos                 (0U)
+#define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */
+
+/*******************  Bits definition for SPI_I2SCFGR register  ***************/
+#define SPI_I2SCFGR_I2SMOD_Pos              (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)        /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk                  /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos              (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk              (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk                  /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2                (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)        /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos              (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk                  /*!<I2SSTD[1:0] I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)        /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)       /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk                 /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_DATLEN_Pos              (8U)
+#define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk                  /*!<DATLEN[1:0] Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)        /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos               (10U)
+#define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)         /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk                   /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos               (11U)
+#define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)         /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk                   /*!<Serial audio clock polarity */
+#define SPI_I2SCFGR_FIXCH_Pos               (12U)
+#define SPI_I2SCFGR_FIXCH_Msk               (0x1UL << SPI_I2SCFGR_FIXCH_Pos)         /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH                   SPI_I2SCFGR_FIXCH_Msk                   /*!<Fixed channel length in SLAVE */
+#define SPI_I2SCFGR_WSINV_Pos               (13U)
+#define SPI_I2SCFGR_WSINV_Msk               (0x1UL << SPI_I2SCFGR_WSINV_Pos)         /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV                   SPI_I2SCFGR_WSINV_Msk                   /*!<Word select inversion */
+#define SPI_I2SCFGR_DATFMT_Pos              (14U)
+#define SPI_I2SCFGR_DATFMT_Msk              (0x1UL << SPI_I2SCFGR_DATFMT_Pos)        /*!< 0x00003000 */
+#define SPI_I2SCFGR_DATFMT                  SPI_I2SCFGR_DATFMT_Msk                  /*!<Data format */
+#define SPI_I2SCFGR_I2SDIV_Pos              (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk              (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)       /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV                  SPI_I2SCFGR_I2SDIV_Msk                  /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos                 (24U)
+#define SPI_I2SCFGR_ODD_Msk                 (0x1UL << SPI_I2SCFGR_ODD_Pos)           /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD                     SPI_I2SCFGR_ODD_Msk                     /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos               (25U)
+#define SPI_I2SCFGR_MCKOE_Msk               (0x1UL << SPI_I2SCFGR_MCKOE_Pos)         /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE                   SPI_I2SCFGR_MCKOE_Msk                   /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFRXEN_Pos       (0U)
+#define SPDIFRX_CR_SPDIFRXEN_Msk       (0x3UL << SPDIFRX_CR_SPDIFRXEN_Pos)     /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFRXEN           SPDIFRX_CR_SPDIFRXEN_Msk                /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_SPDIFRXEN_0         (0x01UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000001 */
+#define SPDIFRX_CR_SPDIFRXEN_1         (0x02UL << SPDIFRX_CR_SPDIFRXEN_Pos)    /*!< 0x00000002 */
+#define SPDIFRX_CR_RXDMAEN_Pos         (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk         (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN             SPDIFRX_CR_RXDMAEN_Msk                  /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos          (3U)
+#define SPDIFRX_CR_RXSTEO_Msk          (0x1UL << SPDIFRX_CR_RXSTEO_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO              SPDIFRX_CR_RXSTEO_Msk                   /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos           (4U)
+#define SPDIFRX_CR_DRFMT_Msk           (0x3UL << SPDIFRX_CR_DRFMT_Pos)         /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT               SPDIFRX_CR_DRFMT_Msk                    /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos            (6U)
+#define SPDIFRX_CR_PMSK_Msk            (0x1UL << SPDIFRX_CR_PMSK_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK                SPDIFRX_CR_PMSK_Msk                     /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos            (7U)
+#define SPDIFRX_CR_VMSK_Msk            (0x1UL << SPDIFRX_CR_VMSK_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK                SPDIFRX_CR_VMSK_Msk                     /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos           (8U)
+#define SPDIFRX_CR_CUMSK_Msk           (0x1UL << SPDIFRX_CR_CUMSK_Pos)         /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK               SPDIFRX_CR_CUMSK_Msk                    /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos           (9U)
+#define SPDIFRX_CR_PTMSK_Msk           (0x1UL << SPDIFRX_CR_PTMSK_Pos)         /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK               SPDIFRX_CR_PTMSK_Msk                    /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos         (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk         (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)       /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN             SPDIFRX_CR_CBDMAEN_Msk                  /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos           (11U)
+#define SPDIFRX_CR_CHSEL_Msk           (0x1UL << SPDIFRX_CR_CHSEL_Pos)         /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL               SPDIFRX_CR_CHSEL_Msk                    /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos            (12U)
+#define SPDIFRX_CR_NBTR_Msk            (0x3UL << SPDIFRX_CR_NBTR_Pos)          /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR                SPDIFRX_CR_NBTR_Msk                     /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos             (14U)
+#define SPDIFRX_CR_WFA_Msk             (0x1UL << SPDIFRX_CR_WFA_Pos)           /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA                 SPDIFRX_CR_WFA_Msk                      /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos           (16U)
+#define SPDIFRX_CR_INSEL_Msk           (0x7UL << SPDIFRX_CR_INSEL_Pos)         /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL               SPDIFRX_CR_INSEL_Msk                    /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos           (20U)
+#define SPDIFRX_CR_CKSEN_Msk           (0x1UL << SPDIFRX_CR_CKSEN_Pos)         /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN               SPDIFRX_CR_CKSEN_Msk                    /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos        (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk        (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)      /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN            SPDIFRX_CR_CKSBKPEN_Msk                 /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos         (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk         (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)       /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE             SPDIFRX_IMR_RXNEIE_Msk                  /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos        (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk        (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)      /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE            SPDIFRX_IMR_CSRNEIE_Msk                 /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos         (2U)
+#define SPDIFRX_IMR_PERRIE_Msk         (0x1UL << SPDIFRX_IMR_PERRIE_Pos)       /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE             SPDIFRX_IMR_PERRIE_Msk                  /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos          (3U)
+#define SPDIFRX_IMR_OVRIE_Msk          (0x1UL << SPDIFRX_IMR_OVRIE_Pos)        /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE              SPDIFRX_IMR_OVRIE_Msk                   /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos         (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk         (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE             SPDIFRX_IMR_SBLKIE_Msk                  /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos        (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk        (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)      /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE            SPDIFRX_IMR_SYNCDIE_Msk                 /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos          (6U)
+#define SPDIFRX_IMR_IFEIE_Msk          (0x1UL << SPDIFRX_IMR_IFEIE_Pos)        /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE              SPDIFRX_IMR_IFEIE_Msk                   /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos            (0U)
+#define SPDIFRX_SR_RXNE_Msk            (0x1UL << SPDIFRX_SR_RXNE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE                SPDIFRX_SR_RXNE_Msk                     /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos           (1U)
+#define SPDIFRX_SR_CSRNE_Msk           (0x1UL << SPDIFRX_SR_CSRNE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE               SPDIFRX_SR_CSRNE_Msk                    /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos            (2U)
+#define SPDIFRX_SR_PERR_Msk            (0x1UL << SPDIFRX_SR_PERR_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR                SPDIFRX_SR_PERR_Msk                     /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos             (3U)
+#define SPDIFRX_SR_OVR_Msk             (0x1UL << SPDIFRX_SR_OVR_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR                 SPDIFRX_SR_OVR_Msk                      /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos             (4U)
+#define SPDIFRX_SR_SBD_Msk             (0x1UL << SPDIFRX_SR_SBD_Pos)           /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD                 SPDIFRX_SR_SBD_Msk                      /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos           (5U)
+#define SPDIFRX_SR_SYNCD_Msk           (0x1UL << SPDIFRX_SR_SYNCD_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD               SPDIFRX_SR_SYNCD_Msk                    /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos            (6U)
+#define SPDIFRX_SR_FERR_Msk            (0x1UL << SPDIFRX_SR_FERR_Pos)          /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR                SPDIFRX_SR_FERR_Msk                     /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos            (7U)
+#define SPDIFRX_SR_SERR_Msk            (0x1UL << SPDIFRX_SR_SERR_Pos)          /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR                SPDIFRX_SR_SERR_Msk                     /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos            (8U)
+#define SPDIFRX_SR_TERR_Msk            (0x1UL << SPDIFRX_SR_TERR_Pos)          /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR                SPDIFRX_SR_TERR_Msk                     /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos          (16U)
+#define SPDIFRX_SR_WIDTH5_Msk          (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)     /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5              SPDIFRX_SR_WIDTH5_Msk                   /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos        (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk        (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)      /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF            SPDIFRX_IFCR_PERRCF_Msk                 /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos         (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk         (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)       /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF             SPDIFRX_IFCR_OVRCF_Msk                  /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos         (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk         (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)       /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF             SPDIFRX_IFCR_SBDCF_Msk                  /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos       (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk       (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)     /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF           SPDIFRX_IFCR_SYNCDCF_Msk                /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos             (0U)
+#define SPDIFRX_DR0_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)      /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR                 SPDIFRX_DR0_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos             (24U)
+#define SPDIFRX_DR0_PE_Msk             (0x1UL << SPDIFRX_DR0_PE_Pos)           /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE                 SPDIFRX_DR0_PE_Msk                      /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos              (25U)
+#define SPDIFRX_DR0_V_Msk              (0x1UL << SPDIFRX_DR0_V_Pos)            /*!< 0x02000000 */
+#define SPDIFRX_DR0_V                  SPDIFRX_DR0_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos              (26U)
+#define SPDIFRX_DR0_U_Msk              (0x1UL << SPDIFRX_DR0_U_Pos)            /*!< 0x04000000 */
+#define SPDIFRX_DR0_U                  SPDIFRX_DR0_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos              (27U)
+#define SPDIFRX_DR0_C_Msk              (0x1UL << SPDIFRX_DR0_C_Pos)            /*!< 0x08000000 */
+#define SPDIFRX_DR0_C                  SPDIFRX_DR0_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos             (28U)
+#define SPDIFRX_DR0_PT_Msk             (0x3UL << SPDIFRX_DR0_PT_Pos)           /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT                 SPDIFRX_DR0_PT_Msk                      /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos             (8U)
+#define SPDIFRX_DR1_DR_Msk             (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)      /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR                 SPDIFRX_DR1_DR_Msk                      /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos             (4U)
+#define SPDIFRX_DR1_PT_Msk             (0x3UL << SPDIFRX_DR1_PT_Pos)           /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT                 SPDIFRX_DR1_PT_Msk                      /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos              (3U)
+#define SPDIFRX_DR1_C_Msk              (0x1UL << SPDIFRX_DR1_C_Pos)            /*!< 0x00000008 */
+#define SPDIFRX_DR1_C                  SPDIFRX_DR1_C_Msk                       /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos              (2U)
+#define SPDIFRX_DR1_U_Msk              (0x1UL << SPDIFRX_DR1_U_Pos)            /*!< 0x00000004 */
+#define SPDIFRX_DR1_U                  SPDIFRX_DR1_U_Msk                       /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos              (1U)
+#define SPDIFRX_DR1_V_Msk              (0x1UL << SPDIFRX_DR1_V_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_DR1_V                  SPDIFRX_DR1_V_Msk                       /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos             (0U)
+#define SPDIFRX_DR1_PE_Msk             (0x1UL << SPDIFRX_DR1_PE_Pos)           /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE                 SPDIFRX_DR1_PE_Msk                      /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register     (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos          (16U)
+#define SPDIFRX_DR1_DRNL1_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)     /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1              SPDIFRX_DR1_DRNL1_Msk                   /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos          (0U)
+#define SPDIFRX_DR1_DRNL2_Msk          (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)     /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2              SPDIFRX_DR1_DRNL2_Msk                   /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos            (0U)
+#define SPDIFRX_CSR_USR_Msk            (0xFFFFUL << SPDIFRX_CSR_USR_Pos)       /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR                SPDIFRX_CSR_USR_Msk                     /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos             (16U)
+#define SPDIFRX_CSR_CS_Msk             (0xFFUL << SPDIFRX_CSR_CS_Pos)          /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS                 SPDIFRX_CSR_CS_Msk                      /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos            (24U)
+#define SPDIFRX_CSR_SOB_Msk            (0x1UL << SPDIFRX_CSR_SOB_Pos)          /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB                SPDIFRX_CSR_SOB_Msk                     /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos            (0U)
+#define SPDIFRX_DIR_THI_Msk            (0x1FFFUL << SPDIFRX_DIR_THI_Pos)       /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI                SPDIFRX_DIR_THI_Msk                     /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos            (16U)
+#define SPDIFRX_DIR_TLO_Msk            (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)       /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO                SPDIFRX_DIR_TLO_Msk                     /*!<Threshold HIGH     */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_BOOTCR register  ****************/
+#define SYSCFG_BOOTCR_BOOT0_PD_Pos          (0U)
+#define SYSCFG_BOOTCR_BOOT0_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT0_PD_Pos)   /*!< 0x00000001 */
+#define SYSCFG_BOOTCR_BOOT0_PD              SYSCFG_BOOTCR_BOOT0_PD_Msk              /*!< BOOT0 pin pull-down disable */
+#define SYSCFG_BOOTCR_BOOT1_PD_Pos          (1U)
+#define SYSCFG_BOOTCR_BOOT1_PD_Msk          (0x1UL << SYSCFG_BOOTCR_BOOT1_PD_Pos)   /*!< 0x00000002 */
+#define SYSCFG_BOOTCR_BOOT1_PD              SYSCFG_BOOTCR_BOOT1_PD_Msk              /*!< BOOT1 pin pull-down disable */
+
+/******************  Bit definition for SYSCFG_CM55CR register  ****************/
+#define SYSCFG_CM55CR_FPU_IT_EN_Pos         (0U)
+#define SYSCFG_CM55CR_FPU_IT_EN_Msk         (0x3FUL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x0000003F */
+#define SYSCFG_CM55CR_FPU_IT_EN             SYSCFG_CM55CR_FPU_IT_EN_Msk             /*!< Enable FPU exception */
+#define SYSCFG_CM55CR_FPU_IT_EN_0           (0x1UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55CR_FPU_IT_EN_1           (0x2UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55CR_FPU_IT_EN_2           (0x4UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55CR_FPU_IT_EN_3           (0x8UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)   /*!< 0x00000008 */
+#define SYSCFG_CM55CR_FPU_IT_EN_4           (0x10UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000010 */
+#define SYSCFG_CM55CR_FPU_IT_EN_5           (0x20UL << SYSCFG_CM55CR_FPU_IT_EN_Pos)  /*!< 0x00000020 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Pos      (16U)
+#define SYSCFG_CM55CR_LOCKSVTAIRCR_Msk      (0x1UL << SYSCFG_CM55CR_LOCKSVTAIRCR_Pos) /*!< 0x00010000 */
+#define SYSCFG_CM55CR_LOCKSVTAIRCR          SYSCFG_CM55CR_LOCKSVTAIRCR_Msk
+#define SYSCFG_CM55CR_LOCKNSVTOR_Pos        (17U)
+#define SYSCFG_CM55CR_LOCKNSVTOR_Msk        (0x1UL << SYSCFG_CM55CR_LOCKNSVTOR_Pos) /*!< 0x00020000 */
+#define SYSCFG_CM55CR_LOCKNSVTOR            SYSCFG_CM55CR_LOCKNSVTOR_Msk            /*!< Prevent changes to the non-secure vector table base address */
+#define SYSCFG_CM55CR_LOCKSMPU_Pos          (18U)
+#define SYSCFG_CM55CR_LOCKSMPU_Msk          (0x1UL << SYSCFG_CM55CR_LOCKSMPU_Pos)   /*!< 0x00040000 */
+#define SYSCFG_CM55CR_LOCKSMPU              SYSCFG_CM55CR_LOCKSMPU_Msk              /*!< Prevent changes to programmed secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKNSMPU_Pos         (19U)
+#define SYSCFG_CM55CR_LOCKNSMPU_Msk         (0x1UL << SYSCFG_CM55CR_LOCKNSMPU_Pos)  /*!< 0x00080000 */
+#define SYSCFG_CM55CR_LOCKNSMPU             SYSCFG_CM55CR_LOCKNSMPU_Msk             /*!< Prevent changes to programmed non-secure MPU memory regions */
+#define SYSCFG_CM55CR_LOCKSAU_Pos           (20U)
+#define SYSCFG_CM55CR_LOCKSAU_Msk           (0x1UL << SYSCFG_CM55CR_LOCKSAU_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CM55CR_LOCKSAU               SYSCFG_CM55CR_LOCKSAU_Msk               /*!< Prevent changes to secure SAU memory regions already programmed */
+#define SYSCFG_CM55CR_LOCKDCAIC_Pos         (21U)
+#define SYSCFG_CM55CR_LOCKDCAIC_Msk         (0x1UL << SYSCFG_CM55CR_LOCKDCAIC_Pos)  /*!< 0x00200000 */
+#define SYSCFG_CM55CR_LOCKDCAIC             SYSCFG_CM55CR_LOCKDCAIC_Msk
+
+/******************  Bit definition for SYSCFG_CM55TCMCR register  ***************/
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Pos      (0U)
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x0000000F */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ          SYSCFG_CM55TCMCR_CFGITCMSZ_Msk               /*!< Select ITCM memory size */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000001 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000002 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000004 */
+#define SYSCFG_CM55TCMCR_CFGITCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos)    /*!< 0x00000008 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos      (4U)
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk      (0xFUL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ          SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk               /*!< Select DTCM memory size */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_0        (0x1UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000010 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_1        (0x2UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000020 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_2        (0x4UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000040 */
+#define SYSCFG_CM55TCMCR_CFGDTCMSZ_3        (0x8UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos)    /*!< 0x00000080 */
+#define SYSCFG_CM55TCMCR_LOCKTCM_Pos        (16U)
+#define SYSCFG_CM55TCMCR_LOCKTCM_Msk        (0x1UL << SYSCFG_CM55TCMCR_LOCKTCM_Pos)      /*!< 0x00010000 */
+#define SYSCFG_CM55TCMCR_LOCKTCM            SYSCFG_CM55TCMCR_LOCKTCM_Msk                 /*!< Disable writes to registers associated with the TCM region */
+#define SYSCFG_CM55TCMCR_LOCKITGU_Pos       (17U)
+#define SYSCFG_CM55TCMCR_LOCKITGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKITGU_Pos)     /*!< 0x00020000 */
+#define SYSCFG_CM55TCMCR_LOCKITGU           SYSCFG_CM55TCMCR_LOCKITGU_Msk                /*!< Disable writes to registers associated with the ITCM interface security/gating */
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Pos       (18U)
+#define SYSCFG_CM55TCMCR_LOCKDTGU_Msk       (0x1UL << SYSCFG_CM55TCMCR_LOCKDTGU_Pos)     /*!< 0x00040000 */
+#define SYSCFG_CM55TCMCR_LOCKDTGU           SYSCFG_CM55TCMCR_LOCKDTGU_Msk                /*!< Disable writes to registers associated with the DTCM interface security/gating. */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos  (23U)
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos) /*!< 0x00800000 */
+#define SYSCFG_CM55TCMCR_ITCMWSDISABLE      SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended ITCM memory */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos  (24U)
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk  (0x1UL << SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos) /*!< 0x01000000 */
+#define SYSCFG_CM55TCMCR_DTCMWSDISABLE      SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk            /*!< Disable wait-state applied by default on extended DTCM memory */
+
+
+/******************  Bit definition for SYSCFG_CM55RWMCR register  **************/
+#define SYSCFG_CM55RWMCR_RME_TCM_Pos        (0U)
+#define SYSCFG_CM55RWMCR_RME_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_RME_TCM_Pos)   /*!< 0x00000001 */
+#define SYSCFG_CM55RWMCR_RME_TCM            SYSCFG_CM55RWMCR_RME_TCM_Msk              /*!< RW margin enable input for TCM memories */
+#define SYSCFG_CM55RWMCR_RM_TCM_Pos         (1U)
+#define SYSCFG_CM55RWMCR_RM_TCM_Msk         (0xFUL << SYSCFG_CM55RWMCR_RM_TCM_Pos)    /*!< 0x0000001E */
+#define SYSCFG_CM55RWMCR_RM_TCM             SYSCFG_CM55RWMCR_RM_TCM_Msk               /*!< External RW margin inputs for TCM memories */
+#define SYSCFG_CM55RWMCR_BC1_TCM_Pos        (5U)
+#define SYSCFG_CM55RWMCR_BC1_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC1_TCM_Pos)   /*!< 0x00000020 */
+#define SYSCFG_CM55RWMCR_BC1_TCM            SYSCFG_CM55RWMCR_BC1_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_TCM_Pos        (6U)
+#define SYSCFG_CM55RWMCR_BC2_TCM_Msk        (0x1UL << SYSCFG_CM55RWMCR_BC2_TCM_Pos)   /*!< 0x00000040 */
+#define SYSCFG_CM55RWMCR_BC2_TCM            SYSCFG_CM55RWMCR_BC2_TCM_Msk              /*!< Biasing level adjust input recommended for Vnom + 10% */
+#define SYSCFG_CM55RWMCR_RME_CACHE_Pos      (7U)
+#define SYSCFG_CM55RWMCR_RME_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_RME_CACHE_Pos) /*!< 0x00000080 */
+#define SYSCFG_CM55RWMCR_RME_CACHE          SYSCFG_CM55RWMCR_RME_CACHE_Msk            /*!< RW margin enable input for caches memories */
+#define SYSCFG_CM55RWMCR_RM_CACHE_Pos       (8U)
+#define SYSCFG_CM55RWMCR_RM_CACHE_Msk       (0xFUL << SYSCFG_CM55RWMCR_RM_CACHE_Pos)  /*!< 0x00000F00 */
+#define SYSCFG_CM55RWMCR_RM_CACHE           SYSCFG_CM55RWMCR_RM_CACHE_Msk             /*!< External read/write (RW) margin inputs for caches memories */
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Pos      (12U)
+#define SYSCFG_CM55RWMCR_BC1_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC1_CACHE_Pos) /*!< 0x0001000 */
+#define SYSCFG_CM55RWMCR_BC1_CACHE          SYSCFG_CM55RWMCR_BC1_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom */
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Pos      (13U)
+#define SYSCFG_CM55RWMCR_BC2_CACHE_Msk      (0x1UL << SYSCFG_CM55RWMCR_BC2_CACHE_Pos) /*!< 0x00002000 */
+#define SYSCFG_CM55RWMCR_BC2_CACHE          SYSCFG_CM55RWMCR_BC2_CACHE_Msk            /*!< Biasing level adjust input recommended for Vnom + 10% */
+
+/******************  Bit definition for SYSCFG_INITSVTORCR register  **************/
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos   (7U)
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk   (0x1FFFFFFUL << SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos)   /*!< 0xFFFFFF80 */
+#define SYSCFG_INITSVTORCR_SVTOR_ADDR       SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk                    /*!< Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_INITNSVTORCR register  **************/
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos  (7U)
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk  (0x1FFFFFFUL << SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos)  /*!< 0xFFFFFF80 */
+#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR      SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk                   /*!< Non-Secure vector table base address */
+
+/******************  Bit definition for SYSCFG_CM55RSTCR register  **************/
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos     (0U)
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk     (0x1UL << SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE         SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk            /*!< Select reset to apply on core upon SYSRESETREQ */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos       (1U)
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos)   /*!< 0x00000002 */
+#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN           SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos       (2U)
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk       (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos)   /*!< 0x00000004 */
+#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN           SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk              /*!< Select action to perform on a lockup state on the core */
+
+/******************  Bit definition for SYSCFG_CM55PAHBWPR register  **************/
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos       (0U)
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk       (0x1UL << SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos) /*!< 0x00000001 */
+#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK           SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk            /*!< Error capture in write posting buffer */
+
+/******************  Bit definition for SYSCFG_VENCRAMCR register  **************/
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Pos     (0U)
+#define SYSCFG_VENCRAMCR_VENCRAM_EN_Msk     (0x1UL << SYSCFG_VENCRAMCR_VENCRAM_EN_Pos)               /*!< 0x00000001 */
+#define SYSCFG_VENCRAMCR_VENCRAM_EN         SYSCFG_VENCRAMCR_VENCRAM_EN_Msk                          /*!< VENCRAM allocation VENC if active, or to system (if VENC inactive) */
+
+/******************  Bit definition for SYSCFG_POTTAMPRSTCR register  **************/
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos       (0U)
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk       (0x1UL << SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos) /*!< 0x00000001 */
+#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK           SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk            /*!< mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper */
+
+/******************  Bit definition for SYSCFG_NPUNICQOSCR register  **************/
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos    (0U)
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR         SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk           /*!< NPUNIC read QoS information for NPU1 master port */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos    (4U)
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW         SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk           /*!< NPUNIC write QoS information for NPU1 master port */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos    (8U)
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR         SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk           /*!< NPUNIC read QoS information for NPU2 master port */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos    (12U)
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk    (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW         SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk           /*!< NPUNIC write QoS information for NPU2 master port */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_0      (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_1      (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_2      (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_3      (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos   (16U)
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk   (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR        SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk           /*!< NPUNIC read QoS information for master port from CPUSS */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_0     (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_1     (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_2     (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_3     (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000008 */
+
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos   (20U)
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk   (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x0000000F */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW        SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk           /*!< NPUNIC write QoS information for master port from CPUSS */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_0     (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_1     (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000002 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_2     (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000004 */
+#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_3     (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000008 */
+
+/******************  Bit definition for SYSCFG_ICNEWRCR register  **************/
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos     (0U)
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000001 */
+#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC1 early-write response */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos     (1U)
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk     (0x1UL << SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE         SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk            /*!< SDMMC2 early-write response */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos       (2U)
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000004 */
+#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk              /*!< USB1 early-write response */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos       (3U)
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk       (0x1UL << SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos)   /*!< 0x00000008 */
+#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE           SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk              /*!< USB2 early-write response */
+
+/******************  Bit definition for SYSCFG_ICNCGCR register  **************/
+#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos              (0U)
+#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos) /*!< 0x00000001 */
+#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk            /*!< NPU_NIC clock gating disable */
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos              (1U)
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk            /*!< CPU_NIC clock gating disable */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos              (2U)
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk              (0x1UL << SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos) /*!< 0x00000004 */
+#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE                  SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk            /*!< CPU_NOC clock gating disable */
+
+/******************  Bit definition for SYSCFG_IOCR register  **************/
+#define SYSCFG_IOCR_IOCR_Pos                (0U)
+#define SYSCFG_IOCR_IOCR_Msk                (0xFFFFFFFFUL << SYSCFG_IOCR_IOCR_Pos)         /*!< 0xFFFFFFFF */
+#define SYSCFG_IOCR_IOCR                    SYSCFG_IOCR_IOCR_Msk                           /*!< Digital or analog pins */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCCR register  **************/
+#define SYSCFG_VDDIO2CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO2CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCCR_RANSRC            SYSCFG_VDDIO2CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO2CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC            SYSCFG_VDDIO2CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO2CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCCR_EN                SYSCFG_VDDIO2CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO2 */
+#define SYSCFG_VDDIO2CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO2CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO2CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO2CCCR_CS                SYSCFG_VDDIO2CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO2CCSR register  **************/
+#define SYSCFG_VDDIO2CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO2CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO2CCSR_ANSRC             SYSCFG_VDDIO2CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO2CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO2CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO2CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO2CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO2CCSR_APSRC             SYSCFG_VDDIO2CCSR_APSRC_Msk
+#define SYSCFG_VDDIO2CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO2CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO2CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO2CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO2CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO2CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO2CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO2CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO2CCSR_READY             SYSCFG_VDDIO2CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO2 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCCR register  **************/
+#define SYSCFG_VDDIO3CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO3CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCCR_RANSRC            SYSCFG_VDDIO3CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO3CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC            SYSCFG_VDDIO3CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO3CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCCR_EN                SYSCFG_VDDIO3CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO3 */
+#define SYSCFG_VDDIO3CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO3CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO3CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO3CCCR_CS                SYSCFG_VDDIO3CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO3CCSR register  **************/
+#define SYSCFG_VDDIO3CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO3CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO3CCSR_ANSRC             SYSCFG_VDDIO3CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO3CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO3CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO3CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO3CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO3CCSR_APSRC             SYSCFG_VDDIO3CCSR_APSRC_Msk
+#define SYSCFG_VDDIO3CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO3CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO3CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO3CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO3CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO3CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO3CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO3CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO3CCSR_READY             SYSCFG_VDDIO3CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO3 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCCR register  **************/
+#define SYSCFG_VDDIO4CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO4CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCCR_RANSRC            SYSCFG_VDDIO4CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO4CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC            SYSCFG_VDDIO4CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO4CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCCR_EN                SYSCFG_VDDIO4CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO4 */
+#define SYSCFG_VDDIO4CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO4CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO4CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO4CCCR_CS                SYSCFG_VDDIO4CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO4CCSR register  **************/
+#define SYSCFG_VDDIO4CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO4CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO4CCSR_ANSRC             SYSCFG_VDDIO4CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO4CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO4CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO4CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO4CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO4CCSR_APSRC             SYSCFG_VDDIO4CCSR_APSRC_Msk
+#define SYSCFG_VDDIO4CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO4CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO4CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO4CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO4CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO4CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO4CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO4CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO4CCSR_READY             SYSCFG_VDDIO4CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO4 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCCR register  **************/
+#define SYSCFG_VDDIO5CCCR_RANSRC_Pos        (0U)
+#define SYSCFG_VDDIO5CCCR_RANSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCCR_RANSRC            SYSCFG_VDDIO5CCCR_RANSRC_Msk                   /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RANSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCCR_RANSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos)        /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Pos        (4U)
+#define SYSCFG_VDDIO5CCCR_RAPSRC_Msk        (0xFUL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC            SYSCFG_VDDIO5CCCR_RAPSRC_Msk                   /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_0          (0x1UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_1          (0x2UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_2          (0x4UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCCR_RAPSRC_3          (0x8UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos)        /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCCR_EN_Pos            (8U)
+#define SYSCFG_VDDIO5CCCR_EN_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_EN_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCCR_EN                SYSCFG_VDDIO5CCCR_EN_Msk                       /*!< Enables the compensation cell of I/Os supplied by VDDIO5 */
+#define SYSCFG_VDDIO5CCCR_CS_Pos            (9U)
+#define SYSCFG_VDDIO5CCCR_CS_Msk            (0x1UL << SYSCFG_VDDIO5CCCR_CS_Pos)            /*!< 0x00000200 */
+#define SYSCFG_VDDIO5CCCR_CS                SYSCFG_VDDIO5CCCR_CS_Msk                       /*!< Code selection for the compensation cell of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDIO5CCSR register  **************/
+#define SYSCFG_VDDIO5CCSR_ANSRC_Pos         (0U)
+#define SYSCFG_VDDIO5CCSR_ANSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_VDDIO5CCSR_ANSRC             SYSCFG_VDDIO5CCSR_ANSRC_Msk
+#define SYSCFG_VDDIO5CCSR_ANSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000001 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000002 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000004 */
+#define SYSCFG_VDDIO5CCSR_ANSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos)         /*!< 0x00000008 */
+#define SYSCFG_VDDIO5CCSR_APSRC_Pos         (4U)
+#define SYSCFG_VDDIO5CCSR_APSRC_Msk         (0xFUL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_VDDIO5CCSR_APSRC             SYSCFG_VDDIO5CCSR_APSRC_Msk
+#define SYSCFG_VDDIO5CCSR_APSRC_0           (0x1UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000010 */
+#define SYSCFG_VDDIO5CCSR_APSRC_1           (0x2UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000020 */
+#define SYSCFG_VDDIO5CCSR_APSRC_2           (0x4UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000040 */
+#define SYSCFG_VDDIO5CCSR_APSRC_3           (0x8UL << SYSCFG_VDDIO5CCSR_APSRC_Pos)         /*!< 0x00000080 */
+#define SYSCFG_VDDIO5CCSR_READY_Pos         (8U)
+#define SYSCFG_VDDIO5CCSR_READY_Msk         (0x1UL << SYSCFG_VDDIO5CCSR_READY_Pos)         /*!< 0x00000100 */
+#define SYSCFG_VDDIO5CCSR_READY             SYSCFG_VDDIO5CCSR_READY_Msk                    /*!< Provides the compensation cell status of I/Os supplied by VDDIO5 */
+
+/******************  Bit definition for SYSCFG_VDDCCCR register  **************/
+#define SYSCFG_VDDCCCR_RANSRC_Pos           (0U)
+#define SYSCFG_VDDCCCR_RANSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x0000000F */
+#define SYSCFG_VDDCCCR_RANSRC               SYSCFG_VDDCCCR_RANSRC_Msk                      /*!< I/O compensation code for NMOS transistors */
+#define SYSCFG_VDDCCCR_RANSRC_0             (0x1UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000001 */
+#define SYSCFG_VDDCCCR_RANSRC_1             (0x2UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000002 */
+#define SYSCFG_VDDCCCR_RANSRC_2             (0x4UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000004 */
+#define SYSCFG_VDDCCCR_RANSRC_3             (0x8UL << SYSCFG_VDDCCCR_RANSRC_Pos)           /*!< 0x00000008 */
+#define SYSCFG_VDDCCCR_RAPSRC_Pos           (4U)
+#define SYSCFG_VDDCCCR_RAPSRC_Msk           (0xFUL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x000000F0 */
+#define SYSCFG_VDDCCCR_RAPSRC               SYSCFG_VDDCCCR_RAPSRC_Msk                      /*!< I/O compensation code for PMOS transistors */
+#define SYSCFG_VDDCCCR_RAPSRC_0             (0x1UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000010 */
+#define SYSCFG_VDDCCCR_RAPSRC_1             (0x2UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000020 */
+#define SYSCFG_VDDCCCR_RAPSRC_2             (0x4UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000040 */
+#define SYSCFG_VDDCCCR_RAPSRC_3             (0x8UL << SYSCFG_VDDCCCR_RAPSRC_Pos)           /*!< 0x00000080 */
+#define SYSCFG_VDDCCCR_EN_Pos               (8U)
+#define SYSCFG_VDDCCCR_EN_Msk               (0x1UL << SYSCFG_VDDCCCR_EN_Pos)               /*!< 0x00000100 */
+#define SYSCFG_VDDCCCR_EN                   SYSCFG_VDDCCCR_EN_Msk                          /*!< Enables the compensation cell of I/Os supplied by VDD */
+#define SYSCFG_VDDCCCR_CS_Pos               (9U)
+#define SYSCFG_VDDCCCR_CS_Msk               (0x1UL << SYSCFG_VDDCCCR_CS_Pos)               /*!< 0x00000200 */
+#define SYSCFG_VDDCCCR_CS                   SYSCFG_VDDCCCR_CS_Msk                          /*!< Code selection for the compensation cell of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_VDDCCSR register  **************/
+#define SYSCFG_VDDCCSR_ANSRC_Pos            (0U)
+#define SYSCFG_VDDCCSR_ANSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x0000000F */
+#define SYSCFG_VDDCCSR_ANSRC                SYSCFG_VDDCCSR_ANSRC_Msk
+#define SYSCFG_VDDCCSR_ANSRC_0              (0x1UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000001 */
+#define SYSCFG_VDDCCSR_ANSRC_1              (0x2UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000002 */
+#define SYSCFG_VDDCCSR_ANSRC_2              (0x4UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000004 */
+#define SYSCFG_VDDCCSR_ANSRC_3              (0x8UL << SYSCFG_VDDCCSR_ANSRC_Pos)            /*!< 0x00000008 */
+#define SYSCFG_VDDCCSR_APSRC_Pos            (4U)
+#define SYSCFG_VDDCCSR_APSRC_Msk            (0xFUL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x000000F0 */
+#define SYSCFG_VDDCCSR_APSRC                SYSCFG_VDDCCSR_APSRC_Msk
+#define SYSCFG_VDDCCSR_APSRC_0              (0x1UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000010 */
+#define SYSCFG_VDDCCSR_APSRC_1              (0x2UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000020 */
+#define SYSCFG_VDDCCSR_APSRC_2              (0x4UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000040 */
+#define SYSCFG_VDDCCSR_APSRC_3              (0x8UL << SYSCFG_VDDCCSR_APSRC_Pos)            /*!< 0x00000080 */
+#define SYSCFG_VDDCCSR_READY_Pos            (8U)
+#define SYSCFG_VDDCCSR_READY_Msk            (0x1UL << SYSCFG_VDDCCSR_READY_Pos)            /*!< 0x00000100 */
+#define SYSCFG_VDDCCSR_READY                SYSCFG_VDDCCSR_READY_Msk                       /*!< Provides the compensation cell status of I/Os supplied by VDD */
+
+/******************  Bit definition for SYSCFG_CBR register  **************/
+#define SYSCFG_CBR_CM55L_Pos                (0U)
+#define SYSCFG_CBR_CM55L_Msk                (0x1UL << SYSCFG_CBR_CM55L_Pos)                /*!< 0x00000001 */
+#define SYSCFG_CBR_CM55L                    SYSCFG_CBR_CM55L_Msk                           /*!< CM55 lockup lock enable */
+#define SYSCFG_CBR_PVDL_LOCK_Pos            (2U)
+#define SYSCFG_CBR_PVDL_LOCK_Msk            (0x1UL << SYSCFG_CBR_PVDL_LOCK_Pos)            /*!< 0x00000004 */
+#define SYSCFG_CBR_PVDL_LOCK                SYSCFG_CBR_PVDL_LOCK_Msk                       /*!< PVD lock enable */
+#define SYSCFG_CBR_BKPRAML_Pos              (8U)
+#define SYSCFG_CBR_BKPRAML_Msk              (0x1UL << SYSCFG_CBR_BKPRAML_Pos)              /*!< 0x00000100 */
+#define SYSCFG_CBR_BKPRAML                  SYSCFG_CBR_BKPRAML_Msk                         /*!< Backup SRAM double ECC error lock */
+#define SYSCFG_CBR_CM55CACHEL_Pos           (9U)
+#define SYSCFG_CBR_CM55CACHEL_Msk           (0x1UL << SYSCFG_CBR_CM55CACHEL_Pos)           /*!< 0x00000200 */
+#define SYSCFG_CBR_CM55CACHEL               SYSCFG_CBR_CM55CACHEL_Msk                      /*!< CM55 cache double ECC error lock */
+#define SYSCFG_CBR_CM55TCML_Pos             (10U)
+#define SYSCFG_CBR_CM55TCML_Msk             (0x1UL << SYSCFG_CBR_CM55TCML_Pos)             /*!< 0x00000400 */
+#define SYSCFG_CBR_CM55TCML                 SYSCFG_CBR_CM55TCML_Msk                        /*!< CM55 TCM double ECC error lock */
+
+/******************  Bit definition for SYSCFG_SEC_AIDCR register  **************/
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Pos     (0U)
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_Msk     (0x7UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x0000000F */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC         SYSCFG_SEC_AIDCR_DMACID_SEC_Msk                /* Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_0       (0x1UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000001 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_1       (0x2UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SEC_AIDCR_DMACID_SEC_2       (0x4UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos)     /*!< 0x00000004 */
+
+/******************  Bit definition for SYSCFG_FMC_RETIMECR register  **************/
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos       (0U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos) /*!< 0x00000001 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX           SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk            /*!< Retiming on Rx path */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos       (1U)
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk       (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos) /*!< 0x00000002 */
+#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX           SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk            /*!< Retiming on Tx path */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos         (2U)
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk         (0x1UL << SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos)   /*!< 0x00000004 */
+#define SYSCFG_FMC_RETIMECR_SDFBCLK_180             SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk              /*!< Delay on feedback clock */
+
+/******************  Bit definition for SYSCFG_NPU_ICNCR register  **************/
+#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos    (0U)
+#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk    (0x1UL << SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos) /*!< 0x00000001 */
+#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE        SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk            /*!< Control interleaving on NPU RAMs */
+
+/******************  Bit definition for SYSCFG_BOOTSR register  **************/
+#define SYSCFG_BOOTSR_BOOT0_Pos             (0U)
+#define SYSCFG_BOOTSR_BOOT0_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT0_Pos)             /*!< 0x00000001 */
+#define SYSCFG_BOOTSR_BOOT0                 SYSCFG_BOOTSR_BOOT0_Msk                        /*!< BOOT0 pin value */
+#define SYSCFG_BOOTSR_BOOT1_Pos             (1U)
+#define SYSCFG_BOOTSR_BOOT1_Msk             (0x1UL << SYSCFG_BOOTSR_BOOT1_Pos)             /*!< 0x00000002 */
+#define SYSCFG_BOOTSR_BOOT1                 SYSCFG_BOOTSR_BOOT1_Msk                        /*!< BOOT1 pin value */
+
+/******************  Bit definition for SYSCFG_AHBWP_ERROR_SR register  **************/
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos  (0U)
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk  (0xFFFFFFFFUL << SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR      SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk                   /*!< Reports address of the first error in P-AHB write-posting buffer */
+
+/******************  Bit definition for SYSCFG_SECPRIV_AIDCR register  **************/
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos  (0U)
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk  (0x7UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x0000000F */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC      SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk             /* Non-Secure OS allocates specific CID to DMA channel through these bits */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_0    (0x1UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000001 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_1    (0x2UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000002 */
+#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_2    (0x4UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos)  /*!< 0x00000004 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Tamper and backup register (TAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for TAMP_CR1 register  *****************/
+#define TAMP_CR1_TAMP1E_Pos                 (0U)
+#define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
+#define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
+#define TAMP_CR1_TAMP2E_Pos                 (1U)
+#define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
+#define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
+#define TAMP_CR1_TAMP3E_Pos                 (2U)
+#define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
+#define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
+#define TAMP_CR1_TAMP4E_Pos                 (3U)
+#define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
+#define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
+#define TAMP_CR1_TAMP5E_Pos                 (4U)
+#define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
+#define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
+#define TAMP_CR1_TAMP6E_Pos                 (5U)
+#define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
+#define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
+#define TAMP_CR1_TAMP7E_Pos                 (6U)
+#define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
+#define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
+#define TAMP_CR1_ITAMP1E_Pos                (16U)
+#define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
+#define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
+#define TAMP_CR1_ITAMP2E_Pos                (17U)
+#define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
+#define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
+#define TAMP_CR1_ITAMP3E_Pos                (18U)
+#define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
+#define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
+#define TAMP_CR1_ITAMP4E_Pos                (19U)
+#define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
+#define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
+#define TAMP_CR1_ITAMP5E_Pos                (20U)
+#define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
+#define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
+#define TAMP_CR1_ITAMP6E_Pos                (21U)
+#define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
+#define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
+#define TAMP_CR1_ITAMP7E_Pos                (22U)
+#define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
+#define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
+#define TAMP_CR1_ITAMP8E_Pos                (23U)
+#define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
+#define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
+#define TAMP_CR1_ITAMP9E_Pos                (24U)
+#define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
+#define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
+#define TAMP_CR1_ITAMP11E_Pos               (26U)
+#define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
+#define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
+
+/********************  Bits definition for TAMP_CR2 register  *****************/
+#define TAMP_CR2_TAMP1POM_Pos               (0U)
+#define TAMP_CR2_TAMP1POM_Msk               (0x1UL << TAMP_CR2_TAMP1POM_Pos)        /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1POM                   TAMP_CR2_TAMP1POM_Msk
+#define TAMP_CR2_TAMP2POM_Pos               (1U)
+#define TAMP_CR2_TAMP2POM_Msk               (0x1UL << TAMP_CR2_TAMP2POM_Pos)        /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2POM                   TAMP_CR2_TAMP2POM_Msk
+#define TAMP_CR2_TAMP3POM_Pos               (2U)
+#define TAMP_CR2_TAMP3POM_Msk               (0x1UL << TAMP_CR2_TAMP3POM_Pos)        /*!< 0x00000004 */
+#define TAMP_CR2_TAMP3POM                   TAMP_CR2_TAMP3POM_Msk
+#define TAMP_CR2_TAMP4POM_Pos               (3U)
+#define TAMP_CR2_TAMP4POM_Msk               (0x1UL << TAMP_CR2_TAMP4POM_Pos)        /*!< 0x00000008 */
+#define TAMP_CR2_TAMP4POM                   TAMP_CR2_TAMP4POM_Msk
+#define TAMP_CR2_TAMP5POM_Pos               (4U)
+#define TAMP_CR2_TAMP5POM_Msk               (0x1UL << TAMP_CR2_TAMP5POM_Pos)        /*!< 0x00000010 */
+#define TAMP_CR2_TAMP5POM                   TAMP_CR2_TAMP5POM_Msk
+#define TAMP_CR2_TAMP6POM_Pos               (5U)
+#define TAMP_CR2_TAMP6POM_Msk               (0x1UL << TAMP_CR2_TAMP6POM_Pos)        /*!< 0x00000020 */
+#define TAMP_CR2_TAMP6POM                   TAMP_CR2_TAMP6POM_Msk
+#define TAMP_CR2_TAMP7POM_Pos               (6U)
+#define TAMP_CR2_TAMP7POM_Msk               (0x1UL << TAMP_CR2_TAMP7POM_Pos)        /*!< 0x00000040 */
+#define TAMP_CR2_TAMP7POM                   TAMP_CR2_TAMP7POM_Msk
+#define TAMP_CR2_TAMP1MSK_Pos               (16U)
+#define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos               (17U)
+#define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP3MSK_Pos               (18U)
+#define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
+#define TAMP_CR2_BKBLOCK_Pos                (22U)
+#define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
+#define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
+#define TAMP_CR2_BKERASE_Pos                (23U)
+#define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
+#define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
+#define TAMP_CR2_TAMP1TRG_Pos               (24U)
+#define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos               (25U)
+#define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
+#define TAMP_CR2_TAMP3TRG_Pos               (26U)
+#define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
+#define TAMP_CR2_TAMP4TRG_Pos               (27U)
+#define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
+#define TAMP_CR2_TAMP5TRG_Pos               (28U)
+#define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
+#define TAMP_CR2_TAMP6TRG_Pos               (29U)
+#define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
+#define TAMP_CR2_TAMP7TRG_Pos               (30U)
+#define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
+#define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
+
+/********************  Bits definition for TAMP_CR3 register  *****************/
+#define TAMP_CR3_ITAMP1POM_Pos              (0U)
+#define TAMP_CR3_ITAMP1POM_Msk              (0x1UL << TAMP_CR3_ITAMP1POM_Pos)       /*!< 0x00000001 */
+#define TAMP_CR3_ITAMP1POM                  TAMP_CR3_ITAMP1POM_Msk
+#define TAMP_CR3_ITAMP2POM_Pos              (1U)
+#define TAMP_CR3_ITAMP2POM_Msk              (0x1UL << TAMP_CR3_ITAMP2POM_Pos)       /*!< 0x00000002 */
+#define TAMP_CR3_ITAMP2POM                  TAMP_CR3_ITAMP2POM_Msk
+#define TAMP_CR3_ITAMP3POM_Pos              (2U)
+#define TAMP_CR3_ITAMP3POM_Msk              (0x1UL << TAMP_CR3_ITAMP3POM_Pos)       /*!< 0x00000004 */
+#define TAMP_CR3_ITAMP3POM                  TAMP_CR3_ITAMP3POM_Msk
+#define TAMP_CR3_ITAMP4POM_Pos              (3U)
+#define TAMP_CR3_ITAMP4POM_Msk              (0x1UL << TAMP_CR3_ITAMP4POM_Pos)       /*!< 0x00000008 */
+#define TAMP_CR3_ITAMP4POM                  TAMP_CR3_ITAMP4POM_Msk
+#define TAMP_CR3_ITAMP5POM_Pos              (4U)
+#define TAMP_CR3_ITAMP5POM_Msk              (0x1UL << TAMP_CR3_ITAMP5POM_Pos)       /*!< 0x00000010 */
+#define TAMP_CR3_ITAMP5POM                  TAMP_CR3_ITAMP5POM_Msk
+#define TAMP_CR3_ITAMP6POM_Pos              (5U)
+#define TAMP_CR3_ITAMP6POM_Msk              (0x1UL << TAMP_CR3_ITAMP6POM_Pos)       /*!< 0x00000020 */
+#define TAMP_CR3_ITAMP6POM                  TAMP_CR3_ITAMP6POM_Msk
+#define TAMP_CR3_ITAMP7POM_Pos              (6U)
+#define TAMP_CR3_ITAMP7POM_Msk              (0x1UL << TAMP_CR3_ITAMP7POM_Pos)       /*!< 0x00000040 */
+#define TAMP_CR3_ITAMP7POM                  TAMP_CR3_ITAMP7POM_Msk
+#define TAMP_CR3_ITAMP8POM_Pos              (7U)
+#define TAMP_CR3_ITAMP8POM_Msk              (0x1UL << TAMP_CR3_ITAMP8POM_Pos)       /*!< 0x00000080 */
+#define TAMP_CR3_ITAMP8POM                  TAMP_CR3_ITAMP8POM_Msk
+#define TAMP_CR3_ITAMP9POM_Pos              (8U)
+#define TAMP_CR3_ITAMP9POM_Msk              (0x1UL << TAMP_CR3_ITAMP9POM_Pos)       /*!< 0x00000100 */
+#define TAMP_CR3_ITAMP9POM                  TAMP_CR3_ITAMP9POM_Msk
+#define TAMP_CR3_ITAMP11POM_Pos             (10U)
+#define TAMP_CR3_ITAMP11POM_Msk             (0x1UL << TAMP_CR3_ITAMP11POM_Pos)      /*!< 0x00000400 */
+#define TAMP_CR3_ITAMP11POM                 TAMP_CR3_ITAMP11POM_Msk
+
+/********************  Bits definition for TAMP_FLTCR register  ***************/
+#define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
+#define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
+#define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
+#define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
+#define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
+#define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
+#define TAMP_FLTCR_TAMPFLT_Pos              (3U)
+#define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
+#define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
+#define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
+#define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
+#define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
+#define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
+#define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
+#define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
+#define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
+#define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
+#define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
+#define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
+
+/********************  Bits definition for TAMP_ATCR1 register  ***************/
+#define TAMP_ATCR1_TAMP1AM_Pos              (0U)
+#define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
+#define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
+#define TAMP_ATCR1_TAMP2AM_Pos              (1U)
+#define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
+#define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
+#define TAMP_ATCR1_TAMP3AM_Pos              (2U)
+#define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
+#define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
+#define TAMP_ATCR1_TAMP4AM_Pos              (3U)
+#define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
+#define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
+#define TAMP_ATCR1_TAMP5AM_Pos              (4U)
+#define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
+#define TAMP_ATCR1_TAMP6AM_Pos              (5U)
+#define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
+#define TAMP_ATCR1_TAMP7AM_Pos              (6U)
+#define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
+#define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
+#define TAMP_ATCR1_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
+#define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
+#define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR1_ATOSEL2_Pos              (10U)
+#define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
+#define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
+#define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR1_ATOSEL3_Pos              (12U)
+#define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
+#define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
+#define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR1_ATOSEL4_Pos              (14U)
+#define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
+#define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
+#define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR1_ATCKSEL_Pos              (16U)
+#define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
+#define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
+#define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR1_ATPER_Pos                (24U)
+#define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
+#define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
+#define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
+#define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
+#define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
+#define TAMP_ATCR1_ATOSHARE_Pos             (30U)
+#define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
+#define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
+#define TAMP_ATCR1_FLTEN_Pos                (31U)
+#define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
+#define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
+
+/********************  Bits definition for TAMP_ATSEEDR register  ******************/
+#define TAMP_ATSEEDR_SEED_Pos               (0U)
+#define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
+
+/********************  Bits definition for TAMP_ATOR register  ******************/
+#define TAMP_ATOR_PRNG_Pos                  (0U)
+#define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)          /*!< 0x000000FF */
+#define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
+#define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
+#define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
+#define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
+#define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
+#define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
+#define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
+#define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
+#define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
+#define TAMP_ATOR_SEEDF_Pos                 (14U)
+#define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
+#define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
+#define TAMP_ATOR_INITS_Pos                 (15U)
+#define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
+#define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
+
+/********************  Bits definition for TAMP_ATCR2 register  ***************/
+#define TAMP_ATCR2_ATOSEL1_Pos              (8U)
+#define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
+#define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
+#define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
+#define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
+#define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
+#define TAMP_ATCR2_ATOSEL2_Pos              (11U)
+#define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
+#define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
+#define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
+#define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
+#define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
+#define TAMP_ATCR2_ATOSEL3_Pos              (14U)
+#define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
+#define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
+#define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
+#define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
+#define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
+#define TAMP_ATCR2_ATOSEL4_Pos              (17U)
+#define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
+#define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
+#define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
+#define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
+#define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
+#define TAMP_ATCR2_ATOSEL5_Pos              (20U)
+#define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
+#define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
+#define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
+#define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
+#define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
+#define TAMP_ATCR2_ATOSEL6_Pos              (23U)
+#define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
+#define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
+#define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
+#define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
+#define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
+#define TAMP_ATCR2_ATOSEL7_Pos              (26U)
+#define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
+#define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
+#define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
+#define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
+#define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
+
+/********************  Bits definition for TAMP_SECCFGR register  *************/
+#define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
+#define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
+#define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
+#define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
+#define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
+#define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
+#define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
+#define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
+#define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
+#define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
+#define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
+#define TAMP_SECCFGR_CNT1SEC_Pos            (15U)
+#define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)     /*!< 0x00008000 */
+#define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
+#define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
+#define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
+#define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
+#define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
+#define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
+#define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
+#define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
+#define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
+#define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
+#define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
+#define TAMP_SECCFGR_BHKLOCK_Pos            (30U)
+#define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
+#define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
+#define TAMP_SECCFGR_TAMPSEC_Pos            (31U)
+#define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
+#define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk
+
+/********************  Bits definition for TAMP_PRIVCFGR register  ************/
+#define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
+#define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
+#define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
+#define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
+#define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
+#define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
+#define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
+#define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
+#define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
+#define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
+#define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
+
+/********************  Bits definition for TAMP_IER register  *****************/
+#define TAMP_IER_TAMP1IE_Pos                (0U)
+#define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
+#define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
+#define TAMP_IER_TAMP2IE_Pos                (1U)
+#define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
+#define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
+#define TAMP_IER_TAMP3IE_Pos                (2U)
+#define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
+#define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
+#define TAMP_IER_TAMP4IE_Pos                (3U)
+#define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
+#define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
+#define TAMP_IER_TAMP5IE_Pos                (4U)
+#define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
+#define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
+#define TAMP_IER_TAMP6IE_Pos                (5U)
+#define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
+#define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
+#define TAMP_IER_TAMP7IE_Pos                (6U)
+#define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
+#define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
+#define TAMP_IER_ITAMP1IE_Pos               (16U)
+#define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
+#define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
+#define TAMP_IER_ITAMP2IE_Pos               (17U)
+#define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
+#define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
+#define TAMP_IER_ITAMP3IE_Pos               (18U)
+#define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
+#define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
+#define TAMP_IER_ITAMP4IE_Pos               (19U)
+#define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
+#define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
+#define TAMP_IER_ITAMP5IE_Pos               (20U)
+#define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
+#define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
+#define TAMP_IER_ITAMP6IE_Pos               (21U)
+#define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
+#define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
+#define TAMP_IER_ITAMP7IE_Pos               (22U)
+#define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
+#define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
+#define TAMP_IER_ITAMP8IE_Pos               (23U)
+#define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
+#define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
+#define TAMP_IER_ITAMP9IE_Pos               (24U)
+#define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
+#define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
+#define TAMP_IER_ITAMP11IE_Pos              (26U)
+#define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
+#define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
+
+/********************  Bits definition for TAMP_SR register  *****************/
+#define TAMP_SR_TAMP1F_Pos                  (0U)
+#define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
+#define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
+#define TAMP_SR_TAMP2F_Pos                  (1U)
+#define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
+#define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
+#define TAMP_SR_TAMP3F_Pos                  (2U)
+#define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
+#define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
+#define TAMP_SR_TAMP4F_Pos                  (3U)
+#define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
+#define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
+#define TAMP_SR_TAMP5F_Pos                  (4U)
+#define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
+#define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
+#define TAMP_SR_TAMP6F_Pos                  (5U)
+#define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
+#define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
+#define TAMP_SR_TAMP7F_Pos                  (6U)
+#define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
+#define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
+#define TAMP_SR_ITAMP1F_Pos                 (16U)
+#define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
+#define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
+#define TAMP_SR_ITAMP2F_Pos                 (17U)
+#define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
+#define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
+#define TAMP_SR_ITAMP3F_Pos                 (18U)
+#define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
+#define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
+#define TAMP_SR_ITAMP4F_Pos                 (19U)
+#define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
+#define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
+#define TAMP_SR_ITAMP5F_Pos                 (20U)
+#define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
+#define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
+#define TAMP_SR_ITAMP6F_Pos                 (21U)
+#define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
+#define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
+#define TAMP_SR_ITAMP7F_Pos                 (22U)
+#define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
+#define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
+#define TAMP_SR_ITAMP8F_Pos                 (23U)
+#define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
+#define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
+#define TAMP_SR_ITAMP9F_Pos                 (24U)
+#define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
+#define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
+#define TAMP_SR_ITAMP11F_Pos                (26U)
+#define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
+#define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
+
+/********************  Bits definition for TAMP_MISR register  ****************/
+#define TAMP_MISR_TAMP1MF_Pos               (0U)
+#define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
+#define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
+#define TAMP_MISR_TAMP2MF_Pos               (1U)
+#define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
+#define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
+#define TAMP_MISR_TAMP3MF_Pos               (2U)
+#define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
+#define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
+#define TAMP_MISR_TAMP4MF_Pos               (3U)
+#define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
+#define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
+#define TAMP_MISR_TAMP5MF_Pos               (4U)
+#define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
+#define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
+#define TAMP_MISR_TAMP6MF_Pos               (5U)
+#define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
+#define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
+#define TAMP_MISR_TAMP7MF_Pos               (6U)
+#define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
+#define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
+#define TAMP_MISR_ITAMP1MF_Pos              (16U)
+#define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
+#define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
+#define TAMP_MISR_ITAMP2MF_Pos              (17U)
+#define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
+#define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
+#define TAMP_MISR_ITAMP3MF_Pos              (18U)
+#define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
+#define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
+#define TAMP_MISR_ITAMP4MF_Pos              (19U)
+#define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
+#define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
+#define TAMP_MISR_ITAMP5MF_Pos              (20U)
+#define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
+#define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
+#define TAMP_MISR_ITAMP6MF_Pos              (21U)
+#define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
+#define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
+#define TAMP_MISR_ITAMP7MF_Pos              (22U)
+#define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
+#define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
+#define TAMP_MISR_ITAMP8MF_Pos              (23U)
+#define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
+#define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
+#define TAMP_MISR_ITAMP9MF_Pos              (24U)
+#define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
+#define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
+#define TAMP_MISR_ITAMP11MF_Pos             (26U)
+#define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
+#define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SMISR register  ************ *****/
+#define TAMP_SMISR_TAMP1MF_Pos              (0U)
+#define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
+#define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
+#define TAMP_SMISR_TAMP2MF_Pos              (1U)
+#define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
+#define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
+#define TAMP_SMISR_TAMP3MF_Pos              (2U)
+#define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
+#define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
+#define TAMP_SMISR_TAMP4MF_Pos              (3U)
+#define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
+#define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
+#define TAMP_SMISR_TAMP5MF_Pos              (4U)
+#define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
+#define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
+#define TAMP_SMISR_TAMP6MF_Pos              (5U)
+#define TAMP_SMISR_TAMP6MF_Msk              (0x1UL << TAMP_SMISR_TAMP6MF_Pos)       /*!< 0x00000020 */
+#define TAMP_SMISR_TAMP6MF                  TAMP_SMISR_TAMP6MF_Msk
+#define TAMP_SMISR_TAMP7MF_Pos              (6U)
+#define TAMP_SMISR_TAMP7MF_Msk              (0x1UL << TAMP_SMISR_TAMP7MF_Pos)       /*!< 0x00000040 */
+#define TAMP_SMISR_TAMP7MF                  TAMP_SMISR_TAMP7MF_Msk
+#define TAMP_SMISR_ITAMP1MF_Pos             (16U)
+#define TAMP_SMISR_ITAMP1MF_Msk             (0x1UL << TAMP_SMISR_ITAMP1MF_Pos)      /*!< 0x00010000 */
+#define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
+#define TAMP_SMISR_ITAMP2MF_Pos             (17U)
+#define TAMP_SMISR_ITAMP2MF_Msk             (0x1UL << TAMP_SMISR_ITAMP2MF_Pos)      /*!< 0x00020000 */
+#define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
+#define TAMP_SMISR_ITAMP3MF_Pos             (18U)
+#define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
+#define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
+#define TAMP_SMISR_ITAMP4MF_Pos             (19U)
+#define TAMP_SMISR_ITAMP4MF_Msk             (0x1UL << TAMP_SMISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
+#define TAMP_SMISR_ITAMP4MF                 TAMP_SMISR_ITAMP4MF_Msk
+#define TAMP_SMISR_ITAMP5MF_Pos             (20U)
+#define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
+#define TAMP_SMISR_ITAMP6MF_Pos             (21U)
+#define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
+#define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
+#define TAMP_SMISR_ITAMP7MF_Pos             (22U)
+#define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
+#define TAMP_SMISR_ITAMP8MF_Pos             (23U)
+#define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
+#define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
+#define TAMP_SMISR_ITAMP9MF_Pos             (24U)
+#define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
+#define TAMP_SMISR_ITAMP11MF_Pos            (26U)
+#define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)      /*!< 0x00400000 */
+#define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
+
+/********************  Bits definition for TAMP_SCR register  *****************/
+#define TAMP_SCR_CTAMP1F_Pos                (0U)
+#define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
+#define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
+#define TAMP_SCR_CTAMP2F_Pos                (1U)
+#define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
+#define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
+#define TAMP_SCR_CTAMP3F_Pos                (2U)
+#define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
+#define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
+#define TAMP_SCR_CTAMP4F_Pos                (3U)
+#define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
+#define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
+#define TAMP_SCR_CTAMP5F_Pos                (4U)
+#define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
+#define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
+#define TAMP_SCR_CTAMP6F_Pos                (5U)
+#define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
+#define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
+#define TAMP_SCR_CTAMP7F_Pos                (6U)
+#define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
+#define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
+#define TAMP_SCR_CTAMP8F_Pos                (7U)
+#define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
+#define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
+#define TAMP_SCR_CITAMP1F_Pos               (16U)
+#define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
+#define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
+#define TAMP_SCR_CITAMP2F_Pos               (17U)
+#define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
+#define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
+#define TAMP_SCR_CITAMP3F_Pos               (18U)
+#define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
+#define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
+#define TAMP_SCR_CITAMP4F_Pos               (19U)
+#define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
+#define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
+#define TAMP_SCR_CITAMP5F_Pos               (20U)
+#define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
+#define TAMP_SCR_CITAMP6F_Pos               (21U)
+#define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
+#define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
+#define TAMP_SCR_CITAMP7F_Pos               (22U)
+#define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
+#define TAMP_SCR_CITAMP8F_Pos               (23U)
+#define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
+#define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
+#define TAMP_SCR_CITAMP9F_Pos               (24U)
+#define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
+#define TAMP_SCR_CITAMP11F_Pos              (26U)
+#define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
+#define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
+
+/********************  Bits definition for TAMP_COUNT1R register  ***************/
+#define TAMP_COUNT1R_COUNT_Pos              (0U)
+#define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
+#define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
+
+/********************  Bits definition for TAMP_OR register  ***************/
+#define TAMP_OR_VCOREMEN_Pos                (0U)
+#define TAMP_OR_VCOREMEN_Msk                (0x1UL << TAMP_OR_VCOREMEN_Pos)         /*!< 0x00000001 */
+#define TAMP_OR_VCOREMEN                    TAMP_OR_VCOREMEN_Msk
+
+/********************  Bits definition for TAMP_RPCFGR register  ***************/
+#define TAMP_RPCFGR_RPCFG0_Pos              (0U)
+#define TAMP_RPCFGR_RPCFG0_Msk              (0x1UL << TAMP_RPCFGR_RPCFG0_Pos)       /*!< 0x00000001 */
+#define TAMP_RPCFGR_RPCFG0                  TAMP_RPCFGR_RPCFG0_Msk
+
+/********************  Bits definition for TAMP_BKP0R register  ***************/
+#define TAMP_BKP0R_Pos                      (0U)
+#define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP0R                          TAMP_BKP0R_Msk
+
+/********************  Bits definition for TAMP_BKP1R register  ****************/
+#define TAMP_BKP1R_Pos                      (0U)
+#define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP1R                          TAMP_BKP1R_Msk
+
+/********************  Bits definition for TAMP_BKP2R register  ****************/
+#define TAMP_BKP2R_Pos                      (0U)
+#define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP2R                          TAMP_BKP2R_Msk
+
+/********************  Bits definition for TAMP_BKP3R register  ****************/
+#define TAMP_BKP3R_Pos                      (0U)
+#define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP3R                          TAMP_BKP3R_Msk
+
+/********************  Bits definition for TAMP_BKP4R register  ****************/
+#define TAMP_BKP4R_Pos                      (0U)
+#define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP4R                          TAMP_BKP4R_Msk
+
+/********************  Bits definition for TAMP_BKP5R register  ****************/
+#define TAMP_BKP5R_Pos                      (0U)
+#define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP5R                          TAMP_BKP5R_Msk
+
+/********************  Bits definition for TAMP_BKP6R register  ****************/
+#define TAMP_BKP6R_Pos                      (0U)
+#define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP6R                          TAMP_BKP6R_Msk
+
+/********************  Bits definition for TAMP_BKP7R register  ****************/
+#define TAMP_BKP7R_Pos                      (0U)
+#define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP7R                          TAMP_BKP7R_Msk
+
+/********************  Bits definition for TAMP_BKP8R register  ****************/
+#define TAMP_BKP8R_Pos                      (0U)
+#define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP8R                          TAMP_BKP8R_Msk
+
+/********************  Bits definition for TAMP_BKP9R register  ****************/
+#define TAMP_BKP9R_Pos                      (0U)
+#define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
+#define TAMP_BKP9R                          TAMP_BKP9R_Msk
+
+/********************  Bits definition for TAMP_BKP10R register  ***************/
+#define TAMP_BKP10R_Pos                     (0U)
+#define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP10R                         TAMP_BKP10R_Msk
+
+/********************  Bits definition for TAMP_BKP11R register  ***************/
+#define TAMP_BKP11R_Pos                     (0U)
+#define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP11R                         TAMP_BKP11R_Msk
+
+/********************  Bits definition for TAMP_BKP12R register  ***************/
+#define TAMP_BKP12R_Pos                     (0U)
+#define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP12R                         TAMP_BKP12R_Msk
+
+/********************  Bits definition for TAMP_BKP13R register  ***************/
+#define TAMP_BKP13R_Pos                     (0U)
+#define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP13R                         TAMP_BKP13R_Msk
+
+/********************  Bits definition for TAMP_BKP14R register  ***************/
+#define TAMP_BKP14R_Pos                     (0U)
+#define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP14R                         TAMP_BKP14R_Msk
+
+/********************  Bits definition for TAMP_BKP15R register  ***************/
+#define TAMP_BKP15R_Pos                     (0U)
+#define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP15R                         TAMP_BKP15R_Msk
+
+/********************  Bits definition for TAMP_BKP16R register  ***************/
+#define TAMP_BKP16R_Pos                     (0U)
+#define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP16R                         TAMP_BKP16R_Msk
+
+/********************  Bits definition for TAMP_BKP17R register  ***************/
+#define TAMP_BKP17R_Pos                     (0U)
+#define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP17R                         TAMP_BKP17R_Msk
+
+/********************  Bits definition for TAMP_BKP18R register  ***************/
+#define TAMP_BKP18R_Pos                     (0U)
+#define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP18R                         TAMP_BKP18R_Msk
+
+/********************  Bits definition for TAMP_BKP19R register  ***************/
+#define TAMP_BKP19R_Pos                     (0U)
+#define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP19R                         TAMP_BKP19R_Msk
+
+/********************  Bits definition for TAMP_BKP20R register  ***************/
+#define TAMP_BKP20R_Pos                     (0U)
+#define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP20R                         TAMP_BKP20R_Msk
+
+/********************  Bits definition for TAMP_BKP21R register  ***************/
+#define TAMP_BKP21R_Pos                     (0U)
+#define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP21R                         TAMP_BKP21R_Msk
+
+/********************  Bits definition for TAMP_BKP22R register  ***************/
+#define TAMP_BKP22R_Pos                     (0U)
+#define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP22R                         TAMP_BKP22R_Msk
+
+/********************  Bits definition for TAMP_BKP23R register  ***************/
+#define TAMP_BKP23R_Pos                     (0U)
+#define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP23R                         TAMP_BKP23R_Msk
+
+/********************  Bits definition for TAMP_BKP24R register  ***************/
+#define TAMP_BKP24R_Pos                     (0U)
+#define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP24R                         TAMP_BKP24R_Msk
+
+/********************  Bits definition for TAMP_BKP25R register  ***************/
+#define TAMP_BKP25R_Pos                     (0U)
+#define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP25R                         TAMP_BKP25R_Msk
+
+/********************  Bits definition for TAMP_BKP26R register  ***************/
+#define TAMP_BKP26R_Pos                     (0U)
+#define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP26R                         TAMP_BKP26R_Msk
+
+/********************  Bits definition for TAMP_BKP27R register  ***************/
+#define TAMP_BKP27R_Pos                     (0U)
+#define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP27R                         TAMP_BKP27R_Msk
+
+/********************  Bits definition for TAMP_BKP28R register  ***************/
+#define TAMP_BKP28R_Pos                     (0U)
+#define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP28R                         TAMP_BKP28R_Msk
+
+/********************  Bits definition for TAMP_BKP29R register  ***************/
+#define TAMP_BKP29R_Pos                     (0U)
+#define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP29R                         TAMP_BKP29R_Msk
+
+/********************  Bits definition for TAMP_BKP30R register  ***************/
+#define TAMP_BKP30R_Pos                     (0U)
+#define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP30R                         TAMP_BKP30R_Msk
+
+/********************  Bits definition for TAMP_BKP31R register  ***************/
+#define TAMP_BKP31R_Pos                     (0U)
+#define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
+#define TAMP_BKP31R                         TAMP_BKP31R_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+#define TIM_CR1_DITHEN_Pos        (12U)
+#define TIM_CR1_DITHEN_Msk        (0x1UL << TIM_CR1_DITHEN_Pos)                /*!< 0x00001000 */
+#define TIM_CR1_DITHEN            TIM_CR1_DITHEN_Msk                           /*!<Dithering enable */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (     0x1UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (     0x2UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (     0x4UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
+#define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS4N_Pos         (15U)
+#define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
+#define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
+#define TIM_CR2_ADSYNC_Pos        (28U)
+#define TIM_CR2_ADSYNC_Msk        (0x1UL << TIM_CR2_ADSYNC_Pos)                /*!< 0x10000000 */
+#define TIM_CR2_ADSYNC            TIM_CR2_ADSYNC_Msk                           /*!<ADC synchronization */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+#define TIM_SMCR_SMSPE_Pos        (24U)
+#define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
+#define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
+#define TIM_SMCR_SMSPS_Pos        (25U)
+#define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
+#define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+#define TIM_DIER_IDXIE_Pos        (20U)
+#define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
+#define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
+#define TIM_DIER_DIRIE_Pos        (21U)
+#define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
+#define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
+#define TIM_DIER_IERRIE_Pos       (22U)
+#define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
+#define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
+#define TIM_DIER_TERRIE_Pos       (23U)
+#define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
+#define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_IDXF_Pos           (20U)
+#define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
+#define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
+#define TIM_SR_DIRF_Pos           (21U)
+#define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
+#define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
+#define TIM_SR_IERRF_Pos          (22U)
+#define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
+#define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
+#define TIM_SR_TERRF_Pos          (23U)
+#define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
+#define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NE_Pos        (14U)
+#define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
+#define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFUL << TIM_CCR5_CCR5_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFFUL << TIM_CCR6_CCR6_Pos)             /*!< 0x000FFFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_DTR2 register  *********************/
+#define TIM_DTR2_DTGF_Pos         (0U)
+#define TIM_DTR2_DTGF_Msk         (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
+#define TIM_DTR2_DTGF             TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
+#define TIM_DTR2_DTGF_0           (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
+#define TIM_DTR2_DTGF_1           (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
+#define TIM_DTR2_DTGF_2           (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
+#define TIM_DTR2_DTGF_3           (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
+#define TIM_DTR2_DTGF_4           (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
+#define TIM_DTR2_DTGF_5           (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
+#define TIM_DTR2_DTGF_6           (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
+#define TIM_DTR2_DTGF_7           (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
+#define TIM_DTR2_DTAE_Pos         (16U)
+#define TIM_DTR2_DTAE_Msk         (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
+#define TIM_DTR2_DTAE             TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
+#define TIM_DTR2_DTPE_Pos         (17U)
+#define TIM_DTR2_DTPE_Msk         (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
+#define TIM_DTR2_DTPE             TIM_DTR2_DTPE_Msk                            /*!<Deadtime preload enable */
+
+/*******************  Bit definition for TIM_ECR register  *********************/
+#define TIM_ECR_IE_Pos            (0U)
+#define TIM_ECR_IE_Msk            (0x1UL << TIM_ECR_IE_Pos)                    /*!< 0x00000001 */
+#define TIM_ECR_IE                TIM_ECR_IE_Msk                               /*!<Index enable */
+#define TIM_ECR_IDIR_Pos          (1U)
+#define TIM_ECR_IDIR_Msk          (0x3UL << TIM_ECR_IDIR_Pos)                  /*!< 0x00000006 */
+#define TIM_ECR_IDIR              TIM_ECR_IDIR_Msk                             /*!<IDIR[1:0] bits (Index direction)*/
+#define TIM_ECR_IDIR_0            (0x01UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000001 */
+#define TIM_ECR_IDIR_1            (0x02UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000002 */
+#define TIM_ECR_IBLK_Pos          (3U)
+#define TIM_ECR_IBLK_Msk          (0x3UL << TIM_ECR_IBLK_Pos)                  /*!< 0x00000018 */
+#define TIM_ECR_IBLK              TIM_ECR_IBLK_Msk                             /*!<IBLK[1:0] bits (Index blanking)*/
+#define TIM_ECR_IBLK_0            (0x01UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000008 */
+#define TIM_ECR_IBLK_1            (0x02UL << TIM_ECR_IBLK_Pos)                 /*!< 0x00000010 */
+#define TIM_ECR_FIDX_Pos          (5U)
+#define TIM_ECR_FIDX_Msk          (0x1UL << TIM_ECR_FIDX_Pos)                  /*!< 0x00000020 */
+#define TIM_ECR_FIDX              TIM_ECR_FIDX_Msk                             /*!<First index enable */
+#define TIM_ECR_IPOS_Pos          (6U)
+#define TIM_ECR_IPOS_Msk          (0x3UL << TIM_ECR_IPOS_Pos)                  /*!< 0x000000C0 */
+#define TIM_ECR_IPOS              TIM_ECR_IPOS_Msk                             /*!<IPOS[1:0] bits (Index positioning)*/
+#define TIM_ECR_IPOS_0            (0x01UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000040 */
+#define TIM_ECR_IPOS_1            (0x02UL << TIM_ECR_IPOS_Pos)                 /*!< 0x00000080 */
+#define TIM_ECR_PW_Pos            (16U)
+#define TIM_ECR_PW_Msk            (0xFFUL << TIM_ECR_PW_Pos)                   /*!< 0x00FF0000 */
+#define TIM_ECR_PW                TIM_ECR_PW_Msk                               /*!<PW[7:0] bits (Pulse width)*/
+#define TIM_ECR_PW_0              (0x01UL << TIM_ECR_PW_Pos)                   /*!< 0x00010000 */
+#define TIM_ECR_PW_1              (0x02UL << TIM_ECR_PW_Pos)                   /*!< 0x00020000 */
+#define TIM_ECR_PW_2              (0x04UL << TIM_ECR_PW_Pos)                   /*!< 0x00040000 */
+#define TIM_ECR_PW_3              (0x08UL << TIM_ECR_PW_Pos)                   /*!< 0x00080000 */
+#define TIM_ECR_PW_4              (0x10UL << TIM_ECR_PW_Pos)                   /*!< 0x00100000 */
+#define TIM_ECR_PW_5              (0x20UL << TIM_ECR_PW_Pos)                   /*!< 0x00200000 */
+#define TIM_ECR_PW_6              (0x40UL << TIM_ECR_PW_Pos)                   /*!< 0x00400000 */
+#define TIM_ECR_PW_7              (0x80UL << TIM_ECR_PW_Pos)                   /*!< 0x00800000 */
+#define TIM_ECR_PWPRSC_Pos        (24U)
+#define TIM_ECR_PWPRSC_Msk        (0x7UL << TIM_ECR_PWPRSC_Pos)                /*!< 0x07000000 */
+#define TIM_ECR_PWPRSC            TIM_ECR_PWPRSC_Msk                           /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
+#define TIM_ECR_PWPRSC_0          (0x01UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x01000000 */
+#define TIM_ECR_PWPRSC_1          (0x02UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x02000000 */
+#define TIM_ECR_PWPRSC_2          (0x04UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x04000000 */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits */
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits */
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits */
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits */
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM_AF1 register  ********************/
+#define TIM_AF1_BKINE_Pos        (0U)
+#define TIM_AF1_BKINE_Msk        (0x1UL << TIM_AF1_BKINE_Pos)                  /*!< 0x00000001 */
+#define TIM_AF1_BKINE            TIM_AF1_BKINE_Msk                             /*!<BRK BKIN input enable */
+#define TIM_AF1_BKCMP1E_Pos      (1U)
+#define TIM_AF1_BKCMP1E_Msk      (0x1UL << TIM_AF1_BKCMP1E_Pos)                /*!< 0x00000002 */
+#define TIM_AF1_BKCMP1E          TIM_AF1_BKCMP1E_Msk                           /*!<BRK CMP1 enable */
+#define TIM_AF1_BKCMP2E_Pos      (2U)
+#define TIM_AF1_BKCMP2E_Msk      (0x1UL << TIM_AF1_BKCMP2E_Pos)                /*!< 0x00000004 */
+#define TIM_AF1_BKCMP2E          TIM_AF1_BKCMP2E_Msk                           /*!<BRK CMP2 enable */
+#define TIM_AF1_BKCMP3E_Pos      (3U)
+#define TIM_AF1_BKCMP3E_Msk      (0x1UL << TIM_AF1_BKCMP3E_Pos)                /*!< 0x00000008 */
+#define TIM_AF1_BKCMP3E          TIM_AF1_BKCMP3E_Msk                           /*!<BRK CMP3 enable */
+#define TIM_AF1_BKCMP4E_Pos      (4U)
+#define TIM_AF1_BKCMP4E_Msk      (0x1UL << TIM_AF1_BKCMP4E_Pos)                /*!< 0x00000010 */
+#define TIM_AF1_BKCMP4E          TIM_AF1_BKCMP4E_Msk                           /*!<BRK CMP4 enable */
+#define TIM_AF1_BKCMP5E_Pos      (5U)
+#define TIM_AF1_BKCMP5E_Msk      (0x1UL << TIM_AF1_BKCMP5E_Pos)                /*!< 0x00000020 */
+#define TIM_AF1_BKCMP5E          TIM_AF1_BKCMP5E_Msk                           /*!<BRK CMP5 enable */
+#define TIM_AF1_BKCMP6E_Pos      (6U)
+#define TIM_AF1_BKCMP6E_Msk      (0x1UL << TIM_AF1_BKCMP6E_Pos)                /*!< 0x00000040 */
+#define TIM_AF1_BKCMP6E          TIM_AF1_BKCMP6E_Msk                           /*!<BRK CMP6 enable */
+#define TIM_AF1_BKCMP7E_Pos      (7U)
+#define TIM_AF1_BKCMP7E_Msk      (0x1UL << TIM_AF1_BKCMP7E_Pos)                /*!< 0x00000080 */
+#define TIM_AF1_BKCMP7E          TIM_AF1_BKCMP7E_Msk                           /*!<BRK CMP7 enable */
+#define TIM_AF1_BKCMP8E_Pos      (8U)
+#define TIM_AF1_BKCMP8E_Msk      (0x1UL << TIM_AF1_BKCMP8E_Pos)                /*!< 0x00000100 */
+#define TIM_AF1_BKCMP8E          TIM_AF1_BKCMP8E_Msk                           /*!<BRK CMP8 enable */
+#define TIM_AF1_BKINP_Pos        (9U)
+#define TIM_AF1_BKINP_Msk        (0x1UL << TIM_AF1_BKINP_Pos)                  /*!< 0x00000200 */
+#define TIM_AF1_BKINP            TIM_AF1_BKINP_Msk                             /*!<BRK BKIN input polarity */
+#define TIM_AF1_BKCMP1P_Pos      (10U)
+#define TIM_AF1_BKCMP1P_Msk      (0x1UL << TIM_AF1_BKCMP1P_Pos)                /*!< 0x00000400 */
+#define TIM_AF1_BKCMP1P          TIM_AF1_BKCMP1P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP2P_Pos      (11U)
+#define TIM_AF1_BKCMP2P_Msk      (0x1UL << TIM_AF1_BKCMP2P_Pos)                /*!< 0x00000800 */
+#define TIM_AF1_BKCMP2P          TIM_AF1_BKCMP2P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP3P_Pos      (12U)
+#define TIM_AF1_BKCMP3P_Msk      (0x1UL << TIM_AF1_BKCMP3P_Pos)                /*!< 0x00001000 */
+#define TIM_AF1_BKCMP3P          TIM_AF1_BKCMP3P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_BKCMP4P_Pos      (13U)
+#define TIM_AF1_BKCMP4P_Msk      (0x1UL << TIM_AF1_BKCMP4P_Pos)                /*!< 0x00002000 */
+#define TIM_AF1_BKCMP4P          TIM_AF1_BKCMP4P_Msk                           /*!<BRK CMP1 input polarity */
+#define TIM_AF1_ETRSEL_Pos       (14U)
+#define TIM_AF1_ETRSEL_Msk       (0xFUL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x0003C000 */
+#define TIM_AF1_ETRSEL           TIM_AF1_ETRSEL_Msk                            /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
+#define TIM_AF1_ETRSEL_0         (0x1UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM_AF1_ETRSEL_1         (0x2UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM_AF1_ETRSEL_2         (0x4UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM_AF1_ETRSEL_3         (0x8UL << TIM_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM_AF2 register  ********************/
+#define TIM_AF2_BK2INE_Pos       (0U)
+#define TIM_AF2_BK2INE_Msk       (0x1UL << TIM_AF2_BK2INE_Pos)                 /*!< 0x00000001 */
+#define TIM_AF2_BK2INE           TIM_AF2_BK2INE_Msk                            /*!<BRK2 BKIN input enable */
+#define TIM_AF2_BK2CMP8E_Pos     (8U)
+#define TIM_AF2_BK2CMP8E_Msk     (0x1UL << TIM_AF2_BK2CMP8E_Pos)               /*!< 0x00000100 */
+#define TIM_AF2_BK2CMP8E         TIM_AF2_BK2CMP8E_Msk                          /*!<BRK2 CMP8 enable */
+#define TIM_AF2_BK2INP_Pos       (9U)
+#define TIM_AF2_BK2INP_Msk       (0x1UL << TIM_AF2_BK2INP_Pos)                 /*!< 0x00000200 */
+#define TIM_AF2_BK2INP           TIM_AF2_BK2INP_Msk                            /*!<BRK2 BKIN input polarity */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
+#define TIM_DCR_DBSS_Pos          (16U)
+#define TIM_DCR_DBSS_Msk          (0xFUL << TIM_DCR_DBSS_Pos)                  /*!< 0x000F0000 */
+#define TIM_DCR_DBSS              TIM_DCR_DBSS_Msk                             /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
+#define TIM_DCR_DBSS_0            (0x01UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00010000 */
+#define TIM_DCR_DBSS_1            (0x02UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00020000 */
+#define TIM_DCR_DBSS_2            (0x04UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00040000 */
+#define TIM_DCR_DBSS_3            (0x08UL << TIM_DCR_DBSS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+
+/*********************************************************************************/
+/*                                                                               */
+/*                                    UCPD                                       */
+/*                                                                               */
+/*********************************************************************************/
+/********************  Bits definition for UCPD_CFG1 register  *******************/
+#define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
+#define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
+#define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk             /*!< Number of cycles (minus 1) for a half bit clock */
+#define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
+#define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
+#define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
+#define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
+#define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
+#define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
+#define UCPD_CFG1_IFRGAP_Pos                (6U)
+#define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x000007C0 */
+#define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                 /*!< Clock divider value to generates Interframe gap */
+#define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000040 */
+#define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000080 */
+#define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000100 */
+#define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000200 */
+#define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)     /*!< 0x00000400 */
+#define UCPD_CFG1_TRANSWIN_Pos              (11U)
+#define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x0000F800 */
+#define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk               /*!< Number of cycles (minus 1) of the half bit clock */
+#define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00000800 */
+#define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00001000 */
+#define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00002000 */
+#define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00004000 */
+#define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)   /*!< 0x00008000 */
+#define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
+#define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
+#define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk            /*!< Prescaler for UCPDCLK */
+#define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
+#define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
+#define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
+#define UCPD_CFG1_RXORDSETEN_Pos            (20U)
+#define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
+#define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk             /*!< Receiver ordered set detection enable */
+#define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
+#define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
+#define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
+#define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
+#define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
+#define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
+#define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
+#define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
+#define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
+#define UCPD_CFG1_TXDMAEN_Pos               (29U)
+#define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)     /*!< 0x20000000 */
+#define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                /*!< DMA transmission requests enable   */
+#define UCPD_CFG1_RXDMAEN_Pos               (30U)
+#define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)     /*!< 0x40000000 */
+#define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                /*!< DMA reception requests enable   */
+#define UCPD_CFG1_UCPDEN_Pos                (31U)
+#define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)      /*!< 0x80000000 */
+#define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                 /*!< USB Power Delivery Block Enable */
+
+/********************  Bits definition for UCPD_CFG2 register  *******************/
+#define UCPD_CFG2_RXFILTDIS_Pos             (0U)
+#define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)   /*!< 0x00000001 */
+#define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk              /*!< Enables an Rx pre-filter for the BMC decoder */
+#define UCPD_CFG2_RXFILT2N3_Pos             (1U)
+#define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)   /*!< 0x00000002 */
+#define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk              /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
+#define UCPD_CFG2_FORCECLK_Pos              (2U)
+#define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)    /*!< 0x00000004 */
+#define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk               /*!< Controls forcing of the clock request UCPDCLK_REQ */
+#define UCPD_CFG2_WUPEN_Pos                 (3U)
+#define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)       /*!< 0x00000008 */
+#define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                  /*!< Wakeup from STOP enable */
+#define UCPD_CFG2_RXAFILTEN_Pos             (8U)
+#define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)   /*!< 0x00000100 */
+#define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk              /*!< Rx analog filter enable */
+
+/********************  Bits definition for UCPD_CR register  *********************/
+#define UCPD_CR_TXMODE_Pos                  (0U)
+#define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000003 */
+#define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000001 */
+#define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)        /*!< 0x00000002 */
+#define UCPD_CR_TXSEND_Pos                  (2U)
+#define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)        /*!< 0x00000004 */
+#define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                   /*!< Type of Tx packet  */
+#define UCPD_CR_TXHRST_Pos                  (3U)
+#define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)        /*!< 0x00000008 */
+#define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                   /*!< Command to send a Tx Hard Reset  */
+#define UCPD_CR_RXMODE_Pos                  (4U)
+#define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)        /*!< 0x00000010 */
+#define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                   /*!< Receiver mode  */
+#define UCPD_CR_PHYRXEN_Pos                 (5U)
+#define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)       /*!< 0x00000020 */
+#define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                  /*!< Controls enable of USB Power Delivery receiver  */
+#define UCPD_CR_PHYCCSEL_Pos                (6U)
+#define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)      /*!< 0x00000040 */
+#define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                 /*!<  */
+#define UCPD_CR_ANASUBMODE_Pos              (7U)
+#define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000180 */
+#define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk               /*!< Analog PHY sub-mode   */
+#define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000080 */
+#define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)    /*!< 0x00000100 */
+#define UCPD_CR_ANAMODE_Pos                 (9U)
+#define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)       /*!< 0x00000200 */
+#define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                  /*!< Analog PHY working mode   */
+#define UCPD_CR_CCENABLE_Pos                (10U)
+#define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000C00 */
+#define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                 /*!<  */
+#define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000400 */
+#define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)      /*!< 0x00000800 */
+#define UCPD_CR_USEEXTPHY_Pos               (12U)
+#define UCPD_CR_USEEXTPHY_Msk               (0x1UL << UCPD_CR_USEEXTPHY_Pos)     /*!< 0x00001000 */
+#define UCPD_CR_USEEXTPHY                   UCPD_CR_USEEXTPHY_Msk                /*!< Controls enable of USB Power Delivery transmitter */
+#define UCPD_CR_CC2VCONNEN_Pos              (13U)
+#define UCPD_CR_CC2VCONNEN_Msk              (0x1UL << UCPD_CR_CC2VCONNEN_Pos)    /*!< 0x00002000 */
+#define UCPD_CR_CC2VCONNEN                  UCPD_CR_CC2VCONNEN_Msk               /*!< VCONN enable for CC2 */
+#define UCPD_CR_CC1VCONNEN_Pos              (14U)
+#define UCPD_CR_CC1VCONNEN_Msk              (0x1UL << UCPD_CR_CC1VCONNEN_Pos)    /*!< 0x00004000 */
+#define UCPD_CR_CC1VCONNEN                  UCPD_CR_CC1VCONNEN_Msk               /*!< VCONN enable for CC1 */
+#define UCPD_CR_DBATEN_Pos                  (15U)
+#define UCPD_CR_DBATEN_Msk                  (0x1UL << UCPD_CR_DBATEN_Pos)        /*!< 0x00008000 */
+#define UCPD_CR_DBATEN                      UCPD_CR_DBATEN_Msk                   /*!< Enable dead battery behavior (Active High) */
+#define UCPD_CR_FRSTX_Pos                   (17U)
+#define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)         /*!< 0x00020000 */
+#define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                    /*!< Signal Fast Role Swap request */
+#define UCPD_CR_RDCH_Pos                    (18U)
+#define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)          /*!< 0x00040000 */
+#define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                     /*!<  */
+#define UCPD_CR_RPUSBABSENT_Pos             (19U)
+#define UCPD_CR_RPUSBABSENT_Msk             (0x1UL << UCPD_CR_RPUSBABSENT_Pos)   /*!< 0x00080000 */
+#define UCPD_CR_RPUSBABSENT                 UCPD_CR_RPUSBABSENT_Msk              /*!<  */
+#define UCPD_CR_CC1TCDIS_Pos                (20U)
+#define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)      /*!< 0x00100000 */
+#define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC0 to be disabled. */
+#define UCPD_CR_CC2TCDIS_Pos                (21U)
+#define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)      /*!< 0x00200000 */
+#define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                 /*!< The bit allows the Type-C detector for CC2 to be disabled. */
+
+/********************  Bits definition for UCPD_IMR register  ********************/
+#define UCPD_IMR_TXISIE_Pos                 (0U)
+#define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)       /*!< 0x00000001 */
+#define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                  /*!< Enable TXIS interrupt  */
+#define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
+#define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)  /*!< 0x00000002 */
+#define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk             /*!< Enable TXMSGDISC interrupt  */
+#define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
+#define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)  /*!< 0x00000004 */
+#define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk             /*!< Enable TXMSGSENT interrupt  */
+#define UCPD_IMR_TXMSGABTIE_Pos             (3U)
+#define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)   /*!< 0x00000008 */
+#define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk              /*!< Enable TXMSGABT interrupt  */
+#define UCPD_IMR_HRSTDISCIE_Pos             (4U)
+#define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)   /*!< 0x00000010 */
+#define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk              /*!< Enable HRSTDISC interrupt  */
+#define UCPD_IMR_HRSTSENTIE_Pos             (5U)
+#define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)   /*!< 0x00000020 */
+#define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk              /*!< Enable HRSTSENT interrupt  */
+#define UCPD_IMR_TXUNDIE_Pos                (6U)
+#define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)      /*!< 0x00000040 */
+#define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                 /*!< Enable TXUND interrupt  */
+#define UCPD_IMR_RXNEIE_Pos                 (8U)
+#define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)       /*!< 0x00000100 */
+#define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                  /*!< Enable RXNE interrupt  */
+#define UCPD_IMR_RXORDDETIE_Pos             (9U)
+#define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)   /*!< 0x00000200 */
+#define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk              /*!< Enable RXORDDET interrupt  */
+#define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
+#define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)  /*!< 0x00000400 */
+#define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk             /*!< Enable RXHRSTDET interrupt  */
+#define UCPD_IMR_RXOVRIE_Pos                (11U)
+#define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)      /*!< 0x00000800 */
+#define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                 /*!< Enable RXOVR interrupt  */
+#define UCPD_IMR_RXMSGENDIE_Pos             (12U)
+#define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)   /*!< 0x00001000 */
+#define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk              /*!< Enable RXMSGEND interrupt  */
+#define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
+#define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)  /*!< 0x00004000 */
+#define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk             /*!< Enable TYPECEVT1IE interrupt  */
+#define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
+#define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)  /*!< 0x00008000 */
+#define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk             /*!< Enable TYPECEVT2IE interrupt  */
+
+/********************  Bits definition for UCPD_SR register  *********************/
+#define UCPD_SR_TXIS_Pos                    (0U)
+#define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)          /*!< 0x00000001 */
+#define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                     /*!< Transmit interrupt status  */
+#define UCPD_SR_TXMSGDISC_Pos               (1U)
+#define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)     /*!< 0x00000002 */
+#define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                /*!< Transmit message discarded interrupt  */
+#define UCPD_SR_TXMSGSENT_Pos               (2U)
+#define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)     /*!< 0x00000004 */
+#define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                /*!< Transmit message sent interrupt  */
+#define UCPD_SR_TXMSGABT_Pos                (3U)
+#define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)      /*!< 0x00000008 */
+#define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                 /*!< Transmit message abort interrupt  */
+#define UCPD_SR_HRSTDISC_Pos                (4U)
+#define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)      /*!< 0x00000010 */
+#define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                 /*!< HRST discarded interrupt  */
+#define UCPD_SR_HRSTSENT_Pos                (5U)
+#define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)      /*!< 0x00000020 */
+#define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                 /*!< HRST sent interrupt  */
+#define UCPD_SR_TXUND_Pos                   (6U)
+#define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)         /*!< 0x00000040 */
+#define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                    /*!< Tx data underrun condition interrupt  */
+#define UCPD_SR_RXNE_Pos                    (8U)
+#define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)          /*!< 0x00000100 */
+#define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                     /*!< Receive data register not empty interrupt  */
+#define UCPD_SR_RXORDDET_Pos                (9U)
+#define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)      /*!< 0x00000200 */
+#define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                 /*!< Rx ordered set (4 K-codes) detected interrupt  */
+#define UCPD_SR_RXHRSTDET_Pos               (10U)
+#define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)     /*!< 0x00000400 */
+#define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                /*!< Rx Hard Reset detect interrupt  */
+#define UCPD_SR_RXOVR_Pos                   (11U)
+#define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)         /*!< 0x00000800 */
+#define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                    /*!< Rx data overflow interrupt  */
+#define UCPD_SR_RXMSGEND_Pos                (12U)
+#define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)      /*!< 0x00001000 */
+#define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                 /*!< Rx message received  */
+#define UCPD_SR_RXERR_Pos                   (13U)
+#define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)         /*!< 0x00002000 */
+#define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                    /*!< RX Error */
+#define UCPD_SR_TYPECEVT1_Pos               (14U)
+#define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)     /*!< 0x00004000 */
+#define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                /*!< Type C voltage level event on CC1  */
+#define UCPD_SR_TYPECEVT2_Pos               (15U)
+#define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)     /*!< 0x00008000 */
+#define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                /*!< Type C voltage level event on CC2  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
+#define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk           /*!< Status of DC level on CC1 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
+#define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
+#define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk           /*!<Status of DC level on CC2 pin  */
+#define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
+#define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
+
+/********************  Bits definition for UCPD_ICR register  ********************/
+#define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
+#define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)  /*!< 0x00000002 */
+#define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk             /*!< Tx message discarded flag (TXMSGDISC) clear  */
+#define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
+#define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)  /*!< 0x00000004 */
+#define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk             /*!< Tx message sent flag (TXMSGSENT) clear  */
+#define UCPD_ICR_TXMSGABTCF_Pos             (3U)
+#define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)   /*!< 0x00000008 */
+#define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk              /*!< Tx message abort flag (TXMSGABT) clear  */
+#define UCPD_ICR_HRSTDISCCF_Pos             (4U)
+#define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)   /*!< 0x00000010 */
+#define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk              /*!< Hard reset discarded flag (HRSTDISC) clear  */
+#define UCPD_ICR_HRSTSENTCF_Pos             (5U)
+#define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)   /*!< 0x00000020 */
+#define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk              /*!< Hard reset sent flag (HRSTSENT) clear  */
+#define UCPD_ICR_TXUNDCF_Pos                (6U)
+#define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)      /*!< 0x00000040 */
+#define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                 /*!< Tx underflow flag (TXUND) clear  */
+#define UCPD_ICR_RXORDDETCF_Pos             (9U)
+#define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)   /*!< 0x00000200 */
+#define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk              /*!< Rx ordered set detect flag (RXORDDET) clear  */
+#define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
+#define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)  /*!< 0x00000400 */
+#define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk             /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
+#define UCPD_ICR_RXOVRCF_Pos                (11U)
+#define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)      /*!< 0x00000800 */
+#define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                 /*!< Rx overflow flag (RXOVR) clear  */
+#define UCPD_ICR_RXMSGENDCF_Pos             (12U)
+#define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)   /*!< 0x00001000 */
+#define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk              /*!< Rx message received flag (RXMSGEND) clear  */
+#define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
+#define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)  /*!< 0x00004000 */
+#define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk             /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
+#define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
+#define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)  /*!< 0x00008000 */
+#define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk             /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
+
+/********************  Bits definition for UCPD_TXORDSET register  ***************/
+#define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
+#define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
+#define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk               /*!< Tx Ordered Set */
+
+/********************  Bits definition for UCPD_TXPAYSZ register  ****************/
+#define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
+#define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk             /*!< Tx payload size in bytes  */
+
+/********************  Bits definition for UCPD_TXDR register  *******************/
+#define UCPD_TXDR_TXDATA_Pos                (0U)
+#define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                 /*!< Tx Data Register */
+
+/********************  Bits definition for UCPD_RXORDSET register  ***************/
+#define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
+#define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
+#define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk            /*!< Rx Ordered Set Code detected  */
+#define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
+#define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
+#define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
+#define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
+#define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
+#define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk           /*!< Rx Ordered Set Debug indication */
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
+#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
+#define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk           /*!< Rx Ordered Set corrupted K-Codes (Debug) */
+
+/********************  Bits definition for UCPD_RXPAYSZ register  ****************/
+#define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
+#define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
+#define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk             /*!< Rx payload size in bytes  */
+
+/********************  Bits definition for UCPD_RXDR register  *******************/
+#define UCPD_RXDR_RXDATA_Pos                (0U)
+#define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)     /*!< 0x000000FF */
+#define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                 /*!< 8-bit receive data  */
+
+/********************  Bits definition for UCPD_RXORDEXT1 register  **************/
+#define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
+#define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+/********************  Bits definition for UCPD_RXORDEXT2 register  **************/
+#define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
+#define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
+#define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk               /*!< RX Ordered Set Extension Register 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                    (0U)
+#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
+#define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
+#define USART_CR1_UESM_Pos                  (1U)
+#define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
+#define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                    (2U)
+#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
+#define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                    (3U)
+#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
+#define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos                (4U)
+#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos                (5U)
+#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
+#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
+#define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos                  (6U)
+#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
+#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos                 (7U)
+#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos                  (8U)
+#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
+#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                    (9U)
+#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
+#define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
+#define USART_CR1_PCE_Pos                   (10U)
+#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
+#define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos                  (11U)
+#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
+#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                     (12U)
+#define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                         USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                    (12U)
+#define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
+#define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos                   (13U)
+#define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
+#define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos                  (14U)
+#define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
+#define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match Interrupt Enable */
+#define USART_CR1_OVER8_Pos                 (15U)
+#define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos                  (16U)
+#define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
+#define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos                  (21U)
+#define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
+#define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos                 (26U)
+#define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
+#define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out Interrupt Enable */
+#define USART_CR1_EOBIE_Pos                 (27U)
+#define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
+#define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block Interrupt Enable */
+#define USART_CR1_M1_Pos                    (28U)
+#define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
+#define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos                (29U)
+#define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos                (30U)
+#define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TX FIFO Empty Interrupt Enable */
+#define USART_CR1_RXFFIE_Pos                (31U)
+#define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RX FIFO Full Interrupt Enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos                 (0U)
+#define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
+#define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
+#define USART_CR2_DIS_NSS_Pos               (3U)
+#define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos                 (4U)
+#define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
+#define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos                  (5U)
+#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
+#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos                 (6U)
+#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
+#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos                  (8U)
+#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
+#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos                  (9U)
+#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
+#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos                  (10U)
+#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
+#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos                 (11U)
+#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
+#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
+#define USART_CR2_STOP_Pos                  (12U)
+#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
+#define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos                 (14U)
+#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
+#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos                  (15U)
+#define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
+#define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos                 (16U)
+#define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
+#define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos                 (17U)
+#define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
+#define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos               (18U)
+#define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
+#define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos              (19U)
+#define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos                 (20U)
+#define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
+#define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos               (21U)
+#define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
+#define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos                 (23U)
+#define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
+#define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos                   (24U)
+#define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
+#define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos                   (0U)
+#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
+#define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos                  (1U)
+#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
+#define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos                  (2U)
+#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
+#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos                 (3U)
+#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
+#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos                  (4U)
+#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
+#define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos                  (5U)
+#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
+#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos                  (6U)
+#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
+#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos                  (7U)
+#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
+#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos                  (8U)
+#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
+#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos                  (9U)
+#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
+#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos                 (10U)
+#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
+#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos                (11U)
+#define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos                (12U)
+#define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos                  (13U)
+#define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
+#define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos                   (14U)
+#define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
+#define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos                   (15U)
+#define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
+#define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos               (17U)
+#define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos                   (20U)
+#define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
+#define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos                 (22U)
+#define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
+#define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos                (23U)
+#define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TCBGTIE_Pos               (24U)
+#define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_Pos               (25U)
+#define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RX FIFO Threshold Configuration */
+#define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos                (28U)
+#define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RX FIFO Threshold Interrupt Enable */
+#define USART_CR3_TXFTCFG_Pos               (29U)
+#define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TX FIFO Threshold configuration */
+#define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_LPUART                    ((uint32_t)0x000FFFFF)                  /*!< LPUART Baud rate register [19:0] */
+#define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos                  (0U)
+#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
+#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos                   (8U)
+#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
+#define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos                  (0U)
+#define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Timeout Value */
+#define USART_RTOR_BLEN_Pos                 (24U)
+#define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos                 (0U)
+#define USART_RQR_ABRRQ_Msk                 (0x1UL << USART_RQR_ABRRQ_Pos)          /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                     USART_RQR_ABRRQ_Msk                     /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos                 (1U)
+#define USART_RQR_SBKRQ_Msk                 (0x1UL << USART_RQR_SBKRQ_Pos)          /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                     USART_RQR_SBKRQ_Msk                     /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos                  (2U)
+#define USART_RQR_MMRQ_Msk                  (0x1UL << USART_RQR_MMRQ_Pos)           /*!< 0x00000004 */
+#define USART_RQR_MMRQ                      USART_RQR_MMRQ_Msk                      /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos                 (3U)
+#define USART_RQR_RXFRQ_Msk                 (0x1UL << USART_RQR_RXFRQ_Pos)          /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                     USART_RQR_RXFRQ_Msk                     /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos                 (4U)
+#define USART_RQR_TXFRQ_Msk                 (0x1UL << USART_RQR_TXFRQ_Pos)          /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                     USART_RQR_TXFRQ_Msk                     /*!< Transmit Data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                    (0U)
+#define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
+#define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
+#define USART_ISR_FE_Pos                    (1U)
+#define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
+#define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
+#define USART_ISR_NE_Pos                    (2U)
+#define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
+#define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise Error detection Flag */
+#define USART_ISR_ORE_Pos                   (3U)
+#define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
+#define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos                  (4U)
+#define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
+#define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos                  (5U)
+#define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
+#define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
+#define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
+#define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                    (6U)
+#define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
+#define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos                   (7U)
+#define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
+#define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
+#define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
+#define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos                  (8U)
+#define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
+#define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos                 (9U)
+#define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
+#define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt Flag */
+#define USART_ISR_CTS_Pos                   (10U)
+#define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
+#define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS Flag */
+#define USART_ISR_RTOF_Pos                  (11U)
+#define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
+#define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Timeout */
+#define USART_ISR_EOBF_Pos                  (12U)
+#define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
+#define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos                   (13U)
+#define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
+#define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI Slave Underrun error Flag */
+#define USART_ISR_ABRE_Pos                  (14U)
+#define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
+#define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos                  (15U)
+#define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
+#define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos                  (16U)
+#define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
+#define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
+#define USART_ISR_CMF_Pos                   (17U)
+#define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
+#define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos                  (18U)
+#define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
+#define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos                   (19U)
+#define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
+#define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos                   (20U)
+#define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
+#define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
+#define USART_ISR_TEACK_Pos                 (21U)
+#define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
+#define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos                 (22U)
+#define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
+#define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos                  (23U)
+#define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
+#define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TX FIFO Empty Flag */
+#define USART_ISR_RXFF_Pos                  (24U)
+#define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
+#define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RX FIFO Full Flag */
+#define USART_ISR_TCBGT_Pos                 (25U)
+#define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
+#define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
+#define USART_ISR_RXFT_Pos                  (26U)
+#define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
+#define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RX FIFO Threshold Flag */
+#define USART_ISR_TXFT_Pos                  (27U)
+#define USART_ISR_TXFT_Msk                 (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
+#define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TX FIFO Threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos                  (0U)
+#define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
+#define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos                  (1U)
+#define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
+#define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos                  (2U)
+#define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
+#define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise Error detected Clear Flag */
+#define USART_ICR_ORECF_Pos                 (3U)
+#define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
+#define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos                (4U)
+#define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
+#define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos                (5U)
+#define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
+#define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TX FIFO Empty Clear Flag */
+#define USART_ICR_TCCF_Pos                  (6U)
+#define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
+#define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos               (7U)
+#define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos                 (8U)
+#define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
+#define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos                 (9U)
+#define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
+#define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos                 (11U)
+#define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
+#define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos                 (12U)
+#define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
+#define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos                 (13U)
+#define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
+#define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF_Pos                  (17U)
+#define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
+#define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos                  (20U)
+#define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
+#define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ****************/
+#define USART_PRESC_PRESCALER_Pos           (0U)
+#define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_CSRSTDONE_Pos            (29U)
+#define USB_OTG_GRSTCTL_CSRSTDONE_Msk            (0x1UL << USB_OTG_GRSTCTL_CSRSTDONE_Pos) /*!< 0x20000000 */
+#define USB_OTG_GRSTCTL_CSRSTDONE                USB_OTG_GRSTCTL_CSRSTDONE_Msk   /*!< Core soft reset done            */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_HS_GCCFG register  ********************/
+#define USB_OTG_GCCFG_CHGDET_Pos                 (0U)
+#define USB_OTG_GCCFG_CHGDET_Msk                 (0x1U << USB_OTG_GCCFG_CHGDET_Pos)           /*!< 0x00000001 */
+#define USB_OTG_GCCFG_CHGDET                     USB_OTG_GCCFG_CHGDET_Msk                     /*!< Battery Charger Detection */
+#define USB_OTG_GCCFG_FSVPLUS_Pos                (1U)
+#define USB_OTG_GCCFG_FSVPLUS_Msk                (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos)          /*!< 0x00000002 */
+#define USB_OTG_GCCFG_FSVPLUS                    USB_OTG_GCCFG_FSVPLUS_Msk                    /*!< Single-Ended DP2 indicator DP voltage level  */
+#define USB_OTG_GCCFG_FSVMINUS_Pos               (2U)
+#define USB_OTG_GCCFG_FSVMINUS_Msk               0x1U << USB_OTG_GCCFG_FSVMINUS_Pos)         /*!< 0x00000004 */
+#define USB_OTG_GCCFG_FSVMINUS                   USB_OTG_GCCFG_FSVMINUS_Msk                  /*!< Single-Ended DM2 indicator DM voltage level  */
+#define USB_OTG_GCCFG_SESSVLD_Pos                (3U)
+#define USB_OTG_GCCFG_SESSVLD_Msk                (0x1U << USB_OTG_GCCFG_SESSVLD_Pos)          /*!< 0x00000008 */
+#define USB_OTG_GCCFG_SESSVLD                    USB_OTG_GCCFG_SESSVLD_Msk                    /*!< VBUS session valid indicator: Vbus is above VBUS session threshold.  */
+#define USB_OTG_GCCFG_VBUSVLD_Pos                (4U)
+#define USB_OTG_GCCFG_VBUSVLD_Msk                (0x1U << USB_OTG_GCCFG_VBUSVLD_Pos)          /*!< 0x00000010 */
+#define USB_OTG_GCCFG_VBUSVLD                    USB_OTG_GCCFG_VBUSVLD_Msk                    /*!< VBUS session valid indicator: VBUS is above VBUS valid threshold.  */
+#define USB_OTG_GCCFG_H_CDPEN_Pos                (16U)
+#define USB_OTG_GCCFG_H_CDPEN_Msk                (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos)          /*!< 0x00010000 */
+#define USB_OTG_GCCFG_H_CDPEN                    USB_OTG_GCCFG_H_CDPEN_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
+#define USB_OTG_GCCFG_H_CDPDETEN_Pos             (17U)
+#define USB_OTG_GCCFG_H_CDPDETEN_Msk             (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos)       /*!< 0x00020000 */
+#define USB_OTG_GCCFG_H_CDPDETEN                 USB_OTG_GCCFG_H_CDPDETEN_Msk                 /*!< Enable of voltage detector on DP for CDP port  */
+#define USB_OTG_GCCFG_H_VDMSRCEN_Pos             (18U)
+#define USB_OTG_GCCFG_H_VDMSRCEN_Msk             (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos)       /*!< 0x00040000 */
+#define USB_OTG_GCCFG_H_VDMSRCEN                 USB_OTG_GCCFG_H_VDMSRCEN_Msk                 /*!< Enable Voltage source on DM for CDP port */
+#define USB_OTG_GCCFG_DCDETEN_Pos                (19U)
+#define USB_OTG_GCCFG_DCDETEN_Msk                (0x1U << USB_OTG_GCCFG_DCDETEN_Pos)          /*!< 0x00080000 */
+#define USB_OTG_GCCFG_DCDETEN                    USB_OTG_GCCFG_DCDETEN_Msk                    /*!< Data contact detection (DCD) mode enable */
+#define USB_OTG_GCCFG_PDETEN_Pos                 (20U)
+#define USB_OTG_GCCFG_PDETEN_Msk                 (0x1U << USB_OTG_GCCFG_PDETEN_Pos)           /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDETEN                     USB_OTG_GCCFG_PDETEN_Msk                     /*!< Primary detection (PD) mode enable */
+#define USB_OTG_GCCFG_SDETEN_Pos                 (22U)
+#define USB_OTG_GCCFG_SDETEN_Msk                 (0x1U << USB_OTG_GCCFG_SDETEN_Pos)           /*!< 0x00400000 */
+#define USB_OTG_GCCFG_SDETEN                     USB_OTG_GCCFG_SDETEN_Msk                     /*!< Secondary detection (PD) mode enable */
+#define USB_OTG_GCCFG_VBVALOVAL_Pos              (23U)
+#define USB_OTG_GCCFG_VBVALOVAL_Msk              (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos)        /*!< 0x00800000 */
+#define USB_OTG_GCCFG_VBVALOVAL                  USB_OTG_GCCFG_VBVALOVAL_Msk                  /*!< Value of VBUSVLDEXT0 PHY input */
+#define USB_OTG_GCCFG_VBVALEXTOEN_Pos            (24U)
+#define USB_OTG_GCCFG_VBVALEXTOEN_Msk            (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos)      /*!< 0x01000000 */
+#define USB_OTG_GCCFG_VBVALEXTOEN                USB_OTG_GCCFG_VBVALEXTOEN_Msk                /*!< Enables of VBUSVLDEXT0 PHY input override */
+#define USB_OTG_GCCFG_PULLDOWNEN_Pos             (25U)
+#define USB_OTG_GCCFG_PULLDOWNEN_Msk             (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos)       /*!< 0x02000000 */
+#define USB_OTG_GCCFG_PULLDOWNEN                 USB_OTG_GCCFG_PULLDOWNEN_Msk                 /*!< Enables Host pulldown resistors, used when ID PAD is disabled */
+#define USB_OTG_GCCFG_FORCEBCMODE_Pos            (26U)
+#define USB_OTG_GCCFG_FORCEBCMODE_Msk            (0x1U << USB_OTG_GCCFG_FORCEBCMODE_Pos)      /*!< 0x04000000 */
+#define USB_OTG_GCCFG_FORCEBCMODE                USB_OTG_GCCFG_FORCEBCMODE_Msk                /*!< Force Battery charging (BC) mode */
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Pos           (28U)
+#define USB_OTG_GCCFG_IDPULLUP_DIS_Msk           (0x1U << USB_OTG_GCCFG_IDPULLUP_DIS_Pos)      /*!< 0x10000000 */
+#define USB_OTG_GCCFG_IDPULLUP_DIS               USB_OTG_GCCFG_IDPULLUP_DIS_Msk                /*!< Analog ID Input Sample Disable: disable sampling on the analog ID line */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/********************  Bit definition for USB_OTG_PCGCCTL1 register  ********************/
+#define USB_OTG_PCGCCTL1_GATEEN_Pos               (0U)
+#define USB_OTG_PCGCCTL1_GATEEN_Msk               (0x1UL << USB_OTG_PCGCCTL1_GATEEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL1_GATEEN                   USB_OTG_PCGCCTL1_GATEEN_Msk   /*!< Enable Active Clock Gating */
+#define USB_OTG_PCGCCTL1_COUNTER_Pos              (1U)
+#define USB_OTG_PCGCCTL1_COUNTER_Msk              (0x3UL << USB_OTG_PCGCCTL1_COUNTER_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL1_COUNTER                  USB_OTG_PCGCCTL1_COUNTER_Msk   /*!< Count to Gate Clock */
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Pos            (3U)
+#define USB_OTG_PCGCCTL1_RAMGATEEN_Msk            (0x1UL << USB_OTG_PCGCCTL1_RAMGATEEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL1_RAMGATEEN                USB_OTG_PCGCCTL1_RAMGATEEN_Msk   /*!< RAM Clock Gating Enable */
+
+/*!< USB registers base address */
+#define USB_OTG_GLOBAL_BASE                       (0x000UL)
+#define USB_OTG_DEVICE_BASE                       (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE                  (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE                 (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                       (0x20UL)
+#define USB_OTG_HOST_BASE                         (0x400UL)
+#define USB_OTG_HOST_PORT_BASE                    (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE                 (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE                 (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                      (0xE00UL)
+#define USB_OTG_FIFO_BASE                         (0x1000UL)
+#define USB_OTG_FIFO_SIZE                         (0x1000UL)
+#define USB_OTG_HS_EP_NBR                         (9UL)            /*!< Number of USB HS Device endpoints */
+#define USB_OTG_HS_CH_NBR                         (16UL)           /*!< Number of USB HS Host channels */
+
+/********************  Bit definition for USB_USBPHYC_CR register  ********************/
+#define USB_USBPHYC_CR_RETENABLEN1_Pos          (0U)
+#define USB_USBPHYC_CR_RETENABLEN1_Msk          (0x1UL << USB_USBPHYC_CR_RETENABLEN1_Pos)    /*!< 0x00000001 */
+#define USB_USBPHYC_CR_RETENABLEN1              USB_USBPHYC_CR_RETENABLEN1_Msk               /*!< Retention mode enable */
+#define USB_USBPHYC_CR_AUTORSMENB1_Pos          (1U)
+#define USB_USBPHYC_CR_AUTORSMENB1_Msk          (0x1UL << USB_USBPHYC_CR_AUTORSMENB1_Pos)    /*!< 0x00000002 */
+#define USB_USBPHYC_CR_AUTORSMENB1              USB_USBPHYC_CR_AUTORSMENB1_Msk               /*!< Auto-resume mode enable */
+#define USB_USBPHYC_CR_CMN_Pos                  (2U)
+#define USB_USBPHYC_CR_CMN_Msk                  (0x1UL << USB_USBPHYC_CR_CMN_Pos)            /*!< 0x00000004 */
+#define USB_USBPHYC_CR_CMN                      USB_USBPHYC_CR_CMN_Msk                       /*!< Controls the power down of analog blocks during Suspend and Sleep */
+#define USB_USBPHYC_CR_FSEL_Pos                 (4U)
+#define USB_USBPHYC_CR_FSEL_Msk                 (0x7UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000070 */
+#define USB_USBPHYC_CR_FSEL                     USB_USBPHYC_CR_FSEL_Msk                      /*!< Frequency selection */
+#define USB_USBPHYC_CR_FSEL_0                   (0x1UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000010 */
+#define USB_USBPHYC_CR_FSEL_1                   (0x2UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000020 */
+#define USB_USBPHYC_CR_FSEL_2                   (0x3UL << USB_USBPHYC_CR_FSEL_Pos)           /*!< 0x00000040 */
+#define USB_USBPHYC_CR_OTGDISABLE0_Pos          (16U)
+#define USB_USBPHYC_CR_OTGDISABLE0_Msk          (0x1UL << USB_USBPHYC_CR_OTGDISABLE0_Pos)    /*!< 0x00010000 */
+#define USB_USBPHYC_CR_OTGDISABLE0              USB_USBPHYC_CR_OTGDISABLE0_Msk               /*!< OTG disable 0 */
+#define USB_USBPHYC_CR_DRVVBUS0_Pos             (17U)
+#define USB_USBPHYC_CR_DRVVBUS0_Msk             (0x1UL << USB_USBPHYC_CR_DRVVBUS0_Pos)       /*!< 0x00020000 */
+#define USB_USBPHYC_CR_DRVVBUS0                 USB_USBPHYC_CR_DRVVBUS0_Msk                  /*!< Drive VBUS 0 */
+#define USB_USBPHYC_CR_SELOTGDBG_Pos            (31U)
+#define USB_USBPHYC_CR_SELOTGDBG_Msk            (0x1UL << USB_USBPHYC_CR_SELOTGDBG_Pos)      /*!< 0x80000000 */
+#define USB_USBPHYC_CR_SELOTGDBG                USB_USBPHYC_CR_SELOTGDBG_Msk                 /*!< Select HS PHY debug port */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)
+#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)
+#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos     (3U)
+#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos     (4U)
+#define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
+#define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000040 */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos                (0U)
+#define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos                       (0U)
+#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
+#define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
+#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
+#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
+#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
+#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
+#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
+#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
+#define WWDG_CR_WDGA_Pos                    (7U)
+#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
+#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos                      (0U)
+#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
+#define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
+#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
+#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
+#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
+#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
+#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
+#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
+#define WWDG_CFR_EWI_Pos                    (9U)
+#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
+#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
+#define WWDG_CFR_WDGTB_Pos                  (11U)
+#define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos                    (0U)
+#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
+#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Extended-SPI Interface (XSPI)                         */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for XSPI_CR register  *******************/
+#define XSPI_CR_EN_Pos                   (0U)
+#define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)            /*!< 0x00000001 */
+#define XSPI_CR_EN                       XSPI_CR_EN_Msk                       /*!< Enable */
+#define XSPI_CR_ABORT_Pos                (1U)
+#define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
+#define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define XSPI_CR_DMAEN_Pos                (2U)
+#define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
+#define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define XSPI_CR_TCEN_Pos                 (3U)
+#define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
+#define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define XSPI_CR_DMM_Pos                  (6U)
+#define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)           /*!< 0x00000040 */
+#define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                      /*!< Dual Memory Mode */
+#define XSPI_CR_FSEL_Pos                 (7U)
+#define XSPI_CR_FSEL_Msk                 (0x1UL << XSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
+#define XSPI_CR_FSEL                     XSPI_CR_FSEL_Msk                     /*!< Flash Select */
+#define XSPI_CR_FTHRES_Pos               (8U)
+#define XSPI_CR_FTHRES_Msk               (0x3FUL << XSPI_CR_FTHRES_Pos)       /*!< 0x00003F00 */
+#define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */
+#define XSPI_CR_TEIE_Pos                 (16U)
+#define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
+#define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define XSPI_CR_TCIE_Pos                 (17U)
+#define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
+#define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define XSPI_CR_FTIE_Pos                 (18U)
+#define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
+#define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define XSPI_CR_SMIE_Pos                 (19U)
+#define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
+#define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define XSPI_CR_TOIE_Pos                 (20U)
+#define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
+#define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define XSPI_CR_APMS_Pos                 (22U)
+#define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)          /*!< 0x00400000 */
+#define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */
+#define XSPI_CR_PMM_Pos                  (23U)
+#define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)           /*!< 0x00800000 */
+#define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define XSPI_CR_CSSEL_Pos                (24U)
+#define XSPI_CR_CSSEL_Msk                (0x1UL << XSPI_CR_CSSEL_Pos)         /*!< 0x01000000 */
+#define XSPI_CR_CSSEL                    XSPI_CR_CSSEL_Msk                    /*!< Chip Select Selection */
+#define XSPI_CR_NOPREF_Pos               (25U)
+#define XSPI_CR_NOPREF_Msk               (0x1UL << XSPI_CR_NOPREF_Pos)        /*!< 0x02000000 */
+#define XSPI_CR_NOPREF                   XSPI_CR_NOPREF_Msk                   /*!< No Prefetch Data */
+#define XSPI_CR_NOPREF_AXI_Pos           (26U)
+#define XSPI_CR_NOPREF_AXI_Msk           (0x1UL << XSPI_CR_NOPREF_AXI_Pos)    /*!< 0x04000000 */
+#define XSPI_CR_NOPREF_AXI               XSPI_CR_NOPREF_AXI_Msk               /*!< No Prefetch For Signaled AXI Transactions */
+#define XSPI_CR_FMODE_Pos                (28U)
+#define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)         /*!< 0x30000000 */
+#define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                    /*!< Functional Mode */
+#define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)         /*!< 0x10000000 */
+#define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)         /*!< 0x20000000 */
+#define XSPI_CR_MSEL_Pos                 (30U)
+#define XSPI_CR_MSEL_Msk                 (0x3UL << XSPI_CR_MSEL_Pos)          /*!< 0xC0000000 */
+#define XSPI_CR_MSEL                     XSPI_CR_MSEL_Msk                     /*!< Memory Select */
+#define XSPI_CR_MSEL_0                   (0x1UL << XSPI_CR_MSEL_Pos)          /*!< 0x40000000 */
+#define XSPI_CR_MSEL_1                   (0x2UL << XSPI_CR_MSEL_Pos)          /*!< 0x80000000 */
+
+/****************  Bit definition for XSPI_DCR1 register  ******************/
+#define XSPI_DCR1_CKMODE_Pos             (0U)
+#define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */
+#define XSPI_DCR1_FRCK_Pos               (1U)
+#define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)        /*!< 0x00000002 */
+#define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */
+#define XSPI_DCR1_CSHT_Pos               (8U)
+#define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)       /*!< 0x00003F00 */
+#define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
+#define XSPI_DCR1_DEVSIZE_Pos            (16U)
+#define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */
+#define XSPI_DCR1_EXTENDMEM_Pos          (21U)
+#define XSPI_DCR1_EXTENDMEM_Msk          (0x1UL << XSPI_DCR1_EXTENDMEM_Pos)   /*!< 0x00200000 */
+#define XSPI_DCR1_EXTENDMEM              XSPI_DCR1_EXTENDMEM_Msk              /*!< Extended Memory Support */
+#define XSPI_DCR1_MTYP_Pos               (24U)
+#define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x07000000 */
+#define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                   /*!< Memory Type */
+#define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x01000000 */
+#define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x02000000 */
+#define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)        /*!< 0x04000000 */
+
+/****************  Bit definition for XSPI_DCR2 register  ******************/
+#define XSPI_DCR2_PRESCALER_Pos          (0U)
+#define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)  /*!< 0x000000FF */
+#define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */
+#define XSPI_DCR2_WRAPSIZE_Pos           (16U)
+#define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00070000 */
+#define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */
+#define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00010000 */
+#define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00020000 */
+#define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)    /*!< 0x00040000 */
+
+/****************  Bit definition for XSPI_DCR3 register  ******************/
+#define XSPI_DCR3_MAXTRAN_Pos            (0U)
+#define XSPI_DCR3_MAXTRAN_Msk            (0xFFUL << XSPI_DCR3_MAXTRAN_Pos)    /*!< 0x000000FF */
+#define XSPI_DCR3_MAXTRAN                XSPI_DCR3_MAXTRAN_Msk                /*!< Maximum transfer */
+#define XSPI_DCR3_CSBOUND_Pos            (16U)
+#define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)    /*!< 0x001F0000 */
+#define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                /*!< Maximum transfer */
+
+/****************  Bit definition for XSPI_DCR4 register  ******************/
+#define XSPI_DCR4_REFRESH_Pos            (0U)
+#define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */
+
+/*****************  Bit definition for XSPI_SR register  *******************/
+#define XSPI_SR_TEF_Pos                  (0U)
+#define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)           /*!< 0x00000001 */
+#define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define XSPI_SR_TCF_Pos                  (1U)
+#define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)           /*!< 0x00000002 */
+#define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define XSPI_SR_FTF_Pos                  (2U)
+#define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)           /*!< 0x00000004 */
+#define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */
+#define XSPI_SR_SMF_Pos                  (3U)
+#define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)           /*!< 0x00000008 */
+#define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define XSPI_SR_TOF_Pos                  (4U)
+#define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)           /*!< 0x00000010 */
+#define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define XSPI_SR_BUSY_Pos                 (5U)
+#define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
+#define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                     /*!< Busy */
+#define XSPI_SR_FLEVEL_Pos               (8U)
+#define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)       /*!< 0x00007F00 */
+#define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */
+
+/****************  Bit definition for XSPI_FCR register  *******************/
+#define XSPI_FCR_CTEF_Pos                (0U)
+#define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
+#define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define XSPI_FCR_CTCF_Pos                (1U)
+#define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
+#define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define XSPI_FCR_CSMF_Pos                (3U)
+#define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
+#define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define XSPI_FCR_CTOF_Pos                (4U)
+#define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
+#define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/****************  Bit definition for XSPI_DLR register  *******************/
+#define XSPI_DLR_DL_Pos                  (0U)
+#define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
+#define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                      /*!< Data Length */
+
+/*****************  Bit definition for XSPI_AR register  *******************/
+#define XSPI_AR_ADDRESS_Pos              (0U)
+#define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                  /*!< Address */
+
+/*****************  Bit definition for XSPI_DR register  *******************/
+#define XSPI_DR_DATA_Pos                 (0U)
+#define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
+#define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                     /*!< Data */
+
+/***************  Bit definition for XSPI_PSMKR register  ******************/
+#define XSPI_PSMKR_MASK_Pos              (0U)
+#define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                  /*!< Status mask */
+
+/***************  Bit definition for XSPI_PSMAR register  ******************/
+#define XSPI_PSMAR_MATCH_Pos             (0U)
+#define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                 /*!< Status match */
+
+/****************  Bit definition for XSPI_PIR register  *******************/
+#define XSPI_PIR_INTERVAL_Pos            (0U)
+#define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
+#define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */
+
+/****************  Bit definition for XSPI_CCR register  *******************/
+#define XSPI_CCR_IMODE_Pos               (0U)
+#define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000007 */
+#define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */
+#define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000001 */
+#define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000002 */
+#define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)        /*!< 0x00000004 */
+#define XSPI_CCR_IDTR_Pos                (3U)
+#define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)         /*!< 0x00000008 */
+#define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */
+#define XSPI_CCR_ISIZE_Pos               (4U)
+#define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000030 */
+#define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */
+#define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000010 */
+#define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)        /*!< 0x00000020 */
+#define XSPI_CCR_ADMODE_Pos              (8U)
+#define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000700 */
+#define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                  /*!< Address Mode */
+#define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000100 */
+#define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000200 */
+#define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define XSPI_CCR_ADDTR_Pos               (11U)
+#define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)        /*!< 0x00000800 */
+#define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */
+#define XSPI_CCR_ADSIZE_Pos              (12U)
+#define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                  /*!< Address Size */
+#define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define XSPI_CCR_ABMODE_Pos              (16U)
+#define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00070000 */
+#define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */
+#define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00010000 */
+#define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00020000 */
+#define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)       /*!< 0x00040000 */
+#define XSPI_CCR_ABDTR_Pos               (19U)
+#define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)        /*!< 0x00080000 */
+#define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_CCR_ABSIZE_Pos              (20U)
+#define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00300000 */
+#define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */
+#define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00100000 */
+#define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)       /*!< 0x00200000 */
+#define XSPI_CCR_DMODE_Pos               (24U)
+#define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)        /*!< 0x07000000 */
+#define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                   /*!< Data Mode */
+#define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)        /*!< 0x04000000 */
+#define XSPI_CCR_DDTR_Pos                (27U)
+#define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)         /*!< 0x08000000 */
+#define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */
+#define XSPI_CCR_DQSE_Pos                (29U)
+#define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)         /*!< 0x20000000 */
+#define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                    /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_TCR register  *******************/
+#define XSPI_TCR_DCYC_Pos                (0U)
+#define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)        /*!< 0x0000001F */
+#define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */
+#define XSPI_TCR_DHQC_Pos                (28U)
+#define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)         /*!< 0x10000000 */
+#define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */
+#define XSPI_TCR_SSHIFT_Pos              (30U)
+#define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)       /*!< 0x40000000 */
+#define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_IR register  *******************/
+#define XSPI_IR_INSTRUCTION_Pos          (0U)
+#define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk              /*!< Instruction */
+
+/****************  Bit definition for XSPI_ABR register  *******************/
+#define XSPI_ABR_ALTERNATE_Pos           (0U)
+#define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_LPTR register  ******************/
+#define XSPI_LPTR_TIMEOUT_Pos            (0U)
+#define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
+#define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */
+
+/****************  Bit definition for XSPI_WPCCR register  *******************/
+#define XSPI_WPCCR_IMODE_Pos             (0U)
+#define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000007 */
+#define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */
+#define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000001 */
+#define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000002 */
+#define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)      /*!< 0x00000004 */
+#define XSPI_WPCCR_IDTR_Pos              (3U)
+#define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)       /*!< 0x00000008 */
+#define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */
+#define XSPI_WPCCR_ISIZE_Pos             (4U)
+#define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000030 */
+#define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */
+#define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000010 */
+#define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)      /*!< 0x00000020 */
+#define XSPI_WPCCR_ADMODE_Pos            (8U)
+#define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000700 */
+#define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */
+#define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000100 */
+#define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000200 */
+#define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)     /*!< 0x00000400 */
+#define XSPI_WPCCR_ADDTR_Pos             (11U)
+#define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)      /*!< 0x00000800 */
+#define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */
+#define XSPI_WPCCR_ADSIZE_Pos            (12U)
+#define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00003000 */
+#define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */
+#define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00001000 */
+#define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)     /*!< 0x00002000 */
+#define XSPI_WPCCR_ABMODE_Pos            (16U)
+#define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00070000 */
+#define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */
+#define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00010000 */
+#define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00020000 */
+#define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)     /*!< 0x00040000 */
+#define XSPI_WPCCR_ABDTR_Pos             (19U)
+#define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)      /*!< 0x00080000 */
+#define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WPCCR_ABSIZE_Pos            (20U)
+#define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00300000 */
+#define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */
+#define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00100000 */
+#define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)     /*!< 0x00200000 */
+#define XSPI_WPCCR_DMODE_Pos             (24U)
+#define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x07000000 */
+#define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */
+#define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x01000000 */
+#define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x02000000 */
+#define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)      /*!< 0x04000000 */
+#define XSPI_WPCCR_DDTR_Pos              (27U)
+#define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)       /*!< 0x08000000 */
+#define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */
+#define XSPI_WPCCR_DQSE_Pos              (29U)
+#define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)       /*!< 0x20000000 */
+#define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WPTCR register  *******************/
+#define XSPI_WPTCR_DCYC_Pos              (0U)
+#define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)      /*!< 0x0000001F */
+#define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */
+#define XSPI_WPTCR_DHQC_Pos              (28U)
+#define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)       /*!< 0x10000000 */
+#define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */
+#define XSPI_WPTCR_SSHIFT_Pos            (30U)
+#define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)     /*!< 0x40000000 */
+#define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */
+
+/*****************  Bit definition for XSPI_WPIR register  *******************/
+#define XSPI_WPIR_INSTRUCTION_Pos        (0U)
+#define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */
+
+/****************  Bit definition for XSPI_WPABR register  *******************/
+#define XSPI_WPABR_ALTERNATE_Pos         (0U)
+#define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_WCCR register  ******************/
+#define XSPI_WCCR_IMODE_Pos              (0U)
+#define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000007 */
+#define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */
+#define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000001 */
+#define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000002 */
+#define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)       /*!< 0x00000004 */
+#define XSPI_WCCR_IDTR_Pos               (3U)
+#define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)        /*!< 0x00000008 */
+#define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */
+#define XSPI_WCCR_ISIZE_Pos              (4U)
+#define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000030 */
+#define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */
+#define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000010 */
+#define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)       /*!< 0x00000020 */
+#define XSPI_WCCR_ADMODE_Pos             (8U)
+#define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000700 */
+#define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */
+#define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000100 */
+#define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000200 */
+#define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)      /*!< 0x00000400 */
+#define XSPI_WCCR_ADDTR_Pos              (11U)
+#define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)       /*!< 0x00000800 */
+#define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */
+#define XSPI_WCCR_ADSIZE_Pos             (12U)
+#define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00003000 */
+#define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */
+#define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00001000 */
+#define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)      /*!< 0x00002000 */
+#define XSPI_WCCR_ABMODE_Pos             (16U)
+#define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00070000 */
+#define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */
+#define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00010000 */
+#define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00020000 */
+#define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)      /*!< 0x00040000 */
+#define XSPI_WCCR_ABDTR_Pos              (19U)
+#define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)       /*!< 0x00080000 */
+#define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */
+#define XSPI_WCCR_ABSIZE_Pos             (20U)
+#define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00300000 */
+#define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */
+#define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00100000 */
+#define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)      /*!< 0x00200000 */
+#define XSPI_WCCR_DMODE_Pos              (24U)
+#define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x07000000 */
+#define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                  /*!< Data Mode */
+#define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x01000000 */
+#define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x02000000 */
+#define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)       /*!< 0x04000000 */
+#define XSPI_WCCR_DDTR_Pos               (27U)
+#define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)        /*!< 0x08000000 */
+#define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */
+#define XSPI_WCCR_DQSE_Pos               (29U)
+#define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)        /*!< 0x20000000 */
+#define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */
+
+/****************  Bit definition for XSPI_WTCR register  ******************/
+#define XSPI_WTCR_DCYC_Pos               (0U)
+#define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)       /*!< 0x0000001F */
+#define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */
+
+/****************  Bit definition for XSPI_WIR register  *******************/
+#define XSPI_WIR_INSTRUCTION_Pos         (0U)
+#define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */
+
+/****************  Bit definition for XSPI_WABR register  ******************/
+#define XSPI_WABR_ALTERNATE_Pos          (0U)
+#define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */
+
+/****************  Bit definition for XSPI_HLCR register  ******************/
+#define XSPI_HLCR_LM_Pos                 (0U)
+#define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)          /*!< 0x00000001 */
+#define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                     /*!< Latency Mode */
+#define XSPI_HLCR_WZL_Pos                (1U)
+#define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)         /*!< 0x00000002 */
+#define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */
+#define XSPI_HLCR_TACC_Pos               (8U)
+#define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)       /*!< 0x0000FF00 */
+#define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                   /*!< Access Time */
+#define XSPI_HLCR_TRWR_Pos               (16U)
+#define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)       /*!< 0x00FF0000 */
+#define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */
+
+/****************  Bit definition for XSPI_CALFCR register  ****************/
+#define XSPI_CALFCR_FINE_Pos             (0U)
+#define XSPI_CALFCR_FINE_Msk             (0x7FUL << XSPI_CALFCR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALFCR_FINE                 XSPI_CALFCR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALFCR_COARSE_Pos           (16U)
+#define XSPI_CALFCR_COARSE_Msk           (0x1FUL << XSPI_CALFCR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALFCR_COARSE               XSPI_CALFCR_COARSE_Msk               /*!< Coarse Calibration */
+#define XSPI_CALFCR_CALMAX_Pos           (31U)
+#define XSPI_CALFCR_CALMAX_Msk           (0x1UL << XSPI_CALFCR_CALMAX_Pos)    /*!< 0x80000000 */
+#define XSPI_CALFCR_CALMAX               XSPI_CALFCR_CALMAX_Msk               /*!< Max Value */
+
+/****************  Bit definition for XSPI_CALMR register  *****************/
+#define XSPI_CALMR_FINE_Pos              (0U)
+#define XSPI_CALMR_FINE_Msk              (0x7FUL << XSPI_CALMR_FINE_Pos)      /*!< 0x0000007F */
+#define XSPI_CALMR_FINE                  XSPI_CALMR_FINE_Msk                  /*!< Fine Calibration */
+#define XSPI_CALMR_COARSE_Pos            (16U)
+#define XSPI_CALMR_COARSE_Msk            (0x1FUL << XSPI_CALMR_COARSE_Pos)    /*!< 0x001F0000 */
+#define XSPI_CALMR_COARSE                XSPI_CALMR_COARSE_Msk                /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSOR register  ****************/
+#define XSPI_CALSOR_FINE_Pos             (0U)
+#define XSPI_CALSOR_FINE_Msk             (0x7FUL << XSPI_CALSOR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSOR_FINE                 XSPI_CALSOR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSOR_COARSE_Pos           (16U)
+#define XSPI_CALSOR_COARSE_Msk           (0x1FUL << XSPI_CALSOR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSOR_COARSE               XSPI_CALSOR_COARSE_Msk               /*!< Coarse Calibration */
+
+/****************  Bit definition for XSPI_CALSIR register  ****************/
+#define XSPI_CALSIR_FINE_Pos             (0U)
+#define XSPI_CALSIR_FINE_Msk             (0x7FUL << XSPI_CALSIR_FINE_Pos)     /*!< 0x0000007F */
+#define XSPI_CALSIR_FINE                 XSPI_CALSIR_FINE_Msk                 /*!< Fine Calibration */
+#define XSPI_CALSIR_COARSE_Pos           (16U)
+#define XSPI_CALSIR_COARSE_Msk           (0x1FUL << XSPI_CALSIR_COARSE_Pos)   /*!< 0x001F0000 */
+#define XSPI_CALSIR_COARSE               XSPI_CALSIR_COARSE_Msk               /*!< Coarse Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 XSPIM                                      */
+/*                                                                            */
+/******************************************************************************/
+/***************  Bit definition for XSPIM_CR register  ********************/
+#define XSPIM_CR_MUXEN_Pos               (0U)
+#define XSPIM_CR_MUXEN_Msk               (0x1UL << XSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */
+#define XSPIM_CR_MUXEN                   XSPIM_CR_MUXEN_Msk                   /*!< Multiplexed Mode Enable */
+#define XSPIM_CR_MODE_Pos                (1U)
+#define XSPIM_CR_MODE_Msk                (0x1UL << XSPIM_CR_MODE_Pos)         /*!< 0x00000002 */
+#define XSPIM_CR_MODE                    XSPIM_CR_MODE_Msk                    /*!< Multiplexing Mode */
+#define XSPIM_CR_CSSEL_OVR_EN_Pos        (4U)
+#define XSPIM_CR_CSSEL_OVR_EN_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_EN_Pos) /*!< 0x00000010 */
+#define XSPIM_CR_CSSEL_OVR_EN            XSPIM_CR_CSSEL_OVR_EN_Msk            /*!< Chip Select Selector Override Enable */
+#define XSPIM_CR_CSSEL_OVR_O1_Pos        (5U)
+#define XSPIM_CR_CSSEL_OVR_O1_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O1_Pos) /*!< 0x00000020 */
+#define XSPIM_CR_CSSEL_OVR_O1            XSPIM_CR_CSSEL_OVR_O1_Msk            /*!< Chip Select Selector Override Setting For XSPI1 */
+#define XSPIM_CR_CSSEL_OVR_O2_Pos        (6U)
+#define XSPIM_CR_CSSEL_OVR_O2_Msk        (0x1UL << XSPIM_CR_CSSEL_OVR_O2_Pos) /*!< 0x00000040 */
+#define XSPIM_CR_CSSEL_OVR_O2            XSPIM_CR_CSSEL_OVR_O2_Msk            /*!< Chip Select Selector Override Setting For XSPI2 */
+#define XSPIM_CR_REQ2ACK_TIME_Pos        (16U)
+#define XSPIM_CR_REQ2ACK_TIME_Msk        (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
+#define XSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK Time */
+
+/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
+
+/** @addtogroup STM32N6xx_Peripheral_Exported_macros
+  * @{
+  */
+#if defined (CPU_IN_SECURE_STATE)
+/* Instances allowed from Secure state */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_S) || ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_S) || ((INSTANCE) == ADC12_COMMON_NS))
+
+/****************************** BSEC Instances *******************************/
+#define IS_BSEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == BSEC_S)
+
+/******************************* CACHEAXI Instances ***************************/
+#define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CACHEAXI_S) || ((INSTANCE) == CACHEAXI_NS))
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_S) || ((INSTANCE) == CRC_NS))
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMI_S) || ((INSTANCE) == DCMI_NS))
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMIPP_S) || ((INSTANCE) == DCMIPP_NS))
+
+/********************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_S) || ((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_S) || ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S)  || ((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_S)  || ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_S)  || ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_S)  || ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA2D_S) || ((INSTANCE) == DMA2D_NS))
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DTS_S) || ((INSTANCE) == DTS_NS))
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ETH1_S) || ((INSTANCE) == ETH1_NS))
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_S) || ((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_S) || ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_S) || ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN_CONFIG_S) || ((INSTANCE) == FDCAN_CONFIG_NS))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_S)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_S) || ((INSTANCE) == GFXMMU_NS))
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXTIM_S) || ((INSTANCE) == GFXTIM_NS))
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_S) || ((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_S) || ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_S) || ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_S) || ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_S) || ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_S) || ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_S) || ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_S) || ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_S) || ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_S) || ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_S) || ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_S) || ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPU2D_BASE_S) || ((INSTANCE) == GPU2D_BASE_NS))
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_S) || ((INSTANCE) == I3C1_NS) || \
+                                       ((INSTANCE) == I3C2_S) || ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_S) || ((INSTANCE) == IWDG_NS))
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == JPEG_S) || ((INSTANCE) == JPEG_NS))
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LTDC_S) || ((INSTANCE) == LTDC_NS))
+
+/******************************* MCE Instances *******************************/
+#define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_S) || ((INSTANCE) == MCE1_NS) || \
+                                       ((INSTANCE) == MCE2_S) || ((INSTANCE) == MCE2_NS) || \
+                                       ((INSTANCE) == MCE3_S) || ((INSTANCE) == MCE3_NS) || \
+                                       ((INSTANCE) == MCE4_S) || ((INSTANCE) == MCE4_NS))
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_S) || ((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_S) || ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_S) || ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_S) || ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_S) || ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_S) || ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_S) || ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDIOS_S) || ((INSTANCE) == MDIOS_NS))
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_S) || ((INSTANCE) == PKA_NS))
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PSSI_S) || ((INSTANCE) == PSSI_NS))
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM1_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_S)  || ((INSTANCE) == RAMCFG_SRAM2_AHB_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM1_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_S)  || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS)  || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_S)    || ((INSTANCE) == RAMCFG_BKPSRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)    || ((INSTANCE) == RAMCFG_FLEXRAM_NS)    || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_S)   || ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_S)  || ((INSTANCE) == RAMCFG_BKPSRAM_NS)  || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_S)  || ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_S) || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_S) || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_S) || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_S) || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_S) || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_S) || ((INSTANCE) == RNG_NS))
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_S) || ((INSTANCE) == RTC_NS))
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_S) || ((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_S) || ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_S) || ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_S) || ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_S) || ((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_S) || ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPDIFRX_S) || ((INSTANCE) == SPDIFRX_NS))
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_S) || ((INSTANCE) == UCPD1_NS))
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_S) || ((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_S) || ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                        ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_S)   || ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_S)   || ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_S)   || ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_S)   || ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_S)   || ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S)  || ((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_S)  || ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_S)  || ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_S)  || ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS) || \
+                                         ((INSTANCE) == TIM18_S)  || ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                               ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                               ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                               ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)   || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS) || \
+                                         ((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS) || \
+                                         ((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS) || \
+                                         ((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS) || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM6_S)   || ((INSTANCE) == TIM6_NS)  || \
+                                         ((INSTANCE) == TIM7_S)   || ((INSTANCE) == TIM7_NS)  || \
+                                         ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                         ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                         ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)   || ((INSTANCE) == TIM1_NS)  || \
+                                          ((INSTANCE) == TIM2_S)   || ((INSTANCE) == TIM2_NS)  || \
+                                          ((INSTANCE) == TIM3_S)   || ((INSTANCE) == TIM3_NS)  || \
+                                          ((INSTANCE) == TIM4_S)   || ((INSTANCE) == TIM4_NS)  || \
+                                          ((INSTANCE) == TIM5_S)   || ((INSTANCE) == TIM5_NS)  || \
+                                          ((INSTANCE) == TIM8_S)   || ((INSTANCE) == TIM8_NS)  || \
+                                          ((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS) || \
+                                          ((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS) || \
+                                          ((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_5) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_6)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM10_S)  || ((INSTANCE) == TIM10_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM11_S)  || ((INSTANCE) == TIM11_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM12_S)  || ((INSTANCE) == TIM12_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM13_S)  || ((INSTANCE) == TIM13_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM14_S)  || ((INSTANCE) == TIM14_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     (((INSTANCE) == TIM15_S)   &&                               \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)                  \
+    (((((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))  &&   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_2) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_3) ||                            \
+      ((CHANNEL) == TIM_CHANNEL_4)))                             \
+     ||                                                          \
+     ((((INSTANCE) == TIM15_S)  || ((INSTANCE) == TIM15_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM16_S)  || ((INSTANCE) == TIM16_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1))                               \
+     ||                                                          \
+     ((((INSTANCE) == TIM17_S)  || ((INSTANCE) == TIM17_NS))  && \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                        ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                        ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                        ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                        ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                        ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                                      ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                                      ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                                      ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                                      ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                                      ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_S)  || ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_S)  || ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS) || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS) || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS) || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_S)  || ((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_S)  || ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_S)  || ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_S)  || ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_S)  || ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_S)  || ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_S)  || ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
+                                            ((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_S) || ((INSTANCE) == WWDG_NS))
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_S) || ((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_S) || ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_S) || ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPIM_S) || ((INSTANCE) == XSPIM_NS))
+
+#else
+/* Instances allowed from Non-Secure state - only alias Non-Secure */
+
+/******************************* ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
+                                       ((INSTANCE) == ADC2_NS))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)
+
+/******************************* CACHEAXI Instances ***************************/
+#define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CACHEAXI_NS)
+
+/******************************* CRC Instances *******************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS)
+
+/******************************* DCMI Instances ******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI_NS)
+
+/******************************* DCMIPP Instances ****************************/
+#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP_NS)
+
+/******************************* DLYB Instances ****************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \
+                                        ((INSTANCE) == DLYB_SDMMC2_NS))
+
+/******************************** DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                       ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_GPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == GPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == GPDMA1_Channel15_NS))
+
+#define IS_HPDMA_INSTANCE(INSTANCE)  (((INSTANCE) == HPDMA1_Channel0_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel1_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel2_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel3_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel4_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel5_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel6_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel7_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel8_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel9_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel10_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel11_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                      ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel12_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel14_NS) || \
+                                                 ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_NS) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel14_NS) || ((INSTANCE) == HPDMA1_Channel15_NS))
+
+#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == GPDMA1_Channel15_NS) || \
+                                         ((INSTANCE) == HPDMA1_Channel0_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel1_NS)  || \
+                                         ((INSTANCE) == HPDMA1_Channel15_NS))
+
+/******************************* DMA2D Instances *****************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D_NS)
+
+/******************************* DTS Instances *****************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS_NS)
+
+/******************************* ETH Instances *******************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH1_NS)
+
+/******************************* FDCAN Instances *****************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || \
+                                         ((INSTANCE) == FDCAN2_NS) || \
+                                         ((INSTANCE) == FDCAN3_NS))
+
+#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_NS)
+
+/******************************* GFXMMU Instance *****************************/
+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU_NS)
+
+/******************************* GFXTIM Instance *****************************/
+#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXTIM_NS)
+
+/********************************* GPIO Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
+                                        ((INSTANCE) == GPIOB_NS) || \
+                                        ((INSTANCE) == GPIOC_NS) || \
+                                        ((INSTANCE) == GPIOD_NS) || \
+                                        ((INSTANCE) == GPIOE_NS) || \
+                                        ((INSTANCE) == GPIOF_NS) || \
+                                        ((INSTANCE) == GPIOG_NS) || \
+                                        ((INSTANCE) == GPIOH_NS) || \
+                                        ((INSTANCE) == GPION_NS) || \
+                                        ((INSTANCE) == GPIOO_NS) || \
+                                        ((INSTANCE) == GPIOP_NS) || \
+                                        ((INSTANCE) == GPIOQ_NS))
+
+/******************************* GPIO AF Instances ***************************/
+/* All GPIO Banks support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances ****************************/
+/* All GPIO Banks support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************* GPU2D Instances *****************************/
+#define IS_GPU2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPU2D_BASE_NS)
+
+/******************************** I2C Instances ******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                       ((INSTANCE) == I2C2_NS) || \
+                                       ((INSTANCE) == I2C3_NS) || \
+                                       ((INSTANCE) == I2C4_NS))
+
+/****************** I2C Instances : wakeup capability from stop modes ********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I3C Instances *******************************/
+#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
+                                      ((INSTANCE) == I3C2_NS))
+
+/****************************** IWDG Instances *******************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS)
+
+/******************************* JPEG Instances ******************************/
+#define IS_JPEG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == JPEG_NS)
+
+/****************************** LTDC Instances *******************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC_NS)
+
+/******************************* MCE Instances *******************************/
+#define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_NS) || \
+                                       ((INSTANCE) == MCE2_NS) || \
+                                       ((INSTANCE) == MCE3_NS) || \
+                                       ((INSTANCE) == MCE4_NS))
+
+/******************************* MDF/ADF Instances ***************************/
+#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || \
+                                       ((INSTANCE) == MDF1_Filter1_NS) || \
+                                       ((INSTANCE) == MDF1_Filter2_NS) || \
+                                       ((INSTANCE) == MDF1_Filter3_NS) || \
+                                       ((INSTANCE) == MDF1_Filter4_NS) || \
+                                       ((INSTANCE) == MDF1_Filter5_NS) || \
+                                       ((INSTANCE) == ADF1_Filter0_NS))
+
+/****************************** MDIOS Instances ******************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS_NS)
+
+/******************************* PKA Instances *******************************/
+#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)
+
+/******************************* PSSI Instances ******************************/
+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI_NS)
+
+/****************************** RAMCFG Instances ********************************/
+#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AHB_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM1_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_SRAM6_AXI_NS) || \
+                                          ((INSTANCE) == RAMCFG_BKPSRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS)   || \
+                                          ((INSTANCE) == RAMCFG_VENC_RAM_NS))
+
+/***************************** RAMCFG ECC Instances *****************************/
+#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
+                                          ((INSTANCE) == RAMCFG_FLEXRAM_NS))
+
+/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
+#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
+                                                        ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
+
+/******************************* RNG Instances *******************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS)
+
+/******************************* RTC Instances *******************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS)
+
+/******************************** SAI Instances ******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || \
+                                       ((INSTANCE) == SAI1_Block_B_NS) || \
+                                       ((INSTANCE) == SAI2_Block_A_NS) || \
+                                       ((INSTANCE) == SAI2_Block_B_NS))
+
+/******************************* SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || \
+                                         ((INSTANCE) == SDMMC2_NS))
+
+/******************************** SMBUS Instances ****************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
+                                         ((INSTANCE) == I2C2_NS) || \
+                                         ((INSTANCE) == I2C3_NS) || \
+                                         ((INSTANCE) == I2C4_NS))
+
+/****************************** SPDIFRX Instances ****************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX_NS)
+
+/******************************** SPI Instances ******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI4_NS) || \
+                                       ((INSTANCE) == SPI5_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                        ((INSTANCE) == SPI2_NS) || \
+                                        ((INSTANCE) == SPI3_NS) || \
+                                        ((INSTANCE) == SPI6_NS))
+
+#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || \
+                                           ((INSTANCE) == SPI5_NS))
+
+/******************************** I2S Instances ******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
+                                       ((INSTANCE) == SPI2_NS) || \
+                                       ((INSTANCE) == SPI3_NS) || \
+                                       ((INSTANCE) == SPI6_NS))
+
+/****************************** UCPD Instances *******************************/
+#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_NS)
+
+/******************************* OTG HS HCD Instances *************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* OTG HS PCD Instances *************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_NS) || \
+                                       ((INSTANCE) == USB2_OTG_HS_NS))
+
+/******************************* USB HS PHY Instances *************************/
+#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_NS) || \
+                                           ((INSTANCE) == USB2_HS_PHYC_NS))
+
+/******************** USART Instances : Synchronous mode *********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                     ((INSTANCE) == USART2_NS) || \
+                                     ((INSTANCE) == USART3_NS) || \
+                                     ((INSTANCE) == USART6_NS) || \
+                                     ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Asynchronous mode *********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                    ((INSTANCE) == USART2_NS) || \
+                                    ((INSTANCE) == USART3_NS) || \
+                                    ((INSTANCE) == UART4_NS)  || \
+                                    ((INSTANCE) == UART5_NS)  || \
+                                    ((INSTANCE) == USART6_NS) || \
+                                    ((INSTANCE) == UART7_NS)  || \
+                                    ((INSTANCE) == UART8_NS)  || \
+                                    ((INSTANCE) == UART9_NS)  || \
+                                    ((INSTANCE) == USART10_NS))
+
+/*********************** UART Instances : FIFO mode **************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == UART4_NS)   || \
+                                         ((INSTANCE) == UART5_NS)   || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == UART7_NS)   || \
+                                         ((INSTANCE) == UART8_NS)   || \
+                                         ((INSTANCE) == UART9_NS)   || \
+                                         ((INSTANCE) == USART10_NS) || \
+                                         ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : SPI Slave mode **********************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                              ((INSTANCE) == USART2_NS)  || \
+                                              ((INSTANCE) == USART3_NS)  || \
+                                              ((INSTANCE) == USART6_NS)  || \
+                                              ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                            ((INSTANCE) == USART2_NS)  || \
+                                                            ((INSTANCE) == USART3_NS)  || \
+                                                            ((INSTANCE) == UART4_NS)   || \
+                                                            ((INSTANCE) == UART5_NS)   || \
+                                                            ((INSTANCE) == USART6_NS)  || \
+                                                            ((INSTANCE) == UART7_NS)   || \
+                                                            ((INSTANCE) == UART8_NS)   || \
+                                                            ((INSTANCE) == UART9_NS)   || \
+                                                            ((INSTANCE) == USART10_NS))
+
+/****************** UART Instances : Driver Enable ***************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                  ((INSTANCE) == USART2_NS)  || \
+                                                  ((INSTANCE) == USART3_NS)  || \
+                                                  ((INSTANCE) == UART4_NS)   || \
+                                                  ((INSTANCE) == UART5_NS)   || \
+                                                  ((INSTANCE) == USART6_NS)  || \
+                                                  ((INSTANCE) == UART7_NS)   || \
+                                                  ((INSTANCE) == UART8_NS)   || \
+                                                  ((INSTANCE) == UART9_NS)   || \
+                                                  ((INSTANCE) == USART10_NS) || \
+                                                  ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                               ((INSTANCE) == USART2_NS)  || \
+                                               ((INSTANCE) == USART3_NS)  || \
+                                               ((INSTANCE) == UART4_NS)   || \
+                                               ((INSTANCE) == UART5_NS)   || \
+                                               ((INSTANCE) == USART6_NS)  || \
+                                               ((INSTANCE) == UART7_NS)   || \
+                                               ((INSTANCE) == UART8_NS)   || \
+                                               ((INSTANCE) == UART9_NS)   || \
+                                               ((INSTANCE) == USART10_NS) || \
+                                               ((INSTANCE) == LPUART1_NS))
+
+/****************** UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                           ((INSTANCE) == USART2_NS)  || \
+                                           ((INSTANCE) == USART3_NS)  || \
+                                           ((INSTANCE) == UART4_NS)   || \
+                                           ((INSTANCE) == UART5_NS)   || \
+                                           ((INSTANCE) == USART6_NS)  || \
+                                           ((INSTANCE) == UART7_NS)   || \
+                                           ((INSTANCE) == UART8_NS)   || \
+                                           ((INSTANCE) == UART9_NS)   || \
+                                           ((INSTANCE) == USART10_NS) || \
+                                           ((INSTANCE) == LPUART1_NS))
+
+/******************** UART Instances : LIN mode ******************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
+                                        ((INSTANCE) == USART2_NS)  || \
+                                        ((INSTANCE) == USART3_NS)  || \
+                                        ((INSTANCE) == UART4_NS)   || \
+                                        ((INSTANCE) == UART5_NS)   || \
+                                        ((INSTANCE) == USART6_NS)  || \
+                                        ((INSTANCE) == UART7_NS)   || \
+                                        ((INSTANCE) == UART8_NS)   || \
+                                        ((INSTANCE) == UART9_NS)   || \
+                                        ((INSTANCE) == USART10_NS))
+
+/******************** UART Instances : Wake-up from Stop mode ****************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                                    ((INSTANCE) == USART2_NS)  || \
+                                                    ((INSTANCE) == USART3_NS)  || \
+                                                    ((INSTANCE) == UART4_NS)   || \
+                                                    ((INSTANCE) == UART5_NS)   || \
+                                                    ((INSTANCE) == USART6_NS)  || \
+                                                    ((INSTANCE) == UART7_NS)   || \
+                                                    ((INSTANCE) == UART8_NS)   || \
+                                                    ((INSTANCE) == UART9_NS)   || \
+                                                    ((INSTANCE) == USART10_NS) || \
+                                                    ((INSTANCE) == LPUART1_NS))
+
+/*********************** UART Instances : IRDA mode **************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                    ((INSTANCE) == USART2_NS)  || \
+                                    ((INSTANCE) == USART3_NS)  || \
+                                    ((INSTANCE) == UART4_NS)   || \
+                                    ((INSTANCE) == UART5_NS)   || \
+                                    ((INSTANCE) == USART6_NS)  || \
+                                    ((INSTANCE) == UART7_NS)   || \
+                                    ((INSTANCE) == UART8_NS)   || \
+                                    ((INSTANCE) == UART9_NS)   || \
+                                    ((INSTANCE) == USART10_NS))
+
+/********************* USART Instances : Smard card mode *********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
+                                         ((INSTANCE) == USART2_NS)  || \
+                                         ((INSTANCE) == USART3_NS)  || \
+                                         ((INSTANCE) == USART6_NS)  || \
+                                         ((INSTANCE) == USART10_NS))
+
+/******************** LPUART Instance ****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/****************** LPTIM Instances : DMA supported instances *****************/
+#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/************* LPTIM Instances : at least 1 capture/compare channel ***********/
+#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS) || \
+                                         ((INSTANCE) == LPTIM4_NS) || \
+                                         ((INSTANCE) == LPTIM5_NS))
+
+/************* LPTIM Instances : at least 2 capture/compare channel ***********/
+#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                         ((INSTANCE) == LPTIM2_NS) || \
+                                         ((INSTANCE) == LPTIM3_NS))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                       ((INSTANCE) == LPTIM2_NS) || \
+                                                       ((INSTANCE) == LPTIM3_NS))
+
+
+/****************** LPTIM Instances : supporting Input Capture **************/
+#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
+                                                   ((INSTANCE) == LPTIM2_NS) || \
+                                                   ((INSTANCE) == LPTIM3_NS))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || \
+                                               ((INSTANCE) == TIM3_NS)  || \
+                                               ((INSTANCE) == TIM4_NS)  || \
+                                               ((INSTANCE) == TIM5_NS))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                               ((INSTANCE) == TIM8_NS)  || \
+                                               ((INSTANCE) == TIM15_NS) || \
+                                               ((INSTANCE) == TIM16_NS) || \
+                                               ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM9_NS)   || \
+                                         ((INSTANCE) == TIM10_NS)  || \
+                                         ((INSTANCE) == TIM11_NS)  || \
+                                         ((INSTANCE) == TIM12_NS)  || \
+                                         ((INSTANCE) == TIM13_NS)  || \
+                                         ((INSTANCE) == TIM14_NS)  || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS)  || \
+                                         ((INSTANCE) == TIM9_NS)  || \
+                                         ((INSTANCE) == TIM12_NS) || \
+                                         ((INSTANCE) == TIM15_NS))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM2_NS)  || \
+                                         ((INSTANCE) == TIM3_NS)  || \
+                                         ((INSTANCE) == TIM4_NS)  || \
+                                         ((INSTANCE) == TIM5_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                         ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)   || \
+                                         ((INSTANCE) == TIM2_NS)   || \
+                                         ((INSTANCE) == TIM3_NS)   || \
+                                         ((INSTANCE) == TIM4_NS)   || \
+                                         ((INSTANCE) == TIM5_NS)   || \
+                                         ((INSTANCE) == TIM6_NS)   || \
+                                         ((INSTANCE) == TIM7_NS)   || \
+                                         ((INSTANCE) == TIM8_NS)   || \
+                                         ((INSTANCE) == TIM15_NS)  || \
+                                         ((INSTANCE) == TIM16_NS)  || \
+                                         ((INSTANCE) == TIM17_NS)  || \
+                                         ((INSTANCE) == TIM18_NS))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || \
+                                          ((INSTANCE) == TIM2_NS)   || \
+                                          ((INSTANCE) == TIM3_NS)   || \
+                                          ((INSTANCE) == TIM4_NS)   || \
+                                          ((INSTANCE) == TIM5_NS)   || \
+                                          ((INSTANCE) == TIM8_NS)   || \
+                                          ((INSTANCE) == TIM15_NS)  || \
+                                          ((INSTANCE) == TIM16_NS)  || \
+                                          ((INSTANCE) == TIM17_NS))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8_NS)    &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM9_NS)   &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM10_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM11_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM12_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM13_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM14_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17_NS)   &&             \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM8_NS)    &&              \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3) ||           \
+      ((CHANNEL) == TIM_CHANNEL_4)))            \
+     ||                                         \
+     (((INSTANCE) == TIM15_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM16_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+     ||                                         \
+     (((INSTANCE) == TIM17_NS)   &&              \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                                    ((INSTANCE) == TIM2_NS)  || \
+                                                    ((INSTANCE) == TIM3_NS)  || \
+                                                    ((INSTANCE) == TIM4_NS)  || \
+                                                    ((INSTANCE) == TIM5_NS)  || \
+                                                    ((INSTANCE) == TIM8_NS)  || \
+                                                    ((INSTANCE) == TIM9_NS)  || \
+                                                    ((INSTANCE) == TIM12_NS) || \
+                                                    ((INSTANCE) == TIM15_NS) || \
+                                                    ((INSTANCE) == TIM16_NS) || \
+                                                    ((INSTANCE) == TIM17_NS))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS)  || \
+                                                        ((INSTANCE) == TIM9_NS)  || \
+                                                        ((INSTANCE) == TIM12_NS) || \
+                                                        ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                     ((INSTANCE) == TIM8_NS)  || \
+                                                     ((INSTANCE) == TIM15_NS) || \
+                                                     ((INSTANCE) == TIM16_NS) || \
+                                                     ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                        ((INSTANCE) == TIM2_NS)  || \
+                                                        ((INSTANCE) == TIM3_NS)  || \
+                                                        ((INSTANCE) == TIM4_NS)  || \
+                                                        ((INSTANCE) == TIM5_NS)  || \
+                                                        ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                      ((INSTANCE) == TIM2_NS)  || \
+                                                      ((INSTANCE) == TIM3_NS)  || \
+                                                      ((INSTANCE) == TIM4_NS)  || \
+                                                      ((INSTANCE) == TIM5_NS)  || \
+                                                      ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                         ((INSTANCE) == TIM2_NS)  || \
+                                                         ((INSTANCE) == TIM3_NS)  || \
+                                                         ((INSTANCE) == TIM4_NS)  || \
+                                                         ((INSTANCE) == TIM5_NS)  || \
+                                                         ((INSTANCE) == TIM8_NS)  || \
+                                                         ((INSTANCE) == TIM9_NS)  || \
+                                                         ((INSTANCE) == TIM12_NS) || \
+                                                         ((INSTANCE) == TIM15_NS))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                             ((INSTANCE) == TIM2_NS)  || \
+                                             ((INSTANCE) == TIM3_NS)  || \
+                                             ((INSTANCE) == TIM4_NS)  || \
+                                             ((INSTANCE) == TIM5_NS)  || \
+                                             ((INSTANCE) == TIM8_NS))
+
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM6_NS)  || \
+                                            ((INSTANCE) == TIM7_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                                ((INSTANCE) == TIM2_NS)  || \
+                                                ((INSTANCE) == TIM3_NS)  || \
+                                                ((INSTANCE) == TIM4_NS)  || \
+                                                ((INSTANCE) == TIM5_NS)  || \
+                                                ((INSTANCE) == TIM8_NS)  || \
+                                                ((INSTANCE) == TIM15_NS) || \
+                                                ((INSTANCE) == TIM16_NS) || \
+                                                ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
+                                                       ((INSTANCE) == TIM8_NS)  || \
+                                                       ((INSTANCE) == TIM15_NS) || \
+                                                       ((INSTANCE) == TIM16_NS) || \
+                                                       ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM4_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM8_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM15_NS))
+
+/******************* TIM Instances : Timer input selection ********************/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2_NS)  || \
+                                            ((INSTANCE) == TIM3_NS)  || \
+                                            ((INSTANCE) == TIM5_NS)  || \
+                                            ((INSTANCE) == TIM9_NS)  || \
+                                            ((INSTANCE) == TIM10_NS) || \
+                                            ((INSTANCE) == TIM11_NS) || \
+                                            ((INSTANCE) == TIM12_NS) || \
+                                            ((INSTANCE) == TIM13_NS) || \
+                                            ((INSTANCE) == TIM14_NS) || \
+                                            ((INSTANCE) == TIM15_NS) || \
+                                            ((INSTANCE) == TIM16_NS) || \
+                                            ((INSTANCE) == TIM17_NS))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
+                                            ((INSTANCE) == TIM8_NS))
+
+/****************************** WWDG Instances *******************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS)
+
+/******************************** XSPI Instances *****************************/
+#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_NS) || \
+                                        ((INSTANCE) == XSPI2_NS) || \
+                                        ((INSTANCE) == XSPI3_NS))
+
+/****************************** XSPIM Instances ***************************/
+#define IS_XSPIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == XSPIM_NS)
+
+#endif
+
+/** @} */ /* End of group STM32N6xx_Peripheral_Exported_macros */
+
+/** @} */ /* End of group STM32N657xx */
+
+/** @} */ /* End of group ST */
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* STM32N657xx_H */
diff --git a/stm32cube/stm32n6xx/soc/stm32n6xx.h b/stm32cube/stm32n6xx/soc/stm32n6xx.h
new file mode 100644
index 000000000..a46ad37e2
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/stm32n6xx.h
@@ -0,0 +1,222 @@
+/**
+  ******************************************************************************
+  * @file    stm32n6xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32N6xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32N6xx device used in the target application
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32N6xx
+  * @{
+  */
+
+#ifndef STM32N6xx_H
+#define STM32N6xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32N6)
+#define STM32N6
+#endif /* STM32N6 */
+
+/* Uncomment the line below according to the target STM32N6 device used in your
+   application
+  */
+
+#if !defined (STM32N647xx) && !defined (STM32N657xx)
+  /* #define STM32N647xx */   /*!< STM32N647xx Devices */
+  /* #define STM32N657xx */   /*!< STM32N657xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32N6_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32N6_CMSIS_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
+#define __STM32N6_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32N6_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32N6_CMSIS_VERSION        ((__STM32N6_CMSIS_VERSION_MAIN << 24U)\
+                                       |(__STM32N6_CMSIS_VERSION_SUB1 << 16U)\
+                                       |(__STM32N6_CMSIS_VERSION_SUB2 << 8U )\
+                                       |(__STM32N6_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32N657xx)
+  #include "stm32n657xx.h"
+#elif defined(STM32N655xx)
+  #include "stm32n655xx.h"
+#elif defined(STM32N647xx)
+  #include "stm32n647xx.h"
+#elif defined(STM32N645xx)
+  #include "stm32n645xx.h"
+#else
+ #error "Please select first the target STM32N6xx device used in your application (in stm32n6xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32n6xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32N6xx_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/soc/system_stm32n6xx.h b/stm32cube/stm32n6xx/soc/system_stm32n6xx.h
new file mode 100644
index 000000000..900b86a42
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/system_stm32n6xx.h
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32n6xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M55 Device System Source File for STM32N6xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32N6xx_system
+  * @{
+  */
+
+#ifndef SYSTEM_STM32N6XX_H
+#define SYSTEM_STM32N6XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup STM32N6xx_System_Includes
+  * @{
+  */
+#include <stdint.h>
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;        /*!< System Clock Frequency (Core Clock)  */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Exported_Functions
+  * @{
+  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable from secure application and return its value
+          when security is implemented in the system (Non-secure callable function).
+
+   Returns the SystemCoreClock value with current core Clock retrieved from cpu registers.
+ */
+extern uint32_t SECURE_SystemCoreClockUpdate(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SYSTEM_STM32N6XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/stm32cube/stm32n6xx/soc/system_stm32n6xx_fsbl.c b/stm32cube/stm32n6xx/soc/system_stm32n6xx_fsbl.c
new file mode 100644
index 000000000..0d9c6bd39
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/system_stm32n6xx_fsbl.c
@@ -0,0 +1,502 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32n6xx_fsbl.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M55 Device Peripheral Access Layer System Source File
+  *          to be used after the boot ROM execution in an applicative code called
+  *          "FSBL" for First Stage Boot Loader.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at secure startup just after the
+  *                      boot ROM execution and before branch to secure main program.
+  *                      This call is made inside the "startup_stm32n6xx_fsbl.s" file.
+  *                      This function does not manage security isolation (IDAU/SAU,
+  *                      interrupts, ...) unless USER_TZ_SAU_SETUP is defined at
+  *                      project level.
+  *
+  *      - SystemCoreClock variable: Contains the CPU core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the HSI (64 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32n6xx_fsbl.s" file, to
+  *   configure the system before to branch to main program.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32N6xx_System
+  * @{
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32n6xx.h"
+#if defined(USER_TZ_SAU_SETUP)
+#include "partition_stm32n6xx.h"  /* Trustzone-M core secure attributes */
+#endif /* USER_TZ_SAU_SETUP */
+#include <math.h>
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+#if defined ( __ICCARM__ )
+#  define CMSE_NS_ENTRY __cmse_nonsecure_entry
+#else
+#  define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#if defined(USE_FPGA)
+#define HSE_VALUE      30000000UL /*!< Value of the High-Speed External oscillator in Hz */
+#else
+#define HSE_VALUE      48000000UL /*!< Value of the High-Speed External oscillator in Hz */
+#endif /* USE_FPGA */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#if defined(USE_FPGA)
+  #define HSI_VALUE      48000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
+#else
+  #define HSI_VALUE      64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
+#endif /* USE_FPGA */
+#endif /* HSI_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE       4000000UL /*!< Minimum value of the Low-power Internal oscillator in Hz */
+#endif /* MSI_VALUE */
+
+#if !defined  (EXTERNAL_I2S_CLOCK_VALUE)
+  #define EXTERNAL_I2S_CLOCK_VALUE  12288000UL /*!< Value of the External clock for I2S_CKIN in Hz */
+#endif /* EXTERNAL_I2S_CLOCK_VALUE */
+
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in memory, else the vector table is kept at the automatic
+     selected boot address */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if !defined(VECT_TAB_BASE_ADDRESS)
+#define VECT_TAB_BASE_ADDRESS   SRAM1_AXI_BASE_S /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x400. */
+#endif
+
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x400. */
+#endif
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = HSI_VALUE;
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Functions
+  * @{
+  */
+
+#if defined(__ICCARM__)
+extern uint32_t __vector_table;
+#define INTVECT_START ((uint32_t)&__vector_table)
+#elif defined(__ARMCC_VERSION)
+extern void *__Vectors;
+#define INTVECT_START ((uint32_t)&__Vectors)
+#elif defined(__GNUC__)
+extern void *g_pfnVectors;
+#define INTVECT_START ((uint32_t)&g_pfnVectors)
+#endif
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#else
+  SCB->VTOR = INTVECT_START;
+#endif  /* USER_VECT_TAB_ADDRESS */
+
+  /* RNG reset */
+  RCC->AHB3RSTSR = RCC_AHB3RSTSR_RNGRSTS;
+  RCC->AHB3RSTCR = RCC_AHB3RSTCR_RNGRSTC;
+  /* Deactivate RNG clock */
+  RCC->AHB3ENCR = RCC_AHB3ENCR_RNGENC;
+
+  /* Clear SAU regions */
+  SAU->RNR = 0;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+  SAU->RNR = 1;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+  SAU->RNR = 2;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+  SAU->RNR = 3;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+  SAU->RNR = 4;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+  SAU->RNR = 5;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+  SAU->RNR = 6;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+  SAU->RNR = 7;
+  SAU->RBAR = 0;
+  SAU->RLAR = 0;
+
+  /* System configuration setup */
+  RCC->APB4ENSR2 = RCC_APB4ENSR2_SYSCFGENS;
+  /* Delay after an RCC peripheral clock enabling */
+  (void)RCC->APB4ENR2;
+
+  /* Set default Vector Table location after system reset or return from Standby */
+  SYSCFG->INITSVTORCR = SCB->VTOR;
+
+  /* Enable VDDADC CLAMP */
+  PWR->SVMCR3 |= PWR_SVMCR3_ASV;
+  PWR->SVMCR3 |= PWR_SVMCR3_AVMEN;
+  /* read back the register to make sure that the transaction has taken place */
+  (void) PWR->SVMCR3;
+  /* enable VREF */
+  RCC->APB4ENR1 |= RCC_APB4ENR1_VREFBUFEN;
+
+  /* RCC Fix to lower power consumption */
+  RCC->APB4ENR2 |= 0x00000010UL;
+  (void) RCC->APB4ENR2;
+  RCC->APB4ENR2 &= ~(0x00000010UL);
+
+  /* XSPI2 & XSPIM reset                                  */
+  RCC->AHB5RSTSR = RCC_AHB5RSTSR_XSPIMRSTS | RCC_AHB5RSTSR_XSPI2RSTS;
+  RCC->AHB5RSTCR = RCC_AHB5RSTCR_XSPIMRSTC | RCC_AHB5RSTCR_XSPI2RSTC;
+
+  /* TIM2 reset */
+  RCC->APB1RSTSR1 = RCC_APB1RSTSR1_TIM2RSTS;
+  RCC->APB1RSTCR1 = RCC_APB1RSTCR1_TIM2RSTC;
+  /* Deactivate TIM2 clock */
+  RCC->APB1ENCR1 = RCC_APB1ENCR1_TIM2ENC;
+
+  /* Deactivate GPIOG clock */
+  RCC->AHB4ENCR = RCC_AHB4ENCR_GPIOGENC;
+
+  /* Read back the value to make sure it is written before deactivating SYSCFG */
+  (void) SYSCFG->INITSVTORCR;
+  /* Deactivate SYSCFG clock */
+  RCC->APB4ENCR2 = RCC_APB4ENCR2_SYSCFGENC;
+
+#if defined(USER_TZ_SAU_SETUP)
+  /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
+  TZ_SAU_Setup();
+#endif /* USER_TZ_SAU_SETUP */
+
+  /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+
+  SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+#endif /* __FPU_PRESENT && __FPU_USED */
+
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the CPU core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If CPUCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If CPUCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(**)
+  *
+  *           - If CPUCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If CPUCLK source is IC1, SystemCoreClock will contain the HSI_VALUE(*)
+  *             or MSI_VALUE(**) or HSE_VALUE(***) or EXTERNAL_I2S_CLOCK_VALUE (****)
+  *             multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE default value is 64 MHz.
+  *             With the HAL, HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file
+  *             but the real value may vary depending on the variations in voltage and temperature.
+  *
+  *        (**) MSI_VALUE default value is 4 MHz.
+  *             With the HAL, MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file
+  *             but the real value may vary depending on the variations in voltage and temperature.
+  *
+  *       (***) HSE_VALUE default value is 30 MHz.
+  *             With the HAL, HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file.
+  *             User has to ensure that HSE_VALUE is same as the real frequency of the crystal used.
+  *             Otherwise, this function may have wrong result.
+  *
+  *      (****) EXTERNAL_I2S_CLOCK_VALUE default value is 12.288 MHz.
+  *             With the HAL, EXTERNAL_I2S_CLOCK_VALUE is a constant defined in stm32n6xx_hal_conf.h file.
+  *             User has to ensure that EXTERNAL_I2S_CLOCK_VALUE is same as the real I2S_CKIN
+  *             pin frequency. Otherwise, this function may have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t sysclk = 0;
+  uint32_t pllm = 0;
+  uint32_t plln = 0;
+  uint32_t pllfracn = 0;
+  uint32_t pllp1 = 0;
+  uint32_t pllp2 = 0;
+  uint32_t pllcfgr, pllsource, pllbypass, ic_divider;
+  float_t pllvco;
+
+  /* Get CPUCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR1 & RCC_CFGR1_CPUSWS)
+  {
+  case 0:  /* HSI used as system clock source (default after reset) */
+    sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos);
+    break;
+
+  case RCC_CFGR1_CPUSWS_0:  /* MSI used as system clock source */
+    if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL)
+    {
+      sysclk = MSI_VALUE;
+    }
+    else
+    {
+      sysclk = 16000000UL;
+    }
+    break;
+
+  case RCC_CFGR1_CPUSWS_1:  /* HSE used as system clock source */
+    sysclk = HSE_VALUE;
+    break;
+
+  case (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0):  /* IC1 used as system clock  source */
+    /* Get IC1 clock source parameters */
+    switch (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL))
+    {
+    case 0:  /* PLL1 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL1CFGR1);
+      pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL;
+      pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >>  RCC_PLL1CFGR1_PLL1DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >>  RCC_PLL1CFGR1_PLL1DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >>  RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL1CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >>  RCC_PLL1CFGR3_PLL1PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >>  RCC_PLL1CFGR3_PLL1PDIV2_Pos;
+      }
+      break;
+    case RCC_IC1CFGR_IC1SEL_0:  /* PLL2 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL2CFGR1);
+      pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL;
+      pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >>  RCC_PLL2CFGR1_PLL2DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >>  RCC_PLL2CFGR1_PLL2DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >>  RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL2CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >>  RCC_PLL2CFGR3_PLL2PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >>  RCC_PLL2CFGR3_PLL2PDIV2_Pos;
+      }
+      break;
+
+    case RCC_IC1CFGR_IC1SEL_1:  /* PLL3 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL3CFGR1);
+      pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL;
+      pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >>  RCC_PLL3CFGR1_PLL3DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >>  RCC_PLL3CFGR1_PLL3DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >>  RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL3CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >>  RCC_PLL3CFGR3_PLL3PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >>  RCC_PLL3CFGR3_PLL3PDIV2_Pos;
+      }
+      break;
+
+    default: /* RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0 */  /* PLL4 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL4CFGR1);
+      pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL;
+      pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >>  RCC_PLL4CFGR1_PLL4DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >>  RCC_PLL4CFGR1_PLL4DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >>  RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL4CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >>  RCC_PLL4CFGR3_PLL4PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >>  RCC_PLL4CFGR3_PLL4PDIV2_Pos;
+      }
+      break;
+    }
+
+#if defined(USE_FPGA)
+    /********** FPGA SPECIFIC *************/
+    /* FPGA PLL implementation use 32MHz as fixed PLL input frequency */
+    (void)pllsource;
+    sysclk = 32000000UL;
+    pllbypass = 0U;
+#else
+    /* Get oscillator frequency used as PLL clock source */
+    switch (pllsource)
+    {
+    case 0:  /* HSI selected as PLL clock source */
+      sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos);
+      break;
+    case RCC_PLL1CFGR1_PLL1SEL_0: /* MSI selected as PLL clock source */
+      if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL)
+      {
+        sysclk = MSI_VALUE;
+      }
+      else
+      {
+        sysclk = 16000000UL;
+      }
+      break;
+    case RCC_PLL1CFGR1_PLL1SEL_1: /* HSE selected as PLL clock source */
+      sysclk = HSE_VALUE;
+      break;
+    case (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0):  /* I2S_CKIN selected as PLL clock source */
+      sysclk = EXTERNAL_I2S_CLOCK_VALUE;
+      break;
+    default:
+      /* Nothing to do, should not occur */
+      break;
+    }
+#endif /* USE_FPGA */
+    /* Check whether PLL is in bypass mode or not */
+    if (pllbypass == 0U)
+    {
+      /* Compte PLL output frequency (Integer and fractional modes) */
+      /* PLLVCO = (Freq * (DIVN + (FRACN / 0x1000000) / DIVM) / (DIVP1 * DIVP2)) */
+      pllvco = ((float_t)sysclk * ((float_t)plln + ((float_t)pllfracn/(float_t)0x1000000UL))) / (float_t)pllm;
+      sysclk = (uint32_t)((float_t)(pllvco/(((float_t)pllp1) * ((float_t)pllp2))));
+    }
+    /* Apply IC1 divider */
+    ic_divider = (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL;
+    sysclk = sysclk / ic_divider;
+    break;
+  default:
+    /* Nothing to do, should not occur */
+    break;
+  }
+
+  /* Return system clock frequency (CPU frequency) */
+  SystemCoreClock = sysclk;
+}
+
+/**
+  * @brief  Secure Non-Secure-Callable function to return the current
+  *         SystemCoreClock value after SystemCoreClock update.
+  *         The SystemCoreClock variable contains the CPU core clock, it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  * @retval SystemCoreClock value
+  */
+uint32_t SECURE_SystemCoreClockUpdate(void)
+{
+  SystemCoreClockUpdate();
+
+  return SystemCoreClock;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/soc/system_stm32n6xx_ns.c b/stm32cube/stm32n6xx/soc/system_stm32n6xx_ns.c
new file mode 100644
index 000000000..13f13d3c9
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/system_stm32n6xx_ns.c
@@ -0,0 +1,250 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32n6xx_ns.c
+  * @author  GPM Application Team
+  * @brief   CMSIS Cortex-M55 Device Peripheral Access Layer System Source File
+  *          to be used in non-secure application when the system implements
+  *          the TrustZone-M security.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at non-secure startup before
+  *                      branch to non-secure main program.
+  *                      This call is made inside the "startup_stm32n6xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the CPU core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the HSI (64 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32n6xx.s" file, to
+  *   configure the system before to branch to main secure program.
+  *   Later, when non-secure SystemInit() function is called, in "startup_stm32n6xx.s"
+  *   file, the system clock may have been updated from reset value by the main
+  *   secure program.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32N6xx_System
+  * @{
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32n6xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE      48000000UL /*!< Value of the High-Speed External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE      64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE       4000000UL /*!< Minimum value of the Low-power Internal oscillator in Hz */
+#endif /* MSI_VALUE */
+
+#if !defined  (EXTERNAL_I2S_CLOCK_VALUE)
+  #define EXTERNAL_I2S_CLOCK_VALUE  12288000UL /*!< Value of the External clock for I2S_CKIN in Hz */
+#endif /* EXTERNAL_I2S_CLOCK_VALUE */
+
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in memory, else the vector table is kept at the automatic
+     selected boot address */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if !defined(VECT_TAB_BASE_ADDRESS)
+#define VECT_TAB_BASE_ADDRESS   SRAM2_AXI_BASE_NS /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x400. */
+#endif
+
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x400. */
+#endif
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = HSI_VALUE;
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Functions
+  * @{
+  */
+
+#if defined(__ICCARM__)
+extern uint32_t __vector_table;
+#define INTVECT_START ((uint32_t)&__vector_table)
+#elif defined(__ARMCC_VERSION)
+extern void *__Vectors;
+#define INTVECT_START ((uint32_t)&__Vectors)
+#elif defined(__GNUC__)
+extern void *g_pfnVectors;
+#define INTVECT_START ((uint32_t)&g_pfnVectors)
+#endif
+/**
+  * @brief  Setup the microcontroller system.
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* Vector table location and FPU setup done by secure application */
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#else
+  SCB->VTOR = INTVECT_START;
+#endif  /* USER_VECT_TAB_ADDRESS */
+
+  /* Non-secure main application shall call SystemCoreClockUpdate() to update */
+  /* the SystemCoreClock variable to insure non-secure application relies on  */
+  /* the initial clock reference set by secure application.                   */
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   From the non-secure application, the SystemCoreClock value is
+  *         retrieved from the secure domain via a Non-Secure Callable function
+  *         since the RCC peripheral may be protected with security attributes
+  *         that prevent to compute the SystemCoreClock variable from the RCC
+  *         peripheral registers.
+  *
+  * @note   Each time the CPU core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If CPUCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If CPUCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(**)
+  *
+  *           - If CPUCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If CPUCLK source is IC1, SystemCoreClock will contain the HSI_VALUE(*)
+  *             or MSI_VALUE(**) or HSE_VALUE(***) or EXTERNAL_I2S_CLOCK_VALUE (****)
+  *             multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE default value is 64 MHz.
+  *             With the HAL, HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file
+  *             but the real value may vary depending on the variations in voltage and temperature.
+  *
+  *        (**) MSI_VALUE default value is 4 MHz.
+  *             With the HAL, MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file
+  *             but the real value may vary depending on the variations in voltage and temperature.
+  *
+  *       (***) HSE_VALUE default value is 30 MHz.
+  *             With the HAL, HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file.
+  *             User has to ensure that HSE_VALUE is same as the real frequency of the crystal used.
+  *             Otherwise, this function may have wrong result.
+  *
+  *      (****) EXTERNAL_I2S_CLOCK_VALUE default value is 12.288 MHz.
+  *             With the HAL, EXTERNAL_I2S_CLOCK_VALUE is a constant defined in stm32n6xx_hal_conf.h file.
+  *             User has to ensure that EXTERNAL_I2S_CLOCK_VALUE is same as the real I2S_CKIN
+  *             pin frequency. Otherwise, this function may have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  /* Get the SystemCoreClock value from the secure domain */
+  SystemCoreClock = SECURE_SystemCoreClockUpdate();
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/stm32cube/stm32n6xx/soc/system_stm32n6xx_s.c b/stm32cube/stm32n6xx/soc/system_stm32n6xx_s.c
new file mode 100644
index 000000000..47b1365f4
--- /dev/null
+++ b/stm32cube/stm32n6xx/soc/system_stm32n6xx_s.c
@@ -0,0 +1,445 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32n6xx_s.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M55 Device Peripheral Access Layer System Source File
+  *          to be used in secure application.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at secure startup just after reset
+  *                      and before branch to secure main program.
+  *                      This call is made inside the "startup_stm32n6xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the CPU core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *      - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
+  *                                        the variable SystemCoreClock and return
+  *                                        its value to the non-secure calling
+  *                                        application. It must be called whenever
+  *                                        the core clock is changed during program
+  *                                        execution.
+  *
+  *   After each device reset the HSI (64 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32n6xx.s" file, to
+  *   configure the system before to branch to main program.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32N6xx_System
+  * @{
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32n6xx.h"
+#include "partition_stm32n6xx.h"  /* Trustzone-M core secure attributes */
+#include <math.h>
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+#if defined ( __ICCARM__ )
+#  define CMSE_NS_ENTRY __cmse_nonsecure_entry
+#else
+#  define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#if defined(USE_FPGA)
+#define HSE_VALUE      30000000UL /*!< Value of the High-Speed External oscillator in Hz */
+#else
+#define HSE_VALUE      48000000UL /*!< Value of the High-Speed External oscillator in Hz */
+#endif /* USE_FPGA */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#if defined(USE_FPGA)
+  #define HSI_VALUE      48000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
+#else
+  #define HSI_VALUE      64000000UL /*!< Value of the High-Speed Internal oscillator in Hz */
+#endif /* USE_FPGA */
+#endif /* HSI_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE       4000000UL /*!< Minimum value of the Low-power Internal oscillator in Hz */
+#endif /* MSI_VALUE */
+
+#if !defined  (EXTERNAL_I2S_CLOCK_VALUE)
+  #define EXTERNAL_I2S_CLOCK_VALUE  12288000UL /*!< Value of the External clock for I2S_CKIN in Hz */
+#endif /* EXTERNAL_I2S_CLOCK_VALUE */
+
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in memory, else the vector table is kept at the automatic
+     selected boot address */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if !defined(VECT_TAB_BASE_ADDRESS)
+#define VECT_TAB_BASE_ADDRESS   SRAM1_AXI_BASE_S /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x400. */
+#endif
+
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x400. */
+#endif
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = HSI_VALUE;
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32N6xx_System_Private_Functions
+  * @{
+  */
+
+#if defined(__ICCARM__)
+extern uint32_t __vector_table;
+#define INTVECT_START ((uint32_t)&__vector_table)
+#elif defined(__ARMCC_VERSION)
+extern void *__Vectors;
+#define INTVECT_START ((uint32_t)&__Vectors)
+#elif defined(__GNUC__)
+extern void *g_pfnVectors;
+#define INTVECT_START ((uint32_t)&g_pfnVectors)
+#endif
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
+  TZ_SAU_Setup();
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#else
+  SCB->VTOR = INTVECT_START;
+#endif  /* USER_VECT_TAB_ADDRESS */
+
+  /* System configuration setup */
+  RCC->APB4ENSR2 = RCC_APB4ENSR2_SYSCFGENS;
+  /* Delay after an RCC peripheral clock enabling */
+  (void)RCC->APB4ENR2;
+
+  /* Set default Vector Table location after system reset or return from Standby */
+  SYSCFG->INITSVTORCR = SCB->VTOR;
+  /* Read back the value to make sure it is written before deactivating SYSCFG */
+  (void) SYSCFG->INITSVTORCR;
+  /* Deactivate SYSCFG clock */
+  RCC->APB4ENCR2 = RCC_APB4ENCR2_SYSCFGENC;
+  /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+
+  SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+#endif /* __FPU_PRESENT && __FPU_USED */
+
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Depending on secure or non-secure compilation, the adequate RCC peripheral
+  *         memory are is accessed thanks to RCC alias defined in stm32n6xxxx.h device file
+  *         so either from RCC_S peripheral register mapped memory in secure or from
+  *         RCC_NS peripheral register mapped memory in non-secure.
+  *
+  * @note   Each time the CPU core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If CPUCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If CPUCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(**)
+  *
+  *           - If CPUCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If CPUCLK source is IC1, SystemCoreClock will contain the HSI_VALUE(*)
+  *             or MSI_VALUE(**) or HSE_VALUE(***) or EXTERNAL_I2S_CLOCK_VALUE (****)
+  *             multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE default value is 64 MHz.
+  *             With the HAL, HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file
+  *             but the real value may vary depending on the variations in voltage and temperature.
+  *
+  *        (**) MSI_VALUE default value is 4 MHz.
+  *             With the HAL, MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file
+  *             but the real value may vary depending on the variations in voltage and temperature.
+  *
+  *       (***) HSE_VALUE default value is 30 MHz.
+  *             With the HAL, HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file.
+  *             User has to ensure that HSE_VALUE is same as the real frequency of the crystal used.
+  *             Otherwise, this function may have wrong result.
+  *
+  *      (****) EXTERNAL_I2S_CLOCK_VALUE default value is 12.288 MHz.
+  *             With the HAL, EXTERNAL_I2S_CLOCK_VALUE is a constant defined in stm32n6xx_hal_conf.h file.
+  *             User has to ensure that EXTERNAL_I2S_CLOCK_VALUE is same as the real I2S_CKIN
+  *             pin frequency. Otherwise, this function may have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t sysclk = 0;
+  uint32_t pllm = 0;
+  uint32_t plln = 0;
+  uint32_t pllfracn = 0;
+  uint32_t pllp1 = 0;
+  uint32_t pllp2 = 0;
+  uint32_t pllcfgr, pllsource, pllbypass, ic_divider;
+  float_t pllvco;
+
+  /* Get CPUCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR1 & RCC_CFGR1_CPUSWS)
+  {
+  case 0:  /* HSI used as system clock source (default after reset) */
+    sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos);
+    break;
+
+  case RCC_CFGR1_CPUSWS_0:  /* MSI used as system clock source */
+    if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL)
+    {
+      sysclk = MSI_VALUE;
+    }
+    else
+    {
+      sysclk = 16000000UL;
+    }
+    break;
+
+  case RCC_CFGR1_CPUSWS_1:  /* HSE used as system clock source */
+    sysclk = HSE_VALUE;
+    break;
+
+  case (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0):  /* IC1 used as system clock  source */
+    /* Get IC1 clock source parameters */
+    switch (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL))
+    {
+    case 0:  /* PLL1 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL1CFGR1);
+      pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL;
+      pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >>  RCC_PLL1CFGR1_PLL1DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >>  RCC_PLL1CFGR1_PLL1DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >>  RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL1CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >>  RCC_PLL1CFGR3_PLL1PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >>  RCC_PLL1CFGR3_PLL1PDIV2_Pos;
+      }
+      break;
+    case RCC_IC1CFGR_IC1SEL_0:  /* PLL2 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL2CFGR1);
+      pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL;
+      pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >>  RCC_PLL2CFGR1_PLL2DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >>  RCC_PLL2CFGR1_PLL2DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >>  RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL2CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >>  RCC_PLL2CFGR3_PLL2PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >>  RCC_PLL2CFGR3_PLL2PDIV2_Pos;
+      }
+      break;
+
+    case RCC_IC1CFGR_IC1SEL_1:  /* PLL3 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL3CFGR1);
+      pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL;
+      pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >>  RCC_PLL3CFGR1_PLL3DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >>  RCC_PLL3CFGR1_PLL3DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >>  RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL3CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >>  RCC_PLL3CFGR3_PLL3PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >>  RCC_PLL3CFGR3_PLL3PDIV2_Pos;
+      }
+      break;
+
+    default: /* RCC_IC1CFGR_IC1SEL_1 | RCC_IC1CFGR_IC1SEL_0 */  /* PLL4 selected at IC1 clock source */
+      pllcfgr = READ_REG(RCC->PLL4CFGR1);
+      pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL;
+      pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP;
+      if (pllbypass == 0U)
+      {
+        pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >>  RCC_PLL4CFGR1_PLL4DIVM_Pos;
+        plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >>  RCC_PLL4CFGR1_PLL4DIVN_Pos;
+        pllfracn = READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >>  RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos;
+        pllcfgr = READ_REG(RCC->PLL4CFGR3);
+        pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >>  RCC_PLL4CFGR3_PLL4PDIV1_Pos;
+        pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >>  RCC_PLL4CFGR3_PLL4PDIV2_Pos;
+      }
+      break;
+    }
+
+#if defined(USE_FPGA)
+    /********** FPGA SPECIFIC *************/
+    /* FPGA PLL implementation use 32MHz as fixed PLL input frequency */
+    (void)pllsource;
+    sysclk = 32000000UL;
+    pllbypass = 0U;
+#else
+    /* Get oscillator frequency used as PLL clock source */
+    switch (pllsource)
+    {
+    case 0:  /* HSI selected as PLL clock source */
+      sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos);
+      break;
+    case RCC_PLL1CFGR1_PLL1SEL_0: /* MSI selected as PLL clock source */
+      if (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL)
+      {
+        sysclk = MSI_VALUE;
+      }
+      else
+      {
+        sysclk = 16000000UL;
+      }
+      break;
+    case RCC_PLL1CFGR1_PLL1SEL_1: /* HSE selected as PLL clock source */
+      sysclk = HSE_VALUE;
+      break;
+    case (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0):  /* I2S_CKIN selected as PLL clock source */
+      sysclk = EXTERNAL_I2S_CLOCK_VALUE;
+      break;
+    default:
+      /* Nothing to do, should not occur */
+      break;
+    }
+#endif /* USE_FPGA */
+    /* Check whether PLL is in bypass mode or not */
+    if (pllbypass == 0U)
+    {
+      /* Compte PLL output frequency (Integer and fractional modes) */
+      /* PLLVCO = (Freq * (DIVN + (FRACN / 0x1000000) / DIVM) / (DIVP1 * DIVP2)) */
+      pllvco = ((float_t)sysclk * ((float_t)plln + ((float_t)pllfracn/(float_t)0x1000000UL))) / (float_t)pllm;
+      sysclk = (uint32_t)((float_t)(pllvco/(((float_t)pllp1) * ((float_t)pllp2))));
+    }
+    /* Apply IC1 divider */
+    ic_divider = (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL;
+    sysclk = sysclk / ic_divider;
+    break;
+  default:
+    /* Nothing to do, should not occur */
+    break;
+  }
+
+  /* Return system clock frequency (CPU frequency) */
+  SystemCoreClock = sysclk;
+}
+
+/**
+  * @brief  Secure Non-Secure-Callable function to return the current
+  *         SystemCoreClock value after SystemCoreClock update.
+  *         The SystemCoreClock variable contains the CPU core clock, it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  * @retval SystemCoreClock value
+  */
+CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
+{
+  SystemCoreClockUpdate();
+
+  return SystemCoreClock;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */